Refresh Valgrind to 3.8.1
Disable Android.mk for now until Android-specific changes are submitted later.
Change-Id: I0673f9b4edbbfacf5f52868c9735272e4bf811de
diff --git a/Android.mk b/Android.mk
index 5053e7d..e69de29 100644
--- a/Android.mk
+++ b/Android.mk
@@ -1 +0,0 @@
-include $(call all-subdir-makefiles)
diff --git a/main/Android.mk b/main/Android.mk
index 844a0e6..ef26cd5 100644
--- a/main/Android.mk
+++ b/main/Android.mk
@@ -65,6 +65,8 @@
VEX/priv/ir_opt.c \
VEX/priv/guest_generic_bb_to_IR.c \
VEX/priv/guest_generic_x87.c \
+ VEX/priv/guest_mips_helpers.c \
+ VEX/priv/guest_mips_toIR.c \
VEX/priv/guest_x86_helpers.c \
VEX/priv/guest_x86_toIR.c \
VEX/priv/guest_amd64_helpers.c \
@@ -83,6 +85,8 @@
VEX/priv/host_x86_isel.c \
VEX/priv/host_amd64_defs.c \
VEX/priv/host_amd64_isel.c \
+ VEX/priv/host_mips_defs.c \
+ VEX/priv/host_mips_isel.c \
VEX/priv/host_ppc_defs.c \
VEX/priv/host_ppc_isel.c \
VEX/priv/host_arm_defs.c \
@@ -110,7 +114,6 @@
LOCAL_ARM_MODE := arm
LOCAL_SRC_FILES := \
- coregrind/link_tool_exe.c \
coregrind/m_commandline.c \
coregrind/m_clientstate.c \
coregrind/m_cpuid.S \
@@ -131,6 +134,7 @@
coregrind/m_mallocfree.c \
coregrind/m_options.c \
coregrind/m_oset.c \
+ coregrind/m_poolalloc.c \
coregrind/m_redir.c \
coregrind/m_seqmatch.c \
coregrind/m_signals.c \
@@ -148,8 +152,6 @@
coregrind/m_wordfm.c \
coregrind/m_xarray.c \
coregrind/m_aspacehl.c \
- coregrind/m_start-amd64-darwin.S \
- coregrind/m_start-x86-darwin.S \
coregrind/m_aspacemgr/aspacemgr-common.c \
coregrind/m_aspacemgr/aspacemgr-linux.c \
coregrind/m_coredump/coredump-elf.c \
@@ -184,8 +186,11 @@
coregrind/m_mach/mach_traps-x86-darwin.S \
coregrind/m_mach/mach_traps-amd64-darwin.S \
coregrind/m_replacemalloc/replacemalloc_core.c \
+ coregrind/m_scheduler/sched-lock.c \
+ coregrind/m_scheduler/sched-lock-generic.c \
coregrind/m_scheduler/scheduler.c \
coregrind/m_scheduler/sema.c \
+ coregrind/m_scheduler/ticket-lock-linux.c \
coregrind/m_sigframe/sigframe-x86-linux.c \
coregrind/m_sigframe/sigframe-amd64-linux.c \
coregrind/m_sigframe/sigframe-ppc32-linux.c \
@@ -219,7 +224,7 @@
coregrind/m_ume/macho.c \
coregrind/m_ume/main.c \
coregrind/m_ume/script.c \
- coregrind/vgdb.c \
+ coregrind/vgdb.c \
coregrind/m_gdbserver/inferiors.c \
coregrind/m_gdbserver/m_gdbserver.c \
coregrind/m_gdbserver/regcache.c \
@@ -230,7 +235,6 @@
coregrind/m_gdbserver/utils.c \
coregrind/m_gdbserver/valgrind-low-amd64.c \
coregrind/m_gdbserver/valgrind-low-arm.c \
- coregrind/m_gdbserver/valgrind-low.c \
coregrind/m_gdbserver/valgrind-low-ppc32.c \
coregrind/m_gdbserver/valgrind-low-ppc64.c \
coregrind/m_gdbserver/valgrind-low-s390x.c \
@@ -391,7 +395,6 @@
callgrind/bbcc.c \
callgrind/callstack.c \
callgrind/clo.c \
- callgrind/command.c \
callgrind/context.c \
callgrind/costs.c \
callgrind/debug.c \
@@ -489,7 +492,6 @@
LOCAL_SRC_FILES := \
drd/drd_barrier.c \
- drd/drd_bitmap2_node.c \
drd/drd_clientobj.c \
drd/drd_clientreq.c \
drd/drd_cond.c \
diff --git a/main/VEX/priv/guest_amd64_defs.h b/main/VEX/priv/guest_amd64_defs.h
index 7d3ed34..396bd6d 100644
--- a/main/VEX/priv/guest_amd64_defs.h
+++ b/main/VEX/priv/guest_amd64_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -47,7 +47,6 @@
bb_to_IR.h. */
extern
DisResult disInstr_AMD64 ( IRSB* irbb,
- Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -118,9 +117,13 @@
extern ULong amd64g_create_mxcsr ( ULong sseround );
-extern VexEmWarn amd64g_dirtyhelper_FLDENV ( VexGuestAMD64State*, HWord );
+extern VexEmWarn amd64g_dirtyhelper_FLDENV ( VexGuestAMD64State*, HWord );
+extern VexEmWarn amd64g_dirtyhelper_FRSTOR ( VexGuestAMD64State*, HWord );
+extern VexEmWarn amd64g_dirtyhelper_FRSTORS ( VexGuestAMD64State*, HWord );
-extern void amd64g_dirtyhelper_FSTENV ( VexGuestAMD64State*, HWord );
+extern void amd64g_dirtyhelper_FSTENV ( VexGuestAMD64State*, HWord );
+extern void amd64g_dirtyhelper_FNSAVE ( VexGuestAMD64State*, HWord );
+extern void amd64g_dirtyhelper_FNSAVES ( VexGuestAMD64State*, HWord );
/* Translate a guest virtual_addr into a guest linear address by
consulting the supplied LDT/GDT structures. Their representation
@@ -137,11 +140,17 @@
extern ULong amd64g_calculate_mmx_pmovmskb ( ULong );
extern ULong amd64g_calculate_sse_pmovmskb ( ULong w64hi, ULong w64lo );
+extern ULong amd64g_calculate_sse_phminposuw ( ULong sLo, ULong sHi );
+
extern ULong amd64g_calc_crc32b ( ULong crcIn, ULong b );
extern ULong amd64g_calc_crc32w ( ULong crcIn, ULong w );
extern ULong amd64g_calc_crc32l ( ULong crcIn, ULong l );
extern ULong amd64g_calc_crc32q ( ULong crcIn, ULong q );
+extern ULong amd64g_calc_mpsadbw ( ULong sHi, ULong sLo,
+ ULong dHi, ULong dLo,
+ ULong imm_and_return_control_bit );
+
/* --- DIRTY HELPERS --- */
extern ULong amd64g_dirtyhelper_loadF80le ( ULong/*addr*/ );
@@ -151,6 +160,7 @@
extern void amd64g_dirtyhelper_CPUID_baseline ( VexGuestAMD64State* st );
extern void amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st );
extern void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st );
+extern void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st );
extern void amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* );
@@ -211,6 +221,55 @@
HWord edxIN, HWord eaxIN
);
+/* Implementation of intel AES instructions as described in
+ Intel Advanced Vector Extensions
+ Programming Reference
+ MARCH 2008
+ 319433-002.
+
+ CALLED FROM GENERATED CODE: DIRTY HELPER(s). (But not really,
+ actually it could be a clean helper, but for the fact that we can't
+ pass by value 2 x V128 to a clean helper, nor have one returned.)
+ Reads guest state, writes to guest state, no
+ accesses of memory, is a pure function.
+
+ opc4 contains the 4th byte of opcode. Front-end should only
+ give opcode corresponding to AESENC/AESENCLAST/AESDEC/AESDECLAST/AESIMC.
+ (will assert otherwise).
+
+ gstOffL and gstOffR are the guest state offsets for the two XMM
+ register inputs, gstOffD is the guest state offset for the XMM register
+ output. We never have to deal with the memory case since that is handled
+ by pre-loading the relevant value into the fake XMM16 register.
+
+*/
+extern void amd64g_dirtyhelper_AES (
+ VexGuestAMD64State* gst,
+ HWord opc4, HWord gstOffD,
+ HWord gstOffL, HWord gstOffR
+ );
+
+/* Implementation of AESKEYGENASSIST.
+
+ CALLED FROM GENERATED CODE: DIRTY HELPER(s). (But not really,
+ actually it could be a clean helper, but for the fact that we can't
+ pass by value 1 x V128 to a clean helper, nor have one returned.)
+ Reads guest state, writes to guest state, no
+ accesses of memory, is a pure function.
+
+ imm8 is the Round Key constant.
+
+ gstOffL and gstOffR are the guest state offsets for the two XMM
+ register input and output. We never have to deal with the memory case since
+ that is handled by pre-loading the relevant value into the fake
+ XMM16 register.
+
+*/
+extern void amd64g_dirtyhelper_AESKEYGENASSIST (
+ VexGuestAMD64State* gst,
+ HWord imm8,
+ HWord gstOffL, HWord gstOffR
+ );
//extern void amd64g_dirtyhelper_CPUID_sse0 ( VexGuestAMD64State* );
//extern void amd64g_dirtyhelper_CPUID_sse1 ( VexGuestAMD64State* );
diff --git a/main/VEX/priv/guest_amd64_helpers.c b/main/VEX/priv/guest_amd64_helpers.c
index d554918..7e67d73 100644
--- a/main/VEX/priv/guest_amd64_helpers.c
+++ b/main/VEX/priv/guest_amd64_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -954,6 +954,14 @@
return unop(Iop_1Uto64,
binop(Iop_CmpLE64U, cc_dep1, cc_dep2));
}
+ if (isU64(cc_op, AMD64G_CC_OP_SUBQ) && isU64(cond, AMD64CondNBE)) {
+ /* long long sub/cmp, then NBE (unsigned greater than)
+ --> test !(dst <=u src) */
+ return binop(Iop_Xor64,
+ unop(Iop_1Uto64,
+ binop(Iop_CmpLE64U, cc_dep1, cc_dep2)),
+ mkU64(1));
+ }
/*---------------- SUBL ----------------*/
@@ -1190,6 +1198,23 @@
mkU64(1));
}
+ /*---------------- LOGICW ----------------*/
+
+ if (isU64(cc_op, AMD64G_CC_OP_LOGICW) && isU64(cond, AMD64CondZ)) {
+ /* word and/or/xor, then Z --> test dst==0 */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64,
+ binop(Iop_And64, cc_dep1, mkU64(0xFFFF)),
+ mkU64(0)));
+ }
+ if (isU64(cc_op, AMD64G_CC_OP_LOGICW) && isU64(cond, AMD64CondNZ)) {
+ /* word and/or/xor, then NZ --> test dst!=0 */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpNE64,
+ binop(Iop_And64, cc_dep1, mkU64(0xFFFF)),
+ mkU64(0)));
+ }
+
/*---------------- LOGICB ----------------*/
if (isU64(cc_op, AMD64G_CC_OP_LOGICB) && isU64(cond, AMD64CondZ)) {
@@ -1553,7 +1578,7 @@
/* handle the control word, setting FPROUND and detecting any
emulation warnings. */
pair = amd64g_check_fldcw ( (ULong)fpucw );
- fpround = (UInt)pair;
+ fpround = (UInt)pair & 0xFFFFFFFFULL;
ew = (VexEmWarn)(pair >> 32);
vex_state->guest_FPROUND = fpround & 3;
@@ -1698,22 +1723,22 @@
_dst[2] = _src[2]; _dst[3] = _src[3]; } \
while (0)
- COPY_U128( xmm[0], gst->guest_XMM0 );
- COPY_U128( xmm[1], gst->guest_XMM1 );
- COPY_U128( xmm[2], gst->guest_XMM2 );
- COPY_U128( xmm[3], gst->guest_XMM3 );
- COPY_U128( xmm[4], gst->guest_XMM4 );
- COPY_U128( xmm[5], gst->guest_XMM5 );
- COPY_U128( xmm[6], gst->guest_XMM6 );
- COPY_U128( xmm[7], gst->guest_XMM7 );
- COPY_U128( xmm[8], gst->guest_XMM8 );
- COPY_U128( xmm[9], gst->guest_XMM9 );
- COPY_U128( xmm[10], gst->guest_XMM10 );
- COPY_U128( xmm[11], gst->guest_XMM11 );
- COPY_U128( xmm[12], gst->guest_XMM12 );
- COPY_U128( xmm[13], gst->guest_XMM13 );
- COPY_U128( xmm[14], gst->guest_XMM14 );
- COPY_U128( xmm[15], gst->guest_XMM15 );
+ COPY_U128( xmm[0], gst->guest_YMM0 );
+ COPY_U128( xmm[1], gst->guest_YMM1 );
+ COPY_U128( xmm[2], gst->guest_YMM2 );
+ COPY_U128( xmm[3], gst->guest_YMM3 );
+ COPY_U128( xmm[4], gst->guest_YMM4 );
+ COPY_U128( xmm[5], gst->guest_YMM5 );
+ COPY_U128( xmm[6], gst->guest_YMM6 );
+ COPY_U128( xmm[7], gst->guest_YMM7 );
+ COPY_U128( xmm[8], gst->guest_YMM8 );
+ COPY_U128( xmm[9], gst->guest_YMM9 );
+ COPY_U128( xmm[10], gst->guest_YMM10 );
+ COPY_U128( xmm[11], gst->guest_YMM11 );
+ COPY_U128( xmm[12], gst->guest_YMM12 );
+ COPY_U128( xmm[13], gst->guest_YMM13 );
+ COPY_U128( xmm[14], gst->guest_YMM14 );
+ COPY_U128( xmm[15], gst->guest_YMM15 );
# undef COPY_U128
}
@@ -1741,22 +1766,22 @@
_dst[2] = _src[2]; _dst[3] = _src[3]; } \
while (0)
- COPY_U128( gst->guest_XMM0, xmm[0] );
- COPY_U128( gst->guest_XMM1, xmm[1] );
- COPY_U128( gst->guest_XMM2, xmm[2] );
- COPY_U128( gst->guest_XMM3, xmm[3] );
- COPY_U128( gst->guest_XMM4, xmm[4] );
- COPY_U128( gst->guest_XMM5, xmm[5] );
- COPY_U128( gst->guest_XMM6, xmm[6] );
- COPY_U128( gst->guest_XMM7, xmm[7] );
- COPY_U128( gst->guest_XMM8, xmm[8] );
- COPY_U128( gst->guest_XMM9, xmm[9] );
- COPY_U128( gst->guest_XMM10, xmm[10] );
- COPY_U128( gst->guest_XMM11, xmm[11] );
- COPY_U128( gst->guest_XMM12, xmm[12] );
- COPY_U128( gst->guest_XMM13, xmm[13] );
- COPY_U128( gst->guest_XMM14, xmm[14] );
- COPY_U128( gst->guest_XMM15, xmm[15] );
+ COPY_U128( gst->guest_YMM0, xmm[0] );
+ COPY_U128( gst->guest_YMM1, xmm[1] );
+ COPY_U128( gst->guest_YMM2, xmm[2] );
+ COPY_U128( gst->guest_YMM3, xmm[3] );
+ COPY_U128( gst->guest_YMM4, xmm[4] );
+ COPY_U128( gst->guest_YMM5, xmm[5] );
+ COPY_U128( gst->guest_YMM6, xmm[6] );
+ COPY_U128( gst->guest_YMM7, xmm[7] );
+ COPY_U128( gst->guest_YMM8, xmm[8] );
+ COPY_U128( gst->guest_YMM9, xmm[9] );
+ COPY_U128( gst->guest_YMM10, xmm[10] );
+ COPY_U128( gst->guest_YMM11, xmm[11] );
+ COPY_U128( gst->guest_YMM12, xmm[12] );
+ COPY_U128( gst->guest_YMM13, xmm[13] );
+ COPY_U128( gst->guest_YMM14, xmm[14] );
+ COPY_U128( gst->guest_YMM15, xmm[15] );
# undef COPY_U128
@@ -1929,47 +1954,7 @@
VexEmWarn amd64g_dirtyhelper_FLDENV ( /*OUT*/VexGuestAMD64State* vex_state,
/*IN*/HWord x87_state)
{
- Int stno, preg;
- UInt tag;
- UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
- Fpu_State* x87 = (Fpu_State*)x87_state;
- UInt ftop = (x87->env[FP_ENV_STAT] >> 11) & 7;
- UInt tagw = x87->env[FP_ENV_TAG];
- UInt fpucw = x87->env[FP_ENV_CTRL];
- ULong c3210 = x87->env[FP_ENV_STAT] & 0x4700;
- VexEmWarn ew;
- ULong fpround;
- ULong pair;
-
- /* Copy tags */
- for (stno = 0; stno < 8; stno++) {
- preg = (stno + ftop) & 7;
- tag = (tagw >> (2*preg)) & 3;
- if (tag == 3) {
- /* register is empty */
- vexTags[preg] = 0;
- } else {
- /* register is non-empty */
- vexTags[preg] = 1;
- }
- }
-
- /* stack pointer */
- vex_state->guest_FTOP = ftop;
-
- /* status word */
- vex_state->guest_FC3210 = c3210;
-
- /* handle the control word, setting FPROUND and detecting any
- emulation warnings. */
- pair = amd64g_check_fldcw ( (ULong)fpucw );
- fpround = pair & 0xFFFFFFFFULL;
- ew = (VexEmWarn)(pair >> 32);
-
- vex_state->guest_FPROUND = fpround & 3;
-
- /* emulation warnings --> caller */
- return ew;
+ return do_put_x87( False, (UChar*)x87_state, vex_state );
}
@@ -2014,6 +1999,130 @@
}
+/* This is used to implement 'fnsave'.
+ Writes 108 bytes at x87_state[0 .. 107]. */
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER */
+void amd64g_dirtyhelper_FNSAVE ( /*IN*/VexGuestAMD64State* vex_state,
+ /*OUT*/HWord x87_state)
+{
+ do_get_x87( vex_state, (UChar*)x87_state );
+}
+
+
+/* This is used to implement 'fnsaves'.
+ Writes 94 bytes at x87_state[0 .. 93]. */
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER */
+void amd64g_dirtyhelper_FNSAVES ( /*IN*/VexGuestAMD64State* vex_state,
+ /*OUT*/HWord x87_state)
+{
+ Int i, stno, preg;
+ UInt tagw;
+ ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
+ UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
+ Fpu_State_16* x87 = (Fpu_State_16*)x87_state;
+ UInt ftop = vex_state->guest_FTOP;
+ UInt c3210 = vex_state->guest_FC3210;
+
+ for (i = 0; i < 7; i++)
+ x87->env[i] = 0;
+
+ x87->env[FPS_ENV_STAT]
+ = toUShort(((ftop & 7) << 11) | (c3210 & 0x4700));
+ x87->env[FPS_ENV_CTRL]
+ = toUShort(amd64g_create_fpucw( vex_state->guest_FPROUND ));
+
+ /* Dump the register stack in ST order. */
+ tagw = 0;
+ for (stno = 0; stno < 8; stno++) {
+ preg = (stno + ftop) & 7;
+ if (vexTags[preg] == 0) {
+ /* register is empty */
+ tagw |= (3 << (2*preg));
+ convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
+ &x87->reg[10*stno] );
+ } else {
+ /* register is full. */
+ tagw |= (0 << (2*preg));
+ convert_f64le_to_f80le( (UChar*)&vexRegs[preg],
+ &x87->reg[10*stno] );
+ }
+ }
+ x87->env[FPS_ENV_TAG] = toUShort(tagw);
+}
+
+
+/* This is used to implement 'frstor'.
+ Reads 108 bytes at x87_state[0 .. 107]. */
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER */
+VexEmWarn amd64g_dirtyhelper_FRSTOR ( /*OUT*/VexGuestAMD64State* vex_state,
+ /*IN*/HWord x87_state)
+{
+ return do_put_x87( True, (UChar*)x87_state, vex_state );
+}
+
+
+/* This is used to implement 'frstors'.
+ Reads 94 bytes at x87_state[0 .. 93]. */
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER */
+VexEmWarn amd64g_dirtyhelper_FRSTORS ( /*OUT*/VexGuestAMD64State* vex_state,
+ /*IN*/HWord x87_state)
+{
+ Int stno, preg;
+ UInt tag;
+ ULong* vexRegs = (ULong*)(&vex_state->guest_FPREG[0]);
+ UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
+ Fpu_State_16* x87 = (Fpu_State_16*)x87_state;
+ UInt ftop = (x87->env[FPS_ENV_STAT] >> 11) & 7;
+ UInt tagw = x87->env[FPS_ENV_TAG];
+ UInt fpucw = x87->env[FPS_ENV_CTRL];
+ UInt c3210 = x87->env[FPS_ENV_STAT] & 0x4700;
+ VexEmWarn ew;
+ UInt fpround;
+ ULong pair;
+
+ /* Copy registers and tags */
+ for (stno = 0; stno < 8; stno++) {
+ preg = (stno + ftop) & 7;
+ tag = (tagw >> (2*preg)) & 3;
+ if (tag == 3) {
+ /* register is empty */
+ /* hmm, if it's empty, does it still get written? Probably
+ safer to say it does. If we don't, memcheck could get out
+ of sync, in that it thinks all FP registers are defined by
+ this helper, but in reality some have not been updated. */
+ vexRegs[preg] = 0; /* IEEE754 64-bit zero */
+ vexTags[preg] = 0;
+ } else {
+ /* register is non-empty */
+ convert_f80le_to_f64le( &x87->reg[10*stno],
+ (UChar*)&vexRegs[preg] );
+ vexTags[preg] = 1;
+ }
+ }
+
+ /* stack pointer */
+ vex_state->guest_FTOP = ftop;
+
+ /* status word */
+ vex_state->guest_FC3210 = c3210;
+
+ /* handle the control word, setting FPROUND and detecting any
+ emulation warnings. */
+ pair = amd64g_check_fldcw ( (ULong)fpucw );
+ fpround = (UInt)pair & 0xFFFFFFFFULL;
+ ew = (VexEmWarn)(pair >> 32);
+
+ vex_state->guest_FPROUND = fpround & 3;
+
+ /* emulation warnings --> caller */
+ return ew;
+}
+
+
/*---------------------------------------------------------------*/
/*--- Misc integer helpers, including rotates and CPUID. ---*/
/*---------------------------------------------------------------*/
@@ -2041,7 +2150,11 @@
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
- power management: ts fid vid ttp
+ power management: ts fid vid ttp
+
+ 2012-Feb-21: don't claim 3dnow or 3dnowext, since in fact
+ we don't support them. See #291568. 3dnow is 80000001.EDX.31
+ and 3dnowext is 80000001.EDX.30.
*/
void amd64g_dirtyhelper_CPUID_baseline ( VexGuestAMD64State* st )
{
@@ -2063,7 +2176,11 @@
SET_ABCD(0x80000018, 0x68747541, 0x444d4163, 0x69746e65);
break;
case 0x80000001:
- SET_ABCD(0x00000f5a, 0x00000505, 0x00000000, 0xe1d3fbff);
+ /* Don't claim to support 3dnow or 3dnowext. 0xe1d3fbff is
+ the original it-is-supported value that the h/w provides.
+ See #291568. */
+ SET_ABCD(0x00000f5a, 0x00000505, 0x00000000, /*0xe1d3fbff*/
+ 0x21d3fbff);
break;
case 0x80000002:
SET_ABCD(0x20444d41, 0x6574704f, 0x206e6f72, 0x296d7428);
@@ -2239,7 +2356,6 @@
dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16
xtpr pdcm sse4_1 sse4_2 popcnt aes lahf_lm ida
arat tpr_shadow vnmi flexpriority ept vpid
- MINUS aes (see below)
bogomips : 6957.57
clflush size : 64
cache_alignment : 64
@@ -2263,10 +2379,7 @@
SET_ABCD(0x0000000b, 0x756e6547, 0x6c65746e, 0x49656e69);
break;
case 0x00000001:
- // & ~(1<<25): don't claim to support AES insns. See
- // bug 249991.
- SET_ABCD(0x00020652, 0x00100800, 0x0298e3ff & ~(1<<25),
- 0xbfebfbff);
+ SET_ABCD(0x00020652, 0x00100800, 0x0298e3ff, 0xbfebfbff);
break;
case 0x00000002:
SET_ABCD(0x55035a01, 0x00f0b2e3, 0x00000000, 0x09ca212c);
@@ -2367,6 +2480,168 @@
}
+/* Claim to be the following CPU (4 x ...), which is AVX and cx16
+ capable.
+
+ vendor_id : GenuineIntel
+ cpu family : 6
+ model : 42
+ model name : Intel(R) Core(TM) i5-2300 CPU @ 2.80GHz
+ stepping : 7
+ cpu MHz : 1600.000
+ cache size : 6144 KB
+ physical id : 0
+ siblings : 4
+ core id : 3
+ cpu cores : 4
+ apicid : 6
+ initial apicid : 6
+ fpu : yes
+ fpu_exception : yes
+ cpuid level : 13
+ wp : yes
+ flags : fpu vme de pse tsc msr pae mce cx8 apic sep
+ mtrr pge mca cmov pat pse36 clflush dts acpi
+ mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp
+ lm constant_tsc arch_perfmon pebs bts rep_good
+ nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq
+ dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16
+ xtpr pdcm sse4_1 sse4_2 popcnt aes xsave avx
+ lahf_lm ida arat epb xsaveopt pln pts dts
+ tpr_shadow vnmi flexpriority ept vpid
+
+ bogomips : 5768.94
+ clflush size : 64
+ cache_alignment : 64
+ address sizes : 36 bits physical, 48 bits virtual
+ power management:
+*/
+void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st )
+{
+# define SET_ABCD(_a,_b,_c,_d) \
+ do { st->guest_RAX = (ULong)(_a); \
+ st->guest_RBX = (ULong)(_b); \
+ st->guest_RCX = (ULong)(_c); \
+ st->guest_RDX = (ULong)(_d); \
+ } while (0)
+
+ UInt old_eax = (UInt)st->guest_RAX;
+ UInt old_ecx = (UInt)st->guest_RCX;
+
+ switch (old_eax) {
+ case 0x00000000:
+ SET_ABCD(0x0000000d, 0x756e6547, 0x6c65746e, 0x49656e69);
+ break;
+ case 0x00000001:
+ SET_ABCD(0x000206a7, 0x00100800, 0x1f9ae3bf, 0xbfebfbff);
+ break;
+ case 0x00000002:
+ SET_ABCD(0x76035a01, 0x00f0b0ff, 0x00000000, 0x00ca0000);
+ break;
+ case 0x00000003:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x00000004:
+ switch (old_ecx) {
+ case 0x00000000: SET_ABCD(0x1c004121, 0x01c0003f,
+ 0x0000003f, 0x00000000); break;
+ case 0x00000001: SET_ABCD(0x1c004122, 0x01c0003f,
+ 0x0000003f, 0x00000000); break;
+ case 0x00000002: SET_ABCD(0x1c004143, 0x01c0003f,
+ 0x000001ff, 0x00000000); break;
+ case 0x00000003: SET_ABCD(0x1c03c163, 0x02c0003f,
+ 0x00001fff, 0x00000006); break;
+ default: SET_ABCD(0x00000000, 0x00000000,
+ 0x00000000, 0x00000000); break;
+ }
+ break;
+ case 0x00000005:
+ SET_ABCD(0x00000040, 0x00000040, 0x00000003, 0x00001120);
+ break;
+ case 0x00000006:
+ SET_ABCD(0x00000077, 0x00000002, 0x00000009, 0x00000000);
+ break;
+ case 0x00000007:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x00000008:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x00000009:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x0000000a:
+ SET_ABCD(0x07300803, 0x00000000, 0x00000000, 0x00000603);
+ break;
+ case 0x0000000b:
+ switch (old_ecx) {
+ case 0x00000000:
+ SET_ABCD(0x00000001, 0x00000001,
+ 0x00000100, 0x00000000); break;
+ case 0x00000001:
+ SET_ABCD(0x00000004, 0x00000004,
+ 0x00000201, 0x00000000); break;
+ default:
+ SET_ABCD(0x00000000, 0x00000000,
+ old_ecx, 0x00000000); break;
+ }
+ break;
+ case 0x0000000c:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x0000000d:
+ switch (old_ecx) {
+ case 0x00000000: SET_ABCD(0x00000007, 0x00000340,
+ 0x00000340, 0x00000000); break;
+ case 0x00000001: SET_ABCD(0x00000001, 0x00000000,
+ 0x00000000, 0x00000000); break;
+ case 0x00000002: SET_ABCD(0x00000100, 0x00000240,
+ 0x00000000, 0x00000000); break;
+ default: SET_ABCD(0x00000000, 0x00000000,
+ 0x00000000, 0x00000000); break;
+ }
+ break;
+ case 0x0000000e:
+ SET_ABCD(0x00000007, 0x00000340, 0x00000340, 0x00000000);
+ break;
+ case 0x0000000f:
+ SET_ABCD(0x00000007, 0x00000340, 0x00000340, 0x00000000);
+ break;
+ case 0x80000000:
+ SET_ABCD(0x80000008, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000001:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000001, 0x28100800);
+ break;
+ case 0x80000002:
+ SET_ABCD(0x20202020, 0x20202020, 0x65746e49, 0x2952286c);
+ break;
+ case 0x80000003:
+ SET_ABCD(0x726f4320, 0x4d542865, 0x35692029, 0x3033322d);
+ break;
+ case 0x80000004:
+ SET_ABCD(0x50432030, 0x20402055, 0x30382e32, 0x007a4847);
+ break;
+ case 0x80000005:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000006:
+ SET_ABCD(0x00000000, 0x00000000, 0x01006040, 0x00000000);
+ break;
+ case 0x80000007:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000100);
+ break;
+ case 0x80000008:
+ SET_ABCD(0x00003024, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ default:
+ SET_ABCD(0x00000007, 0x00000340, 0x00000340, 0x00000000);
+ break;
+ }
+# undef SET_ABCD
+}
+
+
ULong amd64g_calculate_RCR ( ULong arg,
ULong rot_amt,
ULong rflags_in,
@@ -2761,6 +3036,22 @@
}
/* CALLED FROM GENERATED CODE: CLEAN HELPER */
+ULong amd64g_calculate_sse_phminposuw ( ULong sLo, ULong sHi )
+{
+ UShort t, min;
+ UInt idx;
+ t = sel16x4_0(sLo); if (True) { min = t; idx = 0; }
+ t = sel16x4_1(sLo); if (t < min) { min = t; idx = 1; }
+ t = sel16x4_2(sLo); if (t < min) { min = t; idx = 2; }
+ t = sel16x4_3(sLo); if (t < min) { min = t; idx = 3; }
+ t = sel16x4_0(sHi); if (t < min) { min = t; idx = 4; }
+ t = sel16x4_1(sHi); if (t < min) { min = t; idx = 5; }
+ t = sel16x4_2(sHi); if (t < min) { min = t; idx = 6; }
+ t = sel16x4_3(sHi); if (t < min) { min = t; idx = 7; }
+ return ((ULong)(idx << 16)) | ((ULong)min);
+}
+
+/* CALLED FROM GENERATED CODE: CLEAN HELPER */
ULong amd64g_calc_crc32b ( ULong crcIn, ULong b )
{
UInt i;
@@ -2798,6 +3089,59 @@
}
+/* .. helper for next fn .. */
+static inline ULong sad_8x4 ( ULong xx, ULong yy )
+{
+ UInt t = 0;
+ t += (UInt)abdU8( sel8x8_3(xx), sel8x8_3(yy) );
+ t += (UInt)abdU8( sel8x8_2(xx), sel8x8_2(yy) );
+ t += (UInt)abdU8( sel8x8_1(xx), sel8x8_1(yy) );
+ t += (UInt)abdU8( sel8x8_0(xx), sel8x8_0(yy) );
+ return (ULong)t;
+}
+
+/* CALLED FROM GENERATED CODE: CLEAN HELPER */
+ULong amd64g_calc_mpsadbw ( ULong sHi, ULong sLo,
+ ULong dHi, ULong dLo,
+ ULong imm_and_return_control_bit )
+{
+ UInt imm8 = imm_and_return_control_bit & 7;
+ Bool calcHi = (imm_and_return_control_bit >> 7) & 1;
+ UInt srcOffsL = imm8 & 3; /* src offs in 32-bit (L) chunks */
+ UInt dstOffsL = (imm8 >> 2) & 1; /* dst offs in ditto chunks */
+ /* For src we only need 32 bits, so get them into the
+ lower half of a 64 bit word. */
+ ULong src = ((srcOffsL & 2) ? sHi : sLo) >> (32 * (srcOffsL & 1));
+ /* For dst we need to get hold of 56 bits (7 bytes) from a total of
+ 11 bytes. If calculating the low part of the result, need bytes
+ dstOffsL * 4 + (0 .. 6); if calculating the high part,
+ dstOffsL * 4 + (4 .. 10). */
+ ULong dst;
+ /* dstOffL = 0, Lo -> 0 .. 6
+ dstOffL = 1, Lo -> 4 .. 10
+ dstOffL = 0, Hi -> 4 .. 10
+ dstOffL = 1, Hi -> 8 .. 14
+ */
+ if (calcHi && dstOffsL) {
+ /* 8 .. 14 */
+ dst = dHi & 0x00FFFFFFFFFFFFFFULL;
+ }
+ else if (!calcHi && !dstOffsL) {
+ /* 0 .. 6 */
+ dst = dLo & 0x00FFFFFFFFFFFFFFULL;
+ }
+ else {
+ /* 4 .. 10 */
+ dst = (dLo >> 32) | ((dHi & 0x00FFFFFFULL) << 32);
+ }
+ ULong r0 = sad_8x4( dst >> 0, src );
+ ULong r1 = sad_8x4( dst >> 8, src );
+ ULong r2 = sad_8x4( dst >> 16, src );
+ ULong r3 = sad_8x4( dst >> 24, src );
+ ULong res = (r3 << 48) | (r2 << 32) | (r1 << 16) | r0;
+ return res;
+}
+
/*---------------------------------------------------------------*/
/*--- Helpers for SSE4.2 PCMP{E,I}STR{I,M} ---*/
/*---------------------------------------------------------------*/
@@ -2811,6 +3155,15 @@
return res;
}
+static UInt zmask_from_V128_wide ( V128* arg )
+{
+ UInt i, res = 0;
+ for (i = 0; i < 8; i++) {
+ res |= ((arg->w16[i] == 0) ? 1 : 0) << i;
+ }
+ return res;
+}
+
/* Helps with PCMP{I,E}STR{I,M}.
CALLED FROM GENERATED CODE: DIRTY HELPER(s). (But not really,
@@ -2861,7 +3214,7 @@
HWord isISTRx = opc4 & 2;
HWord isxSTRM = (opc4 & 1) ^ 1;
vassert((opc4 & 0xFC) == 0x60); /* 0x60 .. 0x63 */
- vassert((imm8 & 1) == 0); /* we support byte-size cases only */
+ HWord wide = (imm8 & 1);
// where the args are
V128* argL = (V128*)( ((UChar*)gst) + gstOffL );
@@ -2872,34 +3225,63 @@
// FIXME: this is only right for the 8-bit data cases.
// At least that is asserted above.
UInt zmaskL, zmaskR;
- if (isISTRx) {
- zmaskL = zmask_from_V128(argL);
- zmaskR = zmask_from_V128(argR);
- } else {
- Int tmp;
- tmp = edxIN & 0xFFFFFFFF;
- if (tmp < -16) tmp = -16;
- if (tmp > 16) tmp = 16;
- if (tmp < 0) tmp = -tmp;
- vassert(tmp >= 0 && tmp <= 16);
- zmaskL = (1 << tmp) & 0xFFFF;
- tmp = eaxIN & 0xFFFFFFFF;
- if (tmp < -16) tmp = -16;
- if (tmp > 16) tmp = 16;
- if (tmp < 0) tmp = -tmp;
- vassert(tmp >= 0 && tmp <= 16);
- zmaskR = (1 << tmp) & 0xFFFF;
- }
// temp spot for the resulting flags and vector.
V128 resV;
UInt resOSZACP;
- // do the meyaath
- Bool ok = compute_PCMPxSTRx (
- &resV, &resOSZACP, argL, argR,
- zmaskL, zmaskR, imm8, (Bool)isxSTRM
- );
+ // for checking whether case was handled
+ Bool ok = False;
+
+ if (wide) {
+ if (isISTRx) {
+ zmaskL = zmask_from_V128_wide(argL);
+ zmaskR = zmask_from_V128_wide(argR);
+ } else {
+ Int tmp;
+ tmp = edxIN & 0xFFFFFFFF;
+ if (tmp < -8) tmp = -8;
+ if (tmp > 8) tmp = 8;
+ if (tmp < 0) tmp = -tmp;
+ vassert(tmp >= 0 && tmp <= 8);
+ zmaskL = (1 << tmp) & 0xFF;
+ tmp = eaxIN & 0xFFFFFFFF;
+ if (tmp < -8) tmp = -8;
+ if (tmp > 8) tmp = 8;
+ if (tmp < 0) tmp = -tmp;
+ vassert(tmp >= 0 && tmp <= 8);
+ zmaskR = (1 << tmp) & 0xFF;
+ }
+ // do the meyaath
+ ok = compute_PCMPxSTRx_wide (
+ &resV, &resOSZACP, argL, argR,
+ zmaskL, zmaskR, imm8, (Bool)isxSTRM
+ );
+ } else {
+ if (isISTRx) {
+ zmaskL = zmask_from_V128(argL);
+ zmaskR = zmask_from_V128(argR);
+ } else {
+ Int tmp;
+ tmp = edxIN & 0xFFFFFFFF;
+ if (tmp < -16) tmp = -16;
+ if (tmp > 16) tmp = 16;
+ if (tmp < 0) tmp = -tmp;
+ vassert(tmp >= 0 && tmp <= 16);
+ zmaskL = (1 << tmp) & 0xFFFF;
+ tmp = eaxIN & 0xFFFFFFFF;
+ if (tmp < -16) tmp = -16;
+ if (tmp > 16) tmp = 16;
+ if (tmp < 0) tmp = -tmp;
+ vassert(tmp >= 0 && tmp <= 16);
+ zmaskR = (1 << tmp) & 0xFFFF;
+ }
+ // do the meyaath
+ ok = compute_PCMPxSTRx (
+ &resV, &resOSZACP, argL, argR,
+ zmaskL, zmaskR, imm8, (Bool)isxSTRM
+ );
+ }
// front end shouldn't pass us any imm8 variants we can't
// handle. Hence:
@@ -2909,11 +3291,10 @@
// In all cases, the new OSZACP value is the lowest 16 of
// the return value.
if (isxSTRM) {
- /* gst->guest_XMM0 = resV; */ // gcc don't like that
- gst->guest_XMM0[0] = resV.w32[0];
- gst->guest_XMM0[1] = resV.w32[1];
- gst->guest_XMM0[2] = resV.w32[2];
- gst->guest_XMM0[3] = resV.w32[3];
+ gst->guest_YMM0[0] = resV.w32[0];
+ gst->guest_YMM0[1] = resV.w32[1];
+ gst->guest_YMM0[2] = resV.w32[2];
+ gst->guest_YMM0[3] = resV.w32[3];
return resOSZACP & 0x8D5;
} else {
UInt newECX = resV.w32[0] & 0xFFFF;
@@ -2921,6 +3302,328 @@
}
}
+/*---------------------------------------------------------------*/
+/*--- AES primitives and helpers ---*/
+/*---------------------------------------------------------------*/
+/* a 16 x 16 matrix */
+static const UChar sbox[256] = { // row nr
+ 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, // 1
+ 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
+ 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, // 2
+ 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
+ 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, // 3
+ 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+ 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, // 4
+ 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
+ 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, // 5
+ 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
+ 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, // 6
+ 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+ 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, // 7
+ 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
+ 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, // 8
+ 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
+ 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, // 9
+ 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
+ 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, //10
+ 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
+ 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, //11
+ 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
+ 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, //12
+ 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
+ 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, //13
+ 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
+ 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, //14
+ 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
+ 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, //15
+ 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
+ 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, //16
+ 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+};
+static void SubBytes (V128* v)
+{
+ V128 r;
+ UInt i;
+ for (i = 0; i < 16; i++)
+ r.w8[i] = sbox[v->w8[i]];
+ *v = r;
+}
+
+/* a 16 x 16 matrix */
+static const UChar invsbox[256] = { // row nr
+ 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, // 1
+ 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
+ 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, // 2
+ 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
+ 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, // 3
+ 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
+ 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, // 4
+ 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
+ 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, // 5
+ 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
+ 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, // 6
+ 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
+ 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, // 7
+ 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
+ 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, // 8
+ 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
+ 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, // 9
+ 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
+ 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, //10
+ 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
+ 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, //11
+ 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
+ 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, //12
+ 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
+ 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, //13
+ 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
+ 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, //14
+ 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
+ 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, //15
+ 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
+ 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, //16
+ 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
+};
+static void InvSubBytes (V128* v)
+{
+ V128 r;
+ UInt i;
+ for (i = 0; i < 16; i++)
+ r.w8[i] = invsbox[v->w8[i]];
+ *v = r;
+}
+
+static const UChar ShiftRows_op[16] =
+ {11, 6, 1, 12, 7, 2, 13, 8, 3, 14, 9, 4, 15, 10, 5, 0};
+static void ShiftRows (V128* v)
+{
+ V128 r;
+ UInt i;
+ for (i = 0; i < 16; i++)
+ r.w8[i] = v->w8[ShiftRows_op[15-i]];
+ *v = r;
+}
+
+static const UChar InvShiftRows_op[16] =
+ {3, 6, 9, 12, 15, 2, 5, 8, 11, 14, 1, 4, 7, 10, 13, 0};
+static void InvShiftRows (V128* v)
+{
+ V128 r;
+ UInt i;
+ for (i = 0; i < 16; i++)
+ r.w8[i] = v->w8[InvShiftRows_op[15-i]];
+ *v = r;
+}
+
+/* Multiplication of the finite fields elements of AES.
+ See "A Specification for The AES Algorithm Rijndael
+ (by Joan Daemen & Vincent Rijmen)"
+ Dr. Brian Gladman, v3.1, 3rd March 2001. */
+/* N values so that (hex) xy = 0x03^N.
+ 0x00 cannot be used. We put 0xff for this value.*/
+/* a 16 x 16 matrix */
+static const UChar Nxy[256] = { // row nr
+ 0xff, 0x00, 0x19, 0x01, 0x32, 0x02, 0x1a, 0xc6, // 1
+ 0x4b, 0xc7, 0x1b, 0x68, 0x33, 0xee, 0xdf, 0x03,
+ 0x64, 0x04, 0xe0, 0x0e, 0x34, 0x8d, 0x81, 0xef, // 2
+ 0x4c, 0x71, 0x08, 0xc8, 0xf8, 0x69, 0x1c, 0xc1,
+ 0x7d, 0xc2, 0x1d, 0xb5, 0xf9, 0xb9, 0x27, 0x6a, // 3
+ 0x4d, 0xe4, 0xa6, 0x72, 0x9a, 0xc9, 0x09, 0x78,
+ 0x65, 0x2f, 0x8a, 0x05, 0x21, 0x0f, 0xe1, 0x24, // 4
+ 0x12, 0xf0, 0x82, 0x45, 0x35, 0x93, 0xda, 0x8e,
+ 0x96, 0x8f, 0xdb, 0xbd, 0x36, 0xd0, 0xce, 0x94, // 5
+ 0x13, 0x5c, 0xd2, 0xf1, 0x40, 0x46, 0x83, 0x38,
+ 0x66, 0xdd, 0xfd, 0x30, 0xbf, 0x06, 0x8b, 0x62, // 6
+ 0xb3, 0x25, 0xe2, 0x98, 0x22, 0x88, 0x91, 0x10,
+ 0x7e, 0x6e, 0x48, 0xc3, 0xa3, 0xb6, 0x1e, 0x42, // 7
+ 0x3a, 0x6b, 0x28, 0x54, 0xfa, 0x85, 0x3d, 0xba,
+ 0x2b, 0x79, 0x0a, 0x15, 0x9b, 0x9f, 0x5e, 0xca, // 8
+ 0x4e, 0xd4, 0xac, 0xe5, 0xf3, 0x73, 0xa7, 0x57,
+ 0xaf, 0x58, 0xa8, 0x50, 0xf4, 0xea, 0xd6, 0x74, // 9
+ 0x4f, 0xae, 0xe9, 0xd5, 0xe7, 0xe6, 0xad, 0xe8,
+ 0x2c, 0xd7, 0x75, 0x7a, 0xeb, 0x16, 0x0b, 0xf5, //10
+ 0x59, 0xcb, 0x5f, 0xb0, 0x9c, 0xa9, 0x51, 0xa0,
+ 0x7f, 0x0c, 0xf6, 0x6f, 0x17, 0xc4, 0x49, 0xec, //11
+ 0xd8, 0x43, 0x1f, 0x2d, 0xa4, 0x76, 0x7b, 0xb7,
+ 0xcc, 0xbb, 0x3e, 0x5a, 0xfb, 0x60, 0xb1, 0x86, //12
+ 0x3b, 0x52, 0xa1, 0x6c, 0xaa, 0x55, 0x29, 0x9d,
+ 0x97, 0xb2, 0x87, 0x90, 0x61, 0xbe, 0xdc, 0xfc, //13
+ 0xbc, 0x95, 0xcf, 0xcd, 0x37, 0x3f, 0x5b, 0xd1,
+ 0x53, 0x39, 0x84, 0x3c, 0x41, 0xa2, 0x6d, 0x47, //14
+ 0x14, 0x2a, 0x9e, 0x5d, 0x56, 0xf2, 0xd3, 0xab,
+ 0x44, 0x11, 0x92, 0xd9, 0x23, 0x20, 0x2e, 0x89, //15
+ 0xb4, 0x7c, 0xb8, 0x26, 0x77, 0x99, 0xe3, 0xa5,
+ 0x67, 0x4a, 0xed, 0xde, 0xc5, 0x31, 0xfe, 0x18, //16
+ 0x0d, 0x63, 0x8c, 0x80, 0xc0, 0xf7, 0x70, 0x07
+};
+
+/* E values so that E = 0x03^xy. */
+static const UChar Exy[256] = { // row nr
+ 0x01, 0x03, 0x05, 0x0f, 0x11, 0x33, 0x55, 0xff, // 1
+ 0x1a, 0x2e, 0x72, 0x96, 0xa1, 0xf8, 0x13, 0x35,
+ 0x5f, 0xe1, 0x38, 0x48, 0xd8, 0x73, 0x95, 0xa4, // 2
+ 0xf7, 0x02, 0x06, 0x0a, 0x1e, 0x22, 0x66, 0xaa,
+ 0xe5, 0x34, 0x5c, 0xe4, 0x37, 0x59, 0xeb, 0x26, // 3
+ 0x6a, 0xbe, 0xd9, 0x70, 0x90, 0xab, 0xe6, 0x31,
+ 0x53, 0xf5, 0x04, 0x0c, 0x14, 0x3c, 0x44, 0xcc, // 4
+ 0x4f, 0xd1, 0x68, 0xb8, 0xd3, 0x6e, 0xb2, 0xcd,
+ 0x4c, 0xd4, 0x67, 0xa9, 0xe0, 0x3b, 0x4d, 0xd7, // 5
+ 0x62, 0xa6, 0xf1, 0x08, 0x18, 0x28, 0x78, 0x88,
+ 0x83, 0x9e, 0xb9, 0xd0, 0x6b, 0xbd, 0xdc, 0x7f, // 6
+ 0x81, 0x98, 0xb3, 0xce, 0x49, 0xdb, 0x76, 0x9a,
+ 0xb5, 0xc4, 0x57, 0xf9, 0x10, 0x30, 0x50, 0xf0, // 7
+ 0x0b, 0x1d, 0x27, 0x69, 0xbb, 0xd6, 0x61, 0xa3,
+ 0xfe, 0x19, 0x2b, 0x7d, 0x87, 0x92, 0xad, 0xec, // 8
+ 0x2f, 0x71, 0x93, 0xae, 0xe9, 0x20, 0x60, 0xa0,
+ 0xfb, 0x16, 0x3a, 0x4e, 0xd2, 0x6d, 0xb7, 0xc2, // 9
+ 0x5d, 0xe7, 0x32, 0x56, 0xfa, 0x15, 0x3f, 0x41,
+ 0xc3, 0x5e, 0xe2, 0x3d, 0x47, 0xc9, 0x40, 0xc0, //10
+ 0x5b, 0xed, 0x2c, 0x74, 0x9c, 0xbf, 0xda, 0x75,
+ 0x9f, 0xba, 0xd5, 0x64, 0xac, 0xef, 0x2a, 0x7e, //11
+ 0x82, 0x9d, 0xbc, 0xdf, 0x7a, 0x8e, 0x89, 0x80,
+ 0x9b, 0xb6, 0xc1, 0x58, 0xe8, 0x23, 0x65, 0xaf, //12
+ 0xea, 0x25, 0x6f, 0xb1, 0xc8, 0x43, 0xc5, 0x54,
+ 0xfc, 0x1f, 0x21, 0x63, 0xa5, 0xf4, 0x07, 0x09, //13
+ 0x1b, 0x2d, 0x77, 0x99, 0xb0, 0xcb, 0x46, 0xca,
+ 0x45, 0xcf, 0x4a, 0xde, 0x79, 0x8b, 0x86, 0x91, //14
+ 0xa8, 0xe3, 0x3e, 0x42, 0xc6, 0x51, 0xf3, 0x0e,
+ 0x12, 0x36, 0x5a, 0xee, 0x29, 0x7b, 0x8d, 0x8c, //15
+ 0x8f, 0x8a, 0x85, 0x94, 0xa7, 0xf2, 0x0d, 0x17,
+ 0x39, 0x4b, 0xdd, 0x7c, 0x84, 0x97, 0xa2, 0xfd, //16
+ 0x1c, 0x24, 0x6c, 0xb4, 0xc7, 0x52, 0xf6, 0x01};
+
+static inline UChar ff_mul(UChar u1, UChar u2)
+{
+ if ((u1 > 0) && (u2 > 0)) {
+ UInt ui = Nxy[u1] + Nxy[u2];
+ if (ui >= 255)
+ ui = ui - 255;
+ return Exy[ui];
+ } else {
+ return 0;
+ };
+}
+
+static void MixColumns (V128* v)
+{
+ V128 r;
+ Int j;
+#define P(x,row,col) (x)->w8[((row)*4+(col))]
+ for (j = 0; j < 4; j++) {
+ P(&r,j,0) = ff_mul(0x02, P(v,j,0)) ^ ff_mul(0x03, P(v,j,1))
+ ^ P(v,j,2) ^ P(v,j,3);
+ P(&r,j,1) = P(v,j,0) ^ ff_mul( 0x02, P(v,j,1) )
+ ^ ff_mul(0x03, P(v,j,2) ) ^ P(v,j,3);
+ P(&r,j,2) = P(v,j,0) ^ P(v,j,1) ^ ff_mul( 0x02, P(v,j,2) )
+ ^ ff_mul(0x03, P(v,j,3) );
+ P(&r,j,3) = ff_mul(0x03, P(v,j,0) ) ^ P(v,j,1) ^ P(v,j,2)
+ ^ ff_mul( 0x02, P(v,j,3) );
+ }
+ *v = r;
+#undef P
+}
+
+static void InvMixColumns (V128* v)
+{
+ V128 r;
+ Int j;
+#define P(x,row,col) (x)->w8[((row)*4+(col))]
+ for (j = 0; j < 4; j++) {
+ P(&r,j,0) = ff_mul(0x0e, P(v,j,0) ) ^ ff_mul(0x0b, P(v,j,1) )
+ ^ ff_mul(0x0d,P(v,j,2) ) ^ ff_mul(0x09, P(v,j,3) );
+ P(&r,j,1) = ff_mul(0x09, P(v,j,0) ) ^ ff_mul(0x0e, P(v,j,1) )
+ ^ ff_mul(0x0b,P(v,j,2) ) ^ ff_mul(0x0d, P(v,j,3) );
+ P(&r,j,2) = ff_mul(0x0d, P(v,j,0) ) ^ ff_mul(0x09, P(v,j,1) )
+ ^ ff_mul(0x0e,P(v,j,2) ) ^ ff_mul(0x0b, P(v,j,3) );
+ P(&r,j,3) = ff_mul(0x0b, P(v,j,0) ) ^ ff_mul(0x0d, P(v,j,1) )
+ ^ ff_mul(0x09,P(v,j,2) ) ^ ff_mul(0x0e, P(v,j,3) );
+ }
+ *v = r;
+#undef P
+
+}
+
+/* For description, see definition in guest_amd64_defs.h */
+void amd64g_dirtyhelper_AES (
+ VexGuestAMD64State* gst,
+ HWord opc4, HWord gstOffD,
+ HWord gstOffL, HWord gstOffR
+ )
+{
+ // where the args are
+ V128* argD = (V128*)( ((UChar*)gst) + gstOffD );
+ V128* argL = (V128*)( ((UChar*)gst) + gstOffL );
+ V128* argR = (V128*)( ((UChar*)gst) + gstOffR );
+ V128 r;
+
+ switch (opc4) {
+ case 0xDC: /* AESENC */
+ case 0xDD: /* AESENCLAST */
+ r = *argR;
+ ShiftRows (&r);
+ SubBytes (&r);
+ if (opc4 == 0xDC)
+ MixColumns (&r);
+ argD->w64[0] = r.w64[0] ^ argL->w64[0];
+ argD->w64[1] = r.w64[1] ^ argL->w64[1];
+ break;
+
+ case 0xDE: /* AESDEC */
+ case 0xDF: /* AESDECLAST */
+ r = *argR;
+ InvShiftRows (&r);
+ InvSubBytes (&r);
+ if (opc4 == 0xDE)
+ InvMixColumns (&r);
+ argD->w64[0] = r.w64[0] ^ argL->w64[0];
+ argD->w64[1] = r.w64[1] ^ argL->w64[1];
+ break;
+
+ case 0xDB: /* AESIMC */
+ *argD = *argL;
+ InvMixColumns (argD);
+ break;
+ default: vassert(0);
+ }
+}
+
+static inline UInt RotWord (UInt w32)
+{
+ return ((w32 >> 8) | (w32 << 24));
+}
+
+static inline UInt SubWord (UInt w32)
+{
+ UChar *w8;
+ UChar *r8;
+ UInt res;
+ w8 = (UChar*) &w32;
+ r8 = (UChar*) &res;
+ r8[0] = sbox[w8[0]];
+ r8[1] = sbox[w8[1]];
+ r8[2] = sbox[w8[2]];
+ r8[3] = sbox[w8[3]];
+ return res;
+}
+
+/* For description, see definition in guest_amd64_defs.h */
+extern void amd64g_dirtyhelper_AESKEYGENASSIST (
+ VexGuestAMD64State* gst,
+ HWord imm8,
+ HWord gstOffL, HWord gstOffR
+ )
+{
+ // where the args are
+ V128* argL = (V128*)( ((UChar*)gst) + gstOffL );
+ V128* argR = (V128*)( ((UChar*)gst) + gstOffR );
+
+ argR->w32[3] = RotWord (SubWord (argL->w32[3])) ^ imm8;
+ argR->w32[2] = SubWord (argL->w32[3]);
+ argR->w32[1] = RotWord (SubWord (argL->w32[1])) ^ imm8;
+ argR->w32[0] = SubWord (argL->w32[1]);
+}
+
+
/*---------------------------------------------------------------*/
/*--- Helpers for dealing with, and describing, ---*/
@@ -2931,6 +3634,10 @@
/* VISIBLE TO LIBVEX CLIENT */
void LibVEX_GuestAMD64_initialise ( /*OUT*/VexGuestAMD64State* vex_state )
{
+ vex_state->host_EvC_FAILADDR = 0;
+ vex_state->host_EvC_COUNTER = 0;
+ vex_state->pad0 = 0;
+
vex_state->guest_RAX = 0;
vex_state->guest_RCX = 0;
vex_state->guest_RDX = 0;
@@ -2965,29 +3672,31 @@
/* Initialise the simulated FPU */
amd64g_dirtyhelper_FINIT( vex_state );
- /* Initialise the SSE state. */
-# define SSEZERO(_xmm) _xmm[0]=_xmm[1]=_xmm[2]=_xmm[3] = 0;
-
+ /* Initialise the AVX state. */
+# define AVXZERO(_ymm) \
+ do { _ymm[0]=_ymm[1]=_ymm[2]=_ymm[3] = 0; \
+ _ymm[4]=_ymm[5]=_ymm[6]=_ymm[7] = 0; \
+ } while (0)
vex_state->guest_SSEROUND = (ULong)Irrm_NEAREST;
- SSEZERO(vex_state->guest_XMM0);
- SSEZERO(vex_state->guest_XMM1);
- SSEZERO(vex_state->guest_XMM2);
- SSEZERO(vex_state->guest_XMM3);
- SSEZERO(vex_state->guest_XMM4);
- SSEZERO(vex_state->guest_XMM5);
- SSEZERO(vex_state->guest_XMM6);
- SSEZERO(vex_state->guest_XMM7);
- SSEZERO(vex_state->guest_XMM8);
- SSEZERO(vex_state->guest_XMM9);
- SSEZERO(vex_state->guest_XMM10);
- SSEZERO(vex_state->guest_XMM11);
- SSEZERO(vex_state->guest_XMM12);
- SSEZERO(vex_state->guest_XMM13);
- SSEZERO(vex_state->guest_XMM14);
- SSEZERO(vex_state->guest_XMM15);
- SSEZERO(vex_state->guest_XMM16);
+ AVXZERO(vex_state->guest_YMM0);
+ AVXZERO(vex_state->guest_YMM1);
+ AVXZERO(vex_state->guest_YMM2);
+ AVXZERO(vex_state->guest_YMM3);
+ AVXZERO(vex_state->guest_YMM4);
+ AVXZERO(vex_state->guest_YMM5);
+ AVXZERO(vex_state->guest_YMM6);
+ AVXZERO(vex_state->guest_YMM7);
+ AVXZERO(vex_state->guest_YMM8);
+ AVXZERO(vex_state->guest_YMM9);
+ AVXZERO(vex_state->guest_YMM10);
+ AVXZERO(vex_state->guest_YMM11);
+ AVXZERO(vex_state->guest_YMM12);
+ AVXZERO(vex_state->guest_YMM13);
+ AVXZERO(vex_state->guest_YMM14);
+ AVXZERO(vex_state->guest_YMM15);
+ AVXZERO(vex_state->guest_YMM16);
-# undef SSEZERO
+# undef AVXZERO
vex_state->guest_EMWARN = EmWarn_NONE;
@@ -3001,7 +3710,7 @@
vex_state->guest_GS_0x60 = 0;
vex_state->guest_IP_AT_SYSCALL = 0;
- /* vex_state->padding = 0; */
+ vex_state->pad1 = 0;
}
diff --git a/main/VEX/priv/guest_amd64_toIR.c b/main/VEX/priv/guest_amd64_toIR.c
index a3d817e..b690e5e 100644
--- a/main/VEX/priv/guest_amd64_toIR.c
+++ b/main/VEX/priv/guest_amd64_toIR.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -416,34 +416,25 @@
#define OFFB_FTOP offsetof(VexGuestAMD64State,guest_FTOP)
#define OFFB_FC3210 offsetof(VexGuestAMD64State,guest_FC3210)
#define OFFB_FPROUND offsetof(VexGuestAMD64State,guest_FPROUND)
-//..
-//.. #define OFFB_CS offsetof(VexGuestX86State,guest_CS)
-//.. #define OFFB_DS offsetof(VexGuestX86State,guest_DS)
-//.. #define OFFB_ES offsetof(VexGuestX86State,guest_ES)
-//.. #define OFFB_FS offsetof(VexGuestX86State,guest_FS)
-//.. #define OFFB_GS offsetof(VexGuestX86State,guest_GS)
-//.. #define OFFB_SS offsetof(VexGuestX86State,guest_SS)
-//.. #define OFFB_LDT offsetof(VexGuestX86State,guest_LDT)
-//.. #define OFFB_GDT offsetof(VexGuestX86State,guest_GDT)
#define OFFB_SSEROUND offsetof(VexGuestAMD64State,guest_SSEROUND)
-#define OFFB_XMM0 offsetof(VexGuestAMD64State,guest_XMM0)
-#define OFFB_XMM1 offsetof(VexGuestAMD64State,guest_XMM1)
-#define OFFB_XMM2 offsetof(VexGuestAMD64State,guest_XMM2)
-#define OFFB_XMM3 offsetof(VexGuestAMD64State,guest_XMM3)
-#define OFFB_XMM4 offsetof(VexGuestAMD64State,guest_XMM4)
-#define OFFB_XMM5 offsetof(VexGuestAMD64State,guest_XMM5)
-#define OFFB_XMM6 offsetof(VexGuestAMD64State,guest_XMM6)
-#define OFFB_XMM7 offsetof(VexGuestAMD64State,guest_XMM7)
-#define OFFB_XMM8 offsetof(VexGuestAMD64State,guest_XMM8)
-#define OFFB_XMM9 offsetof(VexGuestAMD64State,guest_XMM9)
-#define OFFB_XMM10 offsetof(VexGuestAMD64State,guest_XMM10)
-#define OFFB_XMM11 offsetof(VexGuestAMD64State,guest_XMM11)
-#define OFFB_XMM12 offsetof(VexGuestAMD64State,guest_XMM12)
-#define OFFB_XMM13 offsetof(VexGuestAMD64State,guest_XMM13)
-#define OFFB_XMM14 offsetof(VexGuestAMD64State,guest_XMM14)
-#define OFFB_XMM15 offsetof(VexGuestAMD64State,guest_XMM15)
-#define OFFB_XMM16 offsetof(VexGuestAMD64State,guest_XMM16)
+#define OFFB_YMM0 offsetof(VexGuestAMD64State,guest_YMM0)
+#define OFFB_YMM1 offsetof(VexGuestAMD64State,guest_YMM1)
+#define OFFB_YMM2 offsetof(VexGuestAMD64State,guest_YMM2)
+#define OFFB_YMM3 offsetof(VexGuestAMD64State,guest_YMM3)
+#define OFFB_YMM4 offsetof(VexGuestAMD64State,guest_YMM4)
+#define OFFB_YMM5 offsetof(VexGuestAMD64State,guest_YMM5)
+#define OFFB_YMM6 offsetof(VexGuestAMD64State,guest_YMM6)
+#define OFFB_YMM7 offsetof(VexGuestAMD64State,guest_YMM7)
+#define OFFB_YMM8 offsetof(VexGuestAMD64State,guest_YMM8)
+#define OFFB_YMM9 offsetof(VexGuestAMD64State,guest_YMM9)
+#define OFFB_YMM10 offsetof(VexGuestAMD64State,guest_YMM10)
+#define OFFB_YMM11 offsetof(VexGuestAMD64State,guest_YMM11)
+#define OFFB_YMM12 offsetof(VexGuestAMD64State,guest_YMM12)
+#define OFFB_YMM13 offsetof(VexGuestAMD64State,guest_YMM13)
+#define OFFB_YMM14 offsetof(VexGuestAMD64State,guest_YMM14)
+#define OFFB_YMM15 offsetof(VexGuestAMD64State,guest_YMM15)
+#define OFFB_YMM16 offsetof(VexGuestAMD64State,guest_YMM16)
#define OFFB_EMWARN offsetof(VexGuestAMD64State,guest_EMWARN)
#define OFFB_TISTART offsetof(VexGuestAMD64State,guest_TISTART)
@@ -475,9 +466,6 @@
#define R_R14 14
#define R_R15 15
-//.. #define R_AL (0+R_EAX)
-//.. #define R_AH (4+R_EAX)
-
/* This is the Intel register encoding -- segment regs. */
#define R_ES 0
#define R_CS 1
@@ -531,7 +519,7 @@
/* Get a 8/16/32-bit unsigned value out of the insn stream. */
-static UChar getUChar ( Long delta )
+static inline UChar getUChar ( Long delta )
{
UChar v = guest_code[delta+0];
return v;
@@ -649,8 +637,8 @@
most especially when making sense of register fields in
instructions.
- The top 16 bits of the prefix are 0x3141, just as a hacky way
- to ensure it really is a valid prefix.
+ The top 8 bits of the prefix are 0x55, just as a hacky way to
+ ensure it really is a valid prefix.
Things you can safely assume about a well-formed prefix:
* at most one segment-override bit (CS,DS,ES,FS,GS,SS) is set.
@@ -661,27 +649,37 @@
typedef UInt Prefix;
-#define PFX_ASO (1<<0) /* address-size override present (0x67) */
-#define PFX_66 (1<<1) /* operand-size override-to-16 present (0x66) */
-#define PFX_REX (1<<2) /* REX byte present (0x40 to 0x4F) */
-#define PFX_REXW (1<<3) /* REX W bit, if REX present, else 0 */
-#define PFX_REXR (1<<4) /* REX R bit, if REX present, else 0 */
-#define PFX_REXX (1<<5) /* REX X bit, if REX present, else 0 */
-#define PFX_REXB (1<<6) /* REX B bit, if REX present, else 0 */
-#define PFX_LOCK (1<<7) /* bus LOCK prefix present (0xF0) */
-#define PFX_F2 (1<<8) /* REP/REPE/REPZ prefix present (0xF2) */
-#define PFX_F3 (1<<9) /* REPNE/REPNZ prefix present (0xF3) */
-#define PFX_CS (1<<10) /* CS segment prefix present (0x2E) */
-#define PFX_DS (1<<11) /* DS segment prefix present (0x3E) */
-#define PFX_ES (1<<12) /* ES segment prefix present (0x26) */
-#define PFX_FS (1<<13) /* FS segment prefix present (0x64) */
-#define PFX_GS (1<<14) /* GS segment prefix present (0x65) */
-#define PFX_SS (1<<15) /* SS segment prefix present (0x36) */
+#define PFX_ASO (1<<0) /* address-size override present (0x67) */
+#define PFX_66 (1<<1) /* operand-size override-to-16 present (0x66) */
+#define PFX_REX (1<<2) /* REX byte present (0x40 to 0x4F) */
+#define PFX_REXW (1<<3) /* REX W bit, if REX present, else 0 */
+#define PFX_REXR (1<<4) /* REX R bit, if REX present, else 0 */
+#define PFX_REXX (1<<5) /* REX X bit, if REX present, else 0 */
+#define PFX_REXB (1<<6) /* REX B bit, if REX present, else 0 */
+#define PFX_LOCK (1<<7) /* bus LOCK prefix present (0xF0) */
+#define PFX_F2 (1<<8) /* REP/REPE/REPZ prefix present (0xF2) */
+#define PFX_F3 (1<<9) /* REPNE/REPNZ prefix present (0xF3) */
+#define PFX_CS (1<<10) /* CS segment prefix present (0x2E) */
+#define PFX_DS (1<<11) /* DS segment prefix present (0x3E) */
+#define PFX_ES (1<<12) /* ES segment prefix present (0x26) */
+#define PFX_FS (1<<13) /* FS segment prefix present (0x64) */
+#define PFX_GS (1<<14) /* GS segment prefix present (0x65) */
+#define PFX_SS (1<<15) /* SS segment prefix present (0x36) */
+#define PFX_VEX (1<<16) /* VEX prefix present (0xC4 or 0xC5) */
+#define PFX_VEXL (1<<17) /* VEX L bit, if VEX present, else 0 */
+/* The extra register field VEX.vvvv is encoded (after not-ing it) as
+ PFX_VEXnV3 .. PFX_VEXnV0, so these must occupy adjacent bit
+ positions. */
+#define PFX_VEXnV0 (1<<18) /* ~VEX vvvv[0], if VEX present, else 0 */
+#define PFX_VEXnV1 (1<<19) /* ~VEX vvvv[1], if VEX present, else 0 */
+#define PFX_VEXnV2 (1<<20) /* ~VEX vvvv[2], if VEX present, else 0 */
+#define PFX_VEXnV3 (1<<21) /* ~VEX vvvv[3], if VEX present, else 0 */
-#define PFX_EMPTY 0x31410000
+
+#define PFX_EMPTY 0x55000000
static Bool IS_VALID_PFX ( Prefix pfx ) {
- return toBool((pfx & 0xFFFF0000) == PFX_EMPTY);
+ return toBool((pfx & 0xFF000000) == PFX_EMPTY);
}
static Bool haveREX ( Prefix pfx ) {
@@ -691,11 +689,9 @@
static Int getRexW ( Prefix pfx ) {
return (pfx & PFX_REXW) ? 1 : 0;
}
-/* Apparently unused.
static Int getRexR ( Prefix pfx ) {
return (pfx & PFX_REXR) ? 1 : 0;
}
-*/
static Int getRexX ( Prefix pfx ) {
return (pfx & PFX_REXX) ? 1 : 0;
}
@@ -783,6 +779,42 @@
p & ~(PFX_CS | PFX_DS | PFX_ES | PFX_FS | PFX_GS | PFX_SS);
}
+/* Get the (inverted, hence back to "normal") VEX.vvvv field. */
+static UInt getVexNvvvv ( Prefix pfx ) {
+ UInt r = (UInt)pfx;
+ r /= (UInt)PFX_VEXnV0; /* pray this turns into a shift */
+ return r & 0xF;
+}
+
+static Bool haveVEX ( Prefix pfx ) {
+ return toBool(pfx & PFX_VEX);
+}
+
+static Int getVexL ( Prefix pfx ) {
+ return (pfx & PFX_VEXL) ? 1 : 0;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- For dealing with escapes ---*/
+/*------------------------------------------------------------*/
+
+
+/* Escapes come after the prefixes, but before the primary opcode
+ byte. They escape the primary opcode byte into a bigger space.
+ The 0xF0000000 isn't significant, except so as to make it not
+ overlap valid Prefix values, for sanity checking.
+*/
+
+typedef
+ enum {
+ ESC_NONE=0xF0000000, // none
+ ESC_0F, // 0F
+ ESC_0F38, // 0F 38
+ ESC_0F3A // 0F 3A
+ }
+ Escape;
+
/*------------------------------------------------------------*/
/*--- For dealing with integer registers ---*/
@@ -1310,40 +1342,34 @@
/*--- For dealing with XMM registers ---*/
/*------------------------------------------------------------*/
-//.. static Int segmentGuestRegOffset ( UInt sreg )
-//.. {
-//.. switch (sreg) {
-//.. case R_ES: return OFFB_ES;
-//.. case R_CS: return OFFB_CS;
-//.. case R_SS: return OFFB_SS;
-//.. case R_DS: return OFFB_DS;
-//.. case R_FS: return OFFB_FS;
-//.. case R_GS: return OFFB_GS;
-//.. default: vpanic("segmentGuestRegOffset(x86)");
-//.. }
-//.. }
+static Int ymmGuestRegOffset ( UInt ymmreg )
+{
+ switch (ymmreg) {
+ case 0: return OFFB_YMM0;
+ case 1: return OFFB_YMM1;
+ case 2: return OFFB_YMM2;
+ case 3: return OFFB_YMM3;
+ case 4: return OFFB_YMM4;
+ case 5: return OFFB_YMM5;
+ case 6: return OFFB_YMM6;
+ case 7: return OFFB_YMM7;
+ case 8: return OFFB_YMM8;
+ case 9: return OFFB_YMM9;
+ case 10: return OFFB_YMM10;
+ case 11: return OFFB_YMM11;
+ case 12: return OFFB_YMM12;
+ case 13: return OFFB_YMM13;
+ case 14: return OFFB_YMM14;
+ case 15: return OFFB_YMM15;
+ default: vpanic("ymmGuestRegOffset(amd64)");
+ }
+}
static Int xmmGuestRegOffset ( UInt xmmreg )
{
- switch (xmmreg) {
- case 0: return OFFB_XMM0;
- case 1: return OFFB_XMM1;
- case 2: return OFFB_XMM2;
- case 3: return OFFB_XMM3;
- case 4: return OFFB_XMM4;
- case 5: return OFFB_XMM5;
- case 6: return OFFB_XMM6;
- case 7: return OFFB_XMM7;
- case 8: return OFFB_XMM8;
- case 9: return OFFB_XMM9;
- case 10: return OFFB_XMM10;
- case 11: return OFFB_XMM11;
- case 12: return OFFB_XMM12;
- case 13: return OFFB_XMM13;
- case 14: return OFFB_XMM14;
- case 15: return OFFB_XMM15;
- default: vpanic("xmmGuestRegOffset(amd64)");
- }
+ /* Correct for little-endian host only. */
+ vassert(!host_is_bigendian);
+ return ymmGuestRegOffset( xmmreg );
}
/* Lanes of vector registers are always numbered from zero being the
@@ -1373,16 +1399,29 @@
return xmmGuestRegOffset( xmmreg ) + 8 * laneno;
}
-//.. static IRExpr* getSReg ( UInt sreg )
-//.. {
-//.. return IRExpr_Get( segmentGuestRegOffset(sreg), Ity_I16 );
-//.. }
-//..
-//.. static void putSReg ( UInt sreg, IRExpr* e )
-//.. {
-//.. vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16);
-//.. stmt( IRStmt_Put( segmentGuestRegOffset(sreg), e ) );
-//.. }
+static Int ymmGuestRegLane128offset ( UInt ymmreg, Int laneno )
+{
+ /* Correct for little-endian host only. */
+ vassert(!host_is_bigendian);
+ vassert(laneno >= 0 && laneno < 2);
+ return ymmGuestRegOffset( ymmreg ) + 16 * laneno;
+}
+
+static Int ymmGuestRegLane64offset ( UInt ymmreg, Int laneno )
+{
+ /* Correct for little-endian host only. */
+ vassert(!host_is_bigendian);
+ vassert(laneno >= 0 && laneno < 4);
+ return ymmGuestRegOffset( ymmreg ) + 8 * laneno;
+}
+
+static Int ymmGuestRegLane32offset ( UInt ymmreg, Int laneno )
+{
+ /* Correct for little-endian host only. */
+ vassert(!host_is_bigendian);
+ vassert(laneno >= 0 && laneno < 8);
+ return ymmGuestRegOffset( ymmreg ) + 4 * laneno;
+}
static IRExpr* getXMMReg ( UInt xmmreg )
{
@@ -1444,10 +1483,60 @@
stmt( IRStmt_Put( xmmGuestRegLane32offset(xmmreg,laneno), e ) );
}
-static void putXMMRegLane16 ( UInt xmmreg, Int laneno, IRExpr* e )
+static IRExpr* getYMMReg ( UInt xmmreg )
{
- vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16);
- stmt( IRStmt_Put( xmmGuestRegLane16offset(xmmreg,laneno), e ) );
+ return IRExpr_Get( ymmGuestRegOffset(xmmreg), Ity_V256 );
+}
+
+static IRExpr* getYMMRegLane128 ( UInt ymmreg, Int laneno )
+{
+ return IRExpr_Get( ymmGuestRegLane128offset(ymmreg,laneno), Ity_V128 );
+}
+
+static IRExpr* getYMMRegLane64 ( UInt ymmreg, Int laneno )
+{
+ return IRExpr_Get( ymmGuestRegLane64offset(ymmreg,laneno), Ity_I64 );
+}
+
+static IRExpr* getYMMRegLane32 ( UInt ymmreg, Int laneno )
+{
+ return IRExpr_Get( ymmGuestRegLane32offset(ymmreg,laneno), Ity_I32 );
+}
+
+static void putYMMReg ( UInt ymmreg, IRExpr* e )
+{
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_V256);
+ stmt( IRStmt_Put( ymmGuestRegOffset(ymmreg), e ) );
+}
+
+static void putYMMRegLane128 ( UInt ymmreg, Int laneno, IRExpr* e )
+{
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_V128);
+ stmt( IRStmt_Put( ymmGuestRegLane128offset(ymmreg,laneno), e ) );
+}
+
+static void putYMMRegLane64F ( UInt ymmreg, Int laneno, IRExpr* e )
+{
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F64);
+ stmt( IRStmt_Put( ymmGuestRegLane64offset(ymmreg,laneno), e ) );
+}
+
+static void putYMMRegLane64 ( UInt ymmreg, Int laneno, IRExpr* e )
+{
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64);
+ stmt( IRStmt_Put( ymmGuestRegLane64offset(ymmreg,laneno), e ) );
+}
+
+static void putYMMRegLane32F ( UInt ymmreg, Int laneno, IRExpr* e )
+{
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F32);
+ stmt( IRStmt_Put( ymmGuestRegLane32offset(ymmreg,laneno), e ) );
+}
+
+static void putYMMRegLane32 ( UInt ymmreg, Int laneno, IRExpr* e )
+{
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I32);
+ stmt( IRStmt_Put( ymmGuestRegLane32offset(ymmreg,laneno), e ) );
}
static IRExpr* mkV128 ( UShort mask )
@@ -1455,6 +1544,13 @@
return IRExpr_Const(IRConst_V128(mask));
}
+/* Write the low half of a YMM reg and zero out the upper half. */
+static void putYMMRegLoAndZU ( UInt ymmreg, IRExpr* e )
+{
+ putYMMRegLane128( ymmreg, 0, e );
+ putYMMRegLane128( ymmreg, 1, mkV128(0) );
+}
+
static IRExpr* mkAnd1 ( IRExpr* x, IRExpr* y )
{
vassert(typeOfIRExpr(irsb->tyenv,x) == Ity_I1);
@@ -1490,7 +1586,8 @@
binop( mkSizedOp(tyE,Iop_CasCmpNE8),
mkexpr(oldTmp), mkexpr(expTmp) ),
Ijk_Boring, /*Ijk_NoRedir*/
- IRConst_U64( restart_point )
+ IRConst_U64( restart_point ),
+ OFFB_RIP
));
}
@@ -2065,41 +2162,71 @@
}
}
+static HChar* nameYMMReg ( Int ymmreg )
+{
+ static HChar* ymm_names[16]
+ = { "%ymm0", "%ymm1", "%ymm2", "%ymm3",
+ "%ymm4", "%ymm5", "%ymm6", "%ymm7",
+ "%ymm8", "%ymm9", "%ymm10", "%ymm11",
+ "%ymm12", "%ymm13", "%ymm14", "%ymm15" };
+ if (ymmreg < 0 || ymmreg > 15) vpanic("nameYMMReg(amd64)");
+ return ymm_names[ymmreg];
+}
+
/*------------------------------------------------------------*/
/*--- JMP helpers ---*/
/*------------------------------------------------------------*/
-static void jmp_lit( IRJumpKind kind, Addr64 d64 )
+static void jmp_lit( /*MOD*/DisResult* dres,
+ IRJumpKind kind, Addr64 d64 )
{
- irsb->next = mkU64(d64);
- irsb->jumpkind = kind;
+ vassert(dres->whatNext == Dis_Continue);
+ vassert(dres->len == 0);
+ vassert(dres->continueAt == 0);
+ vassert(dres->jk_StopHere == Ijk_INVALID);
+ dres->whatNext = Dis_StopHere;
+ dres->jk_StopHere = kind;
+ stmt( IRStmt_Put( OFFB_RIP, mkU64(d64) ) );
}
-static void jmp_treg( IRJumpKind kind, IRTemp t )
+static void jmp_treg( /*MOD*/DisResult* dres,
+ IRJumpKind kind, IRTemp t )
{
- irsb->next = mkexpr(t);
- irsb->jumpkind = kind;
+ vassert(dres->whatNext == Dis_Continue);
+ vassert(dres->len == 0);
+ vassert(dres->continueAt == 0);
+ vassert(dres->jk_StopHere == Ijk_INVALID);
+ dres->whatNext = Dis_StopHere;
+ dres->jk_StopHere = kind;
+ stmt( IRStmt_Put( OFFB_RIP, mkexpr(t) ) );
}
static
-void jcc_01 ( AMD64Condcode cond, Addr64 d64_false, Addr64 d64_true )
+void jcc_01 ( /*MOD*/DisResult* dres,
+ AMD64Condcode cond, Addr64 d64_false, Addr64 d64_true )
{
Bool invert;
AMD64Condcode condPos;
+ vassert(dres->whatNext == Dis_Continue);
+ vassert(dres->len == 0);
+ vassert(dres->continueAt == 0);
+ vassert(dres->jk_StopHere == Ijk_INVALID);
+ dres->whatNext = Dis_StopHere;
+ dres->jk_StopHere = Ijk_Boring;
condPos = positiveIse_AMD64Condcode ( cond, &invert );
if (invert) {
stmt( IRStmt_Exit( mk_amd64g_calculate_condition(condPos),
Ijk_Boring,
- IRConst_U64(d64_false) ) );
- irsb->next = mkU64(d64_true);
- irsb->jumpkind = Ijk_Boring;
+ IRConst_U64(d64_false),
+ OFFB_RIP ) );
+ stmt( IRStmt_Put( OFFB_RIP, mkU64(d64_true) ) );
} else {
stmt( IRStmt_Exit( mk_amd64g_calculate_condition(condPos),
Ijk_Boring,
- IRConst_U64(d64_true) ) );
- irsb->next = mkU64(d64_false);
- irsb->jumpkind = Ijk_Boring;
+ IRConst_U64(d64_true),
+ OFFB_RIP ) );
+ stmt( IRStmt_Put( OFFB_RIP, mkU64(d64_false) ) );
}
}
@@ -3945,7 +4072,7 @@
static
ULong dis_Grp5 ( VexAbiInfo* vbi,
Prefix pfx, Int sz, Long delta,
- DisResult* dres, Bool* decode_OK )
+ /*MOD*/DisResult* dres, /*OUT*/Bool* decode_OK )
{
Int len;
UChar modrm;
@@ -3988,8 +4115,8 @@
putIReg64(R_RSP, mkexpr(t2));
storeLE( mkexpr(t2), mkU64(guest_RIP_bbstart+delta+1));
make_redzone_AbiHint(vbi, t2, t3/*nia*/, "call-Ev(reg)");
- jmp_treg(Ijk_Call,t3);
- dres->whatNext = Dis_StopHere;
+ jmp_treg(dres, Ijk_Call, t3);
+ vassert(dres->whatNext == Dis_StopHere);
showSz = False;
break;
case 4: /* jmp Ev */
@@ -3998,8 +4125,8 @@
sz = 8;
t3 = newTemp(Ity_I64);
assign(t3, getIRegE(sz,pfx,modrm));
- jmp_treg(Ijk_Boring,t3);
- dres->whatNext = Dis_StopHere;
+ jmp_treg(dres, Ijk_Boring, t3);
+ vassert(dres->whatNext == Dis_StopHere);
showSz = False;
break;
default:
@@ -4052,8 +4179,8 @@
putIReg64(R_RSP, mkexpr(t2));
storeLE( mkexpr(t2), mkU64(guest_RIP_bbstart+delta+len));
make_redzone_AbiHint(vbi, t2, t3/*nia*/, "call-Ev(mem)");
- jmp_treg(Ijk_Call,t3);
- dres->whatNext = Dis_StopHere;
+ jmp_treg(dres, Ijk_Call, t3);
+ vassert(dres->whatNext == Dis_StopHere);
showSz = False;
break;
case 4: /* JMP Ev */
@@ -4062,8 +4189,8 @@
sz = 8;
t3 = newTemp(Ity_I64);
assign(t3, loadLE(Ity_I64,mkexpr(addr)));
- jmp_treg(Ijk_Boring,t3);
- dres->whatNext = Dis_StopHere;
+ jmp_treg(dres, Ijk_Boring, t3);
+ vassert(dres->whatNext == Dis_StopHere);
showSz = False;
break;
case 6: /* PUSH Ev */
@@ -4266,7 +4393,8 @@
the insn is the last one in the basic block, and so emit a jump to
the next insn, rather than just falling through. */
static
-void dis_REP_op ( AMD64Condcode cond,
+void dis_REP_op ( /*MOD*/DisResult* dres,
+ AMD64Condcode cond,
void (*dis_OP)(Int, IRTemp, Prefix),
Int sz, Addr64 rip, Addr64 rip_next, HChar* name,
Prefix pfx )
@@ -4289,7 +4417,8 @@
cmp = binop(Iop_CmpEQ64, mkexpr(tc), mkU64(0));
}
- stmt( IRStmt_Exit( cmp, Ijk_Boring, IRConst_U64(rip_next) ) );
+ stmt( IRStmt_Exit( cmp, Ijk_Boring,
+ IRConst_U64(rip_next), OFFB_RIP ) );
if (haveASO(pfx))
putIReg32(R_RCX, binop(Iop_Sub32, mkexpr(tc), mkU32(1)) );
@@ -4300,12 +4429,15 @@
dis_OP (sz, t_inc, pfx);
if (cond == AMD64CondAlways) {
- jmp_lit(Ijk_Boring,rip);
+ jmp_lit(dres, Ijk_Boring, rip);
+ vassert(dres->whatNext == Dis_StopHere);
} else {
stmt( IRStmt_Exit( mk_amd64g_calculate_condition(cond),
Ijk_Boring,
- IRConst_U64(rip) ) );
- jmp_lit(Ijk_Boring,rip_next);
+ IRConst_U64(rip),
+ OFFB_RIP ) );
+ jmp_lit(dres, Ijk_Boring, rip_next);
+ vassert(dres->whatNext == Dis_StopHere);
}
DIP("%s%c\n", name, nameISize(sz));
}
@@ -4627,7 +4759,7 @@
IRRegArray* descr;
vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_I8);
descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
- stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
+ stmt( IRStmt_PutI( mkIRPutI(descr, get_ftop(), i, value) ) );
}
/* Given i, generate an expression yielding 'ST_TAG(i)'. This will be
@@ -4651,7 +4783,7 @@
IRRegArray* descr;
vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_F64);
descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 );
- stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
+ stmt( IRStmt_PutI( mkIRPutI(descr, get_ftop(), i, value) ) );
/* Mark the register as in-use. */
put_ST_TAG(i, mkU8(1));
}
@@ -4911,36 +5043,42 @@
fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64, False );
break;
-//.. case 2: /* FCOM single-real */
-//.. DIP("fcoms %s\n", dis_buf);
-//.. /* This forces C1 to zero, which isn't right. */
-//.. put_C3210(
-//.. binop( Iop_And32,
-//.. binop(Iop_Shl32,
-//.. binop(Iop_CmpF64,
-//.. get_ST(0),
-//.. unop(Iop_F32toF64,
-//.. loadLE(Ity_F32,mkexpr(addr)))),
-//.. mkU8(8)),
-//.. mkU32(0x4500)
-//.. ));
-//.. break;
-//..
-//.. case 3: /* FCOMP single-real */
-//.. DIP("fcomps %s\n", dis_buf);
-//.. /* This forces C1 to zero, which isn't right. */
-//.. put_C3210(
-//.. binop( Iop_And32,
-//.. binop(Iop_Shl32,
-//.. binop(Iop_CmpF64,
-//.. get_ST(0),
-//.. unop(Iop_F32toF64,
-//.. loadLE(Ity_F32,mkexpr(addr)))),
-//.. mkU8(8)),
-//.. mkU32(0x4500)
-//.. ));
-//.. fp_pop();
-//.. break;
+ case 2: /* FCOM single-real */
+ DIP("fcoms %s\n", dis_buf);
+ /* This forces C1 to zero, which isn't right. */
+ /* The AMD documentation suggests that forcing C1 to
+ zero is correct (Eliot Moss) */
+ put_C3210(
+ unop( Iop_32Uto64,
+ binop( Iop_And32,
+ binop(Iop_Shl32,
+ binop(Iop_CmpF64,
+ get_ST(0),
+ unop(Iop_F32toF64,
+ loadLE(Ity_F32,mkexpr(addr)))),
+ mkU8(8)),
+ mkU32(0x4500)
+ )));
+ break;
+
+ case 3: /* FCOMP single-real */
+ /* The AMD documentation suggests that forcing C1 to
+ zero is correct (Eliot Moss) */
+ DIP("fcomps %s\n", dis_buf);
+ /* This forces C1 to zero, which isn't right. */
+ put_C3210(
+ unop( Iop_32Uto64,
+ binop( Iop_And32,
+ binop(Iop_Shl32,
+ binop(Iop_CmpF64,
+ get_ST(0),
+ unop(Iop_F32toF64,
+ loadLE(Ity_F32,mkexpr(addr)))),
+ mkU8(8)),
+ mkU32(0x4500)
+ )));
+ fp_pop();
+ break;
case 4: /* FSUB single-real */
fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64, False );
@@ -5080,6 +5218,7 @@
/* declare we're writing guest state */
d->nFxState = 4;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Write;
d->fxState[0].offset = OFFB_FTOP;
@@ -5109,7 +5248,8 @@
IRStmt_Exit(
binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
Ijk_EmWarn,
- IRConst_U64( guest_RIP_bbstart+delta )
+ IRConst_U64( guest_RIP_bbstart+delta ),
+ OFFB_RIP
)
);
@@ -5151,7 +5291,8 @@
IRStmt_Exit(
binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
Ijk_EmWarn,
- IRConst_U64( guest_RIP_bbstart+delta )
+ IRConst_U64( guest_RIP_bbstart+delta ),
+ OFFB_RIP
)
);
break;
@@ -5174,6 +5315,7 @@
/* declare we're reading guest state */
d->nFxState = 4;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Read;
d->fxState[0].offset = OFFB_FTOP;
@@ -5831,6 +5973,7 @@
/* declare we're writing guest state */
d->nFxState = 5;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Write;
d->fxState[0].offset = OFFB_FTOP;
@@ -6017,108 +6160,152 @@
fp_pop();
break;
-//.. case 4: { /* FRSTOR m108 */
-//.. /* Uses dirty helper:
-//.. VexEmWarn x86g_do_FRSTOR ( VexGuestX86State*, Addr32 ) */
-//.. IRTemp ew = newTemp(Ity_I32);
-//.. IRDirty* d = unsafeIRDirty_0_N (
-//.. 0/*regparms*/,
-//.. "x86g_dirtyhelper_FRSTOR",
-//.. &x86g_dirtyhelper_FRSTOR,
-//.. mkIRExprVec_1( mkexpr(addr) )
-//.. );
-//.. d->needsBBP = True;
-//.. d->tmp = ew;
-//.. /* declare we're reading memory */
-//.. d->mFx = Ifx_Read;
-//.. d->mAddr = mkexpr(addr);
-//.. d->mSize = 108;
-//..
-//.. /* declare we're writing guest state */
-//.. d->nFxState = 5;
-//..
-//.. d->fxState[0].fx = Ifx_Write;
-//.. d->fxState[0].offset = OFFB_FTOP;
-//.. d->fxState[0].size = sizeof(UInt);
-//..
-//.. d->fxState[1].fx = Ifx_Write;
-//.. d->fxState[1].offset = OFFB_FPREGS;
-//.. d->fxState[1].size = 8 * sizeof(ULong);
-//..
-//.. d->fxState[2].fx = Ifx_Write;
-//.. d->fxState[2].offset = OFFB_FPTAGS;
-//.. d->fxState[2].size = 8 * sizeof(UChar);
-//..
-//.. d->fxState[3].fx = Ifx_Write;
-//.. d->fxState[3].offset = OFFB_FPROUND;
-//.. d->fxState[3].size = sizeof(UInt);
-//..
-//.. d->fxState[4].fx = Ifx_Write;
-//.. d->fxState[4].offset = OFFB_FC3210;
-//.. d->fxState[4].size = sizeof(UInt);
-//..
-//.. stmt( IRStmt_Dirty(d) );
-//..
-//.. /* ew contains any emulation warning we may need to
-//.. issue. If needed, side-exit to the next insn,
-//.. reporting the warning, so that Valgrind's dispatcher
-//.. sees the warning. */
-//.. put_emwarn( mkexpr(ew) );
-//.. stmt(
-//.. IRStmt_Exit(
-//.. binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
-//.. Ijk_EmWarn,
-//.. IRConst_U32( ((Addr32)guest_eip_bbstart)+delta)
-//.. )
-//.. );
-//..
-//.. DIP("frstor %s\n", dis_buf);
-//.. break;
-//.. }
-//..
-//.. case 6: { /* FNSAVE m108 */
-//.. /* Uses dirty helper:
-//.. void x86g_do_FSAVE ( VexGuestX86State*, UInt ) */
-//.. IRDirty* d = unsafeIRDirty_0_N (
-//.. 0/*regparms*/,
-//.. "x86g_dirtyhelper_FSAVE",
-//.. &x86g_dirtyhelper_FSAVE,
-//.. mkIRExprVec_1( mkexpr(addr) )
-//.. );
-//.. d->needsBBP = True;
-//.. /* declare we're writing memory */
-//.. d->mFx = Ifx_Write;
-//.. d->mAddr = mkexpr(addr);
-//.. d->mSize = 108;
-//..
-//.. /* declare we're reading guest state */
-//.. d->nFxState = 5;
-//..
-//.. d->fxState[0].fx = Ifx_Read;
-//.. d->fxState[0].offset = OFFB_FTOP;
-//.. d->fxState[0].size = sizeof(UInt);
-//..
-//.. d->fxState[1].fx = Ifx_Read;
-//.. d->fxState[1].offset = OFFB_FPREGS;
-//.. d->fxState[1].size = 8 * sizeof(ULong);
-//..
-//.. d->fxState[2].fx = Ifx_Read;
-//.. d->fxState[2].offset = OFFB_FPTAGS;
-//.. d->fxState[2].size = 8 * sizeof(UChar);
-//..
-//.. d->fxState[3].fx = Ifx_Read;
-//.. d->fxState[3].offset = OFFB_FPROUND;
-//.. d->fxState[3].size = sizeof(UInt);
-//..
-//.. d->fxState[4].fx = Ifx_Read;
-//.. d->fxState[4].offset = OFFB_FC3210;
-//.. d->fxState[4].size = sizeof(UInt);
-//..
-//.. stmt( IRStmt_Dirty(d) );
-//..
-//.. DIP("fnsave %s\n", dis_buf);
-//.. break;
-//.. }
+ case 4: { /* FRSTOR m94/m108 */
+ IRTemp ew = newTemp(Ity_I32);
+ IRTemp w64 = newTemp(Ity_I64);
+ IRDirty* d;
+ if ( have66(pfx) ) {
+ /* Uses dirty helper:
+ VexEmWarn amd64g_dirtyhelper_FRSTORS
+ ( VexGuestAMD64State*, HWord ) */
+ d = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_FRSTORS",
+ &amd64g_dirtyhelper_FRSTORS,
+ mkIRExprVec_1( mkexpr(addr) )
+ );
+ d->mSize = 94;
+ } else {
+ /* Uses dirty helper:
+ VexEmWarn amd64g_dirtyhelper_FRSTOR
+ ( VexGuestAMD64State*, HWord ) */
+ d = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_FRSTOR",
+ &amd64g_dirtyhelper_FRSTOR,
+ mkIRExprVec_1( mkexpr(addr) )
+ );
+ d->mSize = 108;
+ }
+
+ d->needsBBP = True;
+ d->tmp = w64;
+ /* declare we're reading memory */
+ d->mFx = Ifx_Read;
+ d->mAddr = mkexpr(addr);
+ /* d->mSize set above */
+
+ /* declare we're writing guest state */
+ d->nFxState = 5;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
+
+ d->fxState[0].fx = Ifx_Write;
+ d->fxState[0].offset = OFFB_FTOP;
+ d->fxState[0].size = sizeof(UInt);
+
+ d->fxState[1].fx = Ifx_Write;
+ d->fxState[1].offset = OFFB_FPREGS;
+ d->fxState[1].size = 8 * sizeof(ULong);
+
+ d->fxState[2].fx = Ifx_Write;
+ d->fxState[2].offset = OFFB_FPTAGS;
+ d->fxState[2].size = 8 * sizeof(UChar);
+
+ d->fxState[3].fx = Ifx_Write;
+ d->fxState[3].offset = OFFB_FPROUND;
+ d->fxState[3].size = sizeof(ULong);
+
+ d->fxState[4].fx = Ifx_Write;
+ d->fxState[4].offset = OFFB_FC3210;
+ d->fxState[4].size = sizeof(ULong);
+
+ stmt( IRStmt_Dirty(d) );
+
+ /* ew contains any emulation warning we may need to
+ issue. If needed, side-exit to the next insn,
+ reporting the warning, so that Valgrind's dispatcher
+ sees the warning. */
+ assign(ew, unop(Iop_64to32,mkexpr(w64)) );
+ put_emwarn( mkexpr(ew) );
+ stmt(
+ IRStmt_Exit(
+ binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
+ Ijk_EmWarn,
+ IRConst_U64( guest_RIP_bbstart+delta ),
+ OFFB_RIP
+ )
+ );
+
+ if ( have66(pfx) ) {
+ DIP("frstors %s\n", dis_buf);
+ } else {
+ DIP("frstor %s\n", dis_buf);
+ }
+ break;
+ }
+
+ case 6: { /* FNSAVE m94/m108 */
+ IRDirty *d;
+ if ( have66(pfx) ) {
+ /* Uses dirty helper:
+ void amd64g_dirtyhelper_FNSAVES ( VexGuestX86State*, HWord ) */
+ d = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_FNSAVES",
+ &amd64g_dirtyhelper_FNSAVES,
+ mkIRExprVec_1( mkexpr(addr) )
+ );
+ d->mSize = 94;
+ } else {
+ /* Uses dirty helper:
+ void amd64g_dirtyhelper_FNSAVE ( VexGuestX86State*, HWord ) */
+ d = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_FNSAVE",
+ &amd64g_dirtyhelper_FNSAVE,
+ mkIRExprVec_1( mkexpr(addr) )
+ );
+ d->mSize = 108;
+ }
+ d->needsBBP = True;
+ /* declare we're writing memory */
+ d->mFx = Ifx_Write;
+ d->mAddr = mkexpr(addr);
+ /* d->mSize set above */
+
+ /* declare we're reading guest state */
+ d->nFxState = 5;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
+
+ d->fxState[0].fx = Ifx_Read;
+ d->fxState[0].offset = OFFB_FTOP;
+ d->fxState[0].size = sizeof(UInt);
+
+ d->fxState[1].fx = Ifx_Read;
+ d->fxState[1].offset = OFFB_FPREGS;
+ d->fxState[1].size = 8 * sizeof(ULong);
+
+ d->fxState[2].fx = Ifx_Read;
+ d->fxState[2].offset = OFFB_FPTAGS;
+ d->fxState[2].size = 8 * sizeof(UChar);
+
+ d->fxState[3].fx = Ifx_Read;
+ d->fxState[3].offset = OFFB_FPROUND;
+ d->fxState[3].size = sizeof(ULong);
+
+ d->fxState[4].fx = Ifx_Read;
+ d->fxState[4].offset = OFFB_FC3210;
+ d->fxState[4].size = sizeof(ULong);
+
+ stmt( IRStmt_Dirty(d) );
+
+ if ( have66(pfx) ) {
+ DIP("fnsaves %s\n", dis_buf);
+ } else {
+ DIP("fnsave %s\n", dis_buf);
+ }
+ break;
+ }
case 7: { /* FNSTSW m16 */
IRExpr* sw = get_FPU_sw();
@@ -6467,7 +6654,7 @@
IRExpr* tag1 = mkU8(1);
put_ftop(zero);
for (i = 0; i < 8; i++)
- stmt( IRStmt_PutI( descr, zero, i, tag1 ) );
+ stmt( IRStmt_PutI( mkIRPutI(descr, zero, i, tag1) ) );
}
static void do_EMMS_preamble ( void )
@@ -6478,7 +6665,7 @@
IRExpr* tag0 = mkU8(0);
put_ftop(zero);
for (i = 0; i < 8; i++)
- stmt( IRStmt_PutI( descr, zero, i, tag0 ) );
+ stmt( IRStmt_PutI( mkIRPutI(descr, zero, i, tag0) ) );
}
@@ -6917,9 +7104,11 @@
goto mmx_decode_failure;
modrm = getUChar(delta);
if (epartIsReg(modrm)) {
- /* Fall through. The assembler doesn't appear to generate
- these. */
- goto mmx_decode_failure;
+ delta++;
+ putMMXReg( eregLO3ofRM(modrm), getMMXReg(gregLO3ofRM(modrm)) );
+ DIP("movq %s, %s\n",
+ nameMMXReg(gregLO3ofRM(modrm)),
+ nameMMXReg(eregLO3ofRM(modrm)));
} else {
IRTemp addr = disAMode( &len, vbi, pfx, delta, dis_buf, 0 );
delta += len;
@@ -8081,7 +8270,7 @@
//.. }
static
-void dis_ret ( VexAbiInfo* vbi, ULong d64 )
+void dis_ret ( /*MOD*/DisResult* dres, VexAbiInfo* vbi, ULong d64 )
{
IRTemp t1 = newTemp(Ity_I64);
IRTemp t2 = newTemp(Ity_I64);
@@ -8091,7 +8280,8 @@
assign(t3, binop(Iop_Add64, mkexpr(t1), mkU64(8+d64)));
putIReg64(R_RSP, mkexpr(t3));
make_redzone_AbiHint(vbi, t3, t2/*nia*/, "ret");
- jmp_treg(Ijk_Ret,t2);
+ jmp_treg(dres, Ijk_Ret, t2);
+ vassert(dres->whatNext == Dis_StopHere);
}
@@ -8388,76 +8578,150 @@
}
-/* Helper for doing SSE FP comparisons. */
-
-static void findSSECmpOp ( Bool* needNot, IROp* op,
- Int imm8, Bool all_lanes, Int sz )
+/* Helper for doing SSE FP comparisons. False return ==> unhandled.
+ This is all a bit of a kludge in that it ignores the subtleties of
+ ordered-vs-unordered and signalling-vs-nonsignalling in the Intel
+ spec. */
+static Bool findSSECmpOp ( /*OUT*/Bool* preSwapP,
+ /*OUT*/IROp* opP,
+ /*OUT*/Bool* postNotP,
+ UInt imm8, Bool all_lanes, Int sz )
{
- imm8 &= 7;
- *needNot = False;
- *op = Iop_INVALID;
- if (imm8 >= 4) {
- *needNot = True;
- imm8 -= 4;
+ if (imm8 >= 32) return False;
+
+ /* First, compute a (preSwap, op, postNot) triple from
+ the supplied imm8. */
+ Bool pre = False;
+ IROp op = Iop_INVALID;
+ Bool not = False;
+
+# define XXX(_pre, _op, _not) { pre = _pre; op = _op; not = _not; }
+ // If you add a case here, add a corresponding test for both VCMPSD_128
+ // and VCMPSS_128 in avx-1.c.
+ switch (imm8) {
+ // "O" = ordered, "U" = unordered
+ // "Q" = non-signalling (quiet), "S" = signalling
+ //
+ // swap operands?
+ // |
+ // | cmp op invert after?
+ // | | |
+ // v v v
+ case 0x0: XXX(False, Iop_CmpEQ32Fx4, False); break; // EQ_OQ
+ case 0x1: XXX(False, Iop_CmpLT32Fx4, False); break; // LT_OS
+ case 0x2: XXX(False, Iop_CmpLE32Fx4, False); break; // LE_OS
+ case 0x3: XXX(False, Iop_CmpUN32Fx4, False); break; // UNORD_Q
+ case 0x4: XXX(False, Iop_CmpEQ32Fx4, True); break; // NEQ_UQ
+ case 0x5: XXX(False, Iop_CmpLT32Fx4, True); break; // NLT_US
+ case 0x6: XXX(False, Iop_CmpLE32Fx4, True); break; // NLE_US
+ case 0x7: XXX(False, Iop_CmpUN32Fx4, True); break; // ORD_Q
+ // 0x8 EQ_UQ
+ case 0x9: XXX(True, Iop_CmpLE32Fx4, True); break; // NGE_US
+ /* "Enhanced Comparison Predicate[s] for VEX-Encoded [insns] */
+ case 0xA: XXX(True, Iop_CmpLT32Fx4, True); break; // NGT_US
+ // 0xB FALSE_OQ
+ // 0xC: this isn't really right because it returns all-1s when
+ // either operand is a NaN, and it should return all-0s.
+ case 0xC: XXX(False, Iop_CmpEQ32Fx4, True); break; // NEQ_OQ
+ case 0xD: XXX(True, Iop_CmpLE32Fx4, False); break; // GE_OS
+ case 0xE: XXX(True, Iop_CmpLT32Fx4, False); break; // GT_OS
+ // 0xF TRUE_UQ
+ // 0x10 EQ_OS
+ case 0x11: XXX(False, Iop_CmpLT32Fx4, False); break; // LT_OQ
+ case 0x12: XXX(False, Iop_CmpLE32Fx4, False); break; // LE_OQ
+ // 0x13 UNORD_S
+ // 0x14 NEQ_US
+ // 0x15 NLT_UQ
+ case 0x16: XXX(False, Iop_CmpLE32Fx4, True); break; // NLE_UQ
+ // 0x17 ORD_S
+ // 0x18 EQ_US
+ // 0x19 NGE_UQ
+ // 0x1A NGT_UQ
+ // 0x1B FALSE_OS
+ // 0x1C NEQ_OS
+ // 0x1D GE_OQ
+ case 0x1E: XXX(True, Iop_CmpLT32Fx4, False); break; // GT_OQ
+ // 0x1F TRUE_US
+ /* Don't forget to add test cases to VCMPSS_128_<imm8> in
+ avx-1.c if new cases turn up. */
+ default: break;
+ }
+# undef XXX
+ if (op == Iop_INVALID) return False;
+
+ /* Now convert the op into one with the same arithmetic but that is
+ correct for the width and laneage requirements. */
+
+ /**/ if (sz == 4 && all_lanes) {
+ switch (op) {
+ case Iop_CmpEQ32Fx4: op = Iop_CmpEQ32Fx4; break;
+ case Iop_CmpLT32Fx4: op = Iop_CmpLT32Fx4; break;
+ case Iop_CmpLE32Fx4: op = Iop_CmpLE32Fx4; break;
+ case Iop_CmpUN32Fx4: op = Iop_CmpUN32Fx4; break;
+ default: vassert(0);
+ }
+ }
+ else if (sz == 4 && !all_lanes) {
+ switch (op) {
+ case Iop_CmpEQ32Fx4: op = Iop_CmpEQ32F0x4; break;
+ case Iop_CmpLT32Fx4: op = Iop_CmpLT32F0x4; break;
+ case Iop_CmpLE32Fx4: op = Iop_CmpLE32F0x4; break;
+ case Iop_CmpUN32Fx4: op = Iop_CmpUN32F0x4; break;
+ default: vassert(0);
+ }
+ }
+ else if (sz == 8 && all_lanes) {
+ switch (op) {
+ case Iop_CmpEQ32Fx4: op = Iop_CmpEQ64Fx2; break;
+ case Iop_CmpLT32Fx4: op = Iop_CmpLT64Fx2; break;
+ case Iop_CmpLE32Fx4: op = Iop_CmpLE64Fx2; break;
+ case Iop_CmpUN32Fx4: op = Iop_CmpUN64Fx2; break;
+ default: vassert(0);
+ }
+ }
+ else if (sz == 8 && !all_lanes) {
+ switch (op) {
+ case Iop_CmpEQ32Fx4: op = Iop_CmpEQ64F0x2; break;
+ case Iop_CmpLT32Fx4: op = Iop_CmpLT64F0x2; break;
+ case Iop_CmpLE32Fx4: op = Iop_CmpLE64F0x2; break;
+ case Iop_CmpUN32Fx4: op = Iop_CmpUN64F0x2; break;
+ default: vassert(0);
+ }
+ }
+ else {
+ vpanic("findSSECmpOp(amd64,guest)");
}
- if (sz == 4 && all_lanes) {
- switch (imm8) {
- case 0: *op = Iop_CmpEQ32Fx4; return;
- case 1: *op = Iop_CmpLT32Fx4; return;
- case 2: *op = Iop_CmpLE32Fx4; return;
- case 3: *op = Iop_CmpUN32Fx4; return;
- default: break;
- }
- }
- if (sz == 4 && !all_lanes) {
- switch (imm8) {
- case 0: *op = Iop_CmpEQ32F0x4; return;
- case 1: *op = Iop_CmpLT32F0x4; return;
- case 2: *op = Iop_CmpLE32F0x4; return;
- case 3: *op = Iop_CmpUN32F0x4; return;
- default: break;
- }
- }
- if (sz == 8 && all_lanes) {
- switch (imm8) {
- case 0: *op = Iop_CmpEQ64Fx2; return;
- case 1: *op = Iop_CmpLT64Fx2; return;
- case 2: *op = Iop_CmpLE64Fx2; return;
- case 3: *op = Iop_CmpUN64Fx2; return;
- default: break;
- }
- }
- if (sz == 8 && !all_lanes) {
- switch (imm8) {
- case 0: *op = Iop_CmpEQ64F0x2; return;
- case 1: *op = Iop_CmpLT64F0x2; return;
- case 2: *op = Iop_CmpLE64F0x2; return;
- case 3: *op = Iop_CmpUN64F0x2; return;
- default: break;
- }
- }
- vpanic("findSSECmpOp(amd64,guest)");
+ *preSwapP = pre; *opP = op; *postNotP = not;
+ return True;
}
-/* Handles SSE 32F/64F comparisons. */
-static ULong dis_SSEcmp_E_to_G ( VexAbiInfo* vbi,
+/* Handles SSE 32F/64F comparisons. It can fail, in which case it
+ returns the original delta to indicate failure. */
+
+static Long dis_SSE_cmp_E_to_G ( VexAbiInfo* vbi,
Prefix pfx, Long delta,
HChar* opname, Bool all_lanes, Int sz )
{
+ Long delta0 = delta;
HChar dis_buf[50];
- Int alen, imm8;
+ Int alen;
+ UInt imm8;
IRTemp addr;
- Bool needNot = False;
+ Bool preSwap = False;
IROp op = Iop_INVALID;
+ Bool postNot = False;
IRTemp plain = newTemp(Ity_V128);
UChar rm = getUChar(delta);
UShort mask = 0;
vassert(sz == 4 || sz == 8);
if (epartIsReg(rm)) {
imm8 = getUChar(delta+1);
- findSSECmpOp(&needNot, &op, imm8, all_lanes, sz);
+ if (imm8 >= 8) return delta0; /* FAIL */
+ Bool ok = findSSECmpOp(&preSwap, &op, &postNot, imm8, all_lanes, sz);
+ if (!ok) return delta0; /* FAIL */
+ vassert(!preSwap); /* never needed for imm8 < 8 */
assign( plain, binop(op, getXMMReg(gregOfRexRM(pfx,rm)),
getXMMReg(eregOfRexRM(pfx,rm))) );
delta += 2;
@@ -8468,14 +8732,20 @@
} else {
addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
imm8 = getUChar(delta+alen);
- findSSECmpOp(&needNot, &op, imm8, all_lanes, sz);
+ if (imm8 >= 8) return delta0; /* FAIL */
+ Bool ok = findSSECmpOp(&preSwap, &op, &postNot, imm8, all_lanes, sz);
+ if (!ok) return delta0; /* FAIL */
+ vassert(!preSwap); /* never needed for imm8 < 8 */
assign( plain,
binop(
op,
getXMMReg(gregOfRexRM(pfx,rm)),
- all_lanes ? loadLE(Ity_V128, mkexpr(addr))
- : sz == 8 ? unop( Iop_64UtoV128, loadLE(Ity_I64, mkexpr(addr)))
- : /*sz==4*/ unop( Iop_32UtoV128, loadLE(Ity_I32, mkexpr(addr)))
+ all_lanes
+ ? loadLE(Ity_V128, mkexpr(addr))
+ : sz == 8
+ ? unop( Iop_64UtoV128, loadLE(Ity_I64, mkexpr(addr)))
+ : /*sz==4*/
+ unop( Iop_32UtoV128, loadLE(Ity_I32, mkexpr(addr)))
)
);
delta += alen+1;
@@ -8485,12 +8755,12 @@
nameXMMReg(gregOfRexRM(pfx,rm)) );
}
- if (needNot && all_lanes) {
+ if (postNot && all_lanes) {
putXMMReg( gregOfRexRM(pfx,rm),
unop(Iop_NotV128, mkexpr(plain)) );
}
else
- if (needNot && !all_lanes) {
+ if (postNot && !all_lanes) {
mask = toUShort(sz==4 ? 0x000F : 0x00FF);
putXMMReg( gregOfRexRM(pfx,rm),
binop(Iop_XorV128, mkexpr(plain), mkV128(mask)) );
@@ -8517,24 +8787,24 @@
UChar rm = getUChar(delta);
IRTemp g0 = newTemp(Ity_V128);
IRTemp g1 = newTemp(Ity_V128);
- IRTemp amt = newTemp(Ity_I32);
+ IRTemp amt = newTemp(Ity_I64);
IRTemp amt8 = newTemp(Ity_I8);
if (epartIsReg(rm)) {
- assign( amt, getXMMRegLane32(eregOfRexRM(pfx,rm), 0) );
+ assign( amt, getXMMRegLane64(eregOfRexRM(pfx,rm), 0) );
DIP("%s %s,%s\n", opname,
nameXMMReg(eregOfRexRM(pfx,rm)),
nameXMMReg(gregOfRexRM(pfx,rm)) );
delta++;
} else {
addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- assign( amt, loadLE(Ity_I32, mkexpr(addr)) );
+ assign( amt, loadLE(Ity_I64, mkexpr(addr)) );
DIP("%s %s,%s\n", opname,
dis_buf,
nameXMMReg(gregOfRexRM(pfx,rm)) );
delta += alen;
}
assign( g0, getXMMReg(gregOfRexRM(pfx,rm)) );
- assign( amt8, unop(Iop_32to8, mkexpr(amt)) );
+ assign( amt8, unop(Iop_64to8, mkexpr(amt)) );
shl = shr = sar = False;
size = 0;
@@ -8555,7 +8825,7 @@
g1,
IRExpr_Mux0X(
unop(Iop_1Uto8,
- binop(Iop_CmpLT64U, unop(Iop_32Uto64,mkexpr(amt)), mkU64(size))),
+ binop(Iop_CmpLT64U, mkexpr(amt), mkU64(size))),
mkV128(0x0000),
binop(op, mkexpr(g0), mkexpr(amt8))
)
@@ -8566,7 +8836,7 @@
g1,
IRExpr_Mux0X(
unop(Iop_1Uto8,
- binop(Iop_CmpLT64U, unop(Iop_32Uto64,mkexpr(amt)), mkU64(size))),
+ binop(Iop_CmpLT64U, mkexpr(amt), mkU64(size))),
binop(op, mkexpr(g0), mkU8(size-1)),
binop(op, mkexpr(g0), mkexpr(amt8))
)
@@ -8653,12 +8923,12 @@
unop(Iop_32Uto64,sseround) ) );
}
-/* Break a 128-bit value up into four 32-bit ints. */
+/* Break a V128-bit value up into four 32-bit ints. */
-static void breakup128to32s ( IRTemp t128,
- /*OUTs*/
- IRTemp* t3, IRTemp* t2,
- IRTemp* t1, IRTemp* t0 )
+static void breakupV128to32s ( IRTemp t128,
+ /*OUTs*/
+ IRTemp* t3, IRTemp* t2,
+ IRTemp* t1, IRTemp* t0 )
{
IRTemp hi64 = newTemp(Ity_I64);
IRTemp lo64 = newTemp(Ity_I64);
@@ -8680,10 +8950,10 @@
assign( *t3, unop(Iop_64HIto32, mkexpr(hi64)) );
}
-/* Construct a 128-bit value from four 32-bit ints. */
+/* Construct a V128-bit value from four 32-bit ints. */
-static IRExpr* mk128from32s ( IRTemp t3, IRTemp t2,
- IRTemp t1, IRTemp t0 )
+static IRExpr* mkV128from32s ( IRTemp t3, IRTemp t2,
+ IRTemp t1, IRTemp t0 )
{
return
binop( Iop_64HLtoV128,
@@ -8731,6 +9001,100 @@
);
}
+/* Break a V256-bit value up into four 64-bit ints. */
+
+static void breakupV256to64s ( IRTemp t256,
+ /*OUTs*/
+ IRTemp* t3, IRTemp* t2,
+ IRTemp* t1, IRTemp* t0 )
+{
+ vassert(t0 && *t0 == IRTemp_INVALID);
+ vassert(t1 && *t1 == IRTemp_INVALID);
+ vassert(t2 && *t2 == IRTemp_INVALID);
+ vassert(t3 && *t3 == IRTemp_INVALID);
+ *t0 = newTemp(Ity_I64);
+ *t1 = newTemp(Ity_I64);
+ *t2 = newTemp(Ity_I64);
+ *t3 = newTemp(Ity_I64);
+ assign( *t0, unop(Iop_V256to64_0, mkexpr(t256)) );
+ assign( *t1, unop(Iop_V256to64_1, mkexpr(t256)) );
+ assign( *t2, unop(Iop_V256to64_2, mkexpr(t256)) );
+ assign( *t3, unop(Iop_V256to64_3, mkexpr(t256)) );
+}
+
+/* Break a V256-bit value up into two V128s. */
+
+static void breakupV256toV128s ( IRTemp t256,
+ /*OUTs*/
+ IRTemp* t1, IRTemp* t0 )
+{
+ vassert(t0 && *t0 == IRTemp_INVALID);
+ vassert(t1 && *t1 == IRTemp_INVALID);
+ *t0 = newTemp(Ity_V128);
+ *t1 = newTemp(Ity_V128);
+ assign(*t1, unop(Iop_V256toV128_1, mkexpr(t256)));
+ assign(*t0, unop(Iop_V256toV128_0, mkexpr(t256)));
+}
+
+/* Break a V256-bit value up into eight 32-bit ints. */
+
+static void breakupV256to32s ( IRTemp t256,
+ /*OUTs*/
+ IRTemp* t7, IRTemp* t6,
+ IRTemp* t5, IRTemp* t4,
+ IRTemp* t3, IRTemp* t2,
+ IRTemp* t1, IRTemp* t0 )
+{
+ IRTemp t128_1 = IRTemp_INVALID;
+ IRTemp t128_0 = IRTemp_INVALID;
+ breakupV256toV128s( t256, &t128_1, &t128_0 );
+ breakupV128to32s( t128_1, t7, t6, t5, t4 );
+ breakupV128to32s( t128_0, t3, t2, t1, t0 );
+}
+
+/* Break a V128-bit value up into two 64-bit ints. */
+
+static void breakupV128to64s ( IRTemp t128,
+ /*OUTs*/
+ IRTemp* t1, IRTemp* t0 )
+{
+ vassert(t0 && *t0 == IRTemp_INVALID);
+ vassert(t1 && *t1 == IRTemp_INVALID);
+ *t0 = newTemp(Ity_I64);
+ *t1 = newTemp(Ity_I64);
+ assign( *t0, unop(Iop_V128to64, mkexpr(t128)) );
+ assign( *t1, unop(Iop_V128HIto64, mkexpr(t128)) );
+}
+
+/* Construct a V256-bit value from eight 32-bit ints. */
+
+static IRExpr* mkV256from32s ( IRTemp t7, IRTemp t6,
+ IRTemp t5, IRTemp t4,
+ IRTemp t3, IRTemp t2,
+ IRTemp t1, IRTemp t0 )
+{
+ return
+ binop( Iop_V128HLtoV256,
+ binop( Iop_64HLtoV128,
+ binop(Iop_32HLto64, mkexpr(t7), mkexpr(t6)),
+ binop(Iop_32HLto64, mkexpr(t5), mkexpr(t4)) ),
+ binop( Iop_64HLtoV128,
+ binop(Iop_32HLto64, mkexpr(t3), mkexpr(t2)),
+ binop(Iop_32HLto64, mkexpr(t1), mkexpr(t0)) )
+ );
+}
+
+/* Construct a V256-bit value from four 64-bit ints. */
+
+static IRExpr* mkV256from64s ( IRTemp t3, IRTemp t2,
+ IRTemp t1, IRTemp t0 )
+{
+ return
+ binop( Iop_V128HLtoV256,
+ binop(Iop_64HLtoV128, mkexpr(t3), mkexpr(t2)),
+ binop(Iop_64HLtoV128, mkexpr(t1), mkexpr(t0))
+ );
+}
/* Helper for the SSSE3 (not SSE3) PMULHRSW insns. Given two 64-bit
values (aa,bb), computes, for each of the 4 16-bit lanes:
@@ -8842,6 +9206,7 @@
}
+
/* Helper for the SSSE3 (not SSE3) PABS{B,W,D} insns. Given a 64-bit
value aa, computes, for each lane
@@ -8851,9 +9216,9 @@
absolute value of the most negative signed input can be
represented.
*/
-static IRExpr* dis_PABS_helper ( IRExpr* aax, Int laneszB )
+static IRTemp math_PABS_MMX ( IRTemp aa, Int laneszB )
{
- IRTemp aa = newTemp(Ity_I64);
+ IRTemp res = newTemp(Ity_I64);
IRTemp zero = newTemp(Ity_I64);
IRTemp aaNeg = newTemp(Ity_I64);
IRTemp negMask = newTemp(Ity_I64);
@@ -8868,15 +9233,43 @@
default: vassert(0);
}
- assign( aa, aax );
assign( negMask, binop(opSarN, mkexpr(aa), mkU8(8*laneszB-1)) );
assign( posMask, unop(Iop_Not64, mkexpr(negMask)) );
assign( zero, mkU64(0) );
assign( aaNeg, binop(opSub, mkexpr(zero), mkexpr(aa)) );
- return
- binop(Iop_Or64,
- binop(Iop_And64, mkexpr(aa), mkexpr(posMask)),
- binop(Iop_And64, mkexpr(aaNeg), mkexpr(negMask)) );
+ assign( res,
+ binop(Iop_Or64,
+ binop(Iop_And64, mkexpr(aa), mkexpr(posMask)),
+ binop(Iop_And64, mkexpr(aaNeg), mkexpr(negMask)) ));
+ return res;
+}
+
+/* XMM version of math_PABS_MMX. */
+static IRTemp math_PABS_XMM ( IRTemp aa, Int laneszB )
+{
+ IRTemp res = newTemp(Ity_V128);
+ IRTemp aaHi = newTemp(Ity_I64);
+ IRTemp aaLo = newTemp(Ity_I64);
+ assign(aaHi, unop(Iop_V128HIto64, mkexpr(aa)));
+ assign(aaLo, unop(Iop_V128to64, mkexpr(aa)));
+ assign(res, binop(Iop_64HLtoV128,
+ mkexpr(math_PABS_MMX(aaHi, laneszB)),
+ mkexpr(math_PABS_MMX(aaLo, laneszB))));
+ return res;
+}
+
+/* Specialisations of math_PABS_XMM, since there's no easy way to do
+ partial applications in C :-( */
+static IRTemp math_PABS_XMM_pap4 ( IRTemp aa ) {
+ return math_PABS_XMM(aa, 4);
+}
+
+static IRTemp math_PABS_XMM_pap2 ( IRTemp aa ) {
+ return math_PABS_XMM(aa, 2);
+}
+
+static IRTemp math_PABS_XMM_pap1 ( IRTemp aa ) {
+ return math_PABS_XMM(aa, 1);
}
static IRExpr* dis_PALIGNR_XMM_helper ( IRTemp hi64,
@@ -8890,27 +9283,91 @@
);
}
+static IRTemp math_PALIGNR_XMM ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ IRTemp res = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ IRTemp rHi = newTemp(Ity_I64);
+ IRTemp rLo = newTemp(Ity_I64);
+
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+
+ if (imm8 == 0) {
+ assign( rHi, mkexpr(sHi) );
+ assign( rLo, mkexpr(sLo) );
+ }
+ else if (imm8 >= 1 && imm8 <= 7) {
+ assign( rHi, dis_PALIGNR_XMM_helper(dLo, sHi, imm8) );
+ assign( rLo, dis_PALIGNR_XMM_helper(sHi, sLo, imm8) );
+ }
+ else if (imm8 == 8) {
+ assign( rHi, mkexpr(dLo) );
+ assign( rLo, mkexpr(sHi) );
+ }
+ else if (imm8 >= 9 && imm8 <= 15) {
+ assign( rHi, dis_PALIGNR_XMM_helper(dHi, dLo, imm8-8) );
+ assign( rLo, dis_PALIGNR_XMM_helper(dLo, sHi, imm8-8) );
+ }
+ else if (imm8 == 16) {
+ assign( rHi, mkexpr(dHi) );
+ assign( rLo, mkexpr(dLo) );
+ }
+ else if (imm8 >= 17 && imm8 <= 23) {
+ assign( rHi, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(imm8-16))) );
+ assign( rLo, dis_PALIGNR_XMM_helper(dHi, dLo, imm8-16) );
+ }
+ else if (imm8 == 24) {
+ assign( rHi, mkU64(0) );
+ assign( rLo, mkexpr(dHi) );
+ }
+ else if (imm8 >= 25 && imm8 <= 31) {
+ assign( rHi, mkU64(0) );
+ assign( rLo, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(imm8-24))) );
+ }
+ else if (imm8 >= 32 && imm8 <= 255) {
+ assign( rHi, mkU64(0) );
+ assign( rLo, mkU64(0) );
+ }
+ else
+ vassert(0);
+
+ assign( res, binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo)));
+ return res;
+}
+
+
/* Generate a SIGSEGV followed by a restart of the current instruction
if effective_addr is not 16-aligned. This is required behaviour
for some SSE3 instructions and all 128-bit SSSE3 instructions.
This assumes that guest_RIP_curr_instr is set correctly! */
-/* TODO(glider): we've replaced the 0xF mask with 0x0, effectively disabling
- * the check. Need to enable it once TSan stops generating unaligned
- * accesses in the wrappers.
- * See http://code.google.com/p/data-race-test/issues/detail?id=49 */
-static void gen_SEGV_if_not_16_aligned ( IRTemp effective_addr )
+static
+void gen_SEGV_if_not_XX_aligned ( IRTemp effective_addr, ULong mask )
{
stmt(
IRStmt_Exit(
binop(Iop_CmpNE64,
- binop(Iop_And64,mkexpr(effective_addr),mkU64(0x0)),
+ binop(Iop_And64,mkexpr(effective_addr),mkU64(mask)),
mkU64(0)),
Ijk_SigSEGV,
- IRConst_U64(guest_RIP_curr_instr)
+ IRConst_U64(guest_RIP_curr_instr),
+ OFFB_RIP
)
);
}
+static void gen_SEGV_if_not_16_aligned ( IRTemp effective_addr ) {
+ gen_SEGV_if_not_XX_aligned(effective_addr, 16-1);
+}
+
+static void gen_SEGV_if_not_32_aligned ( IRTemp effective_addr ) {
+ gen_SEGV_if_not_XX_aligned(effective_addr, 32-1);
+}
/* Helper for deciding whether a given insn (starting at the opcode
byte) may validly be used with a LOCK prefix. The following insns
@@ -9043,7464 +9500,8922 @@
/*------------------------------------------------------------*/
-/*--- Disassemble a single instruction ---*/
+/*--- ---*/
+/*--- Top-level SSE/SSE2: dis_ESC_0F__SSE2 ---*/
+/*--- ---*/
/*------------------------------------------------------------*/
-/* Disassemble a single instruction into IR. The instruction is
- located in host memory at &guest_code[delta]. */
-
-static
-DisResult disInstr_AMD64_WRK (
- /*OUT*/Bool* expect_CAS,
- Bool put_IP,
- Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
- Bool resteerCisOk,
- void* callback_opaque,
- Long delta64,
- VexArchInfo* archinfo,
- VexAbiInfo* vbi
- )
+static Long dis_COMISD ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, UChar opc )
{
- IRType ty;
- IRTemp addr, t0, t1, t2, t3, t4, t5, t6;
- Int alen;
- UChar opc, modrm, abyte, pre;
- Long d64;
- HChar dis_buf[50];
- Int am_sz, d_sz, n, n_prefixes;
- DisResult dres;
- UChar* insn; /* used in SSE decoders */
-
- /* The running delta */
- Long delta = delta64;
-
- /* Holds eip at the start of the insn, so that we can print
- consistent error messages for unimplemented insns. */
- Long delta_start = delta;
-
- /* sz denotes the nominal data-op size of the insn; we change it to
- 2 if an 0x66 prefix is seen and 8 if REX.W is 1. In case of
- conflict REX.W takes precedence. */
- Int sz = 4;
-
- /* pfx holds the summary of prefixes. */
- Prefix pfx = PFX_EMPTY;
-
- /* Set result defaults. */
- dres.whatNext = Dis_Continue;
- dres.len = 0;
- dres.continueAt = 0;
-
- *expect_CAS = False;
-
- vassert(guest_RIP_next_assumed == 0);
- vassert(guest_RIP_next_mustcheck == False);
-
- addr = t0 = t1 = t2 = t3 = t4 = t5 = t6 = IRTemp_INVALID;
-
- DIP("\t0x%llx: ", guest_RIP_bbstart+delta);
-
- /* We may be asked to update the guest RIP before going further. */
- if (put_IP)
- stmt( IRStmt_Put( OFFB_RIP, mkU64(guest_RIP_curr_instr)) );
-
- /* Spot "Special" instructions (see comment at top of file). */
- {
- UChar* code = (UChar*)(guest_code + delta);
- /* Spot the 16-byte preamble:
- 48C1C703 rolq $3, %rdi
- 48C1C70D rolq $13, %rdi
- 48C1C73D rolq $61, %rdi
- 48C1C733 rolq $51, %rdi
- */
- if (code[ 0] == 0x48 && code[ 1] == 0xC1 && code[ 2] == 0xC7
- && code[ 3] == 0x03 &&
- code[ 4] == 0x48 && code[ 5] == 0xC1 && code[ 6] == 0xC7
- && code[ 7] == 0x0D &&
- code[ 8] == 0x48 && code[ 9] == 0xC1 && code[10] == 0xC7
- && code[11] == 0x3D &&
- code[12] == 0x48 && code[13] == 0xC1 && code[14] == 0xC7
- && code[15] == 0x33) {
- /* Got a "Special" instruction preamble. Which one is it? */
- if (code[16] == 0x48 && code[17] == 0x87
- && code[18] == 0xDB /* xchgq %rbx,%rbx */) {
- /* %RDX = client_request ( %RAX ) */
- DIP("%%rdx = client_request ( %%rax )\n");
- delta += 19;
- jmp_lit(Ijk_ClientReq, guest_RIP_bbstart+delta);
- dres.whatNext = Dis_StopHere;
- goto decode_success;
- }
- else
- if (code[16] == 0x48 && code[17] == 0x87
- && code[18] == 0xC9 /* xchgq %rcx,%rcx */) {
- /* %RAX = guest_NRADDR */
- DIP("%%rax = guest_NRADDR\n");
- delta += 19;
- putIRegRAX(8, IRExpr_Get( OFFB_NRADDR, Ity_I64 ));
- goto decode_success;
- }
- else
- if (code[16] == 0x48 && code[17] == 0x87
- && code[18] == 0xD2 /* xchgq %rdx,%rdx */) {
- /* call-noredir *%RAX */
- DIP("call-noredir *%%rax\n");
- delta += 19;
- t1 = newTemp(Ity_I64);
- assign(t1, getIRegRAX(8));
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8)));
- putIReg64(R_RSP, mkexpr(t2));
- storeLE( mkexpr(t2), mkU64(guest_RIP_bbstart+delta));
- jmp_treg(Ijk_NoRedir,t1);
- dres.whatNext = Dis_StopHere;
- goto decode_success;
- }
- /* We don't know what it is. */
- goto decode_failure;
- /*NOTREACHED*/
- }
- }
-
- /* Eat prefixes, summarising the result in pfx and sz, and rejecting
- as many invalid combinations as possible. */
- n_prefixes = 0;
- while (True) {
- if (n_prefixes > 7) goto decode_failure;
- pre = getUChar(delta);
- switch (pre) {
- case 0x66: pfx |= PFX_66; break;
- case 0x67: pfx |= PFX_ASO; break;
- case 0xF2: pfx |= PFX_F2; break;
- case 0xF3: pfx |= PFX_F3; break;
- case 0xF0: pfx |= PFX_LOCK; *expect_CAS = True; break;
- case 0x2E: pfx |= PFX_CS; break;
- case 0x3E: pfx |= PFX_DS; break;
- case 0x26: pfx |= PFX_ES; break;
- case 0x64: pfx |= PFX_FS; break;
- case 0x65: pfx |= PFX_GS; break;
- case 0x36: pfx |= PFX_SS; break;
- case 0x40 ... 0x4F:
- pfx |= PFX_REX;
- if (pre & (1<<3)) pfx |= PFX_REXW;
- if (pre & (1<<2)) pfx |= PFX_REXR;
- if (pre & (1<<1)) pfx |= PFX_REXX;
- if (pre & (1<<0)) pfx |= PFX_REXB;
- break;
- default:
- goto not_a_prefix;
- }
- n_prefixes++;
- delta++;
- }
-
- not_a_prefix:
-
- /* Dump invalid combinations */
- n = 0;
- if (pfx & PFX_F2) n++;
- if (pfx & PFX_F3) n++;
- if (n > 1)
- goto decode_failure; /* can't have both */
-
- n = 0;
- if (pfx & PFX_CS) n++;
- if (pfx & PFX_DS) n++;
- if (pfx & PFX_ES) n++;
- if (pfx & PFX_FS) n++;
- if (pfx & PFX_GS) n++;
- if (pfx & PFX_SS) n++;
- if (n > 1)
- goto decode_failure; /* multiple seg overrides == illegal */
-
- /* We have a %fs prefix. Reject it if there's no evidence in 'vbi'
- that we should accept it. */
- if ((pfx & PFX_FS) && !vbi->guest_amd64_assume_fs_is_zero)
- goto decode_failure;
-
- /* Ditto for %gs prefixes. */
- if ((pfx & PFX_GS) && !vbi->guest_amd64_assume_gs_is_0x60)
- goto decode_failure;
-
- /* Set up sz. */
- sz = 4;
- if (pfx & PFX_66) sz = 2;
- if ((pfx & PFX_REX) && (pfx & PFX_REXW)) sz = 8;
-
- /* Now we should be looking at the primary opcode byte or the
- leading F2 or F3. Check that any LOCK prefix is actually
- allowed. */
-
- if (pfx & PFX_LOCK) {
- if (can_be_used_with_LOCK_prefix( (UChar*)&guest_code[delta] )) {
- DIP("lock ");
- } else {
- *expect_CAS = False;
- goto decode_failure;
- }
- }
-
-
- /* ---------------------------------------------------- */
- /* --- The SSE/SSE2 decoder. --- */
- /* ---------------------------------------------------- */
-
- /* What did I do to deserve SSE ? Perhaps I was really bad in a
- previous life? */
-
- /* Note, this doesn't handle SSE3 right now. All amd64s support
- SSE2 as a minimum so there is no point distinguishing SSE1 vs
- SSE2. */
-
- insn = (UChar*)&guest_code[delta];
-
- /* FXSAVE is spuriously at the start here only because it is
- thusly placed in guest-x86/toIR.c. */
-
- /* 0F AE /0 = FXSAVE m512 -- write x87 and SSE state to memory.
- Note that the presence or absence of REX.W slightly affects the
- written format: whether the saved FPU IP and DP pointers are 64
- or 32 bits. But the helper function we call simply writes zero
- bits in the relevant fields (which are 64 bits regardless of
- what REX.W is) and so it's good enough (iow, equally broken) in
- both cases. */
- if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
- && insn[0] == 0x0F && insn[1] == 0xAE
- && !epartIsReg(insn[2]) && gregOfRexRM(pfx,insn[2]) == 0) {
- IRDirty* d;
- modrm = getUChar(delta+2);
- vassert(!epartIsReg(modrm));
-
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- gen_SEGV_if_not_16_aligned(addr);
-
- DIP("%sfxsave %s\n", sz==8 ? "rex64/" : "", dis_buf);
-
- /* Uses dirty helper:
- void amd64g_do_FXSAVE ( VexGuestAMD64State*, ULong ) */
- d = unsafeIRDirty_0_N (
- 0/*regparms*/,
- "amd64g_dirtyhelper_FXSAVE",
- &amd64g_dirtyhelper_FXSAVE,
- mkIRExprVec_1( mkexpr(addr) )
- );
- d->needsBBP = True;
-
- /* declare we're writing memory */
- d->mFx = Ifx_Write;
- d->mAddr = mkexpr(addr);
- d->mSize = 512;
-
- /* declare we're reading guest state */
- d->nFxState = 7;
-
- d->fxState[0].fx = Ifx_Read;
- d->fxState[0].offset = OFFB_FTOP;
- d->fxState[0].size = sizeof(UInt);
-
- d->fxState[1].fx = Ifx_Read;
- d->fxState[1].offset = OFFB_FPREGS;
- d->fxState[1].size = 8 * sizeof(ULong);
-
- d->fxState[2].fx = Ifx_Read;
- d->fxState[2].offset = OFFB_FPTAGS;
- d->fxState[2].size = 8 * sizeof(UChar);
-
- d->fxState[3].fx = Ifx_Read;
- d->fxState[3].offset = OFFB_FPROUND;
- d->fxState[3].size = sizeof(ULong);
-
- d->fxState[4].fx = Ifx_Read;
- d->fxState[4].offset = OFFB_FC3210;
- d->fxState[4].size = sizeof(ULong);
-
- d->fxState[5].fx = Ifx_Read;
- d->fxState[5].offset = OFFB_XMM0;
- d->fxState[5].size = 16 * sizeof(U128);
-
- d->fxState[6].fx = Ifx_Read;
- d->fxState[6].offset = OFFB_SSEROUND;
- d->fxState[6].size = sizeof(ULong);
-
- /* Be paranoid ... this assertion tries to ensure the 16 %xmm
- images are packed back-to-back. If not, the value of
- d->fxState[5].size is wrong. */
- vassert(16 == sizeof(U128));
- vassert(OFFB_XMM15 == (OFFB_XMM0 + 15 * 16));
-
- stmt( IRStmt_Dirty(d) );
-
- goto decode_success;
- }
-
- /* 0F AE /1 = FXRSTOR m512 -- read x87 and SSE state from memory.
- As with FXSAVE above we ignore the value of REX.W since we're
- not bothering with the FPU DP and IP fields. */
- if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
- && insn[0] == 0x0F && insn[1] == 0xAE
- && !epartIsReg(insn[2]) && gregOfRexRM(pfx,insn[2]) == 1) {
- IRDirty* d;
- modrm = getUChar(delta+2);
- vassert(!epartIsReg(modrm));
-
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- gen_SEGV_if_not_16_aligned(addr);
-
- DIP("%sfxrstor %s\n", sz==8 ? "rex64/" : "", dis_buf);
-
- /* Uses dirty helper:
- VexEmWarn amd64g_do_FXRSTOR ( VexGuestAMD64State*, ULong )
- NOTE:
- the VexEmWarn value is simply ignored
- */
- d = unsafeIRDirty_0_N (
- 0/*regparms*/,
- "amd64g_dirtyhelper_FXRSTOR",
- &amd64g_dirtyhelper_FXRSTOR,
- mkIRExprVec_1( mkexpr(addr) )
- );
- d->needsBBP = True;
-
- /* declare we're reading memory */
- d->mFx = Ifx_Read;
- d->mAddr = mkexpr(addr);
- d->mSize = 512;
-
- /* declare we're writing guest state */
- d->nFxState = 7;
-
- d->fxState[0].fx = Ifx_Write;
- d->fxState[0].offset = OFFB_FTOP;
- d->fxState[0].size = sizeof(UInt);
-
- d->fxState[1].fx = Ifx_Write;
- d->fxState[1].offset = OFFB_FPREGS;
- d->fxState[1].size = 8 * sizeof(ULong);
-
- d->fxState[2].fx = Ifx_Write;
- d->fxState[2].offset = OFFB_FPTAGS;
- d->fxState[2].size = 8 * sizeof(UChar);
-
- d->fxState[3].fx = Ifx_Write;
- d->fxState[3].offset = OFFB_FPROUND;
- d->fxState[3].size = sizeof(ULong);
-
- d->fxState[4].fx = Ifx_Write;
- d->fxState[4].offset = OFFB_FC3210;
- d->fxState[4].size = sizeof(ULong);
-
- d->fxState[5].fx = Ifx_Write;
- d->fxState[5].offset = OFFB_XMM0;
- d->fxState[5].size = 16 * sizeof(U128);
-
- d->fxState[6].fx = Ifx_Write;
- d->fxState[6].offset = OFFB_SSEROUND;
- d->fxState[6].size = sizeof(ULong);
-
- /* Be paranoid ... this assertion tries to ensure the 16 %xmm
- images are packed back-to-back. If not, the value of
- d->fxState[5].size is wrong. */
- vassert(16 == sizeof(U128));
- vassert(OFFB_XMM15 == (OFFB_XMM0 + 15 * 16));
-
- stmt( IRStmt_Dirty(d) );
-
- goto decode_success;
- }
-
- /* ------ SSE decoder main ------ */
-
- /* 0F 58 = ADDPS -- add 32Fx4 from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x58) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "addps", Iop_Add32Fx4 );
- goto decode_success;
- }
-
- /* F3 0F 58 = ADDSS -- add 32F0x4 from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x58) {
- delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta+2, "addss", Iop_Add32F0x4 );
- goto decode_success;
- }
-
- /* 0F 55 = ANDNPS -- G = (not G) and E */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x55) {
- delta = dis_SSE_E_to_G_all_invG( vbi, pfx, delta+2, "andnps", Iop_AndV128 );
- goto decode_success;
- }
-
- /* 0F 54 = ANDPS -- G = G and E */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x54) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "andps", Iop_AndV128 );
- goto decode_success;
- }
-
- /* 0F C2 = CMPPS -- 32Fx4 comparison from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC2) {
- delta = dis_SSEcmp_E_to_G( vbi, pfx, delta+2, "cmpps", True, 4 );
- goto decode_success;
- }
-
- /* F3 0F C2 = CMPSS -- 32F0x4 comparison from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC2) {
- delta = dis_SSEcmp_E_to_G( vbi, pfx, delta+2, "cmpss", False, 4 );
- goto decode_success;
- }
-
- /* 0F 2F = COMISS -- 32F0x4 comparison G,E, and set ZCP */
- /* 0F 2E = UCOMISS -- 32F0x4 comparison G,E, and set ZCP */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) {
- IRTemp argL = newTemp(Ity_F32);
- IRTemp argR = newTemp(Ity_F32);
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- assign( argR, getXMMRegLane32F( eregOfRexRM(pfx,modrm),
- 0/*lowest lane*/ ) );
- delta += 2+1;
- DIP("%scomiss %s,%s\n", insn[1]==0x2E ? "u" : "",
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( argR, loadLE(Ity_F32, mkexpr(addr)) );
- delta += 2+alen;
- DIP("%scomiss %s,%s\n", insn[1]==0x2E ? "u" : "",
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
- assign( argL, getXMMRegLane32F( gregOfRexRM(pfx,modrm),
+ vassert(opc == 0x2F/*COMISD*/ || opc == 0x2E/*UCOMISD*/);
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp argL = newTemp(Ity_F64);
+ IRTemp argR = newTemp(Ity_F64);
+ UChar modrm = getUChar(delta);
+ IRTemp addr = IRTemp_INVALID;
+ if (epartIsReg(modrm)) {
+ assign( argR, getXMMRegLane64F( eregOfRexRM(pfx,modrm),
0/*lowest lane*/ ) );
-
- stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- stmt( IRStmt_Put(
- OFFB_CC_DEP1,
- binop( Iop_And64,
- unop( Iop_32Uto64,
- binop(Iop_CmpF64,
- unop(Iop_F32toF64,mkexpr(argL)),
- unop(Iop_F32toF64,mkexpr(argR)))),
- mkU64(0x45)
- )));
-
- goto decode_success;
+ delta += 1;
+ DIP("%s%scomisd %s,%s\n", isAvx ? "v" : "",
+ opc==0x2E ? "u" : "",
+ nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argR, loadLE(Ity_F64, mkexpr(addr)) );
+ delta += alen;
+ DIP("%s%scomisd %s,%s\n", isAvx ? "v" : "",
+ opc==0x2E ? "u" : "",
+ dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
}
+ assign( argL, getXMMRegLane64F( gregOfRexRM(pfx,modrm),
+ 0/*lowest lane*/ ) );
- /* 0F 2A = CVTPI2PS -- convert 2 x I32 in mem/mmx to 2 x F32 in low
- half xmm */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x2A) {
- IRTemp arg64 = newTemp(Ity_I64);
- IRTemp rmode = newTemp(Ity_I32);
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put(
+ OFFB_CC_DEP1,
+ binop( Iop_And64,
+ unop( Iop_32Uto64,
+ binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR)) ),
+ mkU64(0x45)
+ )));
+ return delta;
+}
- modrm = getUChar(delta+2);
- do_MMX_preamble();
- if (epartIsReg(modrm)) {
- assign( arg64, getMMXReg(eregLO3ofRM(modrm)) );
- delta += 2+1;
- DIP("cvtpi2ps %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtpi2ps %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
- assign( rmode, get_sse_roundingmode() );
-
- putXMMRegLane32F(
- gregOfRexRM(pfx,modrm), 0,
- binop(Iop_F64toF32,
- mkexpr(rmode),
- unop(Iop_I32StoF64,
- unop(Iop_64to32, mkexpr(arg64)) )) );
-
- putXMMRegLane32F(
- gregOfRexRM(pfx,modrm), 1,
- binop(Iop_F64toF32,
- mkexpr(rmode),
- unop(Iop_I32StoF64,
- unop(Iop_64HIto32, mkexpr(arg64)) )) );
-
- goto decode_success;
+static Long dis_COMISS ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, UChar opc )
+{
+ vassert(opc == 0x2F/*COMISS*/ || opc == 0x2E/*UCOMISS*/);
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp argL = newTemp(Ity_F32);
+ IRTemp argR = newTemp(Ity_F32);
+ UChar modrm = getUChar(delta);
+ IRTemp addr = IRTemp_INVALID;
+ if (epartIsReg(modrm)) {
+ assign( argR, getXMMRegLane32F( eregOfRexRM(pfx,modrm),
+ 0/*lowest lane*/ ) );
+ delta += 1;
+ DIP("%s%scomiss %s,%s\n", isAvx ? "v" : "",
+ opc==0x2E ? "u" : "",
+ nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argR, loadLE(Ity_F32, mkexpr(addr)) );
+ delta += alen;
+ DIP("%s%scomiss %s,%s\n", isAvx ? "v" : "",
+ opc==0x2E ? "u" : "",
+ dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
}
+ assign( argL, getXMMRegLane32F( gregOfRexRM(pfx,modrm),
+ 0/*lowest lane*/ ) );
- /* F3 0F 2A = CVTSI2SS
- -- sz==4: convert I32 in mem/ireg to F32 in low quarter xmm
- -- sz==8: convert I64 in mem/ireg to F32 in low quarter xmm */
- if (haveF3no66noF2(pfx) && (sz == 4 || sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x2A) {
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put(
+ OFFB_CC_DEP1,
+ binop( Iop_And64,
+ unop( Iop_32Uto64,
+ binop(Iop_CmpF64,
+ unop(Iop_F32toF64,mkexpr(argL)),
+ unop(Iop_F32toF64,mkexpr(argR)))),
+ mkU64(0x45)
+ )));
+ return delta;
+}
- IRTemp rmode = newTemp(Ity_I32);
- assign( rmode, get_sse_roundingmode() );
- modrm = getUChar(delta+2);
- if (sz == 4) {
- IRTemp arg32 = newTemp(Ity_I32);
- if (epartIsReg(modrm)) {
- assign( arg32, getIReg32(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("cvtsi2ss %s,%s\n", nameIReg32(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( arg32, loadLE(Ity_I32, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtsi2ss %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
- putXMMRegLane32F(
- gregOfRexRM(pfx,modrm), 0,
- binop(Iop_F64toF32,
- mkexpr(rmode),
- unop(Iop_I32StoF64, mkexpr(arg32)) ) );
- } else {
- /* sz == 8 */
- IRTemp arg64 = newTemp(Ity_I64);
- if (epartIsReg(modrm)) {
- assign( arg64, getIReg64(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("cvtsi2ssq %s,%s\n", nameIReg64(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtsi2ssq %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
- putXMMRegLane32F(
- gregOfRexRM(pfx,modrm), 0,
- binop(Iop_F64toF32,
- mkexpr(rmode),
- binop(Iop_I64StoF64, mkexpr(rmode), mkexpr(arg64)) ) );
- }
-
- goto decode_success;
- }
-
- /* 0F 2D = CVTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x
- I32 in mmx, according to prevailing SSE rounding mode */
- /* 0F 2C = CVTTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x
- I32 in mmx, rounding towards zero */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) {
- IRTemp dst64 = newTemp(Ity_I64);
- IRTemp rmode = newTemp(Ity_I32);
- IRTemp f32lo = newTemp(Ity_F32);
- IRTemp f32hi = newTemp(Ity_F32);
- Bool r2zero = toBool(insn[1] == 0x2C);
-
- do_MMX_preamble();
- modrm = getUChar(delta+2);
-
- if (epartIsReg(modrm)) {
- delta += 2+1;
- assign(f32lo, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 0));
- assign(f32hi, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 1));
- DIP("cvt%sps2pi %s,%s\n", r2zero ? "t" : "",
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign(f32lo, loadLE(Ity_F32, mkexpr(addr)));
- assign(f32hi, loadLE(Ity_F32, binop( Iop_Add64,
- mkexpr(addr),
- mkU64(4) )));
- delta += 2+alen;
- DIP("cvt%sps2pi %s,%s\n", r2zero ? "t" : "",
- dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
-
- if (r2zero) {
- assign(rmode, mkU32((UInt)Irrm_ZERO) );
- } else {
- assign( rmode, get_sse_roundingmode() );
- }
-
- assign(
- dst64,
- binop( Iop_32HLto64,
- binop( Iop_F64toI32S,
- mkexpr(rmode),
- unop( Iop_F32toF64, mkexpr(f32hi) ) ),
- binop( Iop_F64toI32S,
- mkexpr(rmode),
- unop( Iop_F32toF64, mkexpr(f32lo) ) )
- )
- );
-
- putMMXReg(gregLO3ofRM(modrm), mkexpr(dst64));
- goto decode_success;
- }
-
- /* F3 0F 2D = CVTSS2SI
- when sz==4 -- convert F32 in mem/low quarter xmm to I32 in ireg,
- according to prevailing SSE rounding mode
- when sz==8 -- convert F32 in mem/low quarter xmm to I64 in ireg,
- according to prevailing SSE rounding mode
- */
- /* F3 0F 2C = CVTTSS2SI
- when sz==4 -- convert F32 in mem/low quarter xmm to I32 in ireg,
- truncating towards zero
- when sz==8 -- convert F32 in mem/low quarter xmm to I64 in ireg,
- truncating towards zero
- */
- if (haveF3no66noF2(pfx)
- && insn[0] == 0x0F
- && (insn[1] == 0x2D || insn[1] == 0x2C)) {
- IRTemp rmode = newTemp(Ity_I32);
- IRTemp f32lo = newTemp(Ity_F32);
- Bool r2zero = toBool(insn[1] == 0x2C);
- vassert(sz == 4 || sz == 8);
-
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- delta += 2+1;
- assign(f32lo, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 0));
- DIP("cvt%sss2si %s,%s\n", r2zero ? "t" : "",
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameIReg(sz, gregOfRexRM(pfx,modrm), False));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign(f32lo, loadLE(Ity_F32, mkexpr(addr)));
- delta += 2+alen;
- DIP("cvt%sss2si %s,%s\n", r2zero ? "t" : "",
- dis_buf,
- nameIReg(sz, gregOfRexRM(pfx,modrm), False));
- }
-
- if (r2zero) {
- assign( rmode, mkU32((UInt)Irrm_ZERO) );
- } else {
- assign( rmode, get_sse_roundingmode() );
- }
-
- if (sz == 4) {
- putIReg32( gregOfRexRM(pfx,modrm),
- binop( Iop_F64toI32S,
- mkexpr(rmode),
- unop(Iop_F32toF64, mkexpr(f32lo))) );
- } else {
- putIReg64( gregOfRexRM(pfx,modrm),
- binop( Iop_F64toI64S,
- mkexpr(rmode),
- unop(Iop_F32toF64, mkexpr(f32lo))) );
- }
-
- goto decode_success;
- }
-
- /* 0F 5E = DIVPS -- div 32Fx4 from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5E) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "divps", Iop_Div32Fx4 );
- goto decode_success;
- }
-
- /* F3 0F 5E = DIVSS -- div 32F0x4 from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5E) {
- delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta+2, "divss", Iop_Div32F0x4 );
- goto decode_success;
- }
-
- /* 0F AE /2 = LDMXCSR m32 -- load %mxcsr */
- if (insn[0] == 0x0F && insn[1] == 0xAE
- && haveNo66noF2noF3(pfx)
- && !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 2) {
-
- IRTemp t64 = newTemp(Ity_I64);
- IRTemp ew = newTemp(Ity_I32);
-
- vassert(sz == 4);
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- DIP("ldmxcsr %s\n", dis_buf);
-
- /* The only thing we observe in %mxcsr is the rounding mode.
- Therefore, pass the 32-bit value (SSE native-format control
- word) to a clean helper, getting back a 64-bit value, the
- lower half of which is the SSEROUND value to store, and the
- upper half of which is the emulation-warning token which may
- be generated.
- */
- /* ULong amd64h_check_ldmxcsr ( ULong ); */
- assign( t64, mkIRExprCCall(
- Ity_I64, 0/*regparms*/,
- "amd64g_check_ldmxcsr",
- &amd64g_check_ldmxcsr,
- mkIRExprVec_1(
- unop(Iop_32Uto64,
- loadLE(Ity_I32, mkexpr(addr))
- )
- )
- )
- );
-
- put_sse_roundingmode( unop(Iop_64to32, mkexpr(t64)) );
- assign( ew, unop(Iop_64HIto32, mkexpr(t64) ) );
- put_emwarn( mkexpr(ew) );
- /* Finally, if an emulation warning was reported, side-exit to
- the next insn, reporting the warning, so that Valgrind's
- dispatcher sees the warning. */
- stmt(
- IRStmt_Exit(
- binop(Iop_CmpNE64, unop(Iop_32Uto64,mkexpr(ew)), mkU64(0)),
- Ijk_EmWarn,
- IRConst_U64(guest_RIP_bbstart+delta)
- )
- );
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F F7 = MASKMOVQ -- 8x8 masked store */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xF7) {
- Bool ok = False;
- delta = dis_MMX( &ok, vbi, pfx, sz, delta+1 );
- if (!ok)
- goto decode_failure;
- goto decode_success;
- }
-
- /* 0F 5F = MAXPS -- max 32Fx4 from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5F) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "maxps", Iop_Max32Fx4 );
- goto decode_success;
- }
-
- /* F3 0F 5F = MAXSS -- max 32F0x4 from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5F) {
- delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta+2, "maxss", Iop_Max32F0x4 );
- goto decode_success;
- }
-
- /* 0F 5D = MINPS -- min 32Fx4 from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5D) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "minps", Iop_Min32Fx4 );
- goto decode_success;
- }
-
- /* F3 0F 5D = MINSS -- min 32F0x4 from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5D) {
- delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta+2, "minss", Iop_Min32F0x4 );
- goto decode_success;
- }
-
- /* 0F 28 = MOVAPS -- move from E (mem or xmm) to G (xmm). */
- /* 0F 10 = MOVUPS -- move from E (mem or xmm) to G (xmm). */
- if (haveNo66noF2noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && (insn[1] == 0x28 || insn[1] == 0x10)) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- putXMMReg( gregOfRexRM(pfx,modrm),
- getXMMReg( eregOfRexRM(pfx,modrm) ));
- DIP("mov[ua]ps %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- if (insn[1] == 0x28/*movaps*/)
- gen_SEGV_if_not_16_aligned( addr );
- putXMMReg( gregOfRexRM(pfx,modrm),
- loadLE(Ity_V128, mkexpr(addr)) );
- DIP("mov[ua]ps %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
- }
- goto decode_success;
- }
-
- /* 0F 29 = MOVAPS -- move from G (xmm) to E (mem or xmm). */
- /* 0F 11 = MOVUPS -- move from G (xmm) to E (mem or xmm). */
- if (haveNo66noF2noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && (insn[1] == 0x29 || insn[1] == 0x11)) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- /* fall through; awaiting test case */
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- if (insn[1] == 0x29/*movaps*/)
- gen_SEGV_if_not_16_aligned( addr );
- storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
- DIP("mov[ua]ps %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
- dis_buf );
- delta += 2+alen;
- goto decode_success;
- }
- }
-
- /* 0F 16 = MOVHPS -- move from mem to high half of XMM. */
- /* 0F 16 = MOVLHPS -- move from lo half to hi half of XMM. */
- if (haveNo66noF2noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x16) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- delta += 2+1;
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 1/*upper lane*/,
- getXMMRegLane64( eregOfRexRM(pfx,modrm), 0 ) );
- DIP("movhps %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 1/*upper lane*/,
- loadLE(Ity_I64, mkexpr(addr)) );
- DIP("movhps %s,%s\n", dis_buf,
- nameXMMReg( gregOfRexRM(pfx,modrm) ));
- }
- goto decode_success;
- }
-
- /* 0F 17 = MOVHPS -- move from high half of XMM to mem. */
- if (haveNo66noF2noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x17) {
- if (!epartIsReg(insn[2])) {
- delta += 2;
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
- storeLE( mkexpr(addr),
- getXMMRegLane64( gregOfRexRM(pfx,insn[2]),
- 1/*upper lane*/ ) );
- DIP("movhps %s,%s\n", nameXMMReg( gregOfRexRM(pfx,insn[2]) ),
- dis_buf);
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* 0F 12 = MOVLPS -- move from mem to low half of XMM. */
- /* OF 12 = MOVHLPS -- from from hi half to lo half of XMM. */
- if (haveNo66noF2noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x12) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- delta += 2+1;
- putXMMRegLane64( gregOfRexRM(pfx,modrm),
- 0/*lower lane*/,
- getXMMRegLane64( eregOfRexRM(pfx,modrm), 1 ));
- DIP("movhlps %s, %s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 0/*lower lane*/,
- loadLE(Ity_I64, mkexpr(addr)) );
- DIP("movlps %s, %s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx,modrm) ));
- }
- goto decode_success;
- }
-
- /* 0F 13 = MOVLPS -- move from low half of XMM to mem. */
- if (haveNo66noF2noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x13) {
- if (!epartIsReg(insn[2])) {
- delta += 2;
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
- storeLE( mkexpr(addr),
- getXMMRegLane64( gregOfRexRM(pfx,insn[2]),
- 0/*lower lane*/ ) );
- DIP("movlps %s, %s\n", nameXMMReg( gregOfRexRM(pfx,insn[2]) ),
- dis_buf);
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* 0F 50 = MOVMSKPS - move 4 sign bits from 4 x F32 in xmm(E)
- to 4 lowest bits of ireg(G) */
- if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x50) {
- /* sz == 8 is a kludge to handle insns with REX.W redundantly
- set to 1, which has been known to happen:
-
- 4c 0f 50 d9 rex64X movmskps %xmm1,%r11d
-
- 20071106: Intel docs say that REX.W isn't redundant: when
- present, a 64-bit register is written; when not present, only
- the 32-bit half is written. However, testing on a Core2
- machine suggests the entire 64 bit register is written
- irrespective of the status of REX.W. That could be because
- of the default rule that says "if the lower half of a 32-bit
- register is written, the upper half is zeroed". By using
- putIReg32 here we inadvertantly produce the same behaviour as
- the Core2, for the same reason -- putIReg32 implements said
- rule.
-
- AMD docs give no indication that REX.W is even valid for this
- insn. */
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- Int src;
- t0 = newTemp(Ity_I32);
- t1 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I32);
- t3 = newTemp(Ity_I32);
- delta += 2+1;
- src = eregOfRexRM(pfx,modrm);
- assign( t0, binop( Iop_And32,
- binop(Iop_Shr32, getXMMRegLane32(src,0), mkU8(31)),
- mkU32(1) ));
- assign( t1, binop( Iop_And32,
- binop(Iop_Shr32, getXMMRegLane32(src,1), mkU8(30)),
- mkU32(2) ));
- assign( t2, binop( Iop_And32,
- binop(Iop_Shr32, getXMMRegLane32(src,2), mkU8(29)),
- mkU32(4) ));
- assign( t3, binop( Iop_And32,
- binop(Iop_Shr32, getXMMRegLane32(src,3), mkU8(28)),
- mkU32(8) ));
- putIReg32( gregOfRexRM(pfx,modrm),
- binop(Iop_Or32,
- binop(Iop_Or32, mkexpr(t0), mkexpr(t1)),
- binop(Iop_Or32, mkexpr(t2), mkexpr(t3))
- )
- );
- DIP("movmskps %s,%s\n", nameXMMReg(src),
- nameIReg32(gregOfRexRM(pfx,modrm)));
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* 66 0F 2B = MOVNTPD -- for us, just a plain SSE store. */
- /* 0F 2B = MOVNTPS -- for us, just a plain SSE store. */
- if ( ( (haveNo66noF2noF3(pfx) && sz == 4)
- || (have66noF2noF3(pfx) && sz == 2)
- )
- && insn[0] == 0x0F && insn[1] == 0x2B) {
- modrm = getUChar(delta+2);
- if (!epartIsReg(modrm)) {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
- DIP("movntp%s %s,%s\n", sz==2 ? "d" : "s",
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F E7 = MOVNTQ -- for us, just a plain MMX store. Note, the
- Intel manual does not say anything about the usual business of
- the FP reg tags getting trashed whenever an MMX insn happens.
- So we just leave them alone.
- */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xE7) {
- modrm = getUChar(delta+2);
- if (!epartIsReg(modrm)) {
- /* do_MMX_preamble(); Intel docs don't specify this */
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- storeLE( mkexpr(addr), getMMXReg(gregLO3ofRM(modrm)) );
- DIP("movntq %s,%s\n", dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- delta += 2+alen;
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* F3 0F 10 = MOVSS -- move 32 bits from E (mem or lo 1/4 xmm) to G
- (lo 1/4 xmm). If E is mem, upper 3/4 of G is zeroed out. */
- if (haveF3no66noF2(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x10) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 0,
- getXMMRegLane32( eregOfRexRM(pfx,modrm), 0 ));
- DIP("movss %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- putXMMReg( gregOfRexRM(pfx,modrm), mkV128(0) );
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 0,
- loadLE(Ity_I32, mkexpr(addr)) );
- DIP("movss %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
- }
- goto decode_success;
- }
-
- /* F3 0F 11 = MOVSS -- move 32 bits from G (lo 1/4 xmm) to E (mem
- or lo 1/4 xmm). */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x11) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- /* fall through, we don't yet have a test case */
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- storeLE( mkexpr(addr),
- getXMMRegLane32(gregOfRexRM(pfx,modrm), 0) );
- DIP("movss %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
- dis_buf);
- delta += 2+alen;
- goto decode_success;
- }
- }
-
- /* 0F 59 = MULPS -- mul 32Fx4 from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x59) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "mulps", Iop_Mul32Fx4 );
- goto decode_success;
- }
-
- /* F3 0F 59 = MULSS -- mul 32F0x4 from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x59) {
- delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta+2, "mulss", Iop_Mul32F0x4 );
- goto decode_success;
- }
-
- /* 0F 56 = ORPS -- G = G and E */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x56) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "orps", Iop_OrV128 );
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xE0) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "pavgb", False );
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xE3) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "pavgw", False );
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F C5 = PEXTRW -- extract 16-bit field from mmx(E) and put
- zero-extend of it in ireg(G). */
- if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
- && insn[0] == 0x0F && insn[1] == 0xC5) {
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- IRTemp sV = newTemp(Ity_I64);
- t5 = newTemp(Ity_I16);
- do_MMX_preamble();
- assign(sV, getMMXReg(eregLO3ofRM(modrm)));
- breakup64to16s( sV, &t3, &t2, &t1, &t0 );
- switch (insn[3] & 3) {
- case 0: assign(t5, mkexpr(t0)); break;
- case 1: assign(t5, mkexpr(t1)); break;
- case 2: assign(t5, mkexpr(t2)); break;
- case 3: assign(t5, mkexpr(t3)); break;
- default: vassert(0);
- }
- if (sz == 8)
- putIReg64(gregOfRexRM(pfx,modrm), unop(Iop_16Uto64, mkexpr(t5)));
- else
- putIReg32(gregOfRexRM(pfx,modrm), unop(Iop_16Uto32, mkexpr(t5)));
- DIP("pextrw $%d,%s,%s\n",
- (Int)insn[3], nameMMXReg(eregLO3ofRM(modrm)),
- sz==8 ? nameIReg64(gregOfRexRM(pfx,modrm))
- : nameIReg32(gregOfRexRM(pfx,modrm))
- );
- delta += 4;
- goto decode_success;
- }
- /* else fall through */
- /* note, for anyone filling in the mem case: this insn has one
- byte after the amode and therefore you must pass 1 as the
- last arg to disAMode */
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
- put it into the specified lane of mmx(G). */
- if (haveNo66noF2noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0xC4) {
- /* Use t0 .. t3 to hold the 4 original 16-bit lanes of the
- mmx reg. t4 is the new lane value. t5 is the original
- mmx value. t6 is the new mmx value. */
- Int lane;
- t4 = newTemp(Ity_I16);
- t5 = newTemp(Ity_I64);
- t6 = newTemp(Ity_I64);
- modrm = insn[2];
- do_MMX_preamble();
-
- assign(t5, getMMXReg(gregLO3ofRM(modrm)));
- breakup64to16s( t5, &t3, &t2, &t1, &t0 );
-
- if (epartIsReg(modrm)) {
- assign(t4, getIReg16(eregOfRexRM(pfx,modrm)));
- delta += 3+1;
- lane = insn[3+1-1];
- DIP("pinsrw $%d,%s,%s\n", (Int)lane,
- nameIReg16(eregOfRexRM(pfx,modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 1 );
- delta += 3+alen;
- lane = insn[3+alen-1];
- assign(t4, loadLE(Ity_I16, mkexpr(addr)));
- DIP("pinsrw $%d,%s,%s\n", (Int)lane,
- dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
-
- switch (lane & 3) {
- case 0: assign(t6, mk64from16s(t3,t2,t1,t4)); break;
- case 1: assign(t6, mk64from16s(t3,t2,t4,t0)); break;
- case 2: assign(t6, mk64from16s(t3,t4,t1,t0)); break;
- case 3: assign(t6, mk64from16s(t4,t2,t1,t0)); break;
- default: vassert(0);
- }
- putMMXReg(gregLO3ofRM(modrm), mkexpr(t6));
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F EE = PMAXSW -- 16x4 signed max */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xEE) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "pmaxsw", False );
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F DE = PMAXUB -- 8x8 unsigned max */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xDE) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "pmaxub", False );
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F EA = PMINSW -- 16x4 signed min */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xEA) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "pminsw", False );
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F DA = PMINUB -- 8x8 unsigned min */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xDA) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "pminub", False );
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F D7 = PMOVMSKB -- extract sign bits from each of 8 lanes in
- mmx(G), turn them into a byte, and put zero-extend of it in
- ireg(G). */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xD7) {
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- do_MMX_preamble();
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- assign(t0, getMMXReg(eregLO3ofRM(modrm)));
- assign(t1, mkIRExprCCall(
- Ity_I64, 0/*regparms*/,
- "amd64g_calculate_mmx_pmovmskb",
- &amd64g_calculate_mmx_pmovmskb,
- mkIRExprVec_1(mkexpr(t0))));
- putIReg32(gregOfRexRM(pfx,modrm), unop(Iop_64to32,mkexpr(t1)));
- DIP("pmovmskb %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
- nameIReg32(gregOfRexRM(pfx,modrm)));
- delta += 3;
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F E4 = PMULUH -- 16x4 hi-half of unsigned widening multiply */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xE4) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "pmuluh", False );
- goto decode_success;
- }
-
- /* 0F 18 /0 = PREFETCHNTA -- prefetch into caches, */
- /* 0F 18 /1 = PREFETCH0 -- with various different hints */
- /* 0F 18 /2 = PREFETCH1 */
- /* 0F 18 /3 = PREFETCH2 */
- if (insn[0] == 0x0F && insn[1] == 0x18
- && haveNo66noF2noF3(pfx)
- && !epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) >= 0 && gregLO3ofRM(insn[2]) <= 3) {
- HChar* hintstr = "??";
-
- modrm = getUChar(delta+2);
- vassert(!epartIsReg(modrm));
-
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
-
- switch (gregLO3ofRM(modrm)) {
- case 0: hintstr = "nta"; break;
- case 1: hintstr = "t0"; break;
- case 2: hintstr = "t1"; break;
- case 3: hintstr = "t2"; break;
- default: vassert(0);
- }
-
- DIP("prefetch%s %s\n", hintstr, dis_buf);
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F F6 = PSADBW -- sum of 8Ux8 absolute differences */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xF6) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "psadbw", False );
- goto decode_success;
- }
-
- /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
- /* 0F 70 = PSHUFW -- rearrange 4x16 from E(mmx or mem) to G(mmx) */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x70) {
- Int order;
- IRTemp sV, dV, s3, s2, s1, s0;
- s3 = s2 = s1 = s0 = IRTemp_INVALID;
- sV = newTemp(Ity_I64);
- dV = newTemp(Ity_I64);
- do_MMX_preamble();
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
- order = (Int)insn[3];
- delta += 2+2;
- DIP("pshufw $%d,%s,%s\n", order,
- nameMMXReg(eregLO3ofRM(modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf,
- 1/*extra byte after amode*/ );
- assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
- order = (Int)insn[2+alen];
- delta += 3+alen;
- DIP("pshufw $%d,%s,%s\n", order,
- dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
- breakup64to16s( sV, &s3, &s2, &s1, &s0 );
-# define SEL(n) \
- ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3)))
- assign(dV,
- mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3),
- SEL((order>>2)&3), SEL((order>>0)&3) )
- );
- putMMXReg(gregLO3ofRM(modrm), mkexpr(dV));
-# undef SEL
- goto decode_success;
- }
-
- /* 0F 53 = RCPPS -- approx reciprocal 32Fx4 from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x53) {
- delta = dis_SSE_E_to_G_unary_all( vbi, pfx, delta+2,
- "rcpps", Iop_Recip32Fx4 );
- goto decode_success;
- }
-
- /* F3 0F 53 = RCPSS -- approx reciprocal 32F0x4 from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x53) {
- delta = dis_SSE_E_to_G_unary_lo32( vbi, pfx, delta+2,
- "rcpss", Iop_Recip32F0x4 );
- goto decode_success;
- }
-
- /* 0F 52 = RSQRTPS -- approx reciprocal sqrt 32Fx4 from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x52) {
- delta = dis_SSE_E_to_G_unary_all( vbi, pfx, delta+2,
- "rsqrtps", Iop_RSqrt32Fx4 );
- goto decode_success;
- }
-
- /* F3 0F 52 = RSQRTSS -- approx reciprocal sqrt 32F0x4 from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x52) {
- delta = dis_SSE_E_to_G_unary_lo32( vbi, pfx, delta+2,
- "rsqrtss", Iop_RSqrt32F0x4 );
- goto decode_success;
- }
-
- /* 0F AE /7 = SFENCE -- flush pending operations to memory */
- if (haveNo66noF2noF3(pfx)
- && insn[0] == 0x0F && insn[1] == 0xAE
- && epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 7
- && sz == 4) {
- delta += 3;
- /* Insert a memory fence. It's sometimes important that these
- are carried through to the generated code. */
- stmt( IRStmt_MBE(Imbe_Fence) );
- DIP("sfence\n");
- goto decode_success;
- }
-
- /* 0F C6 /r ib = SHUFPS -- shuffle packed F32s */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC6) {
- Int select;
- IRTemp sV, dV;
- IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
- sV = newTemp(Ity_V128);
- dV = newTemp(Ity_V128);
- s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
- modrm = insn[2];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- select = (Int)insn[3];
- delta += 2+2;
- DIP("shufps $%d,%s,%s\n", select,
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf,
- 1/*byte at end of insn*/ );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- select = (Int)insn[2+alen];
- delta += 3+alen;
- DIP("shufps $%d,%s,%s\n", select,
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- breakup128to32s( dV, &d3, &d2, &d1, &d0 );
- breakup128to32s( sV, &s3, &s2, &s1, &s0 );
-
-# define SELD(n) ((n)==0 ? d0 : ((n)==1 ? d1 : ((n)==2 ? d2 : d3)))
-# define SELS(n) ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3)))
-
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- mk128from32s( SELS((select>>6)&3), SELS((select>>4)&3),
- SELD((select>>2)&3), SELD((select>>0)&3) )
- );
-
-# undef SELD
-# undef SELS
-
- goto decode_success;
- }
-
- /* 0F 51 = SQRTPS -- approx sqrt 32Fx4 from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x51) {
- delta = dis_SSE_E_to_G_unary_all( vbi, pfx, delta+2,
- "sqrtps", Iop_Sqrt32Fx4 );
- goto decode_success;
- }
-
- /* F3 0F 51 = SQRTSS -- approx sqrt 32F0x4 from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x51) {
- delta = dis_SSE_E_to_G_unary_lo32( vbi, pfx, delta+2,
- "sqrtss", Iop_Sqrt32F0x4 );
- goto decode_success;
- }
-
- /* 0F AE /3 = STMXCSR m32 -- store %mxcsr */
- if (insn[0] == 0x0F && insn[1] == 0xAE
- && haveNo66noF2noF3(pfx)
- && !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 3) {
-
- vassert(sz == 4);
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
-
- /* Fake up a native SSE mxcsr word. The only thing it depends
- on is SSEROUND[1:0], so call a clean helper to cook it up.
- */
- /* ULong amd64h_create_mxcsr ( ULong sseround ) */
- DIP("stmxcsr %s\n", dis_buf);
- storeLE(
- mkexpr(addr),
- unop(Iop_64to32,
- mkIRExprCCall(
- Ity_I64, 0/*regp*/,
- "amd64g_create_mxcsr", &amd64g_create_mxcsr,
- mkIRExprVec_1( unop(Iop_32Uto64,get_sse_roundingmode()) )
- )
- )
- );
- goto decode_success;
- }
-
- /* 0F 5C = SUBPS -- sub 32Fx4 from R/M to R */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5C) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "subps", Iop_Sub32Fx4 );
- goto decode_success;
- }
-
- /* F3 0F 5C = SUBSS -- sub 32F0x4 from R/M to R */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5C) {
- delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta+2, "subss", Iop_Sub32F0x4 );
- goto decode_success;
- }
-
- /* 0F 15 = UNPCKHPS -- unpack and interleave high part F32s */
- /* 0F 14 = UNPCKLPS -- unpack and interleave low part F32s */
- /* These just appear to be special cases of SHUFPS */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) {
- IRTemp sV, dV;
- IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
- Bool hi = toBool(insn[1] == 0x15);
- sV = newTemp(Ity_V128);
- dV = newTemp(Ity_V128);
- s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
- modrm = insn[2];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("unpck%sps %s,%s\n", hi ? "h" : "l",
+static Long dis_PSHUFD_32x4 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool writesYmm )
+{
+ Int order;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp sV = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ HChar* strV = writesYmm ? "v" : "";
+ IRTemp addr = IRTemp_INVALID;
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
+ order = (Int)getUChar(delta+1);
+ delta += 1+1;
+ DIP("%spshufd $%d,%s,%s\n", strV, order,
nameXMMReg(eregOfRexRM(pfx,modrm)),
nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 2+alen;
- DIP("unpck%sps %s,%s\n", hi ? "h" : "l",
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- breakup128to32s( dV, &d3, &d2, &d1, &d0 );
- breakup128to32s( sV, &s3, &s2, &s1, &s0 );
-
- if (hi) {
- putXMMReg( gregOfRexRM(pfx,modrm), mk128from32s( s3, d3, s2, d2 ) );
- } else {
- putXMMReg( gregOfRexRM(pfx,modrm), mk128from32s( s1, d1, s0, d0 ) );
- }
-
- goto decode_success;
- }
-
- /* 0F 57 = XORPS -- G = G and E */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x57) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "xorps", Iop_XorV128 );
- goto decode_success;
- }
-
- /* ---------------------------------------------------- */
- /* --- end of the SSE decoder. --- */
- /* ---------------------------------------------------- */
-
- /* ---------------------------------------------------- */
- /* --- start of the SSE2 decoder. --- */
- /* ---------------------------------------------------- */
-
- /* 66 0F 58 = ADDPD -- add 32Fx4 from R/M to R */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x58) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "addpd", Iop_Add64Fx2 );
- goto decode_success;
- }
-
- /* F2 0F 58 = ADDSD -- add 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x58) {
- delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta+2, "addsd", Iop_Add64F0x2 );
- goto decode_success;
- }
-
- /* 66 0F 55 = ANDNPD -- G = (not G) and E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x55) {
- delta = dis_SSE_E_to_G_all_invG( vbi, pfx, delta+2, "andnpd", Iop_AndV128 );
- goto decode_success;
- }
-
- /* 66 0F 54 = ANDPD -- G = G and E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x54) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "andpd", Iop_AndV128 );
- goto decode_success;
- }
-
- /* 66 0F C2 = CMPPD -- 64Fx2 comparison from R/M to R */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xC2) {
- delta = dis_SSEcmp_E_to_G( vbi, pfx, delta+2, "cmppd", True, 8 );
- goto decode_success;
- }
-
- /* F2 0F C2 = CMPSD -- 64F0x2 comparison from R/M to R */
- if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xC2) {
- delta = dis_SSEcmp_E_to_G( vbi, pfx, delta+2, "cmpsd", False, 8 );
- goto decode_success;
- }
-
- /* 66 0F 2F = COMISD -- 64F0x2 comparison G,E, and set ZCP */
- /* 66 0F 2E = UCOMISD -- 64F0x2 comparison G,E, and set ZCP */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) {
- IRTemp argL = newTemp(Ity_F64);
- IRTemp argR = newTemp(Ity_F64);
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- assign( argR, getXMMRegLane64F( eregOfRexRM(pfx,modrm),
- 0/*lowest lane*/ ) );
- delta += 2+1;
- DIP("%scomisd %s,%s\n", insn[1]==0x2E ? "u" : "",
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( argR, loadLE(Ity_F64, mkexpr(addr)) );
- delta += 2+alen;
- DIP("%scomisd %s,%s\n", insn[1]==0x2E ? "u" : "",
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf,
+ 1/*byte after the amode*/ );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ order = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP("%spshufd $%d,%s,%s\n", strV, order,
dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
- assign( argL, getXMMRegLane64F( gregOfRexRM(pfx,modrm),
- 0/*lowest lane*/ ) );
-
- stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- stmt( IRStmt_Put(
- OFFB_CC_DEP1,
- binop( Iop_And64,
- unop( Iop_32Uto64,
- binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR)) ),
- mkU64(0x45)
- )));
-
- goto decode_success;
- }
-
- /* F3 0F E6 = CVTDQ2PD -- convert 2 x I32 in mem/lo half xmm to 2 x
- F64 in xmm(G) */
- if (haveF3no66noF2(pfx) && insn[0] == 0x0F && insn[1] == 0xE6) {
- IRTemp arg64 = newTemp(Ity_I64);
- if (sz != 4) goto decode_failure;
-
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- assign( arg64, getXMMRegLane64(eregOfRexRM(pfx,modrm), 0) );
- delta += 2+1;
- DIP("cvtdq2pd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtdq2pd %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
-
- putXMMRegLane64F(
- gregOfRexRM(pfx,modrm), 0,
- unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)))
- );
-
- putXMMRegLane64F(
- gregOfRexRM(pfx,modrm), 1,
- unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)))
- );
-
- goto decode_success;
}
- /* 0F 5B = CVTDQ2PS -- convert 4 x I32 in mem/xmm to 4 x F32 in
- xmm(G) */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5B) {
- IRTemp argV = newTemp(Ity_V128);
- IRTemp rmode = newTemp(Ity_I32);
+ IRTemp s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- assign( argV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("cvtdq2ps %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtdq2ps %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
-
- assign( rmode, get_sse_roundingmode() );
- breakup128to32s( argV, &t3, &t2, &t1, &t0 );
+# define SEL(n) ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3)))
+ IRTemp dV = newTemp(Ity_V128);
+ assign(dV,
+ mkV128from32s( SEL((order>>6)&3), SEL((order>>4)&3),
+ SEL((order>>2)&3), SEL((order>>0)&3) )
+ );
+# undef SEL
-# define CVT(_t) binop( Iop_F64toF32, \
- mkexpr(rmode), \
- unop(Iop_I32StoF64,mkexpr(_t)))
-
- putXMMRegLane32F( gregOfRexRM(pfx,modrm), 3, CVT(t3) );
- putXMMRegLane32F( gregOfRexRM(pfx,modrm), 2, CVT(t2) );
- putXMMRegLane32F( gregOfRexRM(pfx,modrm), 1, CVT(t1) );
- putXMMRegLane32F( gregOfRexRM(pfx,modrm), 0, CVT(t0) );
+ (writesYmm ? putYMMRegLoAndZU : putXMMReg)
+ (gregOfRexRM(pfx,modrm), mkexpr(dV));
+ return delta;
+}
-# undef CVT
- goto decode_success;
+static IRTemp math_PSRLDQ ( IRTemp sV, Int imm )
+{
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp hi64 = newTemp(Ity_I64);
+ IRTemp lo64 = newTemp(Ity_I64);
+ IRTemp hi64r = newTemp(Ity_I64);
+ IRTemp lo64r = newTemp(Ity_I64);
+
+ vassert(imm >= 0 && imm <= 255);
+ if (imm >= 16) {
+ assign(dV, mkV128(0x0000));
+ return dV;
}
- /* 66 0F E6 = CVTTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I32 in
- lo half xmm(G), and zero upper half, rounding towards zero */
- /* F2 0F E6 = CVTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I32 in
- lo half xmm(G), according to prevailing rounding mode, and zero
- upper half */
- if ( ( (haveF2no66noF3(pfx) && sz == 4)
- || (have66noF2noF3(pfx) && sz == 2)
- )
- && insn[0] == 0x0F && insn[1] == 0xE6) {
- IRTemp argV = newTemp(Ity_V128);
- IRTemp rmode = newTemp(Ity_I32);
- Bool r2zero = toBool(sz == 2);
+ assign( hi64, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( lo64, unop(Iop_V128to64, mkexpr(sV)) );
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- assign( argV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("cvt%spd2dq %s,%s\n", r2zero ? "t" : "",
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvt%spd2dq %s,%s\n", r2zero ? "t" : "",
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
-
- if (r2zero) {
- assign(rmode, mkU32((UInt)Irrm_ZERO) );
- } else {
- assign( rmode, get_sse_roundingmode() );
- }
+ if (imm == 0) {
+ assign( lo64r, mkexpr(lo64) );
+ assign( hi64r, mkexpr(hi64) );
+ }
+ else
+ if (imm == 8) {
+ assign( hi64r, mkU64(0) );
+ assign( lo64r, mkexpr(hi64) );
+ }
+ else
+ if (imm > 8) {
+ assign( hi64r, mkU64(0) );
+ assign( lo64r, binop( Iop_Shr64, mkexpr(hi64), mkU8( 8*(imm-8) ) ));
+ } else {
+ assign( hi64r, binop( Iop_Shr64, mkexpr(hi64), mkU8(8 * imm) ));
+ assign( lo64r,
+ binop( Iop_Or64,
+ binop(Iop_Shr64, mkexpr(lo64),
+ mkU8(8 * imm)),
+ binop(Iop_Shl64, mkexpr(hi64),
+ mkU8(8 * (8 - imm)) )
+ )
+ );
+ }
+
+ assign( dV, binop(Iop_64HLtoV128, mkexpr(hi64r), mkexpr(lo64r)) );
+ return dV;
+}
- t0 = newTemp(Ity_F64);
- t1 = newTemp(Ity_F64);
- assign( t0, unop(Iop_ReinterpI64asF64,
- unop(Iop_V128to64, mkexpr(argV))) );
- assign( t1, unop(Iop_ReinterpI64asF64,
- unop(Iop_V128HIto64, mkexpr(argV))) );
-
-# define CVT(_t) binop( Iop_F64toI32S, \
- mkexpr(rmode), \
- mkexpr(_t) )
-
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 3, mkU32(0) );
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 2, mkU32(0) );
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 1, CVT(t1) );
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 0, CVT(t0) );
-# undef CVT
+static IRTemp math_PSLLDQ ( IRTemp sV, Int imm )
+{
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp hi64 = newTemp(Ity_I64);
+ IRTemp lo64 = newTemp(Ity_I64);
+ IRTemp hi64r = newTemp(Ity_I64);
+ IRTemp lo64r = newTemp(Ity_I64);
- goto decode_success;
+ vassert(imm >= 0 && imm <= 255);
+ if (imm >= 16) {
+ assign(dV, mkV128(0x0000));
+ return dV;
}
- /* 66 0F 2D = CVTPD2PI -- convert 2 x F64 in mem/xmm to 2 x
- I32 in mmx, according to prevailing SSE rounding mode */
- /* 66 0F 2C = CVTTPD2PI -- convert 2 x F64 in mem/xmm to 2 x
- I32 in mmx, rounding towards zero */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) {
- IRTemp dst64 = newTemp(Ity_I64);
- IRTemp rmode = newTemp(Ity_I32);
- IRTemp f64lo = newTemp(Ity_F64);
- IRTemp f64hi = newTemp(Ity_F64);
- Bool r2zero = toBool(insn[1] == 0x2C);
-
- do_MMX_preamble();
- modrm = getUChar(delta+2);
-
- if (epartIsReg(modrm)) {
- delta += 2+1;
- assign(f64lo, getXMMRegLane64F(eregOfRexRM(pfx,modrm), 0));
- assign(f64hi, getXMMRegLane64F(eregOfRexRM(pfx,modrm), 1));
- DIP("cvt%spd2pi %s,%s\n", r2zero ? "t" : "",
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign(f64lo, loadLE(Ity_F64, mkexpr(addr)));
- assign(f64hi, loadLE(Ity_F64, binop( Iop_Add64,
- mkexpr(addr),
- mkU64(8) )));
- delta += 2+alen;
- DIP("cvt%spf2pi %s,%s\n", r2zero ? "t" : "",
- dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
-
- if (r2zero) {
- assign(rmode, mkU32((UInt)Irrm_ZERO) );
- } else {
- assign( rmode, get_sse_roundingmode() );
- }
-
- assign(
- dst64,
- binop( Iop_32HLto64,
- binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64hi) ),
- binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo) )
- )
- );
-
- putMMXReg(gregLO3ofRM(modrm), mkexpr(dst64));
- goto decode_success;
+ assign( hi64, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( lo64, unop(Iop_V128to64, mkexpr(sV)) );
+
+ if (imm == 0) {
+ assign( lo64r, mkexpr(lo64) );
+ assign( hi64r, mkexpr(hi64) );
+ }
+ else
+ if (imm == 8) {
+ assign( lo64r, mkU64(0) );
+ assign( hi64r, mkexpr(lo64) );
+ }
+ else
+ if (imm > 8) {
+ assign( lo64r, mkU64(0) );
+ assign( hi64r, binop( Iop_Shl64, mkexpr(lo64), mkU8( 8*(imm-8) ) ));
+ } else {
+ assign( lo64r, binop( Iop_Shl64, mkexpr(lo64), mkU8(8 * imm) ));
+ assign( hi64r,
+ binop( Iop_Or64,
+ binop(Iop_Shl64, mkexpr(hi64),
+ mkU8(8 * imm)),
+ binop(Iop_Shr64, mkexpr(lo64),
+ mkU8(8 * (8 - imm)) )
+ )
+ );
}
- /* 66 0F 5A = CVTPD2PS -- convert 2 x F64 in mem/xmm to 2 x F32 in
- lo half xmm(G), rounding according to prevailing SSE rounding
- mode, and zero upper half */
- /* Note, this is practically identical to CVTPD2DQ. It would have
- been nicer to merge them together, but the insn[] offsets differ
- by one. */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5A) {
- IRTemp argV = newTemp(Ity_V128);
- IRTemp rmode = newTemp(Ity_I32);
+ assign( dV, binop(Iop_64HLtoV128, mkexpr(hi64r), mkexpr(lo64r)) );
+ return dV;
+}
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- assign( argV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("cvtpd2ps %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtpd2ps %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
-
- assign( rmode, get_sse_roundingmode() );
- t0 = newTemp(Ity_F64);
- t1 = newTemp(Ity_F64);
- assign( t0, unop(Iop_ReinterpI64asF64,
- unop(Iop_V128to64, mkexpr(argV))) );
- assign( t1, unop(Iop_ReinterpI64asF64,
- unop(Iop_V128HIto64, mkexpr(argV))) );
-
-# define CVT(_t) binop( Iop_F64toF32, \
- mkexpr(rmode), \
- mkexpr(_t) )
-
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 3, mkU32(0) );
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 2, mkU32(0) );
- putXMMRegLane32F( gregOfRexRM(pfx,modrm), 1, CVT(t1) );
- putXMMRegLane32F( gregOfRexRM(pfx,modrm), 0, CVT(t0) );
-# undef CVT
+static Long dis_CVTxSD2SI ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, UChar opc, Int sz )
+{
+ vassert(opc == 0x2D/*CVTSD2SI*/ || opc == 0x2C/*CVTTSD2SI*/);
+ HChar dis_buf[50];
+ Int alen = 0;
+ UChar modrm = getUChar(delta);
+ IRTemp addr = IRTemp_INVALID;
+ IRTemp rmode = newTemp(Ity_I32);
+ IRTemp f64lo = newTemp(Ity_F64);
+ Bool r2zero = toBool(opc == 0x2C);
- goto decode_success;
- }
-
- /* 66 0F 2A = CVTPI2PD -- convert 2 x I32 in mem/mmx to 2 x F64 in
- xmm(G) */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x2A) {
- IRTemp arg64 = newTemp(Ity_I64);
-
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- /* Only switch to MMX mode if the source is a MMX register.
- This is inconsistent with all other instructions which
- convert between XMM and (M64 or MMX), which always switch
- to MMX mode even if 64-bit operand is M64 and not MMX. At
- least, that's what the Intel docs seem to me to say.
- Fixes #210264. */
- do_MMX_preamble();
- assign( arg64, getMMXReg(eregLO3ofRM(modrm)) );
- delta += 2+1;
- DIP("cvtpi2pd %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtpi2pd %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
-
- putXMMRegLane64F(
- gregOfRexRM(pfx,modrm), 0,
- unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)) )
- );
-
- putXMMRegLane64F(
- gregOfRexRM(pfx,modrm), 1,
- unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)) )
- );
-
- goto decode_success;
- }
-
- /* F3 0F 5B = CVTTPS2DQ -- convert 4 x F32 in mem/xmm to 4 x I32 in
- xmm(G), rounding towards zero */
- /* 66 0F 5B = CVTPS2DQ -- convert 4 x F32 in mem/xmm to 4 x I32 in
- xmm(G), as per the prevailing rounding mode */
- if ( ( (have66noF2noF3(pfx) && sz == 2)
- || (haveF3no66noF2(pfx) && sz == 4)
- )
- && insn[0] == 0x0F && insn[1] == 0x5B) {
- IRTemp argV = newTemp(Ity_V128);
- IRTemp rmode = newTemp(Ity_I32);
- Bool r2zero = toBool(sz == 4);
-
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- assign( argV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("cvtps2dq %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtps2dq %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
-
- if (r2zero) {
- assign( rmode, mkU32((UInt)Irrm_ZERO) );
- } else {
- assign( rmode, get_sse_roundingmode() );
- }
-
- breakup128to32s( argV, &t3, &t2, &t1, &t0 );
-
- /* This is less than ideal. If it turns out to be a performance
- bottleneck it can be improved. */
-# define CVT(_t) \
- binop( Iop_F64toI32S, \
- mkexpr(rmode), \
- unop( Iop_F32toF64, \
- unop( Iop_ReinterpI32asF32, mkexpr(_t))) )
-
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 3, CVT(t3) );
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 2, CVT(t2) );
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 1, CVT(t1) );
- putXMMRegLane32( gregOfRexRM(pfx,modrm), 0, CVT(t0) );
-
-# undef CVT
-
- goto decode_success;
- }
-
- /* 0F 5A = CVTPS2PD -- convert 2 x F32 in low half mem/xmm to 2 x
- F64 in xmm(G). */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5A) {
- IRTemp f32lo = newTemp(Ity_F32);
- IRTemp f32hi = newTemp(Ity_F32);
-
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- assign( f32lo, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 0) );
- assign( f32hi, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 1) );
- delta += 2+1;
- DIP("cvtps2pd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( f32lo, loadLE(Ity_F32, mkexpr(addr)) );
- assign( f32hi, loadLE(Ity_F32,
- binop(Iop_Add64,mkexpr(addr),mkU64(4))) );
- delta += 2+alen;
- DIP("cvtps2pd %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
-
- putXMMRegLane64F( gregOfRexRM(pfx,modrm), 1,
- unop(Iop_F32toF64, mkexpr(f32hi)) );
- putXMMRegLane64F( gregOfRexRM(pfx,modrm), 0,
- unop(Iop_F32toF64, mkexpr(f32lo)) );
-
- goto decode_success;
- }
-
- /* F2 0F 2D = CVTSD2SI
- when sz==4 -- convert F64 in mem/low half xmm to I32 in ireg,
- according to prevailing SSE rounding mode
- when sz==8 -- convert F64 in mem/low half xmm to I64 in ireg,
- according to prevailing SSE rounding mode
- */
- /* F2 0F 2C = CVTTSD2SI
- when sz==4 -- convert F64 in mem/low half xmm to I32 in ireg,
- truncating towards zero
- when sz==8 -- convert F64 in mem/low half xmm to I64 in ireg,
- truncating towards zero
- */
- if (haveF2no66noF3(pfx)
- && insn[0] == 0x0F
- && (insn[1] == 0x2D || insn[1] == 0x2C)) {
- IRTemp rmode = newTemp(Ity_I32);
- IRTemp f64lo = newTemp(Ity_F64);
- Bool r2zero = toBool(insn[1] == 0x2C);
- vassert(sz == 4 || sz == 8);
-
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- delta += 2+1;
- assign(f64lo, getXMMRegLane64F(eregOfRexRM(pfx,modrm), 0));
- DIP("cvt%ssd2si %s,%s\n", r2zero ? "t" : "",
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameIReg(sz, gregOfRexRM(pfx,modrm), False));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign(f64lo, loadLE(Ity_F64, mkexpr(addr)));
- delta += 2+alen;
- DIP("cvt%ssd2si %s,%s\n", r2zero ? "t" : "",
- dis_buf,
- nameIReg(sz, gregOfRexRM(pfx,modrm), False));
- }
-
- if (r2zero) {
- assign( rmode, mkU32((UInt)Irrm_ZERO) );
- } else {
- assign( rmode, get_sse_roundingmode() );
- }
-
- if (sz == 4) {
- putIReg32( gregOfRexRM(pfx,modrm),
- binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo)) );
- } else {
- putIReg64( gregOfRexRM(pfx,modrm),
- binop( Iop_F64toI64S, mkexpr(rmode), mkexpr(f64lo)) );
- }
-
- goto decode_success;
- }
-
- /* F2 0F 5A = CVTSD2SS -- convert F64 in mem/low half xmm to F32 in
- low 1/4 xmm(G), according to prevailing SSE rounding mode */
- if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5A) {
- IRTemp rmode = newTemp(Ity_I32);
- IRTemp f64lo = newTemp(Ity_F64);
- vassert(sz == 4);
-
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- delta += 2+1;
- assign(f64lo, getXMMRegLane64F(eregOfRexRM(pfx,modrm), 0));
- DIP("cvtsd2ss %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign(f64lo, loadLE(Ity_F64, mkexpr(addr)));
- delta += 2+alen;
- DIP("cvtsd2ss %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- assign( rmode, get_sse_roundingmode() );
- putXMMRegLane32F(
- gregOfRexRM(pfx,modrm), 0,
- binop( Iop_F64toF32, mkexpr(rmode), mkexpr(f64lo) )
- );
-
- goto decode_success;
- }
-
- /* F2 0F 2A = CVTSI2SD
- when sz==4 -- convert I32 in mem/ireg to F64 in low half xmm
- when sz==8 -- convert I64 in mem/ireg to F64 in low half xmm
- */
- if (haveF2no66noF3(pfx) && (sz == 4 || sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x2A) {
- modrm = getUChar(delta+2);
-
- if (sz == 4) {
- IRTemp arg32 = newTemp(Ity_I32);
- if (epartIsReg(modrm)) {
- assign( arg32, getIReg32(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("cvtsi2sd %s,%s\n", nameIReg32(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( arg32, loadLE(Ity_I32, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtsi2sd %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
- putXMMRegLane64F( gregOfRexRM(pfx,modrm), 0,
- unop(Iop_I32StoF64, mkexpr(arg32))
- );
- } else {
- /* sz == 8 */
- IRTemp arg64 = newTemp(Ity_I64);
- if (epartIsReg(modrm)) {
- assign( arg64, getIReg64(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("cvtsi2sdq %s,%s\n", nameIReg64(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 2+alen;
- DIP("cvtsi2sdq %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)) );
- }
- putXMMRegLane64F(
- gregOfRexRM(pfx,modrm),
- 0,
- binop( Iop_I64StoF64,
- get_sse_roundingmode(),
- mkexpr(arg64)
- )
- );
-
- }
-
- goto decode_success;
- }
-
- /* F3 0F 5A = CVTSS2SD -- convert F32 in mem/low 1/4 xmm to F64 in
- low half xmm(G) */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5A) {
- IRTemp f32lo = newTemp(Ity_F32);
-
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- delta += 2+1;
- assign(f32lo, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 0));
- DIP("cvtss2sd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign(f32lo, loadLE(Ity_F32, mkexpr(addr)));
- delta += 2+alen;
- DIP("cvtss2sd %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- putXMMRegLane64F( gregOfRexRM(pfx,modrm), 0,
- unop( Iop_F32toF64, mkexpr(f32lo) ) );
-
- goto decode_success;
- }
-
- /* 66 0F 5E = DIVPD -- div 64Fx2 from R/M to R */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5E) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "divpd", Iop_Div64Fx2 );
- goto decode_success;
- }
-
- /* F2 0F 5E = DIVSD -- div 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x5E) {
- vassert(sz == 4);
- delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta+2, "divsd", Iop_Div64F0x2 );
- goto decode_success;
- }
-
- /* 0F AE /5 = LFENCE -- flush pending operations to memory */
- /* 0F AE /6 = MFENCE -- flush pending operations to memory */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xAE
- && epartIsReg(insn[2])
- && (gregLO3ofRM(insn[2]) == 5 || gregLO3ofRM(insn[2]) == 6)) {
- delta += 3;
- /* Insert a memory fence. It's sometimes important that these
- are carried through to the generated code. */
- stmt( IRStmt_MBE(Imbe_Fence) );
- DIP("%sfence\n", gregLO3ofRM(insn[2])==5 ? "l" : "m");
- goto decode_success;
- }
-
- /* 66 0F 5F = MAXPD -- max 64Fx2 from R/M to R */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5F) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "maxpd", Iop_Max64Fx2 );
- goto decode_success;
- }
-
- /* F2 0F 5F = MAXSD -- max 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5F) {
- delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta+2, "maxsd", Iop_Max64F0x2 );
- goto decode_success;
- }
-
- /* 66 0F 5D = MINPD -- min 64Fx2 from R/M to R */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5D) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "minpd", Iop_Min64Fx2 );
- goto decode_success;
- }
-
- /* F2 0F 5D = MINSD -- min 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x5D) {
- delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta+2, "minsd", Iop_Min64F0x2 );
- goto decode_success;
- }
-
- /* 66 0F 28 = MOVAPD -- move from E (mem or xmm) to G (xmm). */
- /* 66 0F 10 = MOVUPD -- move from E (mem or xmm) to G (xmm). */
- /* 66 0F 6F = MOVDQA -- move from E (mem or xmm) to G (xmm). */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F
- && (insn[1] == 0x28 || insn[1] == 0x10 || insn[1] == 0x6F)) {
- HChar* wot = insn[1]==0x28 ? "apd" :
- insn[1]==0x10 ? "upd" : "dqa";
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- putXMMReg( gregOfRexRM(pfx,modrm),
- getXMMReg( eregOfRexRM(pfx,modrm) ));
- DIP("mov%s %s,%s\n", wot, nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- if (insn[1] == 0x28/*movapd*/ || insn[1] == 0x6F/*movdqa*/)
- gen_SEGV_if_not_16_aligned( addr );
- putXMMReg( gregOfRexRM(pfx,modrm),
- loadLE(Ity_V128, mkexpr(addr)) );
- DIP("mov%s %s,%s\n", wot, dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
- }
- goto decode_success;
- }
-
- /* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */
- /* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F
- && (insn[1] == 0x29 || insn[1] == 0x11)) {
- HChar* wot = insn[1]==0x29 ? "apd" : "upd";
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- putXMMReg( eregOfRexRM(pfx,modrm),
- getXMMReg( gregOfRexRM(pfx,modrm) ) );
- DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRexRM(pfx,modrm)),
- nameXMMReg(eregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- if (insn[1] == 0x29/*movapd*/)
- gen_SEGV_if_not_16_aligned( addr );
- storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
- DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRexRM(pfx,modrm)),
- dis_buf );
- delta += 2+alen;
- }
- goto decode_success;
- }
-
- /* 66 0F 6E = MOVD from ireg32/m32 to xmm lo 1/4, zeroing high 3/4 of xmm. */
- /* or from ireg64/m64 to xmm lo 1/2, zeroing high 1/2 of xmm. */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x6E) {
- vassert(sz == 2 || sz == 8);
- if (sz == 2) sz = 4;
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- delta += 2+1;
- if (sz == 4) {
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- unop( Iop_32UtoV128, getIReg32(eregOfRexRM(pfx,modrm)) )
- );
- DIP("movd %s, %s\n", nameIReg32(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- unop( Iop_64UtoV128, getIReg64(eregOfRexRM(pfx,modrm)) )
- );
- DIP("movq %s, %s\n", nameIReg64(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- sz == 4
- ? unop( Iop_32UtoV128,loadLE(Ity_I32, mkexpr(addr)) )
- : unop( Iop_64UtoV128,loadLE(Ity_I64, mkexpr(addr)) )
- );
- DIP("mov%c %s, %s\n", sz == 4 ? 'd' : 'q', dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
- goto decode_success;
- }
-
- /* 66 0F 7E = MOVD from xmm low 1/4 to ireg32 or m32. */
- /* or from xmm low 1/2 to ireg64 or m64. */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x7E) {
- if (sz == 2) sz = 4;
- vassert(sz == 4 || sz == 8);
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- delta += 2+1;
- if (sz == 4) {
- putIReg32( eregOfRexRM(pfx,modrm),
- getXMMRegLane32(gregOfRexRM(pfx,modrm), 0) );
- DIP("movd %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
- nameIReg32(eregOfRexRM(pfx,modrm)));
- } else {
- putIReg64( eregOfRexRM(pfx,modrm),
- getXMMRegLane64(gregOfRexRM(pfx,modrm), 0) );
- DIP("movq %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
- nameIReg64(eregOfRexRM(pfx,modrm)));
- }
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- storeLE( mkexpr(addr),
- sz == 4
- ? getXMMRegLane32(gregOfRexRM(pfx,modrm),0)
- : getXMMRegLane64(gregOfRexRM(pfx,modrm),0) );
- DIP("mov%c %s, %s\n", sz == 4 ? 'd' : 'q',
- nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf);
- }
- goto decode_success;
- }
-
- /* 66 0F 7F = MOVDQA -- move from G (xmm) to E (mem or xmm). */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x7F) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- delta += 2+1;
- putXMMReg( eregOfRexRM(pfx,modrm),
- getXMMReg(gregOfRexRM(pfx,modrm)) );
- DIP("movdqa %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
- nameXMMReg(eregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- delta += 2+alen;
- storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
- DIP("movdqa %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf);
- }
- goto decode_success;
- }
-
- /* F3 0F 6F = MOVDQU -- move from E (mem or xmm) to G (xmm). */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x6F) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- putXMMReg( gregOfRexRM(pfx,modrm),
- getXMMReg( eregOfRexRM(pfx,modrm) ));
- DIP("movdqu %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- putXMMReg( gregOfRexRM(pfx,modrm),
- loadLE(Ity_V128, mkexpr(addr)) );
- DIP("movdqu %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
- }
- goto decode_success;
- }
-
- /* F3 0F 7F = MOVDQU -- move from G (xmm) to E (mem or xmm). */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x7F) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- goto decode_failure; /* awaiting test case */
- delta += 2+1;
- putXMMReg( eregOfRexRM(pfx,modrm),
- getXMMReg(gregOfRexRM(pfx,modrm)) );
- DIP("movdqu %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
- nameXMMReg(eregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
- DIP("movdqu %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf);
- }
- goto decode_success;
- }
-
- /* F2 0F D6 = MOVDQ2Q -- move from E (lo half xmm, not mem) to G (mmx). */
- if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xD6) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- do_MMX_preamble();
- putMMXReg( gregLO3ofRM(modrm),
- getXMMRegLane64( eregOfRexRM(pfx,modrm), 0 ));
- DIP("movdq2q %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- delta += 2+1;
- goto decode_success;
- } else {
- /* apparently no mem case for this insn */
- goto decode_failure;
- }
- }
-
- /* 66 0F 16 = MOVHPD -- move from mem to high half of XMM. */
- /* These seems identical to MOVHPS. This instruction encoding is
- completely crazy. */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x16) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- /* fall through; apparently reg-reg is not possible */
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 1/*upper lane*/,
- loadLE(Ity_I64, mkexpr(addr)) );
- DIP("movhpd %s,%s\n", dis_buf,
- nameXMMReg( gregOfRexRM(pfx,modrm) ));
- goto decode_success;
- }
- }
-
- /* 66 0F 17 = MOVHPD -- move from high half of XMM to mem. */
- /* Again, this seems identical to MOVHPS. */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x17) {
- if (!epartIsReg(insn[2])) {
- delta += 2;
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
- storeLE( mkexpr(addr),
- getXMMRegLane64( gregOfRexRM(pfx,insn[2]),
- 1/*upper lane*/ ) );
- DIP("movhpd %s,%s\n", nameXMMReg( gregOfRexRM(pfx,insn[2]) ),
- dis_buf);
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* 66 0F 12 = MOVLPD -- move from mem to low half of XMM. */
- /* Identical to MOVLPS ? */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x12) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- /* fall through; apparently reg-reg is not possible */
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- putXMMRegLane64( gregOfRexRM(pfx,modrm),
- 0/*lower lane*/,
- loadLE(Ity_I64, mkexpr(addr)) );
- DIP("movlpd %s, %s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx,modrm) ));
- goto decode_success;
- }
- }
-
- /* 66 0F 13 = MOVLPD -- move from low half of XMM to mem. */
- /* Identical to MOVLPS ? */
- if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x13) {
- modrm = getUChar(delta+2);
- if (!epartIsReg(modrm)) {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
- storeLE( mkexpr(addr),
- getXMMRegLane64( gregOfRexRM(pfx,modrm),
- 0/*lower lane*/ ) );
- DIP("movlpd %s, %s\n", nameXMMReg( gregOfRexRM(pfx,modrm) ),
- dis_buf);
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* 66 0F 50 = MOVMSKPD - move 2 sign bits from 2 x F64 in xmm(E) to
- 2 lowest bits of ireg(G) */
- if (have66noF2noF3(pfx) && (sz == 2 || sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x50) {
- /* sz == 8 is a kludge to handle insns with REX.W redundantly
- set to 1, which has been known to happen:
- 66 4c 0f 50 d9 rex64X movmskpd %xmm1,%r11d
- 20071106: see further comments on MOVMSKPS implementation above.
- */
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- Int src;
- t0 = newTemp(Ity_I32);
- t1 = newTemp(Ity_I32);
- delta += 2+1;
- src = eregOfRexRM(pfx,modrm);
- assign( t0, binop( Iop_And32,
- binop(Iop_Shr32, getXMMRegLane32(src,1), mkU8(31)),
- mkU32(1) ));
- assign( t1, binop( Iop_And32,
- binop(Iop_Shr32, getXMMRegLane32(src,3), mkU8(30)),
- mkU32(2) ));
- putIReg32( gregOfRexRM(pfx,modrm),
- binop(Iop_Or32, mkexpr(t0), mkexpr(t1))
- );
- DIP("movmskpd %s,%s\n", nameXMMReg(src),
- nameIReg32(gregOfRexRM(pfx,modrm)));
- goto decode_success;
- }
- /* else fall through */
- goto decode_failure;
- }
-
- /* 66 0F F7 = MASKMOVDQU -- store selected bytes of double quadword */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF7) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- IRTemp regD = newTemp(Ity_V128);
- IRTemp mask = newTemp(Ity_V128);
- IRTemp olddata = newTemp(Ity_V128);
- IRTemp newdata = newTemp(Ity_V128);
- addr = newTemp(Ity_I64);
-
- assign( addr, handleAddrOverrides( vbi, pfx, getIReg64(R_RDI) ));
- assign( regD, getXMMReg( gregOfRexRM(pfx,modrm) ));
-
- /* Unfortunately can't do the obvious thing with SarN8x16
- here since that can't be re-emitted as SSE2 code - no such
- insn. */
- assign(
- mask,
- binop(Iop_64HLtoV128,
- binop(Iop_SarN8x8,
- getXMMRegLane64( eregOfRexRM(pfx,modrm), 1 ),
- mkU8(7) ),
- binop(Iop_SarN8x8,
- getXMMRegLane64( eregOfRexRM(pfx,modrm), 0 ),
- mkU8(7) ) ));
- assign( olddata, loadLE( Ity_V128, mkexpr(addr) ));
- assign( newdata,
- binop(Iop_OrV128,
- binop(Iop_AndV128,
- mkexpr(regD),
- mkexpr(mask) ),
- binop(Iop_AndV128,
- mkexpr(olddata),
- unop(Iop_NotV128, mkexpr(mask)))) );
- storeLE( mkexpr(addr), mkexpr(newdata) );
-
- delta += 2+1;
- DIP("maskmovdqu %s,%s\n", nameXMMReg( eregOfRexRM(pfx,modrm) ),
- nameXMMReg( gregOfRexRM(pfx,modrm) ) );
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* 66 0F E7 = MOVNTDQ -- for us, just a plain SSE store. */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE7) {
- modrm = getUChar(delta+2);
- if (!epartIsReg(modrm)) {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
- DIP("movntdq %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
- goto decode_success;
- }
- /* else fall through */
- goto decode_failure;
- }
-
- /* 0F C3 = MOVNTI -- for us, just a plain ireg store. */
- if (haveNo66noF2noF3(pfx) &&
- insn[0] == 0x0F && insn[1] == 0xC3) {
- vassert(sz == 4 || sz == 8);
- modrm = getUChar(delta+2);
- if (!epartIsReg(modrm)) {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- storeLE( mkexpr(addr), getIRegG(sz, pfx, modrm) );
- DIP("movnti %s,%s\n", dis_buf,
- nameIRegG(sz, pfx, modrm));
- delta += 2+alen;
- goto decode_success;
- }
- /* else fall through */
- }
-
- /* 66 0F D6 = MOVQ -- move 64 bits from G (lo half xmm) to E (mem
- or lo half xmm). */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0xD6) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- /* fall through, awaiting test case */
- /* dst: lo half copied, hi half zeroed */
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- storeLE( mkexpr(addr),
- getXMMRegLane64( gregOfRexRM(pfx,modrm), 0 ));
- DIP("movq %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf );
- delta += 2+alen;
- goto decode_success;
- }
- }
-
- /* F3 0F D6 = MOVQ2DQ -- move from E (mmx) to G (lo half xmm, zero
- hi half). */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xD6) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- do_MMX_preamble();
- putXMMReg( gregOfRexRM(pfx,modrm),
- unop(Iop_64UtoV128, getMMXReg( eregLO3ofRM(modrm) )) );
- DIP("movq2dq %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- goto decode_success;
- } else {
- /* apparently no mem case for this insn */
- goto decode_failure;
- }
- }
-
- /* F3 0F 7E = MOVQ -- move 64 bits from E (mem or lo half xmm) to
- G (lo half xmm). Upper half of G is zeroed out. */
- /* F2 0F 10 = MOVSD -- move 64 bits from E (mem or lo half xmm) to
- G (lo half xmm). If E is mem, upper half of G is zeroed out.
- If E is reg, upper half of G is unchanged. */
- if ( (haveF2no66noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x10)
- ||
- (haveF3no66noF2(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x7E)
- ) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 0,
- getXMMRegLane64( eregOfRexRM(pfx,modrm), 0 ));
- if (insn[1] == 0x7E/*MOVQ*/) {
- /* zero bits 127:64 */
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 1, mkU64(0) );
- }
- DIP("movsd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- putXMMReg( gregOfRexRM(pfx,modrm), mkV128(0) );
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 0,
- loadLE(Ity_I64, mkexpr(addr)) );
- DIP("movsd %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
- }
- goto decode_success;
- }
-
- /* F2 0F 11 = MOVSD -- move 64 bits from G (lo half xmm) to E (mem
- or lo half xmm). */
- if (haveF2no66noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x11) {
- modrm = getUChar(delta+2);
- if (epartIsReg(modrm)) {
- putXMMRegLane64( eregOfRexRM(pfx,modrm), 0,
- getXMMRegLane64( gregOfRexRM(pfx,modrm), 0 ));
- DIP("movsd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
- nameXMMReg(eregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- storeLE( mkexpr(addr),
- getXMMRegLane64(gregOfRexRM(pfx,modrm), 0) );
- DIP("movsd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
- dis_buf);
- delta += 2+alen;
- }
- goto decode_success;
- }
-
- /* 66 0F 59 = MULPD -- mul 64Fx2 from R/M to R */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x59) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "mulpd", Iop_Mul64Fx2 );
- goto decode_success;
- }
-
- /* F2 0F 59 = MULSD -- mul 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x59) {
- delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta+2, "mulsd", Iop_Mul64F0x2 );
- goto decode_success;
- }
-
- /* 66 0F 56 = ORPD -- G = G and E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x56) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "orpd", Iop_OrV128 );
- goto decode_success;
- }
-
- /* 66 0F C6 /r ib = SHUFPD -- shuffle packed F64s */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xC6) {
- Int select;
- IRTemp sV = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp s1 = newTemp(Ity_I64);
- IRTemp s0 = newTemp(Ity_I64);
- IRTemp d1 = newTemp(Ity_I64);
- IRTemp d0 = newTemp(Ity_I64);
-
- modrm = insn[2];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- select = (Int)insn[3];
- delta += 2+2;
- DIP("shufpd $%d,%s,%s\n", select,
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 1 );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- select = (Int)insn[2+alen];
- delta += 3+alen;
- DIP("shufpd $%d,%s,%s\n", select,
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- assign( d1, unop(Iop_V128HIto64, mkexpr(dV)) );
- assign( d0, unop(Iop_V128to64, mkexpr(dV)) );
- assign( s1, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( s0, unop(Iop_V128to64, mkexpr(sV)) );
-
-# define SELD(n) mkexpr((n)==0 ? d0 : d1)
-# define SELS(n) mkexpr((n)==0 ? s0 : s1)
-
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128, SELS((select>>1)&1), SELD((select>>0)&1) )
- );
-
-# undef SELD
-# undef SELS
-
- goto decode_success;
- }
-
- /* 66 0F 51 = SQRTPD -- approx sqrt 64Fx2 from R/M to R */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x51) {
- delta = dis_SSE_E_to_G_unary_all( vbi, pfx, delta+2,
- "sqrtpd", Iop_Sqrt64Fx2 );
- goto decode_success;
- }
-
- /* F2 0F 51 = SQRTSD -- approx sqrt 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x51) {
- vassert(sz == 4);
- delta = dis_SSE_E_to_G_unary_lo64( vbi, pfx, delta+2,
- "sqrtsd", Iop_Sqrt64F0x2 );
- goto decode_success;
- }
-
- /* 66 0F 5C = SUBPD -- sub 64Fx2 from R/M to R */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x5C) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "subpd", Iop_Sub64Fx2 );
- goto decode_success;
- }
-
- /* F2 0F 5C = SUBSD -- sub 64F0x2 from R/M to R */
- if (haveF2no66noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x5C) {
- delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta+2, "subsd", Iop_Sub64F0x2 );
- goto decode_success;
- }
-
- /* 66 0F 15 = UNPCKHPD -- unpack and interleave high part F64s */
- /* 66 0F 14 = UNPCKLPD -- unpack and interleave low part F64s */
- /* These just appear to be special cases of SHUFPS */
- if (have66noF2noF3(pfx)
- && sz == 2 /* could be 8 if rex also present */
- && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) {
- IRTemp s1 = newTemp(Ity_I64);
- IRTemp s0 = newTemp(Ity_I64);
- IRTemp d1 = newTemp(Ity_I64);
- IRTemp d0 = newTemp(Ity_I64);
- IRTemp sV = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- Bool hi = toBool(insn[1] == 0x15);
-
- modrm = insn[2];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("unpck%sps %s,%s\n", hi ? "h" : "l",
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ assign(f64lo, getXMMRegLane64F(eregOfRexRM(pfx,modrm), 0));
+ DIP("%scvt%ssd2si %s,%s\n", isAvx ? "v" : "", r2zero ? "t" : "",
nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 2+alen;
- DIP("unpck%sps %s,%s\n", hi ? "h" : "l",
+ nameIReg(sz, gregOfRexRM(pfx,modrm),
+ False));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(f64lo, loadLE(Ity_F64, mkexpr(addr)));
+ delta += alen;
+ DIP("%scvt%ssd2si %s,%s\n", isAvx ? "v" : "", r2zero ? "t" : "",
dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- assign( d1, unop(Iop_V128HIto64, mkexpr(dV)) );
- assign( d0, unop(Iop_V128to64, mkexpr(dV)) );
- assign( s1, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( s0, unop(Iop_V128to64, mkexpr(sV)) );
-
- if (hi) {
- putXMMReg( gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128, mkexpr(s1), mkexpr(d1)) );
- } else {
- putXMMReg( gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128, mkexpr(s0), mkexpr(d0)) );
- }
-
- goto decode_success;
+ nameIReg(sz, gregOfRexRM(pfx,modrm),
+ False));
}
- /* 66 0F 57 = XORPD -- G = G xor E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x57) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "xorpd", Iop_XorV128 );
- goto decode_success;
+ if (r2zero) {
+ assign( rmode, mkU32((UInt)Irrm_ZERO) );
+ } else {
+ assign( rmode, get_sse_roundingmode() );
}
- /* 66 0F 6B = PACKSSDW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x6B) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "packssdw",
- Iop_QNarrowBin32Sto16Sx8, True );
- goto decode_success;
+ if (sz == 4) {
+ putIReg32( gregOfRexRM(pfx,modrm),
+ binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo)) );
+ } else {
+ vassert(sz == 8);
+ putIReg64( gregOfRexRM(pfx,modrm),
+ binop( Iop_F64toI64S, mkexpr(rmode), mkexpr(f64lo)) );
}
- /* 66 0F 63 = PACKSSWB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x63) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "packsswb",
- Iop_QNarrowBin16Sto8Sx16, True );
- goto decode_success;
+ return delta;
+}
+
+
+static Long dis_CVTxSS2SI ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, UChar opc, Int sz )
+{
+ vassert(opc == 0x2D/*CVTSS2SI*/ || opc == 0x2C/*CVTTSS2SI*/);
+ HChar dis_buf[50];
+ Int alen = 0;
+ UChar modrm = getUChar(delta);
+ IRTemp addr = IRTemp_INVALID;
+ IRTemp rmode = newTemp(Ity_I32);
+ IRTemp f32lo = newTemp(Ity_F32);
+ Bool r2zero = toBool(opc == 0x2C);
+
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ assign(f32lo, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 0));
+ DIP("%scvt%sss2si %s,%s\n", isAvx ? "v" : "", r2zero ? "t" : "",
+ nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameIReg(sz, gregOfRexRM(pfx,modrm),
+ False));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(f32lo, loadLE(Ity_F32, mkexpr(addr)));
+ delta += alen;
+ DIP("%scvt%sss2si %s,%s\n", isAvx ? "v" : "", r2zero ? "t" : "",
+ dis_buf,
+ nameIReg(sz, gregOfRexRM(pfx,modrm),
+ False));
}
- /* 66 0F 67 = PACKUSWB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x67) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "packuswb",
- Iop_QNarrowBin16Sto8Ux16, True );
- goto decode_success;
+ if (r2zero) {
+ assign( rmode, mkU32((UInt)Irrm_ZERO) );
+ } else {
+ assign( rmode, get_sse_roundingmode() );
}
- /* 66 0F FC = PADDB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFC) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "paddb", Iop_Add8x16, False );
- goto decode_success;
+ if (sz == 4) {
+ putIReg32( gregOfRexRM(pfx,modrm),
+ binop( Iop_F64toI32S,
+ mkexpr(rmode),
+ unop(Iop_F32toF64, mkexpr(f32lo))) );
+ } else {
+ vassert(sz == 8);
+ putIReg64( gregOfRexRM(pfx,modrm),
+ binop( Iop_F64toI64S,
+ mkexpr(rmode),
+ unop(Iop_F32toF64, mkexpr(f32lo))) );
+ }
+
+ return delta;
+}
+
+
+static Long dis_CVTPS2PD_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp f32lo = newTemp(Ity_F32);
+ IRTemp f32hi = newTemp(Ity_F32);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( f32lo, getXMMRegLane32F(rE, 0) );
+ assign( f32hi, getXMMRegLane32F(rE, 1) );
+ delta += 1;
+ DIP("%scvtps2pd %s,%s\n",
+ isAvx ? "v" : "", nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( f32lo, loadLE(Ity_F32, mkexpr(addr)) );
+ assign( f32hi, loadLE(Ity_F32,
+ binop(Iop_Add64,mkexpr(addr),mkU64(4))) );
+ delta += alen;
+ DIP("%scvtps2pd %s,%s\n",
+ isAvx ? "v" : "", dis_buf, nameXMMReg(rG));
}
- /* 66 0F FE = PADDD */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFE) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "paddd", Iop_Add32x4, False );
- goto decode_success;
+ putXMMRegLane64F( rG, 1, unop(Iop_F32toF64, mkexpr(f32hi)) );
+ putXMMRegLane64F( rG, 0, unop(Iop_F32toF64, mkexpr(f32lo)) );
+ if (isAvx)
+ putYMMRegLane128( rG, 1, mkV128(0));
+ return delta;
+}
+
+
+static Long dis_CVTPS2PD_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp f32_0 = newTemp(Ity_F32);
+ IRTemp f32_1 = newTemp(Ity_F32);
+ IRTemp f32_2 = newTemp(Ity_F32);
+ IRTemp f32_3 = newTemp(Ity_F32);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( f32_0, getXMMRegLane32F(rE, 0) );
+ assign( f32_1, getXMMRegLane32F(rE, 1) );
+ assign( f32_2, getXMMRegLane32F(rE, 2) );
+ assign( f32_3, getXMMRegLane32F(rE, 3) );
+ delta += 1;
+ DIP("vcvtps2pd %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( f32_0, loadLE(Ity_F32, mkexpr(addr)) );
+ assign( f32_1, loadLE(Ity_F32,
+ binop(Iop_Add64,mkexpr(addr),mkU64(4))) );
+ assign( f32_2, loadLE(Ity_F32,
+ binop(Iop_Add64,mkexpr(addr),mkU64(8))) );
+ assign( f32_3, loadLE(Ity_F32,
+ binop(Iop_Add64,mkexpr(addr),mkU64(12))) );
+ delta += alen;
+ DIP("vcvtps2pd %s,%s\n", dis_buf, nameYMMReg(rG));
}
- /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
- /* 0F D4 = PADDQ -- add 64x1 */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xD4) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "paddq", False );
- goto decode_success;
+ putYMMRegLane64F( rG, 3, unop(Iop_F32toF64, mkexpr(f32_3)) );
+ putYMMRegLane64F( rG, 2, unop(Iop_F32toF64, mkexpr(f32_2)) );
+ putYMMRegLane64F( rG, 1, unop(Iop_F32toF64, mkexpr(f32_1)) );
+ putYMMRegLane64F( rG, 0, unop(Iop_F32toF64, mkexpr(f32_0)) );
+ return delta;
+}
+
+
+static Long dis_CVTPD2PS_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp argV = newTemp(Ity_V128);
+ IRTemp rmode = newTemp(Ity_I32);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( argV, getXMMReg(rE) );
+ delta += 1;
+ DIP("%scvtpd2ps %s,%s\n", isAvx ? "v" : "",
+ nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("%scvtpd2ps %s,%s\n", isAvx ? "v" : "",
+ dis_buf, nameXMMReg(rG) );
+ }
+
+ assign( rmode, get_sse_roundingmode() );
+ IRTemp t0 = newTemp(Ity_F64);
+ IRTemp t1 = newTemp(Ity_F64);
+ assign( t0, unop(Iop_ReinterpI64asF64,
+ unop(Iop_V128to64, mkexpr(argV))) );
+ assign( t1, unop(Iop_ReinterpI64asF64,
+ unop(Iop_V128HIto64, mkexpr(argV))) );
+
+# define CVT(_t) binop( Iop_F64toF32, mkexpr(rmode), mkexpr(_t) )
+ putXMMRegLane32( rG, 3, mkU32(0) );
+ putXMMRegLane32( rG, 2, mkU32(0) );
+ putXMMRegLane32F( rG, 1, CVT(t1) );
+ putXMMRegLane32F( rG, 0, CVT(t0) );
+# undef CVT
+ if (isAvx)
+ putYMMRegLane128( rG, 1, mkV128(0) );
+
+ return delta;
+}
+
+
+static Long dis_CVTxPS2DQ_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, Bool r2zero )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ IRTemp argV = newTemp(Ity_V128);
+ IRTemp rmode = newTemp(Ity_I32);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp t0, t1, t2, t3;
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( argV, getXMMReg(rE) );
+ delta += 1;
+ DIP("%scvt%sps2dq %s,%s\n",
+ isAvx ? "v" : "", r2zero ? "t" : "", nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("%scvt%sps2dq %s,%s\n",
+ isAvx ? "v" : "", r2zero ? "t" : "", dis_buf, nameXMMReg(rG) );
}
- /* 66 0F D4 = PADDQ */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD4) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "paddq", Iop_Add64x2, False );
- goto decode_success;
+ assign( rmode, r2zero ? mkU32((UInt)Irrm_ZERO)
+ : get_sse_roundingmode() );
+ t0 = t1 = t2 = t3 = IRTemp_INVALID;
+ breakupV128to32s( argV, &t3, &t2, &t1, &t0 );
+ /* This is less than ideal. If it turns out to be a performance
+ bottleneck it can be improved. */
+# define CVT(_t) \
+ binop( Iop_F64toI32S, \
+ mkexpr(rmode), \
+ unop( Iop_F32toF64, \
+ unop( Iop_ReinterpI32asF32, mkexpr(_t))) )
+
+ putXMMRegLane32( rG, 3, CVT(t3) );
+ putXMMRegLane32( rG, 2, CVT(t2) );
+ putXMMRegLane32( rG, 1, CVT(t1) );
+ putXMMRegLane32( rG, 0, CVT(t0) );
+# undef CVT
+ if (isAvx)
+ putYMMRegLane128( rG, 1, mkV128(0) );
+
+ return delta;
+}
+
+
+static Long dis_CVTxPS2DQ_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool r2zero )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ IRTemp argV = newTemp(Ity_V256);
+ IRTemp rmode = newTemp(Ity_I32);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp t0, t1, t2, t3, t4, t5, t6, t7;
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( argV, getYMMReg(rE) );
+ delta += 1;
+ DIP("vcvt%sps2dq %s,%s\n",
+ r2zero ? "t" : "", nameYMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argV, loadLE(Ity_V256, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvt%sps2dq %s,%s\n",
+ r2zero ? "t" : "", dis_buf, nameYMMReg(rG) );
}
- /* 66 0F FD = PADDW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFD) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "paddw", Iop_Add16x8, False );
- goto decode_success;
+ assign( rmode, r2zero ? mkU32((UInt)Irrm_ZERO)
+ : get_sse_roundingmode() );
+ t0 = t1 = t2 = t3 = t4 = t5 = t6 = t7 = IRTemp_INVALID;
+ breakupV256to32s( argV, &t7, &t6, &t5, &t4, &t3, &t2, &t1, &t0 );
+ /* This is less than ideal. If it turns out to be a performance
+ bottleneck it can be improved. */
+# define CVT(_t) \
+ binop( Iop_F64toI32S, \
+ mkexpr(rmode), \
+ unop( Iop_F32toF64, \
+ unop( Iop_ReinterpI32asF32, mkexpr(_t))) )
+
+ putYMMRegLane32( rG, 7, CVT(t7) );
+ putYMMRegLane32( rG, 6, CVT(t6) );
+ putYMMRegLane32( rG, 5, CVT(t5) );
+ putYMMRegLane32( rG, 4, CVT(t4) );
+ putYMMRegLane32( rG, 3, CVT(t3) );
+ putYMMRegLane32( rG, 2, CVT(t2) );
+ putYMMRegLane32( rG, 1, CVT(t1) );
+ putYMMRegLane32( rG, 0, CVT(t0) );
+# undef CVT
+
+ return delta;
+}
+
+
+static Long dis_CVTxPD2DQ_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, Bool r2zero )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ IRTemp argV = newTemp(Ity_V128);
+ IRTemp rmode = newTemp(Ity_I32);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp t0, t1;
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( argV, getXMMReg(rE) );
+ delta += 1;
+ DIP("%scvt%spd2dq %s,%s\n",
+ isAvx ? "v" : "", r2zero ? "t" : "", nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("%scvt%spd2dqx %s,%s\n",
+ isAvx ? "v" : "", r2zero ? "t" : "", dis_buf, nameXMMReg(rG) );
}
- /* 66 0F EC = PADDSB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEC) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "paddsb", Iop_QAdd8Sx16, False );
- goto decode_success;
+ if (r2zero) {
+ assign(rmode, mkU32((UInt)Irrm_ZERO) );
+ } else {
+ assign( rmode, get_sse_roundingmode() );
}
- /* 66 0F ED = PADDSW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xED) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "paddsw", Iop_QAdd16Sx8, False );
- goto decode_success;
+ t0 = newTemp(Ity_F64);
+ t1 = newTemp(Ity_F64);
+ assign( t0, unop(Iop_ReinterpI64asF64,
+ unop(Iop_V128to64, mkexpr(argV))) );
+ assign( t1, unop(Iop_ReinterpI64asF64,
+ unop(Iop_V128HIto64, mkexpr(argV))) );
+
+# define CVT(_t) binop( Iop_F64toI32S, \
+ mkexpr(rmode), \
+ mkexpr(_t) )
+
+ putXMMRegLane32( rG, 3, mkU32(0) );
+ putXMMRegLane32( rG, 2, mkU32(0) );
+ putXMMRegLane32( rG, 1, CVT(t1) );
+ putXMMRegLane32( rG, 0, CVT(t0) );
+# undef CVT
+ if (isAvx)
+ putYMMRegLane128( rG, 1, mkV128(0) );
+
+ return delta;
+}
+
+
+static Long dis_CVTxPD2DQ_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool r2zero )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ IRTemp argV = newTemp(Ity_V256);
+ IRTemp rmode = newTemp(Ity_I32);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp t0, t1, t2, t3;
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( argV, getYMMReg(rE) );
+ delta += 1;
+ DIP("vcvt%spd2dq %s,%s\n",
+ r2zero ? "t" : "", nameYMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argV, loadLE(Ity_V256, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvt%spd2dqy %s,%s\n",
+ r2zero ? "t" : "", dis_buf, nameXMMReg(rG) );
}
- /* 66 0F DC = PADDUSB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDC) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "paddusb", Iop_QAdd8Ux16, False );
- goto decode_success;
+ if (r2zero) {
+ assign(rmode, mkU32((UInt)Irrm_ZERO) );
+ } else {
+ assign( rmode, get_sse_roundingmode() );
}
- /* 66 0F DD = PADDUSW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDD) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "paddusw", Iop_QAdd16Ux8, False );
- goto decode_success;
+ t0 = IRTemp_INVALID;
+ t1 = IRTemp_INVALID;
+ t2 = IRTemp_INVALID;
+ t3 = IRTemp_INVALID;
+ breakupV256to64s( argV, &t3, &t2, &t1, &t0 );
+
+# define CVT(_t) binop( Iop_F64toI32S, \
+ mkexpr(rmode), \
+ unop( Iop_ReinterpI64asF64, \
+ mkexpr(_t) ) )
+
+ putXMMRegLane32( rG, 3, CVT(t3) );
+ putXMMRegLane32( rG, 2, CVT(t2) );
+ putXMMRegLane32( rG, 1, CVT(t1) );
+ putXMMRegLane32( rG, 0, CVT(t0) );
+# undef CVT
+ putYMMRegLane128( rG, 1, mkV128(0) );
+
+ return delta;
+}
+
+
+static Long dis_CVTDQ2PS_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ IRTemp argV = newTemp(Ity_V128);
+ IRTemp rmode = newTemp(Ity_I32);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp t0, t1, t2, t3;
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( argV, getXMMReg(rE) );
+ delta += 1;
+ DIP("%scvtdq2ps %s,%s\n",
+ isAvx ? "v" : "", nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("%scvtdq2ps %s,%s\n",
+ isAvx ? "v" : "", dis_buf, nameXMMReg(rG) );
}
- /* 66 0F DB = PAND */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDB) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "pand", Iop_AndV128 );
- goto decode_success;
+ assign( rmode, get_sse_roundingmode() );
+ t0 = IRTemp_INVALID;
+ t1 = IRTemp_INVALID;
+ t2 = IRTemp_INVALID;
+ t3 = IRTemp_INVALID;
+ breakupV128to32s( argV, &t3, &t2, &t1, &t0 );
+
+# define CVT(_t) binop( Iop_F64toF32, \
+ mkexpr(rmode), \
+ unop(Iop_I32StoF64,mkexpr(_t)))
+
+ putXMMRegLane32F( rG, 3, CVT(t3) );
+ putXMMRegLane32F( rG, 2, CVT(t2) );
+ putXMMRegLane32F( rG, 1, CVT(t1) );
+ putXMMRegLane32F( rG, 0, CVT(t0) );
+# undef CVT
+ if (isAvx)
+ putYMMRegLane128( rG, 1, mkV128(0) );
+
+ return delta;
+}
+
+static Long dis_CVTDQ2PS_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ IRTemp argV = newTemp(Ity_V256);
+ IRTemp rmode = newTemp(Ity_I32);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp t0, t1, t2, t3, t4, t5, t6, t7;
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( argV, getYMMReg(rE) );
+ delta += 1;
+ DIP("vcvtdq2ps %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argV, loadLE(Ity_V256, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvtdq2ps %s,%s\n", dis_buf, nameYMMReg(rG) );
}
- /* 66 0F DF = PANDN */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDF) {
- delta = dis_SSE_E_to_G_all_invG( vbi, pfx, delta+2, "pandn", Iop_AndV128 );
- goto decode_success;
- }
+ assign( rmode, get_sse_roundingmode() );
+ t0 = IRTemp_INVALID;
+ t1 = IRTemp_INVALID;
+ t2 = IRTemp_INVALID;
+ t3 = IRTemp_INVALID;
+ t4 = IRTemp_INVALID;
+ t5 = IRTemp_INVALID;
+ t6 = IRTemp_INVALID;
+ t7 = IRTemp_INVALID;
+ breakupV256to32s( argV, &t7, &t6, &t5, &t4, &t3, &t2, &t1, &t0 );
- /* 66 0F E0 = PAVGB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE0) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pavgb", Iop_Avg8Ux16, False );
- goto decode_success;
- }
+# define CVT(_t) binop( Iop_F64toF32, \
+ mkexpr(rmode), \
+ unop(Iop_I32StoF64,mkexpr(_t)))
+
+ putYMMRegLane32F( rG, 7, CVT(t7) );
+ putYMMRegLane32F( rG, 6, CVT(t6) );
+ putYMMRegLane32F( rG, 5, CVT(t5) );
+ putYMMRegLane32F( rG, 4, CVT(t4) );
+ putYMMRegLane32F( rG, 3, CVT(t3) );
+ putYMMRegLane32F( rG, 2, CVT(t2) );
+ putYMMRegLane32F( rG, 1, CVT(t1) );
+ putYMMRegLane32F( rG, 0, CVT(t0) );
+# undef CVT
- /* 66 0F E3 = PAVGW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE3) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pavgw", Iop_Avg16Ux8, False );
- goto decode_success;
- }
+ return delta;
+}
- /* 66 0F 74 = PCMPEQB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x74) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pcmpeqb", Iop_CmpEQ8x16, False );
- goto decode_success;
- }
- /* 66 0F 76 = PCMPEQD */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x76) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pcmpeqd", Iop_CmpEQ32x4, False );
- goto decode_success;
- }
-
- /* 66 0F 75 = PCMPEQW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x75) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pcmpeqw", Iop_CmpEQ16x8, False );
- goto decode_success;
- }
-
- /* 66 0F 64 = PCMPGTB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x64) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pcmpgtb", Iop_CmpGT8Sx16, False );
- goto decode_success;
- }
-
- /* 66 0F 66 = PCMPGTD */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x66) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pcmpgtd", Iop_CmpGT32Sx4, False );
- goto decode_success;
- }
-
- /* 66 0F 65 = PCMPGTW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x65) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pcmpgtw", Iop_CmpGT16Sx8, False );
- goto decode_success;
- }
-
- /* 66 0F C5 = PEXTRW -- extract 16-bit field from xmm(E) and put
- zero-extend of it in ireg(G). */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0xC5) {
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- t5 = newTemp(Ity_V128);
- t4 = newTemp(Ity_I16);
- assign(t5, getXMMReg(eregOfRexRM(pfx,modrm)));
- breakup128to32s( t5, &t3, &t2, &t1, &t0 );
- switch (insn[3] & 7) {
- case 0: assign(t4, unop(Iop_32to16, mkexpr(t0))); break;
- case 1: assign(t4, unop(Iop_32HIto16, mkexpr(t0))); break;
- case 2: assign(t4, unop(Iop_32to16, mkexpr(t1))); break;
- case 3: assign(t4, unop(Iop_32HIto16, mkexpr(t1))); break;
- case 4: assign(t4, unop(Iop_32to16, mkexpr(t2))); break;
- case 5: assign(t4, unop(Iop_32HIto16, mkexpr(t2))); break;
- case 6: assign(t4, unop(Iop_32to16, mkexpr(t3))); break;
- case 7: assign(t4, unop(Iop_32HIto16, mkexpr(t3))); break;
- default: vassert(0);
- }
- putIReg32(gregOfRexRM(pfx,modrm), unop(Iop_16Uto32, mkexpr(t4)));
- DIP("pextrw $%d,%s,%s\n",
- (Int)insn[3], nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameIReg32(gregOfRexRM(pfx,modrm)));
- delta += 4;
- goto decode_success;
- }
- /* else fall through */
- /* note, if memory case is ever filled in, there is 1 byte after
- amode */
- }
-
- /* 66 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
- put it into the specified lane of xmm(G). */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0xC4) {
- Int lane;
- t4 = newTemp(Ity_I16);
- modrm = insn[2];
-
- if (epartIsReg(modrm)) {
- assign(t4, getIReg16(eregOfRexRM(pfx,modrm)));
- delta += 3+1;
- lane = insn[3+1-1];
- DIP("pinsrw $%d,%s,%s\n", (Int)lane,
- nameIReg16(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf,
- 1/*byte after the amode*/ );
- delta += 3+alen;
- lane = insn[3+alen-1];
- assign(t4, loadLE(Ity_I16, mkexpr(addr)));
- DIP("pinsrw $%d,%s,%s\n", (Int)lane,
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- putXMMRegLane16( gregOfRexRM(pfx,modrm), lane & 7, mkexpr(t4) );
- goto decode_success;
- }
-
- /* 66 0F F5 = PMADDWD -- Multiply and add packed integers from
- E(xmm or mem) to G(xmm) */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF5) {
- IRTemp s1V = newTemp(Ity_V128);
- IRTemp s2V = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp s1Hi = newTemp(Ity_I64);
- IRTemp s1Lo = newTemp(Ity_I64);
- IRTemp s2Hi = newTemp(Ity_I64);
- IRTemp s2Lo = newTemp(Ity_I64);
- IRTemp dHi = newTemp(Ity_I64);
- IRTemp dLo = newTemp(Ity_I64);
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( s1V, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("pmaddwd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( s1V, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 2+alen;
- DIP("pmaddwd %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
- assign( s2V, getXMMReg(gregOfRexRM(pfx,modrm)) );
- assign( s1Hi, unop(Iop_V128HIto64, mkexpr(s1V)) );
- assign( s1Lo, unop(Iop_V128to64, mkexpr(s1V)) );
- assign( s2Hi, unop(Iop_V128HIto64, mkexpr(s2V)) );
- assign( s2Lo, unop(Iop_V128to64, mkexpr(s2V)) );
- assign( dHi, mkIRExprCCall(
- Ity_I64, 0/*regparms*/,
- "amd64g_calculate_mmx_pmaddwd",
- &amd64g_calculate_mmx_pmaddwd,
- mkIRExprVec_2( mkexpr(s1Hi), mkexpr(s2Hi))
- ));
- assign( dLo, mkIRExprCCall(
- Ity_I64, 0/*regparms*/,
- "amd64g_calculate_mmx_pmaddwd",
- &amd64g_calculate_mmx_pmaddwd,
- mkIRExprVec_2( mkexpr(s1Lo), mkexpr(s2Lo))
- ));
- assign( dV, binop(Iop_64HLtoV128, mkexpr(dHi), mkexpr(dLo))) ;
- putXMMReg(gregOfRexRM(pfx,modrm), mkexpr(dV));
- goto decode_success;
- }
-
- /* 66 0F EE = PMAXSW -- 16x8 signed max */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEE) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pmaxsw", Iop_Max16Sx8, False );
- goto decode_success;
- }
-
- /* 66 0F DE = PMAXUB -- 8x16 unsigned max */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDE) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pmaxub", Iop_Max8Ux16, False );
- goto decode_success;
- }
-
- /* 66 0F EA = PMINSW -- 16x8 signed min */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEA) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pminsw", Iop_Min16Sx8, False );
- goto decode_success;
- }
-
- /* 66 0F DA = PMINUB -- 8x16 unsigned min */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDA) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pminub", Iop_Min8Ux16, False );
- goto decode_success;
- }
-
- /* 66 0F D7 = PMOVMSKB -- extract sign bits from each of 16 lanes in
- xmm(E), turn them into a byte, and put zero-extend of it in
- ireg(G). Doing this directly is just too cumbersome; give up
- therefore and call a helper. */
+static Long dis_PMOVMSKB_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
/* UInt x86g_calculate_sse_pmovmskb ( ULong w64hi, ULong w64lo ); */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0xD7) {
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- assign(t0, getXMMRegLane64(eregOfRexRM(pfx,modrm), 0));
- assign(t1, getXMMRegLane64(eregOfRexRM(pfx,modrm), 1));
- t5 = newTemp(Ity_I64);
- assign(t5, mkIRExprCCall(
- Ity_I64, 0/*regparms*/,
- "amd64g_calculate_sse_pmovmskb",
- &amd64g_calculate_sse_pmovmskb,
- mkIRExprVec_2( mkexpr(t1), mkexpr(t0) )));
- putIReg32(gregOfRexRM(pfx,modrm), unop(Iop_64to32,mkexpr(t5)));
- DIP("pmovmskb %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameIReg32(gregOfRexRM(pfx,modrm)));
- delta += 3;
- goto decode_success;
- }
- /* else fall through */
+ UChar modrm = getUChar(delta);
+ vassert(epartIsReg(modrm)); /* ensured by caller */
+ UInt rE = eregOfRexRM(pfx,modrm);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp t0 = newTemp(Ity_I64);
+ IRTemp t1 = newTemp(Ity_I64);
+ IRTemp t5 = newTemp(Ity_I64);
+ assign(t0, getXMMRegLane64(rE, 0));
+ assign(t1, getXMMRegLane64(rE, 1));
+ assign(t5, mkIRExprCCall( Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_sse_pmovmskb",
+ &amd64g_calculate_sse_pmovmskb,
+ mkIRExprVec_2( mkexpr(t1), mkexpr(t0) )));
+ putIReg32(rG, unop(Iop_64to32,mkexpr(t5)));
+ DIP("%spmovmskb %s,%s\n", isAvx ? "v" : "", nameXMMReg(rE),
+ nameIReg32(rG));
+ delta += 1;
+ return delta;
+}
+
+
+/* FIXME: why not just use InterleaveLO / InterleaveHI? I think the
+ relevant ops are "xIsH ? InterleaveHI32x4 : InterleaveLO32x4". */
+/* Does the maths for 128 bit versions of UNPCKLPS and UNPCKHPS */
+static IRTemp math_UNPCKxPS_128 ( IRTemp sV, IRTemp dV, Bool xIsH )
+{
+ IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
+ s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
+ breakupV128to32s( dV, &d3, &d2, &d1, &d0 );
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, xIsH ? mkV128from32s( s3, d3, s2, d2 )
+ : mkV128from32s( s1, d1, s0, d0 ));
+ return res;
+}
+
+
+/* FIXME: why not just use InterleaveLO / InterleaveHI ?? */
+/* Does the maths for 128 bit versions of UNPCKLPD and UNPCKHPD */
+static IRTemp math_UNPCKxPD_128 ( IRTemp sV, IRTemp dV, Bool xIsH )
+{
+ IRTemp s1 = newTemp(Ity_I64);
+ IRTemp s0 = newTemp(Ity_I64);
+ IRTemp d1 = newTemp(Ity_I64);
+ IRTemp d0 = newTemp(Ity_I64);
+ assign( d1, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( d0, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( s1, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( s0, unop(Iop_V128to64, mkexpr(sV)) );
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, xIsH ? binop(Iop_64HLtoV128, mkexpr(s1), mkexpr(d1))
+ : binop(Iop_64HLtoV128, mkexpr(s0), mkexpr(d0)));
+ return res;
+}
+
+
+/* Does the maths for 256 bit versions of UNPCKLPD and UNPCKHPD.
+ Doesn't seem like this fits in either of the Iop_Interleave{LO,HI}
+ or the Iop_Cat{Odd,Even}Lanes idioms, hence just do it the stupid
+ way. */
+static IRTemp math_UNPCKxPD_256 ( IRTemp sV, IRTemp dV, Bool xIsH )
+{
+ IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
+ s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
+ breakupV256to64s( dV, &d3, &d2, &d1, &d0 );
+ breakupV256to64s( sV, &s3, &s2, &s1, &s0 );
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, xIsH
+ ? IRExpr_Qop(Iop_64x4toV256, mkexpr(s3), mkexpr(d3),
+ mkexpr(s1), mkexpr(d1))
+ : IRExpr_Qop(Iop_64x4toV256, mkexpr(s2), mkexpr(d2),
+ mkexpr(s0), mkexpr(d0)));
+ return res;
+}
+
+
+/* FIXME: this is really bad. Surely can do something better here?
+ One observation is that the steering in the upper and lower 128 bit
+ halves is the same as with math_UNPCKxPS_128, so we simply split
+ into two halves, and use that. Consequently any improvement in
+ math_UNPCKxPS_128 (probably, to use interleave-style primops)
+ benefits this too. */
+static IRTemp math_UNPCKxPS_256 ( IRTemp sV, IRTemp dV, Bool xIsH )
+{
+ IRTemp sVhi = IRTemp_INVALID, sVlo = IRTemp_INVALID;
+ IRTemp dVhi = IRTemp_INVALID, dVlo = IRTemp_INVALID;
+ breakupV256toV128s( sV, &sVhi, &sVlo );
+ breakupV256toV128s( dV, &dVhi, &dVlo );
+ IRTemp rVhi = math_UNPCKxPS_128(sVhi, dVhi, xIsH);
+ IRTemp rVlo = math_UNPCKxPS_128(sVlo, dVlo, xIsH);
+ IRTemp rV = newTemp(Ity_V256);
+ assign(rV, binop(Iop_V128HLtoV256, mkexpr(rVhi), mkexpr(rVlo)));
+ return rV;
+}
+
+
+static IRTemp math_SHUFPS_128 ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
+ s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
+ vassert(imm8 < 256);
+
+ breakupV128to32s( dV, &d3, &d2, &d1, &d0 );
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+
+# define SELD(n) ((n)==0 ? d0 : ((n)==1 ? d1 : ((n)==2 ? d2 : d3)))
+# define SELS(n) ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3)))
+ IRTemp res = newTemp(Ity_V128);
+ assign(res,
+ mkV128from32s( SELS((imm8>>6)&3), SELS((imm8>>4)&3),
+ SELD((imm8>>2)&3), SELD((imm8>>0)&3) ) );
+# undef SELD
+# undef SELS
+ return res;
+}
+
+
+/* 256-bit SHUFPS appears to steer each of the 128-bit halves
+ identically. Hence do the clueless thing and use math_SHUFPS_128
+ twice. */
+static IRTemp math_SHUFPS_256 ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ IRTemp sVhi = IRTemp_INVALID, sVlo = IRTemp_INVALID;
+ IRTemp dVhi = IRTemp_INVALID, dVlo = IRTemp_INVALID;
+ breakupV256toV128s( sV, &sVhi, &sVlo );
+ breakupV256toV128s( dV, &dVhi, &dVlo );
+ IRTemp rVhi = math_SHUFPS_128(sVhi, dVhi, imm8);
+ IRTemp rVlo = math_SHUFPS_128(sVlo, dVlo, imm8);
+ IRTemp rV = newTemp(Ity_V256);
+ assign(rV, binop(Iop_V128HLtoV256, mkexpr(rVhi), mkexpr(rVlo)));
+ return rV;
+}
+
+
+static IRTemp math_SHUFPD_128 ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ IRTemp s1 = newTemp(Ity_I64);
+ IRTemp s0 = newTemp(Ity_I64);
+ IRTemp d1 = newTemp(Ity_I64);
+ IRTemp d0 = newTemp(Ity_I64);
+
+ assign( d1, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( d0, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( s1, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( s0, unop(Iop_V128to64, mkexpr(sV)) );
+
+# define SELD(n) mkexpr((n)==0 ? d0 : d1)
+# define SELS(n) mkexpr((n)==0 ? s0 : s1)
+
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop( Iop_64HLtoV128,
+ SELS((imm8>>1)&1), SELD((imm8>>0)&1) ) );
+
+# undef SELD
+# undef SELS
+ return res;
+}
+
+
+static IRTemp math_SHUFPD_256 ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ IRTemp sVhi = IRTemp_INVALID, sVlo = IRTemp_INVALID;
+ IRTemp dVhi = IRTemp_INVALID, dVlo = IRTemp_INVALID;
+ breakupV256toV128s( sV, &sVhi, &sVlo );
+ breakupV256toV128s( dV, &dVhi, &dVlo );
+ IRTemp rVhi = math_SHUFPD_128(sVhi, dVhi, (imm8 >> 2) & 3);
+ IRTemp rVlo = math_SHUFPD_128(sVlo, dVlo, imm8 & 3);
+ IRTemp rV = newTemp(Ity_V256);
+ assign(rV, binop(Iop_V128HLtoV256, mkexpr(rVhi), mkexpr(rVlo)));
+ return rV;
+}
+
+
+static IRTemp math_BLENDPD_128 ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ UShort imm8_mask_16;
+ IRTemp imm8_mask = newTemp(Ity_V128);
+
+ switch( imm8 & 3 ) {
+ case 0: imm8_mask_16 = 0x0000; break;
+ case 1: imm8_mask_16 = 0x00FF; break;
+ case 2: imm8_mask_16 = 0xFF00; break;
+ case 3: imm8_mask_16 = 0xFFFF; break;
+ default: vassert(0); break;
}
+ assign( imm8_mask, mkV128( imm8_mask_16 ) );
- /* 66 0F E4 = PMULHUW -- 16x8 hi-half of unsigned widening multiply */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE4) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pmulhuw", Iop_MulHi16Ux8, False );
- goto decode_success;
+ IRTemp res = newTemp(Ity_V128);
+ assign ( res, binop( Iop_OrV128,
+ binop( Iop_AndV128, mkexpr(sV),
+ mkexpr(imm8_mask) ),
+ binop( Iop_AndV128, mkexpr(dV),
+ unop( Iop_NotV128, mkexpr(imm8_mask) ) ) ) );
+ return res;
+}
+
+
+static IRTemp math_BLENDPD_256 ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ IRTemp sVhi = IRTemp_INVALID, sVlo = IRTemp_INVALID;
+ IRTemp dVhi = IRTemp_INVALID, dVlo = IRTemp_INVALID;
+ breakupV256toV128s( sV, &sVhi, &sVlo );
+ breakupV256toV128s( dV, &dVhi, &dVlo );
+ IRTemp rVhi = math_BLENDPD_128(sVhi, dVhi, (imm8 >> 2) & 3);
+ IRTemp rVlo = math_BLENDPD_128(sVlo, dVlo, imm8 & 3);
+ IRTemp rV = newTemp(Ity_V256);
+ assign(rV, binop(Iop_V128HLtoV256, mkexpr(rVhi), mkexpr(rVlo)));
+ return rV;
+}
+
+
+static IRTemp math_BLENDPS_128 ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ UShort imm8_perms[16] = { 0x0000, 0x000F, 0x00F0, 0x00FF, 0x0F00,
+ 0x0F0F, 0x0FF0, 0x0FFF, 0xF000, 0xF00F,
+ 0xF0F0, 0xF0FF, 0xFF00, 0xFF0F, 0xFFF0,
+ 0xFFFF };
+ IRTemp imm8_mask = newTemp(Ity_V128);
+ assign( imm8_mask, mkV128( imm8_perms[ (imm8 & 15) ] ) );
+
+ IRTemp res = newTemp(Ity_V128);
+ assign ( res, binop( Iop_OrV128,
+ binop( Iop_AndV128, mkexpr(sV),
+ mkexpr(imm8_mask) ),
+ binop( Iop_AndV128, mkexpr(dV),
+ unop( Iop_NotV128, mkexpr(imm8_mask) ) ) ) );
+ return res;
+}
+
+
+static IRTemp math_BLENDPS_256 ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ IRTemp sVhi = IRTemp_INVALID, sVlo = IRTemp_INVALID;
+ IRTemp dVhi = IRTemp_INVALID, dVlo = IRTemp_INVALID;
+ breakupV256toV128s( sV, &sVhi, &sVlo );
+ breakupV256toV128s( dV, &dVhi, &dVlo );
+ IRTemp rVhi = math_BLENDPS_128(sVhi, dVhi, (imm8 >> 4) & 15);
+ IRTemp rVlo = math_BLENDPS_128(sVlo, dVlo, imm8 & 15);
+ IRTemp rV = newTemp(Ity_V256);
+ assign(rV, binop(Iop_V128HLtoV256, mkexpr(rVhi), mkexpr(rVlo)));
+ return rV;
+}
+
+
+static IRTemp math_PBLENDW_128 ( IRTemp sV, IRTemp dV, UInt imm8 )
+{
+ /* Make w be a 16-bit version of imm8, formed by duplicating each
+ bit in imm8. */
+ Int i;
+ UShort imm16 = 0;
+ for (i = 0; i < 8; i++) {
+ if (imm8 & (1 << i))
+ imm16 |= (3 << (2*i));
}
+ IRTemp imm16_mask = newTemp(Ity_V128);
+ assign( imm16_mask, mkV128( imm16 ));
- /* 66 0F E5 = PMULHW -- 16x8 hi-half of signed widening multiply */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE5) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pmulhw", Iop_MulHi16Sx8, False );
- goto decode_success;
- }
+ IRTemp res = newTemp(Ity_V128);
+ assign ( res, binop( Iop_OrV128,
+ binop( Iop_AndV128, mkexpr(sV),
+ mkexpr(imm16_mask) ),
+ binop( Iop_AndV128, mkexpr(dV),
+ unop( Iop_NotV128, mkexpr(imm16_mask) ) ) ) );
+ return res;
+}
- /* 66 0F D5 = PMULHL -- 16x8 multiply */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD5) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "pmullw", Iop_Mul16x8, False );
- goto decode_success;
- }
- /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
- /* 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x
- 0 to form 64-bit result */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xF4) {
- IRTemp sV = newTemp(Ity_I64);
- IRTemp dV = newTemp(Ity_I64);
- t1 = newTemp(Ity_I32);
- t0 = newTemp(Ity_I32);
- modrm = insn[2];
-
- do_MMX_preamble();
- assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
- delta += 2+1;
- DIP("pmuludq %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 2+alen;
- DIP("pmuludq %s,%s\n", dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
-
- assign( t0, unop(Iop_64to32, mkexpr(dV)) );
- assign( t1, unop(Iop_64to32, mkexpr(sV)) );
- putMMXReg( gregLO3ofRM(modrm),
- binop( Iop_MullU32, mkexpr(t0), mkexpr(t1) ) );
- goto decode_success;
- }
-
- /* 66 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x
- 0 to form lower 64-bit half and lanes 2 x 2 to form upper 64-bit
- half */
+static IRTemp math_PMULUDQ_128 ( IRTemp sV, IRTemp dV )
+{
/* This is a really poor translation -- could be improved if
performance critical */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF4) {
- IRTemp sV, dV;
- IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
- sV = newTemp(Ity_V128);
- dV = newTemp(Ity_V128);
- s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
- t1 = newTemp(Ity_I64);
- t0 = newTemp(Ity_I64);
- modrm = insn[2];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+ IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
+ s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
+ breakupV128to32s( dV, &d3, &d2, &d1, &d0 );
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128,
+ binop( Iop_MullU32, mkexpr(d2), mkexpr(s2)),
+ binop( Iop_MullU32, mkexpr(d0), mkexpr(s0)) ));
+ return res;
+}
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("pmuludq %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 2+alen;
- DIP("pmuludq %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
+
+static IRTemp math_PMULDQ_128 ( IRTemp dV, IRTemp sV )
+{
+ /* This is a really poor translation -- could be improved if
+ performance critical */
+ IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
+ s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
+ breakupV128to32s( dV, &d3, &d2, &d1, &d0 );
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128,
+ binop( Iop_MullS32, mkexpr(d2), mkexpr(s2)),
+ binop( Iop_MullS32, mkexpr(d0), mkexpr(s0)) ));
+ return res;
+}
+
+
+static IRTemp math_PMADDWD_128 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp sVhi, sVlo, dVhi, dVlo;
+ IRTemp resHi = newTemp(Ity_I64);
+ IRTemp resLo = newTemp(Ity_I64);
+ sVhi = sVlo = dVhi = dVlo = IRTemp_INVALID;
+ breakupV128to64s( sV, &sVhi, &sVlo );
+ breakupV128to64s( dV, &dVhi, &dVlo );
+ assign( resHi, mkIRExprCCall(Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_mmx_pmaddwd",
+ &amd64g_calculate_mmx_pmaddwd,
+ mkIRExprVec_2( mkexpr(sVhi), mkexpr(dVhi))));
+ assign( resLo, mkIRExprCCall(Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_mmx_pmaddwd",
+ &amd64g_calculate_mmx_pmaddwd,
+ mkIRExprVec_2( mkexpr(sVlo), mkexpr(dVlo))));
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop(Iop_64HLtoV128, mkexpr(resHi), mkexpr(resLo))) ;
+ return res;
+}
+
+
+static IRTemp math_ADDSUBPD_128 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp addV = newTemp(Ity_V128);
+ IRTemp subV = newTemp(Ity_V128);
+ IRTemp a1 = newTemp(Ity_I64);
+ IRTemp s0 = newTemp(Ity_I64);
+
+ assign( addV, binop(Iop_Add64Fx2, mkexpr(dV), mkexpr(sV)) );
+ assign( subV, binop(Iop_Sub64Fx2, mkexpr(dV), mkexpr(sV)) );
+
+ assign( a1, unop(Iop_V128HIto64, mkexpr(addV) ));
+ assign( s0, unop(Iop_V128to64, mkexpr(subV) ));
+
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop(Iop_64HLtoV128, mkexpr(a1), mkexpr(s0)) );
+ return res;
+}
+
+
+static IRTemp math_ADDSUBPD_256 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp a3, a2, a1, a0, s3, s2, s1, s0;
+ IRTemp addV = newTemp(Ity_V256);
+ IRTemp subV = newTemp(Ity_V256);
+ a3 = a2 = a1 = a0 = s3 = s2 = s1 = s0 = IRTemp_INVALID;
+
+ assign( addV, binop(Iop_Add64Fx4, mkexpr(dV), mkexpr(sV)) );
+ assign( subV, binop(Iop_Sub64Fx4, mkexpr(dV), mkexpr(sV)) );
+
+ breakupV256to64s( addV, &a3, &a2, &a1, &a0 );
+ breakupV256to64s( subV, &s3, &s2, &s1, &s0 );
+
+ IRTemp res = newTemp(Ity_V256);
+ assign( res, mkV256from64s( a3, s2, a1, s0 ) );
+ return res;
+}
+
+
+static IRTemp math_ADDSUBPS_128 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp a3, a2, a1, a0, s3, s2, s1, s0;
+ IRTemp addV = newTemp(Ity_V128);
+ IRTemp subV = newTemp(Ity_V128);
+ a3 = a2 = a1 = a0 = s3 = s2 = s1 = s0 = IRTemp_INVALID;
+
+ assign( addV, binop(Iop_Add32Fx4, mkexpr(dV), mkexpr(sV)) );
+ assign( subV, binop(Iop_Sub32Fx4, mkexpr(dV), mkexpr(sV)) );
+
+ breakupV128to32s( addV, &a3, &a2, &a1, &a0 );
+ breakupV128to32s( subV, &s3, &s2, &s1, &s0 );
+
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, mkV128from32s( a3, s2, a1, s0 ) );
+ return res;
+}
+
+
+static IRTemp math_ADDSUBPS_256 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp a7, a6, a5, a4, a3, a2, a1, a0;
+ IRTemp s7, s6, s5, s4, s3, s2, s1, s0;
+ IRTemp addV = newTemp(Ity_V256);
+ IRTemp subV = newTemp(Ity_V256);
+ a7 = a6 = a5 = a4 = a3 = a2 = a1 = a0 = IRTemp_INVALID;
+ s7 = s6 = s5 = s4 = s3 = s2 = s1 = s0 = IRTemp_INVALID;
+
+ assign( addV, binop(Iop_Add32Fx8, mkexpr(dV), mkexpr(sV)) );
+ assign( subV, binop(Iop_Sub32Fx8, mkexpr(dV), mkexpr(sV)) );
+
+ breakupV256to32s( addV, &a7, &a6, &a5, &a4, &a3, &a2, &a1, &a0 );
+ breakupV256to32s( subV, &s7, &s6, &s5, &s4, &s3, &s2, &s1, &s0 );
+
+ IRTemp res = newTemp(Ity_V256);
+ assign( res, mkV256from32s( a7, s6, a5, s4, a3, s2, a1, s0 ) );
+ return res;
+}
+
+
+/* Handle 128 bit PSHUFLW and PSHUFHW. */
+static Long dis_PSHUFxW_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, Bool xIsH )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt imm8;
+ IRTemp sVmut, dVmut, sVcon, sV, dV, s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ sV = newTemp(Ity_V128);
+ dV = newTemp(Ity_V128);
+ sVmut = newTemp(Ity_I64);
+ dVmut = newTemp(Ity_I64);
+ sVcon = newTemp(Ity_I64);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ imm8 = (UInt)getUChar(delta+1);
+ delta += 1+1;
+ DIP("%spshuf%cw $%u,%s,%s\n",
+ isAvx ? "v" : "", xIsH ? 'h' : 'l',
+ imm8, nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ imm8 = (UInt)getUChar(delta+alen);
+ delta += alen+1;
+ DIP("%spshuf%cw $%u,%s,%s\n",
+ isAvx ? "v" : "", xIsH ? 'h' : 'l',
+ imm8, dis_buf, nameXMMReg(rG));
+ }
+
+ /* Get the to-be-changed (mut) and unchanging (con) bits of the
+ source. */
+ assign( sVmut, unop(xIsH ? Iop_V128HIto64 : Iop_V128to64, mkexpr(sV)) );
+ assign( sVcon, unop(xIsH ? Iop_V128to64 : Iop_V128HIto64, mkexpr(sV)) );
+
+ breakup64to16s( sVmut, &s3, &s2, &s1, &s0 );
+# define SEL(n) \
+ ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3)))
+ assign(dVmut, mk64from16s( SEL((imm8>>6)&3), SEL((imm8>>4)&3),
+ SEL((imm8>>2)&3), SEL((imm8>>0)&3) ));
+# undef SEL
+
+ assign(dV, xIsH ? binop(Iop_64HLtoV128, mkexpr(dVmut), mkexpr(sVcon))
+ : binop(Iop_64HLtoV128, mkexpr(sVcon), mkexpr(dVmut)) );
+
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)(rG, mkexpr(dV));
+ return delta;
+}
+
+
+static Long dis_PEXTRW_128_EregOnly_toG ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ Long deltaIN = delta;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp d16 = newTemp(Ity_I16);
+ UInt imm8;
+ IRTemp s0, s1, s2, s3;
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign(sV, getXMMReg(rE));
+ imm8 = getUChar(delta+1) & 7;
+ delta += 1+1;
+ DIP("%spextrw $%d,%s,%s\n", isAvx ? "v" : "",
+ (Int)imm8, nameXMMReg(rE), nameIReg32(rG));
+ } else {
+ /* The memory case is disallowed, apparently. */
+ return deltaIN; /* FAIL */
+ }
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+ switch (imm8) {
+ case 0: assign(d16, unop(Iop_32to16, mkexpr(s0))); break;
+ case 1: assign(d16, unop(Iop_32HIto16, mkexpr(s0))); break;
+ case 2: assign(d16, unop(Iop_32to16, mkexpr(s1))); break;
+ case 3: assign(d16, unop(Iop_32HIto16, mkexpr(s1))); break;
+ case 4: assign(d16, unop(Iop_32to16, mkexpr(s2))); break;
+ case 5: assign(d16, unop(Iop_32HIto16, mkexpr(s2))); break;
+ case 6: assign(d16, unop(Iop_32to16, mkexpr(s3))); break;
+ case 7: assign(d16, unop(Iop_32HIto16, mkexpr(s3))); break;
+ default: vassert(0);
+ }
+ putIReg32(rG, unop(Iop_16Uto32, mkexpr(d16)));
+ return delta;
+}
+
+
+static Long dis_CVTDQ2PD_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ IRTemp arg64 = newTemp(Ity_I64);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UChar* mbV = isAvx ? "v" : "";
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( arg64, getXMMRegLane64(rE, 0) );
+ delta += 1;
+ DIP("%scvtdq2pd %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("%scvtdq2pd %s,%s\n", mbV, dis_buf, nameXMMReg(rG) );
+ }
+ putXMMRegLane64F(
+ rG, 0,
+ unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)))
+ );
+ putXMMRegLane64F(
+ rG, 1,
+ unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)))
+ );
+ if (isAvx)
+ putYMMRegLane128(rG, 1, mkV128(0));
+ return delta;
+}
+
+
+static Long dis_STMXCSR ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ vassert(!epartIsReg(modrm)); /* ensured by caller */
+ vassert(gregOfRexRM(pfx,modrm) == 3); /* ditto */
+
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+
+ /* Fake up a native SSE mxcsr word. The only thing it depends on
+ is SSEROUND[1:0], so call a clean helper to cook it up.
+ */
+ /* ULong amd64h_create_mxcsr ( ULong sseround ) */
+ DIP("%sstmxcsr %s\n", isAvx ? "v" : "", dis_buf);
+ storeLE(
+ mkexpr(addr),
+ unop(Iop_64to32,
+ mkIRExprCCall(
+ Ity_I64, 0/*regp*/,
+ "amd64g_create_mxcsr", &amd64g_create_mxcsr,
+ mkIRExprVec_1( unop(Iop_32Uto64,get_sse_roundingmode()) )
+ )
+ )
+ );
+ return delta;
+}
+
+
+static Long dis_LDMXCSR ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ vassert(!epartIsReg(modrm)); /* ensured by caller */
+ vassert(gregOfRexRM(pfx,modrm) == 2); /* ditto */
+
+ IRTemp t64 = newTemp(Ity_I64);
+ IRTemp ew = newTemp(Ity_I32);
+
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("%sldmxcsr %s\n", isAvx ? "v" : "", dis_buf);
+
+ /* The only thing we observe in %mxcsr is the rounding mode.
+ Therefore, pass the 32-bit value (SSE native-format control
+ word) to a clean helper, getting back a 64-bit value, the
+ lower half of which is the SSEROUND value to store, and the
+ upper half of which is the emulation-warning token which may
+ be generated.
+ */
+ /* ULong amd64h_check_ldmxcsr ( ULong ); */
+ assign( t64, mkIRExprCCall(
+ Ity_I64, 0/*regparms*/,
+ "amd64g_check_ldmxcsr",
+ &amd64g_check_ldmxcsr,
+ mkIRExprVec_1(
+ unop(Iop_32Uto64,
+ loadLE(Ity_I32, mkexpr(addr))
+ )
+ )
+ )
+ );
+
+ put_sse_roundingmode( unop(Iop_64to32, mkexpr(t64)) );
+ assign( ew, unop(Iop_64HIto32, mkexpr(t64) ) );
+ put_emwarn( mkexpr(ew) );
+ /* Finally, if an emulation warning was reported, side-exit to
+ the next insn, reporting the warning, so that Valgrind's
+ dispatcher sees the warning. */
+ stmt(
+ IRStmt_Exit(
+ binop(Iop_CmpNE64, unop(Iop_32Uto64,mkexpr(ew)), mkU64(0)),
+ Ijk_EmWarn,
+ IRConst_U64(guest_RIP_bbstart+delta),
+ OFFB_RIP
+ )
+ );
+ return delta;
+}
+
+
+static IRTemp math_PINSRW_128 ( IRTemp v128, IRTemp u16, UInt imm8 )
+{
+ vassert(imm8 >= 0 && imm8 <= 7);
+
+ // Create a V128 value which has the selected word in the
+ // specified lane, and zeroes everywhere else.
+ IRTemp tmp128 = newTemp(Ity_V128);
+ IRTemp halfshift = newTemp(Ity_I64);
+ assign(halfshift, binop(Iop_Shl64,
+ unop(Iop_16Uto64, mkexpr(u16)),
+ mkU8(16 * (imm8 & 3))));
+ if (imm8 < 4) {
+ assign(tmp128, binop(Iop_64HLtoV128, mkU64(0), mkexpr(halfshift)));
+ } else {
+ assign(tmp128, binop(Iop_64HLtoV128, mkexpr(halfshift), mkU64(0)));
+ }
+
+ UShort mask = ~(3 << (imm8 * 2));
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop(Iop_OrV128,
+ mkexpr(tmp128),
+ binop(Iop_AndV128, mkexpr(v128), mkV128(mask))) );
+ return res;
+}
+
+
+static IRTemp math_PSADBW_128 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp s1, s0, d1, d0;
+ s1 = s0 = d1 = d0 = IRTemp_INVALID;
+
+ breakupV128to64s( sV, &s1, &s0 );
+ breakupV128to64s( dV, &d1, &d0 );
+
+ IRTemp res = newTemp(Ity_V128);
+ assign( res,
+ binop(Iop_64HLtoV128,
+ mkIRExprCCall(Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_mmx_psadbw",
+ &amd64g_calculate_mmx_psadbw,
+ mkIRExprVec_2( mkexpr(s1), mkexpr(d1))),
+ mkIRExprCCall(Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_mmx_psadbw",
+ &amd64g_calculate_mmx_psadbw,
+ mkIRExprVec_2( mkexpr(s0), mkexpr(d0)))) );
+ return res;
+}
+
+
+static Long dis_MASKMOVDQU ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp regD = newTemp(Ity_V128);
+ IRTemp mask = newTemp(Ity_V128);
+ IRTemp olddata = newTemp(Ity_V128);
+ IRTemp newdata = newTemp(Ity_V128);
+ IRTemp addr = newTemp(Ity_I64);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rE = eregOfRexRM(pfx,modrm);
+
+ assign( addr, handleAddrOverrides( vbi, pfx, getIReg64(R_RDI) ));
+ assign( regD, getXMMReg( rG ));
+
+ /* Unfortunately can't do the obvious thing with SarN8x16
+ here since that can't be re-emitted as SSE2 code - no such
+ insn. */
+ assign( mask,
+ binop(Iop_64HLtoV128,
+ binop(Iop_SarN8x8,
+ getXMMRegLane64( eregOfRexRM(pfx,modrm), 1 ),
+ mkU8(7) ),
+ binop(Iop_SarN8x8,
+ getXMMRegLane64( eregOfRexRM(pfx,modrm), 0 ),
+ mkU8(7) ) ));
+ assign( olddata, loadLE( Ity_V128, mkexpr(addr) ));
+ assign( newdata, binop(Iop_OrV128,
+ binop(Iop_AndV128,
+ mkexpr(regD),
+ mkexpr(mask) ),
+ binop(Iop_AndV128,
+ mkexpr(olddata),
+ unop(Iop_NotV128, mkexpr(mask)))) );
+ storeLE( mkexpr(addr), mkexpr(newdata) );
+
+ delta += 1;
+ DIP("%smaskmovdqu %s,%s\n", isAvx ? "v" : "",
+ nameXMMReg(rE), nameXMMReg(rG) );
+ return delta;
+}
+
+
+static Long dis_MOVMSKPS_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rE = eregOfRexRM(pfx,modrm);
+ IRTemp t0 = newTemp(Ity_I32);
+ IRTemp t1 = newTemp(Ity_I32);
+ IRTemp t2 = newTemp(Ity_I32);
+ IRTemp t3 = newTemp(Ity_I32);
+ delta += 1;
+ assign( t0, binop( Iop_And32,
+ binop(Iop_Shr32, getXMMRegLane32(rE,0), mkU8(31)),
+ mkU32(1) ));
+ assign( t1, binop( Iop_And32,
+ binop(Iop_Shr32, getXMMRegLane32(rE,1), mkU8(30)),
+ mkU32(2) ));
+ assign( t2, binop( Iop_And32,
+ binop(Iop_Shr32, getXMMRegLane32(rE,2), mkU8(29)),
+ mkU32(4) ));
+ assign( t3, binop( Iop_And32,
+ binop(Iop_Shr32, getXMMRegLane32(rE,3), mkU8(28)),
+ mkU32(8) ));
+ putIReg32( rG, binop(Iop_Or32,
+ binop(Iop_Or32, mkexpr(t0), mkexpr(t1)),
+ binop(Iop_Or32, mkexpr(t2), mkexpr(t3)) ) );
+ DIP("%smovmskps %s,%s\n", isAvx ? "v" : "",
+ nameXMMReg(rE), nameIReg32(rG));
+ return delta;
+}
+
+
+static Long dis_MOVMSKPS_256 ( VexAbiInfo* vbi, Prefix pfx, Long delta )
+{
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rE = eregOfRexRM(pfx,modrm);
+ IRTemp t0 = newTemp(Ity_I32);
+ IRTemp t1 = newTemp(Ity_I32);
+ IRTemp t2 = newTemp(Ity_I32);
+ IRTemp t3 = newTemp(Ity_I32);
+ IRTemp t4 = newTemp(Ity_I32);
+ IRTemp t5 = newTemp(Ity_I32);
+ IRTemp t6 = newTemp(Ity_I32);
+ IRTemp t7 = newTemp(Ity_I32);
+ delta += 1;
+ assign( t0, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,0), mkU8(31)),
+ mkU32(1) ));
+ assign( t1, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,1), mkU8(30)),
+ mkU32(2) ));
+ assign( t2, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,2), mkU8(29)),
+ mkU32(4) ));
+ assign( t3, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,3), mkU8(28)),
+ mkU32(8) ));
+ assign( t4, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,4), mkU8(27)),
+ mkU32(16) ));
+ assign( t5, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,5), mkU8(26)),
+ mkU32(32) ));
+ assign( t6, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,6), mkU8(25)),
+ mkU32(64) ));
+ assign( t7, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,7), mkU8(24)),
+ mkU32(128) ));
+ putIReg32( rG, binop(Iop_Or32,
+ binop(Iop_Or32,
+ binop(Iop_Or32, mkexpr(t0), mkexpr(t1)),
+ binop(Iop_Or32, mkexpr(t2), mkexpr(t3)) ),
+ binop(Iop_Or32,
+ binop(Iop_Or32, mkexpr(t4), mkexpr(t5)),
+ binop(Iop_Or32, mkexpr(t6), mkexpr(t7)) ) ) );
+ DIP("vmovmskps %s,%s\n", nameYMMReg(rE), nameIReg32(rG));
+ return delta;
+}
+
+
+static Long dis_MOVMSKPD_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rE = eregOfRexRM(pfx,modrm);
+ IRTemp t0 = newTemp(Ity_I32);
+ IRTemp t1 = newTemp(Ity_I32);
+ delta += 1;
+ assign( t0, binop( Iop_And32,
+ binop(Iop_Shr32, getXMMRegLane32(rE,1), mkU8(31)),
+ mkU32(1) ));
+ assign( t1, binop( Iop_And32,
+ binop(Iop_Shr32, getXMMRegLane32(rE,3), mkU8(30)),
+ mkU32(2) ));
+ putIReg32( rG, binop(Iop_Or32, mkexpr(t0), mkexpr(t1) ) );
+ DIP("%smovmskpd %s,%s\n", isAvx ? "v" : "",
+ nameXMMReg(rE), nameIReg32(rG));
+ return delta;
+}
+
+
+static Long dis_MOVMSKPD_256 ( VexAbiInfo* vbi, Prefix pfx, Long delta )
+{
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rE = eregOfRexRM(pfx,modrm);
+ IRTemp t0 = newTemp(Ity_I32);
+ IRTemp t1 = newTemp(Ity_I32);
+ IRTemp t2 = newTemp(Ity_I32);
+ IRTemp t3 = newTemp(Ity_I32);
+ delta += 1;
+ assign( t0, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,1), mkU8(31)),
+ mkU32(1) ));
+ assign( t1, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,3), mkU8(30)),
+ mkU32(2) ));
+ assign( t2, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,5), mkU8(29)),
+ mkU32(4) ));
+ assign( t3, binop( Iop_And32,
+ binop(Iop_Shr32, getYMMRegLane32(rE,7), mkU8(28)),
+ mkU32(8) ));
+ putIReg32( rG, binop(Iop_Or32,
+ binop(Iop_Or32, mkexpr(t0), mkexpr(t1)),
+ binop(Iop_Or32, mkexpr(t2), mkexpr(t3)) ) );
+ DIP("vmovmskps %s,%s\n", nameYMMReg(rE), nameIReg32(rG));
+ return delta;
+}
+
+
+/* Note, this also handles SSE(1) insns. */
+__attribute__((noinline))
+static
+Long dis_ESC_0F__SSE2 ( Bool* decode_OK,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN,
+ DisResult* dres )
+{
+ IRTemp addr = IRTemp_INVALID;
+ IRTemp t0 = IRTemp_INVALID;
+ IRTemp t1 = IRTemp_INVALID;
+ IRTemp t2 = IRTemp_INVALID;
+ IRTemp t3 = IRTemp_INVALID;
+ IRTemp t4 = IRTemp_INVALID;
+ IRTemp t5 = IRTemp_INVALID;
+ IRTemp t6 = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
+
+ *decode_OK = False;
+
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) {
+
+ case 0x10:
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ /* 66 0F 10 = MOVUPD -- move from E (mem or xmm) to G (xmm). */
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ getXMMReg( eregOfRexRM(pfx,modrm) ));
+ DIP("movupd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("movupd %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
}
-
- breakup128to32s( dV, &d3, &d2, &d1, &d0 );
- breakup128to32s( sV, &s3, &s2, &s1, &s0 );
-
- assign( t0, binop( Iop_MullU32, mkexpr(d0), mkexpr(s0)) );
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 0, mkexpr(t0) );
- assign( t1, binop( Iop_MullU32, mkexpr(d2), mkexpr(s2)) );
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 1, mkexpr(t1) );
- goto decode_success;
- }
-
- /* 66 0F EB = POR */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEB) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "por", Iop_OrV128 );
- goto decode_success;
- }
-
- /* 66 0F F6 = PSADBW -- 2 x (8x8 -> 48 zeroes ++ u16) Sum Abs Diffs
- from E(xmm or mem) to G(xmm) */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF6) {
- IRTemp s1V = newTemp(Ity_V128);
- IRTemp s2V = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp s1Hi = newTemp(Ity_I64);
- IRTemp s1Lo = newTemp(Ity_I64);
- IRTemp s2Hi = newTemp(Ity_I64);
- IRTemp s2Lo = newTemp(Ity_I64);
- IRTemp dHi = newTemp(Ity_I64);
- IRTemp dLo = newTemp(Ity_I64);
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( s1V, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 2+1;
- DIP("psadbw %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( s1V, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 2+alen;
- DIP("psadbw %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
+ /* F2 0F 10 = MOVSD -- move 64 bits from E (mem or lo half xmm) to
+ G (lo half xmm). If E is mem, upper half of G is zeroed out.
+ If E is reg, upper half of G is unchanged. */
+ if (haveF2no66noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8) ) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 0,
+ getXMMRegLane64( eregOfRexRM(pfx,modrm), 0 ));
+ DIP("movsd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putXMMReg( gregOfRexRM(pfx,modrm), mkV128(0) );
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 0,
+ loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movsd %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
}
- assign( s2V, getXMMReg(gregOfRexRM(pfx,modrm)) );
- assign( s1Hi, unop(Iop_V128HIto64, mkexpr(s1V)) );
- assign( s1Lo, unop(Iop_V128to64, mkexpr(s1V)) );
- assign( s2Hi, unop(Iop_V128HIto64, mkexpr(s2V)) );
- assign( s2Lo, unop(Iop_V128to64, mkexpr(s2V)) );
- assign( dHi, mkIRExprCCall(
- Ity_I64, 0/*regparms*/,
- "amd64g_calculate_mmx_psadbw",
- &amd64g_calculate_mmx_psadbw,
- mkIRExprVec_2( mkexpr(s1Hi), mkexpr(s2Hi))
- ));
- assign( dLo, mkIRExprCCall(
- Ity_I64, 0/*regparms*/,
- "amd64g_calculate_mmx_psadbw",
- &amd64g_calculate_mmx_psadbw,
- mkIRExprVec_2( mkexpr(s1Lo), mkexpr(s2Lo))
- ));
- assign( dV, binop(Iop_64HLtoV128, mkexpr(dHi), mkexpr(dLo))) ;
- putXMMReg(gregOfRexRM(pfx,modrm), mkexpr(dV));
- goto decode_success;
- }
-
- /* 66 0F 70 = PSHUFD -- rearrange 4x32 from E(xmm or mem) to G(xmm) */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x70) {
- Int order;
- IRTemp sV, dV, s3, s2, s1, s0;
- s3 = s2 = s1 = s0 = IRTemp_INVALID;
- sV = newTemp(Ity_V128);
- dV = newTemp(Ity_V128);
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- order = (Int)insn[3];
- delta += 3+1;
- DIP("pshufd $%d,%s,%s\n", order,
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf,
- 1/*byte after the amode*/ );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- order = (Int)insn[2+alen];
- delta += 2+alen+1;
- DIP("pshufd $%d,%s,%s\n", order,
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
+ /* F3 0F 10 = MOVSS -- move 32 bits from E (mem or lo 1/4 xmm) to G
+ (lo 1/4 xmm). If E is mem, upper 3/4 of G is zeroed out. */
+ if (haveF3no66noF2(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMRegLane32( gregOfRexRM(pfx,modrm), 0,
+ getXMMRegLane32( eregOfRexRM(pfx,modrm), 0 ));
+ DIP("movss %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putXMMReg( gregOfRexRM(pfx,modrm), mkV128(0) );
+ putXMMRegLane32( gregOfRexRM(pfx,modrm), 0,
+ loadLE(Ity_I32, mkexpr(addr)) );
+ DIP("movss %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
}
- breakup128to32s( sV, &s3, &s2, &s1, &s0 );
+ /* 0F 10 = MOVUPS -- move from E (mem or xmm) to G (xmm). */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ getXMMReg( eregOfRexRM(pfx,modrm) ));
+ DIP("movups %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("movups %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ break;
-# define SEL(n) \
- ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3)))
- assign(dV,
- mk128from32s( SEL((order>>6)&3), SEL((order>>4)&3),
- SEL((order>>2)&3), SEL((order>>0)&3) )
- );
- putXMMReg(gregOfRexRM(pfx,modrm), mkexpr(dV));
-# undef SEL
- goto decode_success;
- }
+ case 0x11:
+ /* F2 0F 11 = MOVSD -- move 64 bits from G (lo half xmm) to E (mem
+ or lo half xmm). */
+ if (haveF2no66noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMRegLane64( eregOfRexRM(pfx,modrm), 0,
+ getXMMRegLane64( gregOfRexRM(pfx,modrm), 0 ));
+ DIP("movsd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ nameXMMReg(eregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr),
+ getXMMRegLane64(gregOfRexRM(pfx,modrm), 0) );
+ DIP("movsd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ dis_buf);
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* F3 0F 11 = MOVSS -- move 32 bits from G (lo 1/4 xmm) to E (mem
+ or lo 1/4 xmm). */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ /* fall through, we don't yet have a test case */
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr),
+ getXMMRegLane32(gregOfRexRM(pfx,modrm), 0) );
+ DIP("movss %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ dis_buf);
+ delta += alen;
+ goto decode_success;
+ }
+ }
+ /* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMReg( eregOfRexRM(pfx,modrm),
+ getXMMReg( gregOfRexRM(pfx,modrm) ) );
+ DIP("movupd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ nameXMMReg(eregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movupd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ dis_buf );
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* 0F 11 = MOVUPS -- move from G (xmm) to E (mem or xmm). */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ /* fall through; awaiting test case */
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movups %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ dis_buf );
+ delta += alen;
+ goto decode_success;
+ }
+ }
+ break;
- /* F3 0F 70 = PSHUFHW -- rearrange upper half 4x16 from E(xmm or
- mem) to G(xmm), and copy lower half */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x70) {
- Int order;
- IRTemp sVhi, dVhi, sV, dV, s3, s2, s1, s0;
- s3 = s2 = s1 = s0 = IRTemp_INVALID;
- sV = newTemp(Ity_V128);
- dV = newTemp(Ity_V128);
- sVhi = newTemp(Ity_I64);
- dVhi = newTemp(Ity_I64);
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- order = (Int)insn[3];
- delta += 3+1;
- DIP("pshufhw $%d,%s,%s\n", order,
- nameXMMReg(eregOfRexRM(pfx,modrm)),
+ case 0x12:
+ /* 66 0F 12 = MOVLPD -- move from mem to low half of XMM. */
+ /* Identical to MOVLPS ? */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ /* fall through; apparently reg-reg is not possible */
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ putXMMRegLane64( gregOfRexRM(pfx,modrm),
+ 0/*lower lane*/,
+ loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movlpd %s, %s\n",
+ dis_buf, nameXMMReg( gregOfRexRM(pfx,modrm) ));
+ goto decode_success;
+ }
+ }
+ /* 0F 12 = MOVLPS -- move from mem to low half of XMM. */
+ /* OF 12 = MOVHLPS -- from from hi half to lo half of XMM. */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ putXMMRegLane64( gregOfRexRM(pfx,modrm),
+ 0/*lower lane*/,
+ getXMMRegLane64( eregOfRexRM(pfx,modrm), 1 ));
+ DIP("movhlps %s, %s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf,
- 1/*byte after the amode*/ );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- order = (Int)insn[2+alen];
- delta += 2+alen+1;
- DIP("pshufhw $%d,%s,%s\n", order,
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 0/*lower lane*/,
+ loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movlps %s, %s\n",
+ dis_buf, nameXMMReg( gregOfRexRM(pfx,modrm) ));
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x13:
+ /* 0F 13 = MOVLPS -- move from low half of XMM to mem. */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (!epartIsReg(modrm)) {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ storeLE( mkexpr(addr),
+ getXMMRegLane64( gregOfRexRM(pfx,modrm),
+ 0/*lower lane*/ ) );
+ DIP("movlps %s, %s\n", nameXMMReg( gregOfRexRM(pfx,modrm) ),
+ dis_buf);
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ /* 66 0F 13 = MOVLPD -- move from low half of XMM to mem. */
+ /* Identical to MOVLPS ? */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (!epartIsReg(modrm)) {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ storeLE( mkexpr(addr),
+ getXMMRegLane64( gregOfRexRM(pfx,modrm),
+ 0/*lower lane*/ ) );
+ DIP("movlpd %s, %s\n", nameXMMReg( gregOfRexRM(pfx,modrm) ),
+ dis_buf);
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ break;
+
+ case 0x14:
+ case 0x15:
+ /* 0F 14 = UNPCKLPS -- unpack and interleave low part F32s */
+ /* 0F 15 = UNPCKHPS -- unpack and interleave high part F32s */
+ /* These just appear to be special cases of SHUFPS */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ Bool hi = toBool(opc == 0x15);
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ assign( dV, getXMMReg(rG) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("unpck%sps %s,%s\n", hi ? "h" : "l",
+ nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("unpck%sps %s,%s\n", hi ? "h" : "l",
+ dis_buf, nameXMMReg(rG));
+ }
+ IRTemp res = math_UNPCKxPS_128( sV, dV, hi );
+ putXMMReg( rG, mkexpr(res) );
+ goto decode_success;
+ }
+ /* 66 0F 15 = UNPCKHPD -- unpack and interleave high part F64s */
+ /* 66 0F 14 = UNPCKLPD -- unpack and interleave low part F64s */
+ /* These just appear to be special cases of SHUFPS */
+ if (have66noF2noF3(pfx)
+ && sz == 2 /* could be 8 if rex also present */) {
+ Bool hi = toBool(opc == 0x15);
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ assign( dV, getXMMReg(rG) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("unpck%sps %s,%s\n", hi ? "h" : "l",
+ nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("unpck%sps %s,%s\n", hi ? "h" : "l",
+ dis_buf, nameXMMReg(rG));
+ }
+ IRTemp res = math_UNPCKxPD_128( sV, dV, hi );
+ putXMMReg( rG, mkexpr(res) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x16:
+ /* 66 0F 16 = MOVHPD -- move from mem to high half of XMM. */
+ /* These seems identical to MOVHPS. This instruction encoding is
+ completely crazy. */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ /* fall through; apparently reg-reg is not possible */
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 1/*upper lane*/,
+ loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movhpd %s,%s\n", dis_buf,
+ nameXMMReg( gregOfRexRM(pfx,modrm) ));
+ goto decode_success;
+ }
+ }
+ /* 0F 16 = MOVHPS -- move from mem to high half of XMM. */
+ /* 0F 16 = MOVLHPS -- move from lo half to hi half of XMM. */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 1/*upper lane*/,
+ getXMMRegLane64( eregOfRexRM(pfx,modrm), 0 ) );
+ DIP("movhps %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 1/*upper lane*/,
+ loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movhps %s,%s\n", dis_buf,
+ nameXMMReg( gregOfRexRM(pfx,modrm) ));
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x17:
+ /* 0F 17 = MOVHPS -- move from high half of XMM to mem. */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (!epartIsReg(modrm)) {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ storeLE( mkexpr(addr),
+ getXMMRegLane64( gregOfRexRM(pfx,modrm),
+ 1/*upper lane*/ ) );
+ DIP("movhps %s,%s\n", nameXMMReg( gregOfRexRM(pfx,modrm) ),
+ dis_buf);
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ /* 66 0F 17 = MOVHPD -- move from high half of XMM to mem. */
+ /* Again, this seems identical to MOVHPS. */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (!epartIsReg(modrm)) {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ storeLE( mkexpr(addr),
+ getXMMRegLane64( gregOfRexRM(pfx,modrm),
+ 1/*upper lane*/ ) );
+ DIP("movhpd %s,%s\n", nameXMMReg( gregOfRexRM(pfx,modrm) ),
+ dis_buf);
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ break;
+
+ case 0x18:
+ /* 0F 18 /0 = PREFETCHNTA -- prefetch into caches, */
+ /* 0F 18 /1 = PREFETCH0 -- with various different hints */
+ /* 0F 18 /2 = PREFETCH1 */
+ /* 0F 18 /3 = PREFETCH2 */
+ if (haveNo66noF2noF3(pfx)
+ && !epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) >= 0
+ && gregLO3ofRM(getUChar(delta)) <= 3) {
+ HChar* hintstr = "??";
+
+ modrm = getUChar(delta);
+ vassert(!epartIsReg(modrm));
+
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+
+ switch (gregLO3ofRM(modrm)) {
+ case 0: hintstr = "nta"; break;
+ case 1: hintstr = "t0"; break;
+ case 2: hintstr = "t1"; break;
+ case 3: hintstr = "t2"; break;
+ default: vassert(0);
+ }
+
+ DIP("prefetch%s %s\n", hintstr, dis_buf);
+ goto decode_success;
+ }
+ break;
+
+ case 0x28:
+ /* 66 0F 28 = MOVAPD -- move from E (mem or xmm) to G (xmm). */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ getXMMReg( eregOfRexRM(pfx,modrm) ));
+ DIP("movapd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("movapd %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* 0F 28 = MOVAPS -- move from E (mem or xmm) to G (xmm). */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ getXMMReg( eregOfRexRM(pfx,modrm) ));
+ DIP("movaps %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("movaps %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x29:
+ /* 0F 29 = MOVAPS -- move from G (xmm) to E (mem or xmm). */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ /* fall through; awaiting test case */
+ putXMMReg( eregOfRexRM(pfx,modrm),
+ getXMMReg( gregOfRexRM(pfx,modrm) ));
+ DIP("movaps %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ nameXMMReg(eregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movaps %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ dis_buf );
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMReg( eregOfRexRM(pfx,modrm),
+ getXMMReg( gregOfRexRM(pfx,modrm) ) );
+ DIP("movapd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ nameXMMReg(eregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movapd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ dis_buf );
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x2A:
+ /* 0F 2A = CVTPI2PS -- convert 2 x I32 in mem/mmx to 2 x F32 in low
+ half xmm */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ IRTemp arg64 = newTemp(Ity_I64);
+ IRTemp rmode = newTemp(Ity_I32);
+
+ modrm = getUChar(delta);
+ do_MMX_preamble();
+ if (epartIsReg(modrm)) {
+ assign( arg64, getMMXReg(eregLO3ofRM(modrm)) );
+ delta += 1;
+ DIP("cvtpi2ps %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("cvtpi2ps %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ }
+
+ assign( rmode, get_sse_roundingmode() );
+
+ putXMMRegLane32F(
+ gregOfRexRM(pfx,modrm), 0,
+ binop(Iop_F64toF32,
+ mkexpr(rmode),
+ unop(Iop_I32StoF64,
+ unop(Iop_64to32, mkexpr(arg64)) )) );
+
+ putXMMRegLane32F(
+ gregOfRexRM(pfx,modrm), 1,
+ binop(Iop_F64toF32,
+ mkexpr(rmode),
+ unop(Iop_I32StoF64,
+ unop(Iop_64HIto32, mkexpr(arg64)) )) );
+
+ goto decode_success;
+ }
+ /* F3 0F 2A = CVTSI2SS
+ -- sz==4: convert I32 in mem/ireg to F32 in low quarter xmm
+ -- sz==8: convert I64 in mem/ireg to F32 in low quarter xmm */
+ if (haveF3no66noF2(pfx) && (sz == 4 || sz == 8)) {
+ IRTemp rmode = newTemp(Ity_I32);
+ assign( rmode, get_sse_roundingmode() );
+ modrm = getUChar(delta);
+ if (sz == 4) {
+ IRTemp arg32 = newTemp(Ity_I32);
+ if (epartIsReg(modrm)) {
+ assign( arg32, getIReg32(eregOfRexRM(pfx,modrm)) );
+ delta += 1;
+ DIP("cvtsi2ss %s,%s\n", nameIReg32(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg32, loadLE(Ity_I32, mkexpr(addr)) );
+ delta += alen;
+ DIP("cvtsi2ss %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ }
+ putXMMRegLane32F(
+ gregOfRexRM(pfx,modrm), 0,
+ binop(Iop_F64toF32,
+ mkexpr(rmode),
+ unop(Iop_I32StoF64, mkexpr(arg32)) ) );
+ } else {
+ /* sz == 8 */
+ IRTemp arg64 = newTemp(Ity_I64);
+ if (epartIsReg(modrm)) {
+ assign( arg64, getIReg64(eregOfRexRM(pfx,modrm)) );
+ delta += 1;
+ DIP("cvtsi2ssq %s,%s\n", nameIReg64(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("cvtsi2ssq %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ }
+ putXMMRegLane32F(
+ gregOfRexRM(pfx,modrm), 0,
+ binop(Iop_F64toF32,
+ mkexpr(rmode),
+ binop(Iop_I64StoF64, mkexpr(rmode), mkexpr(arg64)) ) );
+ }
+ goto decode_success;
+ }
+ /* F2 0F 2A = CVTSI2SD
+ when sz==4 -- convert I32 in mem/ireg to F64 in low half xmm
+ when sz==8 -- convert I64 in mem/ireg to F64 in low half xmm
+ */
+ if (haveF2no66noF3(pfx) && (sz == 4 || sz == 8)) {
+ modrm = getUChar(delta);
+ if (sz == 4) {
+ IRTemp arg32 = newTemp(Ity_I32);
+ if (epartIsReg(modrm)) {
+ assign( arg32, getIReg32(eregOfRexRM(pfx,modrm)) );
+ delta += 1;
+ DIP("cvtsi2sdl %s,%s\n", nameIReg32(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg32, loadLE(Ity_I32, mkexpr(addr)) );
+ delta += alen;
+ DIP("cvtsi2sdl %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ }
+ putXMMRegLane64F( gregOfRexRM(pfx,modrm), 0,
+ unop(Iop_I32StoF64, mkexpr(arg32))
+ );
+ } else {
+ /* sz == 8 */
+ IRTemp arg64 = newTemp(Ity_I64);
+ if (epartIsReg(modrm)) {
+ assign( arg64, getIReg64(eregOfRexRM(pfx,modrm)) );
+ delta += 1;
+ DIP("cvtsi2sdq %s,%s\n", nameIReg64(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("cvtsi2sdq %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ }
+ putXMMRegLane64F(
+ gregOfRexRM(pfx,modrm),
+ 0,
+ binop( Iop_I64StoF64,
+ get_sse_roundingmode(),
+ mkexpr(arg64)
+ )
+ );
+ }
+ goto decode_success;
+ }
+ /* 66 0F 2A = CVTPI2PD -- convert 2 x I32 in mem/mmx to 2 x F64 in
+ xmm(G) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ IRTemp arg64 = newTemp(Ity_I64);
+
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ /* Only switch to MMX mode if the source is a MMX register.
+ This is inconsistent with all other instructions which
+ convert between XMM and (M64 or MMX), which always switch
+ to MMX mode even if 64-bit operand is M64 and not MMX. At
+ least, that's what the Intel docs seem to me to say.
+ Fixes #210264. */
+ do_MMX_preamble();
+ assign( arg64, getMMXReg(eregLO3ofRM(modrm)) );
+ delta += 1;
+ DIP("cvtpi2pd %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("cvtpi2pd %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)) );
+ }
+
+ putXMMRegLane64F(
+ gregOfRexRM(pfx,modrm), 0,
+ unop(Iop_I32StoF64, unop(Iop_64to32, mkexpr(arg64)) )
+ );
+
+ putXMMRegLane64F(
+ gregOfRexRM(pfx,modrm), 1,
+ unop(Iop_I32StoF64, unop(Iop_64HIto32, mkexpr(arg64)) )
+ );
+
+ goto decode_success;
+ }
+ break;
+
+ case 0x2B:
+ /* 66 0F 2B = MOVNTPD -- for us, just a plain SSE store. */
+ /* 0F 2B = MOVNTPS -- for us, just a plain SSE store. */
+ if ( (haveNo66noF2noF3(pfx) && sz == 4)
+ || (have66noF2noF3(pfx) && sz == 2) ) {
+ modrm = getUChar(delta);
+ if (!epartIsReg(modrm)) {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movntp%s %s,%s\n", sz==2 ? "d" : "s",
dis_buf,
nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ goto decode_success;
+ }
+ /* else fall through */
}
- assign( sVhi, unop(Iop_V128HIto64, mkexpr(sV)) );
- breakup64to16s( sVhi, &s3, &s2, &s1, &s0 );
+ break;
-# define SEL(n) \
- ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3)))
- assign(dVhi,
- mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3),
- SEL((order>>2)&3), SEL((order>>0)&3) )
- );
- assign(dV, binop( Iop_64HLtoV128,
- mkexpr(dVhi),
- unop(Iop_V128to64, mkexpr(sV))) );
- putXMMReg(gregOfRexRM(pfx,modrm), mkexpr(dV));
-# undef SEL
- goto decode_success;
- }
+ case 0x2C:
+ case 0x2D:
+ /* 0F 2D = CVTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x
+ I32 in mmx, according to prevailing SSE rounding mode */
+ /* 0F 2C = CVTTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x
+ I32 in mmx, rounding towards zero */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ IRTemp dst64 = newTemp(Ity_I64);
+ IRTemp rmode = newTemp(Ity_I32);
+ IRTemp f32lo = newTemp(Ity_F32);
+ IRTemp f32hi = newTemp(Ity_F32);
+ Bool r2zero = toBool(opc == 0x2C);
- /* F2 0F 70 = PSHUFLW -- rearrange lower half 4x16 from E(xmm or
- mem) to G(xmm), and copy upper half */
- if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x70) {
- Int order;
- IRTemp sVlo, dVlo, sV, dV, s3, s2, s1, s0;
- s3 = s2 = s1 = s0 = IRTemp_INVALID;
- sV = newTemp(Ity_V128);
- dV = newTemp(Ity_V128);
- sVlo = newTemp(Ity_I64);
- dVlo = newTemp(Ity_I64);
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- order = (Int)insn[3];
- delta += 3+1;
- DIP("pshuflw $%d,%s,%s\n", order,
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf,
- 1/*byte after the amode*/ );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- order = (Int)insn[2+alen];
- delta += 2+alen+1;
- DIP("pshuflw $%d,%s,%s\n", order,
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
+ do_MMX_preamble();
+ modrm = getUChar(delta);
+
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ assign(f32lo, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 0));
+ assign(f32hi, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 1));
+ DIP("cvt%sps2pi %s,%s\n", r2zero ? "t" : "",
+ nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(f32lo, loadLE(Ity_F32, mkexpr(addr)));
+ assign(f32hi, loadLE(Ity_F32, binop( Iop_Add64,
+ mkexpr(addr),
+ mkU64(4) )));
+ delta += alen;
+ DIP("cvt%sps2pi %s,%s\n", r2zero ? "t" : "",
+ dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+
+ if (r2zero) {
+ assign(rmode, mkU32((UInt)Irrm_ZERO) );
+ } else {
+ assign( rmode, get_sse_roundingmode() );
+ }
+
+ assign(
+ dst64,
+ binop( Iop_32HLto64,
+ binop( Iop_F64toI32S,
+ mkexpr(rmode),
+ unop( Iop_F32toF64, mkexpr(f32hi) ) ),
+ binop( Iop_F64toI32S,
+ mkexpr(rmode),
+ unop( Iop_F32toF64, mkexpr(f32lo) ) )
+ )
+ );
+
+ putMMXReg(gregLO3ofRM(modrm), mkexpr(dst64));
+ goto decode_success;
}
- assign( sVlo, unop(Iop_V128to64, mkexpr(sV)) );
- breakup64to16s( sVlo, &s3, &s2, &s1, &s0 );
+ /* F3 0F 2D = CVTSS2SI
+ when sz==4 -- convert F32 in mem/low quarter xmm to I32 in ireg,
+ according to prevailing SSE rounding mode
+ when sz==8 -- convert F32 in mem/low quarter xmm to I64 in ireg,
+ according to prevailing SSE rounding mode
+ */
+ /* F3 0F 2C = CVTTSS2SI
+ when sz==4 -- convert F32 in mem/low quarter xmm to I32 in ireg,
+ truncating towards zero
+ when sz==8 -- convert F32 in mem/low quarter xmm to I64 in ireg,
+ truncating towards zero
+ */
+ if (haveF3no66noF2(pfx) && (sz == 4 || sz == 8)) {
+ delta = dis_CVTxSS2SI( vbi, pfx, delta, False/*!isAvx*/, opc, sz);
+ goto decode_success;
+ }
+ /* F2 0F 2D = CVTSD2SI
+ when sz==4 -- convert F64 in mem/low half xmm to I32 in ireg,
+ according to prevailing SSE rounding mode
+ when sz==8 -- convert F64 in mem/low half xmm to I64 in ireg,
+ according to prevailing SSE rounding mode
+ */
+ /* F2 0F 2C = CVTTSD2SI
+ when sz==4 -- convert F64 in mem/low half xmm to I32 in ireg,
+ truncating towards zero
+ when sz==8 -- convert F64 in mem/low half xmm to I64 in ireg,
+ truncating towards zero
+ */
+ if (haveF2no66noF3(pfx) && (sz == 4 || sz == 8)) {
+ delta = dis_CVTxSD2SI( vbi, pfx, delta, False/*!isAvx*/, opc, sz);
+ goto decode_success;
+ }
+ /* 66 0F 2D = CVTPD2PI -- convert 2 x F64 in mem/xmm to 2 x
+ I32 in mmx, according to prevailing SSE rounding mode */
+ /* 66 0F 2C = CVTTPD2PI -- convert 2 x F64 in mem/xmm to 2 x
+ I32 in mmx, rounding towards zero */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ IRTemp dst64 = newTemp(Ity_I64);
+ IRTemp rmode = newTemp(Ity_I32);
+ IRTemp f64lo = newTemp(Ity_F64);
+ IRTemp f64hi = newTemp(Ity_F64);
+ Bool r2zero = toBool(opc == 0x2C);
-# define SEL(n) \
- ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3)))
- assign(dVlo,
- mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3),
- SEL((order>>2)&3), SEL((order>>0)&3) )
- );
- assign(dV, binop( Iop_64HLtoV128,
- unop(Iop_V128HIto64, mkexpr(sV)),
- mkexpr(dVlo) ) );
- putXMMReg(gregOfRexRM(pfx,modrm), mkexpr(dV));
-# undef SEL
- goto decode_success;
- }
+ do_MMX_preamble();
+ modrm = getUChar(delta);
- /* 66 0F 72 /6 ib = PSLLD by immediate */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x72
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 6) {
- delta = dis_SSE_shiftE_imm( pfx, delta+2, "pslld", Iop_ShlN32x4 );
- goto decode_success;
- }
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ assign(f64lo, getXMMRegLane64F(eregOfRexRM(pfx,modrm), 0));
+ assign(f64hi, getXMMRegLane64F(eregOfRexRM(pfx,modrm), 1));
+ DIP("cvt%spd2pi %s,%s\n", r2zero ? "t" : "",
+ nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(f64lo, loadLE(Ity_F64, mkexpr(addr)));
+ assign(f64hi, loadLE(Ity_F64, binop( Iop_Add64,
+ mkexpr(addr),
+ mkU64(8) )));
+ delta += alen;
+ DIP("cvt%spf2pi %s,%s\n", r2zero ? "t" : "",
+ dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
- /* 66 0F F2 = PSLLD by E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF2) {
- delta = dis_SSE_shiftG_byE( vbi, pfx, delta+2, "pslld", Iop_ShlN32x4 );
- goto decode_success;
- }
+ if (r2zero) {
+ assign(rmode, mkU32((UInt)Irrm_ZERO) );
+ } else {
+ assign( rmode, get_sse_roundingmode() );
+ }
- /* 66 0F 73 /7 ib = PSLLDQ by immediate */
- /* note, if mem case ever filled in, 1 byte after amode */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x73
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 7) {
- IRTemp sV, dV, hi64, lo64, hi64r, lo64r;
- Int imm = (Int)insn[3];
- Int reg = eregOfRexRM(pfx,insn[2]);
- DIP("pslldq $%d,%s\n", imm, nameXMMReg(reg));
- vassert(imm >= 0 && imm <= 255);
- delta += 4;
+ assign(
+ dst64,
+ binop( Iop_32HLto64,
+ binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64hi) ),
+ binop( Iop_F64toI32S, mkexpr(rmode), mkexpr(f64lo) )
+ )
+ );
- sV = newTemp(Ity_V128);
- dV = newTemp(Ity_V128);
- hi64 = newTemp(Ity_I64);
- lo64 = newTemp(Ity_I64);
- hi64r = newTemp(Ity_I64);
- lo64r = newTemp(Ity_I64);
+ putMMXReg(gregLO3ofRM(modrm), mkexpr(dst64));
+ goto decode_success;
+ }
+ break;
- if (imm >= 16) {
- putXMMReg(reg, mkV128(0x0000));
+ case 0x2E:
+ case 0x2F:
+ /* 66 0F 2E = UCOMISD -- 64F0x2 comparison G,E, and set ZCP */
+ /* 66 0F 2F = COMISD -- 64F0x2 comparison G,E, and set ZCP */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_COMISD( vbi, pfx, delta, False/*!isAvx*/, opc );
+ goto decode_success;
+ }
+ /* 0F 2E = UCOMISS -- 32F0x4 comparison G,E, and set ZCP */
+ /* 0F 2F = COMISS -- 32F0x4 comparison G,E, and set ZCP */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_COMISS( vbi, pfx, delta, False/*!isAvx*/, opc );
+ goto decode_success;
+ }
+ break;
+
+ case 0x50:
+ /* 0F 50 = MOVMSKPS - move 4 sign bits from 4 x F32 in xmm(E)
+ to 4 lowest bits of ireg(G) */
+ if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
+ && epartIsReg(getUChar(delta))) {
+ /* sz == 8 is a kludge to handle insns with REX.W redundantly
+ set to 1, which has been known to happen:
+
+ 4c 0f 50 d9 rex64X movmskps %xmm1,%r11d
+
+ 20071106: Intel docs say that REX.W isn't redundant: when
+ present, a 64-bit register is written; when not present, only
+ the 32-bit half is written. However, testing on a Core2
+ machine suggests the entire 64 bit register is written
+ irrespective of the status of REX.W. That could be because
+ of the default rule that says "if the lower half of a 32-bit
+ register is written, the upper half is zeroed". By using
+ putIReg32 here we inadvertantly produce the same behaviour as
+ the Core2, for the same reason -- putIReg32 implements said
+ rule.
+
+ AMD docs give no indication that REX.W is even valid for this
+ insn. */
+ delta = dis_MOVMSKPS_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ /* 66 0F 50 = MOVMSKPD - move 2 sign bits from 2 x F64 in xmm(E) to
+ 2 lowest bits of ireg(G) */
+ if (have66noF2noF3(pfx) && (sz == 2 || sz == 8)) {
+ /* sz == 8 is a kludge to handle insns with REX.W redundantly
+ set to 1, which has been known to happen:
+ 66 4c 0f 50 d9 rex64X movmskpd %xmm1,%r11d
+ 20071106: see further comments on MOVMSKPS implementation above.
+ */
+ delta = dis_MOVMSKPD_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x51:
+ /* F3 0F 51 = SQRTSS -- approx sqrt 32F0x4 from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_unary_lo32( vbi, pfx, delta,
+ "sqrtss", Iop_Sqrt32F0x4 );
+ goto decode_success;
+ }
+ /* 0F 51 = SQRTPS -- approx sqrt 32Fx4 from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_unary_all( vbi, pfx, delta,
+ "sqrtps", Iop_Sqrt32Fx4 );
+ goto decode_success;
+ }
+ /* F2 0F 51 = SQRTSD -- approx sqrt 64F0x2 from R/M to R */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_unary_lo64( vbi, pfx, delta,
+ "sqrtsd", Iop_Sqrt64F0x2 );
+ goto decode_success;
+ }
+ /* 66 0F 51 = SQRTPD -- approx sqrt 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_unary_all( vbi, pfx, delta,
+ "sqrtpd", Iop_Sqrt64Fx2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x52:
+ /* F3 0F 52 = RSQRTSS -- approx reciprocal sqrt 32F0x4 from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_unary_lo32( vbi, pfx, delta,
+ "rsqrtss", Iop_RSqrt32F0x4 );
+ goto decode_success;
+ }
+ /* 0F 52 = RSQRTPS -- approx reciprocal sqrt 32Fx4 from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_unary_all( vbi, pfx, delta,
+ "rsqrtps", Iop_RSqrt32Fx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x53:
+ /* F3 0F 53 = RCPSS -- approx reciprocal 32F0x4 from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_unary_lo32( vbi, pfx, delta,
+ "rcpss", Iop_Recip32F0x4 );
+ goto decode_success;
+ }
+ /* 0F 53 = RCPPS -- approx reciprocal 32Fx4 from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_unary_all( vbi, pfx, delta,
+ "rcpps", Iop_Recip32Fx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x54:
+ /* 0F 54 = ANDPS -- G = G and E */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "andps", Iop_AndV128 );
+ goto decode_success;
+ }
+ /* 66 0F 54 = ANDPD -- G = G and E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "andpd", Iop_AndV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x55:
+ /* 0F 55 = ANDNPS -- G = (not G) and E */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all_invG( vbi, pfx, delta, "andnps",
+ Iop_AndV128 );
+ goto decode_success;
+ }
+ /* 66 0F 55 = ANDNPD -- G = (not G) and E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all_invG( vbi, pfx, delta, "andnpd",
+ Iop_AndV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x56:
+ /* 0F 56 = ORPS -- G = G and E */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "orps", Iop_OrV128 );
+ goto decode_success;
+ }
+ /* 66 0F 56 = ORPD -- G = G and E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "orpd", Iop_OrV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x57:
+ /* 66 0F 57 = XORPD -- G = G xor E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "xorpd", Iop_XorV128 );
+ goto decode_success;
+ }
+ /* 0F 57 = XORPS -- G = G xor E */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "xorps", Iop_XorV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x58:
+ /* 0F 58 = ADDPS -- add 32Fx4 from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "addps", Iop_Add32Fx4 );
+ goto decode_success;
+ }
+ /* F3 0F 58 = ADDSS -- add 32F0x4 from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta, "addss", Iop_Add32F0x4 );
+ goto decode_success;
+ }
+ /* F2 0F 58 = ADDSD -- add 64F0x2 from R/M to R */
+ if (haveF2no66noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta, "addsd", Iop_Add64F0x2 );
+ goto decode_success;
+ }
+ /* 66 0F 58 = ADDPD -- add 32Fx4 from R/M to R */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "addpd", Iop_Add64Fx2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x59:
+ /* F2 0F 59 = MULSD -- mul 64F0x2 from R/M to R */
+ if (haveF2no66noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta, "mulsd", Iop_Mul64F0x2 );
+ goto decode_success;
+ }
+ /* F3 0F 59 = MULSS -- mul 32F0x4 from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta, "mulss", Iop_Mul32F0x4 );
+ goto decode_success;
+ }
+ /* 0F 59 = MULPS -- mul 32Fx4 from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "mulps", Iop_Mul32Fx4 );
+ goto decode_success;
+ }
+ /* 66 0F 59 = MULPD -- mul 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "mulpd", Iop_Mul64Fx2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5A:
+ /* 0F 5A = CVTPS2PD -- convert 2 x F32 in low half mem/xmm to 2 x
+ F64 in xmm(G). */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_CVTPS2PD_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ /* F3 0F 5A = CVTSS2SD -- convert F32 in mem/low 1/4 xmm to F64 in
+ low half xmm(G) */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ IRTemp f32lo = newTemp(Ity_F32);
+
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ assign(f32lo, getXMMRegLane32F(eregOfRexRM(pfx,modrm), 0));
+ DIP("cvtss2sd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(f32lo, loadLE(Ity_F32, mkexpr(addr)));
+ delta += alen;
+ DIP("cvtss2sd %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+
+ putXMMRegLane64F( gregOfRexRM(pfx,modrm), 0,
+ unop( Iop_F32toF64, mkexpr(f32lo) ) );
+
+ goto decode_success;
+ }
+ /* F2 0F 5A = CVTSD2SS -- convert F64 in mem/low half xmm to F32 in
+ low 1/4 xmm(G), according to prevailing SSE rounding mode */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ IRTemp rmode = newTemp(Ity_I32);
+ IRTemp f64lo = newTemp(Ity_F64);
+
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ assign(f64lo, getXMMRegLane64F(eregOfRexRM(pfx,modrm), 0));
+ DIP("cvtsd2ss %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(f64lo, loadLE(Ity_F64, mkexpr(addr)));
+ delta += alen;
+ DIP("cvtsd2ss %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+
+ assign( rmode, get_sse_roundingmode() );
+ putXMMRegLane32F(
+ gregOfRexRM(pfx,modrm), 0,
+ binop( Iop_F64toF32, mkexpr(rmode), mkexpr(f64lo) )
+ );
+
+ goto decode_success;
+ }
+ /* 66 0F 5A = CVTPD2PS -- convert 2 x F64 in mem/xmm to 2 x F32 in
+ lo half xmm(G), rounding according to prevailing SSE rounding
+ mode, and zero upper half */
+ /* Note, this is practically identical to CVTPD2DQ. It would have
+ be nice to merge them together. */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_CVTPD2PS_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5B:
+ /* F3 0F 5B = CVTTPS2DQ -- convert 4 x F32 in mem/xmm to 4 x I32 in
+ xmm(G), rounding towards zero */
+ /* 66 0F 5B = CVTPS2DQ -- convert 4 x F32 in mem/xmm to 4 x I32 in
+ xmm(G), as per the prevailing rounding mode */
+ if ( (have66noF2noF3(pfx) && sz == 2)
+ || (haveF3no66noF2(pfx) && sz == 4) ) {
+ Bool r2zero = toBool(sz == 4); // FIXME -- unreliable (???)
+ delta = dis_CVTxPS2DQ_128( vbi, pfx, delta, False/*!isAvx*/, r2zero );
+ goto decode_success;
+ }
+ /* 0F 5B = CVTDQ2PS -- convert 4 x I32 in mem/xmm to 4 x F32 in
+ xmm(G) */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_CVTDQ2PS_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5C:
+ /* F3 0F 5C = SUBSS -- sub 32F0x4 from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta, "subss", Iop_Sub32F0x4 );
+ goto decode_success;
+ }
+ /* F2 0F 5C = SUBSD -- sub 64F0x2 from R/M to R */
+ if (haveF2no66noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta, "subsd", Iop_Sub64F0x2 );
+ goto decode_success;
+ }
+ /* 0F 5C = SUBPS -- sub 32Fx4 from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "subps", Iop_Sub32Fx4 );
+ goto decode_success;
+ }
+ /* 66 0F 5C = SUBPD -- sub 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "subpd", Iop_Sub64Fx2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5D:
+ /* 0F 5D = MINPS -- min 32Fx4 from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "minps", Iop_Min32Fx4 );
+ goto decode_success;
+ }
+ /* F3 0F 5D = MINSS -- min 32F0x4 from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta, "minss", Iop_Min32F0x4 );
+ goto decode_success;
+ }
+ /* F2 0F 5D = MINSD -- min 64F0x2 from R/M to R */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta, "minsd", Iop_Min64F0x2 );
+ goto decode_success;
+ }
+ /* 66 0F 5D = MINPD -- min 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "minpd", Iop_Min64Fx2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5E:
+ /* F2 0F 5E = DIVSD -- div 64F0x2 from R/M to R */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta, "divsd", Iop_Div64F0x2 );
+ goto decode_success;
+ }
+ /* 0F 5E = DIVPS -- div 32Fx4 from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "divps", Iop_Div32Fx4 );
+ goto decode_success;
+ }
+ /* F3 0F 5E = DIVSS -- div 32F0x4 from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta, "divss", Iop_Div32F0x4 );
+ goto decode_success;
+ }
+ /* 66 0F 5E = DIVPD -- div 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "divpd", Iop_Div64Fx2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5F:
+ /* 0F 5F = MAXPS -- max 32Fx4 from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "maxps", Iop_Max32Fx4 );
+ goto decode_success;
+ }
+ /* F3 0F 5F = MAXSS -- max 32F0x4 from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_lo32( vbi, pfx, delta, "maxss", Iop_Max32F0x4 );
+ goto decode_success;
+ }
+ /* F2 0F 5F = MAXSD -- max 64F0x2 from R/M to R */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ delta = dis_SSE_E_to_G_lo64( vbi, pfx, delta, "maxsd", Iop_Max64F0x2 );
+ goto decode_success;
+ }
+ /* 66 0F 5F = MAXPD -- max 64Fx2 from R/M to R */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "maxpd", Iop_Max64Fx2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x60:
+ /* 66 0F 60 = PUNPCKLBW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "punpcklbw",
+ Iop_InterleaveLO8x16, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x61:
+ /* 66 0F 61 = PUNPCKLWD */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "punpcklwd",
+ Iop_InterleaveLO16x8, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x62:
+ /* 66 0F 62 = PUNPCKLDQ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "punpckldq",
+ Iop_InterleaveLO32x4, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x63:
+ /* 66 0F 63 = PACKSSWB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "packsswb",
+ Iop_QNarrowBin16Sto8Sx16, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x64:
+ /* 66 0F 64 = PCMPGTB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pcmpgtb", Iop_CmpGT8Sx16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0x65:
+ /* 66 0F 65 = PCMPGTW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pcmpgtw", Iop_CmpGT16Sx8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0x66:
+ /* 66 0F 66 = PCMPGTD */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pcmpgtd", Iop_CmpGT32Sx4, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0x67:
+ /* 66 0F 67 = PACKUSWB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "packuswb",
+ Iop_QNarrowBin16Sto8Ux16, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x68:
+ /* 66 0F 68 = PUNPCKHBW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "punpckhbw",
+ Iop_InterleaveHI8x16, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x69:
+ /* 66 0F 69 = PUNPCKHWD */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "punpckhwd",
+ Iop_InterleaveHI16x8, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6A:
+ /* 66 0F 6A = PUNPCKHDQ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "punpckhdq",
+ Iop_InterleaveHI32x4, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6B:
+ /* 66 0F 6B = PACKSSDW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "packssdw",
+ Iop_QNarrowBin32Sto16Sx8, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6C:
+ /* 66 0F 6C = PUNPCKLQDQ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "punpcklqdq",
+ Iop_InterleaveLO64x2, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6D:
+ /* 66 0F 6D = PUNPCKHQDQ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "punpckhqdq",
+ Iop_InterleaveHI64x2, True );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6E:
+ /* 66 0F 6E = MOVD from ireg32/m32 to xmm lo 1/4,
+ zeroing high 3/4 of xmm. */
+ /* or from ireg64/m64 to xmm lo 1/2,
+ zeroing high 1/2 of xmm. */
+ if (have66noF2noF3(pfx)) {
+ vassert(sz == 2 || sz == 8);
+ if (sz == 2) sz = 4;
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ if (sz == 4) {
+ putXMMReg(
+ gregOfRexRM(pfx,modrm),
+ unop( Iop_32UtoV128, getIReg32(eregOfRexRM(pfx,modrm)) )
+ );
+ DIP("movd %s, %s\n", nameIReg32(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ putXMMReg(
+ gregOfRexRM(pfx,modrm),
+ unop( Iop_64UtoV128, getIReg64(eregOfRexRM(pfx,modrm)) )
+ );
+ DIP("movq %s, %s\n", nameIReg64(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ putXMMReg(
+ gregOfRexRM(pfx,modrm),
+ sz == 4
+ ? unop( Iop_32UtoV128,loadLE(Ity_I32, mkexpr(addr)) )
+ : unop( Iop_64UtoV128,loadLE(Ity_I64, mkexpr(addr)) )
+ );
+ DIP("mov%c %s, %s\n", sz == 4 ? 'd' : 'q', dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x6F:
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ /* 66 0F 6F = MOVDQA -- move from E (mem or xmm) to G (xmm). */
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ getXMMReg( eregOfRexRM(pfx,modrm) ));
+ DIP("movdqa %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("movdqa %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ /* F3 0F 6F = MOVDQU -- move from E (mem or xmm) to G (xmm). */
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ getXMMReg( eregOfRexRM(pfx,modrm) ));
+ DIP("movdqu %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("movdqu %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x70:
+ /* 66 0F 70 = PSHUFD -- rearrange 4x32 from E(xmm or mem) to G(xmm) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PSHUFD_32x4( vbi, pfx, delta, False/*!writesYmm*/);
+ goto decode_success;
+ }
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F 70 = PSHUFW -- rearrange 4x16 from E(mmx or mem) to G(mmx) */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ Int order;
+ IRTemp sV, dV, s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ sV = newTemp(Ity_I64);
+ dV = newTemp(Ity_I64);
+ do_MMX_preamble();
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
+ order = (Int)getUChar(delta+1);
+ delta += 1+1;
+ DIP("pshufw $%d,%s,%s\n", order,
+ nameMMXReg(eregLO3ofRM(modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf,
+ 1/*extra byte after amode*/ );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ order = (Int)getUChar(delta+alen);
+ delta += 1+alen;
+ DIP("pshufw $%d,%s,%s\n", order,
+ dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+ breakup64to16s( sV, &s3, &s2, &s1, &s0 );
+# define SEL(n) \
+ ((n)==0 ? s0 : ((n)==1 ? s1 : ((n)==2 ? s2 : s3)))
+ assign(dV,
+ mk64from16s( SEL((order>>6)&3), SEL((order>>4)&3),
+ SEL((order>>2)&3), SEL((order>>0)&3) )
+ );
+ putMMXReg(gregLO3ofRM(modrm), mkexpr(dV));
+# undef SEL
+ goto decode_success;
+ }
+ /* F2 0F 70 = PSHUFLW -- rearrange lower half 4x16 from E(xmm or
+ mem) to G(xmm), and copy upper half */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ delta = dis_PSHUFxW_128( vbi, pfx, delta,
+ False/*!isAvx*/, False/*!xIsH*/ );
+ goto decode_success;
+ }
+ /* F3 0F 70 = PSHUFHW -- rearrange upper half 4x16 from E(xmm or
+ mem) to G(xmm), and copy lower half */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_PSHUFxW_128( vbi, pfx, delta,
+ False/*!isAvx*/, True/*xIsH*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x71:
+ /* 66 0F 71 /2 ib = PSRLW by immediate */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 2) {
+ delta = dis_SSE_shiftE_imm( pfx, delta, "psrlw", Iop_ShrN16x8 );
+ goto decode_success;
+ }
+ /* 66 0F 71 /4 ib = PSRAW by immediate */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 4) {
+ delta = dis_SSE_shiftE_imm( pfx, delta, "psraw", Iop_SarN16x8 );
+ goto decode_success;
+ }
+ /* 66 0F 71 /6 ib = PSLLW by immediate */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 6) {
+ delta = dis_SSE_shiftE_imm( pfx, delta, "psllw", Iop_ShlN16x8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x72:
+ /* 66 0F 72 /2 ib = PSRLD by immediate */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 2) {
+ delta = dis_SSE_shiftE_imm( pfx, delta, "psrld", Iop_ShrN32x4 );
+ goto decode_success;
+ }
+ /* 66 0F 72 /4 ib = PSRAD by immediate */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 4) {
+ delta = dis_SSE_shiftE_imm( pfx, delta, "psrad", Iop_SarN32x4 );
+ goto decode_success;
+ }
+ /* 66 0F 72 /6 ib = PSLLD by immediate */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 6) {
+ delta = dis_SSE_shiftE_imm( pfx, delta, "pslld", Iop_ShlN32x4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x73:
+ /* 66 0F 73 /3 ib = PSRLDQ by immediate */
+ /* note, if mem case ever filled in, 1 byte after amode */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 3) {
+ Int imm = (Int)getUChar(delta+1);
+ Int reg = eregOfRexRM(pfx,getUChar(delta));
+ DIP("psrldq $%d,%s\n", imm, nameXMMReg(reg));
+ delta += 2;
+ IRTemp sV = newTemp(Ity_V128);
+ assign( sV, getXMMReg(reg) );
+ putXMMReg(reg, mkexpr(math_PSRLDQ( sV, imm )));
+ goto decode_success;
+ }
+ /* 66 0F 73 /7 ib = PSLLDQ by immediate */
+ /* note, if mem case ever filled in, 1 byte after amode */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 7) {
+ Int imm = (Int)getUChar(delta+1);
+ Int reg = eregOfRexRM(pfx,getUChar(delta));
+ DIP("pslldq $%d,%s\n", imm, nameXMMReg(reg));
+ vassert(imm >= 0 && imm <= 255);
+ delta += 2;
+ IRTemp sV = newTemp(Ity_V128);
+ assign( sV, getXMMReg(reg) );
+ putXMMReg(reg, mkexpr(math_PSLLDQ( sV, imm )));
+ goto decode_success;
+ }
+ /* 66 0F 73 /2 ib = PSRLQ by immediate */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 2) {
+ delta = dis_SSE_shiftE_imm( pfx, delta, "psrlq", Iop_ShrN64x2 );
+ goto decode_success;
+ }
+ /* 66 0F 73 /6 ib = PSLLQ by immediate */
+ if (have66noF2noF3(pfx) && sz == 2
+ && epartIsReg(getUChar(delta))
+ && gregLO3ofRM(getUChar(delta)) == 6) {
+ delta = dis_SSE_shiftE_imm( pfx, delta, "psllq", Iop_ShlN64x2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x74:
+ /* 66 0F 74 = PCMPEQB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pcmpeqb", Iop_CmpEQ8x16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0x75:
+ /* 66 0F 75 = PCMPEQW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pcmpeqw", Iop_CmpEQ16x8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0x76:
+ /* 66 0F 76 = PCMPEQD */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pcmpeqd", Iop_CmpEQ32x4, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0x7E:
+ /* F3 0F 7E = MOVQ -- move 64 bits from E (mem or lo half xmm) to
+ G (lo half xmm). Upper half of G is zeroed out. */
+ if (haveF3no66noF2(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 0,
+ getXMMRegLane64( eregOfRexRM(pfx,modrm), 0 ));
+ /* zero bits 127:64 */
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 1, mkU64(0) );
+ DIP("movsd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putXMMReg( gregOfRexRM(pfx,modrm), mkV128(0) );
+ putXMMRegLane64( gregOfRexRM(pfx,modrm), 0,
+ loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("movsd %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* 66 0F 7E = MOVD from xmm low 1/4 to ireg32 or m32. */
+ /* or from xmm low 1/2 to ireg64 or m64. */
+ if (have66noF2noF3(pfx) && (sz == 2 || sz == 8)) {
+ if (sz == 2) sz = 4;
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ if (sz == 4) {
+ putIReg32( eregOfRexRM(pfx,modrm),
+ getXMMRegLane32(gregOfRexRM(pfx,modrm), 0) );
+ DIP("movd %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ nameIReg32(eregOfRexRM(pfx,modrm)));
+ } else {
+ putIReg64( eregOfRexRM(pfx,modrm),
+ getXMMRegLane64(gregOfRexRM(pfx,modrm), 0) );
+ DIP("movq %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ nameIReg64(eregOfRexRM(pfx,modrm)));
+ }
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ storeLE( mkexpr(addr),
+ sz == 4
+ ? getXMMRegLane32(gregOfRexRM(pfx,modrm),0)
+ : getXMMRegLane64(gregOfRexRM(pfx,modrm),0) );
+ DIP("mov%c %s, %s\n", sz == 4 ? 'd' : 'q',
+ nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf);
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x7F:
+ /* F3 0F 7F = MOVDQU -- move from G (xmm) to E (mem or xmm). */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ goto decode_failure; /* awaiting test case */
+ delta += 1;
+ putXMMReg( eregOfRexRM(pfx,modrm),
+ getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movdqu %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ nameXMMReg(eregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movdqu %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf);
+ }
+ goto decode_success;
+ }
+ /* 66 0F 7F = MOVDQA -- move from G (xmm) to E (mem or xmm). */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ putXMMReg( eregOfRexRM(pfx,modrm),
+ getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movdqa %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
+ nameXMMReg(eregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ delta += alen;
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movdqa %s, %s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf);
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0xAE:
+ /* 0F AE /7 = SFENCE -- flush pending operations to memory */
+ if (haveNo66noF2noF3(pfx)
+ && epartIsReg(getUChar(delta)) && gregLO3ofRM(getUChar(delta)) == 7
+ && sz == 4) {
+ delta += 1;
+ /* Insert a memory fence. It's sometimes important that these
+ are carried through to the generated code. */
+ stmt( IRStmt_MBE(Imbe_Fence) );
+ DIP("sfence\n");
+ goto decode_success;
+ }
+ /* mindless duplication follows .. */
+ /* 0F AE /5 = LFENCE -- flush pending operations to memory */
+ /* 0F AE /6 = MFENCE -- flush pending operations to memory */
+ if (haveNo66noF2noF3(pfx)
+ && epartIsReg(getUChar(delta))
+ && (gregLO3ofRM(getUChar(delta)) == 5
+ || gregLO3ofRM(getUChar(delta)) == 6)
+ && sz == 4) {
+ delta += 1;
+ /* Insert a memory fence. It's sometimes important that these
+ are carried through to the generated code. */
+ stmt( IRStmt_MBE(Imbe_Fence) );
+ DIP("%sfence\n", gregLO3ofRM(getUChar(delta-1))==5 ? "l" : "m");
goto decode_success;
}
- assign( sV, getXMMReg(reg) );
- assign( hi64, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( lo64, unop(Iop_V128to64, mkexpr(sV)) );
+ /* 0F AE /7 = CLFLUSH -- flush cache line */
+ if (haveNo66noF2noF3(pfx)
+ && !epartIsReg(getUChar(delta)) && gregLO3ofRM(getUChar(delta)) == 7
+ && sz == 4) {
- if (imm == 0) {
- assign( lo64r, mkexpr(lo64) );
- assign( hi64r, mkexpr(hi64) );
- }
- else
- if (imm == 8) {
- assign( lo64r, mkU64(0) );
- assign( hi64r, mkexpr(lo64) );
- }
- else
- if (imm > 8) {
- assign( lo64r, mkU64(0) );
- assign( hi64r, binop( Iop_Shl64,
- mkexpr(lo64),
- mkU8( 8*(imm-8) ) ));
- } else {
- assign( lo64r, binop( Iop_Shl64,
- mkexpr(lo64),
- mkU8(8 * imm) ));
- assign( hi64r,
- binop( Iop_Or64,
- binop(Iop_Shl64, mkexpr(hi64),
- mkU8(8 * imm)),
- binop(Iop_Shr64, mkexpr(lo64),
- mkU8(8 * (8 - imm)) )
- )
- );
- }
- assign( dV, binop(Iop_64HLtoV128, mkexpr(hi64r), mkexpr(lo64r)) );
- putXMMReg(reg, mkexpr(dV));
- goto decode_success;
- }
+ /* This is something of a hack. We need to know the size of
+ the cache line containing addr. Since we don't (easily),
+ assume 256 on the basis that no real cache would have a
+ line that big. It's safe to invalidate more stuff than we
+ need, just inefficient. */
+ ULong lineszB = 256ULL;
- /* 66 0F 73 /6 ib = PSLLQ by immediate */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x73
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 6) {
- delta = dis_SSE_shiftE_imm( pfx, delta+2, "psllq", Iop_ShlN64x2 );
- goto decode_success;
- }
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
- /* 66 0F F3 = PSLLQ by E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF3) {
- delta = dis_SSE_shiftG_byE( vbi, pfx, delta+2, "psllq", Iop_ShlN64x2 );
- goto decode_success;
- }
+ /* Round addr down to the start of the containing block. */
+ stmt( IRStmt_Put(
+ OFFB_TISTART,
+ binop( Iop_And64,
+ mkexpr(addr),
+ mkU64( ~(lineszB-1) ))) );
- /* 66 0F 71 /6 ib = PSLLW by immediate */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x71
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 6) {
- delta = dis_SSE_shiftE_imm( pfx, delta+2, "psllw", Iop_ShlN16x8 );
- goto decode_success;
- }
+ stmt( IRStmt_Put(OFFB_TILEN, mkU64(lineszB) ) );
- /* 66 0F F1 = PSLLW by E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF1) {
- delta = dis_SSE_shiftG_byE( vbi, pfx, delta+2, "psllw", Iop_ShlN16x8 );
- goto decode_success;
- }
+ jmp_lit(dres, Ijk_TInval, (Addr64)(guest_RIP_bbstart+delta));
- /* 66 0F 72 /4 ib = PSRAD by immediate */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x72
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 4) {
- delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrad", Iop_SarN32x4 );
- goto decode_success;
- }
-
- /* 66 0F E2 = PSRAD by E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE2) {
- delta = dis_SSE_shiftG_byE( vbi, pfx, delta+2, "psrad", Iop_SarN32x4 );
- goto decode_success;
- }
-
- /* 66 0F 71 /4 ib = PSRAW by immediate */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x71
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 4) {
- delta = dis_SSE_shiftE_imm( pfx, delta+2, "psraw", Iop_SarN16x8 );
- goto decode_success;
- }
-
- /* 66 0F E1 = PSRAW by E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE1) {
- delta = dis_SSE_shiftG_byE( vbi, pfx, delta+2, "psraw", Iop_SarN16x8 );
- goto decode_success;
- }
-
- /* 66 0F 72 /2 ib = PSRLD by immediate */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x72
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 2) {
- delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrld", Iop_ShrN32x4 );
- goto decode_success;
- }
-
- /* 66 0F D2 = PSRLD by E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD2) {
- delta = dis_SSE_shiftG_byE( vbi, pfx, delta+2, "psrld", Iop_ShrN32x4 );
- goto decode_success;
- }
-
- /* 66 0F 73 /3 ib = PSRLDQ by immediate */
- /* note, if mem case ever filled in, 1 byte after amode */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x73
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 3) {
- IRTemp sV, dV, hi64, lo64, hi64r, lo64r;
- Int imm = (Int)insn[3];
- Int reg = eregOfRexRM(pfx,insn[2]);
- DIP("psrldq $%d,%s\n", imm, nameXMMReg(reg));
- vassert(imm >= 0 && imm <= 255);
- delta += 4;
-
- sV = newTemp(Ity_V128);
- dV = newTemp(Ity_V128);
- hi64 = newTemp(Ity_I64);
- lo64 = newTemp(Ity_I64);
- hi64r = newTemp(Ity_I64);
- lo64r = newTemp(Ity_I64);
-
- if (imm >= 16) {
- putXMMReg(reg, mkV128(0x0000));
+ DIP("clflush %s\n", dis_buf);
goto decode_success;
}
- assign( sV, getXMMReg(reg) );
- assign( hi64, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( lo64, unop(Iop_V128to64, mkexpr(sV)) );
-
- if (imm == 0) {
- assign( lo64r, mkexpr(lo64) );
- assign( hi64r, mkexpr(hi64) );
+ /* 0F AE /3 = STMXCSR m32 -- store %mxcsr */
+ if (haveNo66noF2noF3(pfx)
+ && !epartIsReg(getUChar(delta)) && gregLO3ofRM(getUChar(delta)) == 3
+ && sz == 4) {
+ delta = dis_STMXCSR(vbi, pfx, delta, False/*!isAvx*/);
+ goto decode_success;
}
- else
- if (imm == 8) {
- assign( hi64r, mkU64(0) );
- assign( lo64r, mkexpr(hi64) );
+ /* 0F AE /2 = LDMXCSR m32 -- load %mxcsr */
+ if (haveNo66noF2noF3(pfx)
+ && !epartIsReg(getUChar(delta)) && gregLO3ofRM(getUChar(delta)) == 2
+ && sz == 4) {
+ delta = dis_LDMXCSR(vbi, pfx, delta, False/*!isAvx*/);
+ goto decode_success;
}
- else
- if (imm > 8) {
- assign( hi64r, mkU64(0) );
- assign( lo64r, binop( Iop_Shr64,
- mkexpr(hi64),
- mkU8( 8*(imm-8) ) ));
- } else {
- assign( hi64r, binop( Iop_Shr64,
- mkexpr(hi64),
- mkU8(8 * imm) ));
- assign( lo64r,
- binop( Iop_Or64,
- binop(Iop_Shr64, mkexpr(lo64),
- mkU8(8 * imm)),
- binop(Iop_Shl64, mkexpr(hi64),
- mkU8(8 * (8 - imm)) )
- )
- );
+ /* 0F AE /0 = FXSAVE m512 -- write x87 and SSE state to memory.
+ Note that the presence or absence of REX.W slightly affects the
+ written format: whether the saved FPU IP and DP pointers are 64
+ or 32 bits. But the helper function we call simply writes zero
+ bits in the relevant fields (which are 64 bits regardless of
+ what REX.W is) and so it's good enough (iow, equally broken) in
+ both cases. */
+ if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
+ && !epartIsReg(getUChar(delta))
+ && gregOfRexRM(pfx,getUChar(delta)) == 0) {
+ IRDirty* d;
+ modrm = getUChar(delta);
+ vassert(!epartIsReg(modrm));
+
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_16_aligned(addr);
+
+ DIP("%sfxsave %s\n", sz==8 ? "rex64/" : "", dis_buf);
+
+ /* Uses dirty helper:
+ void amd64g_do_FXSAVE ( VexGuestAMD64State*, ULong ) */
+ d = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_FXSAVE",
+ &amd64g_dirtyhelper_FXSAVE,
+ mkIRExprVec_1( mkexpr(addr) )
+ );
+ d->needsBBP = True;
+
+ /* declare we're writing memory */
+ d->mFx = Ifx_Write;
+ d->mAddr = mkexpr(addr);
+ d->mSize = 464; /* according to recent Intel docs */
+
+ /* declare we're reading guest state */
+ d->nFxState = 7;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
+
+ d->fxState[0].fx = Ifx_Read;
+ d->fxState[0].offset = OFFB_FTOP;
+ d->fxState[0].size = sizeof(UInt);
+
+ d->fxState[1].fx = Ifx_Read;
+ d->fxState[1].offset = OFFB_FPREGS;
+ d->fxState[1].size = 8 * sizeof(ULong);
+
+ d->fxState[2].fx = Ifx_Read;
+ d->fxState[2].offset = OFFB_FPTAGS;
+ d->fxState[2].size = 8 * sizeof(UChar);
+
+ d->fxState[3].fx = Ifx_Read;
+ d->fxState[3].offset = OFFB_FPROUND;
+ d->fxState[3].size = sizeof(ULong);
+
+ d->fxState[4].fx = Ifx_Read;
+ d->fxState[4].offset = OFFB_FC3210;
+ d->fxState[4].size = sizeof(ULong);
+
+ d->fxState[5].fx = Ifx_Read;
+ d->fxState[5].offset = OFFB_YMM0;
+ d->fxState[5].size = sizeof(U128);
+ /* plus 15 more of the above, spaced out in YMM sized steps */
+ d->fxState[5].nRepeats = 15;
+ d->fxState[5].repeatLen = sizeof(U256);
+
+ d->fxState[6].fx = Ifx_Read;
+ d->fxState[6].offset = OFFB_SSEROUND;
+ d->fxState[6].size = sizeof(ULong);
+
+ /* Be paranoid ... this assertion tries to ensure the 16 %ymm
+ images are packed back-to-back. If not, the settings for
+ d->fxState[5] are wrong. */
+ vassert(32 == sizeof(U256));
+ vassert(OFFB_YMM15 == (OFFB_YMM0 + 15 * 32));
+
+ stmt( IRStmt_Dirty(d) );
+
+ goto decode_success;
}
+ /* 0F AE /1 = FXRSTOR m512 -- read x87 and SSE state from memory.
+ As with FXSAVE above we ignore the value of REX.W since we're
+ not bothering with the FPU DP and IP fields. */
+ if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
+ && !epartIsReg(getUChar(delta))
+ && gregOfRexRM(pfx,getUChar(delta)) == 1) {
+ IRDirty* d;
+ modrm = getUChar(delta);
+ vassert(!epartIsReg(modrm));
- assign( dV, binop(Iop_64HLtoV128, mkexpr(hi64r), mkexpr(lo64r)) );
- putXMMReg(reg, mkexpr(dV));
- goto decode_success;
- }
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_16_aligned(addr);
- /* 66 0F 73 /2 ib = PSRLQ by immediate */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x73
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 2) {
- delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrlq", Iop_ShrN64x2 );
- goto decode_success;
- }
+ DIP("%sfxrstor %s\n", sz==8 ? "rex64/" : "", dis_buf);
- /* 66 0F D3 = PSRLQ by E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD3) {
- delta = dis_SSE_shiftG_byE( vbi, pfx, delta+2, "psrlq", Iop_ShrN64x2 );
- goto decode_success;
- }
+ /* Uses dirty helper:
+ VexEmWarn amd64g_do_FXRSTOR ( VexGuestAMD64State*, ULong )
+ NOTE:
+ the VexEmWarn value is simply ignored
+ */
+ d = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_FXRSTOR",
+ &amd64g_dirtyhelper_FXRSTOR,
+ mkIRExprVec_1( mkexpr(addr) )
+ );
+ d->needsBBP = True;
- /* 66 0F 71 /2 ib = PSRLW by immediate */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x71
- && epartIsReg(insn[2])
- && gregLO3ofRM(insn[2]) == 2) {
- delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrlw", Iop_ShrN16x8 );
- goto decode_success;
- }
+ /* declare we're reading memory */
+ d->mFx = Ifx_Read;
+ d->mAddr = mkexpr(addr);
+ d->mSize = 464; /* according to recent Intel docs */
- /* 66 0F D1 = PSRLW by E */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD1) {
- delta = dis_SSE_shiftG_byE( vbi, pfx, delta+2, "psrlw", Iop_ShrN16x8 );
- goto decode_success;
- }
+ /* declare we're writing guest state */
+ d->nFxState = 7;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
- /* 66 0F F8 = PSUBB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF8) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "psubb", Iop_Sub8x16, False );
- goto decode_success;
- }
+ d->fxState[0].fx = Ifx_Write;
+ d->fxState[0].offset = OFFB_FTOP;
+ d->fxState[0].size = sizeof(UInt);
- /* 66 0F FA = PSUBD */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFA) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "psubd", Iop_Sub32x4, False );
- goto decode_success;
- }
+ d->fxState[1].fx = Ifx_Write;
+ d->fxState[1].offset = OFFB_FPREGS;
+ d->fxState[1].size = 8 * sizeof(ULong);
- /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
- /* 0F FB = PSUBQ -- sub 64x1 */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xFB) {
- do_MMX_preamble();
- delta = dis_MMXop_regmem_to_reg (
- vbi, pfx, delta+2, insn[1], "psubq", False );
- goto decode_success;
- }
+ d->fxState[2].fx = Ifx_Write;
+ d->fxState[2].offset = OFFB_FPTAGS;
+ d->fxState[2].size = 8 * sizeof(UChar);
- /* 66 0F FB = PSUBQ */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xFB) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "psubq", Iop_Sub64x2, False );
- goto decode_success;
- }
+ d->fxState[3].fx = Ifx_Write;
+ d->fxState[3].offset = OFFB_FPROUND;
+ d->fxState[3].size = sizeof(ULong);
- /* 66 0F F9 = PSUBW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF9) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "psubw", Iop_Sub16x8, False );
- goto decode_success;
- }
+ d->fxState[4].fx = Ifx_Write;
+ d->fxState[4].offset = OFFB_FC3210;
+ d->fxState[4].size = sizeof(ULong);
- /* 66 0F E8 = PSUBSB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE8) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "psubsb", Iop_QSub8Sx16, False );
- goto decode_success;
- }
+ d->fxState[5].fx = Ifx_Write;
+ d->fxState[5].offset = OFFB_YMM0;
+ d->fxState[5].size = sizeof(U128);
+ /* plus 15 more of the above, spaced out in YMM sized steps */
+ d->fxState[5].nRepeats = 15;
+ d->fxState[5].repeatLen = sizeof(U256);
- /* 66 0F E9 = PSUBSW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE9) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "psubsw", Iop_QSub16Sx8, False );
- goto decode_success;
- }
+ d->fxState[6].fx = Ifx_Write;
+ d->fxState[6].offset = OFFB_SSEROUND;
+ d->fxState[6].size = sizeof(ULong);
- /* 66 0F D8 = PSUBSB */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD8) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "psubusb", Iop_QSub8Ux16, False );
- goto decode_success;
- }
+ /* Be paranoid ... this assertion tries to ensure the 16 %ymm
+ images are packed back-to-back. If not, the settings for
+ d->fxState[5] are wrong. */
+ vassert(32 == sizeof(U256));
+ vassert(OFFB_YMM15 == (OFFB_YMM0 + 15 * 32));
- /* 66 0F D9 = PSUBSW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD9) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "psubusw", Iop_QSub16Ux8, False );
- goto decode_success;
- }
+ stmt( IRStmt_Dirty(d) );
- /* 66 0F 68 = PUNPCKHBW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x68) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "punpckhbw",
- Iop_InterleaveHI8x16, True );
- goto decode_success;
- }
-
- /* 66 0F 6A = PUNPCKHDQ */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x6A) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "punpckhdq",
- Iop_InterleaveHI32x4, True );
- goto decode_success;
- }
-
- /* 66 0F 6D = PUNPCKHQDQ */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x6D) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "punpckhqdq",
- Iop_InterleaveHI64x2, True );
- goto decode_success;
- }
-
- /* 66 0F 69 = PUNPCKHWD */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x69) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "punpckhwd",
- Iop_InterleaveHI16x8, True );
- goto decode_success;
- }
-
- /* 66 0F 60 = PUNPCKLBW */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x60) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "punpcklbw",
- Iop_InterleaveLO8x16, True );
- goto decode_success;
- }
-
- /* 66 0F 62 = PUNPCKLDQ */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x62) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "punpckldq",
- Iop_InterleaveLO32x4, True );
- goto decode_success;
- }
-
- /* 66 0F 6C = PUNPCKLQDQ */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x6C) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "punpcklqdq",
- Iop_InterleaveLO64x2, True );
- goto decode_success;
- }
-
- /* 66 0F 61 = PUNPCKLWD */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x61) {
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
- "punpcklwd",
- Iop_InterleaveLO16x8, True );
- goto decode_success;
- }
-
- /* 66 0F EF = PXOR */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEF) {
- delta = dis_SSE_E_to_G_all( vbi, pfx, delta+2, "pxor", Iop_XorV128 );
- goto decode_success;
- }
-
-//.. //-- /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. */
-//.. //-- if (insn[0] == 0x0F && insn[1] == 0xAE
-//.. //-- && (!epartIsReg(insn[2]))
-//.. //-- && (gregOfRM(insn[2]) == 1 || gregOfRM(insn[2]) == 0) ) {
-//.. //-- Bool store = gregOfRM(insn[2]) == 0;
-//.. //-- vg_assert(sz == 4);
-//.. //-- pair = disAMode ( cb, sorb, eip+2, dis_buf );
-//.. //-- t1 = LOW24(pair);
-//.. //-- eip += 2+HI8(pair);
-//.. //-- uInstr3(cb, store ? SSE2a_MemWr : SSE2a_MemRd, 512,
-//.. //-- Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1],
-//.. //-- Lit16, (UShort)insn[2],
-//.. //-- TempReg, t1 );
-//.. //-- DIP("fx%s %s\n", store ? "save" : "rstor", dis_buf );
-//.. //-- goto decode_success;
-//.. //-- }
-
- /* 0F AE /7 = CLFLUSH -- flush cache line */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xAE
- && !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 7) {
-
- /* This is something of a hack. We need to know the size of the
- cache line containing addr. Since we don't (easily), assume
- 256 on the basis that no real cache would have a line that
- big. It's safe to invalidate more stuff than we need, just
- inefficient. */
- ULong lineszB = 256ULL;
-
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- delta += 2+alen;
-
- /* Round addr down to the start of the containing block. */
- stmt( IRStmt_Put(
- OFFB_TISTART,
- binop( Iop_And64,
- mkexpr(addr),
- mkU64( ~(lineszB-1) ))) );
-
- stmt( IRStmt_Put(OFFB_TILEN, mkU64(lineszB) ) );
-
- irsb->jumpkind = Ijk_TInval;
- irsb->next = mkU64(guest_RIP_bbstart+delta);
- dres.whatNext = Dis_StopHere;
-
- DIP("clflush %s\n", dis_buf);
- goto decode_success;
- }
-
- /* ---------------------------------------------------- */
- /* --- end of the SSE/SSE2 decoder. --- */
- /* ---------------------------------------------------- */
-
- /* ---------------------------------------------------- */
- /* --- start of the SSE3 decoder. --- */
- /* ---------------------------------------------------- */
-
- /* F3 0F 12 = MOVSLDUP -- move from E (mem or xmm) to G (xmm),
- duplicating some lanes (2:2:0:0). */
- /* F3 0F 16 = MOVSHDUP -- move from E (mem or xmm) to G (xmm),
- duplicating some lanes (3:3:1:1). */
- if (haveF3no66noF2(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x12 || insn[1] == 0x16)) {
- IRTemp s3, s2, s1, s0;
- IRTemp sV = newTemp(Ity_V128);
- Bool isH = insn[1] == 0x16;
- s3 = s2 = s1 = s0 = IRTemp_INVALID;
-
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg( eregOfRexRM(pfx,modrm)) );
- DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l',
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- DIP("movs%cdup %s,%s\n", isH ? 'h' : 'l',
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
+ goto decode_success;
}
+ break;
- breakup128to32s( sV, &s3, &s2, &s1, &s0 );
- putXMMReg( gregOfRexRM(pfx,modrm),
- isH ? mk128from32s( s3, s3, s1, s1 )
- : mk128from32s( s2, s2, s0, s0 ) );
- goto decode_success;
- }
-
- /* F2 0F 12 = MOVDDUP -- move from E (mem or xmm) to G (xmm),
- duplicating some lanes (0:1:0:1). */
- if (haveF2no66noF3(pfx)
- && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x12) {
- IRTemp sV = newTemp(Ity_V128);
- IRTemp d0 = newTemp(Ity_I64);
-
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg( eregOfRexRM(pfx,modrm)) );
- DIP("movddup %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- assign ( d0, unop(Iop_V128to64, mkexpr(sV)) );
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( d0, loadLE(Ity_I64, mkexpr(addr)) );
- DIP("movddup %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
+ case 0xC2:
+ /* 0F C2 = CMPPS -- 32Fx4 comparison from R/M to R */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ Long delta0 = delta;
+ delta = dis_SSE_cmp_E_to_G( vbi, pfx, delta, "cmpps", True, 4 );
+ if (delta > delta0) goto decode_success;
}
-
- putXMMReg( gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128,mkexpr(d0),mkexpr(d0)) );
- goto decode_success;
- }
-
- /* F2 0F D0 = ADDSUBPS -- 32x4 +/-/+/- from E (mem or xmm) to G (xmm). */
- if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xD0) {
- IRTemp a3, a2, a1, a0, s3, s2, s1, s0;
- IRTemp eV = newTemp(Ity_V128);
- IRTemp gV = newTemp(Ity_V128);
- IRTemp addV = newTemp(Ity_V128);
- IRTemp subV = newTemp(Ity_V128);
- a3 = a2 = a1 = a0 = s3 = s2 = s1 = s0 = IRTemp_INVALID;
-
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( eV, getXMMReg( eregOfRexRM(pfx,modrm)) );
- DIP("addsubps %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
- DIP("addsubps %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
+ /* F3 0F C2 = CMPSS -- 32F0x4 comparison from R/M to R */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ Long delta0 = delta;
+ delta = dis_SSE_cmp_E_to_G( vbi, pfx, delta, "cmpss", False, 4 );
+ if (delta > delta0) goto decode_success;
}
-
- assign( gV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- assign( addV, binop(Iop_Add32Fx4, mkexpr(gV), mkexpr(eV)) );
- assign( subV, binop(Iop_Sub32Fx4, mkexpr(gV), mkexpr(eV)) );
-
- breakup128to32s( addV, &a3, &a2, &a1, &a0 );
- breakup128to32s( subV, &s3, &s2, &s1, &s0 );
-
- putXMMReg( gregOfRexRM(pfx,modrm), mk128from32s( a3, s2, a1, s0 ));
- goto decode_success;
- }
-
- /* 66 0F D0 = ADDSUBPD -- 64x4 +/- from E (mem or xmm) to G (xmm). */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0xD0) {
- IRTemp eV = newTemp(Ity_V128);
- IRTemp gV = newTemp(Ity_V128);
- IRTemp addV = newTemp(Ity_V128);
- IRTemp subV = newTemp(Ity_V128);
- IRTemp a1 = newTemp(Ity_I64);
- IRTemp s0 = newTemp(Ity_I64);
-
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( eV, getXMMReg( eregOfRexRM(pfx,modrm)) );
- DIP("addsubpd %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
- DIP("addsubpd %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
+ /* F2 0F C2 = CMPSD -- 64F0x2 comparison from R/M to R */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ Long delta0 = delta;
+ delta = dis_SSE_cmp_E_to_G( vbi, pfx, delta, "cmpsd", False, 8 );
+ if (delta > delta0) goto decode_success;
}
+ /* 66 0F C2 = CMPPD -- 64Fx2 comparison from R/M to R */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ Long delta0 = delta;
+ delta = dis_SSE_cmp_E_to_G( vbi, pfx, delta, "cmppd", True, 8 );
+ if (delta > delta0) goto decode_success;
+ }
+ break;
- assign( gV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+ case 0xC3:
+ /* 0F C3 = MOVNTI -- for us, just a plain ireg store. */
+ if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)) {
+ modrm = getUChar(delta);
+ if (!epartIsReg(modrm)) {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getIRegG(sz, pfx, modrm) );
+ DIP("movnti %s,%s\n", dis_buf,
+ nameIRegG(sz, pfx, modrm));
+ delta += alen;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ break;
- assign( addV, binop(Iop_Add64Fx2, mkexpr(gV), mkexpr(eV)) );
- assign( subV, binop(Iop_Sub64Fx2, mkexpr(gV), mkexpr(eV)) );
+ case 0xC4:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
+ put it into the specified lane of mmx(G). */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ /* Use t0 .. t3 to hold the 4 original 16-bit lanes of the
+ mmx reg. t4 is the new lane value. t5 is the original
+ mmx value. t6 is the new mmx value. */
+ Int lane;
+ t4 = newTemp(Ity_I16);
+ t5 = newTemp(Ity_I64);
+ t6 = newTemp(Ity_I64);
+ modrm = getUChar(delta);
+ do_MMX_preamble();
- assign( a1, unop(Iop_V128HIto64, mkexpr(addV) ));
- assign( s0, unop(Iop_V128to64, mkexpr(subV) ));
+ assign(t5, getMMXReg(gregLO3ofRM(modrm)));
+ breakup64to16s( t5, &t3, &t2, &t1, &t0 );
- putXMMReg( gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128, mkexpr(a1), mkexpr(s0)) );
- goto decode_success;
- }
+ if (epartIsReg(modrm)) {
+ assign(t4, getIReg16(eregOfRexRM(pfx,modrm)));
+ delta += 1+1;
+ lane = getUChar(delta-1);
+ DIP("pinsrw $%d,%s,%s\n", (Int)lane,
+ nameIReg16(eregOfRexRM(pfx,modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += 1+alen;
+ lane = getUChar(delta-1);
+ assign(t4, loadLE(Ity_I16, mkexpr(addr)));
+ DIP("pinsrw $%d,%s,%s\n", (Int)lane,
+ dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
- /* F2 0F 7D = HSUBPS -- 32x4 sub across from E (mem or xmm) to G (xmm). */
- /* F2 0F 7C = HADDPS -- 32x4 add across from E (mem or xmm) to G (xmm). */
- if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && (insn[1] == 0x7C || insn[1] == 0x7D)) {
- IRTemp e3, e2, e1, e0, g3, g2, g1, g0;
- IRTemp eV = newTemp(Ity_V128);
- IRTemp gV = newTemp(Ity_V128);
- IRTemp leftV = newTemp(Ity_V128);
- IRTemp rightV = newTemp(Ity_V128);
- Bool isAdd = insn[1] == 0x7C;
- HChar* str = isAdd ? "add" : "sub";
- e3 = e2 = e1 = e0 = g3 = g2 = g1 = g0 = IRTemp_INVALID;
+ switch (lane & 3) {
+ case 0: assign(t6, mk64from16s(t3,t2,t1,t4)); break;
+ case 1: assign(t6, mk64from16s(t3,t2,t4,t0)); break;
+ case 2: assign(t6, mk64from16s(t3,t4,t1,t0)); break;
+ case 3: assign(t6, mk64from16s(t4,t2,t1,t0)); break;
+ default: vassert(0);
+ }
+ putMMXReg(gregLO3ofRM(modrm), mkexpr(t6));
+ goto decode_success;
+ }
+ /* 66 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
+ put it into the specified lane of xmm(G). */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ Int lane;
+ t4 = newTemp(Ity_I16);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign(t4, getIReg16(rE));
+ delta += 1+1;
+ lane = getUChar(delta-1);
+ DIP("pinsrw $%d,%s,%s\n",
+ (Int)lane, nameIReg16(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf,
+ 1/*byte after the amode*/ );
+ delta += 1+alen;
+ lane = getUChar(delta-1);
+ assign(t4, loadLE(Ity_I16, mkexpr(addr)));
+ DIP("pinsrw $%d,%s,%s\n",
+ (Int)lane, dis_buf, nameXMMReg(rG));
+ }
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg(rG));
+ IRTemp res_vec = math_PINSRW_128( src_vec, t4, lane & 7);
+ putXMMReg(rG, mkexpr(res_vec));
+ goto decode_success;
+ }
+ break;
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( eV, getXMMReg( eregOfRexRM(pfx,modrm)) );
- DIP("h%sps %s,%s\n", str, nameXMMReg(eregOfRexRM(pfx,modrm)),
+ case 0xC5:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F C5 = PEXTRW -- extract 16-bit field from mmx(E) and put
+ zero-extend of it in ireg(G). */
+ if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ IRTemp sV = newTemp(Ity_I64);
+ t5 = newTemp(Ity_I16);
+ do_MMX_preamble();
+ assign(sV, getMMXReg(eregLO3ofRM(modrm)));
+ breakup64to16s( sV, &t3, &t2, &t1, &t0 );
+ switch (getUChar(delta+1) & 3) {
+ case 0: assign(t5, mkexpr(t0)); break;
+ case 1: assign(t5, mkexpr(t1)); break;
+ case 2: assign(t5, mkexpr(t2)); break;
+ case 3: assign(t5, mkexpr(t3)); break;
+ default: vassert(0);
+ }
+ if (sz == 8)
+ putIReg64(gregOfRexRM(pfx,modrm), unop(Iop_16Uto64, mkexpr(t5)));
+ else
+ putIReg32(gregOfRexRM(pfx,modrm), unop(Iop_16Uto32, mkexpr(t5)));
+ DIP("pextrw $%d,%s,%s\n",
+ (Int)getUChar(delta+1),
+ nameMMXReg(eregLO3ofRM(modrm)),
+ sz==8 ? nameIReg64(gregOfRexRM(pfx,modrm))
+ : nameIReg32(gregOfRexRM(pfx,modrm))
+ );
+ delta += 2;
+ goto decode_success;
+ }
+ /* else fall through */
+ /* note, for anyone filling in the mem case: this insn has one
+ byte after the amode and therefore you must pass 1 as the
+ last arg to disAMode */
+ }
+ /* 66 0F C5 = PEXTRW -- extract 16-bit field from xmm(E) and put
+ zero-extend of it in ireg(G). */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ Long delta0 = delta;
+ delta = dis_PEXTRW_128_EregOnly_toG( vbi, pfx, delta,
+ False/*!isAvx*/ );
+ if (delta > delta0) goto decode_success;
+ /* else fall through -- decoding has failed */
+ }
+ break;
+
+ case 0xC6:
+ /* 0F C6 /r ib = SHUFPS -- shuffle packed F32s */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ Int imm8 = 0;
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ assign( dV, getXMMReg(rG) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ imm8 = (Int)getUChar(delta+1);
+ delta += 1+1;
+ DIP("shufps $%d,%s,%s\n", imm8, nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += 1+alen;
+ DIP("shufps $%d,%s,%s\n", imm8, dis_buf, nameXMMReg(rG));
+ }
+ IRTemp res = math_SHUFPS_128( sV, dV, imm8 );
+ putXMMReg( gregOfRexRM(pfx,modrm), mkexpr(res) );
+ goto decode_success;
+ }
+ /* 66 0F C6 /r ib = SHUFPD -- shuffle packed F64s */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ Int select;
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+
+ modrm = getUChar(delta);
+ assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
+ select = (Int)getUChar(delta+1);
+ delta += 1+1;
+ DIP("shufpd $%d,%s,%s\n", select,
+ nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ select = getUChar(delta+alen);
+ delta += 1+alen;
+ DIP("shufpd $%d,%s,%s\n", select,
+ dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+
+ IRTemp res = math_SHUFPD_128( sV, dV, select );
+ putXMMReg( gregOfRexRM(pfx,modrm), mkexpr(res) );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD1:
+ /* 66 0F D1 = PSRLW by E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_shiftG_byE( vbi, pfx, delta, "psrlw", Iop_ShrN16x8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD2:
+ /* 66 0F D2 = PSRLD by E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_shiftG_byE( vbi, pfx, delta, "psrld", Iop_ShrN32x4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD3:
+ /* 66 0F D3 = PSRLQ by E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_shiftG_byE( vbi, pfx, delta, "psrlq", Iop_ShrN64x2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD4:
+ /* 66 0F D4 = PADDQ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "paddq", Iop_Add64x2, False );
+ goto decode_success;
+ }
+ /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
+ /* 0F D4 = PADDQ -- add 64x1 */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "paddq", False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD5:
+ /* 66 0F D5 = PMULLW -- 16x8 multiply */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pmullw", Iop_Mul16x8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD6:
+ /* F3 0F D6 = MOVQ2DQ -- move from E (mmx) to G (lo half xmm, zero
+ hi half). */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ do_MMX_preamble();
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ unop(Iop_64UtoV128, getMMXReg( eregLO3ofRM(modrm) )) );
+ DIP("movq2dq %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
- DIP("h%sps %s,%s\n", str, dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
+ delta += 1;
+ goto decode_success;
+ }
+ /* apparently no mem case for this insn */
}
-
- assign( gV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- breakup128to32s( eV, &e3, &e2, &e1, &e0 );
- breakup128to32s( gV, &g3, &g2, &g1, &g0 );
-
- assign( leftV, mk128from32s( e2, e0, g2, g0 ) );
- assign( rightV, mk128from32s( e3, e1, g3, g1 ) );
-
- putXMMReg( gregOfRexRM(pfx,modrm),
- binop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4,
- mkexpr(leftV), mkexpr(rightV) ) );
- goto decode_success;
- }
-
- /* 66 0F 7D = HSUBPD -- 64x2 sub across from E (mem or xmm) to G (xmm). */
- /* 66 0F 7C = HADDPD -- 64x2 add across from E (mem or xmm) to G (xmm). */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && (insn[1] == 0x7C || insn[1] == 0x7D)) {
- IRTemp e1 = newTemp(Ity_I64);
- IRTemp e0 = newTemp(Ity_I64);
- IRTemp g1 = newTemp(Ity_I64);
- IRTemp g0 = newTemp(Ity_I64);
- IRTemp eV = newTemp(Ity_V128);
- IRTemp gV = newTemp(Ity_V128);
- IRTemp leftV = newTemp(Ity_V128);
- IRTemp rightV = newTemp(Ity_V128);
- Bool isAdd = insn[1] == 0x7C;
- HChar* str = isAdd ? "add" : "sub";
-
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign( eV, getXMMReg( eregOfRexRM(pfx,modrm)) );
- DIP("h%spd %s,%s\n", str, nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
- DIP("h%spd %s,%s\n", str, dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
+ /* 66 0F D6 = MOVQ -- move 64 bits from G (lo half xmm) to E (mem
+ or lo half xmm). */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ /* fall through, awaiting test case */
+ /* dst: lo half copied, hi half zeroed */
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr),
+ getXMMRegLane64( gregOfRexRM(pfx,modrm), 0 ));
+ DIP("movq %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)), dis_buf );
+ delta += alen;
+ goto decode_success;
+ }
}
-
- assign( gV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- assign( e1, unop(Iop_V128HIto64, mkexpr(eV) ));
- assign( e0, unop(Iop_V128to64, mkexpr(eV) ));
- assign( g1, unop(Iop_V128HIto64, mkexpr(gV) ));
- assign( g0, unop(Iop_V128to64, mkexpr(gV) ));
-
- assign( leftV, binop(Iop_64HLtoV128, mkexpr(e0),mkexpr(g0)) );
- assign( rightV, binop(Iop_64HLtoV128, mkexpr(e1),mkexpr(g1)) );
-
- putXMMReg( gregOfRexRM(pfx,modrm),
- binop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2,
- mkexpr(leftV), mkexpr(rightV) ) );
- goto decode_success;
- }
-
- /* F2 0F F0 = LDDQU -- move from E (mem or xmm) to G (xmm). */
- if (haveF2no66noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0xF0) {
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- goto decode_failure;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
- putXMMReg( gregOfRexRM(pfx,modrm),
- loadLE(Ity_V128, mkexpr(addr)) );
- DIP("lddqu %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 2+alen;
- }
- goto decode_success;
- }
-
- /* ---------------------------------------------------- */
- /* --- end of the SSE3 decoder. --- */
- /* ---------------------------------------------------- */
-
- /* ---------------------------------------------------- */
- /* --- start of the SSSE3 decoder. --- */
- /* ---------------------------------------------------- */
-
- /* 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and
- Unsigned Bytes (MMX) */
- if (haveNo66noF2noF3(pfx)
- && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x04) {
- IRTemp sV = newTemp(Ity_I64);
- IRTemp dV = newTemp(Ity_I64);
- IRTemp sVoddsSX = newTemp(Ity_I64);
- IRTemp sVevensSX = newTemp(Ity_I64);
- IRTemp dVoddsZX = newTemp(Ity_I64);
- IRTemp dVevensZX = newTemp(Ity_I64);
-
- modrm = insn[3];
- do_MMX_preamble();
- assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
- delta += 3+1;
- DIP("pmaddubsw %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 3+alen;
- DIP("pmaddubsw %s,%s\n", dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
-
- /* compute dV unsigned x sV signed */
- assign( sVoddsSX,
- binop(Iop_SarN16x4, mkexpr(sV), mkU8(8)) );
- assign( sVevensSX,
- binop(Iop_SarN16x4,
- binop(Iop_ShlN16x4, mkexpr(sV), mkU8(8)),
- mkU8(8)) );
- assign( dVoddsZX,
- binop(Iop_ShrN16x4, mkexpr(dV), mkU8(8)) );
- assign( dVevensZX,
- binop(Iop_ShrN16x4,
- binop(Iop_ShlN16x4, mkexpr(dV), mkU8(8)),
- mkU8(8)) );
-
- putMMXReg(
- gregLO3ofRM(modrm),
- binop(Iop_QAdd16Sx4,
- binop(Iop_Mul16x4, mkexpr(sVoddsSX), mkexpr(dVoddsZX)),
- binop(Iop_Mul16x4, mkexpr(sVevensSX), mkexpr(dVevensZX))
- )
- );
- goto decode_success;
- }
-
- /* 66 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and
- Unsigned Bytes (XMM) */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /*redundant REX.W*/ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x04) {
- IRTemp sV = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp sVoddsSX = newTemp(Ity_V128);
- IRTemp sVevensSX = newTemp(Ity_V128);
- IRTemp dVoddsZX = newTemp(Ity_V128);
- IRTemp dVevensZX = newTemp(Ity_V128);
-
- modrm = insn[3];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 3+1;
- DIP("pmaddubsw %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 3+alen;
- DIP("pmaddubsw %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- /* compute dV unsigned x sV signed */
- assign( sVoddsSX,
- binop(Iop_SarN16x8, mkexpr(sV), mkU8(8)) );
- assign( sVevensSX,
- binop(Iop_SarN16x8,
- binop(Iop_ShlN16x8, mkexpr(sV), mkU8(8)),
- mkU8(8)) );
- assign( dVoddsZX,
- binop(Iop_ShrN16x8, mkexpr(dV), mkU8(8)) );
- assign( dVevensZX,
- binop(Iop_ShrN16x8,
- binop(Iop_ShlN16x8, mkexpr(dV), mkU8(8)),
- mkU8(8)) );
-
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- binop(Iop_QAdd16Sx8,
- binop(Iop_Mul16x8, mkexpr(sVoddsSX), mkexpr(dVoddsZX)),
- binop(Iop_Mul16x8, mkexpr(sVevensSX), mkexpr(dVevensZX))
- )
- );
- goto decode_success;
- }
-
- /* ***--- these are MMX class insns introduced in SSSE3 ---*** */
- /* 0F 38 03 = PHADDSW -- 16x4 signed qadd across from E (mem or
- mmx) and G to G (mmx). */
- /* 0F 38 07 = PHSUBSW -- 16x4 signed qsub across from E (mem or
- mmx) and G to G (mmx). */
- /* 0F 38 01 = PHADDW -- 16x4 add across from E (mem or mmx) and G
- to G (mmx). */
- /* 0F 38 05 = PHSUBW -- 16x4 sub across from E (mem or mmx) and G
- to G (mmx). */
- /* 0F 38 02 = PHADDD -- 32x2 add across from E (mem or mmx) and G
- to G (mmx). */
- /* 0F 38 06 = PHSUBD -- 32x2 sub across from E (mem or mmx) and G
- to G (mmx). */
-
- if (haveNo66noF2noF3(pfx)
- && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01
- || insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) {
- HChar* str = "???";
- IROp opV64 = Iop_INVALID;
- IROp opCatO = Iop_CatOddLanes16x4;
- IROp opCatE = Iop_CatEvenLanes16x4;
- IRTemp sV = newTemp(Ity_I64);
- IRTemp dV = newTemp(Ity_I64);
-
- modrm = insn[3];
-
- switch (insn[2]) {
- case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break;
- case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break;
- case 0x01: opV64 = Iop_Add16x4; str = "addw"; break;
- case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break;
- case 0x02: opV64 = Iop_Add32x2; str = "addd"; break;
- case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break;
- default: vassert(0);
- }
- if (insn[2] == 0x02 || insn[2] == 0x06) {
- opCatO = Iop_InterleaveHI32x2;
- opCatE = Iop_InterleaveLO32x2;
- }
-
- do_MMX_preamble();
- assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
- delta += 3+1;
- DIP("ph%s %s,%s\n", str, nameMMXReg(eregLO3ofRM(modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 3+alen;
- DIP("ph%s %s,%s\n", str, dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
-
- putMMXReg(
- gregLO3ofRM(modrm),
- binop(opV64,
- binop(opCatE,mkexpr(sV),mkexpr(dV)),
- binop(opCatO,mkexpr(sV),mkexpr(dV))
- )
- );
- goto decode_success;
- }
-
- /* 66 0F 38 03 = PHADDSW -- 16x8 signed qadd across from E (mem or
- xmm) and G to G (xmm). */
- /* 66 0F 38 07 = PHSUBSW -- 16x8 signed qsub across from E (mem or
- xmm) and G to G (xmm). */
- /* 66 0F 38 01 = PHADDW -- 16x8 add across from E (mem or xmm) and
- G to G (xmm). */
- /* 66 0F 38 05 = PHSUBW -- 16x8 sub across from E (mem or xmm) and
- G to G (xmm). */
- /* 66 0F 38 02 = PHADDD -- 32x4 add across from E (mem or xmm) and
- G to G (xmm). */
- /* 66 0F 38 06 = PHSUBD -- 32x4 sub across from E (mem or xmm) and
- G to G (xmm). */
-
- if (have66noF2noF3(pfx)
- && (sz == 2 || /*redundant REX.W*/ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01
- || insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) {
- HChar* str = "???";
- IROp opV64 = Iop_INVALID;
- IROp opCatO = Iop_CatOddLanes16x4;
- IROp opCatE = Iop_CatEvenLanes16x4;
- IRTemp sV = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp sHi = newTemp(Ity_I64);
- IRTemp sLo = newTemp(Ity_I64);
- IRTemp dHi = newTemp(Ity_I64);
- IRTemp dLo = newTemp(Ity_I64);
-
- modrm = insn[3];
-
- switch (insn[2]) {
- case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break;
- case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break;
- case 0x01: opV64 = Iop_Add16x4; str = "addw"; break;
- case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break;
- case 0x02: opV64 = Iop_Add32x2; str = "addd"; break;
- case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break;
- default: vassert(0);
- }
- if (insn[2] == 0x02 || insn[2] == 0x06) {
- opCatO = Iop_InterleaveHI32x2;
- opCatE = Iop_InterleaveLO32x2;
- }
-
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg( eregOfRexRM(pfx,modrm)) );
- DIP("ph%s %s,%s\n", str, nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 3+1;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- DIP("ph%s %s,%s\n", str, dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- delta += 3+alen;
- }
-
- assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
- assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
- assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
-
- /* This isn't a particularly efficient way to compute the
- result, but at least it avoids a proliferation of IROps,
- hence avoids complication all the backends. */
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128,
- binop(opV64,
- binop(opCatE,mkexpr(sHi),mkexpr(sLo)),
- binop(opCatO,mkexpr(sHi),mkexpr(sLo))
- ),
- binop(opV64,
- binop(opCatE,mkexpr(dHi),mkexpr(dLo)),
- binop(opCatO,mkexpr(dHi),mkexpr(dLo))
- )
- )
- );
- goto decode_success;
- }
-
- /* 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and Scale
- (MMX) */
- if (haveNo66noF2noF3(pfx)
- && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x0B) {
- IRTemp sV = newTemp(Ity_I64);
- IRTemp dV = newTemp(Ity_I64);
-
- modrm = insn[3];
- do_MMX_preamble();
- assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
- delta += 3+1;
- DIP("pmulhrsw %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 3+alen;
- DIP("pmulhrsw %s,%s\n", dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
-
- putMMXReg(
- gregLO3ofRM(modrm),
- dis_PMULHRSW_helper( mkexpr(sV), mkexpr(dV) )
- );
- goto decode_success;
- }
-
- /* 66 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and
- Scale (XMM) */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /*redundant REX.W*/ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x0B) {
- IRTemp sV = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp sHi = newTemp(Ity_I64);
- IRTemp sLo = newTemp(Ity_I64);
- IRTemp dHi = newTemp(Ity_I64);
- IRTemp dLo = newTemp(Ity_I64);
-
- modrm = insn[3];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 3+1;
- DIP("pmulhrsw %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 3+alen;
- DIP("pmulhrsw %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
- assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
- assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
-
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128,
- dis_PMULHRSW_helper( mkexpr(sHi), mkexpr(dHi) ),
- dis_PMULHRSW_helper( mkexpr(sLo), mkexpr(dLo) )
- )
- );
- goto decode_success;
- }
-
- /* 0F 38 08 = PSIGNB -- Packed Sign 8x8 (MMX) */
- /* 0F 38 09 = PSIGNW -- Packed Sign 16x4 (MMX) */
- /* 0F 38 09 = PSIGND -- Packed Sign 32x2 (MMX) */
- if (haveNo66noF2noF3(pfx)
- && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x08 || insn[2] == 0x09 || insn[2] == 0x0A)) {
- IRTemp sV = newTemp(Ity_I64);
- IRTemp dV = newTemp(Ity_I64);
- HChar* str = "???";
- Int laneszB = 0;
-
- switch (insn[2]) {
- case 0x08: laneszB = 1; str = "b"; break;
- case 0x09: laneszB = 2; str = "w"; break;
- case 0x0A: laneszB = 4; str = "d"; break;
- default: vassert(0);
- }
-
- modrm = insn[3];
- do_MMX_preamble();
- assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
- delta += 3+1;
- DIP("psign%s %s,%s\n", str, nameMMXReg(eregLO3ofRM(modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 3+alen;
- DIP("psign%s %s,%s\n", str, dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
-
- putMMXReg(
- gregLO3ofRM(modrm),
- dis_PSIGN_helper( mkexpr(sV), mkexpr(dV), laneszB )
- );
- goto decode_success;
- }
-
- /* 66 0F 38 08 = PSIGNB -- Packed Sign 8x16 (XMM) */
- /* 66 0F 38 09 = PSIGNW -- Packed Sign 16x8 (XMM) */
- /* 66 0F 38 09 = PSIGND -- Packed Sign 32x4 (XMM) */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /*redundant REX.W*/ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x08 || insn[2] == 0x09 || insn[2] == 0x0A)) {
- IRTemp sV = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp sHi = newTemp(Ity_I64);
- IRTemp sLo = newTemp(Ity_I64);
- IRTemp dHi = newTemp(Ity_I64);
- IRTemp dLo = newTemp(Ity_I64);
- HChar* str = "???";
- Int laneszB = 0;
-
- switch (insn[2]) {
- case 0x08: laneszB = 1; str = "b"; break;
- case 0x09: laneszB = 2; str = "w"; break;
- case 0x0A: laneszB = 4; str = "d"; break;
- default: vassert(0);
- }
-
- modrm = insn[3];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 3+1;
- DIP("psign%s %s,%s\n", str, nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 3+alen;
- DIP("psign%s %s,%s\n", str, dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
- assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
- assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
-
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128,
- dis_PSIGN_helper( mkexpr(sHi), mkexpr(dHi), laneszB ),
- dis_PSIGN_helper( mkexpr(sLo), mkexpr(dLo), laneszB )
- )
- );
- goto decode_success;
- }
-
- /* 0F 38 1C = PABSB -- Packed Absolute Value 8x8 (MMX) */
- /* 0F 38 1D = PABSW -- Packed Absolute Value 16x4 (MMX) */
- /* 0F 38 1E = PABSD -- Packed Absolute Value 32x2 (MMX) */
- if (haveNo66noF2noF3(pfx)
- && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x1C || insn[2] == 0x1D || insn[2] == 0x1E)) {
- IRTemp sV = newTemp(Ity_I64);
- HChar* str = "???";
- Int laneszB = 0;
-
- switch (insn[2]) {
- case 0x1C: laneszB = 1; str = "b"; break;
- case 0x1D: laneszB = 2; str = "w"; break;
- case 0x1E: laneszB = 4; str = "d"; break;
- default: vassert(0);
- }
-
- modrm = insn[3];
- do_MMX_preamble();
-
- if (epartIsReg(modrm)) {
- assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
- delta += 3+1;
- DIP("pabs%s %s,%s\n", str, nameMMXReg(eregLO3ofRM(modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 3+alen;
- DIP("pabs%s %s,%s\n", str, dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
-
- putMMXReg(
- gregLO3ofRM(modrm),
- dis_PABS_helper( mkexpr(sV), laneszB )
- );
- goto decode_success;
- }
-
- /* 66 0F 38 1C = PABSB -- Packed Absolute Value 8x16 (XMM) */
- /* 66 0F 38 1D = PABSW -- Packed Absolute Value 16x8 (XMM) */
- /* 66 0F 38 1E = PABSD -- Packed Absolute Value 32x4 (XMM) */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /*redundant REX.W*/ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x1C || insn[2] == 0x1D || insn[2] == 0x1E)) {
- IRTemp sV = newTemp(Ity_V128);
- IRTemp sHi = newTemp(Ity_I64);
- IRTemp sLo = newTemp(Ity_I64);
- HChar* str = "???";
- Int laneszB = 0;
-
- switch (insn[2]) {
- case 0x1C: laneszB = 1; str = "b"; break;
- case 0x1D: laneszB = 2; str = "w"; break;
- case 0x1E: laneszB = 4; str = "d"; break;
- default: vassert(0);
- }
-
- modrm = insn[3];
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 3+1;
- DIP("pabs%s %s,%s\n", str, nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 3+alen;
- DIP("pabs%s %s,%s\n", str, dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
-
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128,
- dis_PABS_helper( mkexpr(sHi), laneszB ),
- dis_PABS_helper( mkexpr(sLo), laneszB )
- )
- );
- goto decode_success;
- }
-
- /* 0F 3A 0F = PALIGNR -- Packed Align Right (MMX) */
- if (haveNo66noF2noF3(pfx) && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0F) {
- IRTemp sV = newTemp(Ity_I64);
- IRTemp dV = newTemp(Ity_I64);
- IRTemp res = newTemp(Ity_I64);
-
- modrm = insn[3];
- do_MMX_preamble();
- assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
- d64 = (Long)insn[3+1];
- delta += 3+1+1;
- DIP("palignr $%d,%s,%s\n", (Int)d64,
- nameMMXReg(eregLO3ofRM(modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 1 );
- assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
- d64 = (Long)insn[3+alen];
- delta += 3+alen+1;
- DIP("palignr $%d%s,%s\n", (Int)d64,
- dis_buf,
+ /* F2 0F D6 = MOVDQ2Q -- move from E (lo half xmm, not mem) to G (mmx). */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ do_MMX_preamble();
+ putMMXReg( gregLO3ofRM(modrm),
+ getXMMRegLane64( eregOfRexRM(pfx,modrm), 0 ));
+ DIP("movdq2q %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
nameMMXReg(gregLO3ofRM(modrm)));
+ delta += 1;
+ goto decode_success;
+ }
+ /* apparently no mem case for this insn */
}
+ break;
- if (d64 == 0) {
- assign( res, mkexpr(sV) );
+ case 0xD7:
+ /* 66 0F D7 = PMOVMSKB -- extract sign bits from each of 16
+ lanes in xmm(E), turn them into a byte, and put
+ zero-extend of it in ireg(G). Doing this directly is just
+ too cumbersome; give up therefore and call a helper. */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
+ && epartIsReg(getUChar(delta))) { /* no memory case, it seems */
+ delta = dis_PMOVMSKB_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
}
- else if (d64 >= 1 && d64 <= 7) {
- assign(res,
- binop(Iop_Or64,
- binop(Iop_Shr64, mkexpr(sV), mkU8(8*d64)),
- binop(Iop_Shl64, mkexpr(dV), mkU8(8*(8-d64))
- )));
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F D7 = PMOVMSKB -- extract sign bits from each of 8 lanes in
+ mmx(G), turn them into a byte, and put zero-extend of it in
+ ireg(G). */
+ if (haveNo66noF2noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ do_MMX_preamble();
+ t0 = newTemp(Ity_I64);
+ t1 = newTemp(Ity_I64);
+ assign(t0, getMMXReg(eregLO3ofRM(modrm)));
+ assign(t1, mkIRExprCCall(
+ Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_mmx_pmovmskb",
+ &amd64g_calculate_mmx_pmovmskb,
+ mkIRExprVec_1(mkexpr(t0))));
+ putIReg32(gregOfRexRM(pfx,modrm), unop(Iop_64to32,mkexpr(t1)));
+ DIP("pmovmskb %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
+ nameIReg32(gregOfRexRM(pfx,modrm)));
+ delta += 1;
+ goto decode_success;
+ }
+ /* else fall through */
}
- else if (d64 == 8) {
- assign( res, mkexpr(dV) );
- }
- else if (d64 >= 9 && d64 <= 15) {
- assign( res, binop(Iop_Shr64, mkexpr(dV), mkU8(8*(d64-8))) );
- }
- else if (d64 >= 16 && d64 <= 255) {
- assign( res, mkU64(0) );
- }
- else
- vassert(0);
+ break;
- putMMXReg( gregLO3ofRM(modrm), mkexpr(res) );
- goto decode_success;
+ case 0xD8:
+ /* 66 0F D8 = PSUBUSB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "psubusb", Iop_QSub8Ux16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD9:
+ /* 66 0F D9 = PSUBUSW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "psubusw", Iop_QSub16Ux8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDA:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F DA = PMINUB -- 8x8 unsigned min */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "pminub", False );
+ goto decode_success;
+ }
+ /* 66 0F DA = PMINUB -- 8x16 unsigned min */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pminub", Iop_Min8Ux16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDB:
+ /* 66 0F DB = PAND */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "pand", Iop_AndV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDC:
+ /* 66 0F DC = PADDUSB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "paddusb", Iop_QAdd8Ux16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDD:
+ /* 66 0F DD = PADDUSW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "paddusw", Iop_QAdd16Ux8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDE:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F DE = PMAXUB -- 8x8 unsigned max */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "pmaxub", False );
+ goto decode_success;
+ }
+ /* 66 0F DE = PMAXUB -- 8x16 unsigned max */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pmaxub", Iop_Max8Ux16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDF:
+ /* 66 0F DF = PANDN */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all_invG( vbi, pfx, delta, "pandn", Iop_AndV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE0:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "pavgb", False );
+ goto decode_success;
+ }
+ /* 66 0F E0 = PAVGB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pavgb", Iop_Avg8Ux16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE1:
+ /* 66 0F E1 = PSRAW by E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_shiftG_byE( vbi, pfx, delta, "psraw", Iop_SarN16x8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE2:
+ /* 66 0F E2 = PSRAD by E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_shiftG_byE( vbi, pfx, delta, "psrad", Iop_SarN32x4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE3:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "pavgw", False );
+ goto decode_success;
+ }
+ /* 66 0F E3 = PAVGW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pavgw", Iop_Avg16Ux8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE4:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F E4 = PMULUH -- 16x4 hi-half of unsigned widening multiply */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "pmuluh", False );
+ goto decode_success;
+ }
+ /* 66 0F E4 = PMULHUW -- 16x8 hi-half of unsigned widening multiply */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pmulhuw", Iop_MulHi16Ux8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE5:
+ /* 66 0F E5 = PMULHW -- 16x8 hi-half of signed widening multiply */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pmulhw", Iop_MulHi16Sx8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE6:
+ /* 66 0F E6 = CVTTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I32 in
+ lo half xmm(G), and zero upper half, rounding towards zero */
+ /* F2 0F E6 = CVTPD2DQ -- convert 2 x F64 in mem/xmm to 2 x I32 in
+ lo half xmm(G), according to prevailing rounding mode, and zero
+ upper half */
+ if ( (haveF2no66noF3(pfx) && sz == 4)
+ || (have66noF2noF3(pfx) && sz == 2) ) {
+ delta = dis_CVTxPD2DQ_128( vbi, pfx, delta, False/*!isAvx*/,
+ toBool(sz == 2)/*r2zero*/);
+ goto decode_success;
+ }
+ /* F3 0F E6 = CVTDQ2PD -- convert 2 x I32 in mem/lo half xmm to 2 x
+ F64 in xmm(G) */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_CVTDQ2PD_128(vbi, pfx, delta, False/*!isAvx*/);
+ goto decode_success;
+ }
+ break;
+
+ case 0xE7:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F E7 = MOVNTQ -- for us, just a plain MMX store. Note, the
+ Intel manual does not say anything about the usual business of
+ the FP reg tags getting trashed whenever an MMX insn happens.
+ So we just leave them alone.
+ */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ modrm = getUChar(delta);
+ if (!epartIsReg(modrm)) {
+ /* do_MMX_preamble(); Intel docs don't specify this */
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getMMXReg(gregLO3ofRM(modrm)) );
+ DIP("movntq %s,%s\n", dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ delta += alen;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ /* 66 0F E7 = MOVNTDQ -- for us, just a plain SSE store. */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ modrm = getUChar(delta);
+ if (!epartIsReg(modrm)) {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
+ DIP("movntdq %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ break;
+
+ case 0xE8:
+ /* 66 0F E8 = PSUBSB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "psubsb", Iop_QSub8Sx16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE9:
+ /* 66 0F E9 = PSUBSW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "psubsw", Iop_QSub16Sx8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEA:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F EA = PMINSW -- 16x4 signed min */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "pminsw", False );
+ goto decode_success;
+ }
+ /* 66 0F EA = PMINSW -- 16x8 signed min */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pminsw", Iop_Min16Sx8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEB:
+ /* 66 0F EB = POR */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "por", Iop_OrV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEC:
+ /* 66 0F EC = PADDSB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "paddsb", Iop_QAdd8Sx16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xED:
+ /* 66 0F ED = PADDSW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "paddsw", Iop_QAdd16Sx8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEE:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F EE = PMAXSW -- 16x4 signed max */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "pmaxsw", False );
+ goto decode_success;
+ }
+ /* 66 0F EE = PMAXSW -- 16x8 signed max */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pmaxsw", Iop_Max16Sx8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEF:
+ /* 66 0F EF = PXOR */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_E_to_G_all( vbi, pfx, delta, "pxor", Iop_XorV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF1:
+ /* 66 0F F1 = PSLLW by E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_shiftG_byE( vbi, pfx, delta, "psllw", Iop_ShlN16x8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF2:
+ /* 66 0F F2 = PSLLD by E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_shiftG_byE( vbi, pfx, delta, "pslld", Iop_ShlN32x4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF3:
+ /* 66 0F F3 = PSLLQ by E */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSE_shiftG_byE( vbi, pfx, delta, "psllq", Iop_ShlN64x2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF4:
+ /* 66 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x
+ 0 to form lower 64-bit half and lanes 2 x 2 to form upper 64-bit
+ half */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ assign( dV, getXMMReg(rG) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("pmuludq %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("pmuludq %s,%s\n", dis_buf, nameXMMReg(rG));
+ }
+ putXMMReg( rG, mkexpr(math_PMULUDQ_128( sV, dV )) );
+ goto decode_success;
+ }
+ /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
+ /* 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x
+ 0 to form 64-bit result */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+ t1 = newTemp(Ity_I32);
+ t0 = newTemp(Ity_I32);
+ modrm = getUChar(delta);
+
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
+ delta += 1;
+ DIP("pmuludq %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("pmuludq %s,%s\n", dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+
+ assign( t0, unop(Iop_64to32, mkexpr(dV)) );
+ assign( t1, unop(Iop_64to32, mkexpr(sV)) );
+ putMMXReg( gregLO3ofRM(modrm),
+ binop( Iop_MullU32, mkexpr(t0), mkexpr(t1) ) );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF5:
+ /* 66 0F F5 = PMADDWD -- Multiply and add packed integers from
+ E(xmm or mem) to G(xmm) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("pmaddwd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("pmaddwd %s,%s\n", dis_buf, nameXMMReg(rG));
+ }
+ assign( dV, getXMMReg(rG) );
+ putXMMReg( rG, mkexpr(math_PMADDWD_128(dV, sV)) );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF6:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F F6 = PSADBW -- sum of 8Ux8 absolute differences */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "psadbw", False );
+ goto decode_success;
+ }
+ /* 66 0F F6 = PSADBW -- 2 x (8x8 -> 48 zeroes ++ u16) Sum Abs Diffs
+ from E(xmm or mem) to G(xmm) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("psadbw %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("psadbw %s,%s\n", dis_buf, nameXMMReg(rG));
+ }
+ assign( dV, getXMMReg(rG) );
+ putXMMReg( rG, mkexpr( math_PSADBW_128 ( dV, sV ) ) );
+
+ goto decode_success;
+ }
+ break;
+
+ case 0xF7:
+ /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
+ /* 0F F7 = MASKMOVQ -- 8x8 masked store */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ Bool ok = False;
+ delta = dis_MMX( &ok, vbi, pfx, sz, delta-1 );
+ if (ok) goto decode_success;
+ }
+ /* 66 0F F7 = MASKMOVDQU -- store selected bytes of double quadword */
+ if (have66noF2noF3(pfx) && sz == 2 && epartIsReg(getUChar(delta))) {
+ delta = dis_MASKMOVDQU( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF8:
+ /* 66 0F F8 = PSUBB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "psubb", Iop_Sub8x16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF9:
+ /* 66 0F F9 = PSUBW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "psubw", Iop_Sub16x8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFA:
+ /* 66 0F FA = PSUBD */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "psubd", Iop_Sub32x4, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFB:
+ /* 66 0F FB = PSUBQ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "psubq", Iop_Sub64x2, False );
+ goto decode_success;
+ }
+ /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
+ /* 0F FB = PSUBQ -- sub 64x1 */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ do_MMX_preamble();
+ delta = dis_MMXop_regmem_to_reg (
+ vbi, pfx, delta, opc, "psubq", False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFC:
+ /* 66 0F FC = PADDB */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "paddb", Iop_Add8x16, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFD:
+ /* 66 0F FD = PADDW */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "paddw", Iop_Add16x8, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFE:
+ /* 66 0F FE = PADDD */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "paddd", Iop_Add32x4, False );
+ goto decode_success;
+ }
+ break;
+
+ default:
+ goto decode_failure;
+
}
- /* 66 0F 3A 0F = PALIGNR -- Packed Align Right (XMM) */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /*redundant REX.W*/ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0F) {
- IRTemp sV = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp sHi = newTemp(Ity_I64);
- IRTemp sLo = newTemp(Ity_I64);
- IRTemp dHi = newTemp(Ity_I64);
- IRTemp dLo = newTemp(Ity_I64);
- IRTemp rHi = newTemp(Ity_I64);
- IRTemp rLo = newTemp(Ity_I64);
+ decode_failure:
+ *decode_OK = False;
+ return deltaIN;
- modrm = insn[3];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+ decode_success:
+ *decode_OK = True;
+ return delta;
+}
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- d64 = (Long)insn[3+1];
- delta += 3+1+1;
- DIP("palignr $%d,%s,%s\n", (Int)d64,
- nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 1 );
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level SSE3 (not SupSSE3): dis_ESC_0F__SSE3 ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+static Long dis_MOVDDUP_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp d0 = newTemp(Ity_I64);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ DIP("%smovddup %s,%s\n",
+ isAvx ? "v" : "", nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ assign ( d0, unop(Iop_V128to64, mkexpr(sV)) );
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( d0, loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("%smovddup %s,%s\n",
+ isAvx ? "v" : "", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)
+ ( rG, binop(Iop_64HLtoV128,mkexpr(d0),mkexpr(d0)) );
+ return delta;
+}
+
+
+static Long dis_MOVDDUP_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp d0 = newTemp(Ity_I64);
+ IRTemp d1 = newTemp(Ity_I64);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ DIP("vmovddup %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
+ delta += 1;
+ assign ( d0, getYMMRegLane64(rE, 0) );
+ assign ( d1, getYMMRegLane64(rE, 2) );
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( d0, loadLE(Ity_I64, mkexpr(addr)) );
+ assign( d1, loadLE(Ity_I64, binop(Iop_Add64,
+ mkexpr(addr), mkU64(16))) );
+ DIP("vmovddup %s,%s\n", dis_buf, nameYMMReg(rG));
+ delta += alen;
+ }
+ putYMMRegLane64( rG, 0, mkexpr(d0) );
+ putYMMRegLane64( rG, 1, mkexpr(d0) );
+ putYMMRegLane64( rG, 2, mkexpr(d1) );
+ putYMMRegLane64( rG, 3, mkexpr(d1) );
+ return delta;
+}
+
+
+static Long dis_MOVSxDUP_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, Bool isL )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp sV = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ DIP("%smovs%cdup %s,%s\n",
+ isAvx ? "v" : "", isL ? 'l' : 'h', nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ if (!isAvx)
gen_SEGV_if_not_16_aligned( addr );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- d64 = (Long)insn[3+alen];
- delta += 3+alen+1;
- DIP("palignr $%d,%s,%s\n", (Int)d64,
- dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("%smovs%cdup %s,%s\n",
+ isAvx ? "v" : "", isL ? 'l' : 'h', dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)
+ ( rG, isL ? mkV128from32s( s2, s2, s0, s0 )
+ : mkV128from32s( s3, s3, s1, s1 ) );
+ return delta;
+}
- assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
- assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
- assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
- if (d64 == 0) {
- assign( rHi, mkexpr(sHi) );
- assign( rLo, mkexpr(sLo) );
- }
- else if (d64 >= 1 && d64 <= 7) {
- assign( rHi, dis_PALIGNR_XMM_helper(dLo, sHi, d64) );
- assign( rLo, dis_PALIGNR_XMM_helper(sHi, sLo, d64) );
- }
- else if (d64 == 8) {
- assign( rHi, mkexpr(dLo) );
- assign( rLo, mkexpr(sHi) );
- }
- else if (d64 >= 9 && d64 <= 15) {
- assign( rHi, dis_PALIGNR_XMM_helper(dHi, dLo, d64-8) );
- assign( rLo, dis_PALIGNR_XMM_helper(dLo, sHi, d64-8) );
- }
- else if (d64 == 16) {
- assign( rHi, mkexpr(dHi) );
- assign( rLo, mkexpr(dLo) );
- }
- else if (d64 >= 17 && d64 <= 23) {
- assign( rHi, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(d64-16))) );
- assign( rLo, dis_PALIGNR_XMM_helper(dHi, dLo, d64-16) );
- }
- else if (d64 == 24) {
- assign( rHi, mkU64(0) );
- assign( rLo, mkexpr(dHi) );
- }
- else if (d64 >= 25 && d64 <= 31) {
- assign( rHi, mkU64(0) );
- assign( rLo, binop(Iop_Shr64, mkexpr(dHi), mkU8(8*(d64-24))) );
- }
- else if (d64 >= 32 && d64 <= 255) {
- assign( rHi, mkU64(0) );
- assign( rLo, mkU64(0) );
- }
- else
- vassert(0);
+static Long dis_MOVSxDUP_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isL )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp sV = newTemp(Ity_V256);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp s7, s6, s5, s4, s3, s2, s1, s0;
+ s7 = s6 = s5 = s4 = s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getYMMReg(rE) );
+ DIP("vmovs%cdup %s,%s\n",
+ isL ? 'l' : 'h', nameYMMReg(rE), nameYMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
+ DIP("vmovs%cdup %s,%s\n",
+ isL ? 'l' : 'h', dis_buf, nameYMMReg(rG));
+ delta += alen;
+ }
+ breakupV256to32s( sV, &s7, &s6, &s5, &s4, &s3, &s2, &s1, &s0 );
+ putYMMRegLane128( rG, 1, isL ? mkV128from32s( s6, s6, s4, s4 )
+ : mkV128from32s( s7, s7, s5, s5 ) );
+ putYMMRegLane128( rG, 0, isL ? mkV128from32s( s2, s2, s0, s0 )
+ : mkV128from32s( s3, s3, s1, s1 ) );
+ return delta;
+}
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo))
- );
- goto decode_success;
+
+static IRTemp math_HADDPS_128 ( IRTemp dV, IRTemp sV, Bool isAdd )
+{
+ IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
+ IRTemp leftV = newTemp(Ity_V128);
+ IRTemp rightV = newTemp(Ity_V128);
+ s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
+
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+ breakupV128to32s( dV, &d3, &d2, &d1, &d0 );
+
+ assign( leftV, mkV128from32s( s2, s0, d2, d0 ) );
+ assign( rightV, mkV128from32s( s3, s1, d3, d1 ) );
+
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4,
+ mkexpr(leftV), mkexpr(rightV) ) );
+ return res;
+}
+
+
+static IRTemp math_HADDPD_128 ( IRTemp dV, IRTemp sV, Bool isAdd )
+{
+ IRTemp s1, s0, d1, d0;
+ IRTemp leftV = newTemp(Ity_V128);
+ IRTemp rightV = newTemp(Ity_V128);
+ s1 = s0 = d1 = d0 = IRTemp_INVALID;
+
+ breakupV128to64s( sV, &s1, &s0 );
+ breakupV128to64s( dV, &d1, &d0 );
+
+ assign( leftV, binop(Iop_64HLtoV128, mkexpr(s0), mkexpr(d0)) );
+ assign( rightV, binop(Iop_64HLtoV128, mkexpr(s1), mkexpr(d1)) );
+
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2,
+ mkexpr(leftV), mkexpr(rightV) ) );
+ return res;
+}
+
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F__SSE3 ( Bool* decode_OK,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN )
+{
+ IRTemp addr = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
+
+ *decode_OK = False;
+
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) {
+
+ case 0x12:
+ /* F3 0F 12 = MOVSLDUP -- move from E (mem or xmm) to G (xmm),
+ duplicating some lanes (2:2:0:0). */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_MOVSxDUP_128( vbi, pfx, delta, False/*!isAvx*/,
+ True/*isL*/ );
+ goto decode_success;
+ }
+ /* F2 0F 12 = MOVDDUP -- move from E (mem or xmm) to G (xmm),
+ duplicating some lanes (0:1:0:1). */
+ if (haveF2no66noF3(pfx)
+ && (sz == 4 || /* ignore redundant REX.W */ sz == 8)) {
+ delta = dis_MOVDDUP_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x16:
+ /* F3 0F 16 = MOVSHDUP -- move from E (mem or xmm) to G (xmm),
+ duplicating some lanes (3:3:1:1). */
+ if (haveF3no66noF2(pfx) && sz == 4) {
+ delta = dis_MOVSxDUP_128( vbi, pfx, delta, False/*!isAvx*/,
+ False/*!isL*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x7C:
+ case 0x7D:
+ /* F2 0F 7C = HADDPS -- 32x4 add across from E (mem or xmm) to G (xmm). */
+ /* F2 0F 7D = HSUBPS -- 32x4 sub across from E (mem or xmm) to G (xmm). */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ IRTemp eV = newTemp(Ity_V128);
+ IRTemp gV = newTemp(Ity_V128);
+ Bool isAdd = opc == 0x7C;
+ HChar* str = isAdd ? "add" : "sub";
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getXMMReg(rE) );
+ DIP("h%sps %s,%s\n", str, nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("h%sps %s,%s\n", str, dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+
+ assign( gV, getXMMReg(rG) );
+ putXMMReg( rG, mkexpr( math_HADDPS_128 ( gV, eV, isAdd ) ) );
+ goto decode_success;
+ }
+ /* 66 0F 7C = HADDPD -- 64x2 add across from E (mem or xmm) to G (xmm). */
+ /* 66 0F 7D = HSUBPD -- 64x2 sub across from E (mem or xmm) to G (xmm). */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ IRTemp eV = newTemp(Ity_V128);
+ IRTemp gV = newTemp(Ity_V128);
+ Bool isAdd = opc == 0x7C;
+ HChar* str = isAdd ? "add" : "sub";
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getXMMReg(rE) );
+ DIP("h%spd %s,%s\n", str, nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("h%spd %s,%s\n", str, dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+
+ assign( gV, getXMMReg(rG) );
+ putXMMReg( rG, mkexpr( math_HADDPD_128 ( gV, eV, isAdd ) ) );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD0:
+ /* 66 0F D0 = ADDSUBPD -- 64x4 +/- from E (mem or xmm) to G (xmm). */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ IRTemp eV = newTemp(Ity_V128);
+ IRTemp gV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getXMMReg(rE) );
+ DIP("addsubpd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("addsubpd %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+
+ assign( gV, getXMMReg(rG) );
+ putXMMReg( rG, mkexpr( math_ADDSUBPD_128 ( gV, eV ) ) );
+ goto decode_success;
+ }
+ /* F2 0F D0 = ADDSUBPS -- 32x4 +/-/+/- from E (mem or xmm) to G (xmm). */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ IRTemp eV = newTemp(Ity_V128);
+ IRTemp gV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getXMMReg(rE) );
+ DIP("addsubps %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("addsubps %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+
+ assign( gV, getXMMReg(rG) );
+ putXMMReg( rG, mkexpr( math_ADDSUBPS_128 ( gV, eV ) ) );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF0:
+ /* F2 0F F0 = LDDQU -- move from E (mem or xmm) to G (xmm). */
+ if (haveF2no66noF3(pfx) && sz == 4) {
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ goto decode_failure;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("lddqu %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ break;
+
+ default:
+ goto decode_failure;
+
}
- /* 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x8 (MMX) */
- if (haveNo66noF2noF3(pfx)
- && sz == 4
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x00) {
- IRTemp sV = newTemp(Ity_I64);
- IRTemp dV = newTemp(Ity_I64);
+ decode_failure:
+ *decode_OK = False;
+ return deltaIN;
- modrm = insn[3];
- do_MMX_preamble();
- assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
+ decode_success:
+ *decode_OK = True;
+ return delta;
+}
- if (epartIsReg(modrm)) {
- assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
- delta += 3+1;
- DIP("pshufb %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
- nameMMXReg(gregLO3ofRM(modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
- delta += 3+alen;
- DIP("pshufb %s,%s\n", dis_buf,
- nameMMXReg(gregLO3ofRM(modrm)));
- }
- putMMXReg(
- gregLO3ofRM(modrm),
- binop(
- Iop_And64,
- /* permute the lanes */
- binop(
- Iop_Perm8x8,
- mkexpr(dV),
- binop(Iop_And64, mkexpr(sV), mkU64(0x0707070707070707ULL))
- ),
- /* mask off lanes which have (index & 0x80) == 0x80 */
- unop(Iop_Not64, binop(Iop_SarN8x8, mkexpr(sV), mkU8(7)))
- )
- );
- goto decode_success;
- }
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level SSSE3: dis_ESC_0F38__SupSSE3 ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
- /* 66 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x16 (XMM) */
- if (have66noF2noF3(pfx)
- && (sz == 2 || /*redundant REX.W*/ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x00) {
- IRTemp sV = newTemp(Ity_V128);
- IRTemp dV = newTemp(Ity_V128);
- IRTemp sHi = newTemp(Ity_I64);
- IRTemp sLo = newTemp(Ity_I64);
- IRTemp dHi = newTemp(Ity_I64);
- IRTemp dLo = newTemp(Ity_I64);
- IRTemp rHi = newTemp(Ity_I64);
- IRTemp rLo = newTemp(Ity_I64);
- IRTemp sevens = newTemp(Ity_I64);
- IRTemp mask0x80hi = newTemp(Ity_I64);
- IRTemp mask0x80lo = newTemp(Ity_I64);
- IRTemp maskBit3hi = newTemp(Ity_I64);
- IRTemp maskBit3lo = newTemp(Ity_I64);
- IRTemp sAnd7hi = newTemp(Ity_I64);
- IRTemp sAnd7lo = newTemp(Ity_I64);
- IRTemp permdHi = newTemp(Ity_I64);
- IRTemp permdLo = newTemp(Ity_I64);
+static
+IRTemp math_PSHUFB_XMM ( IRTemp dV/*data to perm*/, IRTemp sV/*perm*/ )
+{
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ IRTemp rHi = newTemp(Ity_I64);
+ IRTemp rLo = newTemp(Ity_I64);
+ IRTemp sevens = newTemp(Ity_I64);
+ IRTemp mask0x80hi = newTemp(Ity_I64);
+ IRTemp mask0x80lo = newTemp(Ity_I64);
+ IRTemp maskBit3hi = newTemp(Ity_I64);
+ IRTemp maskBit3lo = newTemp(Ity_I64);
+ IRTemp sAnd7hi = newTemp(Ity_I64);
+ IRTemp sAnd7lo = newTemp(Ity_I64);
+ IRTemp permdHi = newTemp(Ity_I64);
+ IRTemp permdLo = newTemp(Ity_I64);
+ IRTemp res = newTemp(Ity_V128);
- modrm = insn[3];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 3+1;
- DIP("pshufb %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 3+alen;
- DIP("pshufb %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
+ assign( sevens, mkU64(0x0707070707070707ULL) );
- assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
- assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
- assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
- assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
-
- assign( sevens, mkU64(0x0707070707070707ULL) );
-
- /*
- mask0x80hi = Not(SarN8x8(sHi,7))
+ /* mask0x80hi = Not(SarN8x8(sHi,7))
maskBit3hi = SarN8x8(ShlN8x8(sHi,4),7)
sAnd7hi = And(sHi,sevens)
permdHi = Or( And(Perm8x8(dHi,sAnd7hi),maskBit3hi),
- And(Perm8x8(dLo,sAnd7hi),Not(maskBit3hi)) )
+ And(Perm8x8(dLo,sAnd7hi),Not(maskBit3hi)) )
rHi = And(permdHi,mask0x80hi)
- */
- assign(
- mask0x80hi,
- unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sHi),mkU8(7))));
+ */
+ assign(
+ mask0x80hi,
+ unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sHi),mkU8(7))));
- assign(
- maskBit3hi,
- binop(Iop_SarN8x8,
- binop(Iop_ShlN8x8,mkexpr(sHi),mkU8(4)),
- mkU8(7)));
+ assign(
+ maskBit3hi,
+ binop(Iop_SarN8x8,
+ binop(Iop_ShlN8x8,mkexpr(sHi),mkU8(4)),
+ mkU8(7)));
- assign(sAnd7hi, binop(Iop_And64,mkexpr(sHi),mkexpr(sevens)));
+ assign(sAnd7hi, binop(Iop_And64,mkexpr(sHi),mkexpr(sevens)));
- assign(
- permdHi,
- binop(
- Iop_Or64,
- binop(Iop_And64,
- binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7hi)),
- mkexpr(maskBit3hi)),
- binop(Iop_And64,
- binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7hi)),
- unop(Iop_Not64,mkexpr(maskBit3hi))) ));
+ assign(
+ permdHi,
+ binop(
+ Iop_Or64,
+ binop(Iop_And64,
+ binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7hi)),
+ mkexpr(maskBit3hi)),
+ binop(Iop_And64,
+ binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7hi)),
+ unop(Iop_Not64,mkexpr(maskBit3hi))) ));
- assign(rHi, binop(Iop_And64,mkexpr(permdHi),mkexpr(mask0x80hi)) );
+ assign(rHi, binop(Iop_And64,mkexpr(permdHi),mkexpr(mask0x80hi)) );
- /* And the same for the lower half of the result. What fun. */
+ /* And the same for the lower half of the result. What fun. */
- assign(
- mask0x80lo,
- unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sLo),mkU8(7))));
+ assign(
+ mask0x80lo,
+ unop(Iop_Not64, binop(Iop_SarN8x8,mkexpr(sLo),mkU8(7))));
- assign(
- maskBit3lo,
- binop(Iop_SarN8x8,
- binop(Iop_ShlN8x8,mkexpr(sLo),mkU8(4)),
- mkU8(7)));
+ assign(
+ maskBit3lo,
+ binop(Iop_SarN8x8,
+ binop(Iop_ShlN8x8,mkexpr(sLo),mkU8(4)),
+ mkU8(7)));
- assign(sAnd7lo, binop(Iop_And64,mkexpr(sLo),mkexpr(sevens)));
+ assign(sAnd7lo, binop(Iop_And64,mkexpr(sLo),mkexpr(sevens)));
- assign(
- permdLo,
- binop(
- Iop_Or64,
- binop(Iop_And64,
- binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7lo)),
- mkexpr(maskBit3lo)),
- binop(Iop_And64,
- binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7lo)),
- unop(Iop_Not64,mkexpr(maskBit3lo))) ));
+ assign(
+ permdLo,
+ binop(
+ Iop_Or64,
+ binop(Iop_And64,
+ binop(Iop_Perm8x8,mkexpr(dHi),mkexpr(sAnd7lo)),
+ mkexpr(maskBit3lo)),
+ binop(Iop_And64,
+ binop(Iop_Perm8x8,mkexpr(dLo),mkexpr(sAnd7lo)),
+ unop(Iop_Not64,mkexpr(maskBit3lo))) ));
- assign(rLo, binop(Iop_And64,mkexpr(permdLo),mkexpr(mask0x80lo)) );
+ assign(rLo, binop(Iop_And64,mkexpr(permdLo),mkexpr(mask0x80lo)) );
- putXMMReg(
- gregOfRexRM(pfx,modrm),
- binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo))
- );
- goto decode_success;
+ assign(res, binop(Iop_64HLtoV128, mkexpr(rHi), mkexpr(rLo)));
+ return res;
+}
+
+
+static Long dis_PHADD_128 ( VexAbiInfo* vbi, Prefix pfx, Long delta,
+ Bool isAvx, UChar opc )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ HChar* str = "???";
+ IROp opV64 = Iop_INVALID;
+ IROp opCatO = Iop_CatOddLanes16x4;
+ IROp opCatE = Iop_CatEvenLanes16x4;
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = isAvx ? getVexNvvvv(pfx) : rG;
+
+ switch (opc) {
+ case 0x01: opV64 = Iop_Add16x4; str = "addw"; break;
+ case 0x02: opV64 = Iop_Add32x2; str = "addd"; break;
+ case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break;
+ case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break;
+ case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break;
+ case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break;
+ default: vassert(0);
+ }
+ if (opc == 0x02 || opc == 0x06) {
+ opCatO = Iop_InterleaveHI32x2;
+ opCatE = Iop_InterleaveLO32x2;
}
- /* ---------------------------------------------------- */
- /* --- end of the SSSE3 decoder. --- */
- /* ---------------------------------------------------- */
+ assign( dV, getXMMReg(rV) );
- /* ---------------------------------------------------- */
- /* --- start of the SSE4 decoder --- */
- /* ---------------------------------------------------- */
-
- /* 66 0F 3A 0D /r ib = BLENDPD xmm1, xmm2/m128, imm8
- Blend Packed Double Precision Floating-Point Values (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0D ) {
-
- Int imm8;
- UShort imm8_mask_16;
-
- IRTemp dst_vec = newTemp(Ity_V128);
- IRTemp src_vec = newTemp(Ity_V128);
- IRTemp imm8_mask = newTemp(Ity_V128);
-
- modrm = insn[3];
- assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
-
- if ( epartIsReg( modrm ) ) {
- imm8 = (Int)insn[4];
- assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1+1;
- DIP( "blendpd $%d, %s,%s\n", imm8,
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf,
- 1/* imm8 is 1 byte after the amode */ );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ DIP("ph%s %s,%s\n", str, nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ if (!isAvx)
gen_SEGV_if_not_16_aligned( addr );
- assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
- imm8 = (Int)insn[2+alen+1];
- delta += 3+alen+1;
- DIP( "blendpd $%d, %s,%s\n",
- imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- switch( imm8 & 3 ) {
- case 0: imm8_mask_16 = 0x0000; break;
- case 1: imm8_mask_16 = 0x00FF; break;
- case 2: imm8_mask_16 = 0xFF00; break;
- case 3: imm8_mask_16 = 0xFFFF; break;
- default: vassert(0); break;
- }
- assign( imm8_mask, mkV128( imm8_mask_16 ) );
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_OrV128,
- binop( Iop_AndV128, mkexpr(src_vec), mkexpr(imm8_mask) ),
- binop( Iop_AndV128, mkexpr(dst_vec),
- unop( Iop_NotV128, mkexpr(imm8_mask) ) ) ) );
-
- goto decode_success;
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("ph%s %s,%s\n", str, dis_buf, nameXMMReg(rG));
+ delta += alen;
}
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
- /* 66 0F 3A 0C /r ib = BLENDPS xmm1, xmm2/m128, imm8
- Blend Packed Single Precision Floating-Point Values (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0C ) {
-
- Int imm8;
- IRTemp dst_vec = newTemp(Ity_V128);
- IRTemp src_vec = newTemp(Ity_V128);
-
- modrm = insn[3];
-
- assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
-
- if ( epartIsReg( modrm ) ) {
- imm8 = (Int)insn[3+1];
- assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1+1;
- DIP( "blendps $%d, %s,%s\n", imm8,
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf,
- 1/* imm8 is 1 byte after the amode */ );
- gen_SEGV_if_not_16_aligned( addr );
- assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
- imm8 = (Int)insn[3+alen];
- delta += 3+alen+1;
- DIP( "blendpd $%d, %s,%s\n",
- imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- UShort imm8_perms[16] = { 0x0000, 0x000F, 0x00F0, 0x00FF, 0x0F00, 0x0F0F,
- 0x0FF0, 0x0FFF, 0xF000, 0xF00F, 0xF0F0, 0xF0FF,
- 0xFF00, 0xFF0F, 0xFFF0, 0xFFFF };
- IRTemp imm8_mask = newTemp(Ity_V128);
- assign( imm8_mask, mkV128( imm8_perms[ (imm8 & 15) ] ) );
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_OrV128,
- binop( Iop_AndV128, mkexpr(src_vec), mkexpr(imm8_mask) ),
- binop( Iop_AndV128, mkexpr(dst_vec),
- unop( Iop_NotV128, mkexpr(imm8_mask) ) ) ) );
-
- goto decode_success;
- }
+ /* This isn't a particularly efficient way to compute the
+ result, but at least it avoids a proliferation of IROps,
+ hence avoids complication all the backends. */
+
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)
+ ( rG,
+ binop(Iop_64HLtoV128,
+ binop(opV64,
+ binop(opCatE,mkexpr(sHi),mkexpr(sLo)),
+ binop(opCatO,mkexpr(sHi),mkexpr(sLo)) ),
+ binop(opV64,
+ binop(opCatE,mkexpr(dHi),mkexpr(dLo)),
+ binop(opCatO,mkexpr(dHi),mkexpr(dLo)) ) ) );
+ return delta;
+}
- /* 66 0F 3A 0E /r ib = PBLENDW xmm1, xmm2/m128, imm8
- Blend Packed Words (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x0E ) {
+static IRTemp math_PMADDUBSW_128 ( IRTemp dV, IRTemp sV )
+{
+ IRTemp sVoddsSX = newTemp(Ity_V128);
+ IRTemp sVevensSX = newTemp(Ity_V128);
+ IRTemp dVoddsZX = newTemp(Ity_V128);
+ IRTemp dVevensZX = newTemp(Ity_V128);
+ /* compute dV unsigned x sV signed */
+ assign( sVoddsSX, binop(Iop_SarN16x8, mkexpr(sV), mkU8(8)) );
+ assign( sVevensSX, binop(Iop_SarN16x8,
+ binop(Iop_ShlN16x8, mkexpr(sV), mkU8(8)),
+ mkU8(8)) );
+ assign( dVoddsZX, binop(Iop_ShrN16x8, mkexpr(dV), mkU8(8)) );
+ assign( dVevensZX, binop(Iop_ShrN16x8,
+ binop(Iop_ShlN16x8, mkexpr(dV), mkU8(8)),
+ mkU8(8)) );
- Int imm8;
- IRTemp dst_vec = newTemp(Ity_V128);
- IRTemp src_vec = newTemp(Ity_V128);
-
- modrm = insn[3];
-
- assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
-
- if ( epartIsReg( modrm ) ) {
- imm8 = (Int)insn[3+1];
- assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1+1;
- DIP( "pblendw $%d, %s,%s\n", imm8,
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf,
- 1/* imm8 is 1 byte after the amode */ );
- gen_SEGV_if_not_16_aligned( addr );
- assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
- imm8 = (Int)insn[3+alen];
- delta += 3+alen+1;
- DIP( "pblendw $%d, %s,%s\n",
- imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- /* Make w be a 16-bit version of imm8, formed by duplicating each
- bit in imm8. */
- Int i;
- UShort imm16 = 0;
- for (i = 0; i < 8; i++) {
- if (imm8 & (1 << i))
- imm16 |= (3 << (2*i));
- }
- IRTemp imm16_mask = newTemp(Ity_V128);
- assign( imm16_mask, mkV128( imm16 ));
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_OrV128,
- binop( Iop_AndV128, mkexpr(src_vec), mkexpr(imm16_mask) ),
- binop( Iop_AndV128, mkexpr(dst_vec),
- unop( Iop_NotV128, mkexpr(imm16_mask) ) ) ) );
-
- goto decode_success;
- }
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop(Iop_QAdd16Sx8,
+ binop(Iop_Mul16x8, mkexpr(sVoddsSX), mkexpr(dVoddsZX)),
+ binop(Iop_Mul16x8, mkexpr(sVevensSX), mkexpr(dVevensZX))
+ )
+ );
+ return res;
+}
- /* 66 0F 3A 44 /r ib = PCLMULQDQ xmm1, xmm2/m128, imm8
- * Carry-less multiplication of selected XMM quadwords into XMM
- * registers (a.k.a multiplication of polynomials over GF(2))
- */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x44 ) {
-
- Int imm8;
- IRTemp svec = newTemp(Ity_V128);
- IRTemp dvec = newTemp(Ity_V128);
+__attribute__((noinline))
+static
+Long dis_ESC_0F38__SupSSE3 ( Bool* decode_OK,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN )
+{
+ IRTemp addr = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
- modrm = insn[3];
+ *decode_OK = False;
- assign( dvec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
-
- if ( epartIsReg( modrm ) ) {
- imm8 = (Int)insn[4];
- assign( svec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1+1;
- DIP( "pclmulqdq $%d, %s,%s\n", imm8,
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf,
- 1/* imm8 is 1 byte after the amode */ );
- gen_SEGV_if_not_16_aligned( addr );
- assign( svec, loadLE( Ity_V128, mkexpr(addr) ) );
- imm8 = (Int)insn[2+alen+1];
- delta += 3+alen+1;
- DIP( "pclmulqdq $%d, %s,%s\n",
- imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) {
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- assign(t0, unop((imm8&1)? Iop_V128HIto64 : Iop_V128to64, mkexpr(dvec)));
- assign(t1, unop((imm8&16) ? Iop_V128HIto64 : Iop_V128to64, mkexpr(svec)));
+ case 0x00:
+ /* 66 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x16 (XMM) */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /*redundant REX.W*/ sz == 8)) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
- t2 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
+ modrm = getUChar(delta);
+ assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
- IRExpr** args;
-
- args = mkIRExprVec_3(mkexpr(t0), mkexpr(t1), mkU64(0));
- assign(t2,
- mkIRExprCCall(Ity_I64,0, "amd64g_calculate_pclmul",
- &amd64g_calculate_pclmul, args));
- args = mkIRExprVec_3(mkexpr(t0), mkexpr(t1), mkU64(1));
- assign(t3,
- mkIRExprCCall(Ity_I64,0, "amd64g_calculate_pclmul",
- &amd64g_calculate_pclmul, args));
-
- IRTemp res = newTemp(Ity_V128);
- assign(res, binop(Iop_64HLtoV128, mkexpr(t3), mkexpr(t2)));
- putXMMReg( gregOfRexRM(pfx,modrm), mkexpr(res) );
-
- goto decode_success;
- }
-
- /* 66 0F 3A 41 /r ib = DPPD xmm1, xmm2/m128, imm8
- Dot Product of Packed Double Precision Floating-Point Values (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x41 ) {
-
- Int imm8;
- IRTemp src_vec = newTemp(Ity_V128);
- IRTemp dst_vec = newTemp(Ity_V128);
- IRTemp and_vec = newTemp(Ity_V128);
- IRTemp sum_vec = newTemp(Ity_V128);
-
- modrm = insn[3];
-
- assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
-
- if ( epartIsReg( modrm ) ) {
- imm8 = (Int)insn[4];
- assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1+1;
- DIP( "dppd $%d, %s,%s\n", imm8,
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf,
- 1/* imm8 is 1 byte after the amode */ );
- gen_SEGV_if_not_16_aligned( addr );
- assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
- imm8 = (Int)insn[2+alen+1];
- delta += 3+alen+1;
- DIP( "dppd $%d, %s,%s\n",
- imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- UShort imm8_perms[4] = { 0x0000, 0x00FF, 0xFF00, 0xFFFF };
-
- assign( and_vec, binop( Iop_AndV128,
- binop( Iop_Mul64Fx2,
- mkexpr(dst_vec), mkexpr(src_vec) ),
- mkV128( imm8_perms[ ((imm8 >> 4) & 3) ] ) ) );
-
- assign( sum_vec, binop( Iop_Add64F0x2,
- binop( Iop_InterleaveHI64x2,
- mkexpr(and_vec), mkexpr(and_vec) ),
- binop( Iop_InterleaveLO64x2,
- mkexpr(and_vec), mkexpr(and_vec) ) ) );
-
- putXMMReg( gregOfRexRM( pfx, modrm ),
- binop( Iop_AndV128,
- binop( Iop_InterleaveLO64x2,
- mkexpr(sum_vec), mkexpr(sum_vec) ),
- mkV128( imm8_perms[ (imm8 & 3) ] ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0F 3A 40 /r ib = DPPS xmm1, xmm2/m128, imm8
- Dot Product of Packed Single Precision Floating-Point Values (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F
- && insn[1] == 0x3A
- && insn[2] == 0x40 ) {
-
- Int imm8;
- IRTemp xmm1_vec = newTemp(Ity_V128);
- IRTemp xmm2_vec = newTemp(Ity_V128);
- IRTemp tmp_prod_vec = newTemp(Ity_V128);
- IRTemp prod_vec = newTemp(Ity_V128);
- IRTemp sum_vec = newTemp(Ity_V128);
- IRTemp v3, v2, v1, v0;
- v3 = v2 = v1 = v0 = IRTemp_INVALID;
-
- modrm = insn[3];
-
- assign( xmm1_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
-
- if ( epartIsReg( modrm ) ) {
- imm8 = (Int)insn[4];
- assign( xmm2_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1+1;
- DIP( "dpps $%d, %s,%s\n", imm8,
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf,
- 1/* imm8 is 1 byte after the amode */ );
- gen_SEGV_if_not_16_aligned( addr );
- assign( xmm2_vec, loadLE( Ity_V128, mkexpr(addr) ) );
- imm8 = (Int)insn[2+alen+1];
- delta += 3+alen+1;
- DIP( "dpps $%d, %s,%s\n",
- imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- UShort imm8_perms[16] = { 0x0000, 0x000F, 0x00F0, 0x00FF, 0x0F00,
- 0x0F0F, 0x0FF0, 0x0FFF, 0xF000, 0xF00F,
- 0xF0F0, 0xF0FF, 0xFF00, 0xFF0F, 0xFFF0, 0xFFFF };
-
- assign( tmp_prod_vec,
- binop( Iop_AndV128,
- binop( Iop_Mul32Fx4, mkexpr(xmm1_vec), mkexpr(xmm2_vec) ),
- mkV128( imm8_perms[((imm8 >> 4)& 15)] ) ) );
- breakup128to32s( tmp_prod_vec, &v3, &v2, &v1, &v0 );
- assign( prod_vec, mk128from32s( v3, v1, v2, v0 ) );
-
- assign( sum_vec, binop( Iop_Add32Fx4,
- binop( Iop_InterleaveHI32x4,
- mkexpr(prod_vec), mkexpr(prod_vec) ),
- binop( Iop_InterleaveLO32x4,
- mkexpr(prod_vec), mkexpr(prod_vec) ) ) );
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_AndV128,
- binop( Iop_Add32Fx4,
- binop( Iop_InterleaveHI32x4,
- mkexpr(sum_vec), mkexpr(sum_vec) ),
- binop( Iop_InterleaveLO32x4,
- mkexpr(sum_vec), mkexpr(sum_vec) ) ),
- mkV128( imm8_perms[ (imm8 & 15) ] ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0F 3A 21 /r ib = INSERTPS xmm1, xmm2/m32, imm8
- Insert Packed Single Precision Floating-Point Value (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x21 ) {
-
- Int imm8;
- Int imm8_count_s;
- Int imm8_count_d;
- Int imm8_zmask;
- IRTemp dstVec = newTemp(Ity_V128);
- IRTemp srcDWord = newTemp(Ity_I32);
-
- modrm = insn[3];
-
- assign( dstVec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
-
- if ( epartIsReg( modrm ) ) {
- IRTemp src_vec = newTemp(Ity_V128);
- assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
-
- IRTemp src_lane_0 = IRTemp_INVALID;
- IRTemp src_lane_1 = IRTemp_INVALID;
- IRTemp src_lane_2 = IRTemp_INVALID;
- IRTemp src_lane_3 = IRTemp_INVALID;
- breakup128to32s( src_vec,
- &src_lane_3, &src_lane_2, &src_lane_1, &src_lane_0 );
-
- imm8 = (Int)insn[4];
- imm8_count_s = ((imm8 >> 6) & 3);
- switch( imm8_count_s ) {
- case 0: assign( srcDWord, mkexpr(src_lane_0) ); break;
- case 1: assign( srcDWord, mkexpr(src_lane_1) ); break;
- case 2: assign( srcDWord, mkexpr(src_lane_2) ); break;
- case 3: assign( srcDWord, mkexpr(src_lane_3) ); break;
- default: vassert(0); break;
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
+ delta += 1;
+ DIP("pshufb %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("pshufb %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
}
- delta += 3+1+1;
- DIP( "insertps $%d, %s,%s\n", imm8,
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf,
- 1/* const imm8 is 1 byte after the amode */ );
- assign( srcDWord, loadLE( Ity_I32, mkexpr(addr) ) );
- imm8 = (Int)insn[2+alen+1];
- imm8_count_s = 0;
- delta += 3+alen+1;
- DIP( "insertps $%d, %s,%s\n",
- imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ IRTemp res = math_PSHUFB_XMM( dV, sV );
+ putXMMReg(gregOfRexRM(pfx,modrm), mkexpr(res));
+ goto decode_success;
}
+ /* 0F 38 00 = PSHUFB -- Packed Shuffle Bytes 8x8 (MMX) */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
- IRTemp dst_lane_0 = IRTemp_INVALID;
- IRTemp dst_lane_1 = IRTemp_INVALID;
- IRTemp dst_lane_2 = IRTemp_INVALID;
- IRTemp dst_lane_3 = IRTemp_INVALID;
- breakup128to32s( dstVec,
- &dst_lane_3, &dst_lane_2, &dst_lane_1, &dst_lane_0 );
+ modrm = getUChar(delta);
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
- imm8_count_d = ((imm8 >> 4) & 3);
- switch( imm8_count_d ) {
- case 0: dst_lane_0 = srcDWord; break;
- case 1: dst_lane_1 = srcDWord; break;
- case 2: dst_lane_2 = srcDWord; break;
- case 3: dst_lane_3 = srcDWord; break;
- default: vassert(0); break;
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
+ delta += 1;
+ DIP("pshufb %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("pshufb %s,%s\n", dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+
+ putMMXReg(
+ gregLO3ofRM(modrm),
+ binop(
+ Iop_And64,
+ /* permute the lanes */
+ binop(
+ Iop_Perm8x8,
+ mkexpr(dV),
+ binop(Iop_And64, mkexpr(sV), mkU64(0x0707070707070707ULL))
+ ),
+ /* mask off lanes which have (index & 0x80) == 0x80 */
+ unop(Iop_Not64, binop(Iop_SarN8x8, mkexpr(sV), mkU8(7)))
+ )
+ );
+ goto decode_success;
}
+ break;
- imm8_zmask = (imm8 & 15);
- IRTemp zero_32 = newTemp(Ity_I32);
- assign( zero_32, mkU32(0) );
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ case 0x05:
+ case 0x06:
+ case 0x07:
+ /* 66 0F 38 01 = PHADDW -- 16x8 add across from E (mem or xmm) and
+ G to G (xmm). */
+ /* 66 0F 38 02 = PHADDD -- 32x4 add across from E (mem or xmm) and
+ G to G (xmm). */
+ /* 66 0F 38 03 = PHADDSW -- 16x8 signed qadd across from E (mem or
+ xmm) and G to G (xmm). */
+ /* 66 0F 38 05 = PHSUBW -- 16x8 sub across from E (mem or xmm) and
+ G to G (xmm). */
+ /* 66 0F 38 06 = PHSUBD -- 32x4 sub across from E (mem or xmm) and
+ G to G (xmm). */
+ /* 66 0F 38 07 = PHSUBSW -- 16x8 signed qsub across from E (mem or
+ xmm) and G to G (xmm). */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /*redundant REX.W*/ sz == 8)) {
+ delta = dis_PHADD_128( vbi, pfx, delta, False/*isAvx*/, opc );
+ goto decode_success;
+ }
+ /* ***--- these are MMX class insns introduced in SSSE3 ---*** */
+ /* 0F 38 01 = PHADDW -- 16x4 add across from E (mem or mmx) and G
+ to G (mmx). */
+ /* 0F 38 02 = PHADDD -- 32x2 add across from E (mem or mmx) and G
+ to G (mmx). */
+ /* 0F 38 03 = PHADDSW -- 16x4 signed qadd across from E (mem or
+ mmx) and G to G (mmx). */
+ /* 0F 38 05 = PHSUBW -- 16x4 sub across from E (mem or mmx) and G
+ to G (mmx). */
+ /* 0F 38 06 = PHSUBD -- 32x2 sub across from E (mem or mmx) and G
+ to G (mmx). */
+ /* 0F 38 07 = PHSUBSW -- 16x4 signed qsub across from E (mem or
+ mmx) and G to G (mmx). */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ HChar* str = "???";
+ IROp opV64 = Iop_INVALID;
+ IROp opCatO = Iop_CatOddLanes16x4;
+ IROp opCatE = Iop_CatEvenLanes16x4;
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
- IRExpr* ire_vec_128 = mk128from32s(
- ((imm8_zmask & 8) == 8) ? zero_32 : dst_lane_3,
- ((imm8_zmask & 4) == 4) ? zero_32 : dst_lane_2,
- ((imm8_zmask & 2) == 2) ? zero_32 : dst_lane_1,
- ((imm8_zmask & 1) == 1) ? zero_32 : dst_lane_0 );
+ modrm = getUChar(delta);
- putXMMReg( gregOfRexRM(pfx, modrm), ire_vec_128 );
-
- goto decode_success;
+ switch (opc) {
+ case 0x01: opV64 = Iop_Add16x4; str = "addw"; break;
+ case 0x02: opV64 = Iop_Add32x2; str = "addd"; break;
+ case 0x03: opV64 = Iop_QAdd16Sx4; str = "addsw"; break;
+ case 0x05: opV64 = Iop_Sub16x4; str = "subw"; break;
+ case 0x06: opV64 = Iop_Sub32x2; str = "subd"; break;
+ case 0x07: opV64 = Iop_QSub16Sx4; str = "subsw"; break;
+ default: vassert(0);
+ }
+ if (opc == 0x02 || opc == 0x06) {
+ opCatO = Iop_InterleaveHI32x2;
+ opCatE = Iop_InterleaveLO32x2;
+ }
+
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
+ delta += 1;
+ DIP("ph%s %s,%s\n", str, nameMMXReg(eregLO3ofRM(modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("ph%s %s,%s\n", str, dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+
+ putMMXReg(
+ gregLO3ofRM(modrm),
+ binop(opV64,
+ binop(opCatE,mkexpr(sV),mkexpr(dV)),
+ binop(opCatO,mkexpr(sV),mkexpr(dV))
+ )
+ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x04:
+ /* 66 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and
+ Unsigned Bytes (XMM) */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /*redundant REX.W*/ sz == 8)) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+
+ assign( dV, getXMMReg(rG) );
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("pmaddubsw %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("pmaddubsw %s,%s\n", dis_buf, nameXMMReg(rG));
+ }
+
+ putXMMReg( rG, mkexpr( math_PMADDUBSW_128( dV, sV ) ) );
+ goto decode_success;
+ }
+ /* 0F 38 04 = PMADDUBSW -- Multiply and Add Packed Signed and
+ Unsigned Bytes (MMX) */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+ IRTemp sVoddsSX = newTemp(Ity_I64);
+ IRTemp sVevensSX = newTemp(Ity_I64);
+ IRTemp dVoddsZX = newTemp(Ity_I64);
+ IRTemp dVevensZX = newTemp(Ity_I64);
+
+ modrm = getUChar(delta);
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
+ delta += 1;
+ DIP("pmaddubsw %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("pmaddubsw %s,%s\n", dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+
+ /* compute dV unsigned x sV signed */
+ assign( sVoddsSX,
+ binop(Iop_SarN16x4, mkexpr(sV), mkU8(8)) );
+ assign( sVevensSX,
+ binop(Iop_SarN16x4,
+ binop(Iop_ShlN16x4, mkexpr(sV), mkU8(8)),
+ mkU8(8)) );
+ assign( dVoddsZX,
+ binop(Iop_ShrN16x4, mkexpr(dV), mkU8(8)) );
+ assign( dVevensZX,
+ binop(Iop_ShrN16x4,
+ binop(Iop_ShlN16x4, mkexpr(dV), mkU8(8)),
+ mkU8(8)) );
+
+ putMMXReg(
+ gregLO3ofRM(modrm),
+ binop(Iop_QAdd16Sx4,
+ binop(Iop_Mul16x4, mkexpr(sVoddsSX), mkexpr(dVoddsZX)),
+ binop(Iop_Mul16x4, mkexpr(sVevensSX), mkexpr(dVevensZX))
+ )
+ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x08:
+ case 0x09:
+ case 0x0A:
+ /* 66 0F 38 08 = PSIGNB -- Packed Sign 8x16 (XMM) */
+ /* 66 0F 38 09 = PSIGNW -- Packed Sign 16x8 (XMM) */
+ /* 66 0F 38 0A = PSIGND -- Packed Sign 32x4 (XMM) */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /*redundant REX.W*/ sz == 8)) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ HChar* str = "???";
+ Int laneszB = 0;
+
+ switch (opc) {
+ case 0x08: laneszB = 1; str = "b"; break;
+ case 0x09: laneszB = 2; str = "w"; break;
+ case 0x0A: laneszB = 4; str = "d"; break;
+ default: vassert(0);
+ }
+
+ modrm = getUChar(delta);
+ assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
+ delta += 1;
+ DIP("psign%s %s,%s\n", str, nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("psign%s %s,%s\n", str, dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+
+ putXMMReg(
+ gregOfRexRM(pfx,modrm),
+ binop(Iop_64HLtoV128,
+ dis_PSIGN_helper( mkexpr(sHi), mkexpr(dHi), laneszB ),
+ dis_PSIGN_helper( mkexpr(sLo), mkexpr(dLo), laneszB )
+ )
+ );
+ goto decode_success;
+ }
+ /* 0F 38 08 = PSIGNB -- Packed Sign 8x8 (MMX) */
+ /* 0F 38 09 = PSIGNW -- Packed Sign 16x4 (MMX) */
+ /* 0F 38 0A = PSIGND -- Packed Sign 32x2 (MMX) */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+ HChar* str = "???";
+ Int laneszB = 0;
+
+ switch (opc) {
+ case 0x08: laneszB = 1; str = "b"; break;
+ case 0x09: laneszB = 2; str = "w"; break;
+ case 0x0A: laneszB = 4; str = "d"; break;
+ default: vassert(0);
+ }
+
+ modrm = getUChar(delta);
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
+ delta += 1;
+ DIP("psign%s %s,%s\n", str, nameMMXReg(eregLO3ofRM(modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("psign%s %s,%s\n", str, dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+
+ putMMXReg(
+ gregLO3ofRM(modrm),
+ dis_PSIGN_helper( mkexpr(sV), mkexpr(dV), laneszB )
+ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x0B:
+ /* 66 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and
+ Scale (XMM) */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /*redundant REX.W*/ sz == 8)) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+
+ modrm = getUChar(delta);
+ assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
+ delta += 1;
+ DIP("pmulhrsw %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("pmulhrsw %s,%s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dV)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dV)) );
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+
+ putXMMReg(
+ gregOfRexRM(pfx,modrm),
+ binop(Iop_64HLtoV128,
+ dis_PMULHRSW_helper( mkexpr(sHi), mkexpr(dHi) ),
+ dis_PMULHRSW_helper( mkexpr(sLo), mkexpr(dLo) )
+ )
+ );
+ goto decode_success;
+ }
+ /* 0F 38 0B = PMULHRSW -- Packed Multiply High with Round and Scale
+ (MMX) */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+
+ modrm = getUChar(delta);
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
+ delta += 1;
+ DIP("pmulhrsw %s,%s\n", nameMMXReg(eregLO3ofRM(modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("pmulhrsw %s,%s\n", dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+
+ putMMXReg(
+ gregLO3ofRM(modrm),
+ dis_PMULHRSW_helper( mkexpr(sV), mkexpr(dV) )
+ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x1C:
+ case 0x1D:
+ case 0x1E:
+ /* 66 0F 38 1C = PABSB -- Packed Absolute Value 8x16 (XMM) */
+ /* 66 0F 38 1D = PABSW -- Packed Absolute Value 16x8 (XMM) */
+ /* 66 0F 38 1E = PABSD -- Packed Absolute Value 32x4 (XMM) */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /*redundant REX.W*/ sz == 8)) {
+ IRTemp sV = newTemp(Ity_V128);
+ HChar* str = "???";
+ Int laneszB = 0;
+
+ switch (opc) {
+ case 0x1C: laneszB = 1; str = "b"; break;
+ case 0x1D: laneszB = 2; str = "w"; break;
+ case 0x1E: laneszB = 4; str = "d"; break;
+ default: vassert(0);
+ }
+
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
+ delta += 1;
+ DIP("pabs%s %s,%s\n", str, nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("pabs%s %s,%s\n", str, dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+
+ putXMMReg( gregOfRexRM(pfx,modrm),
+ mkexpr(math_PABS_XMM(sV, laneszB)) );
+ goto decode_success;
+ }
+ /* 0F 38 1C = PABSB -- Packed Absolute Value 8x8 (MMX) */
+ /* 0F 38 1D = PABSW -- Packed Absolute Value 16x4 (MMX) */
+ /* 0F 38 1E = PABSD -- Packed Absolute Value 32x2 (MMX) */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ IRTemp sV = newTemp(Ity_I64);
+ HChar* str = "???";
+ Int laneszB = 0;
+
+ switch (opc) {
+ case 0x1C: laneszB = 1; str = "b"; break;
+ case 0x1D: laneszB = 2; str = "w"; break;
+ case 0x1E: laneszB = 4; str = "d"; break;
+ default: vassert(0);
+ }
+
+ modrm = getUChar(delta);
+ do_MMX_preamble();
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
+ delta += 1;
+ DIP("pabs%s %s,%s\n", str, nameMMXReg(eregLO3ofRM(modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("pabs%s %s,%s\n", str, dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+
+ putMMXReg( gregLO3ofRM(modrm),
+ mkexpr(math_PABS_MMX( sV, laneszB )) );
+ goto decode_success;
+ }
+ break;
+
+ default:
+ break;
+
}
+ //decode_failure:
+ *decode_OK = False;
+ return deltaIN;
- /* 66 0F 3A 14 /r ib = PEXTRB r/m16, xmm, imm8
- Extract Byte from xmm, store in mem or zero-extend + store in gen.reg. (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x14 ) {
-
- Int imm8;
- IRTemp xmm_vec = newTemp(Ity_V128);
- IRTemp sel_lane = newTemp(Ity_I32);
- IRTemp shr_lane = newTemp(Ity_I32);
-
- modrm = insn[3];
- assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) );
- breakup128to32s( xmm_vec, &t3, &t2, &t1, &t0 );
-
- if ( epartIsReg( modrm ) ) {
- imm8 = (Int)insn[3+1];
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
- imm8 = (Int)insn[3+alen];
- }
- switch( (imm8 >> 2) & 3 ) {
- case 0: assign( sel_lane, mkexpr(t0) ); break;
- case 1: assign( sel_lane, mkexpr(t1) ); break;
- case 2: assign( sel_lane, mkexpr(t2) ); break;
- case 3: assign( sel_lane, mkexpr(t3) ); break;
- default: vassert(0);
- }
- assign( shr_lane,
- binop( Iop_Shr32, mkexpr(sel_lane), mkU8(((imm8 & 3)*8)) ) );
-
- if ( epartIsReg( modrm ) ) {
- putIReg64( eregOfRexRM(pfx,modrm),
- unop( Iop_32Uto64,
- binop(Iop_And32, mkexpr(shr_lane), mkU32(255)) ) );
-
- delta += 3+1+1;
- DIP( "pextrb $%d, %s,%s\n", imm8,
- nameXMMReg( gregOfRexRM(pfx, modrm) ),
- nameIReg64( eregOfRexRM(pfx, modrm) ) );
- } else {
- storeLE( mkexpr(addr), unop(Iop_32to8, mkexpr(shr_lane) ) );
- delta += 3+alen+1;
- DIP( "$%d, pextrb %s,%s\n",
- imm8, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf );
- }
-
- goto decode_success;
- }
+ decode_success:
+ *decode_OK = True;
+ return delta;
+}
- /* 66 0F 3A 16 /r ib = PEXTRD reg/mem32, xmm2, imm8
- Extract Doubleword int from xmm reg and store in gen.reg or mem. (XMM)
- Note that this insn has the same opcodes as PEXTRQ, but
- here the REX.W bit is _not_ present */
- if ( have66noF2noF3( pfx )
- && sz == 2 /* REX.W is _not_ present */
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x16 ) {
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level SSSE3: dis_ESC_0F3A__SupSSE3 ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
- Int imm8_10;
- IRTemp xmm_vec = newTemp(Ity_V128);
- IRTemp src_dword = newTemp(Ity_I32);
+__attribute__((noinline))
+static
+Long dis_ESC_0F3A__SupSSE3 ( Bool* decode_OK,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN )
+{
+ Long d64 = 0;
+ IRTemp addr = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
- modrm = insn[3];
- assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) );
- breakup128to32s( xmm_vec, &t3, &t2, &t1, &t0 );
+ *decode_OK = False;
- if ( epartIsReg( modrm ) ) {
- imm8_10 = (Int)(insn[3+1] & 3);
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
- imm8_10 = (Int)(insn[3+alen] & 3);
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) {
+
+ case 0x0F:
+ /* 66 0F 3A 0F = PALIGNR -- Packed Align Right (XMM) */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /*redundant REX.W*/ sz == 8)) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+
+ modrm = getUChar(delta);
+ assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
+ d64 = (Long)getUChar(delta+1);
+ delta += 1+1;
+ DIP("palignr $%d,%s,%s\n", (Int)d64,
+ nameXMMReg(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ d64 = (Long)getUChar(delta+alen);
+ delta += alen+1;
+ DIP("palignr $%d,%s,%s\n", (Int)d64,
+ dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+
+ IRTemp res = math_PALIGNR_XMM( sV, dV, d64 );
+ putXMMReg( gregOfRexRM(pfx,modrm), mkexpr(res) );
+ goto decode_success;
}
+ /* 0F 3A 0F = PALIGNR -- Packed Align Right (MMX) */
+ if (haveNo66noF2noF3(pfx) && sz == 4) {
+ IRTemp sV = newTemp(Ity_I64);
+ IRTemp dV = newTemp(Ity_I64);
+ IRTemp res = newTemp(Ity_I64);
- switch ( imm8_10 ) {
- case 0: assign( src_dword, mkexpr(t0) ); break;
- case 1: assign( src_dword, mkexpr(t1) ); break;
- case 2: assign( src_dword, mkexpr(t2) ); break;
- case 3: assign( src_dword, mkexpr(t3) ); break;
- default: vassert(0);
+ modrm = getUChar(delta);
+ do_MMX_preamble();
+ assign( dV, getMMXReg(gregLO3ofRM(modrm)) );
+
+ if (epartIsReg(modrm)) {
+ assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
+ d64 = (Long)getUChar(delta+1);
+ delta += 1+1;
+ DIP("palignr $%d,%s,%s\n", (Int)d64,
+ nameMMXReg(eregLO3ofRM(modrm)),
+ nameMMXReg(gregLO3ofRM(modrm)));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
+ d64 = (Long)getUChar(delta+alen);
+ delta += alen+1;
+ DIP("palignr $%d%s,%s\n", (Int)d64,
+ dis_buf,
+ nameMMXReg(gregLO3ofRM(modrm)));
+ }
+
+ if (d64 == 0) {
+ assign( res, mkexpr(sV) );
+ }
+ else if (d64 >= 1 && d64 <= 7) {
+ assign(res,
+ binop(Iop_Or64,
+ binop(Iop_Shr64, mkexpr(sV), mkU8(8*d64)),
+ binop(Iop_Shl64, mkexpr(dV), mkU8(8*(8-d64))
+ )));
+ }
+ else if (d64 == 8) {
+ assign( res, mkexpr(dV) );
+ }
+ else if (d64 >= 9 && d64 <= 15) {
+ assign( res, binop(Iop_Shr64, mkexpr(dV), mkU8(8*(d64-8))) );
+ }
+ else if (d64 >= 16 && d64 <= 255) {
+ assign( res, mkU64(0) );
+ }
+ else
+ vassert(0);
+
+ putMMXReg( gregLO3ofRM(modrm), mkexpr(res) );
+ goto decode_success;
}
+ break;
- if ( epartIsReg( modrm ) ) {
- putIReg32( eregOfRexRM(pfx,modrm), mkexpr(src_dword) );
- delta += 3+1+1;
- DIP( "pextrd $%d, %s,%s\n", imm8_10,
- nameXMMReg( gregOfRexRM(pfx, modrm) ),
- nameIReg32( eregOfRexRM(pfx, modrm) ) );
- } else {
- storeLE( mkexpr(addr), mkexpr(src_dword) );
- delta += 3+alen+1;
- DIP( "pextrd $%d, %s,%s\n",
- imm8_10, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf );
- }
+ default:
+ break;
- goto decode_success;
}
+ //decode_failure:
+ *decode_OK = False;
+ return deltaIN;
- /* 66 REX.W 0F 3A 16 /r ib = PEXTRQ reg/mem64, xmm2, imm8
- Extract Quadword int from xmm reg and store in gen.reg or mem. (XMM)
- Note that this insn has the same opcodes as PEXTRD, but
- here the REX.W bit is present */
- if ( have66noF2noF3( pfx )
- && sz == 8 /* REX.W is present */
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x16 ) {
+ decode_success:
+ *decode_OK = True;
+ return delta;
+}
- Int imm8_0;
- IRTemp xmm_vec = newTemp(Ity_V128);
- IRTemp src_qword = newTemp(Ity_I64);
- modrm = insn[3];
- assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) );
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level SSE4: dis_ESC_0F__SSE4 ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
- if ( epartIsReg( modrm ) ) {
- imm8_0 = (Int)(insn[3+1] & 1);
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
- imm8_0 = (Int)(insn[3+alen] & 1);
- }
- switch ( imm8_0 ) {
- case 0: assign( src_qword, unop(Iop_V128to64, mkexpr(xmm_vec)) ); break;
- case 1: assign( src_qword, unop(Iop_V128HIto64, mkexpr(xmm_vec)) ); break;
- default: vassert(0);
- }
+__attribute__((noinline))
+static
+Long dis_ESC_0F__SSE4 ( Bool* decode_OK,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN )
+{
+ IRTemp addr = IRTemp_INVALID;
+ IRType ty = Ity_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
- if ( epartIsReg( modrm ) ) {
- putIReg64( eregOfRexRM(pfx,modrm), mkexpr(src_qword) );
- delta += 3+1+1;
- DIP( "pextrq $%d, %s,%s\n", imm8_0,
- nameXMMReg( gregOfRexRM(pfx, modrm) ),
- nameIReg64( eregOfRexRM(pfx, modrm) ) );
- } else {
- storeLE( mkexpr(addr), mkexpr(src_qword) );
- delta += 3+alen+1;
- DIP( "pextrq $%d, %s,%s\n",
- imm8_0, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf );
- }
+ *decode_OK = False;
- goto decode_success;
- }
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) {
+ case 0xB8:
+ /* F3 0F B8 = POPCNT{W,L,Q}
+ Count the number of 1 bits in a register
+ */
+ if (haveF3noF2(pfx) /* so both 66 and REX.W are possibilities */
+ && (sz == 2 || sz == 4 || sz == 8)) {
+ /*IRType*/ ty = szToITy(sz);
+ IRTemp src = newTemp(ty);
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ assign(src, getIRegE(sz, pfx, modrm));
+ delta += 1;
+ DIP("popcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
+ nameIRegG(sz, pfx, modrm));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0);
+ assign(src, loadLE(ty, mkexpr(addr)));
+ delta += alen;
+ DIP("popcnt%c %s, %s\n", nameISize(sz), dis_buf,
+ nameIRegG(sz, pfx, modrm));
+ }
- /* 66 0F 3A 15 /r ib = PEXTRW r/m16, xmm, imm8
- Extract Word from xmm, store in mem or zero-extend + store in gen.reg. (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x15 ) {
+ IRTemp result = gen_POPCOUNT(ty, src);
+ putIRegG(sz, pfx, modrm, mkexpr(result));
- Int imm8_20;
- IRTemp xmm_vec = newTemp(Ity_V128);
- IRTemp src_word = newTemp(Ity_I16);
-
- modrm = insn[3];
- assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) );
- breakup128to32s( xmm_vec, &t3, &t2, &t1, &t0 );
-
- if ( epartIsReg( modrm ) ) {
- imm8_20 = (Int)(insn[3+1] & 7);
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
- imm8_20 = (Int)(insn[3+alen] & 7);
- }
-
- switch ( imm8_20 ) {
- case 0: assign( src_word, unop(Iop_32to16, mkexpr(t0)) ); break;
- case 1: assign( src_word, unop(Iop_32HIto16, mkexpr(t0)) ); break;
- case 2: assign( src_word, unop(Iop_32to16, mkexpr(t1)) ); break;
- case 3: assign( src_word, unop(Iop_32HIto16, mkexpr(t1)) ); break;
- case 4: assign( src_word, unop(Iop_32to16, mkexpr(t2)) ); break;
- case 5: assign( src_word, unop(Iop_32HIto16, mkexpr(t2)) ); break;
- case 6: assign( src_word, unop(Iop_32to16, mkexpr(t3)) ); break;
- case 7: assign( src_word, unop(Iop_32HIto16, mkexpr(t3)) ); break;
- default: vassert(0);
- }
-
- if ( epartIsReg( modrm ) ) {
- putIReg64( eregOfRexRM(pfx,modrm), unop(Iop_16Uto64, mkexpr(src_word)) );
- delta += 3+1+1;
- DIP( "pextrw $%d, %s,%s\n", imm8_20,
- nameXMMReg( gregOfRexRM(pfx, modrm) ),
- nameIReg64( eregOfRexRM(pfx, modrm) ) );
- } else {
- storeLE( mkexpr(addr), mkexpr(src_word) );
- delta += 3+alen+1;
- DIP( "pextrw $%d, %s,%s\n",
- imm8_20, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf );
- }
-
- goto decode_success;
- }
-
-
- /* 66 REX.W 0F 3A 22 /r ib = PINSRQ xmm1, r/m64, imm8
- Extract Quadword int from gen.reg/mem64 and insert into xmm1 */
- if ( have66noF2noF3( pfx )
- && sz == 8 /* REX.W is present */
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x22 ) {
-
- Int imm8_0;
- IRTemp src_elems = newTemp(Ity_I64);
- IRTemp src_vec = newTemp(Ity_V128);
-
- modrm = insn[3];
-
- if ( epartIsReg( modrm ) ) {
- imm8_0 = (Int)(insn[3+1] & 1);
- assign( src_elems, getIReg64( eregOfRexRM(pfx,modrm) ) );
- delta += 3+1+1;
- DIP( "pinsrq $%d, %s,%s\n", imm8_0,
- nameIReg64( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
- imm8_0 = (Int)(insn[3+alen] & 1);
- assign( src_elems, loadLE( Ity_I64, mkexpr(addr) ) );
- delta += 3+alen+1;
- DIP( "pinsrq $%d, %s,%s\n",
- imm8_0, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- UShort mask = 0;
- if ( imm8_0 == 0 ) {
- mask = 0xFF00;
- assign( src_vec, binop( Iop_64HLtoV128, mkU64(0), mkexpr(src_elems) ) );
- } else {
- mask = 0x00FF;
- assign( src_vec, binop( Iop_64HLtoV128, mkexpr(src_elems), mkU64(0) ) );
- }
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_OrV128, mkexpr(src_vec),
- binop( Iop_AndV128,
- getXMMReg( gregOfRexRM(pfx, modrm) ),
- mkV128(mask) ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 no-REX.W 0F 3A 22 /r ib = PINSRD xmm1, r/m32, imm8
- Extract Doubleword int from gen.reg/mem32 and insert into xmm1 */
- if ( have66noF2noF3( pfx )
- && sz == 2 /* REX.W is NOT present */
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x22 ) {
-
- Int imm8_10;
- IRTemp src_elems = newTemp(Ity_I32);
- IRTemp src_vec = newTemp(Ity_V128);
- IRTemp z32 = newTemp(Ity_I32);
-
- modrm = insn[3];
-
- if ( epartIsReg( modrm ) ) {
- imm8_10 = (Int)(insn[3+1] & 3);
- assign( src_elems, getIReg32( eregOfRexRM(pfx,modrm) ) );
- delta += 3+1+1;
- DIP( "pinsrd $%d, %s,%s\n", imm8_10,
- nameIReg32( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
- imm8_10 = (Int)(insn[3+alen] & 3);
- assign( src_elems, loadLE( Ity_I32, mkexpr(addr) ) );
- delta += 3+alen+1;
- DIP( "pinsrd $%d, %s,%s\n",
- imm8_10, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- assign(z32, mkU32(0));
-
- UShort mask = 0;
- switch (imm8_10) {
- case 3: mask = 0x0FFF;
- assign(src_vec, mk128from32s(src_elems, z32, z32, z32));
- break;
- case 2: mask = 0xF0FF;
- assign(src_vec, mk128from32s(z32, src_elems, z32, z32));
- break;
- case 1: mask = 0xFF0F;
- assign(src_vec, mk128from32s(z32, z32, src_elems, z32));
- break;
- case 0: mask = 0xFFF0;
- assign(src_vec, mk128from32s(z32, z32, z32, src_elems));
- break;
- default: vassert(0);
- }
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_OrV128, mkexpr(src_vec),
- binop( Iop_AndV128,
- getXMMReg( gregOfRexRM(pfx, modrm) ),
- mkV128(mask) ) ) );
-
- goto decode_success;
- }
-
- /* 66 0F 3A 20 /r ib = PINSRB xmm1, r32/m8, imm8
- Extract byte from r32/m8 and insert into xmm1 */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x20 ) {
-
- Int imm8;
- IRTemp new8 = newTemp(Ity_I64);
-
- modrm = insn[3];
-
- if ( epartIsReg( modrm ) ) {
- imm8 = (Int)(insn[3+1] & 0xF);
- assign( new8, binop(Iop_And64,
- unop(Iop_32Uto64,
- getIReg32(eregOfRexRM(pfx,modrm))),
- mkU64(0xFF)));
- delta += 3+1+1;
- DIP( "pinsrb $%d,%s,%s\n", imm8,
- nameIReg32( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
- imm8 = (Int)(insn[3+alen] & 0xF);
- assign( new8, unop(Iop_8Uto64, loadLE( Ity_I8, mkexpr(addr) )));
- delta += 3+alen+1;
- DIP( "pinsrb $%d,%s,%s\n",
- imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- // Create a V128 value which has the selected byte in the
- // specified lane, and zeroes everywhere else.
- IRTemp tmp128 = newTemp(Ity_V128);
- IRTemp halfshift = newTemp(Ity_I64);
- assign(halfshift, binop(Iop_Shl64,
- mkexpr(new8), mkU8(8 * (imm8 & 7))));
- vassert(imm8 >= 0 && imm8 <= 15);
- if (imm8 < 8) {
- assign(tmp128, binop(Iop_64HLtoV128, mkU64(0), mkexpr(halfshift)));
- } else {
- assign(tmp128, binop(Iop_64HLtoV128, mkexpr(halfshift), mkU64(0)));
- }
-
- UShort mask = ~(1 << imm8);
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_OrV128,
- mkexpr(tmp128),
- binop( Iop_AndV128,
- getXMMReg( gregOfRexRM(pfx, modrm) ),
- mkV128(mask) ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0F 3A 17 /r ib = EXTRACTPS reg/mem32, xmm2, imm8 Extract
- float from xmm reg and store in gen.reg or mem. This is
- identical to PEXTRD, except that REX.W appears to be ignored.
- */
- if ( have66noF2noF3( pfx )
- && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x17 ) {
-
- Int imm8_10;
- IRTemp xmm_vec = newTemp(Ity_V128);
- IRTemp src_dword = newTemp(Ity_I32);
-
- modrm = insn[3];
- assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) );
- breakup128to32s( xmm_vec, &t3, &t2, &t1, &t0 );
-
- if ( epartIsReg( modrm ) ) {
- imm8_10 = (Int)(insn[3+1] & 3);
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
- imm8_10 = (Int)(insn[3+alen] & 3);
- }
-
- switch ( imm8_10 ) {
- case 0: assign( src_dword, mkexpr(t0) ); break;
- case 1: assign( src_dword, mkexpr(t1) ); break;
- case 2: assign( src_dword, mkexpr(t2) ); break;
- case 3: assign( src_dword, mkexpr(t3) ); break;
- default: vassert(0);
- }
-
- if ( epartIsReg( modrm ) ) {
- putIReg32( eregOfRexRM(pfx,modrm), mkexpr(src_dword) );
- delta += 3+1+1;
- DIP( "extractps $%d, %s,%s\n", imm8_10,
- nameXMMReg( gregOfRexRM(pfx, modrm) ),
- nameIReg32( eregOfRexRM(pfx, modrm) ) );
- } else {
- storeLE( mkexpr(addr), mkexpr(src_dword) );
- delta += 3+alen+1;
- DIP( "extractps $%d, %s,%s\n",
- imm8_10, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf );
- }
-
- goto decode_success;
- }
-
-
- /* 66 0F 38 37 = PCMPGTQ
- 64x2 comparison (signed, presumably; the Intel docs don't say :-)
- */
- if ( have66noF2noF3( pfx ) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x37) {
- /* FIXME: this needs an alignment check */
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+3,
- "pcmpgtq", Iop_CmpGT64Sx2, False );
- goto decode_success;
- }
-
- /* 66 0F 38 3D /r = PMAXSD xmm1, xmm2/m128
- Maximum of Packed Signed Double Word Integers (XMM)
- 66 0F 38 39 /r = PMINSD xmm1, xmm2/m128
- Minimum of Packed Signed Double Word Integers (XMM) */
- if ( have66noF2noF3( pfx ) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x3D || insn[2] == 0x39)) {
- /* FIXME: this needs an alignment check */
- Bool isMAX = insn[2] == 0x3D;
- delta = dis_SSEint_E_to_G(
- vbi, pfx, delta+3,
- isMAX ? "pmaxsd" : "pminsd",
- isMAX ? Iop_Max32Sx4 : Iop_Min32Sx4,
- False
- );
- goto decode_success;
- }
-
- /* 66 0F 38 3F /r = PMAXUD xmm1, xmm2/m128
- Maximum of Packed Unsigned Doubleword Integers (XMM)
- 66 0F 38 3B /r = PMINUD xmm1, xmm2/m128
- Minimum of Packed Unsigned Doubleword Integers (XMM) */
- if ( have66noF2noF3( pfx ) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x3F || insn[2] == 0x3B)) {
- /* FIXME: this needs an alignment check */
- Bool isMAX = insn[2] == 0x3F;
- delta = dis_SSEint_E_to_G(
- vbi, pfx, delta+3,
- isMAX ? "pmaxud" : "pminud",
- isMAX ? Iop_Max32Ux4 : Iop_Min32Ux4,
- False
- );
- goto decode_success;
- }
-
- /* 66 0F 38 3E /r = PMAXUW xmm1, xmm2/m128
- Maximum of Packed Unsigned Word Integers (XMM)
- 66 0F 38 3A /r = PMINUW xmm1, xmm2/m128
- Minimum of Packed Unsigned Word Integers (XMM)
- */
- if ( have66noF2noF3( pfx ) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x3E || insn[2] == 0x3A)) {
- /* FIXME: this needs an alignment check */
- Bool isMAX = insn[2] == 0x3E;
- delta = dis_SSEint_E_to_G(
- vbi, pfx, delta+3,
- isMAX ? "pmaxuw" : "pminuw",
- isMAX ? Iop_Max16Ux8 : Iop_Min16Ux8,
- False
- );
- goto decode_success;
- }
-
- /* 66 0F 38 3C /r = PMAXSB xmm1, xmm2/m128
- 8Sx16 (signed) max
- 66 0F 38 38 /r = PMINSB xmm1, xmm2/m128
- 8Sx16 (signed) min
- */
- if ( have66noF2noF3( pfx ) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x3C || insn[2] == 0x38)) {
- /* FIXME: this needs an alignment check */
- Bool isMAX = insn[2] == 0x3C;
- delta = dis_SSEint_E_to_G(
- vbi, pfx, delta+3,
- isMAX ? "pmaxsb" : "pminsb",
- isMAX ? Iop_Max8Sx16 : Iop_Min8Sx16,
- False
- );
- goto decode_success;
- }
-
- /* 66 0f 38 20 /r = PMOVSXBW xmm1, xmm2/m64
- Packed Move with Sign Extend from Byte to Word (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x20 ) {
-
- modrm = insn[3];
-
- IRTemp srcVec = newTemp(Ity_V128);
-
- if ( epartIsReg( modrm ) ) {
- assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmovsxbw %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcVec,
- unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) );
- delta += 3+alen;
- DIP( "pmovsxbw %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_SarN16x8,
- binop( Iop_ShlN16x8,
- binop( Iop_InterleaveLO8x16,
- IRExpr_Const( IRConst_V128(0) ),
- mkexpr(srcVec) ),
- mkU8(8) ),
- mkU8(8) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 21 /r = PMOVSXBD xmm1, xmm2/m32
- Packed Move with Sign Extend from Byte to DWord (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x21 ) {
-
- modrm = insn[3];
-
- IRTemp srcVec = newTemp(Ity_V128);
-
- if ( epartIsReg( modrm ) ) {
- assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmovsxbd %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcVec,
- unop( Iop_32UtoV128, loadLE( Ity_I32, mkexpr(addr) ) ) );
- delta += 3+alen;
- DIP( "pmovsxbd %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- IRTemp zeroVec = newTemp(Ity_V128);
- assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_SarN32x4,
- binop( Iop_ShlN32x4,
- binop( Iop_InterleaveLO8x16,
- mkexpr(zeroVec),
- binop( Iop_InterleaveLO8x16,
- mkexpr(zeroVec),
- mkexpr(srcVec) ) ),
- mkU8(24) ), mkU8(24) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 22 /r = PMOVSXBQ xmm1, xmm2/m16
- Packed Move with Sign Extend from Byte to QWord (XMM) */
- if ( have66noF2noF3(pfx)
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x22 ) {
-
- modrm = insn[3];
-
- IRTemp srcBytes = newTemp(Ity_I16);
-
- if ( epartIsReg(modrm) ) {
- assign( srcBytes, getXMMRegLane16( eregOfRexRM(pfx, modrm), 0 ) );
- delta += 3+1;
- DIP( "pmovsxbq %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcBytes, loadLE( Ity_I16, mkexpr(addr) ) );
- delta += 3+alen;
- DIP( "pmovsxbq %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- putXMMReg( gregOfRexRM( pfx, modrm ),
- binop( Iop_64HLtoV128,
- unop( Iop_8Sto64,
- unop( Iop_16HIto8,
- mkexpr(srcBytes) ) ),
- unop( Iop_8Sto64,
- unop( Iop_16to8, mkexpr(srcBytes) ) ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 23 /r = PMOVSXWD xmm1, xmm2/m64
- Packed Move with Sign Extend from Word to DWord (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x23 ) {
-
- modrm = insn[3];
-
- IRTemp srcVec = newTemp(Ity_V128);
-
- if ( epartIsReg(modrm) ) {
- assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmovsxwd %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcVec,
- unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) );
- delta += 3+alen;
- DIP( "pmovsxwd %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_SarN32x4,
- binop( Iop_ShlN32x4,
- binop( Iop_InterleaveLO16x8,
- IRExpr_Const( IRConst_V128(0) ),
- mkexpr(srcVec) ),
- mkU8(16) ),
- mkU8(16) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 24 /r = PMOVSXWQ xmm1, xmm2/m32
- Packed Move with Sign Extend from Word to QWord (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x24 ) {
-
- modrm = insn[3];
-
- IRTemp srcBytes = newTemp(Ity_I32);
-
- if ( epartIsReg( modrm ) ) {
- assign( srcBytes, getXMMRegLane32( eregOfRexRM(pfx, modrm), 0 ) );
- delta += 3+1;
- DIP( "pmovsxwq %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcBytes, loadLE( Ity_I32, mkexpr(addr) ) );
- delta += 3+alen;
- DIP( "pmovsxwq %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- putXMMReg( gregOfRexRM( pfx, modrm ),
- binop( Iop_64HLtoV128,
- unop( Iop_16Sto64,
- unop( Iop_32HIto16, mkexpr(srcBytes) ) ),
- unop( Iop_16Sto64,
- unop( Iop_32to16, mkexpr(srcBytes) ) ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 25 /r = PMOVSXDQ xmm1, xmm2/m64
- Packed Move with Sign Extend from Double Word to Quad Word (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x25 ) {
-
- modrm = insn[3];
-
- IRTemp srcBytes = newTemp(Ity_I64);
-
- if ( epartIsReg(modrm) ) {
- assign( srcBytes, getXMMRegLane64( eregOfRexRM(pfx, modrm), 0 ) );
- delta += 3+1;
- DIP( "pmovsxdq %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcBytes, loadLE( Ity_I64, mkexpr(addr) ) );
- delta += 3+alen;
- DIP( "pmovsxdq %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_64HLtoV128,
- unop( Iop_32Sto64,
- unop( Iop_64HIto32, mkexpr(srcBytes) ) ),
- unop( Iop_32Sto64,
- unop( Iop_64to32, mkexpr(srcBytes) ) ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 30 /r = PMOVZXBW xmm1, xmm2/m64
- Packed Move with Zero Extend from Byte to Word (XMM) */
- if ( have66noF2noF3(pfx)
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x30 ) {
-
- modrm = insn[3];
-
- IRTemp srcVec = newTemp(Ity_V128);
-
- if ( epartIsReg(modrm) ) {
- assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmovzxbw %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcVec,
- unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) );
- delta += 3+alen;
- DIP( "pmovzxbw %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_InterleaveLO8x16,
- IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 31 /r = PMOVZXBD xmm1, xmm2/m32
- Packed Move with Zero Extend from Byte to DWord (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x31 ) {
-
- modrm = insn[3];
-
- IRTemp srcVec = newTemp(Ity_V128);
-
- if ( epartIsReg(modrm) ) {
- assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmovzxbd %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcVec,
- unop( Iop_32UtoV128, loadLE( Ity_I32, mkexpr(addr) ) ) );
- delta += 3+alen;
- DIP( "pmovzxbd %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- IRTemp zeroVec = newTemp(Ity_V128);
- assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
-
- putXMMReg( gregOfRexRM( pfx, modrm ),
- binop( Iop_InterleaveLO8x16,
- mkexpr(zeroVec),
- binop( Iop_InterleaveLO8x16,
- mkexpr(zeroVec), mkexpr(srcVec) ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 32 /r = PMOVZXBQ xmm1, xmm2/m16
- Packed Move with Zero Extend from Byte to QWord (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x32 ) {
-
- modrm = insn[3];
-
- IRTemp srcVec = newTemp(Ity_V128);
-
- if ( epartIsReg(modrm) ) {
- assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmovzxbq %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcVec,
- unop( Iop_32UtoV128,
- unop( Iop_16Uto32, loadLE( Ity_I16, mkexpr(addr) ) ) ) );
- delta += 3+alen;
- DIP( "pmovzxbq %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- IRTemp zeroVec = newTemp(Ity_V128);
- assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
-
- putXMMReg( gregOfRexRM( pfx, modrm ),
- binop( Iop_InterleaveLO8x16,
- mkexpr(zeroVec),
- binop( Iop_InterleaveLO8x16,
- mkexpr(zeroVec),
- binop( Iop_InterleaveLO8x16,
- mkexpr(zeroVec), mkexpr(srcVec) ) ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 33 /r = PMOVZXWD xmm1, xmm2/m64
- Packed Move with Zero Extend from Word to DWord (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x33 ) {
-
- modrm = insn[3];
-
- IRTemp srcVec = newTemp(Ity_V128);
-
- if ( epartIsReg(modrm) ) {
- assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmovzxwd %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcVec,
- unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) );
- delta += 3+alen;
- DIP( "pmovzxwd %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_InterleaveLO16x8,
- IRExpr_Const( IRConst_V128(0) ),
- mkexpr(srcVec) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 34 /r = PMOVZXWQ xmm1, xmm2/m32
- Packed Move with Zero Extend from Word to QWord (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x34 ) {
-
- modrm = insn[3];
-
- IRTemp srcVec = newTemp(Ity_V128);
-
- if ( epartIsReg( modrm ) ) {
- assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmovzxwq %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcVec,
- unop( Iop_32UtoV128, loadLE( Ity_I32, mkexpr(addr) ) ) );
- delta += 3+alen;
- DIP( "pmovzxwq %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- IRTemp zeroVec = newTemp( Ity_V128 );
- assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
-
- putXMMReg( gregOfRexRM( pfx, modrm ),
- binop( Iop_InterleaveLO16x8,
- mkexpr(zeroVec),
- binop( Iop_InterleaveLO16x8,
- mkexpr(zeroVec), mkexpr(srcVec) ) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 35 /r = PMOVZXDQ xmm1, xmm2/m64
- Packed Move with Zero Extend from DWord to QWord (XMM) */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x35 ) {
-
- modrm = insn[3];
-
- IRTemp srcVec = newTemp(Ity_V128);
-
- if ( epartIsReg(modrm) ) {
- assign( srcVec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmovzxdq %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( srcVec,
- unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) );
- delta += 3+alen;
- DIP( "pmovzxdq %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_InterleaveLO32x4,
- IRExpr_Const( IRConst_V128(0) ),
- mkexpr(srcVec) ) );
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 40 /r = PMULLD xmm1, xmm2/m128
- 32x4 integer multiply from xmm2/m128 to xmm1 */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x40 ) {
-
- modrm = insn[3];
-
- IRTemp argL = newTemp(Ity_V128);
- IRTemp argR = newTemp(Ity_V128);
-
- if ( epartIsReg(modrm) ) {
- assign( argL, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "pmulld %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign( argL, loadLE( Ity_V128, mkexpr(addr) ));
- delta += 3+alen;
- DIP( "pmulld %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- assign(argR, getXMMReg( gregOfRexRM(pfx, modrm) ));
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_Mul32x4, mkexpr(argL), mkexpr(argR)) );
-
- goto decode_success;
- }
-
-
- /* F3 0F B8 = POPCNT{W,L,Q}
- Count the number of 1 bits in a register
- */
- if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */
- && insn[0] == 0x0F && insn[1] == 0xB8) {
- vassert(sz == 2 || sz == 4 || sz == 8);
- /*IRType*/ ty = szToITy(sz);
- IRTemp src = newTemp(ty);
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign(src, getIRegE(sz, pfx, modrm));
- delta += 2+1;
- DIP("popcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
- nameIRegG(sz, pfx, modrm));
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0);
- assign(src, loadLE(ty, mkexpr(addr)));
- delta += 2+alen;
- DIP("popcnt%c %s, %s\n", nameISize(sz), dis_buf,
- nameIRegG(sz, pfx, modrm));
- }
-
- IRTemp result = gen_POPCOUNT(ty, src);
- putIRegG(sz, pfx, modrm, mkexpr(result));
-
- // Update flags. This is pretty lame .. perhaps can do better
- // if this turns out to be performance critical.
- // O S A C P are cleared. Z is set if SRC == 0.
- stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
- stmt( IRStmt_Put( OFFB_CC_DEP1,
- binop(Iop_Shl64,
- unop(Iop_1Uto64,
- binop(Iop_CmpEQ64,
- widenUto64(mkexpr(src)),
- mkU64(0))),
- mkU8(AMD64G_CC_SHIFT_Z))));
-
- goto decode_success;
- }
-
-
- /* 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1
- 66 0F 3A 0A /r ib = ROUNDSS imm8, xmm2/m32, xmm1
- */
- if (have66noF2noF3(pfx)
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A
- && (insn[2] == 0x0B || insn[2] == 0x0A)) {
-
- Bool isD = insn[2] == 0x0B;
- IRTemp src = newTemp(isD ? Ity_F64 : Ity_F32);
- IRTemp res = newTemp(isD ? Ity_F64 : Ity_F32);
- Int imm = 0;
-
- modrm = insn[3];
-
- if (epartIsReg(modrm)) {
- assign( src,
- isD ? getXMMRegLane64F( eregOfRexRM(pfx, modrm), 0 )
- : getXMMRegLane32F( eregOfRexRM(pfx, modrm), 0 ) );
- imm = insn[3+1];
- if (imm & ~15) goto decode_failure;
- delta += 3+1+1;
- DIP( "rounds%c $%d,%s,%s\n",
- isD ? 'd' : 's',
- imm, nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( src, loadLE( isD ? Ity_F64 : Ity_F32, mkexpr(addr) ));
- imm = insn[3+alen];
- if (imm & ~15) goto decode_failure;
- delta += 3+alen+1;
- DIP( "rounds%c $%d,%s,%s\n",
- isD ? 'd' : 's',
- imm, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- /* (imm & 3) contains an Intel-encoded rounding mode. Because
- that encoding is the same as the encoding for IRRoundingMode,
- we can use that value directly in the IR as a rounding
- mode. */
- assign(res, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt,
- (imm & 4) ? get_sse_roundingmode()
- : mkU32(imm & 3),
- mkexpr(src)) );
-
- if (isD)
- putXMMRegLane64F( gregOfRexRM(pfx, modrm), 0, mkexpr(res) );
- else
- putXMMRegLane32F( gregOfRexRM(pfx, modrm), 0, mkexpr(res) );
-
- goto decode_success;
- }
-
-
- /* 66 0F 3A 09 /r ib = ROUNDPD imm8, xmm2/m128, xmm1 */
- if (have66noF2noF3(pfx)
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x09) {
-
- IRTemp src0 = newTemp(Ity_F64);
- IRTemp src1 = newTemp(Ity_F64);
- IRTemp res0 = newTemp(Ity_F64);
- IRTemp res1 = newTemp(Ity_F64);
- IRTemp rm = newTemp(Ity_I32);
- Int imm = 0;
-
- modrm = insn[3];
-
- if (epartIsReg(modrm)) {
- assign( src0,
- getXMMRegLane64F( eregOfRexRM(pfx, modrm), 0 ) );
- assign( src1,
- getXMMRegLane64F( eregOfRexRM(pfx, modrm), 1 ) );
- imm = insn[3+1];
- if (imm & ~15) goto decode_failure;
- delta += 3+1+1;
- DIP( "roundpd $%d,%s,%s\n",
- imm, nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned(addr);
- assign( src0, loadLE(Ity_F64,
- binop(Iop_Add64, mkexpr(addr), mkU64(0) )));
- assign( src1, loadLE(Ity_F64,
- binop(Iop_Add64, mkexpr(addr), mkU64(8) )));
- imm = insn[3+alen];
- if (imm & ~15) goto decode_failure;
- delta += 3+alen+1;
- DIP( "roundpd $%d,%s,%s\n",
- imm, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- /* (imm & 3) contains an Intel-encoded rounding mode. Because
- that encoding is the same as the encoding for IRRoundingMode,
- we can use that value directly in the IR as a rounding
- mode. */
- assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
-
- assign(res0, binop(Iop_RoundF64toInt, mkexpr(rm), mkexpr(src0)) );
- assign(res1, binop(Iop_RoundF64toInt, mkexpr(rm), mkexpr(src1)) );
-
- putXMMRegLane64F( gregOfRexRM(pfx, modrm), 0, mkexpr(res0) );
- putXMMRegLane64F( gregOfRexRM(pfx, modrm), 1, mkexpr(res1) );
-
- goto decode_success;
- }
-
-
- /* 66 0F 3A 08 /r ib = ROUNDPS imm8, xmm2/m128, xmm1 */
- if (have66noF2noF3(pfx)
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x08) {
-
- IRTemp src0 = newTemp(Ity_F32);
- IRTemp src1 = newTemp(Ity_F32);
- IRTemp src2 = newTemp(Ity_F32);
- IRTemp src3 = newTemp(Ity_F32);
- IRTemp res0 = newTemp(Ity_F32);
- IRTemp res1 = newTemp(Ity_F32);
- IRTemp res2 = newTemp(Ity_F32);
- IRTemp res3 = newTemp(Ity_F32);
- IRTemp rm = newTemp(Ity_I32);
- Int imm = 0;
-
- modrm = insn[3];
-
- if (epartIsReg(modrm)) {
- assign( src0,
- getXMMRegLane32F( eregOfRexRM(pfx, modrm), 0 ) );
- assign( src1,
- getXMMRegLane32F( eregOfRexRM(pfx, modrm), 1 ) );
- assign( src2,
- getXMMRegLane32F( eregOfRexRM(pfx, modrm), 2 ) );
- assign( src3,
- getXMMRegLane32F( eregOfRexRM(pfx, modrm), 3 ) );
- imm = insn[3+1];
- if (imm & ~15) goto decode_failure;
- delta += 3+1+1;
- DIP( "roundps $%d,%s,%s\n",
- imm, nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned(addr);
- assign( src0, loadLE(Ity_F32,
- binop(Iop_Add64, mkexpr(addr), mkU64(0) )));
- assign( src1, loadLE(Ity_F32,
- binop(Iop_Add64, mkexpr(addr), mkU64(4) )));
- assign( src2, loadLE(Ity_F32,
- binop(Iop_Add64, mkexpr(addr), mkU64(8) )));
- assign( src3, loadLE(Ity_F32,
- binop(Iop_Add64, mkexpr(addr), mkU64(12) )));
- imm = insn[3+alen];
- if (imm & ~15) goto decode_failure;
- delta += 3+alen+1;
- DIP( "roundps $%d,%s,%s\n",
- imm, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- /* (imm & 3) contains an Intel-encoded rounding mode. Because
- that encoding is the same as the encoding for IRRoundingMode,
- we can use that value directly in the IR as a rounding
- mode. */
- assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
-
- assign(res0, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src0)) );
- assign(res1, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src1)) );
- assign(res2, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src2)) );
- assign(res3, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src3)) );
-
- putXMMRegLane32F( gregOfRexRM(pfx, modrm), 0, mkexpr(res0) );
- putXMMRegLane32F( gregOfRexRM(pfx, modrm), 1, mkexpr(res1) );
- putXMMRegLane32F( gregOfRexRM(pfx, modrm), 2, mkexpr(res2) );
- putXMMRegLane32F( gregOfRexRM(pfx, modrm), 3, mkexpr(res3) );
-
- goto decode_success;
- }
-
-
- /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension,
- which we can only decode if we're sure this is an AMD cpu that
- supports LZCNT, since otherwise it's BSR, which behaves
- differently. */
- if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */
- && insn[0] == 0x0F && insn[1] == 0xBD
- && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT)) {
- vassert(sz == 2 || sz == 4 || sz == 8);
- /*IRType*/ ty = szToITy(sz);
- IRTemp src = newTemp(ty);
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- assign(src, getIRegE(sz, pfx, modrm));
- delta += 2+1;
- DIP("lzcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
- nameIRegG(sz, pfx, modrm));
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0);
- assign(src, loadLE(ty, mkexpr(addr)));
- delta += 2+alen;
- DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf,
- nameIRegG(sz, pfx, modrm));
- }
-
- IRTemp res = gen_LZCNT(ty, src);
- putIRegG(sz, pfx, modrm, mkexpr(res));
-
- // Update flags. This is pretty lame .. perhaps can do better
- // if this turns out to be performance critical.
- // O S A P are cleared. Z is set if RESULT == 0.
- // C is set if SRC is zero.
- IRTemp src64 = newTemp(Ity_I64);
- IRTemp res64 = newTemp(Ity_I64);
- assign(src64, widenUto64(mkexpr(src)));
- assign(res64, widenUto64(mkexpr(res)));
-
- IRTemp oszacp = newTemp(Ity_I64);
- assign(
- oszacp,
- binop(Iop_Or64,
+ // Update flags. This is pretty lame .. perhaps can do better
+ // if this turns out to be performance critical.
+ // O S A C P are cleared. Z is set if SRC == 0.
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1,
binop(Iop_Shl64,
unop(Iop_1Uto64,
- binop(Iop_CmpEQ64, mkexpr(res64), mkU64(0))),
- mkU8(AMD64G_CC_SHIFT_Z)),
- binop(Iop_Shl64,
- unop(Iop_1Uto64,
- binop(Iop_CmpEQ64, mkexpr(src64), mkU64(0))),
- mkU8(AMD64G_CC_SHIFT_C))
- )
- );
+ binop(Iop_CmpEQ64,
+ widenUto64(mkexpr(src)),
+ mkU64(0))),
+ mkU8(AMD64G_CC_SHIFT_Z))));
- stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
- stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) ));
+ goto decode_success;
+ }
+ break;
- goto decode_success;
+ case 0xBD:
+ /* F3 0F BD -- LZCNT (count leading zeroes. An AMD extension,
+ which we can only decode if we're sure this is an AMD cpu
+ that supports LZCNT, since otherwise it's BSR, which behaves
+ differently. Bizarrely, my Sandy Bridge also accepts these
+ instructions but produces different results. */
+ if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */
+ && (sz == 2 || sz == 4 || sz == 8)
+ && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT)) {
+ /*IRType*/ ty = szToITy(sz);
+ IRTemp src = newTemp(ty);
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ assign(src, getIRegE(sz, pfx, modrm));
+ delta += 1;
+ DIP("lzcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
+ nameIRegG(sz, pfx, modrm));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0);
+ assign(src, loadLE(ty, mkexpr(addr)));
+ delta += alen;
+ DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf,
+ nameIRegG(sz, pfx, modrm));
+ }
+
+ IRTemp res = gen_LZCNT(ty, src);
+ putIRegG(sz, pfx, modrm, mkexpr(res));
+
+ // Update flags. This is pretty lame .. perhaps can do better
+ // if this turns out to be performance critical.
+ // O S A P are cleared. Z is set if RESULT == 0.
+ // C is set if SRC is zero.
+ IRTemp src64 = newTemp(Ity_I64);
+ IRTemp res64 = newTemp(Ity_I64);
+ assign(src64, widenUto64(mkexpr(src)));
+ assign(res64, widenUto64(mkexpr(res)));
+
+ IRTemp oszacp = newTemp(Ity_I64);
+ assign(
+ oszacp,
+ binop(Iop_Or64,
+ binop(Iop_Shl64,
+ unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64, mkexpr(res64), mkU64(0))),
+ mkU8(AMD64G_CC_SHIFT_Z)),
+ binop(Iop_Shl64,
+ unop(Iop_1Uto64,
+ binop(Iop_CmpEQ64, mkexpr(src64), mkU64(0))),
+ mkU8(AMD64G_CC_SHIFT_C))
+ )
+ );
+
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) ));
+
+ goto decode_success;
+ }
+ break;
+
+ default:
+ break;
+
}
- /* 66 0F 3A 63 /r ib = PCMPISTRI imm8, xmm2/m128, xmm1
- 66 0F 3A 62 /r ib = PCMPISTRM imm8, xmm2/m128, xmm1
- 66 0F 3A 61 /r ib = PCMPESTRI imm8, xmm2/m128, xmm1
- 66 0F 3A 60 /r ib = PCMPESTRM imm8, xmm2/m128, xmm1
- (selected special cases that actually occur in glibc,
- not by any means a complete implementation.)
+ //decode_failure:
+ *decode_OK = False;
+ return deltaIN;
+
+ decode_success:
+ *decode_OK = True;
+ return delta;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level SSE4: dis_ESC_0F38__SSE4 ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+static IRTemp math_PBLENDVB_128 ( IRTemp vecE, IRTemp vecG,
+ IRTemp vec0/*controlling mask*/,
+ UInt gran, IROp opSAR )
+{
+ /* The tricky bit is to convert vec0 into a suitable mask, by
+ copying the most significant bit of each lane into all positions
+ in the lane. */
+ IRTemp sh = newTemp(Ity_I8);
+ assign(sh, mkU8(8 * gran - 1));
+
+ IRTemp mask = newTemp(Ity_V128);
+ assign(mask, binop(opSAR, mkexpr(vec0), mkexpr(sh)));
+
+ IRTemp notmask = newTemp(Ity_V128);
+ assign(notmask, unop(Iop_NotV128, mkexpr(mask)));
+
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_OrV128,
+ binop(Iop_AndV128, mkexpr(vecE), mkexpr(mask)),
+ binop(Iop_AndV128, mkexpr(vecG), mkexpr(notmask))));
+ return res;
+}
+
+static IRTemp math_PBLENDVB_256 ( IRTemp vecE, IRTemp vecG,
+ IRTemp vec0/*controlling mask*/,
+ UInt gran, IROp opSAR128 )
+{
+ /* The tricky bit is to convert vec0 into a suitable mask, by
+ copying the most significant bit of each lane into all positions
+ in the lane. */
+ IRTemp sh = newTemp(Ity_I8);
+ assign(sh, mkU8(8 * gran - 1));
+
+ IRTemp vec0Hi = IRTemp_INVALID;
+ IRTemp vec0Lo = IRTemp_INVALID;
+ breakupV256toV128s( vec0, &vec0Hi, &vec0Lo );
+
+ IRTemp mask = newTemp(Ity_V256);
+ assign(mask, binop(Iop_V128HLtoV256,
+ binop(opSAR128, mkexpr(vec0Hi), mkexpr(sh)),
+ binop(opSAR128, mkexpr(vec0Lo), mkexpr(sh))));
+
+ IRTemp notmask = newTemp(Ity_V256);
+ assign(notmask, unop(Iop_NotV256, mkexpr(mask)));
+
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_OrV256,
+ binop(Iop_AndV256, mkexpr(vecE), mkexpr(mask)),
+ binop(Iop_AndV256, mkexpr(vecG), mkexpr(notmask))));
+ return res;
+}
+
+static Long dis_VBLENDV_128 ( VexAbiInfo* vbi, Prefix pfx, Long delta,
+ const HChar *name, UInt gran, IROp opSAR )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ UInt rIS4 = 0xFF; /* invalid */
+ IRTemp vecE = newTemp(Ity_V128);
+ IRTemp vecV = newTemp(Ity_V128);
+ IRTemp vecIS4 = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) {
+ delta++;
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign(vecE, getXMMReg(rE));
+ UChar ib = getUChar(delta);
+ rIS4 = (ib >> 4) & 0xF;
+ DIP("%s %s,%s,%s,%s\n",
+ name, nameXMMReg(rIS4), nameXMMReg(rE),
+ nameXMMReg(rV), nameXMMReg(rG));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ assign(vecE, loadLE(Ity_V128, mkexpr(addr)));
+ UChar ib = getUChar(delta);
+ rIS4 = (ib >> 4) & 0xF;
+ DIP("%s %s,%s,%s,%s\n",
+ name, nameXMMReg(rIS4), dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ }
+ delta++;
+ assign(vecV, getXMMReg(rV));
+ assign(vecIS4, getXMMReg(rIS4));
+ IRTemp res = math_PBLENDVB_128( vecE, vecV, vecIS4, gran, opSAR );
+ putYMMRegLoAndZU( rG, mkexpr(res) );
+ return delta;
+}
+
+static Long dis_VBLENDV_256 ( VexAbiInfo* vbi, Prefix pfx, Long delta,
+ const HChar *name, UInt gran, IROp opSAR128 )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ UInt rIS4 = 0xFF; /* invalid */
+ IRTemp vecE = newTemp(Ity_V256);
+ IRTemp vecV = newTemp(Ity_V256);
+ IRTemp vecIS4 = newTemp(Ity_V256);
+ if (epartIsReg(modrm)) {
+ delta++;
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign(vecE, getYMMReg(rE));
+ UChar ib = getUChar(delta);
+ rIS4 = (ib >> 4) & 0xF;
+ DIP("%s %s,%s,%s,%s\n",
+ name, nameYMMReg(rIS4), nameYMMReg(rE),
+ nameYMMReg(rV), nameYMMReg(rG));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ assign(vecE, loadLE(Ity_V256, mkexpr(addr)));
+ UChar ib = getUChar(delta);
+ rIS4 = (ib >> 4) & 0xF;
+ DIP("%s %s,%s,%s,%s\n",
+ name, nameYMMReg(rIS4), dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ }
+ delta++;
+ assign(vecV, getYMMReg(rV));
+ assign(vecIS4, getYMMReg(rIS4));
+ IRTemp res = math_PBLENDVB_256( vecE, vecV, vecIS4, gran, opSAR128 );
+ putYMMReg( rG, mkexpr(res) );
+ return delta;
+}
+
+static void finish_xTESTy ( IRTemp andV, IRTemp andnV, Int sign )
+{
+ /* Set Z=1 iff (vecE & vecG) == 0
+ Set C=1 iff (vecE & not vecG) == 0
*/
- if (have66noF2noF3(pfx)
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x3A
- && (insn[2] >= 0x60 && insn[2] <= 0x63)) {
- UInt isISTRx = insn[2] & 2;
- UInt isxSTRM = (insn[2] & 1) ^ 1;
- UInt regNoL = 0;
- UInt regNoR = 0;
- UChar imm = 0;
+ /* andV, andnV: vecE & vecG, vecE and not(vecG) */
- /* This is a nasty kludge. We need to pass 2 x V128 to the
- helper (which is clean). Since we can't do that, use a dirty
- helper to compute the results directly from the XMM regs in
- the guest state. That means for the memory case, we need to
- move the left operand into a pseudo-register (XMM16, let's
- call it). */
- modrm = insn[3];
- if (epartIsReg(modrm)) {
- regNoL = eregOfRexRM(pfx, modrm);
- regNoR = gregOfRexRM(pfx, modrm);
- imm = insn[3+1];
- delta += 3+1+1;
- } else {
- regNoL = 16; /* use XMM16 as an intermediary */
- regNoR = gregOfRexRM(pfx, modrm);
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- /* No alignment check; I guess that makes sense, given that
- these insns are for dealing with C style strings. */
- stmt( IRStmt_Put( OFFB_XMM16, loadLE(Ity_V128, mkexpr(addr)) ));
- imm = insn[3+alen];
- delta += 3+alen+1;
+ /* andV resp. andnV, reduced to 64-bit values, by or-ing the top
+ and bottom 64-bits together. It relies on this trick:
+
+ InterleaveLO64x2([a,b],[c,d]) == [b,d] hence
+
+ InterleaveLO64x2([a,b],[a,b]) == [b,b] and similarly
+ InterleaveHI64x2([a,b],[a,b]) == [a,a]
+
+ and so the OR of the above 2 exprs produces
+ [a OR b, a OR b], from which we simply take the lower half.
+ */
+ IRTemp and64 = newTemp(Ity_I64);
+ IRTemp andn64 = newTemp(Ity_I64);
+
+ assign(and64,
+ unop(Iop_V128to64,
+ binop(Iop_OrV128,
+ binop(Iop_InterleaveLO64x2,
+ mkexpr(andV), mkexpr(andV)),
+ binop(Iop_InterleaveHI64x2,
+ mkexpr(andV), mkexpr(andV)))));
+
+ assign(andn64,
+ unop(Iop_V128to64,
+ binop(Iop_OrV128,
+ binop(Iop_InterleaveLO64x2,
+ mkexpr(andnV), mkexpr(andnV)),
+ binop(Iop_InterleaveHI64x2,
+ mkexpr(andnV), mkexpr(andnV)))));
+
+ IRTemp z64 = newTemp(Ity_I64);
+ IRTemp c64 = newTemp(Ity_I64);
+ if (sign == 64) {
+ /* When only interested in the most significant bit, just shift
+ arithmetically right and negate. */
+ assign(z64,
+ unop(Iop_Not64,
+ binop(Iop_Sar64, mkexpr(and64), mkU8(63))));
+
+ assign(c64,
+ unop(Iop_Not64,
+ binop(Iop_Sar64, mkexpr(andn64), mkU8(63))));
+ } else {
+ if (sign == 32) {
+ /* When interested in bit 31 and bit 63, mask those bits and
+ fallthrough into the PTEST handling. */
+ IRTemp t0 = newTemp(Ity_I64);
+ IRTemp t1 = newTemp(Ity_I64);
+ IRTemp t2 = newTemp(Ity_I64);
+ assign(t0, mkU64(0x8000000080000000ULL));
+ assign(t1, binop(Iop_And64, mkexpr(and64), mkexpr(t0)));
+ assign(t2, binop(Iop_And64, mkexpr(andn64), mkexpr(t0)));
+ and64 = t1;
+ andn64 = t2;
}
-
- /* Now we know the XMM reg numbers for the operands, and the
- immediate byte. Is it one we can actually handle? Throw out
- any cases for which the helper function has not been
- verified. */
- switch (imm) {
- case 0x00:
- case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
- case 0x1A: case 0x38: case 0x3A: case 0x44: case 0x4A:
- break;
- default:
- goto decode_failure;
- }
-
- /* Who ya gonna call? Presumably not Ghostbusters. */
- void* fn = &amd64g_dirtyhelper_PCMPxSTRx;
- HChar* nm = "amd64g_dirtyhelper_PCMPxSTRx";
-
- /* Round up the arguments. Note that this is a kludge -- the
- use of mkU64 rather than mkIRExpr_HWord implies the
- assumption that the host's word size is 64-bit. */
- UInt gstOffL = regNoL == 16 ? OFFB_XMM16 : xmmGuestRegOffset(regNoL);
- UInt gstOffR = xmmGuestRegOffset(regNoR);
-
- IRExpr* opc4_and_imm = mkU64((insn[2] << 8) | (imm & 0xFF));
- IRExpr* gstOffLe = mkU64(gstOffL);
- IRExpr* gstOffRe = mkU64(gstOffR);
- IRExpr* edxIN = isISTRx ? mkU64(0) : getIRegRDX(8);
- IRExpr* eaxIN = isISTRx ? mkU64(0) : getIRegRAX(8);
- IRExpr** args
- = mkIRExprVec_5( opc4_and_imm, gstOffLe, gstOffRe, edxIN, eaxIN );
-
- IRTemp resT = newTemp(Ity_I64);
- IRDirty* d = unsafeIRDirty_1_N( resT, 0/*regparms*/, nm, fn, args );
- /* It's not really a dirty call, but we can't use the clean
- helper mechanism here for the very lame reason that we can't
- pass 2 x V128s by value to a helper, nor get one back. Hence
- this roundabout scheme. */
- d->needsBBP = True;
- d->nFxState = 2;
- d->fxState[0].fx = Ifx_Read;
- d->fxState[0].offset = gstOffL;
- d->fxState[0].size = sizeof(U128);
- d->fxState[1].fx = Ifx_Read;
- d->fxState[1].offset = gstOffR;
- d->fxState[1].size = sizeof(U128);
- if (isxSTRM) {
- /* Declare that the helper writes XMM0. */
- d->nFxState = 3;
- d->fxState[2].fx = Ifx_Write;
- d->fxState[2].offset = xmmGuestRegOffset(0);
- d->fxState[2].size = sizeof(U128);
- }
-
- stmt( IRStmt_Dirty(d) );
-
- /* Now resT[15:0] holds the new OSZACP values, so the condition
- codes must be updated. And for a xSTRI case, resT[31:16]
- holds the new ECX value, so stash that too. */
- if (!isxSTRM) {
- putIReg64(R_RCX, binop(Iop_And64,
- binop(Iop_Shr64, mkexpr(resT), mkU8(16)),
- mkU64(0xFFFF)));
- }
-
- stmt( IRStmt_Put(
- OFFB_CC_DEP1,
- binop(Iop_And64, mkexpr(resT), mkU64(0xFFFF))
- ));
- stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
-
- if (regNoL == 16) {
- DIP("pcmp%cstr%c $%x,%s,%s\n",
- isISTRx ? 'i' : 'e', isxSTRM ? 'm' : 'i',
- (UInt)imm, dis_buf, nameXMMReg(regNoR));
- } else {
- DIP("pcmp%cstr%c $%x,%s,%s\n",
- isISTRx ? 'i' : 'e', isxSTRM ? 'm' : 'i',
- (UInt)imm, nameXMMReg(regNoL), nameXMMReg(regNoR));
- }
-
- goto decode_success;
- }
-
-
- /* 66 0f 38 17 /r = PTEST xmm1, xmm2/m128
- Logical compare (set ZF and CF from AND/ANDN of the operands) */
- if (have66noF2noF3( pfx )
- && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x17) {
- modrm = insn[3];
- IRTemp vecE = newTemp(Ity_V128);
- IRTemp vecG = newTemp(Ity_V128);
-
- if ( epartIsReg(modrm) ) {
- assign(vecE, getXMMReg(eregOfRexRM(pfx, modrm)));
- delta += 3+1;
- DIP( "ptest %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign(vecE, loadLE( Ity_V128, mkexpr(addr) ));
- delta += 3+alen;
- DIP( "ptest %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- assign(vecG, getXMMReg(gregOfRexRM(pfx, modrm)));
-
- /* Set Z=1 iff (vecE & vecG) == 0
- Set C=1 iff (vecE & not vecG) == 0
- */
-
- /* andV, andnV: vecE & vecG, vecE and not(vecG) */
- IRTemp andV = newTemp(Ity_V128);
- IRTemp andnV = newTemp(Ity_V128);
- assign(andV, binop(Iop_AndV128, mkexpr(vecE), mkexpr(vecG)));
- assign(andnV, binop(Iop_AndV128,
- mkexpr(vecE),
- binop(Iop_XorV128, mkexpr(vecG),
- mkV128(0xFFFF))));
-
- /* The same, but reduced to 64-bit values, by or-ing the top
- and bottom 64-bits together. It relies on this trick:
-
- InterleaveLO64x2([a,b],[c,d]) == [b,d] hence
-
- InterleaveLO64x2([a,b],[a,b]) == [b,b] and similarly
- InterleaveHI64x2([a,b],[a,b]) == [a,a]
-
- and so the OR of the above 2 exprs produces
- [a OR b, a OR b], from which we simply take the lower half.
- */
- IRTemp and64 = newTemp(Ity_I64);
- IRTemp andn64 = newTemp(Ity_I64);
-
- assign(
- and64,
- unop(Iop_V128to64,
- binop(Iop_OrV128,
- binop(Iop_InterleaveLO64x2, mkexpr(andV), mkexpr(andV)),
- binop(Iop_InterleaveHI64x2, mkexpr(andV), mkexpr(andV))
- )
- )
- );
-
- assign(
- andn64,
- unop(Iop_V128to64,
- binop(Iop_OrV128,
- binop(Iop_InterleaveLO64x2, mkexpr(andnV), mkexpr(andnV)),
- binop(Iop_InterleaveHI64x2, mkexpr(andnV), mkexpr(andnV))
- )
- )
- );
-
/* Now convert and64, andn64 to all-zeroes or all-1s, so we can
slice out the Z and C bits conveniently. We use the standard
trick all-zeroes -> all-zeroes, anything-else -> all-ones
done by "(x | -x) >>s (word-size - 1)".
*/
- IRTemp z64 = newTemp(Ity_I64);
- IRTemp c64 = newTemp(Ity_I64);
assign(z64,
unop(Iop_Not64,
binop(Iop_Sar64,
binop(Iop_Or64,
binop(Iop_Sub64, mkU64(0), mkexpr(and64)),
- mkexpr(and64)
- ),
- mkU8(63)))
- );
+ mkexpr(and64)), mkU8(63))));
assign(c64,
unop(Iop_Not64,
binop(Iop_Sar64,
binop(Iop_Or64,
binop(Iop_Sub64, mkU64(0), mkexpr(andn64)),
- mkexpr(andn64)
- ),
- mkU8(63)))
- );
-
- /* And finally, slice out the Z and C flags and set the flags
- thunk to COPY for them. OSAP are set to zero. */
- IRTemp newOSZACP = newTemp(Ity_I64);
- assign(newOSZACP,
- binop(Iop_Or64,
- binop(Iop_And64, mkexpr(z64), mkU64(AMD64G_CC_MASK_Z)),
- binop(Iop_And64, mkexpr(c64), mkU64(AMD64G_CC_MASK_C))
- )
- );
-
- stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(newOSZACP)));
- stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
-
- goto decode_success;
+ mkexpr(andn64)), mkU8(63))));
}
- /* 66 0F 38 15 /r = BLENDVPD xmm1, xmm2/m128 (double gran)
- 66 0F 38 14 /r = BLENDVPS xmm1, xmm2/m128 (float gran)
- 66 0F 38 10 /r = PBLENDVB xmm1, xmm2/m128 (byte gran)
- Blend at various granularities, with XMM0 (implicit operand)
- providing the controlling mask.
- */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0x15 || insn[2] == 0x14 || insn[2] == 0x10)) {
- modrm = insn[3];
+ /* And finally, slice out the Z and C flags and set the flags
+ thunk to COPY for them. OSAP are set to zero. */
+ IRTemp newOSZACP = newTemp(Ity_I64);
+ assign(newOSZACP,
+ binop(Iop_Or64,
+ binop(Iop_And64, mkexpr(z64), mkU64(AMD64G_CC_MASK_Z)),
+ binop(Iop_And64, mkexpr(c64), mkU64(AMD64G_CC_MASK_C))));
- HChar* nm = NULL;
- UInt gran = 0;
- IROp opSAR = Iop_INVALID;
- switch (insn[2]) {
- case 0x15:
- nm = "blendvpd"; gran = 8; opSAR = Iop_SarN64x2;
- break;
- case 0x14:
- nm = "blendvps"; gran = 4; opSAR = Iop_SarN32x4;
- break;
- case 0x10:
- nm = "pblendvb"; gran = 1; opSAR = Iop_SarN8x16;
- break;
- }
- vassert(nm);
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(newOSZACP)));
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+}
- IRTemp vecE = newTemp(Ity_V128);
- IRTemp vecG = newTemp(Ity_V128);
- IRTemp vec0 = newTemp(Ity_V128);
- if ( epartIsReg(modrm) ) {
- assign(vecE, getXMMReg(eregOfRexRM(pfx, modrm)));
- delta += 3+1;
- DIP( "%s %s,%s\n", nm,
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
+/* Handles 128 bit versions of PTEST, VTESTPS or VTESTPD.
+ sign is 0 for PTEST insn, 32 for VTESTPS and 64 for VTESTPD. */
+static Long dis_xTESTy_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, Int sign )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp vecE = newTemp(Ity_V128);
+ IRTemp vecG = newTemp(Ity_V128);
+
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign(vecE, getXMMReg(rE));
+ delta += 1;
+ DIP( "%s%stest%s %s,%s\n",
+ isAvx ? "v" : "", sign == 0 ? "p" : "",
+ sign == 0 ? "" : sign == 32 ? "ps" : "pd",
+ nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ if (!isAvx)
gen_SEGV_if_not_16_aligned( addr );
- assign(vecE, loadLE( Ity_V128, mkexpr(addr) ));
- delta += 3+alen;
- DIP( "%s %s,%s\n", nm,
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- assign(vecG, getXMMReg(gregOfRexRM(pfx, modrm)));
- assign(vec0, getXMMReg(0));
-
- /* Now the tricky bit is to convert vec0 into a suitable mask,
- by copying the most significant bit of each lane into all
- positions in the lane. */
- IRTemp sh = newTemp(Ity_I8);
- assign(sh, mkU8(8 * gran - 1));
-
- IRTemp mask = newTemp(Ity_V128);
- assign(mask, binop(opSAR, mkexpr(vec0), mkexpr(sh)));
-
- IRTemp notmask = newTemp(Ity_V128);
- assign(notmask, unop(Iop_NotV128, mkexpr(mask)));
-
- IRExpr* res = binop(Iop_OrV128,
- binop(Iop_AndV128, mkexpr(vecE), mkexpr(mask)),
- binop(Iop_AndV128, mkexpr(vecG), mkexpr(notmask)));
- putXMMReg(gregOfRexRM(pfx, modrm), res);
-
- goto decode_success;
+ assign(vecE, loadLE( Ity_V128, mkexpr(addr) ));
+ delta += alen;
+ DIP( "%s%stest%s %s,%s\n",
+ isAvx ? "v" : "", sign == 0 ? "p" : "",
+ sign == 0 ? "" : sign == 32 ? "ps" : "pd",
+ dis_buf, nameXMMReg(rG) );
}
- /* F2 0F 38 F0 /r = CRC32 r/m8, r32 (REX.W ok, 66 not ok)
- F2 0F 38 F1 /r = CRC32 r/m{16,32,64}, r32
- The decoding on this is a bit unusual.
+ assign(vecG, getXMMReg(rG));
+
+ /* Set Z=1 iff (vecE & vecG) == 0
+ Set C=1 iff (vecE & not vecG) == 0
*/
- if (haveF2noF3(pfx)
- && insn[0] == 0x0F && insn[1] == 0x38
- && (insn[2] == 0xF1
- || (insn[2] == 0xF0 && !have66(pfx)))) {
- modrm = insn[3];
- if (insn[2] == 0xF0)
- sz = 1;
- else
- vassert(sz == 2 || sz == 4 || sz == 8);
+ /* andV, andnV: vecE & vecG, vecE and not(vecG) */
+ IRTemp andV = newTemp(Ity_V128);
+ IRTemp andnV = newTemp(Ity_V128);
+ assign(andV, binop(Iop_AndV128, mkexpr(vecE), mkexpr(vecG)));
+ assign(andnV, binop(Iop_AndV128,
+ mkexpr(vecE),
+ binop(Iop_XorV128, mkexpr(vecG),
+ mkV128(0xFFFF))));
- IRType tyE = szToITy(sz);
- IRTemp valE = newTemp(tyE);
+ finish_xTESTy ( andV, andnV, sign );
+ return delta;
+}
- if (epartIsReg(modrm)) {
- assign(valE, getIRegE(sz, pfx, modrm));
- delta += 3+1;
- DIP("crc32b %s,%s\n", nameIRegE(sz, pfx, modrm),
- nameIRegG(1==getRexW(pfx) ? 8 : 4 ,pfx, modrm));
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign(valE, loadLE(tyE, mkexpr(addr)));
- delta += 3+alen;
- DIP("crc32b %s,%s\n", dis_buf,
- nameIRegG(1==getRexW(pfx) ? 8 : 4 ,pfx, modrm));
- }
- /* Somewhat funny getting/putting of the crc32 value, in order
- to ensure that it turns into 64-bit gets and puts. However,
- mask off the upper 32 bits so as to not get memcheck false
- +ves around the helper call. */
- IRTemp valG0 = newTemp(Ity_I64);
- assign(valG0, binop(Iop_And64, getIRegG(8, pfx, modrm),
- mkU64(0xFFFFFFFF)));
+/* Handles 256 bit versions of PTEST, VTESTPS or VTESTPD.
+ sign is 0 for PTEST insn, 32 for VTESTPS and 64 for VTESTPD. */
+static Long dis_xTESTy_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Int sign )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp vecE = newTemp(Ity_V256);
+ IRTemp vecG = newTemp(Ity_V256);
- HChar* nm = NULL;
- void* fn = NULL;
- switch (sz) {
- case 1: nm = "amd64g_calc_crc32b";
- fn = &amd64g_calc_crc32b; break;
- case 2: nm = "amd64g_calc_crc32w";
- fn = &amd64g_calc_crc32w; break;
- case 4: nm = "amd64g_calc_crc32l";
- fn = &amd64g_calc_crc32l; break;
- case 8: nm = "amd64g_calc_crc32q";
- fn = &amd64g_calc_crc32q; break;
- }
- vassert(nm && fn);
- IRTemp valG1 = newTemp(Ity_I64);
- assign(valG1,
- mkIRExprCCall(Ity_I64, 0/*regparm*/, nm, fn,
- mkIRExprVec_2(mkexpr(valG0),
- widenUto64(mkexpr(valE)))));
-
- putIRegG(4, pfx, modrm, unop(Iop_64to32, mkexpr(valG1)));
- goto decode_success;
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign(vecE, getYMMReg(rE));
+ delta += 1;
+ DIP( "v%stest%s %s,%s\n", sign == 0 ? "p" : "",
+ sign == 0 ? "" : sign == 32 ? "ps" : "pd",
+ nameYMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(vecE, loadLE( Ity_V256, mkexpr(addr) ));
+ delta += alen;
+ DIP( "v%stest%s %s,%s\n", sign == 0 ? "p" : "",
+ sign == 0 ? "" : sign == 32 ? "ps" : "pd",
+ dis_buf, nameYMMReg(rG) );
}
- /* 66 0f 38 2B /r = PACKUSDW xmm1, xmm2/m128
- 2x 32x4 S->U saturating narrow from xmm2/m128 to xmm1 */
- if ( have66noF2noF3( pfx )
- && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x2B ) {
-
- modrm = insn[3];
+ assign(vecG, getYMMReg(rG));
- IRTemp argL = newTemp(Ity_V128);
- IRTemp argR = newTemp(Ity_V128);
-
- if ( epartIsReg(modrm) ) {
- assign( argL, getXMMReg( eregOfRexRM(pfx, modrm) ) );
- delta += 3+1;
- DIP( "packusdw %s,%s\n",
- nameXMMReg( eregOfRexRM(pfx, modrm) ),
- nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- } else {
- addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- gen_SEGV_if_not_16_aligned( addr );
- assign( argL, loadLE( Ity_V128, mkexpr(addr) ));
- delta += 3+alen;
- DIP( "packusdw %s,%s\n",
- dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
- }
-
- assign(argR, getXMMReg( gregOfRexRM(pfx, modrm) ));
-
- putXMMReg( gregOfRexRM(pfx, modrm),
- binop( Iop_QNarrowBin32Sto16Ux8,
- mkexpr(argL), mkexpr(argR)) );
-
- goto decode_success;
- }
-
- /* 66 0F 38 28 = PMULUDQ -- signed widening multiply of 32-lanes 0 x
- 0 to form lower 64-bit half and lanes 2 x 2 to form upper 64-bit
- half */
- /* This is a really poor translation -- could be improved if
- performance critical. It's a copy-paste of PMULDQ, too. */
- if (have66noF2noF3(pfx) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x28) {
- IRTemp sV, dV;
- IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
- sV = newTemp(Ity_V128);
- dV = newTemp(Ity_V128);
- s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
- t1 = newTemp(Ity_I64);
- t0 = newTemp(Ity_I64);
- modrm = insn[3];
- assign( dV, getXMMReg(gregOfRexRM(pfx,modrm)) );
-
- if (epartIsReg(modrm)) {
- assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
- delta += 3+1;
- DIP("pmuldq %s,%s\n", nameXMMReg(eregOfRexRM(pfx,modrm)),
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta+3, dis_buf, 0 );
- assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
- delta += 3+alen;
- DIP("pmuldq %s,%s\n", dis_buf,
- nameXMMReg(gregOfRexRM(pfx,modrm)));
- }
-
- breakup128to32s( dV, &d3, &d2, &d1, &d0 );
- breakup128to32s( sV, &s3, &s2, &s1, &s0 );
-
- assign( t0, binop( Iop_MullS32, mkexpr(d0), mkexpr(s0)) );
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 0, mkexpr(t0) );
- assign( t1, binop( Iop_MullS32, mkexpr(d2), mkexpr(s2)) );
- putXMMRegLane64( gregOfRexRM(pfx,modrm), 1, mkexpr(t1) );
- goto decode_success;
- }
-
- /* 66 0F 38 29 = PCMPEQQ
- 64x2 equality comparison
+ /* Set Z=1 iff (vecE & vecG) == 0
+ Set C=1 iff (vecE & not vecG) == 0
*/
- if ( have66noF2noF3( pfx ) && sz == 2
- && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x29) {
- /* FIXME: this needs an alignment check */
- delta = dis_SSEint_E_to_G( vbi, pfx, delta+3,
- "pcmpeqq", Iop_CmpEQ64x2, False );
- goto decode_success;
+
+ /* andV, andnV: vecE & vecG, vecE and not(vecG) */
+ IRTemp andV = newTemp(Ity_V256);
+ IRTemp andnV = newTemp(Ity_V256);
+ assign(andV, binop(Iop_AndV256, mkexpr(vecE), mkexpr(vecG)));
+ assign(andnV, binop(Iop_AndV256,
+ mkexpr(vecE), unop(Iop_NotV256, mkexpr(vecG))));
+
+ IRTemp andVhi = IRTemp_INVALID;
+ IRTemp andVlo = IRTemp_INVALID;
+ IRTemp andnVhi = IRTemp_INVALID;
+ IRTemp andnVlo = IRTemp_INVALID;
+ breakupV256toV128s( andV, &andVhi, &andVlo );
+ breakupV256toV128s( andnV, &andnVhi, &andnVlo );
+
+ IRTemp andV128 = newTemp(Ity_V128);
+ IRTemp andnV128 = newTemp(Ity_V128);
+ assign( andV128, binop( Iop_OrV128, mkexpr(andVhi), mkexpr(andVlo) ) );
+ assign( andnV128, binop( Iop_OrV128, mkexpr(andnVhi), mkexpr(andnVlo) ) );
+
+ finish_xTESTy ( andV128, andnV128, sign );
+ return delta;
+}
+
+
+/* Handles 128 bit versions of PMOVZXBW and PMOVSXBW. */
+static Long dis_PMOVxXBW_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, Bool xIsZ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ UChar how = xIsZ ? 'z' : 's';
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "%spmov%cxbw %s,%s\n", mbV, how, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec,
+ unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) );
+ delta += alen;
+ DIP( "%spmov%cxbw %s,%s\n", mbV, how, dis_buf, nameXMMReg(rG) );
}
- /* ---------------------------------------------------- */
- /* --- end of the SSE4 decoder --- */
- /* ---------------------------------------------------- */
+ IRExpr* res
+ = xIsZ /* do math for either zero or sign extend */
+ ? binop( Iop_InterleaveLO8x16,
+ IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) )
+ : binop( Iop_SarN16x8,
+ binop( Iop_ShlN16x8,
+ binop( Iop_InterleaveLO8x16,
+ IRExpr_Const( IRConst_V128(0) ),
+ mkexpr(srcVec) ),
+ mkU8(8) ),
+ mkU8(8) );
- /*after_sse_decoders:*/
+ (isAvx ? putYMMRegLoAndZU : putXMMReg) ( rG, res );
- /* Get the primary opcode. */
- opc = getUChar(delta); delta++;
+ return delta;
+}
- /* We get here if the current insn isn't SSE, or this CPU doesn't
- support SSE. */
+static Long dis_PMOVxXWD_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, Bool xIsZ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ UChar how = xIsZ ? 'z' : 's';
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "%spmov%cxwd %s,%s\n", mbV, how, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec,
+ unop( Iop_64UtoV128, loadLE( Ity_I64, mkexpr(addr) ) ) );
+ delta += alen;
+ DIP( "%spmov%cxwd %s,%s\n", mbV, how, dis_buf, nameXMMReg(rG) );
+ }
+
+ IRExpr* res
+ = binop( Iop_InterleaveLO16x8,
+ IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) );
+ if (!xIsZ)
+ res = binop(Iop_SarN32x4,
+ binop(Iop_ShlN32x4, res, mkU8(16)), mkU8(16));
+
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)
+ ( gregOfRexRM(pfx, modrm), res );
+
+ return delta;
+}
+
+
+static Long dis_PMOVSXWQ_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcBytes = newTemp(Ity_I32);
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcBytes, getXMMRegLane32( rE, 0 ) );
+ delta += 1;
+ DIP( "%spmovsxwq %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcBytes, loadLE( Ity_I32, mkexpr(addr) ) );
+ delta += alen;
+ DIP( "%spmovsxwq %s,%s\n", mbV, dis_buf, nameXMMReg(rG) );
+ }
+
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)
+ ( rG, binop( Iop_64HLtoV128,
+ unop( Iop_16Sto64,
+ unop( Iop_32HIto16, mkexpr(srcBytes) ) ),
+ unop( Iop_16Sto64,
+ unop( Iop_32to16, mkexpr(srcBytes) ) ) ) );
+ return delta;
+}
+
+
+static Long dis_PMOVZXWQ_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "%spmovzxwq %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec,
+ unop( Iop_32UtoV128, loadLE( Ity_I32, mkexpr(addr) ) ) );
+ delta += alen;
+ DIP( "%spmovzxwq %s,%s\n", mbV, dis_buf, nameXMMReg(rG) );
+ }
+
+ IRTemp zeroVec = newTemp( Ity_V128 );
+ assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
+
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)
+ ( rG, binop( Iop_InterleaveLO16x8,
+ mkexpr(zeroVec),
+ binop( Iop_InterleaveLO16x8,
+ mkexpr(zeroVec), mkexpr(srcVec) ) ) );
+ return delta;
+}
+
+
+/* Handles 128 bit versions of PMOVZXDQ and PMOVSXDQ. */
+static Long dis_PMOVxXDQ_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, Bool xIsZ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcI64 = newTemp(Ity_I64);
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ UChar how = xIsZ ? 'z' : 's';
+ UInt rG = gregOfRexRM(pfx, modrm);
+ /* Compute both srcI64 -- the value to expand -- and srcVec -- same
+ thing in a V128, with arbitrary junk in the top 64 bits. Use
+ one or both of them and let iropt clean up afterwards (as
+ usual). */
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ assign( srcI64, unop(Iop_V128to64, mkexpr(srcVec)) );
+ delta += 1;
+ DIP( "%spmov%cxdq %s,%s\n", mbV, how, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcI64, loadLE(Ity_I64, mkexpr(addr)) );
+ assign( srcVec, unop( Iop_64UtoV128, mkexpr(srcI64)) );
+ delta += alen;
+ DIP( "%spmov%cxdq %s,%s\n", mbV, how, dis_buf, nameXMMReg(rG) );
+ }
+
+ IRExpr* res
+ = xIsZ /* do math for either zero or sign extend */
+ ? binop( Iop_InterleaveLO32x4,
+ IRExpr_Const( IRConst_V128(0) ), mkexpr(srcVec) )
+ : binop( Iop_64HLtoV128,
+ unop( Iop_32Sto64,
+ unop( Iop_64HIto32, mkexpr(srcI64) ) ),
+ unop( Iop_32Sto64,
+ unop( Iop_64to32, mkexpr(srcI64) ) ) );
+
+ (isAvx ? putYMMRegLoAndZU : putXMMReg) ( rG, res );
+
+ return delta;
+}
+
+
+/* Handles 128 bit versions of PMOVZXBD and PMOVSXBD. */
+static Long dis_PMOVxXBD_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, Bool xIsZ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ UChar how = xIsZ ? 'z' : 's';
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "%spmov%cxbd %s,%s\n", mbV, how, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec,
+ unop( Iop_32UtoV128, loadLE( Ity_I32, mkexpr(addr) ) ) );
+ delta += alen;
+ DIP( "%spmov%cxbd %s,%s\n", mbV, how, dis_buf, nameXMMReg(rG) );
+ }
+
+ IRTemp zeroVec = newTemp(Ity_V128);
+ assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
+
+ IRExpr* res
+ = binop(Iop_InterleaveLO8x16,
+ mkexpr(zeroVec),
+ binop(Iop_InterleaveLO8x16,
+ mkexpr(zeroVec), mkexpr(srcVec)));
+ if (!xIsZ)
+ res = binop(Iop_SarN32x4,
+ binop(Iop_ShlN32x4, res, mkU8(24)), mkU8(24));
+
+ (isAvx ? putYMMRegLoAndZU : putXMMReg) ( rG, res );
+
+ return delta;
+}
+
+
+/* Handles 128 bit versions of PMOVSXBQ. */
+static Long dis_PMOVSXBQ_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcBytes = newTemp(Ity_I16);
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcBytes, getXMMRegLane16( rE, 0 ) );
+ delta += 1;
+ DIP( "%spmovsxbq %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcBytes, loadLE( Ity_I16, mkexpr(addr) ) );
+ delta += alen;
+ DIP( "%spmovsxbq %s,%s\n", mbV, dis_buf, nameXMMReg(rG) );
+ }
+
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)
+ ( rG, binop( Iop_64HLtoV128,
+ unop( Iop_8Sto64,
+ unop( Iop_16HIto8, mkexpr(srcBytes) ) ),
+ unop( Iop_8Sto64,
+ unop( Iop_16to8, mkexpr(srcBytes) ) ) ) );
+ return delta;
+}
+
+
+/* Handles 128 bit versions of PMOVZXBQ. */
+static Long dis_PMOVZXBQ_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp srcVec = newTemp(Ity_V128);
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if ( epartIsReg(modrm) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( srcVec, getXMMReg(rE) );
+ delta += 1;
+ DIP( "%spmovzxbq %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( srcVec,
+ unop( Iop_32UtoV128,
+ unop( Iop_16Uto32, loadLE( Ity_I16, mkexpr(addr) ))));
+ delta += alen;
+ DIP( "%spmovzxbq %s,%s\n", mbV, dis_buf, nameXMMReg(rG) );
+ }
+
+ IRTemp zeroVec = newTemp(Ity_V128);
+ assign( zeroVec, IRExpr_Const( IRConst_V128(0) ) );
+
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)
+ ( rG, binop( Iop_InterleaveLO8x16,
+ mkexpr(zeroVec),
+ binop( Iop_InterleaveLO8x16,
+ mkexpr(zeroVec),
+ binop( Iop_InterleaveLO8x16,
+ mkexpr(zeroVec), mkexpr(srcVec) ) ) ) );
+ return delta;
+}
+
+
+static Long dis_PHMINPOSUW_128 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UChar* mbV = isAvx ? "v" : "";
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("%sphminposuw %s,%s\n", mbV, nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ if (!isAvx)
+ gen_SEGV_if_not_16_aligned(addr);
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("%sphminposuw %s,%s\n", mbV, dis_buf, nameXMMReg(rG));
+ }
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(sV)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(sV)) );
+ assign( dLo, mkIRExprCCall(
+ Ity_I64, 0/*regparms*/,
+ "amd64g_calculate_sse_phminposuw",
+ &amd64g_calculate_sse_phminposuw,
+ mkIRExprVec_2( mkexpr(sLo), mkexpr(sHi) )
+ ));
+ (isAvx ? putYMMRegLoAndZU : putXMMReg)
+ (rG, unop(Iop_64UtoV128, mkexpr(dLo)));
+ return delta;
+}
+
+
+static Long dis_AESx ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, UChar opc )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt regNoL = 0;
+ UInt regNoR = (isAvx && opc != 0xDB) ? getVexNvvvv(pfx) : rG;
+
+ /* This is a nasty kludge. We need to pass 2 x V128 to the
+ helper. Since we can't do that, use a dirty
+ helper to compute the results directly from the XMM regs in
+ the guest state. That means for the memory case, we need to
+ move the left operand into a pseudo-register (XMM16, let's
+ call it). */
+ if (epartIsReg(modrm)) {
+ regNoL = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ } else {
+ regNoL = 16; /* use XMM16 as an intermediary */
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ /* alignment check needed ???? */
+ stmt( IRStmt_Put( OFFB_YMM16, loadLE(Ity_V128, mkexpr(addr)) ));
+ delta += alen;
+ }
+
+ void* fn = &amd64g_dirtyhelper_AES;
+ HChar* nm = "amd64g_dirtyhelper_AES";
+
+ /* Round up the arguments. Note that this is a kludge -- the
+ use of mkU64 rather than mkIRExpr_HWord implies the
+ assumption that the host's word size is 64-bit. */
+ UInt gstOffD = ymmGuestRegOffset(rG);
+ UInt gstOffL = regNoL == 16 ? OFFB_YMM16 : ymmGuestRegOffset(regNoL);
+ UInt gstOffR = ymmGuestRegOffset(regNoR);
+ IRExpr* opc4 = mkU64(opc);
+ IRExpr* gstOffDe = mkU64(gstOffD);
+ IRExpr* gstOffLe = mkU64(gstOffL);
+ IRExpr* gstOffRe = mkU64(gstOffR);
+ IRExpr** args
+ = mkIRExprVec_4( opc4, gstOffDe, gstOffLe, gstOffRe );
+
+ IRDirty* d = unsafeIRDirty_0_N( 0/*regparms*/, nm, fn, args );
+ /* It's not really a dirty call, but we can't use the clean
+ helper mechanism here for the very lame reason that we can't
+ pass 2 x V128s by value to a helper, nor get one back. Hence
+ this roundabout scheme. */
+ d->needsBBP = True;
+ d->nFxState = 2;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
+ /* AES{ENC,ENCLAST,DEC,DECLAST} read both registers, and writes
+ the second for !isAvx or the third for isAvx.
+ AESIMC (0xDB) reads the first register, and writes the second. */
+ d->fxState[0].fx = Ifx_Read;
+ d->fxState[0].offset = gstOffL;
+ d->fxState[0].size = sizeof(U128);
+ d->fxState[1].offset = gstOffR;
+ d->fxState[1].size = sizeof(U128);
+ if (opc == 0xDB)
+ d->fxState[1].fx = Ifx_Write;
+ else if (!isAvx || rG == regNoR)
+ d->fxState[1].fx = Ifx_Modify;
+ else {
+ d->fxState[1].fx = Ifx_Read;
+ d->nFxState++;
+ d->fxState[2].fx = Ifx_Write;
+ d->fxState[2].offset = gstOffD;
+ d->fxState[2].size = sizeof(U128);
+ }
+
+ stmt( IRStmt_Dirty(d) );
+ {
+ HChar* opsuf;
+ switch (opc) {
+ case 0xDC: opsuf = "enc"; break;
+ case 0XDD: opsuf = "enclast"; break;
+ case 0xDE: opsuf = "dec"; break;
+ case 0xDF: opsuf = "declast"; break;
+ case 0xDB: opsuf = "imc"; break;
+ default: vassert(0);
+ }
+ DIP("%saes%s %s,%s%s%s\n", isAvx ? "v" : "", opsuf,
+ (regNoL == 16 ? dis_buf : nameXMMReg(regNoL)),
+ nameXMMReg(regNoR),
+ (isAvx && opc != 0xDB) ? "," : "",
+ (isAvx && opc != 0xDB) ? nameXMMReg(rG) : "");
+ }
+ if (isAvx)
+ putYMMRegLane128( rG, 1, mkV128(0) );
+ return delta;
+}
+
+static Long dis_AESKEYGENASSIST ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt regNoL = 0;
+ UInt regNoR = gregOfRexRM(pfx, modrm);
+ UChar imm = 0;
+
+ /* This is a nasty kludge. See AESENC et al. instructions. */
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ regNoL = eregOfRexRM(pfx, modrm);
+ imm = getUChar(delta+1);
+ delta += 1+1;
+ } else {
+ regNoL = 16; /* use XMM16 as an intermediary */
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ /* alignment check ???? . */
+ stmt( IRStmt_Put( OFFB_YMM16, loadLE(Ity_V128, mkexpr(addr)) ));
+ imm = getUChar(delta+alen);
+ delta += alen+1;
+ }
+
+ /* Who ya gonna call? Presumably not Ghostbusters. */
+ void* fn = &amd64g_dirtyhelper_AESKEYGENASSIST;
+ HChar* nm = "amd64g_dirtyhelper_AESKEYGENASSIST";
+
+ /* Round up the arguments. Note that this is a kludge -- the
+ use of mkU64 rather than mkIRExpr_HWord implies the
+ assumption that the host's word size is 64-bit. */
+ UInt gstOffL = regNoL == 16 ? OFFB_YMM16 : ymmGuestRegOffset(regNoL);
+ UInt gstOffR = ymmGuestRegOffset(regNoR);
+
+ IRExpr* imme = mkU64(imm & 0xFF);
+ IRExpr* gstOffLe = mkU64(gstOffL);
+ IRExpr* gstOffRe = mkU64(gstOffR);
+ IRExpr** args
+ = mkIRExprVec_3( imme, gstOffLe, gstOffRe );
+
+ IRDirty* d = unsafeIRDirty_0_N( 0/*regparms*/, nm, fn, args );
+ /* It's not really a dirty call, but we can't use the clean
+ helper mechanism here for the very lame reason that we can't
+ pass 2 x V128s by value to a helper, nor get one back. Hence
+ this roundabout scheme. */
+ d->needsBBP = True;
+ d->nFxState = 2;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
+ d->fxState[0].fx = Ifx_Read;
+ d->fxState[0].offset = gstOffL;
+ d->fxState[0].size = sizeof(U128);
+ d->fxState[1].fx = Ifx_Write;
+ d->fxState[1].offset = gstOffR;
+ d->fxState[1].size = sizeof(U128);
+ stmt( IRStmt_Dirty(d) );
+
+ DIP("%saeskeygenassist $%x,%s,%s\n", isAvx ? "v" : "", (UInt)imm,
+ (regNoL == 16 ? dis_buf : nameXMMReg(regNoL)),
+ nameXMMReg(regNoR));
+ if (isAvx)
+ putYMMRegLane128( regNoR, 1, mkV128(0) );
+ return delta;
+}
+
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F38__SSE4 ( Bool* decode_OK,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN )
+{
+ IRTemp addr = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
+
+ *decode_OK = False;
+
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
switch (opc) {
- /* ------------------------ Control flow --------------- */
-
- case 0xC2: /* RET imm16 */
- if (have66orF2orF3(pfx)) goto decode_failure;
- d64 = getUDisp16(delta);
- delta += 2;
- dis_ret(vbi, d64);
- dres.whatNext = Dis_StopHere;
- DIP("ret %lld\n", d64);
- break;
-
- case 0xC3: /* RET */
- if (have66orF2(pfx)) goto decode_failure;
- /* F3 is acceptable on AMD. */
- dis_ret(vbi, 0);
- dres.whatNext = Dis_StopHere;
- DIP(haveF3(pfx) ? "rep ; ret\n" : "ret\n");
- break;
-
- case 0xE8: /* CALL J4 */
- if (haveF2orF3(pfx)) goto decode_failure;
- d64 = getSDisp32(delta); delta += 4;
- d64 += (guest_RIP_bbstart+delta);
- /* (guest_RIP_bbstart+delta) == return-to addr, d64 == call-to addr */
- t1 = newTemp(Ity_I64);
- assign(t1, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8)));
- putIReg64(R_RSP, mkexpr(t1));
- storeLE( mkexpr(t1), mkU64(guest_RIP_bbstart+delta));
- t2 = newTemp(Ity_I64);
- assign(t2, mkU64((Addr64)d64));
- make_redzone_AbiHint(vbi, t1, t2/*nia*/, "call-d32");
- if (resteerOkFn( callback_opaque, (Addr64)d64) ) {
- /* follow into the call target. */
- dres.whatNext = Dis_ResteerU;
- dres.continueAt = d64;
- } else {
- jmp_lit(Ijk_Call,d64);
- dres.whatNext = Dis_StopHere;
- }
- DIP("call 0x%llx\n",d64);
- break;
-
-//.. //-- case 0xC8: /* ENTER */
-//.. //-- d32 = getUDisp16(eip); eip += 2;
-//.. //-- abyte = getUChar(delta); delta++;
-//.. //--
-//.. //-- vg_assert(sz == 4);
-//.. //-- vg_assert(abyte == 0);
-//.. //--
-//.. //-- t1 = newTemp(cb); t2 = newTemp(cb);
-//.. //-- uInstr2(cb, GET, sz, ArchReg, R_EBP, TempReg, t1);
-//.. //-- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2);
-//.. //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
-//.. //-- uLiteral(cb, sz);
-//.. //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
-//.. //-- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2);
-//.. //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBP);
-//.. //-- if (d32) {
-//.. //-- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
-//.. //-- uLiteral(cb, d32);
-//.. //-- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
-//.. //-- }
-//.. //-- DIP("enter 0x%x, 0x%x", d32, abyte);
-//.. //-- break;
-
- case 0xC8: /* ENTER */
- /* Same comments re operand size as for LEAVE below apply.
- Also, only handles the case "enter $imm16, $0"; other cases
- for the second operand (nesting depth) are not handled. */
- if (sz != 4)
- goto decode_failure;
- d64 = getUDisp16(delta);
- delta += 2;
- vassert(d64 >= 0 && d64 <= 0xFFFF);
- if (getUChar(delta) != 0)
- goto decode_failure;
- delta++;
- /* Intel docs seem to suggest:
- push rbp
- temp = rsp
- rbp = temp
- rsp = rsp - imm16
+ case 0x10:
+ case 0x14:
+ case 0x15:
+ /* 66 0F 38 10 /r = PBLENDVB xmm1, xmm2/m128 (byte gran)
+ 66 0F 38 14 /r = BLENDVPS xmm1, xmm2/m128 (float gran)
+ 66 0F 38 15 /r = BLENDVPD xmm1, xmm2/m128 (double gran)
+ Blend at various granularities, with XMM0 (implicit operand)
+ providing the controlling mask.
*/
- t1 = newTemp(Ity_I64);
- assign(t1, getIReg64(R_RBP));
- t2 = newTemp(Ity_I64);
- assign(t2, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8)));
- putIReg64(R_RSP, mkexpr(t2));
- storeLE(mkexpr(t2), mkexpr(t1));
- putIReg64(R_RBP, mkexpr(t2));
- if (d64 > 0) {
- putIReg64(R_RSP, binop(Iop_Sub64, mkexpr(t2), mkU64(d64)));
+ if (have66noF2noF3(pfx) && sz == 2) {
+ modrm = getUChar(delta);
+
+ HChar* nm = NULL;
+ UInt gran = 0;
+ IROp opSAR = Iop_INVALID;
+ switch (opc) {
+ case 0x10:
+ nm = "pblendvb"; gran = 1; opSAR = Iop_SarN8x16;
+ break;
+ case 0x14:
+ nm = "blendvps"; gran = 4; opSAR = Iop_SarN32x4;
+ break;
+ case 0x15:
+ nm = "blendvpd"; gran = 8; opSAR = Iop_SarN64x2;
+ break;
+ }
+ vassert(nm);
+
+ IRTemp vecE = newTemp(Ity_V128);
+ IRTemp vecG = newTemp(Ity_V128);
+ IRTemp vec0 = newTemp(Ity_V128);
+
+ if ( epartIsReg(modrm) ) {
+ assign(vecE, getXMMReg(eregOfRexRM(pfx, modrm)));
+ delta += 1;
+ DIP( "%s %s,%s\n", nm,
+ nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign(vecE, loadLE( Ity_V128, mkexpr(addr) ));
+ delta += alen;
+ DIP( "%s %s,%s\n", nm,
+ dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ assign(vecG, getXMMReg(gregOfRexRM(pfx, modrm)));
+ assign(vec0, getXMMReg(0));
+
+ IRTemp res = math_PBLENDVB_128( vecE, vecG, vec0, gran, opSAR );
+ putXMMReg(gregOfRexRM(pfx, modrm), mkexpr(res));
+
+ goto decode_success;
}
- DIP("enter $%u, $0\n", (UInt)d64);
break;
- case 0xC9: /* LEAVE */
- /* In 64-bit mode this defaults to a 64-bit operand size. There
- is no way to encode a 32-bit variant. Hence sz==4 but we do
- it as if sz=8. */
- if (sz != 4)
- goto decode_failure;
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign(t1, getIReg64(R_RBP));
- /* First PUT RSP looks redundant, but need it because RSP must
- always be up-to-date for Memcheck to work... */
- putIReg64(R_RSP, mkexpr(t1));
- assign(t2, loadLE(Ity_I64,mkexpr(t1)));
- putIReg64(R_RBP, mkexpr(t2));
- putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t1), mkU64(8)) );
- DIP("leave\n");
- break;
-
-//.. //-- /* ---------------- Misc weird-ass insns --------------- */
-//.. //--
-//.. //-- case 0x27: /* DAA */
-//.. //-- case 0x2F: /* DAS */
-//.. //-- t1 = newTemp(cb);
-//.. //-- uInstr2(cb, GET, 1, ArchReg, R_AL, TempReg, t1);
-//.. //-- /* Widen %AL to 32 bits, so it's all defined when we push it. */
-//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t1);
-//.. //-- uWiden(cb, 1, False);
-//.. //-- uInstr0(cb, CALLM_S, 0);
-//.. //-- uInstr1(cb, PUSH, 4, TempReg, t1);
-//.. //-- uInstr1(cb, CALLM, 0, Lit16,
-//.. //-- opc == 0x27 ? VGOFF_(helper_DAA) : VGOFF_(helper_DAS) );
-//.. //-- uFlagsRWU(cb, FlagsAC, FlagsSZACP, FlagO);
-//.. //-- uInstr1(cb, POP, 4, TempReg, t1);
-//.. //-- uInstr0(cb, CALLM_E, 0);
-//.. //-- uInstr2(cb, PUT, 1, TempReg, t1, ArchReg, R_AL);
-//.. //-- DIP(opc == 0x27 ? "daa\n" : "das\n");
-//.. //-- break;
-//.. //--
-//.. //-- case 0x37: /* AAA */
-//.. //-- case 0x3F: /* AAS */
-//.. //-- t1 = newTemp(cb);
-//.. //-- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, t1);
-//.. //-- /* Widen %AL to 32 bits, so it's all defined when we push it. */
-//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t1);
-//.. //-- uWiden(cb, 2, False);
-//.. //-- uInstr0(cb, CALLM_S, 0);
-//.. //-- uInstr1(cb, PUSH, 4, TempReg, t1);
-//.. //-- uInstr1(cb, CALLM, 0, Lit16,
-//.. //-- opc == 0x37 ? VGOFF_(helper_AAA) : VGOFF_(helper_AAS) );
-//.. //-- uFlagsRWU(cb, FlagA, FlagsAC, FlagsEmpty);
-//.. //-- uInstr1(cb, POP, 4, TempReg, t1);
-//.. //-- uInstr0(cb, CALLM_E, 0);
-//.. //-- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX);
-//.. //-- DIP(opc == 0x37 ? "aaa\n" : "aas\n");
-//.. //-- break;
-//.. //--
-//.. //-- case 0xD4: /* AAM */
-//.. //-- case 0xD5: /* AAD */
-//.. //-- d32 = getUChar(delta); delta++;
-//.. //-- if (d32 != 10) VG_(core_panic)("disInstr: AAM/AAD but base not 10 !");
-//.. //-- t1 = newTemp(cb);
-//.. //-- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, t1);
-//.. //-- /* Widen %AX to 32 bits, so it's all defined when we push it. */
-//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t1);
-//.. //-- uWiden(cb, 2, False);
-//.. //-- uInstr0(cb, CALLM_S, 0);
-//.. //-- uInstr1(cb, PUSH, 4, TempReg, t1);
-//.. //-- uInstr1(cb, CALLM, 0, Lit16,
-//.. //-- opc == 0xD4 ? VGOFF_(helper_AAM) : VGOFF_(helper_AAD) );
-//.. //-- uFlagsRWU(cb, FlagsEmpty, FlagsSZP, FlagsEmpty);
-//.. //-- uInstr1(cb, POP, 4, TempReg, t1);
-//.. //-- uInstr0(cb, CALLM_E, 0);
-//.. //-- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX);
-//.. //-- DIP(opc == 0xD4 ? "aam\n" : "aad\n");
-//.. //-- break;
-
- /* ------------------------ CWD/CDQ -------------------- */
-
- case 0x98: /* CBW */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz == 8) {
- putIRegRAX( 8, unop(Iop_32Sto64, getIRegRAX(4)) );
- DIP(/*"cdqe\n"*/"cltq");
- break;
+ case 0x17:
+ /* 66 0F 38 17 /r = PTEST xmm1, xmm2/m128
+ Logical compare (set ZF and CF from AND/ANDN of the operands) */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ delta = dis_xTESTy_128( vbi, pfx, delta, False/*!isAvx*/, 0 );
+ goto decode_success;
}
- if (sz == 4) {
- putIRegRAX( 4, unop(Iop_16Sto32, getIRegRAX(2)) );
- DIP("cwtl\n");
- break;
+ break;
+
+ case 0x20:
+ /* 66 0F 38 20 /r = PMOVSXBW xmm1, xmm2/m64
+ Packed Move with Sign Extend from Byte to Word (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVxXBW_128( vbi, pfx, delta,
+ False/*!isAvx*/, False/*!xIsZ*/ );
+ goto decode_success;
}
- if (sz == 2) {
- putIRegRAX( 2, unop(Iop_8Sto16, getIRegRAX(1)) );
- DIP("cbw\n");
- break;
+ break;
+
+ case 0x21:
+ /* 66 0F 38 21 /r = PMOVSXBD xmm1, xmm2/m32
+ Packed Move with Sign Extend from Byte to DWord (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVxXBD_128( vbi, pfx, delta,
+ False/*!isAvx*/, False/*!xIsZ*/ );
+ goto decode_success;
}
- goto decode_failure;
-
- case 0x99: /* CWD/CDQ/CQO */
- if (haveF2orF3(pfx)) goto decode_failure;
- vassert(sz == 2 || sz == 4 || sz == 8);
- ty = szToITy(sz);
- putIRegRDX( sz,
- binop(mkSizedOp(ty,Iop_Sar8),
- getIRegRAX(sz),
- mkU8(sz == 2 ? 15 : (sz == 4 ? 31 : 63))) );
- DIP(sz == 2 ? "cwd\n"
- : (sz == 4 ? /*"cdq\n"*/ "cltd\n"
- : "cqo\n"));
break;
- /* ------------------------ FPU ops -------------------- */
-
- case 0x9E: /* SAHF */
- codegen_SAHF();
- DIP("sahf\n");
+ case 0x22:
+ /* 66 0F 38 22 /r = PMOVSXBQ xmm1, xmm2/m16
+ Packed Move with Sign Extend from Byte to QWord (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVSXBQ_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
break;
- case 0x9F: /* LAHF */
- codegen_LAHF();
- DIP("lahf\n");
+ case 0x23:
+ /* 66 0F 38 23 /r = PMOVSXWD xmm1, xmm2/m64
+ Packed Move with Sign Extend from Word to DWord (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVxXWD_128(vbi, pfx, delta,
+ False/*!isAvx*/, False/*!xIsZ*/);
+ goto decode_success;
+ }
break;
- case 0x9B: /* FWAIT */
- /* ignore? */
- DIP("fwait\n");
+ case 0x24:
+ /* 66 0F 38 24 /r = PMOVSXWQ xmm1, xmm2/m32
+ Packed Move with Sign Extend from Word to QWord (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVSXWQ_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
break;
- case 0xD8:
- case 0xD9:
- case 0xDA:
- case 0xDB:
+ case 0x25:
+ /* 66 0F 38 25 /r = PMOVSXDQ xmm1, xmm2/m64
+ Packed Move with Sign Extend from Double Word to Quad Word (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVxXDQ_128( vbi, pfx, delta,
+ False/*!isAvx*/, False/*!xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x28:
+ /* 66 0F 38 28 = PMULDQ -- signed widening multiply of 32-lanes
+ 0 x 0 to form lower 64-bit half and lanes 2 x 2 to form upper
+ 64-bit half */
+ /* This is a really poor translation -- could be improved if
+ performance critical. It's a copy-paste of PMULUDQ, too. */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ assign( dV, getXMMReg(rG) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("pmuldq %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("pmuldq %s,%s\n", dis_buf, nameXMMReg(rG));
+ }
+
+ putXMMReg( rG, mkexpr(math_PMULDQ_128( dV, sV )) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x29:
+ /* 66 0F 38 29 = PCMPEQQ
+ 64x2 equality comparison */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ /* FIXME: this needs an alignment check */
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pcmpeqq", Iop_CmpEQ64x2, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0x2B:
+ /* 66 0f 38 2B /r = PACKUSDW xmm1, xmm2/m128
+ 2x 32x4 S->U saturating narrow from xmm2/m128 to xmm1 */
+ if (have66noF2noF3(pfx) && sz == 2) {
+
+ modrm = getUChar(delta);
+
+ IRTemp argL = newTemp(Ity_V128);
+ IRTemp argR = newTemp(Ity_V128);
+
+ if ( epartIsReg(modrm) ) {
+ assign( argL, getXMMReg( eregOfRexRM(pfx, modrm) ) );
+ delta += 1;
+ DIP( "packusdw %s,%s\n",
+ nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( argL, loadLE( Ity_V128, mkexpr(addr) ));
+ delta += alen;
+ DIP( "packusdw %s,%s\n",
+ dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ assign(argR, getXMMReg( gregOfRexRM(pfx, modrm) ));
+
+ putXMMReg( gregOfRexRM(pfx, modrm),
+ binop( Iop_QNarrowBin32Sto16Ux8,
+ mkexpr(argL), mkexpr(argR)) );
+
+ goto decode_success;
+ }
+ break;
+
+ case 0x30:
+ /* 66 0F 38 30 /r = PMOVZXBW xmm1, xmm2/m64
+ Packed Move with Zero Extend from Byte to Word (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVxXBW_128( vbi, pfx, delta,
+ False/*!isAvx*/, True/*xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x31:
+ /* 66 0F 38 31 /r = PMOVZXBD xmm1, xmm2/m32
+ Packed Move with Zero Extend from Byte to DWord (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVxXBD_128( vbi, pfx, delta,
+ False/*!isAvx*/, True/*xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x32:
+ /* 66 0F 38 32 /r = PMOVZXBQ xmm1, xmm2/m16
+ Packed Move with Zero Extend from Byte to QWord (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVZXBQ_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x33:
+ /* 66 0F 38 33 /r = PMOVZXWD xmm1, xmm2/m64
+ Packed Move with Zero Extend from Word to DWord (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVxXWD_128( vbi, pfx, delta,
+ False/*!isAvx*/, True/*xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x34:
+ /* 66 0F 38 34 /r = PMOVZXWQ xmm1, xmm2/m32
+ Packed Move with Zero Extend from Word to QWord (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVZXWQ_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x35:
+ /* 66 0F 38 35 /r = PMOVZXDQ xmm1, xmm2/m64
+ Packed Move with Zero Extend from DWord to QWord (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PMOVxXDQ_128( vbi, pfx, delta,
+ False/*!isAvx*/, True/*xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x37:
+ /* 66 0F 38 37 = PCMPGTQ
+ 64x2 comparison (signed, presumably; the Intel docs don't say :-)
+ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ /* FIXME: this needs an alignment check */
+ delta = dis_SSEint_E_to_G( vbi, pfx, delta,
+ "pcmpgtq", Iop_CmpGT64Sx2, False );
+ goto decode_success;
+ }
+ break;
+
+ case 0x38:
+ case 0x3C:
+ /* 66 0F 38 38 /r = PMINSB xmm1, xmm2/m128 8Sx16 (signed) min
+ 66 0F 38 3C /r = PMAXSB xmm1, xmm2/m128 8Sx16 (signed) max
+ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ /* FIXME: this needs an alignment check */
+ Bool isMAX = opc == 0x3C;
+ delta = dis_SSEint_E_to_G(
+ vbi, pfx, delta,
+ isMAX ? "pmaxsb" : "pminsb",
+ isMAX ? Iop_Max8Sx16 : Iop_Min8Sx16,
+ False
+ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x39:
+ case 0x3D:
+ /* 66 0F 38 39 /r = PMINSD xmm1, xmm2/m128
+ Minimum of Packed Signed Double Word Integers (XMM)
+ 66 0F 38 3D /r = PMAXSD xmm1, xmm2/m128
+ Maximum of Packed Signed Double Word Integers (XMM)
+ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ /* FIXME: this needs an alignment check */
+ Bool isMAX = opc == 0x3D;
+ delta = dis_SSEint_E_to_G(
+ vbi, pfx, delta,
+ isMAX ? "pmaxsd" : "pminsd",
+ isMAX ? Iop_Max32Sx4 : Iop_Min32Sx4,
+ False
+ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x3A:
+ case 0x3E:
+ /* 66 0F 38 3A /r = PMINUW xmm1, xmm2/m128
+ Minimum of Packed Unsigned Word Integers (XMM)
+ 66 0F 38 3E /r = PMAXUW xmm1, xmm2/m128
+ Maximum of Packed Unsigned Word Integers (XMM)
+ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ /* FIXME: this needs an alignment check */
+ Bool isMAX = opc == 0x3E;
+ delta = dis_SSEint_E_to_G(
+ vbi, pfx, delta,
+ isMAX ? "pmaxuw" : "pminuw",
+ isMAX ? Iop_Max16Ux8 : Iop_Min16Ux8,
+ False
+ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x3B:
+ case 0x3F:
+ /* 66 0F 38 3B /r = PMINUD xmm1, xmm2/m128
+ Minimum of Packed Unsigned Doubleword Integers (XMM)
+ 66 0F 38 3F /r = PMAXUD xmm1, xmm2/m128
+ Maximum of Packed Unsigned Doubleword Integers (XMM)
+ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ /* FIXME: this needs an alignment check */
+ Bool isMAX = opc == 0x3F;
+ delta = dis_SSEint_E_to_G(
+ vbi, pfx, delta,
+ isMAX ? "pmaxud" : "pminud",
+ isMAX ? Iop_Max32Ux4 : Iop_Min32Ux4,
+ False
+ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x40:
+ /* 66 0F 38 40 /r = PMULLD xmm1, xmm2/m128
+ 32x4 integer multiply from xmm2/m128 to xmm1 */
+ if (have66noF2noF3(pfx) && sz == 2) {
+
+ modrm = getUChar(delta);
+
+ IRTemp argL = newTemp(Ity_V128);
+ IRTemp argR = newTemp(Ity_V128);
+
+ if ( epartIsReg(modrm) ) {
+ assign( argL, getXMMReg( eregOfRexRM(pfx, modrm) ) );
+ delta += 1;
+ DIP( "pmulld %s,%s\n",
+ nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( argL, loadLE( Ity_V128, mkexpr(addr) ));
+ delta += alen;
+ DIP( "pmulld %s,%s\n",
+ dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ assign(argR, getXMMReg( gregOfRexRM(pfx, modrm) ));
+
+ putXMMReg( gregOfRexRM(pfx, modrm),
+ binop( Iop_Mul32x4, mkexpr(argL), mkexpr(argR)) );
+
+ goto decode_success;
+ }
+ break;
+
+ case 0x41:
+ /* 66 0F 38 41 /r = PHMINPOSUW xmm1, xmm2/m128
+ Packed Horizontal Word Minimum from xmm2/m128 to xmm1 */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PHMINPOSUW_128( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
case 0xDC:
case 0xDD:
case 0xDE:
- case 0xDF: {
- Bool redundantREXWok = False;
+ case 0xDF:
+ case 0xDB:
+ /* 66 0F 38 DC /r = AESENC xmm1, xmm2/m128
+ DD /r = AESENCLAST xmm1, xmm2/m128
+ DE /r = AESDEC xmm1, xmm2/m128
+ DF /r = AESDECLAST xmm1, xmm2/m128
- if (haveF2orF3(pfx))
- goto decode_failure;
+ DB /r = AESIMC xmm1, xmm2/m128 */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_AESx( vbi, pfx, delta, False/*!isAvx*/, opc );
+ goto decode_success;
+ }
+ break;
- /* kludge to tolerate redundant rex.w prefixes (should do this
- properly one day) */
- /* mono 1.1.18.1 produces 48 D9 FA, which is rex.w fsqrt */
- if ( (opc == 0xD9 && getUChar(delta+0) == 0xFA)/*fsqrt*/ )
- redundantREXWok = True;
+ case 0xF0:
+ case 0xF1:
+ /* F2 0F 38 F0 /r = CRC32 r/m8, r32 (REX.W ok, 66 not ok)
+ F2 0F 38 F1 /r = CRC32 r/m{16,32,64}, r32
+ The decoding on this is a bit unusual.
+ */
+ if (haveF2noF3(pfx)
+ && (opc == 0xF1 || (opc == 0xF0 && !have66(pfx)))) {
+ modrm = getUChar(delta);
- if ( (sz == 4
- || (sz == 8 && redundantREXWok))
- && haveNo66noF2noF3(pfx)) {
- Long delta0 = delta;
- Bool decode_OK = False;
- delta = dis_FPU ( &decode_OK, vbi, pfx, delta );
- if (!decode_OK) {
- delta = delta0;
- goto decode_failure;
+ if (opc == 0xF0)
+ sz = 1;
+ else
+ vassert(sz == 2 || sz == 4 || sz == 8);
+
+ IRType tyE = szToITy(sz);
+ IRTemp valE = newTemp(tyE);
+
+ if (epartIsReg(modrm)) {
+ assign(valE, getIRegE(sz, pfx, modrm));
+ delta += 1;
+ DIP("crc32b %s,%s\n", nameIRegE(sz, pfx, modrm),
+ nameIRegG(1==getRexW(pfx) ? 8 : 4, pfx, modrm));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(valE, loadLE(tyE, mkexpr(addr)));
+ delta += alen;
+ DIP("crc32b %s,%s\n", dis_buf,
+ nameIRegG(1==getRexW(pfx) ? 8 : 4, pfx, modrm));
}
+
+ /* Somewhat funny getting/putting of the crc32 value, in order
+ to ensure that it turns into 64-bit gets and puts. However,
+ mask off the upper 32 bits so as to not get memcheck false
+ +ves around the helper call. */
+ IRTemp valG0 = newTemp(Ity_I64);
+ assign(valG0, binop(Iop_And64, getIRegG(8, pfx, modrm),
+ mkU64(0xFFFFFFFF)));
+
+ HChar* nm = NULL;
+ void* fn = NULL;
+ switch (sz) {
+ case 1: nm = "amd64g_calc_crc32b";
+ fn = &amd64g_calc_crc32b; break;
+ case 2: nm = "amd64g_calc_crc32w";
+ fn = &amd64g_calc_crc32w; break;
+ case 4: nm = "amd64g_calc_crc32l";
+ fn = &amd64g_calc_crc32l; break;
+ case 8: nm = "amd64g_calc_crc32q";
+ fn = &amd64g_calc_crc32q; break;
+ }
+ vassert(nm && fn);
+ IRTemp valG1 = newTemp(Ity_I64);
+ assign(valG1,
+ mkIRExprCCall(Ity_I64, 0/*regparm*/, nm, fn,
+ mkIRExprVec_2(mkexpr(valG0),
+ widenUto64(mkexpr(valE)))));
+
+ putIRegG(4, pfx, modrm, unop(Iop_64to32, mkexpr(valG1)));
+ goto decode_success;
+ }
+ break;
+
+ default:
+ break;
+
+ }
+
+ //decode_failure:
+ *decode_OK = False;
+ return deltaIN;
+
+ decode_success:
+ *decode_OK = True;
+ return delta;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level SSE4: dis_ESC_0F3A__SSE4 ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+static Long dis_PEXTRW ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ IRTemp t0 = IRTemp_INVALID;
+ IRTemp t1 = IRTemp_INVALID;
+ IRTemp t2 = IRTemp_INVALID;
+ IRTemp t3 = IRTemp_INVALID;
+ UChar modrm = getUChar(delta);
+ Int alen = 0;
+ HChar dis_buf[50];
+ UInt rG = gregOfRexRM(pfx,modrm);
+ Int imm8_20;
+ IRTemp xmm_vec = newTemp(Ity_V128);
+ IRTemp d16 = newTemp(Ity_I16);
+ HChar* mbV = isAvx ? "v" : "";
+
+ vassert(0==getRexW(pfx)); /* ensured by caller */
+ assign( xmm_vec, getXMMReg(rG) );
+ breakupV128to32s( xmm_vec, &t3, &t2, &t1, &t0 );
+
+ if ( epartIsReg( modrm ) ) {
+ imm8_20 = (Int)(getUChar(delta+1) & 7);
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8_20 = (Int)(getUChar(delta+alen) & 7);
+ }
+
+ switch (imm8_20) {
+ case 0: assign(d16, unop(Iop_32to16, mkexpr(t0))); break;
+ case 1: assign(d16, unop(Iop_32HIto16, mkexpr(t0))); break;
+ case 2: assign(d16, unop(Iop_32to16, mkexpr(t1))); break;
+ case 3: assign(d16, unop(Iop_32HIto16, mkexpr(t1))); break;
+ case 4: assign(d16, unop(Iop_32to16, mkexpr(t2))); break;
+ case 5: assign(d16, unop(Iop_32HIto16, mkexpr(t2))); break;
+ case 6: assign(d16, unop(Iop_32to16, mkexpr(t3))); break;
+ case 7: assign(d16, unop(Iop_32HIto16, mkexpr(t3))); break;
+ default: vassert(0);
+ }
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putIReg32( rE, unop(Iop_16Uto32, mkexpr(d16)) );
+ delta += 1+1;
+ DIP( "%spextrw $%d, %s,%s\n", mbV, imm8_20,
+ nameXMMReg( rG ), nameIReg32( rE ) );
+ } else {
+ storeLE( mkexpr(addr), mkexpr(d16) );
+ delta += alen+1;
+ DIP( "%spextrw $%d, %s,%s\n", mbV, imm8_20, nameXMMReg( rG ), dis_buf );
+ }
+ return delta;
+}
+
+
+static Long dis_PEXTRD ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ IRTemp t0 = IRTemp_INVALID;
+ IRTemp t1 = IRTemp_INVALID;
+ IRTemp t2 = IRTemp_INVALID;
+ IRTemp t3 = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
+
+ Int imm8_10;
+ IRTemp xmm_vec = newTemp(Ity_V128);
+ IRTemp src_dword = newTemp(Ity_I32);
+ HChar* mbV = isAvx ? "v" : "";
+
+ vassert(0==getRexW(pfx)); /* ensured by caller */
+ modrm = getUChar(delta);
+ assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) );
+ breakupV128to32s( xmm_vec, &t3, &t2, &t1, &t0 );
+
+ if ( epartIsReg( modrm ) ) {
+ imm8_10 = (Int)(getUChar(delta+1) & 3);
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8_10 = (Int)(getUChar(delta+alen) & 3);
+ }
+
+ switch ( imm8_10 ) {
+ case 0: assign( src_dword, mkexpr(t0) ); break;
+ case 1: assign( src_dword, mkexpr(t1) ); break;
+ case 2: assign( src_dword, mkexpr(t2) ); break;
+ case 3: assign( src_dword, mkexpr(t3) ); break;
+ default: vassert(0);
+ }
+
+ if ( epartIsReg( modrm ) ) {
+ putIReg32( eregOfRexRM(pfx,modrm), mkexpr(src_dword) );
+ delta += 1+1;
+ DIP( "%spextrd $%d, %s,%s\n", mbV, imm8_10,
+ nameXMMReg( gregOfRexRM(pfx, modrm) ),
+ nameIReg32( eregOfRexRM(pfx, modrm) ) );
+ } else {
+ storeLE( mkexpr(addr), mkexpr(src_dword) );
+ delta += alen+1;
+ DIP( "%spextrd $%d, %s,%s\n", mbV,
+ imm8_10, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf );
+ }
+ return delta;
+}
+
+
+static Long dis_PEXTRQ ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
+
+ Int imm8_0;
+ IRTemp xmm_vec = newTemp(Ity_V128);
+ IRTemp src_qword = newTemp(Ity_I64);
+ HChar* mbV = isAvx ? "v" : "";
+
+ vassert(1==getRexW(pfx)); /* ensured by caller */
+ modrm = getUChar(delta);
+ assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) );
+
+ if ( epartIsReg( modrm ) ) {
+ imm8_0 = (Int)(getUChar(delta+1) & 1);
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8_0 = (Int)(getUChar(delta+alen) & 1);
+ }
+
+ switch ( imm8_0 ) {
+ case 0: assign( src_qword, unop(Iop_V128to64, mkexpr(xmm_vec)) );
+ break;
+ case 1: assign( src_qword, unop(Iop_V128HIto64, mkexpr(xmm_vec)) );
+ break;
+ default: vassert(0);
+ }
+
+ if ( epartIsReg( modrm ) ) {
+ putIReg64( eregOfRexRM(pfx,modrm), mkexpr(src_qword) );
+ delta += 1+1;
+ DIP( "%spextrq $%d, %s,%s\n", mbV, imm8_0,
+ nameXMMReg( gregOfRexRM(pfx, modrm) ),
+ nameIReg64( eregOfRexRM(pfx, modrm) ) );
+ } else {
+ storeLE( mkexpr(addr), mkexpr(src_qword) );
+ delta += alen+1;
+ DIP( "%spextrq $%d, %s,%s\n", mbV,
+ imm8_0, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf );
+ }
+ return delta;
+}
+
+
+/* This can fail, in which case it returns the original (unchanged)
+ delta. */
+static Long dis_PCMPxSTRx ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx, UChar opc )
+{
+ Long delta0 = delta;
+ UInt isISTRx = opc & 2;
+ UInt isxSTRM = (opc & 1) ^ 1;
+ UInt regNoL = 0;
+ UInt regNoR = 0;
+ UChar imm = 0;
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+
+ /* This is a nasty kludge. We need to pass 2 x V128 to the helper
+ (which is clean). Since we can't do that, use a dirty helper to
+ compute the results directly from the XMM regs in the guest
+ state. That means for the memory case, we need to move the left
+ operand into a pseudo-register (XMM16, let's call it). */
+ UChar modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ regNoL = eregOfRexRM(pfx, modrm);
+ regNoR = gregOfRexRM(pfx, modrm);
+ imm = getUChar(delta+1);
+ delta += 1+1;
+ } else {
+ regNoL = 16; /* use XMM16 as an intermediary */
+ regNoR = gregOfRexRM(pfx, modrm);
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ /* No alignment check; I guess that makes sense, given that
+ these insns are for dealing with C style strings. */
+ stmt( IRStmt_Put( OFFB_YMM16, loadLE(Ity_V128, mkexpr(addr)) ));
+ imm = getUChar(delta+alen);
+ delta += alen+1;
+ }
+
+ /* Now we know the XMM reg numbers for the operands, and the
+ immediate byte. Is it one we can actually handle? Throw out any
+ cases for which the helper function has not been verified. */
+ switch (imm) {
+ case 0x00:
+ case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
+ case 0x1A: case 0x38: case 0x3A: case 0x44: case 0x4A:
+ case 0x46:
break;
+ case 0x01: // the 16-bit character versions of the above
+ case 0x03: case 0x09: case 0x0B: case 0x0D: case 0x13:
+ case 0x1B: case 0x39: case 0x3B: case 0x45: case 0x4B:
+ break;
+ default:
+ return delta0; /*FAIL*/
+ }
+
+ /* Who ya gonna call? Presumably not Ghostbusters. */
+ void* fn = &amd64g_dirtyhelper_PCMPxSTRx;
+ HChar* nm = "amd64g_dirtyhelper_PCMPxSTRx";
+
+ /* Round up the arguments. Note that this is a kludge -- the use
+ of mkU64 rather than mkIRExpr_HWord implies the assumption that
+ the host's word size is 64-bit. */
+ UInt gstOffL = regNoL == 16 ? OFFB_YMM16 : ymmGuestRegOffset(regNoL);
+ UInt gstOffR = ymmGuestRegOffset(regNoR);
+
+ IRExpr* opc4_and_imm = mkU64((opc << 8) | (imm & 0xFF));
+ IRExpr* gstOffLe = mkU64(gstOffL);
+ IRExpr* gstOffRe = mkU64(gstOffR);
+ IRExpr* edxIN = isISTRx ? mkU64(0) : getIRegRDX(8);
+ IRExpr* eaxIN = isISTRx ? mkU64(0) : getIRegRAX(8);
+ IRExpr** args
+ = mkIRExprVec_5( opc4_and_imm, gstOffLe, gstOffRe, edxIN, eaxIN );
+
+ IRTemp resT = newTemp(Ity_I64);
+ IRDirty* d = unsafeIRDirty_1_N( resT, 0/*regparms*/, nm, fn, args );
+ /* It's not really a dirty call, but we can't use the clean helper
+ mechanism here for the very lame reason that we can't pass 2 x
+ V128s by value to a helper, nor get one back. Hence this
+ roundabout scheme. */
+ d->needsBBP = True;
+ d->nFxState = 2;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
+ d->fxState[0].fx = Ifx_Read;
+ d->fxState[0].offset = gstOffL;
+ d->fxState[0].size = sizeof(U128);
+ d->fxState[1].fx = Ifx_Read;
+ d->fxState[1].offset = gstOffR;
+ d->fxState[1].size = sizeof(U128);
+ if (isxSTRM) {
+ /* Declare that the helper writes XMM0. */
+ d->nFxState = 3;
+ d->fxState[2].fx = Ifx_Write;
+ d->fxState[2].offset = ymmGuestRegOffset(0);
+ d->fxState[2].size = sizeof(U128);
+ }
+
+ stmt( IRStmt_Dirty(d) );
+
+ /* Now resT[15:0] holds the new OSZACP values, so the condition
+ codes must be updated. And for a xSTRI case, resT[31:16] holds
+ the new ECX value, so stash that too. */
+ if (!isxSTRM) {
+ putIReg64(R_RCX, binop(Iop_And64,
+ binop(Iop_Shr64, mkexpr(resT), mkU8(16)),
+ mkU64(0xFFFF)));
+ }
+
+ /* Zap the upper half of the dest reg as per AVX conventions. */
+ if (isxSTRM && isAvx)
+ putYMMRegLane128(/*YMM*/0, 1, mkV128(0));
+
+ stmt( IRStmt_Put(
+ OFFB_CC_DEP1,
+ binop(Iop_And64, mkexpr(resT), mkU64(0xFFFF))
+ ));
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+
+ if (regNoL == 16) {
+ DIP("%spcmp%cstr%c $%x,%s,%s\n",
+ isAvx ? "v" : "", isISTRx ? 'i' : 'e', isxSTRM ? 'm' : 'i',
+ (UInt)imm, dis_buf, nameXMMReg(regNoR));
+ } else {
+ DIP("%spcmp%cstr%c $%x,%s,%s\n",
+ isAvx ? "v" : "", isISTRx ? 'i' : 'e', isxSTRM ? 'm' : 'i',
+ (UInt)imm, nameXMMReg(regNoL), nameXMMReg(regNoR));
+ }
+
+ return delta;
+}
+
+
+static IRTemp math_PINSRB_128 ( IRTemp v128, IRTemp u8, UInt imm8 )
+{
+ vassert(imm8 >= 0 && imm8 <= 15);
+
+ // Create a V128 value which has the selected byte in the
+ // specified lane, and zeroes everywhere else.
+ IRTemp tmp128 = newTemp(Ity_V128);
+ IRTemp halfshift = newTemp(Ity_I64);
+ assign(halfshift, binop(Iop_Shl64,
+ unop(Iop_8Uto64, mkexpr(u8)),
+ mkU8(8 * (imm8 & 7))));
+ if (imm8 < 8) {
+ assign(tmp128, binop(Iop_64HLtoV128, mkU64(0), mkexpr(halfshift)));
+ } else {
+ assign(tmp128, binop(Iop_64HLtoV128, mkexpr(halfshift), mkU64(0)));
+ }
+
+ UShort mask = ~(1 << imm8);
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop(Iop_OrV128,
+ mkexpr(tmp128),
+ binop(Iop_AndV128, mkexpr(v128), mkV128(mask))) );
+ return res;
+}
+
+
+static IRTemp math_PINSRD_128 ( IRTemp v128, IRTemp u32, UInt imm8 )
+{
+ IRTemp z32 = newTemp(Ity_I32);
+ assign(z32, mkU32(0));
+
+ /* Surround u32 with zeroes as per imm, giving us something we can
+ OR into a suitably masked-out v128.*/
+ IRTemp withZs = newTemp(Ity_V128);
+ UShort mask = 0;
+ switch (imm8) {
+ case 3: mask = 0x0FFF;
+ assign(withZs, mkV128from32s(u32, z32, z32, z32));
+ break;
+ case 2: mask = 0xF0FF;
+ assign(withZs, mkV128from32s(z32, u32, z32, z32));
+ break;
+ case 1: mask = 0xFF0F;
+ assign(withZs, mkV128from32s(z32, z32, u32, z32));
+ break;
+ case 0: mask = 0xFFF0;
+ assign(withZs, mkV128from32s(z32, z32, z32, u32));
+ break;
+ default: vassert(0);
+ }
+
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop( Iop_OrV128,
+ mkexpr(withZs),
+ binop( Iop_AndV128, mkexpr(v128), mkV128(mask) ) ) );
+ return res;
+}
+
+
+static IRTemp math_PINSRQ_128 ( IRTemp v128, IRTemp u64, UInt imm8 )
+{
+ /* Surround u64 with zeroes as per imm, giving us something we can
+ OR into a suitably masked-out v128.*/
+ IRTemp withZs = newTemp(Ity_V128);
+ UShort mask = 0;
+ if (imm8 == 0) {
+ mask = 0xFF00;
+ assign(withZs, binop(Iop_64HLtoV128, mkU64(0), mkexpr(u64)));
+ } else {
+ vassert(imm8 == 1);
+ mask = 0x00FF;
+ assign( withZs, binop(Iop_64HLtoV128, mkexpr(u64), mkU64(0)));
+ }
+
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop( Iop_OrV128,
+ mkexpr(withZs),
+ binop( Iop_AndV128, mkexpr(v128), mkV128(mask) ) ) );
+ return res;
+}
+
+
+static IRTemp math_INSERTPS ( IRTemp dstV, IRTemp toInsertD, UInt imm8 )
+{
+ const IRTemp inval = IRTemp_INVALID;
+ IRTemp dstDs[4] = { inval, inval, inval, inval };
+ breakupV128to32s( dstV, &dstDs[3], &dstDs[2], &dstDs[1], &dstDs[0] );
+
+ vassert(imm8 <= 255);
+ dstDs[(imm8 >> 4) & 3] = toInsertD; /* "imm8_count_d" */
+
+ UInt imm8_zmask = (imm8 & 15);
+ IRTemp zero_32 = newTemp(Ity_I32);
+ assign( zero_32, mkU32(0) );
+ IRTemp resV = newTemp(Ity_V128);
+ assign( resV, mkV128from32s(
+ ((imm8_zmask & 8) == 8) ? zero_32 : dstDs[3],
+ ((imm8_zmask & 4) == 4) ? zero_32 : dstDs[2],
+ ((imm8_zmask & 2) == 2) ? zero_32 : dstDs[1],
+ ((imm8_zmask & 1) == 1) ? zero_32 : dstDs[0]) );
+ return resV;
+}
+
+
+static Long dis_PEXTRB_128_GtoE ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp xmm_vec = newTemp(Ity_V128);
+ IRTemp sel_lane = newTemp(Ity_I32);
+ IRTemp shr_lane = newTemp(Ity_I32);
+ UChar* mbV = isAvx ? "v" : "";
+ UChar modrm = getUChar(delta);
+ IRTemp t3, t2, t1, t0;
+ Int imm8;
+ assign( xmm_vec, getXMMReg( gregOfRexRM(pfx,modrm) ) );
+ t3 = t2 = t1 = t0 = IRTemp_INVALID;
+ breakupV128to32s( xmm_vec, &t3, &t2, &t1, &t0 );
+
+ if ( epartIsReg( modrm ) ) {
+ imm8 = (Int)getUChar(delta+1);
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8 = (Int)getUChar(delta+alen);
+ }
+ switch ( (imm8 >> 2) & 3 ) {
+ case 0: assign( sel_lane, mkexpr(t0) ); break;
+ case 1: assign( sel_lane, mkexpr(t1) ); break;
+ case 2: assign( sel_lane, mkexpr(t2) ); break;
+ case 3: assign( sel_lane, mkexpr(t3) ); break;
+ default: vassert(0);
+ }
+ assign( shr_lane,
+ binop( Iop_Shr32, mkexpr(sel_lane), mkU8(((imm8 & 3)*8)) ) );
+
+ if ( epartIsReg( modrm ) ) {
+ putIReg64( eregOfRexRM(pfx,modrm),
+ unop( Iop_32Uto64,
+ binop(Iop_And32, mkexpr(shr_lane), mkU32(255)) ) );
+ delta += 1+1;
+ DIP( "%spextrb $%d, %s,%s\n", mbV, imm8,
+ nameXMMReg( gregOfRexRM(pfx, modrm) ),
+ nameIReg64( eregOfRexRM(pfx, modrm) ) );
+ } else {
+ storeLE( mkexpr(addr), unop(Iop_32to8, mkexpr(shr_lane) ) );
+ delta += alen+1;
+ DIP( "%spextrb $%d,%s,%s\n", mbV,
+ imm8, nameXMMReg( gregOfRexRM(pfx, modrm) ), dis_buf );
+ }
+
+ return delta;
+}
+
+
+static IRTemp math_DPPD_128 ( IRTemp src_vec, IRTemp dst_vec, UInt imm8 )
+{
+ vassert(imm8 < 256);
+ UShort imm8_perms[4] = { 0x0000, 0x00FF, 0xFF00, 0xFFFF };
+ IRTemp and_vec = newTemp(Ity_V128);
+ IRTemp sum_vec = newTemp(Ity_V128);
+ assign( and_vec, binop( Iop_AndV128,
+ binop( Iop_Mul64Fx2,
+ mkexpr(dst_vec), mkexpr(src_vec) ),
+ mkV128( imm8_perms[ ((imm8 >> 4) & 3) ] ) ) );
+
+ assign( sum_vec, binop( Iop_Add64F0x2,
+ binop( Iop_InterleaveHI64x2,
+ mkexpr(and_vec), mkexpr(and_vec) ),
+ binop( Iop_InterleaveLO64x2,
+ mkexpr(and_vec), mkexpr(and_vec) ) ) );
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop( Iop_AndV128,
+ binop( Iop_InterleaveLO64x2,
+ mkexpr(sum_vec), mkexpr(sum_vec) ),
+ mkV128( imm8_perms[ (imm8 & 3) ] ) ) );
+ return res;
+}
+
+
+static IRTemp math_DPPS_128 ( IRTemp src_vec, IRTemp dst_vec, UInt imm8 )
+{
+ vassert(imm8 < 256);
+ IRTemp tmp_prod_vec = newTemp(Ity_V128);
+ IRTemp prod_vec = newTemp(Ity_V128);
+ IRTemp sum_vec = newTemp(Ity_V128);
+ IRTemp v3, v2, v1, v0;
+ v3 = v2 = v1 = v0 = IRTemp_INVALID;
+ UShort imm8_perms[16] = { 0x0000, 0x000F, 0x00F0, 0x00FF, 0x0F00,
+ 0x0F0F, 0x0FF0, 0x0FFF, 0xF000, 0xF00F,
+ 0xF0F0, 0xF0FF, 0xFF00, 0xFF0F, 0xFFF0,
+ 0xFFFF };
+
+ assign( tmp_prod_vec,
+ binop( Iop_AndV128,
+ binop( Iop_Mul32Fx4, mkexpr(dst_vec),
+ mkexpr(src_vec) ),
+ mkV128( imm8_perms[((imm8 >> 4)& 15)] ) ) );
+ breakupV128to32s( tmp_prod_vec, &v3, &v2, &v1, &v0 );
+ assign( prod_vec, mkV128from32s( v3, v1, v2, v0 ) );
+
+ assign( sum_vec, binop( Iop_Add32Fx4,
+ binop( Iop_InterleaveHI32x4,
+ mkexpr(prod_vec), mkexpr(prod_vec) ),
+ binop( Iop_InterleaveLO32x4,
+ mkexpr(prod_vec), mkexpr(prod_vec) ) ) );
+
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop( Iop_AndV128,
+ binop( Iop_Add32Fx4,
+ binop( Iop_InterleaveHI32x4,
+ mkexpr(sum_vec), mkexpr(sum_vec) ),
+ binop( Iop_InterleaveLO32x4,
+ mkexpr(sum_vec), mkexpr(sum_vec) ) ),
+ mkV128( imm8_perms[ (imm8 & 15) ] ) ) );
+ return res;
+}
+
+
+static IRTemp math_MPSADBW_128 ( IRTemp dst_vec, IRTemp src_vec, UInt imm8 )
+{
+ /* Mask out bits of the operands we don't need. This isn't
+ strictly necessary, but it does ensure Memcheck doesn't
+ give us any false uninitialised value errors as a
+ result. */
+ UShort src_mask[4] = { 0x000F, 0x00F0, 0x0F00, 0xF000 };
+ UShort dst_mask[2] = { 0x07FF, 0x7FF0 };
+
+ IRTemp src_maskV = newTemp(Ity_V128);
+ IRTemp dst_maskV = newTemp(Ity_V128);
+ assign(src_maskV, mkV128( src_mask[ imm8 & 3 ] ));
+ assign(dst_maskV, mkV128( dst_mask[ (imm8 >> 2) & 1 ] ));
+
+ IRTemp src_masked = newTemp(Ity_V128);
+ IRTemp dst_masked = newTemp(Ity_V128);
+ assign(src_masked, binop(Iop_AndV128, mkexpr(src_vec), mkexpr(src_maskV)));
+ assign(dst_masked, binop(Iop_AndV128, mkexpr(dst_vec), mkexpr(dst_maskV)));
+
+ /* Generate 4 64 bit values that we can hand to a clean helper */
+ IRTemp sHi = newTemp(Ity_I64);
+ IRTemp sLo = newTemp(Ity_I64);
+ assign( sHi, unop(Iop_V128HIto64, mkexpr(src_masked)) );
+ assign( sLo, unop(Iop_V128to64, mkexpr(src_masked)) );
+
+ IRTemp dHi = newTemp(Ity_I64);
+ IRTemp dLo = newTemp(Ity_I64);
+ assign( dHi, unop(Iop_V128HIto64, mkexpr(dst_masked)) );
+ assign( dLo, unop(Iop_V128to64, mkexpr(dst_masked)) );
+
+ /* Compute halves of the result separately */
+ IRTemp resHi = newTemp(Ity_I64);
+ IRTemp resLo = newTemp(Ity_I64);
+
+ IRExpr** argsHi
+ = mkIRExprVec_5( mkexpr(sHi), mkexpr(sLo), mkexpr(dHi), mkexpr(dLo),
+ mkU64( 0x80 | (imm8 & 7) ));
+ IRExpr** argsLo
+ = mkIRExprVec_5( mkexpr(sHi), mkexpr(sLo), mkexpr(dHi), mkexpr(dLo),
+ mkU64( 0x00 | (imm8 & 7) ));
+
+ assign(resHi, mkIRExprCCall( Ity_I64, 0/*regparm*/,
+ "amd64g_calc_mpsadbw",
+ &amd64g_calc_mpsadbw, argsHi ));
+ assign(resLo, mkIRExprCCall( Ity_I64, 0/*regparm*/,
+ "amd64g_calc_mpsadbw",
+ &amd64g_calc_mpsadbw, argsLo ));
+
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128, mkexpr(resHi), mkexpr(resLo)));
+ return res;
+}
+
+static Long dis_EXTRACTPS ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool isAvx )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ Int imm8_10;
+ IRTemp xmm_vec = newTemp(Ity_V128);
+ IRTemp src_dword = newTemp(Ity_I32);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp t3, t2, t1, t0;
+ t3 = t2 = t1 = t0 = IRTemp_INVALID;
+
+ assign( xmm_vec, getXMMReg( rG ) );
+ breakupV128to32s( xmm_vec, &t3, &t2, &t1, &t0 );
+
+ if ( epartIsReg( modrm ) ) {
+ imm8_10 = (Int)(getUChar(delta+1) & 3);
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8_10 = (Int)(getUChar(delta+alen) & 3);
+ }
+
+ switch ( imm8_10 ) {
+ case 0: assign( src_dword, mkexpr(t0) ); break;
+ case 1: assign( src_dword, mkexpr(t1) ); break;
+ case 2: assign( src_dword, mkexpr(t2) ); break;
+ case 3: assign( src_dword, mkexpr(t3) ); break;
+ default: vassert(0);
+ }
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putIReg32( rE, mkexpr(src_dword) );
+ delta += 1+1;
+ DIP( "%sextractps $%d, %s,%s\n", isAvx ? "v" : "", imm8_10,
+ nameXMMReg( rG ), nameIReg32( rE ) );
+ } else {
+ storeLE( mkexpr(addr), mkexpr(src_dword) );
+ delta += alen+1;
+ DIP( "%sextractps $%d, %s,%s\n", isAvx ? "v" : "", imm8_10,
+ nameXMMReg( rG ), dis_buf );
+ }
+
+ return delta;
+}
+
+
+static IRTemp math_PCLMULQDQ( IRTemp dV, IRTemp sV, UInt imm8 )
+{
+ IRTemp t0 = newTemp(Ity_I64);
+ IRTemp t1 = newTemp(Ity_I64);
+ assign(t0, unop((imm8&1)? Iop_V128HIto64 : Iop_V128to64,
+ mkexpr(dV)));
+ assign(t1, unop((imm8&16) ? Iop_V128HIto64 : Iop_V128to64,
+ mkexpr(sV)));
+
+ IRTemp t2 = newTemp(Ity_I64);
+ IRTemp t3 = newTemp(Ity_I64);
+
+ IRExpr** args;
+
+ args = mkIRExprVec_3(mkexpr(t0), mkexpr(t1), mkU64(0));
+ assign(t2, mkIRExprCCall(Ity_I64,0, "amd64g_calculate_pclmul",
+ &amd64g_calculate_pclmul, args));
+ args = mkIRExprVec_3(mkexpr(t0), mkexpr(t1), mkU64(1));
+ assign(t3, mkIRExprCCall(Ity_I64,0, "amd64g_calculate_pclmul",
+ &amd64g_calculate_pclmul, args));
+
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128, mkexpr(t3), mkexpr(t2)));
+ return res;
+}
+
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F3A__SSE4 ( Bool* decode_OK,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN )
+{
+ IRTemp addr = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
+
+ *decode_OK = False;
+
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) {
+
+ case 0x08:
+ /* 66 0F 3A 08 /r ib = ROUNDPS imm8, xmm2/m128, xmm1 */
+ if (have66noF2noF3(pfx) && sz == 2) {
+
+ IRTemp src0 = newTemp(Ity_F32);
+ IRTemp src1 = newTemp(Ity_F32);
+ IRTemp src2 = newTemp(Ity_F32);
+ IRTemp src3 = newTemp(Ity_F32);
+ IRTemp res0 = newTemp(Ity_F32);
+ IRTemp res1 = newTemp(Ity_F32);
+ IRTemp res2 = newTemp(Ity_F32);
+ IRTemp res3 = newTemp(Ity_F32);
+ IRTemp rm = newTemp(Ity_I32);
+ Int imm = 0;
+
+ modrm = getUChar(delta);
+
+ if (epartIsReg(modrm)) {
+ assign( src0,
+ getXMMRegLane32F( eregOfRexRM(pfx, modrm), 0 ) );
+ assign( src1,
+ getXMMRegLane32F( eregOfRexRM(pfx, modrm), 1 ) );
+ assign( src2,
+ getXMMRegLane32F( eregOfRexRM(pfx, modrm), 2 ) );
+ assign( src3,
+ getXMMRegLane32F( eregOfRexRM(pfx, modrm), 3 ) );
+ imm = getUChar(delta+1);
+ if (imm & ~15) goto decode_failure;
+ delta += 1+1;
+ DIP( "roundps $%d,%s,%s\n",
+ imm, nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ gen_SEGV_if_not_16_aligned(addr);
+ assign( src0, loadLE(Ity_F32,
+ binop(Iop_Add64, mkexpr(addr), mkU64(0) )));
+ assign( src1, loadLE(Ity_F32,
+ binop(Iop_Add64, mkexpr(addr), mkU64(4) )));
+ assign( src2, loadLE(Ity_F32,
+ binop(Iop_Add64, mkexpr(addr), mkU64(8) )));
+ assign( src3, loadLE(Ity_F32,
+ binop(Iop_Add64, mkexpr(addr), mkU64(12) )));
+ imm = getUChar(delta+alen);
+ if (imm & ~15) goto decode_failure;
+ delta += alen+1;
+ DIP( "roundps $%d,%s,%s\n",
+ imm, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ /* (imm & 3) contains an Intel-encoded rounding mode. Because
+ that encoding is the same as the encoding for IRRoundingMode,
+ we can use that value directly in the IR as a rounding
+ mode. */
+ assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
+
+ assign(res0, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src0)) );
+ assign(res1, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src1)) );
+ assign(res2, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src2)) );
+ assign(res3, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src3)) );
+
+ putXMMRegLane32F( gregOfRexRM(pfx, modrm), 0, mkexpr(res0) );
+ putXMMRegLane32F( gregOfRexRM(pfx, modrm), 1, mkexpr(res1) );
+ putXMMRegLane32F( gregOfRexRM(pfx, modrm), 2, mkexpr(res2) );
+ putXMMRegLane32F( gregOfRexRM(pfx, modrm), 3, mkexpr(res3) );
+
+ goto decode_success;
+ }
+ break;
+
+ case 0x09:
+ /* 66 0F 3A 09 /r ib = ROUNDPD imm8, xmm2/m128, xmm1 */
+ if (have66noF2noF3(pfx) && sz == 2) {
+
+ IRTemp src0 = newTemp(Ity_F64);
+ IRTemp src1 = newTemp(Ity_F64);
+ IRTemp res0 = newTemp(Ity_F64);
+ IRTemp res1 = newTemp(Ity_F64);
+ IRTemp rm = newTemp(Ity_I32);
+ Int imm = 0;
+
+ modrm = getUChar(delta);
+
+ if (epartIsReg(modrm)) {
+ assign( src0,
+ getXMMRegLane64F( eregOfRexRM(pfx, modrm), 0 ) );
+ assign( src1,
+ getXMMRegLane64F( eregOfRexRM(pfx, modrm), 1 ) );
+ imm = getUChar(delta+1);
+ if (imm & ~15) goto decode_failure;
+ delta += 1+1;
+ DIP( "roundpd $%d,%s,%s\n",
+ imm, nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ gen_SEGV_if_not_16_aligned(addr);
+ assign( src0, loadLE(Ity_F64,
+ binop(Iop_Add64, mkexpr(addr), mkU64(0) )));
+ assign( src1, loadLE(Ity_F64,
+ binop(Iop_Add64, mkexpr(addr), mkU64(8) )));
+ imm = getUChar(delta+alen);
+ if (imm & ~15) goto decode_failure;
+ delta += alen+1;
+ DIP( "roundpd $%d,%s,%s\n",
+ imm, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ /* (imm & 3) contains an Intel-encoded rounding mode. Because
+ that encoding is the same as the encoding for IRRoundingMode,
+ we can use that value directly in the IR as a rounding
+ mode. */
+ assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
+
+ assign(res0, binop(Iop_RoundF64toInt, mkexpr(rm), mkexpr(src0)) );
+ assign(res1, binop(Iop_RoundF64toInt, mkexpr(rm), mkexpr(src1)) );
+
+ putXMMRegLane64F( gregOfRexRM(pfx, modrm), 0, mkexpr(res0) );
+ putXMMRegLane64F( gregOfRexRM(pfx, modrm), 1, mkexpr(res1) );
+
+ goto decode_success;
+ }
+ break;
+
+ case 0x0A:
+ case 0x0B:
+ /* 66 0F 3A 0A /r ib = ROUNDSS imm8, xmm2/m32, xmm1
+ 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1
+ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+
+ Bool isD = opc == 0x0B;
+ IRTemp src = newTemp(isD ? Ity_F64 : Ity_F32);
+ IRTemp res = newTemp(isD ? Ity_F64 : Ity_F32);
+ Int imm = 0;
+
+ modrm = getUChar(delta);
+
+ if (epartIsReg(modrm)) {
+ assign( src,
+ isD ? getXMMRegLane64F( eregOfRexRM(pfx, modrm), 0 )
+ : getXMMRegLane32F( eregOfRexRM(pfx, modrm), 0 ) );
+ imm = getUChar(delta+1);
+ if (imm & ~15) goto decode_failure;
+ delta += 1+1;
+ DIP( "rounds%c $%d,%s,%s\n",
+ isD ? 'd' : 's',
+ imm, nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( src, loadLE( isD ? Ity_F64 : Ity_F32, mkexpr(addr) ));
+ imm = getUChar(delta+alen);
+ if (imm & ~15) goto decode_failure;
+ delta += alen+1;
+ DIP( "rounds%c $%d,%s,%s\n",
+ isD ? 'd' : 's',
+ imm, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ /* (imm & 3) contains an Intel-encoded rounding mode. Because
+ that encoding is the same as the encoding for IRRoundingMode,
+ we can use that value directly in the IR as a rounding
+ mode. */
+ assign(res, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+ (imm & 4) ? get_sse_roundingmode()
+ : mkU32(imm & 3),
+ mkexpr(src)) );
+
+ if (isD)
+ putXMMRegLane64F( gregOfRexRM(pfx, modrm), 0, mkexpr(res) );
+ else
+ putXMMRegLane32F( gregOfRexRM(pfx, modrm), 0, mkexpr(res) );
+
+ goto decode_success;
+ }
+ break;
+
+ case 0x0C:
+ /* 66 0F 3A 0C /r ib = BLENDPS xmm1, xmm2/m128, imm8
+ Blend Packed Single Precision Floating-Point Values (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+
+ Int imm8;
+ IRTemp dst_vec = newTemp(Ity_V128);
+ IRTemp src_vec = newTemp(Ity_V128);
+
+ modrm = getUChar(delta);
+
+ assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
+
+ if ( epartIsReg( modrm ) ) {
+ imm8 = (Int)getUChar(delta+1);
+ assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
+ delta += 1+1;
+ DIP( "blendps $%d, %s,%s\n", imm8,
+ nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "blendpd $%d, %s,%s\n",
+ imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ putXMMReg( gregOfRexRM(pfx, modrm),
+ mkexpr( math_BLENDPS_128( src_vec, dst_vec, imm8) ) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x0D:
+ /* 66 0F 3A 0D /r ib = BLENDPD xmm1, xmm2/m128, imm8
+ Blend Packed Double Precision Floating-Point Values (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+
+ Int imm8;
+ IRTemp dst_vec = newTemp(Ity_V128);
+ IRTemp src_vec = newTemp(Ity_V128);
+
+ modrm = getUChar(delta);
+ assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
+
+ if ( epartIsReg( modrm ) ) {
+ imm8 = (Int)getUChar(delta+1);
+ assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
+ delta += 1+1;
+ DIP( "blendpd $%d, %s,%s\n", imm8,
+ nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "blendpd $%d, %s,%s\n",
+ imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ putXMMReg( gregOfRexRM(pfx, modrm),
+ mkexpr( math_BLENDPD_128( src_vec, dst_vec, imm8) ) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x0E:
+ /* 66 0F 3A 0E /r ib = PBLENDW xmm1, xmm2/m128, imm8
+ Blend Packed Words (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+
+ Int imm8;
+ IRTemp dst_vec = newTemp(Ity_V128);
+ IRTemp src_vec = newTemp(Ity_V128);
+
+ modrm = getUChar(delta);
+
+ assign( dst_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
+
+ if ( epartIsReg( modrm ) ) {
+ imm8 = (Int)getUChar(delta+1);
+ assign( src_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
+ delta += 1+1;
+ DIP( "pblendw $%d, %s,%s\n", imm8,
+ nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "pblendw $%d, %s,%s\n",
+ imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ putXMMReg( gregOfRexRM(pfx, modrm),
+ mkexpr( math_PBLENDW_128( src_vec, dst_vec, imm8) ) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x14:
+ /* 66 0F 3A 14 /r ib = PEXTRB r/m16, xmm, imm8
+ Extract Byte from xmm, store in mem or zero-extend + store in gen.reg.
+ (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PEXTRB_128_GtoE( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x15:
+ /* 66 0F 3A 15 /r ib = PEXTRW r/m16, xmm, imm8
+ Extract Word from xmm, store in mem or zero-extend + store in gen.reg.
+ (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_PEXTRW( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x16:
+ /* 66 no-REX.W 0F 3A 16 /r ib = PEXTRD reg/mem32, xmm2, imm8
+ Extract Doubleword int from xmm reg and store in gen.reg or mem. (XMM)
+ Note that this insn has the same opcodes as PEXTRQ, but
+ here the REX.W bit is _not_ present */
+ if (have66noF2noF3(pfx)
+ && sz == 2 /* REX.W is _not_ present */) {
+ delta = dis_PEXTRD( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ /* 66 REX.W 0F 3A 16 /r ib = PEXTRQ reg/mem64, xmm2, imm8
+ Extract Quadword int from xmm reg and store in gen.reg or mem. (XMM)
+ Note that this insn has the same opcodes as PEXTRD, but
+ here the REX.W bit is present */
+ if (have66noF2noF3(pfx)
+ && sz == 8 /* REX.W is present */) {
+ delta = dis_PEXTRQ( vbi, pfx, delta, False/*!isAvx*/);
+ goto decode_success;
+ }
+ break;
+
+ case 0x17:
+ /* 66 0F 3A 17 /r ib = EXTRACTPS reg/mem32, xmm2, imm8 Extract
+ float from xmm reg and store in gen.reg or mem. This is
+ identical to PEXTRD, except that REX.W appears to be ignored.
+ */
+ if (have66noF2noF3(pfx)
+ && (sz == 2 || /* ignore redundant REX.W */ sz == 8)) {
+ delta = dis_EXTRACTPS( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x20:
+ /* 66 0F 3A 20 /r ib = PINSRB xmm1, r32/m8, imm8
+ Extract byte from r32/m8 and insert into xmm1 */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ Int imm8;
+ IRTemp new8 = newTemp(Ity_I8);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ imm8 = (Int)(getUChar(delta+1) & 0xF);
+ assign( new8, unop(Iop_32to8, getIReg32(rE)) );
+ delta += 1+1;
+ DIP( "pinsrb $%d,%s,%s\n", imm8,
+ nameIReg32(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8 = (Int)(getUChar(delta+alen) & 0xF);
+ assign( new8, loadLE( Ity_I8, mkexpr(addr) ) );
+ delta += alen+1;
+ DIP( "pinsrb $%d,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rG) );
+ }
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg( gregOfRexRM(pfx, modrm) ));
+ IRTemp res = math_PINSRB_128( src_vec, new8, imm8 );
+ putXMMReg( rG, mkexpr(res) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x21:
+ /* 66 0F 3A 21 /r ib = INSERTPS imm8, xmm2/m32, xmm1
+ Insert Packed Single Precision Floating-Point Value (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ UInt imm8;
+ IRTemp d2ins = newTemp(Ity_I32); /* comes from the E part */
+ const IRTemp inval = IRTemp_INVALID;
+
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ IRTemp vE = newTemp(Ity_V128);
+ assign( vE, getXMMReg(rE) );
+ IRTemp dsE[4] = { inval, inval, inval, inval };
+ breakupV128to32s( vE, &dsE[3], &dsE[2], &dsE[1], &dsE[0] );
+ imm8 = getUChar(delta+1);
+ d2ins = dsE[(imm8 >> 6) & 3]; /* "imm8_count_s" */
+ delta += 1+1;
+ DIP( "insertps $%u, %s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( d2ins, loadLE( Ity_I32, mkexpr(addr) ) );
+ imm8 = getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "insertps $%u, %s,%s\n",
+ imm8, dis_buf, nameXMMReg(rG) );
+ }
+
+ IRTemp vG = newTemp(Ity_V128);
+ assign( vG, getXMMReg(rG) );
+
+ putXMMReg( rG, mkexpr(math_INSERTPS( vG, d2ins, imm8 )) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x22:
+ /* 66 no-REX.W 0F 3A 22 /r ib = PINSRD xmm1, r/m32, imm8
+ Extract Doubleword int from gen.reg/mem32 and insert into xmm1 */
+ if (have66noF2noF3(pfx)
+ && sz == 2 /* REX.W is NOT present */) {
+ Int imm8_10;
+ IRTemp src_u32 = newTemp(Ity_I32);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ imm8_10 = (Int)(getUChar(delta+1) & 3);
+ assign( src_u32, getIReg32( rE ) );
+ delta += 1+1;
+ DIP( "pinsrd $%d, %s,%s\n",
+ imm8_10, nameIReg32(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8_10 = (Int)(getUChar(delta+alen) & 3);
+ assign( src_u32, loadLE( Ity_I32, mkexpr(addr) ) );
+ delta += alen+1;
+ DIP( "pinsrd $%d, %s,%s\n",
+ imm8_10, dis_buf, nameXMMReg(rG) );
+ }
+
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg( rG ));
+ IRTemp res_vec = math_PINSRD_128( src_vec, src_u32, imm8_10 );
+ putXMMReg( rG, mkexpr(res_vec) );
+ goto decode_success;
+ }
+ /* 66 REX.W 0F 3A 22 /r ib = PINSRQ xmm1, r/m64, imm8
+ Extract Quadword int from gen.reg/mem64 and insert into xmm1 */
+ if (have66noF2noF3(pfx)
+ && sz == 8 /* REX.W is present */) {
+ Int imm8_0;
+ IRTemp src_u64 = newTemp(Ity_I64);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ imm8_0 = (Int)(getUChar(delta+1) & 1);
+ assign( src_u64, getIReg64( rE ) );
+ delta += 1+1;
+ DIP( "pinsrq $%d, %s,%s\n",
+ imm8_0, nameIReg64(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8_0 = (Int)(getUChar(delta+alen) & 1);
+ assign( src_u64, loadLE( Ity_I64, mkexpr(addr) ) );
+ delta += alen+1;
+ DIP( "pinsrq $%d, %s,%s\n",
+ imm8_0, dis_buf, nameXMMReg(rG) );
+ }
+
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg( rG ));
+ IRTemp res_vec = math_PINSRQ_128( src_vec, src_u64, imm8_0 );
+ putXMMReg( rG, mkexpr(res_vec) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x40:
+ /* 66 0F 3A 40 /r ib = DPPS xmm1, xmm2/m128, imm8
+ Dot Product of Packed Single Precision Floating-Point Values (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ modrm = getUChar(delta);
+ Int imm8;
+ IRTemp src_vec = newTemp(Ity_V128);
+ IRTemp dst_vec = newTemp(Ity_V128);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ assign( dst_vec, getXMMReg( rG ) );
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ imm8 = (Int)getUChar(delta+1);
+ assign( src_vec, getXMMReg(rE) );
+ delta += 1+1;
+ DIP( "dpps $%d, %s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "dpps $%d, %s,%s\n",
+ imm8, dis_buf, nameXMMReg(rG) );
+ }
+ IRTemp res = math_DPPS_128( src_vec, dst_vec, imm8 );
+ putXMMReg( rG, mkexpr(res) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x41:
+ /* 66 0F 3A 41 /r ib = DPPD xmm1, xmm2/m128, imm8
+ Dot Product of Packed Double Precision Floating-Point Values (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ modrm = getUChar(delta);
+ Int imm8;
+ IRTemp src_vec = newTemp(Ity_V128);
+ IRTemp dst_vec = newTemp(Ity_V128);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ assign( dst_vec, getXMMReg( rG ) );
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ imm8 = (Int)getUChar(delta+1);
+ assign( src_vec, getXMMReg(rE) );
+ delta += 1+1;
+ DIP( "dppd $%d, %s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "dppd $%d, %s,%s\n",
+ imm8, dis_buf, nameXMMReg(rG) );
+ }
+ IRTemp res = math_DPPD_128( src_vec, dst_vec, imm8 );
+ putXMMReg( rG, mkexpr(res) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x42:
+ /* 66 0F 3A 42 /r ib = MPSADBW xmm1, xmm2/m128, imm8
+ Multiple Packed Sums of Absolule Difference (XMM) */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ Int imm8;
+ IRTemp src_vec = newTemp(Ity_V128);
+ IRTemp dst_vec = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ assign( dst_vec, getXMMReg(rG) );
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+
+ imm8 = (Int)getUChar(delta+1);
+ assign( src_vec, getXMMReg(rE) );
+ delta += 1+1;
+ DIP( "mpsadbw $%d, %s,%s\n", imm8,
+ nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "mpsadbw $%d, %s,%s\n", imm8, dis_buf, nameXMMReg(rG) );
+ }
+
+ putXMMReg( rG, mkexpr( math_MPSADBW_128(dst_vec, src_vec, imm8) ) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x44:
+ /* 66 0F 3A 44 /r ib = PCLMULQDQ xmm1, xmm2/m128, imm8
+ * Carry-less multiplication of selected XMM quadwords into XMM
+ * registers (a.k.a multiplication of polynomials over GF(2))
+ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+
+ Int imm8;
+ IRTemp svec = newTemp(Ity_V128);
+ IRTemp dvec = newTemp(Ity_V128);
+ modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+
+ assign( dvec, getXMMReg(rG) );
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ imm8 = (Int)getUChar(delta+1);
+ assign( svec, getXMMReg(rE) );
+ delta += 1+1;
+ DIP( "pclmulqdq $%d, %s,%s\n", imm8,
+ nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ gen_SEGV_if_not_16_aligned( addr );
+ assign( svec, loadLE( Ity_V128, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "pclmulqdq $%d, %s,%s\n",
+ imm8, dis_buf, nameXMMReg(rG) );
+ }
+
+ putXMMReg( rG, mkexpr( math_PCLMULQDQ(dvec, svec, imm8) ) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x60:
+ case 0x61:
+ case 0x62:
+ case 0x63:
+ /* 66 0F 3A 63 /r ib = PCMPISTRI imm8, xmm2/m128, xmm1
+ 66 0F 3A 62 /r ib = PCMPISTRM imm8, xmm2/m128, xmm1
+ 66 0F 3A 61 /r ib = PCMPESTRI imm8, xmm2/m128, xmm1
+ 66 0F 3A 60 /r ib = PCMPESTRM imm8, xmm2/m128, xmm1
+ (selected special cases that actually occur in glibc,
+ not by any means a complete implementation.)
+ */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ Long delta0 = delta;
+ delta = dis_PCMPxSTRx( vbi, pfx, delta, False/*!isAvx*/, opc );
+ if (delta > delta0) goto decode_success;
+ /* else fall though; dis_PCMPxSTRx failed to decode it */
+ }
+ break;
+
+ case 0xDF:
+ /* 66 0F 3A DF /r ib = AESKEYGENASSIST imm8, xmm2/m128, xmm1 */
+ if (have66noF2noF3(pfx) && sz == 2) {
+ delta = dis_AESKEYGENASSIST( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ default:
+ break;
+
+ }
+
+ decode_failure:
+ *decode_OK = False;
+ return deltaIN;
+
+ decode_success:
+ *decode_OK = True;
+ return delta;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level post-escape decoders: dis_ESC_NONE ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+__attribute__((noinline))
+static
+Long dis_ESC_NONE (
+ /*MB_OUT*/DisResult* dres,
+ /*MB_OUT*/Bool* expect_CAS,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN
+ )
+{
+ Long d64 = 0;
+ UChar abyte = 0;
+ IRTemp addr = IRTemp_INVALID;
+ IRTemp t1 = IRTemp_INVALID;
+ IRTemp t2 = IRTemp_INVALID;
+ IRTemp t3 = IRTemp_INVALID;
+ IRTemp t4 = IRTemp_INVALID;
+ IRTemp t5 = IRTemp_INVALID;
+ IRType ty = Ity_INVALID;
+ UChar modrm = 0;
+ Int am_sz = 0;
+ Int d_sz = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
+
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) {
+
+ case 0x00: /* ADD Gb,Eb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Add8, True, 1, delta, "add" );
+ return delta;
+ case 0x01: /* ADD Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Add8, True, sz, delta, "add" );
+ return delta;
+
+ case 0x02: /* ADD Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Add8, True, 1, delta, "add" );
+ return delta;
+ case 0x03: /* ADD Ev,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Add8, True, sz, delta, "add" );
+ return delta;
+
+ case 0x04: /* ADD Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( 1, False, Iop_Add8, True, delta, "add" );
+ return delta;
+ case 0x05: /* ADD Iv, eAX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A(sz, False, Iop_Add8, True, delta, "add" );
+ return delta;
+
+ case 0x08: /* OR Gb,Eb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Or8, True, 1, delta, "or" );
+ return delta;
+ case 0x09: /* OR Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Or8, True, sz, delta, "or" );
+ return delta;
+
+ case 0x0A: /* OR Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Or8, True, 1, delta, "or" );
+ return delta;
+ case 0x0B: /* OR Ev,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Or8, True, sz, delta, "or" );
+ return delta;
+
+ case 0x0C: /* OR Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( 1, False, Iop_Or8, True, delta, "or" );
+ return delta;
+ case 0x0D: /* OR Iv, eAX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( sz, False, Iop_Or8, True, delta, "or" );
+ return delta;
+
+ case 0x10: /* ADC Gb,Eb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, True, Iop_Add8, True, 1, delta, "adc" );
+ return delta;
+ case 0x11: /* ADC Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" );
+ return delta;
+
+ case 0x12: /* ADC Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, 1, delta, "adc" );
+ return delta;
+ case 0x13: /* ADC Ev,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" );
+ return delta;
+
+ case 0x14: /* ADC Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( 1, True, Iop_Add8, True, delta, "adc" );
+ return delta;
+ case 0x15: /* ADC Iv, eAX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( sz, True, Iop_Add8, True, delta, "adc" );
+ return delta;
+
+ case 0x18: /* SBB Gb,Eb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
+ return delta;
+ case 0x19: /* SBB Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
+ return delta;
+
+ case 0x1A: /* SBB Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
+ return delta;
+ case 0x1B: /* SBB Ev,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
+ return delta;
+
+ case 0x1C: /* SBB Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( 1, True, Iop_Sub8, True, delta, "sbb" );
+ return delta;
+ case 0x1D: /* SBB Iv, eAX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( sz, True, Iop_Sub8, True, delta, "sbb" );
+ return delta;
+
+ case 0x20: /* AND Gb,Eb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_And8, True, 1, delta, "and" );
+ return delta;
+ case 0x21: /* AND Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_And8, True, sz, delta, "and" );
+ return delta;
+
+ case 0x22: /* AND Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, True, 1, delta, "and" );
+ return delta;
+ case 0x23: /* AND Ev,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, True, sz, delta, "and" );
+ return delta;
+
+ case 0x24: /* AND Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( 1, False, Iop_And8, True, delta, "and" );
+ return delta;
+ case 0x25: /* AND Iv, eAX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( sz, False, Iop_And8, True, delta, "and" );
+ return delta;
+
+ case 0x28: /* SUB Gb,Eb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, True, 1, delta, "sub" );
+ return delta;
+ case 0x29: /* SUB Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, True, sz, delta, "sub" );
+ return delta;
+
+ case 0x2A: /* SUB Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, True, 1, delta, "sub" );
+ return delta;
+ case 0x2B: /* SUB Ev,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, True, sz, delta, "sub" );
+ return delta;
+
+ case 0x2C: /* SUB Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A(1, False, Iop_Sub8, True, delta, "sub" );
+ return delta;
+
+ case 0x2D: /* SUB Iv, eAX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( sz, False, Iop_Sub8, True, delta, "sub" );
+ return delta;
+
+ case 0x30: /* XOR Gb,Eb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Xor8, True, 1, delta, "xor" );
+ return delta;
+ case 0x31: /* XOR Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Xor8, True, sz, delta, "xor" );
+ return delta;
+
+ case 0x32: /* XOR Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Xor8, True, 1, delta, "xor" );
+ return delta;
+ case 0x33: /* XOR Ev,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Xor8, True, sz, delta, "xor" );
+ return delta;
+
+ case 0x34: /* XOR Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( 1, False, Iop_Xor8, True, delta, "xor" );
+ return delta;
+ case 0x35: /* XOR Iv, eAX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( sz, False, Iop_Xor8, True, delta, "xor" );
+ return delta;
+
+ case 0x38: /* CMP Gb,Eb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, False, 1, delta, "cmp" );
+ return delta;
+ case 0x39: /* CMP Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, False, sz, delta, "cmp" );
+ return delta;
+
+ case 0x3A: /* CMP Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, False, 1, delta, "cmp" );
+ return delta;
+ case 0x3B: /* CMP Ev,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, False, sz, delta, "cmp" );
+ return delta;
+
+ case 0x3C: /* CMP Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( 1, False, Iop_Sub8, False, delta, "cmp" );
+ return delta;
+ case 0x3D: /* CMP Iv, eAX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( sz, False, Iop_Sub8, False, delta, "cmp" );
+ return delta;
+
+ case 0x50: /* PUSH eAX */
+ case 0x51: /* PUSH eCX */
+ case 0x52: /* PUSH eDX */
+ case 0x53: /* PUSH eBX */
+ case 0x55: /* PUSH eBP */
+ case 0x56: /* PUSH eSI */
+ case 0x57: /* PUSH eDI */
+ case 0x54: /* PUSH eSP */
+ /* This is the Right Way, in that the value to be pushed is
+ established before %rsp is changed, so that pushq %rsp
+ correctly pushes the old value. */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ vassert(sz == 2 || sz == 4 || sz == 8);
+ if (sz == 4)
+ sz = 8; /* there is no encoding for 32-bit push in 64-bit mode */
+ ty = sz==2 ? Ity_I16 : Ity_I64;
+ t1 = newTemp(ty);
+ t2 = newTemp(Ity_I64);
+ assign(t1, getIRegRexB(sz, pfx, opc-0x50));
+ assign(t2, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(sz)));
+ putIReg64(R_RSP, mkexpr(t2) );
+ storeLE(mkexpr(t2),mkexpr(t1));
+ DIP("push%c %s\n", nameISize(sz), nameIRegRexB(sz,pfx,opc-0x50));
+ return delta;
+
+ case 0x58: /* POP eAX */
+ case 0x59: /* POP eCX */
+ case 0x5A: /* POP eDX */
+ case 0x5B: /* POP eBX */
+ case 0x5D: /* POP eBP */
+ case 0x5E: /* POP eSI */
+ case 0x5F: /* POP eDI */
+ case 0x5C: /* POP eSP */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ vassert(sz == 2 || sz == 4 || sz == 8);
+ if (sz == 4)
+ sz = 8; /* there is no encoding for 32-bit pop in 64-bit mode */
+ t1 = newTemp(szToITy(sz));
+ t2 = newTemp(Ity_I64);
+ assign(t2, getIReg64(R_RSP));
+ assign(t1, loadLE(szToITy(sz),mkexpr(t2)));
+ putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t2), mkU64(sz)));
+ putIRegRexB(sz, pfx, opc-0x58, mkexpr(t1));
+ DIP("pop%c %s\n", nameISize(sz), nameIRegRexB(sz,pfx,opc-0x58));
+ return delta;
+
+ case 0x63: /* MOVSX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (haveREX(pfx) && 1==getRexW(pfx)) {
+ vassert(sz == 8);
+ /* movsx r/m32 to r64 */
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta++;
+ putIRegG(8, pfx, modrm,
+ unop(Iop_32Sto64,
+ getIRegE(4, pfx, modrm)));
+ DIP("movslq %s,%s\n",
+ nameIRegE(4, pfx, modrm),
+ nameIRegG(8, pfx, modrm));
+ return delta;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ putIRegG(8, pfx, modrm,
+ unop(Iop_32Sto64,
+ loadLE(Ity_I32, mkexpr(addr))));
+ DIP("movslq %s,%s\n", dis_buf,
+ nameIRegG(8, pfx, modrm));
+ return delta;
+ }
} else {
goto decode_failure;
}
- }
- /* ------------------------ INT ------------------------ */
-
- case 0xCC: /* INT 3 */
- jmp_lit(Ijk_SigTRAP, guest_RIP_bbstart + delta);
- dres.whatNext = Dis_StopHere;
- DIP("int $0x3\n");
- break;
-
- case 0xCD: { /* INT imm8 */
- IRJumpKind jk = Ijk_Boring;
- if (have66orF2orF3(pfx)) goto decode_failure;
- d64 = getUChar(delta); delta++;
- switch (d64) {
- case 32: jk = Ijk_Sys_int32; break;
- default: goto decode_failure;
- }
- guest_RIP_next_mustcheck = True;
- guest_RIP_next_assumed = guest_RIP_bbstart + delta;
- jmp_lit(jk, guest_RIP_next_assumed);
- /* It's important that all ArchRegs carry their up-to-date value
- at this point. So we declare an end-of-block here, which
- forces any TempRegs caching ArchRegs to be flushed. */
- dres.whatNext = Dis_StopHere;
- DIP("int $0x%02x\n", (UInt)d64);
- break;
- }
-
- /* ------------------------ Jcond, byte offset --------- */
-
- case 0xEB: /* Jb (jump, byte offset) */
+ case 0x68: /* PUSH Iv */
if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 4)
- goto decode_failure; /* JRS added 2004 July 11 */
- d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta);
- delta++;
- if (resteerOkFn(callback_opaque,d64)) {
- dres.whatNext = Dis_ResteerU;
- dres.continueAt = d64;
- } else {
- jmp_lit(Ijk_Boring,d64);
- dres.whatNext = Dis_StopHere;
- }
- DIP("jmp-8 0x%llx\n", d64);
- break;
+ /* Note, sz==4 is not possible in 64-bit mode. Hence ... */
+ if (sz == 4) sz = 8;
+ d64 = getSDisp(imin(4,sz),delta);
+ delta += imin(4,sz);
+ goto do_push_I;
- case 0xE9: /* Jv (jump, 16/32 offset) */
+ case 0x69: /* IMUL Iv, Ev, Gv */
if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 4)
- goto decode_failure; /* JRS added 2004 July 11 */
- d64 = (guest_RIP_bbstart+delta+sz) + getSDisp(sz,delta);
- delta += sz;
- if (resteerOkFn(callback_opaque,d64)) {
- dres.whatNext = Dis_ResteerU;
- dres.continueAt = d64;
- } else {
- jmp_lit(Ijk_Boring,d64);
- dres.whatNext = Dis_StopHere;
- }
- DIP("jmp 0x%llx\n", d64);
- break;
+ delta = dis_imul_I_E_G ( vbi, pfx, sz, delta, sz );
+ return delta;
+
+ case 0x6A: /* PUSH Ib, sign-extended to sz */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ /* Note, sz==4 is not possible in 64-bit mode. Hence ... */
+ if (sz == 4) sz = 8;
+ d64 = getSDisp8(delta); delta += 1;
+ goto do_push_I;
+ do_push_I:
+ ty = szToITy(sz);
+ t1 = newTemp(Ity_I64);
+ t2 = newTemp(ty);
+ assign( t1, binop(Iop_Sub64,getIReg64(R_RSP),mkU64(sz)) );
+ putIReg64(R_RSP, mkexpr(t1) );
+ /* stop mkU16 asserting if d32 is a negative 16-bit number
+ (bug #132813) */
+ if (ty == Ity_I16)
+ d64 &= 0xFFFF;
+ storeLE( mkexpr(t1), mkU(ty,d64) );
+ DIP("push%c $%lld\n", nameISize(sz), (Long)d64);
+ return delta;
+
+ case 0x6B: /* IMUL Ib, Ev, Gv */
+ delta = dis_imul_I_E_G ( vbi, pfx, sz, delta, 1 );
+ return delta;
case 0x70:
case 0x71:
- case 0x72: /* JBb/JNAEb (jump below) */
- case 0x73: /* JNBb/JAEb (jump not below) */
- case 0x74: /* JZb/JEb (jump zero) */
- case 0x75: /* JNZb/JNEb (jump not zero) */
- case 0x76: /* JBEb/JNAb (jump below or equal) */
- case 0x77: /* JNBEb/JAb (jump not below or equal) */
- case 0x78: /* JSb (jump negative) */
- case 0x79: /* JSb (jump not negative) */
- case 0x7A: /* JP (jump parity even) */
- case 0x7B: /* JNP/JPO (jump parity odd) */
- case 0x7C: /* JLb/JNGEb (jump less) */
- case 0x7D: /* JGEb/JNLb (jump greater or equal) */
- case 0x7E: /* JLEb/JNGb (jump less or equal) */
- case 0x7F: /* JGb/JNLEb (jump greater) */
- { Long jmpDelta;
+ case 0x72: /* JBb/JNAEb (jump below) */
+ case 0x73: /* JNBb/JAEb (jump not below) */
+ case 0x74: /* JZb/JEb (jump zero) */
+ case 0x75: /* JNZb/JNEb (jump not zero) */
+ case 0x76: /* JBEb/JNAb (jump below or equal) */
+ case 0x77: /* JNBEb/JAb (jump not below or equal) */
+ case 0x78: /* JSb (jump negative) */
+ case 0x79: /* JSb (jump not negative) */
+ case 0x7A: /* JP (jump parity even) */
+ case 0x7B: /* JNP/JPO (jump parity odd) */
+ case 0x7C: /* JLb/JNGEb (jump less) */
+ case 0x7D: /* JGEb/JNLb (jump greater or equal) */
+ case 0x7E: /* JLEb/JNGb (jump less or equal) */
+ case 0x7F: { /* JGb/JNLEb (jump greater) */
+ Long jmpDelta;
HChar* comment = "";
if (haveF2orF3(pfx)) goto decode_failure;
jmpDelta = getSDisp8(delta);
@@ -16522,9 +18437,10 @@
mk_amd64g_calculate_condition(
(AMD64Condcode)(1 ^ (opc - 0x70))),
Ijk_Boring,
- IRConst_U64(guest_RIP_bbstart+delta) ) );
- dres.whatNext = Dis_ResteerC;
- dres.continueAt = d64;
+ IRConst_U64(guest_RIP_bbstart+delta),
+ OFFB_RIP ) );
+ dres->whatNext = Dis_ResteerC;
+ dres->continueAt = d64;
comment = "(assumed taken)";
}
else
@@ -16540,137 +18456,118 @@
stmt( IRStmt_Exit(
mk_amd64g_calculate_condition((AMD64Condcode)(opc - 0x70)),
Ijk_Boring,
- IRConst_U64(d64) ) );
- dres.whatNext = Dis_ResteerC;
- dres.continueAt = guest_RIP_bbstart+delta;
+ IRConst_U64(d64),
+ OFFB_RIP ) );
+ dres->whatNext = Dis_ResteerC;
+ dres->continueAt = guest_RIP_bbstart+delta;
comment = "(assumed not taken)";
}
else {
/* Conservative default translation - end the block at this
point. */
- jcc_01( (AMD64Condcode)(opc - 0x70),
- guest_RIP_bbstart+delta,
- d64 );
- dres.whatNext = Dis_StopHere;
+ jcc_01( dres, (AMD64Condcode)(opc - 0x70),
+ guest_RIP_bbstart+delta, d64 );
+ vassert(dres->whatNext == Dis_StopHere);
}
DIP("j%s-8 0x%llx %s\n", name_AMD64Condcode(opc - 0x70), d64, comment);
- break;
- }
+ return delta;
+ }
- case 0xE3:
- /* JRCXZ or JECXZ, depending address size override. */
- if (have66orF2orF3(pfx)) goto decode_failure;
- d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta);
- delta++;
- if (haveASO(pfx)) {
- /* 32-bit */
- stmt( IRStmt_Exit( binop(Iop_CmpEQ64,
- unop(Iop_32Uto64, getIReg32(R_RCX)),
- mkU64(0)),
- Ijk_Boring,
- IRConst_U64(d64))
- );
- DIP("jecxz 0x%llx\n", d64);
- } else {
- /* 64-bit */
- stmt( IRStmt_Exit( binop(Iop_CmpEQ64,
- getIReg64(R_RCX),
- mkU64(0)),
- Ijk_Boring,
- IRConst_U64(d64))
- );
- DIP("jrcxz 0x%llx\n", d64);
- }
- break;
-
- case 0xE0: /* LOOPNE disp8: decrement count, jump if count != 0 && ZF==0 */
- case 0xE1: /* LOOPE disp8: decrement count, jump if count != 0 && ZF==1 */
- case 0xE2: /* LOOP disp8: decrement count, jump if count != 0 */
- { /* The docs say this uses rCX as a count depending on the
- address size override, not the operand one. */
- IRExpr* zbit = NULL;
- IRExpr* count = NULL;
- IRExpr* cond = NULL;
- HChar* xtra = NULL;
-
- if (have66orF2orF3(pfx) || 1==getRexW(pfx)) goto decode_failure;
- /* So at this point we've rejected any variants which appear to
- be governed by the usual operand-size modifiers. Hence only
- the address size prefix can have an effect. It changes the
- size from 64 (default) to 32. */
- d64 = guest_RIP_bbstart+delta+1 + getSDisp8(delta);
- delta++;
- if (haveASO(pfx)) {
- /* 64to32 of 64-bit get is merely a get-put improvement
- trick. */
- putIReg32(R_RCX, binop(Iop_Sub32,
- unop(Iop_64to32, getIReg64(R_RCX)),
- mkU32(1)));
- } else {
- putIReg64(R_RCX, binop(Iop_Sub64, getIReg64(R_RCX), mkU64(1)));
- }
-
- /* This is correct, both for 32- and 64-bit versions. If we're
- doing a 32-bit dec and the result is zero then the default
- zero extension rule will cause the upper 32 bits to be zero
- too. Hence a 64-bit check against zero is OK. */
- count = getIReg64(R_RCX);
- cond = binop(Iop_CmpNE64, count, mkU64(0));
- switch (opc) {
- case 0xE2:
- xtra = "";
- break;
- case 0xE1:
- xtra = "e";
- zbit = mk_amd64g_calculate_condition( AMD64CondZ );
- cond = mkAnd1(cond, zbit);
- break;
- case 0xE0:
- xtra = "ne";
- zbit = mk_amd64g_calculate_condition( AMD64CondNZ );
- cond = mkAnd1(cond, zbit);
- break;
- default:
- vassert(0);
- }
- stmt( IRStmt_Exit(cond, Ijk_Boring, IRConst_U64(d64)) );
-
- DIP("loop%s%s 0x%llx\n", xtra, haveASO(pfx) ? "l" : "", d64);
- break;
- }
-
- /* ------------------------ IMUL ----------------------- */
-
- case 0x69: /* IMUL Iv, Ev, Gv */
+ case 0x80: /* Grp1 Ib,Eb */
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_imul_I_E_G ( vbi, pfx, sz, delta, sz );
- break;
- case 0x6B: /* IMUL Ib, Ev, Gv */
- delta = dis_imul_I_E_G ( vbi, pfx, sz, delta, 1 );
- break;
+ modrm = getUChar(delta);
+ am_sz = lengthAMode(pfx,delta);
+ sz = 1;
+ d_sz = 1;
+ d64 = getSDisp8(delta + am_sz);
+ delta = dis_Grp1 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz, d64 );
+ return delta;
- /* ------------------------ MOV ------------------------ */
+ case 0x81: /* Grp1 Iv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ am_sz = lengthAMode(pfx,delta);
+ d_sz = imin(sz,4);
+ d64 = getSDisp(d_sz, delta + am_sz);
+ delta = dis_Grp1 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz, d64 );
+ return delta;
+
+ case 0x83: /* Grp1 Ib,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ am_sz = lengthAMode(pfx,delta);
+ d_sz = 1;
+ d64 = getSDisp8(delta + am_sz);
+ delta = dis_Grp1 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz, d64 );
+ return delta;
+
+ case 0x84: /* TEST Eb,Gb */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, False, 1, delta, "test" );
+ return delta;
+
+ case 0x85: /* TEST Ev,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, False, sz, delta, "test" );
+ return delta;
+
+ /* XCHG reg,mem automatically asserts LOCK# even without a LOCK
+ prefix. Therefore, surround it with a IRStmt_MBE(Imbe_BusLock)
+ and IRStmt_MBE(Imbe_BusUnlock) pair. But be careful; if it is
+ used with an explicit LOCK prefix, we don't want to end up with
+ two IRStmt_MBE(Imbe_BusLock)s -- one made here and one made by
+ the generic LOCK logic at the top of disInstr. */
+ case 0x86: /* XCHG Gb,Eb */
+ sz = 1;
+ /* Fall through ... */
+ case 0x87: /* XCHG Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ ty = szToITy(sz);
+ t1 = newTemp(ty); t2 = newTemp(ty);
+ if (epartIsReg(modrm)) {
+ assign(t1, getIRegE(sz, pfx, modrm));
+ assign(t2, getIRegG(sz, pfx, modrm));
+ putIRegG(sz, pfx, modrm, mkexpr(t1));
+ putIRegE(sz, pfx, modrm, mkexpr(t2));
+ delta++;
+ DIP("xchg%c %s, %s\n",
+ nameISize(sz), nameIRegG(sz, pfx, modrm),
+ nameIRegE(sz, pfx, modrm));
+ } else {
+ *expect_CAS = True;
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( t1, loadLE(ty, mkexpr(addr)) );
+ assign( t2, getIRegG(sz, pfx, modrm) );
+ casLE( mkexpr(addr),
+ mkexpr(t1), mkexpr(t2), guest_RIP_curr_instr );
+ putIRegG( sz, pfx, modrm, mkexpr(t1) );
+ delta += alen;
+ DIP("xchg%c %s, %s\n", nameISize(sz),
+ nameIRegG(sz, pfx, modrm), dis_buf);
+ }
+ return delta;
case 0x88: /* MOV Gb,Eb */
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_mov_G_E(vbi, pfx, 1, delta);
- break;
+ return delta;
case 0x89: /* MOV Gv,Ev */
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_mov_G_E(vbi, pfx, sz, delta);
- break;
+ return delta;
case 0x8A: /* MOV Eb,Gb */
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_mov_E_G(vbi, pfx, 1, delta);
- break;
-
+ return delta;
+
case 0x8B: /* MOV Ev,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_mov_E_G(vbi, pfx, sz, delta);
- break;
-
+ return delta;
+
case 0x8D: /* LEA M,Gv */
if (haveF2orF3(pfx)) goto decode_failure;
if (sz != 4 && sz != 8)
@@ -16693,424 +18590,179 @@
);
DIP("lea%c %s, %s\n", nameISize(sz), dis_buf,
nameIRegG(sz,pfx,modrm));
- break;
+ return delta;
-//.. case 0x8C: /* MOV Sw,Ew -- MOV from a SEGMENT REGISTER */
-//.. delta = dis_mov_Sw_Ew(sorb, sz, delta);
-//.. break;
-//..
-//.. case 0x8E: /* MOV Ew,Sw -- MOV to a SEGMENT REGISTER */
-//.. delta = dis_mov_Ew_Sw(sorb, delta);
-//.. break;
-
- case 0xA0: /* MOV Ob,AL */
- if (have66orF2orF3(pfx)) goto decode_failure;
- sz = 1;
- /* Fall through ... */
- case 0xA1: /* MOV Ov,eAX */
- if (sz != 8 && sz != 4 && sz != 2 && sz != 1)
- goto decode_failure;
- d64 = getDisp64(delta);
- delta += 8;
- ty = szToITy(sz);
- addr = newTemp(Ity_I64);
- assign( addr, handleAddrOverrides(vbi, pfx, mkU64(d64)) );
- putIRegRAX(sz, loadLE( ty, mkexpr(addr) ));
- DIP("mov%c %s0x%llx, %s\n", nameISize(sz),
- segRegTxt(pfx), d64,
- nameIRegRAX(sz));
- break;
-
- case 0xA2: /* MOV AL,Ob */
- if (have66orF2orF3(pfx)) goto decode_failure;
- sz = 1;
- /* Fall through ... */
- case 0xA3: /* MOV eAX,Ov */
- if (sz != 8 && sz != 4 && sz != 2 && sz != 1)
- goto decode_failure;
- d64 = getDisp64(delta);
- delta += 8;
- ty = szToITy(sz);
- addr = newTemp(Ity_I64);
- assign( addr, handleAddrOverrides(vbi, pfx, mkU64(d64)) );
- storeLE( mkexpr(addr), getIRegRAX(sz) );
- DIP("mov%c %s, %s0x%llx\n", nameISize(sz), nameIRegRAX(sz),
- segRegTxt(pfx), d64);
- break;
-
- /* XXXX be careful here with moves to AH/BH/CH/DH */
- case 0xB0: /* MOV imm,AL */
- case 0xB1: /* MOV imm,CL */
- case 0xB2: /* MOV imm,DL */
- case 0xB3: /* MOV imm,BL */
- case 0xB4: /* MOV imm,AH */
- case 0xB5: /* MOV imm,CH */
- case 0xB6: /* MOV imm,DH */
- case 0xB7: /* MOV imm,BH */
+ case 0x8F: { /* POPQ m64 / POPW m16 */
+ Int len;
+ UChar rm;
+ /* There is no encoding for 32-bit pop in 64-bit mode.
+ So sz==4 actually means sz==8. */
if (haveF2orF3(pfx)) goto decode_failure;
- d64 = getUChar(delta);
- delta += 1;
- putIRegRexB(1, pfx, opc-0xB0, mkU8(d64));
- DIP("movb $%lld,%s\n", d64, nameIRegRexB(1,pfx,opc-0xB0));
- break;
+ vassert(sz == 2 || sz == 4
+ || /* tolerate redundant REX.W, see #210481 */ sz == 8);
+ if (sz == 4) sz = 8;
+ if (sz != 8) goto decode_failure; // until we know a sz==2 test case exists
- case 0xB8: /* MOV imm,eAX */
- case 0xB9: /* MOV imm,eCX */
- case 0xBA: /* MOV imm,eDX */
- case 0xBB: /* MOV imm,eBX */
- case 0xBC: /* MOV imm,eSP */
- case 0xBD: /* MOV imm,eBP */
- case 0xBE: /* MOV imm,eSI */
- case 0xBF: /* MOV imm,eDI */
- /* This is the one-and-only place where 64-bit literals are
- allowed in the instruction stream. */
+ rm = getUChar(delta);
+
+ /* make sure this instruction is correct POP */
+ if (epartIsReg(rm) || gregLO3ofRM(rm) != 0)
+ goto decode_failure;
+ /* and has correct size */
+ vassert(sz == 8);
+
+ t1 = newTemp(Ity_I64);
+ t3 = newTemp(Ity_I64);
+ assign( t1, getIReg64(R_RSP) );
+ assign( t3, loadLE(Ity_I64, mkexpr(t1)) );
+
+ /* Increase RSP; must be done before the STORE. Intel manual
+ says: If the RSP register is used as a base register for
+ addressing a destination operand in memory, the POP
+ instruction computes the effective address of the operand
+ after it increments the RSP register. */
+ putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t1), mkU64(sz)) );
+
+ addr = disAMode ( &len, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), mkexpr(t3) );
+
+ DIP("popl %s\n", dis_buf);
+
+ delta += len;
+ return delta;
+ }
+
+ case 0x90: /* XCHG eAX,eAX */
+ /* detect and handle F3 90 (rep nop) specially */
+ if (!have66(pfx) && !haveF2(pfx) && haveF3(pfx)) {
+ DIP("rep nop (P4 pause)\n");
+ /* "observe" the hint. The Vex client needs to be careful not
+ to cause very long delays as a result, though. */
+ jmp_lit(dres, Ijk_Yield, guest_RIP_bbstart+delta);
+ vassert(dres->whatNext == Dis_StopHere);
+ return delta;
+ }
+ /* detect and handle NOPs specially */
+ if (/* F2/F3 probably change meaning completely */
+ !haveF2orF3(pfx)
+ /* If REX.B is 1, we're not exchanging rAX with itself */
+ && getRexB(pfx)==0 ) {
+ DIP("nop\n");
+ return delta;
+ }
+ /* else fall through to normal case. */
+ case 0x91: /* XCHG rAX,rCX */
+ case 0x92: /* XCHG rAX,rDX */
+ case 0x93: /* XCHG rAX,rBX */
+ case 0x94: /* XCHG rAX,rSP */
+ case 0x95: /* XCHG rAX,rBP */
+ case 0x96: /* XCHG rAX,rSI */
+ case 0x97: /* XCHG rAX,rDI */
+ /* guard against mutancy */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ codegen_xchg_rAX_Reg ( pfx, sz, opc - 0x90 );
+ return delta;
+
+ case 0x98: /* CBW */
if (haveF2orF3(pfx)) goto decode_failure;
if (sz == 8) {
- d64 = getDisp64(delta);
- delta += 8;
- putIRegRexB(8, pfx, opc-0xB8, mkU64(d64));
- DIP("movabsq $%lld,%s\n", (Long)d64,
- nameIRegRexB(8,pfx,opc-0xB8));
- } else {
- d64 = getSDisp(imin(4,sz),delta);
- delta += imin(4,sz);
- putIRegRexB(sz, pfx, opc-0xB8,
- mkU(szToITy(sz), d64 & mkSizeMask(sz)));
- DIP("mov%c $%lld,%s\n", nameISize(sz),
- (Long)d64,
- nameIRegRexB(sz,pfx,opc-0xB8));
+ putIRegRAX( 8, unop(Iop_32Sto64, getIRegRAX(4)) );
+ DIP(/*"cdqe\n"*/"cltq");
+ return delta;
}
- break;
-
- case 0xC6: /* MOV Ib,Eb */
- sz = 1;
- goto do_Mov_I_E;
- case 0xC7: /* MOV Iv,Ev */
- goto do_Mov_I_E;
-
- do_Mov_I_E:
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- if (epartIsReg(modrm)) {
- delta++; /* mod/rm byte */
- d64 = getSDisp(imin(4,sz),delta);
- delta += imin(4,sz);
- putIRegE(sz, pfx, modrm,
- mkU(szToITy(sz), d64 & mkSizeMask(sz)));
- DIP("mov%c $%lld, %s\n", nameISize(sz),
- (Long)d64,
- nameIRegE(sz,pfx,modrm));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf,
- /*xtra*/imin(4,sz) );
- delta += alen;
- d64 = getSDisp(imin(4,sz),delta);
- delta += imin(4,sz);
- storeLE(mkexpr(addr),
- mkU(szToITy(sz), d64 & mkSizeMask(sz)));
- DIP("mov%c $%lld, %s\n", nameISize(sz), (Long)d64, dis_buf);
+ if (sz == 4) {
+ putIRegRAX( 4, unop(Iop_16Sto32, getIRegRAX(2)) );
+ DIP("cwtl\n");
+ return delta;
}
- break;
-
- /* ------------------------ MOVx ------------------------ */
-
- case 0x63: /* MOVSX */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (haveREX(pfx) && 1==getRexW(pfx)) {
- vassert(sz == 8);
- /* movsx r/m32 to r64 */
- modrm = getUChar(delta);
- if (epartIsReg(modrm)) {
- delta++;
- putIRegG(8, pfx, modrm,
- unop(Iop_32Sto64,
- getIRegE(4, pfx, modrm)));
- DIP("movslq %s,%s\n",
- nameIRegE(4, pfx, modrm),
- nameIRegG(8, pfx, modrm));
- break;
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
- putIRegG(8, pfx, modrm,
- unop(Iop_32Sto64,
- loadLE(Ity_I32, mkexpr(addr))));
- DIP("movslq %s,%s\n", dis_buf,
- nameIRegG(8, pfx, modrm));
- break;
- }
- } else {
- goto decode_failure;
+ if (sz == 2) {
+ putIRegRAX( 2, unop(Iop_8Sto16, getIRegRAX(1)) );
+ DIP("cbw\n");
+ return delta;
}
+ goto decode_failure;
- /* ------------------------ opl imm, A ----------------- */
-
- case 0x04: /* ADD Ib, AL */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( 1, False, Iop_Add8, True, delta, "add" );
- break;
- case 0x05: /* ADD Iv, eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A(sz, False, Iop_Add8, True, delta, "add" );
- break;
-
- case 0x0C: /* OR Ib, AL */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( 1, False, Iop_Or8, True, delta, "or" );
- break;
- case 0x0D: /* OR Iv, eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( sz, False, Iop_Or8, True, delta, "or" );
- break;
-
- case 0x14: /* ADC Ib, AL */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( 1, True, Iop_Add8, True, delta, "adc" );
- break;
- case 0x15: /* ADC Iv, eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( sz, True, Iop_Add8, True, delta, "adc" );
- break;
-
- case 0x1C: /* SBB Ib, AL */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( 1, True, Iop_Sub8, True, delta, "sbb" );
- break;
- case 0x1D: /* SBB Iv, eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( sz, True, Iop_Sub8, True, delta, "sbb" );
- break;
-
- case 0x24: /* AND Ib, AL */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( 1, False, Iop_And8, True, delta, "and" );
- break;
- case 0x25: /* AND Iv, eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( sz, False, Iop_And8, True, delta, "and" );
- break;
-
- case 0x2C: /* SUB Ib, AL */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A(1, False, Iop_Sub8, True, delta, "sub" );
- break;
- case 0x2D: /* SUB Iv, eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( sz, False, Iop_Sub8, True, delta, "sub" );
- break;
-
- case 0x34: /* XOR Ib, AL */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( 1, False, Iop_Xor8, True, delta, "xor" );
- break;
- case 0x35: /* XOR Iv, eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( sz, False, Iop_Xor8, True, delta, "xor" );
- break;
-
- case 0x3C: /* CMP Ib, AL */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( 1, False, Iop_Sub8, False, delta, "cmp" );
- break;
- case 0x3D: /* CMP Iv, eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( sz, False, Iop_Sub8, False, delta, "cmp" );
- break;
-
- case 0xA8: /* TEST Ib, AL */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( 1, False, Iop_And8, False, delta, "test" );
- break;
- case 0xA9: /* TEST Iv, eAX */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op_imm_A( sz, False, Iop_And8, False, delta, "test" );
- break;
-
- /* ------------------------ opl Ev, Gv ----------------- */
-
- case 0x02: /* ADD Eb,Gb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Add8, True, 1, delta, "add" );
- break;
- case 0x03: /* ADD Ev,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Add8, True, sz, delta, "add" );
- break;
-
- case 0x0A: /* OR Eb,Gb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Or8, True, 1, delta, "or" );
- break;
- case 0x0B: /* OR Ev,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Or8, True, sz, delta, "or" );
- break;
-
- case 0x12: /* ADC Eb,Gb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, 1, delta, "adc" );
- break;
- case 0x13: /* ADC Ev,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" );
- break;
-
- case 0x1A: /* SBB Eb,Gb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
- break;
- case 0x1B: /* SBB Ev,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
- break;
-
- case 0x22: /* AND Eb,Gb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, True, 1, delta, "and" );
- break;
- case 0x23: /* AND Ev,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, True, sz, delta, "and" );
- break;
-
- case 0x2A: /* SUB Eb,Gb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, True, 1, delta, "sub" );
- break;
- case 0x2B: /* SUB Ev,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, True, sz, delta, "sub" );
- break;
-
- case 0x32: /* XOR Eb,Gb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Xor8, True, 1, delta, "xor" );
- break;
- case 0x33: /* XOR Ev,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Xor8, True, sz, delta, "xor" );
- break;
-
- case 0x3A: /* CMP Eb,Gb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, False, 1, delta, "cmp" );
- break;
- case 0x3B: /* CMP Ev,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_Sub8, False, sz, delta, "cmp" );
- break;
-
- case 0x84: /* TEST Eb,Gb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, False, 1, delta, "test" );
- break;
- case 0x85: /* TEST Ev,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_E_G ( vbi, pfx, False, Iop_And8, False, sz, delta, "test" );
- break;
-
- /* ------------------------ opl Gv, Ev ----------------- */
-
- case 0x00: /* ADD Gb,Eb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Add8, True, 1, delta, "add" );
- break;
- case 0x01: /* ADD Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Add8, True, sz, delta, "add" );
- break;
-
- case 0x08: /* OR Gb,Eb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Or8, True, 1, delta, "or" );
- break;
- case 0x09: /* OR Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Or8, True, sz, delta, "or" );
- break;
-
- case 0x10: /* ADC Gb,Eb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Add8, True, 1, delta, "adc" );
- break;
- case 0x11: /* ADC Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Add8, True, sz, delta, "adc" );
- break;
-
- case 0x18: /* SBB Gb,Eb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
- break;
- case 0x19: /* SBB Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
- break;
-
- case 0x20: /* AND Gb,Eb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_And8, True, 1, delta, "and" );
- break;
- case 0x21: /* AND Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_And8, True, sz, delta, "and" );
- break;
-
- case 0x28: /* SUB Gb,Eb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, True, 1, delta, "sub" );
- break;
- case 0x29: /* SUB Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, True, sz, delta, "sub" );
- break;
-
- case 0x30: /* XOR Gb,Eb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Xor8, True, 1, delta, "xor" );
- break;
- case 0x31: /* XOR Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Xor8, True, sz, delta, "xor" );
- break;
-
- case 0x38: /* CMP Gb,Eb */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, False, 1, delta, "cmp" );
- break;
- case 0x39: /* CMP Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_op2_G_E ( vbi, pfx, False, Iop_Sub8, False, sz, delta, "cmp" );
- break;
-
- /* ------------------------ POP ------------------------ */
-
- case 0x58: /* POP eAX */
- case 0x59: /* POP eCX */
- case 0x5A: /* POP eDX */
- case 0x5B: /* POP eBX */
- case 0x5D: /* POP eBP */
- case 0x5E: /* POP eSI */
- case 0x5F: /* POP eDI */
- case 0x5C: /* POP eSP */
+ case 0x99: /* CWD/CDQ/CQO */
if (haveF2orF3(pfx)) goto decode_failure;
vassert(sz == 2 || sz == 4 || sz == 8);
- if (sz == 4)
- sz = 8; /* there is no encoding for 32-bit pop in 64-bit mode */
- t1 = newTemp(szToITy(sz));
+ ty = szToITy(sz);
+ putIRegRDX( sz,
+ binop(mkSizedOp(ty,Iop_Sar8),
+ getIRegRAX(sz),
+ mkU8(sz == 2 ? 15 : (sz == 4 ? 31 : 63))) );
+ DIP(sz == 2 ? "cwd\n"
+ : (sz == 4 ? /*"cdq\n"*/ "cltd\n"
+ : "cqo\n"));
+ return delta;
+
+ case 0x9B: /* FWAIT (X87 insn) */
+ /* ignore? */
+ DIP("fwait\n");
+ return delta;
+
+ case 0x9C: /* PUSHF */ {
+ /* Note. There is no encoding for a 32-bit pushf in 64-bit
+ mode. So sz==4 actually means sz==8. */
+ /* 24 July 06: has also been seen with a redundant REX prefix,
+ so must also allow sz==8. */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ vassert(sz == 2 || sz == 4 || sz == 8);
+ if (sz == 4) sz = 8;
+ if (sz != 8) goto decode_failure; // until we know a sz==2 test case exists
+
+ t1 = newTemp(Ity_I64);
+ assign( t1, binop(Iop_Sub64,getIReg64(R_RSP),mkU64(sz)) );
+ putIReg64(R_RSP, mkexpr(t1) );
+
t2 = newTemp(Ity_I64);
- assign(t2, getIReg64(R_RSP));
- assign(t1, loadLE(szToITy(sz),mkexpr(t2)));
- putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t2), mkU64(sz)));
- putIRegRexB(sz, pfx, opc-0x58, mkexpr(t1));
- DIP("pop%c %s\n", nameISize(sz), nameIRegRexB(sz,pfx,opc-0x58));
- break;
+ assign( t2, mk_amd64g_calculate_rflags_all() );
+
+ /* Patch in the D flag. This can simply be a copy of bit 10 of
+ baseBlock[OFFB_DFLAG]. */
+ t3 = newTemp(Ity_I64);
+ assign( t3, binop(Iop_Or64,
+ mkexpr(t2),
+ binop(Iop_And64,
+ IRExpr_Get(OFFB_DFLAG,Ity_I64),
+ mkU64(1<<10)))
+ );
+
+ /* And patch in the ID flag. */
+ t4 = newTemp(Ity_I64);
+ assign( t4, binop(Iop_Or64,
+ mkexpr(t3),
+ binop(Iop_And64,
+ binop(Iop_Shl64, IRExpr_Get(OFFB_IDFLAG,Ity_I64),
+ mkU8(21)),
+ mkU64(1<<21)))
+ );
+
+ /* And patch in the AC flag too. */
+ t5 = newTemp(Ity_I64);
+ assign( t5, binop(Iop_Or64,
+ mkexpr(t4),
+ binop(Iop_And64,
+ binop(Iop_Shl64, IRExpr_Get(OFFB_ACFLAG,Ity_I64),
+ mkU8(18)),
+ mkU64(1<<18)))
+ );
+
+ /* if sz==2, the stored value needs to be narrowed. */
+ if (sz == 2)
+ storeLE( mkexpr(t1), unop(Iop_32to16,
+ unop(Iop_64to32,mkexpr(t5))) );
+ else
+ storeLE( mkexpr(t1), mkexpr(t5) );
+
+ DIP("pushf%c\n", nameISize(sz));
+ return delta;
+ }
case 0x9D: /* POPF */
/* Note. There is no encoding for a 32-bit popf in 64-bit mode.
So sz==4 actually means sz==8. */
if (haveF2orF3(pfx)) goto decode_failure;
- vassert(sz == 2 || sz == 4 || sz == 8);
+ vassert(sz == 2 || sz == 4);
if (sz == 4) sz = 8;
if (sz != 8) goto decode_failure; // until we know a sz==2 test case exists
t1 = newTemp(Ity_I64); t2 = newTemp(Ity_I64);
@@ -17172,521 +18824,506 @@
);
DIP("popf%c\n", nameISize(sz));
- break;
+ return delta;
-//.. case 0x61: /* POPA */
-//.. /* This is almost certainly wrong for sz==2. So ... */
-//.. if (sz != 4) goto decode_failure;
-//..
-//.. /* t5 is the old %ESP value. */
-//.. t5 = newTemp(Ity_I32);
-//.. assign( t5, getIReg(4, R_ESP) );
-//..
-//.. /* Reload all the registers, except %esp. */
-//.. putIReg(4,R_EAX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(28)) ));
-//.. putIReg(4,R_ECX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(24)) ));
-//.. putIReg(4,R_EDX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(20)) ));
-//.. putIReg(4,R_EBX, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32(16)) ));
-//.. /* ignore saved %ESP */
-//.. putIReg(4,R_EBP, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32( 8)) ));
-//.. putIReg(4,R_ESI, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32( 4)) ));
-//.. putIReg(4,R_EDI, loadLE(Ity_I32, binop(Iop_Add32,mkexpr(t5),mkU32( 0)) ));
-//..
-//.. /* and move %ESP back up */
-//.. putIReg( 4, R_ESP, binop(Iop_Add32, mkexpr(t5), mkU32(8*4)) );
-//..
-//.. DIP("pusha%c\n", nameISize(sz));
-//.. break;
+ case 0x9E: /* SAHF */
+ codegen_SAHF();
+ DIP("sahf\n");
+ return delta;
- case 0x8F: { /* POPQ m64 / POPW m16 */
- Int len;
- UChar rm;
- /* There is no encoding for 32-bit pop in 64-bit mode.
- So sz==4 actually means sz==8. */
- if (haveF2orF3(pfx)) goto decode_failure;
- vassert(sz == 2 || sz == 4
- || /* tolerate redundant REX.W, see #210481 */ sz == 8);
- if (sz == 4) sz = 8;
- if (sz != 8) goto decode_failure; // until we know a sz==2 test case exists
+ case 0x9F: /* LAHF */
+ codegen_LAHF();
+ DIP("lahf\n");
+ return delta;
- rm = getUChar(delta);
-
- /* make sure this instruction is correct POP */
- if (epartIsReg(rm) || gregLO3ofRM(rm) != 0)
+ case 0xA0: /* MOV Ob,AL */
+ if (have66orF2orF3(pfx)) goto decode_failure;
+ sz = 1;
+ /* Fall through ... */
+ case 0xA1: /* MOV Ov,eAX */
+ if (sz != 8 && sz != 4 && sz != 2 && sz != 1)
goto decode_failure;
- /* and has correct size */
- vassert(sz == 8);
-
- t1 = newTemp(Ity_I64);
- t3 = newTemp(Ity_I64);
- assign( t1, getIReg64(R_RSP) );
- assign( t3, loadLE(Ity_I64, mkexpr(t1)) );
-
- /* Increase RSP; must be done before the STORE. Intel manual
- says: If the RSP register is used as a base register for
- addressing a destination operand in memory, the POP
- instruction computes the effective address of the operand
- after it increments the RSP register. */
- putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t1), mkU64(sz)) );
-
- addr = disAMode ( &len, vbi, pfx, delta, dis_buf, 0 );
- storeLE( mkexpr(addr), mkexpr(t3) );
-
- DIP("popl %s\n", dis_buf);
-
- delta += len;
- break;
- }
-
-//.. //-- case 0x1F: /* POP %DS */
-//.. //-- dis_pop_segreg( cb, R_DS, sz ); break;
-//.. //-- case 0x07: /* POP %ES */
-//.. //-- dis_pop_segreg( cb, R_ES, sz ); break;
-//.. //-- case 0x17: /* POP %SS */
-//.. //-- dis_pop_segreg( cb, R_SS, sz ); break;
-
- /* ------------------------ PUSH ----------------------- */
-
- case 0x50: /* PUSH eAX */
- case 0x51: /* PUSH eCX */
- case 0x52: /* PUSH eDX */
- case 0x53: /* PUSH eBX */
- case 0x55: /* PUSH eBP */
- case 0x56: /* PUSH eSI */
- case 0x57: /* PUSH eDI */
- case 0x54: /* PUSH eSP */
- /* This is the Right Way, in that the value to be pushed is
- established before %rsp is changed, so that pushq %rsp
- correctly pushes the old value. */
- if (haveF2orF3(pfx)) goto decode_failure;
- vassert(sz == 2 || sz == 4 || sz == 8);
- if (sz == 4)
- sz = 8; /* there is no encoding for 32-bit push in 64-bit mode */
- ty = sz==2 ? Ity_I16 : Ity_I64;
- t1 = newTemp(ty);
- t2 = newTemp(Ity_I64);
- assign(t1, getIRegRexB(sz, pfx, opc-0x50));
- assign(t2, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(sz)));
- putIReg64(R_RSP, mkexpr(t2) );
- storeLE(mkexpr(t2),mkexpr(t1));
- DIP("push%c %s\n", nameISize(sz), nameIRegRexB(sz,pfx,opc-0x50));
- break;
-
- case 0x68: /* PUSH Iv */
- if (haveF2orF3(pfx)) goto decode_failure;
- /* Note, sz==4 is not possible in 64-bit mode. Hence ... */
- if (sz == 4) sz = 8;
- d64 = getSDisp(imin(4,sz),delta);
- delta += imin(4,sz);
- goto do_push_I;
- case 0x6A: /* PUSH Ib, sign-extended to sz */
- if (haveF2orF3(pfx)) goto decode_failure;
- /* Note, sz==4 is not possible in 64-bit mode. Hence ... */
- if (sz == 4) sz = 8;
- d64 = getSDisp8(delta); delta += 1;
- goto do_push_I;
- do_push_I:
+ d64 = getDisp64(delta);
+ delta += 8;
ty = szToITy(sz);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(ty);
- assign( t1, binop(Iop_Sub64,getIReg64(R_RSP),mkU64(sz)) );
- putIReg64(R_RSP, mkexpr(t1) );
- /* stop mkU16 asserting if d32 is a negative 16-bit number
- (bug #132813) */
- if (ty == Ity_I16)
- d64 &= 0xFFFF;
- storeLE( mkexpr(t1), mkU(ty,d64) );
- DIP("push%c $%lld\n", nameISize(sz), (Long)d64);
- break;
+ addr = newTemp(Ity_I64);
+ assign( addr, handleAddrOverrides(vbi, pfx, mkU64(d64)) );
+ putIRegRAX(sz, loadLE( ty, mkexpr(addr) ));
+ DIP("mov%c %s0x%llx, %s\n", nameISize(sz),
+ segRegTxt(pfx), d64,
+ nameIRegRAX(sz));
+ return delta;
- case 0x9C: /* PUSHF */ {
- /* Note. There is no encoding for a 32-bit pushf in 64-bit
- mode. So sz==4 actually means sz==8. */
- /* 24 July 06: has also been seen with a redundant REX prefix,
- so must also allow sz==8. */
- if (haveF2orF3(pfx)) goto decode_failure;
- vassert(sz == 2 || sz == 4 || sz == 8);
- if (sz == 4) sz = 8;
- if (sz != 8) goto decode_failure; // until we know a sz==2 test case exists
+ case 0xA2: /* MOV AL,Ob */
+ if (have66orF2orF3(pfx)) goto decode_failure;
+ sz = 1;
+ /* Fall through ... */
+ case 0xA3: /* MOV eAX,Ov */
+ if (sz != 8 && sz != 4 && sz != 2 && sz != 1)
+ goto decode_failure;
+ d64 = getDisp64(delta);
+ delta += 8;
+ ty = szToITy(sz);
+ addr = newTemp(Ity_I64);
+ assign( addr, handleAddrOverrides(vbi, pfx, mkU64(d64)) );
+ storeLE( mkexpr(addr), getIRegRAX(sz) );
+ DIP("mov%c %s, %s0x%llx\n", nameISize(sz), nameIRegRAX(sz),
+ segRegTxt(pfx), d64);
+ return delta;
- t1 = newTemp(Ity_I64);
- assign( t1, binop(Iop_Sub64,getIReg64(R_RSP),mkU64(sz)) );
- putIReg64(R_RSP, mkexpr(t1) );
-
- t2 = newTemp(Ity_I64);
- assign( t2, mk_amd64g_calculate_rflags_all() );
-
- /* Patch in the D flag. This can simply be a copy of bit 10 of
- baseBlock[OFFB_DFLAG]. */
- t3 = newTemp(Ity_I64);
- assign( t3, binop(Iop_Or64,
- mkexpr(t2),
- binop(Iop_And64,
- IRExpr_Get(OFFB_DFLAG,Ity_I64),
- mkU64(1<<10)))
- );
-
- /* And patch in the ID flag. */
- t4 = newTemp(Ity_I64);
- assign( t4, binop(Iop_Or64,
- mkexpr(t3),
- binop(Iop_And64,
- binop(Iop_Shl64, IRExpr_Get(OFFB_IDFLAG,Ity_I64),
- mkU8(21)),
- mkU64(1<<21)))
- );
-
- /* And patch in the AC flag too. */
- t5 = newTemp(Ity_I64);
- assign( t5, binop(Iop_Or64,
- mkexpr(t4),
- binop(Iop_And64,
- binop(Iop_Shl64, IRExpr_Get(OFFB_ACFLAG,Ity_I64),
- mkU8(18)),
- mkU64(1<<18)))
- );
-
- /* if sz==2, the stored value needs to be narrowed. */
- if (sz == 2)
- storeLE( mkexpr(t1), unop(Iop_32to16,
- unop(Iop_64to32,mkexpr(t5))) );
- else
- storeLE( mkexpr(t1), mkexpr(t5) );
-
- DIP("pushf%c\n", nameISize(sz));
- break;
- }
-
-//.. case 0x60: /* PUSHA */
-//.. /* This is almost certainly wrong for sz==2. So ... */
-//.. if (sz != 4) goto decode_failure;
-//..
-//.. /* This is the Right Way, in that the value to be pushed is
-//.. established before %esp is changed, so that pusha
-//.. correctly pushes the old %esp value. New value of %esp is
-//.. pushed at start. */
-//.. /* t0 is the %ESP value we're going to push. */
-//.. t0 = newTemp(Ity_I32);
-//.. assign( t0, getIReg(4, R_ESP) );
-//..
-//.. /* t5 will be the new %ESP value. */
-//.. t5 = newTemp(Ity_I32);
-//.. assign( t5, binop(Iop_Sub32, mkexpr(t0), mkU32(8*4)) );
-//..
-//.. /* Update guest state before prodding memory. */
-//.. putIReg(4, R_ESP, mkexpr(t5));
-//..
-//.. /* Dump all the registers. */
-//.. storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(28)), getIReg(4,R_EAX) );
-//.. storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(24)), getIReg(4,R_ECX) );
-//.. storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(20)), getIReg(4,R_EDX) );
-//.. storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(16)), getIReg(4,R_EBX) );
-//.. storeLE( binop(Iop_Add32,mkexpr(t5),mkU32(12)), mkexpr(t0) /*esp*/);
-//.. storeLE( binop(Iop_Add32,mkexpr(t5),mkU32( 8)), getIReg(4,R_EBP) );
-//.. storeLE( binop(Iop_Add32,mkexpr(t5),mkU32( 4)), getIReg(4,R_ESI) );
-//.. storeLE( binop(Iop_Add32,mkexpr(t5),mkU32( 0)), getIReg(4,R_EDI) );
-//..
-//.. DIP("pusha%c\n", nameISize(sz));
-//.. break;
-//..
-//..
-//.. //-- case 0x0E: /* PUSH %CS */
-//.. //-- dis_push_segreg( cb, R_CS, sz ); break;
-//.. //-- case 0x1E: /* PUSH %DS */
-//.. //-- dis_push_segreg( cb, R_DS, sz ); break;
-//.. //-- case 0x06: /* PUSH %ES */
-//.. //-- dis_push_segreg( cb, R_ES, sz ); break;
-//.. //-- case 0x16: /* PUSH %SS */
-//.. //-- dis_push_segreg( cb, R_SS, sz ); break;
-//..
-//.. /* ------------------------ SCAS et al ----------------- */
-//..
-//.. case 0xA4: /* MOVS, no REP prefix */
-//.. case 0xA5:
-//.. dis_string_op( dis_MOVS, ( opc == 0xA4 ? 1 : sz ), "movs", sorb );
-//.. break;
-//..
-//.. case 0xA6: /* CMPSb, no REP prefix */
-//.. //-- case 0xA7:
-//.. dis_string_op( dis_CMPS, ( opc == 0xA6 ? 1 : sz ), "cmps", sorb );
-//.. break;
-//.. //--
-//.. //--
- case 0xAC: /* LODS, no REP prefix */
- case 0xAD:
- dis_string_op( dis_LODS, ( opc == 0xAC ? 1 : sz ), "lods", pfx );
- break;
-//..
-//.. case 0xAE: /* SCAS, no REP prefix */
-//.. case 0xAF:
-//.. dis_string_op( dis_SCAS, ( opc == 0xAE ? 1 : sz ), "scas", sorb );
-//.. break;
-
-
- case 0xFC: /* CLD */
- if (haveF2orF3(pfx)) goto decode_failure;
- stmt( IRStmt_Put( OFFB_DFLAG, mkU64(1)) );
- DIP("cld\n");
- break;
-
- case 0xFD: /* STD */
- if (haveF2orF3(pfx)) goto decode_failure;
- stmt( IRStmt_Put( OFFB_DFLAG, mkU64(-1ULL)) );
- DIP("std\n");
- break;
-
- case 0xF8: /* CLC */
- case 0xF9: /* STC */
- case 0xF5: /* CMC */
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- assign( t0, mk_amd64g_calculate_rflags_all() );
- switch (opc) {
- case 0xF8:
- assign( t1, binop(Iop_And64, mkexpr(t0),
- mkU64(~AMD64G_CC_MASK_C)));
- DIP("clc\n");
- break;
- case 0xF9:
- assign( t1, binop(Iop_Or64, mkexpr(t0),
- mkU64(AMD64G_CC_MASK_C)));
- DIP("stc\n");
- break;
- case 0xF5:
- assign( t1, binop(Iop_Xor64, mkexpr(t0),
- mkU64(AMD64G_CC_MASK_C)));
- DIP("cmc\n");
- break;
- default:
- vpanic("disInstr(x64)(clc/stc/cmc)");
- }
- stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(t1) ));
- /* Set NDEP even though it isn't used. This makes redundant-PUT
- elimination of previous stores to this field work better. */
- stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
- break;
-
-//.. /* REPNE prefix insn */
-//.. case 0xF2: {
-//.. Addr32 eip_orig = guest_eip_bbstart + delta - 1;
-//.. vassert(sorb == 0);
-//.. abyte = getUChar(delta); delta++;
-//..
-//.. if (abyte == 0x66) { sz = 2; abyte = getUChar(delta); delta++; }
-//.. whatNext = Dis_StopHere;
-//..
-//.. switch (abyte) {
-//.. /* According to the Intel manual, "repne movs" should never occur, but
-//.. * in practice it has happened, so allow for it here... */
-//.. case 0xA4: sz = 1; /* REPNE MOVS<sz> */
-//.. goto decode_failure;
-//.. //-- case 0xA5:
-//.. // dis_REP_op ( CondNZ, dis_MOVS, sz, eip_orig,
-//.. // guest_eip_bbstart+delta, "repne movs" );
-//.. // break;
-//.. //--
-//.. //-- case 0xA6: sz = 1; /* REPNE CMPS<sz> */
-//.. //-- case 0xA7:
-//.. //-- dis_REP_op ( cb, CondNZ, dis_CMPS, sz, eip_orig, eip, "repne cmps" );
-//.. //-- break;
-//.. //--
-//.. case 0xAE: sz = 1; /* REPNE SCAS<sz> */
-//.. case 0xAF:
-//.. dis_REP_op ( X86CondNZ, dis_SCAS, sz, eip_orig,
-//.. guest_eip_bbstart+delta, "repne scas" );
-//.. break;
-//..
-//.. default:
-//.. goto decode_failure;
-//.. }
-//.. break;
-//.. }
-
- /* ------ AE: SCAS variants ------ */
- case 0xAE:
- case 0xAF:
- /* F2 AE/AF: repne scasb/repne scas{w,l,q} */
- if (haveF2(pfx) && !haveF3(pfx)) {
- if (opc == 0xAE)
- sz = 1;
- dis_REP_op ( AMD64CondNZ, dis_SCAS, sz,
- guest_RIP_curr_instr,
- guest_RIP_bbstart+delta, "repne scas", pfx );
- dres.whatNext = Dis_StopHere;
- break;
- }
- /* F3 AE/AF: repe scasb/repe scas{w,l,q} */
- if (!haveF2(pfx) && haveF3(pfx)) {
- if (opc == 0xAE)
- sz = 1;
- dis_REP_op ( AMD64CondZ, dis_SCAS, sz,
- guest_RIP_curr_instr,
- guest_RIP_bbstart+delta, "repe scas", pfx );
- dres.whatNext = Dis_StopHere;
- break;
- }
- /* AE/AF: scasb/scas{w,l,q} */
- if (!haveF2(pfx) && !haveF3(pfx)) {
- if (opc == 0xAE)
- sz = 1;
- dis_string_op( dis_SCAS, sz, "scas", pfx );
- break;
- }
- goto decode_failure;
-
- /* ------ A6, A7: CMPS variants ------ */
- case 0xA6:
- case 0xA7:
- /* F3 A6/A7: repe cmps/rep cmps{w,l,q} */
- if (haveF3(pfx) && !haveF2(pfx)) {
- if (opc == 0xA6)
- sz = 1;
- dis_REP_op ( AMD64CondZ, dis_CMPS, sz,
- guest_RIP_curr_instr,
- guest_RIP_bbstart+delta, "repe cmps", pfx );
- dres.whatNext = Dis_StopHere;
- break;
- }
- goto decode_failure;
-
- /* ------ AA, AB: STOS variants ------ */
- case 0xAA:
- case 0xAB:
- /* F3 AA/AB: rep stosb/rep stos{w,l,q} */
- if (haveF3(pfx) && !haveF2(pfx)) {
- if (opc == 0xAA)
- sz = 1;
- dis_REP_op ( AMD64CondAlways, dis_STOS, sz,
- guest_RIP_curr_instr,
- guest_RIP_bbstart+delta, "rep stos", pfx );
- dres.whatNext = Dis_StopHere;
- break;
- }
- /* AA/AB: stosb/stos{w,l,q} */
- if (!haveF3(pfx) && !haveF2(pfx)) {
- if (opc == 0xAA)
- sz = 1;
- dis_string_op( dis_STOS, sz, "stos", pfx );
- break;
- }
- goto decode_failure;
-
- /* ------ A4, A5: MOVS variants ------ */
case 0xA4:
case 0xA5:
/* F3 A4: rep movsb */
if (haveF3(pfx) && !haveF2(pfx)) {
if (opc == 0xA4)
sz = 1;
- dis_REP_op ( AMD64CondAlways, dis_MOVS, sz,
+ dis_REP_op ( dres, AMD64CondAlways, dis_MOVS, sz,
guest_RIP_curr_instr,
guest_RIP_bbstart+delta, "rep movs", pfx );
- dres.whatNext = Dis_StopHere;
- break;
+ dres->whatNext = Dis_StopHere;
+ return delta;
}
/* A4: movsb */
if (!haveF3(pfx) && !haveF2(pfx)) {
if (opc == 0xA4)
sz = 1;
dis_string_op( dis_MOVS, sz, "movs", pfx );
- break;
+ return delta;
}
goto decode_failure;
+ case 0xA6:
+ case 0xA7:
+ /* F3 A6/A7: repe cmps/rep cmps{w,l,q} */
+ if (haveF3(pfx) && !haveF2(pfx)) {
+ if (opc == 0xA6)
+ sz = 1;
+ dis_REP_op ( dres, AMD64CondZ, dis_CMPS, sz,
+ guest_RIP_curr_instr,
+ guest_RIP_bbstart+delta, "repe cmps", pfx );
+ dres->whatNext = Dis_StopHere;
+ return delta;
+ }
+ goto decode_failure;
- /* ------------------------ XCHG ----------------------- */
+ case 0xAA:
+ case 0xAB:
+ /* F3 AA/AB: rep stosb/rep stos{w,l,q} */
+ if (haveF3(pfx) && !haveF2(pfx)) {
+ if (opc == 0xAA)
+ sz = 1;
+ dis_REP_op ( dres, AMD64CondAlways, dis_STOS, sz,
+ guest_RIP_curr_instr,
+ guest_RIP_bbstart+delta, "rep stos", pfx );
+ vassert(dres->whatNext == Dis_StopHere);
+ return delta;
+ }
+ /* AA/AB: stosb/stos{w,l,q} */
+ if (!haveF3(pfx) && !haveF2(pfx)) {
+ if (opc == 0xAA)
+ sz = 1;
+ dis_string_op( dis_STOS, sz, "stos", pfx );
+ return delta;
+ }
+ goto decode_failure;
- /* XCHG reg,mem automatically asserts LOCK# even without a LOCK
- prefix. Therefore, surround it with a IRStmt_MBE(Imbe_BusLock)
- and IRStmt_MBE(Imbe_BusUnlock) pair. But be careful; if it is
- used with an explicit LOCK prefix, we don't want to end up with
- two IRStmt_MBE(Imbe_BusLock)s -- one made here and one made by
- the generic LOCK logic at the top of disInstr. */
- case 0x86: /* XCHG Gb,Eb */
- sz = 1;
- /* Fall through ... */
- case 0x87: /* XCHG Gv,Ev */
+ case 0xA8: /* TEST Ib, AL */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( 1, False, Iop_And8, False, delta, "test" );
+ return delta;
+ case 0xA9: /* TEST Iv, eAX */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_op_imm_A( sz, False, Iop_And8, False, delta, "test" );
+ return delta;
+
+ case 0xAC: /* LODS, no REP prefix */
+ case 0xAD:
+ dis_string_op( dis_LODS, ( opc == 0xAC ? 1 : sz ), "lods", pfx );
+ return delta;
+
+ case 0xAE:
+ case 0xAF:
+ /* F2 AE/AF: repne scasb/repne scas{w,l,q} */
+ if (haveF2(pfx) && !haveF3(pfx)) {
+ if (opc == 0xAE)
+ sz = 1;
+ dis_REP_op ( dres, AMD64CondNZ, dis_SCAS, sz,
+ guest_RIP_curr_instr,
+ guest_RIP_bbstart+delta, "repne scas", pfx );
+ vassert(dres->whatNext == Dis_StopHere);
+ return delta;
+ }
+ /* F3 AE/AF: repe scasb/repe scas{w,l,q} */
+ if (!haveF2(pfx) && haveF3(pfx)) {
+ if (opc == 0xAE)
+ sz = 1;
+ dis_REP_op ( dres, AMD64CondZ, dis_SCAS, sz,
+ guest_RIP_curr_instr,
+ guest_RIP_bbstart+delta, "repe scas", pfx );
+ vassert(dres->whatNext == Dis_StopHere);
+ return delta;
+ }
+ /* AE/AF: scasb/scas{w,l,q} */
+ if (!haveF2(pfx) && !haveF3(pfx)) {
+ if (opc == 0xAE)
+ sz = 1;
+ dis_string_op( dis_SCAS, sz, "scas", pfx );
+ return delta;
+ }
+ goto decode_failure;
+
+ /* XXXX be careful here with moves to AH/BH/CH/DH */
+ case 0xB0: /* MOV imm,AL */
+ case 0xB1: /* MOV imm,CL */
+ case 0xB2: /* MOV imm,DL */
+ case 0xB3: /* MOV imm,BL */
+ case 0xB4: /* MOV imm,AH */
+ case 0xB5: /* MOV imm,CH */
+ case 0xB6: /* MOV imm,DH */
+ case 0xB7: /* MOV imm,BH */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ d64 = getUChar(delta);
+ delta += 1;
+ putIRegRexB(1, pfx, opc-0xB0, mkU8(d64));
+ DIP("movb $%lld,%s\n", d64, nameIRegRexB(1,pfx,opc-0xB0));
+ return delta;
+
+ case 0xB8: /* MOV imm,eAX */
+ case 0xB9: /* MOV imm,eCX */
+ case 0xBA: /* MOV imm,eDX */
+ case 0xBB: /* MOV imm,eBX */
+ case 0xBC: /* MOV imm,eSP */
+ case 0xBD: /* MOV imm,eBP */
+ case 0xBE: /* MOV imm,eSI */
+ case 0xBF: /* MOV imm,eDI */
+ /* This is the one-and-only place where 64-bit literals are
+ allowed in the instruction stream. */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz == 8) {
+ d64 = getDisp64(delta);
+ delta += 8;
+ putIRegRexB(8, pfx, opc-0xB8, mkU64(d64));
+ DIP("movabsq $%lld,%s\n", (Long)d64,
+ nameIRegRexB(8,pfx,opc-0xB8));
+ } else {
+ d64 = getSDisp(imin(4,sz),delta);
+ delta += imin(4,sz);
+ putIRegRexB(sz, pfx, opc-0xB8,
+ mkU(szToITy(sz), d64 & mkSizeMask(sz)));
+ DIP("mov%c $%lld,%s\n", nameISize(sz),
+ (Long)d64,
+ nameIRegRexB(sz,pfx,opc-0xB8));
+ }
+ return delta;
+
+ case 0xC0: { /* Grp2 Ib,Eb */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
modrm = getUChar(delta);
- ty = szToITy(sz);
- t1 = newTemp(ty); t2 = newTemp(ty);
- if (epartIsReg(modrm)) {
- assign(t1, getIRegE(sz, pfx, modrm));
- assign(t2, getIRegG(sz, pfx, modrm));
- putIRegG(sz, pfx, modrm, mkexpr(t1));
- putIRegE(sz, pfx, modrm, mkexpr(t2));
- delta++;
- DIP("xchg%c %s, %s\n",
- nameISize(sz), nameIRegG(sz, pfx, modrm),
- nameIRegE(sz, pfx, modrm));
- } else {
- *expect_CAS = True;
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- assign( t1, loadLE(ty, mkexpr(addr)) );
- assign( t2, getIRegG(sz, pfx, modrm) );
- casLE( mkexpr(addr),
- mkexpr(t1), mkexpr(t2), guest_RIP_curr_instr );
- putIRegG( sz, pfx, modrm, mkexpr(t1) );
- delta += alen;
- DIP("xchg%c %s, %s\n", nameISize(sz),
- nameIRegG(sz, pfx, modrm), dis_buf);
- }
- break;
+ am_sz = lengthAMode(pfx,delta);
+ d_sz = 1;
+ d64 = getUChar(delta + am_sz);
+ sz = 1;
+ delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
+ mkU8(d64 & 0xFF), NULL, &decode_OK );
+ if (!decode_OK) goto decode_failure;
+ return delta;
+ }
- case 0x90: /* XCHG eAX,eAX */
- /* detect and handle F3 90 (rep nop) specially */
- if (!have66(pfx) && !haveF2(pfx) && haveF3(pfx)) {
- DIP("rep nop (P4 pause)\n");
- /* "observe" the hint. The Vex client needs to be careful not
- to cause very long delays as a result, though. */
- jmp_lit(Ijk_Yield, guest_RIP_bbstart+delta);
- dres.whatNext = Dis_StopHere;
- break;
- }
- /* detect and handle NOPs specially */
- if (/* F2/F3 probably change meaning completely */
- !haveF2orF3(pfx)
- /* If REX.B is 1, we're not exchanging rAX with itself */
- && getRexB(pfx)==0 ) {
- DIP("nop\n");
- break;
- }
- /* else fall through to normal case. */
- case 0x91: /* XCHG rAX,rCX */
- case 0x92: /* XCHG rAX,rDX */
- case 0x93: /* XCHG rAX,rBX */
- case 0x94: /* XCHG rAX,rSP */
- case 0x95: /* XCHG rAX,rBP */
- case 0x96: /* XCHG rAX,rSI */
- case 0x97: /* XCHG rAX,rDI */
-
- /* guard against mutancy */
+ case 0xC1: { /* Grp2 Ib,Ev */
+ Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ am_sz = lengthAMode(pfx,delta);
+ d_sz = 1;
+ d64 = getUChar(delta + am_sz);
+ delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
+ mkU8(d64 & 0xFF), NULL, &decode_OK );
+ if (!decode_OK) goto decode_failure;
+ return delta;
+ }
- codegen_xchg_rAX_Reg ( pfx, sz, opc - 0x90 );
- break;
+ case 0xC2: /* RET imm16 */
+ if (have66orF2orF3(pfx)) goto decode_failure;
+ d64 = getUDisp16(delta);
+ delta += 2;
+ dis_ret(dres, vbi, d64);
+ DIP("ret $%lld\n", d64);
+ return delta;
-//.. //-- /* ------------------------ XLAT ----------------------- */
-//.. //--
-//.. //-- case 0xD7: /* XLAT */
-//.. //-- t1 = newTemp(cb); t2 = newTemp(cb);
-//.. //-- uInstr2(cb, GET, sz, ArchReg, R_EBX, TempReg, t1); /* get eBX */
-//.. //-- handleAddrOverrides( cb, sorb, t1 ); /* make t1 DS:eBX */
-//.. //-- uInstr2(cb, GET, 1, ArchReg, R_AL, TempReg, t2); /* get AL */
-//.. //-- /* Widen %AL to 32 bits, so it's all defined when we add it. */
-//.. //-- uInstr1(cb, WIDEN, 4, TempReg, t2);
-//.. //-- uWiden(cb, 1, False);
-//.. //-- uInstr2(cb, ADD, sz, TempReg, t2, TempReg, t1); /* add AL to eBX */
-//.. //-- uInstr2(cb, LOAD, 1, TempReg, t1, TempReg, t2); /* get byte at t1 into t2 */
-//.. //-- uInstr2(cb, PUT, 1, TempReg, t2, ArchReg, R_AL); /* put byte into AL */
-//.. //--
-//.. //-- DIP("xlat%c [ebx]\n", nameISize(sz));
-//.. //-- break;
+ case 0xC3: /* RET */
+ if (have66orF2(pfx)) goto decode_failure;
+ /* F3 is acceptable on AMD. */
+ dis_ret(dres, vbi, 0);
+ DIP(haveF3(pfx) ? "rep ; ret\n" : "ret\n");
+ return delta;
- /* ------------------------ IN / OUT ----------------------- */
-
+ case 0xC6: /* MOV Ib,Eb */
+ sz = 1;
+ goto do_Mov_I_E;
+ case 0xC7: /* MOV Iv,Ev */
+ goto do_Mov_I_E;
+ do_Mov_I_E:
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta++; /* mod/rm byte */
+ d64 = getSDisp(imin(4,sz),delta);
+ delta += imin(4,sz);
+ putIRegE(sz, pfx, modrm,
+ mkU(szToITy(sz), d64 & mkSizeMask(sz)));
+ DIP("mov%c $%lld, %s\n", nameISize(sz),
+ (Long)d64,
+ nameIRegE(sz,pfx,modrm));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf,
+ /*xtra*/imin(4,sz) );
+ delta += alen;
+ d64 = getSDisp(imin(4,sz),delta);
+ delta += imin(4,sz);
+ storeLE(mkexpr(addr),
+ mkU(szToITy(sz), d64 & mkSizeMask(sz)));
+ DIP("mov%c $%lld, %s\n", nameISize(sz), (Long)d64, dis_buf);
+ }
+ return delta;
+
+ case 0xC8: /* ENTER */
+ /* Same comments re operand size as for LEAVE below apply.
+ Also, only handles the case "enter $imm16, $0"; other cases
+ for the second operand (nesting depth) are not handled. */
+ if (sz != 4)
+ goto decode_failure;
+ d64 = getUDisp16(delta);
+ delta += 2;
+ vassert(d64 >= 0 && d64 <= 0xFFFF);
+ if (getUChar(delta) != 0)
+ goto decode_failure;
+ delta++;
+ /* Intel docs seem to suggest:
+ push rbp
+ temp = rsp
+ rbp = temp
+ rsp = rsp - imm16
+ */
+ t1 = newTemp(Ity_I64);
+ assign(t1, getIReg64(R_RBP));
+ t2 = newTemp(Ity_I64);
+ assign(t2, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8)));
+ putIReg64(R_RSP, mkexpr(t2));
+ storeLE(mkexpr(t2), mkexpr(t1));
+ putIReg64(R_RBP, mkexpr(t2));
+ if (d64 > 0) {
+ putIReg64(R_RSP, binop(Iop_Sub64, mkexpr(t2), mkU64(d64)));
+ }
+ DIP("enter $%u, $0\n", (UInt)d64);
+ return delta;
+
+ case 0xC9: /* LEAVE */
+ /* In 64-bit mode this defaults to a 64-bit operand size. There
+ is no way to encode a 32-bit variant. Hence sz==4 but we do
+ it as if sz=8. */
+ if (sz != 4)
+ goto decode_failure;
+ t1 = newTemp(Ity_I64);
+ t2 = newTemp(Ity_I64);
+ assign(t1, getIReg64(R_RBP));
+ /* First PUT RSP looks redundant, but need it because RSP must
+ always be up-to-date for Memcheck to work... */
+ putIReg64(R_RSP, mkexpr(t1));
+ assign(t2, loadLE(Ity_I64,mkexpr(t1)));
+ putIReg64(R_RBP, mkexpr(t2));
+ putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t1), mkU64(8)) );
+ DIP("leave\n");
+ return delta;
+
+ case 0xCC: /* INT 3 */
+ jmp_lit(dres, Ijk_SigTRAP, guest_RIP_bbstart + delta);
+ vassert(dres->whatNext == Dis_StopHere);
+ DIP("int $0x3\n");
+ return delta;
+
+ case 0xD0: { /* Grp2 1,Eb */
+ Bool decode_OK = True;
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ am_sz = lengthAMode(pfx,delta);
+ d_sz = 0;
+ d64 = 1;
+ sz = 1;
+ delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
+ mkU8(d64), NULL, &decode_OK );
+ if (!decode_OK) goto decode_failure;
+ return delta;
+ }
+
+ case 0xD1: { /* Grp2 1,Ev */
+ Bool decode_OK = True;
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ am_sz = lengthAMode(pfx,delta);
+ d_sz = 0;
+ d64 = 1;
+ delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
+ mkU8(d64), NULL, &decode_OK );
+ if (!decode_OK) goto decode_failure;
+ return delta;
+ }
+
+ case 0xD2: { /* Grp2 CL,Eb */
+ Bool decode_OK = True;
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ am_sz = lengthAMode(pfx,delta);
+ d_sz = 0;
+ sz = 1;
+ delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
+ getIRegCL(), "%cl", &decode_OK );
+ if (!decode_OK) goto decode_failure;
+ return delta;
+ }
+
+ case 0xD3: { /* Grp2 CL,Ev */
+ Bool decode_OK = True;
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ am_sz = lengthAMode(pfx,delta);
+ d_sz = 0;
+ delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
+ getIRegCL(), "%cl", &decode_OK );
+ if (!decode_OK) goto decode_failure;
+ return delta;
+ }
+
+ case 0xD8: /* X87 instructions */
+ case 0xD9:
+ case 0xDA:
+ case 0xDB:
+ case 0xDC:
+ case 0xDD:
+ case 0xDE:
+ case 0xDF: {
+ Bool redundantREXWok = False;
+
+ if (haveF2orF3(pfx))
+ goto decode_failure;
+
+ /* kludge to tolerate redundant rex.w prefixes (should do this
+ properly one day) */
+ /* mono 1.1.18.1 produces 48 D9 FA, which is rex.w fsqrt */
+ if ( (opc == 0xD9 && getUChar(delta+0) == 0xFA)/*fsqrt*/ )
+ redundantREXWok = True;
+
+ Bool size_OK = False;
+ if ( sz == 4 )
+ size_OK = True;
+ else if ( sz == 8 )
+ size_OK = redundantREXWok;
+ else if ( sz == 2 ) {
+ int mod_rm = getUChar(delta+0);
+ int reg = gregLO3ofRM(mod_rm);
+ /* The HotSpot JVM uses these */
+ if ( (opc == 0xDD) && (reg == 0 /* FLDL */ ||
+ reg == 4 /* FNSAVE */ ||
+ reg == 6 /* FRSTOR */ ) )
+ size_OK = True;
+ }
+ /* AMD manual says 0x66 size override is ignored, except where
+ it is meaningful */
+ if (!size_OK)
+ goto decode_failure;
+
+ Bool decode_OK = False;
+ delta = dis_FPU ( &decode_OK, vbi, pfx, delta );
+ if (!decode_OK)
+ goto decode_failure;
+
+ return delta;
+ }
+
+ case 0xE0: /* LOOPNE disp8: decrement count, jump if count != 0 && ZF==0 */
+ case 0xE1: /* LOOPE disp8: decrement count, jump if count != 0 && ZF==1 */
+ case 0xE2: /* LOOP disp8: decrement count, jump if count != 0 */
+ { /* The docs say this uses rCX as a count depending on the
+ address size override, not the operand one. */
+ IRExpr* zbit = NULL;
+ IRExpr* count = NULL;
+ IRExpr* cond = NULL;
+ HChar* xtra = NULL;
+
+ if (have66orF2orF3(pfx) || 1==getRexW(pfx)) goto decode_failure;
+ /* So at this point we've rejected any variants which appear to
+ be governed by the usual operand-size modifiers. Hence only
+ the address size prefix can have an effect. It changes the
+ size from 64 (default) to 32. */
+ d64 = guest_RIP_bbstart+delta+1 + getSDisp8(delta);
+ delta++;
+ if (haveASO(pfx)) {
+ /* 64to32 of 64-bit get is merely a get-put improvement
+ trick. */
+ putIReg32(R_RCX, binop(Iop_Sub32,
+ unop(Iop_64to32, getIReg64(R_RCX)),
+ mkU32(1)));
+ } else {
+ putIReg64(R_RCX, binop(Iop_Sub64, getIReg64(R_RCX), mkU64(1)));
+ }
+
+ /* This is correct, both for 32- and 64-bit versions. If we're
+ doing a 32-bit dec and the result is zero then the default
+ zero extension rule will cause the upper 32 bits to be zero
+ too. Hence a 64-bit check against zero is OK. */
+ count = getIReg64(R_RCX);
+ cond = binop(Iop_CmpNE64, count, mkU64(0));
+ switch (opc) {
+ case 0xE2:
+ xtra = "";
+ break;
+ case 0xE1:
+ xtra = "e";
+ zbit = mk_amd64g_calculate_condition( AMD64CondZ );
+ cond = mkAnd1(cond, zbit);
+ break;
+ case 0xE0:
+ xtra = "ne";
+ zbit = mk_amd64g_calculate_condition( AMD64CondNZ );
+ cond = mkAnd1(cond, zbit);
+ break;
+ default:
+ vassert(0);
+ }
+ stmt( IRStmt_Exit(cond, Ijk_Boring, IRConst_U64(d64), OFFB_RIP) );
+
+ DIP("loop%s%s 0x%llx\n", xtra, haveASO(pfx) ? "l" : "", d64);
+ return delta;
+ }
+
+ case 0xE3:
+ /* JRCXZ or JECXZ, depending address size override. */
+ if (have66orF2orF3(pfx)) goto decode_failure;
+ d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta);
+ delta++;
+ if (haveASO(pfx)) {
+ /* 32-bit */
+ stmt( IRStmt_Exit( binop(Iop_CmpEQ64,
+ unop(Iop_32Uto64, getIReg32(R_RCX)),
+ mkU64(0)),
+ Ijk_Boring,
+ IRConst_U64(d64),
+ OFFB_RIP
+ ));
+ DIP("jecxz 0x%llx\n", d64);
+ } else {
+ /* 64-bit */
+ stmt( IRStmt_Exit( binop(Iop_CmpEQ64,
+ getIReg64(R_RCX),
+ mkU64(0)),
+ Ijk_Boring,
+ IRConst_U64(d64),
+ OFFB_RIP
+ ));
+ DIP("jrcxz 0x%llx\n", d64);
+ }
+ return delta;
+
case 0xE4: /* IN imm8, AL */
sz = 1;
t1 = newTemp(Ity_I64);
@@ -17733,7 +19370,7 @@
/* do the call, dumping the result in t2. */
stmt( IRStmt_Dirty(d) );
putIRegRAX(sz, narrowTo( ty, mkexpr(t2) ) );
- break;
+ return delta;
}
case 0xE6: /* OUT AL, imm8 */
@@ -17780,808 +19417,888 @@
mkU64(sz) )
);
stmt( IRStmt_Dirty(d) );
- break;
+ return delta;
}
- /* ------------------------ (Grp1 extensions) ---------- */
+ case 0xE8: /* CALL J4 */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ d64 = getSDisp32(delta); delta += 4;
+ d64 += (guest_RIP_bbstart+delta);
+ /* (guest_RIP_bbstart+delta) == return-to addr, d64 == call-to addr */
+ t1 = newTemp(Ity_I64);
+ assign(t1, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8)));
+ putIReg64(R_RSP, mkexpr(t1));
+ storeLE( mkexpr(t1), mkU64(guest_RIP_bbstart+delta));
+ t2 = newTemp(Ity_I64);
+ assign(t2, mkU64((Addr64)d64));
+ make_redzone_AbiHint(vbi, t1, t2/*nia*/, "call-d32");
+ if (resteerOkFn( callback_opaque, (Addr64)d64) ) {
+ /* follow into the call target. */
+ dres->whatNext = Dis_ResteerU;
+ dres->continueAt = d64;
+ } else {
+ jmp_lit(dres, Ijk_Call, d64);
+ vassert(dres->whatNext == Dis_StopHere);
+ }
+ DIP("call 0x%llx\n",d64);
+ return delta;
- case 0x80: /* Grp1 Ib,Eb */
+ case 0xE9: /* Jv (jump, 16/32 offset) */
if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- sz = 1;
- d_sz = 1;
- d64 = getSDisp8(delta + am_sz);
- delta = dis_Grp1 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz, d64 );
- break;
+ if (sz != 4)
+ goto decode_failure; /* JRS added 2004 July 11 */
+ d64 = (guest_RIP_bbstart+delta+sz) + getSDisp(sz,delta);
+ delta += sz;
+ if (resteerOkFn(callback_opaque,d64)) {
+ dres->whatNext = Dis_ResteerU;
+ dres->continueAt = d64;
+ } else {
+ jmp_lit(dres, Ijk_Boring, d64);
+ vassert(dres->whatNext == Dis_StopHere);
+ }
+ DIP("jmp 0x%llx\n", d64);
+ return delta;
- case 0x81: /* Grp1 Iv,Ev */
+ case 0xEB: /* Jb (jump, byte offset) */
if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- d_sz = imin(sz,4);
- d64 = getSDisp(d_sz, delta + am_sz);
- delta = dis_Grp1 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz, d64 );
- break;
+ if (sz != 4)
+ goto decode_failure; /* JRS added 2004 July 11 */
+ d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta);
+ delta++;
+ if (resteerOkFn(callback_opaque,d64)) {
+ dres->whatNext = Dis_ResteerU;
+ dres->continueAt = d64;
+ } else {
+ jmp_lit(dres, Ijk_Boring, d64);
+ vassert(dres->whatNext == Dis_StopHere);
+ }
+ DIP("jmp-8 0x%llx\n", d64);
+ return delta;
- case 0x83: /* Grp1 Ib,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- d_sz = 1;
- d64 = getSDisp8(delta + am_sz);
- delta = dis_Grp1 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz, d64 );
- break;
-
- /* ------------------------ (Grp2 extensions) ---------- */
-
- case 0xC0: { /* Grp2 Ib,Eb */
- Bool decode_OK = True;
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- d_sz = 1;
- d64 = getUChar(delta + am_sz);
- sz = 1;
- delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
- mkU8(d64 & 0xFF), NULL, &decode_OK );
- if (!decode_OK) goto decode_failure;
- break;
- }
- case 0xC1: { /* Grp2 Ib,Ev */
- Bool decode_OK = True;
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- d_sz = 1;
- d64 = getUChar(delta + am_sz);
- delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
- mkU8(d64 & 0xFF), NULL, &decode_OK );
- if (!decode_OK) goto decode_failure;
- break;
- }
- case 0xD0: { /* Grp2 1,Eb */
- Bool decode_OK = True;
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- d_sz = 0;
- d64 = 1;
- sz = 1;
- delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
- mkU8(d64), NULL, &decode_OK );
- if (!decode_OK) goto decode_failure;
- break;
- }
- case 0xD1: { /* Grp2 1,Ev */
- Bool decode_OK = True;
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- d_sz = 0;
- d64 = 1;
- delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
- mkU8(d64), NULL, &decode_OK );
- if (!decode_OK) goto decode_failure;
- break;
- }
- case 0xD2: { /* Grp2 CL,Eb */
- Bool decode_OK = True;
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- d_sz = 0;
- sz = 1;
- delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
- getIRegCL(), "%cl", &decode_OK );
- if (!decode_OK) goto decode_failure;
- break;
- }
- case 0xD3: { /* Grp2 CL,Ev */
- Bool decode_OK = True;
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- d_sz = 0;
- delta = dis_Grp2 ( vbi, pfx, delta, modrm, am_sz, d_sz, sz,
- getIRegCL(), "%cl", &decode_OK );
- if (!decode_OK) goto decode_failure;
- break;
- }
-
- /* ------------------------ (Grp3 extensions) ---------- */
+ case 0xF5: /* CMC */
+ case 0xF8: /* CLC */
+ case 0xF9: /* STC */
+ t1 = newTemp(Ity_I64);
+ t2 = newTemp(Ity_I64);
+ assign( t1, mk_amd64g_calculate_rflags_all() );
+ switch (opc) {
+ case 0xF5:
+ assign( t2, binop(Iop_Xor64, mkexpr(t1),
+ mkU64(AMD64G_CC_MASK_C)));
+ DIP("cmc\n");
+ break;
+ case 0xF8:
+ assign( t2, binop(Iop_And64, mkexpr(t1),
+ mkU64(~AMD64G_CC_MASK_C)));
+ DIP("clc\n");
+ break;
+ case 0xF9:
+ assign( t2, binop(Iop_Or64, mkexpr(t1),
+ mkU64(AMD64G_CC_MASK_C)));
+ DIP("stc\n");
+ break;
+ default:
+ vpanic("disInstr(x64)(cmc/clc/stc)");
+ }
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(t2) ));
+ /* Set NDEP even though it isn't used. This makes redundant-PUT
+ elimination of previous stores to this field work better. */
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+ return delta;
case 0xF6: { /* Grp3 Eb */
Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_Grp3 ( vbi, pfx, 1, delta, &decode_OK );
if (!decode_OK) goto decode_failure;
- break;
+ return delta;
}
+
case 0xF7: { /* Grp3 Ev */
Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_Grp3 ( vbi, pfx, sz, delta, &decode_OK );
if (!decode_OK) goto decode_failure;
- break;
+ return delta;
}
- /* ------------------------ (Grp4 extensions) ---------- */
+ case 0xFC: /* CLD */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ stmt( IRStmt_Put( OFFB_DFLAG, mkU64(1)) );
+ DIP("cld\n");
+ return delta;
+
+ case 0xFD: /* STD */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ stmt( IRStmt_Put( OFFB_DFLAG, mkU64(-1ULL)) );
+ DIP("std\n");
+ return delta;
case 0xFE: { /* Grp4 Eb */
Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
delta = dis_Grp4 ( vbi, pfx, delta, &decode_OK );
if (!decode_OK) goto decode_failure;
- break;
+ return delta;
}
- /* ------------------------ (Grp5 extensions) ---------- */
-
case 0xFF: { /* Grp5 Ev */
Bool decode_OK = True;
if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_Grp5 ( vbi, pfx, sz, delta, &dres, &decode_OK );
+ delta = dis_Grp5 ( vbi, pfx, sz, delta, dres, &decode_OK );
if (!decode_OK) goto decode_failure;
+ return delta;
+ }
+
+ default:
+ break;
+
+ }
+
+ decode_failure:
+ return deltaIN; /* fail */
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level post-escape decoders: dis_ESC_0F ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+static IRTemp math_BSWAP ( IRTemp t1, IRType ty )
+{
+ IRTemp t2 = newTemp(ty);
+ if (ty == Ity_I64) {
+ IRTemp m8 = newTemp(Ity_I64);
+ IRTemp s8 = newTemp(Ity_I64);
+ IRTemp m16 = newTemp(Ity_I64);
+ IRTemp s16 = newTemp(Ity_I64);
+ IRTemp m32 = newTemp(Ity_I64);
+ assign( m8, mkU64(0xFF00FF00FF00FF00ULL) );
+ assign( s8,
+ binop(Iop_Or64,
+ binop(Iop_Shr64,
+ binop(Iop_And64,mkexpr(t1),mkexpr(m8)),
+ mkU8(8)),
+ binop(Iop_And64,
+ binop(Iop_Shl64,mkexpr(t1),mkU8(8)),
+ mkexpr(m8))
+ )
+ );
+
+ assign( m16, mkU64(0xFFFF0000FFFF0000ULL) );
+ assign( s16,
+ binop(Iop_Or64,
+ binop(Iop_Shr64,
+ binop(Iop_And64,mkexpr(s8),mkexpr(m16)),
+ mkU8(16)),
+ binop(Iop_And64,
+ binop(Iop_Shl64,mkexpr(s8),mkU8(16)),
+ mkexpr(m16))
+ )
+ );
+
+ assign( m32, mkU64(0xFFFFFFFF00000000ULL) );
+ assign( t2,
+ binop(Iop_Or64,
+ binop(Iop_Shr64,
+ binop(Iop_And64,mkexpr(s16),mkexpr(m32)),
+ mkU8(32)),
+ binop(Iop_And64,
+ binop(Iop_Shl64,mkexpr(s16),mkU8(32)),
+ mkexpr(m32))
+ )
+ );
+ return t2;
+ }
+ if (ty == Ity_I32) {
+ assign( t2,
+ binop(
+ Iop_Or32,
+ binop(Iop_Shl32, mkexpr(t1), mkU8(24)),
+ binop(
+ Iop_Or32,
+ binop(Iop_And32, binop(Iop_Shl32, mkexpr(t1), mkU8(8)),
+ mkU32(0x00FF0000)),
+ binop(Iop_Or32,
+ binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(8)),
+ mkU32(0x0000FF00)),
+ binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(24)),
+ mkU32(0x000000FF) )
+ )))
+ );
+ return t2;
+ }
+ if (ty == Ity_I16) {
+ assign(t2,
+ binop(Iop_Or16,
+ binop(Iop_Shl16, mkexpr(t1), mkU8(8)),
+ binop(Iop_Shr16, mkexpr(t1), mkU8(8)) ));
+ return t2;
+ }
+ vassert(0);
+ /*NOTREACHED*/
+ return IRTemp_INVALID;
+}
+
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F (
+ /*MB_OUT*/DisResult* dres,
+ /*MB_OUT*/Bool* expect_CAS,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN
+ )
+{
+ Long d64 = 0;
+ IRTemp addr = IRTemp_INVALID;
+ IRTemp t1 = IRTemp_INVALID;
+ IRTemp t2 = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int am_sz = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
+
+ /* In the first switch, look for ordinary integer insns. */
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) { /* first switch */
+
+ case 0x01:
+ {
+ modrm = getUChar(delta);
+ /* 0F 01 /0 -- SGDT */
+ /* 0F 01 /1 -- SIDT */
+ if (!epartIsReg(modrm)
+ && (gregLO3ofRM(modrm) == 0 || gregLO3ofRM(modrm) == 1)) {
+ /* This is really revolting, but ... since each processor
+ (core) only has one IDT and one GDT, just let the guest
+ see it (pass-through semantics). I can't see any way to
+ construct a faked-up value, so don't bother to try. */
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ switch (gregLO3ofRM(modrm)) {
+ case 0: DIP("sgdt %s\n", dis_buf); break;
+ case 1: DIP("sidt %s\n", dis_buf); break;
+ default: vassert(0); /*NOTREACHED*/
+ }
+ IRDirty* d = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_SxDT",
+ &amd64g_dirtyhelper_SxDT,
+ mkIRExprVec_2( mkexpr(addr),
+ mkU64(gregLO3ofRM(modrm)) )
+ );
+ /* declare we're writing memory */
+ d->mFx = Ifx_Write;
+ d->mAddr = mkexpr(addr);
+ d->mSize = 6;
+ stmt( IRStmt_Dirty(d) );
+ return delta;
+ }
+ /* 0F 01 D0 = XGETBV */
+ if (modrm == 0xD0 && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) {
+ delta += 1;
+ DIP("xgetbv\n");
+ /* Fault (SEGV) if ECX isn't zero. Intel docs say #GP and I
+ am not sure if that translates in to SEGV or to something
+ else, in user space. */
+ t1 = newTemp(Ity_I32);
+ assign( t1, getIReg32(R_RCX) );
+ stmt( IRStmt_Exit(binop(Iop_CmpNE32, mkexpr(t1), mkU32(0)),
+ Ijk_SigSEGV,
+ IRConst_U64(guest_RIP_curr_instr),
+ OFFB_RIP
+ ));
+ putIRegRAX(4, mkU32(7));
+ putIRegRDX(4, mkU32(0));
+ return delta;
+ }
+ /* else decode failed */
break;
}
- /* ------------------------ Escapes to 2-byte opcodes -- */
+ case 0x05: /* SYSCALL */
+ guest_RIP_next_mustcheck = True;
+ guest_RIP_next_assumed = guest_RIP_bbstart + delta;
+ putIReg64( R_RCX, mkU64(guest_RIP_next_assumed) );
+ /* It's important that all guest state is up-to-date
+ at this point. So we declare an end-of-block here, which
+ forces any cached guest state to be flushed. */
+ jmp_lit(dres, Ijk_Sys_syscall, guest_RIP_next_assumed);
+ vassert(dres->whatNext == Dis_StopHere);
+ DIP("syscall\n");
+ return delta;
- case 0x0F: {
- opc = getUChar(delta); delta++;
- switch (opc) {
+ case 0x0B: /* UD2 */
+ stmt( IRStmt_Put( OFFB_RIP, mkU64(guest_RIP_curr_instr) ) );
+ jmp_lit(dres, Ijk_NoDecode, guest_RIP_curr_instr);
+ vassert(dres->whatNext == Dis_StopHere);
+ DIP("ud2\n");
+ return delta;
- /* =-=-=-=-=-=-=-=-=- Grp8 =-=-=-=-=-=-=-=-=-=-=-= */
+ case 0x0D: /* 0F 0D /0 -- prefetch mem8 */
+ /* 0F 0D /1 -- prefetchw mem8 */
+ if (have66orF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) goto decode_failure;
+ if (gregLO3ofRM(modrm) != 0 && gregLO3ofRM(modrm) != 1)
+ goto decode_failure;
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ switch (gregLO3ofRM(modrm)) {
+ case 0: DIP("prefetch %s\n", dis_buf); break;
+ case 1: DIP("prefetchw %s\n", dis_buf); break;
+ default: vassert(0); /*NOTREACHED*/
+ }
+ return delta;
- case 0xBA: { /* Grp8 Ib,Ev */
- Bool decode_OK = False;
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- am_sz = lengthAMode(pfx,delta);
- d64 = getSDisp8(delta + am_sz);
- delta = dis_Grp8_Imm ( vbi, pfx, delta, modrm, am_sz, sz, d64,
- &decode_OK );
- if (!decode_OK)
- goto decode_failure;
- break;
+ case 0x1F:
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) goto decode_failure;
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("nop%c %s\n", nameISize(sz), dis_buf);
+ return delta;
+
+ case 0x31: { /* RDTSC */
+ IRTemp val = newTemp(Ity_I64);
+ IRExpr** args = mkIRExprVec_0();
+ IRDirty* d = unsafeIRDirty_1_N (
+ val,
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_RDTSC",
+ &amd64g_dirtyhelper_RDTSC,
+ args
+ );
+ if (have66orF2orF3(pfx)) goto decode_failure;
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+ putIRegRDX(4, unop(Iop_64HIto32, mkexpr(val)));
+ putIRegRAX(4, unop(Iop_64to32, mkexpr(val)));
+ DIP("rdtsc\n");
+ return delta;
+ }
+
+ case 0x40:
+ case 0x41:
+ case 0x42: /* CMOVBb/CMOVNAEb (cmov below) */
+ case 0x43: /* CMOVNBb/CMOVAEb (cmov not below) */
+ case 0x44: /* CMOVZb/CMOVEb (cmov zero) */
+ case 0x45: /* CMOVNZb/CMOVNEb (cmov not zero) */
+ case 0x46: /* CMOVBEb/CMOVNAb (cmov below or equal) */
+ case 0x47: /* CMOVNBEb/CMOVAb (cmov not below or equal) */
+ case 0x48: /* CMOVSb (cmov negative) */
+ case 0x49: /* CMOVSb (cmov not negative) */
+ case 0x4A: /* CMOVP (cmov parity even) */
+ case 0x4B: /* CMOVNP (cmov parity odd) */
+ case 0x4C: /* CMOVLb/CMOVNGEb (cmov less) */
+ case 0x4D: /* CMOVGEb/CMOVNLb (cmov greater or equal) */
+ case 0x4E: /* CMOVLEb/CMOVNGb (cmov less or equal) */
+ case 0x4F: /* CMOVGb/CMOVNLEb (cmov greater) */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_cmov_E_G(vbi, pfx, sz, (AMD64Condcode)(opc - 0x40), delta);
+ return delta;
+
+ case 0x80:
+ case 0x81:
+ case 0x82: /* JBb/JNAEb (jump below) */
+ case 0x83: /* JNBb/JAEb (jump not below) */
+ case 0x84: /* JZb/JEb (jump zero) */
+ case 0x85: /* JNZb/JNEb (jump not zero) */
+ case 0x86: /* JBEb/JNAb (jump below or equal) */
+ case 0x87: /* JNBEb/JAb (jump not below or equal) */
+ case 0x88: /* JSb (jump negative) */
+ case 0x89: /* JSb (jump not negative) */
+ case 0x8A: /* JP (jump parity even) */
+ case 0x8B: /* JNP/JPO (jump parity odd) */
+ case 0x8C: /* JLb/JNGEb (jump less) */
+ case 0x8D: /* JGEb/JNLb (jump greater or equal) */
+ case 0x8E: /* JLEb/JNGb (jump less or equal) */
+ case 0x8F: { /* JGb/JNLEb (jump greater) */
+ Long jmpDelta;
+ HChar* comment = "";
+ if (haveF2orF3(pfx)) goto decode_failure;
+ jmpDelta = getSDisp32(delta);
+ d64 = (guest_RIP_bbstart+delta+4) + jmpDelta;
+ delta += 4;
+ if (resteerCisOk
+ && vex_control.guest_chase_cond
+ && (Addr64)d64 != (Addr64)guest_RIP_bbstart
+ && jmpDelta < 0
+ && resteerOkFn( callback_opaque, d64) ) {
+ /* Speculation: assume this backward branch is taken. So
+ we need to emit a side-exit to the insn following this
+ one, on the negation of the condition, and continue at
+ the branch target address (d64). If we wind up back at
+ the first instruction of the trace, just stop; it's
+ better to let the IR loop unroller handle that case. */
+ stmt( IRStmt_Exit(
+ mk_amd64g_calculate_condition(
+ (AMD64Condcode)(1 ^ (opc - 0x80))),
+ Ijk_Boring,
+ IRConst_U64(guest_RIP_bbstart+delta),
+ OFFB_RIP
+ ));
+ dres->whatNext = Dis_ResteerC;
+ dres->continueAt = d64;
+ comment = "(assumed taken)";
+ }
+ else
+ if (resteerCisOk
+ && vex_control.guest_chase_cond
+ && (Addr64)d64 != (Addr64)guest_RIP_bbstart
+ && jmpDelta >= 0
+ && resteerOkFn( callback_opaque, guest_RIP_bbstart+delta ) ) {
+ /* Speculation: assume this forward branch is not taken.
+ So we need to emit a side-exit to d64 (the dest) and
+ continue disassembling at the insn immediately
+ following this one. */
+ stmt( IRStmt_Exit(
+ mk_amd64g_calculate_condition((AMD64Condcode)
+ (opc - 0x80)),
+ Ijk_Boring,
+ IRConst_U64(d64),
+ OFFB_RIP
+ ));
+ dres->whatNext = Dis_ResteerC;
+ dres->continueAt = guest_RIP_bbstart+delta;
+ comment = "(assumed not taken)";
+ }
+ else {
+ /* Conservative default translation - end the block at
+ this point. */
+ jcc_01( dres, (AMD64Condcode)(opc - 0x80),
+ guest_RIP_bbstart+delta, d64 );
+ vassert(dres->whatNext == Dis_StopHere);
+ }
+ DIP("j%s-32 0x%llx %s\n", name_AMD64Condcode(opc - 0x80), d64, comment);
+ return delta;
+ }
+
+ case 0x90:
+ case 0x91:
+ case 0x92: /* set-Bb/set-NAEb (set if below) */
+ case 0x93: /* set-NBb/set-AEb (set if not below) */
+ case 0x94: /* set-Zb/set-Eb (set if zero) */
+ case 0x95: /* set-NZb/set-NEb (set if not zero) */
+ case 0x96: /* set-BEb/set-NAb (set if below or equal) */
+ case 0x97: /* set-NBEb/set-Ab (set if not below or equal) */
+ case 0x98: /* set-Sb (set if negative) */
+ case 0x99: /* set-Sb (set if not negative) */
+ case 0x9A: /* set-P (set if parity even) */
+ case 0x9B: /* set-NP (set if parity odd) */
+ case 0x9C: /* set-Lb/set-NGEb (set if less) */
+ case 0x9D: /* set-GEb/set-NLb (set if greater or equal) */
+ case 0x9E: /* set-LEb/set-NGb (set if less or equal) */
+ case 0x9F: /* set-Gb/set-NLEb (set if greater) */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ t1 = newTemp(Ity_I8);
+ assign( t1, unop(Iop_1Uto8,mk_amd64g_calculate_condition(opc-0x90)) );
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta++;
+ putIRegE(1, pfx, modrm, mkexpr(t1));
+ DIP("set%s %s\n", name_AMD64Condcode(opc-0x90),
+ nameIRegE(1,pfx,modrm));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ storeLE( mkexpr(addr), mkexpr(t1) );
+ DIP("set%s %s\n", name_AMD64Condcode(opc-0x90), dis_buf);
+ }
+ return delta;
+
+ case 0xA2: { /* CPUID */
+ /* Uses dirty helper:
+ void amd64g_dirtyhelper_CPUID ( VexGuestAMD64State* )
+ declared to mod rax, wr rbx, rcx, rdx
+ */
+ IRDirty* d = NULL;
+ HChar* fName = NULL;
+ void* fAddr = NULL;
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3
+ |VEX_HWCAPS_AMD64_CX16
+ |VEX_HWCAPS_AMD64_AVX)) {
+ fName = "amd64g_dirtyhelper_CPUID_avx_and_cx16";
+ fAddr = &amd64g_dirtyhelper_CPUID_avx_and_cx16;
+ /* This is a Core-i5-2300-like machine */
+ }
+ else if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3
+ |VEX_HWCAPS_AMD64_CX16)) {
+ fName = "amd64g_dirtyhelper_CPUID_sse42_and_cx16";
+ fAddr = &amd64g_dirtyhelper_CPUID_sse42_and_cx16;
+ /* This is a Core-i5-670-like machine */
+ }
+ else {
+ /* Give a CPUID for at least a baseline machine, SSE2
+ only, and no CX16 */
+ fName = "amd64g_dirtyhelper_CPUID_baseline";
+ fAddr = &amd64g_dirtyhelper_CPUID_baseline;
}
- /* =-=-=-=-=-=-=-=-=- BSF/BSR -=-=-=-=-=-=-=-=-=-= */
+ vassert(fName); vassert(fAddr);
+ d = unsafeIRDirty_0_N ( 0/*regparms*/,
+ fName, fAddr, mkIRExprVec_0() );
+ /* declare guest state effects */
+ d->needsBBP = True;
+ d->nFxState = 4;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
+ d->fxState[0].fx = Ifx_Modify;
+ d->fxState[0].offset = OFFB_RAX;
+ d->fxState[0].size = 8;
+ d->fxState[1].fx = Ifx_Write;
+ d->fxState[1].offset = OFFB_RBX;
+ d->fxState[1].size = 8;
+ d->fxState[2].fx = Ifx_Modify;
+ d->fxState[2].offset = OFFB_RCX;
+ d->fxState[2].size = 8;
+ d->fxState[3].fx = Ifx_Write;
+ d->fxState[3].offset = OFFB_RDX;
+ d->fxState[3].size = 8;
+ /* execute the dirty call, side-effecting guest state */
+ stmt( IRStmt_Dirty(d) );
+ /* CPUID is a serialising insn. So, just in case someone is
+ using it as a memory fence ... */
+ stmt( IRStmt_MBE(Imbe_Fence) );
+ DIP("cpuid\n");
+ return delta;
+ }
- case 0xBC: /* BSF Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_bs_E_G ( vbi, pfx, sz, delta, True );
- break;
- case 0xBD: /* BSR Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
+ case 0xA3: /* BT Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
+ delta = dis_bt_G_E ( vbi, pfx, sz, delta, BtOpNone );
+ return delta;
+
+ case 0xA4: /* SHLDv imm8,Gv,Ev */
+ modrm = getUChar(delta);
+ d64 = delta + lengthAMode(pfx, delta);
+ vex_sprintf(dis_buf, "$%d", (Int)getUChar(d64));
+ delta = dis_SHLRD_Gv_Ev (
+ vbi, pfx, delta, modrm, sz,
+ mkU8(getUChar(d64)), True, /* literal */
+ dis_buf, True /* left */ );
+ return delta;
+
+ case 0xA5: /* SHLDv %cl,Gv,Ev */
+ modrm = getUChar(delta);
+ delta = dis_SHLRD_Gv_Ev (
+ vbi, pfx, delta, modrm, sz,
+ getIRegCL(), False, /* not literal */
+ "%cl", True /* left */ );
+ return delta;
+
+ case 0xAB: /* BTS Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
+ delta = dis_bt_G_E ( vbi, pfx, sz, delta, BtOpSet );
+ return delta;
+
+ case 0xAC: /* SHRDv imm8,Gv,Ev */
+ modrm = getUChar(delta);
+ d64 = delta + lengthAMode(pfx, delta);
+ vex_sprintf(dis_buf, "$%d", (Int)getUChar(d64));
+ delta = dis_SHLRD_Gv_Ev (
+ vbi, pfx, delta, modrm, sz,
+ mkU8(getUChar(d64)), True, /* literal */
+ dis_buf, False /* right */ );
+ return delta;
+
+ case 0xAD: /* SHRDv %cl,Gv,Ev */
+ modrm = getUChar(delta);
+ delta = dis_SHLRD_Gv_Ev (
+ vbi, pfx, delta, modrm, sz,
+ getIRegCL(), False, /* not literal */
+ "%cl", False /* right */);
+ return delta;
+
+ case 0xAF: /* IMUL Ev, Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_mul_E_G ( vbi, pfx, sz, delta );
+ return delta;
+
+ case 0xB1: { /* CMPXCHG Gv,Ev (allowed in 16,32,64 bit) */
+ Bool ok = True;
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz != 2 && sz != 4 && sz != 8) goto decode_failure;
+ delta = dis_cmpxchg_G_E ( &ok, vbi, pfx, sz, delta );
+ if (!ok) goto decode_failure;
+ return delta;
+ }
+
+ case 0xB0: { /* CMPXCHG Gb,Eb */
+ Bool ok = True;
+ if (haveF2orF3(pfx)) goto decode_failure;
+ delta = dis_cmpxchg_G_E ( &ok, vbi, pfx, 1, delta );
+ if (!ok) goto decode_failure;
+ return delta;
+ }
+
+ case 0xB3: /* BTR Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
+ delta = dis_bt_G_E ( vbi, pfx, sz, delta, BtOpReset );
+ return delta;
+
+ case 0xB6: /* MOVZXb Eb,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz != 2 && sz != 4 && sz != 8)
+ goto decode_failure;
+ delta = dis_movx_E_G ( vbi, pfx, delta, 1, sz, False );
+ return delta;
+
+ case 0xB7: /* MOVZXw Ew,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz != 4 && sz != 8)
+ goto decode_failure;
+ delta = dis_movx_E_G ( vbi, pfx, delta, 2, sz, False );
+ return delta;
+
+ case 0xBA: { /* Grp8 Ib,Ev */
+ Bool decode_OK = False;
+ if (haveF2orF3(pfx)) goto decode_failure;
+ modrm = getUChar(delta);
+ am_sz = lengthAMode(pfx,delta);
+ d64 = getSDisp8(delta + am_sz);
+ delta = dis_Grp8_Imm ( vbi, pfx, delta, modrm, am_sz, sz, d64,
+ &decode_OK );
+ if (!decode_OK)
+ goto decode_failure;
+ return delta;
+ }
+
+ case 0xBB: /* BTC Gv,Ev */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
+ delta = dis_bt_G_E ( vbi, pfx, sz, delta, BtOpComp );
+ return delta;
+
+ case 0xBC: /* BSF Gv,Ev */
+ if (haveF2(pfx)) goto decode_failure;
+ delta = dis_bs_E_G ( vbi, pfx, sz, delta, True );
+ return delta;
+
+ case 0xBD: /* BSR Gv,Ev */
+ if (!haveF2orF3(pfx)
+ || (haveF3noF2(pfx)
+ && 0 == (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT))) {
+ /* no-F2 no-F3 0F BD = BSR
+ or F3 0F BD = REP; BSR on older CPUs. */
delta = dis_bs_E_G ( vbi, pfx, sz, delta, False );
- break;
-
- /* =-=-=-=-=-=-=-=-=- BSWAP -=-=-=-=-=-=-=-=-=-=-= */
-
- case 0xC8: /* BSWAP %eax */
- case 0xC9:
- case 0xCA:
- case 0xCB:
- case 0xCC:
- case 0xCD:
- case 0xCE:
- case 0xCF: /* BSWAP %edi */
- if (haveF2orF3(pfx)) goto decode_failure;
- /* According to the AMD64 docs, this insn can have size 4 or
- 8. */
- if (sz == 4) {
- t1 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I32);
- assign( t1, getIRegRexB(4, pfx, opc-0xC8) );
- assign( t2,
- binop(Iop_Or32,
- binop(Iop_Shl32, mkexpr(t1), mkU8(24)),
- binop(Iop_Or32,
- binop(Iop_And32, binop(Iop_Shl32, mkexpr(t1), mkU8(8)),
- mkU32(0x00FF0000)),
- binop(Iop_Or32,
- binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(8)),
- mkU32(0x0000FF00)),
- binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(24)),
- mkU32(0x000000FF) )
- )))
- );
- putIRegRexB(4, pfx, opc-0xC8, mkexpr(t2));
- DIP("bswapl %s\n", nameIRegRexB(4, pfx, opc-0xC8));
- break;
- }
- else if (sz == 8) {
- IRTemp m8 = newTemp(Ity_I64);
- IRTemp s8 = newTemp(Ity_I64);
- IRTemp m16 = newTemp(Ity_I64);
- IRTemp s16 = newTemp(Ity_I64);
- IRTemp m32 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- t2 = newTemp(Ity_I64);
- assign( t1, getIRegRexB(8, pfx, opc-0xC8) );
-
- assign( m8, mkU64(0xFF00FF00FF00FF00ULL) );
- assign( s8,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- binop(Iop_And64,mkexpr(t1),mkexpr(m8)),
- mkU8(8)),
- binop(Iop_And64,
- binop(Iop_Shl64,mkexpr(t1),mkU8(8)),
- mkexpr(m8))
- )
- );
-
- assign( m16, mkU64(0xFFFF0000FFFF0000ULL) );
- assign( s16,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- binop(Iop_And64,mkexpr(s8),mkexpr(m16)),
- mkU8(16)),
- binop(Iop_And64,
- binop(Iop_Shl64,mkexpr(s8),mkU8(16)),
- mkexpr(m16))
- )
- );
-
- assign( m32, mkU64(0xFFFFFFFF00000000ULL) );
- assign( t2,
- binop(Iop_Or64,
- binop(Iop_Shr64,
- binop(Iop_And64,mkexpr(s16),mkexpr(m32)),
- mkU8(32)),
- binop(Iop_And64,
- binop(Iop_Shl64,mkexpr(s16),mkU8(32)),
- mkexpr(m32))
- )
- );
-
- putIRegRexB(8, pfx, opc-0xC8, mkexpr(t2));
- DIP("bswapq %s\n", nameIRegRexB(8, pfx, opc-0xC8));
- break;
- } else {
- goto decode_failure;
- }
-
- /* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */
-
- /* All of these are possible at sizes 2, 4 and 8, but until a
- size 2 test case shows up, only handle sizes 4 and 8. */
-
- case 0xA3: /* BT Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
- delta = dis_bt_G_E ( vbi, pfx, sz, delta, BtOpNone );
- break;
- case 0xB3: /* BTR Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
- delta = dis_bt_G_E ( vbi, pfx, sz, delta, BtOpReset );
- break;
- case 0xAB: /* BTS Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
- delta = dis_bt_G_E ( vbi, pfx, sz, delta, BtOpSet );
- break;
- case 0xBB: /* BTC Gv,Ev */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 8 && sz != 4 && sz != 2) goto decode_failure;
- delta = dis_bt_G_E ( vbi, pfx, sz, delta, BtOpComp );
- break;
-
- /* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */
-
- case 0x40:
- case 0x41:
- case 0x42: /* CMOVBb/CMOVNAEb (cmov below) */
- case 0x43: /* CMOVNBb/CMOVAEb (cmov not below) */
- case 0x44: /* CMOVZb/CMOVEb (cmov zero) */
- case 0x45: /* CMOVNZb/CMOVNEb (cmov not zero) */
- case 0x46: /* CMOVBEb/CMOVNAb (cmov below or equal) */
- case 0x47: /* CMOVNBEb/CMOVAb (cmov not below or equal) */
- case 0x48: /* CMOVSb (cmov negative) */
- case 0x49: /* CMOVSb (cmov not negative) */
- case 0x4A: /* CMOVP (cmov parity even) */
- case 0x4B: /* CMOVNP (cmov parity odd) */
- case 0x4C: /* CMOVLb/CMOVNGEb (cmov less) */
- case 0x4D: /* CMOVGEb/CMOVNLb (cmov greater or equal) */
- case 0x4E: /* CMOVLEb/CMOVNGb (cmov less or equal) */
- case 0x4F: /* CMOVGb/CMOVNLEb (cmov greater) */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_cmov_E_G(vbi, pfx, sz, (AMD64Condcode)(opc - 0x40), delta);
- break;
-
- /* =-=-=-=-=-=-=-=-=- CMPXCHG -=-=-=-=-=-=-=-=-=-= */
-
- case 0xB0: { /* CMPXCHG Gb,Eb */
- Bool ok = True;
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_cmpxchg_G_E ( &ok, vbi, pfx, 1, delta );
- if (!ok) goto decode_failure;
- break;
+ return delta;
}
- case 0xB1: { /* CMPXCHG Gv,Ev (allowed in 16,32,64 bit) */
- Bool ok = True;
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 2 && sz != 4 && sz != 8) goto decode_failure;
- delta = dis_cmpxchg_G_E ( &ok, vbi, pfx, sz, delta );
- if (!ok) goto decode_failure;
- break;
+ /* Fall through, since F3 0F BD is LZCNT, and needs to
+ be handled by dis_ESC_0F__SSE4. */
+ break;
+
+ case 0xBE: /* MOVSXb Eb,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz != 2 && sz != 4 && sz != 8)
+ goto decode_failure;
+ delta = dis_movx_E_G ( vbi, pfx, delta, 1, sz, True );
+ return delta;
+
+ case 0xBF: /* MOVSXw Ew,Gv */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ if (sz != 4 && sz != 8)
+ goto decode_failure;
+ delta = dis_movx_E_G ( vbi, pfx, delta, 2, sz, True );
+ return delta;
+
+ case 0xC1: { /* XADD Gv,Ev */
+ Bool decode_OK = False;
+ delta = dis_xadd_G_E ( &decode_OK, vbi, pfx, sz, delta );
+ if (!decode_OK)
+ goto decode_failure;
+ return delta;
+ }
+
+ case 0xC7: { /* CMPXCHG8B Ev, CMPXCHG16B Ev */
+ IRType elemTy = sz==4 ? Ity_I32 : Ity_I64;
+ IRTemp expdHi = newTemp(elemTy);
+ IRTemp expdLo = newTemp(elemTy);
+ IRTemp dataHi = newTemp(elemTy);
+ IRTemp dataLo = newTemp(elemTy);
+ IRTemp oldHi = newTemp(elemTy);
+ IRTemp oldLo = newTemp(elemTy);
+ IRTemp flags_old = newTemp(Ity_I64);
+ IRTemp flags_new = newTemp(Ity_I64);
+ IRTemp success = newTemp(Ity_I1);
+ IROp opOR = sz==4 ? Iop_Or32 : Iop_Or64;
+ IROp opXOR = sz==4 ? Iop_Xor32 : Iop_Xor64;
+ IROp opCasCmpEQ = sz==4 ? Iop_CasCmpEQ32 : Iop_CasCmpEQ64;
+ IRExpr* zero = sz==4 ? mkU32(0) : mkU64(0);
+ IRTemp expdHi64 = newTemp(Ity_I64);
+ IRTemp expdLo64 = newTemp(Ity_I64);
+
+ /* Translate this using a DCAS, even if there is no LOCK
+ prefix. Life is too short to bother with generating two
+ different translations for the with/without-LOCK-prefix
+ cases. */
+ *expect_CAS = True;
+
+ /* Decode, and generate address. */
+ if (have66orF2orF3(pfx)) goto decode_failure;
+ if (sz != 4 && sz != 8) goto decode_failure;
+ if (sz == 8 && !(archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16))
+ goto decode_failure;
+ modrm = getUChar(delta);
+ if (epartIsReg(modrm)) goto decode_failure;
+ if (gregLO3ofRM(modrm) != 1) goto decode_failure;
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+
+ /* cmpxchg16b requires an alignment check. */
+ if (sz == 8)
+ gen_SEGV_if_not_16_aligned( addr );
+
+ /* Get the expected and new values. */
+ assign( expdHi64, getIReg64(R_RDX) );
+ assign( expdLo64, getIReg64(R_RAX) );
+
+ /* These are the correctly-sized expected and new values.
+ However, we also get expdHi64/expdLo64 above as 64-bits
+ regardless, because we will need them later in the 32-bit
+ case (paradoxically). */
+ assign( expdHi, sz==4 ? unop(Iop_64to32, mkexpr(expdHi64))
+ : mkexpr(expdHi64) );
+ assign( expdLo, sz==4 ? unop(Iop_64to32, mkexpr(expdLo64))
+ : mkexpr(expdLo64) );
+ assign( dataHi, sz==4 ? getIReg32(R_RCX) : getIReg64(R_RCX) );
+ assign( dataLo, sz==4 ? getIReg32(R_RBX) : getIReg64(R_RBX) );
+
+ /* Do the DCAS */
+ stmt( IRStmt_CAS(
+ mkIRCAS( oldHi, oldLo,
+ Iend_LE, mkexpr(addr),
+ mkexpr(expdHi), mkexpr(expdLo),
+ mkexpr(dataHi), mkexpr(dataLo)
+ )));
+
+ /* success when oldHi:oldLo == expdHi:expdLo */
+ assign( success,
+ binop(opCasCmpEQ,
+ binop(opOR,
+ binop(opXOR, mkexpr(oldHi), mkexpr(expdHi)),
+ binop(opXOR, mkexpr(oldLo), mkexpr(expdLo))
+ ),
+ zero
+ ));
+
+ /* If the DCAS is successful, that is to say oldHi:oldLo ==
+ expdHi:expdLo, then put expdHi:expdLo back in RDX:RAX,
+ which is where they came from originally. Both the actual
+ contents of these two regs, and any shadow values, are
+ unchanged. If the DCAS fails then we're putting into
+ RDX:RAX the value seen in memory. */
+ /* Now of course there's a complication in the 32-bit case
+ (bah!): if the DCAS succeeds, we need to leave RDX:RAX
+ unchanged; but if we use the same scheme as in the 64-bit
+ case, we get hit by the standard rule that a write to the
+ bottom 32 bits of an integer register zeros the upper 32
+ bits. And so the upper halves of RDX and RAX mysteriously
+ become zero. So we have to stuff back in the original
+ 64-bit values which we previously stashed in
+ expdHi64:expdLo64, even if we're doing a cmpxchg8b. */
+ /* It's just _so_ much fun ... */
+ putIRegRDX( 8,
+ IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(success)),
+ sz == 4 ? unop(Iop_32Uto64, mkexpr(oldHi))
+ : mkexpr(oldHi),
+ mkexpr(expdHi64)
+ ));
+ putIRegRAX( 8,
+ IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(success)),
+ sz == 4 ? unop(Iop_32Uto64, mkexpr(oldLo))
+ : mkexpr(oldLo),
+ mkexpr(expdLo64)
+ ));
+
+ /* Copy the success bit into the Z flag and leave the others
+ unchanged */
+ assign( flags_old, widenUto64(mk_amd64g_calculate_rflags_all()));
+ assign(
+ flags_new,
+ binop(Iop_Or64,
+ binop(Iop_And64, mkexpr(flags_old),
+ mkU64(~AMD64G_CC_MASK_Z)),
+ binop(Iop_Shl64,
+ binop(Iop_And64,
+ unop(Iop_1Uto64, mkexpr(success)), mkU64(1)),
+ mkU8(AMD64G_CC_SHIFT_Z)) ));
+
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(flags_new) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ /* Set NDEP even though it isn't used. This makes
+ redundant-PUT elimination of previous stores to this field
+ work better. */
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+
+ /* Sheesh. Aren't you glad it was me and not you that had to
+ write and validate all this grunge? */
+
+ DIP("cmpxchg8b %s\n", dis_buf);
+ return delta;
+ }
+
+ case 0xC8: /* BSWAP %eax */
+ case 0xC9:
+ case 0xCA:
+ case 0xCB:
+ case 0xCC:
+ case 0xCD:
+ case 0xCE:
+ case 0xCF: /* BSWAP %edi */
+ if (haveF2orF3(pfx)) goto decode_failure;
+ /* According to the AMD64 docs, this insn can have size 4 or
+ 8. */
+ if (sz == 4) {
+ t1 = newTemp(Ity_I32);
+ assign( t1, getIRegRexB(4, pfx, opc-0xC8) );
+ t2 = math_BSWAP( t1, Ity_I32 );
+ putIRegRexB(4, pfx, opc-0xC8, mkexpr(t2));
+ DIP("bswapl %s\n", nameIRegRexB(4, pfx, opc-0xC8));
+ return delta;
}
-
- case 0xC7: { /* CMPXCHG8B Ev, CMPXCHG16B Ev */
- IRType elemTy = sz==4 ? Ity_I32 : Ity_I64;
- IRTemp expdHi = newTemp(elemTy);
- IRTemp expdLo = newTemp(elemTy);
- IRTemp dataHi = newTemp(elemTy);
- IRTemp dataLo = newTemp(elemTy);
- IRTemp oldHi = newTemp(elemTy);
- IRTemp oldLo = newTemp(elemTy);
- IRTemp flags_old = newTemp(Ity_I64);
- IRTemp flags_new = newTemp(Ity_I64);
- IRTemp success = newTemp(Ity_I1);
- IROp opOR = sz==4 ? Iop_Or32 : Iop_Or64;
- IROp opXOR = sz==4 ? Iop_Xor32 : Iop_Xor64;
- IROp opCasCmpEQ = sz==4 ? Iop_CasCmpEQ32 : Iop_CasCmpEQ64;
- IRExpr* zero = sz==4 ? mkU32(0) : mkU64(0);
- IRTemp expdHi64 = newTemp(Ity_I64);
- IRTemp expdLo64 = newTemp(Ity_I64);
-
- /* Translate this using a DCAS, even if there is no LOCK
- prefix. Life is too short to bother with generating two
- different translations for the with/without-LOCK-prefix
- cases. */
- *expect_CAS = True;
-
- /* Decode, and generate address. */
- if (have66orF2orF3(pfx)) goto decode_failure;
- if (sz != 4 && sz != 8) goto decode_failure;
- if (sz == 8 && !(archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16))
- goto decode_failure;
- modrm = getUChar(delta);
- if (epartIsReg(modrm)) goto decode_failure;
- if (gregLO3ofRM(modrm) != 1) goto decode_failure;
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
-
- /* cmpxchg16b requires an alignment check. */
- if (sz == 8)
- gen_SEGV_if_not_16_aligned( addr );
-
- /* Get the expected and new values. */
- assign( expdHi64, getIReg64(R_RDX) );
- assign( expdLo64, getIReg64(R_RAX) );
-
- /* These are the correctly-sized expected and new values.
- However, we also get expdHi64/expdLo64 above as 64-bits
- regardless, because we will need them later in the 32-bit
- case (paradoxically). */
- assign( expdHi, sz==4 ? unop(Iop_64to32, mkexpr(expdHi64))
- : mkexpr(expdHi64) );
- assign( expdLo, sz==4 ? unop(Iop_64to32, mkexpr(expdLo64))
- : mkexpr(expdLo64) );
- assign( dataHi, sz==4 ? getIReg32(R_RCX) : getIReg64(R_RCX) );
- assign( dataLo, sz==4 ? getIReg32(R_RBX) : getIReg64(R_RBX) );
-
- /* Do the DCAS */
- stmt( IRStmt_CAS(
- mkIRCAS( oldHi, oldLo,
- Iend_LE, mkexpr(addr),
- mkexpr(expdHi), mkexpr(expdLo),
- mkexpr(dataHi), mkexpr(dataLo)
- )));
-
- /* success when oldHi:oldLo == expdHi:expdLo */
- assign( success,
- binop(opCasCmpEQ,
- binop(opOR,
- binop(opXOR, mkexpr(oldHi), mkexpr(expdHi)),
- binop(opXOR, mkexpr(oldLo), mkexpr(expdLo))
- ),
- zero
- ));
-
- /* If the DCAS is successful, that is to say oldHi:oldLo ==
- expdHi:expdLo, then put expdHi:expdLo back in RDX:RAX,
- which is where they came from originally. Both the actual
- contents of these two regs, and any shadow values, are
- unchanged. If the DCAS fails then we're putting into
- RDX:RAX the value seen in memory. */
- /* Now of course there's a complication in the 32-bit case
- (bah!): if the DCAS succeeds, we need to leave RDX:RAX
- unchanged; but if we use the same scheme as in the 64-bit
- case, we get hit by the standard rule that a write to the
- bottom 32 bits of an integer register zeros the upper 32
- bits. And so the upper halves of RDX and RAX mysteriously
- become zero. So we have to stuff back in the original
- 64-bit values which we previously stashed in
- expdHi64:expdLo64, even if we're doing a cmpxchg8b. */
- /* It's just _so_ much fun ... */
- putIRegRDX( 8,
- IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(success)),
- sz == 4 ? unop(Iop_32Uto64, mkexpr(oldHi))
- : mkexpr(oldHi),
- mkexpr(expdHi64)
- ));
- putIRegRAX( 8,
- IRExpr_Mux0X( unop(Iop_1Uto8, mkexpr(success)),
- sz == 4 ? unop(Iop_32Uto64, mkexpr(oldLo))
- : mkexpr(oldLo),
- mkexpr(expdLo64)
- ));
-
- /* Copy the success bit into the Z flag and leave the others
- unchanged */
- assign( flags_old, widenUto64(mk_amd64g_calculate_rflags_all()));
- assign(
- flags_new,
- binop(Iop_Or64,
- binop(Iop_And64, mkexpr(flags_old),
- mkU64(~AMD64G_CC_MASK_Z)),
- binop(Iop_Shl64,
- binop(Iop_And64,
- unop(Iop_1Uto64, mkexpr(success)), mkU64(1)),
- mkU8(AMD64G_CC_SHIFT_Z)) ));
-
- stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
- stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(flags_new) ));
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- /* Set NDEP even though it isn't used. This makes
- redundant-PUT elimination of previous stores to this field
- work better. */
- stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
-
- /* Sheesh. Aren't you glad it was me and not you that had to
- write and validate all this grunge? */
-
- DIP("cmpxchg8b %s\n", dis_buf);
- break;
-
+ if (sz == 8) {
+ t1 = newTemp(Ity_I64);
+ t2 = newTemp(Ity_I64);
+ assign( t1, getIRegRexB(8, pfx, opc-0xC8) );
+ t2 = math_BSWAP( t1, Ity_I64 );
+ putIRegRexB(8, pfx, opc-0xC8, mkexpr(t2));
+ DIP("bswapq %s\n", nameIRegRexB(8, pfx, opc-0xC8));
+ return delta;
}
+ goto decode_failure;
- /* =-=-=-=-=-=-=-=-=- CPUID -=-=-=-=-=-=-=-=-=-=-= */
+ default:
+ break;
- case 0xA2: { /* CPUID */
- /* Uses dirty helper:
- void amd64g_dirtyhelper_CPUID ( VexGuestAMD64State* )
- declared to mod rax, wr rbx, rcx, rdx
- */
- IRDirty* d = NULL;
- HChar* fName = NULL;
- void* fAddr = NULL;
- if (haveF2orF3(pfx)) goto decode_failure;
- if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3
- |VEX_HWCAPS_AMD64_CX16)) {
- fName = "amd64g_dirtyhelper_CPUID_sse3_and_cx16";
- fAddr = &amd64g_dirtyhelper_CPUID_sse3_and_cx16;
- /* This is a Core-2-like machine */
- //fName = "amd64g_dirtyhelper_CPUID_sse42_and_cx16";
- //fAddr = &amd64g_dirtyhelper_CPUID_sse42_and_cx16;
- /* This is a Core-i5-like machine */
- }
- else {
- /* Give a CPUID for at least a baseline machine, SSE2
- only, and no CX16 */
- fName = "amd64g_dirtyhelper_CPUID_baseline";
- fAddr = &amd64g_dirtyhelper_CPUID_baseline;
- }
+ } /* first switch */
- vassert(fName); vassert(fAddr);
- d = unsafeIRDirty_0_N ( 0/*regparms*/,
- fName, fAddr, mkIRExprVec_0() );
- /* declare guest state effects */
- d->needsBBP = True;
- d->nFxState = 4;
- d->fxState[0].fx = Ifx_Modify;
- d->fxState[0].offset = OFFB_RAX;
- d->fxState[0].size = 8;
- d->fxState[1].fx = Ifx_Write;
- d->fxState[1].offset = OFFB_RBX;
- d->fxState[1].size = 8;
- d->fxState[2].fx = Ifx_Modify;
- d->fxState[2].offset = OFFB_RCX;
- d->fxState[2].size = 8;
- d->fxState[3].fx = Ifx_Write;
- d->fxState[3].offset = OFFB_RDX;
- d->fxState[3].size = 8;
- /* execute the dirty call, side-effecting guest state */
- stmt( IRStmt_Dirty(d) );
- /* CPUID is a serialising insn. So, just in case someone is
- using it as a memory fence ... */
- stmt( IRStmt_MBE(Imbe_Fence) );
- DIP("cpuid\n");
- break;
- }
- /* =-=-=-=-=-=-=-=-=- MOVZX, MOVSX =-=-=-=-=-=-=-= */
+ /* =-=-=-=-=-=-=-=-= MMXery =-=-=-=-=-=-=-=-= */
+ /* In the second switch, pick off MMX insns. */
- case 0xB6: /* MOVZXb Eb,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 2 && sz != 4 && sz != 8)
- goto decode_failure;
- delta = dis_movx_E_G ( vbi, pfx, delta, 1, sz, False );
- break;
- case 0xB7: /* MOVZXw Ew,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 4 && sz != 8)
- goto decode_failure;
- delta = dis_movx_E_G ( vbi, pfx, delta, 2, sz, False );
- break;
+ if (!have66orF2orF3(pfx)) {
+ /* So there's no SIMD prefix. */
- case 0xBE: /* MOVSXb Eb,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 2 && sz != 4 && sz != 8)
- goto decode_failure;
- delta = dis_movx_E_G ( vbi, pfx, delta, 1, sz, True );
- break;
- case 0xBF: /* MOVSXw Ew,Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- if (sz != 4 && sz != 8)
- goto decode_failure;
- delta = dis_movx_E_G ( vbi, pfx, delta, 2, sz, True );
- break;
+ vassert(sz == 4 || sz == 8);
-//.. //-- /* =-=-=-=-=-=-=-=-=-=-= MOVNTI -=-=-=-=-=-=-=-=-= */
-//.. //--
-//.. //-- case 0xC3: /* MOVNTI Gv,Ev */
-//.. //-- vg_assert(sz == 4);
-//.. //-- modrm = getUChar(eip);
-//.. //-- vg_assert(!epartIsReg(modrm));
-//.. //-- t1 = newTemp(cb);
-//.. //-- uInstr2(cb, GET, 4, ArchReg, gregOfRM(modrm), TempReg, t1);
-//.. //-- pair = disAMode ( cb, sorb, eip, dis_buf );
-//.. //-- t2 = LOW24(pair);
-//.. //-- eip += HI8(pair);
-//.. //-- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2);
-//.. //-- DIP("movnti %s,%s\n", nameIReg(4,gregOfRM(modrm)), dis_buf);
-//.. //-- break;
-
- /* =-=-=-=-=-=-=-=-=- MUL/IMUL =-=-=-=-=-=-=-=-=-= */
-
- case 0xAF: /* IMUL Ev, Gv */
- if (haveF2orF3(pfx)) goto decode_failure;
- delta = dis_mul_E_G ( vbi, pfx, sz, delta );
- break;
-
- /* =-=-=-=-=-=-=-=-=- NOPs =-=-=-=-=-=-=-=-=-=-=-= */
-
- case 0x1F:
- if (haveF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- if (epartIsReg(modrm)) goto decode_failure;
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
- DIP("nop%c %s\n", nameISize(sz), dis_buf);
- break;
-
- /* =-=-=-=-=-=-=-=-=- Jcond d32 -=-=-=-=-=-=-=-=-= */
- case 0x80:
- case 0x81:
- case 0x82: /* JBb/JNAEb (jump below) */
- case 0x83: /* JNBb/JAEb (jump not below) */
- case 0x84: /* JZb/JEb (jump zero) */
- case 0x85: /* JNZb/JNEb (jump not zero) */
- case 0x86: /* JBEb/JNAb (jump below or equal) */
- case 0x87: /* JNBEb/JAb (jump not below or equal) */
- case 0x88: /* JSb (jump negative) */
- case 0x89: /* JSb (jump not negative) */
- case 0x8A: /* JP (jump parity even) */
- case 0x8B: /* JNP/JPO (jump parity odd) */
- case 0x8C: /* JLb/JNGEb (jump less) */
- case 0x8D: /* JGEb/JNLb (jump greater or equal) */
- case 0x8E: /* JLEb/JNGb (jump less or equal) */
- case 0x8F: /* JGb/JNLEb (jump greater) */
- { Long jmpDelta;
- HChar* comment = "";
- if (haveF2orF3(pfx)) goto decode_failure;
- jmpDelta = getSDisp32(delta);
- d64 = (guest_RIP_bbstart+delta+4) + jmpDelta;
- delta += 4;
- if (resteerCisOk
- && vex_control.guest_chase_cond
- && (Addr64)d64 != (Addr64)guest_RIP_bbstart
- && jmpDelta < 0
- && resteerOkFn( callback_opaque, d64) ) {
- /* Speculation: assume this backward branch is taken. So
- we need to emit a side-exit to the insn following this
- one, on the negation of the condition, and continue at
- the branch target address (d64). If we wind up back at
- the first instruction of the trace, just stop; it's
- better to let the IR loop unroller handle that case. */
- stmt( IRStmt_Exit(
- mk_amd64g_calculate_condition(
- (AMD64Condcode)(1 ^ (opc - 0x80))),
- Ijk_Boring,
- IRConst_U64(guest_RIP_bbstart+delta) ) );
- dres.whatNext = Dis_ResteerC;
- dres.continueAt = d64;
- comment = "(assumed taken)";
- }
- else
- if (resteerCisOk
- && vex_control.guest_chase_cond
- && (Addr64)d64 != (Addr64)guest_RIP_bbstart
- && jmpDelta >= 0
- && resteerOkFn( callback_opaque, guest_RIP_bbstart+delta ) ) {
- /* Speculation: assume this forward branch is not taken.
- So we need to emit a side-exit to d64 (the dest) and
- continue disassembling at the insn immediately
- following this one. */
- stmt( IRStmt_Exit(
- mk_amd64g_calculate_condition((AMD64Condcode)
- (opc - 0x80)),
- Ijk_Boring,
- IRConst_U64(d64) ) );
- dres.whatNext = Dis_ResteerC;
- dres.continueAt = guest_RIP_bbstart+delta;
- comment = "(assumed not taken)";
- }
- else {
- /* Conservative default translation - end the block at
- this point. */
- jcc_01( (AMD64Condcode)(opc - 0x80),
- guest_RIP_bbstart+delta,
- d64 );
- dres.whatNext = Dis_StopHere;
- }
- DIP("j%s-32 0x%llx %s\n", name_AMD64Condcode(opc - 0x80), d64, comment);
- break;
- }
-
- /* =-=-=-=-=-=-=-=-=- PREFETCH =-=-=-=-=-=-=-=-=-= */
- case 0x0D: /* 0F 0D /0 -- prefetch mem8 */
- /* 0F 0D /1 -- prefetchw mem8 */
- if (have66orF2orF3(pfx)) goto decode_failure;
- modrm = getUChar(delta);
- if (epartIsReg(modrm)) goto decode_failure;
- if (gregLO3ofRM(modrm) != 0 && gregLO3ofRM(modrm) != 1)
- goto decode_failure;
-
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
-
- switch (gregLO3ofRM(modrm)) {
- case 0: DIP("prefetch %s\n", dis_buf); break;
- case 1: DIP("prefetchw %s\n", dis_buf); break;
- default: vassert(0); /*NOTREACHED*/
- }
- break;
-
- /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */
- case 0x31: { /* RDTSC */
- IRTemp val = newTemp(Ity_I64);
- IRExpr** args = mkIRExprVec_0();
- IRDirty* d = unsafeIRDirty_1_N (
- val,
- 0/*regparms*/,
- "amd64g_dirtyhelper_RDTSC",
- &amd64g_dirtyhelper_RDTSC,
- args
- );
- if (have66orF2orF3(pfx)) goto decode_failure;
- /* execute the dirty call, dumping the result in val. */
- stmt( IRStmt_Dirty(d) );
- putIRegRDX(4, unop(Iop_64HIto32, mkexpr(val)));
- putIRegRAX(4, unop(Iop_64to32, mkexpr(val)));
- DIP("rdtsc\n");
- break;
- }
-
-//.. /* =-=-=-=-=-=-=-=-=- PUSH/POP Sreg =-=-=-=-=-=-=-=-=-= */
-//..
-//.. case 0xA1: /* POP %FS */
-//.. dis_pop_segreg( R_FS, sz ); break;
-//.. case 0xA9: /* POP %GS */
-//.. dis_pop_segreg( R_GS, sz ); break;
-//..
-//.. case 0xA0: /* PUSH %FS */
-//.. dis_push_segreg( R_FS, sz ); break;
-//.. case 0xA8: /* PUSH %GS */
-//.. dis_push_segreg( R_GS, sz ); break;
-
- /* =-=-=-=-=-=-=-=-=- SETcc Eb =-=-=-=-=-=-=-=-=-= */
- case 0x90:
- case 0x91:
- case 0x92: /* set-Bb/set-NAEb (set if below) */
- case 0x93: /* set-NBb/set-AEb (set if not below) */
- case 0x94: /* set-Zb/set-Eb (set if zero) */
- case 0x95: /* set-NZb/set-NEb (set if not zero) */
- case 0x96: /* set-BEb/set-NAb (set if below or equal) */
- case 0x97: /* set-NBEb/set-Ab (set if not below or equal) */
- case 0x98: /* set-Sb (set if negative) */
- case 0x99: /* set-Sb (set if not negative) */
- case 0x9A: /* set-P (set if parity even) */
- case 0x9B: /* set-NP (set if parity odd) */
- case 0x9C: /* set-Lb/set-NGEb (set if less) */
- case 0x9D: /* set-GEb/set-NLb (set if greater or equal) */
- case 0x9E: /* set-LEb/set-NGb (set if less or equal) */
- case 0x9F: /* set-Gb/set-NLEb (set if greater) */
- if (haveF2orF3(pfx)) goto decode_failure;
- t1 = newTemp(Ity_I8);
- assign( t1, unop(Iop_1Uto8,mk_amd64g_calculate_condition(opc-0x90)) );
- modrm = getUChar(delta);
- if (epartIsReg(modrm)) {
- delta++;
- putIRegE(1, pfx, modrm, mkexpr(t1));
- DIP("set%s %s\n", name_AMD64Condcode(opc-0x90),
- nameIRegE(1,pfx,modrm));
- } else {
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
- storeLE( mkexpr(addr), mkexpr(t1) );
- DIP("set%s %s\n", name_AMD64Condcode(opc-0x90), dis_buf);
- }
- break;
-
- /* =-=-=-=-=-=-=-=-=- SHLD/SHRD -=-=-=-=-=-=-=-=-= */
-
- case 0xA4: /* SHLDv imm8,Gv,Ev */
- modrm = getUChar(delta);
- d64 = delta + lengthAMode(pfx, delta);
- vex_sprintf(dis_buf, "$%d", (Int)getUChar(d64));
- delta = dis_SHLRD_Gv_Ev (
- vbi, pfx, delta, modrm, sz,
- mkU8(getUChar(d64)), True, /* literal */
- dis_buf, True /* left */ );
- break;
- case 0xA5: /* SHLDv %cl,Gv,Ev */
- modrm = getUChar(delta);
- delta = dis_SHLRD_Gv_Ev (
- vbi, pfx, delta, modrm, sz,
- getIRegCL(), False, /* not literal */
- "%cl", True /* left */ );
- break;
-
- case 0xAC: /* SHRDv imm8,Gv,Ev */
- modrm = getUChar(delta);
- d64 = delta + lengthAMode(pfx, delta);
- vex_sprintf(dis_buf, "$%d", (Int)getUChar(d64));
- delta = dis_SHLRD_Gv_Ev (
- vbi, pfx, delta, modrm, sz,
- mkU8(getUChar(d64)), True, /* literal */
- dis_buf, False /* right */ );
- break;
- case 0xAD: /* SHRDv %cl,Gv,Ev */
- modrm = getUChar(delta);
- delta = dis_SHLRD_Gv_Ev (
- vbi, pfx, delta, modrm, sz,
- getIRegCL(), False, /* not literal */
- "%cl", False /* right */);
- break;
-
- /* =-=-=-=-=-=-=-=-=- SYSCALL -=-=-=-=-=-=-=-=-=-= */
- case 0x05: /* SYSCALL */
- guest_RIP_next_mustcheck = True;
- guest_RIP_next_assumed = guest_RIP_bbstart + delta;
- putIReg64( R_RCX, mkU64(guest_RIP_next_assumed) );
- /* It's important that all guest state is up-to-date
- at this point. So we declare an end-of-block here, which
- forces any cached guest state to be flushed. */
- jmp_lit(Ijk_Sys_syscall, guest_RIP_next_assumed);
- dres.whatNext = Dis_StopHere;
- DIP("syscall\n");
- break;
-
- /* =-=-=-=-=-=-=-=-=- XADD -=-=-=-=-=-=-=-=-=-= */
-
- case 0xC0: { /* XADD Gb,Eb */
- Bool decode_OK = False;
- delta = dis_xadd_G_E ( &decode_OK, vbi, pfx, 1, delta );
- if (!decode_OK)
- goto decode_failure;
- break;
- }
- case 0xC1: { /* XADD Gv,Ev */
- Bool decode_OK = False;
- delta = dis_xadd_G_E ( &decode_OK, vbi, pfx, sz, delta );
- if (!decode_OK)
- goto decode_failure;
- break;
- }
-
- /* =-=-=-=-=-=-=-=-=- MMXery =-=-=-=-=-=-=-=-=-=-= */
+ switch (opc) { /* second switch */
case 0x71:
case 0x72:
@@ -18651,69 +20368,6619 @@
case 0xD3:
case 0xE1: /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */
- case 0xE2:
- {
- Long delta0 = delta-1;
+ case 0xE2: {
Bool decode_OK = False;
-
- /* If sz==2 this is SSE, and we assume sse idec has
- already spotted those cases by now. */
- if (sz != 4 && sz != 8)
- goto decode_failure;
- if (have66orF2orF3(pfx))
- goto decode_failure;
-
- delta = dis_MMX ( &decode_OK, vbi, pfx, sz, delta-1 );
- if (!decode_OK) {
- delta = delta0;
- goto decode_failure;
- }
- break;
+ delta = dis_MMX ( &decode_OK, vbi, pfx, sz, deltaIN );
+ if (decode_OK)
+ return delta;
+ goto decode_failure;
}
- case 0x0E: /* FEMMS */
- case 0x77: /* EMMS */
- if (sz != 4)
- goto decode_failure;
- do_EMMS_preamble();
- DIP("{f}emms\n");
+ default:
break;
+ } /* second switch */
- /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */
- case 0x01: /* 0F 01 /0 -- SGDT */
- /* 0F 01 /1 -- SIDT */
- {
- /* This is really revolting, but ... since each processor
- (core) only has one IDT and one GDT, just let the guest
- see it (pass-through semantics). I can't see any way to
- construct a faked-up value, so don't bother to try. */
+ }
+
+ /* A couple of MMX corner cases */
+ if (opc == 0x0E/* FEMMS */ || opc == 0x77/* EMMS */) {
+ if (sz != 4)
+ goto decode_failure;
+ do_EMMS_preamble();
+ DIP("{f}emms\n");
+ return delta;
+ }
+
+ /* =-=-=-=-=-=-=-=-= SSE2ery =-=-=-=-=-=-=-=-= */
+ /* Perhaps it's an SSE or SSE2 instruction. We can try this
+ without checking the guest hwcaps because SSE2 is a baseline
+ facility in 64 bit mode. */
+ {
+ Bool decode_OK = False;
+ delta = dis_ESC_0F__SSE2 ( &decode_OK, vbi, pfx, sz, deltaIN, dres );
+ if (decode_OK)
+ return delta;
+ }
+
+ /* =-=-=-=-=-=-=-=-= SSE3ery =-=-=-=-=-=-=-=-= */
+ /* Perhaps it's a SSE3 instruction. FIXME: check guest hwcaps
+ first. */
+ {
+ Bool decode_OK = False;
+ delta = dis_ESC_0F__SSE3 ( &decode_OK, vbi, pfx, sz, deltaIN );
+ if (decode_OK)
+ return delta;
+ }
+
+ /* =-=-=-=-=-=-=-=-= SSE4ery =-=-=-=-=-=-=-=-= */
+ /* Perhaps it's a SSE4 instruction. FIXME: check guest hwcaps
+ first. */
+ {
+ Bool decode_OK = False;
+ delta = dis_ESC_0F__SSE4 ( &decode_OK,
+ archinfo, vbi, pfx, sz, deltaIN );
+ if (decode_OK)
+ return delta;
+ }
+
+ decode_failure:
+ return deltaIN; /* fail */
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level post-escape decoders: dis_ESC_0F38 ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F38 (
+ /*MB_OUT*/DisResult* dres,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN
+ )
+{
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) {
+
+ case 0xF0: /* 0F 38 F0 = MOVBE m16/32/64(E), r16/32/64(G) */
+ case 0xF1: { /* 0F 38 F1 = MOVBE r16/32/64(G), m16/32/64(E) */
+ if (!haveF2orF3(pfx) && !haveVEX(pfx)
+ && (sz == 2 || sz == 4 || sz == 8)) {
+ IRTemp addr = IRTemp_INVALID;
+ UChar modrm = 0;
+ Int alen = 0;
+ HChar dis_buf[50];
modrm = getUChar(delta);
+ if (epartIsReg(modrm)) break;
addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
delta += alen;
- if (epartIsReg(modrm)) goto decode_failure;
- if (gregLO3ofRM(modrm) != 0 && gregLO3ofRM(modrm) != 1)
- goto decode_failure;
- switch (gregLO3ofRM(modrm)) {
- case 0: DIP("sgdt %s\n", dis_buf); break;
- case 1: DIP("sidt %s\n", dis_buf); break;
- default: vassert(0); /*NOTREACHED*/
+ IRType ty = szToITy(sz);
+ IRTemp src = newTemp(ty);
+ if (opc == 0xF0) { /* LOAD */
+ assign(src, loadLE(ty, mkexpr(addr)));
+ IRTemp dst = math_BSWAP(src, ty);
+ putIRegG(sz, pfx, modrm, mkexpr(dst));
+ DIP("movbe %s,%s\n", dis_buf, nameIRegG(sz, pfx, modrm));
+ } else { /* STORE */
+ assign(src, getIRegG(sz, pfx, modrm));
+ IRTemp dst = math_BSWAP(src, ty);
+ storeLE(mkexpr(addr), mkexpr(dst));
+ DIP("movbe %s,%s\n", nameIRegG(sz, pfx, modrm), dis_buf);
+ }
+ return delta;
+ }
+ /* else fall through; maybe one of the decoders below knows what
+ it is. */
+ break;
+ }
+
+ default:
+ break;
+
+ }
+
+ /* =-=-=-=-=-=-=-=-= SSSE3ery =-=-=-=-=-=-=-=-= */
+ /* Perhaps it's an SSSE3 instruction. FIXME: consult guest hwcaps
+ rather than proceeding indiscriminately. */
+ {
+ Bool decode_OK = False;
+ delta = dis_ESC_0F38__SupSSE3 ( &decode_OK, vbi, pfx, sz, deltaIN );
+ if (decode_OK)
+ return delta;
+ }
+
+ /* =-=-=-=-=-=-=-=-= SSE4ery =-=-=-=-=-=-=-=-= */
+ /* Perhaps it's an SSE4 instruction. FIXME: consult guest hwcaps
+ rather than proceeding indiscriminately. */
+ {
+ Bool decode_OK = False;
+ delta = dis_ESC_0F38__SSE4 ( &decode_OK, vbi, pfx, sz, deltaIN );
+ if (decode_OK)
+ return delta;
+ }
+
+ /*decode_failure:*/
+ return deltaIN; /* fail */
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level post-escape decoders: dis_ESC_0F3A ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F3A (
+ /*MB_OUT*/DisResult* dres,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN
+ )
+{
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ switch (opc) {
+
+ default:
+ break;
+
+ }
+
+ /* =-=-=-=-=-=-=-=-= SSSE3ery =-=-=-=-=-=-=-=-= */
+ /* Perhaps it's an SSSE3 instruction. FIXME: consult guest hwcaps
+ rather than proceeding indiscriminately. */
+ {
+ Bool decode_OK = False;
+ delta = dis_ESC_0F3A__SupSSE3 ( &decode_OK, vbi, pfx, sz, deltaIN );
+ if (decode_OK)
+ return delta;
+ }
+
+ /* =-=-=-=-=-=-=-=-= SSE4ery =-=-=-=-=-=-=-=-= */
+ /* Perhaps it's an SSE4 instruction. FIXME: consult guest hwcaps
+ rather than proceeding indiscriminately. */
+ {
+ Bool decode_OK = False;
+ delta = dis_ESC_0F3A__SSE4 ( &decode_OK, vbi, pfx, sz, deltaIN );
+ if (decode_OK)
+ return delta;
+ }
+
+ return deltaIN; /* fail */
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level post-escape decoders: dis_ESC_0F__VEX ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+/* FIXME: common up with the _256_ version below? */
+static
+Long dis_VEX_NDS_128_AnySimdPfx_0F_WIG (
+ /*OUT*/Bool* uses_vvvv, VexAbiInfo* vbi,
+ Prefix pfx, Long delta, HChar* name,
+ /* The actual operation. Use either 'op' or 'opfn',
+ but not both. */
+ IROp op, IRTemp(*opFn)(IRTemp,IRTemp),
+ Bool invertLeftArg,
+ Bool swapArgs
+ )
+{
+ UChar modrm = getUChar(delta);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ UInt rSL = getVexNvvvv(pfx);
+ IRTemp tSL = newTemp(Ity_V128);
+ IRTemp tSR = newTemp(Ity_V128);
+ IRTemp addr = IRTemp_INVALID;
+ HChar dis_buf[50];
+ Int alen = 0;
+ vassert(0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*WIG?*/);
+
+ assign(tSL, invertLeftArg ? unop(Iop_NotV128, getXMMReg(rSL))
+ : getXMMReg(rSL));
+
+ if (epartIsReg(modrm)) {
+ UInt rSR = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ assign(tSR, getXMMReg(rSR));
+ DIP("%s %s,%s,%s\n",
+ name, nameXMMReg(rSR), nameXMMReg(rSL), nameXMMReg(rD));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ assign(tSR, loadLE(Ity_V128, mkexpr(addr)));
+ DIP("%s %s,%s,%s\n",
+ name, dis_buf, nameXMMReg(rSL), nameXMMReg(rD));
+ }
+
+ IRTemp res = IRTemp_INVALID;
+ if (op != Iop_INVALID) {
+ vassert(opFn == NULL);
+ res = newTemp(Ity_V128);
+ assign(res, swapArgs ? binop(op, mkexpr(tSR), mkexpr(tSL))
+ : binop(op, mkexpr(tSL), mkexpr(tSR)));
+ } else {
+ vassert(opFn != NULL);
+ res = swapArgs ? opFn(tSR, tSL) : opFn(tSL, tSR);
+ }
+
+ putYMMRegLoAndZU(rD, mkexpr(res));
+
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+/* Handle a VEX_NDS_128_66_0F_WIG (3-addr) insn, with a simple IROp
+ for the operation, no inversion of the left arg, and no swapping of
+ args. */
+static
+Long dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple (
+ /*OUT*/Bool* uses_vvvv, VexAbiInfo* vbi,
+ Prefix pfx, Long delta, HChar* name,
+ IROp op
+ )
+{
+ return dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, name, op, NULL, False, False);
+}
+
+
+/* Handle a VEX_NDS_128_66_0F_WIG (3-addr) insn, using the given IR
+ generator to compute the result, no inversion of the left
+ arg, and no swapping of args. */
+static
+Long dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex (
+ /*OUT*/Bool* uses_vvvv, VexAbiInfo* vbi,
+ Prefix pfx, Long delta, HChar* name,
+ IRTemp(*opFn)(IRTemp,IRTemp)
+ )
+{
+ return dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, name,
+ Iop_INVALID, opFn, False, False );
+}
+
+
+/* Vector by scalar shift of V by the amount specified at the bottom
+ of E. */
+static ULong dis_AVX128_shiftV_byE ( VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ HChar dis_buf[50];
+ Int alen, size;
+ IRTemp addr;
+ Bool shl, shr, sar;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);;
+ IRTemp g0 = newTemp(Ity_V128);
+ IRTemp g1 = newTemp(Ity_V128);
+ IRTemp amt = newTemp(Ity_I64);
+ IRTemp amt8 = newTemp(Ity_I8);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( amt, getXMMRegLane64(rE, 0) );
+ DIP("%s %s,%s,%s\n", opname, nameXMMReg(rE),
+ nameXMMReg(rV), nameXMMReg(rG) );
+ delta++;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( amt, loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("%s %s,%s,%s\n", opname, dis_buf, nameXMMReg(rV), nameXMMReg(rG) );
+ delta += alen;
+ }
+ assign( g0, getXMMReg(rV) );
+ assign( amt8, unop(Iop_64to8, mkexpr(amt)) );
+
+ shl = shr = sar = False;
+ size = 0;
+ switch (op) {
+ case Iop_ShlN16x8: shl = True; size = 32; break;
+ case Iop_ShlN32x4: shl = True; size = 32; break;
+ case Iop_ShlN64x2: shl = True; size = 64; break;
+ case Iop_SarN16x8: sar = True; size = 16; break;
+ case Iop_SarN32x4: sar = True; size = 32; break;
+ case Iop_ShrN16x8: shr = True; size = 16; break;
+ case Iop_ShrN32x4: shr = True; size = 32; break;
+ case Iop_ShrN64x2: shr = True; size = 64; break;
+ default: vassert(0);
+ }
+
+ if (shl || shr) {
+ assign(
+ g1,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpLT64U, mkexpr(amt), mkU64(size))),
+ mkV128(0x0000),
+ binop(op, mkexpr(g0), mkexpr(amt8))
+ )
+ );
+ } else
+ if (sar) {
+ assign(
+ g1,
+ IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpLT64U, mkexpr(amt), mkU64(size))),
+ binop(op, mkexpr(g0), mkU8(size-1)),
+ binop(op, mkexpr(g0), mkexpr(amt8))
+ )
+ );
+ } else {
+ vassert(0);
+ }
+
+ putYMMRegLoAndZU( rG, mkexpr(g1) );
+ return delta;
+}
+
+
+/* Vector by scalar shift of E into V, by an immediate byte. Modified
+ version of dis_SSE_shiftE_imm. */
+static
+Long dis_AVX128_shiftE_to_V_imm( Prefix pfx,
+ Long delta, HChar* opname, IROp op )
+{
+ Bool shl, shr, sar;
+ UChar rm = getUChar(delta);
+ IRTemp e0 = newTemp(Ity_V128);
+ IRTemp e1 = newTemp(Ity_V128);
+ UInt rD = getVexNvvvv(pfx);
+ UChar amt, size;
+ vassert(epartIsReg(rm));
+ vassert(gregLO3ofRM(rm) == 2
+ || gregLO3ofRM(rm) == 4 || gregLO3ofRM(rm) == 6);
+ amt = getUChar(delta+1);
+ delta += 2;
+ DIP("%s $%d,%s,%s\n", opname,
+ (Int)amt,
+ nameXMMReg(eregOfRexRM(pfx,rm)),
+ nameXMMReg(rD));
+ assign( e0, getXMMReg(eregOfRexRM(pfx,rm)) );
+
+ shl = shr = sar = False;
+ size = 0;
+ switch (op) {
+ case Iop_ShlN16x8: shl = True; size = 16; break;
+ case Iop_ShlN32x4: shl = True; size = 32; break;
+ case Iop_ShlN64x2: shl = True; size = 64; break;
+ case Iop_SarN16x8: sar = True; size = 16; break;
+ case Iop_SarN32x4: sar = True; size = 32; break;
+ case Iop_ShrN16x8: shr = True; size = 16; break;
+ case Iop_ShrN32x4: shr = True; size = 32; break;
+ case Iop_ShrN64x2: shr = True; size = 64; break;
+ default: vassert(0);
+ }
+
+ if (shl || shr) {
+ assign( e1, amt >= size
+ ? mkV128(0x0000)
+ : binop(op, mkexpr(e0), mkU8(amt))
+ );
+ } else
+ if (sar) {
+ assign( e1, amt >= size
+ ? binop(op, mkexpr(e0), mkU8(size-1))
+ : binop(op, mkexpr(e0), mkU8(amt))
+ );
+ } else {
+ vassert(0);
+ }
+
+ putYMMRegLoAndZU( rD, mkexpr(e1) );
+ return delta;
+}
+
+
+/* Lower 64-bit lane only AVX128 binary operation:
+ G[63:0] = V[63:0] `op` E[63:0]
+ G[127:64] = V[127:64]
+ G[255:128] = 0.
+ The specified op must be of the 64F0x2 kind, so that it
+ copies the upper half of the left operand to the result.
+*/
+static Long dis_AVX128_E_V_to_G_lo64 ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ HChar dis_buf[50];
+ Int alen;
+ IRTemp addr;
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,rm);
+ UInt rV = getVexNvvvv(pfx);
+ IRExpr* vpart = getXMMReg(rV);
+ if (epartIsReg(rm)) {
+ UInt rE = eregOfRexRM(pfx,rm);
+ putXMMReg( rG, binop(op, vpart, getXMMReg(rE)) );
+ DIP("%s %s,%s,%s\n", opname,
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ delta = delta+1;
+ } else {
+ /* We can only do a 64-bit memory read, so the upper half of the
+ E operand needs to be made simply of zeroes. */
+ IRTemp epart = newTemp(Ity_V128);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( epart, unop( Iop_64UtoV128,
+ loadLE(Ity_I64, mkexpr(addr))) );
+ putXMMReg( rG, binop(op, vpart, mkexpr(epart)) );
+ DIP("%s %s,%s,%s\n", opname,
+ dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ delta = delta+alen;
+ }
+ putYMMRegLane128( rG, 1, mkV128(0) );
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+/* Lower 64-bit lane only AVX128 unary operation:
+ G[63:0] = op(E[63:0])
+ G[127:64] = V[127:64]
+ G[255:128] = 0
+ The specified op must be of the 64F0x2 kind, so that it
+ copies the upper half of the operand to the result.
+*/
+static Long dis_AVX128_E_V_to_G_lo64_unary ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ HChar dis_buf[50];
+ Int alen;
+ IRTemp addr;
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,rm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp e64 = newTemp(Ity_I64);
+
+ /* Fetch E[63:0] */
+ if (epartIsReg(rm)) {
+ UInt rE = eregOfRexRM(pfx,rm);
+ assign(e64, getXMMRegLane64(rE, 0));
+ DIP("%s %s,%s,%s\n", opname,
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(e64, loadLE(Ity_I64, mkexpr(addr)));
+ DIP("%s %s,%s,%s\n", opname,
+ dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ delta += alen;
+ }
+
+ /* Create a value 'arg' as V[127:64]++E[63:0] */
+ IRTemp arg = newTemp(Ity_V128);
+ assign(arg,
+ binop(Iop_SetV128lo64,
+ getXMMReg(rV), mkexpr(e64)));
+ /* and apply op to it */
+ putYMMRegLoAndZU( rG, unop(op, mkexpr(arg)) );
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+/* Lower 32-bit lane only AVX128 unary operation:
+ G[31:0] = op(E[31:0])
+ G[127:32] = V[127:32]
+ G[255:128] = 0
+ The specified op must be of the 32F0x4 kind, so that it
+ copies the upper 3/4 of the operand to the result.
+*/
+static Long dis_AVX128_E_V_to_G_lo32_unary ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ HChar dis_buf[50];
+ Int alen;
+ IRTemp addr;
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,rm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp e32 = newTemp(Ity_I32);
+
+ /* Fetch E[31:0] */
+ if (epartIsReg(rm)) {
+ UInt rE = eregOfRexRM(pfx,rm);
+ assign(e32, getXMMRegLane32(rE, 0));
+ DIP("%s %s,%s,%s\n", opname,
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(e32, loadLE(Ity_I32, mkexpr(addr)));
+ DIP("%s %s,%s,%s\n", opname,
+ dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ delta += alen;
+ }
+
+ /* Create a value 'arg' as V[127:32]++E[31:0] */
+ IRTemp arg = newTemp(Ity_V128);
+ assign(arg,
+ binop(Iop_SetV128lo32,
+ getXMMReg(rV), mkexpr(e32)));
+ /* and apply op to it */
+ putYMMRegLoAndZU( rG, unop(op, mkexpr(arg)) );
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+/* Lower 32-bit lane only AVX128 binary operation:
+ G[31:0] = V[31:0] `op` E[31:0]
+ G[127:32] = V[127:32]
+ G[255:128] = 0.
+ The specified op must be of the 32F0x4 kind, so that it
+ copies the upper 3/4 of the left operand to the result.
+*/
+static Long dis_AVX128_E_V_to_G_lo32 ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ HChar dis_buf[50];
+ Int alen;
+ IRTemp addr;
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,rm);
+ UInt rV = getVexNvvvv(pfx);
+ IRExpr* vpart = getXMMReg(rV);
+ if (epartIsReg(rm)) {
+ UInt rE = eregOfRexRM(pfx,rm);
+ putXMMReg( rG, binop(op, vpart, getXMMReg(rE)) );
+ DIP("%s %s,%s,%s\n", opname,
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ delta = delta+1;
+ } else {
+ /* We can only do a 32-bit memory read, so the upper 3/4 of the
+ E operand needs to be made simply of zeroes. */
+ IRTemp epart = newTemp(Ity_V128);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( epart, unop( Iop_32UtoV128,
+ loadLE(Ity_I32, mkexpr(addr))) );
+ putXMMReg( rG, binop(op, vpart, mkexpr(epart)) );
+ DIP("%s %s,%s,%s\n", opname,
+ dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ delta = delta+alen;
+ }
+ putYMMRegLane128( rG, 1, mkV128(0) );
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+/* All-lanes AVX128 binary operation:
+ G[127:0] = V[127:0] `op` E[127:0]
+ G[255:128] = 0.
+*/
+static Long dis_AVX128_E_V_to_G ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ return dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, opname, op,
+ NULL, False/*!invertLeftArg*/, False/*!swapArgs*/
+ );
+}
+
+
+/* Handles AVX128 32F/64F comparisons. A derivative of
+ dis_SSEcmp_E_to_G. It can fail, in which case it returns the
+ original delta to indicate failure. */
+static
+Long dis_AVX128_cmp_V_E_to_G ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, Bool all_lanes, Int sz )
+{
+ vassert(sz == 4 || sz == 8);
+ Long deltaIN = delta;
+ HChar dis_buf[50];
+ Int alen;
+ UInt imm8;
+ IRTemp addr;
+ Bool preSwap = False;
+ IROp op = Iop_INVALID;
+ Bool postNot = False;
+ IRTemp plain = newTemp(Ity_V128);
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, rm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp argL = newTemp(Ity_V128);
+ IRTemp argR = newTemp(Ity_V128);
+
+ assign(argL, getXMMReg(rV));
+ if (epartIsReg(rm)) {
+ imm8 = getUChar(delta+1);
+ Bool ok = findSSECmpOp(&preSwap, &op, &postNot, imm8, all_lanes, sz);
+ if (!ok) return deltaIN; /* FAIL */
+ UInt rE = eregOfRexRM(pfx,rm);
+ assign(argR, getXMMReg(rE));
+ delta += 1+1;
+ DIP("%s $%d,%s,%s,%s\n",
+ opname, (Int)imm8,
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8 = getUChar(delta+alen);
+ Bool ok = findSSECmpOp(&preSwap, &op, &postNot, imm8, all_lanes, sz);
+ if (!ok) return deltaIN; /* FAIL */
+ assign(argR,
+ all_lanes ? loadLE(Ity_V128, mkexpr(addr))
+ : sz == 8 ? unop( Iop_64UtoV128, loadLE(Ity_I64, mkexpr(addr)))
+ : /*sz==4*/ unop( Iop_32UtoV128, loadLE(Ity_I32, mkexpr(addr))));
+ delta += alen+1;
+ DIP("%s $%d,%s,%s,%s\n",
+ opname, (Int)imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ }
+
+ assign(plain, preSwap ? binop(op, mkexpr(argR), mkexpr(argL))
+ : binop(op, mkexpr(argL), mkexpr(argR)));
+
+ if (all_lanes) {
+ /* This is simple: just invert the result, if necessary, and
+ have done. */
+ if (postNot) {
+ putYMMRegLoAndZU( rG, unop(Iop_NotV128, mkexpr(plain)) );
+ } else {
+ putYMMRegLoAndZU( rG, mkexpr(plain) );
+ }
+ }
+ else
+ if (!preSwap) {
+ /* More complex. It's a one-lane-only, hence need to possibly
+ invert only that one lane. But at least the other lanes are
+ correctly "in" the result, having been copied from the left
+ operand (argL). */
+ if (postNot) {
+ IRExpr* mask = mkV128(sz==4 ? 0x000F : 0x00FF);
+ putYMMRegLoAndZU( rG, binop(Iop_XorV128, mkexpr(plain),
+ mask) );
+ } else {
+ putYMMRegLoAndZU( rG, mkexpr(plain) );
+ }
+ }
+ else {
+ /* This is the most complex case. One-lane-only, but the args
+ were swapped. So we have to possibly invert the bottom lane,
+ and (definitely) we have to copy the upper lane(s) from argL
+ since, due to the swapping, what's currently there is from
+ argR, which is not correct. */
+ IRTemp res = newTemp(Ity_V128);
+ IRTemp mask = newTemp(Ity_V128);
+ IRTemp notMask = newTemp(Ity_V128);
+ assign(mask, mkV128(sz==4 ? 0x000F : 0x00FF));
+ assign(notMask, mkV128(sz==4 ? 0xFFF0 : 0xFF00));
+ if (postNot) {
+ assign(res,
+ binop(Iop_OrV128,
+ binop(Iop_AndV128,
+ unop(Iop_NotV128, mkexpr(plain)),
+ mkexpr(mask)),
+ binop(Iop_AndV128, mkexpr(argL), mkexpr(notMask))));
+ } else {
+ assign(res,
+ binop(Iop_OrV128,
+ binop(Iop_AndV128,
+ mkexpr(plain),
+ mkexpr(mask)),
+ binop(Iop_AndV128, mkexpr(argL), mkexpr(notMask))));
+ }
+ putYMMRegLoAndZU( rG, mkexpr(res) );
+ }
+
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+/* Handles AVX256 32F/64F comparisons. A derivative of
+ dis_SSEcmp_E_to_G. It can fail, in which case it returns the
+ original delta to indicate failure. */
+static
+Long dis_AVX256_cmp_V_E_to_G ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, Int sz )
+{
+ vassert(sz == 4 || sz == 8);
+ Long deltaIN = delta;
+ HChar dis_buf[50];
+ Int alen;
+ UInt imm8;
+ IRTemp addr;
+ Bool preSwap = False;
+ IROp op = Iop_INVALID;
+ Bool postNot = False;
+ IRTemp plain = newTemp(Ity_V256);
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, rm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp argL = newTemp(Ity_V256);
+ IRTemp argR = newTemp(Ity_V256);
+ IRTemp argLhi = IRTemp_INVALID;
+ IRTemp argLlo = IRTemp_INVALID;
+ IRTemp argRhi = IRTemp_INVALID;
+ IRTemp argRlo = IRTemp_INVALID;
+
+ assign(argL, getYMMReg(rV));
+ if (epartIsReg(rm)) {
+ imm8 = getUChar(delta+1);
+ Bool ok = findSSECmpOp(&preSwap, &op, &postNot, imm8,
+ True/*all_lanes*/, sz);
+ if (!ok) return deltaIN; /* FAIL */
+ UInt rE = eregOfRexRM(pfx,rm);
+ assign(argR, getYMMReg(rE));
+ delta += 1+1;
+ DIP("%s $%d,%s,%s,%s\n",
+ opname, (Int)imm8,
+ nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8 = getUChar(delta+alen);
+ Bool ok = findSSECmpOp(&preSwap, &op, &postNot, imm8,
+ True/*all_lanes*/, sz);
+ if (!ok) return deltaIN; /* FAIL */
+ assign(argR, loadLE(Ity_V256, mkexpr(addr)) );
+ delta += alen+1;
+ DIP("%s $%d,%s,%s,%s\n",
+ opname, (Int)imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ }
+
+ breakupV256toV128s( preSwap ? argR : argL, &argLhi, &argLlo );
+ breakupV256toV128s( preSwap ? argL : argR, &argRhi, &argRlo );
+ assign(plain, binop( Iop_V128HLtoV256,
+ binop(op, mkexpr(argLhi), mkexpr(argRhi)),
+ binop(op, mkexpr(argLlo), mkexpr(argRlo)) ) );
+
+ /* This is simple: just invert the result, if necessary, and
+ have done. */
+ if (postNot) {
+ putYMMReg( rG, unop(Iop_NotV256, mkexpr(plain)) );
+ } else {
+ putYMMReg( rG, mkexpr(plain) );
+ }
+
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+/* Handles AVX128 unary E-to-G all-lanes operations. */
+static
+Long dis_AVX128_E_to_G_unary ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname,
+ IRTemp (*opFn)(IRTemp) )
+{
+ HChar dis_buf[50];
+ Int alen;
+ IRTemp addr;
+ IRTemp res = newTemp(Ity_V128);
+ IRTemp arg = newTemp(Ity_V128);
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, rm);
+ if (epartIsReg(rm)) {
+ UInt rE = eregOfRexRM(pfx,rm);
+ assign(arg, getXMMReg(rE));
+ delta += 1;
+ DIP("%s %s,%s\n", opname, nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(arg, loadLE(Ity_V128, mkexpr(addr)));
+ delta += alen;
+ DIP("%s %s,%s\n", opname, dis_buf, nameXMMReg(rG));
+ }
+ res = opFn(arg);
+ putYMMRegLoAndZU( rG, mkexpr(res) );
+ *uses_vvvv = False;
+ return delta;
+}
+
+
+/* Handles AVX128 unary E-to-G all-lanes operations. */
+static
+Long dis_AVX128_E_to_G_unary_all ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ HChar dis_buf[50];
+ Int alen;
+ IRTemp addr;
+ IRTemp arg = newTemp(Ity_V128);
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, rm);
+ if (epartIsReg(rm)) {
+ UInt rE = eregOfRexRM(pfx,rm);
+ assign(arg, getXMMReg(rE));
+ delta += 1;
+ DIP("%s %s,%s\n", opname, nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(arg, loadLE(Ity_V128, mkexpr(addr)));
+ delta += alen;
+ DIP("%s %s,%s\n", opname, dis_buf, nameXMMReg(rG));
+ }
+ putYMMRegLoAndZU( rG, unop(op, mkexpr(arg)) );
+ *uses_vvvv = False;
+ return delta;
+}
+
+
+/* FIXME: common up with the _128_ version above? */
+static
+Long dis_VEX_NDS_256_AnySimdPfx_0F_WIG (
+ /*OUT*/Bool* uses_vvvv, VexAbiInfo* vbi,
+ Prefix pfx, Long delta, HChar* name,
+ /* The actual operation. Use either 'op' or 'opfn',
+ but not both. */
+ IROp op, IRTemp(*opFn)(IRTemp,IRTemp),
+ Bool invertLeftArg,
+ Bool swapArgs
+ )
+{
+ UChar modrm = getUChar(delta);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ UInt rSL = getVexNvvvv(pfx);
+ IRTemp tSL = newTemp(Ity_V256);
+ IRTemp tSR = newTemp(Ity_V256);
+ IRTemp addr = IRTemp_INVALID;
+ HChar dis_buf[50];
+ Int alen = 0;
+ vassert(1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*WIG?*/);
+
+ assign(tSL, invertLeftArg ? unop(Iop_NotV256, getYMMReg(rSL))
+ : getYMMReg(rSL));
+
+ if (epartIsReg(modrm)) {
+ UInt rSR = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ assign(tSR, getYMMReg(rSR));
+ DIP("%s %s,%s,%s\n",
+ name, nameYMMReg(rSR), nameYMMReg(rSL), nameYMMReg(rD));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ assign(tSR, loadLE(Ity_V256, mkexpr(addr)));
+ DIP("%s %s,%s,%s\n",
+ name, dis_buf, nameYMMReg(rSL), nameYMMReg(rD));
+ }
+
+ IRTemp res = IRTemp_INVALID;
+ if (op != Iop_INVALID) {
+ vassert(opFn == NULL);
+ res = newTemp(Ity_V256);
+ assign(res, swapArgs ? binop(op, mkexpr(tSR), mkexpr(tSL))
+ : binop(op, mkexpr(tSL), mkexpr(tSR)));
+ } else {
+ vassert(opFn != NULL);
+ res = swapArgs ? opFn(tSR, tSL) : opFn(tSL, tSR);
+ }
+
+ putYMMReg(rD, mkexpr(res));
+
+ *uses_vvvv = True;
+ return delta;
+}
+
+
+/* All-lanes AVX256 binary operation:
+ G[255:0] = V[255:0] `op` E[255:0]
+*/
+static Long dis_AVX256_E_V_to_G ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ return dis_VEX_NDS_256_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, opname, op,
+ NULL, False/*!invertLeftArg*/, False/*!swapArgs*/
+ );
+}
+
+
+/* Handle a VEX_NDS_256_66_0F_WIG (3-addr) insn, using the given IR
+ generator to compute the result, no inversion of the left
+ arg, and no swapping of args. */
+static
+Long dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex (
+ /*OUT*/Bool* uses_vvvv, VexAbiInfo* vbi,
+ Prefix pfx, Long delta, HChar* name,
+ IRTemp(*opFn)(IRTemp,IRTemp)
+ )
+{
+ return dis_VEX_NDS_256_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, name,
+ Iop_INVALID, opFn, False, False );
+}
+
+
+/* Handles AVX256 unary E-to-G all-lanes operations. */
+static
+Long dis_AVX256_E_to_G_unary_all ( /*OUT*/Bool* uses_vvvv,
+ VexAbiInfo* vbi,
+ Prefix pfx, Long delta,
+ HChar* opname, IROp op )
+{
+ HChar dis_buf[50];
+ Int alen;
+ IRTemp addr;
+ IRTemp arg = newTemp(Ity_V256);
+ UChar rm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, rm);
+ if (epartIsReg(rm)) {
+ UInt rE = eregOfRexRM(pfx,rm);
+ assign(arg, getYMMReg(rE));
+ delta += 1;
+ DIP("%s %s,%s\n", opname, nameYMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(arg, loadLE(Ity_V256, mkexpr(addr)));
+ delta += alen;
+ DIP("%s %s,%s\n", opname, dis_buf, nameYMMReg(rG));
+ }
+ putYMMReg( rG, unop(op, mkexpr(arg)) );
+ *uses_vvvv = False;
+ return delta;
+}
+
+
+/* The use of ReinterpF64asI64 is ugly. Surely could do better if we
+ had a variant of Iop_64x4toV256 that took F64s as args instead. */
+static Long dis_CVTDQ2PD_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ IRTemp sV = newTemp(Ity_V128);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("vcvtdq2pd %s,%s\n", nameXMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvtdq2pd %s,%s\n", dis_buf, nameYMMReg(rG) );
+ }
+ IRTemp s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+ IRExpr* res
+ = IRExpr_Qop(
+ Iop_64x4toV256,
+ unop(Iop_ReinterpF64asI64, unop(Iop_I32StoF64, mkexpr(s3))),
+ unop(Iop_ReinterpF64asI64, unop(Iop_I32StoF64, mkexpr(s2))),
+ unop(Iop_ReinterpF64asI64, unop(Iop_I32StoF64, mkexpr(s1))),
+ unop(Iop_ReinterpF64asI64, unop(Iop_I32StoF64, mkexpr(s0)))
+ );
+ putYMMReg(rG, res);
+ return delta;
+}
+
+
+static Long dis_CVTPD2PS_256 ( VexAbiInfo* vbi, Prefix pfx,
+ Long delta )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp argV = newTemp(Ity_V256);
+ IRTemp rmode = newTemp(Ity_I32);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( argV, getYMMReg(rE) );
+ delta += 1;
+ DIP("vcvtpd2psy %s,%s\n", nameYMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( argV, loadLE(Ity_V256, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvtpd2psy %s,%s\n", dis_buf, nameXMMReg(rG) );
+ }
+
+ assign( rmode, get_sse_roundingmode() );
+ IRTemp t3, t2, t1, t0;
+ t3 = t2 = t1 = t0 = IRTemp_INVALID;
+ breakupV256to64s( argV, &t3, &t2, &t1, &t0 );
+# define CVT(_t) binop( Iop_F64toF32, mkexpr(rmode), \
+ unop(Iop_ReinterpI64asF64, mkexpr(_t)) )
+ putXMMRegLane32F( rG, 3, CVT(t3) );
+ putXMMRegLane32F( rG, 2, CVT(t2) );
+ putXMMRegLane32F( rG, 1, CVT(t1) );
+ putXMMRegLane32F( rG, 0, CVT(t0) );
+# undef CVT
+ putYMMRegLane128( rG, 1, mkV128(0) );
+ return delta;
+}
+
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F__VEX (
+ /*MB_OUT*/DisResult* dres,
+ /*OUT*/ Bool* uses_vvvv,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN
+ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ *uses_vvvv = False;
+
+ switch (opc) {
+
+ case 0x10:
+ /* VMOVSD m64, xmm1 = VEX.LIG.F2.0F.WIG 10 /r */
+ /* Move 64 bits from E (mem only) to G (lo half xmm).
+ Bits 255-64 of the dest are zeroed out. */
+ if (haveF2no66noF3(pfx) && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp z128 = newTemp(Ity_V128);
+ assign(z128, mkV128(0));
+ putXMMReg( rG, mkexpr(z128) );
+ /* FIXME: ALIGNMENT CHECK? */
+ putXMMRegLane64( rG, 0, loadLE(Ity_I64, mkexpr(addr)) );
+ putYMMRegLane128( rG, 1, mkexpr(z128) );
+ DIP("vmovsd %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ goto decode_success;
+ }
+ /* VMOVSD xmm3, xmm2, xmm1 = VEX.LIG.F2.0F.WIG 10 /r */
+ /* Reg form. */
+ if (haveF2no66noF3(pfx) && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rE = eregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ delta++;
+ DIP("vmovsd %s,%s,%s\n",
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128,
+ getXMMRegLane64(rV, 1),
+ getXMMRegLane64(rE, 0)));
+ putYMMRegLoAndZU(rG, mkexpr(res));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VMOVSS m32, xmm1 = VEX.LIG.F3.0F.WIG 10 /r */
+ /* Move 32 bits from E (mem only) to G (lo half xmm).
+ Bits 255-32 of the dest are zeroed out. */
+ if (haveF3no66noF2(pfx) && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ UInt rG = gregOfRexRM(pfx,modrm);
+ IRTemp z128 = newTemp(Ity_V128);
+ assign(z128, mkV128(0));
+ putXMMReg( rG, mkexpr(z128) );
+ /* FIXME: ALIGNMENT CHECK? */
+ putXMMRegLane32( rG, 0, loadLE(Ity_I32, mkexpr(addr)) );
+ putYMMRegLane128( rG, 1, mkexpr(z128) );
+ DIP("vmovss %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ goto decode_success;
+ }
+ /* VMOVSS xmm3, xmm2, xmm1 = VEX.LIG.F3.0F.WIG 10 /r */
+ /* Reg form. */
+ if (haveF3no66noF2(pfx) && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rE = eregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ delta++;
+ DIP("vmovss %s,%s,%s\n",
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop( Iop_64HLtoV128,
+ getXMMRegLane64(rV, 1),
+ binop(Iop_32HLto64,
+ getXMMRegLane32(rV, 1),
+ getXMMRegLane32(rE, 0)) ) );
+ putYMMRegLoAndZU(rG, mkexpr(res));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VMOVUPD xmm2/m128, xmm1 = VEX.128.66.0F.WIG 10 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMRegLoAndZU( rG, getXMMReg( rE ));
+ DIP("vmovupd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putYMMRegLoAndZU( rG, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("vmovupd %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVUPD ymm2/m256, ymm1 = VEX.256.66.0F.WIG 10 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMReg( rG, getYMMReg( rE ));
+ DIP("vmovupd %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putYMMReg( rG, loadLE(Ity_V256, mkexpr(addr)) );
+ DIP("vmovupd %s,%s\n", dis_buf, nameYMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVUPS xmm2/m128, xmm1 = VEX.128.0F.WIG 10 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMRegLoAndZU( rG, getXMMReg( rE ));
+ DIP("vmovups %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putYMMRegLoAndZU( rG, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("vmovups %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVUPS ymm2/m256, ymm1 = VEX.256.0F.WIG 10 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMReg( rG, getYMMReg( rE ));
+ DIP("vmovups %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putYMMReg( rG, loadLE(Ity_V256, mkexpr(addr)) );
+ DIP("vmovups %s,%s\n", dis_buf, nameYMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x11:
+ /* VMOVSD xmm1, m64 = VEX.LIG.F2.0F.WIG 11 /r */
+ /* Move 64 bits from G (low half xmm) to mem only. */
+ if (haveF2no66noF3(pfx) && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ UInt rG = gregOfRexRM(pfx,modrm);
+ /* FIXME: ALIGNMENT CHECK? */
+ storeLE( mkexpr(addr), getXMMRegLane64(rG, 0));
+ DIP("vmovsd %s,%s\n", nameXMMReg(rG), dis_buf);
+ delta += alen;
+ goto decode_success;
+ }
+ /* VMOVSD xmm3, xmm2, xmm1 = VEX.LIG.F2.0F.WIG 11 /r */
+ /* Reg form. */
+ if (haveF2no66noF3(pfx) && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rE = eregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ delta++;
+ DIP("vmovsd %s,%s,%s\n",
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128,
+ getXMMRegLane64(rV, 1),
+ getXMMRegLane64(rE, 0)));
+ putYMMRegLoAndZU(rG, mkexpr(res));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VMOVSS xmm1, m64 = VEX.LIG.F3.0F.WIG 11 /r */
+ /* Move 32 bits from G (low 1/4 xmm) to mem only. */
+ if (haveF3no66noF2(pfx) && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ UInt rG = gregOfRexRM(pfx,modrm);
+ /* FIXME: ALIGNMENT CHECK? */
+ storeLE( mkexpr(addr), getXMMRegLane32(rG, 0));
+ DIP("vmovss %s,%s\n", nameXMMReg(rG), dis_buf);
+ delta += alen;
+ goto decode_success;
+ }
+ /* VMOVSS xmm3, xmm2, xmm1 = VEX.LIG.F3.0F.WIG 11 /r */
+ /* Reg form. */
+ if (haveF3no66noF2(pfx) && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rE = eregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ delta++;
+ DIP("vmovss %s,%s,%s\n",
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ IRTemp res = newTemp(Ity_V128);
+ assign( res, binop( Iop_64HLtoV128,
+ getXMMRegLane64(rV, 1),
+ binop(Iop_32HLto64,
+ getXMMRegLane32(rV, 1),
+ getXMMRegLane32(rE, 0)) ) );
+ putYMMRegLoAndZU(rG, mkexpr(res));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VMOVUPD xmm1, xmm2/m128 = VEX.128.66.0F.WIG 11 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMRegLoAndZU( rE, getXMMReg(rG) );
+ DIP("vmovupd %s,%s\n", nameXMMReg(rG), nameXMMReg(rE));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getXMMReg(rG) );
+ DIP("vmovupd %s,%s\n", nameXMMReg(rG), dis_buf);
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVUPD ymm1, ymm2/m256 = VEX.256.66.0F.WIG 11 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMReg( rE, getYMMReg(rG) );
+ DIP("vmovupd %s,%s\n", nameYMMReg(rG), nameYMMReg(rE));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getYMMReg(rG) );
+ DIP("vmovupd %s,%s\n", nameYMMReg(rG), dis_buf);
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVUPS xmm1, xmm2/m128 = VEX.128.0F.WIG 11 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMRegLoAndZU( rE, getXMMReg(rG) );
+ DIP("vmovups %s,%s\n", nameXMMReg(rG), nameXMMReg(rE));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getXMMReg(rG) );
+ DIP("vmovups %s,%s\n", nameXMMReg(rG), dis_buf);
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVUPS ymm1, ymm2/m256 = VEX.256.0F.WIG 11 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMReg( rE, getYMMReg(rG) );
+ DIP("vmovups %s,%s\n", nameYMMReg(rG), nameYMMReg(rE));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getYMMReg(rG) );
+ DIP("vmovups %s,%s\n", nameYMMReg(rG), dis_buf);
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x12:
+ /* VMOVDDUP xmm2/m64, xmm1 = VEX.128.F2.0F.WIG /12 r */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_MOVDDUP_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ /* VMOVDDUP ymm2/m256, ymm1 = VEX.256.F2.0F.WIG /12 r */
+ if (haveF2no66noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_MOVDDUP_256( vbi, pfx, delta );
+ goto decode_success;
+ }
+ /* VMOVHLPS xmm3, xmm2, xmm1 = VEX.NDS.128.0F.WIG 12 /r */
+ /* Insn only exists in reg form */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rE = eregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ delta++;
+ DIP("vmovhlps %s,%s,%s\n",
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128,
+ getXMMRegLane64(rV, 1),
+ getXMMRegLane64(rE, 1)));
+ putYMMRegLoAndZU(rG, mkexpr(res));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VMOVLPS m64, xmm1, xmm2 = VEX.NDS.128.0F.WIG 12 /r */
+ /* Insn exists only in mem form, it appears. */
+ /* VMOVLPD m64, xmm1, xmm2 = VEX.NDS.128.66.0F.WIG 12 /r */
+ /* Insn exists only in mem form, it appears. */
+ if ((have66noF2noF3(pfx) || haveNo66noF2noF3(pfx))
+ && 0==getVexL(pfx)/*128*/ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vmovlpd %s,%s,%s\n",
+ dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128,
+ getXMMRegLane64(rV, 1),
+ loadLE(Ity_I64, mkexpr(addr))));
+ putYMMRegLoAndZU(rG, mkexpr(res));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VMOVSLDUP xmm2/m128, xmm1 = VEX.NDS.128.F3.0F.WIG 12 /r */
+ if (haveF3no66noF2(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_MOVSxDUP_128( vbi, pfx, delta, True/*isAvx*/,
+ True/*isL*/ );
+ goto decode_success;
+ }
+ /* VMOVSLDUP ymm2/m256, ymm1 = VEX.NDS.256.F3.0F.WIG 12 /r */
+ if (haveF3no66noF2(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_MOVSxDUP_256( vbi, pfx, delta, True/*isL*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x13:
+ /* VMOVLPS xmm1, m64 = VEX.128.0F.WIG 13 /r */
+ /* Insn exists only in mem form, it appears. */
+ /* VMOVLPD xmm1, m64 = VEX.128.66.0F.WIG 13 /r */
+ /* Insn exists only in mem form, it appears. */
+ if ((have66noF2noF3(pfx) || haveNo66noF2noF3(pfx))
+ && 0==getVexL(pfx)/*128*/ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ storeLE( mkexpr(addr), getXMMRegLane64( rG, 0));
+ DIP("vmovlpd %s,%s\n", nameXMMReg(rG), dis_buf);
+ goto decode_success;
+ }
+ break;
+
+ case 0x14:
+ case 0x15:
+ /* VUNPCKLPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 14 /r */
+ /* VUNPCKHPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 15 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ Bool hi = opc == 0x15;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp eV = newTemp(Ity_V128);
+ IRTemp vV = newTemp(Ity_V128);
+ assign( vV, getXMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getXMMReg(rE) );
+ delta += 1;
+ DIP("vunpck%sps %s,%s\n", hi ? "h" : "l",
+ nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("vunpck%sps %s,%s\n", hi ? "h" : "l",
+ dis_buf, nameXMMReg(rG));
+ }
+ IRTemp res = math_UNPCKxPS_128( eV, vV, hi );
+ putYMMRegLoAndZU( rG, mkexpr(res) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VUNPCKLPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 14 /r */
+ /* VUNPCKHPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 15 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ Bool hi = opc == 0x15;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp eV = newTemp(Ity_V256);
+ IRTemp vV = newTemp(Ity_V256);
+ assign( vV, getYMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getYMMReg(rE) );
+ delta += 1;
+ DIP("vunpck%sps %s,%s\n", hi ? "h" : "l",
+ nameYMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V256, mkexpr(addr)) );
+ delta += alen;
+ DIP("vunpck%sps %s,%s\n", hi ? "h" : "l",
+ dis_buf, nameYMMReg(rG));
+ }
+ IRTemp res = math_UNPCKxPS_256( eV, vV, hi );
+ putYMMReg( rG, mkexpr(res) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VUNPCKLPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 14 /r */
+ /* VUNPCKHPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 15 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ Bool hi = opc == 0x15;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp eV = newTemp(Ity_V128);
+ IRTemp vV = newTemp(Ity_V128);
+ assign( vV, getXMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getXMMReg(rE) );
+ delta += 1;
+ DIP("vunpck%spd %s,%s\n", hi ? "h" : "l",
+ nameXMMReg(rE), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("vunpck%spd %s,%s\n", hi ? "h" : "l",
+ dis_buf, nameXMMReg(rG));
+ }
+ IRTemp res = math_UNPCKxPD_128( eV, vV, hi );
+ putYMMRegLoAndZU( rG, mkexpr(res) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VUNPCKLPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 14 /r */
+ /* VUNPCKHPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 15 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ Bool hi = opc == 0x15;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp eV = newTemp(Ity_V256);
+ IRTemp vV = newTemp(Ity_V256);
+ assign( vV, getYMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getYMMReg(rE) );
+ delta += 1;
+ DIP("vunpck%spd %s,%s\n", hi ? "h" : "l",
+ nameYMMReg(rE), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( eV, loadLE(Ity_V256, mkexpr(addr)) );
+ delta += alen;
+ DIP("vunpck%spd %s,%s\n", hi ? "h" : "l",
+ dis_buf, nameYMMReg(rG));
+ }
+ IRTemp res = math_UNPCKxPD_256( eV, vV, hi );
+ putYMMReg( rG, mkexpr(res) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x16:
+ /* VMOVLHPS xmm3, xmm2, xmm1 = VEX.NDS.128.0F.WIG 16 /r */
+ /* Insn only exists in reg form */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rE = eregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ delta++;
+ DIP("vmovlhps %s,%s,%s\n",
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128,
+ getXMMRegLane64(rE, 0),
+ getXMMRegLane64(rV, 0)));
+ putYMMRegLoAndZU(rG, mkexpr(res));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VMOVHPS m64, xmm1, xmm2 = VEX.NDS.128.0F.WIG 16 /r */
+ /* Insn exists only in mem form, it appears. */
+ /* VMOVHPD m64, xmm1, xmm2 = VEX.NDS.128.66.0F.WIG 16 /r */
+ /* Insn exists only in mem form, it appears. */
+ if ((have66noF2noF3(pfx) || haveNo66noF2noF3(pfx))
+ && 0==getVexL(pfx)/*128*/ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vmovhp%c %s,%s,%s\n", have66(pfx) ? 'd' : 's',
+ dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128,
+ loadLE(Ity_I64, mkexpr(addr)),
+ getXMMRegLane64(rV, 0)));
+ putYMMRegLoAndZU(rG, mkexpr(res));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VMOVSHDUP xmm2/m128, xmm1 = VEX.NDS.128.F3.0F.WIG 16 /r */
+ if (haveF3no66noF2(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_MOVSxDUP_128( vbi, pfx, delta, True/*isAvx*/,
+ False/*!isL*/ );
+ goto decode_success;
+ }
+ /* VMOVSHDUP ymm2/m256, ymm1 = VEX.NDS.256.F3.0F.WIG 16 /r */
+ if (haveF3no66noF2(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_MOVSxDUP_256( vbi, pfx, delta, False/*!isL*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x17:
+ /* VMOVHPS xmm1, m64 = VEX.128.0F.WIG 17 /r */
+ /* Insn exists only in mem form, it appears. */
+ /* VMOVHPD xmm1, m64 = VEX.128.66.0F.WIG 17 /r */
+ /* Insn exists only in mem form, it appears. */
+ if ((have66noF2noF3(pfx) || haveNo66noF2noF3(pfx))
+ && 0==getVexL(pfx)/*128*/ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ storeLE( mkexpr(addr), getXMMRegLane64( rG, 1));
+ DIP("vmovhp%c %s,%s\n", have66(pfx) ? 'd' : 's',
+ nameXMMReg(rG), dis_buf);
+ goto decode_success;
+ }
+ break;
+
+ case 0x28:
+ /* VMOVAPD xmm2/m128, xmm1 = VEX.128.66.0F.WIG 28 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMRegLoAndZU( rG, getXMMReg( rE ));
+ DIP("vmovapd %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ putYMMRegLoAndZU( rG, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("vmovapd %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVAPD ymm2/m256, ymm1 = VEX.256.66.0F.WIG 28 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMReg( rG, getYMMReg( rE ));
+ DIP("vmovapd %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_32_aligned( addr );
+ putYMMReg( rG, loadLE(Ity_V256, mkexpr(addr)) );
+ DIP("vmovapd %s,%s\n", dis_buf, nameYMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVAPS xmm2/m128, xmm1 = VEX.128.0F.WIG 28 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMRegLoAndZU( rG, getXMMReg( rE ));
+ DIP("vmovaps %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ putYMMRegLoAndZU( rG, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("vmovaps %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVAPS ymm2/m256, ymm1 = VEX.256.0F.WIG 28 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMReg( rG, getYMMReg( rE ));
+ DIP("vmovaps %s,%s\n", nameYMMReg(rE), nameYMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_32_aligned( addr );
+ putYMMReg( rG, loadLE(Ity_V256, mkexpr(addr)) );
+ DIP("vmovaps %s,%s\n", dis_buf, nameYMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x29:
+ /* VMOVAPD xmm1, xmm2/m128 = VEX.128.66.0F.WIG 29 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMRegLoAndZU( rE, getXMMReg(rG) );
+ DIP("vmovapd %s,%s\n", nameXMMReg(rG), nameXMMReg(rE));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ storeLE( mkexpr(addr), getXMMReg(rG) );
+ DIP("vmovapd %s,%s\n", nameXMMReg(rG), dis_buf );
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVAPD ymm1, ymm2/m256 = VEX.256.66.0F.WIG 29 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMReg( rE, getYMMReg(rG) );
+ DIP("vmovapd %s,%s\n", nameYMMReg(rG), nameYMMReg(rE));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_32_aligned( addr );
+ storeLE( mkexpr(addr), getYMMReg(rG) );
+ DIP("vmovapd %s,%s\n", nameYMMReg(rG), dis_buf );
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVAPS xmm1, xmm2/m128 = VEX.128.0F.WIG 29 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMRegLoAndZU( rE, getXMMReg(rG) );
+ DIP("vmovaps %s,%s\n", nameXMMReg(rG), nameXMMReg(rE));
+ delta += 1;
+ goto decode_success;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ storeLE( mkexpr(addr), getXMMReg(rG) );
+ DIP("vmovaps %s,%s\n", nameXMMReg(rG), dis_buf );
+ delta += alen;
+ goto decode_success;
+ }
+ }
+ /* VMOVAPS ymm1, ymm2/m256 = VEX.256.0F.WIG 29 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putYMMReg( rE, getYMMReg(rG) );
+ DIP("vmovaps %s,%s\n", nameYMMReg(rG), nameYMMReg(rE));
+ delta += 1;
+ goto decode_success;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_32_aligned( addr );
+ storeLE( mkexpr(addr), getYMMReg(rG) );
+ DIP("vmovaps %s,%s\n", nameYMMReg(rG), dis_buf );
+ delta += alen;
+ goto decode_success;
+ }
+ }
+ break;
+
+ case 0x2A: {
+ IRTemp rmode = newTemp(Ity_I32);
+ assign( rmode, get_sse_roundingmode() );
+ /* VCVTSI2SD r/m32, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.W0 2A /r */
+ if (haveF2no66noF3(pfx) && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rV = getVexNvvvv(pfx);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp arg32 = newTemp(Ity_I32);
+ if (epartIsReg(modrm)) {
+ UInt rS = eregOfRexRM(pfx,modrm);
+ assign( arg32, getIReg32(rS) );
+ delta += 1;
+ DIP("vcvtsi2sdl %s,%s,%s\n",
+ nameIReg32(rS), nameXMMReg(rV), nameXMMReg(rD));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg32, loadLE(Ity_I32, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvtsi2sdl %s,%s,%s\n",
+ dis_buf, nameXMMReg(rV), nameXMMReg(rD));
+ }
+ putXMMRegLane64F( rD, 0,
+ unop(Iop_I32StoF64, mkexpr(arg32)));
+ putXMMRegLane64( rD, 1, getXMMRegLane64( rV, 1 ));
+ putYMMRegLane128( rD, 1, mkV128(0) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VCVTSI2SD r/m64, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.W1 2A /r */
+ if (haveF2no66noF3(pfx) && 1==getRexW(pfx)/*W1*/) {
+ UChar modrm = getUChar(delta);
+ UInt rV = getVexNvvvv(pfx);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp arg64 = newTemp(Ity_I64);
+ if (epartIsReg(modrm)) {
+ UInt rS = eregOfRexRM(pfx,modrm);
+ assign( arg64, getIReg64(rS) );
+ delta += 1;
+ DIP("vcvtsi2sdq %s,%s,%s\n",
+ nameIReg64(rS), nameXMMReg(rV), nameXMMReg(rD));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvtsi2sdq %s,%s,%s\n",
+ dis_buf, nameXMMReg(rV), nameXMMReg(rD));
+ }
+ putXMMRegLane64F( rD, 0,
+ binop( Iop_I64StoF64,
+ get_sse_roundingmode(),
+ mkexpr(arg64)) );
+ putXMMRegLane64( rD, 1, getXMMRegLane64( rV, 1 ));
+ putYMMRegLane128( rD, 1, mkV128(0) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VCVTSI2SS r/m64, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.W1 2A /r */
+ if (haveF3no66noF2(pfx) && 1==getRexW(pfx)/*W1*/) {
+ UChar modrm = getUChar(delta);
+ UInt rV = getVexNvvvv(pfx);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp arg64 = newTemp(Ity_I64);
+ if (epartIsReg(modrm)) {
+ UInt rS = eregOfRexRM(pfx,modrm);
+ assign( arg64, getIReg64(rS) );
+ delta += 1;
+ DIP("vcvtsi2ssq %s,%s,%s\n",
+ nameIReg64(rS), nameXMMReg(rV), nameXMMReg(rD));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg64, loadLE(Ity_I64, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvtsi2ssq %s,%s,%s\n",
+ dis_buf, nameXMMReg(rV), nameXMMReg(rD));
+ }
+ putXMMRegLane32F( rD, 0,
+ binop(Iop_F64toF32,
+ mkexpr(rmode),
+ binop(Iop_I64StoF64, mkexpr(rmode),
+ mkexpr(arg64)) ) );
+ putXMMRegLane32( rD, 1, getXMMRegLane32( rV, 1 ));
+ putXMMRegLane64( rD, 1, getXMMRegLane64( rV, 1 ));
+ putYMMRegLane128( rD, 1, mkV128(0) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VCVTSI2SS r/m32, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.W0 2A /r */
+ if (haveF3no66noF2(pfx) && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rV = getVexNvvvv(pfx);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp arg32 = newTemp(Ity_I32);
+ if (epartIsReg(modrm)) {
+ UInt rS = eregOfRexRM(pfx,modrm);
+ assign( arg32, getIReg32(rS) );
+ delta += 1;
+ DIP("vcvtsi2ssl %s,%s,%s\n",
+ nameIReg32(rS), nameXMMReg(rV), nameXMMReg(rD));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( arg32, loadLE(Ity_I32, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvtsi2ssl %s,%s,%s\n",
+ dis_buf, nameXMMReg(rV), nameXMMReg(rD));
+ }
+ putXMMRegLane32F( rD, 0,
+ binop(Iop_F64toF32,
+ mkexpr(rmode),
+ unop(Iop_I32StoF64, mkexpr(arg32)) ) );
+ putXMMRegLane32( rD, 1, getXMMRegLane32( rV, 1 ));
+ putXMMRegLane64( rD, 1, getXMMRegLane64( rV, 1 ));
+ putYMMRegLane128( rD, 1, mkV128(0) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+ }
+
+ case 0x2B:
+ /* VMOVNTPD xmm1, m128 = VEX.128.66.0F.WIG 2B /r */
+ /* VMOVNTPS xmm1, m128 = VEX.128.0F.WIG 2B /r */
+ if ((have66noF2noF3(pfx) || haveNo66noF2noF3(pfx))
+ && 0==getVexL(pfx)/*128*/ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rS = gregOfRexRM(pfx, modrm);
+ IRTemp tS = newTemp(Ity_V128);
+ assign(tS, getXMMReg(rS));
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_16_aligned(addr);
+ storeLE(mkexpr(addr), mkexpr(tS));
+ DIP("vmovntp%c %s,%s\n", have66(pfx) ? 'd' : 's',
+ nameXMMReg(rS), dis_buf);
+ goto decode_success;
+ }
+ /* VMOVNTPD ymm1, m256 = VEX.256.66.0F.WIG 2B /r */
+ /* VMOVNTPS ymm1, m256 = VEX.256.0F.WIG 2B /r */
+ if ((have66noF2noF3(pfx) || haveNo66noF2noF3(pfx))
+ && 1==getVexL(pfx)/*256*/ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rS = gregOfRexRM(pfx, modrm);
+ IRTemp tS = newTemp(Ity_V256);
+ assign(tS, getYMMReg(rS));
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_32_aligned(addr);
+ storeLE(mkexpr(addr), mkexpr(tS));
+ DIP("vmovntp%c %s,%s\n", have66(pfx) ? 'd' : 's',
+ nameYMMReg(rS), dis_buf);
+ goto decode_success;
+ }
+ break;
+
+ case 0x2C:
+ /* VCVTTSD2SI xmm1/m32, r32 = VEX.LIG.F2.0F.W0 2C /r */
+ if (haveF2no66noF3(pfx) && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_CVTxSD2SI( vbi, pfx, delta, True/*isAvx*/, opc, 4);
+ goto decode_success;
+ }
+ /* VCVTTSD2SI xmm1/m64, r64 = VEX.LIG.F2.0F.W1 2C /r */
+ if (haveF2no66noF3(pfx) && 1==getRexW(pfx)/*W1*/) {
+ delta = dis_CVTxSD2SI( vbi, pfx, delta, True/*isAvx*/, opc, 8);
+ goto decode_success;
+ }
+ /* VCVTTSS2SI xmm1/m32, r32 = VEX.LIG.F3.0F.W0 2C /r */
+ if (haveF3no66noF2(pfx) && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_CVTxSS2SI( vbi, pfx, delta, True/*isAvx*/, opc, 4);
+ goto decode_success;
+ }
+ /* VCVTTSS2SI xmm1/m64, r64 = VEX.LIG.F3.0F.W1 2C /r */
+ if (haveF3no66noF2(pfx) && 1==getRexW(pfx)/*W1*/) {
+ delta = dis_CVTxSS2SI( vbi, pfx, delta, True/*isAvx*/, opc, 8);
+ goto decode_success;
+ }
+ break;
+
+ case 0x2D:
+ /* VCVTSD2SI xmm1/m32, r32 = VEX.LIG.F2.0F.W0 2D /r */
+ if (haveF2no66noF3(pfx) && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_CVTxSD2SI( vbi, pfx, delta, True/*isAvx*/, opc, 4);
+ goto decode_success;
+ }
+ /* VCVTSD2SI xmm1/m64, r64 = VEX.LIG.F2.0F.W1 2D /r */
+ if (haveF2no66noF3(pfx) && 1==getRexW(pfx)/*W1*/) {
+ delta = dis_CVTxSD2SI( vbi, pfx, delta, True/*isAvx*/, opc, 8);
+ goto decode_success;
+ }
+ /* VCVTSS2SI xmm1/m32, r32 = VEX.LIG.F3.0F.W0 2D /r */
+ if (haveF3no66noF2(pfx) && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_CVTxSS2SI( vbi, pfx, delta, True/*isAvx*/, opc, 4);
+ goto decode_success;
+ }
+ /* VCVTSS2SI xmm1/m64, r64 = VEX.LIG.F3.0F.W1 2D /r */
+ if (haveF3no66noF2(pfx) && 1==getRexW(pfx)/*W1*/) {
+ delta = dis_CVTxSS2SI( vbi, pfx, delta, True/*isAvx*/, opc, 8);
+ goto decode_success;
+ }
+ break;
+
+ case 0x2E:
+ case 0x2F:
+ /* VUCOMISD xmm2/m64, xmm1 = VEX.LIG.66.0F.WIG 2E /r */
+ /* VCOMISD xmm2/m64, xmm1 = VEX.LIG.66.0F.WIG 2F /r */
+ if (have66noF2noF3(pfx)) {
+ delta = dis_COMISD( vbi, pfx, delta, True/*isAvx*/, opc );
+ goto decode_success;
+ }
+ /* VUCOMISS xmm2/m32, xmm1 = VEX.LIG.0F.WIG 2E /r */
+ /* VCOMISS xmm2/m32, xmm1 = VEX.LIG.0F.WIG 2F /r */
+ if (haveNo66noF2noF3(pfx)) {
+ delta = dis_COMISS( vbi, pfx, delta, True/*isAvx*/, opc );
+ goto decode_success;
+ }
+ break;
+
+ case 0x50:
+ /* VMOVMSKPD xmm2, r32 = VEX.128.66.0F.WIG 50 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_MOVMSKPD_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ /* VMOVMSKPD ymm2, r32 = VEX.256.66.0F.WIG 50 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_MOVMSKPD_256( vbi, pfx, delta );
+ goto decode_success;
+ }
+ /* VMOVMSKPS xmm2, r32 = VEX.128.0F.WIG 50 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_MOVMSKPS_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ /* VMOVMSKPS ymm2, r32 = VEX.256.0F.WIG 50 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_MOVMSKPS_256( vbi, pfx, delta );
+ goto decode_success;
+ }
+ break;
+
+ case 0x51:
+ /* VSQRTSS xmm3/m64(E), xmm2(V), xmm1(G) = VEX.NDS.LIG.F3.0F.WIG 51 /r */
+ if (haveF3no66noF2(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo32_unary(
+ uses_vvvv, vbi, pfx, delta, "vsqrtss", Iop_Sqrt32F0x4 );
+ goto decode_success;
+ }
+ /* VSQRTPS xmm2/m128(E), xmm1(G) = VEX.NDS.128.0F.WIG 51 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_to_G_unary_all(
+ uses_vvvv, vbi, pfx, delta, "vsqrtps", Iop_Sqrt32Fx4 );
+ goto decode_success;
+ }
+ /* VSQRTPS ymm2/m256(E), ymm1(G) = VEX.NDS.256.0F.WIG 51 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_to_G_unary_all(
+ uses_vvvv, vbi, pfx, delta, "vsqrtps", Iop_Sqrt32Fx8 );
+ goto decode_success;
+ }
+ /* VSQRTSD xmm3/m64(E), xmm2(V), xmm1(G) = VEX.NDS.LIG.F2.0F.WIG 51 /r */
+ if (haveF2no66noF3(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo64_unary(
+ uses_vvvv, vbi, pfx, delta, "vsqrtsd", Iop_Sqrt64F0x2 );
+ goto decode_success;
+ }
+ /* VSQRTPD xmm2/m128(E), xmm1(G) = VEX.NDS.128.66.0F.WIG 51 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_to_G_unary_all(
+ uses_vvvv, vbi, pfx, delta, "vsqrtpd", Iop_Sqrt64Fx2 );
+ goto decode_success;
+ }
+ /* VSQRTPD ymm2/m256(E), ymm1(G) = VEX.NDS.256.66.0F.WIG 51 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_to_G_unary_all(
+ uses_vvvv, vbi, pfx, delta, "vsqrtpd", Iop_Sqrt64Fx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x52:
+ /* VRSQRTSS xmm3/m64(E), xmm2(V), xmm1(G) = VEX.NDS.LIG.F3.0F.WIG 52 /r */
+ if (haveF3no66noF2(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo32_unary(
+ uses_vvvv, vbi, pfx, delta, "vrsqrtss", Iop_RSqrt32F0x4 );
+ goto decode_success;
+ }
+ /* VRSQRTPS xmm2/m128(E), xmm1(G) = VEX.NDS.128.0F.WIG 52 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_to_G_unary_all(
+ uses_vvvv, vbi, pfx, delta, "vrsqrtps", Iop_RSqrt32Fx4 );
+ goto decode_success;
+ }
+ /* VRSQRTPS ymm2/m256(E), ymm1(G) = VEX.NDS.256.0F.WIG 52 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_to_G_unary_all(
+ uses_vvvv, vbi, pfx, delta, "vrsqrtps", Iop_RSqrt32Fx8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x53:
+ /* VRCPSS xmm3/m64(E), xmm2(V), xmm1(G) = VEX.NDS.LIG.F3.0F.WIG 53 /r */
+ if (haveF3no66noF2(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo32_unary(
+ uses_vvvv, vbi, pfx, delta, "vrcpss", Iop_Recip32F0x4 );
+ goto decode_success;
+ }
+ /* VRCPPS xmm2/m128(E), xmm1(G) = VEX.NDS.128.0F.WIG 53 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_to_G_unary_all(
+ uses_vvvv, vbi, pfx, delta, "vrcpps", Iop_Recip32Fx4 );
+ goto decode_success;
+ }
+ /* VRCPPS ymm2/m256(E), ymm1(G) = VEX.NDS.256.0F.WIG 53 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_to_G_unary_all(
+ uses_vvvv, vbi, pfx, delta, "vrcpps", Iop_Recip32Fx8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x54:
+ /* VANDPD r/m, rV, r ::: r = rV & r/m */
+ /* VANDPD = VEX.NDS.128.66.0F.WIG 54 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vandpd", Iop_AndV128 );
+ goto decode_success;
+ }
+ /* VANDPD r/m, rV, r ::: r = rV & r/m */
+ /* VANDPD = VEX.NDS.256.66.0F.WIG 54 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vandpd", Iop_AndV256 );
+ goto decode_success;
+ }
+ /* VANDPS = VEX.NDS.128.0F.WIG 54 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vandps", Iop_AndV128 );
+ goto decode_success;
+ }
+ /* VANDPS = VEX.NDS.256.0F.WIG 54 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vandps", Iop_AndV256 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x55:
+ /* VANDNPD r/m, rV, r ::: r = (not rV) & r/m */
+ /* VANDNPD = VEX.NDS.128.66.0F.WIG 55 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vandpd", Iop_AndV128,
+ NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
+ goto decode_success;
+ }
+ /* VANDNPD = VEX.NDS.256.66.0F.WIG 55 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vandpd", Iop_AndV256,
+ NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
+ goto decode_success;
+ }
+ /* VANDNPS = VEX.NDS.128.0F.WIG 55 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vandps", Iop_AndV128,
+ NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
+ goto decode_success;
+ }
+ /* VANDNPS = VEX.NDS.256.0F.WIG 55 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vandps", Iop_AndV256,
+ NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x56:
+ /* VORPD r/m, rV, r ::: r = rV | r/m */
+ /* VORPD = VEX.NDS.128.66.0F.WIG 56 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vorpd", Iop_OrV128 );
+ goto decode_success;
+ }
+ /* VORPD r/m, rV, r ::: r = rV | r/m */
+ /* VORPD = VEX.NDS.256.66.0F.WIG 56 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vorpd", Iop_OrV256 );
+ goto decode_success;
+ }
+ /* VORPS r/m, rV, r ::: r = rV | r/m */
+ /* VORPS = VEX.NDS.128.0F.WIG 56 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vorps", Iop_OrV128 );
+ goto decode_success;
+ }
+ /* VORPS r/m, rV, r ::: r = rV | r/m */
+ /* VORPS = VEX.NDS.256.0F.WIG 56 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vorps", Iop_OrV256 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x57:
+ /* VXORPD r/m, rV, r ::: r = rV ^ r/m */
+ /* VXORPD = VEX.NDS.128.66.0F.WIG 57 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vxorpd", Iop_XorV128 );
+ goto decode_success;
+ }
+ /* VXORPD r/m, rV, r ::: r = rV ^ r/m */
+ /* VXORPD = VEX.NDS.256.66.0F.WIG 57 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vxorpd", Iop_XorV256 );
+ goto decode_success;
+ }
+ /* VXORPS r/m, rV, r ::: r = rV ^ r/m */
+ /* VXORPS = VEX.NDS.128.0F.WIG 57 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vxorps", Iop_XorV128 );
+ goto decode_success;
+ }
+ /* VXORPS r/m, rV, r ::: r = rV ^ r/m */
+ /* VXORPS = VEX.NDS.256.0F.WIG 57 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vxorps", Iop_XorV256 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x58:
+ /* VADDSD xmm3/m64, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.WIG 58 /r */
+ if (haveF2no66noF3(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo64(
+ uses_vvvv, vbi, pfx, delta, "vaddsd", Iop_Add64F0x2 );
+ goto decode_success;
+ }
+ /* VADDSS xmm3/m32, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.WIG 58 /r */
+ if (haveF3no66noF2(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo32(
+ uses_vvvv, vbi, pfx, delta, "vaddss", Iop_Add32F0x4 );
+ goto decode_success;
+ }
+ /* VADDPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 58 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vaddps", Iop_Add32Fx4 );
+ goto decode_success;
+ }
+ /* VADDPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 58 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vaddps", Iop_Add32Fx8 );
+ goto decode_success;
+ }
+ /* VADDPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 58 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vaddpd", Iop_Add64Fx2 );
+ goto decode_success;
+ }
+ /* VADDPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 58 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vaddpd", Iop_Add64Fx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x59:
+ /* VMULSD xmm3/m64, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.WIG 59 /r */
+ if (haveF2no66noF3(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo64(
+ uses_vvvv, vbi, pfx, delta, "vmulsd", Iop_Mul64F0x2 );
+ goto decode_success;
+ }
+ /* VMULSS xmm3/m32, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.WIG 59 /r */
+ if (haveF3no66noF2(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo32(
+ uses_vvvv, vbi, pfx, delta, "vmulss", Iop_Mul32F0x4 );
+ goto decode_success;
+ }
+ /* VMULPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 59 /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vmulps", Iop_Mul32Fx4 );
+ goto decode_success;
+ }
+ /* VMULPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 59 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vmulps", Iop_Mul32Fx8 );
+ goto decode_success;
+ }
+ /* VMULPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 59 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vmulpd", Iop_Mul64Fx2 );
+ goto decode_success;
+ }
+ /* VMULPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 59 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vmulpd", Iop_Mul64Fx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5A:
+ /* VCVTPS2PD xmm2/m64, xmm1 = VEX.128.0F.WIG 5A /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_CVTPS2PD_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ /* VCVTPS2PD xmm2/m128, ymm1 = VEX.256.0F.WIG 5A /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_CVTPS2PD_256( vbi, pfx, delta );
+ goto decode_success;
+ }
+ /* VCVTPD2PS xmm2/m128, xmm1 = VEX.128.66.0F.WIG 5A /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_CVTPD2PS_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ /* VCVTPD2PS ymm2/m256, xmm1 = VEX.256.66.0F.WIG 5A /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_CVTPD2PS_256( vbi, pfx, delta );
+ goto decode_success;
+ }
+ /* VCVTSD2SS xmm3/m64, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.WIG 5A /r */
+ if (haveF2no66noF3(pfx)) {
+ UChar modrm = getUChar(delta);
+ UInt rV = getVexNvvvv(pfx);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp f64lo = newTemp(Ity_F64);
+ IRTemp rmode = newTemp(Ity_I32);
+ assign( rmode, get_sse_roundingmode() );
+ if (epartIsReg(modrm)) {
+ UInt rS = eregOfRexRM(pfx,modrm);
+ assign(f64lo, getXMMRegLane64F(rS, 0));
+ delta += 1;
+ DIP("vcvtsd2ss %s,%s,%s\n",
+ nameXMMReg(rS), nameXMMReg(rV), nameXMMReg(rD));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(f64lo, loadLE(Ity_F64, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvtsd2ss %s,%s,%s\n",
+ dis_buf, nameXMMReg(rV), nameXMMReg(rD));
+ }
+ putXMMRegLane32F( rD, 0,
+ binop( Iop_F64toF32, mkexpr(rmode),
+ mkexpr(f64lo)) );
+ putXMMRegLane32( rD, 1, getXMMRegLane32( rV, 1 ));
+ putXMMRegLane64( rD, 1, getXMMRegLane64( rV, 1 ));
+ putYMMRegLane128( rD, 1, mkV128(0) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VCVTSS2SD xmm3/m32, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.WIG 5A /r */
+ if (haveF3no66noF2(pfx)) {
+ UChar modrm = getUChar(delta);
+ UInt rV = getVexNvvvv(pfx);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp f32lo = newTemp(Ity_F32);
+ if (epartIsReg(modrm)) {
+ UInt rS = eregOfRexRM(pfx,modrm);
+ assign(f32lo, getXMMRegLane32F(rS, 0));
+ delta += 1;
+ DIP("vcvtss2sd %s,%s,%s\n",
+ nameXMMReg(rS), nameXMMReg(rV), nameXMMReg(rD));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign(f32lo, loadLE(Ity_F32, mkexpr(addr)) );
+ delta += alen;
+ DIP("vcvtss2sd %s,%s,%s\n",
+ dis_buf, nameXMMReg(rV), nameXMMReg(rD));
+ }
+ putXMMRegLane64F( rD, 0,
+ unop( Iop_F32toF64, mkexpr(f32lo)) );
+ putXMMRegLane64( rD, 1, getXMMRegLane64( rV, 1 ));
+ putYMMRegLane128( rD, 1, mkV128(0) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x5B:
+ /* VCVTPS2DQ xmm2/m128, xmm1 = VEX.128.66.0F.WIG 5B /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_CVTxPS2DQ_128( vbi, pfx, delta,
+ True/*isAvx*/, False/*!r2zero*/ );
+ goto decode_success;
+ }
+ /* VCVTPS2DQ ymm2/m256, ymm1 = VEX.256.66.0F.WIG 5B /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_CVTxPS2DQ_256( vbi, pfx, delta,
+ False/*!r2zero*/ );
+ goto decode_success;
+ }
+ /* VCVTTPS2DQ xmm2/m128, xmm1 = VEX.128.F3.0F.WIG 5B /r */
+ if (haveF3no66noF2(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_CVTxPS2DQ_128( vbi, pfx, delta,
+ True/*isAvx*/, True/*r2zero*/ );
+ goto decode_success;
+ }
+ /* VCVTTPS2DQ ymm2/m256, ymm1 = VEX.256.F3.0F.WIG 5B /r */
+ if (haveF3no66noF2(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_CVTxPS2DQ_256( vbi, pfx, delta,
+ True/*r2zero*/ );
+ goto decode_success;
+ }
+ /* VCVTDQ2PS xmm2/m128, xmm1 = VEX.128.0F.WIG 5B /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_CVTDQ2PS_128 ( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ /* VCVTDQ2PS ymm2/m256, ymm1 = VEX.256.0F.WIG 5B /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_CVTDQ2PS_256 ( vbi, pfx, delta );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5C:
+ /* VSUBSD xmm3/m64, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.WIG 5C /r */
+ if (haveF2no66noF3(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo64(
+ uses_vvvv, vbi, pfx, delta, "vsubsd", Iop_Sub64F0x2 );
+ goto decode_success;
+ }
+ /* VSUBSS xmm3/m32, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.WIG 5C /r */
+ if (haveF3no66noF2(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo32(
+ uses_vvvv, vbi, pfx, delta, "vsubss", Iop_Sub32F0x4 );
+ goto decode_success;
+ }
+ /* VSUBPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5C /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vsubps", Iop_Sub32Fx4 );
+ goto decode_success;
+ }
+ /* VSUBPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5C /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vsubps", Iop_Sub32Fx8 );
+ goto decode_success;
+ }
+ /* VSUBPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 5C /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vsubpd", Iop_Sub64Fx2 );
+ goto decode_success;
+ }
+ /* VSUBPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5C /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vsubpd", Iop_Sub64Fx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5D:
+ /* VMINSD xmm3/m64, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.WIG 5D /r */
+ if (haveF2no66noF3(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo64(
+ uses_vvvv, vbi, pfx, delta, "vminsd", Iop_Min64F0x2 );
+ goto decode_success;
+ }
+ /* VMINSS xmm3/m32, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.WIG 5D /r */
+ if (haveF3no66noF2(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo32(
+ uses_vvvv, vbi, pfx, delta, "vminss", Iop_Min32F0x4 );
+ goto decode_success;
+ }
+ /* VMINPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5D /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vminps", Iop_Min32Fx4 );
+ goto decode_success;
+ }
+ /* VMINPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5D /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vminps", Iop_Min32Fx8 );
+ goto decode_success;
+ }
+ /* VMINPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 5D /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vminpd", Iop_Min64Fx2 );
+ goto decode_success;
+ }
+ /* VMINPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5D /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vminpd", Iop_Min64Fx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5E:
+ /* VDIVSD xmm3/m64, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.WIG 5E /r */
+ if (haveF2no66noF3(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo64(
+ uses_vvvv, vbi, pfx, delta, "vdivsd", Iop_Div64F0x2 );
+ goto decode_success;
+ }
+ /* VDIVSS xmm3/m32, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.WIG 5E /r */
+ if (haveF3no66noF2(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo32(
+ uses_vvvv, vbi, pfx, delta, "vdivss", Iop_Div32F0x4 );
+ goto decode_success;
+ }
+ /* VDIVPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5E /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vdivps", Iop_Div32Fx4 );
+ goto decode_success;
+ }
+ /* VDIVPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5E /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vdivps", Iop_Div32Fx8 );
+ goto decode_success;
+ }
+ /* VDIVPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 5E /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vdivpd", Iop_Div64Fx2 );
+ goto decode_success;
+ }
+ /* VDIVPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5E /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vdivpd", Iop_Div64Fx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x5F:
+ /* VMAXSD xmm3/m64, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.WIG 5F /r */
+ if (haveF2no66noF3(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo64(
+ uses_vvvv, vbi, pfx, delta, "vmaxsd", Iop_Max64F0x2 );
+ goto decode_success;
+ }
+ /* VMAXSS xmm3/m32, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.WIG 5F /r */
+ if (haveF3no66noF2(pfx)) {
+ delta = dis_AVX128_E_V_to_G_lo32(
+ uses_vvvv, vbi, pfx, delta, "vmaxss", Iop_Max32F0x4 );
+ goto decode_success;
+ }
+ /* VMAXPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5F /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vmaxps", Iop_Max32Fx4 );
+ goto decode_success;
+ }
+ /* VMAXPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5F /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vmaxps", Iop_Max32Fx8 );
+ goto decode_success;
+ }
+ /* VMAXPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 5F /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vmaxpd", Iop_Max64Fx2 );
+ goto decode_success;
+ }
+ /* VMAXPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5F /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vmaxpd", Iop_Max64Fx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x60:
+ /* VPUNPCKLBW r/m, rV, r ::: r = interleave-lo-bytes(rV, r/m) */
+ /* VPUNPCKLBW = VEX.NDS.128.66.0F.WIG 60 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpunpcklbw",
+ Iop_InterleaveLO8x16, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x61:
+ /* VPUNPCKLWD r/m, rV, r ::: r = interleave-lo-words(rV, r/m) */
+ /* VPUNPCKLWD = VEX.NDS.128.66.0F.WIG 61 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpunpcklwd",
+ Iop_InterleaveLO16x8, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x62:
+ /* VPUNPCKLDQ r/m, rV, r ::: r = interleave-lo-dwords(rV, r/m) */
+ /* VPUNPCKLDQ = VEX.NDS.128.66.0F.WIG 62 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpunpckldq",
+ Iop_InterleaveLO32x4, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x63:
+ /* VPACKSSWB r/m, rV, r ::: r = QNarrowBin16Sto8Sx16(rV, r/m) */
+ /* VPACKSSWB = VEX.NDS.128.66.0F.WIG 63 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpacksswb",
+ Iop_QNarrowBin16Sto8Sx16, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x64:
+ /* VPCMPGTB r/m, rV, r ::: r = rV `>s-by-8s` r/m */
+ /* VPCMPGTB = VEX.NDS.128.66.0F.WIG 64 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpgtb", Iop_CmpGT8Sx16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x65:
+ /* VPCMPGTW r/m, rV, r ::: r = rV `>s-by-16s` r/m */
+ /* VPCMPGTW = VEX.NDS.128.66.0F.WIG 65 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpgtw", Iop_CmpGT16Sx8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x66:
+ /* VPCMPGTD r/m, rV, r ::: r = rV `>s-by-32s` r/m */
+ /* VPCMPGTD = VEX.NDS.128.66.0F.WIG 66 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpgtd", Iop_CmpGT32Sx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x67:
+ /* VPACKUSWB r/m, rV, r ::: r = QNarrowBin16Sto8Ux16(rV, r/m) */
+ /* VPACKUSWB = VEX.NDS.128.66.0F.WIG 67 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpackuswb",
+ Iop_QNarrowBin16Sto8Ux16, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x68:
+ /* VPUNPCKHBW r/m, rV, r ::: r = interleave-hi-bytes(rV, r/m) */
+ /* VPUNPCKHBW = VEX.NDS.128.0F.WIG 68 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpunpckhbw",
+ Iop_InterleaveHI8x16, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x69:
+ /* VPUNPCKHWD r/m, rV, r ::: r = interleave-hi-words(rV, r/m) */
+ /* VPUNPCKHWD = VEX.NDS.128.0F.WIG 69 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpunpckhwd",
+ Iop_InterleaveHI16x8, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6A:
+ /* VPUNPCKHDQ r/m, rV, r ::: r = interleave-hi-dwords(rV, r/m) */
+ /* VPUNPCKHDQ = VEX.NDS.128.66.0F.WIG 6A /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpunpckhdq",
+ Iop_InterleaveHI32x4, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6B:
+ /* VPACKSSDW r/m, rV, r ::: r = QNarrowBin32Sto16Sx8(rV, r/m) */
+ /* VPACKSSDW = VEX.NDS.128.66.0F.WIG 6B /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpackssdw",
+ Iop_QNarrowBin32Sto16Sx8, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6C:
+ /* VPUNPCKLQDQ r/m, rV, r ::: r = interleave-lo-64bitses(rV, r/m) */
+ /* VPUNPCKLQDQ = VEX.NDS.128.0F.WIG 6C /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpunpcklqdq",
+ Iop_InterleaveLO64x2, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6D:
+ /* VPUNPCKHQDQ r/m, rV, r ::: r = interleave-hi-64bitses(rV, r/m) */
+ /* VPUNPCKHQDQ = VEX.NDS.128.0F.WIG 6D /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpunpckhqdq",
+ Iop_InterleaveHI64x2, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x6E:
+ /* VMOVD r32/m32, xmm1 = VEX.128.66.0F.W0 6E */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ vassert(sz == 2); /* even tho we are transferring 4, not 2. */
+ UChar modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ putYMMRegLoAndZU(
+ gregOfRexRM(pfx,modrm),
+ unop( Iop_32UtoV128, getIReg32(eregOfRexRM(pfx,modrm)) )
+ );
+ DIP("vmovd %s, %s\n", nameIReg32(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ putYMMRegLoAndZU(
+ gregOfRexRM(pfx,modrm),
+ unop( Iop_32UtoV128,loadLE(Ity_I32, mkexpr(addr)))
+ );
+ DIP("vmovd %s, %s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+ goto decode_success;
+ }
+ /* VMOVQ r64/m64, xmm1 = VEX.128.66.0F.W1 6E */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 1==getRexW(pfx)/*W1*/) {
+ vassert(sz == 2); /* even tho we are transferring 8, not 2. */
+ UChar modrm = getUChar(delta);
+ if (epartIsReg(modrm)) {
+ delta += 1;
+ putYMMRegLoAndZU(
+ gregOfRexRM(pfx,modrm),
+ unop( Iop_64UtoV128, getIReg64(eregOfRexRM(pfx,modrm)) )
+ );
+ DIP("vmovq %s, %s\n", nameIReg64(eregOfRexRM(pfx,modrm)),
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ putYMMRegLoAndZU(
+ gregOfRexRM(pfx,modrm),
+ unop( Iop_64UtoV128,loadLE(Ity_I64, mkexpr(addr)))
+ );
+ DIP("vmovq %s, %s\n", dis_buf,
+ nameXMMReg(gregOfRexRM(pfx,modrm)));
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x6F:
+ /* VMOVDQA ymm2/m256, ymm1 = VEX.256.66.0F.WIG 6F */
+ /* VMOVDQU ymm2/m256, ymm1 = VEX.256.F3.0F.WIG 6F */
+ if ((have66noF2noF3(pfx) || haveF3no66noF2(pfx))
+ && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp tD = newTemp(Ity_V256);
+ Bool isA = have66noF2noF3(pfx);
+ UChar ch = isA ? 'a' : 'u';
+ if (epartIsReg(modrm)) {
+ UInt rS = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ assign(tD, getYMMReg(rS));
+ DIP("vmovdq%c %s,%s\n", ch, nameYMMReg(rS), nameYMMReg(rD));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ if (isA)
+ gen_SEGV_if_not_32_aligned(addr);
+ assign(tD, loadLE(Ity_V256, mkexpr(addr)));
+ DIP("vmovdq%c %s,%s\n", ch, dis_buf, nameYMMReg(rD));
+ }
+ putYMMReg(rD, mkexpr(tD));
+ goto decode_success;
+ }
+ /* VMOVDQA xmm2/m128, xmm1 = VEX.128.66.0F.WIG 6F */
+ /* VMOVDQU xmm2/m128, xmm1 = VEX.128.F3.0F.WIG 6F */
+ if ((have66noF2noF3(pfx) || haveF3no66noF2(pfx))
+ && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp tD = newTemp(Ity_V128);
+ Bool isA = have66noF2noF3(pfx);
+ UChar ch = isA ? 'a' : 'u';
+ if (epartIsReg(modrm)) {
+ UInt rS = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ assign(tD, getXMMReg(rS));
+ DIP("vmovdq%c %s,%s\n", ch, nameXMMReg(rS), nameXMMReg(rD));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ if (isA)
+ gen_SEGV_if_not_16_aligned(addr);
+ assign(tD, loadLE(Ity_V128, mkexpr(addr)));
+ DIP("vmovdq%c %s,%s\n", ch, dis_buf, nameXMMReg(rD));
+ }
+ putYMMRegLoAndZU(rD, mkexpr(tD));
+ goto decode_success;
+ }
+ break;
+
+ case 0x70:
+ /* VPSHUFD imm8, xmm2/m128, xmm1 = VEX.128.66.0F.WIG 70 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PSHUFD_32x4( vbi, pfx, delta, True/*writesYmm*/);
+ goto decode_success;
+ }
+ /* VPSHUFLW imm8, xmm2/m128, xmm1 = VEX.128.F2.0F.WIG 70 /r ib */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PSHUFxW_128( vbi, pfx, delta,
+ True/*isAvx*/, False/*!xIsH*/ );
+ goto decode_success;
+ }
+ /* VPSHUFHW imm8, xmm2/m128, xmm1 = VEX.128.F3.0F.WIG 70 /r ib */
+ if (haveF3no66noF2(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PSHUFxW_128( vbi, pfx, delta,
+ True/*isAvx*/, True/*xIsH*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x71:
+ /* VPSRLW imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 71 /2 ib */
+ /* VPSRAW imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 71 /4 ib */
+ /* VPSLLW imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 71 /6 ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/
+ && epartIsReg(getUChar(delta))) {
+ if (gregLO3ofRM(getUChar(delta)) == 2/*SRL*/) {
+ delta = dis_AVX128_shiftE_to_V_imm( pfx, delta,
+ "vpsrlw", Iop_ShrN16x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 4/*SRA*/) {
+ delta = dis_AVX128_shiftE_to_V_imm( pfx, delta,
+ "vpsraw", Iop_SarN16x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 6/*SLL*/) {
+ delta = dis_AVX128_shiftE_to_V_imm( pfx, delta,
+ "vpsllw", Iop_ShlN16x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ break;
+
+ case 0x72:
+ /* VPSRLD imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 72 /2 ib */
+ /* VPSRAD imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 72 /4 ib */
+ /* VPSLLD imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 72 /6 ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/
+ && epartIsReg(getUChar(delta))) {
+ if (gregLO3ofRM(getUChar(delta)) == 2/*SRL*/) {
+ delta = dis_AVX128_shiftE_to_V_imm( pfx, delta,
+ "vpsrld", Iop_ShrN32x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 4/*SRA*/) {
+ delta = dis_AVX128_shiftE_to_V_imm( pfx, delta,
+ "vpsrad", Iop_SarN32x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 6/*SLL*/) {
+ delta = dis_AVX128_shiftE_to_V_imm( pfx, delta,
+ "vpslld", Iop_ShlN32x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ break;
+
+ case 0x73:
+ /* VPSRLDQ imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 73 /3 ib */
+ /* VPSLLDQ imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 73 /7 ib */
+ /* VPSRLQ imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 73 /2 ib */
+ /* VPSLLQ imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 73 /6 ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && epartIsReg(getUChar(delta))) {
+ Int rS = eregOfRexRM(pfx,getUChar(delta));
+ Int rD = getVexNvvvv(pfx);
+ IRTemp vecS = newTemp(Ity_V128);
+ if (gregLO3ofRM(getUChar(delta)) == 3) {
+ Int imm = (Int)getUChar(delta+1);
+ DIP("vpsrldq $%d,%s,%s\n", imm, nameXMMReg(rS), nameXMMReg(rD));
+ delta += 2;
+ assign( vecS, getXMMReg(rS) );
+ putYMMRegLoAndZU(rD, mkexpr(math_PSRLDQ( vecS, imm )));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 7) {
+ Int imm = (Int)getUChar(delta+1);
+ DIP("vpslldq $%d,%s,%s\n", imm, nameXMMReg(rS), nameXMMReg(rD));
+ delta += 2;
+ assign( vecS, getXMMReg(rS) );
+ putYMMRegLoAndZU(rD, mkexpr(math_PSLLDQ( vecS, imm )));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 2) {
+ delta = dis_AVX128_shiftE_to_V_imm( pfx, delta,
+ "vpsrlq", Iop_ShrN64x2 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ if (gregLO3ofRM(getUChar(delta)) == 6) {
+ delta = dis_AVX128_shiftE_to_V_imm( pfx, delta,
+ "vpsllq", Iop_ShlN64x2 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ break;
+
+ case 0x74:
+ /* VPCMPEQB r/m, rV, r ::: r = rV `eq-by-8s` r/m */
+ /* VPCMPEQB = VEX.NDS.128.66.0F.WIG 74 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpeqb", Iop_CmpEQ8x16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x75:
+ /* VPCMPEQW r/m, rV, r ::: r = rV `eq-by-16s` r/m */
+ /* VPCMPEQW = VEX.NDS.128.66.0F.WIG 75 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpeqw", Iop_CmpEQ16x8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x76:
+ /* VPCMPEQD r/m, rV, r ::: r = rV `eq-by-32s` r/m */
+ /* VPCMPEQD = VEX.NDS.128.66.0F.WIG 76 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpeqd", Iop_CmpEQ32x4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x77:
+ /* VZEROUPPER = VEX.128.0F.WIG 77 */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ Int i;
+ IRTemp zero128 = newTemp(Ity_V128);
+ assign(zero128, mkV128(0));
+ for (i = 0; i < 16; i++) {
+ putYMMRegLane128(i, 1, mkexpr(zero128));
+ }
+ DIP("vzeroupper\n");
+ goto decode_success;
+ }
+ /* VZEROALL = VEX.256.0F.WIG 77 */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ Int i;
+ IRTemp zero128 = newTemp(Ity_V128);
+ assign(zero128, mkV128(0));
+ for (i = 0; i < 16; i++) {
+ putYMMRegLoAndZU(i, mkexpr(zero128));
+ }
+ DIP("vzeroall\n");
+ goto decode_success;
+ }
+ break;
+
+ case 0x7C:
+ case 0x7D:
+ /* VHADDPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.F2.0F.WIG 7C /r */
+ /* VHSUBPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.F2.0F.WIG 7D /r */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ Bool isAdd = opc == 0x7C;
+ HChar* str = isAdd ? "add" : "sub";
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ DIP("vh%spd %s,%s,%s\n", str, nameXMMReg(rE),
+ nameXMMReg(rV), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("vh%spd %s,%s,%s\n", str, dis_buf,
+ nameXMMReg(rV), nameXMMReg(rG));
+ delta += alen;
+ }
+ assign( dV, getXMMReg(rV) );
+ putYMMRegLoAndZU( rG, mkexpr( math_HADDPS_128 ( dV, sV, isAdd ) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VHADDPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.F2.0F.WIG 7C /r */
+ /* VHSUBPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.F2.0F.WIG 7D /r */
+ if (haveF2no66noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp dV = newTemp(Ity_V256);
+ IRTemp s1, s0, d1, d0;
+ Bool isAdd = opc == 0x7C;
+ HChar* str = isAdd ? "add" : "sub";
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ s1 = s0 = d1 = d0 = IRTemp_INVALID;
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getYMMReg(rE) );
+ DIP("vh%spd %s,%s,%s\n", str, nameYMMReg(rE),
+ nameYMMReg(rV), nameYMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
+ DIP("vh%spd %s,%s,%s\n", str, dis_buf,
+ nameYMMReg(rV), nameYMMReg(rG));
+ delta += alen;
+ }
+ assign( dV, getYMMReg(rV) );
+ breakupV256toV128s( dV, &d1, &d0 );
+ breakupV256toV128s( sV, &s1, &s0 );
+ putYMMReg( rG, binop(Iop_V128HLtoV256,
+ mkexpr( math_HADDPS_128 ( d1, s1, isAdd ) ),
+ mkexpr( math_HADDPS_128 ( d0, s0, isAdd ) ) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VHADDPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 7C /r */
+ /* VHSUBPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 7D /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ Bool isAdd = opc == 0x7C;
+ HChar* str = isAdd ? "add" : "sub";
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ DIP("vh%spd %s,%s,%s\n", str, nameXMMReg(rE),
+ nameXMMReg(rV), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ DIP("vh%spd %s,%s,%s\n", str, dis_buf,
+ nameXMMReg(rV), nameXMMReg(rG));
+ delta += alen;
+ }
+ assign( dV, getXMMReg(rV) );
+ putYMMRegLoAndZU( rG, mkexpr( math_HADDPD_128 ( dV, sV, isAdd ) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VHADDPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 7C /r */
+ /* VHSUBPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 7D /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp dV = newTemp(Ity_V256);
+ IRTemp s1, s0, d1, d0;
+ Bool isAdd = opc == 0x7C;
+ HChar* str = isAdd ? "add" : "sub";
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ s1 = s0 = d1 = d0 = IRTemp_INVALID;
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getYMMReg(rE) );
+ DIP("vh%spd %s,%s,%s\n", str, nameYMMReg(rE),
+ nameYMMReg(rV), nameYMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
+ DIP("vh%spd %s,%s,%s\n", str, dis_buf,
+ nameYMMReg(rV), nameYMMReg(rG));
+ delta += alen;
+ }
+ assign( dV, getYMMReg(rV) );
+ breakupV256toV128s( dV, &d1, &d0 );
+ breakupV256toV128s( sV, &s1, &s0 );
+ putYMMReg( rG, binop(Iop_V128HLtoV256,
+ mkexpr( math_HADDPD_128 ( d1, s1, isAdd ) ),
+ mkexpr( math_HADDPD_128 ( d0, s0, isAdd ) ) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x7E:
+ /* Note the Intel docs don't make sense for this. I think they
+ are wrong. They seem to imply it is a store when in fact I
+ think it is a load. Also it's unclear whether this is W0, W1
+ or WIG. */
+ /* VMOVQ xmm2/m64, xmm1 = VEX.128.F3.0F.W0 7E /r */
+ if (haveF3no66noF2(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ vassert(sz == 4); /* even tho we are transferring 8, not 4. */
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ putXMMRegLane64( rG, 0, getXMMRegLane64( rE, 0 ));
+ DIP("vmovq %s,%s\n", nameXMMReg(rE), nameXMMReg(rG));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ putXMMRegLane64( rG, 0, loadLE(Ity_I64, mkexpr(addr)) );
+ DIP("vmovq %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+ /* zero bits 255:64 */
+ putXMMRegLane64( rG, 1, mkU64(0) );
+ putYMMRegLane128( rG, 1, mkV128(0) );
+ goto decode_success;
+ }
+ /* VMOVQ xmm1, r64 = VEX.128.66.0F.W1 7E /r (reg case only) */
+ /* Moves from G to E, so is a store-form insn */
+ /* Intel docs list this in the VMOVD entry for some reason. */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 1==getRexW(pfx)/*W1*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ DIP("vmovq %s,%s\n", nameXMMReg(rG), nameIReg64(rE));
+ putIReg64(rE, getXMMRegLane64(rG, 0));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getXMMRegLane64(rG, 0) );
+ DIP("vmovq %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ /* VMOVD xmm1, m32/r32 = VEX.128.66.0F.W0 7E /r (reg case only) */
+ /* Moves from G to E, so is a store-form insn */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ DIP("vmovd %s,%s\n", nameXMMReg(rG), nameIReg32(rE));
+ putIReg32(rE, getXMMRegLane32(rG, 0));
+ delta += 1;
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getXMMRegLane32(rG, 0) );
+ DIP("vmovd %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0x7F:
+ /* VMOVDQA ymm1, ymm2/m256 = VEX.256.66.0F.WIG 7F */
+ /* VMOVDQU ymm1, ymm2/m256 = VEX.256.F3.0F.WIG 7F */
+ if ((have66noF2noF3(pfx) || haveF3no66noF2(pfx))
+ && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rS = gregOfRexRM(pfx, modrm);
+ IRTemp tS = newTemp(Ity_V256);
+ Bool isA = have66noF2noF3(pfx);
+ UChar ch = isA ? 'a' : 'u';
+ assign(tS, getYMMReg(rS));
+ if (epartIsReg(modrm)) {
+ UInt rD = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ putYMMReg(rD, mkexpr(tS));
+ DIP("vmovdq%c %s,%s\n", ch, nameYMMReg(rS), nameYMMReg(rD));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ if (isA)
+ gen_SEGV_if_not_32_aligned(addr);
+ storeLE(mkexpr(addr), mkexpr(tS));
+ DIP("vmovdq%c %s,%s\n", ch, nameYMMReg(rS), dis_buf);
+ }
+ goto decode_success;
+ }
+ /* VMOVDQA xmm1, xmm2/m128 = VEX.128.66.0F.WIG 7F */
+ /* VMOVDQU xmm1, xmm2/m128 = VEX.128.F3.0F.WIG 7F */
+ if ((have66noF2noF3(pfx) || haveF3no66noF2(pfx))
+ && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rS = gregOfRexRM(pfx, modrm);
+ IRTemp tS = newTemp(Ity_V128);
+ Bool isA = have66noF2noF3(pfx);
+ UChar ch = isA ? 'a' : 'u';
+ assign(tS, getXMMReg(rS));
+ if (epartIsReg(modrm)) {
+ UInt rD = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ putYMMRegLoAndZU(rD, mkexpr(tS));
+ DIP("vmovdq%c %s,%s\n", ch, nameXMMReg(rS), nameXMMReg(rD));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ if (isA)
+ gen_SEGV_if_not_16_aligned(addr);
+ storeLE(mkexpr(addr), mkexpr(tS));
+ DIP("vmovdq%c %s,%s\n", ch, nameXMMReg(rS), dis_buf);
+ }
+ goto decode_success;
+ }
+ break;
+
+ case 0xAE:
+ /* VSTMXCSR m32 = VEX.LZ.0F.WIG AE /3 */
+ if (haveNo66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*LZ*/
+ && 0==getRexW(pfx) /* be paranoid -- Intel docs don't require this */
+ && !epartIsReg(getUChar(delta)) && gregLO3ofRM(getUChar(delta)) == 3
+ && sz == 4) {
+ delta = dis_STMXCSR(vbi, pfx, delta, True/*isAvx*/);
+ goto decode_success;
+ }
+ /* VLDMXCSR m32 = VEX.LZ.0F.WIG AE /2 */
+ if (haveNo66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*LZ*/
+ && 0==getRexW(pfx) /* be paranoid -- Intel docs don't require this */
+ && !epartIsReg(getUChar(delta)) && gregLO3ofRM(getUChar(delta)) == 2
+ && sz == 4) {
+ delta = dis_LDMXCSR(vbi, pfx, delta, True/*isAvx*/);
+ goto decode_success;
+ }
+ break;
+
+ case 0xC2:
+ /* VCMPSD xmm3/m64(E=argL), xmm2(V=argR), xmm1(G) */
+ /* = VEX.NDS.LIG.F2.0F.WIG C2 /r ib */
+ if (haveF2no66noF3(pfx)) {
+ Long delta0 = delta;
+ delta = dis_AVX128_cmp_V_E_to_G( uses_vvvv, vbi, pfx, delta,
+ "vcmpsd", False/*!all_lanes*/,
+ 8/*sz*/);
+ if (delta > delta0) goto decode_success;
+ /* else fall through -- decoding has failed */
+ }
+ /* VCMPSS xmm3/m32(E=argL), xmm2(V=argR), xmm1(G) */
+ /* = VEX.NDS.LIG.F3.0F.WIG C2 /r ib */
+ if (haveF3no66noF2(pfx)) {
+ Long delta0 = delta;
+ delta = dis_AVX128_cmp_V_E_to_G( uses_vvvv, vbi, pfx, delta,
+ "vcmpss", False/*!all_lanes*/,
+ 4/*sz*/);
+ if (delta > delta0) goto decode_success;
+ /* else fall through -- decoding has failed */
+ }
+ /* VCMPPD xmm3/m128(E=argL), xmm2(V=argR), xmm1(G) */
+ /* = VEX.NDS.128.66.0F.WIG C2 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ Long delta0 = delta;
+ delta = dis_AVX128_cmp_V_E_to_G( uses_vvvv, vbi, pfx, delta,
+ "vcmppd", True/*all_lanes*/,
+ 8/*sz*/);
+ if (delta > delta0) goto decode_success;
+ /* else fall through -- decoding has failed */
+ }
+ /* VCMPPD ymm3/m256(E=argL), ymm2(V=argR), ymm1(G) */
+ /* = VEX.NDS.256.66.0F.WIG C2 /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ Long delta0 = delta;
+ delta = dis_AVX256_cmp_V_E_to_G( uses_vvvv, vbi, pfx, delta,
+ "vcmppd", 8/*sz*/);
+ if (delta > delta0) goto decode_success;
+ /* else fall through -- decoding has failed */
+ }
+ /* VCMPPS xmm3/m128(E=argL), xmm2(V=argR), xmm1(G) */
+ /* = VEX.NDS.128.0F.WIG C2 /r ib */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ Long delta0 = delta;
+ delta = dis_AVX128_cmp_V_E_to_G( uses_vvvv, vbi, pfx, delta,
+ "vcmpps", True/*all_lanes*/,
+ 4/*sz*/);
+ if (delta > delta0) goto decode_success;
+ /* else fall through -- decoding has failed */
+ }
+ /* VCMPPS ymm3/m256(E=argL), ymm2(V=argR), ymm1(G) */
+ /* = VEX.NDS.256.0F.WIG C2 /r ib */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ Long delta0 = delta;
+ delta = dis_AVX256_cmp_V_E_to_G( uses_vvvv, vbi, pfx, delta,
+ "vcmpps", 4/*sz*/);
+ if (delta > delta0) goto decode_success;
+ /* else fall through -- decoding has failed */
+ }
+ break;
+
+ case 0xC4:
+ /* VPINSRW r32/m16, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG C4 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ Int imm8;
+ IRTemp new16 = newTemp(Ity_I16);
+
+ if ( epartIsReg( modrm ) ) {
+ imm8 = (Int)(getUChar(delta+1) & 7);
+ assign( new16, unop(Iop_32to16,
+ getIReg32(eregOfRexRM(pfx,modrm))) );
+ delta += 1+1;
+ DIP( "vpinsrw $%d,%s,%s\n", imm8,
+ nameIReg32( eregOfRexRM(pfx, modrm) ), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8 = (Int)(getUChar(delta+alen) & 7);
+ assign( new16, loadLE( Ity_I16, mkexpr(addr) ));
+ delta += alen+1;
+ DIP( "vpinsrw $%d,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rG) );
}
- IRDirty* d = unsafeIRDirty_0_N (
- 0/*regparms*/,
- "amd64g_dirtyhelper_SxDT",
- &amd64g_dirtyhelper_SxDT,
- mkIRExprVec_2( mkexpr(addr),
- mkU64(gregLO3ofRM(modrm)) )
- );
- /* declare we're writing memory */
- d->mFx = Ifx_Write;
- d->mAddr = mkexpr(addr);
- d->mSize = 6;
- stmt( IRStmt_Dirty(d) );
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg( rV ));
+ IRTemp res_vec = math_PINSRW_128( src_vec, new16, imm8 );
+ putYMMRegLoAndZU( rG, mkexpr(res_vec) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xC5:
+ /* VPEXTRW imm8, xmm1, reg32 = VEX.128.66.0F.W0 C5 /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ Long delta0 = delta;
+ delta = dis_PEXTRW_128_EregOnly_toG( vbi, pfx, delta,
+ True/*isAvx*/ );
+ if (delta > delta0) goto decode_success;
+ /* else fall through -- decoding has failed */
+ }
+ break;
+
+ case 0xC6:
+ /* VSHUFPS imm8, xmm3/m128, xmm2, xmm1, xmm2 */
+ /* = VEX.NDS.128.0F.WIG C6 /r ib */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ Int imm8 = 0;
+ IRTemp eV = newTemp(Ity_V128);
+ IRTemp vV = newTemp(Ity_V128);
+ UInt modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ assign( vV, getXMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getXMMReg(rE) );
+ imm8 = (Int)getUChar(delta+1);
+ delta += 1+1;
+ DIP("vshufps $%d,%s,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += 1+alen;
+ DIP("vshufps $%d,%s,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ }
+ IRTemp res = math_SHUFPS_128( eV, vV, imm8 );
+ putYMMRegLoAndZU( rG, mkexpr(res) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VSHUFPS imm8, ymm3/m256, ymm2, ymm1, ymm2 */
+ /* = VEX.NDS.256.0F.WIG C6 /r ib */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ Int imm8 = 0;
+ IRTemp eV = newTemp(Ity_V256);
+ IRTemp vV = newTemp(Ity_V256);
+ UInt modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ assign( vV, getYMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getYMMReg(rE) );
+ imm8 = (Int)getUChar(delta+1);
+ delta += 1+1;
+ DIP("vshufps $%d,%s,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( eV, loadLE(Ity_V256, mkexpr(addr)) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += 1+alen;
+ DIP("vshufps $%d,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ }
+ IRTemp res = math_SHUFPS_256( eV, vV, imm8 );
+ putYMMReg( rG, mkexpr(res) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VSHUFPD imm8, xmm3/m128, xmm2, xmm1, xmm2 */
+ /* = VEX.NDS.128.66.0F.WIG C6 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ Int imm8 = 0;
+ IRTemp eV = newTemp(Ity_V128);
+ IRTemp vV = newTemp(Ity_V128);
+ UInt modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ assign( vV, getXMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getXMMReg(rE) );
+ imm8 = (Int)getUChar(delta+1);
+ delta += 1+1;
+ DIP("vshufpd $%d,%s,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( eV, loadLE(Ity_V128, mkexpr(addr)) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += 1+alen;
+ DIP("vshufpd $%d,%s,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ }
+ IRTemp res = math_SHUFPD_128( eV, vV, imm8 );
+ putYMMRegLoAndZU( rG, mkexpr(res) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VSHUFPD imm8, ymm3/m256, ymm2, ymm1, ymm2 */
+ /* = VEX.NDS.256.66.0F.WIG C6 /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ Int imm8 = 0;
+ IRTemp eV = newTemp(Ity_V256);
+ IRTemp vV = newTemp(Ity_V256);
+ UInt modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+ assign( vV, getYMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( eV, getYMMReg(rE) );
+ imm8 = (Int)getUChar(delta+1);
+ delta += 1+1;
+ DIP("vshufpd $%d,%s,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( eV, loadLE(Ity_V256, mkexpr(addr)) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += 1+alen;
+ DIP("vshufpd $%d,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ }
+ IRTemp res = math_SHUFPD_256( eV, vV, imm8 );
+ putYMMReg( rG, mkexpr(res) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xD0:
+ /* VADDSUBPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D0 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vaddsubpd", math_ADDSUBPD_128 );
+ goto decode_success;
+ }
+ /* VADDSUBPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG D0 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vaddsubpd", math_ADDSUBPD_256 );
+ goto decode_success;
+ }
+ /* VADDSUBPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.F2.0F.WIG D0 /r */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vaddsubps", math_ADDSUBPS_128 );
+ goto decode_success;
+ }
+ /* VADDSUBPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.F2.0F.WIG D0 /r */
+ if (haveF2no66noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vaddsubps", math_ADDSUBPS_256 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD1:
+ /* VPSRLW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D1 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_shiftV_byE( vbi, pfx, delta,
+ "vpsrlw", Iop_ShrN16x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+
+ }
+ break;
+
+ case 0xD2:
+ /* VPSRLD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D2 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_shiftV_byE( vbi, pfx, delta,
+ "vpsrld", Iop_ShrN32x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xD3:
+ /* VPSRLQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D3 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_shiftV_byE( vbi, pfx, delta,
+ "vpsrlq", Iop_ShrN64x2 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xD4:
+ /* VPADDQ r/m, rV, r ::: r = rV + r/m */
+ /* VPADDQ = VEX.NDS.128.66.0F.WIG D4 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpaddq", Iop_Add64x2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD5:
+ /* VPMULLW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D5 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpmullw", Iop_Mul16x8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD6:
+ /* I can't even find any Intel docs for this one. */
+ /* Basically: 66 0F D6 = MOVQ -- move 64 bits from G (lo half
+ xmm) to E (mem or lo half xmm). Looks like L==0(128), W==0
+ (WIG, maybe?) */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && 0==getRexW(pfx)/*this might be redundant, dunno*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (epartIsReg(modrm)) {
+ /* fall through, awaiting test case */
+ /* dst: lo half copied, hi half zeroed */
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ storeLE( mkexpr(addr), getXMMRegLane64( rG, 0 ));
+ DIP("vmovq %s,%s\n", nameXMMReg(rG), dis_buf );
+ delta += alen;
+ goto decode_success;
+ }
+ }
+ break;
+
+ case 0xD7:
+ /* VEX.128.66.0F.WIG D7 /r = VPMOVMSKB xmm1, r32 */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVMSKB_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD8:
+ /* VPSUBUSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D8 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpsubusb", Iop_QSub8Ux16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xD9:
+ /* VPSUBUSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D9 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpsubusw", Iop_QSub16Ux8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDA:
+ /* VPMINUB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DA /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpminub", Iop_Min8Ux16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDB:
+ /* VPAND r/m, rV, r ::: r = rV & r/m */
+ /* VEX.NDS.128.66.0F.WIG DB /r = VPAND xmm3/m128, xmm2, xmm1 */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpand", Iop_AndV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDC:
+ /* VPADDUSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DC /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpaddusb", Iop_QAdd8Ux16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDD:
+ /* VPADDUSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DD /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpaddusw", Iop_QAdd16Ux8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDE:
+ /* VPMAXUB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DE /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpmaxub", Iop_Max8Ux16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDF:
+ /* VPANDN r/m, rV, r ::: r = rV & ~r/m (is that correct, re the ~ ?) */
+ /* VEX.NDS.128.66.0F.WIG DF /r = VPANDN xmm3/m128, xmm2, xmm1 */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpandn", Iop_AndV128,
+ NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE0:
+ /* VPAVGB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E0 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpavgb", Iop_Avg8Ux16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE1:
+ /* VPSRAW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E1 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_shiftV_byE( vbi, pfx, delta,
+ "vpsraw", Iop_SarN16x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xE2:
+ /* VPSRAD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E2 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_shiftV_byE( vbi, pfx, delta,
+ "vpsrad", Iop_SarN32x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xE3:
+ /* VPAVGW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E3 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpavgw", Iop_Avg16Ux8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE4:
+ /* VPMULHUW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E4 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpmulhuw", Iop_MulHi16Ux8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE5:
+ /* VPMULHW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E5 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpmulhw", Iop_MulHi16Sx8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE6:
+ /* VCVTDQ2PD xmm2/m64, xmm1 = VEX.128.F3.0F.WIG E6 /r */
+ if (haveF3no66noF2(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_CVTDQ2PD_128(vbi, pfx, delta, True/*isAvx*/);
+ goto decode_success;
+ }
+ /* VCVTDQ2PD xmm2/m128, ymm1 = VEX.256.F3.0F.WIG E6 /r */
+ if (haveF3no66noF2(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_CVTDQ2PD_256(vbi, pfx, delta);
+ goto decode_success;
+ }
+ /* VCVTTPD2DQ xmm2/m128, xmm1 = VEX.128.66.0F.WIG E6 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_CVTxPD2DQ_128(vbi, pfx, delta, True/*isAvx*/,
+ True/*r2zero*/);
+ goto decode_success;
+ }
+ /* VCVTTPD2DQ ymm2/m256, xmm1 = VEX.256.66.0F.WIG E6 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_CVTxPD2DQ_256(vbi, pfx, delta, True/*r2zero*/);
+ goto decode_success;
+ }
+ /* VCVTPD2DQ xmm2/m128, xmm1 = VEX.128.F2.0F.WIG E6 /r */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_CVTxPD2DQ_128(vbi, pfx, delta, True/*isAvx*/,
+ False/*!r2zero*/);
+ goto decode_success;
+ }
+ /* VCVTPD2DQ ymm2/m256, xmm1 = VEX.256.F2.0F.WIG E6 /r */
+ if (haveF2no66noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_CVTxPD2DQ_256(vbi, pfx, delta, False/*!r2zero*/);
+ goto decode_success;
+ }
+ break;
+
+ case 0xE7:
+ /* VMOVNTDQ xmm1, m128 = VEX.128.66.0F.WIG E7 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (!epartIsReg(modrm)) {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_16_aligned( addr );
+ storeLE( mkexpr(addr), getXMMReg(rG) );
+ DIP("vmovntdq %s,%s\n", dis_buf, nameXMMReg(rG));
+ delta += alen;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ /* VMOVNTDQ ymm1, m256 = VEX.256.66.0F.WIG E7 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ if (!epartIsReg(modrm)) {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ gen_SEGV_if_not_32_aligned( addr );
+ storeLE( mkexpr(addr), getYMMReg(rG) );
+ DIP("vmovntdq %s,%s\n", dis_buf, nameYMMReg(rG));
+ delta += alen;
+ goto decode_success;
+ }
+ /* else fall through */
+ }
+ break;
+
+ case 0xE8:
+ /* VPSUBSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E8 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpsubsb", Iop_QSub8Sx16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xE9:
+ /* VPSUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E9 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpsubsw", Iop_QSub16Sx8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEA:
+ /* VPMINSW r/m, rV, r ::: r = min-signed16s(rV, r/m) */
+ /* VPMINSW = VEX.NDS.128.66.0F.WIG EA /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminsw", Iop_Min16Sx8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEB:
+ /* VPOR r/m, rV, r ::: r = rV | r/m */
+ /* VPOR = VEX.NDS.128.66.0F.WIG EB /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpor", Iop_OrV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEC:
+ /* VPADDSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG EC /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpaddsb", Iop_QAdd8Sx16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xED:
+ /* VPADDSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG ED /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vpaddsw", Iop_QAdd16Sx8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEE:
+ /* VPMAXSW r/m, rV, r ::: r = max-signed16s(rV, r/m) */
+ /* VPMAXSW = VEX.NDS.128.66.0F.WIG EE /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxsw", Iop_Max16Sx8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xEF:
+ /* VPXOR r/m, rV, r ::: r = rV ^ r/m */
+ /* VPXOR = VEX.NDS.128.66.0F.WIG EF /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpxor", Iop_XorV128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF0:
+ /* VLDDQU m256, ymm1 = VEX.256.F2.0F.WIG F0 /r */
+ if (haveF2no66noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp tD = newTemp(Ity_V256);
+ if (epartIsReg(modrm)) break;
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ assign(tD, loadLE(Ity_V256, mkexpr(addr)));
+ DIP("vlddqu %s,%s\n", dis_buf, nameYMMReg(rD));
+ putYMMReg(rD, mkexpr(tD));
+ goto decode_success;
+ }
+ /* VLDDQU m128, xmm1 = VEX.128.F2.0F.WIG F0 /r */
+ if (haveF2no66noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp tD = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) break;
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ assign(tD, loadLE(Ity_V128, mkexpr(addr)));
+ DIP("vlddqu %s,%s\n", dis_buf, nameXMMReg(rD));
+ putYMMRegLoAndZU(rD, mkexpr(tD));
+ goto decode_success;
+ }
+ break;
+
+ case 0xF1:
+ /* VPSLLW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F1 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_shiftV_byE( vbi, pfx, delta,
+ "vpsllw", Iop_ShlN16x8 );
+ *uses_vvvv = True;
+ goto decode_success;
+
+ }
+ break;
+
+ case 0xF2:
+ /* VPSLLD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F2 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_shiftV_byE( vbi, pfx, delta,
+ "vpslld", Iop_ShlN32x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xF3:
+ /* VPSLLQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F3 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_shiftV_byE( vbi, pfx, delta,
+ "vpsllq", Iop_ShlN64x2 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0xF4:
+ /* VPMULUDQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F4 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vpmuludq", math_PMULUDQ_128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF5:
+ /* VPMADDWD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F5 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vpmaddwd", math_PMADDWD_128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF6:
+ /* VPSADBW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F6 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vpsadbw", math_PSADBW_128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF7:
+ /* VMASKMOVDQU xmm2, xmm1 = VEX.128.66.0F.WIG F7 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && epartIsReg(getUChar(delta))) {
+ delta = dis_MASKMOVDQU( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF8:
+ /* VPSUBB r/m, rV, r ::: r = rV - r/m */
+ /* VPSUBB = VEX.NDS.128.66.0F.WIG F8 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpsubb", Iop_Sub8x16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xF9:
+ /* VPSUBW r/m, rV, r ::: r = rV - r/m */
+ /* VPSUBW = VEX.NDS.128.66.0F.WIG F9 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpsubw", Iop_Sub16x8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFA:
+ /* VPSUBD r/m, rV, r ::: r = rV - r/m */
+ /* VPSUBD = VEX.NDS.128.66.0F.WIG FA /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpsubd", Iop_Sub32x4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFB:
+ /* VPSUBQ r/m, rV, r ::: r = rV - r/m */
+ /* VPSUBQ = VEX.NDS.128.66.0F.WIG FB /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpsubq", Iop_Sub64x2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFC:
+ /* VPADDB r/m, rV, r ::: r = rV + r/m */
+ /* VPADDB = VEX.NDS.128.66.0F.WIG FC /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpaddb", Iop_Add8x16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFD:
+ /* VPADDW r/m, rV, r ::: r = rV + r/m */
+ /* VPADDW = VEX.NDS.128.66.0F.WIG FD /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpaddw", Iop_Add16x8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0xFE:
+ /* VPADDD r/m, rV, r ::: r = rV + r/m */
+ /* VPADDD = VEX.NDS.128.66.0F.WIG FE /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpaddd", Iop_Add32x4 );
+ goto decode_success;
+ }
+ break;
+
+ default:
+ break;
+
+ }
+
+ //decode_failure:
+ return deltaIN;
+
+ decode_success:
+ return delta;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level post-escape decoders: dis_ESC_0F38__VEX ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+static IRTemp math_PERMILPS_VAR_128 ( IRTemp dataV, IRTemp ctrlV )
+{
+ /* In the control vector, zero out all but the bottom two bits of
+ each 32-bit lane. */
+ IRExpr* cv1 = binop(Iop_ShrN32x4,
+ binop(Iop_ShlN32x4, mkexpr(ctrlV), mkU8(30)),
+ mkU8(30));
+ /* And use the resulting cleaned-up control vector as steering
+ in a Perm operation. */
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_Perm32x4, mkexpr(dataV), cv1));
+ return res;
+}
+
+static IRTemp math_PERMILPS_VAR_256 ( IRTemp dataV, IRTemp ctrlV )
+{
+ IRTemp dHi, dLo, cHi, cLo;
+ dHi = dLo = cHi = cLo = IRTemp_INVALID;
+ breakupV256toV128s( dataV, &dHi, &dLo );
+ breakupV256toV128s( ctrlV, &cHi, &cLo );
+ IRTemp rHi = math_PERMILPS_VAR_128( dHi, cHi );
+ IRTemp rLo = math_PERMILPS_VAR_128( dLo, cLo );
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_V128HLtoV256, mkexpr(rHi), mkexpr(rLo)));
+ return res;
+}
+
+static IRTemp math_PERMILPD_VAR_128 ( IRTemp dataV, IRTemp ctrlV )
+{
+ /* No cleverness here .. */
+ IRTemp dHi, dLo, cHi, cLo;
+ dHi = dLo = cHi = cLo = IRTemp_INVALID;
+ breakupV128to64s( dataV, &dHi, &dLo );
+ breakupV128to64s( ctrlV, &cHi, &cLo );
+ IRExpr* rHi
+ = IRExpr_Mux0X( unop(Iop_64to8,
+ binop(Iop_And64, mkexpr(cHi), mkU64(2))),
+ mkexpr(dLo), mkexpr(dHi) );
+ IRExpr* rLo
+ = IRExpr_Mux0X( unop(Iop_64to8,
+ binop(Iop_And64, mkexpr(cLo), mkU64(2))),
+ mkexpr(dLo), mkexpr(dHi) );
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, binop(Iop_64HLtoV128, rHi, rLo));
+ return res;
+}
+
+static IRTemp math_PERMILPD_VAR_256 ( IRTemp dataV, IRTemp ctrlV )
+{
+ IRTemp dHi, dLo, cHi, cLo;
+ dHi = dLo = cHi = cLo = IRTemp_INVALID;
+ breakupV256toV128s( dataV, &dHi, &dLo );
+ breakupV256toV128s( ctrlV, &cHi, &cLo );
+ IRTemp rHi = math_PERMILPD_VAR_128( dHi, cHi );
+ IRTemp rLo = math_PERMILPD_VAR_128( dLo, cLo );
+ IRTemp res = newTemp(Ity_V256);
+ assign(res, binop(Iop_V128HLtoV256, mkexpr(rHi), mkexpr(rLo)));
+ return res;
+}
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F38__VEX (
+ /*MB_OUT*/DisResult* dres,
+ /*OUT*/ Bool* uses_vvvv,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN
+ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ *uses_vvvv = False;
+
+ switch (opc) {
+
+ case 0x00:
+ /* VPSHUFB r/m, rV, r ::: r = shuf(rV, r/m) */
+ /* VPSHUFB = VEX.NDS.128.66.0F38.WIG 00 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpshufb", math_PSHUFB_XMM );
+ goto decode_success;
+ }
+ break;
+
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ /* VPHADDW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 01 /r */
+ /* VPHADDD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 02 /r */
+ /* VPHADDSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 03 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PHADD_128( vbi, pfx, delta, True/*isAvx*/, opc );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x04:
+ /* VPMADDUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 04 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta, "vpmaddubsw",
+ math_PMADDUBSW_128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x05:
+ case 0x06:
+ case 0x07:
+ /* VPHSUBW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 05 /r */
+ /* VPHSUBD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 06 /r */
+ /* VPHSUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 07 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PHADD_128( vbi, pfx, delta, True/*isAvx*/, opc );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x08:
+ case 0x09:
+ case 0x0A:
+ /* VPSIGNB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 08 /r */
+ /* VPSIGNW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 09 /r */
+ /* VPSIGND xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 0A /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+ UChar ch = '?';
+ Int laneszB = 0;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+
+ switch (opc) {
+ case 0x08: laneszB = 1; ch = 'b'; break;
+ case 0x09: laneszB = 2; ch = 'w'; break;
+ case 0x0A: laneszB = 4; ch = 'd'; break;
+ default: vassert(0);
+ }
+
+ assign( dV, getXMMReg(rV) );
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("vpsign%c %s,%s,%s\n", ch, nameXMMReg(rE),
+ nameXMMReg(rV), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("vpsign%c %s,%s,%s\n", ch, dis_buf,
+ nameXMMReg(rV), nameXMMReg(rG));
+ }
+
+ breakupV128to64s( dV, &dHi, &dLo );
+ breakupV128to64s( sV, &sHi, &sLo );
+
+ putYMMRegLoAndZU(
+ rG,
+ binop(Iop_64HLtoV128,
+ dis_PSIGN_helper( mkexpr(sHi), mkexpr(dHi), laneszB ),
+ dis_PSIGN_helper( mkexpr(sLo), mkexpr(dLo), laneszB )
+ )
+ );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x0B:
+ /* VPMULHRSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 0B /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ IRTemp sHi, sLo, dHi, dLo;
+ sHi = sLo = dHi = dLo = IRTemp_INVALID;
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx,modrm);
+ UInt rV = getVexNvvvv(pfx);
+
+ assign( dV, getXMMReg(rV) );
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ assign( sV, getXMMReg(rE) );
+ delta += 1;
+ DIP("vpmulhrsw %s,%s,%s\n", nameXMMReg(rE),
+ nameXMMReg(rV), nameXMMReg(rG));
+ } else {
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ delta += alen;
+ DIP("vpmulhrsw %s,%s,%s\n", dis_buf,
+ nameXMMReg(rV), nameXMMReg(rG));
+ }
+
+ breakupV128to64s( dV, &dHi, &dLo );
+ breakupV128to64s( sV, &sHi, &sLo );
+
+ putYMMRegLoAndZU(
+ rG,
+ binop(Iop_64HLtoV128,
+ dis_PMULHRSW_helper( mkexpr(sHi), mkexpr(dHi) ),
+ dis_PMULHRSW_helper( mkexpr(sLo), mkexpr(dLo) )
+ )
+ );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x0C:
+ /* VPERMILPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 0C /r */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp ctrlV = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ DIP("vpermilps %s,%s,%s\n",
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ assign(ctrlV, getXMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpermilps %s,%s,%s\n",
+ dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ assign(ctrlV, loadLE(Ity_V128, mkexpr(addr)));
+ }
+ IRTemp dataV = newTemp(Ity_V128);
+ assign(dataV, getXMMReg(rV));
+ IRTemp resV = math_PERMILPS_VAR_128(dataV, ctrlV);
+ putYMMRegLoAndZU(rG, mkexpr(resV));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VPERMILPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 0C /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp ctrlV = newTemp(Ity_V256);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ DIP("vpermilps %s,%s,%s\n",
+ nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ assign(ctrlV, getYMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpermilps %s,%s,%s\n",
+ dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ assign(ctrlV, loadLE(Ity_V256, mkexpr(addr)));
+ }
+ IRTemp dataV = newTemp(Ity_V256);
+ assign(dataV, getYMMReg(rV));
+ IRTemp resV = math_PERMILPS_VAR_256(dataV, ctrlV);
+ putYMMReg(rG, mkexpr(resV));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x0D:
+ /* VPERMILPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 0D /r */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp ctrlV = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ DIP("vpermilpd %s,%s,%s\n",
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ assign(ctrlV, getXMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpermilpd %s,%s,%s\n",
+ dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ assign(ctrlV, loadLE(Ity_V128, mkexpr(addr)));
+ }
+ IRTemp dataV = newTemp(Ity_V128);
+ assign(dataV, getXMMReg(rV));
+ IRTemp resV = math_PERMILPD_VAR_128(dataV, ctrlV);
+ putYMMRegLoAndZU(rG, mkexpr(resV));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VPERMILPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 0D /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp ctrlV = newTemp(Ity_V256);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ DIP("vpermilpd %s,%s,%s\n",
+ nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ assign(ctrlV, getYMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vpermilpd %s,%s,%s\n",
+ dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ assign(ctrlV, loadLE(Ity_V256, mkexpr(addr)));
+ }
+ IRTemp dataV = newTemp(Ity_V256);
+ assign(dataV, getYMMReg(rV));
+ IRTemp resV = math_PERMILPD_VAR_256(dataV, ctrlV);
+ putYMMReg(rG, mkexpr(resV));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x0E:
+ /* VTESTPS xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 0E /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_xTESTy_128( vbi, pfx, delta, True/*isAvx*/, 32 );
+ goto decode_success;
+ }
+ /* VTESTPS ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 0E /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_xTESTy_256( vbi, pfx, delta, 32 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x0F:
+ /* VTESTPD xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 0F /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_xTESTy_128( vbi, pfx, delta, True/*isAvx*/, 64 );
+ goto decode_success;
+ }
+ /* VTESTPD ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 0F /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_xTESTy_256( vbi, pfx, delta, 64 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x17:
+ /* VPTEST xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 17 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_xTESTy_128( vbi, pfx, delta, True/*isAvx*/, 0 );
+ goto decode_success;
+ }
+ /* VPTEST ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 17 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_xTESTy_256( vbi, pfx, delta, 0 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x18:
+ /* VBROADCASTSS m32, xmm1 = VEX.128.66.0F38.WIG 18 /r */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/
+ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vbroadcastss %s,%s\n", dis_buf, nameXMMReg(rG));
+ IRTemp t32 = newTemp(Ity_I32);
+ assign(t32, loadLE(Ity_I32, mkexpr(addr)));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = binop(Iop_64HLtoV128, mkexpr(t64), mkexpr(t64));
+ putYMMRegLoAndZU(rG, res);
+ goto decode_success;
+ }
+ /* VBROADCASTSS m32, ymm1 = VEX.256.66.0F38.WIG 18 /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/
+ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vbroadcastss %s,%s\n", dis_buf, nameYMMReg(rG));
+ IRTemp t32 = newTemp(Ity_I32);
+ assign(t32, loadLE(Ity_I32, mkexpr(addr)));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, binop(Iop_32HLto64, mkexpr(t32), mkexpr(t32)));
+ IRExpr* res = IRExpr_Qop(Iop_64x4toV256, mkexpr(t64), mkexpr(t64),
+ mkexpr(t64), mkexpr(t64));
+ putYMMReg(rG, res);
+ goto decode_success;
+ }
+ break;
+
+ case 0x19:
+ /* VBROADCASTSD m64, ymm1 = VEX.256.66.0F38.WIG 19 /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/
+ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vbroadcastsd %s,%s\n", dis_buf, nameYMMReg(rG));
+ IRTemp t64 = newTemp(Ity_I64);
+ assign(t64, loadLE(Ity_I64, mkexpr(addr)));
+ IRExpr* res = IRExpr_Qop(Iop_64x4toV256, mkexpr(t64), mkexpr(t64),
+ mkexpr(t64), mkexpr(t64));
+ putYMMReg(rG, res);
+ goto decode_success;
+ }
+ break;
+
+ case 0x1A:
+ /* VBROADCASTF128 m128, ymm1 = VEX.256.66.0F38.WIG 1A /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/
+ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ DIP("vbroadcastf128 %s,%s\n", dis_buf, nameYMMReg(rG));
+ IRTemp t128 = newTemp(Ity_V128);
+ assign(t128, loadLE(Ity_V128, mkexpr(addr)));
+ putYMMReg( rG, binop(Iop_V128HLtoV256, mkexpr(t128), mkexpr(t128)) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x1C:
+ /* VPABSB xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 1C /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_to_G_unary(
+ uses_vvvv, vbi, pfx, delta,
+ "vpabsb", math_PABS_XMM_pap1 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x1D:
+ /* VPABSW xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 1D /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_to_G_unary(
+ uses_vvvv, vbi, pfx, delta,
+ "vpabsw", math_PABS_XMM_pap2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x1E:
+ /* VPABSD xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 1E /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_to_G_unary(
+ uses_vvvv, vbi, pfx, delta,
+ "vpabsd", math_PABS_XMM_pap4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x20:
+ /* VPMOVSXBW xmm2/m64, xmm1 */
+ /* VPMOVSXBW = VEX.128.66.0F38.WIG 20 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVxXBW_128( vbi, pfx, delta,
+ True/*isAvx*/, False/*!xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x21:
+ /* VPMOVSXBD xmm2/m32, xmm1 */
+ /* VPMOVSXBD = VEX.128.66.0F38.WIG 21 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVxXBD_128( vbi, pfx, delta,
+ True/*isAvx*/, False/*!xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x22:
+ /* VPMOVSXBQ xmm2/m16, xmm1 */
+ /* VPMOVSXBQ = VEX.128.66.0F38.WIG 22 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVSXBQ_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x23:
+ /* VPMOVSXWD xmm2/m64, xmm1 = VEX.128.66.0F38.WIG 23 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVxXWD_128( vbi, pfx, delta,
+ True/*isAvx*/, False/*!xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x24:
+ /* VPMOVSXWQ xmm2/m32, xmm1 = VEX.128.66.0F38.WIG 24 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVSXWQ_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x25:
+ /* VPMOVSXDQ xmm2/m64, xmm1 = VEX.128.66.0F38.WIG 25 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVxXDQ_128( vbi, pfx, delta,
+ True/*isAvx*/, False/*!xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x28:
+ /* VPMULDQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 28 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_complex(
+ uses_vvvv, vbi, pfx, delta,
+ "vpmuldq", math_PMULDQ_128 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x29:
+ /* VPCMPEQQ r/m, rV, r ::: r = rV `eq-by-64s` r/m */
+ /* VPCMPEQQ = VEX.NDS.128.66.0F38.WIG 29 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpeqq", Iop_CmpEQ64x2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x2A:
+ /* VMOVNTDQA m128, xmm1 = VEX.128.66.0F38.WIG 2A /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/
+ && !epartIsReg(getUChar(delta))) {
+ UChar modrm = getUChar(delta);
+ UInt rD = gregOfRexRM(pfx, modrm);
+ IRTemp tD = newTemp(Ity_V128);
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_16_aligned(addr);
+ assign(tD, loadLE(Ity_V128, mkexpr(addr)));
+ DIP("vmovntdqa %s,%s\n", dis_buf, nameXMMReg(rD));
+ putYMMRegLoAndZU(rD, mkexpr(tD));
+ goto decode_success;
+ }
+ break;
+
+ case 0x2B:
+ /* VPACKUSDW r/m, rV, r ::: r = QNarrowBin32Sto16Ux8(rV, r/m) */
+ /* VPACKUSDW = VEX.NDS.128.66.0F38.WIG 2B /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vpackusdw",
+ Iop_QNarrowBin32Sto16Ux8, NULL,
+ False/*!invertLeftArg*/, True/*swapArgs*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x30:
+ /* VPMOVZXBW xmm2/m64, xmm1 */
+ /* VPMOVZXBW = VEX.128.66.0F38.WIG 30 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVxXBW_128( vbi, pfx, delta,
+ True/*isAvx*/, True/*xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x31:
+ /* VPMOVZXBD xmm2/m32, xmm1 */
+ /* VPMOVZXBD = VEX.128.66.0F38.WIG 31 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVxXBD_128( vbi, pfx, delta,
+ True/*isAvx*/, True/*xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x32:
+ /* VPMOVZXBQ xmm2/m16, xmm1 */
+ /* VPMOVZXBQ = VEX.128.66.0F38.WIG 32 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVZXBQ_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x33:
+ /* VPMOVZXWD xmm2/m64, xmm1 */
+ /* VPMOVZXWD = VEX.128.66.0F38.WIG 33 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVxXWD_128( vbi, pfx, delta,
+ True/*isAvx*/, True/*xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x34:
+ /* VPMOVZXWQ xmm2/m32, xmm1 = VEX.128.66.0F38.WIG 34 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVZXWQ_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x35:
+ /* VPMOVZXDQ xmm2/m64, xmm1 = VEX.128.66.0F38.WIG 35 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PMOVxXDQ_128( vbi, pfx, delta,
+ True/*isAvx*/, True/*xIsZ*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x37:
+ /* VPCMPGTQ r/m, rV, r ::: r = rV `>s-by-64s` r/m */
+ /* VPCMPGTQ = VEX.NDS.128.66.0F38.WIG 37 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpcmpgtq", Iop_CmpGT64Sx2 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x38:
+ /* VPMINSB r/m, rV, r ::: r = min-signed-8s(rV, r/m) */
+ /* VPMINSB = VEX.NDS.128.66.0F38.WIG 38 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminsb", Iop_Min8Sx16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x39:
+ /* VPMINSD r/m, rV, r ::: r = min-signed-32s(rV, r/m) */
+ /* VPMINSD = VEX.NDS.128.66.0F38.WIG 39 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminsd", Iop_Min32Sx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x3A:
+ /* VPMINUW r/m, rV, r ::: r = min-unsigned-16s(rV, r/m) */
+ /* VPMINUW = VEX.NDS.128.66.0F38.WIG 3A /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminuw", Iop_Min16Ux8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x3B:
+ /* VPMINUD r/m, rV, r ::: r = min-unsigned-32s(rV, r/m) */
+ /* VPMINUD = VEX.NDS.128.66.0F38.WIG 3B /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpminud", Iop_Min32Ux4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x3C:
+ /* VPMAXSB r/m, rV, r ::: r = max-signed-8s(rV, r/m) */
+ /* VPMAXSB = VEX.NDS.128.66.0F38.WIG 3C /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxsb", Iop_Max8Sx16 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x3D:
+ /* VPMAXSD r/m, rV, r ::: r = max-signed-32s(rV, r/m) */
+ /* VPMAXSD = VEX.NDS.128.66.0F38.WIG 3D /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxsd", Iop_Max32Sx4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x3E:
+ /* VPMAXUW r/m, rV, r ::: r = max-unsigned-16s(rV, r/m) */
+ /* VPMAXUW = VEX.NDS.128.66.0F38.WIG 3E /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxuw", Iop_Max16Ux8 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x3F:
+ /* VPMAXUD r/m, rV, r ::: r = max-unsigned-32s(rV, r/m) */
+ /* VPMAXUD = VEX.NDS.128.66.0F38.WIG 3F /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmaxud", Iop_Max32Ux4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x40:
+ /* VPMULLD r/m, rV, r ::: r = mul-32s(rV, r/m) */
+ /* VPMULLD = VEX.NDS.128.66.0F38.WIG 40 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple(
+ uses_vvvv, vbi, pfx, delta, "vpmulld", Iop_Mul32x4 );
+ goto decode_success;
+ }
+ break;
+
+ case 0x41:
+ /* VPHMINPOSUW xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 41 /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_PHMINPOSUW_128( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0xDB:
+ case 0xDC:
+ case 0xDD:
+ case 0xDE:
+ case 0xDF:
+ /* VAESIMC xmm2/m128, xmm1 = VEX.128.66.0F38.WIG DB /r */
+ /* VAESENC xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DC /r */
+ /* VAESENCLAST xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DD /r */
+ /* VAESDEC xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DE /r */
+ /* VAESDECLAST xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DF /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AESx( vbi, pfx, delta, True/*!isAvx*/, opc );
+ if (opc != 0xDB) *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ default:
+ break;
+
+ }
+
+ //decode_failure:
+ return deltaIN;
+
+ decode_success:
+ return delta;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Top-level post-escape decoders: dis_ESC_0F3A__VEX ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+static IRTemp math_VPERMILPS_128 ( IRTemp sV, UInt imm8 )
+{
+ vassert(imm8 < 256);
+ IRTemp s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ breakupV128to32s( sV, &s3, &s2, &s1, &s0 );
+# define SEL(_nn) (((_nn)==0) ? s0 : ((_nn)==1) ? s1 \
+ : ((_nn)==2) ? s2 : s3)
+ IRTemp res = newTemp(Ity_V128);
+ assign(res, mkV128from32s( SEL((imm8 >> 6) & 3),
+ SEL((imm8 >> 4) & 3),
+ SEL((imm8 >> 2) & 3),
+ SEL((imm8 >> 0) & 3) ));
+# undef SEL
+ return res;
+}
+
+__attribute__((noinline))
+static
+Long dis_ESC_0F3A__VEX (
+ /*MB_OUT*/DisResult* dres,
+ /*OUT*/ Bool* uses_vvvv,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi,
+ Prefix pfx, Int sz, Long deltaIN
+ )
+{
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ Long delta = deltaIN;
+ UChar opc = getUChar(delta);
+ delta++;
+ *uses_vvvv = False;
+
+ switch (opc) {
+
+ case 0x04:
+ /* VPERMILPS imm8, ymm2/m256, ymm1 = VEX.256.66.0F3A.WIG 04 /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8 = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp sV = newTemp(Ity_V256);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vpermilps $%u,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rG));
+ assign(sV, getYMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vpermilps $%u,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rG));
+ assign(sV, loadLE(Ity_V256, mkexpr(addr)));
+ }
+ delta++;
+ IRTemp sVhi = IRTemp_INVALID, sVlo = IRTemp_INVALID;
+ breakupV256toV128s( sV, &sVhi, &sVlo );
+ IRTemp dVhi = math_VPERMILPS_128( sVhi, imm8 );
+ IRTemp dVlo = math_VPERMILPS_128( sVlo, imm8 );
+ IRExpr* res = binop(Iop_V128HLtoV256, mkexpr(dVhi), mkexpr(dVlo));
+ putYMMReg(rG, res);
+ goto decode_success;
+ }
+ /* VPERMILPS imm8, xmm2/m128, xmm1 = VEX.128.66.0F3A.WIG 04 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8 = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp sV = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vpermilps $%u,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rG));
+ assign(sV, getXMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vpermilps $%u,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rG));
+ assign(sV, loadLE(Ity_V128, mkexpr(addr)));
+ }
+ delta++;
+ putYMMRegLoAndZU(rG, mkexpr ( math_VPERMILPS_128 ( sV, imm8 ) ) );
+ goto decode_success;
+ }
+ break;
+
+ case 0x05:
+ /* VPERMILPD imm8, xmm2/m128, xmm1 = VEX.128.66.0F3A.WIG 05 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8 = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp sV = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vpermilpd $%u,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rG));
+ assign(sV, getXMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vpermilpd $%u,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rG));
+ assign(sV, loadLE(Ity_V128, mkexpr(addr)));
+ }
+ delta++;
+ IRTemp s1 = newTemp(Ity_I64);
+ IRTemp s0 = newTemp(Ity_I64);
+ assign(s1, unop(Iop_V128HIto64, mkexpr(sV)));
+ assign(s0, unop(Iop_V128to64, mkexpr(sV)));
+ IRTemp dV = newTemp(Ity_V128);
+ assign(dV, binop(Iop_64HLtoV128,
+ mkexpr((imm8 & (1<<1)) ? s1 : s0),
+ mkexpr((imm8 & (1<<0)) ? s1 : s0)));
+ putYMMRegLoAndZU(rG, mkexpr(dV));
+ goto decode_success;
+ }
+ /* VPERMILPD imm8, ymm2/m256, ymm1 = VEX.256.66.0F3A.WIG 05 /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8 = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp sV = newTemp(Ity_V256);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vpermilpd $%u,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rG));
+ assign(sV, getYMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vpermilpd $%u,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rG));
+ assign(sV, loadLE(Ity_V256, mkexpr(addr)));
+ }
+ delta++;
+ IRTemp s3, s2, s1, s0;
+ s3 = s2 = s1 = s0 = IRTemp_INVALID;
+ breakupV256to64s(sV, &s3, &s2, &s1, &s0);
+ IRTemp dV = newTemp(Ity_V256);
+ assign(dV, IRExpr_Qop(Iop_64x4toV256,
+ mkexpr((imm8 & (1<<3)) ? s3 : s2),
+ mkexpr((imm8 & (1<<2)) ? s3 : s2),
+ mkexpr((imm8 & (1<<1)) ? s1 : s0),
+ mkexpr((imm8 & (1<<0)) ? s1 : s0)));
+ putYMMReg(rG, mkexpr(dV));
+ goto decode_success;
+ }
+ break;
+
+ case 0x06:
+ /* VPERM2F128 imm8, ymm3/m256, ymm2, ymm1 = VEX.NDS.66.0F3A.W0 06 /r ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8 = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp s00 = newTemp(Ity_V128);
+ IRTemp s01 = newTemp(Ity_V128);
+ IRTemp s10 = newTemp(Ity_V128);
+ IRTemp s11 = newTemp(Ity_V128);
+ assign(s00, getYMMRegLane128(rV, 0));
+ assign(s01, getYMMRegLane128(rV, 1));
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vperm2f128 $%u,%s,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ assign(s10, getYMMRegLane128(rE, 0));
+ assign(s11, getYMMRegLane128(rE, 1));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vperm2f128 $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ assign(s10, loadLE(Ity_V128, binop(Iop_Add64,
+ mkexpr(addr), mkU64(0))));
+ assign(s11, loadLE(Ity_V128, binop(Iop_Add64,
+ mkexpr(addr), mkU64(16))));
+ }
+ delta++;
+# define SEL(_nn) (((_nn)==0) ? s00 : ((_nn)==1) ? s01 \
+ : ((_nn)==2) ? s10 : s11)
+ putYMMRegLane128(rG, 0, mkexpr(SEL((imm8 >> 0) & 3)));
+ putYMMRegLane128(rG, 1, mkexpr(SEL((imm8 >> 4) & 3)));
+# undef SEL
+ if (imm8 & (1<<3)) putYMMRegLane128(rG, 0, mkV128(0));
+ if (imm8 & (1<<7)) putYMMRegLane128(rG, 1, mkV128(0));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x08:
+ /* VROUNDPS imm8, xmm2/m128, xmm1 */
+ /* VROUNDPS = VEX.NDS.128.66.0F3A.WIG 08 ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp src = newTemp(Ity_V128);
+ IRTemp s0 = IRTemp_INVALID;
+ IRTemp s1 = IRTemp_INVALID;
+ IRTemp s2 = IRTemp_INVALID;
+ IRTemp s3 = IRTemp_INVALID;
+ IRTemp rm = newTemp(Ity_I32);
+ Int imm = 0;
+
+ modrm = getUChar(delta);
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( src, getXMMReg( rE ) );
+ imm = getUChar(delta+1);
+ if (imm & ~15) break;
+ delta += 1+1;
+ DIP( "vroundps $%d,%s,%s\n", imm, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( src, loadLE(Ity_V128, mkexpr(addr) ) );
+ imm = getUChar(delta+alen);
+ if (imm & ~15) break;
+ delta += alen+1;
+ DIP( "vroundps $%d,%s,%s\n", imm, dis_buf, nameXMMReg(rG) );
+ }
+
+ /* (imm & 3) contains an Intel-encoded rounding mode. Because
+ that encoding is the same as the encoding for IRRoundingMode,
+ we can use that value directly in the IR as a rounding
+ mode. */
+ assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
+
+ breakupV128to32s( src, &s3, &s2, &s1, &s0 );
+ putYMMRegLane128( rG, 1, mkV128(0) );
+# define CVT(s) binop(Iop_RoundF32toInt, mkexpr(rm), \
+ unop(Iop_ReinterpI32asF32, mkexpr(s)))
+ putYMMRegLane32F( rG, 3, CVT(s3) );
+ putYMMRegLane32F( rG, 2, CVT(s2) );
+ putYMMRegLane32F( rG, 1, CVT(s1) );
+ putYMMRegLane32F( rG, 0, CVT(s0) );
+# undef CVT
+ goto decode_success;
+ }
+ /* VROUNDPS imm8, ymm2/m256, ymm1 */
+ /* VROUNDPS = VEX.NDS.256.66.0F3A.WIG 08 ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp src = newTemp(Ity_V256);
+ IRTemp s0 = IRTemp_INVALID;
+ IRTemp s1 = IRTemp_INVALID;
+ IRTemp s2 = IRTemp_INVALID;
+ IRTemp s3 = IRTemp_INVALID;
+ IRTemp s4 = IRTemp_INVALID;
+ IRTemp s5 = IRTemp_INVALID;
+ IRTemp s6 = IRTemp_INVALID;
+ IRTemp s7 = IRTemp_INVALID;
+ IRTemp rm = newTemp(Ity_I32);
+ Int imm = 0;
+
+ modrm = getUChar(delta);
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( src, getYMMReg( rE ) );
+ imm = getUChar(delta+1);
+ if (imm & ~15) break;
+ delta += 1+1;
+ DIP( "vroundps $%d,%s,%s\n", imm, nameYMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( src, loadLE(Ity_V256, mkexpr(addr) ) );
+ imm = getUChar(delta+alen);
+ if (imm & ~15) break;
+ delta += alen+1;
+ DIP( "vroundps $%d,%s,%s\n", imm, dis_buf, nameYMMReg(rG) );
+ }
+
+ /* (imm & 3) contains an Intel-encoded rounding mode. Because
+ that encoding is the same as the encoding for IRRoundingMode,
+ we can use that value directly in the IR as a rounding
+ mode. */
+ assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
+
+ breakupV256to32s( src, &s7, &s6, &s5, &s4, &s3, &s2, &s1, &s0 );
+# define CVT(s) binop(Iop_RoundF32toInt, mkexpr(rm), \
+ unop(Iop_ReinterpI32asF32, mkexpr(s)))
+ putYMMRegLane32F( rG, 7, CVT(s7) );
+ putYMMRegLane32F( rG, 6, CVT(s6) );
+ putYMMRegLane32F( rG, 5, CVT(s5) );
+ putYMMRegLane32F( rG, 4, CVT(s4) );
+ putYMMRegLane32F( rG, 3, CVT(s3) );
+ putYMMRegLane32F( rG, 2, CVT(s2) );
+ putYMMRegLane32F( rG, 1, CVT(s1) );
+ putYMMRegLane32F( rG, 0, CVT(s0) );
+# undef CVT
+ goto decode_success;
+ }
+
+ case 0x09:
+ /* VROUNDPD imm8, xmm2/m128, xmm1 */
+ /* VROUNDPD = VEX.NDS.128.66.0F3A.WIG 09 ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp src = newTemp(Ity_V128);
+ IRTemp s0 = IRTemp_INVALID;
+ IRTemp s1 = IRTemp_INVALID;
+ IRTemp rm = newTemp(Ity_I32);
+ Int imm = 0;
+
+ modrm = getUChar(delta);
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( src, getXMMReg( rE ) );
+ imm = getUChar(delta+1);
+ if (imm & ~15) break;
+ delta += 1+1;
+ DIP( "vroundpd $%d,%s,%s\n", imm, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( src, loadLE(Ity_V128, mkexpr(addr) ) );
+ imm = getUChar(delta+alen);
+ if (imm & ~15) break;
+ delta += alen+1;
+ DIP( "vroundpd $%d,%s,%s\n", imm, dis_buf, nameXMMReg(rG) );
+ }
+
+ /* (imm & 3) contains an Intel-encoded rounding mode. Because
+ that encoding is the same as the encoding for IRRoundingMode,
+ we can use that value directly in the IR as a rounding
+ mode. */
+ assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
+
+ breakupV128to64s( src, &s1, &s0 );
+ putYMMRegLane128( rG, 1, mkV128(0) );
+# define CVT(s) binop(Iop_RoundF64toInt, mkexpr(rm), \
+ unop(Iop_ReinterpI64asF64, mkexpr(s)))
+ putYMMRegLane64F( rG, 1, CVT(s1) );
+ putYMMRegLane64F( rG, 0, CVT(s0) );
+# undef CVT
+ goto decode_success;
+ }
+ /* VROUNDPD imm8, ymm2/m256, ymm1 */
+ /* VROUNDPD = VEX.NDS.256.66.0F3A.WIG 09 ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp src = newTemp(Ity_V256);
+ IRTemp s0 = IRTemp_INVALID;
+ IRTemp s1 = IRTemp_INVALID;
+ IRTemp s2 = IRTemp_INVALID;
+ IRTemp s3 = IRTemp_INVALID;
+ IRTemp rm = newTemp(Ity_I32);
+ Int imm = 0;
+
+ modrm = getUChar(delta);
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( src, getYMMReg( rE ) );
+ imm = getUChar(delta+1);
+ if (imm & ~15) break;
+ delta += 1+1;
+ DIP( "vroundpd $%d,%s,%s\n", imm, nameYMMReg(rE), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( src, loadLE(Ity_V256, mkexpr(addr) ) );
+ imm = getUChar(delta+alen);
+ if (imm & ~15) break;
+ delta += alen+1;
+ DIP( "vroundps $%d,%s,%s\n", imm, dis_buf, nameYMMReg(rG) );
+ }
+
+ /* (imm & 3) contains an Intel-encoded rounding mode. Because
+ that encoding is the same as the encoding for IRRoundingMode,
+ we can use that value directly in the IR as a rounding
+ mode. */
+ assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
+
+ breakupV256to64s( src, &s3, &s2, &s1, &s0 );
+# define CVT(s) binop(Iop_RoundF64toInt, mkexpr(rm), \
+ unop(Iop_ReinterpI64asF64, mkexpr(s)))
+ putYMMRegLane64F( rG, 3, CVT(s3) );
+ putYMMRegLane64F( rG, 2, CVT(s2) );
+ putYMMRegLane64F( rG, 1, CVT(s1) );
+ putYMMRegLane64F( rG, 0, CVT(s0) );
+# undef CVT
+ goto decode_success;
+ }
+
+ case 0x0A:
+ case 0x0B:
+ /* VROUNDSS imm8, xmm3/m32, xmm2, xmm1 */
+ /* VROUNDSS = VEX.NDS.128.66.0F3A.WIG 0A ib */
+ /* VROUNDSD imm8, xmm3/m64, xmm2, xmm1 */
+ /* VROUNDSD = VEX.NDS.128.66.0F3A.WIG 0B ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ Bool isD = opc == 0x0B;
+ IRTemp src = newTemp(isD ? Ity_F64 : Ity_F32);
+ IRTemp res = newTemp(isD ? Ity_F64 : Ity_F32);
+ Int imm = 0;
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( src,
+ isD ? getXMMRegLane64F(rE, 0) : getXMMRegLane32F(rE, 0) );
+ imm = getUChar(delta+1);
+ if (imm & ~15) break;
+ delta += 1+1;
+ DIP( "vrounds%c $%d,%s,%s,%s\n",
+ isD ? 'd' : 's',
+ imm, nameXMMReg( rE ), nameXMMReg( rV ), nameXMMReg( rG ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( src, loadLE( isD ? Ity_F64 : Ity_F32, mkexpr(addr) ));
+ imm = getUChar(delta+alen);
+ if (imm & ~15) break;
+ delta += alen+1;
+ DIP( "vrounds%c $%d,%s,%s,%s\n",
+ isD ? 'd' : 's',
+ imm, dis_buf, nameXMMReg( rV ), nameXMMReg( rG ) );
+ }
+
+ /* (imm & 3) contains an Intel-encoded rounding mode. Because
+ that encoding is the same as the encoding for IRRoundingMode,
+ we can use that value directly in the IR as a rounding
+ mode. */
+ assign(res, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+ (imm & 4) ? get_sse_roundingmode()
+ : mkU32(imm & 3),
+ mkexpr(src)) );
+
+ if (isD)
+ putXMMRegLane64F( rG, 0, mkexpr(res) );
+ else {
+ putXMMRegLane32F( rG, 0, mkexpr(res) );
+ putXMMRegLane32F( rG, 1, getXMMRegLane32F( rV, 1 ) );
+ }
+ putXMMRegLane64F( rG, 1, getXMMRegLane64F( rV, 1 ) );
+ putYMMRegLane128( rG, 1, mkV128(0) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x0C:
+ /* VBLENDPS imm8, ymm3/m256, ymm2, ymm1 */
+ /* VBLENDPS = VEX.NDS.256.66.0F3A.WIG 0C /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp sE = newTemp(Ity_V256);
+ assign ( sV, getYMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vblendps $%u,%s,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ assign(sE, getYMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vblendps $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ assign(sE, loadLE(Ity_V256, mkexpr(addr)));
+ }
+ delta++;
+ putYMMReg( rG,
+ mkexpr( math_BLENDPS_256( sE, sV, imm8) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VBLENDPS imm8, xmm3/m128, xmm2, xmm1 */
+ /* VBLENDPS = VEX.NDS.128.66.0F3A.WIG 0C /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp sE = newTemp(Ity_V128);
+ assign ( sV, getXMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vblendps $%u,%s,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ assign(sE, getXMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vblendps $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ assign(sE, loadLE(Ity_V128, mkexpr(addr)));
+ }
+ delta++;
+ putYMMRegLoAndZU( rG,
+ mkexpr( math_BLENDPS_128( sE, sV, imm8) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x0D:
+ /* VBLENDPD imm8, ymm3/m256, ymm2, ymm1 */
+ /* VBLENDPD = VEX.NDS.256.66.0F3A.WIG 0D /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V256);
+ IRTemp sE = newTemp(Ity_V256);
+ assign ( sV, getYMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vblendpd $%u,%s,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ assign(sE, getYMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vblendpd $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ assign(sE, loadLE(Ity_V256, mkexpr(addr)));
+ }
+ delta++;
+ putYMMReg( rG,
+ mkexpr( math_BLENDPD_256( sE, sV, imm8) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VBLENDPD imm8, xmm3/m128, xmm2, xmm1 */
+ /* VBLENDPD = VEX.NDS.128.66.0F3A.WIG 0D /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp sE = newTemp(Ity_V128);
+ assign ( sV, getXMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vblendpd $%u,%s,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ assign(sE, getXMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vblendpd $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ assign(sE, loadLE(Ity_V128, mkexpr(addr)));
+ }
+ delta++;
+ putYMMRegLoAndZU( rG,
+ mkexpr( math_BLENDPD_128( sE, sV, imm8) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x0E:
+ /* VPBLENDW imm8, xmm3/m128, xmm2, xmm1 */
+ /* VPBLENDW = VEX.NDS.128.66.0F3A.WIG 0E /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt imm8;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp sE = newTemp(Ity_V128);
+ assign ( sV, getXMMReg(rV) );
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ imm8 = getUChar(delta);
+ DIP("vpblendw $%u,%s,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
+ assign(sE, getXMMReg(rE));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ imm8 = getUChar(delta);
+ DIP("vpblendw $%u,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ assign(sE, loadLE(Ity_V128, mkexpr(addr)));
+ }
+ delta++;
+ putYMMRegLoAndZU( rG,
+ mkexpr( math_PBLENDW_128( sE, sV, imm8) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x0F:
+ /* VPALIGNR imm8, xmm3/m128, xmm2, xmm1 */
+ /* VPALIGNR = VEX.NDS.128.66.0F3A.WIG 0F /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ UInt imm8;
+
+ assign( dV, getXMMReg(rV) );
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign( sV, getXMMReg(rE) );
+ imm8 = getUChar(delta+1);
+ delta += 1+1;
+ DIP("vpalignr $%d,%s,%s,%s\n", imm8, nameXMMReg(rE),
+ nameXMMReg(rV), nameXMMReg(rG));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
+ imm8 = getUChar(delta+alen);
+ delta += alen+1;
+ DIP("vpalignr $%d,%s,%s,%s\n", imm8, dis_buf,
+ nameXMMReg(rV), nameXMMReg(rG));
+ }
+
+ IRTemp res = math_PALIGNR_XMM( sV, dV, imm8 );
+ putYMMRegLoAndZU( rG, mkexpr(res) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x14:
+ /* VPEXTRB imm8, xmm2, reg/m8 = VEX.128.66.0F3A.W0 14 /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_PEXTRB_128_GtoE( vbi, pfx, delta, False/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x15:
+ /* VPEXTRW imm8, reg/m16, xmm2 */
+ /* VPEXTRW = VEX.128.66.0F3A.W0 15 /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_PEXTRW( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x16:
+ /* VPEXTRD imm8, r32/m32, xmm2 */
+ /* VPEXTRD = VEX.128.66.0F3A.W0 16 /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ delta = dis_PEXTRD( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ /* VPEXTRQ = VEX.128.66.0F3A.W1 16 /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 1==getRexW(pfx)/*W1*/) {
+ delta = dis_PEXTRQ( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x17:
+ /* VEXTRACTPS imm8, xmm1, r32/m32 = VEX.128.66.0F3A.WIG 17 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_EXTRACTPS( vbi, pfx, delta, True/*isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ case 0x18:
+ /* VINSERTF128 r/m, rV, rD
+ ::: rD = insertinto(a lane in rV, 128 bits from r/m) */
+ /* VINSERTF128 = VEX.NDS.256.66.0F3A.W0 18 /r ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt ib = 0;
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp t128 = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ assign(t128, getXMMReg(rE));
+ ib = getUChar(delta);
+ DIP("vinsertf128 $%u,%s,%s,%s\n",
+ ib, nameXMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign(t128, loadLE(Ity_V128, mkexpr(addr)));
+ delta += alen;
+ ib = getUChar(delta);
+ DIP("vinsertf128 $%u,%s,%s,%s\n",
+ ib, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ }
+ delta++;
+ putYMMRegLane128(rG, 0, getYMMRegLane128(rV, 0));
+ putYMMRegLane128(rG, 1, getYMMRegLane128(rV, 1));
+ putYMMRegLane128(rG, ib & 1, mkexpr(t128));
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x19:
+ /* VEXTRACTF128 $lane_no, rS, r/m
+ ::: r/m:V128 = a lane of rS:V256 (RM format) */
+ /* VEXTRACTF128 = VEX.256.66.0F3A.W0 19 /r ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt ib = 0;
+ UInt rS = gregOfRexRM(pfx, modrm);
+ IRTemp t128 = newTemp(Ity_V128);
+ if (epartIsReg(modrm)) {
+ UInt rD = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ ib = getUChar(delta);
+ assign(t128, getYMMRegLane128(rS, ib & 1));
+ putYMMRegLoAndZU(rD, mkexpr(t128));
+ DIP("vextractf128 $%u,%s,%s\n",
+ ib, nameXMMReg(rS), nameYMMReg(rD));
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ ib = getUChar(delta);
+ assign(t128, getYMMRegLane128(rS, ib & 1));
+ storeLE(mkexpr(addr), mkexpr(t128));
+ DIP("vextractf128 $%u,%s,%s\n",
+ ib, nameYMMReg(rS), dis_buf);
+ }
+ delta++;
+ /* doesn't use vvvv */
+ goto decode_success;
+ }
+ break;
+
+ case 0x20:
+ /* VPINSRB r32/m8, xmm2, xmm1 = VEX.NDS.128.66.0F3A.W0 20 /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ Int imm8;
+ IRTemp src_u8 = newTemp(Ity_I8);
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ imm8 = (Int)(getUChar(delta+1) & 15);
+ assign( src_u8, unop(Iop_32to8, getIReg32( rE )) );
+ delta += 1+1;
+ DIP( "vpinsrb $%d,%s,%s,%s\n",
+ imm8, nameIReg32(rE), nameXMMReg(rV), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8 = (Int)(getUChar(delta+alen) & 15);
+ assign( src_u8, loadLE( Ity_I8, mkexpr(addr) ) );
+ delta += alen+1;
+ DIP( "vpinsrb $%d,%s,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG) );
+ }
+
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg( rV ));
+ IRTemp res_vec = math_PINSRB_128( src_vec, src_u8, imm8 );
+ putYMMRegLoAndZU( rG, mkexpr(res_vec) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x21:
+ /* VINSERTPS imm8, xmm3/m32, xmm2, xmm1
+ = VEX.NDS.128.66.0F3A.WIG 21 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ UInt imm8;
+ IRTemp d2ins = newTemp(Ity_I32); /* comes from the E part */
+ const IRTemp inval = IRTemp_INVALID;
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ IRTemp vE = newTemp(Ity_V128);
+ assign( vE, getXMMReg(rE) );
+ IRTemp dsE[4] = { inval, inval, inval, inval };
+ breakupV128to32s( vE, &dsE[3], &dsE[2], &dsE[1], &dsE[0] );
+ imm8 = getUChar(delta+1);
+ d2ins = dsE[(imm8 >> 6) & 3]; /* "imm8_count_s" */
+ delta += 1+1;
+ DIP( "insertps $%u, %s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ assign( d2ins, loadLE( Ity_I32, mkexpr(addr) ) );
+ imm8 = getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "insertps $%u, %s,%s\n",
+ imm8, dis_buf, nameXMMReg(rG) );
+ }
+
+ IRTemp vV = newTemp(Ity_V128);
+ assign( vV, getXMMReg(rV) );
+
+ putYMMRegLoAndZU( rG, mkexpr(math_INSERTPS( vV, d2ins, imm8 )) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x22:
+ /* VPINSRD r32/m32, xmm2, xmm1 = VEX.NDS.128.66.0F3A.W0 22 /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ Int imm8_10;
+ IRTemp src_u32 = newTemp(Ity_I32);
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ imm8_10 = (Int)(getUChar(delta+1) & 3);
+ assign( src_u32, getIReg32( rE ) );
+ delta += 1+1;
+ DIP( "vpinsrd $%d,%s,%s,%s\n",
+ imm8_10, nameIReg32(rE), nameXMMReg(rV), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8_10 = (Int)(getUChar(delta+alen) & 3);
+ assign( src_u32, loadLE( Ity_I32, mkexpr(addr) ) );
+ delta += alen+1;
+ DIP( "vpinsrd $%d,%s,%s,%s\n",
+ imm8_10, dis_buf, nameXMMReg(rV), nameXMMReg(rG) );
+ }
+
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg( rV ));
+ IRTemp res_vec = math_PINSRD_128( src_vec, src_u32, imm8_10 );
+ putYMMRegLoAndZU( rG, mkexpr(res_vec) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VPINSRQ r64/m64, xmm2, xmm1 = VEX.NDS.128.66.0F3A.W1 22 /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 1==getRexW(pfx)/*W1*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ Int imm8_0;
+ IRTemp src_u64 = newTemp(Ity_I64);
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ imm8_0 = (Int)(getUChar(delta+1) & 1);
+ assign( src_u64, getIReg64( rE ) );
+ delta += 1+1;
+ DIP( "vpinsrq $%d,%s,%s,%s\n",
+ imm8_0, nameIReg64(rE), nameXMMReg(rV), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8_0 = (Int)(getUChar(delta+alen) & 1);
+ assign( src_u64, loadLE( Ity_I64, mkexpr(addr) ) );
+ delta += alen+1;
+ DIP( "vpinsrd $%d,%s,%s,%s\n",
+ imm8_0, dis_buf, nameXMMReg(rV), nameXMMReg(rG) );
+ }
+
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg( rV ));
+ IRTemp res_vec = math_PINSRQ_128( src_vec, src_u64, imm8_0 );
+ putYMMRegLoAndZU( rG, mkexpr(res_vec) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x40:
+ /* VDPPS imm8, xmm3/m128,xmm2,xmm1 = VEX.NDS.128.66.0F3A.WIG 40 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp dst_vec = newTemp(Ity_V128);
+ Int imm8;
+ if (epartIsReg( modrm )) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ imm8 = (Int)getUChar(delta+1);
+ assign( dst_vec, getXMMReg( rE ) );
+ delta += 1+1;
+ DIP( "vdpps $%d,%s,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8 = (Int)getUChar(delta+alen);
+ assign( dst_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ delta += alen+1;
+ DIP( "vdpps $%d,%s,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG) );
+ }
+
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg( rV ));
+ IRTemp res_vec = math_DPPS_128( src_vec, dst_vec, imm8 );
+ putYMMRegLoAndZU( rG, mkexpr(res_vec) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VDPPS imm8, ymm3/m128,ymm2,ymm1 = VEX.NDS.256.66.0F3A.WIG 40 /r ib */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp dst_vec = newTemp(Ity_V256);
+ Int imm8;
+ if (epartIsReg( modrm )) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ imm8 = (Int)getUChar(delta+1);
+ assign( dst_vec, getYMMReg( rE ) );
+ delta += 1+1;
+ DIP( "vdpps $%d,%s,%s,%s\n",
+ imm8, nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8 = (Int)getUChar(delta+alen);
+ assign( dst_vec, loadLE( Ity_V256, mkexpr(addr) ) );
+ delta += alen+1;
+ DIP( "vdpps $%d,%s,%s,%s\n",
+ imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG) );
+ }
+
+ IRTemp src_vec = newTemp(Ity_V256);
+ assign(src_vec, getYMMReg( rV ));
+ IRTemp s0, s1, d0, d1;
+ s0 = s1 = d0 = d1 = IRTemp_INVALID;
+ breakupV256toV128s( dst_vec, &d1, &d0 );
+ breakupV256toV128s( src_vec, &s1, &s0 );
+ putYMMReg( rG, binop( Iop_V128HLtoV256,
+ mkexpr( math_DPPS_128(s1, d1, imm8) ),
+ mkexpr( math_DPPS_128(s0, d0, imm8) ) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x41:
+ /* VDPPD imm8, xmm3/m128,xmm2,xmm1 = VEX.NDS.128.66.0F3A.WIG 41 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+ IRTemp dst_vec = newTemp(Ity_V128);
+ Int imm8;
+ if (epartIsReg( modrm )) {
+ UInt rE = eregOfRexRM(pfx,modrm);
+ imm8 = (Int)getUChar(delta+1);
+ assign( dst_vec, getXMMReg( rE ) );
+ delta += 1+1;
+ DIP( "vdppd $%d,%s,%s,%s\n",
+ imm8, nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ imm8 = (Int)getUChar(delta+alen);
+ assign( dst_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ delta += alen+1;
+ DIP( "vdppd $%d,%s,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG) );
+ }
+
+ IRTemp src_vec = newTemp(Ity_V128);
+ assign(src_vec, getXMMReg( rV ));
+ IRTemp res_vec = math_DPPD_128( src_vec, dst_vec, imm8 );
+ putYMMRegLoAndZU( rG, mkexpr(res_vec) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x42:
+ /* VMPSADBW imm8, xmm3/m128,xmm2,xmm1 */
+ /* VMPSADBW = VEX.NDS.128.66.0F3A.WIG 42 /r ib */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ Int imm8;
+ IRTemp src_vec = newTemp(Ity_V128);
+ IRTemp dst_vec = newTemp(Ity_V128);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+
+ assign( dst_vec, getXMMReg(rV) );
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+
+ imm8 = (Int)getUChar(delta+1);
+ assign( src_vec, getXMMReg(rE) );
+ delta += 1+1;
+ DIP( "vmpsadbw $%d, %s,%s,%s\n", imm8,
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ assign( src_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "vmpsadbw $%d, %s,%s,%s\n", imm8,
+ dis_buf, nameXMMReg(rV), nameXMMReg(rG) );
+ }
+
+ putYMMRegLoAndZU( rG, mkexpr( math_MPSADBW_128(dst_vec,
+ src_vec, imm8) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x44:
+ /* VPCLMULQDQ imm8, xmm3/m128,xmm2,xmm1 */
+ /* VPCLMULQDQ = VEX.NDS.128.66.0F3A.WIG 44 /r ib */
+ /* 66 0F 3A 44 /r ib = PCLMULQDQ xmm1, xmm2/m128, imm8
+ * Carry-less multiplication of selected XMM quadwords into XMM
+ * registers (a.k.a multiplication of polynomials over GF(2))
+ */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ UChar modrm = getUChar(delta);
+ Int imm8;
+ IRTemp sV = newTemp(Ity_V128);
+ IRTemp dV = newTemp(Ity_V128);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ UInt rV = getVexNvvvv(pfx);
+
+ assign( dV, getXMMReg(rV) );
+
+ if ( epartIsReg( modrm ) ) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ imm8 = (Int)getUChar(delta+1);
+ assign( sV, getXMMReg(rE) );
+ delta += 1+1;
+ DIP( "vpclmulqdq $%d, %s,%s,%s\n", imm8,
+ nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta, dis_buf,
+ 1/* imm8 is 1 byte after the amode */ );
+ assign( sV, loadLE( Ity_V128, mkexpr(addr) ) );
+ imm8 = (Int)getUChar(delta+alen);
+ delta += alen+1;
+ DIP( "vpclmulqdq $%d, %s,%s,%s\n",
+ imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG) );
+ }
+
+ putYMMRegLoAndZU( rG, mkexpr( math_PCLMULQDQ(dV, sV, imm8) ) );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x4A:
+ /* VBLENDVPS xmmG, xmmE/memE, xmmV, xmmIS4
+ ::: xmmG:V128 = PBLEND(xmmE, xmmV, xmmIS4) (RMVR) */
+ /* VBLENDVPS = VEX.NDS.128.66.0F3A.WIG 4A /r /is4 */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VBLENDV_128 ( vbi, pfx, delta,
+ "vblendvps", 4, Iop_SarN32x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VBLENDVPS ymmG, ymmE/memE, ymmV, ymmIS4
+ ::: ymmG:V256 = PBLEND(ymmE, ymmV, ymmIS4) (RMVR) */
+ /* VBLENDVPS = VEX.NDS.256.66.0F3A.WIG 4A /r /is4 */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VBLENDV_256 ( vbi, pfx, delta,
+ "vblendvps", 4, Iop_SarN32x4 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x4B:
+ /* VBLENDVPD xmmG, xmmE/memE, xmmV, xmmIS4
+ ::: xmmG:V128 = PBLEND(xmmE, xmmV, xmmIS4) (RMVR) */
+ /* VBLENDVPD = VEX.NDS.128.66.0F3A.WIG 4B /r /is4 */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VBLENDV_128 ( vbi, pfx, delta,
+ "vblendvpd", 8, Iop_SarN64x2 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ /* VBLENDVPD ymmG, ymmE/memE, ymmV, ymmIS4
+ ::: ymmG:V256 = PBLEND(ymmE, ymmV, ymmIS4) (RMVR) */
+ /* VBLENDVPD = VEX.NDS.256.66.0F3A.WIG 4B /r /is4 */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VBLENDV_256 ( vbi, pfx, delta,
+ "vblendvpd", 8, Iop_SarN64x2 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x4C:
+ /* VPBLENDVB xmmG, xmmE/memE, xmmV, xmmIS4
+ ::: xmmG:V128 = PBLEND(xmmE, xmmV, xmmIS4) (RMVR) */
+ /* VPBLENDVB = VEX.NDS.128.66.0F3A.WIG 4C /r /is4 */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_VBLENDV_128 ( vbi, pfx, delta,
+ "vpblendvb", 1, Iop_SarN8x16 );
+ *uses_vvvv = True;
+ goto decode_success;
+ }
+ break;
+
+ case 0x60:
+ case 0x61:
+ case 0x62:
+ case 0x63:
+ /* VEX.128.66.0F3A.WIG 63 /r ib = VPCMPISTRI imm8, xmm2/m128, xmm1
+ VEX.128.66.0F3A.WIG 62 /r ib = VPCMPISTRM imm8, xmm2/m128, xmm1
+ VEX.128.66.0F3A.WIG 61 /r ib = VPCMPESTRI imm8, xmm2/m128, xmm1
+ VEX.128.66.0F3A.WIG 60 /r ib = VPCMPESTRM imm8, xmm2/m128, xmm1
+ (selected special cases that actually occur in glibc,
+ not by any means a complete implementation.)
+ */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ Long delta0 = delta;
+ delta = dis_PCMPxSTRx( vbi, pfx, delta, True/*isAvx*/, opc );
+ if (delta > delta0) goto decode_success;
+ /* else fall though; dis_PCMPxSTRx failed to decode it */
+ }
+ break;
+
+ case 0xDF:
+ /* VAESKEYGENASSIST imm8, xmm2/m128, xmm1 = VEX.128.66.0F3A.WIG DF /r */
+ if (have66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AESKEYGENASSIST( vbi, pfx, delta, True/*!isAvx*/ );
+ goto decode_success;
+ }
+ break;
+
+ default:
+ break;
+
+ }
+
+ //decode_failure:
+ return deltaIN;
+
+ decode_success:
+ return delta;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- Disassemble a single instruction ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+/* Disassemble a single instruction into IR. The instruction is
+ located in host memory at &guest_code[delta]. */
+
+static
+DisResult disInstr_AMD64_WRK (
+ /*OUT*/Bool* expect_CAS,
+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ Long delta64,
+ VexArchInfo* archinfo,
+ VexAbiInfo* vbi
+ )
+{
+ IRTemp t1, t2, t3, t4, t5, t6;
+ UChar pre;
+ Int n, n_prefixes;
+ DisResult dres;
+
+ /* The running delta */
+ Long delta = delta64;
+
+ /* Holds eip at the start of the insn, so that we can print
+ consistent error messages for unimplemented insns. */
+ Long delta_start = delta;
+
+ /* sz denotes the nominal data-op size of the insn; we change it to
+ 2 if an 0x66 prefix is seen and 8 if REX.W is 1. In case of
+ conflict REX.W takes precedence. */
+ Int sz = 4;
+
+ /* pfx holds the summary of prefixes. */
+ Prefix pfx = PFX_EMPTY;
+
+ /* Holds the computed opcode-escape indication. */
+ Escape esc = ESC_NONE;
+
+ /* Set result defaults. */
+ dres.whatNext = Dis_Continue;
+ dres.len = 0;
+ dres.continueAt = 0;
+ dres.jk_StopHere = Ijk_INVALID;
+ *expect_CAS = False;
+
+ vassert(guest_RIP_next_assumed == 0);
+ vassert(guest_RIP_next_mustcheck == False);
+
+ t1 = t2 = t3 = t4 = t5 = t6 = IRTemp_INVALID;
+
+ DIP("\t0x%llx: ", guest_RIP_bbstart+delta);
+
+ /* Spot "Special" instructions (see comment at top of file). */
+ {
+ UChar* code = (UChar*)(guest_code + delta);
+ /* Spot the 16-byte preamble:
+ 48C1C703 rolq $3, %rdi
+ 48C1C70D rolq $13, %rdi
+ 48C1C73D rolq $61, %rdi
+ 48C1C733 rolq $51, %rdi
+ */
+ if (code[ 0] == 0x48 && code[ 1] == 0xC1 && code[ 2] == 0xC7
+ && code[ 3] == 0x03 &&
+ code[ 4] == 0x48 && code[ 5] == 0xC1 && code[ 6] == 0xC7
+ && code[ 7] == 0x0D &&
+ code[ 8] == 0x48 && code[ 9] == 0xC1 && code[10] == 0xC7
+ && code[11] == 0x3D &&
+ code[12] == 0x48 && code[13] == 0xC1 && code[14] == 0xC7
+ && code[15] == 0x33) {
+ /* Got a "Special" instruction preamble. Which one is it? */
+ if (code[16] == 0x48 && code[17] == 0x87
+ && code[18] == 0xDB /* xchgq %rbx,%rbx */) {
+ /* %RDX = client_request ( %RAX ) */
+ DIP("%%rdx = client_request ( %%rax )\n");
+ delta += 19;
+ jmp_lit(&dres, Ijk_ClientReq, guest_RIP_bbstart+delta);
+ vassert(dres.whatNext == Dis_StopHere);
+ goto decode_success;
+ }
+ else
+ if (code[16] == 0x48 && code[17] == 0x87
+ && code[18] == 0xC9 /* xchgq %rcx,%rcx */) {
+ /* %RAX = guest_NRADDR */
+ DIP("%%rax = guest_NRADDR\n");
+ delta += 19;
+ putIRegRAX(8, IRExpr_Get( OFFB_NRADDR, Ity_I64 ));
+ goto decode_success;
+ }
+ else
+ if (code[16] == 0x48 && code[17] == 0x87
+ && code[18] == 0xD2 /* xchgq %rdx,%rdx */) {
+ /* call-noredir *%RAX */
+ DIP("call-noredir *%%rax\n");
+ delta += 19;
+ t1 = newTemp(Ity_I64);
+ assign(t1, getIRegRAX(8));
+ t2 = newTemp(Ity_I64);
+ assign(t2, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8)));
+ putIReg64(R_RSP, mkexpr(t2));
+ storeLE( mkexpr(t2), mkU64(guest_RIP_bbstart+delta));
+ jmp_treg(&dres, Ijk_NoRedir, t1);
+ vassert(dres.whatNext == Dis_StopHere);
+ goto decode_success;
+ }
+ /* We don't know what it is. */
+ goto decode_failure;
+ /*NOTREACHED*/
+ }
+ }
+
+ /* Eat prefixes, summarising the result in pfx and sz, and rejecting
+ as many invalid combinations as possible. */
+ n_prefixes = 0;
+ while (True) {
+ if (n_prefixes > 7) goto decode_failure;
+ pre = getUChar(delta);
+ switch (pre) {
+ case 0x66: pfx |= PFX_66; break;
+ case 0x67: pfx |= PFX_ASO; break;
+ case 0xF2: pfx |= PFX_F2; break;
+ case 0xF3: pfx |= PFX_F3; break;
+ case 0xF0: pfx |= PFX_LOCK; *expect_CAS = True; break;
+ case 0x2E: pfx |= PFX_CS; break;
+ case 0x3E: pfx |= PFX_DS; break;
+ case 0x26: pfx |= PFX_ES; break;
+ case 0x64: pfx |= PFX_FS; break;
+ case 0x65: pfx |= PFX_GS; break;
+ case 0x36: pfx |= PFX_SS; break;
+ case 0x40 ... 0x4F:
+ pfx |= PFX_REX;
+ if (pre & (1<<3)) pfx |= PFX_REXW;
+ if (pre & (1<<2)) pfx |= PFX_REXR;
+ if (pre & (1<<1)) pfx |= PFX_REXX;
+ if (pre & (1<<0)) pfx |= PFX_REXB;
+ break;
+ default:
+ goto not_a_legacy_prefix;
+ }
+ n_prefixes++;
+ delta++;
+ }
+
+ not_a_legacy_prefix:
+ /* We've used up all the non-VEX prefixes. Parse and validate a
+ VEX prefix if that's appropriate. */
+ if (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX) {
+ /* Used temporarily for holding VEX prefixes. */
+ UChar vex0 = getUChar(delta);
+ if (vex0 == 0xC4) {
+ /* 3-byte VEX */
+ UChar vex1 = getUChar(delta+1);
+ UChar vex2 = getUChar(delta+2);
+ delta += 3;
+ pfx |= PFX_VEX;
+ /* Snarf contents of byte 1 */
+ /* R */ pfx |= (vex1 & (1<<7)) ? 0 : PFX_REXR;
+ /* X */ pfx |= (vex1 & (1<<6)) ? 0 : PFX_REXX;
+ /* B */ pfx |= (vex1 & (1<<5)) ? 0 : PFX_REXB;
+ /* m-mmmm */
+ switch (vex1 & 0x1F) {
+ case 1: esc = ESC_0F; break;
+ case 2: esc = ESC_0F38; break;
+ case 3: esc = ESC_0F3A; break;
+ /* Any other m-mmmm field will #UD */
+ default: goto decode_failure;
+ }
+ /* Snarf contents of byte 2 */
+ /* W */ pfx |= (vex2 & (1<<7)) ? PFX_REXW : 0;
+ /* ~v3 */ pfx |= (vex2 & (1<<6)) ? 0 : PFX_VEXnV3;
+ /* ~v2 */ pfx |= (vex2 & (1<<5)) ? 0 : PFX_VEXnV2;
+ /* ~v1 */ pfx |= (vex2 & (1<<4)) ? 0 : PFX_VEXnV1;
+ /* ~v0 */ pfx |= (vex2 & (1<<3)) ? 0 : PFX_VEXnV0;
+ /* L */ pfx |= (vex2 & (1<<2)) ? PFX_VEXL : 0;
+ /* pp */
+ switch (vex2 & 3) {
+ case 0: break;
+ case 1: pfx |= PFX_66; break;
+ case 2: pfx |= PFX_F3; break;
+ case 3: pfx |= PFX_F2; break;
+ default: vassert(0);
+ }
+ }
+ else if (vex0 == 0xC5) {
+ /* 2-byte VEX */
+ UChar vex1 = getUChar(delta+1);
+ delta += 2;
+ pfx |= PFX_VEX;
+ /* Snarf contents of byte 1 */
+ /* R */ pfx |= (vex1 & (1<<7)) ? 0 : PFX_REXR;
+ /* ~v3 */ pfx |= (vex1 & (1<<6)) ? 0 : PFX_VEXnV3;
+ /* ~v2 */ pfx |= (vex1 & (1<<5)) ? 0 : PFX_VEXnV2;
+ /* ~v1 */ pfx |= (vex1 & (1<<4)) ? 0 : PFX_VEXnV1;
+ /* ~v0 */ pfx |= (vex1 & (1<<3)) ? 0 : PFX_VEXnV0;
+ /* L */ pfx |= (vex1 & (1<<2)) ? PFX_VEXL : 0;
+ /* pp */
+ switch (vex1 & 3) {
+ case 0: break;
+ case 1: pfx |= PFX_66; break;
+ case 2: pfx |= PFX_F3; break;
+ case 3: pfx |= PFX_F2; break;
+ default: vassert(0);
+ }
+ /* implied: */
+ esc = ESC_0F;
+ }
+ /* Can't have both VEX and REX */
+ if ((pfx & PFX_VEX) && (pfx & PFX_REX))
+ goto decode_failure; /* can't have both */
+ }
+
+ /* Dump invalid combinations */
+ n = 0;
+ if (pfx & PFX_F2) n++;
+ if (pfx & PFX_F3) n++;
+ if (n > 1)
+ goto decode_failure; /* can't have both */
+
+ n = 0;
+ if (pfx & PFX_CS) n++;
+ if (pfx & PFX_DS) n++;
+ if (pfx & PFX_ES) n++;
+ if (pfx & PFX_FS) n++;
+ if (pfx & PFX_GS) n++;
+ if (pfx & PFX_SS) n++;
+ if (n > 1)
+ goto decode_failure; /* multiple seg overrides == illegal */
+
+ /* We have a %fs prefix. Reject it if there's no evidence in 'vbi'
+ that we should accept it. */
+ if ((pfx & PFX_FS) && !vbi->guest_amd64_assume_fs_is_zero)
+ goto decode_failure;
+
+ /* Ditto for %gs prefixes. */
+ if ((pfx & PFX_GS) && !vbi->guest_amd64_assume_gs_is_0x60)
+ goto decode_failure;
+
+ /* Set up sz. */
+ sz = 4;
+ if (pfx & PFX_66) sz = 2;
+ if ((pfx & PFX_REX) && (pfx & PFX_REXW)) sz = 8;
+
+ /* Now we should be looking at the primary opcode byte or the
+ leading escapes. Check that any LOCK prefix is actually
+ allowed. */
+ if (pfx & PFX_LOCK) {
+ if (can_be_used_with_LOCK_prefix( (UChar*)&guest_code[delta] )) {
+ DIP("lock ");
+ } else {
+ *expect_CAS = False;
+ goto decode_failure;
+ }
+ }
+
+ /* Eat up opcode escape bytes, until we're really looking at the
+ primary opcode byte. But only if there's no VEX present. */
+ if (!(pfx & PFX_VEX)) {
+ vassert(esc == ESC_NONE);
+ pre = getUChar(delta);
+ if (pre == 0x0F) {
+ delta++;
+ pre = getUChar(delta);
+ switch (pre) {
+ case 0x38: esc = ESC_0F38; delta++; break;
+ case 0x3A: esc = ESC_0F3A; delta++; break;
+ default: esc = ESC_0F; break;
+ }
+ }
+ }
+
+ /* So now we're really really looking at the primary opcode
+ byte. */
+ Long delta_at_primary_opcode = delta;
+
+ if (!(pfx & PFX_VEX)) {
+ /* Handle non-VEX prefixed instructions. "Legacy" (non-VEX) SSE
+ instructions preserve the upper 128 bits of YMM registers;
+ iow we can simply ignore the presence of the upper halves of
+ these registers. */
+ switch (esc) {
+ case ESC_NONE:
+ delta = dis_ESC_NONE( &dres, expect_CAS,
+ resteerOkFn, resteerCisOk, callback_opaque,
+ archinfo, vbi, pfx, sz, delta );
+ break;
+ case ESC_0F:
+ delta = dis_ESC_0F ( &dres, expect_CAS,
+ resteerOkFn, resteerCisOk, callback_opaque,
+ archinfo, vbi, pfx, sz, delta );
+ break;
+ case ESC_0F38:
+ delta = dis_ESC_0F38( &dres,
+ resteerOkFn, resteerCisOk, callback_opaque,
+ archinfo, vbi, pfx, sz, delta );
+ break;
+ case ESC_0F3A:
+ delta = dis_ESC_0F3A( &dres,
+ resteerOkFn, resteerCisOk, callback_opaque,
+ archinfo, vbi, pfx, sz, delta );
+ break;
+ default:
+ vassert(0);
+ }
+ } else {
+ /* VEX prefixed instruction */
+ /* Sloppy Intel wording: "An instruction encoded with a VEX.128
+ prefix that loads a YMM register operand ..." zeroes out bits
+ 128 and above of the register. */
+ Bool uses_vvvv = False;
+ switch (esc) {
+ case ESC_0F:
+ delta = dis_ESC_0F__VEX ( &dres, &uses_vvvv,
+ resteerOkFn, resteerCisOk,
+ callback_opaque,
+ archinfo, vbi, pfx, sz, delta );
+ break;
+ case ESC_0F38:
+ delta = dis_ESC_0F38__VEX ( &dres, &uses_vvvv,
+ resteerOkFn, resteerCisOk,
+ callback_opaque,
+ archinfo, vbi, pfx, sz, delta );
+ break;
+ case ESC_0F3A:
+ delta = dis_ESC_0F3A__VEX ( &dres, &uses_vvvv,
+ resteerOkFn, resteerCisOk,
+ callback_opaque,
+ archinfo, vbi, pfx, sz, delta );
+ break;
+ case ESC_NONE:
+ /* The presence of a VEX prefix, by Intel definition,
+ always implies at least an 0F escape. */
+ goto decode_failure;
+ default:
+ vassert(0);
+ }
+ /* If the insn doesn't use VEX.vvvv then it must be all ones.
+ Check this. */
+ if (!uses_vvvv) {
+ if (getVexNvvvv(pfx) != 0)
+ goto decode_failure;
+ }
+ }
+
+ vassert(delta - delta_at_primary_opcode >= 0);
+ vassert(delta - delta_at_primary_opcode < 16/*let's say*/);
+
+ /* Use delta == delta_at_primary_opcode to denote decode failure.
+ This implies that any successful decode must use at least one
+ byte up. */
+ if (delta == delta_at_primary_opcode)
+ goto decode_failure;
+ else
+ goto decode_success; /* \o/ */
+
+#if 0 /* XYZZY */
+
+ /* ---------------------------------------------------- */
+ /* --- The SSE/SSE2 decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* What did I do to deserve SSE ? Perhaps I was really bad in a
+ previous life? */
+
+ /* Note, this doesn't handle SSE3 right now. All amd64s support
+ SSE2 as a minimum so there is no point distinguishing SSE1 vs
+ SSE2. */
+
+ insn = (UChar*)&guest_code[delta];
+
+ /* FXSAVE is spuriously at the start here only because it is
+ thusly placed in guest-x86/toIR.c. */
+
+ /* ------ SSE decoder main ------ */
+
+ /* ---------------------------------------------------- */
+ /* --- end of the SSE decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* ---------------------------------------------------- */
+ /* --- start of the SSE2 decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* ---------------------------------------------------- */
+ /* --- end of the SSE/SSE2 decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* ---------------------------------------------------- */
+ /* --- start of the SSE3 decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* ---------------------------------------------------- */
+ /* --- end of the SSE3 decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* ---------------------------------------------------- */
+ /* --- start of the SSSE3 decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* ---------------------------------------------------- */
+ /* --- end of the SSSE3 decoder. --- */
+ /* ---------------------------------------------------- */
+
+ /* ---------------------------------------------------- */
+ /* --- start of the SSE4 decoder --- */
+ /* ---------------------------------------------------- */
+
+ /* ---------------------------------------------------- */
+ /* --- end of the SSE4 decoder --- */
+ /* ---------------------------------------------------- */
+
+ /*after_sse_decoders:*/
+
+ /* Get the primary opcode. */
+ opc = getUChar(delta); delta++;
+
+ /* We get here if the current insn isn't SSE, or this CPU doesn't
+ support SSE. */
+
+ switch (opc) {
+
+ /* ------------------------ Control flow --------------- */
+
+ /* ------------------------ CWD/CDQ -------------------- */
+
+ /* ------------------------ FPU ops -------------------- */
+
+ /* ------------------------ INT ------------------------ */
+
+ case 0xCD: { /* INT imm8 */
+ IRJumpKind jk = Ijk_Boring;
+ if (have66orF2orF3(pfx)) goto decode_failure;
+ d64 = getUChar(delta); delta++;
+ switch (d64) {
+ case 32: jk = Ijk_Sys_int32; break;
+ default: goto decode_failure;
+ }
+ guest_RIP_next_mustcheck = True;
+ guest_RIP_next_assumed = guest_RIP_bbstart + delta;
+ jmp_lit(jk, guest_RIP_next_assumed);
+ /* It's important that all ArchRegs carry their up-to-date value
+ at this point. So we declare an end-of-block here, which
+ forces any TempRegs caching ArchRegs to be flushed. */
+ vassert(dres.whatNext == Dis_StopHere);
+ DIP("int $0x%02x\n", (UInt)d64);
+ break;
+ }
+
+ /* ------------------------ Jcond, byte offset --------- */
+
+ /* ------------------------ IMUL ----------------------- */
+
+ /* ------------------------ MOV ------------------------ */
+
+ /* ------------------------ MOVx ------------------------ */
+
+ /* ------------------------ opl imm, A ----------------- */
+
+ /* ------------------------ opl Ev, Gv ----------------- */
+
+ /* ------------------------ opl Gv, Ev ----------------- */
+
+ /* ------------------------ POP ------------------------ */
+
+ /* ------------------------ PUSH ----------------------- */
+
+ /* ------ AE: SCAS variants ------ */
+
+ /* ------ A6, A7: CMPS variants ------ */
+
+ /* ------ AA, AB: STOS variants ------ */
+
+ /* ------ A4, A5: MOVS variants ------ */
+
+ /* ------------------------ XCHG ----------------------- */
+
+ /* ------------------------ IN / OUT ----------------------- */
+
+ /* ------------------------ (Grp1 extensions) ---------- */
+
+ /* ------------------------ (Grp2 extensions) ---------- */
+
+ /* ------------------------ (Grp3 extensions) ---------- */
+
+ /* ------------------------ (Grp4 extensions) ---------- */
+
+ /* ------------------------ (Grp5 extensions) ---------- */
+
+ /* ------------------------ Escapes to 2-byte opcodes -- */
+
+ case 0x0F: {
+ opc = getUChar(delta); delta++;
+ switch (opc) {
+
+ /* =-=-=-=-=-=-=-=-=- Grp8 =-=-=-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- BSF/BSR -=-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- BSWAP -=-=-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- CMPXCHG -=-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- CPUID -=-=-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- MOVZX, MOVSX =-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- MUL/IMUL =-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- NOPs =-=-=-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- Jcond d32 -=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- PREFETCH =-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- SETcc Eb =-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- SHLD/SHRD -=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- SYSCALL -=-=-=-=-=-=-=-=-=-= */
+
+ /* =-=-=-=-=-=-=-=-=- XADD -=-=-=-=-=-=-=-=-=-= */
+
+ case 0xC0: { /* XADD Gb,Eb */
+ Bool decode_OK = False;
+ delta = dis_xadd_G_E ( &decode_OK, vbi, pfx, 1, delta );
+ if (!decode_OK)
+ goto decode_failure;
break;
}
+ /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */
+
/* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */
default:
@@ -18723,8 +26990,9 @@
} /* case 0x0F: of primary opcode */
/* ------------------------ ??? ------------------------ */
+#endif /* XYZZY */
- default:
+ //default:
decode_failure:
/* All decode failures end up here. */
vex_printf("vex amd64->IR: unhandled instruction bytes: "
@@ -18737,6 +27005,19 @@
(Int)getUChar(delta_start+5),
(Int)getUChar(delta_start+6),
(Int)getUChar(delta_start+7) );
+ vex_printf("vex amd64->IR: REX=%d REX.W=%d REX.R=%d REX.X=%d REX.B=%d\n",
+ haveREX(pfx) ? 1 : 0, getRexW(pfx), getRexR(pfx),
+ getRexX(pfx), getRexB(pfx));
+ vex_printf("vex amd64->IR: VEX=%d VEX.L=%d VEX.nVVVV=0x%x ESC=%s\n",
+ haveVEX(pfx) ? 1 : 0, getVexL(pfx),
+ getVexNvvvv(pfx),
+ esc==ESC_NONE ? "NONE" :
+ esc==ESC_0F ? "0F" :
+ esc==ESC_0F38 ? "0F38" :
+ esc==ESC_0F3A ? "0F3A" : "???");
+ vex_printf("vex amd64->IR: PFX.66=%d PFX.F2=%d PFX.F3=%d\n",
+ have66(pfx) ? 1 : 0, haveF2(pfx) ? 1 : 0,
+ haveF3(pfx) ? 1 : 0);
/* Tell the dispatcher that this insn cannot be decoded, and so has
not been executed, and (is currently) the next to be executed.
@@ -18744,9 +27025,9 @@
insn, but nevertheless be paranoid and update it again right
now. */
stmt( IRStmt_Put( OFFB_RIP, mkU64(guest_RIP_curr_instr) ) );
- jmp_lit(Ijk_NoDecode, guest_RIP_curr_instr);
- dres.whatNext = Dis_StopHere;
- dres.len = 0;
+ jmp_lit(&dres, Ijk_NoDecode, guest_RIP_curr_instr);
+ vassert(dres.whatNext == Dis_StopHere);
+ dres.len = 0;
/* We also need to say that a CAS is not expected now, regardless
of what it might have been set to at the start of the function,
since the IR that we've emitted just above (to synthesis a
@@ -18755,10 +27036,24 @@
*expect_CAS = False;
return dres;
- } /* switch (opc) for the main (primary) opcode switch. */
+ // } /* switch (opc) for the main (primary) opcode switch. */
decode_success:
/* All decode successes end up here. */
+ switch (dres.whatNext) {
+ case Dis_Continue:
+ stmt( IRStmt_Put( OFFB_RIP, mkU64(guest_RIP_bbstart + delta) ) );
+ break;
+ case Dis_ResteerU:
+ case Dis_ResteerC:
+ stmt( IRStmt_Put( OFFB_RIP, mkU64(dres.continueAt) ) );
+ break;
+ case Dis_StopHere:
+ break;
+ default:
+ vassert(0);
+ }
+
DIP("\n");
dres.len = (Int)toUInt(delta - delta_start);
return dres;
@@ -18776,7 +27071,6 @@
is located in host memory at &guest_code[delta]. */
DisResult disInstr_AMD64 ( IRSB* irsb_IN,
- Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -18806,7 +27100,7 @@
x1 = irsb_IN->stmts_used;
expect_CAS = False;
- dres = disInstr_AMD64_WRK ( &expect_CAS, put_IP, resteerOkFn,
+ dres = disInstr_AMD64_WRK ( &expect_CAS, resteerOkFn,
resteerCisOk,
callback_opaque,
delta, archinfo, abiinfo );
@@ -18839,7 +27133,7 @@
/* inconsistency detected. re-disassemble the instruction so as
to generate a useful error message; then assert. */
vex_traceflags |= VEX_TRACE_FE;
- dres = disInstr_AMD64_WRK ( &expect_CAS, put_IP, resteerOkFn,
+ dres = disInstr_AMD64_WRK ( &expect_CAS, resteerOkFn,
resteerCisOk,
callback_opaque,
delta, archinfo, abiinfo );
diff --git a/main/VEX/priv/guest_arm_defs.h b/main/VEX/priv/guest_arm_defs.h
index be6dd1c..14a4cb8 100644
--- a/main/VEX/priv/guest_arm_defs.h
+++ b/main/VEX/priv/guest_arm_defs.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -41,7 +41,6 @@
bb_to_IR.h. */
extern
DisResult disInstr_ARM ( IRSB* irbb,
- Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -157,7 +156,7 @@
OP DEP1 DEP2 DEP3
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- OP_COPY current NZCV unused unused
+ OP_COPY curr_NZCV:28x0 unused unused
OP_ADD argL argR unused
OP_SUB argL argR unused
OP_ADC argL argR 31x0:old_C
diff --git a/main/VEX/priv/guest_arm_helpers.c b/main/VEX/priv/guest_arm_helpers.c
index 90ec93f..d31e64a 100644
--- a/main/VEX/priv/guest_arm_helpers.c
+++ b/main/VEX/priv/guest_arm_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -643,6 +643,12 @@
return unop(Iop_1Uto32,
binop(Iop_CmpLE32U, cc_dep1, cc_dep2));
}
+ if (isU32(cond_n_op, (ARMCondHI << 4) | ARMG_CC_OP_SUB)) {
+ /* HI after SUB --> test argL >u argR
+ --> test argR <u argL */
+ return unop(Iop_1Uto32,
+ binop(Iop_CmpLT32U, cc_dep2, cc_dep1));
+ }
/*---------------- SBB ----------------*/
@@ -691,6 +697,18 @@
mkU32(1)));
}
+ /*---------------- COPY ----------------*/
+
+ if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_COPY)) {
+ /* NE after COPY --> ((cc_dep1 >> ARMG_CC_SHIFT_Z) ^ 1) & 1 */
+ return binop(Iop_And32,
+ binop(Iop_Xor32,
+ binop(Iop_Shr32, cc_dep1,
+ mkU8(ARMG_CC_SHIFT_Z)),
+ mkU32(1)),
+ mkU32(1));
+ }
+
/*----------------- AL -----------------*/
/* A critically important case for Thumb code.
@@ -931,6 +949,9 @@
/* VISIBLE TO LIBVEX CLIENT */
void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state )
{
+ vex_state->host_EvC_FAILADDR = 0;
+ vex_state->host_EvC_COUNTER = 0;
+
vex_state->guest_R0 = 0;
vex_state->guest_R1 = 0;
vex_state->guest_R2 = 0;
@@ -1010,6 +1031,8 @@
vex_state->padding1 = 0;
vex_state->padding2 = 0;
vex_state->padding3 = 0;
+ vex_state->padding4 = 0;
+ vex_state->padding5 = 0;
}
diff --git a/main/VEX/priv/guest_arm_toIR.c b/main/VEX/priv/guest_arm_toIR.c
index d6be839..22aa3db 100644
--- a/main/VEX/priv/guest_arm_toIR.c
+++ b/main/VEX/priv/guest_arm_toIR.c
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
NEON support is
- Copyright (C) 2010-2011 Samsung Electronics
+ Copyright (C) 2010-2012 Samsung Electronics
contributed by Dmitry Zhurikhin <zhur@ispras.ru>
and Kirill Batuzov <batuzovk@ispras.ru>
@@ -1398,7 +1398,8 @@
stmt( IRStmt_Exit(
unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))),
Ijk_Boring,
- IRConst_U32(toUInt(guest_R15_curr_instr_notENC + 4))
+ IRConst_U32(toUInt(guest_R15_curr_instr_notENC + 4)),
+ OFFB_R15T
));
}
@@ -1414,7 +1415,8 @@
stmt( IRStmt_Exit(
unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))),
Ijk_Boring,
- IRConst_U32(toUInt((guest_R15_curr_instr_notENC + 2) | 1))
+ IRConst_U32(toUInt((guest_R15_curr_instr_notENC + 2) | 1)),
+ OFFB_R15T
));
}
@@ -1431,7 +1433,8 @@
stmt( IRStmt_Exit(
unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))),
Ijk_Boring,
- IRConst_U32(toUInt((guest_R15_curr_instr_notENC + 4) | 1))
+ IRConst_U32(toUInt((guest_R15_curr_instr_notENC + 4) | 1)),
+ OFFB_R15T
));
}
@@ -1448,7 +1451,8 @@
IRStmt_Exit(
binop(Iop_CmpNE32, mkexpr(t), mkU32(0)),
Ijk_NoDecode,
- IRConst_U32(toUInt(guest_R15_curr_instr_notENC | 1))
+ IRConst_U32(toUInt(guest_R15_curr_instr_notENC | 1)),
+ OFFB_R15T
)
);
}
@@ -1683,6 +1687,21 @@
mkU8(31) );
}
+/* Similarly .. also from HD p27 .. */
+static
+IRExpr* signed_overflow_after_Sub32 ( IRExpr* resE,
+ IRTemp argL, IRTemp argR )
+{
+ IRTemp res = newTemp(Ity_I32);
+ assign(res, resE);
+ return
+ binop( Iop_Shr32,
+ binop( Iop_And32,
+ binop( Iop_Xor32, mkexpr(argL), mkexpr(argR) ),
+ binop( Iop_Xor32, mkexpr(res), mkexpr(argL) )),
+ mkU8(31) );
+}
+
/*------------------------------------------------------------*/
/*--- Larger helpers ---*/
@@ -9337,6 +9356,51 @@
/* fall through */
}
+ /* ----------------- uhadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFA9 && (INSNT1(15,0) & 0xF0F0) == 0xF060) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,0,0,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HAdd16Ux2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uhadd16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
/* ----------------- shadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
{
UInt regD = 99, regN = 99, regM = 99;
@@ -10206,6 +10270,406 @@
/* fall through */
}
+ /* ------------------ qadd<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF080) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,0,0,1,0,0,0,0) &&
+ INSNA(11,8) == BITS4(0,0,0,0) &&
+ INSNA(7,4) == BITS4(0,1,0,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_QAdd32S, mkexpr(rMt), mkexpr(rNt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ or_into_QFLAG32(
+ signed_overflow_after_Add32(
+ binop(Iop_Add32, mkexpr(rMt), mkexpr(rNt)), rMt, rNt),
+ condT
+ );
+
+ DIP("qadd%s r%u, r%u, r%u\n", nCC(conq),regD,regM,regN);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ------------------ qdadd<c> <Rd>,<Rm>,<Rn> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF090) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,0,0,1,0,1,0,0) &&
+ INSNA(11,8) == BITS4(0,0,0,0) &&
+ INSNA(7,4) == BITS4(0,1,0,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp rN_d = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ or_into_QFLAG32(
+ signed_overflow_after_Add32(
+ binop(Iop_Add32, mkexpr(rNt), mkexpr(rNt)), rNt, rNt),
+ condT
+ );
+
+ assign(rN_d, binop(Iop_QAdd32S, mkexpr(rNt), mkexpr(rNt)));
+ assign(res_q, binop(Iop_QAdd32S, mkexpr(rMt), mkexpr(rN_d)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ or_into_QFLAG32(
+ signed_overflow_after_Add32(
+ binop(Iop_Add32, mkexpr(rMt), mkexpr(rN_d)), rMt, rN_d),
+ condT
+ );
+
+ DIP("qdadd%s r%u, r%u, r%u\n", nCC(conq),regD,regM,regN);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ------------------ qsub<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF0A0) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,0,0,1,0,0,1,0) &&
+ INSNA(11,8) == BITS4(0,0,0,0) &&
+ INSNA(7,4) == BITS4(0,1,0,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_QSub32S, mkexpr(rMt), mkexpr(rNt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ or_into_QFLAG32(
+ signed_overflow_after_Sub32(
+ binop(Iop_Sub32, mkexpr(rMt), mkexpr(rNt)), rMt, rNt),
+ condT
+ );
+
+ DIP("qsub%s r%u, r%u, r%u\n", nCC(conq),regD,regM,regN);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ------------------ qdsub<c> <Rd>,<Rm>,<Rn> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFA8 && (INSNT1(15,0) & 0xF0F0) == 0xF0B0) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,0,0,1,0,1,1,0) &&
+ INSNA(11,8) == BITS4(0,0,0,0) &&
+ INSNA(7,4) == BITS4(0,1,0,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp rN_d = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ or_into_QFLAG32(
+ signed_overflow_after_Add32(
+ binop(Iop_Add32, mkexpr(rNt), mkexpr(rNt)), rNt, rNt),
+ condT
+ );
+
+ assign(rN_d, binop(Iop_QAdd32S, mkexpr(rNt), mkexpr(rNt)));
+ assign(res_q, binop(Iop_QSub32S, mkexpr(rMt), mkexpr(rN_d)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ or_into_QFLAG32(
+ signed_overflow_after_Sub32(
+ binop(Iop_Sub32, mkexpr(rMt), mkexpr(rN_d)), rMt, rN_d),
+ condT
+ );
+
+ DIP("qdsub%s r%u, r%u, r%u\n", nCC(conq),regD,regM,regN);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ------------------ uqsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF050) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,0) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,1,1,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_QSub16Ux2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uqsub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ----------------- shadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFA9 && (INSNT1(15,0) & 0xF0F0) == 0xF020) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,0,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,0,0,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HAdd16Sx2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("shadd16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ----------------- uhsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFAC && (INSNT1(15,0) & 0xF0F0) == 0xF060) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(1,1,1,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HSub8Ux4, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uhsub8%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
+ /* ----------------- uhsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
+ {
+ UInt regD = 99, regN = 99, regM = 99;
+ Bool gate = False;
+
+ if (isT) {
+ if (INSNT0(15,4) == 0xFAD && (INSNT1(15,0) & 0xF0F0) == 0xF060) {
+ regN = INSNT0(3,0);
+ regD = INSNT1(11,8);
+ regM = INSNT1(3,0);
+ if (!isBadRegT(regD) && !isBadRegT(regN) && !isBadRegT(regM))
+ gate = True;
+ }
+ } else {
+ if (INSNA(27,20) == BITS8(0,1,1,0,0,1,1,1) &&
+ INSNA(11,8) == BITS4(1,1,1,1) &&
+ INSNA(7,4) == BITS4(0,1,1,1)) {
+ regD = INSNA(15,12);
+ regN = INSNA(19,16);
+ regM = INSNA(3,0);
+ if (regD != 15 && regN != 15 && regM != 15)
+ gate = True;
+ }
+ }
+
+ if (gate) {
+ IRTemp rNt = newTemp(Ity_I32);
+ IRTemp rMt = newTemp(Ity_I32);
+ IRTemp res_q = newTemp(Ity_I32);
+
+ assign( rNt, isT ? getIRegT(regN) : getIRegA(regN) );
+ assign( rMt, isT ? getIRegT(regM) : getIRegA(regM) );
+
+ assign(res_q, binop(Iop_HSub16Ux2, mkexpr(rNt), mkexpr(rMt)));
+ if (isT)
+ putIRegT( regD, mkexpr(res_q), condT );
+ else
+ putIRegA( regD, mkexpr(res_q), condT, Ijk_Boring );
+
+ DIP("uhsub16%s r%u, r%u, r%u\n", nCC(conq),regD,regN,regM);
+ return True;
+ }
+ /* fall through */
+ }
+
/* ---------- Doesn't match anything. ---------- */
return False;
@@ -11863,6 +12327,61 @@
goto decode_success_vfp;
}
+ /* --------------- VCVT fixed<->floating, VFP --------------- */
+ /* 31 27 23 19 15 11 7 3
+ 28 24 20 16 12 8 4 0
+
+ cond 1110 1D11 1p1U Vd 101f x1i0 imm4
+
+ VCVT<c>.<Td>.F64 <Dd>, <Dd>, #fbits
+ VCVT<c>.<Td>.F32 <Dd>, <Dd>, #fbits
+ VCVT<c>.F64.<Td> <Dd>, <Dd>, #fbits
+ VCVT<c>.F32.<Td> <Dd>, <Dd>, #fbits
+ are of this form. We only handle a subset of the cases though.
+ */
+ if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+ && BITS4(1,0,1,0) == (INSN(19,16) & BITS4(1,0,1,0))
+ && BITS3(1,0,1) == INSN(11,9)
+ && BITS3(1,0,0) == (INSN(6,4) & BITS3(1,0,1))) {
+ UInt bD = INSN(22,22);
+ UInt bOP = INSN(18,18);
+ UInt bU = INSN(16,16);
+ UInt Vd = INSN(15,12);
+ UInt bSF = INSN(8,8);
+ UInt bSX = INSN(7,7);
+ UInt bI = INSN(5,5);
+ UInt imm4 = INSN(3,0);
+ Bool to_fixed = bOP == 1;
+ Bool dp_op = bSF == 1;
+ Bool unsyned = bU == 1;
+ UInt size = bSX == 0 ? 16 : 32;
+ Int frac_bits = size - ((imm4 << 1) | bI);
+ UInt d = dp_op ? ((bD << 4) | Vd) : ((Vd << 1) | bD);
+ if (frac_bits >= 1 && frac_bits <= 32 && !to_fixed && !dp_op && size == 32) {
+ /* VCVT.F32.{S,U}32 S[d], S[d], #frac_bits */
+ /* This generates really horrible code. We could potentially
+ do much better. */
+ IRTemp rmode = newTemp(Ity_I32);
+ assign(rmode, mkU32(Irrm_NEAREST)); // rmode that this insn is defd to use
+ IRTemp src32 = newTemp(Ity_I32);
+ assign(src32, unop(Iop_ReinterpF32asI32, getFReg(d)));
+ IRExpr* as_F64 = unop( unsyned ? Iop_I32UtoF64 : Iop_I32StoF64,
+ mkexpr(src32 ) );
+ IRTemp scale = newTemp(Ity_F64);
+ assign(scale, unop(Iop_I32UtoF64, mkU32( 1 << (frac_bits-1) )));
+ IRExpr* rm = mkU32(Irrm_NEAREST);
+ IRExpr* resF64 = triop(Iop_DivF64,
+ rm, as_F64,
+ triop(Iop_AddF64, rm, mkexpr(scale), mkexpr(scale)));
+ IRExpr* resF32 = binop(Iop_F64toF32, mkexpr(rmode), resF64);
+ putFReg(d, resF32, condT);
+ DIP("vcvt.f32.%c32, s%u, s%u, #%d\n",
+ unsyned ? 'u' : 's', d, d, frac_bits);
+ goto decode_success_vfp;
+ }
+ /* fall through */
+ }
+
/* FAILURE */
return False;
@@ -11962,9 +12481,9 @@
UInt dst = guest_R15_curr_instr_notENC + 8 + (simm24 | 1);
putIRegA( 14, mkU32(guest_R15_curr_instr_notENC + 4),
IRTemp_INVALID/*because AL*/, Ijk_Boring );
- irsb->next = mkU32(dst);
- irsb->jumpkind = Ijk_Call;
- dres->whatNext = Dis_StopHere;
+ llPutIReg(15, mkU32(dst));
+ dres->jk_StopHere = Ijk_Call;
+ dres->whatNext = Dis_StopHere;
DIP("blx 0x%x (and switch to Thumb mode)\n", dst - 1);
return True;
}
@@ -12040,7 +12559,6 @@
static
DisResult disInstr_ARM_WRK (
- Bool put_IP,
Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -12066,9 +12584,10 @@
// etc etc
/* Set result defaults. */
- dres.whatNext = Dis_Continue;
- dres.len = 4;
- dres.continueAt = 0;
+ dres.whatNext = Dis_Continue;
+ dres.len = 4;
+ dres.continueAt = 0;
+ dres.jk_StopHere = Ijk_INVALID;
/* Set default actions for post-insn handling of writes to r15, if
required. */
@@ -12085,11 +12604,7 @@
DIP("\t(arm) 0x%x: ", (UInt)guest_R15_curr_instr_notENC);
- /* We may be asked to update the guest R15 before going further. */
vassert(0 == (guest_R15_curr_instr_notENC & 3));
- if (put_IP) {
- llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC) );
- }
/* ----------------------------------------------------------- */
@@ -12116,9 +12631,9 @@
/* orr r10,r10,r10 */) {
/* R3 = client_request ( R4 ) */
DIP("r3 = client_request ( %%r4 )\n");
- irsb->next = mkU32( guest_R15_curr_instr_notENC + 20 );
- irsb->jumpkind = Ijk_ClientReq;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkU32( guest_R15_curr_instr_notENC + 20 ));
+ dres.jk_StopHere = Ijk_ClientReq;
+ dres.whatNext = Dis_StopHere;
goto decode_success;
}
else
@@ -12136,9 +12651,9 @@
/* branch-and-link-to-noredir R4 */
DIP("branch-and-link-to-noredir r4\n");
llPutIReg(14, mkU32( guest_R15_curr_instr_notENC + 20) );
- irsb->next = llGetIReg(4);
- irsb->jumpkind = Ijk_NoRedir;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, llGetIReg(4));
+ dres.jk_StopHere = Ijk_NoRedir;
+ dres.whatNext = Dis_StopHere;
goto decode_success;
}
/* We don't know what it is. Set opc1/opc2 so decode_failure
@@ -12977,9 +13492,9 @@
dres.continueAt = (Addr64)dst;
} else {
/* no; terminate the SB at this point. */
- irsb->next = mkU32(dst);
- irsb->jumpkind = jk;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkU32(dst));
+ dres.jk_StopHere = jk;
+ dres.whatNext = Dis_StopHere;
}
DIP("b%s 0x%x\n", link ? "l" : "", dst);
} else {
@@ -13002,7 +13517,8 @@
stmt( IRStmt_Exit( unop(Iop_Not1,
unop(Iop_32to1, mkexpr(condT))),
Ijk_Boring,
- IRConst_U32(guest_R15_curr_instr_notENC+4) ));
+ IRConst_U32(guest_R15_curr_instr_notENC+4),
+ OFFB_R15T ));
dres.whatNext = Dis_ResteerC;
dres.continueAt = (Addr64)(Addr32)dst;
comment = "(assumed taken)";
@@ -13021,7 +13537,8 @@
following this one. */
stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(condT)),
Ijk_Boring,
- IRConst_U32(dst) ));
+ IRConst_U32(dst),
+ OFFB_R15T ));
dres.whatNext = Dis_ResteerC;
dres.continueAt = (Addr64)(Addr32)
(guest_R15_curr_instr_notENC+4);
@@ -13031,10 +13548,10 @@
/* Conservative default translation - end the block at
this point. */
stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(condT)),
- jk, IRConst_U32(dst) ));
- irsb->next = mkU32(guest_R15_curr_instr_notENC + 4);
- irsb->jumpkind = Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ jk, IRConst_U32(dst), OFFB_R15T ));
+ llPutIReg(15, mkU32(guest_R15_curr_instr_notENC + 4));
+ dres.jk_StopHere = Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
}
DIP("b%s%s 0x%x %s\n", link ? "l" : "", nCC(INSN_COND),
dst, comment);
@@ -13065,10 +13582,10 @@
putIRegA( 14, mkU32(guest_R15_curr_instr_notENC + 4),
IRTemp_INVALID/*because AL*/, Ijk_Boring );
}
- irsb->next = mkexpr(dst);
- irsb->jumpkind = link ? Ijk_Call
- : (rM == 14 ? Ijk_Ret : Ijk_Boring);
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkexpr(dst));
+ dres.jk_StopHere = link ? Ijk_Call
+ : (rM == 14 ? Ijk_Ret : Ijk_Boring);
+ dres.whatNext = Dis_StopHere;
if (condT == IRTemp_INVALID) {
DIP("b%sx r%u\n", link ? "l" : "", rM);
} else {
@@ -13363,9 +13880,9 @@
mk_skip_over_A32_if_cond_is_false( condT );
}
// AL after here
- irsb->next = mkU32( guest_R15_curr_instr_notENC + 4 );
- irsb->jumpkind = Ijk_Sys_syscall;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkU32( guest_R15_curr_instr_notENC + 4 ));
+ dres.jk_StopHere = Ijk_Sys_syscall;
+ dres.whatNext = Dis_StopHere;
DIP("svc%s #0x%08x\n", nCC(INSN_COND), imm24);
goto decode_success;
}
@@ -13415,7 +13932,8 @@
}
stmt( IRStmt_Exit(unop(Iop_Not1, mkexpr(tSC1)),
/*Ijk_NoRedir*/Ijk_Boring,
- IRConst_U32(guest_R15_curr_instr_notENC)) );
+ IRConst_U32(guest_R15_curr_instr_notENC),
+ OFFB_R15T ));
putIRegA(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld),
IRTemp_INVALID, Ijk_Boring);
DIP("swp%s%s r%u, r%u, [r%u]\n",
@@ -14051,29 +14569,37 @@
means we don't know which they are, so the back end has to
re-emit them all when it comes acrosss an IR Fence.
*/
- if (0xEE070F9A == (insn & 0xFFFF0FFF)) { /* v6 */
- /* mcr 15, 0, r0, c7, c10, 4 (v6) equiv to DSB (v7). Data
- Synch Barrier -- ensures completion of memory accesses. */
- stmt( IRStmt_MBE(Imbe_Fence) );
- DIP("mcr 15, 0, rX, c7, c10, 4 (data synch barrier)\n");
- goto decode_success;
+ /* v6 */ /* mcr 15, 0, rT, c7, c10, 5 */
+ if (0xEE070FBA == (insn & 0xFFFF0FFF)) {
+ UInt rT = INSN(15,12);
+ if (rT <= 14) {
+ /* mcr 15, 0, rT, c7, c10, 5 (v6) equiv to DMB (v7). Data
+ Memory Barrier -- ensures ordering of memory accesses. */
+ stmt( IRStmt_MBE(Imbe_Fence) );
+ DIP("mcr 15, 0, r%u, c7, c10, 5 (data memory barrier)\n", rT);
+ goto decode_success;
+ }
+ /* fall through */
}
- if (0xEE070FBA == (insn & 0xFFFF0FFF)) { /* v6 */
- /* mcr 15, 0, r0, c7, c10, 5 (v6) equiv to DMB (v7). Data
- Memory Barrier -- ensures ordering of memory accesses. */
- stmt( IRStmt_MBE(Imbe_Fence) );
- DIP("mcr 15, 0, rX, c7, c10, 5 (data memory barrier)\n");
- goto decode_success;
- }
- if (0xEE070F95 == (insn & 0xFFFF0FFF)) { /* v6 */
- /* mcr 15, 0, r0, c7, c5, 4 (v6) equiv to ISB (v7).
- Instruction Synchronisation Barrier (or Flush Prefetch
- Buffer) -- a pipe flush, I think. I suspect we could
- ignore those, but to be on the safe side emit a fence
- anyway. */
- stmt( IRStmt_MBE(Imbe_Fence) );
- DIP("mcr 15, 0, rX, c7, c5, 4 (insn synch barrier)\n");
- goto decode_success;
+ /* other flavours of barrier */
+ switch (insn) {
+ case 0xEE070F9A: /* v6 */
+ /* mcr 15, 0, r0, c7, c10, 4 (v6) equiv to DSB (v7). Data
+ Synch Barrier -- ensures completion of memory accesses. */
+ stmt( IRStmt_MBE(Imbe_Fence) );
+ DIP("mcr 15, 0, r0, c7, c10, 4 (data synch barrier)\n");
+ goto decode_success;
+ case 0xEE070F95: /* v6 */
+ /* mcr 15, 0, r0, c7, c5, 4 (v6) equiv to ISB (v7).
+ Instruction Synchronisation Barrier (or Flush Prefetch
+ Buffer) -- a pipe flush, I think. I suspect we could
+ ignore those, but to be on the safe side emit a fence
+ anyway. */
+ stmt( IRStmt_MBE(Imbe_Fence) );
+ DIP("mcr 15, 0, r0, c7, c5, 4 (insn synch barrier)\n");
+ goto decode_success;
+ default:
+ break;
}
/* ----------------------------------------------------------- */
@@ -14134,10 +14660,9 @@
now. */
vassert(0 == (guest_R15_curr_instr_notENC & 3));
llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC) );
- irsb->next = mkU32(guest_R15_curr_instr_notENC);
- irsb->jumpkind = Ijk_NoDecode;
- dres.whatNext = Dis_StopHere;
- dres.len = 0;
+ dres.whatNext = Dis_StopHere;
+ dres.jk_StopHere = Ijk_NoDecode;
+ dres.len = 0;
return dres;
decode_success:
@@ -14178,12 +14703,31 @@
binop(Iop_Xor32,
mkexpr(r15guard), mkU32(1))),
r15kind,
- IRConst_U32(guest_R15_curr_instr_notENC + 4)
+ IRConst_U32(guest_R15_curr_instr_notENC + 4),
+ OFFB_R15T
));
}
- irsb->next = llGetIReg(15);
- irsb->jumpkind = r15kind;
- dres.whatNext = Dis_StopHere;
+ /* This seems crazy, but we're required to finish the insn with
+ a write to the guest PC. As usual we rely on ir_opt to tidy
+ up later. */
+ llPutIReg(15, llGetIReg(15));
+ dres.whatNext = Dis_StopHere;
+ dres.jk_StopHere = r15kind;
+ } else {
+ /* Set up the end-state in the normal way. */
+ switch (dres.whatNext) {
+ case Dis_Continue:
+ llPutIReg(15, mkU32(dres.len + guest_R15_curr_instr_notENC));
+ break;
+ case Dis_ResteerU:
+ case Dis_ResteerC:
+ llPutIReg(15, mkU32(dres.continueAt));
+ break;
+ case Dis_StopHere:
+ break;
+ default:
+ vassert(0);
+ }
}
return dres;
@@ -14211,7 +14755,6 @@
static
DisResult disInstr_THUMB_WRK (
- Bool put_IP,
Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -14227,7 +14770,8 @@
# define INSN0(_bMax,_bMin) SLICE_UInt(((UInt)insn0), (_bMax), (_bMin))
DisResult dres;
- UShort insn0; /* first 16 bits of the insn */
+ UShort insn0; /* first 16 bits of the insn */
+ UShort insn1; /* second 16 bits of the insn */
//Bool allow_VFP = False;
//UInt hwcaps = archinfo->hwcaps;
HChar dis_buf[128]; // big enough to hold LDMIA etc text
@@ -14241,9 +14785,10 @@
// etc etc
/* Set result defaults. */
- dres.whatNext = Dis_Continue;
- dres.len = 2;
- dres.continueAt = 0;
+ dres.whatNext = Dis_Continue;
+ dres.len = 2;
+ dres.continueAt = 0;
+ dres.jk_StopHere = Ijk_INVALID;
/* Set default actions for post-insn handling of writes to r15, if
required. */
@@ -14257,16 +14802,16 @@
unlikely, but ..) if the second 16 bits aren't actually
necessary. */
insn0 = getUShortLittleEndianly( guest_instr );
+ insn1 = 0; /* We'll get it later, once we know we need it. */
+
+ /* Similarly, will set this later. */
+ IRTemp old_itstate = IRTemp_INVALID;
if (0) vex_printf("insn: 0x%x\n", insn0);
DIP("\t(thumb) 0x%x: ", (UInt)guest_R15_curr_instr_notENC);
- /* We may be asked to update the guest R15 before going further. */
vassert(0 == (guest_R15_curr_instr_notENC & 1));
- if (put_IP) {
- llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC | 1) );
- }
/* ----------------------------------------------------------- */
/* Spot "Special" instructions (see comment at top of file). */
@@ -14293,9 +14838,9 @@
/* orr.w r10,r10,r10 */) {
/* R3 = client_request ( R4 ) */
DIP("r3 = client_request ( %%r4 )\n");
- irsb->next = mkU32( (guest_R15_curr_instr_notENC + 20) | 1 );
- irsb->jumpkind = Ijk_ClientReq;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkU32( (guest_R15_curr_instr_notENC + 20) | 1 ));
+ dres.jk_StopHere = Ijk_ClientReq;
+ dres.whatNext = Dis_StopHere;
goto decode_success;
}
else
@@ -14315,9 +14860,9 @@
/* branch-and-link-to-noredir R4 */
DIP("branch-and-link-to-noredir r4\n");
llPutIReg(14, mkU32( (guest_R15_curr_instr_notENC + 20) | 1 ));
- irsb->next = getIRegT(4);
- irsb->jumpkind = Ijk_NoRedir;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, getIRegT(4));
+ dres.jk_StopHere = Ijk_NoRedir;
+ dres.whatNext = Dis_StopHere;
goto decode_success;
}
/* We don't know what it is. Set insn0 so decode_failure
@@ -14440,10 +14985,11 @@
that through the full preamble (which completely disappears). */
IRTemp condT = IRTemp_INVALID;
- IRTemp old_itstate = IRTemp_INVALID;
- IRTemp new_itstate = IRTemp_INVALID;
IRTemp cond_AND_notInIT_T = IRTemp_INVALID;
+ IRTemp new_itstate = IRTemp_INVALID;
+ vassert(old_itstate == IRTemp_INVALID);
+
if (guaranteedUnconditional) {
/* BEGIN "partial eval { ITSTATE = 0; STANDARD_PREAMBLE; }" */
@@ -14974,9 +15520,9 @@
vassert(rM == 15);
assign( dst, mkU32(guest_R15_curr_instr_notENC + 4) );
}
- irsb->next = mkexpr(dst);
- irsb->jumpkind = rM == 14 ? Ijk_Ret : Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkexpr(dst));
+ dres.jk_StopHere = rM == 14 ? Ijk_Ret : Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
DIP("bx r%u (possibly switch to ARM mode)\n", rM);
goto decode_success;
}
@@ -14998,9 +15544,9 @@
assign( dst, getIRegT(rM) );
putIRegT( 14, mkU32( (guest_R15_curr_instr_notENC + 2) | 1 ),
IRTemp_INVALID );
- irsb->next = mkexpr(dst);
- irsb->jumpkind = Ijk_Call;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkexpr(dst));
+ dres.jk_StopHere = Ijk_Call;
+ dres.whatNext = Dis_StopHere;
DIP("blx r%u (possibly switch to ARM mode)\n", rM);
goto decode_success;
}
@@ -15031,9 +15577,9 @@
// stash pseudo-reg, and back up from that if we have to
// restart.
// uncond after here
- irsb->next = mkU32( (guest_R15_curr_instr_notENC + 2) | 1 );
- irsb->jumpkind = Ijk_Sys_syscall;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkU32( (guest_R15_curr_instr_notENC + 2) | 1 ));
+ dres.jk_StopHere = Ijk_Sys_syscall;
+ dres.whatNext = Dis_StopHere;
DIP("svc #0x%08x\n", imm8);
goto decode_success;
}
@@ -15113,9 +15659,9 @@
condT = IRTemp_INVALID;
// now uncond
/* non-interworking branch */
- irsb->next = binop(Iop_Or32, mkexpr(val), mkU32(1));
- irsb->jumpkind = rM == 14 ? Ijk_Ret : Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, binop(Iop_Or32, mkexpr(val), mkU32(1)));
+ dres.jk_StopHere = rM == 14 ? Ijk_Ret : Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
}
DIP("mov r%u, r%u\n", rD, rM);
goto decode_success;
@@ -15170,7 +15716,8 @@
UInt dst = (guest_R15_curr_instr_notENC + 4 + imm32) | 1;
stmt(IRStmt_Exit( mkexpr(kond),
Ijk_Boring,
- IRConst_U32(toUInt(dst)) ));
+ IRConst_U32(toUInt(dst)),
+ OFFB_R15T ));
DIP("cb%s r%u, 0x%x\n", bOP ? "nz" : "z", rN, dst - 1);
goto decode_success;
}
@@ -15198,6 +15745,8 @@
UInt regList = INSN0(7,0);
if (bitR) regList |= (1 << 14);
+ /* At least one register must be transferred, else result is
+ UNPREDICTABLE. */
if (regList != 0) {
/* Since we can't generate a guaranteed non-trapping IR
sequence, (1) jump over the insn if it is gated false, and
@@ -15212,7 +15761,7 @@
if ((regList & (1 << i)) != 0)
nRegs++;
}
- vassert(nRegs >= 1 && nRegs <= 8);
+ vassert(nRegs >= 1 && nRegs <= 9);
/* Move SP down first of all, so we're "covered". And don't
mess with its alignment. */
@@ -15250,6 +15799,8 @@
UInt bitR = INSN0(8,8);
UInt regList = INSN0(7,0);
+ /* At least one register must be transferred, else result is
+ UNPREDICTABLE. */
if (regList != 0 || bitR) {
/* Since we can't generate a guaranteed non-trapping IR
sequence, (1) jump over the insn if it is gated false, and
@@ -15264,7 +15815,7 @@
if ((regList & (1 << i)) != 0)
nRegs++;
}
- vassert(nRegs >= 0 && nRegs <= 7);
+ vassert(nRegs >= 0 && nRegs <= 8);
vassert(bitR == 0 || bitR == 1);
IRTemp oldSP = newTemp(Ity_I32);
@@ -15314,9 +15865,9 @@
it as is, no need to mess with it. Note, therefore, this
is an interworking return. */
if (bitR) {
- irsb->next = mkexpr(newPC);
- irsb->jumpkind = Ijk_Ret;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkexpr(newPC));
+ dres.jk_StopHere = Ijk_Ret;
+ dres.whatNext = Dis_StopHere;
}
DIP("pop {%s0x%04x}\n", bitR ? "pc," : "", regList & 0xFF);
@@ -15861,9 +16412,9 @@
mk_skip_over_T16_if_cond_is_false(condT);
condT = IRTemp_INVALID;
// now uncond
- irsb->next = mkU32( dst | 1 /*CPSR.T*/ );
- irsb->jumpkind = Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkU32( dst | 1 /*CPSR.T*/ ));
+ dres.jk_StopHere = Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
DIP("b 0x%x\n", dst);
goto decode_success;
}
@@ -15892,11 +16443,12 @@
assign( kondT, mk_armg_calculate_condition(cond) );
stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(kondT)),
Ijk_Boring,
- IRConst_U32(dst | 1/*CPSR.T*/) ));
- irsb->next = mkU32( (guest_R15_curr_instr_notENC + 2)
- | 1 /*CPSR.T*/ );
- irsb->jumpkind = Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ IRConst_U32(dst | 1/*CPSR.T*/),
+ OFFB_R15T ));
+ llPutIReg(15, mkU32( (guest_R15_curr_instr_notENC + 2)
+ | 1 /*CPSR.T*/ ));
+ dres.jk_StopHere = Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
DIP("b%s 0x%x\n", nCC(cond), dst);
goto decode_success;
}
@@ -15925,7 +16477,8 @@
# define INSN1(_bMax,_bMin) SLICE_UInt(((UInt)insn1), (_bMax), (_bMin))
/* second 16 bits of the instruction, if any */
- UShort insn1 = getUShortLittleEndianly( guest_instr+2 );
+ vassert(insn1 == 0);
+ insn1 = getUShortLittleEndianly( guest_instr+2 );
anOp = Iop_INVALID; /* paranoia */
anOpNm = NULL; /* paranoia */
@@ -15936,29 +16489,6 @@
vassert(dres.continueAt == 0);
dres.len = 4;
- /* ------------------- (T1) SMMUL{R} ------------------ */
- if (INSN0(15,7) == BITS9(1,1,1,1,1,0,1,1,0)
- && INSN0(6,4) == BITS3(1,0,1)
- && INSN1(15,12) == BITS4(1,1,1,1)
- && INSN1(7,5) == BITS3(0,0,0)) {
- UInt bitR = INSN1(4,4);
- UInt rD = INSN1(11,8);
- UInt rM = INSN1(3,0);
- UInt rN = INSN0(3,0);
- if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
- IRExpr* res = newTemp(Ity_I32);
- assign(res, unop(Iop_64HIto32,
- binop(Iop_Add64,
- binop(Iop_MullS32, getIRegT(rN), getIRegT(rM)),
- mkU64(bitR ? 0x80000000ULL : 0ULL))));
- putIRegT(rD, mkexpr(res), condT);
- DIP("smmul%s r%u, r%u, r%u\n",
- bitR ? "r" : "", rD, rN, rM);
- goto decode_success;
- }
- }
-
-
/* ---------------- BL/BLX simm26 ---------------- */
if (BITS5(1,1,1,1,0) == INSN0(15,11) && BITS2(1,1) == INSN1(15,14)) {
UInt isBL = INSN1(12,12);
@@ -15997,17 +16527,17 @@
if (isBL) {
/* BL: unconditional T -> T call */
/* we're calling Thumb code, hence "| 1" */
- irsb->next = mkU32( dst | 1 );
+ llPutIReg(15, mkU32( dst | 1 ));
DIP("bl 0x%x (stay in Thumb mode)\n", dst);
} else {
/* BLX: unconditional T -> A call */
/* we're calling ARM code, hence "& 3" to align to a
valid ARM insn address */
- irsb->next = mkU32( dst & ~3 );
+ llPutIReg(15, mkU32( dst & ~3 ));
DIP("blx 0x%x (switch to ARM mode)\n", dst & ~3);
}
- irsb->jumpkind = Ijk_Call;
- dres.whatNext = Dis_StopHere;
+ dres.whatNext = Dis_StopHere;
+ dres.jk_StopHere = Ijk_Call;
goto decode_success;
}
}
@@ -16049,15 +16579,6 @@
if (rN == 15) valid = False;
if (popcount32(regList) < 2) valid = False;
if (bW == 1 && (regList & (1<<rN))) valid = False;
- if (regList & (1<<rN)) {
- UInt i;
- /* if Rn is in the list, then it must be the
- lowest numbered entry */
- for (i = 0; i < rN; i++) {
- if (regList & (1<<i))
- valid = False;
- }
- }
}
if (valid) {
@@ -16072,15 +16593,15 @@
condT = IRTemp_INVALID;
// now uncond
- /* Generate the IR. This might generate a write to R15, */
+ /* Generate the IR. This might generate a write to R15. */
mk_ldm_stm(False/*!arm*/, rN, bINC, bBEFORE, bW, bL, regList);
if (bL == 1 && (regList & (1<<15))) {
// If we wrote to R15, we have an interworking return to
// deal with.
- irsb->next = llGetIReg(15);
- irsb->jumpkind = Ijk_Ret;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, llGetIReg(15));
+ dres.jk_StopHere = Ijk_Ret;
+ dres.whatNext = Dis_StopHere;
}
DIP("%sm%c%c r%u%s, {0x%04x}\n",
@@ -16099,8 +16620,8 @@
UInt rN = INSN0(3,0);
UInt rD = INSN1(11,8);
Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
- /* but allow "add.w reg, sp, #constT" */
- if (!valid && rN == 13 && rD != 15)
+ /* but allow "add.w reg, sp, #constT" for reg != PC */
+ if (!valid && rD <= 14 && rN == 13)
valid = True;
if (valid) {
IRTemp argL = newTemp(Ity_I32);
@@ -16126,8 +16647,8 @@
UInt rN = INSN0(3,0);
UInt rD = INSN1(11,8);
Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
- /* but allow "addw sp, sp, #uimm12" */
- if (!valid && rD == 13 && rN == 13)
+ /* but allow "addw reg, sp, #uimm12" for reg != PC */
+ if (!valid && rD <= 14 && rN == 13)
valid = True;
if (valid) {
IRTemp argL = newTemp(Ity_I32);
@@ -16380,10 +16901,10 @@
UInt how = INSN1(5,4);
Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
- /* but allow "add.w reg, sp, reg w/ no shift
+ /* but allow "add.w reg, sp, reg, lsl #N for N=0,1,2 or 3
(T3) "ADD (SP plus register) */
if (!valid && INSN0(8,5) == BITS4(1,0,0,0) // add
- && rD != 15 && rN == 13 && imm5 == 0 && how == 0) {
+ && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
valid = True;
}
/* also allow "sub.w reg, sp, reg w/ no shift
@@ -16945,18 +17466,19 @@
putIRegT(rT, mkexpr(newRt), IRTemp_INVALID);
}
- if (loadsPC) {
- /* Presumably this is an interworking branch. */
- irsb->next = mkexpr(newRt);
- irsb->jumpkind = Ijk_Boring; /* or _Ret ? */
- dres.whatNext = Dis_StopHere;
- }
-
/* Update Rn if necessary. */
if (bW == 1) {
vassert(rN != rT); // assured by validity check above
putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID);
}
+
+ if (loadsPC) {
+ /* Presumably this is an interworking branch. */
+ vassert(rN != 15); // assured by validity check above
+ llPutIReg(15, mkexpr(newRt));
+ dres.jk_StopHere = Ijk_Boring; /* or _Ret ? */
+ dres.whatNext = Dis_StopHere;
+ }
}
if (bP == 1 && bW == 0) {
@@ -17102,9 +17624,9 @@
if (loadsPC) {
/* Presumably this is an interworking branch. */
- irsb->next = mkexpr(newRt);
- irsb->jumpkind = Ijk_Boring; /* or _Ret ? */
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkexpr(newRt));
+ dres.jk_StopHere = Ijk_Boring; /* or _Ret ? */
+ dres.whatNext = Dis_StopHere;
}
}
@@ -17360,11 +17882,12 @@
assign( kondT, mk_armg_calculate_condition(cond) );
stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(kondT)),
Ijk_Boring,
- IRConst_U32(dst | 1/*CPSR.T*/) ));
- irsb->next = mkU32( (guest_R15_curr_instr_notENC + 4)
- | 1 /*CPSR.T*/ );
- irsb->jumpkind = Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ IRConst_U32(dst | 1/*CPSR.T*/),
+ OFFB_R15T ));
+ llPutIReg(15, mkU32( (guest_R15_curr_instr_notENC + 4)
+ | 1 /*CPSR.T*/ ));
+ dres.jk_StopHere = Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
DIP("b%s.w 0x%x\n", nCC(cond), dst);
goto decode_success;
}
@@ -17405,9 +17928,9 @@
// now uncond
// branch to dst
- irsb->next = mkU32( dst | 1 /*CPSR.T*/ );
- irsb->jumpkind = Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(15, mkU32( dst | 1 /*CPSR.T*/ ));
+ dres.jk_StopHere = Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
DIP("b.w 0x%x\n", dst);
goto decode_success;
}
@@ -17438,16 +17961,17 @@
assign(delta, unop(Iop_8Uto32, loadLE(Ity_I8, ea)));
}
- irsb->next
- = binop(Iop_Or32,
- binop(Iop_Add32,
- getIRegT(15),
- binop(Iop_Shl32, mkexpr(delta), mkU8(1))
- ),
- mkU32(1)
- );
- irsb->jumpkind = Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ llPutIReg(
+ 15,
+ binop(Iop_Or32,
+ binop(Iop_Add32,
+ getIRegT(15),
+ binop(Iop_Shl32, mkexpr(delta), mkU8(1))
+ ),
+ mkU32(1)
+ ));
+ dres.jk_StopHere = Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
DIP("tb%c [r%u, r%u%s]\n",
bH ? 'h' : 'b', rN, rM, bH ? ", LSL #1" : "");
goto decode_success;
@@ -18151,6 +18675,28 @@
goto decode_success;
}
+ /* ------------------- (T1) SMMUL{R} ------------------ */
+ if (INSN0(15,7) == BITS9(1,1,1,1,1,0,1,1,0)
+ && INSN0(6,4) == BITS3(1,0,1)
+ && INSN1(15,12) == BITS4(1,1,1,1)
+ && INSN1(7,5) == BITS3(0,0,0)) {
+ UInt bitR = INSN1(4,4);
+ UInt rD = INSN1(11,8);
+ UInt rM = INSN1(3,0);
+ UInt rN = INSN0(3,0);
+ if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
+ IRExpr* res
+ = unop(Iop_64HIto32,
+ binop(Iop_Add64,
+ binop(Iop_MullS32, getIRegT(rN), getIRegT(rM)),
+ mkU64(bitR ? 0x80000000ULL : 0ULL)));
+ putIRegT(rD, res, condT);
+ DIP("smmul%s r%u, r%u, r%u\n",
+ bitR ? "r" : "", rD, rN, rM);
+ goto decode_success;
+ }
+ }
+
/* ----------------------------------------------------------- */
/* -- VFP (CP 10, CP 11) instructions (in Thumb mode) -- */
/* ----------------------------------------------------------- */
@@ -18206,7 +18752,9 @@
/* Back up ITSTATE to the initial value for this instruction.
If we don't do that, any subsequent restart of the instruction
will restart with the wrong value. */
- put_ITSTATE(old_itstate);
+ if (old_itstate != IRTemp_INVALID)
+ put_ITSTATE(old_itstate);
+
/* Tell the dispatcher that this insn cannot be decoded, and so has
not been executed, and (is currently) the next to be executed.
R15 should be up-to-date since it made so at the start of each
@@ -18214,60 +18762,29 @@
now. */
vassert(0 == (guest_R15_curr_instr_notENC & 1));
llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC | 1) );
- irsb->next = mkU32(guest_R15_curr_instr_notENC | 1 /* CPSR.T */);
- irsb->jumpkind = Ijk_NoDecode;
- dres.whatNext = Dis_StopHere;
- dres.len = 0;
+ dres.whatNext = Dis_StopHere;
+ dres.jk_StopHere = Ijk_NoDecode;
+ dres.len = 0;
return dres;
decode_success:
/* All decode successes end up here. */
- DIP("\n");
-
- vassert(dres.len == 2 || dres.len == 4 || dres.len == 20);
-
-#if 0
- // XXX is this necessary on Thumb?
- /* Now then. Do we have an implicit jump to r15 to deal with? */
- if (r15written) {
- /* If we get jump to deal with, we assume that there's been no
- other competing branch stuff previously generated for this
- insn. That's reasonable, in the sense that the ARM insn set
- appears to declare as "Unpredictable" any instruction which
- generates more than one possible new value for r15. Hence
- just assert. The decoders themselves should check against
- all such instructions which are thusly Unpredictable, and
- decline to decode them. Hence we should never get here if we
- have competing new values for r15, and hence it is safe to
- assert here. */
- vassert(dres.whatNext == Dis_Continue);
- vassert(irsb->next == NULL);
- vassert(irsb->jumpkind == Ijk_Boring);
- /* If r15 is unconditionally written, terminate the block by
- jumping to it. If it's conditionally written, still
- terminate the block (a shame, but we can't do side exits to
- arbitrary destinations), but first jump to the next
- instruction if the condition doesn't hold. */
- /* We can't use getIRegT(15) to get the destination, since that
- will produce r15+4, which isn't what we want. Must use
- llGetIReg(15) instead. */
- if (r15guard == IRTemp_INVALID) {
- /* unconditional */
- } else {
- /* conditional */
- stmt( IRStmt_Exit(
- unop(Iop_32to1,
- binop(Iop_Xor32,
- mkexpr(r15guard), mkU32(1))),
- r15kind,
- IRConst_U32(guest_R15_curr_instr_notENC + 4)
- ));
- }
- irsb->next = llGetIReg(15);
- irsb->jumpkind = r15kind;
- dres.whatNext = Dis_StopHere;
+ vassert(dres.len == 4 || dres.len == 2 || dres.len == 20);
+ switch (dres.whatNext) {
+ case Dis_Continue:
+ llPutIReg(15, mkU32(dres.len + (guest_R15_curr_instr_notENC | 1)));
+ break;
+ case Dis_ResteerU:
+ case Dis_ResteerC:
+ llPutIReg(15, mkU32(dres.continueAt));
+ break;
+ case Dis_StopHere:
+ break;
+ default:
+ vassert(0);
}
-#endif
+
+ DIP("\n");
return dres;
@@ -18366,7 +18883,6 @@
is located in host memory at &guest_code[delta]. */
DisResult disInstr_ARM ( IRSB* irsb_IN,
- Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -18395,12 +18911,12 @@
}
if (isThumb) {
- dres = disInstr_THUMB_WRK ( put_IP, resteerOkFn,
+ dres = disInstr_THUMB_WRK ( resteerOkFn,
resteerCisOk, callback_opaque,
&guest_code_IN[delta_ENCODED - 1],
archinfo, abiinfo );
} else {
- dres = disInstr_ARM_WRK ( put_IP, resteerOkFn,
+ dres = disInstr_ARM_WRK ( resteerOkFn,
resteerCisOk, callback_opaque,
&guest_code_IN[delta_ENCODED],
archinfo, abiinfo );
diff --git a/main/VEX/priv/guest_generic_bb_to_IR.c b/main/VEX/priv/guest_generic_bb_to_IR.c
index 32dca8c..6896556 100644
--- a/main/VEX/priv/guest_generic_bb_to_IR.c
+++ b/main/VEX/priv/guest_generic_bb_to_IR.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -140,9 +140,47 @@
(In fact it's a VgInstrumentClosure.)
*/
+/* Regarding IP updating. dis_instr_fn (that does the guest specific
+ work of disassembling an individual instruction) must finish the
+ resulting IR with "PUT(guest_IP) = ". Hence in all cases it must
+ state the next instruction address.
+
+ If the block is to be ended at that point, then this routine
+ (bb_to_IR) will set up the next/jumpkind/offsIP fields so as to
+ make a transfer (of the right kind) to "GET(guest_IP)". Hence if
+ dis_instr_fn generates incorrect IP updates we will see it
+ immediately (due to jumping to the wrong next guest address).
+
+ However it is also necessary to set this up so it can be optimised
+ nicely. The IRSB exit is defined to update the guest IP, so that
+ chaining works -- since the chain_me stubs expect the chain-to
+ address to be in the guest state. Hence what the IRSB next fields
+ will contain initially is (implicitly)
+
+ PUT(guest_IP) [implicitly] = GET(guest_IP) [explicit expr on ::next]
+
+ which looks pretty strange at first. Eg so unconditional branch
+ to some address 0x123456 looks like this:
+
+ PUT(guest_IP) = 0x123456; // dis_instr_fn generates this
+ // the exit
+ PUT(guest_IP) [implicitly] = GET(guest_IP); exit-Boring
+
+ after redundant-GET and -PUT removal by iropt, we get what we want:
+
+ // the exit
+ PUT(guest_IP) [implicitly] = 0x123456; exit-Boring
+
+ This makes the IRSB-end case the same as the side-exit case: update
+ IP, then transfer. There is no redundancy of representation for
+ the destination, and we use the destination specified by
+ dis_instr_fn, so any errors it makes show up sooner.
+*/
+
IRSB* bb_to_IR (
/*OUT*/VexGuestExtents* vge,
/*OUT*/UInt* n_sc_extents,
+ /*OUT*/UInt* n_guest_instrs, /* stats only */
/*IN*/ void* callback_opaque,
/*IN*/ DisOneInstrFn dis_instr_fn,
/*IN*/ UChar* guest_code,
@@ -155,13 +193,15 @@
/*IN*/ IRType guest_word_type,
/*IN*/ UInt (*needs_self_check)(void*,VexGuestExtents*),
/*IN*/ Bool (*preamble_function)(void*,IRSB*),
- /*IN*/ Int offB_TISTART,
- /*IN*/ Int offB_TILEN
+ /*IN*/ Int offB_GUEST_TISTART,
+ /*IN*/ Int offB_GUEST_TILEN,
+ /*IN*/ Int offB_GUEST_IP,
+ /*IN*/ Int szB_GUEST_IP
)
{
Long delta;
Int i, n_instrs, first_stmt_idx;
- Bool resteerOK, need_to_put_IP, debug_print;
+ Bool resteerOK, debug_print;
DisResult dres;
IRStmt* imark;
IRStmt* nop;
@@ -185,6 +225,14 @@
vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns);
vassert(guest_word_type == Ity_I32 || guest_word_type == Ity_I64);
+ if (guest_word_type == Ity_I32) {
+ vassert(szB_GUEST_IP == 4);
+ vassert((offB_GUEST_IP % 4) == 0);
+ } else {
+ vassert(szB_GUEST_IP == 8);
+ vassert((offB_GUEST_IP % 8) == 0);
+ }
+
/* Start a new, empty extent. */
vge->n_used = 1;
vge->base[0] = guest_IP_bbstart;
@@ -198,6 +246,7 @@
so far gone. */
delta = 0;
n_instrs = 0;
+ *n_guest_instrs = 0;
/* Guest addresses as IRConsts. Used in self-checks to specify the
restart-after-discard point. */
@@ -297,13 +346,12 @@
);
}
- /* for the first insn, the dispatch loop will have set
- %IP, but for all the others we have to do it ourselves. */
- need_to_put_IP = toBool(n_instrs > 0);
+ if (debug_print && n_instrs > 0)
+ vex_printf("\n");
/* Finally, actually disassemble an instruction. */
+ vassert(irsb->next == NULL);
dres = dis_instr_fn ( irsb,
- need_to_put_IP,
resteerOKfn,
toBool(n_cond_resteers_allowed > 0),
callback_opaque,
@@ -347,18 +395,22 @@
}
}
- /* If dis_instr_fn terminated the BB at this point, check it
- also filled in the irsb->next field. */
- if (dres.whatNext == Dis_StopHere) {
- vassert(irsb->next != NULL);
- if (debug_print) {
- vex_printf(" ");
- vex_printf( "goto {");
- ppIRJumpKind(irsb->jumpkind);
- vex_printf( "} ");
- ppIRExpr( irsb->next );
- vex_printf( "\n");
- }
+ /* Individual insn disassembly may not mess with irsb->next.
+ This function is the only place where it can be set. */
+ vassert(irsb->next == NULL);
+ vassert(irsb->jumpkind == Ijk_Boring);
+ vassert(irsb->offsIP == 0);
+
+ /* Individual insn disassembly must finish the IR for each
+ instruction with an assignment to the guest PC. */
+ vassert(first_stmt_idx < irsb->stmts_used);
+ /* it follows that irsb->stmts_used must be > 0 */
+ { IRStmt* st = irsb->stmts[irsb->stmts_used-1];
+ vassert(st);
+ vassert(st->tag == Ist_Put);
+ vassert(st->Ist.Put.offset == offB_GUEST_IP);
+ /* Really we should also check that the type of the Put'd data
+ == guest_word_type, but that's a bit expensive. */
}
/* Update the VexGuestExtents we are constructing. */
@@ -370,36 +422,38 @@
vge->len[vge->n_used-1]
= toUShort(toUInt( vge->len[vge->n_used-1] + dres.len ));
n_instrs++;
- if (debug_print)
- vex_printf("\n");
/* Advance delta (inconspicuous but very important :-) */
delta += (Long)dres.len;
switch (dres.whatNext) {
case Dis_Continue:
- vassert(irsb->next == NULL);
+ vassert(dres.continueAt == 0);
+ vassert(dres.jk_StopHere == Ijk_INVALID);
if (n_instrs < vex_control.guest_max_insns) {
/* keep going */
} else {
- /* We have to stop. */
- irsb->next
- = IRExpr_Const(
- guest_word_type == Ity_I32
- ? IRConst_U32(toUInt(guest_IP_bbstart+delta))
- : IRConst_U64(guest_IP_bbstart+delta)
- );
+ /* We have to stop. See comment above re irsb field
+ settings here. */
+ irsb->next = IRExpr_Get(offB_GUEST_IP, guest_word_type);
+ /* irsb->jumpkind must already by Ijk_Boring */
+ irsb->offsIP = offB_GUEST_IP;
goto done;
}
break;
case Dis_StopHere:
- vassert(irsb->next != NULL);
+ vassert(dres.continueAt == 0);
+ vassert(dres.jk_StopHere != Ijk_INVALID);
+ /* See comment above re irsb field settings here. */
+ irsb->next = IRExpr_Get(offB_GUEST_IP, guest_word_type);
+ irsb->jumpkind = dres.jk_StopHere;
+ irsb->offsIP = offB_GUEST_IP;
goto done;
+
case Dis_ResteerU:
case Dis_ResteerC:
/* Check that we actually allowed a resteer .. */
vassert(resteerOK);
- vassert(irsb->next == NULL);
if (dres.whatNext == Dis_ResteerC) {
vassert(n_cond_resteers_allowed > 0);
n_cond_resteers_allowed--;
@@ -628,10 +682,10 @@
= IRStmt_WrTmp(tilen_tmp, IRExpr_Const(len2check_IRConst) );
irsb->stmts[selfcheck_idx + i * 5 + 2]
- = IRStmt_Put( offB_TISTART, IRExpr_RdTmp(tistart_tmp) );
+ = IRStmt_Put( offB_GUEST_TISTART, IRExpr_RdTmp(tistart_tmp) );
irsb->stmts[selfcheck_idx + i * 5 + 3]
- = IRStmt_Put( offB_TILEN, IRExpr_RdTmp(tilen_tmp) );
+ = IRStmt_Put( offB_GUEST_TILEN, IRExpr_RdTmp(tilen_tmp) );
/* Generate the entry point descriptors */
if (abiinfo_both->host_ppc_calls_use_fndescrs) {
@@ -685,11 +739,26 @@
/* Where we must restart if there's a failure: at the
first extent, regardless of which extent the
failure actually happened in. */
- guest_IP_bbstart_IRConst
+ guest_IP_bbstart_IRConst,
+ offB_GUEST_IP
);
} /* for (i = 0; i < vge->n_used; i++) */
}
+ /* irsb->next must now be set, since we've finished the block.
+ Print it if necessary.*/
+ vassert(irsb->next != NULL);
+ if (debug_print) {
+ vex_printf(" ");
+ vex_printf( "PUT(%d) = ", irsb->offsIP);
+ ppIRExpr( irsb->next );
+ vex_printf( "; exit-");
+ ppIRJumpKind(irsb->jumpkind);
+ vex_printf( "\n");
+ vex_printf( "\n");
+ }
+
+ *n_guest_instrs = n_instrs;
return irsb;
}
diff --git a/main/VEX/priv/guest_generic_bb_to_IR.h b/main/VEX/priv/guest_generic_bb_to_IR.h
index f623443..6f865c0 100644
--- a/main/VEX/priv/guest_generic_bb_to_IR.h
+++ b/main/VEX/priv/guest_generic_bb_to_IR.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -76,6 +76,13 @@
enum { Dis_StopHere, Dis_Continue,
Dis_ResteerU, Dis_ResteerC } whatNext;
+ /* For Dis_StopHere, we need to end the block and create a
+ transfer to whatever the NIA is. That will have presumably
+ been set by the IR generated for this insn. So we need to
+ know the jump kind to use. Should Ijk_INVALID in other Dis_
+ cases. */
+ IRJumpKind jk_StopHere;
+
/* For Dis_Resteer, this is the guest address we should continue
at. Otherwise ignored (should be zero). */
Addr64 continueAt;
@@ -112,10 +119,6 @@
/* This is the IRSB to which the resulting IR is to be appended. */
/*OUT*/ IRSB* irbb,
- /* Do we need to generate IR to set the guest IP for this insn,
- or not? */
- /*IN*/ Bool put_IP,
-
/* Return True iff resteering to the given addr is allowed (for
branches/calls to destinations that are known at JIT-time) */
/*IN*/ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
@@ -161,6 +164,7 @@
IRSB* bb_to_IR (
/*OUT*/VexGuestExtents* vge,
/*OUT*/UInt* n_sc_extents,
+ /*OUT*/UInt* n_guest_instrs, /* stats only */
/*IN*/ void* callback_opaque,
/*IN*/ DisOneInstrFn dis_instr_fn,
/*IN*/ UChar* guest_code,
@@ -173,8 +177,10 @@
/*IN*/ IRType guest_word_type,
/*IN*/ UInt (*needs_self_check)(void*,VexGuestExtents*),
/*IN*/ Bool (*preamble_function)(void*,IRSB*),
- /*IN*/ Int offB_TISTART,
- /*IN*/ Int offB_TILEN
+ /*IN*/ Int offB_GUEST_TISTART,
+ /*IN*/ Int offB_GUEST_TILEN,
+ /*IN*/ Int offB_GUEST_IP,
+ /*IN*/ Int szB_GUEST_IP
);
diff --git a/main/VEX/priv/guest_generic_x87.c b/main/VEX/priv/guest_generic_x87.c
index 9c683ab..b4ed034 100644
--- a/main/VEX/priv/guest_generic_x87.c
+++ b/main/VEX/priv/guest_generic_x87.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -192,21 +192,21 @@
preserve them. Anyway, here, the NaN's identity is
destroyed. Could be improved. */
if (f64[6] & 8) {
- /* QNaN. Make a QNaN:
- S 1--1 (15) 1 1--1 (63)
+ /* QNaN. Make a canonical QNaN:
+ S 1--1 (15) 1 1 0--0 (62)
*/
f80[9] = toUChar( (sign << 7) | 0x7F );
f80[8] = 0xFF;
- f80[7] = 0xFF;
+ f80[7] = 0xC0;
f80[6] = f80[5] = f80[4] = f80[3]
- = f80[2] = f80[1] = f80[0] = 0xFF;
+ = f80[2] = f80[1] = f80[0] = 0x00;
} else {
/* SNaN. Make a SNaN:
- S 1--1 (15) 0 1--1 (63)
+ S 1--1 (15) 1 0 1--1 (62)
*/
f80[9] = toUChar( (sign << 7) | 0x7F );
f80[8] = 0xFF;
- f80[7] = 0x7F;
+ f80[7] = 0xBF;
f80[6] = f80[5] = f80[4] = f80[3]
= f80[2] = f80[1] = f80[0] = 0xFF;
}
@@ -265,9 +265,9 @@
/* If the exponent is 7FFF, this is either an Infinity, a SNaN or
QNaN, as determined by examining bits 62:0, thus:
- 0 ... 0 Inf
- 0X ... X SNaN
- 1X ... X QNaN
+ 10 ... 0 Inf
+ 10X ... X SNaN
+ 11X ... X QNaN
where at least one of the Xs is not zero.
*/
if (bexp == 0x7FFF) {
@@ -289,19 +289,19 @@
return;
}
/* So it's either a QNaN or SNaN. Distinguish by considering
- bit 62. Note, this destroys all the trailing bits
+ bit 61. Note, this destroys all the trailing bits
(identity?) of the NaN. IEEE754 doesn't require preserving
these (it only requires that there be one QNaN value and one
SNaN value), but x87 does seem to have some ability to
preserve them. Anyway, here, the NaN's identity is
destroyed. Could be improved. */
- if (f80[8] & 0x40) {
- /* QNaN. Make a QNaN:
- S 1--1 (11) 1 1--1 (51)
+ if (f80[7] & 0x40) {
+ /* QNaN. Make a canonical QNaN:
+ S 1--1 (11) 1 0--0 (51)
*/
f64[7] = toUChar((sign << 7) | 0x7F);
- f64[6] = 0xFF;
- f64[5] = f64[4] = f64[3] = f64[2] = f64[1] = f64[0] = 0xFF;
+ f64[6] = 0xF8;
+ f64[5] = f64[4] = f64[3] = f64[2] = f64[1] = f64[0] = 0x00;
} else {
/* SNaN. Make a SNaN:
S 1--1 (11) 0 1--1 (51)
@@ -606,6 +606,18 @@
}
+/* Convert a 2-bit value to a 32-bit value by cloning each bit 16
+ times. There's surely a better way to do this, but I don't know
+ what it is. */
+static UInt bits2_to_bytes4 ( UInt bits2 )
+{
+ UInt r = 0;
+ r |= (bits2 & 1) ? 0x0000FFFF : 0;
+ r |= (bits2 & 2) ? 0xFFFF0000 : 0;
+ return r;
+}
+
+
/* Given partial results from a pcmpXstrX operation (intRes1,
basically), generate an I- or M-format output value, also the new
OSZACP flags. */
@@ -674,8 +686,76 @@
}
+/* Given partial results from a 16-bit pcmpXstrX operation (intRes1,
+ basically), generate an I- or M-format output value, also the new
+ OSZACP flags. */
+static
+void compute_PCMPxSTRx_gen_output_wide (/*OUT*/V128* resV,
+ /*OUT*/UInt* resOSZACP,
+ UInt intRes1,
+ UInt zmaskL, UInt zmaskR,
+ UInt validL,
+ UInt pol, UInt idx,
+ Bool isxSTRM )
+{
+ vassert((pol >> 2) == 0);
+ vassert((idx >> 1) == 0);
+
+ UInt intRes2 = 0;
+ switch (pol) {
+ case 0: intRes2 = intRes1; break; // pol +
+ case 1: intRes2 = ~intRes1; break; // pol -
+ case 2: intRes2 = intRes1; break; // pol m+
+ case 3: intRes2 = intRes1 ^ validL; break; // pol m-
+ }
+ intRes2 &= 0xFF;
+
+ if (isxSTRM) {
+
+ // generate M-format output (a bit or byte mask in XMM0)
+ if (idx) {
+ resV->w32[0] = bits2_to_bytes4( (intRes2 >> 0) & 0x3 );
+ resV->w32[1] = bits2_to_bytes4( (intRes2 >> 2) & 0x3 );
+ resV->w32[2] = bits2_to_bytes4( (intRes2 >> 4) & 0x3 );
+ resV->w32[3] = bits2_to_bytes4( (intRes2 >> 6) & 0x3 );
+ } else {
+ resV->w32[0] = intRes2 & 0xFF;
+ resV->w32[1] = 0;
+ resV->w32[2] = 0;
+ resV->w32[3] = 0;
+ }
+
+ } else {
+
+ // generate I-format output (an index in ECX)
+ // generate ecx value
+ UInt newECX = 0;
+ if (idx) {
+ // index of ms-1-bit
+ newECX = intRes2 == 0 ? 8 : (31 - clz32(intRes2));
+ } else {
+ // index of ls-1-bit
+ newECX = intRes2 == 0 ? 8 : ctz32(intRes2);
+ }
+
+ resV->w32[0] = newECX;
+ resV->w32[1] = 0;
+ resV->w32[2] = 0;
+ resV->w32[3] = 0;
+
+ }
+
+ // generate new flags, common to all ISTRI and ISTRM cases
+ *resOSZACP // A, P are zero
+ = ((intRes2 == 0) ? 0 : MASK_C) // C == 0 iff intRes2 == 0
+ | ((zmaskL == 0) ? 0 : MASK_Z) // Z == 1 iff any in argL is 0
+ | ((zmaskR == 0) ? 0 : MASK_S) // S == 1 iff any in argR is 0
+ | ((intRes2 & 1) << SHIFT_O); // O == IntRes2[0]
+}
+
+
/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M}
- variants.
+ variants on 8-bit data.
For xSTRI variants, the new ECX value is placed in the 32 bits
pointed to by *resV, and the top 96 bits are zeroed. For xSTRM
@@ -718,6 +798,7 @@
case 0x00:
case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
case 0x1A: case 0x38: case 0x3A: case 0x44: case 0x4A:
+ case 0x46:
break;
default:
return False;
@@ -815,9 +896,6 @@
UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
for (hi = 0; hi < 16; hi++) {
- if ((validL & (1 << hi)) == 0)
- // run off the end of the haystack
- break;
UInt m = 1;
for (ni = 0; ni < 16; ni++) {
if ((validR & (1 << ni)) == 0) break;
@@ -826,6 +904,9 @@
if (argL[i] != argR[ni]) { m = 0; break; }
}
boolRes |= (m << hi);
+ if ((validL & (1 << hi)) == 0)
+ // run off the end of the haystack
+ break;
}
// boolRes is "pre-invalidated"
@@ -880,6 +961,256 @@
return True;
}
+ /*----------------------------------------*/
+ /*-- ranges, signed byte data --*/
+ /*----------------------------------------*/
+
+ if (agg == 1/*ranges*/
+ && fmt == 2/*sb*/) {
+
+ /* argL: string, argR: range-pairs */
+ UInt ri, si;
+ Char* argL = (Char*)argLV;
+ Char* argR = (Char*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+ for (si = 0; si < 16; si++) {
+ if ((validL & (1 << si)) == 0)
+ // run off the end of the string
+ break;
+ UInt m = 0;
+ for (ri = 0; ri < 16; ri += 2) {
+ if ((validR & (3 << ri)) != (3 << ri)) break;
+ if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) {
+ m = 1; break;
+ }
+ }
+ boolRes |= (m << si);
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFFFF;
+
+ // generate I-format output
+ compute_PCMPxSTRx_gen_output(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+ );
+
+ return True;
+ }
+
+ return False;
+}
+
+
+/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M}
+ variants on 16-bit characters.
+
+ For xSTRI variants, the new ECX value is placed in the 32 bits
+ pointed to by *resV, and the top 96 bits are zeroed. For xSTRM
+ variants, the result is a 128 bit value and is placed at *resV in
+ the obvious way.
+
+ For all variants, the new OSZACP value is placed at *resOSZACP.
+
+ argLV and argRV are the vector args. The caller must prepare a
+ 8-bit mask for each, zmaskL and zmaskR. For ISTRx variants this
+ must be 1 for each zero byte of of the respective arg. For ESTRx
+ variants this is derived from the explicit length indication, and
+ must be 0 in all places except at the bit index corresponding to
+ the valid length (0 .. 8). If the valid length is 8 then the
+ mask must be all zeroes. In all cases, bits 31:8 must be zero.
+
+ imm8 is the original immediate from the instruction. isSTRM
+ indicates whether this is a xSTRM or xSTRI variant, which controls
+ how much of *res is written.
+
+ If the given imm8 case can be handled, the return value is True.
+ If not, False is returned, and neither *res not *resOSZACP are
+ altered.
+*/
+
+Bool compute_PCMPxSTRx_wide ( /*OUT*/V128* resV,
+ /*OUT*/UInt* resOSZACP,
+ V128* argLV, V128* argRV,
+ UInt zmaskL, UInt zmaskR,
+ UInt imm8, Bool isxSTRM )
+{
+ vassert(imm8 < 0x80);
+ vassert((zmaskL >> 8) == 0);
+ vassert((zmaskR >> 8) == 0);
+
+ /* Explicitly reject any imm8 values that haven't been validated,
+ even if they would probably work. Life is too short to have
+ unvalidated cases in the code base. */
+ switch (imm8) {
+ case 0x01:
+ case 0x03: case 0x09: case 0x0B: case 0x0D: case 0x13:
+ case 0x1B: case 0x39: case 0x3B: case 0x45: case 0x4B:
+ break;
+ default:
+ return False;
+ }
+
+ UInt fmt = (imm8 >> 0) & 3; // imm8[1:0] data format
+ UInt agg = (imm8 >> 2) & 3; // imm8[3:2] aggregation fn
+ UInt pol = (imm8 >> 4) & 3; // imm8[5:4] polarity
+ UInt idx = (imm8 >> 6) & 1; // imm8[6] 1==msb/bytemask
+
+ /*----------------------------------------*/
+ /*-- strcmp on wide data --*/
+ /*----------------------------------------*/
+
+ if (agg == 2/*equal each, aka strcmp*/
+ && (fmt == 1/*uw*/ || fmt == 3/*sw*/)) {
+ Int i;
+ UShort* argL = (UShort*)argLV;
+ UShort* argR = (UShort*)argRV;
+ UInt boolResII = 0;
+ for (i = 7; i >= 0; i--) {
+ UShort cL = argL[i];
+ UShort cR = argR[i];
+ boolResII = (boolResII << 1) | (cL == cR ? 1 : 0);
+ }
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+
+ // do invalidation, common to all equal-each cases
+ UInt intRes1
+ = (boolResII & validL & validR) // if both valid, use cmpres
+ | (~ (validL | validR)); // if both invalid, force 1
+ // else force 0
+ intRes1 &= 0xFF;
+
+ // generate I-format output
+ compute_PCMPxSTRx_gen_output_wide(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+ );
+
+ return True;
+ }
+
+ /*----------------------------------------*/
+ /*-- set membership on wide data --*/
+ /*----------------------------------------*/
+
+ if (agg == 0/*equal any, aka find chars in a set*/
+ && (fmt == 1/*uw*/ || fmt == 3/*sw*/)) {
+ /* argL: the string, argR: charset */
+ UInt si, ci;
+ UShort* argL = (UShort*)argLV;
+ UShort* argR = (UShort*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+
+ for (si = 0; si < 8; si++) {
+ if ((validL & (1 << si)) == 0)
+ // run off the end of the string.
+ break;
+ UInt m = 0;
+ for (ci = 0; ci < 8; ci++) {
+ if ((validR & (1 << ci)) == 0) break;
+ if (argR[ci] == argL[si]) { m = 1; break; }
+ }
+ boolRes |= (m << si);
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFF;
+
+ // generate I-format output
+ compute_PCMPxSTRx_gen_output_wide(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+ );
+
+ return True;
+ }
+
+ /*----------------------------------------*/
+ /*-- substring search on wide data --*/
+ /*----------------------------------------*/
+
+ if (agg == 3/*equal ordered, aka substring search*/
+ && (fmt == 1/*uw*/ || fmt == 3/*sw*/)) {
+
+ /* argL: haystack, argR: needle */
+ UInt ni, hi;
+ UShort* argL = (UShort*)argLV;
+ UShort* argR = (UShort*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+ for (hi = 0; hi < 8; hi++) {
+ UInt m = 1;
+ for (ni = 0; ni < 8; ni++) {
+ if ((validR & (1 << ni)) == 0) break;
+ UInt i = ni + hi;
+ if (i >= 8) break;
+ if (argL[i] != argR[ni]) { m = 0; break; }
+ }
+ boolRes |= (m << hi);
+ if ((validL & (1 << hi)) == 0)
+ // run off the end of the haystack
+ break;
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFF;
+
+ // generate I-format output
+ compute_PCMPxSTRx_gen_output_wide(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+ );
+
+ return True;
+ }
+
+ /*----------------------------------------*/
+ /*-- ranges, unsigned wide data --*/
+ /*----------------------------------------*/
+
+ if (agg == 1/*ranges*/
+ && fmt == 1/*uw*/) {
+
+ /* argL: string, argR: range-pairs */
+ UInt ri, si;
+ UShort* argL = (UShort*)argLV;
+ UShort* argR = (UShort*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+ for (si = 0; si < 8; si++) {
+ if ((validL & (1 << si)) == 0)
+ // run off the end of the string
+ break;
+ UInt m = 0;
+ for (ri = 0; ri < 8; ri += 2) {
+ if ((validR & (3 << ri)) != (3 << ri)) break;
+ if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) {
+ m = 1; break;
+ }
+ }
+ boolRes |= (m << si);
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFF;
+
+ // generate I-format output
+ compute_PCMPxSTRx_gen_output_wide(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+ );
+
+ return True;
+ }
+
return False;
}
diff --git a/main/VEX/priv/guest_generic_x87.h b/main/VEX/priv/guest_generic_x87.h
index 997c2c2..a3dcc4f 100644
--- a/main/VEX/priv/guest_generic_x87.h
+++ b/main/VEX/priv/guest_generic_x87.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -89,16 +89,35 @@
#define FP_ENV_TAG 4
#define FP_ENV_IP 6 /* and 7 */
#define FP_ENV_CS 8
+#define FP_ENV_LSTOP 9
#define FP_ENV_OPOFF 10 /* and 11 */
#define FP_ENV_OPSEL 12
#define FP_REG(ii) (10*(7-(ii)))
+/* Layout of the 16-bit FNSAVE x87 state. */
+typedef
+ struct {
+ UShort env[7];
+ UChar reg[80];
+ }
+ Fpu_State_16;
+
+/* Offsets, in 16-bit ints, into the FPU environment (env) area. */
+#define FPS_ENV_CTRL 0
+#define FPS_ENV_STAT 1
+#define FPS_ENV_TAG 2
+#define FPS_ENV_IP 3
+#define FPS_ENV_CS 4
+#define FPS_ENV_OPOFF 5
+#define FPS_ENV_OPSEL 6
+
+
/* Do the computations for x86/amd64 FXTRACT. Called directly from
generated code. CLEAN HELPER. */
extern ULong x86amd64g_calculate_FXTRACT ( ULong arg, HWord getExp );
-/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M}
+/* Compute result and new OSZACP flags for all 8-bit PCMP{E,I}STR{I,M}
variants. See bigger comment on implementation of this function
for details on call/return conventions. */
extern Bool compute_PCMPxSTRx ( /*OUT*/V128* resV,
@@ -107,6 +126,15 @@
UInt zmaskL, UInt zmaskR,
UInt imm8, Bool isxSTRM );
+/* Compute result and new OSZACP flags for all 16-bit PCMP{E,I}STR{I,M}
+ variants. See bigger comment on implementation of this function
+ for details on call/return conventions. */
+extern Bool compute_PCMPxSTRx_wide ( /*OUT*/V128* resV,
+ /*OUT*/UInt* resOSZACP,
+ V128* argLV, V128* argRV,
+ UInt zmaskL, UInt zmaskR,
+ UInt imm8, Bool isxSTRM );
+
#endif /* ndef __VEX_GUEST_GENERIC_X87_H */
/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/guest_mips_defs.h b/main/VEX/priv/guest_mips_defs.h
new file mode 100644
index 0000000..afb4f90
--- /dev/null
+++ b/main/VEX/priv/guest_mips_defs.h
@@ -0,0 +1,114 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin guest_mips_defs.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Only to be used within the guest-mips directory. */
+
+#ifndef __VEX_GUEST_MIPS_DEFS_H
+#define __VEX_GUEST_MIPS_DEFS_H
+
+/*---------------------------------------------------------*/
+/*--- mips to IR conversion ---*/
+/*---------------------------------------------------------*/
+
+/* Convert one MIPS insn to IR. See the type DisOneInstrFn in
+ bb_to_IR.h. */
+extern DisResult disInstr_MIPS ( IRSB* irbb,
+ Bool (*resteerOkFn) (void *, Addr64),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ UChar* guest_code,
+ Long delta,
+ Addr64 guest_IP,
+ VexArch guest_arch,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian );
+
+/* Used by the optimiser to specialise calls to helpers. */
+extern IRExpr *guest_mips32_spechelper(HChar * function_name, IRExpr ** args,
+ IRStmt ** precedingStmts,
+ Int n_precedingStmts);
+
+/* Describes to the optimser which part of the guest state require
+ precise memory exceptions. This is logically part of the guest
+ state description. */
+extern Bool guest_mips32_state_requires_precise_mem_exns(Int, Int);
+
+extern VexGuestLayout mips32Guest_layout;
+
+/*---------------------------------------------------------*/
+/*--- mips guest helpers ---*/
+/*---------------------------------------------------------*/
+
+extern UInt mips32_dirtyhelper_mfc0(UInt rd, UInt sel);
+
+extern void mips32_dirtyhelper_sync(UInt sync);
+
+/*---------------------------------------------------------*/
+/*--- Condition code stuff ---*/
+/*---------------------------------------------------------*/
+
+/* Defines conditions which we can ask for (MIPS MIPS 2e page A3-6) */
+
+typedef enum {
+ MIPSCondEQ = 0, /* equal : Z=1 */
+ MIPSCondNE = 1, /* not equal : Z=0 */
+
+ MIPSCondHS = 2, /* >=u (higher or same) : C=1 */
+ MIPSCondLO = 3, /* <u (lower) : C=0 */
+
+ MIPSCondMI = 4, /* minus (negative) : N=1 */
+ MIPSCondPL = 5, /* plus (zero or +ve) : N=0 */
+
+ MIPSCondVS = 6, /* overflow : V=1 */
+ MIPSCondVC = 7, /* no overflow : V=0 */
+
+ MIPSCondHI = 8, /* >u (higher) : C=1 && Z=0 */
+ MIPSCondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */
+
+ MIPSCondGE = 10, /* >=s (signed greater or equal) : N=V */
+ MIPSCondLT = 11, /* <s (signed less than) : N!=V */
+
+ MIPSCondGT = 12, /* >s (signed greater) : Z=0 && N=V */
+ MIPSCondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */
+
+ MIPSCondAL = 14, /* always (unconditional) : 1 */
+ MIPSCondNV = 15 /* never (unconditional): : 0 */
+ /* NB: MIPS have deprecated the use of the NV condition code.
+ You are now supposed to use MOV R0,R0 as a noop rather than
+ MOVNV R0,R0 as was previously recommended. Future processors
+ may have the NV condition code reused to do other things. */
+} MIPSCondcode;
+
+#endif /* __VEX_GUEST_MIPS_DEFS_H */
+
+/*---------------------------------------------------------------*/
+/*--- end guest_mips_defs.h ---*/
+/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/guest_mips_helpers.c b/main/VEX/priv/guest_mips_helpers.c
new file mode 100644
index 0000000..d992b9c
--- /dev/null
+++ b/main/VEX/priv/guest_mips_helpers.c
@@ -0,0 +1,573 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin guest_mips_helpers.c ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "libvex_basictypes.h"
+#include "libvex_emwarn.h"
+#include "libvex_guest_mips32.h"
+#include "libvex_ir.h"
+#include "libvex.h"
+
+#include "main_util.h"
+#include "guest_generic_bb_to_IR.h"
+#include "guest_mips_defs.h"
+
+/* This file contains helper functions for mips guest code. Calls to
+ these functions are generated by the back end.
+*/
+
+#define ALWAYSDEFD32(field) \
+ { offsetof(VexGuestMIPS32State, field), \
+ (sizeof ((VexGuestMIPS32State*)0)->field) }
+
+IRExpr *guest_mips32_spechelper(HChar * function_name, IRExpr ** args,
+ IRStmt ** precedingStmts, Int n_precedingStmts)
+{
+ return NULL;
+}
+
+/* VISIBLE TO LIBVEX CLIENT */
+void LibVEX_GuestMIPS32_initialise( /*OUT*/ VexGuestMIPS32State * vex_state)
+{
+ vex_state->guest_r0 = 0; /* Hardwired to 0 */
+ vex_state->guest_r1 = 0; /* Assembler temporary */
+ vex_state->guest_r2 = 0; /* Values for function returns ... */
+ vex_state->guest_r3 = 0; /* ...and expression evaluation */
+ vex_state->guest_r4 = 0; /* Function arguments */
+ vex_state->guest_r5 = 0;
+ vex_state->guest_r6 = 0;
+ vex_state->guest_r7 = 0;
+ vex_state->guest_r8 = 0; /* Temporaries */
+ vex_state->guest_r9 = 0;
+ vex_state->guest_r10 = 0;
+ vex_state->guest_r11 = 0;
+ vex_state->guest_r12 = 0;
+ vex_state->guest_r13 = 0;
+ vex_state->guest_r14 = 0;
+ vex_state->guest_r15 = 0;
+ vex_state->guest_r16 = 0; /* Saved temporaries */
+ vex_state->guest_r17 = 0;
+ vex_state->guest_r18 = 0;
+ vex_state->guest_r19 = 0;
+ vex_state->guest_r20 = 0;
+ vex_state->guest_r21 = 0;
+ vex_state->guest_r22 = 0;
+ vex_state->guest_r23 = 0;
+ vex_state->guest_r24 = 0; /* Temporaries */
+ vex_state->guest_r25 = 0;
+ vex_state->guest_r26 = 0; /* Reserved for OS kernel */
+ vex_state->guest_r27 = 0;
+ vex_state->guest_r28 = 0; /* Global pointer */
+ vex_state->guest_r29 = 0; /* Stack pointer */
+ vex_state->guest_r30 = 0; /* Frame pointer */
+ vex_state->guest_r31 = 0; /* Return address */
+ vex_state->guest_PC = 0; /* Program counter */
+ vex_state->guest_HI = 0; /* Multiply and divide register higher result */
+ vex_state->guest_LO = 0; /* Multiply and divide register lower result */
+
+ /* FPU Registers */
+ vex_state->guest_f0 = 0x7ff80000; /* Floting point general purpose registers */
+ vex_state->guest_f1 = 0x7ff80000;
+ vex_state->guest_f2 = 0x7ff80000;
+ vex_state->guest_f3 = 0x7ff80000;
+ vex_state->guest_f4 = 0x7ff80000;
+ vex_state->guest_f5 = 0x7ff80000;
+ vex_state->guest_f6 = 0x7ff80000;
+ vex_state->guest_f7 = 0x7ff80000;
+ vex_state->guest_f8 = 0x7ff80000;
+ vex_state->guest_f9 = 0x7ff80000;
+ vex_state->guest_f10 = 0x7ff80000;
+ vex_state->guest_f11 = 0x7ff80000;
+ vex_state->guest_f12 = 0x7ff80000;
+ vex_state->guest_f13 = 0x7ff80000;
+ vex_state->guest_f14 = 0x7ff80000;
+ vex_state->guest_f15 = 0x7ff80000;
+ vex_state->guest_f16 = 0x7ff80000;
+ vex_state->guest_f17 = 0x7ff80000;
+ vex_state->guest_f18 = 0x7ff80000;
+ vex_state->guest_f19 = 0x7ff80000;
+ vex_state->guest_f20 = 0x7ff80000;
+ vex_state->guest_f21 = 0x7ff80000;
+ vex_state->guest_f22 = 0x7ff80000;
+ vex_state->guest_f23 = 0x7ff80000;
+ vex_state->guest_f24 = 0x7ff80000;
+ vex_state->guest_f25 = 0x7ff80000;
+ vex_state->guest_f26 = 0x7ff80000;
+ vex_state->guest_f27 = 0x7ff80000;
+ vex_state->guest_f28 = 0x7ff80000;
+ vex_state->guest_f29 = 0x7ff80000;
+ vex_state->guest_f30 = 0x7ff80000;
+ vex_state->guest_f31 = 0x7ff80000;
+
+ vex_state->guest_FIR = 0; /* FP implementation and revision register */
+ vex_state->guest_FCCR = 0; /* FP condition codes register */
+ vex_state->guest_FEXR = 0; /* FP exceptions register */
+ vex_state->guest_FENR = 0; /* FP enables register */
+ vex_state->guest_FCSR = 0; /* FP control/status register */
+ vex_state->guest_ULR = 0; /* TLS */
+
+ /* Various pseudo-regs mandated by Vex or Valgrind. */
+ /* Emulation warnings */
+ vex_state->guest_EMWARN = 0;
+
+ /* For clflush: record start and length of area to invalidate */
+ vex_state->guest_TISTART = 0;
+ vex_state->guest_TILEN = 0;
+ vex_state->host_EvC_COUNTER = 0;
+ vex_state->host_EvC_FAILADDR = 0;
+
+ /* Used to record the unredirected guest address at the start of
+ a translation whose start has been redirected. By reading
+ this pseudo-register shortly afterwards, the translation can
+ find out what the corresponding no-redirection address was.
+ Note, this is only set for wrap-style redirects, not for
+ replace-style ones. */
+ vex_state->guest_NRADDR = 0;
+
+ vex_state->guest_COND = 0;
+}
+
+/*-----------------------------------------------------------*/
+/*--- Describing the mips guest state, for the benefit ---*/
+/*--- of iropt and instrumenters. ---*/
+/*-----------------------------------------------------------*/
+
+/* Figure out if any part of the guest state contained in minoff
+ .. maxoff requires precise memory exceptions. If in doubt return
+ True (but this is generates significantly slower code).
+
+ We enforce precise exns for guest SP, PC.
+*/
+Bool guest_mips32_state_requires_precise_mem_exns(Int minoff, Int maxoff)
+{
+ Int sp_min = offsetof(VexGuestMIPS32State, guest_r29);
+ Int sp_max = sp_min + 4 - 1;
+ Int pc_min = offsetof(VexGuestMIPS32State, guest_PC);
+ Int pc_max = pc_min + 4 - 1;
+
+ if (maxoff < sp_min || minoff > sp_max) {
+ /* no overlap with sp */
+ } else {
+ return True;
+ }
+
+ if (maxoff < pc_min || minoff > pc_max) {
+ /* no overlap with pc */
+ } else {
+ return True;
+ }
+
+ /* We appear to need precise updates of R11 in order to get proper
+ stacktraces from non-optimised code. */
+ Int fp_min = offsetof(VexGuestMIPS32State, guest_r30);
+ Int fp_max = fp_min + 4 - 1;
+
+ if (maxoff < fp_min || minoff > fp_max) {
+ /* no overlap with fp */
+ } else {
+ return True;
+ }
+
+ return False;
+}
+
+VexGuestLayout mips32Guest_layout = {
+ /* Total size of the guest state, in bytes. */
+ .total_sizeB = sizeof(VexGuestMIPS32State),
+ /* Describe the stack pointer. */
+ .offset_SP = offsetof(VexGuestMIPS32State, guest_r29),
+ .sizeof_SP = 4,
+ /* Describe the frame pointer. */
+ .offset_FP = offsetof(VexGuestMIPS32State, guest_r30),
+ .sizeof_FP = 4,
+ /* Describe the instruction pointer. */
+ .offset_IP = offsetof(VexGuestMIPS32State, guest_PC),
+ .sizeof_IP = 4,
+ /* Describe any sections to be regarded by Memcheck as
+ 'always-defined'. */
+ .n_alwaysDefd = 8,
+ /* ? :( */
+ .alwaysDefd = {
+ /* 0 */ ALWAYSDEFD32(guest_r0),
+ /* 1 */ ALWAYSDEFD32(guest_r1),
+ /* 2 */ ALWAYSDEFD32(guest_EMWARN),
+ /* 3 */ ALWAYSDEFD32(guest_TISTART),
+ /* 4 */ ALWAYSDEFD32(guest_TILEN),
+ /* 5 */ ALWAYSDEFD32(guest_r29),
+ /* 6 */ ALWAYSDEFD32(guest_r31),
+ /* 7 */ ALWAYSDEFD32(guest_ULR)
+ }
+};
+
+#define ASM_VOLATILE_CASE(rd, sel) \
+ case rd: asm volatile ("mfc0 %0, $" #rd ", "#sel"\n\t" :"=r" (x) ); break;
+
+UInt mips32_dirtyhelper_mfc0(UInt rd, UInt sel)
+{
+ UInt x = 0;
+#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
+ switch (sel) {
+ case 0:
+ //__asm__("mfc0 %0, $1, 0" :"=r" (x));
+ switch (rd) {
+ ASM_VOLATILE_CASE(0, 0);
+ ASM_VOLATILE_CASE(1, 0);
+ ASM_VOLATILE_CASE(2, 0);
+ ASM_VOLATILE_CASE(3, 0);
+ ASM_VOLATILE_CASE(4, 0);
+ ASM_VOLATILE_CASE(5, 0);
+ ASM_VOLATILE_CASE(6, 0);
+ ASM_VOLATILE_CASE(7, 0);
+ ASM_VOLATILE_CASE(8, 0);
+ ASM_VOLATILE_CASE(9, 0);
+ ASM_VOLATILE_CASE(10, 0);
+ ASM_VOLATILE_CASE(11, 0);
+ ASM_VOLATILE_CASE(12, 0);
+ ASM_VOLATILE_CASE(13, 0);
+ ASM_VOLATILE_CASE(14, 0);
+ ASM_VOLATILE_CASE(15, 0);
+ ASM_VOLATILE_CASE(16, 0);
+ ASM_VOLATILE_CASE(17, 0);
+ ASM_VOLATILE_CASE(18, 0);
+ ASM_VOLATILE_CASE(19, 0);
+ ASM_VOLATILE_CASE(20, 0);
+ ASM_VOLATILE_CASE(21, 0);
+ ASM_VOLATILE_CASE(22, 0);
+ ASM_VOLATILE_CASE(23, 0);
+ ASM_VOLATILE_CASE(24, 0);
+ ASM_VOLATILE_CASE(25, 0);
+ ASM_VOLATILE_CASE(26, 0);
+ ASM_VOLATILE_CASE(27, 0);
+ ASM_VOLATILE_CASE(28, 0);
+ ASM_VOLATILE_CASE(29, 0);
+ ASM_VOLATILE_CASE(30, 0);
+ ASM_VOLATILE_CASE(31, 0);
+ default:
+ break;
+ }
+ break;
+ case 1:
+ //__asm__("mfc0 %0, $1, 0" :"=r" (x));
+ switch (rd) {
+ ASM_VOLATILE_CASE(0, 1);
+ ASM_VOLATILE_CASE(1, 1);
+ ASM_VOLATILE_CASE(2, 1);
+ ASM_VOLATILE_CASE(3, 1);
+ ASM_VOLATILE_CASE(4, 1);
+ ASM_VOLATILE_CASE(5, 1);
+ ASM_VOLATILE_CASE(6, 1);
+ ASM_VOLATILE_CASE(7, 1);
+ ASM_VOLATILE_CASE(8, 1);
+ ASM_VOLATILE_CASE(9, 1);
+ ASM_VOLATILE_CASE(10, 1);
+ ASM_VOLATILE_CASE(11, 1);
+ ASM_VOLATILE_CASE(12, 1);
+ ASM_VOLATILE_CASE(13, 1);
+ ASM_VOLATILE_CASE(14, 1);
+ ASM_VOLATILE_CASE(15, 1);
+ ASM_VOLATILE_CASE(16, 1);
+ ASM_VOLATILE_CASE(17, 1);
+ ASM_VOLATILE_CASE(18, 1);
+ ASM_VOLATILE_CASE(19, 1);
+ ASM_VOLATILE_CASE(20, 1);
+ ASM_VOLATILE_CASE(21, 1);
+ ASM_VOLATILE_CASE(22, 1);
+ ASM_VOLATILE_CASE(23, 1);
+ ASM_VOLATILE_CASE(24, 1);
+ ASM_VOLATILE_CASE(25, 1);
+ ASM_VOLATILE_CASE(26, 1);
+ ASM_VOLATILE_CASE(27, 1);
+ ASM_VOLATILE_CASE(28, 1);
+ ASM_VOLATILE_CASE(29, 1);
+ ASM_VOLATILE_CASE(30, 1);
+ ASM_VOLATILE_CASE(31, 1);
+ default:
+ break;
+ }
+ break;
+ case 2:
+ //__asm__("mfc0 %0, $1, 0" :"=r" (x));
+ switch (rd) {
+ ASM_VOLATILE_CASE(0, 2);
+ ASM_VOLATILE_CASE(1, 2);
+ ASM_VOLATILE_CASE(2, 2);
+ ASM_VOLATILE_CASE(3, 1);
+ ASM_VOLATILE_CASE(4, 2);
+ ASM_VOLATILE_CASE(5, 2);
+ ASM_VOLATILE_CASE(6, 2);
+ ASM_VOLATILE_CASE(7, 2);
+ ASM_VOLATILE_CASE(8, 2);
+ ASM_VOLATILE_CASE(9, 2);
+ ASM_VOLATILE_CASE(10, 2);
+ ASM_VOLATILE_CASE(11, 2);
+ ASM_VOLATILE_CASE(12, 2);
+ ASM_VOLATILE_CASE(13, 2);
+ ASM_VOLATILE_CASE(14, 2);
+ ASM_VOLATILE_CASE(15, 2);
+ ASM_VOLATILE_CASE(16, 2);
+ ASM_VOLATILE_CASE(17, 2);
+ ASM_VOLATILE_CASE(18, 2);
+ ASM_VOLATILE_CASE(19, 2);
+ ASM_VOLATILE_CASE(20, 2);
+ ASM_VOLATILE_CASE(21, 2);
+ ASM_VOLATILE_CASE(22, 2);
+ ASM_VOLATILE_CASE(23, 2);
+ ASM_VOLATILE_CASE(24, 2);
+ ASM_VOLATILE_CASE(25, 2);
+ ASM_VOLATILE_CASE(26, 2);
+ ASM_VOLATILE_CASE(27, 2);
+ ASM_VOLATILE_CASE(28, 2);
+ ASM_VOLATILE_CASE(29, 2);
+ ASM_VOLATILE_CASE(30, 2);
+ ASM_VOLATILE_CASE(31, 2);
+ default:
+ break;
+ }
+ break;
+ case 3:
+ //__asm__("mfc0 %0, $1, 0" :"=r" (x));
+ switch (rd) {
+ ASM_VOLATILE_CASE(0, 3);
+ ASM_VOLATILE_CASE(1, 3);
+ ASM_VOLATILE_CASE(2, 3);
+ ASM_VOLATILE_CASE(3, 3);
+ ASM_VOLATILE_CASE(4, 3);
+ ASM_VOLATILE_CASE(5, 3);
+ ASM_VOLATILE_CASE(6, 3);
+ ASM_VOLATILE_CASE(7, 3);
+ ASM_VOLATILE_CASE(8, 3);
+ ASM_VOLATILE_CASE(9, 3);
+ ASM_VOLATILE_CASE(10, 3);
+ ASM_VOLATILE_CASE(11, 3);
+ ASM_VOLATILE_CASE(12, 3);
+ ASM_VOLATILE_CASE(13, 3);
+ ASM_VOLATILE_CASE(14, 3);
+ ASM_VOLATILE_CASE(15, 3);
+ ASM_VOLATILE_CASE(16, 3);
+ ASM_VOLATILE_CASE(17, 3);
+ ASM_VOLATILE_CASE(18, 3);
+ ASM_VOLATILE_CASE(19, 3);
+ ASM_VOLATILE_CASE(20, 3);
+ ASM_VOLATILE_CASE(21, 3);
+ ASM_VOLATILE_CASE(22, 3);
+ ASM_VOLATILE_CASE(23, 3);
+ ASM_VOLATILE_CASE(24, 3);
+ ASM_VOLATILE_CASE(25, 3);
+ ASM_VOLATILE_CASE(26, 3);
+ ASM_VOLATILE_CASE(27, 3);
+ ASM_VOLATILE_CASE(28, 3);
+ ASM_VOLATILE_CASE(29, 3);
+ ASM_VOLATILE_CASE(30, 3);
+ ASM_VOLATILE_CASE(31, 3);
+ default:
+ break;
+ }
+ break;
+ case 4:
+ //__asm__("mfc0 %0, $1, 0" :"=r" (x));
+ switch (rd) {
+ ASM_VOLATILE_CASE(0, 4);
+ ASM_VOLATILE_CASE(1, 4);
+ ASM_VOLATILE_CASE(2, 4);
+ ASM_VOLATILE_CASE(3, 4);
+ ASM_VOLATILE_CASE(4, 4);
+ ASM_VOLATILE_CASE(5, 4);
+ ASM_VOLATILE_CASE(6, 4);
+ ASM_VOLATILE_CASE(7, 4);
+ ASM_VOLATILE_CASE(8, 4);
+ ASM_VOLATILE_CASE(9, 4);
+ ASM_VOLATILE_CASE(10, 4);
+ ASM_VOLATILE_CASE(11, 4);
+ ASM_VOLATILE_CASE(12, 4);
+ ASM_VOLATILE_CASE(13, 4);
+ ASM_VOLATILE_CASE(14, 4);
+ ASM_VOLATILE_CASE(15, 4);
+ ASM_VOLATILE_CASE(16, 4);
+ ASM_VOLATILE_CASE(17, 4);
+ ASM_VOLATILE_CASE(18, 4);
+ ASM_VOLATILE_CASE(19, 4);
+ ASM_VOLATILE_CASE(20, 4);
+ ASM_VOLATILE_CASE(21, 4);
+ ASM_VOLATILE_CASE(22, 4);
+ ASM_VOLATILE_CASE(23, 4);
+ ASM_VOLATILE_CASE(24, 4);
+ ASM_VOLATILE_CASE(25, 4);
+ ASM_VOLATILE_CASE(26, 4);
+ ASM_VOLATILE_CASE(27, 4);
+ ASM_VOLATILE_CASE(28, 4);
+ ASM_VOLATILE_CASE(29, 4);
+ ASM_VOLATILE_CASE(30, 4);
+ ASM_VOLATILE_CASE(31, 4);
+ default:
+ break;
+ }
+ break;
+ case 5:
+ //__asm__("mfc0 %0, $1, 0" :"=r" (x));
+ switch (rd) {
+ ASM_VOLATILE_CASE(0, 5);
+ ASM_VOLATILE_CASE(1, 5);
+ ASM_VOLATILE_CASE(2, 5);
+ ASM_VOLATILE_CASE(3, 5);
+ ASM_VOLATILE_CASE(4, 5);
+ ASM_VOLATILE_CASE(5, 5);
+ ASM_VOLATILE_CASE(6, 5);
+ ASM_VOLATILE_CASE(7, 5);
+ ASM_VOLATILE_CASE(8, 5);
+ ASM_VOLATILE_CASE(9, 5);
+ ASM_VOLATILE_CASE(10, 5);
+ ASM_VOLATILE_CASE(11, 5);
+ ASM_VOLATILE_CASE(12, 5);
+ ASM_VOLATILE_CASE(13, 5);
+ ASM_VOLATILE_CASE(14, 5);
+ ASM_VOLATILE_CASE(15, 5);
+ ASM_VOLATILE_CASE(16, 5);
+ ASM_VOLATILE_CASE(17, 5);
+ ASM_VOLATILE_CASE(18, 5);
+ ASM_VOLATILE_CASE(19, 5);
+ ASM_VOLATILE_CASE(20, 5);
+ ASM_VOLATILE_CASE(21, 5);
+ ASM_VOLATILE_CASE(22, 5);
+ ASM_VOLATILE_CASE(23, 5);
+ ASM_VOLATILE_CASE(24, 5);
+ ASM_VOLATILE_CASE(25, 5);
+ ASM_VOLATILE_CASE(26, 5);
+ ASM_VOLATILE_CASE(27, 5);
+ ASM_VOLATILE_CASE(28, 5);
+ ASM_VOLATILE_CASE(29, 5);
+ ASM_VOLATILE_CASE(30, 5);
+ ASM_VOLATILE_CASE(31, 5);
+ default:
+ break;
+ }
+ break;
+ case 6:
+ //__asm__("mfc0 %0, $1, 0" :"=r" (x));
+ switch (rd) {
+ ASM_VOLATILE_CASE(0, 6);
+ ASM_VOLATILE_CASE(1, 6);
+ ASM_VOLATILE_CASE(2, 6);
+ ASM_VOLATILE_CASE(3, 6);
+ ASM_VOLATILE_CASE(4, 6);
+ ASM_VOLATILE_CASE(5, 6);
+ ASM_VOLATILE_CASE(6, 6);
+ ASM_VOLATILE_CASE(7, 6);
+ ASM_VOLATILE_CASE(8, 6);
+ ASM_VOLATILE_CASE(9, 6);
+ ASM_VOLATILE_CASE(10, 6);
+ ASM_VOLATILE_CASE(11, 6);
+ ASM_VOLATILE_CASE(12, 6);
+ ASM_VOLATILE_CASE(13, 6);
+ ASM_VOLATILE_CASE(14, 6);
+ ASM_VOLATILE_CASE(15, 6);
+ ASM_VOLATILE_CASE(16, 6);
+ ASM_VOLATILE_CASE(17, 6);
+ ASM_VOLATILE_CASE(18, 6);
+ ASM_VOLATILE_CASE(19, 6);
+ ASM_VOLATILE_CASE(20, 6);
+ ASM_VOLATILE_CASE(21, 6);
+ ASM_VOLATILE_CASE(22, 6);
+ ASM_VOLATILE_CASE(23, 6);
+ ASM_VOLATILE_CASE(24, 6);
+ ASM_VOLATILE_CASE(25, 6);
+ ASM_VOLATILE_CASE(26, 6);
+ ASM_VOLATILE_CASE(27, 6);
+ ASM_VOLATILE_CASE(28, 6);
+ ASM_VOLATILE_CASE(29, 6);
+ ASM_VOLATILE_CASE(30, 6);
+ ASM_VOLATILE_CASE(31, 6);
+ default:
+ break;
+ }
+ break;
+ case 7:
+ //__asm__("mfc0 %0, $1, 0" :"=r" (x));
+ switch (rd) {
+ ASM_VOLATILE_CASE(0, 7);
+ ASM_VOLATILE_CASE(1, 7);
+ ASM_VOLATILE_CASE(2, 7);
+ ASM_VOLATILE_CASE(3, 7);
+ ASM_VOLATILE_CASE(4, 7);
+ ASM_VOLATILE_CASE(5, 7);
+ ASM_VOLATILE_CASE(6, 7);
+ ASM_VOLATILE_CASE(7, 7);
+ ASM_VOLATILE_CASE(8, 7);
+ ASM_VOLATILE_CASE(9, 7);
+ ASM_VOLATILE_CASE(10, 7);
+ ASM_VOLATILE_CASE(11, 7);
+ ASM_VOLATILE_CASE(12, 7);
+ ASM_VOLATILE_CASE(13, 7);
+ ASM_VOLATILE_CASE(14, 7);
+ ASM_VOLATILE_CASE(15, 7);
+ ASM_VOLATILE_CASE(16, 7);
+ ASM_VOLATILE_CASE(17, 7);
+ ASM_VOLATILE_CASE(18, 7);
+ ASM_VOLATILE_CASE(19, 7);
+ ASM_VOLATILE_CASE(20, 7);
+ ASM_VOLATILE_CASE(21, 7);
+ ASM_VOLATILE_CASE(22, 7);
+ ASM_VOLATILE_CASE(23, 7);
+ ASM_VOLATILE_CASE(24, 7);
+ ASM_VOLATILE_CASE(25, 7);
+ ASM_VOLATILE_CASE(26, 7);
+ ASM_VOLATILE_CASE(27, 7);
+ ASM_VOLATILE_CASE(28, 7);
+ ASM_VOLATILE_CASE(29, 7);
+ ASM_VOLATILE_CASE(30, 7);
+ ASM_VOLATILE_CASE(31, 7);
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#endif
+ return x;
+}
+
+#undef ASM_VOLATILE_CASE
+
+#define ASM_VOLATILE_CASE(rd, sel) \
+ case rd: asm volatile ("dmfc0 %0, $" #rd ", "#sel"\n\t" :"=r" (x) ); break;
+
+#define ASM_VOLATILE_SYNC(stype) \
+ asm volatile ("sync \n\t");
+
+void mips32_dirtyhelper_sync(UInt stype)
+{
+#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
+ ASM_VOLATILE_SYNC(0);
+#endif
+}
+
+/*---------------------------------------------------------------*/
+/*--- end guest_mips_helpers.c ---*/
+/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/guest_mips_toIR.c b/main/VEX/priv/guest_mips_toIR.c
new file mode 100644
index 0000000..0fcb07c
--- /dev/null
+++ b/main/VEX/priv/guest_mips_toIR.c
@@ -0,0 +1,3520 @@
+
+/*--------------------------------------------------------------------*/
+/*--- begin guest_mips_toIR.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Translates MIPS code to IR. */
+
+#include "libvex_basictypes.h"
+#include "libvex_ir.h"
+#include "libvex.h"
+#include "libvex_guest_mips32.h"
+
+#include "main_util.h"
+#include "main_globals.h"
+#include "guest_generic_bb_to_IR.h"
+#include "guest_mips_defs.h"
+
+/*------------------------------------------------------------*/
+/*--- Globals ---*/
+/*------------------------------------------------------------*/
+
+/* These are set at the start of the translation of a instruction, so
+ that we don't have to pass them around endlessly. CONST means does
+ not change during translation of the instruction.
+*/
+
+/* CONST: is the host bigendian? This has to do with float vs double
+ register accesses on VFP, but it's complex and not properly thought
+ out. */
+static Bool host_is_bigendian;
+
+/* Pointer to the guest code area. */
+static UChar *guest_code;
+
+/* The guest address corresponding to guest_code[0]. */
+static Addr32 guest_PC_bbstart;
+
+/* CONST: The guest address for the instruction currently being
+ translated. */
+static Addr32 guest_PC_curr_instr;
+
+/* MOD: The IRSB* into which we're generating code. */
+static IRSB *irsb;
+
+/* Is our guest binary 32 or 64bit? Set at each call to
+ disInstr_MIPS below. */
+static Bool mode64 = False;
+
+/*------------------------------------------------------------*/
+/*--- Debugging output ---*/
+/*------------------------------------------------------------*/
+
+#define DIP(format, args...) \
+ if (vex_traceflags & VEX_TRACE_FE) \
+ vex_printf(format, ## args)
+
+/*------------------------------------------------------------*/
+/*--- Helper bits and pieces for deconstructing the ---*/
+/*--- mips insn stream. ---*/
+/*------------------------------------------------------------*/
+
+/* ---------------- Integer registers ---------------- */
+
+static UInt integerGuestRegOffset(UInt iregNo)
+{
+ /* Do we care about endianness here? We do if sub-parts of integer
+ registers are accessed, but I don't think that ever happens on
+ MIPS. */
+ UInt ret;
+ switch (iregNo) {
+ case 0:
+ ret = offsetof(VexGuestMIPS32State, guest_r0); break;
+ case 1:
+ ret = offsetof(VexGuestMIPS32State, guest_r1); break;
+ case 2:
+ ret = offsetof(VexGuestMIPS32State, guest_r2); break;
+ case 3:
+ ret = offsetof(VexGuestMIPS32State, guest_r3); break;
+ case 4:
+ ret = offsetof(VexGuestMIPS32State, guest_r4); break;
+ case 5:
+ ret = offsetof(VexGuestMIPS32State, guest_r5); break;
+ case 6:
+ ret = offsetof(VexGuestMIPS32State, guest_r6); break;
+ case 7:
+ ret = offsetof(VexGuestMIPS32State, guest_r7); break;
+ case 8:
+ ret = offsetof(VexGuestMIPS32State, guest_r8); break;
+ case 9:
+ ret = offsetof(VexGuestMIPS32State, guest_r9); break;
+ case 10:
+ ret = offsetof(VexGuestMIPS32State, guest_r10); break;
+ case 11:
+ ret = offsetof(VexGuestMIPS32State, guest_r11); break;
+ case 12:
+ ret = offsetof(VexGuestMIPS32State, guest_r12); break;
+ case 13:
+ ret = offsetof(VexGuestMIPS32State, guest_r13); break;
+ case 14:
+ ret = offsetof(VexGuestMIPS32State, guest_r14); break;
+ case 15:
+ ret = offsetof(VexGuestMIPS32State, guest_r15); break;
+ case 16:
+ ret = offsetof(VexGuestMIPS32State, guest_r16); break;
+ case 17:
+ ret = offsetof(VexGuestMIPS32State, guest_r17); break;
+ case 18:
+ ret = offsetof(VexGuestMIPS32State, guest_r18); break;
+ case 19:
+ ret = offsetof(VexGuestMIPS32State, guest_r19); break;
+ case 20:
+ ret = offsetof(VexGuestMIPS32State, guest_r20); break;
+ case 21:
+ ret = offsetof(VexGuestMIPS32State, guest_r21); break;
+ case 22:
+ ret = offsetof(VexGuestMIPS32State, guest_r22); break;
+ case 23:
+ ret = offsetof(VexGuestMIPS32State, guest_r23); break;
+ case 24:
+ ret = offsetof(VexGuestMIPS32State, guest_r24); break;
+ case 25:
+ ret = offsetof(VexGuestMIPS32State, guest_r25); break;
+ case 26:
+ ret = offsetof(VexGuestMIPS32State, guest_r26); break;
+ case 27:
+ ret = offsetof(VexGuestMIPS32State, guest_r27); break;
+ case 28:
+ ret = offsetof(VexGuestMIPS32State, guest_r28); break;
+ case 29:
+ ret = offsetof(VexGuestMIPS32State, guest_r29); break;
+ case 30:
+ ret = offsetof(VexGuestMIPS32State, guest_r30); break;
+ case 31:
+ ret = offsetof(VexGuestMIPS32State, guest_r31); break;
+ default:
+ vassert(0);
+ break;
+ }
+ return ret;
+}
+
+#define OFFB_PC offsetof(VexGuestMIPS32State, guest_PC)
+
+/* ---------------- Floating point registers ---------------- */
+
+static UInt floatGuestRegOffset(UInt fregNo)
+{
+ vassert(fregNo < 32);
+ UInt ret;
+ switch (fregNo) {
+ case 0:
+ ret = offsetof(VexGuestMIPS32State, guest_f0); break;
+ case 1:
+ ret = offsetof(VexGuestMIPS32State, guest_f1); break;
+ case 2:
+ ret = offsetof(VexGuestMIPS32State, guest_f2); break;
+ case 3:
+ ret = offsetof(VexGuestMIPS32State, guest_f3); break;
+ case 4:
+ ret = offsetof(VexGuestMIPS32State, guest_f4); break;
+ case 5:
+ ret = offsetof(VexGuestMIPS32State, guest_f5); break;
+ case 6:
+ ret = offsetof(VexGuestMIPS32State, guest_f6); break;
+ case 7:
+ ret = offsetof(VexGuestMIPS32State, guest_f7); break;
+ case 8:
+ ret = offsetof(VexGuestMIPS32State, guest_f8); break;
+ case 9:
+ ret = offsetof(VexGuestMIPS32State, guest_f9); break;
+ case 10:
+ ret = offsetof(VexGuestMIPS32State, guest_f10); break;
+ case 11:
+ ret = offsetof(VexGuestMIPS32State, guest_f11); break;
+ case 12:
+ ret = offsetof(VexGuestMIPS32State, guest_f12); break;
+ case 13:
+ ret = offsetof(VexGuestMIPS32State, guest_f13); break;
+ case 14:
+ ret = offsetof(VexGuestMIPS32State, guest_f14); break;
+ case 15:
+ ret = offsetof(VexGuestMIPS32State, guest_f15); break;
+ case 16:
+ ret = offsetof(VexGuestMIPS32State, guest_f16); break;
+ case 17:
+ ret = offsetof(VexGuestMIPS32State, guest_f17); break;
+ case 18:
+ ret = offsetof(VexGuestMIPS32State, guest_f18); break;
+ case 19:
+ ret = offsetof(VexGuestMIPS32State, guest_f19); break;
+ case 20:
+ ret = offsetof(VexGuestMIPS32State, guest_f20); break;
+ case 21:
+ ret = offsetof(VexGuestMIPS32State, guest_f21); break;
+ case 22:
+ ret = offsetof(VexGuestMIPS32State, guest_f22); break;
+ case 23:
+ ret = offsetof(VexGuestMIPS32State, guest_f23); break;
+ case 24:
+ ret = offsetof(VexGuestMIPS32State, guest_f24); break;
+ case 25:
+ ret = offsetof(VexGuestMIPS32State, guest_f25); break;
+ case 26:
+ ret = offsetof(VexGuestMIPS32State, guest_f26); break;
+ case 27:
+ ret = offsetof(VexGuestMIPS32State, guest_f27); break;
+ case 28:
+ ret = offsetof(VexGuestMIPS32State, guest_f28); break;
+ case 29:
+ ret = offsetof(VexGuestMIPS32State, guest_f29); break;
+ case 30:
+ ret = offsetof(VexGuestMIPS32State, guest_f30); break;
+ case 31:
+ ret = offsetof(VexGuestMIPS32State, guest_f31); break;
+ default:
+ vassert(0);
+ break;
+ }
+ return ret;
+}
+
+/* Do a endian load of a 32-bit word, regardless of the
+ endianness of the underlying host. */
+static inline UInt getUInt(UChar * p)
+{
+ UInt w = 0;
+#if defined (_MIPSEL)
+ w = (w << 8) | p[3];
+ w = (w << 8) | p[2];
+ w = (w << 8) | p[1];
+ w = (w << 8) | p[0];
+#elif defined (_MIPSEB)
+ w = (w << 8) | p[0];
+ w = (w << 8) | p[1];
+ w = (w << 8) | p[2];
+ w = (w << 8) | p[3];
+#endif
+ return w;
+}
+
+#define BITS2(_b1,_b0) \
+ (((_b1) << 1) | (_b0))
+
+#define BITS3(_b2,_b1,_b0) \
+ (((_b2) << 2) | ((_b1) << 1) | (_b0))
+
+#define BITS4(_b3,_b2,_b1,_b0) \
+ (((_b3) << 3) | ((_b2) << 2) | ((_b1) << 1) | (_b0))
+
+#define BITS5(_b4,_b3,_b2,_b1,_b0) \
+ (((_b4) << 4) | BITS4((_b3),(_b2),(_b1),(_b0)))
+
+#define BITS6(_b5,_b4,_b3,_b2,_b1,_b0) \
+ ((BITS2((_b5),(_b4)) << 4) \
+ | BITS4((_b3),(_b2),(_b1),(_b0)))
+
+#define BITS8(_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \
+ ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \
+ | BITS4((_b3),(_b2),(_b1),(_b0)))
+
+#define LOAD_STORE_PATTERN \
+ t1 = newTemp(Ity_I32); \
+ assign(t1, binop(Iop_Add32, getIReg(rs), mkU32(extend_s_16to32(imm)))); \
+
+#define LWX_SWX_PATTERN \
+ t2 = newTemp(Ity_I32); \
+ assign(t2, binop(Iop_And32, mkexpr(t1), mkU32(0xFFFFFFFC))); \
+ t4 = newTemp(Ity_I32); \
+ assign(t4, binop(Iop_And32, mkexpr(t1), mkU32(0x00000003)))
+
+#define SXXV_PATTERN(op) \
+ putIReg(rd, binop(op, \
+ getIReg(rt), \
+ unop(Iop_32to8, \
+ binop(Iop_And32, \
+ getIReg(rs), \
+ mkU32(0x0000001F) \
+ ) \
+ ) \
+ ) \
+ )
+
+#define SXX_PATTERN(op) \
+ putIReg(rd, binop(op, getIReg(rt), mkU8(sa)));
+
+#define ALU_PATTERN(op) \
+ putIReg(rd, binop(op, getIReg(rs), getIReg(rt)));
+
+#define ALUI_PATTERN(op) \
+ putIReg(rt, binop(op, getIReg(rs), mkU32(imm)));
+
+#define ALUI_PATTERN64(op) \
+ putIReg(rt, binop(op, getIReg(rs), mkU64(imm)));
+
+#define FP_CONDITIONAL_CODE \
+ t3 = newTemp(Ity_I32); \
+ assign(t3, binop(Iop_And32, IRExpr_Mux0X( unop(Iop_1Uto8, \
+ binop(Iop_CmpEQ32, mkU32(cc), mkU32(0))), \
+ binop(Iop_Shr32, getFCSR(), mkU8(24+cc)), \
+ binop(Iop_Shr32, getFCSR(), mkU8(23))), mkU32(0x1)));
+
+/*------------------------------------------------------------*/
+/*--- Field helpers ---*/
+/*------------------------------------------------------------*/
+
+static UInt get_opcode(UInt mipsins)
+{
+ return (0xFC000000 & mipsins) >> 26;
+}
+
+static UInt get_rs(UInt mipsins)
+{
+ return (0x03E00000 & mipsins) >> 21;
+}
+
+static UInt get_rt(UInt mipsins)
+{
+ return (0x001F0000 & mipsins) >> 16;
+}
+
+static UInt get_imm(UInt mipsins)
+{
+ return (0x0000FFFF & mipsins);
+}
+
+static UInt get_instr_index(UInt mipsins)
+{
+ return (0x03FFFFFF & mipsins);
+}
+
+static UInt get_rd(UInt mipsins)
+{
+ return (0x0000F800 & mipsins) >> 11;
+}
+
+static UInt get_sa(UInt mipsins)
+{
+ return (0x000007C0 & mipsins) >> 6;
+}
+
+static UInt get_function(UInt mipsins)
+{
+ return (0x0000003F & mipsins);
+}
+
+static UInt get_ft(UInt mipsins)
+{
+ return (0x001F0000 & mipsins) >> 16;
+}
+
+static UInt get_fs(UInt mipsins)
+{
+ return (0x0000F800 & mipsins) >> 11;
+}
+
+static UInt get_fd(UInt mipsins)
+{
+ return (0x000007C0 & mipsins) >> 6;
+}
+
+static UInt get_mov_cc(UInt mipsins)
+{
+ return (0x001C0000 & mipsins) >> 18;
+}
+
+static UInt get_bc1_cc(UInt mipsins)
+{
+ return (0x001C0000 & mipsins) >> 18;
+}
+
+static UInt get_fpc_cc(UInt mipsins)
+{
+ return (0x00000700 & mipsins) >> 8;
+}
+
+static UInt get_tf(UInt mipsins)
+{
+ return (0x00010000 & mipsins) >> 16;
+}
+
+static UInt get_nd(UInt mipsins)
+{
+ return (0x00020000 & mipsins) >> 17;
+}
+
+static UInt get_fmt(UInt mipsins)
+{
+ return (0x03E00000 & mipsins) >> 21;
+}
+
+static UInt get_FC(UInt mipsins)
+{
+ return (0x000000F0 & mipsins) >> 4;
+}
+
+static UInt get_cond(UInt mipsins)
+{
+ return (0x0000000F & mipsins);
+}
+
+/* for break & syscall */
+static UInt get_code(UInt mipsins)
+{
+ return (0xFFC0 & mipsins) >> 6;
+}
+
+static UInt get_lsb(UInt mipsins)
+{
+ return (0x7C0 & mipsins) >> 6;
+}
+
+static UInt get_msb(UInt mipsins)
+{
+ return (0x0000F800 & mipsins) >> 11;
+}
+
+static UInt get_rot(UInt mipsins)
+{
+ return (0x00200000 & mipsins) >> 21;
+}
+
+static UInt get_rotv(UInt mipsins)
+{
+ return (0x00000040 & mipsins) >> 6;
+}
+
+static UInt get_sel(UInt mipsins)
+{
+ return (0x00000007 & mipsins);
+}
+
+static Bool branch_or_jump(UChar * addr)
+{
+ UInt fmt;
+ UInt cins = getUInt(addr);
+
+ UInt opcode = get_opcode(cins);
+ UInt rt = get_rt(cins);
+ UInt function = get_function(cins);
+
+ /* bgtz, blez, bne, beq, jal */
+ if (opcode == 0x07 || opcode == 0x06 || opcode == 0x05 || opcode == 0x04
+ || opcode == 0x03 || opcode == 0x02) {
+ return True;
+ }
+
+ /* bgez */
+ if (opcode == 0x01 && rt == 0x01) {
+ return True;
+ }
+
+ /* bgezal */
+ if (opcode == 0x01 && rt == 0x11) {
+ return True;
+ }
+
+ /* bltzal */
+ if (opcode == 0x01 && rt == 0x10) {
+ return True;
+ }
+
+ /* bltz */
+ if (opcode == 0x01 && rt == 0x00) {
+ return True;
+ }
+
+ /* jalr */
+ if (opcode == 0x00 && function == 0x09) {
+ return True;
+ }
+
+ /* jr */
+ if (opcode == 0x00 && function == 0x08) {
+ return True;
+ }
+
+ if (opcode == 0x11) {
+ /*bc1f & bc1t */
+ fmt = get_fmt(cins);
+ if (fmt == 0x08) {
+ return True;
+ }
+ }
+
+ return False;
+}
+
+static Bool is_Branch_or_Jump_and_Link(UChar * addr)
+{
+ UInt cins = getUInt(addr);
+
+ UInt opcode = get_opcode(cins);
+ UInt rt = get_rt(cins);
+ UInt function = get_function(cins);
+
+ /* jal */
+ if (opcode == 0x02) {
+ return True;
+ }
+
+ /* bgezal */
+ if (opcode == 0x01 && rt == 0x11) {
+ return True;
+ }
+
+ /* bltzal */
+ if (opcode == 0x01 && rt == 0x10) {
+ return True;
+ }
+
+ /* jalr */
+ if (opcode == 0x00 && function == 0x09) {
+ return True;
+ }
+
+ return False;
+}
+
+static Bool branch_or_link_likely(UChar * addr)
+{
+ UInt cins = getUInt(addr);
+ UInt opcode = get_opcode(cins);
+ UInt rt = get_rt(cins);
+
+ /* bgtzl, blezl, bnel, beql */
+ if (opcode == 0x17 || opcode == 0x16 || opcode == 0x15 || opcode == 0x14)
+ return True;
+
+ /* bgezl */
+ if (opcode == 0x01 && rt == 0x03)
+ return True;
+
+ /* bgezall */
+ if (opcode == 0x01 && rt == 0x13)
+ return True;
+
+ /* bltzall */
+ if (opcode == 0x01 && rt == 0x12)
+ return True;
+
+ /* bltzl */
+ if (opcode == 0x01 && rt == 0x02)
+ return True;
+
+ return False;
+}
+
+/*------------------------------------------------------------*/
+/*--- Helper bits and pieces for creating IR fragments. ---*/
+/*------------------------------------------------------------*/
+
+static IRExpr *mkU8(UInt i)
+{
+ vassert(i < 256);
+ return IRExpr_Const(IRConst_U8((UChar) i));
+}
+
+/* Create an expression node for a 32-bit integer constant */
+static IRExpr *mkU32(UInt i)
+{
+ return IRExpr_Const(IRConst_U32(i));
+}
+
+/* Create an expression node for a 64-bit integer constant */
+static IRExpr *mkU64(ULong i)
+{
+ return IRExpr_Const(IRConst_U64(i));
+}
+
+static IRExpr *mkexpr(IRTemp tmp)
+{
+ return IRExpr_RdTmp(tmp);
+}
+
+static IRExpr *unop(IROp op, IRExpr * a)
+{
+ return IRExpr_Unop(op, a);
+}
+
+static IRExpr *binop(IROp op, IRExpr * a1, IRExpr * a2)
+{
+ return IRExpr_Binop(op, a1, a2);
+}
+
+static IRExpr *triop(IROp op, IRExpr * a1, IRExpr * a2, IRExpr * a3)
+{
+ return IRExpr_Triop(op, a1, a2, a3);
+}
+
+static IRExpr *load(IRType ty, IRExpr * addr)
+{
+ IRExpr *load1 = NULL;
+#if defined (_MIPSEL)
+ load1 = IRExpr_Load(Iend_LE, ty, addr);
+#elif defined (_MIPSEB)
+ load1 = IRExpr_Load(Iend_BE, ty, addr);
+#endif
+ return load1;
+}
+
+/* Add a statement to the list held by "irsb". */
+static void stmt(IRStmt * st)
+{
+ addStmtToIRSB(irsb, st);
+}
+
+static void assign(IRTemp dst, IRExpr * e)
+{
+ stmt(IRStmt_WrTmp(dst, e));
+}
+
+static void store(IRExpr * addr, IRExpr * data)
+{
+#if defined (_MIPSEL)
+ stmt(IRStmt_Store(Iend_LE, addr, data));
+#elif defined (_MIPSEB)
+ stmt(IRStmt_Store(Iend_BE, addr, data));
+#endif
+}
+
+/* Generate a new temporary of the given type. */
+static IRTemp newTemp(IRType ty)
+{
+ vassert(isPlausibleIRType(ty));
+ return newIRTemp(irsb->tyenv, ty);
+}
+
+/* Generate an expression for SRC rotated right by ROT. */
+static IRExpr *genROR32(IRExpr * src, Int rot)
+{
+ vassert(rot >= 0 && rot < 32);
+ if (rot == 0)
+ return src;
+ return binop(Iop_Or32, binop(Iop_Shl32, src, mkU8(32 - rot)),
+ binop(Iop_Shr32, src, mkU8(rot)));
+}
+
+static IRExpr *genRORV32(IRExpr * src, IRExpr * rs)
+{
+ IRTemp t0 = newTemp(Ity_I8);
+ IRTemp t1 = newTemp(Ity_I8);
+
+ assign(t0, unop(Iop_32to8, binop(Iop_And32, rs, mkU32(0x0000001F))));
+ assign(t1, binop(Iop_Sub8, mkU8(32), mkexpr(t0)));
+ return binop(Iop_Or32, binop(Iop_Shl32, src, mkexpr(t1)),
+ binop(Iop_Shr32, src, mkexpr(t0)));
+}
+
+static UInt extend_s_16to32(UInt x)
+{
+ return (UInt) ((((Int) x) << 16) >> 16);
+}
+
+static UInt extend_s_18to32(UInt x)
+{
+ return (UInt) ((((Int) x) << 14) >> 14);
+}
+
+static void jmp_lit( /*MOD*/DisResult* dres,
+ IRJumpKind kind, Addr32 d32 )
+{
+ vassert(dres->whatNext == Dis_Continue);
+ vassert(dres->len == 0);
+ vassert(dres->continueAt == 0);
+ vassert(dres->jk_StopHere == Ijk_INVALID);
+ dres->whatNext = Dis_StopHere;
+ dres->jk_StopHere = kind;
+ stmt( IRStmt_Put( OFFB_PC, mkU32(d32) ) );
+}
+
+/* Fetch a byte from the guest insn stream. */
+static UChar getIByte(Int delta)
+{
+ return guest_code[delta];
+}
+
+static IRExpr *getIReg(UInt iregNo)
+{
+ if (0 == iregNo) {
+ return mode64 ? mkU64(0x0) : mkU32(0x0);
+ } else {
+ IRType ty = mode64 ? Ity_I64 : Ity_I32;
+ vassert(iregNo < 32);
+ return IRExpr_Get(integerGuestRegOffset(iregNo), ty);
+ }
+}
+
+static IRExpr *getHI(void)
+{
+ return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_HI), Ity_I32);
+}
+
+static IRExpr *getLO(void)
+{
+ return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_LO), Ity_I32);
+}
+
+static IRExpr *getFCSR(void)
+{
+ return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_FCSR), Ity_I32);
+}
+
+static void putFCSR(IRExpr * e)
+{
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_FCSR), e));
+}
+
+static IRExpr *getULR(void)
+{
+ return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_ULR), Ity_I32);
+}
+
+static void putIReg(UInt archreg, IRExpr * e)
+{
+ IRType ty = mode64 ? Ity_I64 : Ity_I32;
+ vassert(archreg < 32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == ty);
+ if (archreg != 0)
+ stmt(IRStmt_Put(integerGuestRegOffset(archreg), e));
+}
+
+static void putLO(IRExpr * e)
+{
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_LO), e));
+}
+
+static void putHI(IRExpr * e)
+{
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_HI), e));
+}
+
+static void putPC(IRExpr * e)
+{
+ stmt(IRStmt_Put(OFFB_PC, e));
+}
+
+static IRExpr *mkWidenFrom32(IRType ty, IRExpr * src, Bool sined)
+{
+ vassert(ty == Ity_I32 || ty == Ity_I64);
+ if (ty == Ity_I32)
+ return src;
+ return (sined) ? unop(Iop_32Sto64, src) : unop(Iop_32Uto64, src);
+}
+
+/* Narrow 8/16/32 bit int expr to 8/16/32. Clearly only some
+ of these combinations make sense. */
+static IRExpr *narrowTo(IRType dst_ty, IRExpr * e)
+{
+ IRType src_ty = typeOfIRExpr(irsb->tyenv, e);
+ if (src_ty == dst_ty)
+ return e;
+ if (src_ty == Ity_I32 && dst_ty == Ity_I16)
+ return unop(Iop_32to16, e);
+ if (src_ty == Ity_I32 && dst_ty == Ity_I8)
+ return unop(Iop_32to8, e);
+ if (src_ty == Ity_I64 && dst_ty == Ity_I8) {
+ vassert(mode64);
+ return unop(Iop_64to8, e);
+ }
+ if (src_ty == Ity_I64 && dst_ty == Ity_I16) {
+ vassert(mode64);
+ return unop(Iop_64to16, e);
+ }
+
+ if (vex_traceflags & VEX_TRACE_FE) {
+ vex_printf("\nsrc, dst tys are: ");
+ ppIRType(src_ty);
+ vex_printf(", ");
+ ppIRType(dst_ty);
+ vex_printf("\n");
+ }
+
+ vpanic("narrowTo(mips)");
+ return 0;
+}
+
+static IRExpr *mkNarrowTo32(IRType ty, IRExpr * src)
+{
+ vassert(ty == Ity_I32 || ty == Ity_I64);
+ return ty == Ity_I64 ? unop(Iop_64to32, src) : src;
+}
+
+static IRExpr *getLoFromF64(IRType ty, IRExpr * src)
+{
+ vassert(ty == Ity_F32 || ty == Ity_F64);
+ if (ty == Ity_F64) {
+ IRTemp t0, t1;
+ t0 = newTemp(Ity_I64);
+ t1 = newTemp(Ity_I32);
+ assign(t0, unop(Iop_ReinterpF64asI64, src));
+ assign(t1, unop(Iop_64to32, mkexpr(t0)));
+ return unop(Iop_ReinterpI32asF32, mkexpr(t1));
+ } else
+ return src;
+}
+
+static IRExpr *mkWidenFromF32(IRType ty, IRExpr * src)
+{
+ vassert(ty == Ity_F32 || ty == Ity_F64);
+ return ty == Ity_F64 ? unop(Iop_F32toF64, src) : src;
+}
+
+static IRExpr *dis_branch_likely(IRExpr * guard, UInt imm)
+{
+ ULong branch_offset;
+ IRTemp t0;
+
+ /* PC = PC + (SignExtend(signed_immed_24) << 2)
+ An 18-bit signed offset (the 16-bit offset field shifted left 2 bits)
+ is added to the address of the instruction following
+ the branch (not the branch itself), in the branch delay slot, to form
+ a PC-relative effective target address. */
+ branch_offset = extend_s_18to32(imm << 2);
+
+ t0 = newTemp(Ity_I1);
+ assign(t0, guard);
+
+ stmt(IRStmt_Exit(mkexpr(t0), Ijk_Boring,
+ IRConst_U32(guest_PC_curr_instr + 8), OFFB_PC));
+
+ irsb->jumpkind = Ijk_Boring;
+
+ return mkU32(guest_PC_curr_instr + 4 + branch_offset);
+}
+
+static void dis_branch(Bool link, IRExpr * guard, UInt imm, IRStmt ** set)
+{
+ ULong branch_offset;
+ IRTemp t0;
+
+ if (link) { // LR (GPR31) = addr of the 2nd instr after branch instr
+ putIReg(31, mkU32(guest_PC_curr_instr + 8));
+ }
+
+ /* PC = PC + (SignExtend(signed_immed_24) << 2)
+ An 18-bit signed offset (the 16-bit offset field shifted left 2 bits)
+ is added to the address of the instruction following
+ the branch (not the branch itself), in the branch delay slot, to form
+ a PC-relative effective target address. */
+
+ branch_offset = extend_s_18to32(imm << 2);
+
+ t0 = newTemp(Ity_I1);
+ assign(t0, guard);
+ *set = IRStmt_Exit(mkexpr(t0), link ? Ijk_Call : Ijk_Boring,
+ IRConst_U32(guest_PC_curr_instr + 4 + (UInt) branch_offset),
+ OFFB_PC);
+}
+
+static IRExpr *getFReg(UInt dregNo)
+{
+ vassert(dregNo < 32);
+ IRType ty = mode64 ? Ity_F64 : Ity_F32;
+ return IRExpr_Get(floatGuestRegOffset(dregNo), ty);
+}
+
+static IRExpr *getDReg(UInt dregNo)
+{
+ vassert(dregNo < 32);
+ IRTemp t0 = newTemp(Ity_F32);
+ IRTemp t1 = newTemp(Ity_F32);
+ IRTemp t2 = newTemp(Ity_F64);
+ IRTemp t3 = newTemp(Ity_I32);
+ IRTemp t4 = newTemp(Ity_I32);
+ IRTemp t5 = newTemp(Ity_I64);
+
+ assign(t0, getFReg(dregNo));
+ assign(t1, getFReg(dregNo + 1));
+
+ assign(t3, unop(Iop_ReinterpF32asI32, mkexpr(t0)));
+ assign(t4, unop(Iop_ReinterpF32asI32, mkexpr(t1)));
+ assign(t5, binop(Iop_32HLto64, mkexpr(t4), mkexpr(t3)));
+ assign(t2, unop(Iop_ReinterpI64asF64, mkexpr(t5)));
+
+ return mkexpr(t2);
+}
+
+static void putFReg(UInt dregNo, IRExpr * e)
+{
+ vassert(dregNo < 32);
+ IRType ty = mode64 ? Ity_F64 : Ity_F32;
+ vassert(typeOfIRExpr(irsb->tyenv, e) == ty);
+ stmt(IRStmt_Put(floatGuestRegOffset(dregNo), e));
+}
+
+static void putDReg(UInt dregNo, IRExpr * e)
+{
+ vassert(dregNo < 32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64);
+ IRTemp t1 = newTemp(Ity_F64);
+ IRTemp t4 = newTemp(Ity_I32);
+ IRTemp t5 = newTemp(Ity_I32);
+ IRTemp t6 = newTemp(Ity_I64);
+ assign(t1, e);
+ assign(t6, unop(Iop_ReinterpF64asI64, mkexpr(t1)));
+ assign(t4, unop(Iop_64HIto32, mkexpr(t6))); // hi
+ assign(t5, unop(Iop_64to32, mkexpr(t6))); //lo
+ putFReg(dregNo, unop(Iop_ReinterpI32asF32, mkexpr(t5)));
+ putFReg(dregNo + 1, unop(Iop_ReinterpI32asF32, mkexpr(t4)));
+}
+
+static void setFPUCondCode(IRExpr * e, UInt cc)
+{
+ if (cc == 0) {
+ DIP("setFpu: %d\n", cc);
+ putFCSR(binop(Iop_And32, getFCSR(), mkU32(0xFF7FFFFF)));
+ putFCSR(binop(Iop_Or32, getFCSR(), binop(Iop_Shl32, e, mkU8(23))));
+ } else {
+ DIP("setFpu1: %d\n", cc);
+ putFCSR(binop(Iop_And32, getFCSR(), unop(Iop_Not32,
+ binop(Iop_Shl32, mkU32(0x01000000), mkU8(cc)))));
+ putFCSR(binop(Iop_Or32, getFCSR(), binop(Iop_Shl32, e, mkU8(24 + cc))));
+ }
+}
+
+static IRExpr */* :: Ity_I32 */get_IR_roundingmode(void)
+{
+/*
+ rounding mode | MIPS | IR
+ ------------------------
+ to nearest | 00 | 00
+ to zero | 01 | 11
+ to +infinity | 10 | 10
+ to -infinity | 11 | 01
+*/
+ IRTemp rm_MIPS = newTemp(Ity_I32);
+ /* Last two bits in FCSR are rounding mode. */
+
+ assign(rm_MIPS, binop(Iop_And32, IRExpr_Get(offsetof(VexGuestMIPS32State,
+ guest_FCSR), Ity_I32), mkU32(3)));
+
+ // rm_IR = XOR( rm_MIPS32, (rm_MIPS32 << 1) & 2)
+
+ return binop(Iop_Xor32, mkexpr(rm_MIPS), binop(Iop_And32,
+ binop(Iop_Shl32, mkexpr(rm_MIPS), mkU8(1)), mkU32(2)));
+}
+
+/*********************************************************/
+/*--- Floating Point Compare ---*/
+/*********************************************************/
+static Bool dis_instr_CCondFmt(UInt cins)
+{
+ IRTemp t0, t1, t2, t3;
+ IRTemp ccIR = newTemp(Ity_I32);
+ IRTemp ccMIPS = newTemp(Ity_I32);
+ UInt FC = get_FC(cins);
+ UInt fmt = get_fmt(cins);
+ UInt fs = get_fs(cins);
+ UInt ft = get_ft(cins);
+ UInt cond = get_cond(cins);
+
+ if (FC == 0x3) { // C.cond.fmt
+ UInt fpc_cc = get_fpc_cc(cins);
+ switch (fmt) {
+ case 0x10: { //C.cond.S
+ DIP("C.cond.S %d f%d, f%d\n", fpc_cc, fs, ft);
+ t0 = newTemp(Ity_I32);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+
+ assign(ccIR, binop(Iop_CmpF64, unop(Iop_F32toF64, getFReg(fs)),
+ unop(Iop_F32toF64, getFReg(ft))));
+ /* Map compare result from IR to MIPS */
+ /*
+ FP cmp result | MIPS | IR
+ --------------------------
+ UN | 0x1 | 0x45
+ EQ | 0x2 | 0x40
+ GT | 0x4 | 0x00
+ LT | 0x8 | 0x01
+ */
+
+ // ccMIPS = Shl(1, (~(ccIR>>5) & 2)
+ // | ((ccIR ^ (ccIR>>6)) & 1)
+ assign(ccMIPS, binop(Iop_Shl32, mkU32(1), unop(Iop_32to8,
+ binop(Iop_Or32, binop(Iop_And32, unop(Iop_Not32,
+ binop(Iop_Shr32, mkexpr(ccIR), mkU8(5))), mkU32(2)),
+ binop(Iop_And32, binop(Iop_Xor32, mkexpr(ccIR),
+ binop(Iop_Shr32, mkexpr(ccIR), mkU8(6))),
+ mkU32(1))))));
+ assign(t0, binop(Iop_And32, mkexpr(ccMIPS), mkU32(0x1))); // UN
+ assign(t1, binop(Iop_And32, binop(Iop_Shr32, mkexpr(ccMIPS),
+ mkU8(0x1)), mkU32(0x1))); // EQ
+ assign(t2, binop(Iop_And32, unop(Iop_Not32, binop(Iop_Shr32,
+ mkexpr(ccMIPS), mkU8(0x2))), mkU32(0x1))); // NGT
+ assign(t3, binop(Iop_And32, binop(Iop_Shr32, mkexpr(ccMIPS),
+ mkU8(0x3)), mkU32(0x1))); // LT
+
+ switch (cond) {
+ case 0x0:
+ setFPUCondCode(mkU32(0), fpc_cc);
+ break;
+ case 0x1:
+ DIP("unorderd: %d\n", fpc_cc);
+ setFPUCondCode(mkexpr(t0), fpc_cc);
+ break;
+ case 0x2:
+ setFPUCondCode(mkexpr(t1), fpc_cc);
+ break;
+ case 0x3:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t0), mkexpr(t1)),
+ fpc_cc);
+ break;
+ case 0x4:
+ setFPUCondCode(mkexpr(t3), fpc_cc);
+ break;
+ case 0x5:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t0), mkexpr(t3)),
+ fpc_cc);
+ break;
+ case 0x6:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t3), mkexpr(t1)),
+ fpc_cc);
+ break;
+ case 0x7:
+ setFPUCondCode(mkexpr(t2), fpc_cc);
+ break;
+ case 0x8:
+ setFPUCondCode(mkU32(0), fpc_cc);
+ break;
+ case 0x9:
+ setFPUCondCode(mkexpr(t0), fpc_cc);
+ break;
+ case 0xA:
+ setFPUCondCode(mkexpr(t1), fpc_cc);
+ break;
+ case 0xB:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t0), mkexpr(t1)),
+ fpc_cc);
+ break;
+ case 0xC:
+ setFPUCondCode(mkexpr(t3), fpc_cc);
+ break;
+ case 0xD:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t0), mkexpr(t3)),
+ fpc_cc);
+ break;
+ case 0xE:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t3), mkexpr(t1)),
+ fpc_cc);
+ break;
+ case 0xF:
+ setFPUCondCode(mkexpr(t2), fpc_cc);
+ break;
+
+ default:
+ return False;
+ }
+ }
+ break;
+
+ case 0x11: //C.cond.D
+ DIP("C.%d.D %d f%d, f%d\n", cond, fpc_cc, fs, ft);
+ t0 = newTemp(Ity_I32);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ assign(ccIR, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
+ /* Map compare result from IR to MIPS */
+ /*
+ FP cmp result | MIPS | IR
+ --------------------------
+ UN | 0x1 | 0x45
+ EQ | 0x2 | 0x40
+ GT | 0x4 | 0x00
+ LT | 0x8 | 0x01
+ */
+
+ // ccMIPS = Shl(1, (~(ccIR>>5) & 2)
+ // | ((ccIR ^ (ccIR>>6)) & 1)
+ assign(ccMIPS, binop(Iop_Shl32, mkU32(1), unop(Iop_32to8,
+ binop(Iop_Or32, binop(Iop_And32, unop(Iop_Not32,
+ binop(Iop_Shr32, mkexpr(ccIR), mkU8(5))), mkU32(2)),
+ binop(Iop_And32, binop(Iop_Xor32, mkexpr(ccIR),
+ binop(Iop_Shr32, mkexpr(ccIR), mkU8(6))),
+ mkU32(1))))));
+
+ assign(t0, binop(Iop_And32, mkexpr(ccMIPS), mkU32(0x1))); // UN
+ assign(t1, binop(Iop_And32, binop(Iop_Shr32, mkexpr(ccMIPS),
+ mkU8(0x1)), mkU32(0x1))); // EQ
+ assign(t2, binop(Iop_And32, unop(Iop_Not32, binop(Iop_Shr32,
+ mkexpr(ccMIPS), mkU8(0x2))), mkU32(0x1))); // NGT
+ assign(t3, binop(Iop_And32, binop(Iop_Shr32, mkexpr(ccMIPS),
+ mkU8(0x3)), mkU32(0x1))); // LT
+
+ switch (cond) {
+ case 0x0:
+ setFPUCondCode(mkU32(0), fpc_cc);
+ break;
+ case 0x1:
+ DIP("unorderd: %d\n", fpc_cc);
+ setFPUCondCode(mkexpr(t0), fpc_cc);
+ break;
+ case 0x2:
+ setFPUCondCode(mkexpr(t1), fpc_cc);
+ break;
+ case 0x3:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t0), mkexpr(t1)),
+ fpc_cc);
+ break;
+ case 0x4:
+ setFPUCondCode(mkexpr(t3), fpc_cc);
+ break;
+ case 0x5:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t0), mkexpr(t3)),
+ fpc_cc);
+ break;
+ case 0x6:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t3), mkexpr(t1)),
+ fpc_cc);
+ break;
+ case 0x7:
+ setFPUCondCode(mkexpr(t2), fpc_cc);
+ break;
+ case 0x8:
+ setFPUCondCode(mkU32(0), fpc_cc);
+ break;
+ case 0x9:
+ setFPUCondCode(mkexpr(t0), fpc_cc);
+ break;
+ case 0xA:
+ setFPUCondCode(mkexpr(t1), fpc_cc);
+ break;
+ case 0xB:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t0), mkexpr(t1)),
+ fpc_cc);
+ break;
+ case 0xC:
+ setFPUCondCode(mkexpr(t3), fpc_cc);
+ break;
+ case 0xD:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t0), mkexpr(t3)),
+ fpc_cc);
+ break;
+ case 0xE:
+ setFPUCondCode(binop(Iop_Or32, mkexpr(t3), mkexpr(t1)),
+ fpc_cc);
+ break;
+ case 0xF:
+ setFPUCondCode(mkexpr(t2), fpc_cc);
+ break;
+ default:
+ return False;
+ }
+ break;
+
+ default:
+ return False;
+ }
+ } else {
+ return False;
+ }
+
+ return True;
+}
+
+/*------------------------------------------------------------*/
+/*--- Disassemble a single instruction ---*/
+/*------------------------------------------------------------*/
+
+/* Disassemble a single instruction into IR. The instruction is
+ located in host memory at guest_instr, and has guest IP of
+ guest_PC_curr_instr, which will have been set before the call
+ here. */
+
+static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
+ Addr64),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ Long delta64,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo )
+{
+ IRTemp t0, t1, t2, t3, t4, t5, t6, t7, t8;
+ UInt opcode, cins, rs, rt, rd, sa, ft, fs, fd, fmt, tf, nd, function,
+ trap_code, imm, instr_index, p, msb, lsb, size, rot, sel;
+
+ DisResult dres;
+
+ static IRExpr *lastn = NULL; /* last jump addr */
+ static IRStmt *bstmt = NULL; /* branch (Exit) stmt */
+
+ /* The running delta */
+ Int delta = (Int) delta64;
+
+ /* Holds eip at the start of the insn, so that we can print
+ consistent error messages for unimplemented insns. */
+ Int delta_start = delta;
+
+ /* Are we in a delay slot ? */
+ Bool delay_slot_branch, likely_delay_slot, delay_slot_jump;
+
+ /* Set result defaults. */
+ dres.whatNext = Dis_Continue;
+ dres.len = 0;
+ dres.continueAt = 0;
+ dres.jk_StopHere = Ijk_INVALID;
+
+ delay_slot_branch = likely_delay_slot = delay_slot_jump = False;
+
+ UChar *code = (UChar *) (guest_code + delta);
+ cins = getUInt(code);
+
+ if (delta != 0) {
+ if (branch_or_jump(guest_code + delta - 4)) {
+ if (lastn == NULL && bstmt == NULL) {
+ DIP("Info: jump to delay slot insn...\n");
+ } else {
+ dres.whatNext = Dis_StopHere;
+
+ DIP("lastn = %p bstmt = %p\n", lastn, bstmt);
+ if (lastn != NULL) {
+ DIP("delay slot jump\n");
+ if (vex_traceflags & VEX_TRACE_FE)
+ ppIRExpr(lastn);
+ delay_slot_jump = True;
+ } else if (bstmt != NULL) {
+ DIP("\ndelay slot branch\n");
+ delay_slot_branch = True;
+ }
+ DIP("delay slot\n");
+ }
+ }
+
+ if (branch_or_link_likely(guest_code + delta - 4)) {
+ likely_delay_slot = True;
+ }
+ }
+
+ /* Spot "Special" instructions (see comment at top of file). */
+ {
+ /* Spot the 16-byte preamble:
+ ****mips32****
+ "srl $0, $0, 13
+ "srl $0, $0, 29
+ "srl $0, $0, 3
+ "srl $0, $0, 19 */
+ UInt word1 = 0x00000342;
+ UInt word2 = 0x00000742;
+ UInt word3 = 0x000000C2;
+ UInt word4 = 0x000004C2;
+ if (getUInt(code + 0) == word1 && getUInt(code + 4) == word2 &&
+ getUInt(code + 8) == word3 && getUInt(code + 12) == word4) {
+ /* Got a "Special" instruction preamble. Which one is it? */
+ if (getUInt(code + 16) == 0x01ad6825 /* or t5, t5, t5 */ ) {
+ /* v0 = client_request ( t9 ) */
+ DIP("v0 = client_request ( t9 )\n");
+ putPC(mkU32(guest_PC_curr_instr + 20));
+ dres.jk_StopHere = Ijk_ClientReq;
+ dres.whatNext = Dis_StopHere;
+
+ goto decode_success;
+ } else if (getUInt(code + 16) == 0x01ce7025 /* or t6,t6,t6 */ ) {
+ /* t9 = guest_NRADDR */
+ DIP("t9 = guest_NRADDR\n");
+ dres.len = 20;
+ delta += 20;
+ putIReg(11, IRExpr_Get(offsetof(VexGuestMIPS32State, guest_NRADDR),
+ Ity_I32));
+ goto decode_success;
+ } else if (getUInt(code + 16) == 0x01ef7825/* or t7,t7,t7 */ ) {
+ /* branch-and-link-to-noredir t9 */
+ DIP("branch-and-link-to-noredir t9\n");
+ putIReg(31, mkU32(guest_PC_curr_instr + 20));
+ putPC(getIReg(25));
+ dres.jk_StopHere = Ijk_NoRedir;
+ dres.whatNext = Dis_StopHere;
+ goto decode_success;
+ }
+
+ /* We don't know what it is. Set opc1/opc2 so decode_failure
+ can print the insn following the Special-insn preamble. */
+ delta += 16;
+ goto decode_failure;
+ /*NOTREACHED*/}
+ }
+
+ opcode = get_opcode(cins);
+ imm = get_imm(cins);
+ rs = get_rs(cins);
+ rt = get_rt(cins);
+ rd = get_rd(cins);
+ sa = get_sa(cins);
+ fs = get_fs(cins);
+ fd = get_fd(cins);
+ ft = get_ft(cins);
+ tf = get_tf(cins);
+ nd = get_nd(cins);
+ sel = get_sel(cins);
+ fmt = get_fmt(cins);
+ instr_index = get_instr_index(cins);
+ trap_code = get_code(cins);
+ function = get_function(cins);
+ IRType ty = mode64 ? Ity_I64 : Ity_I32;
+ IRType tyF = mode64 ? Ity_F64 : Ity_F32;
+
+ DIP("[cins = 0x%08x] ", cins);
+
+ switch (opcode) {
+
+ case 0x03: /* JAL */
+ DIP("jal 0x%x", instr_index);
+ putIReg(31, mkU32(guest_PC_curr_instr + 8));
+ t0 = newTemp(ty);
+ assign(t0, mkU32((guest_PC_curr_instr & 0xF0000000) |
+ (instr_index << 2)));
+ lastn = mkexpr(t0);
+ break;
+ case 0x02: /* J */
+ DIP("j 0x%x", instr_index);
+ t0 = newTemp(ty);
+ assign(t0, mkU32((guest_PC_curr_instr & 0xF0000000) |
+ (instr_index << 2)));
+ lastn = mkexpr(t0);
+ break;
+
+ case 0x11: /* COP1 */
+ {
+ UInt bc1_cc = get_bc1_cc(cins);
+ if (0x08 == fmt) {
+ switch (fmt) {
+ case 0x08: //BC
+ {
+ DIP("tf: %d, nd: %d\n", tf, nd);
+ //FcConditionalCode(bc1_cc)
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I1);
+
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(0),
+ mkU32(bc1_cc))));
+ assign(t2, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t1)),
+ binop(Iop_And32, binop(Iop_Shr32, getFCSR(),
+ mkU8(24 + bc1_cc)), mkU32(0x1)), binop(Iop_And32,
+ binop(Iop_Shr32, getFCSR(), mkU8(23)),
+ mkU32(0x1))));
+
+ if (tf == 1 && nd == 0) {
+ //branch on true
+ DIP("bc1t %d, %d", bc1_cc, imm);
+ assign(t3, binop(Iop_CmpEQ32, mkU32(1), mkexpr(t2)));
+ dis_branch(False, mkexpr(t3), imm, &bstmt);
+ break;
+ } else if (tf == 0 && nd == 0) {
+ //branch on false
+ DIP("bc1f %d, %d", bc1_cc, imm);
+ assign(t3, binop(Iop_CmpEQ32, mkU32(0), mkexpr(t2)));
+ dis_branch(False, mkexpr(t3), imm, &bstmt);
+ break;
+ } else if (nd == 1 && tf == 0) {
+ DIP("bc1fl %d, %d", bc1_cc, imm);
+ lastn = dis_branch_likely(binop(Iop_CmpNE32, mkexpr(t2),
+ mode64 ? mkU64(0x0) : mkU32(0x0)), imm);
+ break;
+ } else if (nd == 1 && tf == 1) {
+ DIP("bc1tl %d, %d", bc1_cc, imm);
+ lastn = dis_branch_likely(binop(Iop_CmpEQ32, mkexpr(t2),
+ mkU32(0x0)), imm);
+ break;
+ } else
+ goto decode_failure;
+ }
+
+ default:
+ goto decode_failure;
+ }
+ } else {
+ switch (function) {
+
+ case 0x4: //SQRT.fmt
+ {
+ switch (fmt) {
+ case 0x10: //S
+ {
+ IRExpr *rm = get_IR_roundingmode();
+ putFReg(fd, mkWidenFromF32(tyF, binop(Iop_SqrtF32, rm,
+ getLoFromF64(tyF, getFReg(fs)))));
+ }
+ break;
+ case 0x11: //D
+ {
+ IRExpr *rm = get_IR_roundingmode();
+ putDReg(fd, binop(Iop_SqrtF64, rm, getDReg(fs)));
+ }
+ break;
+ }
+ }
+ break;
+ case 0x5: //abs.fmt
+ switch (fmt) {
+ case 0x10: //S
+ DIP("abs.s f%d, f%d\n", fd, fs);
+ putFReg(fd, mkWidenFromF32(tyF, unop(Iop_AbsF32,
+ getLoFromF64(tyF, getFReg(fs)))));
+ break;
+ case 0x11: //D
+ DIP("abs.d f%d, f%d\n", fd, fs);
+ putDReg(fd, unop(Iop_AbsF64, getDReg(fs)));
+ break;
+ default:
+ goto decode_failure;
+ }
+ break; //case 0x5
+
+ case 0x02: // MUL.fmt
+ switch (fmt) {
+ case 0x11: // D
+ {
+ DIP("mul.d f%d, f%d, f%d", fd, fs, ft);
+ IRExpr *rm = get_IR_roundingmode();
+ putDReg(fd, triop(Iop_MulF64, rm, getDReg(fs),
+ getDReg(ft)));
+ break;
+ }
+ case 0x10: // S
+ {
+ DIP("mul.s f%d, f%d, f%d", fd, fs, ft);
+ IRExpr *rm = get_IR_roundingmode();
+ putFReg(fd, mkWidenFromF32(tyF, triop(Iop_MulF32, rm,
+ getLoFromF64(tyF, getFReg(fs)),
+ getLoFromF64(tyF, getFReg(ft)))));
+ break;
+ }
+ default:
+ goto decode_failure;
+ }
+ break; // MUL.fmt
+
+ case 0x03: // DIV.fmt
+ switch (fmt) {
+ case 0x11: // D
+ {
+ DIP("div.d f%d, f%d, f%d", fd, fs, ft);
+ IRExpr *rm = get_IR_roundingmode();
+ putDReg(fd, triop(Iop_DivF64, rm, getDReg(fs),
+ getDReg(ft)));
+ break;
+ }
+ case 0x10: // S
+ {
+ DIP("div.s f%d, f%d, f%d", fd, fs, ft);
+ IRExpr *rm = get_IR_roundingmode();
+ putFReg(fd, mkWidenFromF32(tyF, triop(Iop_DivF32, rm,
+ getLoFromF64(tyF, getFReg(fs)),
+ getLoFromF64(tyF, getFReg(ft)))));
+ break;
+ }
+ default:
+ goto decode_failure;
+ }
+ break; // DIV.fmt
+
+ case 0x01: // SUB.fmt
+ switch (fmt) {
+ case 0x11: // D
+ {
+ DIP("sub.d f%d, f%d, f%d", fd, fs, ft);
+ IRExpr *rm = get_IR_roundingmode();
+ putDReg(fd, triop(Iop_SubF64, rm, getDReg(fs), getDReg(ft)));
+ break;
+ }
+ case 0x10: // S
+ {
+ DIP("sub.s f%d, f%d, f%d", fd, fs, ft);
+ IRExpr *rm = get_IR_roundingmode();
+ putFReg(fd, mkWidenFromF32(tyF, triop(Iop_SubF32, rm,
+ getLoFromF64(tyF, getFReg(fs)),
+ getLoFromF64(tyF, getFReg(ft)))));
+ break;
+ }
+ default:
+ goto decode_failure;
+ }
+ break; // SUB.fmt
+
+ case 0x06: // MOV.fmt
+ switch (fmt) {
+ case 0x11: // D
+ /* TODO: Check this for 64 bit FPU registers. */
+ DIP("mov.d f%d, f%d", fd, fs);
+ putFReg(fd, getFReg(fs));
+ putFReg(fd + 1, getFReg(fs + 1));
+ break;
+ case 0x10: // S
+ DIP("mov.s f%d, f%d", fd, fs);
+ putFReg(fd, getFReg(fs));
+ break;
+ default:
+ goto decode_failure;
+ }
+ break; // MOV.fmt
+
+ case 0x7: //neg.fmt
+ switch (fmt) {
+ case 0x10: //S
+ DIP("neg.s f%d, f%d", fd, fs);
+ putFReg(fd, mkWidenFromF32(tyF, unop(Iop_NegF32,
+ getLoFromF64(tyF, getFReg(fs)))));
+ break;
+ case 0x11: //D
+ DIP("neg.d f%d, f%d", fd, fs);
+ putDReg(fd, unop(Iop_NegF64, getDReg(fs)));
+ break;
+ default:
+ goto decode_failure;
+ }
+ break; //case 0x7
+
+ case 0x15: //RECIP.fmt
+ switch (fmt) {
+ case 0x10:
+ { //S
+ DIP("recip.s f%d, f%d\n", fd, fs);
+ IRExpr *rm = get_IR_roundingmode();
+ putFReg(fd, mkWidenFromF32(tyF, triop(Iop_DivF32,
+ rm, unop(Iop_ReinterpI32asF32,
+ mkU32(0x3F800000)), getLoFromF64(tyF,
+ getFReg(fs)))));
+ break;
+ }
+ case 0x11:
+ { //D
+ DIP("recip.d f%d, f%d\n", fd, fs);
+ IRExpr *rm = get_IR_roundingmode();
+ putDReg(fd, triop(Iop_DivF64, rm,
+ unop(Iop_ReinterpI64asF64,
+ mkU64(0x3FF0000000000000ULL)), getDReg(fs)));
+ break;
+ }
+ default:
+ goto decode_failure;
+
+ }
+ break; //case 0x15
+
+ case 0x13: //MOVN.fmt
+ switch (fmt) {
+ case 0x10: // S
+ DIP("movn.s f%d, f%d, r%d", fd, fs, rt);
+
+ t1 = newTemp(Ity_F64);
+ t2 = newTemp(Ity_F64);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_F64);
+
+ assign(t1, unop(Iop_F32toF64, getFReg(fs)));
+ assign(t2, unop(Iop_F32toF64, getFReg(fd)));
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpNE32, mkU32(0),
+ getIReg(rt))));
+
+ assign(t4, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ mkexpr(t2), mkexpr(t1)));
+
+ putFReg(fd, binop(Iop_F64toF32, get_IR_roundingmode(),
+ mkexpr(t4)));
+ break;
+ case 0x11: // D
+ DIP("movn.d f%d, f%d, r%d", fd, fs, rt);
+
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_F64);
+
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpNE32, mkU32(0),
+ getIReg(rt))));
+ putDReg(fd, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ getDReg(fd), getDReg(fs)));
+ break;
+ default:
+ goto decode_failure;
+ }
+ break; // MOVN.fmt
+
+ case 0x12: //MOVZ.fmt
+ switch (fmt) {
+ case 0x10: // S
+ DIP("movz.s f%d, f%d, r%d", fd, fs, rt);
+
+ t1 = newTemp(Ity_F64);
+ t2 = newTemp(Ity_F64);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_F64);
+
+ assign(t1, unop(Iop_F32toF64, getFReg(fs)));
+ assign(t2, unop(Iop_F32toF64, getFReg(fd)));
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(0),
+ getIReg(rt))));
+ assign(t4, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ mkexpr(t2), mkexpr(t1)));
+
+ putFReg(fd, binop(Iop_F64toF32, get_IR_roundingmode(),
+ mkexpr(t4)));
+
+ break;
+ case 0x11: // D
+ DIP("movz.d f%d, f%d, r%d", fd, fs, rt);
+
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_F64);
+
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(0),
+ getIReg(rt))));
+ putDReg(fd, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ getDReg(fd), getDReg(fs)));
+ break;
+ default:
+ goto decode_failure;
+ }
+ break; // MOVZ.fmt
+
+ case 0x11: // MOVT.fmt
+ if (tf == 1) {
+ UInt mov_cc = get_mov_cc(cins);
+ switch (fmt) // MOVCF = 010001
+ {
+ case 0x11: // D
+ DIP("movt.d f%d, f%d, %d", fd, fs, mov_cc);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_F64);
+
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(0),
+ mkU32(mov_cc))));
+ assign(t2, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t1)),
+ binop(Iop_And32, binop(Iop_Shr32, getFCSR(),
+ mkU8(24 + mov_cc)), mkU32(0x1)),
+ binop(Iop_And32, binop(Iop_Shr32, getFCSR(),
+ mkU8(23)), mkU32(0x1))));
+
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(1),
+ mkexpr(t2))));
+ assign(t4, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ getDReg(fs), getDReg(fd)));
+ putDReg(fd, mkexpr(t4));
+ break;
+ case 0x10: // S
+ DIP("movt.s f%d, f%d, %d", fd, fs, mov_cc);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_F64);
+ t5 = newTemp(Ity_F64);
+ t6 = newTemp(Ity_F64);
+ t7 = newTemp(Ity_I64);
+
+ assign(t5, unop(Iop_F32toF64, getFReg(fs)));
+ assign(t6, unop(Iop_F32toF64, getFReg(fd)));
+
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(0),
+ mkU32(mov_cc))));
+ assign(t2, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t1)),
+ binop(Iop_And32, binop(Iop_Shr32,
+ getFCSR(), mkU8(24 + mov_cc)),
+ mkU32(0x1)), binop(Iop_And32,
+ binop(Iop_Shr32, getFCSR(),
+ mkU8(23)), mkU32(0x1))));
+
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(1),
+ mkexpr(t2))));
+ assign(t4, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ mkexpr(t5), mkexpr(t6)));
+
+ putFReg(fd, binop(Iop_F64toF32, get_IR_roundingmode(),
+ mkexpr(t4)));
+ break;
+ default:
+ goto decode_failure;
+ }
+ } else if (tf == 0) //movf.fmt
+ {
+ UInt mov_cc = get_mov_cc(cins);
+ switch (fmt) // MOVCF = 010001
+ {
+ case 0x11: // D
+ DIP("movf.d f%d, f%d, %d", fd, fs, mov_cc);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_F64);
+
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32,
+ mkU32(0), mkU32(mov_cc))));
+ assign(t2, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t1)),
+ binop(Iop_And32, binop(Iop_Shr32, getFCSR(),
+ mkU8(24 + mov_cc)), mkU32(0x1)),
+ binop(Iop_And32, binop(Iop_Shr32, getFCSR(),
+ mkU8(23)), mkU32(0x1))));
+
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(1),
+ mkexpr(t2))));
+ assign(t4, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ getDReg(fd), getDReg(fs)));
+ putDReg(fd, mkexpr(t4));
+ break;
+ case 0x10: // S
+ DIP("movf.s f%d, f%d, %d", fd, fs, mov_cc);
+ {
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_F64);
+ t5 = newTemp(Ity_F64);
+ t6 = newTemp(Ity_F64);
+
+ assign(t5, unop(Iop_F32toF64, getFReg(fs)));
+ assign(t6, unop(Iop_F32toF64, getFReg(fd)));
+
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(0),
+ mkU32(mov_cc))));
+ assign(t2, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t1)),
+ binop(Iop_And32, binop(Iop_Shr32, getFCSR(),
+ mkU8(24 + mov_cc)), mkU32(0x1)),
+ binop(Iop_And32, binop(Iop_Shr32, getFCSR(),
+ mkU8(23)), mkU32(0x1))));
+
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(1),
+ mkexpr(t2))));
+ assign(t4, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ mkexpr(t6), mkexpr(t5)));
+ putFReg(fd, binop(Iop_F64toF32, get_IR_roundingmode(),
+ mkexpr(t4)));
+ }
+ break;
+ default:
+ goto decode_failure;
+ }
+ }
+
+ break; // MOVT.fmt
+
+ case 0x0: //add.fmt
+ switch (fmt) {
+ case 0x10: //S
+ {
+ DIP("add.s f%d, f%d, f%d\n", fd, fs, ft);
+ IRExpr *rm = get_IR_roundingmode();
+ putFReg(fd, mkWidenFromF32(tyF, triop(Iop_AddF32, rm,
+ getLoFromF64(tyF, getFReg(fs)),
+ getLoFromF64(tyF, getFReg(ft)))));
+ break;
+ }
+ case 0x11: //D
+ {
+ DIP("add.d f%d, f%d, f%d\n", fd, fs, ft);
+ IRExpr *rm = get_IR_roundingmode();
+ putDReg(fd, triop(Iop_AddF64, rm, getDReg(fs),
+ getDReg(ft)));
+ break;
+ }
+
+ case 0x4: //MTC1 (Move Word to Floating Point)
+ DIP("mtc1 r%d, f%d", rt, fs);
+ putFReg(fs, unop(Iop_ReinterpI32asF32, getIReg(rt)));
+ break;
+
+ case 0x0: //MFC1
+ DIP("mfc1 r%d, f%d", rt, fs);
+ putIReg(rt, unop(Iop_ReinterpF32asI32, getFReg(fs)));
+ break;
+
+ case 0x6: //CTC1
+ DIP("ctc1 r%d, f%d", rt, fs);
+ t0 = newTemp(Ity_I32);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_I32);
+ t5 = newTemp(Ity_I32);
+ t6 = newTemp(Ity_I32);
+ assign(t0, mkNarrowTo32(ty, getIReg(rt)));
+ if (fs == 25) { //FCCR
+ assign(t1, binop(Iop_Shl32, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x000000FE)), mkU8(24)));
+ assign(t2, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x01000000)));
+ assign(t3, binop(Iop_Shl32, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x00000001)), mkU8(23)));
+ assign(t4, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x007FFFFF)));
+ putFCSR(binop(Iop_Or32, binop(Iop_Or32, mkexpr(t1),
+ mkexpr(t2)), binop(Iop_Or32, mkexpr(t3),
+ mkexpr(t4))));
+ } else if (fs == 26) { //FEXR
+ assign(t1, binop(Iop_And32, getFCSR(), mkU32(0xFFFC0000)));
+ assign(t2, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x0003F000)));
+ assign(t3, binop(Iop_And32, getFCSR(), mkU32(0x00000F80)));
+ assign(t4, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x0000007C)));
+ assign(t5, binop(Iop_And32, getFCSR(), mkU32(0x00000003)));
+ putFCSR(binop(Iop_Or32, binop(Iop_Or32, binop(Iop_Or32,
+ mkexpr(t1), mkexpr(t2)), binop(Iop_Or32,
+ mkexpr(t3), mkexpr(t4))), mkexpr(t5)));
+ } else if (fs == 28) {
+ assign(t1, binop(Iop_And32, getFCSR(), mkU32(0xFE000000)));
+ assign(t2, binop(Iop_Shl32, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x00000002)), mkU8(22)));
+ assign(t3, binop(Iop_And32, getFCSR(), mkU32(0x00FFF000)));
+ assign(t4, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x00000F80)));
+ assign(t5, binop(Iop_And32, getFCSR(), mkU32(0x0000007C)));
+ assign(t6, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x00000003)));
+ putFCSR(binop(Iop_Or32, binop(Iop_Or32, binop(Iop_Or32,
+ mkexpr(t1), mkexpr(t2)), binop(Iop_Or32,
+ mkexpr(t3), mkexpr(t4))), binop(Iop_Or32,
+ mkexpr(t5), mkexpr(t6))));
+ } else if (fs == 31) {
+ putFCSR(mkexpr(t0));
+ }
+ break;
+ case 0x2: //CFC1
+ DIP("cfc1 r%d, f%d", rt, fs);
+ t0 = newTemp(Ity_I32);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_I32);
+ t5 = newTemp(Ity_I32);
+ t6 = newTemp(Ity_I32);
+ assign(t0, getFCSR());
+ if (fs == 0) {
+ putIReg(rt, mkWidenFrom32(ty,
+ IRExpr_Get(offsetof(VexGuestMIPS32State,
+ guest_FIR),
+ Ity_I32),
+ False));
+ } else if (fs == 25) {
+ assign(t1, mkU32(0x000000FF));
+ assign(t2, binop(Iop_Shr32, binop(Iop_And32, mkexpr(t0),
+ mkU32(0xFE000000)), mkU8(25)));
+ assign(t3, binop(Iop_Shr32, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x00800000)), mkU8(23)));
+ putIReg(rt, mkWidenFrom32(ty, binop(Iop_Or32,
+ binop(Iop_Or32, mkexpr(t1), mkexpr(t2)),
+ mkexpr(t3)), False));
+ } else if (fs == 26) {
+ assign(t1, mkU32(0xFFFFF07C));
+ assign(t2, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x0003F000)));
+ assign(t3, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x0000007C)));
+ putIReg(rt, mkWidenFrom32(ty, binop(Iop_Or32,
+ binop(Iop_Or32, mkexpr(t1), mkexpr(t2)),
+ mkexpr(t3)), False));
+ } else if (fs == 28) {
+ assign(t1, mkU32(0x00000F87));
+ assign(t2, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x00000F83)));
+ assign(t3, binop(Iop_Shr32, binop(Iop_And32, mkexpr(t0),
+ mkU32(0x01000000)), mkU8(22)));
+ putIReg(rt, mkWidenFrom32(ty, binop(Iop_Or32,
+ binop(Iop_Or32, mkexpr(t1), mkexpr(t2)),
+ mkexpr(t3)), False));
+ } else if (fs == 31) {
+ putIReg(rt, mkWidenFrom32(ty, getFCSR(), False));
+ }
+ break;
+ default:
+ goto decode_failure;
+ }
+ break; //case 0x0: //add.fmt
+
+ case 0x21: //CVT.D
+ switch (fmt) {
+ case 0x10: //S
+ DIP("cvt.d.s f%d, f%d", fd, fs);
+ putDReg(fd, unop(Iop_F32toF64, getFReg(fs)));
+ break;
+
+ case 0x14:
+ { //W
+ DIP("cvt.d.w %d, %d\n", fd, fs);
+ t0 = newTemp(Ity_I32);
+ assign(t0, unop(Iop_ReinterpF32asI32, getFReg(fs)));
+ putDReg(fd, unop(Iop_I32StoF64, mkexpr(t0)));
+ }
+ break;
+
+ default:
+ goto decode_failure;
+ }
+ break; //CVT.D
+
+ case 0x20: //cvt.s
+ switch (fmt) {
+ case 0x14: //W
+ DIP("cvt.s.w %d, %d\n", fd, fs);
+ t0 = newTemp(Ity_I32);
+ assign(t0, unop(Iop_ReinterpF32asI32, getFReg(fs)));
+ putFReg(fd, binop(Iop_I32StoF32, get_IR_roundingmode(),
+ mkexpr(t0)));
+ break;
+
+ case 0x11: //D
+ DIP("cvt.s.d %d, %d\n", fd, fs);
+ putFReg(fd, binop(Iop_F64toF32, get_IR_roundingmode(),
+ getDReg(fs)));
+ break;
+
+ default:
+ goto decode_failure;
+ }
+ break; //cvt.s
+
+ case 0x24: //cvt.w
+ switch (fmt) {
+ case 0x10: //S
+ DIP("cvt.w.s %d, %d\n", fd, fs);
+ putFReg(fd, binop(Iop_RoundF32toInt, get_IR_roundingmode(),
+ getFReg(fs)));
+ break;
+
+ case 0x11:
+ { //D
+ DIP("cvt.w.d %d, %d\n", fd, fs);
+ t0 = newTemp(Ity_I32);
+
+ assign(t0, binop(Iop_F64toI32S, get_IR_roundingmode(),
+ getDReg(fs)));
+
+ putFReg(fd, unop(Iop_ReinterpI32asF32, mkexpr(t0)));
+ }
+ break;
+
+ default:
+ goto decode_failure;
+
+ }
+ break;
+
+ case 0x09: //TRUNC.L
+ switch (fmt) {
+ case 0x10: //S
+ DIP("trunc.l.s %d, %d\n", fd, fs);
+ goto decode_failure;
+
+ case 0x11: //D
+ DIP("trunc.l.d %d, %d\n", fd, fs);
+ goto decode_failure;
+
+ default:
+ goto decode_failure;
+
+ }
+ break; //trunc.l
+
+ case 0x0C: //ROUND.W.fmt
+ switch (fmt) {
+ case 0x10: //S
+ DIP("round.w.s f%d, f%d\n", fd, fs);
+ putFReg(fd, binop(Iop_RoundF32toInt, mkU32(0x0),
+ getFReg(fs)));
+ break;
+
+ case 0x11: //D
+ DIP("round.w.d f%d, f%d\n", fd, fs);
+ t0 = newTemp(Ity_I32);
+
+ assign(t0, binop(Iop_F64toI32S, mkU32(0x0), getDReg(fs)));
+
+ putFReg(fd, unop(Iop_ReinterpI32asF32, mkexpr(t0)));
+ break;
+
+ default:
+ goto decode_failure;
+
+ }
+ break; //ROUND.W.fmt
+
+ case 0x0F: //FLOOR.W.fmt
+ switch (fmt) {
+ case 0x10: //S
+ DIP("floor.w.s f%d, f%d\n", fd, fs);
+ putFReg(fd, binop(Iop_RoundF32toInt, mkU32(0x1),
+ getFReg(fs)));
+ break;
+
+ case 0x11: //D
+ DIP("floor.w.d f%d, f%d\n", fd, fs);
+ t0 = newTemp(Ity_I32);
+
+ assign(t0, binop(Iop_F64toI32S, mkU32(0x1), getDReg(fs)));
+
+ putFReg(fd, unop(Iop_ReinterpI32asF32, mkexpr(t0)));
+ break;
+
+ default:
+ goto decode_failure;
+
+ }
+ break; //FLOOR.W.fmt
+
+ case 0x0D: //TRUNC.W
+ switch (fmt) {
+ case 0x10: //S
+ DIP("trunc.w.s %d, %d\n", fd, fs);
+ putFReg(fd, binop(Iop_RoundF32toInt, mkU32(0x3),
+ getFReg(fs)));
+ break;
+
+ case 0x11: //D
+ DIP("trunc.w.d %d, %d\n", fd, fs);
+ t0 = newTemp(Ity_I32);
+
+ assign(t0, binop(Iop_F64toI32S, mkU32(0x3), getDReg(fs)));
+
+ putFReg(fd, unop(Iop_ReinterpI32asF32, mkexpr(t0)));
+ break;
+
+ default:
+ goto decode_failure;
+
+ }
+ break;
+ case 0x0E: //CEIL.W.fmt
+ switch (fmt) {
+ case 0x10: //S
+ DIP("ceil.w.s %d, %d\n", fd, fs);
+ putFReg(fd, binop(Iop_RoundF32toInt, mkU32(0x2),
+ getFReg(fs)));
+ break;
+
+ case 0x11: //D
+ DIP("ceil.w.d %d, %d\n", fd, fs);
+ t0 = newTemp(Ity_I32);
+
+ assign(t0, binop(Iop_F64toI32S, mkU32(0x2), getDReg(fs)));
+
+ putFReg(fd, unop(Iop_ReinterpI32asF32, mkexpr(t0)));
+ break;
+
+ default:
+ goto decode_failure;
+
+ }
+ break;
+ case 0x0A: //CEIL.L.fmt
+ switch (fmt) {
+ case 0x10: //S
+ DIP("ceil.l.s %d, %d\n", fd, fs);
+ goto decode_failure;
+
+ case 0x11: //D
+ DIP("ceil.l.d %d, %d\n", fd, fs);
+
+ goto decode_failure;
+
+ default:
+ goto decode_failure;
+
+ }
+ break;
+
+ case 0x16: //RSQRT.fmt
+ switch (fmt) {
+ case 0x10:
+ { //S
+ DIP("rsqrt.s %d, %d\n", fd, fs);
+ IRExpr *rm = get_IR_roundingmode();
+ putFReg(fd, mkWidenFromF32(tyF, triop(Iop_DivF32, rm,
+ unop(Iop_ReinterpI32asF32, mkU32(0x3F800000)),
+ binop(Iop_SqrtF32, rm, getLoFromF64(tyF,
+ getFReg(fs))))));
+ break;
+ }
+ case 0x11:
+ { //D
+ DIP("rsqrt.d %d, %d\n", fd, fs);
+ IRExpr *rm = get_IR_roundingmode();
+ putDReg(fd, triop(Iop_DivF64, rm,
+ unop(Iop_ReinterpI64asF64,
+ mkU64(0x3FF0000000000000ULL)),
+ binop(Iop_SqrtF64, rm, getDReg(fs))));
+ break;
+ }
+ default:
+ goto decode_failure;
+
+ }
+ break;
+
+ default:
+ if (dis_instr_CCondFmt(cins))
+ break;
+ goto decode_failure;
+
+ }
+
+ }
+ }
+ break; /*COP1 */
+ case 0x10: /* COP0 */
+ if (rs == 0) { /* MFC0 */
+ DIP("mfc0 r%d, r%d, %d", rt, rd, sel);
+
+ IRTemp val = newTemp(Ity_I32);
+ IRExpr** args = mkIRExprVec_2 (mkU32(rd), mkU32(sel));
+ IRDirty *d = unsafeIRDirty_1_N(val,
+ 0,
+ "mips32_dirtyhelper_mfc0",
+ &mips32_dirtyhelper_mfc0,
+ args);
+
+ stmt(IRStmt_Dirty(d));
+ putIReg(rt, mkexpr(val));
+ } else
+ goto decode_failure;
+ break;
+ case 0x31: /* LWC1 */
+ /* Load Word to Floating Point - LWC1 (MIPS32) */
+ LOAD_STORE_PATTERN;
+ putFReg(ft, load(Ity_F32, mkexpr(t1)));
+
+ DIP("lwc1 f%d, %d(r%d)", ft, imm, rs);
+ break;
+
+ case 0x39: /* SWC1 */
+ LOAD_STORE_PATTERN;
+ store(mkexpr(t1), getFReg(ft));
+ DIP("swc1 f%d, %d(r%d)", ft, imm, rs);
+ break;
+
+ case 0x33: /* PREF */
+ DIP("pref");
+ break;
+
+ case 0x35:
+ /* Load Doubleword to Floating Point - LDC1 (MIPS32) */
+ LOAD_STORE_PATTERN;
+
+ t2 = newTemp(Ity_I32);
+ assign(t2, binop(Iop_Add32, getIReg(rs),
+ mkU32(extend_s_16to32(imm + 4))));
+
+#if defined (_MIPSEL)
+ putFReg(ft, load(Ity_F32, mkexpr(t1)));
+ putFReg(ft + 1, load(Ity_F32, mkexpr(t2)));
+#elif defined (_MIPSEB)
+ putFReg(ft + 1, load(Ity_F32, mkexpr(t1)));
+ putFReg(ft, load(Ity_F32, mkexpr(t2)));
+#endif
+ DIP("ldc1 f%d, %d(%d) \n", rt, imm, rs);
+ break;
+
+ case 0x3D:
+ /* Store Doubleword from Floating Point - SDC1 */
+ LOAD_STORE_PATTERN;
+
+ t2 = newTemp(Ity_I32);
+ assign(t2, binop(Iop_Add32, getIReg(rs),
+ mkU32(extend_s_16to32(imm + 4))));
+
+#if defined (_MIPSEL)
+ store(mkexpr(t1), getFReg(ft));
+ store(mkexpr(t2), getFReg(ft + 1));
+#elif defined (_MIPSEB)
+ store(mkexpr(t1), getFReg(ft + 1));
+ store(mkexpr(t2), getFReg(ft));
+#endif
+ DIP("sdc1 f%d, %d(%d)", ft, imm, rs);
+ break;
+
+ case 0x23: /* LW */
+ DIP("lw r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+ putIReg(rt, mkWidenFrom32(ty, load(Ity_I32, mkexpr(t1)), True));
+ break;
+
+ case 0x20: /* LB */
+ DIP("lb r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+ putIReg(rt, unop(Iop_8Sto32, load(Ity_I8, mkexpr(t1))));
+ break;
+
+ case 0x24: /* LBU */
+ DIP("lbu r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+ putIReg(rt, unop(Iop_8Uto32, load(Ity_I8, mkexpr(t1))));
+ break;
+
+ case 0x21: /* LH */
+ DIP("lh r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+ putIReg(rt, unop(Iop_16Sto32, load(Ity_I16, mkexpr(t1))));
+ break;
+
+ case 0x25: /* LHU */
+ DIP("lhu r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+ putIReg(rt, unop(Iop_16Uto32, load(Ity_I16, mkexpr(t1))));
+ break;
+
+ case 0x0F: /* LUI */
+ p = (imm << 16);
+ DIP("lui rt: %d, imm: %d, imm << 16: %d", rt, imm, p);
+ if ((vex_traceflags & VEX_TRACE_FE) && !mode64)
+ ppIRExpr(mkU32(p));
+ putIReg(rt, mkU32(p));
+ break;
+
+ case 0x13: /* COP1X */
+ switch (function) {
+ case 0x0: { /* LWXC1 */
+ /* Load Word Indexed to Floating Point - LWXC1 (MIPS32r2) */
+ DIP("lwxc1 f%d, r%d(r%d) \n", fd, rt, rs);
+ t0 = newTemp(Ity_I32);
+ assign(t0, binop(Iop_Add32, getIReg(rs), getIReg(rt)));
+ putFReg(fd, load(Ity_F32, mkexpr(t0)));
+ break;
+ }
+
+ case 0x1: { /* LDXC1 */
+ /* Load Doubleword Indexed to Floating Point - LDXC1 (MIPS32r2) */
+ t0 = newTemp(Ity_I32);
+ assign(t0, binop(Iop_Add32, getIReg(rs), getIReg(rt)));
+
+ t1 = newTemp(Ity_I32);
+ assign(t1, binop(Iop_Add32, mkexpr(t0), mkU32(4)));
+
+#if defined (_MIPSEL)
+ putFReg(fd, load(Ity_F32, mkexpr(t0)));
+ putFReg(fd + 1, load(Ity_F32, mkexpr(t1)));
+#elif defined (_MIPSEB)
+ putFReg(fd + 1, load(Ity_F32, mkexpr(t0)));
+ putFReg(fd, load(Ity_F32, mkexpr(t1)));
+#endif
+ DIP("ldxc1 f%d, r%d(r%d) \n", fd, rt, rs);
+ break;
+ }
+
+ case 0x5: // Load Doubleword Indexed Unaligned
+ // to Floating Point - LUXC1; MIPS32r2
+ DIP("luxc1 f%d, r%d(r%d) \n", fd, rt, rs);
+ t0 = newTemp(Ity_I64);
+ t1 = newTemp(Ity_I64);
+ assign(t0, binop(Iop_Add64, getIReg(rs), getIReg(rt)));
+ assign(t1, binop(Iop_And64, mkexpr(t0), mkU64(0xfffffffffffffff8ULL)));
+ putFReg(fd, load(Ity_F64, mkexpr(t1)));
+ break;
+
+ case 0x8: { /* SWXC1 */
+ /* Store Word Indexed from Floating Point - SWXC1 */
+ t0 = newTemp(Ity_I32);
+ assign(t0, binop(Iop_Add32, getIReg(rs), getIReg(rt)));
+
+ store(mkexpr(t0), getFReg(fs));
+
+ DIP("swxc1 f%d, r%d(r%d)", ft, rt, rs);
+ break;
+ }
+ case 0x9: { /* SDXC1 */
+ /* Store Doubleword Indexed from Floating Point - SDXC1 */
+ t0 = newTemp(Ity_I32);
+ assign(t0, binop(Iop_Add32, getIReg(rs), getIReg(rt)));
+
+ t1 = newTemp(Ity_I32);
+ assign(t1, binop(Iop_Add32, mkexpr(t0), mkU32(4)));
+
+#if defined (_MIPSEL)
+ store(mkexpr(t0), getFReg(fs));
+ store(mkexpr(t1), getFReg(fs + 1));
+#elif defined (_MIPSEB)
+ store(mkexpr(t0), getFReg(fs + 1));
+ store(mkexpr(t1), getFReg(fs));
+#endif
+
+ DIP("sdc1 f%d, %d(%d)", ft, imm, rs);
+ break;
+ }
+ case 0x0F: {
+ DIP("prefx");
+ break;
+ }
+ case 0x20: { /* MADD.S */
+ DIP("madd.s f%d, f%d, f%d, f%d", fmt, ft, fs, fd);
+ IRExpr *rm = get_IR_roundingmode();
+ t1 = newTemp(Ity_F32);
+ assign(t1, triop(Iop_MulF32, rm, getLoFromF64(tyF, getFReg(fs)),
+ getLoFromF64(tyF, getFReg(ft))));
+
+ putFReg(fd, mkWidenFromF32(tyF, triop(Iop_AddF32, rm, mkexpr(t1),
+ getLoFromF64(tyF, getFReg(fmt)))));
+ break; /* MADD.S */
+ }
+ case 0x21: { /* MADD.D */
+ DIP("madd.d f%d, f%d, f%d, f%d", fmt, ft, fs, fd);
+ IRExpr *rm = get_IR_roundingmode();
+ t1 = newTemp(Ity_F64);
+ assign(t1, triop(Iop_MulF64, rm, getDReg(fs), getDReg(ft)));
+
+ putDReg(fd, triop(Iop_AddF64, rm, mkexpr(t1), getDReg(fmt)));
+ break; /* MADD.D */
+ }
+ case 0x28: { /* MSUB.S */
+ DIP("msub.s f%d, f%d, f%d, f%d", fmt, ft, fs, fd);
+ IRExpr *rm = get_IR_roundingmode();
+ t1 = newTemp(Ity_F32);
+ assign(t1, triop(Iop_MulF32, rm, getLoFromF64(tyF, getFReg(fs)),
+ getLoFromF64(tyF, getFReg(ft))));
+
+ putFReg(fd, mkWidenFromF32(tyF, triop(Iop_SubF32, rm,
+ mkexpr(t1), getLoFromF64(tyF, getFReg(fmt)))));
+ break; /* MSUB.S */
+ }
+ case 0x29: { /* MSUB.D */
+ DIP("msub.d f%d, f%d, f%d, f%d", fmt, ft, fs, fd);
+ IRExpr *rm = get_IR_roundingmode();
+ t1 = newTemp(Ity_F64);
+ assign(t1, triop(Iop_MulF64, rm, getDReg(fs), getDReg(ft)));
+
+ putDReg(fd, triop(Iop_SubF64, rm, mkexpr(t1), getDReg(fmt)));
+ break; /* MSUB.D */
+ }
+ case 0x30: { /* NMADD.S */
+ DIP("nmadd.s f%d, f%d, f%d, f%d", fmt, ft, fs, fd);
+ IRExpr *rm = get_IR_roundingmode();
+ t1 = newTemp(Ity_F32);
+ t2 = newTemp(Ity_F32);
+ assign(t1, triop(Iop_MulF32, rm, getLoFromF64(tyF, getFReg(fs)),
+ getLoFromF64(tyF, getFReg(ft))));
+
+ assign(t2, triop(Iop_AddF32, rm, mkexpr(t1),
+ getLoFromF64(tyF, getFReg(fmt))));
+
+ putFReg(fd, mkWidenFromF32(tyF, unop(Iop_NegF32, mkexpr(t2))));
+ break; /* NMADD.S */
+ }
+ case 0x31: { /* NMADD.D */
+ DIP("nmadd.d f%d, f%d, f%d, f%d", fmt, ft, fs, fd);
+ IRExpr *rm = get_IR_roundingmode();
+ t1 = newTemp(Ity_F64);
+ t2 = newTemp(Ity_F64);
+ assign(t1, triop(Iop_MulF64, rm, getDReg(fs), getDReg(ft)));
+
+ assign(t2, triop(Iop_AddF64, rm, mkexpr(t1), getDReg(fmt)));
+ putDReg(fd, unop(Iop_NegF64, mkexpr(t2)));
+ break; /* NMADD.D */
+ }
+ case 0x38: { /* NMSUBB.S */
+ DIP("nmsub.s f%d, f%d, f%d, f%d", fmt, ft, fs, fd);
+ IRExpr *rm = get_IR_roundingmode();
+ t1 = newTemp(Ity_F32);
+ t2 = newTemp(Ity_F32);
+ assign(t1, triop(Iop_MulF32, rm, getLoFromF64(tyF, getFReg(fs)),
+ getLoFromF64(tyF, getFReg(ft))));
+
+ assign(t2, triop(Iop_SubF32, rm, mkexpr(t1), getLoFromF64(tyF,
+ getFReg(fmt))));
+
+ putFReg(fd, mkWidenFromF32(tyF, unop(Iop_NegF32, mkexpr(t2))));
+ break; /* NMSUBB.S */
+ }
+ case 0x39: { /* NMSUBB.D */
+ DIP("nmsub.d f%d, f%d, f%d, f%d", fmt, ft, fs, fd);
+ IRExpr *rm = get_IR_roundingmode();
+ t1 = newTemp(Ity_F64);
+ t2 = newTemp(Ity_F64);
+ assign(t1, triop(Iop_MulF64, rm, getDReg(fs), getDReg(ft)));
+
+ assign(t2, triop(Iop_SubF64, rm, mkexpr(t1), getDReg(fmt)));
+ putDReg(fd, unop(Iop_NegF64, mkexpr(t2)));
+ break; /* NMSUBB.D */
+ }
+
+ default:
+ goto decode_failure;
+ }
+ break;
+
+ case 0x22: /* LWL */
+
+ DIP("lwl r%d, %d(r%d)", rt, imm, rs);
+ {
+ /* t1 = addr */
+ t1 = newTemp(Ity_I32);
+#if defined (_MIPSEL)
+ assign(t1, binop(Iop_Add32, getIReg(rs), mkU32(extend_s_16to32(imm))));
+#elif defined (_MIPSEB)
+ assign(t1, binop(Iop_Xor32, mkU32(0x3), binop(Iop_Add32, getIReg(rs),
+ mkU32(extend_s_16to32(imm)))));
+#endif
+
+ /* t2 = word addr */
+ /* t4 = addr mod 4 */
+ LWX_SWX_PATTERN;
+
+ /* t3 = word content - shifted */
+ t3 = newTemp(Ity_I32);
+ assign(t3, binop(Iop_Shl32, load(Ity_I32, mkexpr(t2)), narrowTo(Ity_I8,
+ binop(Iop_Shl32, binop(Iop_Sub32, mkU32(0x03), mkexpr(t4)),
+ mkU8(3)))));
+
+ /* rt content - adjusted */
+ t5 = newTemp(Ity_I32);
+ assign(t5, binop(Iop_And32, getIReg(rt), binop(Iop_Shr32,
+ mkU32(0xFFFFFFFF), narrowTo(Ity_I8, binop(Iop_Shl32,
+ binop(Iop_Add32, mkexpr(t4), mkU32(0x1)), mkU8(0x3))))));
+
+ putIReg(rt, binop(Iop_Or32, mkexpr(t5), mkexpr(t3)));
+ }
+ break;
+
+ case 0x26: /* LWR */
+
+ DIP("lwr r%d, %d(r%d)", rt, imm, rs);
+ {
+ /* t1 = addr */
+ t1 = newTemp(Ity_I32);
+#if defined (_MIPSEL)
+ assign(t1, binop(Iop_Add32, getIReg(rs), mkU32(extend_s_16to32(imm))));
+#elif defined (_MIPSEB)
+ assign(t1, binop(Iop_Xor32, mkU32(0x3), binop(Iop_Add32, getIReg(rs),
+ mkU32(extend_s_16to32(imm)))));
+#endif
+
+ /* t2 = word addr */
+ /* t4 = addr mod 4 */
+ LWX_SWX_PATTERN;
+
+ /* t3 = word content - shifted */
+ t3 = newTemp(Ity_I32);
+ assign(t3, binop(Iop_Shr32, load(Ity_I32, mkexpr(t2)),
+ narrowTo(Ity_I8, binop(Iop_Shl32, mkexpr(t4),
+ mkU8(3)))));
+
+ /* rt content - adjusted */
+ t5 = newTemp(Ity_I32);
+ assign(t5, binop(Iop_And32, getIReg(rt), unop(Iop_Not32,
+ binop(Iop_Shr32, mkU32(0xFFFFFFFF), narrowTo(Ity_I8,
+ binop(Iop_Shl32, mkexpr(t4), mkU8(0x3)))))));
+
+ putIReg(rt, binop(Iop_Or32, mkexpr(t5), mkexpr(t3)));
+ }
+ break;
+
+ case 0x2B: /* SW */
+ DIP("sw r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+ store(mkexpr(t1), mkNarrowTo32(ty, getIReg(rt)));
+ break;
+
+ case 0x28: /* SB */
+ DIP("sb r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+ store(mkexpr(t1), narrowTo(Ity_I8, getIReg(rt)));
+ break;
+
+ case 0x29: /* SH */
+ DIP("sh r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+ store(mkexpr(t1), narrowTo(Ity_I16, getIReg(rt)));
+ break;
+
+ case 0x2A: /* SWL */
+
+ DIP("swl r%d, %d(r%d)", rt, imm, rs);
+ {
+ /* t1 = addr */
+ t1 = newTemp(Ity_I32);
+#if defined (_MIPSEL)
+ assign(t1, binop(Iop_Add32, getIReg(rs), mkU32(extend_s_16to32(imm))));
+#elif defined (_MIPSEB)
+ assign(t1, binop(Iop_Xor32, mkU32(0x3), binop(Iop_Add32, getIReg(rs),
+ mkU32(extend_s_16to32(imm)))));
+#endif
+
+ /* t2 = word addr */
+ /* t4 = addr mod 4 */
+ LWX_SWX_PATTERN;
+
+ /* t3 = rt content - shifted */
+ t3 = newTemp(Ity_I32);
+ assign(t3, binop(Iop_Shr32, getIReg(rt), narrowTo(Ity_I8,
+ binop(Iop_Shl32, binop(Iop_Sub32, mkU32(0x03), mkexpr(t4)),
+ mkU8(3)))));
+
+ /* word content - adjusted */
+ t5 = newTemp(Ity_I32);
+ t6 = newTemp(Ity_I32);
+ t7 = newTemp(Ity_I32);
+ t8 = newTemp(Ity_I32);
+
+ // neg(shr(0xFFFFFFFF, mul(sub(3,n), 8)))
+ assign(t5, binop(Iop_Mul32, binop(Iop_Sub32, mkU32(0x3), mkexpr(t4)),
+ mkU32(0x8)));
+
+ assign(t6, binop(Iop_Shr32, mkU32(0xFFFFFFFF), narrowTo(Ity_I8,
+ mkexpr(t5))));
+ assign(t7, binop(Iop_Xor32, mkU32(0xFFFFFFFF), mkexpr(t6)));
+ assign(t8, binop(Iop_And32, load(Ity_I32, mkexpr(t2)), mkexpr(t7)));
+ store(mkexpr(t2), binop(Iop_Or32, mkexpr(t8), mkexpr(t3)));
+ }
+ break;
+
+ case 0x2E: /* SWR */
+
+ DIP("swr r%d, %d(r%d)", rt, imm, rs);
+ {
+ /* t1 = addr */
+ t1 = newTemp(Ity_I32);
+#if defined (_MIPSEL)
+ assign(t1, binop(Iop_Add32, getIReg(rs), mkU32(extend_s_16to32(imm))));
+#elif defined (_MIPSEB)
+ assign(t1, binop(Iop_Xor32, mkU32(0x3), binop(Iop_Add32, getIReg(rs),
+ mkU32(extend_s_16to32(imm)))));
+#endif
+
+ /* t2 = word addr */
+ /* t4 = addr mod 4 */
+ LWX_SWX_PATTERN;
+
+ /* t3 = rt content - shifted */
+ t3 = newTemp(Ity_I32);
+ assign(t3, binop(Iop_Shl32, getIReg(rt), narrowTo(Ity_I8,
+ binop(Iop_Shl32, mkexpr(t4), mkU8(3)))));
+
+ /* word content - adjusted */
+ t5 = newTemp(Ity_I32);
+ assign(t5, binop(Iop_And32, load(Ity_I32, mkexpr(t2)), unop(Iop_Not32,
+ binop(Iop_Shl32, mkU32(0xFFFFFFFF), narrowTo(Ity_I8,
+ binop(Iop_Shl32, mkexpr(t4), mkU8(0x3)))))));
+
+ store(mkexpr(t2), binop(Iop_Xor32, mkexpr(t5), mkexpr(t3)));
+ }
+ break;
+
+ case 0x1C: /*Special2 */
+ switch (function) {
+ case 0x02: { /* MUL */
+ DIP("mul r%d, r%d, r%d", rd, rs, rt);
+ putIReg(rd, binop(Iop_Mul32, getIReg(rs), getIReg(rt)));
+ break;
+ }
+
+ case 0x00: { /* MADD */
+ DIP("madd r%d, r%d", rs, rt);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I64);
+ t4 = newTemp(Ity_I32);
+ t5 = newTemp(Ity_I32);
+ t6 = newTemp(Ity_I32);
+
+ assign(t1, getHI());
+ assign(t2, getLO());
+
+ assign(t3, binop(Iop_MullS32, getIReg(rs), getIReg(rt)));
+
+ assign(t4, binop(Iop_Add32, mkexpr(t2), unop(Iop_64to32,
+ mkexpr(t3))));
+
+ assign(t5, unop(Iop_1Uto32, binop(Iop_CmpLT32U, mkexpr(t4),
+ unop(Iop_64to32, mkexpr(t3)))));
+ assign(t6, binop(Iop_Add32, mkexpr(t5), mkexpr(t1)));
+
+ putHI(binop(Iop_Add32, mkexpr(t6), unop(Iop_64HIto32, mkexpr(t3))));
+ putLO(mkexpr(t4));
+ break;
+ }
+
+ case 0x01: { /* MADDU */
+ DIP("maddu r%d, r%d", rs, rt);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I64);
+ t4 = newTemp(Ity_I32);
+ t5 = newTemp(Ity_I32);
+ t6 = newTemp(Ity_I32);
+
+ assign(t1, getHI());
+ assign(t2, getLO());
+
+ assign(t3, binop(Iop_MullU32, getIReg(rs), getIReg(rt)));
+
+ assign(t4, binop(Iop_Add32, mkexpr(t2), unop(Iop_64to32,
+ mkexpr(t3))));
+ assign(t5, unop(Iop_1Uto32, binop(Iop_CmpLT32U, mkexpr(t4),
+ unop(Iop_64to32, mkexpr(t3)))));
+ assign(t6, binop(Iop_Add32, mkexpr(t5), mkexpr(t1)));
+
+ putHI(binop(Iop_Add32, mkexpr(t6), unop(Iop_64HIto32, mkexpr(t3))));
+ putLO(mkexpr(t4));
+ break;
+ }
+
+ case 0x04: { /* MSUB */
+ DIP("msub r%d, r%d", rs, rt);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I64);
+ t4 = newTemp(Ity_I32);
+ t5 = newTemp(Ity_I32);
+ t6 = newTemp(Ity_I32);
+
+ assign(t1, getHI());
+ assign(t2, getLO());
+
+ assign(t3, binop(Iop_MullS32, getIReg(rs), getIReg(rt)));
+ assign(t4, unop(Iop_64to32, mkexpr(t3))); //new lo
+
+ //if lo<lo(mul) hi = hi - 1
+ assign(t5, unop(Iop_1Sto32, binop(Iop_CmpLT32U, mkexpr(t2),
+ mkexpr(t4))));
+
+ assign(t6, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t5)), mkexpr(t1),
+ binop(Iop_Sub32, mkexpr(t1), mkU32(0x1))));
+
+ putHI(binop(Iop_Sub32, mkexpr(t6), unop(Iop_64HIto32, mkexpr(t3))));
+ putLO(binop(Iop_Sub32, mkexpr(t2), mkexpr(t4)));
+ break;
+ }
+
+ case 0x05: { /* MSUBU */
+ DIP("msubu r%d, r%d", rs, rt);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I64);
+ t4 = newTemp(Ity_I32);
+ t5 = newTemp(Ity_I32);
+ t6 = newTemp(Ity_I32);
+
+ assign(t1, getHI());
+ assign(t2, getLO());
+
+ assign(t3, binop(Iop_MullU32, getIReg(rs), getIReg(rt)));
+ assign(t4, unop(Iop_64to32, mkexpr(t3))); //new lo
+
+ //if lo<lo(mul) hi = hi - 1
+ assign(t5, unop(Iop_1Sto32, binop(Iop_CmpLT32U, mkexpr(t2),
+ mkexpr(t4))));
+
+ assign(t6, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t5)),
+ mkexpr(t1), binop(Iop_Sub32, mkexpr(t1), mkU32(0x1))));
+
+ putHI(binop(Iop_Sub32, mkexpr(t6), unop(Iop_64HIto32, mkexpr(t3))));
+ putLO(binop(Iop_Sub32, mkexpr(t2), mkexpr(t4)));
+ break;
+ }
+
+ case 0x20: { /* CLZ */
+ DIP("clz r%d, r%d", rd, rs);
+ t1 = newTemp(Ity_I32);
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, getIReg(rs),
+ mkU32(0))));
+ putIReg(rd, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t1)),
+ unop(Iop_Clz32, getIReg(rs)), mkU32(0x00000020)));
+ break;
+ }
+
+ case 0x21: { /* CLO */
+ DIP("clo r%d, r%d", rd, rs);
+ t1 = newTemp(Ity_I32);
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, getIReg(rs),
+ mkU32(0xffffffff))));
+ putIReg(rd, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t1)),
+ unop(Iop_Clz32, unop(Iop_Not32, getIReg(rs))),
+ mkU32(0x00000020)));
+ break;
+ }
+
+ default:
+ goto decode_failure;
+ }
+ break;
+
+ case 0x1F: /*Special3 */
+ switch (function) {
+ case 0x3B:
+ /*RDHWR*/ {
+ DIP("rdhwr r%d, r%d", rt, rd);
+ if (rd == 29) {
+ putIReg(rt, getULR());
+ } else
+ goto decode_failure;
+ break;
+ }
+ case 0x04:
+ /*INS*/ msb = get_msb(cins);
+ lsb = get_lsb(cins);
+
+ size = msb - lsb + 1;
+
+ vassert(lsb + size <= 32);
+ vassert(lsb + size > 0);
+
+ DIP("ins size:%d msb:%d lsb:%d", size, msb, lsb);
+ /*put size bits from rs at the pos in temporary */
+ t0 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ /*shift left for 32 - size to clear leading bits and get zeros
+ at the end */
+ assign(t0, binop(Iop_Shl32, getIReg(rs), mkU8(32 - size)));
+ /*now set it at pos */
+ t1 = newTemp(Ity_I32);
+ assign(t1, binop(Iop_Shr32, mkexpr(t0), mkU8(32 - size - lsb)));
+
+ if (lsb > 0) {
+ t2 = newTemp(Ity_I32);
+ /*clear everything but lower pos bits from rt */
+ assign(t2, binop(Iop_Shl32, getIReg(rt), mkU8(32 - lsb)));
+ assign(t3, binop(Iop_Shr32, mkexpr(t2), mkU8(32 - lsb)));
+ }
+
+ if (msb < 31) {
+ t4 = newTemp(Ity_I32);
+ /*clear everything but upper msb + 1 bits from rt */
+ assign(t4, binop(Iop_Shr32, getIReg(rt), mkU8(msb + 1)));
+ t5 = newTemp(Ity_I32);
+ assign(t5, binop(Iop_Shl32, mkexpr(t4), mkU8(msb + 1)));
+
+ /*now combine these registers */
+ if (lsb > 0) {
+ t6 = newTemp(Ity_I32);
+ assign(t6, binop(Iop_Or32, mkexpr(t5), mkexpr(t1)));
+ putIReg(rt, binop(Iop_Or32, mkexpr(t6), mkexpr(t3)));
+ } else {
+ putIReg(rt, binop(Iop_Or32, mkexpr(t1), mkexpr(t5)));
+ }
+ }
+
+ else {
+ putIReg(rt, binop(Iop_Or32, mkexpr(t1), mkexpr(t3)));
+
+ }
+ break;
+
+ case 0x00:
+ /*EXT*/ msb = get_msb(cins);
+ lsb = get_lsb(cins);
+ size = msb + 1;
+ DIP("ext size:%d msb:%d lsb:%d", size, msb, lsb);
+ vassert(lsb + size <= 32);
+ vassert(lsb + size > 0);
+ /*put size bits from rs at the top of in temporary */
+ if (lsb + size < 32) {
+ t0 = newTemp(Ity_I32);
+ assign(t0, binop(Iop_Shl32, getIReg(rs), mkU8(32 - lsb - size)));
+ putIReg(rt, binop(Iop_Shr32, mkexpr(t0), mkU8(32 - size)));
+ } else {
+ putIReg(rt, binop(Iop_Shr32, getIReg(rs), mkU8(32 - size)));
+
+ }
+ break;
+
+ case 0x20:
+ /*BSHFL*/ switch (sa) {
+ case 0x10:
+ /*SEB*/ DIP("seb r%d, r%d", rd, rt);
+ putIReg(rd, unop(Iop_8Sto32, unop(Iop_32to8, getIReg(rt))));
+ break;
+
+ case 0x18:
+ /*SEH*/ DIP("seh r%d, r%d", rd, rt);
+ putIReg(rd, unop(Iop_16Sto32, unop(Iop_32to16, getIReg(rt))));
+ break;
+
+ case 0x02:
+ /*WSBH*/ DIP("wsbh r%d, r%d", rd, rt);
+ t0 = newTemp(Ity_I32);
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ assign(t0, binop(Iop_Shl32, binop(Iop_And32, getIReg(rt),
+ mkU32(0x00FF0000)), mkU8(0x8)));
+ assign(t1, binop(Iop_Shr32, binop(Iop_And32, getIReg(rt),
+ mkU32(0xFF000000)), mkU8(0x8)));
+ assign(t2, binop(Iop_Shl32, binop(Iop_And32, getIReg(rt),
+ mkU32(0x000000FF)), mkU8(0x8)));
+ assign(t3, binop(Iop_Shr32, binop(Iop_And32, getIReg(rt),
+ mkU32(0x0000FF00)), mkU8(0x8)));
+ putIReg(rd, binop(Iop_Or32, binop(Iop_Or32, mkexpr(t0),
+ mkexpr(t1)), binop(Iop_Or32, mkexpr(t2), mkexpr(t3))));
+ break;
+
+ default:
+ goto decode_failure;
+
+ }
+ break;
+ /*BSHFL*/ default:
+ goto decode_failure;
+
+ }
+ break; /*Special3 */
+
+ case 0x3B:
+ if (0x3B == function && (archinfo->hwcaps & VEX_PRID_COMP_BROADCOM)) {
+ /*RDHWR*/
+ DIP("rdhwr r%d, r%d", rt, rd);
+ if (rd == 29) {
+ putIReg(rt, getULR());
+ } else
+ goto decode_failure;
+ break;
+ } else {
+ goto decode_failure;
+ }
+
+ case 0x00: /*Special */
+
+ switch (function) {
+ case 0x1: {
+ UInt mov_cc = get_mov_cc(cins);
+ if (tf == 0) { /* MOVF */
+ DIP("movf r%d, r%d, %d", rd, rs, mov_cc);
+ {
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_I32);
+
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(0),
+ mkU32(mov_cc))));
+ assign(t2, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t1)),
+ binop(Iop_And32, binop(Iop_Shr32, getFCSR(),
+ mkU8(24 + mov_cc)), mkU32(0x1)), binop(Iop_And32,
+ binop(Iop_Shr32, getFCSR(), mkU8(23)),
+ mkU32(0x1))));
+
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(0),
+ mkexpr(t2))));
+ assign(t4, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ getIReg(rd), getIReg(rs)));
+ putIReg(rd, mkexpr(t4));
+ }
+ } else if (tf == 1) { /* MOVT */
+ DIP("movt r%d, r%d, %d", rd, rs, mov_cc);
+ {
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I32);
+ t3 = newTemp(Ity_I32);
+ t4 = newTemp(Ity_I32);
+
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(0),
+ mkU32(mov_cc))));
+ assign(t2, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t1)),
+ binop(Iop_And32, binop(Iop_Shr32, getFCSR(),
+ mkU8(24 + mov_cc)), mkU32(0x1)), binop(Iop_And32,
+ binop(Iop_Shr32, getFCSR(), mkU8(23)),
+ mkU32(0x1))));
+
+ assign(t3, unop(Iop_1Sto32, binop(Iop_CmpEQ32, mkU32(1),
+ mkexpr(t2))));
+ assign(t4, IRExpr_Mux0X(unop(Iop_32to8, mkexpr(t3)),
+ getIReg(rd), getIReg(rs)));
+ putIReg(rd, mkexpr(t4));
+ }
+ }
+ break;
+ }
+ case 0x0A: {
+ /* MOVZ */
+ DIP("movz r%d, r%d, r%d", rd, rs, rt);
+ t1 = newTemp(ty);
+ t2 = newTemp(ty);
+ {
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, getIReg(rt),
+ mkU32(0x0))));
+ assign(t2, unop(Iop_1Sto32, binop(Iop_CmpNE32, getIReg(rt),
+ mkU32(0x0))));
+ putIReg(rd, binop(Iop_Add32, binop(Iop_And32, getIReg(rs),
+ mkexpr(t1)), binop(Iop_And32, getIReg(rd),
+ mkexpr(t2))));
+ }
+ break;
+ }
+
+ case 0x0B: {
+ /* MOVN */
+ DIP("movn r%d, r%d, r%d", rd, rs, rt);
+ t1 = newTemp(ty);
+ t2 = newTemp(ty);
+ {
+ assign(t1, unop(Iop_1Sto32, binop(Iop_CmpEQ32, getIReg(rt),
+ mkU32(0x0))));
+ assign(t2, unop(Iop_1Sto32, binop(Iop_CmpNE32, getIReg(rt),
+ mkU32(0x0))));
+ putIReg(rd, binop(Iop_Add32, binop(Iop_And32, getIReg(rs),
+ mkexpr(t2)), binop(Iop_And32, getIReg(rd),
+ mkexpr(t1))));
+ }
+ break;
+ }
+
+ case 0x18: /* MULT */
+ DIP("mult r%d, r%d", rs, rt);
+ t2 = newTemp(Ity_I64);
+
+ assign(t2, binop(Iop_MullS32, mkNarrowTo32(ty, getIReg(rs)),
+ mkNarrowTo32(ty, getIReg(rt))));
+
+ putHI(mkWidenFrom32(ty, unop(Iop_64HIto32, mkexpr(t2)), True));
+ putLO(mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(t2)), True));
+ break;
+
+ case 0x19: /* MULTU */
+ DIP("multu r%d, r%d", rs, rt);
+ t2 = newTemp(Ity_I64);
+
+ assign(t2, binop(Iop_MullU32, mkNarrowTo32(ty, getIReg(rs)),
+ mkNarrowTo32(ty, getIReg(rt))));
+
+ putHI(mkWidenFrom32(ty, unop(Iop_64HIto32, mkexpr(t2)), True));
+ putLO(mkWidenFrom32(ty, unop(Iop_64to32, mkexpr(t2)), True));
+ break;
+
+ case 0x20: /* ADD */
+ DIP("add r%d, r%d, r%d", rd, rs, rt);
+ {
+ t2 = newTemp(Ity_I32);
+
+ assign(t2, binop(Iop_Add32, getIReg(rs), getIReg(rt)));
+ putIReg(rd, mkexpr(t2));
+ }
+ break;
+
+ case 0x1A: /* DIV */
+ DIP("div r%d, r%d", rs, rt);
+ {
+ t1 = newTemp(Ity_I64);
+ t2 = newTemp(Ity_I64);
+
+ assign(t1, unop(Iop_32Sto64, getIReg(rs)));
+ assign(t2, binop(Iop_DivModS64to32, mkexpr(t1), getIReg(rt)));
+
+ putHI(unop(Iop_64HIto32, mkexpr(t2)));
+ putLO(unop(Iop_64to32, mkexpr(t2)));
+ }
+ break;
+
+ case 0x1B: /* DIVU */
+ DIP("divu r%d, r%d", rs, rt);
+ {
+ t1 = newTemp(Ity_I64);
+ t2 = newTemp(Ity_I64);
+ assign(t1, unop(Iop_32Uto64, getIReg(rs)));
+ assign(t2, binop(Iop_DivModU64to32, mkexpr(t1), getIReg(rt)));
+ putHI(unop(Iop_64HIto32, mkexpr(t2)));
+ putLO(unop(Iop_64to32, mkexpr(t2)));
+ }
+ break;
+
+ case 0x10: /* MFHI */
+ DIP("mfhi r%d", rd);
+ putIReg(rd, getHI());
+ break;
+
+ case 0x11: /* MTHI */
+ DIP("mthi r%d", rs);
+ putHI(getIReg(rs));
+ break;
+
+ case 0x12: /* MFLO */
+ DIP("mflo r%d", rd);
+ putIReg(rd, getLO());
+ break;
+
+ case 0x13: /* MTLO */
+ DIP("mtlo r%d", rs);
+ putLO(getIReg(rs));
+ break;
+
+ case 0x21: /* ADDU */
+ DIP("addu r%d, r%d, r%d", rd, rs, rt);
+ ALU_PATTERN(Iop_Add32);
+ break;
+
+ case 0x22: /* SUB */
+ DIP("sub r%d, r%d, r%d", rd, rs, rt);
+ ALU_PATTERN(Iop_Sub32);
+ break;
+
+ case 0x23: /* SUBU */
+ DIP("subu r%d, r%d, r%d", rd, rs, rt);
+ ALU_PATTERN(Iop_Sub32);
+ break;
+
+ case 0x24: /* AND */
+ DIP("and r%d, r%d, r%d", rd, rs, rt);
+ ALU_PATTERN(Iop_And32);
+ break;
+
+ case 0x25: /* OR */
+ DIP("or r%d, r%d, r%d", rd, rs, rt);
+ ALU_PATTERN(Iop_Or32);
+ break;
+
+ case 0x26: /* XOR */
+ DIP("xor r%d, r%d, r%d", rd, rs, rt);
+ ALU_PATTERN(Iop_Xor32);
+ break;
+
+ case 0x27: /* NOR */
+ DIP("nor r%d, r%d, r%d", rd, rs, rt);
+ putIReg(rd, unop(Iop_Not32, binop(Iop_Or32, getIReg(rs),getIReg(rt))));
+ break;
+
+ case 0x08: /* JR */
+ DIP("jr r%d", rs);
+ t0 = newTemp(ty);
+ assign(t0, getIReg(rs));
+ lastn = mkexpr(t0);
+ break;
+
+ case 0x09: /* JALR */
+ DIP("jalr r%d r%d", rd, rs);
+ putIReg(rd, mkU32(guest_PC_curr_instr + 8));
+ t0 = newTemp(Ity_I32);
+ assign(t0, getIReg(rs));
+ lastn = mkexpr(t0);
+ break;
+
+ case 0x0C: /* SYSCALL */
+ DIP("syscall");
+ putPC(mkU32(guest_PC_curr_instr + 4));
+ dres.jk_StopHere = Ijk_Sys_syscall;
+ dres.whatNext = Dis_StopHere;
+ break;
+
+ case 0x2A: /* SLT */
+ DIP("slt r%d, r%d, r%d", rd, rs, rt);
+ putIReg(rd, unop(Iop_1Uto32, binop(Iop_CmpLT32S, getIReg(rs),
+ getIReg(rt))));
+ break;
+
+ case 0x2B: /* SLTU */
+ DIP("sltu r%d, r%d, r%d", rd, rs, rt);
+ putIReg(rd, unop(Iop_1Uto32, binop(Iop_CmpLT32U, getIReg(rs),
+ getIReg(rt))));
+ break;
+
+ case 0x00:
+ /* SLL */
+ DIP("sll r%d, r%d, %d", rd, rt, sa);
+ SXX_PATTERN(Iop_Shl32);
+ break;
+
+ case 0x04: /* SLLV */
+ DIP("sllv r%d, r%d, r%d", rd, rt, rs);
+ SXXV_PATTERN(Iop_Shl32);
+ break;
+
+ case 0x03: /* SRA */
+ DIP("sra r%d, r%d, %d", rd, rt, sa);
+ SXX_PATTERN(Iop_Sar32);
+ break;
+
+ case 0x07: /* SRAV */
+ DIP("srav r%d, r%d, r%d", rd, rt, rs);
+ SXXV_PATTERN(Iop_Sar32);
+ break;
+
+ case 0x02: { /* SRL */
+ rot = get_rot(cins);
+ if (rot) {
+ DIP("rotr r%d, r%d, %d", rd, rt, sa);
+ putIReg(rd, mkWidenFrom32(ty, genROR32(mkNarrowTo32(ty,
+ getIReg(rt)), sa), False));
+ } else {
+ DIP("srl r%d, r%d, %d", rd, rt, sa);
+ SXX_PATTERN(Iop_Shr32);
+ }
+ break;
+ }
+
+ case 0x06: {
+ rot = get_rotv(cins);
+ if (rot) {
+ DIP("rotrv r%d, r%d, r%d", rd, rt, rs);
+ putIReg(rd, mkWidenFrom32(ty, genRORV32(mkNarrowTo32(ty,
+ getIReg(rt)), mkNarrowTo32(ty, getIReg(rs))),False));
+ break;
+ } else {
+ /* SRLV */
+ DIP("srlv r%d, r%d, r%d", rd, rt, rs);
+ SXXV_PATTERN(Iop_Shr32);
+ break;
+ }
+ }
+
+ case 0x0D: /* BREAK */
+ DIP("Info: Breakpoint...code = %d", trap_code);
+ jmp_lit(&dres, Ijk_SigTRAP, (guest_PC_curr_instr + 4));
+ vassert(dres.whatNext == Dis_StopHere);
+ break;
+
+ case 0x30: { /* TGE */
+ /*tge */ DIP("tge r%d, r%d %d", rs, rt, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpLT32S, getIReg (rt), getIReg (rs)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x31: { /* TGEU */
+ /*tgeu */ DIP("tgeu r%d, r%d %d", rs, rt, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpLT32U, getIReg (rt), getIReg (rs)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x32: { /* TLT */
+ /*tlt */ DIP("tlt r%d, r%d %d", rs, rt, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpLT32S, getIReg (rs), getIReg (rt)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x33: { /* TLTU */
+ /*tltu */ DIP("tltu r%d, r%d %d", rs, rt, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpLT32U, getIReg (rs), getIReg (rt)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x34: { /* TEQ */
+ /*teq */ DIP("teq r%d, r%d %d", rs, rt, trap_code);
+ stmt (IRStmt_Exit(binop (Iop_CmpEQ32, getIReg (rs), getIReg (rt)),
+ Ijk_SigTRAP, IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x36: { /* TNE */
+ /*tne */ DIP("tne r%d, r%d %d", rs, rt, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpNE32, getIReg (rs), getIReg (rt)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x0F: {
+ /*SYNC*/ DIP("sync r%d, r%d, %d", rt, rd, sel);
+ lsb = get_lsb(cins);
+ IRDirty *d = unsafeIRDirty_0_N(0,
+ "mips32_dirtyhelper_sync",
+ &mips32_dirtyhelper_sync,
+ mkIRExprVec_1
+ (mkU32(lsb)));
+
+ d->needsBBP = False;
+ d->nFxState = 0;
+
+ stmt(IRStmt_Dirty(d));
+ break;
+ }
+
+ default:
+ goto decode_failure;
+ }
+ break;
+
+ case 0x01: /* Regimm */
+
+ switch (rt) {
+ case 0x01: /* BGEZ */
+ DIP("bgez r%d, %d", rs, imm);
+ dis_branch(False, binop(Iop_CmpEQ32, binop(Iop_And32, getIReg(rs),
+ mkU32(0x80000000)), mkU32(0x0)), imm, &bstmt);
+ break;
+
+ case 0x03: /* BGEZL */
+ DIP("bgezl r%d, %d", rs, imm);
+ lastn = dis_branch_likely(binop(Iop_CmpNE32, binop(Iop_And32,
+ getIReg(rs), mode64 ?
+ mkU64(0x8000000000000000ULL)
+ :mkU32(0x80000000)),
+ mkU32(0x0)), imm);
+ break;
+
+ case 0x00: /* BLTZ */
+ DIP("bltz r%d, %d", rs, imm);
+ dis_branch(False, binop(Iop_CmpEQ32, binop(Iop_And32, getIReg(rs),
+ mkU32(0x80000000)), mkU32(0x80000000)), imm, &bstmt);
+ break;
+
+ case 0x02: /* BLTZL */
+ DIP("bltzl r%d, %d", rs, imm);
+ lastn = dis_branch_likely(binop(Iop_CmpNE32, binop(Iop_And32,
+ getIReg(rs), mkU32(0x80000000)),
+ mkU32(0x80000000)), imm);
+ break;
+
+ case 0x10: /* BLTZAL */
+ DIP("bltzal r%d, %d", rs, imm);
+ dis_branch(True, binop(Iop_CmpEQ32, binop(Iop_And32, getIReg(rs),
+ mkU32(0x80000000)), mkU32(0x80000000)), imm, &bstmt);
+ break;
+
+ case 0x12: /* BLTZALL */
+ DIP("bltzall r%d, %d", rs, imm);
+ putIReg(31, mkU32(guest_PC_curr_instr + 8));
+ lastn = dis_branch_likely(binop(Iop_CmpNE32, binop(Iop_And32,
+ getIReg(rs), mkU32(0x80000000)),
+ mkU32(0x80000000)), imm);
+ break;
+
+ case 0x11: /* BGEZAL */
+ DIP("bgezal r%d, %d", rs, imm);
+ dis_branch(True, binop(Iop_CmpEQ32, binop(Iop_And32, getIReg(rs),
+ mkU32(0x80000000)), mkU32(0x0)), imm, &bstmt);
+ break;
+
+ case 0x13: /* BGEZALL */
+ DIP("bgezall r%d, %d", rs, imm);
+ putIReg(31, mkU32(guest_PC_curr_instr + 8));
+ lastn = dis_branch_likely(binop(Iop_CmpNE32, binop(Iop_And32,
+ getIReg(rs), mkU32(0x80000000)),
+ mkU32(0x0)), imm);
+ break;
+
+ case 0x08: { /* TGEI */
+ /*tgei */ DIP("tgei r%d, %d %d", rs, imm, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpLT32S, mkU32 (imm), getIReg (rs)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x09: { /* TGEIU */
+ /*tqeiu */ DIP("tgeiu r%d, %d %d", rs, imm, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpLT32U, mkU32 (imm), getIReg (rs)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x0A: { /* TLTI */
+ /*tlti */ DIP("tlti r%d, %d %d", rs, imm, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpLT32S, getIReg (rs), mkU32 (imm)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x0B: { /* TLTIU */
+ /*tltiu */ DIP("tltiu r%d, %d %d", rs, imm, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpLT32U, getIReg (rs), mkU32 (imm)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x0C: { /* TEQI */
+ /*teqi */ DIP("teqi r%d, %d %d", rs, imm, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpEQ32, getIReg (rs), mkU32 (imm)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x0E: { /* TNEI */
+ /*tnei */ DIP("tnei r%d, %d %d", rs, imm, trap_code);
+ stmt (IRStmt_Exit (binop (Iop_CmpNE32, getIReg (rs), mkU32 (imm)),
+ Ijk_SigTRAP,
+ IRConst_U32 (guest_PC_curr_instr + 4), OFFB_PC));
+ break;
+ }
+ case 0x1F:
+ /*SYNCI*/
+ //Just ignore it
+ break;
+
+ default:
+ goto decode_failure;
+ }
+ break;
+
+ case 0x04:
+ DIP("beq r%d, r%d, %d", rs, rt, imm);
+ dis_branch(False, binop(Iop_CmpEQ32, getIReg(rs), getIReg(rt)),
+ imm, &bstmt);
+ break;
+
+ case 0x14:
+ DIP("beql r%d, r%d, %d", rs, rt, imm);
+ lastn = dis_branch_likely(binop(Iop_CmpNE32, getIReg(rs), getIReg(rt)),
+ imm);
+ break;
+
+ case 0x05:
+ DIP("bne r%d, r%d, %d", rs, rt, imm);
+ dis_branch(False, binop(Iop_CmpNE32, getIReg(rs), getIReg(rt)),
+ imm, &bstmt);
+ break;
+
+ case 0x15:
+ DIP("bnel r%d, r%d, %d", rs, rt, imm);
+ lastn =
+ dis_branch_likely(binop(Iop_CmpEQ32, getIReg(rs), getIReg(rt)), imm);
+ break;
+
+ case 0x07: /* BGTZ */
+ DIP("bgtz r%d, %d", rs, imm);
+ dis_branch(False, unop(Iop_Not1, binop(Iop_CmpLE32S, getIReg(rs),
+ mkU32(0x00))), imm, &bstmt);
+ break;
+
+ case 0x17: /* BGTZL */
+ DIP("bgtzl r%d, %d", rs, imm);
+ lastn = dis_branch_likely(binop(Iop_CmpLE32S, getIReg(rs), mkU32(0x00)),
+ imm);
+ break;
+
+ case 0x06: /* BLEZ */
+ DIP("blez r%d, %d", rs, imm);
+ dis_branch(False,binop(Iop_CmpLE32S, getIReg(rs), mkU32(0x0)), imm,
+ &bstmt);
+ break;
+
+ case 0x16: /* BLEZL */
+ DIP("blezl r%d, %d", rs, imm);
+ lastn = dis_branch_likely(unop(Iop_Not1, (binop(Iop_CmpLE32S,
+ getIReg(rs), mkU32(0x0)))), imm);
+ break;
+
+ case 0x08: /* ADDI TODO: Check this */
+ DIP("addi r%d, r%d, %d", rt, rs, imm);
+ putIReg(rt, binop(Iop_Add32, getIReg(rs), mkU32(extend_s_16to32(imm))));
+ break;
+
+ case 0x09: /* ADDIU */
+ DIP("addiu r%d, r%d, %d", rt, rs, imm);
+ putIReg(rt, binop(Iop_Add32, getIReg(rs), mkU32(extend_s_16to32(imm))));
+ break;
+
+ case 0x0C: /* ANDI */
+ DIP("andi r%d, r%d, %d", rt, rs, imm);
+ ALUI_PATTERN(Iop_And32);
+ break;
+
+ case 0x0E: /* XORI */
+ DIP("xori r%d, r%d, %d", rt, rs, imm);
+ ALUI_PATTERN(Iop_Xor32);
+ break;
+
+ case 0x0D: /* ORI */
+ DIP("ori r%d, r%d, %d", rt, rs, imm);
+ ALUI_PATTERN(Iop_Or32);
+ break;
+
+ case 0x0A: /* SLTI */
+ DIP("slti r%d, r%d, %d", rt, rs, imm);
+ putIReg(rt, unop(Iop_1Uto32, binop(Iop_CmpLT32S, getIReg(rs),
+ mkU32(extend_s_16to32(imm)))));
+ break;
+
+ case 0x0B: /* SLTIU */
+ DIP("sltiu r%d, r%d, %d", rt, rs, imm);
+ putIReg(rt, unop(Iop_1Uto32, binop(Iop_CmpLT32U, getIReg(rs),
+ mkU32(extend_s_16to32(imm)))));
+ break;
+
+ case 0x30: /* LL / LWC0 */
+ DIP("ll r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+
+ t2 = newTemp(Ity_I32);
+#if defined (_MIPSEL)
+ stmt(IRStmt_LLSC(Iend_LE, t2, mkexpr(t1), NULL /*this is a load */ ));
+#elif defined (_MIPSEB)
+ stmt(IRStmt_LLSC(Iend_BE, t2, mkexpr(t1), NULL /*this is a load */ ));
+#endif
+
+ putIReg(rt, mkexpr(t2));
+ break;
+
+ case 0x38: /* SC / SWC0 */
+ DIP("sc r%d, %d(r%d)", rt, imm, rs);
+ LOAD_STORE_PATTERN;
+
+ t2 = newTemp(Ity_I1);
+#if defined (_MIPSEL)
+ stmt(IRStmt_LLSC(Iend_LE, t2, mkexpr(t1), mkNarrowTo32(ty, getIReg(rt))));
+#elif defined (_MIPSEB)
+ stmt(IRStmt_LLSC(Iend_BE, t2, mkexpr(t1), mkNarrowTo32(ty, getIReg(rt))));
+#endif
+
+ putIReg(rt, unop(Iop_1Uto32, mkexpr(t2)));
+ break;
+
+ decode_failure:
+ /* All decode failures end up here. */
+ DIP("vex mips->IR: unhandled instruction bytes: "
+ "0x%x 0x%x 0x%x 0x%x\n",
+ (Int) getIByte(delta_start + 0),
+ (Int) getIByte(delta_start + 1),
+ (Int) getIByte(delta_start + 2),
+ (Int) getIByte(delta_start + 3));
+
+ /* Tell the dispatcher that this insn cannot be decoded, and so has
+ not been executed, and (is currently) the next to be executed.
+ EIP should be up-to-date since it made so at the start bnezof each
+ insn, but nevertheless be paranoid and update it again right
+ now. */
+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_PC),
+ mkU32(guest_PC_curr_instr)));
+ jmp_lit(&dres, Ijk_NoDecode, guest_PC_curr_instr);
+ dres.whatNext = Dis_StopHere;
+ dres.len = 0;
+ return dres;
+ } /* switch (opc) for the main (primary) opcode switch. */
+
+ /* All MIPS insn have 4 bytes */
+
+ if (delay_slot_branch) {
+ delay_slot_branch = False;
+ stmt(bstmt);
+ bstmt = NULL;
+ putPC(mkU32(guest_PC_curr_instr + 4));
+ dres.jk_StopHere = is_Branch_or_Jump_and_Link(guest_code + delta - 4) ?
+ Ijk_Call : Ijk_Boring;
+ }
+
+ if (likely_delay_slot) {
+ dres.jk_StopHere = Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
+ putPC(lastn);
+ lastn = NULL;
+ }
+ if (delay_slot_jump) {
+ putPC(lastn);
+ lastn = NULL;
+ dres.jk_StopHere = is_Branch_or_Jump_and_Link(guest_code + delta - 4) ?
+ Ijk_Call : Ijk_Boring;
+ }
+
+ decode_success:
+ /* All decode successes end up here. */
+ switch (dres.whatNext) {
+ case Dis_Continue:
+ putPC(mkU32(guest_PC_curr_instr + 4));
+ break;
+ case Dis_ResteerU:
+ case Dis_ResteerC:
+ putPC(mkU32(dres.continueAt));
+ break;
+ case Dis_StopHere:
+ break;
+ default:
+ vassert(0);
+ break;
+ }
+
+ // On MIPS we need to check if the last instruction
+ // in block is branch or jump
+ if ((vex_control.guest_max_insns - 1) == (delta+4)/4)
+ if (branch_or_jump(guest_code + delta + 4)) {
+ dres.whatNext = Dis_StopHere;
+ dres.jk_StopHere = Ijk_Boring;
+ putPC(mkU32(guest_PC_curr_instr + 4));
+ }
+ dres.len = 4;
+
+ DIP("\n");
+
+ return dres;
+
+}
+
+/*------------------------------------------------------------*/
+/*--- Top-level fn ---*/
+/*------------------------------------------------------------*/
+
+/* Disassemble a single instruction into IR. The instruction
+ is located in host memory at &guest_code[delta]. */
+
+DisResult
+disInstr_MIPS(IRSB* irsb_IN,
+ Bool (*resteerOkFn) (void *, Addr64),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ UChar* guest_code_IN,
+ Long delta,
+ Addr64 guest_IP,
+ VexArch guest_arch,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian_IN)
+{
+ DisResult dres;
+
+ /* Set globals (see top of this file) */
+ vassert(guest_arch == VexArchMIPS32);
+
+ mode64 = guest_arch != VexArchMIPS32;
+
+ guest_code = guest_code_IN;
+ irsb = irsb_IN;
+ host_is_bigendian = host_bigendian_IN;
+ guest_PC_curr_instr = (Addr32) guest_IP;
+ guest_PC_bbstart = (Addr32) toUInt(guest_IP - delta);
+
+ dres = disInstr_MIPS_WRK(resteerOkFn, resteerCisOk, callback_opaque,
+ delta, archinfo, abiinfo);
+
+ return dres;
+}
+
+/*--------------------------------------------------------------------*/
+/*--- end guest_mips_toIR.c ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/VEX/priv/guest_ppc_defs.h b/main/VEX/priv/guest_ppc_defs.h
index 7c8dc8e..7433298 100644
--- a/main/VEX/priv/guest_ppc_defs.h
+++ b/main/VEX/priv/guest_ppc_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -48,7 +48,6 @@
bb_to_IR.h. */
extern
DisResult disInstr_PPC ( IRSB* irbb,
- Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
diff --git a/main/VEX/priv/guest_ppc_helpers.c b/main/VEX/priv/guest_ppc_helpers.c
index b8a3cd0..6ffb1ea 100644
--- a/main/VEX/priv/guest_ppc_helpers.c
+++ b/main/VEX/priv/guest_ppc_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -352,6 +352,11 @@
void LibVEX_GuestPPC32_initialise ( /*OUT*/VexGuestPPC32State* vex_state )
{
Int i;
+ vex_state->host_EvC_FAILADDR = 0;
+ vex_state->host_EvC_COUNTER = 0;
+ vex_state->pad3 = 0;
+ vex_state->pad4 = 0;
+
vex_state->guest_GPR0 = 0;
vex_state->guest_GPR1 = 0;
vex_state->guest_GPR2 = 0;
@@ -385,7 +390,6 @@
vex_state->guest_GPR30 = 0;
vex_state->guest_GPR31 = 0;
-
/* Initialise the vector state. */
# define VECZERO(_vr) _vr[0]=_vr[1]=_vr[2]=_vr[3] = 0;
@@ -482,7 +486,10 @@
vex_state->guest_CR7_321 = 0;
vex_state->guest_CR7_0 = 0;
- vex_state->guest_FPROUND = (UInt)PPCrm_NEAREST;
+ vex_state->guest_FPROUND = PPCrm_NEAREST;
+ vex_state->guest_DFPROUND = PPCrm_NEAREST;
+ vex_state->pad1 = 0;
+ vex_state->pad2 = 0;
vex_state->guest_VRSAVE = 0;
@@ -502,6 +509,8 @@
vex_state->guest_IP_AT_SYSCALL = 0;
vex_state->guest_SPRG3_RO = 0;
+
+ vex_state->padding = 0;
}
@@ -509,6 +518,9 @@
void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
{
Int i;
+ vex_state->host_EvC_FAILADDR = 0;
+ vex_state->host_EvC_COUNTER = 0;
+ vex_state->pad0 = 0;
vex_state->guest_GPR0 = 0;
vex_state->guest_GPR1 = 0;
vex_state->guest_GPR2 = 0;
@@ -638,7 +650,10 @@
vex_state->guest_CR7_321 = 0;
vex_state->guest_CR7_0 = 0;
- vex_state->guest_FPROUND = (UInt)PPCrm_NEAREST;
+ vex_state->guest_FPROUND = PPCrm_NEAREST;
+ vex_state->guest_DFPROUND = PPCrm_NEAREST;
+ vex_state->pad1 = 0;
+ vex_state->pad2 = 0;
vex_state->guest_VRSAVE = 0;
@@ -662,6 +677,8 @@
vex_state->guest_SPRG3_RO = 0;
vex_state->padding2 = 0;
+ vex_state->padding3 = 0;
+ vex_state->padding4 = 0;
}
diff --git a/main/VEX/priv/guest_ppc_toIR.c b/main/VEX/priv/guest_ppc_toIR.c
index 8789c12..0ca00d8 100644
--- a/main/VEX/priv/guest_ppc_toIR.c
+++ b/main/VEX/priv/guest_ppc_toIR.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -222,6 +222,7 @@
#define OFFB_XER_CA offsetofPPCGuestState(guest_XER_CA)
#define OFFB_XER_BC offsetofPPCGuestState(guest_XER_BC)
#define OFFB_FPROUND offsetofPPCGuestState(guest_FPROUND)
+#define OFFB_DFPROUND offsetofPPCGuestState(guest_DFPROUND)
#define OFFB_VRSAVE offsetofPPCGuestState(guest_VRSAVE)
#define OFFB_VSCR offsetofPPCGuestState(guest_VSCR)
#define OFFB_EMWARN offsetofPPCGuestState(guest_EMWARN)
@@ -253,6 +254,11 @@
return IFIELD( instr, 1, 9 );
}
+/* Extract 8-bit secondary opcode, instr[8:1] */
+static UInt ifieldOPClo8 ( UInt instr) {
+ return IFIELD( instr, 1, 8 );
+}
+
/* Extract 5-bit secondary opcode, instr[5:1] */
static UInt ifieldOPClo5 ( UInt instr) {
return IFIELD( instr, 1, 5 );
@@ -373,8 +379,8 @@
PPC_GST_MAX
} PPC_GST;
-#define MASK_FPSCR_RN 0x3
-#define MASK_FPSCR_FPRF 0x1F000
+#define MASK_FPSCR_RN 0x3ULL // Binary floating point rounding mode
+#define MASK_FPSCR_DRN 0x700000000ULL // Decimal floating point rounding mode
#define MASK_VSCR_VALID 0x00010001
@@ -415,7 +421,6 @@
return mask;
}
-/* ditto for 64bit mask */
static ULong MASK64( UInt begin, UInt end )
{
ULong m1, m2, mask;
@@ -1114,6 +1119,45 @@
stmt( IRStmt_Put(floatGuestRegOffset(archreg), e) );
}
+/* get Decimal float value. Note, they share floating point register file. */
+static IRExpr* getDReg(UInt archreg) {
+ IRExpr *e;
+ vassert( archreg < 32 );
+ e = IRExpr_Get( floatGuestRegOffset( archreg ), Ity_D64 );
+ return e;
+}
+
+/* Read a floating point register pair and combine their contents into a
+ 128-bit value */
+static IRExpr *getDReg_pair(UInt archreg) {
+ IRExpr *high = getDReg( archreg );
+ IRExpr *low = getDReg( archreg + 1 );
+
+ return binop( Iop_D64HLtoD128, high, low );
+}
+
+/* Ditto, but write to a reg instead. */
+static void putDReg(UInt archreg, IRExpr* e) {
+ vassert( archreg < 32 );
+ vassert( typeOfIRExpr(irsb->tyenv, e) == Ity_D64 );
+ stmt( IRStmt_Put( floatGuestRegOffset( archreg ), e ) );
+}
+
+/* Write a 128-bit floating point value into a register pair. */
+static void putDReg_pair(UInt archreg, IRExpr *e) {
+ IRTemp low = newTemp( Ity_D64 );
+ IRTemp high = newTemp( Ity_D64 );
+
+ vassert( archreg < 32 );
+ vassert( typeOfIRExpr(irsb->tyenv, e) == Ity_D128 );
+
+ assign( low, unop( Iop_D128LOtoD64, e ) );
+ assign( high, unop( Iop_D128HItoD64, e ) );
+
+ stmt( IRStmt_Put( floatGuestRegOffset( archreg ), mkexpr( high ) ) );
+ stmt( IRStmt_Put( floatGuestRegOffset( archreg + 1 ), mkexpr( low ) ) );
+}
+
static Int vsxGuestRegOffset ( UInt archreg )
{
vassert(archreg < 64);
@@ -1293,9 +1337,9 @@
/* Generate an IR sequence to do a popcount operation on the supplied
IRTemp, and return a new IRTemp holding the result. 'ty' may be
Ity_I32 or Ity_I64 only. */
-static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src )
+static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src, Bool byte_count )
{
- Int i, shift[6];
+ Int i, shift[6], max;
IRTemp mask[6];
IRTemp old = IRTemp_INVALID;
IRTemp nyu = IRTemp_INVALID;
@@ -1303,6 +1347,14 @@
vassert(ty == Ity_I64 || ty == Ity_I32);
if (ty == Ity_I32) {
+ if (byte_count)
+ /* Return the population count across each byte not across the entire
+ * 32-bit value. Stop after third iteration.
+ */
+ max = 3;
+ else
+ max = 5;
+
for (i = 0; i < 5; i++) {
mask[i] = newTemp(ty);
shift[i] = 1 << i;
@@ -1313,7 +1365,7 @@
assign(mask[3], mkU32(0x00FF00FF));
assign(mask[4], mkU32(0x0000FFFF));
old = src;
- for (i = 0; i < 5; i++) {
+ for (i = 0; i < max; i++) {
nyu = newTemp(ty);
assign(nyu,
binop(Iop_Add32,
@@ -1328,6 +1380,14 @@
return nyu;
}
// else, ty == Ity_I64
+ if (byte_count)
+ /* Return the population count across each byte not across the entire
+ * 64-bit value. Stop after third iteration.
+ */
+ max = 3;
+ else
+ max = 6;
+
for (i = 0; i < 6; i++) {
mask[i] = newTemp( Ity_I64 );
shift[i] = 1 << i;
@@ -1339,7 +1399,7 @@
assign( mask[4], mkU64( 0x0000FFFF0000FFFFULL ) );
assign( mask[5], mkU64( 0x00000000FFFFFFFFULL ) );
old = src;
- for (i = 0; i < 6; i++) {
+ for (i = 0; i < max; i++) {
nyu = newTemp( Ity_I64 );
assign( nyu,
binop( Iop_Add64,
@@ -1466,7 +1526,7 @@
binop(Iop_And64, mkexpr(addr), mkU64(align-1)),
mkU64(0)),
Ijk_SigBUS,
- IRConst_U64( guest_CIA_curr_instr )
+ IRConst_U64( guest_CIA_curr_instr ), OFFB_CIA
)
);
} else {
@@ -1477,7 +1537,7 @@
binop(Iop_And32, mkexpr(addr), mkU32(align-1)),
mkU32(0)),
Ijk_SigBUS,
- IRConst_U32( guest_CIA_curr_instr )
+ IRConst_U32( guest_CIA_curr_instr ), OFFB_CIA
)
);
}
@@ -2464,10 +2524,12 @@
all exceptions masked, round-to-nearest.
This corresponds to a FPSCR value of 0x0. */
- /* We're only keeping track of the rounding mode,
- so if the mask isn't asking for this, just return 0x0 */
- if (mask & (MASK_FPSCR_RN|MASK_FPSCR_FPRF)) {
- assign( val, IRExpr_Get( OFFB_FPROUND, Ity_I32 ) );
+ /* In the lower 32 bits of FPSCR, we're only keeping track of
+ * the binary floating point rounding mode, so if the mask isn't
+ * asking for this, just return 0x0.
+ */
+ if (mask & MASK_FPSCR_RN) {
+ assign( val, unop( Iop_8Uto32, IRExpr_Get( OFFB_FPROUND, Ity_I8 ) ) );
} else {
assign( val, mkU32(0x0) );
}
@@ -2486,6 +2548,36 @@
}
}
+/* Get a masked word from the given reg */
+static IRExpr* /* ::Ity_I32 */getGST_masked_upper(PPC_GST reg, ULong mask) {
+ IRExpr * val;
+ vassert( reg < PPC_GST_MAX );
+
+ switch (reg) {
+
+ case PPC_GST_FPSCR: {
+ /* In the upper 32 bits of FPSCR, we're only keeping track
+ * of the decimal floating point rounding mode, so if the mask
+ * isn't asking for this, just return 0x0.
+ */
+ if (mask & MASK_FPSCR_DRN) {
+ val = binop( Iop_And32,
+ unop( Iop_8Uto32, IRExpr_Get( OFFB_DFPROUND, Ity_I8 ) ),
+ unop( Iop_64HIto32, mkU64( mask ) ) );
+ } else {
+ val = mkU32( 0x0ULL );
+ }
+ break;
+ }
+
+ default:
+ vex_printf( "getGST_masked_upper(ppc): reg = %u", reg );
+ vpanic( "getGST_masked_upper(ppc)" );
+ }
+ return val;
+}
+
+
/* Fetch the specified REG[FLD] nibble (as per IBM/hardware notation)
and return it at the bottom of an I32; the top 27 bits are
guaranteed to be zero. */
@@ -2581,32 +2673,30 @@
}
/* Write masked src to the given reg */
-static void putGST_masked ( PPC_GST reg, IRExpr* src, UInt mask )
+static void putGST_masked ( PPC_GST reg, IRExpr* src, ULong mask )
{
IRType ty = mode64 ? Ity_I64 : Ity_I32;
vassert( reg < PPC_GST_MAX );
- vassert( typeOfIRExpr(irsb->tyenv,src ) == Ity_I32 );
-
+ vassert( typeOfIRExpr( irsb->tyenv,src ) == Ity_I64 );
+
switch (reg) {
case PPC_GST_FPSCR: {
- /* Allow writes to Rounding Mode */
- if (mask & (MASK_FPSCR_RN|MASK_FPSCR_FPRF)) {
- /* construct new fpround from new and old values as per mask:
- new fpround = (src & (3 & mask)) | (fpround & (3 & ~mask)) */
- stmt(
- IRStmt_Put(
- OFFB_FPROUND,
- binop(
- Iop_Or32,
- binop(Iop_And32, src, mkU32((MASK_FPSCR_RN|MASK_FPSCR_FPRF) & mask)),
- binop(
- Iop_And32,
- IRExpr_Get(OFFB_FPROUND,Ity_I32),
- mkU32((MASK_FPSCR_RN|MASK_FPSCR_FPRF) & ~mask)
- )
- )
- )
- );
+ /* Allow writes to either binary or decimal floating point
+ * Rounding Mode
+ */
+ if (mask & MASK_FPSCR_RN) {
+ stmt( IRStmt_Put( OFFB_FPROUND,
+ unop( Iop_32to8,
+ binop( Iop_And32,
+ unop( Iop_64to32, src ),
+ mkU32( MASK_FPSCR_RN & mask ) ) ) ) );
+ } else if (mask & MASK_FPSCR_DRN) {
+ stmt( IRStmt_Put( OFFB_DFPROUND,
+ unop( Iop_32to8,
+ binop( Iop_And32,
+ unop( Iop_64HIto32, src ),
+ mkU32( ( MASK_FPSCR_DRN & mask )
+ >> 32 ) ) ) ) );
}
/* Give EmWarn for attempted writes to:
@@ -2624,7 +2714,7 @@
IRStmt_Exit(
binop(Iop_CmpNE32, mkU32(ew), mkU32(EmWarn_NONE)),
Ijk_EmWarn,
- mkSzConst( ty, nextInsnAddr()) ));
+ mkSzConst( ty, nextInsnAddr()), OFFB_CIA ));
}
/* Ignore all other writes */
@@ -2641,13 +2731,17 @@
REG[FLD] (as per IBM/hardware notation). */
static void putGST_field ( PPC_GST reg, IRExpr* src, UInt fld )
{
- UInt shft, mask;
+ UInt shft;
+ ULong mask;
vassert( typeOfIRExpr(irsb->tyenv,src ) == Ity_I32 );
- vassert( fld < 8 );
+ vassert( fld < 16 );
vassert( reg < PPC_GST_MAX );
- shft = 4*(7-fld);
+ if (fld < 8)
+ shft = 4*(7-fld);
+ else
+ shft = 4*(15-fld);
mask = 0xF<<shft;
switch (reg) {
@@ -2657,12 +2751,16 @@
break;
default:
- if (shft == 0) {
- putGST_masked( reg, src, mask );
- } else {
- putGST_masked( reg,
- binop(Iop_Shl32, src, mkU8(toUChar(shft))),
- mask );
+ {
+ IRExpr * src64 = unop( Iop_32Uto64, src );
+
+ if (shft == 0) {
+ putGST_masked( reg, src64, mask );
+ } else {
+ putGST_masked( reg,
+ binop( Iop_Shl64, src64, mkU8( toUChar( shft ) ) ),
+ mask );
+ }
}
}
}
@@ -3902,7 +4000,7 @@
case 0x1FA: // popcntd (population count doubleword
{
DIP("popcntd r%u,r%u\n", rA_addr, rS_addr);
- IRTemp result = gen_POPCOUNT(ty, rS);
+ IRTemp result = gen_POPCOUNT(ty, rS, False);
putIReg( rA_addr, mkexpr(result) );
return True;
}
@@ -3915,11 +4013,31 @@
IRTemp argHi = newTemp(Ity_I32);
assign(argLo, unop(Iop_64to32, mkexpr(rS)));
assign(argHi, unop(Iop_64HIto32, mkexpr(rS)));
- resultLo = gen_POPCOUNT(Ity_I32, argLo);
- resultHi = gen_POPCOUNT(Ity_I32, argHi);
+ resultLo = gen_POPCOUNT(Ity_I32, argLo, False);
+ resultHi = gen_POPCOUNT(Ity_I32, argHi, False);
putIReg( rA_addr, binop(Iop_32HLto64, mkexpr(resultHi), mkexpr(resultLo)));
} else {
- IRTemp result = gen_POPCOUNT(ty, rS);
+ IRTemp result = gen_POPCOUNT(ty, rS, False);
+ putIReg( rA_addr, mkexpr(result) );
+ }
+ return True;
+ }
+ case 0x7A: // popcntb (Population Count Byte)
+ {
+ DIP("popcntb r%u,r%u\n", rA_addr, rS_addr);
+
+ if (mode64) {
+ IRTemp resultHi, resultLo;
+ IRTemp argLo = newTemp(Ity_I32);
+ IRTemp argHi = newTemp(Ity_I32);
+ assign(argLo, unop(Iop_64to32, mkexpr(rS)));
+ assign(argHi, unop(Iop_64HIto32, mkexpr(rS)));
+ resultLo = gen_POPCOUNT(Ity_I32, argLo, True);
+ resultHi = gen_POPCOUNT(Ity_I32, argHi, True);
+ putIReg( rA_addr, binop(Iop_32HLto64, mkexpr(resultHi),
+ mkexpr(resultLo)));
+ } else {
+ IRTemp result = gen_POPCOUNT(ty, rS, True);
putIReg( rA_addr, mkexpr(result) );
}
return True;
@@ -4900,7 +5018,7 @@
/* if (nBytes < (i+1)) goto NIA; */
stmt( IRStmt_Exit( binop(Iop_CmpLT32U, e_nbytes, mkU32(i+1)),
Ijk_Boring,
- mkSzConst( ty, nextInsnAddr()) ));
+ mkSzConst( ty, nextInsnAddr()), OFFB_CIA ));
/* when crossing into a new dest register, set it to zero. */
if ((i % 4) == 0) {
rD++; if (rD == 32) rD = 0;
@@ -4951,7 +5069,7 @@
/* if (nBytes < (i+1)) goto NIA; */
stmt( IRStmt_Exit( binop(Iop_CmpLT32U, e_nbytes, mkU32(i+1)),
Ijk_Boring,
- mkSzConst( ty, nextInsnAddr() ) ));
+ mkSzConst( ty, nextInsnAddr() ), OFFB_CIA ));
/* check for crossing into a new src register. */
if ((i % 4) == 0) {
rS++; if (rS == 32) rS = 0;
@@ -5173,6 +5291,7 @@
/* The default what-next. Individual cases can override it. */
dres->whatNext = Dis_StopHere;
+ vassert(dres->jk_StopHere == Ijk_INVALID);
switch (opc1) {
case 0x12: // b (Branch, PPC32 p360)
@@ -5205,8 +5324,8 @@
dres->whatNext = Dis_ResteerU;
dres->continueAt = tgt;
} else {
- irsb->jumpkind = flag_LK ? Ijk_Call : Ijk_Boring;
- irsb->next = mkSzImm(ty, tgt);
+ dres->jk_StopHere = flag_LK ? Ijk_Call : Ijk_Boring; ;
+ putGST( PPC_GST_CIA, mkSzImm(ty, tgt) );
}
break;
@@ -5242,10 +5361,10 @@
stmt( IRStmt_Exit(
binop(Iop_CmpNE32, mkexpr(do_branch), mkU32(0)),
flag_LK ? Ijk_Call : Ijk_Boring,
- mkSzConst(ty, tgt) ) );
-
- irsb->jumpkind = Ijk_Boring;
- irsb->next = e_nia;
+ mkSzConst(ty, tgt), OFFB_CIA ) );
+
+ dres->jk_StopHere = Ijk_Boring;
+ putGST( PPC_GST_CIA, e_nia );
break;
case 0x13:
@@ -5277,15 +5396,15 @@
stmt( IRStmt_Exit(
binop(Iop_CmpEQ32, mkexpr(cond_ok), mkU32(0)),
Ijk_Boring,
- c_nia ));
+ c_nia, OFFB_CIA ));
if (flag_LK && vbi->guest_ppc_zap_RZ_at_bl) {
make_redzone_AbiHint( vbi, lr_old,
"b-ctr-l (indirect call)" );
}
- irsb->jumpkind = flag_LK ? Ijk_Call : Ijk_Boring;
- irsb->next = mkexpr(lr_old);
+ dres->jk_StopHere = flag_LK ? Ijk_Call : Ijk_Boring;;
+ putGST( PPC_GST_CIA, mkexpr(lr_old) );
break;
case 0x010: { // bclr (Branch Cond. to Link Register, PPC32 p365)
@@ -5317,7 +5436,7 @@
stmt( IRStmt_Exit(
binop(Iop_CmpEQ32, mkexpr(do_branch), mkU32(0)),
Ijk_Boring,
- c_nia ));
+ c_nia, OFFB_CIA ));
if (vanilla_return && vbi->guest_ppc_zap_RZ_at_blr) {
make_redzone_AbiHint( vbi, lr_old,
@@ -5327,8 +5446,8 @@
/* blrl is pretty strange; it's like a return that sets the
return address of its caller to the insn following this
one. Mark it as a return. */
- irsb->jumpkind = Ijk_Ret; /* was flag_LK ? Ijk_Call : Ijk_Ret; */
- irsb->next = mkexpr(lr_old);
+ dres->jk_StopHere = Ijk_Ret; /* was flag_LK ? Ijk_Call : Ijk_Ret; */
+ putGST( PPC_GST_CIA, mkexpr(lr_old) );
break;
}
default:
@@ -5484,7 +5603,8 @@
stmt( IRStmt_Exit(
binop(opCMPEQ, const0, const0),
Ijk_SigTRAP,
- mode64 ? IRConst_U64(cia) : IRConst_U32((UInt)cia)
+ mode64 ? IRConst_U64(cia) : IRConst_U32((UInt)cia),
+ OFFB_CIA
));
return True; /* unconditional trap */
}
@@ -5527,7 +5647,8 @@
stmt( IRStmt_Exit(
binop(opCMPNE, cond, const0),
Ijk_SigTRAP,
- mode64 ? IRConst_U64(cia) : IRConst_U32((UInt)cia)
+ mode64 ? IRConst_U64(cia) : IRConst_U32((UInt)cia),
+ OFFB_CIA
));
return False; /* not an unconditional trap */
}
@@ -5575,9 +5696,9 @@
if (uncond) {
/* If the trap shows signs of being unconditional, don't
continue decoding past it. */
- irsb->next = mkSzImm( ty, nextInsnAddr() );
- irsb->jumpkind = Ijk_Boring;
- dres->whatNext = Dis_StopHere;
+ putGST( PPC_GST_CIA, mkSzImm( ty, nextInsnAddr() ));
+ dres->jk_StopHere = Ijk_Boring;
+ dres->whatNext = Dis_StopHere;
}
return True;
@@ -5629,9 +5750,9 @@
if (uncond) {
/* If the trap shows signs of being unconditional, don't
continue decoding past it. */
- irsb->next = mkSzImm( ty, nextInsnAddr() );
- irsb->jumpkind = Ijk_Boring;
- dres->whatNext = Dis_StopHere;
+ putGST( PPC_GST_CIA, mkSzImm( ty, nextInsnAddr() ));
+ dres->jk_StopHere = Ijk_Boring;
+ dres->whatNext = Dis_StopHere;
}
return True;
@@ -5662,12 +5783,12 @@
/* It's important that all ArchRegs carry their up-to-date value
at this point. So we declare an end-of-block here, which
forces any TempRegs caching ArchRegs to be flushed. */
- irsb->next = abiinfo->guest_ppc_sc_continues_at_LR
- ? getGST( PPC_GST_LR )
- : mkSzImm( ty, nextInsnAddr() );
- irsb->jumpkind = Ijk_Sys_syscall;
+ putGST( PPC_GST_CIA, abiinfo->guest_ppc_sc_continues_at_LR
+ ? getGST( PPC_GST_LR )
+ : mkSzImm( ty, nextInsnAddr() ));
- dres->whatNext = Dis_StopHere;
+ dres->whatNext = Dis_StopHere;
+ dres->jk_StopHere = Ijk_Sys_syscall;
return True;
}
@@ -6645,9 +6766,9 @@
/* be paranoid ... */
stmt( IRStmt_MBE(Imbe_Fence) );
- irsb->jumpkind = Ijk_TInval;
- irsb->next = mkSzImm(ty, nextInsnAddr());
- dres->whatNext = Dis_StopHere;
+ putGST( PPC_GST_CIA, mkSzImm(ty, nextInsnAddr()));
+ dres->jk_StopHere = Ijk_TInval;
+ dres->whatNext = Dis_StopHere;
break;
}
@@ -6689,6 +6810,118 @@
mkU32(2) ));
}
+/* The DFP IR rounding modes were chosen such that the existing PPC to IR
+ * mapping would still work with the extended three bit DFP rounding
+ * mode designator.
+
+ * rounding mode | PPC | IR
+ * -----------------------------------------------
+ * to nearest, ties to even | 000 | 000
+ * to zero | 001 | 011
+ * to +infinity | 010 | 010
+ * to -infinity | 011 | 001
+ * to nearest, ties away from 0 | 100 | 100
+ * to nearest, ties toward 0 | 101 | 111
+ * to away from 0 | 110 | 110
+ * to prepare for shorter precision | 111 | 101
+ */
+static IRExpr* /* :: Ity_I32 */ get_IR_roundingmode_DFP( void )
+{
+ IRTemp rm_PPC32 = newTemp( Ity_I32 );
+ assign( rm_PPC32, getGST_masked_upper( PPC_GST_FPSCR, MASK_FPSCR_DRN ) );
+
+ // rm_IR = XOR( rm_PPC32, (rm_PPC32 << 1) & 2)
+ return binop( Iop_Xor32,
+ mkexpr( rm_PPC32 ),
+ binop( Iop_And32,
+ binop( Iop_Shl32, mkexpr( rm_PPC32 ), mkU8( 1 ) ),
+ mkU32( 2 ) ) );
+}
+
+#define NANmaskSingle 0x7F800000
+#define NANmaskDouble 0x7FF00000
+
+static IRExpr * Check_NaN( IRExpr * value, IRExpr * Hi32Mask )
+{
+ IRTemp exp_zero = newTemp(Ity_I8);
+ IRTemp frac_mask = newTemp(Ity_I32);
+ IRTemp frac_not_zero = newTemp(Ity_I8);
+
+ /* Check if the result is QNAN or SNAN and not +infinity or -infinity.
+ * The input value is always 64-bits, for single precision values, the
+ * lower 32 bits must be zero.
+ *
+ * Single Pricision
+ * [62:54] exponent field is equal to 0xFF for NAN and Infinity.
+ * [53:32] fraction field is zero for Infinity and non-zero for NAN
+ * [31:0] unused for single precision representation
+ *
+ * Double Pricision
+ * [62:51] exponent field is equal to 0xFF for NAN and Infinity.
+ * [50:0] fraction field is zero for Infinity and non-zero for NAN
+ *
+ * Returned result is a U32 value of 0xFFFFFFFF for NaN and 0 otherwise.
+ */
+ assign( frac_mask, unop( Iop_Not32,
+ binop( Iop_Or32,
+ mkU32( 0x80000000ULL ), Hi32Mask) ) );
+
+ assign( exp_zero,
+ unop( Iop_1Sto8,
+ binop( Iop_CmpEQ32,
+ binop( Iop_And32,
+ unop( Iop_64HIto32,
+ unop( Iop_ReinterpF64asI64,
+ value ) ),
+ Hi32Mask ),
+ Hi32Mask ) ) );
+ assign( frac_not_zero,
+ binop( Iop_Or8,
+ unop( Iop_1Sto8,
+ binop( Iop_CmpNE32,
+ binop( Iop_And32,
+ unop( Iop_64HIto32,
+ unop( Iop_ReinterpF64asI64,
+ value ) ),
+ mkexpr( frac_mask ) ),
+ mkU32( 0x0 ) ) ),
+ unop( Iop_1Sto8,
+ binop( Iop_CmpNE32,
+ binop( Iop_And32,
+ unop( Iop_64to32,
+ unop( Iop_ReinterpF64asI64,
+ value ) ),
+ mkU32( 0xFFFFFFFF ) ),
+ mkU32( 0x0 ) ) ) ) );
+ return unop( Iop_8Sto32,
+ binop( Iop_And8,
+ mkexpr( exp_zero ),
+ mkexpr( frac_not_zero ) ) );
+}
+
+static IRExpr * Complement_non_NaN( IRExpr * value, IRExpr * nan_mask )
+{
+ /* This function will only complement the 64-bit floating point value if it
+ * is not Nan. NaN is not a signed value. Need to do computations using
+ * 32-bit operands to ensure it will run in 32-bit mode.
+ */
+ return binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ nan_mask,
+ unop( Iop_64HIto32,
+ unop( Iop_ReinterpF64asI64,
+ value ) ) ),
+ binop( Iop_And32,
+ unop( Iop_Not32,
+ nan_mask ),
+ unop( Iop_64HIto32,
+ unop( Iop_ReinterpF64asI64,
+ unop( Iop_NegF64,
+ value ) ) ) ) ),
+ unop( Iop_64to32,
+ unop( Iop_ReinterpF64asI64, value ) ) );
+}
/*------------------------------------------------------------*/
/*--- Floating Point Instruction Translation ---*/
@@ -7221,6 +7454,9 @@
IRTemp frB = newTemp(Ity_F64);
IRTemp frC = newTemp(Ity_F64);
IRTemp rmt = newTemp(Ity_I32);
+ IRTemp tmp = newTemp(Ity_F64);
+ IRTemp sign_tmp = newTemp(Ity_I64);
+ IRTemp nan_mask = newTemp(Ity_I32);
IRExpr* rm;
/* By default, we will examine the results of the operation and set
@@ -7270,19 +7506,25 @@
break;
case 0x1E: // fnmsubs (Float Neg Mult-Subtr Single, PPC32 p420)
- DIP("fnmsubs%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"",
- frD_addr, frA_addr, frC_addr, frB_addr);
- assign( frD, unop( Iop_NegF64,
- qop( Iop_MSubF64r32, rm,
- mkexpr(frA), mkexpr(frC), mkexpr(frB) )));
- break;
-
case 0x1F: // fnmadds (Floating Negative Multiply-Add Single, PPC32 p418)
- DIP("fnmadds%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"",
- frD_addr, frA_addr, frC_addr, frB_addr);
- assign( frD, unop( Iop_NegF64,
- qop( Iop_MAddF64r32, rm,
- mkexpr(frA), mkexpr(frC), mkexpr(frB) )));
+
+ if (opc2 == 0x1E) {
+ DIP("fnmsubs%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"",
+ frD_addr, frA_addr, frC_addr, frB_addr);
+ assign( tmp, qop( Iop_MSubF64r32, rm,
+ mkexpr(frA), mkexpr(frC), mkexpr(frB) ) );
+ } else {
+ DIP("fnmadds%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"",
+ frD_addr, frA_addr, frC_addr, frB_addr);
+ assign( tmp, qop( Iop_MAddF64r32, rm,
+ mkexpr(frA), mkexpr(frC), mkexpr(frB) ) );
+ }
+
+ assign( nan_mask, Check_NaN( mkexpr( tmp ),
+ mkU32( NANmaskSingle ) ) );
+ assign( sign_tmp, Complement_non_NaN( mkexpr( tmp ),
+ mkexpr( nan_mask ) ) );
+ assign( frD, unop( Iop_ReinterpI64asF64, mkexpr( sign_tmp ) ) );
break;
default:
@@ -7308,19 +7550,25 @@
break;
case 0x1E: // fnmsub (Float Neg Mult-Subtr (Dbl Precision), PPC32 p419)
- DIP("fnmsub%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"",
- frD_addr, frA_addr, frC_addr, frB_addr);
- assign( frD, unop( Iop_NegF64,
- qop( Iop_MSubF64, rm,
- mkexpr(frA), mkexpr(frC), mkexpr(frB) )));
- break;
-
case 0x1F: // fnmadd (Float Neg Mult-Add (Dbl Precision), PPC32 p417)
- DIP("fnmadd%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"",
- frD_addr, frA_addr, frC_addr, frB_addr);
- assign( frD, unop( Iop_NegF64,
- qop( Iop_MAddF64, rm,
- mkexpr(frA), mkexpr(frC), mkexpr(frB) )));
+
+ if (opc2 == 0x1E) {
+ DIP("fnmsub%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"",
+ frD_addr, frA_addr, frC_addr, frB_addr);
+ assign( tmp, qop( Iop_MSubF64, rm,
+ mkexpr(frA), mkexpr(frC), mkexpr(frB) ) );
+ } else {
+ DIP("fnmadd%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"",
+ frD_addr, frA_addr, frC_addr, frB_addr);
+ assign( tmp, qop( Iop_MAddF64, rm,
+ mkexpr(frA), mkexpr(frC), mkexpr(frB) ));
+ }
+
+ assign( nan_mask, Check_NaN( mkexpr( tmp ),
+ mkU32( NANmaskDouble ) ) );
+ assign( sign_tmp, Complement_non_NaN( mkexpr( tmp ),
+ mkexpr( nan_mask ) ) );
+ assign( frD, unop( Iop_ReinterpI64asF64, mkexpr( sign_tmp ) ) );
break;
default:
@@ -8224,7 +8472,7 @@
/*
Floating Point Status/Control Register Instructions
*/
-static Bool dis_fp_scr ( UInt theInstr )
+static Bool dis_fp_scr ( UInt theInstr, Bool GX_level )
{
/* Many forms - see each switch case */
UChar opc1 = ifieldOPC(theInstr);
@@ -8247,7 +8495,8 @@
return False;
}
DIP("mtfsb1%s crb%d \n", flag_rC ? ".":"", crbD);
- putGST_masked( PPC_GST_FPSCR, mkU32(1<<(31-crbD)), 1<<(31-crbD) );
+ putGST_masked( PPC_GST_FPSCR, mkU64( 1 <<( 31 - crbD ) ),
+ 1ULL << ( 31 - crbD ) );
break;
}
@@ -8283,29 +8532,41 @@
return False;
}
DIP("mtfsb0%s crb%d\n", flag_rC ? ".":"", crbD);
- putGST_masked( PPC_GST_FPSCR, mkU32(0), 1<<(31-crbD) );
+ putGST_masked( PPC_GST_FPSCR, mkU64( 0 ), 1ULL << ( 31 - crbD ) );
break;
}
case 0x086: { // mtfsfi (Move to FPSCR Field Immediate, PPC32 p481)
- UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) );
+ UInt crfD = IFIELD( theInstr, 23, 3 );
UChar b16to22 = toUChar( IFIELD( theInstr, 16, 7 ) );
UChar IMM = toUChar( IFIELD( theInstr, 12, 4 ) );
UChar b11 = toUChar( IFIELD( theInstr, 11, 1 ) );
+ UChar Wbit;
if (b16to22 != 0 || b11 != 0) {
vex_printf("dis_fp_scr(ppc)(instr,mtfsfi)\n");
return False;
}
DIP("mtfsfi%s crf%d,%d\n", flag_rC ? ".":"", crfD, IMM);
- putGST_field( PPC_GST_FPSCR, mkU32(IMM), crfD );
+ if (GX_level) {
+ /* This implies that Decimal Floating Point is supported, and the
+ * FPSCR must be managed as a 64-bit register.
+ */
+ Wbit = toUChar( IFIELD(theInstr, 16, 1) );
+ } else {
+ Wbit = 0;
+ }
+ crfD = crfD + (8 * (1 - Wbit) );
+ putGST_field( PPC_GST_FPSCR, mkU32( IMM ), crfD );
break;
}
case 0x247: { // mffs (Move from FPSCR, PPC32 p468)
UChar frD_addr = ifieldRegDS(theInstr);
UInt b11to20 = IFIELD(theInstr, 11, 10);
- IRExpr* fpscr_all = getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN );
+ IRExpr* fpscr_lower = getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN );
+ IRExpr* fpscr_upper = getGST_masked_upper( PPC_GST_FPSCR,
+ MASK_FPSCR_DRN );
if (b11to20 != 0) {
vex_printf("dis_fp_scr(ppc)(instr,mffs)\n");
@@ -8314,7 +8575,7 @@
DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr);
putFReg( frD_addr,
unop( Iop_ReinterpI64asF64,
- unop( Iop_32Uto64, fpscr_all )));
+ binop( Iop_32HLto64, fpscr_upper, fpscr_lower ) ) );
break;
}
@@ -8323,8 +8584,21 @@
UChar FM = toUChar( IFIELD(theInstr, 17, 8) );
UChar frB_addr = ifieldRegB(theInstr);
IRTemp frB = newTemp(Ity_F64);
- IRTemp rB_32 = newTemp(Ity_I32);
- Int i, mask;
+ IRTemp rB_64 = newTemp( Ity_I64 );
+ Int i;
+ ULong mask;
+ UChar Wbit;
+#define BFP_MASK_SEED 0x3000000000000000ULL
+#define DFP_MASK_SEED 0x7000000000000000ULL
+
+ if (GX_level) {
+ /* This implies that Decimal Floating Point is supported, and the
+ * FPSCR must be managed as a 64-bit register.
+ */
+ Wbit = toUChar( IFIELD(theInstr, 16, 1) );
+ } else {
+ Wbit = 0;
+ }
if (b25 == 1) {
/* new 64 bit move variant for power 6. If L field (bit 25) is
@@ -8342,14 +8616,24 @@
mask = 0;
for (i=0; i<8; i++) {
if ((FM & (1<<(7-i))) == 1) {
- mask |= 0xF << (7-i);
+ /* FPSCR field k is set to the contents of the corresponding
+ * field of register FRB, where k = i+8x(1-W). In the Power
+ * ISA, register field numbering is from left to right, so field
+ * 15 is the least significant field in a 64-bit register. To
+ * generate the mask, we set all the appropriate rounding mode
+ * bits in the highest order nibble (field 0) and shift right
+ * 'k x nibble length'.
+ */
+ if (Wbit)
+ mask |= DFP_MASK_SEED >> ( 4 * ( i + 8 * ( 1 - Wbit ) ) );
+ else
+ mask |= BFP_MASK_SEED >> ( 4 * ( i + 8 * ( 1 - Wbit ) ) );
}
}
}
assign( frB, getFReg(frB_addr));
- assign( rB_32, unop( Iop_64to32,
- unop( Iop_ReinterpF64asI64, mkexpr(frB) )));
- putGST_masked( PPC_GST_FPSCR, mkexpr(rB_32), mask );
+ assign( rB_64, unop( Iop_ReinterpF64asI64, mkexpr( frB ) ) );
+ putGST_masked( PPC_GST_FPSCR, mkexpr( rB_64 ), mask );
break;
}
@@ -8360,7 +8644,2874 @@
return True;
}
+/*------------------------------------------------------------*/
+/*--- Decimal Floating Point (DFP) Helper functions ---*/
+/*------------------------------------------------------------*/
+#define DFP_LONG 1
+#define DFP_EXTND 2
+#define DFP_LONG_BIAS 398
+#define DFP_LONG_ENCODED_FIELD_MASK 0x1F00
+#define DFP_EXTND_BIAS 6176
+#define DFP_EXTND_ENCODED_FIELD_MASK 0x1F000
+#define DFP_LONG_EXP_MSK 0XFF
+#define DFP_EXTND_EXP_MSK 0XFFF
+#define DFP_G_FIELD_LONG_MASK 0x7FFC0000 // upper 32-bits only
+#define DFP_LONG_GFIELD_RT_SHIFT (63 - 13 - 32) // adj for upper 32-bits
+#define DFP_G_FIELD_EXTND_MASK 0x7FFFC000 // upper 32-bits only
+#define DFP_EXTND_GFIELD_RT_SHIFT (63 - 17 - 32) //adj for upper 32 bits
+#define DFP_T_FIELD_LONG_MASK 0x3FFFF // mask for upper 32-bits
+#define DFP_T_FIELD_EXTND_MASK 0x03FFFF // mask for upper 32-bits
+#define DFP_LONG_EXP_MAX 369 // biased max
+#define DFP_LONG_EXP_MIN 0 // biased min
+#define DFP_EXTND_EXP_MAX 6111 // biased max
+#define DFP_EXTND_EXP_MIN 0 // biased min
+#define DFP_LONG_MAX_SIG_DIGITS 16
+#define DFP_EXTND_MAX_SIG_DIGITS 34
+#define MAX_DIGITS_IN_STRING 8
+
+
+#define AND(x, y) binop( Iop_And32, x, y )
+#define AND4(w, x, y, z) AND( AND( w, x ), AND( y, z ) )
+#define OR(x, y) binop( Iop_Or32, x, y )
+#define OR3(x, y, z) OR( x, OR( y, z ) )
+#define OR4(w, x, y, z) OR( OR( w, x ), OR( y, z ) )
+#define NOT(x) unop( Iop_1Uto32, unop( Iop_Not1, unop( Iop_32to1, mkexpr( x ) ) ) )
+
+#define SHL(value, by) binop( Iop_Shl32, value, mkU8( by ) )
+#define SHR(value, by) binop( Iop_Shr32, value, mkU8( by ) )
+
+#define BITS5(_b4,_b3,_b2,_b1,_b0) \
+ (((_b4) << 4) | ((_b3) << 3) | ((_b2) << 2) | \
+ ((_b1) << 1) | ((_b0) << 0))
+
+static IRExpr * Gfield_encoding( IRExpr * lmexp, IRExpr * lmd32 )
+{
+ IRTemp lmd_07_mask = newTemp( Ity_I32 );
+ IRTemp lmd_8_mask = newTemp( Ity_I32 );
+ IRTemp lmd_9_mask = newTemp( Ity_I32 );
+ IRTemp lmexp_00_mask = newTemp( Ity_I32 );
+ IRTemp lmexp_01_mask = newTemp( Ity_I32 );
+ IRTemp lmexp_10_mask = newTemp( Ity_I32 );
+ IRTemp lmd_07_val = newTemp( Ity_I32 );
+ IRTemp lmd_8_val = newTemp( Ity_I32 );
+ IRTemp lmd_9_val = newTemp( Ity_I32 );
+
+ /* The encodig is as follows:
+ * lmd - left most digit
+ * lme - left most 2-bits of the exponent
+ *
+ * lmd
+ * 0 - 7 (lmexp << 3) | lmd
+ * 8 0b11000 (24 decimal) if lme=0b00;
+ * 0b11010 (26 decimal) if lme=0b01;
+ * 0b11100 (28 decimal) if lme=0b10;
+ * 9 0b11001 (25 decimal) if lme=0b00;
+ * 0b11011 (27 decimal) if lme=0b01;
+ * 0b11101 (29 decimal) if lme=0b10;
+ */
+
+ /* Generate the masks for each condition */
+ assign( lmd_07_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpLE32U, lmd32, mkU32( 7 ) ) ) );
+ assign( lmd_8_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmd32, mkU32( 8 ) ) ) );
+ assign( lmd_9_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmd32, mkU32( 9 ) ) ) );
+ assign( lmexp_00_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmexp, mkU32( 0 ) ) ) );
+ assign( lmexp_01_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmexp, mkU32( 1 ) ) ) );
+ assign( lmexp_10_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32, lmexp, mkU32( 2 ) ) ) );
+
+ /* Generate the values for each LMD condition, assuming the condition
+ * is TRUE.
+ */
+ assign( lmd_07_val,
+ binop( Iop_Or32, binop( Iop_Shl32, lmexp, mkU8( 3 ) ), lmd32 ) );
+ assign( lmd_8_val,
+ binop( Iop_Or32,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( lmexp_00_mask ),
+ mkU32( 24 ) ),
+ binop( Iop_And32,
+ mkexpr( lmexp_01_mask ),
+ mkU32( 26 ) ) ),
+ binop( Iop_And32, mkexpr( lmexp_10_mask ), mkU32( 28 ) ) ) );
+ assign( lmd_9_val,
+ binop( Iop_Or32,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( lmexp_00_mask ),
+ mkU32( 25 ) ),
+ binop( Iop_And32,
+ mkexpr( lmexp_01_mask ),
+ mkU32( 27 ) ) ),
+ binop( Iop_And32, mkexpr( lmexp_10_mask ), mkU32( 29 ) ) ) );
+
+ /* generate the result from the possible LMD values */
+ return binop( Iop_Or32,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( lmd_07_mask ),
+ mkexpr( lmd_07_val ) ),
+ binop( Iop_And32,
+ mkexpr( lmd_8_mask ),
+ mkexpr( lmd_8_val ) ) ),
+ binop( Iop_And32, mkexpr( lmd_9_mask ), mkexpr( lmd_9_val ) ) );
+}
+
+static void Get_lmd( IRTemp * lmd, IRExpr * gfield_0_4 )
+{
+ /* Extract the exponent and the left most digit of the mantissa
+ * from the G field bits [0:4].
+ */
+ IRTemp lmd_07_mask = newTemp( Ity_I32 );
+ IRTemp lmd_8_00_mask = newTemp( Ity_I32 );
+ IRTemp lmd_8_01_mask = newTemp( Ity_I32 );
+ IRTemp lmd_8_10_mask = newTemp( Ity_I32 );
+ IRTemp lmd_9_00_mask = newTemp( Ity_I32 );
+ IRTemp lmd_9_01_mask = newTemp( Ity_I32 );
+ IRTemp lmd_9_10_mask = newTemp( Ity_I32 );
+
+ IRTemp lmd_07_val = newTemp( Ity_I32 );
+ IRTemp lmd_8_val = newTemp( Ity_I32 );
+ IRTemp lmd_9_val = newTemp( Ity_I32 );
+
+ /* The left most digit (LMD) encoding is as follows:
+ * lmd
+ * 0 - 7 (lmexp << 3) | lmd
+ * 8 0b11000 (24 decimal) if lme=0b00;
+ * 0b11010 (26 decimal) if lme=0b01;
+ * 0b11100 (28 decimal) if lme=0b10
+ * 9 0b11001 (25 decimal) if lme=0b00;
+ * 0b11011 (27 decimal) if lme=0b01;
+ * 0b11101 (29 decimal) if lme=0b10;
+ */
+
+ /* Generate the masks for each condition of LMD and exponent bits */
+ assign( lmd_07_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpLE32U,
+ gfield_0_4,
+ mkU32( BITS5(1,0,1,1,1) ) ) ) );
+ assign( lmd_8_00_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32,
+ gfield_0_4,
+ mkU32( BITS5(1,1,0,0,0) ) ) ) );
+ assign( lmd_8_01_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32,
+ gfield_0_4,
+ mkU32( BITS5(1,1,0,1,0) ) ) ) );
+ assign( lmd_8_10_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32,
+ gfield_0_4,
+ mkU32( BITS5(1,1,1,0,0) ) ) ) );
+ assign( lmd_9_00_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32,
+ gfield_0_4,
+ mkU32( BITS5(1,1,0,0,1) ) ) ) );
+ assign( lmd_9_01_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32,
+ gfield_0_4,
+ mkU32( BITS5(1,1,0,1,1) ) ) ) );
+ assign( lmd_9_10_mask,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32,
+ gfield_0_4,
+ mkU32( BITS5(1,1,1,0,1) ) ) ) );
+
+ /* Generate the values for each LMD condition, assuming the condition
+ * is TRUE.
+ */
+ assign( lmd_07_val, binop( Iop_And32, gfield_0_4, mkU32( 0x7 ) ) );
+ assign( lmd_8_val, mkU32( 0x8 ) );
+ assign( lmd_9_val, mkU32( 0x9 ) );
+
+ assign( *lmd,
+ OR( OR3 ( AND( mkexpr( lmd_07_mask ), mkexpr( lmd_07_val ) ),
+ AND( mkexpr( lmd_8_00_mask ), mkexpr( lmd_8_val ) ),
+ AND( mkexpr( lmd_8_01_mask ), mkexpr( lmd_8_val ) )),
+ OR4( AND( mkexpr( lmd_8_10_mask ), mkexpr( lmd_8_val ) ),
+ AND( mkexpr( lmd_9_00_mask ), mkexpr( lmd_9_val ) ),
+ AND( mkexpr( lmd_9_01_mask ), mkexpr( lmd_9_val ) ),
+ AND( mkexpr( lmd_9_10_mask ), mkexpr( lmd_9_val ) )
+ ) ) );
+}
+
+#define DIGIT1_SHR 4 // shift digit 1 to bottom 4 bits
+#define DIGIT2_SHR 8 // shift digit 2 to bottom 4 bits
+#define DIGIT3_SHR 12
+#define DIGIT4_SHR 16
+#define DIGIT5_SHR 20
+#define DIGIT6_SHR 24
+#define DIGIT7_SHR 28
+
+static IRExpr * bcd_digit_inval( IRExpr * bcd_u, IRExpr * bcd_l )
+{
+ /* 60-bit BCD string stored in two 32-bit values. Check that each,
+ * digit is a valid BCD number, i.e. less then 9.
+ */
+ IRTemp valid = newTemp( Ity_I32 );
+
+ assign( valid,
+ AND4( AND4 ( unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ bcd_l,
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_l,
+ mkU8 ( DIGIT1_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_l,
+ mkU8 ( DIGIT2_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_l,
+ mkU8 ( DIGIT3_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ) ),
+ AND4 ( unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_l,
+ mkU8 ( DIGIT4_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_l,
+ mkU8 ( DIGIT5_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_l,
+ mkU8 ( DIGIT6_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_l,
+ mkU8 ( DIGIT7_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ) ),
+ AND4( unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ bcd_u,
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_u,
+ mkU8 ( DIGIT1_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_u,
+ mkU8 ( DIGIT2_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_u,
+ mkU8 ( DIGIT3_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ) ),
+ AND4( unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_u,
+ mkU8 ( DIGIT4_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_u,
+ mkU8 ( DIGIT5_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_u,
+ mkU8 ( DIGIT6_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLE32U,
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ bcd_u,
+ mkU8 ( DIGIT7_SHR ) ),
+ mkU32 ( 0xF ) ),
+ mkU32( 0x9 ) ) ) ) ) );
+
+ return unop( Iop_Not32, mkexpr( valid ) );
+}
+#undef DIGIT1_SHR
+#undef DIGIT2_SHR
+#undef DIGIT3_SHR
+#undef DIGIT4_SHR
+#undef DIGIT5_SHR
+#undef DIGIT6_SHR
+#undef DIGIT7_SHR
+
+static IRExpr * Generate_neg_sign_mask( IRExpr * sign )
+{
+ return binop( Iop_Or32,
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32, sign, mkU32( 0xB ) ) ),
+ unop( Iop_1Sto32, binop( Iop_CmpEQ32, sign, mkU32( 0xD ) ) )
+ );
+}
+
+static IRExpr * Generate_pos_sign_mask( IRExpr * sign )
+{
+ return binop( Iop_Or32,
+ binop( Iop_Or32,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32, sign, mkU32( 0xA ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32, sign, mkU32( 0xC ) ) ) ),
+ binop( Iop_Or32,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32, sign, mkU32( 0xE ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32, sign, mkU32( 0xF ) ) ) ) );
+}
+
+static IRExpr * Generate_sign_bit( IRExpr * pos_sign_mask,
+ IRExpr * neg_sign_mask )
+{
+ return binop( Iop_Or32,
+ binop( Iop_And32, neg_sign_mask, mkU32( 0x80000000 ) ),
+ binop( Iop_And32, pos_sign_mask, mkU32( 0x00000000 ) ) );
+}
+
+static IRExpr * Generate_inv_mask( IRExpr * invalid_bcd_mask,
+ IRExpr * pos_sign_mask,
+ IRExpr * neg_sign_mask )
+/* first argument is all 1's if the BCD string had an invalid digit in it. */
+{
+ return binop( Iop_Or32,
+ invalid_bcd_mask,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ binop( Iop_Or32, pos_sign_mask, neg_sign_mask ),
+ mkU32( 0x0 ) ) ) );
+}
+
+static void Generate_132_bit_bcd_string( IRExpr * frBI64_hi, IRExpr * frBI64_lo,
+ IRTemp * top_12_l, IRTemp * mid_60_u,
+ IRTemp * mid_60_l, IRTemp * low_60_u,
+ IRTemp * low_60_l)
+{
+ IRTemp tmplow60 = newTemp( Ity_I64 );
+ IRTemp tmpmid60 = newTemp( Ity_I64 );
+ IRTemp tmptop12 = newTemp( Ity_I64 );
+ IRTemp low_50 = newTemp( Ity_I64 );
+ IRTemp mid_50 = newTemp( Ity_I64 );
+ IRTemp top_10 = newTemp( Ity_I64 );
+ IRTemp top_12_u = newTemp( Ity_I32 ); // only needed for a dummy arg
+
+ /* Convert the 110-bit densely packed BCD string to a 128-bit BCD string */
+
+ /* low_50[49:0] = ((frBI64_lo[49:32] << 14) | frBI64_lo[31:0]) */
+ assign( low_50,
+ binop( Iop_32HLto64,
+ binop( Iop_And32,
+ unop( Iop_64HIto32, frBI64_lo ),
+ mkU32( 0x3FFFF ) ),
+ unop( Iop_64to32, frBI64_lo ) ) );
+
+ /* Convert the 50 bit densely packed BCD string to a 60 bit
+ * BCD string.
+ */
+ assign( tmplow60, unop( Iop_DPBtoBCD, mkexpr( low_50 ) ) );
+ assign( *low_60_u, unop( Iop_64HIto32, mkexpr( tmplow60 ) ) );
+ assign( *low_60_l, unop( Iop_64to32, mkexpr( tmplow60 ) ) );
+
+ /* mid_50[49:0] = ((frBI64_hi[35:32] << 14) | frBI64_hi[31:18]) |
+ * ((frBI64_hi[17:0] << 14) | frBI64_lo[63:50])
+ */
+ assign( mid_50,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ binop( Iop_And32,
+ unop( Iop_64HIto32, frBI64_hi ),
+ mkU32( 0xF ) ),
+ mkU8( 14 ) ),
+ binop( Iop_Shr32,
+ unop( Iop_64to32, frBI64_hi ),
+ mkU8( 18 ) ) ),
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ unop( Iop_64to32, frBI64_hi ),
+ mkU8( 14 ) ),
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, frBI64_lo ),
+ mkU8( 18 ) ) ) ) );
+
+ /* Convert the 50 bit densely packed BCD string to a 60 bit
+ * BCD string.
+ */
+ assign( tmpmid60, unop( Iop_DPBtoBCD, mkexpr( mid_50 ) ) );
+ assign( *mid_60_u, unop( Iop_64HIto32, mkexpr( tmpmid60 ) ) );
+ assign( *mid_60_l, unop( Iop_64to32, mkexpr( tmpmid60 ) ) );
+
+ /* top_10[49:0] = frBI64_hi[45:36]) | */
+ assign( top_10,
+ binop( Iop_32HLto64,
+ mkU32( 0 ),
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, frBI64_hi ),
+ mkU8( 4 ) ),
+ mkU32( 0x3FF ) ) ) );
+
+ /* Convert the 10 bit densely packed BCD string to a 12 bit
+ * BCD string.
+ */
+ assign( tmptop12, unop( Iop_DPBtoBCD, mkexpr( top_10 ) ) );
+ assign( top_12_u, unop( Iop_64HIto32, mkexpr( tmptop12 ) ) );
+ assign( *top_12_l, unop( Iop_64to32, mkexpr( tmptop12 ) ) );
+}
+
+static void Count_zeros( int start, IRExpr * init_cnt, IRExpr * init_flag,
+ IRTemp * final_cnt, IRTemp * final_flag,
+ IRExpr * string )
+{
+ IRTemp cnt[MAX_DIGITS_IN_STRING + 1];IRTemp flag[MAX_DIGITS_IN_STRING+1];
+ int digits = MAX_DIGITS_IN_STRING;
+ int i;
+
+ cnt[start-1] = newTemp( Ity_I8 );
+ flag[start-1] = newTemp( Ity_I8 );
+ assign( cnt[start-1], init_cnt);
+ assign( flag[start-1], init_flag);
+
+ for ( i = start; i <= digits; i++) {
+ cnt[i] = newTemp( Ity_I8 );
+ flag[i] = newTemp( Ity_I8 );
+ assign( cnt[i],
+ binop( Iop_Add8,
+ mkexpr( cnt[i-1] ),
+ binop(Iop_And8,
+ unop( Iop_1Uto8,
+ binop(Iop_CmpEQ32,
+ binop(Iop_And32,
+ string,
+ mkU32( 0xF <<
+ ( ( digits - i ) * 4) ) ),
+ mkU32( 0 ) ) ),
+ binop( Iop_Xor8, /* complement flag */
+ mkexpr( flag[i - 1] ),
+ mkU8( 0xFF ) ) ) ) );
+
+ /* set flag to 1 if digit was not a zero */
+ assign( flag[i],
+ binop(Iop_Or8,
+ unop( Iop_1Sto8,
+ binop(Iop_CmpNE32,
+ binop(Iop_And32,
+ string,
+ mkU32( 0xF <<
+ ( (digits - i) * 4) ) ),
+ mkU32( 0 ) ) ),
+ mkexpr( flag[i - 1] ) ) );
+ }
+
+ *final_cnt = cnt[digits];
+ *final_flag = flag[digits];
+}
+
+static IRExpr * Count_leading_zeros_60( IRExpr * lmd, IRExpr * upper_28,
+ IRExpr * low_32 )
+{
+ IRTemp num_lmd = newTemp( Ity_I8 );
+ IRTemp num_upper = newTemp( Ity_I8 );
+ IRTemp num_low = newTemp( Ity_I8 );
+ IRTemp lmd_flag = newTemp( Ity_I8 );
+ IRTemp upper_flag = newTemp( Ity_I8 );
+ IRTemp low_flag = newTemp( Ity_I8 );
+
+ assign( num_lmd, unop( Iop_1Uto8, binop( Iop_CmpEQ32, lmd, mkU32( 0 ) ) ) );
+ assign( lmd_flag, unop( Iop_Not8, mkexpr( num_lmd ) ) );
+
+ Count_zeros( 2,
+ mkexpr( num_lmd ),
+ mkexpr( lmd_flag ),
+ &num_upper,
+ &upper_flag,
+ upper_28 );
+
+ Count_zeros( 1,
+ mkexpr( num_upper ),
+ mkexpr( upper_flag ),
+ &num_low,
+ &low_flag,
+ low_32 );
+
+ return mkexpr( num_low );
+}
+
+static IRExpr * Count_leading_zeros_128( IRExpr * lmd, IRExpr * top_12_l,
+ IRExpr * mid_60_u, IRExpr * mid_60_l,
+ IRExpr * low_60_u, IRExpr * low_60_l)
+{
+ IRTemp num_lmd = newTemp( Ity_I8 );
+ IRTemp num_top = newTemp( Ity_I8 );
+ IRTemp num_mid_u = newTemp( Ity_I8 );
+ IRTemp num_mid_l = newTemp( Ity_I8 );
+ IRTemp num_low_u = newTemp( Ity_I8 );
+ IRTemp num_low_l = newTemp( Ity_I8 );
+
+ IRTemp lmd_flag = newTemp( Ity_I8 );
+ IRTemp top_flag = newTemp( Ity_I8 );
+ IRTemp mid_u_flag = newTemp( Ity_I8 );
+ IRTemp mid_l_flag = newTemp( Ity_I8 );
+ IRTemp low_u_flag = newTemp( Ity_I8 );
+ IRTemp low_l_flag = newTemp( Ity_I8 );
+
+ /* Check the LMD, digit 16, to see if it is zero. */
+ assign( num_lmd, unop( Iop_1Uto8, binop( Iop_CmpEQ32, lmd, mkU32( 0 ) ) ) );
+
+ assign( lmd_flag, unop( Iop_Not8, mkexpr( num_lmd ) ) );
+
+ Count_zeros( 6,
+ mkexpr( num_lmd ),
+ mkexpr( lmd_flag ),
+ &num_top,
+ &top_flag,
+ top_12_l );
+
+ Count_zeros( 1,
+ mkexpr( num_top ),
+ mkexpr( top_flag ),
+ &num_mid_u,
+ &mid_u_flag,
+ binop( Iop_Or32,
+ binop( Iop_Shl32, mid_60_u, mkU8( 2 ) ),
+ binop( Iop_Shr32, mid_60_l, mkU8( 30 ) ) ) );
+
+ Count_zeros( 2,
+ mkexpr( num_mid_u ),
+ mkexpr( mid_u_flag ),
+ &num_mid_l,
+ &mid_l_flag,
+ mid_60_l );
+
+ Count_zeros( 1,
+ mkexpr( num_mid_l ),
+ mkexpr( mid_l_flag ),
+ &num_low_u,
+ &low_u_flag,
+ binop( Iop_Or32,
+ binop( Iop_Shl32, low_60_u, mkU8( 2 ) ),
+ binop( Iop_Shr32, low_60_l, mkU8( 30 ) ) ) );
+
+ Count_zeros( 2,
+ mkexpr( num_low_u ),
+ mkexpr( low_u_flag ),
+ &num_low_l,
+ &low_l_flag,
+ low_60_l );
+
+ return mkexpr( num_low_l );
+}
+
+static IRExpr * Check_unordered(IRExpr * val)
+{
+ IRTemp gfield0to5 = newTemp( Ity_I32 );
+
+ /* Extract G[0:4] */
+ assign( gfield0to5,
+ binop( Iop_And32,
+ binop( Iop_Shr32, unop( Iop_64HIto32, val ), mkU8( 26 ) ),
+ mkU32( 0x1F ) ) );
+
+ /* Check for unordered, return all 1'x if true */
+ return binop( Iop_Or32, /* QNaN check */
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( gfield0to5 ),
+ mkU32( 0x1E ) ) ),
+ unop( Iop_1Sto32, /* SNaN check */
+ binop( Iop_CmpEQ32,
+ mkexpr( gfield0to5 ),
+ mkU32( 0x1F ) ) ) );
+}
+
+#undef AND
+#undef AND4
+#undef OR
+#undef OR3
+#undef OR4
+#undef NOT
+#undef SHR
+#undef SHL
+#undef BITS5
+
+/*------------------------------------------------------------*/
+/*--- Decimal Floating Point (DFP) instruction translation ---*/
+/*------------------------------------------------------------*/
+
+/* DFP Arithmetic instructions */
+static Bool dis_dfp_arith(UInt theInstr)
+{
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar flag_rC = ifieldBIT0( theInstr );
+
+ IRTemp frA = newTemp( Ity_D64 );
+ IRTemp frB = newTemp( Ity_D64 );
+ IRTemp frS = newTemp( Ity_D64 );
+ IRExpr* round = get_IR_roundingmode_DFP();
+
+ /* By default, if flag_RC is set, we will clear cr1 after the
+ * operation. In reality we should set cr1 to indicate the
+ * exception status of the operation, but since we're not
+ * simulating exceptions, the exception status will appear to be
+ * zero. Hence cr1 should be cleared if this is a . form insn.
+ */
+ Bool clear_CR1 = True;
+
+ assign( frA, getDReg( frA_addr ) );
+ assign( frB, getDReg( frB_addr ) );
+
+ switch (opc2) {
+ case 0x2: // dadd
+ DIP( "dadd%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, triop( Iop_AddD64, round, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ case 0x202: // dsub
+ DIP( "dsub%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, triop( Iop_SubD64, round, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ case 0x22: // dmul
+ DIP( "dmul%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, triop( Iop_MulD64, round, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ case 0x222: // ddiv
+ DIP( "ddiv%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, triop( Iop_DivD64, round, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ }
+
+ putDReg( frS_addr, mkexpr( frS ) );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+/* Quad DFP Arithmetic instructions */
+static Bool dis_dfp_arithq(UInt theInstr)
+{
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar flag_rC = ifieldBIT0( theInstr );
+
+ IRTemp frA = newTemp( Ity_D128 );
+ IRTemp frB = newTemp( Ity_D128 );
+ IRTemp frS = newTemp( Ity_D128 );
+ IRExpr* round = get_IR_roundingmode_DFP();
+
+ /* By default, if flag_RC is set, we will clear cr1 after the
+ * operation. In reality we should set cr1 to indicate the
+ * exception status of the operation, but since we're not
+ * simulating exceptions, the exception status will appear to be
+ * zero. Hence cr1 should be cleared if this is a . form insn.
+ */
+ Bool clear_CR1 = True;
+
+ assign( frA, getDReg_pair( frA_addr ) );
+ assign( frB, getDReg_pair( frB_addr ) );
+
+ switch (opc2) {
+ case 0x2: // daddq
+ DIP( "daddq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, triop( Iop_AddD128, round, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ case 0x202: // dsubq
+ DIP( "dsubq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, triop( Iop_SubD128, round, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ case 0x22: // dmulq
+ DIP( "dmulq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, triop( Iop_MulD128, round, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ case 0x222: // ddivq
+ DIP( "ddivq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, triop( Iop_DivD128, round, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ }
+
+ putDReg_pair( frS_addr, mkexpr( frS ) );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+/* DFP 64-bit logical shift instructions */
+static Bool dis_dfp_shift(UInt theInstr) {
+ UInt opc2 = ifieldOPClo9( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar shift_val = IFIELD(theInstr, 10, 6);
+ UChar flag_rC = ifieldBIT0( theInstr );
+
+ IRTemp frA = newTemp( Ity_D64 );
+ IRTemp frS = newTemp( Ity_D64 );
+ Bool clear_CR1 = True;
+
+ assign( frA, getDReg( frA_addr ) );
+
+ switch (opc2) {
+ case 0x42: // dscli
+ DIP( "dscli%s fr%u,fr%u,%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, shift_val );
+ assign( frS, binop( Iop_ShlD64, mkexpr( frA ), mkU8( shift_val ) ) );
+ break;
+ case 0x62: // dscri
+ DIP( "dscri%s fr%u,fr%u,%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, shift_val );
+ assign( frS, binop( Iop_ShrD64, mkexpr( frA ), mkU8( shift_val ) ) );
+ break;
+ }
+
+ putDReg( frS_addr, mkexpr( frS ) );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+/* Quad DFP logical shift instructions */
+static Bool dis_dfp_shiftq(UInt theInstr) {
+ UInt opc2 = ifieldOPClo9( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar shift_val = IFIELD(theInstr, 10, 6);
+ UChar flag_rC = ifieldBIT0( theInstr );
+
+ IRTemp frA = newTemp( Ity_D128 );
+ IRTemp frS = newTemp( Ity_D128 );
+ Bool clear_CR1 = True;
+
+ assign( frA, getDReg_pair( frA_addr ) );
+
+ switch (opc2) {
+ case 0x42: // dscliq
+ DIP( "dscliq%s fr%u,fr%u,%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, shift_val );
+ assign( frS, binop( Iop_ShlD128, mkexpr( frA ), mkU8( shift_val ) ) );
+ break;
+ case 0x62: // dscriq
+ DIP( "dscriq%s fr%u,fr%u,%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, shift_val );
+ assign( frS, binop( Iop_ShrD128, mkexpr( frA ), mkU8( shift_val ) ) );
+ break;
+ }
+
+ putDReg_pair( frS_addr, mkexpr( frS ) );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+/* DFP 64-bit format conversion instructions */
+static Bool dis_dfp_fmt_conv(UInt theInstr) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ IRExpr* round = get_IR_roundingmode_DFP();
+ UChar flag_rC = ifieldBIT0( theInstr );
+ IRTemp frB;
+ IRTemp frS;
+ Bool clear_CR1 = True;
+
+ switch (opc2) {
+ case 0x102: //dctdp
+ DIP( "dctdp%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+
+ frB = newTemp( Ity_D64 );
+ frS = newTemp( Ity_D64 );
+ assign( frB, getDReg( frB_addr ) );
+ assign( frS, unop( Iop_D32toD64, mkexpr( frB ) ) );
+ putDReg( frS_addr, mkexpr( frS ) );
+ break;
+ case 0x302: // drsp
+ DIP( "drsp%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ frB = newTemp( Ity_D64 );
+ frS = newTemp( Ity_D64 );
+ assign( frB, getDReg( frB_addr ) );
+ assign( frS, binop( Iop_D64toD32, round, mkexpr( frB ) ) );
+ putDReg( frS_addr, mkexpr( frS ) );
+ break;
+ case 0x122: // dctfix
+ DIP( "dctfix%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ frB = newTemp( Ity_D64 );
+ frS = newTemp( Ity_D64 );
+ assign( frB, getDReg( frB_addr ) );
+ assign( frS, binop( Iop_D64toI64S, round, mkexpr( frB ) ) );
+ putDReg( frS_addr, mkexpr( frS ) );
+ break;
+ case 0x322: // dcffix
+ DIP( "dcffix%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ frB = newTemp( Ity_D64 );
+ frS = newTemp( Ity_D64 );
+ assign( frB, getDReg( frB_addr ) );
+ assign( frS, binop( Iop_I64StoD64, round, mkexpr( frB ) ) );
+ putDReg( frS_addr, mkexpr( frS ) );
+ break;
+ }
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+/* Quad DFP format conversion instructions */
+static Bool dis_dfp_fmt_convq(UInt theInstr) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ IRExpr* round = get_IR_roundingmode_DFP();
+ IRTemp frB64 = newTemp( Ity_D64 );
+ IRTemp frB128 = newTemp( Ity_D128 );
+ IRTemp frS64 = newTemp( Ity_D64 );
+ IRTemp frS128 = newTemp( Ity_D128 );
+ UChar flag_rC = ifieldBIT0( theInstr );
+ Bool clear_CR1 = True;
+
+ switch (opc2) {
+ case 0x102: // dctqpq
+ DIP( "dctqpq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ assign( frB64, getDReg( frB_addr ) );
+ assign( frS128, unop( Iop_D64toD128, mkexpr( frB64 ) ) );
+ putDReg_pair( frS_addr, mkexpr( frS128 ) );
+ break;
+ case 0x122: // dctfixq
+ DIP( "dctfixq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ assign( frB128, getDReg_pair( frB_addr ) );
+ assign( frS64, binop( Iop_D128toI64S, round, mkexpr( frB128 ) ) );
+ putDReg( frS_addr, mkexpr( frS64 ) );
+ break;
+ case 0x302: //drdpq
+ DIP( "drdpq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ assign( frB128, getDReg_pair( frB_addr ) );
+ assign( frS64, binop( Iop_D128toD64, round, mkexpr( frB128 ) ) );
+ putDReg( frS_addr, mkexpr( frS64 ) );
+ break;
+ case 0x322: // dcffixq
+ /* Have to introduce an IOP for this instruction so it will work
+ * on POWER 6 because emulating the instruction requires a POWER 7
+ * DFP instruction in the emulation code.
+ */
+ DIP( "dcffixq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ assign( frB64, getDReg( frB_addr ) );
+ assign( frS128, unop( Iop_I64StoD128, mkexpr( frB64 ) ) );
+ putDReg_pair( frS_addr, mkexpr( frS128 ) );
+ break;
+ }
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+static Bool dis_dfp_round( UInt theInstr ) {
+ UChar frS_addr = ifieldRegDS(theInstr);
+ UChar R = IFIELD(theInstr, 16, 1);
+ UChar RMC = IFIELD(theInstr, 9, 2);
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar flag_rC = ifieldBIT0( theInstr );
+ IRTemp frB = newTemp( Ity_D64 );
+ IRTemp frS = newTemp( Ity_D64 );
+ UInt opc2 = ifieldOPClo8( theInstr );
+ Bool clear_CR1 = True;
+
+ switch (opc2) {
+ /* drintn, is the same as drintx. The only difference is this
+ * instruction does not generate an exception for an inexact operation.
+ * Currently not supporting inexact exceptions.
+ */
+ case 0x63: // drintx
+ case 0xE3: // drintn
+ DIP( "drintx/drintn%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+
+ /* pass the value of R and RMC in the same field */
+ assign( frB, getDReg( frB_addr ) );
+ assign( frS, binop( Iop_RoundD64toInt,
+ mkU32( ( R << 3 ) | RMC ),
+ mkexpr( frB ) ) );
+ putDReg( frS_addr, mkexpr( frS ) );
+ break;
+ default:
+ vex_printf("dis_dfp_round(ppc)(opc2)\n");
+ return False;
+ }
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+static Bool dis_dfp_roundq(UInt theInstr) {
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar R = IFIELD(theInstr, 16, 1);
+ UChar RMC = IFIELD(theInstr, 9, 2);
+ UChar flag_rC = ifieldBIT0( theInstr );
+ IRTemp frB = newTemp( Ity_D128 );
+ IRTemp frS = newTemp( Ity_D128 );
+ Bool clear_CR1 = True;
+ UInt opc2 = ifieldOPClo8( theInstr );
+
+ switch (opc2) {
+ /* drintnq, is the same as drintxq. The only difference is this
+ * instruction does not generate an exception for an inexact operation.
+ * Currently not supporting inexact exceptions.
+ */
+ case 0x63: // drintxq
+ case 0xE3: // drintnq
+ DIP( "drintxq/drintnq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+
+ /* pass the value of R and RMC in the same field */
+ assign( frB, getDReg_pair( frB_addr ) );
+ assign( frS, binop( Iop_RoundD128toInt,
+ mkU32( ( R << 3 ) | RMC ),
+ mkexpr( frB ) ) );
+ putDReg_pair( frS_addr, mkexpr( frS ) );
+ break;
+ default:
+ vex_printf("dis_dfp_roundq(ppc)(opc2)\n");
+ return False;
+ }
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+static Bool dis_dfp_quantize_sig_rrnd(UInt theInstr) {
+ UInt opc2 = ifieldOPClo8( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar flag_rC = ifieldBIT0( theInstr );
+ UInt TE_value = IFIELD(theInstr, 16, 4);
+ UInt TE_sign = IFIELD(theInstr, 20, 1);
+ UInt RMC = IFIELD(theInstr, 9, 2);
+ IRTemp frA = newTemp( Ity_D64 );
+ IRTemp frB = newTemp( Ity_D64 );
+ IRTemp frS = newTemp( Ity_D64 );
+ Bool clear_CR1 = True;
+
+ assign( frB, getDReg( frB_addr ) );
+
+ switch (opc2) {
+ case 0x43: // dquai
+ DIP( "dquai%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ IRTemp TE_D64 = newTemp( Ity_D64 );
+
+ /* Generate a reference DFP value frA with the desired exponent
+ * given by TE using significand from frB. Need to add the bias
+ * 398 to TE. TE is stored as a 2's complement number.
+ */
+ if (TE_sign == 1) {
+ /* Take 2's complement of the 5-bit value and subtract from bias.
+ * Bias is adjusted for the +1 required when taking 2's complement.
+ */
+ assign( TE_D64,
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_Sub64, mkU64( 397 ),
+ binop( Iop_And64, mkU64( 0xF ),
+ unop( Iop_Not64, mkU64( TE_value ) )
+ ) ) ) );
+
+ } else {
+ assign( TE_D64,
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_Add64, mkU64( 398 ), mkU64( TE_value ) ) ) );
+ }
+
+ assign( frA, binop( Iop_InsertExpD64, mkexpr( TE_D64 ),
+ unop( Iop_ReinterpI64asD64, mkU64( 1 ) ) ) );
+
+ assign( frS, triop( Iop_QuantizeD64,
+ mkU32( RMC ),
+ mkexpr( frA ),
+ mkexpr( frB ) ) );
+ break;
+
+ case 0x3: // dqua
+ DIP( "dqua%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frA, getDReg( frA_addr ) );
+ assign( frS, triop( Iop_QuantizeD64,
+ mkU32( RMC ),
+ mkexpr( frA ),
+ mkexpr( frB ) ) );
+ break;
+ case 0x23: // drrnd
+ DIP( "drrnd%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frA, getDReg( frA_addr ) );
+ assign( frS, triop( Iop_SignificanceRoundD64,
+ mkU32( RMC ),
+ mkexpr( frA ),
+ mkexpr( frB ) ) );
+ break;
+ default:
+ vex_printf("dis_dfp_quantize_sig_rrnd(ppc)(opc2)\n");
+ return False;
+ }
+ putDReg( frS_addr, mkexpr( frS ) );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+static Bool dis_dfp_quantize_sig_rrndq(UInt theInstr) {
+ UInt opc2 = ifieldOPClo8( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar flag_rC = ifieldBIT0( theInstr );
+ UInt TE_value = IFIELD(theInstr, 16, 4);
+ UInt TE_sign = IFIELD(theInstr, 20, 1);
+ UInt RMC = IFIELD(theInstr, 9, 2);
+ IRTemp frA = newTemp( Ity_D128 );
+ IRTemp frB = newTemp( Ity_D128 );
+ IRTemp frS = newTemp( Ity_D128 );
+ Bool clear_CR1 = True;
+
+ assign( frB, getDReg_pair( frB_addr ) );
+
+ switch (opc2) {
+ case 0x43: // dquaiq
+ DIP( "dquaiq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ IRTemp TE_D64 = newTemp( Ity_D64 );
+
+ /* Generate a reference DFP value frA with the desired exponent
+ * given by TE using significand of 1. Need to add the bias
+ * 6176 to TE.
+ */
+ if (TE_sign == 1) {
+ /* Take 2's complement of the 5-bit value and subtract from bias.
+ * Bias adjusted for the +1 required when taking 2's complement.
+ */
+ assign( TE_D64,
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_Sub64, mkU64( 6175 ),
+ binop( Iop_And64, mkU64( 0xF ),
+ unop( Iop_Not64, mkU64( TE_value ) )
+ ) ) ) );
+
+ } else {
+ assign( TE_D64,
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_Add64, mkU64( 6176 ), mkU64( TE_value ) )
+ ) );
+ }
+
+ assign( frA,
+ binop( Iop_InsertExpD128, mkexpr( TE_D64 ),
+ unop( Iop_D64toD128,
+ unop( Iop_ReinterpI64asD64, mkU64( 1 ) ) ) ) );
+ assign( frS, triop( Iop_QuantizeD128,
+ mkU32( RMC ),
+ mkexpr( frA ),
+ mkexpr( frB ) ) );
+ break;
+ case 0x3: // dquaq
+ DIP( "dquaiq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frA, getDReg_pair( frA_addr ) );
+ assign( frS, triop( Iop_QuantizeD128,
+ mkU32( RMC ),
+ mkexpr( frA ),
+ mkexpr( frB ) ) );
+ break;
+ case 0x23: // drrndq
+ DIP( "drrndq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frA, getDReg_pair( frA_addr ) );
+ assign( frS, triop( Iop_SignificanceRoundD128,
+ mkU32( RMC ),
+ mkexpr( frA ),
+ mkexpr( frB ) ) );
+ break;
+ default:
+ vex_printf("dis_dfp_quantize_sig_rrndq(ppc)(opc2)\n");
+ return False;
+ }
+ putDReg_pair( frS_addr, mkexpr( frS ) );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+static Bool dis_dfp_extract_insert(UInt theInstr) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar flag_rC = ifieldBIT0( theInstr );
+ Bool clear_CR1 = True;
+
+ IRTemp frA = newTemp( Ity_D64 );
+ IRTemp frB = newTemp( Ity_D64 );
+ IRTemp frS = newTemp( Ity_D64 );
+
+ assign( frA, getDReg( frA_addr ) );
+ assign( frB, getDReg( frB_addr ) );
+
+ switch (opc2) {
+ case 0x162: // dxex
+ DIP( "dxex%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, unop( Iop_ExtractExpD64, mkexpr( frB ) ) );
+ break;
+ case 0x362: // diex
+ DIP( "diex%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frS, binop( Iop_InsertExpD64, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ default:
+ vex_printf("dis_dfp_extract_insert(ppc)(opc2)\n");
+ return False;
+ }
+
+ putDReg( frS_addr, mkexpr( frS ) );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+static Bool dis_dfp_extract_insertq(UInt theInstr) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar flag_rC = ifieldBIT0( theInstr );
+
+ IRTemp frA = newTemp( Ity_D64 );
+ IRTemp frB = newTemp( Ity_D128 );
+ IRTemp frS64 = newTemp( Ity_D64 );
+ IRTemp frS = newTemp( Ity_D128 );
+ Bool clear_CR1 = True;
+
+ assign( frB, getDReg_pair( frB_addr ) );
+
+ switch (opc2) {
+ case 0x162: // dxexq
+ DIP( "dxexq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ /* Instruction actually returns a 64-bit result. So as to be
+ * consistent and not have to add a new struct, the emulation returns
+ * the 64-bit result in the upper and lower register.
+ */
+ assign( frS64, unop( Iop_ExtractExpD128, mkexpr( frB ) ) );
+ putDReg( frS_addr, mkexpr( frS64 ) );
+ break;
+ case 0x362: // diexq
+ DIP( "diexq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+ assign( frA, getDReg( frA_addr ) );
+ assign( frS, binop( Iop_InsertExpD128, mkexpr( frA ), mkexpr( frB ) ) );
+ putDReg_pair( frS_addr, mkexpr( frS ) );
+ break;
+ default:
+ vex_printf("dis_dfp_extract_insertq(ppc)(opc2)\n");
+ return False;
+ }
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+ putCR0( 1, mkU8( 0 ) );
+ }
+
+ return True;
+}
+
+/* DFP 64-bit comparison instructions */
+static Bool dis_dfp_compare(UInt theInstr) {
+ /* X-Form */
+ UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); // AKA BF
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UInt opc1 = ifieldOPC( theInstr );
+ IRTemp frA;
+ IRTemp frB;
+
+ IRTemp ccIR = newTemp( Ity_I32 );
+ IRTemp ccPPC32 = newTemp( Ity_I32 );
+
+
+ /* Note: Differences between dcmpu and dcmpo are only in exception
+ flag settings, which aren't supported anyway. */
+ switch (opc1) {
+ case 0x3B: /* dcmpo and dcmpu, DFP 64-bit */
+ DIP( "dcmpo %u,fr%u,fr%u\n", crfD, frA_addr, frB_addr );
+ frA = newTemp( Ity_D64 );
+ frB = newTemp( Ity_D64 );
+
+ assign( frA, getDReg( frA_addr ) );
+ assign( frB, getDReg( frB_addr ) );
+
+ assign( ccIR, binop( Iop_CmpD64, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ case 0x3F: /* dcmpoq and dcmpuq,DFP 128-bit */
+ DIP( "dcmpoq %u,fr%u,fr%u\n", crfD, frA_addr, frB_addr );
+ frA = newTemp( Ity_D128 );
+ frB = newTemp( Ity_D128 );
+
+ assign( frA, getDReg_pair( frA_addr ) );
+ assign( frB, getDReg_pair( frB_addr ) );
+ assign( ccIR, binop( Iop_CmpD128, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ default:
+ vex_printf("dis_dfp_compare(ppc)(opc2)\n");
+ return False;
+ }
+
+ /* Map compare result from IR to PPC32 */
+ /*
+ FP cmp result | PPC | IR
+ --------------------------
+ UN | 0x1 | 0x45
+ EQ | 0x2 | 0x40
+ GT | 0x4 | 0x00
+ LT | 0x8 | 0x01
+ */
+
+ assign( ccPPC32,
+ binop( Iop_Shl32,
+ mkU32( 1 ),
+ unop( Iop_32to8,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ unop( Iop_Not32,
+ binop( Iop_Shr32,
+ mkexpr( ccIR ),
+ mkU8( 5 ) ) ),
+ mkU32( 2 ) ),
+ binop( Iop_And32,
+ binop( Iop_Xor32,
+ mkexpr( ccIR ),
+ binop( Iop_Shr32,
+ mkexpr( ccIR ),
+ mkU8( 6 ) ) ),
+ mkU32( 1 ) ) ) ) ) );
+
+ putGST_field( PPC_GST_CR, mkexpr( ccPPC32 ), crfD );
+ return True;
+}
+
+/* Test class/group/exponent/significance instructions. */
+static Bool dis_dfp_exponent_test ( UInt theInstr )
+{
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) );
+ IRTemp frA = newTemp( Ity_D64 );
+ IRTemp frB = newTemp( Ity_D64 );
+ IRTemp frA128 = newTemp( Ity_D128 );
+ IRTemp frB128 = newTemp( Ity_D128 );
+ UInt opc1 = ifieldOPC( theInstr );
+ IRTemp gfield_A = newTemp( Ity_I32 );
+ IRTemp gfield_B = newTemp( Ity_I32 );
+ IRTemp gfield_mask = newTemp( Ity_I32 );
+ IRTemp exponent_A = newTemp( Ity_I32 );
+ IRTemp exponent_B = newTemp( Ity_I32 );
+ IRTemp A_NaN_true = newTemp( Ity_I32 );
+ IRTemp B_NaN_true = newTemp( Ity_I32 );
+ IRTemp A_inf_true = newTemp( Ity_I32 );
+ IRTemp B_inf_true = newTemp( Ity_I32 );
+ IRTemp A_equals_B = newTemp( Ity_I32 );
+ IRTemp finite_number = newTemp( Ity_I32 );
+ IRTemp cc0 = newTemp( Ity_I32 );
+ IRTemp cc1 = newTemp( Ity_I32 );
+ IRTemp cc2 = newTemp( Ity_I32 );
+ IRTemp cc3 = newTemp( Ity_I32 );
+
+ /* The dtstex and dtstexg instructions only differ in the size of the
+ * exponent field. The following switch statement takes care of the size
+ * specific setup. Once the value of the exponents, the G-field shift
+ * and mask is setup the remaining code is identical.
+ */
+ switch (opc1) {
+ case 0x3b: // dtstex Extended instruction setup
+ DIP("dtstex %u,r%u,r%d\n", crfD, frA_addr, frB_addr);
+ assign( frA, getDReg( frA_addr ) );
+ assign( frB, getDReg( frB_addr ) );
+ assign( gfield_mask, mkU32( DFP_G_FIELD_LONG_MASK ) );
+ assign(exponent_A, unop( Iop_64to32,
+ unop( Iop_ReinterpD64asI64,
+ unop( Iop_ExtractExpD64,
+ mkexpr( frA ) ) ) ) );
+ assign(exponent_B, unop( Iop_64to32,
+ unop( Iop_ReinterpD64asI64,
+ unop( Iop_ExtractExpD64,
+ mkexpr( frB ) ) ) ) );
+ break;
+
+ case 0x3F: // dtstexq Quad instruction setup
+ DIP("dtstexq %u,r%u,r%d\n", crfD, frA_addr, frB_addr);
+ assign( frA128, getDReg_pair( frA_addr ) );
+ assign( frB128, getDReg_pair( frB_addr ) );
+ assign( frA, unop( Iop_D128HItoD64, mkexpr( frA128 ) ) );
+ assign( frB, unop( Iop_D128HItoD64, mkexpr( frB128 ) ) );
+ assign( gfield_mask, mkU32( DFP_G_FIELD_EXTND_MASK ) );
+ assign( exponent_A, unop( Iop_64to32,
+ unop( Iop_ReinterpD64asI64,
+ unop( Iop_ExtractExpD128,
+ mkexpr( frA128 ) ) ) ) );
+ assign( exponent_B, unop( Iop_64to32,
+ unop( Iop_ReinterpD64asI64,
+ unop( Iop_ExtractExpD128,
+ mkexpr( frB128 ) ) ) ) );
+ break;
+ default:
+ vex_printf("dis_dfp_exponent_test(ppc)(opc2)\n");
+ return False;
+ }
+
+ /* Extract the Gfield */
+ assign( gfield_A, binop( Iop_And32,
+ mkexpr( gfield_mask ),
+ unop( Iop_64HIto32,
+ unop( Iop_ReinterpD64asI64,
+ mkexpr(frA) ) ) ) );
+
+ assign( gfield_B, binop( Iop_And32,
+ mkexpr( gfield_mask ),
+ unop( Iop_64HIto32,
+ unop( Iop_ReinterpD64asI64,
+ mkexpr(frB) ) ) ) );
+
+ /* check for NAN */
+ assign( A_NaN_true, binop(Iop_Or32,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( gfield_A ),
+ mkU32( 0x7C000000 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( gfield_A ),
+ mkU32( 0x7E000000 ) )
+ ) ) );
+ assign( B_NaN_true, binop(Iop_Or32,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( gfield_B ),
+ mkU32( 0x7C000000 ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( gfield_B ),
+ mkU32( 0x7E000000 ) )
+ ) ) );
+
+ /* check for infinity */
+ assign( A_inf_true,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( gfield_A ),
+ mkU32( 0x78000000 ) ) ) );
+
+ assign( B_inf_true,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( gfield_B ),
+ mkU32( 0x78000000 ) ) ) );
+
+ assign( finite_number,
+ unop( Iop_Not32,
+ binop( Iop_Or32,
+ binop( Iop_Or32,
+ mkexpr( A_NaN_true ),
+ mkexpr( B_NaN_true ) ),
+ binop( Iop_Or32,
+ mkexpr( A_inf_true ),
+ mkexpr( B_inf_true ) ) ) ) );
+
+ /* Calculate the condition code bits
+ * If QNaN,SNaN, +infinity, -infinity then cc0, cc1 and cc2 are zero
+ * regardless of the value of the comparisons and cc3 is 1. Otherwise,
+ * cc0, cc1 and cc0 reflect the results of the comparisons.
+ */
+ assign( A_equals_B,
+ binop( Iop_Or32,
+ unop( Iop_1Uto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( exponent_A ),
+ mkexpr( exponent_B ) ) ),
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( A_inf_true ),
+ mkexpr( B_inf_true ) ),
+ binop( Iop_And32,
+ mkexpr( A_NaN_true ),
+ mkexpr( B_NaN_true ) ) ) ) );
+
+ assign( cc0, binop( Iop_And32,
+ mkexpr( finite_number ),
+ binop( Iop_Shl32,
+ unop( Iop_1Uto32,
+ binop( Iop_CmpLT32U,
+ mkexpr( exponent_A ),
+ mkexpr( exponent_B ) ) ),
+ mkU8( 3 ) ) ) );
+
+ assign( cc1, binop( Iop_And32,
+ mkexpr( finite_number ),
+ binop( Iop_Shl32,
+ unop( Iop_1Uto32,
+ binop( Iop_CmpLT32U,
+ mkexpr( exponent_B ),
+ mkexpr( exponent_A ) ) ),
+ mkU8( 2 ) ) ) );
+
+ assign( cc2, binop( Iop_Shl32,
+ binop( Iop_And32,
+ mkexpr( A_equals_B ),
+ mkU32( 1 ) ),
+ mkU8( 1 ) ) );
+
+ assign( cc3, binop( Iop_And32,
+ unop( Iop_Not32, mkexpr( A_equals_B ) ),
+ binop( Iop_And32,
+ mkU32( 0x1 ),
+ binop( Iop_Or32,
+ binop( Iop_Or32,
+ mkexpr ( A_inf_true ),
+ mkexpr ( B_inf_true ) ),
+ binop( Iop_Or32,
+ mkexpr ( A_NaN_true ),
+ mkexpr ( B_NaN_true ) ) )
+ ) ) );
+
+ /* store the condition code */
+ putGST_field( PPC_GST_CR,
+ binop( Iop_Or32,
+ mkexpr( cc0 ),
+ binop( Iop_Or32,
+ mkexpr( cc1 ),
+ binop( Iop_Or32,
+ mkexpr( cc2 ),
+ mkexpr( cc3 ) ) ) ),
+ crfD );
+ return True;
+}
+
+/* Test class/group/exponent/significance instructions. */
+static Bool dis_dfp_class_test ( UInt theInstr )
+{
+ UChar frA_addr = ifieldRegA( theInstr );
+ IRTemp frA = newTemp( Ity_D64 );
+ IRTemp abs_frA = newTemp( Ity_D64 );
+ IRTemp frAI64_hi = newTemp( Ity_I64 );
+ IRTemp frAI64_lo = newTemp( Ity_I64 );
+ UInt opc1 = ifieldOPC( theInstr );
+ UInt opc2 = ifieldOPClo9( theInstr );
+ UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); // AKA BF
+ UInt DCM = IFIELD( theInstr, 10, 6 );
+ IRTemp DCM_calc = newTemp( Ity_I32 );
+ UInt max_exp = 0;
+ UInt min_exp = 0;
+ IRTemp min_subnormalD64 = newTemp( Ity_D64 );
+ IRTemp min_subnormalD128 = newTemp( Ity_D128 );
+ IRTemp significand64 = newTemp( Ity_D64 );
+ IRTemp significand128 = newTemp( Ity_D128 );
+ IRTemp exp_min_normal = newTemp( Ity_D64 );
+ IRTemp exponent = newTemp( Ity_I32 );
+
+ IRTemp infinity_true = newTemp( Ity_I32 );
+ IRTemp SNaN_true = newTemp( Ity_I32 );
+ IRTemp QNaN_true = newTemp( Ity_I32 );
+ IRTemp subnormal_true = newTemp( Ity_I32 );
+ IRTemp normal_true = newTemp( Ity_I32 );
+ IRTemp extreme_true = newTemp( Ity_I32 );
+ IRTemp lmd = newTemp( Ity_I32 );
+ IRTemp lmd_zero_true = newTemp( Ity_I32 );
+ IRTemp zero_true = newTemp( Ity_I32 );
+ IRTemp sign = newTemp( Ity_I32 );
+ IRTemp field = newTemp( Ity_I32 );
+ IRTemp ccIR_zero = newTemp( Ity_I32 );
+ IRTemp ccIR_subnormal = newTemp( Ity_I32 );
+
+ /* UInt size = DFP_LONG; JRS:unused */
+ IRTemp gfield = newTemp( Ity_I32 );
+ IRTemp gfield_0_4_shift = newTemp( Ity_I8 );
+ IRTemp gfield_mask = newTemp( Ity_I32 );
+ IRTemp dcm0 = newTemp( Ity_I32 );
+ IRTemp dcm1 = newTemp( Ity_I32 );
+ IRTemp dcm2 = newTemp( Ity_I32 );
+ IRTemp dcm3 = newTemp( Ity_I32 );
+ IRTemp dcm4 = newTemp( Ity_I32 );
+ IRTemp dcm5 = newTemp( Ity_I32 );
+
+ /* The only difference between the dtstdc and dtstdcq instructions is
+ * size of the T and G fields. The calculation of the 4 bit field
+ * is the same. Setup the parameters and values that are DFP size
+ * specific. The rest of the code is independent of the DFP size.
+ *
+ * The Io_CmpD64 is used below. The instruction sets the ccIR values.
+ * The interpretation of the ccIR values is as follows:
+ *
+ * DFP cmp result | IR
+ * --------------------------
+ * UN | 0x45
+ * EQ | 0x40
+ * GT | 0x00
+ * LT | 0x01
+ */
+
+ assign( frA, getDReg( frA_addr ) );
+ assign( frAI64_hi, unop( Iop_ReinterpD64asI64, mkexpr( frA ) ) );
+
+ assign( abs_frA, unop( Iop_ReinterpI64asD64,
+ binop( Iop_And64,
+ unop( Iop_ReinterpD64asI64,
+ mkexpr( frA ) ),
+ mkU64( 0x7FFFFFFFFFFFFFFFULL ) ) ) );
+ assign( gfield_0_4_shift, mkU8( 31 - 5 ) ); // G-field[0:4]
+ switch (opc1) {
+ case 0x3b: // dtstdc, dtstdg
+ DIP("dtstd%s %u,r%u,%d\n", opc2 == 0xc2 ? "c" : "g",
+ crfD, frA_addr, DCM);
+ /* setup the parameters for the long format of the two instructions */
+ assign( frAI64_lo, mkU64( 0 ) );
+ assign( gfield_mask, mkU32( DFP_G_FIELD_LONG_MASK ) );
+ max_exp = DFP_LONG_EXP_MAX;
+ min_exp = DFP_LONG_EXP_MIN;
+
+ assign( exponent, unop( Iop_64to32,
+ unop( Iop_ReinterpD64asI64,
+ unop( Iop_ExtractExpD64,
+ mkexpr( frA ) ) ) ) );
+ assign( significand64,
+ unop( Iop_ReinterpI64asD64,
+ mkU64( 0x2234000000000001ULL ) ) ); // dfp 1.0
+ assign( exp_min_normal,
+ unop( Iop_ReinterpI64asD64, mkU64( 398 - 383 ) ) );
+ assign( min_subnormalD64,
+ binop( Iop_InsertExpD64,
+ mkexpr( exp_min_normal ),
+ mkexpr( significand64 ) ) );
+
+ assign( ccIR_subnormal,
+ binop( Iop_CmpD64,
+ mkexpr( abs_frA ),
+ mkexpr( min_subnormalD64 ) ) );
+
+ /* compare absolute value of frA with zero */
+ assign( ccIR_zero,
+ binop( Iop_CmpD64,
+ mkexpr( abs_frA ),
+ unop( Iop_ReinterpI64asD64,
+ mkU64( 0x2238000000000000ULL ) ) ) );
+
+ /* size = DFP_LONG; JRS: unused */
+ break;
+
+ case 0x3F: // dtstdcq, dtstdgq
+ DIP("dtstd%sq %u,r%u,%d\n", opc2 == 0xc2 ? "c" : "g",
+ crfD, frA_addr, DCM);
+ /* setup the parameters for the extended format of the
+ * two instructions
+ */
+ assign( frAI64_lo, unop( Iop_ReinterpD64asI64,
+ getDReg( frA_addr+1 ) ) );
+
+ assign( gfield_mask, mkU32( DFP_G_FIELD_EXTND_MASK ) );
+ max_exp = DFP_EXTND_EXP_MAX;
+ min_exp = DFP_EXTND_EXP_MIN;
+ assign( exponent, unop( Iop_64to32,
+ unop( Iop_ReinterpD64asI64,
+ unop( Iop_ExtractExpD128,
+ getDReg_pair( frA_addr) ) ) ) );
+
+ /* create quand exponent for minimum normal number */
+ assign( exp_min_normal,
+ unop( Iop_ReinterpI64asD64, mkU64( 6176 - 6143 ) ) );
+ assign( significand128,
+ unop( Iop_D64toD128,
+ unop( Iop_ReinterpI64asD64,
+ mkU64( 0x2234000000000001ULL ) ) ) ); // dfp 1.0
+
+ assign( min_subnormalD128,
+ binop( Iop_InsertExpD128,
+ mkexpr( exp_min_normal ),
+ mkexpr( significand128 ) ) );
+
+ assign( ccIR_subnormal,
+ binop( Iop_CmpD128,
+ binop( Iop_D64HLtoD128,
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_And64,
+ unop( Iop_ReinterpD64asI64,
+ mkexpr( frA ) ),
+ mkU64( 0x7FFFFFFFFFFFFFFFULL ) ) ),
+ getDReg( frA_addr+1 ) ),
+ mkexpr( min_subnormalD128 ) ) );
+ assign( ccIR_zero,
+ binop( Iop_CmpD128,
+ binop( Iop_D64HLtoD128,
+ mkexpr( abs_frA ),
+ getDReg( frA_addr+1 ) ),
+ unop( Iop_D64toD128,
+ unop( Iop_ReinterpI64asD64,
+ mkU64( 0x0ULL ) ) ) ) );
+
+ /* size = DFP_EXTND; JRS:unused */
+ break;
+ default:
+ vex_printf("dis_dfp_class_test(ppc)(opc2)\n");
+ return False;
+ }
+
+ /* The G-field is in the upper 32-bits. The I64 logical operations
+ * do not seem to be supported in 32-bit mode so keep things as 32-bit
+ * operations.
+ */
+ assign( gfield, binop( Iop_And32,
+ mkexpr( gfield_mask ),
+ unop( Iop_64HIto32,
+ mkexpr(frAI64_hi) ) ) );
+
+ /* There is a lot of code that is the same to do the class and group
+ * instructions. Later there is an if statement to handle the specific
+ * instruction.
+ *
+ * Will be using I32 values, compares, shifts and logical operations for
+ * this code as the 64-bit compare, shifts, logical operations are not
+ * supported in 32-bit mode.
+ */
+
+ /* Check the bits for Infinity, QNaN or Signaling NaN */
+ assign( infinity_true,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ binop( Iop_And32,
+ mkU32( 0x7C000000 ),
+ mkexpr( gfield ) ),
+ mkU32( 0x78000000 ) ) ) );
+
+ assign( SNaN_true,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ binop( Iop_And32,
+ mkU32( 0x7E000000 ),
+ mkexpr( gfield ) ),
+ mkU32( 0x7E000000 ) ) ) );
+
+ assign( QNaN_true,
+ binop( Iop_And32,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ binop( Iop_And32,
+ mkU32( 0x7E000000 ),
+ mkexpr( gfield ) ),
+ mkU32( 0x7C000000 ) ) ),
+ unop( Iop_Not32,
+ mkexpr( SNaN_true ) ) ) );
+
+ assign( zero_true,
+ binop( Iop_And32,
+ unop(Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( ccIR_zero ),
+ mkU32( 0x40 ) ) ), // ccIR code for Equal
+ unop( Iop_Not32,
+ binop( Iop_Or32,
+ mkexpr( infinity_true ),
+ binop( Iop_Or32,
+ mkexpr( QNaN_true ),
+ mkexpr( SNaN_true ) ) ) ) ) );
+
+ /* Do compare of frA the minimum normal value. Comparison is size
+ * depenent and was done above to get the ccIR value.
+ */
+ assign( subnormal_true,
+ binop( Iop_And32,
+ binop( Iop_Or32,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( ccIR_subnormal ),
+ mkU32( 0x40 ) ) ), // ccIR code for Equal
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( ccIR_subnormal ),
+ mkU32( 0x1 ) ) ) ), // ccIR code for LT
+ unop( Iop_Not32,
+ binop( Iop_Or32,
+ binop( Iop_Or32,
+ mkexpr( infinity_true ),
+ mkexpr( zero_true) ),
+ binop( Iop_Or32,
+ mkexpr( QNaN_true ),
+ mkexpr( SNaN_true ) ) ) ) ) );
+
+ /* Normal number is not subnormal, infinity, NaN or Zero */
+ assign( normal_true,
+ unop( Iop_Not32,
+ binop( Iop_Or32,
+ binop( Iop_Or32,
+ mkexpr( infinity_true ),
+ mkexpr( zero_true ) ),
+ binop( Iop_Or32,
+ mkexpr( subnormal_true ),
+ binop( Iop_Or32,
+ mkexpr( QNaN_true ),
+ mkexpr( SNaN_true ) ) ) ) ) );
+
+ /* Calculate the DCM bit field based on the tests for the specific
+ * instruction
+ */
+ if (opc2 == 0xC2) { // dtstdc, dtstdcq
+ /* DCM[0:5] Bit Data Class definition
+ * 0 Zero
+ * 1 Subnormal
+ * 2 Normal
+ * 3 Infinity
+ * 4 Quiet NaN
+ * 5 Signaling NaN
+ */
+
+ assign( dcm0, binop( Iop_Shl32,
+ mkexpr( zero_true ),
+ mkU8( 5 ) ) );
+ assign( dcm1, binop( Iop_Shl32,
+ binop( Iop_And32,
+ mkexpr( subnormal_true ),
+ mkU32( 1 ) ),
+ mkU8( 4 ) ) );
+ assign( dcm2, binop( Iop_Shl32,
+ binop( Iop_And32,
+ mkexpr( normal_true ),
+ mkU32( 1 ) ),
+ mkU8( 3 ) ) );
+ assign( dcm3, binop( Iop_Shl32,
+ binop( Iop_And32,
+ mkexpr( infinity_true),
+ mkU32( 1 ) ),
+ mkU8( 2 ) ) );
+ assign( dcm4, binop( Iop_Shl32,
+ binop( Iop_And32,
+ mkexpr( QNaN_true ),
+ mkU32( 1 ) ),
+ mkU8( 1 ) ) );
+ assign( dcm5, binop( Iop_And32, mkexpr( SNaN_true), mkU32( 1 ) ) );
+
+ } else if (opc2 == 0xE2) { // dtstdg, dtstdgq
+ /* check if the exponent is extreme */
+ assign( extreme_true, binop( Iop_Or32,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( exponent ),
+ mkU32( max_exp ) ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( exponent ),
+ mkU32( min_exp ) ) ) ) );
+
+ /* Check if LMD is zero */
+ Get_lmd( &lmd, binop( Iop_Shr32,
+ mkexpr( gfield ), mkU8( 31 - 5 ) ) );
+
+ assign( lmd_zero_true, unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( lmd ),
+ mkU32( 0 ) ) ) );
+
+ /* DCM[0:5] Bit Data Class definition
+ * 0 Zero with non-extreme exponent
+ * 1 Zero with extreme exponent
+ * 2 Subnormal or (Normal with extreme exponent)
+ * 3 Normal with non-extreme exponent and
+ * leftmost zero digit in significand
+ * 4 Normal with non-extreme exponent and
+ * leftmost nonzero digit in significand
+ * 5 Special symbol (Infinity, QNaN, or SNaN)
+ */
+ assign( dcm0, binop( Iop_Shl32,
+ binop( Iop_And32,
+ binop( Iop_And32,
+ unop( Iop_Not32,
+ mkexpr( extreme_true ) ),
+ mkexpr( zero_true ) ),
+ mkU32( 0x1 ) ),
+ mkU8( 5 ) ) );
+
+ assign( dcm1, binop( Iop_Shl32,
+ binop( Iop_And32,
+ binop( Iop_And32,
+ mkexpr( extreme_true ),
+ mkexpr( zero_true ) ),
+ mkU32( 0x1 ) ),
+ mkU8( 4 ) ) );
+
+ assign( dcm2, binop( Iop_Shl32,
+ binop( Iop_And32,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( extreme_true ),
+ mkexpr( normal_true ) ),
+ mkexpr( subnormal_true ) ),
+ mkU32( 0x1 ) ),
+ mkU8( 3 ) ) );
+
+ assign( dcm3, binop( Iop_Shl32,
+ binop( Iop_And32,
+ binop( Iop_And32,
+ binop( Iop_And32,
+ unop( Iop_Not32,
+ mkexpr( extreme_true ) ),
+ mkexpr( normal_true ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ mkexpr( lmd ),
+ mkU32( 0 ) ) ) ),
+ mkU32( 0x1 ) ),
+ mkU8( 2 ) ) );
+
+ assign( dcm4, binop( Iop_Shl32,
+ binop( Iop_And32,
+ binop( Iop_And32,
+ binop( Iop_And32,
+ unop( Iop_Not32,
+ mkexpr( extreme_true ) ),
+ mkexpr( normal_true ) ),
+ unop( Iop_1Sto32,
+ binop( Iop_CmpNE32,
+ mkexpr( lmd ),
+ mkU32( 0 ) ) ) ),
+ mkU32( 0x1 ) ),
+ mkU8( 1 ) ) );
+
+ assign( dcm5, binop( Iop_And32,
+ binop( Iop_Or32,
+ mkexpr( SNaN_true),
+ binop( Iop_Or32,
+ mkexpr( QNaN_true),
+ mkexpr( infinity_true) ) ),
+ mkU32( 0x1 ) ) );
+ }
+
+ /* create DCM field */
+ assign( DCM_calc,
+ binop( Iop_Or32,
+ mkexpr( dcm0 ),
+ binop( Iop_Or32,
+ mkexpr( dcm1 ),
+ binop( Iop_Or32,
+ mkexpr( dcm2 ),
+ binop( Iop_Or32,
+ mkexpr( dcm3 ),
+ binop( Iop_Or32,
+ mkexpr( dcm4 ),
+ mkexpr( dcm5 ) ) ) ) ) ) );
+
+ /* Get the sign of the DFP number, ignore sign for QNaN */
+ assign( sign,
+ unop( Iop_1Uto32,
+ binop( Iop_CmpEQ32,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, mkexpr( frAI64_hi ) ),
+ mkU8( 63 - 32 ) ),
+ mkU32( 1 ) ) ) );
+
+ /* This instruction generates a four bit field to be stored in the
+ * condition code register. The condition code register consists of 7
+ * fields. The field to be written to is specified by the BF (AKA crfD)
+ * field.
+ *
+ * The field layout is as follows:
+ *
+ * Field Meaning
+ * 0000 Operand positive with no match
+ * 0100 Operand positive with at least one match
+ * 0001 Operand negative with no match
+ * 0101 Operand negative with at least one match
+ */
+ assign( field, binop( Iop_Or32,
+ binop( Iop_Shl32,
+ mkexpr( sign ),
+ mkU8( 3 ) ),
+ binop( Iop_Shl32,
+ unop( Iop_1Uto32,
+ binop( Iop_CmpNE32,
+ binop( Iop_And32,
+ mkU32( DCM ),
+ mkexpr( DCM_calc ) ),
+ mkU32( 0 ) ) ),
+ mkU8( 1 ) ) ) );
+
+ putGST_field( PPC_GST_CR, mkexpr( field ), crfD );
+ return True;
+}
+
+static Bool dis_dfp_bcd(UInt theInstr) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ ULong sp = IFIELD(theInstr, 19, 2);
+ ULong s = IFIELD(theInstr, 20, 1);
+ UChar frT_addr = ifieldRegDS( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ IRTemp frB = newTemp( Ity_D64 );
+ IRTemp frBI64 = newTemp( Ity_I64 );
+ IRTemp result = newTemp( Ity_I64 );
+ IRTemp resultD64 = newTemp( Ity_D64 );
+ IRTemp bcd64 = newTemp( Ity_I64 );
+ IRTemp bcd_u = newTemp( Ity_I32 );
+ IRTemp bcd_l = newTemp( Ity_I32 );
+ IRTemp dbcd_u = newTemp( Ity_I32 );
+ IRTemp dbcd_l = newTemp( Ity_I32 );
+ IRTemp lmd = newTemp( Ity_I32 );
+
+ assign( frB, getDReg( frB_addr ) );
+ assign( frBI64, unop( Iop_ReinterpD64asI64, mkexpr( frB ) ) );
+
+ switch ( opc2 ) {
+ case 0x142: // ddedpd DFP Decode DPD to BCD
+ DIP( "ddedpd %llu,r%u,r%u\n", sp, frT_addr, frB_addr );
+
+ assign( bcd64, unop( Iop_DPBtoBCD, mkexpr( frBI64 ) ) );
+ assign( bcd_u, unop( Iop_64HIto32, mkexpr( bcd64 ) ) );
+ assign( bcd_l, unop( Iop_64to32, mkexpr( bcd64 ) ) );
+
+ if ( ( sp == 0 ) || ( sp == 1 ) ) {
+ /* Unsigned BCD string */
+ Get_lmd( &lmd,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, mkexpr( frBI64 ) ),
+ mkU8( 31 - 5 ) ) ); // G-field[0:4]
+
+ assign( result,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_Shl32, mkexpr( lmd ), mkU8( 28 ) ),
+ mkexpr( bcd_u ) ),
+ mkexpr( bcd_l ) ) );
+
+ } else {
+ /* Signed BCD string, the cases for sp 2 and 3 only differ in how
+ * the positive and negative values are encoded in the least
+ * significant bits.
+ */
+ IRTemp sign = newTemp( Ity_I32 );
+
+ if (sp == 2) {
+ /* Positive sign = 0xC, negative sign = 0xD */
+
+ assign( sign,
+ binop( Iop_Or32,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, mkexpr( frBI64 ) ),
+ mkU8( 31 ) ),
+ mkU32( 0xC ) ) );
+
+ } else if ( sp == 3 ) {
+ /* Positive sign = 0xF, negative sign = 0xD */
+ IRTemp tmp32 = newTemp( Ity_I32 );
+
+ /* Complement sign bit then OR into bit position 1 */
+ assign( tmp32,
+ binop( Iop_Xor32,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, mkexpr( frBI64 ) ),
+ mkU8( 30 ) ),
+ mkU32( 0x2 ) ) );
+
+ assign( sign, binop( Iop_Or32, mkexpr( tmp32 ), mkU32( 0xD ) ) );
+
+ } else {
+ vpanic( "The impossible happened: dis_dfp_bcd(ppc), undefined SP field" );
+ }
+
+ /* Put sign in bottom 4 bits, move most significant 4-bits from
+ * bcd_l to bcd_u.
+ */
+ assign( result,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_Shr32,
+ mkexpr( bcd_l ),
+ mkU8( 28 ) ),
+ binop( Iop_Shl32,
+ mkexpr( bcd_u ),
+ mkU8( 4 ) ) ),
+ binop( Iop_Or32,
+ mkexpr( sign ),
+ binop( Iop_Shl32,
+ mkexpr( bcd_l ),
+ mkU8( 4 ) ) ) ) );
+ }
+
+ putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result ) ) );
+ break;
+
+ case 0x342: // denbcd DFP Encode BCD to DPD
+ {
+ IRTemp valid_mask = newTemp( Ity_I32 );
+ IRTemp invalid_mask = newTemp( Ity_I32 );
+ IRTemp without_lmd = newTemp( Ity_I64 );
+ IRTemp tmp64 = newTemp( Ity_I64 );
+ IRTemp dbcd64 = newTemp( Ity_I64 );
+ IRTemp left_exp = newTemp( Ity_I32 );
+ IRTemp g0_4 = newTemp( Ity_I32 );
+
+ DIP( "denbcd %llu,r%u,r%u\n", s, frT_addr, frB_addr );
+
+ if ( s == 0 ) {
+ /* Unsigned BCD string */
+ assign( dbcd64, unop( Iop_BCDtoDPB, mkexpr(frBI64 ) ) );
+ assign( dbcd_u, unop( Iop_64HIto32, mkexpr( dbcd64 ) ) );
+ assign( dbcd_l, unop( Iop_64to32, mkexpr( dbcd64 ) ) );
+
+ assign( lmd,
+ binop( Iop_Shr32,
+ binop( Iop_And32,
+ unop( Iop_64HIto32, mkexpr( frBI64 ) ),
+ mkU32( 0xF0000000 ) ),
+ mkU8( 28 ) ) );
+
+ assign( invalid_mask,
+ bcd_digit_inval( unop( Iop_64HIto32, mkexpr( frBI64 ) ),
+ unop( Iop_64to32, mkexpr( frBI64 ) ) ) );
+ assign( valid_mask, unop( Iop_Not32, mkexpr( invalid_mask ) ) );
+
+ assign( without_lmd,
+ unop( Iop_ReinterpD64asI64,
+ binop( Iop_InsertExpD64,
+ unop( Iop_ReinterpI64asD64,
+ mkU64( DFP_LONG_BIAS ) ),
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_32HLto64,
+ mkexpr( dbcd_u ),
+ mkexpr( dbcd_l ) ) ) ) ) );
+ assign( left_exp,
+ binop( Iop_Shr32,
+ binop( Iop_And32,
+ unop( Iop_64HIto32, mkexpr( without_lmd ) ),
+ mkU32( 0x60000000 ) ),
+ mkU8( 29 ) ) );
+
+ assign( g0_4,
+ binop( Iop_Shl32,
+ Gfield_encoding( mkexpr( left_exp ), mkexpr( lmd ) ),
+ mkU8( 26 ) ) );
+
+ assign( tmp64,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ unop( Iop_64HIto32,
+ mkexpr( without_lmd ) ),
+ mkU32( 0x83FFFFFF ) ),
+ mkexpr( g0_4 ) ),
+ unop( Iop_64to32, mkexpr( without_lmd ) ) ) );
+
+ } else if ( s == 1 ) {
+ IRTemp sign = newTemp( Ity_I32 );
+ IRTemp sign_bit = newTemp( Ity_I32 );
+ IRTemp pos_sign_mask = newTemp( Ity_I32 );
+ IRTemp neg_sign_mask = newTemp( Ity_I32 );
+ IRTemp tmp = newTemp( Ity_I64 );
+
+ /* Signed BCD string, least significant 4 bits are sign bits
+ * positive sign = 0xC, negative sign = 0xD
+ */
+ assign( tmp, unop( Iop_BCDtoDPB,
+ binop( Iop_32HLto64,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32,
+ mkexpr( frBI64 ) ),
+ mkU8( 4 ) ),
+ binop( Iop_Or32,
+ binop( Iop_Shr32,
+ unop( Iop_64to32,
+ mkexpr( frBI64 ) ),
+ mkU8( 4 ) ),
+ binop( Iop_Shl32,
+ unop( Iop_64HIto32,
+ mkexpr( frBI64 ) ),
+ mkU8( 28 ) ) ) ) ) );
+
+ assign( dbcd_u, unop( Iop_64HIto32, mkexpr( tmp ) ) );
+ assign( dbcd_l, unop( Iop_64to32, mkexpr( tmp ) ) );
+
+ /* Get the sign of the BCD string. */
+ assign( sign,
+ binop( Iop_And32,
+ unop( Iop_64to32, mkexpr( frBI64 ) ),
+ mkU32( 0xF ) ) );
+
+ assign( neg_sign_mask, Generate_neg_sign_mask( mkexpr( sign ) ) );
+ assign( pos_sign_mask, Generate_pos_sign_mask( mkexpr( sign ) ) );
+ assign( sign_bit,
+ Generate_sign_bit( mkexpr( pos_sign_mask ),
+ mkexpr( neg_sign_mask ) ) );
+
+ /* Check for invalid sign and BCD digit. Don't check the bottom
+ * four bits of bcd_l as that is the sign value.
+ */
+ assign( invalid_mask,
+ Generate_inv_mask(
+ bcd_digit_inval( unop( Iop_64HIto32,
+ mkexpr( frBI64 ) ),
+ binop( Iop_Shr32,
+ unop( Iop_64to32,
+ mkexpr( frBI64 ) ),
+ mkU8( 4 ) ) ),
+ mkexpr( pos_sign_mask ),
+ mkexpr( neg_sign_mask ) ) );
+
+ assign( valid_mask, unop( Iop_Not32, mkexpr( invalid_mask ) ) );
+
+ /* Generate the result assuming the sign value was valid. */
+ assign( tmp64,
+ unop( Iop_ReinterpD64asI64,
+ binop( Iop_InsertExpD64,
+ unop( Iop_ReinterpI64asD64,
+ mkU64( DFP_LONG_BIAS ) ),
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ mkexpr( dbcd_u ),
+ mkexpr( sign_bit ) ),
+ mkexpr( dbcd_l ) ) ) ) ) );
+ }
+
+ /* Generate the value to store depending on the validity of the
+ * sign value and the validity of the BCD digits.
+ */
+ assign( resultD64,
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( valid_mask ),
+ unop( Iop_64HIto32,
+ mkexpr( tmp64 ) ) ),
+ binop( Iop_And32,
+ mkU32( 0x7C000000 ),
+ mkexpr( invalid_mask ) ) ),
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( valid_mask ),
+ unop( Iop_64to32, mkexpr( tmp64 ) ) ),
+ binop( Iop_And32,
+ mkU32( 0x0 ),
+ mkexpr( invalid_mask ) ) ) ) ) );
+ putDReg( frT_addr, mkexpr( resultD64 ) );
+ }
+ break;
+ default:
+ vpanic( "ERROR: dis_dfp_bcd(ppc), undefined opc2 case " );
+ return False;
+ }
+ return True;
+}
+
+static Bool dis_dfp_bcdq( UInt theInstr )
+{
+ UInt opc2 = ifieldOPClo10( theInstr );
+ ULong sp = IFIELD(theInstr, 19, 2);
+ ULong s = IFIELD(theInstr, 20, 1);
+ IRTemp frB_hi = newTemp( Ity_D64 );
+ IRTemp frB_lo = newTemp( Ity_D64 );
+ IRTemp frBI64_hi = newTemp( Ity_I64 );
+ IRTemp frBI64_lo = newTemp( Ity_I64 );
+ UChar frT_addr = ifieldRegDS( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+
+ IRTemp lmd = newTemp( Ity_I32 );
+ IRTemp result_hi = newTemp( Ity_I64 );
+ IRTemp result_lo = newTemp( Ity_I64 );
+
+ assign( frB_hi, getDReg( frB_addr ) );
+ assign( frB_lo, getDReg( frB_addr + 1 ) );
+ assign( frBI64_hi, unop( Iop_ReinterpD64asI64, mkexpr( frB_hi ) ) );
+ assign( frBI64_lo, unop( Iop_ReinterpD64asI64, mkexpr( frB_lo ) ) );
+
+ switch ( opc2 ) {
+ case 0x142: // ddedpdq DFP Decode DPD to BCD
+ {
+ IRTemp low_60_u = newTemp( Ity_I32 );
+ IRTemp low_60_l = newTemp( Ity_I32 );
+ IRTemp mid_60_u = newTemp( Ity_I32 );
+ IRTemp mid_60_l = newTemp( Ity_I32 );
+ IRTemp top_12_l = newTemp( Ity_I32 );
+
+ DIP( "ddedpdq %llu,r%u,r%u\n", sp, frT_addr, frB_addr );
+
+ /* Note, instruction only stores the lower 32 BCD digits in
+ * the result
+ */
+ Generate_132_bit_bcd_string( mkexpr( frBI64_hi ),
+ mkexpr( frBI64_lo ),
+ &top_12_l,
+ &mid_60_u,
+ &mid_60_l,
+ &low_60_u,
+ &low_60_l );
+
+ if ( ( sp == 0 ) || ( sp == 1 ) ) {
+ /* Unsigned BCD string */
+ assign( result_hi,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ mkexpr( top_12_l ),
+ mkU8( 24 ) ),
+ binop( Iop_Shr32,
+ mkexpr( mid_60_u ),
+ mkU8( 4 ) ) ),
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ mkexpr( mid_60_u ),
+ mkU8( 28 ) ),
+ binop( Iop_Shr32,
+ mkexpr( mid_60_l ),
+ mkU8( 4 ) ) ) ) );
+
+ assign( result_lo,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ mkexpr( mid_60_l ),
+ mkU8( 28 ) ),
+ mkexpr( low_60_u ) ),
+ mkexpr( low_60_l ) ) );
+
+ } else {
+ /* Signed BCD string, the cases for sp 2 and 3 only differ in how
+ * the positive and negative values are encoded in the least
+ * significant bits.
+ */
+ IRTemp sign = newTemp( Ity_I32 );
+
+ if ( sp == 2 ) {
+ /* Positive sign = 0xC, negative sign = 0xD */
+ assign( sign,
+ binop( Iop_Or32,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, mkexpr( frBI64_hi ) ),
+ mkU8( 31 ) ),
+ mkU32( 0xC ) ) );
+
+ } else if ( sp == 3 ) {
+ IRTemp tmp32 = newTemp( Ity_I32 );
+
+ /* Positive sign = 0xF, negative sign = 0xD.
+ * Need to complement sign bit then OR into bit position 1.
+ */
+ assign( tmp32,
+ binop( Iop_Xor32,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, mkexpr( frBI64_hi ) ),
+ mkU8( 30 ) ),
+ mkU32( 0x2 ) ) );
+
+ assign( sign, binop( Iop_Or32, mkexpr( tmp32 ), mkU32( 0xD ) ) );
+
+ } else {
+ vpanic( "The impossible happened: dis_dfp_bcd(ppc), undefined SP field" );
+ }
+
+ assign( result_hi,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ mkexpr( top_12_l ),
+ mkU8( 28 ) ),
+ mkexpr( mid_60_u ) ),
+ mkexpr( mid_60_l ) ) );
+
+ assign( result_lo,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ mkexpr( low_60_u ),
+ mkU8( 4 ) ),
+ binop( Iop_Shr32,
+ mkexpr( low_60_l ),
+ mkU8( 28 ) ) ),
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ mkexpr( low_60_l ),
+ mkU8( 4 ) ),
+ mkexpr( sign ) ) ) );
+ }
+
+ putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result_hi ) ) );
+ putDReg( frT_addr + 1,
+ unop( Iop_ReinterpI64asD64, mkexpr( result_lo ) ) );
+ }
+ break;
+ case 0x342: // denbcdq DFP Encode BCD to DPD
+ {
+ IRTemp valid_mask = newTemp( Ity_I32 );
+ IRTemp invalid_mask = newTemp( Ity_I32 );
+ IRTemp result128 = newTemp( Ity_D128 );
+ IRTemp dfp_significand = newTemp( Ity_D128 );
+ IRTemp tmp_hi = newTemp( Ity_I64 );
+ IRTemp tmp_lo = newTemp( Ity_I64 );
+ IRTemp dbcd_top_l = newTemp( Ity_I32 );
+ IRTemp dbcd_mid_u = newTemp( Ity_I32 );
+ IRTemp dbcd_mid_l = newTemp( Ity_I32 );
+ IRTemp dbcd_low_u = newTemp( Ity_I32 );
+ IRTemp dbcd_low_l = newTemp( Ity_I32 );
+ IRTemp bcd_top_8 = newTemp( Ity_I64 );
+ IRTemp bcd_mid_60 = newTemp( Ity_I64 );
+ IRTemp bcd_low_60 = newTemp( Ity_I64 );
+ IRTemp sign_bit = newTemp( Ity_I32 );
+ IRTemp tmptop10 = newTemp( Ity_I64 );
+ IRTemp tmpmid50 = newTemp( Ity_I64 );
+ IRTemp tmplow50 = newTemp( Ity_I64 );
+ IRTemp inval_bcd_digit_mask = newTemp( Ity_I32 );
+
+ DIP( "denbcd %llu,r%u,r%u\n", s, frT_addr, frB_addr );
+
+ if ( s == 0 ) {
+ /* Unsigned BCD string */
+ assign( sign_bit, mkU32( 0 ) ); // set to zero for unsigned string
+
+ assign( bcd_top_8,
+ binop( Iop_32HLto64,
+ mkU32( 0 ),
+ binop( Iop_And32,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32,
+ mkexpr( frBI64_hi ) ),
+ mkU8( 24 ) ),
+ mkU32( 0xFF ) ) ) );
+ assign( bcd_mid_60,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_Shr32,
+ unop( Iop_64to32,
+ mkexpr( frBI64_hi ) ),
+ mkU8( 28 ) ),
+ binop( Iop_Shl32,
+ unop( Iop_64HIto32,
+ mkexpr( frBI64_hi ) ),
+ mkU8( 4 ) ) ),
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ unop( Iop_64to32,
+ mkexpr( frBI64_hi ) ),
+ mkU8( 4 ) ),
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32,
+ mkexpr( frBI64_lo ) ),
+ mkU8( 28 ) ) ) ) );
+
+ /* Note, the various helper functions ignores top 4-bits */
+ assign( bcd_low_60, mkexpr( frBI64_lo ) );
+
+ assign( tmptop10, unop( Iop_BCDtoDPB, mkexpr( bcd_top_8 ) ) );
+ assign( dbcd_top_l, unop( Iop_64to32, mkexpr( tmptop10 ) ) );
+
+ assign( tmpmid50, unop( Iop_BCDtoDPB, mkexpr( bcd_mid_60 ) ) );
+ assign( dbcd_mid_u, unop( Iop_64HIto32, mkexpr( tmpmid50 ) ) );
+ assign( dbcd_mid_l, unop( Iop_64to32, mkexpr( tmpmid50 ) ) );
+
+ assign( tmplow50, unop( Iop_BCDtoDPB, mkexpr( bcd_low_60 ) ) );
+ assign( dbcd_low_u, unop( Iop_64HIto32, mkexpr( tmplow50 ) ) );
+ assign( dbcd_low_l, unop( Iop_64to32, mkexpr( tmplow50 ) ) );
+
+ /* The entire BCD string fits in lower 110-bits. The LMD = 0,
+ * value is not part of the final result. Only the right most
+ * BCD digits are stored.
+ */
+ assign( lmd, mkU32( 0 ) );
+
+ assign( invalid_mask,
+ binop( Iop_Or32,
+ bcd_digit_inval( mkU32( 0 ),
+ unop( Iop_64to32,
+ mkexpr( bcd_top_8 ) ) ),
+ binop( Iop_Or32,
+ bcd_digit_inval( unop( Iop_64HIto32,
+ mkexpr( bcd_mid_60 ) ),
+ unop( Iop_64to32,
+ mkexpr( bcd_mid_60 ) ) ),
+ bcd_digit_inval( unop( Iop_64HIto32,
+ mkexpr( bcd_low_60 ) ),
+ unop( Iop_64to32,
+ mkexpr( bcd_low_60 ) )
+ ) ) ) );
+
+ } else if ( s == 1 ) {
+ IRTemp sign = newTemp( Ity_I32 );
+ IRTemp zero = newTemp( Ity_I32 );
+ IRTemp pos_sign_mask = newTemp( Ity_I32 );
+ IRTemp neg_sign_mask = newTemp( Ity_I32 );
+
+ /* The sign of the BCD string is stored in lower 4 bits */
+ assign( sign,
+ binop( Iop_And32,
+ unop( Iop_64to32, mkexpr( frBI64_lo ) ),
+ mkU32( 0xF ) ) );
+ assign( neg_sign_mask, Generate_neg_sign_mask( mkexpr( sign ) ) );
+ assign( pos_sign_mask, Generate_pos_sign_mask( mkexpr( sign ) ) );
+ assign( sign_bit,
+ Generate_sign_bit( mkexpr( pos_sign_mask ),
+ mkexpr( neg_sign_mask ) ) );
+
+ /* Generate the value assuminig the sign and BCD digits are vaild */
+ assign( bcd_top_8,
+ binop( Iop_32HLto64,
+ mkU32( 0x0 ),
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, mkexpr( frBI64_hi ) ),
+ mkU8( 28 ) ) ) );
+
+ /* The various helper routines ignore the upper 4-bits */
+ assign( bcd_mid_60, mkexpr( frBI64_hi ) );
+
+ /* Remove bottom four sign bits */
+ assign( bcd_low_60,
+ binop( Iop_32HLto64,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32,
+ mkexpr( frBI64_lo ) ),
+ mkU8( 4 ) ),
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ unop( Iop_64HIto32,
+ mkexpr( frBI64_lo ) ),
+ mkU8( 28 ) ),
+ binop( Iop_Shr32,
+ unop( Iop_64to32,
+ mkexpr( frBI64_lo ) ),
+ mkU8( 4 ) ) ) ) );
+ assign( tmptop10, unop( Iop_BCDtoDPB, mkexpr(bcd_top_8 ) ) );
+ assign( dbcd_top_l, unop( Iop_64to32, mkexpr( tmptop10 ) ) );
+
+ assign( tmpmid50, unop( Iop_BCDtoDPB, mkexpr(bcd_mid_60 ) ) );
+ assign( dbcd_mid_u, unop( Iop_64HIto32, mkexpr( tmpmid50 ) ) );
+ assign( dbcd_mid_l, unop( Iop_64to32, mkexpr( tmpmid50 ) ) );
+
+ assign( tmplow50, unop( Iop_BCDtoDPB, mkexpr( bcd_low_60 ) ) );
+ assign( dbcd_low_u, unop( Iop_64HIto32, mkexpr( tmplow50 ) ) );
+ assign( dbcd_low_l, unop( Iop_64to32, mkexpr( tmplow50 ) ) );
+
+ /* The entire BCD string fits in lower 110-bits. The LMD value
+ * is not stored in the final result for the DFP Long instruction.
+ */
+ assign( lmd, mkU32( 0 ) );
+
+ /* Check for invalid sign and invalid BCD digit. Don't check the
+ * bottom four bits of frBI64_lo as that is the sign value.
+ */
+ assign( zero, mkU32( 0 ) );
+ assign( inval_bcd_digit_mask,
+ binop( Iop_Or32,
+ bcd_digit_inval( mkexpr( zero ),
+ unop( Iop_64to32,
+ mkexpr( bcd_top_8 ) ) ),
+ binop( Iop_Or32,
+ bcd_digit_inval( unop( Iop_64HIto32,
+ mkexpr( bcd_mid_60 ) ),
+ unop( Iop_64to32,
+ mkexpr( bcd_mid_60 ) ) ),
+ bcd_digit_inval( unop( Iop_64HIto32,
+ mkexpr( frBI64_lo ) ),
+ binop( Iop_Shr32,
+ unop( Iop_64to32,
+ mkexpr( frBI64_lo ) ),
+ mkU8( 4 ) ) ) ) ) );
+ assign( invalid_mask,
+ Generate_inv_mask( mkexpr( inval_bcd_digit_mask ),
+ mkexpr( pos_sign_mask ),
+ mkexpr( neg_sign_mask ) ) );
+
+ }
+
+ assign( valid_mask, unop( Iop_Not32, mkexpr( invalid_mask ) ) );
+
+ /* Calculate the value of the result assuming sign and BCD digits
+ * are all valid.
+ */
+ assign( dfp_significand,
+ binop( Iop_D64HLtoD128,
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ mkexpr( sign_bit ),
+ mkexpr( dbcd_top_l ) ),
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ mkexpr( dbcd_mid_u ),
+ mkU8( 18 ) ),
+ binop( Iop_Shr32,
+ mkexpr( dbcd_mid_l ),
+ mkU8( 14 ) ) ) ) ),
+ unop( Iop_ReinterpI64asD64,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ mkexpr( dbcd_low_u ),
+ binop( Iop_Shl32,
+ mkexpr( dbcd_mid_l ),
+ mkU8( 18 ) ) ),
+ mkexpr( dbcd_low_l ) ) ) ) );
+
+ /* Break the result back down to 32-bit chunks and replace chunks.
+ * If there was an invalid BCD digit or invalid sign value, replace
+ * the calculated result with the invalid bit string.
+ */
+ assign( result128,
+ binop( Iop_InsertExpD128,
+ unop( Iop_ReinterpI64asD64, mkU64( DFP_EXTND_BIAS ) ),
+ mkexpr( dfp_significand ) ) );
+
+ assign( tmp_hi,
+ unop( Iop_ReinterpD64asI64,
+ unop( Iop_D128HItoD64, mkexpr( result128 ) ) ) );
+
+ assign( tmp_lo,
+ unop( Iop_ReinterpD64asI64,
+ unop( Iop_D128LOtoD64, mkexpr( result128 ) ) ) );
+
+ assign( result_hi,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( valid_mask ),
+ unop( Iop_64HIto32, mkexpr( tmp_hi ) ) ),
+ binop( Iop_And32,
+ mkU32( 0x7C000000 ),
+ mkexpr( invalid_mask ) ) ),
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( valid_mask ),
+ unop( Iop_64to32, mkexpr( tmp_hi ) ) ),
+ binop( Iop_And32,
+ mkU32( 0x0 ),
+ mkexpr( invalid_mask ) ) ) ) );
+
+ assign( result_lo,
+ binop( Iop_32HLto64,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( valid_mask ),
+ unop( Iop_64HIto32, mkexpr( tmp_lo ) ) ),
+ binop( Iop_And32,
+ mkU32( 0x0 ),
+ mkexpr( invalid_mask ) ) ),
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( valid_mask ),
+ unop( Iop_64to32, mkexpr( tmp_lo ) ) ),
+ binop( Iop_And32,
+ mkU32( 0x0 ),
+ mkexpr( invalid_mask ) ) ) ) );
+
+ putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result_hi ) ) );
+ putDReg( frT_addr + 1,
+ unop( Iop_ReinterpI64asD64, mkexpr( result_lo ) ) );
+
+ }
+ break;
+ default:
+ vpanic( "ERROR: dis_dfp_bcdq(ppc), undefined opc2 case " );
+ break;
+ }
+ return True;
+}
+
+static Bool dis_dfp_significant_digits( UInt theInstr )
+{
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ IRTemp frA = newTemp( Ity_D64 );
+ UInt opc1 = ifieldOPC( theInstr );
+ IRTemp B_sig = newTemp( Ity_I8 );
+ IRTemp K = newTemp( Ity_I8 );
+ IRTemp lmd_B = newTemp( Ity_I32 );
+ IRTemp field = newTemp( Ity_I32 );
+ UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); // AKA BF
+ IRTemp Unordered_true = newTemp( Ity_I32 );
+ IRTemp Eq_true_mask = newTemp( Ity_I32 );
+ IRTemp Lt_true_mask = newTemp( Ity_I32 );
+ IRTemp Gt_true_mask = newTemp( Ity_I32 );
+ IRTemp KisZero_true_mask = newTemp( Ity_I32 );
+ IRTemp KisZero_false_mask = newTemp( Ity_I32 );
+
+ /* Get the reference singificance stored in frA */
+ assign( frA, getDReg( frA_addr ) );
+
+ /* Convert from 64 bit to 8 bits in two steps. The Iop_64to8 is not
+ * supported in 32-bit mode.
+ */
+ assign( K, unop( Iop_32to8,
+ binop( Iop_And32,
+ unop( Iop_64to32,
+ unop( Iop_ReinterpD64asI64,
+ mkexpr( frA ) ) ),
+ mkU32( 0x3F ) ) ) );
+
+ switch ( opc1 ) {
+ case 0x3b: // dtstsf DFP Test Significance
+ {
+ IRTemp frB = newTemp( Ity_D64 );
+ IRTemp frBI64 = newTemp( Ity_I64 );
+ IRTemp B_bcd_u = newTemp( Ity_I32 );
+ IRTemp B_bcd_l = newTemp( Ity_I32 );
+ IRTemp tmp64 = newTemp( Ity_I64 );
+
+ DIP( "dtstsf %u,r%u,r%u\n", crfD, frA_addr, frB_addr );
+
+ assign( frB, getDReg( frB_addr ) );
+ assign( frBI64, unop( Iop_ReinterpD64asI64, mkexpr( frB ) ) );
+
+ /* Get the BCD string for the value stored in a series of I32 values.
+ * Count the number of leading zeros. Subtract the number of leading
+ * zeros from 16 (maximum number of significant digits in DFP
+ * Long).
+ */
+ Get_lmd( &lmd_B,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, mkexpr( frBI64 ) ),
+ mkU8( 31 - 5 ) ) ); // G-field[0:4]
+
+ assign( tmp64, unop( Iop_DPBtoBCD, mkexpr( frBI64 ) ) );
+ assign( B_bcd_u, unop( Iop_64HIto32, mkexpr( tmp64 ) ) );
+ assign( B_bcd_l, unop( Iop_64to32, mkexpr( tmp64 ) ) );
+
+ assign( B_sig,
+ binop( Iop_Sub8,
+ mkU8( DFP_LONG_MAX_SIG_DIGITS ),
+ Count_leading_zeros_60( mkexpr( lmd_B ),
+ mkexpr( B_bcd_u ),
+ mkexpr( B_bcd_l ) ) ) );
+ assign( Unordered_true, Check_unordered( mkexpr( frBI64 ) ) );
+ }
+ break;
+ case 0x3F: // dtstsfq DFP Test Significance
+ {
+ IRTemp frB_hi = newTemp( Ity_D64 );
+ IRTemp frB_lo = newTemp( Ity_D64 );
+ IRTemp frBI64_hi = newTemp( Ity_I64 );
+ IRTemp frBI64_lo = newTemp( Ity_I64 );
+ IRTemp B_low_60_u = newTemp( Ity_I32 );
+ IRTemp B_low_60_l = newTemp( Ity_I32 );
+ IRTemp B_mid_60_u = newTemp( Ity_I32 );
+ IRTemp B_mid_60_l = newTemp( Ity_I32 );
+ IRTemp B_top_12_l = newTemp( Ity_I32 );
+
+ DIP( "dtstsfq %u,r%u,r%u\n", crfD, frA_addr, frB_addr );
+
+ assign( frB_hi, getDReg( frB_addr ) );
+ assign( frB_lo, getDReg( frB_addr + 1 ) );
+
+ assign( frBI64_hi, unop( Iop_ReinterpD64asI64, mkexpr( frB_hi ) ) );
+ assign( frBI64_lo, unop( Iop_ReinterpD64asI64, mkexpr( frB_lo ) ) );
+
+ /* Get the BCD string for the value stored in a series of I32 values.
+ * Count the number of leading zeros. Subtract the number of leading
+ * zeros from 32 (maximum number of significant digits in DFP
+ * extended).
+ */
+ Get_lmd( &lmd_B,
+ binop( Iop_Shr32,
+ unop( Iop_64HIto32, mkexpr( frBI64_hi ) ),
+ mkU8( 31 - 5 ) ) ); // G-field[0:4]
+
+ Generate_132_bit_bcd_string( mkexpr( frBI64_hi ),
+ mkexpr( frBI64_lo ),
+ &B_top_12_l,
+ &B_mid_60_u,
+ &B_mid_60_l,
+ &B_low_60_u,
+ &B_low_60_l );
+
+ assign( B_sig,
+ binop( Iop_Sub8,
+ mkU8( DFP_EXTND_MAX_SIG_DIGITS ),
+ Count_leading_zeros_128( mkexpr( lmd_B ),
+ mkexpr( B_top_12_l ),
+ mkexpr( B_mid_60_u ),
+ mkexpr( B_mid_60_l ),
+ mkexpr( B_low_60_u ),
+ mkexpr( B_low_60_l ) ) ) );
+
+ assign( Unordered_true, Check_unordered( mkexpr( frBI64_hi ) ) );
+ }
+ break;
+ }
+
+ /* Compare (16 - cnt[0]) against K and set the condition code field
+ * accordingly.
+ *
+ * The field layout is as follows:
+ *
+ * bit[3:0] Description
+ * 3 K != 0 and K < Number of significant digits if FRB
+ * 2 K != 0 and K > Number of significant digits if FRB OR K = 0
+ * 1 K != 0 and K = Number of significant digits if FRB
+ * 0 K ? Number of significant digits if FRB
+ */
+ assign( Eq_true_mask,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ unop( Iop_8Uto32, mkexpr( K ) ),
+ unop( Iop_8Uto32, mkexpr( B_sig ) ) ) ) );
+ assign( Lt_true_mask,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLT32U,
+ unop( Iop_8Uto32, mkexpr( K ) ),
+ unop( Iop_8Uto32, mkexpr( B_sig ) ) ) ) );
+ assign( Gt_true_mask,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpLT32U,
+ unop( Iop_8Uto32, mkexpr( B_sig ) ),
+ unop( Iop_8Uto32, mkexpr( K ) ) ) ) );
+
+ assign( KisZero_true_mask,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpEQ32,
+ unop( Iop_8Uto32, mkexpr( K ) ),
+ mkU32( 0 ) ) ) );
+ assign( KisZero_false_mask,
+ unop( Iop_1Sto32,
+ binop( Iop_CmpNE32,
+ unop( Iop_8Uto32, mkexpr( K ) ),
+ mkU32( 0 ) ) ) );
+
+ assign( field,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( KisZero_false_mask ),
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( Lt_true_mask ),
+ mkU32( 0x8 ) ),
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( Gt_true_mask ),
+ mkU32( 0x4 ) ),
+ binop( Iop_And32,
+ mkexpr( Eq_true_mask ),
+ mkU32( 0x2 ) ) ) ) ),
+ binop( Iop_And32,
+ mkexpr( KisZero_true_mask ),
+ mkU32( 0x4 ) ) ) );
+
+ putGST_field( PPC_GST_CR,
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( Unordered_true ),
+ mkU32( 0x1 ) ),
+ binop( Iop_And32,
+ unop( Iop_Not32, mkexpr( Unordered_true ) ),
+ mkexpr( field ) ) ),
+ crfD );
+
+ return True;
+}
/*------------------------------------------------------------*/
/*--- AltiVec Instruction Translation ---*/
@@ -10291,6 +13442,8 @@
* of fnmadd and use pretty much the same code. However, that code has a bug in the
* way it blindly negates the signbit, even if the floating point result is a NaN.
* So, the TODO is to fix fnmadd (which I'll do in a different patch).
+ * FIXED 7/1/2012: carll fnmadd and fnmsubs fixed to not negate sign
+ * bit for NaN result.
*/
Bool mdp = opc2 == 0x2A4;
IRTemp frT = newTemp(Ity_F64);
@@ -11171,6 +14324,7 @@
/* declare guest state effects */
d->needsBBP = True;
d->nFxState = 1;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Write;
d->fxState[0].offset = vD_off;
d->fxState[0].size = sizeof(U128);
@@ -11204,6 +14358,7 @@
/* declare guest state effects */
d->needsBBP = True;
d->nFxState = 1;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Write;
d->fxState[0].offset = vD_off;
d->fxState[0].size = sizeof(U128);
@@ -13315,7 +16470,6 @@
static
DisResult disInstr_PPC_WRK (
- Bool put_IP,
Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -13334,6 +16488,7 @@
Bool allow_FX = False;
Bool allow_GX = False;
Bool allow_VX = False; // Equates to "supports Power ISA 2.06
+ Bool allow_DFP = False;
UInt hwcaps = archinfo->hwcaps;
Long delta;
@@ -13344,21 +16499,24 @@
allow_FX = (0 != (hwcaps & VEX_HWCAPS_PPC64_FX));
allow_GX = (0 != (hwcaps & VEX_HWCAPS_PPC64_GX));
allow_VX = (0 != (hwcaps & VEX_HWCAPS_PPC64_VX));
+ allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC64_DFP));
} else {
allow_F = (0 != (hwcaps & VEX_HWCAPS_PPC32_F));
allow_V = (0 != (hwcaps & VEX_HWCAPS_PPC32_V));
allow_FX = (0 != (hwcaps & VEX_HWCAPS_PPC32_FX));
allow_GX = (0 != (hwcaps & VEX_HWCAPS_PPC32_GX));
allow_VX = (0 != (hwcaps & VEX_HWCAPS_PPC32_VX));
+ allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC32_DFP));
}
/* The running delta */
delta = (Long)mkSzAddr(ty, (ULong)delta64);
/* Set result defaults. */
- dres.whatNext = Dis_Continue;
- dres.len = 0;
- dres.continueAt = 0;
+ dres.whatNext = Dis_Continue;
+ dres.len = 0;
+ dres.continueAt = 0;
+ dres.jk_StopHere = Ijk_INVALID;
/* At least this is simple on PPC32: insns are all 4 bytes long, and
4-aligned. So just fish the whole thing out of memory right now
@@ -13369,10 +16527,6 @@
DIP("\t0x%llx: ", (ULong)guest_CIA_curr_instr);
- /* We may be asked to update the guest CIA before going further. */
- if (put_IP)
- putGST( PPC_GST_CIA, mkSzImm(ty, guest_CIA_curr_instr) );
-
/* Spot "Special" instructions (see comment at top of file). */
{
UChar* code = (UChar*)(guest_code + delta);
@@ -13401,9 +16555,9 @@
/* %R3 = client_request ( %R4 ) */
DIP("r3 = client_request ( %%r4 )\n");
delta += 20;
- irsb->next = mkSzImm( ty, guest_CIA_bbstart + delta );
- irsb->jumpkind = Ijk_ClientReq;
- dres.whatNext = Dis_StopHere;
+ putGST( PPC_GST_CIA, mkSzImm( ty, guest_CIA_bbstart + delta ));
+ dres.jk_StopHere = Ijk_ClientReq;
+ dres.whatNext = Dis_StopHere;
goto decode_success;
}
else
@@ -13421,9 +16575,9 @@
DIP("branch-and-link-to-noredir r11\n");
delta += 20;
putGST( PPC_GST_LR, mkSzImm(ty, guest_CIA_bbstart + (Long)delta) );
- irsb->next = getIReg(11);
- irsb->jumpkind = Ijk_NoRedir;
- dres.whatNext = Dis_StopHere;
+ putGST( PPC_GST_CIA, getIReg(11));
+ dres.jk_StopHere = Ijk_NoRedir;
+ dres.whatNext = Dis_StopHere;
goto decode_success;
}
else
@@ -13542,7 +16696,56 @@
case 0x3B:
if (!allow_F) goto decode_noF;
opc2 = ifieldOPClo10(theInstr);
+
switch (opc2) {
+ case 0x2: // dadd - DFP Add
+ case 0x202: // dsub - DFP Subtract
+ case 0x22: // dmul - DFP Mult
+ case 0x222: // ddiv - DFP Divide
+ if (!allow_DFP) goto decode_noDFP;
+ if (dis_dfp_arith( theInstr ))
+ goto decode_success;
+ case 0x82: // dcmpo, DFP comparison ordered instruction
+ case 0x282: // dcmpu, DFP comparison unordered instruction
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_compare( theInstr ) )
+ goto decode_success;
+ goto decode_failure;
+ case 0x102: // dctdp - DFP convert to DFP long
+ case 0x302: // drsp - DFP round to dfp short
+ case 0x122: // dctfix - DFP convert to fixed
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_fmt_conv( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+ case 0x322: // POWER 7 inst, dcffix - DFP convert from fixed
+ if (!allow_VX)
+ goto decode_failure;
+ if (dis_dfp_fmt_conv( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+ case 0x2A2: // dtstsf - DFP number of significant digits
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_significant_digits(theInstr))
+ goto decode_success;
+ goto decode_failure;
+ case 0x142: // ddedpd DFP Decode DPD to BCD
+ case 0x342: // denbcd DFP Encode BCD to DPD
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_bcd(theInstr))
+ goto decode_success;
+ goto decode_failure;
+ case 0x162: // dxex - Extract exponent
+ case 0x362: // diex - Insert exponent
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_extract_insert( theInstr ) )
+ goto decode_success;
+ goto decode_failure;
case 0x3CE: // fcfidus (implemented as native insn)
if (!allow_VX)
goto decode_noVX;
@@ -13555,6 +16758,52 @@
goto decode_failure;
}
+ opc2 = ifieldOPClo9( theInstr );
+ switch (opc2) {
+ case 0x42: // dscli, DFP shift left
+ case 0x62: // dscri, DFP shift right
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_shift( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+ case 0xc2: // dtstdc, DFP test data class
+ case 0xe2: // dtstdg, DFP test data group
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_class_test( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+ }
+
+ opc2 = ifieldOPClo8( theInstr );
+ switch (opc2) {
+ case 0x3: // dqua - DFP Quantize
+ case 0x23: // drrnd - DFP Reround
+ case 0x43: // dquai - DFP Quantize immediate
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_quantize_sig_rrnd( theInstr ) )
+ goto decode_success;
+ goto decode_failure;
+ case 0xA2: // dtstex - DFP Test exponent
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_exponent_test( theInstr ) )
+ goto decode_success;
+ goto decode_failure;
+ case 0x63: // drintx - Round to an integer value
+ case 0xE3: // drintn - Round to an integer value
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_round( theInstr ) ) {
+ goto decode_success;
+ }
+ goto decode_failure;
+ default:
+ break; /* fall through to next opc2 check */
+ }
+
opc2 = IFIELD(theInstr, 1, 5);
switch (opc2) {
/* Floating Point Arith Instructions */
@@ -13589,6 +16838,10 @@
case 0x3C: // VSX instructions (except load/store)
{
+ // All of these VSX instructions use some VMX facilities, so
+ // if allow_V is not set, we'll skip trying to decode.
+ if (!allow_V) goto decode_noVX;
+
UInt vsxOpc2 = get_VSX60_opc2(opc2);
/* The vsxOpc2 returned is the "normalized" value, representing the
* instructions secondary opcode as taken from the standard secondary
@@ -13654,10 +16907,21 @@
if (dis_vxv_sp_arith(theInstr, vsxOpc2)) goto decode_success;
goto decode_failure;
- case 0x2B0: case 0x2F0: case 0x2D0: // xscvdpsxds, xscvsxddp, xscvuxddp
+ case 0x2D0: case 0x3d0: // xscvuxddp, xvcvuxddp
+ case 0x350: case 0x1d0: // xvcvuxdsp, xvcvuxwdp
+ case 0x090: // xscvdpuxws
+ // The above VSX conversion instructions employ some ISA 2.06
+ // floating point conversion instructions under the covers,
+ // so if allow_VX (which means "supports ISA 2.06") is not set,
+ // we'll skip the decode.
+ if (!allow_VX) goto decode_noVX;
+ if (dis_vx_conv(theInstr, vsxOpc2)) goto decode_success;
+ goto decode_failure;
+
+ case 0x2B0: case 0x2F0: // xscvdpsxds, xscvsxddp
case 0x1b0: case 0x130: // xvcvdpsxws, xvcvspsxws
case 0x0b0: case 0x290: // xscvdpsxws, xscvdpuxds
- case 0x212: case 0x090: // xscvdpsp, xscvdpuxws
+ case 0x212: // xscvdpsp
case 0x292: case 0x312: // xscvspdp, xvcvdpsp
case 0x390: case 0x190: // xvcvdpuxds, xvcvdpuxws
case 0x3B0: case 0x310: // xvcvdpsxds, xvcvspuxds
@@ -13665,8 +16929,6 @@
case 0x110: case 0x3f0: // xvcvspuxws, xvcvsxddp
case 0x370: case 0x1f0: // xvcvsxdsp, xvcvsxwdp
case 0x170: case 0x150: // xvcvsxwsp, xvcvuxwsp
- case 0x3d0: case 0x350: // xvcvuxddp, xvcvuxdsp
- case 0x1d0: // xvcvuxwdp
if (dis_vx_conv(theInstr, vsxOpc2)) goto decode_success;
goto decode_failure;
@@ -13746,6 +17008,56 @@
opc2 = IFIELD(theInstr, 1, 10);
switch (opc2) {
+ /* 128-bit DFP instructions */
+ case 0x2: // daddq - DFP Add
+ case 0x202: // dsubq - DFP Subtract
+ case 0x22: // dmulq - DFP Mult
+ case 0x222: // ddivq - DFP Divide
+ if (!allow_DFP) goto decode_noDFP;
+ if (dis_dfp_arithq( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+ case 0x162: // dxexq - DFP Extract exponent
+ case 0x362: // diexq - DFP Insert exponent
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_extract_insertq( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+
+ case 0x82: // dcmpoq, DFP comparison ordered instruction
+ case 0x282: // dcmpuq, DFP comparison unordered instruction
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_compare( theInstr ) )
+ goto decode_success;
+ goto decode_failure;
+
+ case 0x102: // dctqpq - DFP convert to DFP extended
+ case 0x302: // drdpq - DFP round to dfp Long
+ case 0x122: // dctfixq - DFP convert to fixed quad
+ case 0x322: // dcffixq - DFP convert from fixed quad
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_fmt_convq( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+
+ case 0x2A2: // dtstsfq - DFP number of significant digits
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_significant_digits(theInstr))
+ goto decode_success;
+ goto decode_failure;
+
+ case 0x142: // ddedpdq DFP Decode DPD to BCD
+ case 0x342: // denbcdq DFP Encode BCD to DPD
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_bcdq(theInstr))
+ goto decode_success;
+ goto decode_failure;
+
/* Floating Point Compare Instructions */
case 0x000: // fcmpu
case 0x020: // fcmpo
@@ -13799,14 +17111,62 @@
case 0x086: // mtfsfi
case 0x247: // mffs
case 0x2C7: // mtfsf
- if (dis_fp_scr( theInstr )) goto decode_success;
+ // Some of the above instructions need to know more about the
+ // ISA level supported by the host.
+ if (dis_fp_scr( theInstr, allow_GX )) goto decode_success;
+ goto decode_failure;
+
+ default:
+ break; // Fall through...
+ }
+
+ opc2 = ifieldOPClo9( theInstr );
+ switch (opc2) {
+ case 0x42: // dscli, DFP shift left
+ case 0x62: // dscri, DFP shift right
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_shiftq( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+ case 0xc2: // dtstdc, DFP test data class
+ case 0xe2: // dtstdg, DFP test data group
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_class_test( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+ default:
+ break;
+ }
+
+ opc2 = ifieldOPClo8( theInstr );
+ switch (opc2) {
+ case 0x3: // dquaq - DFP Quantize Quad
+ case 0x23: // drrndq - DFP Reround Quad
+ case 0x43: // dquaiq - DFP Quantize immediate Quad
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_quantize_sig_rrndq( theInstr ))
+ goto decode_success;
+ goto decode_failure;
+ case 0xA2: // dtstexq - DFP Test exponent Quad
+ if (dis_dfp_exponent_test( theInstr ) )
+ goto decode_success;
+ goto decode_failure;
+ case 0x63: // drintxq - DFP Round to an integer value
+ case 0xE3: // drintnq - DFP Round to an integer value
+ if (!allow_DFP)
+ goto decode_failure;
+ if (dis_dfp_roundq( theInstr ))
+ goto decode_success;
goto decode_failure;
default:
goto decode_failure;
}
break;
-
+
case 0x13:
switch (opc2) {
@@ -13962,9 +17322,9 @@
Bool ok = dis_int_ldst_str( theInstr, &stopHere );
if (!ok) goto decode_failure;
if (stopHere) {
- irsb->next = mkSzImm(ty, nextInsnAddr());
- irsb->jumpkind = Ijk_Boring;
- dres.whatNext = Dis_StopHere;
+ putGST( PPC_GST_CIA, mkSzImm(ty, nextInsnAddr()) );
+ dres.jk_StopHere = Ijk_Boring;
+ dres.whatNext = Dis_StopHere;
}
goto decode_success;
}
@@ -14069,6 +17429,10 @@
case 0x34C: // lxvd2x
case 0x14C: // lxvdsx
case 0x30C: // lxvw4x
+ // All of these VSX load instructions use some VMX facilities, so
+ // if allow_V is not set, we'll skip trying to decode.
+ if (!allow_V) goto decode_noV;
+
if (dis_vx_load( theInstr )) goto decode_success;
goto decode_failure;
@@ -14076,12 +17440,17 @@
case 0x2CC: // stxsdx
case 0x3CC: // stxvd2x
case 0x38C: // stxvw4x
+ // All of these VSX store instructions use some VMX facilities, so
+ // if allow_V is not set, we'll skip trying to decode.
+ if (!allow_V) goto decode_noV;
+
if (dis_vx_store( theInstr )) goto decode_success;
goto decode_failure;
/* Miscellaneous ISA 2.06 instructions */
case 0x1FA: // popcntd
case 0x17A: // popcntw
+ case 0x7A: // popcntb
if (dis_int_logic( theInstr )) goto decode_success;
goto decode_failure;
@@ -14288,6 +17657,12 @@
vex_printf("disInstr(ppc): "
"declined to decode a Graphics-Optional insn.\n");
goto decode_failure;
+ decode_noDFP:
+ vassert(!allow_DFP);
+ vex_printf("disInstr(ppc): "
+ "declined to decode a Decimal Floating Point insn.\n");
+ goto decode_failure;
+
decode_failure:
/* All decode failures end up here. */
@@ -14303,16 +17678,28 @@
insn, but nevertheless be paranoid and update it again right
now. */
putGST( PPC_GST_CIA, mkSzImm(ty, guest_CIA_curr_instr) );
- irsb->next = mkSzImm(ty, guest_CIA_curr_instr);
- irsb->jumpkind = Ijk_NoDecode;
- dres.whatNext = Dis_StopHere;
- dres.len = 0;
+ dres.whatNext = Dis_StopHere;
+ dres.jk_StopHere = Ijk_NoDecode;
+ dres.len = 0;
return dres;
} /* switch (opc) for the main (primary) opcode switch. */
decode_success:
/* All decode successes end up here. */
+ switch (dres.whatNext) {
+ case Dis_Continue:
+ putGST( PPC_GST_CIA, mkSzImm(ty, guest_CIA_curr_instr + 4));
+ break;
+ case Dis_ResteerU:
+ case Dis_ResteerC:
+ putGST( PPC_GST_CIA, mkSzImm(ty, dres.continueAt));
+ break;
+ case Dis_StopHere:
+ break;
+ default:
+ vassert(0);
+ }
DIP("\n");
if (dres.len == 0) {
@@ -14335,7 +17722,6 @@
is located in host memory at &guest_code[delta]. */
DisResult disInstr_PPC ( IRSB* irsb_IN,
- Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -14360,10 +17746,11 @@
/* do some sanity checks */
mask32 = VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V
- | VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX | VEX_HWCAPS_PPC32_VX;
+ | VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX | VEX_HWCAPS_PPC32_VX
+ | VEX_HWCAPS_PPC32_DFP;
mask64 = VEX_HWCAPS_PPC64_V | VEX_HWCAPS_PPC64_FX
- | VEX_HWCAPS_PPC64_GX | VEX_HWCAPS_PPC64_VX;
+ | VEX_HWCAPS_PPC64_GX | VEX_HWCAPS_PPC64_VX | VEX_HWCAPS_PPC64_DFP;
if (mode64) {
vassert((hwcaps_guest & mask32) == 0);
@@ -14379,8 +17766,7 @@
guest_CIA_curr_instr = mkSzAddr(ty, guest_IP);
guest_CIA_bbstart = mkSzAddr(ty, guest_IP - delta);
- dres = disInstr_PPC_WRK ( put_IP,
- resteerOkFn, resteerCisOk, callback_opaque,
+ dres = disInstr_PPC_WRK ( resteerOkFn, resteerCisOk, callback_opaque,
delta, archinfo, abiinfo );
return dres;
diff --git a/main/VEX/priv/guest_s390_defs.h b/main/VEX/priv/guest_s390_defs.h
index 3c38955..1d771af 100644
--- a/main/VEX/priv/guest_s390_defs.h
+++ b/main/VEX/priv/guest_s390_defs.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -37,12 +37,12 @@
#include "libvex_ir.h" // IRSB (needed by bb_to_IR.h)
#include "libvex.h" // VexArch (needed by bb_to_IR.h)
#include "guest_generic_bb_to_IR.h" // DisResult
+#include "libvex_guest_s390x.h" // VexGuestS390XState
/* Convert one s390 insn to IR. See the type DisOneInstrFn in
bb_to_IR.h. */
DisResult disInstr_S390 ( IRSB* irbb,
- Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -72,14 +72,26 @@
#define S390X_GUEST_OFFSET(x) offsetof(VexGuestS390XState, x)
/*------------------------------------------------------------*/
-/*--- Dirty Helper functions. ---*/
+/*--- Helper functions. ---*/
/*------------------------------------------------------------*/
-void s390x_dirtyhelper_00(VexGuestS390XState *guest_state);
void s390x_dirtyhelper_EX(ULong torun);
ULong s390x_dirtyhelper_STCK(ULong *addr);
ULong s390x_dirtyhelper_STCKF(ULong *addr);
ULong s390x_dirtyhelper_STCKE(ULong *addr);
-ULong s390x_dirtyhelper_STFLE(VexGuestS390XState *guest_state, HWord addr);
+ULong s390x_dirtyhelper_STFLE(VexGuestS390XState *guest_state, ULong *addr);
+void s390x_dirtyhelper_CUxy(UChar *addr, ULong data, ULong num_bytes);
+
+ULong s390_do_cu12_cu14_helper1(UInt byte1, UInt etf3_and_m3_is_1);
+ULong s390_do_cu12_helper2(UInt byte1, UInt byte2, UInt byte3, UInt byte4,
+ ULong stuff);
+ULong s390_do_cu14_helper2(UInt byte1, UInt byte2, UInt byte3, UInt byte4,
+ ULong stuff);
+ULong s390_do_cu21(UInt srcvalue, UInt low_surrogate);
+ULong s390_do_cu24(UInt srcvalue, UInt low_surrogate);
+ULong s390_do_cu41(UInt srcvalue);
+ULong s390_do_cu42(UInt srcvalue);
+UInt s390_do_cvb(ULong decimal);
+ULong s390_do_cvd(ULong binary);
/* The various ways to compute the condition code. */
enum {
@@ -101,25 +113,24 @@
S390_CC_OP_LOAD_AND_TEST = 15,
S390_CC_OP_LOAD_POSITIVE_32 = 16,
S390_CC_OP_LOAD_POSITIVE_64 = 17,
- S390_CC_OP_TEST_AND_SET = 18,
- S390_CC_OP_TEST_UNDER_MASK_8 = 19,
- S390_CC_OP_TEST_UNDER_MASK_16 = 20,
- S390_CC_OP_SHIFT_LEFT_32 = 21,
- S390_CC_OP_SHIFT_LEFT_64 = 22,
- S390_CC_OP_INSERT_CHAR_MASK_32 = 23,
- S390_CC_OP_BFP_RESULT_32 = 24,
- S390_CC_OP_BFP_RESULT_64 = 25,
- S390_CC_OP_BFP_RESULT_128 = 26,
- S390_CC_OP_BFP_32_TO_INT_32 = 27,
- S390_CC_OP_BFP_64_TO_INT_32 = 28,
- S390_CC_OP_BFP_128_TO_INT_32 = 29,
- S390_CC_OP_BFP_32_TO_INT_64 = 30,
- S390_CC_OP_BFP_64_TO_INT_64 = 31,
- S390_CC_OP_BFP_128_TO_INT_64 = 32,
- S390_CC_OP_BFP_TDC_32 = 33,
- S390_CC_OP_BFP_TDC_64 = 34,
- S390_CC_OP_BFP_TDC_128 = 35,
- S390_CC_OP_SET = 36
+ S390_CC_OP_TEST_UNDER_MASK_8 = 18,
+ S390_CC_OP_TEST_UNDER_MASK_16 = 19,
+ S390_CC_OP_SHIFT_LEFT_32 = 20,
+ S390_CC_OP_SHIFT_LEFT_64 = 21,
+ S390_CC_OP_INSERT_CHAR_MASK_32 = 22,
+ S390_CC_OP_BFP_RESULT_32 = 23,
+ S390_CC_OP_BFP_RESULT_64 = 24,
+ S390_CC_OP_BFP_RESULT_128 = 25,
+ S390_CC_OP_BFP_32_TO_INT_32 = 26,
+ S390_CC_OP_BFP_64_TO_INT_32 = 27,
+ S390_CC_OP_BFP_128_TO_INT_32 = 28,
+ S390_CC_OP_BFP_32_TO_INT_64 = 29,
+ S390_CC_OP_BFP_64_TO_INT_64 = 30,
+ S390_CC_OP_BFP_128_TO_INT_64 = 31,
+ S390_CC_OP_BFP_TDC_32 = 32,
+ S390_CC_OP_BFP_TDC_64 = 33,
+ S390_CC_OP_BFP_TDC_128 = 34,
+ S390_CC_OP_SET = 35
};
/*------------------------------------------------------------*/
@@ -152,7 +163,6 @@
| S390_CC_OP_LOAD_AND_TEST | S loaded value | | |
| S390_CC_OP_LOAD_POSITIVE_32 | S loaded value | | |
| S390_CC_OP_LOAD_POSITIVE_64 | S loaded value | | |
- | S390_CC_OP_TEST_AND_SET | Z tested value | | |
| S390_CC_OP_TEST_UNDER_MASK_8 | Z tested value | Z mask | |
| S390_CC_OP_TEST_UNDER_MASK_16 | Z tested value | Z mask | |
| S390_CC_OP_SHIFT_LEFT_32 | Z value to be shifted | Z shift amount | |
@@ -179,7 +189,6 @@
/*------------------------------------------------------------*/
UInt s390_calculate_cc(ULong cc_op, ULong cc_dep1, ULong cc_dep2,
ULong cc_ndep);
-UInt s390_calculate_icc(ULong op, ULong dep1, ULong dep2);
UInt s390_calculate_cond(ULong mask, ULong op, ULong dep1, ULong dep2,
ULong ndep);
diff --git a/main/VEX/priv/guest_s390_helpers.c b/main/VEX/priv/guest_s390_helpers.c
index 60149f0..08deb64 100644
--- a/main/VEX/priv/guest_s390_helpers.c
+++ b/main/VEX/priv/guest_s390_helpers.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -130,6 +130,8 @@
state->guest_TILEN = 0;
state->guest_IP_AT_SYSCALL = 0;
state->guest_EMWARN = EmWarn_NONE;
+ state->host_EvC_COUNTER = 0;
+ state->host_EvC_FAILADDR = 0;
/*------------------------------------------------------------*/
/*--- Initialise thunk ---*/
@@ -139,6 +141,8 @@
state->guest_CC_DEP1 = 0;
state->guest_CC_DEP2 = 0;
state->guest_CC_NDEP = 0;
+
+ __builtin_memset(state->padding, 0x0, sizeof(state->padding));
}
@@ -227,23 +231,6 @@
};
/*------------------------------------------------------------*/
-/*--- Dirty helper for invalid opcode 00 ---*/
-/*------------------------------------------------------------*/
-#if defined(VGA_s390x)
-void
-s390x_dirtyhelper_00(VexGuestS390XState *guest_state)
-{
- /* Avoid infinite loop in case SIGILL is caught. See also
- none/tests/s390x/op_exception.c */
- guest_state->guest_IA += 2;
-
- asm volatile(".hword 0\n");
-}
-#else
-void s390x_dirtyhelper_00(VexGuestS390XState *guest_state) { }
-#endif
-
-/*------------------------------------------------------------*/
/*--- Dirty helper for EXecute ---*/
/*------------------------------------------------------------*/
void
@@ -257,7 +244,8 @@
/*--- Dirty helper for Clock instructions ---*/
/*------------------------------------------------------------*/
#if defined(VGA_s390x)
-ULong s390x_dirtyhelper_STCK(ULong *addr)
+ULong
+s390x_dirtyhelper_STCK(ULong *addr)
{
int cc;
@@ -268,7 +256,8 @@
return cc;
}
-ULong s390x_dirtyhelper_STCKE(ULong *addr)
+ULong
+s390x_dirtyhelper_STCKE(ULong *addr)
{
int cc;
@@ -300,7 +289,7 @@
/*------------------------------------------------------------*/
#if defined(VGA_s390x)
ULong
-s390x_dirtyhelper_STFLE(VexGuestS390XState *guest_state, HWord addr)
+s390x_dirtyhelper_STFLE(VexGuestS390XState *guest_state, ULong *addr)
{
ULong hoststfle[S390_NUM_FACILITY_DW], cc, num_dw, i;
register ULong reg0 asm("0") = guest_state->guest_r0 & 0xF; /* r0[56:63] */
@@ -321,7 +310,7 @@
guest_state->guest_r0 = reg0;
for (i = 0; i < num_dw; ++i)
- ((ULong *)addr)[i] = hoststfle[i];
+ addr[i] = hoststfle[i];
return cc;
}
@@ -329,13 +318,535 @@
#else
ULong
-s390x_dirtyhelper_STFLE(VexGuestS390XState *guest_state, HWord addr)
+s390x_dirtyhelper_STFLE(VexGuestS390XState *guest_state, ULong *addr)
{
return 3;
}
#endif /* VGA_s390x */
/*------------------------------------------------------------*/
+/*--- Dirty helper for the "convert unicode" insn family. ---*/
+/*------------------------------------------------------------*/
+void
+s390x_dirtyhelper_CUxy(UChar *address, ULong data, ULong num_bytes)
+{
+ UInt i;
+
+ vassert(num_bytes >= 1 && num_bytes <= 4);
+
+ /* Store the least significant NUM_BYTES bytes in DATA left to right
+ at ADDRESS. */
+ for (i = 1; i <= num_bytes; ++i) {
+ address[num_bytes - i] = data & 0xff;
+ data >>= 8;
+ }
+}
+
+
+/*------------------------------------------------------------*/
+/*--- Clean helper for CU21. ---*/
+/*------------------------------------------------------------*/
+
+/* The function performs a CU21 operation. It returns three things
+ encoded in an ULong value:
+ - the converted bytes (at most 4)
+ - the number of converted bytes
+ - an indication whether LOW_SURROGATE, if any, is invalid
+
+ 64 48 16 8 0
+ +-------+-----------------+-----------+-----------------------+
+ | 0x0 | converted bytes | num_bytes | invalid_low_surrogate |
+ +-------+-----------------+-----------+-----------------------+
+*/
+ULong
+s390_do_cu21(UInt srcval, UInt low_surrogate)
+{
+ ULong retval = 0; // shut up gcc
+ UInt b1, b2, b3, b4, num_bytes, invalid_low_surrogate = 0;
+
+ srcval &= 0xffff;
+
+ /* Determine the number of bytes in the converted value */
+ if (srcval <= 0x007f)
+ num_bytes = 1;
+ else if (srcval >= 0x0080 && srcval <= 0x07ff)
+ num_bytes = 2;
+ else if ((srcval >= 0x0800 && srcval <= 0xd7ff) ||
+ (srcval >= 0xdc00 && srcval <= 0xffff))
+ num_bytes = 3;
+ else
+ num_bytes = 4;
+
+ /* Determine UTF-8 bytes according to calculated num_bytes */
+ switch (num_bytes){
+ case 1:
+ retval = srcval;
+ break;
+
+ case 2:
+ /* order of bytes left to right: b1, b2 */
+ b1 = 0xc0;
+ b1 |= srcval >> 6;
+
+ b2 = 0x80;
+ b2 |= srcval & 0x3f;
+
+ retval = (b1 << 8) | b2;
+ break;
+
+ case 3:
+ /* order of bytes left to right: b1, b2, b3 */
+ b1 = 0xe0;
+ b1 |= srcval >> 12;
+
+ b2 = 0x80;
+ b2 |= (srcval >> 6) & 0x3f;
+
+ b3 = 0x80;
+ b3 |= srcval & 0x3f;
+
+ retval = (b1 << 16) | (b2 << 8) | b3;
+ break;
+
+ case 4: {
+ /* order of bytes left to right: b1, b2, b3, b4 */
+ UInt high_surrogate = srcval;
+ UInt uvwxy = ((high_surrogate >> 6) & 0xf) + 1; // abcd + 1
+
+ b1 = 0xf0;
+ b1 |= uvwxy >> 2; // uvw
+
+ b2 = 0x80;
+ b2 |= (uvwxy & 0x3) << 4; // xy
+ b2 |= (high_surrogate >> 2) & 0xf; // efgh
+
+ b3 = 0x80;
+ b3 |= (high_surrogate & 0x3) << 4; // ij
+ b3 |= (low_surrogate >> 6) & 0xf; // klmn
+
+ b4 = 0x80;
+ b4 |= low_surrogate & 0x3f;
+
+ retval = (b1 << 24) | (b2 << 16) | (b3 << 8) | b4;
+
+ invalid_low_surrogate = (low_surrogate & 0xfc00) != 0xdc00;
+ break;
+ }
+ }
+
+ /* At this point RETVAL contains the converted bytes.
+ Build up the final return value. */
+ return (retval << 16) | (num_bytes << 8) | invalid_low_surrogate;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- Clean helper for CU24. ---*/
+/*------------------------------------------------------------*/
+
+/* The function performs a CU24 operation. It returns two things
+ encoded in an ULong value:
+ - the 4 converted bytes
+ - an indication whether LOW_SURROGATE, if any, is invalid
+
+ 64 40 8 0
+ +------------------------+-----------------------+
+ | 0x0 | converted bytes | invalid_low_surrogate |
+ +------------------------+-----------------------+
+*/
+ULong
+s390_do_cu24(UInt srcval, UInt low_surrogate)
+{
+ ULong retval;
+ UInt invalid_low_surrogate = 0;
+
+ srcval &= 0xffff;
+
+ if ((srcval >= 0x0000 && srcval <= 0xd7ff) ||
+ (srcval >= 0xdc00 && srcval <= 0xffff)) {
+ retval = srcval;
+ } else {
+ /* D800 - DBFF */
+ UInt high_surrogate = srcval;
+ UInt uvwxy = ((high_surrogate >> 6) & 0xf) + 1; // abcd + 1
+ UInt efghij = high_surrogate & 0x3f;
+ UInt klmnoprst = low_surrogate & 0x3ff;
+
+ retval = (uvwxy << 16) | (efghij << 10) | klmnoprst;
+
+ invalid_low_surrogate = (low_surrogate & 0xfc00) != 0xdc00;
+ }
+
+ /* At this point RETVAL contains the converted bytes.
+ Build up the final return value. */
+ return (retval << 8) | invalid_low_surrogate;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- Clean helper for CU42. ---*/
+/*------------------------------------------------------------*/
+
+/* The function performs a CU42 operation. It returns three things
+ encoded in an ULong value:
+ - the converted bytes (at most 4)
+ - the number of converted bytes (2 or 4; 0 if invalid character)
+ - an indication whether the UTF-32 character is invalid
+
+ 64 48 16 8 0
+ +-------+-----------------+-----------+-------------------+
+ | 0x0 | converted bytes | num_bytes | invalid_character |
+ +-------+-----------------+-----------+-------------------+
+*/
+ULong
+s390_do_cu42(UInt srcval)
+{
+ ULong retval;
+ UInt num_bytes, invalid_character = 0;
+
+ if ((srcval >= 0x0000 && srcval <= 0xd7ff) ||
+ (srcval >= 0xdc00 && srcval <= 0xffff)) {
+ retval = srcval;
+ num_bytes = 2;
+ } else if (srcval >= 0x00010000 && srcval <= 0x0010FFFF) {
+ UInt uvwxy = srcval >> 16;
+ UInt abcd = (uvwxy - 1) & 0xf;
+ UInt efghij = (srcval >> 10) & 0x3f;
+
+ UInt high_surrogate = (0xd8 << 8) | (abcd << 6) | efghij;
+ UInt low_surrogate = (0xdc << 8) | (srcval & 0x3ff);
+
+ retval = (high_surrogate << 16) | low_surrogate;
+ num_bytes = 4;
+ } else {
+ /* D800 - DBFF or 00110000 - FFFFFFFF */
+ invalid_character = 1;
+ retval = num_bytes = 0; /* does not matter; not used */
+ }
+
+ /* At this point RETVAL contains the converted bytes.
+ Build up the final return value. */
+ return (retval << 16) | (num_bytes << 8) | invalid_character;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- Clean helper for CU41. ---*/
+/*------------------------------------------------------------*/
+
+/* The function performs a CU41 operation. It returns three things
+ encoded in an ULong value:
+ - the converted bytes (at most 4)
+ - the number of converted bytes (1, 2, 3, or 4; 0 if invalid character)
+ - an indication whether the UTF-32 character is invalid
+
+ 64 48 16 8 0
+ +-------+-----------------+-----------+-------------------+
+ | 0x0 | converted bytes | num_bytes | invalid_character |
+ +-------+-----------------+-----------+-------------------+
+*/
+ULong
+s390_do_cu41(UInt srcval)
+{
+ ULong retval;
+ UInt num_bytes, invalid_character = 0;
+
+ if (srcval <= 0x7f) {
+ retval = srcval;
+ num_bytes = 1;
+ } else if (srcval >= 0x80 && srcval <= 0x7ff) {
+ UInt fghij = srcval >> 6;
+ UInt klmnop = srcval & 0x3f;
+ UInt byte1 = (0xc0 | fghij);
+ UInt byte2 = (0x80 | klmnop);
+
+ retval = (byte1 << 8) | byte2;
+ num_bytes = 2;
+ } else if ((srcval >= 0x800 && srcval <= 0xd7ff) ||
+ (srcval >= 0xdc00 && srcval <= 0xffff)) {
+ UInt abcd = srcval >> 12;
+ UInt efghij = (srcval >> 6) & 0x3f;
+ UInt klmnop = srcval & 0x3f;
+ UInt byte1 = 0xe0 | abcd;
+ UInt byte2 = 0x80 | efghij;
+ UInt byte3 = 0x80 | klmnop;
+
+ retval = (byte1 << 16) | (byte2 << 8) | byte3;
+ num_bytes = 3;
+ } else if (srcval >= 0x10000 && srcval <= 0x10ffff) {
+ UInt uvw = (srcval >> 18) & 0x7;
+ UInt xy = (srcval >> 16) & 0x3;
+ UInt efgh = (srcval >> 12) & 0xf;
+ UInt ijklmn = (srcval >> 6) & 0x3f;
+ UInt opqrst = srcval & 0x3f;
+ UInt byte1 = 0xf0 | uvw;
+ UInt byte2 = 0x80 | (xy << 4) | efgh;
+ UInt byte3 = 0x80 | ijklmn;
+ UInt byte4 = 0x80 | opqrst;
+
+ retval = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
+ num_bytes = 4;
+ } else {
+ /* d800 ... dbff or 00110000 ... ffffffff */
+ invalid_character = 1;
+
+ retval = 0;
+ num_bytes = 0;
+ }
+
+ /* At this point RETVAL contains the converted bytes.
+ Build up the final return value. */
+ return (retval << 16) | (num_bytes << 8) | invalid_character;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- Clean helpers for CU12. ---*/
+/*------------------------------------------------------------*/
+
+/* The function looks at the first byte of an UTF-8 character and returns
+ two things encoded in an ULong value:
+
+ - the number of bytes that need to be read
+ - an indication whether the UTF-8 character is invalid
+
+ 64 16 8 0
+ +-------------------+-------------------+
+ | 0x0 | num_bytes | invalid_character |
+ +-------+-----------+-------------------+
+*/
+ULong
+s390_do_cu12_cu14_helper1(UInt byte, UInt etf3_and_m3_is_1)
+{
+ vassert(byte <= 0xff);
+
+ /* Check whether the character is invalid */
+ if (byte >= 0x80 && byte <= 0xbf) return 1;
+ if (byte >= 0xf8) return 1;
+
+ if (etf3_and_m3_is_1) {
+ if (byte == 0xc0 || byte == 0xc1) return 1;
+ if (byte >= 0xf5 && byte <= 0xf7) return 1;
+ }
+
+ /* Character is valid */
+ if (byte <= 0x7f) return 1 << 8; // 1 byte
+ if (byte <= 0xdf) return 2 << 8; // 2 bytes
+ if (byte <= 0xef) return 3 << 8; // 3 bytes
+
+ return 4 << 8; // 4 bytes
+}
+
+/* The function performs a CU12 or CU14 operation. BYTE1, BYTE2, etc are the
+ bytes as read from the input stream, left to right. BYTE1 is a valid
+ byte. The function returns three things encoded in an ULong value:
+
+ - the converted bytes
+ - the number of converted bytes (2 or 4; 0 if invalid character)
+ - an indication whether the UTF-16 character is invalid
+
+ 64 48 16 8 0
+ +-------+-----------------+-----------+-------------------+
+ | 0x0 | converted bytes | num_bytes | invalid_character |
+ +-------+-----------------+-----------+-------------------+
+*/
+static ULong
+s390_do_cu12_cu14_helper2(UInt byte1, UInt byte2, UInt byte3, UInt byte4,
+ ULong stuff, Bool is_cu12)
+{
+ UInt num_src_bytes = stuff >> 1, etf3_and_m3_is_1 = stuff & 0x1;
+ UInt num_bytes = 0, invalid_character = 0;
+ ULong retval = 0;
+
+ vassert(num_src_bytes <= 4);
+
+ switch (num_src_bytes) {
+ case 1:
+ num_bytes = 2;
+ retval = byte1;
+ break;
+
+ case 2: {
+ /* Test validity */
+ if (etf3_and_m3_is_1) {
+ if (byte2 < 0x80 || byte2 > 0xbf) {
+ invalid_character = 1;
+ break;
+ }
+ }
+
+ /* OK */
+ UInt fghij = byte1 & 0x1f;
+ UInt klmnop = byte2 & 0x3f;
+
+ num_bytes = 2;
+ retval = (fghij << 6) | klmnop;
+ break;
+ }
+
+ case 3: {
+ /* Test validity */
+ if (etf3_and_m3_is_1) {
+ if (byte1 == 0xe0) {
+ if ((byte2 < 0xa0 || byte2 > 0xbf) ||
+ (byte3 < 0x80 || byte3 > 0xbf)) {
+ invalid_character = 1;
+ break;
+ }
+ }
+ if ((byte1 >= 0xe1 && byte1 <= 0xec) ||
+ byte1 == 0xee || byte1 == 0xef) {
+ if ((byte2 < 0x80 || byte2 > 0xbf) ||
+ (byte3 < 0x80 || byte3 > 0xbf)) {
+ invalid_character = 1;
+ break;
+ }
+ }
+ if (byte1 == 0xed) {
+ if ((byte2 < 0x80 || byte2 > 0x9f) ||
+ (byte3 < 0x80 || byte3 > 0xbf)) {
+ invalid_character = 1;
+ break;
+ }
+ }
+ }
+
+ /* OK */
+ UInt abcd = byte1 & 0xf;
+ UInt efghij = byte2 & 0x3f;
+ UInt klmnop = byte3 & 0x3f;
+
+ num_bytes = 2;
+ retval = (abcd << 12) | (efghij << 6) | klmnop;
+ break;
+ }
+
+ case 4: {
+ /* Test validity */
+ if (etf3_and_m3_is_1) {
+ if (byte1 == 0xf0) {
+ if ((byte2 < 0x90 || byte2 > 0xbf) ||
+ (byte3 < 0x80 || byte3 > 0xbf) ||
+ (byte4 < 0x80 || byte4 > 0xbf)) {
+ invalid_character = 1;
+ break;
+ }
+ }
+ if (byte1 == 0xf1 || byte1 == 0xf2 || byte1 == 0xf3) {
+ if ((byte2 < 0x80 || byte2 > 0xbf) ||
+ (byte3 < 0x80 || byte3 > 0xbf) ||
+ (byte4 < 0x80 || byte4 > 0xbf)) {
+ invalid_character = 1;
+ break;
+ }
+ }
+ if (byte1 == 0xf4) {
+ if ((byte2 < 0x80 || byte2 > 0x8f) ||
+ (byte3 < 0x80 || byte3 > 0xbf) ||
+ (byte4 < 0x80 || byte4 > 0xbf)) {
+ invalid_character = 1;
+ break;
+ }
+ }
+ }
+
+ /* OK */
+ UInt uvw = byte1 & 0x7;
+ UInt xy = (byte2 >> 4) & 0x3;
+ UInt uvwxy = (uvw << 2) | xy;
+ UInt efgh = byte2 & 0xf;
+ UInt ij = (byte3 >> 4) & 0x3;
+ UInt klmn = byte3 & 0xf;
+ UInt opqrst = byte4 & 0x3f;
+
+ if (is_cu12) {
+ UInt abcd = (uvwxy - 1) & 0xf;
+ UInt high_surrogate = (0xd8 << 8) | (abcd << 6) | (efgh << 2) | ij;
+ UInt low_surrogate = (0xdc << 8) | (klmn << 6) | opqrst;
+
+ num_bytes = 4;
+ retval = (high_surrogate << 16) | low_surrogate;
+ } else {
+ num_bytes = 4;
+ retval =
+ (uvwxy << 16) | (efgh << 12) | (ij << 10) | (klmn << 6) | opqrst;
+ }
+ break;
+ }
+ }
+
+ if (! is_cu12) num_bytes = 4; // for CU14, by definition
+
+ /* At this point RETVAL contains the converted bytes.
+ Build up the final return value. */
+ return (retval << 16) | (num_bytes << 8) | invalid_character;
+}
+
+ULong
+s390_do_cu12_helper2(UInt byte1, UInt byte2, UInt byte3, UInt byte4,
+ ULong stuff)
+{
+ return s390_do_cu12_cu14_helper2(byte1, byte2, byte3, byte4, stuff,
+ /* is_cu12 = */ 1);
+}
+
+ULong
+s390_do_cu14_helper2(UInt byte1, UInt byte2, UInt byte3, UInt byte4,
+ ULong stuff)
+{
+ return s390_do_cu12_cu14_helper2(byte1, byte2, byte3, byte4, stuff,
+ /* is_cu12 = */ 0);
+}
+
+
+/*------------------------------------------------------------*/
+/*--- Clean helper for "convert to binary". ---*/
+/*------------------------------------------------------------*/
+#if defined(VGA_s390x)
+UInt
+s390_do_cvb(ULong decimal)
+{
+ UInt binary;
+
+ __asm__ volatile (
+ "cvb %[result],%[input]\n\t"
+ : [result] "=d"(binary)
+ : [input] "m"(decimal)
+ );
+
+ return binary;
+}
+
+#else
+UInt s390_do_cvb(ULong decimal) { return 0; }
+#endif
+
+
+/*------------------------------------------------------------*/
+/*--- Clean helper for "convert to decimal". ---*/
+/*------------------------------------------------------------*/
+#if defined(VGA_s390x)
+ULong
+s390_do_cvd(ULong binary_in)
+{
+ UInt binary = binary_in & 0xffffffffULL;
+ ULong decimal;
+
+ __asm__ volatile (
+ "cvd %[input],%[result]\n\t"
+ : [result] "=m"(decimal)
+ : [input] "d"(binary)
+ );
+
+ return decimal;
+}
+
+#else
+ULong s390_do_cvd(ULong binary) { return 0; }
+#endif
+
+
+/*------------------------------------------------------------*/
/*--- Helper for condition code. ---*/
/*------------------------------------------------------------*/
@@ -512,25 +1023,20 @@
/* Like signed comparison with 0 */
return S390_CC_FOR_BINARY("cgr", cc_dep1, (Long)0);
- case S390_CC_OP_TEST_AND_SET:
- /* Shift the sign bit into the LSB. Note, that the tested value is an
- 8-bit value which has been zero-extended to 32/64 bit. */
- return cc_dep1 >> 7;
-
case S390_CC_OP_LOAD_POSITIVE_32:
__asm__ volatile (
"lpr %[result],%[op]\n\t"
- "ipm %[psw]\n\t" : [psw] "=d"(psw), [result] "=d"(cc_dep1)
- : [op] "d"(cc_dep1)
- : "cc");
+ "ipm %[psw]\n\t" : [psw] "=d"(psw), [result] "=d"(cc_dep1)
+ : [op] "d"(cc_dep1)
+ : "cc");
return psw >> 28; /* cc */
case S390_CC_OP_LOAD_POSITIVE_64:
__asm__ volatile (
"lpgr %[result],%[op]\n\t"
- "ipm %[psw]\n\t" : [psw] "=d"(psw), [result] "=d"(cc_dep1)
- : [op] "d"(cc_dep1)
- : "cc");
+ "ipm %[psw]\n\t" : [psw] "=d"(psw), [result] "=d"(cc_dep1)
+ : [op] "d"(cc_dep1)
+ : "cc");
return psw >> 28; /* cc */
case S390_CC_OP_TEST_UNDER_MASK_8: {
@@ -578,7 +1084,8 @@
"lr 2,%[high]\n\t"
"lr 3,%[low]\n\t"
"slda 2,0(%[amount])\n\t"
- "ipm %[psw]\n\t" : [psw] "=d"(psw), [high] "+d"(high), [low] "+d"(low)
+ "ipm %[psw]\n\t" : [psw] "=d"(psw), [high] "+d"(high),
+ [low] "+d"(low)
: [amount] "a"(cc_dep2)
: "cc", "r2", "r3");
return psw >> 28; /* cc */
@@ -659,13 +1166,6 @@
}
-UInt
-s390_calculate_icc(ULong op, ULong dep1, ULong dep2)
-{
- return s390_calculate_cc(op, dep1, dep2, 0 /* unused */);
-}
-
-
/* Note that this does *not* return a Boolean value. The result needs to be
explicitly tested against zero. */
UInt
@@ -1231,26 +1731,6 @@
mkU64(0)));
}
- /* S390_CC_OP_TEST_AND_SET */
- if (cc_op == S390_CC_OP_TEST_AND_SET) {
- /* cc_dep1 is the zero-extended loaded value
-
- cc == 0 --> leftmost bit is zero (cond == 8)
- cc == 1 --> leftmost bit is one (cond == 4)
-
- As cc is either 0 or 1, only the two leftmost bits of the mask
- are relevant. */
- IRExpr *bit = binop(Iop_Shr64, cc_dep1, mkU8(7));
-
- switch (cond & (8 + 4)) {
- case 0: return mkU32(0);
- case 4: return unop(Iop_1Uto32, binop(Iop_CmpNE64, bit, mkU64(0)));
- case 8: return unop(Iop_1Uto32, binop(Iop_CmpEQ64, bit, mkU64(0)));
- case 8 + 4: return mkU32(1);
- }
- /* not reached */
- }
-
missed:
;
}
diff --git a/main/VEX/priv/guest_s390_toIR.c b/main/VEX/priv/guest_s390_toIR.c
index ec89860..96c538e 100644
--- a/main/VEX/priv/guest_s390_toIR.c
+++ b/main/VEX/priv/guest_s390_toIR.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -34,9 +34,7 @@
#include "libvex_basictypes.h"
#include "libvex_ir.h"
-#include "libvex_guest_s390x.h" /* VexGuestS390XState */
#include "libvex.h" /* needed for bb_to_IR.h */
-#include "libvex_guest_offsets.h" /* OFFSET_s390x_SYSNO */
#include "libvex_s390x_common.h"
#include "main_util.h" /* vassert */
#include "main_globals.h" /* vex_traceflags */
@@ -50,6 +48,8 @@
/*--- Forward declarations ---*/
/*------------------------------------------------------------*/
static UInt s390_decode_and_irgen(UChar *, UInt, DisResult *);
+static void s390_irgen_xonc(IROp, IRTemp, IRTemp, IRTemp);
+static void s390_irgen_CLC_EX(IRTemp, IRTemp, IRTemp);
/*------------------------------------------------------------*/
@@ -85,6 +85,7 @@
S390_DECODE_ERROR
} s390_decode_t;
+
/*------------------------------------------------------------*/
/*--- Helpers for constructing IR. ---*/
/*------------------------------------------------------------*/
@@ -121,6 +122,13 @@
return IRExpr_RdTmp(tmp);
}
+/* Generate an expression node for an address. */
+static __inline__ IRExpr *
+mkaddr_expr(Addr64 addr)
+{
+ return IRExpr_Const(IRConst_U64(addr));
+}
+
/* Add a statement that assigns to a temporary */
static __inline__ void
assign(IRTemp dst, IRExpr *expr)
@@ -128,6 +136,13 @@
stmt(IRStmt_WrTmp(dst, expr));
}
+/* Write an address into the guest_IA */
+static __inline__ void
+put_IA(IRExpr *address)
+{
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_IA), address));
+}
+
/* Create a temporary of the given type and assign the expression to it */
static __inline__ IRTemp
mktemp(IRType type, IRExpr *expr)
@@ -243,10 +258,10 @@
static void
call_function(IRExpr *callee_address)
{
- irsb->next = callee_address;
- irsb->jumpkind = Ijk_Call;
+ put_IA(callee_address);
- dis_res->whatNext = Dis_StopHere;
+ dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_Call;
}
/* Function call with known target. */
@@ -257,9 +272,10 @@
dis_res->whatNext = Dis_ResteerU;
dis_res->continueAt = callee_address;
} else {
- irsb->next = mkU64(callee_address);
- irsb->jumpkind = Ijk_Call;
+ put_IA(mkaddr_expr(callee_address));
+
dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_Call;
}
}
@@ -267,10 +283,10 @@
static void
return_from_function(IRExpr *return_address)
{
- irsb->next = return_address;
- irsb->jumpkind = Ijk_Ret;
+ put_IA(return_address);
- dis_res->whatNext = Dis_StopHere;
+ dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_Ret;
}
/* A conditional branch whose target is not known at instrumentation time.
@@ -281,21 +297,21 @@
if (! condition) goto next_instruction;
goto computed_target;
-
- This inversion is being handled at code generation time. So we just
- take the condition here as is.
*/
static void
-if_not_condition_goto_computed(IRExpr *condition, IRExpr *target)
+if_condition_goto_computed(IRExpr *condition, IRExpr *target)
{
vassert(typeOfIRExpr(irsb->tyenv, condition) == Ity_I1);
- stmt(IRStmt_Exit(condition, Ijk_Boring, IRConst_U64(guest_IA_next_instr)));
+ condition = unop(Iop_Not1, condition);
- irsb->next = target;
- irsb->jumpkind = Ijk_Boring;
+ stmt(IRStmt_Exit(condition, Ijk_Boring, IRConst_U64(guest_IA_next_instr),
+ S390X_GUEST_OFFSET(guest_IA)));
- dis_res->whatNext = Dis_StopHere;
+ put_IA(target);
+
+ dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_Boring;
}
/* A conditional branch whose target is known at instrumentation time. */
@@ -304,8 +320,13 @@
{
vassert(typeOfIRExpr(irsb->tyenv, condition) == Ity_I1);
- stmt(IRStmt_Exit(condition, Ijk_Boring, IRConst_U64(target)));
- dis_res->whatNext = Dis_Continue;
+ stmt(IRStmt_Exit(condition, Ijk_Boring, IRConst_U64(target),
+ S390X_GUEST_OFFSET(guest_IA)));
+
+ put_IA(mkaddr_expr(guest_IA_next_instr));
+
+ dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_Boring;
}
/* An unconditional branch. Target may or may not be known at instrumentation
@@ -313,23 +334,26 @@
static void
always_goto(IRExpr *target)
{
- irsb->next = target;
- irsb->jumpkind = Ijk_Boring;
+ put_IA(target);
- dis_res->whatNext = Dis_StopHere;
+ dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_Boring;
}
+
/* An unconditional branch to a known target. */
static void
always_goto_and_chase(Addr64 target)
{
if (resteer_fn(resteer_data, target)) {
+ /* Follow into the target */
dis_res->whatNext = Dis_ResteerU;
dis_res->continueAt = target;
} else {
- irsb->next = mkU64(target);
- irsb->jumpkind = Ijk_Boring;
- dis_res->whatNext = Dis_StopHere;
+ put_IA(mkaddr_expr(target));
+
+ dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_Boring;
}
}
@@ -338,19 +362,67 @@
system_call(IRExpr *sysno)
{
/* Store the system call number in the pseudo register. */
- stmt(IRStmt_Put(OFFSET_s390x_SYSNO, sysno));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_SYSNO), sysno));
/* Store the current IA into guest_IP_AT_SYSCALL. libvex_ir.h says so. */
- stmt(IRStmt_Put(OFFSET_s390x_IP_AT_SYSCALL, mkU64(guest_IA_curr_instr)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_IP_AT_SYSCALL),
+ mkU64(guest_IA_curr_instr)));
+
+ put_IA(mkaddr_expr(guest_IA_next_instr));
/* It's important that all ArchRegs carry their up-to-date value
at this point. So we declare an end-of-block here, which
forces any TempRegs caching ArchRegs to be flushed. */
- irsb->next = mkU64(guest_IA_next_instr);
+ dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_Sys_syscall;
+}
- irsb->jumpkind = Ijk_Sys_syscall;
+/* A side exit that branches back to the current insn if CONDITION is
+ true. Does not set DisResult. */
+static void
+iterate_if(IRExpr *condition)
+{
+ vassert(typeOfIRExpr(irsb->tyenv, condition) == Ity_I1);
- dis_res->whatNext = Dis_StopHere;
+ stmt(IRStmt_Exit(condition, Ijk_Boring, IRConst_U64(guest_IA_curr_instr),
+ S390X_GUEST_OFFSET(guest_IA)));
+}
+
+/* A side exit that branches back to the current insn.
+ Does not set DisResult. */
+static __inline__ void
+iterate(void)
+{
+ iterate_if(IRExpr_Const(IRConst_U1(True)));
+}
+
+/* A side exit that branches back to the insn immediately following the
+ current insn if CONDITION is true. Does not set DisResult. */
+static void
+next_insn_if(IRExpr *condition)
+{
+ vassert(typeOfIRExpr(irsb->tyenv, condition) == Ity_I1);
+
+ stmt(IRStmt_Exit(condition, Ijk_Boring, IRConst_U64(guest_IA_next_instr),
+ S390X_GUEST_OFFSET(guest_IA)));
+}
+
+/* Convenience function to restart the current insn */
+static void
+restart_if(IRExpr *condition)
+{
+ vassert(typeOfIRExpr(irsb->tyenv, condition) == Ity_I1);
+
+ stmt(IRStmt_Exit(condition, Ijk_TInval, IRConst_U64(guest_IA_curr_instr),
+ S390X_GUEST_OFFSET(guest_IA)));
+}
+
+/* Convenience function to yield to thread scheduler */
+static void
+yield_if(IRExpr *condition)
+{
+ stmt(IRStmt_Exit(condition, Ijk_Yield, IRConst_U64(guest_IA_next_instr),
+ S390X_GUEST_OFFSET(guest_IA)));
}
/* Encode the s390 rounding mode as it appears in the m3/m4 fields of certain
@@ -393,11 +465,29 @@
}
-/* Flags thunk offsets */
-#define S390X_GUEST_OFFSET_CC_OP S390X_GUEST_OFFSET(guest_CC_OP)
-#define S390X_GUEST_OFFSET_CC_DEP1 S390X_GUEST_OFFSET(guest_CC_DEP1)
-#define S390X_GUEST_OFFSET_CC_DEP2 S390X_GUEST_OFFSET(guest_CC_DEP2)
-#define S390X_GUEST_OFFSET_CC_NDEP S390X_GUEST_OFFSET(guest_CC_NDEP)
+/*------------------------------------------------------------*/
+/*--- IR Debugging aids. ---*/
+/*------------------------------------------------------------*/
+#if 0
+
+static ULong
+s390_do_print(HChar *text, ULong value)
+{
+ vex_printf("%s %llu\n", text, value);
+ return 0;
+}
+
+static void
+s390_print(HChar *text, IRExpr *value)
+{
+ IRDirty *d;
+
+ d = unsafeIRDirty_0_N(0 /* regparms */, "s390_do_print", &s390_do_print,
+ mkIRExprVec_2(mkU64((ULong)text), value));
+ stmt(IRStmt_Dirty(d));
+}
+#endif
+
/*------------------------------------------------------------*/
/*--- Build the flags thunk. ---*/
@@ -410,10 +500,10 @@
{
UInt op_off, dep1_off, dep2_off, ndep_off;
- op_off = S390X_GUEST_OFFSET_CC_OP;
- dep1_off = S390X_GUEST_OFFSET_CC_DEP1;
- dep2_off = S390X_GUEST_OFFSET_CC_DEP2;
- ndep_off = S390X_GUEST_OFFSET_CC_NDEP;
+ op_off = S390X_GUEST_OFFSET(guest_CC_OP);
+ dep1_off = S390X_GUEST_OFFSET(guest_CC_DEP1);
+ dep2_off = S390X_GUEST_OFFSET(guest_CC_DEP2);
+ ndep_off = S390X_GUEST_OFFSET(guest_CC_NDEP);
stmt(IRStmt_Put(op_off, op));
stmt(IRStmt_Put(dep1_off, dep1));
@@ -583,10 +673,10 @@
{
IRExpr **args, *call, *op, *dep1, *dep2, *ndep;
- op = IRExpr_Get(S390X_GUEST_OFFSET_CC_OP, Ity_I64);
- dep1 = IRExpr_Get(S390X_GUEST_OFFSET_CC_DEP1, Ity_I64);
- dep2 = IRExpr_Get(S390X_GUEST_OFFSET_CC_DEP2, Ity_I64);
- ndep = IRExpr_Get(S390X_GUEST_OFFSET_CC_NDEP, Ity_I64);
+ op = IRExpr_Get(S390X_GUEST_OFFSET(guest_CC_OP), Ity_I64);
+ dep1 = IRExpr_Get(S390X_GUEST_OFFSET(guest_CC_DEP1), Ity_I64);
+ dep2 = IRExpr_Get(S390X_GUEST_OFFSET(guest_CC_DEP2), Ity_I64);
+ ndep = IRExpr_Get(S390X_GUEST_OFFSET(guest_CC_NDEP), Ity_I64);
args = mkIRExprVec_4(op, dep1, dep2, ndep);
call = mkIRExprCCall(Ity_I32, 0 /*regparm*/,
@@ -602,21 +692,35 @@
/* Build IR to calculate the internal condition code for a "compare and branch"
insn. Returns an expression of type Ity_I32 */
static IRExpr *
-s390_call_calculate_icc(UInt opc, IRTemp op1, IRTemp op2, Bool sign_extend)
+s390_call_calculate_icc(UInt m, UInt opc, IRTemp op1, IRTemp op2)
{
- IRExpr **args, *call, *op, *dep1, *dep2;
+ IRExpr **args, *call, *op, *dep1, *dep2, *mask;
+ switch (opc) {
+ case S390_CC_OP_SIGNED_COMPARE:
+ dep1 = s390_cc_widen(op1, True);
+ dep2 = s390_cc_widen(op2, True);
+ break;
+
+ case S390_CC_OP_UNSIGNED_COMPARE:
+ dep1 = s390_cc_widen(op1, False);
+ dep2 = s390_cc_widen(op2, False);
+ break;
+
+ default:
+ vpanic("s390_call_calculate_icc");
+ }
+
+ mask = mkU64(m);
op = mkU64(opc);
- dep1 = s390_cc_widen(op1, sign_extend);
- dep2 = s390_cc_widen(op2, sign_extend);
- args = mkIRExprVec_3(op, dep1, dep2);
+ args = mkIRExprVec_5(mask, op, dep1, dep2, mkU64(0) /* unused */);
call = mkIRExprCCall(Ity_I32, 0 /*regparm*/,
- "s390_calculate_icc", &s390_calculate_icc, args);
+ "s390_calculate_cond", &s390_calculate_cond, args);
- /* Exclude OP from definedness checking. We're only
- interested in DEP1 and DEP2. */
- call->Iex.CCall.cee->mcx_mask = (1<<0);
+ /* Exclude the requested condition, OP and NDEP from definedness
+ checking. We're only interested in DEP1 and DEP2. */
+ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<1) | (1<<4);
return call;
}
@@ -629,10 +733,10 @@
IRExpr **args, *call, *op, *dep1, *dep2, *ndep, *mask;
mask = mkU64(m);
- op = IRExpr_Get(S390X_GUEST_OFFSET_CC_OP, Ity_I64);
- dep1 = IRExpr_Get(S390X_GUEST_OFFSET_CC_DEP1, Ity_I64);
- dep2 = IRExpr_Get(S390X_GUEST_OFFSET_CC_DEP2, Ity_I64);
- ndep = IRExpr_Get(S390X_GUEST_OFFSET_CC_NDEP, Ity_I64);
+ op = IRExpr_Get(S390X_GUEST_OFFSET(guest_CC_OP), Ity_I64);
+ dep1 = IRExpr_Get(S390X_GUEST_OFFSET(guest_CC_DEP1), Ity_I64);
+ dep2 = IRExpr_Get(S390X_GUEST_OFFSET(guest_CC_DEP2), Ity_I64);
+ ndep = IRExpr_Get(S390X_GUEST_OFFSET(guest_CC_NDEP), Ity_I64);
args = mkIRExprVec_5(mask, op, dep1, dep2, ndep);
call = mkIRExprCCall(Ity_I32, 0 /*regparm*/,
@@ -655,14 +759,8 @@
s390_cc_thunk_put3(op,dep1,dep2,ndep,False)
#define s390_cc_thunk_putSSS(op,dep1,dep2,ndep) \
s390_cc_thunk_put3(op,dep1,dep2,ndep,True)
-#define s390_call_calculate_iccZZ(op,dep1,dep2) \
- s390_call_calculate_icc(op,dep1,dep2,False)
-#define s390_call_calculate_iccSS(op,dep1,dep2) \
- s390_call_calculate_icc(op,dep1,dep2,True)
-#define OFFB_TISTART S390X_GUEST_OFFSET(guest_TISTART)
-#define OFFB_TILEN S390X_GUEST_OFFSET(guest_TILEN)
/*------------------------------------------------------------*/
@@ -1585,6 +1683,16 @@
}
static void
+s390_format_RRF_M0RERE(HChar *(*irgen)(UChar m3, UChar r1, UChar r2),
+ UChar m3, UChar r1, UChar r2)
+{
+ HChar *mnm = irgen(m3, r1, r2);
+
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
+ s390_disasm(ENC4(MNM, GPR, GPR, UINT), mnm, r1, r2, m3);
+}
+
+static void
s390_format_RRF_F0FF(HChar *(*irgen)(UChar, UChar, UChar),
UChar r1, UChar r3, UChar r2)
{
@@ -1787,14 +1895,16 @@
IRTemp op2addr = newTemp(Ity_I64);
IRTemp d2 = newTemp(Ity_I64);
- if_condition_goto(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
+
assign(d2, mkU64(((ULong)(Long)(Char)dh2 << 12) | ((ULong)dl2)));
assign(op2addr, binop(Iop_Add64, mkexpr(d2), b2 != 0 ? get_gpr_dw0(b2) :
mkU64(0)));
irgen(r1, op2addr);
+ vassert(dis_res->whatNext == Dis_Continue);
+
if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
s390_disasm(ENC3(XMNM, GPR, SDXB), xmnm_kind, m3, r1, dh2, dl2, 0, b2);
}
@@ -2064,26 +2174,6 @@
/*------------------------------------------------------------*/
static HChar *
-s390_irgen_00(UChar r1 __attribute__((unused)),
- UChar r2 __attribute__((unused)))
-{
- IRDirty *d;
-
- d = unsafeIRDirty_0_N (0, "s390x_dirtyhelper_00", &s390x_dirtyhelper_00,
- mkIRExprVec_0());
- d->needsBBP = 1; /* Need to pass pointer to guest state to helper */
-
- d->fxState[0].fx = Ifx_Modify; /* read then write */
- d->fxState[0].offset = S390X_GUEST_OFFSET(guest_IA);
- d->fxState[0].size = sizeof(ULong);
- d->nFxState = 1;
-
- stmt(IRStmt_Dirty(d));
-
- return "00";
-}
-
-static HChar *
s390_irgen_AR(UChar r1, UChar r2)
{
IRTemp op1 = newTemp(Ity_I32);
@@ -3120,8 +3210,8 @@
return_from_function(get_gpr_dw0(r2));
} else {
assign(cond, s390_call_calculate_cond(r1));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), get_gpr_dw0(r2));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
+ get_gpr_dw0(r2));
}
}
if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
@@ -3141,8 +3231,8 @@
always_goto(mkexpr(op2addr));
} else {
assign(cond, s390_call_calculate_cond(r1));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), mkexpr(op2addr));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
+ mkexpr(op2addr));
}
}
if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
@@ -3156,8 +3246,8 @@
{
put_gpr_w1(r1, binop(Iop_Sub32, get_gpr_w1(r1), mkU32(1)));
if (r2 != 0) {
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, get_gpr_w1(r1), mkU32(0)
- ), get_gpr_dw0(r2));
+ if_condition_goto_computed(binop(Iop_CmpNE32, get_gpr_w1(r1), mkU32(0)),
+ get_gpr_dw0(r2));
}
return "bctr";
@@ -3168,8 +3258,8 @@
{
put_gpr_dw0(r1, binop(Iop_Sub64, get_gpr_dw0(r1), mkU64(1)));
if (r2 != 0) {
- if_not_condition_goto_computed(binop(Iop_CmpEQ64, get_gpr_dw0(r1),
- mkU64(0)), get_gpr_dw0(r2));
+ if_condition_goto_computed(binop(Iop_CmpNE64, get_gpr_dw0(r1), mkU64(0)),
+ get_gpr_dw0(r2));
}
return "bctgr";
@@ -3179,8 +3269,8 @@
s390_irgen_BCT(UChar r1, IRTemp op2addr)
{
put_gpr_w1(r1, binop(Iop_Sub32, get_gpr_w1(r1), mkU32(1)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, get_gpr_w1(r1), mkU32(0)),
- mkexpr(op2addr));
+ if_condition_goto_computed(binop(Iop_CmpNE32, get_gpr_w1(r1), mkU32(0)),
+ mkexpr(op2addr));
return "bct";
}
@@ -3189,8 +3279,8 @@
s390_irgen_BCTG(UChar r1, IRTemp op2addr)
{
put_gpr_dw0(r1, binop(Iop_Sub64, get_gpr_dw0(r1), mkU64(1)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ64, get_gpr_dw0(r1), mkU64(0)),
- mkexpr(op2addr));
+ if_condition_goto_computed(binop(Iop_CmpNE64, get_gpr_dw0(r1), mkU64(0)),
+ mkexpr(op2addr));
return "bctg";
}
@@ -3202,8 +3292,8 @@
assign(value, get_gpr_w1(r3 | 1));
put_gpr_w1(r1, binop(Iop_Add32, get_gpr_w1(r1), get_gpr_w1(r3)));
- if_not_condition_goto_computed(binop(Iop_CmpLE32S, get_gpr_w1(r1),
- mkexpr(value)), mkexpr(op2addr));
+ if_condition_goto_computed(binop(Iop_CmpLT32S, mkexpr(value),
+ get_gpr_w1(r1)), mkexpr(op2addr));
return "bxh";
}
@@ -3215,8 +3305,8 @@
assign(value, get_gpr_dw0(r3 | 1));
put_gpr_dw0(r1, binop(Iop_Add64, get_gpr_dw0(r1), get_gpr_dw0(r3)));
- if_not_condition_goto_computed(binop(Iop_CmpLE64S, get_gpr_dw0(r1),
- mkexpr(value)), mkexpr(op2addr));
+ if_condition_goto_computed(binop(Iop_CmpLT64S, mkexpr(value),
+ get_gpr_dw0(r1)), mkexpr(op2addr));
return "bxhg";
}
@@ -3228,8 +3318,8 @@
assign(value, get_gpr_w1(r3 | 1));
put_gpr_w1(r1, binop(Iop_Add32, get_gpr_w1(r1), get_gpr_w1(r3)));
- if_not_condition_goto_computed(binop(Iop_CmpLT32S, mkexpr(value),
- get_gpr_w1(r1)), mkexpr(op2addr));
+ if_condition_goto_computed(binop(Iop_CmpLE32S, get_gpr_w1(r1),
+ mkexpr(value)), mkexpr(op2addr));
return "bxle";
}
@@ -3241,8 +3331,8 @@
assign(value, get_gpr_dw0(r3 | 1));
put_gpr_dw0(r1, binop(Iop_Add64, get_gpr_dw0(r1), get_gpr_dw0(r3)));
- if_not_condition_goto_computed(binop(Iop_CmpLT64S, mkexpr(value),
- get_gpr_dw0(r1)), mkexpr(op2addr));
+ if_condition_goto_computed(binop(Iop_CmpLE64S, get_gpr_dw0(r1),
+ mkexpr(value)), mkexpr(op2addr));
return "bxleg";
}
@@ -3547,7 +3637,6 @@
{
IRTemp op1 = newTemp(Ity_I32);
IRTemp op2 = newTemp(Ity_I32);
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -3557,12 +3646,10 @@
} else {
assign(op1, get_gpr_w1(r1));
assign(op2, get_gpr_w1(r2));
- assign(icc, s390_call_calculate_iccSS(S390_CC_OP_SIGNED_COMPARE, op1,
- op2));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), mkexpr(op4addr));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE,
+ op1, op2));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond),
+ mkU32(0)), mkexpr(op4addr));
}
}
@@ -3574,7 +3661,6 @@
{
IRTemp op1 = newTemp(Ity_I64);
IRTemp op2 = newTemp(Ity_I64);
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -3584,12 +3670,10 @@
} else {
assign(op1, get_gpr_dw0(r1));
assign(op2, get_gpr_dw0(r2));
- assign(icc, s390_call_calculate_iccSS(S390_CC_OP_SIGNED_COMPARE, op1,
- op2));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), mkexpr(op4addr));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE,
+ op1, op2));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond),
+ mkU32(0)), mkexpr(op4addr));
}
}
@@ -3601,7 +3685,6 @@
{
IRTemp op1 = newTemp(Ity_I32);
IRTemp op2 = newTemp(Ity_I32);
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -3612,10 +3695,8 @@
} else {
assign(op1, get_gpr_w1(r1));
assign(op2, get_gpr_w1(r2));
- assign(icc, s390_call_calculate_iccSS(S390_CC_OP_SIGNED_COMPARE, op1,
- op2));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE,
+ op1, op2));
if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1));
@@ -3630,7 +3711,6 @@
{
IRTemp op1 = newTemp(Ity_I64);
IRTemp op2 = newTemp(Ity_I64);
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -3641,10 +3721,8 @@
} else {
assign(op1, get_gpr_dw0(r1));
assign(op2, get_gpr_dw0(r2));
- assign(icc, s390_call_calculate_iccSS(S390_CC_OP_SIGNED_COMPARE, op1,
- op2));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE,
+ op1, op2));
if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1));
@@ -3659,7 +3737,6 @@
{
IRTemp op1 = newTemp(Ity_I32);
Int op2;
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -3669,12 +3746,10 @@
} else {
assign(op1, get_gpr_w1(r1));
op2 = (Int)(Char)i2;
- assign(icc, s390_call_calculate_iccSS(S390_CC_OP_SIGNED_COMPARE, op1,
- mktemp(Ity_I32, mkU32((UInt)op2))));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), mkexpr(op4addr));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE, op1,
+ mktemp(Ity_I32, mkU32((UInt)op2))));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
+ mkexpr(op4addr));
}
}
@@ -3686,7 +3761,6 @@
{
IRTemp op1 = newTemp(Ity_I64);
Long op2;
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -3696,12 +3770,10 @@
} else {
assign(op1, get_gpr_dw0(r1));
op2 = (Long)(Char)i2;
- assign(icc, s390_call_calculate_iccSS(S390_CC_OP_SIGNED_COMPARE, op1,
- mktemp(Ity_I64, mkU64((ULong)op2))));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), mkexpr(op4addr));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE, op1,
+ mktemp(Ity_I64, mkU64((ULong)op2))));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
+ mkexpr(op4addr));
}
}
@@ -3713,7 +3785,6 @@
{
IRTemp op1 = newTemp(Ity_I32);
Int op2;
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -3723,10 +3794,8 @@
} else {
assign(op1, get_gpr_w1(r1));
op2 = (Int)(Char)i2;
- assign(icc, s390_call_calculate_iccSS(S390_CC_OP_SIGNED_COMPARE, op1,
- mktemp(Ity_I32, mkU32((UInt)op2))));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE, op1,
+ mktemp(Ity_I32, mkU32((UInt)op2))));
if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1));
@@ -3741,7 +3810,6 @@
{
IRTemp op1 = newTemp(Ity_I64);
Long op2;
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -3751,10 +3819,8 @@
} else {
assign(op1, get_gpr_dw0(r1));
op2 = (Long)(Char)i2;
- assign(icc, s390_call_calculate_iccSS(S390_CC_OP_SIGNED_COMPARE, op1,
- mktemp(Ity_I64, mkU64((ULong)op2))));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_SIGNED_COMPARE, op1,
+ mktemp(Ity_I64, mkU64((ULong)op2))));
if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1));
@@ -4218,7 +4284,6 @@
{
IRTemp op1 = newTemp(Ity_I32);
IRTemp op2 = newTemp(Ity_I32);
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -4228,12 +4293,10 @@
} else {
assign(op1, get_gpr_w1(r1));
assign(op2, get_gpr_w1(r2));
- assign(icc, s390_call_calculate_iccZZ(S390_CC_OP_UNSIGNED_COMPARE, op1,
- op2));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), mkexpr(op4addr));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE,
+ op1, op2));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
+ mkexpr(op4addr));
}
}
@@ -4245,7 +4308,6 @@
{
IRTemp op1 = newTemp(Ity_I64);
IRTemp op2 = newTemp(Ity_I64);
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -4255,12 +4317,10 @@
} else {
assign(op1, get_gpr_dw0(r1));
assign(op2, get_gpr_dw0(r2));
- assign(icc, s390_call_calculate_iccZZ(S390_CC_OP_UNSIGNED_COMPARE, op1,
- op2));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), mkexpr(op4addr));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE,
+ op1, op2));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
+ mkexpr(op4addr));
}
}
@@ -4272,7 +4332,6 @@
{
IRTemp op1 = newTemp(Ity_I32);
IRTemp op2 = newTemp(Ity_I32);
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -4282,10 +4341,8 @@
} else {
assign(op1, get_gpr_w1(r1));
assign(op2, get_gpr_w1(r2));
- assign(icc, s390_call_calculate_iccZZ(S390_CC_OP_UNSIGNED_COMPARE, op1,
- op2));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE,
+ op1, op2));
if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1));
@@ -4300,7 +4357,6 @@
{
IRTemp op1 = newTemp(Ity_I64);
IRTemp op2 = newTemp(Ity_I64);
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -4310,10 +4366,8 @@
} else {
assign(op1, get_gpr_dw0(r1));
assign(op2, get_gpr_dw0(r2));
- assign(icc, s390_call_calculate_iccZZ(S390_CC_OP_UNSIGNED_COMPARE, op1,
- op2));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE,
+ op1, op2));
if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1));
@@ -4328,7 +4382,6 @@
{
IRTemp op1 = newTemp(Ity_I32);
UInt op2;
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -4338,12 +4391,10 @@
} else {
assign(op1, get_gpr_w1(r1));
op2 = (UInt)i2;
- assign(icc, s390_call_calculate_iccZZ(S390_CC_OP_UNSIGNED_COMPARE, op1,
- mktemp(Ity_I32, mkU32(op2))));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), mkexpr(op4addr));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE, op1,
+ mktemp(Ity_I32, mkU32(op2))));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
+ mkexpr(op4addr));
}
}
@@ -4355,7 +4406,6 @@
{
IRTemp op1 = newTemp(Ity_I64);
ULong op2;
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -4365,12 +4415,10 @@
} else {
assign(op1, get_gpr_dw0(r1));
op2 = (ULong)i2;
- assign(icc, s390_call_calculate_iccZZ(S390_CC_OP_UNSIGNED_COMPARE, op1,
- mktemp(Ity_I64, mkU64(op2))));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
- if_not_condition_goto_computed(binop(Iop_CmpEQ32, mkexpr(cond),
- mkU32(0)), mkexpr(op4addr));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE, op1,
+ mktemp(Ity_I64, mkU64(op2))));
+ if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
+ mkexpr(op4addr));
}
}
@@ -4382,7 +4430,6 @@
{
IRTemp op1 = newTemp(Ity_I32);
UInt op2;
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -4392,10 +4439,8 @@
} else {
assign(op1, get_gpr_w1(r1));
op2 = (UInt)i2;
- assign(icc, s390_call_calculate_iccZZ(S390_CC_OP_UNSIGNED_COMPARE, op1,
- mktemp(Ity_I32, mkU32(op2))));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE, op1,
+ mktemp(Ity_I32, mkU32(op2))));
if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1));
@@ -4410,7 +4455,6 @@
{
IRTemp op1 = newTemp(Ity_I64);
ULong op2;
- IRTemp icc = newTemp(Ity_I32);
IRTemp cond = newTemp(Ity_I32);
if (m3 == 0) {
@@ -4420,10 +4464,8 @@
} else {
assign(op1, get_gpr_dw0(r1));
op2 = (ULong)i2;
- assign(icc, s390_call_calculate_iccZZ(S390_CC_OP_UNSIGNED_COMPARE, op1,
- mktemp(Ity_I64, mkU64(op2))));
- assign(cond, binop(Iop_And32, binop(Iop_Shl32, mkU32(m3),
- unop(Iop_32to8, mkexpr(icc))), mkU32(8)));
+ assign(cond, s390_call_calculate_icc(m3, S390_CC_OP_UNSIGNED_COMPARE, op1,
+ mktemp(Ity_I64, mkU64(op2))));
if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
guest_IA_curr_instr + ((ULong)(Long)(Short)i4 << 1));
@@ -5836,8 +5878,7 @@
static HChar *
s390_irgen_LOCR(UChar m3, UChar r1, UChar r2)
{
- if_condition_goto(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
put_gpr_w1(r1, get_gpr_w1(r2));
return "locr";
@@ -5846,8 +5887,7 @@
static HChar *
s390_irgen_LOCGR(UChar m3, UChar r1, UChar r2)
{
- if_condition_goto(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
put_gpr_dw0(r1, get_gpr_dw0(r2));
return "locgr";
@@ -6844,7 +6884,7 @@
IRTemp p2 = newTemp(Ity_I64);
IRTemp op = newTemp(Ity_I64);
IRTemp result = newTemp(Ity_I64);
- Long sign_mask;
+ ULong sign_mask;
IRTemp shift_amount = newTemp(Ity_I64);
assign(p1, unop(Iop_32Uto64, get_gpr_w1(r1)));
@@ -6854,8 +6894,8 @@
sign_mask = 1ULL << 63;
assign(shift_amount, binop(Iop_And64, mkexpr(op2addr), mkU64(63)));
assign(result, binop(Iop_Or64, binop(Iop_And64, binop(Iop_Shl64, mkexpr(op),
- unop(Iop_64to8, mkexpr(shift_amount))), mkU64((ULong)(~sign_mask))),
- binop(Iop_And64, mkexpr(op), mkU64((ULong)sign_mask))));
+ unop(Iop_64to8, mkexpr(shift_amount))), mkU64(~sign_mask)),
+ binop(Iop_And64, mkexpr(op), mkU64(sign_mask))));
put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result)));
put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result)));
s390_cc_thunk_putZZ(S390_CC_OP_SHIFT_LEFT_64, op, shift_amount);
@@ -7856,18 +7896,6 @@
}
static HChar *
-s390_irgen_TS(IRTemp op2addr)
-{
- IRTemp value = newTemp(Ity_I8);
-
- assign(value, load(Ity_I8, mkexpr(op2addr)));
- s390_cc_thunk_putZ(S390_CC_OP_TEST_AND_SET, value);
- store(mkexpr(op2addr), mkU8(255));
-
- return "ts";
-}
-
-static HChar *
s390_irgen_TM(UChar i2, IRTemp op1addr)
{
UChar mask;
@@ -8563,29 +8591,10 @@
static HChar *
s390_irgen_CLC(UChar length, IRTemp start1, IRTemp start2)
{
- IRTemp current1 = newTemp(Ity_I8);
- IRTemp current2 = newTemp(Ity_I8);
- IRTemp counter = newTemp(Ity_I64);
+ IRTemp len = newTemp(Ity_I64);
- assign(counter, get_counter_dw0());
- put_counter_dw0(mkU64(0));
-
- assign(current1, load(Ity_I8, binop(Iop_Add64, mkexpr(start1),
- mkexpr(counter))));
- assign(current2, load(Ity_I8, binop(Iop_Add64, mkexpr(start2),
- mkexpr(counter))));
- s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, current1, current2,
- False);
-
- /* Both fields differ ? */
- if_condition_goto(binop(Iop_CmpNE8, mkexpr(current1), mkexpr(current2)),
- guest_IA_next_instr);
-
- /* Check for end of field */
- put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
- if_condition_goto(binop(Iop_CmpNE64, mkexpr(counter), mkU64(length)),
- guest_IA_curr_instr);
- put_counter_dw0(mkU64(0));
+ assign(len, mkU64(length));
+ s390_irgen_CLC_EX(len, start1, start2);
return "clc";
}
@@ -8615,9 +8624,8 @@
/* len1 == 0 and len2 == 0? Exit */
s390_cc_set(0);
- if_condition_goto(binop(Iop_CmpEQ32, binop(Iop_Or32, mkexpr(len1),
- mkexpr(len2)), mkU32(0)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ32, binop(Iop_Or32, mkexpr(len1),
+ mkexpr(len2)), mkU32(0)));
/* Because mkite evaluates both the then-clause and the else-clause
we cannot load directly from addr1 here. If len1 is 0, then adddr1
@@ -8640,8 +8648,7 @@
s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, single1, single2, False);
/* Fields differ ? */
- if_condition_goto(binop(Iop_CmpNE8, mkexpr(single1), mkexpr(single2)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpNE8, mkexpr(single1), mkexpr(single2)));
/* Update len1 and addr1, unless len1 == 0. */
put_gpr_dw0(r1,
@@ -8667,7 +8674,7 @@
binop(Iop_And32, mkexpr(r2p1), mkU32(0xFF000000u)),
binop(Iop_Sub32, mkexpr(r2p1), mkU32(1))));
- always_goto_and_chase(guest_IA_curr_instr);
+ iterate();
return "clcl";
}
@@ -8693,9 +8700,8 @@
/* len1 == 0 and len3 == 0? Exit */
s390_cc_set(0);
- if_condition_goto(binop(Iop_CmpEQ64,binop(Iop_Or64, mkexpr(len1),
- mkexpr(len3)), mkU64(0)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ64,binop(Iop_Or64, mkexpr(len1),
+ mkexpr(len3)), mkU64(0)));
/* A mux requires both ways to be possible. This is a way to prevent clcle
from reading from addr1 if it should read from the pad. Since the pad
@@ -8721,8 +8727,7 @@
s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, single1, single3, False);
/* Both fields differ ? */
- if_condition_goto(binop(Iop_CmpNE8, mkexpr(single1), mkexpr(single3)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpNE8, mkexpr(single1), mkexpr(single3)));
/* If a length in 0 we must not change this length and the address */
put_gpr_dw0(r1,
@@ -8743,53 +8748,30 @@
mkite(binop(Iop_CmpEQ64, mkexpr(len3), mkU64(0)),
mkU64(0), binop(Iop_Sub64, mkexpr(len3), mkU64(1))));
- /* The architecture requires that we exit with CC3 after a machine specific
- amount of bytes. We do that if len1+len3 % 4096 == 0 */
- s390_cc_set(3);
- if_condition_goto(binop(Iop_CmpEQ64,
- binop(Iop_And64,
- binop(Iop_Add64, mkexpr(len1), mkexpr(len3)),
- mkU64(0xfff)),
- mkU64(0)),
- guest_IA_next_instr);
-
- always_goto_and_chase(guest_IA_curr_instr);
+ iterate();
return "clcle";
}
+
static void
s390_irgen_XC_EX(IRTemp length, IRTemp start1, IRTemp start2)
{
- IRTemp old1 = newTemp(Ity_I8);
- IRTemp old2 = newTemp(Ity_I8);
- IRTemp new1 = newTemp(Ity_I8);
- IRTemp counter = newTemp(Ity_I32);
- IRTemp addr1 = newTemp(Ity_I64);
+ s390_irgen_xonc(Iop_Xor8, length, start1, start2);
+}
- assign(counter, get_counter_w0());
- assign(addr1, binop(Iop_Add64, mkexpr(start1),
- unop(Iop_32Uto64, mkexpr(counter))));
+static void
+s390_irgen_NC_EX(IRTemp length, IRTemp start1, IRTemp start2)
+{
+ s390_irgen_xonc(Iop_And8, length, start1, start2);
+}
- assign(old1, load(Ity_I8, mkexpr(addr1)));
- assign(old2, load(Ity_I8, binop(Iop_Add64, mkexpr(start2),
- unop(Iop_32Uto64,mkexpr(counter)))));
- assign(new1, binop(Iop_Xor8, mkexpr(old1), mkexpr(old2)));
- store(mkexpr(addr1),
- mkite(binop(Iop_CmpEQ64, mkexpr(start1), mkexpr(start2)),
- mkU8(0), mkexpr(new1)));
- put_counter_w1(binop(Iop_Or32, unop(Iop_8Uto32, mkexpr(new1)),
- get_counter_w1()));
-
- /* Check for end of field */
- put_counter_w0(binop(Iop_Add32, mkexpr(counter), mkU32(1)));
- if_condition_goto(binop(Iop_CmpNE32, mkexpr(counter), mkexpr(length)),
- guest_IA_curr_instr);
- s390_cc_thunk_put1(S390_CC_OP_BITWISE, mktemp(Ity_I32, get_counter_w1()),
- False);
- put_counter_dw0(mkU64(0));
+static void
+s390_irgen_OC_EX(IRTemp length, IRTemp start1, IRTemp start2)
+{
+ s390_irgen_xonc(Iop_Or8, length, start1, start2);
}
@@ -8811,13 +8793,11 @@
False);
/* Both fields differ ? */
- if_condition_goto(binop(Iop_CmpNE8, mkexpr(current1), mkexpr(current2)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpNE8, mkexpr(current1), mkexpr(current2)));
/* Check for end of field */
put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
- if_condition_goto(binop(Iop_CmpNE64, mkexpr(counter), mkexpr(length)),
- guest_IA_curr_instr);
+ iterate_if(binop(Iop_CmpNE64, mkexpr(counter), mkexpr(length)));
put_counter_dw0(mkU64(0));
}
@@ -8833,16 +8813,37 @@
/* Check for end of field */
put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
- if_condition_goto(binop(Iop_CmpNE64, mkexpr(counter), mkexpr(length)),
- guest_IA_curr_instr);
+ iterate_if(binop(Iop_CmpNE64, mkexpr(counter), mkexpr(length)));
+ put_counter_dw0(mkU64(0));
+}
+
+static void
+s390_irgen_TR_EX(IRTemp length, IRTemp start1, IRTemp start2)
+{
+ IRTemp op = newTemp(Ity_I8);
+ IRTemp op1 = newTemp(Ity_I8);
+ IRTemp result = newTemp(Ity_I64);
+ IRTemp counter = newTemp(Ity_I64);
+
+ assign(counter, get_counter_dw0());
+
+ assign(op, load(Ity_I8, binop(Iop_Add64, mkexpr(start1), mkexpr(counter))));
+
+ assign(result, binop(Iop_Add64, unop(Iop_8Uto64, mkexpr(op)), mkexpr(start2)));
+
+ assign(op1, load(Ity_I8, mkexpr(result)));
+ store(binop(Iop_Add64, mkexpr(start1), mkexpr(counter)), mkexpr(op1));
+
+ put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
+ iterate_if(binop(Iop_CmpNE64, mkexpr(counter), mkexpr(length)));
put_counter_dw0(mkU64(0));
}
-
static void
s390_irgen_EX_SS(UChar r, IRTemp addr2,
-void (*irgen)(IRTemp length, IRTemp start1, IRTemp start2), int lensize)
+ void (*irgen)(IRTemp length, IRTemp start1, IRTemp start2),
+ int lensize)
{
struct SS {
unsigned int op : 8;
@@ -8876,10 +8877,10 @@
stmt(IRStmt_Dirty(d));
/* and restart */
- stmt(IRStmt_Put(OFFB_TISTART, mkU64(guest_IA_curr_instr)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU64(4)));
- stmt(IRStmt_Exit(mkexpr(cond), Ijk_TInval,
- IRConst_U64(guest_IA_curr_instr)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART),
+ mkU64(guest_IA_curr_instr)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), mkU64(4)));
+ restart_if(mkexpr(cond));
ss.bytes = last_execute_target;
assign(start1, binop(Iop_Add64, mkU64(ss.dec.d1),
@@ -8889,6 +8890,7 @@
assign(len, unop(lensize == 64 ? Iop_8Uto64 : Iop_8Uto32, binop(Iop_Or8,
r != 0 ? get_gpr_b7(r): mkU8(0), mkU8(ss.dec.l))));
irgen(len, start1, start2);
+
last_execute_target = 0;
}
@@ -8906,13 +8908,15 @@
mkIRExprVec_1(load(Ity_I64, mkexpr(addr2))));
stmt(IRStmt_Dirty(d));
/* and restart */
- stmt(IRStmt_Put(OFFB_TISTART, mkU64(guest_IA_curr_instr)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU64(4)));
- stmt(IRStmt_Exit(IRExpr_Const(IRConst_U1(True)), Ijk_TInval,
- IRConst_U64(guest_IA_curr_instr)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART),
+ mkU64(guest_IA_curr_instr)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), mkU64(4)));
+ restart_if(IRExpr_Const(IRConst_U1(True)));
+
/* we know that this will be invalidated */
- irsb->next = mkU64(guest_IA_next_instr);
+ put_IA(mkaddr_expr(guest_IA_next_instr));
dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_TInval;
break;
}
@@ -8931,6 +8935,20 @@
s390_irgen_EX_SS(r1, addr2, s390_irgen_XC_EX, 32);
return "xc via ex";
+ case 0xd600000000000000ULL:
+ /* special case OC */
+ s390_irgen_EX_SS(r1, addr2, s390_irgen_OC_EX, 32);
+ return "oc via ex";
+
+ case 0xd400000000000000ULL:
+ /* special case NC */
+ s390_irgen_EX_SS(r1, addr2, s390_irgen_NC_EX, 32);
+ return "nc via ex";
+
+ case 0xdc00000000000000ULL:
+ /* special case TR */
+ s390_irgen_EX_SS(r1, addr2, s390_irgen_TR_EX, 64);
+ return "tr via ex";
default:
{
@@ -8964,10 +8982,9 @@
stmt(IRStmt_Dirty(d));
/* and restart */
- stmt(IRStmt_Put(OFFB_TISTART, mkU64(guest_IA_curr_instr)));
- stmt(IRStmt_Put(OFFB_TILEN, mkU64(4)));
- stmt(IRStmt_Exit(mkexpr(cond), Ijk_TInval,
- IRConst_U64(guest_IA_curr_instr)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART), mkU64(guest_IA_curr_instr)));
+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), mkU64(4)));
+ restart_if(mkexpr(cond));
/* Now comes the actual translation */
bytes = (UChar *) &last_execute_target;
@@ -9024,8 +9041,7 @@
// start = next? CC=2 and out r1 and r2 unchanged
s390_cc_set(2);
put_gpr_dw0(r2, binop(Iop_Sub64, mkexpr(address), mkexpr(counter)));
- if_condition_goto(binop(Iop_CmpEQ64, mkexpr(address), mkexpr(next)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ64, mkexpr(address), mkexpr(next)));
assign(byte, load(Ity_I8, mkexpr(address)));
assign(delim, get_gpr_b7(0));
@@ -9033,18 +9049,14 @@
// byte = delim? CC=1, R1=address
s390_cc_set(1);
put_gpr_dw0(r1, mkexpr(address));
- if_condition_goto(binop(Iop_CmpEQ8, mkexpr(delim), mkexpr(byte)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ8, mkexpr(delim), mkexpr(byte)));
// else: all equal, no end yet, loop
put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
put_gpr_dw0(r1, mkexpr(next));
put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(address), mkU64(1)));
- stmt(IRStmt_Exit(binop(Iop_CmpNE64, mkexpr(counter), mkU64(255)),
- Ijk_Boring, IRConst_U64(guest_IA_curr_instr)));
- // >= 256 bytes done CC=3
- s390_cc_set(3);
- put_counter_dw0(mkU64(0));
+
+ iterate();
return "srst";
}
@@ -9071,46 +9083,38 @@
s390_cc_set(0);
put_gpr_dw0(r1, binop(Iop_Sub64, mkexpr(address1), mkexpr(counter)));
put_gpr_dw0(r2, binop(Iop_Sub64, mkexpr(address2), mkexpr(counter)));
- if_condition_goto(binop(Iop_CmpEQ8, mkU8(0),
- binop(Iop_Or8,
- binop(Iop_Xor8, mkexpr(byte1), mkexpr(end)),
- binop(Iop_Xor8, mkexpr(byte2), mkexpr(end)))),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ8, mkU8(0),
+ binop(Iop_Or8,
+ binop(Iop_Xor8, mkexpr(byte1), mkexpr(end)),
+ binop(Iop_Xor8, mkexpr(byte2), mkexpr(end)))));
put_gpr_dw0(r1, mkexpr(address1));
put_gpr_dw0(r2, mkexpr(address2));
// End found in string1
s390_cc_set(1);
- if_condition_goto(binop(Iop_CmpEQ8, mkexpr(end), mkexpr(byte1)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ8, mkexpr(end), mkexpr(byte1)));
// End found in string2
s390_cc_set(2);
- if_condition_goto(binop(Iop_CmpEQ8, mkexpr(end), mkexpr(byte2)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ8, mkexpr(end), mkexpr(byte2)));
// string1 < string2
s390_cc_set(1);
- if_condition_goto(binop(Iop_CmpLT32U, unop(Iop_8Uto32, mkexpr(byte1)),
- unop(Iop_8Uto32, mkexpr(byte2))),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpLT32U, unop(Iop_8Uto32, mkexpr(byte1)),
+ unop(Iop_8Uto32, mkexpr(byte2))));
// string2 < string1
s390_cc_set(2);
- if_condition_goto(binop(Iop_CmpLT32U, unop(Iop_8Uto32, mkexpr(byte2)),
- unop(Iop_8Uto32, mkexpr(byte1))),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpLT32U, unop(Iop_8Uto32, mkexpr(byte2)),
+ unop(Iop_8Uto32, mkexpr(byte1))));
// else: all equal, no end yet, loop
put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
put_gpr_dw0(r1, binop(Iop_Add64, get_gpr_dw0(r1), mkU64(1)));
put_gpr_dw0(r2, binop(Iop_Add64, get_gpr_dw0(r2), mkU64(1)));
- stmt(IRStmt_Exit(binop(Iop_CmpNE64, mkexpr(counter), mkU64(255)),
- Ijk_Boring, IRConst_U64(guest_IA_curr_instr)));
- // >= 256 bytes done CC=3
- s390_cc_set(3);
- put_counter_dw0(mkU64(0));
+
+ iterate();
return "clst";
}
@@ -9270,7 +9274,7 @@
}
static void
-s390_irgen_XONC(IROp op, UChar length, IRTemp start1, IRTemp start2)
+s390_irgen_xonc(IROp op, IRTemp length, IRTemp start1, IRTemp start2)
{
IRTemp old1 = newTemp(Ity_I8);
IRTemp old2 = newTemp(Ity_I8);
@@ -9300,8 +9304,7 @@
/* Check for end of field */
put_counter_w0(binop(Iop_Add32, mkexpr(counter), mkU32(1)));
- if_condition_goto(binop(Iop_CmpNE32, mkexpr(counter), mkU32(length)),
- guest_IA_curr_instr);
+ iterate_if(binop(Iop_CmpNE32, mkexpr(counter), mkexpr(length)));
s390_cc_thunk_put1(S390_CC_OP_BITWISE, mktemp(Ity_I32, get_counter_w1()),
False);
put_counter_dw0(mkU64(0));
@@ -9310,7 +9313,10 @@
static HChar *
s390_irgen_XC(UChar length, IRTemp start1, IRTemp start2)
{
- s390_irgen_XONC(Iop_Xor8, length, start1, start2);
+ IRTemp len = newTemp(Ity_I32);
+
+ assign(len, mkU32(length));
+ s390_irgen_xonc(Iop_Xor8, len, start1, start2);
return "xc";
}
@@ -9341,8 +9347,7 @@
/* Check for end of field */
put_counter_w0(binop(Iop_Add32, mkexpr(counter), mkU32(1)));
- if_condition_goto(binop(Iop_CmpNE32, mkexpr(counter), mkU32(length)),
- guest_IA_curr_instr);
+ iterate_if(binop(Iop_CmpNE32, mkexpr(counter), mkU32(length)));
/* Reset counter */
put_counter_dw0(mkU64(0));
@@ -9357,7 +9362,10 @@
static HChar *
s390_irgen_NC(UChar length, IRTemp start1, IRTemp start2)
{
- s390_irgen_XONC(Iop_And8, length, start1, start2);
+ IRTemp len = newTemp(Ity_I32);
+
+ assign(len, mkU32(length));
+ s390_irgen_xonc(Iop_And8, len, start1, start2);
return "nc";
}
@@ -9365,7 +9373,10 @@
static HChar *
s390_irgen_OC(UChar length, IRTemp start1, IRTemp start2)
{
- s390_irgen_XONC(Iop_Or8, length, start1, start2);
+ IRTemp len = newTemp(Ity_I32);
+
+ assign(len, mkU32(length));
+ s390_irgen_xonc(Iop_Or8, len, start1, start2);
return "oc";
}
@@ -9374,18 +9385,10 @@
static HChar *
s390_irgen_MVC(UChar length, IRTemp start1, IRTemp start2)
{
- IRTemp counter = newTemp(Ity_I64);
+ IRTemp len = newTemp(Ity_I64);
- assign(counter, get_counter_dw0());
-
- store(binop(Iop_Add64, mkexpr(start1), mkexpr(counter)),
- load(Ity_I8, binop(Iop_Add64, mkexpr(start2), mkexpr(counter))));
-
- /* Check for end of field */
- put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
- if_condition_goto(binop(Iop_CmpNE64, mkexpr(counter), mkU64(length)),
- guest_IA_curr_instr);
- put_counter_dw0(mkU64(0));
+ assign(len, mkU64(length));
+ s390_irgen_MVC_EX(len, start1, start2);
return "mvc";
}
@@ -9413,8 +9416,7 @@
/* len1 == 0 ? */
s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, len1, len2, False);
- if_condition_goto(binop(Iop_CmpEQ32, mkexpr(len1), mkU32(0)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ32, mkexpr(len1), mkU32(0)));
/* Check for destructive overlap:
addr1 > addr2 && addr2 + len1 > addr1 && (addr2 + len2) > addr1 */
@@ -9434,12 +9436,11 @@
binop(Iop_Add64, mkexpr(addr2),
unop(Iop_32Uto64, mkexpr(len2))))));
- if_condition_goto(binop(Iop_CmpEQ32,
- binop(Iop_And32,
- binop(Iop_And32, mkexpr(cond1), mkexpr(cond2)),
- mkexpr(cond3)),
- mkU32(1)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ32,
+ binop(Iop_And32,
+ binop(Iop_And32, mkexpr(cond1), mkexpr(cond2)),
+ mkexpr(cond3)),
+ mkU32(1)));
/* See s390_irgen_CLCL for explanation why we cannot load directly
and need two steps. */
@@ -9469,8 +9470,7 @@
binop(Iop_Sub32, mkexpr(r2p1), mkU32(1))));
s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, len1, len2, False);
- if_condition_goto(binop(Iop_CmpNE32, mkexpr(len1), mkU32(1)),
- guest_IA_curr_instr);
+ iterate_if(binop(Iop_CmpNE32, mkexpr(len1), mkU32(1)));
return "mvcl";
}
@@ -9495,8 +9495,7 @@
// len1 == 0 ?
s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, len1, len3, False);
- if_condition_goto(binop(Iop_CmpEQ64,mkexpr(len1), mkU64(0)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ64,mkexpr(len1), mkU64(0)));
/* This is a hack to prevent mvcle from reading from addr3 if it
should read from the pad. Since the pad has no address, just
@@ -9524,19 +9523,8 @@
mkite(binop(Iop_CmpEQ64, mkexpr(len3), mkU64(0)),
mkU64(0), binop(Iop_Sub64, mkexpr(len3), mkU64(1))));
- /* We should set CC=3 (faked by overflow add) and leave after
- a maximum of ~4096 bytes have been processed. This is simpler:
- we leave whenever (len1 % 4096) == 0 */
- s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_ADD_64, mktemp(Ity_I64, mkU64(-1ULL)),
- mktemp(Ity_I64, mkU64(-1ULL)), False);
- if_condition_goto(binop(Iop_CmpEQ64,
- binop(Iop_And64, mkexpr(len1), mkU64(0xfff)),
- mkU64(0)),
- guest_IA_next_instr);
-
s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, len1, len3, False);
- if_condition_goto(binop(Iop_CmpNE64, mkexpr(len1), mkU64(1)),
- guest_IA_curr_instr);
+ iterate_if(binop(Iop_CmpNE64, mkexpr(len1), mkU64(1)));
return "mvcle";
}
@@ -9559,8 +9547,7 @@
// We use unlimited as cpu-determined number
put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
- if_condition_goto(binop(Iop_CmpNE8, mkexpr(end), mkexpr(byte)),
- guest_IA_curr_instr);
+ iterate_if(binop(Iop_CmpNE8, mkexpr(end), mkexpr(byte)));
// and always set cc=1 at the end + update r1
s390_cc_set(1);
@@ -9831,8 +9818,7 @@
Otherwise, store the old_value from memory in r1 and yield. */
assign(nequal, binop(Iop_CmpNE32, s390_call_calculate_cc(), mkU32(0)));
put_gpr_w1(r1, mkite(mkexpr(nequal), mkexpr(old_mem), mkexpr(op1)));
- stmt(IRStmt_Exit(mkexpr(nequal), Ijk_Yield,
- IRConst_U64(guest_IA_next_instr)));
+ yield_if(mkexpr(nequal));
}
static HChar *
@@ -9880,12 +9866,118 @@
Otherwise, store the old_value from memory in r1 and yield. */
assign(nequal, binop(Iop_CmpNE32, s390_call_calculate_cc(), mkU32(0)));
put_gpr_dw0(r1, mkite(mkexpr(nequal), mkexpr(old_mem), mkexpr(op1)));
- stmt(IRStmt_Exit(mkexpr(nequal), Ijk_Yield,
- IRConst_U64(guest_IA_next_instr)));
+ yield_if(mkexpr(nequal));
return "csg";
}
+/* Implementation for 32-bit compare-double-and-swap */
+static void
+s390_irgen_cdas_32(UChar r1, UChar r3, IRTemp op2addr)
+{
+ IRCAS *cas;
+ IRTemp op1_high = newTemp(Ity_I32);
+ IRTemp op1_low = newTemp(Ity_I32);
+ IRTemp old_mem_high = newTemp(Ity_I32);
+ IRTemp old_mem_low = newTemp(Ity_I32);
+ IRTemp op3_high = newTemp(Ity_I32);
+ IRTemp op3_low = newTemp(Ity_I32);
+ IRTemp result = newTemp(Ity_I32);
+ IRTemp nequal = newTemp(Ity_I1);
+
+ assign(op1_high, get_gpr_w1(r1));
+ assign(op1_low, get_gpr_w1(r1+1));
+ assign(op3_high, get_gpr_w1(r3));
+ assign(op3_low, get_gpr_w1(r3+1));
+
+ /* The first and second operands are compared. If they are equal,
+ the third operand is stored at the second-operand location. */
+ cas = mkIRCAS(old_mem_high, old_mem_low,
+ Iend_BE, mkexpr(op2addr),
+ mkexpr(op1_high), mkexpr(op1_low), /* expected value */
+ mkexpr(op3_high), mkexpr(op3_low) /* new value */);
+ stmt(IRStmt_CAS(cas));
+
+ /* Set CC. Operands compared equal -> 0, else 1. */
+ assign(result, unop(Iop_1Uto32,
+ binop(Iop_CmpNE32,
+ binop(Iop_Or32,
+ binop(Iop_Xor32, mkexpr(op1_high), mkexpr(old_mem_high)),
+ binop(Iop_Xor32, mkexpr(op1_low), mkexpr(old_mem_low))),
+ mkU32(0))));
+
+ s390_cc_thunk_put1(S390_CC_OP_BITWISE, result, False);
+
+ /* If operands were equal (cc == 0) just store the old value op1 in r1.
+ Otherwise, store the old_value from memory in r1 and yield. */
+ assign(nequal, binop(Iop_CmpNE32, s390_call_calculate_cc(), mkU32(0)));
+ put_gpr_w1(r1, mkite(mkexpr(nequal), mkexpr(old_mem_high), mkexpr(op1_high)));
+ put_gpr_w1(r1+1, mkite(mkexpr(nequal), mkexpr(old_mem_low), mkexpr(op1_low)));
+ yield_if(mkexpr(nequal));
+}
+
+static HChar *
+s390_irgen_CDS(UChar r1, UChar r3, IRTemp op2addr)
+{
+ s390_irgen_cdas_32(r1, r3, op2addr);
+
+ return "cds";
+}
+
+static HChar *
+s390_irgen_CDSY(UChar r1, UChar r3, IRTemp op2addr)
+{
+ s390_irgen_cdas_32(r1, r3, op2addr);
+
+ return "cdsy";
+}
+
+static HChar *
+s390_irgen_CDSG(UChar r1, UChar r3, IRTemp op2addr)
+{
+ IRCAS *cas;
+ IRTemp op1_high = newTemp(Ity_I64);
+ IRTemp op1_low = newTemp(Ity_I64);
+ IRTemp old_mem_high = newTemp(Ity_I64);
+ IRTemp old_mem_low = newTemp(Ity_I64);
+ IRTemp op3_high = newTemp(Ity_I64);
+ IRTemp op3_low = newTemp(Ity_I64);
+ IRTemp result = newTemp(Ity_I64);
+ IRTemp nequal = newTemp(Ity_I1);
+
+ assign(op1_high, get_gpr_dw0(r1));
+ assign(op1_low, get_gpr_dw0(r1+1));
+ assign(op3_high, get_gpr_dw0(r3));
+ assign(op3_low, get_gpr_dw0(r3+1));
+
+ /* The first and second operands are compared. If they are equal,
+ the third operand is stored at the second-operand location. */
+ cas = mkIRCAS(old_mem_high, old_mem_low,
+ Iend_BE, mkexpr(op2addr),
+ mkexpr(op1_high), mkexpr(op1_low), /* expected value */
+ mkexpr(op3_high), mkexpr(op3_low) /* new value */);
+ stmt(IRStmt_CAS(cas));
+
+ /* Set CC. Operands compared equal -> 0, else 1. */
+ assign(result, unop(Iop_1Uto64,
+ binop(Iop_CmpNE64,
+ binop(Iop_Or64,
+ binop(Iop_Xor64, mkexpr(op1_high), mkexpr(old_mem_high)),
+ binop(Iop_Xor64, mkexpr(op1_low), mkexpr(old_mem_low))),
+ mkU64(0))));
+
+ s390_cc_thunk_put1(S390_CC_OP_BITWISE, result, False);
+
+ /* If operands were equal (cc == 0) just store the old value op1 in r1.
+ Otherwise, store the old_value from memory in r1 and yield. */
+ assign(nequal, binop(Iop_CmpNE32, s390_call_calculate_cc(), mkU32(0)));
+ put_gpr_dw0(r1, mkite(mkexpr(nequal), mkexpr(old_mem_high), mkexpr(op1_high)));
+ put_gpr_dw0(r1+1, mkite(mkexpr(nequal), mkexpr(old_mem_low), mkexpr(op1_low)));
+ yield_if(mkexpr(nequal));
+
+ return "cdsg";
+}
+
/* Binary floating point */
@@ -10543,24 +10635,6 @@
}
-static UInt
-s390_do_cvb(ULong decimal)
-{
-#if defined(VGA_s390x)
- UInt binary;
-
- __asm__ volatile (
- "cvb %[result],%[input]\n\t"
- : [result] "=d"(binary)
- : [input] "m"(decimal)
- );
-
- return binary;
-#else
- return 0;
-#endif
-}
-
static IRExpr *
s390_call_cvb(IRExpr *in)
{
@@ -10593,25 +10667,6 @@
}
-static ULong
-s390_do_cvd(ULong binary_in)
-{
-#if defined(VGA_s390x)
- UInt binary = binary_in & 0xffffffffULL;
- ULong decimal;
-
- __asm__ volatile (
- "cvd %[input],%[result]\n\t"
- : [result] "=m"(decimal)
- : [input] "d"(binary)
- );
-
- return decimal;
-#else
- return 0;
-#endif
-}
-
static IRExpr *
s390_call_cvd(IRExpr *in)
{
@@ -10630,7 +10685,7 @@
static HChar *
s390_irgen_CVD(UChar r1, IRTemp op2addr)
{
- store(mkexpr(op2addr), s390_call_cvd(get_gpr_w1(r1)));
+ store(mkexpr(op2addr), s390_call_cvd(unop(Iop_32Uto64, get_gpr_w1(r1))));
return "cvd";
}
@@ -10764,10 +10819,12 @@
d->needsBBP = 1; /* Need to pass pointer to guest state to helper */
+ d->nFxState = 1;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
+
d->fxState[0].fx = Ifx_Modify; /* read then write */
d->fxState[0].offset = S390X_GUEST_OFFSET(guest_r0);
d->fxState[0].size = sizeof(ULong);
- d->nFxState = 1;
d->mAddr = mkexpr(op2addr);
/* Pretend all double words are written */
@@ -10802,8 +10859,7 @@
s390_cc_set(0);
/* If length is zero, there is no need to calculate the checksum */
- if_condition_goto(binop(Iop_CmpEQ64, mkexpr(len), mkU64(0)),
- guest_IA_next_instr);
+ next_insn_if(binop(Iop_CmpEQ64, mkexpr(len), mkU64(0)));
/* Assiging the increment variable to adjust address and length
later on. */
@@ -10841,12 +10897,858 @@
put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(addr), mkexpr(inc)));
put_gpr_dw0(r2+1, binop(Iop_Sub64, mkexpr(len), mkexpr(inc)));
- if_condition_goto(binop(Iop_CmpNE64, mkexpr(len), mkU64(0)),
- guest_IA_curr_instr);
+ iterate_if(binop(Iop_CmpNE64, mkexpr(len), mkU64(0)));
return "cksm";
}
+static HChar *
+s390_irgen_TROO(UChar m3, UChar r1, UChar r2)
+{
+ IRTemp src_addr, des_addr, tab_addr, src_len, test_byte;
+ src_addr = newTemp(Ity_I64);
+ des_addr = newTemp(Ity_I64);
+ tab_addr = newTemp(Ity_I64);
+ test_byte = newTemp(Ity_I8);
+ src_len = newTemp(Ity_I64);
+
+ assign(src_addr, get_gpr_dw0(r2));
+ assign(des_addr, get_gpr_dw0(r1));
+ assign(tab_addr, get_gpr_dw0(1));
+ assign(src_len, get_gpr_dw0(r1+1));
+ assign(test_byte, get_gpr_b7(0));
+
+ IRTemp op = newTemp(Ity_I8);
+ IRTemp op1 = newTemp(Ity_I8);
+ IRTemp result = newTemp(Ity_I64);
+
+ /* End of source string? We're done; proceed to next insn */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpEQ64, mkexpr(src_len), mkU64(0)));
+
+ /* Load character from source string, index translation table and
+ store translated character in op1. */
+ assign(op, load(Ity_I8, mkexpr(src_addr)));
+
+ assign(result, binop(Iop_Add64, unop(Iop_8Uto64, mkexpr(op)),
+ mkexpr(tab_addr)));
+ assign(op1, load(Ity_I8, mkexpr(result)));
+
+ if (! s390_host_has_etf2 || (m3 & 0x1) == 0) {
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpEQ8, mkexpr(op1), mkexpr(test_byte)));
+ }
+ store(get_gpr_dw0(r1), mkexpr(op1));
+
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(des_addr), mkU64(1)));
+ put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(src_addr), mkU64(1)));
+ put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(1)));
+
+ iterate();
+
+ return "troo";
+}
+
+static HChar *
+s390_irgen_TRTO(UChar m3, UChar r1, UChar r2)
+{
+ IRTemp src_addr, des_addr, tab_addr, src_len, test_byte;
+ src_addr = newTemp(Ity_I64);
+ des_addr = newTemp(Ity_I64);
+ tab_addr = newTemp(Ity_I64);
+ test_byte = newTemp(Ity_I8);
+ src_len = newTemp(Ity_I64);
+
+ assign(src_addr, get_gpr_dw0(r2));
+ assign(des_addr, get_gpr_dw0(r1));
+ assign(tab_addr, get_gpr_dw0(1));
+ assign(src_len, get_gpr_dw0(r1+1));
+ assign(test_byte, get_gpr_b7(0));
+
+ IRTemp op = newTemp(Ity_I16);
+ IRTemp op1 = newTemp(Ity_I8);
+ IRTemp result = newTemp(Ity_I64);
+
+ /* End of source string? We're done; proceed to next insn */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpEQ64, mkexpr(src_len), mkU64(0)));
+
+ /* Load character from source string, index translation table and
+ store translated character in op1. */
+ assign(op, load(Ity_I16, mkexpr(src_addr)));
+
+ assign(result, binop(Iop_Add64, unop(Iop_16Uto64, mkexpr(op)),
+ mkexpr(tab_addr)));
+
+ assign(op1, load(Ity_I8, mkexpr(result)));
+
+ if (! s390_host_has_etf2 || (m3 & 0x1) == 0) {
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpEQ8, mkexpr(op1), mkexpr(test_byte)));
+ }
+ store(get_gpr_dw0(r1), mkexpr(op1));
+
+ put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(src_addr), mkU64(2)));
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(des_addr), mkU64(1)));
+ put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(2)));
+
+ iterate();
+
+ return "trto";
+}
+
+static HChar *
+s390_irgen_TROT(UChar m3, UChar r1, UChar r2)
+{
+ IRTemp src_addr, des_addr, tab_addr, src_len, test_byte;
+ src_addr = newTemp(Ity_I64);
+ des_addr = newTemp(Ity_I64);
+ tab_addr = newTemp(Ity_I64);
+ test_byte = newTemp(Ity_I16);
+ src_len = newTemp(Ity_I64);
+
+ assign(src_addr, get_gpr_dw0(r2));
+ assign(des_addr, get_gpr_dw0(r1));
+ assign(tab_addr, get_gpr_dw0(1));
+ assign(src_len, get_gpr_dw0(r1+1));
+ assign(test_byte, get_gpr_hw3(0));
+
+ IRTemp op = newTemp(Ity_I8);
+ IRTemp op1 = newTemp(Ity_I16);
+ IRTemp result = newTemp(Ity_I64);
+
+ /* End of source string? We're done; proceed to next insn */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpEQ64, mkexpr(src_len), mkU64(0)));
+
+ /* Load character from source string, index translation table and
+ store translated character in op1. */
+ assign(op, binop(Iop_Shl8, load(Ity_I8, mkexpr(src_addr)), mkU8(1)));
+
+ assign(result, binop(Iop_Add64, unop(Iop_8Uto64, mkexpr(op)),
+ mkexpr(tab_addr)));
+ assign(op1, load(Ity_I16, mkexpr(result)));
+
+ if (! s390_host_has_etf2 || (m3 & 0x1) == 0) {
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpEQ16, mkexpr(op1), mkexpr(test_byte)));
+ }
+ store(get_gpr_dw0(r1), mkexpr(op1));
+
+ put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(src_addr), mkU64(1)));
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(des_addr), mkU64(2)));
+ put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(1)));
+
+ iterate();
+
+ return "trot";
+}
+
+static HChar *
+s390_irgen_TRTT(UChar m3, UChar r1, UChar r2)
+{
+ IRTemp src_addr, des_addr, tab_addr, src_len, test_byte;
+ src_addr = newTemp(Ity_I64);
+ des_addr = newTemp(Ity_I64);
+ tab_addr = newTemp(Ity_I64);
+ test_byte = newTemp(Ity_I16);
+ src_len = newTemp(Ity_I64);
+
+ assign(src_addr, get_gpr_dw0(r2));
+ assign(des_addr, get_gpr_dw0(r1));
+ assign(tab_addr, get_gpr_dw0(1));
+ assign(src_len, get_gpr_dw0(r1+1));
+ assign(test_byte, get_gpr_hw3(0));
+
+ IRTemp op = newTemp(Ity_I16);
+ IRTemp op1 = newTemp(Ity_I16);
+ IRTemp result = newTemp(Ity_I64);
+
+ /* End of source string? We're done; proceed to next insn */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpEQ64, mkexpr(src_len), mkU64(0)));
+
+ /* Load character from source string, index translation table and
+ store translated character in op1. */
+ assign(op, binop(Iop_Shl16, load(Ity_I16, mkexpr(src_addr)), mkU8(1)));
+
+ assign(result, binop(Iop_Add64, unop(Iop_16Uto64, mkexpr(op)),
+ mkexpr(tab_addr)));
+ assign(op1, load(Ity_I16, mkexpr(result)));
+
+ if (! s390_host_has_etf2 || (m3 & 0x1) == 0) {
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpEQ16, mkexpr(op1), mkexpr(test_byte)));
+ }
+
+ store(get_gpr_dw0(r1), mkexpr(op1));
+
+ put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(src_addr), mkU64(2)));
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(des_addr), mkU64(2)));
+ put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(2)));
+
+ iterate();
+
+ return "trtt";
+}
+
+static HChar *
+s390_irgen_TR(UChar length, IRTemp start1, IRTemp start2)
+{
+ IRTemp len = newTemp(Ity_I64);
+
+ assign(len, mkU64(length));
+ s390_irgen_TR_EX(len, start1, start2);
+
+ return "tr";
+}
+
+static HChar *
+s390_irgen_TRE(UChar r1,UChar r2)
+{
+ IRTemp src_addr, tab_addr, src_len, test_byte;
+ src_addr = newTemp(Ity_I64);
+ tab_addr = newTemp(Ity_I64);
+ src_len = newTemp(Ity_I64);
+ test_byte = newTemp(Ity_I8);
+
+ assign(src_addr, get_gpr_dw0(r1));
+ assign(src_len, get_gpr_dw0(r1+1));
+ assign(tab_addr, get_gpr_dw0(r2));
+ assign(test_byte, get_gpr_b7(0));
+
+ IRTemp op = newTemp(Ity_I8);
+ IRTemp op1 = newTemp(Ity_I8);
+ IRTemp result = newTemp(Ity_I64);
+
+ /* End of source string? We're done; proceed to next insn */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpEQ64, mkexpr(src_len), mkU64(0)));
+
+ /* Load character from source string and compare with test byte */
+ assign(op, load(Ity_I8, mkexpr(src_addr)));
+
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpEQ8, mkexpr(op), mkexpr(test_byte)));
+
+ assign(result, binop(Iop_Add64, unop(Iop_8Uto64, mkexpr(op)),
+ mkexpr(tab_addr)));
+
+ assign(op1, load(Ity_I8, mkexpr(result)));
+
+ store(get_gpr_dw0(r1), mkexpr(op1));
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(src_addr), mkU64(1)));
+ put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(1)));
+
+ iterate();
+
+ return "tre";
+}
+
+static IRExpr *
+s390_call_cu21(IRExpr *srcval, IRExpr *low_surrogate)
+{
+ IRExpr **args, *call;
+ args = mkIRExprVec_2(srcval, low_surrogate);
+ call = mkIRExprCCall(Ity_I64, 0 /*regparm*/,
+ "s390_do_cu21", &s390_do_cu21, args);
+
+ /* Nothing is excluded from definedness checking. */
+ call->Iex.CCall.cee->mcx_mask = 0;
+
+ return call;
+}
+
+static HChar *
+s390_irgen_CU21(UChar m3, UChar r1, UChar r2)
+{
+ IRTemp addr1 = newTemp(Ity_I64);
+ IRTemp addr2 = newTemp(Ity_I64);
+ IRTemp len1 = newTemp(Ity_I64);
+ IRTemp len2 = newTemp(Ity_I64);
+
+ assign(addr1, get_gpr_dw0(r1));
+ assign(addr2, get_gpr_dw0(r2));
+ assign(len1, get_gpr_dw0(r1 + 1));
+ assign(len2, get_gpr_dw0(r2 + 1));
+
+ /* We're processing the 2nd operand 2 bytes at a time. Therefore, if
+ there are less than 2 bytes left, then the 2nd operand is exhausted
+ and we're done here. cc = 0 */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len2), mkU64(2)));
+
+ /* There are at least two bytes there. Read them. */
+ IRTemp srcval = newTemp(Ity_I32);
+ assign(srcval, unop(Iop_16Uto32, load(Ity_I16, mkexpr(addr2))));
+
+ /* Find out whether this is a high surrogate. I.e. SRCVAL lies
+ inside the interval [0xd800 - 0xdbff] */
+ IRTemp is_high_surrogate = newTemp(Ity_I32);
+ IRExpr *flag1 = mkite(binop(Iop_CmpLE32U, mkU32(0xd800), mkexpr(srcval)),
+ mkU32(1), mkU32(0));
+ IRExpr *flag2 = mkite(binop(Iop_CmpLE32U, mkexpr(srcval), mkU32(0xdbff)),
+ mkU32(1), mkU32(0));
+ assign(is_high_surrogate, binop(Iop_And32, flag1, flag2));
+
+ /* If SRCVAL is a high surrogate and there are less than 4 bytes left,
+ then the 2nd operand is exhausted and we're done here. cc = 0 */
+ IRExpr *not_enough_bytes =
+ mkite(binop(Iop_CmpLT64U, mkexpr(len2), mkU64(4)), mkU32(1), mkU32(0));
+
+ next_insn_if(binop(Iop_CmpEQ32,
+ binop(Iop_And32, mkexpr(is_high_surrogate),
+ not_enough_bytes), mkU32(1)));
+
+ /* The 2nd operand is not exhausted. If the first 2 bytes are a high
+ surrogate, read the next two bytes (low surrogate). */
+ IRTemp low_surrogate = newTemp(Ity_I32);
+ IRExpr *low_surrogate_addr = binop(Iop_Add64, mkexpr(addr2), mkU64(2));
+
+ assign(low_surrogate,
+ mkite(binop(Iop_CmpEQ32, mkexpr(is_high_surrogate), mkU32(1)),
+ unop(Iop_16Uto32, load(Ity_I16, low_surrogate_addr)),
+ mkU32(0))); // any value is fine; it will not be used
+
+ /* Call the helper */
+ IRTemp retval = newTemp(Ity_I64);
+ assign(retval, s390_call_cu21(unop(Iop_32Uto64, mkexpr(srcval)),
+ unop(Iop_32Uto64, mkexpr(low_surrogate))));
+
+ /* Before we can test whether the 1st operand is exhausted we need to
+ test for an invalid low surrogate. Because cc=2 outranks cc=1. */
+ if (s390_host_has_etf3 && (m3 & 0x1) == 1) {
+ IRExpr *invalid_low_surrogate =
+ binop(Iop_And64, mkexpr(retval), mkU64(0xff));
+
+ s390_cc_set(2);
+ next_insn_if(binop(Iop_CmpEQ64, invalid_low_surrogate, mkU64(1)));
+ }
+
+ /* Now test whether the 1st operand is exhausted */
+ IRTemp num_bytes = newTemp(Ity_I64);
+ assign(num_bytes, binop(Iop_And64,
+ binop(Iop_Shr64, mkexpr(retval), mkU8(8)),
+ mkU64(0xff)));
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len1), mkexpr(num_bytes)));
+
+ /* Extract the bytes to be stored at addr1 */
+ IRTemp data = newTemp(Ity_I64);
+ assign(data, binop(Iop_Shr64, mkexpr(retval), mkU8(16)));
+
+ /* To store the bytes construct 4 dirty helper calls. The helper calls
+ are guarded (num_bytes == 1, num_bytes == 2, etc) such that only
+ one of them will be called at runtime. */
+ int i;
+ for (i = 1; i <= 4; ++i) {
+ IRDirty *d;
+
+ d = unsafeIRDirty_0_N(0 /* regparms */, "s390x_dirtyhelper_CUxy",
+ &s390x_dirtyhelper_CUxy,
+ mkIRExprVec_3(mkexpr(addr1), mkexpr(data),
+ mkexpr(num_bytes)));
+ d->guard = binop(Iop_CmpEQ64, mkexpr(num_bytes), mkU64(i));
+ d->mFx = Ifx_Write;
+ d->mAddr = mkexpr(addr1);
+ d->mSize = i;
+ stmt(IRStmt_Dirty(d));
+ }
+
+ /* Update source address and length */
+ IRTemp num_src_bytes = newTemp(Ity_I64);
+ assign(num_src_bytes,
+ mkite(binop(Iop_CmpEQ32, mkexpr(is_high_surrogate), mkU32(1)),
+ mkU64(4), mkU64(2)));
+ put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(addr2), mkexpr(num_src_bytes)));
+ put_gpr_dw0(r2 + 1, binop(Iop_Sub64, mkexpr(len2), mkexpr(num_src_bytes)));
+
+ /* Update destination address and length */
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(addr1), mkexpr(num_bytes)));
+ put_gpr_dw0(r1 + 1, binop(Iop_Sub64, mkexpr(len1), mkexpr(num_bytes)));
+
+ iterate();
+
+ return "cu21";
+}
+
+static IRExpr *
+s390_call_cu24(IRExpr *srcval, IRExpr *low_surrogate)
+{
+ IRExpr **args, *call;
+ args = mkIRExprVec_2(srcval, low_surrogate);
+ call = mkIRExprCCall(Ity_I64, 0 /*regparm*/,
+ "s390_do_cu24", &s390_do_cu24, args);
+
+ /* Nothing is excluded from definedness checking. */
+ call->Iex.CCall.cee->mcx_mask = 0;
+
+ return call;
+}
+
+static HChar *
+s390_irgen_CU24(UChar m3, UChar r1, UChar r2)
+{
+ IRTemp addr1 = newTemp(Ity_I64);
+ IRTemp addr2 = newTemp(Ity_I64);
+ IRTemp len1 = newTemp(Ity_I64);
+ IRTemp len2 = newTemp(Ity_I64);
+
+ assign(addr1, get_gpr_dw0(r1));
+ assign(addr2, get_gpr_dw0(r2));
+ assign(len1, get_gpr_dw0(r1 + 1));
+ assign(len2, get_gpr_dw0(r2 + 1));
+
+ /* We're processing the 2nd operand 2 bytes at a time. Therefore, if
+ there are less than 2 bytes left, then the 2nd operand is exhausted
+ and we're done here. cc = 0 */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len2), mkU64(2)));
+
+ /* There are at least two bytes there. Read them. */
+ IRTemp srcval = newTemp(Ity_I32);
+ assign(srcval, unop(Iop_16Uto32, load(Ity_I16, mkexpr(addr2))));
+
+ /* Find out whether this is a high surrogate. I.e. SRCVAL lies
+ inside the interval [0xd800 - 0xdbff] */
+ IRTemp is_high_surrogate = newTemp(Ity_I32);
+ IRExpr *flag1 = mkite(binop(Iop_CmpLE32U, mkU32(0xd800), mkexpr(srcval)),
+ mkU32(1), mkU32(0));
+ IRExpr *flag2 = mkite(binop(Iop_CmpLE32U, mkexpr(srcval), mkU32(0xdbff)),
+ mkU32(1), mkU32(0));
+ assign(is_high_surrogate, binop(Iop_And32, flag1, flag2));
+
+ /* If SRCVAL is a high surrogate and there are less than 4 bytes left,
+ then the 2nd operand is exhausted and we're done here. cc = 0 */
+ IRExpr *not_enough_bytes =
+ mkite(binop(Iop_CmpLT64U, mkexpr(len2), mkU64(4)), mkU32(1), mkU32(0));
+
+ next_insn_if(binop(Iop_CmpEQ32,
+ binop(Iop_And32, mkexpr(is_high_surrogate),
+ not_enough_bytes),
+ mkU32(1)));
+
+ /* The 2nd operand is not exhausted. If the first 2 bytes are a high
+ surrogate, read the next two bytes (low surrogate). */
+ IRTemp low_surrogate = newTemp(Ity_I32);
+ IRExpr *low_surrogate_addr = binop(Iop_Add64, mkexpr(addr2), mkU64(2));
+
+ assign(low_surrogate,
+ mkite(binop(Iop_CmpEQ32, mkexpr(is_high_surrogate), mkU32(1)),
+ unop(Iop_16Uto32, load(Ity_I16, low_surrogate_addr)),
+ mkU32(0))); // any value is fine; it will not be used
+
+ /* Call the helper */
+ IRTemp retval = newTemp(Ity_I64);
+ assign(retval, s390_call_cu24(unop(Iop_32Uto64, mkexpr(srcval)),
+ unop(Iop_32Uto64, mkexpr(low_surrogate))));
+
+ /* Before we can test whether the 1st operand is exhausted we need to
+ test for an invalid low surrogate. Because cc=2 outranks cc=1. */
+ if (s390_host_has_etf3 && (m3 & 0x1) == 1) {
+ IRExpr *invalid_low_surrogate =
+ binop(Iop_And64, mkexpr(retval), mkU64(0xff));
+
+ s390_cc_set(2);
+ next_insn_if(binop(Iop_CmpEQ64, invalid_low_surrogate, mkU64(1)));
+ }
+
+ /* Now test whether the 1st operand is exhausted */
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len1), mkU64(4)));
+
+ /* Extract the bytes to be stored at addr1 */
+ IRExpr *data = unop(Iop_64to32, binop(Iop_Shr64, mkexpr(retval), mkU8(8)));
+
+ store(mkexpr(addr1), data);
+
+ /* Update source address and length */
+ IRTemp num_src_bytes = newTemp(Ity_I64);
+ assign(num_src_bytes,
+ mkite(binop(Iop_CmpEQ32, mkexpr(is_high_surrogate), mkU32(1)),
+ mkU64(4), mkU64(2)));
+ put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(addr2), mkexpr(num_src_bytes)));
+ put_gpr_dw0(r2 + 1, binop(Iop_Sub64, mkexpr(len2), mkexpr(num_src_bytes)));
+
+ /* Update destination address and length */
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(addr1), mkU64(4)));
+ put_gpr_dw0(r1 + 1, binop(Iop_Sub64, mkexpr(len1), mkU64(4)));
+
+ iterate();
+
+ return "cu24";
+}
+
+static IRExpr *
+s390_call_cu42(IRExpr *srcval)
+{
+ IRExpr **args, *call;
+ args = mkIRExprVec_1(srcval);
+ call = mkIRExprCCall(Ity_I64, 0 /*regparm*/,
+ "s390_do_cu42", &s390_do_cu42, args);
+
+ /* Nothing is excluded from definedness checking. */
+ call->Iex.CCall.cee->mcx_mask = 0;
+
+ return call;
+}
+
+static HChar *
+s390_irgen_CU42(UChar r1, UChar r2)
+{
+ IRTemp addr1 = newTemp(Ity_I64);
+ IRTemp addr2 = newTemp(Ity_I64);
+ IRTemp len1 = newTemp(Ity_I64);
+ IRTemp len2 = newTemp(Ity_I64);
+
+ assign(addr1, get_gpr_dw0(r1));
+ assign(addr2, get_gpr_dw0(r2));
+ assign(len1, get_gpr_dw0(r1 + 1));
+ assign(len2, get_gpr_dw0(r2 + 1));
+
+ /* We're processing the 2nd operand 4 bytes at a time. Therefore, if
+ there are less than 4 bytes left, then the 2nd operand is exhausted
+ and we're done here. cc = 0 */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len2), mkU64(4)));
+
+ /* Read the 2nd operand. */
+ IRTemp srcval = newTemp(Ity_I32);
+ assign(srcval, load(Ity_I32, mkexpr(addr2)));
+
+ /* Call the helper */
+ IRTemp retval = newTemp(Ity_I64);
+ assign(retval, s390_call_cu42(unop(Iop_32Uto64, mkexpr(srcval))));
+
+ /* If the UTF-32 character was invalid, set cc=2 and we're done.
+ cc=2 outranks cc=1 (1st operand exhausted) */
+ IRExpr *invalid_character = binop(Iop_And64, mkexpr(retval), mkU64(0xff));
+
+ s390_cc_set(2);
+ next_insn_if(binop(Iop_CmpEQ64, invalid_character, mkU64(1)));
+
+ /* Now test whether the 1st operand is exhausted */
+ IRTemp num_bytes = newTemp(Ity_I64);
+ assign(num_bytes, binop(Iop_And64,
+ binop(Iop_Shr64, mkexpr(retval), mkU8(8)),
+ mkU64(0xff)));
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len1), mkexpr(num_bytes)));
+
+ /* Extract the bytes to be stored at addr1 */
+ IRTemp data = newTemp(Ity_I64);
+ assign(data, binop(Iop_Shr64, mkexpr(retval), mkU8(16)));
+
+ /* To store the bytes construct 2 dirty helper calls. The helper calls
+ are guarded (num_bytes == 2 and num_bytes == 4, respectively) such
+ that only one of them will be called at runtime. */
+
+ Int i;
+ for (i = 2; i <= 4; ++i) {
+ IRDirty *d;
+
+ if (i == 3) continue; // skip this one
+
+ d = unsafeIRDirty_0_N(0 /* regparms */, "s390x_dirtyhelper_CUxy",
+ &s390x_dirtyhelper_CUxy,
+ mkIRExprVec_3(mkexpr(addr1), mkexpr(data),
+ mkexpr(num_bytes)));
+ d->guard = binop(Iop_CmpEQ64, mkexpr(num_bytes), mkU64(i));
+ d->mFx = Ifx_Write;
+ d->mAddr = mkexpr(addr1);
+ d->mSize = i;
+ stmt(IRStmt_Dirty(d));
+ }
+
+ /* Update source address and length */
+ put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(addr2), mkU64(4)));
+ put_gpr_dw0(r2 + 1, binop(Iop_Sub64, mkexpr(len2), mkU64(4)));
+
+ /* Update destination address and length */
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(addr1), mkexpr(num_bytes)));
+ put_gpr_dw0(r1 + 1, binop(Iop_Sub64, mkexpr(len1), mkexpr(num_bytes)));
+
+ iterate();
+
+ return "cu42";
+}
+
+static IRExpr *
+s390_call_cu41(IRExpr *srcval)
+{
+ IRExpr **args, *call;
+ args = mkIRExprVec_1(srcval);
+ call = mkIRExprCCall(Ity_I64, 0 /*regparm*/,
+ "s390_do_cu41", &s390_do_cu41, args);
+
+ /* Nothing is excluded from definedness checking. */
+ call->Iex.CCall.cee->mcx_mask = 0;
+
+ return call;
+}
+
+static HChar *
+s390_irgen_CU41(UChar r1, UChar r2)
+{
+ IRTemp addr1 = newTemp(Ity_I64);
+ IRTemp addr2 = newTemp(Ity_I64);
+ IRTemp len1 = newTemp(Ity_I64);
+ IRTemp len2 = newTemp(Ity_I64);
+
+ assign(addr1, get_gpr_dw0(r1));
+ assign(addr2, get_gpr_dw0(r2));
+ assign(len1, get_gpr_dw0(r1 + 1));
+ assign(len2, get_gpr_dw0(r2 + 1));
+
+ /* We're processing the 2nd operand 4 bytes at a time. Therefore, if
+ there are less than 4 bytes left, then the 2nd operand is exhausted
+ and we're done here. cc = 0 */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len2), mkU64(4)));
+
+ /* Read the 2nd operand. */
+ IRTemp srcval = newTemp(Ity_I32);
+ assign(srcval, load(Ity_I32, mkexpr(addr2)));
+
+ /* Call the helper */
+ IRTemp retval = newTemp(Ity_I64);
+ assign(retval, s390_call_cu41(unop(Iop_32Uto64, mkexpr(srcval))));
+
+ /* If the UTF-32 character was invalid, set cc=2 and we're done.
+ cc=2 outranks cc=1 (1st operand exhausted) */
+ IRExpr *invalid_character = binop(Iop_And64, mkexpr(retval), mkU64(0xff));
+
+ s390_cc_set(2);
+ next_insn_if(binop(Iop_CmpEQ64, invalid_character, mkU64(1)));
+
+ /* Now test whether the 1st operand is exhausted */
+ IRTemp num_bytes = newTemp(Ity_I64);
+ assign(num_bytes, binop(Iop_And64,
+ binop(Iop_Shr64, mkexpr(retval), mkU8(8)),
+ mkU64(0xff)));
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len1), mkexpr(num_bytes)));
+
+ /* Extract the bytes to be stored at addr1 */
+ IRTemp data = newTemp(Ity_I64);
+ assign(data, binop(Iop_Shr64, mkexpr(retval), mkU8(16)));
+
+ /* To store the bytes construct 4 dirty helper calls. The helper calls
+ are guarded (num_bytes == 1, num_bytes == 2, etc) such that only
+ one of them will be called at runtime. */
+ int i;
+ for (i = 1; i <= 4; ++i) {
+ IRDirty *d;
+
+ d = unsafeIRDirty_0_N(0 /* regparms */, "s390x_dirtyhelper_CUxy",
+ &s390x_dirtyhelper_CUxy,
+ mkIRExprVec_3(mkexpr(addr1), mkexpr(data),
+ mkexpr(num_bytes)));
+ d->guard = binop(Iop_CmpEQ64, mkexpr(num_bytes), mkU64(i));
+ d->mFx = Ifx_Write;
+ d->mAddr = mkexpr(addr1);
+ d->mSize = i;
+ stmt(IRStmt_Dirty(d));
+ }
+
+ /* Update source address and length */
+ put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(addr2), mkU64(4)));
+ put_gpr_dw0(r2 + 1, binop(Iop_Sub64, mkexpr(len2), mkU64(4)));
+
+ /* Update destination address and length */
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(addr1), mkexpr(num_bytes)));
+ put_gpr_dw0(r1 + 1, binop(Iop_Sub64, mkexpr(len1), mkexpr(num_bytes)));
+
+ iterate();
+
+ return "cu41";
+}
+
+static IRExpr *
+s390_call_cu12_cu14_helper1(IRExpr *byte1, IRExpr *etf3_and_m3_is_1)
+{
+ IRExpr **args, *call;
+ args = mkIRExprVec_2(byte1, etf3_and_m3_is_1);
+ call = mkIRExprCCall(Ity_I64, 0 /*regparm*/, "s390_do_cu12_cu14_helper1",
+ &s390_do_cu12_cu14_helper1, args);
+
+ /* Nothing is excluded from definedness checking. */
+ call->Iex.CCall.cee->mcx_mask = 0;
+
+ return call;
+}
+
+static IRExpr *
+s390_call_cu12_helper2(IRExpr *byte1, IRExpr *byte2, IRExpr *byte3,
+ IRExpr *byte4, IRExpr *stuff)
+{
+ IRExpr **args, *call;
+ args = mkIRExprVec_5(byte1, byte2, byte3, byte4, stuff);
+ call = mkIRExprCCall(Ity_I64, 0 /*regparm*/,
+ "s390_do_cu12_helper2", &s390_do_cu12_helper2, args);
+
+ /* Nothing is excluded from definedness checking. */
+ call->Iex.CCall.cee->mcx_mask = 0;
+
+ return call;
+}
+
+static IRExpr *
+s390_call_cu14_helper2(IRExpr *byte1, IRExpr *byte2, IRExpr *byte3,
+ IRExpr *byte4, IRExpr *stuff)
+{
+ IRExpr **args, *call;
+ args = mkIRExprVec_5(byte1, byte2, byte3, byte4, stuff);
+ call = mkIRExprCCall(Ity_I64, 0 /*regparm*/,
+ "s390_do_cu14_helper2", &s390_do_cu14_helper2, args);
+
+ /* Nothing is excluded from definedness checking. */
+ call->Iex.CCall.cee->mcx_mask = 0;
+
+ return call;
+}
+
+static void
+s390_irgen_cu12_cu14(UChar m3, UChar r1, UChar r2, Bool is_cu12)
+{
+ IRTemp addr1 = newTemp(Ity_I64);
+ IRTemp addr2 = newTemp(Ity_I64);
+ IRTemp len1 = newTemp(Ity_I64);
+ IRTemp len2 = newTemp(Ity_I64);
+
+ assign(addr1, get_gpr_dw0(r1));
+ assign(addr2, get_gpr_dw0(r2));
+ assign(len1, get_gpr_dw0(r1 + 1));
+ assign(len2, get_gpr_dw0(r2 + 1));
+
+ UInt extended_checking = s390_host_has_etf3 && (m3 & 0x1) == 1;
+
+ /* We're processing the 2nd operand 1 byte at a time. Therefore, if
+ there is less than 1 byte left, then the 2nd operand is exhausted
+ and we're done here. cc = 0 */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len2), mkU64(1)));
+
+ /* There is at least one byte there. Read it. */
+ IRTemp byte1 = newTemp(Ity_I64);
+ assign(byte1, unop(Iop_8Uto64, load(Ity_I8, mkexpr(addr2))));
+
+ /* Call the helper to get number of bytes and invalid byte indicator */
+ IRTemp retval1 = newTemp(Ity_I64);
+ assign(retval1, s390_call_cu12_cu14_helper1(mkexpr(byte1),
+ mkU64(extended_checking)));
+
+ /* Check for invalid 1st byte */
+ IRExpr *is_invalid = unop(Iop_64to1, mkexpr(retval1));
+ s390_cc_set(2);
+ next_insn_if(is_invalid);
+
+ /* How many bytes do we have to read? */
+ IRTemp num_src_bytes = newTemp(Ity_I64);
+ assign(num_src_bytes, binop(Iop_Shr64, mkexpr(retval1), mkU8(8)));
+
+ /* Now test whether the 2nd operand is exhausted */
+ s390_cc_set(0);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len2), mkexpr(num_src_bytes)));
+
+ /* Read the remaining bytes */
+ IRExpr *cond, *addr, *byte2, *byte3, *byte4;
+
+ cond = binop(Iop_CmpLE64U, mkU64(2), mkexpr(num_src_bytes));
+ addr = binop(Iop_Add64, mkexpr(addr2), mkU64(1));
+ byte2 = mkite(cond, unop(Iop_8Uto64, load(Ity_I8, addr)), mkU64(0));
+ cond = binop(Iop_CmpLE64U, mkU64(3), mkexpr(num_src_bytes));
+ addr = binop(Iop_Add64, mkexpr(addr2), mkU64(2));
+ byte3 = mkite(cond, unop(Iop_8Uto64, load(Ity_I8, addr)), mkU64(0));
+ cond = binop(Iop_CmpLE64U, mkU64(4), mkexpr(num_src_bytes));
+ addr = binop(Iop_Add64, mkexpr(addr2), mkU64(3));
+ byte4 = mkite(cond, unop(Iop_8Uto64, load(Ity_I8, addr)), mkU64(0));
+
+ /* Call the helper to get the converted value and invalid byte indicator.
+ We can pass at most 5 arguments; therefore some encoding is needed
+ here */
+ IRExpr *stuff = binop(Iop_Or64,
+ binop(Iop_Shl64, mkexpr(num_src_bytes), mkU8(1)),
+ mkU64(extended_checking));
+ IRTemp retval2 = newTemp(Ity_I64);
+
+ if (is_cu12) {
+ assign(retval2, s390_call_cu12_helper2(mkexpr(byte1), byte2, byte3,
+ byte4, stuff));
+ } else {
+ assign(retval2, s390_call_cu14_helper2(mkexpr(byte1), byte2, byte3,
+ byte4, stuff));
+ }
+
+ /* Check for invalid character */
+ s390_cc_set(2);
+ is_invalid = unop(Iop_64to1, mkexpr(retval2));
+ next_insn_if(is_invalid);
+
+ /* Now test whether the 1st operand is exhausted */
+ IRTemp num_bytes = newTemp(Ity_I64);
+ assign(num_bytes, binop(Iop_And64,
+ binop(Iop_Shr64, mkexpr(retval2), mkU8(8)),
+ mkU64(0xff)));
+ s390_cc_set(1);
+ next_insn_if(binop(Iop_CmpLT64U, mkexpr(len1), mkexpr(num_bytes)));
+
+ /* Extract the bytes to be stored at addr1 */
+ IRTemp data = newTemp(Ity_I64);
+ assign(data, binop(Iop_Shr64, mkexpr(retval2), mkU8(16)));
+
+ if (is_cu12) {
+ /* To store the bytes construct 2 dirty helper calls. The helper calls
+ are guarded (num_bytes == 2 and num_bytes == 4, respectively) such
+ that only one of them will be called at runtime. */
+
+ Int i;
+ for (i = 2; i <= 4; ++i) {
+ IRDirty *d;
+
+ if (i == 3) continue; // skip this one
+
+ d = unsafeIRDirty_0_N(0 /* regparms */, "s390x_dirtyhelper_CUxy",
+ &s390x_dirtyhelper_CUxy,
+ mkIRExprVec_3(mkexpr(addr1), mkexpr(data),
+ mkexpr(num_bytes)));
+ d->guard = binop(Iop_CmpEQ64, mkexpr(num_bytes), mkU64(i));
+ d->mFx = Ifx_Write;
+ d->mAddr = mkexpr(addr1);
+ d->mSize = i;
+ stmt(IRStmt_Dirty(d));
+ }
+ } else {
+ // cu14
+ store(mkexpr(addr1), unop(Iop_64to32, mkexpr(data)));
+ }
+
+ /* Update source address and length */
+ put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(addr2), mkexpr(num_src_bytes)));
+ put_gpr_dw0(r2 + 1, binop(Iop_Sub64, mkexpr(len2), mkexpr(num_src_bytes)));
+
+ /* Update destination address and length */
+ put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(addr1), mkexpr(num_bytes)));
+ put_gpr_dw0(r1 + 1, binop(Iop_Sub64, mkexpr(len1), mkexpr(num_bytes)));
+
+ iterate();
+}
+
+static HChar *
+s390_irgen_CU12(UChar m3, UChar r1, UChar r2)
+{
+ s390_irgen_cu12_cu14(m3, r1, r2, /* is_cu12 = */ 1);
+
+ return "cu12";
+}
+
+static HChar *
+s390_irgen_CU14(UChar m3, UChar r1, UChar r2)
+{
+ s390_irgen_cu12_cu14(m3, r1, r2, /* is_cu12 = */ 0);
+
+ return "cu14";
+}
/*------------------------------------------------------------*/
/*--- Build IR for special instructions ---*/
@@ -10858,12 +11760,13 @@
if (0)
vex_printf("%%R3 = client_request ( %%R2 )\n");
- irsb->next = mkU64((ULong)(guest_IA_curr_instr
- + S390_SPECIAL_OP_PREAMBLE_SIZE
- + S390_SPECIAL_OP_SIZE));
- irsb->jumpkind = Ijk_ClientReq;
+ Addr64 next = guest_IA_curr_instr + S390_SPECIAL_OP_PREAMBLE_SIZE
+ + S390_SPECIAL_OP_SIZE;
+ dis_res->jk_StopHere = Ijk_ClientReq;
dis_res->whatNext = Dis_StopHere;
+
+ put_IA(mkaddr_expr(next));
}
static void
@@ -10878,16 +11781,17 @@
static void
s390_irgen_call_noredir(void)
{
+ Addr64 next = guest_IA_curr_instr + S390_SPECIAL_OP_PREAMBLE_SIZE
+ + S390_SPECIAL_OP_SIZE;
+
/* Continue after special op */
- put_gpr_dw0(14, mkU64(guest_IA_curr_instr
- + S390_SPECIAL_OP_PREAMBLE_SIZE
- + S390_SPECIAL_OP_SIZE));
+ put_gpr_dw0(14, mkaddr_expr(next));
/* The address is in REG1, all parameters are in the right (guest) places */
- irsb->next = get_gpr_dw0(1);
- irsb->jumpkind = Ijk_NoRedir;
+ put_IA(get_gpr_dw0(1));
dis_res->whatNext = Dis_StopHere;
+ dis_res->jk_StopHere = Ijk_NoRedir;
}
/* Force proper alignment for the structures below. */
@@ -10922,8 +11826,6 @@
((char *)(&ovl.value))[1] = bytes[1];
switch (ovl.value & 0xffff) {
- case 0x0000: /* invalid opcode */
- s390_format_RR_RR(s390_irgen_00, 0, 0); goto ok;
case 0x0101: /* PR */ goto unimplemented;
case 0x0102: /* UPT */ goto unimplemented;
case 0x0104: /* PTFF */ goto unimplemented;
@@ -11194,11 +12096,11 @@
switch ((ovl.value & 0xffff0000) >> 16) {
case 0x8000: /* SSM */ goto unimplemented;
case 0x8200: /* LPSW */ goto unimplemented;
- case 0x9300: s390_format_S_RD(s390_irgen_TS, ovl.fmt.S.b2, ovl.fmt.S.d2);
- goto ok;
+ case 0x9300: /* TS */ goto unimplemented;
case 0xb202: /* STIDP */ goto unimplemented;
case 0xb204: /* SCK */ goto unimplemented;
- case 0xb205: s390_format_S_RD(s390_irgen_STCK, ovl.fmt.S.b2, ovl.fmt.S.d2);goto ok;
+ case 0xb205: s390_format_S_RD(s390_irgen_STCK, ovl.fmt.S.b2, ovl.fmt.S.d2);
+ goto ok;
case 0xb206: /* SCKC */ goto unimplemented;
case 0xb207: /* STCKC */ goto unimplemented;
case 0xb208: /* SPT */ goto unimplemented;
@@ -11286,9 +12188,13 @@
goto ok;
case 0xb29d: s390_format_S_RD(s390_irgen_LFPC, ovl.fmt.S.b2, ovl.fmt.S.d2);
goto ok;
- case 0xb2a5: /* TRE */ goto unimplemented;
- case 0xb2a6: /* CU21 */ goto unimplemented;
- case 0xb2a7: /* CU12 */ goto unimplemented;
+ case 0xb2a5: s390_format_RRE_FF(s390_irgen_TRE, ovl.fmt.RRE.r1, ovl.fmt.RRE.r2); goto ok;
+ case 0xb2a6: s390_format_RRF_M0RERE(s390_irgen_CU21, ovl.fmt.RRF3.r3,
+ ovl.fmt.RRF3.r1, ovl.fmt.RRF3.r2);
+ goto ok;
+ case 0xb2a7: s390_format_RRF_M0RERE(s390_irgen_CU12, ovl.fmt.RRF3.r3,
+ ovl.fmt.RRF3.r1, ovl.fmt.RRF3.r2);
+ goto ok;
case 0xb2b0: s390_format_S_RD(s390_irgen_STFLE, ovl.fmt.S.b2, ovl.fmt.S.d2);
goto ok;
case 0xb2b1: /* STFL */ goto unimplemented;
@@ -11649,10 +12555,14 @@
case 0xb98a: /* CSPG */ goto unimplemented;
case 0xb98d: /* EPSW */ goto unimplemented;
case 0xb98e: /* IDTE */ goto unimplemented;
- case 0xb990: /* TRTT */ goto unimplemented;
- case 0xb991: /* TRTO */ goto unimplemented;
- case 0xb992: /* TROT */ goto unimplemented;
- case 0xb993: /* TROO */ goto unimplemented;
+ case 0xb990: s390_format_RRF_M0RERE(s390_irgen_TRTT, ovl.fmt.RRF3.r3,
+ ovl.fmt.RRF3.r1, ovl.fmt.RRF3.r2); goto ok;
+ case 0xb991: s390_format_RRF_M0RERE(s390_irgen_TRTO, ovl.fmt.RRF3.r3,
+ ovl.fmt.RRF3.r1, ovl.fmt.RRF3.r2); goto ok;
+ case 0xb992: s390_format_RRF_M0RERE(s390_irgen_TROT, ovl.fmt.RRF3.r3,
+ ovl.fmt.RRF3.r1, ovl.fmt.RRF3.r2); goto ok;
+ case 0xb993: s390_format_RRF_M0RERE(s390_irgen_TROO, ovl.fmt.RRF3.r3,
+ ovl.fmt.RRF3.r1, ovl.fmt.RRF3.r2); goto ok;
case 0xb994: s390_format_RRE_RR(s390_irgen_LLCR, ovl.fmt.RRE.r1,
ovl.fmt.RRE.r2); goto ok;
case 0xb995: s390_format_RRE_RR(s390_irgen_LLHR, ovl.fmt.RRE.r1,
@@ -11674,10 +12584,16 @@
case 0xb9aa: /* LPTEA */ goto unimplemented;
case 0xb9ae: /* RRBM */ goto unimplemented;
case 0xb9af: /* PFMF */ goto unimplemented;
- case 0xb9b0: /* CU14 */ goto unimplemented;
- case 0xb9b1: /* CU24 */ goto unimplemented;
- case 0xb9b2: /* CU41 */ goto unimplemented;
- case 0xb9b3: /* CU42 */ goto unimplemented;
+ case 0xb9b0: s390_format_RRF_M0RERE(s390_irgen_CU14, ovl.fmt.RRF3.r3,
+ ovl.fmt.RRF3.r1, ovl.fmt.RRF3.r2);
+ goto ok;
+ case 0xb9b1: s390_format_RRF_M0RERE(s390_irgen_CU24, ovl.fmt.RRF3.r3,
+ ovl.fmt.RRF3.r1, ovl.fmt.RRF3.r2);
+ goto ok;
+ case 0xb9b2: s390_format_RRE_RR(s390_irgen_CU41, ovl.fmt.RRE.r1,
+ ovl.fmt.RRE.r2); goto ok;
+ case 0xb9b3: s390_format_RRE_RR(s390_irgen_CU42, ovl.fmt.RRE.r1,
+ ovl.fmt.RRE.r2); goto ok;
case 0xb9bd: /* TRTRE */ goto unimplemented;
case 0xb9be: /* SRSTU */ goto unimplemented;
case 0xb9bf: /* TRTE */ goto unimplemented;
@@ -11910,7 +12826,8 @@
case 0xb7: /* LCTL */ goto unimplemented;
case 0xba: s390_format_RS_RRRD(s390_irgen_CS, ovl.fmt.RS.r1, ovl.fmt.RS.r3,
ovl.fmt.RS.b2, ovl.fmt.RS.d2); goto ok;
- case 0xbb: /* CDS */ goto unimplemented;
+ case 0xbb: s390_format_RS_RRRD(s390_irgen_CDS, ovl.fmt.RS.r1, ovl.fmt.RS.r3,
+ ovl.fmt.RS.b2, ovl.fmt.RS.d2); goto ok;
case 0xbd: s390_format_RS_RURD(s390_irgen_CLM, ovl.fmt.RS.r1, ovl.fmt.RS.r3,
ovl.fmt.RS.b2, ovl.fmt.RS.d2); goto ok;
case 0xbe: s390_format_RS_RURD(s390_irgen_STCM, ovl.fmt.RS.r1, ovl.fmt.RS.r3,
@@ -12539,8 +13456,14 @@
ovl.fmt.RSY.r3, ovl.fmt.RSY.b2,
ovl.fmt.RSY.dl2,
ovl.fmt.RSY.dh2); goto ok;
- case 0xeb0000000031ULL: /* CDSY */ goto unimplemented;
- case 0xeb000000003eULL: /* CDSG */ goto unimplemented;
+ case 0xeb0000000031ULL: s390_format_RSY_RRRD(s390_irgen_CDSY, ovl.fmt.RSY.r1,
+ ovl.fmt.RSY.r3, ovl.fmt.RSY.b2,
+ ovl.fmt.RSY.dl2,
+ ovl.fmt.RSY.dh2); goto ok;
+ case 0xeb000000003eULL: s390_format_RSY_RRRD(s390_irgen_CDSG, ovl.fmt.RSY.r1,
+ ovl.fmt.RSY.r3, ovl.fmt.RSY.b2,
+ ovl.fmt.RSY.dl2,
+ ovl.fmt.RSY.dh2); goto ok;
case 0xeb0000000044ULL: s390_format_RSY_RRRD(s390_irgen_BXHG, ovl.fmt.RSY.r1,
ovl.fmt.RSY.r3, ovl.fmt.RSY.b2,
ovl.fmt.RSY.dl2,
@@ -13073,7 +13996,9 @@
case 0xd9ULL: /* MVCK */ goto unimplemented;
case 0xdaULL: /* MVCP */ goto unimplemented;
case 0xdbULL: /* MVCS */ goto unimplemented;
- case 0xdcULL: /* TR */ goto unimplemented;
+ case 0xdcULL: s390_format_SS_L0RDRD(s390_irgen_TR, ovl.fmt.SS.l,
+ ovl.fmt.SS.b1, ovl.fmt.SS.d1,
+ ovl.fmt.SS.b2, ovl.fmt.SS.d2); goto ok;
case 0xddULL: /* TRT */ goto unimplemented;
case 0xdeULL: /* ED */ goto unimplemented;
case 0xdfULL: /* EDMK */ goto unimplemented;
@@ -13209,11 +14134,10 @@
}
}
/* If next instruction is execute, stop here */
- if (irsb->next == NULL && dis_res->whatNext == Dis_Continue
- && bytes[insn_length] == 0x44) {
- irsb->next = IRExpr_Const(IRConst_U64(guest_IA_next_instr));
+ if (dis_res->whatNext == Dis_Continue && bytes[insn_length] == 0x44) {
+ put_IA(mkaddr_expr(guest_IA_next_instr));
dis_res->whatNext = Dis_StopHere;
- dis_res->continueAt = 0;
+ dis_res->jk_StopHere = Ijk_Boring;
}
if (status == S390_DECODE_OK) return insn_length; /* OK */
@@ -13252,14 +14176,6 @@
}
-/* Generate an IRExpr for an address. */
-static __inline__ IRExpr *
-mkaddr_expr(Addr64 addr)
-{
- return IRExpr_Const(IRConst_U64(addr));
-}
-
-
/* Disassemble a single instruction INSN into IR. */
static DisResult
disInstr_S390_WRK(UChar *insn)
@@ -13287,6 +14203,7 @@
dres.whatNext = Dis_Continue;
dres.len = insn_length;
dres.continueAt = 0;
+ dres.jk_StopHere = Ijk_INVALID;
/* fixs390: consider chasing of conditional jumps */
@@ -13296,16 +14213,30 @@
error message.
Tell the dispatcher that this insn cannot be decoded, and so has
not been executed, and (is currently) the next to be executed.
- IA should be up-to-date since it made so at the start of each
- insn, but nevertheless be paranoid and update it again right
- now. */
- addStmtToIRSB(irsb, IRStmt_Put(S390X_GUEST_OFFSET(guest_IA),
- mkaddr_expr(guest_IA_curr_instr)));
+ The insn address in the guest state needs to be set to
+ guest_IA_curr_instr, otherwise the complaint will report an
+ incorrect address. */
+ put_IA(mkaddr_expr(guest_IA_curr_instr));
- irsb->next = mkaddr_expr(guest_IA_next_instr);
- irsb->jumpkind = Ijk_NoDecode;
- dres.whatNext = Dis_StopHere;
- dres.len = 0;
+ dres.whatNext = Dis_StopHere;
+ dres.jk_StopHere = Ijk_NoDecode;
+ dres.continueAt = 0;
+ dres.len = 0;
+ } else {
+ /* Decode success */
+ switch (dres.whatNext) {
+ case Dis_Continue:
+ put_IA(mkaddr_expr(guest_IA_next_instr));
+ break;
+ case Dis_ResteerU:
+ case Dis_ResteerC:
+ put_IA(mkaddr_expr(dres.continueAt));
+ break;
+ case Dis_StopHere:
+ break;
+ default:
+ vassert(0);
+ }
}
return dres;
@@ -13321,7 +14252,6 @@
DisResult
disInstr_S390(IRSB *irsb_IN,
- Bool put_IP,
Bool (*resteerOkFn)(void *, Addr64),
Bool resteerCisOk,
void *callback_opaque,
@@ -13344,11 +14274,6 @@
resteer_fn = resteerOkFn;
resteer_data = callback_opaque;
- /* We may be asked to update the guest IA before going further. */
- if (put_IP)
- addStmtToIRSB(irsb, IRStmt_Put(S390X_GUEST_OFFSET(guest_IA),
- mkaddr_expr(guest_IA_curr_instr)));
-
return disInstr_S390_WRK(guest_code + delta);
}
diff --git a/main/VEX/priv/guest_x86_defs.h b/main/VEX/priv/guest_x86_defs.h
index 130d84d..994bce9 100644
--- a/main/VEX/priv/guest_x86_defs.h
+++ b/main/VEX/priv/guest_x86_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -47,7 +47,6 @@
bb_to_IR.h. */
extern
DisResult disInstr_X86 ( IRSB* irbb,
- Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
diff --git a/main/VEX/priv/guest_x86_helpers.c b/main/VEX/priv/guest_x86_helpers.c
index 2bfe210..62c9dd1 100644
--- a/main/VEX/priv/guest_x86_helpers.c
+++ b/main/VEX/priv/guest_x86_helpers.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -1787,7 +1787,20 @@
/* Copy the x87 registers out of the image, into a temporary
Fpu_State struct. */
- for (i = 0; i < 14; i++) tmp.env[i] = 0;
+
+ /* LLVM on Darwin turns the following loop into a movaps plus a
+ handful of scalar stores. This would work fine except for the
+ fact that VEX doesn't keep the stack correctly (16-) aligned for
+ the call, so it segfaults. Hence, split the loop into two
+ pieces (and pray LLVM doesn't merely glue them back together) so
+ it's composed only of scalar stores and so is alignment
+ insensitive. Of course this is a kludge of the lamest kind --
+ VEX should be fixed properly. */
+ /* Code that seems to trigger the problem:
+ for (i = 0; i < 14; i++) tmp.env[i] = 0; */
+ for (i = 0; i < 7; i++) tmp.env[i+0] = 0;
+ for (i = 0; i < 7; i++) tmp.env[i+7] = 0;
+
for (i = 0; i < 80; i++) tmp.reg[i] = 0;
/* fill in tmp.reg[0..7] */
for (stno = 0; stno < 8; stno++) {
@@ -2657,6 +2670,9 @@
/* VISIBLE TO LIBVEX CLIENT */
void LibVEX_GuestX86_initialise ( /*OUT*/VexGuestX86State* vex_state )
{
+ vex_state->host_EvC_FAILADDR = 0;
+ vex_state->host_EvC_COUNTER = 0;
+
vex_state->guest_EAX = 0;
vex_state->guest_ECX = 0;
vex_state->guest_EDX = 0;
@@ -2713,9 +2729,11 @@
vex_state->guest_SC_CLASS = 0;
vex_state->guest_IP_AT_SYSCALL = 0;
- vex_state->padding1 = 0;
- vex_state->padding2 = 0;
- vex_state->padding3 = 0;
+ Int i;
+ for (i = 0; i < sizeof(vex_state->padding)
+ / sizeof(vex_state->padding[0]); i++) {
+ vex_state->padding[i] = 0;
+ }
}
diff --git a/main/VEX/priv/guest_x86_toIR.c b/main/VEX/priv/guest_x86_toIR.c
index 363d66b..e8780db 100644
--- a/main/VEX/priv/guest_x86_toIR.c
+++ b/main/VEX/priv/guest_x86_toIR.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -768,7 +768,8 @@
binop( mkSizedOp(tyE,Iop_CasCmpNE8),
mkexpr(oldTmp), mkexpr(expTmp) ),
Ijk_Boring, /*Ijk_NoRedir*/
- IRConst_U32( restart_point )
+ IRConst_U32( restart_point ),
+ OFFB_EIP
));
}
@@ -1340,36 +1341,55 @@
/*--- JMP helpers ---*/
/*------------------------------------------------------------*/
-static void jmp_lit( IRJumpKind kind, Addr32 d32 )
+static void jmp_lit( /*MOD*/DisResult* dres,
+ IRJumpKind kind, Addr32 d32 )
{
- irsb->next = mkU32(d32);
- irsb->jumpkind = kind;
+ vassert(dres->whatNext == Dis_Continue);
+ vassert(dres->len == 0);
+ vassert(dres->continueAt == 0);
+ vassert(dres->jk_StopHere == Ijk_INVALID);
+ dres->whatNext = Dis_StopHere;
+ dres->jk_StopHere = kind;
+ stmt( IRStmt_Put( OFFB_EIP, mkU32(d32) ) );
}
-static void jmp_treg( IRJumpKind kind, IRTemp t )
+static void jmp_treg( /*MOD*/DisResult* dres,
+ IRJumpKind kind, IRTemp t )
{
- irsb->next = mkexpr(t);
- irsb->jumpkind = kind;
+ vassert(dres->whatNext == Dis_Continue);
+ vassert(dres->len == 0);
+ vassert(dres->continueAt == 0);
+ vassert(dres->jk_StopHere == Ijk_INVALID);
+ dres->whatNext = Dis_StopHere;
+ dres->jk_StopHere = kind;
+ stmt( IRStmt_Put( OFFB_EIP, mkexpr(t) ) );
}
static
-void jcc_01( X86Condcode cond, Addr32 d32_false, Addr32 d32_true )
+void jcc_01( /*MOD*/DisResult* dres,
+ X86Condcode cond, Addr32 d32_false, Addr32 d32_true )
{
Bool invert;
X86Condcode condPos;
+ vassert(dres->whatNext == Dis_Continue);
+ vassert(dres->len == 0);
+ vassert(dres->continueAt == 0);
+ vassert(dres->jk_StopHere == Ijk_INVALID);
+ dres->whatNext = Dis_StopHere;
+ dres->jk_StopHere = Ijk_Boring;
condPos = positiveIse_X86Condcode ( cond, &invert );
if (invert) {
stmt( IRStmt_Exit( mk_x86g_calculate_condition(condPos),
Ijk_Boring,
- IRConst_U32(d32_false) ) );
- irsb->next = mkU32(d32_true);
- irsb->jumpkind = Ijk_Boring;
+ IRConst_U32(d32_false),
+ OFFB_EIP ) );
+ stmt( IRStmt_Put( OFFB_EIP, mkU32(d32_true) ) );
} else {
stmt( IRStmt_Exit( mk_x86g_calculate_condition(condPos),
Ijk_Boring,
- IRConst_U32(d32_true) ) );
- irsb->next = mkU32(d32_false);
- irsb->jumpkind = Ijk_Boring;
+ IRConst_U32(d32_true),
+ OFFB_EIP ) );
+ stmt( IRStmt_Put( OFFB_EIP, mkU32(d32_false) ) );
}
}
@@ -1450,7 +1470,8 @@
IRStmt_Exit(
binop(Iop_CmpNE32, unop(Iop_64HIto32, mkexpr(r64)), mkU32(0)),
Ijk_MapFail,
- IRConst_U32( guest_EIP_curr_instr )
+ IRConst_U32( guest_EIP_curr_instr ),
+ OFFB_EIP
)
);
@@ -3009,7 +3030,7 @@
/* Group 5 extended opcodes. */
static
UInt dis_Grp5 ( UChar sorb, Bool locked, Int sz, Int delta,
- DisResult* dres, Bool* decode_OK )
+ /*MOD*/DisResult* dres, /*OUT*/Bool* decode_OK )
{
Int len;
UChar modrm;
@@ -3054,13 +3075,13 @@
assign(t2, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4)));
putIReg(4, R_ESP, mkexpr(t2));
storeLE( mkexpr(t2), mkU32(guest_EIP_bbstart+delta+1));
- jmp_treg(Ijk_Call,t1);
- dres->whatNext = Dis_StopHere;
+ jmp_treg(dres, Ijk_Call, t1);
+ vassert(dres->whatNext == Dis_StopHere);
break;
case 4: /* jmp Ev */
vassert(sz == 4);
- jmp_treg(Ijk_Boring,t1);
- dres->whatNext = Dis_StopHere;
+ jmp_treg(dres, Ijk_Boring, t1);
+ vassert(dres->whatNext == Dis_StopHere);
break;
case 6: /* PUSH Ev */
vassert(sz == 4 || sz == 2);
@@ -3110,13 +3131,13 @@
assign(t2, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4)));
putIReg(4, R_ESP, mkexpr(t2));
storeLE( mkexpr(t2), mkU32(guest_EIP_bbstart+delta+len));
- jmp_treg(Ijk_Call,t1);
- dres->whatNext = Dis_StopHere;
+ jmp_treg(dres, Ijk_Call, t1);
+ vassert(dres->whatNext == Dis_StopHere);
break;
case 4: /* JMP Ev */
vassert(sz == 4);
- jmp_treg(Ijk_Boring,t1);
- dres->whatNext = Dis_StopHere;
+ jmp_treg(dres, Ijk_Boring, t1);
+ vassert(dres->whatNext == Dis_StopHere);
break;
case 6: /* PUSH Ev */
vassert(sz == 4 || sz == 2);
@@ -3253,7 +3274,8 @@
We assume the insn is the last one in the basic block, and so emit a jump
to the next insn, rather than just falling through. */
static
-void dis_REP_op ( X86Condcode cond,
+void dis_REP_op ( /*MOD*/DisResult* dres,
+ X86Condcode cond,
void (*dis_OP)(Int, IRTemp),
Int sz, Addr32 eip, Addr32 eip_next, HChar* name )
{
@@ -3264,7 +3286,7 @@
stmt( IRStmt_Exit( binop(Iop_CmpEQ32,mkexpr(tc),mkU32(0)),
Ijk_Boring,
- IRConst_U32(eip_next) ) );
+ IRConst_U32(eip_next), OFFB_EIP ) );
putIReg(4, R_ECX, binop(Iop_Sub32, mkexpr(tc), mkU32(1)) );
@@ -3272,12 +3294,14 @@
dis_OP (sz, t_inc);
if (cond == X86CondAlways) {
- jmp_lit(Ijk_Boring,eip);
+ jmp_lit(dres, Ijk_Boring, eip);
+ vassert(dres->whatNext == Dis_StopHere);
} else {
stmt( IRStmt_Exit( mk_x86g_calculate_condition(cond),
Ijk_Boring,
- IRConst_U32(eip) ) );
- jmp_lit(Ijk_Boring,eip_next);
+ IRConst_U32(eip), OFFB_EIP ) );
+ jmp_lit(dres, Ijk_Boring, eip_next);
+ vassert(dres->whatNext == Dis_StopHere);
}
DIP("%s%c\n", name, nameISize(sz));
}
@@ -3498,7 +3522,7 @@
IRRegArray* descr;
vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_I8);
descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
- stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
+ stmt( IRStmt_PutI( mkIRPutI(descr, get_ftop(), i, value) ) );
}
/* Given i, generate an expression yielding 'ST_TAG(i)'. This will be
@@ -3522,7 +3546,7 @@
IRRegArray* descr;
vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_F64);
descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 );
- stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
+ stmt( IRStmt_PutI( mkIRPutI(descr, get_ftop(), i, value) ) );
/* Mark the register as in-use. */
put_ST_TAG(i, mkU8(1));
}
@@ -3930,6 +3954,7 @@
/* declare we're writing guest state */
d->nFxState = 4;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Write;
d->fxState[0].offset = OFFB_FTOP;
@@ -3958,7 +3983,8 @@
IRStmt_Exit(
binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
Ijk_EmWarn,
- IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta)
+ IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta),
+ OFFB_EIP
)
);
@@ -4000,7 +4026,8 @@
IRStmt_Exit(
binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
Ijk_EmWarn,
- IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta)
+ IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta),
+ OFFB_EIP
)
);
break;
@@ -4023,6 +4050,7 @@
/* declare we're reading guest state */
d->nFxState = 4;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Read;
d->fxState[0].offset = OFFB_FTOP;
@@ -4712,6 +4740,7 @@
/* declare we're writing guest state */
d->nFxState = 5;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Write;
d->fxState[0].offset = OFFB_FTOP;
@@ -4916,6 +4945,7 @@
/* declare we're writing guest state */
d->nFxState = 5;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Write;
d->fxState[0].offset = OFFB_FTOP;
@@ -4948,7 +4978,8 @@
IRStmt_Exit(
binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
Ijk_EmWarn,
- IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta)
+ IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta),
+ OFFB_EIP
)
);
@@ -4973,6 +5004,7 @@
/* declare we're reading guest state */
d->nFxState = 5;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Read;
d->fxState[0].offset = OFFB_FTOP;
@@ -5379,7 +5411,7 @@
IRExpr* tag1 = mkU8(1);
put_ftop(zero);
for (i = 0; i < 8; i++)
- stmt( IRStmt_PutI( descr, zero, i, tag1 ) );
+ stmt( IRStmt_PutI( mkIRPutI(descr, zero, i, tag1) ) );
}
static void do_EMMS_preamble ( void )
@@ -5390,7 +5422,7 @@
IRExpr* tag0 = mkU8(0);
put_ftop(zero);
for (i = 0; i < 8; i++)
- stmt( IRStmt_PutI( descr, zero, i, tag0 ) );
+ stmt( IRStmt_PutI( mkIRPutI(descr, zero, i, tag0) ) );
}
@@ -6811,13 +6843,15 @@
}
static
-void dis_ret ( UInt d32 )
+void dis_ret ( /*MOD*/DisResult* dres, UInt d32 )
{
- IRTemp t1 = newTemp(Ity_I32), t2 = newTemp(Ity_I32);
+ IRTemp t1 = newTemp(Ity_I32);
+ IRTemp t2 = newTemp(Ity_I32);
assign(t1, getIReg(4,R_ESP));
assign(t2, loadLE(Ity_I32,mkexpr(t1)));
putIReg(4, R_ESP,binop(Iop_Add32, mkexpr(t1), mkU32(4+d32)));
- jmp_treg(Ijk_Ret,t2);
+ jmp_treg(dres, Ijk_Ret, t2);
+ vassert(dres->whatNext == Dis_StopHere);
}
/*------------------------------------------------------------*/
@@ -7523,7 +7557,8 @@
binop(Iop_And32, mkexpr(t1), mkU32(1<<18)),
mkU32(0) ),
Ijk_EmWarn,
- IRConst_U32( next_insn_EIP )
+ IRConst_U32( next_insn_EIP ),
+ OFFB_EIP
)
);
}
@@ -7692,19 +7727,16 @@
if effective_addr is not 16-aligned. This is required behaviour
for some SSE3 instructions and all 128-bit SSSE3 instructions.
This assumes that guest_RIP_curr_instr is set correctly! */
-/* TODO(glider): we've replaced the 0xF mask with 0x0, effectively disabling
- * the check. Need to enable it once TSan stops generating unaligned
- * accesses in the wrappers.
- * See http://code.google.com/p/data-race-test/issues/detail?id=49 */
static void gen_SEGV_if_not_16_aligned ( IRTemp effective_addr )
{
stmt(
IRStmt_Exit(
binop(Iop_CmpNE32,
- binop(Iop_And32,mkexpr(effective_addr),mkU32(0x0)),
+ binop(Iop_And32,mkexpr(effective_addr),mkU32(0xF)),
mkU32(0)),
Ijk_SigSEGV,
- IRConst_U32(guest_EIP_curr_instr)
+ IRConst_U32(guest_EIP_curr_instr),
+ OFFB_EIP
)
);
}
@@ -7839,6 +7871,38 @@
return False;
}
+static IRTemp math_BSWAP ( IRTemp t1, IRType ty )
+{
+ IRTemp t2 = newTemp(ty);
+ if (ty == Ity_I32) {
+ assign( t2,
+ binop(
+ Iop_Or32,
+ binop(Iop_Shl32, mkexpr(t1), mkU8(24)),
+ binop(
+ Iop_Or32,
+ binop(Iop_And32, binop(Iop_Shl32, mkexpr(t1), mkU8(8)),
+ mkU32(0x00FF0000)),
+ binop(Iop_Or32,
+ binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(8)),
+ mkU32(0x0000FF00)),
+ binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(24)),
+ mkU32(0x000000FF) )
+ )))
+ );
+ return t2;
+ }
+ if (ty == Ity_I16) {
+ assign(t2,
+ binop(Iop_Or16,
+ binop(Iop_Shl16, mkexpr(t1), mkU8(8)),
+ binop(Iop_Shr16, mkexpr(t1), mkU8(8)) ));
+ return t2;
+ }
+ vassert(0);
+ /*NOTREACHED*/
+ return IRTemp_INVALID;
+}
/*------------------------------------------------------------*/
/*--- Disassemble a single instruction ---*/
@@ -7858,7 +7922,6 @@
static
DisResult disInstr_X86_WRK (
/*OUT*/Bool* expect_CAS,
- Bool put_IP,
Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -7897,9 +7960,10 @@
Bool pfx_lock = False;
/* Set result defaults. */
- dres.whatNext = Dis_Continue;
- dres.len = 0;
- dres.continueAt = 0;
+ dres.whatNext = Dis_Continue;
+ dres.len = 0;
+ dres.continueAt = 0;
+ dres.jk_StopHere = Ijk_INVALID;
*expect_CAS = False;
@@ -7908,10 +7972,6 @@
vassert(guest_EIP_bbstart + delta == guest_EIP_curr_instr);
DIP("\t0x%x: ", guest_EIP_bbstart+delta);
- /* We may be asked to update the guest EIP before going further. */
- if (put_IP)
- stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_curr_instr)) );
-
/* Spot "Special" instructions (see comment at top of file). */
{
UChar* code = (UChar*)(guest_code + delta);
@@ -7930,8 +7990,8 @@
/* %EDX = client_request ( %EAX ) */
DIP("%%edx = client_request ( %%eax )\n");
delta += 14;
- jmp_lit(Ijk_ClientReq, guest_EIP_bbstart+delta);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_ClientReq, guest_EIP_bbstart+delta);
+ vassert(dres.whatNext == Dis_StopHere);
goto decode_success;
}
else
@@ -7953,8 +8013,8 @@
assign(t2, binop(Iop_Sub32, getIReg(4,R_ESP), mkU32(4)));
putIReg(4, R_ESP, mkexpr(t2));
storeLE( mkexpr(t2), mkU32(guest_EIP_bbstart+delta));
- jmp_treg(Ijk_NoRedir,t1);
- dres.whatNext = Dis_StopHere;
+ jmp_treg(&dres, Ijk_NoRedir, t1);
+ vassert(dres.whatNext == Dis_StopHere);
goto decode_success;
}
/* We don't know what it is. */
@@ -8115,10 +8175,11 @@
/* declare we're writing memory */
d->mFx = Ifx_Write;
d->mAddr = mkexpr(addr);
- d->mSize = 512;
+ d->mSize = 464; /* according to recent Intel docs */
/* declare we're reading guest state */
d->nFxState = 7;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Read;
d->fxState[0].offset = OFFB_FTOP;
@@ -8189,10 +8250,11 @@
/* declare we're reading memory */
d->mFx = Ifx_Read;
d->mAddr = mkexpr(addr);
- d->mSize = 512;
+ d->mSize = 464; /* according to recent Intel docs */
/* declare we're writing guest state */
d->nFxState = 7;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Write;
d->fxState[0].offset = OFFB_FTOP;
@@ -8541,7 +8603,8 @@
IRStmt_Exit(
binop(Iop_CmpNE32, mkexpr(ew), mkU32(0)),
Ijk_EmWarn,
- IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta)
+ IRConst_U32( ((Addr32)guest_EIP_bbstart)+delta),
+ OFFB_EIP
)
);
goto decode_success;
@@ -11525,9 +11588,7 @@
stmt( IRStmt_Put(OFFB_TILEN, mkU32(lineszB) ) );
- irsb->jumpkind = Ijk_TInval;
- irsb->next = mkU32(guest_EIP_bbstart+delta);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_TInval, (Addr32)(guest_EIP_bbstart+delta));
DIP("clflush %s\n", dis_buf);
goto decode_success;
@@ -12594,6 +12655,33 @@
);
goto decode_success;
}
+
+ /* 0F 38 F0 = MOVBE m16/32(E), r16/32(G) */
+ /* 0F 38 F1 = MOVBE r16/32(G), m16/32(E) */
+ if ((sz == 2 || sz == 4)
+ && insn[0] == 0x0F && insn[1] == 0x38
+ && (insn[2] == 0xF0 || insn[2] == 0xF1)
+ && !epartIsReg(insn[3])) {
+
+ modrm = insn[3];
+ addr = disAMode(&alen, sorb, delta + 3, dis_buf);
+ delta += 3 + alen;
+ ty = szToITy(sz);
+ IRTemp src = newTemp(ty);
+
+ if (insn[2] == 0xF0) { /* LOAD */
+ assign(src, loadLE(ty, mkexpr(addr)));
+ IRTemp dst = math_BSWAP(src, ty);
+ putIReg(sz, gregOfRM(modrm), mkexpr(dst));
+ DIP("movbe %s,%s\n", dis_buf, nameIReg(sz, gregOfRM(modrm)));
+ } else { /* STORE */
+ assign(src, getIReg(sz, gregOfRM(modrm)));
+ IRTemp dst = math_BSWAP(src, ty);
+ storeLE(mkexpr(addr), mkexpr(dst));
+ DIP("movbe %s,%s\n", nameIReg(sz, gregOfRM(modrm)), dis_buf);
+ }
+ goto decode_success;
+ }
/* ---------------------------------------------------- */
/* --- end of the SSSE3 decoder. --- */
@@ -12733,7 +12821,8 @@
stmt( IRStmt_Exit(
binop(Iop_CmpEQ16, getIReg(2,R_ECX), mkU16(0)),
Ijk_Boring,
- IRConst_U32(d32)
+ IRConst_U32(d32),
+ OFFB_EIP
));
DIP("jcxz 0x%x\n", d32);
goto decode_success;
@@ -12756,13 +12845,11 @@
case 0xC2: /* RET imm16 */
d32 = getUDisp16(delta);
delta += 2;
- dis_ret(d32);
- dres.whatNext = Dis_StopHere;
+ dis_ret(&dres, d32);
DIP("ret %d\n", (Int)d32);
break;
case 0xC3: /* RET */
- dis_ret(0);
- dres.whatNext = Dis_StopHere;
+ dis_ret(&dres, 0);
DIP("ret\n");
break;
@@ -12786,8 +12873,8 @@
/* set %EFLAGS */
set_EFLAGS_from_value( t4, False/*!emit_AC_emwarn*/, 0/*unused*/ );
/* goto new EIP value */
- jmp_treg(Ijk_Ret,t2);
- dres.whatNext = Dis_StopHere;
+ jmp_treg(&dres, Ijk_Ret, t2);
+ vassert(dres.whatNext == Dis_StopHere);
DIP("iret (very kludgey)\n");
break;
@@ -12819,8 +12906,8 @@
dres.whatNext = Dis_ResteerU;
dres.continueAt = (Addr64)(Addr32)d32;
} else {
- jmp_lit(Ijk_Call,d32);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_Call, d32);
+ vassert(dres.whatNext == Dis_StopHere);
}
DIP("call 0x%x\n",d32);
}
@@ -13064,8 +13151,8 @@
/* ------------------------ INT ------------------------ */
case 0xCC: /* INT 3 */
- jmp_lit(Ijk_SigTRAP,((Addr32)guest_EIP_bbstart)+delta);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_SigTRAP, ((Addr32)guest_EIP_bbstart)+delta);
+ vassert(dres.whatNext == Dis_StopHere);
DIP("int $0x3\n");
break;
@@ -13078,14 +13165,16 @@
end-of-block here, which forces any TempRegs caching ArchRegs
to be flushed. */
- /* Handle int $0x40 .. $0x43 by synthesising a segfault and a
+ /* Handle int $0x3F .. $0x4F by synthesising a segfault and a
restart of this instruction (hence the "-2" two lines below,
to get the restart EIP to be this instruction. This is
probably Linux-specific and it would be more correct to only
- do this if the VexAbiInfo says that is what we should do. */
- if (d32 >= 0x40 && d32 <= 0x43) {
- jmp_lit(Ijk_SigSEGV,((Addr32)guest_EIP_bbstart)+delta-2);
- dres.whatNext = Dis_StopHere;
+ do this if the VexAbiInfo says that is what we should do.
+ This used to handle just 0x40-0x43; Jikes RVM uses a larger
+ range (0x3F-0x49), and this allows some slack as well. */
+ if (d32 >= 0x3F && d32 <= 0x4F) {
+ jmp_lit(&dres, Ijk_SigSEGV, ((Addr32)guest_EIP_bbstart)+delta-2);
+ vassert(dres.whatNext == Dis_StopHere);
DIP("int $0x%x\n", (Int)d32);
break;
}
@@ -13097,24 +13186,24 @@
if (d32 == 0x80) {
stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL,
mkU32(guest_EIP_curr_instr) ) );
- jmp_lit(Ijk_Sys_int128,((Addr32)guest_EIP_bbstart)+delta);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_Sys_int128, ((Addr32)guest_EIP_bbstart)+delta);
+ vassert(dres.whatNext == Dis_StopHere);
DIP("int $0x80\n");
break;
}
if (d32 == 0x81) {
stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL,
mkU32(guest_EIP_curr_instr) ) );
- jmp_lit(Ijk_Sys_int129,((Addr32)guest_EIP_bbstart)+delta);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_Sys_int129, ((Addr32)guest_EIP_bbstart)+delta);
+ vassert(dres.whatNext == Dis_StopHere);
DIP("int $0x81\n");
break;
}
if (d32 == 0x82) {
stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL,
mkU32(guest_EIP_curr_instr) ) );
- jmp_lit(Ijk_Sys_int130,((Addr32)guest_EIP_bbstart)+delta);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_Sys_int130, ((Addr32)guest_EIP_bbstart)+delta);
+ vassert(dres.whatNext == Dis_StopHere);
DIP("int $0x82\n");
break;
}
@@ -13131,8 +13220,8 @@
dres.whatNext = Dis_ResteerU;
dres.continueAt = (Addr64)(Addr32)d32;
} else {
- jmp_lit(Ijk_Boring,d32);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_Boring, d32);
+ vassert(dres.whatNext == Dis_StopHere);
}
DIP("jmp-8 0x%x\n", d32);
break;
@@ -13145,8 +13234,8 @@
dres.whatNext = Dis_ResteerU;
dres.continueAt = (Addr64)(Addr32)d32;
} else {
- jmp_lit(Ijk_Boring,d32);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_Boring, d32);
+ vassert(dres.whatNext == Dis_StopHere);
}
DIP("jmp 0x%x\n", d32);
break;
@@ -13187,7 +13276,8 @@
stmt( IRStmt_Exit(
mk_x86g_calculate_condition((X86Condcode)(1 ^ (opc - 0x70))),
Ijk_Boring,
- IRConst_U32(guest_EIP_bbstart+delta) ) );
+ IRConst_U32(guest_EIP_bbstart+delta),
+ OFFB_EIP ) );
dres.whatNext = Dis_ResteerC;
dres.continueAt = (Addr64)(Addr32)d32;
comment = "(assumed taken)";
@@ -13206,7 +13296,8 @@
stmt( IRStmt_Exit(
mk_x86g_calculate_condition((X86Condcode)(opc - 0x70)),
Ijk_Boring,
- IRConst_U32(d32) ) );
+ IRConst_U32(d32),
+ OFFB_EIP ) );
dres.whatNext = Dis_ResteerC;
dres.continueAt = (Addr64)(Addr32)(guest_EIP_bbstart+delta);
comment = "(assumed not taken)";
@@ -13214,9 +13305,9 @@
else {
/* Conservative default translation - end the block at this
point. */
- jcc_01( (X86Condcode)(opc - 0x70),
+ jcc_01( &dres, (X86Condcode)(opc - 0x70),
(Addr32)(guest_EIP_bbstart+delta), d32);
- dres.whatNext = Dis_StopHere;
+ vassert(dres.whatNext == Dis_StopHere);
}
DIP("j%s-8 0x%x %s\n", name_X86Condcode(opc - 0x70), d32, comment);
break;
@@ -13229,7 +13320,8 @@
stmt( IRStmt_Exit(
binop(Iop_CmpEQ32, getIReg(4,R_ECX), mkU32(0)),
Ijk_Boring,
- IRConst_U32(d32)
+ IRConst_U32(d32),
+ OFFB_EIP
));
DIP("jecxz 0x%x\n", d32);
break;
@@ -13270,7 +13362,7 @@
default:
vassert(0);
}
- stmt( IRStmt_Exit(cond, Ijk_Boring, IRConst_U32(d32)) );
+ stmt( IRStmt_Exit(cond, Ijk_Boring, IRConst_U32(d32), OFFB_EIP) );
DIP("loop%s 0x%x\n", xtra, d32);
break;
@@ -13950,33 +14042,32 @@
abyte = getIByte(delta); delta++;
if (abyte == 0x66) { sz = 2; abyte = getIByte(delta); delta++; }
- dres.whatNext = Dis_StopHere;
switch (abyte) {
/* According to the Intel manual, "repne movs" should never occur, but
* in practice it has happened, so allow for it here... */
case 0xA4: sz = 1; /* REPNE MOVS<sz> */
case 0xA5:
- dis_REP_op ( X86CondNZ, dis_MOVS, sz, eip_orig,
- guest_EIP_bbstart+delta, "repne movs" );
+ dis_REP_op ( &dres, X86CondNZ, dis_MOVS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "repne movs" );
break;
case 0xA6: sz = 1; /* REPNE CMP<sz> */
case 0xA7:
- dis_REP_op ( X86CondNZ, dis_CMPS, sz, eip_orig,
- guest_EIP_bbstart+delta, "repne cmps" );
+ dis_REP_op ( &dres, X86CondNZ, dis_CMPS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "repne cmps" );
break;
case 0xAA: sz = 1; /* REPNE STOS<sz> */
case 0xAB:
- dis_REP_op ( X86CondNZ, dis_STOS, sz, eip_orig,
- guest_EIP_bbstart+delta, "repne stos" );
+ dis_REP_op ( &dres, X86CondNZ, dis_STOS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "repne stos" );
break;
case 0xAE: sz = 1; /* REPNE SCAS<sz> */
case 0xAF:
- dis_REP_op ( X86CondNZ, dis_SCAS, sz, eip_orig,
- guest_EIP_bbstart+delta, "repne scas" );
+ dis_REP_op ( &dres, X86CondNZ, dis_SCAS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "repne scas" );
break;
default:
@@ -13989,41 +14080,56 @@
for the rest, it means REP) */
case 0xF3: {
Addr32 eip_orig = guest_EIP_bbstart + delta_start;
- if (sorb != 0) goto decode_failure;
abyte = getIByte(delta); delta++;
if (abyte == 0x66) { sz = 2; abyte = getIByte(delta); delta++; }
- dres.whatNext = Dis_StopHere;
+
+ if (sorb != 0 && abyte != 0x0F) goto decode_failure;
switch (abyte) {
+ case 0x0F:
+ switch (getIByte(delta)) {
+ /* On older CPUs, TZCNT behaves the same as BSF. */
+ case 0xBC: /* REP BSF Gv,Ev */
+ delta = dis_bs_E_G ( sorb, sz, delta + 1, True );
+ break;
+ /* On older CPUs, LZCNT behaves the same as BSR. */
+ case 0xBD: /* REP BSR Gv,Ev */
+ delta = dis_bs_E_G ( sorb, sz, delta + 1, False );
+ break;
+ default:
+ goto decode_failure;
+ }
+ break;
+
case 0xA4: sz = 1; /* REP MOVS<sz> */
case 0xA5:
- dis_REP_op ( X86CondAlways, dis_MOVS, sz, eip_orig,
- guest_EIP_bbstart+delta, "rep movs" );
+ dis_REP_op ( &dres, X86CondAlways, dis_MOVS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "rep movs" );
break;
case 0xA6: sz = 1; /* REPE CMP<sz> */
case 0xA7:
- dis_REP_op ( X86CondZ, dis_CMPS, sz, eip_orig,
- guest_EIP_bbstart+delta, "repe cmps" );
+ dis_REP_op ( &dres, X86CondZ, dis_CMPS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "repe cmps" );
break;
case 0xAA: sz = 1; /* REP STOS<sz> */
case 0xAB:
- dis_REP_op ( X86CondAlways, dis_STOS, sz, eip_orig,
- guest_EIP_bbstart+delta, "rep stos" );
+ dis_REP_op ( &dres, X86CondAlways, dis_STOS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "rep stos" );
break;
case 0xAC: sz = 1; /* REP LODS<sz> */
case 0xAD:
- dis_REP_op ( X86CondAlways, dis_LODS, sz, eip_orig,
- guest_EIP_bbstart+delta, "rep lods" );
+ dis_REP_op ( &dres, X86CondAlways, dis_LODS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "rep lods" );
break;
case 0xAE: sz = 1; /* REPE SCAS<sz> */
case 0xAF:
- dis_REP_op ( X86CondZ, dis_SCAS, sz, eip_orig,
- guest_EIP_bbstart+delta, "repe scas" );
+ dis_REP_op ( &dres, X86CondZ, dis_SCAS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "repe scas" );
break;
case 0x90: /* REP NOP (PAUSE) */
@@ -14031,13 +14137,12 @@
DIP("rep nop (P4 pause)\n");
/* "observe" the hint. The Vex client needs to be careful not
to cause very long delays as a result, though. */
- jmp_lit(Ijk_Yield, ((Addr32)guest_EIP_bbstart)+delta);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_Yield, ((Addr32)guest_EIP_bbstart)+delta);
+ vassert(dres.whatNext == Dis_StopHere);
break;
case 0xC3: /* REP RET -- same as normal ret? */
- dis_ret(0);
- dres.whatNext = Dis_StopHere;
+ dis_ret(&dres, 0);
DIP("rep ret\n");
break;
@@ -14391,24 +14496,11 @@
case 0xCE:
case 0xCF: /* BSWAP %edi */
/* AFAICS from the Intel docs, this only exists at size 4. */
- vassert(sz == 4);
+ if (sz != 4) goto decode_failure;
+
t1 = newTemp(Ity_I32);
- t2 = newTemp(Ity_I32);
assign( t1, getIReg(4, opc-0xC8) );
-
- assign( t2,
- binop(Iop_Or32,
- binop(Iop_Shl32, mkexpr(t1), mkU8(24)),
- binop(Iop_Or32,
- binop(Iop_And32, binop(Iop_Shl32, mkexpr(t1), mkU8(8)),
- mkU32(0x00FF0000)),
- binop(Iop_Or32,
- binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(8)),
- mkU32(0x0000FF00)),
- binop(Iop_And32, binop(Iop_Shr32, mkexpr(t1), mkU8(24)),
- mkU32(0x000000FF) )
- )))
- );
+ t2 = math_BSWAP(t1, Ity_I32);
putIReg(4, opc-0xC8, mkexpr(t2));
DIP("bswapl %s\n", nameIReg(4, opc-0xC8));
@@ -14585,6 +14677,7 @@
/* declare guest state effects */
d->needsBBP = True;
d->nFxState = 4;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
d->fxState[0].fx = Ifx_Modify;
d->fxState[0].offset = OFFB_EAX;
d->fxState[0].size = 4;
@@ -14743,7 +14836,8 @@
mk_x86g_calculate_condition((X86Condcode)
(1 ^ (opc - 0x80))),
Ijk_Boring,
- IRConst_U32(guest_EIP_bbstart+delta) ) );
+ IRConst_U32(guest_EIP_bbstart+delta),
+ OFFB_EIP ) );
dres.whatNext = Dis_ResteerC;
dres.continueAt = (Addr64)(Addr32)d32;
comment = "(assumed taken)";
@@ -14762,7 +14856,8 @@
stmt( IRStmt_Exit(
mk_x86g_calculate_condition((X86Condcode)(opc - 0x80)),
Ijk_Boring,
- IRConst_U32(d32) ) );
+ IRConst_U32(d32),
+ OFFB_EIP ) );
dres.whatNext = Dis_ResteerC;
dres.continueAt = (Addr64)(Addr32)(guest_EIP_bbstart+delta);
comment = "(assumed not taken)";
@@ -14770,9 +14865,9 @@
else {
/* Conservative default translation - end the block at
this point. */
- jcc_01( (X86Condcode)(opc - 0x80),
+ jcc_01( &dres, (X86Condcode)(opc - 0x80),
(Addr32)(guest_EIP_bbstart+delta), d32);
- dres.whatNext = Dis_StopHere;
+ vassert(dres.whatNext == Dis_StopHere);
}
DIP("j%s-32 0x%x %s\n", name_X86Condcode(opc - 0x80), d32, comment);
break;
@@ -14898,8 +14993,8 @@
point if the syscall needs to be restarted. */
stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL,
mkU32(guest_EIP_curr_instr) ) );
- jmp_lit(Ijk_Sys_sysenter, 0/*bogus next EIP value*/);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_Sys_sysenter, 0/*bogus next EIP value*/);
+ vassert(dres.whatNext == Dis_StopHere);
DIP("sysenter");
break;
@@ -15075,8 +15170,8 @@
insn, but nevertheless be paranoid and update it again right
now. */
stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_curr_instr) ) );
- jmp_lit(Ijk_NoDecode, guest_EIP_curr_instr);
- dres.whatNext = Dis_StopHere;
+ jmp_lit(&dres, Ijk_NoDecode, guest_EIP_curr_instr);
+ vassert(dres.whatNext == Dis_StopHere);
dres.len = 0;
/* We also need to say that a CAS is not expected now, regardless
of what it might have been set to at the start of the function,
@@ -15090,6 +15185,20 @@
decode_success:
/* All decode successes end up here. */
+ switch (dres.whatNext) {
+ case Dis_Continue:
+ stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_bbstart + delta) ) );
+ break;
+ case Dis_ResteerU:
+ case Dis_ResteerC:
+ stmt( IRStmt_Put( OFFB_EIP, mkU32(dres.continueAt) ) );
+ break;
+ case Dis_StopHere:
+ break;
+ default:
+ vassert(0);
+ }
+
DIP("\n");
dres.len = delta - delta_start;
return dres;
@@ -15107,7 +15216,6 @@
is located in host memory at &guest_code[delta]. */
DisResult disInstr_X86 ( IRSB* irsb_IN,
- Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
Bool resteerCisOk,
void* callback_opaque,
@@ -15133,7 +15241,7 @@
x1 = irsb_IN->stmts_used;
expect_CAS = False;
- dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn,
+ dres = disInstr_X86_WRK ( &expect_CAS, resteerOkFn,
resteerCisOk,
callback_opaque,
delta, archinfo, abiinfo );
@@ -15153,7 +15261,7 @@
/* inconsistency detected. re-disassemble the instruction so as
to generate a useful error message; then assert. */
vex_traceflags |= VEX_TRACE_FE;
- dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn,
+ dres = disInstr_X86_WRK ( &expect_CAS, resteerOkFn,
resteerCisOk,
callback_opaque,
delta, archinfo, abiinfo );
diff --git a/main/VEX/priv/host_amd64_defs.c b/main/VEX/priv/host_amd64_defs.c
index 807ab4b..cdb8ab6 100644
--- a/main/VEX/priv/host_amd64_defs.c
+++ b/main/VEX/priv/host_amd64_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -118,16 +118,8 @@
HReg hregAMD64_R14 ( void ) { return mkHReg(14, HRcInt64, False); }
HReg hregAMD64_R15 ( void ) { return mkHReg(15, HRcInt64, False); }
-//.. HReg hregAMD64_FAKE0 ( void ) { return mkHReg(0, HRcFlt64, False); }
-//.. HReg hregAMD64_FAKE1 ( void ) { return mkHReg(1, HRcFlt64, False); }
-//.. HReg hregAMD64_FAKE2 ( void ) { return mkHReg(2, HRcFlt64, False); }
-//.. HReg hregAMD64_FAKE3 ( void ) { return mkHReg(3, HRcFlt64, False); }
-//.. HReg hregAMD64_FAKE4 ( void ) { return mkHReg(4, HRcFlt64, False); }
-//.. HReg hregAMD64_FAKE5 ( void ) { return mkHReg(5, HRcFlt64, False); }
-//..
HReg hregAMD64_XMM0 ( void ) { return mkHReg( 0, HRcVec128, False); }
HReg hregAMD64_XMM1 ( void ) { return mkHReg( 1, HRcVec128, False); }
-HReg hregAMD64_XMM2 ( void ) { return mkHReg( 2, HRcVec128, False); }
HReg hregAMD64_XMM3 ( void ) { return mkHReg( 3, HRcVec128, False); }
HReg hregAMD64_XMM4 ( void ) { return mkHReg( 4, HRcVec128, False); }
HReg hregAMD64_XMM5 ( void ) { return mkHReg( 5, HRcVec128, False); }
@@ -138,9 +130,6 @@
HReg hregAMD64_XMM10 ( void ) { return mkHReg(10, HRcVec128, False); }
HReg hregAMD64_XMM11 ( void ) { return mkHReg(11, HRcVec128, False); }
HReg hregAMD64_XMM12 ( void ) { return mkHReg(12, HRcVec128, False); }
-HReg hregAMD64_XMM13 ( void ) { return mkHReg(13, HRcVec128, False); }
-HReg hregAMD64_XMM14 ( void ) { return mkHReg(14, HRcVec128, False); }
-HReg hregAMD64_XMM15 ( void ) { return mkHReg(15, HRcVec128, False); }
void getAllocableRegs_AMD64 ( Int* nregs, HReg** arr )
@@ -231,18 +220,6 @@
return am;
}
-//.. AMD64AMode* dopyAMD64AMode ( AMD64AMode* am ) {
-//.. switch (am->tag) {
-//.. case Xam_IR:
-//.. return AMD64AMode_IR( am->Xam.IR.imm, am->Xam.IR.reg );
-//.. case Xam_IRRS:
-//.. return AMD64AMode_IRRS( am->Xam.IRRS.imm, am->Xam.IRRS.base,
-//.. am->Xam.IRRS.index, am->Xam.IRRS.shift );
-//.. default:
-//.. vpanic("dopyAMD64AMode");
-//.. }
-//.. }
-
void ppAMD64AMode ( AMD64AMode* am ) {
switch (am->tag) {
case Aam_IR:
@@ -538,10 +515,6 @@
HChar* showA87FpOp ( A87FpOp op ) {
switch (op) {
-//.. case Xfp_ADD: return "add";
-//.. case Xfp_SUB: return "sub";
-//.. case Xfp_MUL: return "mul";
-//.. case Xfp_DIV: return "div";
case Afp_SCALE: return "scale";
case Afp_ATAN: return "atan";
case Afp_YL2X: return "yl2x";
@@ -549,9 +522,6 @@
case Afp_PREM: return "prem";
case Afp_PREM1: return "prem1";
case Afp_SQRT: return "sqrt";
-//.. case Xfp_ABS: return "abs";
-//.. case Xfp_NEG: return "chs";
-//.. case Xfp_MOV: return "mov";
case Afp_SIN: return "sin";
case Afp_COS: return "cos";
case Afp_TAN: return "tan";
@@ -717,16 +687,6 @@
vassert(sz == 4 || sz == 8);
return i;
}
-//.. AMD64Instr* AMD64Instr_Sh3232 ( AMD64ShiftOp op, UInt amt, HReg src, HReg dst ) {
-//.. AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag = Xin_Sh3232;
-//.. i->Xin.Sh3232.op = op;
-//.. i->Xin.Sh3232.amt = amt;
-//.. i->Xin.Sh3232.src = src;
-//.. i->Xin.Sh3232.dst = dst;
-//.. vassert(op == Xsh_SHL || op == Xsh_SHR);
-//.. return i;
-//.. }
AMD64Instr* AMD64Instr_Push( AMD64RMI* src ) {
AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
i->tag = Ain_Push;
@@ -742,14 +702,37 @@
vassert(regparms >= 0 && regparms <= 6);
return i;
}
-AMD64Instr* AMD64Instr_Goto ( IRJumpKind jk, AMD64CondCode cond, AMD64RI* dst ) {
- AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
- i->tag = Ain_Goto;
- i->Ain.Goto.cond = cond;
- i->Ain.Goto.dst = dst;
- i->Ain.Goto.jk = jk;
+
+AMD64Instr* AMD64Instr_XDirect ( Addr64 dstGA, AMD64AMode* amRIP,
+ AMD64CondCode cond, Bool toFastEP ) {
+ AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
+ i->tag = Ain_XDirect;
+ i->Ain.XDirect.dstGA = dstGA;
+ i->Ain.XDirect.amRIP = amRIP;
+ i->Ain.XDirect.cond = cond;
+ i->Ain.XDirect.toFastEP = toFastEP;
return i;
}
+AMD64Instr* AMD64Instr_XIndir ( HReg dstGA, AMD64AMode* amRIP,
+ AMD64CondCode cond ) {
+ AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
+ i->tag = Ain_XIndir;
+ i->Ain.XIndir.dstGA = dstGA;
+ i->Ain.XIndir.amRIP = amRIP;
+ i->Ain.XIndir.cond = cond;
+ return i;
+}
+AMD64Instr* AMD64Instr_XAssisted ( HReg dstGA, AMD64AMode* amRIP,
+ AMD64CondCode cond, IRJumpKind jk ) {
+ AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
+ i->tag = Ain_XAssisted;
+ i->Ain.XAssisted.dstGA = dstGA;
+ i->Ain.XAssisted.amRIP = amRIP;
+ i->Ain.XAssisted.cond = cond;
+ i->Ain.XAssisted.jk = jk;
+ return i;
+}
+
AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode cond, AMD64RM* src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
i->tag = Ain_CMov64;
@@ -863,72 +846,12 @@
i->Ain.A87StSW.addr = addr;
return i;
}
-
-//.. AMD64Instr* AMD64Instr_FpUnary ( AMD64FpOp op, HReg src, HReg dst ) {
-//.. AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag = Xin_FpUnary;
-//.. i->Xin.FpUnary.op = op;
-//.. i->Xin.FpUnary.src = src;
-//.. i->Xin.FpUnary.dst = dst;
-//.. return i;
-//.. }
-//.. AMD64Instr* AMD64Instr_FpBinary ( AMD64FpOp op, HReg srcL, HReg srcR, HReg dst ) {
-//.. AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag = Xin_FpBinary;
-//.. i->Xin.FpBinary.op = op;
-//.. i->Xin.FpBinary.srcL = srcL;
-//.. i->Xin.FpBinary.srcR = srcR;
-//.. i->Xin.FpBinary.dst = dst;
-//.. return i;
-//.. }
-//.. AMD64Instr* AMD64Instr_FpLdSt ( Bool isLoad, UChar sz, HReg reg, AMD64AMode* addr ) {
-//.. AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag = Xin_FpLdSt;
-//.. i->Xin.FpLdSt.isLoad = isLoad;
-//.. i->Xin.FpLdSt.sz = sz;
-//.. i->Xin.FpLdSt.reg = reg;
-//.. i->Xin.FpLdSt.addr = addr;
-//.. vassert(sz == 4 || sz == 8);
-//.. return i;
-//.. }
-//.. AMD64Instr* AMD64Instr_FpLdStI ( Bool isLoad, UChar sz,
-//.. HReg reg, AMD64AMode* addr ) {
-//.. AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag = Xin_FpLdStI;
-//.. i->Xin.FpLdStI.isLoad = isLoad;
-//.. i->Xin.FpLdStI.sz = sz;
-//.. i->Xin.FpLdStI.reg = reg;
-//.. i->Xin.FpLdStI.addr = addr;
-//.. vassert(sz == 2 || sz == 4 || sz == 8);
-//.. return i;
-//.. }
-//.. AMD64Instr* AMD64Instr_Fp64to32 ( HReg src, HReg dst ) {
-//.. AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag = Xin_Fp64to32;
-//.. i->Xin.Fp64to32.src = src;
-//.. i->Xin.Fp64to32.dst = dst;
-//.. return i;
-//.. }
-//.. AMD64Instr* AMD64Instr_FpCMov ( AMD64CondCode cond, HReg src, HReg dst ) {
-//.. AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag = Xin_FpCMov;
-//.. i->Xin.FpCMov.cond = cond;
-//.. i->Xin.FpCMov.src = src;
-//.. i->Xin.FpCMov.dst = dst;
-//.. vassert(cond != Xcc_ALWAYS);
-//.. return i;
-//.. }
AMD64Instr* AMD64Instr_LdMXCSR ( AMD64AMode* addr ) {
AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
i->tag = Ain_LdMXCSR;
i->Ain.LdMXCSR.addr = addr;
return i;
}
-//.. AMD64Instr* AMD64Instr_FpStSW_AX ( void ) {
-//.. AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag = Xin_FpStSW_AX;
-//.. return i;
-//.. }
AMD64Instr* AMD64Instr_SseUComIS ( Int sz, HReg srcL, HReg srcR, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
i->tag = Ain_SseUComIS;
@@ -970,15 +893,6 @@
i->Ain.SseSDSS.dst = dst;
return i;
}
-
-//.. AMD64Instr* AMD64Instr_SseConst ( UShort con, HReg dst ) {
-//.. AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
-//.. i->tag = Xin_SseConst;
-//.. i->Xin.SseConst.con = con;
-//.. i->Xin.SseConst.dst = dst;
-//.. vassert(hregClass(dst) == HRcVec128);
-//.. return i;
-//.. }
AMD64Instr* AMD64Instr_SseLdSt ( Bool isLoad, Int sz,
HReg reg, AMD64AMode* addr ) {
AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
@@ -1062,6 +976,36 @@
vassert(order >= 0 && order <= 0xFF);
return i;
}
+//uu AMD64Instr* AMD64Instr_AvxLdSt ( Bool isLoad,
+//uu HReg reg, AMD64AMode* addr ) {
+//uu AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
+//uu i->tag = Ain_AvxLdSt;
+//uu i->Ain.AvxLdSt.isLoad = isLoad;
+//uu i->Ain.AvxLdSt.reg = reg;
+//uu i->Ain.AvxLdSt.addr = addr;
+//uu return i;
+//uu }
+//uu AMD64Instr* AMD64Instr_AvxReRg ( AMD64SseOp op, HReg re, HReg rg ) {
+//uu AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
+//uu i->tag = Ain_AvxReRg;
+//uu i->Ain.AvxReRg.op = op;
+//uu i->Ain.AvxReRg.src = re;
+//uu i->Ain.AvxReRg.dst = rg;
+//uu return i;
+//uu }
+AMD64Instr* AMD64Instr_EvCheck ( AMD64AMode* amCounter,
+ AMD64AMode* amFailAddr ) {
+ AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
+ i->tag = Ain_EvCheck;
+ i->Ain.EvCheck.amCounter = amCounter;
+ i->Ain.EvCheck.amFailAddr = amFailAddr;
+ return i;
+}
+AMD64Instr* AMD64Instr_ProfInc ( void ) {
+ AMD64Instr* i = LibVEX_Alloc(sizeof(AMD64Instr));
+ i->tag = Ain_ProfInc;
+ return i;
+}
void ppAMD64Instr ( AMD64Instr* i, Bool mode64 )
{
@@ -1121,16 +1065,6 @@
showAMD64ScalarSz(i->Ain.Div.sz));
ppAMD64RM(i->Ain.Div.src);
return;
-//.. case Xin_Sh3232:
-//.. vex_printf("%sdl ", showAMD64ShiftOp(i->Xin.Sh3232.op));
-//.. if (i->Xin.Sh3232.amt == 0)
-//.. vex_printf(" %%cl,");
-//.. else
-//.. vex_printf(" $%d,", i->Xin.Sh3232.amt);
-//.. ppHRegAMD64(i->Xin.Sh3232.src);
-//.. vex_printf(",");
-//.. ppHRegAMD64(i->Xin.Sh3232.dst);
-//.. return;
case Ain_Push:
vex_printf("pushq ");
ppAMD64RMI(i->Ain.Push.src);
@@ -1142,25 +1076,41 @@
i->Ain.Call.regparms );
vex_printf("0x%llx", i->Ain.Call.target);
break;
- case Ain_Goto:
- if (i->Ain.Goto.cond != Acc_ALWAYS) {
- vex_printf("if (%%rflags.%s) { ",
- showAMD64CondCode(i->Ain.Goto.cond));
- }
- if (i->Ain.Goto.jk != Ijk_Boring
- && i->Ain.Goto.jk != Ijk_Call
- && i->Ain.Goto.jk != Ijk_Ret) {
- vex_printf("movl $");
- ppIRJumpKind(i->Ain.Goto.jk);
- vex_printf(",%%ebp ; ");
- }
- vex_printf("movq ");
- ppAMD64RI(i->Ain.Goto.dst);
- vex_printf(",%%rax ; movabsq $dispatcher_addr,%%rdx ; jmp *%%rdx");
- if (i->Ain.Goto.cond != Acc_ALWAYS) {
- vex_printf(" }");
- }
+
+ case Ain_XDirect:
+ vex_printf("(xDirect) ");
+ vex_printf("if (%%rflags.%s) { ",
+ showAMD64CondCode(i->Ain.XDirect.cond));
+ vex_printf("movabsq $0x%llx,%%r11; ", i->Ain.XDirect.dstGA);
+ vex_printf("movq %%r11,");
+ ppAMD64AMode(i->Ain.XDirect.amRIP);
+ vex_printf("; ");
+ vex_printf("movabsq $disp_cp_chain_me_to_%sEP,%%r11; call *%%r11 }",
+ i->Ain.XDirect.toFastEP ? "fast" : "slow");
return;
+ case Ain_XIndir:
+ vex_printf("(xIndir) ");
+ vex_printf("if (%%rflags.%s) { ",
+ showAMD64CondCode(i->Ain.XIndir.cond));
+ vex_printf("movq ");
+ ppHRegAMD64(i->Ain.XIndir.dstGA);
+ vex_printf(",");
+ ppAMD64AMode(i->Ain.XIndir.amRIP);
+ vex_printf("; movabsq $disp_indir,%%r11; jmp *%%r11 }");
+ return;
+ case Ain_XAssisted:
+ vex_printf("(xAssisted) ");
+ vex_printf("if (%%rflags.%s) { ",
+ showAMD64CondCode(i->Ain.XAssisted.cond));
+ vex_printf("movq ");
+ ppHRegAMD64(i->Ain.XAssisted.dstGA);
+ vex_printf(",");
+ ppAMD64AMode(i->Ain.XAssisted.amRIP);
+ vex_printf("; movl $IRJumpKind_to_TRCVAL(%d),%%rbp",
+ (Int)i->Ain.XAssisted.jk);
+ vex_printf("; movabsq $disp_assisted,%%r11; jmp *%%r11 }");
+ return;
+
case Ain_CMov64:
vex_printf("cmov%s ", showAMD64CondCode(i->Ain.CMov64.cond));
ppAMD64RM(i->Ain.CMov64.src);
@@ -1241,67 +1191,6 @@
vex_printf("fstsw ");
ppAMD64AMode(i->Ain.A87StSW.addr);
break;
-//.. case Xin_FpUnary:
-//.. vex_printf("g%sD ", showAMD64FpOp(i->Xin.FpUnary.op));
-//.. ppHRegAMD64(i->Xin.FpUnary.src);
-//.. vex_printf(",");
-//.. ppHRegAMD64(i->Xin.FpUnary.dst);
-//.. break;
-//.. case Xin_FpBinary:
-//.. vex_printf("g%sD ", showAMD64FpOp(i->Xin.FpBinary.op));
-//.. ppHRegAMD64(i->Xin.FpBinary.srcL);
-//.. vex_printf(",");
-//.. ppHRegAMD64(i->Xin.FpBinary.srcR);
-//.. vex_printf(",");
-//.. ppHRegAMD64(i->Xin.FpBinary.dst);
-//.. break;
-//.. case Xin_FpLdSt:
-//.. if (i->Xin.FpLdSt.isLoad) {
-//.. vex_printf("gld%c " , i->Xin.FpLdSt.sz==8 ? 'D' : 'F');
-//.. ppAMD64AMode(i->Xin.FpLdSt.addr);
-//.. vex_printf(", ");
-//.. ppHRegAMD64(i->Xin.FpLdSt.reg);
-//.. } else {
-//.. vex_printf("gst%c " , i->Xin.FpLdSt.sz==8 ? 'D' : 'F');
-//.. ppHRegAMD64(i->Xin.FpLdSt.reg);
-//.. vex_printf(", ");
-//.. ppAMD64AMode(i->Xin.FpLdSt.addr);
-//.. }
-//.. return;
-//.. case Xin_FpLdStI:
-//.. if (i->Xin.FpLdStI.isLoad) {
-//.. vex_printf("gild%s ", i->Xin.FpLdStI.sz==8 ? "ll" :
-//.. i->Xin.FpLdStI.sz==4 ? "l" : "w");
-//.. ppAMD64AMode(i->Xin.FpLdStI.addr);
-//.. vex_printf(", ");
-//.. ppHRegAMD64(i->Xin.FpLdStI.reg);
-//.. } else {
-//.. vex_printf("gist%s ", i->Xin.FpLdStI.sz==8 ? "ll" :
-//.. i->Xin.FpLdStI.sz==4 ? "l" : "w");
-//.. ppHRegAMD64(i->Xin.FpLdStI.reg);
-//.. vex_printf(", ");
-//.. ppAMD64AMode(i->Xin.FpLdStI.addr);
-//.. }
-//.. return;
-//.. case Xin_Fp64to32:
-//.. vex_printf("gdtof ");
-//.. ppHRegAMD64(i->Xin.Fp64to32.src);
-//.. vex_printf(",");
-//.. ppHRegAMD64(i->Xin.Fp64to32.dst);
-//.. return;
-//.. case Xin_FpCMov:
-//.. vex_printf("gcmov%s ", showAMD64CondCode(i->Xin.FpCMov.cond));
-//.. ppHRegAMD64(i->Xin.FpCMov.src);
-//.. vex_printf(",");
-//.. ppHRegAMD64(i->Xin.FpCMov.dst);
-//.. return;
-//.. case Xin_FpLdStCW:
-//.. vex_printf(i->Xin.FpLdStCW.isLoad ? "fldcw " : "fstcw ");
-//.. ppAMD64AMode(i->Xin.FpLdStCW.addr);
-//.. return;
-//.. case Xin_FpStSW_AX:
-//.. vex_printf("fstsw %%ax");
-//.. return;
case Ain_LdMXCSR:
vex_printf("ldmxcsr ");
ppAMD64AMode(i->Ain.LdMXCSR.addr);
@@ -1334,10 +1223,6 @@
vex_printf(",");
ppHRegAMD64(i->Ain.SseSDSS.dst);
break;
-//.. case Xin_SseConst:
-//.. vex_printf("const $0x%04x,", (Int)i->Xin.SseConst.con);
-//.. ppHRegAMD64(i->Xin.SseConst.dst);
-//.. break;
case Ain_SseLdSt:
switch (i->Ain.SseLdSt.sz) {
case 4: vex_printf("movss "); break;
@@ -1403,7 +1288,34 @@
vex_printf(",");
ppHRegAMD64(i->Ain.SseShuf.dst);
return;
-
+ //uu case Ain_AvxLdSt:
+ //uu vex_printf("vmovups ");
+ //uu if (i->Ain.AvxLdSt.isLoad) {
+ //uu ppAMD64AMode(i->Ain.AvxLdSt.addr);
+ //uu vex_printf(",");
+ //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
+ //uu } else {
+ //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
+ //uu vex_printf(",");
+ //uu ppAMD64AMode(i->Ain.AvxLdSt.addr);
+ //uu }
+ //uu return;
+ //uu case Ain_AvxReRg:
+ //uu vex_printf("v%s ", showAMD64SseOp(i->Ain.SseReRg.op));
+ //uu ppHRegAMD64(i->Ain.AvxReRg.src);
+ //uu vex_printf(",");
+ //uu ppHRegAMD64(i->Ain.AvxReRg.dst);
+ //uu return;
+ case Ain_EvCheck:
+ vex_printf("(evCheck) decl ");
+ ppAMD64AMode(i->Ain.EvCheck.amCounter);
+ vex_printf("; jns nofail; jmp *");
+ ppAMD64AMode(i->Ain.EvCheck.amFailAddr);
+ vex_printf("; nofail:");
+ return;
+ case Ain_ProfInc:
+ vex_printf("(profInc) movabsq $NotKnownYet, %%r11; incq (%%r11)");
+ return;
default:
vpanic("ppAMD64Instr");
}
@@ -1470,12 +1382,6 @@
addHRegUse(u, HRmModify, hregAMD64_RAX());
addHRegUse(u, HRmModify, hregAMD64_RDX());
return;
-//.. case Xin_Sh3232:
-//.. addHRegUse(u, HRmRead, i->Xin.Sh3232.src);
-//.. addHRegUse(u, HRmModify, i->Xin.Sh3232.dst);
-//.. if (i->Xin.Sh3232.amt == 0)
-//.. addHRegUse(u, HRmRead, hregAMD64_ECX());
-//.. return;
case Ain_Push:
addRegUsage_AMD64RMI(u, i->Ain.Push.src);
addHRegUse(u, HRmModify, hregAMD64_RSP());
@@ -1498,7 +1404,6 @@
addHRegUse(u, HRmWrite, hregAMD64_R11());
addHRegUse(u, HRmWrite, hregAMD64_XMM0());
addHRegUse(u, HRmWrite, hregAMD64_XMM1());
- addHRegUse(u, HRmWrite, hregAMD64_XMM2());
addHRegUse(u, HRmWrite, hregAMD64_XMM3());
addHRegUse(u, HRmWrite, hregAMD64_XMM4());
addHRegUse(u, HRmWrite, hregAMD64_XMM5());
@@ -1509,9 +1414,6 @@
addHRegUse(u, HRmWrite, hregAMD64_XMM10());
addHRegUse(u, HRmWrite, hregAMD64_XMM11());
addHRegUse(u, HRmWrite, hregAMD64_XMM12());
- addHRegUse(u, HRmWrite, hregAMD64_XMM13());
- addHRegUse(u, HRmWrite, hregAMD64_XMM14());
- addHRegUse(u, HRmWrite, hregAMD64_XMM15());
/* Now we have to state any parameter-carrying registers
which might be read. This depends on the regparmness. */
@@ -1533,16 +1435,25 @@
/* Upshot of this is that the assembler really must use r11,
and no other, as a destination temporary. */
return;
- case Ain_Goto:
- addRegUsage_AMD64RI(u, i->Ain.Goto.dst);
- addHRegUse(u, HRmWrite, hregAMD64_RAX()); /* used for next guest addr */
- addHRegUse(u, HRmWrite, hregAMD64_RDX()); /* used for dispatcher addr */
- if (i->Ain.Goto.jk != Ijk_Boring
- && i->Ain.Goto.jk != Ijk_Call
- && i->Ain.Goto.jk != Ijk_Ret)
- /* note, this is irrelevant since rbp is not actually
- available to the allocator. But still .. */
- addHRegUse(u, HRmWrite, hregAMD64_RBP());
+ /* XDirect/XIndir/XAssisted are also a bit subtle. They
+ conditionally exit the block. Hence we only need to list (1)
+ the registers that they read, and (2) the registers that they
+ write in the case where the block is not exited. (2) is
+ empty, hence only (1) is relevant here. */
+ case Ain_XDirect:
+ /* Don't bother to mention the write to %r11, since it is not
+ available to the allocator. */
+ addRegUsage_AMD64AMode(u, i->Ain.XDirect.amRIP);
+ return;
+ case Ain_XIndir:
+ /* Ditto re %r11 */
+ addHRegUse(u, HRmRead, i->Ain.XIndir.dstGA);
+ addRegUsage_AMD64AMode(u, i->Ain.XIndir.amRIP);
+ return;
+ case Ain_XAssisted:
+ /* Ditto re %r11 and %rbp (the baseblock ptr) */
+ addHRegUse(u, HRmRead, i->Ain.XAssisted.dstGA);
+ addRegUsage_AMD64AMode(u, i->Ain.XAssisted.amRIP);
return;
case Ain_CMov64:
addRegUsage_AMD64RM(u, i->Ain.CMov64.src, HRmRead);
@@ -1594,39 +1505,9 @@
case Ain_A87StSW:
addRegUsage_AMD64AMode(u, i->Ain.A87StSW.addr);
return;
-//.. case Xin_FpUnary:
-//.. addHRegUse(u, HRmRead, i->Xin.FpUnary.src);
-//.. addHRegUse(u, HRmWrite, i->Xin.FpUnary.dst);
-//.. return;
-//.. case Xin_FpBinary:
-//.. addHRegUse(u, HRmRead, i->Xin.FpBinary.srcL);
-//.. addHRegUse(u, HRmRead, i->Xin.FpBinary.srcR);
-//.. addHRegUse(u, HRmWrite, i->Xin.FpBinary.dst);
-//.. return;
-//.. case Xin_FpLdSt:
-//.. addRegUsage_AMD64AMode(u, i->Xin.FpLdSt.addr);
-//.. addHRegUse(u, i->Xin.FpLdSt.isLoad ? HRmWrite : HRmRead,
-//.. i->Xin.FpLdSt.reg);
-//.. return;
-//.. case Xin_FpLdStI:
-//.. addRegUsage_AMD64AMode(u, i->Xin.FpLdStI.addr);
-//.. addHRegUse(u, i->Xin.FpLdStI.isLoad ? HRmWrite : HRmRead,
-//.. i->Xin.FpLdStI.reg);
-//.. return;
-//.. case Xin_Fp64to32:
-//.. addHRegUse(u, HRmRead, i->Xin.Fp64to32.src);
-//.. addHRegUse(u, HRmWrite, i->Xin.Fp64to32.dst);
-//.. return;
-//.. case Xin_FpCMov:
-//.. addHRegUse(u, HRmRead, i->Xin.FpCMov.src);
-//.. addHRegUse(u, HRmModify, i->Xin.FpCMov.dst);
-//.. return;
case Ain_LdMXCSR:
addRegUsage_AMD64AMode(u, i->Ain.LdMXCSR.addr);
return;
-//.. case Xin_FpStSW_AX:
-//.. addHRegUse(u, HRmWrite, hregAMD64_EAX());
-//.. return;
case Ain_SseUComIS:
addHRegUse(u, HRmRead, i->Ain.SseUComIS.srcL);
addHRegUse(u, HRmRead, i->Ain.SseUComIS.srcR);
@@ -1653,9 +1534,6 @@
addRegUsage_AMD64AMode(u, i->Ain.SseLdzLO.addr);
addHRegUse(u, HRmWrite, i->Ain.SseLdzLO.reg);
return;
-//.. case Xin_SseConst:
-//.. addHRegUse(u, HRmWrite, i->Xin.SseConst.dst);
-//.. return;
case Ain_Sse32Fx4:
vassert(i->Ain.Sse32Fx4.op != Asse_MOV);
unary = toBool( i->Ain.Sse32Fx4.op == Asse_RCPF
@@ -1716,6 +1594,33 @@
addHRegUse(u, HRmRead, i->Ain.SseShuf.src);
addHRegUse(u, HRmWrite, i->Ain.SseShuf.dst);
return;
+ //uu case Ain_AvxLdSt:
+ //uu addRegUsage_AMD64AMode(u, i->Ain.AvxLdSt.addr);
+ //uu addHRegUse(u, i->Ain.AvxLdSt.isLoad ? HRmWrite : HRmRead,
+ //uu i->Ain.AvxLdSt.reg);
+ //uu return;
+ //uu case Ain_AvxReRg:
+ //uu if ( (i->Ain.AvxReRg.op == Asse_XOR
+ //uu || i->Ain.AvxReRg.op == Asse_CMPEQ32)
+ //uu && i->Ain.AvxReRg.src == i->Ain.AvxReRg.dst) {
+ //uu /* See comments on the case for Ain_SseReRg. */
+ //uu addHRegUse(u, HRmWrite, i->Ain.AvxReRg.dst);
+ //uu } else {
+ //uu addHRegUse(u, HRmRead, i->Ain.AvxReRg.src);
+ //uu addHRegUse(u, i->Ain.AvxReRg.op == Asse_MOV
+ //uu ? HRmWrite : HRmModify,
+ //uu i->Ain.AvxReRg.dst);
+ //uu }
+ //uu return;
+ case Ain_EvCheck:
+ /* We expect both amodes only to mention %rbp, so this is in
+ fact pointless, since %rbp isn't allocatable, but anyway.. */
+ addRegUsage_AMD64AMode(u, i->Ain.EvCheck.amCounter);
+ addRegUsage_AMD64AMode(u, i->Ain.EvCheck.amFailAddr);
+ return;
+ case Ain_ProfInc:
+ addHRegUse(u, HRmWrite, hregAMD64_R11());
+ return;
default:
ppAMD64Instr(i, mode64);
vpanic("getRegUsage_AMD64Instr");
@@ -1766,17 +1671,21 @@
case Ain_Div:
mapRegs_AMD64RM(m, i->Ain.Div.src);
return;
-//.. case Xin_Sh3232:
-//.. mapReg(m, &i->Xin.Sh3232.src);
-//.. mapReg(m, &i->Xin.Sh3232.dst);
-//.. return;
case Ain_Push:
mapRegs_AMD64RMI(m, i->Ain.Push.src);
return;
case Ain_Call:
return;
- case Ain_Goto:
- mapRegs_AMD64RI(m, i->Ain.Goto.dst);
+ case Ain_XDirect:
+ mapRegs_AMD64AMode(m, i->Ain.XDirect.amRIP);
+ return;
+ case Ain_XIndir:
+ mapReg(m, &i->Ain.XIndir.dstGA);
+ mapRegs_AMD64AMode(m, i->Ain.XIndir.amRIP);
+ return;
+ case Ain_XAssisted:
+ mapReg(m, &i->Ain.XAssisted.dstGA);
+ mapRegs_AMD64AMode(m, i->Ain.XAssisted.amRIP);
return;
case Ain_CMov64:
mapRegs_AMD64RM(m, i->Ain.CMov64.src);
@@ -1822,36 +1731,9 @@
case Ain_A87StSW:
mapRegs_AMD64AMode(m, i->Ain.A87StSW.addr);
return;
-//.. case Xin_FpUnary:
-//.. mapReg(m, &i->Xin.FpUnary.src);
-//.. mapReg(m, &i->Xin.FpUnary.dst);
-//.. return;
-//.. case Xin_FpBinary:
-//.. mapReg(m, &i->Xin.FpBinary.srcL);
-//.. mapReg(m, &i->Xin.FpBinary.srcR);
-//.. mapReg(m, &i->Xin.FpBinary.dst);
-//.. return;
-//.. case Xin_FpLdSt:
-//.. mapRegs_AMD64AMode(m, i->Xin.FpLdSt.addr);
-//.. mapReg(m, &i->Xin.FpLdSt.reg);
-//.. return;
-//.. case Xin_FpLdStI:
-//.. mapRegs_AMD64AMode(m, i->Xin.FpLdStI.addr);
-//.. mapReg(m, &i->Xin.FpLdStI.reg);
-//.. return;
-//.. case Xin_Fp64to32:
-//.. mapReg(m, &i->Xin.Fp64to32.src);
-//.. mapReg(m, &i->Xin.Fp64to32.dst);
-//.. return;
-//.. case Xin_FpCMov:
-//.. mapReg(m, &i->Xin.FpCMov.src);
-//.. mapReg(m, &i->Xin.FpCMov.dst);
-//.. return;
case Ain_LdMXCSR:
mapRegs_AMD64AMode(m, i->Ain.LdMXCSR.addr);
return;
-//.. case Xin_FpStSW_AX:
-//.. return;
case Ain_SseUComIS:
mapReg(m, &i->Ain.SseUComIS.srcL);
mapReg(m, &i->Ain.SseUComIS.srcR);
@@ -1869,9 +1751,6 @@
mapReg(m, &i->Ain.SseSDSS.src);
mapReg(m, &i->Ain.SseSDSS.dst);
return;
-//.. case Xin_SseConst:
-//.. mapReg(m, &i->Xin.SseConst.dst);
-//.. return;
case Ain_SseLdSt:
mapReg(m, &i->Ain.SseLdSt.reg);
mapRegs_AMD64AMode(m, i->Ain.SseLdSt.addr);
@@ -1908,6 +1787,23 @@
mapReg(m, &i->Ain.SseShuf.src);
mapReg(m, &i->Ain.SseShuf.dst);
return;
+ //uu case Ain_AvxLdSt:
+ //uu mapReg(m, &i->Ain.AvxLdSt.reg);
+ //uu mapRegs_AMD64AMode(m, i->Ain.AvxLdSt.addr);
+ //uu break;
+ //uu case Ain_AvxReRg:
+ //uu mapReg(m, &i->Ain.AvxReRg.src);
+ //uu mapReg(m, &i->Ain.AvxReRg.dst);
+ //uu return;
+ case Ain_EvCheck:
+ /* We expect both amodes only to mention %rbp, so this is in
+ fact pointless, since %rbp isn't allocatable, but anyway.. */
+ mapRegs_AMD64AMode(m, i->Ain.EvCheck.amCounter);
+ mapRegs_AMD64AMode(m, i->Ain.EvCheck.amFailAddr);
+ return;
+ case Ain_ProfInc:
+ /* hardwires r11 -- nothing to modify. */
+ return;
default:
ppAMD64Instr(i, mode64);
vpanic("mapRegs_AMD64Instr");
@@ -1920,25 +1816,34 @@
*/
Bool isMove_AMD64Instr ( AMD64Instr* i, HReg* src, HReg* dst )
{
- /* Moves between integer regs */
- if (i->tag == Ain_Alu64R) {
- if (i->Ain.Alu64R.op != Aalu_MOV)
+ switch (i->tag) {
+ case Ain_Alu64R:
+ /* Moves between integer regs */
+ if (i->Ain.Alu64R.op != Aalu_MOV)
+ return False;
+ if (i->Ain.Alu64R.src->tag != Armi_Reg)
+ return False;
+ *src = i->Ain.Alu64R.src->Armi.Reg.reg;
+ *dst = i->Ain.Alu64R.dst;
+ return True;
+ case Ain_SseReRg:
+ /* Moves between SSE regs */
+ if (i->Ain.SseReRg.op != Asse_MOV)
+ return False;
+ *src = i->Ain.SseReRg.src;
+ *dst = i->Ain.SseReRg.dst;
+ return True;
+ //uu case Ain_AvxReRg:
+ //uu /* Moves between AVX regs */
+ //uu if (i->Ain.AvxReRg.op != Asse_MOV)
+ //uu return False;
+ //uu *src = i->Ain.AvxReRg.src;
+ //uu *dst = i->Ain.AvxReRg.dst;
+ //uu return True;
+ default:
return False;
- if (i->Ain.Alu64R.src->tag != Armi_Reg)
- return False;
- *src = i->Ain.Alu64R.src->Armi.Reg.reg;
- *dst = i->Ain.Alu64R.dst;
- return True;
}
- /* Moves between vector regs */
- if (i->tag == Ain_SseReRg) {
- if (i->Ain.SseReRg.op != Asse_MOV)
- return False;
- *src = i->Ain.SseReRg.src;
- *dst = i->Ain.SseReRg.dst;
- return True;
- }
- return False;
+ /*NOTREACHED*/
}
@@ -2041,6 +1946,17 @@
return mkHReg(n, HRcInt64, False);
}
+//uu /* Ditto for ymm regs. */
+//uu static UInt dvreg2ireg ( HReg r )
+//uu {
+//uu UInt n;
+//uu vassert(hregClass(r) == HRcVec256);
+//uu vassert(!hregIsVirtual(r));
+//uu n = hregNumber(r);
+//uu vassert(n <= 15);
+//uu return mkHReg(n, HRcInt64, False);
+//uu }
+
static UChar mkModRegRM ( UChar mod, UChar reg, UChar regmem )
{
return toUChar( ((mod & 3) << 6)
@@ -2243,6 +2159,87 @@
}
+//uu /* May 2012: this VEX prefix stuff is currently unused, but has
+//uu verified correct (I reckon). Certainly it has been known to
+//uu produce correct VEX prefixes during testing. */
+//uu
+//uu /* Assemble a 2 or 3 byte VEX prefix from parts. rexR, rexX, rexB and
+//uu notVvvvv need to be not-ed before packing. mmmmm, rexW, L and pp go
+//uu in verbatim. There's no range checking on the bits. */
+//uu static UInt packVexPrefix ( UInt rexR, UInt rexX, UInt rexB,
+//uu UInt mmmmm, UInt rexW, UInt notVvvv,
+//uu UInt L, UInt pp )
+//uu {
+//uu UChar byte0 = 0;
+//uu UChar byte1 = 0;
+//uu UChar byte2 = 0;
+//uu if (rexX == 0 && rexB == 0 && mmmmm == 1 && rexW == 0) {
+//uu /* 2 byte encoding is possible. */
+//uu byte0 = 0xC5;
+//uu byte1 = ((rexR ^ 1) << 7) | ((notVvvv ^ 0xF) << 3)
+//uu | (L << 2) | pp;
+//uu } else {
+//uu /* 3 byte encoding is needed. */
+//uu byte0 = 0xC4;
+//uu byte1 = ((rexR ^ 1) << 7) | ((rexX ^ 1) << 6)
+//uu | ((rexB ^ 1) << 5) | mmmmm;
+//uu byte2 = (rexW << 7) | ((notVvvv ^ 0xF) << 3) | (L << 2) | pp;
+//uu }
+//uu return (((UInt)byte2) << 16) | (((UInt)byte1) << 8) | ((UInt)byte0);
+//uu }
+//uu
+//uu /* Make up a VEX prefix for a (greg,amode) pair. First byte in bits
+//uu 7:0 of result, second in 15:8, third (for a 3 byte prefix) in
+//uu 23:16. Has m-mmmm set to indicate a prefix of 0F, pp set to
+//uu indicate no SIMD prefix, W=0 (ignore), L=1 (size=256), and
+//uu vvvv=1111 (unused 3rd reg). */
+//uu static UInt vexAMode_M ( HReg greg, AMD64AMode* am )
+//uu {
+//uu UChar L = 1; /* size = 256 */
+//uu UChar pp = 0; /* no SIMD prefix */
+//uu UChar mmmmm = 1; /* 0F */
+//uu UChar notVvvv = 0; /* unused */
+//uu UChar rexW = 0;
+//uu UChar rexR = 0;
+//uu UChar rexX = 0;
+//uu UChar rexB = 0;
+//uu /* Same logic as in rexAMode_M. */
+//uu if (am->tag == Aam_IR) {
+//uu rexR = iregBit3(greg);
+//uu rexX = 0; /* not relevant */
+//uu rexB = iregBit3(am->Aam.IR.reg);
+//uu }
+//uu else if (am->tag == Aam_IRRS) {
+//uu rexR = iregBit3(greg);
+//uu rexX = iregBit3(am->Aam.IRRS.index);
+//uu rexB = iregBit3(am->Aam.IRRS.base);
+//uu } else {
+//uu vassert(0);
+//uu }
+//uu return packVexPrefix( rexR, rexX, rexB, mmmmm, rexW, notVvvv, L, pp );
+//uu }
+//uu
+//uu static UChar* emitVexPrefix ( UChar* p, UInt vex )
+//uu {
+//uu switch (vex & 0xFF) {
+//uu case 0xC5:
+//uu *p++ = 0xC5;
+//uu *p++ = (vex >> 8) & 0xFF;
+//uu vassert(0 == (vex >> 16));
+//uu break;
+//uu case 0xC4:
+//uu *p++ = 0xC4;
+//uu *p++ = (vex >> 8) & 0xFF;
+//uu *p++ = (vex >> 16) & 0xFF;
+//uu vassert(0 == (vex >> 24));
+//uu break;
+//uu default:
+//uu vassert(0);
+//uu }
+//uu return p;
+//uu }
+
+
/* Emit ffree %st(N) */
static UChar* do_ffree_st ( UChar* p, Int n )
{
@@ -2252,101 +2249,19 @@
return p;
}
-//.. /* Emit fstp %st(i), 1 <= i <= 7 */
-//.. static UChar* do_fstp_st ( UChar* p, Int i )
-//.. {
-//.. vassert(1 <= i && i <= 7);
-//.. *p++ = 0xDD;
-//.. *p++ = 0xD8+i;
-//.. return p;
-//.. }
-//..
-//.. /* Emit fld %st(i), 0 <= i <= 6 */
-//.. static UChar* do_fld_st ( UChar* p, Int i )
-//.. {
-//.. vassert(0 <= i && i <= 6);
-//.. *p++ = 0xD9;
-//.. *p++ = 0xC0+i;
-//.. return p;
-//.. }
-//..
-//.. /* Emit f<op> %st(0) */
-//.. static UChar* do_fop1_st ( UChar* p, AMD64FpOp op )
-//.. {
-//.. switch (op) {
-//.. case Xfp_NEG: *p++ = 0xD9; *p++ = 0xE0; break;
-//.. case Xfp_ABS: *p++ = 0xD9; *p++ = 0xE1; break;
-//.. case Xfp_SQRT: *p++ = 0xD9; *p++ = 0xFA; break;
-//.. case Xfp_ROUND: *p++ = 0xD9; *p++ = 0xFC; break;
-//.. case Xfp_SIN: *p++ = 0xD9; *p++ = 0xFE; break;
-//.. case Xfp_COS: *p++ = 0xD9; *p++ = 0xFF; break;
-//.. case Xfp_2XM1: *p++ = 0xD9; *p++ = 0xF0; break;
-//.. case Xfp_MOV: break;
-//.. case Xfp_TAN: p = do_ffree_st7(p); /* since fptan pushes 1.0 */
-//.. *p++ = 0xD9; *p++ = 0xF2; /* fptan */
-//.. *p++ = 0xD9; *p++ = 0xF7; /* fincstp */
-//.. break;
-//.. default: vpanic("do_fop1_st: unknown op");
-//.. }
-//.. return p;
-//.. }
-//..
-//.. /* Emit f<op> %st(i), 1 <= i <= 5 */
-//.. static UChar* do_fop2_st ( UChar* p, AMD64FpOp op, Int i )
-//.. {
-//.. # define fake(_n) mkHReg((_n), HRcInt32, False)
-//.. Int subopc;
-//.. switch (op) {
-//.. case Xfp_ADD: subopc = 0; break;
-//.. case Xfp_SUB: subopc = 4; break;
-//.. case Xfp_MUL: subopc = 1; break;
-//.. case Xfp_DIV: subopc = 6; break;
-//.. default: vpanic("do_fop2_st: unknown op");
-//.. }
-//.. *p++ = 0xD8;
-//.. p = doAMode_R(p, fake(subopc), fake(i));
-//.. return p;
-//.. # undef fake
-//.. }
-//..
-//.. /* Push a 32-bit word on the stack. The word depends on tags[3:0];
-//.. each byte is either 0x00 or 0xFF depending on the corresponding bit in tags[].
-//.. */
-//.. static UChar* push_word_from_tags ( UChar* p, UShort tags )
-//.. {
-//.. UInt w;
-//.. vassert(0 == (tags & ~0xF));
-//.. if (tags == 0) {
-//.. /* pushl $0x00000000 */
-//.. *p++ = 0x6A;
-//.. *p++ = 0x00;
-//.. }
-//.. else
-//.. /* pushl $0xFFFFFFFF */
-//.. if (tags == 0xF) {
-//.. *p++ = 0x6A;
-//.. *p++ = 0xFF;
-//.. } else {
-//.. vassert(0); /* awaiting test case */
-//.. w = 0;
-//.. if (tags & 1) w |= 0x000000FF;
-//.. if (tags & 2) w |= 0x0000FF00;
-//.. if (tags & 4) w |= 0x00FF0000;
-//.. if (tags & 8) w |= 0xFF000000;
-//.. *p++ = 0x68;
-//.. p = emit32(p, w);
-//.. }
-//.. return p;
-//.. }
-
/* Emit an instruction into buf and return the number of bytes used.
Note that buf is not the insn's final place, and therefore it is
- imperative to emit position-independent code. */
+ imperative to emit position-independent code. If the emitted
+ instruction was a profiler inc, set *is_profInc to True, else
+ leave it unchanged. */
-Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i,
+Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, AMD64Instr* i,
Bool mode64,
- void* dispatch_unassisted,
- void* dispatch_assisted )
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted )
{
UInt /*irno,*/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc;
UInt xtra;
@@ -2545,35 +2460,6 @@
goto bad;
}
}
-//.. /* ADD/SUB/ADC/SBB/AND/OR/XOR/CMP. MUL is not
-//.. allowed here. */
-//.. opc = subopc_imm = opc_imma = 0;
-//.. switch (i->Xin.Alu32M.op) {
-//.. case Xalu_ADD: opc = 0x01; subopc_imm = 0; break;
-//.. case Xalu_SUB: opc = 0x29; subopc_imm = 5; break;
-//.. default: goto bad;
-//.. }
-//.. switch (i->Xin.Alu32M.src->tag) {
-//.. case Xri_Reg:
-//.. *p++ = opc;
-//.. p = doAMode_M(p, i->Xin.Alu32M.src->Xri.Reg.reg,
-//.. i->Xin.Alu32M.dst);
-//.. goto done;
-//.. case Xri_Imm:
-//.. if (fits8bits(i->Xin.Alu32M.src->Xri.Imm.imm32)) {
-//.. *p++ = 0x83;
-//.. p = doAMode_M(p, fake(subopc_imm), i->Xin.Alu32M.dst);
-//.. *p++ = 0xFF & i->Xin.Alu32M.src->Xri.Imm.imm32;
-//.. goto done;
-//.. } else {
-//.. *p++ = 0x81;
-//.. p = doAMode_M(p, fake(subopc_imm), i->Xin.Alu32M.dst);
-//.. p = emit32(p, i->Xin.Alu32M.src->Xri.Imm.imm32);
-//.. goto done;
-//.. }
-//.. default:
-//.. goto bad;
-//.. }
break;
case Ain_Sh64:
@@ -2756,21 +2642,6 @@
}
break;
-//.. case Xin_Sh3232:
-//.. vassert(i->Xin.Sh3232.op == Xsh_SHL || i->Xin.Sh3232.op == Xsh_SHR);
-//.. if (i->Xin.Sh3232.amt == 0) {
-//.. /* shldl/shrdl by %cl */
-//.. *p++ = 0x0F;
-//.. if (i->Xin.Sh3232.op == Xsh_SHL) {
-//.. *p++ = 0xA5;
-//.. } else {
-//.. *p++ = 0xAD;
-//.. }
-//.. p = doAMode_R(p, i->Xin.Sh3232.src, i->Xin.Sh3232.dst);
-//.. goto done;
-//.. }
-//.. break;
-
case Ain_Push:
switch (i->Ain.Push.src->tag) {
case Armi_Mem:
@@ -2822,120 +2693,189 @@
goto done;
}
- case Ain_Goto: {
- void* dispatch_to_use = NULL;
- vassert(dispatch_unassisted != NULL);
- vassert(dispatch_assisted != NULL);
+ case Ain_XDirect: {
+ /* NB: what goes on here has to be very closely coordinated with the
+ chainXDirect_AMD64 and unchainXDirect_AMD64 below. */
+ /* We're generating chain-me requests here, so we need to be
+ sure this is actually allowed -- no-redir translations can't
+ use chain-me's. Hence: */
+ vassert(disp_cp_chain_me_to_slowEP != NULL);
+ vassert(disp_cp_chain_me_to_fastEP != NULL);
+
+ HReg r11 = hregAMD64_R11();
/* Use ptmp for backpatching conditional jumps. */
ptmp = NULL;
/* First off, if this is conditional, create a conditional
jump over the rest of it. */
- if (i->Ain.Goto.cond != Acc_ALWAYS) {
+ if (i->Ain.XDirect.cond != Acc_ALWAYS) {
/* jmp fwds if !condition */
- *p++ = toUChar(0x70 + (i->Ain.Goto.cond ^ 1));
+ *p++ = toUChar(0x70 + (0xF & (i->Ain.XDirect.cond ^ 1)));
ptmp = p; /* fill in this bit later */
*p++ = 0; /* # of bytes to jump over; don't know how many yet. */
}
- /* If a non-boring, set %rbp (the guest state pointer)
- appropriately. Since these numbers are all small positive
- integers, we can get away with "movl $N, %ebp" rather than
- the longer "movq $N, %rbp". Also, decide which dispatcher we
- need to use. */
- dispatch_to_use = dispatch_assisted;
-
- /* movl $magic_number, %ebp */
- switch (i->Ain.Goto.jk) {
- case Ijk_ClientReq:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_CLIENTREQ); break;
- case Ijk_Sys_syscall:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SYS_SYSCALL); break;
- case Ijk_Sys_int32:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SYS_INT32); break;
- case Ijk_Yield:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_YIELD); break;
- case Ijk_YieldNoRedir:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_YIELD_NOREDIR); break;
- case Ijk_EmWarn:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_EMWARN); break;
- case Ijk_MapFail:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_MAPFAIL); break;
- case Ijk_NoDecode:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_NODECODE); break;
- case Ijk_TInval:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_TINVAL); break;
- case Ijk_NoRedir:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_NOREDIR); break;
- case Ijk_SigTRAP:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SIGTRAP); break;
- case Ijk_SigSEGV:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SIGSEGV); break;
- case Ijk_Ret:
- case Ijk_Call:
- case Ijk_Boring:
- dispatch_to_use = dispatch_unassisted;
- break;
- default:
- ppIRJumpKind(i->Ain.Goto.jk);
- vpanic("emit_AMD64Instr.Ain_Goto: unknown jump kind");
- }
-
- /* Get the destination address into %rax */
- if (i->Ain.Goto.dst->tag == Ari_Imm) {
- /* movl sign-ext($immediate), %rax ; ret */
- *p++ = 0x48;
+ /* Update the guest RIP. */
+ if (fitsIn32Bits(i->Ain.XDirect.dstGA)) {
+ /* use a shorter encoding */
+ /* movl sign-extend(dstGA), %r11 */
+ *p++ = 0x49;
*p++ = 0xC7;
- *p++ = 0xC0;
- p = emit32(p, i->Ain.Goto.dst->Ari.Imm.imm32);
+ *p++ = 0xC3;
+ p = emit32(p, (UInt)i->Ain.XDirect.dstGA);
} else {
- vassert(i->Ain.Goto.dst->tag == Ari_Reg);
- /* movq %reg, %rax ; ret */
- if (i->Ain.Goto.dst->Ari.Reg.reg != hregAMD64_RAX()) {
- *p++ = rexAMode_R(i->Ain.Goto.dst->Ari.Reg.reg, hregAMD64_RAX());
- *p++ = 0x89;
- p = doAMode_R(p, i->Ain.Goto.dst->Ari.Reg.reg, hregAMD64_RAX());
- }
+ /* movabsq $dstGA, %r11 */
+ *p++ = 0x49;
+ *p++ = 0xBB;
+ p = emit64(p, i->Ain.XDirect.dstGA);
}
- /* Get the dispatcher address into %rdx. This has to happen
- after the load of %rax since %rdx might be carrying the value
- destined for %rax immediately prior to this Ain_Goto. */
- vassert(sizeof(ULong) == sizeof(void*));
+ /* movq %r11, amRIP */
+ *p++ = rexAMode_M(r11, i->Ain.XDirect.amRIP);
+ *p++ = 0x89;
+ p = doAMode_M(p, r11, i->Ain.XDirect.amRIP);
- if (fitsIn32Bits(Ptr_to_ULong(dispatch_to_use))) {
- /* movl sign-extend(imm32), %rdx */
- *p++ = 0x48;
- *p++ = 0xC7;
- *p++ = 0xC2;
- p = emit32(p, (UInt)Ptr_to_ULong(dispatch_to_use));
- } else {
- /* movabsq $imm64, %rdx */
- *p++ = 0x48;
- *p++ = 0xBA;
- p = emit64(p, Ptr_to_ULong(dispatch_to_use));
- }
- /* jmp *%rdx */
+ /* --- FIRST PATCHABLE BYTE follows --- */
+ /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're calling
+ to) backs up the return address, so as to find the address of
+ the first patchable byte. So: don't change the length of the
+ two instructions below. */
+ /* movabsq $disp_cp_chain_me_to_{slow,fast}EP,%r11; */
+ *p++ = 0x49;
+ *p++ = 0xBB;
+ void* disp_cp_chain_me
+ = i->Ain.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
+ : disp_cp_chain_me_to_slowEP;
+ p = emit64(p, Ptr_to_ULong(disp_cp_chain_me));
+ /* call *%r11 */
+ *p++ = 0x41;
*p++ = 0xFF;
- *p++ = 0xE2;
+ *p++ = 0xD3;
+ /* --- END of PATCHABLE BYTES --- */
/* Fix up the conditional jump, if there was one. */
- if (i->Ain.Goto.cond != Acc_ALWAYS) {
+ if (i->Ain.XDirect.cond != Acc_ALWAYS) {
Int delta = p - ptmp;
- vassert(delta > 0 && delta < 30);
+ vassert(delta > 0 && delta < 40);
+ *ptmp = toUChar(delta-1);
+ }
+ goto done;
+ }
+
+ case Ain_XIndir: {
+ /* We're generating transfers that could lead indirectly to a
+ chain-me, so we need to be sure this is actually allowed --
+ no-redir translations are not allowed to reach normal
+ translations without going through the scheduler. That means
+ no XDirects or XIndirs out from no-redir translations.
+ Hence: */
+ vassert(disp_cp_xindir != NULL);
+
+ /* Use ptmp for backpatching conditional jumps. */
+ ptmp = NULL;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. */
+ if (i->Ain.XIndir.cond != Acc_ALWAYS) {
+ /* jmp fwds if !condition */
+ *p++ = toUChar(0x70 + (0xF & (i->Ain.XIndir.cond ^ 1)));
+ ptmp = p; /* fill in this bit later */
+ *p++ = 0; /* # of bytes to jump over; don't know how many yet. */
+ }
+
+ /* movq dstGA(a reg), amRIP -- copied from Alu64M MOV case */
+ *p++ = rexAMode_M(i->Ain.XIndir.dstGA, i->Ain.XIndir.amRIP);
+ *p++ = 0x89;
+ p = doAMode_M(p, i->Ain.XIndir.dstGA, i->Ain.XIndir.amRIP);
+
+ /* get $disp_cp_xindir into %r11 */
+ if (fitsIn32Bits(Ptr_to_ULong(disp_cp_xindir))) {
+ /* use a shorter encoding */
+ /* movl sign-extend(disp_cp_xindir), %r11 */
+ *p++ = 0x49;
+ *p++ = 0xC7;
+ *p++ = 0xC3;
+ p = emit32(p, (UInt)Ptr_to_ULong(disp_cp_xindir));
+ } else {
+ /* movabsq $disp_cp_xindir, %r11 */
+ *p++ = 0x49;
+ *p++ = 0xBB;
+ p = emit64(p, Ptr_to_ULong(disp_cp_xindir));
+ }
+
+ /* jmp *%r11 */
+ *p++ = 0x41;
+ *p++ = 0xFF;
+ *p++ = 0xE3;
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->Ain.XIndir.cond != Acc_ALWAYS) {
+ Int delta = p - ptmp;
+ vassert(delta > 0 && delta < 40);
+ *ptmp = toUChar(delta-1);
+ }
+ goto done;
+ }
+
+ case Ain_XAssisted: {
+ /* Use ptmp for backpatching conditional jumps. */
+ ptmp = NULL;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. */
+ if (i->Ain.XAssisted.cond != Acc_ALWAYS) {
+ /* jmp fwds if !condition */
+ *p++ = toUChar(0x70 + (0xF & (i->Ain.XAssisted.cond ^ 1)));
+ ptmp = p; /* fill in this bit later */
+ *p++ = 0; /* # of bytes to jump over; don't know how many yet. */
+ }
+
+ /* movq dstGA(a reg), amRIP -- copied from Alu64M MOV case */
+ *p++ = rexAMode_M(i->Ain.XAssisted.dstGA, i->Ain.XAssisted.amRIP);
+ *p++ = 0x89;
+ p = doAMode_M(p, i->Ain.XAssisted.dstGA, i->Ain.XAssisted.amRIP);
+ /* movl $magic_number, %ebp. Since these numbers are all small positive
+ integers, we can get away with "movl $N, %ebp" rather than
+ the longer "movq $N, %rbp". */
+ UInt trcval = 0;
+ switch (i->Ain.XAssisted.jk) {
+ case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break;
+ case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break;
+ case Ijk_Sys_int32: trcval = VEX_TRC_JMP_SYS_INT32; break;
+ case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break;
+ case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
+ case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
+ case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
+ case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
+ case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
+ case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
+ case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break;
+ /* We don't expect to see the following being assisted. */
+ case Ijk_Ret:
+ case Ijk_Call:
+ /* fallthrough */
+ default:
+ ppIRJumpKind(i->Ain.XAssisted.jk);
+ vpanic("emit_AMD64Instr.Ain_XAssisted: unexpected jump kind");
+ }
+ vassert(trcval != 0);
+ *p++ = 0xBD;
+ p = emit32(p, trcval);
+ /* movabsq $disp_assisted, %r11 */
+ *p++ = 0x49;
+ *p++ = 0xBB;
+ p = emit64(p, Ptr_to_ULong(disp_cp_xassisted));
+ /* jmp *%r11 */
+ *p++ = 0x41;
+ *p++ = 0xFF;
+ *p++ = 0xE3;
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->Ain.XAssisted.cond != Acc_ALWAYS) {
+ Int delta = p - ptmp;
+ vassert(delta > 0 && delta < 40);
*ptmp = toUChar(delta-1);
}
goto done;
@@ -3167,165 +3107,6 @@
}
break;
-//.. case Xin_FpUnary:
-//.. /* gop %src, %dst
-//.. --> ffree %st7 ; fld %st(src) ; fop %st(0) ; fstp %st(1+dst)
-//.. */
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 0+hregNumber(i->Xin.FpUnary.src));
-//.. p = do_fop1_st(p, i->Xin.FpUnary.op);
-//.. p = do_fstp_st(p, 1+hregNumber(i->Xin.FpUnary.dst));
-//.. goto done;
-//..
-//.. case Xin_FpBinary:
-//.. if (i->Xin.FpBinary.op == Xfp_YL2X
-//.. || i->Xin.FpBinary.op == Xfp_YL2XP1) {
-//.. /* Have to do this specially. */
-//.. /* ffree %st7 ; fld %st(srcL) ;
-//.. ffree %st7 ; fld %st(srcR+1) ; fyl2x{p1} ; fstp(1+dst) */
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcL));
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 1+hregNumber(i->Xin.FpBinary.srcR));
-//.. *p++ = 0xD9;
-//.. *p++ = i->Xin.FpBinary.op==Xfp_YL2X ? 0xF1 : 0xF9;
-//.. p = do_fstp_st(p, 1+hregNumber(i->Xin.FpBinary.dst));
-//.. goto done;
-//.. }
-//.. if (i->Xin.FpBinary.op == Xfp_ATAN) {
-//.. /* Have to do this specially. */
-//.. /* ffree %st7 ; fld %st(srcL) ;
-//.. ffree %st7 ; fld %st(srcR+1) ; fpatan ; fstp(1+dst) */
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcL));
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 1+hregNumber(i->Xin.FpBinary.srcR));
-//.. *p++ = 0xD9; *p++ = 0xF3;
-//.. p = do_fstp_st(p, 1+hregNumber(i->Xin.FpBinary.dst));
-//.. goto done;
-//.. }
-//.. if (i->Xin.FpBinary.op == Xfp_PREM
-//.. || i->Xin.FpBinary.op == Xfp_PREM1
-//.. || i->Xin.FpBinary.op == Xfp_SCALE) {
-//.. /* Have to do this specially. */
-//.. /* ffree %st7 ; fld %st(srcR) ;
-//.. ffree %st7 ; fld %st(srcL+1) ; fprem/fprem1/fscale ; fstp(2+dst) ;
-//.. fincstp ; ffree %st7 */
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcR));
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 1+hregNumber(i->Xin.FpBinary.srcL));
-//.. *p++ = 0xD9;
-//.. switch (i->Xin.FpBinary.op) {
-//.. case Xfp_PREM: *p++ = 0xF8; break;
-//.. case Xfp_PREM1: *p++ = 0xF5; break;
-//.. case Xfp_SCALE: *p++ = 0xFD; break;
-//.. default: vpanic("emitAMD64Instr(FpBinary,PREM/PREM1/SCALE)");
-//.. }
-//.. p = do_fstp_st(p, 2+hregNumber(i->Xin.FpBinary.dst));
-//.. *p++ = 0xD9; *p++ = 0xF7;
-//.. p = do_ffree_st7(p);
-//.. goto done;
-//.. }
-//.. /* General case */
-//.. /* gop %srcL, %srcR, %dst
-//.. --> ffree %st7 ; fld %st(srcL) ; fop %st(1+srcR) ; fstp %st(1+dst)
-//.. */
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcL));
-//.. p = do_fop2_st(p, i->Xin.FpBinary.op,
-//.. 1+hregNumber(i->Xin.FpBinary.srcR));
-//.. p = do_fstp_st(p, 1+hregNumber(i->Xin.FpBinary.dst));
-//.. goto done;
-//..
-//.. case Xin_FpLdSt:
-//.. vassert(i->Xin.FpLdSt.sz == 4 || i->Xin.FpLdSt.sz == 8);
-//.. if (i->Xin.FpLdSt.isLoad) {
-//.. /* Load from memory into %fakeN.
-//.. --> ffree %st(7) ; fld{s/l} amode ; fstp st(N+1)
-//.. */
-//.. p = do_ffree_st7(p);
-//.. *p++ = i->Xin.FpLdSt.sz==4 ? 0xD9 : 0xDD;
-//.. p = doAMode_M(p, fake(0)/*subopcode*/, i->Xin.FpLdSt.addr);
-//.. p = do_fstp_st(p, 1+hregNumber(i->Xin.FpLdSt.reg));
-//.. goto done;
-//.. } else {
-//.. /* Store from %fakeN into memory.
-//.. --> ffree %st(7) ; fld st(N) ; fstp{l|s} amode
-//.. */
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 0+hregNumber(i->Xin.FpLdSt.reg));
-//.. *p++ = i->Xin.FpLdSt.sz==4 ? 0xD9 : 0xDD;
-//.. p = doAMode_M(p, fake(3)/*subopcode*/, i->Xin.FpLdSt.addr);
-//.. goto done;
-//.. }
-//.. break;
-//..
-//.. case Xin_FpLdStI:
-//.. if (i->Xin.FpLdStI.isLoad) {
-//.. /* Load from memory into %fakeN, converting from an int.
-//.. --> ffree %st(7) ; fild{w/l/ll} amode ; fstp st(N+1)
-//.. */
-//.. switch (i->Xin.FpLdStI.sz) {
-//.. case 8: opc = 0xDF; subopc_imm = 5; break;
-//.. case 4: opc = 0xDB; subopc_imm = 0; break;
-//.. case 2: vassert(0); opc = 0xDF; subopc_imm = 0; break;
-//.. default: vpanic("emitAMD64Instr(Xin_FpLdStI-load)");
-//.. }
-//.. p = do_ffree_st7(p);
-//.. *p++ = opc;
-//.. p = doAMode_M(p, fake(subopc_imm)/*subopcode*/, i->Xin.FpLdStI.addr);
-//.. p = do_fstp_st(p, 1+hregNumber(i->Xin.FpLdStI.reg));
-//.. goto done;
-//.. } else {
-//.. /* Store from %fakeN into memory, converting to an int.
-//.. --> ffree %st(7) ; fld st(N) ; fistp{w/l/ll} amode
-//.. */
-//.. switch (i->Xin.FpLdStI.sz) {
-//.. case 8: opc = 0xDF; subopc_imm = 7; break;
-//.. case 4: opc = 0xDB; subopc_imm = 3; break;
-//.. case 2: opc = 0xDF; subopc_imm = 3; break;
-//.. default: vpanic("emitAMD64Instr(Xin_FpLdStI-store)");
-//.. }
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 0+hregNumber(i->Xin.FpLdStI.reg));
-//.. *p++ = opc;
-//.. p = doAMode_M(p, fake(subopc_imm)/*subopcode*/, i->Xin.FpLdStI.addr);
-//.. goto done;
-//.. }
-//.. break;
-//..
-//.. case Xin_Fp64to32:
-//.. /* ffree %st7 ; fld %st(src) */
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 0+fregNo(i->Xin.Fp64to32.src));
-//.. /* subl $4, %esp */
-//.. *p++ = 0x83; *p++ = 0xEC; *p++ = 0x04;
-//.. /* fstps (%esp) */
-//.. *p++ = 0xD9; *p++ = 0x1C; *p++ = 0x24;
-//.. /* flds (%esp) */
-//.. *p++ = 0xD9; *p++ = 0x04; *p++ = 0x24;
-//.. /* addl $4, %esp */
-//.. *p++ = 0x83; *p++ = 0xC4; *p++ = 0x04;
-//.. /* fstp %st(1+dst) */
-//.. p = do_fstp_st(p, 1+fregNo(i->Xin.Fp64to32.dst));
-//.. goto done;
-//..
-//.. case Xin_FpCMov:
-//.. /* jmp fwds if !condition */
-//.. *p++ = 0x70 + (i->Xin.FpCMov.cond ^ 1);
-//.. *p++ = 0; /* # of bytes in the next bit, which we don't know yet */
-//.. ptmp = p;
-//..
-//.. /* ffree %st7 ; fld %st(src) ; fstp %st(1+dst) */
-//.. p = do_ffree_st7(p);
-//.. p = do_fld_st(p, 0+fregNo(i->Xin.FpCMov.src));
-//.. p = do_fstp_st(p, 1+fregNo(i->Xin.FpCMov.dst));
-//..
-//.. /* Fill in the jump offset. */
-//.. *(ptmp-1) = p - ptmp;
-//.. goto done;
-
case Ain_LdMXCSR:
*p++ = clearWBit(rexAMode_M( fake(0), i->Ain.LdMXCSR.addr));
*p++ = 0x0F;
@@ -3333,12 +3114,6 @@
p = doAMode_M(p, fake(2)/*subopcode*/, i->Ain.LdMXCSR.addr);
goto done;
-//.. case Xin_FpStSW_AX:
-//.. /* note, this emits fnstsw %ax, not fstsw %ax */
-//.. *p++ = 0xDF;
-//.. *p++ = 0xE0;
-//.. goto done;
-
case Ain_SseUComIS:
/* ucomi[sd] %srcL, %srcR ; pushfq ; popq %dst */
/* ucomi[sd] %srcL, %srcR */
@@ -3398,45 +3173,6 @@
vreg2ireg(i->Ain.SseSDSS.src) );
goto done;
-//..
-//.. case Xin_FpCmp:
-//.. /* gcmp %fL, %fR, %dst
-//.. -> ffree %st7; fpush %fL ; fucomp %(fR+1) ;
-//.. fnstsw %ax ; movl %eax, %dst
-//.. */
-//.. /* ffree %st7 */
-//.. p = do_ffree_st7(p);
-//.. /* fpush %fL */
-//.. p = do_fld_st(p, 0+fregNo(i->Xin.FpCmp.srcL));
-//.. /* fucomp %(fR+1) */
-//.. *p++ = 0xDD;
-//.. *p++ = 0xE8 + (7 & (1+fregNo(i->Xin.FpCmp.srcR)));
-//.. /* fnstsw %ax */
-//.. *p++ = 0xDF;
-//.. *p++ = 0xE0;
-//.. /* movl %eax, %dst */
-//.. *p++ = 0x89;
-//.. p = doAMode_R(p, hregAMD64_EAX(), i->Xin.FpCmp.dst);
-//.. goto done;
-//..
-//.. case Xin_SseConst: {
-//.. UShort con = i->Xin.SseConst.con;
-//.. p = push_word_from_tags(p, (con >> 12) & 0xF);
-//.. p = push_word_from_tags(p, (con >> 8) & 0xF);
-//.. p = push_word_from_tags(p, (con >> 4) & 0xF);
-//.. p = push_word_from_tags(p, con & 0xF);
-//.. /* movl (%esp), %xmm-dst */
-//.. *p++ = 0x0F;
-//.. *p++ = 0x10;
-//.. *p++ = 0x04 + 8 * (7 & vregNo(i->Xin.SseConst.dst));
-//.. *p++ = 0x24;
-//.. /* addl $16, %esp */
-//.. *p++ = 0x83;
-//.. *p++ = 0xC4;
-//.. *p++ = 0x10;
-//.. goto done;
-//.. }
-
case Ain_SseLdSt:
if (i->Ain.SseLdSt.sz == 8) {
*p++ = 0xF2;
@@ -3508,8 +3244,6 @@
case Asse_MAXF: *p++ = 0x5F; break;
case Asse_MINF: *p++ = 0x5D; break;
case Asse_MULF: *p++ = 0x59; break;
-//.. case Xsse_RCPF: *p++ = 0x53; break;
-//.. case Xsse_RSQRTF: *p++ = 0x52; break;
case Asse_SQRTF: *p++ = 0x51; break;
case Asse_SUBF: *p++ = 0x5C; break;
case Asse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break;
@@ -3566,8 +3300,6 @@
case Asse_MAXF: *p++ = 0x5F; break;
case Asse_MINF: *p++ = 0x5D; break;
case Asse_MULF: *p++ = 0x59; break;
-//.. case Xsse_RCPF: *p++ = 0x53; break;
-//.. case Xsse_RSQRTF: *p++ = 0x52; break;
case Asse_SQRTF: *p++ = 0x51; break;
case Asse_SUBF: *p++ = 0x5C; break;
case Asse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break;
@@ -3683,6 +3415,79 @@
*p++ = (UChar)(i->Ain.SseShuf.order);
goto done;
+ //uu case Ain_AvxLdSt: {
+ //uu UInt vex = vexAMode_M( dvreg2ireg(i->Ain.AvxLdSt.reg),
+ //uu i->Ain.AvxLdSt.addr );
+ //uu p = emitVexPrefix(p, vex);
+ //uu *p++ = toUChar(i->Ain.AvxLdSt.isLoad ? 0x10 : 0x11);
+ //uu p = doAMode_M(p, dvreg2ireg(i->Ain.AvxLdSt.reg), i->Ain.AvxLdSt.addr);
+ //uu goto done;
+ //uu }
+
+ case Ain_EvCheck: {
+ /* We generate:
+ (3 bytes) decl 8(%rbp) 8 == offsetof(host_EvC_COUNTER)
+ (2 bytes) jns nofail expected taken
+ (3 bytes) jmp* 0(%rbp) 0 == offsetof(host_EvC_FAILADDR)
+ nofail:
+ */
+ /* This is heavily asserted re instruction lengths. It needs to
+ be. If we get given unexpected forms of .amCounter or
+ .amFailAddr -- basically, anything that's not of the form
+ uimm7(%rbp) -- they are likely to fail. */
+ /* Note also that after the decl we must be very careful not to
+ read the carry flag, else we get a partial flags stall.
+ js/jns avoids that, though. */
+ UChar* p0 = p;
+ /* --- decl 8(%rbp) --- */
+ /* Need to compute the REX byte for the decl in order to prove
+ that we don't need it, since this is a 32-bit inc and all
+ registers involved in the amode are < r8. "fake(1)" because
+ there's no register in this encoding; instead the register
+ field is used as a sub opcode. The encoding for "decl r/m32"
+ is FF /1, hence the fake(1). */
+ rex = clearWBit(rexAMode_M(fake(1), i->Ain.EvCheck.amCounter));
+ if (rex != 0x40) goto bad; /* We don't expect to need the REX byte. */
+ *p++ = 0xFF;
+ p = doAMode_M(p, fake(1), i->Ain.EvCheck.amCounter);
+ vassert(p - p0 == 3);
+ /* --- jns nofail --- */
+ *p++ = 0x79;
+ *p++ = 0x03; /* need to check this 0x03 after the next insn */
+ vassert(p - p0 == 5);
+ /* --- jmp* 0(%rbp) --- */
+ /* Once again, verify we don't need REX. The encoding is FF /4.
+ We don't need REX.W since by default FF /4 in 64-bit mode
+ implies a 64 bit load. */
+ rex = clearWBit(rexAMode_M(fake(4), i->Ain.EvCheck.amFailAddr));
+ if (rex != 0x40) goto bad;
+ *p++ = 0xFF;
+ p = doAMode_M(p, fake(4), i->Ain.EvCheck.amFailAddr);
+ vassert(p - p0 == 8); /* also ensures that 0x03 offset above is ok */
+ /* And crosscheck .. */
+ vassert(evCheckSzB_AMD64() == 8);
+ goto done;
+ }
+
+ case Ain_ProfInc: {
+ /* We generate movabsq $0, %r11
+ incq (%r11)
+ in the expectation that a later call to LibVEX_patchProfCtr
+ will be used to fill in the immediate field once the right
+ value is known.
+ 49 BB 00 00 00 00 00 00 00 00
+ 49 FF 03
+ */
+ *p++ = 0x49; *p++ = 0xBB;
+ *p++ = 0x00; *p++ = 0x00; *p++ = 0x00; *p++ = 0x00;
+ *p++ = 0x00; *p++ = 0x00; *p++ = 0x00; *p++ = 0x00;
+ *p++ = 0x49; *p++ = 0xFF; *p++ = 0x03;
+ /* Tell the caller .. */
+ vassert(!(*is_profInc));
+ *is_profInc = True;
+ goto done;
+ }
+
default:
goto bad;
}
@@ -3699,6 +3504,200 @@
# undef fake
}
+
+/* How big is an event check? See case for Ain_EvCheck in
+ emit_AMD64Instr just above. That crosschecks what this returns, so
+ we can tell if we're inconsistent. */
+Int evCheckSzB_AMD64 ( void )
+{
+ return 8;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange chainXDirect_AMD64 ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to )
+{
+ /* What we're expecting to see is:
+ movabsq $disp_cp_chain_me_EXPECTED, %r11
+ call *%r11
+ viz
+ 49 BB <8 bytes value == disp_cp_chain_me_EXPECTED>
+ 41 FF D3
+ */
+ UChar* p = (UChar*)place_to_chain;
+ vassert(p[0] == 0x49);
+ vassert(p[1] == 0xBB);
+ vassert(*(ULong*)(&p[2]) == Ptr_to_ULong(disp_cp_chain_me_EXPECTED));
+ vassert(p[10] == 0x41);
+ vassert(p[11] == 0xFF);
+ vassert(p[12] == 0xD3);
+ /* And what we want to change it to is either:
+ (general case):
+ movabsq $place_to_jump_to, %r11
+ jmpq *%r11
+ viz
+ 49 BB <8 bytes value == place_to_jump_to>
+ 41 FF E3
+ So it's the same length (convenient, huh) and we don't
+ need to change all the bits.
+ ---OR---
+ in the case where the displacement falls within 32 bits
+ jmpq disp32 where disp32 is relative to the next insn
+ ud2; ud2; ud2; ud2
+ viz
+ E9 <4 bytes == disp32>
+ 0F 0B 0F 0B 0F 0B 0F 0B
+
+ In both cases the replacement has the same length as the original.
+ To remain sane & verifiable,
+ (1) limit the displacement for the short form to
+ (say) +/- one billion, so as to avoid wraparound
+ off-by-ones
+ (2) even if the short form is applicable, once every (say)
+ 1024 times use the long form anyway, so as to maintain
+ verifiability
+ */
+ /* This is the delta we need to put into a JMP d32 insn. It's
+ relative to the start of the next insn, hence the -5. */
+ Long delta = (Long)((UChar*)place_to_jump_to - (UChar*)p) - (Long)5;
+ Bool shortOK = delta >= -1000*1000*1000 && delta < 1000*1000*1000;
+
+ static UInt shortCTR = 0; /* DO NOT MAKE NON-STATIC */
+ if (shortOK) {
+ shortCTR++; // thread safety bleh
+ if (0 == (shortCTR & 0x3FF)) {
+ shortOK = False;
+ if (0)
+ vex_printf("QQQ chainXDirect_AMD64: shortCTR = %u, "
+ "using long jmp\n", shortCTR);
+ }
+ }
+
+ /* And make the modifications. */
+ if (shortOK) {
+ p[0] = 0xE9;
+ p[1] = (delta >> 0) & 0xFF;
+ p[2] = (delta >> 8) & 0xFF;
+ p[3] = (delta >> 16) & 0xFF;
+ p[4] = (delta >> 24) & 0xFF;
+ p[5] = 0x0F; p[6] = 0x0B;
+ p[7] = 0x0F; p[8] = 0x0B;
+ p[9] = 0x0F; p[10] = 0x0B;
+ p[11] = 0x0F; p[12] = 0x0B;
+ /* sanity check on the delta -- top 32 are all 0 or all 1 */
+ delta >>= 32;
+ vassert(delta == 0LL || delta == -1LL);
+ } else {
+ /* Minimal modifications from the starting sequence. */
+ *(ULong*)(&p[2]) = Ptr_to_ULong(place_to_jump_to);
+ p[12] = 0xE3;
+ }
+ VexInvalRange vir = {0, 0};
+ return vir;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange unchainXDirect_AMD64 ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me )
+{
+ /* What we're expecting to see is either:
+ (general case)
+ movabsq $place_to_jump_to_EXPECTED, %r11
+ jmpq *%r11
+ viz
+ 49 BB <8 bytes value == place_to_jump_to_EXPECTED>
+ 41 FF E3
+ ---OR---
+ in the case where the displacement falls within 32 bits
+ jmpq d32
+ ud2; ud2; ud2; ud2
+ viz
+ E9 <4 bytes == disp32>
+ 0F 0B 0F 0B 0F 0B 0F 0B
+ */
+ UChar* p = (UChar*)place_to_unchain;
+ Bool valid = False;
+ if (p[0] == 0x49 && p[1] == 0xBB
+ && *(ULong*)(&p[2]) == Ptr_to_ULong(place_to_jump_to_EXPECTED)
+ && p[10] == 0x41 && p[11] == 0xFF && p[12] == 0xE3) {
+ /* it's the long form */
+ valid = True;
+ }
+ else
+ if (p[0] == 0xE9
+ && p[5] == 0x0F && p[6] == 0x0B
+ && p[7] == 0x0F && p[8] == 0x0B
+ && p[9] == 0x0F && p[10] == 0x0B
+ && p[11] == 0x0F && p[12] == 0x0B) {
+ /* It's the short form. Check the offset is right. */
+ Int s32 = *(Int*)(&p[1]);
+ Long s64 = (Long)s32;
+ if ((UChar*)p + 5 + s64 == (UChar*)place_to_jump_to_EXPECTED) {
+ valid = True;
+ if (0)
+ vex_printf("QQQ unchainXDirect_AMD64: found short form\n");
+ }
+ }
+ vassert(valid);
+ /* And what we want to change it to is:
+ movabsq $disp_cp_chain_me, %r11
+ call *%r11
+ viz
+ 49 BB <8 bytes value == disp_cp_chain_me>
+ 41 FF D3
+ So it's the same length (convenient, huh).
+ */
+ p[0] = 0x49;
+ p[1] = 0xBB;
+ *(ULong*)(&p[2]) = Ptr_to_ULong(disp_cp_chain_me);
+ p[10] = 0x41;
+ p[11] = 0xFF;
+ p[12] = 0xD3;
+ VexInvalRange vir = {0, 0};
+ return vir;
+}
+
+
+/* Patch the counter address into a profile inc point, as previously
+ created by the Ain_ProfInc case for emit_AMD64Instr. */
+VexInvalRange patchProfInc_AMD64 ( void* place_to_patch,
+ ULong* location_of_counter )
+{
+ vassert(sizeof(ULong*) == 8);
+ UChar* p = (UChar*)place_to_patch;
+ vassert(p[0] == 0x49);
+ vassert(p[1] == 0xBB);
+ vassert(p[2] == 0x00);
+ vassert(p[3] == 0x00);
+ vassert(p[4] == 0x00);
+ vassert(p[5] == 0x00);
+ vassert(p[6] == 0x00);
+ vassert(p[7] == 0x00);
+ vassert(p[8] == 0x00);
+ vassert(p[9] == 0x00);
+ vassert(p[10] == 0x49);
+ vassert(p[11] == 0xFF);
+ vassert(p[12] == 0x03);
+ ULong imm64 = (ULong)Ptr_to_ULong(location_of_counter);
+ p[2] = imm64 & 0xFF; imm64 >>= 8;
+ p[3] = imm64 & 0xFF; imm64 >>= 8;
+ p[4] = imm64 & 0xFF; imm64 >>= 8;
+ p[5] = imm64 & 0xFF; imm64 >>= 8;
+ p[6] = imm64 & 0xFF; imm64 >>= 8;
+ p[7] = imm64 & 0xFF; imm64 >>= 8;
+ p[8] = imm64 & 0xFF; imm64 >>= 8;
+ p[9] = imm64 & 0xFF; imm64 >>= 8;
+ VexInvalRange vir = {0, 0};
+ return vir;
+}
+
+
/*---------------------------------------------------------------*/
/*--- end host_amd64_defs.c ---*/
/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/host_amd64_defs.h b/main/VEX/priv/host_amd64_defs.h
index 4e7ae05..ad13cfa 100644
--- a/main/VEX/priv/host_amd64_defs.h
+++ b/main/VEX/priv/host_amd64_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -71,7 +71,6 @@
extern HReg hregAMD64_XMM0 ( void );
extern HReg hregAMD64_XMM1 ( void );
-extern HReg hregAMD64_XMM2 ( void );
extern HReg hregAMD64_XMM3 ( void );
extern HReg hregAMD64_XMM4 ( void );
extern HReg hregAMD64_XMM5 ( void );
@@ -82,9 +81,6 @@
extern HReg hregAMD64_XMM10 ( void );
extern HReg hregAMD64_XMM11 ( void );
extern HReg hregAMD64_XMM12 ( void );
-extern HReg hregAMD64_XMM13 ( void );
-extern HReg hregAMD64_XMM14 ( void );
-extern HReg hregAMD64_XMM15 ( void );
/* --------- Condition codes, AMD encoding. --------- */
@@ -363,10 +359,11 @@
Ain_Alu32R, /* 32-bit add/sub/and/or/xor/cmp, dst=REG (a la Alu64R) */
Ain_MulL, /* widening multiply */
Ain_Div, /* div and mod */
-//.. Xin_Sh3232, /* shldl or shrdl */
Ain_Push, /* push 64-bit value on stack */
Ain_Call, /* call to address in register */
- Ain_Goto, /* conditional/unconditional jmp to dst */
+ Ain_XDirect, /* direct transfer to GA */
+ Ain_XIndir, /* indirect transfer to GA */
+ Ain_XAssisted, /* assisted transfer to GA */
Ain_CMov64, /* conditional move */
Ain_MovxLQ, /* reg-reg move, zx-ing/sx-ing top half */
Ain_LoadEX, /* mov{s,z}{b,w,l}q from mem to reg */
@@ -377,28 +374,17 @@
Ain_ACAS, /* 8/16/32/64-bit lock;cmpxchg */
Ain_DACAS, /* lock;cmpxchg8b/16b (doubleword ACAS, 2 x
32-bit or 2 x 64-bit only) */
-
Ain_A87Free, /* free up x87 registers */
Ain_A87PushPop, /* x87 loads/stores */
Ain_A87FpOp, /* x87 operations */
Ain_A87LdCW, /* load x87 control word */
Ain_A87StSW, /* store x87 status word */
-//..
-//.. Xin_FpUnary, /* FP fake unary op */
-//.. Xin_FpBinary, /* FP fake binary op */
-//.. Xin_FpLdSt, /* FP fake load/store */
-//.. Xin_FpLdStI, /* FP fake load/store, converting to/from Int */
-//.. Xin_Fp64to32, /* FP round IEEE754 double to IEEE754 single */
-//.. Xin_FpCMov, /* FP fake floating point conditional move */
Ain_LdMXCSR, /* load %mxcsr */
-//.. Xin_FpStSW_AX, /* fstsw %ax */
Ain_SseUComIS, /* ucomisd/ucomiss, then get %rflags into int
register */
Ain_SseSI2SF, /* scalar 32/64 int to 32/64 float conversion */
Ain_SseSF2SI, /* scalar 32/64 float to 32/64 int conversion */
Ain_SseSDSS, /* scalar float32 to/from float64 */
-//..
-//.. Xin_SseConst, /* Generate restricted SSE literal */
Ain_SseLdSt, /* SSE load/store 32/64/128 bits, no alignment
constraints, upper 96/64/0 bits arbitrary */
Ain_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg */
@@ -408,7 +394,12 @@
Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */
Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */
Ain_SseCMov, /* SSE conditional move */
- Ain_SseShuf /* SSE2 shuffle (pshufd) */
+ Ain_SseShuf, /* SSE2 shuffle (pshufd) */
+ //uu Ain_AvxLdSt, /* AVX load/store 256 bits,
+ //uu no alignment constraints */
+ //uu Ain_AvxReRg, /* AVX binary general reg-reg, Re, Rg */
+ Ain_EvCheck, /* Event check */
+ Ain_ProfInc /* 64-bit profile counter increment */
}
AMD64InstrTag;
@@ -470,13 +461,6 @@
Int sz; /* 4 or 8 only */
AMD64RM* src;
} Div;
-//.. /* shld/shrd. op may only be Xsh_SHL or Xsh_SHR */
-//.. struct {
-//.. X86ShiftOp op;
-//.. UInt amt; /* shift amount, or 0 means %cl */
-//.. HReg src;
-//.. HReg dst;
-//.. } Sh3232;
struct {
AMD64RMI* src;
} Push;
@@ -487,13 +471,29 @@
Addr64 target;
Int regparms; /* 0 .. 6 */
} Call;
- /* Pseudo-insn. Goto dst, on given condition (which could be
- Acc_ALWAYS). */
+ /* Update the guest RIP value, then exit requesting to chain
+ to it. May be conditional. */
struct {
+ Addr64 dstGA; /* next guest address */
+ AMD64AMode* amRIP; /* amode in guest state for RIP */
+ AMD64CondCode cond; /* can be Acc_ALWAYS */
+ Bool toFastEP; /* chain to the slow or fast point? */
+ } XDirect;
+ /* Boring transfer to a guest address not known at JIT time.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ AMD64AMode* amRIP;
+ AMD64CondCode cond; /* can be Acc_ALWAYS */
+ } XIndir;
+ /* Assisted transfer to a guest address, most general case.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ AMD64AMode* amRIP;
+ AMD64CondCode cond; /* can be Acc_ALWAYS */
IRJumpKind jk;
- AMD64CondCode cond;
- AMD64RI* dst;
- } Goto;
+ } XAssisted;
/* Mov src to dst on the given condition, which may not
be the bogus Acc_ALWAYS. */
struct {
@@ -588,11 +588,6 @@
AMD64AMode* addr;
}
LdMXCSR;
-//.. /* fstsw %ax */
-//.. struct {
-//.. /* no fields */
-//.. }
-//.. FpStSW_AX;
/* ucomisd/ucomiss, then get %rflags into int register */
struct {
UChar sz; /* 4 or 8 only */
@@ -620,12 +615,6 @@
HReg src;
HReg dst;
} SseSDSS;
-//..
-//.. /* Simplistic SSE[123] */
-//.. struct {
-//.. UShort con;
-//.. HReg dst;
-//.. } SseConst;
struct {
Bool isLoad;
UChar sz; /* 4, 8 or 16 only */
@@ -674,6 +663,25 @@
HReg src;
HReg dst;
} SseShuf;
+ //uu struct {
+ //uu Bool isLoad;
+ //uu HReg reg;
+ //uu AMD64AMode* addr;
+ //uu } AvxLdSt;
+ //uu struct {
+ //uu AMD64SseOp op;
+ //uu HReg src;
+ //uu HReg dst;
+ //uu } AvxReRg;
+ struct {
+ AMD64AMode* amCounter;
+ AMD64AMode* amFailAddr;
+ } EvCheck;
+ struct {
+ /* No fields. The address of the counter to inc is
+ installed later, post-translation, by patching it in,
+ as it is not known at translation time. */
+ } ProfInc;
} Ain;
}
@@ -689,10 +697,14 @@
extern AMD64Instr* AMD64Instr_Test64 ( UInt imm32, HReg dst );
extern AMD64Instr* AMD64Instr_MulL ( Bool syned, AMD64RM* );
extern AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* );
-//.. extern AMD64Instr* AMD64Instr_Sh3232 ( AMD64ShiftOp, UInt amt, HReg src, HReg dst );
extern AMD64Instr* AMD64Instr_Push ( AMD64RMI* );
extern AMD64Instr* AMD64Instr_Call ( AMD64CondCode, Addr64, Int );
-extern AMD64Instr* AMD64Instr_Goto ( IRJumpKind, AMD64CondCode cond, AMD64RI* dst );
+extern AMD64Instr* AMD64Instr_XDirect ( Addr64 dstGA, AMD64AMode* amRIP,
+ AMD64CondCode cond, Bool toFastEP );
+extern AMD64Instr* AMD64Instr_XIndir ( HReg dstGA, AMD64AMode* amRIP,
+ AMD64CondCode cond );
+extern AMD64Instr* AMD64Instr_XAssisted ( HReg dstGA, AMD64AMode* amRIP,
+ AMD64CondCode cond, IRJumpKind jk );
extern AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode, AMD64RM* src, HReg dst );
extern AMD64Instr* AMD64Instr_MovxLQ ( Bool syned, HReg src, HReg dst );
extern AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned,
@@ -709,21 +721,11 @@
extern AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op );
extern AMD64Instr* AMD64Instr_A87LdCW ( AMD64AMode* addr );
extern AMD64Instr* AMD64Instr_A87StSW ( AMD64AMode* addr );
-//..
-//.. extern AMD64Instr* AMD64Instr_FpUnary ( AMD64FpOp op, HReg src, HReg dst );
-//.. extern AMD64Instr* AMD64Instr_FpBinary ( AMD64FpOp op, HReg srcL, HReg srcR, HReg dst );
-//.. extern AMD64Instr* AMD64Instr_FpLdSt ( Bool isLoad, UChar sz, HReg reg, AMD64AMode* );
-//.. extern AMD64Instr* AMD64Instr_FpLdStI ( Bool isLoad, UChar sz, HReg reg, AMD64AMode* );
-//.. extern AMD64Instr* AMD64Instr_Fp64to32 ( HReg src, HReg dst );
-//.. extern AMD64Instr* AMD64Instr_FpCMov ( AMD64CondCode, HReg src, HReg dst );
extern AMD64Instr* AMD64Instr_LdMXCSR ( AMD64AMode* );
-//.. extern AMD64Instr* AMD64Instr_FpStSW_AX ( void );
extern AMD64Instr* AMD64Instr_SseUComIS ( Int sz, HReg srcL, HReg srcR, HReg dst );
extern AMD64Instr* AMD64Instr_SseSI2SF ( Int szS, Int szD, HReg src, HReg dst );
extern AMD64Instr* AMD64Instr_SseSF2SI ( Int szS, Int szD, HReg src, HReg dst );
extern AMD64Instr* AMD64Instr_SseSDSS ( Bool from64, HReg src, HReg dst );
-//..
-//.. extern AMD64Instr* AMD64Instr_SseConst ( UShort con, HReg dst );
extern AMD64Instr* AMD64Instr_SseLdSt ( Bool isLoad, Int sz, HReg, AMD64AMode* );
extern AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg, AMD64AMode* );
extern AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp, HReg, HReg );
@@ -733,6 +735,11 @@
extern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg );
extern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg dst );
extern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst );
+//uu extern AMD64Instr* AMD64Instr_AvxLdSt ( Bool isLoad, HReg, AMD64AMode* );
+//uu extern AMD64Instr* AMD64Instr_AvxReRg ( AMD64SseOp, HReg, HReg );
+extern AMD64Instr* AMD64Instr_EvCheck ( AMD64AMode* amCounter,
+ AMD64AMode* amFailAddr );
+extern AMD64Instr* AMD64Instr_ProfInc ( void );
extern void ppAMD64Instr ( AMD64Instr*, Bool );
@@ -742,10 +749,13 @@
extern void getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr*, Bool );
extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool );
extern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* );
-extern Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr*,
- Bool,
- void* dispatch_unassisted,
- void* dispatch_assisted );
+extern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, AMD64Instr* i,
+ Bool mode64,
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted );
extern void genSpill_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
HReg rreg, Int offset, Bool );
@@ -753,9 +763,36 @@
HReg rreg, Int offset, Bool );
extern void getAllocableRegs_AMD64 ( Int*, HReg** );
-extern HInstrArray* iselSB_AMD64 ( IRSB*, VexArch,
- VexArchInfo*,
- VexAbiInfo* );
+extern HInstrArray* iselSB_AMD64 ( IRSB*,
+ VexArch,
+ VexArchInfo*,
+ VexAbiInfo*,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga );
+
+/* How big is an event check? This is kind of a kludge because it
+ depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER,
+ and so assumes that they are both <= 128, and so can use the short
+ offset encoding. This is all checked with assertions, so in the
+ worst case we will merely assert at startup. */
+extern Int evCheckSzB_AMD64 ( void );
+
+/* Perform a chaining and unchaining of an XDirect jump. */
+extern VexInvalRange chainXDirect_AMD64 ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to );
+
+extern VexInvalRange unchainXDirect_AMD64 ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me );
+
+/* Patch the counter location into an existing ProfInc point. */
+extern VexInvalRange patchProfInc_AMD64 ( void* place_to_patch,
+ ULong* location_of_counter );
+
#endif /* ndef __VEX_HOST_AMD64_DEFS_H */
diff --git a/main/VEX/priv/host_amd64_isel.c b/main/VEX/priv/host_amd64_isel.c
index bcd213f..1296390 100644
--- a/main/VEX/priv/host_amd64_isel.c
+++ b/main/VEX/priv/host_amd64_isel.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -112,12 +112,24 @@
64-bit virtual HReg, which holds the high half
of the value.
+ - The host subarchitecture we are selecting insns for.
+ This is set at the start and does not change.
+
- The code array, that is, the insns selected so far.
- A counter, for generating new virtual registers.
- - The host subarchitecture we are selecting insns for.
- This is set at the start and does not change.
+ - A Bool for indicating whether we may generate chain-me
+ instructions for control flow transfers, or whether we must use
+ XAssisted.
+
+ - The maximum guest address of any guest insn in this block.
+ Actually, the address of the highest-addressed byte from any insn
+ in this block. Is set at the start and does not change. This is
+ used for detecting jumps which are definitely forward-edges from
+ this block, and therefore can be made (chained) to the fast entry
+ point of the destination, thereby avoiding the destination's
+ event check.
Note, this is all host-independent. (JRS 20050201: well, kinda
... not completely. Compare with ISelEnv for X86.)
@@ -125,17 +137,21 @@
typedef
struct {
+ /* Constant -- are set at the start and do not change. */
IRTypeEnv* type_env;
HReg* vregmap;
HReg* vregmapHI;
Int n_vregmap;
- HInstrArray* code;
-
- Int vreg_ctr;
-
UInt hwcaps;
+
+ Bool chainingAllowed;
+ Addr64 max_ga;
+
+ /* These are modified as we go along. */
+ HInstrArray* code;
+ Int vreg_ctr;
}
ISelEnv;
@@ -147,8 +163,8 @@
return env->vregmap[tmp];
}
-static void lookupIRTemp128 ( HReg* vrHI, HReg* vrLO,
- ISelEnv* env, IRTemp tmp )
+static void lookupIRTempPair ( HReg* vrHI, HReg* vrLO,
+ ISelEnv* env, IRTemp tmp )
{
vassert(tmp >= 0);
vassert(tmp < env->n_vregmap);
@@ -173,13 +189,6 @@
return reg;
}
-//.. static HReg newVRegF ( ISelEnv* env )
-//.. {
-//.. HReg reg = mkHReg(env->vreg_ctr, HRcFlt64, True/*virtual reg*/);
-//.. env->vreg_ctr++;
-//.. return reg;
-//.. }
-
static HReg newVRegV ( ISelEnv* env )
{
HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/);
@@ -213,9 +222,9 @@
static AMD64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e );
static AMD64AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e );
-static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo,
+static void iselInt128Expr_wrk ( /*OUT*/HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e );
-static void iselInt128Expr ( HReg* rHi, HReg* rLo,
+static void iselInt128Expr ( /*OUT*/HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e );
static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e );
@@ -230,6 +239,11 @@
static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
+static void iselDVecExpr_wrk ( /*OUT*/HReg* rHi, HReg* rLo,
+ ISelEnv* env, IRExpr* e );
+static void iselDVecExpr ( /*OUT*/HReg* rHi, HReg* rLo,
+ ISelEnv* env, IRExpr* e );
+
/*---------------------------------------------------------*/
/*--- ISEL: Misc helpers ---*/
@@ -292,7 +306,7 @@
return AMD64Instr_Alu64R(Aalu_MOV, AMD64RMI_Reg(src), dst);
}
-/* Make a vector reg-reg move. */
+/* Make a vector (128 bit) reg-reg move. */
static AMD64Instr* mk_vMOVsd_RR ( HReg src, HReg dst )
{
@@ -334,46 +348,6 @@
}
}
-//.. /* Given an amode, return one which references 4 bytes further
-//.. along. */
-//..
-//.. static X86AMode* advance4 ( X86AMode* am )
-//.. {
-//.. X86AMode* am4 = dopyX86AMode(am);
-//.. switch (am4->tag) {
-//.. case Xam_IRRS:
-//.. am4->Xam.IRRS.imm += 4; break;
-//.. case Xam_IR:
-//.. am4->Xam.IR.imm += 4; break;
-//.. default:
-//.. vpanic("advance4(x86,host)");
-//.. }
-//.. return am4;
-//.. }
-//..
-//..
-//.. /* Push an arg onto the host stack, in preparation for a call to a
-//.. helper function of some kind. Returns the number of 32-bit words
-//.. pushed. */
-//..
-//.. static Int pushArg ( ISelEnv* env, IRExpr* arg )
-//.. {
-//.. IRType arg_ty = typeOfIRExpr(env->type_env, arg);
-//.. if (arg_ty == Ity_I32) {
-//.. addInstr(env, X86Instr_Push(iselIntExpr_RMI(env, arg)));
-//.. return 1;
-//.. } else
-//.. if (arg_ty == Ity_I64) {
-//.. HReg rHi, rLo;
-//.. iselInt64Expr(&rHi, &rLo, env, arg);
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(rHi)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(rLo)));
-//.. return 2;
-//.. }
-//.. ppIRExpr(arg);
-//.. vpanic("pushArg(x86): can't handle arg of this type");
-//.. }
-
/* Used only in doHelperCall. If possible, produce a single
instruction which computes 'e' into 'dst'. If not possible, return
@@ -563,11 +537,11 @@
/* SLOW SCHEME; move via temporaries */
slowscheme:
-#if 0
-if (n_args > 0) {for (i = 0; args[i]; i++) {
-ppIRExpr(args[i]); vex_printf(" "); }
-vex_printf("\n");}
-#endif
+# if 0 /* debug only */
+ if (n_args > 0) {for (i = 0; args[i]; i++) {
+ ppIRExpr(args[i]); vex_printf(" "); }
+ vex_printf("\n");}
+# endif
argreg = 0;
if (passBBP) {
@@ -803,23 +777,6 @@
}
-//.. /* Round an x87 FPU value to 53-bit-mantissa precision, to be used
-//.. after most non-simple FPU operations (simple = +, -, *, / and
-//.. sqrt).
-//..
-//.. This could be done a lot more efficiently if needed, by loading
-//.. zero and adding it to the value to be rounded (fldz ; faddp?).
-//.. */
-//.. static void roundToF64 ( ISelEnv* env, HReg reg )
-//.. {
-//.. X86AMode* zero_esp = X86AMode_IR(0, hregX86_ESP());
-//.. sub_from_esp(env, 8);
-//.. addInstr(env, X86Instr_FpLdSt(False/*store*/, 8, reg, zero_esp));
-//.. addInstr(env, X86Instr_FpLdSt(True/*load*/, 8, reg, zero_esp));
-//.. add_to_esp(env, 8);
-//.. }
-
-
/*---------------------------------------------------------*/
/*--- ISEL: Integer expressions (64/32/16/8 bit) ---*/
/*---------------------------------------------------------*/
@@ -1309,68 +1266,6 @@
return dst;
}
-//.. if (e->Iex.Binop.op == Iop_F64toI32 || e->Iex.Binop.op == Iop_F64toI16) {
-//.. Int sz = e->Iex.Binop.op == Iop_F64toI16 ? 2 : 4;
-//.. HReg rf = iselDblExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst = newVRegI(env);
-//..
-//.. /* Used several times ... */
-//.. X86AMode* zero_esp = X86AMode_IR(0, hregX86_ESP());
-//..
-//.. /* rf now holds the value to be converted, and rrm holds the
-//.. rounding mode value, encoded as per the IRRoundingMode
-//.. enum. The first thing to do is set the FPU's rounding
-//.. mode accordingly. */
-//..
-//.. /* Create a space for the format conversion. */
-//.. /* subl $4, %esp */
-//.. sub_from_esp(env, 4);
-//..
-//.. /* Set host rounding mode */
-//.. set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
-//..
-//.. /* gistw/l %rf, 0(%esp) */
-//.. addInstr(env, X86Instr_FpLdStI(False/*store*/, sz, rf, zero_esp));
-//..
-//.. if (sz == 2) {
-//.. /* movzwl 0(%esp), %dst */
-//.. addInstr(env, X86Instr_LoadEX(2,False,zero_esp,dst));
-//.. } else {
-//.. /* movl 0(%esp), %dst */
-//.. vassert(sz == 4);
-//.. addInstr(env, X86Instr_Alu32R(
-//.. Xalu_MOV, X86RMI_Mem(zero_esp), dst));
-//.. }
-//..
-//.. /* Restore default FPU rounding. */
-//.. set_FPU_rounding_default( env );
-//..
-//.. /* addl $4, %esp */
-//.. add_to_esp(env, 4);
-//.. return dst;
-//.. }
-//..
-//.. /* C3210 flags following FPU partial remainder (fprem), both
-//.. IEEE compliant (PREM1) and non-IEEE compliant (PREM). */
-//.. if (e->Iex.Binop.op == Iop_PRemC3210F64
-//.. || e->Iex.Binop.op == Iop_PRem1C3210F64) {
-//.. HReg junk = newVRegF(env);
-//.. HReg dst = newVRegI(env);
-//.. HReg srcL = iselDblExpr(env, e->Iex.Binop.arg1);
-//.. HReg srcR = iselDblExpr(env, e->Iex.Binop.arg2);
-//.. addInstr(env, X86Instr_FpBinary(
-//.. e->Iex.Binop.op==Iop_PRemC3210F64
-//.. ? Xfp_PREM : Xfp_PREM1,
-//.. srcL,srcR,junk
-//.. ));
-//.. /* The previous pseudo-insn will have left the FPU's C3210
-//.. flags set correctly. So bag them. */
-//.. addInstr(env, X86Instr_FpStSW_AX());
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), dst));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0x4700), dst));
-//.. return dst;
-//.. }
-
break;
}
@@ -1507,16 +1402,6 @@
addInstr(env, AMD64Instr_Unary64(Aun_NOT,dst));
return dst;
}
-//.. case Iop_64HIto32: {
-//.. HReg rHi, rLo;
-//.. iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
-//.. return rHi; /* and abandon rLo .. poor wee thing :-) */
-//.. }
-//.. case Iop_64to32: {
-//.. HReg rHi, rLo;
-//.. iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
-//.. return rLo; /* similar stupid comment to the above ... */
-//.. }
case Iop_16HIto8:
case Iop_32HIto16:
case Iop_64HIto32: {
@@ -1624,16 +1509,42 @@
/* V128{HI}to64 */
case Iop_V128HIto64:
case Iop_V128to64: {
- Int off = e->Iex.Unop.op==Iop_V128HIto64 ? 8 : 0;
HReg dst = newVRegI(env);
+ Int off = e->Iex.Unop.op==Iop_V128HIto64 ? -8 : -16;
+ HReg rsp = hregAMD64_RSP();
HReg vec = iselVecExpr(env, e->Iex.Unop.arg);
- AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP());
- AMD64AMode* rspN = AMD64AMode_IR(off, hregAMD64_RSP());
- sub_from_rsp(env, 16);
- addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vec, rsp0));
+ AMD64AMode* m16_rsp = AMD64AMode_IR(-16, rsp);
+ AMD64AMode* off_rsp = AMD64AMode_IR(off, rsp);
+ addInstr(env, AMD64Instr_SseLdSt(False/*store*/,
+ 16, vec, m16_rsp));
addInstr(env, AMD64Instr_Alu64R( Aalu_MOV,
- AMD64RMI_Mem(rspN), dst ));
- add_to_rsp(env, 16);
+ AMD64RMI_Mem(off_rsp), dst ));
+ return dst;
+ }
+
+ case Iop_V256to64_0: case Iop_V256to64_1:
+ case Iop_V256to64_2: case Iop_V256to64_3: {
+ HReg vHi, vLo, vec;
+ iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
+ /* Do the first part of the selection by deciding which of
+ the 128 bit registers do look at, and second part using
+ the same scheme as for V128{HI}to64 above. */
+ Int off = 0;
+ switch (e->Iex.Unop.op) {
+ case Iop_V256to64_0: vec = vLo; off = -16; break;
+ case Iop_V256to64_1: vec = vLo; off = -8; break;
+ case Iop_V256to64_2: vec = vHi; off = -16; break;
+ case Iop_V256to64_3: vec = vHi; off = -8; break;
+ default: vassert(0);
+ }
+ HReg dst = newVRegI(env);
+ HReg rsp = hregAMD64_RSP();
+ AMD64AMode* m16_rsp = AMD64AMode_IR(-16, rsp);
+ AMD64AMode* off_rsp = AMD64AMode_IR(off, rsp);
+ addInstr(env, AMD64Instr_SseLdSt(False/*store*/,
+ 16, vec, m16_rsp));
+ addInstr(env, AMD64Instr_Alu64R( Aalu_MOV,
+ AMD64RMI_Mem(off_rsp), dst ));
return dst;
}
@@ -1804,13 +1715,14 @@
/* --------- TERNARY OP --------- */
case Iex_Triop: {
+ IRTriop *triop = e->Iex.Triop.details;
/* C3210 flags following FPU partial remainder (fprem), both
IEEE compliant (PREM1) and non-IEEE compliant (PREM). */
- if (e->Iex.Triop.op == Iop_PRemC3210F64
- || e->Iex.Triop.op == Iop_PRem1C3210F64) {
+ if (triop->op == Iop_PRemC3210F64
+ || triop->op == Iop_PRem1C3210F64) {
AMD64AMode* m8_rsp = AMD64AMode_IR(-8, hregAMD64_RSP());
- HReg arg1 = iselDblExpr(env, e->Iex.Triop.arg2);
- HReg arg2 = iselDblExpr(env, e->Iex.Triop.arg3);
+ HReg arg1 = iselDblExpr(env, triop->arg2);
+ HReg arg2 = iselDblExpr(env, triop->arg3);
HReg dst = newVRegI(env);
addInstr(env, AMD64Instr_A87Free(2));
@@ -1822,7 +1734,7 @@
addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg1, m8_rsp));
addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
- switch (e->Iex.Triop.op) {
+ switch (triop->op) {
case Iop_PRemC3210F64:
addInstr(env, AMD64Instr_A87FpOp(Afp_PREM));
break;
@@ -2176,6 +2088,15 @@
return Acc_NZ;
}
+ /* --- patterns rooted at: 32to1 --- */
+
+ /* 32to1 */
+ if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_32to1) {
+ HReg reg = iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, AMD64Instr_Test64(1,reg));
+ return Acc_NZ;
+ }
+
/* --- patterns rooted at: CmpNEZ8 --- */
/* CmpNEZ8(x) */
@@ -2372,95 +2293,15 @@
static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
{
-//.. HWord fn = 0; /* helper fn for most SIMD64 stuff */
vassert(e);
vassert(typeOfIRExpr(env->type_env,e) == Ity_I128);
-//.. /* 64-bit literal */
-//.. if (e->tag == Iex_Const) {
-//.. ULong w64 = e->Iex.Const.con->Ico.U64;
-//.. UInt wHi = ((UInt)(w64 >> 32)) & 0xFFFFFFFF;
-//.. UInt wLo = ((UInt)w64) & 0xFFFFFFFF;
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. vassert(e->Iex.Const.con->tag == Ico_U64);
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(wHi), tHi));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(wLo), tLo));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-
/* read 128-bit IRTemp */
if (e->tag == Iex_RdTmp) {
- lookupIRTemp128( rHi, rLo, env, e->Iex.RdTmp.tmp);
+ lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp);
return;
}
-//.. /* 64-bit load */
-//.. if (e->tag == Iex_LDle) {
-//.. HReg tLo, tHi;
-//.. X86AMode *am0, *am4;
-//.. vassert(e->Iex.LDle.ty == Ity_I64);
-//.. tLo = newVRegI(env);
-//.. tHi = newVRegI(env);
-//.. am0 = iselIntExpr_AMode(env, e->Iex.LDle.addr);
-//.. am4 = advance4(am0);
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am0), tLo ));
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am4), tHi ));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. /* 64-bit GET */
-//.. if (e->tag == Iex_Get) {
-//.. X86AMode* am = X86AMode_IR(e->Iex.Get.offset, hregX86_EBP());
-//.. X86AMode* am4 = advance4(am);
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am), tLo ));
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am4), tHi ));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. /* 64-bit GETI */
-//.. if (e->tag == Iex_GetI) {
-//.. X86AMode* am
-//.. = genGuestArrayOffset( env, e->Iex.GetI.descr,
-//.. e->Iex.GetI.ix, e->Iex.GetI.bias );
-//.. X86AMode* am4 = advance4(am);
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am), tLo ));
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am4), tHi ));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. /* 64-bit Mux0X */
-//.. if (e->tag == Iex_Mux0X) {
-//.. HReg e0Lo, e0Hi, eXLo, eXHi, r8;
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. iselInt64Expr(&e0Hi, &e0Lo, env, e->Iex.Mux0X.expr0);
-//.. iselInt64Expr(&eXHi, &eXLo, env, e->Iex.Mux0X.exprX);
-//.. addInstr(env, mk_iMOVsd_RR(eXHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(eXLo, tLo));
-//.. r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
-//.. addInstr(env, X86Instr_Test32(X86RI_Imm(0xFF), X86RM_Reg(r8)));
-//.. /* This assumes the first cmov32 doesn't trash the condition
-//.. codes, so they are still available for the second cmov32 */
-//.. addInstr(env, X86Instr_CMov32(Xcc_Z,X86RM_Reg(e0Hi),tHi));
-//.. addInstr(env, X86Instr_CMov32(Xcc_Z,X86RM_Reg(e0Lo),tLo));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-
/* --------- BINARY ops --------- */
if (e->tag == Iex_Binop) {
switch (e->Iex.Binop.op) {
@@ -2512,276 +2353,11 @@
*rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
return;
-//.. /* Or64/And64/Xor64 */
-//.. case Iop_Or64:
-//.. case Iop_And64:
-//.. case Iop_Xor64: {
-//.. HReg xLo, xHi, yLo, yHi;
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. X86AluOp op = e->Iex.Binop.op==Iop_Or64 ? Xalu_OR
-//.. : e->Iex.Binop.op==Iop_And64 ? Xalu_AND
-//.. : Xalu_XOR;
-//.. iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
-//.. addInstr(env, mk_iMOVsd_RR(xHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(xLo, tLo));
-//.. iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
-//.. addInstr(env, X86Instr_Alu32R(op, X86RMI_Reg(yHi), tHi));
-//.. addInstr(env, X86Instr_Alu32R(op, X86RMI_Reg(yLo), tLo));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. /* Add64/Sub64 */
-//.. case Iop_Add64:
-//.. case Iop_Sub64: {
-//.. HReg xLo, xHi, yLo, yHi;
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
-//.. addInstr(env, mk_iMOVsd_RR(xHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(xLo, tLo));
-//.. iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
-//.. if (e->Iex.Binop.op==Iop_Add64) {
-//.. addInstr(env, X86Instr_Alu32R(Xalu_ADD, X86RMI_Reg(yLo), tLo));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_ADC, X86RMI_Reg(yHi), tHi));
-//.. } else {
-//.. addInstr(env, X86Instr_Alu32R(Xalu_SUB, X86RMI_Reg(yLo), tLo));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_SBB, X86RMI_Reg(yHi), tHi));
-//.. }
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. /* 32HLto64(e1,e2) */
-//.. case Iop_32HLto64:
-//.. *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
-//.. *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. return;
-//..
-//.. /* 64-bit shifts */
-//.. case Iop_Shl64: {
-//.. /* We use the same ingenious scheme as gcc. Put the value
-//.. to be shifted into %hi:%lo, and the shift amount into
-//.. %cl. Then (dsts on right, a la ATT syntax):
-//..
-//.. shldl %cl, %lo, %hi -- make %hi be right for the
-//.. -- shift amt %cl % 32
-//.. shll %cl, %lo -- make %lo be right for the
-//.. -- shift amt %cl % 32
-//..
-//.. Now, if (shift amount % 64) is in the range 32 .. 63,
-//.. we have to do a fixup, which puts the result low half
-//.. into the result high half, and zeroes the low half:
-//..
-//.. testl $32, %ecx
-//..
-//.. cmovnz %lo, %hi
-//.. movl $0, %tmp -- sigh; need yet another reg
-//.. cmovnz %tmp, %lo
-//.. */
-//.. HReg rAmt, sHi, sLo, tHi, tLo, tTemp;
-//.. tLo = newVRegI(env);
-//.. tHi = newVRegI(env);
-//.. tTemp = newVRegI(env);
-//.. rAmt = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. iselInt64Expr(&sHi,&sLo, env, e->Iex.Binop.arg1);
-//.. addInstr(env, mk_iMOVsd_RR(rAmt, hregX86_ECX()));
-//.. addInstr(env, mk_iMOVsd_RR(sHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(sLo, tLo));
-//.. /* Ok. Now shift amt is in %ecx, and value is in tHi/tLo
-//.. and those regs are legitimately modifiable. */
-//.. addInstr(env, X86Instr_Sh3232(Xsh_SHL, 0/*%cl*/, tLo, tHi));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHL, 0/*%cl*/, X86RM_Reg(tLo)));
-//.. addInstr(env, X86Instr_Test32(X86RI_Imm(32),
-//.. X86RM_Reg(hregX86_ECX())));
-//.. addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tLo), tHi));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tTemp));
-//.. addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tTemp), tLo));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. case Iop_Shr64: {
-//.. /* We use the same ingenious scheme as gcc. Put the value
-//.. to be shifted into %hi:%lo, and the shift amount into
-//.. %cl. Then:
-//..
-//.. shrdl %cl, %hi, %lo -- make %lo be right for the
-//.. -- shift amt %cl % 32
-//.. shrl %cl, %hi -- make %hi be right for the
-//.. -- shift amt %cl % 32
-//..
-//.. Now, if (shift amount % 64) is in the range 32 .. 63,
-//.. we have to do a fixup, which puts the result high half
-//.. into the result low half, and zeroes the high half:
-//..
-//.. testl $32, %ecx
-//..
-//.. cmovnz %hi, %lo
-//.. movl $0, %tmp -- sigh; need yet another reg
-//.. cmovnz %tmp, %hi
-//.. */
-//.. HReg rAmt, sHi, sLo, tHi, tLo, tTemp;
-//.. tLo = newVRegI(env);
-//.. tHi = newVRegI(env);
-//.. tTemp = newVRegI(env);
-//.. rAmt = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. iselInt64Expr(&sHi,&sLo, env, e->Iex.Binop.arg1);
-//.. addInstr(env, mk_iMOVsd_RR(rAmt, hregX86_ECX()));
-//.. addInstr(env, mk_iMOVsd_RR(sHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(sLo, tLo));
-//.. /* Ok. Now shift amt is in %ecx, and value is in tHi/tLo
-//.. and those regs are legitimately modifiable. */
-//.. addInstr(env, X86Instr_Sh3232(Xsh_SHR, 0/*%cl*/, tHi, tLo));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHR, 0/*%cl*/, X86RM_Reg(tHi)));
-//.. addInstr(env, X86Instr_Test32(X86RI_Imm(32),
-//.. X86RM_Reg(hregX86_ECX())));
-//.. addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tHi), tLo));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tTemp));
-//.. addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tTemp), tHi));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. /* F64 -> I64 */
-//.. /* Sigh, this is an almost exact copy of the F64 -> I32/I16
-//.. case. Unfortunately I see no easy way to avoid the
-//.. duplication. */
-//.. case Iop_F64toI64: {
-//.. HReg rf = iselDblExpr(env, e->Iex.Binop.arg2);
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//..
-//.. /* Used several times ... */
-//.. /* Careful ... this sharing is only safe because
-//.. zero_esp/four_esp do not hold any registers which the
-//.. register allocator could attempt to swizzle later. */
-//.. X86AMode* zero_esp = X86AMode_IR(0, hregX86_ESP());
-//.. X86AMode* four_esp = X86AMode_IR(4, hregX86_ESP());
-//..
-//.. /* rf now holds the value to be converted, and rrm holds
-//.. the rounding mode value, encoded as per the
-//.. IRRoundingMode enum. The first thing to do is set the
-//.. FPU's rounding mode accordingly. */
-//..
-//.. /* Create a space for the format conversion. */
-//.. /* subl $8, %esp */
-//.. sub_from_esp(env, 8);
-//..
-//.. /* Set host rounding mode */
-//.. set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
-//..
-//.. /* gistll %rf, 0(%esp) */
-//.. addInstr(env, X86Instr_FpLdStI(False/*store*/, 8, rf, zero_esp));
-//..
-//.. /* movl 0(%esp), %dstLo */
-//.. /* movl 4(%esp), %dstHi */
-//.. addInstr(env, X86Instr_Alu32R(
-//.. Xalu_MOV, X86RMI_Mem(zero_esp), tLo));
-//.. addInstr(env, X86Instr_Alu32R(
-//.. Xalu_MOV, X86RMI_Mem(four_esp), tHi));
-//..
-//.. /* Restore default FPU rounding. */
-//.. set_FPU_rounding_default( env );
-//..
-//.. /* addl $8, %esp */
-//.. add_to_esp(env, 8);
-//..
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
default:
break;
}
} /* if (e->tag == Iex_Binop) */
-
-//.. /* --------- UNARY ops --------- */
-//.. if (e->tag == Iex_Unop) {
-//.. switch (e->Iex.Unop.op) {
-//..
-//.. /* 32Sto64(e) */
-//.. case Iop_32Sto64: {
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-//.. addInstr(env, mk_iMOVsd_RR(src,tHi));
-//.. addInstr(env, mk_iMOVsd_RR(src,tLo));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, X86RM_Reg(tHi)));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. /* 32Uto64(e) */
-//.. case Iop_32Uto64: {
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-//.. addInstr(env, mk_iMOVsd_RR(src,tLo));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tHi));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-
-//.. /* could do better than this, but for now ... */
-//.. case Iop_1Sto64: {
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. X86CondCode cond = iselCondCode(env, e->Iex.Unop.arg);
-//.. addInstr(env, X86Instr_Set32(cond,tLo));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHL, 31, X86RM_Reg(tLo)));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, X86RM_Reg(tLo)));
-//.. addInstr(env, mk_iMOVsd_RR(tLo, tHi));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. /* Not64(e) */
-//.. case Iop_Not64: {
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//.. HReg sHi, sLo;
-//.. iselInt64Expr(&sHi, &sLo, env, e->Iex.Unop.arg);
-//.. addInstr(env, mk_iMOVsd_RR(sHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(sLo, tLo));
-//.. addInstr(env, X86Instr_Unary32(Xun_NOT,X86RM_Reg(tHi)));
-//.. addInstr(env, X86Instr_Unary32(Xun_NOT,X86RM_Reg(tLo)));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-//..
-//.. default:
-//.. break;
-//.. }
-//.. } /* if (e->tag == Iex_Unop) */
-//..
-//..
-//.. /* --------- CCALL --------- */
-//.. if (e->tag == Iex_CCall) {
-//.. HReg tLo = newVRegI(env);
-//.. HReg tHi = newVRegI(env);
-//..
-//.. /* Marshal args, do the call, clear stack. */
-//.. doHelperCall( env, False, NULL, e->Iex.CCall.cee, e->Iex.CCall.args );
-//..
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EDX(), tHi));
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), tLo));
-//.. *rHi = tHi;
-//.. *rLo = tLo;
-//.. return;
-//.. }
-
ppIRExpr(e);
vpanic("iselInt128Expr");
}
@@ -2991,8 +2567,9 @@
}
if (e->tag == Iex_Triop) {
+ IRTriop *triop = e->Iex.Triop.details;
AMD64SseOp op = Asse_INVALID;
- switch (e->Iex.Triop.op) {
+ switch (triop->op) {
case Iop_AddF64: op = Asse_ADDF; break;
case Iop_SubF64: op = Asse_SUBF; break;
case Iop_MulF64: op = Asse_MULF; break;
@@ -3001,8 +2578,8 @@
}
if (op != Asse_INVALID) {
HReg dst = newVRegV(env);
- HReg argL = iselDblExpr(env, e->Iex.Triop.arg2);
- HReg argR = iselDblExpr(env, e->Iex.Triop.arg3);
+ HReg argL = iselDblExpr(env, triop->arg2);
+ HReg argR = iselDblExpr(env, triop->arg3);
addInstr(env, mk_vMOVsd_RR(argL, dst));
/* XXXROUNDINGFIXME */
/* set roundingmode here */
@@ -3035,21 +2612,22 @@
return dst;
}
+ IRTriop *triop = e->Iex.Triop.details;
if (e->tag == Iex_Triop
- && (e->Iex.Triop.op == Iop_ScaleF64
- || e->Iex.Triop.op == Iop_AtanF64
- || e->Iex.Triop.op == Iop_Yl2xF64
- || e->Iex.Triop.op == Iop_Yl2xp1F64
- || e->Iex.Triop.op == Iop_PRemF64
- || e->Iex.Triop.op == Iop_PRem1F64)
+ && (triop->op == Iop_ScaleF64
+ || triop->op == Iop_AtanF64
+ || triop->op == Iop_Yl2xF64
+ || triop->op == Iop_Yl2xp1F64
+ || triop->op == Iop_PRemF64
+ || triop->op == Iop_PRem1F64)
) {
AMD64AMode* m8_rsp = AMD64AMode_IR(-8, hregAMD64_RSP());
- HReg arg1 = iselDblExpr(env, e->Iex.Triop.arg2);
- HReg arg2 = iselDblExpr(env, e->Iex.Triop.arg3);
+ HReg arg1 = iselDblExpr(env, triop->arg2);
+ HReg arg2 = iselDblExpr(env, triop->arg3);
HReg dst = newVRegV(env);
- Bool arg2first = toBool(e->Iex.Triop.op == Iop_ScaleF64
- || e->Iex.Triop.op == Iop_PRemF64
- || e->Iex.Triop.op == Iop_PRem1F64);
+ Bool arg2first = toBool(triop->op == Iop_ScaleF64
+ || triop->op == Iop_PRemF64
+ || triop->op == Iop_PRem1F64);
addInstr(env, AMD64Instr_A87Free(2));
/* one arg -> top of x87 stack */
@@ -3065,7 +2643,7 @@
/* do it */
/* XXXROUNDINGFIXME */
/* set roundingmode here */
- switch (e->Iex.Triop.op) {
+ switch (triop->op) {
case Iop_ScaleF64:
addInstr(env, AMD64Instr_A87FpOp(Afp_SCALE));
break;
@@ -3363,8 +2941,6 @@
return dst;
}
-//.. case Iop_Recip64Fx2: op = Xsse_RCPF; goto do_64Fx2_unary;
-//.. case Iop_RSqrt64Fx2: op = Asse_RSQRTF; goto do_64Fx2_unary;
case Iop_Sqrt64Fx2: op = Asse_SQRTF; goto do_64Fx2_unary;
do_64Fx2_unary:
{
@@ -3392,8 +2968,6 @@
return dst;
}
-//.. case Iop_Recip64F0x2: op = Xsse_RCPF; goto do_64F0x2_unary;
-//.. case Iop_RSqrt64F0x2: op = Xsse_RSQRTF; goto do_64F0x2_unary;
case Iop_Sqrt64F0x2: op = Asse_SQRTF; goto do_64F0x2_unary;
do_64F0x2_unary:
{
@@ -3429,6 +3003,13 @@
return dst;
}
+ case Iop_V256toV128_0:
+ case Iop_V256toV128_1: {
+ HReg vHi, vLo;
+ iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
+ return (e->Iex.Unop.op == Iop_V256toV128_1) ? vHi : vLo;
+ }
+
default:
break;
} /* switch (e->Iex.Unop.op) */
@@ -3437,6 +3018,7 @@
if (e->tag == Iex_Binop) {
switch (e->Iex.Binop.op) {
+ /* FIXME: could we generate MOVQ here? */
case Iop_SetV128lo64: {
HReg dst = newVRegV(env);
HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1);
@@ -3448,6 +3030,7 @@
return dst;
}
+ /* FIXME: could we generate MOVD here? */
case Iop_SetV128lo32: {
HReg dst = newVRegV(env);
HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1);
@@ -3460,13 +3043,16 @@
}
case Iop_64HLtoV128: {
- AMD64AMode* rsp = AMD64AMode_IR(0, hregAMD64_RSP());
+ HReg rsp = hregAMD64_RSP();
+ AMD64AMode* m8_rsp = AMD64AMode_IR(-8, rsp);
+ AMD64AMode* m16_rsp = AMD64AMode_IR(-16, rsp);
+ AMD64RI* qHi = iselIntExpr_RI(env, e->Iex.Binop.arg1);
+ AMD64RI* qLo = iselIntExpr_RI(env, e->Iex.Binop.arg2);
+ addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, qHi, m8_rsp));
+ addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, qLo, m16_rsp));
HReg dst = newVRegV(env);
- /* do this via the stack (easy, convenient, etc) */
- addInstr(env, AMD64Instr_Push(iselIntExpr_RMI(env, e->Iex.Binop.arg1)));
- addInstr(env, AMD64Instr_Push(iselIntExpr_RMI(env, e->Iex.Binop.arg2)));
- addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, rsp));
- add_to_rsp(env, 16);
+ /* One store-forwarding stall coming up, oh well :-( */
+ addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, m16_rsp));
return dst;
}
@@ -3666,6 +3252,8 @@
goto do_SseAssistedBinary;
case Iop_CmpGT64Sx2: fn = (HWord)h_generic_calc_CmpGT64Sx2;
goto do_SseAssistedBinary;
+ case Iop_Perm32x4: fn = (HWord)h_generic_calc_Perm32x4;
+ goto do_SseAssistedBinary;
case Iop_QNarrowBin32Sto16Ux8:
fn = (HWord)h_generic_calc_QNarrowBin32Sto16Ux8;
goto do_SseAssistedBinary;
@@ -3795,6 +3383,283 @@
/*---------------------------------------------------------*/
+/*--- ISEL: SIMD (V256) expressions, into 2 XMM regs. --*/
+/*---------------------------------------------------------*/
+
+static void iselDVecExpr ( /*OUT*/HReg* rHi, /*OUT*/HReg* rLo,
+ ISelEnv* env, IRExpr* e )
+{
+ iselDVecExpr_wrk( rHi, rLo, env, e );
+# if 0
+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
+# endif
+ vassert(hregClass(*rHi) == HRcVec128);
+ vassert(hregClass(*rLo) == HRcVec128);
+ vassert(hregIsVirtual(*rHi));
+ vassert(hregIsVirtual(*rLo));
+}
+
+
+/* DO NOT CALL THIS DIRECTLY */
+static void iselDVecExpr_wrk ( /*OUT*/HReg* rHi, /*OUT*/HReg* rLo,
+ ISelEnv* env, IRExpr* e )
+{
+ vassert(e);
+ IRType ty = typeOfIRExpr(env->type_env,e);
+ vassert(ty == Ity_V256);
+
+ AMD64SseOp op = Asse_INVALID;
+
+ /* read 256-bit IRTemp */
+ if (e->tag == Iex_RdTmp) {
+ lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp);
+ return;
+ }
+
+ if (e->tag == Iex_Get) {
+ HReg vHi = newVRegV(env);
+ HReg vLo = newVRegV(env);
+ HReg rbp = hregAMD64_RBP();
+ AMD64AMode* am0 = AMD64AMode_IR(e->Iex.Get.offset + 0, rbp);
+ AMD64AMode* am16 = AMD64AMode_IR(e->Iex.Get.offset + 16, rbp);
+ addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));
+ addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
+ *rHi = vHi;
+ *rLo = vLo;
+ return;
+ }
+
+ if (e->tag == Iex_Load) {
+ HReg vHi = newVRegV(env);
+ HReg vLo = newVRegV(env);
+ HReg rA = iselIntExpr_R(env, e->Iex.Load.addr);
+ AMD64AMode* am0 = AMD64AMode_IR(0, rA);
+ AMD64AMode* am16 = AMD64AMode_IR(16, rA);
+ addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));
+ addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
+ *rHi = vHi;
+ *rLo = vLo;
+ return;
+ }
+
+ if (e->tag == Iex_Const) {
+ vassert(e->Iex.Const.con->tag == Ico_V256);
+ switch (e->Iex.Const.con->Ico.V256) {
+ case 0x00000000: {
+ HReg vHi = generate_zeroes_V128(env);
+ HReg vLo = newVRegV(env);
+ addInstr(env, mk_vMOVsd_RR(vHi, vLo));
+ *rHi = vHi;
+ *rLo = vLo;
+ return;
+ }
+ default:
+ break; /* give up. Until such time as is necessary. */
+ }
+ }
+
+ if (e->tag == Iex_Unop) {
+ switch (e->Iex.Unop.op) {
+
+ case Iop_NotV256: {
+ HReg argHi, argLo;
+ iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
+ *rHi = do_sse_NotV128(env, argHi);
+ *rLo = do_sse_NotV128(env, argLo);
+ return;
+ }
+
+ case Iop_Recip32Fx8: op = Asse_RCPF; goto do_32Fx8_unary;
+ case Iop_Sqrt32Fx8: op = Asse_SQRTF; goto do_32Fx8_unary;
+ case Iop_RSqrt32Fx8: op = Asse_RSQRTF; goto do_32Fx8_unary;
+ do_32Fx8_unary:
+ {
+ HReg argHi, argLo;
+ iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ addInstr(env, AMD64Instr_Sse32Fx4(op, argHi, dstHi));
+ addInstr(env, AMD64Instr_Sse32Fx4(op, argLo, dstLo));
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
+ case Iop_Sqrt64Fx4: op = Asse_SQRTF; goto do_64Fx4_unary;
+ do_64Fx4_unary:
+ {
+ HReg argHi, argLo;
+ iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ addInstr(env, AMD64Instr_Sse64Fx2(op, argHi, dstHi));
+ addInstr(env, AMD64Instr_Sse64Fx2(op, argLo, dstLo));
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
+ case Iop_CmpNEZ64x4: {
+ /* We can use SSE2 instructions for this. */
+ /* Same scheme as Iop_CmpNEZ64x2, except twice as wide
+ (obviously). See comment on Iop_CmpNEZ64x2 for
+ explanation of what's going on here. */
+ HReg argHi, argLo;
+ iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
+ HReg tmpHi = generate_zeroes_V128(env);
+ HReg tmpLo = newVRegV(env);
+ addInstr(env, mk_vMOVsd_RR(tmpHi, tmpLo));
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, argHi, tmpHi));
+ addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, argLo, tmpLo));
+ tmpHi = do_sse_NotV128(env, tmpHi);
+ tmpLo = do_sse_NotV128(env, tmpLo);
+ addInstr(env, AMD64Instr_SseShuf(0xB1, tmpHi, dstHi));
+ addInstr(env, AMD64Instr_SseShuf(0xB1, tmpLo, dstLo));
+ addInstr(env, AMD64Instr_SseReRg(Asse_OR, tmpHi, dstHi));
+ addInstr(env, AMD64Instr_SseReRg(Asse_OR, tmpLo, dstLo));
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
+ case Iop_CmpNEZ32x8: op = Asse_CMPEQ32; goto do_CmpNEZ_vector;
+ do_CmpNEZ_vector:
+ {
+ HReg argHi, argLo;
+ iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
+ HReg tmpHi = newVRegV(env);
+ HReg tmpLo = newVRegV(env);
+ HReg zero = generate_zeroes_V128(env);
+ HReg dstHi, dstLo;
+ addInstr(env, mk_vMOVsd_RR(argHi, tmpHi));
+ addInstr(env, mk_vMOVsd_RR(argLo, tmpLo));
+ addInstr(env, AMD64Instr_SseReRg(op, zero, tmpHi));
+ addInstr(env, AMD64Instr_SseReRg(op, zero, tmpLo));
+ dstHi = do_sse_NotV128(env, tmpHi);
+ dstLo = do_sse_NotV128(env, tmpLo);
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
+ default:
+ break;
+ } /* switch (e->Iex.Unop.op) */
+ } /* if (e->tag == Iex_Unop) */
+
+ if (e->tag == Iex_Binop) {
+ switch (e->Iex.Binop.op) {
+
+ case Iop_Add64Fx4: op = Asse_ADDF; goto do_64Fx4;
+ case Iop_Sub64Fx4: op = Asse_SUBF; goto do_64Fx4;
+ case Iop_Mul64Fx4: op = Asse_MULF; goto do_64Fx4;
+ case Iop_Div64Fx4: op = Asse_DIVF; goto do_64Fx4;
+ case Iop_Max64Fx4: op = Asse_MAXF; goto do_64Fx4;
+ case Iop_Min64Fx4: op = Asse_MINF; goto do_64Fx4;
+ do_64Fx4:
+ {
+ HReg argLhi, argLlo, argRhi, argRlo;
+ iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1);
+ iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ addInstr(env, mk_vMOVsd_RR(argLhi, dstHi));
+ addInstr(env, mk_vMOVsd_RR(argLlo, dstLo));
+ addInstr(env, AMD64Instr_Sse64Fx2(op, argRhi, dstHi));
+ addInstr(env, AMD64Instr_Sse64Fx2(op, argRlo, dstLo));
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
+ case Iop_Add32Fx8: op = Asse_ADDF; goto do_32Fx8;
+ case Iop_Sub32Fx8: op = Asse_SUBF; goto do_32Fx8;
+ case Iop_Mul32Fx8: op = Asse_MULF; goto do_32Fx8;
+ case Iop_Div32Fx8: op = Asse_DIVF; goto do_32Fx8;
+ case Iop_Max32Fx8: op = Asse_MAXF; goto do_32Fx8;
+ case Iop_Min32Fx8: op = Asse_MINF; goto do_32Fx8;
+ do_32Fx8:
+ {
+ HReg argLhi, argLlo, argRhi, argRlo;
+ iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1);
+ iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ addInstr(env, mk_vMOVsd_RR(argLhi, dstHi));
+ addInstr(env, mk_vMOVsd_RR(argLlo, dstLo));
+ addInstr(env, AMD64Instr_Sse32Fx4(op, argRhi, dstHi));
+ addInstr(env, AMD64Instr_Sse32Fx4(op, argRlo, dstLo));
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
+ case Iop_AndV256: op = Asse_AND; goto do_SseReRg;
+ case Iop_OrV256: op = Asse_OR; goto do_SseReRg;
+ case Iop_XorV256: op = Asse_XOR; goto do_SseReRg;
+ do_SseReRg:
+ {
+ HReg argLhi, argLlo, argRhi, argRlo;
+ iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1);
+ iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ addInstr(env, mk_vMOVsd_RR(argLhi, dstHi));
+ addInstr(env, mk_vMOVsd_RR(argLlo, dstLo));
+ addInstr(env, AMD64Instr_SseReRg(op, argRhi, dstHi));
+ addInstr(env, AMD64Instr_SseReRg(op, argRlo, dstLo));
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+
+ case Iop_V128HLtoV256: {
+ *rHi = iselVecExpr(env, e->Iex.Binop.arg1);
+ *rLo = iselVecExpr(env, e->Iex.Binop.arg2);
+ return;
+ }
+
+ default:
+ break;
+ } /* switch (e->Iex.Binop.op) */
+ } /* if (e->tag == Iex_Binop) */
+
+ if (e->tag == Iex_Qop && e->Iex.Qop.details->op == Iop_64x4toV256) {
+ HReg rsp = hregAMD64_RSP();
+ HReg vHi = newVRegV(env);
+ HReg vLo = newVRegV(env);
+ AMD64AMode* m8_rsp = AMD64AMode_IR(-8, rsp);
+ AMD64AMode* m16_rsp = AMD64AMode_IR(-16, rsp);
+ /* arg1 is the most significant (Q3), arg4 the least (Q0) */
+ /* Get all the args into regs, before messing with the stack. */
+ AMD64RI* q3 = iselIntExpr_RI(env, e->Iex.Qop.details->arg1);
+ AMD64RI* q2 = iselIntExpr_RI(env, e->Iex.Qop.details->arg2);
+ AMD64RI* q1 = iselIntExpr_RI(env, e->Iex.Qop.details->arg3);
+ AMD64RI* q0 = iselIntExpr_RI(env, e->Iex.Qop.details->arg4);
+ /* less significant lane (Q2) at the lower address (-16(rsp)) */
+ addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q3, m8_rsp));
+ addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q2, m16_rsp));
+ addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, m16_rsp));
+ /* and then the lower half .. */
+ addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q1, m8_rsp));
+ addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q0, m16_rsp));
+ addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, m16_rsp));
+ *rHi = vHi;
+ *rLo = vLo;
+ return;
+ }
+
+ //avx_fail:
+ vex_printf("iselDVecExpr (amd64, subarch = %s): can't reduce\n",
+ LibVEX_ppVexHwCaps(VexArchAMD64, env->hwcaps));
+ ppIRExpr(e);
+ vpanic("iselDVecExpr_wrk");
+}
+
+
+/*---------------------------------------------------------*/
/*--- ISEL: Statements ---*/
/*---------------------------------------------------------*/
@@ -3849,6 +3714,16 @@
addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, r, am));
return;
}
+ if (tyd == Ity_V256) {
+ HReg rA = iselIntExpr_R(env, stmt->Ist.Store.addr);
+ AMD64AMode* am0 = AMD64AMode_IR(0, rA);
+ AMD64AMode* am16 = AMD64AMode_IR(16, rA);
+ HReg vHi, vLo;
+ iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Store.data);
+ addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));
+ addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
+ return;
+ }
break;
}
@@ -3877,13 +3752,6 @@
hregAMD64_RBP())));
return;
}
- if (ty == Ity_V128) {
- HReg vec = iselVecExpr(env, stmt->Ist.Put.data);
- AMD64AMode* am = AMD64AMode_IR(stmt->Ist.Put.offset,
- hregAMD64_RBP());
- addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vec, am));
- return;
- }
if (ty == Ity_F32) {
HReg f32 = iselFltExpr(env, stmt->Ist.Put.data);
AMD64AMode* am = AMD64AMode_IR(stmt->Ist.Put.offset, hregAMD64_RBP());
@@ -3898,29 +3766,48 @@
addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, f64, am ));
return;
}
+ if (ty == Ity_V128) {
+ HReg vec = iselVecExpr(env, stmt->Ist.Put.data);
+ AMD64AMode* am = AMD64AMode_IR(stmt->Ist.Put.offset,
+ hregAMD64_RBP());
+ addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vec, am));
+ return;
+ }
+ if (ty == Ity_V256) {
+ HReg vHi, vLo;
+ iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Put.data);
+ HReg rbp = hregAMD64_RBP();
+ AMD64AMode* am0 = AMD64AMode_IR(stmt->Ist.Put.offset + 0, rbp);
+ AMD64AMode* am16 = AMD64AMode_IR(stmt->Ist.Put.offset + 16, rbp);
+ addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));
+ addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
+ return;
+ }
break;
}
/* --------- Indexed PUT --------- */
case Ist_PutI: {
+ IRPutI *puti = stmt->Ist.PutI.details;
+
AMD64AMode* am
= genGuestArrayOffset(
- env, stmt->Ist.PutI.descr,
- stmt->Ist.PutI.ix, stmt->Ist.PutI.bias );
+ env, puti->descr,
+ puti->ix, puti->bias );
- IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.PutI.data);
+ IRType ty = typeOfIRExpr(env->type_env, puti->data);
if (ty == Ity_F64) {
- HReg val = iselDblExpr(env, stmt->Ist.PutI.data);
+ HReg val = iselDblExpr(env, puti->data);
addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, val, am ));
return;
}
if (ty == Ity_I8) {
- HReg r = iselIntExpr_R(env, stmt->Ist.PutI.data);
+ HReg r = iselIntExpr_R(env, puti->data);
addInstr(env, AMD64Instr_Store( 1, r, am ));
return;
}
if (ty == Ity_I64) {
- AMD64RI* ri = iselIntExpr_RI(env, stmt->Ist.PutI.data);
+ AMD64RI* ri = iselIntExpr_RI(env, puti->data);
addInstr(env, AMD64Instr_Alu64M( Aalu_MOV, ri, am ));
return;
}
@@ -3965,7 +3852,7 @@
if (ty == Ity_I128) {
HReg rHi, rLo, dstHi, dstLo;
iselInt128Expr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
- lookupIRTemp128( &dstHi, &dstLo, env, tmp);
+ lookupIRTempPair( &dstHi, &dstLo, env, tmp);
addInstr(env, mk_iMOVsd_RR(rHi,dstHi) );
addInstr(env, mk_iMOVsd_RR(rLo,dstLo) );
return;
@@ -3994,6 +3881,14 @@
addInstr(env, mk_vMOVsd_RR(src, dst));
return;
}
+ if (ty == Ity_V256) {
+ HReg rHi, rLo, dstHi, dstLo;
+ iselDVecExpr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
+ lookupIRTempPair( &dstHi, &dstLo, env, tmp);
+ addInstr(env, mk_vMOVsd_RR(rHi,dstHi) );
+ addInstr(env, mk_vMOVsd_RR(rLo,dstLo) );
+ return;
+ }
break;
}
@@ -4131,14 +4026,57 @@
/* --------- EXIT --------- */
case Ist_Exit: {
- AMD64RI* dst;
- AMD64CondCode cc;
if (stmt->Ist.Exit.dst->tag != Ico_U64)
vpanic("iselStmt(amd64): Ist_Exit: dst is not a 64-bit value");
- dst = iselIntExpr_RI(env, IRExpr_Const(stmt->Ist.Exit.dst));
- cc = iselCondCode(env,stmt->Ist.Exit.guard);
- addInstr(env, AMD64Instr_Goto(stmt->Ist.Exit.jk, cc, dst));
- return;
+
+ AMD64CondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
+ AMD64AMode* amRIP = AMD64AMode_IR(stmt->Ist.Exit.offsIP,
+ hregAMD64_RBP());
+
+ /* Case: boring transfer to known address */
+ if (stmt->Ist.Exit.jk == Ijk_Boring) {
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > env->max_ga;
+ if (0) vex_printf("%s", toFastEP ? "Y" : ",");
+ addInstr(env, AMD64Instr_XDirect(stmt->Ist.Exit.dst->Ico.U64,
+ amRIP, cc, toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, AMD64Instr_XAssisted(r, amRIP, cc, Ijk_Boring));
+ }
+ return;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (stmt->Ist.Exit.jk) {
+ /* Keep this list in sync with that in iselNext below */
+ case Ijk_ClientReq:
+ case Ijk_EmWarn:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_SigSEGV:
+ case Ijk_SigTRAP:
+ case Ijk_Sys_syscall:
+ case Ijk_TInval:
+ case Ijk_Yield:
+ {
+ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, AMD64Instr_XAssisted(r, amRIP, cc, stmt->Ist.Exit.jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Do we ever expect to see any other kind? */
+ goto stmt_fail;
}
default: break;
@@ -4153,18 +4091,91 @@
/*--- ISEL: Basic block terminators (Nexts) ---*/
/*---------------------------------------------------------*/
-static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk )
+static void iselNext ( ISelEnv* env,
+ IRExpr* next, IRJumpKind jk, Int offsIP )
{
- AMD64RI* ri;
if (vex_traceflags & VEX_TRACE_VCODE) {
- vex_printf("\n-- goto {");
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
ppIRJumpKind(jk);
- vex_printf("} ");
- ppIRExpr(next);
- vex_printf("\n");
+ vex_printf( "\n");
}
- ri = iselIntExpr_RI(env, next);
- addInstr(env, AMD64Instr_Goto(jk, Acc_ALWAYS,ri));
+
+ /* Case: boring transfer to known address */
+ if (next->tag == Iex_Const) {
+ IRConst* cdst = next->Iex.Const.con;
+ vassert(cdst->tag == Ico_U64);
+ if (jk == Ijk_Boring || jk == Ijk_Call) {
+ /* Boring transfer to known address */
+ AMD64AMode* amRIP = AMD64AMode_IR(offsIP, hregAMD64_RBP());
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = ((Addr64)cdst->Ico.U64) > env->max_ga;
+ if (0) vex_printf("%s", toFastEP ? "X" : ".");
+ addInstr(env, AMD64Instr_XDirect(cdst->Ico.U64,
+ amRIP, Acc_ALWAYS,
+ toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an indirect transfer,
+ as that's the cheapest alternative that is
+ allowable. */
+ HReg r = iselIntExpr_R(env, next);
+ addInstr(env, AMD64Instr_XAssisted(r, amRIP, Acc_ALWAYS,
+ Ijk_Boring));
+ }
+ return;
+ }
+ }
+
+ /* Case: call/return (==boring) transfer to any address */
+ switch (jk) {
+ case Ijk_Boring: case Ijk_Ret: case Ijk_Call: {
+ HReg r = iselIntExpr_R(env, next);
+ AMD64AMode* amRIP = AMD64AMode_IR(offsIP, hregAMD64_RBP());
+ if (env->chainingAllowed) {
+ addInstr(env, AMD64Instr_XIndir(r, amRIP, Acc_ALWAYS));
+ } else {
+ addInstr(env, AMD64Instr_XAssisted(r, amRIP, Acc_ALWAYS,
+ Ijk_Boring));
+ }
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (jk) {
+ /* Keep this list in sync with that for Ist_Exit above */
+ case Ijk_ClientReq:
+ case Ijk_EmWarn:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_SigSEGV:
+ case Ijk_SigTRAP:
+ case Ijk_Sys_syscall:
+ case Ijk_TInval:
+ case Ijk_Yield: {
+ HReg r = iselIntExpr_R(env, next);
+ AMD64AMode* amRIP = AMD64AMode_IR(offsIP, hregAMD64_RBP());
+ addInstr(env, AMD64Instr_XAssisted(r, amRIP, Acc_ALWAYS, jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
+ ppIRJumpKind(jk);
+ vex_printf( "\n");
+ vassert(0); // are we expecting any other kind?
}
@@ -4174,21 +4185,29 @@
/* Translate an entire SB to amd64 code. */
-HInstrArray* iselSB_AMD64 ( IRSB* bb, VexArch arch_host,
- VexArchInfo* archinfo_host,
- VexAbiInfo* vbi/*UNUSED*/ )
+HInstrArray* iselSB_AMD64 ( IRSB* bb,
+ VexArch arch_host,
+ VexArchInfo* archinfo_host,
+ VexAbiInfo* vbi/*UNUSED*/,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga )
{
- Int i, j;
- HReg hreg, hregHI;
- ISelEnv* env;
- UInt hwcaps_host = archinfo_host->hwcaps;
+ Int i, j;
+ HReg hreg, hregHI;
+ ISelEnv* env;
+ UInt hwcaps_host = archinfo_host->hwcaps;
+ AMD64AMode *amCounter, *amFailAddr;
/* sanity ... */
vassert(arch_host == VexArchAMD64);
vassert(0 == (hwcaps_host
& ~(VEX_HWCAPS_AMD64_SSE3
| VEX_HWCAPS_AMD64_CX16
- | VEX_HWCAPS_AMD64_LZCNT)));
+ | VEX_HWCAPS_AMD64_LZCNT
+ | VEX_HWCAPS_AMD64_AVX)));
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
@@ -4207,7 +4226,9 @@
env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
/* and finally ... */
- env->hwcaps = hwcaps_host;
+ env->chainingAllowed = chainingAllowed;
+ env->hwcaps = hwcaps_host;
+ env->max_ga = max_ga;
/* For each IR temporary, allocate a suitably-kinded virtual
register. */
@@ -4216,29 +4237,50 @@
hregHI = hreg = INVALID_HREG;
switch (bb->tyenv->types[i]) {
case Ity_I1:
- case Ity_I8:
- case Ity_I16:
- case Ity_I32:
- case Ity_I64: hreg = mkHReg(j++, HRcInt64, True); break;
- case Ity_I128: hreg = mkHReg(j++, HRcInt64, True);
- hregHI = mkHReg(j++, HRcInt64, True); break;
+ case Ity_I8: case Ity_I16: case Ity_I32: case Ity_I64:
+ hreg = mkHReg(j++, HRcInt64, True);
+ break;
+ case Ity_I128:
+ hreg = mkHReg(j++, HRcInt64, True);
+ hregHI = mkHReg(j++, HRcInt64, True);
+ break;
case Ity_F32:
case Ity_F64:
- case Ity_V128: hreg = mkHReg(j++, HRcVec128, True); break;
- default: ppIRType(bb->tyenv->types[i]);
- vpanic("iselBB(amd64): IRTemp type");
+ case Ity_V128:
+ hreg = mkHReg(j++, HRcVec128, True);
+ break;
+ case Ity_V256:
+ hreg = mkHReg(j++, HRcVec128, True);
+ hregHI = mkHReg(j++, HRcVec128, True);
+ break;
+ default:
+ ppIRType(bb->tyenv->types[i]);
+ vpanic("iselBB(amd64): IRTemp type");
}
env->vregmap[i] = hreg;
env->vregmapHI[i] = hregHI;
}
env->vreg_ctr = j;
+ /* The very first instruction must be an event check. */
+ amCounter = AMD64AMode_IR(offs_Host_EvC_Counter, hregAMD64_RBP());
+ amFailAddr = AMD64AMode_IR(offs_Host_EvC_FailAddr, hregAMD64_RBP());
+ addInstr(env, AMD64Instr_EvCheck(amCounter, amFailAddr));
+
+ /* Possibly a block counter increment (for profiling). At this
+ point we don't know the address of the counter, so just pretend
+ it is zero. It will have to be patched later, but before this
+ translation is used, by a call to LibVEX_patchProfCtr. */
+ if (addProfInc) {
+ addInstr(env, AMD64Instr_ProfInc());
+ }
+
/* Ok, finally we can iterate over the statements. */
for (i = 0; i < bb->stmts_used; i++)
if (bb->stmts[i])
- iselStmt(env,bb->stmts[i]);
+ iselStmt(env, bb->stmts[i]);
- iselNext(env,bb->next,bb->jumpkind);
+ iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
/* record the number of vregs we used. */
env->code->n_vregs = env->vreg_ctr;
diff --git a/main/VEX/priv/host_arm_defs.c b/main/VEX/priv/host_arm_defs.c
index fc3c02c..e428da0 100644
--- a/main/VEX/priv/host_arm_defs.c
+++ b/main/VEX/priv/host_arm_defs.c
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
NEON support is
- Copyright (C) 2010-2011 Samsung Electronics
+ Copyright (C) 2010-2012 Samsung Electronics
contributed by Dmitry Zhurikhin <zhur@ispras.ru>
and Kirill Batuzov <batuzovk@ispras.ru>
@@ -1170,13 +1170,33 @@
i->ARMin.LdSt8U.amode = amode;
return i;
}
-//extern ARMInstr* ARMInstr_Ld8S ( HReg, ARMAMode2* );
-ARMInstr* ARMInstr_Goto ( IRJumpKind jk, ARMCondCode cond, HReg gnext ) {
- ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
- i->tag = ARMin_Goto;
- i->ARMin.Goto.jk = jk;
- i->ARMin.Goto.cond = cond;
- i->ARMin.Goto.gnext = gnext;
+ARMInstr* ARMInstr_XDirect ( Addr32 dstGA, ARMAMode1* amR15T,
+ ARMCondCode cond, Bool toFastEP ) {
+ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+ i->tag = ARMin_XDirect;
+ i->ARMin.XDirect.dstGA = dstGA;
+ i->ARMin.XDirect.amR15T = amR15T;
+ i->ARMin.XDirect.cond = cond;
+ i->ARMin.XDirect.toFastEP = toFastEP;
+ return i;
+}
+ARMInstr* ARMInstr_XIndir ( HReg dstGA, ARMAMode1* amR15T,
+ ARMCondCode cond ) {
+ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+ i->tag = ARMin_XIndir;
+ i->ARMin.XIndir.dstGA = dstGA;
+ i->ARMin.XIndir.amR15T = amR15T;
+ i->ARMin.XIndir.cond = cond;
+ return i;
+}
+ARMInstr* ARMInstr_XAssisted ( HReg dstGA, ARMAMode1* amR15T,
+ ARMCondCode cond, IRJumpKind jk ) {
+ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+ i->tag = ARMin_XAssisted;
+ i->ARMin.XAssisted.dstGA = dstGA;
+ i->ARMin.XAssisted.amR15T = amR15T;
+ i->ARMin.XAssisted.cond = cond;
+ i->ARMin.XAssisted.jk = jk;
return i;
}
ARMInstr* ARMInstr_CMov ( ARMCondCode cond, HReg dst, ARMRI84* src ) {
@@ -1479,6 +1499,21 @@
return i;
}
+ARMInstr* ARMInstr_EvCheck ( ARMAMode1* amCounter,
+ ARMAMode1* amFailAddr ) {
+ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+ i->tag = ARMin_EvCheck;
+ i->ARMin.EvCheck.amCounter = amCounter;
+ i->ARMin.EvCheck.amFailAddr = amFailAddr;
+ return i;
+}
+
+ARMInstr* ARMInstr_ProfInc ( void ) {
+ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+ i->tag = ARMin_ProfInc;
+ return i;
+}
+
/* ... */
void ppARMInstr ( ARMInstr* i ) {
@@ -1564,28 +1599,47 @@
return;
case ARMin_Ld8S:
goto unhandled;
- case ARMin_Goto:
- if (i->ARMin.Goto.cond != ARMcc_AL) {
- vex_printf("if (%%cpsr.%s) { ",
- showARMCondCode(i->ARMin.Goto.cond));
- } else {
- vex_printf("if (1) { ");
- }
- if (i->ARMin.Goto.jk != Ijk_Boring
- && i->ARMin.Goto.jk != Ijk_Call
- && i->ARMin.Goto.jk != Ijk_Ret) {
- vex_printf("mov r8, $");
- ppIRJumpKind(i->ARMin.Goto.jk);
- vex_printf(" ; ");
- }
- vex_printf("mov r0, ");
- ppHRegARM(i->ARMin.Goto.gnext);
- vex_printf(" ; bx r14");
- if (i->ARMin.Goto.cond != ARMcc_AL) {
- vex_printf(" }");
- } else {
- vex_printf(" }");
- }
+ case ARMin_XDirect:
+ vex_printf("(xDirect) ");
+ vex_printf("if (%%cpsr.%s) { ",
+ showARMCondCode(i->ARMin.XDirect.cond));
+ vex_printf("movw r12,0x%x; ",
+ (UInt)(i->ARMin.XDirect.dstGA & 0xFFFF));
+ vex_printf("movt r12,0x%x; ",
+ (UInt)((i->ARMin.XDirect.dstGA >> 16) & 0xFFFF));
+ vex_printf("str r12,");
+ ppARMAMode1(i->ARMin.XDirect.amR15T);
+ vex_printf("; movw r12,LO16($disp_cp_chain_me_to_%sEP); ",
+ i->ARMin.XDirect.toFastEP ? "fast" : "slow");
+ vex_printf("movt r12,HI16($disp_cp_chain_me_to_%sEP); ",
+ i->ARMin.XDirect.toFastEP ? "fast" : "slow");
+ vex_printf("blx r12 }");
+ return;
+ case ARMin_XIndir:
+ vex_printf("(xIndir) ");
+ vex_printf("if (%%cpsr.%s) { ",
+ showARMCondCode(i->ARMin.XIndir.cond));
+ vex_printf("str ");
+ ppHRegARM(i->ARMin.XIndir.dstGA);
+ vex_printf(",");
+ ppARMAMode1(i->ARMin.XIndir.amR15T);
+ vex_printf("; movw r12,LO16($disp_cp_xindir); ");
+ vex_printf("movt r12,HI16($disp_cp_xindir); ");
+ vex_printf("blx r12 }");
+ return;
+ case ARMin_XAssisted:
+ vex_printf("(xAssisted) ");
+ vex_printf("if (%%cpsr.%s) { ",
+ showARMCondCode(i->ARMin.XAssisted.cond));
+ vex_printf("str ");
+ ppHRegARM(i->ARMin.XAssisted.dstGA);
+ vex_printf(",");
+ ppARMAMode1(i->ARMin.XAssisted.amR15T);
+ vex_printf("movw r8,$IRJumpKind_to_TRCVAL(%d); ",
+ (Int)i->ARMin.XAssisted.jk);
+ vex_printf("movw r12,LO16($disp_cp_xassisted); ");
+ vex_printf("movt r12,HI16($disp_cp_xassisted); ");
+ vex_printf("blx r12 }");
return;
case ARMin_CMov:
vex_printf("mov%s ", showARMCondCode(i->ARMin.CMov.cond));
@@ -1761,8 +1815,7 @@
}
return;
case ARMin_MFence:
- vex_printf("mfence (mcr 15,0,r0,c7,c10,4; 15,0,r0,c7,c10,5; "
- "15,0,r0,c7,c5,4)");
+ vex_printf("(mfence) dsb sy; dmb sy; isb");
return;
case ARMin_CLREX:
vex_printf("clrex");
@@ -1878,6 +1931,25 @@
vex_printf(", ");
vex_printf("%d", i->ARMin.Add32.imm32);
return;
+ case ARMin_EvCheck:
+ vex_printf("(evCheck) ldr r12,");
+ ppARMAMode1(i->ARMin.EvCheck.amCounter);
+ vex_printf("; subs r12,r12,$1; str r12,");
+ ppARMAMode1(i->ARMin.EvCheck.amCounter);
+ vex_printf("; bpl nofail; ldr r12,");
+ ppARMAMode1(i->ARMin.EvCheck.amFailAddr);
+ vex_printf("; bx r12; nofail:");
+ return;
+ case ARMin_ProfInc:
+ vex_printf("(profInc) movw r12,LO16($NotKnownYet); "
+ "movw r12,HI16($NotKnownYet); "
+ "ldr r11,[r12]; "
+ "adds r11,r11,$1; "
+ "str r11,[r12]; "
+ "ldr r11,[r12+4]; "
+ "adc r11,r11,$0; "
+ "str r11,[r12+4]");
+ return;
default:
unhandled:
vex_printf("ppARMInstr: unhandled case (tag %d)", (Int)i->tag);
@@ -1945,18 +2017,21 @@
return;
case ARMin_Ld8S:
goto unhandled;
- case ARMin_Goto:
- /* reads the reg holding the next guest addr */
- addHRegUse(u, HRmRead, i->ARMin.Goto.gnext);
- /* writes it to the standard integer return register */
- addHRegUse(u, HRmWrite, hregARM_R0());
- /* possibly messes with the baseblock pointer */
- if (i->ARMin.Goto.jk != Ijk_Boring
- && i->ARMin.Goto.jk != Ijk_Call
- && i->ARMin.Goto.jk != Ijk_Ret)
- /* note, this is irrelevant since r8 is not actually
- available to the allocator. But still .. */
- addHRegUse(u, HRmWrite, hregARM_R8());
+ /* XDirect/XIndir/XAssisted are also a bit subtle. They
+ conditionally exit the block. Hence we only need to list (1)
+ the registers that they read, and (2) the registers that they
+ write in the case where the block is not exited. (2) is
+ empty, hence only (1) is relevant here. */
+ case ARMin_XDirect:
+ addRegUsage_ARMAMode1(u, i->ARMin.XDirect.amR15T);
+ return;
+ case ARMin_XIndir:
+ addHRegUse(u, HRmRead, i->ARMin.XIndir.dstGA);
+ addRegUsage_ARMAMode1(u, i->ARMin.XIndir.amR15T);
+ return;
+ case ARMin_XAssisted:
+ addHRegUse(u, HRmRead, i->ARMin.XAssisted.dstGA);
+ addRegUsage_ARMAMode1(u, i->ARMin.XAssisted.amR15T);
return;
case ARMin_CMov:
addHRegUse(u, HRmWrite, i->ARMin.CMov.dst);
@@ -2159,6 +2234,18 @@
addHRegUse(u, HRmWrite, i->ARMin.Add32.rD);
addHRegUse(u, HRmRead, i->ARMin.Add32.rN);
return;
+ case ARMin_EvCheck:
+ /* We expect both amodes only to mention r8, so this is in
+ fact pointless, since r8 isn't allocatable, but
+ anyway.. */
+ addRegUsage_ARMAMode1(u, i->ARMin.EvCheck.amCounter);
+ addRegUsage_ARMAMode1(u, i->ARMin.EvCheck.amFailAddr);
+ addHRegUse(u, HRmWrite, hregARM_R12()); /* also unavail to RA */
+ return;
+ case ARMin_ProfInc:
+ addHRegUse(u, HRmWrite, hregARM_R12());
+ addHRegUse(u, HRmWrite, hregARM_R11());
+ return;
unhandled:
default:
ppARMInstr(i);
@@ -2210,8 +2297,18 @@
return;
case ARMin_Ld8S:
goto unhandled;
- case ARMin_Goto:
- i->ARMin.Goto.gnext = lookupHRegRemap(m, i->ARMin.Goto.gnext);
+ case ARMin_XDirect:
+ mapRegs_ARMAMode1(m, i->ARMin.XDirect.amR15T);
+ return;
+ case ARMin_XIndir:
+ i->ARMin.XIndir.dstGA
+ = lookupHRegRemap(m, i->ARMin.XIndir.dstGA);
+ mapRegs_ARMAMode1(m, i->ARMin.XIndir.amR15T);
+ return;
+ case ARMin_XAssisted:
+ i->ARMin.XAssisted.dstGA
+ = lookupHRegRemap(m, i->ARMin.XAssisted.dstGA);
+ mapRegs_ARMAMode1(m, i->ARMin.XAssisted.amR15T);
return;
case ARMin_CMov:
i->ARMin.CMov.dst = lookupHRegRemap(m, i->ARMin.CMov.dst);
@@ -2329,6 +2426,17 @@
case ARMin_Add32:
i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD);
i->ARMin.Add32.rN = lookupHRegRemap(m, i->ARMin.Add32.rN);
+ return;
+ case ARMin_EvCheck:
+ /* We expect both amodes only to mention r8, so this is in
+ fact pointless, since r8 isn't allocatable, but
+ anyway.. */
+ mapRegs_ARMAMode1(m, i->ARMin.EvCheck.amCounter);
+ mapRegs_ARMAMode1(m, i->ARMin.EvCheck.amFailAddr);
+ return;
+ case ARMin_ProfInc:
+ /* hardwires r11 and r12 -- nothing to modify. */
+ return;
unhandled:
default:
ppARMInstr(i);
@@ -2586,6 +2694,9 @@
(((zzx3) & 0xF) << 12) | (((zzx2) & 0xF) << 8) | \
(((zzx1) & 0xF) << 4) | (((zzx0) & 0xF) << 0))
+#define XX______(zzx7,zzx6) \
+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24))
+
/* Generate a skeletal insn that involves an a RI84 shifter operand.
Returns a word which is all zeroes apart from bits 25 and 11..0,
since it is those that encode the shifter operand (at least to the
@@ -2704,10 +2815,92 @@
return p;
}
+/* Get an immediate into a register, using only that register, and
+ generating exactly 2 instructions, regardless of the value of the
+ immediate. This is used when generating sections of code that need
+ to be patched later, so as to guarantee a specific size. */
+static UInt* imm32_to_iregNo_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
+{
+ if (VEX_ARM_ARCHLEVEL(arm_hwcaps) > 6) {
+ /* Generate movw rD, #low16 ; movt rD, #high16. */
+ UInt lo16 = imm32 & 0xFFFF;
+ UInt hi16 = (imm32 >> 16) & 0xFFFF;
+ UInt instr;
+ instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
+ (lo16 >> 8) & 0xF, (lo16 >> 4) & 0xF,
+ lo16 & 0xF);
+ *p++ = instr;
+ instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
+ (hi16 >> 8) & 0xF, (hi16 >> 4) & 0xF,
+ hi16 & 0xF);
+ *p++ = instr;
+ } else {
+ vassert(0); /* lose */
+ }
+ return p;
+}
-Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr* i,
+/* Check whether p points at a 2-insn sequence cooked up by
+ imm32_to_iregNo_EXACTLY2(). */
+static Bool is_imm32_to_iregNo_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
+{
+ if (VEX_ARM_ARCHLEVEL(arm_hwcaps) > 6) {
+ /* Generate movw rD, #low16 ; movt rD, #high16. */
+ UInt lo16 = imm32 & 0xFFFF;
+ UInt hi16 = (imm32 >> 16) & 0xFFFF;
+ UInt i0, i1;
+ i0 = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
+ (lo16 >> 8) & 0xF, (lo16 >> 4) & 0xF,
+ lo16 & 0xF);
+ i1 = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
+ (hi16 >> 8) & 0xF, (hi16 >> 4) & 0xF,
+ hi16 & 0xF);
+ return p[0] == i0 && p[1] == i1;
+ } else {
+ vassert(0); /* lose */
+ }
+}
+
+
+static UInt* do_load_or_store32 ( UInt* p,
+ Bool isLoad, UInt rD, ARMAMode1* am )
+{
+ vassert(rD <= 12);
+ vassert(am->tag == ARMam1_RI); // RR case is not handled
+ UInt bB = 0;
+ UInt bL = isLoad ? 1 : 0;
+ Int simm12;
+ UInt instr, bP;
+ if (am->ARMam1.RI.simm13 < 0) {
+ bP = 0;
+ simm12 = -am->ARMam1.RI.simm13;
+ } else {
+ bP = 1;
+ simm12 = am->ARMam1.RI.simm13;
+ }
+ vassert(simm12 >= 0 && simm12 <= 4095);
+ instr = XXXXX___(X1110,X0101,BITS4(bP,bB,0,bL),
+ iregNo(am->ARMam1.RI.reg),
+ rD);
+ instr |= simm12;
+ *p++ = instr;
+ return p;
+}
+
+
+/* Emit an instruction into buf and return the number of bytes used.
+ Note that buf is not the insn's final place, and therefore it is
+ imperative to emit position-independent code. If the emitted
+ instruction was a profiler inc, set *is_profInc to True, else
+ leave it unchanged. */
+
+Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, ARMInstr* i,
Bool mode64,
- void* dispatch_unassisted, void* dispatch_assisted )
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted )
{
UInt* p = (UInt*)buf;
vassert(nbuf >= 32);
@@ -2894,61 +3087,177 @@
}
case ARMin_Ld8S:
goto bad;
- case ARMin_Goto: {
- UInt instr;
- IRJumpKind jk = i->ARMin.Goto.jk;
- ARMCondCode cond = i->ARMin.Goto.cond;
- UInt rnext = iregNo(i->ARMin.Goto.gnext);
- Int trc = -1;
- /* since we branch to lr(r13) to get back to dispatch: */
- vassert(dispatch_unassisted == NULL);
- vassert(dispatch_assisted == NULL);
- switch (jk) {
- case Ijk_Ret: case Ijk_Call: case Ijk_Boring:
- break; /* no need to set GST in these common cases */
- case Ijk_ClientReq:
- trc = VEX_TRC_JMP_CLIENTREQ; break;
- case Ijk_Sys_int128:
- case Ijk_Sys_int129:
- case Ijk_Sys_int130:
- case Ijk_Yield:
- case Ijk_EmWarn:
- case Ijk_MapFail:
- goto unhandled_jk;
- case Ijk_YieldNoRedir:
- trc = VEX_TRC_JMP_YIELD_NOREDIR; break;
- case Ijk_NoDecode:
- trc = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval:
- trc = VEX_TRC_JMP_TINVAL; break;
- case Ijk_NoRedir:
- trc = VEX_TRC_JMP_NOREDIR; break;
- case Ijk_Sys_sysenter:
- case Ijk_SigTRAP:
- case Ijk_SigSEGV:
- goto unhandled_jk;
- case Ijk_Sys_syscall:
- trc = VEX_TRC_JMP_SYS_SYSCALL; break;
- unhandled_jk:
- default:
- goto bad;
+
+ case ARMin_XDirect: {
+ /* NB: what goes on here has to be very closely coordinated
+ with the chainXDirect_ARM and unchainXDirect_ARM below. */
+ /* We're generating chain-me requests here, so we need to be
+ sure this is actually allowed -- no-redir translations
+ can't use chain-me's. Hence: */
+ vassert(disp_cp_chain_me_to_slowEP != NULL);
+ vassert(disp_cp_chain_me_to_fastEP != NULL);
+
+ /* Use ptmp for backpatching conditional jumps. */
+ UInt* ptmp = NULL;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. Or at least, leave a space for
+ it that we will shortly fill in. */
+ if (i->ARMin.XDirect.cond != ARMcc_AL) {
+ vassert(i->ARMin.XDirect.cond != ARMcc_NV);
+ ptmp = p;
+ *p++ = 0;
}
- if (trc != -1) {
- // mov{cond} r8, #trc
- vassert(trc >= 0 && trc <= 255);
- instr = (cond << 28) | 0x03A08000 | (0xFF & (UInt)trc);
- *p++ = instr;
+
+ /* Update the guest R15T. */
+ /* movw r12, lo16(dstGA) */
+ /* movt r12, hi16(dstGA) */
+ /* str r12, amR15T */
+ p = imm32_to_iregNo(p, /*r*/12, i->ARMin.XDirect.dstGA);
+ p = do_load_or_store32(p, False/*!isLoad*/,
+ /*r*/12, i->ARMin.XDirect.amR15T);
+
+ /* --- FIRST PATCHABLE BYTE follows --- */
+ /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're
+ calling to) backs up the return address, so as to find the
+ address of the first patchable byte. So: don't change the
+ number of instructions (3) below. */
+ /* movw r12, lo16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */
+ /* movt r12, hi16(VG_(disp_cp_chain_me_to_{slowEP,fastEP})) */
+ /* blx r12 (A1) */
+ void* disp_cp_chain_me
+ = i->ARMin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
+ : disp_cp_chain_me_to_slowEP;
+ p = imm32_to_iregNo_EXACTLY2(p, /*r*/12,
+ (UInt)Ptr_to_ULong(disp_cp_chain_me));
+ *p++ = 0xE12FFF3C;
+ /* --- END of PATCHABLE BYTES --- */
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->ARMin.XDirect.cond != ARMcc_AL) {
+ Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */
+ vassert(delta > 0 && delta < 40);
+ vassert((delta & 3) == 0);
+ UInt notCond = 1 ^ (UInt)i->ARMin.XDirect.cond;
+ vassert(notCond <= 13); /* Neither AL nor NV */
+ delta = (delta >> 2) - 2;
+ *ptmp = XX______(notCond, X1010) | (delta & 0xFFFFFF);
}
- // mov{cond} r0, rnext
- if (rnext != 0) {
- instr = (cond << 28) | 0x01A00000 | rnext;
- *p++ = instr;
- }
- // bx{cond} r14
- instr =(cond << 28) | 0x012FFF1E;
- *p++ = instr;
goto done;
}
+
+ case ARMin_XIndir: {
+ /* We're generating transfers that could lead indirectly to a
+ chain-me, so we need to be sure this is actually allowed
+ -- no-redir translations are not allowed to reach normal
+ translations without going through the scheduler. That
+ means no XDirects or XIndirs out from no-redir
+ translations. Hence: */
+ vassert(disp_cp_xindir != NULL);
+
+ /* Use ptmp for backpatching conditional jumps. */
+ UInt* ptmp = NULL;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. Or at least, leave a space for
+ it that we will shortly fill in. */
+ if (i->ARMin.XIndir.cond != ARMcc_AL) {
+ vassert(i->ARMin.XIndir.cond != ARMcc_NV);
+ ptmp = p;
+ *p++ = 0;
+ }
+
+ /* Update the guest R15T. */
+ /* str r-dstGA, amR15T */
+ p = do_load_or_store32(p, False/*!isLoad*/,
+ iregNo(i->ARMin.XIndir.dstGA),
+ i->ARMin.XIndir.amR15T);
+
+ /* movw r12, lo16(VG_(disp_cp_xindir)) */
+ /* movt r12, hi16(VG_(disp_cp_xindir)) */
+ /* bx r12 (A1) */
+ p = imm32_to_iregNo(p, /*r*/12,
+ (UInt)Ptr_to_ULong(disp_cp_xindir));
+ *p++ = 0xE12FFF1C;
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->ARMin.XIndir.cond != ARMcc_AL) {
+ Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */
+ vassert(delta > 0 && delta < 40);
+ vassert((delta & 3) == 0);
+ UInt notCond = 1 ^ (UInt)i->ARMin.XIndir.cond;
+ vassert(notCond <= 13); /* Neither AL nor NV */
+ delta = (delta >> 2) - 2;
+ *ptmp = XX______(notCond, X1010) | (delta & 0xFFFFFF);
+ }
+ goto done;
+ }
+
+ case ARMin_XAssisted: {
+ /* Use ptmp for backpatching conditional jumps. */
+ UInt* ptmp = NULL;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. Or at least, leave a space for
+ it that we will shortly fill in. */
+ if (i->ARMin.XAssisted.cond != ARMcc_AL) {
+ vassert(i->ARMin.XAssisted.cond != ARMcc_NV);
+ ptmp = p;
+ *p++ = 0;
+ }
+
+ /* Update the guest R15T. */
+ /* str r-dstGA, amR15T */
+ p = do_load_or_store32(p, False/*!isLoad*/,
+ iregNo(i->ARMin.XAssisted.dstGA),
+ i->ARMin.XAssisted.amR15T);
+
+ /* movw r8, $magic_number */
+ UInt trcval = 0;
+ switch (i->ARMin.XAssisted.jk) {
+ case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break;
+ case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break;
+ //case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break;
+ //case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break;
+ //case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
+ //case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
+ case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
+ case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
+ //case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
+ //case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
+ case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break;
+ /* We don't expect to see the following being assisted. */
+ //case Ijk_Ret:
+ //case Ijk_Call:
+ /* fallthrough */
+ default:
+ ppIRJumpKind(i->ARMin.XAssisted.jk);
+ vpanic("emit_ARMInstr.ARMin_XAssisted: unexpected jump kind");
+ }
+ vassert(trcval != 0);
+ p = imm32_to_iregNo(p, /*r*/8, trcval);
+
+ /* movw r12, lo16(VG_(disp_cp_xassisted)) */
+ /* movt r12, hi16(VG_(disp_cp_xassisted)) */
+ /* bx r12 (A1) */
+ p = imm32_to_iregNo(p, /*r*/12,
+ (UInt)Ptr_to_ULong(disp_cp_xassisted));
+ *p++ = 0xE12FFF1C;
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->ARMin.XAssisted.cond != ARMcc_AL) {
+ Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */
+ vassert(delta > 0 && delta < 40);
+ vassert((delta & 3) == 0);
+ UInt notCond = 1 ^ (UInt)i->ARMin.XAssisted.cond;
+ vassert(notCond <= 13); /* Neither AL nor NV */
+ delta = (delta >> 2) - 2;
+ *ptmp = XX______(notCond, X1010) | (delta & 0xFFFFFF);
+ }
+ goto done;
+ }
+
case ARMin_CMov: {
UInt instr = skeletal_RI84(i->ARMin.CMov.src);
UInt subopc = X1101; /* MOV */
@@ -3295,9 +3604,15 @@
goto bad; // FPSCR -> iReg case currently ATC
}
case ARMin_MFence: {
- *p++ = 0xEE070F9A; /* mcr 15,0,r0,c7,c10,4 (DSB) */
- *p++ = 0xEE070FBA; /* mcr 15,0,r0,c7,c10,5 (DMB) */
- *p++ = 0xEE070F95; /* mcr 15,0,r0,c7,c5,4 (ISB) */
+ // It's not clear (to me) how these relate to the ARMv7
+ // versions, so let's just use the v7 versions as they
+ // are at least well documented.
+ //*p++ = 0xEE070F9A; /* mcr 15,0,r0,c7,c10,4 (DSB) */
+ //*p++ = 0xEE070FBA; /* mcr 15,0,r0,c7,c10,5 (DMB) */
+ //*p++ = 0xEE070F95; /* mcr 15,0,r0,c7,c5,4 (ISB) */
+ *p++ = 0xF57FF04F; /* DSB sy */
+ *p++ = 0xF57FF05F; /* DMB sy */
+ *p++ = 0xF57FF06F; /* ISB */
goto done;
}
case ARMin_CLREX: {
@@ -4101,6 +4416,62 @@
*p++ = insn;
goto done;
}
+
+ case ARMin_EvCheck: {
+ /* We generate:
+ ldr r12, [r8 + #4] 4 == offsetof(host_EvC_COUNTER)
+ subs r12, r12, #1 (A1)
+ str r12, [r8 + #4] 4 == offsetof(host_EvC_COUNTER)
+ bpl nofail
+ ldr r12, [r8 + #0] 0 == offsetof(host_EvC_FAILADDR)
+ bx r12
+ nofail:
+ */
+ UInt* p0 = p;
+ p = do_load_or_store32(p, True/*isLoad*/, /*r*/12,
+ i->ARMin.EvCheck.amCounter);
+ *p++ = 0xE25CC001; /* subs r12, r12, #1 */
+ p = do_load_or_store32(p, False/*!isLoad*/, /*r*/12,
+ i->ARMin.EvCheck.amCounter);
+ *p++ = 0x5A000001; /* bpl nofail */
+ p = do_load_or_store32(p, True/*isLoad*/, /*r*/12,
+ i->ARMin.EvCheck.amFailAddr);
+ *p++ = 0xE12FFF1C; /* bx r12 */
+ /* nofail: */
+
+ /* Crosscheck */
+ vassert(evCheckSzB_ARM() == (UChar*)p - (UChar*)p0);
+ goto done;
+ }
+
+ case ARMin_ProfInc: {
+ /* We generate:
+ (ctrP is unknown now, so use 0x65556555 in the
+ expectation that a later call to LibVEX_patchProfCtr
+ will be used to fill in the immediate fields once the
+ right value is known.)
+ movw r12, lo16(0x65556555)
+ movt r12, lo16(0x65556555)
+ ldr r11, [r12]
+ adds r11, r11, #1
+ str r11, [r12]
+ ldr r11, [r12+4]
+ adc r11, r11, #0
+ str r11, [r12+4]
+ */
+ p = imm32_to_iregNo_EXACTLY2(p, /*r*/12, 0x65556555);
+ *p++ = 0xE59CB000;
+ *p++ = 0xE29BB001;
+ *p++ = 0xE58CB000;
+ *p++ = 0xE59CB004;
+ *p++ = 0xE2ABB000;
+ *p++ = 0xE58CB004;
+ /* Tell the caller .. */
+ vassert(!(*is_profInc));
+ *is_profInc = True;
+ goto done;
+ }
+
/* ... */
default:
goto bad;
@@ -4116,6 +4487,179 @@
return ((UChar*)p) - &buf[0];
}
+
+/* How big is an event check? See case for ARMin_EvCheck in
+ emit_ARMInstr just above. That crosschecks what this returns, so
+ we can tell if we're inconsistent. */
+Int evCheckSzB_ARM ( void )
+{
+ return 24;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange chainXDirect_ARM ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to )
+{
+ /* What we're expecting to see is:
+ movw r12, lo16(disp_cp_chain_me_to_EXPECTED)
+ movt r12, hi16(disp_cp_chain_me_to_EXPECTED)
+ blx r12
+ viz
+ <8 bytes generated by imm32_to_iregNo_EXACTLY2>
+ E1 2F FF 3C
+ */
+ UInt* p = (UInt*)place_to_chain;
+ vassert(0 == (3 & (HWord)p));
+ vassert(is_imm32_to_iregNo_EXACTLY2(
+ p, /*r*/12, (UInt)Ptr_to_ULong(disp_cp_chain_me_EXPECTED)));
+ vassert(p[2] == 0xE12FFF3C);
+ /* And what we want to change it to is either:
+ (general case)
+ movw r12, lo16(place_to_jump_to)
+ movt r12, hi16(place_to_jump_to)
+ bx r12
+ viz
+ <8 bytes generated by imm32_to_iregNo_EXACTLY2>
+ E1 2F FF 1C
+ ---OR---
+ in the case where the displacement falls within 26 bits
+ b disp24; undef; undef
+ viz
+ EA <3 bytes == disp24>
+ FF 00 00 00
+ FF 00 00 00
+
+ In both cases the replacement has the same length as the original.
+ To remain sane & verifiable,
+ (1) limit the displacement for the short form to
+ (say) +/- 30 million, so as to avoid wraparound
+ off-by-ones
+ (2) even if the short form is applicable, once every (say)
+ 1024 times use the long form anyway, so as to maintain
+ verifiability
+ */
+
+ /* This is the delta we need to put into a B insn. It's relative
+ to the start of the next-but-one insn, hence the -8. */
+ Long delta = (Long)((UChar*)place_to_jump_to - (UChar*)p) - (Long)8;
+ Bool shortOK = delta >= -30*1000*1000 && delta < 30*1000*1000;
+ vassert(0 == (delta & (Long)3));
+
+ static UInt shortCTR = 0; /* DO NOT MAKE NON-STATIC */
+ if (shortOK) {
+ shortCTR++; // thread safety bleh
+ if (0 == (shortCTR & 0x3FF)) {
+ shortOK = False;
+ if (0)
+ vex_printf("QQQ chainXDirect_ARM: shortCTR = %u, "
+ "using long form\n", shortCTR);
+ }
+ }
+
+ /* And make the modifications. */
+ if (shortOK) {
+ Int simm24 = (Int)(delta >> 2);
+ vassert(simm24 == ((simm24 << 8) >> 8));
+ p[0] = 0xEA000000 | (simm24 & 0x00FFFFFF);
+ p[1] = 0xFF000000;
+ p[2] = 0xFF000000;
+ } else {
+ (void)imm32_to_iregNo_EXACTLY2(
+ p, /*r*/12, (UInt)Ptr_to_ULong(place_to_jump_to));
+ p[2] = 0xE12FFF1C;
+ }
+
+ VexInvalRange vir = {(HWord)p, 12};
+ return vir;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange unchainXDirect_ARM ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me )
+{
+ /* What we're expecting to see is:
+ (general case)
+ movw r12, lo16(place_to_jump_to_EXPECTED)
+ movt r12, lo16(place_to_jump_to_EXPECTED)
+ bx r12
+ viz
+ <8 bytes generated by imm32_to_iregNo_EXACTLY2>
+ E1 2F FF 1C
+ ---OR---
+ in the case where the displacement falls within 26 bits
+ b disp24; undef; undef
+ viz
+ EA <3 bytes == disp24>
+ FF 00 00 00
+ FF 00 00 00
+ */
+ UInt* p = (UInt*)place_to_unchain;
+ vassert(0 == (3 & (HWord)p));
+
+ Bool valid = False;
+ if (is_imm32_to_iregNo_EXACTLY2(
+ p, /*r*/12, (UInt)Ptr_to_ULong(place_to_jump_to_EXPECTED))
+ && p[2] == 0xE12FFF1C) {
+ valid = True; /* it's the long form */
+ if (0)
+ vex_printf("QQQ unchainXDirect_ARM: found long form\n");
+ } else
+ if ((p[0] >> 24) == 0xEA && p[1] == 0xFF000000 && p[2] == 0xFF000000) {
+ /* It's the short form. Check the displacement is right. */
+ Int simm24 = p[0] & 0x00FFFFFF;
+ simm24 <<= 8; simm24 >>= 8;
+ if ((UChar*)p + (simm24 << 2) + 8 == (UChar*)place_to_jump_to_EXPECTED) {
+ valid = True;
+ if (0)
+ vex_printf("QQQ unchainXDirect_ARM: found short form\n");
+ }
+ }
+ vassert(valid);
+
+ /* And what we want to change it to is:
+ movw r12, lo16(disp_cp_chain_me)
+ movt r12, hi16(disp_cp_chain_me)
+ blx r12
+ viz
+ <8 bytes generated by imm32_to_iregNo_EXACTLY2>
+ E1 2F FF 3C
+ */
+ (void)imm32_to_iregNo_EXACTLY2(
+ p, /*r*/12, (UInt)Ptr_to_ULong(disp_cp_chain_me));
+ p[2] = 0xE12FFF3C;
+ VexInvalRange vir = {(HWord)p, 12};
+ return vir;
+}
+
+
+/* Patch the counter address into a profile inc point, as previously
+ created by the ARMin_ProfInc case for emit_ARMInstr. */
+VexInvalRange patchProfInc_ARM ( void* place_to_patch,
+ ULong* location_of_counter )
+{
+ vassert(sizeof(ULong*) == 4);
+ UInt* p = (UInt*)place_to_patch;
+ vassert(0 == (3 & (HWord)p));
+ vassert(is_imm32_to_iregNo_EXACTLY2(p, /*r*/12, 0x65556555));
+ vassert(p[2] == 0xE59CB000);
+ vassert(p[3] == 0xE29BB001);
+ vassert(p[4] == 0xE58CB000);
+ vassert(p[5] == 0xE59CB004);
+ vassert(p[6] == 0xE2ABB000);
+ vassert(p[7] == 0xE58CB004);
+ imm32_to_iregNo_EXACTLY2(p, /*r*/12,
+ (UInt)Ptr_to_ULong(location_of_counter));
+ VexInvalRange vir = {(HWord)p, 8};
+ return vir;
+}
+
+
#undef BITS4
#undef X0000
#undef X0001
@@ -4138,6 +4682,7 @@
#undef XXX___XX
#undef XXXXX__X
#undef XXXXXXXX
+#undef XX______
/*---------------------------------------------------------------*/
/*--- end host_arm_defs.c ---*/
diff --git a/main/VEX/priv/host_arm_defs.h b/main/VEX/priv/host_arm_defs.h
index 0dea3f5..91a6757 100644
--- a/main/VEX/priv/host_arm_defs.h
+++ b/main/VEX/priv/host_arm_defs.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -564,7 +564,9 @@
ARMin_LdSt16,
ARMin_LdSt8U,
ARMin_Ld8S,
- ARMin_Goto,
+ ARMin_XDirect, /* direct transfer to GA */
+ ARMin_XIndir, /* indirect transfer to GA */
+ ARMin_XAssisted, /* assisted transfer to GA */
ARMin_CMov,
ARMin_Call,
ARMin_Mul,
@@ -604,9 +606,10 @@
allocator demands them to consist of no more than two instructions.
We will split this instruction into 2 or 3 ARM instructions on the
emiting phase.
-
NOTE: source and destination registers should be different! */
- ARMin_Add32
+ ARMin_Add32,
+ ARMin_EvCheck, /* Event check */
+ ARMin_ProfInc /* 64-bit profile counter increment */
}
ARMInstrTag;
@@ -676,13 +679,30 @@
HReg rD;
ARMAMode2* amode;
} Ld8S;
- /* Pseudo-insn. Go to guest address gnext, on given
- condition, which could be ARMcc_AL. */
+ /* Update the guest R15T value, then exit requesting to chain
+ to it. May be conditional. Urr, use of Addr32 implicitly
+ assumes that wordsize(guest) == wordsize(host). */
struct {
+ Addr32 dstGA; /* next guest address */
+ ARMAMode1* amR15T; /* amode in guest state for R15T */
+ ARMCondCode cond; /* can be ARMcc_AL */
+ Bool toFastEP; /* chain to the slow or fast point? */
+ } XDirect;
+ /* Boring transfer to a guest address not known at JIT time.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ ARMAMode1* amR15T;
+ ARMCondCode cond; /* can be ARMcc_AL */
+ } XIndir;
+ /* Assisted transfer to a guest address, most general case.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ ARMAMode1* amR15T;
+ ARMCondCode cond; /* can be ARMcc_AL */
IRJumpKind jk;
- ARMCondCode cond;
- HReg gnext;
- } Goto;
+ } XAssisted;
/* Mov src to dst on the given condition, which may not
be ARMcc_AL. */
struct {
@@ -905,6 +925,15 @@
HReg rN;
UInt imm32;
} Add32;
+ struct {
+ ARMAMode1* amCounter;
+ ARMAMode1* amFailAddr;
+ } EvCheck;
+ struct {
+ /* No fields. The address of the counter to inc is
+ installed later, post-translation, by patching it in,
+ as it is not known at translation time. */
+ } ProfInc;
} ARMin;
}
ARMInstr;
@@ -921,7 +950,12 @@
HReg, ARMAMode2* );
extern ARMInstr* ARMInstr_LdSt8U ( Bool isLoad, HReg, ARMAMode1* );
extern ARMInstr* ARMInstr_Ld8S ( HReg, ARMAMode2* );
-extern ARMInstr* ARMInstr_Goto ( IRJumpKind, ARMCondCode, HReg gnext );
+extern ARMInstr* ARMInstr_XDirect ( Addr32 dstGA, ARMAMode1* amR15T,
+ ARMCondCode cond, Bool toFastEP );
+extern ARMInstr* ARMInstr_XIndir ( HReg dstGA, ARMAMode1* amR15T,
+ ARMCondCode cond );
+extern ARMInstr* ARMInstr_XAssisted ( HReg dstGA, ARMAMode1* amR15T,
+ ARMCondCode cond, IRJumpKind jk );
extern ARMInstr* ARMInstr_CMov ( ARMCondCode, HReg dst, ARMRI84* src );
extern ARMInstr* ARMInstr_Call ( ARMCondCode, HWord, Int nArgRegs );
extern ARMInstr* ARMInstr_Mul ( ARMMulOp op );
@@ -957,6 +991,9 @@
extern ARMInstr* ARMInstr_NeonImm ( HReg, ARMNImm* );
extern ARMInstr* ARMInstr_NCMovQ ( ARMCondCode, HReg, HReg );
extern ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 );
+extern ARMInstr* ARMInstr_EvCheck ( ARMAMode1* amCounter,
+ ARMAMode1* amFailAddr );
+extern ARMInstr* ARMInstr_ProfInc ( void );
extern void ppARMInstr ( ARMInstr* );
@@ -966,10 +1003,13 @@
extern void getRegUsage_ARMInstr ( HRegUsage*, ARMInstr*, Bool );
extern void mapRegs_ARMInstr ( HRegRemap*, ARMInstr*, Bool );
extern Bool isMove_ARMInstr ( ARMInstr*, HReg*, HReg* );
-extern Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr*,
- Bool,
- void* dispatch_unassisted,
- void* dispatch_assisted );
+extern Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, ARMInstr* i,
+ Bool mode64,
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted );
extern void genSpill_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
HReg rreg, Int offset, Bool );
@@ -977,8 +1017,34 @@
HReg rreg, Int offset, Bool );
extern void getAllocableRegs_ARM ( Int*, HReg** );
-extern HInstrArray* iselSB_ARM ( IRSB*, VexArch,
- VexArchInfo*, VexAbiInfo* );
+extern HInstrArray* iselSB_ARM ( IRSB*,
+ VexArch,
+ VexArchInfo*,
+ VexAbiInfo*,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga );
+
+/* How big is an event check? This is kind of a kludge because it
+ depends on the offsets of host_EvC_FAILADDR and
+ host_EvC_COUNTER. */
+extern Int evCheckSzB_ARM ( void );
+
+/* Perform a chaining and unchaining of an XDirect jump. */
+extern VexInvalRange chainXDirect_ARM ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to );
+
+extern VexInvalRange unchainXDirect_ARM ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me );
+
+/* Patch the counter location into an existing ProfInc point. */
+extern VexInvalRange patchProfInc_ARM ( void* place_to_patch,
+ ULong* location_of_counter );
+
#endif /* ndef __VEX_HOST_ARM_DEFS_H */
diff --git a/main/VEX/priv/host_arm_isel.c b/main/VEX/priv/host_arm_isel.c
index e695567..62739fd 100644
--- a/main/VEX/priv/host_arm_isel.c
+++ b/main/VEX/priv/host_arm_isel.c
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
NEON support is
- Copyright (C) 2010-2011 Samsung Electronics
+ Copyright (C) 2010-2012 Samsung Electronics
contributed by Dmitry Zhurikhin <zhur@ispras.ru>
and Kirill Batuzov <batuzovk@ispras.ru>
@@ -84,9 +84,6 @@
32-bit virtual HReg, which holds the high half
of the value.
- - The name of the vreg in which we stash a copy of the link reg, so
- helper functions don't kill it.
-
- The code array, that is, the insns selected so far.
- A counter, for generating new virtual registers.
@@ -94,23 +91,38 @@
- The host hardware capabilities word. This is set at the start
and does not change.
- Note, this is all host-independent. */
+ - A Bool for indicating whether we may generate chain-me
+ instructions for control flow transfers, or whether we must use
+ XAssisted.
+
+ - The maximum guest address of any guest insn in this block.
+ Actually, the address of the highest-addressed byte from any insn
+ in this block. Is set at the start and does not change. This is
+ used for detecting jumps which are definitely forward-edges from
+ this block, and therefore can be made (chained) to the fast entry
+ point of the destination, thereby avoiding the destination's
+ event check.
+
+ Note, this is all (well, mostly) host-independent.
+*/
typedef
struct {
+ /* Constant -- are set at the start and do not change. */
IRTypeEnv* type_env;
HReg* vregmap;
HReg* vregmapHI;
Int n_vregmap;
- HReg savedLR;
-
- HInstrArray* code;
-
- Int vreg_ctr;
-
UInt hwcaps;
+
+ Bool chainingAllowed;
+ Addr64 max_ga;
+
+ /* These are modified as we go along. */
+ HInstrArray* code;
+ Int vreg_ctr;
}
ISelEnv;
@@ -1121,14 +1133,15 @@
//zz /* --------- TERNARY OP --------- */
//zz case Iex_Triop: {
+//zz IRTriop *triop = e->Iex.Triop.details;
//zz /* C3210 flags following FPU partial remainder (fprem), both
//zz IEEE compliant (PREM1) and non-IEEE compliant (PREM). */
-//zz if (e->Iex.Triop.op == Iop_PRemC3210F64
-//zz || e->Iex.Triop.op == Iop_PRem1C3210F64) {
+//zz if (triop->op == Iop_PRemC3210F64
+//zz || triop->op == Iop_PRem1C3210F64) {
//zz HReg junk = newVRegF(env);
//zz HReg dst = newVRegI(env);
-//zz HReg srcL = iselDblExpr(env, e->Iex.Triop.arg2);
-//zz HReg srcR = iselDblExpr(env, e->Iex.Triop.arg3);
+//zz HReg srcL = iselDblExpr(env, triop->arg2);
+//zz HReg srcR = iselDblExpr(env, triop->arg3);
//zz /* XXXROUNDINGFIXME */
//zz /* set roundingmode here */
//zz addInstr(env, X86Instr_FpBinary(
@@ -1262,7 +1275,7 @@
|| e->Iex.Binop.op == Iop_GetElem16x4
|| e->Iex.Binop.op == Iop_GetElem32x2) {
HReg res = newVRegI(env);
- HReg arg = iselNeon64Expr(env, e->Iex.Triop.arg1);
+ HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1);
UInt index, size;
if (e->Iex.Binop.arg2->tag != Iex_Const ||
typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
@@ -1287,7 +1300,7 @@
|| e->Iex.Binop.op == Iop_GetElem16x8
|| e->Iex.Binop.op == Iop_GetElem32x4) {
HReg res = newVRegI(env);
- HReg arg = iselNeonExpr(env, e->Iex.Triop.arg1);
+ HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1);
UInt index, size;
if (e->Iex.Binop.arg2->tag != Iex_Const ||
typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
@@ -1349,6 +1362,12 @@
fn = &h_generic_calc_QSub8Ux4; break;
case Iop_Sad8Ux4:
fn = &h_generic_calc_Sad8Ux4; break;
+ case Iop_QAdd32S:
+ fn = &h_generic_calc_QAdd32S; break;
+ case Iop_QSub32S:
+ fn = &h_generic_calc_QSub32S; break;
+ case Iop_QSub16Ux2:
+ fn = &h_generic_calc_QSub16Ux2; break;
default:
break;
}
@@ -1514,7 +1533,7 @@
}
case Iop_64to8: {
HReg rHi, rLo;
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
HReg tHi = newVRegI(env);
HReg tLo = newVRegI(env);
HReg tmp = iselNeon64Expr(env, e->Iex.Unop.arg);
@@ -1819,7 +1838,7 @@
/* read 64-bit IRTemp */
if (e->tag == Iex_RdTmp) {
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
HReg tHi = newVRegI(env);
HReg tLo = newVRegI(env);
HReg tmp = iselNeon64Expr(env, e);
@@ -2028,7 +2047,7 @@
/* It is convenient sometimes to call iselInt64Expr even when we
have NEON support (e.g. in do_helper_call we need 64-bit
arguments as 2 x 32 regs). */
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
HReg tHi = newVRegI(env);
HReg tLo = newVRegI(env);
HReg tmp = iselNeon64Expr(env, e);
@@ -3585,18 +3604,20 @@
} /* if (e->tag == Iex_Unop) */
if (e->tag == Iex_Triop) {
- switch (e->Iex.Triop.op) {
+ IRTriop *triop = e->Iex.Triop.details;
+
+ switch (triop->op) {
case Iop_Extract64: {
HReg res = newVRegD(env);
- HReg argL = iselNeon64Expr(env, e->Iex.Triop.arg1);
- HReg argR = iselNeon64Expr(env, e->Iex.Triop.arg2);
+ HReg argL = iselNeon64Expr(env, triop->arg1);
+ HReg argR = iselNeon64Expr(env, triop->arg2);
UInt imm4;
- if (e->Iex.Triop.arg3->tag != Iex_Const ||
- typeOfIRExpr(env->type_env, e->Iex.Triop.arg3) != Ity_I8) {
+ if (triop->arg3->tag != Iex_Const ||
+ typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) {
vpanic("ARM target supports Iop_Extract64 with constant "
"third argument less than 16 only\n");
}
- imm4 = e->Iex.Triop.arg3->Iex.Const.con->Ico.U8;
+ imm4 = triop->arg3->Iex.Const.con->Ico.U8;
if (imm4 >= 8) {
vpanic("ARM target supports Iop_Extract64 with constant "
"third argument less than 16 only\n");
@@ -3609,16 +3630,16 @@
case Iop_SetElem16x4:
case Iop_SetElem32x2: {
HReg res = newVRegD(env);
- HReg dreg = iselNeon64Expr(env, e->Iex.Triop.arg1);
- HReg arg = iselIntExpr_R(env, e->Iex.Triop.arg3);
+ HReg dreg = iselNeon64Expr(env, triop->arg1);
+ HReg arg = iselIntExpr_R(env, triop->arg3);
UInt index, size;
- if (e->Iex.Triop.arg2->tag != Iex_Const ||
- typeOfIRExpr(env->type_env, e->Iex.Triop.arg2) != Ity_I8) {
+ if (triop->arg2->tag != Iex_Const ||
+ typeOfIRExpr(env->type_env, triop->arg2) != Ity_I8) {
vpanic("ARM target supports SetElem with constant "
"second argument only\n");
}
- index = e->Iex.Triop.arg2->Iex.Const.con->Ico.U8;
- switch (e->Iex.Triop.op) {
+ index = triop->arg2->Iex.Const.con->Ico.U8;
+ switch (triop->op) {
case Iop_SetElem8x8: vassert(index < 8); size = 0; break;
case Iop_SetElem16x4: vassert(index < 4); size = 1; break;
case Iop_SetElem32x2: vassert(index < 2); size = 2; break;
@@ -5232,18 +5253,20 @@
}
if (e->tag == Iex_Triop) {
- switch (e->Iex.Triop.op) {
+ IRTriop *triop = e->Iex.Triop.details;
+
+ switch (triop->op) {
case Iop_ExtractV128: {
HReg res = newVRegV(env);
- HReg argL = iselNeonExpr(env, e->Iex.Triop.arg1);
- HReg argR = iselNeonExpr(env, e->Iex.Triop.arg2);
+ HReg argL = iselNeonExpr(env, triop->arg1);
+ HReg argR = iselNeonExpr(env, triop->arg2);
UInt imm4;
- if (e->Iex.Triop.arg3->tag != Iex_Const ||
- typeOfIRExpr(env->type_env, e->Iex.Triop.arg3) != Ity_I8) {
+ if (triop->arg3->tag != Iex_Const ||
+ typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) {
vpanic("ARM target supports Iop_ExtractV128 with constant "
"third argument less than 16 only\n");
}
- imm4 = e->Iex.Triop.arg3->Iex.Const.con->Ico.U8;
+ imm4 = triop->arg3->Iex.Const.con->Ico.U8;
if (imm4 >= 16) {
vpanic("ARM target supports Iop_ExtractV128 with constant "
"third argument less than 16 only\n");
@@ -5339,7 +5362,7 @@
if (e->tag == Iex_Unop) {
switch (e->Iex.Unop.op) {
case Iop_ReinterpI64asF64: {
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
return iselNeon64Expr(env, e->Iex.Unop.arg);
} else {
HReg srcHi, srcLo;
@@ -5400,16 +5423,18 @@
}
if (e->tag == Iex_Triop) {
- switch (e->Iex.Triop.op) {
+ IRTriop *triop = e->Iex.Triop.details;
+
+ switch (triop->op) {
case Iop_DivF64:
case Iop_MulF64:
case Iop_AddF64:
case Iop_SubF64: {
ARMVfpOp op = 0; /*INVALID*/
- HReg argL = iselDblExpr(env, e->Iex.Triop.arg2);
- HReg argR = iselDblExpr(env, e->Iex.Triop.arg3);
+ HReg argL = iselDblExpr(env, triop->arg2);
+ HReg argR = iselDblExpr(env, triop->arg3);
HReg dst = newVRegD(env);
- switch (e->Iex.Triop.op) {
+ switch (triop->op) {
case Iop_DivF64: op = ARMvfp_DIV; break;
case Iop_MulF64: op = ARMvfp_MUL; break;
case Iop_AddF64: op = ARMvfp_ADD; break;
@@ -5543,16 +5568,18 @@
}
if (e->tag == Iex_Triop) {
- switch (e->Iex.Triop.op) {
+ IRTriop *triop = e->Iex.Triop.details;
+
+ switch (triop->op) {
case Iop_DivF32:
case Iop_MulF32:
case Iop_AddF32:
case Iop_SubF32: {
ARMVfpOp op = 0; /*INVALID*/
- HReg argL = iselFltExpr(env, e->Iex.Triop.arg2);
- HReg argR = iselFltExpr(env, e->Iex.Triop.arg3);
+ HReg argL = iselFltExpr(env, triop->arg2);
+ HReg argR = iselFltExpr(env, triop->arg3);
HReg dst = newVRegF(env);
- switch (e->Iex.Triop.op) {
+ switch (triop->op) {
case Iop_DivF32: op = ARMvfp_DIV; break;
case Iop_MulF32: op = ARMvfp_MUL; break;
case Iop_AddF32: op = ARMvfp_ADD; break;
@@ -5631,7 +5658,7 @@
return;
}
if (tyd == Ity_I64) {
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
HReg dD = iselNeon64Expr(env, stmt->Ist.Store.data);
ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr);
addInstr(env, ARMInstr_NLdStD(False, dD, am));
@@ -5680,7 +5707,7 @@
return;
}
if (tyd == Ity_I64) {
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
HReg addr = newVRegI(env);
HReg qD = iselNeon64Expr(env, stmt->Ist.Put.data);
addInstr(env, ARMInstr_Add32(addr, hregARM_R8(),
@@ -5765,7 +5792,7 @@
return;
}
if (ty == Ity_I64) {
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
HReg src = iselNeon64Expr(env, stmt->Ist.WrTmp.data);
HReg dst = lookupIRTemp(env, tmp);
addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, src, 4, False));
@@ -5824,7 +5851,7 @@
retty = typeOfIRTemp(env->type_env, d->tmp);
if (retty == Ity_I64) {
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
HReg tmp = lookupIRTemp(env, d->tmp);
addInstr(env, ARMInstr_VXferD(True, tmp, hregARM_R1(),
hregARM_R0()));
@@ -5878,7 +5905,7 @@
move it into a result register pair. On a NEON capable
CPU, the result register will be a 64 bit NEON
register, so we must move it there instead. */
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
HReg dst = lookupIRTemp(env, res);
addInstr(env, ARMInstr_VXferD(True, dst, hregARM_R3(),
hregARM_R2()));
@@ -5964,15 +5991,56 @@
/* --------- EXIT --------- */
case Ist_Exit: {
- HReg gnext;
- ARMCondCode cc;
if (stmt->Ist.Exit.dst->tag != Ico_U32)
vpanic("isel_arm: Ist_Exit: dst is not a 32-bit value");
- gnext = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
- cc = iselCondCode(env, stmt->Ist.Exit.guard);
- addInstr(env, mk_iMOVds_RR(hregARM_R14(), env->savedLR));
- addInstr(env, ARMInstr_Goto(stmt->Ist.Exit.jk, cc, gnext));
- return;
+
+ ARMCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
+ ARMAMode1* amR15T = ARMAMode1_RI(hregARM_R8(),
+ stmt->Ist.Exit.offsIP);
+
+ /* Case: boring transfer to known address */
+ if (stmt->Ist.Exit.jk == Ijk_Boring
+ || stmt->Ist.Exit.jk == Ijk_Call
+ || stmt->Ist.Exit.jk == Ijk_Ret) {
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = ((Addr32)stmt->Ist.Exit.dst->Ico.U32) > env->max_ga;
+ if (0) vex_printf("%s", toFastEP ? "Y" : ",");
+ addInstr(env, ARMInstr_XDirect(stmt->Ist.Exit.dst->Ico.U32,
+ amR15T, cc, toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, ARMInstr_XAssisted(r, amR15T, cc, Ijk_Boring));
+ }
+ return;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (stmt->Ist.Exit.jk) {
+ /* Keep this list in sync with that in iselNext below */
+ case Ijk_ClientReq:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_Sys_syscall:
+ case Ijk_TInval:
+ {
+ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, ARMInstr_XAssisted(r, amR15T, cc,
+ stmt->Ist.Exit.jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Do we ever expect to see any other kind? */
+ goto stmt_fail;
}
default: break;
@@ -5987,19 +6055,86 @@
/*--- ISEL: Basic block terminators (Nexts) ---*/
/*---------------------------------------------------------*/
-static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk )
+static void iselNext ( ISelEnv* env,
+ IRExpr* next, IRJumpKind jk, Int offsIP )
{
- HReg rDst;
if (vex_traceflags & VEX_TRACE_VCODE) {
- vex_printf("\n-- goto {");
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
ppIRJumpKind(jk);
- vex_printf("} ");
- ppIRExpr(next);
- vex_printf("\n");
+ vex_printf( "\n");
}
- rDst = iselIntExpr_R(env, next);
- addInstr(env, mk_iMOVds_RR(hregARM_R14(), env->savedLR));
- addInstr(env, ARMInstr_Goto(jk, ARMcc_AL, rDst));
+
+ /* Case: boring transfer to known address */
+ if (next->tag == Iex_Const) {
+ IRConst* cdst = next->Iex.Const.con;
+ vassert(cdst->tag == Ico_U32);
+ if (jk == Ijk_Boring || jk == Ijk_Call) {
+ /* Boring transfer to known address */
+ ARMAMode1* amR15T = ARMAMode1_RI(hregARM_R8(), offsIP);
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = ((Addr64)cdst->Ico.U32) > env->max_ga;
+ if (0) vex_printf("%s", toFastEP ? "X" : ".");
+ addInstr(env, ARMInstr_XDirect(cdst->Ico.U32,
+ amR15T, ARMcc_AL,
+ toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg r = iselIntExpr_R(env, next);
+ addInstr(env, ARMInstr_XAssisted(r, amR15T, ARMcc_AL,
+ Ijk_Boring));
+ }
+ return;
+ }
+ }
+
+ /* Case: call/return (==boring) transfer to any address */
+ switch (jk) {
+ case Ijk_Boring: case Ijk_Ret: case Ijk_Call: {
+ HReg r = iselIntExpr_R(env, next);
+ ARMAMode1* amR15T = ARMAMode1_RI(hregARM_R8(), offsIP);
+ if (env->chainingAllowed) {
+ addInstr(env, ARMInstr_XIndir(r, amR15T, ARMcc_AL));
+ } else {
+ addInstr(env, ARMInstr_XAssisted(r, amR15T, ARMcc_AL,
+ Ijk_Boring));
+ }
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (jk) {
+ /* Keep this list in sync with that for Ist_Exit above */
+ case Ijk_ClientReq:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_Sys_syscall:
+ {
+ HReg r = iselIntExpr_R(env, next);
+ ARMAMode1* amR15T = ARMAMode1_RI(hregARM_R8(), offsIP);
+ addInstr(env, ARMInstr_XAssisted(r, amR15T, ARMcc_AL, jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
+ ppIRJumpKind(jk);
+ vex_printf( "\n");
+ vassert(0); // are we expecting any other kind?
}
@@ -6009,21 +6144,27 @@
/* Translate an entire SB to arm code. */
-HInstrArray* iselSB_ARM ( IRSB* bb, VexArch arch_host,
- VexArchInfo* archinfo_host,
- VexAbiInfo* vbi/*UNUSED*/ )
+HInstrArray* iselSB_ARM ( IRSB* bb,
+ VexArch arch_host,
+ VexArchInfo* archinfo_host,
+ VexAbiInfo* vbi/*UNUSED*/,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga )
{
- Int i, j;
- HReg hreg, hregHI;
- ISelEnv* env;
- UInt hwcaps_host = archinfo_host->hwcaps;
- static UInt counter = 0;
+ Int i, j;
+ HReg hreg, hregHI;
+ ISelEnv* env;
+ UInt hwcaps_host = archinfo_host->hwcaps;
+ ARMAMode1 *amCounter, *amFailAddr;
/* sanity ... */
vassert(arch_host == VexArchARM);
/* hwcaps should not change from one ISEL call to another. */
- arm_hwcaps = hwcaps_host;
+ arm_hwcaps = hwcaps_host; // JRS 2012 Mar 31: FIXME (RM)
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
@@ -6041,6 +6182,11 @@
env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
+ /* and finally ... */
+ env->chainingAllowed = chainingAllowed;
+ env->hwcaps = hwcaps_host;
+ env->max_ga = max_ga;
+
/* For each IR temporary, allocate a suitably-kinded virtual
register. */
j = 0;
@@ -6052,7 +6198,7 @@
case Ity_I16:
case Ity_I32: hreg = mkHReg(j++, HRcInt32, True); break;
case Ity_I64:
- if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+ if (hwcaps_host & VEX_HWCAPS_ARM_NEON) {
hreg = mkHReg(j++, HRcFlt64, True);
} else {
hregHI = mkHReg(j++, HRcInt32, True);
@@ -6070,21 +6216,27 @@
}
env->vreg_ctr = j;
- /* Keep a copy of the link reg, since any call to a helper function
- will trash it, and we can't get back to the dispatcher once that
- happens. */
- env->savedLR = newVRegI(env);
- addInstr(env, mk_iMOVds_RR(env->savedLR, hregARM_R14()));
+ /* The very first instruction must be an event check. */
+ amCounter = ARMAMode1_RI(hregARM_R8(), offs_Host_EvC_Counter);
+ amFailAddr = ARMAMode1_RI(hregARM_R8(), offs_Host_EvC_FailAddr);
+ addInstr(env, ARMInstr_EvCheck(amCounter, amFailAddr));
+
+ /* Possibly a block counter increment (for profiling). At this
+ point we don't know the address of the counter, so just pretend
+ it is zero. It will have to be patched later, but before this
+ translation is used, by a call to LibVEX_patchProfCtr. */
+ if (addProfInc) {
+ addInstr(env, ARMInstr_ProfInc());
+ }
/* Ok, finally we can iterate over the statements. */
for (i = 0; i < bb->stmts_used; i++)
- iselStmt(env,bb->stmts[i]);
+ iselStmt(env, bb->stmts[i]);
- iselNext(env,bb->next,bb->jumpkind);
+ iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
/* record the number of vregs we used. */
env->code->n_vregs = env->vreg_ctr;
- counter++;
return env->code;
}
diff --git a/main/VEX/priv/host_generic_reg_alloc2.c b/main/VEX/priv/host_generic_reg_alloc2.c
index 5052d9d..b1bf586 100644
--- a/main/VEX/priv/host_generic_reg_alloc2.c
+++ b/main/VEX/priv/host_generic_reg_alloc2.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -207,10 +207,11 @@
/* Check that this vreg has been assigned a sane spill offset. */
static inline void sanity_check_spill_offset ( VRegLR* vreg )
{
- if (vreg->reg_class == HRcVec128 || vreg->reg_class == HRcFlt64) {
- vassert(0 == ((UShort)vreg->spill_offset % 16));
- } else {
- vassert(0 == ((UShort)vreg->spill_offset % 8));
+ switch (vreg->reg_class) {
+ case HRcVec128: case HRcFlt64:
+ vassert(0 == ((UShort)vreg->spill_offset % 16)); break;
+ default:
+ vassert(0 == ((UShort)vreg->spill_offset % 8)); break;
}
}
@@ -398,14 +399,14 @@
not at each insn processed. */
Bool do_sanity_check;
- vassert(0 == (guest_sizeB % 16));
- vassert(0 == (LibVEX_N_SPILL_BYTES % 16));
- vassert(0 == (N_SPILL64S % 2));
+ vassert(0 == (guest_sizeB % 32));
+ vassert(0 == (LibVEX_N_SPILL_BYTES % 32));
+ vassert(0 == (N_SPILL64S % 4));
/* The live range numbers are signed shorts, and so limiting the
- number of insns to 10000 comfortably guards against them
+ number of insns to 15000 comfortably guards against them
overflowing 32k. */
- vassert(instrs_in->arr_used <= 10000);
+ vassert(instrs_in->arr_used <= 15000);
# define INVALID_INSTRNO (-2)
@@ -790,18 +791,24 @@
/* Each spill slot is 8 bytes long. For vregs which take more than
64 bits to spill (classes Flt64 and Vec128), we have to allocate
- two spill slots.
+ two consecutive spill slots. For 256 bit registers (class
+ Vec256), we have to allocate four consecutive spill slots.
For Vec128-class on PowerPC, the spill slot's actual address
must be 16-byte aligned. Since the spill slot's address is
computed as an offset from the guest state pointer, and since
the user of the generated code must set that pointer to a
- 16-aligned value, we have the residual obligation here of
+ 32-aligned value, we have the residual obligation here of
choosing a 16-aligned spill slot offset for Vec128-class values.
Since each spill slot is 8 bytes long, that means for
Vec128-class values we must allocated a spill slot number which
is zero mod 2.
+ Similarly, for Vec256 calss on amd64, find a spill slot number
+ which is zero mod 4. This guarantees it will be 32 byte
+ aligned, which isn't actually necessary on amd64 (we use movUpd
+ etc to spill), but seems like good practice.
+
Do a rank-based allocation of vregs to spill slot numbers. We
put as few values as possible in spill slots, but nevertheless
need to have a spill slot available for all vregs, just in case.
@@ -821,48 +828,49 @@
}
/* The spill slots are 64 bits in size. As per the comment on
- definition of HRegClass in host_generic_regs.h, that means, to
- spill a vreg of class Flt64 or Vec128, we'll need to find two
- adjacent spill slots to use. Note, this logic needs to kept
- in sync with the size info on the definition of HRegClass. */
+ definition of HRegClass in host_generic_regs.h, that means,
+ to spill a vreg of class Flt64 or Vec128, we'll need to find
+ two adjacent spill slots to use. For Vec256, we'll need to
+ find four adjacent slots to use. Note, this logic needs to
+ kept in sync with the size info on the definition of
+ HRegClass. */
+ switch (vreg_lrs[j].reg_class) {
- if (vreg_lrs[j].reg_class == HRcVec128
- || vreg_lrs[j].reg_class == HRcFlt64) {
+ case HRcVec128: case HRcFlt64:
+ /* Find two adjacent free slots in which between them
+ provide up to 128 bits in which to spill the vreg.
+ Since we are trying to find an even:odd pair, move
+ along in steps of 2 (slots). */
+ for (k = 0; k < N_SPILL64S-1; k += 2)
+ if (ss_busy_until_before[k+0] <= vreg_lrs[j].live_after
+ && ss_busy_until_before[k+1] <= vreg_lrs[j].live_after)
+ break;
+ if (k >= N_SPILL64S-1) {
+ vpanic("LibVEX_N_SPILL_BYTES is too low. "
+ "Increase and recompile.");
+ }
+ if (0) vex_printf("16-byte spill offset in spill slot %d\n",
+ (Int)k);
+ ss_busy_until_before[k+0] = vreg_lrs[j].dead_before;
+ ss_busy_until_before[k+1] = vreg_lrs[j].dead_before;
+ break;
- /* Find two adjacent free slots in which between them provide
- up to 128 bits in which to spill the vreg. Since we are
- trying to find an even:odd pair, move along in steps of 2
- (slots). */
+ default:
+ /* The ordinary case -- just find a single spill slot. */
+ /* Find the lowest-numbered spill slot which is available
+ at the start point of this interval, and assign the
+ interval to it. */
+ for (k = 0; k < N_SPILL64S; k++)
+ if (ss_busy_until_before[k] <= vreg_lrs[j].live_after)
+ break;
+ if (k == N_SPILL64S) {
+ vpanic("LibVEX_N_SPILL_BYTES is too low. "
+ "Increase and recompile.");
+ }
+ ss_busy_until_before[k] = vreg_lrs[j].dead_before;
+ break;
- for (k = 0; k < N_SPILL64S-1; k += 2)
- if (ss_busy_until_before[k] <= vreg_lrs[j].live_after
- && ss_busy_until_before[k+1] <= vreg_lrs[j].live_after)
- break;
- if (k >= N_SPILL64S-1) {
- vpanic("LibVEX_N_SPILL_BYTES is too low. "
- "Increase and recompile.");
- }
- if (0) vex_printf("16-byte spill offset in spill slot %d\n", (Int)k);
- ss_busy_until_before[k+0] = vreg_lrs[j].dead_before;
- ss_busy_until_before[k+1] = vreg_lrs[j].dead_before;
-
- } else {
-
- /* The ordinary case -- just find a single spill slot. */
-
- /* Find the lowest-numbered spill slot which is available at
- the start point of this interval, and assign the interval
- to it. */
- for (k = 0; k < N_SPILL64S; k++)
- if (ss_busy_until_before[k] <= vreg_lrs[j].live_after)
- break;
- if (k == N_SPILL64S) {
- vpanic("LibVEX_N_SPILL_BYTES is too low. "
- "Increase and recompile.");
- }
- ss_busy_until_before[k] = vreg_lrs[j].dead_before;
-
- }
+ } /* switch (vreg_lrs[j].reg_class) { */
/* This reflects LibVEX's hard-wired knowledge of the baseBlock
layout: the guest state, then two equal sized areas following
diff --git a/main/VEX/priv/host_generic_regs.c b/main/VEX/priv/host_generic_regs.c
index 713add9..3035bfd 100644
--- a/main/VEX/priv/host_generic_regs.c
+++ b/main/VEX/priv/host_generic_regs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/main/VEX/priv/host_generic_regs.h b/main/VEX/priv/host_generic_regs.h
index 0fde5ae..580895e 100644
--- a/main/VEX/priv/host_generic_regs.h
+++ b/main/VEX/priv/host_generic_regs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -188,7 +188,7 @@
This is precisely the behaviour that the register allocator needs
to impose its decisions on the instructions it processes. */
-#define N_HREG_REMAP 5
+#define N_HREG_REMAP 6
typedef
struct {
diff --git a/main/VEX/priv/host_generic_simd128.c b/main/VEX/priv/host_generic_simd128.c
index 6e1100c..908f250 100644
--- a/main/VEX/priv/host_generic_simd128.c
+++ b/main/VEX/priv/host_generic_simd128.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2011 OpenWorks GbR
+ Copyright (C) 2010-2012 OpenWorks GbR
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -358,6 +358,16 @@
res->w16[7] = narrow32to16(argL->w32[3]);
}
+void VEX_REGPARM(3)
+ h_generic_calc_Perm32x4 ( /*OUT*/V128* res,
+ V128* argL, V128* argR )
+{
+ res->w32[0] = argL->w32[ argR->w32[0] & 3 ];
+ res->w32[1] = argL->w32[ argR->w32[1] & 3 ];
+ res->w32[2] = argL->w32[ argR->w32[2] & 3 ];
+ res->w32[3] = argL->w32[ argR->w32[3] & 3 ];
+}
+
/*---------------------------------------------------------------*/
/*--- end host_generic_simd128.c ---*/
diff --git a/main/VEX/priv/host_generic_simd128.h b/main/VEX/priv/host_generic_simd128.h
index 6f9cc97..7956b80 100644
--- a/main/VEX/priv/host_generic_simd128.h
+++ b/main/VEX/priv/host_generic_simd128.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2011 OpenWorks GbR
+ Copyright (C) 2010-2012 OpenWorks GbR
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -83,6 +83,9 @@
void h_generic_calc_NarrowBin32to16x8
( /*OUT*/V128*, V128*, V128* );
+extern VEX_REGPARM(3)
+ void h_generic_calc_Perm32x4 ( /*OUT*/V128*, V128*, V128* );
+
#endif /* ndef __VEX_HOST_GENERIC_SIMD128_H */
/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/host_generic_simd64.c b/main/VEX/priv/host_generic_simd64.c
index 52af103..b70ce88 100644
--- a/main/VEX/priv/host_generic_simd64.c
+++ b/main/VEX/priv/host_generic_simd64.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -139,6 +139,16 @@
/* Scalar helpers. */
+static inline Int qadd32S ( Int xx, Int yy )
+{
+ Long t = ((Long)xx) + ((Long)yy);
+ const Long loLim = -0x80000000LL;
+ const Long hiLim = 0x7FFFFFFFLL;
+ if (t < loLim) t = loLim;
+ if (t > hiLim) t = hiLim;
+ return (Int)t;
+}
+
static inline Short qadd16S ( Short xx, Short yy )
{
Int t = ((Int)xx) + ((Int)yy);
@@ -169,6 +179,16 @@
return (UChar)t;
}
+static inline Int qsub32S ( Int xx, Int yy )
+{
+ Long t = ((Long)xx) - ((Long)yy);
+ const Long loLim = -0x80000000LL;
+ const Long hiLim = 0x7FFFFFFFLL;
+ if (t < loLim) t = loLim;
+ if (t > hiLim) t = hiLim;
+ return (Int)t;
+}
+
static inline Short qsub16S ( Short xx, Short yy )
{
Int t = ((Int)xx) - ((Int)yy);
@@ -1379,7 +1399,143 @@
+ absdiff8U( sel8x4_0(xx), sel8x4_0(yy) );
}
+UInt h_generic_calc_QAdd32S ( UInt xx, UInt yy )
+{
+ return qadd32S( xx, yy );
+}
+
+UInt h_generic_calc_QSub32S ( UInt xx, UInt yy )
+{
+ return qsub32S( xx, yy );
+}
+
+
+/*------------------------------------------------------------------*/
+/* Decimal Floating Point (DFP) externally visible helper functions */
+/* that implement Iop_BCDtoDPB and Iop_DPBtoBCD */
+/*------------------------------------------------------------------*/
+
+#define NOT( x ) ( ( ( x ) == 0) ? 1 : 0)
+#define GET( x, y ) ( ( ( x ) & ( 0x1UL << ( y ) ) ) >> ( y ) )
+#define PUT( x, y ) ( ( x )<< ( y ) )
+
+ULong dpb_to_bcd( ULong chunk )
+{
+ Short a, b, c, d, e, f, g, h, i, j, k, m;
+ Short p, q, r, s, t, u, v, w, x, y;
+ ULong value;
+
+ /* convert 10 bit densely packed BCD to BCD */
+ p = GET( chunk, 9 );
+ q = GET( chunk, 8 );
+ r = GET( chunk, 7 );
+ s = GET( chunk, 6 );
+ t = GET( chunk, 5 );
+ u = GET( chunk, 4 );
+ v = GET( chunk, 3 );
+ w = GET( chunk, 2 );
+ x = GET( chunk, 1 );
+ y = GET( chunk, 0 );
+
+ /* The BCD bit values are given by the following boolean equations.*/
+ a = ( NOT(s) & v & w ) | ( t & v & w & s ) | ( v & w & NOT(x) );
+ b = ( p & s & x & NOT(t) ) | ( p & NOT(w) ) | ( p & NOT(v) );
+ c = ( q & s & x & NOT(t) ) | ( q & NOT(w) ) | ( q & NOT(v) );
+ d = r;
+ e = ( v & NOT(w) & x ) | ( s & v & w & x ) | ( NOT(t) & v & x & w );
+ f = ( p & t & v & w & x & NOT(s) ) | ( s & NOT(x) & v ) | ( s & NOT(v) );
+ g = ( q & t & w & v & x & NOT(s) ) | ( t & NOT(x) & v ) | ( t & NOT(v) );
+ h = u;
+ i = ( t & v & w & x ) | ( s & v & w & x ) | ( v & NOT(w) & NOT(x) );
+ j = ( p & NOT(s) & NOT(t) & w & v ) | ( s & v & NOT(w) & x )
+ | ( p & w & NOT(x) & v ) | ( w & NOT(v) );
+ k = ( q & NOT(s) & NOT(t) & v & w ) | ( t & v & NOT(w) & x )
+ | ( q & v & w & NOT(x) ) | ( x & NOT(v) );
+ m = y;
+
+ value = PUT(a, 11) | PUT(b, 10) | PUT(c, 9) | PUT(d, 8) | PUT(e, 7)
+ | PUT(f, 6) | PUT(g, 5) | PUT(h, 4) | PUT(i, 3) | PUT(j, 2)
+ | PUT(k, 1) | PUT(m, 0);
+ return value;
+}
+
+ULong bcd_to_dpb( ULong chunk )
+{
+ Short a, b, c, d, e, f, g, h, i, j, k, m;
+ Short p, q, r, s, t, u, v, w, x, y;
+ ULong value;
+ /* Convert a 3 digit BCD value to a 10 bit Densely Packed Binary (DPD) value
+ The boolean equations to calculate the value of each of the DPD bit
+ is given in Appendix B of Book 1: Power ISA User Instruction set. The
+ bits for the DPD number are [abcdefghijkm]. The bits for the BCD value
+ are [pqrstuvwxy]. The boolean logic equations in psuedo C code are:
+ */
+ a = GET( chunk, 11 );
+ b = GET( chunk, 10 );
+ c = GET( chunk, 9 );
+ d = GET( chunk, 8 );
+ e = GET( chunk, 7 );
+ f = GET( chunk, 6 );
+ g = GET( chunk, 5 );
+ h = GET( chunk, 4 );
+ i = GET( chunk, 3 );
+ j = GET( chunk, 2 );
+ k = GET( chunk, 1 );
+ m = GET( chunk, 0 );
+
+ p = ( f & a & i & NOT(e) ) | ( j & a & NOT(i) ) | ( b & NOT(a) );
+ q = ( g & a & i & NOT(e) ) | ( k & a & NOT(i) ) | ( c & NOT(a) );
+ r = d;
+ s = ( j & NOT(a) & e & NOT(i) ) | ( f & NOT(i) & NOT(e) )
+ | ( f & NOT(a) & NOT(e) ) | ( e & i );
+ t = ( k & NOT(a) & e & NOT(i) ) | ( g & NOT(i) & NOT(e) )
+ | ( g & NOT(a) & NOT(e) ) | ( a & i );
+ u = h;
+ v = a | e | i;
+ w = ( NOT(e) & j & NOT(i) ) | ( e & i ) | a;
+ x = ( NOT(a) & k & NOT(i) ) | ( a & i ) | e;
+ y = m;
+
+ value = PUT(p, 9) | PUT(q, 8) | PUT(r, 7) | PUT(s, 6) | PUT(t, 5)
+ | PUT(u, 4) | PUT(v, 3) | PUT(w, 2) | PUT(x, 1) | y;
+
+ return value;
+}
+
+ULong h_DPBtoBCD( ULong dpb )
+{
+ ULong result, chunk;
+ Int i;
+
+ result = 0;
+
+ for (i = 0; i < 5; i++) {
+ chunk = dpb >> ( 4 - i ) * 10;
+ result = result << 12;
+ result |= dpb_to_bcd( chunk & 0x3FF );
+ }
+ return result;
+}
+
+ULong h_BCDtoDPB( ULong bcd )
+{
+ ULong result, chunk;
+ Int i;
+
+ result = 0;
+
+ for (i = 0; i < 5; i++) {
+ chunk = bcd >> ( 4 - i ) * 12;
+ result = result << 10;
+ result |= bcd_to_dpb( chunk & 0xFFF );
+ }
+ return result;
+}
+#undef NOT
+#undef GET
+#undef PUT
/*---------------------------------------------------------------*/
/*--- end host_generic_simd64.c ---*/
/*---------------------------------------------------------------*/
+
diff --git a/main/VEX/priv/host_generic_simd64.h b/main/VEX/priv/host_generic_simd64.h
index 5b6640c..0858583 100644
--- a/main/VEX/priv/host_generic_simd64.h
+++ b/main/VEX/priv/host_generic_simd64.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -153,9 +153,18 @@
extern UInt h_generic_calc_Sad8Ux4 ( UInt, UInt );
+extern UInt h_generic_calc_QAdd32S ( UInt, UInt );
+extern UInt h_generic_calc_QSub32S ( UInt, UInt );
+
extern UInt h_generic_calc_CmpNEZ16x2 ( UInt );
extern UInt h_generic_calc_CmpNEZ8x4 ( UInt );
+extern ULong h_DPBtoBCD ( ULong dpb );
+extern ULong h_BCDtoDPB ( ULong bcd );
+
+ULong dpb_to_bcd(ULong chunk); // helper for h_DPBtoBCD
+ULong bcd_to_dpb(ULong chunk); // helper for h_BCDtoDPB
+
#endif /* ndef __VEX_HOST_GENERIC_SIMD64_H */
/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/host_mips_defs.c b/main/VEX/priv/host_mips_defs.c
new file mode 100644
index 0000000..f2a1e82
--- /dev/null
+++ b/main/VEX/priv/host_mips_defs.c
@@ -0,0 +1,4045 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin host_mips_defs.c ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "libvex_basictypes.h"
+#include "libvex.h"
+#include "libvex_trc_values.h"
+
+#include "main_util.h"
+#include "host_generic_regs.h"
+#include "host_mips_defs.h"
+
+/*---------------- Registers ----------------*/
+
+void ppHRegMIPS(HReg reg, Bool mode64)
+{
+ Int r;
+ static HChar *ireg32_names[35]
+ = { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
+ "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
+ "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
+ "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
+ "%32", "%33", "%34",
+ };
+
+ static HChar *freg32_names[32]
+ = { "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
+ "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
+ "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
+ "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "f30", "$f31"
+ };
+
+ static HChar *freg64_names[32]
+ = { "$d0", "$d1", "$d2", "$d3", "$d4", "$d5", "$d6", "$d7",
+ "$d8", "$d9", "$d10", "$d11", "$d12", "$d13", "$d14", "$d15",
+ };
+
+ /* Be generic for all virtual regs. */
+ if (hregIsVirtual(reg)) {
+ ppHReg(reg);
+ return;
+ }
+
+ /* But specific for real regs. */
+ vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 ||
+ hregClass(reg) == HRcFlt32 || hregClass(reg) == HRcFlt64);
+
+ /* But specific for real regs. */
+ {
+ switch (hregClass(reg)) {
+ case HRcInt32:
+ r = hregNumber(reg);
+ vassert(r >= 0 && r < 32);
+ vex_printf("%s", ireg32_names[r]);
+ return;
+ case HRcFlt32:
+ r = hregNumber(reg);
+ vassert(r >= 0 && r < 32);
+ vex_printf("%s", freg32_names[r]);
+ return;
+ case HRcFlt64:
+ r = hregNumber(reg);
+ vassert(r >= 0 && r < 32);
+ vex_printf("%s", freg64_names[r]);
+ return;
+ default:
+ vpanic("ppHRegMIPS");
+ break;
+ }
+ }
+
+ return;
+}
+
+#define MkHRegGPR(_n, _mode64) \
+ mkHReg(_n, _mode64 ? HRcInt64 : HRcInt32, False)
+
+HReg hregMIPS_GPR0(Bool mode64)
+{
+ return MkHRegGPR(0, mode64);
+}
+
+HReg hregMIPS_GPR1(Bool mode64)
+{
+ return MkHRegGPR(1, mode64);
+}
+
+HReg hregMIPS_GPR2(Bool mode64)
+{
+ return MkHRegGPR(2, mode64);
+}
+
+HReg hregMIPS_GPR3(Bool mode64)
+{
+ return MkHRegGPR(3, mode64);
+}
+
+HReg hregMIPS_GPR4(Bool mode64)
+{
+ return MkHRegGPR(4, mode64);
+}
+
+HReg hregMIPS_GPR5(Bool mode64)
+{
+ return MkHRegGPR(5, mode64);
+}
+
+HReg hregMIPS_GPR6(Bool mode64)
+{
+ return MkHRegGPR(6, mode64);
+}
+
+HReg hregMIPS_GPR7(Bool mode64)
+{
+ return MkHRegGPR(7, mode64);
+}
+
+HReg hregMIPS_GPR8(Bool mode64)
+{
+ return MkHRegGPR(8, mode64);
+}
+
+HReg hregMIPS_GPR9(Bool mode64)
+{
+ return MkHRegGPR(9, mode64);
+}
+
+HReg hregMIPS_GPR10(Bool mode64)
+{
+ return MkHRegGPR(10, mode64);
+}
+
+HReg hregMIPS_GPR11(Bool mode64)
+{
+ return MkHRegGPR(11, mode64);
+}
+
+HReg hregMIPS_GPR12(Bool mode64)
+{
+ return MkHRegGPR(12, mode64);
+}
+
+HReg hregMIPS_GPR13(Bool mode64)
+{
+ return MkHRegGPR(13, mode64);
+}
+
+HReg hregMIPS_GPR14(Bool mode64)
+{
+ return MkHRegGPR(14, mode64);
+}
+
+HReg hregMIPS_GPR15(Bool mode64)
+{
+ return MkHRegGPR(15, mode64);
+}
+
+HReg hregMIPS_GPR16(Bool mode64)
+{
+ return MkHRegGPR(16, mode64);
+}
+
+HReg hregMIPS_GPR17(Bool mode64)
+{
+ return MkHRegGPR(17, mode64);
+}
+
+HReg hregMIPS_GPR18(Bool mode64)
+{
+ return MkHRegGPR(18, mode64);
+}
+
+HReg hregMIPS_GPR19(Bool mode64)
+{
+ return MkHRegGPR(19, mode64);
+}
+
+HReg hregMIPS_GPR20(Bool mode64)
+{
+ return MkHRegGPR(20, mode64);
+}
+
+HReg hregMIPS_GPR21(Bool mode64)
+{
+ return MkHRegGPR(21, mode64);
+}
+
+HReg hregMIPS_GPR22(Bool mode64)
+{
+ return MkHRegGPR(22, mode64);
+}
+
+HReg hregMIPS_GPR23(Bool mode64)
+{
+ return MkHRegGPR(23, mode64);
+}
+
+HReg hregMIPS_GPR24(Bool mode64)
+{
+ return MkHRegGPR(24, mode64);
+}
+
+HReg hregMIPS_GPR25(Bool mode64)
+{
+ return MkHRegGPR(25, mode64);
+}
+
+HReg hregMIPS_GPR26(Bool mode64)
+{
+ return MkHRegGPR(26, mode64);
+}
+
+HReg hregMIPS_GPR27(Bool mode64)
+{
+ return MkHRegGPR(27, mode64);
+}
+
+HReg hregMIPS_GPR28(Bool mode64)
+{
+ return MkHRegGPR(28, mode64);
+}
+
+HReg hregMIPS_GPR29(Bool mode64)
+{
+ return MkHRegGPR(29, mode64);
+}
+
+HReg hregMIPS_GPR30(Bool mode64)
+{
+ return MkHRegGPR(30, mode64);
+}
+
+HReg hregMIPS_GPR31(Bool mode64)
+{
+ return MkHRegGPR(31, mode64);
+}
+
+#define MkHRegFPR(_n, _mode64) \
+ mkHReg(_n, _mode64 ? HRcFlt64 : HRcFlt32, False)
+
+HReg hregMIPS_F0(Bool mode64)
+{
+ return MkHRegFPR(0, mode64);
+}
+
+HReg hregMIPS_F1(Bool mode64)
+{
+ return MkHRegFPR(1, mode64);
+}
+
+HReg hregMIPS_F2(Bool mode64)
+{
+ return MkHRegFPR(2, mode64);
+}
+
+HReg hregMIPS_F3(Bool mode64)
+{
+ return MkHRegFPR(3, mode64);
+}
+
+HReg hregMIPS_F4(Bool mode64)
+{
+ return MkHRegFPR(4, mode64);
+}
+
+HReg hregMIPS_F5(Bool mode64)
+{
+ return MkHRegFPR(5, mode64);
+}
+
+HReg hregMIPS_F6(Bool mode64)
+{
+ return MkHRegFPR(6, mode64);
+}
+
+HReg hregMIPS_F7(Bool mode64)
+{
+ return MkHRegFPR(7, mode64);
+}
+
+HReg hregMIPS_F8(Bool mode64)
+{
+ return MkHRegFPR(8, mode64);
+}
+
+HReg hregMIPS_F9(Bool mode64)
+{
+ return MkHRegFPR(9, mode64);
+}
+
+HReg hregMIPS_F10(Bool mode64)
+{
+ return MkHRegFPR(10, mode64);
+}
+
+HReg hregMIPS_F11(Bool mode64)
+{
+ return MkHRegFPR(11, mode64);
+}
+
+HReg hregMIPS_F12(Bool mode64)
+{
+ return MkHRegFPR(12, mode64);
+}
+
+HReg hregMIPS_F13(Bool mode64)
+{
+ return MkHRegFPR(13, mode64);
+}
+
+HReg hregMIPS_F14(Bool mode64)
+{
+ return MkHRegFPR(14, mode64);
+}
+
+HReg hregMIPS_F15(Bool mode64)
+{
+ return MkHRegFPR(15, mode64);
+}
+
+HReg hregMIPS_F16(Bool mode64)
+{
+ return MkHRegFPR(16, mode64);
+}
+
+HReg hregMIPS_F17(Bool mode64)
+{
+ return MkHRegFPR(17, mode64);
+}
+
+HReg hregMIPS_F18(Bool mode64)
+{
+ return MkHRegFPR(18, mode64);
+}
+
+HReg hregMIPS_F19(Bool mode64)
+{
+ return MkHRegFPR(19, mode64);
+}
+
+HReg hregMIPS_F20(Bool mode64)
+{
+ return MkHRegFPR(20, mode64);
+}
+
+HReg hregMIPS_F21(Bool mode64)
+{
+ return MkHRegFPR(21, mode64);
+}
+
+HReg hregMIPS_F22(Bool mode64)
+{
+ return MkHRegFPR(22, mode64);
+}
+
+HReg hregMIPS_F23(Bool mode64)
+{
+ return MkHRegFPR(23, mode64);
+}
+
+HReg hregMIPS_F24(Bool mode64)
+{
+ return MkHRegFPR(24, mode64);
+}
+
+HReg hregMIPS_F25(Bool mode64)
+{
+ return MkHRegFPR(25, mode64);
+}
+
+HReg hregMIPS_F26(Bool mode64)
+{
+ return MkHRegFPR(26, mode64);
+}
+
+HReg hregMIPS_F27(Bool mode64)
+{
+ return MkHRegFPR(27, mode64);
+}
+
+HReg hregMIPS_F28(Bool mode64)
+{
+ return MkHRegFPR(28, mode64);
+}
+
+HReg hregMIPS_F29(Bool mode64)
+{
+ return MkHRegFPR(29, mode64);
+}
+
+HReg hregMIPS_F30(Bool mode64)
+{
+ return MkHRegFPR(30, mode64);
+}
+
+HReg hregMIPS_F31(Bool mode64)
+{
+ return MkHRegFPR(31, mode64);
+}
+
+HReg hregMIPS_PC(Bool mode64)
+{
+ return mkHReg(32, mode64 ? HRcFlt64 : HRcFlt32, False);
+}
+
+HReg hregMIPS_HI(Bool mode64)
+{
+ return mkHReg(33, mode64 ? HRcFlt64 : HRcFlt32, False);
+}
+
+HReg hregMIPS_LO(Bool mode64)
+{
+ return mkHReg(34, mode64 ? HRcFlt64 : HRcFlt32, False);
+}
+
+HReg hregMIPS_D0(void)
+{
+ return mkHReg(0, HRcFlt64, False);
+}
+
+HReg hregMIPS_D1(void)
+{
+ return mkHReg(2, HRcFlt64, False);
+}
+
+HReg hregMIPS_D2(void)
+{
+ return mkHReg(4, HRcFlt64, False);
+}
+
+HReg hregMIPS_D3(void)
+{
+ return mkHReg(6, HRcFlt64, False);
+}
+
+HReg hregMIPS_D4(void)
+{
+ return mkHReg(8, HRcFlt64, False);
+}
+
+HReg hregMIPS_D5(void)
+{
+ return mkHReg(10, HRcFlt64, False);
+}
+
+HReg hregMIPS_D6(void)
+{
+ return mkHReg(12, HRcFlt64, False);
+}
+
+HReg hregMIPS_D7(void)
+{
+ return mkHReg(14, HRcFlt64, False);
+}
+
+HReg hregMIPS_D8(void)
+{
+ return mkHReg(16, HRcFlt64, False);
+}
+
+HReg hregMIPS_D9(void)
+{
+ return mkHReg(18, HRcFlt64, False);
+}
+
+HReg hregMIPS_D10(void)
+{
+ return mkHReg(20, HRcFlt64, False);
+}
+
+HReg hregMIPS_D11(void)
+{
+ return mkHReg(22, HRcFlt64, False);
+}
+
+HReg hregMIPS_D12(void)
+{
+ return mkHReg(24, HRcFlt64, False);
+}
+
+HReg hregMIPS_D13(void)
+{
+ return mkHReg(26, HRcFlt64, False);
+}
+
+HReg hregMIPS_D14(void)
+{
+ return mkHReg(28, HRcFlt64, False);
+}
+
+HReg hregMIPS_D15(void)
+{
+ return mkHReg(30, HRcFlt64, False);
+}
+
+HReg hregMIPS_FIR(void)
+{
+ return mkHReg(35, HRcInt32, False);
+}
+
+HReg hregMIPS_FCCR(void)
+{
+ return mkHReg(36, HRcInt32, False);
+}
+
+HReg hregMIPS_FEXR(void)
+{
+ return mkHReg(37, HRcInt32, False);
+}
+
+HReg hregMIPS_FENR(void)
+{
+ return mkHReg(38, HRcInt32, False);
+}
+
+HReg hregMIPS_FCSR(void)
+{
+ return mkHReg(39, HRcInt32, False);
+}
+
+HReg hregMIPS_COND(void)
+{
+ return mkHReg(47, HRcInt32, False);
+}
+
+void getAllocableRegs_MIPS(Int * nregs, HReg ** arr, Bool mode64)
+{
+ if (mode64)
+ *nregs = 27;
+ else
+ *nregs = 34;
+ UInt i = 0;
+ *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
+
+ //ZERO = constant 0
+ //AT = assembler temporary
+ // callee saves ones are listed first, since we prefer them
+ // if they're available
+ (*arr)[i++] = hregMIPS_GPR16(mode64);
+ (*arr)[i++] = hregMIPS_GPR17(mode64);
+ (*arr)[i++] = hregMIPS_GPR18(mode64);
+ (*arr)[i++] = hregMIPS_GPR19(mode64);
+ (*arr)[i++] = hregMIPS_GPR20(mode64);
+ (*arr)[i++] = hregMIPS_GPR21(mode64);
+ (*arr)[i++] = hregMIPS_GPR22(mode64);
+ if (!mode64)
+ (*arr)[i++] = hregMIPS_GPR23(mode64);
+
+ // otherwise we'll have to slum it out with caller-saves ones
+ if (mode64) {
+ (*arr)[i++] = hregMIPS_GPR8(mode64);
+ (*arr)[i++] = hregMIPS_GPR9(mode64);
+ (*arr)[i++] = hregMIPS_GPR10(mode64);
+ (*arr)[i++] = hregMIPS_GPR11(mode64);
+ }
+ (*arr)[i++] = hregMIPS_GPR12(mode64);
+ (*arr)[i++] = hregMIPS_GPR13(mode64);
+ (*arr)[i++] = hregMIPS_GPR14(mode64);
+ (*arr)[i++] = hregMIPS_GPR15(mode64);
+ (*arr)[i++] = hregMIPS_GPR24(mode64);
+ /***********mips32********************/
+ // t0 (=dispatch_ctr)
+ // t1 spill reg temp
+ // t2 (=guest_state)
+ // t3 (=PC = next guest address)
+ // K0 and K1 are reserved for OS kernel
+ // GP = global pointer
+ // SP = stack pointer
+ // FP = frame pointer
+ // RA = link register
+ // + PC, HI and LO
+ (*arr)[i++] = hregMIPS_F20(mode64);
+ (*arr)[i++] = hregMIPS_F21(mode64);
+ (*arr)[i++] = hregMIPS_F22(mode64);
+ (*arr)[i++] = hregMIPS_F23(mode64);
+ (*arr)[i++] = hregMIPS_F24(mode64);
+ (*arr)[i++] = hregMIPS_F25(mode64);
+ (*arr)[i++] = hregMIPS_F26(mode64);
+ (*arr)[i++] = hregMIPS_F27(mode64);
+ (*arr)[i++] = hregMIPS_F28(mode64);
+ (*arr)[i++] = hregMIPS_F29(mode64);
+ (*arr)[i++] = hregMIPS_F30(mode64);
+ if (!mode64) {
+ /* Fake double floating point */
+ (*arr)[i++] = hregMIPS_D0();
+ (*arr)[i++] = hregMIPS_D1();
+ (*arr)[i++] = hregMIPS_D2();
+ (*arr)[i++] = hregMIPS_D3();
+ (*arr)[i++] = hregMIPS_D4();
+ (*arr)[i++] = hregMIPS_D5();
+ (*arr)[i++] = hregMIPS_D6();
+ (*arr)[i++] = hregMIPS_D7();
+ (*arr)[i++] = hregMIPS_D8();
+ (*arr)[i++] = hregMIPS_D9();
+ }
+ vassert(i == *nregs);
+
+}
+
+/*----------------- Condition Codes ----------------------*/
+
+HChar *showMIPSCondCode(MIPSCondCode cond)
+{
+ HChar* ret;
+ switch (cond) {
+ case MIPScc_EQ:
+ ret = "EQ"; /* equal */
+ break;
+ case MIPScc_NE:
+ ret = "NEQ"; /* not equal */
+ break;
+ case MIPScc_HS:
+ ret = "GE"; /* >=u (Greater Than or Equal) */
+ break;
+ case MIPScc_LO:
+ ret = "LT"; /* <u (lower) */
+ break;
+ case MIPScc_MI:
+ ret = "mi"; /* minus (negative) */
+ break;
+ case MIPScc_PL:
+ ret = "pl"; /* plus (zero or +ve) */
+ break;
+ case MIPScc_VS:
+ ret = "vs"; /* overflow */
+ break;
+ case MIPScc_VC:
+ ret = "vc"; /* no overflow */
+ break;
+ case MIPScc_HI:
+ ret = "hi"; /* >u (higher) */
+ break;
+ case MIPScc_LS:
+ ret = "ls"; /* <=u (lower or same) */
+ break;
+ case MIPScc_GE:
+ ret = "ge"; /* >=s (signed greater or equal) */
+ break;
+ case MIPScc_LT:
+ ret = "lt"; /* <s (signed less than) */
+ break;
+ case MIPScc_GT:
+ ret = "gt"; /* >s (signed greater) */
+ break;
+ case MIPScc_LE:
+ ret = "le"; /* <=s (signed less or equal) */
+ break;
+ case MIPScc_AL:
+ ret = "al"; /* always (unconditional) */
+ break;
+ case MIPScc_NV:
+ ret = "nv"; /* never (unconditional): */
+ break;
+ default:
+ vpanic("showMIPSCondCode");
+ break;
+ }
+ return ret;
+}
+
+HChar *showMIPSFpOp(MIPSFpOp op)
+{
+ HChar *ret;
+ switch (op) {
+ case Mfp_ADDD:
+ ret = "ADD.D";
+ break;
+ case Mfp_SUBD:
+ ret = "SUB.D";
+ break;
+ case Mfp_MULD:
+ ret = "MUL.D";
+ break;
+ case Mfp_DIVD:
+ ret = "DIV.D";
+ break;
+ case Mfp_MADDD:
+ ret = "MADD.D";
+ break;
+ case Mfp_MSUBD:
+ ret = "MSUB.D";
+ break;
+ case Mfp_MADDS:
+ ret = "MADD.S";
+ break;
+ case Mfp_MSUBS:
+ ret = "MSUB.S";
+ break;
+ case Mfp_ADDS:
+ ret = "ADD.S";
+ break;
+ case Mfp_SUBS:
+ ret = "SUB.S";
+ break;
+ case Mfp_MULS:
+ ret = "MUL.S";
+ break;
+ case Mfp_DIVS:
+ ret = "DIV.S";
+ break;
+ case Mfp_SQRTS:
+ ret = "SQRT.S";
+ break;
+ case Mfp_SQRTD:
+ ret = "SQRT.D";
+ break;
+ case Mfp_RSQRTS:
+ ret = "RSQRT.S";
+ break;
+ case Mfp_RSQRTD:
+ ret = "RSQRT.D";
+ break;
+ case Mfp_RECIPS:
+ ret = "RECIP.S";
+ break;
+ case Mfp_RECIPD:
+ ret = "RECIP.D";
+ break;
+ case Mfp_ABSS:
+ ret = "ABS.S";
+ break;
+ case Mfp_ABSD:
+ ret = "ABS.D";
+ break;
+ case Mfp_NEGS:
+ ret = "NEG.S";
+ break;
+ case Mfp_NEGD:
+ ret = "NEG.D";
+ break;
+ case Mfp_MOVS:
+ ret = "MOV.S";
+ break;
+ case Mfp_MOVD:
+ ret = "MOV.D";
+ break;
+ case Mfp_RES:
+ ret = "RES";
+ break;
+ case Mfp_ROUNDWS:
+ ret = "ROUND.W.S";
+ break;
+ case Mfp_ROUNDWD:
+ ret = "ROUND.W.D";
+ break;
+ case Mfp_FLOORWS:
+ ret = "FLOOR.W.S";
+ break;
+ case Mfp_FLOORWD:
+ ret = "FLOOR.W.D";
+ break;
+ case Mfp_RSQRTE:
+ ret = "frsqrte";
+ break;
+ case Mfp_CVTDW:
+ case Mfp_CVTD:
+ ret = "CVT.D";
+ break;
+ case Mfp_CVTSD:
+ case Mfp_CVTSW:
+ ret = "CVT.S";
+ break;
+ case Mfp_CVTWS:
+ case Mfp_CVTWD:
+ ret = "CVT.W";
+ break;
+ case Mfp_TRUWD:
+ case Mfp_TRUWS:
+ ret = "TRUNC.W";
+ break;
+ case Mfp_TRULD:
+ case Mfp_TRULS:
+ ret = "TRUNC.L";
+ break;
+ case Mfp_CEILWS:
+ case Mfp_CEILWD:
+ ret = "CEIL.W";
+ break;
+ case Mfp_CEILLS:
+ case Mfp_CEILLD:
+ ret = "CEIL.L";
+ break;
+ case Mfp_CMP:
+ ret = "C.cond.d";
+ break;
+ default:
+ vpanic("showMIPSFpOp");
+ break;
+ }
+ return ret;
+}
+
+/* --------- MIPSAMode: memory address expressions. --------- */
+
+MIPSAMode *MIPSAMode_IR(Int idx, HReg base)
+{
+ MIPSAMode *am = LibVEX_Alloc(sizeof(MIPSAMode));
+ am->tag = Mam_IR;
+ am->Mam.IR.base = base;
+ am->Mam.IR.index = idx;
+
+ return am;
+}
+
+MIPSAMode *MIPSAMode_RR(HReg idx, HReg base)
+{
+ MIPSAMode *am = LibVEX_Alloc(sizeof(MIPSAMode));
+ am->tag = Mam_RR;
+ am->Mam.RR.base = base;
+ am->Mam.RR.index = idx;
+
+ return am;
+}
+
+MIPSAMode *dopyMIPSAMode(MIPSAMode * am)
+{
+ MIPSAMode* ret;
+ switch (am->tag) {
+ case Mam_IR:
+ ret = MIPSAMode_IR(am->Mam.IR.index, am->Mam.IR.base);
+ break;
+ case Mam_RR:
+ ret = MIPSAMode_RR(am->Mam.RR.index, am->Mam.RR.base);
+ break;
+ default:
+ vpanic("dopyMIPSAMode");
+ break;
+ }
+ return ret;
+}
+
+MIPSAMode *nextMIPSAModeFloat(MIPSAMode * am)
+{
+ MIPSAMode* ret;
+ switch (am->tag) {
+ case Mam_IR:
+ ret = MIPSAMode_IR(am->Mam.IR.index + 8, am->Mam.IR.base);
+ break;
+ case Mam_RR:
+ ret = MIPSAMode_RR(am->Mam.RR.index + 1, am->Mam.RR.base);
+ break;
+ default:
+ vpanic("dopyMIPSAMode");
+ break;
+ }
+ return ret;
+}
+
+MIPSAMode *nextMIPSAModeInt(MIPSAMode * am)
+{
+ MIPSAMode* ret;
+ switch (am->tag) {
+ case Mam_IR:
+ ret = MIPSAMode_IR(am->Mam.IR.index + 4, am->Mam.IR.base);
+ break;
+ case Mam_RR:
+ ret = MIPSAMode_RR(am->Mam.RR.index + 1, am->Mam.RR.base);
+ break;
+ default:
+ vpanic("dopyMIPSAMode");
+ break;
+ }
+ return ret;
+}
+
+void ppMIPSAMode(MIPSAMode * am, Bool mode64)
+{
+ switch (am->tag) {
+ case Mam_IR:
+ if (am->Mam.IR.index == 0)
+ vex_printf("0(");
+ else
+ vex_printf("%d(", (Int) am->Mam.IR.index);
+ ppHRegMIPS(am->Mam.IR.base, mode64);
+ vex_printf(")");
+ return;
+ case Mam_RR:
+ ppHRegMIPS(am->Mam.RR.base, mode64);
+ vex_printf(", ");
+ ppHRegMIPS(am->Mam.RR.index, mode64);
+ return;
+ default:
+ vpanic("ppMIPSAMode");
+ break;
+ }
+}
+
+static void addRegUsage_MIPSAMode(HRegUsage * u, MIPSAMode * am)
+{
+ switch (am->tag) {
+ case Mam_IR:
+ addHRegUse(u, HRmRead, am->Mam.IR.base);
+ return;
+ case Mam_RR:
+ addHRegUse(u, HRmRead, am->Mam.RR.base);
+ addHRegUse(u, HRmRead, am->Mam.RR.index);
+ return;
+ default:
+ vpanic("addRegUsage_MIPSAMode");
+ break;
+ }
+}
+
+static void mapRegs_MIPSAMode(HRegRemap * m, MIPSAMode * am)
+{
+ switch (am->tag) {
+ case Mam_IR:
+ am->Mam.IR.base = lookupHRegRemap(m, am->Mam.IR.base);
+ return;
+ case Mam_RR:
+ am->Mam.RR.base = lookupHRegRemap(m, am->Mam.RR.base);
+ am->Mam.RR.index = lookupHRegRemap(m, am->Mam.RR.index);
+ return;
+ default:
+ vpanic("mapRegs_MIPSAMode");
+ break;
+ }
+}
+
+/* --------- Operand, which can be a reg or a u16/s16. --------- */
+
+MIPSRH *MIPSRH_Imm(Bool syned, UShort imm16)
+{
+ MIPSRH *op = LibVEX_Alloc(sizeof(MIPSRH));
+ op->tag = Mrh_Imm;
+ op->Mrh.Imm.syned = syned;
+ op->Mrh.Imm.imm16 = imm16;
+ /* If this is a signed value, ensure it's not -32768, so that we
+ are guaranteed always to be able to negate if needed. */
+ if (syned)
+ vassert(imm16 != 0x8000);
+ vassert(syned == True || syned == False);
+ return op;
+}
+
+MIPSRH *MIPSRH_Reg(HReg reg)
+{
+ MIPSRH *op = LibVEX_Alloc(sizeof(MIPSRH));
+ op->tag = Mrh_Reg;
+ op->Mrh.Reg.reg = reg;
+ return op;
+}
+
+void ppMIPSRH(MIPSRH * op, Bool mode64)
+{
+ MIPSRHTag tag = op->tag;
+ switch (tag) {
+ case Mrh_Imm:
+ if (op->Mrh.Imm.syned)
+ vex_printf("%d", (Int) (Short) op->Mrh.Imm.imm16);
+ else
+ vex_printf("%u", (UInt) (UShort) op->Mrh.Imm.imm16);
+ return;
+ case Mrh_Reg:
+ ppHRegMIPS(op->Mrh.Reg.reg, mode64);
+ return;
+ default:
+ vpanic("ppMIPSRH");
+ break;
+ }
+}
+
+/* An MIPSRH can only be used in a "read" context (what would it mean
+ to write or modify a literal?) and so we enumerate its registers
+ accordingly. */
+static void addRegUsage_MIPSRH(HRegUsage * u, MIPSRH * op)
+{
+ switch (op->tag) {
+ case Mrh_Imm:
+ return;
+ case Mrh_Reg:
+ addHRegUse(u, HRmRead, op->Mrh.Reg.reg);
+ return;
+ default:
+ vpanic("addRegUsage_MIPSRH");
+ break;
+ }
+}
+
+static void mapRegs_MIPSRH(HRegRemap * m, MIPSRH * op)
+{
+ switch (op->tag) {
+ case Mrh_Imm:
+ return;
+ case Mrh_Reg:
+ op->Mrh.Reg.reg = lookupHRegRemap(m, op->Mrh.Reg.reg);
+ return;
+ default:
+ vpanic("mapRegs_MIPSRH");
+ break;
+ }
+}
+
+/* --------- Instructions. --------- */
+
+HChar *showMIPSUnaryOp(MIPSUnaryOp op)
+{
+ HChar* ret;
+ switch (op) {
+ case Mun_CLO:
+ ret = "clo";
+ break;
+ case Mun_CLZ:
+ ret = "clz";
+ break;
+ case Mun_NOP:
+ ret = "nop";
+ break;
+ default:
+ vpanic("showMIPSUnaryOp");
+ break;
+ }
+ return ret;
+}
+
+HChar *showMIPSAluOp(MIPSAluOp op, Bool immR)
+{
+ HChar* ret;
+ switch (op) {
+ case Malu_ADD:
+ ret = immR ? "addiu" : "addu";
+ break;
+ case Malu_SUB:
+ ret = "subu";
+ break;
+ case Malu_AND:
+ ret = immR ? "andi" : "and";
+ break;
+ case Malu_OR:
+ ret = immR ? "ori" : "or";
+ break;
+ case Malu_NOR:
+ vassert(immR == False); /*there's no nor with an immediate operand!? */
+ ret = "nor";
+ break;
+ case Malu_XOR:
+ ret = immR ? "xori" : "xor";
+ break;
+ default:
+ vpanic("showMIPSAluOp");
+ break;
+ }
+ return ret;
+}
+
+HChar *showMIPSShftOp(MIPSShftOp op, Bool immR, Bool sz32)
+{
+ HChar *ret;
+ switch (op) {
+ case Mshft_SRA:
+ ret = immR ? (sz32 ? "sar" : "dsar") : (sz32 ? "sarv" : "dsrav");
+ break;
+ case Mshft_SLL:
+ ret = immR ? (sz32 ? "sll" : "dsll") : (sz32 ? "sllv" : "dsllv");
+ break;
+ case Mshft_SRL:
+ ret = immR ? (sz32 ? "srl" : "dsrl") : (sz32 ? "srlv" : "dsrlv");
+ break;
+ default:
+ vpanic("showMIPSShftOp");
+ break;
+ }
+ return ret;
+}
+
+HChar *showMIPSMaccOp(MIPSMaccOp op, Bool variable)
+{
+ HChar *ret;
+ switch (op) {
+ case Macc_ADD:
+ ret = variable ? "madd" : "maddu";
+ break;
+ case Macc_SUB:
+ ret = variable ? "msub" : "msubu";
+ break;
+ default:
+ vpanic("showMIPSAccOp");
+ break;
+ }
+ return ret;
+}
+
+MIPSInstr *MIPSInstr_LI(HReg dst, ULong imm)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_LI;
+ i->Min.LI.dst = dst;
+ i->Min.LI.imm = imm;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Alu(MIPSAluOp op, HReg dst, HReg srcL, MIPSRH * srcR)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Alu;
+ i->Min.Alu.op = op;
+ i->Min.Alu.dst = dst;
+ i->Min.Alu.srcL = srcL;
+ i->Min.Alu.srcR = srcR;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Shft(MIPSShftOp op, Bool sz32, HReg dst, HReg srcL,
+ MIPSRH * srcR)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Shft;
+ i->Min.Shft.op = op;
+ i->Min.Shft.sz32 = sz32;
+ i->Min.Shft.dst = dst;
+ i->Min.Shft.srcL = srcL;
+ i->Min.Shft.srcR = srcR;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Unary(MIPSUnaryOp op, HReg dst, HReg src)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Unary;
+ i->Min.Unary.op = op;
+ i->Min.Unary.dst = dst;
+ i->Min.Unary.src = src;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Cmp(Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR,
+ MIPSCondCode cond)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Cmp;
+ i->Min.Cmp.syned = syned;
+ i->Min.Cmp.sz32 = sz32;
+ i->Min.Cmp.dst = dst;
+ i->Min.Cmp.srcL = srcL;
+ i->Min.Cmp.srcR = srcR;
+ i->Min.Cmp.cond = cond;
+ return i;
+}
+
+/* multiply */
+MIPSInstr *MIPSInstr_Mul(Bool syned, Bool wid, Bool sz32, HReg dst, HReg srcL,
+ HReg srcR)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Mul;
+ i->Min.Mul.syned = syned;
+ i->Min.Mul.widening = wid; /* widen=True else False */
+ i->Min.Mul.sz32 = sz32; /* True = 32 bits */
+ i->Min.Mul.dst = dst;
+ i->Min.Mul.srcL = srcL;
+ i->Min.Mul.srcR = srcR;
+ return i;
+}
+
+/* msub */
+MIPSInstr *MIPSInstr_Msub(Bool syned, HReg srcL, HReg srcR)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Macc;
+
+ i->Min.Macc.op = Macc_SUB;
+ i->Min.Macc.syned = syned;
+ i->Min.Macc.srcL = srcL;
+ i->Min.Macc.srcR = srcR;
+ return i;
+}
+
+/* madd */
+MIPSInstr *MIPSInstr_Madd(Bool syned, HReg srcL, HReg srcR)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Macc;
+
+ i->Min.Macc.op = Macc_ADD;
+ i->Min.Macc.syned = syned;
+ i->Min.Macc.srcL = srcL;
+ i->Min.Macc.srcR = srcR;
+ return i;
+}
+
+/* div */
+MIPSInstr *MIPSInstr_Div(Bool syned, Bool sz32, HReg srcL, HReg srcR)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Div;
+ i->Min.Div.syned = syned;
+ i->Min.Div.sz32 = sz32; /* True = 32 bits */
+ i->Min.Div.srcL = srcL;
+ i->Min.Div.srcR = srcR;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Call(MIPSCondCode cond, Addr32 target, UInt argiregs,
+ HReg src)
+{
+ UInt mask;
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Call;
+ i->Min.Call.cond = cond;
+ i->Min.Call.target = target;
+ i->Min.Call.argiregs = argiregs;
+ i->Min.Call.src = src;
+ /* Only r4 .. r7 inclusive may be used as arg regs. Hence: */
+ mask = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
+ vassert(0 == (argiregs & ~mask));
+ return i;
+}
+
+MIPSInstr *MIPSInstr_CallAlways(MIPSCondCode cond, Addr32 target, UInt argiregs)
+{
+ UInt mask;
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Call;
+ i->Min.Call.cond = cond;
+ i->Min.Call.target = target;
+ i->Min.Call.argiregs = argiregs;
+ /* Only r4 .. r7 inclusive may be used as arg regs. Hence: */
+ mask = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
+ vassert(0 == (argiregs & ~mask));
+ return i;
+}
+
+MIPSInstr *MIPSInstr_XDirect ( Addr32 dstGA, MIPSAMode* amPC,
+ MIPSCondCode cond, Bool toFastEP ) {
+ MIPSInstr* i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_XDirect;
+ i->Min.XDirect.dstGA = dstGA;
+ i->Min.XDirect.amPC = amPC;
+ i->Min.XDirect.cond = cond;
+ i->Min.XDirect.toFastEP = toFastEP;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_XIndir ( HReg dstGA, MIPSAMode* amPC,
+ MIPSCondCode cond ) {
+ MIPSInstr* i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_XIndir;
+ i->Min.XIndir.dstGA = dstGA;
+ i->Min.XIndir.amPC = amPC;
+ i->Min.XIndir.cond = cond;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_XAssisted ( HReg dstGA, MIPSAMode* amPC,
+ MIPSCondCode cond, IRJumpKind jk ) {
+ MIPSInstr* i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_XAssisted;
+ i->Min.XAssisted.dstGA = dstGA;
+ i->Min.XAssisted.amPC = amPC;
+ i->Min.XAssisted.cond = cond;
+ i->Min.XAssisted.jk = jk;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Load(UChar sz, HReg dst, MIPSAMode * src, Bool mode64)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Load;
+ i->Min.Load.sz = sz;
+ i->Min.Load.src = src;
+ i->Min.Load.dst = dst;
+ vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8);
+
+ if (sz == 8)
+ vassert(mode64);
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Store(UChar sz, MIPSAMode * dst, HReg src, Bool mode64)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Store;
+ i->Min.Store.sz = sz;
+ i->Min.Store.src = src;
+ i->Min.Store.dst = dst;
+ vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8);
+
+ if (sz == 8)
+ vassert(mode64);
+ return i;
+}
+
+MIPSInstr *MIPSInstr_LoadL(UChar sz, HReg dst, MIPSAMode * src, Bool mode64)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_LoadL;
+ i->Min.LoadL.sz = sz;
+ i->Min.LoadL.src = src;
+ i->Min.LoadL.dst = dst;
+ vassert(sz == 4 || sz == 8);
+
+ if (sz == 8)
+ vassert(mode64);
+ return i;
+}
+
+MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src, Bool mode64)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_StoreC;
+ i->Min.StoreC.sz = sz;
+ i->Min.StoreC.src = src;
+ i->Min.StoreC.dst = dst;
+ vassert(sz == 4 || sz == 8);
+
+ if (sz == 8)
+ vassert(mode64);
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Mthi(HReg src)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Mthi;
+ i->Min.MtHL.src = src;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Mtlo(HReg src)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Mtlo;
+ i->Min.MtHL.src = src;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Mfhi(HReg dst)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Mfhi;
+ i->Min.MfHL.dst = dst;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_Mflo(HReg dst)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_Mflo;
+ i->Min.MfHL.dst = dst;
+ return i;
+}
+
+/* Read/Write Link Register */
+MIPSInstr *MIPSInstr_RdWrLR(Bool wrLR, HReg gpr)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_RdWrLR;
+ i->Min.RdWrLR.wrLR = wrLR;
+ i->Min.RdWrLR.gpr = gpr;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_FpLdSt(Bool isLoad, UChar sz, HReg reg, MIPSAMode * addr)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_FpLdSt;
+ i->Min.FpLdSt.isLoad = isLoad;
+ i->Min.FpLdSt.sz = sz;
+ i->Min.FpLdSt.reg = reg;
+ i->Min.FpLdSt.addr = addr;
+ vassert(sz == 4 || sz == 8);
+ return i;
+}
+
+MIPSInstr *MIPSInstr_FpUnary(MIPSFpOp op, HReg dst, HReg src)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_FpUnary;
+ i->Min.FpUnary.op = op;
+ i->Min.FpUnary.dst = dst;
+ i->Min.FpUnary.src = src;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_FpBinary(MIPSFpOp op, HReg dst, HReg srcL, HReg srcR)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_FpBinary;
+ i->Min.FpBinary.op = op;
+ i->Min.FpBinary.dst = dst;
+ i->Min.FpBinary.srcL = srcL;
+ i->Min.FpBinary.srcR = srcR;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_FpConvert(MIPSFpOp op, HReg dst, HReg src)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_FpConvert;
+ i->Min.FpConvert.op = op;
+ i->Min.FpConvert.dst = dst;
+ i->Min.FpConvert.src = src;
+ return i;
+
+}
+
+MIPSInstr *MIPSInstr_FpCompare(MIPSFpOp op, HReg dst, HReg srcL, HReg srcR,
+ UChar cond1)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_FpCompare;
+ i->Min.FpCompare.op = op;
+ i->Min.FpCompare.dst = dst;
+ i->Min.FpCompare.srcL = srcL;
+ i->Min.FpCompare.srcR = srcR;
+ i->Min.FpCompare.cond1 = cond1;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_MovCond(HReg dst, HReg argL, MIPSRH * argR, HReg condR,
+ MIPSCondCode cond)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_MovCond;
+ i->Min.MovCond.dst = dst;
+ i->Min.MovCond.srcL = argL;
+ i->Min.MovCond.srcR = argR;
+ i->Min.MovCond.condR = condR;
+ i->Min.MovCond.cond = cond;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_MtFCSR(HReg src)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_MtFCSR;
+ i->Min.MtFCSR.src = src;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_MfFCSR(HReg dst)
+{
+ MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_MfFCSR;
+ i->Min.MfFCSR.dst = dst;
+ return i;
+}
+
+MIPSInstr *MIPSInstr_EvCheck ( MIPSAMode* amCounter,
+ MIPSAMode* amFailAddr ) {
+ MIPSInstr* i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_EvCheck;
+ i->Min.EvCheck.amCounter = amCounter;
+ i->Min.EvCheck.amFailAddr = amFailAddr;
+ return i;
+}
+
+MIPSInstr* MIPSInstr_ProfInc ( void ) {
+ MIPSInstr* i = LibVEX_Alloc(sizeof(MIPSInstr));
+ i->tag = Min_ProfInc;
+ return i;
+}
+
+/* -------- Pretty Print instructions ------------- */
+static void ppLoadImm(HReg dst, ULong imm, Bool mode64)
+{
+ vex_printf("li ");
+ ppHRegMIPS(dst, mode64);
+ vex_printf(",0x%016llx", imm);
+}
+
+void ppMIPSInstr(MIPSInstr * i, Bool mode64)
+{
+ switch (i->tag) {
+ case Min_LI:
+ ppLoadImm(i->Min.LI.dst, i->Min.LI.imm, mode64);
+ break;
+ case Min_Alu: {
+ HReg r_srcL = i->Min.Alu.srcL;
+ MIPSRH *rh_srcR = i->Min.Alu.srcR;
+ /* generic */
+ vex_printf("%s ", showMIPSAluOp(i->Min.Alu.op,
+ toBool(rh_srcR->tag == Mrh_Imm)));
+ ppHRegMIPS(i->Min.Alu.dst, mode64);
+ vex_printf(",");
+ ppHRegMIPS(r_srcL, mode64);
+ vex_printf(",");
+ ppMIPSRH(rh_srcR, mode64);
+ return;
+ }
+ case Min_Shft: {
+ HReg r_srcL = i->Min.Shft.srcL;
+ MIPSRH *rh_srcR = i->Min.Shft.srcR;
+ vex_printf("%s ", showMIPSShftOp(i->Min.Shft.op,
+ toBool(rh_srcR->tag == Mrh_Imm),
+ i->Min.Shft.sz32));
+ ppHRegMIPS(i->Min.Shft.dst, mode64);
+ vex_printf(",");
+ ppHRegMIPS(r_srcL, mode64);
+ vex_printf(",");
+ ppMIPSRH(rh_srcR, mode64);
+ return;
+ }
+ case Min_Unary: {
+ vex_printf("%s ", showMIPSUnaryOp(i->Min.Unary.op));
+ ppHRegMIPS(i->Min.Unary.dst, mode64);
+ vex_printf(",");
+ ppHRegMIPS(i->Min.Unary.src, mode64);
+ return;
+ }
+ case Min_Cmp: {
+ vex_printf("word_compare ");
+ ppHRegMIPS(i->Min.Cmp.dst, mode64);
+ vex_printf(" = %s ( ", showMIPSCondCode(i->Min.Cmp.cond));
+ ppHRegMIPS(i->Min.Cmp.srcL, mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Cmp.srcR, mode64);
+ vex_printf(" )");
+
+ return;
+ }
+ case Min_Mul: {
+ switch (i->Min.Mul.widening) {
+ case False:
+ vex_printf("mul ");
+ ppHRegMIPS(i->Min.Mul.dst, mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Mul.srcL, mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Mul.srcR, mode64);
+ return;
+ case True:
+ vex_printf("%s%s ", i->Min.Mul.sz32 ? "mult" : "dmult",
+ i->Min.Mul.syned ? "" : "u");
+ ppHRegMIPS(i->Min.Mul.dst, mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Mul.srcL, mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Mul.srcR, mode64);
+ return;
+ }
+ break;
+ }
+ case Min_Mthi: {
+ vex_printf("mthi ");
+ ppHRegMIPS(i->Min.MtHL.src, mode64);
+ return;
+ }
+ case Min_Mtlo: {
+ vex_printf("mtlo ");
+ ppHRegMIPS(i->Min.MtHL.src, mode64);
+ return;
+ }
+ case Min_Mfhi: {
+ vex_printf("mfhi ");
+ ppHRegMIPS(i->Min.MfHL.dst, mode64);
+ return;
+ }
+ case Min_Mflo: {
+ vex_printf("mflo ");
+ ppHRegMIPS(i->Min.MfHL.dst, mode64);
+ return;
+ }
+ case Min_Macc: {
+ vex_printf("%s ", showMIPSMaccOp(i->Min.Macc.op, i->Min.Macc.syned));
+ ppHRegMIPS(i->Min.Macc.srcL, mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Macc.srcR, mode64);
+ return;
+ }
+ case Min_Div: {
+ if (!i->Min.Div.sz32)
+ vex_printf("d");
+ vex_printf("div");
+ vex_printf("%s ", i->Min.Div.syned ? "s" : "u");
+ ppHRegMIPS(i->Min.Div.srcL, mode64);
+ vex_printf(", ");
+ ppHRegMIPS(i->Min.Div.srcR, mode64);
+ return;
+ }
+ case Min_Call: {
+ Int n;
+ vex_printf("call: ");
+ if (i->Min.Call.cond != MIPScc_AL) {
+ vex_printf("if (%s) ", showMIPSCondCode(i->Min.Call.cond));
+ }
+ vex_printf("{ ");
+ ppLoadImm(hregMIPS_GPR11(mode64), i->Min.Call.target, mode64);
+
+ vex_printf(" ; mtctr r10 ; bctrl [");
+ for (n = 0; n < 32; n++) {
+ if (i->Min.Call.argiregs & (1 << n)) {
+ vex_printf("r%d", n);
+ if ((i->Min.Call.argiregs >> n) > 1)
+ vex_printf(",");
+ }
+ }
+ vex_printf("] }");
+ break;
+ }
+ case Min_XDirect:
+ vex_printf("(xDirect) ");
+ vex_printf("if (guest_COND.%s) { ",
+ showMIPSCondCode(i->Min.XDirect.cond));
+ vex_printf("move $9, 0x%x,", i->Min.XDirect.dstGA);
+ vex_printf("; sw $9, ");
+ ppMIPSAMode(i->Min.XDirect.amPC, mode64);
+ vex_printf("; move $9, $disp_cp_chain_me_to_%sEP; jalr $9; nop}",
+ i->Min.XDirect.toFastEP ? "fast" : "slow");
+ return;
+ case Min_XIndir:
+ vex_printf("(xIndir) ");
+ vex_printf("if (guest_COND.%s) { sw ",
+ showMIPSCondCode(i->Min.XIndir.cond));
+ ppHRegMIPS(i->Min.XIndir.dstGA, mode64);
+ vex_printf(", ");
+ ppMIPSAMode(i->Min.XIndir.amPC, mode64);
+ vex_printf("; move $9, $disp_indir; jalr $9; nop}");
+ return;
+ case Min_XAssisted:
+ vex_printf("(xAssisted) ");
+ vex_printf("if (guest_COND.%s) { ",
+ showMIPSCondCode(i->Min.XAssisted.cond));
+ vex_printf("sw ");
+ ppHRegMIPS(i->Min.XAssisted.dstGA, mode64);
+ vex_printf(", ");
+ ppMIPSAMode(i->Min.XAssisted.amPC, mode64);
+ vex_printf("; move $9, $IRJumpKind_to_TRCVAL(%d)",
+ (Int)i->Min.XAssisted.jk);
+ vex_printf("; move $9, $disp_assisted; jalr $9; nop; }");
+ return;
+ case Min_Load: {
+ Bool idxd = toBool(i->Min.Load.src->tag == Mam_RR);
+ UChar sz = i->Min.Load.sz;
+ UChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
+ vex_printf("l%c%s ", c_sz, idxd ? "x" : "");
+ ppHRegMIPS(i->Min.Load.dst, mode64);
+ vex_printf(",");
+ ppMIPSAMode(i->Min.Load.src, mode64);
+ return;
+ }
+ case Min_Store: {
+ UChar sz = i->Min.Store.sz;
+ Bool idxd = toBool(i->Min.Store.dst->tag == Mam_RR);
+ UChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
+ vex_printf("s%c%s ", c_sz, idxd ? "x" : "");
+ ppHRegMIPS(i->Min.Store.src, mode64);
+ vex_printf(",");
+ ppMIPSAMode(i->Min.Store.dst, mode64);
+ return;
+ }
+ case Min_LoadL: {
+ vex_printf("ll ");
+ ppHRegMIPS(i->Min.LoadL.dst, mode64);
+ vex_printf(",");
+ ppMIPSAMode(i->Min.LoadL.src, mode64);
+ return;
+ }
+ case Min_StoreC: {
+ vex_printf("sc ");
+ ppHRegMIPS(i->Min.StoreC.src, mode64);
+ vex_printf(",");
+ ppMIPSAMode(i->Min.StoreC.dst, mode64);
+ return;
+ }
+ case Min_RdWrLR: {
+ vex_printf("%s ", i->Min.RdWrLR.wrLR ? "mtlr" : "mflr");
+ ppHRegMIPS(i->Min.RdWrLR.gpr, mode64);
+ return;
+ }
+ case Min_FpUnary:
+ vex_printf("%s ", showMIPSFpOp(i->Min.FpUnary.op));
+ ppHRegMIPS(i->Min.FpUnary.dst, mode64);
+ vex_printf(",");
+ ppHRegMIPS(i->Min.FpUnary.src, mode64);
+ return;
+ case Min_FpBinary:
+ vex_printf("%s", showMIPSFpOp(i->Min.FpBinary.op));
+ ppHRegMIPS(i->Min.FpBinary.dst, mode64);
+ vex_printf(",");
+ ppHRegMIPS(i->Min.FpBinary.srcL, mode64);
+ vex_printf(",");
+ ppHRegMIPS(i->Min.FpBinary.srcR, mode64);
+ return;
+ case Min_FpConvert:
+ vex_printf("%s", showMIPSFpOp(i->Min.FpConvert.op));
+ ppHRegMIPS(i->Min.FpConvert.dst, mode64);
+ vex_printf(",");
+ ppHRegMIPS(i->Min.FpConvert.src, mode64);
+ return;
+ case Min_FpCompare:
+ vex_printf("%s ", showMIPSFpOp(i->Min.FpCompare.op));
+ ppHRegMIPS(i->Min.FpCompare.srcL, mode64);
+ vex_printf(",");
+ ppHRegMIPS(i->Min.FpCompare.srcR, mode64);
+ vex_printf(" cond: %c", i->Min.FpCompare.cond1);
+ return;
+ case Min_FpMulAcc:
+ vex_printf("%s ", showMIPSFpOp(i->Min.FpMulAcc.op));
+ ppHRegMIPS(i->Min.FpMulAcc.dst, mode64);
+ vex_printf(",");
+ ppHRegMIPS(i->Min.FpMulAcc.srcML, mode64);
+ vex_printf(",");
+ ppHRegMIPS(i->Min.FpMulAcc.srcMR, mode64);
+ vex_printf(",");
+ ppHRegMIPS(i->Min.FpMulAcc.srcAcc, mode64);
+ return;
+ case Min_FpLdSt: {
+ if (i->Min.FpLdSt.sz == 4) {
+ if (i->Min.FpLdSt.isLoad) {
+ vex_printf("lwc1 ");
+ ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
+ vex_printf(",");
+ ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
+ } else {
+ vex_printf("swc1 ");
+ ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
+ vex_printf(",");
+ ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
+ }
+ } else if (i->Min.FpLdSt.sz == 8) {
+ if (i->Min.FpLdSt.isLoad) {
+ if (mode64)
+ vex_printf("ldc1 ");
+ else
+ vex_printf("lwc1 ");
+ ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
+ vex_printf(",");
+ ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
+ } else {
+ if (mode64)
+ vex_printf("sdc1 ");
+ else
+ vex_printf("swc1 ");
+ ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
+ vex_printf(",");
+ ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
+ }
+ }
+ return;
+ }
+ case Min_MovCond: {
+ if (i->Min.MovCond.cond == MIPScc_MI) {
+ vex_printf("\ncond move\n");
+ return;
+
+ }
+ break;
+ }
+ case Min_MtFCSR: {
+ vex_printf("ctc1 ");
+ ppHRegMIPS(i->Min.MtFCSR.src, mode64);
+ vex_printf(", $31");
+ return;
+ }
+
+ case Min_MfFCSR: {
+ vex_printf("ctc1 ");
+ ppHRegMIPS(i->Min.MfFCSR.dst, mode64);
+ vex_printf(", $31");
+ return;
+ }
+ case Min_EvCheck:
+ vex_printf("(evCheck) lw $9, ");
+ ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
+ vex_printf("; addiu $9, $9, -1");
+ vex_printf("; sw $9, ");
+ ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
+ vex_printf("; bgez $t9, nofail; jalr *");
+ ppMIPSAMode(i->Min.EvCheck.amFailAddr, mode64);
+ vex_printf("; nofail:");
+ return;
+ case Min_ProfInc:
+ vex_printf("(profInc) move $9, ($NotKnownYet); "
+ "lw $8, 0($9); "
+ "addiu $8, $8, 1; "
+ "sw $8, 0($9); "
+ "sltiu $1, $8, 1; "
+ "lw $8, 4($9); "
+ "addu $8, $8, $1; "
+ "sw $8, 4($9); " );
+ return;
+ default:
+ vpanic("ppMIPSInstr");
+ break;
+ }
+}
+
+/* --------- Helpers for register allocation. --------- */
+
+void getRegUsage_MIPSInstr(HRegUsage * u, MIPSInstr * i, Bool mode64)
+{
+ initHRegUsage(u);
+ switch (i->tag) {
+ case Min_LI:
+ addHRegUse(u, HRmWrite, i->Min.LI.dst);
+ break;
+ case Min_Alu:
+ addHRegUse(u, HRmRead, i->Min.Alu.srcL);
+ addRegUsage_MIPSRH(u, i->Min.Alu.srcR);
+ addHRegUse(u, HRmWrite, i->Min.Alu.dst);
+ return;
+ case Min_Shft:
+ addHRegUse(u, HRmRead, i->Min.Shft.srcL);
+ addRegUsage_MIPSRH(u, i->Min.Shft.srcR);
+ addHRegUse(u, HRmWrite, i->Min.Shft.dst);
+ return;
+ case Min_Cmp:
+ addHRegUse(u, HRmRead, i->Min.Cmp.srcL);
+ addHRegUse(u, HRmRead, i->Min.Cmp.srcR);
+ addHRegUse(u, HRmWrite, i->Min.Cmp.dst);
+ return;
+ case Min_Unary:
+ addHRegUse(u, HRmRead, i->Min.Unary.src);
+ addHRegUse(u, HRmWrite, i->Min.Unary.dst);
+ return;
+ case Min_Mul:
+ addHRegUse(u, HRmWrite, i->Min.Mul.dst);
+ addHRegUse(u, HRmRead, i->Min.Mul.srcL);
+ addHRegUse(u, HRmRead, i->Min.Mul.srcR);
+ return;
+ case Min_Mthi:
+ case Min_Mtlo:
+ addHRegUse(u, HRmWrite, hregMIPS_HI(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_LO(mode64));
+ addHRegUse(u, HRmRead, i->Min.MtHL.src);
+ return;
+ case Min_Mfhi:
+ case Min_Mflo:
+ addHRegUse(u, HRmRead, hregMIPS_HI(mode64));
+ addHRegUse(u, HRmRead, hregMIPS_LO(mode64));
+ addHRegUse(u, HRmWrite, i->Min.MfHL.dst);
+ return;
+ case Min_MtFCSR:
+ addHRegUse(u, HRmRead, i->Min.MtFCSR.src);
+ return;
+ case Min_MfFCSR:
+ addHRegUse(u, HRmWrite, i->Min.MfFCSR.dst);
+ return;
+ case Min_Macc:
+ addHRegUse(u, HRmModify, hregMIPS_HI(mode64));
+ addHRegUse(u, HRmModify, hregMIPS_LO(mode64));
+ addHRegUse(u, HRmRead, i->Min.Macc.srcL);
+ addHRegUse(u, HRmRead, i->Min.Macc.srcR);
+ return;
+ case Min_Div:
+ addHRegUse(u, HRmWrite, hregMIPS_HI(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_LO(mode64));
+ addHRegUse(u, HRmRead, i->Min.Div.srcL);
+ addHRegUse(u, HRmRead, i->Min.Div.srcR);
+ return;
+ case Min_Call: {
+ if (i->Min.Call.cond != MIPScc_AL)
+ addHRegUse(u, HRmRead, i->Min.Call.src);
+ UInt argir;
+ addHRegUse(u, HRmWrite, hregMIPS_GPR1(mode64));
+
+ addHRegUse(u, HRmWrite, hregMIPS_GPR2(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR3(mode64));
+
+ addHRegUse(u, HRmWrite, hregMIPS_GPR4(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR5(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR6(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR7(mode64));
+
+ addHRegUse(u, HRmWrite, hregMIPS_GPR8(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR9(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR10(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR11(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR12(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR13(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR14(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR15(mode64));
+
+ addHRegUse(u, HRmWrite, hregMIPS_GPR24(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR25(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR26(mode64));
+ addHRegUse(u, HRmWrite, hregMIPS_GPR27(mode64));
+
+ /* Now we have to state any parameter-carrying registers
+ which might be read. This depends on the argiregs field. */
+ argir = i->Min.Call.argiregs;
+ if (argir & (1 << 7))
+ addHRegUse(u, HRmRead, hregMIPS_GPR7(mode64));
+ if (argir & (1 << 6))
+ addHRegUse(u, HRmRead, hregMIPS_GPR6(mode64));
+ if (argir & (1 << 5))
+ addHRegUse(u, HRmRead, hregMIPS_GPR5(mode64));
+ if (argir & (1 << 4))
+ addHRegUse(u, HRmRead, hregMIPS_GPR4(mode64));
+
+ vassert(0 == (argir & ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7))));
+ return;
+ }
+ /* XDirect/XIndir/XAssisted are also a bit subtle. They
+ conditionally exit the block. Hence we only need to list (1)
+ the registers that they read, and (2) the registers that they
+ write in the case where the block is not exited. (2) is
+ empty, hence only (1) is relevant here. */
+ case Min_XDirect:
+ addRegUsage_MIPSAMode(u, i->Min.XDirect.amPC);
+ return;
+ case Min_XIndir:
+ addHRegUse(u, HRmRead, i->Min.XIndir.dstGA);
+ addRegUsage_MIPSAMode(u, i->Min.XIndir.amPC);
+ return;
+ case Min_XAssisted:
+ addHRegUse(u, HRmRead, i->Min.XAssisted.dstGA);
+ addRegUsage_MIPSAMode(u, i->Min.XAssisted.amPC);
+ return;
+ case Min_Load:
+ addRegUsage_MIPSAMode(u, i->Min.Load.src);
+ addHRegUse(u, HRmWrite, i->Min.Load.dst);
+ return;
+ case Min_Store:
+ addHRegUse(u, HRmRead, i->Min.Store.src);
+ addRegUsage_MIPSAMode(u, i->Min.Store.dst);
+ return;
+ case Min_LoadL:
+ addRegUsage_MIPSAMode(u, i->Min.LoadL.src);
+ addHRegUse(u, HRmWrite, i->Min.LoadL.dst);
+ return;
+ case Min_StoreC:
+ addHRegUse(u, HRmWrite, i->Min.StoreC.src);
+ addHRegUse(u, HRmRead, i->Min.StoreC.src);
+ addRegUsage_MIPSAMode(u, i->Min.StoreC.dst);
+ return;
+ case Min_RdWrLR:
+ addHRegUse(u, (i->Min.RdWrLR.wrLR ? HRmRead : HRmWrite),
+ i->Min.RdWrLR.gpr);
+ return;
+ case Min_FpLdSt:
+ if (i->Min.FpLdSt.sz == 4) {
+ addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead),
+ i->Min.FpLdSt.reg);
+ addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr);
+ return;
+ } else if (i->Min.FpLdSt.sz == 8) {
+ if (mode64) {
+ addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead),
+ i->Min.FpLdSt.reg);
+ addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr);
+ } else {
+ addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead),
+ i->Min.FpLdSt.reg);
+ addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr);
+ addRegUsage_MIPSAMode(u, nextMIPSAModeFloat(i->Min.FpLdSt.addr));
+ }
+ return;
+ }
+ break;
+ case Min_FpUnary:
+ if (i->Min.FpUnary.op == Mfp_CVTD) {
+ addHRegUse(u, HRmWrite, i->Min.FpUnary.dst);
+ addHRegUse(u, HRmRead, i->Min.FpUnary.src);
+ return;
+ } else {
+ addHRegUse(u, HRmWrite, i->Min.FpUnary.dst);
+ addHRegUse(u, HRmRead, i->Min.FpUnary.src);
+ return;
+ }
+ case Min_FpBinary:
+ addHRegUse(u, HRmWrite, i->Min.FpBinary.dst);
+ addHRegUse(u, HRmRead, i->Min.FpBinary.srcL);
+ addHRegUse(u, HRmRead, i->Min.FpBinary.srcR);
+ return;
+ case Min_FpConvert:
+ addHRegUse(u, HRmWrite, i->Min.FpConvert.dst);
+ addHRegUse(u, HRmRead, i->Min.FpConvert.src);
+ return;
+ case Min_FpCompare:
+ addHRegUse(u, HRmWrite, i->Min.FpCompare.dst);
+ addHRegUse(u, HRmRead, i->Min.FpCompare.srcL);
+ addHRegUse(u, HRmRead, i->Min.FpCompare.srcR);
+ return;
+ case Min_MovCond:
+ if (i->Min.MovCond.srcR->tag == Mrh_Reg) {
+ addHRegUse(u, HRmRead, i->Min.MovCond.srcR->Mrh.Reg.reg);
+ }
+ addHRegUse(u, HRmRead, i->Min.MovCond.srcL);
+ addHRegUse(u, HRmRead, i->Min.MovCond.condR);
+ addHRegUse(u, HRmWrite, i->Min.MovCond.dst);
+ return;
+ case Min_EvCheck:
+ /* We expect both amodes only to mention %ebp, so this is in
+ fact pointless, since %ebp isn't allocatable, but anyway.. */
+ addRegUsage_MIPSAMode(u, i->Min.EvCheck.amCounter);
+ addRegUsage_MIPSAMode(u, i->Min.EvCheck.amFailAddr);
+ return;
+ case Min_ProfInc:
+ /* does not use any registers. */
+ return;
+ default:
+ ppMIPSInstr(i, mode64);
+ vpanic("getRegUsage_MIPSInstr");
+ break;
+ }
+}
+
+/* local helper */
+static void mapReg(HRegRemap * m, HReg * r)
+{
+ *r = lookupHRegRemap(m, *r);
+}
+
+void mapRegs_MIPSInstr(HRegRemap * m, MIPSInstr * i, Bool mode64)
+{
+ switch (i->tag) {
+ case Min_LI:
+ mapReg(m, &i->Min.LI.dst);
+ break;
+ case Min_Alu:
+ mapReg(m, &i->Min.Alu.srcL);
+ mapRegs_MIPSRH(m, i->Min.Alu.srcR);
+ mapReg(m, &i->Min.Alu.dst);
+ return;
+ case Min_Shft:
+ mapReg(m, &i->Min.Shft.srcL);
+ mapRegs_MIPSRH(m, i->Min.Shft.srcR);
+ mapReg(m, &i->Min.Shft.dst);
+ return;
+ case Min_Cmp:
+ mapReg(m, &i->Min.Cmp.srcL);
+ mapReg(m, &i->Min.Cmp.srcR);
+ mapReg(m, &i->Min.Cmp.dst);
+ return;
+ case Min_Unary:
+ mapReg(m, &i->Min.Unary.src);
+ mapReg(m, &i->Min.Unary.dst);
+ return;
+ case Min_Mul:
+ mapReg(m, &i->Min.Mul.dst);
+ mapReg(m, &i->Min.Mul.srcL);
+ mapReg(m, &i->Min.Mul.srcR);
+ return;
+ case Min_Mthi:
+ case Min_Mtlo:
+ mapReg(m, &i->Min.MtHL.src);
+ return;
+ case Min_Mfhi:
+ case Min_Mflo:
+ mapReg(m, &i->Min.MfHL.dst);
+ return;
+ case Min_Macc:
+ mapReg(m, &i->Min.Macc.srcL);
+ mapReg(m, &i->Min.Macc.srcR);
+ return;
+ case Min_Div:
+ mapReg(m, &i->Min.Div.srcL);
+ mapReg(m, &i->Min.Div.srcR);
+ return;
+ case Min_Call:
+ {
+ if (i->Min.Call.cond != MIPScc_AL)
+ mapReg(m, &i->Min.Call.src);
+ return;
+ }
+ case Min_XDirect:
+ mapRegs_MIPSAMode(m, i->Min.XDirect.amPC);
+ return;
+ case Min_XIndir:
+ mapReg(m, &i->Min.XIndir.dstGA);
+ mapRegs_MIPSAMode(m, i->Min.XIndir.amPC);
+ return;
+ case Min_XAssisted:
+ mapReg(m, &i->Min.XAssisted.dstGA);
+ mapRegs_MIPSAMode(m, i->Min.XAssisted.amPC);
+ return;
+ case Min_Load:
+ mapRegs_MIPSAMode(m, i->Min.Load.src);
+ mapReg(m, &i->Min.Load.dst);
+ return;
+ case Min_Store:
+ mapReg(m, &i->Min.Store.src);
+ mapRegs_MIPSAMode(m, i->Min.Store.dst);
+ return;
+ case Min_LoadL:
+ mapRegs_MIPSAMode(m, i->Min.LoadL.src);
+ mapReg(m, &i->Min.LoadL.dst);
+ return;
+ case Min_StoreC:
+ mapReg(m, &i->Min.StoreC.src);
+ mapRegs_MIPSAMode(m, i->Min.StoreC.dst);
+ return;
+ case Min_RdWrLR:
+ mapReg(m, &i->Min.RdWrLR.gpr);
+ return;
+ case Min_FpLdSt:
+ if (i->Min.FpLdSt.sz == 4) {
+ mapReg(m, &i->Min.FpLdSt.reg);
+ mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr);
+ return;
+ } else if (i->Min.FpLdSt.sz == 8) {
+ if (mode64) {
+ mapReg(m, &i->Min.FpLdSt.reg);
+ mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr);
+ } else {
+ mapReg(m, &i->Min.FpLdSt.reg);
+ mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr);
+ mapRegs_MIPSAMode(m, nextMIPSAModeFloat(i->Min.FpLdSt.addr));
+ }
+ return;
+ }
+ break;
+ case Min_FpUnary:
+ if (i->Min.FpUnary.op == Mfp_CVTD) {
+ mapReg(m, &i->Min.FpUnary.dst);
+ mapReg(m, &i->Min.FpUnary.src);
+ return;
+ } else {
+ mapReg(m, &i->Min.FpUnary.dst);
+ mapReg(m, &i->Min.FpUnary.src);
+ return;
+ }
+ case Min_FpBinary:
+ mapReg(m, &i->Min.FpBinary.dst);
+ mapReg(m, &i->Min.FpBinary.srcL);
+ mapReg(m, &i->Min.FpBinary.srcR);
+ return;
+ case Min_FpConvert:
+ mapReg(m, &i->Min.FpConvert.dst);
+ mapReg(m, &i->Min.FpConvert.src);
+ return;
+ case Min_FpCompare:
+ mapReg(m, &i->Min.FpCompare.dst);
+ mapReg(m, &i->Min.FpCompare.srcL);
+ mapReg(m, &i->Min.FpCompare.srcR);
+ return;
+ case Min_MtFCSR:
+ mapReg(m, &i->Min.MtFCSR.src);
+ return;
+ case Min_MfFCSR:
+ mapReg(m, &i->Min.MfFCSR.dst);
+ return;
+ case Min_MovCond:
+ if (i->Min.MovCond.srcR->tag == Mrh_Reg) {
+ mapReg(m, &(i->Min.MovCond.srcR->Mrh.Reg.reg));
+ }
+ mapReg(m, &i->Min.MovCond.srcL);
+ mapReg(m, &i->Min.MovCond.condR);
+ mapReg(m, &i->Min.MovCond.dst);
+
+ return;
+ case Min_EvCheck:
+ /* We expect both amodes only to mention %ebp, so this is in
+ fact pointless, since %ebp isn't allocatable, but anyway.. */
+ mapRegs_MIPSAMode(m, i->Min.EvCheck.amCounter);
+ mapRegs_MIPSAMode(m, i->Min.EvCheck.amFailAddr);
+ return;
+ case Min_ProfInc:
+ /* does not use any registers. */
+ return;
+ default:
+ ppMIPSInstr(i, mode64);
+ vpanic("mapRegs_MIPSInstr");
+ break;
+ }
+
+}
+
+/* Figure out if i represents a reg-reg move, and if so assign the
+ source and destination to *src and *dst. If in doubt say No. Used
+ by the register allocator to do move coalescing.
+*/
+Bool isMove_MIPSInstr(MIPSInstr * i, HReg * src, HReg * dst)
+{
+ /* Moves between integer regs */
+ if (i->tag == Min_Alu) {
+ // or Rd,Rs,Rs == mr Rd,Rs
+ if (i->Min.Alu.op != Malu_OR)
+ return False;
+ if (i->Min.Alu.srcR->tag != Mrh_Reg)
+ return False;
+ if (i->Min.Alu.srcR->Mrh.Reg.reg != i->Min.Alu.srcL)
+ return False;
+ *src = i->Min.Alu.srcL;
+ *dst = i->Min.Alu.dst;
+ return True;
+ }
+ return False;
+}
+
+/* Generate mips spill/reload instructions under the direction of the
+ register allocator.
+*/
+void genSpill_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg,
+ Int offsetB, Bool mode64)
+{
+ MIPSAMode *am;
+ vassert(offsetB >= 0);
+ vassert(!hregIsVirtual(rreg));
+ *i1 = *i2 = NULL;
+ am = MIPSAMode_IR(offsetB, GuestStatePointer(mode64));
+
+ switch (hregClass(rreg)) {
+ case HRcInt64:
+ vassert(mode64);
+ *i1 = MIPSInstr_Store(8, am, rreg, mode64);
+ break;
+ case HRcInt32:
+ vassert(!mode64);
+ *i1 = MIPSInstr_Store(4, am, rreg, mode64);
+ break;
+ case HRcFlt32:
+ vassert(!mode64);
+ *i1 = MIPSInstr_FpLdSt(False /*Store */ , 4, rreg, am);
+ break;
+ case HRcFlt64:
+ *i1 = MIPSInstr_FpLdSt(False /*Store */ , 8, rreg, am);
+ break;
+ default:
+ ppHRegClass(hregClass(rreg));
+ vpanic("genSpill_MIPS: unimplemented regclass");
+ break;
+ }
+}
+
+void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg,
+ Int offsetB, Bool mode64)
+{
+ MIPSAMode *am;
+ vassert(!hregIsVirtual(rreg));
+ am = MIPSAMode_IR(offsetB, GuestStatePointer(mode64));
+
+ switch (hregClass(rreg)) {
+ case HRcInt64:
+ vassert(mode64);
+ *i1 = MIPSInstr_Load(8, rreg, am, mode64);
+ break;
+ case HRcInt32:
+ vassert(!mode64);
+ *i1 = MIPSInstr_Load(4, rreg, am, mode64);
+ break;
+ case HRcFlt32:
+ if (mode64)
+ *i1 = MIPSInstr_FpLdSt(True /*Load */ , 8, rreg, am);
+ else
+ *i1 = MIPSInstr_FpLdSt(True /*Load */ , 4, rreg, am);
+ break;
+ case HRcFlt64:
+ *i1 = MIPSInstr_FpLdSt(True /*Load */ , 8, rreg, am);
+ break;
+ default:
+ ppHRegClass(hregClass(rreg));
+ vpanic("genReload_MIPS: unimplemented regclass");
+ break;
+ }
+}
+
+/* --------- The mips assembler --------- */
+
+static UInt iregNo(HReg r, Bool mode64)
+{
+ UInt n;
+ vassert(hregClass(r) == mode64 ? HRcInt64 : HRcInt32);
+ vassert(!hregIsVirtual(r));
+ n = hregNumber(r);
+ vassert(n <= 32);
+ return n;
+}
+
+static UChar fregNo(HReg r, Bool mode64)
+{
+ UInt n;
+ vassert(hregClass(r) == mode64 ? HRcFlt64 : HRcFlt32);
+ vassert(!hregIsVirtual(r));
+ n = hregNumber(r);
+ vassert(n <= 31);
+ return n;
+}
+
+static UChar dregNo(HReg r)
+{
+ UInt n;
+ vassert(hregClass(r) == HRcFlt64);
+ vassert(!hregIsVirtual(r));
+ n = hregNumber(r);
+ vassert(n <= 31);
+ return n;
+}
+
+/* Emit 32bit instruction */
+static UChar *emit32(UChar * p, UInt w32)
+{
+#if defined (_MIPSEL)
+ *p++ = toUChar(w32 & 0x000000FF);
+ *p++ = toUChar((w32 >> 8) & 0x000000FF);
+ *p++ = toUChar((w32 >> 16) & 0x000000FF);
+ *p++ = toUChar((w32 >> 24) & 0x000000FF);
+#elif defined (_MIPSEB)
+ *p++ = toUChar((w32 >> 24) & 0x000000FF);
+ *p++ = toUChar((w32 >> 16) & 0x000000FF);
+ *p++ = toUChar((w32 >> 8) & 0x000000FF);
+ *p++ = toUChar(w32 & 0x000000FF);
+#endif
+ return p;
+}
+/* Fetch an instruction */
+static UInt fetch32 ( UChar* p )
+{
+ UInt w32 = 0;
+#if defined (_MIPSEL)
+ w32 |= ((0xFF & (UInt)p[0]) << 0);
+ w32 |= ((0xFF & (UInt)p[1]) << 8);
+ w32 |= ((0xFF & (UInt)p[2]) << 16);
+ w32 |= ((0xFF & (UInt)p[3]) << 24);
+#elif defined (_MIPSEB)
+ w32 |= ((0xFF & (UInt)p[0]) << 24);
+ w32 |= ((0xFF & (UInt)p[1]) << 16);
+ w32 |= ((0xFF & (UInt)p[2]) << 8);
+ w32 |= ((0xFF & (UInt)p[3]) << 0);
+#endif
+ return w32;
+}
+
+/* physical structure of mips instructions */
+/* type I : opcode - 6 bits
+ rs - 5 bits
+ rt - 5 bits
+ immediate - 16 bits
+*/
+static UChar *mkFormI(UChar * p, UInt opc, UInt rs, UInt rt, UInt imm)
+{
+ UInt theInstr;
+ vassert(opc < 0x40);
+ vassert(rs < 0x20);
+ vassert(rt < 0x20);
+ imm = imm & 0xFFFF;
+ theInstr = ((opc << 26) | (rs << 21) | (rt << 16) | (imm));
+ return emit32(p, theInstr);
+}
+
+/* type R: opcode - 6 bits
+ rs - 5 bits
+ rt - 5 bits
+ rd - 5 bits
+ sa - 5 bits
+ func - 6 bits
+*/
+static UChar *mkFormR(UChar * p, UInt opc, UInt rs, UInt rt, UInt rd, UInt sa,
+ UInt func)
+{
+ if (rs >= 0x20)
+ vex_printf("rs = %d\n", rs);
+ UInt theInstr;
+ vassert(opc < 0x40);
+ vassert(rs < 0x20);
+ vassert(rt < 0x20);
+ vassert(rd < 0x20);
+ vassert(sa < 0x20);
+ func = func & 0xFFFF;
+ theInstr = ((opc << 26) | (rs << 21) | (rt << 16) | (rd << 11) | (sa << 6) |
+ (func));
+
+ return emit32(p, theInstr);
+}
+
+static UChar *mkFormS(UChar * p, UInt opc1, UInt rRD, UInt rRS, UInt rRT,
+ UInt sa, UInt opc2)
+{
+ UInt theInstr;
+ vassert(opc1 <= 0x3F);
+ vassert(rRD < 0x20);
+ vassert(rRS < 0x20);
+ vassert(rRT < 0x20);
+ vassert(opc2 <= 0x3F);
+ vassert(sa >= 0 && sa <= 0x3F);
+
+ theInstr = ((opc1 << 26) | (rRS << 21) | (rRT << 16) | (rRD << 11) |
+ ((sa & 0x1F) << 6) | (opc2));
+
+ return emit32(p, theInstr);
+}
+
+static UChar *doAMode_IR(UChar * p, UInt opc1, UInt rSD, MIPSAMode * am,
+ Bool mode64)
+{
+ UInt rA, idx, r_dst;
+ vassert(am->tag == Mam_IR);
+ vassert(am->Mam.IR.index < 0x10000);
+
+ rA = iregNo(am->Mam.IR.base, mode64);
+ idx = am->Mam.IR.index;
+
+ if (rSD == 33 || rSD == 34)
+ r_dst = 24;
+ else
+ r_dst = rSD;
+
+ if (opc1 < 40) {
+ //load
+ if (rSD == 33)
+ /* mfhi */
+ p = mkFormR(p, 0, 0, 0, r_dst, 0, 16);
+ else if (rSD == 34)
+ /* mflo */
+ p = mkFormR(p, 0, 0, 0, r_dst, 0, 18);
+ }
+
+ p = mkFormI(p, opc1, rA, r_dst, idx);
+
+ if (opc1 >= 40) {
+ //store
+ if (rSD == 33)
+ /* mthi */
+ p = mkFormR(p, 0, r_dst, 0, 0, 0, 17);
+ else if (rSD == 34)
+ /* mtlo */
+ p = mkFormR(p, 0, r_dst, 0, 0, 0, 19);
+ }
+
+ return p;
+}
+
+static UChar *doAMode_RR(UChar * p, UInt opc1, UInt rSD, MIPSAMode * am,
+ Bool mode64)
+{
+ UInt rA, rB, r_dst;
+ vassert(am->tag == Mam_RR);
+
+ rA = iregNo(am->Mam.RR.base, mode64);
+ rB = iregNo(am->Mam.RR.index, mode64);
+
+ if (rSD == 33 || rSD == 34)
+ r_dst = 24;
+ else
+ r_dst = rSD;
+
+ if (opc1 < 40) {
+ //load
+ if (rSD == 33)
+ /* mfhi */
+ p = mkFormR(p, 0, 0, 0, r_dst, 0, 16);
+ else if (rSD == 34)
+ /* mflo */
+ p = mkFormR(p, 0, 0, 0, r_dst, 0, 18);
+ }
+ /* addiu sp, sp, -4
+ * sw rA, 0(sp)
+ * addu rA, rA, rB
+ * sw/lw r_dst, 0(rA)
+ * lw rA, 0(sp)
+ * addiu sp, sp, 4 */
+ if (mode64) {
+ p = mkFormI(p, 25, 29, 29, 0xFFFC);
+ p = mkFormI(p, 63, 29, rA, 0);
+ p = mkFormR(p, 0, rA, rB, rA, 0, 45);
+ p = mkFormI(p, opc1, rA, r_dst, 0);
+ p = mkFormI(p, 55, 29, rA, 0);
+ p = mkFormI(p, 25, 29, 29, 4);
+ } else {
+ p = mkFormI(p, 9, 29, 29, 0xFFFC);
+ p = mkFormI(p, 43, 29, rA, 0);
+ p = mkFormR(p, 0, rA, rB, rA, 0, 33);
+ p = mkFormI(p, opc1, rA, r_dst, 0);
+ p = mkFormI(p, 35, 29, rA, 0);
+ p = mkFormI(p, 9, 29, 29, 4);
+ }
+ if (opc1 >= 40) {
+ //store
+ if (rSD == 33)
+ /* mthi */
+ p = mkFormR(p, 0, r_dst, 0, 0, 0, 17);
+ else if (rSD == 34)
+ /* mtlo */
+ p = mkFormR(p, 0, r_dst, 0, 0, 0, 19);
+ }
+
+ return p;
+}
+
+/* Load imm to r_dst */
+static UChar *mkLoadImm(UChar * p, UInt r_dst, ULong imm, Bool mode64)
+{
+ if (!mode64) {
+ vassert(r_dst < 0x20);
+ UInt u32 = (UInt) imm;
+ Int s32 = (Int) u32;
+ Long s64 = (Long) s32;
+ imm = (ULong) s64;
+ }
+
+ if (imm >= 0xFFFFFFFFFFFF8000ULL || imm < 0x8000) {
+ // sign-extendable from 16 bits
+ // addiu r_dst,0,imm => li r_dst,imm
+ p = mkFormI(p, 9, 0, r_dst, imm & 0xFFFF);
+ } else {
+ if (imm >= 0xFFFFFFFF80000000ULL || imm < 0x80000000ULL) {
+ // sign-extendable from 32 bits
+ // addiu r_dst,r0,(imm>>16) => lis r_dst, (imm>>16)
+ // lui r_dst, (imm>>16)
+ p = mkFormI(p, 15, 0, r_dst, (imm >> 16) & 0xFFFF);
+ // ori r_dst, r_dst, (imm & 0xFFFF)
+ p = mkFormI(p, 13, r_dst, r_dst, imm & 0xFFFF);
+ } else {
+ vassert(mode64);
+ // lui load in upper half of low word
+ p = mkFormI(p, 15, 0, r_dst, (imm >> 48) & 0xFFFF);
+ // ori
+ p = mkFormI(p, 13, r_dst, r_dst, (imm >> 32) & 0xFFFF);
+ //shift
+ p = mkFormS(p, 0, r_dst, 0, r_dst, 16, 56);
+ // ori
+ p = mkFormI(p, 13, r_dst, r_dst, (imm >> 16) & 0xFFFF);
+ //shift
+ p = mkFormS(p, 0, r_dst, 0, r_dst, 16, 56);
+ // ori
+ p = mkFormI(p, 13, r_dst, r_dst, imm & 0xFFFF);
+ }
+ }
+ return p;
+}
+
+/* A simplified version of mkLoadImm that always generates 2 or 5
+ instructions (32 or 64 bits respectively) even if it could generate
+ fewer. This is needed for generating fixed sized patchable
+ sequences. */
+static UChar* mkLoadImm_EXACTLY2or5 ( UChar* p,
+ UInt r_dst, ULong imm, Bool mode64 )
+{
+ vassert(r_dst < 0x20);
+
+ if (!mode64) {
+ /* In 32-bit mode, make sure the top 32 bits of imm are a sign
+ extension of the bottom 32 bits. (Probably unnecessary.) */
+ UInt u32 = (UInt)imm;
+ Int s32 = (Int)u32;
+ Long s64 = (Long)s32;
+ imm = (ULong)s64;
+ }
+
+ if (!mode64) {
+ // sign-extendable from 32 bits
+ // addiu r_dst,r0,(imm>>16) => lis r_dst, (imm>>16)
+ // lui r_dst, (imm>>16)
+ p = mkFormI(p, 15, 0, r_dst, (imm >> 16) & 0xFFFF);
+ // ori r_dst, r_dst, (imm & 0xFFFF)
+ p = mkFormI(p, 13, r_dst, r_dst, imm & 0xFFFF);
+ } else {
+ vassert(0);
+ }
+ return p;
+}
+
+/* Checks whether the sequence of bytes at p was indeed created
+ by mkLoadImm_EXACTLY2or5 with the given parameters. */
+static Bool isLoadImm_EXACTLY2or5 ( UChar* p_to_check,
+ UInt r_dst, ULong imm, Bool mode64 )
+{
+ vassert(r_dst < 0x20);
+ Bool ret;
+ if (!mode64) {
+ /* In 32-bit mode, make sure the top 32 bits of imm are a sign
+ extension of the bottom 32 bits. (Probably unnecessary.) */
+ UInt u32 = (UInt)imm;
+ Int s32 = (Int)u32;
+ Long s64 = (Long)s32;
+ imm = (ULong)s64;
+ }
+
+ if (!mode64) {
+ UInt expect[2] = { 0, 0 };
+ UChar* p = (UChar*)&expect[0];
+ // lui r_dst, (imm>>16)
+ p = mkFormI(p, 15, 0, r_dst, (imm >> 16) & 0xFFFF);
+ // ori r_dst, r_dst, (imm & 0xFFFF)
+ p = mkFormI(p, 13, r_dst, r_dst, imm & 0xFFFF);
+ vassert(p == (UChar*)&expect[2]);
+
+ ret = fetch32(p_to_check + 0) == expect[0]
+ && fetch32(p_to_check + 4) == expect[1];
+
+ } else {
+ vassert(0);
+ }
+ return ret;
+}
+
+/* Generate a machine-word sized load or store. Simplified version of
+ the Min_Load and Min_Store cases below. */
+static UChar* do_load_or_store_machine_word (
+ UChar* p, Bool isLoad,
+ UInt reg, MIPSAMode* am, Bool mode64 )
+{
+ if (isLoad) { /* load */
+ UInt opc1, sz = mode64 ? 8 : 4;
+ switch (am->tag) {
+ case Mam_IR:
+ if (mode64) {
+ vassert(0 == (am->Mam.IR.index & 3));
+ }
+ switch (sz) {
+ case 1:
+ opc1 = 32;
+ break;
+ case 2:
+ opc1 = 33;
+ break;
+ case 4:
+ opc1 = 35;
+ break;
+ case 8:
+ opc1 = 55;
+ vassert(mode64);
+ break;
+ default:
+ vassert(0);
+ break;
+ }
+ p = doAMode_IR(p, opc1, reg, am, mode64);
+ break;
+ case Mam_RR:
+ /* we could handle this case, but we don't expect to ever
+ need to. */
+ vassert(0);
+ break;
+ default:
+ vassert(0);
+ break;
+ }
+ } else /* store */ {
+ UInt opc1, sz = mode64 ? 8 : 4;
+ switch (am->tag) {
+ case Mam_IR:
+ if (mode64) {
+ vassert(0 == (am->Mam.IR.index & 3));
+ }
+ switch (sz) {
+ case 1:
+ opc1 = 40;
+ break;
+ case 2:
+ opc1 = 41;
+ break;
+ case 4:
+ opc1 = 43;
+ break;
+ case 8:
+ vassert(mode64);
+ opc1 = 63;
+ break;
+ default:
+ vassert(0);
+ break;
+ }
+ p = doAMode_IR(p, opc1, reg, am, mode64);
+ break;
+ case Mam_RR:
+ /* we could handle this case, but we don't expect to ever
+ need to. */
+ vassert(0);
+ break;
+ default:
+ vassert(0);
+ break;
+ }
+ }
+ return p;
+}
+
+/* Move r_dst to r_src */
+static UChar *mkMoveReg(UChar * p, UInt r_dst, UInt r_src)
+{
+ vassert(r_dst < 0x20);
+ vassert(r_src < 0x20);
+
+ if (r_dst != r_src) {
+ /* or r_dst, r_src, r_src */
+ p = mkFormR(p, 0, r_src, r_src, r_dst, 0, 37);
+ }
+ return p;
+}
+
+/* Emit an instruction into buf and return the number of bytes used.
+ Note that buf is not the insn's final place, and therefore it is
+ imperative to emit position-independent code. If the emitted
+ instruction was a profiler inc, set *is_profInc to True, else
+ leave it unchanged. */
+Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, MIPSInstr* i,
+ Bool mode64,
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted )
+{
+ UChar *p = &buf[0];
+ UChar *ptmp = p;
+ vassert(nbuf >= 32);
+
+ switch (i->tag) {
+ case Min_MovCond: {
+ MIPSRH *srcR = i->Min.MovCond.srcR;
+ UInt condR = iregNo(i->Min.MovCond.condR, mode64);
+ UInt dst = iregNo(i->Min.MovCond.dst, mode64);
+
+ UInt srcL = iregNo(i->Min.MovCond.srcL, mode64);
+
+ p = mkMoveReg(p, dst, srcL);
+ if (i->Min.MovCond.cond == MIPScc_MI) {
+ p = mkFormI(p, 7, condR, 0, 2); //bgtz cond,2
+ }
+
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0); //nop
+
+ if (srcR->tag == Mrh_Reg) {
+ //or dst,src,src
+ p = mkMoveReg(p, dst, iregNo(srcR->Mrh.Reg.reg, mode64));
+ /*p = mkFormR(p, 0, dst, iregNo(src->Mrh.Reg.reg, mode64),
+ iregNo(src->Mrh.Reg.reg, mode64), 0, 37);*/
+ } else {
+ p = mkLoadImm(p, dst, srcR->Mrh.Imm.imm16, mode64);
+ }
+ }
+ goto done;
+
+ case Min_LI:
+ p = mkLoadImm(p, iregNo(i->Min.LI.dst, mode64), i->Min.LI.imm, mode64);
+ goto done;
+
+ case Min_Alu: {
+ MIPSRH *srcR = i->Min.Alu.srcR;
+ Bool immR = toBool(srcR->tag == Mrh_Imm);
+ UInt r_dst = iregNo(i->Min.Alu.dst, mode64);
+ UInt r_srcL = iregNo(i->Min.Alu.srcL, mode64);
+ UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->Mrh.Reg.reg, mode64);
+
+ switch (i->Min.Alu.op) {
+ /*Malu_ADD, Malu_SUB, Malu_AND, Malu_OR, Malu_NOR, Malu_XOR */
+ case Malu_ADD:
+ if (immR) {
+ vassert(srcR->Mrh.Imm.imm16 != 0x8000);
+ if (srcR->Mrh.Imm.syned)
+ /* addi */
+ p = mkFormI(p, 9, r_srcL, r_dst, srcR->Mrh.Imm.imm16);
+ else
+ /* addiu */
+ p = mkFormI(p, 9, r_srcL, r_dst, srcR->Mrh.Imm.imm16);
+ } else {
+ /* addu */
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 33);
+ }
+ break;
+ case Malu_SUB:
+ if (immR) {
+ /* addi , but with negated imm */
+ vassert(srcR->Mrh.Imm.syned);
+ vassert(srcR->Mrh.Imm.imm16 != 0x8000);
+ p = mkFormI(p, 8, r_srcL, r_dst, (-srcR->Mrh.Imm.imm16));
+ } else {
+ /* subu */
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 35);
+ }
+ break;
+ case Malu_AND:
+ if (immR) {
+ /* andi */
+ vassert(!srcR->Mrh.Imm.syned);
+ p = mkFormI(p, 12, r_srcL, r_dst, srcR->Mrh.Imm.imm16);
+ } else {
+ /* and */
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 36);
+ }
+ break;
+ case Malu_OR:
+ if (immR) {
+ /* ori */
+ vassert(!srcR->Mrh.Imm.syned);
+ p = mkFormI(p, 13, r_srcL, r_dst, srcR->Mrh.Imm.imm16);
+ } else {
+ /* or */
+ if (r_srcL == 33)
+ //MFHI
+ p = mkFormR(p, 0, 0, 0, r_dst, 0, 16);
+ else if (r_srcL == 34)
+ //MFLO
+ p = mkFormR(p, 0, 0, 0, r_dst, 0, 18);
+ else if (r_dst == 33)
+ //MTHI
+ p = mkFormR(p, 0, r_srcL, 0, 0, 0, 17);
+ else if (r_dst == 34)
+ //MTLO
+ p = mkFormR(p, 0, r_srcL, 0, 0, 0, 19);
+ else
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 37);
+ }
+ break;
+ case Malu_NOR:
+ /* nor */
+ vassert(!immR);
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 39);
+ break;
+ case Malu_XOR:
+ if (immR) {
+ /* xori */
+ vassert(!srcR->Mrh.Imm.syned);
+ p = mkFormI(p, 14, r_srcL, r_dst, srcR->Mrh.Imm.imm16);
+ } else {
+ /* xor */
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 38);
+ }
+ break;
+
+ default:
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Min_Shft: {
+ MIPSRH *srcR = i->Min.Shft.srcR;
+ Bool sz32 = i->Min.Shft.sz32;
+ Bool immR = toBool(srcR->tag == Mrh_Imm);
+ UInt r_dst = iregNo(i->Min.Shft.dst, mode64);
+ UInt r_srcL = iregNo(i->Min.Shft.srcL, mode64);
+ UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->Mrh.Reg.reg,
+ mode64);
+ if (!mode64)
+ vassert(sz32);
+ switch (i->Min.Shft.op) {
+ case Mshft_SLL:
+ if (sz32) {
+ if (immR) {
+ UInt n = srcR->Mrh.Imm.imm16;
+ vassert(n >= 0 && n < 32);
+ p = mkFormS(p, 0, r_dst, 0, r_srcL, n, 0);
+ } else {
+ /* shift variable */
+ p = mkFormS(p, 0, r_dst, r_srcR, r_srcL, 0, 4);
+ }
+ } else {
+ if (immR) {
+ UInt n = srcR->Mrh.Imm.imm16;
+ vassert((n >= 0 && n < 32) || (n > 31 && n < 64));
+ if (n >= 0 && n < 32) {
+ p = mkFormS(p, 0, r_dst, 0, r_srcL, n, 56);
+ } else {
+ p = mkFormS(p, 0, r_dst, 0, r_srcL, n - 32, 60);
+ }
+ } else {
+ p = mkFormS(p, 0, r_dst, r_srcR, r_srcL, 0, 20);
+ }
+ }
+ break;
+
+ case Mshft_SRL:
+ if (sz32) {
+ // SRL, SRLV
+ if (immR) {
+ UInt n = srcR->Mrh.Imm.imm16;
+ vassert(n >= 0 && n < 32);
+ p = mkFormS(p, 0, r_dst, 0, r_srcL, n, 2);
+ } else {
+ /* shift variable */
+ p = mkFormS(p, 0, r_dst, r_srcR, r_srcL, 0, 6);
+ }
+ } else {
+ // DSRL, DSRL32, DSRLV
+ if (immR) {
+ UInt n = srcR->Mrh.Imm.imm16;
+ vassert((n >= 0 && n < 32) || (n > 31 && n < 64));
+ if (n >= 0 && n < 32) {
+ p = mkFormS(p, 0, r_dst, 0, r_srcL, n, 58);
+ } else {
+ p = mkFormS(p, 0, r_dst, 0, r_srcL, n - 32, 62);
+ }
+ } else {
+ p = mkFormS(p, 0, r_dst, r_srcR, r_srcL, 0, 22);
+ }
+ }
+ break;
+
+ case Mshft_SRA:
+ if (sz32) {
+ // SRA, SRAV
+ if (immR) {
+ UInt n = srcR->Mrh.Imm.imm16;
+ vassert(n >= 0 && n < 32);
+ p = mkFormS(p, 0, r_dst, 0, r_srcL, n, 3);
+ } else {
+ /* shift variable */
+ p = mkFormS(p, 0, r_dst, r_srcR, r_srcL, 0, 7);
+ }
+ } else {
+ // DSRA, DSRA32, DSRAV
+ if (immR) {
+ UInt n = srcR->Mrh.Imm.imm16;
+ vassert((n >= 0 && n < 32) || (n > 31 && n < 64));
+ if (n >= 0 && n < 32) {
+ p = mkFormS(p, 0, r_dst, 0, r_srcL, n, 59);
+ } else {
+ p = mkFormS(p, 0, r_dst, 0, r_srcL, n - 32, 63);
+ }
+ } else {
+ p = mkFormS(p, 0, r_dst, r_srcR, r_srcL, 0, 23);
+ }
+ }
+ break;
+
+ default:
+ goto bad;
+ }
+
+ goto done;
+ }
+
+ case Min_Unary: {
+ UInt r_dst = iregNo(i->Min.Unary.dst, mode64);
+ UInt r_src = iregNo(i->Min.Unary.src, mode64);
+
+ switch (i->Min.Unary.op) {
+ /*Mun_CLO, Mun_CLZ, Mun_NOP */
+ case Mun_CLO: //clo
+ p = mkFormR(p, 28, r_src, 0 /*whatever */ , r_dst, 0, 33);
+ break;
+ case Mun_CLZ: //clz
+ p = mkFormR(p, 28, r_src, 0 /*whatever */ , r_dst, 0, 32);
+ break;
+ case Mun_NOP: //nop (sll r0,r0,0)
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0);
+ break;
+ }
+ goto done;
+ }
+
+ case Min_Cmp: {
+ UInt r_srcL = iregNo(i->Min.Cmp.srcL, mode64);
+ UInt r_srcR = iregNo(i->Min.Cmp.srcR, mode64);
+ UInt r_dst = iregNo(i->Min.Cmp.dst, mode64);
+
+ switch (i->Min.Cmp.cond) {
+ case MIPScc_EQ:
+ /* addiu r_dst, r0, 1
+ beq r_srcL, r_srcR, 2
+ nop
+ addiu r_dst, r0, 0
+ */
+ p = mkFormI(p, 9, 0, r_dst, 1);
+ p = mkFormI(p, 4, r_srcL, r_srcR, 2);
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0);
+ p = mkFormI(p, 9, 0, r_dst, 0);
+ break;
+ case MIPScc_NE:
+ /* addiu r_dst, r0, 1
+ bne r_srcL, r_srcR, 2
+ nop
+ addiu r_dst, r0, 0
+ */
+ p = mkFormI(p, 9, 0, r_dst, 1);
+ p = mkFormI(p, 5, r_srcL, r_srcR, 2);
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0);
+ p = mkFormI(p, 9, 0, r_dst, 0);
+ break;
+ case MIPScc_LT:
+ /* slt r_dst, r_srcL, r_srcR */
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 42);
+ break;
+ case MIPScc_LO:
+ /* sltu r_dst, r_srcL, r_srcR */
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 43);
+ break;
+ case MIPScc_LE:
+ /* addiu r_dst, r0, 1
+ beq r_srcL, r_srcR, 2
+ nop
+ slt r_dst, r_srcL, r_srcR */
+ p = mkFormI(p, 9, 0, r_dst, 1);
+ p = mkFormI(p, 4, r_srcL, r_srcR, 2);
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0);
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 42);
+ break;
+ case MIPScc_LS:
+ /* addiu r_dst, r0, 1
+ beq r_srcL, r_srcR, 2
+ nop
+ sltu r_dst, r_srcL, r_srcR */
+ p = mkFormI(p, 9, 0, r_dst, 1);
+ p = mkFormI(p, 4, r_srcL, r_srcR, 2);
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0);
+ p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 43);
+ break;
+ default:
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Min_Mul: {
+ Bool syned = i->Min.Mul.syned;
+ Bool widening = i->Min.Mul.widening;
+ Bool sz32 = i->Min.Mul.sz32;
+ UInt r_srcL = iregNo(i->Min.Mul.srcL, mode64);
+ UInt r_srcR = iregNo(i->Min.Mul.srcR, mode64);
+ UInt r_dst = iregNo(i->Min.Mul.dst, mode64);
+
+ if (widening) {
+ if (sz32) {
+ if (syned)
+ /* mult */
+ p = mkFormR(p, 0, r_srcL, r_srcR, 0, 0, 24);
+ else
+ /* multu */
+ p = mkFormR(p, 0, r_srcL, r_srcR, 0, 0, 25);
+ } else {
+ if (syned) /* DMULT r_dst,r_srcL,r_srcR */
+ p = mkFormR(p, 0, r_srcL, r_srcR, 0, 0, 28);
+ else /* DMULTU r_dst,r_srcL,r_srcR */
+ p = mkFormR(p, 0, r_srcL, r_srcR, 0, 0, 29);
+ }
+ } else {
+ if (sz32)
+ /* mul */
+ p = mkFormR(p, 28, r_srcL, r_srcR, r_dst, 0, 2);
+ else if (mode64 && !sz32)
+ p = mkFormR(p, 28, r_srcL, r_srcR, r_dst, 0, 2);
+ else
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Min_Macc: {
+ Bool syned = i->Min.Macc.syned;
+ UInt r_srcL = iregNo(i->Min.Macc.srcL, mode64);
+ UInt r_srcR = iregNo(i->Min.Macc.srcR, mode64);
+
+ if (syned) {
+ switch (i->Min.Macc.op) {
+ case Macc_ADD:
+ //madd
+ p = mkFormR(p, 28, r_srcL, r_srcR, 0, 0, 0);
+ break;
+ case Macc_SUB:
+ //msub
+ p = mkFormR(p, 28, r_srcL, r_srcR, 0, 0,
+ 4);
+ break;
+ default:
+ goto bad;
+ }
+ } else {
+ switch (i->Min.Macc.op) {
+ case Macc_ADD:
+ //maddu
+ p = mkFormR(p, 28, r_srcL, r_srcR, 0, 0,
+ 1);
+ break;
+ case Macc_SUB:
+ //msubu
+ p = mkFormR(p, 28, r_srcL, r_srcR, 0, 0,
+ 5);
+ break;
+ default:
+ goto bad;
+ }
+ }
+
+ goto done;
+ }
+
+ case Min_Div: {
+ Bool syned = i->Min.Div.syned;
+ Bool sz32 = i->Min.Div.sz32;
+ UInt r_srcL = iregNo(i->Min.Div.srcL, mode64);
+ UInt r_srcR = iregNo(i->Min.Div.srcR, mode64);
+ if (sz32) {
+ if (syned) {
+ /* div */
+ p = mkFormR(p, 0, r_srcL, r_srcR, 0, 0, 26);
+ } else
+ /* divu */
+ p = mkFormR(p, 0, r_srcL, r_srcR, 0, 0, 27);
+ goto done;
+ } else {
+ if (syned) {
+ /* ddiv */
+ p = mkFormR(p, 0, r_srcL, r_srcR, 0, 0, 30);
+ } else
+ /* ddivu */
+ p = mkFormR(p, 0, r_srcL, r_srcR, 0, 0, 31);
+ goto done;
+ }
+ }
+
+ case Min_Mthi: {
+ UInt r_src = iregNo(i->Min.MtHL.src, mode64);
+ p = mkFormR(p, 0, r_src, 0, 0, 0, 17);
+ goto done;
+ }
+
+ case Min_Mtlo: {
+ UInt r_src = iregNo(i->Min.MtHL.src, mode64);
+ p = mkFormR(p, 0, r_src, 0, 0, 0, 19);
+ goto done;
+ }
+
+ case Min_Mfhi: {
+ UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
+ p = mkFormR(p, 0, 0, 0, r_dst, 0, 16);
+ goto done;
+ }
+
+ case Min_Mflo: {
+ UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
+ p = mkFormR(p, 0, 0, 0, r_dst, 0, 18);
+ goto done;
+ }
+
+ case Min_MtFCSR: {
+ UInt r_src = iregNo(i->Min.MtFCSR.src, mode64);
+ /* ctc1 */
+ p = mkFormR(p, 17, 6, r_src, 31, 0, 0);
+ goto done;
+ }
+
+ case Min_MfFCSR: {
+ UInt r_dst = iregNo(i->Min.MfFCSR.dst, mode64);
+ /* cfc1 */
+ p = mkFormR(p, 17, 2, r_dst, 31, 0, 0);
+ goto done;
+ }
+
+ case Min_Call: {
+ MIPSCondCode cond = i->Min.Call.cond;
+ UInt r_dst = 25; /* using %r25 as address temporary -
+ see getRegUsage_MIPSInstr */
+
+ /* jump over the following insns if condition does not hold */
+ if (cond != MIPScc_AL) {
+ /* jmp fwds if !condition */
+ /* don't know how many bytes to jump over yet...
+ make space for a jump instruction + nop!!! and fill in later. */
+ ptmp = p; /* fill in this bit later */
+ p += 8; // p += 8
+ }
+
+ /* load target to r_dst */// p += 4|8
+ p = mkLoadImm(p, r_dst, i->Min.Call.target, mode64);
+
+ /* jalr %r_dst */
+ p = mkFormR(p, 0, r_dst, 0, 31, 0, 9); // p += 4
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0); // p += 4
+
+ /* Fix up the conditional jump, if there was one. */
+ if (cond != MIPScc_AL) {
+ UInt r_src = iregNo(i->Min.Call.src, mode64);
+ Int delta = p - ptmp;
+
+ vassert(delta >= 20 && delta <= 32);
+ /* bc !ct,cf,delta/4 */
+ /* blez r_src, delta/4-1 */
+ vassert(cond == MIPScc_EQ);
+ ptmp = mkFormI(ptmp, 6, r_src, 0, delta / 4 - 1);
+ ptmp = mkFormR(ptmp, 0, 0, 0, 0, 0, 0);
+ }
+ goto done;
+ }
+
+ case Min_XDirect: {
+ /* NB: what goes on here has to be very closely coordinated
+ with the chainXDirect_MIPS and unchainXDirect_MIPS below. */
+ /* We're generating chain-me requests here, so we need to be
+ sure this is actually allowed -- no-redir translations
+ can't use chain-me's. Hence: */
+ vassert(disp_cp_chain_me_to_slowEP != NULL);
+ vassert(disp_cp_chain_me_to_fastEP != NULL);
+
+ /* Use ptmp for backpatching conditional jumps. */
+ ptmp = NULL;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. Or at least, leave a space for
+ it that we will shortly fill in. */
+ if (i->Min.XDirect.cond != MIPScc_AL) {
+ vassert(i->Min.XDirect.cond != MIPScc_NV);
+ ptmp = p;
+ p += 12;
+ }
+
+ /* Update the guest PC. */
+ /* move r9, dstGA */
+ /* sw r9, amPC */
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/9,
+ (ULong)i->Min.XDirect.dstGA, mode64);
+ p = do_load_or_store_machine_word(p, False/*!isLoad*/,
+ /*r*/9, i->Min.XDirect.amPC, mode64);
+
+ /* --- FIRST PATCHABLE BYTE follows --- */
+ /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're
+ calling to) backs up the return address, so as to find the
+ address of the first patchable byte. So: don't change the
+ number of instructions (3) below. */
+ /* move r9, VG_(disp_cp_chain_me_to_{slowEP,fastEP}) */
+ /* jr r9 */
+ void* disp_cp_chain_me
+ = i->Min.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
+ : disp_cp_chain_me_to_slowEP;
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/9,
+ Ptr_to_ULong(disp_cp_chain_me), mode64);
+ /* jalr $9 */
+ /* nop */
+ p = mkFormR(p, 0, 9, 0, 31, 0, 9); // p += 4
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0); // p += 4
+ /* --- END of PATCHABLE BYTES --- */
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->Min.XDirect.cond != MIPScc_AL) {
+ Int delta = p - ptmp;
+ delta = delta / 4 - 3;
+ vassert(delta > 0 && delta < 40);
+ /* lw $9, 316($10) // guest_COND
+ beq $9, $0, 2
+ nop*/
+ ptmp = mkFormI(ptmp, 35, 10, 9, 316);
+ ptmp = mkFormI(ptmp, 4, 0, 9, (delta));
+ ptmp = mkFormR(ptmp, 0, 0, 0, 0, 0, 0);
+ }
+ goto done;
+ }
+
+ case Min_XIndir: {
+ /* We're generating transfers that could lead indirectly to a
+ chain-me, so we need to be sure this is actually allowed --
+ no-redir translations are not allowed to reach normal
+ translations without going through the scheduler. That means
+ no XDirects or XIndirs out from no-redir translations.
+ Hence: */
+ vassert(disp_cp_xindir != NULL);
+
+ /* Use ptmp for backpatching conditional jumps. */
+ ptmp = NULL;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. */
+ if (i->Min.XIndir.cond != MIPScc_AL) {
+ vassert(i->Min.XIndir.cond != MIPScc_NV);
+ ptmp = p;
+ p += 12;
+ }
+
+ /* Update the guest PC. */
+ /* sw r-dstGA, amPC */
+ p = do_load_or_store_machine_word(p, False/*!isLoad*/,
+ iregNo(i->Min.XIndir.dstGA, mode64),
+ i->Min.XIndir.amPC, mode64);
+
+ /* move r9, VG_(disp_cp_xindir) */
+ /* jalr r9 */
+ /* nop */
+ p = mkLoadImm_EXACTLY2or5 ( p, /*r*/9,
+ Ptr_to_ULong(disp_cp_xindir), mode64);
+ p = mkFormR(p, 0, 9, 0, 31, 0, 9); // p += 4
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0); // p += 4
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->Min.XIndir.cond != MIPScc_AL) {
+ Int delta = p - ptmp;
+ delta = delta / 4 - 3;
+ vassert(delta > 0 && delta < 40);
+ /* lw $9, 316($10) // guest_COND
+ beq $9, $0, 2
+ nop*/
+ ptmp = mkFormI(ptmp, 35, 10, 9, 316);
+ ptmp = mkFormI(ptmp, 4, 0, 9, (delta));
+ ptmp = mkFormR(ptmp, 0, 0, 0, 0, 0, 0);
+ }
+ goto done;
+ }
+
+ case Min_XAssisted: {
+ /* First off, if this is conditional, create a conditional jump
+ over the rest of it. Or at least, leave a space for it that
+ we will shortly fill in. */
+ ptmp = NULL;
+ if (i->Min.XAssisted.cond != MIPScc_AL) {
+ vassert(i->Min.XAssisted.cond != MIPScc_NV);
+ ptmp = p;
+ p += 12;
+ }
+
+ /* Update the guest PC. */
+ /* sw r-dstGA, amPC */
+ p = do_load_or_store_machine_word(p, False/*!isLoad*/,
+ iregNo(i->Min.XIndir.dstGA, mode64),
+ i->Min.XIndir.amPC, mode64);
+
+ /* imm32/64 r31, $magic_number */
+ UInt trcval = 0;
+ switch (i->Min.XAssisted.jk) {
+ case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break;
+ case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break;
+ //case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break;
+ //case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break;
+ case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
+ case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break;
+ //case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
+ case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
+ case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
+ case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
+ //case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
+ case Ijk_SigBUS: trcval = VEX_TRC_JMP_SIGBUS; break;
+ case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break;
+ /* We don't expect to see the following being assisted. */
+ //case Ijk_Ret:
+ //case Ijk_Call:
+ /* fallthrough */
+ default:
+ ppIRJumpKind(i->Min.XAssisted.jk);
+ vpanic("emit_MIPSInstr.Min_XAssisted: unexpected jump kind");
+ }
+ vassert(trcval != 0);
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/10, trcval, mode64);
+
+ /* move r9, VG_(disp_cp_xassisted) */
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/9,
+ (ULong)Ptr_to_ULong(disp_cp_xassisted), mode64);
+ /* jalr $9
+ nop */
+ p = mkFormR(p, 0, 9, 0, 31, 0, 9); // p += 4
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0); // p += 4
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->Min.XAssisted.cond != MIPScc_AL) {
+ Int delta = p - ptmp;
+ delta = delta / 4 - 3;
+ vassert(delta > 0 && delta < 40);
+ /* lw $9, 316($10) // guest_COND
+ beq $9, $0, 2
+ nop*/
+ ptmp = mkFormI(ptmp, 35, 10, 9, 316);
+ ptmp = mkFormI(ptmp, 4, 0, 9, (delta));
+ ptmp = mkFormR(ptmp, 0, 0, 0, 0, 0, 0);
+ }
+ goto done;
+ }
+
+ case Min_Load: {
+ MIPSAMode *am_addr = i->Min.Load.src;
+ if (am_addr->tag == Mam_IR) {
+ UInt r_dst = iregNo(i->Min.Load.dst, mode64);
+ UInt opc, sz = i->Min.Load.sz;
+ if (mode64 && (sz == 4 || sz == 8)) {
+ /* should be guaranteed to us by iselWordExpr_AMode */
+ vassert(0 == (am_addr->Mam.IR.index & 3));
+ }
+ switch (sz) {
+ case 1:
+ opc = 32;
+ break;
+ case 2:
+ opc = 33;
+ break;
+ case 4:
+ opc = 35;
+ break;
+ case 8:
+ opc = 55;
+ vassert(mode64);
+ break;
+ default:
+ goto bad;
+ }
+
+ p = doAMode_IR(p, opc, r_dst, am_addr, mode64);
+ goto done;
+ } else if (am_addr->tag == Mam_RR) {
+ UInt r_dst = iregNo(i->Min.Load.dst, mode64);
+ UInt opc, sz = i->Min.Load.sz;
+
+ switch (sz) {
+ case 1:
+ opc = 32;
+ break;
+ case 2:
+ opc = 33;
+ break;
+ case 4:
+ opc = 35;
+ break;
+ case 8:
+ opc = 55;
+ vassert(mode64);
+ break;
+ default:
+ goto bad;
+ }
+
+ p = doAMode_RR(p, opc, r_dst, am_addr, mode64);
+ goto done;
+ }
+ break;
+ }
+
+ case Min_Store: {
+ MIPSAMode *am_addr = i->Min.Store.dst;
+ if (am_addr->tag == Mam_IR) {
+ UInt r_src = iregNo(i->Min.Store.src, mode64);
+ UInt opc, sz = i->Min.Store.sz;
+ if (mode64 && (sz == 4 || sz == 8)) {
+ /* should be guaranteed to us by iselWordExpr_AMode */
+ vassert(0 == (am_addr->Mam.IR.index & 3));
+ }
+ switch (sz) {
+ case 1:
+ opc = 40;
+ break;
+ case 2:
+ opc = 41;
+ break;
+ case 4:
+ opc = 43;
+ break;
+ case 8:
+ vassert(mode64);
+ opc = 63;
+ break;
+ default:
+ goto bad;
+ }
+
+ p = doAMode_IR(p, opc, r_src, am_addr, mode64);
+ goto done;
+ } else if (am_addr->tag == Mam_RR) {
+ UInt r_src = iregNo(i->Min.Store.src, mode64);
+ UInt opc, sz = i->Min.Store.sz;
+
+ switch (sz) {
+ case 1:
+ opc = 40;
+ break;
+ case 2:
+ opc = 41;
+ break;
+ case 4:
+ opc = 43;
+ break;
+ case 8:
+ vassert(mode64);
+ opc = 63;
+ break;
+ default:
+ goto bad;
+ }
+
+ p = doAMode_RR(p, opc, r_src, am_addr, mode64);
+ goto done;
+ }
+ break;
+ }
+ case Min_LoadL: {
+ MIPSAMode *am_addr = i->Min.LoadL.src;
+ UInt r_src = iregNo(am_addr->Mam.IR.base, mode64);
+ UInt idx = am_addr->Mam.IR.index;
+ UInt r_dst = iregNo(i->Min.LoadL.dst, mode64);
+
+ p = mkFormI(p, 0x30, r_src, r_dst, idx);
+ goto done;
+ }
+ case Min_StoreC: {
+ MIPSAMode *am_addr = i->Min.StoreC.dst;
+ UInt r_src = iregNo(i->Min.StoreC.src, mode64);
+ UInt idx = am_addr->Mam.IR.index;
+ UInt r_dst = iregNo(am_addr->Mam.IR.base, mode64);
+
+ p = mkFormI(p, 0x38, r_dst, r_src, idx);
+ goto done;
+ }
+ case Min_RdWrLR: {
+ UInt reg = iregNo(i->Min.RdWrLR.gpr, mode64);
+ Bool wrLR = i->Min.RdWrLR.wrLR;
+ if (wrLR)
+ p = mkMoveReg(p, 31, reg);
+ else
+ p = mkMoveReg(p, reg, 31);
+ goto done;
+ }
+
+ // Floating point
+
+ case Min_FpLdSt: {
+ MIPSAMode *am_addr = i->Min.FpLdSt.addr;
+ UChar sz = i->Min.FpLdSt.sz;
+ vassert(sz == 4 || sz == 8);
+ if (sz == 4) {
+ UInt f_reg = fregNo(i->Min.FpLdSt.reg, mode64);
+ if (i->Min.FpLdSt.isLoad) {
+ if (am_addr->tag == Mam_IR)
+ p = doAMode_IR(p, 0x31, f_reg, am_addr, mode64);
+ else if (am_addr->tag == Mam_RR)
+ p = doAMode_RR(p, 0x31, f_reg, am_addr, mode64);
+ } else {
+ if (am_addr->tag == Mam_IR)
+ p = doAMode_IR(p, 0x39, f_reg, am_addr, mode64);
+ else if (am_addr->tag == Mam_RR)
+ p = doAMode_RR(p, 0x39, f_reg, am_addr, mode64);
+ }
+ } else if (sz == 8) {
+ UInt f_reg = dregNo(i->Min.FpLdSt.reg);
+ if (i->Min.FpLdSt.isLoad) {
+ if (am_addr->tag == Mam_IR) {
+ if (mode64) {
+ p = doAMode_IR(p, 0x35, f_reg, am_addr, mode64);
+ } else {
+ p = doAMode_IR(p, 0x31, f_reg, am_addr, mode64);
+ p = doAMode_IR(p, 0x31, f_reg + 1,
+ nextMIPSAModeFloat(am_addr), mode64);
+ }
+ } else if (am_addr->tag == Mam_RR) {
+ if (mode64) {
+ p = doAMode_RR(p, 0x35, f_reg, am_addr, mode64);
+ } else {
+ p = doAMode_RR(p, 0x31, f_reg, am_addr, mode64);
+ p = doAMode_RR(p, 0x31, f_reg + 1,
+ nextMIPSAModeFloat(am_addr), mode64);
+ }
+ }
+ } else {
+ if (am_addr->tag == Mam_IR) {
+ if (mode64) {
+ p = doAMode_IR(p, 0x3d, f_reg, am_addr, mode64);
+ } else {
+ p = doAMode_IR(p, 0x39, f_reg, am_addr, mode64);
+ p = doAMode_IR(p, 0x39, f_reg + 1,
+ nextMIPSAModeFloat(am_addr), mode64);
+ }
+ } else if (am_addr->tag == Mam_RR) {
+ if (mode64) {
+ p = doAMode_RR(p, 0x3d, f_reg, am_addr, mode64);
+ } else {
+ p = doAMode_RR(p, 0x39, f_reg, am_addr, mode64);
+ p = doAMode_RR(p, 0x39, f_reg + 1,
+ nextMIPSAModeFloat(am_addr), mode64);
+ }
+ }
+ }
+ }
+ goto done;
+ }
+
+ case Min_FpUnary: {
+ switch (i->Min.FpUnary.op) {
+ case Mfp_MOVS: { // FP move
+ UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
+ UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x6);
+ break;
+ }
+ case Mfp_MOVD: { // FP move
+ UInt fr_dst = dregNo(i->Min.FpUnary.dst);
+ UInt fr_src = dregNo(i->Min.FpUnary.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x6);
+ break;
+ }
+ case Mfp_ABSS: { // ABSS
+ UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
+ UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x5);
+ break;
+ }
+ case Mfp_ABSD: { // ABSD
+ UInt fr_dst = dregNo(i->Min.FpUnary.dst);
+ UInt fr_src = dregNo(i->Min.FpUnary.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x5);
+ break;
+ }
+ case Mfp_NEGS: { // ABSS
+ UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
+ UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x7);
+ break;
+ }
+ case Mfp_NEGD: { // ABSD
+ UInt fr_dst = dregNo(i->Min.FpUnary.dst);
+ UInt fr_src = dregNo(i->Min.FpUnary.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x7);
+ break;
+ }
+ case Mfp_CVTD: { //CVT.D
+ UInt fr_dst = dregNo(i->Min.FpUnary.dst);
+ UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x21);
+ break;
+ }
+ case Mfp_SQRTS: { //SQRT.S
+ UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
+ UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x04);
+ break;
+ }
+ case Mfp_SQRTD: { //SQRT.D
+ UInt fr_dst = dregNo(i->Min.FpUnary.dst);
+ UInt fr_src = dregNo(i->Min.FpUnary.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x04);
+ break;
+ }
+ case Mfp_RSQRTS: { //RSQRT.S
+ UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
+ UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x16);
+ break;
+ }
+ case Mfp_RSQRTD: { //RSQRT.D
+ UInt fr_dst = dregNo(i->Min.FpUnary.dst);
+ UInt fr_src = dregNo(i->Min.FpUnary.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x16);
+ break;
+ }
+ case Mfp_RECIPS: { //RECIP.S
+ UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
+ UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x15);
+ break;
+ }
+ case Mfp_RECIPD: { //RECIP.D
+ UInt fr_dst = dregNo(i->Min.FpUnary.dst);
+ UInt fr_src = dregNo(i->Min.FpUnary.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x15);
+ break;
+ }
+ default:
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Min_FpBinary: {
+ switch (i->Min.FpBinary.op) {
+ case Mfp_ADDS: {
+ UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
+ UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
+ UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
+ p = mkFormR(p, 0x11, 0x10, fr_srcR, fr_srcL, fr_dst, 0);
+ break;
+ }
+ case Mfp_SUBS: {
+ UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
+ UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
+ UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
+ p = mkFormR(p, 0x11, 0x10, fr_srcR, fr_srcL, fr_dst, 1);
+ break;
+ }
+ case Mfp_MULS: {
+ UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
+ UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
+ UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
+ p = mkFormR(p, 0x11, 0x10, fr_srcR, fr_srcL, fr_dst, 2);
+ break;
+ }
+ case Mfp_DIVS: {
+ UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
+ UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
+ UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
+ p = mkFormR(p, 0x11, 0x10, fr_srcR, fr_srcL, fr_dst, 3);
+ break;
+ }
+ case Mfp_ADDD: {
+ UInt fr_dst = dregNo(i->Min.FpBinary.dst);
+ UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
+ UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
+ p = mkFormR(p, 0x11, 0x11, fr_srcR, fr_srcL, fr_dst, 0);
+ break;
+ }
+ case Mfp_SUBD: {
+ UInt fr_dst = dregNo(i->Min.FpBinary.dst);
+ UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
+ UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
+ p = mkFormR(p, 0x11, 0x11, fr_srcR, fr_srcL, fr_dst, 1);
+ break;
+ }
+ case Mfp_MULD: {
+ UInt fr_dst = dregNo(i->Min.FpBinary.dst);
+ UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
+ UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
+ p = mkFormR(p, 0x11, 0x11, fr_srcR, fr_srcL, fr_dst, 2);
+ break;
+ }
+ case Mfp_DIVD: {
+ UInt fr_dst = dregNo(i->Min.FpBinary.dst);
+ UInt fr_srcL = dregNo(i->Min.FpBinary.srcL);
+ UInt fr_srcR = dregNo(i->Min.FpBinary.srcR);
+ p = mkFormR(p, 0x11, 0x11, fr_srcR, fr_srcL, fr_dst, 3);
+ break;
+ }
+ default:
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Min_FpConvert: {
+ switch (i->Min.FpConvert.op) {
+ UInt fr_dst, fr_src;
+ case Mfp_CVTSD:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x20);
+ break;
+ case Mfp_CVTSW:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = fregNo(i->Min.FpConvert.src, mode64);
+ p = mkFormR(p, 0x11, 0x14, 0, fr_src, fr_dst, 0x20);
+ break;
+ case Mfp_CVTWD:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x24);
+ break;
+ case Mfp_CVTWS:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = fregNo(i->Min.FpConvert.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x24);
+ break;
+ case Mfp_CVTDW:
+ fr_dst = dregNo(i->Min.FpConvert.dst);
+ fr_src = fregNo(i->Min.FpConvert.src, mode64);
+ p = mkFormR(p, 0x11, 0x14, 0, fr_src, fr_dst, 0x21);
+ break;
+ case Mfp_TRUWS:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = fregNo(i->Min.FpConvert.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x0D);
+ break;
+ case Mfp_TRUWD:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x0D);
+ break;
+ case Mfp_TRULS:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x09);
+ break;
+ case Mfp_TRULD:
+ fr_dst = dregNo(i->Min.FpConvert.dst);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x09);
+ break;
+ case Mfp_CEILWS:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = fregNo(i->Min.FpConvert.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x0E);
+ break;
+ case Mfp_CEILWD:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x0E);
+ break;
+ case Mfp_CEILLS:
+ fr_dst = dregNo(i->Min.FpConvert.dst);
+ fr_src = fregNo(i->Min.FpConvert.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x0A);
+ break;
+ case Mfp_CEILLD:
+ fr_dst = dregNo(i->Min.FpConvert.dst);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x0A);
+ break;
+ case Mfp_ROUNDWS:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = fregNo(i->Min.FpConvert.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x0C);
+ break;
+ case Mfp_ROUNDWD:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x0C);
+ break;
+ case Mfp_FLOORWS:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = fregNo(i->Min.FpConvert.src, mode64);
+ p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x0F);
+ break;
+ case Mfp_FLOORWD:
+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
+ fr_src = dregNo(i->Min.FpConvert.src);
+ p = mkFormR(p, 0x11, 0x11, 0, fr_src, fr_dst, 0x0F);
+ break;
+
+ default:
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Min_FpCompare: {
+ UInt r_dst = iregNo(i->Min.FpCompare.dst, mode64);
+ UInt fr_srcL = dregNo(i->Min.FpCompare.srcL);
+ UInt fr_srcR = dregNo(i->Min.FpCompare.srcR);
+
+ switch (i->Min.FpConvert.op) {
+ case Mfp_CMP:
+ p = mkFormR(p, 0x11, 0x11, fr_srcL, fr_srcR, 0,
+ (i->Min.FpCompare.cond1 + 48));
+ p = mkFormR(p, 0x11, 0x2, r_dst, 31, 0, 0);
+ break;
+ default:
+ goto bad;
+ }
+ goto done;
+ }
+ case Min_EvCheck: {
+ /* This requires a 32-bit dec/test in 32 mode. */
+ /* We generate:
+ lw r9, amCounter
+ addiu r9, r9, -1
+ sw r9, amCounter
+ bgez r9, nofail
+ lw r9, amFailAddr
+ jalr r9
+ nop
+ nofail:
+ */
+ UChar* p0 = p;
+ /* lw r9, amCounter */
+ p = do_load_or_store_machine_word(p, True/*isLoad*/, /*r*/9,
+ i->Min.EvCheck.amCounter, mode64);
+ /* addiu r9,r9,-1 */
+ p = mkFormI(p, 9, 9, 9, 0xFFFF);
+ /* sw r30, amCounter */
+ p = do_load_or_store_machine_word(p, False/*!isLoad*/, /*r*/9,
+ i->Min.EvCheck.amCounter, mode64);
+ /* bgez t9, nofail */
+ p = mkFormI(p, 1, 9, 1, 3);
+ /* lw r9, amFailAddr */
+ p = do_load_or_store_machine_word(p, True/*isLoad*/, /*r*/9,
+ i->Min.EvCheck.amFailAddr, mode64);
+ /* jalr $9 */
+ p = mkFormR(p, 0, 9, 0, 31, 0, 9); // p += 4
+ p = mkFormR(p, 0, 0, 0, 0, 0, 0); // p += 4
+ /* nofail: */
+
+ /* Crosscheck */
+ vassert(evCheckSzB_MIPS() == (UChar*)p - (UChar*)p0);
+ goto done;
+ }
+
+ case Min_ProfInc: {
+ /* Generate a code template to increment a memory location whose
+ address will be known later as an immediate value. This code
+ template will be patched once the memory location is known.
+ For now we do this with address == 0x65556555.
+ 32-bit:
+
+ move r9, 0x65556555
+ lw r8, 0(r9)
+ addiu r8, r8, 1 # add least significant word
+ sw r8, 0(r9)
+ sltiu r1, r8, 1 # set carry-in bit
+ lw r8, 4(r9)
+ addu r8, r8, r1
+ sw r8, 4(r9) */
+
+ if (mode64) {
+ vassert(0);
+ } else {
+ // move r9, 0x65556555
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/9, 0x65556555ULL,
+ False/*!mode64*/);
+ // lw r8, 0(r9)
+ p = mkFormI(p, 35, 9, 8, 0);
+
+ // addiu r8, r8, 1 # add least significant word
+ p = mkFormI(p, 9, 8, 8, 1);
+
+ // sw r8, 0(r9)
+ p = mkFormI(p, 43, 9, 8, 0);
+
+ // sltiu r1, r8, 1 # set carry-in bit
+ p = mkFormI(p, 11, 8, 1, 1);
+
+ // lw r8, 4(r9)
+ p = mkFormI(p, 35, 9, 8, 4);
+
+ // addu r8, r8, r1
+ p = mkFormR(p, 0, 8, 1, 8, 0, 33);
+
+ // sw r8, 4(r9)
+ p = mkFormI(p, 43, 9, 8, 4);
+
+ }
+ /* Tell the caller .. */
+ vassert(!(*is_profInc));
+ *is_profInc = True;
+ goto done;
+ }
+
+ default:
+ goto bad;
+
+ }
+
+ bad:
+ vex_printf("\n=> ");
+ ppMIPSInstr(i, mode64);
+ vpanic("emit_MIPSInstr");
+ /*NOTREACHED*/ done:
+ //vassert(p - &buf[0] <= 32);
+ return p - &buf[0];
+}
+
+/* How big is an event check? See case for Min_EvCheck in
+ emit_MIPSInstr just above. That crosschecks what this returns, so
+ we can tell if we're inconsistent. */
+Int evCheckSzB_MIPS ( void )
+{
+ UInt kInstrSize = 4;
+ return 7*kInstrSize;
+}
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange chainXDirect_MIPS ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to,
+ Bool mode64 )
+{
+ /* What we're expecting to see is:
+ move r9, disp_cp_chain_me_to_EXPECTED
+ jalr r9
+ nop
+ viz
+ <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5>
+ 0x120F809 // jalr r9
+ 0x00000000 // nop
+ */
+ UChar* p = (UChar*)place_to_chain;
+ vassert(0 == (3 & (HWord)p));
+ vassert(isLoadImm_EXACTLY2or5(p, /*r*/9,
+ (UInt)Ptr_to_ULong(disp_cp_chain_me_EXPECTED),
+ mode64));
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x120F809);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x00000000);
+ /* And what we want to change it to is either:
+ move r9, place_to_jump_to
+ jalr r9
+ nop
+ viz
+ <8 bytes generated by mkLoadImm_EXACTLY2or5>
+ 0x120F809 // jalr r9
+ 0x00000000 // nop
+
+ The replacement has the same length as the original.
+ */
+
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/9,
+ Ptr_to_ULong(place_to_jump_to), mode64);
+ p = emit32(p, 0x120F809);
+ p = emit32(p, 0x00000000);
+
+ Int len = p - (UChar*)place_to_chain;
+ vassert(len == (mode64 ? 28 : 16)); /* stay sane */
+ VexInvalRange vir = {(HWord)place_to_chain, len};
+ return vir;
+}
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange unchainXDirect_MIPS ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me,
+ Bool mode64 )
+{
+ /* What we're expecting to see is:
+ move r9, place_to_jump_to_EXPECTED
+ jalr r9
+ nop
+ viz
+ <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5>
+ 0x120F809 // jalr r9
+ 0x00000000 // nop
+ */
+ UChar* p = (UChar*)place_to_unchain;
+ vassert(0 == (3 & (HWord)p));
+ vassert(isLoadImm_EXACTLY2or5(p, /*r*/9,
+ Ptr_to_ULong(place_to_jump_to_EXPECTED),
+ mode64));
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x120F809);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x00000000);
+ /* And what we want to change it to is:
+ move r9, disp_cp_chain_me
+ jalr r9
+ nop
+ viz
+ <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5>
+ 0x120F809 // jalr r9
+ 0x00000000 // nop
+ The replacement has the same length as the original.
+ */
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/9,
+ Ptr_to_ULong(disp_cp_chain_me), mode64);
+ p = emit32(p, 0x120F809);
+ p = emit32(p, 0x00000000);
+
+ Int len = p - (UChar*)place_to_unchain;
+ vassert(len == (mode64 ? 28 : 16)); /* stay sane */
+ VexInvalRange vir = {(HWord)place_to_unchain, len};
+ return vir;
+}
+
+/* Patch the counter address into a profile inc point, as previously
+ created by the Min_ProfInc case for emit_MIPSInstr. */
+VexInvalRange patchProfInc_MIPS ( void* place_to_patch,
+ ULong* location_of_counter, Bool mode64 )
+{
+ vassert(sizeof(ULong*) == 4);
+ UChar* p = (UChar*)place_to_patch;
+ vassert(0 == (3 & (HWord)p));
+ vassert(isLoadImm_EXACTLY2or5((UChar *)p, /*r*/9, 0x65556555, mode64));
+
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x8D280000);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x25080001);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 8) == 0xAD280000);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 12) == 0x2d010001);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 16) == 0x8d280004);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 20) == 0x01014021);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 24) == 0xad280004);
+
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/9,
+ Ptr_to_ULong(location_of_counter), mode64);
+
+ VexInvalRange vir = {(HWord)p, 8};
+ return vir;
+}
+
+
+/*---------------------------------------------------------------*/
+/*--- end host_mips_defs.c ---*/
+/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/host_mips_defs.h b/main/VEX/priv/host_mips_defs.h
new file mode 100644
index 0000000..1431ff5
--- /dev/null
+++ b/main/VEX/priv/host_mips_defs.h
@@ -0,0 +1,753 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin host_mips_defs.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __VEX_HOST_MIPS_DEFS_H
+#define __VEX_HOST_MIPS_DEFS_H
+
+/* Num registers used for function calls */
+#define MIPS_N_REGPARMS 4
+
+/* --------- Registers. --------- */
+
+/* The usual HReg abstraction.
+ There are 32 general purpose regs.
+*/
+
+extern void ppHRegMIPS(HReg, Bool);
+
+extern HReg hregMIPS_GPR0(Bool mode64); // scratch reg / zero reg
+extern HReg hregMIPS_GPR1(Bool mode64); // reserved for trap handling
+extern HReg hregMIPS_GPR2(Bool mode64); // reserved for trap handling
+extern HReg hregMIPS_GPR3(Bool mode64);
+extern HReg hregMIPS_GPR4(Bool mode64);
+extern HReg hregMIPS_GPR5(Bool mode64);
+extern HReg hregMIPS_GPR6(Bool mode64);
+extern HReg hregMIPS_GPR7(Bool mode64);
+extern HReg hregMIPS_GPR8(Bool mode64);
+extern HReg hregMIPS_GPR9(Bool mode64);
+extern HReg hregMIPS_GPR10(Bool mode64);
+extern HReg hregMIPS_GPR11(Bool mode64);
+extern HReg hregMIPS_GPR12(Bool mode64);
+extern HReg hregMIPS_GPR13(Bool mode64);
+extern HReg hregMIPS_GPR14(Bool mode64);
+extern HReg hregMIPS_GPR15(Bool mode64);
+extern HReg hregMIPS_GPR16(Bool mode64);
+extern HReg hregMIPS_GPR17(Bool mode64);
+extern HReg hregMIPS_GPR18(Bool mode64);
+extern HReg hregMIPS_GPR19(Bool mode64);
+extern HReg hregMIPS_GPR20(Bool mode64);
+extern HReg hregMIPS_GPR21(Bool mode64);
+extern HReg hregMIPS_GPR22(Bool mode64);
+extern HReg hregMIPS_GPR23(Bool mode64); // GuestStatePtr
+extern HReg hregMIPS_GPR24(Bool mode64); // reserved for dispatcher
+extern HReg hregMIPS_GPR25(Bool mode64);
+extern HReg hregMIPS_GPR26(Bool mode64);
+extern HReg hregMIPS_GPR27(Bool mode64);
+extern HReg hregMIPS_GPR28(Bool mode64);
+extern HReg hregMIPS_GPR29(Bool mode64);
+extern HReg hregMIPS_GPR30(Bool mode64);
+extern HReg hregMIPS_GPR31(Bool mode64);
+extern HReg hregMIPS_PC(Bool mode64);
+
+extern HReg hregMIPS_HI(Bool mode64);
+extern HReg hregMIPS_LO(Bool mode64);
+
+extern HReg hregMIPS_F0(Bool mode64);
+extern HReg hregMIPS_F1(Bool mode64);
+extern HReg hregMIPS_F2(Bool mode64);
+extern HReg hregMIPS_F3(Bool mode64);
+extern HReg hregMIPS_F4(Bool mode64);
+extern HReg hregMIPS_F5(Bool mode64);
+extern HReg hregMIPS_F6(Bool mode64);
+extern HReg hregMIPS_F7(Bool mode64);
+extern HReg hregMIPS_F8(Bool mode64);
+extern HReg hregMIPS_F9(Bool mode64);
+extern HReg hregMIPS_F10(Bool mode64);
+extern HReg hregMIPS_F11(Bool mode64);
+extern HReg hregMIPS_F12(Bool mode64);
+extern HReg hregMIPS_F13(Bool mode64);
+extern HReg hregMIPS_F14(Bool mode64);
+extern HReg hregMIPS_F15(Bool mode64);
+extern HReg hregMIPS_F16(Bool mode64);
+extern HReg hregMIPS_F17(Bool mode64);
+extern HReg hregMIPS_F18(Bool mode64);
+extern HReg hregMIPS_F19(Bool mode64);
+extern HReg hregMIPS_F20(Bool mode64);
+extern HReg hregMIPS_F21(Bool mode64);
+extern HReg hregMIPS_F22(Bool mode64);
+extern HReg hregMIPS_F23(Bool mode64);
+extern HReg hregMIPS_F24(Bool mode64);
+extern HReg hregMIPS_F25(Bool mode64);
+extern HReg hregMIPS_F26(Bool mode64);
+extern HReg hregMIPS_F27(Bool mode64);
+extern HReg hregMIPS_F28(Bool mode64);
+extern HReg hregMIPS_F29(Bool mode64);
+extern HReg hregMIPS_F30(Bool mode64);
+extern HReg hregMIPS_F31(Bool mode64);
+extern HReg hregMIPS_FIR(void);
+extern HReg hregMIPS_FCCR(void);
+extern HReg hregMIPS_FEXR(void);
+extern HReg hregMIPS_FENR(void);
+extern HReg hregMIPS_FCSR(void);
+extern HReg hregMIPS_COND(void);
+
+extern HReg hregMIPS_D0(void);
+extern HReg hregMIPS_D1(void);
+extern HReg hregMIPS_D2(void);
+extern HReg hregMIPS_D3(void);
+extern HReg hregMIPS_D4(void);
+extern HReg hregMIPS_D5(void);
+extern HReg hregMIPS_D6(void);
+extern HReg hregMIPS_D7(void);
+extern HReg hregMIPS_D8(void);
+extern HReg hregMIPS_D9(void);
+extern HReg hregMIPS_D10(void);
+extern HReg hregMIPS_D11(void);
+extern HReg hregMIPS_D12(void);
+extern HReg hregMIPS_D13(void);
+extern HReg hregMIPS_D14(void);
+extern HReg hregMIPS_D15(void);
+
+#define GuestStatePointer(_mode64) hregMIPS_GPR10(_mode64)
+
+#define StackFramePointer(_mode64) hregMIPS_GPR30(_mode64)
+#define LinkRegister(_mode64) hregMIPS_GPR31(_mode64)
+#define StackPointer(_mode64) hregMIPS_GPR29(_mode64)
+#define FCSR() hregMIPS_FCSR()
+#define COND() hregMIPS_COND()
+
+#define HIRegister(_mode64) hregMIPS_HI(_mode64)
+#define LORegister(_mode64) hregMIPS_LO(_mode64)
+
+/* a0, a1, a2, a3 */
+#define MIPS_N_ARGREGS 4
+
+/* --------- Condition codes, Intel encoding. --------- */
+typedef enum {
+ MIPScc_EQ = 0, /* equal */
+ MIPScc_NE = 1, /* not equal */
+
+ MIPScc_HS = 2, /* >=u (higher or same) */
+ MIPScc_LO = 3, /* <u (lower) */
+
+ MIPScc_MI = 4, /* minus (negative) */
+ MIPScc_PL = 5, /* plus (zero or +ve) */
+
+ MIPScc_VS = 6, /* overflow */
+ MIPScc_VC = 7, /* no overflow */
+
+ MIPScc_HI = 8, /* >u (higher) */
+ MIPScc_LS = 9, /* <=u (lower or same) */
+
+ MIPScc_GE = 10, /* >=s (signed greater or equal) */
+ MIPScc_LT = 11, /* <s (signed less than) */
+
+ MIPScc_GT = 12, /* >s (signed greater) */
+ MIPScc_LE = 13, /* <=s (signed less or equal) */
+
+ MIPScc_AL = 14, /* always (unconditional) */
+ MIPScc_NV = 15 /* never (unconditional): */
+} MIPSCondCode;
+
+extern HChar *showMIPSCondCode(MIPSCondCode);
+
+/* --------- Memory address expressions (amodes). --------- */
+typedef enum {
+ Mam_IR, /* Immediate (signed 16-bit) + Reg */
+ Mam_RR /* Reg1 + Reg2 */
+} MIPSAModeTag;
+
+typedef struct {
+ MIPSAModeTag tag;
+ union {
+ struct {
+ HReg base;
+ Int index;
+ } IR;
+ struct {
+ HReg base;
+ HReg index;
+ } RR;
+ } Mam;
+} MIPSAMode;
+
+extern MIPSAMode *MIPSAMode_IR(Int, HReg);
+extern MIPSAMode *MIPSAMode_RR(HReg, HReg);
+
+extern MIPSAMode *dopyMIPSAMode(MIPSAMode *);
+extern MIPSAMode *nextMIPSAModeFloat(MIPSAMode *);
+extern MIPSAMode *nextMIPSAModeInt(MIPSAMode *);
+
+extern void ppMIPSAMode(MIPSAMode *, Bool);
+
+/* --------- Operand, which can be a reg or a u16/s16. --------- */
+/* ("RH" == "Register or Halfword immediate") */
+typedef enum {
+ Mrh_Imm,
+ Mrh_Reg
+} MIPSRHTag;
+
+typedef struct {
+ MIPSRHTag tag;
+ union {
+ struct {
+ Bool syned;
+ UShort imm16;
+ } Imm;
+ struct {
+ HReg reg;
+ } Reg;
+ } Mrh;
+} MIPSRH;
+
+extern void ppMIPSRH(MIPSRH *, Bool);
+
+extern MIPSRH *MIPSRH_Imm(Bool, UShort);
+extern MIPSRH *MIPSRH_Reg(HReg);
+
+/* --- Addressing Mode suitable for VFP --- */
+typedef struct {
+ HReg reg;
+ Int simm11;
+} MIPSAModeV;
+
+extern MIPSAModeV *mkMIPSAModeV(HReg reg, Int simm11);
+
+extern void ppMIPSAModeV(MIPSAModeV *);
+
+/* --------- Reg or imm-8x4 operands --------- */
+/* a.k.a (a very restricted form of) Shifter Operand,
+ in the MIPS parlance. */
+
+typedef enum {
+ MIPSri84_I84 = 5, /* imm8 `ror` (2 * imm4) */
+ MIPSri84_R /* reg */
+} MIPSRI84Tag;
+
+typedef struct {
+ MIPSRI84Tag tag;
+ union {
+ struct {
+ UShort imm8;
+ UShort imm4;
+ } I84;
+ struct {
+ HReg reg;
+ } R;
+ } MIPSri84;
+} MIPSRI84;
+
+extern MIPSRI84 *MIPSRI84_I84(UShort imm8, UShort imm4);
+extern MIPSRI84 *MIPSRI84_R(HReg);
+
+extern void ppMIPSRI84(MIPSRI84 *);
+
+/* --------- Reg or imm5 operands --------- */
+typedef enum {
+ MIPSri5_I5 = 7, /* imm5, 1 .. 31 only (no zero!) */
+ MIPSri5_R /* reg */
+} MIPSRI5Tag;
+
+typedef struct {
+ MIPSRI5Tag tag;
+ union {
+ struct {
+ UInt imm5;
+ } I5;
+ struct {
+ HReg reg;
+ } R;
+ } MIPSri5;
+} MIPSRI5;
+
+extern MIPSRI5 *MIPSRI5_I5(UInt imm5);
+extern MIPSRI5 *MIPSRI5_R(HReg);
+
+extern void ppMIPSRI5(MIPSRI5 *);
+
+/* --------- Instructions. --------- */
+
+/*Tags for operations*/
+
+/* --------- */
+typedef enum {
+ Mun_CLO,
+ Mun_CLZ,
+ Mun_NOP,
+} MIPSUnaryOp;
+
+extern HChar *showMIPSUnaryOp(MIPSUnaryOp);
+/* --------- */
+
+/* --------- */
+
+typedef enum {
+ Malu_INVALID,
+ Malu_ADD, Malu_SUB,
+ Malu_AND, Malu_OR, Malu_NOR, Malu_XOR,
+} MIPSAluOp;
+
+extern HChar *showMIPSAluOp(MIPSAluOp,
+ Bool /* is the 2nd operand an immediate? */ );
+
+/* --------- */
+typedef enum {
+ Mshft_INVALID,
+ Mshft_SLL, Mshft_SRL,
+ Mshft_SRA
+} MIPSShftOp;
+
+extern HChar *showMIPSShftOp(MIPSShftOp,
+ Bool /* is the 2nd operand an immediate? */ ,
+ Bool /* is this a 32bit or 64bit op? */ );
+
+/* --------- */
+typedef enum {
+ Macc_ADD,
+ Macc_SUB
+} MIPSMaccOp;
+
+extern HChar *showMIPSMaccOp(MIPSMaccOp, Bool);
+/* --------- */
+
+/* ----- Instruction tags ----- */
+typedef enum {
+ Min_LI, /* load word (32/64-bit) immediate (fake insn) */
+ Min_Alu, /* word add/sub/and/or/xor/nor/others? */
+ Min_Shft, /* word sll/srl/sra */
+ Min_Unary, /* clo, clz, nop, neg */
+
+ Min_Cmp, /* word compare (fake insn) */
+
+ Min_Mul, /* widening/non-widening multiply */
+ Min_Div, /* div */
+
+ Min_Call, /* call to address in register */
+
+ /* The following 5 insns are mandated by translation chaining */
+ Min_XDirect, /* direct transfer to GA */
+ Min_XIndir, /* indirect transfer to GA */
+ Min_XAssisted, /* assisted transfer to GA */
+ Min_EvCheck, /* Event check */
+ Min_ProfInc, /* 64-bit profile counter increment */
+
+ Min_RdWrLR, /* Read/Write Link Register */
+ Min_Mthi, /* Move to HI from GP register */
+ Min_Mtlo, /* Move to LO from GP register */
+ Min_Mfhi, /* Move from HI to GP register */
+ Min_Mflo, /* Move from LO to GP register */
+ Min_Macc, /* Multiply and accumulate */
+
+ Min_Load, /* zero-extending load a 8|16|32 bit value from mem */
+ Min_Store, /* store a 8|16|32 bit value to mem */
+ Min_LoadL, /* mips Load Linked Word */
+ Min_StoreC, /* mips Store Conditional Word */
+
+ Min_FpUnary, /* FP unary op */
+ Min_FpBinary, /* FP binary op */
+ Min_FpConvert, /* FP conversion op */
+ Min_FpMulAcc, /* FP multipy-accumulate style op */
+ Min_FpLdSt, /* FP load/store */
+ Min_FpSTFIW, /* stfiwx */
+ Min_FpRSP, /* FP round IEEE754 double to IEEE754 single */
+ Min_FpCftI, /* fcfid/fctid/fctiw */
+ Min_FpCMov, /* FP floating point conditional move */
+ Min_MtFCSR, /* set FCSR register */
+ Min_MfFCSR, /* get FCSR register */
+ Min_FpCompare, /* FP compare, generating value into int reg */
+ Min_MovCond
+} MIPSInstrTag;
+
+/* --------- */
+typedef enum {
+ Mfp_INVALID,
+
+ /* Ternary */
+ Mfp_MADDD, Mfp_MSUBD,
+ Mfp_MADDS, Mfp_MSUBS,
+
+ /* Binary */
+ Mfp_ADDD, Mfp_SUBD, Mfp_MULD, Mfp_DIVD,
+ Mfp_ADDS, Mfp_SUBS, Mfp_MULS, Mfp_DIVS, Mfp_CVTSD, Mfp_CVTSW, Mfp_CVTWD,
+ Mfp_CVTWS, Mfp_TRULS, Mfp_TRULD, Mfp_TRUWS, Mfp_TRUWD, Mfp_FLOORWS,
+ Mfp_FLOORWD, Mfp_ROUNDWS, Mfp_ROUNDWD, Mfp_CVTDW, Mfp_CMP,
+ Mfp_CEILWS, Mfp_CEILWD, Mfp_CEILLS, Mfp_CEILLD,
+
+ /* Unary */
+ Mfp_SQRTS, Mfp_SQRTD, Mfp_RSQRTS, Mfp_RSQRTD, Mfp_RECIPS, Mfp_RECIPD,
+ Mfp_ABSS, Mfp_ABSD, Mfp_NEGS, Mfp_NEGD, Mfp_MOVS, Mfp_MOVD,
+ Mfp_RES, Mfp_RSQRTE, Mfp_FRIN, Mfp_FRIM, Mfp_FRIP, Mfp_FRIZ, Mfp_CVTD
+} MIPSFpOp;
+
+extern HChar *showMIPSFpOp(MIPSFpOp);
+
+/*--------- Structure for instructions ----------*/
+/* Destinations are on the LEFT (first operand) */
+
+typedef struct {
+ MIPSInstrTag tag;
+ union {
+ /* Get a 32/64-bit literal into a register.
+ May turn into a number of real insns. */
+ struct {
+ HReg dst;
+ ULong imm;
+ } LI;
+ /* Integer add/sub/and/or/xor. Limitations:
+ - For add, the immediate, if it exists, is a signed 16.
+ - For sub, the immediate, if it exists, is a signed 16
+ which may not be -32768, since no such instruction
+ exists, and so we have to emit addi with +32768, but
+ that is not possible.
+ - For and/or/xor, the immediate, if it exists,
+ is an unsigned 16.
+ */
+ struct {
+ MIPSAluOp op;
+ HReg dst;
+ HReg srcL;
+ MIPSRH *srcR;
+ } Alu;
+ /* Integer shl/shr/sar.
+ Limitations: the immediate, if it exists,
+ is a signed 5-bit value between 1 and 31 inclusive.
+ */
+ struct {
+ MIPSShftOp op;
+ Bool sz32; /* mode64 has both 32 and 64bit shft */
+ HReg dst;
+ HReg srcL;
+ MIPSRH *srcR;
+ } Shft;
+ /* Clz, Clo, nop */
+ struct {
+ MIPSUnaryOp op;
+ HReg dst;
+ HReg src;
+ } Unary;
+ /* Word compare. Fake instruction, used for basic block ending */
+ struct {
+ Bool syned;
+ Bool sz32;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+
+ MIPSCondCode cond;
+ } Cmp;
+ struct {
+ Bool widening; //True => widening, False => non-widening
+ Bool syned; //signed/unsigned - meaningless if widenind = False
+ Bool sz32;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } Mul;
+ struct {
+ Bool syned; //signed/unsigned - meaningless if widenind = False
+ Bool sz32;
+ HReg srcL;
+ HReg srcR;
+ } Div;
+ /* Pseudo-insn. Call target (an absolute address), on given
+ condition (which could be Mcc_ALWAYS). argiregs indicates
+ which of r3 .. r10
+ carries argument values for this call,
+ using a bit mask (1<<N is set if rN holds an arg, for N in
+ 3 .. 10 inclusive).
+ If cond is != Mcc_ALWAYS, src is checked.
+ Otherwise, unconditional call */
+ struct {
+ MIPSCondCode cond;
+ Addr32 target;
+ UInt argiregs;
+ HReg src;
+ } Call;
+ /* Update the guest EIP value, then exit requesting to chain
+ to it. May be conditional. Urr, use of Addr32 implicitly
+ assumes that wordsize(guest) == wordsize(host). */
+ struct {
+ Addr32 dstGA; /* next guest address */
+ MIPSAMode* amPC; /* amode in guest state for PC */
+ MIPSCondCode cond; /* can be MIPScc_AL */
+ Bool toFastEP; /* chain to the slow or fast point? */
+ } XDirect;
+ /* Boring transfer to a guest address not known at JIT time.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ MIPSAMode* amPC;
+ MIPSCondCode cond; /* can be MIPScc_AL */
+ } XIndir;
+ /* Assisted transfer to a guest address, most general case.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ MIPSAMode* amPC;
+ MIPSCondCode cond; /* can be MIPScc_AL */
+ IRJumpKind jk;
+ } XAssisted;
+ /* Zero extending loads. Dst size is host word size */
+ struct {
+ UChar sz; /* 1|2|4|8 */
+ HReg dst;
+ MIPSAMode *src;
+ } Load;
+ /* 64/32/16/8 bit stores */
+ struct {
+ UChar sz; /* 1|2|4|8 */
+ MIPSAMode *dst;
+ HReg src;
+ } Store;
+ struct {
+ UChar sz; /* 4|8 */
+ HReg dst;
+ MIPSAMode *src;
+ } LoadL;
+ struct {
+ UChar sz; /* 4|8 */
+ MIPSAMode *dst;
+ HReg src;
+ } StoreC;
+ /* Move from HI/LO register to GP register. */
+ struct {
+ HReg dst;
+ } MfHL;
+
+ /* Move to HI/LO register from GP register. */
+ struct {
+ HReg src;
+ } MtHL;
+
+ /* Read/Write Link Register */
+ struct {
+ Bool wrLR;
+ HReg gpr;
+ } RdWrLR;
+
+ /* MIPS Multiply and accumulate instructions. */
+ struct {
+ MIPSMaccOp op;
+ Bool syned;
+
+ HReg srcL;
+ HReg srcR;
+ } Macc;
+
+ /* MIPS Floating point */
+ struct {
+ MIPSFpOp op;
+ HReg dst;
+ HReg src;
+ } FpUnary;
+ struct {
+ MIPSFpOp op;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } FpBinary;
+ struct {
+ MIPSFpOp op;
+ HReg dst;
+ HReg srcML;
+ HReg srcMR;
+ HReg srcAcc;
+ } FpMulAcc;
+ struct {
+ Bool isLoad;
+ UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */
+ HReg reg;
+ MIPSAMode *addr;
+ } FpLdSt;
+
+ struct {
+ MIPSFpOp op;
+ HReg dst;
+ HReg src;
+ } FpConvert;
+ struct {
+ MIPSFpOp op;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ UChar cond1;
+ } FpCompare;
+ struct {
+ MIPSFpOp op;
+ HReg dst;
+ HReg srcL;
+ MIPSRH *srcR;
+ HReg condR;
+ MIPSCondCode cond;
+ } MovCond;
+ /* Move from GP register to FCSR register. */
+ struct {
+ HReg src;
+ } MtFCSR;
+ /* Move from FCSR register to GP register. */
+ struct {
+ HReg dst;
+ } MfFCSR;
+ struct {
+ MIPSAMode* amCounter;
+ MIPSAMode* amFailAddr;
+ } EvCheck;
+ struct {
+ /* No fields. The address of the counter to inc is
+ installed later, post-translation, by patching it in,
+ as it is not known at translation time. */
+ } ProfInc;
+
+ } Min;
+} MIPSInstr;
+
+extern MIPSInstr *MIPSInstr_LI(HReg, ULong);
+extern MIPSInstr *MIPSInstr_Alu(MIPSAluOp, HReg, HReg, MIPSRH *);
+extern MIPSInstr *MIPSInstr_Shft(MIPSShftOp, Bool sz32, HReg, HReg, MIPSRH *);
+extern MIPSInstr *MIPSInstr_Unary(MIPSUnaryOp op, HReg dst, HReg src);
+extern MIPSInstr *MIPSInstr_Cmp(Bool, Bool, HReg, HReg, HReg, MIPSCondCode);
+
+extern MIPSInstr *MIPSInstr_Mul(Bool syned, Bool hi32, Bool sz32, HReg,
+ HReg, HReg);
+extern MIPSInstr *MIPSInstr_Div(Bool syned, Bool sz32, HReg, HReg);
+extern MIPSInstr *MIPSInstr_Madd(Bool, HReg, HReg);
+extern MIPSInstr *MIPSInstr_Msub(Bool, HReg, HReg);
+
+extern MIPSInstr *MIPSInstr_Load(UChar sz, HReg dst, MIPSAMode * src,
+ Bool mode64);
+extern MIPSInstr *MIPSInstr_Store(UChar sz, MIPSAMode * dst, HReg src,
+ Bool mode64);
+
+extern MIPSInstr *MIPSInstr_LoadL(UChar sz, HReg dst, MIPSAMode * src,
+ Bool mode64);
+extern MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src,
+ Bool mode64);
+
+extern MIPSInstr *MIPSInstr_Call(MIPSCondCode, Addr32, UInt, HReg);
+extern MIPSInstr *MIPSInstr_CallAlways(MIPSCondCode, Addr32, UInt);
+
+extern MIPSInstr *MIPSInstr_XDirect(Addr32 dstGA, MIPSAMode* amPC,
+ MIPSCondCode cond, Bool toFastEP);
+extern MIPSInstr *MIPSInstr_XIndir(HReg dstGA, MIPSAMode* amPC,
+ MIPSCondCode cond);
+extern MIPSInstr *MIPSInstr_XAssisted(HReg dstGA, MIPSAMode* amPC,
+ MIPSCondCode cond, IRJumpKind jk);
+
+extern MIPSInstr *MIPSInstr_FpUnary(MIPSFpOp op, HReg dst, HReg src);
+extern MIPSInstr *MIPSInstr_FpBinary(MIPSFpOp op, HReg dst, HReg srcL,
+ HReg srcR);
+extern MIPSInstr *MIPSInstr_FpConvert(MIPSFpOp op, HReg dst, HReg src);
+extern MIPSInstr *MIPSInstr_FpCompare(MIPSFpOp op, HReg dst, HReg srcL,
+ HReg srcR, UChar cond1);
+extern MIPSInstr *MIPSInstr_FpMulAcc(MIPSFpOp op, HReg dst, HReg srcML,
+ HReg srcMR, HReg srcAcc);
+extern MIPSInstr *MIPSInstr_FpLdSt(Bool isLoad, UChar sz, HReg, MIPSAMode *);
+extern MIPSInstr *MIPSInstr_FpSTFIW(HReg addr, HReg data);
+extern MIPSInstr *MIPSInstr_FpRSP(HReg dst, HReg src);
+extern MIPSInstr *MIPSInstr_FpCftI(Bool fromI, Bool int32, HReg dst, HReg src);
+extern MIPSInstr *MIPSInstr_FpCMov(MIPSCondCode, HReg dst, HReg src);
+extern MIPSInstr *MIPSInstr_MtFCSR(HReg src);
+extern MIPSInstr *MIPSInstr_MfFCSR(HReg dst);
+extern MIPSInstr *MIPSInstr_FpCmp(HReg dst, HReg srcL, HReg srcR);
+
+extern MIPSInstr *MIPSInstr_Mfhi(HReg dst);
+extern MIPSInstr *MIPSInstr_Mflo(HReg dst);
+extern MIPSInstr *MIPSInstr_Mthi(HReg src);
+extern MIPSInstr *MIPSInstr_Mtlo(HReg src);
+
+extern MIPSInstr *MIPSInstr_RdWrLR(Bool wrLR, HReg gpr);
+
+// srcL will be copied if !condR
+extern MIPSInstr *MIPSInstr_MovCond(HReg dst, HReg srcL, MIPSRH * src,
+ HReg condR, MIPSCondCode cond);
+
+extern MIPSInstr *MIPSInstr_EvCheck(MIPSAMode* amCounter,
+ MIPSAMode* amFailAddr );
+extern MIPSInstr *MIPSInstr_ProfInc( void );
+
+extern void ppMIPSInstr(MIPSInstr *, Bool mode64);
+
+/* Some functions that insulate the register allocator from details
+ of the underlying instruction set. */
+extern void getRegUsage_MIPSInstr (HRegUsage *, MIPSInstr *, Bool);
+extern void mapRegs_MIPSInstr (HRegRemap *, MIPSInstr *, Bool mode64);
+extern Bool isMove_MIPSInstr (MIPSInstr *, HReg *, HReg *);
+extern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, MIPSInstr* i,
+ Bool mode64,
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted );
+
+extern void genSpill_MIPS ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
+ HReg rreg, Int offset, Bool);
+extern void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
+ HReg rreg, Int offset, Bool);
+
+extern void getAllocableRegs_MIPS (Int *, HReg **, Bool mode64);
+extern HInstrArray *iselSB_MIPS ( IRSB*,
+ VexArch,
+ VexArchInfo*,
+ VexAbiInfo*,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga );
+
+/* How big is an event check? This is kind of a kludge because it
+ depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER,
+ and so assumes that they are both <= 128, and so can use the short
+ offset encoding. This is all checked with assertions, so in the
+ worst case we will merely assert at startup. */
+extern Int evCheckSzB_MIPS ( void );
+
+/* Perform a chaining and unchaining of an XDirect jump. */
+extern VexInvalRange chainXDirect_MIPS ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to,
+ Bool mode64 );
+
+extern VexInvalRange unchainXDirect_MIPS ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me,
+ Bool mode64 );
+
+/* Patch the counter location into an existing ProfInc point. */
+extern VexInvalRange patchProfInc_MIPS ( void* place_to_patch,
+ ULong* location_of_counter,
+ Bool mode64 );
+
+#endif /* ndef __LIBVEX_HOST_MIPS_HDEFS_H */
+
+/*---------------------------------------------------------------*/
+/*--- end host-mips_defs.h ---*/
+/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/host_mips_isel.c b/main/VEX/priv/host_mips_isel.c
new file mode 100644
index 0000000..347a682
--- /dev/null
+++ b/main/VEX/priv/host_mips_isel.c
@@ -0,0 +1,3263 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin host_mips_isel.c ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ 02110-1301, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "libvex_basictypes.h"
+#include "libvex_ir.h"
+#include "libvex.h"
+
+#include "main_util.h"
+#include "main_globals.h"
+#include "host_generic_regs.h"
+#include "host_mips_defs.h"
+
+/*---------------------------------------------------------*/
+/*--- Register Usage Conventions ---*/
+/*---------------------------------------------------------*/
+/*
+
+Integer Regs
+------------
+ZERO0 Reserved
+GPR1:9 Allocateable
+10 GuestStatePointer
+GPR1:9 Allocateable
+SP StackFramePointer
+RA LinkRegister
+
+*/
+
+static Bool mode64 = False;
+
+/* GPR register class for mips32/64 */
+#define HRcGPR(__mode64) (__mode64 ? HRcInt64 : HRcInt32)
+
+/* FPR register class for mips32/64 */
+#define HRcFPR(__mode64) (__mode64 ? HRcFlt64 : HRcFlt32)
+
+/*---------------------------------------------------------*/
+/*--- ISelEnv ---*/
+/*---------------------------------------------------------*/
+
+/* This carries around:
+
+ - A mapping from IRTemp to IRType, giving the type of any IRTemp we
+ might encounter. This is computed before insn selection starts,
+ and does not change.
+
+ - A mapping from IRTemp to HReg. This tells the insn selector
+ which virtual register(s) are associated with each IRTemp
+ temporary. This is computed before insn selection starts, and
+ does not change. We expect this mapping to map precisely the
+ same set of IRTemps as the type mapping does.
+
+ - vregmap holds the primary register for the IRTemp.
+ - vregmapHI is only used for 64-bit integer-typed
+ IRTemps. It holds the identity of a second
+ 32-bit virtual HReg, which holds the high half
+ of the value.
+
+ - The code array, that is, the insns selected so far.
+
+ - A counter, for generating new virtual registers.
+
+ - The host subarchitecture we are selecting insns for.
+ This is set at the start and does not change.
+
+ - A Bool for indicating whether we may generate chain-me
+ instructions for control flow transfers, or whether we must use
+ XAssisted.
+
+ - The maximum guest address of any guest insn in this block.
+ Actually, the address of the highest-addressed byte from any insn
+ in this block. Is set at the start and does not change. This is
+ used for detecting jumps which are definitely forward-edges from
+ this block, and therefore can be made (chained) to the fast entry
+ point of the destination, thereby avoiding the destination's
+ event check.
+
+ Note, this is all (well, mostly) host-independent.
+*/
+
+typedef
+ struct {
+ /* Constant -- are set at the start and do not change. */
+ IRTypeEnv* type_env;
+
+ HReg* vregmap;
+ HReg* vregmapHI;
+ Int n_vregmap;
+
+ UInt hwcaps;
+ Bool mode64;
+
+ Bool chainingAllowed;
+ Addr64 max_ga;
+
+ /* These are modified as we go along. */
+ HInstrArray* code;
+ Int vreg_ctr;
+ }
+ ISelEnv;
+
+static HReg lookupIRTemp(ISelEnv * env, IRTemp tmp)
+{
+ vassert(tmp >= 0);
+ vassert(tmp < env->n_vregmap);
+ return env->vregmap[tmp];
+}
+
+static void lookupIRTemp64(HReg * vrHI, HReg * vrLO, ISelEnv * env, IRTemp tmp)
+{
+ vassert(tmp >= 0);
+ vassert(tmp < env->n_vregmap);
+ vassert(env->vregmapHI[tmp] != INVALID_HREG);
+ *vrLO = env->vregmap[tmp];
+ *vrHI = env->vregmapHI[tmp];
+}
+
+static void
+lookupIRTempPair(HReg * vrHI, HReg * vrLO, ISelEnv * env, IRTemp tmp)
+{
+ vassert(env->mode64);
+ vassert(tmp >= 0);
+ vassert(tmp < env->n_vregmap);
+ vassert(env->vregmapHI[tmp] != INVALID_HREG);
+ *vrLO = env->vregmap[tmp];
+ *vrHI = env->vregmapHI[tmp];
+}
+
+static void addInstr(ISelEnv * env, MIPSInstr * instr)
+{
+ addHInstr(env->code, instr);
+ if (vex_traceflags & VEX_TRACE_VCODE) {
+ ppMIPSInstr(instr, mode64);
+ vex_printf("\n");
+ }
+}
+
+static HReg newVRegI(ISelEnv * env)
+{
+ HReg reg = mkHReg(env->vreg_ctr, HRcGPR(env->mode64),
+ True /*virtual reg */ );
+ env->vreg_ctr++;
+ return reg;
+}
+
+static HReg newVRegD(ISelEnv * env)
+{
+ HReg reg = mkHReg(env->vreg_ctr, HRcFlt64, True /*virtual reg */ );
+ env->vreg_ctr++;
+ return reg;
+}
+
+static HReg newVRegF(ISelEnv * env)
+{
+ HReg reg = mkHReg(env->vreg_ctr, HRcFPR(env->mode64),
+ True /*virtual reg */ );
+ env->vreg_ctr++;
+ return reg;
+}
+
+static void add_to_sp(ISelEnv * env, UInt n)
+{
+ HReg sp = StackPointer(mode64);
+ vassert(n < 256 && (n % 8) == 0);
+ addInstr(env, MIPSInstr_Alu(Malu_ADD, sp, sp, MIPSRH_Imm(True,
+ toUShort(n))));
+}
+
+static void sub_from_sp(ISelEnv * env, UInt n)
+{
+ HReg sp = StackPointer(mode64);
+ vassert(n < 256 && (n % 8) == 0);
+ addInstr(env, MIPSInstr_Alu(Malu_SUB, sp, sp,
+ MIPSRH_Imm(True, toUShort(n))));
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Forward declarations ---*/
+/*---------------------------------------------------------*/
+
+/* These are organised as iselXXX and iselXXX_wrk pairs. The
+ iselXXX_wrk do the real work, but are not to be called directly.
+ For each XXX, iselXXX calls its iselXXX_wrk counterpart, then
+ checks that all returned registers are virtual. You should not
+ call the _wrk version directly.
+*/
+/* 32-bit mode: Compute an I8/I16/I32 into a RH
+ (reg-or-halfword-immediate).
+ It's important to specify whether the immediate is to be regarded
+ as signed or not. If yes, this will never return -32768 as an
+ immediate; this guaranteed that all signed immediates that are
+ return can have their sign inverted if need be.
+*/
+static MIPSRH *iselWordExpr_RH_wrk(ISelEnv * env, Bool syned, IRExpr * e);
+static MIPSRH *iselWordExpr_RH(ISelEnv * env, Bool syned, IRExpr * e);
+
+/* Compute an I8 into a reg-or-5-bit-unsigned-immediate, the latter being an immediate in
+ the range 1 .. 31 inclusive. Used for doing shift amounts. */
+static MIPSRH *iselWordExpr_RH5u_wrk(ISelEnv * env, IRExpr * e);
+static MIPSRH *iselWordExpr_RH5u(ISelEnv * env, IRExpr * e);
+
+/* compute an I8/I16/I32 into a GPR*/
+static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e);
+static HReg iselWordExpr_R(ISelEnv * env, IRExpr * e);
+
+/* compute an I32 into an AMode. */
+static MIPSAMode *iselWordExpr_AMode_wrk(ISelEnv * env, IRExpr * e,
+ IRType xferTy);
+static MIPSAMode *iselWordExpr_AMode(ISelEnv * env, IRExpr * e, IRType xferTy);
+
+static void iselInt64Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env,
+ IRExpr * e);
+static void iselInt64Expr(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e);
+
+/* 64-bit mode ONLY: compute an I128 into a GPR64 pair. */
+static void iselInt128Expr_wrk(HReg * rHi, HReg * rLo,
+ ISelEnv * env, IRExpr * e);
+static void iselInt128Expr(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e);
+
+static MIPSCondCode iselCondCode_wrk(ISelEnv * env, IRExpr * e);
+static MIPSCondCode iselCondCode(ISelEnv * env, IRExpr * e);
+
+static HReg iselDblExpr_wrk(ISelEnv * env, IRExpr * e);
+static HReg iselDblExpr(ISelEnv * env, IRExpr * e);
+
+static HReg iselFltExpr_wrk(ISelEnv * env, IRExpr * e);
+static HReg iselFltExpr(ISelEnv * env, IRExpr * e);
+
+static void set_MIPS_rounding_mode(ISelEnv * env, IRExpr * mode)
+{
+ /*
+ rounding mode | MIPS | IR
+ ------------------------
+ to nearest | 00 | 00
+ to zero | 01 | 11
+ to +infinity | 10 | 10
+ to -infinity | 11 | 01
+ */
+ // rm_MIPS32 = XOR(rm_IR , (rm_IR << 1)) & 2
+ HReg irrm = iselWordExpr_R(env, mode);
+ HReg tmp = newVRegI(env);
+ HReg fcsr_old = newVRegI(env);
+ MIPSAMode *am_addr;
+
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, irrm,
+ MIPSRH_Imm(False, 1)));
+ addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp, MIPSRH_Imm(False, 3)));
+ /* save old value of FCSR */
+ addInstr(env, MIPSInstr_MfFCSR(fcsr_old));
+ sub_from_sp(env, 8); // Move SP down 4 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ //store old FCSR to stack
+ addInstr(env, MIPSInstr_Store(4, am_addr, fcsr_old, mode64));
+
+ //set new value of FCSR
+ addInstr(env, MIPSInstr_MtFCSR(irrm));
+}
+
+static void set_MIPS_rounding_default(ISelEnv * env)
+{
+ HReg fcsr = newVRegI(env);
+ // load as float
+ MIPSAMode *am_addr;
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ addInstr(env, MIPSInstr_Load(4, fcsr, am_addr, mode64));
+
+ add_to_sp(env, 8); // Reset SP
+
+ //set new value of FCSR
+ addInstr(env, MIPSInstr_MtFCSR(fcsr));
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Misc helpers ---*/
+/*---------------------------------------------------------*/
+
+/* Make an int reg-reg move. */
+static MIPSInstr *mk_iMOVds_RR(HReg r_dst, HReg r_src)
+{
+ vassert(hregClass(r_dst) == hregClass(r_src));
+ vassert(hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64);
+ return MIPSInstr_Alu(Malu_OR, r_dst, r_src, MIPSRH_Reg(r_src));
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Function call helpers ---*/
+/*---------------------------------------------------------*/
+
+/* Used only in doHelperCall. See big comment in doHelperCall re
+ handling of register-parameter args. This function figures out
+ whether evaluation of an expression might require use of a fixed
+ register. If in doubt return True (safe but suboptimal).
+*/
+static Bool mightRequireFixedRegs(IRExpr * e)
+{
+ switch (e->tag) {
+ case Iex_RdTmp:
+ case Iex_Const:
+ case Iex_Get:
+ return False;
+ default:
+ return True;
+ }
+}
+
+/* Load 2*I32 regs to fp reg */
+static HReg mk_LoadRR32toFPR(ISelEnv * env, HReg r_srcHi, HReg r_srcLo)
+{
+ HReg fr_dst = newVRegD(env);
+ MIPSAMode *am_addr0, *am_addr1;
+
+ vassert(hregClass(r_srcHi) == HRcInt32);
+ vassert(hregClass(r_srcLo) == HRcInt32);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr0 = MIPSAMode_IR(0, StackPointer(mode64));
+ am_addr1 = MIPSAMode_IR(8, StackPointer(mode64));
+
+ // store hi,lo as Ity_I32's
+ addInstr(env, MIPSInstr_Store(4, am_addr0, r_srcLo, mode64));
+ addInstr(env, MIPSInstr_Store(4, am_addr1, r_srcHi, mode64));
+
+ // load as float
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 8, fr_dst, am_addr0));
+
+ add_to_sp(env, 16); // Reset SP
+ return fr_dst;
+}
+
+/* Do a complete function call. guard is a Ity_Bit expression
+ indicating whether or not the call happens. If guard==NULL, the
+ call is unconditional. */
+
+static void doHelperCall(ISelEnv * env, Bool passBBP, IRExpr * guard,
+ IRCallee * cee, IRExpr ** args)
+{
+ MIPSCondCode cc;
+ HReg argregs[MIPS_N_REGPARMS];
+ HReg tmpregs[MIPS_N_REGPARMS];
+ Bool go_fast;
+ Int n_args, i, argreg;
+ UInt argiregs;
+ ULong target;
+ HReg src = 0;
+
+ /* MIPS O32 calling convention: up to four registers ($a0 ... $a3)
+ are allowed to be used for passing integer arguments. They correspond
+ to regs GPR4 ... GPR7. Note that the cee->regparms field is meaningless
+ on MIPS host (since we only implement one calling convention) and so we
+ always ignore it. */
+
+ /* MIPS 64 calling convention: up to four registers ($a0 ... $a7)
+ are allowed to be used for passing integer arguments. They correspond
+ to regs GPR4 ... GPR11. Note that the cee->regparms field is meaningless
+ on MIPS host (since we only implement one calling convention) and so we
+ always ignore it. */
+ n_args = 0;
+ for (i = 0; args[i]; i++)
+ n_args++;
+
+ if (MIPS_N_REGPARMS < n_args + (passBBP ? 1 : 0)) {
+ vpanic("doHelperCall(MIPS): cannot currently handle > 4 args");
+ }
+ argregs[0] = hregMIPS_GPR4(mode64);
+ argregs[1] = hregMIPS_GPR5(mode64);
+ argregs[2] = hregMIPS_GPR6(mode64);
+ argregs[3] = hregMIPS_GPR7(mode64);
+ argiregs = 0;
+
+ tmpregs[0] = tmpregs[1] = tmpregs[2] = tmpregs[3] = INVALID_HREG;
+
+ /* First decide which scheme (slow or fast) is to be used. First
+ assume the fast scheme, and select slow if any contraindications
+ (wow) appear. */
+
+ go_fast = True;
+
+ if (guard) {
+ if (guard->tag == Iex_Const && guard->Iex.Const.con->tag == Ico_U1
+ && guard->Iex.Const.con->Ico.U1 == True) {
+ /* unconditional */
+ } else {
+ /* Not manifestly unconditional -- be conservative. */
+ go_fast = False;
+ }
+ }
+
+ if (go_fast) {
+ for (i = 0; i < n_args; i++) {
+ if (mightRequireFixedRegs(args[i])) {
+ go_fast = False;
+ break;
+ }
+ }
+ }
+
+ /* save GuestStatePointer on the stack */
+ sub_from_sp(env, 8); // Move SP down 4 bytes
+ addInstr(env, MIPSInstr_Store(4, MIPSAMode_IR(0, StackPointer(mode64)),
+ GuestStatePointer(mode64), mode64));
+
+ /* At this point the scheme to use has been established. Generate
+ code to get the arg values into the argument rregs. */
+ if (go_fast) {
+ /* FAST SCHEME */
+ argreg = 0;
+ if (passBBP) {
+ argiregs |= (1 << (argreg + 4));
+ addInstr(env, mk_iMOVds_RR(argregs[argreg],
+ GuestStatePointer(mode64)));
+ argreg++;
+ }
+
+ for (i = 0; i < n_args; i++) {
+ vassert(argreg < MIPS_N_REGPARMS);
+ vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I32
+ || typeOfIRExpr(env->type_env, args[i]) == Ity_I64);
+ if (typeOfIRExpr(env->type_env, args[i]) == Ity_I32) {
+ argiregs |= (1 << (argreg + 4));
+ addInstr(env, mk_iMOVds_RR(argregs[argreg], iselWordExpr_R(env,
+ args[i])));
+ } else { // Ity_I64
+ vassert(mode64);
+ argiregs |= (1 << (argreg + 4));
+ addInstr(env, mk_iMOVds_RR(argregs[argreg], iselWordExpr_R(env,
+ args[i])));
+ }
+ argreg++;
+ }
+ /* Fast scheme only applies for unconditional calls. Hence: */
+ cc = MIPScc_AL;
+ } else {
+ /* SLOW SCHEME; move via temporaries */
+ argreg = 0;
+ if (passBBP) {
+ /* This is pretty stupid; better to move directly to r3
+ after the rest of the args are done. */
+ tmpregs[argreg] = newVRegI(env);
+ addInstr(env, mk_iMOVds_RR(tmpregs[argreg],
+ GuestStatePointer(mode64)));
+ argreg++;
+ }
+ for (i = 0; i < n_args; i++) {
+ vassert(argreg < MIPS_N_REGPARMS);
+ vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I32
+ || typeOfIRExpr(env->type_env, args[i]) == Ity_I64);
+ if (typeOfIRExpr(env->type_env, args[i]) == Ity_I32) {
+ tmpregs[argreg] = iselWordExpr_R(env, args[i]);
+ } else { // Ity_I64
+ vassert(mode64);
+ tmpregs[argreg] = iselWordExpr_R(env, args[i]);
+ }
+ argreg++;
+ }
+
+ /* Now we can compute the condition. We can't do it earlier
+ because the argument computations could trash the condition
+ codes. Be a bit clever to handle the common case where the
+ guard is 1:Bit. */
+ cc = MIPScc_AL;
+ if (guard) {
+ if (guard->tag == Iex_Const && guard->Iex.Const.con->tag == Ico_U1
+ && guard->Iex.Const.con->Ico.U1 == True) {
+ /* unconditional -- do nothing */
+ } else {
+ cc = iselCondCode(env, guard);
+ src = iselWordExpr_R(env, guard);
+ }
+ }
+ /* Move the args to their final destinations. */
+ for (i = 0; i < argreg; i++) {
+ if (tmpregs[i] == INVALID_HREG) // Skip invalid regs
+ continue;
+ /* None of these insns, including any spill code that might
+ be generated, may alter the condition codes. */
+ argiregs |= (1 << (i + 4));
+ addInstr(env, mk_iMOVds_RR(argregs[i], tmpregs[i]));
+ }
+ }
+
+ target = toUInt(Ptr_to_ULong(cee->addr));
+
+ /* Finally, the call itself. */
+ if (mode64)
+ if (cc == MIPScc_AL) {
+ addInstr(env, MIPSInstr_CallAlways(cc, target, argiregs));
+ } else {
+ addInstr(env, MIPSInstr_Call(cc, target, argiregs, src));
+ } else if (cc == MIPScc_AL) {
+ addInstr(env, MIPSInstr_CallAlways(cc, (Addr32) target, argiregs));
+ } else {
+ addInstr(env, MIPSInstr_Call(cc, (Addr32) target, argiregs, src));
+ }
+ /* restore GuestStatePointer */
+ addInstr(env, MIPSInstr_Load(4, GuestStatePointer(mode64),
+ MIPSAMode_IR(0, StackPointer(mode64)), mode64));
+ add_to_sp(env, 8); // Reset SP
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Integer expression auxiliaries ---*/
+/*---------------------------------------------------------*/
+
+/* --------------------- AMODEs --------------------- */
+
+/* Return an AMode which computes the value of the specified
+ expression, possibly also adding insns to the code list as a
+ result. The expression may only be a word-size one.
+*/
+
+static Bool uInt_fits_in_16_bits(UInt u)
+{
+ Int i = u & 0xFFFF;
+ i <<= 16;
+ i >>= 16;
+ return toBool(u == (UInt) i);
+}
+
+static Bool sane_AMode(ISelEnv * env, MIPSAMode * am)
+{
+ switch (am->tag) {
+ case Mam_IR:
+ return toBool(hregClass(am->Mam.IR.base) == HRcGPR(mode64) &&
+ hregIsVirtual(am->Mam.IR.base) &&
+ uInt_fits_in_16_bits(am->Mam.IR.index));
+ case Mam_RR:
+ return toBool(hregClass(am->Mam.RR.base) == HRcGPR(mode64) &&
+ hregIsVirtual(am->Mam.RR.base) &&
+ hregClass(am->Mam.RR.index) == HRcGPR(mode64) &&
+ hregIsVirtual(am->Mam.IR.index));
+ default:
+ vpanic("sane_AMode: unknown mips amode tag");
+ }
+}
+
+static MIPSAMode *iselWordExpr_AMode(ISelEnv * env, IRExpr * e, IRType xferTy)
+{
+ MIPSAMode *am = iselWordExpr_AMode_wrk(env, e, xferTy);
+ vassert(sane_AMode(env, am));
+ return am;
+}
+
+/* DO NOT CALL THIS DIRECTLY ! */
+static MIPSAMode *iselWordExpr_AMode_wrk(ISelEnv * env, IRExpr * e,
+ IRType xferTy)
+{
+ IRType ty = typeOfIRExpr(env->type_env, e);
+ {
+ vassert(ty == Ity_I32);
+
+ /* Add32(expr,i), where i == sign-extend of (i & 0xFFFF) */
+ if (e->tag == Iex_Binop
+ && e->Iex.Binop.op == Iop_Add32
+ && e->Iex.Binop.arg2->tag == Iex_Const
+ && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32
+ && uInt_fits_in_16_bits(e->Iex.Binop.arg2->Iex.Const.con-> Ico.U32)) {
+ return MIPSAMode_IR((Int) e->Iex.Binop.arg2->Iex.Const.con->Ico.U32,
+ iselWordExpr_R(env, e->Iex.Binop.arg1));
+ }
+
+ /* Add32(expr,expr) */
+ if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_Add32) {
+ HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2);
+
+ return MIPSAMode_RR(r_idx, r_base);
+ }
+ }
+
+ /* Doesn't match anything in particular. Generate it into
+ a register and use that. */
+ return MIPSAMode_IR(0, iselWordExpr_R(env, e));
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Integer expressions (64/32/16/8 bit) ---*/
+/*---------------------------------------------------------*/
+
+/* Select insns for an integer-typed expression, and add them to the
+ code list. Return a reg holding the result. This reg will be a
+ virtual register. THE RETURNED REG MUST NOT BE MODIFIED. If you
+ want to modify it, ask for a new vreg, copy it in there, and modify
+ the copy. The register allocator will do its best to map both
+ vregs to the same real register, so the copies will often disappear
+ later in the game.
+
+ This should handle expressions of 64, 32, 16 and 8-bit type.
+ All results are returned in a (mode64 ? 64bit : 32bit) register.
+ For 16- and 8-bit expressions, the upper (32/48/56 : 16/24) bits
+ are arbitrary, so you should mask or sign extend partial values
+ if necessary.
+*/
+static HReg iselWordExpr_R(ISelEnv * env, IRExpr * e)
+{
+ HReg r = iselWordExpr_R_wrk(env, e);
+ /* sanity checks ... */
+
+ vassert(hregClass(r) == HRcGPR(env->mode64));
+ vassert(hregIsVirtual(r));
+ return r;
+}
+
+/* DO NOT CALL THIS DIRECTLY ! */
+static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e)
+{
+ IRType ty = typeOfIRExpr(env->type_env, e);
+ vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I1
+ || ty == Ity_F32 || (ty == Ity_I64 && mode64)
+ || (ty == Ity_I128 && mode64));
+
+ switch (e->tag) {
+ /* --------- TEMP --------- */
+ case Iex_RdTmp:
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
+
+ /* --------- LOAD --------- */
+ case Iex_Load: {
+ HReg r_dst = newVRegI(env);
+ MIPSAMode *am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty);
+
+ if (e->Iex.Load.end != Iend_LE
+ && e->Iex.Load.end != Iend_BE)
+ goto irreducible;
+
+ addInstr(env, MIPSInstr_Load(toUChar(sizeofIRType(ty)),
+ r_dst, am_addr, mode64));
+ return r_dst;
+ }
+
+ /* --------- BINARY OP --------- */
+ case Iex_Binop: {
+ MIPSAluOp aluOp;
+ MIPSShftOp shftOp;
+
+ /* Is it an addition or logical style op? */
+ switch (e->Iex.Binop.op) {
+ case Iop_Add32:
+ aluOp = Malu_ADD;
+ break;
+
+ case Iop_Sub8:
+ case Iop_Sub16:
+ case Iop_Sub32:
+ aluOp = Malu_SUB;
+ break;
+
+ case Iop_And32:
+ case Iop_And64:
+ aluOp = Malu_AND;
+ break;
+
+ case Iop_Or32:
+ case Iop_Or64:
+ aluOp = Malu_OR;
+ break;
+
+ case Iop_Xor32:
+ case Iop_Xor64:
+ aluOp = Malu_XOR;
+ break;
+
+ default:
+ aluOp = Malu_INVALID;
+ break;
+ }
+
+ /* For commutative ops we assume any literal
+ values are on the second operand. */
+ if (aluOp != Malu_INVALID) {
+ HReg r_dst = newVRegI(env);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ MIPSRH *ri_srcR = NULL;
+ /* get right arg into an RH, in the appropriate way */
+ switch (aluOp) {
+ case Malu_ADD:
+ case Malu_SUB:
+ ri_srcR = iselWordExpr_RH(env, True /*signed */ ,
+ e->Iex.Binop.arg2);
+ break;
+ case Malu_AND:
+ case Malu_OR:
+ case Malu_XOR:
+ ri_srcR = iselWordExpr_RH(env, False /*unsigned */,
+ e->Iex.Binop.arg2);
+ break;
+ default:
+ vpanic("iselWordExpr_R_wrk-aluOp-arg2");
+ }
+ addInstr(env, MIPSInstr_Alu(aluOp, r_dst, r_srcL, ri_srcR));
+ return r_dst;
+ }
+
+ /* a shift? */
+ switch (e->Iex.Binop.op) {
+ case Iop_Shl32:
+ case Iop_Shl64:
+ shftOp = Mshft_SLL;
+ break;
+ case Iop_Shr32:
+ case Iop_Shr64:
+ shftOp = Mshft_SRL;
+ break;
+ case Iop_Sar32:
+ case Iop_Sar64:
+ shftOp = Mshft_SRA;
+ break;
+ default:
+ shftOp = Mshft_INVALID;
+ break;
+ }
+
+ /* we assume any literal values are on the second operand. */
+ if (shftOp != Mshft_INVALID) {
+ HReg r_dst = newVRegI(env);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ MIPSRH *ri_srcR = NULL;
+ /* get right arg into an RH, in the appropriate way */
+ switch (shftOp) {
+ case Mshft_SLL:
+ case Mshft_SRL:
+ case Mshft_SRA:
+ ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop. arg2);
+ break;
+ default:
+ vpanic("iselIntExpr_R_wrk-shftOp-arg2");
+ }
+ /* widen the left arg if needed */
+ /*TODO do we need this? */
+ if (ty == Ity_I8 || ty == Ity_I16)
+ goto irreducible;
+ if (ty == Ity_I64) {
+ vassert(mode64);
+ addInstr(env, MIPSInstr_Shft(shftOp, False/*64bit shift */,
+ r_dst, r_srcL, ri_srcR));
+ } else {
+ addInstr(env, MIPSInstr_Shft(shftOp, True /*32bit shift */,
+ r_dst, r_srcL, ri_srcR));
+ }
+ return r_dst;
+ }
+
+ /* Cmp*32*(x,y) ? */
+ if (e->Iex.Binop.op == Iop_CmpEQ32
+ || e->Iex.Binop.op == Iop_CmpNE32
+ || e->Iex.Binop.op == Iop_CmpNE64
+ || e->Iex.Binop.op == Iop_CmpLT32S
+ || e->Iex.Binop.op == Iop_CmpLT32U
+ || e->Iex.Binop.op == Iop_CmpLT64U
+ || e->Iex.Binop.op == Iop_CmpLE32S
+ || e->Iex.Binop.op == Iop_CmpLE64S
+ || e->Iex.Binop.op == Iop_CmpLT64S
+ || e->Iex.Binop.op == Iop_CmpEQ64) {
+
+ Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S
+ || e->Iex.Binop.op == Iop_CmpLE32S
+ || e->Iex.Binop.op == Iop_CmpLT64S
+ || e->Iex.Binop.op == Iop_CmpLE64S);
+ Bool size32;
+ HReg dst = newVRegI(env);
+ HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2);
+
+ MIPSCondCode cc;
+
+ switch (e->Iex.Binop.op) {
+ case Iop_CmpEQ32:
+ cc = MIPScc_EQ;
+ size32 = True;
+ break;
+ case Iop_CmpNE32:
+ cc = MIPScc_NE;
+ size32 = True;
+ break;
+ case Iop_CmpNE64:
+ cc = MIPScc_NE;
+ size32 = True;
+ break;
+ case Iop_CmpLT32S:
+ cc = MIPScc_LT;
+ size32 = True;
+ break;
+ case Iop_CmpLT32U:
+ cc = MIPScc_LO;
+ size32 = True;
+ break;
+ case Iop_CmpLT64U:
+ cc = MIPScc_LO;
+ size32 = False;
+ break;
+ case Iop_CmpLE32S:
+ cc = MIPScc_LE;
+ size32 = True;
+ break;
+ case Iop_CmpLE64S:
+ cc = MIPScc_LE;
+ size32 = False;
+ break;
+ case Iop_CmpLT64S:
+ cc = MIPScc_LT;
+ size32 = False;
+ break;
+ case Iop_CmpEQ64:
+ cc = MIPScc_EQ;
+ size32 = False;
+ break;
+ default:
+ vpanic
+ ("iselCondCode(mips): CmpXX32 or CmpXX64");
+ }
+
+ addInstr(env, MIPSInstr_Cmp(syned, size32, dst, r1, r2, cc));
+ return dst;
+ }
+
+ if (e->Iex.Binop.op == Iop_Max32U) {
+ /*
+ tmp = argR - argL;
+ dst = argL;
+ bltz tmp,2;
+ dst = argR;
+
+ */
+ HReg argL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ MIPSRH *argR = iselWordExpr_RH(env, False /*signed */ ,
+ e->Iex.Binop.arg2);
+ HReg dst = newVRegI(env);
+ HReg tmp = newVRegI(env);
+ addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp, argL, argR));
+ addInstr(env, MIPSInstr_MovCond(dst, argL, argR, tmp, MIPScc_MI));
+
+ return dst;
+ }
+
+ if (e->Iex.Binop.op == Iop_Mul32 || e->Iex.Binop.op == Iop_Mul64) {
+ Bool sz32 = (e->Iex.Binop.op == Iop_Mul32);
+ HReg r_dst = newVRegI(env);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ addInstr(env, MIPSInstr_Mul(False/*Unsigned or Signed */ ,
+ False /*widen */ ,
+ sz32 /*32bit or 64bit */,
+ r_dst, r_srcL, r_srcR));
+ return r_dst;
+ }
+
+ if (e->Iex.Binop.op == Iop_MullU32 || e->Iex.Binop.op == Iop_MullS32) {
+ HReg r_dst = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg tLo = newVRegI(env);
+ HReg tLo_1 = newVRegI(env);
+ HReg tHi_1 = newVRegI(env);
+ HReg mask = newVRegI(env);
+
+ Bool syned = toBool(e->Iex.Binop.op == Iop_MullS32);
+ Bool size = toBool(e->Iex.Binop.op == Iop_MullS32)
+ || toBool(e->Iex.Binop.op == Iop_MullU32);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ addInstr(env, MIPSInstr_Mul(syned /*Unsigned or Signed */ ,
+ True /*widen */ ,
+ size /*32bit or 64bit mul */ ,
+ r_dst, r_srcL, r_srcR));
+
+ addInstr(env, MIPSInstr_Mfhi(tHi));
+ addInstr(env, MIPSInstr_Mflo(tLo));
+
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, False, tHi_1,
+ tHi, MIPSRH_Imm(False, 32)));
+
+ addInstr(env, MIPSInstr_LI(mask, 0xffffffff));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
+ MIPSRH_Reg(mask)));
+
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
+ MIPSRH_Reg(tLo_1)));
+
+ return r_dst;
+ }
+
+ if (e->Iex.Binop.op == Iop_CmpF64) {
+ HReg r_srcL, r_srcR;
+ {
+ r_srcL = iselDblExpr(env, e->Iex.Binop.arg1);
+ r_srcR = iselDblExpr(env, e->Iex.Binop.arg2);
+ }
+ HReg tmp = newVRegI(env);
+ HReg r_ccMIPS = newVRegI(env);
+ HReg r_ccIR = newVRegI(env);
+ HReg r_ccIR_b0 = newVRegI(env);
+ HReg r_ccIR_b2 = newVRegI(env);
+ HReg r_ccIR_b6 = newVRegI(env);
+
+ /* Create in dst, the IRCmpF64Result encoded result. */
+ // chech for EQ
+ addInstr(env, MIPSInstr_FpCompare(Mfp_CMP, tmp, r_srcL, r_srcR,
+ toUChar(2)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, r_ccMIPS, tmp,
+ MIPSRH_Imm(False, 22)));
+ // chech for UN
+ addInstr(env, MIPSInstr_FpCompare(Mfp_CMP, tmp, r_srcL, r_srcR,
+ toUChar(1)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp, tmp,
+ MIPSRH_Imm(False, 23)));
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS,
+ MIPSRH_Reg(tmp)));
+ // chech for LT
+ addInstr(env, MIPSInstr_FpCompare(Mfp_CMP, tmp, r_srcL, r_srcR,
+ toUChar(12)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp,
+ tmp, MIPSRH_Imm(False, 21)));
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS,
+ MIPSRH_Reg(tmp)));
+ // chech for GT
+ addInstr(env, MIPSInstr_FpCompare(Mfp_CMP, tmp, r_srcL, r_srcR,
+ toUChar(15)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp, tmp,
+ MIPSRH_Imm(False, 20)));
+
+ addInstr(env, MIPSInstr_Alu(Malu_NOR, tmp, tmp, MIPSRH_Reg(tmp)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tmp, tmp,
+ MIPSRH_Imm(False, 8)));
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS,
+ MIPSRH_Reg(tmp)));
+ /* Map compare result from PPC to IR,
+ conforming to CmpF64 definition. */
+ /*
+ FP cmp result | MIPS | IR
+ --------------------------
+ UN | 0x1 | 0x45
+ EQ | 0x2 | 0x40
+ GT | 0x4 | 0x00
+ LT | 0x8 | 0x01
+ */
+
+ // r_ccIR_b0 = r_ccPPC[0] | r_ccPPC[3]
+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True, r_ccIR_b0, r_ccMIPS,
+ MIPSRH_Imm(False, 0x3)));
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR_b0, r_ccMIPS,
+ MIPSRH_Reg(r_ccIR_b0)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_ccIR_b0, r_ccIR_b0,
+ MIPSRH_Imm(False, 0x1)));
+
+ // r_ccIR_b2 = r_ccPPC[0]
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, r_ccIR_b2, r_ccMIPS,
+ MIPSRH_Imm(False, 0x2)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_ccIR_b2, r_ccIR_b2,
+ MIPSRH_Imm(False, 0x4)));
+
+ // r_ccIR_b6 = r_ccPPC[0] | r_ccPPC[1]
+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True, r_ccIR_b6,
+ r_ccMIPS, MIPSRH_Imm(False, 0x1)));
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR_b6, r_ccMIPS,
+ MIPSRH_Reg(r_ccIR_b6)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, r_ccIR_b6, r_ccIR_b6,
+ MIPSRH_Imm(False, 0x6)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_ccIR_b6, r_ccIR_b6,
+ MIPSRH_Imm(False, 0x40)));
+
+ // r_ccIR = r_ccIR_b0 | r_ccIR_b2 | r_ccIR_b6
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR, r_ccIR_b0,
+ MIPSRH_Reg(r_ccIR_b2)));
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR, r_ccIR,
+ MIPSRH_Reg(r_ccIR_b6)));
+ return r_ccIR;
+ }
+
+ if (e->Iex.Binop.op == Iop_DivModU64to32 ||
+ e->Iex.Binop.op == Iop_DivModS64to32) {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg mask = newVRegI(env);
+ HReg tLo_1 = newVRegI(env);
+ HReg tHi_1 = newVRegI(env);
+ HReg r_dst = newVRegI(env);
+ Bool syned = toBool(e->Iex.Binop.op == Iop_DivModS64to32);
+
+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+
+ addInstr(env, MIPSInstr_Div(syned, True, r_srcL, r_srcR));
+ addInstr(env, MIPSInstr_Mfhi(tHi));
+ addInstr(env, MIPSInstr_Mflo(tLo));
+
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, False, tHi_1, tHi,
+ MIPSRH_Imm(False, 32)));
+
+ addInstr(env, MIPSInstr_LI(mask, 0xffffffff));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
+ MIPSRH_Reg(mask)));
+
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
+ MIPSRH_Reg(tLo_1)));
+
+ return r_dst;
+ }
+
+ if (e->Iex.Binop.op == Iop_32HLto64) {
+ vassert(mode64);
+ HReg tHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg tLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ HReg tLo_1 = newVRegI(env);
+ HReg tHi_1 = newVRegI(env);
+ HReg r_dst = newVRegI(env);
+ HReg mask = newVRegI(env);
+
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, False, tHi_1, tHi,
+ MIPSRH_Imm(False, 32)));
+
+ addInstr(env, MIPSInstr_LI(mask, 0xffffffff));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
+ MIPSRH_Reg(mask)));
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
+ MIPSRH_Reg(tLo_1)));
+
+ return r_dst;
+ }
+
+ if (e->Iex.Binop.op == Iop_F64toI32S) {
+ HReg valD = iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg valS = newVRegF(env);
+ HReg r_dst = newVRegI(env);
+ MIPSAMode *am_addr;
+
+ set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, MIPSInstr_FpConvert(Mfp_CVTWD, valS, valD));
+ set_MIPS_rounding_default(env);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as F32
+ addInstr(env, MIPSInstr_FpLdSt(False/*store */ , 4, valS, am_addr));
+ // load as I32
+ addInstr(env, MIPSInstr_Load(4, r_dst, am_addr, mode64));
+
+ add_to_sp(env, 16); // Reset SP
+
+ return r_dst;
+ }
+
+ break;
+ }
+
+ /* --------- UNARY OP --------- */
+ case Iex_Unop: {
+ IROp op_unop = e->Iex.Unop.op;
+
+ switch (op_unop) {
+ case Iop_1Sto32:
+ case Iop_8Sto32:
+ case Iop_16Sto32:
+ case Iop_16Sto64:
+ case Iop_8Sto64:
+ case Iop_1Sto64: {
+ HReg r_dst = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ Bool sz32;
+ UShort amt;
+ switch (op_unop) {
+ case Iop_1Sto32:
+ amt = 31;
+ sz32 = True;
+ break;
+ case Iop_16Sto32:
+ amt = 16;
+ sz32 = True;
+ break;
+ case Iop_16Sto64:
+ amt = 48;
+ sz32 = False;
+ break;
+ case Iop_8Sto32:
+ amt = 24;
+ sz32 = True;
+ break;
+ case Iop_8Sto64:
+ amt = 56;
+ sz32 = False;
+ break;
+ case Iop_1Sto64:
+ amt = 63;
+ sz32 = False;
+ break;
+ default:
+ vassert(0);
+ }
+
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, sz32, r_dst, r_src,
+ MIPSRH_Imm(False, amt)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, sz32, r_dst, r_dst,
+ MIPSRH_Imm(False, amt)));
+ return r_dst;
+ }
+
+ /*not(x) = nor(x,x) */
+ case Iop_Not1: {
+ HReg r_dst = newVRegI(env);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg);
+ MIPSRH *r_srcR = MIPSRH_Reg(r_srcL);
+
+ addInstr(env, MIPSInstr_LI(r_dst, 0x1));
+ addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, r_dst, r_srcR));
+ return r_dst;
+ }
+
+ case Iop_Not32:
+ case Iop_Not64: {
+ HReg r_dst = newVRegI(env);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg);
+ MIPSRH *r_srcR = MIPSRH_Reg(r_srcL);
+
+ addInstr(env, MIPSInstr_Alu(Malu_NOR, r_dst, r_srcL, r_srcR));
+ return r_dst;
+ }
+
+ case Iop_ReinterpF32asI32: {
+ MIPSAMode *am_addr;
+ HReg fr_src = iselFltExpr(env, e->Iex.Unop.arg);
+ HReg r_dst = newVRegI(env);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as F32
+ addInstr(env, MIPSInstr_FpLdSt(False/*store */ , 4, fr_src,
+ am_addr));
+ // load as Ity_I32
+ addInstr(env, MIPSInstr_Load(4, r_dst, am_addr, mode64));
+
+ add_to_sp(env, 16); // Reset SP
+ return r_dst;
+ }
+
+ case Iop_ReinterpF64asI64: {
+ vassert(mode64);
+ MIPSAMode *am_addr;
+ HReg fr_src = iselFltExpr(env, e->Iex.Unop.arg);
+ HReg r_dst = newVRegI(env);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as F64
+ addInstr(env, MIPSInstr_FpLdSt(False/*store */ , 8, fr_src,
+ am_addr));
+ // load as Ity_I64
+ addInstr(env, MIPSInstr_Load(8, r_dst, am_addr, mode64));
+
+ add_to_sp(env, 16); // Reset SP
+ return r_dst;
+ }
+
+ case Iop_32to8:
+ case Iop_32to16:
+ return iselWordExpr_R(env, e->Iex.Unop.arg);
+
+ case Iop_64to8: {
+ vassert(mode64);
+ HReg r_src, r_dst;
+ r_dst = newVRegI(env);
+ r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_dst, r_src,
+ MIPSRH_Imm(False, 0xFF)));
+ return r_dst;
+ }
+
+ case Iop_16Uto32:
+ case Iop_8Uto32:
+ case Iop_1Uto32: {
+ HReg r_dst = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ UShort amt;
+ switch (op_unop) {
+ case Iop_1Uto32:
+ case Iop_1Uto8:
+ amt = 31;
+ break;
+
+ case Iop_16Uto32:
+ amt = 16;
+ break;
+
+ default:
+ amt = 24;
+ break;
+ }
+
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, r_dst, r_src,
+ MIPSRH_Imm(False, amt)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True, r_dst, r_dst,
+ MIPSRH_Imm(False, amt)));
+ return r_dst;
+ }
+
+ case Iop_8Uto16:
+ case Iop_8Uto64:
+ case Iop_16Uto64: {
+ vassert(mode64);
+ HReg r_dst = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ UShort mask = toUShort(op_unop == Iop_16Uto64 ? 0xFFFF :
+ op_unop == Iop_16Uto32 ? 0xFFFF : 0xFF);
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_dst, r_src,
+ MIPSRH_Imm(False, mask)));
+ return r_dst;
+ }
+
+ case Iop_32Uto64: {
+ HReg r_dst = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ vassert(mode64);
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, False/*!32bit shift */,
+ r_dst, r_src, MIPSRH_Imm(False, 32)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, False/*!32bit shift */,
+ r_dst, r_dst, MIPSRH_Imm(False, 32)));
+ return r_dst;
+ }
+
+ case Iop_1Uto64:
+ vassert(mode64);
+ return iselWordExpr_R(env, e->Iex.Unop.arg);
+
+ case Iop_64HIto32: {
+ HReg rHi, rLo;
+ iselInt64Expr(&rHi, &rLo, env, e->Iex.Unop.arg);
+ return rHi;
+ }
+
+ case Iop_64to32: {
+ HReg rHi, rLo;
+ iselInt64Expr(&rHi, &rLo, env, e->Iex.Unop.arg);
+ return rLo;
+ }
+
+ case Iop_64to16: {
+ vassert(env->mode64);
+ HReg r_dst = newVRegI(env);
+ r_dst = iselWordExpr_R(env, e->Iex.Unop.arg);
+ return r_dst;
+ }
+
+ case Iop_32Sto64: {
+ HReg r_dst = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ vassert(mode64);
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True/*!32bit shift */,
+ r_dst, r_src, MIPSRH_Imm(True, 0)));
+ return r_dst;
+ }
+
+ case Iop_CmpNEZ8: {
+ HReg r_dst = newVRegI(env);
+ HReg tmp = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+
+ MIPSCondCode cc;
+
+ cc = MIPScc_NE;
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tmp, r_src,
+ MIPSRH_Imm(False, 0xFF)));
+ addInstr(env, MIPSInstr_Cmp(False, True, r_dst, tmp,
+ hregMIPS_GPR0(mode64), cc));
+ return r_dst;
+ }
+
+ case Iop_CmpNEZ32: {
+ HReg r_dst = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+
+ MIPSCondCode cc;
+
+ cc = MIPScc_NE;
+
+ addInstr(env, MIPSInstr_Cmp(False, True, r_dst, r_src,
+ hregMIPS_GPR0(mode64), cc));
+ return r_dst;
+ }
+
+ case Iop_CmpwNEZ32: {
+ HReg r_dst = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+
+ addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, hregMIPS_GPR0(mode64),
+ MIPSRH_Reg(r_src)));
+
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, r_dst,
+ MIPSRH_Reg(r_src)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, r_dst, r_dst,
+ MIPSRH_Imm(False, 31)));
+ return r_dst;
+ }
+
+ case Iop_Left8:
+ case Iop_Left32:
+ case Iop_Left64: {
+ if (op_unop == Iop_Left64 && !mode64)
+ goto irreducible;
+ HReg r_dst = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, hregMIPS_GPR0(mode64),
+ MIPSRH_Reg(r_src)));
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, r_dst,
+ MIPSRH_Reg(r_src)));
+ return r_dst;
+ }
+
+ case Iop_Clz32: {
+ HReg r_dst = newVRegI(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, MIPSInstr_Unary(Mun_CLZ, r_dst, r_src));
+ return r_dst;
+ }
+
+ case Iop_CmpNEZ64: {
+ HReg hi, lo;
+ HReg r_dst = newVRegI(env);
+ HReg r_src;
+ r_src = newVRegI(env);
+ iselInt64Expr(&hi, &lo, env, e->Iex.Unop.arg);
+ addInstr(env, MIPSInstr_Alu(Malu_OR, r_src, lo, MIPSRH_Reg(hi)));
+ MIPSCondCode cc;
+
+ cc = MIPScc_NE;
+
+ addInstr(env, MIPSInstr_Cmp(False, !(env->mode64), r_dst, r_src,
+ hregMIPS_GPR0(mode64), cc));
+ return r_dst;
+ }
+
+ case Iop_CmpwNEZ64: {
+ HReg tmp1;
+ HReg tmp2 = newVRegI(env);
+ vassert(env->mode64);
+ tmp1 = iselWordExpr_R(env, e->Iex.Unop.arg);
+
+ addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, hregMIPS_GPR0(mode64),
+ MIPSRH_Reg(tmp1)));
+
+ addInstr(env, MIPSInstr_Alu(Malu_OR, tmp2, tmp2, MIPSRH_Reg(tmp1)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, False, tmp2, tmp2,
+ MIPSRH_Imm (False, 63)));
+ return tmp2;
+ }
+
+ case Iop_128HIto64: {
+ vassert(mode64);
+ HReg rHi, rLo;
+ iselInt128Expr(&rHi, &rLo, env, e->Iex.Unop.arg);
+ return rHi; /* and abandon rLo .. poor wee thing :-) */
+ }
+
+ case Iop_128to64: {
+ vassert(mode64);
+ HReg rHi, rLo;
+ iselInt128Expr(&rHi, &rLo, env, e->Iex.Unop.arg);
+ return rLo; /* and abandon rLo .. poor wee thing :-) */
+ }
+
+ default:
+ break;
+ }
+ break;
+ }
+
+ /* --------- GET --------- */
+ case Iex_Get: {
+ if (ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32
+ || ((ty == Ity_I64) && mode64)) {
+ HReg r_dst = newVRegI(env);
+
+ MIPSAMode *am_addr = MIPSAMode_IR(e->Iex.Get.offset,
+ GuestStatePointer(mode64));
+ addInstr(env, MIPSInstr_Load(toUChar(sizeofIRType(ty)), r_dst, am_addr,
+ mode64));
+ return r_dst;
+ }
+ break;
+ }
+
+ /* --------- MULTIPLEX --------- */
+ case Iex_Mux0X: {
+ if ((ty == Ity_I8 || ty == Ity_I16 ||
+ ty == Ity_I32 || ((ty == Ity_I64))) &&
+ typeOfIRExpr(env->type_env, e->Iex.Mux0X.cond) == Ity_I8) {
+ /*
+ * r_dst = cond && rX
+ * cond = not(cond)
+ * tmp = cond && r0
+ * r_dst = tmp + r_dst
+ */
+ HReg r0 = iselWordExpr_R(env, e->Iex.Mux0X.expr0);
+ HReg rX = iselWordExpr_R(env, e->Iex.Mux0X.exprX);
+ HReg r_cond = iselWordExpr_R(env, e->Iex.Mux0X.cond);
+ HReg r_dst = newVRegI(env);
+ HReg r_tmp = newVRegI(env);
+ HReg r_tmp1 = newVRegI(env);
+ HReg r_cond_neg = newVRegI(env);
+
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp, r_cond, MIPSRH_Reg(rX)));
+ addInstr(env, MIPSInstr_Alu(Malu_NOR, r_cond_neg, r_cond,
+ MIPSRH_Reg(r_cond)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp1, r_cond_neg,
+ MIPSRH_Reg(r0)));
+ addInstr(env, MIPSInstr_Alu(Malu_ADD, r_dst, r_tmp,
+ MIPSRH_Reg(r_tmp1)));
+
+ return r_dst;
+ }
+ break;
+ }
+
+ /* --------- LITERAL --------- */
+ /* 32/16/8-bit literals */
+ case Iex_Const: {
+ Long l;
+ HReg r_dst = newVRegI(env);
+ IRConst *con = e->Iex.Const.con;
+ switch (con->tag) {
+ case Ico_U64:
+ if (!mode64)
+ goto irreducible;
+ l = (Long) con->Ico.U64;
+ break;
+ case Ico_U32:
+ l = (Long) (Int) con->Ico.U32;
+ break;
+ case Ico_U16:
+ l = (Long) (Int) (Short) con->Ico.U16;
+ break;
+ case Ico_U8:
+ l = (Long) (Int) (Char) con->Ico.U8;
+ break;
+ default:
+ vpanic("iselIntExpr_R.const(mips)");
+ }
+ addInstr(env, MIPSInstr_LI(r_dst, (ULong) l));
+ return r_dst;
+ }
+
+ /* --------- CCALL --------- */
+ case Iex_CCall: {
+ HReg r_dst = newVRegI(env);
+ vassert(ty == e->Iex.CCall.retty);
+
+ /* be very restrictive for now. Only 32/64-bit ints allowed
+ for args, and 32 bits for return type. */
+ if (e->Iex.CCall.retty != Ity_I32 && !mode64)
+ goto irreducible;
+
+ /* Marshal args, do the call, clear stack. */
+ doHelperCall(env, False, NULL, e->Iex.CCall.cee, e->Iex.CCall.args);
+ addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
+ return r_dst;
+ }
+
+ default:
+ break;
+ } /* end switch(e->tag) */
+
+ /* We get here if no pattern matched. */
+ irreducible:
+ vex_printf("--------------->\n");
+ if (e->tag == Iex_RdTmp)
+ vex_printf("Iex_RdTmp \n");
+ ppIRExpr(e);
+
+ vpanic("iselWordExpr_R(mips): cannot reduce tree");
+}
+
+/* --------------------- RH --------------------- */
+
+/* Compute an I8/I16/I32 (and I64, in 64-bit mode) into a RH
+ (reg-or-halfword-immediate). It's important to specify whether the
+ immediate is to be regarded as signed or not. If yes, this will
+ never return -32768 as an immediate; this guaranteed that all
+ signed immediates that are return can have their sign inverted if
+ need be. */
+
+static MIPSRH *iselWordExpr_RH(ISelEnv * env, Bool syned, IRExpr * e)
+{
+ MIPSRH *ri = iselWordExpr_RH_wrk(env, syned, e);
+ /* sanity checks ... */
+ switch (ri->tag) {
+ case Mrh_Imm:
+ vassert(ri->Mrh.Imm.syned == syned);
+ if (syned)
+ vassert(ri->Mrh.Imm.imm16 != 0x8000);
+ return ri;
+ case Mrh_Reg:
+ vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64));
+ vassert(hregIsVirtual(ri->Mrh.Reg.reg));
+ return ri;
+ default:
+ vpanic("iselIntExpr_RH: unknown mips RH tag");
+ }
+}
+
+/* DO NOT CALL THIS DIRECTLY ! */
+static MIPSRH *iselWordExpr_RH_wrk(ISelEnv * env, Bool syned, IRExpr * e)
+{
+ ULong u;
+ Long l;
+ IRType ty = typeOfIRExpr(env->type_env, e);
+ vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 ||
+ ((ty == Ity_I64) && env->mode64));
+
+ /* special case: immediate */
+ if (e->tag == Iex_Const) {
+ IRConst *con = e->Iex.Const.con;
+ /* What value are we aiming to generate? */
+ switch (con->tag) {
+ /* Note: Not sign-extending - we carry 'syned' around */
+ case Ico_U64:
+ vassert(env->mode64);
+ u = con->Ico.U64;
+ break;
+ case Ico_U32:
+ u = 0xFFFFFFFF & con->Ico.U32;
+ break;
+ case Ico_U16:
+ u = 0x0000FFFF & con->Ico.U16;
+ break;
+ case Ico_U8:
+ u = 0x000000FF & con->Ico.U8;
+ break;
+ default:
+ vpanic("iselIntExpr_RH.Iex_Const(mips)");
+ }
+ l = (Long) u;
+ /* Now figure out if it's representable. */
+ if (!syned && u <= 65535) {
+ return MIPSRH_Imm(False /*unsigned */ , toUShort(u & 0xFFFF));
+ }
+ if (syned && l >= -32767 && l <= 32767) {
+ return MIPSRH_Imm(True /*signed */ , toUShort(u & 0xFFFF));
+ }
+ /* no luck; use the Slow Way. */
+ }
+ /* default case: calculate into a register and return that */
+ return MIPSRH_Reg(iselWordExpr_R(env, e));
+}
+
+/* --------------------- RH5u --------------------- */
+
+/* Compute an I8 into a reg-or-5-bit-unsigned-immediate, the latter
+ being an immediate in the range 1 .. 31 inclusive. Used for doing
+ shift amounts. */
+
+static MIPSRH *iselWordExpr_RH5u(ISelEnv * env, IRExpr * e)
+{
+ MIPSRH *ri;
+ ri = iselWordExpr_RH5u_wrk(env, e);
+ /* sanity checks ... */
+ switch (ri->tag) {
+ case Mrh_Imm:
+ vassert(ri->Mrh.Imm.imm16 >= 1 && ri->Mrh.Imm.imm16 <= 31);
+ vassert(!ri->Mrh.Imm.syned);
+ return ri;
+ case Mrh_Reg:
+ vassert(hregClass(ri->Mrh.Reg.reg) == HRcInt32);
+ vassert(hregIsVirtual(ri->Mrh.Reg.reg));
+ return ri;
+ default:
+ vpanic("iselIntExpr_RH5u: unknown mips RH tag");
+ }
+}
+
+/* DO NOT CALL THIS DIRECTLY ! */
+static MIPSRH *iselWordExpr_RH5u_wrk(ISelEnv * env, IRExpr * e)
+{
+ IRType ty = typeOfIRExpr(env->type_env, e);
+ vassert(ty == Ity_I8);
+
+ /* special case: immediate */
+ if (e->tag == Iex_Const
+ && e->Iex.Const.con->tag == Ico_U8
+ && e->Iex.Const.con->Ico.U8 >= 1 && e->Iex.Const.con->Ico.U8 <= 31) {
+ return MIPSRH_Imm(False /*unsigned */ , e->Iex.Const.con->Ico.U8);
+ }
+
+ /* default case: calculate into a register and return that */
+ return MIPSRH_Reg(iselWordExpr_R(env, e));
+}
+
+/* --------------------- CONDCODE --------------------- */
+
+/* Generate code to evaluated a bit-typed expression, returning the
+ condition code which would correspond when the expression would
+ notionally have returned 1. */
+
+static MIPSCondCode iselCondCode(ISelEnv * env, IRExpr * e)
+{
+ MIPSCondCode cc = iselCondCode_wrk(env,e);
+ vassert(cc != MIPScc_NV);
+ return cc;
+}
+
+/* DO NOT CALL THIS DIRECTLY ! */
+static MIPSCondCode iselCondCode_wrk(ISelEnv * env, IRExpr * e)
+{
+ vassert(e);
+ vassert(typeOfIRExpr(env->type_env, e) == Ity_I1);
+ /* Cmp*32*(x,y) ? */
+ if (e->Iex.Binop.op == Iop_CmpEQ32
+ || e->Iex.Binop.op == Iop_CmpNE32
+ || e->Iex.Binop.op == Iop_CmpNE64
+ || e->Iex.Binop.op == Iop_CmpLT32S
+ || e->Iex.Binop.op == Iop_CmpLT32U
+ || e->Iex.Binop.op == Iop_CmpLT64U
+ || e->Iex.Binop.op == Iop_CmpLE32S
+ || e->Iex.Binop.op == Iop_CmpLE64S
+ || e->Iex.Binop.op == Iop_CmpLT64S
+ || e->Iex.Binop.op == Iop_CmpEQ64) {
+
+ Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S
+ || e->Iex.Binop.op == Iop_CmpLE32S
+ || e->Iex.Binop.op == Iop_CmpLT64S
+ || e->Iex.Binop.op == Iop_CmpLE64S);
+ Bool size32;
+ HReg dst = newVRegI(env);
+ HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2);
+
+ MIPSCondCode cc;
+
+ switch (e->Iex.Binop.op) {
+ case Iop_CmpEQ32:
+ cc = MIPScc_EQ;
+ size32 = True;
+ break;
+ case Iop_CmpNE32:
+ cc = MIPScc_NE;
+ size32 = True;
+ break;
+ case Iop_CmpNE64:
+ cc = MIPScc_NE;
+ size32 = True;
+ break;
+ case Iop_CmpLT32S:
+ cc = MIPScc_LT;
+ size32 = True;
+ break;
+ case Iop_CmpLT32U:
+ cc = MIPScc_LO;
+ size32 = True;
+ break;
+ case Iop_CmpLT64U:
+ cc = MIPScc_LO;
+ size32 = False;
+ break;
+ case Iop_CmpLE32S:
+ cc = MIPScc_LE;
+ size32 = True;
+ break;
+ case Iop_CmpLE64S:
+ cc = MIPScc_LE;
+ size32 = False;
+ break;
+ case Iop_CmpLT64S:
+ cc = MIPScc_LT;
+ size32 = False;
+ break;
+ case Iop_CmpEQ64:
+ cc = MIPScc_EQ;
+ size32 = False;
+ break;
+ default:
+ vpanic
+ ("iselCondCode(mips): CmpXX32 or CmpXX64");
+ }
+
+ addInstr(env, MIPSInstr_Cmp(syned, size32, dst, r1, r2, cc));
+ // Store result to guest_COND
+ MIPSAMode *am_addr = MIPSAMode_IR(0, GuestStatePointer(mode64));
+
+ addInstr(env, MIPSInstr_Store(4,
+ MIPSAMode_IR(am_addr->Mam.IR.index + 316, am_addr->Mam.IR.base),
+ dst, mode64));
+ return cc;
+ }
+ if (e->Iex.Binop.op == Iop_Not1) {
+ HReg r_dst = newVRegI(env);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg);
+ MIPSRH *r_srcR = MIPSRH_Reg(r_srcL);
+
+ addInstr(env, MIPSInstr_LI(r_dst, 0x1));
+ addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, r_dst, r_srcR));
+ // Store result to guest_COND
+ MIPSAMode *am_addr = MIPSAMode_IR(0, GuestStatePointer(mode64));
+
+ addInstr(env, MIPSInstr_Store(4,
+ MIPSAMode_IR(am_addr->Mam.IR.index + 316, am_addr->Mam.IR.base),
+ r_dst, mode64));
+ return MIPScc_NE;
+ }
+ if (e->tag == Iex_RdTmp || e->tag == Iex_Unop) {
+ HReg r_dst = iselWordExpr_R_wrk(env, e);
+ // Store result to guest_COND
+ MIPSAMode *am_addr = MIPSAMode_IR(0, GuestStatePointer(mode64));
+
+ addInstr(env, MIPSInstr_Store(4,
+ MIPSAMode_IR(am_addr->Mam.IR.index + 316, am_addr->Mam.IR.base),
+ r_dst, mode64));
+ return MIPScc_EQ;
+ }
+
+ vex_printf("iselCondCode(mips): No such tag(%u)\n", e->tag);
+ ppIRExpr(e);
+ vpanic("iselCondCode(mips)");
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Integer expressions (128 bit) ---*/
+/*---------------------------------------------------------*/
+
+/* 64-bit mode ONLY: compute a 128-bit value into a register pair,
+ which is returned as the first two parameters. As with
+ iselWordExpr_R, these may be either real or virtual regs; in any
+ case they must not be changed by subsequent code emitted by the
+ caller. */
+
+static void iselInt128Expr(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e)
+{
+ vassert(env->mode64);
+ iselInt128Expr_wrk(rHi, rLo, env, e);
+# if 0
+ vex_printf("\n");
+ ppIRExpr(e);
+ vex_printf("\n");
+# endif
+ vassert(hregClass(*rHi) == HRcGPR(env->mode64));
+ vassert(hregIsVirtual(*rHi));
+ vassert(hregClass(*rLo) == HRcGPR(env->mode64));
+ vassert(hregIsVirtual(*rLo));
+}
+
+/* DO NOT CALL THIS DIRECTLY ! */
+static void iselInt128Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env,
+ IRExpr * e)
+{
+ vassert(e);
+ vassert(typeOfIRExpr(env->type_env, e) == Ity_I128);
+
+ /* read 128-bit IRTemp */
+ if (e->tag == Iex_RdTmp) {
+ lookupIRTempPair(rHi, rLo, env, e->Iex.RdTmp.tmp);
+ return;
+ }
+
+ /* --------- BINARY ops --------- */
+ if (e->tag == Iex_Binop) {
+ switch (e->Iex.Binop.op) {
+ /* 64 x 64 -> 128 multiply */
+ case Iop_MullU64:
+ case Iop_MullS64:
+ {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64);
+ HReg r_dst = newVRegI(env);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ addInstr(env, MIPSInstr_Mul(syned, True, False /*64bit mul */ ,
+ r_dst, r_srcL, r_srcR));
+ addInstr(env, MIPSInstr_Mfhi(tHi));
+ addInstr(env, MIPSInstr_Mflo(tLo));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ /* 64HLto128(e1,e2) */
+ case Iop_64HLto128:
+ *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ return;
+
+ case Iop_DivModS64to64: {
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ Bool syned = toBool(e->Iex.Binop.op == Iop_DivModS64to64);
+
+ addInstr(env, MIPSInstr_Div(syned, False, r_srcL, r_srcR));
+ addInstr(env, MIPSInstr_Mfhi(tHi));
+ addInstr(env, MIPSInstr_Mflo(tLo));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ case Iop_DivModU128to64: {
+ vassert(mode64);
+ HReg rHi1, rLo1;
+ iselInt128Expr(&rHi1, &rLo1, env, e->Iex.Binop.arg1);
+
+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ Bool syned = toBool(e->Iex.Binop.op == Iop_DivModS128to64);
+
+ addInstr(env, MIPSInstr_Div(syned, False, rLo1, r_srcR));
+ addInstr(env, MIPSInstr_Mfhi(tHi));
+ addInstr(env, MIPSInstr_Mflo(tLo));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ default:
+ break;
+ }
+ }
+ vex_printf("iselInt128Expr(mips64): No such tag(%u)\n", e->tag);
+ ppIRExpr(e);
+ vpanic("iselInt128Expr(mips64)");
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Integer expressions (64 bit) ---*/
+/*---------------------------------------------------------*/
+
+/* 32-bit mode ONLY. Compute a 64-bit value into the register
+ * pair HI, LO. HI and LO must not be changed by subsequent
+ * code emitted by the caller. */
+
+static void iselInt64Expr(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e)
+{
+ vassert(!env->mode64);
+ iselInt64Expr_wrk(rHi, rLo, env, e);
+ vassert(hregClass(*rHi) == HRcInt32);
+ vassert(hregIsVirtual(*rHi));
+ vassert(hregClass(*rLo) == HRcInt32);
+ vassert(hregIsVirtual(*rLo));
+}
+
+/* DO NOT CALL THIS DIRECTLY ! */
+static void iselInt64Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e)
+{
+ vassert(e);
+ vassert(typeOfIRExpr(env->type_env, e) == Ity_I64);
+
+ /* read 64-bit IRTemp */
+ if (e->tag == Iex_RdTmp) {
+ lookupIRTemp64(rHi, rLo, env, e->Iex.RdTmp.tmp);
+ return;
+ }
+ /* 64-bit load */
+ if (e->tag == Iex_Load) {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg r_addr = iselWordExpr_R(env, e->Iex.Load.addr);
+ addInstr(env, MIPSInstr_Load(4, tHi, MIPSAMode_IR(0, r_addr), mode64));
+ addInstr(env, MIPSInstr_Load(4, tLo, MIPSAMode_IR(4, r_addr), mode64));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ /* 64-bit literal */
+ if (e->tag == Iex_Const) {
+ ULong w64 = e->Iex.Const.con->Ico.U64;
+ UInt wHi = toUInt(w64 >> 32);
+ UInt wLo = toUInt(w64);
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ vassert(e->Iex.Const.con->tag == Ico_U64);
+
+ if (wLo == wHi) {
+ /* Save a precious Int register in this special case. */
+ addInstr(env, MIPSInstr_LI(tLo, (ULong) wLo));
+ *rHi = tLo;
+ *rLo = tLo;
+ } else {
+ addInstr(env, MIPSInstr_LI(tHi, (ULong) wHi));
+ addInstr(env, MIPSInstr_LI(tLo, (ULong) wLo));
+ *rHi = tHi;
+ *rLo = tLo;
+ }
+
+ return;
+ }
+
+ /* 64-bit GET */
+ if (e->tag == Iex_Get) {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+
+ MIPSAMode *am_addr = MIPSAMode_IR(e->Iex.Get.offset,
+ GuestStatePointer(mode64));
+ addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
+ addInstr(env, MIPSInstr_Load(4, tHi, nextMIPSAModeInt(am_addr), mode64));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ /* 64-bit Mux0X */
+ if (e->tag == Iex_Mux0X) {
+ HReg expr0Lo, expr0Hi;
+ HReg exprXLo, exprXHi;
+ HReg tmpHi = newVRegI(env);
+ HReg tmpLo = newVRegI(env);
+ HReg tmp1Hi = newVRegI(env);
+ HReg tmp1Lo = newVRegI(env);
+ HReg r_cond = iselWordExpr_R(env, e->Iex.Mux0X.cond);
+ HReg r_cond_neg = newVRegI(env);
+ HReg desLo = newVRegI(env);
+ HReg desHi = newVRegI(env);
+
+ /* expr0Hi:expr0Lo = expr0 */
+ /* exprXHi:exprXLo = exprX */
+ iselInt64Expr(&expr0Hi, &expr0Lo, env, e->Iex.Mux0X.expr0);
+ iselInt64Expr(&exprXHi, &exprXLo, env, e->Iex.Mux0X.exprX);
+
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tmpLo, r_cond,
+ MIPSRH_Reg(exprXLo)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tmpHi, r_cond,
+ MIPSRH_Reg(exprXHi)));
+ addInstr(env, MIPSInstr_Alu(Malu_NOR, r_cond_neg, r_cond,
+ MIPSRH_Reg(r_cond)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tmp1Lo, r_cond_neg,
+ MIPSRH_Reg(exprXLo)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, tmp1Hi, r_cond_neg,
+ MIPSRH_Reg(exprXHi)));
+ addInstr(env, MIPSInstr_Alu(Malu_ADD, desLo, tmpLo,
+ MIPSRH_Reg(tmp1Lo)));
+ addInstr(env, MIPSInstr_Alu(Malu_ADD, desHi, tmpHi,
+ MIPSRH_Reg(tmp1Hi)));
+ *rHi = desHi;
+ *rLo = desLo;
+ return;
+ }
+
+ /* --------- BINARY ops --------- */
+ if (e->tag == Iex_Binop) {
+ IROp op_binop = e->Iex.Binop.op;
+ switch (op_binop) {
+ /* 32 x 32 -> 64 multiply */
+ /* Add64 */
+ case Iop_Add64: {
+ HReg xLo, xHi, yLo, yHi;
+ HReg tHi = newVRegI(env);
+ HReg tLo = newVRegI(env);
+ iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
+ iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
+ addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, xHi, MIPSRH_Reg(yHi)));
+ addInstr(env, MIPSInstr_Alu(Malu_ADD, tLo, xLo, MIPSRH_Reg(yLo)));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+ case Iop_MullU32:
+ case Iop_MullS32: {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg r_dst = newVRegI(env);
+ Bool syned = toBool(op_binop == Iop_MullS32);
+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
+
+ addInstr(env, MIPSInstr_Mul(syned/*Unsigned or Signed */ ,
+ True /*widen */ , True,
+ r_dst, r_srcL, r_srcR));
+ addInstr(env, MIPSInstr_Mfhi(tHi));
+ addInstr(env, MIPSInstr_Mflo(tLo));
+ *rHi = tHi;
+ *rLo = tLo;
+
+ return;
+ }
+ case Iop_DivModS64to32:
+ case Iop_DivModU64to32: {
+ HReg r_sHi, r_sLo;
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ Bool syned = toBool(op_binop == Iop_DivModS64to32);
+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
+
+ iselInt64Expr(&r_sHi, &r_sLo, env, e->Iex.Binop.arg1);
+ addInstr(env, MIPSInstr_Div(syned, True, r_sLo, r_srcR));
+ addInstr(env, MIPSInstr_Mfhi(tHi));
+ addInstr(env, MIPSInstr_Mflo(tLo));
+ *rHi = tHi;
+ *rLo = tLo;
+
+ return;
+ }
+
+ /* 32HLto64(e1,e2) */
+ case Iop_32HLto64:
+ *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
+
+ return;
+ /* Or64/And64/Xor64 */
+ case Iop_Or64:
+ case Iop_And64:
+ case Iop_Xor64: {
+ HReg xLo, xHi, yLo, yHi;
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ MIPSAluOp op = (op_binop == Iop_Or64) ? Malu_OR :
+ (op_binop == Iop_And64) ? Malu_AND : Malu_XOR;
+ iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
+ iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
+ addInstr(env, MIPSInstr_Alu(op, tHi, xHi, MIPSRH_Reg(yHi)));
+ addInstr(env, MIPSInstr_Alu(op, tLo, xLo, MIPSRH_Reg(yLo)));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ default:
+ break;
+ }
+ }
+
+ /* --------- UNARY ops --------- */
+ if (e->tag == Iex_Unop) {
+
+ switch (e->Iex.Unop.op) {
+ case Iop_1Sto64: {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ HReg tmp = newVRegI(env);
+
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, src,
+ MIPSRH_Imm(False, 31)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp, src,
+ MIPSRH_Imm(False, 31)));
+
+ addInstr(env, mk_iMOVds_RR(tHi, tmp));
+ addInstr(env, mk_iMOVds_RR(tLo, tmp));
+
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ /* 32Sto64(e) */
+ case Iop_32Sto64: {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, mk_iMOVds_RR(tHi, src));
+ addInstr(env, mk_iMOVds_RR(tLo, src));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tHi, tHi,
+ MIPSRH_Imm(False, 31)));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ /* 32Uto64(e) */
+ case Iop_32Uto64: {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, mk_iMOVds_RR(tLo, src));
+ addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, hregMIPS_GPR0(mode64),
+ MIPSRH_Reg(hregMIPS_GPR0(mode64))));
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ case Iop_CmpwNEZ64: {
+ HReg srcLo, srcHi;
+ HReg tmp1 = newVRegI(env);
+ HReg tmp2 = newVRegI(env);
+ /* srcHi:srcLo = arg */
+ iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
+ /* tmp1 = srcHi | srcLo */
+ addInstr(env, MIPSInstr_Alu(Malu_OR, tmp1, srcLo,
+ MIPSRH_Reg(srcHi)));
+ /* tmp2 = (tmp1 | -tmp1) >>s 31 */
+
+ addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, hregMIPS_GPR0(mode64),
+ MIPSRH_Reg(tmp1)));
+
+ addInstr(env, MIPSInstr_Alu(Malu_OR, tmp2, tmp2, MIPSRH_Reg(tmp1)));
+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp2, tmp2,
+ MIPSRH_Imm(False, 31)));
+ *rHi = tmp2;
+ *rLo = tmp2;
+ return;
+
+ }
+ case Iop_ReinterpF64asI64: {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ MIPSAMode *am_addr;
+ HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as F64
+ addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, fr_src,
+ am_addr));
+ // load as 2xI32
+ addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
+ addInstr(env, MIPSInstr_Load(4, tHi, nextMIPSAModeFloat(am_addr),
+ mode64));
+
+ add_to_sp(env, 16); // Reset SP
+
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ default:
+ vex_printf("UNARY: No such op: ");
+ ppIROp(e->Iex.Unop.op);
+ vex_printf("\n");
+ break;
+ }
+ }
+
+ vex_printf("iselInt64Expr(mips): No such tag(%u)\n", e->tag);
+ ppIRExpr(e);
+ vpanic("iselInt64Expr(mips)");
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Floating point expressions (32 bit) ---*/
+/*---------------------------------------------------------*/
+
+/* Nothing interesting here; really just wrappers for
+ 64-bit stuff. */
+
+static HReg iselFltExpr(ISelEnv * env, IRExpr * e)
+{
+ HReg r = iselFltExpr_wrk(env, e);
+ vassert(hregIsVirtual(r));
+ return r;
+}
+
+/* DO NOT CALL THIS DIRECTLY */
+static HReg iselFltExpr_wrk(ISelEnv * env, IRExpr * e)
+{
+ IRType ty = typeOfIRExpr(env->type_env, e);
+ vassert(ty == Ity_F32 || (ty == Ity_F64 && mode64));
+
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
+ }
+
+ if (e->tag == Iex_Load) {
+ MIPSAMode *am_addr;
+ HReg r_dst = newVRegF(env);
+ vassert(e->Iex.Load.ty == Ity_F32
+ || (e->Iex.Load.ty == Ity_F64 && mode64));
+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty);
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 4, r_dst, am_addr));
+ return r_dst;
+ }
+
+ if (e->tag == Iex_Get) {
+ HReg r_dst = newVRegF(env);
+ MIPSAMode *am_addr = MIPSAMode_IR(e->Iex.Get.offset,
+ GuestStatePointer(mode64));
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 4, r_dst, am_addr));
+ return r_dst;
+ }
+
+ if (e->tag == Iex_Unop) {
+ switch (e->Iex.Unop.op) {
+ case Iop_ReinterpI32asF32: {
+ MIPSAMode *am_addr;
+ HReg fr_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ HReg r_dst = newVRegF(env);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as I32
+ addInstr(env, MIPSInstr_Store(4, am_addr, fr_src, mode64));
+
+ // load as Ity_F32
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 4, r_dst, am_addr));
+
+ add_to_sp(env, 16); // Reset SP
+ return r_dst;
+
+ }
+ case Iop_F32toF64: {
+ /* first arg is rounding mode; we ignore it. */
+ MIPSAMode *am_addr;
+ HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+ HReg dst = newVRegF(env);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ addInstr(env, MIPSInstr_Store(4,
+ MIPSAMode_IR(am_addr->Mam.IR.index + 4,
+ am_addr->Mam.IR.base),
+ hregMIPS_GPR0(mode64), mode64));
+ addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 4, src, am_addr));
+
+ // load as Ity_F32
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 8, dst, am_addr));
+ add_to_sp(env, 16); // Reset SP
+
+ return dst;
+ }
+ case Iop_ReinterpI64asF64:
+ {
+ vassert(mode64);
+ MIPSAMode *am_addr;
+ HReg fr_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ HReg r_dst = newVRegF(env);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as I32
+ addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64));
+
+ // load as Ity_F32
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 8, r_dst, am_addr));
+
+ add_to_sp(env, 16); // Reset SP
+ return r_dst;
+ }
+ case Iop_AbsF32:
+ case Iop_AbsF64: {
+ Bool sz32 = e->Iex.Unop.op == Iop_AbsF32;
+ HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+ HReg dst = newVRegF(env);
+ addInstr(env, MIPSInstr_FpUnary(sz32 ? Mfp_ABSS : Mfp_ABSD, dst, src));
+ return dst;
+ }
+ case Iop_NegF32:
+ case Iop_NegF64: {
+ Bool sz32 = e->Iex.Unop.op == Iop_NegF32;
+ HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+ HReg dst = newVRegF(env);
+ addInstr(env, MIPSInstr_FpUnary(sz32 ? Mfp_NEGS : Mfp_NEGD, dst, src));
+ return dst;
+ }
+ default:
+ break;
+ }
+ }
+
+ if (e->tag == Iex_Triop) {
+ switch (e->Iex.Triop.details->op) {
+ case Iop_DivF32:
+ case Iop_DivF64:
+ case Iop_MulF32:
+ case Iop_MulF64:
+ case Iop_AddF32:
+ case Iop_AddF64:
+ case Iop_SubF32:
+ case Iop_SubF64: {
+ MIPSFpOp op = 0;
+ /*INVALID*/ HReg argL = iselFltExpr(env, e->Iex.Triop.details->arg2);
+ HReg argR = iselFltExpr(env, e->Iex.Triop.details->arg3);
+ HReg dst = newVRegF(env);
+ switch (e->Iex.Triop.details->op) {
+ case Iop_DivF32:
+ op = Mfp_DIVS;
+ break;
+ case Iop_MulF32:
+ op = Mfp_MULS;
+ break;
+ case Iop_AddF32:
+ op = Mfp_ADDS;
+ break;
+ case Iop_SubF32:
+ op = Mfp_SUBS;
+ break;
+ default:
+ vassert(0);
+ }
+ addInstr(env, MIPSInstr_FpBinary(op, dst, argL, argR));
+ return dst;
+ }
+ default:
+ break;
+ }
+ }
+
+ if (e->tag == Iex_Binop) {
+ switch (e->Iex.Binop.op) {
+ case Iop_F64toF32: {
+ HReg valD = iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg valS = newVRegF(env);
+
+ set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, MIPSInstr_FpConvert(Mfp_CVTSD, valS, valD));
+ set_MIPS_rounding_default(env);
+ return valS;
+ }
+
+ case Iop_RoundF32toInt: {
+ HReg valS = newVRegF(env);
+ HReg valF = iselFltExpr(env, e->Iex.Binop.arg2);
+
+ set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, MIPSInstr_FpConvert(Mfp_CVTWS, valS, valF));
+
+ set_MIPS_rounding_default(env);
+ return valS;
+ }
+
+ case Iop_I32StoF32: {
+ HReg r_dst = newVRegF(env);
+
+ MIPSAMode *am_addr;
+ HReg fr_src = iselWordExpr_R(env, e->Iex.Binop.arg2);
+ HReg tmp = newVRegF(env);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as I32
+ addInstr(env, MIPSInstr_Store(4, am_addr, fr_src, mode64));
+
+ // load as Ity_F32
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 4, tmp, am_addr));
+
+ add_to_sp(env, 16); // Reset SP
+
+ set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, MIPSInstr_FpConvert(Mfp_CVTSW, r_dst, tmp));
+ set_MIPS_rounding_default(env);
+
+ return r_dst;
+ }
+
+ case Iop_SqrtF32:
+ case Iop_SqrtF64: {
+ /* first arg is rounding mode; we ignore it. */
+ Bool sz32 = e->Iex.Binop.op == Iop_SqrtF32;
+ HReg src = iselFltExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegF(env);
+ set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, MIPSInstr_FpUnary(sz32 ? Mfp_SQRTS : Mfp_SQRTD, dst,
+ src));
+ set_MIPS_rounding_default(env);
+ return dst;
+ }
+
+ default:
+ break;
+ }
+ }
+
+ if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_TruncF64asF32) {
+ /* This is quite subtle. The only way to do the relevant
+ truncation is to do a single-precision store and then a
+ double precision load to get it back into a register. The
+ problem is, if the data is then written to memory a second
+ time, as in
+
+ STbe(...) = TruncF64asF32(...)
+
+ then will the second truncation further alter the value? The
+ answer is no: flds (as generated here) followed by fsts
+ (generated for the STbe) is the identity function on 32-bit
+ floats, so we are safe.
+
+ Another upshot of this is that if iselStmt can see the
+ entirety of
+
+ STbe(...) = TruncF64asF32(arg)
+
+ then it can short circuit having to deal with TruncF64asF32
+ individually; instead just compute arg into a 64-bit FP
+ register and do 'fsts' (since that itself does the
+ truncation).
+
+ We generate pretty poor code here (should be ok both for
+ 32-bit and 64-bit mode); but it is expected that for the most
+ part the latter optimisation will apply and hence this code
+ will not often be used.
+ */
+ HReg fsrc = iselDblExpr(env, e->Iex.Unop.arg);
+ HReg fdst = newVRegF(env);
+ MIPSAMode *zero_r1 = MIPSAMode_IR(0, StackPointer(mode64));
+
+ sub_from_sp(env, 16);
+ // store as F32, hence truncating
+ addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 4, fsrc, zero_r1));
+ // and reload. Good huh?! (sigh)
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 4, fdst, zero_r1));
+ add_to_sp(env, 16);
+ return fdst;
+ }
+
+ vex_printf("iselFltExpr(mips): No such tag(0x%x)\n", e->tag);
+ ppIRExpr(e);
+ vpanic("iselFltExpr_wrk(mips)");
+}
+
+static HReg iselDblExpr(ISelEnv * env, IRExpr * e)
+{
+ HReg r = iselDblExpr_wrk(env, e);
+ vassert(hregClass(r) == HRcFlt64);
+ vassert(hregIsVirtual(r));
+ return r;
+}
+
+/* DO NOT CALL THIS DIRECTLY */
+static HReg iselDblExpr_wrk(ISelEnv * env, IRExpr * e)
+{
+ IRType ty = typeOfIRExpr(env->type_env, e);
+ vassert(e);
+ vassert(ty == Ity_F64);
+
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
+ }
+
+ /* --------- LOAD --------- */
+ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
+ HReg r_dst = newVRegD(env);
+ MIPSAMode *am_addr;
+ vassert(e->Iex.Load.ty == Ity_F64);
+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty);
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 8, r_dst, am_addr));
+ return r_dst;
+ }
+
+ /* --------- GET --------- */
+ if (e->tag == Iex_Get) {
+
+ HReg r_dst = newVRegD(env);
+ MIPSAMode *am_addr = MIPSAMode_IR(e->Iex.Get.offset,
+ GuestStatePointer(mode64));
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 8, r_dst, am_addr));
+ return r_dst;
+ }
+
+ if (e->tag == Iex_Unop) {
+ MIPSFpOp fpop = Mfp_INVALID;
+ switch (e->Iex.Unop.op) {
+ case Iop_NegF64:
+ fpop = Mfp_NEGD;
+ break;
+ case Iop_AbsF64:
+ fpop = Mfp_ABSD;
+ break;
+ case Iop_F32toF64: {
+ HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+ HReg dst = newVRegD(env);
+
+ HReg irrm = newVRegI(env);
+
+ MIPSAMode *am_addr1 = MIPSAMode_IR(284, GuestStatePointer(mode64));
+
+ addInstr(env, MIPSInstr_Load(4, irrm, am_addr1, mode64));
+
+ // set new FCSR
+ HReg tmp = newVRegI(env);
+ HReg fcsr_old = newVRegI(env);
+ MIPSAMode *am_addr;
+
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, irrm,
+ MIPSRH_Imm(False, 1)));
+ addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp,
+ MIPSRH_Imm(False, 3)));
+ /* save old value of FCSR */
+ addInstr(env, MIPSInstr_MfFCSR(fcsr_old));
+ sub_from_sp(env, 8); // Move SP down 4 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ //store old FCSR to stack
+ addInstr(env, MIPSInstr_Store(4, am_addr, fcsr_old, mode64));
+
+ //set new value of FCSR
+ addInstr(env, MIPSInstr_MtFCSR(irrm));
+
+ //set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, MIPSInstr_FpUnary(Mfp_CVTD, dst, src));
+ set_MIPS_rounding_default(env);
+ return dst;
+ }
+ case Iop_ReinterpI64asF64: {
+ HReg Hi;
+ HReg Lo;
+ HReg dst = newVRegD(env);
+
+ iselInt64Expr(&Hi, &Lo, env, e->Iex.Unop.arg);
+
+ dst = mk_LoadRR32toFPR(env, Hi, Lo); // 2*I32 -> F64
+ return dst;
+ }
+ case Iop_I32StoF64: {
+ HReg dst = newVRegD(env);
+ HReg tmp1 = newVRegF(env);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ MIPSAMode *am_addr;
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as I32
+ addInstr(env, MIPSInstr_Store(4, am_addr, r_src, mode64));
+
+ // load as Ity_F32
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 4, tmp1, am_addr));
+
+ add_to_sp(env, 16); // Reset SP
+
+ HReg irrm = newVRegI(env);
+
+ MIPSAMode *am_addr1 = MIPSAMode_IR(284, GuestStatePointer(mode64));
+
+ addInstr(env, MIPSInstr_Load(4, irrm, am_addr1, mode64));
+
+ //set rounding mode
+ HReg tmp = newVRegI(env);
+ HReg fcsr_old = newVRegI(env);
+
+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, irrm,
+ MIPSRH_Imm(False, 1)));
+ addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp,
+ MIPSRH_Imm(False, 3)));
+ /* save old value of FCSR */
+ addInstr(env, MIPSInstr_MfFCSR(fcsr_old));
+ sub_from_sp(env, 8); // Move SP down 4 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ //store old FCSR to stack
+ addInstr(env, MIPSInstr_Store(4, am_addr, fcsr_old, mode64));
+
+ //set new value of FCSR
+ addInstr(env, MIPSInstr_MtFCSR(irrm));
+
+ // and do convert
+ addInstr(env, MIPSInstr_FpConvert(Mfp_CVTDW, dst, tmp1));
+ set_MIPS_rounding_default(env);
+
+ return dst;
+ }
+ default:
+ break;
+ }
+
+ if (fpop != Mfp_INVALID) {
+ HReg src = iselDblExpr(env, e->Iex.Unop.arg);
+ HReg dst = newVRegD(env);
+ addInstr(env, MIPSInstr_FpUnary(fpop, dst, src));
+ return dst;
+ }
+ }
+
+ if (e->tag == Iex_Binop) {
+ switch (e->Iex.Binop.op) {
+ case Iop_RoundF64toInt: {
+ HReg valD = iselDblExpr(env, e->Iex.Binop.arg2);
+ MIPSRH *fmt = iselWordExpr_RH(env, False, e->Iex.Binop.arg1);
+ HReg valD1 = newVRegD(env);
+
+ if (fmt->Mrh.Imm.imm16 == 0x3)
+ addInstr(env, MIPSInstr_FpConvert(Mfp_TRULD, valD1, valD));
+ else if (fmt->Mrh.Imm.imm16 == 0x2)
+ addInstr(env, MIPSInstr_FpConvert(Mfp_CEILLD, valD1, valD));
+ else
+ vassert(0);
+ return valD1;
+ }
+
+ case Iop_SqrtF64:{
+ /* first arg is rounding mode; we ignore it. */
+ HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegD(env);
+ addInstr(env, MIPSInstr_FpUnary(Mfp_SQRTD, dst, src));
+ return dst;
+ }
+
+ default:
+ break;
+
+ }
+ }
+
+ if (e->tag == Iex_Triop) {
+ switch (e->Iex.Triop.details->op) {
+ case Iop_DivF64:
+ case Iop_DivF32:
+ case Iop_MulF64:
+ case Iop_AddF64:
+ case Iop_SubF64: {
+ MIPSFpOp op = 0;
+ /*INVALID*/ HReg argL = iselDblExpr(env, e->Iex.Triop.details->arg2);
+ HReg argR = iselDblExpr(env, e->Iex.Triop.details->arg3);
+ HReg dst = newVRegD(env);
+ switch (e->Iex.Triop.details->op) {
+ case Iop_DivF64:
+ op = Mfp_DIVD;
+ break;
+ case Iop_MulF64:
+ op = Mfp_MULD;
+ break;
+ case Iop_AddF64:
+ op = Mfp_ADDD;
+ break;
+ case Iop_SubF64:
+ op = Mfp_SUBD;
+ break;
+ default:
+ vassert(0);
+ }
+ addInstr(env, MIPSInstr_FpBinary(op, dst, argL, argR));
+ return dst;
+ }
+ default:
+ break;
+ }
+ }
+
+ /* --------- MULTIPLEX --------- */
+ if (e->tag == Iex_Mux0X) {
+ if (ty == Ity_F64
+ && typeOfIRExpr(env->type_env, e->Iex.Mux0X.cond) == Ity_I8) {
+ HReg r0 = iselDblExpr(env, e->Iex.Mux0X.expr0);
+ HReg rX = iselDblExpr(env, e->Iex.Mux0X.exprX);
+ HReg r_cond = iselWordExpr_R(env, e->Iex.Mux0X.cond);
+ HReg r_cond_neg = newVRegI(env);
+ HReg r_dst = newVRegD(env);
+ HReg r_tmp_lo = newVRegI(env);
+ HReg r_tmp_hi = newVRegI(env);
+ HReg r_tmp1_lo = newVRegI(env);
+ HReg r_tmp1_hi = newVRegI(env);
+ HReg r_r0_lo = newVRegI(env);
+ HReg r_r0_hi = newVRegI(env);
+ HReg r_rX_lo = newVRegI(env);
+ HReg r_rX_hi = newVRegI(env);
+ HReg r_dst_lo = newVRegI(env);
+ HReg r_dst_hi = newVRegI(env);
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ MIPSAMode *am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as Ity_F64
+ addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, r0, am_addr));
+
+ // load as 2xI32
+ addInstr(env, MIPSInstr_Load(4, r_r0_lo, am_addr, mode64));
+ addInstr(env, MIPSInstr_Load(4, r_r0_hi, nextMIPSAModeFloat(am_addr),
+ mode64));
+
+ add_to_sp(env, 16); // Reset SP
+
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp_lo, r_cond,
+ MIPSRH_Reg(r_r0_lo)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp_hi, r_cond,
+ MIPSRH_Reg(r_r0_hi)));
+
+ addInstr(env, MIPSInstr_Alu(Malu_NOR, r_cond_neg, r_cond,
+ MIPSRH_Reg(r_cond)));
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as Ity_F64
+ addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, rX, am_addr));
+
+ // load as 2xI32
+ addInstr(env, MIPSInstr_Load(4, r_rX_lo, am_addr, mode64));
+ addInstr(env, MIPSInstr_Load(4, r_rX_hi, nextMIPSAModeFloat(am_addr),
+ mode64));
+
+ add_to_sp(env, 16); // Reset SP
+
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp1_lo, r_cond_neg,
+ MIPSRH_Reg(r_rX_lo)));
+ addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp1_hi, r_cond_neg,
+ MIPSRH_Reg(r_rX_hi)));
+
+ addInstr(env, MIPSInstr_Alu(Malu_ADD, r_dst_lo, r_tmp_lo,
+ MIPSRH_Reg(r_tmp1_lo)));
+ addInstr(env, MIPSInstr_Alu(Malu_ADD, r_dst_hi, r_tmp_hi,
+ MIPSRH_Reg(r_tmp1_hi)));
+
+ sub_from_sp(env, 16); // Move SP down 16 bytes
+ am_addr = MIPSAMode_IR(0, StackPointer(mode64));
+
+ // store as I32
+ addInstr(env, MIPSInstr_Store(4, am_addr, r_dst_lo, mode64));
+ addInstr(env, MIPSInstr_Store(4, nextMIPSAModeFloat(am_addr),
+ r_dst_hi, mode64));
+
+ // load as Ity_F32
+ addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 8, r_dst, am_addr));
+
+ add_to_sp(env, 16); // Reset SP
+
+ return r_dst;
+ }
+ }
+
+ vex_printf("iselDblExpr(mips): No such tag(%u)\n", e->tag);
+ ppIRExpr(e);
+ vpanic("iselDblExpr_wrk(mips)");
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Statements ---*/
+/*---------------------------------------------------------*/
+
+static void iselStmt(ISelEnv * env, IRStmt * stmt)
+{
+ if (vex_traceflags & VEX_TRACE_VCODE) {
+ vex_printf("\n-- ");
+
+ ppIRStmt(stmt);
+ vex_printf("\n");
+ }
+
+ switch (stmt->tag) {
+ /* --------- STORE --------- */
+ case Ist_Store: {
+ MIPSAMode *am_addr;
+ IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
+
+ /*constructs addressing mode from address provided */
+ am_addr = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd);
+
+ if (tyd == Ity_I8 || tyd == Ity_I16 || tyd == Ity_I32 ||
+ (mode64 && (tyd == Ity_I64))) {
+ HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data);
+ addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(tyd)),
+ am_addr, r_src, mode64));
+ return;
+ }
+ if (!mode64 && (tyd == Ity_I64)) {
+ HReg vHi, vLo;
+ HReg r_addr = iselWordExpr_R(env, stmt->Ist.Store.addr);
+
+ iselInt64Expr(&vHi, &vLo, env, stmt->Ist.Store.data);
+
+ addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(Ity_I32)),
+ MIPSAMode_IR(0, r_addr), vHi, mode64));
+ addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(Ity_I32)),
+ MIPSAMode_IR(4, r_addr), vLo, mode64));
+ return;
+ }
+ if (tyd == Ity_F32) {
+ HReg fr_src = iselFltExpr(env, stmt->Ist.Store.data);
+ addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 4, fr_src,
+ am_addr));
+ return;
+ }
+
+ break;
+ }
+
+ /* --------- PUT --------- */
+ case Ist_Put: {
+ IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
+
+ if (ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 ||
+ (ty == Ity_I64 && mode64)) {
+ HReg r_src = iselWordExpr_R(env, stmt->Ist.Put.data);
+ MIPSAMode *am_addr = MIPSAMode_IR(stmt->Ist.Put.offset,
+ GuestStatePointer(mode64));
+ addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(ty)),
+ am_addr, r_src, mode64));
+ return;
+ }
+
+ if (ty == Ity_I64 && !mode64) {
+ HReg vHi, vLo;
+ MIPSAMode *am_addr = MIPSAMode_IR(stmt->Ist.Put.offset,
+ GuestStatePointer(mode64));
+ MIPSAMode *am_addr4 = MIPSAMode_IR(stmt->Ist.Put.offset + 4,
+ GuestStatePointer(mode64));
+ iselInt64Expr(&vHi, &vLo, env, stmt->Ist.Put.data);
+ addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(Ity_I32)),
+ am_addr, vLo, mode64));
+ addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(Ity_I32)),
+ am_addr4, vHi, mode64));
+ return;
+
+ }
+
+ if (ty == Ity_F32) {
+ HReg fr_src = iselFltExpr(env, stmt->Ist.Put.data);
+ MIPSAMode *am_addr = MIPSAMode_IR(stmt->Ist.Put.offset,
+ GuestStatePointer(mode64));
+ addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 4, fr_src,
+ am_addr));
+ return;
+ }
+
+ if (ty == Ity_F64) {
+ HReg fr_src;
+ fr_src = iselDblExpr(env, stmt->Ist.Put.data);
+ MIPSAMode *am_addr = MIPSAMode_IR(stmt->Ist.Put.offset,
+ GuestStatePointer(mode64));
+ addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, fr_src,
+ am_addr));
+ return;
+ }
+ break;
+ }
+
+ /* --------- TMP --------- */
+ case Ist_WrTmp: {
+ IRTemp tmp = stmt->Ist.WrTmp.tmp;
+ IRType ty = typeOfIRTemp(env->type_env, tmp);
+
+ if (ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I1) {
+ HReg r_dst = lookupIRTemp(env, tmp);
+ HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data);
+ addInstr(env, mk_iMOVds_RR(r_dst, r_src));
+ return;
+ }
+
+ if (ty == Ity_I64) {
+ HReg rHi, rLo, dstHi, dstLo;
+ iselInt64Expr(&rHi, &rLo, env, stmt->Ist.WrTmp.data);
+ lookupIRTemp64(&dstHi, &dstLo, env, tmp);
+ addInstr(env, mk_iMOVds_RR(dstHi, rHi));
+ addInstr(env, mk_iMOVds_RR(dstLo, rLo));
+ return;
+ }
+
+ if (ty == Ity_F32) {
+ HReg fr_dst = lookupIRTemp(env, tmp);
+ HReg fr_src = iselFltExpr(env, stmt->Ist.WrTmp.data);
+ addInstr(env, MIPSInstr_FpUnary(Mfp_MOVS, fr_dst, fr_src));
+ return;
+ }
+
+ if (ty == Ity_F64) {
+ HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data);
+ HReg dst = lookupIRTemp(env, tmp);
+ addInstr(env, MIPSInstr_FpUnary(Mfp_MOVD, dst, src));
+ return;
+ }
+ break;
+ }
+
+ /* --------- Call to DIRTY helper --------- */
+ case Ist_Dirty: {
+ IRType retty;
+ IRDirty *d = stmt->Ist.Dirty.details;
+ Bool passBBP = False;
+
+ if (d->nFxState == 0)
+ vassert(!d->needsBBP);
+ passBBP = toBool(d->nFxState > 0 && d->needsBBP);
+
+ /* Marshal args, do the call, clear stack. */
+ doHelperCall(env, passBBP, d->guard, d->cee, d->args);
+
+ /* Now figure out what to do with the returned value, if any. */
+ if (d->tmp == IRTemp_INVALID)
+ /* No return value. Nothing to do. */
+ return;
+
+ retty = typeOfIRTemp(env->type_env, d->tmp);
+ if (retty == Ity_I64 && !mode64) {
+ vex_printf
+ ("Dirty! Return 64 bits. Not implemented (yet!)\n");
+ return;
+ }
+ if (retty == Ity_I8 || retty == Ity_I16 || retty == Ity_I32
+ || (retty == Ity_I64 && mode64)) {
+ /* The returned value is in %r2. Park it in the register
+ associated with tmp. */
+ HReg r_dst = lookupIRTemp(env, d->tmp);
+ addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
+ return;
+ }
+ break;
+ }
+
+ /* --------- Load Linked or Store Conditional --------- */
+ case Ist_LLSC: {
+ //Temporary solution; this need to be rewritten again for MIPS.
+ //On MIPS you can not read from address that is locked with LL before SC.
+ // If you read from address that is locked than SC will fall.
+ IRTemp res = stmt->Ist.LLSC.result;
+ IRType tyRes = typeOfIRTemp(env->type_env, res);
+ IRType tyAddr = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.addr);
+
+ if (!mode64 && (tyAddr != Ity_I32))
+ goto stmt_fail;
+
+ if (stmt->Ist.LLSC.storedata == NULL) {
+ /* LL */
+ MIPSAMode *r_addr;
+ /*constructs addressing mode from address provided */
+ r_addr = iselWordExpr_AMode(env, stmt->Ist.LLSC.addr, tyAddr);
+
+ HReg r_dst = lookupIRTemp(env, res);
+ if (tyRes == Ity_I32) {
+ addInstr(env, MIPSInstr_Load(4, r_dst, r_addr, mode64));
+ return;
+ } else if (tyRes == Ity_I64 && mode64) {
+ addInstr(env, MIPSInstr_Load(8, r_dst, r_addr, mode64));
+ return;
+ }
+ /* fallthru */ ;
+ } else {
+ /* SC */
+ MIPSAMode *r_addr;
+ r_addr = iselWordExpr_AMode(env, stmt->Ist.LLSC.addr, tyAddr);
+ HReg r_src = iselWordExpr_R(env, stmt->Ist.LLSC.storedata);
+ HReg r_dst = lookupIRTemp(env, res);
+ IRType tyData = typeOfIRExpr(env->type_env,
+ stmt->Ist.LLSC.storedata);
+
+ if (tyData == Ity_I32) {
+ addInstr(env, MIPSInstr_Store(4, r_addr, r_src, mode64));
+ addInstr(env, MIPSInstr_LI(r_dst, 0x1));
+ return;
+ } else if (tyData == Ity_I64 && mode64) {
+ addInstr(env, MIPSInstr_Store(8, r_addr, r_src, mode64));
+ addInstr(env, MIPSInstr_LI(r_dst, 0x1));
+ return;
+ }
+ /* fallthru */
+ }
+ goto stmt_fail;
+ /*NOTREACHED*/}
+
+ /* --------- INSTR MARK --------- */
+ /* Doesn't generate any executable code ... */
+ case Ist_IMark:
+ return;
+
+ /* --------- ABI HINT --------- */
+ /* These have no meaning (denotation in the IR) and so we ignore
+ them ... if any actually made it this far. */
+ case Ist_AbiHint:
+ return;
+
+ /* --------- NO-OP --------- */
+ /* Fairly self-explanatory, wouldn't you say? */
+ case Ist_NoOp:
+ return;
+
+ /* --------- EXIT --------- */
+ case Ist_Exit: {
+ IRConst* dst = stmt->Ist.Exit.dst;
+ if (!mode64 && dst->tag != Ico_U32)
+ vpanic("iselStmt(mips32): Ist_Exit: dst is not a 32-bit value");
+ if (mode64 && dst->tag != Ico_U64)
+ vpanic("iselStmt(mips64): Ist_Exit: dst is not a 64-bit value");
+
+ MIPSCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
+ MIPSAMode* amPC = MIPSAMode_IR(stmt->Ist.Exit.offsIP,
+ hregMIPS_GPR10(mode64));
+
+ /* Case: boring transfer to known address */
+ if (stmt->Ist.Exit.jk == Ijk_Boring
+ || stmt->Ist.Exit.jk == Ijk_Call
+ /* || stmt->Ist.Exit.jk == Ijk_Ret */) {
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = mode64
+ ? (((Addr64)stmt->Ist.Exit.dst->Ico.U64) > (Addr64)env->max_ga)
+ : (((Addr32)stmt->Ist.Exit.dst->Ico.U32) > (Addr32)env->max_ga);
+ if (0) vex_printf("%s", toFastEP ? "Y" : ",");
+ addInstr(env, MIPSInstr_XDirect(
+ mode64 ? (Addr64)stmt->Ist.Exit.dst->Ico.U64
+ : (Addr64)stmt->Ist.Exit.dst->Ico.U32,
+ amPC, cc, toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, MIPSInstr_XAssisted(r, amPC, cc, Ijk_Boring));
+ }
+ return;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (stmt->Ist.Exit.jk) {
+ /* Keep this list in sync with that in iselNext below */
+ case Ijk_ClientReq:
+ case Ijk_EmFail:
+ case Ijk_EmWarn:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_SigBUS:
+ case Ijk_SigTRAP:
+ case Ijk_Sys_syscall:
+ case Ijk_TInval:
+ {
+ HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, MIPSInstr_XAssisted(r, amPC, cc,
+ stmt->Ist.Exit.jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Do we ever expect to see any other kind? */
+ goto stmt_fail;
+ }
+
+ default:
+ break;
+ }
+
+ stmt_fail:
+ vex_printf("stmt_fail tag: 0x%x\n", stmt->tag);
+ ppIRStmt(stmt);
+ vpanic("iselStmt:\n");
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Basic block terminators (Nexts) ---*/
+/*---------------------------------------------------------*/
+
+static void iselNext ( ISelEnv* env,
+ IRExpr* next, IRJumpKind jk, Int offsIP )
+{
+ if (vex_traceflags & VEX_TRACE_VCODE) {
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
+ ppIRJumpKind(jk);
+ vex_printf( "\n");
+ }
+
+ /* Case: boring transfer to known address */
+ if (next->tag == Iex_Const) {
+ IRConst* cdst = next->Iex.Const.con;
+ vassert(cdst->tag == (env->mode64 ? Ico_U64 :Ico_U32));
+ if (jk == Ijk_Boring || jk == Ijk_Call) {
+ /* Boring transfer to known address */
+ MIPSAMode* amPC = MIPSAMode_IR(offsIP, hregMIPS_GPR10(env->mode64));
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = env->mode64
+ ? (((Addr64)cdst->Ico.U64) > (Addr64)env->max_ga)
+ : (((Addr32)cdst->Ico.U32) > (Addr32)env->max_ga);
+ if (0) vex_printf("%s", toFastEP ? "X" : ".");
+ addInstr(env, MIPSInstr_XDirect(
+ env->mode64 ? (Addr64)cdst->Ico.U64
+ : (Addr64)cdst->Ico.U32,
+ amPC, MIPScc_AL, toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg r = iselWordExpr_R(env, next);
+ addInstr(env, MIPSInstr_XAssisted(r, amPC, MIPScc_AL,
+ Ijk_Boring));
+ }
+ return;
+ }
+ }
+
+ /* Case: call/return (==boring) transfer to any address */
+ switch (jk) {
+ case Ijk_Boring: case Ijk_Ret: case Ijk_Call: {
+
+ HReg r = iselWordExpr_R(env, next);
+ MIPSAMode* amPC = MIPSAMode_IR(offsIP, hregMIPS_GPR10(env->mode64));
+ if (env->chainingAllowed) {
+ addInstr(env, MIPSInstr_XIndir(r, amPC, MIPScc_AL));
+ } else {
+ addInstr(env, MIPSInstr_XAssisted(r, amPC, MIPScc_AL,
+ Ijk_Boring));
+ }
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (jk) {
+ /* Keep this list in sync with that for Ist_Exit above */
+ case Ijk_ClientReq:
+ case Ijk_EmFail:
+ case Ijk_EmWarn:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_SigBUS:
+ case Ijk_SigTRAP:
+ case Ijk_Sys_syscall:
+ case Ijk_TInval: {
+ HReg r = iselWordExpr_R(env, next);
+ MIPSAMode* amPC = MIPSAMode_IR(offsIP, hregMIPS_GPR10(env->mode64));
+ addInstr(env, MIPSInstr_XAssisted(r, amPC, MIPScc_AL, jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
+ ppIRJumpKind(jk);
+ vex_printf( "\n");
+ vassert(0); // are we expecting any other kind?
+}
+
+/*---------------------------------------------------------*/
+/*--- Insn selector top-level ---*/
+/*---------------------------------------------------------*/
+
+/* Translate an entire BB to mips code. */
+HInstrArray *iselSB_MIPS ( IRSB* bb,
+ VexArch arch_host,
+ VexArchInfo* archinfo_host,
+ VexAbiInfo* vbi,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga )
+{
+ Int i, j;
+ HReg hreg, hregHI;
+ ISelEnv* env;
+ UInt hwcaps_host = archinfo_host->hwcaps;
+ MIPSAMode *amCounter, *amFailAddr;
+
+ /* sanity ... */
+ vassert(arch_host == VexArchMIPS32);
+ vassert(VEX_PRID_COMP_MIPS == hwcaps_host
+ || VEX_PRID_COMP_BROADCOM == hwcaps_host);
+
+ mode64 = arch_host != VexArchMIPS32;
+
+ /* Make up an initial environment to use. */
+ env = LibVEX_Alloc(sizeof(ISelEnv));
+ env->vreg_ctr = 0;
+ env->mode64 = mode64;
+
+ /* Set up output code array. */
+ env->code = newHInstrArray();
+
+ /* Copy BB's type env. */
+ env->type_env = bb->tyenv;
+
+ /* Make up an IRTemp -> virtual HReg mapping. This doesn't
+ change as we go along. */
+ env->n_vregmap = bb->tyenv->types_used;
+ env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
+ env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
+
+ /* and finally ... */
+ env->hwcaps = hwcaps_host;
+ env->chainingAllowed = chainingAllowed;
+ env->hwcaps = hwcaps_host;
+ env->max_ga = max_ga;
+
+ /* For each IR temporary, allocate a suitably-kinded virtual
+ register. */
+ j = 0;
+ for (i = 0; i < env->n_vregmap; i++) {
+ hregHI = hreg = INVALID_HREG;
+ switch (bb->tyenv->types[i]) {
+ case Ity_I1:
+ case Ity_I8:
+ case Ity_I16:
+ case Ity_I32: {
+ hreg = mkHReg(j++, HRcInt32, True);
+ break;
+ }
+ case Ity_I64: {
+ hreg = mkHReg(j++, HRcInt32, True);
+ hregHI = mkHReg(j++, HRcInt32, True);
+ break;
+ }
+ case Ity_I128:
+ vassert(mode64);
+ hreg = mkHReg(j++, HRcInt64, True);
+ hregHI = mkHReg(j++, HRcInt64, True);
+ break;
+ case Ity_F32: {
+ hreg = mkHReg(j++, HRcFlt32, True);
+ break;
+ }
+ case Ity_F64:
+ hreg = mkHReg(j++, HRcFlt64, True);
+ break;
+ default:
+ ppIRType(bb->tyenv->types[i]);
+ vpanic("iselBB(mips): IRTemp type");
+ }
+ env->vregmap[i] = hreg;
+ env->vregmapHI[i] = hregHI;
+ }
+ env->vreg_ctr = j;
+
+ /* The very first instruction must be an event check. */
+ amCounter = MIPSAMode_IR(offs_Host_EvC_Counter, hregMIPS_GPR10(mode64));
+ amFailAddr = MIPSAMode_IR(offs_Host_EvC_FailAddr, hregMIPS_GPR10(mode64));
+ addInstr(env, MIPSInstr_EvCheck(amCounter, amFailAddr));
+
+ /* Possibly a block counter increment (for profiling). At this
+ point we don't know the address of the counter, so just pretend
+ it is zero. It will have to be patched later, but before this
+ translation is used, by a call to LibVEX_patchProfCtr. */
+ if (addProfInc) {
+ addInstr(env, MIPSInstr_ProfInc());
+ }
+
+ /* Ok, finally we can iterate over the statements. */
+ for (i = 0; i < bb->stmts_used; i++)
+ iselStmt(env, bb->stmts[i]);
+
+ iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
+
+ /* record the number of vregs we used. */
+ env->code->n_vregs = env->vreg_ctr;
+ return env->code;
+
+}
+
+/*---------------------------------------------------------------*/
+/*--- end host_mips_isel.c ---*/
+/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/host_ppc_defs.c b/main/VEX/priv/host_ppc_defs.c
index ea06495..44c23ba 100644
--- a/main/VEX/priv/host_ppc_defs.c
+++ b/main/VEX/priv/host_ppc_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -630,6 +630,27 @@
case Pfp_FRIN: return "frin";
case Pfp_FRIP: return "frip";
case Pfp_FRIZ: return "friz";
+ case Pfp_DFPADD: return "dadd";
+ case Pfp_DFPADDQ: return "daddq";
+ case Pfp_DFPSUB: return "dsub";
+ case Pfp_DFPSUBQ: return "dsubq";
+ case Pfp_DFPMUL: return "dmul";
+ case Pfp_DFPMULQ: return "dmulq";
+ case Pfp_DFPDIV: return "ddivd";
+ case Pfp_DFPDIVQ: return "ddivq";
+ case Pfp_DCTDP: return "dctdp";
+ case Pfp_DRSP: return "drsp";
+ case Pfp_DCTFIX: return "dctfix";
+ case Pfp_DCFFIX: return "dcffix";
+ case Pfp_DCTQPQ: return "dctqpq";
+ case Pfp_DCFFIXQ: return "dcffixq";
+ case Pfp_DQUA: return "dqua";
+ case Pfp_DQUAQ: return "dquaq";
+ case Pfp_DXEX: return "dxex";
+ case Pfp_DXEXQ: return "dxexq";
+ case Pfp_DIEX: return "diex";
+ case Pfp_DIEXQ: return "diexq";
+ case Pfp_RRDTR: return "rrdtr";
default: vpanic("showPPCFpOp");
}
}
@@ -830,13 +851,33 @@
vassert(0 == (argiregs & ~mask));
return i;
}
-PPCInstr* PPCInstr_Goto ( IRJumpKind jk,
- PPCCondCode cond, PPCRI* dst ) {
- PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
- i->tag = Pin_Goto;
- i->Pin.Goto.cond = cond;
- i->Pin.Goto.dst = dst;
- i->Pin.Goto.jk = jk;
+PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA,
+ PPCCondCode cond, Bool toFastEP ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_XDirect;
+ i->Pin.XDirect.dstGA = dstGA;
+ i->Pin.XDirect.amCIA = amCIA;
+ i->Pin.XDirect.cond = cond;
+ i->Pin.XDirect.toFastEP = toFastEP;
+ return i;
+}
+PPCInstr* PPCInstr_XIndir ( HReg dstGA, PPCAMode* amCIA,
+ PPCCondCode cond ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_XIndir;
+ i->Pin.XIndir.dstGA = dstGA;
+ i->Pin.XIndir.amCIA = amCIA;
+ i->Pin.XIndir.cond = cond;
+ return i;
+}
+PPCInstr* PPCInstr_XAssisted ( HReg dstGA, PPCAMode* amCIA,
+ PPCCondCode cond, IRJumpKind jk ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_XAssisted;
+ i->Pin.XAssisted.dstGA = dstGA;
+ i->Pin.XAssisted.amCIA = amCIA;
+ i->Pin.XAssisted.cond = cond;
+ i->Pin.XAssisted.jk = jk;
return i;
}
PPCInstr* PPCInstr_CMov ( PPCCondCode cond,
@@ -970,6 +1011,187 @@
i->Pin.FpRSP.src = src;
return i;
}
+PPCInstr* PPCInstr_Dfp64Unary(PPCFpOp op, HReg dst, HReg src) {
+ PPCInstr* i = LibVEX_Alloc( sizeof(PPCInstr) );
+ i->tag = Pin_Dfp64Unary;
+ i->Pin.Dfp64Unary.op = op;
+ i->Pin.Dfp64Unary.dst = dst;
+ i->Pin.Dfp64Unary.src = src;
+ return i;
+}
+PPCInstr* PPCInstr_Dfp64Binary(PPCFpOp op, HReg dst, HReg srcL, HReg srcR) {
+ PPCInstr* i = LibVEX_Alloc( sizeof(PPCInstr) );
+ i->tag = Pin_Dfp64Binary;
+ i->Pin.Dfp64Binary.op = op;
+ i->Pin.Dfp64Binary.dst = dst;
+ i->Pin.Dfp64Binary.srcL = srcL;
+ i->Pin.Dfp64Binary.srcR = srcR;
+ return i;
+}
+PPCInstr* PPCInstr_DfpShift ( PPCFpOp op, HReg dst, HReg src, PPCRI* shift ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_DfpShift;
+ i->Pin.DfpShift.op = op;
+ i->Pin.DfpShift.shift = shift;
+ i->Pin.DfpShift.src = src;
+ i->Pin.DfpShift.dst = dst;
+ return i;
+}
+PPCInstr* PPCInstr_Dfp128Unary(PPCFpOp op, HReg dst_hi, HReg dst_lo,
+ HReg src_hi, HReg src_lo) {
+ PPCInstr* i = LibVEX_Alloc( sizeof(PPCInstr) );
+ i->tag = Pin_Dfp128Unary;
+ i->Pin.Dfp128Unary.op = op;
+ i->Pin.Dfp128Unary.dst_hi = dst_hi;
+ i->Pin.Dfp128Unary.dst_lo = dst_lo;
+ i->Pin.Dfp128Unary.src_hi = src_hi;
+ i->Pin.Dfp128Unary.src_lo = src_lo;
+ return i;
+}
+PPCInstr* PPCInstr_Dfp128Binary(PPCFpOp op, HReg dst_hi, HReg dst_lo,
+ HReg srcR_hi, HReg srcR_lo) {
+ /* dst is used to pass the srcL argument and return the result */
+ PPCInstr* i = LibVEX_Alloc( sizeof(PPCInstr) );
+ i->tag = Pin_Dfp128Binary;
+ i->Pin.Dfp128Binary.op = op;
+ i->Pin.Dfp128Binary.dst_hi = dst_hi;
+ i->Pin.Dfp128Binary.dst_lo = dst_lo;
+ i->Pin.Dfp128Binary.srcR_hi = srcR_hi;
+ i->Pin.Dfp128Binary.srcR_lo = srcR_lo;
+ return i;
+}
+PPCInstr* PPCInstr_DfpShift128 ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
+ HReg src_hi, HReg src_lo,
+ PPCRI* shift ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_DfpShift128;
+ i->Pin.DfpShift128.op = op;
+ i->Pin.DfpShift128.shift = shift;
+ i->Pin.DfpShift128.src_hi = src_hi;
+ i->Pin.DfpShift128.src_lo = src_lo;
+ i->Pin.DfpShift128.dst_hi = dst_hi;
+ i->Pin.DfpShift128.dst_lo = dst_lo;
+ return i;
+}
+PPCInstr* PPCInstr_DfpRound ( HReg dst, HReg src, PPCRI* r_rmc ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_DfpRound;
+ i->Pin.DfpRound.dst = dst;
+ i->Pin.DfpRound.src = src;
+ i->Pin.DfpRound.r_rmc = r_rmc;
+ return i;
+}
+PPCInstr* PPCInstr_DfpRound128 ( HReg dst_hi, HReg dst_lo, HReg src_hi,
+ HReg src_lo, PPCRI* r_rmc ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_DfpRound128;
+ i->Pin.DfpRound128.dst_hi = dst_hi;
+ i->Pin.DfpRound128.dst_lo = dst_lo;
+ i->Pin.DfpRound128.src_hi = src_hi;
+ i->Pin.DfpRound128.src_lo = src_lo;
+ i->Pin.DfpRound128.r_rmc = r_rmc;
+ return i;
+}
+PPCInstr* PPCInstr_DfpQuantize ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR,
+ PPCRI* rmc ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_DfpQuantize;
+ i->Pin.DfpQuantize.op = op;
+ i->Pin.DfpQuantize.dst = dst;
+ i->Pin.DfpQuantize.srcL = srcL;
+ i->Pin.DfpQuantize.srcR = srcR;
+ i->Pin.DfpQuantize.rmc = rmc;
+ return i;
+}
+PPCInstr* PPCInstr_DfpQuantize128 ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
+ HReg src_hi, HReg src_lo, PPCRI* rmc ) {
+ /* dst is used to pass left operand in and return result */
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_DfpQuantize128;
+ i->Pin.DfpQuantize128.op = op;
+ i->Pin.DfpQuantize128.dst_hi = dst_hi;
+ i->Pin.DfpQuantize128.dst_lo = dst_lo;
+ i->Pin.DfpQuantize128.src_hi = src_hi;
+ i->Pin.DfpQuantize128.src_lo = src_lo;
+ i->Pin.DfpQuantize128.rmc = rmc;
+ return i;
+}
+PPCInstr* PPCInstr_DfpD128toD64 ( PPCFpOp op, HReg dst,
+ HReg src_hi, HReg src_lo ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_DfpD128toD64;
+ i->Pin.DfpD128toD64.op = op;
+ i->Pin.DfpD128toD64.src_hi = src_hi;
+ i->Pin.DfpD128toD64.src_lo = src_lo;
+ i->Pin.DfpD128toD64.dst = dst;
+ return i;
+}
+PPCInstr* PPCInstr_DfpI64StoD128 ( PPCFpOp op, HReg dst_hi,
+ HReg dst_lo, HReg src ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_DfpI64StoD128;
+ i->Pin.DfpI64StoD128.op = op;
+ i->Pin.DfpI64StoD128.src = src;
+ i->Pin.DfpI64StoD128.dst_hi = dst_hi;
+ i->Pin.DfpI64StoD128.dst_lo = dst_lo;
+ return i;
+}
+PPCInstr* PPCInstr_ExtractExpD128 ( PPCFpOp op, HReg dst,
+ HReg src_hi, HReg src_lo ) {
+ /* dst is used to pass the srcL argument */
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_ExtractExpD128;
+ i->Pin.ExtractExpD128.op = op;
+ i->Pin.ExtractExpD128.dst = dst;
+ i->Pin.ExtractExpD128.src_hi = src_hi;
+ i->Pin.ExtractExpD128.src_lo = src_lo;
+ return i;
+}
+PPCInstr* PPCInstr_InsertExpD128 ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
+ HReg srcL, HReg srcR_hi, HReg srcR_lo ) {
+ /* dst is used to pass the srcL argument */
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_InsertExpD128;
+ i->Pin.InsertExpD128.op = op;
+ i->Pin.InsertExpD128.dst_hi = dst_hi;
+ i->Pin.InsertExpD128.dst_lo = dst_lo;
+ i->Pin.InsertExpD128.srcL = srcL;
+ i->Pin.InsertExpD128.srcR_hi = srcR_hi;
+ i->Pin.InsertExpD128.srcR_lo = srcR_lo;
+ return i;
+}
+PPCInstr* PPCInstr_Dfp64Cmp (/* UInt crfD,*/ HReg dst, HReg srcL, HReg srcR ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_Dfp64Cmp;
+ i->Pin.Dfp64Cmp.dst = dst;
+ i->Pin.Dfp64Cmp.srcL = srcL;
+ i->Pin.Dfp64Cmp.srcR = srcR;
+ return i;
+}
+PPCInstr* PPCInstr_Dfp128Cmp ( HReg dst, HReg srcL_hi, HReg srcL_lo,
+ HReg srcR_hi, HReg srcR_lo ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_Dfp128Cmp;
+ i->Pin.Dfp128Cmp.dst = dst;
+ i->Pin.Dfp128Cmp.srcL_hi = srcL_hi;
+ i->Pin.Dfp128Cmp.srcL_lo = srcL_lo;
+ i->Pin.Dfp128Cmp.srcR_hi = srcR_hi;
+ i->Pin.Dfp128Cmp.srcR_lo = srcR_lo;
+ return i;
+}
+PPCInstr* PPCInstr_EvCheck ( PPCAMode* amCounter,
+ PPCAMode* amFailAddr ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_EvCheck;
+ i->Pin.EvCheck.amCounter = amCounter;
+ i->Pin.EvCheck.amFailAddr = amFailAddr;
+ return i;
+}
+PPCInstr* PPCInstr_ProfInc ( void ) {
+ PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag = Pin_ProfInc;
+ return i;
+}
/*
Valid combo | fromI | int32 | syned | flt64 |
@@ -1040,10 +1262,11 @@
vassert(cond.test != Pct_ALWAYS);
return i;
}
-PPCInstr* PPCInstr_FpLdFPSCR ( HReg src ) {
+PPCInstr* PPCInstr_FpLdFPSCR ( HReg src, Bool dfp_rm ) {
PPCInstr* i = LibVEX_Alloc(sizeof(PPCInstr));
i->tag = Pin_FpLdFPSCR;
i->Pin.FpLdFPSCR.src = src;
+ i->Pin.FpLdFPSCR.dfp_rm = dfp_rm ? 1 : 0;
return i;
}
PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR ) {
@@ -1333,26 +1556,53 @@
vex_printf("] }");
break;
}
- case Pin_Goto:
- vex_printf("goto: ");
- if (i->Pin.Goto.cond.test != Pct_ALWAYS) {
- vex_printf("if (%s) ", showPPCCondCode(i->Pin.Goto.cond));
- }
- vex_printf("{ ");
- if (i->Pin.Goto.jk != Ijk_Boring
- && i->Pin.Goto.jk != Ijk_Call
- && i->Pin.Goto.jk != Ijk_Ret) {
- vex_printf("li %%r31,$");
- ppIRJumpKind(i->Pin.Goto.jk);
- vex_printf(" ; ");
- }
- if (i->Pin.Goto.dst->tag == Pri_Imm) {
- ppLoadImm(hregPPC_GPR3(mode64), i->Pin.Goto.dst->Pri.Imm,
- mode64);
+ case Pin_XDirect:
+ vex_printf("(xDirect) ");
+ vex_printf("if (%s) { ",
+ showPPCCondCode(i->Pin.XDirect.cond));
+ if (mode64) {
+ vex_printf("imm64 r30,0x%llx; ", i->Pin.XDirect.dstGA);
+ vex_printf("std r30,");
} else {
- ppMovReg(hregPPC_GPR3(mode64), i->Pin.Goto.dst->Pri.Reg);
+ vex_printf("imm32 r30,0x%llx; ", i->Pin.XDirect.dstGA);
+ vex_printf("stw r30,");
}
- vex_printf(" ; blr }");
+ ppPPCAMode(i->Pin.XDirect.amCIA);
+ vex_printf("; ");
+ if (mode64) {
+ vex_printf("imm64-fixed5 r30,$disp_cp_chain_me_to_%sEP; ",
+ i->Pin.XDirect.toFastEP ? "fast" : "slow");
+ } else {
+ vex_printf("imm32-fixed2 r30,$disp_cp_chain_me_to_%sEP; ",
+ i->Pin.XDirect.toFastEP ? "fast" : "slow");
+ }
+ vex_printf("mtctr r30; bctrl }");
+ return;
+ case Pin_XIndir:
+ vex_printf("(xIndir) ");
+ vex_printf("if (%s) { ",
+ showPPCCondCode(i->Pin.XIndir.cond));
+ vex_printf("%s ", mode64 ? "std" : "stw");
+ ppHRegPPC(i->Pin.XIndir.dstGA);
+ vex_printf(",");
+ ppPPCAMode(i->Pin.XIndir.amCIA);
+ vex_printf("; ");
+ vex_printf("imm%s r30,$disp_cp_xindir; ", mode64 ? "64" : "32");
+ vex_printf("mtctr r30; bctr }");
+ return;
+ case Pin_XAssisted:
+ vex_printf("(xAssisted) ");
+ vex_printf("if (%s) { ",
+ showPPCCondCode(i->Pin.XAssisted.cond));
+ vex_printf("%s ", mode64 ? "std" : "stw");
+ ppHRegPPC(i->Pin.XAssisted.dstGA);
+ vex_printf(",");
+ ppPPCAMode(i->Pin.XAssisted.amCIA);
+ vex_printf("; ");
+ vex_printf("li r31,$IRJumpKind_to_TRCVAL(%d); ",
+ (Int)i->Pin.XAssisted.jk);
+ vex_printf("imm%s r30,$disp_cp_xindir; ", mode64 ? "64" : "32");
+ vex_printf("mtctr r30; bctr }");
return;
case Pin_CMov:
vex_printf("cmov (%s) ", showPPCCondCode(i->Pin.CMov.cond));
@@ -1547,6 +1797,7 @@
case Pin_FpLdFPSCR:
vex_printf("mtfsf 0xFF,");
ppHRegPPC(i->Pin.FpLdFPSCR.src);
+ vex_printf(",0, %s", i->Pin.FpLdFPSCR.dfp_rm ? "1" : "0");
return;
case Pin_FpCmp:
vex_printf("fcmpo %%cr1,");
@@ -1711,6 +1962,172 @@
ppHRegPPC(i->Pin.AvLdVSCR.src);
return;
+ case Pin_Dfp64Unary:
+ vex_printf("%s ", showPPCFpOp(i->Pin.Dfp64Unary.op));
+ ppHRegPPC(i->Pin.Dfp64Unary.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.Dfp64Unary.src);
+ return;
+
+ case Pin_Dfp64Binary:
+ vex_printf("%s ", showPPCFpOp(i->Pin.Dfp64Binary.op));
+ ppHRegPPC(i->Pin.Dfp64Binary.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.Dfp64Binary.srcL);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.Dfp64Binary.srcR);
+ return;
+
+ case Pin_DfpShift:
+ vex_printf("%s ", showPPCFpOp(i->Pin.DfpShift.op));
+ ppHRegPPC(i->Pin.DfpShift.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpShift.src);
+ vex_printf(",");
+ ppPPCRI(i->Pin.DfpShift.shift);
+ return;
+
+ case Pin_Dfp128Unary:
+ vex_printf("%s ", showPPCFpOp(i->Pin.Dfp128Unary.op));
+ ppHRegPPC(i->Pin.Dfp128Unary.dst_hi);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.Dfp128Unary.src_hi);
+ return;
+
+ case Pin_Dfp128Binary:
+ vex_printf("%s ", showPPCFpOp(i->Pin.Dfp128Binary.op));
+ ppHRegPPC(i->Pin.Dfp128Binary.dst_hi);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.Dfp128Binary.srcR_hi);
+ return;
+
+ case Pin_DfpShift128:
+ vex_printf("%s ", showPPCFpOp(i->Pin.DfpShift128.op));
+ ppHRegPPC(i->Pin.DfpShift128.dst_hi);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpShift128.src_hi);
+ vex_printf(",");
+ ppPPCRI(i->Pin.DfpShift128.shift);
+ return;
+
+ case Pin_DfpRound:
+ vex_printf("drintx ");
+ ppHRegPPC(i->Pin.DfpRound.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpRound.src);
+ vex_printf(",");
+ ppPPCRI(i->Pin.DfpRound.r_rmc); /* R in bit 3 and RMC in bits 2:0 */
+ return;
+
+ case Pin_DfpRound128:
+ vex_printf("drintxq ");
+ ppHRegPPC(i->Pin.DfpRound128.dst_hi);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpRound128.src_hi);
+ vex_printf(",");
+ ppPPCRI(i->Pin.DfpRound128.r_rmc); /* R in bit 3 and RMC in bits 2:0 */
+ return;
+
+ case Pin_DfpQuantize:
+ vex_printf("%s ", showPPCFpOp(i->Pin.DfpQuantize.op));
+ ppHRegPPC(i->Pin.DfpQuantize.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpQuantize.srcL);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpQuantize.srcR);
+ vex_printf(",");
+ ppPPCRI(i->Pin.DfpQuantize.rmc);
+ return;
+
+ case Pin_DfpQuantize128:
+ /* Dst is used to pass in left source and return result */
+ vex_printf("dquaq ");
+ ppHRegPPC(i->Pin.DfpQuantize128.dst_hi);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpQuantize128.dst_hi);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpQuantize128.src_hi);
+ vex_printf(",");
+ ppPPCRI(i->Pin.DfpQuantize128.rmc);
+ return;
+
+ case Pin_DfpD128toD64:
+ vex_printf("%s ", showPPCFpOp(i->Pin.DfpD128toD64.op));
+ ppHRegPPC(i->Pin.DfpD128toD64.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpD128toD64.src_hi);
+ vex_printf(",");
+ return;
+
+ case Pin_DfpI64StoD128:
+ vex_printf("%s ", showPPCFpOp(i->Pin.DfpI64StoD128.op));
+ ppHRegPPC(i->Pin.DfpI64StoD128.dst_hi);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.DfpI64StoD128.src);
+ vex_printf(",");
+ return;
+ case Pin_ExtractExpD128:
+ vex_printf("dxexq ");
+ ppHRegPPC(i->Pin.ExtractExpD128.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.ExtractExpD128.src_hi);
+ return;
+ case Pin_InsertExpD128:
+ vex_printf("diexq ");
+ ppHRegPPC(i->Pin.InsertExpD128.dst_hi);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.InsertExpD128.srcL);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.InsertExpD128.srcR_hi);
+ return;
+ case Pin_Dfp64Cmp:
+ vex_printf("dcmpo %%cr1,");
+ ppHRegPPC(i->Pin.Dfp64Cmp.srcL);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.Dfp64Cmp.srcR);
+ vex_printf("; mfcr ");
+ ppHRegPPC(i->Pin.Dfp64Cmp.dst);
+ vex_printf("; rlwinm ");
+ ppHRegPPC(i->Pin.Dfp64Cmp.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.Dfp64Cmp.dst);
+ vex_printf(",8,28,31");
+ return;
+ case Pin_Dfp128Cmp:
+ vex_printf("dcmpoq %%cr1,");
+ ppHRegPPC(i->Pin.Dfp128Cmp.srcL_hi);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.Dfp128Cmp.srcR_hi);
+ vex_printf("; mfcr ");
+ ppHRegPPC(i->Pin.Dfp128Cmp.dst);
+ vex_printf("; rlwinm ");
+ ppHRegPPC(i->Pin.Dfp128Cmp.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.Dfp128Cmp.dst);
+ vex_printf(",8,28,31");
+ return;
+ case Pin_EvCheck:
+ /* Note that the counter dec is 32 bit even in 64-bit mode. */
+ vex_printf("(evCheck) ");
+ vex_printf("lwz r30,");
+ ppPPCAMode(i->Pin.EvCheck.amCounter);
+ vex_printf("; addic. r30,r30,-1; ");
+ vex_printf("stw r30,");
+ ppPPCAMode(i->Pin.EvCheck.amCounter);
+ vex_printf("; bge nofail; lwz r30,");
+ ppPPCAMode(i->Pin.EvCheck.amFailAddr);
+ vex_printf("; mtctr r30; bctr; nofail:");
+ return;
+ case Pin_ProfInc:
+ if (mode64) {
+ vex_printf("(profInc) imm64-fixed5 r30,$NotKnownYet; ");
+ vex_printf("ld r29,(r30); addi r29,r29,1; std r29,(r30)");
+ } else {
+ vex_printf("(profInc) imm32-fixed2 r30,$NotKnownYet; ");
+ vex_printf("lwz r29,4(r30); addic. r29,r29,1; stw r29,4(r30)");
+ vex_printf("lwz r29,0(r30); addze r29,r29; stw r29,0(r30)");
+ }
+ break;
default:
vex_printf("\nppPPCInstr: No such tag(%d)\n", (Int)i->tag);
vpanic("ppPPCInstr");
@@ -1809,17 +2226,21 @@
and no other, as a destination temporary. */
return;
}
- case Pin_Goto:
- addRegUsage_PPCRI(u, i->Pin.Goto.dst);
- /* GPR3 holds destination address from Pin_Goto */
- addHRegUse(u, HRmWrite, hregPPC_GPR3(mode64));
- if (i->Pin.Goto.jk != Ijk_Boring
- && i->Pin.Goto.jk != Ijk_Call
- && i->Pin.Goto.jk != Ijk_Ret)
- /* note, this is irrelevant since the guest state pointer
- register is not actually available to the allocator.
- But still .. */
- addHRegUse(u, HRmWrite, GuestStatePtr(mode64));
+ /* XDirect/XIndir/XAssisted are also a bit subtle. They
+ conditionally exit the block. Hence we only need to list (1)
+ the registers that they read, and (2) the registers that they
+ write in the case where the block is not exited. (2) is empty,
+ hence only (1) is relevant here. */
+ case Pin_XDirect:
+ addRegUsage_PPCAMode(u, i->Pin.XDirect.amCIA);
+ return;
+ case Pin_XIndir:
+ addHRegUse(u, HRmRead, i->Pin.XIndir.dstGA);
+ addRegUsage_PPCAMode(u, i->Pin.XIndir.amCIA);
+ return;
+ case Pin_XAssisted:
+ addHRegUse(u, HRmRead, i->Pin.XAssisted.dstGA);
+ addRegUsage_PPCAMode(u, i->Pin.XAssisted.amCIA);
return;
case Pin_CMov:
addRegUsage_PPCRI(u, i->Pin.CMov.src);
@@ -1978,7 +2399,107 @@
case Pin_AvLdVSCR:
addHRegUse(u, HRmRead, i->Pin.AvLdVSCR.src);
return;
-
+ case Pin_Dfp64Unary:
+ addHRegUse(u, HRmWrite, i->Pin.Dfp64Unary.dst);
+ addHRegUse(u, HRmRead, i->Pin.Dfp64Unary.src);
+ return;
+ case Pin_Dfp64Binary:
+ addHRegUse(u, HRmWrite, i->Pin.Dfp64Binary.dst);
+ addHRegUse(u, HRmRead, i->Pin.Dfp64Binary.srcL);
+ addHRegUse(u, HRmRead, i->Pin.Dfp64Binary.srcR);
+ return;
+ case Pin_DfpShift:
+ addRegUsage_PPCRI(u, i->Pin.DfpShift.shift);
+ addHRegUse(u, HRmWrite, i->Pin.DfpShift.src);
+ addHRegUse(u, HRmWrite, i->Pin.DfpShift.dst);
+ return;
+ case Pin_Dfp128Unary:
+ addHRegUse(u, HRmWrite, i->Pin.Dfp128Unary.dst_hi);
+ addHRegUse(u, HRmWrite, i->Pin.Dfp128Unary.dst_lo);
+ addHRegUse(u, HRmRead, i->Pin.Dfp128Unary.src_hi);
+ addHRegUse(u, HRmRead, i->Pin.Dfp128Unary.src_lo);
+ return;
+ case Pin_Dfp128Binary:
+ addHRegUse(u, HRmWrite, i->Pin.Dfp128Binary.dst_hi);
+ addHRegUse(u, HRmWrite, i->Pin.Dfp128Binary.dst_lo);
+ addHRegUse(u, HRmRead, i->Pin.Dfp128Binary.srcR_hi);
+ addHRegUse(u, HRmRead, i->Pin.Dfp128Binary.srcR_lo);
+ return;
+ case Pin_DfpRound:
+ addHRegUse(u, HRmWrite, i->Pin.DfpRound.dst);
+ addHRegUse(u, HRmRead, i->Pin.DfpRound.src);
+ return;
+ case Pin_DfpRound128:
+ addHRegUse(u, HRmWrite, i->Pin.DfpRound128.dst_hi);
+ addHRegUse(u, HRmWrite, i->Pin.DfpRound128.dst_lo);
+ addHRegUse(u, HRmRead, i->Pin.DfpRound128.src_hi);
+ addHRegUse(u, HRmRead, i->Pin.DfpRound128.src_lo);
+ return;
+ case Pin_DfpQuantize:
+ addRegUsage_PPCRI(u, i->Pin.DfpQuantize.rmc);
+ addHRegUse(u, HRmWrite, i->Pin.DfpQuantize.dst);
+ addHRegUse(u, HRmRead, i->Pin.DfpQuantize.srcL);
+ addHRegUse(u, HRmRead, i->Pin.DfpQuantize.srcR);
+ return;
+ case Pin_DfpQuantize128:
+ addHRegUse(u, HRmWrite, i->Pin.DfpQuantize128.dst_hi);
+ addHRegUse(u, HRmWrite, i->Pin.DfpQuantize128.dst_lo);
+ addHRegUse(u, HRmRead, i->Pin.DfpQuantize128.src_hi);
+ addHRegUse(u, HRmRead, i->Pin.DfpQuantize128.src_lo);
+ return;
+ case Pin_DfpShift128:
+ addRegUsage_PPCRI(u, i->Pin.DfpShift128.shift);
+ addHRegUse(u, HRmWrite, i->Pin.DfpShift128.src_hi);
+ addHRegUse(u, HRmWrite, i->Pin.DfpShift128.src_lo);
+ addHRegUse(u, HRmWrite, i->Pin.DfpShift128.dst_hi);
+ addHRegUse(u, HRmWrite, i->Pin.DfpShift128.dst_lo);
+ return;
+ case Pin_DfpD128toD64:
+ addHRegUse(u, HRmWrite, i->Pin.DfpD128toD64.src_hi);
+ addHRegUse(u, HRmWrite, i->Pin.DfpD128toD64.src_lo);
+ addHRegUse(u, HRmWrite, i->Pin.DfpD128toD64.dst);
+ return;
+ case Pin_DfpI64StoD128:
+ addHRegUse(u, HRmWrite, i->Pin.DfpI64StoD128.src);
+ addHRegUse(u, HRmWrite, i->Pin.DfpI64StoD128.dst_hi);
+ addHRegUse(u, HRmWrite, i->Pin.DfpI64StoD128.dst_lo);
+ return;
+ case Pin_ExtractExpD128:
+ addHRegUse(u, HRmWrite, i->Pin.ExtractExpD128.dst);
+ addHRegUse(u, HRmRead, i->Pin.ExtractExpD128.src_hi);
+ addHRegUse(u, HRmRead, i->Pin.ExtractExpD128.src_lo);
+ return;
+ case Pin_InsertExpD128:
+ addHRegUse(u, HRmWrite, i->Pin.InsertExpD128.dst_hi);
+ addHRegUse(u, HRmWrite, i->Pin.InsertExpD128.dst_lo);
+ addHRegUse(u, HRmRead, i->Pin.InsertExpD128.srcL);
+ addHRegUse(u, HRmRead, i->Pin.InsertExpD128.srcR_hi);
+ addHRegUse(u, HRmRead, i->Pin.InsertExpD128.srcR_lo);
+ return;
+ case Pin_Dfp64Cmp:
+ addHRegUse(u, HRmWrite, i->Pin.Dfp64Cmp.dst);
+ addHRegUse(u, HRmRead, i->Pin.Dfp64Cmp.srcL);
+ addHRegUse(u, HRmRead, i->Pin.Dfp64Cmp.srcR);
+ return;
+ case Pin_Dfp128Cmp:
+ addHRegUse(u, HRmWrite, i->Pin.Dfp128Cmp.dst);
+ addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcL_hi);
+ addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcL_lo);
+ addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcR_hi);
+ addHRegUse(u, HRmRead, i->Pin.Dfp128Cmp.srcR_lo);
+ return;
+ case Pin_EvCheck:
+ /* We expect both amodes only to mention the GSP (r31), so this
+ is in fact pointless, since GSP isn't allocatable, but
+ anyway.. */
+ addRegUsage_PPCAMode(u, i->Pin.EvCheck.amCounter);
+ addRegUsage_PPCAMode(u, i->Pin.EvCheck.amFailAddr);
+ addHRegUse(u, HRmWrite, hregPPC_GPR30(mode64)); /* also unavail to RA */
+ return;
+ case Pin_ProfInc:
+ addHRegUse(u, HRmWrite, hregPPC_GPR29(mode64));
+ addHRegUse(u, HRmWrite, hregPPC_GPR30(mode64));
+ return;
default:
ppPPCInstr(i, mode64);
vpanic("getRegUsage_PPCInstr");
@@ -2032,8 +2553,16 @@
return;
case Pin_Call:
return;
- case Pin_Goto:
- mapRegs_PPCRI(m, i->Pin.Goto.dst);
+ case Pin_XDirect:
+ mapRegs_PPCAMode(m, i->Pin.XDirect.amCIA);
+ return;
+ case Pin_XIndir:
+ mapReg(m, &i->Pin.XIndir.dstGA);
+ mapRegs_PPCAMode(m, i->Pin.XIndir.amCIA);
+ return;
+ case Pin_XAssisted:
+ mapReg(m, &i->Pin.XAssisted.dstGA);
+ mapRegs_PPCAMode(m, i->Pin.XAssisted.amCIA);
return;
case Pin_CMov:
mapRegs_PPCRI(m, i->Pin.CMov.src);
@@ -2174,7 +2703,106 @@
case Pin_AvLdVSCR:
mapReg(m, &i->Pin.AvLdVSCR.src);
return;
-
+ case Pin_Dfp64Unary:
+ mapReg(m, &i->Pin.Dfp64Unary.dst);
+ mapReg(m, &i->Pin.Dfp64Unary.src);
+ return;
+ case Pin_Dfp64Binary:
+ mapReg(m, &i->Pin.Dfp64Binary.dst);
+ mapReg(m, &i->Pin.Dfp64Binary.srcL);
+ mapReg(m, &i->Pin.Dfp64Binary.srcR);
+ return;
+ case Pin_DfpShift:
+ mapRegs_PPCRI(m, i->Pin.DfpShift.shift);
+ mapReg(m, &i->Pin.DfpShift.src);
+ mapReg(m, &i->Pin.DfpShift.dst);
+ return;
+ case Pin_Dfp128Unary:
+ mapReg(m, &i->Pin.Dfp128Unary.dst_hi);
+ mapReg(m, &i->Pin.Dfp128Unary.dst_lo);
+ mapReg(m, &i->Pin.Dfp128Unary.src_hi);
+ mapReg(m, &i->Pin.Dfp128Unary.src_lo);
+ return;
+ case Pin_Dfp128Binary:
+ mapReg(m, &i->Pin.Dfp128Binary.dst_hi);
+ mapReg(m, &i->Pin.Dfp128Binary.dst_lo);
+ mapReg(m, &i->Pin.Dfp128Binary.srcR_hi);
+ mapReg(m, &i->Pin.Dfp128Binary.srcR_lo);
+ return;
+ case Pin_DfpShift128:
+ mapRegs_PPCRI(m, i->Pin.DfpShift128.shift);
+ mapReg(m, &i->Pin.DfpShift128.src_hi);
+ mapReg(m, &i->Pin.DfpShift128.src_lo);
+ mapReg(m, &i->Pin.DfpShift128.dst_hi);
+ mapReg(m, &i->Pin.DfpShift128.dst_lo);
+ return;
+ case Pin_DfpRound:
+ mapReg(m, &i->Pin.DfpRound.dst);
+ mapReg(m, &i->Pin.DfpRound.src);
+ return;
+ case Pin_DfpRound128:
+ mapReg(m, &i->Pin.DfpRound128.dst_hi);
+ mapReg(m, &i->Pin.DfpRound128.dst_lo);
+ mapReg(m, &i->Pin.DfpRound128.src_hi);
+ mapReg(m, &i->Pin.DfpRound128.src_lo);
+ return;
+ case Pin_DfpQuantize:
+ mapRegs_PPCRI(m, i->Pin.DfpQuantize.rmc);
+ mapReg(m, &i->Pin.DfpQuantize.dst);
+ mapReg(m, &i->Pin.DfpQuantize.srcL);
+ mapReg(m, &i->Pin.DfpQuantize.srcR);
+ return;
+ case Pin_DfpQuantize128:
+ mapRegs_PPCRI(m, i->Pin.DfpQuantize128.rmc);
+ mapReg(m, &i->Pin.DfpQuantize128.dst_hi);
+ mapReg(m, &i->Pin.DfpQuantize128.dst_lo);
+ mapReg(m, &i->Pin.DfpQuantize128.src_hi);
+ mapReg(m, &i->Pin.DfpQuantize128.src_lo);
+ return;
+ case Pin_DfpD128toD64:
+ mapReg(m, &i->Pin.DfpD128toD64.src_hi);
+ mapReg(m, &i->Pin.DfpD128toD64.src_lo);
+ mapReg(m, &i->Pin.DfpD128toD64.dst);
+ return;
+ case Pin_DfpI64StoD128:
+ mapReg(m, &i->Pin.DfpI64StoD128.src);
+ mapReg(m, &i->Pin.DfpI64StoD128.dst_hi);
+ mapReg(m, &i->Pin.DfpI64StoD128.dst_lo);
+ return;
+ case Pin_ExtractExpD128:
+ mapReg(m, &i->Pin.ExtractExpD128.dst);
+ mapReg(m, &i->Pin.ExtractExpD128.src_hi);
+ mapReg(m, &i->Pin.ExtractExpD128.src_lo);
+ return;
+ case Pin_InsertExpD128:
+ mapReg(m, &i->Pin.InsertExpD128.dst_hi);
+ mapReg(m, &i->Pin.InsertExpD128.dst_lo);
+ mapReg(m, &i->Pin.InsertExpD128.srcL);
+ mapReg(m, &i->Pin.InsertExpD128.srcR_hi);
+ mapReg(m, &i->Pin.InsertExpD128.srcR_lo);
+ return;
+ case Pin_Dfp64Cmp:
+ mapReg(m, &i->Pin.Dfp64Cmp.dst);
+ mapReg(m, &i->Pin.Dfp64Cmp.srcL);
+ mapReg(m, &i->Pin.Dfp64Cmp.srcR);
+ return;
+ case Pin_Dfp128Cmp:
+ mapReg(m, &i->Pin.Dfp128Cmp.dst);
+ mapReg(m, &i->Pin.Dfp128Cmp.srcL_hi);
+ mapReg(m, &i->Pin.Dfp128Cmp.srcL_lo);
+ mapReg(m, &i->Pin.Dfp128Cmp.srcR_hi);
+ mapReg(m, &i->Pin.Dfp128Cmp.srcR_lo);
+ return;
+ case Pin_EvCheck:
+ /* We expect both amodes only to mention the GSP (r31), so this
+ is in fact pointless, since GSP isn't allocatable, but
+ anyway.. */
+ mapRegs_PPCAMode(m, i->Pin.EvCheck.amCounter);
+ mapRegs_PPCAMode(m, i->Pin.EvCheck.amFailAddr);
+ return;
+ case Pin_ProfInc:
+ /* hardwires r29 and r30 -- nothing to modify. */
+ return;
default:
ppPPCInstr(i, mode64);
vpanic("mapRegs_PPCInstr");
@@ -2308,7 +2936,7 @@
return n;
}
-/* Emit 32bit instruction big-endianly */
+/* Emit an instruction big-endianly */
static UChar* emit32 ( UChar* p, UInt w32 )
{
*p++ = toUChar((w32 >> 24) & 0x000000FF);
@@ -2318,6 +2946,17 @@
return p;
}
+/* Fetch an instruction big-endianly */
+static UInt fetch32 ( UChar* p )
+{
+ UInt w32 = 0;
+ w32 |= ((0xFF & (UInt)p[0]) << 24);
+ w32 |= ((0xFF & (UInt)p[1]) << 16);
+ w32 |= ((0xFF & (UInt)p[2]) << 8);
+ w32 |= ((0xFF & (UInt)p[3]) << 0);
+ return w32;
+}
+
/* The following mkForm[...] functions refer to ppc instruction forms
as per PPC32 p576
*/
@@ -2423,12 +3062,12 @@
}
// Only used by mtfsf
-static UChar* mkFormXFL ( UChar* p, UInt FM, UInt freg )
+static UChar* mkFormXFL ( UChar* p, UInt FM, UInt freg, UInt dfp_rm )
{
UInt theInstr;
vassert(FM < 0x100);
vassert(freg < 0x20);
- theInstr = ((63<<26) | (FM<<17) | (freg<<11) | (711<<1));
+ theInstr = ((63<<26) | (FM<<17) | (dfp_rm<<16) | (freg<<11) | (711<<1));
return emit32(p, theInstr);
}
@@ -2509,6 +3148,37 @@
return emit32(p, theInstr);
}
+static UChar* mkFormZ22 ( UChar* p, UInt opc1, UInt r1, UInt r2,
+ UInt constant, UInt opc2, UInt b0 )
+{
+ UInt theInstr;
+ vassert(opc1 < 0x40);
+ vassert(r1 < 0x20);
+ vassert(r2 < 0x20);
+ vassert(constant < 0x40); /* 6 bit constant */
+ vassert(opc2 < 0x200); /* 9 bit field */
+ vassert(b0 < 0x2);
+ theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) |
+ (constant<<10) | (opc2<<1) | (b0));
+ return emit32(p, theInstr);
+}
+
+static UChar* mkFormZ23 ( UChar* p, UInt opc1, UInt r1, UInt r2,
+ UInt r3, UInt rmc, UInt opc2, UInt b0 )
+{
+ UInt theInstr;
+ vassert(opc1 < 0x40);
+ vassert(r1 < 0x20);
+ vassert(r2 < 0x20);
+ vassert(r3 < 0x20);
+ vassert(rmc < 0x4);
+ vassert(opc2 < 0x100);
+ vassert(b0 < 0x2);
+ theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) |
+ (r3<<11) | (rmc<<9) | (opc2<<1) | (b0));
+ return emit32(p, theInstr);
+}
+
static UChar* doAMode_IR ( UChar* p, UInt opc1, UInt rSD,
PPCAMode* am, Bool mode64 )
{
@@ -2601,6 +3271,210 @@
return p;
}
+/* A simplified version of mkLoadImm that always generates 2 or 5
+ instructions (32 or 64 bits respectively) even if it could generate
+ fewer. This is needed for generating fixed sized patchable
+ sequences. */
+static UChar* mkLoadImm_EXACTLY2or5 ( UChar* p,
+ UInt r_dst, ULong imm, Bool mode64 )
+{
+ vassert(r_dst < 0x20);
+
+ if (!mode64) {
+ /* In 32-bit mode, make sure the top 32 bits of imm are a sign
+ extension of the bottom 32 bits. (Probably unnecessary.) */
+ UInt u32 = (UInt)imm;
+ Int s32 = (Int)u32;
+ Long s64 = (Long)s32;
+ imm = (ULong)s64;
+ }
+
+ if (!mode64) {
+ // addis r_dst,r0,(imm>>16) => lis r_dst, (imm>>16)
+ p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF);
+ // ori r_dst, r_dst, (imm & 0xFFFF)
+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF);
+
+ } else {
+ // full 64bit immediate load: 5 (five!) insns.
+
+ // load high word
+ // lis r_dst, (imm>>48) & 0xFFFF
+ p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF);
+
+ // ori r_dst, r_dst, (imm>>32) & 0xFFFF
+ p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF);
+
+ // shift r_dst low word to high word => rldicr
+ p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1);
+
+ // load low word
+ // oris r_dst, r_dst, (imm>>16) & 0xFFFF
+ p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF);
+
+ // ori r_dst, r_dst, (imm) & 0xFFFF
+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF);
+ }
+ return p;
+}
+
+/* Checks whether the sequence of bytes at p was indeed created
+ by mkLoadImm_EXACTLY2or5 with the given parameters. */
+static Bool isLoadImm_EXACTLY2or5 ( UChar* p_to_check,
+ UInt r_dst, ULong imm, Bool mode64 )
+{
+ vassert(r_dst < 0x20);
+
+ if (!mode64) {
+ /* In 32-bit mode, make sure the top 32 bits of imm are a sign
+ extension of the bottom 32 bits. (Probably unnecessary.) */
+ UInt u32 = (UInt)imm;
+ Int s32 = (Int)u32;
+ Long s64 = (Long)s32;
+ imm = (ULong)s64;
+ }
+
+ if (!mode64) {
+ UInt expect[2] = { 0, 0 };
+ UChar* p = (UChar*)&expect[0];
+ // addis r_dst,r0,(imm>>16) => lis r_dst, (imm>>16)
+ p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF);
+ // ori r_dst, r_dst, (imm & 0xFFFF)
+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF);
+ vassert(p == (UChar*)&expect[2]);
+
+ return fetch32(p_to_check + 0) == expect[0]
+ && fetch32(p_to_check + 4) == expect[1];
+
+ } else {
+ UInt expect[5] = { 0, 0, 0, 0, 0 };
+ UChar* p = (UChar*)&expect[0];
+ // full 64bit immediate load: 5 (five!) insns.
+
+ // load high word
+ // lis r_dst, (imm>>48) & 0xFFFF
+ p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF);
+
+ // ori r_dst, r_dst, (imm>>32) & 0xFFFF
+ p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF);
+
+ // shift r_dst low word to high word => rldicr
+ p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1);
+
+ // load low word
+ // oris r_dst, r_dst, (imm>>16) & 0xFFFF
+ p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF);
+
+ // ori r_dst, r_dst, (imm) & 0xFFFF
+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF);
+
+ vassert(p == (UChar*)&expect[5]);
+
+ return fetch32(p_to_check + 0) == expect[0]
+ && fetch32(p_to_check + 4) == expect[1]
+ && fetch32(p_to_check + 8) == expect[2]
+ && fetch32(p_to_check + 12) == expect[3]
+ && fetch32(p_to_check + 16) == expect[4];
+ }
+}
+
+
+/* Generate a machine-word sized load or store. Simplified version of
+ the Pin_Load and Pin_Store cases below. */
+static UChar* do_load_or_store_machine_word (
+ UChar* p, Bool isLoad,
+ UInt reg, PPCAMode* am, Bool mode64 )
+{
+ if (isLoad) {
+ UInt opc1, sz = mode64 ? 8 : 4;
+ switch (am->tag) {
+ case Pam_IR:
+ if (mode64) {
+ vassert(0 == (am->Pam.IR.index & 3));
+ }
+ switch (sz) {
+ case 4: opc1 = 32; vassert(!mode64); break;
+ case 8: opc1 = 58; vassert(mode64); break;
+ default: vassert(0);
+ }
+ p = doAMode_IR(p, opc1, reg, am, mode64);
+ break;
+ case Pam_RR:
+ /* we could handle this case, but we don't expect to ever
+ need to. */
+ vassert(0);
+ default:
+ vassert(0);
+ }
+ } else /*store*/ {
+ UInt opc1, sz = mode64 ? 8 : 4;
+ switch (am->tag) {
+ case Pam_IR:
+ if (mode64) {
+ vassert(0 == (am->Pam.IR.index & 3));
+ }
+ switch (sz) {
+ case 4: opc1 = 36; vassert(!mode64); break;
+ case 8: opc1 = 62; vassert(mode64); break;
+ default: vassert(0);
+ }
+ p = doAMode_IR(p, opc1, reg, am, mode64);
+ break;
+ case Pam_RR:
+ /* we could handle this case, but we don't expect to ever
+ need to. */
+ vassert(0);
+ default:
+ vassert(0);
+ }
+ }
+ return p;
+}
+
+/* Generate a 32-bit sized load or store. Simplified version of
+ do_load_or_store_machine_word above. */
+static UChar* do_load_or_store_word32 (
+ UChar* p, Bool isLoad,
+ UInt reg, PPCAMode* am, Bool mode64 )
+{
+ if (isLoad) {
+ UInt opc1;
+ switch (am->tag) {
+ case Pam_IR:
+ if (mode64) {
+ vassert(0 == (am->Pam.IR.index & 3));
+ }
+ opc1 = 32;
+ p = doAMode_IR(p, opc1, reg, am, mode64);
+ break;
+ case Pam_RR:
+ /* we could handle this case, but we don't expect to ever
+ need to. */
+ vassert(0);
+ default:
+ vassert(0);
+ }
+ } else /*store*/ {
+ UInt opc1;
+ switch (am->tag) {
+ case Pam_IR:
+ if (mode64) {
+ vassert(0 == (am->Pam.IR.index & 3));
+ }
+ opc1 = 36;
+ p = doAMode_IR(p, opc1, reg, am, mode64);
+ break;
+ case Pam_RR:
+ /* we could handle this case, but we don't expect to ever
+ need to. */
+ vassert(0);
+ default:
+ vassert(0);
+ }
+ }
+ return p;
+}
+
/* Move r_dst to r_src */
static UChar* mkMoveReg ( UChar* p, UInt r_dst, UInt r_src )
{
@@ -2661,18 +3535,19 @@
/* Emit an instruction into buf and return the number of bytes used.
Note that buf is not the insn's final place, and therefore it is
- imperative to emit position-independent code.
-
- Note, dispatch should always be NULL since ppc32/64 backends
- use a call-return scheme to get from the dispatcher to generated
- code and back.
+ imperative to emit position-independent code. If the emitted
+ instruction was a profiler inc, set *is_profInc to True, else leave
+ it unchanged.
*/
-Int emit_PPCInstr ( UChar* buf, Int nbuf, PPCInstr* i,
+Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, PPCInstr* i,
Bool mode64,
- void* dispatch_unassisted, void* dispatch_assisted )
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted )
{
UChar* p = &buf[0];
- UChar* ptmp = p;
vassert(nbuf >= 32);
if (0) {
@@ -3039,6 +3914,7 @@
getRegUsage_PPCInstr above, %r10 is used as an address temp */
/* jump over the following insns if condition does not hold */
+ UChar* ptmp = NULL;
if (cond.test != Pct_ALWAYS) {
/* jmp fwds if !condition */
/* don't know how many bytes to jump over yet...
@@ -3067,76 +3943,176 @@
goto done;
}
- case Pin_Goto: {
- UInt trc = 0;
- UChar r_ret = 3; /* Put target addr into %r3 */
- PPCCondCode cond = i->Pin.Goto.cond;
- UInt r_dst;
- ULong imm_dst;
+ case Pin_XDirect: {
+ /* NB: what goes on here has to be very closely coordinated
+ with the chainXDirect_PPC and unchainXDirect_PPC below. */
+ /* We're generating chain-me requests here, so we need to be
+ sure this is actually allowed -- no-redir translations
+ can't use chain-me's. Hence: */
+ vassert(disp_cp_chain_me_to_slowEP != NULL);
+ vassert(disp_cp_chain_me_to_fastEP != NULL);
- vassert(dispatch_unassisted == NULL);
- vassert(dispatch_assisted == NULL);
-
- /* First off, if this is conditional, create a conditional
- jump over the rest of it. */
- if (cond.test != Pct_ALWAYS) {
- /* jmp fwds if !condition */
- /* don't know how many bytes to jump over yet...
- make space for a jump instruction and fill in later. */
- ptmp = p; /* fill in this bit later */
+ /* First off, if this is conditional, create a conditional jump
+ over the rest of it. Or at least, leave a space for it that
+ we will shortly fill in. */
+ UChar* ptmp = NULL;
+ if (i->Pin.XDirect.cond.test != Pct_ALWAYS) {
+ vassert(i->Pin.XDirect.cond.flag != Pcf_NONE);
+ ptmp = p;
p += 4;
- }
-
- // cond succeeds...
-
- /* If a non-boring, set GuestStatePtr appropriately. */
- switch (i->Pin.Goto.jk) {
- case Ijk_ClientReq: trc = VEX_TRC_JMP_CLIENTREQ; break;
- case Ijk_Sys_syscall: trc = VEX_TRC_JMP_SYS_SYSCALL; break;
- case Ijk_Yield: trc = VEX_TRC_JMP_YIELD; break;
- case Ijk_YieldNoRedir: trc = VEX_TRC_JMP_YIELD_NOREDIR; break;
- case Ijk_EmWarn: trc = VEX_TRC_JMP_EMWARN; break;
- case Ijk_EmFail: trc = VEX_TRC_JMP_EMFAIL; break;
- case Ijk_MapFail: trc = VEX_TRC_JMP_MAPFAIL; break;
- case Ijk_NoDecode: trc = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval: trc = VEX_TRC_JMP_TINVAL; break;
- case Ijk_NoRedir: trc = VEX_TRC_JMP_NOREDIR; break;
- case Ijk_SigTRAP: trc = VEX_TRC_JMP_SIGTRAP; break;
- case Ijk_SigBUS: trc = VEX_TRC_JMP_SIGBUS; break;
- case Ijk_Ret:
- case Ijk_Call:
- case Ijk_Boring:
- break;
- default:
- ppIRJumpKind(i->Pin.Goto.jk);
- vpanic("emit_PPCInstr.Pin_Goto: unknown jump kind");
- }
- if (trc !=0) {
- vassert(trc < 0x10000);
- /* addi r31,0,trc */
- p = mkFormD(p, 14, 31, 0, trc); // p += 4
- }
-
- /* Get the destination address into %r_ret */
- if (i->Pin.Goto.dst->tag == Pri_Imm) {
- imm_dst = i->Pin.Goto.dst->Pri.Imm;
- p = mkLoadImm(p, r_ret, imm_dst, mode64); // p += 4|8|20
} else {
- vassert(i->Pin.Goto.dst->tag == Pri_Reg);
- r_dst = iregNo(i->Pin.Goto.dst->Pri.Reg, mode64);
- p = mkMoveReg(p, r_ret, r_dst); // p += 4
+ vassert(i->Pin.XDirect.cond.flag == Pcf_NONE);
}
-
- /* blr */
- p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 16, 0); // p += 4
+
+ /* Update the guest CIA. */
+ /* imm32/64 r30, dstGA */
+ if (!mode64) vassert(0 == (((ULong)i->Pin.XDirect.dstGA) >> 32));
+ p = mkLoadImm(p, /*r*/30, (ULong)i->Pin.XDirect.dstGA, mode64);
+ /* stw/std r30, amCIA */
+ p = do_load_or_store_machine_word(
+ p, False/*!isLoad*/,
+ /*r*/30, i->Pin.XDirect.amCIA, mode64
+ );
+
+ /* --- FIRST PATCHABLE BYTE follows --- */
+ /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're calling
+ to) backs up the return address, so as to find the address of
+ the first patchable byte. So: don't change the number of
+ instructions (32-bit: 4, 64-bit: 7) below. */
+ /* imm32/64-fixed r30, VG_(disp_cp_chain_me_to_{slowEP,fastEP} */
+ void* disp_cp_chain_me
+ = i->Pin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
+ : disp_cp_chain_me_to_slowEP;
+ p = mkLoadImm_EXACTLY2or5(
+ p, /*r*/30, Ptr_to_ULong(disp_cp_chain_me), mode64);
+ /* mtctr r30 */
+ p = mkFormXFX(p, /*r*/30, 9, 467);
+ /* bctrl */
+ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 1);
+ /* --- END of PATCHABLE BYTES --- */
/* Fix up the conditional jump, if there was one. */
- if (cond.test != Pct_ALWAYS) {
+ if (i->Pin.XDirect.cond.test != Pct_ALWAYS) {
Int delta = p - ptmp;
- vassert(delta >= 12 && delta <= 32);
+ vassert(delta >= 16 && delta <= 64 && 0 == (delta & 3));
/* bc !ct,cf,delta */
- mkFormB(ptmp, invertCondTest(cond.test),
- cond.flag, delta>>2, 0, 0);
+ mkFormB(ptmp, invertCondTest(i->Pin.XDirect.cond.test),
+ i->Pin.XDirect.cond.flag, (delta>>2), 0, 0);
+ }
+ goto done;
+ }
+
+ case Pin_XIndir: {
+ /* We're generating transfers that could lead indirectly to a
+ chain-me, so we need to be sure this is actually allowed --
+ no-redir translations are not allowed to reach normal
+ translations without going through the scheduler. That means
+ no XDirects or XIndirs out from no-redir translations.
+ Hence: */
+ vassert(disp_cp_xindir != NULL);
+
+ /* First off, if this is conditional, create a conditional jump
+ over the rest of it. Or at least, leave a space for it that
+ we will shortly fill in. */
+ UChar* ptmp = NULL;
+ if (i->Pin.XIndir.cond.test != Pct_ALWAYS) {
+ vassert(i->Pin.XIndir.cond.flag != Pcf_NONE);
+ ptmp = p;
+ p += 4;
+ } else {
+ vassert(i->Pin.XIndir.cond.flag == Pcf_NONE);
+ }
+
+ /* Update the guest CIA. */
+ /* stw/std r-dstGA, amCIA */
+ p = do_load_or_store_machine_word(
+ p, False/*!isLoad*/,
+ iregNo(i->Pin.XIndir.dstGA, mode64),
+ i->Pin.XIndir.amCIA, mode64
+ );
+
+ /* imm32/64 r30, VG_(disp_cp_xindir) */
+ p = mkLoadImm(p, /*r*/30, (ULong)Ptr_to_ULong(disp_cp_xindir), mode64);
+ /* mtctr r30 */
+ p = mkFormXFX(p, /*r*/30, 9, 467);
+ /* bctr */
+ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0);
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->Pin.XIndir.cond.test != Pct_ALWAYS) {
+ Int delta = p - ptmp;
+ vassert(delta >= 16 && delta <= 32 && 0 == (delta & 3));
+ /* bc !ct,cf,delta */
+ mkFormB(ptmp, invertCondTest(i->Pin.XIndir.cond.test),
+ i->Pin.XIndir.cond.flag, (delta>>2), 0, 0);
+ }
+ goto done;
+ }
+
+ case Pin_XAssisted: {
+ /* First off, if this is conditional, create a conditional jump
+ over the rest of it. Or at least, leave a space for it that
+ we will shortly fill in. */
+ UChar* ptmp = NULL;
+ if (i->Pin.XAssisted.cond.test != Pct_ALWAYS) {
+ vassert(i->Pin.XAssisted.cond.flag != Pcf_NONE);
+ ptmp = p;
+ p += 4;
+ } else {
+ vassert(i->Pin.XAssisted.cond.flag == Pcf_NONE);
+ }
+
+ /* Update the guest CIA. */
+ /* stw/std r-dstGA, amCIA */
+ p = do_load_or_store_machine_word(
+ p, False/*!isLoad*/,
+ iregNo(i->Pin.XIndir.dstGA, mode64),
+ i->Pin.XIndir.amCIA, mode64
+ );
+
+ /* imm32/64 r31, $magic_number */
+ UInt trcval = 0;
+ switch (i->Pin.XAssisted.jk) {
+ case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break;
+ case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break;
+ //case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break;
+ //case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break;
+ case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
+ case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break;
+ //case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
+ case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
+ case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
+ case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
+ //case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
+ case Ijk_SigBUS: trcval = VEX_TRC_JMP_SIGBUS; break;
+ case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break;
+ /* We don't expect to see the following being assisted. */
+ //case Ijk_Ret:
+ //case Ijk_Call:
+ /* fallthrough */
+ default:
+ ppIRJumpKind(i->Pin.XAssisted.jk);
+ vpanic("emit_ARMInstr.Pin_XAssisted: unexpected jump kind");
+ }
+ vassert(trcval != 0);
+ p = mkLoadImm(p, /*r*/31, trcval, mode64);
+
+ /* imm32/64 r30, VG_(disp_cp_xassisted) */
+ p = mkLoadImm(p, /*r*/30,
+ (ULong)Ptr_to_ULong(disp_cp_xassisted), mode64);
+ /* mtctr r30 */
+ p = mkFormXFX(p, /*r*/30, 9, 467);
+ /* bctr */
+ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0);
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->Pin.XAssisted.cond.test != Pct_ALWAYS) {
+ Int delta = p - ptmp;
+ vassert(delta >= 16 && delta <= 32 && 0 == (delta & 3));
+ /* bc !ct,cf,delta */
+ mkFormB(ptmp, invertCondTest(i->Pin.XAssisted.cond.test),
+ i->Pin.XAssisted.cond.flag, (delta>>2), 0, 0);
}
goto done;
}
@@ -3151,6 +4127,7 @@
cond = i->Pin.CMov.cond;
/* branch (if cond fails) over move instrs */
+ UChar* ptmp = NULL;
if (cond.test != Pct_ALWAYS) {
/* don't know how many bytes to jump over yet...
make space for a jump instruction and fill in later. */
@@ -3534,7 +4511,7 @@
case Pin_FpLdFPSCR: {
UInt fr_src = fregNo(i->Pin.FpLdFPSCR.src);
- p = mkFormXFL(p, 0xFF, fr_src); // mtfsf, PPC32 p480
+ p = mkFormXFL(p, 0xFF, fr_src, i->Pin.FpLdFPSCR.dfp_rm); // mtfsf, PPC32 p480
goto done;
}
@@ -3951,6 +4928,532 @@
goto done;
}
+ case Pin_Dfp64Unary: {
+ UInt fr_dst = fregNo( i->Pin.FpUnary.dst );
+ UInt fr_src = fregNo( i->Pin.FpUnary.src );
+
+ switch (i->Pin.Dfp64Unary.op) {
+ case Pfp_MOV: // fmr, PPC32 p410
+ p = mkFormX( p, 63, fr_dst, 0, fr_src, 72, 0 );
+ break;
+ case Pfp_DCTDP: // D32 to D64
+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 258, 0 );
+ break;
+ case Pfp_DRSP: // D64 to D32
+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 770, 0 );
+ break;
+ case Pfp_DCFFIX: // I64 to D64 conversion
+ /* ONLY WORKS ON POWER7 */
+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 802, 0);
+ break;
+ case Pfp_DCTFIX: // D64 to I64 conversion
+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 290, 0);
+ break;
+ case Pfp_DXEX: // Extract exponent
+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 354, 0 );
+ break;
+ default:
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Pin_Dfp64Binary: {
+ UInt fr_dst = fregNo( i->Pin.Dfp64Binary.dst );
+ UInt fr_srcL = fregNo( i->Pin.Dfp64Binary.srcL );
+ UInt fr_srcR = fregNo( i->Pin.Dfp64Binary.srcR );
+ switch (i->Pin.Dfp64Binary.op) {
+ case Pfp_DFPADD: /* dadd, dfp add, use default RM from reg ignore mode
+ * from the Iop instruction. */
+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 2, 0 );
+ break;
+ case Pfp_DFPSUB: /* dsub, dfp subtract, use default RM from reg ignore
+ * mode from the Iop instruction. */
+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 514, 0 );
+ break;
+ case Pfp_DFPMUL: /* dmul, dfp multipy, use default RM from reg ignore
+ * mode from the Iop instruction. */
+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 34, 0 );
+ break;
+ case Pfp_DFPDIV: /* ddiv, dfp divide, use default RM from reg ignore
+ * mode from the Iop instruction. */
+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 546, 0 );
+ break;
+ case Pfp_DIEX: /* diex, insert exponent */
+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 866, 0 );
+ break;
+ default:
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Pin_DfpShift: {
+ UInt fr_src = fregNo(i->Pin.DfpShift.src);
+ UInt fr_dst = fregNo(i->Pin.DfpShift.dst);
+ UInt shift;
+
+ shift = i->Pin.DfpShift.shift->Pri.Imm;
+
+ switch (i->Pin.DfpShift.op) {
+ case Pfp_DSCLI: /* dscli, DFP shift left by fr_srcR */
+ p = mkFormZ22( p, 59, fr_dst, fr_src, shift, 66, 0 );
+ break;
+ case Pfp_DSCRI: /* dscri, DFP shift right by fr_srcR */
+ p = mkFormZ22( p, 59, fr_dst, fr_src, shift, 98, 0 );
+ break;
+ default:
+ vex_printf("ERROR: emit_PPCInstr default case\n");
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Pin_ExtractExpD128: {
+ UInt fr_dst = fregNo(i->Pin.ExtractExpD128.dst);
+ UInt fr_srcHi = fregNo(i->Pin.ExtractExpD128.src_hi);
+ UInt fr_srcLo = fregNo(i->Pin.ExtractExpD128.src_lo);
+
+ switch (i->Pin.ExtractExpD128.op) {
+ case Pfp_DXEXQ:
+ /* Setup the upper and lower registers of the source operand
+ * register pair.
+ */
+ p = mkFormX( p, 63, 12, 0, fr_srcHi, 72, 0);
+ p = mkFormX( p, 63, 13, 0, fr_srcLo, 72, 0);
+ p = mkFormX( p, 63, 10, 0, 12, 354, 0 );
+
+ /* The instruction will put the 64-bit result in
+ * register 10.
+ */
+ p = mkFormX(p, 63, fr_dst, 0, 10, 72, 0);
+ break;
+ default:
+ vex_printf("Error: emit_PPCInstr case Pin_DfpExtractExp, case inst Default\n");
+ goto bad;
+ }
+ goto done;
+ }
+ case Pin_Dfp128Unary: {
+ UInt fr_dstHi = fregNo(i->Pin.Dfp128Unary.dst_hi);
+ UInt fr_dstLo = fregNo(i->Pin.Dfp128Unary.dst_lo);
+ UInt fr_srcLo = fregNo(i->Pin.Dfp128Unary.src_lo);
+
+ /* Do instruction with 128-bit source operands in registers (10,11)
+ * and (12,13).
+ */
+ switch (i->Pin.Dfp128Unary.op) {
+ case Pfp_DCTQPQ: // D64 to D128, srcLo holds 64 bit operand
+ p = mkFormX( p, 63, 12, 0, fr_srcLo, 72, 0);
+
+ p = mkFormX( p, 63, 10, 0, 12, 258, 0 );
+
+ /* The instruction will put the 128-bit result in
+ * registers (10,11). Note, the operand in the instruction only
+ * reference the first of the two registers in the pair.
+ */
+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0);
+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0);
+ break;
+ default:
+ vex_printf("Error: emit_PPCInstr case Pin_Dfp128Unary, case inst Default\
+\n");
+ goto bad;
+ }
+ goto done;
+ }
+
+ case Pin_Dfp128Binary: {
+ /* dst is used to supply the left source operand and return
+ * the result.
+ */
+ UInt fr_dstHi = fregNo( i->Pin.Dfp128Binary.dst_hi );
+ UInt fr_dstLo = fregNo( i->Pin.Dfp128Binary.dst_lo );
+ UInt fr_srcRHi = fregNo( i->Pin.Dfp128Binary.srcR_hi );
+ UInt fr_srcRLo = fregNo( i->Pin.Dfp128Binary.srcR_lo );
+
+ /* Setup the upper and lower registers of the source operand
+ * register pair.
+ */
+ p = mkFormX( p, 63, 10, 0, fr_dstHi, 72, 0 );
+ p = mkFormX( p, 63, 11, 0, fr_dstLo, 72, 0 );
+ p = mkFormX( p, 63, 12, 0, fr_srcRHi, 72, 0 );
+ p = mkFormX( p, 63, 13, 0, fr_srcRLo, 72, 0 );
+
+ /* Do instruction with 128-bit source operands in registers (10,11)
+ * and (12,13).
+ */
+ switch (i->Pin.Dfp128Binary.op) {
+ case Pfp_DFPADDQ:
+ p = mkFormX( p, 63, 10, 10, 12, 2, 0 );
+ break;
+ case Pfp_DFPSUBQ:
+ p = mkFormX( p, 63, 10, 10, 12, 514, 0 );
+ break;
+ case Pfp_DFPMULQ:
+ p = mkFormX( p, 63, 10, 10, 12, 34, 0 );
+ break;
+ case Pfp_DFPDIVQ:
+ p = mkFormX( p, 63, 10, 10, 12, 546, 0 );
+ break;
+ default:
+ goto bad;
+ }
+
+ /* The instruction will put the 128-bit result in
+ * registers (10,11). Note, the operand in the instruction only
+ * reference the first of the two registers in the pair.
+ */
+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0);
+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0);
+ goto done;
+ }
+
+ case Pin_DfpShift128: {
+ UInt fr_src_hi = fregNo(i->Pin.DfpShift128.src_hi);
+ UInt fr_src_lo = fregNo(i->Pin.DfpShift128.src_lo);
+ UInt fr_dst_hi = fregNo(i->Pin.DfpShift128.dst_hi);
+ UInt fr_dst_lo = fregNo(i->Pin.DfpShift128.dst_lo);
+ UInt shift;
+
+ shift = i->Pin.DfpShift128.shift->Pri.Imm;
+
+ /* setup source operand in register 12, 13 pair */
+ p = mkFormX(p, 63, 12, 0, fr_src_hi, 72, 0);
+ p = mkFormX(p, 63, 13, 0, fr_src_lo, 72, 0);
+
+ /* execute instruction putting result in register 10, 11 pair */
+ switch (i->Pin.DfpShift128.op) {
+ case Pfp_DSCLIQ: /* dscliq, DFP shift left, fr_srcR is the integer
+ * shift amount.
+ */
+ p = mkFormZ22( p, 63, 10, 12, shift, 66, 0 );
+ break;
+ case Pfp_DSCRIQ: /* dscriq, DFP shift right, fr_srcR is the integer
+ * shift amount.
+ */
+ p = mkFormZ22( p, 63, 10, 12, shift, 98, 0 );
+ break;
+ default:
+ vex_printf("ERROR: emit_PPCInstr quad default case %d \n",
+ i->Pin.DfpShift128.op);
+ goto bad;
+ }
+
+ /* The instruction put the 128-bit result in registers (10,11).
+ * Note, the operand in the instruction only reference the first of
+ * the two registers in the pair.
+ */
+ p = mkFormX(p, 63, fr_dst_hi, 0, 10, 72, 0);
+ p = mkFormX(p, 63, fr_dst_lo, 0, 11, 72, 0);
+ goto done;
+ }
+
+ case Pin_DfpRound: {
+ UInt fr_dst = fregNo(i->Pin.DfpRound.dst);
+ UInt fr_src = fregNo(i->Pin.DfpRound.src);
+ UInt r_rmc, r, rmc;
+
+ r_rmc = i->Pin.DfpRound.r_rmc->Pri.Imm;
+ r = (r_rmc & 0x8) >> 3;
+ rmc = r_rmc & 0x3;
+
+ // drintx
+ p = mkFormZ23(p, 59, fr_dst, r, fr_src, rmc, 99, 0);
+ goto done;
+ }
+
+ case Pin_DfpRound128: {
+ UInt fr_dstHi = fregNo(i->Pin.DfpRound128.dst_hi);
+ UInt fr_dstLo = fregNo(i->Pin.DfpRound128.dst_lo);
+ UInt fr_srcHi = fregNo(i->Pin.DfpRound128.src_hi);
+ UInt fr_srcLo = fregNo(i->Pin.DfpRound128.src_lo);
+ UInt r_rmc, r, rmc;
+
+ r_rmc = i->Pin.DfpRound128.r_rmc->Pri.Imm;
+ r = (r_rmc & 0x8) >> 3;
+ rmc = r_rmc & 0x3;
+
+ /* Setup the upper and lower registers of the source operand
+ * register pair.
+ */
+ p = mkFormX(p, 63, 12, 0, fr_srcHi, 72, 0);
+ p = mkFormX(p, 63, 13, 0, fr_srcLo, 72, 0);
+
+ /* Do drintx instruction with 128-bit source operands in
+ * registers (12,13).
+ */
+ p = mkFormZ23(p, 63, 10, r, 12, rmc, 99, 0);
+
+ /* The instruction will put the 128-bit result in
+ * registers (10,11). Note, the operand in the instruction only
+ * reference the first of the two registers in the pair.
+ */
+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0);
+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0);
+ goto done;
+ }
+
+ case Pin_DfpQuantize: {
+ UInt fr_dst = fregNo(i->Pin.DfpQuantize.dst);
+ UInt fr_srcL = fregNo(i->Pin.DfpQuantize.srcL);
+ UInt fr_srcR = fregNo(i->Pin.DfpQuantize.srcR);
+ UInt rmc;
+
+ rmc = i->Pin.DfpQuantize.rmc->Pri.Imm;
+
+ switch (i->Pin.DfpQuantize.op) {
+ case Pfp_DQUA:
+ p = mkFormZ23(p, 59, fr_dst, fr_srcL, fr_srcR, rmc, 3, 0);
+ break;
+ case Pfp_RRDTR:
+ p = mkFormZ23(p, 59, fr_dst, fr_srcL, fr_srcR, rmc, 35, 0);
+ break;
+ default:
+ break;
+ }
+ goto done;
+ }
+
+ case Pin_DfpQuantize128: {
+ UInt fr_dst_hi = fregNo(i->Pin.DfpQuantize128.dst_hi);
+ UInt fr_dst_lo = fregNo(i->Pin.DfpQuantize128.dst_lo);
+ UInt fr_src_hi = fregNo(i->Pin.DfpQuantize128.src_hi);
+ UInt fr_src_lo = fregNo(i->Pin.DfpQuantize128.src_lo);
+ UInt rmc;
+
+ rmc = i->Pin.DfpQuantize128.rmc->Pri.Imm;
+ /* Setup the upper and lower registers of the source operand
+ * register pairs. Note, left source operand passed in via the
+ * dst register pair.
+ */
+ p = mkFormX(p, 63, 10, 0, fr_dst_hi, 72, 0);
+ p = mkFormX(p, 63, 11, 0, fr_dst_lo, 72, 0);
+ p = mkFormX(p, 63, 12, 0, fr_src_hi, 72, 0);
+ p = mkFormX(p, 63, 13, 0, fr_src_lo, 72, 0);
+
+ /* Do dquaq instruction with 128-bit source operands in
+ * registers (12,13).
+ */
+ switch (i->Pin.DfpQuantize128.op) {
+ case Pfp_DQUAQ:
+ p = mkFormZ23(p, 63, 10, 10, 12, rmc, 3, 0);
+ break;
+ case Pfp_DRRNDQ:
+ p = mkFormZ23(p, 63, 10, 10, 12, rmc, 35, 0);
+ break;
+ default:
+ vpanic("Pin_DfpQuantize128: default case, couldn't find inst to issue \n");
+ break;
+ }
+
+ /* The instruction will put the 128-bit result in
+ * registers (10,11). Note, the operand in the instruction only
+ * reference the first of the two registers in the pair.
+ */
+ p = mkFormX(p, 63, fr_dst_hi, 0, 10, 72, 0);
+ p = mkFormX(p, 63, fr_dst_lo, 0, 11, 72, 0);
+ goto done;
+ }
+
+ case Pin_DfpD128toD64: {
+ UInt fr_dst = fregNo( i->Pin.DfpD128toD64.dst );
+ UInt fr_srcHi = fregNo( i->Pin.DfpD128toD64.src_hi );
+ UInt fr_srcLo = fregNo( i->Pin.DfpD128toD64.src_lo );
+
+ /* Setup the upper and lower registers of the source operand
+ * register pair.
+ */
+ p = mkFormX( p, 63, 10, 0, fr_dst, 72, 0 );
+ p = mkFormX( p, 63, 12, 0, fr_srcHi, 72, 0 );
+ p = mkFormX( p, 63, 13, 0, fr_srcLo, 72, 0 );
+
+ /* Do instruction with 128-bit source operands in registers (10,11) */
+ switch (i->Pin.Dfp128Binary.op) {
+ case Pfp_DRDPQ:
+ p = mkFormX( p, 63, 10, 0, 12, 770, 0 );
+ break;
+ case Pfp_DCTFIXQ:
+ p = mkFormX( p, 63, 10, 0, 12, 290, 0 );
+ break;
+ default:
+ goto bad;
+ }
+
+ /* The instruction will put the 64-bit result in registers 10. */
+ p = mkFormX(p, 63, fr_dst, 0, 10, 72, 0);
+ goto done;
+ }
+
+ case Pin_DfpI64StoD128: {
+ UInt fr_dstHi = fregNo( i->Pin.DfpI64StoD128.dst_hi );
+ UInt fr_dstLo = fregNo( i->Pin.DfpI64StoD128.dst_lo );
+ UInt fr_src = fregNo( i->Pin.DfpI64StoD128.src );
+
+ switch (i->Pin.Dfp128Binary.op) {
+ case Pfp_DCFFIXQ:
+ p = mkFormX( p, 63, 10, 11, fr_src, 802, 0 );
+ break;
+ default:
+ goto bad;
+ }
+
+ /* The instruction will put the 64-bit result in registers 10, 11. */
+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0);
+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0);
+ goto done;
+ }
+
+ case Pin_InsertExpD128: {
+ UInt fr_dstHi = fregNo(i->Pin.InsertExpD128.dst_hi);
+ UInt fr_dstLo = fregNo(i->Pin.InsertExpD128.dst_lo);
+ UInt fr_srcL = fregNo(i->Pin.InsertExpD128.srcL);
+ UInt fr_srcRHi = fregNo(i->Pin.InsertExpD128.srcR_hi);
+ UInt fr_srcRLo = fregNo(i->Pin.InsertExpD128.srcR_lo);
+
+ /* The left operand is a single F64 value, the right is an F128
+ * register pair.
+ */
+ p = mkFormX(p, 63, 10, 0, fr_srcL, 72, 0);
+ p = mkFormX(p, 63, 12, 0, fr_srcRHi, 72, 0);
+ p = mkFormX(p, 63, 13, 0, fr_srcRLo, 72, 0);
+ p = mkFormX(p, 63, 10, 10, 12, 866, 0 );
+
+ /* The instruction will put the 128-bit result into
+ * registers (10,11). Note, the operand in the instruction only
+ * reference the first of the two registers in the pair.
+ */
+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0);
+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0);
+ goto done;
+ }
+
+ case Pin_Dfp64Cmp:{
+ UChar crfD = 1;
+ UInt r_dst = iregNo(i->Pin.Dfp64Cmp.dst, mode64);
+ UInt fr_srcL = fregNo(i->Pin.Dfp64Cmp.srcL);
+ UInt fr_srcR = fregNo(i->Pin.Dfp64Cmp.srcR);
+ vassert(crfD < 8);
+ // dcmpo, dcmpu
+ p = mkFormX(p, 59, crfD<<2, fr_srcL, fr_srcR, 130, 0);
+
+ // mfcr (mv CR to r_dst)
+ p = mkFormX(p, 31, r_dst, 0, 0, 19, 0);
+
+ // rlwinm r_dst,r_dst,8,28,31
+ // => rotate field 1 to bottomw of word, masking out upper 28
+ p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0);
+ goto done;
+ }
+
+ case Pin_Dfp128Cmp: {
+ UChar crfD = 1;
+ UInt r_dst = iregNo(i->Pin.Dfp128Cmp.dst, mode64);
+ UInt fr_srcL_hi = fregNo(i->Pin.Dfp128Cmp.srcL_hi);
+ UInt fr_srcL_lo = fregNo(i->Pin.Dfp128Cmp.srcL_lo);
+ UInt fr_srcR_hi = fregNo(i->Pin.Dfp128Cmp.srcR_hi);
+ UInt fr_srcR_lo = fregNo(i->Pin.Dfp128Cmp.srcR_lo);
+ vassert(crfD < 8);
+ // dcmpoq, dcmpuq
+ /* Setup the upper and lower registers of the source operand
+ * register pair.
+ */
+ p = mkFormX(p, 63, 10, 0, fr_srcL_hi, 72, 0);
+ p = mkFormX(p, 63, 11, 0, fr_srcL_lo, 72, 0);
+ p = mkFormX(p, 63, 12, 0, fr_srcR_hi, 72, 0);
+ p = mkFormX(p, 63, 13, 0, fr_srcR_lo, 72, 0);
+
+ p = mkFormX(p, 63, crfD<<2, 10, 12, 130, 0);
+
+ // mfcr (mv CR to r_dst)
+ p = mkFormX(p, 31, r_dst, 0, 0, 19, 0);
+
+ // rlwinm r_dst,r_dst,8,28,31
+ // => rotate field 1 to bottomw of word, masking out upper 28
+ p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0);
+ goto done;
+ }
+
+ case Pin_EvCheck: {
+ /* This requires a 32-bit dec/test in both 32- and 64-bit
+ modes. */
+ /* We generate:
+ lwz r30, amCounter
+ addic. r30, r30, -1
+ stw r30, amCounter
+ bge nofail
+ lwz/ld r30, amFailAddr
+ mtctr r30
+ bctr
+ nofail:
+ */
+ UChar* p0 = p;
+ /* lwz r30, amCounter */
+ p = do_load_or_store_word32(p, True/*isLoad*/, /*r*/30,
+ i->Pin.EvCheck.amCounter, mode64);
+ /* addic. r30,r30,-1 */
+ p = emit32(p, 0x37DEFFFF);
+ /* stw r30, amCounter */
+ p = do_load_or_store_word32(p, False/*!isLoad*/, /*r*/30,
+ i->Pin.EvCheck.amCounter, mode64);
+ /* bge nofail */
+ p = emit32(p, 0x40800010);
+ /* lwz/ld r30, amFailAddr */
+ p = do_load_or_store_machine_word(p, True/*isLoad*/, /*r*/30,
+ i->Pin.EvCheck.amFailAddr, mode64);
+ /* mtctr r30 */
+ p = mkFormXFX(p, /*r*/30, 9, 467);
+ /* bctr */
+ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0);
+ /* nofail: */
+
+ /* Crosscheck */
+ vassert(evCheckSzB_PPC() == (UChar*)p - (UChar*)p0);
+ goto done;
+ }
+
+ case Pin_ProfInc: {
+ /* We generate:
+ (ctrP is unknown now, so use 0x65556555(65556555) in the
+ expectation that a later call to LibVEX_patchProfCtr
+ will be used to fill in the immediate fields once the
+ right value is known.)
+ 32-bit:
+ imm32-exactly r30, 0x65556555
+ lwz r29, 4(r30)
+ addic. r29, r29, 1
+ stw r29, 4(r30)
+ lwz r29, 0(r30)
+ addze r29, r29
+ stw r29, 0(r30)
+ 64-bit:
+ imm64-exactly r30, 0x6555655565556555
+ ld r29, 0(r30)
+ addi r29, r29, 1
+ std r29, 0(r30)
+ */
+ if (mode64) {
+ p = mkLoadImm_EXACTLY2or5(
+ p, /*r*/30, 0x6555655565556555ULL, True/*mode64*/);
+ p = emit32(p, 0xEBBE0000);
+ p = emit32(p, 0x3BBD0001);
+ p = emit32(p, 0xFBBE0000);
+ } else {
+ p = mkLoadImm_EXACTLY2or5(
+ p, /*r*/30, 0x65556555ULL, False/*!mode64*/);
+ p = emit32(p, 0x83BE0004);
+ p = emit32(p, 0x37BD0001);
+ p = emit32(p, 0x93BE0004);
+ p = emit32(p, 0x83BE0000);
+ p = emit32(p, 0x7FBD0194);
+ p = emit32(p, 0x93BE0000);
+ }
+ /* Tell the caller .. */
+ vassert(!(*is_profInc));
+ *is_profInc = True;
+ goto done;
+ }
+
default:
goto bad;
}
@@ -3962,10 +5465,151 @@
/*NOTREACHED*/
done:
- vassert(p - &buf[0] <= 32);
+ vassert(p - &buf[0] <= 64);
return p - &buf[0];
}
+
+/* How big is an event check? See case for Pin_EvCheck in
+ emit_PPCInstr just above. That crosschecks what this returns, so
+ we can tell if we're inconsistent. */
+Int evCheckSzB_PPC ( void )
+{
+ return 28;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange chainXDirect_PPC ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to,
+ Bool mode64 )
+{
+ /* What we're expecting to see is:
+ imm32/64-fixed r30, disp_cp_chain_me_to_EXPECTED
+ mtctr r30
+ bctrl
+ viz
+ <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5>
+ 7F C9 03 A6
+ 4E 80 04 21
+ */
+ UChar* p = (UChar*)place_to_chain;
+ vassert(0 == (3 & (HWord)p));
+ vassert(isLoadImm_EXACTLY2or5(p, /*r*/30,
+ Ptr_to_ULong(disp_cp_chain_me_EXPECTED),
+ mode64));
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x7FC903A6);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x4E800421);
+ /* And what we want to change it to is:
+ imm32/64-fixed r30, place_to_jump_to
+ mtctr r30
+ bctr
+ viz
+ <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5>
+ 7F C9 03 A6
+ 4E 80 04 20
+ The replacement has the same length as the original.
+ */
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/30,
+ Ptr_to_ULong(place_to_jump_to), mode64);
+ p = emit32(p, 0x7FC903A6);
+ p = emit32(p, 0x4E800420);
+
+ Int len = p - (UChar*)place_to_chain;
+ vassert(len == (mode64 ? 28 : 16)); /* stay sane */
+ VexInvalRange vir = {(HWord)place_to_chain, len};
+ return vir;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange unchainXDirect_PPC ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me,
+ Bool mode64 )
+{
+ /* What we're expecting to see is:
+ imm32/64-fixed r30, place_to_jump_to_EXPECTED
+ mtctr r30
+ bctr
+ viz
+ <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5>
+ 7F C9 03 A6
+ 4E 80 04 20
+ */
+ UChar* p = (UChar*)place_to_unchain;
+ vassert(0 == (3 & (HWord)p));
+ vassert(isLoadImm_EXACTLY2or5(p, /*r*/30,
+ Ptr_to_ULong(place_to_jump_to_EXPECTED),
+ mode64));
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x7FC903A6);
+ vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x4E800420);
+ /* And what we want to change it to is:
+ imm32/64-fixed r30, disp_cp_chain_me
+ mtctr r30
+ bctrl
+ viz
+ <8 or 20 bytes generated by mkLoadImm_EXACTLY2or5>
+ 7F C9 03 A6
+ 4E 80 04 21
+ The replacement has the same length as the original.
+ */
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/30,
+ Ptr_to_ULong(disp_cp_chain_me), mode64);
+ p = emit32(p, 0x7FC903A6);
+ p = emit32(p, 0x4E800421);
+
+ Int len = p - (UChar*)place_to_unchain;
+ vassert(len == (mode64 ? 28 : 16)); /* stay sane */
+ VexInvalRange vir = {(HWord)place_to_unchain, len};
+ return vir;
+}
+
+
+/* Patch the counter address into a profile inc point, as previously
+ created by the Pin_ProfInc case for emit_PPCInstr. */
+VexInvalRange patchProfInc_PPC ( void* place_to_patch,
+ ULong* location_of_counter,
+ Bool mode64 )
+{
+ UChar* p = (UChar*)place_to_patch;
+ vassert(0 == (3 & (HWord)p));
+
+ Int len = 0;
+ if (mode64) {
+ vassert(isLoadImm_EXACTLY2or5(p, /*r*/30,
+ 0x6555655565556555ULL, True/*mode64*/));
+ vassert(fetch32(p + 20) == 0xEBBE0000);
+ vassert(fetch32(p + 24) == 0x3BBD0001);
+ vassert(fetch32(p + 28) == 0xFBBE0000);
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/30,
+ Ptr_to_ULong(location_of_counter),
+ True/*mode64*/);
+ len = p - (UChar*)place_to_patch;
+ vassert(len == 20);
+ } else {
+ vassert(isLoadImm_EXACTLY2or5(p, /*r*/30,
+ 0x65556555ULL, False/*!mode64*/));
+ vassert(fetch32(p + 8) == 0x83BE0004);
+ vassert(fetch32(p + 12) == 0x37BD0001);
+ vassert(fetch32(p + 16) == 0x93BE0004);
+ vassert(fetch32(p + 20) == 0x83BE0000);
+ vassert(fetch32(p + 24) == 0x7FBD0194);
+ vassert(fetch32(p + 28) == 0x93BE0000);
+ p = mkLoadImm_EXACTLY2or5(p, /*r*/30,
+ Ptr_to_ULong(location_of_counter),
+ False/*!mode64*/);
+ len = p - (UChar*)place_to_patch;
+ vassert(len == 8);
+ }
+ VexInvalRange vir = {(HWord)place_to_patch, len};
+ return vir;
+}
+
+
/*---------------------------------------------------------------*/
/*--- end host_ppc_defs.c ---*/
/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/host_ppc_defs.h b/main/VEX/priv/host_ppc_defs.h
index 58ddb43..5be5c35 100644
--- a/main/VEX/priv/host_ppc_defs.h
+++ b/main/VEX/priv/host_ppc_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -359,16 +359,26 @@
Pfp_INVALID,
/* Ternary */
- Pfp_MADDD, Pfp_MSUBD,
- Pfp_MADDS, Pfp_MSUBS,
+ Pfp_MADDD, Pfp_MSUBD,
+ Pfp_MADDS, Pfp_MSUBS,
+ Pfp_DFPADD, Pfp_DFPADDQ,
+ Pfp_DFPSUB, Pfp_DFPSUBQ,
+ Pfp_DFPMUL, Pfp_DFPMULQ,
+ Pfp_DFPDIV, Pfp_DFPDIVQ,
+ Pfp_DQUAQ, Pfp_DRRNDQ,
/* Binary */
- Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD,
- Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS,
+ Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD,
+ Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS,
+ Pfp_DRSP, Pfp_DRDPQ, Pfp_DCTFIX, Pfp_DCTFIXQ, Pfp_DCFFIX,
+ Pfp_DQUA, Pfp_RRDTR, Pfp_DIEX, Pfp_DIEXQ,
/* Unary */
Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE,
- Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ
+ Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ,
+ Pfp_DSCLI, Pfp_DSCRI, Pfp_DSCLIQ, Pfp_DSCRIQ, Pfp_DCTDP,
+ Pfp_DCTQPQ, Pfp_DCFFIXQ, Pfp_DXEX, Pfp_DXEXQ,
+
}
PPCFpOp;
@@ -446,7 +456,9 @@
Pin_MulL, /* widening multiply */
Pin_Div, /* div */
Pin_Call, /* call to address in register */
- Pin_Goto, /* conditional/unconditional jmp to dst */
+ Pin_XDirect, /* direct transfer to GA */
+ Pin_XIndir, /* indirect transfer to GA */
+ Pin_XAssisted, /* assisted transfer to GA */
Pin_CMov, /* conditional move */
Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */
Pin_LoadL, /* load-linked (lwarx/ldarx) 32|64 bit value from mem */
@@ -485,7 +497,31 @@
Pin_AvShlDbl, /* AV shift-left double by imm */
Pin_AvSplat, /* One elem repeated throughout dst */
Pin_AvLdVSCR, /* mtvscr */
- Pin_AvCMov /* AV conditional move */
+ Pin_AvCMov, /* AV conditional move */
+ Pin_Dfp64Unary, /* DFP64 unary op */
+ Pin_Dfp128Unary, /* DFP128 unary op */
+ Pin_DfpShift, /* Decimal floating point shift by immediate value */
+ Pin_Dfp64Binary, /* DFP64 binary op */
+ Pin_Dfp128Binary, /* DFP128 binary op */
+ Pin_DfpShift128, /* 128-bit Decimal floating point shift by
+ * immediate value */
+ Pin_DfpD128toD64, /* DFP 128 to DFP 64 op */
+ Pin_DfpI64StoD128, /* DFP signed integer to DFP 128 */
+ Pin_DfpRound, /* D64 round to D64 */
+ Pin_DfpRound128, /* D128 round to D128 */
+ Pin_ExtractExpD128, /* DFP, extract 64 bit exponent */
+ Pin_InsertExpD128, /* DFP, insert 64 bit exponent and 128 bit binary
+ * significand into a DFP 128-bit value*/
+ Pin_Dfp64Cmp, /* DFP 64-bit compare, generating value into
+ * int reg */
+ Pin_Dfp128Cmp, /* DFP 128-bit compare, generating value into
+ * int reg */
+ Pin_DfpQuantize, /* D64 quantize using register value, significance
+ * round */
+ Pin_DfpQuantize128, /* D128 quantize using register value, significance
+ * round */
+ Pin_EvCheck, /* Event check */
+ Pin_ProfInc /* 64-bit profile counter increment */
}
PPCInstrTag;
@@ -577,13 +613,30 @@
Addr64 target;
UInt argiregs;
} Call;
- /* Pseudo-insn. Goto dst, on given condition (which could be
- Pct_ALWAYS). */
+ /* Update the guest CIA value, then exit requesting to chain
+ to it. May be conditional. Use of Addr64 in order to cope
+ with 64-bit hosts. */
struct {
+ Addr64 dstGA; /* next guest address */
+ PPCAMode* amCIA; /* amode in guest state for CIA */
+ PPCCondCode cond; /* can be ALWAYS */
+ Bool toFastEP; /* chain to the slow or fast point? */
+ } XDirect;
+ /* Boring transfer to a guest address not known at JIT time.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ PPCAMode* amCIA;
+ PPCCondCode cond; /* can be ALWAYS */
+ } XIndir;
+ /* Assisted transfer to a guest address, most general case.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ PPCAMode* amCIA;
+ PPCCondCode cond; /* can be ALWAYS */
IRJumpKind jk;
- PPCCondCode cond;
- PPCRI* dst;
- } Goto;
+ } XAssisted;
/* Mov src to dst on the given condition, which may not
be the bogus Pct_ALWAYS. */
struct {
@@ -685,6 +738,7 @@
/* Load FP Status & Control Register */
struct {
HReg src;
+ UInt dfp_rm;
} FpLdFPSCR;
/* Do a compare, generating result into an int register. */
struct {
@@ -782,7 +836,125 @@
struct {
HReg src;
} AvLdVSCR;
- } Pin;
+ struct {
+ PPCFpOp op;
+ HReg dst;
+ HReg src;
+ } Dfp64Unary;
+ struct {
+ PPCFpOp op;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } Dfp64Binary;
+ struct {
+ PPCFpOp op;
+ HReg dst;
+ HReg src;
+ PPCRI* shift;
+ } DfpShift;
+ struct {
+ PPCFpOp op;
+ HReg dst_hi;
+ HReg dst_lo;
+ HReg src_hi;
+ HReg src_lo;
+ } Dfp128Unary;
+ struct {
+ /* The dst is used to pass the left source operand in and return
+ * the result.
+ */
+ PPCFpOp op;
+ HReg dst_hi;
+ HReg dst_lo;
+ HReg srcR_hi;
+ HReg srcR_lo;
+ } Dfp128Binary;
+ struct {
+ PPCFpOp op;
+ HReg dst_hi;
+ HReg dst_lo;
+ HReg src_hi;
+ HReg src_lo;
+ PPCRI* shift;
+ } DfpShift128;
+ struct {
+ HReg dst;
+ HReg src;
+ PPCRI* r_rmc;
+ } DfpRound;
+ struct {
+ HReg dst_hi;
+ HReg dst_lo;
+ HReg src_hi;
+ HReg src_lo;
+ PPCRI* r_rmc;
+ } DfpRound128;
+ struct {
+ PPCFpOp op;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ PPCRI* rmc;
+ } DfpQuantize;
+ struct {
+ PPCFpOp op;
+ HReg dst_hi;
+ HReg dst_lo;
+ HReg src_hi;
+ HReg src_lo;
+ PPCRI* rmc;
+ } DfpQuantize128;
+ struct {
+ PPCFpOp op;
+ HReg dst;
+ HReg src_hi;
+ HReg src_lo;
+ } ExtractExpD128;
+ struct {
+ PPCFpOp op;
+ HReg dst_hi;
+ HReg dst_lo;
+ HReg srcL;
+ HReg srcR_hi;
+ HReg srcR_lo;
+ } InsertExpD128;
+ struct {
+ PPCFpOp op;
+ HReg dst;
+ HReg src_hi;
+ HReg src_lo;
+ } DfpD128toD64;
+ struct {
+ PPCFpOp op;
+ HReg dst_hi;
+ HReg dst_lo;
+ HReg src;
+ } DfpI64StoD128;
+ struct {
+ UChar crfD;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } Dfp64Cmp;
+ struct {
+ UChar crfD;
+ HReg dst;
+ HReg srcL_hi;
+ HReg srcL_lo;
+ HReg srcR_hi;
+ HReg srcR_lo;
+ } Dfp128Cmp;
+ struct {
+ PPCAMode* amCounter;
+ PPCAMode* amFailAddr;
+ } EvCheck;
+ struct {
+ /* No fields. The address of the counter to inc is
+ installed later, post-translation, by patching it in,
+ as it is not known at translation time. */
+ } ProfInc;
+ } Pin;
}
PPCInstr;
@@ -796,7 +968,12 @@
extern PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg );
extern PPCInstr* PPCInstr_Div ( Bool extended, Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR );
extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt );
-extern PPCInstr* PPCInstr_Goto ( IRJumpKind, PPCCondCode cond, PPCRI* dst );
+extern PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA,
+ PPCCondCode cond, Bool toFastEP );
+extern PPCInstr* PPCInstr_XIndir ( HReg dstGA, PPCAMode* amCIA,
+ PPCCondCode cond );
+extern PPCInstr* PPCInstr_XAssisted ( HReg dstGA, PPCAMode* amCIA,
+ PPCCondCode cond, IRJumpKind jk );
extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src );
extern PPCInstr* PPCInstr_Load ( UChar sz,
HReg dst, PPCAMode* src, Bool mode64 );
@@ -820,7 +997,7 @@
extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, Bool syned,
Bool dst64, HReg dst, HReg src );
extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src );
-extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src );
+extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src, Bool dfp_rm );
extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR );
extern PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr );
@@ -840,17 +1017,58 @@
extern PPCInstr* PPCInstr_AvCMov ( PPCCondCode, HReg dst, HReg src );
extern PPCInstr* PPCInstr_AvLdVSCR ( HReg src );
-extern void ppPPCInstr ( PPCInstr*, Bool mode64 );
+extern PPCInstr* PPCInstr_Dfp64Unary ( PPCFpOp op, HReg dst, HReg src );
+extern PPCInstr* PPCInstr_Dfp64Binary ( PPCFpOp op, HReg dst, HReg srcL,
+ HReg srcR );
+extern PPCInstr* PPCInstr_DfpShift ( PPCFpOp op, HReg dst, HReg src,
+ PPCRI* shift );
+extern PPCInstr* PPCInstr_Dfp128Unary ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
+ HReg srcR_hi, HReg srcR_lo );
+extern PPCInstr* PPCInstr_Dfp128Binary ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
+ HReg srcR_hi, HReg srcR_lo );
+extern PPCInstr* PPCInstr_DfpShift128 ( PPCFpOp op, HReg dst_hi, HReg src_hi,
+ HReg dst_lo, HReg src_lo,
+ PPCRI* shift );
+extern PPCInstr* PPCInstr_DfpD128toD64 ( PPCFpOp op, HReg dst,
+ HReg dst_lo, HReg src_lo);
+extern PPCInstr* PPCInstr_DfpI64StoD128 ( PPCFpOp op, HReg dst_hi,
+ HReg dst_lo, HReg src);
+extern PPCInstr* PPCInstr_DfpRound ( HReg dst, HReg src, PPCRI* r_rmc );
+extern PPCInstr* PPCInstr_DfpRound128 ( HReg dst_hi, HReg dst_lo, HReg src_hi,
+ HReg src_lo, PPCRI* r_rmc );
+extern PPCInstr* PPCInstr_DfpQuantize ( PPCFpOp op, HReg dst, HReg srcL,
+ HReg srcR, PPCRI* rmc );
+extern PPCInstr* PPCInstr_DfpQuantize128 ( PPCFpOp op, HReg dst_hi,
+ HReg dst_lo,
+ HReg src_hi,
+ HReg src_lo, PPCRI* rmc );
+extern PPCInstr* PPCInstr_ExtractExpD128 ( PPCFpOp op, HReg dst,
+ HReg src_hi, HReg src_lo );
+extern PPCInstr* PPCInstr_InsertExpD128 ( PPCFpOp op, HReg dst_hi,
+ HReg dst_lo, HReg srcL,
+ HReg srcR_hi, HReg srcR_lo );
+extern PPCInstr* PPCInstr_Dfp64Cmp ( HReg dst, HReg srcL, HReg srcR );
+extern PPCInstr* PPCInstr_Dfp128Cmp ( HReg dst, HReg srcL_hi, HReg srcL_lo,
+ HReg srcR_hi, HReg srcR_lo );
+extern PPCInstr* PPCInstr_EvCheck ( PPCAMode* amCounter,
+ PPCAMode* amFailAddr );
+extern PPCInstr* PPCInstr_ProfInc ( void );
+
+extern void ppPPCInstr(PPCInstr*, Bool mode64);
+
/* Some functions that insulate the register allocator from details
of the underlying instruction set. */
extern void getRegUsage_PPCInstr ( HRegUsage*, PPCInstr*, Bool mode64 );
extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64);
extern Bool isMove_PPCInstr ( PPCInstr*, HReg*, HReg* );
-extern Int emit_PPCInstr ( UChar* buf, Int nbuf, PPCInstr*,
+extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, PPCInstr* i,
Bool mode64,
- void* dispatch_unassisted,
- void* dispatch_assisted );
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted );
extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
HReg rreg, Int offsetB, Bool mode64 );
@@ -858,9 +1076,37 @@
HReg rreg, Int offsetB, Bool mode64 );
extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 );
-extern HInstrArray* iselSB_PPC ( IRSB*, VexArch,
- VexArchInfo*,
- VexAbiInfo* );
+extern HInstrArray* iselSB_PPC ( IRSB*,
+ VexArch,
+ VexArchInfo*,
+ VexAbiInfo*,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga );
+
+/* How big is an event check? This is kind of a kludge because it
+ depends on the offsets of host_EvC_FAILADDR and
+ host_EvC_COUNTER. */
+extern Int evCheckSzB_PPC ( void );
+
+/* Perform a chaining and unchaining of an XDirect jump. */
+extern VexInvalRange chainXDirect_PPC ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to,
+ Bool mode64 );
+
+extern VexInvalRange unchainXDirect_PPC ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me,
+ Bool mode64 );
+
+/* Patch the counter location into an existing ProfInc point. */
+extern VexInvalRange patchProfInc_PPC ( void* place_to_patch,
+ ULong* location_of_counter,
+ Bool mode64 );
+
#endif /* ndef __VEX_HOST_PPC_DEFS_H */
diff --git a/main/VEX/priv/host_ppc_isel.c b/main/VEX/priv/host_ppc_isel.c
index 642fc81..c51392d 100644
--- a/main/VEX/priv/host_ppc_isel.c
+++ b/main/VEX/priv/host_ppc_isel.c
@@ -1,4 +1,5 @@
+
/*---------------------------------------------------------------*/
/*--- begin host_ppc_isel.c ---*/
/*---------------------------------------------------------------*/
@@ -7,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -41,6 +42,7 @@
#include "main_util.h"
#include "main_globals.h"
#include "host_generic_regs.h"
+#include "host_generic_simd64.h"
#include "host_ppc_defs.h"
/* GPR register class for ppc32/64 */
@@ -218,17 +220,20 @@
- A mapping from IRTemp to HReg. This tells the insn selector
which virtual register(s) are associated with each IRTemp
- temporary. This is computed before insn selection starts, and
- does not change. We expect this mapping to map precisely the
- same set of IRTemps as the type mapping does.
+ temporary. This is computed before insn selection starts, and
+ does not change. We expect this mapping to map precisely the
+ same set of IRTemps as the type mapping does.
- - vregmap holds the primary register for the IRTemp.
- - vregmapHI holds the secondary register for the IRTemp,
+ - vregmapLo holds the primary register for the IRTemp.
+ - vregmapMedLo holds the secondary register for the IRTemp,
if any is needed. That's only for Ity_I64 temps
in 32 bit mode or Ity_I128 temps in 64-bit mode.
-
- - The name of the vreg in which we stash a copy of the link reg,
- so helper functions don't kill it.
+ - vregmapMedHi is only for dealing with Ity_I128 temps in
+ 32 bit mode. It holds bits 95:64 (Intel numbering)
+ of the IRTemp.
+ - vregmapHi is also only for dealing with Ity_I128 temps
+ in 32 bit mode. It holds the most significant bits
+ (127:96 in Intel numbering) of the IRTemp.
- The code array, that is, the insns selected so far.
@@ -247,31 +252,43 @@
described in set_FPU_rounding_mode below.
- A VexMiscInfo*, needed for knowing how to generate
- function calls for this target
+ function calls for this target.
+
+ - The maximum guest address of any guest insn in this block.
+ Actually, the address of the highest-addressed byte from any
+ insn in this block. Is set at the start and does not change.
+ This is used for detecting jumps which are definitely
+ forward-edges from this block, and therefore can be made
+ (chained) to the fast entry point of the destination, thereby
+ avoiding the destination's event check.
*/
typedef
struct {
- IRTypeEnv* type_env;
-
- HReg* vregmap;
- HReg* vregmapHI;
- Int n_vregmap;
-
- HReg savedLR;
+ /* Constant -- are set at the start and do not change. */
+ IRTypeEnv* type_env;
+ // 64-bit mode 32-bit mode
+ HReg* vregmapLo; // Low 64-bits [63:0] Low 32-bits [31:0]
+ HReg* vregmapMedLo; // high 64-bits[127:64] Next 32-bits [63:32]
+ HReg* vregmapMedHi; // unused Next 32-bits [95:64]
+ HReg* vregmapHi; // unused highest 32-bits [127:96]
+ Int n_vregmap;
- HInstrArray* code;
-
- Int vreg_ctr;
-
/* 27 Jan 06: Not currently used, but should be */
UInt hwcaps;
Bool mode64;
- IRExpr* previous_rm;
-
VexAbiInfo* vbi;
+
+ Bool chainingAllowed;
+ Addr64 max_ga;
+
+ /* These are modified as we go along. */
+ HInstrArray* code;
+ Int vreg_ctr;
+
+ IRExpr* previous_rm;
}
ISelEnv;
@@ -280,18 +297,31 @@
{
vassert(tmp >= 0);
vassert(tmp < env->n_vregmap);
- return env->vregmap[tmp];
+ return env->vregmapLo[tmp];
}
static void lookupIRTempPair ( HReg* vrHI, HReg* vrLO,
ISelEnv* env, IRTemp tmp )
{
+ vassert(tmp >= 0);
+ vassert(tmp < env->n_vregmap);
+ vassert(env->vregmapMedLo[tmp] != INVALID_HREG);
+ *vrLO = env->vregmapLo[tmp];
+ *vrHI = env->vregmapMedLo[tmp];
+}
+
+/* Only for used in 32-bit mode */
+static void lookupIRTempQuad ( HReg* vrHi, HReg* vrMedHi, HReg* vrMedLo,
+ HReg* vrLo, ISelEnv* env, IRTemp tmp )
+{
vassert(!env->mode64);
vassert(tmp >= 0);
vassert(tmp < env->n_vregmap);
- vassert(env->vregmapHI[tmp] != INVALID_HREG);
- *vrLO = env->vregmap[tmp];
- *vrHI = env->vregmapHI[tmp];
+ vassert(env->vregmapMedLo[tmp] != INVALID_HREG);
+ *vrHi = env->vregmapHi[tmp];
+ *vrMedHi = env->vregmapMedHi[tmp];
+ *vrMedLo = env->vregmapMedLo[tmp];
+ *vrLo = env->vregmapLo[tmp];
}
static void addInstr ( ISelEnv* env, PPCInstr* instr )
@@ -391,6 +421,14 @@
static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, IRType xferTy );
static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e, IRType xferTy );
+static void iselInt128Expr_to_32x4_wrk ( HReg* rHi, HReg* rMedHi,
+ HReg* rMedLo, HReg* rLo,
+ ISelEnv* env, IRExpr* e );
+static void iselInt128Expr_to_32x4 ( HReg* rHi, HReg* rMedHi,
+ HReg* rMedLo, HReg* rLo,
+ ISelEnv* env, IRExpr* e );
+
+
/* 32-bit mode ONLY: compute an I64 into a GPR pair. */
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e );
@@ -415,6 +453,15 @@
static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
+/* 64-bit mode ONLY. */
+static HReg iselDfp64Expr_wrk ( ISelEnv* env, IRExpr* e );
+static HReg iselDfp64Expr ( ISelEnv* env, IRExpr* e );
+
+/* 64-bit mode ONLY: compute an D128 into a GPR64 pair. */
+static void iselDfp128Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env,
+ IRExpr* e );
+static void iselDfp128Expr ( HReg* rHi, HReg* rLo, ISelEnv* env,
+ IRExpr* e );
/*---------------------------------------------------------*/
/*--- ISEL: Misc helpers ---*/
@@ -888,15 +935,21 @@
static HReg roundModeIRtoPPC ( ISelEnv* env, HReg r_rmIR )
{
/*
- rounding mode | PPC | IR
- ------------------------
- to nearest | 00 | 00
- to zero | 01 | 11
- to +infinity | 10 | 10
- to -infinity | 11 | 01
+ rounding mode | PPC | IR
+ -----------------------------------------------
+ to nearest, ties to even | 000 | 000
+ to zero | 001 | 011
+ to +infinity | 010 | 010
+ to -infinity | 011 | 001
+ +++++ Below are the extended rounding modes for decimal floating point +++++
+ to nearest, ties away from 0 | 100 | 100
+ to nearest, ties toward 0 | 101 | 111
+ to away from 0 | 110 | 110
+ to prepare for shorter precision | 111 | 101
*/
HReg r_rmPPC = newVRegI(env);
HReg r_tmp1 = newVRegI(env);
+ HReg r_tmp2 = newVRegI(env);
vassert(hregClass(r_rmIR) == HRcGPR(env->mode64));
@@ -909,20 +962,22 @@
addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/,
r_tmp1, r_rmIR, PPCRH_Imm(False,1)));
- addInstr(env, PPCInstr_Alu( Palu_XOR, r_tmp1, r_rmIR,
- PPCRH_Reg(r_tmp1) ));
+ addInstr( env, PPCInstr_Alu( Palu_AND,
+ r_tmp2, r_tmp1, PPCRH_Imm( False, 3 ) ) );
- addInstr(env, PPCInstr_Alu( Palu_AND, r_rmPPC, r_tmp1,
- PPCRH_Imm(False,3) ));
+ addInstr( env, PPCInstr_Alu( Palu_XOR,
+ r_rmPPC, r_rmIR, PPCRH_Reg( r_tmp2 ) ) );
return r_rmPPC;
}
/* Set the FPU's rounding mode: 'mode' is an I32-typed expression
- denoting a value in the range 0 .. 3, indicating a round mode
+ denoting a value in the range 0 .. 7, indicating a round mode
encoded as per type IRRoundingMode. Set the PPC FPSCR to have the
- same rounding.
+ same rounding. When the dfp_rm arg is True, set the decimal
+ floating point rounding mode bits (29:31); otherwise, set the
+ binary floating point rounding mode bits (62:63).
For speed & simplicity, we're setting the *entire* FPSCR here.
@@ -947,7 +1002,7 @@
on any block with any sign of floating point activity.
*/
static
-void set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode )
+void _set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode, Bool dfp_rm )
{
HReg fr_src = newVRegF(env);
HReg r_src;
@@ -972,15 +1027,40 @@
// Resolve rounding mode and convert to PPC representation
r_src = roundModeIRtoPPC( env, iselWordExpr_R(env, mode) );
+
// gpr -> fpr
if (env->mode64) {
- fr_src = mk_LoadR64toFPR( env, r_src ); // 1*I64 -> F64
+ if (dfp_rm) {
+ HReg r_tmp1 = newVRegI( env );
+ addInstr( env,
+ PPCInstr_Shft( Pshft_SHL, False/*64bit shift*/,
+ r_tmp1, r_src, PPCRH_Imm( False, 32 ) ) );
+ fr_src = mk_LoadR64toFPR( env, r_tmp1 );
+ } else {
+ fr_src = mk_LoadR64toFPR( env, r_src ); // 1*I64 -> F64
+ }
} else {
- fr_src = mk_LoadRR32toFPR( env, r_src, r_src ); // 2*I32 -> F64
+ if (dfp_rm) {
+ HReg r_zero = newVRegI( env );
+ addInstr( env, PPCInstr_LI( r_zero, 0, env->mode64 ) );
+ fr_src = mk_LoadRR32toFPR( env, r_src, r_zero );
+ } else {
+ fr_src = mk_LoadRR32toFPR( env, r_src, r_src ); // 2*I32 -> F64
+ }
}
// Move to FPSCR
- addInstr(env, PPCInstr_FpLdFPSCR( fr_src ));
+ addInstr(env, PPCInstr_FpLdFPSCR( fr_src, dfp_rm ));
+}
+
+static void set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode )
+{
+ _set_FPU_rounding_mode(env, mode, False);
+}
+
+static void set_FPU_DFP_rounding_mode ( ISelEnv* env, IRExpr* mode )
+{
+ _set_FPU_rounding_mode(env, mode, True);
}
@@ -1418,9 +1498,13 @@
return r_dst;
}
- if (e->Iex.Binop.op == Iop_CmpF64) {
- HReg fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1);
- HReg fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2);
+ if ((e->Iex.Binop.op == Iop_CmpF64) ||
+ (e->Iex.Binop.op == Iop_CmpD64) ||
+ (e->Iex.Binop.op == Iop_CmpD128)) {
+ HReg fr_srcL;
+ HReg fr_srcL_lo;
+ HReg fr_srcR;
+ HReg fr_srcR_lo;
HReg r_ccPPC = newVRegI(env);
HReg r_ccIR = newVRegI(env);
@@ -1428,7 +1512,22 @@
HReg r_ccIR_b2 = newVRegI(env);
HReg r_ccIR_b6 = newVRegI(env);
- addInstr(env, PPCInstr_FpCmp(r_ccPPC, fr_srcL, fr_srcR));
+ if (e->Iex.Binop.op == Iop_CmpF64) {
+ fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1);
+ fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_FpCmp(r_ccPPC, fr_srcL, fr_srcR));
+
+ } else if (e->Iex.Binop.op == Iop_CmpD64) {
+ fr_srcL = iselDfp64Expr(env, e->Iex.Binop.arg1);
+ fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_Dfp64Cmp(r_ccPPC, fr_srcL, fr_srcR));
+
+ } else { // e->Iex.Binop.op == Iop_CmpD128
+ iselDfp128Expr(&fr_srcL, &fr_srcL_lo, env, e->Iex.Binop.arg1);
+ iselDfp128Expr(&fr_srcR, &fr_srcR_lo, env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_Dfp128Cmp(r_ccPPC, fr_srcL, fr_srcL_lo,
+ fr_srcR, fr_srcR_lo));
+ }
/* Map compare result from PPC to IR,
conforming to CmpF64 definition. */
@@ -1698,13 +1797,16 @@
return rLo; /* similar stupid comment to the above ... */
}
break;
+ case Iop_1Uto64:
case Iop_1Uto32:
- case Iop_1Uto8: {
- HReg r_dst = newVRegI(env);
- PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
- addInstr(env, PPCInstr_Set(cond,r_dst));
- return r_dst;
- }
+ case Iop_1Uto8:
+ if ((op_unop != Iop_1Uto64) || mode64) {
+ HReg r_dst = newVRegI(env);
+ PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
+ addInstr(env, PPCInstr_Set(cond,r_dst));
+ return r_dst;
+ }
+ break;
case Iop_1Sto8:
case Iop_1Sto16:
case Iop_1Sto32: {
@@ -1882,6 +1984,76 @@
add_to_sp( env, 16 ); // Reset SP
return r_dst;
}
+ break;
+
+ case Iop_ReinterpD64asI64:
+ if (mode64) {
+ PPCAMode *am_addr;
+ HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg);
+ HReg r_dst = newVRegI(env);
+
+ sub_from_sp( env, 16 ); // Move SP down 16 bytes
+ am_addr = PPCAMode_IR( 0, StackFramePtr(mode64) );
+
+ // store as D64
+ addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
+ fr_src, am_addr ));
+ // load as Ity_I64
+ addInstr(env, PPCInstr_Load( 8, r_dst, am_addr, mode64 ));
+ add_to_sp( env, 16 ); // Reset SP
+ return r_dst;
+ }
+ break;
+
+ case Iop_BCDtoDPB: {
+ PPCCondCode cc;
+ UInt argiregs;
+ HReg argregs[1];
+ HReg r_dst = newVRegI(env);
+ Int argreg;
+ HWord* fdescr;
+
+ argiregs = 0;
+ argreg = 0;
+ argregs[0] = hregPPC_GPR3(mode64);
+
+ argiregs |= (1 << (argreg+3));
+ addInstr(env, mk_iMOVds_RR( argregs[argreg++],
+ iselWordExpr_R(env, e->Iex.Unop.arg) ) );
+
+ cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
+
+ fdescr = (HWord*)h_BCDtoDPB;
+ addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]), argiregs ) );
+
+ addInstr(env, mk_iMOVds_RR(r_dst, argregs[0]));
+ return r_dst;
+ }
+
+ case Iop_DPBtoBCD: {
+ PPCCondCode cc;
+ UInt argiregs;
+ HReg argregs[1];
+ HReg r_dst = newVRegI(env);
+ Int argreg;
+ HWord* fdescr;
+
+ argiregs = 0;
+ argreg = 0;
+ argregs[0] = hregPPC_GPR3(mode64);
+
+ argiregs |= (1 << (argreg+3));
+ addInstr(env, mk_iMOVds_RR( argregs[argreg++],
+ iselWordExpr_R(env, e->Iex.Unop.arg) ) );
+
+ cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
+
+ fdescr = (HWord*)h_DPBtoBCD;
+ addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]), argiregs ) );
+
+ addInstr(env, mk_iMOVds_RR(r_dst, argregs[0]));
+ return r_dst;
+ }
default:
break;
@@ -2449,7 +2621,7 @@
7/*cr*/, tmp,PPCRH_Imm(False,0)));
return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
} else { // mode64
- HReg r_src = iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Cmp(False/*sign*/, False/*64bit cmp*/,
7/*cr*/, r_src,PPCRH_Imm(False,0)));
return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
@@ -2566,7 +2738,6 @@
*rHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
*rLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
return;
-
default:
break;
}
@@ -2591,6 +2762,57 @@
/*--- ISEL: Integer expressions (64 bit) ---*/
/*---------------------------------------------------------*/
+/* 32-bit mode ONLY: compute a 128-bit value into a register quad */
+static void iselInt128Expr_to_32x4 ( HReg* rHi, HReg* rMedHi, HReg* rMedLo,
+ HReg* rLo, ISelEnv* env, IRExpr* e )
+{
+ vassert(!env->mode64);
+ iselInt128Expr_to_32x4_wrk(rHi, rMedHi, rMedLo, rLo, env, e);
+# if 0
+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
+# endif
+ vassert(hregClass(*rHi) == HRcInt32);
+ vassert(hregIsVirtual(*rHi));
+ vassert(hregClass(*rMedHi) == HRcInt32);
+ vassert(hregIsVirtual(*rMedHi));
+ vassert(hregClass(*rMedLo) == HRcInt32);
+ vassert(hregIsVirtual(*rMedLo));
+ vassert(hregClass(*rLo) == HRcInt32);
+ vassert(hregIsVirtual(*rLo));
+}
+
+static void iselInt128Expr_to_32x4_wrk ( HReg* rHi, HReg* rMedHi,
+ HReg* rMedLo, HReg* rLo,
+ ISelEnv* env, IRExpr* e )
+{
+ vassert(e);
+ vassert(typeOfIRExpr(env->type_env,e) == Ity_I128);
+
+ /* read 128-bit IRTemp */
+ if (e->tag == Iex_RdTmp) {
+ lookupIRTempQuad( rHi, rMedHi, rMedLo, rLo, env, e->Iex.RdTmp.tmp);
+ return;
+ }
+
+ if (e->tag == Iex_Binop) {
+
+ IROp op_binop = e->Iex.Binop.op;
+ switch (op_binop) {
+ case Iop_64HLto128:
+ iselInt64Expr(rHi, rMedHi, env, e->Iex.Binop.arg1);
+ iselInt64Expr(rMedLo, rLo, env, e->Iex.Binop.arg2);
+ return;
+ default:
+ vex_printf("iselInt128Expr_to_32x4_wrk: Binop case 0x%x not found\n",
+ op_binop);
+ break;
+ }
+ }
+
+ vex_printf("iselInt128Expr_to_32x4_wrk: e->tag 0x%x not found\n", e->tag);
+ return;
+}
+
/* 32-bit mode ONLY: compute a 64-bit value into a register pair,
which is returned as the first two parameters. As with
iselIntExpr_R, these may be either real or virtual regs; in any
@@ -2861,6 +3083,36 @@
return;
}
+ case Iop_128to64: {
+ /* Narrow, return the low 64-bit half as a 32-bit
+ * register pair */
+ HReg r_Hi = INVALID_HREG;
+ HReg r_MedHi = INVALID_HREG;
+ HReg r_MedLo = INVALID_HREG;
+ HReg r_Lo = INVALID_HREG;
+
+ iselInt128Expr_to_32x4(&r_Hi, &r_MedHi, &r_MedLo, &r_Lo,
+ env, e->Iex.Unop.arg);
+ *rHi = r_MedLo;
+ *rLo = r_Lo;
+ return;
+ }
+
+ case Iop_128HIto64: {
+ /* Narrow, return the high 64-bit half as a 32-bit
+ * register pair */
+ HReg r_Hi = INVALID_HREG;
+ HReg r_MedHi = INVALID_HREG;
+ HReg r_MedLo = INVALID_HREG;
+ HReg r_Lo = INVALID_HREG;
+
+ iselInt128Expr_to_32x4(&r_Hi, &r_MedHi, &r_MedLo, &r_Lo,
+ env, e->Iex.Unop.arg);
+ *rHi = r_Hi;
+ *rLo = r_MedHi;
+ return;
+ }
+
/* V128{HI}to64 */
case Iop_V128HIto64:
case Iop_V128to64: {
@@ -2951,6 +3203,111 @@
return;
}
+ case Iop_ReinterpD64asI64: {
+ HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg);
+ PPCAMode *am_addr0, *am_addr1;
+ HReg r_dstLo = newVRegI(env);
+ HReg r_dstHi = newVRegI(env);
+
+
+ sub_from_sp( env, 16 ); // Move SP down 16 bytes
+ am_addr0 = PPCAMode_IR( 0, StackFramePtr(False/*mode32*/) );
+ am_addr1 = PPCAMode_IR( 4, StackFramePtr(False/*mode32*/) );
+
+ // store as D64
+ addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
+ fr_src, am_addr0 ));
+
+ // load hi,lo as Ity_I32's
+ addInstr(env, PPCInstr_Load( 4, r_dstHi,
+ am_addr0, False/*mode32*/ ));
+ addInstr(env, PPCInstr_Load( 4, r_dstLo,
+ am_addr1, False/*mode32*/ ));
+ *rHi = r_dstHi;
+ *rLo = r_dstLo;
+
+ add_to_sp( env, 16 ); // Reset SP
+
+ return;
+ }
+
+ case Iop_BCDtoDPB: {
+ PPCCondCode cc;
+ UInt argiregs;
+ HReg argregs[2];
+ Int argreg;
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg tmpHi;
+ HReg tmpLo;
+ ULong target;
+ Bool mode64 = env->mode64;
+
+ argregs[0] = hregPPC_GPR3(mode64);
+ argregs[1] = hregPPC_GPR4(mode64);
+
+ argiregs = 0;
+ argreg = 0;
+
+ iselInt64Expr( &tmpHi, &tmpLo, env, e->Iex.Unop.arg );
+
+ argiregs |= ( 1 << (argreg+3 ) );
+ addInstr( env, mk_iMOVds_RR( argregs[argreg++], tmpHi ) );
+
+ argiregs |= ( 1 << (argreg+3 ) );
+ addInstr( env, mk_iMOVds_RR( argregs[argreg], tmpLo ) );
+
+ cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
+ target = toUInt( Ptr_to_ULong(h_BCDtoDPB ) );
+
+ addInstr( env, PPCInstr_Call( cc, (Addr64)target, argiregs ) );
+ addInstr( env, mk_iMOVds_RR( tHi, argregs[argreg-1] ) );
+ addInstr( env, mk_iMOVds_RR( tLo, argregs[argreg] ) );
+
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
+ case Iop_DPBtoBCD: {
+ PPCCondCode cc;
+ UInt argiregs;
+ HReg argregs[2];
+ Int argreg;
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg tmpHi;
+ HReg tmpLo;
+ ULong target;
+ Bool mode64 = env->mode64;
+
+ argregs[0] = hregPPC_GPR3(mode64);
+ argregs[1] = hregPPC_GPR4(mode64);
+
+ argiregs = 0;
+ argreg = 0;
+
+ iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg);
+
+ argiregs |= (1 << (argreg+3));
+ addInstr(env, mk_iMOVds_RR( argregs[argreg++], tmpHi ));
+
+ argiregs |= (1 << (argreg+3));
+ addInstr(env, mk_iMOVds_RR( argregs[argreg], tmpLo));
+
+ cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
+
+ target = toUInt( Ptr_to_ULong( h_DPBtoBCD ) );
+
+ addInstr(env, PPCInstr_Call( cc, (Addr64)target, argiregs ) );
+ addInstr(env, mk_iMOVds_RR(tHi, argregs[argreg-1]));
+ addInstr(env, mk_iMOVds_RR(tLo, argregs[argreg]));
+
+ *rHi = tHi;
+ *rLo = tLo;
+ return;
+ }
+
default:
break;
}
@@ -3215,7 +3572,7 @@
/* --------- OPS --------- */
if (e->tag == Iex_Qop) {
PPCFpOp fpop = Pfp_INVALID;
- switch (e->Iex.Qop.op) {
+ switch (e->Iex.Qop.details->op) {
case Iop_MAddF64: fpop = Pfp_MADDD; break;
case Iop_MAddF64r32: fpop = Pfp_MADDS; break;
case Iop_MSubF64: fpop = Pfp_MSUBD; break;
@@ -3224,10 +3581,10 @@
}
if (fpop != Pfp_INVALID) {
HReg r_dst = newVRegF(env);
- HReg r_srcML = iselDblExpr(env, e->Iex.Qop.arg2);
- HReg r_srcMR = iselDblExpr(env, e->Iex.Qop.arg3);
- HReg r_srcAcc = iselDblExpr(env, e->Iex.Qop.arg4);
- set_FPU_rounding_mode( env, e->Iex.Qop.arg1 );
+ HReg r_srcML = iselDblExpr(env, e->Iex.Qop.details->arg2);
+ HReg r_srcMR = iselDblExpr(env, e->Iex.Qop.details->arg3);
+ HReg r_srcAcc = iselDblExpr(env, e->Iex.Qop.details->arg4);
+ set_FPU_rounding_mode( env, e->Iex.Qop.details->arg1 );
addInstr(env, PPCInstr_FpMulAcc(fpop, r_dst,
r_srcML, r_srcMR, r_srcAcc));
return r_dst;
@@ -3235,8 +3592,9 @@
}
if (e->tag == Iex_Triop) {
+ IRTriop *triop = e->Iex.Triop.details;
PPCFpOp fpop = Pfp_INVALID;
- switch (e->Iex.Triop.op) {
+ switch (triop->op) {
case Iop_AddF64: fpop = Pfp_ADDD; break;
case Iop_SubF64: fpop = Pfp_SUBD; break;
case Iop_MulF64: fpop = Pfp_MULD; break;
@@ -3249,19 +3607,36 @@
}
if (fpop != Pfp_INVALID) {
HReg r_dst = newVRegF(env);
- HReg r_srcL = iselDblExpr(env, e->Iex.Triop.arg2);
- HReg r_srcR = iselDblExpr(env, e->Iex.Triop.arg3);
- set_FPU_rounding_mode( env, e->Iex.Triop.arg1 );
+ HReg r_srcL = iselDblExpr(env, triop->arg2);
+ HReg r_srcR = iselDblExpr(env, triop->arg3);
+ set_FPU_rounding_mode( env, triop->arg1 );
addInstr(env, PPCInstr_FpBinary(fpop, r_dst, r_srcL, r_srcR));
return r_dst;
}
+ switch (triop->op) {
+ case Iop_QuantizeD64: fpop = Pfp_DQUA; break;
+ case Iop_SignificanceRoundD64: fpop = Pfp_RRDTR; break;
+ default: break;
+ }
+ if (fpop != Pfp_INVALID) {
+ HReg r_dst = newVRegF(env);
+ HReg r_srcL = iselDblExpr(env, triop->arg2);
+ HReg r_srcR = iselDblExpr(env, triop->arg3);
+ PPCRI* rmc = iselWordExpr_RI(env, triop->arg1);
+
+ // will set TE and RMC when issuing instruction
+ addInstr(env, PPCInstr_DfpQuantize(fpop, r_dst, r_srcL, r_srcR, rmc));
+ return r_dst;
+ }
}
if (e->tag == Iex_Binop) {
PPCFpOp fpop = Pfp_INVALID;
switch (e->Iex.Binop.op) {
- case Iop_SqrtF64: fpop = Pfp_SQRT; break;
- default: break;
+ case Iop_SqrtF64: fpop = Pfp_SQRT; break;
+ case Iop_I64StoD64: fpop = Pfp_DCFFIX; break;
+ case Iop_D64toI64S: fpop = Pfp_DCTFIX; break;
+ default: break;
}
if (fpop != Pfp_INVALID) {
HReg fr_dst = newVRegF(env);
@@ -3350,6 +3725,7 @@
case Iop_RoundF64toF64_PosINF: fpop = Pfp_FRIP; break;
case Iop_RoundF64toF64_NEAREST: fpop = Pfp_FRIN; break;
case Iop_RoundF64toF64_ZERO: fpop = Pfp_FRIZ; break;
+ case Iop_ExtractExpD64: fpop = Pfp_DXEX; break;
default: break;
}
if (fpop != Pfp_INVALID) {
@@ -3433,6 +3809,432 @@
vpanic("iselDblExpr_wrk(ppc)");
}
+static HReg iselDfp64Expr(ISelEnv* env, IRExpr* e)
+{
+ HReg r = iselDfp64Expr_wrk( env, e );
+ vassert(hregClass(r) == HRcFlt64);
+ vassert( hregIsVirtual(r) );
+ return r;
+}
+
+/* DO NOT CALL THIS DIRECTLY */
+static HReg iselDfp64Expr_wrk(ISelEnv* env, IRExpr* e)
+{
+ Bool mode64 = env->mode64;
+ IRType ty = typeOfIRExpr( env->type_env, e );
+ HReg r_dstHi, r_dstLo;
+
+ vassert( e );
+ vassert( ty == Ity_D64 );
+
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp( env, e->Iex.RdTmp.tmp );
+ }
+
+ /* --------- GET --------- */
+ if (e->tag == Iex_Get) {
+ HReg r_dst = newVRegF( env );
+ PPCAMode* am_addr = PPCAMode_IR( e->Iex.Get.offset,
+ GuestStatePtr(mode64) );
+ addInstr( env, PPCInstr_FpLdSt( True/*load*/, 8, r_dst, am_addr ) );
+ return r_dst;
+ }
+
+ /* --------- OPS --------- */
+ if (e->tag == Iex_Qop) {
+ HReg r_dst = newVRegF( env );
+ return r_dst;
+ }
+
+ if (e->tag == Iex_Unop) {
+ HReg fr_dst = newVRegF(env);
+ switch (e->Iex.Unop.op) {
+ case Iop_ReinterpI64asD64: {
+ /* Given an I64, produce an IEEE754 DFP with the same
+ bit pattern. */
+ if (!mode64) {
+ HReg r_srcHi, r_srcLo;
+ iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg);
+ return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo );
+ } else {
+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
+ return mk_LoadR64toFPR( env, r_src );
+ }
+ }
+
+ case Iop_ExtractExpD64: {
+ HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg);
+
+ addInstr(env, PPCInstr_Dfp64Unary(Pfp_DXEX, fr_dst, fr_src));
+ return fr_dst;
+ }
+ case Iop_ExtractExpD128: {
+ /* Result is a D64 */
+ HReg r_srcHi;
+ HReg r_srcLo;
+
+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Unop.arg);
+ addInstr(env, PPCInstr_ExtractExpD128(Pfp_DXEXQ, fr_dst,
+ r_srcHi, r_srcLo));
+ return fr_dst;
+ }
+ case Iop_D32toD64: {
+ HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg);
+ addInstr(env, PPCInstr_Dfp64Unary(Pfp_DCTDP, fr_dst, fr_src));
+ return fr_dst;
+ }
+ case Iop_D128HItoD64:
+ iselDfp128Expr( &r_dstHi, &r_dstLo, env, e->Iex.Unop.arg );
+ return r_dstHi;
+ case Iop_D128LOtoD64:
+ iselDfp128Expr( &r_dstHi, &r_dstLo, env, e->Iex.Unop.arg );
+ return r_dstLo;
+ case Iop_InsertExpD64: {
+ HReg fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1);
+ HReg fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2);
+
+ addInstr(env, PPCInstr_Dfp64Binary(Pfp_DIEX, fr_dst, fr_srcL,
+ fr_srcR));
+ return fr_dst;
+ }
+ default:
+ vex_printf( "ERROR: iselDfp64Expr_wrk, UNKNOWN unop case %d\n",
+ e->Iex.Unop.op );
+ }
+ }
+
+ if (e->tag == Iex_Binop) {
+
+ switch (e->Iex.Binop.op) {
+ case Iop_D128toI64S: {
+ PPCFpOp fpop = Pfp_DCTFIXQ;
+ HReg fr_dst = newVRegF(env);
+ HReg r_srcHi = newVRegF(env);
+ HReg r_srcLo = newVRegF(env);
+
+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 );
+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_DfpD128toD64(fpop, fr_dst, r_srcHi, r_srcLo));
+ return fr_dst;
+ }
+ case Iop_D128toD64: {
+ PPCFpOp fpop = Pfp_DRDPQ;
+ HReg fr_dst = newVRegF(env);
+ HReg r_srcHi = newVRegF(env);
+ HReg r_srcLo = newVRegF(env);
+
+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 );
+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_DfpD128toD64(fpop, fr_dst, r_srcHi, r_srcLo));
+ return fr_dst;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (e->Iex.Unop.op == Iop_RoundD64toInt) {
+ HReg fr_dst = newVRegF(env);
+ HReg fr_src = newVRegF(env);
+ PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1);
+
+ fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_DfpRound(fr_dst, fr_src, r_rmc));
+ return fr_dst;
+ }
+ }
+
+ if (e->tag == Iex_Binop) {
+ PPCFpOp fpop = Pfp_INVALID;
+ HReg fr_dst = newVRegF(env);
+
+ switch (e->Iex.Binop.op) {
+ case Iop_D64toD32: fpop = Pfp_DRSP; break;
+ case Iop_I64StoD64: fpop = Pfp_DCFFIX; break;
+ case Iop_D64toI64S: fpop = Pfp_DCTFIX; break;
+ default: break;
+ }
+ if (fpop != Pfp_INVALID) {
+ HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2);
+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 );
+ addInstr(env, PPCInstr_Dfp64Unary(fpop, fr_dst, fr_src));
+ return fr_dst;
+ }
+
+ switch (e->Iex.Binop.op) {
+ /* shift instructions F64, I32 -> F64 */
+ case Iop_ShlD64: fpop = Pfp_DSCLI; break;
+ case Iop_ShrD64: fpop = Pfp_DSCRI; break;
+ default: break;
+ }
+ if (fpop != Pfp_INVALID) {
+ HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg1);
+ PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2);
+
+ addInstr(env, PPCInstr_DfpShift(fpop, fr_dst, fr_src, shift));
+ return fr_dst;
+ }
+
+ switch (e->Iex.Binop.op) {
+ case Iop_InsertExpD64:
+ fpop = Pfp_DIEX;
+ break;
+ default: break;
+ }
+ if (fpop != Pfp_INVALID) {
+ HReg fr_srcL = iselDfp64Expr(env, e->Iex.Binop.arg1);
+ HReg fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_Dfp64Binary(fpop, fr_dst, fr_srcL, fr_srcR));
+ return fr_dst;
+ }
+ }
+
+ if (e->tag == Iex_Triop) {
+ IRTriop *triop = e->Iex.Triop.details;
+ PPCFpOp fpop = Pfp_INVALID;
+
+ switch (triop->op) {
+ case Iop_AddD64:
+ fpop = Pfp_DFPADD;
+ break;
+ case Iop_SubD64:
+ fpop = Pfp_DFPSUB;
+ break;
+ case Iop_MulD64:
+ fpop = Pfp_DFPMUL;
+ break;
+ case Iop_DivD64:
+ fpop = Pfp_DFPDIV;
+ break;
+ default:
+ break;
+ }
+ if (fpop != Pfp_INVALID) {
+ HReg r_dst = newVRegF( env );
+ HReg r_srcL = iselDfp64Expr( env, triop->arg2 );
+ HReg r_srcR = iselDfp64Expr( env, triop->arg3 );
+
+ set_FPU_DFP_rounding_mode( env, triop->arg1 );
+ addInstr( env, PPCInstr_Dfp64Binary( fpop, r_dst, r_srcL, r_srcR ) );
+ return r_dst;
+ }
+
+ switch (triop->op) {
+ case Iop_QuantizeD64: fpop = Pfp_DQUA; break;
+ case Iop_SignificanceRoundD64: fpop = Pfp_RRDTR; break;
+ default: break;
+ }
+ if (fpop != Pfp_INVALID) {
+ HReg r_dst = newVRegF(env);
+ HReg r_srcL = iselDfp64Expr(env, triop->arg2);
+ HReg r_srcR = iselDfp64Expr(env, triop->arg3);
+ PPCRI* rmc = iselWordExpr_RI(env, triop->arg1);
+
+ addInstr(env, PPCInstr_DfpQuantize(fpop, r_dst, r_srcL, r_srcR,
+ rmc));
+ return r_dst;
+ }
+ }
+
+ ppIRExpr( e );
+ vpanic( "iselDfp64Expr_wrk(ppc)" );
+}
+
+static void iselDfp128Expr(HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e)
+{
+ iselDfp128Expr_wrk( rHi, rLo, env, e );
+ vassert( hregIsVirtual(*rHi) );
+ vassert( hregIsVirtual(*rLo) );
+}
+
+/* DO NOT CALL THIS DIRECTLY */
+static void iselDfp128Expr_wrk(HReg* rHi, HReg *rLo, ISelEnv* env, IRExpr* e)
+{
+ vassert( e );
+ vassert( typeOfIRExpr(env->type_env,e) == Ity_D128 );
+
+ /* read 128-bit IRTemp */
+ if (e->tag == Iex_RdTmp) {
+ lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp );
+ return;
+ }
+
+ if (e->tag == Iex_Unop) {
+ PPCFpOp fpop = Pfp_INVALID;
+ HReg r_dstHi = newVRegF(env);
+ HReg r_dstLo = newVRegF(env);
+
+ if (e->Iex.Unop.op == Iop_I64StoD128) {
+ HReg r_src = iselDfp64Expr(env, e->Iex.Unop.arg);
+ fpop = Pfp_DCFFIXQ;
+
+ addInstr(env, PPCInstr_DfpI64StoD128(fpop, r_dstHi, r_dstLo,
+ r_src));
+ }
+ if (e->Iex.Unop.op == Iop_D64toD128) {
+ HReg r_src = iselDfp64Expr(env, e->Iex.Unop.arg);
+ fpop = Pfp_DCTQPQ;
+
+ /* Source is 64bit result is 128 bit. High 64bit source arg,
+ * is ignored by the instruction. Set high arg to r_src just
+ * to meet the vassert tests.
+ */
+ addInstr(env, PPCInstr_Dfp128Unary(fpop, r_dstHi, r_dstLo,
+ r_src, r_src));
+ }
+ *rHi = r_dstHi;
+ *rLo = r_dstLo;
+ return;
+ }
+
+ /* --------- OPS --------- */
+ if (e->tag == Iex_Binop) {
+ HReg r_srcHi;
+ HReg r_srcLo;
+
+ switch (e->Iex.Binop.op) {
+ case Iop_D64HLtoD128:
+ r_srcHi = iselDfp64Expr( env, e->Iex.Binop.arg1 );
+ r_srcLo = iselDfp64Expr( env, e->Iex.Binop.arg2 );
+ *rHi = r_srcHi;
+ *rLo = r_srcLo;
+ return;
+ break;
+ case Iop_D128toD64: {
+ PPCFpOp fpop = Pfp_DRDPQ;
+ HReg fr_dst = newVRegF(env);
+
+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_DfpD128toD64(fpop, fr_dst, r_srcHi, r_srcLo));
+
+ /* Need to meet the interface spec but the result is
+ * just 64-bits so send the result back in both halfs.
+ */
+ *rHi = fr_dst;
+ *rLo = fr_dst;
+ return;
+ }
+ case Iop_ShlD128:
+ case Iop_ShrD128: {
+ HReg fr_dst_hi = newVRegF(env);
+ HReg fr_dst_lo = newVRegF(env);
+ PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2);
+ PPCFpOp fpop = Pfp_DSCLIQ; /* fix later if necessary */
+
+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg1);
+
+ if (e->Iex.Binop.op == Iop_ShrD128)
+ fpop = Pfp_DSCRIQ;
+
+ addInstr(env, PPCInstr_DfpShift128(fpop, fr_dst_hi, fr_dst_lo,
+ r_srcHi, r_srcLo, shift));
+
+ *rHi = fr_dst_hi;
+ *rLo = fr_dst_lo;
+ return;
+ }
+ case Iop_RoundD128toInt: {
+ HReg r_dstHi = newVRegF(env);
+ HReg r_dstLo = newVRegF(env);
+ PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1);
+
+ // will set R and RMC when issuing instruction
+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2);
+
+ addInstr(env, PPCInstr_DfpRound128(r_dstHi, r_dstLo,
+ r_srcHi, r_srcLo, r_rmc));
+ *rHi = r_dstHi;
+ *rLo = r_dstLo;
+ return;
+ }
+ case Iop_InsertExpD128: {
+ HReg r_dstHi = newVRegF(env);
+ HReg r_dstLo = newVRegF(env);
+ HReg r_srcL = newVRegF(env);
+
+ r_srcL = iselDfp64Expr(env, e->Iex.Binop.arg1);
+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_InsertExpD128(Pfp_DIEXQ,
+ r_dstHi, r_dstLo,
+ r_srcL, r_srcHi, r_srcLo));
+ *rHi = r_dstHi;
+ *rLo = r_dstLo;
+ return;
+ }
+ default:
+ vex_printf( "ERROR: iselDfp128Expr_wrk, UNKNOWN binop case %d\n",
+ e->Iex.Binop.op );
+ break;
+ }
+ }
+
+ if (e->tag == Iex_Triop) {
+ IRTriop *triop = e->Iex.Triop.details;
+ PPCFpOp fpop = Pfp_INVALID;
+ switch (triop->op) {
+ case Iop_AddD128:
+ fpop = Pfp_DFPADDQ;
+ break;
+ case Iop_SubD128:
+ fpop = Pfp_DFPSUBQ;
+ break;
+ case Iop_MulD128:
+ fpop = Pfp_DFPMULQ;
+ break;
+ case Iop_DivD128:
+ fpop = Pfp_DFPDIVQ;
+ break;
+ default:
+ break;
+ }
+
+ if (fpop != Pfp_INVALID) {
+ HReg r_dstHi = newVRegV( env );
+ HReg r_dstLo = newVRegV( env );
+ HReg r_srcRHi = newVRegV( env );
+ HReg r_srcRLo = newVRegV( env );
+
+ /* dst will be used to pass in the left operand and get the result. */
+ iselDfp128Expr( &r_dstHi, &r_dstLo, env, triop->arg2 );
+ iselDfp128Expr( &r_srcRHi, &r_srcRLo, env, triop->arg3 );
+ set_FPU_rounding_mode( env, triop->arg1 );
+ addInstr( env,
+ PPCInstr_Dfp128Binary( fpop, r_dstHi, r_dstLo,
+ r_srcRHi, r_srcRLo ) );
+ *rHi = r_dstHi;
+ *rLo = r_dstLo;
+ return;
+ }
+ switch (triop->op) {
+ case Iop_QuantizeD128: fpop = Pfp_DQUAQ; break;
+ case Iop_SignificanceRoundD128: fpop = Pfp_DRRNDQ; break;
+ default: break;
+ }
+ if (fpop != Pfp_INVALID) {
+ HReg r_dstHi = newVRegF(env);
+ HReg r_dstLo = newVRegF(env);
+ HReg r_srcHi = newVRegF(env);
+ HReg r_srcLo = newVRegF(env);
+ PPCRI* rmc = iselWordExpr_RI(env, triop->arg1);
+
+ /* dst will be used to pass in the left operand and get the result */
+ iselDfp128Expr(&r_dstHi, &r_dstLo, env, triop->arg2);
+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, triop->arg3);
+
+ // will set RMC when issuing instruction
+ addInstr(env, PPCInstr_DfpQuantize128(fpop, r_dstHi, r_dstLo,
+ r_srcHi, r_srcLo, rmc));
+ *rHi = r_dstHi;
+ *rLo = r_dstLo;
+ return;
+ }
+ }
+
+ ppIRExpr( e );
+ vpanic( "iselDfp128Expr(ppc64)" );
+}
+
/*---------------------------------------------------------*/
/*--- ISEL: SIMD (Vector) expressions, 128 bit. ---*/
@@ -3575,7 +4377,7 @@
case Iop_Dup8x16:
case Iop_Dup16x8:
case Iop_Dup32x4:
- return mk_AvDuplicateRI(env, e->Iex.Binop.arg1);
+ return mk_AvDuplicateRI(env, e->Iex.Unop.arg);
default:
break;
@@ -3982,24 +4784,33 @@
fr_src, am_addr ));
return;
}
+ if (ty == Ity_D64) {
+ HReg fr_src = iselDfp64Expr( env, stmt->Ist.Put.data );
+ PPCAMode* am_addr = PPCAMode_IR( stmt->Ist.Put.offset,
+ GuestStatePtr(mode64) );
+ addInstr( env, PPCInstr_FpLdSt( False/*store*/, 8, fr_src, am_addr ) );
+ return;
+ }
break;
}
/* --------- Indexed PUT --------- */
case Ist_PutI: {
+ IRPutI *puti = stmt->Ist.PutI.details;
+
PPCAMode* dst_am
= genGuestArrayOffset(
- env, stmt->Ist.PutI.descr,
- stmt->Ist.PutI.ix, stmt->Ist.PutI.bias );
- IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.PutI.data);
+ env, puti->descr,
+ puti->ix, puti->bias );
+ IRType ty = typeOfIRExpr(env->type_env, puti->data);
if (mode64 && ty == Ity_I64) {
- HReg r_src = iselWordExpr_R(env, stmt->Ist.PutI.data);
+ HReg r_src = iselWordExpr_R(env, puti->data);
addInstr(env, PPCInstr_Store( toUChar(8),
dst_am, r_src, mode64 ));
return;
}
if ((!mode64) && ty == Ity_I32) {
- HReg r_src = iselWordExpr_R(env, stmt->Ist.PutI.data);
+ HReg r_src = iselWordExpr_R(env, puti->data);
addInstr(env, PPCInstr_Store( toUChar(4),
dst_am, r_src, mode64 ));
return;
@@ -4020,6 +4831,7 @@
}
if (!mode64 && ty == Ity_I64) {
HReg r_srcHi, r_srcLo, r_dstHi, r_dstLo;
+
iselInt64Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.WrTmp.data);
lookupIRTempPair( &r_dstHi, &r_dstLo, env, tmp);
addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) );
@@ -4034,6 +4846,23 @@
addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) );
return;
}
+ if (!mode64 && ty == Ity_I128) {
+ HReg r_srcHi, r_srcMedHi, r_srcMedLo, r_srcLo;
+ HReg r_dstHi, r_dstMedHi, r_dstMedLo, r_dstLo;
+
+ iselInt128Expr_to_32x4(&r_srcHi, &r_srcMedHi,
+ &r_srcMedLo, &r_srcLo,
+ env, stmt->Ist.WrTmp.data);
+
+ lookupIRTempQuad( &r_dstHi, &r_dstMedHi, &r_dstMedLo,
+ &r_dstLo, env, tmp);
+
+ addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) );
+ addInstr(env, mk_iMOVds_RR(r_dstMedHi, r_srcMedHi) );
+ addInstr(env, mk_iMOVds_RR(r_dstMedLo, r_srcMedLo) );
+ addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) );
+ return;
+ }
if (ty == Ity_I1) {
PPCCondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data);
HReg r_dst = lookupIRTemp(env, tmp);
@@ -4058,6 +4887,21 @@
addInstr(env, PPCInstr_AvUnary(Pav_MOV, v_dst, v_src));
return;
}
+ if (ty == Ity_D64) {
+ HReg fr_dst = lookupIRTemp( env, tmp );
+ HReg fr_src = iselDfp64Expr( env, stmt->Ist.WrTmp.data );
+ addInstr( env, PPCInstr_Dfp64Unary( Pfp_MOV, fr_dst, fr_src ) );
+ return;
+ }
+ if (ty == Ity_D128) {
+ HReg fr_srcHi, fr_srcLo, fr_dstHi, fr_dstLo;
+ // lookupDfp128IRTempPair( &fr_dstHi, &fr_dstLo, env, tmp );
+ lookupIRTempPair( &fr_dstHi, &fr_dstLo, env, tmp );
+ iselDfp128Expr( &fr_srcHi, &fr_srcLo, env, stmt->Ist.WrTmp.data );
+ addInstr( env, PPCInstr_Dfp64Unary( Pfp_MOV, fr_dstHi, fr_srcHi ) );
+ addInstr( env, PPCInstr_Dfp64Unary( Pfp_MOV, fr_dstLo, fr_srcLo ) );
+ return;
+ }
break;
}
@@ -4190,18 +5034,67 @@
/* --------- EXIT --------- */
case Ist_Exit: {
- PPCRI* ri_dst;
- PPCCondCode cc;
- IRConstTag tag = stmt->Ist.Exit.dst->tag;
- if (!mode64 && (tag != Ico_U32))
+ IRConst* dst = stmt->Ist.Exit.dst;
+ if (!mode64 && dst->tag != Ico_U32)
vpanic("iselStmt(ppc): Ist_Exit: dst is not a 32-bit value");
- if (mode64 && (tag != Ico_U64))
+ if (mode64 && dst->tag != Ico_U64)
vpanic("iselStmt(ppc64): Ist_Exit: dst is not a 64-bit value");
- ri_dst = iselWordExpr_RI(env, IRExpr_Const(stmt->Ist.Exit.dst));
- cc = iselCondCode(env,stmt->Ist.Exit.guard);
- addInstr(env, PPCInstr_RdWrLR(True, env->savedLR));
- addInstr(env, PPCInstr_Goto(stmt->Ist.Exit.jk, cc, ri_dst));
- return;
+
+ PPCCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
+ PPCAMode* amCIA = PPCAMode_IR(stmt->Ist.Exit.offsIP,
+ hregPPC_GPR31(mode64));
+
+ /* Case: boring transfer to known address */
+ if (stmt->Ist.Exit.jk == Ijk_Boring
+ || stmt->Ist.Exit.jk == Ijk_Call
+ /* || stmt->Ist.Exit.jk == Ijk_Ret */) {
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = mode64
+ ? (((Addr64)stmt->Ist.Exit.dst->Ico.U64) > (Addr64)env->max_ga)
+ : (((Addr32)stmt->Ist.Exit.dst->Ico.U32) > (Addr32)env->max_ga);
+ if (0) vex_printf("%s", toFastEP ? "Y" : ",");
+ addInstr(env, PPCInstr_XDirect(
+ mode64 ? (Addr64)stmt->Ist.Exit.dst->Ico.U64
+ : (Addr64)stmt->Ist.Exit.dst->Ico.U32,
+ amCIA, cc, toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, PPCInstr_XAssisted(r, amCIA, cc, Ijk_Boring));
+ }
+ return;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (stmt->Ist.Exit.jk) {
+ /* Keep this list in sync with that in iselNext below */
+ case Ijk_ClientReq:
+ case Ijk_EmFail:
+ case Ijk_EmWarn:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_SigBUS:
+ case Ijk_SigTRAP:
+ case Ijk_Sys_syscall:
+ case Ijk_TInval:
+ {
+ HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, PPCInstr_XAssisted(r, amCIA, cc,
+ stmt->Ist.Exit.jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Do we ever expect to see any other kind? */
+ goto stmt_fail;
}
default: break;
@@ -4216,21 +5109,96 @@
/*--- ISEL: Basic block terminators (Nexts) ---*/
/*---------------------------------------------------------*/
-static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk )
+static void iselNext ( ISelEnv* env,
+ IRExpr* next, IRJumpKind jk, Int offsIP )
{
- PPCCondCode cond;
- PPCRI* ri;
if (vex_traceflags & VEX_TRACE_VCODE) {
- vex_printf("\n-- goto {");
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
ppIRJumpKind(jk);
- vex_printf("} ");
- ppIRExpr(next);
- vex_printf("\n");
+ vex_printf( "\n");
}
- cond = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
- ri = iselWordExpr_RI(env, next);
- addInstr(env, PPCInstr_RdWrLR(True, env->savedLR));
- addInstr(env, PPCInstr_Goto(jk, cond, ri));
+
+ PPCCondCode always = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
+
+ /* Case: boring transfer to known address */
+ if (next->tag == Iex_Const) {
+ IRConst* cdst = next->Iex.Const.con;
+ vassert(cdst->tag == (env->mode64 ? Ico_U64 :Ico_U32));
+ if (jk == Ijk_Boring || jk == Ijk_Call) {
+ /* Boring transfer to known address */
+ PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64));
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = env->mode64
+ ? (((Addr64)cdst->Ico.U64) > (Addr64)env->max_ga)
+ : (((Addr32)cdst->Ico.U32) > (Addr32)env->max_ga);
+ if (0) vex_printf("%s", toFastEP ? "X" : ".");
+ addInstr(env, PPCInstr_XDirect(
+ env->mode64 ? (Addr64)cdst->Ico.U64
+ : (Addr64)cdst->Ico.U32,
+ amCIA, always, toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg r = iselWordExpr_R(env, next);
+ addInstr(env, PPCInstr_XAssisted(r, amCIA, always,
+ Ijk_Boring));
+ }
+ return;
+ }
+ }
+
+ /* Case: call/return (==boring) transfer to any address */
+ switch (jk) {
+ case Ijk_Boring: case Ijk_Ret: case Ijk_Call: {
+ HReg r = iselWordExpr_R(env, next);
+ PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64));
+ if (env->chainingAllowed) {
+ addInstr(env, PPCInstr_XIndir(r, amCIA, always));
+ } else {
+ addInstr(env, PPCInstr_XAssisted(r, amCIA, always,
+ Ijk_Boring));
+ }
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (jk) {
+ /* Keep this list in sync with that for Ist_Exit above */
+ case Ijk_ClientReq:
+ case Ijk_EmFail:
+ case Ijk_EmWarn:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_SigBUS:
+ case Ijk_SigTRAP:
+ case Ijk_Sys_syscall:
+ case Ijk_TInval:
+ {
+ HReg r = iselWordExpr_R(env, next);
+ PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64));
+ addInstr(env, PPCInstr_XAssisted(r, amCIA, always, jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
+ ppIRJumpKind(jk);
+ vex_printf( "\n");
+ vassert(0); // are we expecting any other kind?
}
@@ -4238,28 +5206,37 @@
/*--- Insn selector top-level ---*/
/*---------------------------------------------------------*/
-/* Translate an entire BS to ppc code. */
-
-HInstrArray* iselSB_PPC ( IRSB* bb, VexArch arch_host,
- VexArchInfo* archinfo_host,
- VexAbiInfo* vbi )
+/* Translate an entire SB to ppc code. */
+HInstrArray* iselSB_PPC ( IRSB* bb,
+ VexArch arch_host,
+ VexArchInfo* archinfo_host,
+ VexAbiInfo* vbi,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga )
{
- Int i, j;
- HReg hreg, hregHI;
- ISelEnv* env;
- UInt hwcaps_host = archinfo_host->hwcaps;
- Bool mode64 = False;
- UInt mask32, mask64;
+ Int i, j;
+ HReg hregLo, hregMedLo, hregMedHi, hregHi;
+ ISelEnv* env;
+ UInt hwcaps_host = archinfo_host->hwcaps;
+ Bool mode64 = False;
+ UInt mask32, mask64;
+ PPCAMode *amCounter, *amFailAddr;
+
vassert(arch_host == VexArchPPC32 || arch_host == VexArchPPC64);
mode64 = arch_host == VexArchPPC64;
+ if (!mode64) vassert(max_ga <= 0xFFFFFFFFULL);
/* do some sanity checks */
mask32 = VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V
- | VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX | VEX_HWCAPS_PPC32_VX;
+ | VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX | VEX_HWCAPS_PPC32_VX
+ | VEX_HWCAPS_PPC32_DFP;
mask64 = VEX_HWCAPS_PPC64_V | VEX_HWCAPS_PPC64_FX
- | VEX_HWCAPS_PPC64_GX | VEX_HWCAPS_PPC64_VX;
+ | VEX_HWCAPS_PPC64_GX | VEX_HWCAPS_PPC64_VX | VEX_HWCAPS_PPC64_DFP;
if (mode64) {
vassert((hwcaps_host & mask32) == 0);
@@ -4281,59 +5258,92 @@
env->type_env = bb->tyenv;
/* Make up an IRTemp -> virtual HReg mapping. This doesn't
- change as we go along. */
+ * change as we go along.
+ *
+ * vregmap2 and vregmap3 are only used in 32 bit mode
+ * for supporting I128 in 32-bit mode
+ */
env->n_vregmap = bb->tyenv->types_used;
- env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
- env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
+ env->vregmapLo = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
+ env->vregmapMedLo = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
+ if (mode64) {
+ env->vregmapMedHi = NULL;
+ env->vregmapHi = NULL;
+ } else {
+ env->vregmapMedHi = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
+ env->vregmapHi = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
+ }
/* and finally ... */
- env->hwcaps = hwcaps_host;
- env->previous_rm = NULL;
- env->vbi = vbi;
+ env->chainingAllowed = chainingAllowed;
+ env->max_ga = max_ga;
+ env->hwcaps = hwcaps_host;
+ env->previous_rm = NULL;
+ env->vbi = vbi;
/* For each IR temporary, allocate a suitably-kinded virtual
register. */
j = 0;
for (i = 0; i < env->n_vregmap; i++) {
- hregHI = hreg = INVALID_HREG;
+ hregLo = hregMedLo = hregMedHi = hregHi = INVALID_HREG;
switch (bb->tyenv->types[i]) {
case Ity_I1:
case Ity_I8:
case Ity_I16:
case Ity_I32:
- if (mode64) { hreg = mkHReg(j++, HRcInt64, True); break;
- } else { hreg = mkHReg(j++, HRcInt32, True); break;
+ if (mode64) { hregLo = mkHReg(j++, HRcInt64, True); break;
+ } else { hregLo = mkHReg(j++, HRcInt32, True); break;
}
case Ity_I64:
- if (mode64) { hreg = mkHReg(j++, HRcInt64, True); break;
- } else { hreg = mkHReg(j++, HRcInt32, True);
- hregHI = mkHReg(j++, HRcInt32, True); break;
+ if (mode64) { hregLo = mkHReg(j++, HRcInt64, True); break;
+ } else { hregLo = mkHReg(j++, HRcInt32, True);
+ hregMedLo = mkHReg(j++, HRcInt32, True); break;
}
- case Ity_I128: vassert(mode64);
- hreg = mkHReg(j++, HRcInt64, True);
- hregHI = mkHReg(j++, HRcInt64, True); break;
+ case Ity_I128:
+ if (mode64) { hregLo = mkHReg(j++, HRcInt64, True);
+ hregMedLo = mkHReg(j++, HRcInt64, True); break;
+ } else { hregLo = mkHReg(j++, HRcInt32, True);
+ hregMedLo = mkHReg(j++, HRcInt32, True);
+ hregMedHi = mkHReg(j++, HRcInt32, True);
+ hregHi = mkHReg(j++, HRcInt32, True); break;
+ }
case Ity_F32:
- case Ity_F64: hreg = mkHReg(j++, HRcFlt64, True); break;
- case Ity_V128: hreg = mkHReg(j++, HRcVec128, True); break;
+ case Ity_F64: hregLo = mkHReg(j++, HRcFlt64, True); break;
+ case Ity_V128: hregLo = mkHReg(j++, HRcVec128, True); break;
+ case Ity_D64: hregLo = mkHReg(j++, HRcFlt64, True); break;
+ case Ity_D128: hregLo = mkHReg(j++, HRcFlt64, True);
+ hregMedLo = mkHReg(j++, HRcFlt64, True); break;
default:
ppIRType(bb->tyenv->types[i]);
vpanic("iselBB(ppc): IRTemp type");
}
- env->vregmap[i] = hreg;
- env->vregmapHI[i] = hregHI;
+ env->vregmapLo[i] = hregLo;
+ env->vregmapMedLo[i] = hregMedLo;
+ if (!mode64) {
+ env->vregmapMedHi[i] = hregMedHi;
+ env->vregmapHi[i] = hregHi;
+ }
}
env->vreg_ctr = j;
- /* Keep a copy of the link reg, so helper functions don't kill it. */
- env->savedLR = newVRegI(env);
- addInstr(env, PPCInstr_RdWrLR(False, env->savedLR));
+ /* The very first instruction must be an event check. */
+ amCounter = PPCAMode_IR(offs_Host_EvC_Counter, hregPPC_GPR31(mode64));
+ amFailAddr = PPCAMode_IR(offs_Host_EvC_FailAddr, hregPPC_GPR31(mode64));
+ addInstr(env, PPCInstr_EvCheck(amCounter, amFailAddr));
+
+ /* Possibly a block counter increment (for profiling). At this
+ point we don't know the address of the counter, so just pretend
+ it is zero. It will have to be patched later, but before this
+ translation is used, by a call to LibVEX_patchProfCtr. */
+ if (addProfInc) {
+ addInstr(env, PPCInstr_ProfInc());
+ }
/* Ok, finally we can iterate over the statements. */
for (i = 0; i < bb->stmts_used; i++)
- if (bb->stmts[i])
- iselStmt(env,bb->stmts[i]);
+ iselStmt(env, bb->stmts[i]);
- iselNext(env,bb->next,bb->jumpkind);
+ iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
/* record the number of vregs we used. */
env->code->n_vregs = env->vreg_ctr;
diff --git a/main/VEX/priv/host_s390_defs.c b/main/VEX/priv/host_s390_defs.c
index a8052b5..ed98c3c 100644
--- a/main/VEX/priv/host_s390_defs.c
+++ b/main/VEX/priv/host_s390_defs.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -33,7 +33,6 @@
#include "libvex_basictypes.h"
#include "libvex.h"
#include "libvex_trc_values.h"
-#include "libvex_guest_offsets.h"
#include "libvex_s390x_common.h"
#include "main_util.h"
@@ -41,6 +40,7 @@
#include "host_generic_regs.h"
#include "host_s390_defs.h"
#include "host_s390_disasm.h"
+#include "guest_s390_defs.h" /* S390X_GUEST_OFFSET */
#include <stdarg.h>
/* KLUDGE: We need to know the hwcaps of the host when generating
@@ -49,7 +49,7 @@
Until then, we use a global variable. This variable is set as a side
effect of iselSB_S390. This is safe because instructions are selected
before they are emitted. */
-const VexArchInfo *s390_archinfo_host;
+UInt s390_host_hwcaps;
/*------------------------------------------------------------*/
@@ -59,6 +59,7 @@
static Bool s390_insn_is_reg_reg_move(const s390_insn *, HReg *src, HReg *dst);
static void s390_insn_map_regs(HRegRemap *, s390_insn *);
static void s390_insn_get_reg_usage(HRegUsage *u, const s390_insn *);
+static UInt s390_tchain_load64_len(void);
/*------------------------------------------------------------*/
@@ -118,7 +119,7 @@
/* Total number of allocable registers (all classes) */
*nregs = 16 /* GPRs */
- 1 /* r0 */
- - 1 /* r12 register holding VG_(dispatch_ctr) */
+ - 1 /* r12 scratch register for translation chaining support */
- 1 /* r13 guest state pointer */
- 1 /* r14 link register */
- 1 /* r15 stack pointer */
@@ -144,7 +145,8 @@
Otherwise, they are available to the allocator */
(*arr)[i++] = mkHReg(10, HRcInt64, False);
(*arr)[i++] = mkHReg(11, HRcInt64, False);
- /* GPR12 is not available because it caches VG_(dispatch_ctr) */
+ /* GPR12 is not available because it us used as a scratch register
+ in translation chaining. */
/* GPR13 is not available because it is used as guest state pointer */
/* GPR14 is not available because it is used as link register */
/* GPR15 is not available because it is used as stack pointer */
@@ -178,6 +180,7 @@
return mkHReg(S390_REGNO_GUEST_STATE_POINTER, HRcInt64, False);
}
+
/* Is VALUE within the domain of a 20-bit signed integer. */
static __inline__ Bool
fits_signed_20bit(Int value)
@@ -607,19 +610,22 @@
addHRegUse(u, HRmWrite, insn->variant.cas.old_mem);
break;
+ case S390_INSN_CDAS:
+ addHRegUse(u, HRmRead, insn->variant.cdas.op1_high);
+ addHRegUse(u, HRmRead, insn->variant.cdas.op1_low);
+ s390_amode_get_reg_usage(u, insn->variant.cas.op2);
+ addHRegUse(u, HRmRead, insn->variant.cdas.op3_high);
+ addHRegUse(u, HRmRead, insn->variant.cdas.op3_low);
+ addHRegUse(u, HRmWrite, insn->variant.cdas.old_mem_high);
+ addHRegUse(u, HRmWrite, insn->variant.cdas.old_mem_low);
+ addHRegUse(u, HRmWrite, insn->variant.cdas.scratch);
+ break;
+
case S390_INSN_COMPARE:
addHRegUse(u, HRmRead, insn->variant.compare.src1);
s390_opnd_RMI_get_reg_usage(u, insn->variant.compare.src2);
break;
- case S390_INSN_BRANCH:
- s390_opnd_RMI_get_reg_usage(u, insn->variant.branch.dst);
- /* The destination address is loaded into S390_REGNO_RETURN_VALUE.
- See s390_insn_branch_emit. */
- addHRegUse(u, HRmWrite,
- mkHReg(S390_REGNO_RETURN_VALUE, HRcInt64, False));
- break;
-
case S390_INSN_HELPER_CALL: {
UInt i;
@@ -629,6 +635,8 @@
for (i = 1; i <= 5; ++i) {
addHRegUse(u, HRmWrite, mkHReg(i, HRcInt64, False));
}
+ if (insn->variant.helper_call.dst != INVALID_HREG)
+ addHRegUse(u, HRmWrite, insn->variant.helper_call.dst);
/* Ditto for floating point registers. f0 - f7 are volatile */
for (i = 0; i <= 7; ++i) {
@@ -709,6 +717,31 @@
break;
case S390_INSN_MFENCE:
+ case S390_INSN_GZERO:
+ case S390_INSN_GADD:
+ break;
+
+ case S390_INSN_EVCHECK:
+ s390_amode_get_reg_usage(u, insn->variant.evcheck.counter);
+ s390_amode_get_reg_usage(u, insn->variant.evcheck.fail_addr);
+ break;
+
+ case S390_INSN_PROFINC:
+ /* Does not use any register visible to the register allocator */
+ break;
+
+ case S390_INSN_XDIRECT:
+ s390_amode_get_reg_usage(u, insn->variant.xdirect.guest_IA);
+ break;
+
+ case S390_INSN_XINDIR:
+ addHRegUse(u, HRmRead, insn->variant.xindir.dst);
+ s390_amode_get_reg_usage(u, insn->variant.xindir.guest_IA);
+ break;
+
+ case S390_INSN_XASSISTED:
+ addHRegUse(u, HRmRead, insn->variant.xassisted.dst);
+ s390_amode_get_reg_usage(u, insn->variant.xassisted.guest_IA);
break;
default:
@@ -817,16 +850,22 @@
insn->variant.cas.old_mem = lookupHRegRemap(m, insn->variant.cas.old_mem);
break;
+ case S390_INSN_CDAS:
+ insn->variant.cdas.op1_high = lookupHRegRemap(m, insn->variant.cdas.op1_high);
+ insn->variant.cdas.op1_low = lookupHRegRemap(m, insn->variant.cdas.op1_low);
+ s390_amode_map_regs(m, insn->variant.cdas.op2);
+ insn->variant.cdas.op3_high = lookupHRegRemap(m, insn->variant.cdas.op3_high);
+ insn->variant.cdas.op3_low = lookupHRegRemap(m, insn->variant.cdas.op3_low);
+ insn->variant.cdas.old_mem_high = lookupHRegRemap(m, insn->variant.cdas.old_mem_high);
+ insn->variant.cdas.old_mem_low = lookupHRegRemap(m, insn->variant.cdas.old_mem_low);
+ insn->variant.cdas.scratch = lookupHRegRemap(m, insn->variant.cdas.scratch);
+ break;
+
case S390_INSN_COMPARE:
insn->variant.compare.src1 = lookupHRegRemap(m, insn->variant.compare.src1);
s390_opnd_RMI_map_regs(m, &insn->variant.compare.src2);
break;
- case S390_INSN_BRANCH:
- s390_opnd_RMI_map_regs(m, &insn->variant.branch.dst);
- /* No need to map S390_REGNO_RETURN_VALUE. It's not virtual */
- break;
-
case S390_INSN_HELPER_CALL:
/* s390_insn_helper_call_emit also reads / writes the link register
and stack pointer. But those registers are not visible to the
@@ -834,6 +873,8 @@
As for the arguments of the helper call -- they will be loaded into
non-virtual registers. Again, we don't need to do anything for those
here. */
+ if (insn->variant.helper_call.dst != INVALID_HREG)
+ insn->variant.helper_call.dst = lookupHRegRemap(m, insn->variant.helper_call.dst);
break;
case S390_INSN_BFP_TRIOP:
@@ -912,6 +953,33 @@
break;
case S390_INSN_MFENCE:
+ case S390_INSN_GZERO:
+ case S390_INSN_GADD:
+ break;
+
+ case S390_INSN_EVCHECK:
+ s390_amode_map_regs(m, insn->variant.evcheck.counter);
+ s390_amode_map_regs(m, insn->variant.evcheck.fail_addr);
+ break;
+
+ case S390_INSN_PROFINC:
+ /* Does not use any register visible to the register allocator */
+ break;
+
+ case S390_INSN_XDIRECT:
+ s390_amode_map_regs(m, insn->variant.xdirect.guest_IA);
+ break;
+
+ case S390_INSN_XINDIR:
+ s390_amode_map_regs(m, insn->variant.xindir.guest_IA);
+ insn->variant.xindir.dst =
+ lookupHRegRemap(m, insn->variant.xindir.dst);
+ break;
+
+ case S390_INSN_XASSISTED:
+ s390_amode_map_regs(m, insn->variant.xassisted.guest_IA);
+ insn->variant.xassisted.dst =
+ lookupHRegRemap(m, insn->variant.xassisted.dst);
break;
default:
@@ -1110,6 +1178,35 @@
}
+static UChar *
+emit_SIY(UChar *p, ULong op, UChar i2, UChar b1, UShort dl1, UChar dh1)
+{
+ ULong the_insn = op;
+
+ the_insn |= ((ULong)i2) << 32;
+ the_insn |= ((ULong)b1) << 28;
+ the_insn |= ((ULong)dl1) << 16;
+ the_insn |= ((ULong)dh1) << 8;
+
+ return emit_6bytes(p, the_insn);
+}
+
+
+static UChar *
+emit_SSa(UChar *p, ULong op, UChar l, UChar b1, UShort d1, UChar b2, UShort d2)
+{
+ ULong the_insn = op;
+
+ the_insn |= ((ULong)l) << 32;
+ the_insn |= ((ULong)b1) << 28;
+ the_insn |= ((ULong)d1) << 16;
+ the_insn |= ((ULong)b2) << 12;
+ the_insn |= ((ULong)d2) << 0;
+
+ return emit_6bytes(p, the_insn);
+}
+
+
/*------------------------------------------------------------*/
/*--- Functions to emit particular instructions ---*/
/*------------------------------------------------------------*/
@@ -1235,6 +1332,30 @@
static UChar *
+s390_emit_AGSI(UChar *p, UChar i2, UChar b1, UShort dl1, UChar dh1)
+{
+ vassert(s390_host_has_gie);
+
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+ s390_disasm(ENC3(MNM, SDXB, INT), "agsi", dh1, dl1, 0, b1, (Int)(Char)i2);
+
+ return emit_SIY(p, 0xeb000000007aULL, i2, b1, dl1, dh1);
+}
+
+
+static UChar *
+s390_emit_ASI(UChar *p, UChar i2, UChar b1, UShort dl1, UChar dh1)
+{
+ vassert(s390_host_has_gie);
+
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+ s390_disasm(ENC3(MNM, SDXB, INT), "asi", dh1, dl1, 0, b1, (Int)(Char)i2);
+
+ return emit_SIY(p, 0xeb000000006aULL, i2, b1, dl1, dh1);
+}
+
+
+static UChar *
s390_emit_NR(UChar *p, UChar r1, UChar r2)
{
if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
@@ -1353,6 +1474,16 @@
static UChar *
+s390_emit_BRCL(UChar *p, UChar r1, ULong i2)
+{
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+ s390_disasm(ENC2(XMNM, PCREL), S390_XMNM_BRCL, r1, i2);
+
+ return emit_RIL(p, 0xc00400000000ULL, r1, i2);
+}
+
+
+static UChar *
s390_emit_CR(UChar *p, UChar r1, UChar r2)
{
if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
@@ -1419,6 +1550,18 @@
static UChar *
+s390_emit_CGFI(UChar *p, UChar r1, UInt i2)
+{
+ vassert(s390_host_has_eimm);
+
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+ s390_disasm(ENC3(MNM, GPR, INT), "cgfi", r1, i2);
+
+ return emit_RIL(p, 0xc20c00000000ULL, r1, i2);
+}
+
+
+static UChar *
s390_emit_CS(UChar *p, UChar r1, UChar r3, UChar b2, UShort d2)
{
if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
@@ -1453,6 +1596,40 @@
static UChar *
+s390_emit_CDS(UChar *p, UChar r1, UChar r3, UChar b2, UShort d2)
+{
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+ s390_disasm(ENC4(MNM, GPR, GPR, UDXB), "cds", r1, r3, d2, 0, b2);
+
+ return emit_RS(p, 0xbb000000, r1, r3, b2, d2);
+}
+
+
+static UChar *
+s390_emit_CDSY(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2)
+{
+ vassert(s390_host_has_ldisp);
+
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+ s390_disasm(ENC4(MNM, GPR, GPR, SDXB), "cdsy", r1, r3, dh2, dl2, 0, b2);
+
+ return emit_RSY(p, 0xeb0000000031ULL, r1, r3, b2, dl2, dh2);
+}
+
+
+static UChar *
+s390_emit_CDSG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2)
+{
+ vassert(s390_host_has_ldisp || dh2 == 0);
+
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+ s390_disasm(ENC4(MNM, GPR, GPR, SDXB), "cdsg", r1, r3, dh2, dl2, 0, b2);
+
+ return emit_RSY(p, 0xeb000000003eULL, r1, r3, b2, dl2, dh2);
+}
+
+
+static UChar *
s390_emit_CLR(UChar *p, UChar r1, UChar r2)
{
if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
@@ -1519,6 +1696,18 @@
static UChar *
+s390_emit_CLGFI(UChar *p, UChar r1, UInt i2)
+{
+ vassert(s390_host_has_eimm);
+
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+ s390_disasm(ENC3(MNM, GPR, UINT), "clgfi", r1, i2);
+
+ return emit_RIL(p, 0xc20e00000000ULL, r1, i2);
+}
+
+
+static UChar *
s390_emit_DR(UChar *p, UChar r1, UChar r2)
{
if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
@@ -1683,6 +1872,16 @@
static UChar *
+s390_emit_XC(UChar *p, UInt l, UChar b1, UShort d1, UChar b2, UShort d2)
+{
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM))
+ s390_disasm(ENC3(MNM, UDLB, UDXB), "xc", d1, l, b1, d2, 0, b2);
+
+ return emit_SSa(p, 0xd70000000000ULL, l, b1, d1, b2, d2);
+}
+
+
+static UChar *
s390_emit_FLOGR(UChar *p, UChar r1, UChar r2)
{
vassert(s390_host_has_eimm);
@@ -4174,6 +4373,32 @@
s390_insn *
+s390_insn_cdas(UChar size, HReg op1_high, HReg op1_low, s390_amode *op2,
+ HReg op3_high, HReg op3_low, HReg old_mem_high, HReg old_mem_low,
+ HReg scratch)
+{
+ s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
+
+ vassert(size == 4 || size == 8);
+ vassert(op2->x == 0);
+ vassert(hregNumber(scratch) == 1); /* r0,r1 used as scratch reg pair */
+
+ insn->tag = S390_INSN_CDAS;
+ insn->size = size;
+ insn->variant.cdas.op1_high = op1_high;
+ insn->variant.cdas.op1_low = op1_low;
+ insn->variant.cdas.op2 = op2;
+ insn->variant.cdas.op3_high = op3_high;
+ insn->variant.cdas.op3_low = op3_low;
+ insn->variant.cdas.old_mem_high = old_mem_high;
+ insn->variant.cdas.old_mem_low = old_mem_low;
+ insn->variant.cdas.scratch = scratch;
+
+ return insn;
+}
+
+
+s390_insn *
s390_insn_compare(UChar size, HReg src1, s390_opnd_RMI src2,
Bool signed_comparison)
{
@@ -4192,23 +4417,8 @@
s390_insn *
-s390_insn_branch(IRJumpKind kind, s390_cc_t cond, s390_opnd_RMI dst)
-{
- s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
-
- insn->tag = S390_INSN_BRANCH;
- insn->size = 0; /* does not matter */
- insn->variant.branch.kind = kind;
- insn->variant.branch.dst = dst;
- insn->variant.branch.cond = cond;
-
- return insn;
-}
-
-
-s390_insn *
s390_insn_helper_call(s390_cc_t cond, Addr64 target, UInt num_args,
- HChar *name)
+ HChar *name, HReg dst)
{
s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
@@ -4218,6 +4428,7 @@
insn->variant.helper_call.target = target;
insn->variant.helper_call.num_args = num_args;
insn->variant.helper_call.name = name;
+ insn->variant.helper_call.dst = dst;
return insn;
}
@@ -4401,6 +4612,116 @@
}
+s390_insn *
+s390_insn_gzero(UChar size, UInt offset)
+{
+ s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
+
+ insn->tag = S390_INSN_GZERO;
+ insn->size = size;
+ insn->variant.gzero.offset = offset;
+
+ return insn;
+}
+
+
+s390_insn *
+s390_insn_gadd(UChar size, UInt offset, UChar delta, ULong value)
+{
+ s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
+
+ insn->tag = S390_INSN_GADD;
+ insn->size = size;
+ insn->variant.gadd.offset = offset;
+ insn->variant.gadd.delta = delta;
+ insn->variant.gadd.value = value;
+
+ return insn;
+}
+
+
+s390_insn *
+s390_insn_xdirect(s390_cc_t cond, Addr64 dst, s390_amode *guest_IA,
+ Bool to_fast_entry)
+{
+ s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
+
+ insn->tag = S390_INSN_XDIRECT;
+ insn->size = 0; /* does not matter */
+
+ insn->variant.xdirect.cond = cond;
+ insn->variant.xdirect.dst = dst;
+ insn->variant.xdirect.guest_IA = guest_IA;
+ insn->variant.xdirect.to_fast_entry = to_fast_entry;
+
+ return insn;
+}
+
+
+s390_insn *
+s390_insn_xindir(s390_cc_t cond, HReg dst, s390_amode *guest_IA)
+{
+ s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
+
+ insn->tag = S390_INSN_XINDIR;
+ insn->size = 0; /* does not matter */
+
+ insn->variant.xindir.cond = cond;
+ insn->variant.xindir.dst = dst;
+ insn->variant.xindir.guest_IA = guest_IA;
+
+ return insn;
+}
+
+
+s390_insn *
+s390_insn_xassisted(s390_cc_t cond, HReg dst, s390_amode *guest_IA,
+ IRJumpKind kind)
+{
+ s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
+
+ insn->tag = S390_INSN_XASSISTED;
+ insn->size = 0; /* does not matter */
+
+ insn->variant.xassisted.cond = cond;
+ insn->variant.xassisted.dst = dst;
+ insn->variant.xassisted.guest_IA = guest_IA;
+ insn->variant.xassisted.kind = kind;
+
+ return insn;
+}
+
+
+s390_insn *
+s390_insn_evcheck(s390_amode *counter, s390_amode *fail_addr)
+{
+ s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
+
+ vassert(counter->tag == S390_AMODE_B12);
+ vassert(fail_addr->tag == S390_AMODE_B12);
+
+ insn->tag = S390_INSN_EVCHECK;
+ insn->size = 0; /* does not matter */
+
+ insn->variant.evcheck.counter = counter;
+ insn->variant.evcheck.fail_addr = fail_addr;
+
+ return insn;
+}
+
+
+s390_insn *
+s390_insn_profinc(void)
+{
+ s390_insn *insn = LibVEX_Alloc(sizeof(s390_insn));
+
+ insn->tag = S390_INSN_PROFINC;
+ insn->size = 0; /* does not matter */
+
+ return insn;
+}
+
+
/*---------------------------------------------------------------*/
/*--- Debug print ---*/
/*---------------------------------------------------------------*/
@@ -4431,6 +4752,31 @@
}
+static const HChar *
+s390_jump_kind_as_string(IRJumpKind kind)
+{
+ switch (kind) {
+ case Ijk_Boring: return "Boring";
+ case Ijk_Call: return "Call";
+ case Ijk_Ret: return "Return";
+ case Ijk_ClientReq: return "ClientReq";
+ case Ijk_Yield: return "Yield";
+ case Ijk_EmWarn: return "EmWarn";
+ case Ijk_EmFail: return "EmFail";
+ case Ijk_NoDecode: return "NoDecode";
+ case Ijk_MapFail: return "MapFail";
+ case Ijk_TInval: return "Invalidate";
+ case Ijk_NoRedir: return "NoRedir";
+ case Ijk_SigTRAP: return "SigTRAP";
+ case Ijk_SigSEGV: return "SigSEGV";
+ case Ijk_SigBUS: return "SigBUS";
+ case Ijk_Sys_syscall: return "Sys_syscall";
+ default:
+ vpanic("s390_jump_kind_as_string");
+ }
+}
+
+
/* Helper function for writing out a V insn */
static void
s390_sprintf(HChar *buf, HChar *fmt, ...)
@@ -4472,10 +4818,19 @@
s390_amode_as_string(va_arg(args, s390_amode *)));
continue;
+ case 'G': /* %G = guest state @ offset */
+ p += vex_sprintf(p, "guest[%d]", va_arg(args, UInt));
+ continue;
+
case 'C': /* %C = condition code */
p += vex_sprintf(p, "%s", s390_cc_as_string(va_arg(args, s390_cc_t)));
continue;
+ case 'J': /* &J = jump kind */
+ p += vex_sprintf(p, "%s",
+ s390_jump_kind_as_string(va_arg(args, IRJumpKind)));
+ continue;
+
case 'L': { /* %L = argument list in helper call*/
UInt i, num_args;
@@ -4585,8 +4940,7 @@
case S390_ALU_RSHA: op = "v-rsha"; break;
default: goto fail;
}
- s390_sprintf(buf, "%M %R,%R,%O", op, insn->variant.alu.dst,
- insn->variant.alu.dst /* op1 same as dst */,
+ s390_sprintf(buf, "%M %R,%O", op, insn->variant.alu.dst, /* also op1 */
&insn->variant.alu.op2);
break;
@@ -4660,6 +5014,14 @@
insn->variant.cas.old_mem);
break;
+ case S390_INSN_CDAS:
+ s390_sprintf(buf, "%M %R,%R,%A,%R,%R,%R,%R", "v-cdas",
+ insn->variant.cdas.op1_high, insn->variant.cdas.op1_low,
+ insn->variant.cdas.op2, insn->variant.cdas.op3_high,
+ insn->variant.cdas.op3_low, insn->variant.cdas.old_mem_high,
+ insn->variant.cdas.old_mem_low);
+ break;
+
case S390_INSN_COMPARE:
if (insn->variant.compare.signed_comparison) {
op = "v-cmps";
@@ -4670,43 +5032,22 @@
&insn->variant.compare.src2);
break;
- case S390_INSN_BRANCH:
- switch (insn->variant.branch.kind) {
- case Ijk_ClientReq: op = "clientreq"; break;
- case Ijk_Sys_syscall: op = "syscall"; break;
- case Ijk_Yield: op = "yield"; break;
- case Ijk_EmWarn: op = "emwarn"; break;
- case Ijk_EmFail: op = "emfail"; break;
- case Ijk_MapFail: op = "mapfail"; break;
- case Ijk_NoDecode: op = "nodecode"; break;
- case Ijk_TInval: op = "tinval"; break;
- case Ijk_NoRedir: op = "noredir"; break;
- case Ijk_SigTRAP: op = "sigtrap"; break;
- case Ijk_Boring: op = "goto"; break;
- case Ijk_Call: op = "call"; break;
- case Ijk_Ret: op = "return"; break;
- default:
- goto fail;
- }
- s390_sprintf(buf, "if (%C) %s %O", insn->variant.branch.cond, op,
- &insn->variant.branch.dst);
- break;
-
case S390_INSN_HELPER_CALL: {
-
- if (insn->variant.helper_call.cond != S390_CC_ALWAYS) {
+ if (insn->variant.helper_call.dst != INVALID_HREG) {
+ s390_sprintf(buf, "%M if (%C) %R = %s{%I}(%L)", "v-call",
+ insn->variant.helper_call.cond,
+ insn->variant.helper_call.dst,
+ insn->variant.helper_call.name,
+ insn->variant.helper_call.target,
+ insn->variant.helper_call.num_args);
+ } else {
s390_sprintf(buf, "%M if (%C) %s{%I}(%L)", "v-call",
insn->variant.helper_call.cond,
insn->variant.helper_call.name,
insn->variant.helper_call.target,
insn->variant.helper_call.num_args);
- } else {
- s390_sprintf(buf, "%M %s{%I}(%L)", "v-call",
- insn->variant.helper_call.name,
- insn->variant.helper_call.target,
- insn->variant.helper_call.num_args);
}
- break;
+ return buf; /* avoid printing "size = ..." which is meaningless */
}
case S390_INSN_BFP_TRIOP:
@@ -4715,7 +5056,7 @@
case S390_BFP_MSUB: op = "v-fmsub"; break;
default: goto fail;
}
- s390_sprintf(buf, "%M %R,%R,%R,%R", op, insn->variant.bfp_triop.dst,
+ s390_sprintf(buf, "%M %R,%R,%R", op,
insn->variant.bfp_triop.dst /* op1 same as dst */,
insn->variant.bfp_triop.op2, insn->variant.bfp_triop.op3);
break;
@@ -4728,7 +5069,7 @@
case S390_BFP_DIV: op = "v-fdiv"; break;
default: goto fail;
}
- s390_sprintf(buf, "%M %R,%R,%R", op, insn->variant.bfp_binop.dst,
+ s390_sprintf(buf, "%M %R,%R", op,
insn->variant.bfp_binop.dst /* op1 same as dst */,
insn->variant.bfp_binop.op2);
break;
@@ -4777,7 +5118,7 @@
default: goto fail;
}
/* Only write the register that identifies the register pair */
- s390_sprintf(buf, "%M %R,%R,%R", op, insn->variant.bfp128_binop.dst_hi,
+ s390_sprintf(buf, "%M %R,%R", op,
insn->variant.bfp128_binop.dst_hi /* op1 same as dst */,
insn->variant.bfp128_binop.op2_hi);
break;
@@ -4816,6 +5157,50 @@
s390_sprintf(buf, "%M", "v-mfence");
return buf; /* avoid printing "size = ..." which is meaningless */
+ case S390_INSN_GZERO:
+ s390_sprintf(buf, "%M %G", "v-gzero", insn->variant.gzero.offset);
+ break;
+
+ case S390_INSN_GADD:
+ s390_sprintf(buf, "%M %G += %I (= %I)", "v-gadd",
+ insn->variant.gadd.offset,
+ (Long)(Char)insn->variant.gadd.delta,
+ insn->variant.gadd.value);
+ break;
+
+ case S390_INSN_EVCHECK:
+ s390_sprintf(buf, "%M counter = %A, fail-addr = %A", "v-evcheck",
+ insn->variant.evcheck.counter,
+ insn->variant.evcheck.fail_addr);
+ return buf; /* avoid printing "size = ..." which is meaningless */
+
+ case S390_INSN_PROFINC:
+ s390_sprintf(buf, "%M", "v-profinc");
+ return buf; /* avoid printing "size = ..." which is meaningless */
+
+ case S390_INSN_XDIRECT:
+ s390_sprintf(buf, "%M if (%C) %A = %I %s", "v-xdirect",
+ insn->variant.xdirect.cond,
+ insn->variant.xdirect.guest_IA,
+ insn->variant.xdirect.dst,
+ insn->variant.xdirect.to_fast_entry ? "fast" : "slow");
+ return buf; /* avoid printing "size = ..." which is meaningless */
+
+ case S390_INSN_XINDIR:
+ s390_sprintf(buf, "%M if (%C) %A = %R", "v-xindir",
+ insn->variant.xindir.cond,
+ insn->variant.xindir.guest_IA,
+ insn->variant.xindir.dst);
+ return buf; /* avoid printing "size = ..." which is meaningless */
+
+ case S390_INSN_XASSISTED:
+ s390_sprintf(buf, "%M if (%C) %J %A = %R", "v-xassisted",
+ insn->variant.xassisted.cond,
+ insn->variant.xassisted.kind,
+ insn->variant.xassisted.guest_IA,
+ insn->variant.xassisted.dst);
+ return buf; /* avoid printing "size = ..." which is meaningless */
+
default: goto fail;
}
@@ -5120,10 +5505,22 @@
if (dst_class == HRcFlt64)
return s390_emit_LDR(buf, dst, src);
} else {
- if (dst_class == HRcFlt64 && src_class == HRcInt64)
- return s390_emit_LDGRw(buf, dst, src);
- if (dst_class == HRcInt64 && src_class == HRcFlt64)
- return s390_emit_LGDRw(buf, dst, src);
+ if (dst_class == HRcFlt64 && src_class == HRcInt64) {
+ if (insn->size == 4) {
+ buf = s390_emit_SLLG(buf, R0, src, 0, DISP20(32)); /* r0 = src << 32 */
+ return s390_emit_LDGRw(buf, dst, R0);
+ } else {
+ return s390_emit_LDGRw(buf, dst, src);
+ }
+ }
+ if (dst_class == HRcInt64 && src_class == HRcFlt64) {
+ if (insn->size == 4) {
+ buf = s390_emit_LGDRw(buf, dst, src);
+ return s390_emit_SRLG(buf, dst, dst, 0, DISP20(32)); /* dst >>= 32 */
+ } else {
+ return s390_emit_LGDRw(buf, dst, src);
+ }
+ }
/* A move between floating point registers and general purpose
registers of different size should never occur and indicates
an error elsewhere. */
@@ -5953,6 +6350,66 @@
}
+/* Only 4-byte and 8-byte operands are handled. */
+static UChar *
+s390_insn_cdas_emit(UChar *buf, const s390_insn *insn)
+{
+ UChar r1, r1p1, r3, /*r3p1,*/ b, old_high, old_low, scratch;
+ Int d;
+ s390_amode *am;
+
+ r1 = hregNumber(insn->variant.cdas.op1_high); /* expected value */
+ r1p1 = hregNumber(insn->variant.cdas.op1_low); /* expected value */
+ r3 = hregNumber(insn->variant.cdas.op3_high);
+ /* r3p1 = hregNumber(insn->variant.cdas.op3_low); */ /* unused */
+ old_high = hregNumber(insn->variant.cdas.old_mem_high);
+ old_low = hregNumber(insn->variant.cdas.old_mem_low);
+ scratch = hregNumber(insn->variant.cdas.scratch);
+ am = insn->variant.cdas.op2;
+ b = hregNumber(am->b);
+ d = am->d;
+
+ vassert(scratch == 1);
+
+ switch (insn->size) {
+ case 4:
+ /* r1, r1+1 must not be overwritten. So copy them to R0,scratch
+ and let CDS/CDSY clobber it */
+ buf = s390_emit_LR(buf, R0, r1);
+ buf = s390_emit_LR(buf, scratch, r1p1);
+
+ if (am->tag == S390_AMODE_B12)
+ buf = s390_emit_CDS(buf, R0, r3, b, d);
+ else
+ buf = s390_emit_CDSY(buf, R0, r3, b, DISP20(d));
+
+ /* Now copy R0,scratch which has the old memory value to OLD */
+ buf = s390_emit_LR(buf, old_high, R0);
+ buf = s390_emit_LR(buf, old_low, scratch);
+ return buf;
+
+ case 8:
+ /* r1, r1+1 must not be overwritten. So copy them to R0,scratch
+ and let CDSG clobber it */
+ buf = s390_emit_LGR(buf, R0, r1);
+ buf = s390_emit_LGR(buf, scratch, r1p1);
+
+ buf = s390_emit_CDSG(buf, R0, r3, b, DISP20(d));
+
+ /* Now copy R0,scratch which has the old memory value to OLD */
+ buf = s390_emit_LGR(buf, old_high, R0);
+ buf = s390_emit_LGR(buf, old_low, scratch);
+ return buf;
+
+ default:
+ goto fail;
+ }
+
+ fail:
+ vpanic("s390_insn_cas_emit");
+}
+
+
/* Only 4-byte and 8-byte comparisons are handled. 1-byte and 2-byte
comparisons will have been converted to 4-byte comparisons in
s390_isel_cc and should not occur here. */
@@ -6039,6 +6496,15 @@
return s390_emit_CLFIw(buf, r1, value);
case 8:
+ if (s390_host_has_eimm) {
+ if (signed_comparison) {
+ if (ulong_fits_signed_32bit(value))
+ return s390_emit_CGFI(buf, r1, value);
+ } else {
+ if (ulong_fits_unsigned_32bit(value))
+ return s390_emit_CLGFI(buf, r1, value);
+ }
+ }
buf = s390_emit_load_64imm(buf, R0, value);
if (signed_comparison)
return s390_emit_CGR(buf, r1, R0);
@@ -6392,104 +6858,6 @@
static UChar *
-s390_insn_branch_emit(UChar *buf, const s390_insn *insn)
-{
- s390_opnd_RMI dst;
- s390_cc_t cond;
- UInt trc;
- UChar *p, *ptmp = 0; /* avoid compiler warnings */
-
- cond = insn->variant.branch.cond;
- dst = insn->variant.branch.dst;
-
- p = buf;
- trc = 0;
-
- if (cond != S390_CC_ALWAYS) {
- /* So we have something like this
- if (cond) goto X;
- Y: ...
- We convert this into
- if (! cond) goto Y; // BRC insn; 4 bytes
- return_reg = X;
- return to dispatcher
- Y:
- */
- ptmp = p; /* 4 bytes (a BRC insn) to be filled in here */
- p += 4;
- }
-
- /* If a non-boring, set guest-state-pointer appropriately. */
-
- switch (insn->variant.branch.kind) {
- case Ijk_ClientReq: trc = VEX_TRC_JMP_CLIENTREQ; break;
- case Ijk_Sys_syscall: trc = VEX_TRC_JMP_SYS_SYSCALL; break;
- case Ijk_Yield: trc = VEX_TRC_JMP_YIELD; break;
- case Ijk_EmWarn: trc = VEX_TRC_JMP_EMWARN; break;
- case Ijk_EmFail: trc = VEX_TRC_JMP_EMFAIL; break;
- case Ijk_MapFail: trc = VEX_TRC_JMP_MAPFAIL; break;
- case Ijk_NoDecode: trc = VEX_TRC_JMP_NODECODE; break;
- case Ijk_TInval: trc = VEX_TRC_JMP_TINVAL; break;
- case Ijk_NoRedir: trc = VEX_TRC_JMP_NOREDIR; break;
- case Ijk_SigTRAP: trc = VEX_TRC_JMP_SIGTRAP; break;
- case Ijk_Ret: trc = 0; break;
- case Ijk_Call: trc = 0; break;
- case Ijk_Boring: trc = 0; break;
- break;
-
- default:
- vpanic("s390_insn_branch_emit: unknown jump kind");
- }
-
- /* Get the destination address into the return register */
- switch (dst.tag) {
- case S390_OPND_REG:
- p = s390_emit_LGR(p, S390_REGNO_RETURN_VALUE, hregNumber(dst.variant.reg));
- break;
-
- case S390_OPND_AMODE: {
- const s390_amode *am = dst.variant.am;
- UChar b = hregNumber(am->b);
- UChar x = hregNumber(am->x);
- Int d = am->d;
-
- p = s390_emit_LG(p, S390_REGNO_RETURN_VALUE, x, b, DISP20(d));
- break;
- }
-
- case S390_OPND_IMMEDIATE:
- p = s390_emit_load_64imm(p, S390_REGNO_RETURN_VALUE, dst.variant.imm);
- break;
-
- default:
- goto fail;
- }
-
- if (trc != 0) {
- /* Something special. Set guest-state pointer appropriately */
- p = s390_emit_LGHI(p, S390_REGNO_GUEST_STATE_POINTER, trc);
- } else {
- /* Nothing special needs to be done for calls and returns. */
- }
-
- p = s390_emit_BCR(p, S390_CC_ALWAYS, S390_REGNO_LINK_REGISTER);
-
- if (cond != S390_CC_ALWAYS) {
- Int delta = p - ptmp;
-
- delta >>= 1; /* immediate constant is #half-words */
- vassert(delta > 0 && delta < (1 << 16));
- s390_emit_BRC(ptmp, s390_cc_invert(cond), delta);
- }
-
- return p;
-
- fail:
- vpanic("s390_insn_branch_emit");
-}
-
-
-static UChar *
s390_insn_helper_call_emit(UChar *buf, const s390_insn *insn)
{
s390_cc_t cond;
@@ -6515,7 +6883,8 @@
/* Load the target address into a register, that
(a) is not used for passing parameters to the helper and
(b) can be clobbered by the callee
- r1 looks like a good choice.
+ (c) is not special to the BASR insn
+ r1 is the only choice.
Also, need to arrange for the return address be put into the
link-register */
buf = s390_emit_load_64imm(buf, 1, target);
@@ -6534,6 +6903,13 @@
buf = s390_emit_STG(buf, S390_REGNO_LINK_REGISTER, 0, // save LR
S390_REGNO_STACK_POINTER, S390_OFFSET_SAVED_LR, 0);
buf = s390_emit_BASR(buf, S390_REGNO_LINK_REGISTER, 1); // call helper
+
+ /* Move the return value to the destination register */
+ if (insn->variant.helper_call.dst != INVALID_HREG) {
+ buf = s390_emit_LGR(buf, hregNumber(insn->variant.helper_call.dst),
+ S390_REGNO_RETURN_VALUE);
+ }
+
buf = s390_emit_LG(buf, S390_REGNO_LINK_REGISTER, 0, // restore LR
S390_REGNO_STACK_POINTER, S390_OFFSET_SAVED_LR, 0);
buf = s390_emit_LFPC(buf, S390_REGNO_STACK_POINTER, // restore FPC
@@ -6641,7 +7017,7 @@
/* Copy FPC from guest state to R0 and OR in the new rounding mode */
buf = s390_emit_L(buf, R0, 0, S390_REGNO_GUEST_STATE_POINTER,
- OFFSET_s390x_fpc); // r0 = guest_fpc
+ S390X_GUEST_OFFSET(guest_fpc)); // r0 = guest_fpc
buf = s390_emit_NILL(buf, R0, 0xFFFC); /* Clear out right-most 2 bits */
buf = s390_emit_OILL(buf, R0, bits); /* OR in the new rounding mode */
@@ -6686,7 +7062,7 @@
if (rounding_mode != S390_ROUND_NEAREST_EVEN) {
/* Restore FPC register from guest state */
buf = s390_emit_LFPC(buf, S390_REGNO_GUEST_STATE_POINTER,
- OFFSET_s390x_fpc); // fpc = guest_fpc
+ S390X_GUEST_OFFSET(guest_fpc)); // fpc = guest_fpc
}
return buf;
@@ -6733,7 +7109,7 @@
if (rounding_mode != S390_ROUND_NEAREST_EVEN) {
/* Restore FPC register from guest state */
buf = s390_emit_LFPC(buf, S390_REGNO_GUEST_STATE_POINTER,
- OFFSET_s390x_fpc);
+ S390X_GUEST_OFFSET(guest_fpc));
}
return buf;
@@ -6822,7 +7198,7 @@
if (rounding_mode != S390_ROUND_NEAREST_EVEN) {
/* Restore FPC register from guest state */
buf = s390_emit_LFPC(buf, S390_REGNO_GUEST_STATE_POINTER,
- OFFSET_s390x_fpc); // fpc = guest_fpc
+ S390X_GUEST_OFFSET(guest_fpc)); // fpc = guest_fpc
}
return buf;
@@ -6888,7 +7264,7 @@
if (rounding_mode != S390_ROUND_NEAREST_EVEN) {
/* Restore FPC register from guest state */
buf = s390_emit_LFPC(buf, S390_REGNO_GUEST_STATE_POINTER,
- OFFSET_s390x_fpc); // fpc = guest_fpc
+ S390X_GUEST_OFFSET(guest_fpc)); // fpc = guest_fpc
}
return buf;
@@ -6953,7 +7329,7 @@
if (rounding_mode != S390_ROUND_NEAREST_EVEN) {
/* Restore FPC register from guest state */
buf = s390_emit_LFPC(buf, S390_REGNO_GUEST_STATE_POINTER,
- OFFSET_s390x_fpc); // fpc = guest_fpc
+ S390X_GUEST_OFFSET(guest_fpc)); // fpc = guest_fpc
}
return buf;
@@ -6996,7 +7372,7 @@
UInt r1 = hregNumber(insn->variant.bfp128_unop.dst_hi);
UInt r2_hi = hregNumber(insn->variant.bfp128_unop.op_hi);
UInt r2_lo = hregNumber(insn->variant.bfp128_unop.op_lo);
- s390_round_t rounding_mode = insn->variant.bfp_binop.rounding_mode;
+ s390_round_t rounding_mode = insn->variant.bfp128_unop.rounding_mode;
/* Paranoia */
vassert(insn->size != 16);
@@ -7007,10 +7383,12 @@
mode and no FPC modification is necessary. So we handle them
upfront. */
switch (insn->variant.bfp_unop.tag) {
- case S390_BFP_F128_TO_I32: return s390_emit_CFXBR(buf, rounding_mode,
- r1, r2_hi); break;
- case S390_BFP_F128_TO_I64: return s390_emit_CGXBR(buf, rounding_mode,
- r1, r2_hi); break;
+ case S390_BFP_F128_TO_I32:
+ return s390_emit_CFXBR(buf, rounding_mode, r1, r2_hi);
+
+ case S390_BFP_F128_TO_I64:
+ return s390_emit_CGXBR(buf, rounding_mode, r1, r2_hi);
+
default: break;
}
@@ -7025,9 +7403,459 @@
}
+static UChar *
+s390_insn_gzero_emit(UChar *buf, const s390_insn *insn)
+{
+ return s390_emit_XC(buf, insn->size - 1,
+ S390_REGNO_GUEST_STATE_POINTER, insn->variant.gzero.offset,
+ S390_REGNO_GUEST_STATE_POINTER, insn->variant.gzero.offset);
+}
+
+
+static UChar *
+s390_insn_gadd_emit(UChar *buf, const s390_insn *insn)
+{
+ return s390_emit_AGSI(buf, insn->variant.gadd.delta,
+ S390_REGNO_GUEST_STATE_POINTER,
+ DISP20(insn->variant.gadd.offset));
+}
+
+
+/* Define convenience functions needed for translation chaining.
+ Any changes need to be applied to the functions in concert. */
+
+static __inline__ Bool
+s390_insn_is_BRCL(const UChar *p, UChar condition)
+{
+ return p[0] == 0xc0 && p[1] == ((condition << 4) | 0x04);
+}
+
+static __inline__ Bool
+s390_insn_is_BR(const UChar *p, UChar reg)
+{
+ return p[0] == 0x07 && p[1] == (0xF0 | reg); /* BCR 15,reg */
+}
+
+
+/* The length of the BASR insn */
+#define S390_BASR_LEN 2
+
+
+/* Load the 64-bit VALUE into REG. Note that this function must NOT
+ optimise the generated code by looking at the value. I.e. using
+ LGHI if value == 0 would be very wrong. */
+static UChar *
+s390_tchain_load64(UChar *buf, UChar regno, ULong value)
+{
+ UChar *begin = buf;
+
+ if (s390_host_has_eimm) {
+ /* Do it in two steps: upper half [0:31] and lower half [32:63] */
+ buf = s390_emit_IIHF(buf, regno, value >> 32);
+ buf = s390_emit_IILF(buf, regno, value & 0xFFFFFFFF);
+ } else {
+ buf = s390_emit_IILL(buf, regno, value & 0xFFFF);
+ value >>= 16;
+ buf = s390_emit_IILH(buf, regno, value & 0xFFFF);
+ value >>= 16;
+ buf = s390_emit_IIHL(buf, regno, value & 0xFFFF);
+ value >>= 16;
+ buf = s390_emit_IIHH(buf, regno, value & 0xFFFF);
+ }
+
+ vassert(buf - begin == s390_tchain_load64_len());
+
+ return buf;
+}
+
+/* Return number of bytes generated by s390_tchain_load64 */
+static UInt
+s390_tchain_load64_len(void)
+{
+ if (s390_host_has_eimm) {
+ return 6 + 6; /* IIHF + IILF */
+ }
+ return 4 + 4 + 4 + 4; /* IIHH + IIHL + IILH + IILL */
+}
+
+/* Verify that CODE is the code sequence generated by s390_tchain_load64
+ to load VALUE into REGNO. Return pointer to the byte following the
+ insn sequence. */
+static const UChar *
+s390_tchain_verify_load64(const UChar *code, UChar regno, ULong value)
+{
+ UInt regmask = regno << 4;
+ UInt hw;
+
+ if (s390_host_has_eimm) {
+ /* Check for IIHF */
+ vassert(code[0] == 0xC0);
+ vassert(code[1] == (0x08 | regmask));
+ vassert(*(const UInt *)&code[2] == (value >> 32));
+ /* Check for IILF */
+ vassert(code[6] == 0xC0);
+ vassert(code[7] == (0x09 | regmask));
+ vassert(*(const UInt *)&code[8] == (value & 0xFFFFFFFF));
+ } else {
+ /* Check for IILL */
+ hw = value & 0xFFFF;
+ vassert(code[0] == 0xA5);
+ vassert(code[1] == (0x03 | regmask));
+ vassert(code[2] == (hw >> 8));
+ vassert(code[3] == (hw & 0xFF));
+
+ /* Check for IILH */
+ hw = (value >> 16) & 0xFFFF;
+ vassert(code[4] == 0xA5);
+ vassert(code[5] == (0x02 | regmask));
+ vassert(code[6] == (hw >> 8));
+ vassert(code[7] == (hw & 0xFF));
+
+ /* Check for IIHL */
+ hw = (value >> 32) & 0xFFFF;
+ vassert(code[8] == 0xA5);
+ vassert(code[9] == (0x01 | regmask));
+ vassert(code[10] == (hw >> 8));
+ vassert(code[11] == (hw & 0xFF));
+
+ /* Check for IIHH */
+ hw = (value >> 48) & 0xFFFF;
+ vassert(code[12] == 0xA5);
+ vassert(code[13] == (0x00 | regmask));
+ vassert(code[14] == (hw >> 8));
+ vassert(code[15] == (hw & 0xFF));
+ }
+
+ return code + s390_tchain_load64_len();
+}
+
+/* CODE points to the code sequence as generated by s390_tchain_load64.
+ Change the loaded value to VALUE. Return pointer to the byte following
+ the patched code sequence. */
+static UChar *
+s390_tchain_patch_load64(UChar *code, ULong imm64)
+{
+ if (s390_host_has_eimm) {
+ /* Patch IIHF */
+ *(UInt *)&code[2] = imm64 >> 32;
+ /* Patch IILF */
+ *(UInt *)&code[8] = imm64 & 0xFFFFFFFF;
+ } else {
+ code[3] = imm64 & 0xFF; imm64 >>= 8;
+ code[2] = imm64 & 0xFF; imm64 >>= 8;
+ code[7] = imm64 & 0xFF; imm64 >>= 8;
+ code[6] = imm64 & 0xFF; imm64 >>= 8;
+ code[11] = imm64 & 0xFF; imm64 >>= 8;
+ code[10] = imm64 & 0xFF; imm64 >>= 8;
+ code[15] = imm64 & 0xFF; imm64 >>= 8;
+ code[14] = imm64 & 0xFF; imm64 >>= 8;
+ }
+
+ return code + s390_tchain_load64_len();
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ chainXDirect_S390 and unchainXDirect_S390 below. */
+static UChar *
+s390_insn_xdirect_emit(UChar *buf, const s390_insn *insn,
+ void *disp_cp_chain_me_to_slowEP,
+ void *disp_cp_chain_me_to_fastEP)
+{
+ /* We're generating chain-me requests here, so we need to be
+ sure this is actually allowed -- no-redir translations can't
+ use chain-me's. Hence: */
+ vassert(disp_cp_chain_me_to_slowEP != NULL);
+ vassert(disp_cp_chain_me_to_fastEP != NULL);
+
+ /* Use ptmp for backpatching conditional jumps. */
+ UChar *ptmp = buf;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. */
+ s390_cc_t cond = insn->variant.xdirect.cond;
+
+ if (cond != S390_CC_ALWAYS) {
+ /* So we have something like this
+ if (cond) do_xdirect;
+ Y: ...
+ We convert this into
+ if (! cond) goto Y; // BRC opcode; 4 bytes
+ do_xdirect;
+ Y:
+ */
+ /* 4 bytes (a BRC insn) to be filled in here */
+ buf += 4;
+ }
+
+ /* Update the guest IA. */
+ buf = s390_emit_load_64imm(buf, R0, insn->variant.xdirect.dst);
+
+ const s390_amode *amode = insn->variant.xdirect.guest_IA;
+ vassert(amode->tag == S390_AMODE_B12);
+ UInt b = hregNumber(amode->b);
+ UInt d = amode->d;
+
+ buf = s390_emit_STG(buf, R0, 0, b, DISP20(d));
+
+ /* Load the chosen entry point into the scratch reg */
+ void *disp_cp_chain_me;
+
+ disp_cp_chain_me =
+ insn->variant.xdirect.to_fast_entry ? disp_cp_chain_me_to_fastEP
+ : disp_cp_chain_me_to_slowEP;
+ /* Get the address of the beginning of the load64 code sequence into %r1.
+ Do not change the register! This is part of the protocol with the
+ dispatcher. */
+ buf = s390_emit_BASR(buf, 1, R0);
+
+ /* --- FIRST PATCHABLE BYTE follows (must not modify %r1) --- */
+ ULong addr = Ptr_to_ULong(disp_cp_chain_me);
+ buf = s390_tchain_load64(buf, S390_REGNO_TCHAIN_SCRATCH, addr);
+
+ /* goto *tchain_scratch */
+ buf = s390_emit_BCR(buf, S390_CC_ALWAYS, S390_REGNO_TCHAIN_SCRATCH);
+
+ /* --- END of PATCHABLE BYTES --- */
+
+ /* Fix up the conditional jump, if there was one. */
+ if (cond != S390_CC_ALWAYS) {
+ Int delta = buf - ptmp;
+
+ delta >>= 1; /* immediate constant is #half-words */
+ vassert(delta > 0 && delta < (1 << 16));
+ s390_emit_BRC(ptmp, s390_cc_invert(cond), delta);
+ }
+
+ return buf;
+}
+
+/* Return the number of patchable bytes from an xdirect insn. */
+static UInt
+s390_xdirect_patchable_len(void)
+{
+ return s390_tchain_load64_len() + S390_BASR_LEN;
+}
+
+
+static UChar *
+s390_insn_xindir_emit(UChar *buf, const s390_insn *insn, void *disp_cp_xindir)
+{
+ /* We're generating transfers that could lead indirectly to a
+ chain-me, so we need to be sure this is actually allowed --
+ no-redir translations are not allowed to reach normal
+ translations without going through the scheduler. That means
+ no XDirects or XIndirs out from no-redir translations.
+ Hence: */
+ vassert(disp_cp_xindir != NULL);
+
+ /* Use ptmp for backpatching conditional jumps. */
+ UChar *ptmp = buf;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. */
+ s390_cc_t cond = insn->variant.xdirect.cond;
+
+ if (cond != S390_CC_ALWAYS) {
+ /* So we have something like this
+ if (cond) do_xdirect;
+ Y: ...
+ We convert this into
+ if (! cond) goto Y; // BRC opcode; 4 bytes
+ do_xdirect;
+ Y:
+ */
+ /* 4 bytes (a BRC insn) to be filled in here */
+ buf += 4;
+ }
+
+ /* Update the guest IA with the address in xdirect.dst. */
+ const s390_amode *amode = insn->variant.xindir.guest_IA;
+
+ vassert(amode->tag == S390_AMODE_B12);
+ UInt b = hregNumber(amode->b);
+ UInt d = amode->d;
+ UInt regno = hregNumber(insn->variant.xindir.dst);
+
+ buf = s390_emit_STG(buf, regno, 0, b, DISP20(d));
+
+ /* load tchain_scratch, #disp_indir */
+ buf = s390_tchain_load64(buf, S390_REGNO_TCHAIN_SCRATCH,
+ Ptr_to_ULong(disp_cp_xindir));
+ /* goto *tchain_direct */
+ buf = s390_emit_BCR(buf, S390_CC_ALWAYS, S390_REGNO_TCHAIN_SCRATCH);
+
+ /* Fix up the conditional jump, if there was one. */
+ if (cond != S390_CC_ALWAYS) {
+ Int delta = buf - ptmp;
+
+ delta >>= 1; /* immediate constant is #half-words */
+ vassert(delta > 0 && delta < (1 << 16));
+ s390_emit_BRC(ptmp, s390_cc_invert(cond), delta);
+ }
+
+ return buf;
+}
+
+static UChar *
+s390_insn_xassisted_emit(UChar *buf, const s390_insn *insn,
+ void *disp_cp_xassisted)
+{
+ /* Use ptmp for backpatching conditional jumps. */
+ UChar *ptmp = buf;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. */
+ s390_cc_t cond = insn->variant.xdirect.cond;
+
+ if (cond != S390_CC_ALWAYS) {
+ /* So we have something like this
+ if (cond) do_xdirect;
+ Y: ...
+ We convert this into
+ if (! cond) goto Y; // BRC opcode; 4 bytes
+ do_xdirect;
+ Y:
+ */
+ /* 4 bytes (a BRC insn) to be filled in here */
+ buf += 4;
+ }
+
+ /* Update the guest IA with the address in xassisted.dst. */
+ const s390_amode *amode = insn->variant.xassisted.guest_IA;
+
+ vassert(amode->tag == S390_AMODE_B12);
+ UInt b = hregNumber(amode->b);
+ UInt d = amode->d;
+ UInt regno = hregNumber(insn->variant.xassisted.dst);
+
+ buf = s390_emit_STG(buf, regno, 0, b, DISP20(d));
+
+ UInt trcval = 0;
+
+ switch (insn->variant.xassisted.kind) {
+ case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break;
+ case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break;
+ case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break;
+ case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
+ case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
+ case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
+ case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
+ case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
+ case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
+ case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break;
+ /* We don't expect to see the following being assisted. */
+ case Ijk_Ret:
+ case Ijk_Call:
+ /* fallthrough */
+ default:
+ ppIRJumpKind(insn->variant.xassisted.kind);
+ vpanic("s390_insn_xassisted_emit: unexpected jump kind");
+ }
+
+ vassert(trcval != 0);
+
+ /* guest_state_pointer = trcval */
+ buf = s390_emit_LGHI(buf, S390_REGNO_GUEST_STATE_POINTER, trcval);
+
+ /* load tchain_scratch, #disp_assisted */
+ buf = s390_tchain_load64(buf, S390_REGNO_TCHAIN_SCRATCH,
+ Ptr_to_ULong(disp_cp_xassisted));
+
+ /* goto *tchain_direct */
+ buf = s390_emit_BCR(buf, S390_CC_ALWAYS, S390_REGNO_TCHAIN_SCRATCH);
+
+ /* Fix up the conditional jump, if there was one. */
+ if (cond != S390_CC_ALWAYS) {
+ Int delta = buf - ptmp;
+
+ delta >>= 1; /* immediate constant is #half-words */
+ vassert(delta > 0 && delta < (1 << 16));
+ s390_emit_BRC(ptmp, s390_cc_invert(cond), delta);
+ }
+
+ return buf;
+}
+
+
+/* Pseudo code:
+
+ guest_state[host_EvC_COUNTER] -= 1;
+ if (guest_state[host_EvC_COUNTER] >= 0) goto nofail;
+ goto guest_state[host_EvC_FAILADDR];
+ nofail: ;
+
+ The dispatch counter is a 32-bit value. */
+static UChar *
+s390_insn_evcheck_emit(UChar *buf, const s390_insn *insn)
+{
+ s390_amode *amode;
+ UInt b, d;
+ UChar *code_begin, *code_end;
+
+ code_begin = buf;
+
+ amode = insn->variant.evcheck.counter;
+ vassert(amode->tag == S390_AMODE_B12);
+ b = hregNumber(amode->b);
+ d = amode->d;
+
+ /* Decrement the dispatch counter in the guest state */
+ if (s390_host_has_gie) {
+ buf = s390_emit_ASI(buf, -1, b, DISP20(d)); /* 6 bytes */
+ } else {
+ buf = s390_emit_LHI(buf, R0, -1); /* 4 bytes */
+ buf = s390_emit_A(buf, R0, 0, b, d); /* 4 bytes */
+ buf = s390_emit_ST(buf, R0, 0, b, d); /* 4 bytes */
+ }
+
+ /* Jump over the next insn if >= 0 */
+ buf = s390_emit_BRC(buf, S390_CC_HE, (4 + 6 + 2) / 2); /* 4 bytes */
+
+ /* Computed goto to fail_address */
+ amode = insn->variant.evcheck.fail_addr;
+ b = hregNumber(amode->b);
+ d = amode->d;
+ buf = s390_emit_LG(buf, S390_REGNO_TCHAIN_SCRATCH, 0, b, DISP20(d)); /* 6 bytes */
+ buf = s390_emit_BCR(buf, S390_CC_ALWAYS, S390_REGNO_TCHAIN_SCRATCH); /* 2 bytes */
+
+ code_end = buf;
+
+ /* Make sure the size of the generated code is identical to the size
+ returned by evCheckSzB_S390 */
+ vassert(evCheckSzB_S390() == code_end - code_begin);
+
+ return buf;
+}
+
+
+static UChar *
+s390_insn_profinc_emit(UChar *buf,
+ const s390_insn *insn __attribute__((unused)))
+{
+ /* Generate a code template to increment a memory location whose
+ address will be known later as an immediate value. This code
+ template will be patched once the memory location is known.
+ For now we do this with address == 0. */
+ buf = s390_tchain_load64(buf, S390_REGNO_TCHAIN_SCRATCH, 0);
+ if (s390_host_has_gie) {
+ buf = s390_emit_AGSI(buf, 1, S390_REGNO_TCHAIN_SCRATCH, DISP20(0));
+ } else {
+ buf = s390_emit_LGHI(buf, R0, 1);
+ buf = s390_emit_AG( buf, R0, 0, S390_REGNO_TCHAIN_SCRATCH, DISP20(0));
+ buf = s390_emit_STG(buf, R0, 0, S390_REGNO_TCHAIN_SCRATCH, DISP20(0));
+ }
+
+ return buf;
+}
+
+
Int
-emit_S390Instr(UChar *buf, Int nbuf, s390_insn *insn, Bool mode64,
- void *dispatch_unassisted, void *dispatch_assisted)
+emit_S390Instr(Bool *is_profinc, UChar *buf, Int nbuf, s390_insn *insn,
+ Bool mode64, void *disp_cp_chain_me_to_slowEP,
+ void *disp_cp_chain_me_to_fastEP, void *disp_cp_xindir,
+ void *disp_cp_xassisted)
{
UChar *end;
@@ -7088,14 +7916,12 @@
end = s390_insn_cas_emit(buf, insn);
break;
- case S390_INSN_COMPARE:
- end = s390_insn_compare_emit(buf, insn);
+ case S390_INSN_CDAS:
+ end = s390_insn_cdas_emit(buf, insn);
break;
- case S390_INSN_BRANCH:
- vassert(dispatch_unassisted == NULL);
- vassert(dispatch_assisted == NULL);
- end = s390_insn_branch_emit(buf, insn);
+ case S390_INSN_COMPARE:
+ end = s390_insn_compare_emit(buf, insn);
break;
case S390_INSN_HELPER_CALL:
@@ -7142,8 +7968,40 @@
end = s390_insn_mfence_emit(buf, insn);
break;
+ case S390_INSN_GZERO:
+ end = s390_insn_gzero_emit(buf, insn);
+ break;
+
+ case S390_INSN_GADD:
+ end = s390_insn_gadd_emit(buf, insn);
+ break;
+
+ case S390_INSN_PROFINC:
+ end = s390_insn_profinc_emit(buf, insn);
+ /* Tell the caller .. */
+ vassert(*is_profinc == False);
+ *is_profinc = True;
+ break;
+
+ case S390_INSN_EVCHECK:
+ end = s390_insn_evcheck_emit(buf, insn);
+ break;
+
+ case S390_INSN_XDIRECT:
+ end = s390_insn_xdirect_emit(buf, insn, disp_cp_chain_me_to_slowEP,
+ disp_cp_chain_me_to_fastEP);
+ break;
+
+ case S390_INSN_XINDIR:
+ end = s390_insn_xindir_emit(buf, insn, disp_cp_xindir);
+ break;
+
+ case S390_INSN_XASSISTED:
+ end = s390_insn_xassisted_emit(buf, insn, disp_cp_xassisted);
+ break;
+
default:
- vpanic("s390_insn_emit");
+ vpanic("emit_S390Instr");
}
vassert(end - buf <= nbuf);
@@ -7152,6 +8010,184 @@
}
+/* Return the number of bytes emitted for an S390_INSN_EVCHECK.
+ See s390_insn_evcheck_emit */
+Int
+evCheckSzB_S390(void)
+{
+ return s390_host_has_gie ? 18 : 24;
+}
+
+
+/* Patch the counter address into CODE_TO_PATCH as previously
+ generated by s390_insn_profinc_emit. */
+VexInvalRange
+patchProfInc_S390(void *code_to_patch, ULong *location_of_counter)
+{
+ vassert(sizeof(ULong *) == 8);
+
+ s390_tchain_verify_load64(code_to_patch, S390_REGNO_TCHAIN_SCRATCH, 0);
+
+ s390_tchain_patch_load64(code_to_patch, Ptr_to_ULong(location_of_counter));
+
+ VexInvalRange vir = {0, 0};
+ return vir;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ s390_insn_xdirect_emit code above. */
+VexInvalRange
+chainXDirect_S390(void *place_to_chain,
+ void *disp_cp_chain_me_EXPECTED,
+ void *place_to_jump_to)
+{
+ /* What we're expecting to see @ PLACE_TO_CHAIN is:
+
+ load tchain_scratch, #disp_cp_chain_me_EXPECTED
+ goto *tchain_scratch
+ */
+ const UChar *next;
+ next = s390_tchain_verify_load64(place_to_chain, S390_REGNO_TCHAIN_SCRATCH,
+ Ptr_to_ULong(disp_cp_chain_me_EXPECTED));
+ vassert(s390_insn_is_BR(next, S390_REGNO_TCHAIN_SCRATCH));
+
+ /* And what we want to change it to is either:
+ (general case):
+
+ load tchain_scratch, #place_to_jump_to
+ goto *tchain_scratch
+
+ ---OR---
+
+ in the case where the displacement is small enough
+
+ BRCL delta where delta is in half-words
+ invalid opcodes
+
+ In both cases the replacement has the same length as the original.
+ To remain sane & verifiable,
+ (1) limit the displacement for the short form to
+ (say) +/- one billion, so as to avoid wraparound
+ off-by-ones
+ (2) even if the short form is applicable, once every (say)
+ 1024 times use the long form anyway, so as to maintain
+ verifiability
+ */
+
+ /* This is the delta we need to put into a BRCL insn. Note, that the
+ offset in BRCL is in half-words. Hence division by 2. */
+ Long delta = (Long)((UChar *)place_to_jump_to - (UChar *)place_to_chain) / 2;
+ Bool shortOK = delta >= -1000*1000*1000 && delta < 1000*1000*1000;
+
+ static UInt shortCTR = 0; /* DO NOT MAKE NON-STATIC */
+ if (shortOK) {
+ shortCTR++; // thread safety bleh
+ if (0 == (shortCTR & 0x3FF)) {
+ shortOK = False;
+ if (0)
+ vex_printf("QQQ chainXDirect_S390: shortCTR = %u, "
+ "using long jmp\n", shortCTR);
+ }
+ }
+
+ /* And make the modifications. */
+ UChar *p = (UChar *)place_to_chain;
+ if (shortOK) {
+ p = s390_emit_BRCL(p, S390_CC_ALWAYS, delta); /* 6 bytes */
+
+ /* Make sure that BRCL fits into the patchable part of an xdirect
+ code sequence */
+ vassert(6 <= s390_xdirect_patchable_len());
+
+ /* Fill remaining bytes with 0x00 (invalid opcode) */
+ Int i;
+ for (i = 0; i < s390_xdirect_patchable_len() - 6; ++i)
+ p[i] = 0x00;
+ } else {
+ /*
+ load tchain_scratch, #place_to_jump_to
+ goto *tchain_scratch
+ */
+ ULong addr = Ptr_to_ULong(place_to_jump_to);
+ p = s390_tchain_load64(p, S390_REGNO_TCHAIN_SCRATCH, addr);
+ /* There is not need to emit a BCR here, as it is already there. */
+ }
+
+ VexInvalRange vir = {0, 0};
+ return vir;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ s390_insn_xdirect_emit code above. */
+VexInvalRange
+unchainXDirect_S390(void *place_to_unchain,
+ void *place_to_jump_to_EXPECTED,
+ void *disp_cp_chain_me)
+{
+ /* What we're expecting to see @ PLACE_TO_UNCHAIN:
+
+ load tchain_scratch, #place_to_jump_to_EXPECTED
+ goto *tchain_scratch
+
+ ---OR---
+ in the case where the displacement falls within 32 bits
+
+ BRCL delta
+ invalid opcodes
+ */
+ UChar *p = place_to_unchain;
+
+ Bool uses_short_form = False;
+
+ if (s390_insn_is_BRCL(p, S390_CC_ALWAYS)) {
+ /* Looks like the short form */
+ Int num_hw = *(Int *)&p[2];
+ Int delta = 2 *num_hw;
+
+ vassert(p + delta == place_to_jump_to_EXPECTED);
+
+ Int i;
+ for (i = 0; i < s390_xdirect_patchable_len() - 6; ++i)
+ vassert(p[6+i] == 0x00);
+ uses_short_form = True;
+ } else {
+ /* Should be the long form */
+ const UChar *next;
+
+ next = s390_tchain_verify_load64(p, S390_REGNO_TCHAIN_SCRATCH,
+ Ptr_to_ULong(place_to_jump_to_EXPECTED));
+ /* Check for BR *tchain_scratch */
+ vassert(s390_insn_is_BR(next, S390_REGNO_TCHAIN_SCRATCH));
+ }
+
+ /* And what we want to change it to is:
+
+ load tchain_scratch, #disp_cp_chain_me
+ goto *tchain_scratch
+ */
+
+ /* Get the address of the beginning of the load64 code sequence into %r1.
+ Do not change the register! This is part of the protocol with the
+ dispatcher.
+ Note: the incoming argument PLACE_TO_CHAIN points to the beginning of the
+ load64 insn sequence. That sequence is prefixed with a BASR to get its
+ address (see s390_insn_xdirect_emit). */
+ p = s390_emit_BASR(p - S390_BASR_LEN, 1, R0);
+
+ ULong addr = Ptr_to_ULong(disp_cp_chain_me);
+ p = s390_tchain_load64(p, S390_REGNO_TCHAIN_SCRATCH, addr);
+
+ /* Emit the BCR in case the short form was used. In case of the long
+ form, the BCR is already there. */
+ if (uses_short_form)
+ s390_emit_BCR(p, S390_CC_ALWAYS, S390_REGNO_TCHAIN_SCRATCH);
+
+ VexInvalRange vir = {0, 0};
+ return vir;
+}
+
/*---------------------------------------------------------------*/
/*--- end host_s390_defs.c ---*/
/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/host_s390_defs.h b/main/VEX/priv/host_s390_defs.h
index 2a5eddd..5c45797 100644
--- a/main/VEX/priv/host_s390_defs.h
+++ b/main/VEX/priv/host_s390_defs.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -130,9 +130,9 @@
S390_INSN_TEST, /* test operand and set cc */
S390_INSN_CC2BOOL,/* convert condition code to 0/1 */
S390_INSN_COMPARE,
- S390_INSN_BRANCH, /* un/conditional goto */
S390_INSN_HELPER_CALL,
S390_INSN_CAS, /* compare and swap */
+ S390_INSN_CDAS, /* compare double and swap */
S390_INSN_BFP_BINOP, /* Binary floating point 32-bit / 64-bit */
S390_INSN_BFP_UNOP,
S390_INSN_BFP_TRIOP,
@@ -142,7 +142,15 @@
S390_INSN_BFP128_COMPARE,
S390_INSN_BFP128_CONVERT_TO,
S390_INSN_BFP128_CONVERT_FROM,
- S390_INSN_MFENCE
+ S390_INSN_MFENCE,
+ S390_INSN_GZERO, /* Assign zero to a guest register */
+ S390_INSN_GADD, /* Add a value to a guest register */
+ /* The following 5 insns are mandated by translation chaining */
+ S390_INSN_XDIRECT, /* direct transfer to guest address */
+ S390_INSN_XINDIR, /* indirect transfer to guest address */
+ S390_INSN_XASSISTED, /* assisted transfer to guest address */
+ S390_INSN_EVCHECK, /* Event check */
+ S390_INSN_PROFINC /* 64-bit profile counter increment */
} s390_insn_tag;
@@ -337,10 +345,15 @@
HReg old_mem;
} cas;
struct {
- IRJumpKind kind;
- s390_cc_t cond;
- s390_opnd_RMI dst;
- } branch;
+ HReg op1_high;
+ HReg op1_low;
+ s390_amode *op2;
+ HReg op3_high;
+ HReg op3_low;
+ HReg old_mem_high;
+ HReg old_mem_low;
+ HReg scratch;
+ } cdas;
/* Pseudo-insn for representing a helper call.
TARGET is the absolute address of the helper function
NUM_ARGS says how many arguments are being passed.
@@ -351,6 +364,7 @@
s390_cc_t cond;
Addr64 target;
UInt num_args;
+ HReg dst; /* if not INVALID_HREG, put return value here */
HChar *name; /* callee's name (for debugging) */
} helper_call;
struct {
@@ -397,6 +411,52 @@
HReg op2_hi; /* right operand; high part */
HReg op2_lo; /* right operand; low part */
} bfp128_compare;
+ struct {
+ UInt offset;
+ } gzero;
+ struct {
+ UInt offset;
+ UChar delta;
+ ULong value; /* for debugging only */
+ } gadd;
+
+ /* The next 5 entries are generic to support translation chaining */
+
+ /* Update the guest IA value, then exit requesting to chain
+ to it. May be conditional. */
+ struct {
+ s390_cc_t cond;
+ Bool to_fast_entry; /* chain to the what entry point? */
+ Addr64 dst; /* next guest address */
+ s390_amode *guest_IA;
+ } xdirect;
+ /* Boring transfer to a guest address not known at JIT time.
+ Not chainable. May be conditional. */
+ struct {
+ s390_cc_t cond;
+ HReg dst;
+ s390_amode *guest_IA;
+ } xindir;
+ /* Assisted transfer to a guest address, most general case.
+ Not chainable. May be conditional. */
+ struct {
+ s390_cc_t cond;
+ IRJumpKind kind;
+ HReg dst;
+ s390_amode *guest_IA;
+ } xassisted;
+ struct {
+ /* fixs390: I don't think these are really needed
+ as the gsp and the offset are fixed no ? */
+ s390_amode *counter; /* dispatch counter */
+ s390_amode *fail_addr;
+ } evcheck;
+ struct {
+ /* No fields. The address of the counter to increment is
+ installed later, post-translation, by patching it in,
+ as it is not known at translation time. */
+ } profinc;
+
} variant;
} s390_insn;
@@ -417,15 +477,17 @@
s390_opnd_RMI op);
s390_insn *s390_insn_cas(UChar size, HReg op1, s390_amode *op2, HReg op3,
HReg old);
+s390_insn *s390_insn_cdas(UChar size, HReg op1_high, HReg op1_low,
+ s390_amode *op2, HReg op3_high, HReg op3_low,
+ HReg old_high, HReg old_low, HReg scratch);
s390_insn *s390_insn_unop(UChar size, s390_unop_t tag, HReg dst,
s390_opnd_RMI opnd);
s390_insn *s390_insn_cc2bool(HReg dst, s390_cc_t src);
s390_insn *s390_insn_test(UChar size, s390_opnd_RMI src);
s390_insn *s390_insn_compare(UChar size, HReg dst, s390_opnd_RMI opnd,
Bool signed_comparison);
-s390_insn *s390_insn_branch(IRJumpKind jk, s390_cc_t cond, s390_opnd_RMI dst);
s390_insn *s390_insn_helper_call(s390_cc_t cond, Addr64 target, UInt num_args,
- HChar *name);
+ HChar *name, HReg dst);
s390_insn *s390_insn_bfp_triop(UChar size, s390_bfp_triop_t, HReg dst, HReg op2,
HReg op3, s390_round_t);
s390_insn *s390_insn_bfp_binop(UChar size, s390_bfp_binop_t, HReg dst, HReg op2,
@@ -447,8 +509,17 @@
HReg dst, HReg op_hi, HReg op_lo,
s390_round_t);
s390_insn *s390_insn_mfence(void);
-UInt s390_insn_emit(UChar *buf, Int nbuf, const s390_insn *insn,
- void *dispatch);
+s390_insn *s390_insn_gzero(UChar size, UInt offset);
+s390_insn *s390_insn_gadd(UChar size, UInt offset, UChar delta, ULong value);
+
+/* Five for translation chaining */
+s390_insn *s390_insn_xdirect(s390_cc_t cond, Addr64 dst, s390_amode *guest_IA,
+ Bool to_fast_entry);
+s390_insn *s390_insn_xindir(s390_cc_t cond, HReg dst, s390_amode *guest_IA);
+s390_insn *s390_insn_xassisted(s390_cc_t cond, HReg dst, s390_amode *guest_IA,
+ IRJumpKind kind);
+s390_insn *s390_insn_evcheck(s390_amode *counter, s390_amode *fail_addr);
+s390_insn *s390_insn_profinc(void);
const HChar *s390_insn_as_string(const s390_insn *);
@@ -465,28 +536,51 @@
void getRegUsage_S390Instr( HRegUsage *, s390_insn *, Bool );
void mapRegs_S390Instr ( HRegRemap *, s390_insn *, Bool );
Bool isMove_S390Instr ( s390_insn *, HReg *, HReg * );
-Int emit_S390Instr ( UChar *, Int, s390_insn *, Bool,
- void *, void * );
+Int emit_S390Instr ( Bool *, UChar *, Int, s390_insn *, Bool,
+ void *, void *, void *, void *);
void getAllocableRegs_S390( Int *, HReg **, Bool );
void genSpill_S390 ( HInstr **, HInstr **, HReg , Int , Bool );
void genReload_S390 ( HInstr **, HInstr **, HReg , Int , Bool );
s390_insn *directReload_S390 ( s390_insn *, HReg, Short );
-HInstrArray *iselSB_S390 ( IRSB *, VexArch, VexArchInfo *, VexAbiInfo * );
+HInstrArray *iselSB_S390 ( IRSB *, VexArch, VexArchInfo *, VexAbiInfo *,
+ Int, Int, Bool, Bool, Addr64);
+
+/* Return the number of bytes of code needed for an event check */
+Int evCheckSzB_S390(void);
+
+/* Perform a chaining and unchaining of an XDirect jump. */
+VexInvalRange chainXDirect_S390(void *place_to_chain,
+ void *disp_cp_chain_me_EXPECTED,
+ void *place_to_jump_to);
+
+VexInvalRange unchainXDirect_S390(void *place_to_unchain,
+ void *place_to_jump_to_EXPECTED,
+ void *disp_cp_chain_me);
+
+/* Patch the counter location into an existing ProfInc point. */
+VexInvalRange patchProfInc_S390(void *code_to_patch,
+ ULong *location_of_counter);
/* KLUDGE: See detailled comment in host_s390_defs.c. */
-extern const VexArchInfo *s390_archinfo_host;
+extern UInt s390_host_hwcaps;
/* Convenience macros to test installed facilities */
#define s390_host_has_ldisp \
- (s390_archinfo_host->hwcaps & (VEX_HWCAPS_S390X_LDISP))
+ (s390_host_hwcaps & (VEX_HWCAPS_S390X_LDISP))
#define s390_host_has_eimm \
- (s390_archinfo_host->hwcaps & (VEX_HWCAPS_S390X_EIMM))
+ (s390_host_hwcaps & (VEX_HWCAPS_S390X_EIMM))
#define s390_host_has_gie \
- (s390_archinfo_host->hwcaps & (VEX_HWCAPS_S390X_GIE))
+ (s390_host_hwcaps & (VEX_HWCAPS_S390X_GIE))
#define s390_host_has_dfp \
- (s390_archinfo_host->hwcaps & (VEX_HWCAPS_S390X_DFP))
+ (s390_host_hwcaps & (VEX_HWCAPS_S390X_DFP))
#define s390_host_has_fgx \
- (s390_archinfo_host->hwcaps & (VEX_HWCAPS_S390X_FGX))
+ (s390_host_hwcaps & (VEX_HWCAPS_S390X_FGX))
+#define s390_host_has_etf2 \
+ (s390_host_hwcaps & (VEX_HWCAPS_S390X_ETF2))
+#define s390_host_has_stfle \
+ (s390_host_hwcaps & (VEX_HWCAPS_S390X_STFLE))
+#define s390_host_has_etf3 \
+ (s390_host_hwcaps & (VEX_HWCAPS_S390X_ETF3))
#endif /* ndef __VEX_HOST_S390_DEFS_H */
diff --git a/main/VEX/priv/host_s390_disasm.c b/main/VEX/priv/host_s390_disasm.c
index 35f1010..a23009e 100644
--- a/main/VEX/priv/host_s390_disasm.c
+++ b/main/VEX/priv/host_s390_disasm.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/VEX/priv/host_s390_disasm.h b/main/VEX/priv/host_s390_disasm.h
index c01aa34..f053dc8 100644
--- a/main/VEX/priv/host_s390_disasm.h
+++ b/main/VEX/priv/host_s390_disasm.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/VEX/priv/host_s390_isel.c b/main/VEX/priv/host_s390_isel.c
index 4cdf443..292db94 100644
--- a/main/VEX/priv/host_s390_isel.c
+++ b/main/VEX/priv/host_s390_isel.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -35,9 +35,9 @@
#include "libvex.h"
#include "libvex_s390x_common.h"
-#include "ir_match.h"
#include "main_util.h"
#include "main_globals.h"
+#include "guest_s390_defs.h" /* guest_s390x_state_requires_precise_mem_exns */
#include "host_generic_regs.h"
#include "host_s390_defs.h"
@@ -68,21 +68,58 @@
- The host subarchitecture we are selecting insns for.
This is set at the start and does not change.
+
+ - A Bool for indicating whether we may generate chain-me
+ instructions for control flow transfers, or whether we must use
+ XAssisted.
+
+ - The maximum guest address of any guest insn in this block.
+ Actually, the address of the highest-addressed byte from any insn
+ in this block. Is set at the start and does not change. This is
+ used for detecting jumps which are definitely forward-edges from
+ this block, and therefore can be made (chained) to the fast entry
+ point of the destination, thereby avoiding the destination's
+ event check.
+
+ - A flag to indicate whether the guest IA has been assigned to.
+
+ - Values of certain guest registers which are often assigned constants.
*/
+/* Symbolic names for guest registers whose value we're tracking */
+enum {
+ GUEST_IA,
+ GUEST_CC_OP,
+ GUEST_CC_DEP1,
+ GUEST_CC_DEP2,
+ GUEST_CC_NDEP,
+ GUEST_SYSNO,
+ GUEST_COUNTER,
+ GUEST_UNKNOWN /* must be the last entry */
+};
+
+/* Number of registers we're tracking. */
+#define NUM_TRACKED_REGS GUEST_UNKNOWN
+
+
typedef struct {
IRTypeEnv *type_env;
+ HInstrArray *code;
HReg *vregmap;
HReg *vregmapHI;
UInt n_vregmap;
-
- HInstrArray *code;
-
UInt vreg_ctr;
-
UInt hwcaps;
+ ULong old_value[NUM_TRACKED_REGS];
+
+ /* The next two are for translation chaining */
+ Addr64 max_ga;
+ Bool chaining_allowed;
+
+ Bool first_IA_assignment;
+ Bool old_value_valid[NUM_TRACKED_REGS];
} ISelEnv;
@@ -96,6 +133,38 @@
static void s390_isel_float128_expr(HReg *, HReg *, ISelEnv *, IRExpr *);
+static Int
+get_guest_reg(Int offset)
+{
+ switch (offset) {
+ case S390X_GUEST_OFFSET(guest_IA): return GUEST_IA;
+ case S390X_GUEST_OFFSET(guest_CC_OP): return GUEST_CC_OP;
+ case S390X_GUEST_OFFSET(guest_CC_DEP1): return GUEST_CC_DEP1;
+ case S390X_GUEST_OFFSET(guest_CC_DEP2): return GUEST_CC_DEP2;
+ case S390X_GUEST_OFFSET(guest_CC_NDEP): return GUEST_CC_NDEP;
+ case S390X_GUEST_OFFSET(guest_SYSNO): return GUEST_SYSNO;
+ case S390X_GUEST_OFFSET(guest_counter): return GUEST_COUNTER;
+
+ /* Also make sure there is never a partial write to one of
+ these registers. That would complicate matters. */
+ case S390X_GUEST_OFFSET(guest_IA)+1 ... S390X_GUEST_OFFSET(guest_IA)+7:
+ case S390X_GUEST_OFFSET(guest_CC_OP)+1 ... S390X_GUEST_OFFSET(guest_CC_OP)+7:
+ case S390X_GUEST_OFFSET(guest_CC_DEP1)+1 ... S390X_GUEST_OFFSET(guest_CC_DEP1)+7:
+ case S390X_GUEST_OFFSET(guest_CC_DEP2)+1 ... S390X_GUEST_OFFSET(guest_CC_DEP2)+7:
+ case S390X_GUEST_OFFSET(guest_CC_NDEP)+1 ... S390X_GUEST_OFFSET(guest_CC_NDEP)+7:
+ case S390X_GUEST_OFFSET(guest_SYSNO)+1 ... S390X_GUEST_OFFSET(guest_SYSNO)+7:
+ /* counter is used both as 4-byte and as 8-byte entity */
+ case S390X_GUEST_OFFSET(guest_counter)+1 ... S390X_GUEST_OFFSET(guest_counter)+3:
+ case S390X_GUEST_OFFSET(guest_counter)+5 ... S390X_GUEST_OFFSET(guest_counter)+7:
+ vpanic("partial update of this guest state register is not allowed");
+ break;
+
+ default: break;
+ }
+
+ return GUEST_UNKNOWN;
+}
+
/* Add an instruction */
static void
addInstr(ISelEnv *env, s390_insn *insn)
@@ -167,7 +236,7 @@
/* Construct a non-virtual general purpose register */
static __inline__ HReg
-make_gpr(ISelEnv *env, UInt regno)
+make_gpr(UInt regno)
{
return mkHReg(regno, HRcInt64, False /* virtual */ );
}
@@ -203,6 +272,16 @@
}
+static __inline__ Bool
+ulong_fits_signed_8bit(ULong val)
+{
+ Long v = val & 0xFFu;
+
+ v = (v << 56) >> 56; /* sign extend */
+
+ return val == (ULong)v;
+}
+
/* EXPR is an expression that is used as an address. Return an s390_amode
for it. */
static s390_amode *
@@ -346,14 +425,32 @@
/* Call a helper (clean or dirty)
Arguments must satisfy the following conditions:
+
(a) they are expressions yielding an integer result
(b) there can be no more than S390_NUM_GPRPARMS arguments
- guard is a Ity_Bit expression indicating whether or not the
- call happens. If guard==NULL, the call is unconditional.
+
+ guard is a Ity_Bit expression indicating whether or not the
+ call happens. If guard == NULL, the call is unconditional.
+
+ Calling the helper function proceeds as follows:
+
+ (1) The helper arguments are evaluated and their value stored in
+ virtual registers.
+ (2) The condition code is evaluated
+ (3) The argument values are copied from the virtual registers to the
+ registers mandated by the ABI.
+ (4) Call the helper function.
+
+ This is not the most efficient way as step 3 generates register-to-register
+ moves. But it is the least fragile way as the only hidden dependency here
+ is that register-to-register moves (step 3) must not clobber the condition
+ code. Other schemes (e.g. VEX r2326) that attempt to avoid the register-
+ to-register add more such dependencies. Not good. Besides, it's the job
+ of the register allocator to throw out those reg-to-reg moves.
*/
static void
doHelperCall(ISelEnv *env, Bool passBBP, IRExpr *guard,
- IRCallee *callee, IRExpr **args)
+ IRCallee *callee, IRExpr **args, HReg dst)
{
UInt n_args, i, argreg, size;
ULong target;
@@ -368,7 +465,25 @@
vpanic("doHelperCall: too many arguments");
}
- /* This is the "slow scheme". fixs390: implement the fast one */
+ /* All arguments must have Ity_I64. For two reasons:
+ (1) We do not handle floating point arguments.
+ (2) The ABI requires that integer values are sign- or zero-extended
+ to 64 bit.
+ */
+ Int arg_errors = 0;
+ for (i = 0; i < n_args; ++i) {
+ IRType type = typeOfIRExpr(env->type_env, args[i]);
+ if (type != Ity_I64) {
+ ++arg_errors;
+ vex_printf("calling %s: argument #%d has type ", callee->name, i);
+ ppIRType(type);
+ vex_printf("; Ity_I64 is required\n");
+ }
+ }
+
+ if (arg_errors)
+ vpanic("cannot continue due to errors in argument passing");
+
argreg = 0;
/* If we need the guest state pointer put it in a temporary arg reg */
@@ -397,11 +512,12 @@
}
}
- /* Move the args to the final register */
+ /* Move the args to the final register. It is paramount, that the
+ code to move the registers does not clobber the condition code ! */
for (i = 0; i < argreg; i++) {
HReg finalreg;
- finalreg = mkHReg(s390_gprno_from_arg_index(i), HRcInt64, False);
+ finalreg = make_gpr(s390_gprno_from_arg_index(i));
size = sizeofIRType(Ity_I64);
addInstr(env, s390_insn_move(size, finalreg, tmpregs[i]));
}
@@ -410,7 +526,7 @@
/* Finally, the call itself. */
addInstr(env, s390_insn_helper_call(cc, (Addr64)target, n_args,
- callee->name));
+ callee->name, dst));
}
@@ -541,8 +657,8 @@
op2 = s390_isel_int_expr_RMI(env, arg2); /* Process 2nd operand */
/* We use non-virtual registers r10 and r11 as pair */
- r10 = make_gpr(env, 10);
- r11 = make_gpr(env, 11);
+ r10 = make_gpr(10);
+ r11 = make_gpr(11);
/* Move 1st operand into r11 and */
addInstr(env, s390_insn_move(8, r11, h1));
@@ -574,8 +690,8 @@
op2 = s390_isel_int_expr_RMI(env, arg2); /* Process 2nd operand */
/* We use non-virtual registers r10 and r11 as pair */
- r10 = make_gpr(env, 10);
- r11 = make_gpr(env, 11);
+ r10 = make_gpr(10);
+ r11 = make_gpr(11);
/* Move the first operand to r11 */
addInstr(env, s390_insn_move(8, r11, h1));
@@ -600,8 +716,8 @@
op2 = s390_isel_int_expr_RMI(env, arg2); /* Process 2nd operand */
/* We use non-virtual registers r10 and r11 as pair */
- r10 = make_gpr(env, 10);
- r11 = make_gpr(env, 11);
+ r10 = make_gpr(10);
+ r11 = make_gpr(11);
/* Move high 64 bits of the 1st operand into r10 and
the low 64 bits into r11. */
@@ -730,8 +846,8 @@
op2 = s390_isel_int_expr_RMI(env, arg2); /* Process 2nd operand */
/* We use non-virtual registers r10 and r11 as pair */
- r10 = make_gpr(env, 10);
- r11 = make_gpr(env, 11);
+ r10 = make_gpr(10);
+ r11 = make_gpr(11);
/* Move the first operand to r11 */
addInstr(env, s390_insn_move(arg_size, r11, h1));
@@ -767,8 +883,8 @@
op2 = s390_isel_int_expr_RMI(env, arg2); /* Process 2nd operand */
/* We use non-virtual registers r10 and r11 as pair */
- r10 = make_gpr(env, 10);
- r11 = make_gpr(env, 11);
+ r10 = make_gpr(10);
+ r11 = make_gpr(11);
/* Split the first operand and put the high 32 bits into r10 and
the low 32 bits into r11. */
@@ -1030,7 +1146,7 @@
return dst;
}
- if (unop == Iop_ReinterpF64asI64) {
+ if (unop == Iop_ReinterpF64asI64 || unop == Iop_ReinterpF32asI32) {
dst = newVRegI(env);
h1 = s390_isel_float_expr(env, arg); /* Process the operand */
addInstr(env, s390_insn_move(size, dst, h1));
@@ -1047,8 +1163,15 @@
switch (unop) {
case Iop_1Uto8:
case Iop_1Uto32:
+ /* Zero extend */
+ mask.variant.imm = 1;
+ addInstr(env, s390_insn_alu(4, S390_ALU_AND, dst, mask));
+ break;
+
case Iop_1Uto64:
- /* Nothing to do */
+ /* Zero extend */
+ mask.variant.imm = 1;
+ addInstr(env, s390_insn_alu(8, S390_ALU_AND, dst, mask));
break;
case Iop_1Sto8:
@@ -1188,8 +1311,8 @@
set aside a pair of non-virtual registers. The result (number of
left-most zero bits) will be in r10. The value in r11 is unspecified
and must not be used. */
- r10 = make_gpr(env, 10);
- r11 = make_gpr(env, 11);
+ r10 = make_gpr(10);
+ r11 = make_gpr(11);
addInstr(env, s390_insn_clz(8, r10, r11, opnd));
addInstr(env, s390_insn_move(8, dst, r10));
@@ -1228,12 +1351,7 @@
HReg dst = newVRegI(env);
doHelperCall(env, False, NULL, expr->Iex.CCall.cee,
- expr->Iex.CCall.args);
-
- /* Move the returned value into the return register */
- addInstr(env, s390_insn_move(sizeofIRType(expr->Iex.CCall.retty), dst,
- mkHReg(S390_REGNO_RETURN_VALUE,
- HRcInt64, False)));
+ expr->Iex.CCall.args, dst);
return dst;
}
@@ -1425,9 +1543,10 @@
/* --------- TERNARY OP --------- */
case Iex_Triop: {
- IROp op = expr->Iex.Triop.op;
- IRExpr *left = expr->Iex.Triop.arg2;
- IRExpr *right = expr->Iex.Triop.arg3;
+ IRTriop *triop = expr->Iex.Triop.details;
+ IROp op = triop->op;
+ IRExpr *left = triop->arg2;
+ IRExpr *right = triop->arg3;
s390_bfp_binop_t bfpop;
s390_round_t rounding_mode;
HReg op1_hi, op1_lo, op2_hi, op2_lo, f12, f13, f14, f15;
@@ -1458,7 +1577,7 @@
goto irreducible;
}
- rounding_mode = decode_rounding_mode(expr->Iex.Triop.arg1);
+ rounding_mode = decode_rounding_mode(triop->arg1);
addInstr(env, s390_insn_bfp128_binop(16, bfpop, f12, f14, f13,
f15, rounding_mode));
@@ -1516,7 +1635,7 @@
/* --------- UNARY OP --------- */
case Iex_Unop: {
- IRExpr *left = expr->Iex.Binop.arg1;
+ IRExpr *left = expr->Iex.Unop.arg;
s390_bfp_unop_t bfpop;
s390_round_t rounding_mode;
HReg op_hi, op_lo, op, f12, f13, f14, f15;
@@ -1527,7 +1646,7 @@
f14 = make_fpr(14);
f15 = make_fpr(15);
- switch (expr->Iex.Binop.op) {
+ switch (expr->Iex.Unop.op) {
case Iop_NegF128: bfpop = S390_BFP_NEG; goto float128_opnd;
case Iop_AbsF128: bfpop = S390_BFP_ABS; goto float128_opnd;
case Iop_I32StoF128: bfpop = S390_BFP_I32_TO_F128; goto convert_int;
@@ -1668,13 +1787,13 @@
s390_bfp_triop_t bfpop;
s390_round_t rounding_mode;
- op1 = s390_isel_float_expr(env, expr->Iex.Qop.arg2);
- op2 = s390_isel_float_expr(env, expr->Iex.Qop.arg3);
- op3 = s390_isel_float_expr(env, expr->Iex.Qop.arg4);
+ op1 = s390_isel_float_expr(env, expr->Iex.Qop.details->arg2);
+ op2 = s390_isel_float_expr(env, expr->Iex.Qop.details->arg3);
+ op3 = s390_isel_float_expr(env, expr->Iex.Qop.details->arg4);
dst = newVRegF(env);
addInstr(env, s390_insn_move(size, dst, op1));
- switch (expr->Iex.Qop.op) {
+ switch (expr->Iex.Qop.details->op) {
case Iop_MAddF32:
case Iop_MAddF64: bfpop = S390_BFP_MADD; break;
case Iop_MSubF32:
@@ -1684,7 +1803,7 @@
goto irreducible;
}
- rounding_mode = decode_rounding_mode(expr->Iex.Qop.arg1);
+ rounding_mode = decode_rounding_mode(expr->Iex.Qop.details->arg1);
addInstr(env, s390_insn_bfp_triop(size, bfpop, dst, op2, op3,
rounding_mode));
return dst;
@@ -1692,9 +1811,10 @@
/* --------- TERNARY OP --------- */
case Iex_Triop: {
- IROp op = expr->Iex.Triop.op;
- IRExpr *left = expr->Iex.Triop.arg2;
- IRExpr *right = expr->Iex.Triop.arg3;
+ IRTriop *triop = expr->Iex.Triop.details;
+ IROp op = triop->op;
+ IRExpr *left = triop->arg2;
+ IRExpr *right = triop->arg3;
s390_bfp_binop_t bfpop;
s390_round_t rounding_mode;
HReg h1, op2, dst;
@@ -1717,7 +1837,7 @@
goto irreducible;
}
- rounding_mode = decode_rounding_mode(expr->Iex.Triop.arg1);
+ rounding_mode = decode_rounding_mode(triop->arg1);
addInstr(env, s390_insn_bfp_binop(size, bfpop, dst, op2, rounding_mode));
return dst;
}
@@ -1810,7 +1930,7 @@
return op == Iop_F128LOtoF64 ? dst_lo : dst_hi;
}
- if (op == Iop_ReinterpI64asF64) {
+ if (op == Iop_ReinterpI64asF64 || op == Iop_ReinterpI32asF32) {
dst = newVRegF(env);
h1 = s390_isel_int_expr(env, left); /* Process the operand */
addInstr(env, s390_insn_move(size, dst, h1));
@@ -1921,10 +2041,12 @@
/* Iop_32/64to1 select the LSB from their operand */
case Iop_32to1:
case Iop_64to1: {
- HReg dst = s390_isel_int_expr(env, arg);
+ HReg dst = newVRegI(env);
+ HReg h1 = s390_isel_int_expr(env, arg);
size = sizeofIRType(typeOfIRExpr(env->type_env, arg));
+ addInstr(env, s390_insn_move(size, dst, h1));
addInstr(env, s390_insn_alu(size, S390_ALU_AND, dst, s390_opnd_imm(1)));
addInstr(env, s390_insn_test(size, s390_opnd_reg(dst)));
return S390_CC_NE;
@@ -2139,7 +2261,99 @@
IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
HReg src;
s390_amode *am;
+ ULong new_value, old_value, difference;
+ /* Detect updates to certain guest registers. We track the contents
+ of those registers as long as they contain constants. If the new
+ constant is either zero or in the 8-bit neighbourhood of the
+ current value we can use a memory-to-memory insn to do the update. */
+
+ Int offset = stmt->Ist.Put.offset;
+
+ /* Check necessary conditions:
+ (1) must be one of the registers we care about
+ (2) assigned value must be a constant */
+ Int guest_reg = get_guest_reg(offset);
+
+ if (guest_reg == GUEST_UNKNOWN) goto not_special;
+
+ if (guest_reg == GUEST_IA) {
+ /* If this is the first assignment to the IA reg, don't special case
+ it. We need to do a full 8-byte assignment here. The reason is
+ that in case of a redirected translation the guest IA does not
+ contain the redirected-to address. Instead it contains the
+ redirected-from address and those can be far apart. So in order to
+ do incremnetal updates if the IA in the future we need to get the
+ initial address of the super block correct. */
+ if (env->first_IA_assignment) {
+ env->first_IA_assignment = False;
+ goto not_special;
+ }
+ }
+
+ if (stmt->Ist.Put.data->tag != Iex_Const) {
+ /* Invalidate guest register contents */
+ env->old_value_valid[guest_reg] = False;
+ goto not_special;
+ }
+
+ /* We can only handle Ity_I64, but the CC_DEPS field can have floats */
+ if (tyd != Ity_I64)
+ goto not_special;
+
+ /* OK. Necessary conditions are satisfied. */
+
+ old_value = env->old_value[guest_reg];
+ new_value = stmt->Ist.Put.data->Iex.Const.con->Ico.U64;
+ env->old_value[guest_reg] = new_value;
+
+ Bool old_value_is_valid = env->old_value_valid[guest_reg];
+ env->old_value_valid[guest_reg] = True;
+
+ /* If the register already contains the new value, there is nothing
+ to do here. Unless the guest register requires precise memory
+ exceptions. */
+ if (old_value_is_valid && new_value == old_value) {
+ if (! guest_s390x_state_requires_precise_mem_exns(offset, offset + 8)) {
+ return;
+ }
+ }
+
+ /* guest register = 0 */
+ if (new_value == 0) {
+ addInstr(env, s390_insn_gzero(sizeofIRType(tyd), offset));
+ return;
+ }
+
+ if (old_value_is_valid == False) goto not_special;
+
+ /* If the new value is in the neighbourhood of the old value
+ we can use a memory-to-memory insn */
+ difference = new_value - old_value;
+
+ if (s390_host_has_gie && ulong_fits_signed_8bit(difference)) {
+ addInstr(env, s390_insn_gadd(sizeofIRType(tyd), offset,
+ (difference & 0xFF), new_value));
+ return;
+ }
+
+ /* If the high word is the same it is sufficient to load the low word.
+ Use R0 as a scratch reg. */
+ if ((old_value >> 32) == (new_value >> 32)) {
+ HReg r0 = make_gpr(0);
+ HReg gsp = make_gpr(S390_REGNO_GUEST_STATE_POINTER);
+ s390_amode *gam;
+
+ gam = s390_amode_b12(offset + 4, gsp);
+ addInstr(env, s390_insn_load_immediate(4, r0,
+ new_value & 0xFFFFFFFF));
+ addInstr(env, s390_insn_store(4, gam, r0));
+ return;
+ }
+
+ /* No special case applies... fall through */
+
+ not_special:
am = s390_amode_for_guest_state(stmt->Ist.Put.offset);
switch (tyd) {
@@ -2230,27 +2444,40 @@
IRType retty;
IRDirty* d = stmt->Ist.Dirty.details;
Bool passBBP;
+ HReg dst;
+ Int i;
+
+ /* Invalidate tracked values of those guest state registers that are
+ modified by this helper. */
+ for (i = 0; i < d->nFxState; ++i) {
+ /* JRS 1 June 2012: AFAICS, s390 guest doesn't use 'repeat'
+ descriptors in guest state effect descriptions. Hence: */
+ vassert(d->fxState[i].nRepeats == 0 && d->fxState[i].repeatLen == 0);
+ if ((d->fxState[i].fx == Ifx_Write || d->fxState[i].fx == Ifx_Modify)) {
+ Int guest_reg = get_guest_reg(d->fxState[i].offset);
+ if (guest_reg != GUEST_UNKNOWN)
+ env->old_value_valid[guest_reg] = False;
+ }
+ }
if (d->nFxState == 0)
vassert(!d->needsBBP);
passBBP = toBool(d->nFxState > 0 && d->needsBBP);
- doHelperCall(env, passBBP, d->guard, d->cee, d->args);
-
- /* Now figure out what to do with the returned value, if any. */
- if (d->tmp == IRTemp_INVALID)
- /* No return value. Nothing to do. */
+ if (d->tmp == IRTemp_INVALID) {
+ /* No return value. */
+ dst = INVALID_HREG;
+ doHelperCall(env, passBBP, d->guard, d->cee, d->args, dst);
return;
+ }
retty = typeOfIRTemp(env->type_env, d->tmp);
if (retty == Ity_I64 || retty == Ity_I32
|| retty == Ity_I16 || retty == Ity_I8) {
- /* Move the returned value into the return register */
- HReg dst = lookupIRTemp(env, d->tmp);
- addInstr(env, s390_insn_move(sizeofIRType(retty), dst,
- mkHReg(S390_REGNO_RETURN_VALUE,
- HRcInt64, False)));
+ /* Move the returned value to the destination register */
+ dst = lookupIRTemp(env, d->tmp);
+ doHelperCall(env, passBBP, d->guard, d->cee, d->args, dst);
return;
}
break;
@@ -2271,23 +2498,101 @@
}
return;
} else {
- vpanic("compare double and swap not implemented\n");
+ IRCAS *cas = stmt->Ist.CAS.details;
+ s390_amode *op2 = s390_isel_amode(env, cas->addr);
+ HReg r8, r9, r10, r11, r1;
+ HReg op3_high = s390_isel_int_expr(env, cas->dataHi); /* new value */
+ HReg op3_low = s390_isel_int_expr(env, cas->dataLo); /* new value */
+ HReg op1_high = s390_isel_int_expr(env, cas->expdHi); /* expected value */
+ HReg op1_low = s390_isel_int_expr(env, cas->expdLo); /* expected value */
+ HReg old_low = lookupIRTemp(env, cas->oldLo);
+ HReg old_high = lookupIRTemp(env, cas->oldHi);
+
+ /* Use non-virtual registers r8 and r9 as pair for op1
+ and move op1 there */
+ r8 = make_gpr(8);
+ r9 = make_gpr(9);
+ addInstr(env, s390_insn_move(8, r8, op1_high));
+ addInstr(env, s390_insn_move(8, r9, op1_low));
+
+ /* Use non-virtual registers r10 and r11 as pair for op3
+ and move op3 there */
+ r10 = make_gpr(10);
+ r11 = make_gpr(11);
+ addInstr(env, s390_insn_move(8, r10, op3_high));
+ addInstr(env, s390_insn_move(8, r11, op3_low));
+
+ /* Register r1 is used as a scratch register */
+ r1 = make_gpr(1);
+
+ if (typeOfIRTemp(env->type_env, cas->oldLo) == Ity_I32) {
+ addInstr(env, s390_insn_cdas(4, r8, r9, op2, r10, r11,
+ old_high, old_low, r1));
+ } else {
+ addInstr(env, s390_insn_cdas(8, r8, r9, op2, r10, r11,
+ old_high, old_low, r1));
+ }
+ addInstr(env, s390_insn_move(8, op1_high, r8));
+ addInstr(env, s390_insn_move(8, op1_low, r9));
+ addInstr(env, s390_insn_move(8, op3_high, r10));
+ addInstr(env, s390_insn_move(8, op3_low, r11));
+ return;
}
break;
/* --------- EXIT --------- */
case Ist_Exit: {
- s390_opnd_RMI dst;
s390_cc_t cond;
IRConstTag tag = stmt->Ist.Exit.dst->tag;
if (tag != Ico_U64)
vpanic("s390_isel_stmt: Ist_Exit: dst is not a 64-bit value");
- dst = s390_isel_int_expr_RMI(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ s390_amode *guest_IA = s390_amode_for_guest_state(stmt->Ist.Exit.offsIP);
cond = s390_isel_cc(env, stmt->Ist.Exit.guard);
- addInstr(env, s390_insn_branch(stmt->Ist.Exit.jk, cond, dst));
- return;
+
+ /* Case: boring transfer to known address */
+ if (stmt->Ist.Exit.jk == Ijk_Boring) {
+ if (env->chaining_allowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool to_fast_entry
+ = ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > env->max_ga;
+ if (0) vex_printf("%s", to_fast_entry ? "Y" : ",");
+ addInstr(env, s390_insn_xdirect(cond, stmt->Ist.Exit.dst->Ico.U64,
+ guest_IA, to_fast_entry));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg dst = s390_isel_int_expr(env,
+ IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, s390_insn_xassisted(cond, dst, guest_IA, Ijk_Boring));
+ }
+ return;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (stmt->Ist.Exit.jk) {
+ case Ijk_NoDecode:
+ case Ijk_TInval:
+ case Ijk_Sys_syscall:
+ case Ijk_ClientReq:
+ case Ijk_NoRedir:
+ case Ijk_Yield:
+ case Ijk_SigTRAP: {
+ HReg dst = s390_isel_int_expr(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, s390_insn_xassisted(cond, dst, guest_IA,
+ stmt->Ist.Exit.jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Do we ever expect to see any other kind? */
+ goto stmt_fail;
}
/* --------- MEM FENCE --------- */
@@ -2324,20 +2629,81 @@
/*---------------------------------------------------------*/
static void
-iselNext(ISelEnv *env, IRExpr *next, IRJumpKind jk)
+iselNext(ISelEnv *env, IRExpr *next, IRJumpKind jk, int offsIP)
{
- s390_opnd_RMI dst;
-
if (vex_traceflags & VEX_TRACE_VCODE) {
- vex_printf("\n-- goto {");
- ppIRJumpKind(jk);
- vex_printf("} ");
+ vex_printf("\n-- PUT(%d) = ", offsIP);
ppIRExpr(next);
+ vex_printf("; exit-");
+ ppIRJumpKind(jk);
vex_printf("\n");
}
- dst = s390_isel_int_expr_RMI(env, next);
- addInstr(env, s390_insn_branch(jk, S390_CC_ALWAYS, dst));
+ s390_amode *guest_IA = s390_amode_for_guest_state(offsIP);
+
+ /* Case: boring transfer to known address */
+ if (next->tag == Iex_Const) {
+ IRConst *cdst = next->Iex.Const.con;
+ vassert(cdst->tag == Ico_U64);
+ if (jk == Ijk_Boring || jk == Ijk_Call) {
+ /* Boring transfer to known address */
+ if (env->chaining_allowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool to_fast_entry
+ = ((Addr64)cdst->Ico.U64) > env->max_ga;
+ if (0) vex_printf("%s", to_fast_entry ? "X" : ".");
+ addInstr(env, s390_insn_xdirect(S390_CC_ALWAYS, cdst->Ico.U64,
+ guest_IA, to_fast_entry));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an indirect transfer,
+ as that's the cheapest alternative that is allowable. */
+ HReg dst = s390_isel_int_expr(env, next);
+ addInstr(env, s390_insn_xassisted(S390_CC_ALWAYS, dst, guest_IA,
+ Ijk_Boring));
+ }
+ return;
+ }
+ }
+
+ /* Case: call/return (==boring) transfer to any address */
+ switch (jk) {
+ case Ijk_Boring:
+ case Ijk_Ret:
+ case Ijk_Call: {
+ HReg dst = s390_isel_int_expr(env, next);
+ if (env->chaining_allowed) {
+ addInstr(env, s390_insn_xindir(S390_CC_ALWAYS, dst, guest_IA));
+ } else {
+ addInstr(env, s390_insn_xassisted(S390_CC_ALWAYS, dst, guest_IA,
+ Ijk_Boring));
+ }
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Case: some other kind of transfer to any address */
+ switch (jk) {
+ case Ijk_NoDecode:
+ case Ijk_TInval:
+ case Ijk_Sys_syscall:
+ case Ijk_ClientReq:
+ case Ijk_NoRedir:
+ case Ijk_Yield:
+ case Ijk_SigTRAP: {
+ HReg dst = s390_isel_int_expr(env, next);
+ addInstr(env, s390_insn_xassisted(S390_CC_ALWAYS, dst, guest_IA, jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ vpanic("iselNext");
}
@@ -2345,19 +2711,23 @@
/*--- Insn selector top-level ---*/
/*---------------------------------------------------------*/
-/* Translate an entire SB to s390 code. */
+/* Translate an entire SB to s390 code.
+ Note: archinfo_host is a pointer to a stack-allocated variable.
+ Do not assign it to a global variable! */
HInstrArray *
iselSB_S390(IRSB *bb, VexArch arch_host, VexArchInfo *archinfo_host,
- VexAbiInfo *vbi)
+ VexAbiInfo *vbi, Int offset_host_evcheck_counter,
+ Int offset_host_evcheck_fail_addr, Bool chaining_allowed,
+ Bool add_profinc, Addr64 max_ga)
{
UInt i, j;
HReg hreg, hregHI;
ISelEnv *env;
UInt hwcaps_host = archinfo_host->hwcaps;
- /* KLUDGE: export archinfo_host. */
- s390_archinfo_host = archinfo_host;
+ /* KLUDGE: export hwcaps. */
+ s390_host_hwcaps = hwcaps_host;
/* Do some sanity checks */
vassert((VEX_HWCAPS_S390X(hwcaps_host) & ~(VEX_HWCAPS_S390X_ALL)) == 0);
@@ -2372,6 +2742,13 @@
/* Copy BB's type env. */
env->type_env = bb->tyenv;
+ /* Set up data structures for tracking guest register values. */
+ env->first_IA_assignment = True;
+ for (i = 0; i < NUM_TRACKED_REGS; ++i) {
+ env->old_value[i] = 0; /* just something to have a defined value */
+ env->old_value_valid[i] = False;
+ }
+
/* Make up an IRTemp -> virtual HReg mapping. This doesn't
change as we go along. For some reason types_used has Int type -- but
it should be unsigned. Internally we use an unsigned type; so we
@@ -2385,6 +2762,9 @@
/* and finally ... */
env->hwcaps = hwcaps_host;
+ env->max_ga = max_ga;
+ env->chaining_allowed = chaining_allowed;
+
/* For each IR temporary, allocate a suitably-kinded virtual
register. */
j = 0;
@@ -2428,12 +2808,26 @@
}
env->vreg_ctr = j;
+ /* The very first instruction must be an event check. */
+ s390_amode *counter, *fail_addr;
+ counter = s390_amode_for_guest_state(offset_host_evcheck_counter);
+ fail_addr = s390_amode_for_guest_state(offset_host_evcheck_fail_addr);
+ addInstr(env, s390_insn_evcheck(counter, fail_addr));
+
+ /* Possibly a block counter increment (for profiling). At this
+ point we don't know the address of the counter, so just pretend
+ it is zero. It will have to be patched later, but before this
+ translation is used, by a call to LibVEX_patchProfInc. */
+ if (add_profinc) {
+ addInstr(env, s390_insn_profinc());
+ }
+
/* Ok, finally we can iterate over the statements. */
for (i = 0; i < bb->stmts_used; i++)
if (bb->stmts[i])
s390_isel_stmt(env, bb->stmts[i]);
- iselNext(env, bb->next, bb->jumpkind);
+ iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
/* Record the number of vregs we used. */
env->code->n_vregs = env->vreg_ctr;
diff --git a/main/VEX/priv/host_x86_defs.c b/main/VEX/priv/host_x86_defs.c
index e26a076..efd511e 100644
--- a/main/VEX/priv/host_x86_defs.c
+++ b/main/VEX/priv/host_x86_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -647,12 +647,33 @@
vassert(regparms >= 0 && regparms <= 3);
return i;
}
-X86Instr* X86Instr_Goto ( IRJumpKind jk, X86CondCode cond, X86RI* dst ) {
- X86Instr* i = LibVEX_Alloc(sizeof(X86Instr));
- i->tag = Xin_Goto;
- i->Xin.Goto.cond = cond;
- i->Xin.Goto.dst = dst;
- i->Xin.Goto.jk = jk;
+X86Instr* X86Instr_XDirect ( Addr32 dstGA, X86AMode* amEIP,
+ X86CondCode cond, Bool toFastEP ) {
+ X86Instr* i = LibVEX_Alloc(sizeof(X86Instr));
+ i->tag = Xin_XDirect;
+ i->Xin.XDirect.dstGA = dstGA;
+ i->Xin.XDirect.amEIP = amEIP;
+ i->Xin.XDirect.cond = cond;
+ i->Xin.XDirect.toFastEP = toFastEP;
+ return i;
+}
+X86Instr* X86Instr_XIndir ( HReg dstGA, X86AMode* amEIP,
+ X86CondCode cond ) {
+ X86Instr* i = LibVEX_Alloc(sizeof(X86Instr));
+ i->tag = Xin_XIndir;
+ i->Xin.XIndir.dstGA = dstGA;
+ i->Xin.XIndir.amEIP = amEIP;
+ i->Xin.XIndir.cond = cond;
+ return i;
+}
+X86Instr* X86Instr_XAssisted ( HReg dstGA, X86AMode* amEIP,
+ X86CondCode cond, IRJumpKind jk ) {
+ X86Instr* i = LibVEX_Alloc(sizeof(X86Instr));
+ i->tag = Xin_XAssisted;
+ i->Xin.XAssisted.dstGA = dstGA;
+ i->Xin.XAssisted.amEIP = amEIP;
+ i->Xin.XAssisted.cond = cond;
+ i->Xin.XAssisted.jk = jk;
return i;
}
X86Instr* X86Instr_CMov32 ( X86CondCode cond, X86RM* src, HReg dst ) {
@@ -797,7 +818,6 @@
i->Xin.FpCmp.dst = dst;
return i;
}
-
X86Instr* X86Instr_SseConst ( UShort con, HReg dst ) {
X86Instr* i = LibVEX_Alloc(sizeof(X86Instr));
i->tag = Xin_SseConst;
@@ -886,6 +906,19 @@
vassert(order >= 0 && order <= 0xFF);
return i;
}
+X86Instr* X86Instr_EvCheck ( X86AMode* amCounter,
+ X86AMode* amFailAddr ) {
+ X86Instr* i = LibVEX_Alloc(sizeof(X86Instr));
+ i->tag = Xin_EvCheck;
+ i->Xin.EvCheck.amCounter = amCounter;
+ i->Xin.EvCheck.amFailAddr = amFailAddr;
+ return i;
+}
+X86Instr* X86Instr_ProfInc ( void ) {
+ X86Instr* i = LibVEX_Alloc(sizeof(X86Instr));
+ i->tag = Xin_ProfInc;
+ return i;
+}
void ppX86Instr ( X86Instr* i, Bool mode64 ) {
vassert(mode64 == False);
@@ -953,24 +986,36 @@
i->Xin.Call.regparms);
vex_printf("0x%x", i->Xin.Call.target);
break;
- case Xin_Goto:
- if (i->Xin.Goto.cond != Xcc_ALWAYS) {
- vex_printf("if (%%eflags.%s) { ",
- showX86CondCode(i->Xin.Goto.cond));
- }
- if (i->Xin.Goto.jk != Ijk_Boring
- && i->Xin.Goto.jk != Ijk_Call
- && i->Xin.Goto.jk != Ijk_Ret) {
- vex_printf("movl $");
- ppIRJumpKind(i->Xin.Goto.jk);
- vex_printf(",%%ebp ; ");
- }
+ case Xin_XDirect:
+ vex_printf("(xDirect) ");
+ vex_printf("if (%%eflags.%s) { ",
+ showX86CondCode(i->Xin.XDirect.cond));
+ vex_printf("movl $0x%x,", i->Xin.XDirect.dstGA);
+ ppX86AMode(i->Xin.XDirect.amEIP);
+ vex_printf("; ");
+ vex_printf("movl $disp_cp_chain_me_to_%sEP,%%edx; call *%%edx }",
+ i->Xin.XDirect.toFastEP ? "fast" : "slow");
+ return;
+ case Xin_XIndir:
+ vex_printf("(xIndir) ");
+ vex_printf("if (%%eflags.%s) { movl ",
+ showX86CondCode(i->Xin.XIndir.cond));
+ ppHRegX86(i->Xin.XIndir.dstGA);
+ vex_printf(",");
+ ppX86AMode(i->Xin.XIndir.amEIP);
+ vex_printf("; movl $disp_indir,%%edx; jmp *%%edx }");
+ return;
+ case Xin_XAssisted:
+ vex_printf("(xAssisted) ");
+ vex_printf("if (%%eflags.%s) { ",
+ showX86CondCode(i->Xin.XAssisted.cond));
vex_printf("movl ");
- ppX86RI(i->Xin.Goto.dst);
- vex_printf(",%%eax ; movl $dispatcher_addr,%%edx ; jmp *%%edx");
- if (i->Xin.Goto.cond != Xcc_ALWAYS) {
- vex_printf(" }");
- }
+ ppHRegX86(i->Xin.XAssisted.dstGA);
+ vex_printf(",");
+ ppX86AMode(i->Xin.XAssisted.amEIP);
+ vex_printf("; movl $IRJumpKind_to_TRCVAL(%d),%%ebp",
+ (Int)i->Xin.XAssisted.jk);
+ vex_printf("; movl $disp_assisted,%%edx; jmp *%%edx }");
return;
case Xin_CMov32:
vex_printf("cmov%s ", showX86CondCode(i->Xin.CMov32.cond));
@@ -1152,7 +1197,17 @@
vex_printf(",");
ppHRegX86(i->Xin.SseShuf.dst);
return;
-
+ case Xin_EvCheck:
+ vex_printf("(evCheck) decl ");
+ ppX86AMode(i->Xin.EvCheck.amCounter);
+ vex_printf("; jns nofail; jmp *");
+ ppX86AMode(i->Xin.EvCheck.amFailAddr);
+ vex_printf("; nofail:");
+ return;
+ case Xin_ProfInc:
+ vex_printf("(profInc) addl $1,NotKnownYet; "
+ "adcl $0,NotKnownYet+4");
+ return;
default:
vpanic("ppX86Instr");
}
@@ -1258,16 +1313,21 @@
address temporary, depending on the regparmness: 0==EAX,
1==EDX, 2==ECX, 3==EDI. */
return;
- case Xin_Goto:
- addRegUsage_X86RI(u, i->Xin.Goto.dst);
- addHRegUse(u, HRmWrite, hregX86_EAX()); /* used for next guest addr */
- addHRegUse(u, HRmWrite, hregX86_EDX()); /* used for dispatcher addr */
- if (i->Xin.Goto.jk != Ijk_Boring
- && i->Xin.Goto.jk != Ijk_Call
- && i->Xin.Goto.jk != Ijk_Ret)
- /* note, this is irrelevant since ebp is not actually
- available to the allocator. But still .. */
- addHRegUse(u, HRmWrite, hregX86_EBP());
+ /* XDirect/XIndir/XAssisted are also a bit subtle. They
+ conditionally exit the block. Hence we only need to list (1)
+ the registers that they read, and (2) the registers that they
+ write in the case where the block is not exited. (2) is
+ empty, hence only (1) is relevant here. */
+ case Xin_XDirect:
+ addRegUsage_X86AMode(u, i->Xin.XDirect.amEIP);
+ return;
+ case Xin_XIndir:
+ addHRegUse(u, HRmRead, i->Xin.XIndir.dstGA);
+ addRegUsage_X86AMode(u, i->Xin.XIndir.amEIP);
+ return;
+ case Xin_XAssisted:
+ addHRegUse(u, HRmRead, i->Xin.XAssisted.dstGA);
+ addRegUsage_X86AMode(u, i->Xin.XAssisted.amEIP);
return;
case Xin_CMov32:
addRegUsage_X86RM(u, i->Xin.CMov32.src, HRmRead);
@@ -1410,6 +1470,15 @@
addHRegUse(u, HRmRead, i->Xin.SseShuf.src);
addHRegUse(u, HRmWrite, i->Xin.SseShuf.dst);
return;
+ case Xin_EvCheck:
+ /* We expect both amodes only to mention %ebp, so this is in
+ fact pointless, since %ebp isn't allocatable, but anyway.. */
+ addRegUsage_X86AMode(u, i->Xin.EvCheck.amCounter);
+ addRegUsage_X86AMode(u, i->Xin.EvCheck.amFailAddr);
+ return;
+ case Xin_ProfInc:
+ /* does not use any registers. */
+ return;
default:
ppX86Instr(i, False);
vpanic("getRegUsage_X86Instr");
@@ -1462,8 +1531,16 @@
return;
case Xin_Call:
return;
- case Xin_Goto:
- mapRegs_X86RI(m, i->Xin.Goto.dst);
+ case Xin_XDirect:
+ mapRegs_X86AMode(m, i->Xin.XDirect.amEIP);
+ return;
+ case Xin_XIndir:
+ mapReg(m, &i->Xin.XIndir.dstGA);
+ mapRegs_X86AMode(m, i->Xin.XIndir.amEIP);
+ return;
+ case Xin_XAssisted:
+ mapReg(m, &i->Xin.XAssisted.dstGA);
+ mapRegs_X86AMode(m, i->Xin.XAssisted.amEIP);
return;
case Xin_CMov32:
mapRegs_X86RM(m, i->Xin.CMov32.src);
@@ -1566,6 +1643,16 @@
mapReg(m, &i->Xin.SseShuf.src);
mapReg(m, &i->Xin.SseShuf.dst);
return;
+ case Xin_EvCheck:
+ /* We expect both amodes only to mention %ebp, so this is in
+ fact pointless, since %ebp isn't allocatable, but anyway.. */
+ mapRegs_X86AMode(m, i->Xin.EvCheck.amCounter);
+ mapRegs_X86AMode(m, i->Xin.EvCheck.amFailAddr);
+ return;
+ case Xin_ProfInc:
+ /* does not use any registers. */
+ return;
+
default:
ppX86Instr(i, mode64);
vpanic("mapRegs_X86Instr");
@@ -1986,12 +2073,17 @@
/* Emit an instruction into buf and return the number of bytes used.
Note that buf is not the insn's final place, and therefore it is
- imperative to emit position-independent code. */
+ imperative to emit position-independent code. If the emitted
+ instruction was a profiler inc, set *is_profInc to True, else
+ leave it unchanged. */
-Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i,
+Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, X86Instr* i,
Bool mode64,
- void* dispatch_unassisted,
- void* dispatch_assisted )
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted )
{
UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc;
@@ -2306,113 +2398,156 @@
*p++ = toUChar(0xD0 + irno);
goto done;
- case Xin_Goto: {
- void* dispatch_to_use = NULL;
- vassert(dispatch_unassisted != NULL);
- vassert(dispatch_assisted != NULL);
+ case Xin_XDirect: {
+ /* NB: what goes on here has to be very closely coordinated with the
+ chainXDirect_X86 and unchainXDirect_X86 below. */
+ /* We're generating chain-me requests here, so we need to be
+ sure this is actually allowed -- no-redir translations can't
+ use chain-me's. Hence: */
+ vassert(disp_cp_chain_me_to_slowEP != NULL);
+ vassert(disp_cp_chain_me_to_fastEP != NULL);
/* Use ptmp for backpatching conditional jumps. */
ptmp = NULL;
/* First off, if this is conditional, create a conditional
- jump over the rest of it. */
- if (i->Xin.Goto.cond != Xcc_ALWAYS) {
+ jump over the rest of it. */
+ if (i->Xin.XDirect.cond != Xcc_ALWAYS) {
/* jmp fwds if !condition */
- *p++ = toUChar(0x70 + (0xF & (i->Xin.Goto.cond ^ 1)));
+ *p++ = toUChar(0x70 + (0xF & (i->Xin.XDirect.cond ^ 1)));
ptmp = p; /* fill in this bit later */
*p++ = 0; /* # of bytes to jump over; don't know how many yet. */
}
- /* If a non-boring, set %ebp (the guest state pointer)
- appropriately. Also, decide which dispatcher we need to
- use. */
- dispatch_to_use = dispatch_assisted;
+ /* Update the guest EIP. */
+ /* movl $dstGA, amEIP */
+ *p++ = 0xC7;
+ p = doAMode_M(p, fake(0), i->Xin.XDirect.amEIP);
+ p = emit32(p, i->Xin.XDirect.dstGA);
- /* movl $magic_number, %ebp */
- switch (i->Xin.Goto.jk) {
- case Ijk_ClientReq:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_CLIENTREQ); break;
- case Ijk_Sys_int128:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SYS_INT128); break;
- case Ijk_Sys_int129:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SYS_INT129); break;
- case Ijk_Sys_int130:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SYS_INT130); break;
- case Ijk_Yield:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_YIELD); break;
- case Ijk_YieldNoRedir:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_YIELD_NOREDIR); break;
- case Ijk_EmWarn:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_EMWARN); break;
- case Ijk_MapFail:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_MAPFAIL); break;
- case Ijk_NoDecode:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_NODECODE); break;
- case Ijk_TInval:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_TINVAL); break;
- case Ijk_NoRedir:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_NOREDIR); break;
- case Ijk_Sys_sysenter:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SYS_SYSENTER); break;
- case Ijk_SigTRAP:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SIGTRAP); break;
- case Ijk_SigSEGV:
- *p++ = 0xBD;
- p = emit32(p, VEX_TRC_JMP_SIGSEGV); break;
- case Ijk_Ret:
- case Ijk_Call:
- case Ijk_Boring:
- dispatch_to_use = dispatch_unassisted;
- break;
- default:
- ppIRJumpKind(i->Xin.Goto.jk);
- vpanic("emit_X86Instr.Xin_Goto: unknown jump kind");
- }
-
- /* Get the destination address into %eax */
- if (i->Xin.Goto.dst->tag == Xri_Imm) {
- /* movl $immediate, %eax */
- *p++ = 0xB8;
- p = emit32(p, i->Xin.Goto.dst->Xri.Imm.imm32);
- } else {
- vassert(i->Xin.Goto.dst->tag == Xri_Reg);
- /* movl %reg, %eax */
- if (i->Xin.Goto.dst->Xri.Reg.reg != hregX86_EAX()) {
- *p++ = 0x89;
- p = doAMode_R(p, i->Xin.Goto.dst->Xri.Reg.reg, hregX86_EAX());
- }
- }
-
- /* Get the dispatcher address into %edx. This has to happen
- after the load of %eax since %edx might be carrying the value
- destined for %eax immediately prior to this Xin_Goto. */
- vassert(sizeof(UInt) == sizeof(void*));
- vassert(dispatch_to_use != NULL);
- /* movl $imm32, %edx */
+ /* --- FIRST PATCHABLE BYTE follows --- */
+ /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're calling
+ to) backs up the return address, so as to find the address of
+ the first patchable byte. So: don't change the length of the
+ two instructions below. */
+ /* movl $disp_cp_chain_me_to_{slow,fast}EP,%edx; */
*p++ = 0xBA;
- p = emit32(p, (UInt)Ptr_to_ULong(dispatch_to_use));
+ void* disp_cp_chain_me
+ = i->Xin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
+ : disp_cp_chain_me_to_slowEP;
+ p = emit32(p, (UInt)Ptr_to_ULong(disp_cp_chain_me));
+ /* call *%edx */
+ *p++ = 0xFF;
+ *p++ = 0xD2;
+ /* --- END of PATCHABLE BYTES --- */
+ /* Fix up the conditional jump, if there was one. */
+ if (i->Xin.XDirect.cond != Xcc_ALWAYS) {
+ Int delta = p - ptmp;
+ vassert(delta > 0 && delta < 40);
+ *ptmp = toUChar(delta-1);
+ }
+ goto done;
+ }
+
+ case Xin_XIndir: {
+ /* We're generating transfers that could lead indirectly to a
+ chain-me, so we need to be sure this is actually allowed --
+ no-redir translations are not allowed to reach normal
+ translations without going through the scheduler. That means
+ no XDirects or XIndirs out from no-redir translations.
+ Hence: */
+ vassert(disp_cp_xindir != NULL);
+
+ /* Use ptmp for backpatching conditional jumps. */
+ ptmp = NULL;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. */
+ if (i->Xin.XIndir.cond != Xcc_ALWAYS) {
+ /* jmp fwds if !condition */
+ *p++ = toUChar(0x70 + (0xF & (i->Xin.XIndir.cond ^ 1)));
+ ptmp = p; /* fill in this bit later */
+ *p++ = 0; /* # of bytes to jump over; don't know how many yet. */
+ }
+
+ /* movl dstGA(a reg), amEIP -- copied from Alu32M MOV case */
+ *p++ = 0x89;
+ p = doAMode_M(p, i->Xin.XIndir.dstGA, i->Xin.XIndir.amEIP);
+
+ /* movl $disp_indir, %edx */
+ *p++ = 0xBA;
+ p = emit32(p, (UInt)Ptr_to_ULong(disp_cp_xindir));
/* jmp *%edx */
*p++ = 0xFF;
*p++ = 0xE2;
/* Fix up the conditional jump, if there was one. */
- if (i->Xin.Goto.cond != Xcc_ALWAYS) {
+ if (i->Xin.XIndir.cond != Xcc_ALWAYS) {
Int delta = p - ptmp;
- vassert(delta > 0 && delta < 20);
+ vassert(delta > 0 && delta < 40);
+ *ptmp = toUChar(delta-1);
+ }
+ goto done;
+ }
+
+ case Xin_XAssisted: {
+ /* Use ptmp for backpatching conditional jumps. */
+ ptmp = NULL;
+
+ /* First off, if this is conditional, create a conditional
+ jump over the rest of it. */
+ if (i->Xin.XAssisted.cond != Xcc_ALWAYS) {
+ /* jmp fwds if !condition */
+ *p++ = toUChar(0x70 + (0xF & (i->Xin.XAssisted.cond ^ 1)));
+ ptmp = p; /* fill in this bit later */
+ *p++ = 0; /* # of bytes to jump over; don't know how many yet. */
+ }
+
+ /* movl dstGA(a reg), amEIP -- copied from Alu32M MOV case */
+ *p++ = 0x89;
+ p = doAMode_M(p, i->Xin.XIndir.dstGA, i->Xin.XIndir.amEIP);
+ /* movl $magic_number, %ebp. */
+ UInt trcval = 0;
+ switch (i->Xin.XAssisted.jk) {
+ case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break;
+ case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break;
+ case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break;
+ case Ijk_Sys_int129: trcval = VEX_TRC_JMP_SYS_INT129; break;
+ case Ijk_Sys_int130: trcval = VEX_TRC_JMP_SYS_INT130; break;
+ case Ijk_Sys_sysenter: trcval = VEX_TRC_JMP_SYS_SYSENTER; break;
+ case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break;
+ case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break;
+ case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break;
+ case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break;
+ case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break;
+ case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
+ case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
+ case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
+ case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break;
+ /* We don't expect to see the following being assisted. */
+ case Ijk_Ret:
+ case Ijk_Call:
+ /* fallthrough */
+ default:
+ ppIRJumpKind(i->Xin.XAssisted.jk);
+ vpanic("emit_X86Instr.Xin_XAssisted: unexpected jump kind");
+ }
+ vassert(trcval != 0);
+ *p++ = 0xBD;
+ p = emit32(p, trcval);
+
+ /* movl $disp_indir, %edx */
+ *p++ = 0xBA;
+ p = emit32(p, (UInt)Ptr_to_ULong(disp_cp_xassisted));
+ /* jmp *%edx */
+ *p++ = 0xFF;
+ *p++ = 0xE2;
+
+ /* Fix up the conditional jump, if there was one. */
+ if (i->Xin.XAssisted.cond != Xcc_ALWAYS) {
+ Int delta = p - ptmp;
+ vassert(delta > 0 && delta < 40);
*ptmp = toUChar(delta-1);
}
goto done;
@@ -3091,6 +3226,63 @@
*p++ = (UChar)(i->Xin.SseShuf.order);
goto done;
+ case Xin_EvCheck: {
+ /* We generate:
+ (3 bytes) decl 4(%ebp) 4 == offsetof(host_EvC_COUNTER)
+ (2 bytes) jns nofail expected taken
+ (3 bytes) jmp* 0(%ebp) 0 == offsetof(host_EvC_FAILADDR)
+ nofail:
+ */
+ /* This is heavily asserted re instruction lengths. It needs to
+ be. If we get given unexpected forms of .amCounter or
+ .amFailAddr -- basically, anything that's not of the form
+ uimm7(%ebp) -- they are likely to fail. */
+ /* Note also that after the decl we must be very careful not to
+ read the carry flag, else we get a partial flags stall.
+ js/jns avoids that, though. */
+ UChar* p0 = p;
+ /* --- decl 8(%ebp) --- */
+ /* "fake(1)" because + there's no register in this encoding;
+ instead the register + field is used as a sub opcode. The
+ encoding for "decl r/m32" + is FF /1, hence the fake(1). */
+ *p++ = 0xFF;
+ p = doAMode_M(p, fake(1), i->Xin.EvCheck.amCounter);
+ vassert(p - p0 == 3);
+ /* --- jns nofail --- */
+ *p++ = 0x79;
+ *p++ = 0x03; /* need to check this 0x03 after the next insn */
+ vassert(p - p0 == 5);
+ /* --- jmp* 0(%ebp) --- */
+ /* The encoding is FF /4. */
+ *p++ = 0xFF;
+ p = doAMode_M(p, fake(4), i->Xin.EvCheck.amFailAddr);
+ vassert(p - p0 == 8); /* also ensures that 0x03 offset above is ok */
+ /* And crosscheck .. */
+ vassert(evCheckSzB_X86() == 8);
+ goto done;
+ }
+
+ case Xin_ProfInc: {
+ /* We generate addl $1,NotKnownYet
+ adcl $0,NotKnownYet+4
+ in the expectation that a later call to LibVEX_patchProfCtr
+ will be used to fill in the immediate fields once the right
+ value is known.
+ 83 05 00 00 00 00 01
+ 83 15 00 00 00 00 00
+ */
+ *p++ = 0x83; *p++ = 0x05;
+ *p++ = 0x00; *p++ = 0x00; *p++ = 0x00; *p++ = 0x00;
+ *p++ = 0x01;
+ *p++ = 0x83; *p++ = 0x15;
+ *p++ = 0x00; *p++ = 0x00; *p++ = 0x00; *p++ = 0x00;
+ *p++ = 0x00;
+ /* Tell the caller .. */
+ vassert(!(*is_profInc));
+ *is_profInc = True;
+ goto done;
+ }
+
default:
goto bad;
}
@@ -3107,6 +3299,140 @@
# undef fake
}
+
+/* How big is an event check? See case for Xin_EvCheck in
+ emit_X86Instr just above. That crosschecks what this returns, so
+ we can tell if we're inconsistent. */
+Int evCheckSzB_X86 ( void )
+{
+ return 8;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange chainXDirect_X86 ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to )
+{
+ /* What we're expecting to see is:
+ movl $disp_cp_chain_me_EXPECTED, %edx
+ call *%edx
+ viz
+ BA <4 bytes value == disp_cp_chain_me_EXPECTED>
+ FF D2
+ */
+ UChar* p = (UChar*)place_to_chain;
+ vassert(p[0] == 0xBA);
+ vassert(*(UInt*)(&p[1]) == (UInt)Ptr_to_ULong(disp_cp_chain_me_EXPECTED));
+ vassert(p[5] == 0xFF);
+ vassert(p[6] == 0xD2);
+ /* And what we want to change it to is:
+ jmp disp32 where disp32 is relative to the next insn
+ ud2;
+ viz
+ E9 <4 bytes == disp32>
+ 0F 0B
+ The replacement has the same length as the original.
+ */
+ /* This is the delta we need to put into a JMP d32 insn. It's
+ relative to the start of the next insn, hence the -5. */
+ Long delta = (Long)((UChar*)place_to_jump_to - (UChar*)p) - (Long)5;
+
+ /* And make the modifications. */
+ p[0] = 0xE9;
+ p[1] = (delta >> 0) & 0xFF;
+ p[2] = (delta >> 8) & 0xFF;
+ p[3] = (delta >> 16) & 0xFF;
+ p[4] = (delta >> 24) & 0xFF;
+ p[5] = 0x0F; p[6] = 0x0B;
+ /* sanity check on the delta -- top 32 are all 0 or all 1 */
+ delta >>= 32;
+ vassert(delta == 0LL || delta == -1LL);
+ VexInvalRange vir = {0, 0};
+ return vir;
+}
+
+
+/* NB: what goes on here has to be very closely coordinated with the
+ emitInstr case for XDirect, above. */
+VexInvalRange unchainXDirect_X86 ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me )
+{
+ /* What we're expecting to see is:
+ jmp d32
+ ud2;
+ viz
+ E9 <4 bytes == disp32>
+ 0F 0B
+ */
+ UChar* p = (UChar*)place_to_unchain;
+ Bool valid = False;
+ if (p[0] == 0xE9
+ && p[5] == 0x0F && p[6] == 0x0B) {
+ /* Check the offset is right. */
+ Int s32 = *(Int*)(&p[1]);
+ if ((UChar*)p + 5 + s32 == (UChar*)place_to_jump_to_EXPECTED) {
+ valid = True;
+ if (0)
+ vex_printf("QQQ unchainXDirect_X86: found valid\n");
+ }
+ }
+ vassert(valid);
+ /* And what we want to change it to is:
+ movl $disp_cp_chain_me, %edx
+ call *%edx
+ viz
+ BA <4 bytes value == disp_cp_chain_me_EXPECTED>
+ FF D2
+ So it's the same length (convenient, huh).
+ */
+ p[0] = 0xBA;
+ *(UInt*)(&p[1]) = (UInt)Ptr_to_ULong(disp_cp_chain_me);
+ p[5] = 0xFF;
+ p[6] = 0xD2;
+ VexInvalRange vir = {0, 0};
+ return vir;
+}
+
+
+/* Patch the counter address into a profile inc point, as previously
+ created by the Xin_ProfInc case for emit_X86Instr. */
+VexInvalRange patchProfInc_X86 ( void* place_to_patch,
+ ULong* location_of_counter )
+{
+ vassert(sizeof(ULong*) == 4);
+ UChar* p = (UChar*)place_to_patch;
+ vassert(p[0] == 0x83);
+ vassert(p[1] == 0x05);
+ vassert(p[2] == 0x00);
+ vassert(p[3] == 0x00);
+ vassert(p[4] == 0x00);
+ vassert(p[5] == 0x00);
+ vassert(p[6] == 0x01);
+ vassert(p[7] == 0x83);
+ vassert(p[8] == 0x15);
+ vassert(p[9] == 0x00);
+ vassert(p[10] == 0x00);
+ vassert(p[11] == 0x00);
+ vassert(p[12] == 0x00);
+ vassert(p[13] == 0x00);
+ UInt imm32 = (UInt)Ptr_to_ULong(location_of_counter);
+ p[2] = imm32 & 0xFF; imm32 >>= 8;
+ p[3] = imm32 & 0xFF; imm32 >>= 8;
+ p[4] = imm32 & 0xFF; imm32 >>= 8;
+ p[5] = imm32 & 0xFF; imm32 >>= 8;
+ imm32 = 4 + (UInt)Ptr_to_ULong(location_of_counter);
+ p[9] = imm32 & 0xFF; imm32 >>= 8;
+ p[10] = imm32 & 0xFF; imm32 >>= 8;
+ p[11] = imm32 & 0xFF; imm32 >>= 8;
+ p[12] = imm32 & 0xFF; imm32 >>= 8;
+ VexInvalRange vir = {0, 0};
+ return vir;
+}
+
+
/*---------------------------------------------------------------*/
/*--- end host_x86_defs.c ---*/
/*---------------------------------------------------------------*/
diff --git a/main/VEX/priv/host_x86_defs.h b/main/VEX/priv/host_x86_defs.h
index f68a426..a5f281c 100644
--- a/main/VEX/priv/host_x86_defs.h
+++ b/main/VEX/priv/host_x86_defs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -349,7 +349,9 @@
Xin_Sh3232, /* shldl or shrdl */
Xin_Push, /* push (32-bit?) value on stack */
Xin_Call, /* call to address in register */
- Xin_Goto, /* conditional/unconditional jmp to dst */
+ Xin_XDirect, /* direct transfer to GA */
+ Xin_XIndir, /* indirect transfer to GA */
+ Xin_XAssisted, /* assisted transfer to GA */
Xin_CMov32, /* conditional move */
Xin_LoadEX, /* mov{s,z}{b,w}l from mem to reg */
Xin_Store, /* store 16/8 bit value in memory */
@@ -378,7 +380,9 @@
Xin_Sse64FLo, /* SSE binary, 64F in lowest lane only */
Xin_SseReRg, /* SSE binary general reg-reg, Re, Rg */
Xin_SseCMov, /* SSE conditional move */
- Xin_SseShuf /* SSE2 shuffle (pshufd) */
+ Xin_SseShuf, /* SSE2 shuffle (pshufd) */
+ Xin_EvCheck, /* Event check */
+ Xin_ProfInc /* 64-bit profile counter increment */
}
X86InstrTag;
@@ -444,13 +448,30 @@
Addr32 target;
Int regparms; /* 0 .. 3 */
} Call;
- /* Pseudo-insn. Goto dst, on given condition (which could be
- Xcc_ALWAYS). */
+ /* Update the guest EIP value, then exit requesting to chain
+ to it. May be conditional. Urr, use of Addr32 implicitly
+ assumes that wordsize(guest) == wordsize(host). */
struct {
+ Addr32 dstGA; /* next guest address */
+ X86AMode* amEIP; /* amode in guest state for EIP */
+ X86CondCode cond; /* can be Xcc_ALWAYS */
+ Bool toFastEP; /* chain to the slow or fast point? */
+ } XDirect;
+ /* Boring transfer to a guest address not known at JIT time.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ X86AMode* amEIP;
+ X86CondCode cond; /* can be Xcc_ALWAYS */
+ } XIndir;
+ /* Assisted transfer to a guest address, most general case.
+ Not chainable. May be conditional. */
+ struct {
+ HReg dstGA;
+ X86AMode* amEIP;
+ X86CondCode cond; /* can be Xcc_ALWAYS */
IRJumpKind jk;
- X86CondCode cond;
- X86RI* dst;
- } Goto;
+ } XAssisted;
/* Mov src to dst on the given condition, which may not
be the bogus Xcc_ALWAYS. */
struct {
@@ -615,6 +636,15 @@
HReg src;
HReg dst;
} SseShuf;
+ struct {
+ X86AMode* amCounter;
+ X86AMode* amFailAddr;
+ } EvCheck;
+ struct {
+ /* No fields. The address of the counter to inc is
+ installed later, post-translation, by patching it in,
+ as it is not known at translation time. */
+ } ProfInc;
} Xin;
}
@@ -632,7 +662,12 @@
extern X86Instr* X86Instr_Sh3232 ( X86ShiftOp, UInt amt, HReg src, HReg dst );
extern X86Instr* X86Instr_Push ( X86RMI* );
extern X86Instr* X86Instr_Call ( X86CondCode, Addr32, Int );
-extern X86Instr* X86Instr_Goto ( IRJumpKind, X86CondCode cond, X86RI* dst );
+extern X86Instr* X86Instr_XDirect ( Addr32 dstGA, X86AMode* amEIP,
+ X86CondCode cond, Bool toFastEP );
+extern X86Instr* X86Instr_XIndir ( HReg dstGA, X86AMode* amEIP,
+ X86CondCode cond );
+extern X86Instr* X86Instr_XAssisted ( HReg dstGA, X86AMode* amEIP,
+ X86CondCode cond, IRJumpKind jk );
extern X86Instr* X86Instr_CMov32 ( X86CondCode, X86RM* src, HReg dst );
extern X86Instr* X86Instr_LoadEX ( UChar szSmall, Bool syned,
X86AMode* src, HReg dst );
@@ -663,6 +698,9 @@
extern X86Instr* X86Instr_SseReRg ( X86SseOp, HReg, HReg );
extern X86Instr* X86Instr_SseCMov ( X86CondCode, HReg src, HReg dst );
extern X86Instr* X86Instr_SseShuf ( Int order, HReg src, HReg dst );
+extern X86Instr* X86Instr_EvCheck ( X86AMode* amCounter,
+ X86AMode* amFailAddr );
+extern X86Instr* X86Instr_ProfInc ( void );
extern void ppX86Instr ( X86Instr*, Bool );
@@ -672,10 +710,13 @@
extern void getRegUsage_X86Instr ( HRegUsage*, X86Instr*, Bool );
extern void mapRegs_X86Instr ( HRegRemap*, X86Instr*, Bool );
extern Bool isMove_X86Instr ( X86Instr*, HReg*, HReg* );
-extern Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr*,
- Bool,
- void* dispatch_unassisted,
- void* dispatch_assisted );
+extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc,
+ UChar* buf, Int nbuf, X86Instr* i,
+ Bool mode64,
+ void* disp_cp_chain_me_to_slowEP,
+ void* disp_cp_chain_me_to_fastEP,
+ void* disp_cp_xindir,
+ void* disp_cp_xassisted );
extern void genSpill_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
HReg rreg, Int offset, Bool );
@@ -685,9 +726,36 @@
extern X86Instr* directReload_X86 ( X86Instr* i,
HReg vreg, Short spill_off );
extern void getAllocableRegs_X86 ( Int*, HReg** );
-extern HInstrArray* iselSB_X86 ( IRSB*, VexArch,
- VexArchInfo*,
- VexAbiInfo* );
+extern HInstrArray* iselSB_X86 ( IRSB*,
+ VexArch,
+ VexArchInfo*,
+ VexAbiInfo*,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga );
+
+/* How big is an event check? This is kind of a kludge because it
+ depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER,
+ and so assumes that they are both <= 128, and so can use the short
+ offset encoding. This is all checked with assertions, so in the
+ worst case we will merely assert at startup. */
+extern Int evCheckSzB_X86 ( void );
+
+/* Perform a chaining and unchaining of an XDirect jump. */
+extern VexInvalRange chainXDirect_X86 ( void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to );
+
+extern VexInvalRange unchainXDirect_X86 ( void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me );
+
+/* Patch the counter location into an existing ProfInc point. */
+extern VexInvalRange patchProfInc_X86 ( void* place_to_patch,
+ ULong* location_of_counter );
+
#endif /* ndef __VEX_HOST_X86_DEFS_H */
diff --git a/main/VEX/priv/host_x86_isel.c b/main/VEX/priv/host_x86_isel.c
index 81896b3..d342d92 100644
--- a/main/VEX/priv/host_x86_isel.c
+++ b/main/VEX/priv/host_x86_isel.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -154,21 +154,38 @@
- The host subarchitecture we are selecting insns for.
This is set at the start and does not change.
- Note, this is all host-independent. */
+ - A Bool for indicating whether we may generate chain-me
+ instructions for control flow transfers, or whether we must use
+ XAssisted.
+
+ - The maximum guest address of any guest insn in this block.
+ Actually, the address of the highest-addressed byte from any insn
+ in this block. Is set at the start and does not change. This is
+ used for detecting jumps which are definitely forward-edges from
+ this block, and therefore can be made (chained) to the fast entry
+ point of the destination, thereby avoiding the destination's
+ event check.
+
+ Note, this is all (well, mostly) host-independent.
+*/
typedef
struct {
+ /* Constant -- are set at the start and do not change. */
IRTypeEnv* type_env;
HReg* vregmap;
HReg* vregmapHI;
Int n_vregmap;
- HInstrArray* code;
-
- Int vreg_ctr;
-
UInt hwcaps;
+
+ Bool chainingAllowed;
+ Addr64 max_ga;
+
+ /* These are modified as we go along. */
+ HInstrArray* code;
+ Int vreg_ctr;
}
ISelEnv;
@@ -772,14 +789,15 @@
/* --------- TERNARY OP --------- */
case Iex_Triop: {
+ IRTriop *triop = e->Iex.Triop.details;
/* C3210 flags following FPU partial remainder (fprem), both
IEEE compliant (PREM1) and non-IEEE compliant (PREM). */
- if (e->Iex.Triop.op == Iop_PRemC3210F64
- || e->Iex.Triop.op == Iop_PRem1C3210F64) {
+ if (triop->op == Iop_PRemC3210F64
+ || triop->op == Iop_PRem1C3210F64) {
HReg junk = newVRegF(env);
HReg dst = newVRegI(env);
- HReg srcL = iselDblExpr(env, e->Iex.Triop.arg2);
- HReg srcR = iselDblExpr(env, e->Iex.Triop.arg3);
+ HReg srcL = iselDblExpr(env, triop->arg2);
+ HReg srcR = iselDblExpr(env, triop->arg3);
/* XXXROUNDINGFIXME */
/* set roundingmode here */
addInstr(env, X86Instr_FpBinary(
@@ -2941,7 +2959,8 @@
if (e->tag == Iex_Triop) {
X86FpOp fpop = Xfp_INVALID;
- switch (e->Iex.Triop.op) {
+ IRTriop *triop = e->Iex.Triop.details;
+ switch (triop->op) {
case Iop_AddF64: fpop = Xfp_ADD; break;
case Iop_SubF64: fpop = Xfp_SUB; break;
case Iop_MulF64: fpop = Xfp_MUL; break;
@@ -2956,8 +2975,8 @@
}
if (fpop != Xfp_INVALID) {
HReg res = newVRegF(env);
- HReg srcL = iselDblExpr(env, e->Iex.Triop.arg2);
- HReg srcR = iselDblExpr(env, e->Iex.Triop.arg3);
+ HReg srcL = iselDblExpr(env, triop->arg2);
+ HReg srcR = iselDblExpr(env, triop->arg3);
/* XXXROUNDINGFIXME */
/* set roundingmode here */
addInstr(env, X86Instr_FpBinary(fpop,srcL,srcR,res));
@@ -3813,31 +3832,33 @@
/* --------- Indexed PUT --------- */
case Ist_PutI: {
+ IRPutI *puti = stmt->Ist.PutI.details;
+
X86AMode* am
= genGuestArrayOffset(
- env, stmt->Ist.PutI.descr,
- stmt->Ist.PutI.ix, stmt->Ist.PutI.bias );
+ env, puti->descr,
+ puti->ix, puti->bias );
- IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.PutI.data);
+ IRType ty = typeOfIRExpr(env->type_env, puti->data);
if (ty == Ity_F64) {
- HReg val = iselDblExpr(env, stmt->Ist.PutI.data);
+ HReg val = iselDblExpr(env, puti->data);
addInstr(env, X86Instr_FpLdSt( False/*store*/, 8, val, am ));
return;
}
if (ty == Ity_I8) {
- HReg r = iselIntExpr_R(env, stmt->Ist.PutI.data);
+ HReg r = iselIntExpr_R(env, puti->data);
addInstr(env, X86Instr_Store( 1, r, am ));
return;
}
if (ty == Ity_I32) {
- HReg r = iselIntExpr_R(env, stmt->Ist.PutI.data);
+ HReg r = iselIntExpr_R(env, puti->data);
addInstr(env, X86Instr_Alu32M( Xalu_MOV, X86RI_Reg(r), am ));
return;
}
if (ty == Ity_I64) {
HReg rHi, rLo;
X86AMode* am4 = advance4(am);
- iselInt64Expr(&rHi, &rLo, env, stmt->Ist.PutI.data);
+ iselInt64Expr(&rHi, &rLo, env, puti->data);
addInstr(env, X86Instr_Alu32M( Xalu_MOV, X86RI_Reg(rLo), am ));
addInstr(env, X86Instr_Alu32M( Xalu_MOV, X86RI_Reg(rHi), am4 ));
return;
@@ -4038,14 +4059,61 @@
/* --------- EXIT --------- */
case Ist_Exit: {
- X86RI* dst;
- X86CondCode cc;
if (stmt->Ist.Exit.dst->tag != Ico_U32)
- vpanic("isel_x86: Ist_Exit: dst is not a 32-bit value");
- dst = iselIntExpr_RI(env, IRExpr_Const(stmt->Ist.Exit.dst));
- cc = iselCondCode(env,stmt->Ist.Exit.guard);
- addInstr(env, X86Instr_Goto(stmt->Ist.Exit.jk, cc, dst));
- return;
+ vpanic("iselStmt(x86): Ist_Exit: dst is not a 32-bit value");
+
+ X86CondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
+ X86AMode* amEIP = X86AMode_IR(stmt->Ist.Exit.offsIP,
+ hregX86_EBP());
+
+ /* Case: boring transfer to known address */
+ if (stmt->Ist.Exit.jk == Ijk_Boring) {
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = ((Addr32)stmt->Ist.Exit.dst->Ico.U32) > env->max_ga;
+ if (0) vex_printf("%s", toFastEP ? "Y" : ",");
+ addInstr(env, X86Instr_XDirect(stmt->Ist.Exit.dst->Ico.U32,
+ amEIP, cc, toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, X86Instr_XAssisted(r, amEIP, cc, Ijk_Boring));
+ }
+ return;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (stmt->Ist.Exit.jk) {
+ /* Keep this list in sync with that in iselNext below */
+ case Ijk_ClientReq:
+ case Ijk_EmWarn:
+ case Ijk_MapFail:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_SigSEGV:
+ case Ijk_SigTRAP:
+ case Ijk_Sys_int128:
+ case Ijk_Sys_int129:
+ case Ijk_Sys_int130:
+ case Ijk_Sys_sysenter:
+ case Ijk_TInval:
+ case Ijk_Yield:
+ {
+ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
+ addInstr(env, X86Instr_XAssisted(r, amEIP, cc, stmt->Ist.Exit.jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Do we ever expect to see any other kind? */
+ goto stmt_fail;
}
default: break;
@@ -4060,18 +4128,95 @@
/*--- ISEL: Basic block terminators (Nexts) ---*/
/*---------------------------------------------------------*/
-static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk )
+static void iselNext ( ISelEnv* env,
+ IRExpr* next, IRJumpKind jk, Int offsIP )
{
- X86RI* ri;
if (vex_traceflags & VEX_TRACE_VCODE) {
- vex_printf("\n-- goto {");
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
ppIRJumpKind(jk);
- vex_printf("} ");
- ppIRExpr(next);
- vex_printf("\n");
+ vex_printf( "\n");
}
- ri = iselIntExpr_RI(env, next);
- addInstr(env, X86Instr_Goto(jk, Xcc_ALWAYS,ri));
+
+ /* Case: boring transfer to known address */
+ if (next->tag == Iex_Const) {
+ IRConst* cdst = next->Iex.Const.con;
+ vassert(cdst->tag == Ico_U32);
+ if (jk == Ijk_Boring || jk == Ijk_Call) {
+ /* Boring transfer to known address */
+ X86AMode* amEIP = X86AMode_IR(offsIP, hregX86_EBP());
+ if (env->chainingAllowed) {
+ /* .. almost always true .. */
+ /* Skip the event check at the dst if this is a forwards
+ edge. */
+ Bool toFastEP
+ = ((Addr64)cdst->Ico.U32) > env->max_ga;
+ if (0) vex_printf("%s", toFastEP ? "X" : ".");
+ addInstr(env, X86Instr_XDirect(cdst->Ico.U32,
+ amEIP, Xcc_ALWAYS,
+ toFastEP));
+ } else {
+ /* .. very occasionally .. */
+ /* We can't use chaining, so ask for an assisted transfer,
+ as that's the only alternative that is allowable. */
+ HReg r = iselIntExpr_R(env, next);
+ addInstr(env, X86Instr_XAssisted(r, amEIP, Xcc_ALWAYS,
+ Ijk_Boring));
+ }
+ return;
+ }
+ }
+
+ /* Case: call/return (==boring) transfer to any address */
+ switch (jk) {
+ case Ijk_Boring: case Ijk_Ret: case Ijk_Call: {
+ HReg r = iselIntExpr_R(env, next);
+ X86AMode* amEIP = X86AMode_IR(offsIP, hregX86_EBP());
+ if (env->chainingAllowed) {
+ addInstr(env, X86Instr_XIndir(r, amEIP, Xcc_ALWAYS));
+ } else {
+ addInstr(env, X86Instr_XAssisted(r, amEIP, Xcc_ALWAYS,
+ Ijk_Boring));
+ }
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* Case: assisted transfer to arbitrary address */
+ switch (jk) {
+ /* Keep this list in sync with that for Ist_Exit above */
+ case Ijk_ClientReq:
+ case Ijk_EmWarn:
+ case Ijk_MapFail:
+ case Ijk_NoDecode:
+ case Ijk_NoRedir:
+ case Ijk_SigSEGV:
+ case Ijk_SigTRAP:
+ case Ijk_Sys_int128:
+ case Ijk_Sys_int129:
+ case Ijk_Sys_int130:
+ case Ijk_Sys_sysenter:
+ case Ijk_TInval:
+ case Ijk_Yield:
+ {
+ HReg r = iselIntExpr_R(env, next);
+ X86AMode* amEIP = X86AMode_IR(offsIP, hregX86_EBP());
+ addInstr(env, X86Instr_XAssisted(r, amEIP, Xcc_ALWAYS, jk));
+ return;
+ }
+ default:
+ break;
+ }
+
+ vex_printf( "\n-- PUT(%d) = ", offsIP);
+ ppIRExpr( next );
+ vex_printf( "; exit-");
+ ppIRJumpKind(jk);
+ vex_printf( "\n");
+ vassert(0); // are we expecting any other kind?
}
@@ -4081,14 +4226,21 @@
/* Translate an entire SB to x86 code. */
-HInstrArray* iselSB_X86 ( IRSB* bb, VexArch arch_host,
- VexArchInfo* archinfo_host,
- VexAbiInfo* vbi/*UNUSED*/ )
+HInstrArray* iselSB_X86 ( IRSB* bb,
+ VexArch arch_host,
+ VexArchInfo* archinfo_host,
+ VexAbiInfo* vbi/*UNUSED*/,
+ Int offs_Host_EvC_Counter,
+ Int offs_Host_EvC_FailAddr,
+ Bool chainingAllowed,
+ Bool addProfInc,
+ Addr64 max_ga )
{
Int i, j;
HReg hreg, hregHI;
ISelEnv* env;
UInt hwcaps_host = archinfo_host->hwcaps;
+ X86AMode *amCounter, *amFailAddr;
/* sanity ... */
vassert(arch_host == VexArchX86);
@@ -4097,6 +4249,8 @@
| VEX_HWCAPS_X86_SSE2
| VEX_HWCAPS_X86_SSE3
| VEX_HWCAPS_X86_LZCNT)));
+ vassert(sizeof(max_ga) == 8);
+ vassert((max_ga >> 32) == 0);
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
@@ -4115,7 +4269,9 @@
env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
/* and finally ... */
- env->hwcaps = hwcaps_host;
+ env->chainingAllowed = chainingAllowed;
+ env->hwcaps = hwcaps_host;
+ env->max_ga = max_ga;
/* For each IR temporary, allocate a suitably-kinded virtual
register. */
@@ -4140,11 +4296,24 @@
}
env->vreg_ctr = j;
+ /* The very first instruction must be an event check. */
+ amCounter = X86AMode_IR(offs_Host_EvC_Counter, hregX86_EBP());
+ amFailAddr = X86AMode_IR(offs_Host_EvC_FailAddr, hregX86_EBP());
+ addInstr(env, X86Instr_EvCheck(amCounter, amFailAddr));
+
+ /* Possibly a block counter increment (for profiling). At this
+ point we don't know the address of the counter, so just pretend
+ it is zero. It will have to be patched later, but before this
+ translation is used, by a call to LibVEX_patchProfCtr. */
+ if (addProfInc) {
+ addInstr(env, X86Instr_ProfInc());
+ }
+
/* Ok, finally we can iterate over the statements. */
for (i = 0; i < bb->stmts_used; i++)
- iselStmt(env,bb->stmts[i]);
+ iselStmt(env, bb->stmts[i]);
- iselNext(env,bb->next,bb->jumpkind);
+ iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
/* record the number of vregs we used. */
env->code->n_vregs = env->vreg_ctr;
diff --git a/main/VEX/priv/ir_defs.c b/main/VEX/priv/ir_defs.c
index f68f21f..eb6bb41 100644
--- a/main/VEX/priv/ir_defs.c
+++ b/main/VEX/priv/ir_defs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -57,7 +57,11 @@
case Ity_F32: vex_printf( "F32"); break;
case Ity_F64: vex_printf( "F64"); break;
case Ity_F128: vex_printf( "F128"); break;
+ case Ity_D32: vex_printf( "D32"); break;
+ case Ity_D64: vex_printf( "D64"); break;
+ case Ity_D128: vex_printf( "D128"); break;
case Ity_V128: vex_printf( "V128"); break;
+ case Ity_V256: vex_printf( "V256"); break;
default: vex_printf("ty = 0x%x\n", (Int)ty);
vpanic("ppIRType");
}
@@ -82,6 +86,7 @@
break;
case Ico_F64i: vex_printf( "F64i{0x%llx}", con->Ico.F64i); break;
case Ico_V128: vex_printf( "V128{0x%04x}", (UInt)(con->Ico.V128)); break;
+ case Ico_V256: vex_printf( "V256{0x%08x}", con->Ico.V256); break;
default: vpanic("ppIRConst");
}
}
@@ -329,6 +334,8 @@
case Iop_TruncF64asF32: vex_printf("TruncF64asF32"); return;
case Iop_CalcFPRF: vex_printf("CalcFPRF"); return;
+ case Iop_QAdd32S: vex_printf("QAdd32S"); return;
+ case Iop_QSub32S: vex_printf("QSub32S"); return;
case Iop_Add16x2: vex_printf("Add16x2"); return;
case Iop_Sub16x2: vex_printf("Sub16x2"); return;
case Iop_QAdd16Sx2: vex_printf("QAdd16Sx2"); return;
@@ -587,19 +594,23 @@
case Iop_Div64Fx2: vex_printf("Div64Fx2"); return;
case Iop_Div64F0x2: vex_printf("Div64F0x2"); return;
+ case Iop_Max32Fx8: vex_printf("Max32Fx8"); return;
case Iop_Max32Fx4: vex_printf("Max32Fx4"); return;
case Iop_Max32Fx2: vex_printf("Max32Fx2"); return;
case Iop_PwMax32Fx4: vex_printf("PwMax32Fx4"); return;
case Iop_PwMax32Fx2: vex_printf("PwMax32Fx2"); return;
case Iop_Max32F0x4: vex_printf("Max32F0x4"); return;
+ case Iop_Max64Fx4: vex_printf("Max64Fx4"); return;
case Iop_Max64Fx2: vex_printf("Max64Fx2"); return;
case Iop_Max64F0x2: vex_printf("Max64F0x2"); return;
+ case Iop_Min32Fx8: vex_printf("Min32Fx8"); return;
case Iop_Min32Fx4: vex_printf("Min32Fx4"); return;
case Iop_Min32Fx2: vex_printf("Min32Fx2"); return;
case Iop_PwMin32Fx4: vex_printf("PwMin32Fx4"); return;
case Iop_PwMin32Fx2: vex_printf("PwMin32Fx2"); return;
case Iop_Min32F0x4: vex_printf("Min32F0x4"); return;
+ case Iop_Min64Fx4: vex_printf("Min64Fx4"); return;
case Iop_Min64Fx2: vex_printf("Min64Fx2"); return;
case Iop_Min64F0x2: vex_printf("Min64F0x2"); return;
@@ -611,6 +622,7 @@
case Iop_Recip32x2: vex_printf("Recip32x2"); return;
case Iop_Recip32Fx2: vex_printf("Recip32Fx2"); return;
case Iop_Recip32Fx4: vex_printf("Recip32Fx4"); return;
+ case Iop_Recip32Fx8: vex_printf("Recip32Fx8"); return;
case Iop_Recip32x4: vex_printf("Recip32x4"); return;
case Iop_Recip32F0x4: vex_printf("Recip32F0x4"); return;
case Iop_Recip64Fx2: vex_printf("Recip64Fx2"); return;
@@ -623,6 +635,7 @@
case Iop_RSqrt32Fx4: vex_printf("RSqrt32Fx4"); return;
case Iop_RSqrt32F0x4: vex_printf("RSqrt32F0x4"); return;
+ case Iop_RSqrt32Fx8: vex_printf("RSqrt32Fx8"); return;
case Iop_RSqrt64Fx2: vex_printf("RSqrt64Fx2"); return;
case Iop_RSqrt64F0x2: vex_printf("RSqrt64F0x2"); return;
@@ -630,7 +643,9 @@
case Iop_Sqrt32F0x4: vex_printf("Sqrt32F0x4"); return;
case Iop_Sqrt64Fx2: vex_printf("Sqrt64Fx2"); return;
case Iop_Sqrt64F0x2: vex_printf("Sqrt64F0x2"); return;
-
+ case Iop_Sqrt32Fx8: vex_printf("Sqrt32Fx8"); return;
+ case Iop_Sqrt64Fx4: vex_printf("Sqrt64Fx4"); return;
+
case Iop_Sub32Fx4: vex_printf("Sub32Fx4"); return;
case Iop_Sub32Fx2: vex_printf("Sub32Fx2"); return;
case Iop_Sub32F0x4: vex_printf("Sub32F0x4"); return;
@@ -918,6 +933,7 @@
case Iop_ExtractV128: vex_printf("ExtractV128"); return;
case Iop_Perm8x16: vex_printf("Perm8x16"); return;
+ case Iop_Perm32x4: vex_printf("Perm32x4"); return;
case Iop_Reverse16_8x16: vex_printf("Reverse16_8x16"); return;
case Iop_Reverse32_8x16: vex_printf("Reverse32_8x16"); return;
case Iop_Reverse32_16x8: vex_printf("Reverse32_16x8"); return;
@@ -934,6 +950,69 @@
case Iop_Fixed32UToF32x2_RN: vex_printf("Fixed32UToF32x2_RN"); return;
case Iop_Fixed32SToF32x2_RN: vex_printf("Fixed32SToF32x2_RN"); return;
+ case Iop_D32toD64: vex_printf("D32toD64"); return;
+ case Iop_D64toD32: vex_printf("D64toD32"); return;
+ case Iop_AddD64: vex_printf("AddD64"); return;
+ case Iop_SubD64: vex_printf("SubD64"); return;
+ case Iop_MulD64: vex_printf("MulD64"); return;
+ case Iop_DivD64: vex_printf("DivD64"); return;
+ case Iop_ShlD64: vex_printf("ShlD64"); return;
+ case Iop_ShrD64: vex_printf("ShrD64"); return;
+ case Iop_D64toI64S: vex_printf("D64toI64S"); return;
+ case Iop_I64StoD64: vex_printf("I64StoD64"); return;
+ case Iop_I64StoD128: vex_printf("I64StoD128"); return;
+ case Iop_D64toD128: vex_printf("D64toD128"); return;
+ case Iop_D128toD64: vex_printf("D128toD64"); return;
+ case Iop_D128toI64S: vex_printf("D128toI64S"); return;
+ case Iop_AddD128: vex_printf("AddD128"); return;
+ case Iop_SubD128: vex_printf("SubD128"); return;
+ case Iop_MulD128: vex_printf("MulD128"); return;
+ case Iop_DivD128: vex_printf("DivD128"); return;
+ case Iop_ShlD128: vex_printf("ShlD128"); return;
+ case Iop_ShrD128: vex_printf("ShrD128"); return;
+ case Iop_RoundD64toInt: vex_printf("Iop_RoundD64toInt"); return;
+ case Iop_RoundD128toInt: vex_printf("Iop_RoundD128toInt"); return;
+ case Iop_QuantizeD64: vex_printf("Iop_QuantizeD64"); return;
+ case Iop_QuantizeD128: vex_printf("Iop_QuantizeD128"); return;
+ case Iop_ExtractExpD64: vex_printf("Iop_ExtractExpD64"); return;
+ case Iop_ExtractExpD128: vex_printf("Iop_ExtractExpD128"); return;
+ case Iop_InsertExpD64: vex_printf("Iop_InsertExpD64"); return;
+ case Iop_InsertExpD128: vex_printf("Iop_InsertExpD128"); return;
+ case Iop_CmpD64: vex_printf("CmpD64"); return;
+ case Iop_CmpD128: vex_printf("CmpD128"); return;
+ case Iop_D64HLtoD128: vex_printf("D64HLtoD128"); return;
+ case Iop_D128HItoD64: vex_printf("D128HItoD64"); return;
+ case Iop_D128LOtoD64: vex_printf("D128LOtoD64"); return;
+ case Iop_SignificanceRoundD64: vex_printf("Iop_SignificanceRoundD64");
+ return;
+ case Iop_SignificanceRoundD128: vex_printf("Iop_SignificanceRoundD128");
+ return;
+ case Iop_ReinterpI64asD64: vex_printf("ReinterpI64asD64"); return;
+ case Iop_ReinterpD64asI64: vex_printf("ReinterpD64asI64"); return;
+ case Iop_V256to64_0: vex_printf("V256to64_0"); return;
+ case Iop_V256to64_1: vex_printf("V256to64_1"); return;
+ case Iop_V256to64_2: vex_printf("V256to64_2"); return;
+ case Iop_V256to64_3: vex_printf("V256to64_3"); return;
+ case Iop_64x4toV256: vex_printf("64x4toV256"); return;
+ case Iop_V256toV128_0: vex_printf("V256toV128_0"); return;
+ case Iop_V256toV128_1: vex_printf("V256toV128_1"); return;
+ case Iop_V128HLtoV256: vex_printf("V128HLtoV256"); return;
+ case Iop_DPBtoBCD: vex_printf("DPBtoBCD"); return;
+ case Iop_BCDtoDPB: vex_printf("BCDtoDPB"); return;
+ case Iop_Add64Fx4: vex_printf("Add64Fx4"); return;
+ case Iop_Sub64Fx4: vex_printf("Sub64Fx4"); return;
+ case Iop_Mul64Fx4: vex_printf("Mul64Fx4"); return;
+ case Iop_Div64Fx4: vex_printf("Div64Fx4"); return;
+ case Iop_Add32Fx8: vex_printf("Add32Fx8"); return;
+ case Iop_Sub32Fx8: vex_printf("Sub32Fx8"); return;
+ case Iop_Mul32Fx8: vex_printf("Mul32Fx8"); return;
+ case Iop_Div32Fx8: vex_printf("Div32Fx8"); return;
+ case Iop_AndV256: vex_printf("AndV256"); return;
+ case Iop_OrV256: vex_printf("OrV256"); return;
+ case Iop_XorV256: vex_printf("XorV256"); return;
+ case Iop_NotV256: vex_printf("NotV256"); return;
+ case Iop_CmpNEZ64x4: vex_printf("CmpNEZ64x4"); return;
+ case Iop_CmpNEZ32x8: vex_printf("CmpNEZ32x8"); return;
default: vpanic("ppIROp(1)");
}
@@ -969,28 +1048,32 @@
case Iex_RdTmp:
ppIRTemp(e->Iex.RdTmp.tmp);
break;
- case Iex_Qop:
- ppIROp(e->Iex.Qop.op);
+ case Iex_Qop: {
+ IRQop *qop = e->Iex.Qop.details;
+ ppIROp(qop->op);
vex_printf( "(" );
- ppIRExpr(e->Iex.Qop.arg1);
+ ppIRExpr(qop->arg1);
vex_printf( "," );
- ppIRExpr(e->Iex.Qop.arg2);
+ ppIRExpr(qop->arg2);
vex_printf( "," );
- ppIRExpr(e->Iex.Qop.arg3);
+ ppIRExpr(qop->arg3);
vex_printf( "," );
- ppIRExpr(e->Iex.Qop.arg4);
+ ppIRExpr(qop->arg4);
vex_printf( ")" );
break;
- case Iex_Triop:
- ppIROp(e->Iex.Triop.op);
+ }
+ case Iex_Triop: {
+ IRTriop *triop = e->Iex.Triop.details;
+ ppIROp(triop->op);
vex_printf( "(" );
- ppIRExpr(e->Iex.Triop.arg1);
+ ppIRExpr(triop->arg1);
vex_printf( "," );
- ppIRExpr(e->Iex.Triop.arg2);
+ ppIRExpr(triop->arg2);
vex_printf( "," );
- ppIRExpr(e->Iex.Triop.arg3);
+ ppIRExpr(triop->arg3);
vex_printf( ")" );
break;
+ }
case Iex_Binop:
ppIROp(e->Iex.Binop.op);
vex_printf( "(" );
@@ -1072,7 +1155,13 @@
for (i = 0; i < d->nFxState; i++) {
vex_printf(" ");
ppIREffect(d->fxState[i].fx);
- vex_printf("-gst(%d,%d)", d->fxState[i].offset, d->fxState[i].size);
+ vex_printf("-gst(%u,%u", (UInt)d->fxState[i].offset,
+ (UInt)d->fxState[i].size);
+ if (d->fxState[i].nRepeats > 0) {
+ vex_printf(",reps%u,step%u", (UInt)d->fxState[i].nRepeats,
+ (UInt)d->fxState[i].repeatLen);
+ }
+ vex_printf(")");
}
vex_printf(" ::: ");
ppIRCallee(d->cee);
@@ -1112,6 +1201,16 @@
vex_printf(")");
}
+void ppIRPutI ( IRPutI* puti )
+{
+ vex_printf( "PUTI" );
+ ppIRRegArray(puti->descr);
+ vex_printf("[");
+ ppIRExpr(puti->ix);
+ vex_printf(",%d] = ", puti->bias);
+ ppIRExpr(puti->data);
+}
+
void ppIRJumpKind ( IRJumpKind kind )
{
switch (kind) {
@@ -1120,7 +1219,6 @@
case Ijk_Ret: vex_printf("Return"); break;
case Ijk_ClientReq: vex_printf("ClientReq"); break;
case Ijk_Yield: vex_printf("Yield"); break;
- case Ijk_YieldNoRedir: vex_printf("YieldNoRedir"); break;
case Ijk_EmWarn: vex_printf("EmWarn"); break;
case Ijk_EmFail: vex_printf("EmFail"); break;
case Ijk_NoDecode: vex_printf("NoDecode"); break;
@@ -1179,12 +1277,7 @@
ppIRExpr(s->Ist.Put.data);
break;
case Ist_PutI:
- vex_printf( "PUTI" );
- ppIRRegArray(s->Ist.PutI.descr);
- vex_printf("[");
- ppIRExpr(s->Ist.PutI.ix);
- vex_printf(",%d] = ", s->Ist.PutI.bias);
- ppIRExpr(s->Ist.PutI.data);
+ ppIRPutI(s->Ist.PutI.details);
break;
case Ist_WrTmp:
ppIRTemp(s->Ist.WrTmp.tmp);
@@ -1227,10 +1320,11 @@
case Ist_Exit:
vex_printf( "if (" );
ppIRExpr(s->Ist.Exit.guard);
- vex_printf( ") goto {");
- ppIRJumpKind(s->Ist.Exit.jk);
- vex_printf("} ");
+ vex_printf( ") { PUT(%d) = ", s->Ist.Exit.offsIP);
ppIRConst(s->Ist.Exit.dst);
+ vex_printf("; exit-");
+ ppIRJumpKind(s->Ist.Exit.jk);
+ vex_printf(" } ");
break;
default:
vpanic("ppIRStmt");
@@ -1265,10 +1359,10 @@
ppIRStmt(bb->stmts[i]);
vex_printf( "\n");
}
- vex_printf( " goto {");
- ppIRJumpKind(bb->jumpkind);
- vex_printf( "} ");
+ vex_printf( " PUT(%d) = ", bb->offsIP );
ppIRExpr( bb->next );
+ vex_printf( "; exit-");
+ ppIRJumpKind(bb->jumpkind);
vex_printf( "\n}\n");
}
@@ -1352,6 +1446,13 @@
c->Ico.V128 = con;
return c;
}
+IRConst* IRConst_V256 ( UInt con )
+{
+ IRConst* c = LibVEX_Alloc(sizeof(IRConst));
+ c->tag = Ico_V256;
+ c->Ico.V256 = con;
+ return c;
+}
/* Constructors -- IRCallee */
@@ -1416,22 +1517,26 @@
IRExpr* IRExpr_Qop ( IROp op, IRExpr* arg1, IRExpr* arg2,
IRExpr* arg3, IRExpr* arg4 ) {
IRExpr* e = LibVEX_Alloc(sizeof(IRExpr));
+ IRQop* qop = LibVEX_Alloc(sizeof(IRQop));
+ qop->op = op;
+ qop->arg1 = arg1;
+ qop->arg2 = arg2;
+ qop->arg3 = arg3;
+ qop->arg4 = arg4;
e->tag = Iex_Qop;
- e->Iex.Qop.op = op;
- e->Iex.Qop.arg1 = arg1;
- e->Iex.Qop.arg2 = arg2;
- e->Iex.Qop.arg3 = arg3;
- e->Iex.Qop.arg4 = arg4;
+ e->Iex.Qop.details = qop;
return e;
}
IRExpr* IRExpr_Triop ( IROp op, IRExpr* arg1,
IRExpr* arg2, IRExpr* arg3 ) {
- IRExpr* e = LibVEX_Alloc(sizeof(IRExpr));
+ IRExpr* e = LibVEX_Alloc(sizeof(IRExpr));
+ IRTriop* triop = LibVEX_Alloc(sizeof(IRTriop));
+ triop->op = op;
+ triop->arg1 = arg1;
+ triop->arg2 = arg2;
+ triop->arg3 = arg3;
e->tag = Iex_Triop;
- e->Iex.Triop.op = op;
- e->Iex.Triop.arg1 = arg1;
- e->Iex.Triop.arg2 = arg2;
- e->Iex.Triop.arg3 = arg3;
+ e->Iex.Triop.details = triop;
return e;
}
IRExpr* IRExpr_Binop ( IROp op, IRExpr* arg1, IRExpr* arg2 ) {
@@ -1611,6 +1716,20 @@
}
+/* Constructors -- IRPutI */
+
+IRPutI* mkIRPutI ( IRRegArray* descr, IRExpr* ix,
+ Int bias, IRExpr* data )
+{
+ IRPutI* puti = LibVEX_Alloc(sizeof(IRPutI));
+ puti->descr = descr;
+ puti->ix = ix;
+ puti->bias = bias;
+ puti->data = data;
+ return puti;
+}
+
+
/* Constructors -- IRStmt */
IRStmt* IRStmt_NoOp ( void )
@@ -1643,14 +1762,10 @@
s->Ist.Put.data = data;
return s;
}
-IRStmt* IRStmt_PutI ( IRRegArray* descr, IRExpr* ix,
- Int bias, IRExpr* data ) {
- IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
- s->tag = Ist_PutI;
- s->Ist.PutI.descr = descr;
- s->Ist.PutI.ix = ix;
- s->Ist.PutI.bias = bias;
- s->Ist.PutI.data = data;
+IRStmt* IRStmt_PutI ( IRPutI* details ) {
+ IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
+ s->tag = Ist_PutI;
+ s->Ist.PutI.details = details;
return s;
}
IRStmt* IRStmt_WrTmp ( IRTemp tmp, IRExpr* data ) {
@@ -1699,12 +1814,14 @@
s->Ist.MBE.event = event;
return s;
}
-IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* dst ) {
- IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
- s->tag = Ist_Exit;
- s->Ist.Exit.guard = guard;
- s->Ist.Exit.jk = jk;
- s->Ist.Exit.dst = dst;
+IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* dst,
+ Int offsIP ) {
+ IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
+ s->tag = Ist_Exit;
+ s->Ist.Exit.guard = guard;
+ s->Ist.Exit.jk = jk;
+ s->Ist.Exit.dst = dst;
+ s->Ist.Exit.offsIP = offsIP;
return s;
}
@@ -1732,6 +1849,7 @@
bb->stmts = LibVEX_Alloc(bb->stmts_size * sizeof(IRStmt*));
bb->next = NULL;
bb->jumpkind = Ijk_Boring;
+ bb->offsIP = 0;
return bb;
}
@@ -1812,17 +1930,23 @@
e->Iex.GetI.bias);
case Iex_RdTmp:
return IRExpr_RdTmp(e->Iex.RdTmp.tmp);
- case Iex_Qop:
- return IRExpr_Qop(e->Iex.Qop.op,
- deepCopyIRExpr(e->Iex.Qop.arg1),
- deepCopyIRExpr(e->Iex.Qop.arg2),
- deepCopyIRExpr(e->Iex.Qop.arg3),
- deepCopyIRExpr(e->Iex.Qop.arg4));
- case Iex_Triop:
- return IRExpr_Triop(e->Iex.Triop.op,
- deepCopyIRExpr(e->Iex.Triop.arg1),
- deepCopyIRExpr(e->Iex.Triop.arg2),
- deepCopyIRExpr(e->Iex.Triop.arg3));
+ case Iex_Qop: {
+ IRQop* qop = e->Iex.Qop.details;
+
+ return IRExpr_Qop(qop->op,
+ deepCopyIRExpr(qop->arg1),
+ deepCopyIRExpr(qop->arg2),
+ deepCopyIRExpr(qop->arg3),
+ deepCopyIRExpr(qop->arg4));
+ }
+ case Iex_Triop: {
+ IRTriop *triop = e->Iex.Triop.details;
+
+ return IRExpr_Triop(triop->op,
+ deepCopyIRExpr(triop->arg1),
+ deepCopyIRExpr(triop->arg2),
+ deepCopyIRExpr(triop->arg3));
+ }
case Iex_Binop:
return IRExpr_Binop(e->Iex.Binop.op,
deepCopyIRExpr(e->Iex.Binop.arg1),
@@ -1878,6 +2002,14 @@
deepCopyIRExpr(cas->dataLo) );
}
+IRPutI* deepCopyIRPutI ( IRPutI * puti )
+{
+ return mkIRPutI( deepCopyIRRegArray(puti->descr),
+ deepCopyIRExpr(puti->ix),
+ puti->bias,
+ deepCopyIRExpr(puti->data));
+}
+
IRStmt* deepCopyIRStmt ( IRStmt* s )
{
switch (s->tag) {
@@ -1895,10 +2027,7 @@
return IRStmt_Put(s->Ist.Put.offset,
deepCopyIRExpr(s->Ist.Put.data));
case Ist_PutI:
- return IRStmt_PutI(deepCopyIRRegArray(s->Ist.PutI.descr),
- deepCopyIRExpr(s->Ist.PutI.ix),
- s->Ist.PutI.bias,
- deepCopyIRExpr(s->Ist.PutI.data));
+ return IRStmt_PutI(deepCopyIRPutI(s->Ist.PutI.details));
case Ist_WrTmp:
return IRStmt_WrTmp(s->Ist.WrTmp.tmp,
deepCopyIRExpr(s->Ist.WrTmp.data));
@@ -1922,7 +2051,8 @@
case Ist_Exit:
return IRStmt_Exit(deepCopyIRExpr(s->Ist.Exit.guard),
s->Ist.Exit.jk,
- deepCopyIRConst(s->Ist.Exit.dst));
+ deepCopyIRConst(s->Ist.Exit.dst),
+ s->Ist.Exit.offsIP);
default:
vpanic("deepCopyIRStmt");
}
@@ -1949,7 +2079,7 @@
sts2 = LibVEX_Alloc(bb2->stmts_used * sizeof(IRStmt*));
for (i = 0; i < bb2->stmts_used; i++)
sts2[i] = deepCopyIRStmt(bb->stmts[i]);
- bb2->stmts = sts2;
+ bb2->stmts = sts2;
return bb2;
}
@@ -1959,6 +2089,7 @@
bb2->tyenv = deepCopyIRTypeEnv(bb->tyenv);
bb2->next = deepCopyIRExpr(bb->next);
bb2->jumpkind = bb->jumpkind;
+ bb2->offsIP = bb->offsIP;
return bb2;
}
@@ -2013,6 +2144,7 @@
case Iop_Add32: case Iop_Sub32: case Iop_Mul32:
case Iop_Or32: case Iop_And32: case Iop_Xor32:
case Iop_Max32U:
+ case Iop_QAdd32S: case Iop_QSub32S:
case Iop_Add16x2: case Iop_Sub16x2:
case Iop_QAdd16Sx2: case Iop_QAdd16Ux2:
case Iop_QSub16Sx2: case Iop_QSub16Ux2:
@@ -2466,7 +2598,7 @@
case Iop_InterleaveOddLanes8x16: case Iop_InterleaveEvenLanes8x16:
case Iop_InterleaveOddLanes16x8: case Iop_InterleaveEvenLanes16x8:
case Iop_InterleaveOddLanes32x4: case Iop_InterleaveEvenLanes32x4:
- case Iop_Perm8x16:
+ case Iop_Perm8x16: case Iop_Perm32x4:
case Iop_Recps32Fx4:
case Iop_Rsqrts32Fx4:
BINARY(Ity_V128,Ity_V128, Ity_V128);
@@ -2592,6 +2724,126 @@
case Iop_F128toF32: BINARY(ity_RMode,Ity_F128, Ity_F32);
case Iop_F128toF64: BINARY(ity_RMode,Ity_F128, Ity_F64);
+ case Iop_D32toD64:
+ case Iop_ExtractExpD64:
+ UNARY(Ity_D64, Ity_D64);
+
+ case Iop_InsertExpD64:
+ BINARY(Ity_D64,Ity_D64, Ity_D64);
+
+ case Iop_ExtractExpD128:
+ UNARY(Ity_D128, Ity_D64);
+
+ case Iop_InsertExpD128:
+ BINARY(Ity_D64,Ity_D128, Ity_D128);
+
+ case Iop_D64toD128:
+ UNARY(Ity_D64, Ity_D128);
+
+ case Iop_ReinterpD64asI64:
+ UNARY(Ity_D64, Ity_I64);
+
+ case Iop_ReinterpI64asD64:
+ UNARY(Ity_I64, Ity_D64);
+
+ case Iop_RoundD64toInt:
+ BINARY(ity_RMode,Ity_D64, Ity_D64);
+
+ case Iop_RoundD128toInt:
+ BINARY(ity_RMode,Ity_D128, Ity_D128);
+
+ case Iop_I64StoD128: /* I64 bit pattern stored in Float register */
+ UNARY(Ity_D64, Ity_D128);
+
+ case Iop_DPBtoBCD:
+ case Iop_BCDtoDPB:
+ UNARY(Ity_I64, Ity_I64);
+
+ case Iop_D128HItoD64:
+ case Iop_D128LOtoD64:
+ UNARY(Ity_D128, Ity_D64);
+
+ case Iop_D128toI64S:
+ BINARY(ity_RMode, Ity_D128, Ity_D64);
+
+ case Iop_D64HLtoD128:
+ BINARY(Ity_D64, Ity_D64, Ity_D128);
+
+ case Iop_ShlD64:
+ case Iop_ShrD64:
+ BINARY(Ity_D64, Ity_I8, Ity_D64 );
+
+ case Iop_D64toD32:
+ case Iop_D64toI64S:
+ BINARY(ity_RMode, Ity_D64, Ity_D64);
+
+ case Iop_I64StoD64: /* I64 bit pattern stored in Float register */
+ BINARY(ity_RMode, Ity_D64, Ity_D64);
+
+ case Iop_CmpD64:
+ BINARY(Ity_D64,Ity_D64, Ity_I32);
+
+ case Iop_CmpD128:
+ BINARY(Ity_D128,Ity_D128, Ity_I32);
+
+ case Iop_QuantizeD64:
+ case Iop_SignificanceRoundD64:
+ TERNARY(ity_RMode,Ity_D64,Ity_D64, Ity_D64);
+
+ case Iop_QuantizeD128:
+ case Iop_SignificanceRoundD128:
+ TERNARY(ity_RMode,Ity_D128,Ity_D128, Ity_D128);
+
+ case Iop_ShlD128:
+ case Iop_ShrD128:
+ BINARY(Ity_D128, Ity_I8, Ity_D128 );
+
+ case Iop_AddD64:
+ case Iop_SubD64:
+ case Iop_MulD64:
+ case Iop_DivD64:
+ TERNARY( ity_RMode, Ity_D64, Ity_D64, Ity_D64 );
+
+ case Iop_D128toD64:
+ BINARY( ity_RMode, Ity_D128, Ity_D64 );
+
+ case Iop_AddD128:
+ case Iop_SubD128:
+ case Iop_MulD128:
+ case Iop_DivD128:
+ TERNARY(ity_RMode,Ity_D128,Ity_D128, Ity_D128);
+
+ case Iop_V256to64_0: case Iop_V256to64_1:
+ case Iop_V256to64_2: case Iop_V256to64_3:
+ UNARY(Ity_V256, Ity_I64);
+
+ case Iop_64x4toV256:
+ QUATERNARY(Ity_I64, Ity_I64, Ity_I64, Ity_I64, Ity_V256);
+
+ case Iop_Add64Fx4: case Iop_Sub64Fx4:
+ case Iop_Mul64Fx4: case Iop_Div64Fx4:
+ case Iop_Add32Fx8: case Iop_Sub32Fx8:
+ case Iop_Mul32Fx8: case Iop_Div32Fx8:
+ case Iop_AndV256: case Iop_OrV256:
+ case Iop_XorV256:
+ case Iop_Max32Fx8: case Iop_Min32Fx8:
+ case Iop_Max64Fx4: case Iop_Min64Fx4:
+ BINARY(Ity_V256,Ity_V256, Ity_V256);
+
+ case Iop_V256toV128_1: case Iop_V256toV128_0:
+ UNARY(Ity_V256, Ity_V128);
+
+ case Iop_V128HLtoV256:
+ BINARY(Ity_V128,Ity_V128, Ity_V256);
+
+ case Iop_NotV256:
+ case Iop_RSqrt32Fx8:
+ case Iop_Sqrt32Fx8:
+ case Iop_Sqrt64Fx4:
+ case Iop_Recip32Fx8:
+ case Iop_CmpNEZ64x4: case Iop_CmpNEZ32x8:
+ UNARY(Ity_V256, Ity_V256);
+
default:
ppIROp(op);
vpanic("typeOfPrimop");
@@ -2679,6 +2931,7 @@
case Ico_F64: return Ity_F64;
case Ico_F64i: return Ity_F64;
case Ico_V128: return Ity_V128;
+ case Ico_V256: return Ity_V256;
default: vpanic("typeOfIRConst");
}
}
@@ -2699,11 +2952,11 @@
case Iex_Const:
return typeOfIRConst(e->Iex.Const.con);
case Iex_Qop:
- typeOfPrimop(e->Iex.Qop.op,
+ typeOfPrimop(e->Iex.Qop.details->op,
&t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4);
return t_dst;
case Iex_Triop:
- typeOfPrimop(e->Iex.Triop.op,
+ typeOfPrimop(e->Iex.Triop.details->op,
&t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4);
return t_dst;
case Iex_Binop:
@@ -2736,7 +2989,8 @@
case Ity_I8: case Ity_I16: case Ity_I32:
case Ity_I64: case Ity_I128:
case Ity_F32: case Ity_F64: case Ity_F128:
- case Ity_V128:
+ case Ity_D32: case Ity_D64: case Ity_D128:
+ case Ity_V128: case Ity_V256:
return True;
default:
return False;
@@ -2764,6 +3018,9 @@
IRExpr* e;
IRDirty* di;
IRCAS* cas;
+ IRPutI* puti;
+ IRQop* qop;
+ IRTriop* triop;
switch (st->tag) {
case Ist_AbiHint:
@@ -2772,8 +3029,9 @@
case Ist_Put:
return isIRAtom(st->Ist.Put.data);
case Ist_PutI:
- return toBool( isIRAtom(st->Ist.PutI.ix)
- && isIRAtom(st->Ist.PutI.data) );
+ puti = st->Ist.PutI.details;
+ return toBool( isIRAtom(puti->ix)
+ && isIRAtom(puti->data) );
case Ist_WrTmp:
/* This is the only interesting case. The RHS can be any
expression, *but* all its subexpressions *must* be
@@ -2784,15 +3042,17 @@
case Iex_Get: return True;
case Iex_GetI: return isIRAtom(e->Iex.GetI.ix);
case Iex_RdTmp: return True;
- case Iex_Qop: return toBool(
- isIRAtom(e->Iex.Qop.arg1)
- && isIRAtom(e->Iex.Qop.arg2)
- && isIRAtom(e->Iex.Qop.arg3)
- && isIRAtom(e->Iex.Qop.arg4));
- case Iex_Triop: return toBool(
- isIRAtom(e->Iex.Triop.arg1)
- && isIRAtom(e->Iex.Triop.arg2)
- && isIRAtom(e->Iex.Triop.arg3));
+ case Iex_Qop: qop = e->Iex.Qop.details;
+ return toBool(
+ isIRAtom(qop->arg1)
+ && isIRAtom(qop->arg2)
+ && isIRAtom(qop->arg3)
+ && isIRAtom(qop->arg4));
+ case Iex_Triop: triop = e->Iex.Triop.details;
+ return toBool(
+ isIRAtom(triop->arg1)
+ && isIRAtom(triop->arg2)
+ && isIRAtom(triop->arg3));
case Iex_Binop: return toBool(
isIRAtom(e->Iex.Binop.arg1)
&& isIRAtom(e->Iex.Binop.arg2));
@@ -2942,17 +3202,21 @@
case Iex_RdTmp:
useBeforeDef_Temp(bb,stmt,expr->Iex.RdTmp.tmp,def_counts);
break;
- case Iex_Qop:
- useBeforeDef_Expr(bb,stmt,expr->Iex.Qop.arg1,def_counts);
- useBeforeDef_Expr(bb,stmt,expr->Iex.Qop.arg2,def_counts);
- useBeforeDef_Expr(bb,stmt,expr->Iex.Qop.arg3,def_counts);
- useBeforeDef_Expr(bb,stmt,expr->Iex.Qop.arg4,def_counts);
+ case Iex_Qop: {
+ IRQop* qop = expr->Iex.Qop.details;
+ useBeforeDef_Expr(bb,stmt,qop->arg1,def_counts);
+ useBeforeDef_Expr(bb,stmt,qop->arg2,def_counts);
+ useBeforeDef_Expr(bb,stmt,qop->arg3,def_counts);
+ useBeforeDef_Expr(bb,stmt,qop->arg4,def_counts);
break;
- case Iex_Triop:
- useBeforeDef_Expr(bb,stmt,expr->Iex.Triop.arg1,def_counts);
- useBeforeDef_Expr(bb,stmt,expr->Iex.Triop.arg2,def_counts);
- useBeforeDef_Expr(bb,stmt,expr->Iex.Triop.arg3,def_counts);
+ }
+ case Iex_Triop: {
+ IRTriop* triop = expr->Iex.Triop.details;
+ useBeforeDef_Expr(bb,stmt,triop->arg1,def_counts);
+ useBeforeDef_Expr(bb,stmt,triop->arg2,def_counts);
+ useBeforeDef_Expr(bb,stmt,triop->arg3,def_counts);
break;
+ }
case Iex_Binop:
useBeforeDef_Expr(bb,stmt,expr->Iex.Binop.arg1,def_counts);
useBeforeDef_Expr(bb,stmt,expr->Iex.Binop.arg2,def_counts);
@@ -2985,6 +3249,7 @@
Int i;
IRDirty* d;
IRCAS* cas;
+ IRPutI* puti;
switch (stmt->tag) {
case Ist_IMark:
break;
@@ -2996,8 +3261,9 @@
useBeforeDef_Expr(bb,stmt,stmt->Ist.Put.data,def_counts);
break;
case Ist_PutI:
- useBeforeDef_Expr(bb,stmt,stmt->Ist.PutI.ix,def_counts);
- useBeforeDef_Expr(bb,stmt,stmt->Ist.PutI.data,def_counts);
+ puti = stmt->Ist.PutI.details;
+ useBeforeDef_Expr(bb,stmt,puti->ix,def_counts);
+ useBeforeDef_Expr(bb,stmt,puti->data,def_counts);
break;
case Ist_WrTmp:
useBeforeDef_Expr(bb,stmt,stmt->Ist.WrTmp.data,def_counts);
@@ -3058,29 +3324,30 @@
break;
case Iex_Qop: {
IRType ttarg1, ttarg2, ttarg3, ttarg4;
- tcExpr(bb,stmt, expr->Iex.Qop.arg1, gWordTy );
- tcExpr(bb,stmt, expr->Iex.Qop.arg2, gWordTy );
- tcExpr(bb,stmt, expr->Iex.Qop.arg3, gWordTy );
- tcExpr(bb,stmt, expr->Iex.Qop.arg4, gWordTy );
- typeOfPrimop(expr->Iex.Qop.op,
+ IRQop* qop = expr->Iex.Qop.details;
+ tcExpr(bb,stmt, qop->arg1, gWordTy );
+ tcExpr(bb,stmt, qop->arg2, gWordTy );
+ tcExpr(bb,stmt, qop->arg3, gWordTy );
+ tcExpr(bb,stmt, qop->arg4, gWordTy );
+ typeOfPrimop(qop->op,
&t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4);
if (t_arg1 == Ity_INVALID || t_arg2 == Ity_INVALID
|| t_arg3 == Ity_INVALID || t_arg4 == Ity_INVALID) {
vex_printf(" op name: " );
- ppIROp(expr->Iex.Qop.op);
+ ppIROp(qop->op);
vex_printf("\n");
sanityCheckFail(bb,stmt,
"Iex.Qop: wrong arity op\n"
"... name of op precedes BB printout\n");
}
- ttarg1 = typeOfIRExpr(tyenv, expr->Iex.Qop.arg1);
- ttarg2 = typeOfIRExpr(tyenv, expr->Iex.Qop.arg2);
- ttarg3 = typeOfIRExpr(tyenv, expr->Iex.Qop.arg3);
- ttarg4 = typeOfIRExpr(tyenv, expr->Iex.Qop.arg4);
+ ttarg1 = typeOfIRExpr(tyenv, qop->arg1);
+ ttarg2 = typeOfIRExpr(tyenv, qop->arg2);
+ ttarg3 = typeOfIRExpr(tyenv, qop->arg3);
+ ttarg4 = typeOfIRExpr(tyenv, qop->arg4);
if (t_arg1 != ttarg1 || t_arg2 != ttarg2
|| t_arg3 != ttarg3 || t_arg4 != ttarg4) {
vex_printf(" op name: ");
- ppIROp(expr->Iex.Qop.op);
+ ppIROp(qop->op);
vex_printf("\n");
vex_printf(" op type is (");
ppIRType(t_arg1);
@@ -3109,26 +3376,27 @@
}
case Iex_Triop: {
IRType ttarg1, ttarg2, ttarg3;
- tcExpr(bb,stmt, expr->Iex.Triop.arg1, gWordTy );
- tcExpr(bb,stmt, expr->Iex.Triop.arg2, gWordTy );
- tcExpr(bb,stmt, expr->Iex.Triop.arg3, gWordTy );
- typeOfPrimop(expr->Iex.Triop.op,
+ IRTriop *triop = expr->Iex.Triop.details;
+ tcExpr(bb,stmt, triop->arg1, gWordTy );
+ tcExpr(bb,stmt, triop->arg2, gWordTy );
+ tcExpr(bb,stmt, triop->arg3, gWordTy );
+ typeOfPrimop(triop->op,
&t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4);
if (t_arg1 == Ity_INVALID || t_arg2 == Ity_INVALID
|| t_arg3 == Ity_INVALID || t_arg4 != Ity_INVALID) {
vex_printf(" op name: " );
- ppIROp(expr->Iex.Triop.op);
+ ppIROp(triop->op);
vex_printf("\n");
sanityCheckFail(bb,stmt,
"Iex.Triop: wrong arity op\n"
"... name of op precedes BB printout\n");
}
- ttarg1 = typeOfIRExpr(tyenv, expr->Iex.Triop.arg1);
- ttarg2 = typeOfIRExpr(tyenv, expr->Iex.Triop.arg2);
- ttarg3 = typeOfIRExpr(tyenv, expr->Iex.Triop.arg3);
+ ttarg1 = typeOfIRExpr(tyenv, triop->arg1);
+ ttarg2 = typeOfIRExpr(tyenv, triop->arg2);
+ ttarg3 = typeOfIRExpr(tyenv, triop->arg3);
if (t_arg1 != ttarg1 || t_arg2 != ttarg2 || t_arg3 != ttarg3) {
vex_printf(" op name: ");
- ppIROp(expr->Iex.Triop.op);
+ ppIROp(triop->op);
vex_printf("\n");
vex_printf(" op type is (");
ppIRType(t_arg1);
@@ -3191,7 +3459,7 @@
}
case Iex_Unop:
tcExpr(bb,stmt, expr->Iex.Unop.arg, gWordTy );
- typeOfPrimop(expr->Iex.Binop.op,
+ typeOfPrimop(expr->Iex.Unop.op,
&t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4);
if (t_arg1 == Ity_INVALID || t_arg2 != Ity_INVALID
|| t_arg3 != Ity_INVALID || t_arg4 != Ity_INVALID)
@@ -3248,6 +3516,7 @@
Int i;
IRDirty* d;
IRCAS* cas;
+ IRPutI* puti;
IRType tyExpd, tyData;
IRTypeEnv* tyenv = bb->tyenv;
switch (stmt->tag) {
@@ -3273,16 +3542,17 @@
sanityCheckFail(bb,stmt,"IRStmt.Put.data: cannot Put :: Ity_I1");
break;
case Ist_PutI:
- tcExpr( bb, stmt, stmt->Ist.PutI.data, gWordTy );
- tcExpr( bb, stmt, stmt->Ist.PutI.ix, gWordTy );
- if (typeOfIRExpr(tyenv,stmt->Ist.PutI.data) == Ity_I1)
+ puti = stmt->Ist.PutI.details;
+ tcExpr( bb, stmt, puti->data, gWordTy );
+ tcExpr( bb, stmt, puti->ix, gWordTy );
+ if (typeOfIRExpr(tyenv,puti->data) == Ity_I1)
sanityCheckFail(bb,stmt,"IRStmt.PutI.data: cannot PutI :: Ity_I1");
- if (typeOfIRExpr(tyenv,stmt->Ist.PutI.data)
- != stmt->Ist.PutI.descr->elemTy)
+ if (typeOfIRExpr(tyenv,puti->data)
+ != puti->descr->elemTy)
sanityCheckFail(bb,stmt,"IRStmt.PutI.data: data ty != elem ty");
- if (typeOfIRExpr(tyenv,stmt->Ist.PutI.ix) != Ity_I32)
+ if (typeOfIRExpr(tyenv,puti->ix) != Ity_I32)
sanityCheckFail(bb,stmt,"IRStmt.PutI.ix: not :: Ity_I32");
- if (!saneIRRegArray(stmt->Ist.PutI.descr))
+ if (!saneIRRegArray(puti->descr))
sanityCheckFail(bb,stmt,"IRStmt.PutI.descr: invalid descr");
break;
case Ist_WrTmp:
@@ -3395,12 +3665,31 @@
for (i = 0; i < d->nFxState; i++) {
if (d->fxState[i].fx == Ifx_None) goto bad_dirty;
if (d->fxState[i].size <= 0) goto bad_dirty;
+ if (d->fxState[i].nRepeats == 0) {
+ if (d->fxState[i].repeatLen != 0) goto bad_dirty;
+ } else {
+ if (d->fxState[i].repeatLen <= d->fxState[i].size)
+ goto bad_dirty;
+ /* the % is safe because of the .size check above */
+ if ((d->fxState[i].repeatLen % d->fxState[i].size) != 0)
+ goto bad_dirty;
+ }
}
- /* check types, minimally */
+ /* check guard */
if (d->guard == NULL) goto bad_dirty;
tcExpr( bb, stmt, d->guard, gWordTy );
if (typeOfIRExpr(tyenv, d->guard) != Ity_I1)
sanityCheckFail(bb,stmt,"IRStmt.Dirty.guard not :: Ity_I1");
+ /* A dirty helper that is executed conditionally (or not at
+ all) may not return a value. Hence if .tmp is not
+ IRTemp_INVALID, .guard must be manifestly True at JIT
+ time. */
+ if (d->tmp != IRTemp_INVALID
+ && (d->guard->tag != Iex_Const
+ || d->guard->Iex.Const.con->Ico.U1 == 0))
+ sanityCheckFail(bb,stmt,"IRStmt.Dirty with a return value"
+ " is executed under a condition");
+ /* check types, minimally */
if (d->tmp != IRTemp_INVALID
&& typeOfIRTemp(tyenv, d->tmp) == Ity_I1)
sanityCheckFail(bb,stmt,"IRStmt.Dirty.dst :: Ity_I1");
@@ -3432,6 +3721,9 @@
sanityCheckFail(bb,stmt,"IRStmt.Exit.dst: bad dst");
if (typeOfIRConst(stmt->Ist.Exit.dst) != gWordTy)
sanityCheckFail(bb,stmt,"IRStmt.Exit.dst: not :: guest word type");
+ /* because it would intersect with host_EvC_* */
+ if (stmt->Ist.Exit.offsIP < 16)
+ sanityCheckFail(bb,stmt,"IRStmt.Exit.offsIP: too low");
break;
default:
vpanic("tcStmt");
@@ -3558,6 +3850,10 @@
tcStmt( bb, bb->stmts[i], guest_word_size );
if (typeOfIRExpr(bb->tyenv,bb->next) != guest_word_size)
sanityCheckFail(bb, NULL, "bb->next field has wrong type");
+ /* because it would intersect with host_EvC_* */
+ if (bb->offsIP < 16)
+ sanityCheckFail(bb, NULL, "bb->offsIP: too low");
+
}
/*---------------------------------------------------------------*/
@@ -3580,6 +3876,7 @@
case Ico_F64: return toBool( c1->Ico.F64 == c2->Ico.F64 );
case Ico_F64i: return toBool( c1->Ico.F64i == c2->Ico.F64i );
case Ico_V128: return toBool( c1->Ico.V128 == c2->Ico.V128 );
+ case Ico_V256: return toBool( c1->Ico.V256 == c2->Ico.V256 );
default: vpanic("eqIRConst");
}
}
@@ -3602,7 +3899,11 @@
case Ity_F32: return 4;
case Ity_F64: return 8;
case Ity_F128: return 16;
+ case Ity_D32: return 4;
+ case Ity_D64: return 8;
+ case Ity_D128: return 16;
case Ity_V128: return 16;
+ case Ity_V256: return 32;
default: vex_printf("\n"); ppIRType(ty); vex_printf("\n");
vpanic("sizeofIRType");
}
diff --git a/main/VEX/priv/ir_match.c b/main/VEX/priv/ir_match.c
index 39e483c..bf4030e 100644
--- a/main/VEX/priv/ir_match.c
+++ b/main/VEX/priv/ir_match.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/main/VEX/priv/ir_match.h b/main/VEX/priv/ir_match.h
index 0db1be7..96d8169 100644
--- a/main/VEX/priv/ir_match.h
+++ b/main/VEX/priv/ir_match.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/main/VEX/priv/ir_opt.c b/main/VEX/priv/ir_opt.c
index cb7f507..6d93b63 100644
--- a/main/VEX/priv/ir_opt.c
+++ b/main/VEX/priv/ir_opt.c
@@ -1,3 +1,4 @@
+/* -*- mode: C; c-basic-offset: 3; -*- */
/*---------------------------------------------------------------*/
/*--- begin ir_opt.c ---*/
@@ -7,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -45,6 +46,9 @@
/* Set to 1 for lots of debugging output. */
#define DEBUG_IROPT 0
+/* Set to 1 to gather some statistics. Currently only for sameIRExprs. */
+#define STATS_IROPT 0
+
/* What iropt does, 29 Dec 04.
@@ -65,12 +69,20 @@
not marked as being read or modified by the helper cannot be
assumed to be up-to-date at the point where the helper is called.
- * Immediately prior to any load or store, those parts of the guest
+ * If iropt_register_updates == VexRegUpdUnwindregsAtMemAccess :
+ Immediately prior to any load or store, those parts of the guest
state marked as requiring precise exceptions will be up to date.
Also, guest memory will be up to date. Parts of the guest state
not marked as requiring precise exceptions cannot be assumed to
be up-to-date at the point of the load/store.
+ If iropt_register_updates == VexRegUpdAllregsAtMemAccess:
+ Same as minimal, but all the guest state is up to date at memory
+ exception points.
+
+ If iropt_register_updates == VexRegUpdAllregsAtEachInsn :
+ Guest state is up to date at each instruction.
+
The relative order of loads and stores (including loads/stores of
guest memory done by dirty helpers annotated as such) is not
changed. However, the relative order of loads with no intervening
@@ -286,24 +298,28 @@
IRStmt_WrTmp(t1, ex));
return IRExpr_RdTmp(t1);
- case Iex_Qop:
+ case Iex_Qop: {
+ IRQop* qop = ex->Iex.Qop.details;
t1 = newIRTemp(bb->tyenv, ty);
addStmtToIRSB(bb, IRStmt_WrTmp(t1,
- IRExpr_Qop(ex->Iex.Qop.op,
- flatten_Expr(bb, ex->Iex.Qop.arg1),
- flatten_Expr(bb, ex->Iex.Qop.arg2),
- flatten_Expr(bb, ex->Iex.Qop.arg3),
- flatten_Expr(bb, ex->Iex.Qop.arg4))));
+ IRExpr_Qop(qop->op,
+ flatten_Expr(bb, qop->arg1),
+ flatten_Expr(bb, qop->arg2),
+ flatten_Expr(bb, qop->arg3),
+ flatten_Expr(bb, qop->arg4))));
return IRExpr_RdTmp(t1);
+ }
- case Iex_Triop:
+ case Iex_Triop: {
+ IRTriop* triop = ex->Iex.Triop.details;
t1 = newIRTemp(bb->tyenv, ty);
addStmtToIRSB(bb, IRStmt_WrTmp(t1,
- IRExpr_Triop(ex->Iex.Triop.op,
- flatten_Expr(bb, ex->Iex.Triop.arg1),
- flatten_Expr(bb, ex->Iex.Triop.arg2),
- flatten_Expr(bb, ex->Iex.Triop.arg3))));
+ IRExpr_Triop(triop->op,
+ flatten_Expr(bb, triop->arg1),
+ flatten_Expr(bb, triop->arg2),
+ flatten_Expr(bb, triop->arg3))));
return IRExpr_RdTmp(t1);
+ }
case Iex_Binop:
t1 = newIRTemp(bb->tyenv, ty);
@@ -380,6 +396,7 @@
IRExpr *e1, *e2, *e3, *e4, *e5;
IRDirty *d, *d2;
IRCAS *cas, *cas2;
+ IRPutI *puti, *puti2;
switch (st->tag) {
case Ist_Put:
if (isIRAtom(st->Ist.Put.data)) {
@@ -393,12 +410,11 @@
}
break;
case Ist_PutI:
- e1 = flatten_Expr(bb, st->Ist.PutI.ix);
- e2 = flatten_Expr(bb, st->Ist.PutI.data);
- addStmtToIRSB(bb, IRStmt_PutI(st->Ist.PutI.descr,
- e1,
- st->Ist.PutI.bias,
- e2));
+ puti = st->Ist.PutI.details;
+ e1 = flatten_Expr(bb, puti->ix);
+ e2 = flatten_Expr(bb, puti->data);
+ puti2 = mkIRPutI(puti->descr, e1, puti->bias, e2);
+ addStmtToIRSB(bb, IRStmt_PutI(puti2));
break;
case Ist_WrTmp:
if (isFlat(st->Ist.WrTmp.data)) {
@@ -463,7 +479,8 @@
case Ist_Exit:
e1 = flatten_Expr(bb, st->Ist.Exit.guard);
addStmtToIRSB(bb, IRStmt_Exit(e1, st->Ist.Exit.jk,
- st->Ist.Exit.dst));
+ st->Ist.Exit.dst,
+ st->Ist.Exit.offsIP));
break;
default:
vex_printf("\n");
@@ -485,6 +502,7 @@
flatten_Stmt( out, in->stmts[i] );
out->next = flatten_Expr( out, in->next );
out->jumpkind = in->jumpkind;
+ out->offsIP = in->offsIP;
return out;
}
@@ -622,7 +640,7 @@
typeOfIRExpr(bb->tyenv,st->Ist.Put.data) );
} else {
vassert(st->tag == Ist_PutI);
- key = mk_key_GetIPutI( st->Ist.PutI.descr );
+ key = mk_key_GetIPutI( st->Ist.PutI.details->descr );
}
k_lo = (key >> 16) & 0xFFFF;
@@ -744,8 +762,8 @@
break;
case Ist_PutI:
- vassert(isIRAtom(st->Ist.PutI.ix));
- vassert(isIRAtom(st->Ist.PutI.data));
+ vassert(isIRAtom(st->Ist.PutI.details->ix));
+ vassert(isIRAtom(st->Ist.PutI.details->data));
break;
case Ist_NoOp:
@@ -764,20 +782,29 @@
of the environment corresponding to guest state that may not
be reordered with respect to memory references. That means
at least the stack pointer. */
- for (j = 0; j < env->used; j++) {
- if (!env->inuse[j])
- continue;
- if (vex_control.iropt_precise_memory_exns) {
- /* Precise exceptions required. Flush all guest state. */
- env->inuse[j] = False;
- } else {
- /* Just flush the minimal amount required, as computed by
- preciseMemExnsFn. */
- HWord k_lo = (env->key[j] >> 16) & 0xFFFF;
- HWord k_hi = env->key[j] & 0xFFFF;
- if (preciseMemExnsFn( k_lo, k_hi ))
+ switch (vex_control.iropt_register_updates) {
+ case VexRegUpdAllregsAtMemAccess:
+ /* Precise exceptions required at mem access.
+ Flush all guest state. */
+ for (j = 0; j < env->used; j++)
env->inuse[j] = False;
- }
+ break;
+ case VexRegUpdUnwindregsAtMemAccess:
+ for (j = 0; j < env->used; j++) {
+ if (!env->inuse[j])
+ continue;
+ /* Just flush the minimal amount required, as computed by
+ preciseMemExnsFn. */
+ HWord k_lo = (env->key[j] >> 16) & 0xFFFF;
+ HWord k_hi = env->key[j] & 0xFFFF;
+ if (preciseMemExnsFn( k_lo, k_hi ))
+ env->inuse[j] = False;
+ }
+ break;
+ default:
+ // VexRegUpdAllregsAtEachInsn cannot happen here.
+ // Neither any rubbish other value.
+ vassert(0);
}
} /* if (memRW) */
@@ -810,7 +837,19 @@
IRStmt* st;
UInt key = 0; /* keep gcc -O happy */
+ vassert
+ (vex_control.iropt_register_updates == VexRegUpdUnwindregsAtMemAccess
+ || vex_control.iropt_register_updates == VexRegUpdAllregsAtMemAccess);
+
HashHW* env = newHHW();
+
+ /* Initialise the running env with the fact that the final exit
+ writes the IP (or, whatever it claims to write. We don't
+ care.) */
+ key = mk_key_GetPut(bb->offsIP, typeOfIRExpr(bb->tyenv, bb->next));
+ addToHHW(env, (HWord)key, 0);
+
+ /* And now scan backwards through the statements. */
for (i = bb->stmts_used-1; i >= 0; i--) {
st = bb->stmts[i];
@@ -819,13 +858,32 @@
/* Deal with conditional exits. */
if (st->tag == Ist_Exit) {
- /* Since control may not get beyond this point, we must empty
- out the set, since we can no longer claim that the next
- event for any part of the guest state is definitely a
- write. */
- vassert(isIRAtom(st->Ist.Exit.guard));
+ //Bool re_add;
+ /* Need to throw out from the env, any part of it which
+ doesn't overlap with the guest state written by this exit.
+ Since the exit only writes one section, it's simplest to
+ do this: (1) check whether env contains a write that
+ completely overlaps the write done by this exit; (2) empty
+ out env; and (3) if (1) was true, add the write done by
+ this exit.
+
+ To make (1) a bit simpler, merely search for a write that
+ exactly matches the one done by this exit. That's safe
+ because it will fail as often or more often than a full
+ overlap check, and failure to find an overlapping write in
+ env is the safe case (we just nuke env if that
+ happens). */
+ //vassert(isIRAtom(st->Ist.Exit.guard));
+ /* (1) */
+ //key = mk_key_GetPut(st->Ist.Exit.offsIP,
+ // typeOfIRConst(st->Ist.Exit.dst));
+ //re_add = lookupHHW(env, NULL, key);
+ /* (2) */
for (j = 0; j < env->used; j++)
env->inuse[j] = False;
+ /* (3) */
+ //if (0 && re_add)
+ // addToHHW(env, (HWord)key, 0);
continue;
}
@@ -839,9 +897,9 @@
break;
case Ist_PutI:
isPut = True;
- key = mk_key_GetIPutI( st->Ist.PutI.descr );
- vassert(isIRAtom(st->Ist.PutI.ix));
- vassert(isIRAtom(st->Ist.PutI.data));
+ key = mk_key_GetIPutI( st->Ist.PutI.details->descr );
+ vassert(isIRAtom(st->Ist.PutI.details->ix));
+ vassert(isIRAtom(st->Ist.PutI.details->data));
break;
default:
isPut = False;
@@ -882,41 +940,190 @@
/*--- Constant propagation and folding ---*/
/*---------------------------------------------------------------*/
+#if STATS_IROPT
+/* How often sameIRExprs was invoked */
+static UInt invocation_count;
+/* How often sameIRExprs recursed through IRTemp assignments */
+static UInt recursion_count;
+/* How often sameIRExprs found identical IRExprs */
+static UInt success_count;
+/* How often recursing through assignments to IRTemps helped
+ establishing equality. */
+static UInt recursion_success_count;
+/* Whether or not recursing through an IRTemp assignment helped
+ establishing IRExpr equality for a given sameIRExprs invocation. */
+static Bool recursion_helped;
+/* Whether or not a given sameIRExprs invocation recursed through an
+ IRTemp assignment */
+static Bool recursed;
+/* Maximum number of nodes ever visited when comparing two IRExprs. */
+static UInt max_nodes_visited;
+#endif /* STATS_IROPT */
+
+/* Count the number of nodes visited for a given sameIRExprs invocation. */
+static UInt num_nodes_visited;
+
+/* Do not visit more than NODE_LIMIT nodes when comparing two IRExprs.
+ This is to guard against performance degradation by visiting large
+ trees without success. */
+#define NODE_LIMIT 30
+
+
/* The env in this section is a map from IRTemp to IRExpr*,
that is, an array indexed by IRTemp. */
-/* Are both expressions simply the same IRTemp ? */
-static Bool sameIRTemps ( IRExpr* e1, IRExpr* e2 )
+/* Do both expressions compute the same value? The answer is generally
+ conservative, i.e. it will report that the expressions do not compute
+ the same value when in fact they do. The reason is that we do not
+ keep track of changes in the guest state and memory. Thusly, two
+ Get's, GetI's or Load's, even when accessing the same location, will be
+ assumed to compute different values. After all the accesses may happen
+ at different times and the guest state / memory can have changed in
+ the meantime.
+
+ XXX IMPORTANT XXX the two expressions must have the same IR type.
+ DO NOT CALL HERE WITH DIFFERENTLY-TYPED EXPRESSIONS. */
+
+/* JRS 20-Mar-2012: split sameIRExprs_aux into a fast inlineable
+ wrapper that deals with the common tags-don't-match case, and a
+ slower out of line general case. Saves a few insns. */
+
+__attribute__((noinline))
+static Bool sameIRExprs_aux2 ( IRExpr** env, IRExpr* e1, IRExpr* e2 );
+
+inline
+static Bool sameIRExprs_aux ( IRExpr** env, IRExpr* e1, IRExpr* e2 )
{
- return toBool( e1->tag == Iex_RdTmp
- && e2->tag == Iex_RdTmp
- && e1->Iex.RdTmp.tmp == e2->Iex.RdTmp.tmp );
+ if (e1->tag != e2->tag) return False;
+ return sameIRExprs_aux2(env, e1, e2);
}
-static Bool sameIcoU32s ( IRExpr* e1, IRExpr* e2 )
+__attribute__((noinline))
+static Bool sameIRExprs_aux2 ( IRExpr** env, IRExpr* e1, IRExpr* e2 )
{
- return toBool( e1->tag == Iex_Const
- && e2->tag == Iex_Const
- && e1->Iex.Const.con->tag == Ico_U32
- && e2->Iex.Const.con->tag == Ico_U32
- && e1->Iex.Const.con->Ico.U32
- == e2->Iex.Const.con->Ico.U32 );
-}
+ if (num_nodes_visited++ > NODE_LIMIT) return False;
-/* Are both expressions either the same IRTemp or IRConst-U32s ? If
- in doubt, say No. */
-static Bool sameIRTempsOrIcoU32s ( IRExpr* e1, IRExpr* e2 )
-{
switch (e1->tag) {
case Iex_RdTmp:
- return sameIRTemps(e1, e2);
- case Iex_Const:
- return sameIcoU32s(e1, e2);
- default:
+ if (e1->Iex.RdTmp.tmp == e2->Iex.RdTmp.tmp) return True;
+
+ if (env[e1->Iex.RdTmp.tmp] && env[e2->Iex.RdTmp.tmp]) {
+ Bool same = sameIRExprs_aux(env, env[e1->Iex.RdTmp.tmp],
+ env[e2->Iex.RdTmp.tmp]);
+#if STATS_IROPT
+ recursed = True;
+ if (same) recursion_helped = True;
+#endif
+ return same;
+ }
return False;
+
+ case Iex_Get:
+ case Iex_GetI:
+ case Iex_Load:
+ /* Guest state / memory could have changed in the meantime. */
+ return False;
+
+ case Iex_Binop:
+ return toBool( e1->Iex.Binop.op == e2->Iex.Binop.op
+ && sameIRExprs_aux( env, e1->Iex.Binop.arg1,
+ e2->Iex.Binop.arg1 )
+ && sameIRExprs_aux( env, e1->Iex.Binop.arg2,
+ e2->Iex.Binop.arg2 ));
+
+ case Iex_Unop:
+ return toBool( e1->Iex.Unop.op == e2->Iex.Unop.op
+ && sameIRExprs_aux( env, e1->Iex.Unop.arg,
+ e2->Iex.Unop.arg ));
+
+ case Iex_Const: {
+ IRConst *c1 = e1->Iex.Const.con;
+ IRConst *c2 = e2->Iex.Const.con;
+ vassert(c1->tag == c2->tag);
+ switch (c1->tag) {
+ case Ico_U1: return toBool( c1->Ico.U1 == c2->Ico.U1 );
+ case Ico_U8: return toBool( c1->Ico.U8 == c2->Ico.U8 );
+ case Ico_U16: return toBool( c1->Ico.U16 == c2->Ico.U16 );
+ case Ico_U32: return toBool( c1->Ico.U32 == c2->Ico.U32 );
+ case Ico_U64: return toBool( c1->Ico.U64 == c2->Ico.U64 );
+ default: break;
+ }
+ return False;
+ }
+
+ case Iex_Triop: {
+ IRTriop *tri1 = e1->Iex.Triop.details;
+ IRTriop *tri2 = e2->Iex.Triop.details;
+ return toBool( tri1->op == tri2->op
+ && sameIRExprs_aux( env, tri1->arg1, tri2->arg1 )
+ && sameIRExprs_aux( env, tri1->arg2, tri2->arg2 )
+ && sameIRExprs_aux( env, tri1->arg3, tri2->arg3 ));
+ }
+
+ case Iex_Mux0X:
+ return toBool( sameIRExprs_aux( env, e1->Iex.Mux0X.cond,
+ e2->Iex.Mux0X.cond )
+ && sameIRExprs_aux( env, e1->Iex.Mux0X.expr0,
+ e2->Iex.Mux0X.expr0 )
+ && sameIRExprs_aux( env, e1->Iex.Mux0X.exprX,
+ e2->Iex.Mux0X.exprX ));
+
+ default:
+ /* Not very likely to be "same". */
+ break;
}
+
+ return False;
}
+inline
+static Bool sameIRExprs ( IRExpr** env, IRExpr* e1, IRExpr* e2 )
+{
+ Bool same;
+
+ num_nodes_visited = 0;
+ same = sameIRExprs_aux(env, e1, e2);
+
+#if STATS_IROPT
+ ++invocation_count;
+ if (recursed) ++recursion_count;
+ success_count += same;
+ if (same && recursion_helped)
+ ++recursion_success_count;
+ if (num_nodes_visited > max_nodes_visited)
+ max_nodes_visited = num_nodes_visited;
+ recursed = False; /* reset */
+ recursion_helped = False; /* reset */
+#endif /* STATS_IROPT */
+
+ return same;
+}
+
+
+/* Debugging-only hack (not used in production runs): make a guess
+ whether sameIRExprs might assert due to the two args being of
+ different types. If in doubt return False. Is only used when
+ --vex-iropt-level > 0, that is, vex_control.iropt_verbosity > 0.
+ Bad because it duplicates functionality from typeOfIRExpr. See
+ comment on the single use point below for rationale. */
+static
+Bool debug_only_hack_sameIRExprs_might_assert ( IRExpr* e1, IRExpr* e2 )
+{
+ if (e1->tag != e2->tag) return False;
+ switch (e1->tag) {
+ case Iex_Const: {
+ /* The only interesting case */
+ IRConst *c1 = e1->Iex.Const.con;
+ IRConst *c2 = e2->Iex.Const.con;
+ return c1->tag != c2->tag;
+ }
+ default:
+ break;
+ }
+ return False;
+}
+
+
/* Is this literally IRExpr_Const(IRConst_U32(0)) ? */
static Bool isZeroU32 ( IRExpr* e )
{
@@ -925,6 +1132,14 @@
&& e->Iex.Const.con->Ico.U32 == 0);
}
+/* Is this literally IRExpr_Const(IRConst_U32(1---1)) ? */
+static Bool isOnesU32 ( IRExpr* e )
+{
+ return toBool( e->tag == Iex_Const
+ && e->Iex.Const.con->tag == Ico_U32
+ && e->Iex.Const.con->Ico.U32 == 0xFFFFFFFF );
+}
+
/* Is this literally IRExpr_Const(IRConst_U64(0)) ? */
static Bool isZeroU64 ( IRExpr* e )
{
@@ -933,6 +1148,35 @@
&& e->Iex.Const.con->Ico.U64 == 0);
}
+/* Is this an integer constant with value 0 ? */
+static Bool isZeroU ( IRExpr* e )
+{
+ if (e->tag != Iex_Const) return False;
+ switch (e->Iex.Const.con->tag) {
+ case Ico_U1: return toBool( e->Iex.Const.con->Ico.U1 == 0);
+ case Ico_U8: return toBool( e->Iex.Const.con->Ico.U8 == 0);
+ case Ico_U16: return toBool( e->Iex.Const.con->Ico.U16 == 0);
+ case Ico_U32: return toBool( e->Iex.Const.con->Ico.U32 == 0);
+ case Ico_U64: return toBool( e->Iex.Const.con->Ico.U64 == 0);
+ default: vpanic("isZeroU");
+ }
+}
+
+/* Is this an integer constant with value 1---1b ? */
+static Bool isOnesU ( IRExpr* e )
+{
+ if (e->tag != Iex_Const) return False;
+ switch (e->Iex.Const.con->tag) {
+ case Ico_U8: return toBool( e->Iex.Const.con->Ico.U8 == 0xFF);
+ case Ico_U16: return toBool( e->Iex.Const.con->Ico.U16 == 0xFFFF);
+ case Ico_U32: return toBool( e->Iex.Const.con->Ico.U32
+ == 0xFFFFFFFF);
+ case Ico_U64: return toBool( e->Iex.Const.con->Ico.U64
+ == 0xFFFFFFFFFFFFFFFFULL);
+ default: ppIRExpr(e); vpanic("isOnesU");
+ }
+}
+
static Bool notBool ( Bool b )
{
if (b == True) return False;
@@ -945,6 +1189,7 @@
static IRExpr* mkZeroOfPrimopResultType ( IROp op )
{
switch (op) {
+ case Iop_CmpNE32: return IRExpr_Const(IRConst_U1(toBool(0)));
case Iop_Xor8: return IRExpr_Const(IRConst_U8(0));
case Iop_Xor16: return IRExpr_Const(IRConst_U16(0));
case Iop_Sub32:
@@ -961,13 +1206,24 @@
static IRExpr* mkOnesOfPrimopResultType ( IROp op )
{
switch (op) {
+ case Iop_CmpEQ32:
case Iop_CmpEQ64:
return IRExpr_Const(IRConst_U1(toBool(1)));
+ case Iop_Or8:
+ return IRExpr_Const(IRConst_U8(0xFF));
+ case Iop_Or16:
+ return IRExpr_Const(IRConst_U16(0xFFFF));
+ case Iop_Or32:
+ return IRExpr_Const(IRConst_U32(0xFFFFFFFF));
case Iop_CmpEQ8x8:
+ case Iop_Or64:
return IRExpr_Const(IRConst_U64(0xFFFFFFFFFFFFFFFFULL));
case Iop_CmpEQ8x16:
+ case Iop_CmpEQ16x8:
+ case Iop_CmpEQ32x4:
return IRExpr_Const(IRConst_V128(0xFFFF));
default:
+ ppIROp(op);
vpanic("mkOnesOfPrimopResultType: bad primop");
}
}
@@ -997,16 +1253,33 @@
return 0;
}
+/* V64 holds 8 summary-constant bits in V128/V256 style. Convert to
+ the corresponding real constant. */
+//XXX re-check this before use
+//static ULong de_summarise_V64 ( UChar v64 )
+//{
+// ULong r = 0;
+// if (v64 & (1<<0)) r |= 0x00000000000000FFULL;
+// if (v64 & (1<<1)) r |= 0x000000000000FF00ULL;
+// if (v64 & (1<<2)) r |= 0x0000000000FF0000ULL;
+// if (v64 & (1<<3)) r |= 0x00000000FF000000ULL;
+// if (v64 & (1<<4)) r |= 0x000000FF00000000ULL;
+// if (v64 & (1<<5)) r |= 0x0000FF0000000000ULL;
+// if (v64 & (1<<6)) r |= 0x00FF000000000000ULL;
+// if (v64 & (1<<7)) r |= 0xFF00000000000000ULL;
+// return r;
+//}
-static IRExpr* fold_Expr ( IRExpr* e )
+static IRExpr* fold_Expr ( IRExpr** env, IRExpr* e )
{
Int shift;
IRExpr* e2 = e; /* e2 is the result of folding e, if possible */
- /* UNARY ops */
- if (e->tag == Iex_Unop
- && e->Iex.Unop.arg->tag == Iex_Const) {
- switch (e->Iex.Unop.op) {
+ switch (e->tag) {
+ case Iex_Unop:
+ /* UNARY ops */
+ if (e->Iex.Unop.arg->tag == Iex_Const) {
+ switch (e->Iex.Unop.op) {
case Iop_1Uto8:
e2 = IRExpr_Const(IRConst_U8(toUChar(
e->Iex.Unop.arg->Iex.Const.con->Ico.U1
@@ -1104,6 +1377,10 @@
)));
break;
+ case Iop_NotV128:
+ e2 = IRExpr_Const(IRConst_V128(
+ ~ (e->Iex.Unop.arg->Iex.Const.con->Ico.V128)));
+ break;
case Iop_Not64:
e2 = IRExpr_Const(IRConst_U64(
~ (e->Iex.Unop.arg->Iex.Const.con->Ico.U64)));
@@ -1248,13 +1525,67 @@
break;
}
+ /* For these vector ones, can't fold all cases, but at least
+ do the most obvious one. Could do better here using
+ summarise/desummarise of vector constants, but too
+ difficult to verify; hence just handle the zero cases. */
+ case Iop_32UtoV128: {
+ UInt u32 = e->Iex.Unop.arg->Iex.Const.con->Ico.U32;
+ if (0 == u32) {
+ e2 = IRExpr_Const(IRConst_V128(0x0000));
+ } else {
+ goto unhandled;
+ }
+ break;
+ }
+ case Iop_V128to64: {
+ UShort v128 = e->Iex.Unop.arg->Iex.Const.con->Ico.V128;
+ if (0 == ((v128 >> 0) & 0xFF)) {
+ e2 = IRExpr_Const(IRConst_U64(0));
+ } else {
+ goto unhandled;
+ }
+ break;
+ }
+ case Iop_V128HIto64: {
+ UShort v128 = e->Iex.Unop.arg->Iex.Const.con->Ico.V128;
+ if (0 == ((v128 >> 8) & 0xFF)) {
+ e2 = IRExpr_Const(IRConst_U64(0));
+ } else {
+ goto unhandled;
+ }
+ break;
+ }
+ case Iop_64UtoV128: {
+ ULong u64 = e->Iex.Unop.arg->Iex.Const.con->Ico.U64;
+ if (0 == u64) {
+ e2 = IRExpr_Const(IRConst_V128(0x0000));
+ } else {
+ goto unhandled;
+ }
+ break;
+ }
+
+ /* Even stupider (although still correct ..) */
+ case Iop_V256to64_0: case Iop_V256to64_1:
+ case Iop_V256to64_2: case Iop_V256to64_3: {
+ UInt v256 = e->Iex.Unop.arg->Iex.Const.con->Ico.V256;
+ if (v256 == 0x00000000) {
+ e2 = IRExpr_Const(IRConst_U64(0));
+ } else {
+ goto unhandled;
+ }
+ break;
+ }
+
default:
goto unhandled;
}
- }
+ }
+ break;
- /* BINARY ops */
- if (e->tag == Iex_Binop) {
+ case Iex_Binop:
+ /* BINARY ops */
if (e->Iex.Binop.arg1->tag == Iex_Const
&& e->Iex.Binop.arg2->tag == Iex_Const) {
/* cases where both args are consts */
@@ -1281,6 +1612,11 @@
(e->Iex.Binop.arg1->Iex.Const.con->Ico.U64
| e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)));
break;
+ case Iop_OrV128:
+ e2 = IRExpr_Const(IRConst_V128(
+ (e->Iex.Binop.arg1->Iex.Const.con->Ico.V128
+ | e->Iex.Binop.arg2->Iex.Const.con->Ico.V128)));
+ break;
/* -- Xor -- */
case Iop_Xor8:
@@ -1303,6 +1639,11 @@
(e->Iex.Binop.arg1->Iex.Const.con->Ico.U64
^ e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)));
break;
+ case Iop_XorV128:
+ e2 = IRExpr_Const(IRConst_V128(
+ (e->Iex.Binop.arg1->Iex.Const.con->Ico.V128
+ ^ e->Iex.Binop.arg2->Iex.Const.con->Ico.V128)));
+ break;
/* -- And -- */
case Iop_And8:
@@ -1325,6 +1666,11 @@
(e->Iex.Binop.arg1->Iex.Const.con->Ico.U64
& e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)));
break;
+ case Iop_AndV128:
+ e2 = IRExpr_Const(IRConst_V128(
+ (e->Iex.Binop.arg1->Iex.Const.con->Ico.V128
+ & e->Iex.Binop.arg2->Iex.Const.con->Ico.V128)));
+ break;
/* -- Add -- */
case Iop_Add8:
@@ -1563,7 +1909,8 @@
/* -- nHLto2n -- */
case Iop_32HLto64:
e2 = IRExpr_Const(IRConst_U64(
- (((ULong)(e->Iex.Binop.arg1->Iex.Const.con->Ico.U32)) << 32)
+ (((ULong)(e->Iex.Binop.arg1
+ ->Iex.Const.con->Ico.U32)) << 32)
| ((ULong)(e->Iex.Binop.arg2->Iex.Const.con->Ico.U32))
));
break;
@@ -1573,6 +1920,35 @@
handle it, so as to stop getting blasted with
no-rule-for-this-primop messages. */
break;
+ /* For this vector one, can't fold all cases, but at
+ least do the most obvious one. Could do better here
+ using summarise/desummarise of vector constants, but
+ too difficult to verify; hence just handle the zero
+ cases. */
+ case Iop_64HLtoV128: {
+ ULong argHi = e->Iex.Binop.arg1->Iex.Const.con->Ico.U64;
+ ULong argLo = e->Iex.Binop.arg2->Iex.Const.con->Ico.U64;
+ if (0 == argHi && 0 == argLo) {
+ e2 = IRExpr_Const(IRConst_V128(0));
+ } else {
+ goto unhandled;
+ }
+ break;
+ }
+
+ /* -- V128 stuff -- */
+ case Iop_InterleaveLO8x16: {
+ /* This turns up a lot in Memcheck instrumentation of
+ Icc generated code. I don't know why. */
+ UShort arg1 = e->Iex.Binop.arg1->Iex.Const.con->Ico.V128;
+ UShort arg2 = e->Iex.Binop.arg2->Iex.Const.con->Ico.V128;
+ if (0 == arg1 && 0 == arg2) {
+ e2 = IRExpr_Const(IRConst_V128(0));
+ } else {
+ goto unhandled;
+ }
+ break;
+ }
default:
goto unhandled;
@@ -1581,170 +1957,195 @@
} else {
/* other cases (identities, etc) */
-
- /* Shl64/Shr64(x,0) ==> x */
- if ((e->Iex.Binop.op == Iop_Shl64 || e->Iex.Binop.op == Iop_Shr64)
- && e->Iex.Binop.arg2->tag == Iex_Const
- && e->Iex.Binop.arg2->Iex.Const.con->Ico.U8 == 0) {
- e2 = e->Iex.Binop.arg1;
- } else
-
- /* Shl32/Shr32(x,0) ==> x */
- if ((e->Iex.Binop.op == Iop_Shl32 || e->Iex.Binop.op == Iop_Shr32)
- && e->Iex.Binop.arg2->tag == Iex_Const
- && e->Iex.Binop.arg2->Iex.Const.con->Ico.U8 == 0) {
- e2 = e->Iex.Binop.arg1;
- } else
-
- /* Or8(x,0) ==> x */
- if ((e->Iex.Binop.op == Iop_Or8)
- && e->Iex.Binop.arg2->tag == Iex_Const
- && e->Iex.Binop.arg2->Iex.Const.con->Ico.U8 == 0) {
- e2 = e->Iex.Binop.arg1;
- } else
-
- /* Or16(x,0) ==> x */
- if ((e->Iex.Binop.op == Iop_Or16)
- && e->Iex.Binop.arg2->tag == Iex_Const
- && e->Iex.Binop.arg2->Iex.Const.con->Ico.U16 == 0) {
- e2 = e->Iex.Binop.arg1;
- } else
-
- /* Or32/Add32/Max32U(x,0) ==> x
- Or32/Add32/Max32U(0,x) ==> x */
- if (e->Iex.Binop.op == Iop_Add32
- || e->Iex.Binop.op == Iop_Or32 || e->Iex.Binop.op == Iop_Max32U) {
- if (isZeroU32(e->Iex.Binop.arg2))
- e2 = e->Iex.Binop.arg1;
- else if (isZeroU32(e->Iex.Binop.arg1))
- e2 = e->Iex.Binop.arg2;
- } else
-
- /* Sub64(x,0) ==> x */
- if (e->Iex.Binop.op == Iop_Sub64 && isZeroU64(e->Iex.Binop.arg2)) {
- e2 = e->Iex.Binop.arg1;
- } else
-
- /* Add32(t,t) ==> t << 1. Memcheck doesn't understand that
- x+x produces a defined least significant bit, and it seems
- simplest just to get rid of the problem by rewriting it
- out, since the opportunity to do so exists. */
- if (e->Iex.Binop.op == Iop_Add32
- && e->Iex.Binop.arg1->tag == Iex_RdTmp
- && e->Iex.Binop.arg2->tag == Iex_RdTmp
- && e->Iex.Binop.arg1->Iex.RdTmp.tmp
- == e->Iex.Binop.arg2->Iex.RdTmp.tmp) {
- e2 = IRExpr_Binop(Iop_Shl32,
- e->Iex.Binop.arg1,
- IRExpr_Const(IRConst_U8(1)));
- } else
-
- /* Add64(t,t) ==> t << 1; rationale as for Add32(t,t) above. */
- if (e->Iex.Binop.op == Iop_Add64
- && e->Iex.Binop.arg1->tag == Iex_RdTmp
- && e->Iex.Binop.arg2->tag == Iex_RdTmp
- && e->Iex.Binop.arg1->Iex.RdTmp.tmp
- == e->Iex.Binop.arg2->Iex.RdTmp.tmp) {
- e2 = IRExpr_Binop(Iop_Shl64,
- e->Iex.Binop.arg1,
- IRExpr_Const(IRConst_U8(1)));
- } else
-
- /* Add8(t,t) ==> t << 1; rationale as for Add32(t,t) above. */
- if (e->Iex.Binop.op == Iop_Add8
- && e->Iex.Binop.arg1->tag == Iex_RdTmp
- && e->Iex.Binop.arg2->tag == Iex_RdTmp
- && e->Iex.Binop.arg1->Iex.RdTmp.tmp
- == e->Iex.Binop.arg2->Iex.RdTmp.tmp) {
- e2 = IRExpr_Binop(Iop_Shl8,
- e->Iex.Binop.arg1,
- IRExpr_Const(IRConst_U8(1)));
- } else
- /* NB no Add16(t,t) case yet as no known test case exists */
-
- /* Or64/Add64(x,0) ==> x
- Or64/Add64(0,x) ==> x */
- if (e->Iex.Binop.op == Iop_Add64 || e->Iex.Binop.op == Iop_Or64) {
- if (isZeroU64(e->Iex.Binop.arg2))
- e2 = e->Iex.Binop.arg1;
- else if (isZeroU64(e->Iex.Binop.arg1))
- e2 = e->Iex.Binop.arg2;
- } else
-
- /* And32(x,0xFFFFFFFF) ==> x */
- if (e->Iex.Binop.op == Iop_And32
- && e->Iex.Binop.arg2->tag == Iex_Const
- && e->Iex.Binop.arg2->Iex.Const.con->Ico.U32 == 0xFFFFFFFF) {
- e2 = e->Iex.Binop.arg1;
- } else
-
- /* And32(x,0) ==> 0 */
- if (e->Iex.Binop.op == Iop_And32
- && e->Iex.Binop.arg2->tag == Iex_Const
- && e->Iex.Binop.arg2->Iex.Const.con->Ico.U32 == 0) {
- e2 = IRExpr_Const(IRConst_U32(0));
- } else
-
- /* And32/Shl32(0,x) ==> 0 */
- if ((e->Iex.Binop.op == Iop_And32 || e->Iex.Binop.op == Iop_Shl32)
- && e->Iex.Binop.arg1->tag == Iex_Const
- && e->Iex.Binop.arg1->Iex.Const.con->Ico.U32 == 0) {
- e2 = IRExpr_Const(IRConst_U32(0));
- } else
-
- /* Or8(0,x) ==> x */
- if (e->Iex.Binop.op == Iop_Or8
- && e->Iex.Binop.arg1->tag == Iex_Const
- && e->Iex.Binop.arg1->Iex.Const.con->Ico.U8 == 0) {
- e2 = e->Iex.Binop.arg2;
- } else
-
- /* Or8/16/32/64/V128(t,t) ==> t, for some IRTemp t */
- /* And8/16/32/64(t,t) ==> t, for some IRTemp t */
- /* Max32U(t,t) ==> t, for some IRTemp t */
switch (e->Iex.Binop.op) {
- case Iop_And64: case Iop_And32:
- case Iop_And16: case Iop_And8:
- case Iop_Or64: case Iop_Or32:
- case Iop_Or16: case Iop_Or8: case Iop_OrV128:
- case Iop_Max32U:
- if (sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2))
+
+ case Iop_Shl32:
+ case Iop_Shl64:
+ case Iop_Shr64:
+ /* Shl32/Shl64/Shr64(x,0) ==> x */
+ if (isZeroU(e->Iex.Binop.arg2)) {
e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ /* Shl32/Shl64/Shr64(0,x) ==> 0 */
+ if (isZeroU(e->Iex.Binop.arg1)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
break;
- default:
- break;
- }
- /* Xor8/16/32/64/V128(t,t) ==> 0, for some IRTemp t */
- /* Sub32/64(t,t) ==> 0, for some IRTemp t */
- switch (e->Iex.Binop.op) {
- case Iop_Xor64: case Iop_Xor32:
- case Iop_Xor16: case Iop_Xor8:
- case Iop_XorV128:
- case Iop_Sub64: case Iop_Sub32:
- if (sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2))
+ case Iop_Shr32:
+ /* Shr32(x,0) ==> x */
+ if (isZeroU(e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ break;
+
+ case Iop_Or8:
+ case Iop_Or16:
+ case Iop_Or32:
+ case Iop_Or64:
+ case Iop_Max32U:
+ /* Or8/Or16/Or32/Or64/Max32U(x,0) ==> x */
+ if (isZeroU(e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ /* Or8/Or16/Or32/Or64/Max32U(0,x) ==> x */
+ if (isZeroU(e->Iex.Binop.arg1)) {
+ e2 = e->Iex.Binop.arg2;
+ break;
+ }
+ /* Or8/Or16/Or32/Or64/Max32U(x,1---1b) ==> 1---1b */
+ /* Or8/Or16/Or32/Or64/Max32U(1---1b,x) ==> 1---1b */
+ if (isOnesU(e->Iex.Binop.arg1) || isOnesU(e->Iex.Binop.arg2)) {
+ e2 = mkOnesOfPrimopResultType(e->Iex.Binop.op);
+ break;
+ }
+ /* Or8/Or16/Or32/Or64/Max32U(t,t) ==> t, for some IRTemp t */
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ break;
+
+ case Iop_Add8:
+ /* Add8(t,t) ==> t << 1.
+ Memcheck doesn't understand that
+ x+x produces a defined least significant bit, and it seems
+ simplest just to get rid of the problem by rewriting it
+ out, since the opportunity to do so exists. */
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
+ e2 = IRExpr_Binop(Iop_Shl8, e->Iex.Binop.arg1,
+ IRExpr_Const(IRConst_U8(1)));
+ break;
+ }
+ break;
+
+ /* NB no Add16(t,t) case yet as no known test case exists */
+
+ case Iop_Add32:
+ case Iop_Add64:
+ /* Add32/Add64(x,0) ==> x */
+ if (isZeroU(e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ /* Add32/Add64(0,x) ==> x */
+ if (isZeroU(e->Iex.Binop.arg1)) {
+ e2 = e->Iex.Binop.arg2;
+ break;
+ }
+ /* Add32/Add64(t,t) ==> t << 1. Same rationale as for Add8. */
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
+ e2 = IRExpr_Binop(
+ e->Iex.Binop.op == Iop_Add32 ? Iop_Shl32 : Iop_Shl64,
+ e->Iex.Binop.arg1, IRExpr_Const(IRConst_U8(1)));
+ break;
+ }
+ break;
+
+ case Iop_Sub64:
+ /* Sub64(x,0) ==> x */
+ if (isZeroU64(e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ /* Sub64(t,t) ==> 0, for some IRTemp t */
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
e2 = mkZeroOfPrimopResultType(e->Iex.Binop.op);
+ break;
+ }
break;
- default:
- break;
- }
- switch (e->Iex.Binop.op) {
+ case Iop_And32:
+ /* And32(x,0xFFFFFFFF) ==> x */
+ if (isOnesU32(e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ /* And32(x,0) ==> 0 */
+ if (isZeroU32(e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg2;
+ break;
+ }
+ /* And32(0,x) ==> 0 */
+ if (isZeroU32(e->Iex.Binop.arg1)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ /* And32(t,t) ==> t, for some IRTemp t */
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ break;
+
+ case Iop_And8:
+ case Iop_And16:
+ case Iop_And64:
+ case Iop_AndV128:
+ case Iop_AndV256:
+ /* And8/And16/And64/AndV128/AndV256(t,t)
+ ==> t, for some IRTemp t */
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ break;
+
+ case Iop_OrV128:
+ case Iop_OrV256:
+ /* V128/V256(t,t) ==> t, for some IRTemp t */
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
+ e2 = e->Iex.Binop.arg1;
+ break;
+ }
+ break;
+
+ case Iop_Xor8:
+ case Iop_Xor16:
+ case Iop_Xor32:
+ case Iop_Xor64:
+ case Iop_XorV128:
+ /* Xor8/16/32/64/V128(t,t) ==> 0, for some IRTemp t */
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
+ e2 = mkZeroOfPrimopResultType(e->Iex.Binop.op);
+ break;
+ }
+ break;
+
+ case Iop_Sub32:
+ case Iop_CmpNE32:
+ /* Sub32/CmpNE32(t,t) ==> 0, for some IRTemp t */
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
+ e2 = mkZeroOfPrimopResultType(e->Iex.Binop.op);
+ break;
+ }
+ break;
+
+ case Iop_CmpEQ32:
case Iop_CmpEQ64:
case Iop_CmpEQ8x8:
case Iop_CmpEQ8x16:
- if (sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2))
+ case Iop_CmpEQ16x8:
+ case Iop_CmpEQ32x4:
+ if (sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
e2 = mkOnesOfPrimopResultType(e->Iex.Binop.op);
+ break;
+ }
break;
+
default:
break;
}
-
}
- }
+ break;
- /* Mux0X */
- if (e->tag == Iex_Mux0X) {
+ case Iex_Mux0X:
+ /* Mux0X */
+
/* is the discriminant is a constant? */
if (e->Iex.Mux0X.cond->tag == Iex_Const) {
Bool zero;
@@ -1756,17 +2157,41 @@
}
else
/* are the arms identical? (pretty weedy test) */
- if (sameIRTempsOrIcoU32s(e->Iex.Mux0X.expr0,
- e->Iex.Mux0X.exprX)) {
+ if (sameIRExprs(env, e->Iex.Mux0X.expr0,
+ e->Iex.Mux0X.exprX)) {
e2 = e->Iex.Mux0X.expr0;
}
+ break;
+
+ default:
+ /* not considered */
+ break;
}
- /* Show cases where we've found but not folded 'op(t,t)'. */
- if (0 && e == e2 && e->tag == Iex_Binop
- && sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
- vex_printf("IDENT: ");
- ppIRExpr(e); vex_printf("\n");
+ /* Show cases where we've found but not folded 'op(t,t)'. Be
+ careful not to call sameIRExprs with values of different types,
+ though, else it will assert (and so it should!). We can't
+ conveniently call typeOfIRExpr on the two args without a whole
+ bunch of extra plumbing to pass in a type env, so just use a
+ hacky test to check the arguments are not anything that might
+ sameIRExprs to assert. This is only OK because this kludge is
+ only used for debug printing, not for "real" operation. For
+ "real" operation (ie, all other calls to sameIRExprs), it is
+ essential that the to args have the same type.
+
+ The "right" solution is to plumb the containing block's
+ IRTypeEnv through to here and use typeOfIRExpr to be sure. But
+ that's a bunch of extra parameter passing which will just slow
+ down the normal case, for no purpose. */
+ if (vex_control.iropt_verbosity > 0
+ && e == e2
+ && e->tag == Iex_Binop
+ && !debug_only_hack_sameIRExprs_might_assert(e->Iex.Binop.arg1,
+ e->Iex.Binop.arg2)
+ && sameIRExprs(env, e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
+ vex_printf("vex iropt: fold_Expr: no ident rule for: ");
+ ppIRExpr(e);
+ vex_printf("\n");
}
/* Show the overall results of folding. */
@@ -1785,7 +2210,7 @@
vpanic("fold_Expr: no rule for the above");
# else
if (vex_control.iropt_verbosity > 0) {
- vex_printf("vex iropt: fold_Expr: no rule for: ");
+ vex_printf("vex iropt: fold_Expr: no const rule for: ");
ppIRExpr(e);
vex_printf("\n");
}
@@ -1802,11 +2227,15 @@
switch (ex->tag) {
case Iex_RdTmp:
if (env[(Int)ex->Iex.RdTmp.tmp] != NULL) {
- return env[(Int)ex->Iex.RdTmp.tmp];
- } else {
- /* not bound in env */
- return ex;
+ IRExpr *rhs = env[(Int)ex->Iex.RdTmp.tmp];
+ if (rhs->tag == Iex_RdTmp)
+ return rhs;
+ if (rhs->tag == Iex_Const
+ && rhs->Iex.Const.con->tag != Ico_F64i)
+ return rhs;
}
+ /* not bound in env */
+ return ex;
case Iex_Const:
case Iex_Get:
@@ -1820,29 +2249,33 @@
ex->Iex.GetI.bias
);
- case Iex_Qop:
- vassert(isIRAtom(ex->Iex.Qop.arg1));
- vassert(isIRAtom(ex->Iex.Qop.arg2));
- vassert(isIRAtom(ex->Iex.Qop.arg3));
- vassert(isIRAtom(ex->Iex.Qop.arg4));
+ case Iex_Qop: {
+ IRQop* qop = ex->Iex.Qop.details;
+ vassert(isIRAtom(qop->arg1));
+ vassert(isIRAtom(qop->arg2));
+ vassert(isIRAtom(qop->arg3));
+ vassert(isIRAtom(qop->arg4));
return IRExpr_Qop(
- ex->Iex.Qop.op,
- subst_Expr(env, ex->Iex.Qop.arg1),
- subst_Expr(env, ex->Iex.Qop.arg2),
- subst_Expr(env, ex->Iex.Qop.arg3),
- subst_Expr(env, ex->Iex.Qop.arg4)
+ qop->op,
+ subst_Expr(env, qop->arg1),
+ subst_Expr(env, qop->arg2),
+ subst_Expr(env, qop->arg3),
+ subst_Expr(env, qop->arg4)
);
+ }
- case Iex_Triop:
- vassert(isIRAtom(ex->Iex.Triop.arg1));
- vassert(isIRAtom(ex->Iex.Triop.arg2));
- vassert(isIRAtom(ex->Iex.Triop.arg3));
+ case Iex_Triop: {
+ IRTriop* triop = ex->Iex.Triop.details;
+ vassert(isIRAtom(triop->arg1));
+ vassert(isIRAtom(triop->arg2));
+ vassert(isIRAtom(triop->arg3));
return IRExpr_Triop(
- ex->Iex.Triop.op,
- subst_Expr(env, ex->Iex.Triop.arg1),
- subst_Expr(env, ex->Iex.Triop.arg2),
- subst_Expr(env, ex->Iex.Triop.arg3)
+ triop->op,
+ subst_Expr(env, triop->arg1),
+ subst_Expr(env, triop->arg2),
+ subst_Expr(env, triop->arg3)
);
+ }
case Iex_Binop:
vassert(isIRAtom(ex->Iex.Binop.arg1));
@@ -1917,33 +2350,35 @@
vassert(isIRAtom(st->Ist.AbiHint.base));
vassert(isIRAtom(st->Ist.AbiHint.nia));
return IRStmt_AbiHint(
- fold_Expr(subst_Expr(env, st->Ist.AbiHint.base)),
+ fold_Expr(env, subst_Expr(env, st->Ist.AbiHint.base)),
st->Ist.AbiHint.len,
- fold_Expr(subst_Expr(env, st->Ist.AbiHint.nia))
+ fold_Expr(env, subst_Expr(env, st->Ist.AbiHint.nia))
);
case Ist_Put:
vassert(isIRAtom(st->Ist.Put.data));
return IRStmt_Put(
st->Ist.Put.offset,
- fold_Expr(subst_Expr(env, st->Ist.Put.data))
+ fold_Expr(env, subst_Expr(env, st->Ist.Put.data))
);
- case Ist_PutI:
- vassert(isIRAtom(st->Ist.PutI.ix));
- vassert(isIRAtom(st->Ist.PutI.data));
- return IRStmt_PutI(
- st->Ist.PutI.descr,
- fold_Expr(subst_Expr(env, st->Ist.PutI.ix)),
- st->Ist.PutI.bias,
- fold_Expr(subst_Expr(env, st->Ist.PutI.data))
- );
+ case Ist_PutI: {
+ IRPutI *puti, *puti2;
+ puti = st->Ist.PutI.details;
+ vassert(isIRAtom(puti->ix));
+ vassert(isIRAtom(puti->data));
+ puti2 = mkIRPutI(puti->descr,
+ fold_Expr(env, subst_Expr(env, puti->ix)),
+ puti->bias,
+ fold_Expr(env, subst_Expr(env, puti->data)));
+ return IRStmt_PutI(puti2);
+ }
case Ist_WrTmp:
/* This is the one place where an expr (st->Ist.WrTmp.data) is
allowed to be more than just a constant or a tmp. */
return IRStmt_WrTmp(
st->Ist.WrTmp.tmp,
- fold_Expr(subst_Expr(env, st->Ist.WrTmp.data))
+ fold_Expr(env, subst_Expr(env, st->Ist.WrTmp.data))
);
case Ist_Store:
@@ -1951,8 +2386,8 @@
vassert(isIRAtom(st->Ist.Store.data));
return IRStmt_Store(
st->Ist.Store.end,
- fold_Expr(subst_Expr(env, st->Ist.Store.addr)),
- fold_Expr(subst_Expr(env, st->Ist.Store.data))
+ fold_Expr(env, subst_Expr(env, st->Ist.Store.addr)),
+ fold_Expr(env, subst_Expr(env, st->Ist.Store.data))
);
case Ist_CAS: {
@@ -1965,11 +2400,13 @@
vassert(isIRAtom(cas->dataLo));
cas2 = mkIRCAS(
cas->oldHi, cas->oldLo, cas->end,
- fold_Expr(subst_Expr(env, cas->addr)),
- cas->expdHi ? fold_Expr(subst_Expr(env, cas->expdHi)) : NULL,
- fold_Expr(subst_Expr(env, cas->expdLo)),
- cas->dataHi ? fold_Expr(subst_Expr(env, cas->dataHi)) : NULL,
- fold_Expr(subst_Expr(env, cas->dataLo))
+ fold_Expr(env, subst_Expr(env, cas->addr)),
+ cas->expdHi ? fold_Expr(env, subst_Expr(env, cas->expdHi))
+ : NULL,
+ fold_Expr(env, subst_Expr(env, cas->expdLo)),
+ cas->dataHi ? fold_Expr(env, subst_Expr(env, cas->dataHi))
+ : NULL,
+ fold_Expr(env, subst_Expr(env, cas->dataLo))
);
return IRStmt_CAS(cas2);
}
@@ -1981,9 +2418,9 @@
return IRStmt_LLSC(
st->Ist.LLSC.end,
st->Ist.LLSC.result,
- fold_Expr(subst_Expr(env, st->Ist.LLSC.addr)),
+ fold_Expr(env, subst_Expr(env, st->Ist.LLSC.addr)),
st->Ist.LLSC.storedata
- ? fold_Expr(subst_Expr(env, st->Ist.LLSC.storedata))
+ ? fold_Expr(env, subst_Expr(env, st->Ist.LLSC.storedata))
: NULL
);
@@ -1996,13 +2433,13 @@
d2->args = shallowCopyIRExprVec(d2->args);
if (d2->mFx != Ifx_None) {
vassert(isIRAtom(d2->mAddr));
- d2->mAddr = fold_Expr(subst_Expr(env, d2->mAddr));
+ d2->mAddr = fold_Expr(env, subst_Expr(env, d2->mAddr));
}
vassert(isIRAtom(d2->guard));
- d2->guard = fold_Expr(subst_Expr(env, d2->guard));
+ d2->guard = fold_Expr(env, subst_Expr(env, d2->guard));
for (i = 0; d2->args[i]; i++) {
vassert(isIRAtom(d2->args[i]));
- d2->args[i] = fold_Expr(subst_Expr(env, d2->args[i]));
+ d2->args[i] = fold_Expr(env, subst_Expr(env, d2->args[i]));
}
return IRStmt_Dirty(d2);
}
@@ -2021,7 +2458,7 @@
case Ist_Exit: {
IRExpr* fcond;
vassert(isIRAtom(st->Ist.Exit.guard));
- fcond = fold_Expr(subst_Expr(env, st->Ist.Exit.guard));
+ fcond = fold_Expr(env, subst_Expr(env, st->Ist.Exit.guard));
if (fcond->tag == Iex_Const) {
/* Interesting. The condition on this exit has folded down to
a constant. */
@@ -2043,7 +2480,8 @@
vex_printf("vex iropt: IRStmt_Exit became unconditional\n");
}
}
- return IRStmt_Exit(fcond, st->Ist.Exit.jk, st->Ist.Exit.dst);
+ return IRStmt_Exit(fcond, st->Ist.Exit.jk,
+ st->Ist.Exit.dst, st->Ist.Exit.offsIP);
}
default:
@@ -2065,10 +2503,9 @@
out->tyenv = deepCopyIRTypeEnv( in->tyenv );
/* Set up the env with which travels forward. This holds a
- substitution, mapping IRTemps to atoms, that is, IRExprs which
- are either IRTemps or IRConsts. Thus, copy and constant
- propagation is done. The environment is to be applied as we
- move along. Keys are IRTemps. Values are IRExpr*s.
+ substitution, mapping IRTemps to IRExprs. The environment
+ is to be applied as we move along. Keys are IRTemps.
+ Values are IRExpr*s.
*/
for (i = 0; i < n_tmps; i++)
env[i] = NULL;
@@ -2091,34 +2528,37 @@
/* If the statement has been folded into a no-op, forget it. */
if (st2->tag == Ist_NoOp) continue;
- /* Now consider what the stmt looks like. If it's of the form
- 't = const' or 't1 = t2', add it to the running environment
- and not to the output BB. Otherwise, add it to the output
- BB. Note, we choose not to propagate const when const is an
- F64i, so that F64i literals can be CSE'd later. This helps
- x86 floating point code generation. */
+ /* If the statement assigns to an IRTemp add it to the running
+ environment. This is for the benefit of copy propagation
+ and to allow sameIRExpr look through IRTemps. */
+ if (st2->tag == Ist_WrTmp) {
+ vassert(env[(Int)(st2->Ist.WrTmp.tmp)] == NULL);
+ env[(Int)(st2->Ist.WrTmp.tmp)] = st2->Ist.WrTmp.data;
- if (st2->tag == Ist_WrTmp
- && st2->Ist.WrTmp.data->tag == Iex_Const
- && st2->Ist.WrTmp.data->Iex.Const.con->tag != Ico_F64i) {
- /* 't = const' -- add to env.
- The pair (IRTemp, IRExpr*) is added. */
- env[(Int)(st2->Ist.WrTmp.tmp)] = st2->Ist.WrTmp.data;
+ /* 't1 = t2' -- don't add to BB; will be optimized out */
+ if (st2->Ist.WrTmp.data->tag == Iex_RdTmp) continue;
+
+ /* 't = const' && 'const != F64i' -- don't add to BB
+ Note, we choose not to propagate const when const is an
+ F64i, so that F64i literals can be CSE'd later. This helps
+ x86 floating point code generation. */
+ if (st2->Ist.WrTmp.data->tag == Iex_Const
+ && st2->Ist.WrTmp.data->Iex.Const.con->tag != Ico_F64i) continue;
}
- else
- if (st2->tag == Ist_WrTmp && st2->Ist.WrTmp.data->tag == Iex_RdTmp) {
- /* 't1 = t2' -- add to env.
- The pair (IRTemp, IRExpr*) is added. */
- env[(Int)(st2->Ist.WrTmp.tmp)] = st2->Ist.WrTmp.data;
- }
- else {
- /* Not interesting, copy st2 into the output block. */
- addStmtToIRSB( out, st2 );
- }
+
+ /* Not interesting, copy st2 into the output block. */
+ addStmtToIRSB( out, st2 );
}
+#if STATS_IROPT
+ vex_printf("sameIRExpr: invoked = %u/%u equal = %u/%u max_nodes = %u\n",
+ invocation_count, recursion_count, success_count,
+ recursion_success_count, max_nodes_visited);
+#endif
+
out->next = subst_Expr( env, in->next );
out->jumpkind = in->jumpkind;
+ out->offsIP = in->offsIP;
return out;
}
@@ -2160,15 +2600,15 @@
addUses_Expr(set, e->Iex.Load.addr);
return;
case Iex_Qop:
- addUses_Expr(set, e->Iex.Qop.arg1);
- addUses_Expr(set, e->Iex.Qop.arg2);
- addUses_Expr(set, e->Iex.Qop.arg3);
- addUses_Expr(set, e->Iex.Qop.arg4);
+ addUses_Expr(set, e->Iex.Qop.details->arg1);
+ addUses_Expr(set, e->Iex.Qop.details->arg2);
+ addUses_Expr(set, e->Iex.Qop.details->arg3);
+ addUses_Expr(set, e->Iex.Qop.details->arg4);
return;
case Iex_Triop:
- addUses_Expr(set, e->Iex.Triop.arg1);
- addUses_Expr(set, e->Iex.Triop.arg2);
- addUses_Expr(set, e->Iex.Triop.arg3);
+ addUses_Expr(set, e->Iex.Triop.details->arg1);
+ addUses_Expr(set, e->Iex.Triop.details->arg2);
+ addUses_Expr(set, e->Iex.Triop.details->arg3);
return;
case Iex_Binop:
addUses_Expr(set, e->Iex.Binop.arg1);
@@ -2201,8 +2641,8 @@
addUses_Expr(set, st->Ist.AbiHint.nia);
return;
case Ist_PutI:
- addUses_Expr(set, st->Ist.PutI.ix);
- addUses_Expr(set, st->Ist.PutI.data);
+ addUses_Expr(set, st->Ist.PutI.details->ix);
+ addUses_Expr(set, st->Ist.PutI.details->data);
return;
case Ist_WrTmp:
addUses_Expr(set, st->Ist.WrTmp.data);
@@ -2344,6 +2784,8 @@
= IRExpr_Const( bb->stmts[i_unconditional_exit]->Ist.Exit.dst );
bb->jumpkind
= bb->stmts[i_unconditional_exit]->Ist.Exit.jk;
+ bb->offsIP
+ = bb->stmts[i_unconditional_exit]->Ist.Exit.offsIP;
for (i = i_unconditional_exit; i < bb->stmts_used; i++)
bb->stmts[i] = IRStmt_NoOp();
}
@@ -2526,7 +2968,72 @@
typedef
struct {
- enum { Ut, Btt, Btc, Bct, Cf64i, Mttt, GetIt } tag;
+ enum { TCc, TCt } tag;
+ union { IRTemp tmp; IRConst* con; } u;
+ }
+ TmpOrConst;
+
+static Bool eqTmpOrConst ( TmpOrConst* tc1, TmpOrConst* tc2 )
+{
+ if (tc1->tag != tc2->tag)
+ return False;
+ switch (tc1->tag) {
+ case TCc:
+ return eqIRConst(tc1->u.con, tc2->u.con);
+ case TCt:
+ return tc1->u.tmp == tc2->u.tmp;
+ default:
+ vpanic("eqTmpOrConst");
+ }
+}
+
+static Bool eqIRCallee ( IRCallee* cee1, IRCallee* cee2 )
+{
+ Bool eq = cee1->addr == cee2->addr;
+ if (eq) {
+ vassert(cee1->regparms == cee2->regparms);
+ vassert(cee1->mcx_mask == cee2->mcx_mask);
+ /* Names should be the same too, but we don't bother to
+ check. */
+ }
+ return eq;
+}
+
+/* Convert a NULL terminated IRExpr* vector to an array of
+ TmpOrConsts, and a length. */
+static void irExprVec_to_TmpOrConsts ( /*OUT*/TmpOrConst** outs,
+ /*OUT*/Int* nOuts,
+ IRExpr** ins )
+{
+ Int i, n;
+ /* We have to make two passes, one to count, one to copy. */
+ for (n = 0; ins[n]; n++)
+ ;
+ *outs = LibVEX_Alloc(n * sizeof(TmpOrConst));
+ *nOuts = n;
+ /* and now copy .. */
+ for (i = 0; i < n; i++) {
+ IRExpr* arg = ins[i];
+ TmpOrConst* dst = &(*outs)[i];
+ if (arg->tag == Iex_RdTmp) {
+ dst->tag = TCt;
+ dst->u.tmp = arg->Iex.RdTmp.tmp;
+ }
+ else if (arg->tag == Iex_Const) {
+ dst->tag = TCc;
+ dst->u.con = arg->Iex.Const.con;
+ }
+ else {
+ /* Failure of this is serious; it means that the presented arg
+ isn't an IR atom, as it should be. */
+ vpanic("irExprVec_to_TmpOrConsts");
+ }
+ }
+}
+
+typedef
+ struct {
+ enum { Ut, Btt, Btc, Bct, Cf64i, Mttt, GetIt, CCall } tag;
union {
/* unop(tmp) */
struct {
@@ -2567,13 +3074,20 @@
IRTemp ix;
Int bias;
} GetIt;
+ /* Clean helper call */
+ struct {
+ IRCallee* cee;
+ TmpOrConst* args;
+ Int nArgs;
+ IRType retty;
+ } CCall;
} u;
}
AvailExpr;
static Bool eq_AvailExpr ( AvailExpr* a1, AvailExpr* a2 )
{
- if (a1->tag != a2->tag)
+ if (LIKELY(a1->tag != a2->tag))
return False;
switch (a1->tag) {
case Ut:
@@ -2605,6 +3119,23 @@
return toBool(eqIRRegArray(a1->u.GetIt.descr, a2->u.GetIt.descr)
&& a1->u.GetIt.ix == a2->u.GetIt.ix
&& a1->u.GetIt.bias == a2->u.GetIt.bias);
+ case CCall: {
+ Int i, n;
+ Bool eq = a1->u.CCall.nArgs == a2->u.CCall.nArgs
+ && eqIRCallee(a1->u.CCall.cee, a2->u.CCall.cee);
+ if (eq) {
+ n = a1->u.CCall.nArgs;
+ for (i = 0; i < n; i++) {
+ if (!eqTmpOrConst( &a1->u.CCall.args[i],
+ &a2->u.CCall.args[i] )) {
+ eq = False;
+ break;
+ }
+ }
+ }
+ if (eq) vassert(a1->u.CCall.retty == a2->u.CCall.retty);
+ return eq;
+ }
default: vpanic("eq_AvailExpr");
}
}
@@ -2641,6 +3172,25 @@
return IRExpr_GetI(ae->u.GetIt.descr,
IRExpr_RdTmp(ae->u.GetIt.ix),
ae->u.GetIt.bias);
+ case CCall: {
+ Int i, n = ae->u.CCall.nArgs;
+ vassert(n >= 0);
+ IRExpr** vec = LibVEX_Alloc((n+1) * sizeof(IRExpr*));
+ vec[n] = NULL;
+ for (i = 0; i < n; i++) {
+ TmpOrConst* tc = &ae->u.CCall.args[i];
+ if (tc->tag == TCc) {
+ vec[i] = IRExpr_Const(tc->u.con);
+ }
+ else if (tc->tag == TCt) {
+ vec[i] = IRExpr_RdTmp(tc->u.tmp);
+ }
+ else vpanic("availExpr_to_IRExpr:CCall-arg");
+ }
+ return IRExpr_CCall(ae->u.CCall.cee,
+ ae->u.CCall.retty,
+ vec);
+ }
default:
vpanic("availExpr_to_IRExpr");
}
@@ -2684,6 +3234,16 @@
case GetIt:
ae->u.GetIt.ix = subst_AvailExpr_Temp( env, ae->u.GetIt.ix );
break;
+ case CCall: {
+ Int i, n = ae->u.CCall.nArgs;;
+ for (i = 0; i < n; i++) {
+ TmpOrConst* tc = &ae->u.CCall.args[i];
+ if (tc->tag == TCt) {
+ tc->u.tmp = subst_AvailExpr_Temp( env, tc->u.tmp );
+ }
+ }
+ break;
+ }
default:
vpanic("subst_AvailExpr");
}
@@ -2765,6 +3325,22 @@
return ae;
}
+ if (e->tag == Iex_CCall) {
+ ae = LibVEX_Alloc(sizeof(AvailExpr));
+ ae->tag = CCall;
+ /* Ok to share only the cee, since it is immutable. */
+ ae->u.CCall.cee = e->Iex.CCall.cee;
+ ae->u.CCall.retty = e->Iex.CCall.retty;
+ /* irExprVec_to_TmpOrConsts will assert if the args are
+ neither tmps nor constants, but that's ok .. that's all they
+ should be. */
+ irExprVec_to_TmpOrConsts(
+ &ae->u.CCall.args, &ae->u.CCall.nArgs,
+ e->Iex.CCall.args
+ );
+ return ae;
+ }
+
return NULL;
}
@@ -2853,13 +3429,14 @@
}
else
if (st->tag == Ist_PutI) {
+ IRPutI *puti = st->Ist.PutI.details;
if (getAliasingRelation_II(
ae->u.GetIt.descr,
IRExpr_RdTmp(ae->u.GetIt.ix),
ae->u.GetIt.bias,
- st->Ist.PutI.descr,
- st->Ist.PutI.ix,
- st->Ist.PutI.bias
+ puti->descr,
+ puti->ix,
+ puti->bias
) != NoAlias)
invalidate = True;
}
@@ -3070,22 +3647,22 @@
}
/* Perhaps st is PutI[t, con] ? */
-
+ IRPutI *puti = st->Ist.PutI.details;
if (st->tag == Ist_PutI
- && st->Ist.PutI.ix->tag == Iex_RdTmp
- && collapseChain(bb, i-1, st->Ist.PutI.ix->Iex.RdTmp.tmp,
+ && puti->ix->tag == Iex_RdTmp
+ && collapseChain(bb, i-1, puti->ix->Iex.RdTmp.tmp,
&var2, &con2)) {
if (DEBUG_IROPT) {
vex_printf("replacing2 ");
ppIRStmt(st);
vex_printf(" with ");
}
- con2 += st->Ist.PutI.bias;
+ con2 += puti->bias;
bb->stmts[i]
- = IRStmt_PutI(st->Ist.PutI.descr,
- IRExpr_RdTmp(var2),
- con2,
- st->Ist.PutI.data);
+ = IRStmt_PutI(mkIRPutI(puti->descr,
+ IRExpr_RdTmp(var2),
+ con2,
+ puti->data));
if (DEBUG_IROPT) {
ppIRStmt(bb->stmts[i]);
vex_printf("\n");
@@ -3157,12 +3734,13 @@
}
if (st->tag == Ist_PutI) {
+ IRPutI *puti = st->Ist.PutI.details;
relation = getAliasingRelation_II(
descrG, ixG, biasG,
- st->Ist.PutI.descr,
- st->Ist.PutI.ix,
- st->Ist.PutI.bias
+ puti->descr,
+ puti->ix,
+ puti->bias
);
if (relation == NoAlias) {
@@ -3179,7 +3757,7 @@
/* Otherwise, we've found what we're looking for. */
vassert(relation == ExactAlias);
- return st->Ist.PutI.data;
+ return puti->data;
} /* if (st->tag == Ist_PutI) */
@@ -3209,10 +3787,13 @@
if (s2->tag != Ist_PutI)
return False;
+ IRPutI *p1 = pi->Ist.PutI.details;
+ IRPutI *p2 = s2->Ist.PutI.details;
+
return toBool(
getAliasingRelation_II(
- pi->Ist.PutI.descr, pi->Ist.PutI.ix, pi->Ist.PutI.bias,
- s2->Ist.PutI.descr, s2->Ist.PutI.ix, s2->Ist.PutI.bias
+ p1->descr, p1->ix, p1->bias,
+ p2->descr, p2->ix, p2->bias
)
== ExactAlias
);
@@ -3232,7 +3813,10 @@
UInt minoffP, maxoffP;
vassert(pi->tag == Ist_PutI);
- getArrayBounds(pi->Ist.PutI.descr, &minoffP, &maxoffP);
+
+ IRPutI *p1 = pi->Ist.PutI.details;
+
+ getArrayBounds(p1->descr, &minoffP, &maxoffP);
switch (s2->tag) {
case Ist_NoOp:
@@ -3262,28 +3846,30 @@
vassert(isIRAtom(s2->Ist.Put.data));
relation
= getAliasingRelation_IC(
- pi->Ist.PutI.descr, pi->Ist.PutI.ix,
+ p1->descr, p1->ix,
s2->Ist.Put.offset,
typeOfIRExpr(tyenv,s2->Ist.Put.data)
);
goto have_relation;
- case Ist_PutI:
- vassert(isIRAtom(s2->Ist.PutI.ix));
- vassert(isIRAtom(s2->Ist.PutI.data));
+ case Ist_PutI: {
+ IRPutI *p2 = s2->Ist.PutI.details;
+
+ vassert(isIRAtom(p2->ix));
+ vassert(isIRAtom(p2->data));
relation
= getAliasingRelation_II(
- pi->Ist.PutI.descr, pi->Ist.PutI.ix, pi->Ist.PutI.bias,
- s2->Ist.PutI.descr, s2->Ist.PutI.ix, s2->Ist.PutI.bias
+ p1->descr, p1->ix, p1->bias,
+ p2->descr, p2->ix, p2->bias
);
goto have_relation;
+ }
case Ist_WrTmp:
if (s2->Ist.WrTmp.data->tag == Iex_GetI) {
relation
= getAliasingRelation_II(
- pi->Ist.PutI.descr, pi->Ist.PutI.ix,
- pi->Ist.PutI.bias,
+ p1->descr, p1->ix, p1->bias,
s2->Ist.WrTmp.data->Iex.GetI.descr,
s2->Ist.WrTmp.data->Iex.GetI.ix,
s2->Ist.WrTmp.data->Iex.GetI.bias
@@ -3293,7 +3879,7 @@
if (s2->Ist.WrTmp.data->tag == Iex_Get) {
relation
= getAliasingRelation_IC(
- pi->Ist.PutI.descr, pi->Ist.PutI.ix,
+ p1->descr, p1->ix,
s2->Ist.WrTmp.data->Iex.Get.offset,
s2->Ist.WrTmp.data->Iex.Get.ty
);
@@ -3372,6 +3958,10 @@
Bool delete;
IRStmt *st, *stj;
+ vassert
+ (vex_control.iropt_register_updates == VexRegUpdUnwindregsAtMemAccess
+ || vex_control.iropt_register_updates == VexRegUpdAllregsAtMemAccess);
+
for (i = 0; i < bb->stmts_used; i++) {
st = bb->stmts[i];
if (st->tag != Ist_PutI)
@@ -3444,15 +4034,15 @@
deltaIRExpr(e->Iex.GetI.ix, delta);
break;
case Iex_Qop:
- deltaIRExpr(e->Iex.Qop.arg1, delta);
- deltaIRExpr(e->Iex.Qop.arg2, delta);
- deltaIRExpr(e->Iex.Qop.arg3, delta);
- deltaIRExpr(e->Iex.Qop.arg4, delta);
+ deltaIRExpr(e->Iex.Qop.details->arg1, delta);
+ deltaIRExpr(e->Iex.Qop.details->arg2, delta);
+ deltaIRExpr(e->Iex.Qop.details->arg3, delta);
+ deltaIRExpr(e->Iex.Qop.details->arg4, delta);
break;
case Iex_Triop:
- deltaIRExpr(e->Iex.Triop.arg1, delta);
- deltaIRExpr(e->Iex.Triop.arg2, delta);
- deltaIRExpr(e->Iex.Triop.arg3, delta);
+ deltaIRExpr(e->Iex.Triop.details->arg1, delta);
+ deltaIRExpr(e->Iex.Triop.details->arg2, delta);
+ deltaIRExpr(e->Iex.Triop.details->arg3, delta);
break;
case Iex_Binop:
deltaIRExpr(e->Iex.Binop.arg1, delta);
@@ -3499,8 +4089,8 @@
deltaIRExpr(st->Ist.Put.data, delta);
break;
case Ist_PutI:
- deltaIRExpr(st->Ist.PutI.ix, delta);
- deltaIRExpr(st->Ist.PutI.data, delta);
+ deltaIRExpr(st->Ist.PutI.details->ix, delta);
+ deltaIRExpr(st->Ist.PutI.details->data, delta);
break;
case Ist_WrTmp:
st->Ist.WrTmp.tmp += delta;
@@ -3839,15 +4429,15 @@
setHints_Expr(doesLoad, doesGet, e->Iex.Mux0X.exprX);
return;
case Iex_Qop:
- setHints_Expr(doesLoad, doesGet, e->Iex.Qop.arg1);
- setHints_Expr(doesLoad, doesGet, e->Iex.Qop.arg2);
- setHints_Expr(doesLoad, doesGet, e->Iex.Qop.arg3);
- setHints_Expr(doesLoad, doesGet, e->Iex.Qop.arg4);
+ setHints_Expr(doesLoad, doesGet, e->Iex.Qop.details->arg1);
+ setHints_Expr(doesLoad, doesGet, e->Iex.Qop.details->arg2);
+ setHints_Expr(doesLoad, doesGet, e->Iex.Qop.details->arg3);
+ setHints_Expr(doesLoad, doesGet, e->Iex.Qop.details->arg4);
return;
case Iex_Triop:
- setHints_Expr(doesLoad, doesGet, e->Iex.Triop.arg1);
- setHints_Expr(doesLoad, doesGet, e->Iex.Triop.arg2);
- setHints_Expr(doesLoad, doesGet, e->Iex.Triop.arg3);
+ setHints_Expr(doesLoad, doesGet, e->Iex.Triop.details->arg1);
+ setHints_Expr(doesLoad, doesGet, e->Iex.Triop.details->arg2);
+ setHints_Expr(doesLoad, doesGet, e->Iex.Triop.details->arg3);
return;
case Iex_Binop:
setHints_Expr(doesLoad, doesGet, e->Iex.Binop.arg1);
@@ -3912,16 +4502,16 @@
return;
case Iex_Qop:
- aoccCount_Expr(uses, e->Iex.Qop.arg1);
- aoccCount_Expr(uses, e->Iex.Qop.arg2);
- aoccCount_Expr(uses, e->Iex.Qop.arg3);
- aoccCount_Expr(uses, e->Iex.Qop.arg4);
+ aoccCount_Expr(uses, e->Iex.Qop.details->arg1);
+ aoccCount_Expr(uses, e->Iex.Qop.details->arg2);
+ aoccCount_Expr(uses, e->Iex.Qop.details->arg3);
+ aoccCount_Expr(uses, e->Iex.Qop.details->arg4);
return;
case Iex_Triop:
- aoccCount_Expr(uses, e->Iex.Triop.arg1);
- aoccCount_Expr(uses, e->Iex.Triop.arg2);
- aoccCount_Expr(uses, e->Iex.Triop.arg3);
+ aoccCount_Expr(uses, e->Iex.Triop.details->arg1);
+ aoccCount_Expr(uses, e->Iex.Triop.details->arg2);
+ aoccCount_Expr(uses, e->Iex.Triop.details->arg3);
return;
case Iex_Binop:
@@ -3978,8 +4568,8 @@
aoccCount_Expr(uses, st->Ist.Put.data);
return;
case Ist_PutI:
- aoccCount_Expr(uses, st->Ist.PutI.ix);
- aoccCount_Expr(uses, st->Ist.PutI.data);
+ aoccCount_Expr(uses, st->Ist.PutI.details->ix);
+ aoccCount_Expr(uses, st->Ist.PutI.details->data);
return;
case Ist_Store:
aoccCount_Expr(uses, st->Ist.Store.addr);
@@ -4157,6 +4747,33 @@
/* 32Uto64( 16Uto32( x )) --> 16Uto64(x) */
if (is_Unop(aa, Iop_16Uto32))
return IRExpr_Unop(Iop_16Uto64, aa->Iex.Unop.arg);
+ /* 32Uto64(64to32( Shr64( 32Uto64(64to32(x)), sh ))
+ --> Shr64( 32Uto64(64to32(x)), sh )) */
+ if (is_Unop(aa, Iop_64to32)
+ && is_Binop(aa->Iex.Unop.arg, Iop_Shr64)
+ && is_Unop(aa->Iex.Unop.arg->Iex.Binop.arg1, Iop_32Uto64)
+ && is_Unop(aa->Iex.Unop.arg->Iex.Binop.arg1->Iex.Unop.arg,
+ Iop_64to32)) {
+ return aa->Iex.Unop.arg;
+ }
+ /* 32Uto64(64to32( Shl64( 32Uto64(64to32(x)), sh ))
+ --> 32Uto64(64to32( Shl64( x, sh )) */
+ if (is_Unop(aa, Iop_64to32)
+ && is_Binop(aa->Iex.Unop.arg, Iop_Shl64)
+ && is_Unop(aa->Iex.Unop.arg->Iex.Binop.arg1, Iop_32Uto64)
+ && is_Unop(aa->Iex.Unop.arg->Iex.Binop.arg1->Iex.Unop.arg,
+ Iop_64to32)) {
+ return
+ IRExpr_Unop(
+ Iop_32Uto64,
+ IRExpr_Unop(
+ Iop_64to32,
+ IRExpr_Binop(
+ Iop_Shl64,
+ aa->Iex.Unop.arg->Iex.Binop.arg1->Iex.Unop.arg->Iex.Unop.arg,
+ aa->Iex.Unop.arg->Iex.Binop.arg2
+ )));
+ }
break;
case Iop_1Sto32:
@@ -4172,7 +4789,6 @@
}
break;
-
default:
break;
}
@@ -4208,18 +4824,18 @@
);
case Iex_Qop:
return IRExpr_Qop(
- e->Iex.Qop.op,
- atbSubst_Expr(env, e->Iex.Qop.arg1),
- atbSubst_Expr(env, e->Iex.Qop.arg2),
- atbSubst_Expr(env, e->Iex.Qop.arg3),
- atbSubst_Expr(env, e->Iex.Qop.arg4)
+ e->Iex.Qop.details->op,
+ atbSubst_Expr(env, e->Iex.Qop.details->arg1),
+ atbSubst_Expr(env, e->Iex.Qop.details->arg2),
+ atbSubst_Expr(env, e->Iex.Qop.details->arg3),
+ atbSubst_Expr(env, e->Iex.Qop.details->arg4)
);
case Iex_Triop:
return IRExpr_Triop(
- e->Iex.Triop.op,
- atbSubst_Expr(env, e->Iex.Triop.arg1),
- atbSubst_Expr(env, e->Iex.Triop.arg2),
- atbSubst_Expr(env, e->Iex.Triop.arg3)
+ e->Iex.Triop.details->op,
+ atbSubst_Expr(env, e->Iex.Triop.details->arg1),
+ atbSubst_Expr(env, e->Iex.Triop.details->arg2),
+ atbSubst_Expr(env, e->Iex.Triop.details->arg3)
);
case Iex_Binop:
return fold_IRExpr_Binop(
@@ -4260,6 +4876,8 @@
Int i;
IRDirty *d, *d2;
IRCAS *cas, *cas2;
+ IRPutI *puti, *puti2;
+
switch (st->tag) {
case Ist_AbiHint:
return IRStmt_AbiHint(
@@ -4284,18 +4902,19 @@
atbSubst_Expr(env, st->Ist.Put.data)
);
case Ist_PutI:
- return IRStmt_PutI(
- st->Ist.PutI.descr,
- atbSubst_Expr(env, st->Ist.PutI.ix),
- st->Ist.PutI.bias,
- atbSubst_Expr(env, st->Ist.PutI.data)
- );
+ puti = st->Ist.PutI.details;
+ puti2 = mkIRPutI(puti->descr,
+ atbSubst_Expr(env, puti->ix),
+ puti->bias,
+ atbSubst_Expr(env, puti->data));
+ return IRStmt_PutI(puti2);
case Ist_Exit:
return IRStmt_Exit(
atbSubst_Expr(env, st->Ist.Exit.guard),
st->Ist.Exit.jk,
- st->Ist.Exit.dst
+ st->Ist.Exit.dst,
+ st->Ist.Exit.offsIP
);
case Ist_IMark:
return IRStmt_IMark(st->Ist.IMark.addr,
@@ -4340,7 +4959,7 @@
}
}
-/* notstatic */ void ado_treebuild_BB ( IRSB* bb )
+/* notstatic */ Addr64 ado_treebuild_BB ( IRSB* bb )
{
Int i, j, k, m;
Bool stmtPuts, stmtStores, invalidateMe;
@@ -4348,19 +4967,37 @@
IRStmt* st2;
ATmpInfo env[A_NENV];
+ Bool max_ga_known = False;
+ Addr64 max_ga = 0;
+
Int n_tmps = bb->tyenv->types_used;
UShort* uses = LibVEX_Alloc(n_tmps * sizeof(UShort));
/* Phase 1. Scan forwards in bb, counting use occurrences of each
- temp. Also count occurrences in the bb->next field. */
+ temp. Also count occurrences in the bb->next field. Take the
+ opportunity to also find the maximum guest address in the block,
+ since that will be needed later for deciding when we can safely
+ elide event checks. */
for (i = 0; i < n_tmps; i++)
uses[i] = 0;
for (i = 0; i < bb->stmts_used; i++) {
st = bb->stmts[i];
- if (st->tag == Ist_NoOp)
- continue;
+ switch (st->tag) {
+ case Ist_NoOp:
+ continue;
+ case Ist_IMark: {
+ Int len = st->Ist.IMark.len;
+ Addr64 mga = st->Ist.IMark.addr + (len < 1 ? 1 : len) - 1;
+ max_ga_known = True;
+ if (mga > max_ga)
+ max_ga = mga;
+ break;
+ }
+ default:
+ break;
+ }
aoccCount_Stmt( uses, st );
}
aoccCount_Expr(uses, bb->next );
@@ -4471,7 +5108,8 @@
stmtStores
= toBool( st->tag == Ist_Store
|| st->tag == Ist_Dirty
- || st->tag == Ist_LLSC );
+ || st->tag == Ist_LLSC
+ || st->tag == Ist_CAS );
for (k = A_NENV-1; k >= 0; k--) {
if (env[k].bindee == NULL)
@@ -4532,6 +5170,8 @@
by definition dead? */
bb->next = atbSubst_Expr(env, bb->next);
bb->stmts_used = j;
+
+ return max_ga_known ? max_ga : ~(Addr64)0;
}
@@ -4561,7 +5201,9 @@
ppIRSB(bb);
}
- redundant_put_removal_BB ( bb, preciseMemExnsFn );
+ if (vex_control.iropt_register_updates != VexRegUpdAllregsAtEachInsn) {
+ redundant_put_removal_BB ( bb, preciseMemExnsFn );
+ }
if (iropt_verbose) {
vex_printf("\n========= REDUNDANT PUT\n\n" );
ppIRSB(bb);
@@ -4599,7 +5241,9 @@
(void)do_cse_BB( bb );
collapse_AddSub_chains_BB( bb );
do_redundant_GetI_elimination( bb );
- do_redundant_PutI_elimination( bb );
+ if (vex_control.iropt_register_updates != VexRegUpdAllregsAtEachInsn) {
+ do_redundant_PutI_elimination( bb );
+ }
do_deadcode_BB( bb );
return bb;
}
@@ -4640,7 +5284,11 @@
case Ity_I1: case Ity_I8: case Ity_I16:
case Ity_I32: case Ity_I64: case Ity_I128:
break;
- case Ity_F32: case Ity_F64: case Ity_F128: case Ity_V128:
+ case Ity_F32: case Ity_F64: case Ity_F128:
+ case Ity_V128: case Ity_V256:
+ *hasVorFtemps = True;
+ break;
+ case Ity_D32: case Ity_D64: case Ity_D128:
*hasVorFtemps = True;
break;
default:
@@ -4744,7 +5392,9 @@
work extra hard to get rid of it. */
bb = cprop_BB(bb);
bb = spec_helpers_BB ( bb, specHelper );
- redundant_put_removal_BB ( bb, preciseMemExnsFn );
+ if (vex_control.iropt_register_updates != VexRegUpdAllregsAtEachInsn) {
+ redundant_put_removal_BB ( bb, preciseMemExnsFn );
+ }
do_cse_BB( bb );
do_deadcode_BB( bb );
}
diff --git a/main/VEX/priv/ir_opt.h b/main/VEX/priv/ir_opt.h
index 9390a1c..c215fa2 100644
--- a/main/VEX/priv/ir_opt.h
+++ b/main/VEX/priv/ir_opt.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -60,9 +60,11 @@
void do_deadcode_BB ( IRSB* bb );
/* The tree-builder. Make (approximately) maximal safe trees. bb is
- destructively modified. */
+ destructively modified. Returns (unrelatedly, but useful later on)
+ the guest address of the highest addressed byte from any insn in
+ this block, or Addr64_MAX if unknown (can that ever happen?) */
extern
-void ado_treebuild_BB ( IRSB* bb );
+Addr64 ado_treebuild_BB ( IRSB* bb );
#endif /* ndef __VEX_IR_OPT_H */
diff --git a/main/VEX/priv/main_globals.c b/main/VEX/priv/main_globals.c
index 8da96be..8e170b8 100644
--- a/main/VEX/priv/main_globals.c
+++ b/main/VEX/priv/main_globals.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/main/VEX/priv/main_globals.h b/main/VEX/priv/main_globals.h
index 6404526..127d6dd 100644
--- a/main/VEX/priv/main_globals.h
+++ b/main/VEX/priv/main_globals.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/main/VEX/priv/main_main.c b/main/VEX/priv/main_main.c
index 5b818ae..b093292 100644
--- a/main/VEX/priv/main_main.c
+++ b/main/VEX/priv/main_main.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -41,6 +41,7 @@
#include "libvex_guest_ppc32.h"
#include "libvex_guest_ppc64.h"
#include "libvex_guest_s390x.h"
+#include "libvex_guest_mips32.h"
#include "main_globals.h"
#include "main_util.h"
@@ -52,6 +53,7 @@
#include "host_ppc_defs.h"
#include "host_arm_defs.h"
#include "host_s390_defs.h"
+#include "host_mips_defs.h"
#include "guest_generic_bb_to_IR.h"
#include "guest_x86_defs.h"
@@ -59,6 +61,7 @@
#include "guest_arm_defs.h"
#include "guest_ppc_defs.h"
#include "guest_s390_defs.h"
+#include "guest_mips_defs.h"
#include "host_generic_simd128.h"
@@ -79,7 +82,7 @@
{
vcon->iropt_verbosity = 0;
vcon->iropt_level = 2;
- vcon->iropt_precise_memory_exns = False;
+ vcon->iropt_register_updates = VexRegUpdUnwindregsAtMemAccess;
vcon->iropt_unroll_thresh = 120;
vcon->guest_max_insns = 60;
vcon->guest_chase_thresh = 10;
@@ -147,6 +150,7 @@
vassert(8 == sizeof(Addr64));
vassert(16 == sizeof(U128));
vassert(16 == sizeof(V128));
+ vassert(32 == sizeof(U256));
vassert(sizeof(void*) == 4 || sizeof(void*) == 8);
vassert(sizeof(void*) == sizeof(int*));
@@ -155,6 +159,17 @@
vassert(VEX_HOST_WORDSIZE == sizeof(void*));
vassert(VEX_HOST_WORDSIZE == sizeof(HWord));
+ /* These take a lot of space, so make sure we don't have
+ any unnoticed size regressions. */
+ if (VEX_HOST_WORDSIZE == 4) {
+ vassert(sizeof(IRExpr) == 16);
+ vassert(sizeof(IRStmt) == 20 /* x86 */
+ || sizeof(IRStmt) == 24 /* arm */);
+ } else {
+ vassert(sizeof(IRExpr) == 32);
+ vassert(sizeof(IRStmt) == 32);
+ }
+
/* Really start up .. */
vex_debuglevel = debuglevel;
vex_valgrind_support = valgrind_support;
@@ -183,9 +198,11 @@
HInstr* (*directReload) ( HInstr*, HReg, Short );
void (*ppInstr) ( HInstr*, Bool );
void (*ppReg) ( HReg );
- HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*,
- VexAbiInfo* );
- Int (*emit) ( UChar*, Int, HInstr*, Bool, void*, void* );
+ HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*, VexAbiInfo*,
+ Int, Int, Bool, Bool, Addr64 );
+ Int (*emit) ( /*MB_MOD*/Bool*,
+ UChar*, Int, HInstr*, Bool,
+ void*, void*, void*, void* );
IRExpr* (*specHelper) ( HChar*, IRExpr**, IRStmt**, Int );
Bool (*preciseMemExnsFn) ( Int, Int );
@@ -197,11 +214,13 @@
HInstrArray* vcode;
HInstrArray* rcode;
Int i, j, k, out_used, guest_sizeB;
- Int offB_TISTART, offB_TILEN;
- UChar insn_bytes[48];
+ Int offB_TISTART, offB_TILEN, offB_GUEST_IP, szB_GUEST_IP;
+ Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR;
+ UChar insn_bytes[64];
IRType guest_word_type;
IRType host_word_type;
- Bool mode64;
+ Bool mode64, chainingAllowed;
+ Addr64 max_ga;
guest_layout = NULL;
available_real_regs = NULL;
@@ -223,12 +242,27 @@
host_word_type = Ity_INVALID;
offB_TISTART = 0;
offB_TILEN = 0;
+ offB_GUEST_IP = 0;
+ szB_GUEST_IP = 0;
+ offB_HOST_EvC_COUNTER = 0;
+ offB_HOST_EvC_FAILADDR = 0;
mode64 = False;
+ chainingAllowed = False;
vex_traceflags = vta->traceflags;
vassert(vex_initdone);
- vassert(vta->needs_self_check != NULL);
+ vassert(vta->needs_self_check != NULL);
+ vassert(vta->disp_cp_xassisted != NULL);
+ /* Both the chainers and the indir are either NULL or non-NULL. */
+ if (vta->disp_cp_chain_me_to_slowEP != NULL) {
+ vassert(vta->disp_cp_chain_me_to_fastEP != NULL);
+ vassert(vta->disp_cp_xindir != NULL);
+ chainingAllowed = True;
+ } else {
+ vassert(vta->disp_cp_chain_me_to_fastEP == NULL);
+ vassert(vta->disp_cp_xindir == NULL);
+ }
vexSetAllocModeTEMP_and_clear();
vexAllocSanityCheck();
@@ -254,14 +288,12 @@
ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr;
ppReg = (void(*)(HReg)) ppHRegX86;
iselSB = iselSB_X86;
- emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*,void*))
+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,
+ void*,void*,void*,void*))
emit_X86Instr;
host_is_bigendian = False;
host_word_type = Ity_I32;
vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps));
- /* jump-to-dispatcher scheme */
- vassert(vta->dispatch_unassisted != NULL);
- vassert(vta->dispatch_assisted != NULL);
break;
case VexArchAMD64:
@@ -279,14 +311,12 @@
ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr;
ppReg = (void(*)(HReg)) ppHRegAMD64;
iselSB = iselSB_AMD64;
- emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*,void*))
+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,
+ void*,void*,void*,void*))
emit_AMD64Instr;
host_is_bigendian = False;
host_word_type = Ity_I64;
vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_host.hwcaps));
- /* jump-to-dispatcher scheme */
- vassert(vta->dispatch_unassisted != NULL);
- vassert(vta->dispatch_assisted != NULL);
break;
case VexArchPPC32:
@@ -301,14 +331,12 @@
ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr;
ppReg = (void(*)(HReg)) ppHRegPPC;
iselSB = iselSB_PPC;
- emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*,void*))
+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,
+ void*,void*,void*,void*))
emit_PPCInstr;
host_is_bigendian = True;
host_word_type = Ity_I32;
vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_host.hwcaps));
- /* return-to-dispatcher scheme */
- vassert(vta->dispatch_unassisted == NULL);
- vassert(vta->dispatch_assisted == NULL);
break;
case VexArchPPC64:
@@ -323,14 +351,12 @@
ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr;
ppReg = (void(*)(HReg)) ppHRegPPC;
iselSB = iselSB_PPC;
- emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*,void*))
+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,
+ void*,void*,void*,void*))
emit_PPCInstr;
host_is_bigendian = True;
host_word_type = Ity_I64;
vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps));
- /* return-to-dispatcher scheme */
- vassert(vta->dispatch_unassisted == NULL);
- vassert(vta->dispatch_assisted == NULL);
break;
case VexArchS390X:
@@ -345,14 +371,11 @@
ppInstr = (void(*)(HInstr*, Bool)) ppS390Instr;
ppReg = (void(*)(HReg)) ppHRegS390;
iselSB = iselSB_S390;
- emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*,void*))
- emit_S390Instr;
+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,
+ void*,void*,void*,void*)) emit_S390Instr;
host_is_bigendian = True;
host_word_type = Ity_I64;
vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_host.hwcaps));
- /* return-to-dispatcher scheme */
- vassert(vta->dispatch_unassisted == NULL);
- vassert(vta->dispatch_assisted == NULL);
break;
case VexArchARM:
@@ -367,14 +390,36 @@
ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr;
ppReg = (void(*)(HReg)) ppHRegARM;
iselSB = iselSB_ARM;
- emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*,void*))
+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,
+ void*,void*,void*,void*))
emit_ARMInstr;
host_is_bigendian = False;
host_word_type = Ity_I32;
vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps));
- vassert(vta->dispatch_unassisted == NULL);
- vassert(vta->dispatch_assisted == NULL);
- /* return-to-dispatcher scheme */
+ break;
+
+ case VexArchMIPS32:
+ mode64 = False;
+ getAllocableRegs_MIPS ( &n_available_real_regs,
+ &available_real_regs, mode64 );
+ isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_MIPSInstr;
+ getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_MIPSInstr;
+ mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_MIPSInstr;
+ genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_MIPS;
+ genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_MIPS;
+ ppInstr = (void(*)(HInstr*, Bool)) ppMIPSInstr;
+ ppReg = (void(*)(HReg)) ppHRegMIPS;
+ iselSB = iselSB_MIPS;
+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,
+ void*,void*,void*,void*))
+ emit_MIPSInstr;
+#if defined(VKI_LITTLE_ENDIAN)
+ host_is_bigendian = False;
+#elif defined(VKI_BIG_ENDIAN)
+ host_is_bigendian = True;
+#endif
+ host_word_type = Ity_I32;
+ vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_host.hwcaps));
break;
default:
@@ -385,14 +430,18 @@
switch (vta->arch_guest) {
case VexArchX86:
- preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns;
- disInstrFn = disInstr_X86;
- specHelper = guest_x86_spechelper;
- guest_sizeB = sizeof(VexGuestX86State);
- guest_word_type = Ity_I32;
- guest_layout = &x86guest_layout;
- offB_TISTART = offsetof(VexGuestX86State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestX86State,guest_TILEN);
+ preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns;
+ disInstrFn = disInstr_X86;
+ specHelper = guest_x86_spechelper;
+ guest_sizeB = sizeof(VexGuestX86State);
+ guest_word_type = Ity_I32;
+ guest_layout = &x86guest_layout;
+ offB_TISTART = offsetof(VexGuestX86State,guest_TISTART);
+ offB_TILEN = offsetof(VexGuestX86State,guest_TILEN);
+ offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP);
+ szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP );
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestX86State) % 16);
vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4);
@@ -401,14 +450,18 @@
break;
case VexArchAMD64:
- preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns;
- disInstrFn = disInstr_AMD64;
- specHelper = guest_amd64_spechelper;
- guest_sizeB = sizeof(VexGuestAMD64State);
- guest_word_type = Ity_I64;
- guest_layout = &amd64guest_layout;
- offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN);
+ preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns;
+ disInstrFn = disInstr_AMD64;
+ specHelper = guest_amd64_spechelper;
+ guest_sizeB = sizeof(VexGuestAMD64State);
+ guest_word_type = Ity_I64;
+ guest_layout = &amd64guest_layout;
+ offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART);
+ offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN);
+ offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP);
+ szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP );
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestAMD64State) % 16);
vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8);
@@ -417,14 +470,18 @@
break;
case VexArchPPC32:
- preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns;
- disInstrFn = disInstr_PPC;
- specHelper = guest_ppc32_spechelper;
- guest_sizeB = sizeof(VexGuestPPC32State);
- guest_word_type = Ity_I32;
- guest_layout = &ppc32Guest_layout;
- offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN);
+ preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns;
+ disInstrFn = disInstr_PPC;
+ specHelper = guest_ppc32_spechelper;
+ guest_sizeB = sizeof(VexGuestPPC32State);
+ guest_word_type = Ity_I32;
+ guest_layout = &ppc32Guest_layout;
+ offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART);
+ offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN);
+ offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA);
+ szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA );
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestPPC32State) % 16);
vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4);
@@ -433,14 +490,18 @@
break;
case VexArchPPC64:
- preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns;
- disInstrFn = disInstr_PPC;
- specHelper = guest_ppc64_spechelper;
- guest_sizeB = sizeof(VexGuestPPC64State);
- guest_word_type = Ity_I64;
- guest_layout = &ppc64Guest_layout;
- offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART);
- offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN);
+ preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns;
+ disInstrFn = disInstr_PPC;
+ specHelper = guest_ppc64_spechelper;
+ guest_sizeB = sizeof(VexGuestPPC64State);
+ guest_word_type = Ity_I64;
+ guest_layout = &ppc64Guest_layout;
+ offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART);
+ offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN);
+ offB_GUEST_IP = offsetof(VexGuestPPC64State,guest_CIA);
+ szB_GUEST_IP = sizeof( ((VexGuestPPC64State*)0)->guest_CIA );
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestPPC64State) % 16);
vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8);
@@ -458,6 +519,10 @@
guest_layout = &s390xGuest_layout;
offB_TISTART = offsetof(VexGuestS390XState,guest_TISTART);
offB_TILEN = offsetof(VexGuestS390XState,guest_TILEN);
+ offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA);
+ szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA);
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestS390XState) % 16);
vassert(sizeof( ((VexGuestS390XState*)0)->guest_TISTART ) == 8);
@@ -466,14 +531,18 @@
break;
case VexArchARM:
- preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns;
- disInstrFn = disInstr_ARM;
- specHelper = guest_arm_spechelper;
- guest_sizeB = sizeof(VexGuestARMState);
- guest_word_type = Ity_I32;
- guest_layout = &armGuest_layout;
- offB_TISTART = offsetof(VexGuestARMState,guest_TISTART);
- offB_TILEN = offsetof(VexGuestARMState,guest_TILEN);
+ preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns;
+ disInstrFn = disInstr_ARM;
+ specHelper = guest_arm_spechelper;
+ guest_sizeB = sizeof(VexGuestARMState);
+ guest_word_type = Ity_I32;
+ guest_layout = &armGuest_layout;
+ offB_TISTART = offsetof(VexGuestARMState,guest_TISTART);
+ offB_TILEN = offsetof(VexGuestARMState,guest_TILEN);
+ offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T);
+ szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T );
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR);
vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps));
vassert(0 == sizeof(VexGuestARMState) % 16);
vassert(sizeof( ((VexGuestARMState*)0)->guest_TISTART) == 4);
@@ -481,14 +550,36 @@
vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4);
break;
+ case VexArchMIPS32:
+ preciseMemExnsFn = guest_mips32_state_requires_precise_mem_exns;
+ disInstrFn = disInstr_MIPS;
+ specHelper = guest_mips32_spechelper;
+ guest_sizeB = sizeof(VexGuestMIPS32State);
+ guest_word_type = Ity_I32;
+ guest_layout = &mips32Guest_layout;
+ offB_TISTART = offsetof(VexGuestMIPS32State,guest_TISTART);
+ offB_TILEN = offsetof(VexGuestMIPS32State,guest_TILEN);
+ offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC);
+ szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC );
+ offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER);
+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR);
+ vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_guest.hwcaps));
+ vassert(0 == sizeof(VexGuestMIPS32State) % 16);
+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TISTART) == 4);
+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TILEN ) == 4);
+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4);
+ break;
+
default:
vpanic("LibVEX_Translate: unsupported guest insn set");
}
/* Set up result struct. */
VexTranslateResult res;
- res.status = VexTransOK;
- res.n_sc_extents = 0;
+ res.status = VexTransOK;
+ res.n_sc_extents = 0;
+ res.offs_profInc = -1;
+ res.n_guest_instrs = 0;
/* yet more sanity checks ... */
if (vta->arch_guest == vta->arch_host) {
@@ -507,6 +598,7 @@
irsb = bb_to_IR ( vta->guest_extents,
&res.n_sc_extents,
+ &res.n_guest_instrs,
vta->callback_opaque,
disInstrFn,
vta->guest_bytes,
@@ -520,7 +612,9 @@
vta->needs_self_check,
vta->preamble_function,
offB_TISTART,
- offB_TILEN );
+ offB_TILEN,
+ offB_GUEST_IP,
+ szB_GUEST_IP );
vexAllocSanityCheck();
@@ -627,7 +721,7 @@
/* Turn it into virtual-registerised code. Build trees -- this
also throws away any dead bindings. */
- ado_treebuild_BB( irsb );
+ max_ga = ado_treebuild_BB( irsb );
if (vta->finaltidy) {
irsb = vta->finaltidy(irsb);
@@ -655,8 +749,19 @@
" Instruction selection "
"------------------------\n");
- vcode = iselSB ( irsb, vta->arch_host, &vta->archinfo_host,
- &vta->abiinfo_both );
+ /* No guest has its IP field at offset zero. If this fails it
+ means some transformation pass somewhere failed to update/copy
+ irsb->offsIP properly. */
+ vassert(irsb->offsIP >= 16);
+
+ vcode = iselSB ( irsb, vta->arch_host,
+ &vta->archinfo_host,
+ &vta->abiinfo_both,
+ offB_HOST_EvC_COUNTER,
+ offB_HOST_EvC_FAILADDR,
+ chainingAllowed,
+ vta->addProfInc,
+ max_ga );
vexAllocSanityCheck();
@@ -710,13 +815,19 @@
out_used = 0; /* tracks along the host_bytes array */
for (i = 0; i < rcode->arr_used; i++) {
- if (vex_traceflags & VEX_TRACE_ASM) {
- ppInstr(rcode->arr[i], mode64);
+ HInstr* hi = rcode->arr[i];
+ Bool hi_isProfInc = False;
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
+ ppInstr(hi, mode64);
vex_printf("\n");
}
- j = (*emit)( insn_bytes, sizeof insn_bytes, rcode->arr[i], mode64,
- vta->dispatch_unassisted, vta->dispatch_assisted );
- if (vex_traceflags & VEX_TRACE_ASM) {
+ j = emit( &hi_isProfInc,
+ insn_bytes, sizeof insn_bytes, hi, mode64,
+ vta->disp_cp_chain_me_to_slowEP,
+ vta->disp_cp_chain_me_to_fastEP,
+ vta->disp_cp_xindir,
+ vta->disp_cp_xassisted );
+ if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
for (k = 0; k < j; k++)
if (insn_bytes[k] < 16)
vex_printf("0%x ", (UInt)insn_bytes[k]);
@@ -724,15 +835,23 @@
vex_printf("%x ", (UInt)insn_bytes[k]);
vex_printf("\n\n");
}
- if (out_used + j > vta->host_bytes_size) {
+ if (UNLIKELY(out_used + j > vta->host_bytes_size)) {
vexSetAllocModeTEMP_and_clear();
vex_traceflags = 0;
res.status = VexTransOutputFull;
return res;
}
- for (k = 0; k < j; k++) {
- vta->host_bytes[out_used] = insn_bytes[k];
- out_used++;
+ if (UNLIKELY(hi_isProfInc)) {
+ vassert(vta->addProfInc); /* else where did it come from? */
+ vassert(res.offs_profInc == -1); /* there can be only one (tm) */
+ vassert(out_used >= 0);
+ res.offs_profInc = out_used;
+ }
+ { UChar* dst = &vta->host_bytes[out_used];
+ for (k = 0; k < j; k++) {
+ dst[k] = insn_bytes[k];
+ }
+ out_used += j;
}
vassert(out_used <= vta->host_bytes_size);
}
@@ -748,6 +867,140 @@
}
+/* --------- Chain/Unchain XDirects. --------- */
+
+VexInvalRange LibVEX_Chain ( VexArch arch_host,
+ void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to )
+{
+ VexInvalRange (*chainXDirect)(void*, void*, void*) = NULL;
+ switch (arch_host) {
+ case VexArchX86:
+ chainXDirect = chainXDirect_X86; break;
+ case VexArchAMD64:
+ chainXDirect = chainXDirect_AMD64; break;
+ case VexArchARM:
+ chainXDirect = chainXDirect_ARM; break;
+ case VexArchS390X:
+ chainXDirect = chainXDirect_S390; break;
+ case VexArchPPC32:
+ return chainXDirect_PPC(place_to_chain,
+ disp_cp_chain_me_EXPECTED,
+ place_to_jump_to, False/*!mode64*/);
+ case VexArchPPC64:
+ return chainXDirect_PPC(place_to_chain,
+ disp_cp_chain_me_EXPECTED,
+ place_to_jump_to, True/*mode64*/);
+ case VexArchMIPS32:
+ return chainXDirect_MIPS(place_to_chain,
+ disp_cp_chain_me_EXPECTED,
+ place_to_jump_to, False/*!mode64*/);
+ default:
+ vassert(0);
+ }
+ vassert(chainXDirect);
+ VexInvalRange vir
+ = chainXDirect(place_to_chain, disp_cp_chain_me_EXPECTED,
+ place_to_jump_to);
+ return vir;
+}
+
+VexInvalRange LibVEX_UnChain ( VexArch arch_host,
+ void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me )
+{
+ VexInvalRange (*unchainXDirect)(void*, void*, void*) = NULL;
+ switch (arch_host) {
+ case VexArchX86:
+ unchainXDirect = unchainXDirect_X86; break;
+ case VexArchAMD64:
+ unchainXDirect = unchainXDirect_AMD64; break;
+ case VexArchARM:
+ unchainXDirect = unchainXDirect_ARM; break;
+ case VexArchS390X:
+ unchainXDirect = unchainXDirect_S390; break;
+ case VexArchPPC32:
+ return unchainXDirect_PPC(place_to_unchain,
+ place_to_jump_to_EXPECTED,
+ disp_cp_chain_me, False/*!mode64*/);
+ case VexArchPPC64:
+ return unchainXDirect_PPC(place_to_unchain,
+ place_to_jump_to_EXPECTED,
+ disp_cp_chain_me, True/*mode64*/);
+ case VexArchMIPS32:
+ return unchainXDirect_MIPS(place_to_unchain,
+ place_to_jump_to_EXPECTED,
+ disp_cp_chain_me, False/*!mode64*/);
+ default:
+ vassert(0);
+ }
+ vassert(unchainXDirect);
+ VexInvalRange vir
+ = unchainXDirect(place_to_unchain, place_to_jump_to_EXPECTED,
+ disp_cp_chain_me);
+ return vir;
+}
+
+Int LibVEX_evCheckSzB ( VexArch arch_host )
+{
+ static Int cached = 0; /* DO NOT MAKE NON-STATIC */
+ if (UNLIKELY(cached == 0)) {
+ switch (arch_host) {
+ case VexArchX86:
+ cached = evCheckSzB_X86(); break;
+ case VexArchAMD64:
+ cached = evCheckSzB_AMD64(); break;
+ case VexArchARM:
+ cached = evCheckSzB_ARM(); break;
+ case VexArchS390X:
+ cached = evCheckSzB_S390(); break;
+ case VexArchPPC32:
+ case VexArchPPC64:
+ cached = evCheckSzB_PPC(); break;
+ case VexArchMIPS32:
+ cached = evCheckSzB_MIPS(); break;
+ default:
+ vassert(0);
+ }
+ }
+ return cached;
+}
+
+VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host,
+ void* place_to_patch,
+ ULong* location_of_counter )
+{
+ VexInvalRange (*patchProfInc)(void*,ULong*) = NULL;
+ switch (arch_host) {
+ case VexArchX86:
+ patchProfInc = patchProfInc_X86; break;
+ case VexArchAMD64:
+ patchProfInc = patchProfInc_AMD64; break;
+ case VexArchARM:
+ patchProfInc = patchProfInc_ARM; break;
+ case VexArchS390X:
+ patchProfInc = patchProfInc_S390; break;
+ case VexArchPPC32:
+ return patchProfInc_PPC(place_to_patch,
+ location_of_counter, False/*!mode64*/);
+ case VexArchPPC64:
+ return patchProfInc_PPC(place_to_patch,
+ location_of_counter, True/*mode64*/);
+ case VexArchMIPS32:
+ return patchProfInc_MIPS(place_to_patch,
+ location_of_counter, False/*!mode64*/);
+ default:
+ vassert(0);
+ }
+ vassert(patchProfInc);
+ VexInvalRange vir
+ = patchProfInc(place_to_patch, location_of_counter);
+ return vir;
+}
+
+
/* --------- Emulation warnings. --------- */
HChar* LibVEX_EmWarn_string ( VexEmWarn ew )
@@ -790,6 +1043,7 @@
case VexArchPPC32: return "PPC32";
case VexArchPPC64: return "PPC64";
case VexArchS390X: return "S390X";
+ case VexArchMIPS32: return "MIPS32";
default: return "VexArch???";
}
}
@@ -858,7 +1112,12 @@
/* SSE3 and CX16 are orthogonal and > baseline, although we really
don't expect to come across anything which can do SSE3 but can't
do CX16. Still, we can handle that case. LZCNT is similarly
- orthogonal. */
+ orthogonal. AVX is technically orthogonal, but just add the
+ cases we actually come across. (This scheme for printing is
+ very stupid. We should add strings independently based on
+ feature bits, but then it would be hard to return a string that
+ didn't need deallocating by the caller.) */
+ /* FIXME: show_hwcaps_s390x is a much better way to do this. */
switch (hwcaps) {
case 0:
return "amd64-sse2";
@@ -875,7 +1134,12 @@
case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
| VEX_HWCAPS_AMD64_LZCNT:
return "amd64-sse3-cx16-lzcnt";
-
+ case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
+ | VEX_HWCAPS_AMD64_AVX:
+ return "amd64-sse3-cx16-avx";
+ case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
+ | VEX_HWCAPS_AMD64_LZCNT | VEX_HWCAPS_AMD64_AVX:
+ return "amd64-sse3-cx16-lzcnt-avx";
default:
return NULL;
}
@@ -890,6 +1154,7 @@
const UInt FX = VEX_HWCAPS_PPC32_FX;
const UInt GX = VEX_HWCAPS_PPC32_GX;
const UInt VX = VEX_HWCAPS_PPC32_VX;
+ const UInt DFP = VEX_HWCAPS_PPC32_DFP;
UInt c = hwcaps;
if (c == 0) return "ppc32-int";
if (c == F) return "ppc32-int-flt";
@@ -900,7 +1165,8 @@
if (c == (F|V|FX)) return "ppc32-int-flt-vmx-FX";
if (c == (F|V|GX)) return "ppc32-int-flt-vmx-GX";
if (c == (F|V|FX|GX)) return "ppc32-int-flt-vmx-FX-GX";
- if (c == (F|V|FX|GX|VX)) return "ppc32-int-flt-vmx-FX-GX-VX";
+ if (c == (F|V|FX|GX|DFP)) return "ppc32-int-flt-vmx-FX-GX-DFP";
+ if (c == (F|V|FX|GX|VX|DFP)) return "ppc32-int-flt-vmx-FX-GX-VX-DFP";
return NULL;
}
@@ -912,6 +1178,7 @@
const UInt FX = VEX_HWCAPS_PPC64_FX;
const UInt GX = VEX_HWCAPS_PPC64_GX;
const UInt VX = VEX_HWCAPS_PPC64_VX;
+ const UInt DFP = VEX_HWCAPS_PPC64_DFP;
UInt c = hwcaps;
if (c == 0) return "ppc64-int-flt";
if (c == FX) return "ppc64-int-flt-FX";
@@ -921,7 +1188,8 @@
if (c == (V|FX)) return "ppc64-int-flt-vmx-FX";
if (c == (V|GX)) return "ppc64-int-flt-vmx-GX";
if (c == (V|FX|GX)) return "ppc64-int-flt-vmx-FX-GX";
- if (c == (V|FX|GX|VX)) return "ppc64-int-flt-vmx-FX-GX-VX";
+ if (c == (V|FX|GX|DFP)) return "ppc64-int-flt-vmx-FX-GX-DFP";
+ if (c == (V|FX|GX|VX|DFP)) return "ppc64-int-flt-vmx-FX-GX-VX-DFP";
return NULL;
}
@@ -974,6 +1242,9 @@
{ "gie" },
{ "dfp" },
{ "fgx" },
+ { "stfle" },
+ { "etf2" },
+ { "etf3" },
};
static HChar buf[sizeof facilities + sizeof prefix + 1];
static HChar *p;
@@ -993,6 +1264,12 @@
p = p + vex_sprintf(p, "-%s", facilities[3]);
if (hwcaps & VEX_HWCAPS_S390X_FGX)
p = p + vex_sprintf(p, "-%s", facilities[4]);
+ if (hwcaps & VEX_HWCAPS_S390X_STFLE)
+ p = p + vex_sprintf(p, "-%s", facilities[5]);
+ if (hwcaps & VEX_HWCAPS_S390X_ETF2)
+ p = p + vex_sprintf(p, "-%s", facilities[6]);
+ if (hwcaps & VEX_HWCAPS_S390X_ETF3)
+ p = p + vex_sprintf(p, "-%s", facilities[7]);
/* If there are no facilities, add "zarch" */
if (hwcaps == 0)
@@ -1001,16 +1278,24 @@
return buf;
}
+static HChar* show_hwcaps_mips32 ( UInt hwcaps )
+{
+ if (hwcaps == 0x00010000) return "MIPS-baseline";
+ if (hwcaps == 0x00020000) return "Broadcom-baseline";
+ return NULL;
+}
+
/* ---- */
static HChar* show_hwcaps ( VexArch arch, UInt hwcaps )
{
switch (arch) {
- case VexArchX86: return show_hwcaps_x86(hwcaps);
- case VexArchAMD64: return show_hwcaps_amd64(hwcaps);
- case VexArchPPC32: return show_hwcaps_ppc32(hwcaps);
- case VexArchPPC64: return show_hwcaps_ppc64(hwcaps);
- case VexArchARM: return show_hwcaps_arm(hwcaps);
- case VexArchS390X: return show_hwcaps_s390x(hwcaps);
+ case VexArchX86: return show_hwcaps_x86(hwcaps);
+ case VexArchAMD64: return show_hwcaps_amd64(hwcaps);
+ case VexArchPPC32: return show_hwcaps_ppc32(hwcaps);
+ case VexArchPPC64: return show_hwcaps_ppc64(hwcaps);
+ case VexArchARM: return show_hwcaps_arm(hwcaps);
+ case VexArchS390X: return show_hwcaps_s390x(hwcaps);
+ case VexArchMIPS32: return show_hwcaps_mips32(hwcaps);
default: return NULL;
}
}
diff --git a/main/VEX/priv/main_util.c b/main/VEX/priv/main_util.c
index 618254b..b4ca7be 100644
--- a/main/VEX/priv/main_util.c
+++ b/main/VEX/priv/main_util.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -254,6 +254,15 @@
}
}
+void vex_bzero ( void* sV, UInt n )
+{
+ UInt i;
+ UChar* s = (UChar*)sV;
+ /* No laughing, please. Just don't call this too often. Thank you
+ for your attention. */
+ for (i = 0; i < n; i++) s[i] = 0;
+}
+
/* Convert N0 into ascii in BUF, which is assumed to be big enough (at
least 67 bytes long). Observe BASE, SYNED and HEXCAPS. */
diff --git a/main/VEX/priv/main_util.h b/main/VEX/priv/main_util.h
index 914dc64..bee6649 100644
--- a/main/VEX/priv/main_util.h
+++ b/main/VEX/priv/main_util.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -75,7 +75,8 @@
/* String ops */
extern Bool vex_streq ( const HChar* s1, const HChar* s2 );
-extern Int vex_strlen ( const HChar* str );
+extern Int vex_strlen ( const HChar* str );
+extern void vex_bzero ( void* s, UInt n );
/* Storage management: clear the area, and allocate from it. */
diff --git a/main/VEX/pub/libvex.h b/main/VEX/pub/libvex.h
index e2933c9..9d7fcb0 100644
--- a/main/VEX/pub/libvex.h
+++ b/main/VEX/pub/libvex.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -57,7 +57,8 @@
VexArchARM,
VexArchPPC32,
VexArchPPC64,
- VexArchS390X
+ VexArchS390X,
+ VexArchMIPS32
}
VexArch;
@@ -80,6 +81,7 @@
#define VEX_HWCAPS_AMD64_SSE3 (1<<5) /* SSE3 support */
#define VEX_HWCAPS_AMD64_CX16 (1<<6) /* cmpxchg16b support */
#define VEX_HWCAPS_AMD64_LZCNT (1<<7) /* SSE4a LZCNT insn */
+#define VEX_HWCAPS_AMD64_AVX (1<<8) /* AVX instructions */
/* ppc32: baseline capability is integer only */
#define VEX_HWCAPS_PPC32_F (1<<8) /* basic (non-optional) FP */
@@ -88,6 +90,7 @@
#define VEX_HWCAPS_PPC32_GX (1<<11) /* Graphics extns
(fres,frsqrte,fsel,stfiwx) */
#define VEX_HWCAPS_PPC32_VX (1<<12) /* Vector-scalar floating-point (VSX); implies ISA 2.06 or higher */
+#define VEX_HWCAPS_PPC32_DFP (1<<17) /* Decimal Floating Point (DFP) -- e.g., dadd */
/* ppc64: baseline capability is integer and basic FP insns */
#define VEX_HWCAPS_PPC64_V (1<<13) /* Altivec (VMX) */
@@ -95,17 +98,13 @@
#define VEX_HWCAPS_PPC64_GX (1<<15) /* Graphics extns
(fres,frsqrte,fsel,stfiwx) */
#define VEX_HWCAPS_PPC64_VX (1<<16) /* Vector-scalar floating-point (VSX); implies ISA 2.06 or higher */
+#define VEX_HWCAPS_PPC64_DFP (1<<18) /* Decimal Floating Point (DFP) -- e.g., dadd */
/* s390x: Hardware capability encoding
- Bits Information
- [26:31] Machine model
- [25] Long displacement facility
- [24] Extended-immediate facility
- [23] General-instruction-extension facility
- [22] Decimal floating point facility
- [21] FPR-GR transfer facility
- [0:20] Currently unused; reserved for future use
+ Bits [26:31] encode the machine model (see VEX_S390X_MODEL... below)
+ Bits [0:20] encode specific hardware capabilities
+ (see VEX_HWAPS_S390X_... below)
*/
/* Model numbers must be assigned in chronological order.
@@ -120,7 +119,7 @@
#define VEX_S390X_MODEL_Z10_BC 7
#define VEX_S390X_MODEL_Z196 8
#define VEX_S390X_MODEL_Z114 9
-#define VEX_S390X_MODEL_INVALID 10
+#define VEX_S390X_MODEL_UNKNOWN 10 /* always last in list */
#define VEX_S390X_MODEL_MASK 0x3F
#define VEX_HWCAPS_S390X_LDISP (1<<6) /* Long-displacement facility */
@@ -128,13 +127,19 @@
#define VEX_HWCAPS_S390X_GIE (1<<8) /* General-instruction-extension facility */
#define VEX_HWCAPS_S390X_DFP (1<<9) /* Decimal floating point facility */
#define VEX_HWCAPS_S390X_FGX (1<<10) /* FPR-GR transfer facility */
+#define VEX_HWCAPS_S390X_ETF2 (1<<11) /* ETF2-enhancement facility */
+#define VEX_HWCAPS_S390X_STFLE (1<<12) /* STFLE facility */
+#define VEX_HWCAPS_S390X_ETF3 (1<<13) /* ETF3-enhancement facility */
/* Special value representing all available s390x hwcaps */
#define VEX_HWCAPS_S390X_ALL (VEX_HWCAPS_S390X_LDISP | \
VEX_HWCAPS_S390X_EIMM | \
VEX_HWCAPS_S390X_GIE | \
VEX_HWCAPS_S390X_DFP | \
- VEX_HWCAPS_S390X_FGX)
+ VEX_HWCAPS_S390X_FGX | \
+ VEX_HWCAPS_S390X_STFLE | \
+ VEX_HWCAPS_S390X_ETF3 | \
+ VEX_HWCAPS_S390X_ETF2)
#define VEX_HWCAPS_S390X(x) ((x) & ~VEX_S390X_MODEL_MASK)
#define VEX_S390X_MODEL(x) ((x) & VEX_S390X_MODEL_MASK)
@@ -150,6 +155,22 @@
/* Get an ARM architecure level from HWCAPS */
#define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f)
+/* MIPS baseline capability */
+/* Assigned Company values for bits 23:16 of the PRId Register
+ (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
+ MTI, the PRId register is defined in this (backwards compatible)
+ way:
+
+ +----------------+----------------+----------------+----------------+
+ | Company Options| Company ID | Processor ID | Revision |
+ +----------------+----------------+----------------+----------------+
+ 31 24 23 16 15 8 7
+
+*/
+
+#define VEX_PRID_COMP_MIPS 0x00010000
+#define VEX_PRID_COMP_BROADCOM 0x00020000
+
/* These return statically allocated strings. */
extern const HChar* LibVEX_ppVexArch ( VexArch );
@@ -286,6 +307,23 @@
/*--- Control of Vex's optimiser (iropt). ---*/
/*-------------------------------------------------------*/
+
+/* VexRegisterUpdates specifies when to ensure that the guest state is
+ up to date.
+
+ VexRegUpdUnwindregsAtMemAccess : registers needed to make a stack trace are
+ up to date at memory exception points. Typically, these are PC/SP/FP. The
+ minimal registers are described by the arch specific functions
+ guest_<arch>_state_requires_precise_mem_exns.
+
+ VexRegUpdAllregsAtMemAccess : all registers up to date at memory exception
+ points.
+
+ VexRegUpdAllregsAtEachInsn : all registers up to date at each instruction. */
+typedef enum { VexRegUpdUnwindregsAtMemAccess,
+ VexRegUpdAllregsAtMemAccess,
+ VexRegUpdAllregsAtEachInsn } VexRegisterUpdates;
+
/* Control of Vex's optimiser. */
typedef
@@ -295,10 +333,8 @@
/* Control aggressiveness of iropt. 0 = no opt, 1 = simple
opts, 2 (default) = max optimisation. */
Int iropt_level;
- /* Ensure all integer registers are up to date at potential
- memory exception points? True(default)=yes, False=no, only
- the guest's stack pointer. */
- Bool iropt_precise_memory_exns;
+ /* Controls when registers are updated in guest state. */
+ VexRegisterUpdates iropt_register_updates;
/* How aggressive should iropt be in unrolling loops? Higher
numbers make it more enthusiastic about loop unrolling.
Default=120. A setting of zero disables unrolling. */
@@ -343,6 +379,24 @@
static inline void* LibVEX_Alloc ( Int nbytes )
{
+ struct align {
+ char c;
+ union {
+ char c;
+ short s;
+ int i;
+ long l;
+ long long ll;
+ float f;
+ double d;
+ /* long double is currently not used and would increase alignment
+ unnecessarily. */
+ /* long double ld; */
+ void *pto;
+ void (*ptf)(void);
+ } x;
+ };
+
#if 0
/* Nasty debugging hack, do not use. */
return malloc(nbytes);
@@ -350,7 +404,7 @@
HChar* curr;
HChar* next;
Int ALIGN;
- ALIGN = sizeof(void*)-1;
+ ALIGN = offsetof(struct align,x) - 1;
nbytes = (nbytes + ALIGN) & ~ALIGN;
curr = private_LibVEX_alloc_curr;
next = curr + nbytes;
@@ -463,6 +517,12 @@
VexTransAccessFail, VexTransOutputFull } status;
/* The number of extents that have a self-check (0 to 3) */
UInt n_sc_extents;
+ /* Offset in generated code of the profile inc, or -1 if
+ none. Needed for later patching. */
+ Int offs_profInc;
+ /* Stats only: the number of guest insns included in the
+ translation. It may be zero (!). */
+ UInt n_guest_instrs;
}
VexTranslateResult;
@@ -560,6 +620,10 @@
/* IN: debug: trace vex activity at various points */
Int traceflags;
+ /* IN: profiling: add a 64 bit profiler counter increment to the
+ translation? */
+ Bool addProfInc;
+
/* IN: address of the dispatcher entry points. Describes the
places where generated code should jump to at the end of each
bb.
@@ -592,9 +656,13 @@
The aim is to get back and forth between translations and the
dispatcher without creating memory traffic to store return
addresses.
+
+ FIXME: update this comment
*/
- void* dispatch_unassisted;
- void* dispatch_assisted;
+ void* disp_cp_chain_me_to_slowEP;
+ void* disp_cp_chain_me_to_fastEP;
+ void* disp_cp_xindir;
+ void* disp_cp_xassisted;
}
VexTranslateArgs;
@@ -612,7 +680,60 @@
would not be the result. Therefore chase_into_ok should disallow
following into #2. That will force the caller to eventually
request a new translation starting at #2, at which point Vex will
- correctly observe the make-a-self-check flag. */
+ correctly observe the make-a-self-check flag.
+
+ FIXME: is this still up to date? */
+
+
+/*-------------------------------------------------------*/
+/*--- Patch existing translations ---*/
+/*-------------------------------------------------------*/
+
+/* Indicates a host address range for which callers to the functions
+ below must request I-D cache syncing after the call. ::len == 0 is
+ ambiguous -- it could mean either zero bytes or the entire address
+ space, so we mean the former. */
+typedef
+ struct {
+ HWord start;
+ HWord len;
+ }
+ VexInvalRange;
+
+/* Chain an XDirect jump located at place_to_chain so it jumps to
+ place_to_jump_to. It is expected (and checked) that this site
+ currently contains a call to the dispatcher specified by
+ disp_cp_chain_me_EXPECTED. */
+extern
+VexInvalRange LibVEX_Chain ( VexArch arch_host,
+ void* place_to_chain,
+ void* disp_cp_chain_me_EXPECTED,
+ void* place_to_jump_to );
+
+/* Undo an XDirect jump located at place_to_unchain, so it is
+ converted back into a call to disp_cp_chain_me. It is expected
+ (and checked) that this site currently contains a jump directly to
+ the address specified by place_to_jump_to_EXPECTED. */
+extern
+VexInvalRange LibVEX_UnChain ( VexArch arch_host,
+ void* place_to_unchain,
+ void* place_to_jump_to_EXPECTED,
+ void* disp_cp_chain_me );
+
+/* Returns a constant -- the size of the event check that is put at
+ the start of every translation. This makes it possible to
+ calculate the fast entry point address if the slow entry point
+ address is known (the usual case), or vice versa. */
+extern
+Int LibVEX_evCheckSzB ( VexArch arch_host );
+
+
+/* Patch the counter location into an existing ProfInc point. The
+ specified point is checked to make sure it is plausible. */
+extern
+VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host,
+ void* place_to_patch,
+ ULong* location_of_counter );
/*-------------------------------------------------------*/
diff --git a/main/VEX/pub/libvex_basictypes.h b/main/VEX/pub/libvex_basictypes.h
index 4731d71..9f60f19 100644
--- a/main/VEX/pub/libvex_basictypes.h
+++ b/main/VEX/pub/libvex_basictypes.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -62,6 +62,9 @@
/* Always 128 bits. */
typedef UInt U128[4];
+/* Always 256 bits. */
+typedef UInt U256[8];
+
/* A union for doing 128-bit vector primitives conveniently. */
typedef
union {
@@ -171,6 +174,10 @@
# define VEX_HOST_WORDSIZE 8
# define VEX_REGPARM(_n) /* */
+#elif defined(__mips__)
+# define VEX_HOST_WORDSIZE 4
+# define VEX_REGPARM(_n) /* */
+
#else
# error "Vex: Fatal: Can't establish the host architecture"
#endif
diff --git a/main/VEX/pub/libvex_emwarn.h b/main/VEX/pub/libvex_emwarn.h
index 114388b..4f43f43 100644
--- a/main/VEX/pub/libvex_emwarn.h
+++ b/main/VEX/pub/libvex_emwarn.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
diff --git a/main/VEX/pub/libvex_guest_amd64.h b/main/VEX/pub/libvex_guest_amd64.h
index 564f6a0..3712cbc 100644
--- a/main/VEX/pub/libvex_guest_amd64.h
+++ b/main/VEX/pub/libvex_guest_amd64.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -52,34 +52,39 @@
typedef
struct {
- /* 0 */ ULong guest_RAX;
- /* 8 */ ULong guest_RCX;
- /* 16 */ ULong guest_RDX;
- /* 24 */ ULong guest_RBX;
- /* 32 */ ULong guest_RSP;
- /* 40 */ ULong guest_RBP;
- /* 48 */ ULong guest_RSI;
- /* 56 */ ULong guest_RDI;
- /* 64 */ ULong guest_R8;
- /* 72 */ ULong guest_R9;
- /* 80 */ ULong guest_R10;
- /* 88 */ ULong guest_R11;
- /* 96 */ ULong guest_R12;
- /* 104 */ ULong guest_R13;
- /* 112 */ ULong guest_R14;
- /* 120 */ ULong guest_R15;
+ /* Event check fail addr, counter, and padding to make RAX 16
+ aligned. */
+ /* 0 */ ULong host_EvC_FAILADDR;
+ /* 8 */ UInt host_EvC_COUNTER;
+ /* 12 */ UInt pad0;
+ /* 16 */ ULong guest_RAX;
+ /* 24 */ ULong guest_RCX;
+ /* 32 */ ULong guest_RDX;
+ /* 40 */ ULong guest_RBX;
+ /* 48 */ ULong guest_RSP;
+ /* 56 */ ULong guest_RBP;
+ /* 64 */ ULong guest_RSI;
+ /* 72 */ ULong guest_RDI;
+ /* 80 */ ULong guest_R8;
+ /* 88 */ ULong guest_R9;
+ /* 96 */ ULong guest_R10;
+ /* 104 */ ULong guest_R11;
+ /* 112 */ ULong guest_R12;
+ /* 120 */ ULong guest_R13;
+ /* 128 */ ULong guest_R14;
+ /* 136 */ ULong guest_R15;
/* 4-word thunk used to calculate O S Z A C P flags. */
- /* 128 */ ULong guest_CC_OP;
- /* 136 */ ULong guest_CC_DEP1;
- /* 144 */ ULong guest_CC_DEP2;
- /* 152 */ ULong guest_CC_NDEP;
+ /* 144 */ ULong guest_CC_OP;
+ /* 152 */ ULong guest_CC_DEP1;
+ /* 160 */ ULong guest_CC_DEP2;
+ /* 168 */ ULong guest_CC_NDEP;
/* The D flag is stored here, encoded as either -1 or +1 */
- /* 160 */ ULong guest_DFLAG;
- /* 168 */ ULong guest_RIP;
+ /* 176 */ ULong guest_DFLAG;
+ /* 184 */ ULong guest_RIP;
/* Bit 18 (AC) of eflags stored here, as either 0 or 1. */
/* ... */ ULong guest_ACFLAG;
/* Bit 21 (ID) of eflags stored here, as either 0 or 1. */
- /* 176 */ ULong guest_IDFLAG;
+ /* 192 */ ULong guest_IDFLAG;
/* Probably a lot more stuff too.
D,ID flags
16 128-bit SSE registers
@@ -89,43 +94,43 @@
/* HACK to make tls on amd64-linux work. %fs only ever seems to
hold zero, and so guest_FS_ZERO holds the 64-bit offset
associated with a %fs value of zero. */
- /* 184 */ ULong guest_FS_ZERO;
+ /* 200 */ ULong guest_FS_ZERO;
- /* XMM registers. Note that these must be allocated
+ /* YMM registers. Note that these must be allocated
consecutively in order that the SSE4.2 PCMP{E,I}STR{I,M}
- helpers can treat them as an array. XMM16 is a fake reg used
+ helpers can treat them as an array. YMM16 is a fake reg used
as an intermediary in handling aforementioned insns. */
- /* 192 */ULong guest_SSEROUND;
- /* 200 */U128 guest_XMM0;
- U128 guest_XMM1;
- U128 guest_XMM2;
- U128 guest_XMM3;
- U128 guest_XMM4;
- U128 guest_XMM5;
- U128 guest_XMM6;
- U128 guest_XMM7;
- U128 guest_XMM8;
- U128 guest_XMM9;
- U128 guest_XMM10;
- U128 guest_XMM11;
- U128 guest_XMM12;
- U128 guest_XMM13;
- U128 guest_XMM14;
- U128 guest_XMM15;
- U128 guest_XMM16;
+ /* 208 */ULong guest_SSEROUND;
+ /* 216 */U256 guest_YMM0;
+ U256 guest_YMM1;
+ U256 guest_YMM2;
+ U256 guest_YMM3;
+ U256 guest_YMM4;
+ U256 guest_YMM5;
+ U256 guest_YMM6;
+ U256 guest_YMM7;
+ U256 guest_YMM8;
+ U256 guest_YMM9;
+ U256 guest_YMM10;
+ U256 guest_YMM11;
+ U256 guest_YMM12;
+ U256 guest_YMM13;
+ U256 guest_YMM14;
+ U256 guest_YMM15;
+ U256 guest_YMM16;
/* FPU */
/* Note. Setting guest_FTOP to be ULong messes up the
delicately-balanced PutI/GetI optimisation machinery.
Therefore best to leave it as a UInt. */
- /* 456 */UInt guest_FTOP;
+ UInt guest_FTOP;
ULong guest_FPREG[8];
- /* 528 */ UChar guest_FPTAG[8];
- /* 536 */ ULong guest_FPROUND;
- /* 544 */ ULong guest_FC3210;
+ UChar guest_FPTAG[8];
+ ULong guest_FPROUND;
+ ULong guest_FC3210;
/* Emulation warnings */
- /* 552 */ UInt guest_EMWARN;
+ UInt guest_EMWARN;
/* Translation-invalidation area description. Not used on amd64
(there is no invalidate-icache insn), but needed so as to
@@ -161,7 +166,7 @@
ULong guest_IP_AT_SYSCALL;
/* Padding to make it have an 16-aligned size */
- ULong padding;
+ ULong pad1;
}
VexGuestAMD64State;
diff --git a/main/VEX/pub/libvex_guest_arm.h b/main/VEX/pub/libvex_guest_arm.h
index b6a6a4f..f5cdeac 100644
--- a/main/VEX/pub/libvex_guest_arm.h
+++ b/main/VEX/pub/libvex_guest_arm.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -42,6 +42,9 @@
typedef
struct {
/* 0 */
+ /* Event check fail addr and counter. */
+ UInt host_EvC_FAILADDR; /* 0 */
+ UInt host_EvC_COUNTER; /* 4 */
UInt guest_R0;
UInt guest_R1;
UInt guest_R2;
@@ -69,7 +72,7 @@
/* 4-word thunk used to calculate N(sign) Z(zero) C(carry,
unsigned overflow) and V(signed overflow) flags. */
- /* 64 */
+ /* 72 */
UInt guest_CC_OP;
UInt guest_CC_DEP1;
UInt guest_CC_DEP2;
@@ -108,11 +111,11 @@
program counter at the last syscall insn (int 0x80/81/82,
sysenter, syscall, svc). Used when backing up to restart a
syscall that has been interrupted by a signal. */
- /* 116 */
+ /* 124 */
UInt guest_IP_AT_SYSCALL;
/* VFP state. D0 .. D15 must be 8-aligned. */
- /* 120 -- I guess there's 4 bytes of padding just prior to this? */
+ /* 128 */
ULong guest_D0;
ULong guest_D1;
ULong guest_D2;
@@ -191,10 +194,12 @@
*/
UInt guest_ITSTATE;
- /* Padding to make it have an 16-aligned size */
+ /* Padding to make it have an 32-aligned size */
UInt padding1;
UInt padding2;
UInt padding3;
+ UInt padding4;
+ UInt padding5;
}
VexGuestARMState;
diff --git a/main/VEX/pub/libvex_guest_mips32.h b/main/VEX/pub/libvex_guest_mips32.h
new file mode 100644
index 0000000..177bf6b
--- /dev/null
+++ b/main/VEX/pub/libvex_guest_mips32.h
@@ -0,0 +1,161 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin libvex_guest_mips32.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __LIBVEX_PUB_GUEST_MIPS32_H
+#define __LIBVEX_PUB_GUEST_MIPS32_H
+
+#include "libvex_basictypes.h"
+#include "libvex_emwarn.h"
+
+
+/*---------------------------------------------------------------*/
+/*--- Vex's representation of the MIPS32 CPU state. ---*/
+/*---------------------------------------------------------------*/
+
+typedef
+ struct {
+ /* CPU Registers */
+ /* 0 */ UInt guest_r0; /* Hardwired to 0 */
+ /* 4 */ UInt guest_r1; /* Assembler temporary */
+ /* 8 */ UInt guest_r2; /* Values for function returns ...*/
+ /* 12 */ UInt guest_r3; /* ...and expression evaluation */
+ /* 16 */ UInt guest_r4; /* Function arguments */
+ /* 20 */ UInt guest_r5;
+ /* 24 */ UInt guest_r6;
+ /* 28 */ UInt guest_r7;
+ /* 32 */ UInt guest_r8; /* Temporaries */
+ /* 36 */ UInt guest_r9;
+ /* 40 */ UInt guest_r10;
+ /* 44 */ UInt guest_r11;
+ /* 48 */ UInt guest_r12;
+ /* 52 */ UInt guest_r13;
+ /* 56 */ UInt guest_r14;
+ /* 60 */ UInt guest_r15;
+ /* 64 */ UInt guest_r16; /* Saved temporaries */
+ /* 68 */ UInt guest_r17;
+ /* 72 */ UInt guest_r18;
+ /* 76 */ UInt guest_r19;
+ /* 80 */ UInt guest_r20;
+ /* 84 */ UInt guest_r21;
+ /* 88 */ UInt guest_r22;
+ /* 92 */ UInt guest_r23;
+ /* 96 */ UInt guest_r24; /* Temporaries */
+ /* 100 */ UInt guest_r25;
+ /* 104 */ UInt guest_r26; /* Reserved for OS kernel */
+ /* 108 */ UInt guest_r27;
+ /* 112 */ UInt guest_r28; /* Global pointer */
+ /* 116 */ UInt guest_r29; /* Stack pointer */
+ /* 120 */ UInt guest_r30; /* Frame pointer */
+ /* 124 */ UInt guest_r31; /* Return address */
+ /* 128 */ UInt guest_PC; /* Program counter */
+ /* 132 */ UInt guest_HI;/* Multiply and divide register higher result */
+ /* 136 */ UInt guest_LO;/* Multiply and divide register lower result */
+
+ /* FPU Registers */
+ /* 140 */ UInt guest_f0; /* Floting point general purpose registers */
+ /* 144 */ UInt guest_f1;
+ /* 148 */ UInt guest_f2;
+ /* 152 */ UInt guest_f3;
+ /* 156 */ UInt guest_f4;
+ /* 160 */ UInt guest_f5;
+ /* 164 */ UInt guest_f6;
+ /* 168 */ UInt guest_f7;
+ /* 172 */ UInt guest_f8;
+ /* 176 */ UInt guest_f9;
+ /* 180 */ UInt guest_f10;
+ /* 184 */ UInt guest_f11;
+ /* 188 */ UInt guest_f12;
+ /* 192 */ UInt guest_f13;
+ /* 196 */ UInt guest_f14;
+ /* 200 */ UInt guest_f15;
+ /* 204 */ UInt guest_f16;
+ /* 208 */ UInt guest_f17;
+ /* 212 */ UInt guest_f18;
+ /* 216 */ UInt guest_f19;
+ /* 220 */ UInt guest_f20;
+ /* 224 */ UInt guest_f21;
+ /* 228 */ UInt guest_f22;
+ /* 232 */ UInt guest_f23;
+ /* 236 */ UInt guest_f24;
+ /* 240 */ UInt guest_f25;
+ /* 244 */ UInt guest_f26;
+ /* 248 */ UInt guest_f27;
+ /* 252 */ UInt guest_f28;
+ /* 256 */ UInt guest_f29;
+ /* 260 */ UInt guest_f30;
+ /* 264 */ UInt guest_f31;
+
+ /* 268 */ UInt guest_FIR;
+ /* 272 */ UInt guest_FCCR;
+ /* 276 */ UInt guest_FEXR;
+ /* 280 */ UInt guest_FENR;
+ /* 284 */ UInt guest_FCSR;
+
+ /* TLS pointer for the thread. It's read-only in user space.
+ On Linux it is set in user space by various thread-related
+ syscalls.
+ User Local Register.
+ This register provides read access to the coprocessor 0
+ UserLocal register, if it is implemented. In some operating
+ environments, the UserLocal register is a pointer to a
+ thread-specific storage block.
+ */
+ /* 288 */ UInt guest_ULR;
+
+ /* Emulation warnings */
+ UInt guest_EMWARN; /* 292 */
+
+ /* For clflush: record start and length of area to invalidate */
+ UInt guest_TISTART; /* 296 */
+ UInt guest_TILEN; /* 300 */
+ UInt guest_NRADDR; /* 304 */
+
+ UInt host_EvC_FAILADDR; /* 308 */
+ UInt host_EvC_COUNTER; /* 312 */
+ UInt guest_COND; /* 316 */
+} VexGuestMIPS32State;
+/*---------------------------------------------------------------*/
+/*--- Utility functions for MIPS32 guest stuff. ---*/
+/*---------------------------------------------------------------*/
+
+/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */
+
+/* Initialise all guest MIPS32 state. */
+
+extern
+void LibVEX_GuestMIPS32_initialise ( /*OUT*/VexGuestMIPS32State* vex_state );
+
+
+#endif /* ndef __LIBVEX_PUB_GUEST_MIPS32_H */
+
+
+/*---------------------------------------------------------------*/
+/*--- libvex_guest_mips32.h ---*/
+/*---------------------------------------------------------------*/
diff --git a/main/VEX/pub/libvex_guest_offsets.h b/main/VEX/pub/libvex_guest_offsets.h
index 6cf2d83..59b089b 100644
--- a/main/VEX/pub/libvex_guest_offsets.h
+++ b/main/VEX/pub/libvex_guest_offsets.h
@@ -1,71 +1,71 @@
-#define OFFSET_x86_EAX 0
-#define OFFSET_x86_EBX 12
-#define OFFSET_x86_ECX 4
-#define OFFSET_x86_EDX 8
-#define OFFSET_x86_ESI 24
-#define OFFSET_x86_EDI 28
-#define OFFSET_x86_EBP 20
-#define OFFSET_x86_ESP 16
-#define OFFSET_x86_EIP 60
-#define OFFSET_x86_CS 280
-#define OFFSET_x86_DS 282
-#define OFFSET_x86_ES 284
-#define OFFSET_x86_FS 286
-#define OFFSET_x86_GS 288
-#define OFFSET_x86_SS 290
-#define OFFSET_amd64_RAX 0
-#define OFFSET_amd64_RBX 24
-#define OFFSET_amd64_RCX 8
-#define OFFSET_amd64_RDX 16
-#define OFFSET_amd64_RSI 48
-#define OFFSET_amd64_RDI 56
-#define OFFSET_amd64_RSP 32
-#define OFFSET_amd64_RBP 40
-#define OFFSET_amd64_R8 64
-#define OFFSET_amd64_R9 72
-#define OFFSET_amd64_R10 80
-#define OFFSET_amd64_R11 88
-#define OFFSET_amd64_R12 96
-#define OFFSET_amd64_R13 104
-#define OFFSET_amd64_R14 112
-#define OFFSET_amd64_R15 120
-#define OFFSET_amd64_RIP 168
-#define OFFSET_ppc32_GPR0 0
-#define OFFSET_ppc32_GPR1 4
-#define OFFSET_ppc32_GPR2 8
-#define OFFSET_ppc32_GPR3 12
-#define OFFSET_ppc32_GPR4 16
-#define OFFSET_ppc32_GPR5 20
-#define OFFSET_ppc32_GPR6 24
-#define OFFSET_ppc32_GPR7 28
-#define OFFSET_ppc32_GPR8 32
-#define OFFSET_ppc32_GPR9 36
-#define OFFSET_ppc32_GPR10 40
-#define OFFSET_ppc32_CIA 1152
-#define OFFSET_ppc32_CR0_0 1169
-#define OFFSET_ppc64_GPR0 0
-#define OFFSET_ppc64_GPR1 8
-#define OFFSET_ppc64_GPR2 16
-#define OFFSET_ppc64_GPR3 24
-#define OFFSET_ppc64_GPR4 32
-#define OFFSET_ppc64_GPR5 40
-#define OFFSET_ppc64_GPR6 48
-#define OFFSET_ppc64_GPR7 56
-#define OFFSET_ppc64_GPR8 64
-#define OFFSET_ppc64_GPR9 72
-#define OFFSET_ppc64_GPR10 80
-#define OFFSET_ppc64_CIA 1280
-#define OFFSET_ppc64_CR0_0 1309
-#define OFFSET_arm_R0 0
-#define OFFSET_arm_R1 4
-#define OFFSET_arm_R2 8
-#define OFFSET_arm_R3 12
-#define OFFSET_arm_R4 16
-#define OFFSET_arm_R5 20
-#define OFFSET_arm_R7 28
-#define OFFSET_arm_R13 52
-#define OFFSET_arm_R14 56
-#define OFFSET_arm_R15T 60
+#define OFFSET_x86_EAX 8
+#define OFFSET_x86_EBX 20
+#define OFFSET_x86_ECX 12
+#define OFFSET_x86_EDX 16
+#define OFFSET_x86_ESI 32
+#define OFFSET_x86_EDI 36
+#define OFFSET_x86_EBP 28
+#define OFFSET_x86_ESP 24
+#define OFFSET_x86_EIP 68
+#define OFFSET_x86_CS 288
+#define OFFSET_x86_DS 290
+#define OFFSET_x86_ES 292
+#define OFFSET_x86_FS 294
+#define OFFSET_x86_GS 296
+#define OFFSET_x86_SS 298
+#define OFFSET_amd64_RAX 16
+#define OFFSET_amd64_RBX 40
+#define OFFSET_amd64_RCX 24
+#define OFFSET_amd64_RDX 32
+#define OFFSET_amd64_RSI 64
+#define OFFSET_amd64_RDI 72
+#define OFFSET_amd64_RSP 48
+#define OFFSET_amd64_RBP 56
+#define OFFSET_amd64_R8 80
+#define OFFSET_amd64_R9 88
+#define OFFSET_amd64_R10 96
+#define OFFSET_amd64_R11 104
+#define OFFSET_amd64_R12 112
+#define OFFSET_amd64_R13 120
+#define OFFSET_amd64_R14 128
+#define OFFSET_amd64_R15 136
+#define OFFSET_amd64_RIP 184
+#define OFFSET_ppc32_GPR0 16
+#define OFFSET_ppc32_GPR1 20
+#define OFFSET_ppc32_GPR2 24
+#define OFFSET_ppc32_GPR3 28
+#define OFFSET_ppc32_GPR4 32
+#define OFFSET_ppc32_GPR5 36
+#define OFFSET_ppc32_GPR6 40
+#define OFFSET_ppc32_GPR7 44
+#define OFFSET_ppc32_GPR8 48
+#define OFFSET_ppc32_GPR9 52
+#define OFFSET_ppc32_GPR10 56
+#define OFFSET_ppc32_CIA 1168
+#define OFFSET_ppc32_CR0_0 1185
+#define OFFSET_ppc64_GPR0 16
+#define OFFSET_ppc64_GPR1 24
+#define OFFSET_ppc64_GPR2 32
+#define OFFSET_ppc64_GPR3 40
+#define OFFSET_ppc64_GPR4 48
+#define OFFSET_ppc64_GPR5 56
+#define OFFSET_ppc64_GPR6 64
+#define OFFSET_ppc64_GPR7 72
+#define OFFSET_ppc64_GPR8 80
+#define OFFSET_ppc64_GPR9 88
+#define OFFSET_ppc64_GPR10 96
+#define OFFSET_ppc64_CIA 1296
+#define OFFSET_ppc64_CR0_0 1325
+#define OFFSET_arm_R0 8
+#define OFFSET_arm_R1 12
+#define OFFSET_arm_R2 16
+#define OFFSET_arm_R3 20
+#define OFFSET_arm_R4 24
+#define OFFSET_arm_R5 28
+#define OFFSET_arm_R7 36
+#define OFFSET_arm_R13 60
+#define OFFSET_arm_R14 64
+#define OFFSET_arm_R15T 68
#define OFFSET_s390x_r2 208
#define OFFSET_s390x_r3 216
#define OFFSET_s390x_r4 224
@@ -77,3 +77,42 @@
#define OFFSET_s390x_SYSNO 344
#define OFFSET_s390x_IP_AT_SYSCALL 408
#define OFFSET_s390x_fpc 328
+#define OFFSET_s390x_CC_OP 352
+#define OFFSET_s390x_CC_DEP1 360
+#define OFFSET_s390x_CC_DEP2 368
+#define OFFSET_s390x_CC_NDEP 376
+#define OFFSET_mips32_r0 0
+#define OFFSET_mips32_r1 4
+#define OFFSET_mips32_r2 8
+#define OFFSET_mips32_r3 12
+#define OFFSET_mips32_r4 16
+#define OFFSET_mips32_r5 20
+#define OFFSET_mips32_r6 24
+#define OFFSET_mips32_r7 28
+#define OFFSET_mips32_r8 32
+#define OFFSET_mips32_r9 36
+#define OFFSET_mips32_r10 40
+#define OFFSET_mips32_r11 44
+#define OFFSET_mips32_r12 48
+#define OFFSET_mips32_r13 52
+#define OFFSET_mips32_r14 56
+#define OFFSET_mips32_r15 60
+#define OFFSET_mips32_r15 60
+#define OFFSET_mips32_r17 68
+#define OFFSET_mips32_r18 72
+#define OFFSET_mips32_r19 76
+#define OFFSET_mips32_r20 80
+#define OFFSET_mips32_r21 84
+#define OFFSET_mips32_r22 88
+#define OFFSET_mips32_r23 92
+#define OFFSET_mips32_r24 96
+#define OFFSET_mips32_r25 100
+#define OFFSET_mips32_r26 104
+#define OFFSET_mips32_r27 108
+#define OFFSET_mips32_r28 112
+#define OFFSET_mips32_r29 116
+#define OFFSET_mips32_r30 120
+#define OFFSET_mips32_r31 124
+#define OFFSET_mips32_PC 128
+#define OFFSET_mips32_HI 132
+#define OFFSET_mips32_LO 136
diff --git a/main/VEX/pub/libvex_guest_ppc32.h b/main/VEX/pub/libvex_guest_ppc32.h
index 00b7649..606f16c 100644
--- a/main/VEX/pub/libvex_guest_ppc32.h
+++ b/main/VEX/pub/libvex_guest_ppc32.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -48,6 +48,12 @@
typedef
struct {
+ /* Event check fail addr and counter. */
+ /* 0 */ UInt host_EvC_FAILADDR;
+ /* 4 */ UInt host_EvC_COUNTER;
+ /* 8 */ UInt pad3;
+ /* 12 */ UInt pad4;
+ /* Add 16 to all the numbers below. Sigh. */
/* General Purpose Registers */
/* 0 */ UInt guest_GPR0;
/* 4 */ UInt guest_GPR1;
@@ -189,8 +195,11 @@
/* 1182 */ UChar guest_CR7_321; /* in [3:1] */
/* 1183 */ UChar guest_CR7_0; /* in lsb */
- /* FP Status & Control Register fields */
- /* 1184 */ UInt guest_FPROUND; // FP Rounding Mode
+ /* FP Status & Control Register fields. Only rounding mode fields are supported. */
+ /* 1184 */ UChar guest_FPROUND; // Binary Floating Point Rounding Mode
+ /* 1185 */ UChar guest_DFPROUND; // Decimal Floating Point Rounding Mode
+ /* 1186 */ UChar pad1;
+ /* 1187 */ UChar pad2;
/* Vector Save/Restore Register */
/* 1188 */ UInt guest_VRSAVE;
diff --git a/main/VEX/pub/libvex_guest_ppc64.h b/main/VEX/pub/libvex_guest_ppc64.h
index 631791b..e034509 100644
--- a/main/VEX/pub/libvex_guest_ppc64.h
+++ b/main/VEX/pub/libvex_guest_ppc64.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -86,6 +86,12 @@
typedef
struct {
+ /* Event check fail addr, counter, and padding to make GPR0 16
+ aligned. */
+ /* 0 */ ULong host_EvC_FAILADDR;
+ /* 8 */ UInt host_EvC_COUNTER;
+ /* 12 */ UInt pad0;
+ /* Add 16 to all of the offsets below .. */
/* General Purpose Registers */
/* 0 */ ULong guest_GPR0;
/* 8 */ ULong guest_GPR1;
@@ -227,8 +233,12 @@
/* 1322 */ UChar guest_CR7_321; /* in [3:1] */
/* 1323 */ UChar guest_CR7_0; /* in lsb */
- /* FP Status & Control Register fields */
- /* 1324 */ UInt guest_FPROUND; // FP Rounding Mode
+ /* FP Status and Control Register fields. Only rounding mode fields
+ are supported. */
+ /* 1324 */ UChar guest_FPROUND; // Binary Floating Point Rounding Mode
+ /* 1325 */ UChar guest_DFPROUND; // Decimal Floating Point Rounding Mode
+ /* 1326 */ UChar pad1;
+ /* 1327 */ UChar pad2;
/* Vector Save/Restore Register */
/* 1328 */ UInt guest_VRSAVE;
@@ -270,8 +280,11 @@
threading on AIX. */
/* 1648 */ ULong guest_SPRG3_RO;
+ /* offsets in comments are wrong ..*/
/* Padding to make it have an 16-aligned size */
/* 1656 */ ULong padding2;
+ /* 16XX */ ULong padding3;
+ /* 16XX */ ULong padding4;
}
VexGuestPPC64State;
diff --git a/main/VEX/pub/libvex_guest_s390x.h b/main/VEX/pub/libvex_guest_s390x.h
index 3bbeaf2..8156342 100644
--- a/main/VEX/pub/libvex_guest_s390x.h
+++ b/main/VEX/pub/libvex_guest_s390x.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -144,12 +144,16 @@
/* Emulation warnings; see comments in libvex_emwarn.h */
/* 416 */ UInt guest_EMWARN;
-/*------------------------------------------------------------*/
-/*--- Force alignment to 16 bytes ---*/
-/*------------------------------------------------------------*/
- /* 420 */ UChar padding[12];
+ /* For translation chaining */
+ /* 420 */ UInt host_EvC_COUNTER;
+ /* 424 */ ULong host_EvC_FAILADDR;
- /* 432 */ /* This is the size of the guest state */
+/*------------------------------------------------------------*/
+/*--- Force alignment to 32 bytes ---*/
+/*------------------------------------------------------------*/
+ /* 432 */ UChar padding[16];
+
+ /* 448 */ /* This is the size of the guest state */
} VexGuestS390XState;
diff --git a/main/VEX/pub/libvex_guest_x86.h b/main/VEX/pub/libvex_guest_x86.h
index 80ee423..3878557 100644
--- a/main/VEX/pub/libvex_guest_x86.h
+++ b/main/VEX/pub/libvex_guest_x86.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -141,40 +141,43 @@
*/
typedef
struct {
- UInt guest_EAX; /* 0 */
+ /* Event check fail addr and counter. */
+ UInt host_EvC_FAILADDR; /* 0 */
+ UInt host_EvC_COUNTER; /* 4 */
+ UInt guest_EAX; /* 8 */
UInt guest_ECX;
UInt guest_EDX;
UInt guest_EBX;
UInt guest_ESP;
UInt guest_EBP;
UInt guest_ESI;
- UInt guest_EDI; /* 28 */
+ UInt guest_EDI; /* 36 */
/* 4-word thunk used to calculate O S Z A C P flags. */
- UInt guest_CC_OP; /* 32 */
+ UInt guest_CC_OP; /* 40 */
UInt guest_CC_DEP1;
UInt guest_CC_DEP2;
- UInt guest_CC_NDEP; /* 44 */
+ UInt guest_CC_NDEP; /* 52 */
/* The D flag is stored here, encoded as either -1 or +1 */
- UInt guest_DFLAG; /* 48 */
+ UInt guest_DFLAG; /* 56 */
/* Bit 21 (ID) of eflags stored here, as either 0 or 1. */
- UInt guest_IDFLAG; /* 52 */
+ UInt guest_IDFLAG; /* 60 */
/* Bit 18 (AC) of eflags stored here, as either 0 or 1. */
- UInt guest_ACFLAG; /* 56 */
+ UInt guest_ACFLAG; /* 64 */
/* EIP */
- UInt guest_EIP; /* 60 */
+ UInt guest_EIP; /* 68 */
/* FPU */
- ULong guest_FPREG[8]; /* 64 */
- UChar guest_FPTAG[8]; /* 128 */
- UInt guest_FPROUND; /* 136 */
- UInt guest_FC3210; /* 140 */
- UInt guest_FTOP; /* 144 */
+ ULong guest_FPREG[8]; /* 72 */
+ UChar guest_FPTAG[8]; /* 136 */
+ UInt guest_FPROUND; /* 144 */
+ UInt guest_FC3210; /* 148 */
+ UInt guest_FTOP; /* 152 */
/* SSE */
- UInt guest_SSEROUND; /* 148 */
- U128 guest_XMM0; /* 152 */
+ UInt guest_SSEROUND; /* 156 */
+ U128 guest_XMM0; /* 160 */
U128 guest_XMM1;
U128 guest_XMM2;
U128 guest_XMM3;
@@ -218,10 +221,8 @@
been interrupted by a signal. */
UInt guest_IP_AT_SYSCALL;
- /* Padding to make it have an 16-aligned size */
- UInt padding1;
- UInt padding2;
- UInt padding3;
+ /* Padding to make it have an 32-aligned size */
+ UInt padding[5];
}
VexGuestX86State;
diff --git a/main/VEX/pub/libvex_ir.h b/main/VEX/pub/libvex_ir.h
index 0c316c5..0995ec8 100644
--- a/main/VEX/pub/libvex_ir.h
+++ b/main/VEX/pub/libvex_ir.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -227,8 +227,12 @@
Ity_I128, /* 128-bit scalar */
Ity_F32, /* IEEE 754 float */
Ity_F64, /* IEEE 754 double */
+ Ity_D32, /* 32-bit Decimal floating point */
+ Ity_D64, /* 64-bit Decimal floating point */
+ Ity_D128, /* 128-bit Decimal floating point */
Ity_F128, /* 128-bit floating point; implementation defined */
- Ity_V128 /* 128-bit SIMD */
+ Ity_V128, /* 128-bit SIMD */
+ Ity_V256 /* 256-bit SIMD */
}
IRType;
@@ -268,8 +272,10 @@
Ico_F64, /* 64-bit IEEE754 floating */
Ico_F64i, /* 64-bit unsigned int to be interpreted literally
as a IEEE754 double value. */
- Ico_V128 /* 128-bit restricted vector constant, with 1 bit
+ Ico_V128, /* 128-bit restricted vector constant, with 1 bit
(repeated 8 times) for each of the 16 x 1-byte lanes */
+ Ico_V256 /* 256-bit restricted vector constant, with 1 bit
+ (repeated 8 times) for each of the 32 x 1-byte lanes */
}
IRConstTag;
@@ -291,6 +297,7 @@
Double F64;
ULong F64i;
UShort V128; /* 16-bit value; see Ico_V128 comment above */
+ UInt V256; /* 32-bit value; see Ico_V256 comment above */
} Ico;
}
IRConst;
@@ -306,6 +313,7 @@
extern IRConst* IRConst_F64 ( Double );
extern IRConst* IRConst_F64i ( ULong );
extern IRConst* IRConst_V128 ( UShort );
+extern IRConst* IRConst_V256 ( UInt );
/* Deep-copy an IRConst */
extern IRConst* deepCopyIRConst ( IRConst* );
@@ -738,6 +746,10 @@
/* ------------------ 32-bit SIMD Integer ------------------ */
+ /* 32x1 saturating add/sub (ok, well, not really SIMD :) */
+ Iop_QAdd32S,
+ Iop_QSub32S,
+
/* 16x2 add/sub, also signed/unsigned saturating variants */
Iop_Add16x2, Iop_Sub16x2,
Iop_QAdd16Sx2, Iop_QAdd16Ux2,
@@ -983,6 +995,140 @@
See floating-point equiwalents for details. */
Iop_Recip32x2, Iop_Rsqrte32x2,
+ /* ------------------ Decimal Floating Point ------------------ */
+
+ /* ARITHMETIC INSTRUCTIONS 64-bit
+ ----------------------------------
+ IRRoundingModeDFP(I32) X D64 X D64 -> D64
+ */
+ Iop_AddD64, Iop_SubD64, Iop_MulD64, Iop_DivD64,
+
+ /* ARITHMETIC INSTRUCTIONS 128-bit
+ ----------------------------------
+ IRRoundingModeDFP(I32) X D128 X D128 -> D128
+ */
+ Iop_AddD128, Iop_SubD128, Iop_MulD128, Iop_DivD128,
+
+ /* SHIFT SIGNIFICAND INSTRUCTIONS
+ * The DFP significand is shifted by the number of digits specified
+ * by the U8 operand. Digits shifted out of the leftmost digit are
+ * lost. Zeros are supplied to the vacated positions on the right.
+ * The sign of the result is the same as the sign of the original
+ * operand.
+ *
+ * D64 x U8 -> D64 left shift and right shift respectively */
+ Iop_ShlD64, Iop_ShrD64,
+
+ /* D128 x U8 -> D128 left shift and right shift respectively */
+ Iop_ShlD128, Iop_ShrD128,
+
+
+ /* FORMAT CONVERSION INSTRUCTIONS
+ * D32 -> D64
+ */
+ Iop_D32toD64,
+
+ /* D64 -> D128 */
+ Iop_D64toD128,
+
+ /* I64S -> D128 */
+ Iop_I64StoD128,
+
+ /* IRRoundingModeDFP(I32) x D64 -> D32 */
+ Iop_D64toD32,
+
+ /* IRRoundingModeDFP(I32) x D128 -> D64 */
+ Iop_D128toD64,
+
+ /* IRRoundingModeDFP(I32) x I64 -> D64 */
+ Iop_I64StoD64,
+
+ /* IRRoundingModeDFP(I32) x D64 -> I64 */
+ Iop_D64toI64S,
+
+ /* IRRoundingModeDFP(I32) x D128 -> I64 */
+ Iop_D128toI64S,
+
+ /* ROUNDING INSTRUCTIONS
+ * IRRoundingMode(I32) x D64 -> D64
+ * The D64 operand, if a finite number, is rounded to an integer value.
+ */
+ Iop_RoundD64toInt,
+
+ /* IRRoundingMode(I32) x D128 -> D128 */
+ Iop_RoundD128toInt,
+
+ /* COMPARE INSTRUCTIONS
+ * D64 x D64 -> IRCmpD64Result(I32) */
+ Iop_CmpD64,
+
+ /* D128 x D128 -> IRCmpD64Result(I32) */
+ Iop_CmpD128,
+
+ /* QUANTIZE AND ROUND INSTRUCTIONS
+ * The source operand is converted and rounded to the form with the
+ * immediate exponent specified by the rounding and exponent parameter.
+ *
+ * The second operand is converted and rounded to the form
+ * of the first operand's exponent and the rounded based on the specified
+ * rounding mode parameter.
+ *
+ * IRRoundingModeDFP(I32) x D64 x D64-> D64 */
+ Iop_QuantizeD64,
+
+ /* IRRoundingModeDFP(I32) x D128 x D128 -> D128 */
+ Iop_QuantizeD128,
+
+ /* IRRoundingModeDFP(I32) x I8 x D64 -> D64
+ * The Decimal Floating point operand is rounded to the requested
+ * significance given by the I8 operand as specified by the rounding
+ * mode.
+ */
+ Iop_SignificanceRoundD64,
+
+ /* IRRoundingModeDFP(I32) x I8 x D128 -> D128 */
+ Iop_SignificanceRoundD128,
+
+ /* EXTRACT AND INSERT INSTRUCTIONS
+ * D64 -> I64
+ * The exponent of the D32 or D64 operand is extracted. The
+ * extracted exponent is converted to a 64-bit signed binary integer.
+ */
+ Iop_ExtractExpD64,
+
+ /* D128 -> I64 */
+ Iop_ExtractExpD128,
+
+ /* I64 x I64 -> D64
+ * The exponent is specified by the first I64 operand the signed
+ * significand is given by the second I64 value. The result is a D64
+ * value consisting of the specified significand and exponent whose
+ * sign is that of the specified significand.
+ */
+ Iop_InsertExpD64,
+
+ /* I64 x I128 -> D128 */
+ Iop_InsertExpD128,
+
+ /* Support for 128-bit DFP type */
+ Iop_D64HLtoD128, Iop_D128HItoD64, Iop_D128LOtoD64,
+
+ /* I64 -> I64
+ * Convert 50-bit densely packed BCD string to 60 bit BCD string
+ */
+ Iop_DPBtoBCD,
+
+ /* I64 -> I64
+ * Convert 60 bit BCD string to 50-bit densely packed BCD string
+ */
+ Iop_BCDtoDPB,
+
+ /* Conversion I64 -> D64 */
+ Iop_ReinterpI64asD64,
+
+ /* Conversion D64 -> I64 */
+ Iop_ReinterpD64asI64,
+
/* ------------------ 128-bit SIMD FP. ------------------ */
/* --- 32x4 vector FP --- */
@@ -1277,10 +1423,52 @@
argR[i] values may only be in the range 0 .. 15, else behaviour
is undefined. */
Iop_Perm8x16,
+ Iop_Perm32x4, /* ditto, except argR values are restricted to 0 .. 3 */
/* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate
See floating-point equiwalents for details. */
- Iop_Recip32x4, Iop_Rsqrte32x4
+ Iop_Recip32x4, Iop_Rsqrte32x4,
+
+ /* ------------------ 256-bit SIMD Integer. ------------------ */
+
+ /* Pack/unpack */
+ Iop_V256to64_0, // V256 -> I64, extract least significant lane
+ Iop_V256to64_1,
+ Iop_V256to64_2,
+ Iop_V256to64_3, // V256 -> I64, extract most significant lane
+
+ Iop_64x4toV256, // (I64,I64,I64,I64)->V256
+ // first arg is most significant lane
+
+ Iop_V256toV128_0, // V256 -> V128, less significant lane
+ Iop_V256toV128_1, // V256 -> V128, more significant lane
+ Iop_V128HLtoV256, // (V128,V128)->V256, first arg is most signif
+
+ Iop_AndV256,
+ Iop_OrV256,
+ Iop_XorV256,
+ Iop_NotV256,
+
+ /* MISC (vector integer cmp != 0) */
+ Iop_CmpNEZ32x8, Iop_CmpNEZ64x4,
+
+ /* ------------------ 256-bit SIMD FP. ------------------ */
+ Iop_Add64Fx4,
+ Iop_Sub64Fx4,
+ Iop_Mul64Fx4,
+ Iop_Div64Fx4,
+ Iop_Add32Fx8,
+ Iop_Sub32Fx8,
+ Iop_Mul32Fx8,
+ Iop_Div32Fx8,
+
+ Iop_Sqrt32Fx8,
+ Iop_Sqrt64Fx4,
+ Iop_RSqrt32Fx8,
+ Iop_Recip32Fx8,
+
+ Iop_Max32Fx8, Iop_Min32Fx8,
+ Iop_Max64Fx4, Iop_Min64Fx4
}
IROp;
@@ -1301,6 +1489,27 @@
}
IRRoundingMode;
+/* DFP encoding of IEEE754 2008 specified rounding modes extends the two bit
+ * binary floating point rounding mode (IRRoundingMode) to three bits. The
+ * DFP rounding modes are a super set of the binary rounding modes. The
+ * encoding was chosen such that the mapping of the least significant two bits
+ * of the IR to POWER encodings is same. The upper IR encoding bit is just
+ * a logical OR of the upper rounding mode bit from the POWER encoding.
+ */
+typedef
+ enum {
+ Irrm_DFP_NEAREST = 0, // Round to nearest, ties to even
+ Irrm_DFP_NegINF = 1, // Round to negative infinity
+ Irrm_DFP_PosINF = 2, // Round to posative infinity
+ Irrm_DFP_ZERO = 3, // Round toward zero
+ Irrm_DFP_NEAREST_TIE_AWAY_0 = 4, // Round to nearest, ties away from 0
+ Irrm_DFP_PREPARE_SHORTER = 5, // Round to prepare for storter
+ // precision
+ Irrm_DFP_AWAY_FROM_ZERO = 6, // Round to away from 0
+ Irrm_DFP_NEAREST_TIE_TOWARD_0 = 7 // Round to nearest, ties towards 0
+ }
+ IRRoundingModeDFP;
+
/* Floating point comparison result values, as created by Iop_CmpF64.
This is also derived from what IA32 does. */
typedef
@@ -1317,6 +1526,10 @@
/* ------------------ Expressions ------------------ */
+typedef struct _IRQop IRQop; /* forward declaration */
+typedef struct _IRTriop IRTriop; /* forward declaration */
+
+
/* The different kinds of expressions. Their meaning is explained below
in the comments for IRExpr. */
typedef
@@ -1420,11 +1633,7 @@
eg. MAddF64r32(t1, t2, t3, t4)
*/
struct {
- IROp op; /* op-code */
- IRExpr* arg1; /* operand 1 */
- IRExpr* arg2; /* operand 2 */
- IRExpr* arg3; /* operand 3 */
- IRExpr* arg4; /* operand 4 */
+ IRQop* details;
} Qop;
/* A ternary operation.
@@ -1432,10 +1641,7 @@
eg. MulF64(1, 2.0, 3.0)
*/
struct {
- IROp op; /* op-code */
- IRExpr* arg1; /* operand 1 */
- IRExpr* arg2; /* operand 2 */
- IRExpr* arg3; /* operand 3 */
+ IRTriop* details;
} Triop;
/* A binary operation.
@@ -1499,6 +1705,9 @@
* it may not access guest memory, since that would hide
guest memory transactions from the instrumenters
+ * it must not assume that arguments are being evaluated in a
+ particular order. The oder of evaluation is unspecified.
+
This is restrictive, but makes the semantics clean, and does
not interfere with IR optimisation.
@@ -1534,6 +1743,23 @@
} Iex;
};
+/* ------------------ A ternary expression ---------------------- */
+struct _IRTriop {
+ IROp op; /* op-code */
+ IRExpr* arg1; /* operand 1 */
+ IRExpr* arg2; /* operand 2 */
+ IRExpr* arg3; /* operand 3 */
+};
+
+/* ------------------ A quarternary expression ------------------ */
+struct _IRQop {
+ IROp op; /* op-code */
+ IRExpr* arg1; /* operand 1 */
+ IRExpr* arg2; /* operand 2 */
+ IRExpr* arg3; /* operand 3 */
+ IRExpr* arg4; /* operand 4 */
+};
+
/* Expression constructors. */
extern IRExpr* IRExpr_Binder ( Int binder );
extern IRExpr* IRExpr_Get ( Int off, IRType ty );
@@ -1629,14 +1855,13 @@
guest to restart a syscall that has been interrupted by a signal.
*/
typedef
- enum {
- Ijk_Boring=0x16000, /* not interesting; just goto next */
+ enum {
+ Ijk_INVALID=0x16000,
+ Ijk_Boring, /* not interesting; just goto next */
Ijk_Call, /* guest is doing a call */
Ijk_Ret, /* guest is doing a return */
Ijk_ClientReq, /* do guest client req before continuing */
Ijk_Yield, /* client is yielding to thread scheduler */
- Ijk_YieldNoRedir, /* client is yielding to thread scheduler AND jump to
- un-redirected guest addr */
Ijk_EmWarn, /* report emulation warning before continuing */
Ijk_EmFail, /* emulation critical (FATAL) error; give up */
Ijk_NoDecode, /* next instruction cannot be decoded */
@@ -1653,7 +1878,7 @@
Ijk_Sys_int128, /* amd64/x86 'int $0x80' */
Ijk_Sys_int129, /* amd64/x86 'int $0x81' */
Ijk_Sys_int130, /* amd64/x86 'int $0x82' */
- Ijk_Sys_sysenter /* x86 'sysenter'. guest_EIP becomes
+ Ijk_Sys_sysenter /* x86 'sysenter'. guest_EIP becomes
invalid at the point this happens. */
}
IRJumpKind;
@@ -1698,9 +1923,9 @@
call does not access guest state.
IMPORTANT NOTE re GUARDS: Dirty calls are strict, very strict. The
- arguments are evaluated REGARDLESS of the guard value. It is
- unspecified the relative order of arg evaluation and guard
- evaluation.
+ arguments are evaluated REGARDLESS of the guard value. The order of
+ argument evaluation is unspecified. The guard expression is evaluated
+ AFTER the arguments have been evaluated.
*/
#define VEX_N_FXSTATE 7 /* enough for FXSAVE/FXRSTOR on x86 */
@@ -1708,7 +1933,7 @@
/* Effects on resources (eg. registers, memory locations) */
typedef
enum {
- Ifx_None = 0x17000, /* no effect */
+ Ifx_None = 0x1700, /* no effect */
Ifx_Read, /* reads the resource */
Ifx_Write, /* writes the resource */
Ifx_Modify, /* modifies the resource */
@@ -1720,8 +1945,13 @@
typedef
- struct {
- /* What to call, and details of args/results */
+ struct _IRDirty {
+ /* What to call, and details of args/results. .guard must be
+ non-NULL. If .tmp is not IRTemp_INVALID (that is, the call
+ returns a result) then .guard must be demonstrably (at
+ JIT-time) always true, that is, the call must be
+ unconditional. Conditional calls that assign .tmp are not
+ allowed. */
IRCallee* cee; /* where to call */
IRExpr* guard; /* :: Ity_Bit. Controls whether call happens */
IRExpr** args; /* arg list, ends in NULL */
@@ -1736,10 +1966,26 @@
Bool needsBBP; /* True => also pass guest state ptr to callee */
Int nFxState; /* must be 0 .. VEX_N_FXSTATE */
struct {
- IREffect fx; /* read, write or modify? Ifx_None is invalid. */
- Int offset;
- Int size;
+ IREffect fx:16; /* read, write or modify? Ifx_None is invalid. */
+ UShort offset;
+ UShort size;
+ UChar nRepeats;
+ UChar repeatLen;
} fxState[VEX_N_FXSTATE];
+ /* The access can be repeated, as specified by nRepeats and
+ repeatLen. To describe only a single access, nRepeats and
+ repeatLen should be zero. Otherwise, repeatLen must be a
+ multiple of size and greater than size. */
+ /* Overall, the parts of the guest state denoted by (offset,
+ size, nRepeats, repeatLen) is
+ [offset, +size)
+ and, if nRepeats > 0,
+ for (i = 1; i <= nRepeats; i++)
+ [offset + i * repeatLen, +size)
+ A convenient way to enumerate all segments is therefore
+ for (i = 0; i < 1 + nRepeats; i++)
+ [offset + i * repeatLen, +size)
+ */
}
IRDirty;
@@ -1872,6 +2118,24 @@
extern IRCAS* deepCopyIRCAS ( IRCAS* );
+
+/* ------------------ Circular Array Put ------------------ */
+typedef
+ struct {
+ IRRegArray* descr; /* Part of guest state treated as circular */
+ IRExpr* ix; /* Variable part of index into array */
+ Int bias; /* Constant offset part of index into array */
+ IRExpr* data; /* The value to write */
+ } IRPutI;
+
+extern void ppIRPutI ( IRPutI* puti );
+
+extern IRPutI* mkIRPutI ( IRRegArray* descr, IRExpr* ix,
+ Int bias, IRExpr* data );
+
+extern IRPutI* deepCopyIRPutI ( IRPutI* );
+
+
/* ------------------ Statements ------------------ */
/* The different kinds of statements. Their meaning is explained
@@ -1987,10 +2251,7 @@
eg. PUTI(64:8xF64)[t5,0] = t1
*/
struct {
- IRRegArray* descr; /* Part of guest state treated as circular */
- IRExpr* ix; /* Variable part of index into array */
- Int bias; /* Constant offset part of index into array */
- IRExpr* data; /* The value to write */
+ IRPutI* details;
} PutI;
/* Assign a value to a temporary. Note that SSA rules require
@@ -2113,11 +2374,15 @@
/* Conditional exit from the middle of an IRSB.
ppIRStmt output: if (<guard>) goto {<jk>} <dst>
eg. if (t69) goto {Boring} 0x4000AAA:I32
+ If <guard> is true, the guest state is also updated by
+ PUT-ing <dst> at <offsIP>. This is done because a
+ taken exit must update the guest program counter.
*/
struct {
IRExpr* guard; /* Conditional expression */
- IRJumpKind jk; /* Jump kind */
IRConst* dst; /* Jump target (constant only) */
+ IRJumpKind jk; /* Jump kind */
+ Int offsIP; /* Guest state offset for IP */
} Exit;
} Ist;
}
@@ -2128,8 +2393,7 @@
extern IRStmt* IRStmt_IMark ( Addr64 addr, Int len, UChar delta );
extern IRStmt* IRStmt_AbiHint ( IRExpr* base, Int len, IRExpr* nia );
extern IRStmt* IRStmt_Put ( Int off, IRExpr* data );
-extern IRStmt* IRStmt_PutI ( IRRegArray* descr, IRExpr* ix, Int bias,
- IRExpr* data );
+extern IRStmt* IRStmt_PutI ( IRPutI* details );
extern IRStmt* IRStmt_WrTmp ( IRTemp tmp, IRExpr* data );
extern IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* data );
extern IRStmt* IRStmt_CAS ( IRCAS* details );
@@ -2137,7 +2401,8 @@
IRExpr* addr, IRExpr* storedata );
extern IRStmt* IRStmt_Dirty ( IRDirty* details );
extern IRStmt* IRStmt_MBE ( IRMBusEvent event );
-extern IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* dst );
+extern IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* dst,
+ Int offsIP );
/* Deep-copy an IRStmt. */
extern IRStmt* deepCopyIRStmt ( IRStmt* );
@@ -2182,6 +2447,8 @@
executes all the way to the end, without a side exit
- An indication of any special actions (JumpKind) needed
for this final jump.
+ - Offset of the IP field in the guest state. This will be
+ updated before the final jump is done.
"IRSB" stands for "IR Super Block".
*/
@@ -2193,6 +2460,7 @@
Int stmts_used;
IRExpr* next;
IRJumpKind jumpkind;
+ Int offsIP;
}
IRSB;
diff --git a/main/VEX/pub/libvex_s390x_common.h b/main/VEX/pub/libvex_s390x_common.h
index 95efef6..332cca5 100644
--- a/main/VEX/pub/libvex_s390x_common.h
+++ b/main/VEX/pub/libvex_s390x_common.h
@@ -1,3 +1,4 @@
+/* -*- mode: C; c-basic-offset: 3; -*- */
/*--------------------------------------------------------------------*/
/*--- Common defs for s390x libvex_s390x_common.h ---*/
@@ -7,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -27,8 +28,6 @@
The GNU General Public License is contained in the file COPYING.
*/
-/* -*- mode: C; c-basic-offset: 3; -*- */
-
#ifndef __LIBVEX_PUB_S390X_H
#define __LIBVEX_PUB_S390X_H
@@ -42,7 +41,7 @@
/*--------------------------------------------------------------*/
#define S390_REGNO_RETURN_VALUE 2
-#define S390_REGNO_DISPATCH_CTR 12 /* Holds VG_(dispatch_ctr) */
+#define S390_REGNO_TCHAIN_SCRATCH 12
#define S390_REGNO_GUEST_STATE_POINTER 13
#define S390_REGNO_LINK_REGISTER 14
#define S390_REGNO_STACK_POINTER 15
@@ -52,7 +51,7 @@
/*--- Offsets in the stack frame allocated by the dispatcher ---*/
/*--------------------------------------------------------------*/
-/* Where the profiling dispatcher saves the r2 contents. */
+/* Where the dispatcher saves the r2 contents. */
#define S390_OFFSET_SAVED_R2 160+96
/* Where client's FPC register is saved. */
@@ -64,18 +63,15 @@
/* Where client code will save the link register before calling a helper. */
#define S390_OFFSET_SAVED_LR 160+72
-/* Location of saved guest state pointer */
-#define S390_OFFSET_SAVED_GSP 160+64
-
-/* Size of frame allocated by VG_(run_innerloop)
+/* Size of frame allocated by VG_(disp_run_translations)
Need size for
8 FPRs
- + 3 GPRs (SAVED_GSP, SAVED_LR, and SAVED_R2)
+ + 2 GPRs (SAVED_LR, and SAVED_R2)
+ 2 FPCs (SAVED_FPC_C and SAVED_FPC_V).
Additionally, we need a standard frame for helper functions being called
from client code. (See figure 1-16 in zSeries ABI) */
-#define S390_INNERLOOP_FRAME_SIZE ((8+3+2)*8 + 160)
+#define S390_INNERLOOP_FRAME_SIZE ((8+2+2)*8 + 160)
/*--------------------------------------------------------------*/
diff --git a/main/VEX/pub/libvex_trc_values.h b/main/VEX/pub/libvex_trc_values.h
index d983455..688f28e 100644
--- a/main/VEX/pub/libvex_trc_values.h
+++ b/main/VEX/pub/libvex_trc_values.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2011 OpenWorks LLP
+ Copyright (C) 2004-2012 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -69,9 +69,6 @@
#define VEX_TRC_JMP_CLIENTREQ 65 /* do a client req before continuing */
#define VEX_TRC_JMP_YIELD 67 /* yield to thread sched
before continuing */
-#define VEX_TRC_JMP_YIELD_NOREDIR 111 /* yield to thread sched before
- continuing AND jump to undirected
- guest addr */
#define VEX_TRC_JMP_NODECODE 69 /* next instruction is not decodable */
#define VEX_TRC_JMP_MAPFAIL 71 /* address translation failed */
@@ -83,6 +80,9 @@
#define VEX_TRC_JMP_SYS_SYSENTER 79 /* do syscall before continuing */
+#define VEX_TRC_JMP_BORING 95 /* return to sched, but just
+ keep going; no special action */
+
#endif /* ndef __LIBVEX_TRC_VALUES_H */
/*---------------------------------------------------------------*/
diff --git a/main/cachegrind/Makefile.am b/main/cachegrind/Makefile.am
index 0b6879c..f22fe17 100644
--- a/main/cachegrind/Makefile.am
+++ b/main/cachegrind/Makefile.am
@@ -46,7 +46,8 @@
cg-ppc32.c \
cg-ppc64.c \
cg-arm.c \
- cg-s390x.c
+ cg-s390x.c \
+ cg-mips32.c
cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
$(CACHEGRIND_SOURCES_COMMON)
diff --git a/main/cachegrind/Makefile.in b/main/cachegrind/Makefile.in
new file mode 100644
index 0000000..4552e0d
--- /dev/null
+++ b/main/cachegrind/Makefile.in
@@ -0,0 +1,1460 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(srcdir)/cg_annotate.in \
+ $(srcdir)/cg_diff.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+
+# On Android we must ask for non-executable stack, not sure why.
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_2 = -Wl,-z,noexecstack
+bin_PROGRAMS = cg_merge$(EXEEXT)
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_3 = -Wl,-read_only_relocs -Wl,suppress
+noinst_PROGRAMS = cachegrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
+ $(am__EXEEXT_1)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = cachegrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
+subdir = cachegrind
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES = cg_annotate cg_diff
+CONFIG_CLEAN_VPATH_FILES =
+am__installdirs = "$(DESTDIR)$(bindir)" "$(DESTDIR)$(bindir)"
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = cachegrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+PROGRAMS = $(bin_PROGRAMS) $(noinst_PROGRAMS)
+am__objects_1 = \
+ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.$(OBJEXT)
+am_cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = \
+ $(am__objects_1)
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = \
+ $(am_cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
+am__cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = cg_main.c \
+ cg-arch.c cg-x86-amd64.c cg-ppc32.c cg-ppc64.c cg-arm.c \
+ cg-s390x.c cg-mips32.c
+am__objects_2 = \
+ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.$(OBJEXT) \
+ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_2)
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+ $(am_cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
+am_cg_merge_OBJECTS = cg_merge-cg_merge.$(OBJEXT)
+cg_merge_OBJECTS = $(am_cg_merge_OBJECTS)
+cg_merge_LDADD = $(LDADD)
+cg_merge_LINK = $(CCLD) $(cg_merge_CFLAGS) $(CFLAGS) \
+ $(cg_merge_LDFLAGS) $(LDFLAGS) -o $@
+am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
+am__vpath_adj = case $$p in \
+ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
+ *) f=$$p;; \
+ esac;
+am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;
+am__install_max = 40
+am__nobase_strip_setup = \
+ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`
+am__nobase_strip = \
+ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"
+am__nobase_list = $(am__nobase_strip_setup); \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \
+ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \
+ if (++n[$$2] == $(am__install_max)) \
+ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \
+ END { for (dir in files) print dir, files[dir] }'
+am__base_list = \
+ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \
+ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'
+SCRIPTS = $(bin_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES) \
+ $(cg_merge_SOURCES)
+DIST_SOURCES = $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(am__cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST) \
+ $(cg_merge_SOURCES)
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+HEADERS = $(noinst_HEADERS)
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DIST_SUBDIRS = $(SUBDIRS)
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+SUBDIRS = . tests
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+#----------------------------------------------------------------------------
+# <tool>-<platform> stuff
+#----------------------------------------------------------------------------
+TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+
+TOOL_LDADD_COMMON = -lgcc
+TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) $(TOOL_LDADD_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
+
+
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+ -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_X86_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_AMD64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_PPC32_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_PPC64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_ARM_LINUX = $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
+ $(am__append_2)
+TOOL_LDFLAGS_S390X_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_X86_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386
+
+TOOL_LDFLAGS_AMD64_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+
+
+# MIPS Linux default start symbol is __start, not _start like on x86 or amd
+TOOL_LDFLAGS_MIPS32_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
+ @FLAG_M32@
+
+
+# NB for 64-bit darwin. We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them). Although such setting is probably
+# better done in link_tool_exe.c.
+#
+# -Wl,-pagezero_size,0x100000000
+
+#----------------------------------------------------------------------------
+# vgpreload_<tool>-<platform>.a stuff
+#----------------------------------------------------------------------------
+LIBREPLACEMALLOC_X86_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-linux.a
+
+LIBREPLACEMALLOC_AMD64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-linux.a
+
+LIBREPLACEMALLOC_PPC32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a
+
+LIBREPLACEMALLOC_PPC64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a
+
+LIBREPLACEMALLOC_ARM_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a
+
+LIBREPLACEMALLOC_X86_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-darwin.a
+
+LIBREPLACEMALLOC_AMD64_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-darwin.a
+
+LIBREPLACEMALLOC_S390X_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-s390x-linux.a
+
+LIBREPLACEMALLOC_MIPS32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips32-linux.a
+
+LIBREPLACEMALLOC_LDFLAGS_X86_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_X86_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_AMD64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC32_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_ARM_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_X86_DARWIN = \
+ $(LIBREPLACEMALLOC_X86_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_DARWIN = \
+ $(LIBREPLACEMALLOC_AMD64_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_S390X_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_S390X_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_MIPS32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_MIPS32_LINUX) \
+ -Wl,--no-whole-archive
+
+EXTRA_DIST = \
+ docs/cg-manual.xml \
+ docs/cg_annotate-manpage.xml
+
+
+#----------------------------------------------------------------------------
+# Headers, etc
+#----------------------------------------------------------------------------
+bin_SCRIPTS = cg_annotate cg_diff
+noinst_HEADERS = \
+ cg_arch.h \
+ cg_branchpred.c \
+ cg_sim.c
+
+cg_merge_SOURCES = cg_merge.c
+cg_merge_CPPFLAGS = $(AM_CPPFLAGS_PRI)
+cg_merge_CFLAGS = $(AM_CFLAGS_PRI)
+cg_merge_CCASFLAGS = $(AM_CCASFLAGS_PRI)
+cg_merge_LDFLAGS = $(AM_CFLAGS_PRI) $(am__append_3)
+CACHEGRIND_SOURCES_COMMON = \
+ cg_main.c \
+ cg-arch.c \
+ cg-x86-amd64.c \
+ cg-ppc32.c \
+ cg-ppc64.c \
+ cg-arm.c \
+ cg-s390x.c \
+ cg-mips32.c
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+ $(CACHEGRIND_SOURCES_COMMON)
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@)
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
+ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
+ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+ @VALT_LOAD_ADDRESS_PRI@ \
+ $(LINK) \
+ $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+ $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(CACHEGRIND_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign cachegrind/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign cachegrind/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+cg_annotate: $(top_builddir)/config.status $(srcdir)/cg_annotate.in
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+cg_diff: $(top_builddir)/config.status $(srcdir)/cg_diff.in
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+install-binPROGRAMS: $(bin_PROGRAMS)
+ @$(NORMAL_INSTALL)
+ test -z "$(bindir)" || $(MKDIR_P) "$(DESTDIR)$(bindir)"
+ @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed 's/$(EXEEXT)$$//' | \
+ while read p p1; do if test -f $$p; \
+ then echo "$$p"; echo "$$p"; else :; fi; \
+ done | \
+ sed -e 'p;s,.*/,,;n;h' -e 's|.*|.|' \
+ -e 'p;x;s,.*/,,;s/$(EXEEXT)$$//;$(transform);s/$$/$(EXEEXT)/' | \
+ sed 'N;N;N;s,\n, ,g' | \
+ $(AWK) 'BEGIN { files["."] = ""; dirs["."] = 1 } \
+ { d=$$3; if (dirs[d] != 1) { print "d", d; dirs[d] = 1 } \
+ if ($$2 == $$4) files[d] = files[d] " " $$1; \
+ else { print "f", $$3 "/" $$4, $$1; } } \
+ END { for (d in files) print "f", d, files[d] }' | \
+ while read type dir files; do \
+ if test "$$dir" = .; then dir=; else dir=/$$dir; fi; \
+ test -z "$$files" || { \
+ echo " $(INSTALL_PROGRAM_ENV) $(INSTALL_PROGRAM) $$files '$(DESTDIR)$(bindir)$$dir'"; \
+ $(INSTALL_PROGRAM_ENV) $(INSTALL_PROGRAM) $$files "$(DESTDIR)$(bindir)$$dir" || exit $$?; \
+ } \
+ ; done
+
+uninstall-binPROGRAMS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \
+ files=`for p in $$list; do echo "$$p"; done | \
+ sed -e 'h;s,^.*/,,;s/$(EXEEXT)$$//;$(transform)' \
+ -e 's/$$/$(EXEEXT)/' `; \
+ test -n "$$list" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(bindir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(bindir)" && rm -f $$files
+
+clean-binPROGRAMS:
+ -test -z "$(bin_PROGRAMS)" || rm -f $(bin_PROGRAMS)
+
+clean-noinstPROGRAMS:
+ -test -z "$(noinst_PROGRAMS)" || rm -f $(noinst_PROGRAMS)
+cachegrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT): $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f cachegrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT)
+ $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD) $(LIBS)
+cachegrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT): $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f cachegrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+ $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD) $(LIBS)
+cg_merge$(EXEEXT): $(cg_merge_OBJECTS) $(cg_merge_DEPENDENCIES)
+ @rm -f cg_merge$(EXEEXT)
+ $(cg_merge_LINK) $(cg_merge_OBJECTS) $(cg_merge_LDADD) $(LIBS)
+install-binSCRIPTS: $(bin_SCRIPTS)
+ @$(NORMAL_INSTALL)
+ test -z "$(bindir)" || $(MKDIR_P) "$(DESTDIR)$(bindir)"
+ @list='$(bin_SCRIPTS)'; test -n "$(bindir)" || list=; \
+ for p in $$list; do \
+ if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+ if test -f "$$d$$p"; then echo "$$d$$p"; echo "$$p"; else :; fi; \
+ done | \
+ sed -e 'p;s,.*/,,;n' \
+ -e 'h;s|.*|.|' \
+ -e 'p;x;s,.*/,,;$(transform)' | sed 'N;N;N;s,\n, ,g' | \
+ $(AWK) 'BEGIN { files["."] = ""; dirs["."] = 1; } \
+ { d=$$3; if (dirs[d] != 1) { print "d", d; dirs[d] = 1 } \
+ if ($$2 == $$4) { files[d] = files[d] " " $$1; \
+ if (++n[d] == $(am__install_max)) { \
+ print "f", d, files[d]; n[d] = 0; files[d] = "" } } \
+ else { print "f", d "/" $$4, $$1 } } \
+ END { for (d in files) print "f", d, files[d] }' | \
+ while read type dir files; do \
+ if test "$$dir" = .; then dir=; else dir=/$$dir; fi; \
+ test -z "$$files" || { \
+ echo " $(INSTALL_SCRIPT) $$files '$(DESTDIR)$(bindir)$$dir'"; \
+ $(INSTALL_SCRIPT) $$files "$(DESTDIR)$(bindir)$$dir" || exit $$?; \
+ } \
+ ; done
+
+uninstall-binSCRIPTS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(bin_SCRIPTS)'; test -n "$(bindir)" || exit 0; \
+ files=`for p in $$list; do echo "$$p"; done | \
+ sed -e 's,.*/,,;$(transform)'`; \
+ test -n "$$list" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(bindir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(bindir)" && rm -f $$files
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cg_merge-cg_merge.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.o: cg_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.o `test -f 'cg_main.c' || echo '$(srcdir)/'`cg_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg_main.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.o `test -f 'cg_main.c' || echo '$(srcdir)/'`cg_main.c
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.obj: cg_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.obj `if test -f 'cg_main.c'; then $(CYGPATH_W) 'cg_main.c'; else $(CYGPATH_W) '$(srcdir)/cg_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg_main.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg_main.obj `if test -f 'cg_main.c'; then $(CYGPATH_W) 'cg_main.c'; else $(CYGPATH_W) '$(srcdir)/cg_main.c'; fi`
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o: cg-arch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o `test -f 'cg-arch.c' || echo '$(srcdir)/'`cg-arch.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-arch.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o `test -f 'cg-arch.c' || echo '$(srcdir)/'`cg-arch.c
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj: cg-arch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj `if test -f 'cg-arch.c'; then $(CYGPATH_W) 'cg-arch.c'; else $(CYGPATH_W) '$(srcdir)/cg-arch.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-arch.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj `if test -f 'cg-arch.c'; then $(CYGPATH_W) 'cg-arch.c'; else $(CYGPATH_W) '$(srcdir)/cg-arch.c'; fi`
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o: cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o `test -f 'cg-x86-amd64.c' || echo '$(srcdir)/'`cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-x86-amd64.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o `test -f 'cg-x86-amd64.c' || echo '$(srcdir)/'`cg-x86-amd64.c
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj: cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj `if test -f 'cg-x86-amd64.c'; then $(CYGPATH_W) 'cg-x86-amd64.c'; else $(CYGPATH_W) '$(srcdir)/cg-x86-amd64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-x86-amd64.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj `if test -f 'cg-x86-amd64.c'; then $(CYGPATH_W) 'cg-x86-amd64.c'; else $(CYGPATH_W) '$(srcdir)/cg-x86-amd64.c'; fi`
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o: cg-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o `test -f 'cg-ppc32.c' || echo '$(srcdir)/'`cg-ppc32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-ppc32.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o `test -f 'cg-ppc32.c' || echo '$(srcdir)/'`cg-ppc32.c
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj: cg-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj `if test -f 'cg-ppc32.c'; then $(CYGPATH_W) 'cg-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/cg-ppc32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-ppc32.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj `if test -f 'cg-ppc32.c'; then $(CYGPATH_W) 'cg-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/cg-ppc32.c'; fi`
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o: cg-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o `test -f 'cg-ppc64.c' || echo '$(srcdir)/'`cg-ppc64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-ppc64.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o `test -f 'cg-ppc64.c' || echo '$(srcdir)/'`cg-ppc64.c
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj: cg-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj `if test -f 'cg-ppc64.c'; then $(CYGPATH_W) 'cg-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/cg-ppc64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-ppc64.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj `if test -f 'cg-ppc64.c'; then $(CYGPATH_W) 'cg-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/cg-ppc64.c'; fi`
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o: cg-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o `test -f 'cg-arm.c' || echo '$(srcdir)/'`cg-arm.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-arm.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o `test -f 'cg-arm.c' || echo '$(srcdir)/'`cg-arm.c
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj: cg-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj `if test -f 'cg-arm.c'; then $(CYGPATH_W) 'cg-arm.c'; else $(CYGPATH_W) '$(srcdir)/cg-arm.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-arm.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj `if test -f 'cg-arm.c'; then $(CYGPATH_W) 'cg-arm.c'; else $(CYGPATH_W) '$(srcdir)/cg-arm.c'; fi`
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o: cg-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o `test -f 'cg-s390x.c' || echo '$(srcdir)/'`cg-s390x.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-s390x.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o `test -f 'cg-s390x.c' || echo '$(srcdir)/'`cg-s390x.c
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj: cg-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj `if test -f 'cg-s390x.c'; then $(CYGPATH_W) 'cg-s390x.c'; else $(CYGPATH_W) '$(srcdir)/cg-s390x.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-s390x.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj `if test -f 'cg-s390x.c'; then $(CYGPATH_W) 'cg-s390x.c'; else $(CYGPATH_W) '$(srcdir)/cg-s390x.c'; fi`
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o: cg-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o `test -f 'cg-mips32.c' || echo '$(srcdir)/'`cg-mips32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-mips32.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o `test -f 'cg-mips32.c' || echo '$(srcdir)/'`cg-mips32.c
+
+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj: cg-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Tpo -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj `if test -f 'cg-mips32.c'; then $(CYGPATH_W) 'cg-mips32.c'; else $(CYGPATH_W) '$(srcdir)/cg-mips32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-mips32.c' object='cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj `if test -f 'cg-mips32.c'; then $(CYGPATH_W) 'cg-mips32.c'; else $(CYGPATH_W) '$(srcdir)/cg-mips32.c'; fi`
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.o: cg_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.o `test -f 'cg_main.c' || echo '$(srcdir)/'`cg_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg_main.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.o `test -f 'cg_main.c' || echo '$(srcdir)/'`cg_main.c
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.obj: cg_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.obj `if test -f 'cg_main.c'; then $(CYGPATH_W) 'cg_main.c'; else $(CYGPATH_W) '$(srcdir)/cg_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg_main.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg_main.obj `if test -f 'cg_main.c'; then $(CYGPATH_W) 'cg_main.c'; else $(CYGPATH_W) '$(srcdir)/cg_main.c'; fi`
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o: cg-arch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o `test -f 'cg-arch.c' || echo '$(srcdir)/'`cg-arch.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-arch.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o `test -f 'cg-arch.c' || echo '$(srcdir)/'`cg-arch.c
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj: cg-arch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj `if test -f 'cg-arch.c'; then $(CYGPATH_W) 'cg-arch.c'; else $(CYGPATH_W) '$(srcdir)/cg-arch.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-arch.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj `if test -f 'cg-arch.c'; then $(CYGPATH_W) 'cg-arch.c'; else $(CYGPATH_W) '$(srcdir)/cg-arch.c'; fi`
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o: cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o `test -f 'cg-x86-amd64.c' || echo '$(srcdir)/'`cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-x86-amd64.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o `test -f 'cg-x86-amd64.c' || echo '$(srcdir)/'`cg-x86-amd64.c
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj: cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj `if test -f 'cg-x86-amd64.c'; then $(CYGPATH_W) 'cg-x86-amd64.c'; else $(CYGPATH_W) '$(srcdir)/cg-x86-amd64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-x86-amd64.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj `if test -f 'cg-x86-amd64.c'; then $(CYGPATH_W) 'cg-x86-amd64.c'; else $(CYGPATH_W) '$(srcdir)/cg-x86-amd64.c'; fi`
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o: cg-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o `test -f 'cg-ppc32.c' || echo '$(srcdir)/'`cg-ppc32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-ppc32.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o `test -f 'cg-ppc32.c' || echo '$(srcdir)/'`cg-ppc32.c
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj: cg-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj `if test -f 'cg-ppc32.c'; then $(CYGPATH_W) 'cg-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/cg-ppc32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-ppc32.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj `if test -f 'cg-ppc32.c'; then $(CYGPATH_W) 'cg-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/cg-ppc32.c'; fi`
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o: cg-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o `test -f 'cg-ppc64.c' || echo '$(srcdir)/'`cg-ppc64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-ppc64.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o `test -f 'cg-ppc64.c' || echo '$(srcdir)/'`cg-ppc64.c
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj: cg-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj `if test -f 'cg-ppc64.c'; then $(CYGPATH_W) 'cg-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/cg-ppc64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-ppc64.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj `if test -f 'cg-ppc64.c'; then $(CYGPATH_W) 'cg-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/cg-ppc64.c'; fi`
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o: cg-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o `test -f 'cg-arm.c' || echo '$(srcdir)/'`cg-arm.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-arm.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o `test -f 'cg-arm.c' || echo '$(srcdir)/'`cg-arm.c
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj: cg-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj `if test -f 'cg-arm.c'; then $(CYGPATH_W) 'cg-arm.c'; else $(CYGPATH_W) '$(srcdir)/cg-arm.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-arm.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj `if test -f 'cg-arm.c'; then $(CYGPATH_W) 'cg-arm.c'; else $(CYGPATH_W) '$(srcdir)/cg-arm.c'; fi`
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o: cg-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o `test -f 'cg-s390x.c' || echo '$(srcdir)/'`cg-s390x.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-s390x.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o `test -f 'cg-s390x.c' || echo '$(srcdir)/'`cg-s390x.c
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj: cg-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj `if test -f 'cg-s390x.c'; then $(CYGPATH_W) 'cg-s390x.c'; else $(CYGPATH_W) '$(srcdir)/cg-s390x.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-s390x.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj `if test -f 'cg-s390x.c'; then $(CYGPATH_W) 'cg-s390x.c'; else $(CYGPATH_W) '$(srcdir)/cg-s390x.c'; fi`
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o: cg-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o `test -f 'cg-mips32.c' || echo '$(srcdir)/'`cg-mips32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-mips32.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o `test -f 'cg-mips32.c' || echo '$(srcdir)/'`cg-mips32.c
+
+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj: cg-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj -MD -MP -MF $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Tpo -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj `if test -f 'cg-mips32.c'; then $(CYGPATH_W) 'cg-mips32.c'; else $(CYGPATH_W) '$(srcdir)/cg-mips32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Tpo $(DEPDIR)/cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg-mips32.c' object='cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj `if test -f 'cg-mips32.c'; then $(CYGPATH_W) 'cg-mips32.c'; else $(CYGPATH_W) '$(srcdir)/cg-mips32.c'; fi`
+
+cg_merge-cg_merge.o: cg_merge.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cg_merge_CPPFLAGS) $(CPPFLAGS) $(cg_merge_CFLAGS) $(CFLAGS) -MT cg_merge-cg_merge.o -MD -MP -MF $(DEPDIR)/cg_merge-cg_merge.Tpo -c -o cg_merge-cg_merge.o `test -f 'cg_merge.c' || echo '$(srcdir)/'`cg_merge.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cg_merge-cg_merge.Tpo $(DEPDIR)/cg_merge-cg_merge.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg_merge.c' object='cg_merge-cg_merge.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cg_merge_CPPFLAGS) $(CPPFLAGS) $(cg_merge_CFLAGS) $(CFLAGS) -c -o cg_merge-cg_merge.o `test -f 'cg_merge.c' || echo '$(srcdir)/'`cg_merge.c
+
+cg_merge-cg_merge.obj: cg_merge.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cg_merge_CPPFLAGS) $(CPPFLAGS) $(cg_merge_CFLAGS) $(CFLAGS) -MT cg_merge-cg_merge.obj -MD -MP -MF $(DEPDIR)/cg_merge-cg_merge.Tpo -c -o cg_merge-cg_merge.obj `if test -f 'cg_merge.c'; then $(CYGPATH_W) 'cg_merge.c'; else $(CYGPATH_W) '$(srcdir)/cg_merge.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cg_merge-cg_merge.Tpo $(DEPDIR)/cg_merge-cg_merge.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cg_merge.c' object='cg_merge-cg_merge.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(cg_merge_CPPFLAGS) $(CPPFLAGS) $(cg_merge_CFLAGS) $(CFLAGS) -c -o cg_merge-cg_merge.obj `if test -f 'cg_merge.c'; then $(CYGPATH_W) 'cg_merge.c'; else $(CYGPATH_W) '$(srcdir)/cg_merge.c'; fi`
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+check: check-recursive
+all-am: Makefile $(PROGRAMS) $(SCRIPTS) $(HEADERS) all-local
+installdirs: installdirs-recursive
+installdirs-am:
+ for dir in "$(DESTDIR)$(bindir)" "$(DESTDIR)$(bindir)"; do \
+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ done
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-binPROGRAMS clean-generic clean-local \
+ clean-noinstPROGRAMS mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am: install-binPROGRAMS install-binSCRIPTS \
+ install-exec-local
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am: uninstall-binPROGRAMS uninstall-binSCRIPTS
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+ install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am all-local check check-am clean clean-binPROGRAMS \
+ clean-generic clean-local clean-noinstPROGRAMS ctags \
+ ctags-recursive distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-binPROGRAMS install-binSCRIPTS \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-exec-local install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ installdirs-am maintainer-clean maintainer-clean-generic \
+ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \
+ ps ps-am tags tags-recursive uninstall uninstall-am \
+ uninstall-binPROGRAMS uninstall-binSCRIPTS
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+#----------------------------------------------------------------------------
+# General stuff
+#----------------------------------------------------------------------------
+
+all-local: inplace-noinst_PROGRAMS inplace-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/cachegrind/cg-arch.c b/main/cachegrind/cg-arch.c
index 77adfc2..4afaab6 100644
--- a/main/cachegrind/cg-arch.c
+++ b/main/cachegrind/cg-arch.c
@@ -9,7 +9,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2011-2011 Nicholas Nethercote
+ Copyright (C) 2011-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/cachegrind/cg-arm.c b/main/cachegrind/cg-arm.c
index c9ef4d4..00badcd 100644
--- a/main/cachegrind/cg-arm.c
+++ b/main/cachegrind/cg-arm.c
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2005-2011 Johan Bjork
+ Copyright (C) 2005-2012 Johan Bjork
jbjoerk@gmail.com
This program is free software; you can redistribute it and/or
diff --git a/main/cachegrind/cg-mips32.c b/main/cachegrind/cg-mips32.c
new file mode 100644
index 0000000..5ad69c2
--- /dev/null
+++ b/main/cachegrind/cg-mips32.c
@@ -0,0 +1,59 @@
+
+/*--------------------------------------------------------------------*/
+/*--- MIPS-specific definitions. cg-mips32.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Cachegrind, a Valgrind tool for cache
+ profiling programs.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#if defined(VGA_mips32)
+
+#include "pub_tool_basics.h"
+#include "pub_tool_libcbase.h"
+#include "pub_tool_libcassert.h"
+#include "pub_tool_libcprint.h"
+
+#include "cg_arch.h"
+
+void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
+ Bool all_caches_clo_defined)
+{
+ // Set caches to default (for MIPS32-r2(mips 74kc))
+ *I1c = (cache_t) { 32768, 4, 32 };
+ *D1c = (cache_t) { 32768, 4, 32 };
+ *L2c = (cache_t) { 524288, 8, 32 };
+
+ if (!all_caches_clo_defined) {
+ VG_(message)(Vg_DebugMsg,
+ "Warning: Cannot auto-detect cache config on MIPS32, using one "
+ "or more defaults\n");
+ }
+}
+
+#endif // #if defined(VGA_mips32)
+
+/*--------------------------------------------------------------------*/
+/*--- end cg-mips32.c ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/cachegrind/cg-ppc32.c b/main/cachegrind/cg-ppc32.c
index 528efa7..d0386d6 100644
--- a/main/cachegrind/cg-ppc32.c
+++ b/main/cachegrind/cg-ppc32.c
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/cachegrind/cg-ppc64.c b/main/cachegrind/cg-ppc64.c
index 9845451..e594b99 100644
--- a/main/cachegrind/cg-ppc64.c
+++ b/main/cachegrind/cg-ppc64.c
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/cachegrind/cg-s390x.c b/main/cachegrind/cg-s390x.c
index 824a0d7..add8f33 100644
--- a/main/cachegrind/cg-s390x.c
+++ b/main/cachegrind/cg-s390x.c
@@ -8,7 +8,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/cachegrind/cg-x86-amd64.c b/main/cachegrind/cg-x86-amd64.c
index 16e4a72..1eb6c99 100644
--- a/main/cachegrind/cg-x86-amd64.c
+++ b/main/cachegrind/cg-x86-amd64.c
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2011 Nicholas Nethercote
+ Copyright (C) 2002-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/cachegrind/cg_arch.h b/main/cachegrind/cg_arch.h
index 68f9ab3..99d0cb1 100644
--- a/main/cachegrind/cg_arch.h
+++ b/main/cachegrind/cg_arch.h
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2011 Nicholas Nethercote
+ Copyright (C) 2002-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/cachegrind/cg_branchpred.c b/main/cachegrind/cg_branchpred.c
index 1db7fb5..cc246c3 100644
--- a/main/cachegrind/cg_branchpred.c
+++ b/main/cachegrind/cg_branchpred.c
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2011 Nicholas Nethercote
+ Copyright (C) 2002-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -44,7 +44,8 @@
/* How many bits at the bottom of an instruction address are
guaranteed to be zero? */
-#if defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm)
+#if defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm) \
+ || defined(VGA_mips32)
# define N_IADDR_LO_ZERO_BITS 2
#elif defined(VGA_x86) || defined(VGA_amd64)
# define N_IADDR_LO_ZERO_BITS 0
diff --git a/main/cachegrind/cg_main.c b/main/cachegrind/cg_main.c
index 4b36204..c26be83 100644
--- a/main/cachegrind/cg_main.c
+++ b/main/cachegrind/cg_main.c
@@ -8,7 +8,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2011 Nicholas Nethercote
+ Copyright (C) 2002-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -70,6 +70,12 @@
static Char* clo_cachegrind_out_file = "cachegrind.out.%p";
/*------------------------------------------------------------*/
+/*--- Cachesim configuration ---*/
+/*------------------------------------------------------------*/
+
+static Int min_line_size = 0; /* min of L1 and LL cache line sizes */
+
+/*------------------------------------------------------------*/
/*--- Types and Data Structures ---*/
/*------------------------------------------------------------*/
@@ -846,7 +852,7 @@
{
Event* evt;
tl_assert(isIRAtom(ea));
- tl_assert(datasize >= 1 && datasize <= MIN_LINE_SIZE);
+ tl_assert(datasize >= 1 && datasize <= min_line_size);
if (!clo_cache_sim)
return;
if (cgs->events_used == N_EVENTS)
@@ -868,7 +874,7 @@
Event* evt;
tl_assert(isIRAtom(ea));
- tl_assert(datasize >= 1 && datasize <= MIN_LINE_SIZE);
+ tl_assert(datasize >= 1 && datasize <= min_line_size);
if (!clo_cache_sim)
return;
@@ -1058,8 +1064,8 @@
// instructions will be done inaccurately, but they're
// very rare and this avoids errors from hitting more
// than two cache lines in the simulation.
- if (dataSize > MIN_LINE_SIZE)
- dataSize = MIN_LINE_SIZE;
+ if (dataSize > min_line_size)
+ dataSize = min_line_size;
if (d->mFx == Ifx_Read || d->mFx == Ifx_Modify)
addEvent_Dr( &cgs, curr_inode, dataSize, d->mAddr );
if (d->mFx == Ifx_Write || d->mFx == Ifx_Modify)
@@ -1085,8 +1091,8 @@
if (cas->dataHi != NULL)
dataSize *= 2; /* since it's a doubleword-CAS */
/* I don't think this can ever happen, but play safe. */
- if (dataSize > MIN_LINE_SIZE)
- dataSize = MIN_LINE_SIZE;
+ if (dataSize > min_line_size)
+ dataSize = min_line_size;
addEvent_Dr( &cgs, curr_inode, dataSize, cas->addr );
addEvent_Dw( &cgs, curr_inode, dataSize, cas->addr );
break;
@@ -1685,7 +1691,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a cache and branch-prediction profiler");
VG_(details_copyright_author)(
- "Copyright (C) 2002-2011, and GNU GPL'd, by Nicholas Nethercote et al.");
+ "Copyright (C) 2002-2012, and GNU GPL'd, by Nicholas Nethercote et al.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 500 );
@@ -1724,6 +1730,26 @@
&clo_D1_cache,
&clo_LL_cache);
+ // min_line_size is used to make sure that we never feed
+ // accesses to the simulator straddling more than two
+ // cache lines at any cache level
+ min_line_size = (I1c.line_size < D1c.line_size) ? I1c.line_size : D1c.line_size;
+ min_line_size = (LLc.line_size < min_line_size) ? LLc.line_size : min_line_size;
+
+ Int largest_load_or_store_size
+ = VG_(machine_get_size_of_largest_guest_register)();
+ if (min_line_size < largest_load_or_store_size) {
+ /* We can't continue, because the cache simulation might
+ straddle more than 2 lines, and it will assert. So let's
+ just stop before we start. */
+ VG_(umsg)("Cachegrind: cannot continue: the minimum line size (%d)\n",
+ (Int)min_line_size);
+ VG_(umsg)(" must be equal to or larger than the maximum register size (%d)\n",
+ largest_load_or_store_size );
+ VG_(umsg)(" but it is not. Exiting now.\n");
+ VG_(exit)(1);
+ }
+
cachesim_I1_initcache(I1c);
cachesim_D1_initcache(D1c);
cachesim_LL_initcache(LLc);
diff --git a/main/cachegrind/cg_merge.c b/main/cachegrind/cg_merge.c
index 9564c62..54b82a3 100644
--- a/main/cachegrind/cg_merge.c
+++ b/main/cachegrind/cg_merge.c
@@ -8,7 +8,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2011 Nicholas Nethercote
+ Copyright (C) 2002-2012 Nicholas Nethercote
njn@valgrind.org
AVL tree code derived from
diff --git a/main/cachegrind/cg_sim.c b/main/cachegrind/cg_sim.c
index a16b25e..1360733 100644
--- a/main/cachegrind/cg_sim.c
+++ b/main/cachegrind/cg_sim.c
@@ -7,7 +7,7 @@
This file is part of Cachegrind, a Valgrind tool for cache
profiling programs.
- Copyright (C) 2002-2011 Nicholas Nethercote
+ Copyright (C) 2002-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/cachegrind/tests/Makefile.am b/main/cachegrind/tests/Makefile.am
index 1dafb0a..e21d52d 100644
--- a/main/cachegrind/tests/Makefile.am
+++ b/main/cachegrind/tests/Makefile.am
@@ -30,5 +30,4 @@
else
myprint_so_LDFLAGS = $(AM_CFLAGS) -shared -fPIC
endif
-myprint_so_SOURCES = myprint.c # Only needed for automake-1.7.
myprint_so_CFLAGS = $(AM_CFLAGS) -fPIC
diff --git a/main/cachegrind/tests/Makefile.in b/main/cachegrind/tests/Makefile.in
new file mode 100644
index 0000000..ff73237
--- /dev/null
+++ b/main/cachegrind/tests/Makefile.in
@@ -0,0 +1,898 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+@VGCONF_ARCHS_INCLUDE_X86_TRUE@am__append_3 = x86
+check_PROGRAMS = chdir$(EXEEXT) clreq$(EXEEXT) dlclose$(EXEEXT) \
+ myprint.so$(EXEEXT)
+subdir = cachegrind/tests
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+chdir_SOURCES = chdir.c
+chdir_OBJECTS = chdir.$(OBJEXT)
+chdir_LDADD = $(LDADD)
+clreq_SOURCES = clreq.c
+clreq_OBJECTS = clreq.$(OBJEXT)
+clreq_LDADD = $(LDADD)
+dlclose_SOURCES = dlclose.c
+dlclose_OBJECTS = dlclose.$(OBJEXT)
+dlclose_DEPENDENCIES =
+myprint_so_SOURCES = myprint.c
+myprint_so_OBJECTS = myprint_so-myprint.$(OBJEXT)
+myprint_so_LDADD = $(LDADD)
+myprint_so_LINK = $(CCLD) $(myprint_so_CFLAGS) $(CFLAGS) \
+ $(myprint_so_LDFLAGS) $(LDFLAGS) -o $@
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = chdir.c clreq.c dlclose.c myprint.c
+DIST_SOURCES = chdir.c clreq.c dlclose.c myprint.c
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+SUBDIRS = . $(am__append_3)
+DIST_SUBDIRS = x86 .
+dist_noinst_SCRIPTS = filter_stderr filter_cachesim_discards
+EXTRA_DIST = \
+ chdir.vgtest chdir.stderr.exp \
+ clreq.vgtest clreq.stderr.exp \
+ dlclose.vgtest dlclose.stderr.exp dlclose.stdout.exp \
+ notpower2.vgtest notpower2.stderr.exp \
+ wrap5.vgtest wrap5.stderr.exp wrap5.stdout.exp
+
+
+# C ones
+dlclose_LDADD = -ldl
+@VGCONF_OS_IS_DARWIN_FALSE@myprint_so_LDFLAGS = $(AM_CFLAGS) -shared -fPIC
+@VGCONF_OS_IS_DARWIN_TRUE@myprint_so_LDFLAGS = $(AM_CFLAGS) -dynamic -dynamiclib -all_load -fpic
+myprint_so_CFLAGS = $(AM_CFLAGS) -fPIC
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign cachegrind/tests/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign cachegrind/tests/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+chdir$(EXEEXT): $(chdir_OBJECTS) $(chdir_DEPENDENCIES)
+ @rm -f chdir$(EXEEXT)
+ $(LINK) $(chdir_OBJECTS) $(chdir_LDADD) $(LIBS)
+clreq$(EXEEXT): $(clreq_OBJECTS) $(clreq_DEPENDENCIES)
+ @rm -f clreq$(EXEEXT)
+ $(LINK) $(clreq_OBJECTS) $(clreq_LDADD) $(LIBS)
+dlclose$(EXEEXT): $(dlclose_OBJECTS) $(dlclose_DEPENDENCIES)
+ @rm -f dlclose$(EXEEXT)
+ $(LINK) $(dlclose_OBJECTS) $(dlclose_LDADD) $(LIBS)
+myprint.so$(EXEEXT): $(myprint_so_OBJECTS) $(myprint_so_DEPENDENCIES)
+ @rm -f myprint.so$(EXEEXT)
+ $(myprint_so_LINK) $(myprint_so_OBJECTS) $(myprint_so_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/chdir.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clreq.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dlclose.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/myprint_so-myprint.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+myprint_so-myprint.o: myprint.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(myprint_so_CFLAGS) $(CFLAGS) -MT myprint_so-myprint.o -MD -MP -MF $(DEPDIR)/myprint_so-myprint.Tpo -c -o myprint_so-myprint.o `test -f 'myprint.c' || echo '$(srcdir)/'`myprint.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/myprint_so-myprint.Tpo $(DEPDIR)/myprint_so-myprint.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='myprint.c' object='myprint_so-myprint.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(myprint_so_CFLAGS) $(CFLAGS) -c -o myprint_so-myprint.o `test -f 'myprint.c' || echo '$(srcdir)/'`myprint.c
+
+myprint_so-myprint.obj: myprint.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(myprint_so_CFLAGS) $(CFLAGS) -MT myprint_so-myprint.obj -MD -MP -MF $(DEPDIR)/myprint_so-myprint.Tpo -c -o myprint_so-myprint.obj `if test -f 'myprint.c'; then $(CYGPATH_W) 'myprint.c'; else $(CYGPATH_W) '$(srcdir)/myprint.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/myprint_so-myprint.Tpo $(DEPDIR)/myprint_so-myprint.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='myprint.c' object='myprint_so-myprint.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(myprint_so_CFLAGS) $(CFLAGS) -c -o myprint_so-myprint.obj `if test -f 'myprint.c'; then $(CYGPATH_W) 'myprint.c'; else $(CYGPATH_W) '$(srcdir)/myprint.c'; fi`
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-recursive
+all-am: Makefile $(SCRIPTS)
+installdirs: installdirs-recursive
+installdirs-am:
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) check-am \
+ ctags-recursive install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags \
+ ctags-recursive distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ installdirs-am maintainer-clean maintainer-clean-generic \
+ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \
+ ps ps-am tags tags-recursive uninstall uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/cachegrind/tests/filter_stderr b/main/cachegrind/tests/filter_stderr
index d6800cd..2d38fb3 100755
--- a/main/cachegrind/tests/filter_stderr
+++ b/main/cachegrind/tests/filter_stderr
@@ -20,4 +20,5 @@
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d" |
sed "/Warning: Cannot auto-detect cache config on ARM, using one or more defaults/d" |
sed "/Warning: Cannot auto-detect cache config on s390x, using one or more defaults/d" |
+sed "/Warning: Cannot auto-detect cache config on MIPS.., using one or more defaults/d" |
sed "/warning: pretending that LL cache has associativity .*$/d"
diff --git a/main/cachegrind/tests/x86/Makefile.in b/main/cachegrind/tests/x86/Makefile.in
new file mode 100644
index 0000000..d04925a
--- /dev/null
+++ b/main/cachegrind/tests/x86/Makefile.in
@@ -0,0 +1,701 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = fpu-28-108$(EXEEXT)
+subdir = cachegrind/tests/x86
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+am_fpu_28_108_OBJECTS = fpu-28-108.$(OBJEXT)
+fpu_28_108_OBJECTS = $(am_fpu_28_108_OBJECTS)
+fpu_28_108_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+CPPASCOMPILE = $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CCASFLAGS) $(CCASFLAGS)
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(fpu_28_108_SOURCES)
+DIST_SOURCES = $(fpu_28_108_SOURCES)
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ fpu-28-108.vgtest fpu-28-108.stderr.exp
+
+fpu_28_108_SOURCES = fpu-28-108.S
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .S .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign cachegrind/tests/x86/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign cachegrind/tests/x86/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+fpu-28-108$(EXEEXT): $(fpu_28_108_OBJECTS) $(fpu_28_108_DEPENDENCIES)
+ @rm -f fpu-28-108$(EXEEXT)
+ $(LINK) $(fpu_28_108_OBJECTS) $(fpu_28_108_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fpu-28-108.Po@am__quote@
+
+.S.o:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ $<
+
+.S.obj:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/callgrind/Makefile.am b/main/callgrind/Makefile.am
index 0a8a2d3..ae4ff4f 100644
--- a/main/callgrind/Makefile.am
+++ b/main/callgrind/Makefile.am
@@ -35,7 +35,6 @@
bbcc.c \
callstack.c \
clo.c \
- command.c \
context.c \
costs.c \
debug.c \
@@ -51,7 +50,8 @@
../cachegrind/cg-ppc32.c \
../cachegrind/cg-ppc64.c \
../cachegrind/cg-arm.c \
- ../cachegrind/cg-s390x.c
+ ../cachegrind/cg-s390x.c \
+ ../cachegrind/cg-mips32.c
CALLGRIND_CFLAGS_COMMON = -I$(top_srcdir)/cachegrind
diff --git a/main/callgrind/Makefile.in b/main/callgrind/Makefile.in
new file mode 100644
index 0000000..5ee3e68
--- /dev/null
+++ b/main/callgrind/Makefile.in
@@ -0,0 +1,1846 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
+ $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(srcdir)/callgrind_annotate.in $(srcdir)/callgrind_control.in \
+ $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+
+# On Android we must ask for non-executable stack, not sure why.
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_2 = -Wl,-z,noexecstack
+noinst_PROGRAMS = callgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
+ $(am__EXEEXT_1)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_3 = callgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
+subdir = callgrind
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES = callgrind_annotate callgrind_control
+CONFIG_CLEAN_VPATH_FILES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = callgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+PROGRAMS = $(noinst_PROGRAMS)
+am__objects_1 = callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.$(OBJEXT)
+am_callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = \
+ $(am_callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
+am__callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = bb.c bbcc.c \
+ callstack.c clo.c context.c costs.c debug.c dump.c events.c \
+ fn.c jumps.c main.c sim.c threads.c ../cachegrind/cg-arch.c \
+ ../cachegrind/cg-x86-amd64.c ../cachegrind/cg-ppc32.c \
+ ../cachegrind/cg-ppc64.c ../cachegrind/cg-arm.c \
+ ../cachegrind/cg-s390x.c ../cachegrind/cg-mips32.c
+am__objects_2 = callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.$(OBJEXT) \
+ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_2)
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+ $(am_callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
+am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
+am__vpath_adj = case $$p in \
+ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
+ *) f=$$p;; \
+ esac;
+am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;
+am__install_max = 40
+am__nobase_strip_setup = \
+ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`
+am__nobase_strip = \
+ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"
+am__nobase_list = $(am__nobase_strip_setup); \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \
+ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \
+ if (++n[$$2] == $(am__install_max)) \
+ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \
+ END { for (dir in files) print dir, files[dir] }'
+am__base_list = \
+ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \
+ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'
+am__installdirs = "$(DESTDIR)$(bindir)" "$(DESTDIR)$(pkgincludedir)"
+SCRIPTS = $(bin_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES)
+DIST_SOURCES = $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(am__callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST)
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+HEADERS = $(noinst_HEADERS) $(pkginclude_HEADERS)
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DIST_SUBDIRS = $(SUBDIRS)
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+SUBDIRS = . tests
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+#----------------------------------------------------------------------------
+# <tool>-<platform> stuff
+#----------------------------------------------------------------------------
+TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+
+TOOL_LDADD_COMMON = -lgcc
+TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) $(TOOL_LDADD_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
+
+
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+ -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_X86_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_AMD64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_PPC32_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_PPC64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_ARM_LINUX = $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
+ $(am__append_2)
+TOOL_LDFLAGS_S390X_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_X86_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386
+
+TOOL_LDFLAGS_AMD64_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+
+
+# MIPS Linux default start symbol is __start, not _start like on x86 or amd
+TOOL_LDFLAGS_MIPS32_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
+ @FLAG_M32@
+
+
+# NB for 64-bit darwin. We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them). Although such setting is probably
+# better done in link_tool_exe.c.
+#
+# -Wl,-pagezero_size,0x100000000
+
+#----------------------------------------------------------------------------
+# vgpreload_<tool>-<platform>.a stuff
+#----------------------------------------------------------------------------
+LIBREPLACEMALLOC_X86_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-linux.a
+
+LIBREPLACEMALLOC_AMD64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-linux.a
+
+LIBREPLACEMALLOC_PPC32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a
+
+LIBREPLACEMALLOC_PPC64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a
+
+LIBREPLACEMALLOC_ARM_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a
+
+LIBREPLACEMALLOC_X86_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-darwin.a
+
+LIBREPLACEMALLOC_AMD64_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-darwin.a
+
+LIBREPLACEMALLOC_S390X_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-s390x-linux.a
+
+LIBREPLACEMALLOC_MIPS32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips32-linux.a
+
+LIBREPLACEMALLOC_LDFLAGS_X86_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_X86_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_AMD64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC32_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_ARM_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_X86_DARWIN = \
+ $(LIBREPLACEMALLOC_X86_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_DARWIN = \
+ $(LIBREPLACEMALLOC_AMD64_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_S390X_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_S390X_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_MIPS32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_MIPS32_LINUX) \
+ -Wl,--no-whole-archive
+
+EXTRA_DIST = \
+ docs/callgrind_annotate-manpage.xml \
+ docs/callgrind_control-manpage.xml \
+ docs/cl-manual.xml \
+ docs/cl-format.xml
+
+
+#----------------------------------------------------------------------------
+# Headers, etc
+#----------------------------------------------------------------------------
+pkginclude_HEADERS = callgrind.h
+bin_SCRIPTS = \
+ callgrind_annotate \
+ callgrind_control
+
+noinst_HEADERS = \
+ costs.h \
+ events.h \
+ global.h
+
+CALLGRIND_SOURCES_COMMON = \
+ bb.c \
+ bbcc.c \
+ callstack.c \
+ clo.c \
+ context.c \
+ costs.c \
+ debug.c \
+ dump.c \
+ events.c \
+ fn.c \
+ jumps.c \
+ main.c \
+ sim.c \
+ threads.c \
+ ../cachegrind/cg-arch.c \
+ ../cachegrind/cg-x86-amd64.c \
+ ../cachegrind/cg-ppc32.c \
+ ../cachegrind/cg-ppc64.c \
+ ../cachegrind/cg-arm.c \
+ ../cachegrind/cg-s390x.c \
+ ../cachegrind/cg-mips32.c
+
+CALLGRIND_CFLAGS_COMMON = -I$(top_srcdir)/cachegrind
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+ $(CALLGRIND_SOURCES_COMMON)
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(CALLGRIND_CFLAGS_COMMON)
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@)
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
+ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
+ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+ @VALT_LOAD_ADDRESS_PRI@ \
+ $(LINK) \
+ $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+ $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(CALLGRIND_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) $(CALLGRIND_CFLAGS_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign callgrind/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign callgrind/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+callgrind_annotate: $(top_builddir)/config.status $(srcdir)/callgrind_annotate.in
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+callgrind_control: $(top_builddir)/config.status $(srcdir)/callgrind_control.in
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+
+clean-noinstPROGRAMS:
+ -test -z "$(noinst_PROGRAMS)" || rm -f $(noinst_PROGRAMS)
+callgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT): $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f callgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT)
+ $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD) $(LIBS)
+callgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT): $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f callgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+ $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD) $(LIBS)
+install-binSCRIPTS: $(bin_SCRIPTS)
+ @$(NORMAL_INSTALL)
+ test -z "$(bindir)" || $(MKDIR_P) "$(DESTDIR)$(bindir)"
+ @list='$(bin_SCRIPTS)'; test -n "$(bindir)" || list=; \
+ for p in $$list; do \
+ if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+ if test -f "$$d$$p"; then echo "$$d$$p"; echo "$$p"; else :; fi; \
+ done | \
+ sed -e 'p;s,.*/,,;n' \
+ -e 'h;s|.*|.|' \
+ -e 'p;x;s,.*/,,;$(transform)' | sed 'N;N;N;s,\n, ,g' | \
+ $(AWK) 'BEGIN { files["."] = ""; dirs["."] = 1; } \
+ { d=$$3; if (dirs[d] != 1) { print "d", d; dirs[d] = 1 } \
+ if ($$2 == $$4) { files[d] = files[d] " " $$1; \
+ if (++n[d] == $(am__install_max)) { \
+ print "f", d, files[d]; n[d] = 0; files[d] = "" } } \
+ else { print "f", d "/" $$4, $$1 } } \
+ END { for (d in files) print "f", d, files[d] }' | \
+ while read type dir files; do \
+ if test "$$dir" = .; then dir=; else dir=/$$dir; fi; \
+ test -z "$$files" || { \
+ echo " $(INSTALL_SCRIPT) $$files '$(DESTDIR)$(bindir)$$dir'"; \
+ $(INSTALL_SCRIPT) $$files "$(DESTDIR)$(bindir)$$dir" || exit $$?; \
+ } \
+ ; done
+
+uninstall-binSCRIPTS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(bin_SCRIPTS)'; test -n "$(bindir)" || exit 0; \
+ files=`for p in $$list; do echo "$$p"; done | \
+ sed -e 's,.*/,,;$(transform)'`; \
+ test -n "$$list" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(bindir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(bindir)" && rm -f $$files
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.o: bb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.o `test -f 'bb.c' || echo '$(srcdir)/'`bb.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='bb.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.o `test -f 'bb.c' || echo '$(srcdir)/'`bb.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.obj: bb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.obj `if test -f 'bb.c'; then $(CYGPATH_W) 'bb.c'; else $(CYGPATH_W) '$(srcdir)/bb.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='bb.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.obj `if test -f 'bb.c'; then $(CYGPATH_W) 'bb.c'; else $(CYGPATH_W) '$(srcdir)/bb.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.o: bbcc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.o `test -f 'bbcc.c' || echo '$(srcdir)/'`bbcc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='bbcc.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.o `test -f 'bbcc.c' || echo '$(srcdir)/'`bbcc.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.obj: bbcc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.obj `if test -f 'bbcc.c'; then $(CYGPATH_W) 'bbcc.c'; else $(CYGPATH_W) '$(srcdir)/bbcc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='bbcc.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bbcc.obj `if test -f 'bbcc.c'; then $(CYGPATH_W) 'bbcc.c'; else $(CYGPATH_W) '$(srcdir)/bbcc.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.o: callstack.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.o `test -f 'callstack.c' || echo '$(srcdir)/'`callstack.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='callstack.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.o `test -f 'callstack.c' || echo '$(srcdir)/'`callstack.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.obj: callstack.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.obj `if test -f 'callstack.c'; then $(CYGPATH_W) 'callstack.c'; else $(CYGPATH_W) '$(srcdir)/callstack.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='callstack.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-callstack.obj `if test -f 'callstack.c'; then $(CYGPATH_W) 'callstack.c'; else $(CYGPATH_W) '$(srcdir)/callstack.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.o: clo.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.o `test -f 'clo.c' || echo '$(srcdir)/'`clo.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='clo.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.o `test -f 'clo.c' || echo '$(srcdir)/'`clo.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.obj: clo.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.obj `if test -f 'clo.c'; then $(CYGPATH_W) 'clo.c'; else $(CYGPATH_W) '$(srcdir)/clo.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='clo.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-clo.obj `if test -f 'clo.c'; then $(CYGPATH_W) 'clo.c'; else $(CYGPATH_W) '$(srcdir)/clo.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.o: context.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.o `test -f 'context.c' || echo '$(srcdir)/'`context.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='context.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.o `test -f 'context.c' || echo '$(srcdir)/'`context.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.obj: context.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.obj `if test -f 'context.c'; then $(CYGPATH_W) 'context.c'; else $(CYGPATH_W) '$(srcdir)/context.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='context.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-context.obj `if test -f 'context.c'; then $(CYGPATH_W) 'context.c'; else $(CYGPATH_W) '$(srcdir)/context.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.o: costs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.o `test -f 'costs.c' || echo '$(srcdir)/'`costs.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='costs.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.o `test -f 'costs.c' || echo '$(srcdir)/'`costs.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.obj: costs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.obj `if test -f 'costs.c'; then $(CYGPATH_W) 'costs.c'; else $(CYGPATH_W) '$(srcdir)/costs.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='costs.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-costs.obj `if test -f 'costs.c'; then $(CYGPATH_W) 'costs.c'; else $(CYGPATH_W) '$(srcdir)/costs.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.o: debug.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.o `test -f 'debug.c' || echo '$(srcdir)/'`debug.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='debug.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.o `test -f 'debug.c' || echo '$(srcdir)/'`debug.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.obj: debug.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.obj `if test -f 'debug.c'; then $(CYGPATH_W) 'debug.c'; else $(CYGPATH_W) '$(srcdir)/debug.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='debug.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-debug.obj `if test -f 'debug.c'; then $(CYGPATH_W) 'debug.c'; else $(CYGPATH_W) '$(srcdir)/debug.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.o: dump.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.o `test -f 'dump.c' || echo '$(srcdir)/'`dump.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='dump.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.o `test -f 'dump.c' || echo '$(srcdir)/'`dump.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.obj: dump.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.obj `if test -f 'dump.c'; then $(CYGPATH_W) 'dump.c'; else $(CYGPATH_W) '$(srcdir)/dump.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='dump.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-dump.obj `if test -f 'dump.c'; then $(CYGPATH_W) 'dump.c'; else $(CYGPATH_W) '$(srcdir)/dump.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.o: events.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.o `test -f 'events.c' || echo '$(srcdir)/'`events.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='events.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.o `test -f 'events.c' || echo '$(srcdir)/'`events.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.obj: events.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.obj `if test -f 'events.c'; then $(CYGPATH_W) 'events.c'; else $(CYGPATH_W) '$(srcdir)/events.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='events.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-events.obj `if test -f 'events.c'; then $(CYGPATH_W) 'events.c'; else $(CYGPATH_W) '$(srcdir)/events.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.o: fn.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.o `test -f 'fn.c' || echo '$(srcdir)/'`fn.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fn.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.o `test -f 'fn.c' || echo '$(srcdir)/'`fn.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.obj: fn.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.obj `if test -f 'fn.c'; then $(CYGPATH_W) 'fn.c'; else $(CYGPATH_W) '$(srcdir)/fn.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fn.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-fn.obj `if test -f 'fn.c'; then $(CYGPATH_W) 'fn.c'; else $(CYGPATH_W) '$(srcdir)/fn.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.o: jumps.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.o `test -f 'jumps.c' || echo '$(srcdir)/'`jumps.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='jumps.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.o `test -f 'jumps.c' || echo '$(srcdir)/'`jumps.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.obj: jumps.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.obj `if test -f 'jumps.c'; then $(CYGPATH_W) 'jumps.c'; else $(CYGPATH_W) '$(srcdir)/jumps.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='jumps.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-jumps.obj `if test -f 'jumps.c'; then $(CYGPATH_W) 'jumps.c'; else $(CYGPATH_W) '$(srcdir)/jumps.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.o: main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.o `test -f 'main.c' || echo '$(srcdir)/'`main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='main.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.o `test -f 'main.c' || echo '$(srcdir)/'`main.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.obj: main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.obj `if test -f 'main.c'; then $(CYGPATH_W) 'main.c'; else $(CYGPATH_W) '$(srcdir)/main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='main.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-main.obj `if test -f 'main.c'; then $(CYGPATH_W) 'main.c'; else $(CYGPATH_W) '$(srcdir)/main.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.o: sim.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.o `test -f 'sim.c' || echo '$(srcdir)/'`sim.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sim.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.o `test -f 'sim.c' || echo '$(srcdir)/'`sim.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.obj: sim.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.obj `if test -f 'sim.c'; then $(CYGPATH_W) 'sim.c'; else $(CYGPATH_W) '$(srcdir)/sim.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sim.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-sim.obj `if test -f 'sim.c'; then $(CYGPATH_W) 'sim.c'; else $(CYGPATH_W) '$(srcdir)/sim.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.o: threads.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.o `test -f 'threads.c' || echo '$(srcdir)/'`threads.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='threads.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.o `test -f 'threads.c' || echo '$(srcdir)/'`threads.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.obj: threads.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.obj `if test -f 'threads.c'; then $(CYGPATH_W) 'threads.c'; else $(CYGPATH_W) '$(srcdir)/threads.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='threads.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-threads.obj `if test -f 'threads.c'; then $(CYGPATH_W) 'threads.c'; else $(CYGPATH_W) '$(srcdir)/threads.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o: ../cachegrind/cg-arch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o `test -f '../cachegrind/cg-arch.c' || echo '$(srcdir)/'`../cachegrind/cg-arch.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-arch.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.o `test -f '../cachegrind/cg-arch.c' || echo '$(srcdir)/'`../cachegrind/cg-arch.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj: ../cachegrind/cg-arch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj `if test -f '../cachegrind/cg-arch.c'; then $(CYGPATH_W) '../cachegrind/cg-arch.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-arch.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-arch.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arch.obj `if test -f '../cachegrind/cg-arch.c'; then $(CYGPATH_W) '../cachegrind/cg-arch.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-arch.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o: ../cachegrind/cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o `test -f '../cachegrind/cg-x86-amd64.c' || echo '$(srcdir)/'`../cachegrind/cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-x86-amd64.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.o `test -f '../cachegrind/cg-x86-amd64.c' || echo '$(srcdir)/'`../cachegrind/cg-x86-amd64.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj: ../cachegrind/cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj `if test -f '../cachegrind/cg-x86-amd64.c'; then $(CYGPATH_W) '../cachegrind/cg-x86-amd64.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-x86-amd64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-x86-amd64.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-x86-amd64.obj `if test -f '../cachegrind/cg-x86-amd64.c'; then $(CYGPATH_W) '../cachegrind/cg-x86-amd64.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-x86-amd64.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o: ../cachegrind/cg-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o `test -f '../cachegrind/cg-ppc32.c' || echo '$(srcdir)/'`../cachegrind/cg-ppc32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-ppc32.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.o `test -f '../cachegrind/cg-ppc32.c' || echo '$(srcdir)/'`../cachegrind/cg-ppc32.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj: ../cachegrind/cg-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj `if test -f '../cachegrind/cg-ppc32.c'; then $(CYGPATH_W) '../cachegrind/cg-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-ppc32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-ppc32.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc32.obj `if test -f '../cachegrind/cg-ppc32.c'; then $(CYGPATH_W) '../cachegrind/cg-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-ppc32.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o: ../cachegrind/cg-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o `test -f '../cachegrind/cg-ppc64.c' || echo '$(srcdir)/'`../cachegrind/cg-ppc64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-ppc64.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.o `test -f '../cachegrind/cg-ppc64.c' || echo '$(srcdir)/'`../cachegrind/cg-ppc64.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj: ../cachegrind/cg-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj `if test -f '../cachegrind/cg-ppc64.c'; then $(CYGPATH_W) '../cachegrind/cg-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-ppc64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-ppc64.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-ppc64.obj `if test -f '../cachegrind/cg-ppc64.c'; then $(CYGPATH_W) '../cachegrind/cg-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-ppc64.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o: ../cachegrind/cg-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o `test -f '../cachegrind/cg-arm.c' || echo '$(srcdir)/'`../cachegrind/cg-arm.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-arm.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.o `test -f '../cachegrind/cg-arm.c' || echo '$(srcdir)/'`../cachegrind/cg-arm.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj: ../cachegrind/cg-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj `if test -f '../cachegrind/cg-arm.c'; then $(CYGPATH_W) '../cachegrind/cg-arm.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-arm.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-arm.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-arm.obj `if test -f '../cachegrind/cg-arm.c'; then $(CYGPATH_W) '../cachegrind/cg-arm.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-arm.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o: ../cachegrind/cg-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o `test -f '../cachegrind/cg-s390x.c' || echo '$(srcdir)/'`../cachegrind/cg-s390x.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-s390x.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.o `test -f '../cachegrind/cg-s390x.c' || echo '$(srcdir)/'`../cachegrind/cg-s390x.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj: ../cachegrind/cg-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj `if test -f '../cachegrind/cg-s390x.c'; then $(CYGPATH_W) '../cachegrind/cg-s390x.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-s390x.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-s390x.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-s390x.obj `if test -f '../cachegrind/cg-s390x.c'; then $(CYGPATH_W) '../cachegrind/cg-s390x.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-s390x.c'; fi`
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o: ../cachegrind/cg-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o `test -f '../cachegrind/cg-mips32.c' || echo '$(srcdir)/'`../cachegrind/cg-mips32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-mips32.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.o `test -f '../cachegrind/cg-mips32.c' || echo '$(srcdir)/'`../cachegrind/cg-mips32.c
+
+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj: ../cachegrind/cg-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Tpo -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj `if test -f '../cachegrind/cg-mips32.c'; then $(CYGPATH_W) '../cachegrind/cg-mips32.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-mips32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-mips32.c' object='callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-cg-mips32.obj `if test -f '../cachegrind/cg-mips32.c'; then $(CYGPATH_W) '../cachegrind/cg-mips32.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-mips32.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.o: bb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.o `test -f 'bb.c' || echo '$(srcdir)/'`bb.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='bb.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.o `test -f 'bb.c' || echo '$(srcdir)/'`bb.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.obj: bb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.obj `if test -f 'bb.c'; then $(CYGPATH_W) 'bb.c'; else $(CYGPATH_W) '$(srcdir)/bb.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='bb.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.obj `if test -f 'bb.c'; then $(CYGPATH_W) 'bb.c'; else $(CYGPATH_W) '$(srcdir)/bb.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.o: bbcc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.o `test -f 'bbcc.c' || echo '$(srcdir)/'`bbcc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='bbcc.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.o `test -f 'bbcc.c' || echo '$(srcdir)/'`bbcc.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.obj: bbcc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.obj `if test -f 'bbcc.c'; then $(CYGPATH_W) 'bbcc.c'; else $(CYGPATH_W) '$(srcdir)/bbcc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='bbcc.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbcc.obj `if test -f 'bbcc.c'; then $(CYGPATH_W) 'bbcc.c'; else $(CYGPATH_W) '$(srcdir)/bbcc.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.o: callstack.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.o `test -f 'callstack.c' || echo '$(srcdir)/'`callstack.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='callstack.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.o `test -f 'callstack.c' || echo '$(srcdir)/'`callstack.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.obj: callstack.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.obj `if test -f 'callstack.c'; then $(CYGPATH_W) 'callstack.c'; else $(CYGPATH_W) '$(srcdir)/callstack.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='callstack.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-callstack.obj `if test -f 'callstack.c'; then $(CYGPATH_W) 'callstack.c'; else $(CYGPATH_W) '$(srcdir)/callstack.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.o: clo.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.o `test -f 'clo.c' || echo '$(srcdir)/'`clo.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='clo.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.o `test -f 'clo.c' || echo '$(srcdir)/'`clo.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.obj: clo.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.obj `if test -f 'clo.c'; then $(CYGPATH_W) 'clo.c'; else $(CYGPATH_W) '$(srcdir)/clo.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='clo.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-clo.obj `if test -f 'clo.c'; then $(CYGPATH_W) 'clo.c'; else $(CYGPATH_W) '$(srcdir)/clo.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.o: context.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.o `test -f 'context.c' || echo '$(srcdir)/'`context.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='context.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.o `test -f 'context.c' || echo '$(srcdir)/'`context.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.obj: context.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.obj `if test -f 'context.c'; then $(CYGPATH_W) 'context.c'; else $(CYGPATH_W) '$(srcdir)/context.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='context.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-context.obj `if test -f 'context.c'; then $(CYGPATH_W) 'context.c'; else $(CYGPATH_W) '$(srcdir)/context.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.o: costs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.o `test -f 'costs.c' || echo '$(srcdir)/'`costs.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='costs.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.o `test -f 'costs.c' || echo '$(srcdir)/'`costs.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.obj: costs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.obj `if test -f 'costs.c'; then $(CYGPATH_W) 'costs.c'; else $(CYGPATH_W) '$(srcdir)/costs.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='costs.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-costs.obj `if test -f 'costs.c'; then $(CYGPATH_W) 'costs.c'; else $(CYGPATH_W) '$(srcdir)/costs.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.o: debug.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.o `test -f 'debug.c' || echo '$(srcdir)/'`debug.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='debug.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.o `test -f 'debug.c' || echo '$(srcdir)/'`debug.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.obj: debug.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.obj `if test -f 'debug.c'; then $(CYGPATH_W) 'debug.c'; else $(CYGPATH_W) '$(srcdir)/debug.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='debug.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-debug.obj `if test -f 'debug.c'; then $(CYGPATH_W) 'debug.c'; else $(CYGPATH_W) '$(srcdir)/debug.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.o: dump.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.o `test -f 'dump.c' || echo '$(srcdir)/'`dump.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='dump.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.o `test -f 'dump.c' || echo '$(srcdir)/'`dump.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.obj: dump.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.obj `if test -f 'dump.c'; then $(CYGPATH_W) 'dump.c'; else $(CYGPATH_W) '$(srcdir)/dump.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='dump.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-dump.obj `if test -f 'dump.c'; then $(CYGPATH_W) 'dump.c'; else $(CYGPATH_W) '$(srcdir)/dump.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.o: events.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.o `test -f 'events.c' || echo '$(srcdir)/'`events.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='events.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.o `test -f 'events.c' || echo '$(srcdir)/'`events.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.obj: events.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.obj `if test -f 'events.c'; then $(CYGPATH_W) 'events.c'; else $(CYGPATH_W) '$(srcdir)/events.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='events.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-events.obj `if test -f 'events.c'; then $(CYGPATH_W) 'events.c'; else $(CYGPATH_W) '$(srcdir)/events.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.o: fn.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.o `test -f 'fn.c' || echo '$(srcdir)/'`fn.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fn.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.o `test -f 'fn.c' || echo '$(srcdir)/'`fn.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.obj: fn.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.obj `if test -f 'fn.c'; then $(CYGPATH_W) 'fn.c'; else $(CYGPATH_W) '$(srcdir)/fn.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fn.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-fn.obj `if test -f 'fn.c'; then $(CYGPATH_W) 'fn.c'; else $(CYGPATH_W) '$(srcdir)/fn.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.o: jumps.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.o `test -f 'jumps.c' || echo '$(srcdir)/'`jumps.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='jumps.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.o `test -f 'jumps.c' || echo '$(srcdir)/'`jumps.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.obj: jumps.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.obj `if test -f 'jumps.c'; then $(CYGPATH_W) 'jumps.c'; else $(CYGPATH_W) '$(srcdir)/jumps.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='jumps.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-jumps.obj `if test -f 'jumps.c'; then $(CYGPATH_W) 'jumps.c'; else $(CYGPATH_W) '$(srcdir)/jumps.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.o: main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.o `test -f 'main.c' || echo '$(srcdir)/'`main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='main.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.o `test -f 'main.c' || echo '$(srcdir)/'`main.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.obj: main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.obj `if test -f 'main.c'; then $(CYGPATH_W) 'main.c'; else $(CYGPATH_W) '$(srcdir)/main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='main.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-main.obj `if test -f 'main.c'; then $(CYGPATH_W) 'main.c'; else $(CYGPATH_W) '$(srcdir)/main.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.o: sim.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.o `test -f 'sim.c' || echo '$(srcdir)/'`sim.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sim.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.o `test -f 'sim.c' || echo '$(srcdir)/'`sim.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.obj: sim.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.obj `if test -f 'sim.c'; then $(CYGPATH_W) 'sim.c'; else $(CYGPATH_W) '$(srcdir)/sim.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sim.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-sim.obj `if test -f 'sim.c'; then $(CYGPATH_W) 'sim.c'; else $(CYGPATH_W) '$(srcdir)/sim.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.o: threads.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.o `test -f 'threads.c' || echo '$(srcdir)/'`threads.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='threads.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.o `test -f 'threads.c' || echo '$(srcdir)/'`threads.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.obj: threads.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.obj `if test -f 'threads.c'; then $(CYGPATH_W) 'threads.c'; else $(CYGPATH_W) '$(srcdir)/threads.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='threads.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-threads.obj `if test -f 'threads.c'; then $(CYGPATH_W) 'threads.c'; else $(CYGPATH_W) '$(srcdir)/threads.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o: ../cachegrind/cg-arch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o `test -f '../cachegrind/cg-arch.c' || echo '$(srcdir)/'`../cachegrind/cg-arch.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-arch.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.o `test -f '../cachegrind/cg-arch.c' || echo '$(srcdir)/'`../cachegrind/cg-arch.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj: ../cachegrind/cg-arch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj `if test -f '../cachegrind/cg-arch.c'; then $(CYGPATH_W) '../cachegrind/cg-arch.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-arch.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-arch.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arch.obj `if test -f '../cachegrind/cg-arch.c'; then $(CYGPATH_W) '../cachegrind/cg-arch.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-arch.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o: ../cachegrind/cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o `test -f '../cachegrind/cg-x86-amd64.c' || echo '$(srcdir)/'`../cachegrind/cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-x86-amd64.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.o `test -f '../cachegrind/cg-x86-amd64.c' || echo '$(srcdir)/'`../cachegrind/cg-x86-amd64.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj: ../cachegrind/cg-x86-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj `if test -f '../cachegrind/cg-x86-amd64.c'; then $(CYGPATH_W) '../cachegrind/cg-x86-amd64.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-x86-amd64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-x86-amd64.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-x86-amd64.obj `if test -f '../cachegrind/cg-x86-amd64.c'; then $(CYGPATH_W) '../cachegrind/cg-x86-amd64.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-x86-amd64.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o: ../cachegrind/cg-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o `test -f '../cachegrind/cg-ppc32.c' || echo '$(srcdir)/'`../cachegrind/cg-ppc32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-ppc32.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.o `test -f '../cachegrind/cg-ppc32.c' || echo '$(srcdir)/'`../cachegrind/cg-ppc32.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj: ../cachegrind/cg-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj `if test -f '../cachegrind/cg-ppc32.c'; then $(CYGPATH_W) '../cachegrind/cg-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-ppc32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-ppc32.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc32.obj `if test -f '../cachegrind/cg-ppc32.c'; then $(CYGPATH_W) '../cachegrind/cg-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-ppc32.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o: ../cachegrind/cg-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o `test -f '../cachegrind/cg-ppc64.c' || echo '$(srcdir)/'`../cachegrind/cg-ppc64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-ppc64.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.o `test -f '../cachegrind/cg-ppc64.c' || echo '$(srcdir)/'`../cachegrind/cg-ppc64.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj: ../cachegrind/cg-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj `if test -f '../cachegrind/cg-ppc64.c'; then $(CYGPATH_W) '../cachegrind/cg-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-ppc64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-ppc64.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-ppc64.obj `if test -f '../cachegrind/cg-ppc64.c'; then $(CYGPATH_W) '../cachegrind/cg-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-ppc64.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o: ../cachegrind/cg-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o `test -f '../cachegrind/cg-arm.c' || echo '$(srcdir)/'`../cachegrind/cg-arm.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-arm.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.o `test -f '../cachegrind/cg-arm.c' || echo '$(srcdir)/'`../cachegrind/cg-arm.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj: ../cachegrind/cg-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj `if test -f '../cachegrind/cg-arm.c'; then $(CYGPATH_W) '../cachegrind/cg-arm.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-arm.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-arm.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-arm.obj `if test -f '../cachegrind/cg-arm.c'; then $(CYGPATH_W) '../cachegrind/cg-arm.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-arm.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o: ../cachegrind/cg-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o `test -f '../cachegrind/cg-s390x.c' || echo '$(srcdir)/'`../cachegrind/cg-s390x.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-s390x.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.o `test -f '../cachegrind/cg-s390x.c' || echo '$(srcdir)/'`../cachegrind/cg-s390x.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj: ../cachegrind/cg-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj `if test -f '../cachegrind/cg-s390x.c'; then $(CYGPATH_W) '../cachegrind/cg-s390x.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-s390x.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-s390x.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-s390x.obj `if test -f '../cachegrind/cg-s390x.c'; then $(CYGPATH_W) '../cachegrind/cg-s390x.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-s390x.c'; fi`
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o: ../cachegrind/cg-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o `test -f '../cachegrind/cg-mips32.c' || echo '$(srcdir)/'`../cachegrind/cg-mips32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-mips32.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.o `test -f '../cachegrind/cg-mips32.c' || echo '$(srcdir)/'`../cachegrind/cg-mips32.c
+
+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj: ../cachegrind/cg-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj -MD -MP -MF $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Tpo -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj `if test -f '../cachegrind/cg-mips32.c'; then $(CYGPATH_W) '../cachegrind/cg-mips32.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-mips32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Tpo $(DEPDIR)/callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='../cachegrind/cg-mips32.c' object='callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-cg-mips32.obj `if test -f '../cachegrind/cg-mips32.c'; then $(CYGPATH_W) '../cachegrind/cg-mips32.c'; else $(CYGPATH_W) '$(srcdir)/../cachegrind/cg-mips32.c'; fi`
+install-pkgincludeHEADERS: $(pkginclude_HEADERS)
+ @$(NORMAL_INSTALL)
+ test -z "$(pkgincludedir)" || $(MKDIR_P) "$(DESTDIR)$(pkgincludedir)"
+ @list='$(pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ for p in $$list; do \
+ if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+ echo "$$d$$p"; \
+ done | $(am__base_list) | \
+ while read files; do \
+ echo " $(INSTALL_HEADER) $$files '$(DESTDIR)$(pkgincludedir)'"; \
+ $(INSTALL_HEADER) $$files "$(DESTDIR)$(pkgincludedir)" || exit $$?; \
+ done
+
+uninstall-pkgincludeHEADERS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
+ test -n "$$files" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(pkgincludedir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(pkgincludedir)" && rm -f $$files
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+check: check-recursive
+all-am: Makefile $(PROGRAMS) $(SCRIPTS) $(HEADERS) all-local
+installdirs: installdirs-recursive
+installdirs-am:
+ for dir in "$(DESTDIR)$(bindir)" "$(DESTDIR)$(pkgincludedir)"; do \
+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ done
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-generic clean-local clean-noinstPROGRAMS \
+ mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am: install-pkgincludeHEADERS
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am: install-binSCRIPTS install-exec-local
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am: uninstall-binSCRIPTS uninstall-pkgincludeHEADERS
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+ install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am all-local check check-am clean clean-generic \
+ clean-local clean-noinstPROGRAMS ctags ctags-recursive \
+ distclean distclean-compile distclean-generic distclean-tags \
+ distdir dvi dvi-am html html-am info info-am install \
+ install-am install-binSCRIPTS install-data install-data-am \
+ install-dvi install-dvi-am install-exec install-exec-am \
+ install-exec-local install-html install-html-am install-info \
+ install-info-am install-man install-pdf install-pdf-am \
+ install-pkgincludeHEADERS install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ installdirs-am maintainer-clean maintainer-clean-generic \
+ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \
+ ps ps-am tags tags-recursive uninstall uninstall-am \
+ uninstall-binSCRIPTS uninstall-pkgincludeHEADERS
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+#----------------------------------------------------------------------------
+# General stuff
+#----------------------------------------------------------------------------
+
+all-local: inplace-noinst_PROGRAMS inplace-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/callgrind/bb.c b/main/callgrind/bb.c
index 5a0f465..58de2c2 100644
--- a/main/callgrind/bb.c
+++ b/main/callgrind/bb.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/callgrind/bbcc.c b/main/callgrind/bbcc.c
index ad8caeb..22dc16f 100644
--- a/main/callgrind/bbcc.c
+++ b/main/callgrind/bbcc.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -555,7 +555,9 @@
Addr sp;
BB* last_bb;
ThreadId tid;
- Int jmpkind, passed = 0, csp;
+ ClgJumpKind jmpkind;
+ Bool isConditionalJump;
+ Int passed = 0, csp;
Bool ret_without_call = False;
Int popcount_on_return = 1;
@@ -581,16 +583,8 @@
if (last_bb) {
passed = CLG_(current_state).jmps_passed;
CLG_ASSERT(passed <= last_bb->cjmp_count);
- if (passed == last_bb->cjmp_count) {
- jmpkind = last_bb->jmpkind;
-
- /* VEX always gives a Boring jump kind also when passed trough */
- if ((jmpkind == Ijk_Boring) &&
- (last_bb->offset + last_bb->instr_len == bb->offset))
- jmpkind = JmpNone;
- }
- else
- jmpkind = JmpCond;
+ jmpkind = last_bb->jmp[passed].jmpkind;
+ isConditionalJump = (passed < last_bb->cjmp_count);
/* if we are in a function which is skipped in the call graph, we
* do not increment the exe counter to produce cost (if simulation off),
@@ -612,7 +606,8 @@
}
}
else {
- jmpkind = JmpNone;
+ jmpkind = jk_None;
+ isConditionalJump = False;
}
/* Manipulate JmpKind if needed, only using BB specific info */
@@ -620,7 +615,7 @@
csp = CLG_(current_call_stack).sp;
/* A return not matching the top call in our callstack is a jump */
- if ( (jmpkind == Ijk_Ret) && (csp >0)) {
+ if ( (jmpkind == jk_Return) && (csp >0)) {
Int csp_up = csp-1;
call_entry* top_ce = &(CLG_(current_call_stack).entry[csp_up]);
@@ -650,14 +645,14 @@
}
}
if (popcount_on_return == 0) {
- jmpkind = Ijk_Boring;
+ jmpkind = jk_Jump;
ret_without_call = True;
}
}
/* Should this jump be converted to call or pop/call ? */
- if (( jmpkind != Ijk_Ret) &&
- ( jmpkind != Ijk_Call) && last_bb) {
+ if (( jmpkind != jk_Return) &&
+ ( jmpkind != jk_Call) && last_bb) {
/* We simulate a JMP/Cont to be a CALL if
* - jump is in another ELF object or section kind
@@ -701,30 +696,32 @@
}
}
- jmpkind = Ijk_Call;
+ jmpkind = jk_Call;
call_emulation = True;
}
}
- if (jmpkind == Ijk_Call)
+ if (jmpkind == jk_Call)
skip = CLG_(get_fn_node)(bb)->skip;
CLG_DEBUGIF(1) {
- if (jmpkind == JmpCond)
- VG_(printf)("Conditional");
- else if (jmpkind == JmpNone)
- VG_(printf)("None");
- else
- ppIRJumpKind( jmpkind );
-
- VG_(printf)(" %08lx -> %08lx, SP %08lx\n",
- last_bb ? bb_jmpaddr(last_bb) : 0,
- bb_addr(bb), sp);
+ if (isConditionalJump)
+ VG_(printf)("Cond-");
+ switch(jmpkind) {
+ case jk_None: VG_(printf)("Fall-through"); break;
+ case jk_Jump: VG_(printf)("Jump"); break;
+ case jk_Call: VG_(printf)("Call"); break;
+ case jk_Return: VG_(printf)("Return"); break;
+ default: tl_assert(0);
+ }
+ VG_(printf)(" %08lx -> %08lx, SP %08lx\n",
+ last_bb ? bb_jmpaddr(last_bb) : 0,
+ bb_addr(bb), sp);
}
/* Handle CALL/RET and update context to get correct BBCC */
- if (jmpkind == Ijk_Ret) {
+ if (jmpkind == jk_Return) {
if ((csp == 0) ||
((CLG_(current_fn_stack).top > CLG_(current_fn_stack).bottom) &&
@@ -745,10 +742,10 @@
Int unwind_count = CLG_(unwind_call_stack)(sp, 0);
if (unwind_count > 0) {
/* if unwinding was done, this actually is a return */
- jmpkind = Ijk_Ret;
+ jmpkind = jk_Return;
}
- if (jmpkind == Ijk_Call) {
+ if (jmpkind == jk_Call) {
delayed_push = True;
csp = CLG_(current_call_stack).sp;
@@ -811,10 +808,10 @@
if (delayed_push && !skip) {
if (CLG_(clo).skip_direct_recursion) {
- /* do not increment rec. level if called from
- * same function */
- if (!CLG_(current_state).bbcc ||
- (CLG_(current_state).bbcc->cxt->fn[0] != bbcc->cxt->fn[0]))
+ /* a call was detected, which means that the source BB != 0 */
+ CLG_ASSERT(CLG_(current_state).bbcc != 0);
+ /* only increment rec. level if called from different function */
+ if (CLG_(current_state).bbcc->cxt->fn[0] != bbcc->cxt->fn[0])
level++;
}
else level++;
@@ -848,8 +845,7 @@
bbcc, sp, skip);
}
- if (CLG_(clo).collect_jumps &&
- ((jmpkind == JmpCond) || (jmpkind == Ijk_Boring))) {
+ if (CLG_(clo).collect_jumps && (jmpkind == jk_Jump)) {
/* Handle conditional jumps followed, i.e. trace arcs
* This uses JCC structures, too */
@@ -857,15 +853,15 @@
jCC* jcc = CLG_(get_jcc)(last_bbcc, passed, bbcc);
CLG_ASSERT(jcc != 0);
// Change from default, and check if already changed
- if (jcc->jmpkind == Ijk_Call)
- jcc->jmpkind = jmpkind;
+ if (jcc->jmpkind == jk_Call)
+ jcc->jmpkind = isConditionalJump ? jk_CondJump : jk_Jump;
else {
// FIXME: Why can this fail?
// CLG_ASSERT(jcc->jmpkind == jmpkind);
}
jcc->call_counter++;
- if (jmpkind == JmpCond)
+ if (isConditionalJump)
CLG_(stat).jcnd_counter++;
else
CLG_(stat).jump_counter++;
diff --git a/main/callgrind/callgrind.h b/main/callgrind/callgrind.h
index 752d0af..196c5a4 100644
--- a/main/callgrind/callgrind.h
+++ b/main/callgrind/callgrind.h
@@ -13,7 +13,7 @@
This file is part of callgrind, a valgrind tool for cache simulation
and call tree tracing.
- Copyright (C) 2003-2011 Josef Weidendorfer. All rights reserved.
+ Copyright (C) 2003-2012 Josef Weidendorfer. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
diff --git a/main/callgrind/callstack.c b/main/callgrind/callstack.c
index 59dc117..294e437 100644
--- a/main/callgrind/callstack.c
+++ b/main/callgrind/callstack.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -235,8 +235,14 @@
/* return address is only is useful with a real call;
* used to detect RET w/o CALL */
- ret_addr = (from->bb->jmpkind == Ijk_Call) ?
- bb_addr(from->bb) + from->bb->instr_len : 0;
+ if (from->bb->jmp[jmp].jmpkind == jk_Call) {
+ UInt instr = from->bb->jmp[jmp].instr;
+ ret_addr = bb_addr(from->bb) +
+ from->bb->instr[instr].instr_offset +
+ from->bb->instr[instr].instr_size;
+ }
+ else
+ ret_addr = 0;
/* put jcc on call stack */
current_entry->jcc = jcc;
diff --git a/main/callgrind/clo.c b/main/callgrind/clo.c
index 6488bac..61afe62 100644
--- a/main/callgrind/clo.c
+++ b/main/callgrind/clo.c
@@ -2,10 +2,10 @@
This file is part of Callgrind, a Valgrind tool for call graph
profiling programs.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This tool is derived from and contains lot of code from Cachegrind
- Copyright (C) 2002-2011 Nicholas Nethercote (njn@valgrind.org)
+ Copyright (C) 2002-2012 Nicholas Nethercote (njn@valgrind.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/callgrind/command.c b/main/callgrind/command.c
deleted file mode 100644
index 5b9342a..0000000
--- a/main/callgrind/command.c
+++ /dev/null
@@ -1,535 +0,0 @@
-/*
- This file is part of Callgrind, a Valgrind tool for call graph
- profiling programs.
-
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
-
- This tool is derived from and contains lot of code from Cachegrind
- Copyright (C) 2002-2011 Nicholas Nethercote (njn@valgrind.org)
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/*
- * Functions related to interactive commands via "callgrind.cmd"
- */
-
-#include "config.h"
-#include "global.h"
-
-#include "pub_tool_threadstate.h" // VG_N_THREADS
-
-// Version for the syntax in command/result files for interactive control
-#define COMMAND_VERSION "1.0"
-
-static Char outbuf[FILENAME_LEN + FN_NAME_LEN + OBJ_NAME_LEN];
-
-static Char* command_file = 0;
-static Char* command_file2 = 0;
-static Char* current_command_file = 0;
-static Char* result_file = 0;
-static Char* result_file2 = 0;
-static Char* current_result_file = 0;
-static Char* info_file = 0;
-static Char* out_file = 0;
-
-static Int thisPID = 0;
-
-/**
- * Setup for interactive control of a callgrind run
- */
-static void setup_control(void)
-{
- Int fd, size;
- SysRes res;
- Char* dir;
- const HChar *tmpdir;
-
- CLG_ASSERT(thisPID != 0);
-
- fd = -1;
- dir = CLG_(get_out_directory)();
- out_file = CLG_(get_out_file)();
-
- /* name of command file */
- size = VG_(strlen)(dir) + VG_(strlen)(DEFAULT_COMMANDNAME) +10;
- command_file = (char*) CLG_MALLOC("cl.command.sc.1", size);
- CLG_ASSERT(command_file != 0);
- VG_(sprintf)(command_file, "%s/%s.%d",
- dir, DEFAULT_COMMANDNAME, thisPID);
-
- /* This is for compatibility with the "Force Now" Button of current
- * KCachegrind releases, as it doesn't use ".pid" to distinguish
- * different callgrind instances from same base directory.
- */
- command_file2 = (char*) CLG_MALLOC("cl.command.sc.2", size);
- CLG_ASSERT(command_file2 != 0);
- VG_(sprintf)(command_file2, "%s/%s",
- dir, DEFAULT_COMMANDNAME);
-
- size = VG_(strlen)(dir) + VG_(strlen)(DEFAULT_RESULTNAME) +10;
- result_file = (char*) CLG_MALLOC("cl.command.sc.3", size);
- CLG_ASSERT(result_file != 0);
- VG_(sprintf)(result_file, "%s/%s.%d",
- dir, DEFAULT_RESULTNAME, thisPID);
-
- /* If we get a command from a command file without .pid, use
- * a result file without .pid suffix
- */
- result_file2 = (char*) CLG_MALLOC("cl.command.sc.4", size);
- CLG_ASSERT(result_file2 != 0);
- VG_(sprintf)(result_file2, "%s/%s",
- dir, DEFAULT_RESULTNAME);
-
- tmpdir = VG_(tmpdir)();
- info_file = (char*) CLG_MALLOC("cl.command.sc.5",
- VG_(strlen)(tmpdir) +
- VG_(strlen)(DEFAULT_INFONAME) + 10);
- CLG_ASSERT(info_file != 0);
- VG_(sprintf)(info_file, "%s/%s.%d", tmpdir, DEFAULT_INFONAME, thisPID);
-
- CLG_DEBUG(1, "Setup for interactive control (PID: %d):\n", thisPID);
- CLG_DEBUG(1, " output file: '%s'\n", out_file);
- CLG_DEBUG(1, " command file: '%s'\n", command_file);
- CLG_DEBUG(1, " result file: '%s'\n", result_file);
- CLG_DEBUG(1, " info file: '%s'\n", info_file);
-
- /* create info file to indicate that we are running */
- res = VG_(open)(info_file, VKI_O_WRONLY|VKI_O_TRUNC, 0);
- if (sr_isError(res)) {
- res = VG_(open)(info_file, VKI_O_CREAT|VKI_O_WRONLY,
- VKI_S_IRUSR|VKI_S_IWUSR);
- if (sr_isError(res)) {
- VG_(message)(Vg_DebugMsg,
- "warning: can't write info file '%s'\n", info_file);
- info_file = 0;
- fd = -1;
- }
- }
- if (!sr_isError(res))
- fd = (Int) sr_Res(res);
- if (fd>=0) {
- Char buf[512];
- Int i;
-
- WRITE_STR3(fd,
- "# This file is generated by Callgrind-" VERSION ".\n"
- "# It is used to enable controlling the supervision of\n"
- "# '", VG_(args_the_exename), "'\n"
- "# by external tools.\n\n");
-
- VG_(sprintf)(buf, "version: " COMMAND_VERSION "\n");
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- WRITE_STR3(fd, "base: ", dir, "\n");
- WRITE_STR3(fd, "dumps: ", out_file, "\n");
- WRITE_STR3(fd, "control: ", command_file, "\n");
- WRITE_STR3(fd, "result: ", result_file, "\n");
-
- WRITE_STR2(fd, "cmd: ", VG_(args_the_exename));
- for (i = 0; i < VG_(sizeXA)( VG_(args_for_client) ); i++) {
- HChar* arg = * (HChar**)VG_(indexXA)( VG_(args_for_client), i );
- if (!arg) continue;
- WRITE_STR2(fd, " ", arg);
- }
- VG_(write)(fd, "\n", 1);
- VG_(close)(fd);
- }
-}
-
-void CLG_(init_command)()
-{
- thisPID = VG_(getpid)();
- setup_control();
-}
-
-void CLG_(finish_command)()
-{
- /* unlink info file */
- if (info_file) VG_(unlink)(info_file);
-}
-
-
-static Int createRes(Int fd)
-{
- SysRes res;
-
- if (fd > -2) return fd;
-
- /* fd == -2: No error, but we need to create the file */
- CLG_ASSERT(current_result_file != 0);
- res = VG_(open)(current_result_file,
- VKI_O_CREAT|VKI_O_WRONLY|VKI_O_TRUNC,
- VKI_S_IRUSR|VKI_S_IWUSR);
-
- /* VG_(open) can return any negative number on error. Remap errors to -1,
- * to not confuse it with our special value -2
- */
- if (sr_isError(res)) fd = -1;
- else fd = (Int) sr_Res(res);
-
- return fd;
-}
-
-/* Run Info: Persistant information of the callgrind run */
-static Int dump_info(Int fd)
-{
- Char* buf = outbuf;
- int i;
-
- if ( (fd = createRes(fd)) <0) return fd;
-
- /* creator */
- VG_(sprintf)(buf, "creator: callgrind-" VERSION "\n");
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- /* version */
- VG_(sprintf)(buf, "version: " COMMAND_VERSION "\n");
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- /* "pid:" line */
- VG_(sprintf)(buf, "pid: %d\n", VG_(getpid)());
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- /* "base:" line */
- WRITE_STR3(fd, "base: ", out_file, "\n");
-
- /* "cmd:" line */
- WRITE_STR2(fd, "cmd: ", VG_(args_the_exename));
- for (i = 0; i < VG_(sizeXA)( VG_(args_for_client) ); i++) {
- HChar* arg = * (HChar**)VG_(indexXA)( VG_(args_for_client), i );
- if (!arg) continue;
- WRITE_STR2(fd, " ", arg);
- }
- VG_(write)(fd, "\n", 1);
-
- return fd;
-}
-
-
-/* Helper for dump_state */
-
-Int dump_fd;
-
-void static dump_state_of_thread(thread_info* ti)
-{
- Char* buf = outbuf;
- int t = CLG_(current_tid);
- Int p, i;
- static FullCost sum = 0, tmp = 0;
- BBCC *from, *to;
- call_entry* ce;
-
- p = VG_(sprintf)(buf, "events-%d: ", t);
- CLG_(init_cost_lz)( CLG_(sets).full, &sum );
- CLG_(copy_cost_lz)( CLG_(sets).full, &tmp, ti->lastdump_cost );
- CLG_(add_diff_cost)( CLG_(sets).full, sum,
- ti->lastdump_cost,
- ti->states.entry[0]->cost);
- CLG_(copy_cost)( CLG_(sets).full, ti->lastdump_cost, tmp );
- p += CLG_(sprint_mappingcost)(buf + p, CLG_(dumpmap), sum);
- p += VG_(sprintf)(buf+p, "\n");
- VG_(write)(dump_fd, (void*)buf, p);
-
- p = VG_(sprintf)(buf, "frames-%d: %d\n", t,
- CLG_(current_call_stack).sp);
- VG_(write)(dump_fd, (void*)buf, p);
- ce = 0;
- for(i = 0; i < CLG_(current_call_stack).sp; i++) {
- ce = CLG_(get_call_entry)(i);
- /* if this frame is skipped, we don't have counters */
- if (!ce->jcc) continue;
-
- from = ce->jcc->from;
- p = VG_(sprintf)(buf, "function-%d-%d: %s\n",t, i,
- from->cxt->fn[0]->name);
- VG_(write)(dump_fd, (void*)buf, p);
-
- p = VG_(sprintf)(buf, "calls-%d-%d: ",t, i);
- p+= VG_(sprintf)(buf+p, "%llu\n", ce->jcc->call_counter);
- VG_(write)(dump_fd, (void*)buf, p);
-
- /* FIXME: EventSets! */
- CLG_(copy_cost)( CLG_(sets).full, sum, ce->jcc->cost );
- CLG_(copy_cost)( CLG_(sets).full, tmp, ce->enter_cost );
- CLG_(add_diff_cost)( CLG_(sets).full, sum,
- ce->enter_cost, CLG_(current_state).cost );
- CLG_(copy_cost)( CLG_(sets).full, ce->enter_cost, tmp );
-
- p = VG_(sprintf)(buf, "events-%d-%d: ",t, i);
- p += CLG_(sprint_mappingcost)(buf + p, CLG_(dumpmap), sum );
- p += VG_(sprintf)(buf+p, "\n");
- VG_(write)(dump_fd, (void*)buf, p);
- }
- if (ce && ce->jcc) {
- to = ce->jcc->to;
- p = VG_(sprintf)(buf, "function-%d-%d: %s\n",t, i,
- to->cxt->fn[0]->name );
- VG_(write)(dump_fd, (void*)buf, p);
- }
-}
-
-/* Dump info on current callgrind state */
-static Int dump_state(Int fd)
-{
- Char* buf = outbuf;
- thread_info** th;
- int t, p;
- Int orig_tid = CLG_(current_tid);
-
- if ( (fd = createRes(fd)) <0) return fd;
-
- VG_(sprintf)(buf, "instrumentation: %s\n",
- CLG_(instrument_state) ? "on":"off");
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- if (!CLG_(instrument_state)) return fd;
-
- VG_(sprintf)(buf, "executed-bbs: %llu\n", CLG_(stat).bb_executions);
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- VG_(sprintf)(buf, "executed-calls: %llu\n", CLG_(stat).call_counter);
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- VG_(sprintf)(buf, "distinct-bbs: %d\n", CLG_(stat).distinct_bbs);
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- VG_(sprintf)(buf, "distinct-calls: %d\n", CLG_(stat).distinct_jccs);
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- VG_(sprintf)(buf, "distinct-functions: %d\n", CLG_(stat).distinct_fns);
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- VG_(sprintf)(buf, "distinct-contexts: %d\n", CLG_(stat).distinct_contexts);
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- /* "events:" line. Given here because it will be dynamic in the future */
- p = VG_(sprintf)(buf, "events: ");
- CLG_(sprint_eventmapping)(buf+p, CLG_(dumpmap));
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
- VG_(write)(fd, "\n", 1);
-
- /* "part:" line (number of last part. Is 0 at start */
- VG_(sprintf)(buf, "\npart: %d\n", CLG_(get_dump_counter)());
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- /* threads */
- th = CLG_(get_threads)();
- p = VG_(sprintf)(buf, "threads:");
- for(t=1;t<VG_N_THREADS;t++) {
- if (!th[t]) continue;
- p += VG_(sprintf)(buf+p, " %d", t);
- }
- p += VG_(sprintf)(buf+p, "\n");
- VG_(write)(fd, (void*)buf, p);
-
- VG_(sprintf)(buf, "current-tid: %d\n", orig_tid);
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- /* current event counters */
- dump_fd = fd;
- CLG_(forall_threads)(dump_state_of_thread);
-
- return fd;
-}
-
-void CLG_(check_command)()
-{
- /* check for dumps needed */
- static Char buf[512];
- static Char cmdBuffer[512];
- Char *cmdPos = 0, *cmdNextLine = 0;
- Int fd, bytesRead = 0, do_kill = 0;
- SysRes res;
- Int currentPID;
- static Int check_counter = 0;
-
- /* Check for PID change, i.e. whether we run as child after a fork.
- * If yes, we setup interactive control for the new process
- */
- currentPID = VG_(getpid)();
- if (thisPID != currentPID) {
- thisPID = currentPID;
- setup_control();
- }
-
- /* Toggle between 2 command files, with/without ".pid" postfix
- * (needed for compatibility with KCachegrind, which wants to trigger
- * a dump by writing into a command file without the ".pid" postfix)
- */
- check_counter++;
- if (check_counter % 2) {
- current_command_file = command_file;
- current_result_file = result_file;
- }
- else {
- current_command_file = command_file2;
- current_result_file = result_file2;
- }
-
- res = VG_(open)(current_command_file, VKI_O_RDONLY,0);
- if (!sr_isError(res)) {
- fd = (Int) sr_Res(res);
- bytesRead = VG_(read)(fd,cmdBuffer,500);
- cmdBuffer[500] = 0; /* no command overrun please */
- VG_(close)(fd);
- /* don't delete command file on read error (e.g. EAGAIN) */
- if (bytesRead>0) {
- cmdPos = cmdBuffer;
- }
- }
-
- /* force creation of result file if needed */
- fd = -2;
-
- while((bytesRead>0) && *cmdPos) {
-
- /* Calculate pointer for next line */
- cmdNextLine = cmdPos+1;
- while((bytesRead>0) && *cmdNextLine && (*cmdNextLine != '\n')) {
- cmdNextLine++;
- bytesRead--;
- }
- if ((bytesRead>0) && (*cmdNextLine == '\n')) {
- *cmdNextLine = 0;
- cmdNextLine++;
- bytesRead--;
- }
-
- /* Command with integer option */
- if ((*cmdPos >= '0') && (*cmdPos <='9')) {
- int value = *cmdPos-'0';
- cmdPos++;
- while((*cmdPos >= '0') && (*cmdPos <='9')) {
- value = 10*value + (*cmdPos-'0');
- cmdPos++;
- }
- while((*cmdPos == ' ') || (*cmdPos == '\t')) cmdPos++;
-
- switch(*cmdPos) {
-#if CLG_ENABLE_DEBUG
- /* verbosity */
- case 'V':
- case 'v':
- CLG_(clo).verbose = value;
- break;
-#endif
- default:
- break;
- }
-
- cmdPos = cmdNextLine;
- continue;
- }
-
- /* Command with boolean/switch option */
- if ((*cmdPos=='+') ||
- (*cmdPos=='-')) {
- int value = (cmdPos[0] == '+');
- cmdPos++;
- while((*cmdPos == ' ') || (*cmdPos == '\t')) cmdPos++;
-
- switch(*cmdPos) {
- case 'I':
- case 'i':
- CLG_(set_instrument_state)("Command", value);
- break;
-
- default:
- break;
- }
-
- cmdPos = cmdNextLine;
- continue;
- }
-
- /* regular command */
- switch(*cmdPos) {
- case 'D':
- case 'd':
- /* DUMP */
-
- /* skip command */
- while(*cmdPos && (*cmdPos != ' ')) cmdPos++;
- if (*cmdPos)
- VG_(sprintf)(buf, "Dump Command:%s", cmdPos);
- else
- VG_(sprintf)(buf, "Dump Command");
- CLG_(dump_profile)(buf, False);
- break;
-
- case 'Z':
- case 'z':
- CLG_(zero_all_cost)(False);
- break;
-
- case 'K':
- case 'k':
- /* Kill: Delay to be able to remove command file before. */
- do_kill = 1;
- break;
-
- case 'I':
- case 'i':
- fd = dump_info(fd);
- break;
-
- case 's':
- case 'S':
- fd = dump_state(fd);
- break;
-
- case 'O':
- case 'o':
- /* Options Info */
- if ( (fd = createRes(fd)) <0) break;
-
- VG_(sprintf)(buf, "\ndesc: Option: --skip-plt=%s\n",
- CLG_(clo).skip_plt ? "yes" : "no");
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
- VG_(sprintf)(buf, "desc: Option: --collect-jumps=%s\n",
- CLG_(clo).collect_jumps ? "yes" : "no");
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
- VG_(sprintf)(buf, "desc: Option: --separate-recs=%d\n",
- CLG_(clo).separate_recursions);
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
- VG_(sprintf)(buf, "desc: Option: --separate-callers=%d\n",
- CLG_(clo).separate_callers);
- VG_(write)(fd, (void*)buf, VG_(strlen)(buf));
-
- break;
-
- default:
- break;
- }
-
- cmdPos = cmdNextLine;
- }
-
- /* If command executed, delete command file */
- if (cmdPos) VG_(unlink)(current_command_file);
- if (fd>=0) VG_(close)(fd);
-
- if (do_kill) {
- VG_(message)(Vg_UserMsg,
- "Killed because of command from %s\n",
- current_command_file);
- CLG_(fini)(0);
- VG_(exit)(1);
- }
-}
diff --git a/main/callgrind/context.c b/main/callgrind/context.c
index 42d8e4f..dcadcb6 100644
--- a/main/callgrind/context.c
+++ b/main/callgrind/context.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/callgrind/costs.c b/main/callgrind/costs.c
index 357fcb4..32cdfbf 100644
--- a/main/callgrind/costs.c
+++ b/main/callgrind/costs.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/callgrind/debug.c b/main/callgrind/debug.c
index 6d21d48..7f5a8e7 100644
--- a/main/callgrind/debug.c
+++ b/main/callgrind/debug.c
@@ -2,10 +2,10 @@
This file is part of Callgrind, a Valgrind tool for call graph
profiling programs.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This tool is derived from and contains lot of code from Cachegrind
- Copyright (C) 2002-2011 Nicholas Nethercote (njn@valgrind.org)
+ Copyright (C) 2002-2012 Nicholas Nethercote (njn@valgrind.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/callgrind/docs/cl-manual.xml b/main/callgrind/docs/cl-manual.xml
index 994ddcb..ab8d9bb 100644
--- a/main/callgrind/docs/cl-manual.xml
+++ b/main/callgrind/docs/cl-manual.xml
@@ -93,11 +93,11 @@
features.</para>
<para>Callgrind's ability to detect function calls and returns depends
-on the instruction set of the platform it is run on. It works best
-on x86 and amd64, and unfortunately currently does not work so well
-on PowerPC code. This is because there are no explicit call or return
-instructions in the PowerPC instruction set, so Callgrind has to rely
-on heuristics to detect calls and returns.</para>
+on the instruction set of the platform it is run on. It works best on
+x86 and amd64, and unfortunately currently does not work so well on
+PowerPC, ARM, Thumb or MIPS code. This is because there are no explicit
+call or return instructions in these instruction sets, so Callgrind
+has to rely on heuristics to detect calls and returns.</para>
</sect2>
diff --git a/main/callgrind/dump.c b/main/callgrind/dump.c
index 7db9ec5..c073af0 100644
--- a/main/callgrind/dump.c
+++ b/main/callgrind/dump.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -669,7 +669,7 @@
target.file = last->file;
}
- if ((jcc->jmpkind == JmpCond) || (jcc->jmpkind == Ijk_Boring)) {
+ if ((jcc->jmpkind == jk_CondJump) || (jcc->jmpkind == jk_Jump)) {
/* this is a JCC for a followed conditional or boring jump. */
CLG_ASSERT(CLG_(is_zero_cost)( CLG_(sets).full, jcc->cost));
@@ -703,7 +703,7 @@
print_fn(fd, outbuf, "jfn", jcc->to->cxt->fn[0]);
}
- if (jcc->jmpkind == JmpCond) {
+ if (jcc->jmpkind == jk_CondJump) {
/* format: jcnd=<followed>/<executions> <target> */
VG_(sprintf)(outbuf, "jcnd=%llu/%llu ",
jcc->call_counter, ecounter);
@@ -834,7 +834,7 @@
if (bb->jmp[jmp].instr == instr) {
jcc_count=0;
for(jcc=bbcc->jmp[jmp].jcc_list; jcc; jcc=jcc->next_from)
- if (((jcc->jmpkind != Ijk_Call) && (jcc->call_counter >0)) ||
+ if (((jcc->jmpkind != jk_Call) && (jcc->call_counter >0)) ||
(!CLG_(is_zero_cost)( CLG_(sets).full, jcc->cost )))
jcc_count++;
@@ -848,7 +848,7 @@
fprint_apos(fd, &(currCost->p), last, bbcc->cxt->fn[0]->file);
something_written = True;
for(jcc=bbcc->jmp[jmp].jcc_list; jcc; jcc=jcc->next_from) {
- if (((jcc->jmpkind != Ijk_Call) && (jcc->call_counter >0)) ||
+ if (((jcc->jmpkind != jk_Call) && (jcc->call_counter >0)) ||
(!CLG_(is_zero_cost)( CLG_(sets).full, jcc->cost )))
fprint_jcc(fd, jcc, &(currCost->p), last, ecounter);
}
@@ -867,7 +867,7 @@
jcc_count = 0;
for(jcc=bbcc->jmp[jmp].jcc_list; jcc; jcc=jcc->next_from) {
/* yes, if JCC only counts jmp arcs or cost >0 */
- if ( ((jcc->jmpkind != Ijk_Call) && (jcc->call_counter >0)) ||
+ if ( ((jcc->jmpkind != jk_Call) && (jcc->call_counter >0)) ||
(!CLG_(is_zero_cost)( CLG_(sets).full, jcc->cost )))
jcc_count++;
}
@@ -901,7 +901,7 @@
if (jcc_count > 0)
for(jcc=bbcc->jmp[jmp].jcc_list; jcc; jcc=jcc->next_from) {
CLG_ASSERT(jcc->jmp == jmp);
- if ( ((jcc->jmpkind != Ijk_Call) && (jcc->call_counter >0)) ||
+ if ( ((jcc->jmpkind != jk_Call) && (jcc->call_counter >0)) ||
(!CLG_(is_zero_cost)( CLG_(sets).full, jcc->cost )))
fprint_jcc(fd, jcc, &(currCost->p), last, ecounter);
diff --git a/main/callgrind/events.c b/main/callgrind/events.c
index 9d38b06..af5c568 100644
--- a/main/callgrind/events.c
+++ b/main/callgrind/events.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/callgrind/events.h b/main/callgrind/events.h
index 5a4cddd..aa59d54 100644
--- a/main/callgrind/events.h
+++ b/main/callgrind/events.h
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/callgrind/fn.c b/main/callgrind/fn.c
index 6a50306..099d20c 100644
--- a/main/callgrind/fn.c
+++ b/main/callgrind/fn.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/callgrind/global.h b/main/callgrind/global.h
index 19065da..b10165d 100644
--- a/main/callgrind/global.h
+++ b/main/callgrind/global.h
@@ -51,9 +51,6 @@
/*------------------------------------------------------------*/
#define DEFAULT_OUTFORMAT "callgrind.out.%p"
-#define DEFAULT_COMMANDNAME "callgrind.cmd"
-#define DEFAULT_RESULTNAME "callgrind.res"
-#define DEFAULT_INFONAME "callgrind.info"
typedef struct _CommandLineOptions CommandLineOptions;
struct _CommandLineOptions {
@@ -232,6 +229,18 @@
typedef ULong* FullCost; /* Simulator + User */
+/* The types of control flow changes that can happen between
+ * execution of two BBs in a thread.
+ */
+typedef enum {
+ jk_None = 0, /* no explicit change by a guest instruction */
+ jk_Jump, /* regular jump */
+ jk_Call,
+ jk_Return,
+ jk_CondJump /* conditional jump taken (only used as jCC type) */
+} ClgJumpKind;
+
+
/* JmpCall cost center
* for subroutine call (from->bb->jmp_addr => to->bb->addr)
*
@@ -251,11 +260,9 @@
* After updating, <last> is set to current event counters. Thus,
* events are not counted twice for recursive calls (TODO: True?)
*/
-#define JmpNone (Ijk_Boring+30)
-#define JmpCond (Ijk_Boring+31)
struct _jCC {
- Int jmpkind; /* JmpCall, JmpBoring, JmpCond */
+ ClgJumpKind jmpkind; /* jk_Call, jk_Jump, jk_CondJump */
jCC* next_hash; /* for hash entry chain */
jCC* next_from; /* next JCC from a BBCC */
BBCC *from, *to; /* call arc from/to this BBCC */
@@ -279,13 +286,14 @@
};
+
/*
- * Info for a conditional jump in a basic block
+ * Info for a side exit in a BB
*/
typedef struct _CJmpInfo CJmpInfo;
struct _CJmpInfo {
- UInt instr; /* instruction index in this basic block */
- Bool skip; /* Cond.Jumps to next instruction should be ignored */
+ UInt instr; /* instruction index for BB.instr array */
+ ClgJumpKind jmpkind; /* jump kind when leaving BB at this side exit */
};
@@ -322,11 +330,10 @@
BBCC* last_bbcc; /* Temporary: Cached for faster access (LRU) */
/* filled by CLG_(instrument) if not seen before */
- UInt cjmp_count; /* number of conditional exits */
+ UInt cjmp_count; /* number of side exits */
CJmpInfo* jmp; /* array of info for condition jumps,
* allocated directly after this struct */
- Int jmpkind; /* remember jump kind of final exit */
- Bool cjmp_inverted; /* condition of last cond.jump can be inverted by VEX */
+ Bool cjmp_inverted; /* is last side exit actually fall through? */
UInt instr_len;
UInt cost_count;
@@ -360,12 +367,12 @@
/*
- * Info for a conditional jump in a basic block
+ * Cost info for a side exits from a BB
*/
typedef struct _JmpData JmpData;
struct _JmpData {
ULong ecounter; /* number of times the BB was left at this exit */
- jCC* jcc_list; /* JCCs for Cond.Jumps from this exit */
+ jCC* jcc_list; /* JCCs used for this exit */
};
@@ -723,11 +730,6 @@
Int CLG_(get_dump_counter)(void);
void CLG_(fini)(Int exitcode);
-/* from command.c */
-void CLG_(init_command)(void);
-void CLG_(check_command)(void);
-void CLG_(finish_command)(void);
-
/* from bb.c */
void CLG_(init_bb_hash)(void);
bb_hash* CLG_(get_bb_hash)(void);
@@ -825,6 +827,8 @@
/* Function active counter array, indexed by function number */
extern UInt* CLG_(fn_active_array);
extern Bool CLG_(instrument_state);
+ /* min of L1 and LL cache line sizes */
+extern Int CLG_(min_line_size);
extern call_stack CLG_(current_call_stack);
extern fn_stack CLG_(current_fn_stack);
diff --git a/main/callgrind/jumps.c b/main/callgrind/jumps.c
index f40665b..633152e 100644
--- a/main/callgrind/jumps.c
+++ b/main/callgrind/jumps.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -152,7 +152,7 @@
jcc->from = from;
jcc->jmp = jmp;
jcc->to = to;
- jcc->jmpkind = Ijk_Call;
+ jcc->jmpkind = jk_Call;
jcc->call_counter = 0;
jcc->cost = 0;
diff --git a/main/callgrind/main.c b/main/callgrind/main.c
index c44f360..80585fe 100644
--- a/main/callgrind/main.c
+++ b/main/callgrind/main.c
@@ -8,10 +8,10 @@
This file is part of Callgrind, a Valgrind tool for call graph
profiling programs.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This tool is derived from and contains code from Cachegrind
- Copyright (C) 2002-2011 Nicholas Nethercote (njn@valgrind.org)
+ Copyright (C) 2002-2012 Nicholas Nethercote (njn@valgrind.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -52,6 +52,10 @@
/* thread and signal handler specific */
exec_state CLG_(current_state);
+/* min of L1 and LL cache line sizes. This only gets set to a
+ non-zero value if we are doing cache simulation. */
+Int CLG_(min_line_size) = 0;
+
/*------------------------------------------------------------*/
/*--- Statistics ---*/
@@ -613,8 +617,9 @@
{
Event* evt;
tl_assert(isIRAtom(ea));
- tl_assert(datasize >= 1 && datasize <= MIN_LINE_SIZE);
+ tl_assert(datasize >= 1);
if (!CLG_(clo).simulate_cache) return;
+ tl_assert(datasize <= CLG_(min_line_size));
if (clgs->events_used == N_EVENTS)
flushEvents(clgs);
@@ -634,8 +639,9 @@
Event* lastEvt;
Event* evt;
tl_assert(isIRAtom(ea));
- tl_assert(datasize >= 1 && datasize <= MIN_LINE_SIZE);
+ tl_assert(datasize >= 1);
if (!CLG_(clo).simulate_cache) return;
+ tl_assert(datasize <= CLG_(min_line_size));
/* Is it possible to merge this write with the preceding read? */
lastEvt = &clgs->events[clgs->events_used-1];
@@ -905,10 +911,9 @@
VexGuestExtents* vge,
IRType gWordTy, IRType hWordTy )
{
- Int i, isize;
+ Int i;
IRStmt* st;
Addr origAddr;
- Addr64 cia; /* address of current insn */
InstrInfo* curr_inode = NULL;
ClgState clgs;
UInt cJumps = 0;
@@ -944,10 +949,9 @@
st = sbIn->stmts[i];
CLG_ASSERT(Ist_IMark == st->tag);
- origAddr = (Addr)st->Ist.IMark.addr;
- cia = st->Ist.IMark.addr;
- isize = st->Ist.IMark.len;
- CLG_ASSERT(origAddr == st->Ist.IMark.addr); // XXX: check no overflow
+ origAddr = (Addr)st->Ist.IMark.addr + (Addr)st->Ist.IMark.delta;
+ CLG_ASSERT(origAddr == st->Ist.IMark.addr
+ + st->Ist.IMark.delta); // XXX: check no overflow
/* Get BB struct (creating if necessary).
* JS: The hash table is keyed with orig_addr_noredir -- important!
@@ -977,8 +981,8 @@
break;
case Ist_IMark: {
- cia = st->Ist.IMark.addr;
- isize = st->Ist.IMark.len;
+ Addr64 cia = st->Ist.IMark.addr + st->Ist.IMark.delta;
+ Int isize = st->Ist.IMark.len;
CLG_ASSERT(clgs.instr_offset == (Addr)cia - origAddr);
// If Vex fails to decode an instruction, the size will be zero.
// Pretend otherwise.
@@ -1029,8 +1033,8 @@
// instructions will be done inaccurately, but they're
// very rare and this avoids errors from hitting more
// than two cache lines in the simulation.
- if (dataSize > MIN_LINE_SIZE)
- dataSize = MIN_LINE_SIZE;
+ if (CLG_(clo).simulate_cache && dataSize > CLG_(min_line_size))
+ dataSize = CLG_(min_line_size);
if (d->mFx == Ifx_Read || d->mFx == Ifx_Modify)
addEvent_Dr( &clgs, curr_inode, dataSize, d->mAddr );
if (d->mFx == Ifx_Write || d->mFx == Ifx_Modify)
@@ -1148,8 +1152,20 @@
CLG_ASSERT(clgs.ii_index>0);
if (!clgs.seen_before) {
- clgs.bb->jmp[cJumps].instr = clgs.ii_index-1;
- clgs.bb->jmp[cJumps].skip = False;
+ ClgJumpKind jk;
+
+ if (st->Ist.Exit.jk == Ijk_Call) jk = jk_Call;
+ else if (st->Ist.Exit.jk == Ijk_Ret) jk = jk_Return;
+ else {
+ if (IRConst2Addr(st->Ist.Exit.dst) ==
+ origAddr + curr_inode->instr_offset + curr_inode->instr_size)
+ jk = jk_None;
+ else
+ jk = jk_Jump;
+ }
+
+ clgs.bb->jmp[cJumps].instr = clgs.ii_index-1;
+ clgs.bb->jmp[cJumps].jmpkind = jk;
}
/* Update global variable jmps_passed before the jump
@@ -1214,18 +1230,45 @@
CLG_ASSERT(clgs.bb->cjmp_count == cJumps);
CLG_ASSERT(clgs.bb->instr_count = clgs.ii_index);
- /* This stores the instr of the call/ret at BB end */
- clgs.bb->jmp[cJumps].instr = clgs.ii_index-1;
+ /* Info for final exit from BB */
+ {
+ ClgJumpKind jk;
+
+ if (sbIn->jumpkind == Ijk_Call) jk = jk_Call;
+ else if (sbIn->jumpkind == Ijk_Ret) jk = jk_Return;
+ else {
+ jk = jk_Jump;
+ if ((sbIn->next->tag == Iex_Const) &&
+ (IRConst2Addr(sbIn->next->Iex.Const.con) ==
+ origAddr + clgs.instr_offset))
+ jk = jk_None;
+ }
+ clgs.bb->jmp[cJumps].jmpkind = jk;
+ /* Instruction index of the call/ret at BB end
+ * (it is wrong for fall-through, but does not matter) */
+ clgs.bb->jmp[cJumps].instr = clgs.ii_index-1;
+ }
+
+ /* swap information of last exit with final exit if inverted */
+ if (clgs.bb->cjmp_inverted) {
+ ClgJumpKind jk;
+ UInt instr;
+
+ jk = clgs.bb->jmp[cJumps].jmpkind;
+ clgs.bb->jmp[cJumps].jmpkind = clgs.bb->jmp[cJumps-1].jmpkind;
+ clgs.bb->jmp[cJumps-1].jmpkind = jk;
+ instr = clgs.bb->jmp[cJumps].instr;
+ clgs.bb->jmp[cJumps].instr = clgs.bb->jmp[cJumps-1].instr;
+ clgs.bb->jmp[cJumps-1].instr = instr;
+ }
if (clgs.seen_before) {
CLG_ASSERT(clgs.bb->cost_count == update_cost_offsets(&clgs));
CLG_ASSERT(clgs.bb->instr_len = clgs.instr_offset);
- CLG_ASSERT(clgs.bb->jmpkind == sbIn->jumpkind);
}
else {
clgs.bb->cost_count = update_cost_offsets(&clgs);
clgs.bb->instr_len = clgs.instr_offset;
- clgs.bb->jmpkind = sbIn->jumpkind;
}
CLG_DEBUG(3, "- instrument(BB %#lx): byteLen %u, CJumps %u, CostLen %u\n",
@@ -1708,8 +1751,6 @@
CLG_(dump_profile)(0, False);
- CLG_(finish_command)();
-
if (VG_(clo_verbosity) == 0) return;
/* Hash table stats */
@@ -1861,7 +1902,6 @@
}
CLG_(init_dumps)();
- CLG_(init_command)();
(*CLG_(cachesim).post_clo_init)();
@@ -1891,7 +1931,7 @@
VG_(details_name) ("Callgrind");
VG_(details_version) (NULL);
VG_(details_description) ("a call-graph generating cache profiler");
- VG_(details_copyright_author)("Copyright (C) 2002-2011, and GNU GPL'd, "
+ VG_(details_copyright_author)("Copyright (C) 2002-2012, and GNU GPL'd, "
"by Josef Weidendorfer et al.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 500 );
diff --git a/main/callgrind/sim.c b/main/callgrind/sim.c
index c1deff7..2348cbe 100644
--- a/main/callgrind/sim.c
+++ b/main/callgrind/sim.c
@@ -7,10 +7,10 @@
This file is part of Callgrind, a Valgrind tool for call graph
profiling programs.
- Copyright (C) 2003-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2003-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This tool is derived from and contains code from Cachegrind
- Copyright (C) 2002-2011 Nicholas Nethercote (njn@valgrind.org)
+ Copyright (C) 2002-2012 Nicholas Nethercote (njn@valgrind.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -1307,6 +1307,28 @@
D1.name = "D1";
LL.name = "LL";
+ // min_line_size is used to make sure that we never feed
+ // accesses to the simulator straddling more than two
+ // cache lines at any cache level
+ CLG_(min_line_size) = (I1c.line_size < D1c.line_size)
+ ? I1c.line_size : D1c.line_size;
+ CLG_(min_line_size) = (LLc.line_size < CLG_(min_line_size))
+ ? LLc.line_size : CLG_(min_line_size);
+
+ Int largest_load_or_store_size
+ = VG_(machine_get_size_of_largest_guest_register)();
+ if (CLG_(min_line_size) < largest_load_or_store_size) {
+ /* We can't continue, because the cache simulation might
+ straddle more than 2 lines, and it will assert. So let's
+ just stop before we start. */
+ VG_(umsg)("Callgrind: cannot continue: the minimum line size (%d)\n",
+ (Int)CLG_(min_line_size));
+ VG_(umsg)(" must be equal to or larger than the maximum register size (%d)\n",
+ largest_load_or_store_size );
+ VG_(umsg)(" but it is not. Exiting now.\n");
+ VG_(exit)(1);
+ }
+
cachesim_initcache(I1c, &I1);
cachesim_initcache(D1c, &D1);
cachesim_initcache(LLc, &LL);
diff --git a/main/callgrind/tests/Makefile.in b/main/callgrind/tests/Makefile.in
new file mode 100644
index 0000000..98d87ce
--- /dev/null
+++ b/main/callgrind/tests/Makefile.in
@@ -0,0 +1,876 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = clreq$(EXEEXT) simwork$(EXEEXT) threads$(EXEEXT)
+subdir = callgrind/tests
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+clreq_SOURCES = clreq.c
+clreq_OBJECTS = clreq.$(OBJEXT)
+clreq_LDADD = $(LDADD)
+simwork_SOURCES = simwork.c
+simwork_OBJECTS = simwork.$(OBJEXT)
+simwork_LDADD = $(LDADD)
+threads_SOURCES = threads.c
+threads_OBJECTS = threads.$(OBJEXT)
+threads_DEPENDENCIES =
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = clreq.c simwork.c threads.c
+DIST_SOURCES = clreq.c simwork.c threads.c
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+SUBDIRS = .
+DIST_SUBDIRS = .
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ clreq.vgtest clreq.stderr.exp \
+ simwork1.vgtest simwork1.stdout.exp simwork1.stderr.exp \
+ simwork2.vgtest simwork2.stdout.exp simwork2.stderr.exp \
+ simwork3.vgtest simwork3.stdout.exp simwork3.stderr.exp \
+ simwork-both.vgtest simwork-both.stdout.exp simwork-both.stderr.exp \
+ simwork-branch.vgtest simwork-branch.stdout.exp simwork-branch.stderr.exp \
+ simwork-cache.vgtest simwork-cache.stdout.exp simwork-cache.stderr.exp \
+ notpower2.vgtest notpower2.stderr.exp \
+ notpower2-wb.vgtest notpower2-wb.stderr.exp \
+ notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \
+ notpower2-use.vgtest notpower2-use.stderr.exp \
+ threads.vgtest threads.stderr.exp \
+ threads-use.vgtest threads-use.stderr.exp
+
+threads_LDADD = -lpthread
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign callgrind/tests/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign callgrind/tests/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+clreq$(EXEEXT): $(clreq_OBJECTS) $(clreq_DEPENDENCIES)
+ @rm -f clreq$(EXEEXT)
+ $(LINK) $(clreq_OBJECTS) $(clreq_LDADD) $(LIBS)
+simwork$(EXEEXT): $(simwork_OBJECTS) $(simwork_DEPENDENCIES)
+ @rm -f simwork$(EXEEXT)
+ $(LINK) $(simwork_OBJECTS) $(simwork_LDADD) $(LIBS)
+threads$(EXEEXT): $(threads_OBJECTS) $(threads_DEPENDENCIES)
+ @rm -f threads$(EXEEXT)
+ $(LINK) $(threads_OBJECTS) $(threads_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clreq.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/simwork.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/threads.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-recursive
+all-am: Makefile $(SCRIPTS)
+installdirs: installdirs-recursive
+installdirs-am:
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) check-am \
+ ctags-recursive install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags \
+ ctags-recursive distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ installdirs-am maintainer-clean maintainer-clean-generic \
+ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \
+ ps ps-am tags tags-recursive uninstall uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/callgrind/tests/filter_stderr b/main/callgrind/tests/filter_stderr
index 9664d51..9acedd3 100755
--- a/main/callgrind/tests/filter_stderr
+++ b/main/callgrind/tests/filter_stderr
@@ -29,4 +29,5 @@
sed "/Warning: Cannot auto-detect cache config on PPC.., using one or more defaults/d" |
sed "/Warning: Cannot auto-detect cache config on ARM, using one or more defaults/d" |
sed "/Warning: Cannot auto-detect cache config on s390x, using one or more defaults/d" |
+sed "/Warning: Cannot auto-detect cache config on MIPS.., using one or more defaults/d" |
sed "/warning: pretending that LL cache has associativity .*$/d"
diff --git a/main/callgrind/threads.c b/main/callgrind/threads.c
index 03b8c61..a784f12 100644
--- a/main/callgrind/threads.c
+++ b/main/callgrind/threads.c
@@ -6,7 +6,7 @@
/*
This file is part of Callgrind, a Valgrind tool for call tracing.
- Copyright (C) 2002-2011, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+ Copyright (C) 2002-2012, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -189,8 +189,6 @@
}
}
- CLG_(check_command)();
-
/* now check for thread switch */
CLG_(switch_thread)(tid);
}
diff --git a/main/coregrind/Makefile.am b/main/coregrind/Makefile.am
index 6220f79..01015a7 100644
--- a/main/coregrind/Makefile.am
+++ b/main/coregrind/Makefile.am
@@ -52,12 +52,20 @@
if VGCONF_PLATFORMS_INCLUDE_X86_DARWIN
valgrind_LDFLAGS += -Wl,-read_only_relocs -Wl,suppress
endif
+# On Android we must ask for non-executable stack, not sure why.
+if VGCONF_PLATVARIANT_IS_ANDROID
+valgrind_CFLAGS += -static
+valgrind_LDFLAGS += -Wl,-z,noexecstack
+endif
vgdb_SOURCES = vgdb.c
vgdb_CPPFLAGS = $(AM_CPPFLAGS_PRI)
vgdb_CFLAGS = $(AM_CFLAGS_PRI)
vgdb_CCASFLAGS = $(AM_CCASFLAGS_PRI)
vgdb_LDFLAGS = $(AM_CFLAGS_PRI)
+if VGCONF_PLATVARIANT_IS_ANDROID
+vgdb_CFLAGS += -static
+endif
if !VGCONF_PLATVARIANT_IS_ANDROID
vgdb_LDADD = -lpthread
endif
@@ -208,6 +216,8 @@
m_initimg/priv_initimg_pathscan.h \
m_initimg/simple_huffman.c \
m_scheduler/priv_sema.h \
+ m_scheduler/priv_sched-lock.h \
+ m_scheduler/priv_sched-lock-impl.h \
m_syswrap/priv_types_n_macros.h \
m_syswrap/priv_syswrap-generic.h \
m_syswrap/priv_syswrap-linux.h \
@@ -236,6 +246,7 @@
m_debuglog.c \
m_errormgr.c \
m_execontext.c \
+ m_poolalloc.c \
m_hashtable.c \
m_libcbase.c \
m_libcassert.c \
@@ -292,9 +303,9 @@
m_dispatch/dispatch-ppc64-linux.S \
m_dispatch/dispatch-arm-linux.S \
m_dispatch/dispatch-s390x-linux.S \
+ m_dispatch/dispatch-mips32-linux.S \
m_dispatch/dispatch-x86-darwin.S \
m_dispatch/dispatch-amd64-darwin.S \
- m_gdbserver/m_gdbserver.c \
m_gdbserver/inferiors.c \
m_gdbserver/m_gdbserver.c \
m_gdbserver/regcache.c \
@@ -303,13 +314,13 @@
m_gdbserver/signals.c \
m_gdbserver/target.c \
m_gdbserver/utils.c \
- m_gdbserver/valgrind-low.c \
m_gdbserver/valgrind-low-x86.c \
m_gdbserver/valgrind-low-amd64.c \
m_gdbserver/valgrind-low-arm.c \
m_gdbserver/valgrind-low-ppc32.c \
m_gdbserver/valgrind-low-ppc64.c \
m_gdbserver/valgrind-low-s390x.c \
+ m_gdbserver/valgrind-low-mips32.c \
m_gdbserver/version.c \
m_initimg/initimg-linux.c \
m_initimg/initimg-darwin.c \
@@ -321,12 +332,15 @@
m_replacemalloc/replacemalloc_core.c \
m_scheduler/scheduler.c \
m_scheduler/sema.c \
+ m_scheduler/sched-lock.c \
+ m_scheduler/sched-lock-generic.c \
m_sigframe/sigframe-x86-linux.c \
m_sigframe/sigframe-amd64-linux.c \
m_sigframe/sigframe-ppc32-linux.c \
m_sigframe/sigframe-ppc64-linux.c \
m_sigframe/sigframe-arm-linux.c \
m_sigframe/sigframe-s390x-linux.c \
+ m_sigframe/sigframe-mips32-linux.c \
m_sigframe/sigframe-x86-darwin.c \
m_sigframe/sigframe-amd64-darwin.c \
m_syswrap/syscall-x86-linux.S \
@@ -335,6 +349,7 @@
m_syswrap/syscall-ppc64-linux.S \
m_syswrap/syscall-arm-linux.S \
m_syswrap/syscall-s390x-linux.S \
+ m_syswrap/syscall-mips32-linux.S \
m_syswrap/syscall-x86-darwin.S \
m_syswrap/syscall-amd64-darwin.S \
m_syswrap/syswrap-main.c \
@@ -348,6 +363,7 @@
m_syswrap/syswrap-ppc64-linux.c \
m_syswrap/syswrap-arm-linux.c \
m_syswrap/syswrap-s390x-linux.c \
+ m_syswrap/syswrap-mips32-linux.c \
m_syswrap/syswrap-x86-darwin.c \
m_syswrap/syswrap-amd64-darwin.c \
m_ume/elf.c \
@@ -365,6 +381,13 @@
$(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS = \
$(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+if ENABLE_LINUX_TICKET_LOCK_PRIMARY
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES += \
+ m_scheduler/ticket-lock-linux.c
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS += \
+ -DENABLE_LINUX_TICKET_LOCK
+endif
+
if VGCONF_HAVE_PLATFORM_SEC
libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES = \
$(COREGRIND_SOURCES_COMMON)
@@ -376,6 +399,12 @@
$(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS = \
$(AM_CCASFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+if ENABLE_LINUX_TICKET_LOCK_SECONDARY
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES += \
+ m_scheduler/ticket-lock-linux.c
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS += \
+ -DENABLE_LINUX_TICKET_LOCK
+endif
endif
#----------------------------------------------------------------------------
@@ -446,6 +475,9 @@
m_gdbserver/32bit-sse-valgrind-s1.xml \
m_gdbserver/32bit-sse-valgrind-s2.xml \
m_gdbserver/32bit-sse.xml \
+ m_gdbserver/64bit-avx-valgrind-s2.xml \
+ m_gdbserver/64bit-avx-valgrind-s1.xml \
+ m_gdbserver/64bit-avx.xml \
m_gdbserver/64bit-core-valgrind-s1.xml \
m_gdbserver/64bit-core-valgrind-s2.xml \
m_gdbserver/64bit-core.xml \
@@ -455,6 +487,10 @@
m_gdbserver/64bit-sse-valgrind-s1.xml \
m_gdbserver/64bit-sse-valgrind-s2.xml \
m_gdbserver/64bit-sse.xml \
+ m_gdbserver/amd64-avx-coresse-valgrind.xml \
+ m_gdbserver/amd64-avx-coresse.xml \
+ m_gdbserver/amd64-avx-linux-valgrind.xml \
+ m_gdbserver/amd64-avx-linux.xml \
m_gdbserver/amd64-coresse-valgrind.xml \
m_gdbserver/amd64-linux-valgrind.xml \
m_gdbserver/arm-core-valgrind-s1.xml \
@@ -476,6 +512,8 @@
m_gdbserver/power-altivec-valgrind-s1.xml \
m_gdbserver/power-altivec-valgrind-s2.xml \
m_gdbserver/power-altivec.xml \
+ m_gdbserver/power-core-valgrind-s1.xml \
+ m_gdbserver/power-core-valgrind-s2.xml \
m_gdbserver/power-core.xml \
m_gdbserver/power-fpu-valgrind-s1.xml \
m_gdbserver/power-fpu-valgrind-s2.xml \
@@ -486,10 +524,36 @@
m_gdbserver/powerpc-altivec32l-valgrind.xml \
m_gdbserver/powerpc-altivec32l.xml \
m_gdbserver/powerpc-altivec64l-valgrind.xml \
- m_gdbserver/powerpc-altivec64l.xml
+ m_gdbserver/powerpc-altivec64l.xml \
+ m_gdbserver/s390-acr-valgrind-s1.xml \
+ m_gdbserver/s390-acr-valgrind-s2.xml \
+ m_gdbserver/s390-acr.xml \
+ m_gdbserver/s390-fpr-valgrind-s1.xml \
+ m_gdbserver/s390-fpr-valgrind-s2.xml \
+ m_gdbserver/s390-fpr.xml \
+ m_gdbserver/s390x-core64-valgrind-s1.xml \
+ m_gdbserver/s390x-core64-valgrind-s2.xml \
+ m_gdbserver/s390x-core64.xml \
+ m_gdbserver/s390x-generic-valgrind.xml \
+ m_gdbserver/s390x-generic.xml \
+ m_gdbserver/s390x-linux64-valgrind-s1.xml \
+ m_gdbserver/s390x-linux64-valgrind-s2.xml \
+ m_gdbserver/s390x-linux64.xml \
+ m_gdbserver/mips-cp0-valgrind-s1.xml \
+ m_gdbserver/mips-cp0-valgrind-s2.xml \
+ m_gdbserver/mips-cp0.xml \
+ m_gdbserver/mips-cpu-valgrind-s1.xml \
+ m_gdbserver/mips-cpu-valgrind-s2.xml \
+ m_gdbserver/mips-cpu.xml \
+ m_gdbserver/mips-linux.xml \
+ m_gdbserver/mips-linux-valgrind.xml \
+ m_gdbserver/mips-fpu-valgrind-s1.xml \
+ m_gdbserver/mips-fpu-valgrind-s2.xml \
+ m_gdbserver/mips-fpu.xml
# so as to make sure these get copied into the install tree
-pkglib_DATA = $(GDBSERVER_XML_FILES)
+vglibdir = $(pkglibdir)
+vglib_DATA = $(GDBSERVER_XML_FILES)
# so as to make sure these get copied into the tarball
EXTRA_DIST += $(GDBSERVER_XML_FILES)
@@ -500,7 +564,7 @@
all-local: inplace-noinst_PROGRAMS inplace-noinst_DSYMS
mkdir -p $(inplacedir); \
- for f in $(pkglib_DATA); do \
+ for f in $(vglib_DATA); do \
rm -f $(inplacedir)/$$f; \
ln -f -s ../$(subdir)/$$f $(inplacedir); \
done
diff --git a/main/coregrind/Makefile.in b/main/coregrind/Makefile.in
new file mode 100644
index 0000000..d62cf92
--- /dev/null
+++ b/main/coregrind/Makefile.in
@@ -0,0 +1,6084 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# Be very careful when renaming any files, targets, whatever, in this
+# Makefile. Various parts of the system rely on these names having
+# particular forms.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(srcdir)/link_tool_exe_darwin.in \
+ $(srcdir)/link_tool_exe_linux.in $(top_srcdir)/Makefile.all.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+bin_PROGRAMS = valgrind$(EXEEXT) vgdb$(EXEEXT)
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_2 = -Wl,-read_only_relocs -Wl,suppress
+# On Android we must ask for non-executable stack, not sure why.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -static
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_4 = -Wl,-z,noexecstack
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_5 = -static
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_6 = -Wl,-read_only_relocs -Wl,suppress
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_7 = \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/mach_vmUser.c \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/taskUser.c \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/thread_actUser.c \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/vm_mapUser.c
+
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_8 = \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/mach_vmServer.c \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/taskServer.c \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/thread_actServer.c \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/vm_mapServer.c
+
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_9 = \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/mach_vm.h \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/task.h \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/thread_act.h \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_mach/vm_map.h
+
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_10 = \
+@VGCONF_OS_IS_DARWIN_TRUE@ /usr/include/mach/mach_vm.defs \
+@VGCONF_OS_IS_DARWIN_TRUE@ /usr/include/mach/task.defs \
+@VGCONF_OS_IS_DARWIN_TRUE@ /usr/include/mach/thread_act.defs \
+@VGCONF_OS_IS_DARWIN_TRUE@ /usr/include/mach/vm_map.defs
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_11 = libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+@ENABLE_LINUX_TICKET_LOCK_PRIMARY_TRUE@am__append_12 = \
+@ENABLE_LINUX_TICKET_LOCK_PRIMARY_TRUE@ m_scheduler/ticket-lock-linux.c
+
+@ENABLE_LINUX_TICKET_LOCK_PRIMARY_TRUE@am__append_13 = \
+@ENABLE_LINUX_TICKET_LOCK_PRIMARY_TRUE@ -DENABLE_LINUX_TICKET_LOCK
+
+@ENABLE_LINUX_TICKET_LOCK_SECONDARY_TRUE@@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_14 = \
+@ENABLE_LINUX_TICKET_LOCK_SECONDARY_TRUE@@VGCONF_HAVE_PLATFORM_SEC_TRUE@ m_scheduler/ticket-lock-linux.c
+
+@ENABLE_LINUX_TICKET_LOCK_SECONDARY_TRUE@@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_15 = \
+@ENABLE_LINUX_TICKET_LOCK_SECONDARY_TRUE@@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DENABLE_LINUX_TICKET_LOCK
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_16 = libreplacemalloc_toolpreload-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+noinst_PROGRAMS = \
+ vgpreload_core-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
+ $(am__EXEEXT_1)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_17 = vgpreload_core-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+
+#----------------------------------------------------------------------------
+# Darwin linker kludges
+#----------------------------------------------------------------------------
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_18 = fixup_macho_loadcmds
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_19 = fixup_macho_loadcmds
+subdir = coregrind
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES = link_tool_exe_linux link_tool_exe_darwin
+CONFIG_CLEAN_VPATH_FILES =
+am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
+am__vpath_adj = case $$p in \
+ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
+ *) f=$$p;; \
+ esac;
+am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;
+am__install_max = 40
+am__nobase_strip_setup = \
+ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`
+am__nobase_strip = \
+ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"
+am__nobase_list = $(am__nobase_strip_setup); \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \
+ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \
+ if (++n[$$2] == $(am__install_max)) \
+ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \
+ END { for (dir in files) print dir, files[dir] }'
+am__base_list = \
+ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \
+ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'
+am__installdirs = "$(DESTDIR)$(pkglibdir)" "$(DESTDIR)$(bindir)" \
+ "$(DESTDIR)$(vglibdir)"
+LIBRARIES = $(pkglib_LIBRARIES)
+ARFLAGS = cru
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_AR = $(AR) $(ARFLAGS)
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_LIBADD =
+am__libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES_DIST = \
+ m_commandline.c m_clientstate.c m_cpuid.S m_debugger.c \
+ m_debuglog.c m_errormgr.c m_execontext.c m_poolalloc.c \
+ m_hashtable.c m_libcbase.c m_libcassert.c m_libcfile.c \
+ m_libcprint.c m_libcproc.c m_libcsetjmp.c m_libcsignal.c \
+ m_machine.c m_main.c m_mallocfree.c m_options.c m_oset.c \
+ m_redir.c m_seqmatch.c m_signals.c m_sparsewa.c m_stacks.c \
+ m_stacktrace.c m_syscall.c m_threadstate.c m_tooliface.c \
+ m_trampoline.S m_translate.c m_transtab.c m_vki.c \
+ m_vkiscnums.c m_wordfm.c m_xarray.c m_aspacehl.c \
+ m_aspacemgr/aspacemgr-common.c m_aspacemgr/aspacemgr-linux.c \
+ m_coredump/coredump-elf.c m_coredump/coredump-macho.c \
+ m_debuginfo/misc.c m_debuginfo/d3basics.c \
+ m_debuginfo/debuginfo.c m_debuginfo/readdwarf.c \
+ m_debuginfo/readdwarf3.c m_debuginfo/readelf.c \
+ m_debuginfo/readmacho.c m_debuginfo/readpdb.c \
+ m_debuginfo/readstabs.c m_debuginfo/storage.c \
+ m_debuginfo/tytypes.c m_demangle/cp-demangle.c \
+ m_demangle/cplus-dem.c m_demangle/demangle.c \
+ m_demangle/dyn-string.c m_demangle/safe-ctype.c \
+ m_dispatch/dispatch-x86-linux.S \
+ m_dispatch/dispatch-amd64-linux.S \
+ m_dispatch/dispatch-ppc32-linux.S \
+ m_dispatch/dispatch-ppc64-linux.S \
+ m_dispatch/dispatch-arm-linux.S \
+ m_dispatch/dispatch-s390x-linux.S \
+ m_dispatch/dispatch-mips32-linux.S \
+ m_dispatch/dispatch-x86-darwin.S \
+ m_dispatch/dispatch-amd64-darwin.S m_gdbserver/inferiors.c \
+ m_gdbserver/m_gdbserver.c m_gdbserver/regcache.c \
+ m_gdbserver/remote-utils.c m_gdbserver/server.c \
+ m_gdbserver/signals.c m_gdbserver/target.c m_gdbserver/utils.c \
+ m_gdbserver/valgrind-low-x86.c \
+ m_gdbserver/valgrind-low-amd64.c \
+ m_gdbserver/valgrind-low-arm.c \
+ m_gdbserver/valgrind-low-ppc32.c \
+ m_gdbserver/valgrind-low-ppc64.c \
+ m_gdbserver/valgrind-low-s390x.c \
+ m_gdbserver/valgrind-low-mips32.c m_gdbserver/version.c \
+ m_initimg/initimg-linux.c m_initimg/initimg-darwin.c \
+ m_initimg/initimg-pathscan.c m_mach/mach_basics.c \
+ m_mach/mach_msg.c m_mach/mach_traps-x86-darwin.S \
+ m_mach/mach_traps-amd64-darwin.S \
+ m_replacemalloc/replacemalloc_core.c m_scheduler/scheduler.c \
+ m_scheduler/sema.c m_scheduler/sched-lock.c \
+ m_scheduler/sched-lock-generic.c \
+ m_sigframe/sigframe-x86-linux.c \
+ m_sigframe/sigframe-amd64-linux.c \
+ m_sigframe/sigframe-ppc32-linux.c \
+ m_sigframe/sigframe-ppc64-linux.c \
+ m_sigframe/sigframe-arm-linux.c \
+ m_sigframe/sigframe-s390x-linux.c \
+ m_sigframe/sigframe-mips32-linux.c \
+ m_sigframe/sigframe-x86-darwin.c \
+ m_sigframe/sigframe-amd64-darwin.c \
+ m_syswrap/syscall-x86-linux.S m_syswrap/syscall-amd64-linux.S \
+ m_syswrap/syscall-ppc32-linux.S \
+ m_syswrap/syscall-ppc64-linux.S m_syswrap/syscall-arm-linux.S \
+ m_syswrap/syscall-s390x-linux.S \
+ m_syswrap/syscall-mips32-linux.S \
+ m_syswrap/syscall-x86-darwin.S \
+ m_syswrap/syscall-amd64-darwin.S m_syswrap/syswrap-main.c \
+ m_syswrap/syswrap-generic.c m_syswrap/syswrap-linux.c \
+ m_syswrap/syswrap-linux-variants.c m_syswrap/syswrap-darwin.c \
+ m_syswrap/syswrap-x86-linux.c m_syswrap/syswrap-amd64-linux.c \
+ m_syswrap/syswrap-ppc32-linux.c \
+ m_syswrap/syswrap-ppc64-linux.c m_syswrap/syswrap-arm-linux.c \
+ m_syswrap/syswrap-s390x-linux.c \
+ m_syswrap/syswrap-mips32-linux.c \
+ m_syswrap/syswrap-x86-darwin.c \
+ m_syswrap/syswrap-amd64-darwin.c m_ume/elf.c m_ume/macho.c \
+ m_ume/main.c m_ume/script.c m_scheduler/ticket-lock-linux.c
+am__objects_1 = libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.$(OBJEXT)
+@ENABLE_LINUX_TICKET_LOCK_PRIMARY_TRUE@am__objects_2 = libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.$(OBJEXT)
+am_libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS = \
+ $(am__objects_1) $(am__objects_2)
+@VGCONF_OS_IS_DARWIN_TRUE@am__objects_3 = libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.$(OBJEXT) \
+@VGCONF_OS_IS_DARWIN_TRUE@ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.$(OBJEXT) \
+@VGCONF_OS_IS_DARWIN_TRUE@ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.$(OBJEXT) \
+@VGCONF_OS_IS_DARWIN_TRUE@ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.$(OBJEXT)
+am__objects_4 = $(am__objects_3)
+am__objects_5 =
+am__objects_6 = $(am__objects_4) $(am__objects_5)
+nodist_libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS = \
+ $(am__objects_6)
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS = \
+ $(am_libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS) \
+ $(nodist_libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS)
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_AR = $(AR) $(ARFLAGS)
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_LIBADD =
+am__libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST = \
+ m_commandline.c m_clientstate.c m_cpuid.S m_debugger.c \
+ m_debuglog.c m_errormgr.c m_execontext.c m_poolalloc.c \
+ m_hashtable.c m_libcbase.c m_libcassert.c m_libcfile.c \
+ m_libcprint.c m_libcproc.c m_libcsetjmp.c m_libcsignal.c \
+ m_machine.c m_main.c m_mallocfree.c m_options.c m_oset.c \
+ m_redir.c m_seqmatch.c m_signals.c m_sparsewa.c m_stacks.c \
+ m_stacktrace.c m_syscall.c m_threadstate.c m_tooliface.c \
+ m_trampoline.S m_translate.c m_transtab.c m_vki.c \
+ m_vkiscnums.c m_wordfm.c m_xarray.c m_aspacehl.c \
+ m_aspacemgr/aspacemgr-common.c m_aspacemgr/aspacemgr-linux.c \
+ m_coredump/coredump-elf.c m_coredump/coredump-macho.c \
+ m_debuginfo/misc.c m_debuginfo/d3basics.c \
+ m_debuginfo/debuginfo.c m_debuginfo/readdwarf.c \
+ m_debuginfo/readdwarf3.c m_debuginfo/readelf.c \
+ m_debuginfo/readmacho.c m_debuginfo/readpdb.c \
+ m_debuginfo/readstabs.c m_debuginfo/storage.c \
+ m_debuginfo/tytypes.c m_demangle/cp-demangle.c \
+ m_demangle/cplus-dem.c m_demangle/demangle.c \
+ m_demangle/dyn-string.c m_demangle/safe-ctype.c \
+ m_dispatch/dispatch-x86-linux.S \
+ m_dispatch/dispatch-amd64-linux.S \
+ m_dispatch/dispatch-ppc32-linux.S \
+ m_dispatch/dispatch-ppc64-linux.S \
+ m_dispatch/dispatch-arm-linux.S \
+ m_dispatch/dispatch-s390x-linux.S \
+ m_dispatch/dispatch-mips32-linux.S \
+ m_dispatch/dispatch-x86-darwin.S \
+ m_dispatch/dispatch-amd64-darwin.S m_gdbserver/inferiors.c \
+ m_gdbserver/m_gdbserver.c m_gdbserver/regcache.c \
+ m_gdbserver/remote-utils.c m_gdbserver/server.c \
+ m_gdbserver/signals.c m_gdbserver/target.c m_gdbserver/utils.c \
+ m_gdbserver/valgrind-low-x86.c \
+ m_gdbserver/valgrind-low-amd64.c \
+ m_gdbserver/valgrind-low-arm.c \
+ m_gdbserver/valgrind-low-ppc32.c \
+ m_gdbserver/valgrind-low-ppc64.c \
+ m_gdbserver/valgrind-low-s390x.c \
+ m_gdbserver/valgrind-low-mips32.c m_gdbserver/version.c \
+ m_initimg/initimg-linux.c m_initimg/initimg-darwin.c \
+ m_initimg/initimg-pathscan.c m_mach/mach_basics.c \
+ m_mach/mach_msg.c m_mach/mach_traps-x86-darwin.S \
+ m_mach/mach_traps-amd64-darwin.S \
+ m_replacemalloc/replacemalloc_core.c m_scheduler/scheduler.c \
+ m_scheduler/sema.c m_scheduler/sched-lock.c \
+ m_scheduler/sched-lock-generic.c \
+ m_sigframe/sigframe-x86-linux.c \
+ m_sigframe/sigframe-amd64-linux.c \
+ m_sigframe/sigframe-ppc32-linux.c \
+ m_sigframe/sigframe-ppc64-linux.c \
+ m_sigframe/sigframe-arm-linux.c \
+ m_sigframe/sigframe-s390x-linux.c \
+ m_sigframe/sigframe-mips32-linux.c \
+ m_sigframe/sigframe-x86-darwin.c \
+ m_sigframe/sigframe-amd64-darwin.c \
+ m_syswrap/syscall-x86-linux.S m_syswrap/syscall-amd64-linux.S \
+ m_syswrap/syscall-ppc32-linux.S \
+ m_syswrap/syscall-ppc64-linux.S m_syswrap/syscall-arm-linux.S \
+ m_syswrap/syscall-s390x-linux.S \
+ m_syswrap/syscall-mips32-linux.S \
+ m_syswrap/syscall-x86-darwin.S \
+ m_syswrap/syscall-amd64-darwin.S m_syswrap/syswrap-main.c \
+ m_syswrap/syswrap-generic.c m_syswrap/syswrap-linux.c \
+ m_syswrap/syswrap-linux-variants.c m_syswrap/syswrap-darwin.c \
+ m_syswrap/syswrap-x86-linux.c m_syswrap/syswrap-amd64-linux.c \
+ m_syswrap/syswrap-ppc32-linux.c \
+ m_syswrap/syswrap-ppc64-linux.c m_syswrap/syswrap-arm-linux.c \
+ m_syswrap/syswrap-s390x-linux.c \
+ m_syswrap/syswrap-mips32-linux.c \
+ m_syswrap/syswrap-x86-darwin.c \
+ m_syswrap/syswrap-amd64-darwin.c m_ume/elf.c m_ume/macho.c \
+ m_ume/main.c m_ume/script.c m_scheduler/ticket-lock-linux.c
+am__objects_7 = libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.$(OBJEXT) \
+ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.$(OBJEXT)
+@ENABLE_LINUX_TICKET_LOCK_SECONDARY_TRUE@@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__objects_8 = libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_7) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_8)
+@VGCONF_OS_IS_DARWIN_TRUE@am__objects_9 = libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.$(OBJEXT) \
+@VGCONF_OS_IS_DARWIN_TRUE@ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.$(OBJEXT) \
+@VGCONF_OS_IS_DARWIN_TRUE@ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.$(OBJEXT) \
+@VGCONF_OS_IS_DARWIN_TRUE@ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.$(OBJEXT)
+am__objects_10 = $(am__objects_9)
+am__objects_11 = $(am__objects_10) $(am__objects_5)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@nodist_libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_11)
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS = \
+ $(am_libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS) \
+ $(nodist_libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS)
+libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_AR = \
+ $(AR) $(ARFLAGS)
+libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_LIBADD =
+am_libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS = libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.$(OBJEXT)
+libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS = $(am_libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS)
+libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_AR = \
+ $(AR) $(ARFLAGS)
+libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_LIBADD =
+am__libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST = \
+ m_replacemalloc/vg_replace_malloc.c
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS = libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.$(OBJEXT)
+libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS = $(am_libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = vgpreload_core-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+PROGRAMS = $(bin_PROGRAMS) $(noinst_PROGRAMS)
+am__valgrind_SOURCES_DIST = launcher-darwin.c m_debuglog.c \
+ launcher-linux.c
+@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_LINUX_TRUE@am_valgrind_OBJECTS = valgrind-launcher-linux.$(OBJEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_LINUX_TRUE@ valgrind-m_debuglog.$(OBJEXT)
+@VGCONF_OS_IS_DARWIN_TRUE@am_valgrind_OBJECTS = \
+@VGCONF_OS_IS_DARWIN_TRUE@ valgrind-launcher-darwin.$(OBJEXT) \
+@VGCONF_OS_IS_DARWIN_TRUE@ valgrind-m_debuglog.$(OBJEXT)
+valgrind_OBJECTS = $(am_valgrind_OBJECTS)
+valgrind_LDADD = $(LDADD)
+valgrind_LINK = $(CCLD) $(valgrind_CFLAGS) $(CFLAGS) \
+ $(valgrind_LDFLAGS) $(LDFLAGS) -o $@
+am_vgdb_OBJECTS = vgdb-vgdb.$(OBJEXT)
+vgdb_OBJECTS = $(am_vgdb_OBJECTS)
+vgdb_DEPENDENCIES =
+vgdb_LINK = $(CCLD) $(vgdb_CFLAGS) $(CFLAGS) $(vgdb_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am_vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.$(OBJEXT)
+vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = \
+ $(am_vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am__vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES_DIST = \
+ vg_preloaded.c
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS = vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.$(OBJEXT)
+vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS = \
+ $(am_vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+CPPASCOMPILE = $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CCASFLAGS) $(CCASFLAGS)
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES) \
+ $(nodist_libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES) \
+ $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES) \
+ $(nodist_libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES) \
+ $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES) \
+ $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES) \
+ $(valgrind_SOURCES) $(vgdb_SOURCES) \
+ $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES) \
+ $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES)
+DIST_SOURCES = $(am__libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES_DIST) \
+ $(am__libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST) \
+ $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES) \
+ $(am__libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST) \
+ $(am__valgrind_SOURCES_DIST) $(vgdb_SOURCES) \
+ $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES) \
+ $(am__vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES_DIST)
+DATA = $(vglib_DATA)
+HEADERS = $(noinst_HEADERS)
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+
+#----------------------------------------------------------------------------
+# Basics, flags
+#----------------------------------------------------------------------------
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = -I$(top_srcdir) \
+ -I$(top_srcdir)/include -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ -I$(top_srcdir)/coregrind -DVG_LIBDIR="\"$(pkglibdir)"\" \
+ -DVG_PLATFORM="\"@VGCONF_ARCH_PRI@-@VGCONF_OS@\""
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/coregrind \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVG_LIBDIR="\"$(pkglibdir)"\" \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVG_PLATFORM="\"@VGCONF_ARCH_SEC@-@VGCONF_OS@\""
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+# so as to make sure these get copied into the tarball
+EXTRA_DIST = m_debuginfo/UNUSED_STABS.txt m_debuginfo/README.txt \
+ m_gdbserver/README_DEVELOPERS $(GDBSERVER_XML_FILES) \
+ fixup_macho_loadcmds.c
+@VGCONF_OS_IS_DARWIN_TRUE@valgrind_SOURCES = \
+@VGCONF_OS_IS_DARWIN_TRUE@ launcher-darwin.c \
+@VGCONF_OS_IS_DARWIN_TRUE@ m_debuglog.c
+
+@VGCONF_OS_IS_LINUX_TRUE@valgrind_SOURCES = \
+@VGCONF_OS_IS_LINUX_TRUE@ launcher-linux.c \
+@VGCONF_OS_IS_LINUX_TRUE@ m_debuglog.c
+
+valgrind_CPPFLAGS = $(AM_CPPFLAGS_PRI)
+valgrind_CFLAGS = $(AM_CFLAGS_PRI) $(am__append_3)
+valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI)
+valgrind_LDFLAGS = $(AM_CFLAGS_PRI) $(am__append_2) $(am__append_4)
+vgdb_SOURCES = vgdb.c
+vgdb_CPPFLAGS = $(AM_CPPFLAGS_PRI)
+vgdb_CFLAGS = $(AM_CFLAGS_PRI) $(am__append_5)
+vgdb_CCASFLAGS = $(AM_CCASFLAGS_PRI)
+vgdb_LDFLAGS = $(AM_CFLAGS_PRI) $(am__append_6)
+@VGCONF_PLATVARIANT_IS_ANDROID_FALSE@vgdb_LDADD = -lpthread
+
+#----------------------------------------------------------------------------
+# Darwin Mach stuff
+#----------------------------------------------------------------------------
+
+# Mach RPC interface definitions
+# Here are some more .defs files that are not used, but could be in the
+# future:
+# clock.defs \
+# clock_priv.defs \
+# clock_reply.defs \
+# exc.defs \
+# host_priv.defs \
+# host_security.defs \
+# ledger.defs \
+# lock_set.defs \
+# mach_host.defs \
+# mach_port.defs \
+# notify.defs \
+# processor.defs \
+# processor_set.defs \
+#
+mach_user_srcs = $(am__append_7)
+mach_server_srcs = $(am__append_8)
+mach_hdrs = $(am__append_9)
+mach_defs = $(am__append_10)
+
+#----------------------------------------------------------------------------
+# Headers
+#----------------------------------------------------------------------------
+noinst_HEADERS = \
+ pub_core_aspacehl.h \
+ pub_core_aspacemgr.h \
+ pub_core_basics.h \
+ pub_core_basics_asm.h \
+ pub_core_clientstate.h \
+ pub_core_clreq.h \
+ pub_core_commandline.h \
+ pub_core_coredump.h \
+ pub_core_cpuid.h \
+ pub_core_debuginfo.h \
+ pub_core_debugger.h \
+ pub_core_debuglog.h \
+ pub_core_demangle.h \
+ pub_core_dispatch.h \
+ pub_core_dispatch_asm.h \
+ pub_core_errormgr.h \
+ pub_core_execontext.h \
+ pub_core_gdbserver.h \
+ pub_core_hashtable.h \
+ pub_core_initimg.h \
+ pub_core_libcbase.h \
+ pub_core_libcassert.h \
+ pub_core_libcfile.h \
+ pub_core_libcprint.h \
+ pub_core_libcproc.h \
+ pub_core_libcsetjmp.h \
+ pub_core_libcsignal.h \
+ pub_core_mach.h \
+ pub_core_machine.h \
+ pub_core_mallocfree.h \
+ pub_core_options.h \
+ pub_core_oset.h \
+ pub_core_redir.h \
+ pub_core_replacemalloc.h\
+ pub_core_scheduler.h \
+ pub_core_seqmatch.h \
+ pub_core_sigframe.h \
+ pub_core_signals.h \
+ pub_core_sparsewa.h \
+ pub_core_stacks.h \
+ pub_core_stacktrace.h \
+ pub_core_syscall.h \
+ pub_core_syswrap.h \
+ pub_core_threadstate.h \
+ pub_core_tooliface.h \
+ pub_core_trampoline.h \
+ pub_core_translate.h \
+ pub_core_transtab.h \
+ pub_core_transtab_asm.h \
+ pub_core_ume.h \
+ pub_core_vki.h \
+ pub_core_vkiscnums.h \
+ pub_core_vkiscnums_asm.h\
+ pub_core_wordfm.h \
+ pub_core_xarray.h \
+ m_aspacemgr/priv_aspacemgr.h \
+ m_debuginfo/priv_misc.h \
+ m_debuginfo/priv_storage.h \
+ m_debuginfo/priv_tytypes.h \
+ m_debuginfo/priv_readstabs.h \
+ m_debuginfo/priv_readpdb.h \
+ m_debuginfo/priv_d3basics.h \
+ m_debuginfo/priv_readdwarf.h \
+ m_debuginfo/priv_readdwarf3.h \
+ m_debuginfo/priv_readelf.h \
+ m_debuginfo/priv_readmacho.h \
+ m_demangle/ansidecl.h \
+ m_demangle/cp-demangle.h \
+ m_demangle/dyn-string.h \
+ m_demangle/demangle.h \
+ m_demangle/safe-ctype.h \
+ m_demangle/vg_libciface.h \
+ m_gdbserver/regcache.h \
+ m_gdbserver/regdef.h \
+ m_gdbserver/server.h \
+ m_gdbserver/target.h \
+ m_gdbserver/valgrind_low.h \
+ m_gdbserver/gdb/signals.h \
+ m_initimg/priv_initimg_pathscan.h \
+ m_initimg/simple_huffman.c \
+ m_scheduler/priv_sema.h \
+ m_scheduler/priv_sched-lock.h \
+ m_scheduler/priv_sched-lock-impl.h \
+ m_syswrap/priv_types_n_macros.h \
+ m_syswrap/priv_syswrap-generic.h \
+ m_syswrap/priv_syswrap-linux.h \
+ m_syswrap/priv_syswrap-linux-variants.h \
+ m_syswrap/priv_syswrap-darwin.h \
+ m_syswrap/priv_syswrap-main.h \
+ m_ume/priv_ume.h
+
+
+#----------------------------------------------------------------------------
+# libcoregrind-<platform>.a
+#----------------------------------------------------------------------------
+BUILT_SOURCES = $(mach_user_srcs) $(am__append_18)
+CLEANFILES = $(mach_user_srcs) $(mach_server_srcs) $(mach_hdrs) \
+ $(am__append_19)
+
+#----------------------------------------------------------------------------
+# libreplacemalloc_toolpreload-<platform>.a
+#----------------------------------------------------------------------------
+pkglib_LIBRARIES = libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ $(am__append_11) \
+ libreplacemalloc_toolpreload-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ $(am__append_16)
+COREGRIND_SOURCES_COMMON = \
+ m_commandline.c \
+ m_clientstate.c \
+ m_cpuid.S \
+ m_debugger.c \
+ m_debuglog.c \
+ m_errormgr.c \
+ m_execontext.c \
+ m_poolalloc.c \
+ m_hashtable.c \
+ m_libcbase.c \
+ m_libcassert.c \
+ m_libcfile.c \
+ m_libcprint.c \
+ m_libcproc.c \
+ m_libcsetjmp.c \
+ m_libcsignal.c \
+ m_machine.c \
+ m_main.c \
+ m_mallocfree.c \
+ m_options.c \
+ m_oset.c \
+ m_redir.c \
+ m_seqmatch.c \
+ m_signals.c \
+ m_sparsewa.c \
+ m_stacks.c \
+ m_stacktrace.c \
+ m_syscall.c \
+ m_threadstate.c \
+ m_tooliface.c \
+ m_trampoline.S \
+ m_translate.c \
+ m_transtab.c \
+ m_vki.c \
+ m_vkiscnums.c \
+ m_wordfm.c \
+ m_xarray.c \
+ m_aspacehl.c \
+ m_aspacemgr/aspacemgr-common.c \
+ m_aspacemgr/aspacemgr-linux.c \
+ m_coredump/coredump-elf.c \
+ m_coredump/coredump-macho.c \
+ m_debuginfo/misc.c \
+ m_debuginfo/d3basics.c \
+ m_debuginfo/debuginfo.c \
+ m_debuginfo/readdwarf.c \
+ m_debuginfo/readdwarf3.c \
+ m_debuginfo/readelf.c \
+ m_debuginfo/readmacho.c \
+ m_debuginfo/readpdb.c \
+ m_debuginfo/readstabs.c \
+ m_debuginfo/storage.c \
+ m_debuginfo/tytypes.c \
+ m_demangle/cp-demangle.c \
+ m_demangle/cplus-dem.c \
+ m_demangle/demangle.c \
+ m_demangle/dyn-string.c \
+ m_demangle/safe-ctype.c \
+ m_dispatch/dispatch-x86-linux.S \
+ m_dispatch/dispatch-amd64-linux.S \
+ m_dispatch/dispatch-ppc32-linux.S \
+ m_dispatch/dispatch-ppc64-linux.S \
+ m_dispatch/dispatch-arm-linux.S \
+ m_dispatch/dispatch-s390x-linux.S \
+ m_dispatch/dispatch-mips32-linux.S \
+ m_dispatch/dispatch-x86-darwin.S \
+ m_dispatch/dispatch-amd64-darwin.S \
+ m_gdbserver/inferiors.c \
+ m_gdbserver/m_gdbserver.c \
+ m_gdbserver/regcache.c \
+ m_gdbserver/remote-utils.c \
+ m_gdbserver/server.c \
+ m_gdbserver/signals.c \
+ m_gdbserver/target.c \
+ m_gdbserver/utils.c \
+ m_gdbserver/valgrind-low-x86.c \
+ m_gdbserver/valgrind-low-amd64.c \
+ m_gdbserver/valgrind-low-arm.c \
+ m_gdbserver/valgrind-low-ppc32.c \
+ m_gdbserver/valgrind-low-ppc64.c \
+ m_gdbserver/valgrind-low-s390x.c \
+ m_gdbserver/valgrind-low-mips32.c \
+ m_gdbserver/version.c \
+ m_initimg/initimg-linux.c \
+ m_initimg/initimg-darwin.c \
+ m_initimg/initimg-pathscan.c \
+ m_mach/mach_basics.c \
+ m_mach/mach_msg.c \
+ m_mach/mach_traps-x86-darwin.S \
+ m_mach/mach_traps-amd64-darwin.S \
+ m_replacemalloc/replacemalloc_core.c \
+ m_scheduler/scheduler.c \
+ m_scheduler/sema.c \
+ m_scheduler/sched-lock.c \
+ m_scheduler/sched-lock-generic.c \
+ m_sigframe/sigframe-x86-linux.c \
+ m_sigframe/sigframe-amd64-linux.c \
+ m_sigframe/sigframe-ppc32-linux.c \
+ m_sigframe/sigframe-ppc64-linux.c \
+ m_sigframe/sigframe-arm-linux.c \
+ m_sigframe/sigframe-s390x-linux.c \
+ m_sigframe/sigframe-mips32-linux.c \
+ m_sigframe/sigframe-x86-darwin.c \
+ m_sigframe/sigframe-amd64-darwin.c \
+ m_syswrap/syscall-x86-linux.S \
+ m_syswrap/syscall-amd64-linux.S \
+ m_syswrap/syscall-ppc32-linux.S \
+ m_syswrap/syscall-ppc64-linux.S \
+ m_syswrap/syscall-arm-linux.S \
+ m_syswrap/syscall-s390x-linux.S \
+ m_syswrap/syscall-mips32-linux.S \
+ m_syswrap/syscall-x86-darwin.S \
+ m_syswrap/syscall-amd64-darwin.S \
+ m_syswrap/syswrap-main.c \
+ m_syswrap/syswrap-generic.c \
+ m_syswrap/syswrap-linux.c \
+ m_syswrap/syswrap-linux-variants.c \
+ m_syswrap/syswrap-darwin.c \
+ m_syswrap/syswrap-x86-linux.c \
+ m_syswrap/syswrap-amd64-linux.c \
+ m_syswrap/syswrap-ppc32-linux.c \
+ m_syswrap/syswrap-ppc64-linux.c \
+ m_syswrap/syswrap-arm-linux.c \
+ m_syswrap/syswrap-s390x-linux.c \
+ m_syswrap/syswrap-mips32-linux.c \
+ m_syswrap/syswrap-x86-darwin.c \
+ m_syswrap/syswrap-amd64-darwin.c \
+ m_ume/elf.c \
+ m_ume/macho.c \
+ m_ume/main.c \
+ m_ume/script.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES = \
+ $(COREGRIND_SOURCES_COMMON) $(am__append_12)
+nodist_libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES = \
+ $(BUILT_SOURCES)
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(am__append_13)
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS = \
+ $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(COREGRIND_SOURCES_COMMON) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__append_14)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@nodist_libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(BUILT_SOURCES)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS = $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__append_15)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CCASFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES = \
+ m_replacemalloc/vg_replace_malloc.c
+
+libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(AM_CFLAGS_PIC)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ m_replacemalloc/vg_replace_malloc.c
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) $(AM_CFLAGS_PIC)
+
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
+vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = vg_preloaded.c
+vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(AM_CFLAGS_PIC)
+
+vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
+ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = vg_preloaded.c
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) $(AM_CFLAGS_PIC)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+
+#----------------------------------------------------------------------------
+# gdbserver xml target descriptions
+#----------------------------------------------------------------------------
+GDBSERVER_XML_FILES = \
+ m_gdbserver/32bit-core-valgrind-s1.xml \
+ m_gdbserver/32bit-core-valgrind-s2.xml \
+ m_gdbserver/32bit-core.xml \
+ m_gdbserver/32bit-linux-valgrind-s1.xml \
+ m_gdbserver/32bit-linux-valgrind-s2.xml \
+ m_gdbserver/32bit-linux.xml \
+ m_gdbserver/32bit-sse-valgrind-s1.xml \
+ m_gdbserver/32bit-sse-valgrind-s2.xml \
+ m_gdbserver/32bit-sse.xml \
+ m_gdbserver/64bit-avx-valgrind-s2.xml \
+ m_gdbserver/64bit-avx-valgrind-s1.xml \
+ m_gdbserver/64bit-avx.xml \
+ m_gdbserver/64bit-core-valgrind-s1.xml \
+ m_gdbserver/64bit-core-valgrind-s2.xml \
+ m_gdbserver/64bit-core.xml \
+ m_gdbserver/64bit-linux-valgrind-s1.xml \
+ m_gdbserver/64bit-linux-valgrind-s2.xml \
+ m_gdbserver/64bit-linux.xml \
+ m_gdbserver/64bit-sse-valgrind-s1.xml \
+ m_gdbserver/64bit-sse-valgrind-s2.xml \
+ m_gdbserver/64bit-sse.xml \
+ m_gdbserver/amd64-avx-coresse-valgrind.xml \
+ m_gdbserver/amd64-avx-coresse.xml \
+ m_gdbserver/amd64-avx-linux-valgrind.xml \
+ m_gdbserver/amd64-avx-linux.xml \
+ m_gdbserver/amd64-coresse-valgrind.xml \
+ m_gdbserver/amd64-linux-valgrind.xml \
+ m_gdbserver/arm-core-valgrind-s1.xml \
+ m_gdbserver/arm-core-valgrind-s2.xml \
+ m_gdbserver/arm-core.xml \
+ m_gdbserver/arm-vfpv3-valgrind-s1.xml \
+ m_gdbserver/arm-vfpv3-valgrind-s2.xml \
+ m_gdbserver/arm-vfpv3.xml \
+ m_gdbserver/arm-with-vfpv3-valgrind.xml \
+ m_gdbserver/arm-with-vfpv3.xml \
+ m_gdbserver/i386-coresse-valgrind.xml \
+ m_gdbserver/i386-linux-valgrind.xml \
+ m_gdbserver/power64-core-valgrind-s1.xml \
+ m_gdbserver/power64-core-valgrind-s2.xml \
+ m_gdbserver/power64-core.xml \
+ m_gdbserver/power64-linux-valgrind-s1.xml \
+ m_gdbserver/power64-linux-valgrind-s2.xml \
+ m_gdbserver/power64-linux.xml \
+ m_gdbserver/power-altivec-valgrind-s1.xml \
+ m_gdbserver/power-altivec-valgrind-s2.xml \
+ m_gdbserver/power-altivec.xml \
+ m_gdbserver/power-core-valgrind-s1.xml \
+ m_gdbserver/power-core-valgrind-s2.xml \
+ m_gdbserver/power-core.xml \
+ m_gdbserver/power-fpu-valgrind-s1.xml \
+ m_gdbserver/power-fpu-valgrind-s2.xml \
+ m_gdbserver/power-fpu.xml \
+ m_gdbserver/power-linux-valgrind-s1.xml \
+ m_gdbserver/power-linux-valgrind-s2.xml \
+ m_gdbserver/power-linux.xml \
+ m_gdbserver/powerpc-altivec32l-valgrind.xml \
+ m_gdbserver/powerpc-altivec32l.xml \
+ m_gdbserver/powerpc-altivec64l-valgrind.xml \
+ m_gdbserver/powerpc-altivec64l.xml \
+ m_gdbserver/s390-acr-valgrind-s1.xml \
+ m_gdbserver/s390-acr-valgrind-s2.xml \
+ m_gdbserver/s390-acr.xml \
+ m_gdbserver/s390-fpr-valgrind-s1.xml \
+ m_gdbserver/s390-fpr-valgrind-s2.xml \
+ m_gdbserver/s390-fpr.xml \
+ m_gdbserver/s390x-core64-valgrind-s1.xml \
+ m_gdbserver/s390x-core64-valgrind-s2.xml \
+ m_gdbserver/s390x-core64.xml \
+ m_gdbserver/s390x-generic-valgrind.xml \
+ m_gdbserver/s390x-generic.xml \
+ m_gdbserver/s390x-linux64-valgrind-s1.xml \
+ m_gdbserver/s390x-linux64-valgrind-s2.xml \
+ m_gdbserver/s390x-linux64.xml \
+ m_gdbserver/mips-cp0-valgrind-s1.xml \
+ m_gdbserver/mips-cp0-valgrind-s2.xml \
+ m_gdbserver/mips-cp0.xml \
+ m_gdbserver/mips-cpu-valgrind-s1.xml \
+ m_gdbserver/mips-cpu-valgrind-s2.xml \
+ m_gdbserver/mips-cpu.xml \
+ m_gdbserver/mips-linux.xml \
+ m_gdbserver/mips-linux-valgrind.xml \
+ m_gdbserver/mips-fpu-valgrind-s1.xml \
+ m_gdbserver/mips-fpu-valgrind-s2.xml \
+ m_gdbserver/mips-fpu.xml
+
+
+# so as to make sure these get copied into the install tree
+vglibdir = $(pkglibdir)
+vglib_DATA = $(GDBSERVER_XML_FILES)
+all: $(BUILT_SOURCES)
+ $(MAKE) $(AM_MAKEFLAGS) all-am
+
+.SUFFIXES:
+.SUFFIXES: .S .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign coregrind/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign coregrind/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+link_tool_exe_linux: $(top_builddir)/config.status $(srcdir)/link_tool_exe_linux.in
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+link_tool_exe_darwin: $(top_builddir)/config.status $(srcdir)/link_tool_exe_darwin.in
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+install-pkglibLIBRARIES: $(pkglib_LIBRARIES)
+ @$(NORMAL_INSTALL)
+ test -z "$(pkglibdir)" || $(MKDIR_P) "$(DESTDIR)$(pkglibdir)"
+ @list='$(pkglib_LIBRARIES)'; test -n "$(pkglibdir)" || list=; \
+ list2=; for p in $$list; do \
+ if test -f $$p; then \
+ list2="$$list2 $$p"; \
+ else :; fi; \
+ done; \
+ test -z "$$list2" || { \
+ echo " $(INSTALL_DATA) $$list2 '$(DESTDIR)$(pkglibdir)'"; \
+ $(INSTALL_DATA) $$list2 "$(DESTDIR)$(pkglibdir)" || exit $$?; }
+ @$(POST_INSTALL)
+ @list='$(pkglib_LIBRARIES)'; test -n "$(pkglibdir)" || list=; \
+ for p in $$list; do \
+ if test -f $$p; then \
+ $(am__strip_dir) \
+ echo " ( cd '$(DESTDIR)$(pkglibdir)' && $(RANLIB) $$f )"; \
+ ( cd "$(DESTDIR)$(pkglibdir)" && $(RANLIB) $$f ) || exit $$?; \
+ else :; fi; \
+ done
+
+uninstall-pkglibLIBRARIES:
+ @$(NORMAL_UNINSTALL)
+ @list='$(pkglib_LIBRARIES)'; test -n "$(pkglibdir)" || list=; \
+ files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
+ test -n "$$files" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(pkglibdir)' && rm -f "$$files" )"; \
+ cd "$(DESTDIR)$(pkglibdir)" && rm -f $$files
+
+clean-pkglibLIBRARIES:
+ -test -z "$(pkglib_LIBRARIES)" || rm -f $(pkglib_LIBRARIES)
+libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a: $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_DEPENDENCIES)
+ -rm -f libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+ $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_AR) libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_LIBADD)
+ $(RANLIB) libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a: $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_DEPENDENCIES)
+ -rm -f libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+ $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_AR) libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_LIBADD)
+ $(RANLIB) libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+libreplacemalloc_toolpreload-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a: $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_DEPENDENCIES)
+ -rm -f libreplacemalloc_toolpreload-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+ $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_AR) libreplacemalloc_toolpreload-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_OBJECTS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_LIBADD)
+ $(RANLIB) libreplacemalloc_toolpreload-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+libreplacemalloc_toolpreload-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a: $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_DEPENDENCIES)
+ -rm -f libreplacemalloc_toolpreload-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+ $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_AR) libreplacemalloc_toolpreload-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_OBJECTS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_LIBADD)
+ $(RANLIB) libreplacemalloc_toolpreload-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+install-binPROGRAMS: $(bin_PROGRAMS)
+ @$(NORMAL_INSTALL)
+ test -z "$(bindir)" || $(MKDIR_P) "$(DESTDIR)$(bindir)"
+ @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed 's/$(EXEEXT)$$//' | \
+ while read p p1; do if test -f $$p; \
+ then echo "$$p"; echo "$$p"; else :; fi; \
+ done | \
+ sed -e 'p;s,.*/,,;n;h' -e 's|.*|.|' \
+ -e 'p;x;s,.*/,,;s/$(EXEEXT)$$//;$(transform);s/$$/$(EXEEXT)/' | \
+ sed 'N;N;N;s,\n, ,g' | \
+ $(AWK) 'BEGIN { files["."] = ""; dirs["."] = 1 } \
+ { d=$$3; if (dirs[d] != 1) { print "d", d; dirs[d] = 1 } \
+ if ($$2 == $$4) files[d] = files[d] " " $$1; \
+ else { print "f", $$3 "/" $$4, $$1; } } \
+ END { for (d in files) print "f", d, files[d] }' | \
+ while read type dir files; do \
+ if test "$$dir" = .; then dir=; else dir=/$$dir; fi; \
+ test -z "$$files" || { \
+ echo " $(INSTALL_PROGRAM_ENV) $(INSTALL_PROGRAM) $$files '$(DESTDIR)$(bindir)$$dir'"; \
+ $(INSTALL_PROGRAM_ENV) $(INSTALL_PROGRAM) $$files "$(DESTDIR)$(bindir)$$dir" || exit $$?; \
+ } \
+ ; done
+
+uninstall-binPROGRAMS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \
+ files=`for p in $$list; do echo "$$p"; done | \
+ sed -e 'h;s,^.*/,,;s/$(EXEEXT)$$//;$(transform)' \
+ -e 's/$$/$(EXEEXT)/' `; \
+ test -n "$$list" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(bindir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(bindir)" && rm -f $$files
+
+clean-binPROGRAMS:
+ -test -z "$(bin_PROGRAMS)" || rm -f $(bin_PROGRAMS)
+
+clean-noinstPROGRAMS:
+ -test -z "$(noinst_PROGRAMS)" || rm -f $(noinst_PROGRAMS)
+valgrind$(EXEEXT): $(valgrind_OBJECTS) $(valgrind_DEPENDENCIES)
+ @rm -f valgrind$(EXEEXT)
+ $(valgrind_LINK) $(valgrind_OBJECTS) $(valgrind_LDADD) $(LIBS)
+vgdb$(EXEEXT): $(vgdb_OBJECTS) $(vgdb_DEPENDENCIES)
+ @rm -f vgdb$(EXEEXT)
+ $(vgdb_LINK) $(vgdb_OBJECTS) $(vgdb_LDADD) $(LIBS)
+vgpreload_core-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_core-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD) $(LIBS)
+vgpreload_core-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_core-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/valgrind-launcher-darwin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/valgrind-launcher-linux.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/valgrind-m_debuglog.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgdb-vgdb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.Po@am__quote@
+
+.S.o:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ $<
+
+.S.obj:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.o: m_cpuid.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.o `test -f 'm_cpuid.S' || echo '$(srcdir)/'`m_cpuid.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_cpuid.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.o `test -f 'm_cpuid.S' || echo '$(srcdir)/'`m_cpuid.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.obj: m_cpuid.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.obj `if test -f 'm_cpuid.S'; then $(CYGPATH_W) 'm_cpuid.S'; else $(CYGPATH_W) '$(srcdir)/m_cpuid.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_cpuid.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_cpuid.obj `if test -f 'm_cpuid.S'; then $(CYGPATH_W) 'm_cpuid.S'; else $(CYGPATH_W) '$(srcdir)/m_cpuid.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.o: m_trampoline.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.o `test -f 'm_trampoline.S' || echo '$(srcdir)/'`m_trampoline.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_trampoline.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.o `test -f 'm_trampoline.S' || echo '$(srcdir)/'`m_trampoline.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.obj: m_trampoline.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.obj `if test -f 'm_trampoline.S'; then $(CYGPATH_W) 'm_trampoline.S'; else $(CYGPATH_W) '$(srcdir)/m_trampoline.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_trampoline.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_trampoline.obj `if test -f 'm_trampoline.S'; then $(CYGPATH_W) 'm_trampoline.S'; else $(CYGPATH_W) '$(srcdir)/m_trampoline.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.o: m_dispatch/dispatch-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.o `test -f 'm_dispatch/dispatch-x86-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-x86-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.o `test -f 'm_dispatch/dispatch-x86-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-x86-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.obj: m_dispatch/dispatch-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.obj `if test -f 'm_dispatch/dispatch-x86-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-x86-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-x86-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-x86-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-linux.obj `if test -f 'm_dispatch/dispatch-x86-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-x86-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-x86-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.o: m_dispatch/dispatch-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.o `test -f 'm_dispatch/dispatch-amd64-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-amd64-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.o `test -f 'm_dispatch/dispatch-amd64-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-amd64-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.obj: m_dispatch/dispatch-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.obj `if test -f 'm_dispatch/dispatch-amd64-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-amd64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-amd64-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-amd64-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-linux.obj `if test -f 'm_dispatch/dispatch-amd64-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-amd64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-amd64-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.o: m_dispatch/dispatch-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.o `test -f 'm_dispatch/dispatch-ppc32-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-ppc32-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.o `test -f 'm_dispatch/dispatch-ppc32-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-ppc32-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj: m_dispatch/dispatch-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj `if test -f 'm_dispatch/dispatch-ppc32-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-ppc32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-ppc32-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-ppc32-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj `if test -f 'm_dispatch/dispatch-ppc32-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-ppc32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-ppc32-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.o: m_dispatch/dispatch-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.o `test -f 'm_dispatch/dispatch-ppc64-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-ppc64-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.o `test -f 'm_dispatch/dispatch-ppc64-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-ppc64-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj: m_dispatch/dispatch-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj `if test -f 'm_dispatch/dispatch-ppc64-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-ppc64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-ppc64-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-ppc64-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj `if test -f 'm_dispatch/dispatch-ppc64-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-ppc64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-ppc64-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.o: m_dispatch/dispatch-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.o `test -f 'm_dispatch/dispatch-arm-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-arm-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.o `test -f 'm_dispatch/dispatch-arm-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-arm-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.obj: m_dispatch/dispatch-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.obj `if test -f 'm_dispatch/dispatch-arm-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-arm-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-arm-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-arm-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-arm-linux.obj `if test -f 'm_dispatch/dispatch-arm-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-arm-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-arm-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.o: m_dispatch/dispatch-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.o `test -f 'm_dispatch/dispatch-s390x-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-s390x-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.o `test -f 'm_dispatch/dispatch-s390x-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-s390x-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.obj: m_dispatch/dispatch-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.obj `if test -f 'm_dispatch/dispatch-s390x-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-s390x-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-s390x-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-s390x-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-s390x-linux.obj `if test -f 'm_dispatch/dispatch-s390x-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-s390x-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-s390x-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.o: m_dispatch/dispatch-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.o `test -f 'm_dispatch/dispatch-mips32-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-mips32-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.o `test -f 'm_dispatch/dispatch-mips32-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-mips32-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.obj: m_dispatch/dispatch-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.obj `if test -f 'm_dispatch/dispatch-mips32-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-mips32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-mips32-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-mips32-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-mips32-linux.obj `if test -f 'm_dispatch/dispatch-mips32-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-mips32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-mips32-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.o: m_dispatch/dispatch-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.o `test -f 'm_dispatch/dispatch-x86-darwin.S' || echo '$(srcdir)/'`m_dispatch/dispatch-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.o `test -f 'm_dispatch/dispatch-x86-darwin.S' || echo '$(srcdir)/'`m_dispatch/dispatch-x86-darwin.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.obj: m_dispatch/dispatch-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.obj `if test -f 'm_dispatch/dispatch-x86-darwin.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-x86-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-x86-darwin.obj `if test -f 'm_dispatch/dispatch-x86-darwin.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-x86-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.o: m_dispatch/dispatch-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.o `test -f 'm_dispatch/dispatch-amd64-darwin.S' || echo '$(srcdir)/'`m_dispatch/dispatch-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.o `test -f 'm_dispatch/dispatch-amd64-darwin.S' || echo '$(srcdir)/'`m_dispatch/dispatch-amd64-darwin.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj: m_dispatch/dispatch-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj `if test -f 'm_dispatch/dispatch-amd64-darwin.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-amd64-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj `if test -f 'm_dispatch/dispatch-amd64-darwin.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-amd64-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.o: m_mach/mach_traps-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.o `test -f 'm_mach/mach_traps-x86-darwin.S' || echo '$(srcdir)/'`m_mach/mach_traps-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_mach/mach_traps-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.o `test -f 'm_mach/mach_traps-x86-darwin.S' || echo '$(srcdir)/'`m_mach/mach_traps-x86-darwin.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj: m_mach/mach_traps-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj `if test -f 'm_mach/mach_traps-x86-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-x86-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_mach/mach_traps-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj `if test -f 'm_mach/mach_traps-x86-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-x86-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o: m_mach/mach_traps-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o `test -f 'm_mach/mach_traps-amd64-darwin.S' || echo '$(srcdir)/'`m_mach/mach_traps-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_mach/mach_traps-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o `test -f 'm_mach/mach_traps-amd64-darwin.S' || echo '$(srcdir)/'`m_mach/mach_traps-amd64-darwin.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj: m_mach/mach_traps-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj `if test -f 'm_mach/mach_traps-amd64-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-amd64-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_mach/mach_traps-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj `if test -f 'm_mach/mach_traps-amd64-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-amd64-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o: m_syswrap/syscall-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o `test -f 'm_syswrap/syscall-x86-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-x86-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o `test -f 'm_syswrap/syscall-x86-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.obj: m_syswrap/syscall-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.obj `if test -f 'm_syswrap/syscall-x86-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-x86-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-x86-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-x86-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.obj `if test -f 'm_syswrap/syscall-x86-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-x86-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-x86-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.o: m_syswrap/syscall-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.o `test -f 'm_syswrap/syscall-amd64-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-amd64-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.o `test -f 'm_syswrap/syscall-amd64-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-amd64-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.obj: m_syswrap/syscall-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.obj `if test -f 'm_syswrap/syscall-amd64-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-amd64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-amd64-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-amd64-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.obj `if test -f 'm_syswrap/syscall-amd64-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-amd64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-amd64-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.o: m_syswrap/syscall-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.o `test -f 'm_syswrap/syscall-ppc32-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-ppc32-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.o `test -f 'm_syswrap/syscall-ppc32-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-ppc32-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.obj: m_syswrap/syscall-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.obj `if test -f 'm_syswrap/syscall-ppc32-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-ppc32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-ppc32-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-ppc32-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.obj `if test -f 'm_syswrap/syscall-ppc32-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-ppc32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-ppc32-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.o: m_syswrap/syscall-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.o `test -f 'm_syswrap/syscall-ppc64-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-ppc64-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.o `test -f 'm_syswrap/syscall-ppc64-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-ppc64-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.obj: m_syswrap/syscall-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.obj `if test -f 'm_syswrap/syscall-ppc64-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-ppc64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-ppc64-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-ppc64-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc64-linux.obj `if test -f 'm_syswrap/syscall-ppc64-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-ppc64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-ppc64-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.o: m_syswrap/syscall-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.o `test -f 'm_syswrap/syscall-arm-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-arm-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.o `test -f 'm_syswrap/syscall-arm-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-arm-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.obj: m_syswrap/syscall-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.obj `if test -f 'm_syswrap/syscall-arm-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-arm-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-arm-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-arm-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-arm-linux.obj `if test -f 'm_syswrap/syscall-arm-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-arm-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-arm-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.o: m_syswrap/syscall-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.o `test -f 'm_syswrap/syscall-s390x-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-s390x-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.o `test -f 'm_syswrap/syscall-s390x-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-s390x-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.obj: m_syswrap/syscall-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.obj `if test -f 'm_syswrap/syscall-s390x-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-s390x-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-s390x-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-s390x-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-s390x-linux.obj `if test -f 'm_syswrap/syscall-s390x-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-s390x-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-s390x-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.o: m_syswrap/syscall-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.o `test -f 'm_syswrap/syscall-mips32-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-mips32-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.o `test -f 'm_syswrap/syscall-mips32-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-mips32-linux.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.obj: m_syswrap/syscall-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.obj `if test -f 'm_syswrap/syscall-mips32-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-mips32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-mips32-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-mips32-linux.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-mips32-linux.obj `if test -f 'm_syswrap/syscall-mips32-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-mips32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-mips32-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.o: m_syswrap/syscall-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.o `test -f 'm_syswrap/syscall-x86-darwin.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.o `test -f 'm_syswrap/syscall-x86-darwin.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-darwin.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.obj: m_syswrap/syscall-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.obj `if test -f 'm_syswrap/syscall-x86-darwin.S'; then $(CYGPATH_W) 'm_syswrap/syscall-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-x86-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-darwin.obj `if test -f 'm_syswrap/syscall-x86-darwin.S'; then $(CYGPATH_W) 'm_syswrap/syscall-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-x86-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.o: m_syswrap/syscall-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.o `test -f 'm_syswrap/syscall-amd64-darwin.S' || echo '$(srcdir)/'`m_syswrap/syscall-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.o `test -f 'm_syswrap/syscall-amd64-darwin.S' || echo '$(srcdir)/'`m_syswrap/syscall-amd64-darwin.S
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.obj: m_syswrap/syscall-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.obj `if test -f 'm_syswrap/syscall-amd64-darwin.S'; then $(CYGPATH_W) 'm_syswrap/syscall-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-amd64-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-darwin.obj `if test -f 'm_syswrap/syscall-amd64-darwin.S'; then $(CYGPATH_W) 'm_syswrap/syscall-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-amd64-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.o: m_cpuid.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.o `test -f 'm_cpuid.S' || echo '$(srcdir)/'`m_cpuid.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_cpuid.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.o `test -f 'm_cpuid.S' || echo '$(srcdir)/'`m_cpuid.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.obj: m_cpuid.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.obj `if test -f 'm_cpuid.S'; then $(CYGPATH_W) 'm_cpuid.S'; else $(CYGPATH_W) '$(srcdir)/m_cpuid.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_cpuid.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_cpuid.obj `if test -f 'm_cpuid.S'; then $(CYGPATH_W) 'm_cpuid.S'; else $(CYGPATH_W) '$(srcdir)/m_cpuid.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.o: m_trampoline.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.o `test -f 'm_trampoline.S' || echo '$(srcdir)/'`m_trampoline.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_trampoline.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.o `test -f 'm_trampoline.S' || echo '$(srcdir)/'`m_trampoline.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.obj: m_trampoline.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.obj `if test -f 'm_trampoline.S'; then $(CYGPATH_W) 'm_trampoline.S'; else $(CYGPATH_W) '$(srcdir)/m_trampoline.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_trampoline.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_trampoline.obj `if test -f 'm_trampoline.S'; then $(CYGPATH_W) 'm_trampoline.S'; else $(CYGPATH_W) '$(srcdir)/m_trampoline.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.o: m_dispatch/dispatch-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.o `test -f 'm_dispatch/dispatch-x86-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-x86-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.o `test -f 'm_dispatch/dispatch-x86-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-x86-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.obj: m_dispatch/dispatch-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.obj `if test -f 'm_dispatch/dispatch-x86-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-x86-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-x86-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-x86-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-linux.obj `if test -f 'm_dispatch/dispatch-x86-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-x86-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-x86-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.o: m_dispatch/dispatch-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.o `test -f 'm_dispatch/dispatch-amd64-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-amd64-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.o `test -f 'm_dispatch/dispatch-amd64-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-amd64-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.obj: m_dispatch/dispatch-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.obj `if test -f 'm_dispatch/dispatch-amd64-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-amd64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-amd64-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-amd64-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-linux.obj `if test -f 'm_dispatch/dispatch-amd64-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-amd64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-amd64-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.o: m_dispatch/dispatch-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.o `test -f 'm_dispatch/dispatch-ppc32-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-ppc32-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.o `test -f 'm_dispatch/dispatch-ppc32-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-ppc32-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj: m_dispatch/dispatch-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj `if test -f 'm_dispatch/dispatch-ppc32-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-ppc32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-ppc32-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-ppc32-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc32-linux.obj `if test -f 'm_dispatch/dispatch-ppc32-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-ppc32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-ppc32-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.o: m_dispatch/dispatch-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.o `test -f 'm_dispatch/dispatch-ppc64-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-ppc64-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.o `test -f 'm_dispatch/dispatch-ppc64-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-ppc64-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj: m_dispatch/dispatch-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj `if test -f 'm_dispatch/dispatch-ppc64-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-ppc64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-ppc64-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-ppc64-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-ppc64-linux.obj `if test -f 'm_dispatch/dispatch-ppc64-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-ppc64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-ppc64-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.o: m_dispatch/dispatch-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.o `test -f 'm_dispatch/dispatch-arm-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-arm-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.o `test -f 'm_dispatch/dispatch-arm-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-arm-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.obj: m_dispatch/dispatch-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.obj `if test -f 'm_dispatch/dispatch-arm-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-arm-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-arm-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-arm-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-arm-linux.obj `if test -f 'm_dispatch/dispatch-arm-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-arm-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-arm-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.o: m_dispatch/dispatch-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.o `test -f 'm_dispatch/dispatch-s390x-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-s390x-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.o `test -f 'm_dispatch/dispatch-s390x-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-s390x-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.obj: m_dispatch/dispatch-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.obj `if test -f 'm_dispatch/dispatch-s390x-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-s390x-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-s390x-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-s390x-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-s390x-linux.obj `if test -f 'm_dispatch/dispatch-s390x-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-s390x-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-s390x-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.o: m_dispatch/dispatch-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.o `test -f 'm_dispatch/dispatch-mips32-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-mips32-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.o `test -f 'm_dispatch/dispatch-mips32-linux.S' || echo '$(srcdir)/'`m_dispatch/dispatch-mips32-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.obj: m_dispatch/dispatch-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.obj `if test -f 'm_dispatch/dispatch-mips32-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-mips32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-mips32-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-mips32-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-mips32-linux.obj `if test -f 'm_dispatch/dispatch-mips32-linux.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-mips32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-mips32-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.o: m_dispatch/dispatch-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.o `test -f 'm_dispatch/dispatch-x86-darwin.S' || echo '$(srcdir)/'`m_dispatch/dispatch-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.o `test -f 'm_dispatch/dispatch-x86-darwin.S' || echo '$(srcdir)/'`m_dispatch/dispatch-x86-darwin.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.obj: m_dispatch/dispatch-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.obj `if test -f 'm_dispatch/dispatch-x86-darwin.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-x86-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-x86-darwin.obj `if test -f 'm_dispatch/dispatch-x86-darwin.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-x86-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.o: m_dispatch/dispatch-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.o `test -f 'm_dispatch/dispatch-amd64-darwin.S' || echo '$(srcdir)/'`m_dispatch/dispatch-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.o `test -f 'm_dispatch/dispatch-amd64-darwin.S' || echo '$(srcdir)/'`m_dispatch/dispatch-amd64-darwin.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj: m_dispatch/dispatch-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj `if test -f 'm_dispatch/dispatch-amd64-darwin.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-amd64-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_dispatch/dispatch-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dispatch-amd64-darwin.obj `if test -f 'm_dispatch/dispatch-amd64-darwin.S'; then $(CYGPATH_W) 'm_dispatch/dispatch-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_dispatch/dispatch-amd64-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.o: m_mach/mach_traps-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.o `test -f 'm_mach/mach_traps-x86-darwin.S' || echo '$(srcdir)/'`m_mach/mach_traps-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_mach/mach_traps-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.o `test -f 'm_mach/mach_traps-x86-darwin.S' || echo '$(srcdir)/'`m_mach/mach_traps-x86-darwin.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj: m_mach/mach_traps-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj `if test -f 'm_mach/mach_traps-x86-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-x86-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_mach/mach_traps-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-x86-darwin.obj `if test -f 'm_mach/mach_traps-x86-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-x86-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o: m_mach/mach_traps-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o `test -f 'm_mach/mach_traps-amd64-darwin.S' || echo '$(srcdir)/'`m_mach/mach_traps-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_mach/mach_traps-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.o `test -f 'm_mach/mach_traps-amd64-darwin.S' || echo '$(srcdir)/'`m_mach/mach_traps-amd64-darwin.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj: m_mach/mach_traps-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj `if test -f 'm_mach/mach_traps-amd64-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-amd64-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_mach/mach_traps-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj `if test -f 'm_mach/mach_traps-amd64-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-amd64-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o: m_syswrap/syscall-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o `test -f 'm_syswrap/syscall-x86-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-x86-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o `test -f 'm_syswrap/syscall-x86-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.obj: m_syswrap/syscall-x86-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.obj `if test -f 'm_syswrap/syscall-x86-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-x86-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-x86-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-x86-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.obj `if test -f 'm_syswrap/syscall-x86-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-x86-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-x86-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.o: m_syswrap/syscall-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.o `test -f 'm_syswrap/syscall-amd64-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-amd64-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.o `test -f 'm_syswrap/syscall-amd64-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-amd64-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.obj: m_syswrap/syscall-amd64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.obj `if test -f 'm_syswrap/syscall-amd64-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-amd64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-amd64-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-amd64-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.obj `if test -f 'm_syswrap/syscall-amd64-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-amd64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-amd64-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.o: m_syswrap/syscall-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.o `test -f 'm_syswrap/syscall-ppc32-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-ppc32-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.o `test -f 'm_syswrap/syscall-ppc32-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-ppc32-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.obj: m_syswrap/syscall-ppc32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.obj `if test -f 'm_syswrap/syscall-ppc32-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-ppc32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-ppc32-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-ppc32-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.obj `if test -f 'm_syswrap/syscall-ppc32-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-ppc32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-ppc32-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.o: m_syswrap/syscall-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.o `test -f 'm_syswrap/syscall-ppc64-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-ppc64-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.o `test -f 'm_syswrap/syscall-ppc64-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-ppc64-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.obj: m_syswrap/syscall-ppc64-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.obj `if test -f 'm_syswrap/syscall-ppc64-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-ppc64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-ppc64-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-ppc64-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc64-linux.obj `if test -f 'm_syswrap/syscall-ppc64-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-ppc64-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-ppc64-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.o: m_syswrap/syscall-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.o `test -f 'm_syswrap/syscall-arm-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-arm-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.o `test -f 'm_syswrap/syscall-arm-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-arm-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.obj: m_syswrap/syscall-arm-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.obj `if test -f 'm_syswrap/syscall-arm-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-arm-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-arm-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-arm-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-arm-linux.obj `if test -f 'm_syswrap/syscall-arm-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-arm-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-arm-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.o: m_syswrap/syscall-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.o `test -f 'm_syswrap/syscall-s390x-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-s390x-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.o `test -f 'm_syswrap/syscall-s390x-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-s390x-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.obj: m_syswrap/syscall-s390x-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.obj `if test -f 'm_syswrap/syscall-s390x-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-s390x-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-s390x-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-s390x-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-s390x-linux.obj `if test -f 'm_syswrap/syscall-s390x-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-s390x-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-s390x-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.o: m_syswrap/syscall-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.o `test -f 'm_syswrap/syscall-mips32-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-mips32-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.o `test -f 'm_syswrap/syscall-mips32-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-mips32-linux.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.obj: m_syswrap/syscall-mips32-linux.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.obj `if test -f 'm_syswrap/syscall-mips32-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-mips32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-mips32-linux.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-mips32-linux.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-mips32-linux.obj `if test -f 'm_syswrap/syscall-mips32-linux.S'; then $(CYGPATH_W) 'm_syswrap/syscall-mips32-linux.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-mips32-linux.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.o: m_syswrap/syscall-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.o `test -f 'm_syswrap/syscall-x86-darwin.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.o `test -f 'm_syswrap/syscall-x86-darwin.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-darwin.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.obj: m_syswrap/syscall-x86-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.obj `if test -f 'm_syswrap/syscall-x86-darwin.S'; then $(CYGPATH_W) 'm_syswrap/syscall-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-x86-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-darwin.obj `if test -f 'm_syswrap/syscall-x86-darwin.S'; then $(CYGPATH_W) 'm_syswrap/syscall-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-x86-darwin.S'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.o: m_syswrap/syscall-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.o `test -f 'm_syswrap/syscall-amd64-darwin.S' || echo '$(srcdir)/'`m_syswrap/syscall-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.o `test -f 'm_syswrap/syscall-amd64-darwin.S' || echo '$(srcdir)/'`m_syswrap/syscall-amd64-darwin.S
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.obj: m_syswrap/syscall-amd64-darwin.S
+@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.obj `if test -f 'm_syswrap/syscall-amd64-darwin.S'; then $(CYGPATH_W) 'm_syswrap/syscall-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-amd64-darwin.S'; fi`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='m_syswrap/syscall-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-darwin.obj `if test -f 'm_syswrap/syscall-amd64-darwin.S'; then $(CYGPATH_W) 'm_syswrap/syscall-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syscall-amd64-darwin.S'; fi`
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.o: m_commandline.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.o `test -f 'm_commandline.c' || echo '$(srcdir)/'`m_commandline.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_commandline.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.o `test -f 'm_commandline.c' || echo '$(srcdir)/'`m_commandline.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.obj: m_commandline.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.obj `if test -f 'm_commandline.c'; then $(CYGPATH_W) 'm_commandline.c'; else $(CYGPATH_W) '$(srcdir)/m_commandline.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_commandline.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.obj `if test -f 'm_commandline.c'; then $(CYGPATH_W) 'm_commandline.c'; else $(CYGPATH_W) '$(srcdir)/m_commandline.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.o: m_clientstate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.o `test -f 'm_clientstate.c' || echo '$(srcdir)/'`m_clientstate.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_clientstate.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.o `test -f 'm_clientstate.c' || echo '$(srcdir)/'`m_clientstate.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.obj: m_clientstate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.obj `if test -f 'm_clientstate.c'; then $(CYGPATH_W) 'm_clientstate.c'; else $(CYGPATH_W) '$(srcdir)/m_clientstate.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_clientstate.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_clientstate.obj `if test -f 'm_clientstate.c'; then $(CYGPATH_W) 'm_clientstate.c'; else $(CYGPATH_W) '$(srcdir)/m_clientstate.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.o: m_debugger.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.o `test -f 'm_debugger.c' || echo '$(srcdir)/'`m_debugger.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debugger.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.o `test -f 'm_debugger.c' || echo '$(srcdir)/'`m_debugger.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.obj: m_debugger.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.obj `if test -f 'm_debugger.c'; then $(CYGPATH_W) 'm_debugger.c'; else $(CYGPATH_W) '$(srcdir)/m_debugger.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debugger.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debugger.obj `if test -f 'm_debugger.c'; then $(CYGPATH_W) 'm_debugger.c'; else $(CYGPATH_W) '$(srcdir)/m_debugger.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.o: m_debuglog.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.o `test -f 'm_debuglog.c' || echo '$(srcdir)/'`m_debuglog.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuglog.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.o `test -f 'm_debuglog.c' || echo '$(srcdir)/'`m_debuglog.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.obj: m_debuglog.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.obj `if test -f 'm_debuglog.c'; then $(CYGPATH_W) 'm_debuglog.c'; else $(CYGPATH_W) '$(srcdir)/m_debuglog.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuglog.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_debuglog.obj `if test -f 'm_debuglog.c'; then $(CYGPATH_W) 'm_debuglog.c'; else $(CYGPATH_W) '$(srcdir)/m_debuglog.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.o: m_errormgr.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.o `test -f 'm_errormgr.c' || echo '$(srcdir)/'`m_errormgr.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_errormgr.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.o `test -f 'm_errormgr.c' || echo '$(srcdir)/'`m_errormgr.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.obj: m_errormgr.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.obj `if test -f 'm_errormgr.c'; then $(CYGPATH_W) 'm_errormgr.c'; else $(CYGPATH_W) '$(srcdir)/m_errormgr.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_errormgr.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_errormgr.obj `if test -f 'm_errormgr.c'; then $(CYGPATH_W) 'm_errormgr.c'; else $(CYGPATH_W) '$(srcdir)/m_errormgr.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.o: m_execontext.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.o `test -f 'm_execontext.c' || echo '$(srcdir)/'`m_execontext.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_execontext.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.o `test -f 'm_execontext.c' || echo '$(srcdir)/'`m_execontext.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.obj: m_execontext.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.obj `if test -f 'm_execontext.c'; then $(CYGPATH_W) 'm_execontext.c'; else $(CYGPATH_W) '$(srcdir)/m_execontext.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_execontext.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_execontext.obj `if test -f 'm_execontext.c'; then $(CYGPATH_W) 'm_execontext.c'; else $(CYGPATH_W) '$(srcdir)/m_execontext.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.o: m_poolalloc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.o `test -f 'm_poolalloc.c' || echo '$(srcdir)/'`m_poolalloc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_poolalloc.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.o `test -f 'm_poolalloc.c' || echo '$(srcdir)/'`m_poolalloc.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.obj: m_poolalloc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.obj `if test -f 'm_poolalloc.c'; then $(CYGPATH_W) 'm_poolalloc.c'; else $(CYGPATH_W) '$(srcdir)/m_poolalloc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_poolalloc.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_poolalloc.obj `if test -f 'm_poolalloc.c'; then $(CYGPATH_W) 'm_poolalloc.c'; else $(CYGPATH_W) '$(srcdir)/m_poolalloc.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.o: m_hashtable.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.o `test -f 'm_hashtable.c' || echo '$(srcdir)/'`m_hashtable.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_hashtable.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.o `test -f 'm_hashtable.c' || echo '$(srcdir)/'`m_hashtable.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.obj: m_hashtable.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.obj `if test -f 'm_hashtable.c'; then $(CYGPATH_W) 'm_hashtable.c'; else $(CYGPATH_W) '$(srcdir)/m_hashtable.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_hashtable.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_hashtable.obj `if test -f 'm_hashtable.c'; then $(CYGPATH_W) 'm_hashtable.c'; else $(CYGPATH_W) '$(srcdir)/m_hashtable.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.o: m_libcbase.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.o `test -f 'm_libcbase.c' || echo '$(srcdir)/'`m_libcbase.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcbase.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.o `test -f 'm_libcbase.c' || echo '$(srcdir)/'`m_libcbase.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.obj: m_libcbase.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.obj `if test -f 'm_libcbase.c'; then $(CYGPATH_W) 'm_libcbase.c'; else $(CYGPATH_W) '$(srcdir)/m_libcbase.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcbase.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcbase.obj `if test -f 'm_libcbase.c'; then $(CYGPATH_W) 'm_libcbase.c'; else $(CYGPATH_W) '$(srcdir)/m_libcbase.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.o: m_libcassert.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.o `test -f 'm_libcassert.c' || echo '$(srcdir)/'`m_libcassert.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcassert.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.o `test -f 'm_libcassert.c' || echo '$(srcdir)/'`m_libcassert.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.obj: m_libcassert.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.obj `if test -f 'm_libcassert.c'; then $(CYGPATH_W) 'm_libcassert.c'; else $(CYGPATH_W) '$(srcdir)/m_libcassert.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcassert.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcassert.obj `if test -f 'm_libcassert.c'; then $(CYGPATH_W) 'm_libcassert.c'; else $(CYGPATH_W) '$(srcdir)/m_libcassert.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.o: m_libcfile.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.o `test -f 'm_libcfile.c' || echo '$(srcdir)/'`m_libcfile.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcfile.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.o `test -f 'm_libcfile.c' || echo '$(srcdir)/'`m_libcfile.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.obj: m_libcfile.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.obj `if test -f 'm_libcfile.c'; then $(CYGPATH_W) 'm_libcfile.c'; else $(CYGPATH_W) '$(srcdir)/m_libcfile.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcfile.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcfile.obj `if test -f 'm_libcfile.c'; then $(CYGPATH_W) 'm_libcfile.c'; else $(CYGPATH_W) '$(srcdir)/m_libcfile.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.o: m_libcprint.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.o `test -f 'm_libcprint.c' || echo '$(srcdir)/'`m_libcprint.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcprint.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.o `test -f 'm_libcprint.c' || echo '$(srcdir)/'`m_libcprint.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.obj: m_libcprint.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.obj `if test -f 'm_libcprint.c'; then $(CYGPATH_W) 'm_libcprint.c'; else $(CYGPATH_W) '$(srcdir)/m_libcprint.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcprint.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcprint.obj `if test -f 'm_libcprint.c'; then $(CYGPATH_W) 'm_libcprint.c'; else $(CYGPATH_W) '$(srcdir)/m_libcprint.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.o: m_libcproc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.o `test -f 'm_libcproc.c' || echo '$(srcdir)/'`m_libcproc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcproc.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.o `test -f 'm_libcproc.c' || echo '$(srcdir)/'`m_libcproc.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.obj: m_libcproc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.obj `if test -f 'm_libcproc.c'; then $(CYGPATH_W) 'm_libcproc.c'; else $(CYGPATH_W) '$(srcdir)/m_libcproc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcproc.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcproc.obj `if test -f 'm_libcproc.c'; then $(CYGPATH_W) 'm_libcproc.c'; else $(CYGPATH_W) '$(srcdir)/m_libcproc.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.o: m_libcsetjmp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.o `test -f 'm_libcsetjmp.c' || echo '$(srcdir)/'`m_libcsetjmp.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcsetjmp.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.o `test -f 'm_libcsetjmp.c' || echo '$(srcdir)/'`m_libcsetjmp.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.obj: m_libcsetjmp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.obj `if test -f 'm_libcsetjmp.c'; then $(CYGPATH_W) 'm_libcsetjmp.c'; else $(CYGPATH_W) '$(srcdir)/m_libcsetjmp.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcsetjmp.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsetjmp.obj `if test -f 'm_libcsetjmp.c'; then $(CYGPATH_W) 'm_libcsetjmp.c'; else $(CYGPATH_W) '$(srcdir)/m_libcsetjmp.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.o: m_libcsignal.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.o `test -f 'm_libcsignal.c' || echo '$(srcdir)/'`m_libcsignal.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcsignal.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.o `test -f 'm_libcsignal.c' || echo '$(srcdir)/'`m_libcsignal.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.obj: m_libcsignal.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.obj `if test -f 'm_libcsignal.c'; then $(CYGPATH_W) 'm_libcsignal.c'; else $(CYGPATH_W) '$(srcdir)/m_libcsignal.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcsignal.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_libcsignal.obj `if test -f 'm_libcsignal.c'; then $(CYGPATH_W) 'm_libcsignal.c'; else $(CYGPATH_W) '$(srcdir)/m_libcsignal.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.o: m_machine.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.o `test -f 'm_machine.c' || echo '$(srcdir)/'`m_machine.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_machine.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.o `test -f 'm_machine.c' || echo '$(srcdir)/'`m_machine.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.obj: m_machine.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.obj `if test -f 'm_machine.c'; then $(CYGPATH_W) 'm_machine.c'; else $(CYGPATH_W) '$(srcdir)/m_machine.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_machine.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_machine.obj `if test -f 'm_machine.c'; then $(CYGPATH_W) 'm_machine.c'; else $(CYGPATH_W) '$(srcdir)/m_machine.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.o: m_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.o `test -f 'm_main.c' || echo '$(srcdir)/'`m_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_main.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.o `test -f 'm_main.c' || echo '$(srcdir)/'`m_main.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.obj: m_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.obj `if test -f 'm_main.c'; then $(CYGPATH_W) 'm_main.c'; else $(CYGPATH_W) '$(srcdir)/m_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_main.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_main.obj `if test -f 'm_main.c'; then $(CYGPATH_W) 'm_main.c'; else $(CYGPATH_W) '$(srcdir)/m_main.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.o: m_mallocfree.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.o `test -f 'm_mallocfree.c' || echo '$(srcdir)/'`m_mallocfree.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mallocfree.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.o `test -f 'm_mallocfree.c' || echo '$(srcdir)/'`m_mallocfree.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.obj: m_mallocfree.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.obj `if test -f 'm_mallocfree.c'; then $(CYGPATH_W) 'm_mallocfree.c'; else $(CYGPATH_W) '$(srcdir)/m_mallocfree.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mallocfree.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_mallocfree.obj `if test -f 'm_mallocfree.c'; then $(CYGPATH_W) 'm_mallocfree.c'; else $(CYGPATH_W) '$(srcdir)/m_mallocfree.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.o: m_options.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.o `test -f 'm_options.c' || echo '$(srcdir)/'`m_options.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_options.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.o `test -f 'm_options.c' || echo '$(srcdir)/'`m_options.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.obj: m_options.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.obj `if test -f 'm_options.c'; then $(CYGPATH_W) 'm_options.c'; else $(CYGPATH_W) '$(srcdir)/m_options.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_options.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_options.obj `if test -f 'm_options.c'; then $(CYGPATH_W) 'm_options.c'; else $(CYGPATH_W) '$(srcdir)/m_options.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.o: m_oset.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.o `test -f 'm_oset.c' || echo '$(srcdir)/'`m_oset.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_oset.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.o `test -f 'm_oset.c' || echo '$(srcdir)/'`m_oset.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.obj: m_oset.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.obj `if test -f 'm_oset.c'; then $(CYGPATH_W) 'm_oset.c'; else $(CYGPATH_W) '$(srcdir)/m_oset.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_oset.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_oset.obj `if test -f 'm_oset.c'; then $(CYGPATH_W) 'm_oset.c'; else $(CYGPATH_W) '$(srcdir)/m_oset.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.o: m_redir.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.o `test -f 'm_redir.c' || echo '$(srcdir)/'`m_redir.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_redir.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.o `test -f 'm_redir.c' || echo '$(srcdir)/'`m_redir.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.obj: m_redir.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.obj `if test -f 'm_redir.c'; then $(CYGPATH_W) 'm_redir.c'; else $(CYGPATH_W) '$(srcdir)/m_redir.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_redir.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_redir.obj `if test -f 'm_redir.c'; then $(CYGPATH_W) 'm_redir.c'; else $(CYGPATH_W) '$(srcdir)/m_redir.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.o: m_seqmatch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.o `test -f 'm_seqmatch.c' || echo '$(srcdir)/'`m_seqmatch.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_seqmatch.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.o `test -f 'm_seqmatch.c' || echo '$(srcdir)/'`m_seqmatch.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.obj: m_seqmatch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.obj `if test -f 'm_seqmatch.c'; then $(CYGPATH_W) 'm_seqmatch.c'; else $(CYGPATH_W) '$(srcdir)/m_seqmatch.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_seqmatch.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_seqmatch.obj `if test -f 'm_seqmatch.c'; then $(CYGPATH_W) 'm_seqmatch.c'; else $(CYGPATH_W) '$(srcdir)/m_seqmatch.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.o: m_signals.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.o `test -f 'm_signals.c' || echo '$(srcdir)/'`m_signals.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_signals.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.o `test -f 'm_signals.c' || echo '$(srcdir)/'`m_signals.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.obj: m_signals.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.obj `if test -f 'm_signals.c'; then $(CYGPATH_W) 'm_signals.c'; else $(CYGPATH_W) '$(srcdir)/m_signals.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_signals.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_signals.obj `if test -f 'm_signals.c'; then $(CYGPATH_W) 'm_signals.c'; else $(CYGPATH_W) '$(srcdir)/m_signals.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.o: m_sparsewa.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.o `test -f 'm_sparsewa.c' || echo '$(srcdir)/'`m_sparsewa.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sparsewa.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.o `test -f 'm_sparsewa.c' || echo '$(srcdir)/'`m_sparsewa.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.obj: m_sparsewa.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.obj `if test -f 'm_sparsewa.c'; then $(CYGPATH_W) 'm_sparsewa.c'; else $(CYGPATH_W) '$(srcdir)/m_sparsewa.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sparsewa.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.obj `if test -f 'm_sparsewa.c'; then $(CYGPATH_W) 'm_sparsewa.c'; else $(CYGPATH_W) '$(srcdir)/m_sparsewa.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.o: m_stacks.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.o `test -f 'm_stacks.c' || echo '$(srcdir)/'`m_stacks.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_stacks.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.o `test -f 'm_stacks.c' || echo '$(srcdir)/'`m_stacks.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.obj: m_stacks.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.obj `if test -f 'm_stacks.c'; then $(CYGPATH_W) 'm_stacks.c'; else $(CYGPATH_W) '$(srcdir)/m_stacks.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_stacks.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.obj `if test -f 'm_stacks.c'; then $(CYGPATH_W) 'm_stacks.c'; else $(CYGPATH_W) '$(srcdir)/m_stacks.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.o: m_stacktrace.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.o `test -f 'm_stacktrace.c' || echo '$(srcdir)/'`m_stacktrace.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_stacktrace.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.o `test -f 'm_stacktrace.c' || echo '$(srcdir)/'`m_stacktrace.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.obj: m_stacktrace.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.obj `if test -f 'm_stacktrace.c'; then $(CYGPATH_W) 'm_stacktrace.c'; else $(CYGPATH_W) '$(srcdir)/m_stacktrace.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_stacktrace.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.obj `if test -f 'm_stacktrace.c'; then $(CYGPATH_W) 'm_stacktrace.c'; else $(CYGPATH_W) '$(srcdir)/m_stacktrace.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.o: m_syscall.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.o `test -f 'm_syscall.c' || echo '$(srcdir)/'`m_syscall.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syscall.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.o `test -f 'm_syscall.c' || echo '$(srcdir)/'`m_syscall.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.obj: m_syscall.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.obj `if test -f 'm_syscall.c'; then $(CYGPATH_W) 'm_syscall.c'; else $(CYGPATH_W) '$(srcdir)/m_syscall.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syscall.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.obj `if test -f 'm_syscall.c'; then $(CYGPATH_W) 'm_syscall.c'; else $(CYGPATH_W) '$(srcdir)/m_syscall.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.o: m_threadstate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.o `test -f 'm_threadstate.c' || echo '$(srcdir)/'`m_threadstate.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_threadstate.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.o `test -f 'm_threadstate.c' || echo '$(srcdir)/'`m_threadstate.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.obj: m_threadstate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.obj `if test -f 'm_threadstate.c'; then $(CYGPATH_W) 'm_threadstate.c'; else $(CYGPATH_W) '$(srcdir)/m_threadstate.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_threadstate.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.obj `if test -f 'm_threadstate.c'; then $(CYGPATH_W) 'm_threadstate.c'; else $(CYGPATH_W) '$(srcdir)/m_threadstate.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.o: m_tooliface.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.o `test -f 'm_tooliface.c' || echo '$(srcdir)/'`m_tooliface.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_tooliface.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.o `test -f 'm_tooliface.c' || echo '$(srcdir)/'`m_tooliface.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.obj: m_tooliface.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.obj `if test -f 'm_tooliface.c'; then $(CYGPATH_W) 'm_tooliface.c'; else $(CYGPATH_W) '$(srcdir)/m_tooliface.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_tooliface.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.obj `if test -f 'm_tooliface.c'; then $(CYGPATH_W) 'm_tooliface.c'; else $(CYGPATH_W) '$(srcdir)/m_tooliface.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.o: m_translate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.o `test -f 'm_translate.c' || echo '$(srcdir)/'`m_translate.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_translate.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.o `test -f 'm_translate.c' || echo '$(srcdir)/'`m_translate.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.obj: m_translate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.obj `if test -f 'm_translate.c'; then $(CYGPATH_W) 'm_translate.c'; else $(CYGPATH_W) '$(srcdir)/m_translate.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_translate.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_translate.obj `if test -f 'm_translate.c'; then $(CYGPATH_W) 'm_translate.c'; else $(CYGPATH_W) '$(srcdir)/m_translate.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.o: m_transtab.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.o `test -f 'm_transtab.c' || echo '$(srcdir)/'`m_transtab.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_transtab.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.o `test -f 'm_transtab.c' || echo '$(srcdir)/'`m_transtab.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.obj: m_transtab.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.obj `if test -f 'm_transtab.c'; then $(CYGPATH_W) 'm_transtab.c'; else $(CYGPATH_W) '$(srcdir)/m_transtab.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_transtab.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_transtab.obj `if test -f 'm_transtab.c'; then $(CYGPATH_W) 'm_transtab.c'; else $(CYGPATH_W) '$(srcdir)/m_transtab.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.o: m_vki.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.o `test -f 'm_vki.c' || echo '$(srcdir)/'`m_vki.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_vki.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.o `test -f 'm_vki.c' || echo '$(srcdir)/'`m_vki.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.obj: m_vki.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.obj `if test -f 'm_vki.c'; then $(CYGPATH_W) 'm_vki.c'; else $(CYGPATH_W) '$(srcdir)/m_vki.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_vki.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vki.obj `if test -f 'm_vki.c'; then $(CYGPATH_W) 'm_vki.c'; else $(CYGPATH_W) '$(srcdir)/m_vki.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.o: m_vkiscnums.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.o `test -f 'm_vkiscnums.c' || echo '$(srcdir)/'`m_vkiscnums.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_vkiscnums.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.o `test -f 'm_vkiscnums.c' || echo '$(srcdir)/'`m_vkiscnums.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.obj: m_vkiscnums.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.obj `if test -f 'm_vkiscnums.c'; then $(CYGPATH_W) 'm_vkiscnums.c'; else $(CYGPATH_W) '$(srcdir)/m_vkiscnums.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_vkiscnums.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_vkiscnums.obj `if test -f 'm_vkiscnums.c'; then $(CYGPATH_W) 'm_vkiscnums.c'; else $(CYGPATH_W) '$(srcdir)/m_vkiscnums.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.o: m_wordfm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.o `test -f 'm_wordfm.c' || echo '$(srcdir)/'`m_wordfm.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_wordfm.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.o `test -f 'm_wordfm.c' || echo '$(srcdir)/'`m_wordfm.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.obj: m_wordfm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.obj `if test -f 'm_wordfm.c'; then $(CYGPATH_W) 'm_wordfm.c'; else $(CYGPATH_W) '$(srcdir)/m_wordfm.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_wordfm.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_wordfm.obj `if test -f 'm_wordfm.c'; then $(CYGPATH_W) 'm_wordfm.c'; else $(CYGPATH_W) '$(srcdir)/m_wordfm.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.o: m_xarray.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.o `test -f 'm_xarray.c' || echo '$(srcdir)/'`m_xarray.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_xarray.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.o `test -f 'm_xarray.c' || echo '$(srcdir)/'`m_xarray.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.obj: m_xarray.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.obj `if test -f 'm_xarray.c'; then $(CYGPATH_W) 'm_xarray.c'; else $(CYGPATH_W) '$(srcdir)/m_xarray.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_xarray.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_xarray.obj `if test -f 'm_xarray.c'; then $(CYGPATH_W) 'm_xarray.c'; else $(CYGPATH_W) '$(srcdir)/m_xarray.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.o: m_aspacehl.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.o `test -f 'm_aspacehl.c' || echo '$(srcdir)/'`m_aspacehl.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacehl.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.o `test -f 'm_aspacehl.c' || echo '$(srcdir)/'`m_aspacehl.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.obj: m_aspacehl.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.obj `if test -f 'm_aspacehl.c'; then $(CYGPATH_W) 'm_aspacehl.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacehl.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacehl.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_aspacehl.obj `if test -f 'm_aspacehl.c'; then $(CYGPATH_W) 'm_aspacehl.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacehl.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.o: m_aspacemgr/aspacemgr-common.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.o `test -f 'm_aspacemgr/aspacemgr-common.c' || echo '$(srcdir)/'`m_aspacemgr/aspacemgr-common.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacemgr/aspacemgr-common.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.o `test -f 'm_aspacemgr/aspacemgr-common.c' || echo '$(srcdir)/'`m_aspacemgr/aspacemgr-common.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.obj: m_aspacemgr/aspacemgr-common.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.obj `if test -f 'm_aspacemgr/aspacemgr-common.c'; then $(CYGPATH_W) 'm_aspacemgr/aspacemgr-common.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacemgr/aspacemgr-common.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacemgr/aspacemgr-common.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-common.obj `if test -f 'm_aspacemgr/aspacemgr-common.c'; then $(CYGPATH_W) 'm_aspacemgr/aspacemgr-common.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacemgr/aspacemgr-common.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.o: m_aspacemgr/aspacemgr-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.o `test -f 'm_aspacemgr/aspacemgr-linux.c' || echo '$(srcdir)/'`m_aspacemgr/aspacemgr-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacemgr/aspacemgr-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.o `test -f 'm_aspacemgr/aspacemgr-linux.c' || echo '$(srcdir)/'`m_aspacemgr/aspacemgr-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.obj: m_aspacemgr/aspacemgr-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.obj `if test -f 'm_aspacemgr/aspacemgr-linux.c'; then $(CYGPATH_W) 'm_aspacemgr/aspacemgr-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacemgr/aspacemgr-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacemgr/aspacemgr-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-aspacemgr-linux.obj `if test -f 'm_aspacemgr/aspacemgr-linux.c'; then $(CYGPATH_W) 'm_aspacemgr/aspacemgr-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacemgr/aspacemgr-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.o: m_coredump/coredump-elf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.o `test -f 'm_coredump/coredump-elf.c' || echo '$(srcdir)/'`m_coredump/coredump-elf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_coredump/coredump-elf.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.o `test -f 'm_coredump/coredump-elf.c' || echo '$(srcdir)/'`m_coredump/coredump-elf.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.obj: m_coredump/coredump-elf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.obj `if test -f 'm_coredump/coredump-elf.c'; then $(CYGPATH_W) 'm_coredump/coredump-elf.c'; else $(CYGPATH_W) '$(srcdir)/m_coredump/coredump-elf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_coredump/coredump-elf.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-elf.obj `if test -f 'm_coredump/coredump-elf.c'; then $(CYGPATH_W) 'm_coredump/coredump-elf.c'; else $(CYGPATH_W) '$(srcdir)/m_coredump/coredump-elf.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.o: m_coredump/coredump-macho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.o `test -f 'm_coredump/coredump-macho.c' || echo '$(srcdir)/'`m_coredump/coredump-macho.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_coredump/coredump-macho.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.o `test -f 'm_coredump/coredump-macho.c' || echo '$(srcdir)/'`m_coredump/coredump-macho.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.obj: m_coredump/coredump-macho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.obj `if test -f 'm_coredump/coredump-macho.c'; then $(CYGPATH_W) 'm_coredump/coredump-macho.c'; else $(CYGPATH_W) '$(srcdir)/m_coredump/coredump-macho.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_coredump/coredump-macho.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-coredump-macho.obj `if test -f 'm_coredump/coredump-macho.c'; then $(CYGPATH_W) 'm_coredump/coredump-macho.c'; else $(CYGPATH_W) '$(srcdir)/m_coredump/coredump-macho.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.o: m_debuginfo/misc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.o `test -f 'm_debuginfo/misc.c' || echo '$(srcdir)/'`m_debuginfo/misc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/misc.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.o `test -f 'm_debuginfo/misc.c' || echo '$(srcdir)/'`m_debuginfo/misc.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.obj: m_debuginfo/misc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.obj `if test -f 'm_debuginfo/misc.c'; then $(CYGPATH_W) 'm_debuginfo/misc.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/misc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/misc.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-misc.obj `if test -f 'm_debuginfo/misc.c'; then $(CYGPATH_W) 'm_debuginfo/misc.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/misc.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.o: m_debuginfo/d3basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.o `test -f 'm_debuginfo/d3basics.c' || echo '$(srcdir)/'`m_debuginfo/d3basics.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/d3basics.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.o `test -f 'm_debuginfo/d3basics.c' || echo '$(srcdir)/'`m_debuginfo/d3basics.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.obj: m_debuginfo/d3basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.obj `if test -f 'm_debuginfo/d3basics.c'; then $(CYGPATH_W) 'm_debuginfo/d3basics.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/d3basics.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/d3basics.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-d3basics.obj `if test -f 'm_debuginfo/d3basics.c'; then $(CYGPATH_W) 'm_debuginfo/d3basics.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/d3basics.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.o: m_debuginfo/debuginfo.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.o `test -f 'm_debuginfo/debuginfo.c' || echo '$(srcdir)/'`m_debuginfo/debuginfo.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/debuginfo.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.o `test -f 'm_debuginfo/debuginfo.c' || echo '$(srcdir)/'`m_debuginfo/debuginfo.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.obj: m_debuginfo/debuginfo.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.obj `if test -f 'm_debuginfo/debuginfo.c'; then $(CYGPATH_W) 'm_debuginfo/debuginfo.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/debuginfo.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/debuginfo.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-debuginfo.obj `if test -f 'm_debuginfo/debuginfo.c'; then $(CYGPATH_W) 'm_debuginfo/debuginfo.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/debuginfo.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.o: m_debuginfo/readdwarf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.o `test -f 'm_debuginfo/readdwarf.c' || echo '$(srcdir)/'`m_debuginfo/readdwarf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readdwarf.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.o `test -f 'm_debuginfo/readdwarf.c' || echo '$(srcdir)/'`m_debuginfo/readdwarf.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.obj: m_debuginfo/readdwarf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.obj `if test -f 'm_debuginfo/readdwarf.c'; then $(CYGPATH_W) 'm_debuginfo/readdwarf.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readdwarf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readdwarf.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf.obj `if test -f 'm_debuginfo/readdwarf.c'; then $(CYGPATH_W) 'm_debuginfo/readdwarf.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readdwarf.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.o: m_debuginfo/readdwarf3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.o `test -f 'm_debuginfo/readdwarf3.c' || echo '$(srcdir)/'`m_debuginfo/readdwarf3.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readdwarf3.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.o `test -f 'm_debuginfo/readdwarf3.c' || echo '$(srcdir)/'`m_debuginfo/readdwarf3.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.obj: m_debuginfo/readdwarf3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.obj `if test -f 'm_debuginfo/readdwarf3.c'; then $(CYGPATH_W) 'm_debuginfo/readdwarf3.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readdwarf3.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readdwarf3.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readdwarf3.obj `if test -f 'm_debuginfo/readdwarf3.c'; then $(CYGPATH_W) 'm_debuginfo/readdwarf3.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readdwarf3.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.o: m_debuginfo/readelf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.o `test -f 'm_debuginfo/readelf.c' || echo '$(srcdir)/'`m_debuginfo/readelf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readelf.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.o `test -f 'm_debuginfo/readelf.c' || echo '$(srcdir)/'`m_debuginfo/readelf.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.obj: m_debuginfo/readelf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.obj `if test -f 'm_debuginfo/readelf.c'; then $(CYGPATH_W) 'm_debuginfo/readelf.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readelf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readelf.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readelf.obj `if test -f 'm_debuginfo/readelf.c'; then $(CYGPATH_W) 'm_debuginfo/readelf.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readelf.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.o: m_debuginfo/readmacho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.o `test -f 'm_debuginfo/readmacho.c' || echo '$(srcdir)/'`m_debuginfo/readmacho.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readmacho.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.o `test -f 'm_debuginfo/readmacho.c' || echo '$(srcdir)/'`m_debuginfo/readmacho.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.obj: m_debuginfo/readmacho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.obj `if test -f 'm_debuginfo/readmacho.c'; then $(CYGPATH_W) 'm_debuginfo/readmacho.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readmacho.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readmacho.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readmacho.obj `if test -f 'm_debuginfo/readmacho.c'; then $(CYGPATH_W) 'm_debuginfo/readmacho.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readmacho.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.o: m_debuginfo/readpdb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.o `test -f 'm_debuginfo/readpdb.c' || echo '$(srcdir)/'`m_debuginfo/readpdb.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readpdb.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.o `test -f 'm_debuginfo/readpdb.c' || echo '$(srcdir)/'`m_debuginfo/readpdb.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.obj: m_debuginfo/readpdb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.obj `if test -f 'm_debuginfo/readpdb.c'; then $(CYGPATH_W) 'm_debuginfo/readpdb.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readpdb.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readpdb.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readpdb.obj `if test -f 'm_debuginfo/readpdb.c'; then $(CYGPATH_W) 'm_debuginfo/readpdb.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readpdb.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.o: m_debuginfo/readstabs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.o `test -f 'm_debuginfo/readstabs.c' || echo '$(srcdir)/'`m_debuginfo/readstabs.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readstabs.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.o `test -f 'm_debuginfo/readstabs.c' || echo '$(srcdir)/'`m_debuginfo/readstabs.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.obj: m_debuginfo/readstabs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.obj `if test -f 'm_debuginfo/readstabs.c'; then $(CYGPATH_W) 'm_debuginfo/readstabs.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readstabs.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readstabs.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-readstabs.obj `if test -f 'm_debuginfo/readstabs.c'; then $(CYGPATH_W) 'm_debuginfo/readstabs.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readstabs.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.o: m_debuginfo/storage.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.o `test -f 'm_debuginfo/storage.c' || echo '$(srcdir)/'`m_debuginfo/storage.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/storage.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.o `test -f 'm_debuginfo/storage.c' || echo '$(srcdir)/'`m_debuginfo/storage.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.obj: m_debuginfo/storage.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.obj `if test -f 'm_debuginfo/storage.c'; then $(CYGPATH_W) 'm_debuginfo/storage.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/storage.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/storage.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-storage.obj `if test -f 'm_debuginfo/storage.c'; then $(CYGPATH_W) 'm_debuginfo/storage.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/storage.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.o: m_debuginfo/tytypes.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.o `test -f 'm_debuginfo/tytypes.c' || echo '$(srcdir)/'`m_debuginfo/tytypes.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/tytypes.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.o `test -f 'm_debuginfo/tytypes.c' || echo '$(srcdir)/'`m_debuginfo/tytypes.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.obj: m_debuginfo/tytypes.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.obj `if test -f 'm_debuginfo/tytypes.c'; then $(CYGPATH_W) 'm_debuginfo/tytypes.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/tytypes.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/tytypes.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-tytypes.obj `if test -f 'm_debuginfo/tytypes.c'; then $(CYGPATH_W) 'm_debuginfo/tytypes.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/tytypes.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.o: m_demangle/cp-demangle.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.o `test -f 'm_demangle/cp-demangle.c' || echo '$(srcdir)/'`m_demangle/cp-demangle.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/cp-demangle.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.o `test -f 'm_demangle/cp-demangle.c' || echo '$(srcdir)/'`m_demangle/cp-demangle.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.obj: m_demangle/cp-demangle.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.obj `if test -f 'm_demangle/cp-demangle.c'; then $(CYGPATH_W) 'm_demangle/cp-demangle.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/cp-demangle.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/cp-demangle.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cp-demangle.obj `if test -f 'm_demangle/cp-demangle.c'; then $(CYGPATH_W) 'm_demangle/cp-demangle.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/cp-demangle.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.o: m_demangle/cplus-dem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.o `test -f 'm_demangle/cplus-dem.c' || echo '$(srcdir)/'`m_demangle/cplus-dem.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/cplus-dem.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.o `test -f 'm_demangle/cplus-dem.c' || echo '$(srcdir)/'`m_demangle/cplus-dem.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.obj: m_demangle/cplus-dem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.obj `if test -f 'm_demangle/cplus-dem.c'; then $(CYGPATH_W) 'm_demangle/cplus-dem.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/cplus-dem.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/cplus-dem.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-cplus-dem.obj `if test -f 'm_demangle/cplus-dem.c'; then $(CYGPATH_W) 'm_demangle/cplus-dem.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/cplus-dem.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.o: m_demangle/demangle.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.o `test -f 'm_demangle/demangle.c' || echo '$(srcdir)/'`m_demangle/demangle.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/demangle.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.o `test -f 'm_demangle/demangle.c' || echo '$(srcdir)/'`m_demangle/demangle.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.obj: m_demangle/demangle.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.obj `if test -f 'm_demangle/demangle.c'; then $(CYGPATH_W) 'm_demangle/demangle.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/demangle.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/demangle.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-demangle.obj `if test -f 'm_demangle/demangle.c'; then $(CYGPATH_W) 'm_demangle/demangle.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/demangle.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.o: m_demangle/dyn-string.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.o `test -f 'm_demangle/dyn-string.c' || echo '$(srcdir)/'`m_demangle/dyn-string.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/dyn-string.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.o `test -f 'm_demangle/dyn-string.c' || echo '$(srcdir)/'`m_demangle/dyn-string.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.obj: m_demangle/dyn-string.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.obj `if test -f 'm_demangle/dyn-string.c'; then $(CYGPATH_W) 'm_demangle/dyn-string.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/dyn-string.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/dyn-string.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-dyn-string.obj `if test -f 'm_demangle/dyn-string.c'; then $(CYGPATH_W) 'm_demangle/dyn-string.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/dyn-string.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.o: m_demangle/safe-ctype.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.o `test -f 'm_demangle/safe-ctype.c' || echo '$(srcdir)/'`m_demangle/safe-ctype.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/safe-ctype.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.o `test -f 'm_demangle/safe-ctype.c' || echo '$(srcdir)/'`m_demangle/safe-ctype.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.obj: m_demangle/safe-ctype.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.obj `if test -f 'm_demangle/safe-ctype.c'; then $(CYGPATH_W) 'm_demangle/safe-ctype.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/safe-ctype.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/safe-ctype.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-safe-ctype.obj `if test -f 'm_demangle/safe-ctype.c'; then $(CYGPATH_W) 'm_demangle/safe-ctype.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/safe-ctype.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.o: m_gdbserver/inferiors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.o `test -f 'm_gdbserver/inferiors.c' || echo '$(srcdir)/'`m_gdbserver/inferiors.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/inferiors.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.o `test -f 'm_gdbserver/inferiors.c' || echo '$(srcdir)/'`m_gdbserver/inferiors.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.obj: m_gdbserver/inferiors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.obj `if test -f 'm_gdbserver/inferiors.c'; then $(CYGPATH_W) 'm_gdbserver/inferiors.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/inferiors.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/inferiors.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-inferiors.obj `if test -f 'm_gdbserver/inferiors.c'; then $(CYGPATH_W) 'm_gdbserver/inferiors.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/inferiors.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.o: m_gdbserver/m_gdbserver.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.o `test -f 'm_gdbserver/m_gdbserver.c' || echo '$(srcdir)/'`m_gdbserver/m_gdbserver.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/m_gdbserver.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.o `test -f 'm_gdbserver/m_gdbserver.c' || echo '$(srcdir)/'`m_gdbserver/m_gdbserver.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.obj: m_gdbserver/m_gdbserver.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.obj `if test -f 'm_gdbserver/m_gdbserver.c'; then $(CYGPATH_W) 'm_gdbserver/m_gdbserver.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/m_gdbserver.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/m_gdbserver.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_gdbserver.obj `if test -f 'm_gdbserver/m_gdbserver.c'; then $(CYGPATH_W) 'm_gdbserver/m_gdbserver.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/m_gdbserver.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.o: m_gdbserver/regcache.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.o `test -f 'm_gdbserver/regcache.c' || echo '$(srcdir)/'`m_gdbserver/regcache.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/regcache.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.o `test -f 'm_gdbserver/regcache.c' || echo '$(srcdir)/'`m_gdbserver/regcache.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.obj: m_gdbserver/regcache.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.obj `if test -f 'm_gdbserver/regcache.c'; then $(CYGPATH_W) 'm_gdbserver/regcache.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/regcache.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/regcache.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-regcache.obj `if test -f 'm_gdbserver/regcache.c'; then $(CYGPATH_W) 'm_gdbserver/regcache.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/regcache.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.o: m_gdbserver/remote-utils.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.o `test -f 'm_gdbserver/remote-utils.c' || echo '$(srcdir)/'`m_gdbserver/remote-utils.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/remote-utils.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.o `test -f 'm_gdbserver/remote-utils.c' || echo '$(srcdir)/'`m_gdbserver/remote-utils.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.obj: m_gdbserver/remote-utils.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.obj `if test -f 'm_gdbserver/remote-utils.c'; then $(CYGPATH_W) 'm_gdbserver/remote-utils.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/remote-utils.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/remote-utils.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-remote-utils.obj `if test -f 'm_gdbserver/remote-utils.c'; then $(CYGPATH_W) 'm_gdbserver/remote-utils.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/remote-utils.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.o: m_gdbserver/server.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.o `test -f 'm_gdbserver/server.c' || echo '$(srcdir)/'`m_gdbserver/server.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/server.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.o `test -f 'm_gdbserver/server.c' || echo '$(srcdir)/'`m_gdbserver/server.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.obj: m_gdbserver/server.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.obj `if test -f 'm_gdbserver/server.c'; then $(CYGPATH_W) 'm_gdbserver/server.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/server.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/server.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-server.obj `if test -f 'm_gdbserver/server.c'; then $(CYGPATH_W) 'm_gdbserver/server.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/server.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.o: m_gdbserver/signals.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.o `test -f 'm_gdbserver/signals.c' || echo '$(srcdir)/'`m_gdbserver/signals.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/signals.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.o `test -f 'm_gdbserver/signals.c' || echo '$(srcdir)/'`m_gdbserver/signals.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.obj: m_gdbserver/signals.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.obj `if test -f 'm_gdbserver/signals.c'; then $(CYGPATH_W) 'm_gdbserver/signals.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/signals.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/signals.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-signals.obj `if test -f 'm_gdbserver/signals.c'; then $(CYGPATH_W) 'm_gdbserver/signals.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/signals.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.o: m_gdbserver/target.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.o `test -f 'm_gdbserver/target.c' || echo '$(srcdir)/'`m_gdbserver/target.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/target.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.o `test -f 'm_gdbserver/target.c' || echo '$(srcdir)/'`m_gdbserver/target.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.obj: m_gdbserver/target.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.obj `if test -f 'm_gdbserver/target.c'; then $(CYGPATH_W) 'm_gdbserver/target.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/target.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/target.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-target.obj `if test -f 'm_gdbserver/target.c'; then $(CYGPATH_W) 'm_gdbserver/target.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/target.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.o: m_gdbserver/utils.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.o `test -f 'm_gdbserver/utils.c' || echo '$(srcdir)/'`m_gdbserver/utils.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/utils.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.o `test -f 'm_gdbserver/utils.c' || echo '$(srcdir)/'`m_gdbserver/utils.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.obj: m_gdbserver/utils.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.obj `if test -f 'm_gdbserver/utils.c'; then $(CYGPATH_W) 'm_gdbserver/utils.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/utils.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/utils.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-utils.obj `if test -f 'm_gdbserver/utils.c'; then $(CYGPATH_W) 'm_gdbserver/utils.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/utils.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.o: m_gdbserver/valgrind-low-x86.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.o `test -f 'm_gdbserver/valgrind-low-x86.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-x86.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-x86.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.o `test -f 'm_gdbserver/valgrind-low-x86.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-x86.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.obj: m_gdbserver/valgrind-low-x86.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.obj `if test -f 'm_gdbserver/valgrind-low-x86.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-x86.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-x86.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-x86.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-x86.obj `if test -f 'm_gdbserver/valgrind-low-x86.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-x86.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-x86.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.o: m_gdbserver/valgrind-low-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.o `test -f 'm_gdbserver/valgrind-low-amd64.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-amd64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-amd64.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.o `test -f 'm_gdbserver/valgrind-low-amd64.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-amd64.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.obj: m_gdbserver/valgrind-low-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.obj `if test -f 'm_gdbserver/valgrind-low-amd64.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-amd64.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-amd64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-amd64.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-amd64.obj `if test -f 'm_gdbserver/valgrind-low-amd64.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-amd64.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-amd64.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.o: m_gdbserver/valgrind-low-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.o `test -f 'm_gdbserver/valgrind-low-arm.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-arm.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-arm.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.o `test -f 'm_gdbserver/valgrind-low-arm.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-arm.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.obj: m_gdbserver/valgrind-low-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.obj `if test -f 'm_gdbserver/valgrind-low-arm.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-arm.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-arm.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-arm.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-arm.obj `if test -f 'm_gdbserver/valgrind-low-arm.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-arm.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-arm.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.o: m_gdbserver/valgrind-low-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.o `test -f 'm_gdbserver/valgrind-low-ppc32.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-ppc32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-ppc32.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.o `test -f 'm_gdbserver/valgrind-low-ppc32.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-ppc32.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.obj: m_gdbserver/valgrind-low-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.obj `if test -f 'm_gdbserver/valgrind-low-ppc32.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-ppc32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-ppc32.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc32.obj `if test -f 'm_gdbserver/valgrind-low-ppc32.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-ppc32.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.o: m_gdbserver/valgrind-low-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.o `test -f 'm_gdbserver/valgrind-low-ppc64.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-ppc64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-ppc64.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.o `test -f 'm_gdbserver/valgrind-low-ppc64.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-ppc64.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.obj: m_gdbserver/valgrind-low-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.obj `if test -f 'm_gdbserver/valgrind-low-ppc64.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-ppc64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-ppc64.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-ppc64.obj `if test -f 'm_gdbserver/valgrind-low-ppc64.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-ppc64.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.o: m_gdbserver/valgrind-low-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.o `test -f 'm_gdbserver/valgrind-low-s390x.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-s390x.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-s390x.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.o `test -f 'm_gdbserver/valgrind-low-s390x.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-s390x.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.obj: m_gdbserver/valgrind-low-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.obj `if test -f 'm_gdbserver/valgrind-low-s390x.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-s390x.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-s390x.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-s390x.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-s390x.obj `if test -f 'm_gdbserver/valgrind-low-s390x.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-s390x.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-s390x.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.o: m_gdbserver/valgrind-low-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.o `test -f 'm_gdbserver/valgrind-low-mips32.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-mips32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-mips32.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.o `test -f 'm_gdbserver/valgrind-low-mips32.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-mips32.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.obj: m_gdbserver/valgrind-low-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.obj `if test -f 'm_gdbserver/valgrind-low-mips32.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-mips32.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-mips32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-mips32.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-valgrind-low-mips32.obj `if test -f 'm_gdbserver/valgrind-low-mips32.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-mips32.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-mips32.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.o: m_gdbserver/version.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.o `test -f 'm_gdbserver/version.c' || echo '$(srcdir)/'`m_gdbserver/version.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/version.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.o `test -f 'm_gdbserver/version.c' || echo '$(srcdir)/'`m_gdbserver/version.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.obj: m_gdbserver/version.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.obj `if test -f 'm_gdbserver/version.c'; then $(CYGPATH_W) 'm_gdbserver/version.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/version.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/version.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-version.obj `if test -f 'm_gdbserver/version.c'; then $(CYGPATH_W) 'm_gdbserver/version.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/version.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.o: m_initimg/initimg-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.o `test -f 'm_initimg/initimg-linux.c' || echo '$(srcdir)/'`m_initimg/initimg-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.o `test -f 'm_initimg/initimg-linux.c' || echo '$(srcdir)/'`m_initimg/initimg-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.obj: m_initimg/initimg-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.obj `if test -f 'm_initimg/initimg-linux.c'; then $(CYGPATH_W) 'm_initimg/initimg-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-linux.obj `if test -f 'm_initimg/initimg-linux.c'; then $(CYGPATH_W) 'm_initimg/initimg-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.o: m_initimg/initimg-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.o `test -f 'm_initimg/initimg-darwin.c' || echo '$(srcdir)/'`m_initimg/initimg-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.o `test -f 'm_initimg/initimg-darwin.c' || echo '$(srcdir)/'`m_initimg/initimg-darwin.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.obj: m_initimg/initimg-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.obj `if test -f 'm_initimg/initimg-darwin.c'; then $(CYGPATH_W) 'm_initimg/initimg-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-darwin.obj `if test -f 'm_initimg/initimg-darwin.c'; then $(CYGPATH_W) 'm_initimg/initimg-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.o: m_initimg/initimg-pathscan.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.o `test -f 'm_initimg/initimg-pathscan.c' || echo '$(srcdir)/'`m_initimg/initimg-pathscan.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-pathscan.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.o `test -f 'm_initimg/initimg-pathscan.c' || echo '$(srcdir)/'`m_initimg/initimg-pathscan.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.obj: m_initimg/initimg-pathscan.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.obj `if test -f 'm_initimg/initimg-pathscan.c'; then $(CYGPATH_W) 'm_initimg/initimg-pathscan.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-pathscan.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-pathscan.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-initimg-pathscan.obj `if test -f 'm_initimg/initimg-pathscan.c'; then $(CYGPATH_W) 'm_initimg/initimg-pathscan.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-pathscan.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.o: m_mach/mach_basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.o `test -f 'm_mach/mach_basics.c' || echo '$(srcdir)/'`m_mach/mach_basics.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_basics.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.o `test -f 'm_mach/mach_basics.c' || echo '$(srcdir)/'`m_mach/mach_basics.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.obj: m_mach/mach_basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.obj `if test -f 'm_mach/mach_basics.c'; then $(CYGPATH_W) 'm_mach/mach_basics.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_basics.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_basics.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_basics.obj `if test -f 'm_mach/mach_basics.c'; then $(CYGPATH_W) 'm_mach/mach_basics.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_basics.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.o: m_mach/mach_msg.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.o `test -f 'm_mach/mach_msg.c' || echo '$(srcdir)/'`m_mach/mach_msg.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_msg.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.o `test -f 'm_mach/mach_msg.c' || echo '$(srcdir)/'`m_mach/mach_msg.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.obj: m_mach/mach_msg.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.obj `if test -f 'm_mach/mach_msg.c'; then $(CYGPATH_W) 'm_mach/mach_msg.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_msg.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_msg.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_msg.obj `if test -f 'm_mach/mach_msg.c'; then $(CYGPATH_W) 'm_mach/mach_msg.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_msg.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.o: m_replacemalloc/replacemalloc_core.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.o `test -f 'm_replacemalloc/replacemalloc_core.c' || echo '$(srcdir)/'`m_replacemalloc/replacemalloc_core.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_replacemalloc/replacemalloc_core.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.o `test -f 'm_replacemalloc/replacemalloc_core.c' || echo '$(srcdir)/'`m_replacemalloc/replacemalloc_core.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.obj: m_replacemalloc/replacemalloc_core.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.obj `if test -f 'm_replacemalloc/replacemalloc_core.c'; then $(CYGPATH_W) 'm_replacemalloc/replacemalloc_core.c'; else $(CYGPATH_W) '$(srcdir)/m_replacemalloc/replacemalloc_core.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_replacemalloc/replacemalloc_core.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-replacemalloc_core.obj `if test -f 'm_replacemalloc/replacemalloc_core.c'; then $(CYGPATH_W) 'm_replacemalloc/replacemalloc_core.c'; else $(CYGPATH_W) '$(srcdir)/m_replacemalloc/replacemalloc_core.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.o: m_scheduler/scheduler.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.o `test -f 'm_scheduler/scheduler.c' || echo '$(srcdir)/'`m_scheduler/scheduler.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/scheduler.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.o `test -f 'm_scheduler/scheduler.c' || echo '$(srcdir)/'`m_scheduler/scheduler.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.obj: m_scheduler/scheduler.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.obj `if test -f 'm_scheduler/scheduler.c'; then $(CYGPATH_W) 'm_scheduler/scheduler.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/scheduler.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/scheduler.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-scheduler.obj `if test -f 'm_scheduler/scheduler.c'; then $(CYGPATH_W) 'm_scheduler/scheduler.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/scheduler.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.o: m_scheduler/sema.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.o `test -f 'm_scheduler/sema.c' || echo '$(srcdir)/'`m_scheduler/sema.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sema.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.o `test -f 'm_scheduler/sema.c' || echo '$(srcdir)/'`m_scheduler/sema.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.obj: m_scheduler/sema.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.obj `if test -f 'm_scheduler/sema.c'; then $(CYGPATH_W) 'm_scheduler/sema.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sema.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sema.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sema.obj `if test -f 'm_scheduler/sema.c'; then $(CYGPATH_W) 'm_scheduler/sema.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sema.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.o: m_scheduler/sched-lock.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.o `test -f 'm_scheduler/sched-lock.c' || echo '$(srcdir)/'`m_scheduler/sched-lock.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sched-lock.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.o `test -f 'm_scheduler/sched-lock.c' || echo '$(srcdir)/'`m_scheduler/sched-lock.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.obj: m_scheduler/sched-lock.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.obj `if test -f 'm_scheduler/sched-lock.c'; then $(CYGPATH_W) 'm_scheduler/sched-lock.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sched-lock.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sched-lock.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock.obj `if test -f 'm_scheduler/sched-lock.c'; then $(CYGPATH_W) 'm_scheduler/sched-lock.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sched-lock.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.o: m_scheduler/sched-lock-generic.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.o `test -f 'm_scheduler/sched-lock-generic.c' || echo '$(srcdir)/'`m_scheduler/sched-lock-generic.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sched-lock-generic.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.o `test -f 'm_scheduler/sched-lock-generic.c' || echo '$(srcdir)/'`m_scheduler/sched-lock-generic.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.obj: m_scheduler/sched-lock-generic.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.obj `if test -f 'm_scheduler/sched-lock-generic.c'; then $(CYGPATH_W) 'm_scheduler/sched-lock-generic.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sched-lock-generic.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sched-lock-generic.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sched-lock-generic.obj `if test -f 'm_scheduler/sched-lock-generic.c'; then $(CYGPATH_W) 'm_scheduler/sched-lock-generic.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sched-lock-generic.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.o: m_sigframe/sigframe-x86-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.o `test -f 'm_sigframe/sigframe-x86-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-x86-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-x86-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.o `test -f 'm_sigframe/sigframe-x86-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-x86-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.obj: m_sigframe/sigframe-x86-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.obj `if test -f 'm_sigframe/sigframe-x86-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-x86-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-x86-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-x86-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-linux.obj `if test -f 'm_sigframe/sigframe-x86-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-x86-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-x86-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.o: m_sigframe/sigframe-amd64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.o `test -f 'm_sigframe/sigframe-amd64-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-amd64-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-amd64-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.o `test -f 'm_sigframe/sigframe-amd64-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-amd64-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.obj: m_sigframe/sigframe-amd64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.obj `if test -f 'm_sigframe/sigframe-amd64-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-amd64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-amd64-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-amd64-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-linux.obj `if test -f 'm_sigframe/sigframe-amd64-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-amd64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-amd64-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.o: m_sigframe/sigframe-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.o `test -f 'm_sigframe/sigframe-ppc32-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-ppc32-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.o `test -f 'm_sigframe/sigframe-ppc32-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-ppc32-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj: m_sigframe/sigframe-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj `if test -f 'm_sigframe/sigframe-ppc32-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-ppc32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-ppc32-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-ppc32-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj `if test -f 'm_sigframe/sigframe-ppc32-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-ppc32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-ppc32-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.o: m_sigframe/sigframe-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.o `test -f 'm_sigframe/sigframe-ppc64-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-ppc64-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.o `test -f 'm_sigframe/sigframe-ppc64-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-ppc64-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj: m_sigframe/sigframe-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj `if test -f 'm_sigframe/sigframe-ppc64-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-ppc64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-ppc64-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-ppc64-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj `if test -f 'm_sigframe/sigframe-ppc64-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-ppc64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-ppc64-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.o: m_sigframe/sigframe-arm-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.o `test -f 'm_sigframe/sigframe-arm-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-arm-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-arm-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.o `test -f 'm_sigframe/sigframe-arm-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-arm-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.obj: m_sigframe/sigframe-arm-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.obj `if test -f 'm_sigframe/sigframe-arm-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-arm-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-arm-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-arm-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-arm-linux.obj `if test -f 'm_sigframe/sigframe-arm-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-arm-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-arm-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.o: m_sigframe/sigframe-s390x-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.o `test -f 'm_sigframe/sigframe-s390x-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-s390x-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-s390x-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.o `test -f 'm_sigframe/sigframe-s390x-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-s390x-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.obj: m_sigframe/sigframe-s390x-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.obj `if test -f 'm_sigframe/sigframe-s390x-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-s390x-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-s390x-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-s390x-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-s390x-linux.obj `if test -f 'm_sigframe/sigframe-s390x-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-s390x-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-s390x-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.o: m_sigframe/sigframe-mips32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.o `test -f 'm_sigframe/sigframe-mips32-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-mips32-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-mips32-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.o `test -f 'm_sigframe/sigframe-mips32-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-mips32-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.obj: m_sigframe/sigframe-mips32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.obj `if test -f 'm_sigframe/sigframe-mips32-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-mips32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-mips32-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-mips32-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-mips32-linux.obj `if test -f 'm_sigframe/sigframe-mips32-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-mips32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-mips32-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.o: m_sigframe/sigframe-x86-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.o `test -f 'm_sigframe/sigframe-x86-darwin.c' || echo '$(srcdir)/'`m_sigframe/sigframe-x86-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-x86-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.o `test -f 'm_sigframe/sigframe-x86-darwin.c' || echo '$(srcdir)/'`m_sigframe/sigframe-x86-darwin.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.obj: m_sigframe/sigframe-x86-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.obj `if test -f 'm_sigframe/sigframe-x86-darwin.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-x86-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-x86-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-x86-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.obj `if test -f 'm_sigframe/sigframe-x86-darwin.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-x86-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-x86-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.o: m_sigframe/sigframe-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.o `test -f 'm_sigframe/sigframe-amd64-darwin.c' || echo '$(srcdir)/'`m_sigframe/sigframe-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-amd64-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.o `test -f 'm_sigframe/sigframe-amd64-darwin.c' || echo '$(srcdir)/'`m_sigframe/sigframe-amd64-darwin.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj: m_sigframe/sigframe-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj `if test -f 'm_sigframe/sigframe-amd64-darwin.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-amd64-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-amd64-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-amd64-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj `if test -f 'm_sigframe/sigframe-amd64-darwin.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-amd64-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-amd64-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.o: m_syswrap/syswrap-main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.o `test -f 'm_syswrap/syswrap-main.c' || echo '$(srcdir)/'`m_syswrap/syswrap-main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-main.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.o `test -f 'm_syswrap/syswrap-main.c' || echo '$(srcdir)/'`m_syswrap/syswrap-main.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.obj: m_syswrap/syswrap-main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.obj `if test -f 'm_syswrap/syswrap-main.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-main.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-main.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-main.obj `if test -f 'm_syswrap/syswrap-main.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-main.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-main.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.o: m_syswrap/syswrap-generic.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.o `test -f 'm_syswrap/syswrap-generic.c' || echo '$(srcdir)/'`m_syswrap/syswrap-generic.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-generic.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.o `test -f 'm_syswrap/syswrap-generic.c' || echo '$(srcdir)/'`m_syswrap/syswrap-generic.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.obj: m_syswrap/syswrap-generic.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.obj `if test -f 'm_syswrap/syswrap-generic.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-generic.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-generic.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-generic.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-generic.obj `if test -f 'm_syswrap/syswrap-generic.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-generic.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-generic.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.o: m_syswrap/syswrap-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.o `test -f 'm_syswrap/syswrap-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.o `test -f 'm_syswrap/syswrap-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.obj: m_syswrap/syswrap-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.obj `if test -f 'm_syswrap/syswrap-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux.obj `if test -f 'm_syswrap/syswrap-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.o: m_syswrap/syswrap-linux-variants.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.o `test -f 'm_syswrap/syswrap-linux-variants.c' || echo '$(srcdir)/'`m_syswrap/syswrap-linux-variants.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-linux-variants.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.o `test -f 'm_syswrap/syswrap-linux-variants.c' || echo '$(srcdir)/'`m_syswrap/syswrap-linux-variants.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.obj: m_syswrap/syswrap-linux-variants.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.obj `if test -f 'm_syswrap/syswrap-linux-variants.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-linux-variants.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-linux-variants.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-linux-variants.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-linux-variants.obj `if test -f 'm_syswrap/syswrap-linux-variants.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-linux-variants.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-linux-variants.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.o: m_syswrap/syswrap-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.o `test -f 'm_syswrap/syswrap-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.o `test -f 'm_syswrap/syswrap-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-darwin.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.obj: m_syswrap/syswrap-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.obj `if test -f 'm_syswrap/syswrap-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-darwin.obj `if test -f 'm_syswrap/syswrap-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.o: m_syswrap/syswrap-x86-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.o `test -f 'm_syswrap/syswrap-x86-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-x86-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.o `test -f 'm_syswrap/syswrap-x86-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.obj: m_syswrap/syswrap-x86-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.obj `if test -f 'm_syswrap/syswrap-x86-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-x86-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-x86-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-x86-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-linux.obj `if test -f 'm_syswrap/syswrap-x86-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-x86-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-x86-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.o: m_syswrap/syswrap-amd64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.o `test -f 'm_syswrap/syswrap-amd64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-amd64-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-amd64-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.o `test -f 'm_syswrap/syswrap-amd64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-amd64-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.obj: m_syswrap/syswrap-amd64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.obj `if test -f 'm_syswrap/syswrap-amd64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-amd64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-amd64-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-amd64-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-linux.obj `if test -f 'm_syswrap/syswrap-amd64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-amd64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-amd64-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.o: m_syswrap/syswrap-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.o `test -f 'm_syswrap/syswrap-ppc32-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-ppc32-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.o `test -f 'm_syswrap/syswrap-ppc32-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-ppc32-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj: m_syswrap/syswrap-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj `if test -f 'm_syswrap/syswrap-ppc32-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-ppc32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-ppc32-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-ppc32-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj `if test -f 'm_syswrap/syswrap-ppc32-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-ppc32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-ppc32-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.o: m_syswrap/syswrap-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.o `test -f 'm_syswrap/syswrap-ppc64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-ppc64-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.o `test -f 'm_syswrap/syswrap-ppc64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-ppc64-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj: m_syswrap/syswrap-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj `if test -f 'm_syswrap/syswrap-ppc64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-ppc64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-ppc64-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-ppc64-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj `if test -f 'm_syswrap/syswrap-ppc64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-ppc64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-ppc64-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.o: m_syswrap/syswrap-arm-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.o `test -f 'm_syswrap/syswrap-arm-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-arm-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-arm-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.o `test -f 'm_syswrap/syswrap-arm-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-arm-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.obj: m_syswrap/syswrap-arm-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.obj `if test -f 'm_syswrap/syswrap-arm-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-arm-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-arm-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-arm-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-arm-linux.obj `if test -f 'm_syswrap/syswrap-arm-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-arm-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-arm-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.o: m_syswrap/syswrap-s390x-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.o `test -f 'm_syswrap/syswrap-s390x-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-s390x-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-s390x-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.o `test -f 'm_syswrap/syswrap-s390x-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-s390x-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.obj: m_syswrap/syswrap-s390x-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.obj `if test -f 'm_syswrap/syswrap-s390x-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-s390x-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-s390x-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-s390x-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-s390x-linux.obj `if test -f 'm_syswrap/syswrap-s390x-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-s390x-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-s390x-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.o: m_syswrap/syswrap-mips32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.o `test -f 'm_syswrap/syswrap-mips32-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-mips32-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-mips32-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.o `test -f 'm_syswrap/syswrap-mips32-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-mips32-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.obj: m_syswrap/syswrap-mips32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.obj `if test -f 'm_syswrap/syswrap-mips32-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-mips32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-mips32-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-mips32-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-mips32-linux.obj `if test -f 'm_syswrap/syswrap-mips32-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-mips32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-mips32-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.o: m_syswrap/syswrap-x86-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.o `test -f 'm_syswrap/syswrap-x86-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-x86-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.o `test -f 'm_syswrap/syswrap-x86-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-darwin.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.obj: m_syswrap/syswrap-x86-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.obj `if test -f 'm_syswrap/syswrap-x86-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-x86-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-x86-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-x86-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-x86-darwin.obj `if test -f 'm_syswrap/syswrap-x86-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-x86-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-x86-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.o: m_syswrap/syswrap-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.o `test -f 'm_syswrap/syswrap-amd64-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-amd64-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.o `test -f 'm_syswrap/syswrap-amd64-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-amd64-darwin.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj: m_syswrap/syswrap-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj `if test -f 'm_syswrap/syswrap-amd64-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-amd64-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-amd64-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-amd64-darwin.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj `if test -f 'm_syswrap/syswrap-amd64-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-amd64-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-amd64-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.o: m_ume/elf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.o `test -f 'm_ume/elf.c' || echo '$(srcdir)/'`m_ume/elf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/elf.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.o `test -f 'm_ume/elf.c' || echo '$(srcdir)/'`m_ume/elf.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.obj: m_ume/elf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.obj `if test -f 'm_ume/elf.c'; then $(CYGPATH_W) 'm_ume/elf.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/elf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/elf.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-elf.obj `if test -f 'm_ume/elf.c'; then $(CYGPATH_W) 'm_ume/elf.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/elf.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.o: m_ume/macho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.o `test -f 'm_ume/macho.c' || echo '$(srcdir)/'`m_ume/macho.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/macho.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.o `test -f 'm_ume/macho.c' || echo '$(srcdir)/'`m_ume/macho.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.obj: m_ume/macho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.obj `if test -f 'm_ume/macho.c'; then $(CYGPATH_W) 'm_ume/macho.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/macho.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/macho.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-macho.obj `if test -f 'm_ume/macho.c'; then $(CYGPATH_W) 'm_ume/macho.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/macho.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.o: m_ume/main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.o `test -f 'm_ume/main.c' || echo '$(srcdir)/'`m_ume/main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/main.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.o `test -f 'm_ume/main.c' || echo '$(srcdir)/'`m_ume/main.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.obj: m_ume/main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.obj `if test -f 'm_ume/main.c'; then $(CYGPATH_W) 'm_ume/main.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/main.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-main.obj `if test -f 'm_ume/main.c'; then $(CYGPATH_W) 'm_ume/main.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/main.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.o: m_ume/script.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.o `test -f 'm_ume/script.c' || echo '$(srcdir)/'`m_ume/script.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/script.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.o `test -f 'm_ume/script.c' || echo '$(srcdir)/'`m_ume/script.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.obj: m_ume/script.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.obj `if test -f 'm_ume/script.c'; then $(CYGPATH_W) 'm_ume/script.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/script.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/script.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-script.obj `if test -f 'm_ume/script.c'; then $(CYGPATH_W) 'm_ume/script.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/script.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.o: m_scheduler/ticket-lock-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.o `test -f 'm_scheduler/ticket-lock-linux.c' || echo '$(srcdir)/'`m_scheduler/ticket-lock-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/ticket-lock-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.o `test -f 'm_scheduler/ticket-lock-linux.c' || echo '$(srcdir)/'`m_scheduler/ticket-lock-linux.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.obj: m_scheduler/ticket-lock-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.obj `if test -f 'm_scheduler/ticket-lock-linux.c'; then $(CYGPATH_W) 'm_scheduler/ticket-lock-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/ticket-lock-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/ticket-lock-linux.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-ticket-lock-linux.obj `if test -f 'm_scheduler/ticket-lock-linux.c'; then $(CYGPATH_W) 'm_scheduler/ticket-lock-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/ticket-lock-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.o: m_mach/mach_vmUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.o `test -f 'm_mach/mach_vmUser.c' || echo '$(srcdir)/'`m_mach/mach_vmUser.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_vmUser.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.o `test -f 'm_mach/mach_vmUser.c' || echo '$(srcdir)/'`m_mach/mach_vmUser.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.obj: m_mach/mach_vmUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.obj `if test -f 'm_mach/mach_vmUser.c'; then $(CYGPATH_W) 'm_mach/mach_vmUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_vmUser.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_vmUser.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_vmUser.obj `if test -f 'm_mach/mach_vmUser.c'; then $(CYGPATH_W) 'm_mach/mach_vmUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_vmUser.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.o: m_mach/taskUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.o `test -f 'm_mach/taskUser.c' || echo '$(srcdir)/'`m_mach/taskUser.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/taskUser.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.o `test -f 'm_mach/taskUser.c' || echo '$(srcdir)/'`m_mach/taskUser.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.obj: m_mach/taskUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.obj `if test -f 'm_mach/taskUser.c'; then $(CYGPATH_W) 'm_mach/taskUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/taskUser.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/taskUser.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-taskUser.obj `if test -f 'm_mach/taskUser.c'; then $(CYGPATH_W) 'm_mach/taskUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/taskUser.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.o: m_mach/thread_actUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.o `test -f 'm_mach/thread_actUser.c' || echo '$(srcdir)/'`m_mach/thread_actUser.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/thread_actUser.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.o `test -f 'm_mach/thread_actUser.c' || echo '$(srcdir)/'`m_mach/thread_actUser.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.obj: m_mach/thread_actUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.obj `if test -f 'm_mach/thread_actUser.c'; then $(CYGPATH_W) 'm_mach/thread_actUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/thread_actUser.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/thread_actUser.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-thread_actUser.obj `if test -f 'm_mach/thread_actUser.c'; then $(CYGPATH_W) 'm_mach/thread_actUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/thread_actUser.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.o: m_mach/vm_mapUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.o `test -f 'm_mach/vm_mapUser.c' || echo '$(srcdir)/'`m_mach/vm_mapUser.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/vm_mapUser.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.o `test -f 'm_mach/vm_mapUser.c' || echo '$(srcdir)/'`m_mach/vm_mapUser.c
+
+libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.obj: m_mach/vm_mapUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.obj `if test -f 'm_mach/vm_mapUser.c'; then $(CYGPATH_W) 'm_mach/vm_mapUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/vm_mapUser.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/vm_mapUser.c' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vm_mapUser.obj `if test -f 'm_mach/vm_mapUser.c'; then $(CYGPATH_W) 'm_mach/vm_mapUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/vm_mapUser.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.o: m_commandline.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.o `test -f 'm_commandline.c' || echo '$(srcdir)/'`m_commandline.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_commandline.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.o `test -f 'm_commandline.c' || echo '$(srcdir)/'`m_commandline.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.obj: m_commandline.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.obj `if test -f 'm_commandline.c'; then $(CYGPATH_W) 'm_commandline.c'; else $(CYGPATH_W) '$(srcdir)/m_commandline.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_commandline.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.obj `if test -f 'm_commandline.c'; then $(CYGPATH_W) 'm_commandline.c'; else $(CYGPATH_W) '$(srcdir)/m_commandline.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.o: m_clientstate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.o `test -f 'm_clientstate.c' || echo '$(srcdir)/'`m_clientstate.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_clientstate.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.o `test -f 'm_clientstate.c' || echo '$(srcdir)/'`m_clientstate.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.obj: m_clientstate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.obj `if test -f 'm_clientstate.c'; then $(CYGPATH_W) 'm_clientstate.c'; else $(CYGPATH_W) '$(srcdir)/m_clientstate.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_clientstate.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_clientstate.obj `if test -f 'm_clientstate.c'; then $(CYGPATH_W) 'm_clientstate.c'; else $(CYGPATH_W) '$(srcdir)/m_clientstate.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.o: m_debugger.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.o `test -f 'm_debugger.c' || echo '$(srcdir)/'`m_debugger.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debugger.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.o `test -f 'm_debugger.c' || echo '$(srcdir)/'`m_debugger.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.obj: m_debugger.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.obj `if test -f 'm_debugger.c'; then $(CYGPATH_W) 'm_debugger.c'; else $(CYGPATH_W) '$(srcdir)/m_debugger.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debugger.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debugger.obj `if test -f 'm_debugger.c'; then $(CYGPATH_W) 'm_debugger.c'; else $(CYGPATH_W) '$(srcdir)/m_debugger.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.o: m_debuglog.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.o `test -f 'm_debuglog.c' || echo '$(srcdir)/'`m_debuglog.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuglog.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.o `test -f 'm_debuglog.c' || echo '$(srcdir)/'`m_debuglog.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.obj: m_debuglog.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.obj `if test -f 'm_debuglog.c'; then $(CYGPATH_W) 'm_debuglog.c'; else $(CYGPATH_W) '$(srcdir)/m_debuglog.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuglog.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_debuglog.obj `if test -f 'm_debuglog.c'; then $(CYGPATH_W) 'm_debuglog.c'; else $(CYGPATH_W) '$(srcdir)/m_debuglog.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.o: m_errormgr.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.o `test -f 'm_errormgr.c' || echo '$(srcdir)/'`m_errormgr.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_errormgr.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.o `test -f 'm_errormgr.c' || echo '$(srcdir)/'`m_errormgr.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.obj: m_errormgr.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.obj `if test -f 'm_errormgr.c'; then $(CYGPATH_W) 'm_errormgr.c'; else $(CYGPATH_W) '$(srcdir)/m_errormgr.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_errormgr.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_errormgr.obj `if test -f 'm_errormgr.c'; then $(CYGPATH_W) 'm_errormgr.c'; else $(CYGPATH_W) '$(srcdir)/m_errormgr.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.o: m_execontext.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.o `test -f 'm_execontext.c' || echo '$(srcdir)/'`m_execontext.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_execontext.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.o `test -f 'm_execontext.c' || echo '$(srcdir)/'`m_execontext.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.obj: m_execontext.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.obj `if test -f 'm_execontext.c'; then $(CYGPATH_W) 'm_execontext.c'; else $(CYGPATH_W) '$(srcdir)/m_execontext.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_execontext.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_execontext.obj `if test -f 'm_execontext.c'; then $(CYGPATH_W) 'm_execontext.c'; else $(CYGPATH_W) '$(srcdir)/m_execontext.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.o: m_poolalloc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.o `test -f 'm_poolalloc.c' || echo '$(srcdir)/'`m_poolalloc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_poolalloc.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.o `test -f 'm_poolalloc.c' || echo '$(srcdir)/'`m_poolalloc.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.obj: m_poolalloc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.obj `if test -f 'm_poolalloc.c'; then $(CYGPATH_W) 'm_poolalloc.c'; else $(CYGPATH_W) '$(srcdir)/m_poolalloc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_poolalloc.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_poolalloc.obj `if test -f 'm_poolalloc.c'; then $(CYGPATH_W) 'm_poolalloc.c'; else $(CYGPATH_W) '$(srcdir)/m_poolalloc.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.o: m_hashtable.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.o `test -f 'm_hashtable.c' || echo '$(srcdir)/'`m_hashtable.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_hashtable.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.o `test -f 'm_hashtable.c' || echo '$(srcdir)/'`m_hashtable.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.obj: m_hashtable.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.obj `if test -f 'm_hashtable.c'; then $(CYGPATH_W) 'm_hashtable.c'; else $(CYGPATH_W) '$(srcdir)/m_hashtable.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_hashtable.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_hashtable.obj `if test -f 'm_hashtable.c'; then $(CYGPATH_W) 'm_hashtable.c'; else $(CYGPATH_W) '$(srcdir)/m_hashtable.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.o: m_libcbase.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.o `test -f 'm_libcbase.c' || echo '$(srcdir)/'`m_libcbase.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcbase.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.o `test -f 'm_libcbase.c' || echo '$(srcdir)/'`m_libcbase.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.obj: m_libcbase.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.obj `if test -f 'm_libcbase.c'; then $(CYGPATH_W) 'm_libcbase.c'; else $(CYGPATH_W) '$(srcdir)/m_libcbase.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcbase.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcbase.obj `if test -f 'm_libcbase.c'; then $(CYGPATH_W) 'm_libcbase.c'; else $(CYGPATH_W) '$(srcdir)/m_libcbase.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.o: m_libcassert.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.o `test -f 'm_libcassert.c' || echo '$(srcdir)/'`m_libcassert.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcassert.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.o `test -f 'm_libcassert.c' || echo '$(srcdir)/'`m_libcassert.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.obj: m_libcassert.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.obj `if test -f 'm_libcassert.c'; then $(CYGPATH_W) 'm_libcassert.c'; else $(CYGPATH_W) '$(srcdir)/m_libcassert.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcassert.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcassert.obj `if test -f 'm_libcassert.c'; then $(CYGPATH_W) 'm_libcassert.c'; else $(CYGPATH_W) '$(srcdir)/m_libcassert.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.o: m_libcfile.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.o `test -f 'm_libcfile.c' || echo '$(srcdir)/'`m_libcfile.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcfile.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.o `test -f 'm_libcfile.c' || echo '$(srcdir)/'`m_libcfile.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.obj: m_libcfile.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.obj `if test -f 'm_libcfile.c'; then $(CYGPATH_W) 'm_libcfile.c'; else $(CYGPATH_W) '$(srcdir)/m_libcfile.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcfile.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcfile.obj `if test -f 'm_libcfile.c'; then $(CYGPATH_W) 'm_libcfile.c'; else $(CYGPATH_W) '$(srcdir)/m_libcfile.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.o: m_libcprint.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.o `test -f 'm_libcprint.c' || echo '$(srcdir)/'`m_libcprint.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcprint.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.o `test -f 'm_libcprint.c' || echo '$(srcdir)/'`m_libcprint.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.obj: m_libcprint.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.obj `if test -f 'm_libcprint.c'; then $(CYGPATH_W) 'm_libcprint.c'; else $(CYGPATH_W) '$(srcdir)/m_libcprint.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcprint.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcprint.obj `if test -f 'm_libcprint.c'; then $(CYGPATH_W) 'm_libcprint.c'; else $(CYGPATH_W) '$(srcdir)/m_libcprint.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.o: m_libcproc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.o `test -f 'm_libcproc.c' || echo '$(srcdir)/'`m_libcproc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcproc.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.o `test -f 'm_libcproc.c' || echo '$(srcdir)/'`m_libcproc.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.obj: m_libcproc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.obj `if test -f 'm_libcproc.c'; then $(CYGPATH_W) 'm_libcproc.c'; else $(CYGPATH_W) '$(srcdir)/m_libcproc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcproc.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcproc.obj `if test -f 'm_libcproc.c'; then $(CYGPATH_W) 'm_libcproc.c'; else $(CYGPATH_W) '$(srcdir)/m_libcproc.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.o: m_libcsetjmp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.o `test -f 'm_libcsetjmp.c' || echo '$(srcdir)/'`m_libcsetjmp.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcsetjmp.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.o `test -f 'm_libcsetjmp.c' || echo '$(srcdir)/'`m_libcsetjmp.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.obj: m_libcsetjmp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.obj `if test -f 'm_libcsetjmp.c'; then $(CYGPATH_W) 'm_libcsetjmp.c'; else $(CYGPATH_W) '$(srcdir)/m_libcsetjmp.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcsetjmp.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsetjmp.obj `if test -f 'm_libcsetjmp.c'; then $(CYGPATH_W) 'm_libcsetjmp.c'; else $(CYGPATH_W) '$(srcdir)/m_libcsetjmp.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.o: m_libcsignal.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.o `test -f 'm_libcsignal.c' || echo '$(srcdir)/'`m_libcsignal.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcsignal.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.o `test -f 'm_libcsignal.c' || echo '$(srcdir)/'`m_libcsignal.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.obj: m_libcsignal.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.obj `if test -f 'm_libcsignal.c'; then $(CYGPATH_W) 'm_libcsignal.c'; else $(CYGPATH_W) '$(srcdir)/m_libcsignal.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_libcsignal.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_libcsignal.obj `if test -f 'm_libcsignal.c'; then $(CYGPATH_W) 'm_libcsignal.c'; else $(CYGPATH_W) '$(srcdir)/m_libcsignal.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.o: m_machine.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.o `test -f 'm_machine.c' || echo '$(srcdir)/'`m_machine.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_machine.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.o `test -f 'm_machine.c' || echo '$(srcdir)/'`m_machine.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.obj: m_machine.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.obj `if test -f 'm_machine.c'; then $(CYGPATH_W) 'm_machine.c'; else $(CYGPATH_W) '$(srcdir)/m_machine.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_machine.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_machine.obj `if test -f 'm_machine.c'; then $(CYGPATH_W) 'm_machine.c'; else $(CYGPATH_W) '$(srcdir)/m_machine.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.o: m_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.o `test -f 'm_main.c' || echo '$(srcdir)/'`m_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_main.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.o `test -f 'm_main.c' || echo '$(srcdir)/'`m_main.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.obj: m_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.obj `if test -f 'm_main.c'; then $(CYGPATH_W) 'm_main.c'; else $(CYGPATH_W) '$(srcdir)/m_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_main.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_main.obj `if test -f 'm_main.c'; then $(CYGPATH_W) 'm_main.c'; else $(CYGPATH_W) '$(srcdir)/m_main.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.o: m_mallocfree.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.o `test -f 'm_mallocfree.c' || echo '$(srcdir)/'`m_mallocfree.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mallocfree.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.o `test -f 'm_mallocfree.c' || echo '$(srcdir)/'`m_mallocfree.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.obj: m_mallocfree.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.obj `if test -f 'm_mallocfree.c'; then $(CYGPATH_W) 'm_mallocfree.c'; else $(CYGPATH_W) '$(srcdir)/m_mallocfree.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mallocfree.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_mallocfree.obj `if test -f 'm_mallocfree.c'; then $(CYGPATH_W) 'm_mallocfree.c'; else $(CYGPATH_W) '$(srcdir)/m_mallocfree.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.o: m_options.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.o `test -f 'm_options.c' || echo '$(srcdir)/'`m_options.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_options.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.o `test -f 'm_options.c' || echo '$(srcdir)/'`m_options.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.obj: m_options.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.obj `if test -f 'm_options.c'; then $(CYGPATH_W) 'm_options.c'; else $(CYGPATH_W) '$(srcdir)/m_options.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_options.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_options.obj `if test -f 'm_options.c'; then $(CYGPATH_W) 'm_options.c'; else $(CYGPATH_W) '$(srcdir)/m_options.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.o: m_oset.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.o `test -f 'm_oset.c' || echo '$(srcdir)/'`m_oset.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_oset.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.o `test -f 'm_oset.c' || echo '$(srcdir)/'`m_oset.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.obj: m_oset.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.obj `if test -f 'm_oset.c'; then $(CYGPATH_W) 'm_oset.c'; else $(CYGPATH_W) '$(srcdir)/m_oset.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_oset.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_oset.obj `if test -f 'm_oset.c'; then $(CYGPATH_W) 'm_oset.c'; else $(CYGPATH_W) '$(srcdir)/m_oset.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.o: m_redir.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.o `test -f 'm_redir.c' || echo '$(srcdir)/'`m_redir.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_redir.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.o `test -f 'm_redir.c' || echo '$(srcdir)/'`m_redir.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.obj: m_redir.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.obj `if test -f 'm_redir.c'; then $(CYGPATH_W) 'm_redir.c'; else $(CYGPATH_W) '$(srcdir)/m_redir.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_redir.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_redir.obj `if test -f 'm_redir.c'; then $(CYGPATH_W) 'm_redir.c'; else $(CYGPATH_W) '$(srcdir)/m_redir.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.o: m_seqmatch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.o `test -f 'm_seqmatch.c' || echo '$(srcdir)/'`m_seqmatch.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_seqmatch.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.o `test -f 'm_seqmatch.c' || echo '$(srcdir)/'`m_seqmatch.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.obj: m_seqmatch.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.obj `if test -f 'm_seqmatch.c'; then $(CYGPATH_W) 'm_seqmatch.c'; else $(CYGPATH_W) '$(srcdir)/m_seqmatch.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_seqmatch.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_seqmatch.obj `if test -f 'm_seqmatch.c'; then $(CYGPATH_W) 'm_seqmatch.c'; else $(CYGPATH_W) '$(srcdir)/m_seqmatch.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.o: m_signals.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.o `test -f 'm_signals.c' || echo '$(srcdir)/'`m_signals.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_signals.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.o `test -f 'm_signals.c' || echo '$(srcdir)/'`m_signals.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.obj: m_signals.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.obj `if test -f 'm_signals.c'; then $(CYGPATH_W) 'm_signals.c'; else $(CYGPATH_W) '$(srcdir)/m_signals.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_signals.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_signals.obj `if test -f 'm_signals.c'; then $(CYGPATH_W) 'm_signals.c'; else $(CYGPATH_W) '$(srcdir)/m_signals.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.o: m_sparsewa.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.o `test -f 'm_sparsewa.c' || echo '$(srcdir)/'`m_sparsewa.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sparsewa.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.o `test -f 'm_sparsewa.c' || echo '$(srcdir)/'`m_sparsewa.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.obj: m_sparsewa.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.obj `if test -f 'm_sparsewa.c'; then $(CYGPATH_W) 'm_sparsewa.c'; else $(CYGPATH_W) '$(srcdir)/m_sparsewa.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sparsewa.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.obj `if test -f 'm_sparsewa.c'; then $(CYGPATH_W) 'm_sparsewa.c'; else $(CYGPATH_W) '$(srcdir)/m_sparsewa.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.o: m_stacks.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.o `test -f 'm_stacks.c' || echo '$(srcdir)/'`m_stacks.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_stacks.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.o `test -f 'm_stacks.c' || echo '$(srcdir)/'`m_stacks.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.obj: m_stacks.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.obj `if test -f 'm_stacks.c'; then $(CYGPATH_W) 'm_stacks.c'; else $(CYGPATH_W) '$(srcdir)/m_stacks.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_stacks.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.obj `if test -f 'm_stacks.c'; then $(CYGPATH_W) 'm_stacks.c'; else $(CYGPATH_W) '$(srcdir)/m_stacks.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.o: m_stacktrace.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.o `test -f 'm_stacktrace.c' || echo '$(srcdir)/'`m_stacktrace.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_stacktrace.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.o `test -f 'm_stacktrace.c' || echo '$(srcdir)/'`m_stacktrace.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.obj: m_stacktrace.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.obj `if test -f 'm_stacktrace.c'; then $(CYGPATH_W) 'm_stacktrace.c'; else $(CYGPATH_W) '$(srcdir)/m_stacktrace.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_stacktrace.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.obj `if test -f 'm_stacktrace.c'; then $(CYGPATH_W) 'm_stacktrace.c'; else $(CYGPATH_W) '$(srcdir)/m_stacktrace.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.o: m_syscall.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.o `test -f 'm_syscall.c' || echo '$(srcdir)/'`m_syscall.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syscall.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.o `test -f 'm_syscall.c' || echo '$(srcdir)/'`m_syscall.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.obj: m_syscall.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.obj `if test -f 'm_syscall.c'; then $(CYGPATH_W) 'm_syscall.c'; else $(CYGPATH_W) '$(srcdir)/m_syscall.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syscall.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.obj `if test -f 'm_syscall.c'; then $(CYGPATH_W) 'm_syscall.c'; else $(CYGPATH_W) '$(srcdir)/m_syscall.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.o: m_threadstate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.o `test -f 'm_threadstate.c' || echo '$(srcdir)/'`m_threadstate.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_threadstate.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.o `test -f 'm_threadstate.c' || echo '$(srcdir)/'`m_threadstate.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.obj: m_threadstate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.obj `if test -f 'm_threadstate.c'; then $(CYGPATH_W) 'm_threadstate.c'; else $(CYGPATH_W) '$(srcdir)/m_threadstate.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_threadstate.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.obj `if test -f 'm_threadstate.c'; then $(CYGPATH_W) 'm_threadstate.c'; else $(CYGPATH_W) '$(srcdir)/m_threadstate.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.o: m_tooliface.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.o `test -f 'm_tooliface.c' || echo '$(srcdir)/'`m_tooliface.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_tooliface.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.o `test -f 'm_tooliface.c' || echo '$(srcdir)/'`m_tooliface.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.obj: m_tooliface.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.obj `if test -f 'm_tooliface.c'; then $(CYGPATH_W) 'm_tooliface.c'; else $(CYGPATH_W) '$(srcdir)/m_tooliface.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_tooliface.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.obj `if test -f 'm_tooliface.c'; then $(CYGPATH_W) 'm_tooliface.c'; else $(CYGPATH_W) '$(srcdir)/m_tooliface.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.o: m_translate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.o `test -f 'm_translate.c' || echo '$(srcdir)/'`m_translate.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_translate.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.o `test -f 'm_translate.c' || echo '$(srcdir)/'`m_translate.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.obj: m_translate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.obj `if test -f 'm_translate.c'; then $(CYGPATH_W) 'm_translate.c'; else $(CYGPATH_W) '$(srcdir)/m_translate.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_translate.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_translate.obj `if test -f 'm_translate.c'; then $(CYGPATH_W) 'm_translate.c'; else $(CYGPATH_W) '$(srcdir)/m_translate.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.o: m_transtab.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.o `test -f 'm_transtab.c' || echo '$(srcdir)/'`m_transtab.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_transtab.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.o `test -f 'm_transtab.c' || echo '$(srcdir)/'`m_transtab.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.obj: m_transtab.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.obj `if test -f 'm_transtab.c'; then $(CYGPATH_W) 'm_transtab.c'; else $(CYGPATH_W) '$(srcdir)/m_transtab.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_transtab.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_transtab.obj `if test -f 'm_transtab.c'; then $(CYGPATH_W) 'm_transtab.c'; else $(CYGPATH_W) '$(srcdir)/m_transtab.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.o: m_vki.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.o `test -f 'm_vki.c' || echo '$(srcdir)/'`m_vki.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_vki.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.o `test -f 'm_vki.c' || echo '$(srcdir)/'`m_vki.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.obj: m_vki.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.obj `if test -f 'm_vki.c'; then $(CYGPATH_W) 'm_vki.c'; else $(CYGPATH_W) '$(srcdir)/m_vki.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_vki.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vki.obj `if test -f 'm_vki.c'; then $(CYGPATH_W) 'm_vki.c'; else $(CYGPATH_W) '$(srcdir)/m_vki.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.o: m_vkiscnums.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.o `test -f 'm_vkiscnums.c' || echo '$(srcdir)/'`m_vkiscnums.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_vkiscnums.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.o `test -f 'm_vkiscnums.c' || echo '$(srcdir)/'`m_vkiscnums.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.obj: m_vkiscnums.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.obj `if test -f 'm_vkiscnums.c'; then $(CYGPATH_W) 'm_vkiscnums.c'; else $(CYGPATH_W) '$(srcdir)/m_vkiscnums.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_vkiscnums.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_vkiscnums.obj `if test -f 'm_vkiscnums.c'; then $(CYGPATH_W) 'm_vkiscnums.c'; else $(CYGPATH_W) '$(srcdir)/m_vkiscnums.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.o: m_wordfm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.o `test -f 'm_wordfm.c' || echo '$(srcdir)/'`m_wordfm.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_wordfm.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.o `test -f 'm_wordfm.c' || echo '$(srcdir)/'`m_wordfm.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.obj: m_wordfm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.obj `if test -f 'm_wordfm.c'; then $(CYGPATH_W) 'm_wordfm.c'; else $(CYGPATH_W) '$(srcdir)/m_wordfm.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_wordfm.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_wordfm.obj `if test -f 'm_wordfm.c'; then $(CYGPATH_W) 'm_wordfm.c'; else $(CYGPATH_W) '$(srcdir)/m_wordfm.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.o: m_xarray.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.o `test -f 'm_xarray.c' || echo '$(srcdir)/'`m_xarray.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_xarray.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.o `test -f 'm_xarray.c' || echo '$(srcdir)/'`m_xarray.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.obj: m_xarray.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.obj `if test -f 'm_xarray.c'; then $(CYGPATH_W) 'm_xarray.c'; else $(CYGPATH_W) '$(srcdir)/m_xarray.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_xarray.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_xarray.obj `if test -f 'm_xarray.c'; then $(CYGPATH_W) 'm_xarray.c'; else $(CYGPATH_W) '$(srcdir)/m_xarray.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.o: m_aspacehl.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.o `test -f 'm_aspacehl.c' || echo '$(srcdir)/'`m_aspacehl.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacehl.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.o `test -f 'm_aspacehl.c' || echo '$(srcdir)/'`m_aspacehl.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.obj: m_aspacehl.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.obj `if test -f 'm_aspacehl.c'; then $(CYGPATH_W) 'm_aspacehl.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacehl.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacehl.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_aspacehl.obj `if test -f 'm_aspacehl.c'; then $(CYGPATH_W) 'm_aspacehl.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacehl.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.o: m_aspacemgr/aspacemgr-common.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.o `test -f 'm_aspacemgr/aspacemgr-common.c' || echo '$(srcdir)/'`m_aspacemgr/aspacemgr-common.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacemgr/aspacemgr-common.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.o `test -f 'm_aspacemgr/aspacemgr-common.c' || echo '$(srcdir)/'`m_aspacemgr/aspacemgr-common.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.obj: m_aspacemgr/aspacemgr-common.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.obj `if test -f 'm_aspacemgr/aspacemgr-common.c'; then $(CYGPATH_W) 'm_aspacemgr/aspacemgr-common.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacemgr/aspacemgr-common.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacemgr/aspacemgr-common.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-common.obj `if test -f 'm_aspacemgr/aspacemgr-common.c'; then $(CYGPATH_W) 'm_aspacemgr/aspacemgr-common.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacemgr/aspacemgr-common.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.o: m_aspacemgr/aspacemgr-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.o `test -f 'm_aspacemgr/aspacemgr-linux.c' || echo '$(srcdir)/'`m_aspacemgr/aspacemgr-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacemgr/aspacemgr-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.o `test -f 'm_aspacemgr/aspacemgr-linux.c' || echo '$(srcdir)/'`m_aspacemgr/aspacemgr-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.obj: m_aspacemgr/aspacemgr-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.obj `if test -f 'm_aspacemgr/aspacemgr-linux.c'; then $(CYGPATH_W) 'm_aspacemgr/aspacemgr-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacemgr/aspacemgr-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_aspacemgr/aspacemgr-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-aspacemgr-linux.obj `if test -f 'm_aspacemgr/aspacemgr-linux.c'; then $(CYGPATH_W) 'm_aspacemgr/aspacemgr-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_aspacemgr/aspacemgr-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.o: m_coredump/coredump-elf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.o `test -f 'm_coredump/coredump-elf.c' || echo '$(srcdir)/'`m_coredump/coredump-elf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_coredump/coredump-elf.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.o `test -f 'm_coredump/coredump-elf.c' || echo '$(srcdir)/'`m_coredump/coredump-elf.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.obj: m_coredump/coredump-elf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.obj `if test -f 'm_coredump/coredump-elf.c'; then $(CYGPATH_W) 'm_coredump/coredump-elf.c'; else $(CYGPATH_W) '$(srcdir)/m_coredump/coredump-elf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_coredump/coredump-elf.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-elf.obj `if test -f 'm_coredump/coredump-elf.c'; then $(CYGPATH_W) 'm_coredump/coredump-elf.c'; else $(CYGPATH_W) '$(srcdir)/m_coredump/coredump-elf.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.o: m_coredump/coredump-macho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.o `test -f 'm_coredump/coredump-macho.c' || echo '$(srcdir)/'`m_coredump/coredump-macho.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_coredump/coredump-macho.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.o `test -f 'm_coredump/coredump-macho.c' || echo '$(srcdir)/'`m_coredump/coredump-macho.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.obj: m_coredump/coredump-macho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.obj `if test -f 'm_coredump/coredump-macho.c'; then $(CYGPATH_W) 'm_coredump/coredump-macho.c'; else $(CYGPATH_W) '$(srcdir)/m_coredump/coredump-macho.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_coredump/coredump-macho.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-coredump-macho.obj `if test -f 'm_coredump/coredump-macho.c'; then $(CYGPATH_W) 'm_coredump/coredump-macho.c'; else $(CYGPATH_W) '$(srcdir)/m_coredump/coredump-macho.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.o: m_debuginfo/misc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.o `test -f 'm_debuginfo/misc.c' || echo '$(srcdir)/'`m_debuginfo/misc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/misc.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.o `test -f 'm_debuginfo/misc.c' || echo '$(srcdir)/'`m_debuginfo/misc.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.obj: m_debuginfo/misc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.obj `if test -f 'm_debuginfo/misc.c'; then $(CYGPATH_W) 'm_debuginfo/misc.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/misc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/misc.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-misc.obj `if test -f 'm_debuginfo/misc.c'; then $(CYGPATH_W) 'm_debuginfo/misc.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/misc.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.o: m_debuginfo/d3basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.o `test -f 'm_debuginfo/d3basics.c' || echo '$(srcdir)/'`m_debuginfo/d3basics.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/d3basics.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.o `test -f 'm_debuginfo/d3basics.c' || echo '$(srcdir)/'`m_debuginfo/d3basics.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.obj: m_debuginfo/d3basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.obj `if test -f 'm_debuginfo/d3basics.c'; then $(CYGPATH_W) 'm_debuginfo/d3basics.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/d3basics.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/d3basics.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-d3basics.obj `if test -f 'm_debuginfo/d3basics.c'; then $(CYGPATH_W) 'm_debuginfo/d3basics.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/d3basics.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.o: m_debuginfo/debuginfo.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.o `test -f 'm_debuginfo/debuginfo.c' || echo '$(srcdir)/'`m_debuginfo/debuginfo.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/debuginfo.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.o `test -f 'm_debuginfo/debuginfo.c' || echo '$(srcdir)/'`m_debuginfo/debuginfo.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.obj: m_debuginfo/debuginfo.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.obj `if test -f 'm_debuginfo/debuginfo.c'; then $(CYGPATH_W) 'm_debuginfo/debuginfo.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/debuginfo.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/debuginfo.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-debuginfo.obj `if test -f 'm_debuginfo/debuginfo.c'; then $(CYGPATH_W) 'm_debuginfo/debuginfo.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/debuginfo.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.o: m_debuginfo/readdwarf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.o `test -f 'm_debuginfo/readdwarf.c' || echo '$(srcdir)/'`m_debuginfo/readdwarf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readdwarf.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.o `test -f 'm_debuginfo/readdwarf.c' || echo '$(srcdir)/'`m_debuginfo/readdwarf.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.obj: m_debuginfo/readdwarf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.obj `if test -f 'm_debuginfo/readdwarf.c'; then $(CYGPATH_W) 'm_debuginfo/readdwarf.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readdwarf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readdwarf.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf.obj `if test -f 'm_debuginfo/readdwarf.c'; then $(CYGPATH_W) 'm_debuginfo/readdwarf.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readdwarf.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.o: m_debuginfo/readdwarf3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.o `test -f 'm_debuginfo/readdwarf3.c' || echo '$(srcdir)/'`m_debuginfo/readdwarf3.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readdwarf3.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.o `test -f 'm_debuginfo/readdwarf3.c' || echo '$(srcdir)/'`m_debuginfo/readdwarf3.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.obj: m_debuginfo/readdwarf3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.obj `if test -f 'm_debuginfo/readdwarf3.c'; then $(CYGPATH_W) 'm_debuginfo/readdwarf3.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readdwarf3.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readdwarf3.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readdwarf3.obj `if test -f 'm_debuginfo/readdwarf3.c'; then $(CYGPATH_W) 'm_debuginfo/readdwarf3.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readdwarf3.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.o: m_debuginfo/readelf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.o `test -f 'm_debuginfo/readelf.c' || echo '$(srcdir)/'`m_debuginfo/readelf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readelf.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.o `test -f 'm_debuginfo/readelf.c' || echo '$(srcdir)/'`m_debuginfo/readelf.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.obj: m_debuginfo/readelf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.obj `if test -f 'm_debuginfo/readelf.c'; then $(CYGPATH_W) 'm_debuginfo/readelf.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readelf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readelf.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readelf.obj `if test -f 'm_debuginfo/readelf.c'; then $(CYGPATH_W) 'm_debuginfo/readelf.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readelf.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.o: m_debuginfo/readmacho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.o `test -f 'm_debuginfo/readmacho.c' || echo '$(srcdir)/'`m_debuginfo/readmacho.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readmacho.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.o `test -f 'm_debuginfo/readmacho.c' || echo '$(srcdir)/'`m_debuginfo/readmacho.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.obj: m_debuginfo/readmacho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.obj `if test -f 'm_debuginfo/readmacho.c'; then $(CYGPATH_W) 'm_debuginfo/readmacho.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readmacho.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readmacho.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readmacho.obj `if test -f 'm_debuginfo/readmacho.c'; then $(CYGPATH_W) 'm_debuginfo/readmacho.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readmacho.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.o: m_debuginfo/readpdb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.o `test -f 'm_debuginfo/readpdb.c' || echo '$(srcdir)/'`m_debuginfo/readpdb.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readpdb.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.o `test -f 'm_debuginfo/readpdb.c' || echo '$(srcdir)/'`m_debuginfo/readpdb.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.obj: m_debuginfo/readpdb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.obj `if test -f 'm_debuginfo/readpdb.c'; then $(CYGPATH_W) 'm_debuginfo/readpdb.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readpdb.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readpdb.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readpdb.obj `if test -f 'm_debuginfo/readpdb.c'; then $(CYGPATH_W) 'm_debuginfo/readpdb.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readpdb.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.o: m_debuginfo/readstabs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.o `test -f 'm_debuginfo/readstabs.c' || echo '$(srcdir)/'`m_debuginfo/readstabs.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readstabs.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.o `test -f 'm_debuginfo/readstabs.c' || echo '$(srcdir)/'`m_debuginfo/readstabs.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.obj: m_debuginfo/readstabs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.obj `if test -f 'm_debuginfo/readstabs.c'; then $(CYGPATH_W) 'm_debuginfo/readstabs.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readstabs.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/readstabs.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-readstabs.obj `if test -f 'm_debuginfo/readstabs.c'; then $(CYGPATH_W) 'm_debuginfo/readstabs.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/readstabs.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.o: m_debuginfo/storage.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.o `test -f 'm_debuginfo/storage.c' || echo '$(srcdir)/'`m_debuginfo/storage.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/storage.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.o `test -f 'm_debuginfo/storage.c' || echo '$(srcdir)/'`m_debuginfo/storage.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.obj: m_debuginfo/storage.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.obj `if test -f 'm_debuginfo/storage.c'; then $(CYGPATH_W) 'm_debuginfo/storage.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/storage.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/storage.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-storage.obj `if test -f 'm_debuginfo/storage.c'; then $(CYGPATH_W) 'm_debuginfo/storage.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/storage.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.o: m_debuginfo/tytypes.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.o `test -f 'm_debuginfo/tytypes.c' || echo '$(srcdir)/'`m_debuginfo/tytypes.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/tytypes.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.o `test -f 'm_debuginfo/tytypes.c' || echo '$(srcdir)/'`m_debuginfo/tytypes.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.obj: m_debuginfo/tytypes.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.obj `if test -f 'm_debuginfo/tytypes.c'; then $(CYGPATH_W) 'm_debuginfo/tytypes.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/tytypes.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuginfo/tytypes.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-tytypes.obj `if test -f 'm_debuginfo/tytypes.c'; then $(CYGPATH_W) 'm_debuginfo/tytypes.c'; else $(CYGPATH_W) '$(srcdir)/m_debuginfo/tytypes.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.o: m_demangle/cp-demangle.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.o `test -f 'm_demangle/cp-demangle.c' || echo '$(srcdir)/'`m_demangle/cp-demangle.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/cp-demangle.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.o `test -f 'm_demangle/cp-demangle.c' || echo '$(srcdir)/'`m_demangle/cp-demangle.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.obj: m_demangle/cp-demangle.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.obj `if test -f 'm_demangle/cp-demangle.c'; then $(CYGPATH_W) 'm_demangle/cp-demangle.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/cp-demangle.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/cp-demangle.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cp-demangle.obj `if test -f 'm_demangle/cp-demangle.c'; then $(CYGPATH_W) 'm_demangle/cp-demangle.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/cp-demangle.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.o: m_demangle/cplus-dem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.o `test -f 'm_demangle/cplus-dem.c' || echo '$(srcdir)/'`m_demangle/cplus-dem.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/cplus-dem.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.o `test -f 'm_demangle/cplus-dem.c' || echo '$(srcdir)/'`m_demangle/cplus-dem.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.obj: m_demangle/cplus-dem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.obj `if test -f 'm_demangle/cplus-dem.c'; then $(CYGPATH_W) 'm_demangle/cplus-dem.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/cplus-dem.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/cplus-dem.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-cplus-dem.obj `if test -f 'm_demangle/cplus-dem.c'; then $(CYGPATH_W) 'm_demangle/cplus-dem.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/cplus-dem.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.o: m_demangle/demangle.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.o `test -f 'm_demangle/demangle.c' || echo '$(srcdir)/'`m_demangle/demangle.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/demangle.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.o `test -f 'm_demangle/demangle.c' || echo '$(srcdir)/'`m_demangle/demangle.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.obj: m_demangle/demangle.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.obj `if test -f 'm_demangle/demangle.c'; then $(CYGPATH_W) 'm_demangle/demangle.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/demangle.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/demangle.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-demangle.obj `if test -f 'm_demangle/demangle.c'; then $(CYGPATH_W) 'm_demangle/demangle.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/demangle.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.o: m_demangle/dyn-string.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.o `test -f 'm_demangle/dyn-string.c' || echo '$(srcdir)/'`m_demangle/dyn-string.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/dyn-string.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.o `test -f 'm_demangle/dyn-string.c' || echo '$(srcdir)/'`m_demangle/dyn-string.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.obj: m_demangle/dyn-string.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.obj `if test -f 'm_demangle/dyn-string.c'; then $(CYGPATH_W) 'm_demangle/dyn-string.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/dyn-string.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/dyn-string.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-dyn-string.obj `if test -f 'm_demangle/dyn-string.c'; then $(CYGPATH_W) 'm_demangle/dyn-string.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/dyn-string.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.o: m_demangle/safe-ctype.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.o `test -f 'm_demangle/safe-ctype.c' || echo '$(srcdir)/'`m_demangle/safe-ctype.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/safe-ctype.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.o `test -f 'm_demangle/safe-ctype.c' || echo '$(srcdir)/'`m_demangle/safe-ctype.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.obj: m_demangle/safe-ctype.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.obj `if test -f 'm_demangle/safe-ctype.c'; then $(CYGPATH_W) 'm_demangle/safe-ctype.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/safe-ctype.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_demangle/safe-ctype.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-safe-ctype.obj `if test -f 'm_demangle/safe-ctype.c'; then $(CYGPATH_W) 'm_demangle/safe-ctype.c'; else $(CYGPATH_W) '$(srcdir)/m_demangle/safe-ctype.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.o: m_gdbserver/inferiors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.o `test -f 'm_gdbserver/inferiors.c' || echo '$(srcdir)/'`m_gdbserver/inferiors.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/inferiors.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.o `test -f 'm_gdbserver/inferiors.c' || echo '$(srcdir)/'`m_gdbserver/inferiors.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.obj: m_gdbserver/inferiors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.obj `if test -f 'm_gdbserver/inferiors.c'; then $(CYGPATH_W) 'm_gdbserver/inferiors.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/inferiors.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/inferiors.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-inferiors.obj `if test -f 'm_gdbserver/inferiors.c'; then $(CYGPATH_W) 'm_gdbserver/inferiors.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/inferiors.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.o: m_gdbserver/m_gdbserver.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.o `test -f 'm_gdbserver/m_gdbserver.c' || echo '$(srcdir)/'`m_gdbserver/m_gdbserver.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/m_gdbserver.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.o `test -f 'm_gdbserver/m_gdbserver.c' || echo '$(srcdir)/'`m_gdbserver/m_gdbserver.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.obj: m_gdbserver/m_gdbserver.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.obj `if test -f 'm_gdbserver/m_gdbserver.c'; then $(CYGPATH_W) 'm_gdbserver/m_gdbserver.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/m_gdbserver.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/m_gdbserver.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_gdbserver.obj `if test -f 'm_gdbserver/m_gdbserver.c'; then $(CYGPATH_W) 'm_gdbserver/m_gdbserver.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/m_gdbserver.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.o: m_gdbserver/regcache.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.o `test -f 'm_gdbserver/regcache.c' || echo '$(srcdir)/'`m_gdbserver/regcache.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/regcache.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.o `test -f 'm_gdbserver/regcache.c' || echo '$(srcdir)/'`m_gdbserver/regcache.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.obj: m_gdbserver/regcache.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.obj `if test -f 'm_gdbserver/regcache.c'; then $(CYGPATH_W) 'm_gdbserver/regcache.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/regcache.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/regcache.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-regcache.obj `if test -f 'm_gdbserver/regcache.c'; then $(CYGPATH_W) 'm_gdbserver/regcache.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/regcache.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.o: m_gdbserver/remote-utils.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.o `test -f 'm_gdbserver/remote-utils.c' || echo '$(srcdir)/'`m_gdbserver/remote-utils.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/remote-utils.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.o `test -f 'm_gdbserver/remote-utils.c' || echo '$(srcdir)/'`m_gdbserver/remote-utils.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.obj: m_gdbserver/remote-utils.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.obj `if test -f 'm_gdbserver/remote-utils.c'; then $(CYGPATH_W) 'm_gdbserver/remote-utils.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/remote-utils.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/remote-utils.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-remote-utils.obj `if test -f 'm_gdbserver/remote-utils.c'; then $(CYGPATH_W) 'm_gdbserver/remote-utils.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/remote-utils.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.o: m_gdbserver/server.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.o `test -f 'm_gdbserver/server.c' || echo '$(srcdir)/'`m_gdbserver/server.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/server.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.o `test -f 'm_gdbserver/server.c' || echo '$(srcdir)/'`m_gdbserver/server.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.obj: m_gdbserver/server.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.obj `if test -f 'm_gdbserver/server.c'; then $(CYGPATH_W) 'm_gdbserver/server.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/server.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/server.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-server.obj `if test -f 'm_gdbserver/server.c'; then $(CYGPATH_W) 'm_gdbserver/server.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/server.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.o: m_gdbserver/signals.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.o `test -f 'm_gdbserver/signals.c' || echo '$(srcdir)/'`m_gdbserver/signals.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/signals.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.o `test -f 'm_gdbserver/signals.c' || echo '$(srcdir)/'`m_gdbserver/signals.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.obj: m_gdbserver/signals.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.obj `if test -f 'm_gdbserver/signals.c'; then $(CYGPATH_W) 'm_gdbserver/signals.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/signals.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/signals.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-signals.obj `if test -f 'm_gdbserver/signals.c'; then $(CYGPATH_W) 'm_gdbserver/signals.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/signals.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.o: m_gdbserver/target.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.o `test -f 'm_gdbserver/target.c' || echo '$(srcdir)/'`m_gdbserver/target.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/target.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.o `test -f 'm_gdbserver/target.c' || echo '$(srcdir)/'`m_gdbserver/target.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.obj: m_gdbserver/target.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.obj `if test -f 'm_gdbserver/target.c'; then $(CYGPATH_W) 'm_gdbserver/target.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/target.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/target.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-target.obj `if test -f 'm_gdbserver/target.c'; then $(CYGPATH_W) 'm_gdbserver/target.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/target.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.o: m_gdbserver/utils.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.o `test -f 'm_gdbserver/utils.c' || echo '$(srcdir)/'`m_gdbserver/utils.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/utils.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.o `test -f 'm_gdbserver/utils.c' || echo '$(srcdir)/'`m_gdbserver/utils.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.obj: m_gdbserver/utils.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.obj `if test -f 'm_gdbserver/utils.c'; then $(CYGPATH_W) 'm_gdbserver/utils.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/utils.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/utils.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-utils.obj `if test -f 'm_gdbserver/utils.c'; then $(CYGPATH_W) 'm_gdbserver/utils.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/utils.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.o: m_gdbserver/valgrind-low-x86.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.o `test -f 'm_gdbserver/valgrind-low-x86.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-x86.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-x86.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.o `test -f 'm_gdbserver/valgrind-low-x86.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-x86.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.obj: m_gdbserver/valgrind-low-x86.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.obj `if test -f 'm_gdbserver/valgrind-low-x86.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-x86.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-x86.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-x86.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-x86.obj `if test -f 'm_gdbserver/valgrind-low-x86.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-x86.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-x86.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.o: m_gdbserver/valgrind-low-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.o `test -f 'm_gdbserver/valgrind-low-amd64.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-amd64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-amd64.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.o `test -f 'm_gdbserver/valgrind-low-amd64.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-amd64.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.obj: m_gdbserver/valgrind-low-amd64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.obj `if test -f 'm_gdbserver/valgrind-low-amd64.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-amd64.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-amd64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-amd64.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-amd64.obj `if test -f 'm_gdbserver/valgrind-low-amd64.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-amd64.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-amd64.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.o: m_gdbserver/valgrind-low-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.o `test -f 'm_gdbserver/valgrind-low-arm.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-arm.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-arm.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.o `test -f 'm_gdbserver/valgrind-low-arm.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-arm.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.obj: m_gdbserver/valgrind-low-arm.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.obj `if test -f 'm_gdbserver/valgrind-low-arm.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-arm.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-arm.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-arm.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-arm.obj `if test -f 'm_gdbserver/valgrind-low-arm.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-arm.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-arm.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.o: m_gdbserver/valgrind-low-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.o `test -f 'm_gdbserver/valgrind-low-ppc32.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-ppc32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-ppc32.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.o `test -f 'm_gdbserver/valgrind-low-ppc32.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-ppc32.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.obj: m_gdbserver/valgrind-low-ppc32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.obj `if test -f 'm_gdbserver/valgrind-low-ppc32.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-ppc32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-ppc32.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc32.obj `if test -f 'm_gdbserver/valgrind-low-ppc32.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-ppc32.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-ppc32.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.o: m_gdbserver/valgrind-low-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.o `test -f 'm_gdbserver/valgrind-low-ppc64.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-ppc64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-ppc64.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.o `test -f 'm_gdbserver/valgrind-low-ppc64.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-ppc64.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.obj: m_gdbserver/valgrind-low-ppc64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.obj `if test -f 'm_gdbserver/valgrind-low-ppc64.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-ppc64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-ppc64.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-ppc64.obj `if test -f 'm_gdbserver/valgrind-low-ppc64.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-ppc64.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-ppc64.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.o: m_gdbserver/valgrind-low-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.o `test -f 'm_gdbserver/valgrind-low-s390x.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-s390x.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-s390x.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.o `test -f 'm_gdbserver/valgrind-low-s390x.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-s390x.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.obj: m_gdbserver/valgrind-low-s390x.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.obj `if test -f 'm_gdbserver/valgrind-low-s390x.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-s390x.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-s390x.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-s390x.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-s390x.obj `if test -f 'm_gdbserver/valgrind-low-s390x.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-s390x.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-s390x.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.o: m_gdbserver/valgrind-low-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.o `test -f 'm_gdbserver/valgrind-low-mips32.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-mips32.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-mips32.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.o `test -f 'm_gdbserver/valgrind-low-mips32.c' || echo '$(srcdir)/'`m_gdbserver/valgrind-low-mips32.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.obj: m_gdbserver/valgrind-low-mips32.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.obj `if test -f 'm_gdbserver/valgrind-low-mips32.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-mips32.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-mips32.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/valgrind-low-mips32.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-valgrind-low-mips32.obj `if test -f 'm_gdbserver/valgrind-low-mips32.c'; then $(CYGPATH_W) 'm_gdbserver/valgrind-low-mips32.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/valgrind-low-mips32.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.o: m_gdbserver/version.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.o `test -f 'm_gdbserver/version.c' || echo '$(srcdir)/'`m_gdbserver/version.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/version.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.o `test -f 'm_gdbserver/version.c' || echo '$(srcdir)/'`m_gdbserver/version.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.obj: m_gdbserver/version.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.obj `if test -f 'm_gdbserver/version.c'; then $(CYGPATH_W) 'm_gdbserver/version.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/version.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_gdbserver/version.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-version.obj `if test -f 'm_gdbserver/version.c'; then $(CYGPATH_W) 'm_gdbserver/version.c'; else $(CYGPATH_W) '$(srcdir)/m_gdbserver/version.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.o: m_initimg/initimg-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.o `test -f 'm_initimg/initimg-linux.c' || echo '$(srcdir)/'`m_initimg/initimg-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.o `test -f 'm_initimg/initimg-linux.c' || echo '$(srcdir)/'`m_initimg/initimg-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.obj: m_initimg/initimg-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.obj `if test -f 'm_initimg/initimg-linux.c'; then $(CYGPATH_W) 'm_initimg/initimg-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-linux.obj `if test -f 'm_initimg/initimg-linux.c'; then $(CYGPATH_W) 'm_initimg/initimg-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.o: m_initimg/initimg-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.o `test -f 'm_initimg/initimg-darwin.c' || echo '$(srcdir)/'`m_initimg/initimg-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.o `test -f 'm_initimg/initimg-darwin.c' || echo '$(srcdir)/'`m_initimg/initimg-darwin.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.obj: m_initimg/initimg-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.obj `if test -f 'm_initimg/initimg-darwin.c'; then $(CYGPATH_W) 'm_initimg/initimg-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-darwin.obj `if test -f 'm_initimg/initimg-darwin.c'; then $(CYGPATH_W) 'm_initimg/initimg-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.o: m_initimg/initimg-pathscan.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.o `test -f 'm_initimg/initimg-pathscan.c' || echo '$(srcdir)/'`m_initimg/initimg-pathscan.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-pathscan.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.o `test -f 'm_initimg/initimg-pathscan.c' || echo '$(srcdir)/'`m_initimg/initimg-pathscan.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.obj: m_initimg/initimg-pathscan.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.obj `if test -f 'm_initimg/initimg-pathscan.c'; then $(CYGPATH_W) 'm_initimg/initimg-pathscan.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-pathscan.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_initimg/initimg-pathscan.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-initimg-pathscan.obj `if test -f 'm_initimg/initimg-pathscan.c'; then $(CYGPATH_W) 'm_initimg/initimg-pathscan.c'; else $(CYGPATH_W) '$(srcdir)/m_initimg/initimg-pathscan.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.o: m_mach/mach_basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.o `test -f 'm_mach/mach_basics.c' || echo '$(srcdir)/'`m_mach/mach_basics.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_basics.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.o `test -f 'm_mach/mach_basics.c' || echo '$(srcdir)/'`m_mach/mach_basics.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.obj: m_mach/mach_basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.obj `if test -f 'm_mach/mach_basics.c'; then $(CYGPATH_W) 'm_mach/mach_basics.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_basics.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_basics.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_basics.obj `if test -f 'm_mach/mach_basics.c'; then $(CYGPATH_W) 'm_mach/mach_basics.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_basics.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.o: m_mach/mach_msg.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.o `test -f 'm_mach/mach_msg.c' || echo '$(srcdir)/'`m_mach/mach_msg.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_msg.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.o `test -f 'm_mach/mach_msg.c' || echo '$(srcdir)/'`m_mach/mach_msg.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.obj: m_mach/mach_msg.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.obj `if test -f 'm_mach/mach_msg.c'; then $(CYGPATH_W) 'm_mach/mach_msg.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_msg.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_msg.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_msg.obj `if test -f 'm_mach/mach_msg.c'; then $(CYGPATH_W) 'm_mach/mach_msg.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_msg.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.o: m_replacemalloc/replacemalloc_core.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.o `test -f 'm_replacemalloc/replacemalloc_core.c' || echo '$(srcdir)/'`m_replacemalloc/replacemalloc_core.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_replacemalloc/replacemalloc_core.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.o `test -f 'm_replacemalloc/replacemalloc_core.c' || echo '$(srcdir)/'`m_replacemalloc/replacemalloc_core.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.obj: m_replacemalloc/replacemalloc_core.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.obj `if test -f 'm_replacemalloc/replacemalloc_core.c'; then $(CYGPATH_W) 'm_replacemalloc/replacemalloc_core.c'; else $(CYGPATH_W) '$(srcdir)/m_replacemalloc/replacemalloc_core.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_replacemalloc/replacemalloc_core.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-replacemalloc_core.obj `if test -f 'm_replacemalloc/replacemalloc_core.c'; then $(CYGPATH_W) 'm_replacemalloc/replacemalloc_core.c'; else $(CYGPATH_W) '$(srcdir)/m_replacemalloc/replacemalloc_core.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.o: m_scheduler/scheduler.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.o `test -f 'm_scheduler/scheduler.c' || echo '$(srcdir)/'`m_scheduler/scheduler.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/scheduler.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.o `test -f 'm_scheduler/scheduler.c' || echo '$(srcdir)/'`m_scheduler/scheduler.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.obj: m_scheduler/scheduler.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.obj `if test -f 'm_scheduler/scheduler.c'; then $(CYGPATH_W) 'm_scheduler/scheduler.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/scheduler.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/scheduler.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-scheduler.obj `if test -f 'm_scheduler/scheduler.c'; then $(CYGPATH_W) 'm_scheduler/scheduler.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/scheduler.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.o: m_scheduler/sema.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.o `test -f 'm_scheduler/sema.c' || echo '$(srcdir)/'`m_scheduler/sema.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sema.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.o `test -f 'm_scheduler/sema.c' || echo '$(srcdir)/'`m_scheduler/sema.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.obj: m_scheduler/sema.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.obj `if test -f 'm_scheduler/sema.c'; then $(CYGPATH_W) 'm_scheduler/sema.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sema.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sema.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sema.obj `if test -f 'm_scheduler/sema.c'; then $(CYGPATH_W) 'm_scheduler/sema.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sema.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.o: m_scheduler/sched-lock.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.o `test -f 'm_scheduler/sched-lock.c' || echo '$(srcdir)/'`m_scheduler/sched-lock.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sched-lock.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.o `test -f 'm_scheduler/sched-lock.c' || echo '$(srcdir)/'`m_scheduler/sched-lock.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.obj: m_scheduler/sched-lock.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.obj `if test -f 'm_scheduler/sched-lock.c'; then $(CYGPATH_W) 'm_scheduler/sched-lock.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sched-lock.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sched-lock.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock.obj `if test -f 'm_scheduler/sched-lock.c'; then $(CYGPATH_W) 'm_scheduler/sched-lock.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sched-lock.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.o: m_scheduler/sched-lock-generic.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.o `test -f 'm_scheduler/sched-lock-generic.c' || echo '$(srcdir)/'`m_scheduler/sched-lock-generic.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sched-lock-generic.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.o `test -f 'm_scheduler/sched-lock-generic.c' || echo '$(srcdir)/'`m_scheduler/sched-lock-generic.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.obj: m_scheduler/sched-lock-generic.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.obj `if test -f 'm_scheduler/sched-lock-generic.c'; then $(CYGPATH_W) 'm_scheduler/sched-lock-generic.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sched-lock-generic.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/sched-lock-generic.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sched-lock-generic.obj `if test -f 'm_scheduler/sched-lock-generic.c'; then $(CYGPATH_W) 'm_scheduler/sched-lock-generic.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/sched-lock-generic.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.o: m_sigframe/sigframe-x86-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.o `test -f 'm_sigframe/sigframe-x86-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-x86-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-x86-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.o `test -f 'm_sigframe/sigframe-x86-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-x86-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.obj: m_sigframe/sigframe-x86-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.obj `if test -f 'm_sigframe/sigframe-x86-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-x86-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-x86-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-x86-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-linux.obj `if test -f 'm_sigframe/sigframe-x86-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-x86-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-x86-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.o: m_sigframe/sigframe-amd64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.o `test -f 'm_sigframe/sigframe-amd64-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-amd64-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-amd64-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.o `test -f 'm_sigframe/sigframe-amd64-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-amd64-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.obj: m_sigframe/sigframe-amd64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.obj `if test -f 'm_sigframe/sigframe-amd64-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-amd64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-amd64-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-amd64-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-linux.obj `if test -f 'm_sigframe/sigframe-amd64-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-amd64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-amd64-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.o: m_sigframe/sigframe-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.o `test -f 'm_sigframe/sigframe-ppc32-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-ppc32-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.o `test -f 'm_sigframe/sigframe-ppc32-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-ppc32-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj: m_sigframe/sigframe-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj `if test -f 'm_sigframe/sigframe-ppc32-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-ppc32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-ppc32-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-ppc32-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc32-linux.obj `if test -f 'm_sigframe/sigframe-ppc32-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-ppc32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-ppc32-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.o: m_sigframe/sigframe-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.o `test -f 'm_sigframe/sigframe-ppc64-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-ppc64-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.o `test -f 'm_sigframe/sigframe-ppc64-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-ppc64-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj: m_sigframe/sigframe-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj `if test -f 'm_sigframe/sigframe-ppc64-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-ppc64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-ppc64-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-ppc64-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-linux.obj `if test -f 'm_sigframe/sigframe-ppc64-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-ppc64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-ppc64-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.o: m_sigframe/sigframe-arm-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.o `test -f 'm_sigframe/sigframe-arm-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-arm-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-arm-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.o `test -f 'm_sigframe/sigframe-arm-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-arm-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.obj: m_sigframe/sigframe-arm-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.obj `if test -f 'm_sigframe/sigframe-arm-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-arm-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-arm-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-arm-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-arm-linux.obj `if test -f 'm_sigframe/sigframe-arm-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-arm-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-arm-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.o: m_sigframe/sigframe-s390x-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.o `test -f 'm_sigframe/sigframe-s390x-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-s390x-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-s390x-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.o `test -f 'm_sigframe/sigframe-s390x-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-s390x-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.obj: m_sigframe/sigframe-s390x-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.obj `if test -f 'm_sigframe/sigframe-s390x-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-s390x-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-s390x-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-s390x-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-s390x-linux.obj `if test -f 'm_sigframe/sigframe-s390x-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-s390x-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-s390x-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.o: m_sigframe/sigframe-mips32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.o `test -f 'm_sigframe/sigframe-mips32-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-mips32-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-mips32-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.o `test -f 'm_sigframe/sigframe-mips32-linux.c' || echo '$(srcdir)/'`m_sigframe/sigframe-mips32-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.obj: m_sigframe/sigframe-mips32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.obj `if test -f 'm_sigframe/sigframe-mips32-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-mips32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-mips32-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-mips32-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-mips32-linux.obj `if test -f 'm_sigframe/sigframe-mips32-linux.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-mips32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-mips32-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.o: m_sigframe/sigframe-x86-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.o `test -f 'm_sigframe/sigframe-x86-darwin.c' || echo '$(srcdir)/'`m_sigframe/sigframe-x86-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-x86-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.o `test -f 'm_sigframe/sigframe-x86-darwin.c' || echo '$(srcdir)/'`m_sigframe/sigframe-x86-darwin.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.obj: m_sigframe/sigframe-x86-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.obj `if test -f 'm_sigframe/sigframe-x86-darwin.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-x86-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-x86-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-x86-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.obj `if test -f 'm_sigframe/sigframe-x86-darwin.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-x86-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-x86-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.o: m_sigframe/sigframe-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.o `test -f 'm_sigframe/sigframe-amd64-darwin.c' || echo '$(srcdir)/'`m_sigframe/sigframe-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-amd64-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.o `test -f 'm_sigframe/sigframe-amd64-darwin.c' || echo '$(srcdir)/'`m_sigframe/sigframe-amd64-darwin.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj: m_sigframe/sigframe-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj `if test -f 'm_sigframe/sigframe-amd64-darwin.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-amd64-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-amd64-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_sigframe/sigframe-amd64-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.obj `if test -f 'm_sigframe/sigframe-amd64-darwin.c'; then $(CYGPATH_W) 'm_sigframe/sigframe-amd64-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_sigframe/sigframe-amd64-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.o: m_syswrap/syswrap-main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.o `test -f 'm_syswrap/syswrap-main.c' || echo '$(srcdir)/'`m_syswrap/syswrap-main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-main.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.o `test -f 'm_syswrap/syswrap-main.c' || echo '$(srcdir)/'`m_syswrap/syswrap-main.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.obj: m_syswrap/syswrap-main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.obj `if test -f 'm_syswrap/syswrap-main.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-main.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-main.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-main.obj `if test -f 'm_syswrap/syswrap-main.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-main.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-main.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.o: m_syswrap/syswrap-generic.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.o `test -f 'm_syswrap/syswrap-generic.c' || echo '$(srcdir)/'`m_syswrap/syswrap-generic.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-generic.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.o `test -f 'm_syswrap/syswrap-generic.c' || echo '$(srcdir)/'`m_syswrap/syswrap-generic.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.obj: m_syswrap/syswrap-generic.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.obj `if test -f 'm_syswrap/syswrap-generic.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-generic.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-generic.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-generic.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-generic.obj `if test -f 'm_syswrap/syswrap-generic.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-generic.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-generic.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.o: m_syswrap/syswrap-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.o `test -f 'm_syswrap/syswrap-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.o `test -f 'm_syswrap/syswrap-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.obj: m_syswrap/syswrap-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.obj `if test -f 'm_syswrap/syswrap-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux.obj `if test -f 'm_syswrap/syswrap-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.o: m_syswrap/syswrap-linux-variants.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.o `test -f 'm_syswrap/syswrap-linux-variants.c' || echo '$(srcdir)/'`m_syswrap/syswrap-linux-variants.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-linux-variants.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.o `test -f 'm_syswrap/syswrap-linux-variants.c' || echo '$(srcdir)/'`m_syswrap/syswrap-linux-variants.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.obj: m_syswrap/syswrap-linux-variants.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.obj `if test -f 'm_syswrap/syswrap-linux-variants.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-linux-variants.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-linux-variants.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-linux-variants.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-linux-variants.obj `if test -f 'm_syswrap/syswrap-linux-variants.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-linux-variants.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-linux-variants.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.o: m_syswrap/syswrap-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.o `test -f 'm_syswrap/syswrap-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.o `test -f 'm_syswrap/syswrap-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-darwin.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.obj: m_syswrap/syswrap-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.obj `if test -f 'm_syswrap/syswrap-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-darwin.obj `if test -f 'm_syswrap/syswrap-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.o: m_syswrap/syswrap-x86-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.o `test -f 'm_syswrap/syswrap-x86-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-x86-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.o `test -f 'm_syswrap/syswrap-x86-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.obj: m_syswrap/syswrap-x86-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.obj `if test -f 'm_syswrap/syswrap-x86-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-x86-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-x86-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-x86-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-linux.obj `if test -f 'm_syswrap/syswrap-x86-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-x86-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-x86-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.o: m_syswrap/syswrap-amd64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.o `test -f 'm_syswrap/syswrap-amd64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-amd64-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-amd64-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.o `test -f 'm_syswrap/syswrap-amd64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-amd64-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.obj: m_syswrap/syswrap-amd64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.obj `if test -f 'm_syswrap/syswrap-amd64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-amd64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-amd64-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-amd64-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-linux.obj `if test -f 'm_syswrap/syswrap-amd64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-amd64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-amd64-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.o: m_syswrap/syswrap-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.o `test -f 'm_syswrap/syswrap-ppc32-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-ppc32-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.o `test -f 'm_syswrap/syswrap-ppc32-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-ppc32-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj: m_syswrap/syswrap-ppc32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj `if test -f 'm_syswrap/syswrap-ppc32-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-ppc32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-ppc32-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-ppc32-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc32-linux.obj `if test -f 'm_syswrap/syswrap-ppc32-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-ppc32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-ppc32-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.o: m_syswrap/syswrap-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.o `test -f 'm_syswrap/syswrap-ppc64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-ppc64-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.o `test -f 'm_syswrap/syswrap-ppc64-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-ppc64-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj: m_syswrap/syswrap-ppc64-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj `if test -f 'm_syswrap/syswrap-ppc64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-ppc64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-ppc64-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-ppc64-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-ppc64-linux.obj `if test -f 'm_syswrap/syswrap-ppc64-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-ppc64-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-ppc64-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.o: m_syswrap/syswrap-arm-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.o `test -f 'm_syswrap/syswrap-arm-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-arm-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-arm-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.o `test -f 'm_syswrap/syswrap-arm-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-arm-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.obj: m_syswrap/syswrap-arm-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.obj `if test -f 'm_syswrap/syswrap-arm-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-arm-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-arm-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-arm-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-arm-linux.obj `if test -f 'm_syswrap/syswrap-arm-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-arm-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-arm-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.o: m_syswrap/syswrap-s390x-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.o `test -f 'm_syswrap/syswrap-s390x-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-s390x-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-s390x-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.o `test -f 'm_syswrap/syswrap-s390x-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-s390x-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.obj: m_syswrap/syswrap-s390x-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.obj `if test -f 'm_syswrap/syswrap-s390x-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-s390x-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-s390x-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-s390x-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-s390x-linux.obj `if test -f 'm_syswrap/syswrap-s390x-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-s390x-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-s390x-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.o: m_syswrap/syswrap-mips32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.o `test -f 'm_syswrap/syswrap-mips32-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-mips32-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-mips32-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.o `test -f 'm_syswrap/syswrap-mips32-linux.c' || echo '$(srcdir)/'`m_syswrap/syswrap-mips32-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.obj: m_syswrap/syswrap-mips32-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.obj `if test -f 'm_syswrap/syswrap-mips32-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-mips32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-mips32-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-mips32-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-mips32-linux.obj `if test -f 'm_syswrap/syswrap-mips32-linux.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-mips32-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-mips32-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o: m_syswrap/syswrap-x86-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o `test -f 'm_syswrap/syswrap-x86-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-x86-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.o `test -f 'm_syswrap/syswrap-x86-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-x86-darwin.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.obj: m_syswrap/syswrap-x86-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.obj `if test -f 'm_syswrap/syswrap-x86-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-x86-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-x86-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-x86-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-x86-darwin.obj `if test -f 'm_syswrap/syswrap-x86-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-x86-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-x86-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.o: m_syswrap/syswrap-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.o `test -f 'm_syswrap/syswrap-amd64-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-amd64-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.o `test -f 'm_syswrap/syswrap-amd64-darwin.c' || echo '$(srcdir)/'`m_syswrap/syswrap-amd64-darwin.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj: m_syswrap/syswrap-amd64-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj `if test -f 'm_syswrap/syswrap-amd64-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-amd64-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-amd64-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_syswrap/syswrap-amd64-darwin.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syswrap-amd64-darwin.obj `if test -f 'm_syswrap/syswrap-amd64-darwin.c'; then $(CYGPATH_W) 'm_syswrap/syswrap-amd64-darwin.c'; else $(CYGPATH_W) '$(srcdir)/m_syswrap/syswrap-amd64-darwin.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.o: m_ume/elf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.o `test -f 'm_ume/elf.c' || echo '$(srcdir)/'`m_ume/elf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/elf.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.o `test -f 'm_ume/elf.c' || echo '$(srcdir)/'`m_ume/elf.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.obj: m_ume/elf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.obj `if test -f 'm_ume/elf.c'; then $(CYGPATH_W) 'm_ume/elf.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/elf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/elf.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-elf.obj `if test -f 'm_ume/elf.c'; then $(CYGPATH_W) 'm_ume/elf.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/elf.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.o: m_ume/macho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.o `test -f 'm_ume/macho.c' || echo '$(srcdir)/'`m_ume/macho.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/macho.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.o `test -f 'm_ume/macho.c' || echo '$(srcdir)/'`m_ume/macho.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.obj: m_ume/macho.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.obj `if test -f 'm_ume/macho.c'; then $(CYGPATH_W) 'm_ume/macho.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/macho.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/macho.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-macho.obj `if test -f 'm_ume/macho.c'; then $(CYGPATH_W) 'm_ume/macho.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/macho.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.o: m_ume/main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.o `test -f 'm_ume/main.c' || echo '$(srcdir)/'`m_ume/main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/main.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.o `test -f 'm_ume/main.c' || echo '$(srcdir)/'`m_ume/main.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.obj: m_ume/main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.obj `if test -f 'm_ume/main.c'; then $(CYGPATH_W) 'm_ume/main.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/main.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main.obj `if test -f 'm_ume/main.c'; then $(CYGPATH_W) 'm_ume/main.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/main.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.o: m_ume/script.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.o `test -f 'm_ume/script.c' || echo '$(srcdir)/'`m_ume/script.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/script.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.o `test -f 'm_ume/script.c' || echo '$(srcdir)/'`m_ume/script.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.obj: m_ume/script.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.obj `if test -f 'm_ume/script.c'; then $(CYGPATH_W) 'm_ume/script.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/script.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_ume/script.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-script.obj `if test -f 'm_ume/script.c'; then $(CYGPATH_W) 'm_ume/script.c'; else $(CYGPATH_W) '$(srcdir)/m_ume/script.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.o: m_scheduler/ticket-lock-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.o `test -f 'm_scheduler/ticket-lock-linux.c' || echo '$(srcdir)/'`m_scheduler/ticket-lock-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/ticket-lock-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.o `test -f 'm_scheduler/ticket-lock-linux.c' || echo '$(srcdir)/'`m_scheduler/ticket-lock-linux.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.obj: m_scheduler/ticket-lock-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.obj `if test -f 'm_scheduler/ticket-lock-linux.c'; then $(CYGPATH_W) 'm_scheduler/ticket-lock-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/ticket-lock-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_scheduler/ticket-lock-linux.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-ticket-lock-linux.obj `if test -f 'm_scheduler/ticket-lock-linux.c'; then $(CYGPATH_W) 'm_scheduler/ticket-lock-linux.c'; else $(CYGPATH_W) '$(srcdir)/m_scheduler/ticket-lock-linux.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.o: m_mach/mach_vmUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.o `test -f 'm_mach/mach_vmUser.c' || echo '$(srcdir)/'`m_mach/mach_vmUser.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_vmUser.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.o `test -f 'm_mach/mach_vmUser.c' || echo '$(srcdir)/'`m_mach/mach_vmUser.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.obj: m_mach/mach_vmUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.obj `if test -f 'm_mach/mach_vmUser.c'; then $(CYGPATH_W) 'm_mach/mach_vmUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_vmUser.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/mach_vmUser.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_vmUser.obj `if test -f 'm_mach/mach_vmUser.c'; then $(CYGPATH_W) 'm_mach/mach_vmUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_vmUser.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.o: m_mach/taskUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.o `test -f 'm_mach/taskUser.c' || echo '$(srcdir)/'`m_mach/taskUser.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/taskUser.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.o `test -f 'm_mach/taskUser.c' || echo '$(srcdir)/'`m_mach/taskUser.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.obj: m_mach/taskUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.obj `if test -f 'm_mach/taskUser.c'; then $(CYGPATH_W) 'm_mach/taskUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/taskUser.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/taskUser.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-taskUser.obj `if test -f 'm_mach/taskUser.c'; then $(CYGPATH_W) 'm_mach/taskUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/taskUser.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.o: m_mach/thread_actUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.o `test -f 'm_mach/thread_actUser.c' || echo '$(srcdir)/'`m_mach/thread_actUser.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/thread_actUser.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.o `test -f 'm_mach/thread_actUser.c' || echo '$(srcdir)/'`m_mach/thread_actUser.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.obj: m_mach/thread_actUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.obj `if test -f 'm_mach/thread_actUser.c'; then $(CYGPATH_W) 'm_mach/thread_actUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/thread_actUser.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/thread_actUser.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-thread_actUser.obj `if test -f 'm_mach/thread_actUser.c'; then $(CYGPATH_W) 'm_mach/thread_actUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/thread_actUser.c'; fi`
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.o: m_mach/vm_mapUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.o `test -f 'm_mach/vm_mapUser.c' || echo '$(srcdir)/'`m_mach/vm_mapUser.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/vm_mapUser.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.o `test -f 'm_mach/vm_mapUser.c' || echo '$(srcdir)/'`m_mach/vm_mapUser.c
+
+libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.obj: m_mach/vm_mapUser.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.obj `if test -f 'm_mach/vm_mapUser.c'; then $(CYGPATH_W) 'm_mach/vm_mapUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/vm_mapUser.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_mach/vm_mapUser.c' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vm_mapUser.obj `if test -f 'm_mach/vm_mapUser.c'; then $(CYGPATH_W) 'm_mach/vm_mapUser.c'; else $(CYGPATH_W) '$(srcdir)/m_mach/vm_mapUser.c'; fi`
+
+libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.o: m_replacemalloc/vg_replace_malloc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.o -MD -MP -MF $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.Tpo -c -o libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.o `test -f 'm_replacemalloc/vg_replace_malloc.c' || echo '$(srcdir)/'`m_replacemalloc/vg_replace_malloc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.Tpo $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_replacemalloc/vg_replace_malloc.c' object='libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.o `test -f 'm_replacemalloc/vg_replace_malloc.c' || echo '$(srcdir)/'`m_replacemalloc/vg_replace_malloc.c
+
+libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.obj: m_replacemalloc/vg_replace_malloc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.obj -MD -MP -MF $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.Tpo -c -o libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.obj `if test -f 'm_replacemalloc/vg_replace_malloc.c'; then $(CYGPATH_W) 'm_replacemalloc/vg_replace_malloc.c'; else $(CYGPATH_W) '$(srcdir)/m_replacemalloc/vg_replace_malloc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.Tpo $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_replacemalloc/vg_replace_malloc.c' object='libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libreplacemalloc_toolpreload_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-vg_replace_malloc.obj `if test -f 'm_replacemalloc/vg_replace_malloc.c'; then $(CYGPATH_W) 'm_replacemalloc/vg_replace_malloc.c'; else $(CYGPATH_W) '$(srcdir)/m_replacemalloc/vg_replace_malloc.c'; fi`
+
+libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.o: m_replacemalloc/vg_replace_malloc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.o -MD -MP -MF $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.Tpo -c -o libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.o `test -f 'm_replacemalloc/vg_replace_malloc.c' || echo '$(srcdir)/'`m_replacemalloc/vg_replace_malloc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.Tpo $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_replacemalloc/vg_replace_malloc.c' object='libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.o `test -f 'm_replacemalloc/vg_replace_malloc.c' || echo '$(srcdir)/'`m_replacemalloc/vg_replace_malloc.c
+
+libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.obj: m_replacemalloc/vg_replace_malloc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.obj -MD -MP -MF $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.Tpo -c -o libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.obj `if test -f 'm_replacemalloc/vg_replace_malloc.c'; then $(CYGPATH_W) 'm_replacemalloc/vg_replace_malloc.c'; else $(CYGPATH_W) '$(srcdir)/m_replacemalloc/vg_replace_malloc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.Tpo $(DEPDIR)/libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_replacemalloc/vg_replace_malloc.c' object='libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libreplacemalloc_toolpreload_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-vg_replace_malloc.obj `if test -f 'm_replacemalloc/vg_replace_malloc.c'; then $(CYGPATH_W) 'm_replacemalloc/vg_replace_malloc.c'; else $(CYGPATH_W) '$(srcdir)/m_replacemalloc/vg_replace_malloc.c'; fi`
+
+valgrind-launcher-darwin.o: launcher-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -MT valgrind-launcher-darwin.o -MD -MP -MF $(DEPDIR)/valgrind-launcher-darwin.Tpo -c -o valgrind-launcher-darwin.o `test -f 'launcher-darwin.c' || echo '$(srcdir)/'`launcher-darwin.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/valgrind-launcher-darwin.Tpo $(DEPDIR)/valgrind-launcher-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='launcher-darwin.c' object='valgrind-launcher-darwin.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -c -o valgrind-launcher-darwin.o `test -f 'launcher-darwin.c' || echo '$(srcdir)/'`launcher-darwin.c
+
+valgrind-launcher-darwin.obj: launcher-darwin.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -MT valgrind-launcher-darwin.obj -MD -MP -MF $(DEPDIR)/valgrind-launcher-darwin.Tpo -c -o valgrind-launcher-darwin.obj `if test -f 'launcher-darwin.c'; then $(CYGPATH_W) 'launcher-darwin.c'; else $(CYGPATH_W) '$(srcdir)/launcher-darwin.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/valgrind-launcher-darwin.Tpo $(DEPDIR)/valgrind-launcher-darwin.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='launcher-darwin.c' object='valgrind-launcher-darwin.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -c -o valgrind-launcher-darwin.obj `if test -f 'launcher-darwin.c'; then $(CYGPATH_W) 'launcher-darwin.c'; else $(CYGPATH_W) '$(srcdir)/launcher-darwin.c'; fi`
+
+valgrind-m_debuglog.o: m_debuglog.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -MT valgrind-m_debuglog.o -MD -MP -MF $(DEPDIR)/valgrind-m_debuglog.Tpo -c -o valgrind-m_debuglog.o `test -f 'm_debuglog.c' || echo '$(srcdir)/'`m_debuglog.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/valgrind-m_debuglog.Tpo $(DEPDIR)/valgrind-m_debuglog.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuglog.c' object='valgrind-m_debuglog.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -c -o valgrind-m_debuglog.o `test -f 'm_debuglog.c' || echo '$(srcdir)/'`m_debuglog.c
+
+valgrind-m_debuglog.obj: m_debuglog.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -MT valgrind-m_debuglog.obj -MD -MP -MF $(DEPDIR)/valgrind-m_debuglog.Tpo -c -o valgrind-m_debuglog.obj `if test -f 'm_debuglog.c'; then $(CYGPATH_W) 'm_debuglog.c'; else $(CYGPATH_W) '$(srcdir)/m_debuglog.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/valgrind-m_debuglog.Tpo $(DEPDIR)/valgrind-m_debuglog.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='m_debuglog.c' object='valgrind-m_debuglog.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -c -o valgrind-m_debuglog.obj `if test -f 'm_debuglog.c'; then $(CYGPATH_W) 'm_debuglog.c'; else $(CYGPATH_W) '$(srcdir)/m_debuglog.c'; fi`
+
+valgrind-launcher-linux.o: launcher-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -MT valgrind-launcher-linux.o -MD -MP -MF $(DEPDIR)/valgrind-launcher-linux.Tpo -c -o valgrind-launcher-linux.o `test -f 'launcher-linux.c' || echo '$(srcdir)/'`launcher-linux.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/valgrind-launcher-linux.Tpo $(DEPDIR)/valgrind-launcher-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='launcher-linux.c' object='valgrind-launcher-linux.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -c -o valgrind-launcher-linux.o `test -f 'launcher-linux.c' || echo '$(srcdir)/'`launcher-linux.c
+
+valgrind-launcher-linux.obj: launcher-linux.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -MT valgrind-launcher-linux.obj -MD -MP -MF $(DEPDIR)/valgrind-launcher-linux.Tpo -c -o valgrind-launcher-linux.obj `if test -f 'launcher-linux.c'; then $(CYGPATH_W) 'launcher-linux.c'; else $(CYGPATH_W) '$(srcdir)/launcher-linux.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/valgrind-launcher-linux.Tpo $(DEPDIR)/valgrind-launcher-linux.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='launcher-linux.c' object='valgrind-launcher-linux.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(valgrind_CPPFLAGS) $(CPPFLAGS) $(valgrind_CFLAGS) $(CFLAGS) -c -o valgrind-launcher-linux.obj `if test -f 'launcher-linux.c'; then $(CYGPATH_W) 'launcher-linux.c'; else $(CYGPATH_W) '$(srcdir)/launcher-linux.c'; fi`
+
+vgdb-vgdb.o: vgdb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgdb_CPPFLAGS) $(CPPFLAGS) $(vgdb_CFLAGS) $(CFLAGS) -MT vgdb-vgdb.o -MD -MP -MF $(DEPDIR)/vgdb-vgdb.Tpo -c -o vgdb-vgdb.o `test -f 'vgdb.c' || echo '$(srcdir)/'`vgdb.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgdb-vgdb.Tpo $(DEPDIR)/vgdb-vgdb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vgdb.c' object='vgdb-vgdb.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgdb_CPPFLAGS) $(CPPFLAGS) $(vgdb_CFLAGS) $(CFLAGS) -c -o vgdb-vgdb.o `test -f 'vgdb.c' || echo '$(srcdir)/'`vgdb.c
+
+vgdb-vgdb.obj: vgdb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgdb_CPPFLAGS) $(CPPFLAGS) $(vgdb_CFLAGS) $(CFLAGS) -MT vgdb-vgdb.obj -MD -MP -MF $(DEPDIR)/vgdb-vgdb.Tpo -c -o vgdb-vgdb.obj `if test -f 'vgdb.c'; then $(CYGPATH_W) 'vgdb.c'; else $(CYGPATH_W) '$(srcdir)/vgdb.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgdb-vgdb.Tpo $(DEPDIR)/vgdb-vgdb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vgdb.c' object='vgdb-vgdb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgdb_CPPFLAGS) $(CPPFLAGS) $(vgdb_CFLAGS) $(CFLAGS) -c -o vgdb-vgdb.obj `if test -f 'vgdb.c'; then $(CYGPATH_W) 'vgdb.c'; else $(CYGPATH_W) '$(srcdir)/vgdb.c'; fi`
+
+vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.o: vg_preloaded.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.o -MD -MP -MF $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.Tpo -c -o vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.o `test -f 'vg_preloaded.c' || echo '$(srcdir)/'`vg_preloaded.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.Tpo $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vg_preloaded.c' object='vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.o `test -f 'vg_preloaded.c' || echo '$(srcdir)/'`vg_preloaded.c
+
+vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.obj: vg_preloaded.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.obj -MD -MP -MF $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.Tpo -c -o vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.obj `if test -f 'vg_preloaded.c'; then $(CYGPATH_W) 'vg_preloaded.c'; else $(CYGPATH_W) '$(srcdir)/vg_preloaded.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.Tpo $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vg_preloaded.c' object='vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_core_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-vg_preloaded.obj `if test -f 'vg_preloaded.c'; then $(CYGPATH_W) 'vg_preloaded.c'; else $(CYGPATH_W) '$(srcdir)/vg_preloaded.c'; fi`
+
+vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.o: vg_preloaded.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.o -MD -MP -MF $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.Tpo -c -o vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.o `test -f 'vg_preloaded.c' || echo '$(srcdir)/'`vg_preloaded.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.Tpo $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vg_preloaded.c' object='vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.o `test -f 'vg_preloaded.c' || echo '$(srcdir)/'`vg_preloaded.c
+
+vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.obj: vg_preloaded.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.obj -MD -MP -MF $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.Tpo -c -o vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.obj `if test -f 'vg_preloaded.c'; then $(CYGPATH_W) 'vg_preloaded.c'; else $(CYGPATH_W) '$(srcdir)/vg_preloaded.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.Tpo $(DEPDIR)/vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vg_preloaded.c' object='vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_core_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-vg_preloaded.obj `if test -f 'vg_preloaded.c'; then $(CYGPATH_W) 'vg_preloaded.c'; else $(CYGPATH_W) '$(srcdir)/vg_preloaded.c'; fi`
+install-vglibDATA: $(vglib_DATA)
+ @$(NORMAL_INSTALL)
+ test -z "$(vglibdir)" || $(MKDIR_P) "$(DESTDIR)$(vglibdir)"
+ @list='$(vglib_DATA)'; test -n "$(vglibdir)" || list=; \
+ for p in $$list; do \
+ if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+ echo "$$d$$p"; \
+ done | $(am__base_list) | \
+ while read files; do \
+ echo " $(INSTALL_DATA) $$files '$(DESTDIR)$(vglibdir)'"; \
+ $(INSTALL_DATA) $$files "$(DESTDIR)$(vglibdir)" || exit $$?; \
+ done
+
+uninstall-vglibDATA:
+ @$(NORMAL_UNINSTALL)
+ @list='$(vglib_DATA)'; test -n "$(vglibdir)" || list=; \
+ files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
+ test -n "$$files" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(vglibdir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(vglibdir)" && rm -f $$files
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+check: $(BUILT_SOURCES)
+ $(MAKE) $(AM_MAKEFLAGS) check-am
+all-am: Makefile $(LIBRARIES) $(PROGRAMS) $(DATA) $(HEADERS) all-local
+installdirs:
+ for dir in "$(DESTDIR)$(pkglibdir)" "$(DESTDIR)$(bindir)" "$(DESTDIR)$(vglibdir)"; do \
+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ done
+install: $(BUILT_SOURCES)
+ $(MAKE) $(AM_MAKEFLAGS) install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+ -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+ -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)
+clean: clean-am
+
+clean-am: clean-binPROGRAMS clean-generic clean-local \
+ clean-noinstPROGRAMS clean-pkglibLIBRARIES mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am: install-vglibDATA
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am: install-binPROGRAMS install-exec-local \
+ install-pkglibLIBRARIES
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am: uninstall-binPROGRAMS uninstall-pkglibLIBRARIES \
+ uninstall-vglibDATA
+
+.MAKE: all check install install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am all-local check check-am clean \
+ clean-binPROGRAMS clean-generic clean-local \
+ clean-noinstPROGRAMS clean-pkglibLIBRARIES ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-binPROGRAMS install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-exec-local \
+ install-html install-html-am install-info install-info-am \
+ install-man install-pdf install-pdf-am install-pkglibLIBRARIES \
+ install-ps install-ps-am install-strip install-vglibDATA \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am uninstall-binPROGRAMS uninstall-pkglibLIBRARIES \
+ uninstall-vglibDATA
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+# Be careful w.r.t. parallel builds. See section 27.9 of the automake info
+# page, "Handling Tools that Produce many Outputs".
+$(abs_builddir)/m_mach:
+ mkdir -p $@
+$(mach_user_srcs): $(mach_defs) $(abs_builddir)/m_mach
+ (cd m_mach && mig $(mach_defs))
+$(mach_hdrs): $(mach_defs) $(mach_user_srcs) $(abs_builddir)/m_mach
+ (cd m_mach && mig $(mach_defs))
+
+#----------------------------------------------------------------------------
+# General stuff
+#----------------------------------------------------------------------------
+
+all-local: inplace-noinst_PROGRAMS inplace-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(vglib_DATA); do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+clean-local: clean-noinst_DSYMS
+
+install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS
+@VGCONF_OS_IS_DARWIN_TRUE@fixup_macho_loadcmds: fixup_macho_loadcmds.c
+@VGCONF_OS_IS_DARWIN_TRUE@ $(CC) -g -Wall -o fixup_macho_loadcmds fixup_macho_loadcmds.c
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/coregrind/launcher-darwin.c b/main/coregrind/launcher-darwin.c
index 9eedcf4..8f8c608 100644
--- a/main/coregrind/launcher-darwin.c
+++ b/main/coregrind/launcher-darwin.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/launcher-linux.c b/main/coregrind/launcher-linux.c
index 4ae7d49..3b7eb66 100644
--- a/main/coregrind/launcher-linux.c
+++ b/main/coregrind/launcher-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -60,10 +60,6 @@
#ifndef EM_X86_64
#define EM_X86_64 62 // elf.h doesn't define this on some older systems
#endif
-#ifndef EM_PPC64
-#define EM_PPC64 21 // elf.h doesn't define this on Android
-#endif
-
/* Report fatal errors */
__attribute__((noreturn))
@@ -183,6 +179,12 @@
ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "arm-linux";
}
+ else
+ if (ehdr->e_machine == EM_MIPS &&
+ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ platform = "mips32-linux";
+ }
}
else if (header[EI_DATA] == ELFDATA2MSB) {
if (ehdr->e_machine == EM_PPC &&
@@ -190,6 +192,12 @@
ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "ppc32-linux";
}
+ else
+ if (ehdr->e_machine == EM_MIPS &&
+ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ platform = "mips32-linux";
+ }
}
} else if (n_bytes >= sizeof(Elf64_Ehdr) && header[EI_CLASS] == ELFCLASS64) {
@@ -288,7 +296,8 @@
(0==strcmp(VG_PLATFORM,"ppc32-linux")) ||
(0==strcmp(VG_PLATFORM,"ppc64-linux")) ||
(0==strcmp(VG_PLATFORM,"arm-linux")) ||
- (0==strcmp(VG_PLATFORM,"s390x-linux")))
+ (0==strcmp(VG_PLATFORM,"s390x-linux")) ||
+ (0==strcmp(VG_PLATFORM,"mips32-linux")))
default_platform = VG_PLATFORM;
else
barf("Unknown VG_PLATFORM '%s'", VG_PLATFORM);
diff --git a/main/coregrind/link_tool_exe.c b/main/coregrind/link_tool_exe.c
deleted file mode 100644
index e69de29..0000000
--- a/main/coregrind/link_tool_exe.c
+++ /dev/null
diff --git a/main/coregrind/link_tool_exe_darwin.in b/main/coregrind/link_tool_exe_darwin.in
index e111738..bf483a9 100644
--- a/main/coregrind/link_tool_exe_darwin.in
+++ b/main/coregrind/link_tool_exe_darwin.in
@@ -98,7 +98,8 @@
die "Not enough arguments"
if (($#ARGV + 1) < 5);
-my $ala = $ARGV[0];
+my $ala = $ARGV[0]; # the load address to use
+my $cc = $ARGV[1]; # the C compiler in use
# check for plausible-ish alt load address
die "Bogus alt-load address (1)"
@@ -140,6 +141,14 @@
my $cmd = "/usr/bin/ld";
$cmd = "$cmd -static";
+
+# If we're building with clang (viz, the C compiler as specified
+# by the 2nd arg ends in "clang"), we also need -new_linker. See
+# https://bugs.kde.org/show_bug.cgi?id=295427
+if ("$cc" =~ /clang$/) {
+ $cmd = "$cmd -new_linker";
+}
+
$cmd = "$cmd -arch $archstr";
$cmd = "$cmd -macosx_version_min 10.5";
$cmd = "$cmd -o $outname";
diff --git a/main/coregrind/link_tool_exe_linux.in b/main/coregrind/link_tool_exe_linux.in
index 6de2562..a47747b 100644
--- a/main/coregrind/link_tool_exe_linux.in
+++ b/main/coregrind/link_tool_exe_linux.in
@@ -68,7 +68,18 @@
# so, build up the complete command here:
# 'cc' -static -Ttext='ala' 'restargs'
-my $cmd="$cc -static -Wl,-Ttext=$ala";
+# For mips we need to use "--section-start=.reginfo=$ala" because
+# "--section-start=.reginfo=$ala" will put all the sections to the
+# specificed address ($ala)
+my $x=`$cc -v 2>&1 | grep Target | sed 's/Target: //g'`;
+my $arch=substr($x, 0, index($x, '-'));
+my $cmd;
+
+if (($arch eq 'mips') || ($arch eq 'mipsel')) {
+ $cmd = "$cc -static -Wl,--section-start=.reginfo=$ala";
+} else {
+ $cmd = "$cc -static -Wl,-Ttext=$ala";
+}
# Add the rest of the parameters
foreach my $n (2 .. $#ARGV) {
diff --git a/main/coregrind/m_aspacehl.c b/main/coregrind/m_aspacehl.c
index dfac89e..e4ae2d1 100644
--- a/main/coregrind/m_aspacehl.c
+++ b/main/coregrind/m_aspacehl.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2011 Julian Seward
+ Copyright (C) 2006-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_aspacemgr/aspacemgr-common.c b/main/coregrind/m_aspacemgr/aspacemgr-common.c
index 7f7717c..07b6303 100644
--- a/main/coregrind/m_aspacemgr/aspacemgr-common.c
+++ b/main/coregrind/m_aspacemgr/aspacemgr-common.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -159,7 +159,7 @@
res = VG_(do_syscall6)(__NR_mmap2, (UWord)start, length,
prot, flags, fd, offset / 4096);
# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \
- || defined(VGP_s390x_linux)
+ || defined(VGP_s390x_linux) || defined(VGP_mips32_linux)
res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length,
prot, flags, fd, offset);
# elif defined(VGP_x86_darwin)
diff --git a/main/coregrind/m_aspacemgr/aspacemgr-linux.c b/main/coregrind/m_aspacemgr/aspacemgr-linux.c
index 04156bb..b56da6a 100644
--- a/main/coregrind/m_aspacemgr/aspacemgr-linux.c
+++ b/main/coregrind/m_aspacemgr/aspacemgr-linux.c
@@ -10,7 +10,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -265,24 +265,10 @@
/* ------ start of STATE for the address-space manager ------ */
/* Max number of segments we can track. */
-/* glider: We keep VG_N_SEGMENTS low on Android, because they occupy
- too much memory. We used to have VG_N_SEGMENTS=10000 on Darwin,
- but it turned out to be too low for Chromium.
-*/
-#if defined(VGO_darwin)
-#define VG_N_SEGMENTS 50000
-#elif defined(ANDROID)
-#define VG_N_SEGMENTS 10000
-#else
-#define VG_N_SEGMENTS 100000
-#endif
+#define VG_N_SEGMENTS 5000
/* Max number of segment file names we can track. */
-#if defined(VGO_darwin) || defined(ANDROID)
#define VG_N_SEGNAMES 1000
-#else
-#define VG_N_SEGNAMES 100000
-#endif
/* Max length of a segment file name. */
#define VG_MAX_SEGNAMELEN 1000
@@ -1065,7 +1051,7 @@
"segment mismatch: V's gap 1st, kernel's 2nd:\n");
show_nsegment_full( 0, i, &nsegments[i] );
VG_(debugLog)(0,"aspacem",
- " : .... %010llx-%010llx %s",
+ " : .... %010llx-%010llx %s\n",
(ULong)start, (ULong)end, len_buf);
return;
}
@@ -1663,7 +1649,7 @@
aspacem_minAddr = (Addr) 0x04000000; // 64M
# if VG_WORDSIZE == 8
- aspacem_maxAddr = (Addr)0x8000000000 - 1; // 512G
+ aspacem_maxAddr = (Addr)0x800000000 - 1; // 32G
# ifdef ENABLE_INNER
{ Addr cse = VG_PGROUNDDN( sp_at_startup ) - 1;
if (aspacem_maxAddr > cse)
@@ -1675,7 +1661,8 @@
# endif
aspacem_cStart = aspacem_minAddr; // 64M
- aspacem_vStart = VG_PGROUNDUP((aspacem_minAddr + aspacem_maxAddr + 1) / 2);
+ aspacem_vStart = VG_PGROUNDUP(aspacem_minAddr
+ + (aspacem_maxAddr - aspacem_minAddr + 1) / 2);
# ifdef ENABLE_INNER
aspacem_vStart -= 0x10000000; // 256M
# endif
@@ -1995,7 +1982,29 @@
mreq.rkind = start==0 ? MAny : MFixed;
mreq.start = start;
mreq.len = len;
- return VG_(am_get_advisory)( &mreq, True/*client*/, ok );
+ return VG_(am_get_advisory)( &mreq, True/*forClient*/, ok );
+}
+
+/* Similar to VG_(am_find_nsegment) but only returns free segments. */
+static NSegment const * VG_(am_find_free_nsegment) ( Addr a )
+{
+ Int i = find_nsegment_idx(a);
+ aspacem_assert(i >= 0 && i < nsegments_used);
+ aspacem_assert(nsegments[i].start <= a);
+ aspacem_assert(a <= nsegments[i].end);
+ if (nsegments[i].kind == SkFree)
+ return &nsegments[i];
+ else
+ return NULL;
+}
+
+Bool VG_(am_covered_by_single_free_segment)
+ ( Addr start, SizeT len)
+{
+ NSegment const* segLo = VG_(am_find_free_nsegment)( start );
+ NSegment const* segHi = VG_(am_find_free_nsegment)( start + len - 1 );
+
+ return segLo != NULL && segHi != NULL && segLo == segHi;
}
@@ -2046,41 +2055,6 @@
return needDiscard;
}
-Bool
-VG_(am_notify_fake_client_mmap)( Addr a, SizeT len, UInt prot, UInt flags,
- HChar* fileName, Off64T offset )
-{
- HChar buf[VKI_PATH_MAX];
- ULong dev, ino;
- UInt mode;
- NSegment seg;
- Bool needDiscard;
-
- aspacem_assert(len > 0);
- aspacem_assert(VG_IS_PAGE_ALIGNED(a));
- aspacem_assert(VG_IS_PAGE_ALIGNED(len));
- aspacem_assert(VG_IS_PAGE_ALIGNED(offset));
-
- /* Discard is needed if any of the just-trashed range had T. */
- needDiscard = any_Ts_in_range( a, len );
-
- init_nsegment( &seg );
- seg.kind = (flags & VKI_MAP_ANONYMOUS) ? SkAnonC : SkFileC;
- seg.start = a;
- seg.end = a + len - 1;
- seg.hasR = toBool(prot & VKI_PROT_READ);
- seg.hasW = toBool(prot & VKI_PROT_WRITE);
- seg.hasX = toBool(prot & VKI_PROT_EXEC);
- if (!(flags & VKI_MAP_ANONYMOUS)) {
- // Nb: We ignore offset requests in anonymous mmaps (see bug #126722)
- seg.offset = offset;
- seg.fnIdx = allocate_segname( fileName );
- }
- add_segment( &seg );
- AM_SANITY_CHECK;
- return needDiscard;
-}
-
/* Notifies aspacem that the client completed a shmat successfully.
The segment array is updated accordingly. If the returned Bool is
True, the caller should immediately discard translations from the
@@ -2256,7 +2230,7 @@
req.rkind = MFixed;
req.start = start;
req.len = length;
- advised = VG_(am_get_advisory)( &req, True/*client*/, &ok );
+ advised = VG_(am_get_advisory)( &req, True/*forClient*/, &ok );
if (!ok || advised != start)
return VG_(mk_SysRes_Error)( VKI_EINVAL );
@@ -2325,7 +2299,7 @@
req.rkind = MFixed;
req.start = start;
req.len = length;
- advised = VG_(am_get_advisory)( &req, True/*client*/, &ok );
+ advised = VG_(am_get_advisory)( &req, True/*forClient*/, &ok );
if (!ok || advised != start)
return VG_(mk_SysRes_Error)( VKI_EINVAL );
@@ -2383,7 +2357,7 @@
req.rkind = MAny;
req.start = 0;
req.len = length;
- advised = VG_(am_get_advisory)( &req, True/*client*/, &ok );
+ advised = VG_(am_get_advisory)( &req, True/*forClient*/, &ok );
if (!ok)
return VG_(mk_SysRes_Error)( VKI_EINVAL );
@@ -2457,7 +2431,7 @@
req.rkind = MAny;
req.start = 0;
req.len = length;
- advised = VG_(am_get_advisory)( &req, False/*valgrind*/, &ok );
+ advised = VG_(am_get_advisory)( &req, False/*forClient*/, &ok );
if (!ok)
return VG_(mk_SysRes_Error)( VKI_EINVAL );
@@ -2537,12 +2511,11 @@
/* Map a file at an unconstrained address for V, and update the
- segment array accordingly. This is used by V for transiently
segment array accordingly. Use the provided flags */
-SysRes VG_(am_mmap_file_float_valgrind_flags) ( SizeT length, UInt prot,
- UInt flags,
- Int fd, Off64T offset )
+static SysRes VG_(am_mmap_file_float_valgrind_flags) ( SizeT length, UInt prot,
+ UInt flags,
+ Int fd, Off64T offset )
{
SysRes sres;
NSegment seg;
@@ -2560,10 +2533,22 @@
/* Ask for an advisory. If it's negative, fail immediately. */
req.rkind = MAny;
req.start = 0;
- req.len = length;
- advised = VG_(am_get_advisory)( &req, True/*client*/, &ok );
+ #if defined(VGA_arm) || defined(VGA_mips32)
+ aspacem_assert(VKI_SHMLBA >= VKI_PAGE_SIZE);
+ #else
+ aspacem_assert(VKI_SHMLBA == VKI_PAGE_SIZE);
+ #endif
+ if ((VKI_SHMLBA > VKI_PAGE_SIZE) && (VKI_MAP_SHARED & flags)) {
+ /* arm-linux only. See ML_(generic_PRE_sys_shmat) and bug 290974 */
+ req.len = length + VKI_SHMLBA - VKI_PAGE_SIZE;
+ } else {
+ req.len = length;
+ }
+ advised = VG_(am_get_advisory)( &req, False/*forClient*/, &ok );
if (!ok)
return VG_(mk_SysRes_Error)( VKI_EINVAL );
+ if ((VKI_SHMLBA > VKI_PAGE_SIZE) && (VKI_MAP_SHARED & flags))
+ advised = VG_ROUNDUP(advised, VKI_SHMLBA);
/* We have been advised that the mapping is allowable at the
specified address. So hand it off to the kernel, and propagate
@@ -2571,7 +2556,7 @@
sres = VG_(am_do_mmap_NO_NOTIFY)(
advised, length, prot,
flags,
- fd, offset
+ fd, offset
);
if (sr_isError(sres))
return sres;
@@ -2580,10 +2565,8 @@
/* I don't think this can happen. It means the kernel made a
fixed map succeed but not at the requested location. Try to
repair the damage, then return saying the mapping failed. */
- /*TODO(kcc): it apprers this may actually happen if allocating
- in hugetlbfs. No idea why. */
-// (void)ML_(am_do_munmap_NO_NOTIFY)( sr_Res(sres), length );
-// return VG_(mk_SysRes_Error)( VKI_EINVAL );
+ (void)ML_(am_do_munmap_NO_NOTIFY)( sr_Res(sres), length );
+ return VG_(mk_SysRes_Error)( VKI_EINVAL );
}
/* Ok, the mapping succeeded. Now notify the interval map. */
@@ -2608,7 +2591,6 @@
AM_SANITY_CHECK;
return sres;
}
-
/* Map privately a file at an unconstrained address for V, and update the
segment array accordingly. This is used by V for transiently
mapping in object files to read their debug info. */
@@ -2621,7 +2603,7 @@
fd, offset );
}
-extern SysRes VG_(am_shared_mmap_file_float_valgrind)
+SysRes VG_(am_shared_mmap_file_float_valgrind)
( SizeT length, UInt prot, Int fd, Off64T offset )
{
return VG_(am_mmap_file_float_valgrind_flags) (length, prot,
@@ -3172,7 +3154,7 @@
{
Int n = 0;
*val = 0;
- while (hexdigit(*buf) >= 0) {
+ while (decdigit(*buf) >= 0) {
*val = (*val * 10) + decdigit(*buf);
n++; buf++;
}
@@ -3330,19 +3312,21 @@
read_line_ok:
- /* Try and find the name of the file mapped to this segment, if
- it exists. Note that files can contains spaces. */
+ aspacem_assert(i < buf_n_tot);
- // Move i to the next non-space char, which should be either a '/' or
- // a newline.
- while (procmap_buf[i] == ' ' && i < buf_n_tot-1) i++;
+ /* Try and find the name of the file mapped to this segment, if
+ it exists. Note that file names can contain spaces. */
+
+ // Move i to the next non-space char, which should be either a '/',
+ // a '[', or a newline.
+ while (procmap_buf[i] == ' ') i++;
// Move i_eol to the end of the line.
i_eol = i;
- while (procmap_buf[i_eol] != '\n' && i_eol < buf_n_tot-1) i_eol++;
+ while (procmap_buf[i_eol] != '\n') i_eol++;
// If there's a filename...
- if (i < i_eol-1 && procmap_buf[i] == '/') {
+ if (procmap_buf[i] == '/') {
/* Minor hack: put a '\0' at the filename end for the call to
'record_mapping', then restore the old char with 'tmp'. */
filename = &procmap_buf[i];
@@ -3497,12 +3481,23 @@
static Int css_size_local;
static Int css_used_local;
+static Addr Addr__max ( Addr a, Addr b ) { return a > b ? a : b; }
+static Addr Addr__min ( Addr a, Addr b ) { return a < b ? a : b; }
+
static void add_mapping_callback(Addr addr, SizeT len, UInt prot,
ULong dev, ULong ino, Off64T offset,
const UChar *filename)
{
// derived from sync_check_mapping_callback()
+ /* JRS 2012-Mar-07: this all seems very dubious to me. It would be
+ safer to see if we can find, in V's segment collection, one
+ single segment that completely covers the range [addr, +len)
+ (and possibly more), and that has the exact same other
+ properties (prot, dev, ino, offset, etc) as the data presented
+ here. If found, we just skip. Otherwise add the data presented
+ here into css_local[]. */
+
Int iLo, iHi, i;
if (len == 0) return;
@@ -3513,7 +3508,6 @@
iLo = find_nsegment_idx( addr );
iHi = find_nsegment_idx( addr + len - 1 );
-
/* NSegments iLo .. iHi inclusive should agree with the presented
data. */
for (i = iLo; i <= iHi; i++) {
@@ -3525,7 +3519,7 @@
continue;
}
else if (nsegments[i].kind == SkFree || nsegments[i].kind == SkResvn) {
- /* Add mapping for SkResvn regions */
+ /* Add mapping for SkResvn regions */
ChangedSeg* cs = &css_local[css_used_local];
if (css_used_local < css_size_local) {
cs->is_added = True;
@@ -3586,20 +3580,28 @@
/* NSegments iLo .. iHi inclusive should agree with the presented data. */
for (i = iLo; i <= iHi; i++) {
- if (nsegments[i].kind != SkFree && nsegments[i].kind != SkResvn) {
- // V has a mapping, kernel doesn't
+ if (nsegments[i].kind != SkFree && nsegments[i].kind != SkResvn) {
+ /* V has a mapping, kernel doesn't. Add to css_local[],
+ directives to chop off the part of the V mapping that
+ falls within the gap that the kernel tells us is
+ present. */
ChangedSeg* cs = &css_local[css_used_local];
if (css_used_local < css_size_local) {
cs->is_added = False;
- cs->start = nsegments[i].start;
- cs->end = nsegments[i].end;
+ cs->start = Addr__max(nsegments[i].start, addr);
+ cs->end = Addr__min(nsegments[i].end, addr + len - 1);
+ aspacem_assert(VG_IS_PAGE_ALIGNED(cs->start));
+ aspacem_assert(VG_IS_PAGE_ALIGNED(cs->end+1));
+ /* I don't think the following should fail. But if it
+ does, just omit the css_used_local++ in the cases where
+ it doesn't hold. */
+ aspacem_assert(cs->start < cs->end);
cs->prot = 0;
cs->offset = 0;
css_used_local++;
} else {
css_overflowed = True;
}
- return;
}
}
}
diff --git a/main/coregrind/m_aspacemgr/priv_aspacemgr.h b/main/coregrind/m_aspacemgr/priv_aspacemgr.h
index ade252e..daa2d8c 100644
--- a/main/coregrind/m_aspacemgr/priv_aspacemgr.h
+++ b/main/coregrind/m_aspacemgr/priv_aspacemgr.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_clientstate.c b/main/coregrind/m_clientstate.c
index 6b9d710..8c18c5a 100644
--- a/main/coregrind/m_clientstate.c
+++ b/main/coregrind/m_clientstate.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_commandline.c b/main/coregrind/m_commandline.c
index 76f22a9..64133a3 100644
--- a/main/coregrind/m_commandline.c
+++ b/main/coregrind/m_commandline.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_coredump/coredump-elf.c b/main/coregrind/m_coredump/coredump-elf.c
index 9b4beb7..42a1965 100644
--- a/main/coregrind/m_coredump/coredump-elf.c
+++ b/main/coregrind/m_coredump/coredump-elf.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -136,6 +136,17 @@
phdr->p_align = VKI_PAGE_SIZE;
}
+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
+/* Android's libc doesn't provide a definition for this. Hence: */
+typedef
+ struct {
+ Elf32_Word n_namesz;
+ Elf32_Word n_descsz;
+ Elf32_Word n_type;
+ }
+ Elf32_Nhdr;
+#endif
+
struct note {
struct note *next;
ESZ(Nhdr) note;
@@ -148,7 +159,7 @@
+ VG_ROUNDUP(n->note.n_descsz, 4);
}
-#if !defined(VGPV_arm_linux_android)
+#if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android)
static void add_note(struct note **list, const Char *name, UInt type,
const void *data, UInt datasz)
{
@@ -170,7 +181,7 @@
VG_(memcpy)(n->name, name, namelen);
VG_(memcpy)(n->name+VG_ROUNDUP(namelen,4), data, datasz);
}
-#endif /* !defined(VGPV_arm_linux_android) */
+#endif /* !defined(VGPV_*_linux_android) */
static void write_note(Int fd, const struct note *n)
{
@@ -364,6 +375,15 @@
DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
# undef DO
regs->orig_gpr2 = arch->vex.guest_r2;
+#elif defined(VGP_mips32_linux)
+# define DO(n) regs->MIPS_r##n = arch->vex.guest_r##n
+ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
+ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
+ DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
+ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
+# undef DO
+ regs->MIPS_hi = arch->vex.guest_HI;
+ regs->MIPS_lo = arch->vex.guest_LO;
#else
# error Unknown ELF platform
#endif
@@ -406,7 +426,8 @@
//:: fpu->mxcsr_mask = ?;
//:: fpu->st_space = ?;
-# define DO(n) VG_(memcpy)(fpu->xmm_space + n * 4, &arch->vex.guest_XMM##n, sizeof(arch->vex.guest_XMM##n))
+# define DO(n) VG_(memcpy)(fpu->xmm_space + n * 4, \
+ &arch->vex.guest_YMM##n[0], 16)
DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
# undef DO
@@ -443,12 +464,19 @@
DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
# undef DO
+#elif defined(VGP_mips32_linux)
+# define DO(n) (*fpu)[n] = *(double*)(&arch->vex.guest_f##n)
+ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
+ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
+ DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
+ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
+# undef DO
#else
# error Unknown ELF platform
#endif
}
-#if defined(VGP_x86_linux)
+#if defined(VGP_x86_linux) && !defined(VGPV_x86_linux_android)
static void fill_xfpu(const ThreadState *tst, vki_elf_fpxregset_t *xfpu)
{
ThreadArchState* arch = (ThreadArchState*)&tst->arch;
@@ -561,12 +589,14 @@
continue;
# if defined(VGP_x86_linux)
+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android)
{
vki_elf_fpxregset_t xfpu;
fill_xfpu(&VG_(threads)[i], &xfpu);
add_note(¬elist, "LINUX", NT_PRXFPREG, &xfpu, sizeof(xfpu));
}
# endif
+# endif
fill_fpu(&VG_(threads)[i], &fpu);
# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android)
diff --git a/main/coregrind/m_cpuid.S b/main/coregrind/m_cpuid.S
index 1942fb8..6ffa6e0 100644
--- a/main/coregrind/m_cpuid.S
+++ b/main/coregrind/m_cpuid.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_debugger.c b/main/coregrind/m_debugger.c
index bb559f4..4fc636a 100644
--- a/main/coregrind/m_debugger.c
+++ b/main/coregrind/m_debugger.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -307,6 +307,43 @@
return VG_(ptrace)(VKI_PTRACE_POKEUSR_AREA, pid, &pa, NULL);
+#elif defined(VGP_mips32_linux)
+ struct vki_user_regs_struct regs;
+ VG_(memset)(®s, 0, sizeof(regs));
+ regs.MIPS_r0 = vex->guest_r0;
+ regs.MIPS_r1 = vex->guest_r1;
+ regs.MIPS_r2 = vex->guest_r2;
+ regs.MIPS_r3 = vex->guest_r3;
+ regs.MIPS_r4 = vex->guest_r4;
+ regs.MIPS_r5 = vex->guest_r5;
+ regs.MIPS_r6 = vex->guest_r6;
+ regs.MIPS_r7 = vex->guest_r7;
+ regs.MIPS_r8 = vex->guest_r8;
+ regs.MIPS_r9 = vex->guest_r9;
+ regs.MIPS_r10 = vex->guest_r10;
+ regs.MIPS_r11 = vex->guest_r11;
+ regs.MIPS_r12 = vex->guest_r12;
+ regs.MIPS_r13 = vex->guest_r13;
+ regs.MIPS_r14 = vex->guest_r14;
+ regs.MIPS_r15 = vex->guest_r15;
+ regs.MIPS_r16 = vex->guest_r16;
+ regs.MIPS_r17 = vex->guest_r17;
+ regs.MIPS_r18 = vex->guest_r18;
+ regs.MIPS_r19 = vex->guest_r19;
+ regs.MIPS_r20 = vex->guest_r20;
+ regs.MIPS_r21 = vex->guest_r21;
+ regs.MIPS_r22 = vex->guest_r22;
+ regs.MIPS_r23 = vex->guest_r23;
+ regs.MIPS_r24 = vex->guest_r24;
+ regs.MIPS_r25 = vex->guest_r25;
+ regs.MIPS_r26 = vex->guest_r26;
+ regs.MIPS_r27 = vex->guest_r27;
+ regs.MIPS_r28 = vex->guest_r28;
+ regs.MIPS_r29 = vex->guest_r29;
+ regs.MIPS_r30 = vex->guest_r30;
+ regs.MIPS_r31 = vex->guest_r31;
+ return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, ®s);
+
#else
# error Unknown arch
#endif
diff --git a/main/coregrind/m_debuginfo/d3basics.c b/main/coregrind/m_debuginfo/d3basics.c
index 540cd30..e6f6c7d 100644
--- a/main/coregrind/m_debuginfo/d3basics.c
+++ b/main/coregrind/m_debuginfo/d3basics.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks LLP
+ Copyright (C) 2008-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -53,8 +53,8 @@
switch (hashch) {
case DW_children_no: return "no children";
case DW_children_yes: return "has children";
- default: return "DW_children_???";
}
+ return "DW_children_???";
}
HChar* ML_(pp_DW_TAG) ( DW_TAG tag )
@@ -148,8 +148,8 @@
case DW_TAG_PGI_kanji_type: return "DW_TAG_PGI_kanji_type";
case DW_TAG_PGI_interface_block:
return "DW_TAG_PGI_interface_block";
- default: return "DW_TAG_???";
}
+ return "DW_TAG_???";
}
HChar* ML_(pp_DW_FORM) ( DW_FORM form )
@@ -180,8 +180,10 @@
case DW_FORM_exprloc: return "DW_FORM_exprloc";
case DW_FORM_flag_present:return "DW_FORM_flag_present";
case DW_FORM_ref_sig8: return "DW_FORM_ref_sig8";
- default: return "DW_FORM_???";
+ case DW_FORM_GNU_ref_alt:return "DW_FORM_GNU_ref_alt";
+ case DW_FORM_GNU_strp_alt:return "DW_FORM_GNU_strp_alt";
}
+ return "DW_FORM_???";
}
HChar* ML_(pp_DW_AT) ( DW_AT attr )
@@ -328,8 +330,8 @@
case DW_AT_PGI_lbase: return "DW_AT_PGI_lbase";
case DW_AT_PGI_soffset: return "DW_AT_PGI_soffset";
case DW_AT_PGI_lstride: return "DW_AT_PGI_lstride";
- default: return "DW_AT_???";
}
+ return "DW_AT_???";
}
@@ -410,6 +412,9 @@
# elif defined(VGP_s390x_linux)
if (regno == 15) { *a = regs->sp; return True; }
if (regno == 11) { *a = regs->fp; return True; }
+# elif defined(VGP_mips32_linux)
+ if (regno == 29) { *a = regs->sp; return True; }
+ if (regno == 30) { *a = regs->fp; return True; }
# else
# error "Unknown platform"
# endif
diff --git a/main/coregrind/m_debuginfo/debuginfo.c b/main/coregrind/m_debuginfo/debuginfo.c
index 4aef3db..218547b 100644
--- a/main/coregrind/m_debuginfo/debuginfo.c
+++ b/main/coregrind/m_debuginfo/debuginfo.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -178,6 +178,9 @@
di = ML_(dinfo_zalloc)("di.debuginfo.aDI.1", sizeof(DebugInfo));
di->handle = handle_counter++;
di->fsm.filename = ML_(dinfo_strdup)("di.debuginfo.aDI.2", filename);
+ di->fsm.maps = VG_(newXA)(
+ ML_(dinfo_zalloc), "di.debuginfo.aDI.3",
+ ML_(dinfo_free), sizeof(struct _DebugInfoMapping));
/* Everything else -- pointers, sizes, arrays -- is zeroed by
ML_(dinfo_zalloc). Now set up the debugging-output flags. */
@@ -204,7 +207,9 @@
GExpr* gexpr;
vg_assert(di != NULL);
+ if (di->fsm.maps) VG_(deleteXA)(di->fsm.maps);
if (di->fsm.filename) ML_(dinfo_free)(di->fsm.filename);
+ if (di->soname) ML_(dinfo_free)(di->soname);
if (di->loctab) ML_(dinfo_free)(di->loctab);
if (di->cfsi) ML_(dinfo_free)(di->cfsi);
if (di->cfsi_exprs) VG_(deleteXA)(di->cfsi_exprs);
@@ -384,32 +389,20 @@
}
-/* Do the basic rx_ and rw_ mappings of the two DebugInfos overlap in
- any way? */
+/* Do the basic mappings of the two DebugInfos overlap in any way? */
static Bool do_DebugInfos_overlap ( DebugInfo* di1, DebugInfo* di2 )
{
+ Word i, j;
vg_assert(di1);
vg_assert(di2);
-
- if (di1->fsm.have_rx_map && di2->fsm.have_rx_map
- && ranges_overlap(di1->fsm.rx_map_avma, di1->fsm.rx_map_size,
- di2->fsm.rx_map_avma, di2->fsm.rx_map_size))
- return True;
-
- if (di1->fsm.have_rx_map && di2->fsm.have_rw_map
- && ranges_overlap(di1->fsm.rx_map_avma, di1->fsm.rx_map_size,
- di2->fsm.rw_map_avma, di2->fsm.rw_map_size))
- return True;
-
- if (di1->fsm.have_rw_map && di2->fsm.have_rx_map
- && ranges_overlap(di1->fsm.rw_map_avma, di1->fsm.rw_map_size,
- di2->fsm.rx_map_avma, di2->fsm.rx_map_size))
- return True;
-
- if (di1->fsm.have_rw_map && di2->fsm.have_rw_map
- && ranges_overlap(di1->fsm.rw_map_avma, di1->fsm.rw_map_size,
- di2->fsm.rw_map_avma, di2->fsm.rw_map_size))
- return True;
+ for (i = 0; i < VG_(sizeXA)(di1->fsm.maps); i++) {
+ struct _DebugInfoMapping* map1 = VG_(indexXA)(di1->fsm.maps, i);
+ for (j = 0; j < VG_(sizeXA)(di2->fsm.maps); j++) {
+ struct _DebugInfoMapping* map2 = VG_(indexXA)(di2->fsm.maps, j);
+ if (ranges_overlap(map1->avma, map1->size, map2->avma, map2->size))
+ return True;
+ }
+ }
return False;
}
@@ -440,8 +433,7 @@
/* Discard any elements of debugInfo_list which overlap with diRef.
- Clearly diRef must have its rx_ and rw_ mapping information set to
- something sane. */
+ Clearly diRef must have its mapping information set to something sane. */
static void discard_DebugInfos_which_overlap_with ( DebugInfo* diRef )
{
DebugInfo* di;
@@ -489,41 +481,67 @@
static void check_CFSI_related_invariants ( DebugInfo* di )
{
DebugInfo* di2 = NULL;
+ Bool has_nonempty_rx = False;
+ Bool cfsi_fits = False;
+ Word i, j;
vg_assert(di);
/* This fn isn't called until after debuginfo for this object has
been successfully read. And that shouldn't happen until we have
both a r-x and rw- mapping for the object. Hence: */
vg_assert(di->fsm.have_rx_map);
vg_assert(di->fsm.have_rw_map);
- /* degenerate case: r-x section is empty */
- if (di->fsm.rx_map_size == 0) {
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ /* We are interested in r-x mappings only */
+ if (!map->rx)
+ continue;
+
+ /* degenerate case: r-x section is empty */
+ if (map->size == 0)
+ continue;
+ has_nonempty_rx = True;
+
+ /* normal case: r-x section is nonempty */
+ /* invariant (0) */
+ vg_assert(map->size > 0);
+
+ /* invariant (1) */
+ for (di2 = debugInfo_list; di2; di2 = di2->next) {
+ if (di2 == di)
+ continue;
+ for (j = 0; j < VG_(sizeXA)(di2->fsm.maps); j++) {
+ struct _DebugInfoMapping* map2 = VG_(indexXA)(di2->fsm.maps, j);
+ if (!map2->rx || map2->size == 0)
+ continue;
+ vg_assert(!ranges_overlap(map->avma, map->size,
+ map2->avma, map2->size));
+ }
+ }
+ di2 = NULL;
+
+ /* invariant (2) */
+ if (di->cfsi) {
+ vg_assert(di->cfsi_minavma <= di->cfsi_maxavma); /* duh! */
+ /* Assume the csfi fits completely into one individual mapping
+ for now. This might need to be improved/reworked later. */
+ if (di->cfsi_minavma >= map->avma &&
+ di->cfsi_maxavma < map->avma + map->size)
+ cfsi_fits = True;
+ }
+ }
+
+ /* degenerate case: all r-x sections are empty */
+ if (!has_nonempty_rx) {
vg_assert(di->cfsi == NULL);
return;
}
- /* normal case: r-x section is nonempty */
- /* invariant (0) */
- vg_assert(di->fsm.rx_map_size > 0);
- /* invariant (1) */
- for (di2 = debugInfo_list; di2; di2 = di2->next) {
- if (di2 == di)
- continue;
- if (di2->fsm.rx_map_size == 0)
- continue;
- vg_assert(
- di->fsm.rx_map_avma + di->fsm.rx_map_size <= di2->fsm.rx_map_avma
- || di2->fsm.rx_map_avma + di2->fsm.rx_map_size <= di->fsm.rx_map_avma
- );
- }
- di2 = NULL;
- /* invariant (2) */
- if (di->cfsi) {
- vg_assert(di->cfsi_minavma <= di->cfsi_maxavma); /* duh! */
- vg_assert(di->cfsi_minavma >= di->fsm.rx_map_avma);
- vg_assert(di->cfsi_maxavma < di->fsm.rx_map_avma + di->fsm.rx_map_size);
- }
+
+ /* invariant (2) - cont. */
+ if (di->cfsi)
+ vg_assert(cfsi_fits);
+
/* invariants (3) and (4) */
if (di->cfsi) {
- Word i;
vg_assert(di->cfsi_used > 0);
vg_assert(di->cfsi_size > 0);
for (i = 0; i < di->cfsi_used; i++) {
@@ -600,9 +618,9 @@
TRACE_SYMTAB("\n");
/* We're going to read symbols and debug info for the avma
- ranges [rx_map_avma, +rx_map_size) and [rw_map_avma,
- +rw_map_size). First get rid of any other DebugInfos which
- overlap either of those ranges (to avoid total confusion). */
+ ranges specified in the _DebugInfoFsm mapping array. First
+ get rid of any other DebugInfos which overlap any of those
+ ranges (to avoid total confusion). */
discard_DebugInfos_which_overlap_with( di );
/* .. and acquire new info. */
@@ -726,9 +744,6 @@
if (sr_isError(statres)) {
DebugInfo fake_di;
Bool quiet = VG_(strstr)(filename, "/var/run/nscd/") != NULL;
-#ifdef ANDROID
- quiet |= VG_(strstr)(filename, "/dev/__properties__") != NULL;
-#endif
if (!quiet && VG_(clo_verbosity) > 1) {
VG_(memset)(&fake_di, 0, sizeof(fake_di));
fake_di.fsm.filename = filename;
@@ -794,7 +809,7 @@
is_rw_map = False;
is_ro_map = False;
-# if defined(VGA_x86) || defined(VGA_ppc32)
+# if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_mips32)
is_rx_map = seg->hasR && seg->hasX;
is_rw_map = seg->hasR && seg->hasW;
# elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_arm)
@@ -862,7 +877,7 @@
/* We're only interested in mappings of object files. */
# if defined(VGO_linux)
- if (!ML_(is_elf_object_file)( buf1k, (SizeT)sr_Res(preadres) ))
+ if (!ML_(is_elf_object_file)( buf1k, (SizeT)sr_Res(preadres), False ))
return 0;
# elif defined(VGO_darwin)
if (!ML_(is_macho_object_file)( buf1k, (SizeT)sr_Res(preadres) ))
@@ -876,41 +891,20 @@
di = find_or_create_DebugInfo_for( filename );
vg_assert(di);
- if (is_rx_map) {
- /* We have a text-like mapping. Note the details. */
- if (!di->fsm.have_rx_map) {
- di->fsm.have_rx_map = True;
- di->fsm.rx_map_avma = a;
- di->fsm.rx_map_size = seg->end + 1 - seg->start;
- di->fsm.rx_map_foff = seg->offset;
- } else {
- /* FIXME: complain about a second text-like mapping */
- }
- }
+ /* Note the details about the mapping. */
+ struct _DebugInfoMapping map;
+ map.avma = a;
+ map.size = seg->end + 1 - seg->start;
+ map.foff = seg->offset;
+ map.rx = is_rx_map;
+ map.rw = is_rw_map;
+ map.ro = is_ro_map;
+ VG_(addToXA)(di->fsm.maps, &map);
- if (is_rw_map) {
- /* We have a data-like mapping. Note the details. */
- if (!di->fsm.have_rw_map) {
- di->fsm.have_rw_map = True;
- di->fsm.rw_map_avma = a;
- di->fsm.rw_map_size = seg->end + 1 - seg->start;
- di->fsm.rw_map_foff = seg->offset;
- } else {
- /* FIXME: complain about a second data-like mapping */
- }
- }
-
- if (is_ro_map) {
- /* We have a r-- mapping. Note the details (OSX 10.7, 32-bit only) */
- if (!di->fsm.have_ro_map) {
- di->fsm.have_ro_map = True;
- di->fsm.ro_map_avma = a;
- di->fsm.ro_map_size = seg->end + 1 - seg->start;
- di->fsm.ro_map_foff = seg->offset;
- } else {
- /* FIXME: complain about a second r-- mapping */
- }
- }
+ /* Update flags about what kind of mappings we've already seen. */
+ di->fsm.have_rx_map |= is_rx_map;
+ di->fsm.have_rw_map |= is_rw_map;
+ di->fsm.have_ro_map |= is_ro_map;
/* So, finally, are we in an accept state? */
if (di->fsm.have_rx_map && di->fsm.have_rw_map && !di->have_dinfo) {
@@ -962,7 +956,7 @@
void VG_(di_notify_vm_protect)( Addr a, SizeT len, UInt prot )
{
Bool do_nothing = True;
-# if defined(VGP_x86_darwin) && DARWIN_VERS == DARWIN_10_7
+# if defined(VGP_x86_darwin) && (DARWIN_VERS == DARWIN_10_7 || DARWIN_VERS == DARWIN_10_8)
do_nothing = False;
# endif
if (do_nothing /* wrong platform */)
@@ -979,6 +973,8 @@
is found, conclude we're in an accept state and read debuginfo
accordingly. */
DebugInfo* di;
+ struct _DebugInfoMapping *map = NULL;
+ Word i;
for (di = debugInfo_list; di; di = di->next) {
vg_assert(di->fsm.filename);
if (di->have_dinfo)
@@ -989,36 +985,45 @@
continue; /* rx- mapping already exists */
if (!di->fsm.have_rw_map)
continue; /* need to have a rw- mapping */
- if (di->fsm.ro_map_avma != a || di->fsm.ro_map_size != len)
- continue; /* this isn't an upgrade of the r-- mapping */
+ /* Try to find a mapping matching the memory area. */
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ map = (struct _DebugInfoMapping*)VG_(indexXA)(di->fsm.maps, i);
+ if (map->ro && map->avma == a && map->size == len)
+ break;
+ map = NULL;
+ }
+ if (!map)
+ continue; /* this isn't an upgrade of an r-- mapping */
/* looks like we're in luck! */
break;
}
if (di == NULL)
return; /* didn't find anything */
- /* Do the upgrade. Copy the RO map info into the RX map info and
- pretend we never saw the RO map at all. */
- vg_assert(di->fsm.have_rw_map);
+ /* Do the upgrade. Simply update the flags of the mapping
+ and pretend we never saw the RO map at all. */
vg_assert(di->fsm.have_ro_map);
- vg_assert(!di->fsm.have_rx_map);
-
+ map->rx = True;
+ map->ro = False;
di->fsm.have_rx_map = True;
- di->fsm.rx_map_avma = di->fsm.ro_map_avma;
- di->fsm.rx_map_size = di->fsm.ro_map_size;
- di->fsm.rx_map_foff = di->fsm.ro_map_foff;
-
di->fsm.have_ro_map = False;
- di->fsm.ro_map_avma = 0;
- di->fsm.ro_map_size = 0;
- di->fsm.ro_map_foff = 0;
+ /* See if there are any more ro mappings */
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ map = (struct _DebugInfoMapping*)VG_(indexXA)(di->fsm.maps, i);
+ if (map->ro) {
+ di->fsm.have_ro_map = True;
+ break;
+ }
+ }
- /* And since we're now in an accept state, read debuginfo. Finally. */
- ULong di_handle __attribute__((unused))
- = di_notify_ACHIEVE_ACCEPT_STATE( di );
- /* di_handle is ignored. That's not a problem per se -- it just
- means nobody will ever be able to refer to this debuginfo by
- handle since nobody will know what the handle value is. */
+ /* Check if we're now in an accept state and read debuginfo. Finally. */
+ if (di->fsm.have_rx_map && di->fsm.have_rw_map && !di->have_dinfo) {
+ ULong di_handle __attribute__((unused))
+ = di_notify_ACHIEVE_ACCEPT_STATE( di );
+ /* di_handle is ignored. That's not a problem per se -- it just
+ means nobody will ever be able to refer to this debuginfo by
+ handle since nobody will know what the handle value is. */
+ }
}
@@ -1026,8 +1031,7 @@
/* this should really return ULong, as per VG_(di_notify_mmap). */
void VG_(di_notify_pdb_debuginfo)( Int fd_obj, Addr avma_obj,
- SizeT total_size,
- PtrdiffT unknown_purpose__reloc )
+ SizeT total_size, PtrdiffT bias_obj )
{
Int i, r, sz_exename;
ULong obj_mtime, pdb_mtime;
@@ -1043,8 +1047,8 @@
VG_(message)(Vg_UserMsg, "\n");
VG_(message)(Vg_UserMsg,
"LOAD_PDB_DEBUGINFO: clreq: fd=%d, avma=%#lx, total_size=%lu, "
- "uu_reloc=%#lx\n",
- fd_obj, avma_obj, total_size, unknown_purpose__reloc
+ "bias=%#lx\n",
+ fd_obj, avma_obj, total_size, bias_obj
);
}
@@ -1103,8 +1107,8 @@
*/
Int mashedSzB = VG_(strlen)(pdbname) + VG_(strlen)(wpfx) + 50/*misc*/;
HChar* mashed = ML_(dinfo_zalloc)("di.debuginfo.dnpdi.1", mashedSzB);
- VG_(sprintf)(mashed, "%s/drive_%c%s",
- wpfx, VG_(tolower)(pdbname[0]), &pdbname[2]);
+ VG_(snprintf)(mashed, mashedSzB, "%s/drive_%c%s",
+ wpfx, pdbname[0], &pdbname[2]);
vg_assert(mashed[mashedSzB-1] == 0);
ML_(dinfo_free)(pdbname);
pdbname = mashed;
@@ -1115,8 +1119,8 @@
*/
Int mashedSzB = VG_(strlen)(pdbname) + VG_(strlen)(home) + 50/*misc*/;
HChar* mashed = ML_(dinfo_zalloc)("di.debuginfo.dnpdi.2", mashedSzB);
- VG_(sprintf)(mashed, "%s/.wine/drive_%c%s",
- home, VG_(tolower)(pdbname[0]), &pdbname[2]);
+ VG_(snprintf)(mashed, mashedSzB, "%s/.wine/drive_%c%s",
+ home, pdbname[0], &pdbname[2]);
vg_assert(mashed[mashedSzB-1] == 0);
ML_(dinfo_free)(pdbname);
pdbname = mashed;
@@ -1234,7 +1238,7 @@
/* don't set up any of the di-> fields; let
ML_(read_pdb_debug_info) do it. */
- ML_(read_pdb_debug_info)( di, avma_obj, unknown_purpose__reloc,
+ ML_(read_pdb_debug_info)( di, avma_obj, bias_obj,
pdbimage, n_pdbimage, pdbname, pdb_mtime );
// JRS fixme: take notice of return value from read_pdb_debug_info,
// and handle failure
@@ -1275,6 +1279,31 @@
}
+struct _DebugInfoMapping* ML_(find_rx_mapping) ( struct _DebugInfo* di,
+ Addr lo, Addr hi )
+{
+ Word i;
+ vg_assert(lo <= hi);
+
+ /* Optimization: Try to use the last matched rx mapping first */
+ if ( di->last_rx_map
+ && lo >= di->last_rx_map->avma
+ && hi < di->last_rx_map->avma + di->last_rx_map->size)
+ return di->last_rx_map;
+
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ if ( map->rx && map->size > 0
+ && lo >= map->avma && hi < map->avma + map->size) {
+ di->last_rx_map = map;
+ return map;
+ }
+ }
+
+ return NULL;
+}
+
+
/*------------------------------------------------------------*/
/*--- Use of symbol table & location info to create ---*/
/*--- plausible-looking stack dumps. ---*/
@@ -1302,9 +1331,7 @@
See Comment_Regarding_Text_Range_Checks in storage.c for
details. */
inRange = di->fsm.have_rx_map
- && di->fsm.rx_map_size > 0
- && di->fsm.rx_map_avma <= ptr
- && ptr < di->fsm.rx_map_avma + di->fsm.rx_map_size;
+ && (ML_(find_rx_mapping)(di, ptr, ptr) != NULL);
} else {
inRange = (di->data_present
&& di->data_size > 0
@@ -1518,6 +1545,22 @@
/*offsetP*/NULL );
}
+/* mips-linux only: find the offset of current address. This is needed for
+ stack unwinding for MIPS.
+*/
+Bool VG_(get_inst_offset_in_function)( Addr a,
+ /*OUT*/PtrdiffT* offset )
+{
+ Char fnname[64];
+ return get_sym_name ( /*C++-demangle*/False, /*Z-demangle*/False,
+ /*below-main-renaming*/False,
+ a, fnname, 64,
+ /*match_anywhere_in_sym*/True,
+ /*show offset?*/True,
+ /*data syms only please*/True,
+ offset );
+}
+
Vg_FnNameKind VG_(get_fnname_kind) ( Char* name )
{
if (VG_STREQ("main", name)) {
@@ -2042,6 +2085,11 @@
case Creg_IA_SP: return eec->uregs->sp;
case Creg_IA_BP: return eec->uregs->fp;
case Creg_S390_R14: return eec->uregs->lr;
+# elif defined(VGA_mips32)
+ case Creg_IA_IP: return eec->uregs->pc;
+ case Creg_IA_SP: return eec->uregs->sp;
+ case Creg_IA_BP: return eec->uregs->fp;
+ case Creg_MIPS_RA: return eec->uregs->ra;
# elif defined(VGA_ppc32) || defined(VGA_ppc64)
# else
# error "Unsupported arch"
@@ -2270,6 +2318,16 @@
case CFIC_IA_BPREL:
cfa = cfsi->cfa_off + uregs->fp;
break;
+# elif defined(VGA_mips32)
+ case CFIC_IA_SPREL:
+ cfa = cfsi->cfa_off + uregs->sp;
+ break;
+ case CFIR_SAME:
+ cfa = uregs->fp;
+ break;
+ case CFIC_IA_BPREL:
+ cfa = cfsi->cfa_off + uregs->fp;
+ break;
# elif defined(VGA_ppc32) || defined(VGA_ppc64)
# else
# error "Unsupported arch"
@@ -2364,6 +2422,8 @@
ipHere = uregsHere->r15;
# elif defined(VGA_s390x)
ipHere = uregsHere->ia;
+# elif defined(VGA_mips32)
+ ipHere = uregsHere->pc;
# elif defined(VGA_ppc32) || defined(VGA_ppc64)
# else
# error "Unknown arch"
@@ -2440,6 +2500,10 @@
COMPUTE(uregsPrev.ia, uregsHere->ia, cfsi->ra_how, cfsi->ra_off);
COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi->sp_how, cfsi->sp_off);
COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi->fp_how, cfsi->fp_off);
+# elif defined(VGA_mips32)
+ COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi->ra_how, cfsi->ra_off);
+ COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi->sp_how, cfsi->sp_off);
+ COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi->fp_how, cfsi->fp_off);
# elif defined(VGA_ppc32) || defined(VGA_ppc64)
# else
# error "Unknown arch"
diff --git a/main/coregrind/m_debuginfo/misc.c b/main/coregrind/m_debuginfo/misc.c
index 39df3e1..880a2cc 100644
--- a/main/coregrind/m_debuginfo/misc.c
+++ b/main/coregrind/m_debuginfo/misc.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks LLP
+ Copyright (C) 2008-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_debuginfo/priv_d3basics.h b/main/coregrind/m_debuginfo/priv_d3basics.h
index bc58294..457943e 100644
--- a/main/coregrind/m_debuginfo/priv_d3basics.h
+++ b/main/coregrind/m_debuginfo/priv_d3basics.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks LLP and others; see below
+ Copyright (C) 2008-2012 OpenWorks LLP and others; see below
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -199,7 +199,11 @@
DW_FORM_sec_offset = 0x17,
DW_FORM_exprloc = 0x18,
DW_FORM_flag_present = 0x19,
- DW_FORM_ref_sig8 = 0x20
+ DW_FORM_ref_sig8 = 0x20,
+ /* Extensions for DWZ multifile.
+ See http://www.dwarfstd.org/ShowIssue.php?issue=120604.1&type=open . */
+ DW_FORM_GNU_ref_alt = 0x1f20,
+ DW_FORM_GNU_strp_alt = 0x1f21
}
DW_FORM;
diff --git a/main/coregrind/m_debuginfo/priv_misc.h b/main/coregrind/m_debuginfo/priv_misc.h
index fba4182..48de94b 100644
--- a/main/coregrind/m_debuginfo/priv_misc.h
+++ b/main/coregrind/m_debuginfo/priv_misc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks LLP
+ Copyright (C) 2008-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_debuginfo/priv_readdwarf.h b/main/coregrind/m_debuginfo/priv_readdwarf.h
index 9147953..027b5ec 100644
--- a/main/coregrind/m_debuginfo/priv_readdwarf.h
+++ b/main/coregrind/m_debuginfo/priv_readdwarf.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -45,9 +45,11 @@
void ML_(read_debuginfo_dwarf3)
( struct _DebugInfo* di,
UChar* debug_info_img, Word debug_info_sz, /* .debug_info */
+ UChar* debug_types_img, Word debug_types_sz, /* .debug_types */
UChar* debug_abbv_img, Word debug_abbv_sz, /* .debug_abbrev */
UChar* debug_line_img, Word debug_line_sz, /* .debug_line */
- UChar* debug_str_img, Word debug_str_sz ); /* .debug_str */
+ UChar* debug_str_img, Word debug_str_sz, /* .debug_str */
+ UChar* debug_str_alt_img, Word debug_str_alt_sz ); /* .debug_str */
/* --------------------
DWARF1 reader
diff --git a/main/coregrind/m_debuginfo/priv_readdwarf3.h b/main/coregrind/m_debuginfo/priv_readdwarf3.h
index 4cef084..69280ac 100644
--- a/main/coregrind/m_debuginfo/priv_readdwarf3.h
+++ b/main/coregrind/m_debuginfo/priv_readdwarf3.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks LLP
+ Copyright (C) 2008-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -43,11 +43,16 @@
ML_(new_dwarf3_reader) (
struct _DebugInfo* di,
UChar* debug_info_img, SizeT debug_info_sz,
+ UChar* debug_types_img, SizeT debug_types_sz,
UChar* debug_abbv_img, SizeT debug_abbv_sz,
UChar* debug_line_img, SizeT debug_line_sz,
UChar* debug_str_img, SizeT debug_str_sz,
UChar* debug_ranges_img, SizeT debug_ranges_sz,
- UChar* debug_loc_img, SizeT debug_loc_sz
+ UChar* debug_loc_img, SizeT debug_loc_sz,
+ UChar* debug_info_alt_img, SizeT debug_info_alt_sz,
+ UChar* debug_abbv_alt_img, SizeT debug_abbv_alt_sz,
+ UChar* debug_line_alt_img, SizeT debug_line_alt_sz,
+ UChar* debug_str_alt_img, SizeT debug_str_alt_sz
);
#endif /* ndef __PRIV_READDWARF3_H */
diff --git a/main/coregrind/m_debuginfo/priv_readelf.h b/main/coregrind/m_debuginfo/priv_readelf.h
index 0876670..a78cbb9 100644
--- a/main/coregrind/m_debuginfo/priv_readelf.h
+++ b/main/coregrind/m_debuginfo/priv_readelf.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -40,7 +40,7 @@
/* Identify an ELF object file by peering at the first few bytes of
it. */
-extern Bool ML_(is_elf_object_file)( void* image, SizeT n_image );
+extern Bool ML_(is_elf_object_file)( void* image, SizeT n_image, Bool rel_ok );
/* The central function for reading ELF debug info. For the
object/exe specified by the SegInfo, find ELF sections, then read
diff --git a/main/coregrind/m_debuginfo/priv_readpdb.h b/main/coregrind/m_debuginfo/priv_readpdb.h
index c36016b..be8405a 100644
--- a/main/coregrind/m_debuginfo/priv_readpdb.h
+++ b/main/coregrind/m_debuginfo/priv_readpdb.h
@@ -11,7 +11,7 @@
derived from readelf.c and valgrind-20031012-wine/vg_symtab2.c
derived from wine-1.0/tools/winedump/pdb.c and msc.c
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -41,7 +41,7 @@
extern Bool ML_(read_pdb_debug_info)(
DebugInfo* di,
Addr obj_avma,
- PtrdiffT unknown_purpose__reloc,
+ PtrdiffT obj_bias,
void* pdbimage,
SizeT n_pdbimage,
Char* pdbname,
diff --git a/main/coregrind/m_debuginfo/priv_readstabs.h b/main/coregrind/m_debuginfo/priv_readstabs.h
index 2df00f3..22f3110 100644
--- a/main/coregrind/m_debuginfo/priv_readstabs.h
+++ b/main/coregrind/m_debuginfo/priv_readstabs.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_debuginfo/priv_storage.h b/main/coregrind/m_debuginfo/priv_storage.h
index 99f0ad4..d42fa45 100644
--- a/main/coregrind/m_debuginfo/priv_storage.h
+++ b/main/coregrind/m_debuginfo/priv_storage.h
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -257,6 +257,21 @@
Int fp_off;
}
DiCfSI;
+#elif defined(VGA_mips32)
+typedef
+ struct {
+ Addr base;
+ UInt len;
+ UChar cfa_how; /* a CFIC_ value */
+ UChar ra_how; /* a CFIR_ value */
+ UChar sp_how; /* a CFIR_ value */
+ UChar fp_how; /* a CFIR_ value */
+ Int cfa_off;
+ Int ra_off;
+ Int sp_off;
+ Int fp_off;
+ }
+ DiCfSI;
#else
# error "Unknown arch"
#endif
@@ -288,7 +303,8 @@
Creg_ARM_R12,
Creg_ARM_R15,
Creg_ARM_R14,
- Creg_S390_R14
+ Creg_S390_R14,
+ Creg_MIPS_RA
}
CfiReg;
@@ -405,13 +421,9 @@
true. The initial state is one in which we have no observations,
so have_rx_map and have_rw_map are both false.
- This is all rather ad-hoc; for example it has no way to record more
- than one rw or rx mapping for a given object, not because such
- events have never been observed, but because we've never needed to
- note more than the first one of any such in order when to decide to
- read debug info. It may be that in future we need to track more
- state in order to make the decision, so this struct would then get
- expanded.
+ This all started as a rather ad-hoc solution, but was further
+ expanded to handle weird object layouts, e.g. more than one rw
+ or rx mapping for one binary.
The normal sequence of events is one of
@@ -428,28 +440,22 @@
where the upgrade is done by a call to vm_protect. Hence we
need to also track this possibility.
*/
+
+struct _DebugInfoMapping
+{
+ Addr avma; /* these fields record the file offset, length */
+ SizeT size; /* and map address of each mapping */
+ OffT foff;
+ Bool rx, rw, ro; /* memory access flags for this mapping */
+};
+
struct _DebugInfoFSM
{
- /* --- all targets --- */
- UChar* filename; /* in mallocville (VG_AR_DINFO) */
-
+ UChar* filename; /* in mallocville (VG_AR_DINFO) */
+ XArray* maps; /* XArray of _DebugInfoMapping structs */
Bool have_rx_map; /* did we see a r?x mapping yet for the file? */
Bool have_rw_map; /* did we see a rw? mapping yet for the file? */
-
- Addr rx_map_avma; /* these fields record the file offset, length */
- SizeT rx_map_size; /* and map address of the r?x mapping we believe */
- OffT rx_map_foff; /* is the .text segment mapping */
-
- Addr rw_map_avma; /* ditto, for the rw? mapping we believe is the */
- SizeT rw_map_size; /* .data segment mapping */
- OffT rw_map_foff;
-
- /* --- OSX 10.7, 32-bit only --- */
Bool have_ro_map; /* did we see a r-- mapping yet for the file? */
-
- Addr ro_map_avma; /* file offset, length, avma for said mapping */
- SizeT ro_map_size;
- OffT ro_map_foff;
};
@@ -515,8 +521,7 @@
we have committed to reading the symbols and debug info (that
is, at the point where .have_dinfo is set to True). */
- /* The file's soname. FIXME: ensure this is always allocated in
- VG_AR_DINFO. */
+ /* The file's soname. */
UChar* soname;
/* Description of some important mapped segments. The presence or
@@ -530,17 +535,17 @@
Comment_on_IMPORTANT_CFSI_REPRESENTATIONAL_INVARIANTS: we require that
- either (rx_map_size == 0 && cfsi == NULL) (the degenerate case)
+ either (size of all rx maps == 0 && cfsi == NULL) (the degenerate case)
or the normal case, which is the AND of the following:
- (0) rx_map_size > 0
- (1) no two DebugInfos with rx_map_size > 0
- have overlapping [rx_map_avma,+rx_map_size)
- (2) [cfsi_minavma,cfsi_maxavma] does not extend
- beyond [rx_map_avma,+rx_map_size); that is, the former is a
- subrange or equal to the latter.
+ (0) size of at least one rx mapping > 0
+ (1) no two DebugInfos with some rx mapping of size > 0
+ have overlapping rx mappings
+ (2) [cfsi_minavma,cfsi_maxavma] does not extend beyond
+ [avma,+size) of one rx mapping; that is, the former
+ is a subrange or equal to the latter.
(3) all DiCfSI in the cfsi array all have ranges that fall within
- [rx_map_avma,+rx_map_size).
+ [avma,+size) of that rx mapping.
(4) all DiCfSI in the cfsi array are non-overlapping
The cumulative effect of these restrictions is to ensure that
@@ -749,6 +754,7 @@
UWord fpo_size;
Addr fpo_minavma;
Addr fpo_maxavma;
+ Addr fpo_base_avma;
/* Expandable arrays of characters -- the string table. Pointers
into this are stable (the arrays are not reallocated). */
@@ -793,6 +799,11 @@
/* An array of guarded DWARF3 expressions. */
XArray* admin_gexprs;
+
+ /* Cached last rx mapping matched and returned by ML_(find_rx_mapping).
+ This helps performance a lot during ML_(addLineInfo) etc., which can
+ easily be invoked hundreds of thousands of times. */
+ struct _DebugInfoMapping* last_rx_map;
};
/* --------------------- functions --------------------- */
@@ -861,6 +872,13 @@
if not found. Binary search. */
extern Word ML_(search_one_fpotab) ( struct _DebugInfo* di, Addr ptr );
+/* Helper function for the most often needed searching for an rx
+ mapping containing the specified address range. The range must
+ fall entirely within the mapping to be considered to be within it.
+ Asserts if lo > hi; caller must ensure this doesn't happen. */
+extern struct _DebugInfoMapping* ML_(find_rx_mapping) ( struct _DebugInfo* di,
+ Addr lo, Addr hi );
+
/* ------ Misc ------ */
/* Show a non-fatal debug info reading error. Use vg_panic if
diff --git a/main/coregrind/m_debuginfo/priv_tytypes.h b/main/coregrind/m_debuginfo/priv_tytypes.h
index 9a03134..26282a2 100644
--- a/main/coregrind/m_debuginfo/priv_tytypes.h
+++ b/main/coregrind/m_debuginfo/priv_tytypes.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks LLP
+ Copyright (C) 2008-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -45,7 +45,10 @@
Te_Field, /* struct/class field defn */
Te_Bound, /* array bounds indication, for one dimension */
Te_TyBase, /* base type */
- Te_TyPorR, /* pointer or reference type */
+ Te_TyPtr, /* pointer type */
+ Te_TyRef, /* reference type */
+ Te_TyPtrMbr, /* pointer to member type */
+ Te_TyRvalRef,/* rvalue reference type */
Te_TyTyDef, /* a renaming of some other type */
Te_TyStOrUn, /* structure or union type */
Te_TyEnum, /* an enum type */
@@ -101,7 +104,6 @@
struct {
Int szB;
UWord typeR;
- Bool isPtr;
} TyPorR;
struct {
UChar* name; /* in mallocville */
diff --git a/main/coregrind/m_debuginfo/readdwarf.c b/main/coregrind/m_debuginfo/readdwarf.c
index 5553543..daf5736 100644
--- a/main/coregrind/m_debuginfo/readdwarf.c
+++ b/main/coregrind/m_debuginfo/readdwarf.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -985,7 +985,8 @@
void read_unitinfo_dwarf2( /*OUT*/UnitInfo* ui,
UChar* unitblock_img,
UChar* debugabbrev_img,
- UChar* debugstr_img )
+ UChar* debugstr_img,
+ UChar* debugstr_alt_img )
{
UInt acode, abcode;
ULong atoffs, blklen;
@@ -1114,7 +1115,9 @@
case 0x01: /* FORM_addr */ p += addr_size; break;
case 0x03: /* FORM_block2 */ p += ML_(read_UShort)(p) + 2; break;
case 0x04: /* FORM_block4 */ p += ML_(read_UInt)(p) + 4; break;
- case 0x09: /* FORM_block */ p += read_leb128U( &p ); break;
+ case 0x09: /* FORM_block */ /* fallthrough */
+ case 0x18: /* FORM_exprloc */ { ULong block_len = read_leb128U( &p );
+ p += block_len; break; }
case 0x0a: /* FORM_block1 */ p += *p + 1; break;
case 0x0c: /* FORM_flag */ p++; break;
case 0x0d: /* FORM_sdata */ read_leb128S( &p ); break;
@@ -1125,9 +1128,16 @@
case 0x13: /* FORM_ref4 */ p += 4; break;
case 0x14: /* FORM_ref8 */ p += 8; break;
case 0x15: /* FORM_ref_udata */ read_leb128U( &p ); break;
- case 0x18: /* FORM_exprloc */ p += read_leb128U( &p ); break;
case 0x19: /* FORM_flag_present */break;
case 0x20: /* FORM_ref_sig8 */ p += 8; break;
+ case 0x1f20: /* FORM_GNU_ref_alt */ p += ui->dw64 ? 8 : 4; break;
+ case 0x1f21: /* FORM_GNU_strp_alt */
+ if (debugstr_alt_img && !ui->dw64)
+ sval = debugstr_alt_img + ML_(read_UInt)(p);
+ if (debugstr_alt_img && ui->dw64)
+ sval = debugstr_alt_img + ML_(read_ULong)(p);
+ p += ui->dw64 ? 8 : 4;
+ break;
default:
VG_(printf)( "### unhandled dwarf2 abbrev form code 0x%x\n", form );
@@ -1166,9 +1176,11 @@
void ML_(read_debuginfo_dwarf3)
( struct _DebugInfo* di,
UChar* debug_info_img, Word debug_info_sz, /* .debug_info */
+ UChar* debug_types_img, Word debug_types_sz, /* .debug_types */
UChar* debug_abbv_img, Word debug_abbv_sz, /* .debug_abbrev */
UChar* debug_line_img, Word debug_line_sz, /* .debug_line */
- UChar* debug_str_img, Word debug_str_sz ) /* .debug_str */
+ UChar* debug_str_img, Word debug_str_sz, /* .debug_str */
+ UChar* debug_str_alt_img, Word debug_str_alt_sz ) /* .debug_str */
{
UnitInfo ui;
UShort ver;
@@ -1217,7 +1229,8 @@
VG_(printf)( "Reading UnitInfo at 0x%lx.....\n",
block_img - debug_info_img + 0UL );
read_unitinfo_dwarf2( &ui, block_img,
- debug_abbv_img, debug_str_img );
+ debug_abbv_img, debug_str_img,
+ debug_str_alt_img );
if (0)
VG_(printf)( " => LINES=0x%llx NAME=%s DIR=%s\n",
ui.stmt_list, ui.name, ui.compdir );
@@ -1842,18 +1855,23 @@
# define FP_REG 11 // sometimes s390 has a frame pointer in r11
# define SP_REG 15 // stack is always r15
# define RA_REG_DEFAULT 14 // the return address is in r14
+#elif defined(VGP_mips32_linux)
+# define FP_REG 30
+# define SP_REG 29
+# define RA_REG_DEFAULT 31
#else
# error "Unknown platform"
#endif
-/* the number of regs we are prepared to unwind */
-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+/* The number of regs we are prepared to unwind. The number for
+ arm-linux (320) seems ludicrously high, but the ARM IHI 0040A page
+ 7 (DWARF for the ARM Architecture) specifies that values up to 320
+ might exist, for Neon/VFP-v3. */
+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
+ || defined(VGP_mips32_linux)
# define N_CFI_REGS 72
-#elif defined (VGP_arm_linux)
-/* 287 is the highest allocated DWARF register name as of 27.07.2011
- http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040a/IHI0040A_aadwarf.pdf
-*/
-# define N_CFI_REGS 287
+#elif defined(VGP_arm_linux)
+# define N_CFI_REGS 320
#else
# define N_CFI_REGS 20
#endif
@@ -2154,7 +2172,8 @@
else
if (ctxs->cfa_is_regoff && ctxs->cfa_reg == SP_REG) {
si->cfa_off = ctxs->cfa_off;
-# if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x)
+# if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \
+ || defined(VGA_mips32)
si->cfa_how = CFIC_IA_SPREL;
# elif defined(VGA_arm)
si->cfa_how = CFIC_ARM_R13REL;
@@ -2165,7 +2184,8 @@
else
if (ctxs->cfa_is_regoff && ctxs->cfa_reg == FP_REG) {
si->cfa_off = ctxs->cfa_off;
-# if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x)
+# if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \
+ || defined(VGA_mips32)
si->cfa_how = CFIC_IA_BPREL;
# elif defined(VGA_arm)
si->cfa_how = CFIC_ARM_R12REL;
@@ -2366,6 +2386,50 @@
return True;
+# elif defined(VGA_mips32)
+
+ /* --- entire tail of this fn specialised for mips --- */
+
+ SUMMARISE_HOW(si->ra_how, si->ra_off,
+ ctxs->reg[ctx->ra_reg] );
+ SUMMARISE_HOW(si->fp_how, si->fp_off,
+ ctxs->reg[FP_REG] );
+ SUMMARISE_HOW(si->sp_how, si->sp_off,
+ ctxs->reg[SP_REG] );
+ si->sp_how = CFIR_CFAREL;
+ si->sp_off = 0;
+
+ if (si->fp_how == CFIR_UNKNOWN)
+ si->fp_how = CFIR_SAME;
+ if (si->cfa_how == CFIR_UNKNOWN) {
+ si->cfa_how = CFIC_IA_SPREL;
+ si->cfa_off = 160;
+ }
+ if (si->ra_how == CFIR_UNKNOWN) {
+ if (!debuginfo->cfsi_exprs)
+ debuginfo->cfsi_exprs = VG_(newXA)( ML_(dinfo_zalloc),
+ "di.ccCt.2a",
+ ML_(dinfo_free),
+ sizeof(CfiExpr) );
+ si->ra_how = CFIR_EXPR;
+ si->ra_off = ML_(CfiExpr_CfiReg)( debuginfo->cfsi_exprs,
+ Creg_MIPS_RA);
+ }
+
+ if (si->ra_how == CFIR_SAME)
+ { why = 3; goto failed; }
+
+ if (loc_start >= ctx->loc)
+ { why = 4; goto failed; }
+ if (ctx->loc - loc_start > 10000000 /* let's say */)
+ { why = 5; goto failed; }
+
+ si->base = loc_start + ctx->initloc;
+ si->len = (UInt)(ctx->loc - loc_start);
+
+ return True;
+
+
# elif defined(VGA_ppc32) || defined(VGA_ppc64)
# else
@@ -2448,6 +2512,13 @@
return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_BP );
if (dwreg == srcuc->ra_reg)
return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_IP ); /* correct? */
+# elif defined(VGA_mips32)
+ if (dwreg == SP_REG)
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_SP );
+ if (dwreg == FP_REG)
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_BP );
+ if (dwreg == srcuc->ra_reg)
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_IP );
# elif defined(VGA_ppc32) || defined(VGA_ppc64)
# else
# error "Unknown arch"
@@ -3603,11 +3674,7 @@
cie->saw_z_augmentation = False;
}
-#ifdef VGP_arm_linux_android
-#define N_CIEs 8000
-#else
#define N_CIEs 4000
-#endif
static CIE the_CIEs[N_CIEs];
diff --git a/main/coregrind/m_debuginfo/readdwarf3.c b/main/coregrind/m_debuginfo/readdwarf3.c
index c537004..38f07ac 100644
--- a/main/coregrind/m_debuginfo/readdwarf3.c
+++ b/main/coregrind/m_debuginfo/readdwarf3.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks LLP
+ Copyright (C) 2008-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -71,7 +71,7 @@
ML_(sizeOfType): differentiate between zero sized types and types
for which the size is unknown. Is this important? I don't know.
- DW_AT_array_types: deal with explicit sizes (currently we compute
+ DW_TAG_array_types: deal with explicit sizes (currently we compute
the size from the bounds and the element size, although that's
fragile, if the bounds incompletely specified, or completely
absent)
@@ -85,7 +85,7 @@
expressions correctly, by failing to evaluate them and hence
effectively ignoring the variable with which they are associated.
- Deal with DW_AT_array_types which have element size != stride
+ Deal with DW_TAG_array_types which have element size != stride
In some cases, the info for a variable is split between two
different DIEs (generally a declarer and a definer). We punt on
@@ -140,6 +140,7 @@
#include "pub_core_libcassert.h"
#include "pub_core_libcprint.h"
#include "pub_core_libcsetjmp.h" // setjmp facilities
+#include "pub_core_hashtable.h"
#include "pub_core_options.h"
#include "pub_core_tooliface.h" /* VG_(needs) */
#include "pub_core_xarray.h"
@@ -415,6 +416,19 @@
/* Where is .debug_info? */
UChar* debug_info_img;
UWord debug_info_sz;
+ /* Where is .debug_types? */
+ UChar* debug_types_img;
+ UWord debug_types_sz;
+ /* Where is alternate .debug_info? */
+ UChar* debug_info_alt_img;
+ UWord debug_info_alt_sz;
+ /* Where is alternate .debug_str ? */
+ UChar* debug_str_alt_img;
+ UWord debug_str_alt_sz;
+ /* How much to add to .debug_types resp. alternate .debug_info offsets
+ in cook_die*. */
+ UWord types_cuOff_bias;
+ UWord alt_cuOff_bias;
/* --- Needed so we can add stuff to the string table. --- */
struct _DebugInfo* di;
/* --- a cache for set_abbv_Cursor --- */
@@ -422,10 +436,75 @@
struct { ULong abbv_code; UWord posn; } saC_cache[N_ABBV_CACHE];
UWord saC_cache_queries;
UWord saC_cache_misses;
+
+ /* True if this came from .debug_types; otherwise it came from
+ .debug_info. */
+ Bool is_type_unit;
+ /* For a unit coming from .debug_types, these hold the TU's type
+ signature and the uncooked DIE offset of the TU's signatured
+ type. For a unit coming from .debug_info, these are unused. */
+ ULong type_signature;
+ ULong type_offset;
+
+ /* Signatured type hash; computed once and then shared by all
+ CUs. */
+ VgHashTable signature_types;
+
+ /* True if this came from alternate .debug_info; otherwise
+ it came from normal .debug_info or .debug_types. */
+ Bool is_alt_info;
}
CUConst;
+/* Return the cooked value of DIE depending on whether CC represents a
+ .debug_types unit. To cook a DIE, we pretend that the .debug_info,
+ .debug_types and optional alternate .debug_info sections form
+ a contiguous whole, so that DIEs coming from .debug_types are numbered
+ starting at the end of .debug_info and DIEs coming from alternate
+ .debug_info are numbered starting at the end of .debug_types. */
+static UWord cook_die( CUConst* cc, UWord die )
+{
+ if (cc->is_type_unit)
+ die += cc->types_cuOff_bias;
+ else if (cc->is_alt_info)
+ die += cc->alt_cuOff_bias;
+ return die;
+}
+
+/* Like cook_die, but understand that DIEs coming from a
+ DW_FORM_ref_sig8 reference are already cooked. Also, handle
+ DW_FORM_GNU_ref_alt from within primary .debug_info or .debug_types
+ as reference to alternate .debug_info. */
+static UWord cook_die_using_form( CUConst *cc, UWord die, DW_FORM form)
+{
+ if (form == DW_FORM_ref_sig8)
+ return die;
+ if (form == DW_FORM_GNU_ref_alt)
+ return die + cc->alt_cuOff_bias;
+ return cook_die( cc, die );
+}
+
+/* Return the uncooked offset of DIE and set *TYPE_FLAG to true if the DIE
+ came from the .debug_types section and *ALT_FLAG to true if the DIE
+ came from alternate .debug_info section. */
+static UWord uncook_die( CUConst *cc, UWord die, /*OUT*/Bool *type_flag,
+ Bool *alt_flag )
+{
+ *alt_flag = False;
+ *type_flag = False;
+ if (die >= cc->debug_info_sz) {
+ if (die >= cc->debug_info_sz + cc->debug_types_sz) {
+ *alt_flag = True;
+ die -= cc->debug_info_sz + cc->debug_types_sz;
+ } else {
+ *type_flag = True;
+ die -= cc->debug_info_sz;
+ }
+ }
+ return die;
+}
+
/*------------------------------------------------------------*/
/*--- ---*/
/*--- Helper functions for Guarded Expressions ---*/
@@ -778,7 +857,9 @@
void parse_CU_Header ( /*OUT*/CUConst* cc,
Bool td3,
Cursor* c,
- UChar* debug_abbv_img, UWord debug_abbv_sz )
+ UChar* debug_abbv_img, UWord debug_abbv_sz,
+ Bool type_unit,
+ Bool alt_info )
{
UChar address_size;
UWord debug_abbrev_offset;
@@ -816,6 +897,14 @@
cc->barf( "parse_CU_Header: invalid address_size" );
TRACE_D3(" Pointer Size: %d\n", (Int)address_size );
+ cc->is_type_unit = type_unit;
+ cc->is_alt_info = alt_info;
+
+ if (type_unit) {
+ cc->type_signature = get_ULong( c );
+ cc->type_offset = get_Dwarfish_UWord( c, cc->is_dw64 );
+ }
+
/* Set up so that cc->debug_abbv points to the relevant table for
this CU. Set the szB so that at least we can't read off the end
of the debug_abbrev section -- potentially (and quite likely)
@@ -926,6 +1015,50 @@
cc->saC_cache[N_ABBV_CACHE/2].posn = get_position_of_Cursor(c);
}
+/* This represents a single signatured type. It maps a type signature
+ (a ULong) to a cooked DIE offset. Objects of this type are stored
+ in the type signature hash table. */
+typedef
+ struct D3SignatureType {
+ struct D3SignatureType *next;
+ UWord data;
+ ULong type_signature;
+ UWord die;
+ }
+ D3SignatureType;
+
+/* Record a signatured type in the hash table. */
+static void record_signatured_type ( VgHashTable tab,
+ ULong type_signature,
+ UWord die )
+{
+ D3SignatureType *dstype = ML_(dinfo_zalloc) ( "di.readdwarf3.sigtype",
+ sizeof(D3SignatureType) );
+ dstype->data = (UWord) type_signature;
+ dstype->type_signature = type_signature;
+ dstype->die = die;
+ VG_(HT_add_node) ( tab, dstype );
+}
+
+/* Given a type signature hash table and a type signature, return the
+ cooked DIE offset of the type. If the type cannot be found, call
+ BARF. */
+static UWord lookup_signatured_type ( VgHashTable tab,
+ ULong type_signature,
+ void (*barf)( HChar* ) __attribute__((noreturn)) )
+{
+ D3SignatureType *dstype = VG_(HT_lookup) ( tab, (UWord) type_signature );
+ /* This may be unwarranted chumminess with the hash table
+ implementation. */
+ while ( dstype != NULL && dstype->type_signature != type_signature)
+ dstype = dstype->next;
+ if (dstype == NULL) {
+ barf("lookup_signatured_type: could not find signatured type");
+ /*NOTREACHED*/
+ vg_assert(0);
+ }
+ return dstype->die;
+}
/* From 'c', get the Form data into the lowest 1/2/4/8 bytes of *cts.
@@ -1018,9 +1151,17 @@
So for the moment we merely range-check, to see that they
actually do specify a plausible offset within this
object's .debug_info, and return the value unchanged.
+
+ In DWARF 2, DW_FORM_ref_addr is address-sized, but in
+ DWARF 3 and later, it is offset-sized.
*/
- *cts = (ULong)(UWord)get_UWord(c);
- *ctsSzB = sizeof(UWord);
+ if (cc->version == 2) {
+ *cts = (ULong)(UWord)get_UWord(c);
+ *ctsSzB = sizeof(UWord);
+ } else {
+ *cts = get_Dwarfish_UWord(c, cc->is_dw64);
+ *ctsSzB = cc->is_dw64 ? sizeof(ULong) : sizeof(UInt);
+ }
TRACE_D3("0x%lx", (UWord)*cts);
if (0) VG_(printf)("DW_FORM_ref_addr 0x%lx\n", (UWord)*cts);
if (/* the following 2 are surely impossible, but ... */
@@ -1164,14 +1305,20 @@
}
case DW_FORM_ref_sig8: {
ULong u64b;
- UChar* block = get_address_of_Cursor(c);
+ ULong signature = get_ULong (c);
+ ULong work = signature;
TRACE_D3("8 byte signature: ");
for (u64b = 8; u64b > 0; u64b--) {
- UChar u8 = get_UChar(c);
+ UChar u8 = work & 0xff;
TRACE_D3("%x ", (UInt)u8);
+ work >>= 8;
}
- *cts = (ULong)(UWord)block;
- *ctsMemSzB = 8;
+ /* Due to the way that the hash table is constructed, the
+ resulting DIE offset here is already "cooked". See
+ cook_die_using_form. */
+ *cts = lookup_signatured_type (cc->signature_types, signature,
+ c->barf);
+ *ctsSzB = sizeof(UWord);
break;
}
case DW_FORM_indirect:
@@ -1179,6 +1326,37 @@
(DW_FORM)get_ULEB128(c));
return;
+ case DW_FORM_GNU_ref_alt:
+ *cts = get_Dwarfish_UWord(c, cc->is_dw64);
+ *ctsSzB = cc->is_dw64 ? sizeof(ULong) : sizeof(UInt);
+ TRACE_D3("0x%lx", (UWord)*cts);
+ if (0) VG_(printf)("DW_FORM_GNU_ref_alt 0x%lx\n", (UWord)*cts);
+ if (/* the following 2 are surely impossible, but ... */
+ cc->debug_info_alt_img == NULL || cc->debug_info_alt_sz == 0
+ || *cts >= (ULong)cc->debug_info_alt_sz) {
+ /* Hmm. Offset is nonsensical for this object's .debug_info
+ section. Be safe and reject it. */
+ cc->barf("get_Form_contents: DW_FORM_ref_addr points "
+ "outside alternate .debug_info");
+ }
+ break;
+
+ case DW_FORM_GNU_strp_alt: {
+ /* this is an offset into alternate .debug_str */
+ UChar* str;
+ UWord uw = (UWord)get_Dwarfish_UWord( c, cc->is_dw64 );
+ if (cc->debug_str_alt_img == NULL || uw >= cc->debug_str_alt_sz)
+ cc->barf("get_Form_contents: DW_FORM_GNU_strp_alt "
+ "points outside alternate .debug_str");
+ /* FIXME: check the entire string lies inside debug_str,
+ not just the first byte of it. */
+ str = (UChar*)cc->debug_str_alt_img + uw;
+ TRACE_D3("(indirect alt string, offset: 0x%lx): %s", uw, str);
+ *cts = (ULong)(UWord)str;
+ *ctsMemSzB = 1 + (ULong)VG_(strlen)(str);
+ break;
+ }
+
default:
VG_(printf)(
"get_Form_contents: unhandled %d (%s) at <%lx>\n",
@@ -1468,12 +1646,17 @@
UWord saved_die_c_offset = get_position_of_Cursor( c_die );
UWord saved_abbv_c_offset = get_position_of_Cursor( c_abbv );
+ Bool debug_types_flag;
+ Bool alt_flag;
varstack_preen( parser, td3, level-1 );
- if (dtag == DW_TAG_compile_unit) {
+ if (dtag == DW_TAG_compile_unit
+ || dtag == DW_TAG_type_unit
+ || dtag == DW_TAG_partial_unit) {
Bool have_lo = False;
Bool have_hi1 = False;
+ Bool hiIsRelative = False;
Bool have_range = False;
Addr ip_lo = 0;
Addr ip_hi1 = 0;
@@ -1491,6 +1674,8 @@
if (attr == DW_AT_high_pc && ctsSzB > 0) {
ip_hi1 = cts;
have_hi1 = True;
+ if (form != DW_FORM_addr)
+ hiIsRelative = True;
}
if (attr == DW_AT_ranges && ctsSzB > 0) {
rangeoff = cts;
@@ -1500,6 +1685,8 @@
read_filename_table( parser, cc, (UWord)cts, td3 );
}
}
+ if (have_lo && have_hi1 && hiIsRelative)
+ ip_hi1 += ip_lo;
/* Now, does this give us an opportunity to find this
CU's svma? */
#if 0
@@ -1580,6 +1767,7 @@
Bool have_lo = False;
Bool have_hi1 = False;
Bool have_range = False;
+ Bool hiIsRelative = False;
Addr ip_lo = 0;
Addr ip_hi1 = 0;
Addr rangeoff = 0;
@@ -1598,6 +1786,8 @@
if (attr == DW_AT_high_pc && ctsSzB > 0) {
ip_hi1 = cts;
have_hi1 = True;
+ if (form != DW_FORM_addr)
+ hiIsRelative = True;
}
if (attr == DW_AT_ranges && ctsSzB > 0) {
rangeoff = cts;
@@ -1612,6 +1802,8 @@
VG_(addToXA)(gexprs, &fbGX);
}
}
+ if (have_lo && have_hi1 && hiIsRelative)
+ ip_hi1 += ip_lo;
/* Do we have something that looks sane? */
if (dtag == DW_TAG_subprogram
&& (!have_lo) && (!have_hi1) && (!have_range)) {
@@ -1685,7 +1877,7 @@
VG_(addToXA)(gexprs, &gexpr);
}
if (attr == DW_AT_type && ctsSzB > 0) {
- typeR = (UWord)cts;
+ typeR = cook_die_using_form( cc, (UWord)cts, form );
}
if (attr == DW_AT_external && ctsSzB > 0 && cts > 0) {
external = True;
@@ -1917,7 +2109,15 @@
set_position_of_Cursor( c_die, saved_die_c_offset );
set_position_of_Cursor( c_abbv, saved_abbv_c_offset );
VG_(printf)("\nparse_var_DIE: confused by:\n");
- VG_(printf)(" <%d><%lx>: %s\n", level, posn, ML_(pp_DW_TAG)( dtag ) );
+ posn = uncook_die( cc, posn, &debug_types_flag, &alt_flag );
+ VG_(printf)(" <%d><%lx>: %s", level, posn, ML_(pp_DW_TAG)( dtag ) );
+ if (debug_types_flag) {
+ VG_(printf)(" (in .debug_types)");
+ }
+ else if (alt_flag) {
+ VG_(printf)(" (in alternate .debug_info)");
+ }
+ VG_(printf)("\n");
while (True) {
DW_AT attr = (DW_AT) get_ULEB128( c_abbv );
DW_FORM form = (DW_FORM)get_ULEB128( c_abbv );
@@ -2097,6 +2297,8 @@
TyEnt atomE;
TyEnt fieldE;
TyEnt boundE;
+ Bool debug_types_flag;
+ Bool alt_flag;
UWord saved_die_c_offset = get_position_of_Cursor( c_die );
UWord saved_abbv_c_offset = get_position_of_Cursor( c_abbv );
@@ -2111,7 +2313,9 @@
its children. */
typestack_preen( parser, td3, level-1 );
- if (dtag == DW_TAG_compile_unit) {
+ if (dtag == DW_TAG_compile_unit
+ || dtag == DW_TAG_type_unit
+ || dtag == DW_TAG_partial_unit) {
/* See if we can find DW_AT_language, since it is important for
establishing array bounds (see DW_TAG_subrange_type below in
this fn) */
@@ -2173,8 +2377,10 @@
case DW_ATE_unsigned: case DW_ATE_unsigned_char:
case DW_ATE_UTF: /* since DWARF4, e.g. char16_t from C++ */
case DW_ATE_boolean:/* FIXME - is this correct? */
+ case DW_ATE_unsigned_fixed:
typeE.Te.TyBase.enc = 'U'; break;
case DW_ATE_signed: case DW_ATE_signed_char:
+ case DW_ATE_signed_fixed:
typeE.Te.TyBase.enc = 'S'; break;
case DW_ATE_float:
typeE.Te.TyBase.enc = 'F'; break;
@@ -2221,19 +2427,41 @@
goto acquire_Type;
}
+ /*
+ * An example of DW_TAG_rvalue_reference_type:
+ *
+ * $ readelf --debug-dump /usr/lib/debug/usr/lib/libstdc++.so.6.0.16.debug
+ * <1><1014>: Abbrev Number: 55 (DW_TAG_rvalue_reference_type)
+ * <1015> DW_AT_byte_size : 4
+ * <1016> DW_AT_type : <0xe52>
+ */
if (dtag == DW_TAG_pointer_type || dtag == DW_TAG_reference_type
- || dtag == DW_TAG_ptr_to_member_type) {
+ || dtag == DW_TAG_ptr_to_member_type
+ || dtag == DW_TAG_rvalue_reference_type) {
/* This seems legit for _pointer_type and _reference_type. I
don't know if rolling _ptr_to_member_type in here really is
legit, but it's better than not handling it at all. */
VG_(memset)(&typeE, 0, sizeof(typeE));
typeE.cuOff = D3_INVALID_CUOFF;
- typeE.tag = Te_TyPorR;
+ switch (dtag) {
+ case DW_TAG_pointer_type:
+ typeE.tag = Te_TyPtr;
+ break;
+ case DW_TAG_reference_type:
+ typeE.tag = Te_TyRef;
+ break;
+ case DW_TAG_ptr_to_member_type:
+ typeE.tag = Te_TyPtrMbr;
+ break;
+ case DW_TAG_rvalue_reference_type:
+ typeE.tag = Te_TyRvalRef;
+ break;
+ default:
+ vg_assert(False);
+ }
/* target type defaults to void */
typeE.Te.TyPorR.typeR = D3_FAKEVOID_CUOFF;
- typeE.Te.TyPorR.isPtr = dtag == DW_TAG_pointer_type
- || dtag == DW_TAG_ptr_to_member_type;
- /* These three type kinds don't *have* to specify their size, in
+ /* These four type kinds don't *have* to specify their size, in
which case we assume it's a machine word. But if they do
specify it, it must be a machine word :-) This probably
assumes that the word size of the Dwarf3 we're reading is the
@@ -2250,7 +2478,7 @@
typeE.Te.TyPorR.szB = cts;
}
if (attr == DW_AT_type && ctsSzB > 0) {
- typeE.Te.TyPorR.typeR = (UWord)cts;
+ typeE.Te.TyPorR.typeR = cook_die_using_form( cc, (UWord)cts, form );
}
}
/* Do we have something that looks sane? */
@@ -2295,8 +2523,23 @@
/* we must know the size */
/* but not for Ada, which uses such dummy
enumerations as helper for gdb ada mode. */
- && parser->language != 'A')
- goto bad_DIE;
+ && parser->language != 'A') {
+ /* GCC has been seen to put an odd DIE like this into
+ .debug_types:
+
+ <1><cb72>: DW_TAG_enumeration_type (in .debug_types)
+ DW_AT_name : (indirect string, offset: 0x3374a): exec_direction_kind
+ DW_AT_declaration : 1
+
+ It isn't clear what this means, but we accept it and
+ assume that the enum is int-sized. */
+ if (cc->is_type_unit) {
+ typeE.Te.TyEnum.szB = sizeof(int);
+ } else {
+ goto bad_DIE;
+ }
+ }
+
/* On't stack! */
typestack_push( cc, parser, td3, &typeE, level );
goto acquire_Type;
@@ -2415,8 +2658,14 @@
if (is_decl && (!is_spec)) {
/* It's a DW_AT_declaration. We require the name but
nothing else. */
+ /* JRS 2012-06-28: following discussion w/ tromey, if the the
+ type doesn't have name, just make one up, and accept it.
+ It might be referred to by other DIEs, so ignoring it
+ doesn't seem like a safe option. */
if (typeE.Te.TyStOrUn.name == NULL)
- goto bad_DIE;
+ typeE.Te.TyStOrUn.name
+ = ML_(dinfo_strdup)( "di.readdwarf3.ptD.struct_type.3",
+ "<anon_struct_type>" );
typeE.Te.TyStOrUn.complete = False;
/* JRS 2009 Aug 10: <possible kludge>? */
/* Push this tyent on the stack, even though it's incomplete.
@@ -2465,7 +2714,7 @@
(UChar*)(UWord)cts );
}
if (attr == DW_AT_type && ctsSzB > 0) {
- fieldE.Te.Field.typeR = (UWord)cts;
+ fieldE.Te.Field.typeR = cook_die_using_form( cc, (UWord)cts, form );
}
/* There are 2 different cases for DW_AT_data_member_location.
If it is a constant class attribute, it contains byte offset
@@ -2525,6 +2774,7 @@
const members in C++ code which are compile time constants
that do no exist in the class. They're not of any interest
to us so we ignore them. */
+ ML_(TyEnt__make_EMPTY)(&fieldE);
}
}
@@ -2544,7 +2794,8 @@
get_Form_contents( &cts, &ctsSzB, &ctsMemSzB,
cc, c_die, False/*td3*/, form );
if (attr == DW_AT_type && ctsSzB > 0) {
- typeE.Te.TyArray.typeR = (UWord)cts;
+ typeE.Te.TyArray.typeR = cook_die_using_form( cc, (UWord)cts,
+ form );
}
}
if (typeE.Te.TyArray.typeR == D3_INVALID_CUOFF)
@@ -2638,7 +2889,7 @@
boundE.cuOff = posn;
vg_assert(parser->qparentE[parser->sp].Te.TyArray.boundRs);
VG_(addToXA)( parser->qparentE[parser->sp].Te.TyArray.boundRs,
- &boundE );
+ &boundE.cuOff );
/* And record the child itself */
goto acquire_Bound;
}
@@ -2667,7 +2918,8 @@
(UChar*)(UWord)cts );
}
if (attr == DW_AT_type && ctsSzB > 0) {
- typeE.Te.TyTyDef.typeR = (UWord)cts;
+ typeE.Te.TyTyDef.typeR = cook_die_using_form( cc, (UWord)cts,
+ form );
}
}
/* Do we have something that looks sane? */
@@ -2710,7 +2962,7 @@
get_Form_contents( &cts, &ctsSzB, &ctsMemSzB,
cc, c_die, False/*td3*/, form );
if (attr == DW_AT_type && ctsSzB > 0) {
- typeE.Te.TyQual.typeR = (UWord)cts;
+ typeE.Te.TyQual.typeR = cook_die_using_form( cc, (UWord)cts, form );
have_ty++;
}
}
@@ -2723,6 +2975,21 @@
goto bad_DIE;
}
+ /*
+ * Treat DW_TAG_unspecified_type as type void. An example of DW_TAG_unspecified_type:
+ *
+ * $ readelf --debug-dump /usr/lib/debug/usr/lib/libstdc++.so.6.0.16.debug
+ * <1><10d4>: Abbrev Number: 53 (DW_TAG_unspecified_type)
+ * <10d5> DW_AT_name : (indirect string, offset: 0xdb7): decltype(nullptr)
+ */
+ if (dtag == DW_TAG_unspecified_type) {
+ VG_(memset)(&typeE, 0, sizeof(typeE));
+ typeE.cuOff = D3_INVALID_CUOFF;
+ typeE.tag = Te_TyQual;
+ typeE.Te.TyQual.typeR = D3_FAKEVOID_CUOFF;
+ goto acquire_Type;
+ }
+
/* else ignore this DIE */
return;
/*NOTREACHED*/
@@ -2775,7 +3042,14 @@
set_position_of_Cursor( c_die, saved_die_c_offset );
set_position_of_Cursor( c_abbv, saved_abbv_c_offset );
VG_(printf)("\nparse_type_DIE: confused by:\n");
- VG_(printf)(" <%d><%lx>: %s\n", level, posn, ML_(pp_DW_TAG)( dtag ) );
+ posn = uncook_die( cc, posn, &debug_types_flag, &alt_flag );
+ VG_(printf)(" <%d><%lx>: %s", level, posn, ML_(pp_DW_TAG)( dtag ) );
+ if (debug_types_flag) {
+ VG_(printf)(" (in .debug_types)");
+ } else if (alt_flag) {
+ VG_(printf)(" (in alternate .debug_info)");
+ }
+ VG_(printf)("\n");
while (True) {
DW_AT attr = (DW_AT) get_ULEB128( c_abbv );
DW_FORM form = (DW_FORM)get_ULEB128( c_abbv );
@@ -2867,7 +3141,10 @@
break;
case Te_TyBase:
break;
- case Te_TyPorR:
+ case Te_TyPtr:
+ case Te_TyRef:
+ case Te_TyPtrMbr:
+ case Te_TyRvalRef:
te->Te.TyPorR.typeR
= chase_cuOff( &b, ents, ents_cache, te->Te.TyPorR.typeR );
if (b) changed = True;
@@ -3145,7 +3422,7 @@
UWord after_die_c_offset, after_abbv_c_offset;
/* --- Deal with this DIE --- */
- posn = get_position_of_Cursor( c );
+ posn = cook_die( cc, get_position_of_Cursor( c ) );
abbv_code = get_ULEB128( c );
set_abbv_Cursor( &abbv, td3, cc, abbv_code );
atag = get_ULEB128( &abbv );
@@ -3243,11 +3520,16 @@
struct _DebugInfo* di,
__attribute__((noreturn)) void (*barf)( HChar* ),
UChar* debug_info_img, SizeT debug_info_sz,
+ UChar* debug_types_img, SizeT debug_types_sz,
UChar* debug_abbv_img, SizeT debug_abbv_sz,
UChar* debug_line_img, SizeT debug_line_sz,
UChar* debug_str_img, SizeT debug_str_sz,
UChar* debug_ranges_img, SizeT debug_ranges_sz,
- UChar* debug_loc_img, SizeT debug_loc_sz
+ UChar* debug_loc_img, SizeT debug_loc_sz,
+ UChar* debug_info_alt_img, SizeT debug_info_alt_sz,
+ UChar* debug_abbv_alt_img, SizeT debug_abbv_alt_sz,
+ UChar* debug_line_alt_img, SizeT debug_line_alt_sz,
+ UChar* debug_str_alt_img, SizeT debug_str_alt_sz
)
{
XArray* /* of TyEnt */ tyents;
@@ -3269,6 +3551,8 @@
Word i, j, n;
Bool td3 = di->trace_symtab;
XArray* /* of TempVar* */ dioff_lookup_tab;
+ Int pass;
+ VgHashTable signature_types;
#if 0
/* This doesn't work properly because it assumes all entries are
packed end to end, with no holes. But that doesn't always
@@ -3402,13 +3686,6 @@
}
TRACE_SYMTAB("\n");
- /* Now loop over the Compilation Units listed in the .debug_info
- section (see D3SPEC sec 7.5) paras 1 and 2. Each compilation
- unit contains a Compilation Unit Header followed by precisely
- one DW_TAG_compile_unit or DW_TAG_partial_unit DIE. */
- init_Cursor( &info, debug_info_img, debug_info_sz, 0, barf,
- "Overrun whilst reading .debug_info section" );
-
/* We'll park the harvested type information in here. Also create
a fake "void" entry with offset D3_FAKEVOID_CUOFF, so we always
have at least one type entry to refer to. D3_FAKEVOID_CUOFF is
@@ -3470,158 +3747,259 @@
VG_(memset)( &varparser, 0, sizeof(varparser) );
varparser.sp = -1;
- TRACE_D3("\n------ Parsing .debug_info section ------\n");
- while (True) {
- UWord cu_start_offset, cu_offset_now;
- CUConst cc;
- /* It may be that the stated size of this CU is larger than the
- amount of stuff actually in it. icc9 seems to generate CUs
- thusly. We use these variables to figure out if this is
- indeed the case, and if so how many bytes we need to skip to
- get to the start of the next CU. Not skipping those bytes
- causes us to misidentify the start of the next CU, and it all
- goes badly wrong after that (not surprisingly). */
- UWord cu_size_including_IniLen, cu_amount_used;
+ signature_types = VG_(HT_construct) ("signature_types");
+
+ /* Do an initial pass to scan the .debug_types section, if any, and
+ fill in the signatured types hash table. This lets us handle
+ mapping from a type signature to a (cooked) DIE offset directly
+ in get_Form_contents. */
+ if (debug_types_img != NULL) {
+ init_Cursor( &info, debug_types_img, debug_types_sz, 0, barf,
+ "Overrun whilst reading .debug_types section" );
+ TRACE_D3("\n------ Collecting signatures from .debug_types section ------\n");
- /* It seems icc9 finishes the DIE info before debug_info_sz
- bytes have been used up. So be flexible, and declare the
- sequence complete if there is not enough remaining bytes to
- hold even the smallest conceivable CU header. (11 bytes I
- reckon). */
- /* JRS 23Jan09: I suspect this is no longer necessary now that
- the code below contains a 'while (cu_amount_used <
- cu_size_including_IniLen ...' style loop, which skips over
- any leftover bytes at the end of a CU in the case where the
- CU's stated size is larger than its actual size (as
- determined by reading all its DIEs). However, for prudence,
- I'll leave the following test in place. I can't see that a
- CU header can be smaller than 11 bytes, so I don't think
- there's any harm possible through the test -- it just adds
- robustness. */
- Word avail = get_remaining_length_Cursor( &info );
- if (avail < 11) {
- if (avail > 0)
- TRACE_D3("new_dwarf3_reader_wrk: warning: "
- "%ld unused bytes after end of DIEs\n", avail);
- break;
+ while (True) {
+ UWord cu_start_offset, cu_offset_now;
+ CUConst cc;
+
+ cu_start_offset = get_position_of_Cursor( &info );
+ TRACE_D3("\n");
+ TRACE_D3(" Compilation Unit @ offset 0x%lx:\n", cu_start_offset);
+ /* parse_CU_header initialises the CU's set_abbv_Cursor cache
+ (saC_cache) */
+ parse_CU_Header( &cc, td3, &info,
+ (UChar*)debug_abbv_img, debug_abbv_sz,
+ True, False );
+
+ /* Needed by cook_die. */
+ cc.types_cuOff_bias = debug_info_sz;
+
+ record_signatured_type( signature_types, cc.type_signature,
+ cook_die( &cc, cc.type_offset ));
+
+ /* Until proven otherwise we assume we don't need the icc9
+ workaround in this case; see the DIE-reading loop below
+ for details. */
+ cu_offset_now = (cu_start_offset + cc.unit_length
+ + (cc.is_dw64 ? 12 : 4));
+
+ if (cu_offset_now == debug_types_sz)
+ break;
+
+ set_position_of_Cursor ( &info, cu_offset_now );
+ }
+ }
+
+ /* Perform three DIE-reading passes. The first pass reads DIEs from
+ alternate .debug_info (if any), the second pass reads DIEs from
+ .debug_info, and the third pass reads DIEs from .debug_types.
+ Moving the body of this loop into a separate function would
+ require a large number of arguments to be passed in, so it is
+ kept inline instead. */
+ for (pass = 0; pass < 3; ++pass) {
+ UWord section_size;
+
+ if (pass == 0) {
+ if (debug_info_alt_img == NULL)
+ continue;
+ /* Now loop over the Compilation Units listed in the alternate
+ .debug_info section (see D3SPEC sec 7.5) paras 1 and 2.
+ Each compilation unit contains a Compilation Unit Header
+ followed by precisely one DW_TAG_compile_unit or
+ DW_TAG_partial_unit DIE. */
+ init_Cursor( &info, debug_info_alt_img, debug_info_alt_sz, 0, barf,
+ "Overrun whilst reading alternate .debug_info section" );
+ section_size = debug_info_alt_sz;
+
+ TRACE_D3("\n------ Parsing alternate .debug_info section ------\n");
+ } else if (pass == 1) {
+ /* Now loop over the Compilation Units listed in the .debug_info
+ section (see D3SPEC sec 7.5) paras 1 and 2. Each compilation
+ unit contains a Compilation Unit Header followed by precisely
+ one DW_TAG_compile_unit or DW_TAG_partial_unit DIE. */
+ init_Cursor( &info, debug_info_img, debug_info_sz, 0, barf,
+ "Overrun whilst reading .debug_info section" );
+ section_size = debug_info_sz;
+
+ TRACE_D3("\n------ Parsing .debug_info section ------\n");
+ } else {
+ if (debug_types_img == NULL)
+ continue;
+ init_Cursor( &info, debug_types_img, debug_types_sz, 0, barf,
+ "Overrun whilst reading .debug_types section" );
+ section_size = debug_types_sz;
+
+ TRACE_D3("\n------ Parsing .debug_types section ------\n");
}
- /* Check the varparser's stack is in a sane state. */
- vg_assert(varparser.sp == -1);
- for (i = 0; i < N_D3_VAR_STACK; i++) {
- vg_assert(varparser.ranges[i] == NULL);
- vg_assert(varparser.level[i] == 0);
- }
- for (i = 0; i < N_D3_TYPE_STACK; i++) {
- vg_assert(typarser.qparentE[i].cuOff == D3_INVALID_CUOFF);
- vg_assert(typarser.qparentE[i].tag == Te_EMPTY);
- vg_assert(typarser.qlevel[i] == 0);
- }
+ while (True) {
+ UWord cu_start_offset, cu_offset_now;
+ CUConst cc;
+ /* It may be that the stated size of this CU is larger than the
+ amount of stuff actually in it. icc9 seems to generate CUs
+ thusly. We use these variables to figure out if this is
+ indeed the case, and if so how many bytes we need to skip to
+ get to the start of the next CU. Not skipping those bytes
+ causes us to misidentify the start of the next CU, and it all
+ goes badly wrong after that (not surprisingly). */
+ UWord cu_size_including_IniLen, cu_amount_used;
- cu_start_offset = get_position_of_Cursor( &info );
- TRACE_D3("\n");
- TRACE_D3(" Compilation Unit @ offset 0x%lx:\n", cu_start_offset);
- /* parse_CU_header initialises the CU's set_abbv_Cursor cache
- (saC_cache) */
- parse_CU_Header( &cc, td3, &info,
- (UChar*)debug_abbv_img, debug_abbv_sz );
- cc.debug_str_img = debug_str_img;
- cc.debug_str_sz = debug_str_sz;
- cc.debug_ranges_img = debug_ranges_img;
- cc.debug_ranges_sz = debug_ranges_sz;
- cc.debug_loc_img = debug_loc_img;
- cc.debug_loc_sz = debug_loc_sz;
- cc.debug_line_img = debug_line_img;
- cc.debug_line_sz = debug_line_sz;
- cc.debug_info_img = debug_info_img;
- cc.debug_info_sz = debug_info_sz;
- cc.cu_start_offset = cu_start_offset;
- cc.di = di;
- /* The CU's svma can be deduced by looking at the AT_low_pc
- value in the top level TAG_compile_unit, which is the topmost
- DIE. We'll leave it for the 'varparser' to acquire that info
- and fill it in -- since it is the only party to want to know
- it. */
- cc.cu_svma_known = False;
- cc.cu_svma = 0;
+ /* It seems icc9 finishes the DIE info before debug_info_sz
+ bytes have been used up. So be flexible, and declare the
+ sequence complete if there is not enough remaining bytes to
+ hold even the smallest conceivable CU header. (11 bytes I
+ reckon). */
+ /* JRS 23Jan09: I suspect this is no longer necessary now that
+ the code below contains a 'while (cu_amount_used <
+ cu_size_including_IniLen ...' style loop, which skips over
+ any leftover bytes at the end of a CU in the case where the
+ CU's stated size is larger than its actual size (as
+ determined by reading all its DIEs). However, for prudence,
+ I'll leave the following test in place. I can't see that a
+ CU header can be smaller than 11 bytes, so I don't think
+ there's any harm possible through the test -- it just adds
+ robustness. */
+ Word avail = get_remaining_length_Cursor( &info );
+ if (avail < 11) {
+ if (avail > 0)
+ TRACE_D3("new_dwarf3_reader_wrk: warning: "
+ "%ld unused bytes after end of DIEs\n", avail);
+ break;
+ }
- /* Create a fake outermost-level range covering the entire
- address range. So we always have *something* to catch all
- variable declarations. */
- varstack_push( &cc, &varparser, td3,
- unitary_range_list(0UL, ~0UL),
- -1, False/*isFunc*/, NULL/*fbGX*/ );
+ /* Check the varparser's stack is in a sane state. */
+ vg_assert(varparser.sp == -1);
+ for (i = 0; i < N_D3_VAR_STACK; i++) {
+ vg_assert(varparser.ranges[i] == NULL);
+ vg_assert(varparser.level[i] == 0);
+ }
+ for (i = 0; i < N_D3_TYPE_STACK; i++) {
+ vg_assert(typarser.qparentE[i].cuOff == D3_INVALID_CUOFF);
+ vg_assert(typarser.qparentE[i].tag == Te_EMPTY);
+ vg_assert(typarser.qlevel[i] == 0);
+ }
- /* And set up the file name table. When we come across the top
- level DIE for this CU (which is what the next call to
- read_DIE should process) we will copy all the file names out
- of the .debug_line img area and use this table to look up the
- copies when we later see filename numbers in DW_TAG_variables
- etc. */
- vg_assert(!varparser.filenameTable );
- varparser.filenameTable
- = VG_(newXA)( ML_(dinfo_zalloc), "di.readdwarf3.ndrw.5",
- ML_(dinfo_free),
- sizeof(UChar*) );
- vg_assert(varparser.filenameTable);
+ cu_start_offset = get_position_of_Cursor( &info );
+ TRACE_D3("\n");
+ TRACE_D3(" Compilation Unit @ offset 0x%lx:\n", cu_start_offset);
+ /* parse_CU_header initialises the CU's set_abbv_Cursor cache
+ (saC_cache) */
+ if (pass == 0)
+ parse_CU_Header( &cc, td3, &info,
+ (UChar*)debug_abbv_alt_img, debug_abbv_alt_sz,
+ False, True );
+ else
+ parse_CU_Header( &cc, td3, &info,
+ (UChar*)debug_abbv_img, debug_abbv_sz,
+ pass == 2, False );
+ cc.debug_str_img = pass == 0 ? debug_str_alt_img : debug_str_img;
+ cc.debug_str_sz = pass == 0 ? debug_str_alt_sz : debug_str_sz;
+ cc.debug_ranges_img = debug_ranges_img;
+ cc.debug_ranges_sz = debug_ranges_sz;
+ cc.debug_loc_img = debug_loc_img;
+ cc.debug_loc_sz = debug_loc_sz;
+ cc.debug_line_img = pass == 0 ? debug_line_alt_img : debug_line_img;
+ cc.debug_line_sz = pass == 0 ? debug_line_alt_sz : debug_line_sz;
+ cc.debug_info_img = pass == 0 ? debug_info_alt_img : debug_info_img;
+ cc.debug_info_sz = pass == 0 ? debug_info_alt_sz : debug_info_sz;
+ cc.debug_types_img = debug_types_img;
+ cc.debug_types_sz = debug_types_sz;
+ cc.debug_info_alt_img = debug_info_alt_img;
+ cc.debug_info_alt_sz = debug_info_alt_sz;
+ cc.debug_str_alt_img = debug_str_alt_img;
+ cc.debug_str_alt_sz = debug_str_alt_sz;
+ cc.types_cuOff_bias = debug_info_sz;
+ cc.alt_cuOff_bias = debug_info_sz + debug_types_sz;
+ cc.cu_start_offset = cu_start_offset;
+ cc.di = di;
+ /* The CU's svma can be deduced by looking at the AT_low_pc
+ value in the top level TAG_compile_unit, which is the topmost
+ DIE. We'll leave it for the 'varparser' to acquire that info
+ and fill it in -- since it is the only party to want to know
+ it. */
+ cc.cu_svma_known = False;
+ cc.cu_svma = 0;
- /* Now read the one-and-only top-level DIE for this CU. */
- vg_assert(varparser.sp == 0);
- read_DIE( rangestree,
- tyents, tempvars, gexprs,
- &typarser, &varparser,
- &info, td3, &cc, 0 );
+ cc.signature_types = signature_types;
- cu_offset_now = get_position_of_Cursor( &info );
+ /* Create a fake outermost-level range covering the entire
+ address range. So we always have *something* to catch all
+ variable declarations. */
+ varstack_push( &cc, &varparser, td3,
+ unitary_range_list(0UL, ~0UL),
+ -1, False/*isFunc*/, NULL/*fbGX*/ );
- if (0) VG_(printf)("Travelled: %lu size %llu\n",
- cu_offset_now - cc.cu_start_offset,
- cc.unit_length + (cc.is_dw64 ? 12 : 4));
+ /* And set up the file name table. When we come across the top
+ level DIE for this CU (which is what the next call to
+ read_DIE should process) we will copy all the file names out
+ of the .debug_line img area and use this table to look up the
+ copies when we later see filename numbers in DW_TAG_variables
+ etc. */
+ vg_assert(!varparser.filenameTable );
+ varparser.filenameTable
+ = VG_(newXA)( ML_(dinfo_zalloc), "di.readdwarf3.ndrw.5",
+ ML_(dinfo_free),
+ sizeof(UChar*) );
+ vg_assert(varparser.filenameTable);
- /* How big the CU claims it is .. */
- cu_size_including_IniLen = cc.unit_length + (cc.is_dw64 ? 12 : 4);
- /* .. vs how big we have found it to be */
- cu_amount_used = cu_offset_now - cc.cu_start_offset;
+ /* Now read the one-and-only top-level DIE for this CU. */
+ vg_assert(varparser.sp == 0);
+ read_DIE( rangestree,
+ tyents, tempvars, gexprs,
+ &typarser, &varparser,
+ &info, td3, &cc, 0 );
- if (1) TRACE_D3("offset now %ld, d-i-size %ld\n",
- cu_offset_now, debug_info_sz);
- if (cu_offset_now > debug_info_sz)
- barf("toplevel DIEs beyond end of CU");
-
- /* If the CU is bigger than it claims to be, we've got a serious
- problem. */
- if (cu_amount_used > cu_size_including_IniLen)
- barf("CU's actual size appears to be larger than it claims it is");
-
- /* If the CU is smaller than it claims to be, we need to skip some
- bytes. Loop updates cu_offset_new and cu_amount_used. */
- while (cu_amount_used < cu_size_including_IniLen
- && get_remaining_length_Cursor( &info ) > 0) {
- if (0) VG_(printf)("SKIP\n");
- (void)get_UChar( &info );
cu_offset_now = get_position_of_Cursor( &info );
+
+ if (0) VG_(printf)("Travelled: %lu size %llu\n",
+ cu_offset_now - cc.cu_start_offset,
+ cc.unit_length + (cc.is_dw64 ? 12 : 4));
+
+ /* How big the CU claims it is .. */
+ cu_size_including_IniLen = cc.unit_length + (cc.is_dw64 ? 12 : 4);
+ /* .. vs how big we have found it to be */
cu_amount_used = cu_offset_now - cc.cu_start_offset;
+
+ if (1) TRACE_D3("offset now %ld, d-i-size %ld\n",
+ cu_offset_now, section_size);
+ if (cu_offset_now > section_size)
+ barf("toplevel DIEs beyond end of CU");
+
+ /* If the CU is bigger than it claims to be, we've got a serious
+ problem. */
+ if (cu_amount_used > cu_size_including_IniLen)
+ barf("CU's actual size appears to be larger than it claims it is");
+
+ /* If the CU is smaller than it claims to be, we need to skip some
+ bytes. Loop updates cu_offset_new and cu_amount_used. */
+ while (cu_amount_used < cu_size_including_IniLen
+ && get_remaining_length_Cursor( &info ) > 0) {
+ if (0) VG_(printf)("SKIP\n");
+ (void)get_UChar( &info );
+ cu_offset_now = get_position_of_Cursor( &info );
+ cu_amount_used = cu_offset_now - cc.cu_start_offset;
+ }
+
+ /* Preen to level -2. DIEs have level >= 0 so -2 cannot occur
+ anywhere else at all. Our fake the-entire-address-space
+ range is at level -1, so preening to -2 should completely
+ empty the stack out. */
+ TRACE_D3("\n");
+ varstack_preen( &varparser, td3, -2 );
+ /* Similarly, empty the type stack out. */
+ typestack_preen( &typarser, td3, -2 );
+
+ TRACE_D3("set_abbv_Cursor cache: %lu queries, %lu misses\n",
+ cc.saC_cache_queries, cc.saC_cache_misses);
+
+ vg_assert(varparser.filenameTable );
+ VG_(deleteXA)( varparser.filenameTable );
+ varparser.filenameTable = NULL;
+
+ if (cu_offset_now == section_size)
+ break;
+ /* else keep going */
}
-
- if (cu_offset_now == debug_info_sz)
- break;
-
- /* Preen to level -2. DIEs have level >= 0 so -2 cannot occur
- anywhere else at all. Our fake the-entire-address-space
- range is at level -1, so preening to -2 should completely
- empty the stack out. */
- TRACE_D3("\n");
- varstack_preen( &varparser, td3, -2 );
- /* Similarly, empty the type stack out. */
- typestack_preen( &typarser, td3, -2 );
- /* else keep going */
-
- TRACE_D3("set_abbv_Cursor cache: %lu queries, %lu misses\n",
- cc.saC_cache_queries, cc.saC_cache_misses);
-
- vg_assert(varparser.filenameTable );
- VG_(deleteXA)( varparser.filenameTable );
- varparser.filenameTable = NULL;
}
/* From here on we're post-processing the stuff we got
@@ -3714,10 +4092,19 @@
vg_assert(dioff_lookup_tab);
n = VG_(sizeXA)( tempvars );
+ Word first_primary_var;
+ for (first_primary_var = 0;
+ debug_info_alt_sz && first_primary_var < n;
+ first_primary_var++) {
+ varp = *(TempVar**)VG_(indexXA)( tempvars, first_primary_var );
+ if (varp->dioff < debug_info_sz + debug_types_sz)
+ break;
+ }
for (i = 0; i < n; i++) {
- varp = *(TempVar**)VG_(indexXA)( tempvars, i );
- if (i > 0) {
- varp2 = *(TempVar**)VG_(indexXA)( tempvars, i-1 );
+ varp = *(TempVar**)VG_(indexXA)( tempvars, (i + first_primary_var) % n );
+ if (i > first_primary_var) {
+ varp2 = *(TempVar**)VG_(indexXA)( tempvars,
+ (i + first_primary_var - 1) % n );
/* why should this hold? Only, I think, because we've
constructed the array by reading .debug_info sequentially,
and so the array .dioff fields should reflect that, and be
@@ -3932,14 +4319,10 @@
ML_(dinfo_free)( tyents_to_keep_cache );
tyents_to_keep_cache = NULL;
- /* and the file name table (just the array, not the entries
- themselves). (Apparently, 2008-Oct-23, varparser.filenameTable
- can be NULL here, for icc9 generated Dwarf3. Not sure what that
- signifies (a deeper problem with the reader?)) */
- if (varparser.filenameTable) {
- VG_(deleteXA)( varparser.filenameTable );
- varparser.filenameTable = NULL;
- }
+ vg_assert( varparser.filenameTable == NULL );
+
+ /* And the signatured type hash. */
+ VG_(HT_destruct) ( signature_types, ML_(dinfo_free) );
/* record the GExprs in di so they can be freed later */
vg_assert(!di->admin_gexprs);
@@ -3970,11 +4353,16 @@
ML_(new_dwarf3_reader) (
struct _DebugInfo* di,
UChar* debug_info_img, SizeT debug_info_sz,
+ UChar* debug_types_img, SizeT debug_types_sz,
UChar* debug_abbv_img, SizeT debug_abbv_sz,
UChar* debug_line_img, SizeT debug_line_sz,
UChar* debug_str_img, SizeT debug_str_sz,
UChar* debug_ranges_img, SizeT debug_ranges_sz,
- UChar* debug_loc_img, SizeT debug_loc_sz
+ UChar* debug_loc_img, SizeT debug_loc_sz,
+ UChar* debug_info_alt_img, SizeT debug_info_alt_sz,
+ UChar* debug_abbv_alt_img, SizeT debug_abbv_alt_sz,
+ UChar* debug_line_alt_img, SizeT debug_line_alt_sz,
+ UChar* debug_str_alt_img, SizeT debug_str_alt_sz
)
{
volatile Int jumped;
@@ -3993,11 +4381,16 @@
/* try this ... */
new_dwarf3_reader_wrk( di, barf,
debug_info_img, debug_info_sz,
+ debug_types_img, debug_types_sz,
debug_abbv_img, debug_abbv_sz,
debug_line_img, debug_line_sz,
debug_str_img, debug_str_sz,
debug_ranges_img, debug_ranges_sz,
- debug_loc_img, debug_loc_sz );
+ debug_loc_img, debug_loc_sz,
+ debug_info_alt_img, debug_info_alt_sz,
+ debug_abbv_alt_img, debug_abbv_alt_sz,
+ debug_line_alt_img, debug_line_alt_sz,
+ debug_str_alt_img, debug_str_alt_sz);
d3rd_jmpbuf_valid = False;
TRACE_D3("\n------ .debug_info reading was successful ------\n");
} else {
diff --git a/main/coregrind/m_debuginfo/readelf.c b/main/coregrind/m_debuginfo/readelf.c
index f3cf26c..d78dc7a 100644
--- a/main/coregrind/m_debuginfo/readelf.c
+++ b/main/coregrind/m_debuginfo/readelf.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -40,7 +40,6 @@
#include "pub_core_libcfile.h"
#include "pub_core_aspacemgr.h" /* for mmaping debuginfo files */
#include "pub_core_machine.h" /* VG_ELF_CLASS */
-#include "pub_core_mallocfree.h"
#include "pub_core_options.h"
#include "pub_core_oset.h"
#include "pub_core_tooliface.h" /* VG_(needs) */
@@ -112,7 +111,7 @@
/* Identify an ELF object file by peering at the first few bytes of
it. */
-Bool ML_(is_elf_object_file)( void* image, SizeT n_image )
+Bool ML_(is_elf_object_file)( void* image, SizeT n_image, Bool rel_ok )
{
ElfXX_Ehdr* ehdr = (ElfXX_Ehdr*)image;
Int ok = 1;
@@ -127,12 +126,14 @@
ok &= (ehdr->e_ident[EI_CLASS] == VG_ELF_CLASS
&& ehdr->e_ident[EI_DATA] == VG_ELF_DATA2XXX
&& ehdr->e_ident[EI_VERSION] == EV_CURRENT);
- ok &= (ehdr->e_type == ET_EXEC || ehdr->e_type == ET_DYN);
+ ok &= (ehdr->e_type == ET_EXEC || ehdr->e_type == ET_DYN
+ || (rel_ok && ehdr->e_type == ET_REL));
ok &= (ehdr->e_machine == VG_ELF_MACHINE);
ok &= (ehdr->e_version == EV_CURRENT);
ok &= (ehdr->e_shstrndx != SHN_UNDEF);
ok &= (ehdr->e_shoff != 0 && ehdr->e_shnum != 0);
- ok &= (ehdr->e_phoff != 0 && ehdr->e_phnum != 0);
+ ok &= ((ehdr->e_phoff != 0 && ehdr->e_phnum != 0)
+ || ehdr->e_type == ET_REL);
if (ok)
return True;
@@ -235,10 +236,21 @@
*sym_name_out = sym_name;
*sym_avma_out = sym_svma; /* we will bias this shortly */
*is_text_out = True;
- *sym_size_out = (Int)sym->st_size;
*sym_tocptr_out = 0; /* unknown/inapplicable */
*from_opd_out = False;
*is_ifunc = False;
+ /* Get the symbol size, but restrict it to fit in a signed 32 bit
+ int. Also, deal with the stupid case of negative size by making
+ the size be 1. Note that sym->st_size has type UWord,
+ effectively. */
+ { Word size_tmp = (Word)sym->st_size;
+ Word max_Int = (1LL << 31) - 1;
+ if (size_tmp < 0) size_tmp = 1;
+ if (size_tmp > max_Int) size_tmp = max_Int;
+ *sym_size_out = (Int)size_tmp;
+ }
+ /* After this point refer only to *sym_size_out and not to
+ sym->st_size. */
/* Figure out if we're interested in the symbol. Firstly, is it of
the right flavour? */
@@ -250,9 +262,9 @@
&&
(ELFXX_ST_TYPE(sym->st_info) == STT_FUNC
|| ELFXX_ST_TYPE(sym->st_info) == STT_OBJECT
-#ifdef STT_GNU_IFUNC
+# ifdef STT_GNU_IFUNC
|| ELFXX_ST_TYPE(sym->st_info) == STT_GNU_IFUNC
-#endif
+# endif
);
/* Work out the svma and bias for each section as it will appear in
@@ -350,7 +362,7 @@
if (!plausible
&& *is_text_out
&& ELFXX_ST_TYPE(sym->st_info) == STT_NOTYPE
- && sym->st_size > 0
+ && *sym_size_out > 0
&& di->opd_present
&& di->opd_size > 0
&& *sym_avma_out >= di->opd_avma
@@ -383,9 +395,9 @@
in /system/lib/libc.so: strlen strcmp strcpy memcmp memcpy
in /system/bin/linker: __dl_strcmp __dl_strlen
*/
- if (sym->st_size == 0) {
-# if defined(VGPV_arm_linux_android)
- *sym_size_out = 1024;
+ if (*sym_size_out == 0) {
+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
+ *sym_size_out = 2048;
# else
TRACE_SYMTAB(" ignore -- size=0: %s\n", sym_name);
return False;
@@ -555,9 +567,11 @@
background. */
Bool in_rx;
vg_assert(di->fsm.have_rx_map);
- in_rx = (!(*sym_avma_out + *sym_size_out <= di->fsm.rx_map_avma
- || *sym_avma_out >= di->fsm.rx_map_avma
- + di->fsm.rx_map_size));
+ /* This could actually wrap around and cause
+ ML_(find_rx_mapping) to assert. But that seems so unlikely,
+ let's wait for it to happen before fixing it. */
+ in_rx = (ML_(find_rx_mapping)(di, *sym_avma_out,
+ *sym_avma_out + *sym_size_out) != NULL);
if (in_text)
vg_assert(in_rx);
if (!in_rx) {
@@ -888,7 +902,7 @@
* http://fedoraproject.org/wiki/RolandMcGrath/BuildID
*/
static
-Char *find_buildid(Addr image, UWord n_image)
+Char *find_buildid(Addr image, UWord n_image, Bool rel_ok)
{
Char* buildid = NULL;
__attribute__((unused)) /* on Android, at least */
@@ -896,7 +910,7 @@
#ifdef NT_GNU_BUILD_ID
if (n_image >= sizeof(ElfXX_Ehdr) &&
- ML_(is_elf_object_file)(ehdr, n_image)) {
+ ML_(is_elf_object_file)(ehdr, n_image, rel_ok)) {
Word i;
for (i = 0; i < ehdr->e_phnum; i++) {
@@ -928,7 +942,41 @@
+ ((note->n_descsz + 3) & ~3);
}
}
- }
+ }
+
+ if (buildid || !rel_ok)
+ return buildid;
+
+ for (i = 0; i < ehdr->e_shnum; i++) {
+ ElfXX_Shdr* shdr
+ = (ElfXX_Shdr*)(image + ehdr->e_shoff + i * ehdr->e_shentsize);
+
+ if (shdr->sh_type == SHT_NOTE) {
+ ElfXX_Off offset = shdr->sh_offset;
+
+ while (offset < shdr->sh_offset + shdr->sh_size) {
+ ElfXX_Nhdr* note = (ElfXX_Nhdr*)(image + offset);
+ Char* name = (Char *)note + sizeof(ElfXX_Nhdr);
+ UChar *desc = (UChar *)name + ((note->n_namesz + 3) & ~3);
+ Word j;
+
+ if (VG_(strcmp)(name, ELF_NOTE_GNU) == 0 &&
+ note->n_type == NT_GNU_BUILD_ID) {
+ buildid = ML_(dinfo_zalloc)("di.fbi.1",
+ note->n_descsz * 2 + 1);
+
+ for (j = 0; j < note->n_descsz; j++) {
+ VG_(sprintf)(buildid + VG_(strlen)(buildid),
+ "%02x", desc[j]);
+ }
+ }
+
+ offset = offset + sizeof(ElfXX_Nhdr)
+ + ((note->n_namesz + 3) & ~3)
+ + ((note->n_descsz + 3) & ~3);
+ }
+ }
+ }
}
#endif
@@ -1010,7 +1058,8 @@
* not match the value from the main object file.
*/
static
-Addr open_debug_file( Char* name, Char* buildid, UInt crc, /*OUT*/UWord* size )
+Addr open_debug_file( Char* name, Char* buildid, UInt crc, Bool rel_ok,
+ /*OUT*/UWord* size )
{
SysRes fd, sres;
struct vg_stat stat_buf;
@@ -1039,7 +1088,7 @@
return 0;
if (buildid) {
- Char* debug_buildid = find_buildid(sr_Res(sres), *size);
+ Char* debug_buildid = find_buildid(sr_Res(sres), *size, rel_ok);
if (debug_buildid == NULL || VG_(strcmp)(buildid, debug_buildid) != 0) {
SysRes res = VG_(am_munmap_valgrind)(sr_Res(sres), *size);
vg_assert(!sr_isError(res));
@@ -1085,14 +1134,14 @@
{
vg_assert(*dimage == 0 && *n_dimage == 0);
-# if !defined(VGPV_arm_linux_android)
+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android)
return False; /* we don't know narfink */
# else /* android specific hacks; look away now. */
/* The deal is: if we're looking for for a debuginfo file for some
- object /system/blah (where blah can be any path), see if we can
- find the file /sdcard/symbols/system/blah. So for example it
+ object /path/to/object (which can be any path), see if we can
+ find the file /sdcard/symbols/path/to/object. So for example it
produces the following mappings, both of which are important for
Memcheck:
@@ -1110,7 +1159,7 @@
But beware: there is no checking that the debuginfo file, if
found, matches the main file in any way.
*/
- if (0 != VG_(strncmp)(filename, "/system/", 8))
+ if (!filename || *filename != '/')
return False;
HChar* nm = ML_(dinfo_zalloc)("di.fahdi.1",
@@ -1158,7 +1207,7 @@
static
void find_debug_file( struct _DebugInfo* di,
Char* objpath, Char* buildid,
- Char* debugname, UInt crc,
+ Char* debugname, UInt crc, Bool rel_ok,
/*OUT*/Addr* dimage,
/*OUT*/SizeT* n_dimage )
{
@@ -1176,13 +1225,14 @@
VG_(sprintf)(debugpath, "/usr/lib/debug/.build-id/%c%c/%s.debug",
buildid[0], buildid[1], buildid + 2);
- if ((addr = open_debug_file(debugpath, buildid, 0, &size)) == 0) {
+ if ((addr = open_debug_file(debugpath, buildid, 0,
+ rel_ok, &size)) == 0) {
ML_(dinfo_free)(debugpath);
debugpath = NULL;
}
}
- if (addr == 0 && debugname != NULL) {
+ if (addr == 0 && debugname != NULL && !rel_ok) {
Char *objdir = ML_(dinfo_strdup)("di.fdf.2", objpath);
Char *objdirptr;
@@ -1195,17 +1245,11 @@
VG_(sprintf)(debugpath, "%s/%s", objdir, debugname);
- if ((addr = open_debug_file(debugpath, NULL, crc, &size)) == 0) {
+ if ((addr = open_debug_file(debugpath, NULL, crc, rel_ok, &size)) == 0) {
VG_(sprintf)(debugpath, "%s/.debug/%s", objdir, debugname);
- if ((addr = open_debug_file(debugpath, NULL, crc, &size)) == 0) {
+ if ((addr = open_debug_file(debugpath, NULL, crc, rel_ok, &size)) == 0) {
VG_(sprintf)(debugpath, "/usr/lib/debug%s/%s", objdir, debugname);
- if ((addr = open_debug_file(debugpath, NULL, crc, &size)) == 0) {
-#ifdef ANDROID
- VG_(sprintf)(debugpath, "/data/local/symbols%s/%s", objdir, debugname);
- addr = open_debug_file(debugpath, NULL, crc, &size);
-#endif
- }
-
+ addr = open_debug_file(debugpath, NULL, crc, rel_ok, &size);
}
}
@@ -1273,12 +1317,6 @@
supplied DebugInfo.
*/
-/* Temporarily holds information copied out of PT_LOAD entries
- in ML_(read_elf_debug_info. */
-typedef
- struct { Addr svma_base; Addr svma_limit; PtrdiffT bias; }
- RangeAndBias;
-
Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di )
{
/* This function is long and complex. That, and the presence of
@@ -1290,7 +1328,7 @@
/* TOPLEVEL */
Bool res, ok;
SysRes fd, sres;
- Word i;
+ Word i, j;
Bool dynbss_present = False;
Bool sdynbss_present = False;
@@ -1302,6 +1340,10 @@
Addr dimage = 0;
UWord n_dimage = 0;
+ /* Ditto for alternate ELF debuginfo file that we might happen to load. */
+ Addr aimage = 0;
+ UWord n_aimage = 0;
+
/* ELF header for the main file. Should == oimage since is at
start of file. */
ElfXX_Ehdr* ehdr_img = NULL;
@@ -1319,19 +1361,19 @@
UChar* shdr_strtab_img = NULL;
/* SVMAs covered by rx and rw segments and corresponding biases.
- We keep separate lists of rx and rw areas. Each can have up to
- N_RX_RW_AREAS entries. Normally each object would provide just
- one rx and one rw area, but Mike Hommey's elfhack creates
- objects with two rx PT_LOAD entries, hence the generality. */
- const Int N_RX_RW_AREAS = 2;
+ Normally each object would provide just one rx and one rw area,
+ but various ELF mangling tools create objects with multiple
+ such entries, hence the generality. */
+ typedef
+ struct {
+ Addr svma_base;
+ Addr svma_limit;
+ PtrdiffT bias;
+ Bool exec;
+ }
+ RangeAndBias;
- RangeAndBias rx[N_RX_RW_AREAS];
- RangeAndBias rw[N_RX_RW_AREAS];
- Word n_rx = 0; /* 0 .. N_RX_RW_AREAS */
- Word n_rw = 0; /* 0 .. N_RX_RW_AREAS */
- /* Pointless paranoia: */
- VG_(memset)( rx, 0, sizeof(rx) );
- VG_(memset)( rw, 0, sizeof(rw) );
+ XArray* /* of RangeAndBias */ svma_ranges = NULL;
/* Build ID */
Char* buildid = NULL;
@@ -1339,8 +1381,6 @@
vg_assert(di);
vg_assert(di->fsm.have_rx_map == True);
vg_assert(di->fsm.have_rw_map == True);
- vg_assert(di->fsm.rx_map_size > 0);
- vg_assert(di->fsm.rw_map_size > 0);
vg_assert(di->have_dinfo == False);
vg_assert(di->fsm.filename);
vg_assert(!di->symtab);
@@ -1350,19 +1390,32 @@
vg_assert(!di->strchunks);
vg_assert(!di->soname);
- /* If these don't hold true, it means that m_syswrap/m_aspacemgr
- managed to do a mapping where the start isn't page aligned.
- Which sounds pretty bogus to me. */
- vg_assert(VG_IS_PAGE_ALIGNED(di->fsm.rx_map_avma));
- vg_assert(VG_IS_PAGE_ALIGNED(di->fsm.rw_map_avma));
+ {
+ Bool has_nonempty_rx = False;
+ Bool has_nonempty_rw = False;
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ if (!map->rx && !map->rw)
+ continue;
+ if (map->rx && map->size > 0)
+ has_nonempty_rx = True;
+ if (map->rw && map->size > 0)
+ has_nonempty_rw = True;
+ /* If this doesn't hold true, it means that m_syswrap/m_aspacemgr
+ managed to do a mapping where the start isn't page aligned.
+ Which sounds pretty bogus to me. */
+ vg_assert(VG_IS_PAGE_ALIGNED(map->avma));
+ }
+ vg_assert(has_nonempty_rx);
+ vg_assert(has_nonempty_rw);
+ }
/* ----------------------------------------------------------
At this point, there is very little information in the
DebugInfo. We only know that something that looks like an ELF
- file has been mapped rx-ishly as recorded with the di->*rx_map*
- fields and has also been mapped rw-ishly as recorded with the
- di->*rw_map* fields. First we examine the file's ELF Program
- Header, and, by comparing that against the di->*r{w,x}_map*
+ file has been mapped rx-ishly and rw-ishly as recorded in the
+ di->fsm.maps array items. First we examine the file's ELF
+ Program Header, and, by comparing that against the di->fsm.maps
info, try to figure out the AVMAs for the sections we care
about, that should have been mapped: text, data, sdata, bss,
got, plt, and toc.
@@ -1372,8 +1425,8 @@
oimage = (Addr)NULL;
if (VG_(clo_verbosity) > 1 || VG_(clo_trace_redir))
- VG_(message)(Vg_DebugMsg, "Reading syms from %s (%#lx)\n",
- di->fsm.filename, di->fsm.rx_map_avma );
+ VG_(message)(Vg_DebugMsg, "Reading syms from %s\n",
+ di->fsm.filename );
/* mmap the object image aboard, so that we can read symbols and
line number info out of it. It will be munmapped immediately
@@ -1424,7 +1477,7 @@
ehdr_img = (ElfXX_Ehdr*)oimage;
if (ok)
- ok &= ML_(is_elf_object_file)(ehdr_img, n_oimage);
+ ok &= ML_(is_elf_object_file)(ehdr_img, n_oimage, False);
if (!ok) {
ML_(symerr)(di, True, "Invalid ELF Header");
@@ -1448,10 +1501,18 @@
phdr_img, phdr_nent, phdr_ent_szB);
TRACE_SYMTAB("shdr: img %p nent %ld ent_szB %ld\n",
shdr_img, shdr_nent, shdr_ent_szB);
- TRACE_SYMTAB("rx_map: avma %#lx size %lu foff %lu\n",
- di->fsm.rx_map_avma, di->fsm.rx_map_size, di->fsm.rx_map_foff);
- TRACE_SYMTAB("rw_map: avma %#lx size %lu foff %lu\n",
- di->fsm.rw_map_avma, di->fsm.rw_map_size, di->fsm.rw_map_foff);
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ if (map->rx)
+ TRACE_SYMTAB("rx_map: avma %#lx size %lu foff %lu\n",
+ map->avma, map->size, map->foff);
+ }
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ if (map->rw)
+ TRACE_SYMTAB("rw_map: avma %#lx size %lu foff %lu\n",
+ map->avma, map->size, map->foff);
+ }
if (phdr_nent == 0
|| !contained_within(
@@ -1485,10 +1546,12 @@
TRACE_SYMTAB("shdr: string table at %p\n", shdr_strtab_img );
+ svma_ranges = VG_(newXA)(ML_(dinfo_zalloc), "di.relfdi.1",
+ ML_(dinfo_free), sizeof(RangeAndBias));
+
/* TOPLEVEL */
/* Look through the program header table, and:
- - copy information from suitable PT_LOAD entries into rx[] or
- rw[]
+ - copy information from suitable PT_LOAD entries into svma_ranges
- find (or fake up) the .soname for this object.
*/
TRACE_SYMTAB("\n");
@@ -1503,10 +1566,8 @@
/* Make sure the PT_LOADable entries are in order and
non-overlapping. This in turn means the address ranges
- slurped into rx[] and rw[] are in order and
+ slurped into svma_ranges are in order and
non-overlapping. */
- vg_assert(n_rx >= 0 && n_rx <= N_RX_RW_AREAS);
- vg_assert(n_rw >= 0 && n_rw <= N_RX_RW_AREAS);
if (phdr->p_type == PT_LOAD) {
TRACE_SYMTAB("PT_LOAD[%ld]: p_vaddr %#lx (prev %#lx)\n",
@@ -1523,42 +1584,41 @@
goto out;
}
prev_svma = phdr->p_vaddr;
- if (phdr->p_offset >= di->fsm.rx_map_foff
- && phdr->p_offset < di->fsm.rx_map_foff + di->fsm.rx_map_size
- && phdr->p_offset + phdr->p_filesz
- <= di->fsm.rx_map_foff + di->fsm.rx_map_size
- && (phdr->p_flags & (PF_R | PF_W | PF_X)) == (PF_R | PF_X)) {
- if (n_rx == N_RX_RW_AREAS) {
- ML_(symerr)(di, True,
- "N_RX_RW_AREAS is too low; "
- "increase and recompile.");
+ if (phdr->p_memsz > 0) {
+ Bool loaded = False;
+ for (j = 0; j < VG_(sizeXA)(di->fsm.maps); j++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, j);
+ if ( (map->rx || map->rw)
+ && phdr->p_offset >= map->foff
+ && phdr->p_offset < map->foff + map->size
+ && phdr->p_offset + phdr->p_filesz <= map->foff
+ + map->size) {
+ RangeAndBias item;
+ item.svma_base = phdr->p_vaddr;
+ item.svma_limit = phdr->p_vaddr + phdr->p_memsz;
+ item.bias = map->avma - map->foff
+ + phdr->p_offset - phdr->p_vaddr;
+ if ( map->rw
+ && (phdr->p_flags & (PF_R | PF_W)) == (PF_R | PF_W)) {
+ item.exec = False;
+ VG_(addToXA)(svma_ranges, &item);
+ TRACE_SYMTAB("PT_LOAD[%ld]: acquired as rw\n", i);
+ loaded = True;
+ }
+ if ( map->rx
+ && (phdr->p_flags & (PF_R | PF_X)) == (PF_R | PF_X)) {
+ item.exec = True;
+ VG_(addToXA)(svma_ranges, &item);
+ TRACE_SYMTAB("PT_LOAD[%ld]: acquired as rx\n", i);
+ loaded = True;
+ }
+ }
+ }
+ if (!loaded) {
+ ML_(symerr)(di, False,
+ "ELF section outside all mapped regions");
goto out;
}
- rx[n_rx].svma_base = phdr->p_vaddr;
- rx[n_rx].svma_limit = phdr->p_vaddr + phdr->p_memsz;
- rx[n_rx].bias = di->fsm.rx_map_avma - di->fsm.rx_map_foff
- + phdr->p_offset - phdr->p_vaddr;
- n_rx++;
- TRACE_SYMTAB("PT_LOAD[%ld]: acquired as rx\n", i);
- }
- else
- if (phdr->p_offset >= di->fsm.rw_map_foff
- && phdr->p_offset < di->fsm.rw_map_foff + di->fsm.rw_map_size
- && phdr->p_offset + phdr->p_filesz
- <= di->fsm.rw_map_foff + di->fsm.rw_map_size
- && (phdr->p_flags & (PF_R | PF_W | PF_X)) == (PF_R | PF_W)) {
- if (n_rw == N_RX_RW_AREAS) {
- ML_(symerr)(di, True,
- "N_RX_RW_AREAS is too low; "
- "increase and recompile.");
- goto out;
- }
- rw[n_rw].svma_base = phdr->p_vaddr;
- rw[n_rw].svma_limit = phdr->p_vaddr + phdr->p_memsz;
- rw[n_rw].bias = di->fsm.rw_map_avma - di->fsm.rw_map_foff
- + phdr->p_offset - phdr->p_vaddr;
- n_rw++;
- TRACE_SYMTAB("PT_LOAD[%ld]: acquired as rw\n", i);
}
}
@@ -1571,7 +1631,6 @@
+ phdr->p_offset);
Word stroff = -1;
UChar* strtab = NULL;
- Word j;
for (j = 0; dyn_img[j].d_tag != DT_NULL; j++) {
switch (dyn_img[j].d_tag) {
case DT_SONAME: {
@@ -1612,46 +1671,39 @@
find a soname, add a fake one. */
if (di->soname == NULL) {
TRACE_SYMTAB("No soname found; using (fake) \"NONE\"\n");
- di->soname = "NONE";
+ di->soname = ML_(dinfo_strdup)("di.redi.2", "NONE");
}
- // NaCl nexe
- if (ehdr_img->e_ident[EI_OSABI] == 0x7b) {
- HChar* s = VG_(arena_malloc)(VG_AR_DINFO, "di.redi.1", 6 + VG_(strlen)(di->soname));
- VG_(strcpy)(s, "NaCl_");
- VG_(strcpy)(s + 5, di->soname);
- di->soname = s;
- TRACE_SYMTAB("Fixed soname = %s\n", di->soname);
- }
-
-
- vg_assert(n_rx >= 0 && n_rx <= N_RX_RW_AREAS);
- vg_assert(n_rw >= 0 && n_rw <= N_RX_RW_AREAS);
- for (i = 0; i < n_rx; i++) {
- vg_assert(rx[i].svma_limit != 0);
- }
- for (i = 0; i < n_rw; i++) {
- vg_assert(rw[i].svma_limit != 0);
- }
+ vg_assert(VG_(sizeXA)(svma_ranges) != 0);
/* Now read the section table. */
TRACE_SYMTAB("\n");
TRACE_SYMTAB("------ Examining the section headers ------\n");
- TRACE_SYMTAB("rx: at %#lx are mapped foffsets %ld .. %ld\n",
- di->fsm.rx_map_avma,
- di->fsm.rx_map_foff,
- di->fsm.rx_map_foff + di->fsm.rx_map_size - 1 );
- for (i = 0; i < n_rx; i++) {
- TRACE_SYMTAB("rx[%ld]: contains svmas %#lx .. %#lx with bias %#lx\n",
- i, rx[i].svma_base, rx[i].svma_limit - 1, rx[i].bias );
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ if (map->rx)
+ TRACE_SYMTAB("rx: at %#lx are mapped foffsets %ld .. %ld\n",
+ map->avma, map->foff, map->foff + map->size - 1 );
}
- TRACE_SYMTAB("rw: at %#lx are mapped foffsets %ld .. %ld\n",
- di->fsm.rw_map_avma,
- di->fsm.rw_map_foff,
- di->fsm.rw_map_foff + di->fsm.rw_map_size - 1 );
- for (i = 0; i < n_rw; i++) {
- TRACE_SYMTAB("rw[%ld]: contains svmas %#lx .. %#lx with bias %#lx\n",
- i, rw[i].svma_base, rw[i].svma_limit - 1, rw[i].bias );
+ TRACE_SYMTAB("rx: contains these svma regions:\n");
+ for (i = 0; i < VG_(sizeXA)(svma_ranges); i++) {
+ RangeAndBias* reg = VG_(indexXA)(svma_ranges, i);
+ if (reg->exec)
+ TRACE_SYMTAB(" svmas %#lx .. %#lx with bias %#lx\n",
+ reg->svma_base, reg->svma_limit - 1, reg->bias );
+ }
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ if (map->rw)
+ TRACE_SYMTAB("rw: at %#lx are mapped foffsets %ld .. %ld\n",
+ map->avma, map->foff, map->foff + map->size - 1 );
+ }
+ TRACE_SYMTAB("rw: contains these svma regions:\n");
+ for (i = 0; i < VG_(sizeXA)(svma_ranges); i++) {
+ RangeAndBias* reg = VG_(indexXA)(svma_ranges, i);
+ if (!reg->exec)
+ TRACE_SYMTAB(" svmas %#lx .. %#lx with bias %#lx\n",
+ reg->svma_base, reg->svma_limit - 1, reg->bias );
}
/* TOPLEVEL */
@@ -1670,19 +1722,17 @@
leave the relevant pointer at NULL. */
RangeAndBias* inrx = NULL;
RangeAndBias* inrw = NULL;
- { Word j;
- for (j = 0; j < n_rx; j++) {
- if (svma >= rx[j].svma_base && svma < rx[j].svma_limit) {
- inrx = &rx[j];
- break;
- }
- }
- for (j = 0; j < n_rw; j++) {
- if (svma >= rw[j].svma_base && svma < rw[j].svma_limit) {
- inrw = &rw[j];
- break;
- }
- }
+ for (j = 0; j < VG_(sizeXA)(svma_ranges); j++) {
+ RangeAndBias* rng = VG_(indexXA)(svma_ranges, j);
+ if (svma >= rng->svma_base && svma < rng->svma_limit) {
+ if (!inrx && rng->exec) {
+ inrx = rng;
+ } else if (!inrw && !rng->exec) {
+ inrw = rng;
+ }
+ if (inrx && inrw)
+ break;
+ }
}
TRACE_SYMTAB(" [sec %2ld] %s %s al%2u foff %6ld .. %6ld "
@@ -1692,8 +1742,7 @@
/* Check for sane-sized segments. SHT_NOBITS sections have zero
size in the file. */
- if (bits &&
- ((foff >= n_oimage) || (foff + (bits ? size : 0) > n_oimage))) {
+ if ((foff >= n_oimage) || (foff + (bits ? size : 0) > n_oimage)) {
ML_(symerr)(di, True, "ELF Section extends beyond image end");
goto out;
}
@@ -1973,7 +2022,8 @@
/* PLT is different on different platforms, it seems. */
# if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \
- || defined(VGP_arm_linux) || defined (VGP_s390x_linux)
+ || defined(VGP_arm_linux) || defined (VGP_s390x_linux) \
+ || defined(VGP_mips32_linux)
/* Accept .plt where mapped as rx (code) */
if (0 == VG_(strcmp)(name, ".plt")) {
if (inrx && size > 0 && !di->plt_present) {
@@ -2086,15 +2136,21 @@
UChar* dynstr_img = NULL; /* .dynstr */
ElfXX_Sym* dynsym_img = NULL; /* .dynsym */
UChar* debuglink_img = NULL; /* .gnu_debuglink */
+ UChar* debugaltlink_img = NULL; /* .gnu_debugaltlink */
UChar* stab_img = NULL; /* .stab (stabs) */
UChar* stabstr_img = NULL; /* .stabstr (stabs) */
UChar* debug_line_img = NULL; /* .debug_line (dwarf2) */
UChar* debug_info_img = NULL; /* .debug_info (dwarf2) */
+ UChar* debug_types_img = NULL; /* .debug_types (dwarf4) */
UChar* debug_abbv_img = NULL; /* .debug_abbrev (dwarf2) */
UChar* debug_str_img = NULL; /* .debug_str (dwarf2) */
UChar* debug_ranges_img = NULL; /* .debug_ranges (dwarf2) */
UChar* debug_loc_img = NULL; /* .debug_loc (dwarf2) */
UChar* debug_frame_img = NULL; /* .debug_frame (dwarf2) */
+ UChar* debug_line_alt_img = NULL; /* .debug_line (alternate) */
+ UChar* debug_info_alt_img = NULL; /* .debug_info (alternate) */
+ UChar* debug_abbv_alt_img = NULL; /* .debug_abbrev (alternate) */
+ UChar* debug_str_alt_img = NULL; /* .debug_str (alternate) */
UChar* dwarf1d_img = NULL; /* .debug (dwarf1) */
UChar* dwarf1l_img = NULL; /* .line (dwarf1) */
UChar* opd_img = NULL; /* .opd (dwarf2,
@@ -2107,15 +2163,21 @@
SizeT dynstr_sz = 0;
SizeT dynsym_sz = 0;
SizeT debuglink_sz = 0;
+ SizeT debugaltlink_sz = 0;
SizeT stab_sz = 0;
SizeT stabstr_sz = 0;
SizeT debug_line_sz = 0;
SizeT debug_info_sz = 0;
+ SizeT debug_types_sz = 0;
SizeT debug_abbv_sz = 0;
SizeT debug_str_sz = 0;
SizeT debug_ranges_sz = 0;
SizeT debug_loc_sz = 0;
SizeT debug_frame_sz = 0;
+ SizeT debug_line_alt_sz = 0;
+ SizeT debug_info_alt_sz = 0;
+ SizeT debug_abbv_alt_sz = 0;
+ SizeT debug_str_alt_sz = 0;
SizeT dwarf1d_sz = 0;
SizeT dwarf1l_sz = 0;
SizeT opd_sz_unused = 0;
@@ -2180,12 +2242,14 @@
FIND(".strtab", strtab_sz, strtab_img)
FIND(".gnu_debuglink", debuglink_sz, debuglink_img)
+ FIND(".gnu_debugaltlink", debugaltlink_sz, debugaltlink_img)
FIND(".stab", stab_sz, stab_img)
FIND(".stabstr", stabstr_sz, stabstr_img)
FIND(".debug_line", debug_line_sz, debug_line_img)
FIND(".debug_info", debug_info_sz, debug_info_img)
+ FIND(".debug_types", debug_types_sz, debug_types_img)
FIND(".debug_abbrev", debug_abbv_sz, debug_abbv_img)
FIND(".debug_str", debug_str_sz, debug_str_img)
FIND(".debug_ranges", debug_ranges_sz, debug_ranges_img)
@@ -2224,7 +2288,7 @@
vg_assert(dimage == 0 && n_dimage == 0);
/* Look for a build-id */
- buildid = find_buildid(oimage, n_oimage);
+ buildid = find_buildid(oimage, n_oimage, False);
/* Look for a debug image */
if (buildid != NULL || debuglink_img != NULL) {
@@ -2240,11 +2304,11 @@
/* See if we can find a matching debug file */
find_debug_file( di, di->fsm.filename, buildid,
- debuglink_img, crc, &dimage, &n_dimage );
+ debuglink_img, crc, False, &dimage, &n_dimage );
} else {
/* See if we can find a matching debug file */
find_debug_file( di, di->fsm.filename, buildid,
- NULL, 0, &dimage, &n_dimage );
+ NULL, 0, False, &dimage, &n_dimage );
}
}
@@ -2267,7 +2331,7 @@
SVMA/bias/size and image addresses out of it. */
if (dimage != 0
&& n_dimage >= sizeof(ElfXX_Ehdr)
- && ML_(is_elf_object_file)((void*)dimage, n_dimage)) {
+ && ML_(is_elf_object_file)((void*)dimage, n_dimage, False)) {
/* Pull out and validate program header and section header info */
ElfXX_Ehdr* ehdr_dimg = (ElfXX_Ehdr*)dimage;
@@ -2282,10 +2346,8 @@
UChar* shdr_strtab_dimg = NULL;
/* SVMAs covered by rx and rw segments and corresponding bias. */
- /* Addr rx_dsvma_base = 0; */ /* UNUSED */
Addr rx_dsvma_limit = 0;
PtrdiffT rx_dbias = 0;
- /* Addr rw_dsvma_base = 0; */ /* UNUSED */
Addr rw_dsvma_limit = 0;
PtrdiffT rw_dbias = 0;
@@ -2338,28 +2400,24 @@
= INDEX_BIS( (void*)(dimage + ehdr_dimg->e_phoff),
i, phdr_ent_szB );
if (phdr->p_type == PT_LOAD) {
- if (rx_dsvma_limit == 0
- && phdr->p_offset >= di->fsm.rx_map_foff
- && phdr->p_offset
- < di->fsm.rx_map_foff + di->fsm.rx_map_size
- && phdr->p_offset + phdr->p_filesz
- <= di->fsm.rx_map_foff + di->fsm.rx_map_size) {
- /* rx_dsvma_base = phdr->p_vaddr; */ /* UNUSED */
- rx_dsvma_limit = phdr->p_vaddr + phdr->p_memsz;
- rx_dbias = di->fsm.rx_map_avma - di->fsm.rx_map_foff
- + phdr->p_offset - phdr->p_vaddr;
- }
- else
- if (rw_dsvma_limit == 0
- && phdr->p_offset >= di->fsm.rw_map_foff
- && phdr->p_offset
- < di->fsm.rw_map_foff + di->fsm.rw_map_size
- && phdr->p_offset + phdr->p_filesz
- <= di->fsm.rw_map_foff + di->fsm.rw_map_size) {
- /* rw_dsvma_base = phdr->p_vaddr; */ /* UNUSED */
- rw_dsvma_limit = phdr->p_vaddr + phdr->p_memsz;
- rw_dbias = di->fsm.rw_map_avma - di->fsm.rw_map_foff
- + phdr->p_offset - phdr->p_vaddr;
+ for (j = 0; j < VG_(sizeXA)(di->fsm.maps); j++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, j);
+ if ( phdr->p_offset >= map->foff
+ && phdr->p_offset < map->foff + map->size
+ && phdr->p_offset + phdr->p_filesz < map->foff
+ + map->size) {
+ if (map->rx && rx_dsvma_limit == 0) {
+ rx_dsvma_limit = phdr->p_vaddr + phdr->p_memsz;
+ rx_dbias = map->avma - map->foff + phdr->p_offset
+ - phdr->p_vaddr;
+ }
+ if (map->rw && rw_dsvma_limit == 0) {
+ rw_dsvma_limit = phdr->p_vaddr + phdr->p_memsz;
+ rw_dbias = map->avma - map->foff + phdr->p_offset
+ - phdr->p_vaddr;
+ }
+ break;
+ }
}
}
}
@@ -2443,6 +2501,8 @@
FIND(need_stabs, ".stabstr", stabstr_sz, stabstr_img)
FIND(need_dwarf2, ".debug_line", debug_line_sz, debug_line_img)
FIND(need_dwarf2, ".debug_info", debug_info_sz, debug_info_img)
+ FIND(need_dwarf2, ".debug_types", debug_types_sz,
+ debug_types_img)
FIND(need_dwarf2, ".debug_abbrev", debug_abbv_sz, debug_abbv_img)
FIND(need_dwarf2, ".debug_str", debug_str_sz, debug_str_img)
FIND(need_dwarf2, ".debug_ranges", debug_ranges_sz,
@@ -2450,6 +2510,8 @@
FIND(need_dwarf2, ".debug_loc", debug_loc_sz, debug_loc_img)
FIND(need_dwarf2, ".debug_frame", debug_frame_sz,
debug_frame_img)
+ FIND(need_dwarf2, ".gnu_debugaltlink", debugaltlink_sz,
+ debugaltlink_img)
FIND(need_dwarf1, ".debug", dwarf1d_sz, dwarf1d_img)
FIND(need_dwarf1, ".line", dwarf1l_sz, dwarf1l_img)
@@ -2457,6 +2519,100 @@
} /* Find all interesting sections */
} /* do we have a debug image? */
+ /* Look for alternate debug image */
+ if (debugaltlink_img != NULL) {
+ UInt buildid_offset = VG_(strlen)(debugaltlink_img)+1;
+
+ vg_assert(buildid_offset < debugaltlink_sz);
+
+ Char *altbuildid
+ = ML_(dinfo_zalloc)("di.fbi.4",
+ (debugaltlink_sz - buildid_offset)
+ * 2 + 1);
+
+ for (j = 0; j < debugaltlink_sz - buildid_offset; j++)
+ VG_(sprintf)(altbuildid + 2 * j,
+ "%02x", debugaltlink_img[buildid_offset + j]);
+
+ /* See if we can find a matching debug file */
+ find_debug_file( di, di->fsm.filename, altbuildid,
+ NULL, 0, True, &aimage, &n_aimage );
+
+ ML_(dinfo_free)(altbuildid);
+ }
+
+ /* TOPLEVEL */
+ /* If we were successful in finding alternate debug image, pull various
+ size and image addresses out of it. */
+ if (aimage != 0
+ && n_aimage >= sizeof(ElfXX_Ehdr)
+ && ML_(is_elf_object_file)((void*)aimage, n_aimage, True)) {
+
+ /* Pull out and validate program header and section header info */
+ ElfXX_Ehdr* ehdr_aimg = (ElfXX_Ehdr*)aimage;
+ ElfXX_Shdr* shdr_aimg = (ElfXX_Shdr*)( ((UChar*)ehdr_aimg)
+ + ehdr_aimg->e_shoff );
+ UWord shdr_dnent = ehdr_aimg->e_shnum;
+ UWord shdr_dent_szB = ehdr_aimg->e_shentsize;
+ UChar* shdr_strtab_aimg = NULL;
+
+ if (shdr_dnent == 0
+ || !contained_within(
+ aimage, n_aimage,
+ (Addr)shdr_aimg, shdr_dnent * shdr_dent_szB)) {
+ ML_(symerr)(di, True,
+ "Missing or invalid ELF Section Header Table"
+ " (alternate debuginfo file)");
+ goto out;
+ }
+
+ /* Also find the section header's string table, and validate. */
+ /* checked previously by is_elf_object_file: */
+ vg_assert( ehdr_aimg->e_shstrndx != SHN_UNDEF );
+
+ shdr_strtab_aimg
+ = (UChar*)( ((UChar*)ehdr_aimg)
+ + shdr_aimg[ehdr_aimg->e_shstrndx].sh_offset);
+ if (!contained_within(
+ aimage, n_aimage,
+ (Addr)shdr_strtab_aimg,
+ 1/*bogus, but we don't know the real size*/ )) {
+ ML_(symerr)(di, True,
+ "Invalid ELF Section Header String Table"
+ " (alternate debuginfo file)");
+ goto out;
+ }
+
+ /* Find all interesting sections */
+ for (i = 0; i < ehdr_aimg->e_shnum; i++) {
+
+# define FIND(sec_name, sec_size, sec_img) \
+ do { ElfXX_Shdr* shdr \
+ = INDEX_BIS( shdr_aimg, i, shdr_dent_szB ); \
+ if (0 == VG_(strcmp)(sec_name, \
+ shdr_strtab_aimg + shdr->sh_name)) { \
+ if (0 != sec_img) \
+ VG_(core_panic)("repeated section!\n"); \
+ sec_img = (void*)(aimage + shdr->sh_offset); \
+ sec_size = shdr->sh_size; \
+ TRACE_SYMTAB( "%18s: aimg %p .. %p\n", \
+ sec_name, \
+ (UChar*)sec_img, \
+ ((UChar*)sec_img) + sec_size - 1); \
+ } \
+ } while (0);
+
+ /* NAME SIZE IMAGE addr */
+ FIND(".debug_line", debug_line_alt_sz, debug_line_alt_img)
+ FIND(".debug_info", debug_info_alt_sz, debug_info_alt_img)
+ FIND(".debug_abbrev", debug_abbv_alt_sz, debug_abbv_alt_img)
+ FIND(".debug_str", debug_str_alt_sz, debug_str_alt_img)
+
+# undef FIND
+ } /* Find all interesting sections */
+ } /* do we have a debug image? */
+
+
/* TOPLEVEL */
/* Check some sizes */
vg_assert((dynsym_sz % sizeof(ElfXX_Sym)) == 0);
@@ -2535,9 +2691,11 @@
/* The old reader: line numbers and unwind info only */
ML_(read_debuginfo_dwarf3) ( di,
debug_info_img, debug_info_sz,
+ debug_types_img, debug_types_sz,
debug_abbv_img, debug_abbv_sz,
debug_line_img, debug_line_sz,
- debug_str_img, debug_str_sz );
+ debug_str_img, debug_str_sz,
+ debug_str_alt_img, debug_str_alt_sz );
/* The new reader: read the DIEs in .debug_info to acquire
information on variable types and locations. But only if
@@ -2547,11 +2705,16 @@
|| VG_(clo_read_var_info) /* the user asked for it */) {
ML_(new_dwarf3_reader)(
di, debug_info_img, debug_info_sz,
+ debug_types_img, debug_types_sz,
debug_abbv_img, debug_abbv_sz,
debug_line_img, debug_line_sz,
debug_str_img, debug_str_sz,
debug_ranges_img, debug_ranges_sz,
- debug_loc_img, debug_loc_sz
+ debug_loc_img, debug_loc_sz,
+ debug_info_alt_img, debug_info_alt_sz,
+ debug_abbv_alt_img, debug_abbv_alt_sz,
+ debug_line_alt_img, debug_line_alt_sz,
+ debug_str_alt_img, debug_str_alt_sz
);
}
}
@@ -2573,7 +2736,6 @@
exp-sgcheck.) */
if (0 && (VG_(needs).var_info || VG_(clo_read_var_info))) {
UWord nVars = 0;
- Word j;
if (di->varinfo) {
for (j = 0; j < VG_(sizeXA)(di->varinfo); j++) {
OSet* /* of DiAddrRange */ scope
@@ -2607,6 +2769,10 @@
}
m_res = VG_(am_munmap_valgrind) ( oimage, n_oimage );
vg_assert(!sr_isError(m_res));
+
+ if (svma_ranges)
+ VG_(deleteXA)(svma_ranges);
+
return res;
} /* out: */
diff --git a/main/coregrind/m_debuginfo/readmacho.c b/main/coregrind/m_debuginfo/readmacho.c
index 8487243..e12c7d7 100644
--- a/main/coregrind/m_debuginfo/readmacho.c
+++ b/main/coregrind/m_debuginfo/readmacho.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Apple Inc.
+ Copyright (C) 2005-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -676,19 +676,35 @@
ImageInfo ii; /* main file */
ImageInfo iid; /* auxiliary .dSYM file */
Bool ok;
+ Word i;
+ struct _DebugInfoMapping* rx_map = NULL;
+ struct _DebugInfoMapping* rw_map = NULL;
/* mmap the object file to look for di->soname and di->text_bias
and uuid and nlist and STABS */
- if (VG_(clo_verbosity) > 1)
- VG_(message)(Vg_DebugMsg,
- "%s (%#lx)\n", di->fsm.filename, di->fsm.rx_map_avma );
-
/* This should be ensured by our caller (that we're in the accept
state). */
vg_assert(di->fsm.have_rx_map);
vg_assert(di->fsm.have_rw_map);
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ if (map->rx && !rx_map)
+ rx_map = map;
+ if (map->rw && !rw_map)
+ rw_map = map;
+ if (rx_map && rw_map)
+ break;
+ }
+ vg_assert(rx_map);
+ vg_assert(rw_map);
+
+ if (VG_(clo_verbosity) > 1)
+ VG_(message)(Vg_DebugMsg,
+ "%s (rx at %#lx, rw at %#lx)\n", di->fsm.filename,
+ rx_map->avma, rw_map->avma );
+
VG_(memset)(&ii, 0, sizeof(ii));
VG_(memset)(&iid, 0, sizeof(iid));
VG_(memset)(&uuid, 0, sizeof(uuid));
@@ -779,7 +795,7 @@
&& seg->fileoff == 0 && seg->filesize != 0) {
di->text_present = True;
di->text_svma = (Addr)seg->vmaddr;
- di->text_avma = di->fsm.rx_map_avma;
+ di->text_avma = rx_map->avma;
di->text_size = seg->vmsize;
di->text_bias = di->text_avma - di->text_svma;
/* Make the _debug_ values be the same as the
@@ -796,7 +812,7 @@
/* && DDD:seg->fileoff == 0 */ && seg->filesize != 0) {
di->data_present = True;
di->data_svma = (Addr)seg->vmaddr;
- di->data_avma = di->fsm.rw_map_avma;
+ di->data_avma = rw_map->avma;
di->data_size = seg->vmsize;
di->data_bias = di->data_avma - di->data_svma;
di->data_debug_svma = di->data_svma;
@@ -829,7 +845,7 @@
struct NLIST *syms;
UChar *strs;
XArray* /* DiSym */ candSyms = NULL;
- Word i, nCandSyms;
+ Word nCandSyms;
if (ii.macho_img_szB < symcmd->stroff + symcmd->strsize
|| ii.macho_img_szB < symcmd->symoff + symcmd->nsyms
@@ -1068,9 +1084,11 @@
/* The old reader: line numbers and unwind info only */
ML_(read_debuginfo_dwarf3) ( di,
debug_info_img, debug_info_sz,
+ NULL, 0,
debug_abbv_img, debug_abbv_sz,
debug_line_img, debug_line_sz,
- debug_str_img, debug_str_sz );
+ debug_str_img, debug_str_sz,
+ NULL, 0 /* ALT .debug_str */ );
/* The new reader: read the DIEs in .debug_info to acquire
information on variable types and locations. But only if
@@ -1080,11 +1098,16 @@
|| VG_(clo_read_var_info) /* the user asked for it */) {
ML_(new_dwarf3_reader)(
di, debug_info_img, debug_info_sz,
+ NULL, 0,
debug_abbv_img, debug_abbv_sz,
debug_line_img, debug_line_sz,
debug_str_img, debug_str_sz,
debug_ranges_img, debug_ranges_sz,
- debug_loc_img, debug_loc_sz
+ debug_loc_img, debug_loc_sz,
+ NULL, 0, /* ALT .debug_info */
+ NULL, 0, /* ALT .debug_abbv */
+ NULL, 0, /* ALT .debug_line */
+ NULL, 0 /* ALT .debug_str */
);
}
}
diff --git a/main/coregrind/m_debuginfo/readpdb.c b/main/coregrind/m_debuginfo/readpdb.c
index b8febf8..a29c443 100644
--- a/main/coregrind/m_debuginfo/readpdb.c
+++ b/main/coregrind/m_debuginfo/readpdb.c
@@ -11,7 +11,7 @@
derived from readelf.c and valgrind-20031012-wine/vg_symtab2.c
derived from wine-1.0/tools/winedump/pdb.c and msc.c
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
Copyright 2006 Eric Pouech (winedump/pdb.c and msc.c)
GNU Lesser General Public License version 2.1 or later applies.
@@ -61,46 +61,23 @@
/*--- ---*/
/*------------------------------------------------------------*/
-/* JRS 2009-Apr-13: Mostly this PDB reader is straightforward. But
- the biasing is incomprehensible, and I don't claim to understand it
- at all. There are four places where biasing is required:
+/* There are just two simple ways of biasing in use here.
- - when reading symbol addresses (DEBUG_SnarfCodeView)
- - when reading old-style line number tables (DEBUG_SnarfLinetab)
- - when reading new-style line number tables (codeview_dump_linetab2)
- - when reading FPO (stack-unwind) tables (pdb_dump)
+ The CodeView debug info entries contain virtual addresses
+ relative to segment (here it is one PE section), which in
+ turn specifies its start as a VA relative to "image base".
- To complicate matters further, Wine supplies us, via the
- VG_USERREQ__LOAD_PDB_DEBUGINFO client request that initiates PDB
- reading, a value 'unknown_purpose__reloc' which, if you read
- 'virtual.c' in the Wine sources, looks a lot like a text bias
- value. Yet the code below ignores it.
+ The second type of debug info (FPOs) contain VAs relative
+ directly to the image base, without the segment indirection.
- To make future experimentation with biasing easier, here are four
- macros which give the bias to use in each of the four cases. Be
- warned, they can and do refer to local vars in the relevant
- functions. */
+ The original/preferred image base is set in the PE header,
+ but it can change as long as the file contains relocation
+ data. So everything is biased using the current image base,
+ which is the base AVMA passed by Wine.
-/* The BIAS_FOR_{SYMBOLS,LINETAB,LINETAB2} are as in JohnR's original
- patch. BIAS_FOR_FPO was originally hardwired to zero, but that
- doesn't make much sense. Here, we use text_bias as empirically
- producing the most ranges that fall inside the text segments for a
- multi-dll program. Of course, it could still be nonsense :-) */
-#define BIAS_FOR_SYMBOLS (di->fsm.rx_map_avma)
-#define BIAS_FOR_LINETAB (di->fsm.rx_map_avma)
-#define BIAS_FOR_LINETAB2 (di->text_bias)
-#define BIAS_FOR_FPO (di->text_bias)
-/* Using di->text_bias for the FPOs causes 981 in range and 1 out of
- range. Using rx_map_avma gives 953 in range and 29 out of range,
- so di->text_bias looks like a better bet.:
- $ grep FPO spew-B-text_bias | grep keep | wc
- 981 4905 57429
- $ grep FPO spew-B-text_bias | grep SKIP | wc
- 1 5 53
- $ grep FPO spew-B-rx_map_avma | grep keep | wc
- 953 4765 55945
- $ grep FPO spew-B-rx_map_avma | grep SKIP | wc
- 29 145 1537
+ The difference between the original image base and current
+ image base, which is what Wine sends here in the last
+ argument of VG_(di_notify_pdb_debuginfo), is not used.
*/
/* This module leaks space; enable m_main's calling of
@@ -1223,6 +1200,7 @@
static ULong DEBUG_SnarfCodeView(
DebugInfo* di,
+ PtrdiffT bias,
IMAGE_SECTION_HEADER* sectp,
void* root, /* FIXME: better name */
Int offset,
@@ -1235,7 +1213,6 @@
Char symname[4096 /*WIN32_PATH_MAX*/];
Bool debug = di->trace_symtab;
- Addr bias = BIAS_FOR_SYMBOLS;
ULong n_syms_read = 0;
if (debug)
@@ -1538,6 +1515,7 @@
static ULong DEBUG_SnarfLinetab(
DebugInfo* di,
+ PtrdiffT bias,
IMAGE_SECTION_HEADER* sectp,
Char* linetab,
Int size
@@ -1559,7 +1537,6 @@
Int this_seg;
Bool debug = di->trace_symtab;
- Addr bias = BIAS_FOR_LINETAB;
ULong n_lines_read = 0;
if (debug)
@@ -1708,6 +1685,8 @@
static ULong codeview_dump_linetab2(
DebugInfo* di,
+ Addr bias,
+ IMAGE_SECTION_HEADER* sectp,
Char* linetab,
DWORD size,
Char* strimage,
@@ -1721,7 +1700,6 @@
struct codeview_linetab2_file* fd;
Bool debug = di->trace_symtab;
- Addr bias = BIAS_FOR_LINETAB2;
ULong n_line2s_read = 0;
if (*(const DWORD*)linetab != 0x000000f4)
@@ -1780,8 +1758,10 @@
if (lbh->nlines > 1) {
for (i = 0; i < lbh->nlines-1; i++) {
- svma_s = lbh->start + lbh->l[i].offset;
- svma_e = lbh->start + lbh->l[i+1].offset-1;
+ svma_s = sectp[lbh->seg - 1].VirtualAddress + lbh->start
+ + lbh->l[i].offset;
+ svma_e = sectp[lbh->seg - 1].VirtualAddress + lbh->start
+ + lbh->l[i+1].offset-1;
if (debug)
VG_(printf)("%s line %d: %08lx to %08lx\n",
pfx, lbh->l[i].lineno ^ 0x80000000, svma_s, svma_e);
@@ -1791,8 +1771,10 @@
lbh->l[i].lineno ^ 0x80000000, 0 );
n_line2s_read++;
}
- svma_s = lbh->start + lbh->l[ lbh->nlines-1].offset;
- svma_e = lbh->start + lbh->size - 1;
+ svma_s = sectp[lbh->seg - 1].VirtualAddress + lbh->start
+ + lbh->l[ lbh->nlines-1].offset;
+ svma_e = sectp[lbh->seg - 1].VirtualAddress + lbh->start
+ + lbh->size - 1;
if (debug)
VG_(printf)("%s line %d: %08lx to %08lx\n",
pfx, lbh->l[ lbh->nlines-1 ].lineno ^ 0x80000000,
@@ -1835,8 +1817,8 @@
/* JRS fixme: compare with version in current Wine sources */
static void pdb_dump( struct pdb_reader* pdb,
DebugInfo* di,
- Addr pe_avma,
- Int unknown_purpose__reloc,
+ Addr pe_avma,
+ PtrdiffT pe_bias,
IMAGE_SECTION_HEADER* sectp_avma )
{
Int header_size;
@@ -1848,7 +1830,6 @@
char *file;
Bool debug = di->trace_symtab;
- Addr bias_for_fpo = BIAS_FOR_FPO;
ULong n_fpos_read = 0, n_syms_read = 0,
n_lines_read = 0, n_line2s_read = 0;
@@ -1875,26 +1856,6 @@
}
}
- if (VG_(clo_verbosity) > 1) {
- VG_(message)(Vg_DebugMsg,
- "PDB_READER:\n");
- VG_(message)(Vg_DebugMsg,
- " BIAS_FOR_SYMBOLS = %#08lx %s\n",
- (PtrdiffT)BIAS_FOR_SYMBOLS, VG_STRINGIFY(BIAS_FOR_SYMBOLS));
- VG_(message)(Vg_DebugMsg,
- " BIAS_FOR_LINETAB = %#08lx %s\n",
- (PtrdiffT)BIAS_FOR_LINETAB, VG_STRINGIFY(BIAS_FOR_LINETAB));
- VG_(message)(Vg_DebugMsg,
- " BIAS_FOR_LINETAB2 = %#08lx %s\n",
- (PtrdiffT)BIAS_FOR_LINETAB2, VG_STRINGIFY(BIAS_FOR_LINETAB2));
- VG_(message)(Vg_DebugMsg,
- " BIAS_FOR_FPO = %#08lx %s\n",
- (PtrdiffT)BIAS_FOR_FPO, VG_STRINGIFY(BIAS_FOR_FPO));
- VG_(message)(Vg_DebugMsg,
- " RELOC = %#08lx\n",
- (PtrdiffT)unknown_purpose__reloc);
- }
-
/* Since we just use the FPO data without reformatting, at least
do a basic sanity check on the struct layout. */
vg_assert(sizeof(FPO_DATA) == 16);
@@ -1914,6 +1875,7 @@
di->fpo_size = sz;
if (0) VG_(printf)("FPO: got fpo_size %lu\n", (UWord)sz);
vg_assert(0 == (di->fpo_size % sizeof(FPO_DATA)));
+ di->fpo_base_avma = pe_avma;
} else {
vg_assert(di->fpo == NULL);
vg_assert(di->fpo_size == 0);
@@ -1997,7 +1959,7 @@
/* Now bias the table. This can't be done in the same pass as
the sanity check, hence a second loop. */
for (i = 0; i < di->fpo_size; i++) {
- di->fpo[i].ulOffStart += bias_for_fpo;
+ di->fpo[i].ulOffStart += pe_avma;
// make sure the biasing didn't royally screw up, by wrapping
// the range around the end of the address space
vg_assert(0xFFFFFFFF - di->fpo[i].ulOffStart /* "remaining space" */
@@ -2098,7 +2060,7 @@
VG_(umsg)("\n");
if (VG_(clo_verbosity) > 1)
VG_(message)(Vg_UserMsg, "Reading global symbols\n" );
- DEBUG_SnarfCodeView( di, sectp_avma, modimage, 0, len_modimage );
+ DEBUG_SnarfCodeView( di, pe_avma, sectp_avma, modimage, 0, len_modimage );
ML_(dinfo_free)( (void*)modimage );
}
@@ -2141,7 +2103,7 @@
VG_(message)(Vg_UserMsg, "Reading symbols for %s\n",
file_name );
n_syms_read
- += DEBUG_SnarfCodeView( di, sectp_avma, modimage,
+ += DEBUG_SnarfCodeView( di, pe_avma, sectp_avma, modimage,
sizeof(unsigned long),
symbol_size );
}
@@ -2152,7 +2114,7 @@
if (VG_(clo_verbosity) > 1)
VG_(message)(Vg_UserMsg, "Reading lines for %s\n", file_name );
n_lines_read
- += DEBUG_SnarfLinetab( di, sectp_avma,
+ += DEBUG_SnarfLinetab( di, pe_avma, sectp_avma,
modimage + symbol_size, lineno_size );
}
@@ -2162,7 +2124,8 @@
*/
n_line2s_read
+= codeview_dump_linetab2(
- di, (char*)modimage + symbol_size + lineno_size,
+ di, pe_avma, sectp_avma,
+ (char*)modimage + symbol_size + lineno_size,
total_size - (symbol_size + lineno_size),
/* if filesimage is NULL, pass that directly onwards
to codeview_dump_linetab2, so it knows not to
@@ -2211,7 +2174,7 @@
Bool ML_(read_pdb_debug_info)(
DebugInfo* di,
Addr obj_avma,
- PtrdiffT unknown_purpose__reloc,
+ PtrdiffT obj_bias,
void* pdbimage,
SizeT n_pdbimage,
Char* pdbname,
@@ -2249,8 +2212,7 @@
);
/* JRS: this seems like something of a hack. */
-// di->soname = ML_(dinfo_strdup)("di.readpdb.rpdi.1", pdbname);
- di->soname = "NONE";
+ di->soname = ML_(dinfo_strdup)("di.readpdb.rpdi.1", pdbname);
/* someone (ie WINE) is loading a Windows PE format object. we
need to use its details to determine which area of memory is
@@ -2260,29 +2222,34 @@
+ OFFSET_OF(IMAGE_NT_HEADERS, OptionalHeader)
+ ntheaders_avma->FileHeader.SizeOfOptionalHeader;
- di->fsm.rx_map_avma = (Addr)obj_avma;
-
- /* Iterate over PE(?) headers. Try to establish the text_bias,
- that's all we really care about. */
+ /* Iterate over PE headers and fill our section mapping table. */
for ( i = 0;
i < ntheaders_avma->FileHeader.NumberOfSections;
i++, pe_seg_avma += sizeof(IMAGE_SECTION_HEADER) ) {
pe_sechdr_avma = (IMAGE_SECTION_HEADER *)pe_seg_avma;
- if (VG_(clo_verbosity) > 1)
+ if (VG_(clo_verbosity) > 1) {
+ /* Copy name, it can be 8 chars and not NUL-terminated */
+ char name[9];
+ VG_(memcpy)(name, pe_sechdr_avma->Name, 8);
+ name[8] = '\0';
VG_(message)(Vg_UserMsg,
- " Scanning PE section %s at avma %p svma %#lx\n",
- pe_sechdr_avma->Name, pe_seg_avma,
+ " Scanning PE section %ps at avma %#lx svma %#lx\n",
+ name, obj_avma + pe_sechdr_avma->VirtualAddress,
pe_sechdr_avma->VirtualAddress);
+ }
if (pe_sechdr_avma->Characteristics & IMAGE_SCN_MEM_DISCARDABLE)
continue;
mapped_avma = (Addr)obj_avma + pe_sechdr_avma->VirtualAddress;
mapped_end_avma = mapped_avma + pe_sechdr_avma->Misc.VirtualSize;
- if (VG_(clo_verbosity) > 1)
- VG_(message)(Vg_DebugMsg,
- " ::: mapped_avma is %#lx\n", mapped_avma);
+
+ struct _DebugInfoMapping map;
+ map.avma = mapped_avma;
+ map.size = pe_sechdr_avma->Misc.VirtualSize;
+ map.foff = pe_sechdr_avma->PointerToRawData;
+ map.ro = False;
if (pe_sechdr_avma->Characteristics & IMAGE_SCN_CNT_CODE) {
/* Ignore uninitialised code sections - if you have
@@ -2291,60 +2258,44 @@
the real text section and valgrind will compute the wrong
avma value and hence the wrong bias. */
if (!(pe_sechdr_avma->Characteristics & IMAGE_SCN_CNT_UNINITIALIZED_DATA)) {
+ map.rx = True;
+ map.rw = False;
+ VG_(addToXA)(di->fsm.maps, &map);
di->fsm.have_rx_map = True;
- if (di->fsm.rx_map_avma == 0) {
- di->fsm.rx_map_avma = mapped_avma;
- }
- if (di->fsm.rx_map_size==0) {
- di->fsm.rx_map_foff = pe_sechdr_avma->PointerToRawData;
- }
+
di->text_present = True;
- if (di->text_avma==0) {
+ if (di->text_avma == 0) {
+ di->text_svma = pe_sechdr_avma->VirtualAddress;
di->text_avma = mapped_avma;
+ di->text_size = pe_sechdr_avma->Misc.VirtualSize;
+ } else {
+ di->text_size = mapped_end_avma - di->text_avma;
}
- di->text_size += pe_sechdr_avma->Misc.VirtualSize;
- di->fsm.rx_map_size += pe_sechdr_avma->Misc.VirtualSize;
}
}
else if (pe_sechdr_avma->Characteristics
& IMAGE_SCN_CNT_INITIALIZED_DATA) {
+ map.rx = False;
+ map.rw = True;
+ VG_(addToXA)(di->fsm.maps, &map);
di->fsm.have_rw_map = True;
- if (di->fsm.rw_map_avma == 0) {
- di->fsm.rw_map_avma = mapped_avma;
- }
- if (di->fsm.rw_map_size==0) {
- di->fsm.rw_map_foff = pe_sechdr_avma->PointerToRawData;
- }
+
di->data_present = True;
- if (di->data_avma==0) {
+ if (di->data_avma == 0) {
di->data_avma = mapped_avma;
+ di->data_size = pe_sechdr_avma->Misc.VirtualSize;
+ } else {
+ di->data_size = mapped_end_avma - di->data_avma;
}
- di->fsm.rw_map_size += pe_sechdr_avma->Misc.VirtualSize;
- di->data_size += pe_sechdr_avma->Misc.VirtualSize;
}
else if (pe_sechdr_avma->Characteristics
& IMAGE_SCN_CNT_UNINITIALIZED_DATA) {
di->bss_present = True;
- di->bss_avma = mapped_avma;
- di->bss_size = pe_sechdr_avma->Misc.VirtualSize;
- }
-
- mapped_avma = VG_PGROUNDDN(mapped_avma);
- mapped_end_avma = VG_PGROUNDUP(mapped_end_avma);
-
- /* Urr. These tests are bogus; ->fsm.rx_map_avma is not necessarily
- the start of the text section. */
- if ((1 /*VG_(needs).data_syms*/
- || (pe_sechdr_avma->Characteristics & IMAGE_SCN_CNT_CODE))
- && mapped_avma >= di->fsm.rx_map_avma
- && mapped_avma <= (di->fsm.rx_map_avma+di->text_size)
- && mapped_end_avma > (di->fsm.rx_map_avma+di->text_size)) {
- UInt newsz = mapped_end_avma - di->fsm.rx_map_avma;
- if (newsz > di->text_size) {
- /* extending the mapping is always needed for PE files
- under WINE */
- di->text_size = newsz;
- di->fsm.rx_map_size = newsz;
+ if (di->bss_avma == 0) {
+ di->bss_avma = mapped_avma;
+ di->bss_size = pe_sechdr_avma->Misc.VirtualSize;
+ } else {
+ di->bss_size = mapped_end_avma - di->bss_avma;
}
}
}
@@ -2358,21 +2309,23 @@
TRACE_SYMTAB("\n");
}
- if (di->text_present) {
- di->text_bias = di->text_avma - di->text_svma;
- } else {
- di->text_bias = 0;
- }
+ di->text_bias = obj_bias;
if (VG_(clo_verbosity) > 1) {
- VG_(message)(Vg_DebugMsg,
- "rx_map: avma %#lx size %7lu foff %llu\n",
- di->fsm.rx_map_avma, di->fsm.rx_map_size,
- (Off64T)di->fsm.rx_map_foff);
- VG_(message)(Vg_DebugMsg,
- "rw_map: avma %#lx size %7lu foff %llu\n",
- di->fsm.rw_map_avma, di->fsm.rw_map_size,
- (Off64T)di->fsm.rw_map_foff);
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ if (map->rx)
+ VG_(message)(Vg_DebugMsg,
+ "rx_map: avma %#lx size %7lu foff %llu\n",
+ map->avma, map->size, (Off64T)map->foff);
+ }
+ for (i = 0; i < VG_(sizeXA)(di->fsm.maps); i++) {
+ struct _DebugInfoMapping* map = VG_(indexXA)(di->fsm.maps, i);
+ if (map->rw)
+ VG_(message)(Vg_DebugMsg,
+ "rw_map: avma %#lx size %7lu foff %llu\n",
+ map->avma, map->size, (Off64T)map->foff);
+ }
VG_(message)(Vg_DebugMsg,
" text: avma %#lx svma %#lx size %7lu bias %#lx\n",
@@ -2400,7 +2353,7 @@
pdbname, pdbmtime, root->version, root->TimeDateStamp );
ML_(dinfo_free)( root );
}
- pdb_dump( &reader, di, obj_avma, unknown_purpose__reloc, sectp_avma );
+ pdb_dump( &reader, di, obj_avma, obj_bias, sectp_avma );
}
else
if (0==VG_(strncmp)((char const *)&signature, "JG\0\0", 4)) {
@@ -2412,7 +2365,7 @@
pdbname, pdbmtime, root->version, root->TimeDateStamp);
ML_(dinfo_free)( root );
}
- pdb_dump( &reader, di, obj_avma, unknown_purpose__reloc, sectp_avma );
+ pdb_dump( &reader, di, obj_avma, obj_bias, sectp_avma );
}
if (1) {
@@ -2474,9 +2427,9 @@
/* Make up the command to run, essentially:
sh -c "strings (pename) | egrep '\.pdb|\.PDB' > (tmpname)"
*/
- HChar* sh = SH_PATH;
- HChar* strings = STRINGS_PATH;
- HChar* egrep = EGREP_PATH;
+ HChar* sh = "/bin/sh";
+ HChar* strings = "/usr/bin/strings";
+ HChar* egrep = "/usr/bin/egrep";
/* (sh) -c "(strings) (pename) | (egrep) 'pdb' > (tmpname) */
Int cmdlen = VG_(strlen)(strings) + VG_(strlen)(pename)
diff --git a/main/coregrind/m_debuginfo/readstabs.c b/main/coregrind/m_debuginfo/readstabs.c
index e62721b..d667fce 100644
--- a/main/coregrind/m_debuginfo/readstabs.c
+++ b/main/coregrind/m_debuginfo/readstabs.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -35,8 +35,9 @@
*/
/* "on Linux (except android), or on Darwin" */
-#if (defined(VGO_linux) && !defined(VGPV_arm_linux_android)) \
- || defined(VGO_darwin)
+#if (defined(VGO_linux) && \
+ !(defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)) \
+ || defined(VGO_darwin))
#include "pub_core_basics.h"
#include "pub_core_debuginfo.h"
@@ -388,7 +389,7 @@
}
}
-#endif /* (defined(VGO_linux) && !defined(VGPV_arm_linux_android)) \
+#endif /* (defined(VGO_linux) && !defined(VGPV_*_linux_android)) \
|| defined(VGO_darwin) */
/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_debuginfo/storage.c b/main/coregrind/m_debuginfo/storage.c
index 2a9938f..6bd7ebb 100644
--- a/main/coregrind/m_debuginfo/storage.c
+++ b/main/coregrind/m_debuginfo/storage.c
@@ -9,7 +9,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -189,7 +189,7 @@
VG_(printf)(" R7=");
SHOW_HOW(si->r7_how, si->r7_off);
# elif defined(VGA_ppc32) || defined(VGA_ppc64)
-# elif defined(VGA_s390x)
+# elif defined(VGA_s390x) || defined(VGA_mips32)
VG_(printf)(" SP=");
SHOW_HOW(si->sp_how, si->sp_off);
VG_(printf)(" FP=");
@@ -347,7 +347,7 @@
{
static const Bool debug = False;
DiLoc loc;
- Int size = next - this;
+ UWord size = next - this;
/* Ignore zero-sized locs */
if (this == next) return;
@@ -377,23 +377,30 @@
if (0)
VG_(message)(Vg_DebugMsg,
"warning: line info address range too large "
- "at entry %d: %d\n", entry, size);
+ "at entry %d: %lu\n", entry, size);
size = 1;
}
+ /* At this point, we know that the original value for |size|, viz
+ |next - this|, will only still be used in the case where
+ |this| <u |next|, so it can't have underflowed. Considering
+ that and the three checks that follow it, the following must
+ hold. */
+ vg_assert(size >= 1);
+ vg_assert(size <= MAX_LOC_SIZE);
+
/* Rule out ones which are completely outside the r-x mapped area.
See "Comment_Regarding_Text_Range_Checks" elsewhere in this file
for background and rationale. */
vg_assert(di->fsm.have_rx_map && di->fsm.have_rw_map);
- if (next-1 < di->fsm.rx_map_avma
- || this >= di->fsm.rx_map_avma + di->fsm.rx_map_size ) {
+ if (ML_(find_rx_mapping)(di, this, this + size - 1) == NULL) {
if (0)
VG_(message)(Vg_DebugMsg,
"warning: ignoring line info entry falling "
"outside current DebugInfo: %#lx %#lx %#lx %#lx\n",
di->text_avma,
di->text_avma + di->text_size,
- this, next-1);
+ this, this + size - 1);
return;
}
@@ -421,7 +428,7 @@
loc.dirname = dirname;
if (0) VG_(message)(Vg_DebugMsg,
- "addLoc: addr %#lx, size %d, line %d, file %s\n",
+ "addLoc: addr %#lx, size %lu, line %d, file %s\n",
this,size,lineno,filename);
addLoc ( di, &loc );
@@ -436,6 +443,8 @@
UInt new_sz, i;
DiCfSI* new_tab;
SSizeT delta;
+ struct _DebugInfoMapping* map;
+ struct _DebugInfoMapping* map2;
/* copy the original, so we can mess with it */
DiCfSI cfsi = *cfsi_orig;
@@ -456,27 +465,30 @@
vg_assert(cfsi.len < 5000000);
vg_assert(di->fsm.have_rx_map && di->fsm.have_rw_map);
- /* If we have an empty r-x mapping (is that possible?) then the
- DiCfSI can't possibly fall inside it. In which case skip. */
- if (di->fsm.rx_map_size == 0)
- return;
+ /* Find mapping where at least one end of the CFSI falls into. */
+ map = ML_(find_rx_mapping)(di, cfsi.base, cfsi.base);
+ map2 = ML_(find_rx_mapping)(di, cfsi.base + cfsi.len - 1,
+ cfsi.base + cfsi.len - 1);
+ if (map == NULL)
+ map = map2;
+ else if (map2 == NULL)
+ map2 = map;
- /* Rule out ones which are completely outside the r-x mapped area.
+ /* Rule out ones which are completely outside the r-x mapped area
+ (or which span across different areas).
See "Comment_Regarding_Text_Range_Checks" elsewhere in this file
for background and rationale. */
- if (cfsi.base + cfsi.len - 1 < di->fsm.rx_map_avma
- || cfsi.base >= di->fsm.rx_map_avma + di->fsm.rx_map_size) {
+ if (map == NULL || map != map2) {
static Int complaints = 10;
if (VG_(clo_trace_cfi) || complaints > 0) {
complaints--;
if (VG_(clo_verbosity) > 1) {
VG_(message)(
Vg_DebugMsg,
- "warning: DiCfSI %#lx .. %#lx outside segment %#lx .. %#lx\n",
+ "warning: DiCfSI %#lx .. %#lx outside mapped rw segments (%s)\n",
cfsi.base,
cfsi.base + cfsi.len - 1,
- di->text_avma,
- di->text_avma + di->text_size - 1
+ di->soname
);
}
if (VG_(clo_trace_cfi))
@@ -493,27 +505,27 @@
will fail. See
"Comment_on_IMPORTANT_CFSI_REPRESENTATIONAL_INVARIANTS" in
priv_storage.h for background. */
- if (cfsi.base < di->fsm.rx_map_avma) {
+ if (cfsi.base < map->avma) {
/* Lower end is outside the mapped area. Hence upper end must
be inside it. */
if (0) VG_(printf)("XXX truncate lower\n");
- vg_assert(cfsi.base + cfsi.len - 1 >= di->fsm.rx_map_avma);
- delta = (SSizeT)(di->fsm.rx_map_avma - cfsi.base);
+ vg_assert(cfsi.base + cfsi.len - 1 >= map->avma);
+ delta = (SSizeT)(map->avma - cfsi.base);
vg_assert(delta > 0);
vg_assert(delta < (SSizeT)cfsi.len);
cfsi.base += delta;
cfsi.len -= delta;
}
else
- if (cfsi.base + cfsi.len - 1 > di->fsm.rx_map_avma
- + di->fsm.rx_map_size - 1) {
+ if (cfsi.base + cfsi.len - 1 > map->avma + map->size - 1) {
/* Upper end is outside the mapped area. Hence lower end must be
inside it. */
if (0) VG_(printf)("XXX truncate upper\n");
- vg_assert(cfsi.base <= di->fsm.rx_map_avma + di->fsm.rx_map_size - 1);
+ vg_assert(cfsi.base <= map->avma + map->size - 1);
delta = (SSizeT)( (cfsi.base + cfsi.len - 1)
- - (di->fsm.rx_map_avma + di->fsm.rx_map_size - 1) );
- vg_assert(delta > 0); vg_assert(delta < (SSizeT)cfsi.len);
+ - (map->avma + map->size - 1) );
+ vg_assert(delta > 0);
+ vg_assert(delta < (SSizeT)cfsi.len);
cfsi.len -= delta;
}
@@ -526,9 +538,9 @@
vg_assert(cfsi.len > 0);
/* Similar logic applies for the next two assertions. */
- vg_assert(cfsi.base >= di->fsm.rx_map_avma);
+ vg_assert(cfsi.base >= map->avma);
vg_assert(cfsi.base + cfsi.len - 1
- <= di->fsm.rx_map_avma + di->fsm.rx_map_size - 1);
+ <= map->avma + map->size - 1);
if (di->cfsi_used == di->cfsi_size) {
new_sz = 2 * di->cfsi_size;
@@ -629,6 +641,8 @@
case Creg_ARM_R12: VG_(printf)("R12"); break;
case Creg_ARM_R15: VG_(printf)("R15"); break;
case Creg_ARM_R14: VG_(printf)("R14"); break;
+ case Creg_MIPS_RA: VG_(printf)("RA"); break;
+ case Creg_S390_R14: VG_(printf)("R14"); break;
default: vg_assert(0);
}
}
@@ -917,16 +931,12 @@
and it is re-checked at the start of
ML_(read_elf_debug_info). */
vg_assert(di->fsm.have_rx_map && di->fsm.have_rw_map);
- if (level > 0
- && (aMax < di->fsm.rx_map_avma
- || aMin >= di->fsm.rx_map_avma + di->fsm.rx_map_size)) {
+ if (level > 0 && ML_(find_rx_mapping)(di, aMin, aMax) == NULL) {
if (VG_(clo_verbosity) >= 0) {
VG_(message)(Vg_DebugMsg,
"warning: addVar: in range %#lx .. %#lx outside "
- "segment %#lx .. %#lx (%s)\n",
- aMin, aMax,
- di->text_avma, di->text_avma + di->text_size -1,
- name
+ "all rx mapped areas (%s)\n",
+ aMin, aMax, name
);
}
return;
@@ -1368,11 +1378,18 @@
vg_assert(w < r);
if ( di->symtab[w].addr == di->symtab[r].addr
&& di->symtab[w].size == di->symtab[r].size
- && !!di->symtab[w].isText == !!di->symtab[r].isText
- && !!di->symtab[w].isIFunc == !!di->symtab[r].isIFunc) {
+ && !!di->symtab[w].isText == !!di->symtab[r].isText) {
/* merge the two into one */
n_merged++;
- add_DiSym_names_to_from(di, &di->symtab[w], &di->symtab[r]);
+ /* Add r names to w if r has secondary names
+ or r and w primary names differ. */
+ if (di->symtab[r].sec_names
+ || (0 != VG_(strcmp)(di->symtab[r].pri_name,
+ di->symtab[w].pri_name))) {
+ add_DiSym_names_to_from(di, &di->symtab[w], &di->symtab[r]);
+ }
+ /* mark w as an IFunc if either w or r are */
+ di->symtab[w].isIFunc = di->symtab[w].isIFunc || di->symtab[r].isIFunc;
/* and use ::pri_names to indicate this slot is no longer in use */
di->symtab[r].pri_name = NULL;
if (di->symtab[r].sec_names) {
@@ -1850,7 +1867,7 @@
Word ML_(search_one_fpotab) ( struct _DebugInfo* di, Addr ptr )
{
- Addr const addr = ptr - di->fsm.rx_map_avma;
+ Addr const addr = ptr - di->fpo_base_avma;
Addr a_mid_lo, a_mid_hi;
Word mid, size,
lo = 0,
diff --git a/main/coregrind/m_debuginfo/tytypes.c b/main/coregrind/m_debuginfo/tytypes.c
index dba5288..d85d0ac 100644
--- a/main/coregrind/m_debuginfo/tytypes.c
+++ b/main/coregrind/m_debuginfo/tytypes.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks LLP
+ Copyright (C) 2008-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -54,9 +54,10 @@
case Te_EMPTY: case Te_INDIR: case Te_UNKNOWN:
case Te_Atom: case Te_Field: case Te_Bound:
return False;
- case Te_TyBase: case Te_TyPorR: case Te_TyTyDef:
- case Te_TyStOrUn: case Te_TyEnum: case Te_TyArray:
- case Te_TyFn: case Te_TyQual: case Te_TyVoid:
+ case Te_TyBase: case Te_TyPtr: case Te_TyRef:
+ case Te_TyPtrMbr: case Te_TyRvalRef: case Te_TyTyDef:
+ case Te_TyStOrUn: case Te_TyEnum: case Te_TyArray:
+ case Te_TyFn: case Te_TyQual: case Te_TyVoid:
return True;
default:
vg_assert(0);
@@ -127,10 +128,20 @@
te->Te.TyBase.name ? te->Te.TyBase.name
: (UChar*)"(null)" );
break;
- case Te_TyPorR:
- VG_(printf)("Te_TyPorR(%d,%c,0x%05lx)",
- te->Te.TyPorR.szB,
- te->Te.TyPorR.isPtr ? 'P' : 'R',
+ case Te_TyPtr:
+ VG_(printf)("Te_TyPtr(%d,0x%05lx)", te->Te.TyPorR.szB,
+ te->Te.TyPorR.typeR);
+ break;
+ case Te_TyRef:
+ VG_(printf)("Te_TyRef(%d,0x%05lx)", te->Te.TyPorR.szB,
+ te->Te.TyPorR.typeR);
+ break;
+ case Te_TyPtrMbr:
+ VG_(printf)("Te_TyMbr(%d,0x%05lx)", te->Te.TyPorR.szB,
+ te->Te.TyPorR.typeR);
+ break;
+ case Te_TyRvalRef:
+ VG_(printf)("Te_TyRvalRef(%d,0x%05lx)", te->Te.TyPorR.szB,
te->Te.TyPorR.typeR);
break;
case Te_TyTyDef:
@@ -237,9 +248,21 @@
if (!ent->Te.TyBase.name) goto unhandled;
VG_(printf)("%s", ent->Te.TyBase.name);
break;
- case Te_TyPorR:
+ case Te_TyPtr:
ML_(pp_TyEnt_C_ishly)(tyents, ent->Te.TyPorR.typeR);
- VG_(printf)("%s", ent->Te.TyPorR.isPtr ? "*" : "&");
+ VG_(printf)("*");
+ break;
+ case Te_TyRef:
+ ML_(pp_TyEnt_C_ishly)(tyents, ent->Te.TyPorR.typeR);
+ VG_(printf)("&");
+ break;
+ case Te_TyPtrMbr:
+ ML_(pp_TyEnt_C_ishly)(tyents, ent->Te.TyPorR.typeR);
+ VG_(printf)("*");
+ break;
+ case Te_TyRvalRef:
+ ML_(pp_TyEnt_C_ishly)(tyents, ent->Te.TyPorR.typeR);
+ VG_(printf)("&&");
break;
case Te_TyEnum:
if (!ent->Te.TyEnum.name) goto unhandled;
@@ -397,29 +420,29 @@
/* Generates a total ordering on TyEnts based on everything except
their .cuOff fields. */
-static __attribute__((always_inline)) Word UWord__cmp ( UWord a, UWord b ) {
+static inline Word UWord__cmp ( UWord a, UWord b ) {
if (a < b) return -1;
if (a > b) return 1;
return 0;
}
-static __attribute__((always_inline)) Word Long__cmp ( Long a, Long b ) {
+static inline Word Long__cmp ( Long a, Long b ) {
if (a < b) return -1;
if (a > b) return 1;
return 0;
}
-static __attribute__((always_inline)) Word Bool__cmp ( Bool a, Bool b ) {
+static inline Word Bool__cmp ( Bool a, Bool b ) {
vg_assert( ((UWord)a) <= 1 );
vg_assert( ((UWord)b) <= 1 );
if (a < b) return -1;
if (a > b) return 1;
return 0;
}
-static __attribute__((always_inline)) Word UChar__cmp ( UChar a, UChar b ) {
+static inline Word UChar__cmp ( UChar a, UChar b ) {
if (a < b) return -1;
if (a > b) return 1;
return 0;
}
-static __attribute__((always_inline)) Word Int__cmp ( Int a, Int b ) {
+static inline Word Int__cmp ( Int a, Int b ) {
if (a < b) return -1;
if (a > b) return 1;
return 0;
@@ -503,12 +526,13 @@
if (r != 0) return r;
r = Asciiz__cmp(te1->Te.TyBase.name, te2->Te.TyBase.name);
return r;
- case Te_TyPorR:
+ case Te_TyPtr:
+ case Te_TyRef:
+ case Te_TyPtrMbr:
+ case Te_TyRvalRef:
r = Int__cmp(te1->Te.TyPorR.szB, te2->Te.TyPorR.szB);
if (r != 0) return r;
r = UWord__cmp(te1->Te.TyPorR.typeR, te2->Te.TyPorR.typeR);
- if (r != 0) return r;
- r = Bool__cmp(te1->Te.TyPorR.isPtr, te2->Te.TyPorR.isPtr);
return r;
case Te_TyTyDef:
r = UWord__cmp(te1->Te.TyTyDef.typeR, te2->Te.TyTyDef.typeR);
@@ -584,7 +608,10 @@
case Te_TyBase:
if (te->Te.TyBase.name) ML_(dinfo_free)(te->Te.TyBase.name);
break;
- case Te_TyPorR:
+ case Te_TyPtr:
+ case Te_TyRef:
+ case Te_TyPtrMbr:
+ case Te_TyRvalRef:
break;
case Te_TyTyDef:
if (te->Te.TyTyDef.name) ML_(dinfo_free)(te->Te.TyTyDef.name);
@@ -661,7 +688,10 @@
if (ent2->tag == Te_UNKNOWN)
return mk_MaybeULong_Nothing(); /*UNKNOWN*/
return ML_(sizeOfType)( tyents, ent->Te.TyTyDef.typeR );
- case Te_TyPorR:
+ case Te_TyPtr:
+ case Te_TyRef:
+ case Te_TyPtrMbr:
+ case Te_TyRvalRef:
vg_assert(ent->Te.TyPorR.szB == 4 || ent->Te.TyPorR.szB == 8);
return mk_MaybeULong_Just( ent->Te.TyPorR.szB );
case Te_TyStOrUn:
@@ -738,7 +768,10 @@
case Te_TyEnum:
case Te_TyFn:
case Te_TyVoid:
- case Te_TyPorR:
+ case Te_TyPtr:
+ case Te_TyRef:
+ case Te_TyPtrMbr:
+ case Te_TyRvalRef:
case Te_TyBase:
goto done;
diff --git a/main/coregrind/m_debuglog.c b/main/coregrind/m_debuglog.c
index ab580ed..f817b59 100644
--- a/main/coregrind/m_debuglog.c
+++ b/main/coregrind/m_debuglog.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -73,28 +73,20 @@
static UInt local_sys_write_stderr ( HChar* buf, Int n )
{
- volatile Int block[2];
- block[0] = (Int)buf;
- block[1] = n;
+ Int result;
+
__asm__ volatile (
- "pushl %%ebx\n" /* ebx is callee-save */
- "movl %0, %%ebx\n" /* ebx = &block */
- "pushl %%ebx\n" /* save &block */
- "movl 0(%%ebx), %%ecx\n" /* %ecx = buf */
- "movl 4(%%ebx), %%edx\n" /* %edx = n */
+ "pushl %%ebx\n"
"movl $"VG_STRINGIFY(__NR_write)", %%eax\n" /* %eax = __NR_write */
"movl $2, %%ebx\n" /* %ebx = stderr */
"int $0x80\n" /* write(stderr, buf, n) */
- "popl %%ebx\n" /* reestablish &block */
- "movl %%eax, 0(%%ebx)\n" /* block[0] = result */
- "popl %%ebx\n" /* restore ebx */
- : /*wr*/
- : /*rd*/ "r" (block)
- : /*trash*/ "eax", "edi", "ecx", "edx", "memory", "cc"
+ "popl %%ebx\n"
+ : /*wr*/ "=a" (result)
+ : /*rd*/ "c" (buf), "d" (n)
+ : /*trash*/ "edi", "memory", "cc"
);
- if (block[0] < 0)
- block[0] = -1;
- return block[0];
+
+ return result >= 0 ? result : -1;
}
static UInt local_sys_getpid ( void )
@@ -398,6 +390,43 @@
return (UInt)(__res);
}
+#elif defined(VGP_mips32_linux)
+static UInt local_sys_write_stderr ( HChar* buf, Int n )
+{
+ volatile Int block[2];
+ block[0] = (Int)buf;
+ block[1] = n;
+ __asm__ volatile (
+ "li $4, 2\n\t" /* stderr */
+ "lw $5, 0(%0)\n\t" /* buf */
+ "lw $6, 4(%0)\n\t" /* n */
+ "move $7, $0\n\t"
+ "li $2, %1\n\t" /* set v0 = __NR_write */
+ "syscall\n\t" /* write() */
+ "nop\n\t"
+ :
+ : "r" (block), "n" (__NR_write)
+ : "2", "4", "5", "6", "7"
+ );
+ if (block[0] < 0)
+ block[0] = -1;
+ return (UInt)block[0];
+}
+
+static UInt local_sys_getpid ( void )
+{
+ UInt __res;
+ __asm__ volatile (
+ "li $2, %1\n\t" /* set v0 = __NR_getpid */
+ "syscall\n\t" /* getpid() */
+ "nop\n\t"
+ "move %0, $2\n"
+ : "=r" (__res)
+ : "n" (__NR_getpid)
+ : "$2" );
+ return __res;
+}
+
#else
# error Unknown platform
diff --git a/main/coregrind/m_demangle/ansidecl.h b/main/coregrind/m_demangle/ansidecl.h
index c19955a..23d85bf 100644
--- a/main/coregrind/m_demangle/ansidecl.h
+++ b/main/coregrind/m_demangle/ansidecl.h
@@ -1,5 +1,6 @@
/* ANSI and traditional C compatability macros
- Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001
+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
+ 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010
Free Software Foundation, Inc.
This file is part of the GNU C Library.
@@ -114,6 +115,10 @@
#ifndef _ANSIDECL_H
#define _ANSIDECL_H 1
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/* Every source file includes this file,
so they will all get the switch for lint. */
/* LINTLIBRARY */
@@ -136,7 +141,7 @@
#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__)
#endif /* GCC_VERSION */
-#if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(_WIN32) || (defined(__alpha) && defined(__cplusplus))
+#if defined (__STDC__) || defined(__cplusplus) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(_WIN32)
/* All known AIX compilers implement these things (but don't always
define __STDC__). The RISC/OS MIPS compiler defines these things
in SVR4 mode, but does not define __STDC__. */
@@ -173,7 +178,7 @@
/* inline requires special treatment; it's in C99, and GCC >=2.7 supports
it too, but it's not in C89. */
#undef inline
-#if __STDC_VERSION__ > 199901L
+#if __STDC_VERSION__ >= 199901L || defined(__cplusplus) || (defined(__SUNPRO_C) && defined(__C99FEATURES__))
/* it's a keyword */
#else
# if GCC_VERSION >= 2007
@@ -256,14 +261,23 @@
# endif /* GNUC >= 2.96 */
#endif /* ATTRIBUTE_MALLOC */
-/* Attributes on labels were valid as of gcc 2.93. */
+/* Attributes on labels were valid as of gcc 2.93 and g++ 4.5. For
+ g++ an attribute on a label must be followed by a semicolon. */
#ifndef ATTRIBUTE_UNUSED_LABEL
-# if (!defined (__cplusplus) && GCC_VERSION >= 2093)
-# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED
+# ifndef __cplusplus
+# if GCC_VERSION >= 2093
+# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED
+# else
+# define ATTRIBUTE_UNUSED_LABEL
+# endif
# else
-# define ATTRIBUTE_UNUSED_LABEL
-# endif /* !__cplusplus && GNUC >= 2.93 */
-#endif /* ATTRIBUTE_UNUSED_LABEL */
+# if GCC_VERSION >= 4005
+# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED ;
+# else
+# define ATTRIBUTE_UNUSED_LABEL
+# endif
+# endif
+#endif
#ifndef ATTRIBUTE_UNUSED
#define ATTRIBUTE_UNUSED __attribute__ ((__unused__))
@@ -390,4 +404,31 @@
#define __extension__
#endif
+/* This is used to declare a const variable which should be visible
+ outside of the current compilation unit. Use it as
+ EXPORTED_CONST int i = 1;
+ This is because the semantics of const are different in C and C++.
+ "extern const" is permitted in C but it looks strange, and gcc
+ warns about it when -Wc++-compat is not used. */
+#ifdef __cplusplus
+#define EXPORTED_CONST extern const
+#else
+#define EXPORTED_CONST const
+#endif
+
+/* Be conservative and only use enum bitfields with C++ or GCC.
+ FIXME: provide a complete autoconf test for buggy enum bitfields. */
+
+#ifdef __cplusplus
+#define ENUM_BITFIELD(TYPE) enum TYPE
+#elif (GCC_VERSION > 2000)
+#define ENUM_BITFIELD(TYPE) __extension__ enum TYPE
+#else
+#define ENUM_BITFIELD(TYPE) unsigned int
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
#endif /* ansidecl.h */
diff --git a/main/coregrind/m_demangle/cp-demangle.c b/main/coregrind/m_demangle/cp-demangle.c
index 00aba99..98d3746 100644
--- a/main/coregrind/m_demangle/cp-demangle.c
+++ b/main/coregrind/m_demangle/cp-demangle.c
@@ -1,5 +1,5 @@
/* Demangler for g++ V3 ABI.
- Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008
+ Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
Free Software Foundation, Inc.
Written by Ian Lance Taylor <ian@wasabisystems.com>.
@@ -293,8 +293,6 @@
enum { D_PRINT_BUFFER_LENGTH = 256 };
struct d_print_info
{
- /* The options passed to the demangler. */
- int options;
/* Fixed-length allocated buffer for demangled data, flushed to the
callback with a NUL termination once full. */
char buf[D_PRINT_BUFFER_LENGTH];
@@ -317,6 +315,8 @@
/* The current index into any template argument packs we are using
for printing. */
int pack_index;
+ /* Number of d_print_flush calls so far. */
+ unsigned long int flush_count;
};
#ifdef CP_DEMANGLE_DEBUG
@@ -335,6 +335,9 @@
d_make_name (struct d_info *, const char *, int);
static struct demangle_component *
+d_make_demangle_mangled_name (struct d_info *, const char *);
+
+static struct demangle_component *
d_make_builtin_type (struct d_info *,
const struct demangle_builtin_type_info *);
@@ -404,6 +407,8 @@
static struct demangle_component *d_array_type (struct d_info *);
+static struct demangle_component *d_vector_type (struct d_info *);
+
static struct demangle_component *
d_pointer_to_member_type (struct d_info *);
@@ -423,6 +428,13 @@
static int d_discriminator (struct d_info *);
+static struct demangle_component *d_lambda (struct d_info *);
+
+static struct demangle_component *d_unnamed_type (struct d_info *);
+
+static struct demangle_component *
+d_clone_suffix (struct d_info *, struct demangle_component *);
+
static int
d_add_substitution (struct d_info *, struct demangle_component *);
@@ -440,7 +452,7 @@
d_growable_string_callback_adapter (const char *, size_t, void *);
static void
-d_print_init (struct d_print_info *, int, demangle_callbackref, void *);
+d_print_init (struct d_print_info *, demangle_callbackref, void *);
static inline void d_print_error (struct d_print_info *);
@@ -458,32 +470,32 @@
static inline char d_last_char (struct d_print_info *);
static void
-d_print_comp (struct d_print_info *, const struct demangle_component *);
+d_print_comp (struct d_print_info *, int, const struct demangle_component *);
static void
d_print_java_identifier (struct d_print_info *, const char *, int);
static void
-d_print_mod_list (struct d_print_info *, struct d_print_mod *, int);
+d_print_mod_list (struct d_print_info *, int, struct d_print_mod *, int);
static void
-d_print_mod (struct d_print_info *, const struct demangle_component *);
+d_print_mod (struct d_print_info *, int, const struct demangle_component *);
static void
-d_print_function_type (struct d_print_info *,
+d_print_function_type (struct d_print_info *, int,
const struct demangle_component *,
struct d_print_mod *);
static void
-d_print_array_type (struct d_print_info *,
+d_print_array_type (struct d_print_info *, int,
const struct demangle_component *,
struct d_print_mod *);
static void
-d_print_expr_op (struct d_print_info *, const struct demangle_component *);
+d_print_expr_op (struct d_print_info *, int, const struct demangle_component *);
static void
-d_print_cast (struct d_print_info *, const struct demangle_component *);
+d_print_cast (struct d_print_info *, int, const struct demangle_component *);
static int d_demangle_callback (const char *, int,
demangle_callbackref, void *);
@@ -588,6 +600,12 @@
case DEMANGLE_COMPONENT_HIDDEN_ALIAS:
printf ("hidden alias\n");
break;
+ case DEMANGLE_COMPONENT_TRANSACTION_CLONE:
+ printf ("transaction clone\n");
+ break;
+ case DEMANGLE_COMPONENT_NONTRANSACTION_CLONE:
+ printf ("non-transaction clone\n");
+ break;
case DEMANGLE_COMPONENT_RESTRICT:
printf ("restrict\n");
break;
@@ -636,6 +654,9 @@
case DEMANGLE_COMPONENT_PTRMEM_TYPE:
printf ("pointer to member type\n");
break;
+ case DEMANGLE_COMPONENT_FIXED_TYPE:
+ printf ("fixed-point type\n");
+ break;
case DEMANGLE_COMPONENT_ARGLIST:
printf ("argument list\n");
break;
@@ -731,8 +752,8 @@
{
if (p == NULL
|| name == NULL
- || (kind < gnu_v3_complete_object_ctor
- && kind > gnu_v3_complete_object_allocating_ctor))
+ || (int) kind < gnu_v3_complete_object_ctor
+ || (int) kind > gnu_v3_object_ctor_group)
return 0;
p->type = DEMANGLE_COMPONENT_CTOR;
p->u.s_ctor.kind = kind;
@@ -750,8 +771,8 @@
{
if (p == NULL
|| name == NULL
- || (kind < gnu_v3_deleting_dtor
- && kind > gnu_v3_base_object_dtor))
+ || (int) kind < gnu_v3_deleting_dtor
+ || (int) kind > gnu_v3_object_dtor_group)
return 0;
p->type = DEMANGLE_COMPONENT_DTOR;
p->u.s_dtor.kind = kind;
@@ -804,6 +825,8 @@
case DEMANGLE_COMPONENT_LITERAL:
case DEMANGLE_COMPONENT_LITERAL_NEG:
case DEMANGLE_COMPONENT_COMPOUND_NAME:
+ case DEMANGLE_COMPONENT_VECTOR_TYPE:
+ case DEMANGLE_COMPONENT_CLONE:
if (left == NULL || right == NULL)
return NULL;
break;
@@ -821,6 +844,8 @@
case DEMANGLE_COMPONENT_GUARD:
case DEMANGLE_COMPONENT_REFTEMP:
case DEMANGLE_COMPONENT_HIDDEN_ALIAS:
+ case DEMANGLE_COMPONENT_TRANSACTION_CLONE:
+ case DEMANGLE_COMPONENT_NONTRANSACTION_CLONE:
case DEMANGLE_COMPONENT_POINTER:
case DEMANGLE_COMPONENT_REFERENCE:
case DEMANGLE_COMPONENT_RVALUE_REFERENCE:
@@ -831,6 +856,8 @@
case DEMANGLE_COMPONENT_JAVA_RESOURCE:
case DEMANGLE_COMPONENT_DECLTYPE:
case DEMANGLE_COMPONENT_PACK_EXPANSION:
+ case DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS:
+ case DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS:
if (left == NULL)
return NULL;
break;
@@ -870,6 +897,17 @@
return p;
}
+/* Add a new demangle mangled name component. */
+
+static struct demangle_component *
+d_make_demangle_mangled_name (struct d_info *di, const char *s)
+{
+ if (d_peek_char (di) != '_' || d_peek_next_char (di) != 'Z')
+ return d_make_name (di, s, strlen (s));
+ d_advance (di, 2);
+ return d_encoding (di, 0);
+}
+
/* Add a new name component. */
static struct demangle_component *
@@ -932,6 +970,20 @@
return p;
}
+static struct demangle_component *
+d_make_default_arg (struct d_info *di, int num,
+ struct demangle_component *sub)
+{
+ struct demangle_component *p = d_make_empty (di);
+ if (p)
+ {
+ p->type = DEMANGLE_COMPONENT_DEFAULT_ARG;
+ p->u.s_unary_num.num = num;
+ p->u.s_unary_num.sub = sub;
+ }
+ return p;
+}
+
/* Add a new constructor component. */
static struct demangle_component *
@@ -976,6 +1028,22 @@
return p;
}
+/* Add a new function parameter. */
+
+static struct demangle_component *
+d_make_function_param (struct d_info *di, long i)
+{
+ struct demangle_component *p;
+
+ p = d_make_empty (di);
+ if (p != NULL)
+ {
+ p->type = DEMANGLE_COMPONENT_FUNCTION_PARAM;
+ p->u.s_number.number = i;
+ }
+ return p;
+}
+
/* Add a new standard substitution component. */
static struct demangle_component *
@@ -993,7 +1061,7 @@
return p;
}
-/* <mangled-name> ::= _Z <encoding>
+/* <mangled-name> ::= _Z <encoding> [<clone-suffix>]*
TOP_LEVEL is non-zero when called at the top level. */
@@ -1001,11 +1069,28 @@
struct demangle_component *
cplus_demangle_mangled_name (struct d_info *di, int top_level)
{
- if (! d_check_char (di, '_'))
+ struct demangle_component *p;
+
+ if (! d_check_char (di, '_')
+ /* Allow missing _ if not at toplevel to work around a
+ bug in G++ abi-version=2 mangling; see the comment in
+ write_template_arg. */
+ && top_level)
return NULL;
if (! d_check_char (di, 'Z'))
return NULL;
- return d_encoding (di, top_level);
+ p = d_encoding (di, top_level);
+
+ /* If at top level and parsing parameters, check for a clone
+ suffix. */
+ if (top_level && (di->options & DMGL_PARAMS) != 0)
+ while (d_peek_char (di) == '.'
+ && (IS_LOWER (d_peek_next_char (di))
+ || d_peek_next_char (di) == '_'
+ || IS_DIGIT (d_peek_next_char (di))))
+ p = d_clone_suffix (di, p);
+
+ return p;
}
/* Return whether a function should have a return type. The argument
@@ -1143,8 +1228,9 @@
return d_local_name (di);
case 'L':
+ case 'U':
return d_unqualified_name (di);
-
+
case 'S':
{
int subst;
@@ -1234,6 +1320,7 @@
/* <prefix> ::= <prefix> <unqualified-name>
::= <template-prefix> <template-args>
::= <template-param>
+ ::= <decltype>
::=
::= <substitution>
@@ -1262,10 +1349,20 @@
<template-param> here. */
comb_type = DEMANGLE_COMPONENT_QUAL_NAME;
- if (IS_DIGIT (peek)
+ if (peek == 'D')
+ {
+ char peek2 = d_peek_next_char (di);
+ if (peek2 == 'T' || peek2 == 't')
+ /* Decltype. */
+ dc = cplus_demangle_type (di);
+ else
+ /* Destructor name. */
+ dc = d_unqualified_name (di);
+ }
+ else if (IS_DIGIT (peek)
|| IS_LOWER (peek)
|| peek == 'C'
- || peek == 'D'
+ || peek == 'U'
|| peek == 'L')
dc = d_unqualified_name (di);
else if (peek == 'S')
@@ -1281,6 +1378,16 @@
dc = d_template_param (di);
else if (peek == 'E')
return ret;
+ else if (peek == 'M')
+ {
+ /* Initializer scope for a lambda. We don't need to represent
+ this; the normal code will just treat the variable as a type
+ scope, which gives appropriate output. */
+ if (ret == NULL)
+ return NULL;
+ d_advance (di, 1);
+ continue;
+ }
else
return NULL;
@@ -1337,6 +1444,18 @@
return NULL;
return ret;
}
+ else if (peek == 'U')
+ {
+ switch (d_peek_next_char (di))
+ {
+ case 'l':
+ return d_lambda (di);
+ case 't':
+ return d_unnamed_type (di);
+ default:
+ return NULL;
+ }
+ }
else
return NULL;
}
@@ -1390,6 +1509,20 @@
}
}
+/* Like d_number, but returns a demangle_component. */
+
+static struct demangle_component *
+d_number_component (struct d_info *di)
+{
+ struct demangle_component *ret = d_make_empty (di);
+ if (ret)
+ {
+ ret->type = DEMANGLE_COMPONENT_NUMBER;
+ ret->u.s_number.number = d_number (di);
+ }
+ return ret;
+}
+
/* identifier ::= <(unqualified source code identifier)> */
static struct demangle_component *
@@ -1493,6 +1626,8 @@
{ "rs", NL (">>"), 2 },
{ "st", NL ("sizeof "), 1 },
{ "sz", NL ("sizeof "), 1 },
+ { "at", NL ("alignof "), 1 },
+ { "az", NL ("alignof "), 1 },
{ NULL, NULL, 0, 0 }
};
@@ -1650,6 +1785,8 @@
::= GR <name>
::= GA <encoding>
::= Gr <resource name>
+ ::= GTt <encoding>
+ ::= GTn <encoding>
*/
static struct demangle_component *
@@ -1734,13 +1871,33 @@
return d_make_comp (di, DEMANGLE_COMPONENT_GUARD, d_name (di), NULL);
case 'R':
- return d_make_comp (di, DEMANGLE_COMPONENT_REFTEMP, d_name (di),
- NULL);
+ {
+ struct demangle_component *name = d_name (di);
+ return d_make_comp (di, DEMANGLE_COMPONENT_REFTEMP, name,
+ d_number_component (di));
+ }
case 'A':
return d_make_comp (di, DEMANGLE_COMPONENT_HIDDEN_ALIAS,
d_encoding (di, 0), NULL);
+ case 'T':
+ switch (d_next_char (di))
+ {
+ case 'n':
+ return d_make_comp (di, DEMANGLE_COMPONENT_NONTRANSACTION_CLONE,
+ d_encoding (di, 0), NULL);
+ default:
+ /* ??? The proposal is that other letters (such as 'h') stand
+ for different variants of transaction cloning, such as
+ compiling directly for hardware transaction support. But
+ they still should all be transactional clones of some sort
+ so go ahead and call them that. */
+ case 't':
+ return d_make_comp (di, DEMANGLE_COMPONENT_TRANSACTION_CLONE,
+ d_encoding (di, 0), NULL);
+ }
+
case 'r':
return d_java_resource (di);
@@ -1824,6 +1981,9 @@
case '3':
kind = gnu_v3_complete_object_allocating_ctor;
break;
+ case '5':
+ kind = gnu_v3_object_ctor_group;
+ break;
default:
return NULL;
}
@@ -1846,6 +2006,9 @@
case '2':
kind = gnu_v3_base_object_dtor;
break;
+ case '5':
+ kind = gnu_v3_object_dtor_group;
+ break;
default:
return NULL;
}
@@ -1916,6 +2079,8 @@
/* 29 */ { NL ("half"), NL ("half"), D_PRINT_FLOAT },
/* 30 */ { NL ("char16_t"), NL ("char16_t"), D_PRINT_DEFAULT },
/* 31 */ { NL ("char32_t"), NL ("char32_t"), D_PRINT_DEFAULT },
+ /* 32 */ { NL ("decltype(nullptr)"), NL ("decltype(nullptr)"),
+ D_PRINT_DEFAULT },
};
CP_STATIC_IF_GLIBCPP_V3
@@ -2130,6 +2295,34 @@
ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[31]);
di->expansion += ret->u.s_builtin.type->len;
break;
+
+ case 'F':
+ /* Fixed point types. DF<int bits><length><fract bits><sat> */
+ ret = d_make_empty (di);
+ ret->type = DEMANGLE_COMPONENT_FIXED_TYPE;
+ if ((ret->u.s_fixed.accum = IS_DIGIT (d_peek_char (di))))
+ /* For demangling we don't care about the bits. */
+ d_number (di);
+ ret->u.s_fixed.length = cplus_demangle_type (di);
+ if (ret->u.s_fixed.length == NULL)
+ return NULL;
+ d_number (di);
+ peek = d_next_char (di);
+ ret->u.s_fixed.sat = (peek == 's');
+ break;
+
+ case 'v':
+ ret = d_vector_type (di);
+ break;
+
+ case 'n':
+ /* decltype(nullptr) */
+ ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[32]);
+ di->expansion += ret->u.s_builtin.type->len;
+ break;
+
+ default:
+ return NULL;
}
break;
@@ -2152,8 +2345,10 @@
d_cv_qualifiers (struct d_info *di,
struct demangle_component **pret, int member_fn)
{
+ struct demangle_component **pstart;
char peek;
+ pstart = pret;
peek = d_peek_char (di);
while (peek == 'r' || peek == 'V' || peek == 'K')
{
@@ -2190,6 +2385,28 @@
peek = d_peek_char (di);
}
+ if (!member_fn && peek == 'F')
+ {
+ while (pstart != pret)
+ {
+ switch ((*pstart)->type)
+ {
+ case DEMANGLE_COMPONENT_RESTRICT:
+ (*pstart)->type = DEMANGLE_COMPONENT_RESTRICT_THIS;
+ break;
+ case DEMANGLE_COMPONENT_VOLATILE:
+ (*pstart)->type = DEMANGLE_COMPONENT_VOLATILE_THIS;
+ break;
+ case DEMANGLE_COMPONENT_CONST:
+ (*pstart)->type = DEMANGLE_COMPONENT_CONST_THIS;
+ break;
+ default:
+ break;
+ }
+ pstart = &d_left (*pstart);
+ }
+ }
+
return pret;
}
@@ -2214,50 +2431,30 @@
return ret;
}
-/* <bare-function-type> ::= [J]<type>+ */
+/* <type>+ */
static struct demangle_component *
-d_bare_function_type (struct d_info *di, int has_return_tipe)
+d_parmlist (struct d_info *di)
{
- struct demangle_component *return_type;
struct demangle_component *tl;
struct demangle_component **ptl;
- char peek;
- /* Detect special qualifier indicating that the first argument
- is the return type. */
- peek = d_peek_char (di);
- if (peek == 'J')
- {
- d_advance (di, 1);
- has_return_tipe = 1;
- }
-
- return_type = NULL;
tl = NULL;
ptl = &tl;
while (1)
{
struct demangle_component *type;
- peek = d_peek_char (di);
- if (peek == '\0' || peek == 'E')
+ char peek = d_peek_char (di);
+ if (peek == '\0' || peek == 'E' || peek == '.')
break;
type = cplus_demangle_type (di);
if (type == NULL)
return NULL;
- if (has_return_tipe)
- {
- return_type = type;
- has_return_tipe = 0;
- }
- else
- {
- *ptl = d_make_comp (di, DEMANGLE_COMPONENT_ARGLIST, type, NULL);
- if (*ptl == NULL)
- return NULL;
- ptl = &d_right (*ptl);
- }
+ *ptl = d_make_comp (di, DEMANGLE_COMPONENT_ARGLIST, type, NULL);
+ if (*ptl == NULL)
+ return NULL;
+ ptl = &d_right (*ptl);
}
/* There should be at least one parameter type besides the optional
@@ -2272,10 +2469,45 @@
&& d_left (tl)->u.s_builtin.type->print == D_PRINT_VOID)
{
di->expansion -= d_left (tl)->u.s_builtin.type->len;
- tl = NULL;
+ d_left (tl) = NULL;
}
- return d_make_comp (di, DEMANGLE_COMPONENT_FUNCTION_TYPE, return_type, tl);
+ return tl;
+}
+
+/* <bare-function-type> ::= [J]<type>+ */
+
+static struct demangle_component *
+d_bare_function_type (struct d_info *di, int has_return_tipe)
+{
+ struct demangle_component *return_type;
+ struct demangle_component *tl;
+ char peek;
+
+ /* Detect special qualifier indicating that the first argument
+ is the return type. */
+ peek = d_peek_char (di);
+ if (peek == 'J')
+ {
+ d_advance (di, 1);
+ has_return_tipe = 1;
+ }
+
+ if (has_return_tipe)
+ {
+ return_type = cplus_demangle_type (di);
+ if (return_type == NULL)
+ return NULL;
+ }
+ else
+ return_type = NULL;
+
+ tl = d_parmlist (di);
+ if (tl == NULL)
+ return NULL;
+
+ return d_make_comp (di, DEMANGLE_COMPONENT_FUNCTION_TYPE,
+ return_type, tl);
}
/* <class-enum-type> ::= <name> */
@@ -2331,6 +2563,34 @@
cplus_demangle_type (di));
}
+/* <vector-type> ::= Dv <number> _ <type>
+ ::= Dv _ <expression> _ <type> */
+
+static struct demangle_component *
+d_vector_type (struct d_info *di)
+{
+ char peek;
+ struct demangle_component *dim;
+
+ peek = d_peek_char (di);
+ if (peek == '_')
+ {
+ d_advance (di, 1);
+ dim = d_expression (di);
+ }
+ else
+ dim = d_number_component (di);
+
+ if (dim == NULL)
+ return NULL;
+
+ if (! d_check_char (di, '_'))
+ return NULL;
+
+ return d_make_comp (di, DEMANGLE_COMPONENT_VECTOR_TYPE, dim,
+ cplus_demangle_type (di));
+}
+
/* <pointer-to-member-type> ::= M <(class) type> <(member) type> */
static struct demangle_component *
@@ -2377,6 +2637,24 @@
return d_make_comp (di, DEMANGLE_COMPONENT_PTRMEM_TYPE, cl, mem);
}
+/* <non-negative number> _ */
+
+static long
+d_compact_number (struct d_info *di)
+{
+ long num;
+ if (d_peek_char (di) == '_')
+ num = 0;
+ else if (d_peek_char (di) == 'n')
+ return -1;
+ else
+ num = d_number (di) + 1;
+
+ if (! d_check_char (di, '_'))
+ return -1;
+ return num;
+}
+
/* <template-param> ::= T_
::= T <(parameter-2 non-negative) number> _
*/
@@ -2389,17 +2667,8 @@
if (! d_check_char (di, 'T'))
return NULL;
- if (d_peek_char (di) == '_')
- param = 0;
- else
- {
- param = d_number (di);
- if (param < 0)
- return NULL;
- param += 1;
- }
-
- if (! d_check_char (di, '_'))
+ param = d_compact_number (di);
+ if (param < 0)
return NULL;
++di->did_subs;
@@ -2560,17 +2829,43 @@
d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE, name,
d_template_args (di)));
}
- else if (peek == 's' && d_peek_next_char (di) == 'T')
+ else if (peek == 's' && d_peek_next_char (di) == 'p')
{
- /* Just demangle a parameter placeholder as its type. */
d_advance (di, 2);
- return cplus_demangle_type (di);
+ return d_make_comp (di, DEMANGLE_COMPONENT_PACK_EXPANSION,
+ d_expression (di), NULL);
}
- else if (IS_DIGIT (peek))
+ else if (peek == 'f' && d_peek_next_char (di) == 'p')
+ {
+ /* Function parameter used in a late-specified return type. */
+ int index;
+ d_advance (di, 2);
+ if (d_peek_char (di) == 'T')
+ {
+ /* 'this' parameter. */
+ d_advance (di, 1);
+ index = 0;
+ }
+ else
+ {
+ index = d_compact_number (di) + 1;
+ if (index == 0)
+ return NULL;
+ }
+ return d_make_function_param (di, index);
+ }
+ else if (IS_DIGIT (peek)
+ || (peek == 'o' && d_peek_next_char (di) == 'n'))
{
/* We can get an unqualified name as an expression in the case of
- a dependent member access, i.e. decltype(T().i). */
- struct demangle_component *name = d_unqualified_name (di);
+ a dependent function call, i.e. decltype(f(t)). */
+ struct demangle_component *name;
+
+ if (peek == 'o')
+ /* operator-function-id, i.e. operator+(t). */
+ d_advance (di, 2);
+
+ name = d_unqualified_name (di);
if (name == NULL)
return NULL;
if (d_peek_char (di) == 'I')
@@ -2607,28 +2902,39 @@
args = op->u.s_extended_operator.args;
break;
case DEMANGLE_COMPONENT_CAST:
- if (d_peek_char (di) == 'v')
- /* T() encoded as an operand of void. */
- return d_make_comp (di, DEMANGLE_COMPONENT_UNARY, op,
- cplus_demangle_type (di));
- else
- args = 1;
+ args = 1;
break;
}
switch (args)
{
case 1:
- return d_make_comp (di, DEMANGLE_COMPONENT_UNARY, op,
- d_expression (di));
+ {
+ struct demangle_component *operand;
+ if (op->type == DEMANGLE_COMPONENT_CAST
+ && d_check_char (di, '_'))
+ operand = d_exprlist (di);
+ else
+ operand = d_expression (di);
+ return d_make_comp (di, DEMANGLE_COMPONENT_UNARY, op,
+ operand);
+ }
case 2:
{
struct demangle_component *left;
struct demangle_component *right;
+ const char *code = op->u.s_operator.op->code;
left = d_expression (di);
- if (!strcmp (op->u.s_operator.op->code, "cl"))
+ if (!strcmp (code, "cl"))
right = d_exprlist (di);
+ else if (!strcmp (code, "dt") || !strcmp (code, "pt"))
+ {
+ right = d_unqualified_name (di);
+ if (d_peek_char (di) == 'I')
+ right = d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE,
+ right, d_template_args (di));
+ }
else
right = d_expression (di);
@@ -2671,7 +2977,9 @@
if (! d_check_char (di, 'L'))
return NULL;
- if (d_peek_char (di) == '_')
+ if (d_peek_char (di) == '_'
+ /* Workaround for G++ bug; see comment in write_template_arg. */
+ || d_peek_char (di) == 'Z')
ret = cplus_demangle_mangled_name (di, 0);
else
{
@@ -2749,10 +3057,31 @@
else
{
struct demangle_component *name;
+ int num = -1;
+
+ if (d_peek_char (di) == 'd')
+ {
+ /* Default argument scope: d <number> _. */
+ d_advance (di, 1);
+ num = d_compact_number (di);
+ if (num < 0)
+ return NULL;
+ }
name = d_name (di);
- if (! d_discriminator (di))
- return NULL;
+ if (name)
+ switch (name->type)
+ {
+ /* Lambdas and unnamed types have internal discriminators. */
+ case DEMANGLE_COMPONENT_LAMBDA:
+ case DEMANGLE_COMPONENT_UNNAMED_TYPE:
+ break;
+ default:
+ if (! d_discriminator (di))
+ return NULL;
+ }
+ if (num >= 0)
+ name = d_make_default_arg (di, num, name);
return d_make_comp (di, DEMANGLE_COMPONENT_LOCAL_NAME, function, name);
}
}
@@ -2776,6 +3105,102 @@
return 1;
}
+/* <closure-type-name> ::= Ul <lambda-sig> E [ <nonnegative number> ] _ */
+
+static struct demangle_component *
+d_lambda (struct d_info *di)
+{
+ struct demangle_component *tl;
+ struct demangle_component *ret;
+ int num;
+
+ if (! d_check_char (di, 'U'))
+ return NULL;
+ if (! d_check_char (di, 'l'))
+ return NULL;
+
+ tl = d_parmlist (di);
+ if (tl == NULL)
+ return NULL;
+
+ if (! d_check_char (di, 'E'))
+ return NULL;
+
+ num = d_compact_number (di);
+ if (num < 0)
+ return NULL;
+
+ ret = d_make_empty (di);
+ if (ret)
+ {
+ ret->type = DEMANGLE_COMPONENT_LAMBDA;
+ ret->u.s_unary_num.sub = tl;
+ ret->u.s_unary_num.num = num;
+ }
+
+ if (! d_add_substitution (di, ret))
+ return NULL;
+
+ return ret;
+}
+
+/* <unnamed-type-name> ::= Ut [ <nonnegative number> ] _ */
+
+static struct demangle_component *
+d_unnamed_type (struct d_info *di)
+{
+ struct demangle_component *ret;
+ long num;
+
+ if (! d_check_char (di, 'U'))
+ return NULL;
+ if (! d_check_char (di, 't'))
+ return NULL;
+
+ num = d_compact_number (di);
+ if (num < 0)
+ return NULL;
+
+ ret = d_make_empty (di);
+ if (ret)
+ {
+ ret->type = DEMANGLE_COMPONENT_UNNAMED_TYPE;
+ ret->u.s_number.number = num;
+ }
+
+ if (! d_add_substitution (di, ret))
+ return NULL;
+
+ return ret;
+}
+
+/* <clone-suffix> ::= [ . <clone-type-identifier> ] [ . <nonnegative number> ]*
+*/
+
+static struct demangle_component *
+d_clone_suffix (struct d_info *di, struct demangle_component *encoding)
+{
+ const char *suffix = d_str (di);
+ const char *pend = suffix;
+ struct demangle_component *n;
+
+ if (*pend == '.' && (IS_LOWER (pend[1]) || pend[1] == '_'))
+ {
+ pend += 2;
+ while (IS_LOWER (*pend) || *pend == '_')
+ ++pend;
+ }
+ while (*pend == '.' && IS_DIGIT (pend[1]))
+ {
+ pend += 2;
+ while (IS_DIGIT (*pend))
+ ++pend;
+ }
+ d_advance (di, pend - suffix);
+ n = d_make_name (di, suffix, pend - suffix);
+ return d_make_comp (di, DEMANGLE_COMPONENT_CLONE, encoding, n);
+}
+
/* Add a new substitution. */
static int
@@ -3003,14 +3428,15 @@
/* Initialize a print information structure. */
static void
-d_print_init (struct d_print_info *dpi, int options,
- demangle_callbackref callback, void *opaque)
+d_print_init (struct d_print_info *dpi, demangle_callbackref callback,
+ void *opaque)
{
- dpi->options = options;
dpi->len = 0;
dpi->last_char = '\0';
dpi->templates = NULL;
dpi->modifiers = NULL;
+ dpi->pack_index = 0;
+ dpi->flush_count = 0;
dpi->callback = callback;
dpi->opaque = opaque;
@@ -3040,6 +3466,7 @@
dpi->buf[dpi->len] = '\0';
dpi->callback (dpi->buf, dpi->len, dpi->opaque);
dpi->len = 0;
+ dpi->flush_count++;
}
/* Append characters and buffers for printing. */
@@ -3069,6 +3496,14 @@
d_append_buffer (dpi, s, strlen (s));
}
+static inline void
+d_append_num (struct d_print_info *dpi, long l)
+{
+ char buf[25];
+ sprintf (buf,"%ld", l);
+ d_append_string (dpi, buf);
+}
+
static inline char
d_last_char (struct d_print_info *dpi)
{
@@ -3092,9 +3527,9 @@
{
struct d_print_info dpi;
- d_print_init (&dpi, options, callback, opaque);
+ d_print_init (&dpi, callback, opaque);
- d_print_comp (&dpi, dc);
+ d_print_comp (&dpi, options, dc);
d_print_flush (&dpi);
@@ -3194,11 +3629,13 @@
case DEMANGLE_COMPONENT_PACK_EXPANSION:
return NULL;
+ case DEMANGLE_COMPONENT_LAMBDA:
case DEMANGLE_COMPONENT_NAME:
case DEMANGLE_COMPONENT_OPERATOR:
case DEMANGLE_COMPONENT_BUILTIN_TYPE:
case DEMANGLE_COMPONENT_SUB_STD:
case DEMANGLE_COMPONENT_CHARACTER:
+ case DEMANGLE_COMPONENT_FUNCTION_PARAM:
return NULL;
case DEMANGLE_COMPONENT_EXTENDED_OPERATOR:
@@ -3235,15 +3672,16 @@
if needed. */
static void
-d_print_subexpr (struct d_print_info *dpi,
+d_print_subexpr (struct d_print_info *dpi, int options,
const struct demangle_component *dc)
{
int simple = 0;
- if (dc->type == DEMANGLE_COMPONENT_NAME)
+ if (dc->type == DEMANGLE_COMPONENT_NAME
+ || dc->type == DEMANGLE_COMPONENT_FUNCTION_PARAM)
simple = 1;
if (!simple)
d_append_char (dpi, '(');
- d_print_comp (dpi, dc);
+ d_print_comp (dpi, options, dc);
if (!simple)
d_append_char (dpi, ')');
}
@@ -3251,9 +3689,13 @@
/* Subroutine to handle components. */
static void
-d_print_comp (struct d_print_info *dpi,
+d_print_comp (struct d_print_info *dpi, int options,
const struct demangle_component *dc)
{
+ /* Magic variable to let reference smashing skip over the next modifier
+ without needing to modify *dc. */
+ const struct demangle_component *mod_inner = NULL;
+
if (dc == NULL)
{
d_print_error (dpi);
@@ -3265,7 +3707,7 @@
switch (dc->type)
{
case DEMANGLE_COMPONENT_NAME:
- if ((dpi->options & DMGL_JAVA) == 0)
+ if ((options & DMGL_JAVA) == 0)
d_append_buffer (dpi, dc->u.s_name.s, dc->u.s_name.len);
else
d_print_java_identifier (dpi, dc->u.s_name.s, dc->u.s_name.len);
@@ -3273,12 +3715,12 @@
case DEMANGLE_COMPONENT_QUAL_NAME:
case DEMANGLE_COMPONENT_LOCAL_NAME:
- d_print_comp (dpi, d_left (dc));
- if ((dpi->options & DMGL_JAVA) == 0)
+ d_print_comp (dpi, options, d_left (dc));
+ if ((options & DMGL_JAVA) == 0)
d_append_string (dpi, "::");
else
d_append_char (dpi, '.');
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
return;
case DEMANGLE_COMPONENT_TYPED_NAME:
@@ -3293,6 +3735,7 @@
the right place for the type. We also have to pass down
any CV-qualifiers, which apply to the this parameter. */
hold_modifiers = dpi->modifiers;
+ dpi->modifiers = 0;
i = 0;
typed_name = d_left (dc);
while (typed_name != NULL)
@@ -3342,6 +3785,8 @@
struct demangle_component *local_name;
local_name = d_right (typed_name);
+ if (local_name->type == DEMANGLE_COMPONENT_DEFAULT_ARG)
+ local_name = local_name->u.s_unary_num.sub;
while (local_name->type == DEMANGLE_COMPONENT_RESTRICT_THIS
|| local_name->type == DEMANGLE_COMPONENT_VOLATILE_THIS
|| local_name->type == DEMANGLE_COMPONENT_CONST_THIS)
@@ -3365,7 +3810,7 @@
}
}
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
if (typed_name->type == DEMANGLE_COMPONENT_TEMPLATE)
dpi->templates = dpt.next;
@@ -3378,7 +3823,7 @@
if (! adpm[i].printed)
{
d_append_char (dpi, ' ');
- d_print_mod (dpi, adpm[i].mod);
+ d_print_mod (dpi, options, adpm[i].mod);
}
}
@@ -3401,7 +3846,7 @@
dcl = d_left (dc);
- if ((dpi->options & DMGL_JAVA) != 0
+ if ((options & DMGL_JAVA) != 0
&& dcl->type == DEMANGLE_COMPONENT_NAME
&& dcl->u.s_name.len == 6
&& strncmp (dcl->u.s_name.s, "JArray", 6) == 0)
@@ -3409,16 +3854,16 @@
/* Special-case Java arrays, so that JArray<TYPE> appears
instead as TYPE[]. */
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
d_append_string (dpi, "[]");
}
else
{
- d_print_comp (dpi, dcl);
+ d_print_comp (dpi, options, dcl);
if (d_last_char (dpi) == '<')
d_append_char (dpi, ' ');
d_append_char (dpi, '<');
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
/* Avoid generating two consecutive '>' characters, to avoid
the C++ syntactic ambiguity. */
if (d_last_char (dpi) == '>')
@@ -3453,7 +3898,7 @@
hold_dpt = dpi->templates;
dpi->templates = hold_dpt->next;
- d_print_comp (dpi, a);
+ d_print_comp (dpi, options, a);
dpi->templates = hold_dpt;
@@ -3461,79 +3906,91 @@
}
case DEMANGLE_COMPONENT_CTOR:
- d_print_comp (dpi, dc->u.s_ctor.name);
+ d_print_comp (dpi, options, dc->u.s_ctor.name);
return;
case DEMANGLE_COMPONENT_DTOR:
d_append_char (dpi, '~');
- d_print_comp (dpi, dc->u.s_dtor.name);
+ d_print_comp (dpi, options, dc->u.s_dtor.name);
return;
case DEMANGLE_COMPONENT_VTABLE:
d_append_string (dpi, "vtable for ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_VTT:
d_append_string (dpi, "VTT for ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE:
d_append_string (dpi, "construction vtable for ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
d_append_string (dpi, "-in-");
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
return;
case DEMANGLE_COMPONENT_TYPEINFO:
d_append_string (dpi, "typeinfo for ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_TYPEINFO_NAME:
d_append_string (dpi, "typeinfo name for ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_TYPEINFO_FN:
d_append_string (dpi, "typeinfo fn for ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_THUNK:
d_append_string (dpi, "non-virtual thunk to ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_VIRTUAL_THUNK:
d_append_string (dpi, "virtual thunk to ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_COVARIANT_THUNK:
d_append_string (dpi, "covariant return thunk to ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_JAVA_CLASS:
d_append_string (dpi, "java Class for ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_GUARD:
d_append_string (dpi, "guard variable for ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_REFTEMP:
- d_append_string (dpi, "reference temporary for ");
- d_print_comp (dpi, d_left (dc));
+ d_append_string (dpi, "reference temporary #");
+ d_print_comp (dpi, options, d_right (dc));
+ d_append_string (dpi, " for ");
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_HIDDEN_ALIAS:
d_append_string (dpi, "hidden alias for ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
+ return;
+
+ case DEMANGLE_COMPONENT_TRANSACTION_CLONE:
+ d_append_string (dpi, "transaction clone for ");
+ d_print_comp (dpi, options, d_left (dc));
+ return;
+
+ case DEMANGLE_COMPONENT_NONTRANSACTION_CLONE:
+ d_append_string (dpi, "non-transaction clone for ");
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_SUB_STD:
@@ -3560,22 +4017,50 @@
break;
if (pdpm->mod->type == dc->type)
{
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
}
}
}
}
+ goto modifier;
+
+ case DEMANGLE_COMPONENT_REFERENCE:
+ case DEMANGLE_COMPONENT_RVALUE_REFERENCE:
+ {
+ /* Handle reference smashing: & + && = &. */
+ const struct demangle_component *sub = d_left (dc);
+ if (sub->type == DEMANGLE_COMPONENT_TEMPLATE_PARAM)
+ {
+ struct demangle_component *a = d_lookup_template_argument (dpi, sub);
+ if (a && a->type == DEMANGLE_COMPONENT_TEMPLATE_ARGLIST)
+ a = d_index_template_argument (a, dpi->pack_index);
+
+ if (a == NULL)
+ {
+ d_print_error (dpi);
+ return;
+ }
+
+ sub = a;
+ }
+
+ if (sub->type == DEMANGLE_COMPONENT_REFERENCE
+ || sub->type == dc->type)
+ dc = sub;
+ else if (sub->type == DEMANGLE_COMPONENT_RVALUE_REFERENCE)
+ mod_inner = d_left (sub);
+ }
/* Fall through. */
+
case DEMANGLE_COMPONENT_RESTRICT_THIS:
case DEMANGLE_COMPONENT_VOLATILE_THIS:
case DEMANGLE_COMPONENT_CONST_THIS:
case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
case DEMANGLE_COMPONENT_POINTER:
- case DEMANGLE_COMPONENT_REFERENCE:
- case DEMANGLE_COMPONENT_RVALUE_REFERENCE:
case DEMANGLE_COMPONENT_COMPLEX:
case DEMANGLE_COMPONENT_IMAGINARY:
+ modifier:
{
/* We keep a list of modifiers on the stack. */
struct d_print_mod dpm;
@@ -3586,12 +4071,15 @@
dpm.printed = 0;
dpm.templates = dpi->templates;
- d_print_comp (dpi, d_left (dc));
+ if (!mod_inner)
+ mod_inner = d_left (dc);
+
+ d_print_comp (dpi, options, mod_inner);
/* If the modifier didn't get printed by the type, print it
now. */
if (! dpm.printed)
- d_print_mod (dpi, dc);
+ d_print_mod (dpi, options, dc);
dpi->modifiers = dpm.next;
@@ -3599,7 +4087,7 @@
}
case DEMANGLE_COMPONENT_BUILTIN_TYPE:
- if ((dpi->options & DMGL_JAVA) == 0)
+ if ((options & DMGL_JAVA) == 0)
d_append_buffer (dpi, dc->u.s_builtin.type->name,
dc->u.s_builtin.type->len);
else
@@ -3608,16 +4096,21 @@
return;
case DEMANGLE_COMPONENT_VENDOR_TYPE:
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_FUNCTION_TYPE:
{
- if ((dpi->options & DMGL_RET_POSTFIX) != 0)
- d_print_function_type (dpi, dc, dpi->modifiers);
+ if ((options & DMGL_RET_POSTFIX) != 0)
+ d_print_function_type (dpi,
+ options & ~(DMGL_RET_POSTFIX | DMGL_RET_DROP),
+ dc, dpi->modifiers);
/* Print return type if present */
- if (d_left (dc) != NULL)
+ if (d_left (dc) != NULL && (options & DMGL_RET_POSTFIX) != 0)
+ d_print_comp (dpi, options & ~(DMGL_RET_POSTFIX | DMGL_RET_DROP),
+ d_left (dc));
+ else if (d_left (dc) != NULL && (options & DMGL_RET_DROP) == 0)
{
struct d_print_mod dpm;
@@ -3629,7 +4122,8 @@
dpm.printed = 0;
dpm.templates = dpi->templates;
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options & ~(DMGL_RET_POSTFIX | DMGL_RET_DROP),
+ d_left (dc));
dpi->modifiers = dpm.next;
@@ -3638,12 +4132,14 @@
/* In standard prefix notation, there is a space between the
return type and the function signature. */
- if ((dpi->options & DMGL_RET_POSTFIX) == 0)
+ if ((options & DMGL_RET_POSTFIX) == 0)
d_append_char (dpi, ' ');
}
- if ((dpi->options & DMGL_RET_POSTFIX) == 0)
- d_print_function_type (dpi, dc, dpi->modifiers);
+ if ((options & DMGL_RET_POSTFIX) == 0)
+ d_print_function_type (dpi,
+ options & ~(DMGL_RET_POSTFIX | DMGL_RET_DROP),
+ dc, dpi->modifiers);
return;
}
@@ -3696,7 +4192,7 @@
pdpm = pdpm->next;
}
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
dpi->modifiers = hold_modifiers;
@@ -3706,15 +4202,16 @@
while (i > 1)
{
--i;
- d_print_mod (dpi, adpm[i].mod);
+ d_print_mod (dpi, options, adpm[i].mod);
}
- d_print_array_type (dpi, dc, dpi->modifiers);
+ d_print_array_type (dpi, options, dc, dpi->modifiers);
return;
}
case DEMANGLE_COMPONENT_PTRMEM_TYPE:
+ case DEMANGLE_COMPONENT_VECTOR_TYPE:
{
struct d_print_mod dpm;
@@ -3724,30 +4221,54 @@
dpm.printed = 0;
dpm.templates = dpi->templates;
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
/* If the modifier didn't get printed by the type, print it
now. */
if (! dpm.printed)
- {
- d_append_char (dpi, ' ');
- d_print_comp (dpi, d_left (dc));
- d_append_string (dpi, "::*");
- }
+ d_print_mod (dpi, options, dc);
dpi->modifiers = dpm.next;
return;
}
+ case DEMANGLE_COMPONENT_FIXED_TYPE:
+ if (dc->u.s_fixed.sat)
+ d_append_string (dpi, "_Sat ");
+ /* Don't print "int _Accum". */
+ if (dc->u.s_fixed.length->u.s_builtin.type
+ != &cplus_demangle_builtin_types['i'-'a'])
+ {
+ d_print_comp (dpi, options, dc->u.s_fixed.length);
+ d_append_char (dpi, ' ');
+ }
+ if (dc->u.s_fixed.accum)
+ d_append_string (dpi, "_Accum");
+ else
+ d_append_string (dpi, "_Fract");
+ return;
+
case DEMANGLE_COMPONENT_ARGLIST:
case DEMANGLE_COMPONENT_TEMPLATE_ARGLIST:
if (d_left (dc) != NULL)
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
if (d_right (dc) != NULL)
{
+ size_t len;
+ unsigned long int flush_count;
+ /* Make sure ", " isn't flushed by d_append_string, otherwise
+ dpi->len -= 2 wouldn't work. */
+ if (dpi->len >= sizeof (dpi->buf) - 2)
+ d_print_flush (dpi);
d_append_string (dpi, ", ");
- d_print_comp (dpi, d_right (dc));
+ len = dpi->len;
+ flush_count = dpi->flush_count;
+ d_print_comp (dpi, options, d_right (dc));
+ /* If that didn't print anything (which can happen with empty
+ template argument packs), remove the comma and space. */
+ if (dpi->flush_count == flush_count && dpi->len == len)
+ dpi->len -= 2;
}
return;
@@ -3766,29 +4287,63 @@
case DEMANGLE_COMPONENT_EXTENDED_OPERATOR:
d_append_string (dpi, "operator ");
- d_print_comp (dpi, dc->u.s_extended_operator.name);
+ d_print_comp (dpi, options, dc->u.s_extended_operator.name);
return;
case DEMANGLE_COMPONENT_CAST:
d_append_string (dpi, "operator ");
- d_print_cast (dpi, dc);
+ d_print_cast (dpi, options, dc);
return;
case DEMANGLE_COMPONENT_UNARY:
- if (d_left (dc)->type != DEMANGLE_COMPONENT_CAST)
- d_print_expr_op (dpi, d_left (dc));
+ if (d_left (dc)->type == DEMANGLE_COMPONENT_OPERATOR
+ && d_left (dc)->u.s_operator.op->len == 1
+ && d_left (dc)->u.s_operator.op->name[0] == '&'
+ && d_right (dc)->type == DEMANGLE_COMPONENT_TYPED_NAME
+ && d_left (d_right (dc))->type == DEMANGLE_COMPONENT_QUAL_NAME
+ && d_right (d_right (dc))->type == DEMANGLE_COMPONENT_FUNCTION_TYPE)
+ {
+ /* Address of a function (therefore in an expression context) must
+ have its argument list suppressed.
+
+ unary operator ... dc
+ operator & ... d_left (dc)
+ typed name ... d_right (dc)
+ qualified name ... d_left (d_right (dc))
+ <names>
+ function type ... d_right (d_right (dc))
+ argument list
+ <arguments> */
+
+ d_print_expr_op (dpi, options, d_left (dc));
+ d_print_comp (dpi, options, d_left (d_right (dc)));
+ return;
+ }
+ else if (d_left (dc)->type == DEMANGLE_COMPONENT_OPERATOR
+ && d_left (dc)->u.s_operator.op->len == 1
+ && d_left (dc)->u.s_operator.op->name[0] == '&'
+ && d_right (dc)->type == DEMANGLE_COMPONENT_QUAL_NAME)
+ {
+ /* Keep also already processed variant without the argument list.
+
+ unary operator ... dc
+ operator & ... d_left (dc)
+ qualified name ... d_right (dc)
+ <names> */
+
+ d_print_expr_op (dpi, options, d_left (dc));
+ d_print_comp (dpi, options, d_right (dc));
+ return;
+ }
+ else if (d_left (dc)->type != DEMANGLE_COMPONENT_CAST)
+ d_print_expr_op (dpi, options, d_left (dc));
else
{
d_append_char (dpi, '(');
- d_print_cast (dpi, d_left (dc));
+ d_print_cast (dpi, options, d_left (dc));
d_append_char (dpi, ')');
}
- if (d_left (dc)->type == DEMANGLE_COMPONENT_CAST
- && d_right (dc)->type == DEMANGLE_COMPONENT_BUILTIN_TYPE)
- /* type() -- FIXME what about type(multiple,args) */
- d_append_string (dpi, "()");
- else
- d_print_subexpr (dpi, d_right (dc));
+ d_print_subexpr (dpi, options, d_right (dc));
return;
case DEMANGLE_COMPONENT_BINARY:
@@ -3806,10 +4361,33 @@
&& d_left (dc)->u.s_operator.op->name[0] == '>')
d_append_char (dpi, '(');
- d_print_subexpr (dpi, d_left (d_right (dc)));
- if (strcmp (d_left (dc)->u.s_operator.op->code, "cl") != 0)
- d_print_expr_op (dpi, d_left (dc));
- d_print_subexpr (dpi, d_right (d_right (dc)));
+ if (strcmp (d_left (dc)->u.s_operator.op->code, "cl") == 0
+ && d_left (d_right (dc))->type == DEMANGLE_COMPONENT_TYPED_NAME)
+ {
+ /* Function call used in an expression should not have printed types
+ of the function arguments. Values of the function arguments still
+ get printed below. */
+
+ const struct demangle_component *func = d_left (d_right (dc));
+
+ if (d_right (func)->type != DEMANGLE_COMPONENT_FUNCTION_TYPE)
+ d_print_error (dpi);
+ d_print_subexpr (dpi, options, d_left (func));
+ }
+ else
+ d_print_subexpr (dpi, options, d_left (d_right (dc)));
+ if (strcmp (d_left (dc)->u.s_operator.op->code, "ix") == 0)
+ {
+ d_append_char (dpi, '[');
+ d_print_comp (dpi, options, d_right (d_right (dc)));
+ d_append_char (dpi, ']');
+ }
+ else
+ {
+ if (strcmp (d_left (dc)->u.s_operator.op->code, "cl") != 0)
+ d_print_expr_op (dpi, options, d_left (dc));
+ d_print_subexpr (dpi, options, d_right (d_right (dc)));
+ }
if (d_left (dc)->type == DEMANGLE_COMPONENT_OPERATOR
&& d_left (dc)->u.s_operator.op->len == 1
@@ -3830,11 +4408,11 @@
d_print_error (dpi);
return;
}
- d_print_subexpr (dpi, d_left (d_right (dc)));
- d_print_expr_op (dpi, d_left (dc));
- d_print_subexpr (dpi, d_left (d_right (d_right (dc))));
+ d_print_subexpr (dpi, options, d_left (d_right (dc)));
+ d_print_expr_op (dpi, options, d_left (dc));
+ d_print_subexpr (dpi, options, d_left (d_right (d_right (dc))));
d_append_string (dpi, " : ");
- d_print_subexpr (dpi, d_right (d_right (d_right (dc))));
+ d_print_subexpr (dpi, options, d_right (d_right (d_right (dc))));
return;
case DEMANGLE_COMPONENT_TRINARY_ARG1:
@@ -3865,7 +4443,7 @@
{
if (dc->type == DEMANGLE_COMPONENT_LITERAL_NEG)
d_append_char (dpi, '-');
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
switch (tp)
{
default:
@@ -3915,26 +4493,30 @@
}
d_append_char (dpi, '(');
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
d_append_char (dpi, ')');
if (dc->type == DEMANGLE_COMPONENT_LITERAL_NEG)
d_append_char (dpi, '-');
if (tp == D_PRINT_FLOAT)
d_append_char (dpi, '[');
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
if (tp == D_PRINT_FLOAT)
d_append_char (dpi, ']');
}
return;
+ case DEMANGLE_COMPONENT_NUMBER:
+ d_append_num (dpi, dc->u.s_number.number);
+ return;
+
case DEMANGLE_COMPONENT_JAVA_RESOURCE:
d_append_string (dpi, "java resource ");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
return;
case DEMANGLE_COMPONENT_COMPOUND_NAME:
- d_print_comp (dpi, d_left (dc));
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_left (dc));
+ d_print_comp (dpi, options, d_right (dc));
return;
case DEMANGLE_COMPONENT_CHARACTER:
@@ -3943,27 +4525,82 @@
case DEMANGLE_COMPONENT_DECLTYPE:
d_append_string (dpi, "decltype (");
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
d_append_char (dpi, ')');
return;
case DEMANGLE_COMPONENT_PACK_EXPANSION:
{
- struct demangle_component *a = d_find_pack (dpi, d_left (dc));
- int len = d_pack_length (a);
+ int len;
int i;
+ struct demangle_component *a = d_find_pack (dpi, d_left (dc));
+ if (a == NULL)
+ {
+ /* d_find_pack won't find anything if the only packs involved
+ in this expansion are function parameter packs; in that
+ case, just print the pattern and "...". */
+ d_print_subexpr (dpi, options, d_left (dc));
+ d_append_string (dpi, "...");
+ return;
+ }
+ len = d_pack_length (a);
dc = d_left (dc);
for (i = 0; i < len; ++i)
{
dpi->pack_index = i;
- d_print_comp (dpi, dc);
+ d_print_comp (dpi, options, dc);
if (i < len-1)
d_append_string (dpi, ", ");
}
}
return;
+ case DEMANGLE_COMPONENT_FUNCTION_PARAM:
+ {
+ long num = dc->u.s_number.number;
+ if (num == 0)
+ d_append_string (dpi, "this");
+ else
+ {
+ d_append_string (dpi, "{parm#");
+ d_append_num (dpi, num);
+ d_append_char (dpi, '}');
+ }
+ }
+ return;
+
+ case DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS:
+ d_append_string (dpi, "global constructors keyed to ");
+ d_print_comp (dpi, options, dc->u.s_binary.left);
+ return;
+
+ case DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS:
+ d_append_string (dpi, "global destructors keyed to ");
+ d_print_comp (dpi, options, dc->u.s_binary.left);
+ return;
+
+ case DEMANGLE_COMPONENT_LAMBDA:
+ d_append_string (dpi, "{lambda(");
+ d_print_comp (dpi, options, dc->u.s_unary_num.sub);
+ d_append_string (dpi, ")#");
+ d_append_num (dpi, dc->u.s_unary_num.num + 1);
+ d_append_char (dpi, '}');
+ return;
+
+ case DEMANGLE_COMPONENT_UNNAMED_TYPE:
+ d_append_string (dpi, "{unnamed type#");
+ d_append_num (dpi, dc->u.s_number.number + 1);
+ d_append_char (dpi, '}');
+ return;
+
+ case DEMANGLE_COMPONENT_CLONE:
+ d_print_comp (dpi, options, d_left (dc));
+ d_append_string (dpi, " [clone ");
+ d_print_comp (dpi, options, d_right (dc));
+ d_append_char (dpi, ']');
+ return;
+
default:
d_print_error (dpi);
return;
@@ -4026,7 +4663,7 @@
qualifiers on this after printing a function. */
static void
-d_print_mod_list (struct d_print_info *dpi,
+d_print_mod_list (struct d_print_info *dpi, int options,
struct d_print_mod *mods, int suffix)
{
struct d_print_template *hold_dpt;
@@ -4040,7 +4677,7 @@
|| mods->mod->type == DEMANGLE_COMPONENT_VOLATILE_THIS
|| mods->mod->type == DEMANGLE_COMPONENT_CONST_THIS)))
{
- d_print_mod_list (dpi, mods->next, suffix);
+ d_print_mod_list (dpi, options, mods->next, suffix);
return;
}
@@ -4051,13 +4688,13 @@
if (mods->mod->type == DEMANGLE_COMPONENT_FUNCTION_TYPE)
{
- d_print_function_type (dpi, mods->mod, mods->next);
+ d_print_function_type (dpi, options, mods->mod, mods->next);
dpi->templates = hold_dpt;
return;
}
else if (mods->mod->type == DEMANGLE_COMPONENT_ARRAY_TYPE)
{
- d_print_array_type (dpi, mods->mod, mods->next);
+ d_print_array_type (dpi, options, mods->mod, mods->next);
dpi->templates = hold_dpt;
return;
}
@@ -4073,37 +4710,46 @@
hold_modifiers = dpi->modifiers;
dpi->modifiers = NULL;
- d_print_comp (dpi, d_left (mods->mod));
+ d_print_comp (dpi, options, d_left (mods->mod));
dpi->modifiers = hold_modifiers;
- if ((dpi->options & DMGL_JAVA) == 0)
+ if ((options & DMGL_JAVA) == 0)
d_append_string (dpi, "::");
else
d_append_char (dpi, '.');
dc = d_right (mods->mod);
+
+ if (dc->type == DEMANGLE_COMPONENT_DEFAULT_ARG)
+ {
+ d_append_string (dpi, "{default arg#");
+ d_append_num (dpi, dc->u.s_unary_num.num + 1);
+ d_append_string (dpi, "}::");
+ dc = dc->u.s_unary_num.sub;
+ }
+
while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS
|| dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS
|| dc->type == DEMANGLE_COMPONENT_CONST_THIS)
dc = d_left (dc);
- d_print_comp (dpi, dc);
+ d_print_comp (dpi, options, dc);
dpi->templates = hold_dpt;
return;
}
- d_print_mod (dpi, mods->mod);
+ d_print_mod (dpi, options, mods->mod);
dpi->templates = hold_dpt;
- d_print_mod_list (dpi, mods->next, suffix);
+ d_print_mod_list (dpi, options, mods->next, suffix);
}
/* Print a modifier. */
static void
-d_print_mod (struct d_print_info *dpi,
+d_print_mod (struct d_print_info *dpi, int options,
const struct demangle_component *mod)
{
switch (mod->type)
@@ -4122,11 +4768,11 @@
return;
case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL:
d_append_char (dpi, ' ');
- d_print_comp (dpi, d_right (mod));
+ d_print_comp (dpi, options, d_right (mod));
return;
case DEMANGLE_COMPONENT_POINTER:
/* There is no pointer symbol in Java. */
- if ((dpi->options & DMGL_JAVA) == 0)
+ if ((options & DMGL_JAVA) == 0)
d_append_char (dpi, '*');
return;
case DEMANGLE_COMPONENT_REFERENCE:
@@ -4144,16 +4790,22 @@
case DEMANGLE_COMPONENT_PTRMEM_TYPE:
if (d_last_char (dpi) != '(')
d_append_char (dpi, ' ');
- d_print_comp (dpi, d_left (mod));
+ d_print_comp (dpi, options, d_left (mod));
d_append_string (dpi, "::*");
return;
case DEMANGLE_COMPONENT_TYPED_NAME:
- d_print_comp (dpi, d_left (mod));
+ d_print_comp (dpi, options, d_left (mod));
return;
+ case DEMANGLE_COMPONENT_VECTOR_TYPE:
+ d_append_string (dpi, " __vector(");
+ d_print_comp (dpi, options, d_left (mod));
+ d_append_char (dpi, ')');
+ return;
+
default:
/* Otherwise, we have something that won't go back on the
modifier stack, so we can just print it. */
- d_print_comp (dpi, mod);
+ d_print_comp (dpi, options, mod);
return;
}
}
@@ -4161,25 +4813,22 @@
/* Print a function type, except for the return type. */
static void
-d_print_function_type (struct d_print_info *dpi,
+d_print_function_type (struct d_print_info *dpi, int options,
const struct demangle_component *dc,
struct d_print_mod *mods)
{
int need_paren;
- int saw_mod;
int need_space;
struct d_print_mod *p;
struct d_print_mod *hold_modifiers;
need_paren = 0;
- saw_mod = 0;
need_space = 0;
for (p = mods; p != NULL; p = p->next)
{
if (p->printed)
break;
- saw_mod = 1;
switch (p->mod->type)
{
case DEMANGLE_COMPONENT_POINTER:
@@ -4208,9 +4857,6 @@
break;
}
- if (d_left (dc) != NULL && ! saw_mod)
- need_paren = 1;
-
if (need_paren)
{
if (! need_space)
@@ -4227,7 +4873,7 @@
hold_modifiers = dpi->modifiers;
dpi->modifiers = NULL;
- d_print_mod_list (dpi, mods, 0);
+ d_print_mod_list (dpi, options, mods, 0);
if (need_paren)
d_append_char (dpi, ')');
@@ -4235,11 +4881,11 @@
d_append_char (dpi, '(');
if (d_right (dc) != NULL)
- d_print_comp (dpi, d_right (dc));
+ d_print_comp (dpi, options, d_right (dc));
d_append_char (dpi, ')');
- d_print_mod_list (dpi, mods, 1);
+ d_print_mod_list (dpi, options, mods, 1);
dpi->modifiers = hold_modifiers;
}
@@ -4247,7 +4893,7 @@
/* Print an array type, except for the element type. */
static void
-d_print_array_type (struct d_print_info *dpi,
+d_print_array_type (struct d_print_info *dpi, int options,
const struct demangle_component *dc,
struct d_print_mod *mods)
{
@@ -4281,7 +4927,7 @@
if (need_paren)
d_append_string (dpi, " (");
- d_print_mod_list (dpi, mods, 0);
+ d_print_mod_list (dpi, options, mods, 0);
if (need_paren)
d_append_char (dpi, ')');
@@ -4293,7 +4939,7 @@
d_append_char (dpi, '[');
if (d_left (dc) != NULL)
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
d_append_char (dpi, ']');
}
@@ -4301,24 +4947,24 @@
/* Print an operator in an expression. */
static void
-d_print_expr_op (struct d_print_info *dpi,
+d_print_expr_op (struct d_print_info *dpi, int options,
const struct demangle_component *dc)
{
if (dc->type == DEMANGLE_COMPONENT_OPERATOR)
d_append_buffer (dpi, dc->u.s_operator.op->name,
dc->u.s_operator.op->len);
else
- d_print_comp (dpi, dc);
+ d_print_comp (dpi, options, dc);
}
/* Print a cast. */
static void
-d_print_cast (struct d_print_info *dpi,
+d_print_cast (struct d_print_info *dpi, int options,
const struct demangle_component *dc)
{
if (d_left (dc)->type != DEMANGLE_COMPONENT_TEMPLATE)
- d_print_comp (dpi, d_left (dc));
+ d_print_comp (dpi, options, d_left (dc));
else
{
struct d_print_mod *hold_dpm;
@@ -4336,14 +4982,14 @@
dpi->templates = &dpt;
dpt.template_decl = d_left (dc);
- d_print_comp (dpi, d_left (d_left (dc)));
+ d_print_comp (dpi, options, d_left (d_left (dc)));
dpi->templates = dpt.next;
if (d_last_char (dpi) == '<')
d_append_char (dpi, ' ');
d_append_char (dpi, '<');
- d_print_comp (dpi, d_right (d_left (dc)));
+ d_print_comp (dpi, options, d_right (d_left (dc)));
/* Avoid generating two consecutive '>' characters, to avoid
the C++ syntactic ambiguity. */
if (d_last_char (dpi) == '>')
@@ -4394,33 +5040,30 @@
d_demangle_callback (const char *mangled, int options,
demangle_callbackref callback, void *opaque)
{
- int type;
+ enum
+ {
+ DCT_TYPE,
+ DCT_MANGLED,
+ DCT_GLOBAL_CTORS,
+ DCT_GLOBAL_DTORS
+ }
+ type;
struct d_info di;
struct demangle_component *dc;
int status;
if (mangled[0] == '_' && mangled[1] == 'Z')
- type = 0;
+ type = DCT_MANGLED;
else if (strncmp (mangled, "_GLOBAL_", 8) == 0
&& (mangled[8] == '.' || mangled[8] == '_' || mangled[8] == '$')
&& (mangled[9] == 'D' || mangled[9] == 'I')
&& mangled[10] == '_')
- {
- const char *intro;
-
- intro = (mangled[9] == 'I')
- ? "global constructors keyed to "
- : "global destructors keyed to ";
-
- callback (intro, strlen (intro), opaque);
- callback (mangled + 11, strlen (mangled + 11), opaque);
- return 1;
- }
+ type = mangled[9] == 'I' ? DCT_GLOBAL_CTORS : DCT_GLOBAL_DTORS;
else
{
if ((options & DMGL_TYPES) == 0)
return 0;
- type = 1;
+ type = DCT_TYPE;
}
cplus_demangle_init_info (mangled, options, strlen (mangled), &di);
@@ -4437,10 +5080,26 @@
di.subs = alloca (di.num_subs * sizeof (*di.subs));
#endif
- if (type)
- dc = cplus_demangle_type (&di);
- else
- dc = cplus_demangle_mangled_name (&di, 1);
+ switch (type)
+ {
+ case DCT_TYPE:
+ dc = cplus_demangle_type (&di);
+ break;
+ case DCT_MANGLED:
+ dc = cplus_demangle_mangled_name (&di, 1);
+ break;
+ case DCT_GLOBAL_CTORS:
+ case DCT_GLOBAL_DTORS:
+ d_advance (&di, 11);
+ dc = d_make_comp (&di,
+ (type == DCT_GLOBAL_CTORS
+ ? DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS
+ : DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS),
+ d_make_demangle_mangled_name (&di, d_str (&di)),
+ NULL);
+ d_advance (&di, strlen (d_str (&di)));
+ break;
+ }
/* If DMGL_PARAMS is set, then if we didn't consume the entire
mangled string, then we didn't successfully demangle it. If
@@ -4485,7 +5144,7 @@
return NULL;
}
- *palc = dgs.allocation_failure ? 1 : 0;
+ *palc = dgs.allocation_failure ? 1 : dgs.alc;
return dgs.buf;
}
diff --git a/main/coregrind/m_demangle/cp-demangle.h b/main/coregrind/m_demangle/cp-demangle.h
index aad3743..ae635be 100644
--- a/main/coregrind/m_demangle/cp-demangle.h
+++ b/main/coregrind/m_demangle/cp-demangle.h
@@ -1,5 +1,6 @@
/* Internal demangler interface for g++ V3 ABI.
- Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+ Copyright (C) 2003, 2004, 2005, 2006, 2007, 2010
+ Free Software Foundation, Inc.
Written by Ian Lance Taylor <ian@wasabisystems.com>.
This file is part of the libiberty library, which is part of GCC.
@@ -147,7 +148,7 @@
extern const struct demangle_operator_info cplus_demangle_operators[];
#endif
-#define D_BUILTIN_TYPE_COUNT (32)
+#define D_BUILTIN_TYPE_COUNT (33)
CP_STATIC_IF_GLIBCPP_V3
const struct demangle_builtin_type_info
diff --git a/main/coregrind/m_demangle/cplus-dem.c b/main/coregrind/m_demangle/cplus-dem.c
index 6eac15e..4b5600a 100644
--- a/main/coregrind/m_demangle/cplus-dem.c
+++ b/main/coregrind/m_demangle/cplus-dem.c
@@ -1,6 +1,6 @@
/* Demangler for GNU C++
Copyright 1989, 1991, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+ 2000, 2001, 2002, 2003, 2004, 2010 Free Software Foundation, Inc.
Written by James Clark (jjc@jclark.uucp)
Rewritten by Fred Fish (fnf@cygnus.com) for ARM and Lucid demangling
Modified by Satish Pai (pai@apollo.hp.com) for HP demangling
@@ -80,8 +80,6 @@
#include "demangle.h"
#include "safe-ctype.h"
-static char *ada_demangle (const char *, int);
-
#define min(X,Y) (((X) < (Y)) ? (X) : (Y))
/* A value at least one greater than the maximum number of characters
@@ -495,8 +493,6 @@
static void
recursively_demangle (struct work_stuff *, const char **, string *, int);
-static void grow_vect (char **, size_t *, size_t, int);
-
/* Translate count to integer, consuming tokens in the process.
Conversion terminates on the first non-digit character.
@@ -889,126 +885,268 @@
}
if (GNAT_DEMANGLING)
- return ada_demangle(mangled,options);
+ return ada_demangle (mangled, options);
ret = internal_cplus_demangle (work, mangled);
squangle_mop_up (work);
return (ret);
}
+/* Demangle ada names. The encoding is documented in gcc/ada/exp_dbug.ads. */
-/* Assuming *OLD_VECT points to an array of *SIZE objects of size
- ELEMENT_SIZE, grow it to contain at least MIN_SIZE objects,
- updating *OLD_VECT and *SIZE as necessary. */
-
-static void
-grow_vect (char **old_vect, size_t *size, size_t min_size, int element_size)
-{
- if (*size < min_size)
- {
- *size *= 2;
- if (*size < min_size)
- *size = min_size;
- *old_vect = XRESIZEVAR (char, *old_vect, *size * element_size);
- }
-}
-
-/* Demangle ada names:
- 1. Discard final __{DIGIT}+ or ${DIGIT}+
- 2. Convert other instances of embedded "__" to `.'.
- 3. Discard leading _ada_.
- 4. Remove everything after first ___ if it is followed by 'X'.
- 5. Put symbols that should be suppressed in <...> brackets.
- The resulting string is valid until the next call of ada_demangle. */
-
-static char *
+char *
ada_demangle (const char *mangled, int option ATTRIBUTE_UNUSED)
{
- int i, j;
int len0;
const char* p;
- char *demangled = NULL;
- int changed;
- size_t demangled_size = 0;
+ char *d;
+ char *demangled;
- changed = 0;
-
+ /* Discard leading _ada_, which is used for library level subprograms. */
if (strncmp (mangled, "_ada_", 5) == 0)
- {
- mangled += 5;
- changed = 1;
- }
-
- if (mangled[0] == '_' || mangled[0] == '<')
- goto Suppress;
-
- p = strstr (mangled, "___");
- if (p == NULL)
- len0 = strlen (mangled);
- else
- {
- if (p[3] == 'X')
- {
- len0 = p - mangled;
- changed = 1;
- }
- else
- goto Suppress;
- }
-
- /* Make demangled big enough for possible expansion by operator name. */
- grow_vect (&demangled,
- &demangled_size, 2 * len0 + 1,
- sizeof (char));
-
- if (ISDIGIT ((unsigned char) mangled[len0 - 1])) {
- for (i = len0 - 2; i >= 0 && ISDIGIT ((unsigned char) mangled[i]); i -= 1)
- ;
- if (i > 1 && mangled[i] == '_' && mangled[i - 1] == '_')
- {
- len0 = i - 1;
- changed = 1;
- }
- else if (mangled[i] == '$')
- {
- len0 = i;
- changed = 1;
- }
- }
-
- for (i = 0, j = 0; i < len0 && ! ISALPHA ((unsigned char)mangled[i]);
- i += 1, j += 1)
- demangled[j] = mangled[i];
-
- while (i < len0)
- {
- if (i < len0 - 2 && mangled[i] == '_' && mangled[i + 1] == '_')
- {
- demangled[j] = '.';
- changed = 1;
- i += 2; j += 1;
- }
- else
- {
- demangled[j] = mangled[i];
- i += 1; j += 1;
- }
- }
- demangled[j] = '\000';
-
- for (i = 0; demangled[i] != '\0'; i += 1)
- if (ISUPPER ((unsigned char)demangled[i]) || demangled[i] == ' ')
- goto Suppress;
+ mangled += 5;
- if (! changed)
- return NULL;
- else
- return demangled;
+ /* All ada unit names are lower-case. */
+ if (!ISLOWER (mangled[0]))
+ goto unknown;
+
+ /* Most of the demangling will trivially remove chars. Operator names
+ may add one char but because they are always preceeded by '__' which is
+ replaced by '.', they eventually never expand the size.
+ A few special names such as '___elabs' add a few chars (at most 7), but
+ they occur only once. */
+ len0 = strlen (mangled) + 7 + 1;
+ demangled = XNEWVEC (char, len0);
- Suppress:
- grow_vect (&demangled,
- &demangled_size, strlen (mangled) + 3,
- sizeof (char));
+ d = demangled;
+ p = mangled;
+ while (1)
+ {
+ /* An entity names is expected. */
+ if (ISLOWER (*p))
+ {
+ /* An identifier, which is always lower case. */
+ do
+ *d++ = *p++;
+ while (ISLOWER(*p) || ISDIGIT (*p)
+ || (p[0] == '_' && (ISLOWER (p[1]) || ISDIGIT (p[1]))));
+ }
+ else if (p[0] == 'O')
+ {
+ /* An operator name. */
+ static const char * const operators[][2] =
+ {{"Oabs", "abs"}, {"Oand", "and"}, {"Omod", "mod"},
+ {"Onot", "not"}, {"Oor", "or"}, {"Orem", "rem"},
+ {"Oxor", "xor"}, {"Oeq", "="}, {"One", "/="},
+ {"Olt", "<"}, {"Ole", "<="}, {"Ogt", ">"},
+ {"Oge", ">="}, {"Oadd", "+"}, {"Osubtract", "-"},
+ {"Oconcat", "&"}, {"Omultiply", "*"}, {"Odivide", "/"},
+ {"Oexpon", "**"}, {NULL, NULL}};
+ int k;
+
+ for (k = 0; operators[k][0] != NULL; k++)
+ {
+ size_t slen = strlen (operators[k][0]);
+ if (strncmp (p, operators[k][0], slen) == 0)
+ {
+ p += slen;
+ slen = strlen (operators[k][1]);
+ *d++ = '"';
+ memcpy (d, operators[k][1], slen);
+ d += slen;
+ *d++ = '"';
+ break;
+ }
+ }
+ /* Operator not found. */
+ if (operators[k][0] == NULL)
+ goto unknown;
+ }
+ else
+ {
+ /* Not a GNAT encoding. */
+ goto unknown;
+ }
+
+ /* The name can be directly followed by some uppercase letters. */
+ if (p[0] == 'T' && p[1] == 'K')
+ {
+ /* Task stuff. */
+ if (p[2] == 'B' && p[3] == 0)
+ {
+ /* Subprogram for task body. */
+ break;
+ }
+ else if (p[2] == '_' && p[3] == '_')
+ {
+ /* Inner declarations in a task. */
+ p += 4;
+ *d++ = '.';
+ continue;
+ }
+ else
+ goto unknown;
+ }
+ if (p[0] == 'E' && p[1] == 0)
+ {
+ /* Exception name. */
+ goto unknown;
+ }
+ if ((p[0] == 'P' || p[0] == 'N') && p[1] == 0)
+ {
+ /* Protected type subprogram. */
+ break;
+ }
+ if ((*p == 'N' || *p == 'S') && p[1] == 0)
+ {
+ /* Enumerated type name table. */
+ goto unknown;
+ }
+ if (p[0] == 'X')
+ {
+ /* Body nested. */
+ p++;
+ while (p[0] == 'n' || p[0] == 'b')
+ p++;
+ }
+ if (p[0] == 'S' && p[1] != 0 && (p[2] == '_' || p[2] == 0))
+ {
+ /* Stream operations. */
+ const char *name;
+ switch (p[1])
+ {
+ case 'R':
+ name = "'Read";
+ break;
+ case 'W':
+ name = "'Write";
+ break;
+ case 'I':
+ name = "'Input";
+ break;
+ case 'O':
+ name = "'Output";
+ break;
+ default:
+ goto unknown;
+ }
+ p += 2;
+ strcpy (d, name);
+ d += strlen (name);
+ }
+ else if (p[0] == 'D')
+ {
+ /* Controlled type operation. */
+ const char *name;
+ switch (p[1])
+ {
+ case 'F':
+ name = ".Finalize";
+ break;
+ case 'A':
+ name = ".Adjust";
+ break;
+ default:
+ goto unknown;
+ }
+ strcpy (d, name);
+ d += strlen (name);
+ break;
+ }
+
+ if (p[0] == '_')
+ {
+ /* Separator. */
+ if (p[1] == '_')
+ {
+ /* Standard separator. Handled first. */
+ p += 2;
+
+ if (ISDIGIT (*p))
+ {
+ /* Overloading number. */
+ do
+ p++;
+ while (ISDIGIT (*p) || (p[0] == '_' && ISDIGIT (p[1])));
+ if (*p == 'X')
+ {
+ p++;
+ while (p[0] == 'n' || p[0] == 'b')
+ p++;
+ }
+ }
+ else if (p[0] == '_' && p[1] != '_')
+ {
+ /* Special names. */
+ static const char * const special[][2] = {
+ { "_elabb", "'Elab_Body" },
+ { "_elabs", "'Elab_Spec" },
+ { "_size", "'Size" },
+ { "_alignment", "'Alignment" },
+ { "_assign", ".\":=\"" },
+ { NULL, NULL }
+ };
+ int k;
+
+ for (k = 0; special[k][0] != NULL; k++)
+ {
+ size_t slen = strlen (special[k][0]);
+ if (strncmp (p, special[k][0], slen) == 0)
+ {
+ p += slen;
+ slen = strlen (special[k][1]);
+ memcpy (d, special[k][1], slen);
+ d += slen;
+ break;
+ }
+ }
+ if (special[k][0] != NULL)
+ break;
+ else
+ goto unknown;
+ }
+ else
+ {
+ *d++ = '.';
+ continue;
+ }
+ }
+ else if (p[1] == 'B' || p[1] == 'E')
+ {
+ /* Entry Body or barrier Evaluation. */
+ p += 2;
+ while (ISDIGIT (*p))
+ p++;
+ if (p[0] == 's' && p[1] == 0)
+ break;
+ else
+ goto unknown;
+ }
+ else
+ goto unknown;
+ }
+
+ if (p[0] == '.' && ISDIGIT (p[1]))
+ {
+ /* Nested subprogram. */
+ p += 2;
+ while (ISDIGIT (*p))
+ p++;
+ }
+ if (*p == 0)
+ {
+ /* End of mangled name. */
+ break;
+ }
+ else
+ goto unknown;
+ }
+ *d = 0;
+ return demangled;
+
+ unknown:
+ len0 = strlen (mangled);
+ demangled = XNEWVEC (char, len0 + 3);
if (mangled[0] == '<')
strcpy (demangled, mangled);
@@ -1190,8 +1328,7 @@
int i;
for (i = 0; i < work->ntmpl_args; i++)
- if (work->tmpl_argvec[i])
- free ((char*) work->tmpl_argvec[i]);
+ free ((char*) work->tmpl_argvec[i]);
free ((char*) work->tmpl_argvec);
work->tmpl_argvec = NULL;
diff --git a/main/coregrind/m_demangle/demangle.c b/main/coregrind/m_demangle/demangle.c
index 5b5b422..6e2b1a2 100644
--- a/main/coregrind/m_demangle/demangle.c
+++ b/main/coregrind/m_demangle/demangle.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -75,13 +75,13 @@
impedance-match the libiberty code into our own framework.
The current code is from libiberty in the gcc tree, gcc svn
- r141363, dated 26 Oct 2008 (when the gcc trunk was in Stage 3
- leading up to a gcc-4.4 release). As of r141363, libiberty is LGPL
+ r181975, dated 12 Dec 2011 (when the gcc trunk was in Stage 3
+ leading up to a gcc-4.7 release). As of r141363, libiberty is LGPL
2.1, which AFAICT is compatible with "GPL 2 or later" and so is OK
for inclusion in Valgrind.
To update to a newer libiberty, it might be simplest to svn diff
- the gcc tree libibery against r141363 and then apply those diffs
+ the gcc tree libibery against r181975 and then apply those diffs
here. */
/* This is the main, standard demangler entry point. */
diff --git a/main/coregrind/m_demangle/demangle.h b/main/coregrind/m_demangle/demangle.h
index 145d9fd..c0215a1 100644
--- a/main/coregrind/m_demangle/demangle.h
+++ b/main/coregrind/m_demangle/demangle.h
@@ -1,6 +1,6 @@
/* Defs for interface to demanglers.
Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002,
- 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
+ 2003, 2004, 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public License
@@ -47,7 +47,13 @@
#define DMGL_VERBOSE (1 << 3) /* Include implementation details. */
#define DMGL_TYPES (1 << 4) /* Also try to demangle type encodings. */
#define DMGL_RET_POSTFIX (1 << 5) /* Print function return types (when
- present) after function signature */
+ present) after function signature.
+ It applies only to the toplevel
+ function type. */
+#define DMGL_RET_DROP (1 << 6) /* Suppress printing function return
+ types, even if present. It applies
+ only to the toplevel function type.
+ */
#define DMGL_AUTO (1 << 8)
#define DMGL_GNU (1 << 9)
@@ -162,10 +168,14 @@
extern char*
java_demangle_v3 (const char *mangled);
+char *
+ada_demangle (const char *mangled, int options);
+
enum gnu_v3_ctor_kinds {
gnu_v3_complete_object_ctor = 1,
gnu_v3_base_object_ctor,
- gnu_v3_complete_object_allocating_ctor
+ gnu_v3_complete_object_allocating_ctor,
+ gnu_v3_object_ctor_group
};
/* Return non-zero iff NAME is the mangled form of a constructor name
@@ -179,7 +189,8 @@
enum gnu_v3_dtor_kinds {
gnu_v3_deleting_dtor = 1,
gnu_v3_complete_object_dtor,
- gnu_v3_base_object_dtor
+ gnu_v3_base_object_dtor,
+ gnu_v3_object_dtor_group
};
/* Return non-zero iff NAME is the mangled form of a destructor name
@@ -223,6 +234,8 @@
/* A template parameter. This holds a number, which is the template
parameter index. */
DEMANGLE_COMPONENT_TEMPLATE_PARAM,
+ /* A function parameter. This holds a number, which is the index. */
+ DEMANGLE_COMPONENT_FUNCTION_PARAM,
/* A constructor. This holds a name and the kind of
constructor. */
DEMANGLE_COMPONENT_CTOR,
@@ -321,6 +334,11 @@
and the right subtree is the member type. CV-qualifiers appear
on the latter. */
DEMANGLE_COMPONENT_PTRMEM_TYPE,
+ /* A fixed-point type. */
+ DEMANGLE_COMPONENT_FIXED_TYPE,
+ /* A vector type. The left subtree is the number of elements,
+ the right subtree is the element type. */
+ DEMANGLE_COMPONENT_VECTOR_TYPE,
/* An argument list. The left subtree is the current argument, and
the right subtree is either NULL or another ARGLIST node. */
DEMANGLE_COMPONENT_ARGLIST,
@@ -373,10 +391,31 @@
DEMANGLE_COMPONENT_COMPOUND_NAME,
/* A name formed by a single character. */
DEMANGLE_COMPONENT_CHARACTER,
+ /* A number. */
+ DEMANGLE_COMPONENT_NUMBER,
/* A decltype type. */
DEMANGLE_COMPONENT_DECLTYPE,
+ /* Global constructors keyed to name. */
+ DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS,
+ /* Global destructors keyed to name. */
+ DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS,
+ /* A lambda closure type. */
+ DEMANGLE_COMPONENT_LAMBDA,
+ /* A default argument scope. */
+ DEMANGLE_COMPONENT_DEFAULT_ARG,
+ /* An unnamed type. */
+ DEMANGLE_COMPONENT_UNNAMED_TYPE,
+ /* A transactional clone. This has one subtree, the encoding for
+ which it is providing alternative linkage. */
+ DEMANGLE_COMPONENT_TRANSACTION_CLONE,
+ /* A non-transactional clone entry point. In the i386/x86_64 abi,
+ the unmangled symbol of a tm_callable becomes a thunk and the
+ non-transactional function version is mangled thus. */
+ DEMANGLE_COMPONENT_NONTRANSACTION_CLONE,
/* A pack expansion. */
- DEMANGLE_COMPONENT_PACK_EXPANSION
+ DEMANGLE_COMPONENT_PACK_EXPANSION,
+ /* A cloned function. */
+ DEMANGLE_COMPONENT_CLONE
};
/* Types which are only used internally. */
@@ -421,6 +460,17 @@
struct demangle_component *name;
} s_extended_operator;
+ /* For DEMANGLE_COMPONENT_FIXED_TYPE. */
+ struct
+ {
+ /* The length, indicated by a C integer type name. */
+ struct demangle_component *length;
+ /* _Accum or _Fract? */
+ short accum;
+ /* Saturating or not? */
+ short sat;
+ } s_fixed;
+
/* For DEMANGLE_COMPONENT_CTOR. */
struct
{
@@ -455,10 +505,10 @@
int len;
} s_string;
- /* For DEMANGLE_COMPONENT_TEMPLATE_PARAM. */
+ /* For DEMANGLE_COMPONENT_*_PARAM. */
struct
{
- /* Template parameter index. */
+ /* Parameter index. */
long number;
} s_number;
@@ -477,6 +527,14 @@
struct demangle_component *right;
} s_binary;
+ struct
+ {
+ /* subtree, same place as d_left. */
+ struct demangle_component *sub;
+ /* integer. */
+ int num;
+ } s_unary_num;
+
} u;
};
diff --git a/main/coregrind/m_demangle/dyn-string.c b/main/coregrind/m_demangle/dyn-string.c
index 70449dd..0dbb3ac 100644
--- a/main/coregrind/m_demangle/dyn-string.c
+++ b/main/coregrind/m_demangle/dyn-string.c
@@ -349,7 +349,7 @@
return 1;
}
-/* Appends C to the end of DEST. Returns 1 on success. On failiure,
+/* Appends C to the end of DEST. Returns 1 on success. On failure,
if RETURN_ON_ALLOCATION_FAILURE, deletes DEST and returns 0. */
int
diff --git a/main/coregrind/m_demangle/dyn-string.h b/main/coregrind/m_demangle/dyn-string.h
index 44e33de..2b14727 100644
--- a/main/coregrind/m_demangle/dyn-string.h
+++ b/main/coregrind/m_demangle/dyn-string.h
@@ -1,5 +1,6 @@
/* An abstract string datatype.
- Copyright (C) 1998, 1999, 2000, 2002, 2004 Free Software Foundation, Inc.
+ Copyright (C) 1998, 1999, 2000, 2002, 2004, 2005, 2009
+ Free Software Foundation, Inc.
Contributed by Mark Mitchell (mark@markmitchell.com).
This file is part of GCC.
@@ -19,6 +20,12 @@
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
+#ifndef DYN_STRING_H
+#define DYN_STRING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
typedef struct dyn_string
{
@@ -58,3 +65,9 @@
extern int dyn_string_append_char (dyn_string_t, int);
extern int dyn_string_substring (dyn_string_t, dyn_string_t, int, int);
extern int dyn_string_eq (dyn_string_t, dyn_string_t);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined (DYN_STRING_H) */
diff --git a/main/coregrind/m_demangle/vg_libciface.h b/main/coregrind/m_demangle/vg_libciface.h
index 66835ee..0d2b35e 100644
--- a/main/coregrind/m_demangle/vg_libciface.h
+++ b/main/coregrind/m_demangle/vg_libciface.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_dispatch/dispatch-amd64-darwin.S b/main/coregrind/m_dispatch/dispatch-amd64-darwin.S
index 6354281..165666a 100644
--- a/main/coregrind/m_dispatch/dispatch-amd64-darwin.S
+++ b/main/coregrind/m_dispatch/dispatch-amd64-darwin.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -39,29 +39,35 @@
/*------------------------------------------------------------*/
/*--- ---*/
-/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
-/*--- run all translations except no-redir ones. ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
/*--- ---*/
/*------------------------------------------------------------*/
/*----------------------------------------------------*/
-/*--- Preamble (set everything up) ---*/
+/*--- Entry and preamble (set everything up) ---*/
/*----------------------------------------------------*/
/* signature:
-UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
*/
-
.text
-.globl VG_(run_innerloop)
-VG_(run_innerloop):
- /* %rdi holds guest_state */
- /* %rsi holds do_profiling */
-
- /* ----- entry point to VG_(run_innerloop) ----- */
+.globl VG_(disp_run_translations)
+VG_(disp_run_translations):
+ /* %rdi holds two_words */
+ /* %rsi holds guest_state */
+ /* %rdx holds host_addr */
+
+ /* The preamble */
+
+ /* Save integer registers, since this is a pseudo-function. */
+ pushq %rax
pushq %rbx
pushq %rcx
- pushq %rdx
+ pushq %rdx
pushq %rsi
pushq %rbp
pushq %r8
@@ -72,20 +78,10 @@
pushq %r13
pushq %r14
pushq %r15
- pushq %rdi /* guest_state */
+ /* %rdi must be saved last */
+ pushq %rdi
- movq VG_(dispatch_ctr)@GOTPCREL(%rip), %r15
- movl (%r15), %r15d
- pushq %r15
-
- /* 8(%rsp) holds cached copy of guest_state ptr */
- /* 0(%rsp) holds cached copy of VG_(dispatch_ctr) */
-
- /* Set up the guest state pointer */
- movq %rdi, %rbp
-
- /* fetch %RIP into %rax */
- movq OFFSET_amd64_RIP(%rbp), %rax
+ /* Get the host CPU in the state expected by generated code. */
/* set host FPU control word to the default mode expected
by VEX-generated code. See comments in libvex.h for
@@ -104,153 +100,37 @@
/* set dir flag to known value */
cld
- /* fall into main loop (the right one) */
- cmpq $0, %rsi
- je VG_(run_innerloop__dispatch_unassisted_unprofiled)
- jmp VG_(run_innerloop__dispatch_unassisted_profiled)
- /*NOTREACHED*/
+ /* Set up the guest state pointer */
+ movq %rsi, %rbp
+
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ jmpq *%rdx
+ /*NOTREACHED*/
/*----------------------------------------------------*/
-/*--- NO-PROFILING (standard) dispatcher ---*/
+/*--- Postamble and exit. ---*/
/*----------------------------------------------------*/
-.align 4
-.globl VG_(run_innerloop__dispatch_unassisted_unprofiled)
-VG_(run_innerloop__dispatch_unassisted_unprofiled):
- /* AT ENTRY: %rax is next guest addr, %rbp is the
- unmodified guest state ptr */
-
- /* save the jump address in the guest state */
- movq %rax, OFFSET_amd64_RIP(%rbp)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subl $1, 0(%rsp)
- jz counter_is_zero
-
- /* try a fast lookup in the translation cache */
- movabsq $VG_(tt_fast), %rcx
- movq %rax, %rbx
- andq $VG_TT_FAST_MASK, %rbx /* entry# */
- shlq $4, %rbx /* entry# * sizeof(FastCacheEntry) */
- movq 0(%rcx,%rbx,1), %r10 /* .guest */
- movq 8(%rcx,%rbx,1), %r11 /* .host */
- cmpq %rax, %r10
- jnz fast_lookup_failed
-
- /* Found a match. Jump to .host. */
- jmp *%r11
- ud2 /* persuade insn decoders not to speculate past here */
- /* generated code should run, then jump back to
- VG_(run_innerloop__dispatch_{un,}assisted_unprofiled). */
- /*NOTREACHED*/
-
-.align 4
-.globl VG_(run_innerloop__dispatch_assisted_unprofiled)
-VG_(run_innerloop__dispatch_assisted_unprofiled):
- /* AT ENTRY: %rax is next guest addr, %rbp is the
- modified guest state ptr. Since the GSP has changed,
- jump directly to gsp_changed. */
- jmp gsp_changed
- ud2
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- PROFILING dispatcher (can be much slower) ---*/
-/*----------------------------------------------------*/
-
-.align 4
-.globl VG_(run_innerloop__dispatch_unassisted_profiled)
-VG_(run_innerloop__dispatch_unassisted_profiled):
- /* AT ENTRY: %rax is next guest addr, %rbp is the
- unmodified guest state ptr */
-
- /* save the jump address in the guest state */
- movq %rax, OFFSET_amd64_RIP(%rbp)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subl $1, 0(%rsp)
- jz counter_is_zero
-
- /* try a fast lookup in the translation cache */
- movabsq $VG_(tt_fast), %rcx
- movq %rax, %rbx
- andq $VG_TT_FAST_MASK, %rbx /* entry# */
- shlq $4, %rbx /* entry# * sizeof(FastCacheEntry) */
- movq 0(%rcx,%rbx,1), %r10 /* .guest */
- movq 8(%rcx,%rbx,1), %r11 /* .host */
- cmpq %rax, %r10
- jnz fast_lookup_failed
-
- /* increment bb profile counter */
- movabsq $VG_(tt_fastN), %rdx
- shrq $1, %rbx /* entry# * sizeof(UInt*) */
- movq (%rdx,%rbx,1), %rdx
- addl $1, (%rdx)
-
- /* Found a match. Jump to .host. */
- jmp *%r11
- ud2 /* persuade insn decoders not to speculate past here */
- /* generated code should run, then jump back to
- VG_(run_innerloop__dispatch_{un,}assisted_profiled). */
- /*NOTREACHED*/
-
-.align 4
-.globl VG_(run_innerloop__dispatch_assisted_profiled)
-VG_(run_innerloop__dispatch_assisted_profiled):
- /* AT ENTRY: %rax is next guest addr, %rbp is the
- modified guest state ptr. Since the GSP has changed,
- jump directly to gsp_changed. */
- jmp gsp_changed
- ud2
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- exit points ---*/
-/*----------------------------------------------------*/
-
-gsp_changed:
- /* Someone messed with the gsp. Have to
- defer to scheduler to resolve this. dispatch ctr
- is not yet decremented, so no need to increment. */
- /* %RIP is NOT up to date here. First, need to write
- %rax back to %RIP, but without trashing %rbp since
- that holds the value we want to return to the scheduler.
- Hence use %r15 transiently for the guest state pointer. */
- movq 8(%rsp), %r15
- movq %rax, OFFSET_amd64_RIP(%r15)
- movq %rbp, %rax
- jmp run_innerloop_exit
- /*NOTREACHED*/
-
-counter_is_zero:
- /* %RIP is up to date here */
- /* back out decrement of the dispatch counter */
- addl $1, 0(%rsp)
- movq $VG_TRC_INNER_COUNTERZERO, %rax
- jmp run_innerloop_exit
-
-fast_lookup_failed:
- /* %RIP is up to date here */
- /* back out decrement of the dispatch counter */
- addl $1, 0(%rsp)
- movq $VG_TRC_INNER_FASTMISS, %rax
- jmp run_innerloop_exit
-
-
-
-/* All exits from the dispatcher go through here. %rax holds
- the return value.
-*/
-run_innerloop_exit:
- /* We're leaving. Check that nobody messed with
- %mxcsr or %fpucw. We can't mess with %rax here as it
- holds the tentative return value, but any other is OK. */
+postamble:
+ /* At this point, %rax and %rdx contain two
+ words to be returned to the caller. %rax
+ holds a TRC value, and %rdx optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
+
+ /* We're leaving. Check that nobody messed with %mxcsr
+ or %fpucw. We can't mess with %rax or %rdx here as they
+ hold the tentative return values, but any others are OK. */
#if !defined(ENABLE_INNER)
/* This check fails for self-hosting, so skip in that case */
pushq $0
fstcw (%rsp)
cmpl $0x027F, (%rsp)
- popq %r15 /* get rid of the word without trashing %eflags */
+ popq %r15 /* get rid of the word without trashing %rflags */
jnz invariant_violation
#endif
pushq $0
@@ -260,20 +140,17 @@
popq %r15
jnz invariant_violation
/* otherwise we're OK */
- jmp run_innerloop_exit_REALLY
-
+ jmp remove_frame
invariant_violation:
movq $VG_TRC_INVARIANT_FAILED, %rax
- jmp run_innerloop_exit_REALLY
+ movq $0, %rdx
-run_innerloop_exit_REALLY:
-
- /* restore VG_(dispatch_ctr) */
- popq %r14
- movq VG_(dispatch_ctr)@GOTPCREL(%rip), %r15
- movl %r14d, (%r15)
-
+remove_frame:
+ /* Pop %rdi, stash return values */
popq %rdi
+ movq %rax, 0(%rdi)
+ movq %rdx, 8(%rdi)
+ /* Now pop everything else */
popq %r15
popq %r14
popq %r13
@@ -287,58 +164,89 @@
popq %rdx
popq %rcx
popq %rbx
+ popq %rax
ret
+
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
-
-/*------------------------------------------------------------*/
-/*--- ---*/
-/*--- A special dispatcher, for running no-redir ---*/
-/*--- translations. Just runs the given translation once. ---*/
-/*--- ---*/
-/*------------------------------------------------------------*/
+/* ------ Chain me to slow entry point ------ */
+.globl VG_(disp_cp_chain_me_to_slowEP)
+VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ movq $VG_TRC_CHAIN_ME_TO_SLOW_EP, %rax
+ popq %rdx
+ /* 10 = movabsq $VG_(disp_chain_me_to_slowEP), %r11;
+ 3 = call *%r11 */
+ subq $10+3, %rdx
+ jmp postamble
-/* signature:
-void VG_(run_a_noredir_translation) ( UWord* argblock );
-*/
+/* ------ Chain me to fast entry point ------ */
+.globl VG_(disp_cp_chain_me_to_fastEP)
+VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_F, RA) */
+ movq $VG_TRC_CHAIN_ME_TO_FAST_EP, %rax
+ popq %rdx
+ /* 10 = movabsq $VG_(disp_chain_me_to_fastEP), %r11;
+ 3 = call *%r11 */
+ subq $10+3, %rdx
+ jmp postamble
-/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
- and 2 to carry results:
- 0: input: ptr to translation
- 1: input: ptr to guest state
- 2: output: next guest PC
- 3: output: guest state pointer afterwards (== thread return code)
-*/
-.align 4
-.globl VG_(run_a_noredir_translation)
-VG_(run_a_noredir_translation):
- /* Save callee-saves regs */
- pushq %rbx
- pushq %rbp
- pushq %r12
- pushq %r13
- pushq %r14
- pushq %r15
+/* ------ Indirect but boring jump ------ */
+.globl VG_(disp_cp_xindir)
+VG_(disp_cp_xindir):
+ /* Where are we going? */
+ movq OFFSET_amd64_RIP(%rbp), %rax
- pushq %rdi /* we will need it after running the translation */
- movq 8(%rdi), %rbp
- jmp *0(%rdi)
- /*NOTREACHED*/
- ud2
- /* If the translation has been correctly constructed, we
- should resume at the the following label. */
-.globl VG_(run_a_noredir_translation__return_point)
-VG_(run_a_noredir_translation__return_point):
- popq %rdi
- movq %rax, 16(%rdi)
- movq %rbp, 24(%rdi)
+ /* stats only */
+ movabsq $VG_(stats__n_xindirs_32), %r10
+ addl $1, (%r10)
+
+ /* try a fast lookup in the translation cache */
+ movabsq $VG_(tt_fast), %rcx
+ movq %rax, %rbx /* next guest addr */
+ andq $VG_TT_FAST_MASK, %rbx /* entry# */
+ shlq $4, %rbx /* entry# * sizeof(FastCacheEntry) */
+ movq 0(%rcx,%rbx,1), %r10 /* .guest */
+ movq 8(%rcx,%rbx,1), %r11 /* .host */
+ cmpq %rax, %r10
+ jnz fast_lookup_failed
- popq %r15
- popq %r14
- popq %r13
- popq %r12
- popq %rbp
- popq %rbx
- ret
+ /* Found a match. Jump to .host. */
+ jmp *%r11
+ ud2 /* persuade insn decoders not to speculate past here */
+
+fast_lookup_failed:
+ /* stats only */
+ movabsq $VG_(stats__n_xindir_misses_32), %r10
+ addl $1, (%r10)
+
+ movq $VG_TRC_INNER_FASTMISS, %rax
+ movq $0, %rdx
+ jmp postamble
+
+/* ------ Assisted jump ------ */
+.globl VG_(disp_cp_xassisted)
+VG_(disp_cp_xassisted):
+ /* %rbp contains the TRC */
+ movq %rbp, %rax
+ movq $0, %rdx
+ jmp postamble
+
+/* ------ Event check failed ------ */
+.globl VG_(disp_cp_evcheck_fail)
+VG_(disp_cp_evcheck_fail):
+ movq $VG_TRC_INNER_COUNTERZERO, %rax
+ movq $0, %rdx
+ jmp postamble
+
#endif // defined(VGP_amd64_darwin)
diff --git a/main/coregrind/m_dispatch/dispatch-amd64-linux.S b/main/coregrind/m_dispatch/dispatch-amd64-linux.S
index a3e22d5..c6a0ea0 100644
--- a/main/coregrind/m_dispatch/dispatch-amd64-linux.S
+++ b/main/coregrind/m_dispatch/dispatch-amd64-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -39,30 +39,36 @@
/*------------------------------------------------------------*/
/*--- ---*/
-/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
-/*--- run all translations except no-redir ones. ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
/*--- ---*/
/*------------------------------------------------------------*/
/*----------------------------------------------------*/
-/*--- Preamble (set everything up) ---*/
+/*--- Entry and preamble (set everything up) ---*/
/*----------------------------------------------------*/
/* signature:
-UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
*/
-
.text
-.globl VG_(run_innerloop)
-.type VG_(run_innerloop), @function
-VG_(run_innerloop):
- /* %rdi holds guest_state */
- /* %rsi holds do_profiling */
-
- /* ----- entry point to VG_(run_innerloop) ----- */
+.globl VG_(disp_run_translations)
+.type VG_(disp_run_translations), @function
+VG_(disp_run_translations):
+ /* %rdi holds two_words */
+ /* %rsi holds guest_state */
+ /* %rdx holds host_addr */
+
+ /* The preamble */
+
+ /* Save integer registers, since this is a pseudo-function. */
+ pushq %rax
pushq %rbx
pushq %rcx
- pushq %rdx
+ pushq %rdx
pushq %rsi
pushq %rbp
pushq %r8
@@ -73,20 +79,10 @@
pushq %r13
pushq %r14
pushq %r15
- pushq %rdi /* guest_state */
+ /* %rdi must be saved last */
+ pushq %rdi
- movq VG_(dispatch_ctr)@GOTPCREL(%rip), %r15
- movl (%r15), %r15d
- pushq %r15
-
- /* 8(%rsp) holds cached copy of guest_state ptr */
- /* 0(%rsp) holds cached copy of VG_(dispatch_ctr) */
-
- /* Set up the guest state pointer */
- movq %rdi, %rbp
-
- /* fetch %RIP into %rax */
- movq OFFSET_amd64_RIP(%rbp), %rax
+ /* Get the host CPU in the state expected by generated code. */
/* set host FPU control word to the default mode expected
by VEX-generated code. See comments in libvex.h for
@@ -105,158 +101,37 @@
/* set dir flag to known value */
cld
- /* fall into main loop (the right one) */
- cmpq $0, %rsi
- je VG_(run_innerloop__dispatch_unassisted_unprofiled)
- jmp VG_(run_innerloop__dispatch_unassisted_profiled)
- /*NOTREACHED*/
+ /* Set up the guest state pointer */
+ movq %rsi, %rbp
+
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ jmpq *%rdx
+ /*NOTREACHED*/
/*----------------------------------------------------*/
-/*--- NO-PROFILING (standard) dispatcher ---*/
+/*--- Postamble and exit. ---*/
/*----------------------------------------------------*/
-.align 16
-.global VG_(run_innerloop__dispatch_unassisted_unprofiled)
-VG_(run_innerloop__dispatch_unassisted_unprofiled):
- /* AT ENTRY: %rax is next guest addr, %rbp is the
- unmodified guest state ptr */
-
- /* save the jump address in the guest state */
- movq %rax, OFFSET_amd64_RIP(%rbp)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subl $1, 0(%rsp)
- jz counter_is_zero
-
- /* try a fast lookup in the translation cache */
- movabsq $VG_(tt_fast), %rcx
- movq %rax, %rbx /* next guest addr */
- andq $VG_TT_FAST_MASK, %rbx /* entry# */
- shlq $4, %rbx /* entry# * sizeof(FastCacheEntry) */
- movq 0(%rcx,%rbx,1), %r10 /* .guest */
- movq 8(%rcx,%rbx,1), %r11 /* .host */
- cmpq %rax, %r10
- jnz fast_lookup_failed
-
- /* Found a match. Jump to .host. */
- jmp *%r11
- ud2 /* persuade insn decoders not to speculate past here */
- /* generated code should run, then jump back to either
- VG_(run_innerloop__dispatch_unassisted_unprofiled)
- VG_(run_innerloop__dispatch_assisted_unprofiled). */
- /*NOTREACHED*/
-
-.align 16
-.global VG_(run_innerloop__dispatch_assisted_unprofiled)
-VG_(run_innerloop__dispatch_assisted_unprofiled):
- /* AT ENTRY: %rax is next guest addr, %rbp is the
- modified guest state ptr */
- /* We know the guest state pointer has been modified.
- So jump directly to gsp_changed. */
- jmp gsp_changed
- ud2
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- PROFILING dispatcher (can be much slower) ---*/
-/*----------------------------------------------------*/
-
-.align 16
-.global VG_(run_innerloop__dispatch_unassisted_profiled)
-VG_(run_innerloop__dispatch_unassisted_profiled):
- /* AT ENTRY: %rax is next guest addr, %rbp is the
- unmodified guest state ptr */
-
- /* save the jump address in the guest state */
- movq %rax, OFFSET_amd64_RIP(%rbp)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subl $1, 0(%rsp)
- jz counter_is_zero
-
- /* try a fast lookup in the translation cache */
- movabsq $VG_(tt_fast), %rcx
- movq %rax, %rbx
- andq $VG_TT_FAST_MASK, %rbx /* entry# */
- shlq $4, %rbx /* entry# * sizeof(FastCacheEntry) */
- movq 0(%rcx,%rbx,1), %r10 /* .guest */
- movq 8(%rcx,%rbx,1), %r11 /* .host */
- cmpq %rax, %r10
- jnz fast_lookup_failed
-
- /* increment bb profile counter */
- movabsq $VG_(tt_fastN), %rdx
- shrq $1, %rbx /* entry# * sizeof(UInt*) */
- movq (%rdx,%rbx,1), %rdx
- addl $1, (%rdx)
-
- /* Found a match. Jump to .host. */
- jmp *%r11
- ud2 /* persuade insn decoders not to speculate past here */
- /* generated code should run, then jump back to either
- VG_(run_innerloop__dispatch_unassisted_profiled)
- VG_(run_innerloop__dispatch_assisted_profiled). */
- /*NOTREACHED*/
-
-.align 16
-.global VG_(run_innerloop__dispatch_assisted_profiled)
-VG_(run_innerloop__dispatch_assisted_profiled):
- /* AT ENTRY: %rax is next guest addr, %rbp is the
- modified guest state ptr */
-
- /* Well, we know the guest state pointer has been modified.
- So jump directly to gsp_changed. */
- jmp gsp_changed
- ud2
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- exit points ---*/
-/*----------------------------------------------------*/
-
-gsp_changed:
- /* Someone messed with the gsp. Have to
- defer to scheduler to resolve this. dispatch ctr
- is not yet decremented, so no need to increment. */
- /* %RIP is NOT up to date here. First, need to write
- %rax back to %RIP, but without trashing %rbp since
- that holds the value we want to return to the scheduler.
- Hence use %r15 transiently for the guest state pointer. */
- movq 8(%rsp), %r15
- movq %rax, OFFSET_amd64_RIP(%r15)
- movq %rbp, %rax
- jmp run_innerloop_exit
- /*NOTREACHED*/
-
-counter_is_zero:
- /* %RIP is up to date here */
- /* back out decrement of the dispatch counter */
- addl $1, 0(%rsp)
- movq $VG_TRC_INNER_COUNTERZERO, %rax
- jmp run_innerloop_exit
-
-fast_lookup_failed:
- /* %RIP is up to date here */
- /* back out decrement of the dispatch counter */
- addl $1, 0(%rsp)
- movq $VG_TRC_INNER_FASTMISS, %rax
- jmp run_innerloop_exit
-
-
-
-/* All exits from the dispatcher go through here. %rax holds
- the return value.
-*/
-run_innerloop_exit:
- /* We're leaving. Check that nobody messed with
- %mxcsr or %fpucw. We can't mess with %rax here as it
- holds the tentative return value, but any other is OK. */
+postamble:
+ /* At this point, %rax and %rdx contain two
+ words to be returned to the caller. %rax
+ holds a TRC value, and %rdx optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
+
+ /* We're leaving. Check that nobody messed with %mxcsr
+ or %fpucw. We can't mess with %rax or %rdx here as they
+ hold the tentative return values, but any others are OK. */
#if !defined(ENABLE_INNER)
/* This check fails for self-hosting, so skip in that case */
pushq $0
fstcw (%rsp)
cmpl $0x027F, (%rsp)
- popq %r15 /* get rid of the word without trashing %eflags */
+ popq %r15 /* get rid of the word without trashing %rflags */
jnz invariant_violation
#endif
pushq $0
@@ -266,20 +141,17 @@
popq %r15
jnz invariant_violation
/* otherwise we're OK */
- jmp run_innerloop_exit_REALLY
-
+ jmp remove_frame
invariant_violation:
movq $VG_TRC_INVARIANT_FAILED, %rax
- jmp run_innerloop_exit_REALLY
+ movq $0, %rdx
-run_innerloop_exit_REALLY:
-
- /* restore VG_(dispatch_ctr) */
- popq %r14
- movq VG_(dispatch_ctr)@GOTPCREL(%rip), %r15
- movl %r14d, (%r15)
-
+remove_frame:
+ /* Pop %rdi, stash return values */
popq %rdi
+ movq %rax, 0(%rdi)
+ movq %rdx, 8(%rdi)
+ /* Now pop everything else */
popq %r15
popq %r14
popq %r13
@@ -293,61 +165,89 @@
popq %rdx
popq %rcx
popq %rbx
+ popq %rax
ret
-.size VG_(run_innerloop), .-VG_(run_innerloop)
+
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
-
-/*------------------------------------------------------------*/
-/*--- ---*/
-/*--- A special dispatcher, for running no-redir ---*/
-/*--- translations. Just runs the given translation once. ---*/
-/*--- ---*/
-/*------------------------------------------------------------*/
+/* ------ Chain me to slow entry point ------ */
+.global VG_(disp_cp_chain_me_to_slowEP)
+VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ movq $VG_TRC_CHAIN_ME_TO_SLOW_EP, %rax
+ popq %rdx
+ /* 10 = movabsq $VG_(disp_chain_me_to_slowEP), %r11;
+ 3 = call *%r11 */
+ subq $10+3, %rdx
+ jmp postamble
-/* signature:
-void VG_(run_a_noredir_translation) ( UWord* argblock );
-*/
+/* ------ Chain me to fast entry point ------ */
+.global VG_(disp_cp_chain_me_to_fastEP)
+VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_F, RA) */
+ movq $VG_TRC_CHAIN_ME_TO_FAST_EP, %rax
+ popq %rdx
+ /* 10 = movabsq $VG_(disp_chain_me_to_fastEP), %r11;
+ 3 = call *%r11 */
+ subq $10+3, %rdx
+ jmp postamble
-/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
- and 2 to carry results:
- 0: input: ptr to translation
- 1: input: ptr to guest state
- 2: output: next guest PC
- 3: output: guest state pointer afterwards (== thread return code)
-*/
-.align 16
-.global VG_(run_a_noredir_translation)
-.type VG_(run_a_noredir_translation), @function
-VG_(run_a_noredir_translation):
- /* Save callee-saves regs */
- pushq %rbx
- pushq %rbp
- pushq %r12
- pushq %r13
- pushq %r14
- pushq %r15
+/* ------ Indirect but boring jump ------ */
+.global VG_(disp_cp_xindir)
+VG_(disp_cp_xindir):
+ /* Where are we going? */
+ movq OFFSET_amd64_RIP(%rbp), %rax
- pushq %rdi /* we will need it after running the translation */
- movq 8(%rdi), %rbp
- jmp *0(%rdi)
- /*NOTREACHED*/
- ud2
- /* If the translation has been correctly constructed, we
- should resume at the the following label. */
-.global VG_(run_a_noredir_translation__return_point)
-VG_(run_a_noredir_translation__return_point):
- popq %rdi
- movq %rax, 16(%rdi)
- movq %rbp, 24(%rdi)
+ /* stats only */
+ addl $1, VG_(stats__n_xindirs_32)
+
+ /* try a fast lookup in the translation cache */
+ movabsq $VG_(tt_fast), %rcx
+ movq %rax, %rbx /* next guest addr */
+ andq $VG_TT_FAST_MASK, %rbx /* entry# */
+ shlq $4, %rbx /* entry# * sizeof(FastCacheEntry) */
+ movq 0(%rcx,%rbx,1), %r10 /* .guest */
+ movq 8(%rcx,%rbx,1), %r11 /* .host */
+ cmpq %rax, %r10
+ jnz fast_lookup_failed
- popq %r15
- popq %r14
- popq %r13
- popq %r12
- popq %rbp
- popq %rbx
- ret
-.size VG_(run_a_noredir_translation), .-VG_(run_a_noredir_translation)
+ /* Found a match. Jump to .host. */
+ jmp *%r11
+ ud2 /* persuade insn decoders not to speculate past here */
+
+fast_lookup_failed:
+ /* stats only */
+ addl $1, VG_(stats__n_xindir_misses_32)
+
+ movq $VG_TRC_INNER_FASTMISS, %rax
+ movq $0, %rdx
+ jmp postamble
+
+/* ------ Assisted jump ------ */
+.global VG_(disp_cp_xassisted)
+VG_(disp_cp_xassisted):
+ /* %rbp contains the TRC */
+ movq %rbp, %rax
+ movq $0, %rdx
+ jmp postamble
+
+/* ------ Event check failed ------ */
+.global VG_(disp_cp_evcheck_fail)
+VG_(disp_cp_evcheck_fail):
+ movq $VG_TRC_INNER_COUNTERZERO, %rax
+ movq $0, %rdx
+ jmp postamble
+
+
+.size VG_(disp_run_translations), .-VG_(disp_run_translations)
/* Let the linker know we don't need an executable stack */
.section .note.GNU-stack,"",@progbits
diff --git a/main/coregrind/m_dispatch/dispatch-arm-linux.S b/main/coregrind/m_dispatch/dispatch-arm-linux.S
index 9e23349..348af7c 100644
--- a/main/coregrind/m_dispatch/dispatch-arm-linux.S
+++ b/main/coregrind/m_dispatch/dispatch-arm-linux.S
@@ -1,3 +1,4 @@
+
/*--------------------------------------------------------------------*/
/*--- The core dispatch loop, for jumping to a code address. ---*/
/*--- dispatch-arm-linux.S ---*/
@@ -7,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 Evan Geller
+ Copyright (C) 2008-2012 Evan Geller
gaze@bea.ms
This program is free software; you can redistribute it and/or
@@ -39,256 +40,171 @@
/*------------------------------------------------------------*/
/*--- ---*/
-/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
-/*--- run all translations except no-redir ones. ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
/*--- ---*/
/*------------------------------------------------------------*/
/*----------------------------------------------------*/
-/*--- Preamble (set everything up) ---*/
+/*--- Entry and preamble (set everything up) ---*/
/*----------------------------------------------------*/
/* signature:
-UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
*/
.text
-.globl VG_(run_innerloop)
-VG_(run_innerloop):
- push {r0, r1, r4, r5, r6, r7, r8, r9, fp, lr}
+.global VG_(disp_run_translations)
+VG_(disp_run_translations):
+ /* r0 holds two_words
+ r1 holds guest_state
+ r2 holds host_addr
+ */
+ /* The number of regs in this list needs to be even, in
+ order to keep the stack 8-aligned. */
+ push {r0, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}
/* set FPSCR to vex-required default value */
mov r4, #0
fmxr fpscr, r4
- /* r0 (hence also [sp,#0]) holds guest_state */
- /* r1 holds do_profiling */
- mov r8, r0
- ldr r0, [r8, #OFFSET_arm_R15T]
+ /* Set up the guest state pointer */
+ mov r8, r1
+
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ bx r2
+ /* NOTREACHED */
- /* fall into main loop (the right one) */
- cmp r1, #0 /* do_profiling */
- beq VG_(run_innerloop__dispatch_unprofiled)
- b VG_(run_innerloop__dispatch_profiled)
-
-
/*----------------------------------------------------*/
-/*--- NO-PROFILING (standard) dispatcher ---*/
+/*--- Postamble and exit. ---*/
/*----------------------------------------------------*/
-/* Pairing of insns below is my guesstimate of how dual dispatch would
- work on an A8. JRS, 2011-May-28 */
-
-.global VG_(run_innerloop__dispatch_unprofiled)
-VG_(run_innerloop__dispatch_unprofiled):
+postamble:
+ /* At this point, r1 and r2 contain two
+ words to be returned to the caller. r1
+ holds a TRC value, and r2 optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
- /* AT ENTRY: r0 is next guest addr, r8 is possibly
- modified guest state ptr */
-
- /* Has the guest state pointer been messed with? If yes, exit. */
- movw r3, #:lower16:VG_(dispatch_ctr)
- tst r8, #1
-
- movt r3, #:upper16:VG_(dispatch_ctr)
-
- bne gsp_changed
-
- /* save the jump address in the guest state */
- str r0, [r8, #OFFSET_arm_R15T]
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- ldr r2, [r3]
-
- subs r2, r2, #1
-
- str r2, [r3]
-
- beq counter_is_zero
-
- /* try a fast lookup in the translation cache */
- // r0 = next guest, r1,r2,r3,r4 scratch
- movw r1, #VG_TT_FAST_MASK // r1 = VG_TT_FAST_MASK
- movw r4, #:lower16:VG_(tt_fast)
-
- and r2, r1, r0, LSR #1 // r2 = entry #
- movt r4, #:upper16:VG_(tt_fast) // r4 = &VG_(tt_fast)
-
- add r1, r4, r2, LSL #3 // r1 = &tt_fast[entry#]
-
- ldrd r4, r5, [r1, #0] // r4 = .guest, r5 = .host
-
- cmp r4, r0
-
- bne fast_lookup_failed
- // r5: next-host r8: live, gsp
- // r4: next-guest
- // r2: entry #
- // LIVE: r5, r8; all others dead
-
- /* Found a match. Jump to .host. */
- blx r5
- b VG_(run_innerloop__dispatch_unprofiled)
-.ltorg
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- PROFILING dispatcher (can be much slower) ---*/
-/*----------------------------------------------------*/
-
-.global VG_(run_innerloop__dispatch_profiled)
-VG_(run_innerloop__dispatch_profiled):
-
- /* AT ENTRY: r0 is next guest addr, r8 is possibly
- modified guest state ptr */
-
- /* Has the guest state pointer been messed with? If yes, exit. */
- movw r3, #:lower16:VG_(dispatch_ctr)
- tst r8, #1
-
- movt r3, #:upper16:VG_(dispatch_ctr)
-
- bne gsp_changed
-
- /* save the jump address in the guest state */
- str r0, [r8, #OFFSET_arm_R15T]
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- ldr r2, [r3]
-
- subs r2, r2, #1
-
- str r2, [r3]
-
- beq counter_is_zero
-
- /* try a fast lookup in the translation cache */
- // r0 = next guest, r1,r2,r3,r4 scratch
- movw r1, #VG_TT_FAST_MASK // r1 = VG_TT_FAST_MASK
- movw r4, #:lower16:VG_(tt_fast)
-
- and r2, r1, r0, LSR #1 // r2 = entry #
- movt r4, #:upper16:VG_(tt_fast) // r4 = &VG_(tt_fast)
-
- add r1, r4, r2, LSL #3 // r1 = &tt_fast[entry#]
-
- ldrd r4, r5, [r1, #0] // r4 = .guest, r5 = .host
-
- cmp r4, r0
-
- bne fast_lookup_failed
- // r5: next-host r8: live, gsp
- // r4: next-guest
- // r2: entry #
- // LIVE: r5, r8; all others dead
-
- /* increment bb profile counter */
- movw r0, #:lower16:VG_(tt_fastN)
- movt r0, #:upper16:VG_(tt_fastN) // r0 = &tt_fastN[0]
- ldr r0, [r0, r2, LSL #2] // r0 = tt_fast[entry #]
- ldr r3, [r0] // *r0 ++
- add r3, r3, #1
- str r3, [r0]
-
- /* Found a match. Jump to .host. */
- blx r5
- b VG_(run_innerloop__dispatch_profiled)
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- exit points ---*/
-/*----------------------------------------------------*/
-
-gsp_changed:
- // r0 = next guest addr (R15T), r8 = modified gsp
- /* Someone messed with the gsp. Have to
- defer to scheduler to resolve this. dispatch ctr
- is not yet decremented, so no need to increment. */
- /* R15T is NOT up to date here. First, need to write
- r0 back to R15T, but without trashing r8 since
- that holds the value we want to return to the scheduler.
- Hence use r1 transiently for the guest state pointer. */
- ldr r1, [sp, #0]
- str r0, [r1, #OFFSET_arm_R15T]
- mov r0, r8 // "return modified gsp"
- b run_innerloop_exit
- /*NOTREACHED*/
-
-counter_is_zero:
- /* R15T is up to date here */
- /* Back out increment of the dispatch ctr */
- ldr r1, =VG_(dispatch_ctr)
- ldr r2, [r1]
- add r2, r2, #1
- str r2, [r1]
- mov r0, #VG_TRC_INNER_COUNTERZERO
- b run_innerloop_exit
- /*NOTREACHED*/
-
-fast_lookup_failed:
- /* R15T is up to date here */
- /* Back out increment of the dispatch ctr */
- ldr r1, =VG_(dispatch_ctr)
- ldr r2, [r1]
- add r2, r2, #1
- str r2, [r1]
- mov r0, #VG_TRC_INNER_FASTMISS
- b run_innerloop_exit
- /*NOTREACHED*/
-
-/* All exits from the dispatcher go through here. %r0 holds
- the return value.
-*/
-run_innerloop_exit:
/* We're leaving. Check that nobody messed with
FPSCR in ways we don't expect. */
fmrx r4, fpscr
bic r4, #0xF8000000 /* mask out NZCV and QC */
bic r4, #0x0000009F /* mask out IDC,IXC,UFC,OFC,DZC,IOC */
cmp r4, #0
- bne invariant_violation
- b run_innerloop_exit_REALLY
+ beq remove_frame /* we're OK */
+ /* otherwise we have an invariant violation */
+ movw r1, #VG_TRC_INVARIANT_FAILED
+ movw r2, #0
+ /* fall through */
-invariant_violation:
- mov r0, #VG_TRC_INVARIANT_FAILED
- b run_innerloop_exit_REALLY
+remove_frame:
+ /* Restore int regs, including importantly r0 (two_words) */
+ pop {r0, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}
+ /* Stash return values */
+ str r1, [r0, #0]
+ str r2, [r0, #4]
+ bx lr
-run_innerloop_exit_REALLY:
- add sp, sp, #8
- pop {r4, r5, r6, r7, r8, r9, fp, pc}
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
-.size VG_(run_innerloop), .-VG_(run_innerloop)
+/* ------ Chain me to slow entry point ------ */
+.global VG_(disp_cp_chain_me_to_slowEP)
+VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ mov r1, #VG_TRC_CHAIN_ME_TO_SLOW_EP
+ mov r2, lr
+ /* 4 = movw r12, lo16(disp_cp_chain_me_to_slowEP)
+ 4 = movt r12, hi16(disp_cp_chain_me_to_slowEP)
+ 4 = blx r12 */
+ sub r2, r2, #4+4+4
+ b postamble
+
+/* ------ Chain me to fast entry point ------ */
+.global VG_(disp_cp_chain_me_to_fastEP)
+VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_F, RA) */
+ mov r1, #VG_TRC_CHAIN_ME_TO_FAST_EP
+ mov r2, lr
+ /* 4 = movw r12, lo16(disp_cp_chain_me_to_fastEP)
+ 4 = movt r12, hi16(disp_cp_chain_me_to_fastEP)
+ 4 = blx r12 */
+ sub r2, r2, #4+4+4
+ b postamble
+
+/* ------ Indirect but boring jump ------ */
+.global VG_(disp_cp_xindir)
+VG_(disp_cp_xindir):
+ /* Where are we going? */
+ ldr r0, [r8, #OFFSET_arm_R15T]
+
+ /* stats only */
+ movw r1, #:lower16:vgPlain_stats__n_xindirs_32
+ movt r1, #:upper16:vgPlain_stats__n_xindirs_32
+ ldr r2, [r1, #0]
+ add r2, r2, #1
+ str r2, [r1, #0]
+
+ /* try a fast lookup in the translation cache */
+ // r0 = next guest, r1,r2,r3,r4 scratch
+ movw r1, #VG_TT_FAST_MASK // r1 = VG_TT_FAST_MASK
+ movw r4, #:lower16:VG_(tt_fast)
+
+ and r2, r1, r0, LSR #1 // r2 = entry #
+ movt r4, #:upper16:VG_(tt_fast) // r4 = &VG_(tt_fast)
+
+ add r1, r4, r2, LSL #3 // r1 = &tt_fast[entry#]
+
+ ldrd r4, r5, [r1, #0] // r4 = .guest, r5 = .host
+
+ cmp r4, r0
+
+ // jump to host if lookup succeeded
+ bxeq r5
+
+ /* otherwise the fast lookup failed */
+ /* RM ME -- stats only */
+ movw r1, #:lower16:vgPlain_stats__n_xindir_misses_32
+ movt r1, #:upper16:vgPlain_stats__n_xindir_misses_32
+ ldr r2, [r1, #0]
+ add r2, r2, #1
+ str r2, [r1, #0]
+
+ mov r1, #VG_TRC_INNER_FASTMISS
+ mov r2, #0
+ b postamble
+
+/* ------ Assisted jump ------ */
+.global VG_(disp_cp_xassisted)
+VG_(disp_cp_xassisted):
+ /* r8 contains the TRC */
+ mov r1, r8
+ mov r2, #0
+ b postamble
+
+/* ------ Event check failed ------ */
+.global VG_(disp_cp_evcheck_fail)
+VG_(disp_cp_evcheck_fail):
+ mov r1, #VG_TRC_INNER_COUNTERZERO
+ mov r2, #0
+ b postamble
-/*------------------------------------------------------------*/
-/*--- ---*/
-/*--- A special dispatcher, for running no-redir ---*/
-/*--- translations. Just runs the given translation once. ---*/
-/*--- ---*/
-/*------------------------------------------------------------*/
-
-/* signature:
-void VG_(run_a_noredir_translation) ( UWord* argblock );
-*/
-
-/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
- and 2 to carry results:
- 0: input: ptr to translation
- 1: input: ptr to guest state
- 2: output: next guest PC
- 3: output: guest state pointer afterwards (== thread return code)
-*/
-.global VG_(run_a_noredir_translation)
-VG_(run_a_noredir_translation):
- push {r0,r1 /* EABI compliance */, r4-r12, lr}
- ldr r8, [r0, #4]
- mov lr, pc
- ldr pc, [r0, #0]
-
- pop {r1}
- str r0, [r1, #8]
- str r8, [r1, #12]
- pop {r1/*EABI compliance*/,r4-r12, pc}
-
-.size VG_(run_a_noredir_translation), .-VG_(run_a_noredir_translation)
+.size VG_(disp_run_translations), .-VG_(disp_run_translations)
/* Let the linker know we don't need an executable stack */
.section .note.GNU-stack,"",%progbits
diff --git a/main/coregrind/m_dispatch/dispatch-mips32-linux.S b/main/coregrind/m_dispatch/dispatch-mips32-linux.S
new file mode 100644
index 0000000..4fcba08
--- /dev/null
+++ b/main/coregrind/m_dispatch/dispatch-mips32-linux.S
@@ -0,0 +1,249 @@
+
+/*--------------------------------------------------------------------*/
+/*--- The core dispatch loop, for jumping to a code address. ---*/
+/*--- dispatch-mips-linux.S ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2000-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+
+#if defined(VGP_mips32_linux)
+
+#include "pub_core_basics_asm.h"
+#include "pub_core_dispatch_asm.h"
+#include "pub_core_transtab_asm.h"
+#include "libvex_guest_offsets.h" /* for OFFSET_mips_PC */
+
+
+/*------------------------------------------------------------*/
+/*--- ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
+/*--- ---*/
+/*------------------------------------------------------------*/
+
+/*----------------------------------------------------*/
+/*--- Entry and preamble (set everything up) ---*/
+/*----------------------------------------------------*/
+
+/* signature:
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
+*/
+
+.text
+.globl VG_(disp_run_translations)
+VG_(disp_run_translations):
+ /* a0 ($4) holds two_words */
+ /* a1 ($5) holds guest_state */
+ /* a2 ($6) holds host_addr */
+
+ /* New stack frame. Stack must remain 8 aligned (at least) */
+ addiu $29, -56
+
+ /* Save ra */
+ sw $31, 0($29)
+
+ /* ... and orig guest state*/
+ sw $5, 4($29)
+
+ /* ... and s0 - s7 */
+ sw $16, 8($29)
+ sw $17, 12($29)
+ sw $18, 16($29)
+ sw $19, 20($29)
+ sw $20, 24($29)
+ sw $21, 28($29)
+ sw $22, 32($29)
+ sw $23, 36($29)
+
+ /* ... and gp, fp/s8 */
+ sw $28, 40($29)
+ sw $30, 44($29)
+
+ /* Save a0 ($4) on stack. In postamble it will be restored such that the
+ return values can be written */
+ sw $4, 48($29)
+
+ /* Load address of guest state into guest state register (r10) */
+ move $10, $5
+
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ jr $6
+ /*NOTREACHED*/
+
+/*----------------------------------------------------*/
+/*--- Postamble and exit. ---*/
+/*----------------------------------------------------*/
+
+postamble:
+ /* At this point, r2 and r3 contain two
+ words to be returned to the caller. r2
+ holds a TRC value, and r3 optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
+
+ /* Restore $4 from stack; holds address of two_words */
+ lw $4, 48($29)
+ sw $2, 0($4) /* Store $2 to two_words[0] */
+ sw $3, 4($4) /* Store $3 to two_words[1] */
+
+ /* Restore callee-saved registers... */
+
+ /* Restore ra */
+ lw $31, 0($29)
+
+ /* ... and s0 - s7 */
+ lw $16, 8($29)
+ lw $17, 12($29)
+ lw $18, 16($29)
+ lw $19, 20($29)
+ lw $20, 24($29)
+ lw $21, 28($29)
+ lw $22, 32($29)
+ lw $23, 36($29)
+
+ /* ... and gp, fp/s8 */
+ lw $28, 40($29)
+ lw $30, 44($29)
+
+
+ addiu $29, 56 /* stack_size */
+ jr $31
+ nop
+
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
+
+/* ------ Chain me to slow entry point ------ */
+.global VG_(disp_cp_chain_me_to_slowEP)
+VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li $2, VG_TRC_CHAIN_ME_TO_SLOW_EP
+ move $3, $31
+ /* 8 = mkLoadImm_EXACTLY2or5
+ 4 = jalr $9
+ 4 = nop */
+ addiu $3, $3, -16
+ b postamble
+
+/* ------ Chain me to slow entry point ------ */
+.global VG_(disp_cp_chain_me_to_fastEP)
+VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li $2, VG_TRC_CHAIN_ME_TO_FAST_EP
+ move $3, $31
+ /* 8 = mkLoadImm_EXACTLY2or5
+ 4 = jalr $9
+ 4 = nop */
+ addiu $3, $3, -16
+ b postamble
+
+/* ------ Indirect but boring jump ------ */
+.global VG_(disp_cp_xindir)
+VG_(disp_cp_xindir):
+ /* Where are we going? */
+ lw $11, OFFSET_mips32_PC($10)
+
+ lw $13, vgPlain_stats__n_xindirs_32
+ addiu $13, $13, 0x1
+ sw $13, vgPlain_stats__n_xindirs_32
+
+ /* try a fast lookup in the translation cache */
+ /* t1 = VG_TT_FAST_HASH(addr) * sizeof(ULong*)
+ = (t8 >> 2 & VG_TT_FAST_MASK) << 3 */
+
+ move $14, $11
+ li $12, VG_TT_FAST_MASK
+ srl $14, $14, 2
+ and $14, $14, $12
+ sll $14, $14, 3
+
+ /* t2 = (addr of VG_(tt_fast)) + t1 */
+ la $13, VG_(tt_fast)
+ addu $13, $13, $14
+
+ lw $12, 0($13) /* t3 = VG_(tt_fast)[hash] :: ULong* */
+ addi $13, $13, 4
+ lw $25, 0($13) /* little-endian, so comparing 1st 32bit word */
+ nop
+
+check:
+ bne $12, $11, fast_lookup_failed
+ /* run the translation */
+ jr $25
+ .long 0x0 /* persuade insn decoders not to speculate past here */
+
+fast_lookup_failed:
+ /* %PC is up to date */
+ /* back out decrement of the dispatch counter */
+ /* hold dispatch_ctr in t0 (r8) */
+ lw $13, vgPlain_stats__n_xindirs_32
+ addiu $13, $13, 0x1
+ sw $13, vgPlain_stats__n_xindirs_32
+ li $2, VG_TRC_INNER_FASTMISS
+ li $3, 0
+ b postamble
+
+/* ------ Assisted jump ------ */
+ .global VG_(disp_cp_xassisted)
+VG_(disp_cp_xassisted):
+ /* guest-state-pointer contains the TRC. Put the value into the
+ return register */
+ move $2, $10
+ move $3, $0
+ b postamble
+
+/* ------ Event check failed ------ */
+ .global VG_(disp_cp_evcheck_fail)
+VG_(disp_cp_evcheck_fail):
+ li $2, VG_TRC_INNER_COUNTERZERO
+ move $3, $0
+ b postamble
+
+.size VG_(disp_run_translations), .-VG_(disp_run_translations)
+
+
+/* Let the linker know we do not need an executable stack */
+.section .note.GNU-stack,"",@progbits
+
+#endif // defined(VGP_mips32_linux)
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_dispatch/dispatch-ppc32-linux.S b/main/coregrind/m_dispatch/dispatch-ppc32-linux.S
index edf6065..1689b53 100644
--- a/main/coregrind/m_dispatch/dispatch-ppc32-linux.S
+++ b/main/coregrind/m_dispatch/dispatch-ppc32-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Cerion Armour-Brown <cerion@open-works.co.uk>
+ Copyright (C) 2005-2012 Cerion Armour-Brown <cerion@open-works.co.uk>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -39,26 +39,30 @@
/*------------------------------------------------------------*/
/*--- ---*/
-/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
-/*--- run all translations except no-redir ones. ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
/*--- ---*/
/*------------------------------------------------------------*/
/*----------------------------------------------------*/
-/*--- Preamble (set everything up) ---*/
+/*--- Entry and preamble (set everything up) ---*/
/*----------------------------------------------------*/
/* signature:
-UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
*/
.text
-.globl VG_(run_innerloop)
-.type VG_(run_innerloop), @function
-VG_(run_innerloop):
- /* r3 holds guest_state */
- /* r4 holds do_profiling */
+.globl VG_(disp_run_translations)
+.type VG_(disp_run_translations), @function
+VG_(disp_run_translations):
+ /* r3 holds two_words */
+ /* r4 holds guest_state */
+ /* r5 holds host_addr */
- /* ----- entry point to VG_(run_innerloop) ----- */
+ /* ----- entry point to VG_(disp_run_translations) ----- */
/* For Linux/ppc32 we need the SysV ABI, which uses
LR->4(parent_sp), CR->anywhere.
(The AIX ABI, used on Darwin,
@@ -66,17 +70,17 @@
*/
/* Save lr */
- mflr 0
- stw 0,4(1)
+ mflr 6
+ stw 6,4(1)
/* New stack frame */
stwu 1,-496(1) /* sp should maintain 16-byte alignment */
/* Save callee-saved registers... */
- /* r3, r4 are live here, so use r5 */
- lis 5,VG_(machine_ppc32_has_FP)@ha
- lwz 5,VG_(machine_ppc32_has_FP)@l(5)
- cmplwi 5,0
+ /* r3, r4, r5 are live here, so use r6 */
+ lis 6,VG_(machine_ppc32_has_FP)@ha
+ lwz 6,VG_(machine_ppc32_has_FP)@l(6)
+ cmplwi 6,0
beq LafterFP1
/* Floating-point reg save area : 144 bytes */
@@ -100,7 +104,7 @@
stfd 14,352(1)
LafterFP1:
- /* General reg save area : 72 bytes */
+ /* General reg save area : 76 bytes */
stw 31,348(1)
stw 30,344(1)
stw 29,340(1)
@@ -119,67 +123,65 @@
stw 16,288(1)
stw 15,284(1)
stw 14,280(1)
- /* Probably not necessary to save r13 (thread-specific ptr),
- as VEX stays clear of it... but what the hey. */
stw 13,276(1)
+ stw 3,272(1) /* save two_words for later */
/* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI.
The Linux kernel might not actually use VRSAVE for its intended
purpose, but it should be harmless to preserve anyway. */
- /* r3, r4 are live here, so use r5 */
- lis 5,VG_(machine_ppc32_has_VMX)@ha
- lwz 5,VG_(machine_ppc32_has_VMX)@l(5)
- cmplwi 5,0
+ /* r3, r4, r5 are live here, so use r6 */
+ lis 6,VG_(machine_ppc32_has_VMX)@ha
+ lwz 6,VG_(machine_ppc32_has_VMX)@l(6)
+ cmplwi 6,0
beq LafterVMX1
#ifdef HAS_ALTIVEC
/* VRSAVE save word : 32 bytes */
- mfspr 5,256 /* vrsave reg is spr number 256 */
- stw 5,244(1)
+ mfspr 6,256 /* vrsave reg is spr number 256 */
+ stw 6,244(1)
/* Alignment padding : 4 bytes */
/* Vector reg save area (quadword aligned) : 192 bytes */
- li 5,224
- stvx 31,5,1
- li 5,208
- stvx 30,5,1
- li 5,192
- stvx 29,5,1
- li 5,176
- stvx 28,5,1
- li 5,160
- stvx 27,5,1
- li 5,144
- stvx 26,5,1
- li 5,128
- stvx 25,5,1
- li 5,112
- stvx 25,5,1
- li 5,96
- stvx 23,5,1
- li 5,80
- stvx 22,5,1
- li 5,64
- stvx 21,5,1
- li 5,48
- stvx 20,5,1
+ li 6,224
+ stvx 31,6,1
+ li 6,208
+ stvx 30,6,1
+ li 6,192
+ stvx 29,6,1
+ li 6,176
+ stvx 28,6,1
+ li 6,160
+ stvx 27,6,1
+ li 6,144
+ stvx 26,6,1
+ li 6,128
+ stvx 25,6,1
+ li 6,112
+ stvx 25,6,1
+ li 6,96
+ stvx 23,6,1
+ li 6,80
+ stvx 22,6,1
+ li 6,64
+ stvx 21,6,1
+ li 6,48
+ stvx 20,6,1
#endif
LafterVMX1:
/* Save cr */
- mfcr 0
- stw 0,44(1)
+ mfcr 6
+ stw 6,44(1)
/* Local variable space... */
/* 32(sp) used later to check FPSCR[RM] */
- /* r3 holds guest_state */
- /* r4 holds do_profiling */
- mr 31,3 /* r31 (generated code gsp) = r3 */
- stw 3,28(1) /* spill orig guest_state ptr */
+ /* r3 holds two_words */
+ /* r4 holds guest_state */
+ /* r5 holds host_addr */
/* 24(sp) used later to stop ctr reg being clobbered */
/* 20(sp) used later to load fpscr with zero */
@@ -190,36 +192,29 @@
0(sp) : back-chain
*/
- /* CAB TODO: Use a caller-saved reg for orig guest_state ptr
- - rem to set non-allocateable in isel.c */
-
- /* hold dispatch_ctr in r29 */
- lis 5,VG_(dispatch_ctr)@ha
- lwz 29,VG_(dispatch_ctr)@l(5)
-
/* set host FPU control word to the default mode expected
by VEX-generated code. See comments in libvex.h for
more info. */
- lis 5,VG_(machine_ppc32_has_FP)@ha
- lwz 5,VG_(machine_ppc32_has_FP)@l(5)
- cmplwi 5,0
+ lis 6,VG_(machine_ppc32_has_FP)@ha
+ lwz 6,VG_(machine_ppc32_has_FP)@l(6)
+ cmplwi 6,0
beq LafterFP2
/* get zero into f3 (tedious) */
/* note: fsub 3,3,3 is not a reliable way to do this,
since if f3 holds a NaN or similar then we don't necessarily
wind up with zero. */
- li 5,0
- stw 5,20(1)
+ li 6,0
+ stw 6,20(1)
lfs 3,20(1)
mtfsf 0xFF,3 /* fpscr = f3 */
LafterFP2:
/* set host AltiVec control word to the default mode expected
by VEX-generated code. */
- lis 5,VG_(machine_ppc32_has_VMX)@ha
- lwz 5,VG_(machine_ppc32_has_VMX)@l(5)
- cmplwi 5,0
+ lis 6,VG_(machine_ppc32_has_VMX)@ha
+ lwz 6,VG_(machine_ppc32_has_VMX)@l(6)
+ cmplwi 6,0
beq LafterVMX2
#ifdef HAS_ALTIVEC
@@ -232,172 +227,40 @@
/* make a stack frame for the code we are calling */
stwu 1,-16(1)
- /* fetch %CIA into r3 */
- lwz 3,OFFSET_ppc32_CIA(31)
+ /* Set up the guest state ptr */
+ mr 31,4 /* r31 (generated code gsp) = r4 */
- /* fall into main loop (the right one) */
- /* r4 = do_profiling. It's probably trashed after here,
- but that's OK: we don't need it after here. */
- cmplwi 4,0
- beq VG_(run_innerloop__dispatch_unprofiled)
- b VG_(run_innerloop__dispatch_profiled)
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ mtctr 5
+ bctr
/*NOTREACHED*/
/*----------------------------------------------------*/
-/*--- NO-PROFILING (standard) dispatcher ---*/
+/*--- Postamble and exit. ---*/
/*----------------------------------------------------*/
-.global VG_(run_innerloop__dispatch_unprofiled)
-VG_(run_innerloop__dispatch_unprofiled):
- /* At entry: Live regs:
- r1 (=sp)
- r3 (=CIA = next guest address)
- r29 (=dispatch_ctr)
- r31 (=guest_state)
- */
- /* Has the guest state pointer been messed with? If yes, exit.
- Also set up & VG_(tt_fast) early in an attempt at better
- scheduling. */
- lis 5,VG_(tt_fast)@ha
- addi 5,5,VG_(tt_fast)@l /* & VG_(tt_fast) */
- andi. 0,31,1
- bne gsp_changed
+postamble:
+ /* At this point, r6 and r7 contain two
+ words to be returned to the caller. r6
+ holds a TRC value, and r7 optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
- /* save the jump address in the guest state */
- stw 3,OFFSET_ppc32_CIA(31)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subi 29,29,1
- cmplwi 29,0
- beq counter_is_zero
-
- /* try a fast lookup in the translation cache */
- /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
- = ((r3 >>u 2) & VG_TT_FAST_MASK) << 3 */
- rlwinm 4,3,1, 29-VG_TT_FAST_BITS, 28 /* entry# * 8 */
- add 5,5,4 /* & VG_(tt_fast)[entry#] */
- lwz 6,0(5) /* .guest */
- lwz 7,4(5) /* .host */
- cmpw 3,6
- bne fast_lookup_failed
-
- /* Found a match. Call .host. */
- mtctr 7
- bctrl
-
- /* On return from guest code:
- r3 holds destination (original) address.
- r31 may be unchanged (guest_state), or may indicate further
- details of the control transfer requested to *r3.
- */
- /* start over */
- b VG_(run_innerloop__dispatch_unprofiled)
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- PROFILING dispatcher (can be much slower) ---*/
-/*----------------------------------------------------*/
-
-.global VG_(run_innerloop__dispatch_profiled)
-VG_(run_innerloop__dispatch_profiled):
- /* At entry: Live regs:
- r1 (=sp)
- r3 (=CIA = next guest address)
- r29 (=dispatch_ctr)
- r31 (=guest_state)
- */
- /* Has the guest state pointer been messed with? If yes, exit.
- Also set up & VG_(tt_fast) early in an attempt at better
- scheduling. */
- lis 5,VG_(tt_fast)@ha
- addi 5,5,VG_(tt_fast)@l /* & VG_(tt_fast) */
- andi. 0,31,1
- bne gsp_changed
-
- /* save the jump address in the guest state */
- stw 3,OFFSET_ppc32_CIA(31)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subi 29,29,1
- cmplwi 29,0
- beq counter_is_zero
-
- /* try a fast lookup in the translation cache */
- /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
- = ((r3 >>u 2) & VG_TT_FAST_MASK) << 3 */
- rlwinm 4,3,1, 29-VG_TT_FAST_BITS, 28 /* entry# * 8 */
- add 5,5,4 /* & VG_(tt_fast)[entry#] */
- lwz 6,0(5) /* .guest */
- lwz 7,4(5) /* .host */
- cmpw 3,6
- bne fast_lookup_failed
-
- /* increment bb profile counter */
- srwi 4,4,1 /* entry# * sizeof(UInt*) */
- addis 6,4,VG_(tt_fastN)@ha
- lwz 9,VG_(tt_fastN)@l(6)
- lwz 8,0(9)
- addi 8,8,1
- stw 8,0(9)
-
- /* Found a match. Call .host. */
- mtctr 7
- bctrl
-
- /* On return from guest code:
- r3 holds destination (original) address.
- r31 may be unchanged (guest_state), or may indicate further
- details of the control transfer requested to *r3.
- */
- /* start over */
- b VG_(run_innerloop__dispatch_profiled)
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- exit points ---*/
-/*----------------------------------------------------*/
-
-gsp_changed:
- /* Someone messed with the gsp (in r31). Have to
- defer to scheduler to resolve this. dispatch ctr
- is not yet decremented, so no need to increment. */
- /* %CIA is NOT up to date here. First, need to write
- %r3 back to %CIA, but without trashing %r31 since
- that holds the value we want to return to the scheduler.
- Hence use %r5 transiently for the guest state pointer. */
- lwz 5,44(1) /* original guest_state ptr */
- stw 3,OFFSET_ppc32_CIA(5)
- mr 3,31 /* r3 = new gsp value */
- b run_innerloop_exit
- /*NOTREACHED*/
-
-counter_is_zero:
- /* %CIA is up to date */
- /* back out decrement of the dispatch counter */
- addi 29,29,1
- li 3,VG_TRC_INNER_COUNTERZERO
- b run_innerloop_exit
-
-fast_lookup_failed:
- /* %CIA is up to date */
- /* back out decrement of the dispatch counter */
- addi 29,29,1
- li 3,VG_TRC_INNER_FASTMISS
- b run_innerloop_exit
-
-
-
-/* All exits from the dispatcher go through here.
- r3 holds the return value.
-*/
-run_innerloop_exit:
/* We're leaving. Check that nobody messed with
- VSCR or FPSCR. */
-
+ VSCR or FPSCR in ways we don't expect. */
/* Using r10 - value used again further on, so don't trash! */
lis 10,VG_(machine_ppc32_has_FP)@ha
lwz 10,VG_(machine_ppc32_has_FP)@l(10)
- cmplwi 10,0
+
+ /* Using r11 - value used again further on, so don't trash! */
+ lis 11,VG_(machine_ppc32_has_VMX)@ha
+ lwz 11,VG_(machine_ppc32_has_VMX)@l(11)
+
+ cmplwi 10,0 /* Do we have FP ? */
beq LafterFP8
/* Set fpscr back to a known state, since vex-generated code
@@ -410,10 +273,7 @@
mtfsf 0xFF,3 /* fpscr = f3 */
LafterFP8:
- /* Using r11 - value used again further on, so don't trash! */
- lis 11,VG_(machine_ppc32_has_VMX)@ha
- lwz 11,VG_(machine_ppc32_has_VMX)@l(11)
- cmplwi 11,0
+ cmplwi 11,0 /* Do we have altivec? */
beq LafterVMX8
#ifdef HAS_ALTIVEC
@@ -429,32 +289,18 @@
vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */
bt 24,invariant_violation /* branch if all_equal */
#endif
+
LafterVMX8:
-
/* otherwise we're OK */
- b run_innerloop_exit_REALLY
-
+ b remove_frame
invariant_violation:
- li 3,VG_TRC_INVARIANT_FAILED
- b run_innerloop_exit_REALLY
+ li 6,VG_TRC_INVARIANT_FAILED
+ li 7,0
+ /* fall through */
-run_innerloop_exit_REALLY:
- /* r3 holds VG_TRC_* value to return */
-
- /* Return to parent stack */
- addi 1,1,16
-
- /* Write ctr to VG(dispatch_ctr) */
- lis 5,VG_(dispatch_ctr)@ha
- stw 29,VG_(dispatch_ctr)@l(5)
-
- /* Restore cr */
- lwz 0,44(1)
- mtcr 0
-
- /* Restore callee-saved registers... */
-
+remove_frame:
+ /* Restore FP regs */
/* r10 already holds VG_(machine_ppc32_has_FP) value */
cmplwi 10,0
beq LafterFP9
@@ -480,31 +326,11 @@
lfd 14,352(1)
LafterFP9:
- /* General regs */
- lwz 31,348(1)
- lwz 30,344(1)
- lwz 29,340(1)
- lwz 28,336(1)
- lwz 27,332(1)
- lwz 26,328(1)
- lwz 25,324(1)
- lwz 24,320(1)
- lwz 23,316(1)
- lwz 22,312(1)
- lwz 21,308(1)
- lwz 20,304(1)
- lwz 19,300(1)
- lwz 18,296(1)
- lwz 17,292(1)
- lwz 16,288(1)
- lwz 15,284(1)
- lwz 14,280(1)
- lwz 13,276(1)
-
/* r11 already holds VG_(machine_ppc32_has_VMX) value */
cmplwi 11,0
beq LafterVMX9
+ /* Restore Altivec regs */
#ifdef HAS_ALTIVEC
/* VRSAVE */
lwz 4,244(1)
@@ -538,92 +364,136 @@
#endif
LafterVMX9:
- /* reset lr & sp */
+ /* restore int regs, including importantly r3 (two_words) */
+ addi 1,1,16
+ lwz 31,348(1)
+ lwz 30,344(1)
+ lwz 29,340(1)
+ lwz 28,336(1)
+ lwz 27,332(1)
+ lwz 26,328(1)
+ lwz 25,324(1)
+ lwz 24,320(1)
+ lwz 23,316(1)
+ lwz 22,312(1)
+ lwz 21,308(1)
+ lwz 20,304(1)
+ lwz 19,300(1)
+ lwz 18,296(1)
+ lwz 17,292(1)
+ lwz 16,288(1)
+ lwz 15,284(1)
+ lwz 14,280(1)
+ lwz 13,276(1)
+ lwz 3,272(1)
+ /* Stash return values */
+ stw 6,0(3)
+ stw 7,4(3)
+
+ /* restore lr & sp, and leave */
lwz 0,500(1) /* stack_size + 4 */
mtlr 0
addi 1,1,496 /* stack_size */
blr
-.size VG_(run_innerloop), .-VG_(run_innerloop)
-/*------------------------------------------------------------*/
-/*--- ---*/
-/*--- A special dispatcher, for running no-redir ---*/
-/*--- translations. Just runs the given translation once. ---*/
-/*--- ---*/
-/*------------------------------------------------------------*/
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
-/* signature:
-void VG_(run_a_noredir_translation) ( UWord* argblock );
-*/
+/* ------ Chain me to slow entry point ------ */
+.global VG_(disp_cp_chain_me_to_slowEP)
+VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li 6, VG_TRC_CHAIN_ME_TO_SLOW_EP
+ mflr 7
+ /* 8 = imm32-fixed2 r30, disp_cp_chain_me_to_slowEP
+ 4 = mtctr r30
+ 4 = btctr
+ */
+ subi 7,7,8+4+4
+ b postamble
-/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
- and 2 to carry results:
- 0: input: ptr to translation
- 1: input: ptr to guest state
- 2: output: next guest PC
- 3: output: guest state pointer afterwards (== thread return code)
-*/
-.global VG_(run_a_noredir_translation)
-.type VG_(run_a_noredir_translation), @function
-VG_(run_a_noredir_translation):
- /* save callee-save int regs, & lr */
- stwu 1,-256(1)
- stw 14,128(1)
- stw 15,132(1)
- stw 16,136(1)
- stw 17,140(1)
- stw 18,144(1)
- stw 19,148(1)
- stw 20,152(1)
- stw 21,156(1)
- stw 22,160(1)
- stw 23,164(1)
- stw 24,168(1)
- stw 25,172(1)
- stw 26,176(1)
- stw 27,180(1)
- stw 28,184(1)
- stw 29,188(1)
- stw 30,192(1)
- stw 31,196(1)
- mflr 31
- stw 31,200(1)
+/* ------ Chain me to fast entry point ------ */
+.global VG_(disp_cp_chain_me_to_fastEP)
+VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li 6, VG_TRC_CHAIN_ME_TO_FAST_EP
+ mflr 7
+ /* 8 = imm32-fixed2 r30, disp_cp_chain_me_to_fastEP
+ 4 = mtctr r30
+ 4 = btctr
+ */
+ subi 7,7,8+4+4
+ b postamble
- stw 3,204(1)
- lwz 31,4(3)
- lwz 30,0(3)
- mtlr 30
- blrl
+/* ------ Indirect but boring jump ------ */
+.global VG_(disp_cp_xindir)
+VG_(disp_cp_xindir):
+ /* Where are we going? */
+ lwz 3,OFFSET_ppc32_CIA(31)
- lwz 4,204(1)
- stw 3, 8(4)
- stw 31,12(4)
+ /* stats only */
+ lis 5,VG_(stats__n_xindirs_32)@ha
+ addi 5,5,VG_(stats__n_xindirs_32)@l
+ lwz 6,0(5)
+ addi 6,6,1
+ stw 6,0(5)
+
+ /* r5 = &VG_(tt_fast) */
+ lis 5,VG_(tt_fast)@ha
+ addi 5,5,VG_(tt_fast)@l /* & VG_(tt_fast) */
- lwz 14,128(1)
- lwz 15,132(1)
- lwz 16,136(1)
- lwz 17,140(1)
- lwz 18,144(1)
- lwz 19,148(1)
- lwz 20,152(1)
- lwz 21,156(1)
- lwz 22,160(1)
- lwz 23,164(1)
- lwz 24,168(1)
- lwz 25,172(1)
- lwz 26,176(1)
- lwz 27,180(1)
- lwz 28,184(1)
- lwz 29,188(1)
- lwz 30,192(1)
- lwz 31,200(1)
- mtlr 31
- lwz 31,196(1)
- addi 1,1,256
- blr
-.size VG_(run_a_noredir_translation), .-VG_(run_a_noredir_translation)
+ /* try a fast lookup in the translation cache */
+ /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
+ = ((r3 >>u 2) & VG_TT_FAST_MASK) << 3 */
+ rlwinm 4,3,1, 29-VG_TT_FAST_BITS, 28 /* entry# * 8 */
+ add 5,5,4 /* & VG_(tt_fast)[entry#] */
+ lwz 6,0(5) /* .guest */
+ lwz 7,4(5) /* .host */
+ cmpw 3,6
+ bne fast_lookup_failed
+ /* Found a match. Jump to .host. */
+ mtctr 7
+ bctr
+
+fast_lookup_failed:
+ /* stats only */
+ lis 5,VG_(stats__n_xindir_misses_32)@ha
+ addi 5,5,VG_(stats__n_xindir_misses_32)@l
+ lwz 6,0(5)
+ addi 6,6,1
+ stw 6,0(5)
+
+ li 6,VG_TRC_INNER_FASTMISS
+ li 7,0
+ b postamble
+ /*NOTREACHED*/
+
+/* ------ Assisted jump ------ */
+.global VG_(disp_cp_xassisted)
+VG_(disp_cp_xassisted):
+ /* r31 contains the TRC */
+ mr 6,31
+ li 7,0
+ b postamble
+
+/* ------ Event check failed ------ */
+.global VG_(disp_cp_evcheck_fail)
+VG_(disp_cp_evcheck_fail):
+ li 6,VG_TRC_INNER_COUNTERZERO
+ li 7,0
+ b postamble
+
+
+.size VG_(disp_run_translations), .-VG_(disp_run_translations)
/* Let the linker know we don't need an executable stack */
.section .note.GNU-stack,"",@progbits
diff --git a/main/coregrind/m_dispatch/dispatch-ppc64-linux.S b/main/coregrind/m_dispatch/dispatch-ppc64-linux.S
index 4c08a7e..5a4d4bc 100644
--- a/main/coregrind/m_dispatch/dispatch-ppc64-linux.S
+++ b/main/coregrind/m_dispatch/dispatch-ppc64-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Cerion Armour-Brown <cerion@open-works.co.uk>
+ Copyright (C) 2005-2012 Cerion Armour-Brown <cerion@open-works.co.uk>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -39,63 +39,88 @@
/* References to globals via the TOC */
/*
- .globl vgPlain_tt_fast
+ .globl vgPlain_tt_fast
.lcomm vgPlain_tt_fast,4,4
.type vgPlain_tt_fast, @object
*/
- .section ".toc","aw"
+.section ".toc","aw"
.tocent__vgPlain_tt_fast:
.tc vgPlain_tt_fast[TC],vgPlain_tt_fast
-.tocent__vgPlain_tt_fastN:
- .tc vgPlain_tt_fastN[TC],vgPlain_tt_fastN
-.tocent__vgPlain_dispatch_ctr:
- .tc vgPlain_dispatch_ctr[TC],vgPlain_dispatch_ctr
+.tocent__vgPlain_stats__n_xindirs_32:
+ .tc vgPlain_stats__n_xindirs_32[TC],vgPlain_stats__n_xindirs_32
+.tocent__vgPlain_stats__n_xindir_misses_32:
+ .tc vgPlain_stats__n_xindir_misses_32[TC],vgPlain_stats__n_xindir_misses_32
.tocent__vgPlain_machine_ppc64_has_VMX:
.tc vgPlain_machine_ppc64_has_VMX[TC],vgPlain_machine_ppc64_has_VMX
/*------------------------------------------------------------*/
/*--- ---*/
-/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
-/*--- run all translations except no-redir ones. ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
/*--- ---*/
/*------------------------------------------------------------*/
/*----------------------------------------------------*/
-/*--- Preamble (set everything up) ---*/
+/*--- Entry and preamble (set everything up) ---*/
/*----------------------------------------------------*/
/* signature:
-UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
*/
.section ".text"
.align 2
-.globl VG_(run_innerloop)
+.globl VG_(disp_run_translations)
.section ".opd","aw"
.align 3
-VG_(run_innerloop):
-.quad .VG_(run_innerloop),.TOC.@tocbase,0
+VG_(disp_run_translations):
+.quad .VG_(disp_run_translations),.TOC.@tocbase,0
.previous
-.type .VG_(run_innerloop),@function
-.globl .VG_(run_innerloop)
-.VG_(run_innerloop):
- /* r3 holds guest_state */
- /* r4 holds do_profiling */
+.type .VG_(disp_run_translations),@function
+.globl .VG_(disp_run_translations)
+.VG_(disp_run_translations):
+ /* r3 holds two_words */
+ /* r4 holds guest_state */
+ /* r5 holds host_addr */
- /* ----- entry point to VG_(run_innerloop) ----- */
+ /* ----- entry point to VG_(disp_run_translations) ----- */
/* PPC64 ABI saves LR->16(prt_sp), CR->8(prt_sp)) */
/* Save lr, cr */
- mflr 0
- std 0,16(1)
- mfcr 0
- std 0,8(1)
+ mflr 6
+ std 6,16(1)
+ mfcr 6
+ std 6,8(1)
/* New stack frame */
stdu 1,-624(1) /* sp should maintain 16-byte alignment */
- /* Save callee-saved registers... */
+ /* General reg save area : 152 bytes */
+ std 31,472(1)
+ std 30,464(1)
+ std 29,456(1)
+ std 28,448(1)
+ std 27,440(1)
+ std 26,432(1)
+ std 25,424(1)
+ std 24,416(1)
+ std 23,408(1)
+ std 22,400(1)
+ std 21,392(1)
+ std 20,384(1)
+ std 19,376(1)
+ std 18,368(1)
+ std 17,360(1)
+ std 16,352(1)
+ std 15,344(1)
+ std 14,336(1)
+ std 13,328(1)
+ std 3,104(1) /* save two_words for later */
+ /* Save callee-saved registers... */
/* Floating-point reg save area : 144 bytes */
stfd 31,616(1)
stfd 30,608(1)
@@ -116,77 +141,53 @@
stfd 15,488(1)
stfd 14,480(1)
- /* General reg save area : 144 bytes */
- std 31,472(1)
- std 30,464(1)
- std 29,456(1)
- std 28,448(1)
- std 27,440(1)
- std 26,432(1)
- std 25,424(1)
- std 24,416(1)
- std 23,408(1)
- std 22,400(1)
- std 21,392(1)
- std 20,384(1)
- std 19,376(1)
- std 18,368(1)
- std 17,360(1)
- std 16,352(1)
- std 15,344(1)
- std 14,336(1)
- /* Probably not necessary to save r13 (thread-specific ptr),
- as VEX stays clear of it... but what the hey. */
- std 13,328(1)
-
/* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI.
The Linux kernel might not actually use VRSAVE for its intended
purpose, but it should be harmless to preserve anyway. */
- /* r3, r4 are live here, so use r5 */
- ld 5,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
- ld 5,0(5)
- cmpldi 5,0
+ /* r3, r4, r5 are live here, so use r6 */
+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
+ ld 6,0(6)
+ cmpldi 6,0
beq .LafterVMX1
/* VRSAVE save word : 32 bytes */
- mfspr 5,256 /* vrsave reg is spr number 256 */
- stw 5,324(1)
+ mfspr 6,256 /* vrsave reg is spr number 256 */
+ stw 6,324(1)
/* Alignment padding : 4 bytes */
/* Vector reg save area (quadword aligned) : 192 bytes */
- li 5,304
- stvx 31,5,1
- li 5,288
- stvx 30,5,1
- li 5,272
- stvx 29,5,1
- li 5,256
- stvx 28,5,1
- li 5,240
- stvx 27,5,1
- li 5,224
- stvx 26,5,1
- li 5,208
- stvx 25,5,1
- li 5,192
- stvx 24,5,1
- li 5,176
- stvx 23,5,1
- li 5,160
- stvx 22,5,1
- li 5,144
- stvx 21,5,1
- li 5,128
- stvx 20,5,1
+ li 6,304
+ stvx 31,6,1
+ li 6,288
+ stvx 30,6,1
+ li 6,272
+ stvx 29,6,1
+ li 6,256
+ stvx 28,6,1
+ li 6,240
+ stvx 27,6,1
+ li 6,224
+ stvx 26,6,1
+ li 6,208
+ stvx 25,6,1
+ li 6,192
+ stvx 24,6,1
+ li 6,176
+ stvx 23,6,1
+ li 6,160
+ stvx 22,6,1
+ li 6,144
+ stvx 21,6,1
+ li 6,128
+ stvx 20,6,1
.LafterVMX1:
/* Local variable space... */
- /* r3 holds guest_state */
- /* r4 holds do_profiling */
- mr 31,3
- std 3,104(1) /* spill orig guest_state ptr */
+ /* r3 holds two_words */
+ /* r4 holds guest_state */
+ /* r5 holds host_addr */
/* 96(sp) used later to check FPSCR[RM] */
/* 88(sp) used later to load fpscr with zero */
@@ -201,13 +202,6 @@
0(sp) : back-chain
*/
-// CAB TODO: Use a caller-saved reg for orig guest_state ptr
-// - rem to set non-allocateable in isel.c
-
- /* hold dispatch_ctr (=32bit value) in r29 */
- ld 29,.tocent__vgPlain_dispatch_ctr@toc(2)
- lwz 29,0(29) /* 32-bit zero-extending load */
-
/* set host FPU control word to the default mode expected
by VEX-generated code. See comments in libvex.h for
more info. */
@@ -215,16 +209,16 @@
fsub 3,3,3 is not a reliable way to do this, since if
f3 holds a NaN or similar then we don't necessarily
wind up with zero. */
- li 5,0
- stw 5,88(1)
+ li 6,0
+ stw 6,88(1)
lfs 3,88(1)
mtfsf 0xFF,3 /* fpscr = lo32 of f3 */
/* set host AltiVec control word to the default mode expected
by VEX-generated code. */
- ld 5,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
- ld 5,0(5)
- cmpldi 5,0
+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
+ ld 6,0(6)
+ cmpldi 6,0
beq .LafterVMX2
vspltisw 3,0x0 /* generate zero */
@@ -234,196 +228,37 @@
/* make a stack frame for the code we are calling */
stdu 1,-48(1)
- /* fetch %CIA into r3 */
- ld 3,OFFSET_ppc64_CIA(31)
+ /* Set up the guest state ptr */
+ mr 31,4 /* r31 (generated code gsp) = r4 */
- /* fall into main loop (the right one) */
- /* r4 = do_profiling. It's probably trashed after here,
- but that's OK: we don't need it after here. */
- cmplwi 4,0
- beq .VG_(run_innerloop__dispatch_unprofiled)
- b .VG_(run_innerloop__dispatch_profiled)
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ mtctr 5
+ bctr
/*NOTREACHED*/
-
/*----------------------------------------------------*/
-/*--- NO-PROFILING (standard) dispatcher ---*/
+/*--- Postamble and exit. ---*/
/*----------------------------------------------------*/
- .section ".text"
- .align 2
- .globl VG_(run_innerloop__dispatch_unprofiled)
- .section ".opd","aw"
- .align 3
-VG_(run_innerloop__dispatch_unprofiled):
- .quad .VG_(run_innerloop__dispatch_unprofiled),.TOC.@tocbase,0
- .previous
- .type .VG_(run_innerloop__dispatch_unprofiled),@function
- .globl .VG_(run_innerloop__dispatch_unprofiled)
-.VG_(run_innerloop__dispatch_unprofiled):
- /* At entry: Live regs:
- r1 (=sp)
- r2 (toc pointer)
- r3 (=CIA = next guest address)
- r29 (=dispatch_ctr)
- r31 (=guest_state)
- Stack state:
- 144(r1) (=var space for FPSCR[RM])
- */
- /* Has the guest state pointer been messed with? If yes, exit.
- Also set up & VG_(tt_fast) early in an attempt at better
- scheduling. */
- ld 5, .tocent__vgPlain_tt_fast@toc(2) /* &VG_(tt_fast) */
- rldicl. 0,31,0,63
- bne .gsp_changed
+.postamble:
+ /* At this point, r6 and r7 contain two
+ words to be returned to the caller. r6
+ holds a TRC value, and r7 optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
- /* save the jump address in the guest state */
- std 3,OFFSET_ppc64_CIA(31)
+ /* undo the "make a stack frame for the code we are calling" */
+ addi 1,1,48
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subi 29,29,1
- cmpldi 29,0
- beq .counter_is_zero
-
- /* try a fast lookup in the translation cache */
- /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
- = ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */
- rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */
- sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */
- add 5,5,4 /* & VG_(tt_fast)[entry#] */
- ld 6,0(5) /* .guest */
- ld 7,8(5) /* .host */
- cmpd 3,6
- bne .fast_lookup_failed
-
- /* Found a match. Call .host. */
- mtctr 7
- bctrl
-
- /* On return from guest code:
- r3 holds destination (original) address.
- r31 may be unchanged (guest_state), or may indicate further
- details of the control transfer requested to *r3.
- */
- /* start over */
- b .VG_(run_innerloop__dispatch_unprofiled)
- /*NOTREACHED*/
- .size .VG_(run_innerloop), .-.VG_(run_innerloop)
-
-
-/*----------------------------------------------------*/
-/*--- PROFILING dispatcher (can be much slower) ---*/
-/*----------------------------------------------------*/
-
- .section ".text"
- .align 2
- .globl VG_(run_innerloop__dispatch_profiled)
- .section ".opd","aw"
- .align 3
-VG_(run_innerloop__dispatch_profiled):
- .quad .VG_(run_innerloop__dispatch_profiled),.TOC.@tocbase,0
- .previous
- .type .VG_(run_innerloop__dispatch_profiled),@function
- .globl .VG_(run_innerloop__dispatch_profiled)
-.VG_(run_innerloop__dispatch_profiled):
- /* At entry: Live regs:
- r1 (=sp)
- r2 (toc pointer)
- r3 (=CIA = next guest address)
- r29 (=dispatch_ctr)
- r31 (=guest_state)
- Stack state:
- 144(r1) (=var space for FPSCR[RM])
- */
- /* Has the guest state pointer been messed with? If yes, exit.
- Also set up & VG_(tt_fast) early in an attempt at better
- scheduling. */
- ld 5, .tocent__vgPlain_tt_fast@toc(2) /* &VG_(tt_fast) */
- rldicl. 0,31,0,63
- bne .gsp_changed
-
- /* save the jump address in the guest state */
- std 3,OFFSET_ppc64_CIA(31)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subi 29,29,1
- cmpldi 29,0
- beq .counter_is_zero
-
- /* try a fast lookup in the translation cache */
- /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
- = ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */
- rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */
- sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */
- add 5,5,4 /* & VG_(tt_fast)[entry#] */
- ld 6,0(5) /* .guest */
- ld 7,8(5) /* .host */
- cmpd 3,6
- bne .fast_lookup_failed
-
- /* increment bb profile counter VG_(tt_fastN)[x] (=32bit val) */
- ld 9, .tocent__vgPlain_tt_fastN@toc(2)
- srdi 4, 4,1 /* entry# * sizeof(UInt*) */
- ldx 9, 9,4 /* r7 = VG_(tt_fastN)[VG_TT_HASH(addr)] */
- lwz 6, 0(9) /* *(UInt*)r7 ++ */
- addi 6, 6,1
- stw 6, 0(9)
-
- /* Found a match. Call .host. */
- mtctr 7
- bctrl
-
- /* On return from guest code:
- r3 holds destination (original) address.
- r31 may be unchanged (guest_state), or may indicate further
- details of the control transfer requested to *r3.
- */
- /* start over */
- b .VG_(run_innerloop__dispatch_profiled)
- /*NOTREACHED*/
- .size .VG_(run_a_noredir_translation), .-.VG_(run_a_noredir_translation)
-
-
-/*----------------------------------------------------*/
-/*--- exit points ---*/
-/*----------------------------------------------------*/
-
-.gsp_changed:
- /* Someone messed with the gsp (in r31). Have to
- defer to scheduler to resolve this. dispatch ctr
- is not yet decremented, so no need to increment. */
- /* %CIA is NOT up to date here. First, need to write
- %r3 back to %CIA, but without trashing %r31 since
- that holds the value we want to return to the scheduler.
- Hence use %r5 transiently for the guest state pointer. */
- ld 5,152(1) /* original guest_state ptr */
- std 3,OFFSET_ppc64_CIA(5)
- mr 3,31 /* r3 = new gsp value */
- b .run_innerloop_exit
- /*NOTREACHED*/
-
-.counter_is_zero:
- /* %CIA is up to date */
- /* back out decrement of the dispatch counter */
- addi 29,29,1
- li 3,VG_TRC_INNER_COUNTERZERO
- b .run_innerloop_exit
-
-.fast_lookup_failed:
- /* %CIA is up to date */
- /* back out decrement of the dispatch counter */
- addi 29,29,1
- li 3,VG_TRC_INNER_FASTMISS
- b .run_innerloop_exit
-
-
-
-/* All exits from the dispatcher go through here.
- r3 holds the return value.
-*/
-.run_innerloop_exit:
/* We're leaving. Check that nobody messed with
- VSCR or FPSCR. */
+ VSCR or FPSCR in ways we don't expect. */
+ /* Using r11 - value used again further on, so don't trash! */
+ ld 11,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
+ ld 11,0(11)
/* Set fpscr back to a known state, since vex-generated code
may have messed with fpscr[rm]. */
@@ -434,10 +269,7 @@
addi 1,1,16
mtfsf 0xFF,3 /* fpscr = f3 */
- /* Using r11 - value used again further on, so don't trash! */
- ld 11,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2)
- ld 11,0(11)
- cmpldi 11,0
+ cmpldi 11,0 /* Do we have altivec? */
beq .LafterVMX8
/* Check VSCR[NJ] == 1 */
@@ -451,32 +283,55 @@
vspltw 7,7,0x3 /* flags-word to all lanes */
vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */
bt 24,.invariant_violation /* branch if all_equal */
+
.LafterVMX8:
-
/* otherwise we're OK */
- b .run_innerloop_exit_REALLY
-
+ b .remove_frame
.invariant_violation:
- li 3,VG_TRC_INVARIANT_FAILED
- b .run_innerloop_exit_REALLY
+ li 6,VG_TRC_INVARIANT_FAILED
+ li 7,0
+ /* fall through */
-.run_innerloop_exit_REALLY:
- /* r3 holds VG_TRC_* value to return */
+.remove_frame:
+ /* r11 already holds VG_(machine_ppc32_has_VMX) value */
+ cmplwi 11,0
+ beq .LafterVMX9
- /* Return to parent stack */
- addi 1,1,48
+ /* Restore Altivec regs.
+ Use r5 as scratch since r6/r7 are live. */
+ /* VRSAVE */
+ lwz 5,324(1)
+ mfspr 5,256 /* VRSAVE reg is spr number 256 */
- /* Write ctr to VG_(dispatch_ctr) (=32bit value) */
- ld 5,.tocent__vgPlain_dispatch_ctr@toc(2)
- stw 29,0(5)
+ /* Vector regs */
+ li 5,304
+ lvx 31,5,1
+ li 5,288
+ lvx 30,5,1
+ li 5,272
+ lvx 29,5,1
+ li 5,256
+ lvx 28,5,1
+ li 5,240
+ lvx 27,5,1
+ li 5,224
+ lvx 26,5,1
+ li 5,208
+ lvx 25,5,1
+ li 5,192
+ lvx 24,5,1
+ li 5,176
+ lvx 23,5,1
+ li 5,160
+ lvx 22,5,1
+ li 5,144
+ lvx 21,5,1
+ li 5,128
+ lvx 20,5,1
+.LafterVMX9:
- /* Restore cr */
- lwz 0,44(1)
- mtcr 0
-
- /* Restore callee-saved registers... */
-
+ /* Restore FP regs */
/* Floating-point regs */
lfd 31,616(1)
lfd 30,608(1)
@@ -497,7 +352,7 @@
lfd 15,488(1)
lfd 14,480(1)
- /* General regs */
+ /* restore int regs, including importantly r3 (two_words) */
ld 31,472(1)
ld 30,464(1)
ld 29,456(1)
@@ -517,43 +372,12 @@
ld 15,344(1)
ld 14,336(1)
ld 13,328(1)
+ ld 3,104(1)
+ /* Stash return values */
+ std 6,0(3)
+ std 7,8(3)
- /* r11 already holds VG_(machine_ppc64_has_VMX) value */
- cmpldi 11,0
- beq .LafterVMX9
-
- /* VRSAVE */
- lwz 4,324(1)
- mfspr 4,256 /* VRSAVE reg is spr number 256 */
-
- /* Vector regs */
- li 4,304
- lvx 31,4,1
- li 4,288
- lvx 30,4,1
- li 4,272
- lvx 29,4,1
- li 4,256
- lvx 28,4,1
- li 4,240
- lvx 27,4,1
- li 4,224
- lvx 26,4,1
- li 4,208
- lvx 25,4,1
- li 4,192
- lvx 24,4,1
- li 4,176
- lvx 23,4,1
- li 4,160
- lvx 22,4,1
- li 4,144
- lvx 21,4,1
- li 4,128
- lvx 20,4,1
-.LafterVMX9:
-
- /* reset cr, lr, sp */
+ /* restore lr & sp, and leave */
ld 0,632(1) /* stack_size + 8 */
mtcr 0
ld 0,640(1) /* stack_size + 16 */
@@ -562,94 +386,146 @@
blr
-/*------------------------------------------------------------*/
-/*--- ---*/
-/*--- A special dispatcher, for running no-redir ---*/
-/*--- translations. Just runs the given translation once. ---*/
-/*--- ---*/
-/*------------------------------------------------------------*/
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
-/* signature:
-void VG_(run_a_noredir_translation) ( UWord* argblock );
-*/
+/* ------ Chain me to slow entry point ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_chain_me_to_slowEP)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_chain_me_to_slowEP):
+ .quad .VG_(disp_cp_chain_me_to_slowEP),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_chain_me_to_slowEP),@function
+ .globl .VG_(disp_cp_chain_me_to_slowEP)
+.VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li 6, VG_TRC_CHAIN_ME_TO_SLOW_EP
+ mflr 7
+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_slowEP
+ 4 = mtctr r30
+ 4 = btctr
+ */
+ subi 7,7,20+4+4
+ b .postamble
-/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
- and 2 to carry results:
- 0: input: ptr to translation
- 1: input: ptr to guest state
- 2: output: next guest PC
- 3: output: guest state pointer afterwards (== thread return code)
-*/
+/* ------ Chain me to fast entry point ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_chain_me_to_fastEP)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_chain_me_to_fastEP):
+ .quad .VG_(disp_cp_chain_me_to_fastEP),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_chain_me_to_fastEP),@function
+ .globl .VG_(disp_cp_chain_me_to_fastEP)
+.VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ li 6, VG_TRC_CHAIN_ME_TO_FAST_EP
+ mflr 7
+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_fastEP
+ 4 = mtctr r30
+ 4 = btctr
+ */
+ subi 7,7,20+4+4
+ b .postamble
+
+/* ------ Indirect but boring jump ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_xindir)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_xindir):
+ .quad .VG_(disp_cp_xindir),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_xindir),@function
+ .globl .VG_(disp_cp_xindir)
+.VG_(disp_cp_xindir):
+ /* Where are we going? */
+ ld 3,OFFSET_ppc64_CIA(31)
+
+ /* stats only */
+ ld 5, .tocent__vgPlain_stats__n_xindirs_32@toc(2)
+ lwz 6,0(5)
+ addi 6,6,1
+ stw 6,0(5)
+
+ /* r5 = &VG_(tt_fast) */
+ ld 5, .tocent__vgPlain_tt_fast@toc(2) /* &VG_(tt_fast) */
+
+ /* try a fast lookup in the translation cache */
+ /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
+ = ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */
+ rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */
+ sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */
+ add 5,5,4 /* & VG_(tt_fast)[entry#] */
+ ld 6,0(5) /* .guest */
+ ld 7,8(5) /* .host */
+ cmpd 3,6
+ bne .fast_lookup_failed
+
+ /* Found a match. Jump to .host. */
+ mtctr 7
+ bctr
+
+.fast_lookup_failed:
+ /* stats only */
+ ld 5, .tocent__vgPlain_stats__n_xindir_misses_32@toc(2)
+ lwz 6,0(5)
+ addi 6,6,1
+ stw 6,0(5)
+
+ li 6,VG_TRC_INNER_FASTMISS
+ li 7,0
+ b .postamble
+ /*NOTREACHED*/
+
+/* ------ Assisted jump ------ */
.section ".text"
-.align 2
-.globl VG_(run_a_noredir_translation)
-.section ".opd","aw"
-.align 3
-VG_(run_a_noredir_translation):
-.quad .VG_(run_a_noredir_translation),.TOC.@tocbase,0
-.previous
-.type .VG_(run_a_noredir_translation),@function
-.globl .VG_(run_a_noredir_translation)
-.VG_(run_a_noredir_translation):
- /* save callee-save int regs, & lr */
- stdu 1,-512(1)
- std 14,256(1)
- std 15,264(1)
- std 16,272(1)
- std 17,280(1)
- std 18,288(1)
- std 19,296(1)
- std 20,304(1)
- std 21,312(1)
- std 22,320(1)
- std 23,328(1)
- std 24,336(1)
- std 25,344(1)
- std 26,352(1)
- std 27,360(1)
- std 28,368(1)
- std 29,376(1)
- std 30,384(1)
- std 31,392(1)
- mflr 31
- std 31,400(1)
- std 2,408(1) /* also preserve R2, just in case .. */
+ .align 2
+ .globl VG_(disp_cp_xassisted)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_xassisted):
+ .quad .VG_(disp_cp_xassisted),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_xassisted),@function
+ .globl .VG_(disp_cp_xassisted)
+.VG_(disp_cp_xassisted):
+ /* r31 contains the TRC */
+ mr 6,31
+ li 7,0
+ b .postamble
- std 3,416(1)
- ld 31,8(3)
- ld 30,0(3)
- mtlr 30
- blrl
+/* ------ Event check failed ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_evcheck_fail)
+ .section ".opd","aw"
+ .align 3
+VG_(disp_cp_evcheck_fail):
+ .quad .VG_(disp_cp_evcheck_fail),.TOC.@tocbase,0
+ .previous
+ .type .VG_(disp_cp_evcheck_fail),@function
+ .globl .VG_(disp_cp_evcheck_fail)
+.VG_(disp_cp_evcheck_fail):
+ li 6,VG_TRC_INNER_COUNTERZERO
+ li 7,0
+ b .postamble
- ld 4,416(1)
- std 3, 16(4)
- std 31,24(4)
-
- ld 14,256(1)
- ld 15,264(1)
- ld 16,272(1)
- ld 17,280(1)
- ld 18,288(1)
- ld 19,296(1)
- ld 20,304(1)
- ld 21,312(1)
- ld 22,320(1)
- ld 23,328(1)
- ld 24,336(1)
- ld 25,344(1)
- ld 26,352(1)
- ld 27,360(1)
- ld 28,368(1)
- ld 29,376(1)
- ld 30,384(1)
- ld 31,400(1)
- mtlr 31
- ld 31,392(1)
- ld 2,408(1) /* also preserve R2, just in case .. */
-
- addi 1,1,512
- blr
-
+
+.size .VG_(disp_run_translations), .-.VG_(disp_run_translations)
/* Let the linker know we don't need an executable stack */
.section .note.GNU-stack,"",@progbits
diff --git a/main/coregrind/m_dispatch/dispatch-s390x-linux.S b/main/coregrind/m_dispatch/dispatch-s390x-linux.S
index 97c4d93..c63115d 100644
--- a/main/coregrind/m_dispatch/dispatch-s390x-linux.S
+++ b/main/coregrind/m_dispatch/dispatch-s390x-linux.S
@@ -8,8 +8,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
-
+ Copyright IBM Corp. 2010-2012
+ Copyright (C) 2011-2012, Florian Krohm (britzel@acm.org)
+
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2 of the
@@ -40,8 +41,9 @@
/*------------------------------------------------------------*/
/*--- ---*/
-/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
-/*--- run all translations except no-redir ones. ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
/*--- ---*/
/*------------------------------------------------------------*/
@@ -55,106 +57,154 @@
/* Location of valgrind's saved FPC register */
#define S390_LOC_SAVED_FPC_V S390_OFFSET_SAVED_FPC_V(SP)
-/* Location of saved guest state pointer */
-#define S390_LOC_SAVED_GSP S390_OFFSET_SAVED_GSP(SP)
-
/* Location of saved R2 register */
#define S390_LOC_SAVED_R2 S390_OFFSET_SAVED_R2(SP)
+
/*----------------------------------------------------*/
-/*--- Preamble (set everything up) ---*/
+/*--- Entry and preamble (set everything up) ---*/
/*----------------------------------------------------*/
/* signature:
-UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
-*/
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
-.text
-.align 4
-.globl VG_(run_innerloop)
-VG_(run_innerloop):
- /* r2 holds address of guest_state */
- /* r3 holds do_profiling (a flag) */
+ Return results are placed in two_words:
+
+ two_words[0] is set to the TRC
+ two_words[1] is set to the address to patch (in case two_words[0] is
+ VG_TRC_CHAIN_ME_TO_{SLOW,FAST}_EP). Otherwise, it is 0.
+*/
+ .text
+ .align 4
+ .globl VG_(disp_run_translations)
+ .type VG_(disp_run_translations), @function
+VG_(disp_run_translations):
+
+ /* r2 holds two_words */
+ /* r3 holds pointer to guest_state */
+ /* r4 holds host_addr, i.e. the address of the translation to run */
/* Save gprs ABI: r6...r13 and r15 */
- stmg %r6,%r15,48(SP)
+ stmg %r6,%r15,48(SP)
/* New stack frame */
- aghi SP,-S390_INNERLOOP_FRAME_SIZE
+ aghi SP,-S390_INNERLOOP_FRAME_SIZE
/* Save fprs: ABI: f8...f15 */
- std %f8,160+0(SP)
- std %f9,160+8(SP)
- std %f10,160+16(SP)
- std %f11,160+24(SP)
- std %f12,160+32(SP)
- std %f13,160+40(SP)
- std %f14,160+48(SP)
- std %f15,160+56(SP)
+ std %f8,160+0(SP)
+ std %f9,160+8(SP)
+ std %f10,160+16(SP)
+ std %f11,160+24(SP)
+ std %f12,160+32(SP)
+ std %f13,160+40(SP)
+ std %f14,160+48(SP)
+ std %f15,160+56(SP)
/* Load address of guest state into guest state register (r13) */
- lgr %r13,%r2
+ lgr %r13,%r3
- /* Store address of guest state pointer on stack.
- It will be needed later because upon return from a VEX translation
- r13 may contain a special value. So the old value will be used to
- determine whether r13 contains a special value. */
- stg %r13,S390_LOC_SAVED_GSP
-
- /* Save valgrind's FPC on stack so run_innerloop_exit can restore
+ /* Save R2 on stack. In postamble it will be restored such that the
+ return values can be written */
+ stg %r2,S390_LOC_SAVED_R2
+
+ /* Save valgrind's FPC on stack so postamble can restore
it later . */
stfpc S390_LOC_SAVED_FPC_V
/* Load the FPC the way the client code wants it. I.e. pull the
- value from the guest state.
- lfpc OFFSET_s390x_fpc(%r13)
+ value from the guest state. */
+ lfpc OFFSET_s390x_fpc(%r13)
- /* Get the IA from the guest state */
- lg %r2,OFFSET_s390x_IA(%r13)
+ /* Jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ br %r4
- /* Get VG_(dispatch_ctr) -- a 32-bit value -- and store it in a reg */
- larl %r6,VG_(dispatch_ctr)
- l S390_REGNO_DISPATCH_CTR,0(%r6)
-
- /* Fall into main loop (the right one) */
-
- /* r3 = 1 --> do_profiling. We may trash r3 later on. That's OK,
- because it's a volatile register (does not need to be preserved). */
- ltgr %r3,%r3
- je run_innerloop__dispatch_unprofiled
- j run_innerloop__dispatch_profiled
/*----------------------------------------------------*/
-/*--- NO-PROFILING (standard) dispatcher ---*/
+/*--- Postamble and return to C code. ---*/
/*----------------------------------------------------*/
-run_innerloop__dispatch_unprofiled:
- /* Load the link register with the address the jitted code will
- return to when it's done executing. The link register is loaded
- exactly once per loop. This is safe, because the jitted code
- cannot possibly modify the LR. How else would it be able to return
- to the location in the LR otherwise? */
- basr LR,0
+postamble:
+ /* At this point, %r0 and %r1 contain two
+ words to be returned to the caller. %r0
+ holds a TRC value, and %r1 optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
- /* Loop begins here */
+ /* We're leaving. AMD has some code here to check invariants.
+ We don't have (need) that, as we save and restore the FPC register
+ whenever we switch between valgrind proper to client code. */
+
+ /* Restore valgrind's FPC, as client code may have changed it. */
+ lfpc S390_LOC_SAVED_FPC_V
+
+ /* Restore %r2 from stack; holds address of two_words */
+ lg %r2,S390_LOC_SAVED_R2
+
+ stg %r0,0(%r2) /* Store %r0 to two_words[0] */
+ stg %r1,8(%r2) /* Store %r1 to two_words[1] */
- /* This is the story:
+ /* Restore callee-saved registers... */
- r2 = IA = next guest address
- r12 = VG_(dispatch_ctr)
- r13 = guest state pointer or (upon return from guest code) some
- special value
- r15 = stack pointer (as usual)
- */
-innermost_loop:
- /* Has the guest state pointer been messed with? If yes, exit.
- The mess is recognised by r13 containing an odd value. */
- tmll %r13,1
- jne gsp_changed
+ /* Floating-point regs */
+ ld %f8,160+0(SP)
+ ld %f9,160+8(SP)
+ ld %f10,160+16(SP)
+ ld %f11,160+24(SP)
+ ld %f12,160+32(SP)
+ ld %f13,160+40(SP)
+ ld %f14,160+48(SP)
+ ld %f15,160+56(SP)
- /* Save the jump address in the guest state */
- stg %r2,OFFSET_s390x_IA(%r13)
+ /* Remove stack frame */
+ aghi SP,S390_INNERLOOP_FRAME_SIZE
+ /* General-purpose regs. This also restores the original link
+ register (r14) and stack pointer (r15). */
+ lmg %r6,%r15,48(SP)
+
+ /* Return */
+ br LR
+
+
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
+
+/* ------ Chain me to slow entry point ------ */
+ .global VG_(disp_cp_chain_me_to_slowEP)
+VG_(disp_cp_chain_me_to_slowEP):
+ /* When we come here %r1 contains the address of the place to patch.
+ The return values (TRC, address-to-patch) are stored here in
+ %r0 and %r1, respectively */
+ lghi %r0,VG_TRC_CHAIN_ME_TO_SLOW_EP
+ j postamble
+
+
+/* ------ Chain me to fast entry point ------ */
+ .global VG_(disp_cp_chain_me_to_fastEP)
+VG_(disp_cp_chain_me_to_fastEP):
+ /* Identical to VG_(disp_cp_chain_me_to_slowEP), except value of %r0. */
+ lghi %r0,VG_TRC_CHAIN_ME_TO_FAST_EP
+ j postamble
+
+
+/* ------ Indirect but boring jump ------ */
+ .global VG_(disp_cp_xindir)
+VG_(disp_cp_xindir):
+ /* Where are we going? */
+ lg %r2, OFFSET_s390x_IA(%r13)
+
+ /* Increment VG_(stats__n_xindirs_32) */
+ larl %r8, VG_(stats__n_xindirs_32)
+ l %r10,0(%r8)
+ ahi %r10,1
+ st %r10,0(%r8)
/* Try a fast lookup in the translation cache:
Compute offset (not index) into VT_(tt_fast):
@@ -168,204 +218,57 @@
which is
offset = ((addr & (VG_TT_FAST_MASK << 1) ) << 3
*/
- larl %r8, VG_(tt_fast)
- llill %r5,( VG_TT_FAST_MASK << 1) & 0xffff
+ larl %r8, VG_(tt_fast)
+ llill %r5,(VG_TT_FAST_MASK << 1) & 0xffff
#if ((( VG_TT_FAST_MASK << 1) & 0xffff0000) >> 16 != 0)
- iilh %r5,(( VG_TT_FAST_MASK << 1) & 0xffff0000) >> 16
+ iilh %r5,((VG_TT_FAST_MASK << 1) & 0xffff0000) >> 16
#endif
- ngr %r5,%r2
- sllg %r7,%r5,3
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- ahi S390_REGNO_DISPATCH_CTR,-1
- jz counter_is_zero
-
- lg %r11, 8(%r8,%r7) /* .host */
- cg %r2, 0(%r8,%r7) /* next guest address == .guest ? */
- jne fast_lookup_failed
-
+ ngr %r5,%r2
+ sllg %r7,%r5,3
+ lg %r11, 8(%r8,%r7) /* .host */
+ cg %r2, 0(%r8,%r7) /* next guest address == .guest ? */
+ jne fast_lookup_failed
+
/* Found a match. Call .host.
r11 is an address. There we will find the instrumented client code.
- That code may modify the guest state register r13. The client code
- will return to the beginning of this loop start by issuing br LR.
- We can simply branch to the host code */
- br %r11
-
-
-/*----------------------------------------------------*/
-/*--- PROFILING dispatcher (can be much slower) ---*/
-/*----------------------------------------------------*/
-
-run_innerloop__dispatch_profiled:
- stg %r2,S390_LOC_SAVED_R2
-
- /* Load the link register with the address the jitted code will
- return to when it's done executing. */
- bras LR,innermost_loop
-
- /* Jitted code returns here. Update profile counter for previous IA */
-
- llill %r5,( VG_TT_FAST_MASK << 1) & 0xffff
-#if ((( VG_TT_FAST_MASK << 1) & 0xffff0000) >> 16 != 0)
- iilh %r5,(( VG_TT_FAST_MASK << 1) & 0xffff0000) >> 16
-#endif
- ng %r5,S390_LOC_SAVED_R2
- sllg %r7,%r5,2
-
- /* Increment bb profile counter */
- larl %r8, VG_(tt_fastN)
- lg %r9,0(%r8,%r7)
- l %r10,0(%r9)
- ahi %r10,1
- st %r10,0(%r9)
-
- j run_innerloop__dispatch_profiled
-
-/*----------------------------------------------------*/
-/*--- exit points ---*/
-/*----------------------------------------------------*/
-
-gsp_changed:
- /* Someone messed with the gsp (in r13). Have to
- defer to scheduler to resolve this. The register
- holding VG_(dispatch_ctr) is not yet decremented,
- so no need to increment. */
-
- /* Update the IA in the guest state */
- lg %r6,S390_LOC_SAVED_GSP /* r6 = original guest state pointer */
- stg %r2,OFFSET_s390x_IA(%r6)
-
- /* Return the special guest state pointer value */
- lgr %r2, %r13
- j run_innerloop_exit
-
-
-counter_is_zero:
- /* IA is up to date */
-
- /* Back out decrement of the dispatch counter */
- ahi S390_REGNO_DISPATCH_CTR,1
-
- /* Set return value for the scheduler */
- lghi %r2,VG_TRC_INNER_COUNTERZERO
- j run_innerloop_exit
-
+ That code may modify the guest state register r13. */
+ br %r11
+ .long 0x0 /* persuade insn decoders not to speculate past here */
fast_lookup_failed:
- /* IA is up to date */
+ /* Increment VG_(stats__n_xindir_misses_32) */
+ larl %r8, VG_(stats__n_xindir_misses_32)
+ l %r10,0(%r8)
+ ahi %r10,1
+ st %r10,0(%r8)
- /* Back out decrement of the dispatch counter */
- ahi S390_REGNO_DISPATCH_CTR,1
+ lghi %r0,VG_TRC_INNER_FASTMISS
+ lghi %r1,0
+ j postamble
- /* Set return value for the scheduler */
- lghi %r2,VG_TRC_INNER_FASTMISS
- j run_innerloop_exit
+
+/* ------ Assisted jump ------ */
+ .global VG_(disp_cp_xassisted)
+VG_(disp_cp_xassisted):
+ /* guest-state-pointer contains the TRC. Put the value into the
+ return register */
+ lgr %r0,%r13
+ lghi %r1,0
+ j postamble
- /* All exits from the dispatcher go through here.
- When we come here r2 holds the return value. */
-run_innerloop_exit:
+/* ------ Event check failed ------ */
+ .global VG_(disp_cp_evcheck_fail)
+VG_(disp_cp_evcheck_fail):
+ lghi %r0,VG_TRC_INNER_COUNTERZERO
+ lghi %r1,0
+ j postamble
- /* Restore valgrind's FPC, as client code may have changed it. */
- lfpc S390_LOC_SAVED_FPC_V
- /* Write ctr to VG_(dispatch_ctr) (=32bit value) */
- larl %r6,VG_(dispatch_ctr)
- st S390_REGNO_DISPATCH_CTR,0(%r6)
-
- /* Restore callee-saved registers... */
-
- /* Floating-point regs */
- ld %f8,160+0(SP)
- ld %f9,160+8(SP)
- ld %f10,160+16(SP)
- ld %f11,160+24(SP)
- ld %f12,160+32(SP)
- ld %f13,160+40(SP)
- ld %f14,160+48(SP)
- ld %f15,160+56(SP)
-
- /* Remove atack frame */
- aghi SP,S390_INNERLOOP_FRAME_SIZE
-
- /* General-purpose regs. This also restores the original link
- register (r14) and stack pointer (r15). */
- lmg %r6,%r15,48(SP)
-
- /* Return */
- br LR
-
-/*------------------------------------------------------------*/
-/*--- ---*/
-/*--- A special dispatcher, for running no-redir ---*/
-/*--- translations. Just runs the given translation once. ---*/
-/*--- ---*/
-/*------------------------------------------------------------*/
-
-/* signature:
-void VG_(run_a_noredir_translation) ( UWord* argblock );
-*/
-
-/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
- and 2 to carry results:
- 0: input: ptr to translation
- 1: input: ptr to guest state
- 2: output: next guest PC
- 3: output: guest state pointer afterwards (== thread return code)
-*/
-.text
-.align 4
-.globl VG_(run_a_noredir_translation)
-VG_(run_a_noredir_translation):
- stmg %r6,%r15,48(SP)
- aghi SP,-S390_INNERLOOP_FRAME_SIZE
- std %f8,160+0(SP)
- std %f9,160+8(SP)
- std %f10,160+16(SP)
- std %f11,160+24(SP)
- std %f12,160+32(SP)
- std %f13,160+40(SP)
- std %f14,160+48(SP)
- std %f15,160+56(SP)
-
- /* Load address of guest state into guest state register (r13) */
- lg %r13,8(%r2)
-
- /* Get the IA */
- lg %r11,0(%r2)
-
- /* save r2 (argblock) as it is clobbered */
- stg %r2,160+64(SP)
-
- /* the call itself */
- basr LR,%r11
-
- /* restore argblock */
- lg %r1,160+64(SP)
- /* save the next guest PC */
- stg %r2,16(%r1)
-
- /* save the guest state */
- stg %r13,24(%r1)
-
- /* Restore Floating-point regs */
- ld %f8,160+0(SP)
- ld %f9,160+8(SP)
- ld %f10,160+16(SP)
- ld %f11,160+24(SP)
- ld %f12,160+32(SP)
- ld %f13,160+40(SP)
- ld %f14,160+48(SP)
- ld %f15,160+56(SP)
-
- aghi SP,S390_INNERLOOP_FRAME_SIZE
-
- lmg %r6,%r15,48(SP)
- br %r14
-
+ .size VG_(disp_run_translations), .-VG_(disp_run_translations)
/* Let the linker know we don't need an executable stack */
-.section .note.GNU-stack,"",@progbits
+ .section .note.GNU-stack,"",@progbits
#endif /* VGA_s390x */
diff --git a/main/coregrind/m_dispatch/dispatch-x86-darwin.S b/main/coregrind/m_dispatch/dispatch-x86-darwin.S
index 1b216b3..a54b732 100644
--- a/main/coregrind/m_dispatch/dispatch-x86-darwin.S
+++ b/main/coregrind/m_dispatch/dispatch-x86-darwin.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -37,45 +37,35 @@
#include "libvex_guest_offsets.h" /* for OFFSET_x86_EIP */
-/* Global variables */
-/* These are defined here instead of in their respective C files to
- avoid extra PIC branch code here. */
-.data
-.align 2
-
-/* m_transtab.c */
-.globl VG_(tt_fast)
-.align 4
-VG_(tt_fast): .space VG_TT_FAST_SIZE*8, 0 /* (2*Addr) [VG_TT_FAST_SIZE] */
-.globl VG_(tt_fastN)
-VG_(tt_fastN): .space VG_TT_FAST_SIZE*4, 0 /* (UInt *) [VG_TT_FAST_SIZE] */
-
-/* scheduler.c */
-.globl VG_(dispatch_ctr)
-VG_(dispatch_ctr): .long 0
-
-
/*------------------------------------------------------------*/
/*--- ---*/
-/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
-/*--- run all translations except no-redir ones. ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
/*--- ---*/
/*------------------------------------------------------------*/
/*----------------------------------------------------*/
-/*--- Preamble (set everything up) ---*/
+/*--- Entry and preamble (set everything up) ---*/
/*----------------------------------------------------*/
/* signature:
-UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
*/
.text
-.globl VG_(run_innerloop)
-VG_(run_innerloop):
- /* 4(%esp) holds guest_state */
- /* 8(%esp) holds do_profiling */
-
- /* ----- entry point to VG_(run_innerloop) ----- */
+.globl VG_(disp_run_translations)
+VG_(disp_run_translations):
+ /* 0(%esp) holds our return address. */
+ /* 4(%esp) holds two_words */
+ /* 8(%esp) holds guest_state */
+ /* 12(%esp) holds host_addr */
+
+ /* The preamble */
+
+ /* Save integer registers, since this is a pseudo-function. */
+ pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
@@ -83,14 +73,11 @@
pushl %edi
pushl %ebp
- /* 28(%esp) holds guest_state */
- /* 32(%esp) holds do_profiling */
+ /* 28+4(%esp) holds two_words */
+ /* 28+8(%esp) holds guest_state */
+ /* 28+12(%esp) holds host_addr */
- /* Set up the guest state pointer */
- movl 28(%esp), %ebp
-
- /* fetch %EIP into %eax */
- movl OFFSET_x86_EIP(%ebp), %eax
+ /* Get the host CPU in the state expected by generated code. */
/* set host FPU control word to the default mode expected
by VEX-generated code. See comments in libvex.h for
@@ -110,140 +97,32 @@
L1:
/* set dir flag to known value */
cld
-
- /* fall into main loop (the right one) */
- cmpl $0, 32(%esp) /* do_profiling */
- je VG_(run_innerloop__dispatch_unassisted_unprofiled)
- jmp VG_(run_innerloop__dispatch_unassisted_profiled)
+
+ /* Set up the guest state pointer */
+ movl 28+8(%esp), %ebp
+
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ jmpl *28+12(%esp)
/*NOTREACHED*/
/*----------------------------------------------------*/
-/*--- NO-PROFILING (standard) dispatcher ---*/
+/*--- Postamble and exit. ---*/
/*----------------------------------------------------*/
-.globl VG_(run_innerloop__dispatch_unassisted_unprofiled)
-VG_(run_innerloop__dispatch_unassisted_unprofiled):
- /* AT ENTRY: %eax is next guest addr, %ebp is the
- unmodified guest state ptr */
+postamble:
+ /* At this point, %eax and %edx contain two
+ words to be returned to the caller. %eax
+ holds a TRC value, and %edx optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
- /* save the jump address in the guest state */
- movl %eax, OFFSET_x86_EIP(%ebp)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subl $1, VG_(dispatch_ctr)
- jz counter_is_zero
-
- /* try a fast lookup in the translation cache */
- movl %eax, %ebx
- andl $VG_TT_FAST_MASK, %ebx
- movl 0+VG_(tt_fast)(,%ebx,8), %esi /* .guest */
- movl 4+VG_(tt_fast)(,%ebx,8), %edi /* .host */
- cmpl %eax, %esi
- jnz fast_lookup_failed
-
- /* Found a match. Jump to .host. */
- jmp *%edi
- ud2 /* persuade insn decoders not to speculate past here */
- /* generated code should run, then jump back to
- VG_(run_innerloop__dispatch_{un,}assisted_unprofiled). */
- /*NOTREACHED*/
-
-.globl VG_(run_innerloop__dispatch_assisted_unprofiled)
-VG_(run_innerloop__dispatch_assisted_unprofiled):
- /* AT ENTRY: %eax is next guest addr, %ebp is the
- modified guest state ptr */
- jmp gsp_changed
- ud2
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- PROFILING dispatcher (can be much slower) ---*/
-/*----------------------------------------------------*/
-
-.globl VG_(run_innerloop__dispatch_unassisted_profiled)
-VG_(run_innerloop__dispatch_unassisted_profiled):
- /* AT ENTRY: %eax is next guest addr, %ebp is the
- unmodified guest state ptr */
-
- /* save the jump address in the guest state */
- movl %eax, OFFSET_x86_EIP(%ebp)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subl $1, VG_(dispatch_ctr)
- jz counter_is_zero
-
- /* try a fast lookup in the translation cache */
- movl %eax, %ebx
- andl $VG_TT_FAST_MASK, %ebx
- movl 0+VG_(tt_fast)(,%ebx,8), %esi /* .guest */
- movl 4+VG_(tt_fast)(,%ebx,8), %edi /* .host */
- cmpl %eax, %esi
- jnz fast_lookup_failed
- /* increment bb profile counter */
- /* note: innocuous as this sounds, it causes a huge amount more
- stress on D1 and significantly slows everything down. */
- movl VG_(tt_fastN)(,%ebx,4), %edx
- /* Use "addl $1", not "incl", to avoid partial-flags stall on P4 */
- addl $1, (%edx)
-
- /* Found a match. Jump to .host. */
- jmp *%edi
- ud2 /* persuade insn decoders not to speculate past here */
- /* generated code should run, then jump back to
- VG_(run_innerloop__dispatch_{un,}assisted_profiled). */
- /*NOTREACHED*/
-
-.globl VG_(run_innerloop__dispatch_assisted_profiled)
-VG_(run_innerloop__dispatch_assisted_profiled):
- /* AT ENTRY: %eax is next guest addr, %ebp is the
- modified guest state ptr */
- jmp gsp_changed
- ud2
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- exit points ---*/
-/*----------------------------------------------------*/
-
-gsp_changed:
- /* Someone messed with the gsp. Have to
- defer to scheduler to resolve this. dispatch ctr
- is not yet decremented, so no need to increment. */
- /* %EIP is NOT up to date here. First, need to write
- %eax back to %EIP, but without trashing %ebp since
- that holds the value we want to return to the scheduler.
- Hence use %esi transiently for the guest state pointer. */
- movl 28(%esp), %esi
- movl %eax, OFFSET_x86_EIP(%esi)
- movl %ebp, %eax
- jmp run_innerloop_exit
- /*NOTREACHED*/
-
-counter_is_zero:
- /* %EIP is up to date here */
- /* back out decrement of the dispatch counter */
- addl $1, VG_(dispatch_ctr)
- movl $VG_TRC_INNER_COUNTERZERO, %eax
- jmp run_innerloop_exit
- /*NOTREACHED*/
-
-fast_lookup_failed:
- /* %EIP is up to date here */
- /* back out decrement of the dispatch counter */
- addl $1, VG_(dispatch_ctr)
- movl $VG_TRC_INNER_FASTMISS, %eax
- jmp run_innerloop_exit
- /*NOTREACHED*/
-
-
-
-/* All exits from the dispatcher go through here. %eax holds
- the return value.
-*/
-run_innerloop_exit:
- /* We're leaving. Check that nobody messed with
- %mxcsr or %fpucw. We can't mess with %eax here as it
- holds the tentative return value, but any other is OK. */
+ /* We're leaving. Check that nobody messed with %mxcsr
+ or %fpucw. We can't mess with %eax or %edx here as they
+ holds the tentative return value, but any others are OK. */
#if !defined(ENABLE_INNER)
/* This check fails for self-hosting, so skip in that case */
pushl $0
@@ -252,7 +131,7 @@
popl %esi /* get rid of the word without trashing %eflags */
jnz invariant_violation
#endif
- cmpl $0, VG_(machine_x86_have_mxcsr)
+# cmpl $0, VG_(machine_x86_have_mxcsr)
jz L2
pushl $0
stmxcsr (%esp)
@@ -261,69 +140,105 @@
popl %esi
jnz invariant_violation
L2: /* otherwise we're OK */
- jmp run_innerloop_exit_REALLY
-
+ jmp remove_frame
invariant_violation:
movl $VG_TRC_INVARIANT_FAILED, %eax
- jmp run_innerloop_exit_REALLY
+ movl $0, %edx
-run_innerloop_exit_REALLY:
+remove_frame:
+ /* Stash return values */
+ movl 28+4(%esp), %edi /* two_words */
+ movl %eax, 0(%edi)
+ movl %edx, 4(%edi)
+ /* Restore int regs and return. */
popl %ebp
popl %edi
popl %esi
popl %edx
popl %ecx
popl %ebx
+ popl %eax
ret
+
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
+/* ------ Chain me to slow entry point ------ */
+.globl VG_(disp_cp_chain_me_to_slowEP)
+VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ movl $VG_TRC_CHAIN_ME_TO_SLOW_EP, %eax
+ popl %edx
+ /* 5 = movl $VG_(disp_chain_me_to_slowEP), %edx;
+ 2 = call *%edx */
+ subl $5+2, %edx
+ jmp postamble
-/*------------------------------------------------------------*/
-/*--- ---*/
-/*--- A special dispatcher, for running no-redir ---*/
-/*--- translations. Just runs the given translation once. ---*/
-/*--- ---*/
-/*------------------------------------------------------------*/
+/* ------ Chain me to fast entry point ------ */
+.globl VG_(disp_cp_chain_me_to_fastEP)
+VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_F, RA) */
+ movl $VG_TRC_CHAIN_ME_TO_FAST_EP, %eax
+ popl %edx
+ /* 5 = movl $VG_(disp_chain_me_to_fastEP), %edx;
+ 2 = call *%edx */
+ subl $5+2, %edx
+ jmp postamble
-/* signature:
-void VG_(run_a_noredir_translation) ( UWord* argblock );
-*/
+/* ------ Indirect but boring jump ------ */
+.globl VG_(disp_cp_xindir)
+VG_(disp_cp_xindir):
+ /* Where are we going? */
+ movl OFFSET_x86_EIP(%ebp), %eax
-/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
- and 2 to carry results:
- 0: input: ptr to translation
- 1: input: ptr to guest state
- 2: output: next guest PC
- 3: output: guest state pointer afterwards (== thread return code)
-*/
-.globl VG_(run_a_noredir_translation)
-VG_(run_a_noredir_translation):
- /* Save callee-saves regs */
- pushl %esi
- pushl %edi
- pushl %ebp
- pushl %ebx
+ /* stats only */
+ addl $1, VG_(stats__n_xindirs_32)
+
+ /* try a fast lookup in the translation cache */
+ movl %eax, %ebx /* next guest addr */
+ andl $VG_TT_FAST_MASK, %ebx /* entry# */
+ movl 0+VG_(tt_fast)(,%ebx,8), %esi /* .guest */
+ movl 4+VG_(tt_fast)(,%ebx,8), %edi /* .host */
+ cmpl %eax, %esi
+ jnz fast_lookup_failed
- movl 20(%esp), %edi /* %edi = argblock */
- movl 4(%edi), %ebp /* argblock[1] */
- jmp *0(%edi) /* argblock[0] */
- /*NOTREACHED*/
- ud2
- /* If the translation has been correctly constructed, we
- should resume at the the following label. */
-.globl VG_(run_a_noredir_translation__return_point)
-VG_(run_a_noredir_translation__return_point):
- movl 20(%esp), %edi
- movl %eax, 8(%edi) /* argblock[2] */
- movl %ebp, 12(%edi) /* argblock[3] */
+ /* Found a match. Jump to .host. */
+ jmp *%edi
+ ud2 /* persuade insn decoders not to speculate past here */
- popl %ebx
- popl %ebp
- popl %edi
- popl %esi
- ret
+fast_lookup_failed:
+ /* stats only */
+ addl $1, VG_(stats__n_xindir_misses_32)
+
+ movl $VG_TRC_INNER_FASTMISS, %eax
+ movl $0, %edx
+ jmp postamble
+
+/* ------ Assisted jump ------ */
+.globl VG_(disp_cp_xassisted)
+VG_(disp_cp_xassisted):
+ /* %ebp contains the TRC */
+ movl %ebp, %eax
+ movl $0, %edx
+ jmp postamble
+
+/* ------ Event check failed ------ */
+.globl VG_(disp_cp_evcheck_fail)
+VG_(disp_cp_evcheck_fail):
+ movl $VG_TRC_INNER_COUNTERZERO, %eax
+ movl $0, %edx
+ jmp postamble
+
#endif // defined(VGP_x86_darwin)
-
+
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_dispatch/dispatch-x86-linux.S b/main/coregrind/m_dispatch/dispatch-x86-linux.S
index 3e13ba6..a79ab4a 100644
--- a/main/coregrind/m_dispatch/dispatch-x86-linux.S
+++ b/main/coregrind/m_dispatch/dispatch-x86-linux.S
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -39,26 +39,34 @@
/*------------------------------------------------------------*/
/*--- ---*/
-/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
-/*--- run all translations except no-redir ones. ---*/
+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
+/*--- used to run all translations, ---*/
+/*--- including no-redir ones. ---*/
/*--- ---*/
/*------------------------------------------------------------*/
/*----------------------------------------------------*/
-/*--- Preamble (set everything up) ---*/
+/*--- Entry and preamble (set everything up) ---*/
/*----------------------------------------------------*/
/* signature:
-UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
+void VG_(disp_run_translations)( UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
*/
.text
-.globl VG_(run_innerloop)
-.type VG_(run_innerloop), @function
-VG_(run_innerloop):
- /* 4(%esp) holds guest_state */
- /* 8(%esp) holds do_profiling */
-
- /* ----- entry point to VG_(run_innerloop) ----- */
+.globl VG_(disp_run_translations)
+.type VG_(disp_run_translations), @function
+VG_(disp_run_translations):
+ /* 0(%esp) holds our return address. */
+ /* 4(%esp) holds two_words */
+ /* 8(%esp) holds guest_state */
+ /* 12(%esp) holds host_addr */
+
+ /* The preamble */
+
+ /* Save integer registers, since this is a pseudo-function. */
+ pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
@@ -66,14 +74,11 @@
pushl %edi
pushl %ebp
- /* 28(%esp) holds guest_state */
- /* 32(%esp) holds do_profiling */
+ /* 28+4(%esp) holds two_words */
+ /* 28+8(%esp) holds guest_state */
+ /* 28+12(%esp) holds host_addr */
- /* Set up the guest state pointer */
- movl 28(%esp), %ebp
-
- /* fetch %EIP into %eax */
- movl OFFSET_x86_EIP(%ebp), %eax
+ /* Get the host CPU in the state expected by generated code. */
/* set host FPU control word to the default mode expected
by VEX-generated code. See comments in libvex.h for
@@ -93,151 +98,32 @@
L1:
/* set dir flag to known value */
cld
-
- /* fall into main loop (the right one) */
- cmpl $0, 32(%esp) /* do_profiling */
- je VG_(run_innerloop__dispatch_unassisted_unprofiled)
- jmp VG_(run_innerloop__dispatch_unassisted_profiled)
+
+ /* Set up the guest state pointer */
+ movl 28+8(%esp), %ebp
+
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+ continue. When that happens, the translation in question
+ will jump (or call) to one of the continuation points
+ VG_(cp_...) below. */
+ jmpl *28+12(%esp)
/*NOTREACHED*/
/*----------------------------------------------------*/
-/*--- NO-PROFILING (standard) dispatcher ---*/
+/*--- Postamble and exit. ---*/
/*----------------------------------------------------*/
-.align 16
-.global VG_(run_innerloop__dispatch_unassisted_unprofiled)
-VG_(run_innerloop__dispatch_unassisted_unprofiled):
- /* AT ENTRY: %eax is next guest addr, %ebp is the
- unmodified guest state ptr */
+postamble:
+ /* At this point, %eax and %edx contain two
+ words to be returned to the caller. %eax
+ holds a TRC value, and %edx optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
- /* save the jump address in the guest state */
- movl %eax, OFFSET_x86_EIP(%ebp)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subl $1, VG_(dispatch_ctr)
- jz counter_is_zero
-
- /* try a fast lookup in the translation cache */
- movl %eax, %ebx /* next guest addr */
- andl $ VG_TT_FAST_MASK, %ebx /* entry# */
- movl 0+VG_(tt_fast)(,%ebx,8), %esi /* .guest */
- movl 4+VG_(tt_fast)(,%ebx,8), %edi /* .host */
- cmpl %eax, %esi
- jnz fast_lookup_failed
-
- /* Found a match. Jump to .host. */
- jmp *%edi
- ud2 /* persuade insn decoders not to speculate past here */
- /* generated code should run, then jump back to either
- VG_(run_innerloop__dispatch_unassisted_unprofiled) or
- VG_(run_innerloop__dispatch_assisted_unprofiled). */
- /*NOTREACHED*/
-
-.align 16
-.global VG_(run_innerloop__dispatch_assisted_unprofiled)
-VG_(run_innerloop__dispatch_assisted_unprofiled):
- /* AT ENTRY: %eax is next guest addr, %ebp is the
- modified guest state ptr */
- /* We know the guest state pointer has been modified.
- So jump directly to gsp_changed. */
- jmp gsp_changed
- ud2
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- PROFILING dispatcher (can be much slower) ---*/
-/*----------------------------------------------------*/
-
-.align 16
-.global VG_(run_innerloop__dispatch_unassisted_profiled)
-VG_(run_innerloop__dispatch_unassisted_profiled):
- /* AT ENTRY: %eax is next guest addr, %ebp is the
- unmodified guest state ptr */
-
- /* save the jump address in the guest state */
- movl %eax, OFFSET_x86_EIP(%ebp)
-
- /* Are we out of timeslice? If yes, defer to scheduler. */
- subl $1, VG_(dispatch_ctr)
- jz counter_is_zero
-
- /* try a fast lookup in the translation cache */
- movl %eax, %ebx /* next guest addr */
- andl $ VG_TT_FAST_MASK, %ebx /* entry# */
- movl 0+VG_(tt_fast)(,%ebx,8), %esi /* .guest */
- movl 4+VG_(tt_fast)(,%ebx,8), %edi /* .host */
- cmpl %eax, %esi
- jnz fast_lookup_failed
-
- /* increment bb profile counter */
- /* note: innocuous as this sounds, it causes a huge amount more
- stress on D1 and significantly slows everything down. */
- movl VG_(tt_fastN)(,%ebx,4), %edx
- /* Use "addl $1", not "incl", to avoid partial-flags stall on P4 */
- addl $1, (%edx)
-
- /* Found a match. Jump to .host. */
- jmp *%edi
- ud2 /* persuade insn decoders not to speculate past here */
- /* generated code should run, then jump back to either
- VG_(run_innerloop__dispatch_unassisted_profiled) or
- VG_(run_innerloop__dispatch_assisted_profiled). */
- /*NOTREACHED*/
-
-.align 16
-.global VG_(run_innerloop__dispatch_assisted_profiled)
-VG_(run_innerloop__dispatch_assisted_profiled):
- /* AT ENTRY: %eax is next guest addr, %ebp is the
- modified guest state ptr */
- /* We know the guest state pointer has been modified.
- So jump directly to gsp_changed. */
- jmp gsp_changed
- ud2
- /*NOTREACHED*/
-
-/*----------------------------------------------------*/
-/*--- exit points ---*/
-/*----------------------------------------------------*/
-
-gsp_changed:
- /* Someone messed with the gsp. Have to
- defer to scheduler to resolve this. dispatch ctr
- is not yet decremented, so no need to increment. */
- /* %EIP is NOT up to date here. First, need to write
- %eax back to %EIP, but without trashing %ebp since
- that holds the value we want to return to the scheduler.
- Hence use %esi transiently for the guest state pointer. */
- movl 28(%esp), %esi
- movl %eax, OFFSET_x86_EIP(%esi)
- movl %ebp, %eax
- jmp run_innerloop_exit
- /*NOTREACHED*/
-
-counter_is_zero:
- /* %EIP is up to date here */
- /* back out decrement of the dispatch counter */
- addl $1, VG_(dispatch_ctr)
- movl $ VG_TRC_INNER_COUNTERZERO, %eax
- jmp run_innerloop_exit
- /*NOTREACHED*/
-
-fast_lookup_failed:
- /* %EIP is up to date here */
- /* back out decrement of the dispatch counter */
- addl $1, VG_(dispatch_ctr)
- movl $ VG_TRC_INNER_FASTMISS, %eax
- jmp run_innerloop_exit
- /*NOTREACHED*/
-
-
-
-/* All exits from the dispatcher go through here. %eax holds
- the return value.
-*/
-run_innerloop_exit:
- /* We're leaving. Check that nobody messed with
- %mxcsr or %fpucw. We can't mess with %eax here as it
- holds the tentative return value, but any other is OK. */
+ /* We're leaving. Check that nobody messed with %mxcsr
+ or %fpucw. We can't mess with %eax or %edx here as they
+ holds the tentative return value, but any others are OK. */
#if !defined(ENABLE_INNER)
/* This check fails for self-hosting, so skip in that case */
pushl $0
@@ -246,7 +132,7 @@
popl %esi /* get rid of the word without trashing %eflags */
jnz invariant_violation
#endif
- cmpl $0, VG_(machine_x86_have_mxcsr)
+# cmpl $0, VG_(machine_x86_have_mxcsr)
jz L2
pushl $0
stmxcsr (%esp)
@@ -255,72 +141,105 @@
popl %esi
jnz invariant_violation
L2: /* otherwise we're OK */
- jmp run_innerloop_exit_REALLY
-
+ jmp remove_frame
invariant_violation:
- movl $ VG_TRC_INVARIANT_FAILED, %eax
- jmp run_innerloop_exit_REALLY
+ movl $VG_TRC_INVARIANT_FAILED, %eax
+ movl $0, %edx
-run_innerloop_exit_REALLY:
+remove_frame:
+ /* Stash return values */
+ movl 28+4(%esp), %edi /* two_words */
+ movl %eax, 0(%edi)
+ movl %edx, 4(%edi)
+ /* Restore int regs and return. */
popl %ebp
popl %edi
popl %esi
popl %edx
popl %ecx
popl %ebx
+ popl %eax
ret
-.size VG_(run_innerloop), .-VG_(run_innerloop)
+
+/*----------------------------------------------------*/
+/*--- Continuation points ---*/
+/*----------------------------------------------------*/
+
+/* ------ Chain me to slow entry point ------ */
+.global VG_(disp_cp_chain_me_to_slowEP)
+VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ movl $VG_TRC_CHAIN_ME_TO_SLOW_EP, %eax
+ popl %edx
+ /* 5 = movl $VG_(disp_chain_me_to_slowEP), %edx;
+ 2 = call *%edx */
+ subl $5+2, %edx
+ jmp postamble
+
+/* ------ Chain me to fast entry point ------ */
+.global VG_(disp_cp_chain_me_to_fastEP)
+VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_F, RA) */
+ movl $VG_TRC_CHAIN_ME_TO_FAST_EP, %eax
+ popl %edx
+ /* 5 = movl $VG_(disp_chain_me_to_fastEP), %edx;
+ 2 = call *%edx */
+ subl $5+2, %edx
+ jmp postamble
+
+/* ------ Indirect but boring jump ------ */
+.global VG_(disp_cp_xindir)
+VG_(disp_cp_xindir):
+ /* Where are we going? */
+ movl OFFSET_x86_EIP(%ebp), %eax
+
+ /* stats only */
+ addl $1, VG_(stats__n_xindirs_32)
+
+ /* try a fast lookup in the translation cache */
+ movl %eax, %ebx /* next guest addr */
+ andl $VG_TT_FAST_MASK, %ebx /* entry# */
+ movl 0+VG_(tt_fast)(,%ebx,8), %esi /* .guest */
+ movl 4+VG_(tt_fast)(,%ebx,8), %edi /* .host */
+ cmpl %eax, %esi
+ jnz fast_lookup_failed
+
+ /* Found a match. Jump to .host. */
+ jmp *%edi
+ ud2 /* persuade insn decoders not to speculate past here */
+
+fast_lookup_failed:
+ /* stats only */
+ addl $1, VG_(stats__n_xindir_misses_32)
+
+ movl $VG_TRC_INNER_FASTMISS, %eax
+ movl $0, %edx
+ jmp postamble
+
+/* ------ Assisted jump ------ */
+.global VG_(disp_cp_xassisted)
+VG_(disp_cp_xassisted):
+ /* %ebp contains the TRC */
+ movl %ebp, %eax
+ movl $0, %edx
+ jmp postamble
+
+/* ------ Event check failed ------ */
+.global VG_(disp_cp_evcheck_fail)
+VG_(disp_cp_evcheck_fail):
+ movl $VG_TRC_INNER_COUNTERZERO, %eax
+ movl $0, %edx
+ jmp postamble
-/*------------------------------------------------------------*/
-/*--- ---*/
-/*--- A special dispatcher, for running no-redir ---*/
-/*--- translations. Just runs the given translation once. ---*/
-/*--- ---*/
-/*------------------------------------------------------------*/
+.size VG_(disp_run_translations), .-VG_(disp_run_translations)
-/* signature:
-void VG_(run_a_noredir_translation) ( UWord* argblock );
-*/
-
-/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
- and 2 to carry results:
- 0: input: ptr to translation
- 1: input: ptr to guest state
- 2: output: next guest PC
- 3: output: guest state pointer afterwards (== thread return code)
-*/
-.align 16
-.global VG_(run_a_noredir_translation)
-.type VG_(run_a_noredir_translation), @function
-VG_(run_a_noredir_translation):
- /* Save callee-saves regs */
- pushl %esi
- pushl %edi
- pushl %ebp
- pushl %ebx
-
- movl 20(%esp), %edi /* %edi = argblock */
- movl 4(%edi), %ebp /* argblock[1] */
- jmp *0(%edi) /* argblock[0] */
- /*NOTREACHED*/
- ud2
- /* If the translation has been correctly constructed, we
- should resume at the the following label. */
-.global VG_(run_a_noredir_translation__return_point)
-VG_(run_a_noredir_translation__return_point):
- movl 20(%esp), %edi
- movl %eax, 8(%edi) /* argblock[2] */
- movl %ebp, 12(%edi) /* argblock[3] */
-
- popl %ebx
- popl %ebp
- popl %edi
- popl %esi
- ret
-.size VG_(run_a_noredir_translation), .-VG_(run_a_noredir_translation)
-
-
/* Let the linker know we don't need an executable stack */
.section .note.GNU-stack,"",@progbits
diff --git a/main/coregrind/m_errormgr.c b/main/coregrind/m_errormgr.c
index 0c0b83d..b7df38a 100644
--- a/main/coregrind/m_errormgr.c
+++ b/main/coregrind/m_errormgr.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -82,6 +82,9 @@
/* Running count of suppressed errors detected. */
static UInt n_errs_suppressed = 0;
+/* Running count of errors shown. */
+static UInt n_errs_shown = 0;
+
/* Running count of unsuppressed error contexts. */
static UInt n_err_contexts = 0;
@@ -171,6 +174,11 @@
return n_errs_found;
}
+UInt VG_(get_n_errs_shown)( void )
+{
+ return n_errs_shown;
+}
+
/*------------------------------------------------------------*/
/*--- Suppression type ---*/
/*------------------------------------------------------------*/
@@ -203,6 +211,8 @@
typedef
struct {
SuppLocTy ty;
+ Bool name_is_simple_str; /* True if name is a string without
+ '?' and '*' wildcard characters. */
Char* name; /* NULL for NoName and DotDotDot */
}
SuppLoc;
@@ -498,7 +508,7 @@
/* if user wants to debug from a certain error nr, then wait for gdb/vgdb */
if (VG_(clo_vgdb) != Vg_VgdbNo
&& allow_db_attach
- && VG_(dyn_vgdb_error) <= n_errs_found) {
+ && VG_(dyn_vgdb_error) <= n_errs_shown) {
VG_(umsg)("(action on error) vgdb me ... \n");
VG_(gdbserver)( err->tid );
VG_(umsg)("Continuing ...\n");
@@ -524,34 +534,6 @@
VG_(clo_gen_suppressions) = 0;
}
-// See https://bugs.kde.org/show_bug.cgi?id=265803 and b/3423996
-static Bool seen_pc_with_no_function_name_nor_object_file_name = False;
-
-static Bool ErrHasNoFunctionNamesNorObjectFileNames(Error *err) {
- // boil out if the stack trace has no function/object names.
- StackTrace ips = VG_(get_ExeContext_StackTrace)(err->where);
- UWord n_ips = VG_(get_ExeContext_n_ips)(err->where);
- UWord i;
- for (i = 0; i < n_ips; i++) {
- Addr ip = ips[i];
- Char buffer[1024];
- if (VG_(get_fnname)(ip, buffer, sizeof(buffer))) {
- return False;
- }
- if (VG_(get_objname)(ip, buffer, sizeof(buffer))) {
- return False;
- }
- }
- if (!seen_pc_with_no_function_name_nor_object_file_name)
- VG_(umsg)("\n\n\nWARNING: Valgrind encountered a stack trace which has\n"
- "no function names nor object file names.\n"
- "Unless your program has a dynamically generated code (e.g. it is a JIT)\n"
- "something is very much wrong with your binary's debug info.\n"
- "See https://bugs.kde.org/show_bug.cgi?id=265803 and b/3423996\n\n\n"
- );
- seen_pc_with_no_function_name_nor_object_file_name = True;
- return True;
-}
/* Prints an error. Not entirely simple because of the differences
between XML and text mode output.
@@ -666,8 +648,6 @@
-static Int n_errs_shown = 0;
-
/* Top-level entry point to the error management subsystem.
All detected errors are notified here; this routine decides if/when the
user should see the error. */
@@ -741,10 +721,6 @@
"detail than before.\n");
slowdown_message = True;
}
- } else if (seen_pc_with_no_function_name_nor_object_file_name) {
- // we are probably inside some unknown code -- don't spend too much time
- // matching the error reports.
- exe_res = Vg_LowRes;
}
/* Build ourselves the error */
@@ -764,8 +740,7 @@
p->supp->count++;
n_errs_suppressed++;
} else {
- if (!seen_pc_with_no_function_name_nor_object_file_name)
- n_errs_found++;
+ n_errs_found++;
}
/* Move p to the front of the list so that future searches
@@ -828,17 +803,13 @@
p->next = errors;
p->supp = is_suppressible_error(&err);
errors = p;
-
- if (ErrHasNoFunctionNamesNorObjectFileNames(p))
- return;
-
if (p->supp == NULL) {
+ /* update stats */
n_err_contexts++;
n_errs_found++;
+ n_errs_shown++;
/* Actually show the error; more complex than you might think. */
pp_Error( p, /*allow_db_attach*/True, VG_(clo_xml) );
- /* update stats */
- n_errs_shown++;
} else {
n_supp_contexts++;
n_errs_suppressed++;
@@ -885,10 +856,10 @@
}
if (print_error) {
- /* Actually show the error; more complex than you might think. */
- pp_Error(&err, allow_db_attach, VG_(clo_xml));
/* update stats */
n_errs_shown++;
+ /* Actually show the error; more complex than you might think. */
+ pp_Error(&err, allow_db_attach, VG_(clo_xml));
}
return False;
@@ -1134,27 +1105,45 @@
}
-/* *p_caller contains the raw name of a caller, supposedly either
+/* True if s contains no wildcard (?, *) characters. */
+static Bool is_simple_str (Char *s)
+{
+ while (*s) {
+ if (*s == '?' || *s == '*')
+ return False;
+ s++;
+ }
+ return True;
+}
+
+/* buf contains the raw name of a caller, supposedly either
fun:some_function_name or
- obj:some_object_name.
- Set *p_ty accordingly and advance *p_caller over the descriptor
- (fun: or obj:) part.
+ obj:some_object_name or
+ ...
+ Set p->ty and p->name accordingly.
+ p->name is allocated and set to the string
+ after the descriptor (fun: or obj:) part.
Returns False if failed.
*/
-static Bool setLocationTy ( SuppLoc* p )
+static Bool setLocationTy ( SuppLoc* p, Char *buf )
{
- if (VG_(strncmp)(p->name, "fun:", 4) == 0) {
- p->name += 4;
+ if (VG_(strncmp)(buf, "fun:", 4) == 0) {
+ p->name = VG_(arena_strdup)(VG_AR_CORE,
+ "errormgr.sLTy.1", buf+4);
+ p->name_is_simple_str = is_simple_str (p->name);
p->ty = FunName;
return True;
}
- if (VG_(strncmp)(p->name, "obj:", 4) == 0) {
- p->name += 4;
+ if (VG_(strncmp)(buf, "obj:", 4) == 0) {
+ p->name = VG_(arena_strdup)(VG_AR_CORE,
+ "errormgr.sLTy.2", buf+4);
+ p->name_is_simple_str = is_simple_str (p->name);
p->ty = ObjName;
return True;
}
- if (VG_(strcmp)(p->name, "...") == 0) {
+ if (VG_(strcmp)(buf, "...") == 0) {
p->name = NULL;
+ p->name_is_simple_str = False;
p->ty = DotDotDot;
return True;
}
@@ -1225,13 +1214,17 @@
// Initialise temporary reading-in buffer.
for (i = 0; i < VG_MAX_SUPP_CALLERS; i++) {
tmp_callers[i].ty = NoName;
+ tmp_callers[i].name_is_simple_str = False;
tmp_callers[i].name = NULL;
}
supp->string = supp->extra = NULL;
eof = VG_(get_line) ( fd, &buf, &nBuf, &lineno );
- if (eof) break;
+ if (eof) {
+ VG_(arena_free)(VG_AR_CORE, supp);
+ break;
+ }
if (!VG_STREQ(buf, "{")) BOMB("expected '{' or end-of-file");
@@ -1284,6 +1277,8 @@
if (VG_STREQ(buf, "}"))
break;
}
+ VG_(arena_free)(VG_AR_CORE, supp->sname);
+ VG_(arena_free)(VG_AR_CORE, supp);
continue;
}
@@ -1311,9 +1306,7 @@
BOMB("too many callers in stack trace");
if (i > 0 && i >= VG_(clo_backtrace_size))
break;
- tmp_callers[i].name = VG_(arena_strdup)(VG_AR_CORE,
- "errormgr.losf.3", buf);
- if (!setLocationTy(&(tmp_callers[i])))
+ if (!setLocationTy(&(tmp_callers[i]), buf))
BOMB("location should be \"...\", or should start "
"with \"fun:\" or \"obj:\"");
i++;
@@ -1408,13 +1401,117 @@
return False; /* there's no '?' equivalent in the supp syntax */
}
-static Bool supp_pattEQinp ( void* supplocV, void* addrV )
+/* IPtoFunOrObjCompleter is a lazy completer of the IPs
+ needed to match an error with the suppression patterns.
+ The matching between an IP and a suppression pattern is done either
+ with the IP function name or with the IP object name.
+ First time the fun or obj name is needed for an IP member
+ of a stack trace, it will be computed and stored in names.
+ The IPtoFunOrObjCompleter type is designed to minimise the nr of
+ allocations and the nr of debuginfo search. */
+typedef
+ struct {
+ StackTrace ips; // stack trace we are lazily completing.
+ UWord n_ips; // nr of elements in ips.
+
+ Int* fun_offsets;
+ // fun_offsets[i] is the offset in names where the
+ // function name for ips[i] is located.
+ // An offset -1 means the function name is not yet completed.
+ Int* obj_offsets;
+ // Similarly, obj_offsets[i] gives the offset for the
+ // object name for ips[i] (-1 meaning object name not yet completed).
+
+ // All function names and object names will be concatenated
+ // in names. names is reallocated on demand.
+ Char *names;
+ Int names_szB; // size of names.
+ Int names_free; // offset first free Char in names.
+ }
+ IPtoFunOrObjCompleter;
+
+// free the memory in ip2fo.
+static void clearIPtoFunOrObjCompleter
+ (IPtoFunOrObjCompleter* ip2fo)
+{
+ if (ip2fo->fun_offsets) VG_(free)(ip2fo->fun_offsets);
+ if (ip2fo->obj_offsets) VG_(free)(ip2fo->obj_offsets);
+ if (ip2fo->names) VG_(free)(ip2fo->names);
+}
+
+/* foComplete returns the function name or object name for IP.
+ If needFun, returns the function name for IP
+ else returns the object name for IP.
+ The function name or object name will be computed and added in
+ names if not yet done.
+ IP must be equal to focompl->ipc[ixIP]. */
+static Char* foComplete(IPtoFunOrObjCompleter* ip2fo,
+ Addr IP, Int ixIP, Bool needFun)
+{
+ vg_assert (ixIP < ip2fo->n_ips);
+ vg_assert (IP == ip2fo->ips[ixIP]);
+
+ // ptr to the offset array for function offsets (if needFun)
+ // or object offsets (if !needFun).
+ Int** offsets;
+ if (needFun)
+ offsets = &ip2fo->fun_offsets;
+ else
+ offsets = &ip2fo->obj_offsets;
+
+ // Allocate offsets if not yet done.
+ if (!*offsets) {
+ Int i;
+ *offsets =
+ VG_(malloc)("foComplete",
+ ip2fo->n_ips * sizeof(Int));
+ for (i = 0; i < ip2fo->n_ips; i++)
+ (*offsets)[i] = -1;
+ }
+
+ // Complete Fun name or Obj name for IP if not yet done.
+ if ((*offsets)[ixIP] == -1) {
+ /* Ensure we have ERRTXT_LEN characters available in names */
+ if (ip2fo->names_szB
+ < ip2fo->names_free + ERRTXT_LEN) {
+ ip2fo->names
+ = VG_(realloc)("foc_names",
+ ip2fo->names,
+ ip2fo->names_szB + ERRTXT_LEN);
+ ip2fo->names_szB += ERRTXT_LEN;
+ }
+ Char* caller_name = ip2fo->names + ip2fo->names_free;
+ (*offsets)[ixIP] = ip2fo->names_free;
+ if (needFun) {
+ /* Get the function name into 'caller_name', or "???"
+ if unknown. */
+ // Nb: C++-mangled names are used in suppressions. Do, though,
+ // Z-demangle them, since otherwise it's possible to wind
+ // up comparing "malloc" in the suppression against
+ // "_vgrZU_libcZdsoZa_malloc" in the backtrace, and the
+ // two of them need to be made to match.
+ if (!VG_(get_fnname_no_cxx_demangle)(IP, caller_name, ERRTXT_LEN))
+ VG_(strcpy)(caller_name, "???");
+ } else {
+ /* Get the object name into 'caller_name', or "???"
+ if unknown. */
+ if (!VG_(get_objname)(IP, caller_name, ERRTXT_LEN))
+ VG_(strcpy)(caller_name, "???");
+ }
+ ip2fo->names_free += VG_(strlen)(caller_name) + 1;
+ }
+
+ return ip2fo->names + (*offsets)[ixIP];
+}
+
+static Bool supp_pattEQinp ( void* supplocV, void* addrV,
+ void* inputCompleter, UWord ixAddrV )
{
SuppLoc* supploc = (SuppLoc*)supplocV; /* PATTERN */
Addr ip = *(Addr*)addrV; /* INPUT */
-
- Char caller_name[ERRTXT_LEN];
- caller_name[0] = 0;
+ IPtoFunOrObjCompleter* ip2fo
+ = (IPtoFunOrObjCompleter*)inputCompleter;
+ Char* funobj_name; // Fun or Obj name.
/* So, does this IP address match this suppression-line? */
switch (supploc->ty) {
@@ -1426,43 +1523,33 @@
this can't happen. */
vg_assert(0);
case ObjName:
- /* Get the object name into 'caller_name', or "???"
- if unknown. */
- if (!VG_(get_objname)(ip, caller_name, ERRTXT_LEN))
- VG_(strcpy)(caller_name, "???");
+ funobj_name = foComplete(ip2fo, ip, ixAddrV, False /*needFun*/);
break;
- case FunName:
- /* Get the function name into 'caller_name', or "???"
- if unknown. */
- // Nb: C++-mangled names are used in suppressions. Do, though,
- // Z-demangle them, since otherwise it's possible to wind
- // up comparing "malloc" in the suppression against
- // "_vgrZU_libcZdsoZa_malloc" in the backtrace, and the
- // two of them need to be made to match.
- if (!VG_(get_fnname_no_cxx_demangle)(ip, caller_name, ERRTXT_LEN))
- VG_(strcpy)(caller_name, "???");
+ case FunName:
+ funobj_name = foComplete(ip2fo, ip, ixAddrV, True /*needFun*/);
break;
default:
vg_assert(0);
}
- /* So now we have the function or object name in caller_name, and
+ /* So now we have the function or object name in funobj_name, and
the pattern (at the character level) to match against is in
supploc->name. Hence (and leading to a re-entrant call of
- VG_(generic_match)): */
- return VG_(string_match)(supploc->name, caller_name);
+ VG_(generic_match) if there is a wildcard character): */
+ if (supploc->name_is_simple_str)
+ return VG_(strcmp) (supploc->name, funobj_name) == 0;
+ else
+ return VG_(string_match)(supploc->name, funobj_name);
}
/////////////////////////////////////////////////////
-static Bool supp_matches_callers(Error* err, Supp* su)
+static Bool supp_matches_callers(IPtoFunOrObjCompleter* ip2fo, Supp* su)
{
/* Unwrap the args and set up the correct parameterisation of
VG_(generic_match), using supploc_IsStar, supploc_IsQuery and
supp_pattEQinp. */
- /* note, StackTrace === Addr* */
- StackTrace ips = VG_(get_ExeContext_StackTrace)(err->where);
- UWord n_ips = VG_(get_ExeContext_n_ips)(err->where);
+ /* note, StackTrace ip2fo->ips === Addr* */
SuppLoc* supps = su->callers;
UWord n_supps = su->n_callers;
UWord szbPatt = sizeof(SuppLoc);
@@ -1472,8 +1559,9 @@
VG_(generic_match)(
matchAll,
/*PATT*/supps, szbPatt, n_supps, 0/*initial Ix*/,
- /*INPUT*/ips, szbInput, n_ips, 0/*initial Ix*/,
- supploc_IsStar, supploc_IsQuery, supp_pattEQinp
+ /*INPUT*/ip2fo->ips, szbInput, ip2fo->n_ips, 0/*initial Ix*/,
+ supploc_IsStar, supploc_IsQuery, supp_pattEQinp,
+ ip2fo
);
}
@@ -1510,14 +1598,38 @@
Supp* su;
Supp* su_prev;
+ IPtoFunOrObjCompleter ip2fo;
+ /* Conceptually, ip2fo contains an array of function names and an array of
+ object names, corresponding to the array of IP of err->where.
+ These names are just computed 'on demand' (so once maximum),
+ then stored (efficiently, avoiding too many allocs) in ip2fo to be re-usable
+ for the matching of the same IP with the next suppression pattern.
+
+ VG_(generic_match) gets this 'IP to Fun or Obj name completer' as one
+ of its arguments. It will then pass it to the function
+ supp_pattEQinp which will then lazily complete the IP function name or
+ object name inside ip2fo. Next time the fun or obj name for the same
+ IP is needed (i.e. for the matching with the next suppr pattern), then
+ the fun or obj name will not be searched again in the debug info. */
+
/* stats gathering */
em_supplist_searches++;
+ /* Prepare the lazy input completer. */
+ ip2fo.ips = VG_(get_ExeContext_StackTrace)(err->where);
+ ip2fo.n_ips = VG_(get_ExeContext_n_ips)(err->where);
+ ip2fo.fun_offsets = NULL;
+ ip2fo.obj_offsets = NULL;
+ ip2fo.names = NULL;
+ ip2fo.names_szB = 0;
+ ip2fo.names_free = 0;
+
/* See if the error context matches any suppression. */
su_prev = NULL;
for (su = suppressions; su != NULL; su = su->next) {
em_supplist_cmps++;
- if (supp_matches_error(su, err) && supp_matches_callers(err, su)) {
+ if (supp_matches_error(su, err)
+ && supp_matches_callers(&ip2fo, su)) {
/* got a match. Move this entry to the head of the list
in the hope of making future searches cheaper. */
if (su_prev) {
@@ -1526,10 +1638,12 @@
su->next = suppressions;
suppressions = su;
}
+ clearIPtoFunOrObjCompleter(&ip2fo);
return su;
}
su_prev = su;
}
+ clearIPtoFunOrObjCompleter(&ip2fo);
return NULL; /* no matches */
}
diff --git a/main/coregrind/m_execontext.c b/main/coregrind/m_execontext.c
index 208684d..61f79e3 100644
--- a/main/coregrind/m_execontext.c
+++ b/main/coregrind/m_execontext.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -297,7 +297,7 @@
static ExeContext* record_ExeContext_wrk ( ThreadId tid, Word first_ip_delta,
Bool first_ip_only )
{
- Addr ips[VG_DEEPEST_BACKTRACE];
+ Addr ips[VG_(clo_backtrace_size)];
UInt n_ips;
init_ExeContext_storage();
@@ -307,12 +307,9 @@
vg_assert(VG_(is_valid_tid)(tid));
- vg_assert(VG_(clo_backtrace_size) >= 1 &&
- VG_(clo_backtrace_size) <= VG_DEEPEST_BACKTRACE);
-
if (first_ip_only) {
n_ips = 1;
- ips[0] = VG_(get_IP)(tid);
+ ips[0] = VG_(get_IP)(tid) + first_ip_delta;
} else {
n_ips = VG_(get_StackTrace)( tid, ips, VG_(clo_backtrace_size),
NULL/*array to dump SP values in*/,
@@ -431,8 +428,9 @@
False/*!first_ip_only*/ );
}
-ExeContext* VG_(record_depth_1_ExeContext)( ThreadId tid ) {
- return record_ExeContext_wrk( tid, 0/*first_ip_delta*/,
+ExeContext* VG_(record_depth_1_ExeContext)( ThreadId tid, Word first_ip_delta )
+{
+ return record_ExeContext_wrk( tid, first_ip_delta,
True/*first_ip_only*/ );
}
diff --git a/main/coregrind/m_gdbserver/32bit-core-valgrind-s1.xml b/main/coregrind/m_gdbserver/32bit-core-valgrind-s1.xml
index 9a0582f..a29701f 100644
--- a/main/coregrind/m_gdbserver/32bit-core-valgrind-s1.xml
+++ b/main/coregrind/m_gdbserver/32bit-core-valgrind-s1.xml
@@ -27,6 +27,11 @@
<field name="ID" start="21" end="21"/>
</flags>
+ <struct id="i387_ext_s">
+ <field name="b64" type="uint64"/>
+ <field name="b16" type="uint16"/>
+ </struct>
+
<reg name="eaxs1" bitsize="32" type="int32"/>
<reg name="ecxs1" bitsize="32" type="int32"/>
<reg name="edxs1" bitsize="32" type="int32"/>
@@ -45,14 +50,14 @@
<reg name="fss1" bitsize="32" type="int32"/>
<reg name="gss1" bitsize="32" type="int32"/>
- <reg name="st0s1" bitsize="80" type="i387_ext"/>
- <reg name="st1s1" bitsize="80" type="i387_ext"/>
- <reg name="st2s1" bitsize="80" type="i387_ext"/>
- <reg name="st3s1" bitsize="80" type="i387_ext"/>
- <reg name="st4s1" bitsize="80" type="i387_ext"/>
- <reg name="st5s1" bitsize="80" type="i387_ext"/>
- <reg name="st6s1" bitsize="80" type="i387_ext"/>
- <reg name="st7s1" bitsize="80" type="i387_ext"/>
+ <reg name="st0s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st1s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st2s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st3s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st4s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st5s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st6s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st7s1" bitsize="80" type="i387_ext_s"/>
<reg name="fctrls1" bitsize="32" type="int" group="float"/>
<reg name="fstats1" bitsize="32" type="int" group="float"/>
diff --git a/main/coregrind/m_gdbserver/32bit-core-valgrind-s2.xml b/main/coregrind/m_gdbserver/32bit-core-valgrind-s2.xml
index 1b272c5..7ea1482 100644
--- a/main/coregrind/m_gdbserver/32bit-core-valgrind-s2.xml
+++ b/main/coregrind/m_gdbserver/32bit-core-valgrind-s2.xml
@@ -27,6 +27,11 @@
<field name="ID" start="21" end="21"/>
</flags>
+ <struct id="i387_ext_s">
+ <field name="b64" type="uint64"/>
+ <field name="b16" type="uint16"/>
+ </struct>
+
<reg name="eaxs2" bitsize="32" type="int32"/>
<reg name="ecxs2" bitsize="32" type="int32"/>
<reg name="edxs2" bitsize="32" type="int32"/>
@@ -45,14 +50,14 @@
<reg name="fss2" bitsize="32" type="int32"/>
<reg name="gss2" bitsize="32" type="int32"/>
- <reg name="st0s2" bitsize="80" type="i387_ext"/>
- <reg name="st1s2" bitsize="80" type="i387_ext"/>
- <reg name="st2s2" bitsize="80" type="i387_ext"/>
- <reg name="st3s2" bitsize="80" type="i387_ext"/>
- <reg name="st4s2" bitsize="80" type="i387_ext"/>
- <reg name="st5s2" bitsize="80" type="i387_ext"/>
- <reg name="st6s2" bitsize="80" type="i387_ext"/>
- <reg name="st7s2" bitsize="80" type="i387_ext"/>
+ <reg name="st0s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st1s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st2s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st3s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st4s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st5s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st6s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st7s2" bitsize="80" type="i387_ext_s"/>
<reg name="fctrls2" bitsize="32" type="int" group="float"/>
<reg name="fstats2" bitsize="32" type="int" group="float"/>
diff --git a/main/coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml b/main/coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml
index 1a368c4..a650b16 100644
--- a/main/coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml
+++ b/main/coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml
@@ -7,15 +7,15 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.i386.sse.valgrind.s1">
- <vector id="v4f" type="ieee_single" count="4"/>
- <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v4f_s" type="uint32" count="4"/>
+ <vector id="v2d_s" type="uint64" count="2"/>
<vector id="v16i8" type="int8" count="16"/>
<vector id="v8i16" type="int16" count="8"/>
<vector id="v4i32" type="int32" count="4"/>
<vector id="v2i64" type="int64" count="2"/>
- <union id="vec128">
- <field name="v4_float" type="v4f"/>
- <field name="v2_double" type="v2d"/>
+ <union id="vec128_s">
+ <field name="v4_float" type="v4f_s"/>
+ <field name="v2_double" type="v2d_s"/>
<field name="v16_int8" type="v16i8"/>
<field name="v8_int16" type="v8i16"/>
<field name="v4_int32" type="v4i32"/>
@@ -39,14 +39,14 @@
<field name="FZ" start="15" end="15"/>
</flags>
- <reg name="xmm0s1" bitsize="128" type="vec128"/>
- <reg name="xmm1s1" bitsize="128" type="vec128"/>
- <reg name="xmm2s1" bitsize="128" type="vec128"/>
- <reg name="xmm3s1" bitsize="128" type="vec128"/>
- <reg name="xmm4s1" bitsize="128" type="vec128"/>
- <reg name="xmm5s1" bitsize="128" type="vec128"/>
- <reg name="xmm6s1" bitsize="128" type="vec128"/>
- <reg name="xmm7s1" bitsize="128" type="vec128"/>
+ <reg name="xmm0s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm1s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm2s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm3s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm4s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm5s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm6s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm7s1" bitsize="128" type="vec128_s"/>
<reg name="mxcsrs1" bitsize="32" type="i386_mxcsr" group="vector"/>
</feature>
diff --git a/main/coregrind/m_gdbserver/32bit-sse-valgrind-s2.xml b/main/coregrind/m_gdbserver/32bit-sse-valgrind-s2.xml
index c69da70..b3b1ac4 100644
--- a/main/coregrind/m_gdbserver/32bit-sse-valgrind-s2.xml
+++ b/main/coregrind/m_gdbserver/32bit-sse-valgrind-s2.xml
@@ -7,15 +7,15 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.i386.sse.valgrind.s2">
- <vector id="v4f" type="ieee_single" count="4"/>
- <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v4f_s" type="uint32" count="4"/>
+ <vector id="v2d_s" type="uint64" count="2"/>
<vector id="v16i8" type="int8" count="16"/>
<vector id="v8i16" type="int16" count="8"/>
<vector id="v4i32" type="int32" count="4"/>
<vector id="v2i64" type="int64" count="2"/>
- <union id="vec128">
- <field name="v4_float" type="v4f"/>
- <field name="v2_double" type="v2d"/>
+ <union id="vec128_s">
+ <field name="v4_float" type="v4f_s"/>
+ <field name="v2_double" type="v2d_s"/>
<field name="v16_int8" type="v16i8"/>
<field name="v8_int16" type="v8i16"/>
<field name="v4_int32" type="v4i32"/>
@@ -39,14 +39,14 @@
<field name="FZ" start="15" end="15"/>
</flags>
- <reg name="xmm0s2" bitsize="128" type="vec128"/>
- <reg name="xmm1s2" bitsize="128" type="vec128"/>
- <reg name="xmm2s2" bitsize="128" type="vec128"/>
- <reg name="xmm3s2" bitsize="128" type="vec128"/>
- <reg name="xmm4s2" bitsize="128" type="vec128"/>
- <reg name="xmm5s2" bitsize="128" type="vec128"/>
- <reg name="xmm6s2" bitsize="128" type="vec128"/>
- <reg name="xmm7s2" bitsize="128" type="vec128"/>
+ <reg name="xmm0s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm1s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm2s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm3s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm4s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm5s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm6s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm7s2" bitsize="128" type="vec128_s"/>
<reg name="mxcsrs2" bitsize="32" type="i386_mxcsr" group="vector"/>
</feature>
diff --git a/main/coregrind/m_gdbserver/64bit-avx-valgrind-s1.xml b/main/coregrind/m_gdbserver/64bit-avx-valgrind-s1.xml
new file mode 100644
index 0000000..cc2bb59
--- /dev/null
+++ b/main/coregrind/m_gdbserver/64bit-avx-valgrind-s1.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.i386.avx.valgrind.s1">
+ <reg name="ymm0hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm1hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm2hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm3hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm4hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm5hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm6hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm7hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm8hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm9hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm10hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm11hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm12hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm13hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm14hs1" bitsize="128" type="uint128"/>
+ <reg name="ymm15hs1" bitsize="128" type="uint128"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/64bit-avx-valgrind-s2.xml b/main/coregrind/m_gdbserver/64bit-avx-valgrind-s2.xml
new file mode 100644
index 0000000..f82cb16
--- /dev/null
+++ b/main/coregrind/m_gdbserver/64bit-avx-valgrind-s2.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.i386.avx.valgrind.s2">
+ <reg name="ymm0hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm1hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm2hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm3hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm4hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm5hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm6hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm7hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm8hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm9hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm10hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm11hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm12hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm13hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm14hs2" bitsize="128" type="uint128"/>
+ <reg name="ymm15hs2" bitsize="128" type="uint128"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/64bit-avx.xml b/main/coregrind/m_gdbserver/64bit-avx.xml
new file mode 100644
index 0000000..838bd6a
--- /dev/null
+++ b/main/coregrind/m_gdbserver/64bit-avx.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.i386.avx">
+ <reg name="ymm0h" bitsize="128" type="uint128"/>
+ <reg name="ymm1h" bitsize="128" type="uint128"/>
+ <reg name="ymm2h" bitsize="128" type="uint128"/>
+ <reg name="ymm3h" bitsize="128" type="uint128"/>
+ <reg name="ymm4h" bitsize="128" type="uint128"/>
+ <reg name="ymm5h" bitsize="128" type="uint128"/>
+ <reg name="ymm6h" bitsize="128" type="uint128"/>
+ <reg name="ymm7h" bitsize="128" type="uint128"/>
+ <reg name="ymm8h" bitsize="128" type="uint128"/>
+ <reg name="ymm9h" bitsize="128" type="uint128"/>
+ <reg name="ymm10h" bitsize="128" type="uint128"/>
+ <reg name="ymm11h" bitsize="128" type="uint128"/>
+ <reg name="ymm12h" bitsize="128" type="uint128"/>
+ <reg name="ymm13h" bitsize="128" type="uint128"/>
+ <reg name="ymm14h" bitsize="128" type="uint128"/>
+ <reg name="ymm15h" bitsize="128" type="uint128"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/64bit-core-valgrind-s1.xml b/main/coregrind/m_gdbserver/64bit-core-valgrind-s1.xml
index 67b497f..8c3b504 100644
--- a/main/coregrind/m_gdbserver/64bit-core-valgrind-s1.xml
+++ b/main/coregrind/m_gdbserver/64bit-core-valgrind-s1.xml
@@ -27,6 +27,11 @@
<field name="ID" start="21" end="21"/>
</flags>
+ <struct id="i387_ext_s">
+ <field name="b64" type="uint64"/>
+ <field name="b16" type="uint16"/>
+ </struct>
+
<reg name="raxs1" bitsize="64" type="int64"/>
<reg name="rbxs1" bitsize="64" type="int64"/>
<reg name="rcxs1" bitsize="64" type="int64"/>
@@ -53,14 +58,14 @@
<reg name="fss1" bitsize="32" type="int32"/>
<reg name="gss1" bitsize="32" type="int32"/>
- <reg name="st0s1" bitsize="80" type="i387_ext"/>
- <reg name="st1s1" bitsize="80" type="i387_ext"/>
- <reg name="st2s1" bitsize="80" type="i387_ext"/>
- <reg name="st3s1" bitsize="80" type="i387_ext"/>
- <reg name="st4s1" bitsize="80" type="i387_ext"/>
- <reg name="st5s1" bitsize="80" type="i387_ext"/>
- <reg name="st6s1" bitsize="80" type="i387_ext"/>
- <reg name="st7s1" bitsize="80" type="i387_ext"/>
+ <reg name="st0s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st1s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st2s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st3s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st4s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st5s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st6s1" bitsize="80" type="i387_ext_s"/>
+ <reg name="st7s1" bitsize="80" type="i387_ext_s"/>
<reg name="fctrls1" bitsize="32" type="int" group="float"/>
<reg name="fstats1" bitsize="32" type="int" group="float"/>
diff --git a/main/coregrind/m_gdbserver/64bit-core-valgrind-s2.xml b/main/coregrind/m_gdbserver/64bit-core-valgrind-s2.xml
index 14f2726..b1bcba8 100644
--- a/main/coregrind/m_gdbserver/64bit-core-valgrind-s2.xml
+++ b/main/coregrind/m_gdbserver/64bit-core-valgrind-s2.xml
@@ -27,6 +27,11 @@
<field name="ID" start="21" end="21"/>
</flags>
+ <struct id="i387_ext_s">
+ <field name="b64" type="uint64"/>
+ <field name="b16" type="uint16"/>
+ </struct>
+
<reg name="raxs2" bitsize="64" type="int64"/>
<reg name="rbxs2" bitsize="64" type="int64"/>
<reg name="rcxs2" bitsize="64" type="int64"/>
@@ -53,14 +58,14 @@
<reg name="fss2" bitsize="32" type="int32"/>
<reg name="gss2" bitsize="32" type="int32"/>
- <reg name="st0s2" bitsize="80" type="i387_ext"/>
- <reg name="st1s2" bitsize="80" type="i387_ext"/>
- <reg name="st2s2" bitsize="80" type="i387_ext"/>
- <reg name="st3s2" bitsize="80" type="i387_ext"/>
- <reg name="st4s2" bitsize="80" type="i387_ext"/>
- <reg name="st5s2" bitsize="80" type="i387_ext"/>
- <reg name="st6s2" bitsize="80" type="i387_ext"/>
- <reg name="st7s2" bitsize="80" type="i387_ext"/>
+ <reg name="st0s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st1s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st2s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st3s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st4s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st5s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st6s2" bitsize="80" type="i387_ext_s"/>
+ <reg name="st7s2" bitsize="80" type="i387_ext_s"/>
<reg name="fctrls2" bitsize="32" type="int" group="float"/>
<reg name="fstats2" bitsize="32" type="int" group="float"/>
diff --git a/main/coregrind/m_gdbserver/64bit-sse-valgrind-s1.xml b/main/coregrind/m_gdbserver/64bit-sse-valgrind-s1.xml
index 9db6c74..eb01261 100644
--- a/main/coregrind/m_gdbserver/64bit-sse-valgrind-s1.xml
+++ b/main/coregrind/m_gdbserver/64bit-sse-valgrind-s1.xml
@@ -7,15 +7,15 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.i386.sse.valgrind.s1">
- <vector id="v4f" type="ieee_single" count="4"/>
- <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v4f_s" type="uint32" count="4"/>
+ <vector id="v2d_s" type="uint64" count="2"/>
<vector id="v16i8" type="int8" count="16"/>
<vector id="v8i16" type="int16" count="8"/>
<vector id="v4i32" type="int32" count="4"/>
<vector id="v2i64" type="int64" count="2"/>
- <union id="vec128">
- <field name="v4_float" type="v4f"/>
- <field name="v2_double" type="v2d"/>
+ <union id="vec128_s">
+ <field name="v4_float" type="v4f_s"/>
+ <field name="v2_double" type="v2d_s"/>
<field name="v16_int8" type="v16i8"/>
<field name="v8_int16" type="v8i16"/>
<field name="v4_int32" type="v4i32"/>
@@ -39,22 +39,22 @@
<field name="FZ" start="15" end="15"/>
</flags>
- <reg name="xmm0s1" bitsize="128" type="vec128"/>
- <reg name="xmm1s1" bitsize="128" type="vec128"/>
- <reg name="xmm2s1" bitsize="128" type="vec128"/>
- <reg name="xmm3s1" bitsize="128" type="vec128"/>
- <reg name="xmm4s1" bitsize="128" type="vec128"/>
- <reg name="xmm5s1" bitsize="128" type="vec128"/>
- <reg name="xmm6s1" bitsize="128" type="vec128"/>
- <reg name="xmm7s1" bitsize="128" type="vec128"/>
- <reg name="xmm8s1" bitsize="128" type="vec128"/>
- <reg name="xmm9s1" bitsize="128" type="vec128"/>
- <reg name="xmm10s1" bitsize="128" type="vec128"/>
- <reg name="xmm11s1" bitsize="128" type="vec128"/>
- <reg name="xmm12s1" bitsize="128" type="vec128"/>
- <reg name="xmm13s1" bitsize="128" type="vec128"/>
- <reg name="xmm14s1" bitsize="128" type="vec128"/>
- <reg name="xmm15s1" bitsize="128" type="vec128"/>
+ <reg name="xmm0s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm1s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm2s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm3s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm4s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm5s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm6s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm7s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm8s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm9s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm10s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm11s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm12s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm13s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm14s1" bitsize="128" type="vec128_s"/>
+ <reg name="xmm15s1" bitsize="128" type="vec128_s"/>
<reg name="mxcsrs1" bitsize="32" type="i386_mxcsr" group="vector"/>
</feature>
diff --git a/main/coregrind/m_gdbserver/64bit-sse-valgrind-s2.xml b/main/coregrind/m_gdbserver/64bit-sse-valgrind-s2.xml
index 189910e..c4a66f1 100644
--- a/main/coregrind/m_gdbserver/64bit-sse-valgrind-s2.xml
+++ b/main/coregrind/m_gdbserver/64bit-sse-valgrind-s2.xml
@@ -7,15 +7,15 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.i386.sse.valgrind.s2">
- <vector id="v4f" type="ieee_single" count="4"/>
- <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v4f_s" type="uint32" count="4"/>
+ <vector id="v2d_s" type="uint64" count="2"/>
<vector id="v16i8" type="int8" count="16"/>
<vector id="v8i16" type="int16" count="8"/>
<vector id="v4i32" type="int32" count="4"/>
<vector id="v2i64" type="int64" count="2"/>
- <union id="vec128">
- <field name="v4_float" type="v4f"/>
- <field name="v2_double" type="v2d"/>
+ <union id="vec128_s">
+ <field name="v4_float" type="v4f_s"/>
+ <field name="v2_double" type="v2d_s"/>
<field name="v16_int8" type="v16i8"/>
<field name="v8_int16" type="v8i16"/>
<field name="v4_int32" type="v4i32"/>
@@ -39,22 +39,22 @@
<field name="FZ" start="15" end="15"/>
</flags>
- <reg name="xmm0s2" bitsize="128" type="vec128"/>
- <reg name="xmm1s2" bitsize="128" type="vec128"/>
- <reg name="xmm2s2" bitsize="128" type="vec128"/>
- <reg name="xmm3s2" bitsize="128" type="vec128"/>
- <reg name="xmm4s2" bitsize="128" type="vec128"/>
- <reg name="xmm5s2" bitsize="128" type="vec128"/>
- <reg name="xmm6s2" bitsize="128" type="vec128"/>
- <reg name="xmm7s2" bitsize="128" type="vec128"/>
- <reg name="xmm8s2" bitsize="128" type="vec128"/>
- <reg name="xmm9s2" bitsize="128" type="vec128"/>
- <reg name="xmm10s2" bitsize="128" type="vec128"/>
- <reg name="xmm11s2" bitsize="128" type="vec128"/>
- <reg name="xmm12s2" bitsize="128" type="vec128"/>
- <reg name="xmm13s2" bitsize="128" type="vec128"/>
- <reg name="xmm14s2" bitsize="128" type="vec128"/>
- <reg name="xmm15s2" bitsize="128" type="vec128"/>
+ <reg name="xmm0s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm1s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm2s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm3s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm4s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm5s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm6s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm7s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm8s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm9s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm10s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm11s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm12s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm13s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm14s2" bitsize="128" type="vec128_s"/>
+ <reg name="xmm15s2" bitsize="128" type="vec128_s"/>
<reg name="mxcsrs2" bitsize="32" type="i386_mxcsr" group="vector"/>
</feature>
diff --git a/main/coregrind/m_gdbserver/README_DEVELOPERS b/main/coregrind/m_gdbserver/README_DEVELOPERS
index 153660f..3cf740f 100644
--- a/main/coregrind/m_gdbserver/README_DEVELOPERS
+++ b/main/coregrind/m_gdbserver/README_DEVELOPERS
@@ -193,7 +193,7 @@
and select are working ok and red-hat 5.3 (an old kernel), everything
works properly.
-Need to investigate if darwin and/or AIX can similarly do syscall
+Need to investigate if darwin can similarly do syscall
restart with ptrace.
The vgdb argument --max-invoke-ms=xxx allows to control the nr of
@@ -219,7 +219,7 @@
This code had to be changed to integrate properly within valgrind
(e.g. no libc usage). Some of these changes have been ensured by
using the preprocessor to replace calls by valgrind equivalent,
-e.g. #define memcpy(...) VG_(memcpy) (...).
+e.g. #define strcmp(...) VG_(strcmp) (...).
Some "control flow" changes are due to the fact that gdbserver inside
valgrind must return the control to valgrind when the 'debugged'
@@ -246,7 +246,7 @@
---------------------------
Automatic Valgrind gdbserver tests are in the directory
$(top_srcdir)/gdbserver_tests.
-Read $(top_srcdir)/gdbserver_tests/README_DEVELOPPERS for more
+Read $(top_srcdir)/gdbserver_tests/README_DEVELOPERS for more
info about testing.
How to integrate support for a new architecture xxx?
@@ -295,16 +295,9 @@
Modify coregrind/Makefile.am:
add valgrind-low-hal9000.c
- If you have target xml description, also add them in pkglib_DATA
+ If you have target xml description, also add them to GDBSERVER_XML_FILES
-A not handled comment given by Julian at FOSDEM.
-------------------------------------------------
-* the check for vgdb-poll in scheduler.c could/should be moved to another place:
- instead of having it in run_thread_for_a_while
- the vgdb poll check could be in VG_(scheduler).
- (not clear to me why one is better than the other ???)
-
TODO and/or additional nice things to have
------------------------------------------
* many options can be changed on-line without problems.
@@ -312,11 +305,9 @@
its arguments like the startup options of m_main.c and tool clo processing.
* have a memcheck monitor command
- who_points_at <address> | <loss_record_nr>
- that would describe the addresses where a pointer is found
- to address (or address leaked at loss_record_nr>)
- This would allow to interactively searching who is "keeping" a piece
- of memory.
+ show_dangling_pointers [last_n_recently_released_blocks]
+ showing which of the n last recently released blocks are still
+ referenced. These references are (potential) dangling pointers.
* some GDBTD in the code
@@ -330,24 +321,6 @@
of these architectures might complete this
(see the GDBTD in valgrind-low-*.c)
-* "hardware" watchpoint (read/write/access watchpoints) are implemented
- but can't persuade gdb to insert a hw watchpoint of what valgrind
- supports (i.e. of whatever length).
- The reason why gdb does not accept a hardware watch of let's say
- 10 bytes is:
-default_region_ok_for_hw_watchpoint (addr=134520360, len=10) at target.c:2738
-2738 return (len <= gdbarch_ptr_bit (target_gdbarch) / TARGET_CHAR_BIT);
-#0 default_region_ok_for_hw_watchpoint (addr=134520360, len=10)
- at target.c:2738
-2738 return (len <= gdbarch_ptr_bit (target_gdbarch) / TARGET_CHAR_BIT);
-#1 0x08132e65 in can_use_hardware_watchpoint (v=0x85a8ef0)
- at breakpoint.c:8300
-8300 if (!target_region_ok_for_hw_watchpoint (vaddr, len))
-#2 0x0813bd17 in watch_command_1 (arg=0x84169f0 "", accessflag=2,
- from_tty=<value optimized out>) at breakpoint.c:8140
- A small patch in gdb remote.c allowed to control the remote target watchpoint
- length limit. This patch is to be submitted.
-
* Currently, at least on recent linux kernel, vgdb can properly wake
up a valgrind process which is blocked in system calls. Maybe we
need to see till which kernel version the ptrace + syscall restart
diff --git a/main/coregrind/m_gdbserver/amd64-avx-coresse-valgrind.xml b/main/coregrind/m_gdbserver/amd64-avx-coresse-valgrind.xml
new file mode 100644
index 0000000..2b75715
--- /dev/null
+++ b/main/coregrind/m_gdbserver/amd64-avx-coresse-valgrind.xml
@@ -0,0 +1,22 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- AMD64 - core and sse. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>i386:x86-64</architecture>
+ <xi:include href="64bit-core.xml"/>
+ <xi:include href="64bit-sse.xml"/>
+ <xi:include href="64bit-avx.xml"/>
+ <xi:include href="64bit-core-valgrind-s1.xml"/>
+ <xi:include href="64bit-sse-valgrind-s1.xml"/>
+ <xi:include href="64bit-avx-valgrind-s1.xml"/>
+ <xi:include href="64bit-core-valgrind-s2.xml"/>
+ <xi:include href="64bit-sse-valgrind-s2.xml"/>
+ <xi:include href="64bit-avx-valgrind-s2.xml"/>
+</target>
diff --git a/main/coregrind/m_gdbserver/amd64-avx-coresse.xml b/main/coregrind/m_gdbserver/amd64-avx-coresse.xml
new file mode 100644
index 0000000..c46b318
--- /dev/null
+++ b/main/coregrind/m_gdbserver/amd64-avx-coresse.xml
@@ -0,0 +1,16 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- AMD64 - core and sse and avx. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>i386:x86-64</architecture>
+ <xi:include href="64bit-core.xml"/>
+ <xi:include href="64bit-sse.xml"/>
+ <xi:include href="64bit-avx.xml"/>
+</target>
diff --git a/main/coregrind/m_gdbserver/amd64-avx-linux-valgrind.xml b/main/coregrind/m_gdbserver/amd64-avx-linux-valgrind.xml
new file mode 100644
index 0000000..d692664
--- /dev/null
+++ b/main/coregrind/m_gdbserver/amd64-avx-linux-valgrind.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- AMD64 with avx - Includes Linux-only special "register". -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>i386:x86-64</architecture>
+ <osabi>GNU/Linux</osabi>
+ <xi:include href="64bit-core.xml"/>
+ <xi:include href="64bit-sse.xml"/>
+ <xi:include href="64bit-linux.xml"/>
+ <xi:include href="64bit-avx.xml"/>
+ <xi:include href="64bit-core-valgrind-s1.xml"/>
+ <xi:include href="64bit-sse-valgrind-s1.xml"/>
+ <xi:include href="64bit-linux-valgrind-s1.xml"/>
+ <xi:include href="64bit-avx-valgrind-s1.xml"/>
+ <xi:include href="64bit-core-valgrind-s2.xml"/>
+ <xi:include href="64bit-sse-valgrind-s2.xml"/>
+ <xi:include href="64bit-linux-valgrind-s2.xml"/>
+ <xi:include href="64bit-avx-valgrind-s2.xml"/>
+</target>
diff --git a/main/coregrind/m_gdbserver/amd64-avx-linux.xml b/main/coregrind/m_gdbserver/amd64-avx-linux.xml
new file mode 100644
index 0000000..3fea2e4
--- /dev/null
+++ b/main/coregrind/m_gdbserver/amd64-avx-linux.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- AMD64 with avx - Includes Linux-only special "register". -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>i386:x86-64</architecture>
+ <osabi>GNU/Linux</osabi>
+ <xi:include href="64bit-core.xml"/>
+ <xi:include href="64bit-sse.xml"/>
+ <xi:include href="64bit-linux.xml"/>
+ <xi:include href="64bit-avx.xml"/>
+</target>
diff --git a/main/coregrind/m_gdbserver/arm-vfpv3-valgrind-s1.xml b/main/coregrind/m_gdbserver/arm-vfpv3-valgrind-s1.xml
index 619f73f..c91f9c1 100644
--- a/main/coregrind/m_gdbserver/arm-vfpv3-valgrind-s1.xml
+++ b/main/coregrind/m_gdbserver/arm-vfpv3-valgrind-s1.xml
@@ -7,38 +7,38 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.arm.vfp.valgrind.s1">
- <reg name="d0s1" bitsize="64" type="ieee_double"/>
- <reg name="d1s1" bitsize="64" type="ieee_double"/>
- <reg name="d2s1" bitsize="64" type="ieee_double"/>
- <reg name="d3s1" bitsize="64" type="ieee_double"/>
- <reg name="d4s1" bitsize="64" type="ieee_double"/>
- <reg name="d5s1" bitsize="64" type="ieee_double"/>
- <reg name="d6s1" bitsize="64" type="ieee_double"/>
- <reg name="d7s1" bitsize="64" type="ieee_double"/>
- <reg name="d8s1" bitsize="64" type="ieee_double"/>
- <reg name="d9s1" bitsize="64" type="ieee_double"/>
- <reg name="d10s1" bitsize="64" type="ieee_double"/>
- <reg name="d11s1" bitsize="64" type="ieee_double"/>
- <reg name="d12s1" bitsize="64" type="ieee_double"/>
- <reg name="d13s1" bitsize="64" type="ieee_double"/>
- <reg name="d14s1" bitsize="64" type="ieee_double"/>
- <reg name="d15s1" bitsize="64" type="ieee_double"/>
- <reg name="d16s1" bitsize="64" type="ieee_double"/>
- <reg name="d17s1" bitsize="64" type="ieee_double"/>
- <reg name="d18s1" bitsize="64" type="ieee_double"/>
- <reg name="d19s1" bitsize="64" type="ieee_double"/>
- <reg name="d20s1" bitsize="64" type="ieee_double"/>
- <reg name="d21s1" bitsize="64" type="ieee_double"/>
- <reg name="d22s1" bitsize="64" type="ieee_double"/>
- <reg name="d23s1" bitsize="64" type="ieee_double"/>
- <reg name="d24s1" bitsize="64" type="ieee_double"/>
- <reg name="d25s1" bitsize="64" type="ieee_double"/>
- <reg name="d26s1" bitsize="64" type="ieee_double"/>
- <reg name="d27s1" bitsize="64" type="ieee_double"/>
- <reg name="d28s1" bitsize="64" type="ieee_double"/>
- <reg name="d29s1" bitsize="64" type="ieee_double"/>
- <reg name="d30s1" bitsize="64" type="ieee_double"/>
- <reg name="d31s1" bitsize="64" type="ieee_double"/>
+ <reg name="d0s1" bitsize="64" type="uint64"/>
+ <reg name="d1s1" bitsize="64" type="uint64"/>
+ <reg name="d2s1" bitsize="64" type="uint64"/>
+ <reg name="d3s1" bitsize="64" type="uint64"/>
+ <reg name="d4s1" bitsize="64" type="uint64"/>
+ <reg name="d5s1" bitsize="64" type="uint64"/>
+ <reg name="d6s1" bitsize="64" type="uint64"/>
+ <reg name="d7s1" bitsize="64" type="uint64"/>
+ <reg name="d8s1" bitsize="64" type="uint64"/>
+ <reg name="d9s1" bitsize="64" type="uint64"/>
+ <reg name="d10s1" bitsize="64" type="uint64"/>
+ <reg name="d11s1" bitsize="64" type="uint64"/>
+ <reg name="d12s1" bitsize="64" type="uint64"/>
+ <reg name="d13s1" bitsize="64" type="uint64"/>
+ <reg name="d14s1" bitsize="64" type="uint64"/>
+ <reg name="d15s1" bitsize="64" type="uint64"/>
+ <reg name="d16s1" bitsize="64" type="uint64"/>
+ <reg name="d17s1" bitsize="64" type="uint64"/>
+ <reg name="d18s1" bitsize="64" type="uint64"/>
+ <reg name="d19s1" bitsize="64" type="uint64"/>
+ <reg name="d20s1" bitsize="64" type="uint64"/>
+ <reg name="d21s1" bitsize="64" type="uint64"/>
+ <reg name="d22s1" bitsize="64" type="uint64"/>
+ <reg name="d23s1" bitsize="64" type="uint64"/>
+ <reg name="d24s1" bitsize="64" type="uint64"/>
+ <reg name="d25s1" bitsize="64" type="uint64"/>
+ <reg name="d26s1" bitsize="64" type="uint64"/>
+ <reg name="d27s1" bitsize="64" type="uint64"/>
+ <reg name="d28s1" bitsize="64" type="uint64"/>
+ <reg name="d29s1" bitsize="64" type="uint64"/>
+ <reg name="d30s1" bitsize="64" type="uint64"/>
+ <reg name="d31s1" bitsize="64" type="uint64"/>
<reg name="fpscrs1" bitsize="32" type="int" group="float"/>
</feature>
diff --git a/main/coregrind/m_gdbserver/arm-vfpv3-valgrind-s2.xml b/main/coregrind/m_gdbserver/arm-vfpv3-valgrind-s2.xml
index c0e8677..9c0bc7a 100644
--- a/main/coregrind/m_gdbserver/arm-vfpv3-valgrind-s2.xml
+++ b/main/coregrind/m_gdbserver/arm-vfpv3-valgrind-s2.xml
@@ -7,38 +7,38 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.arm.vfp.valgrind.s2">
- <reg name="d0s2" bitsize="64" type="ieee_double"/>
- <reg name="d1s2" bitsize="64" type="ieee_double"/>
- <reg name="d2s2" bitsize="64" type="ieee_double"/>
- <reg name="d3s2" bitsize="64" type="ieee_double"/>
- <reg name="d4s2" bitsize="64" type="ieee_double"/>
- <reg name="d5s2" bitsize="64" type="ieee_double"/>
- <reg name="d6s2" bitsize="64" type="ieee_double"/>
- <reg name="d7s2" bitsize="64" type="ieee_double"/>
- <reg name="d8s2" bitsize="64" type="ieee_double"/>
- <reg name="d9s2" bitsize="64" type="ieee_double"/>
- <reg name="d10s2" bitsize="64" type="ieee_double"/>
- <reg name="d11s2" bitsize="64" type="ieee_double"/>
- <reg name="d12s2" bitsize="64" type="ieee_double"/>
- <reg name="d13s2" bitsize="64" type="ieee_double"/>
- <reg name="d14s2" bitsize="64" type="ieee_double"/>
- <reg name="d15s2" bitsize="64" type="ieee_double"/>
- <reg name="d16s2" bitsize="64" type="ieee_double"/>
- <reg name="d17s2" bitsize="64" type="ieee_double"/>
- <reg name="d18s2" bitsize="64" type="ieee_double"/>
- <reg name="d19s2" bitsize="64" type="ieee_double"/>
- <reg name="d20s2" bitsize="64" type="ieee_double"/>
- <reg name="d21s2" bitsize="64" type="ieee_double"/>
- <reg name="d22s2" bitsize="64" type="ieee_double"/>
- <reg name="d23s2" bitsize="64" type="ieee_double"/>
- <reg name="d24s2" bitsize="64" type="ieee_double"/>
- <reg name="d25s2" bitsize="64" type="ieee_double"/>
- <reg name="d26s2" bitsize="64" type="ieee_double"/>
- <reg name="d27s2" bitsize="64" type="ieee_double"/>
- <reg name="d28s2" bitsize="64" type="ieee_double"/>
- <reg name="d29s2" bitsize="64" type="ieee_double"/>
- <reg name="d30s2" bitsize="64" type="ieee_double"/>
- <reg name="d31s2" bitsize="64" type="ieee_double"/>
+ <reg name="d0s2" bitsize="64" type="uint64"/>
+ <reg name="d1s2" bitsize="64" type="uint64"/>
+ <reg name="d2s2" bitsize="64" type="uint64"/>
+ <reg name="d3s2" bitsize="64" type="uint64"/>
+ <reg name="d4s2" bitsize="64" type="uint64"/>
+ <reg name="d5s2" bitsize="64" type="uint64"/>
+ <reg name="d6s2" bitsize="64" type="uint64"/>
+ <reg name="d7s2" bitsize="64" type="uint64"/>
+ <reg name="d8s2" bitsize="64" type="uint64"/>
+ <reg name="d9s2" bitsize="64" type="uint64"/>
+ <reg name="d10s2" bitsize="64" type="uint64"/>
+ <reg name="d11s2" bitsize="64" type="uint64"/>
+ <reg name="d12s2" bitsize="64" type="uint64"/>
+ <reg name="d13s2" bitsize="64" type="uint64"/>
+ <reg name="d14s2" bitsize="64" type="uint64"/>
+ <reg name="d15s2" bitsize="64" type="uint64"/>
+ <reg name="d16s2" bitsize="64" type="uint64"/>
+ <reg name="d17s2" bitsize="64" type="uint64"/>
+ <reg name="d18s2" bitsize="64" type="uint64"/>
+ <reg name="d19s2" bitsize="64" type="uint64"/>
+ <reg name="d20s2" bitsize="64" type="uint64"/>
+ <reg name="d21s2" bitsize="64" type="uint64"/>
+ <reg name="d22s2" bitsize="64" type="uint64"/>
+ <reg name="d23s2" bitsize="64" type="uint64"/>
+ <reg name="d24s2" bitsize="64" type="uint64"/>
+ <reg name="d25s2" bitsize="64" type="uint64"/>
+ <reg name="d26s2" bitsize="64" type="uint64"/>
+ <reg name="d27s2" bitsize="64" type="uint64"/>
+ <reg name="d28s2" bitsize="64" type="uint64"/>
+ <reg name="d29s2" bitsize="64" type="uint64"/>
+ <reg name="d30s2" bitsize="64" type="uint64"/>
+ <reg name="d31s2" bitsize="64" type="uint64"/>
<reg name="fpscrs2" bitsize="32" type="int" group="float"/>
</feature>
diff --git a/main/coregrind/m_gdbserver/m_gdbserver.c b/main/coregrind/m_gdbserver/m_gdbserver.c
index 6a0a196..bdc0b4c 100644
--- a/main/coregrind/m_gdbserver/m_gdbserver.c
+++ b/main/coregrind/m_gdbserver/m_gdbserver.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2011 Philippe Waroquiers
+ Copyright (C) 2011-2012 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -39,9 +39,11 @@
#include "pub_core_threadstate.h"
#include "pub_core_transtab.h"
#include "pub_tool_hashtable.h"
+#include "pub_tool_xarray.h"
#include "pub_core_libcassert.h"
#include "pub_tool_libcbase.h"
#include "pub_core_libcsignal.h"
+#include "pub_core_signals.h"
#include "pub_tool_machine.h" // VG_(fnptr_to_fnentry)
#include "pub_tool_debuginfo.h"
#include "pub_core_scheduler.h"
@@ -129,13 +131,6 @@
static void call_gdbserver ( ThreadId tid , CallReason reason);
-/* convert from CORE_ADDR to void* */
-static
-void* C2v(CORE_ADDR addr)
-{
- return (void*) addr;
-}
-
/* Describes the address addr (for debugging/printing purposes).
Last two results are kept. A third call will replace the
oldest result. */
@@ -145,6 +140,7 @@
static int w = 0;
PtrdiffT offset;
if (w == 2) w = 0;
+ buf[w][0] = '\0';
if (is_code) {
VG_(describe_IP) (addr, buf[w], 200);
} else {
@@ -158,6 +154,18 @@
static int gdbserver_called = 0;
static int gdbserver_exited = 0;
+/* alloc and free functions for xarray and similar. */
+static void* gs_alloc (HChar* cc, SizeT sz)
+{
+ void* res = VG_(arena_malloc)(VG_AR_CORE, cc, sz);
+ vg_assert (res);
+ return res;
+}
+static void gs_free (void* ptr)
+{
+ VG_(arena_free)(VG_AR_CORE, ptr);
+}
+
typedef
enum {
GS_break,
@@ -227,21 +235,52 @@
case write_watchpoint: return "write_watchpoint";
case read_watchpoint: return "read_watchpoint";
case access_watchpoint: return "access_watchpoint";
- default: vg_assert(0);
+ default: return "???wrong PointKind";
}
}
typedef
struct _GS_Watch {
- struct _GS_Watch* next;
Addr addr;
SizeT len;
PointKind kind;
}
GS_Watch;
-/* gs_watches contains a list of all addresses+len that are being watched. */
-static VgHashTable gs_watches = NULL;
+/* gs_watches contains a list of all addresses+len+kind that are being
+ watched. */
+static XArray* gs_watches = NULL;
+
+static inline GS_Watch* index_gs_watches(Word i)
+{
+ return *(GS_Watch **) VG_(indexXA) (gs_watches, i);
+}
+
+/* Returns the GS_Watch matching addr/len/kind and sets *g_ix to its
+ position in gs_watches.
+ If no matching GS_Watch is found, returns NULL and sets g_ix to -1. */
+static GS_Watch* lookup_gs_watch (Addr addr, SizeT len, PointKind kind,
+ Word* g_ix)
+{
+ const Word n_elems = VG_(sizeXA) (gs_watches);
+ Word i;
+ GS_Watch *g;
+
+ /* Linear search. If we have many watches, this might be optimised
+ by having the array sorted and using VG_(lookupXA) */
+ for (i = 0; i < n_elems; i++) {
+ g = index_gs_watches(i);
+ if (g->addr == addr && g->len == len && g->kind == kind) {
+ // Found.
+ *g_ix = i;
+ return g;
+ }
+ }
+
+ // Not found.
+ *g_ix = -1;
+ return NULL;
+}
/* protocol spec tells the below must be idempotent. */
@@ -296,6 +335,7 @@
{
Bool res;
GS_Watch *g;
+ Word g_ix;
Bool is_code = kind == software_breakpoint || kind == hardware_breakpoint;
dlog(1, "%s %s at addr %p %s\n",
@@ -320,7 +360,10 @@
if (!res)
return False; /* error or unsupported */
- g = VG_(HT_lookup) (gs_watches, (UWord)addr);
+ // Protocol says insert/remove must be idempotent.
+ // So, we just ignore double insert or (supposed) double delete.
+
+ g = lookup_gs_watch (addr, len, kind, &g_ix);
if (insert) {
if (g == NULL) {
g = VG_(arena_malloc)(VG_AR_CORE, "gdbserver_point watchpoint",
@@ -328,27 +371,38 @@
g->addr = addr;
g->len = len;
g->kind = kind;
- VG_(HT_add_node)(gs_watches, g);
+ VG_(addToXA)(gs_watches, &g);
} else {
- g->kind = kind;
+ dlog(1,
+ "VG_(gdbserver_point) addr %p len %d kind %s already inserted\n",
+ C2v(addr), len, VG_(ppPointKind) (kind));
}
} else {
- vg_assert (g != NULL);
- VG_(HT_remove) (gs_watches, g->addr);
- VG_(arena_free) (VG_AR_CORE, g);
+ if (g != NULL) {
+ VG_(removeIndexXA) (gs_watches, g_ix);
+ VG_(arena_free) (VG_AR_CORE, g);
+ } else {
+ dlog(1,
+ "VG_(gdbserver_point) addr %p len %d kind %s already deleted?\n",
+ C2v(addr), len, VG_(ppPointKind) (kind));
+ }
}
return True;
}
Bool VG_(is_watched)(PointKind kind, Addr addr, Int szB)
{
+ Word n_elems;
GS_Watch* g;
+ Word i;
Bool watched = False;
const ThreadId tid = VG_(running_tid);
if (!gdbserver_called)
return False;
+ n_elems = VG_(sizeXA) (gs_watches);
+
Addr to = addr + szB; // semi-open interval [addr, to[
vg_assert (kind == access_watchpoint
@@ -356,8 +410,9 @@
|| kind == write_watchpoint);
dlog(1, "tid %d VG_(is_watched) %s addr %p szB %d\n",
tid, VG_(ppPointKind) (kind), C2v(addr), szB);
- VG_(HT_ResetIter) (gs_watches);
- while ((g = VG_(HT_Next) (gs_watches))) {
+
+ for (i = 0; i < n_elems; i++) {
+ g = index_gs_watches(i);
switch (g->kind) {
case software_breakpoint:
case hardware_breakpoint:
@@ -479,26 +534,29 @@
VG_(free) (ag);
}
-// Clear watched addressed in gs_watches
+// Clear watched addressed in gs_watches, delete gs_watches.
static void clear_watched_addresses(void)
{
- GS_Watch** ag;
- UInt n_elems;
- int i;
+ GS_Watch* g;
+ const Word n_elems = VG_(sizeXA) (gs_watches);
+ Word i;
dlog(1,
- "clear_watched_addresses: scanning hash table nodes %d\n",
- VG_(HT_count_nodes) (gs_watches));
- ag = (GS_Watch**) VG_(HT_to_array) (gs_watches, &n_elems);
+ "clear_watched_addresses: %ld elements\n",
+ n_elems);
+
for (i = 0; i < n_elems; i++) {
- if (!VG_(gdbserver_point) (ag[i]->kind,
+ g = index_gs_watches(i);
+ if (!VG_(gdbserver_point) (g->kind,
/* insert */ False,
- ag[i]->addr,
- ag[i]->len)) {
+ g->addr,
+ g->len)) {
vg_assert (0);
}
}
- VG_(free) (ag);
+
+ VG_(deleteXA) (gs_watches);
+ gs_watches = NULL;
}
static void invalidate_if_jump_not_yet_gdbserved (Addr addr, char* from)
@@ -549,11 +607,9 @@
vg_assert (gs_addresses != NULL);
vg_assert (gs_watches != NULL);
clear_gdbserved_addresses(/* clear only jumps */ False);
- VG_(HT_destruct) (gs_addresses);
+ VG_(HT_destruct) (gs_addresses, VG_(free));
gs_addresses = NULL;
clear_watched_addresses();
- VG_(HT_destruct) (gs_watches);
- gs_watches = NULL;
} else {
vg_assert (gs_addresses == NULL);
vg_assert (gs_watches == NULL);
@@ -598,7 +654,10 @@
vg_assert (gs_addresses == NULL);
vg_assert (gs_watches == NULL);
gs_addresses = VG_(HT_construct)( "gdbserved_addresses" );
- gs_watches = VG_(HT_construct)( "gdbserved_watches" );
+ gs_watches = VG_(newXA)(gs_alloc,
+ "gdbserved_watches",
+ gs_free,
+ sizeof(GS_Watch*));
VG_(atfork)(NULL, NULL, gdbserver_cleanup_in_child_after_fork);
}
vg_assert (gs_addresses != NULL);
@@ -835,9 +894,14 @@
return ret;
}
-Bool VG_(gdbserver_report_signal) (Int sigNo, ThreadId tid)
+Bool VG_(gdbserver_report_signal) (Int vki_sigNo, ThreadId tid)
{
- dlog(1, "signal %d tid %d\n", sigNo, tid);
+ dlog(1, "VG core calling VG_(gdbserver_report_signal) "
+ "vki_nr %d %s gdb_nr %d %s tid %d\n",
+ vki_sigNo, VG_(signame)(vki_sigNo),
+ target_signal_from_host (vki_sigNo),
+ target_signal_to_name(target_signal_from_host (vki_sigNo)),
+ tid);
/* if gdbserver is currently not connected, then signal
is to be given to the process */
@@ -848,19 +912,19 @@
/* if gdb has informed gdbserver that this signal can be
passed directly without informing gdb, then signal is
to be given to the process. */
- if (pass_signals[sigNo]) {
+ if (pass_signals[target_signal_from_host(vki_sigNo)]) {
dlog(1, "pass_signals => pass\n");
return True;
}
/* indicate to gdbserver that there is a signal */
- gdbserver_signal_encountered (sigNo);
+ gdbserver_signal_encountered (vki_sigNo);
/* let gdbserver do some work, e.g. show the signal to the user */
call_gdbserver (tid, signal_reason);
/* ask gdbserver what is the final decision */
- if (gdbserver_deliver_signal (sigNo)) {
+ if (gdbserver_deliver_signal (vki_sigNo)) {
dlog(1, "gdbserver deliver signal\n");
return True;
} else {
@@ -1023,12 +1087,16 @@
gdb interactions. */
di->nFxState = 2;
- di->fxState[0].fx = Ifx_Read;
- di->fxState[0].offset = layout->offset_SP;
- di->fxState[0].size = layout->sizeof_SP;
- di->fxState[1].fx = Ifx_Modify;
- di->fxState[1].offset = layout->offset_IP;
- di->fxState[1].size = layout->sizeof_IP;
+ di->fxState[0].fx = Ifx_Read;
+ di->fxState[0].offset = layout->offset_SP;
+ di->fxState[0].size = layout->sizeof_SP;
+ di->fxState[0].nRepeats = 0;
+ di->fxState[0].repeatLen = 0;
+ di->fxState[1].fx = Ifx_Modify;
+ di->fxState[1].offset = layout->offset_IP;
+ di->fxState[1].size = layout->sizeof_IP;
+ di->fxState[1].nRepeats = 0;
+ di->fxState[1].repeatLen = 0;
addStmtToIRSB(irsb, IRStmt_Dirty(di));
@@ -1323,7 +1391,7 @@
const int nr_gdbserved_addresses
= (gs_addresses == NULL ? -1 : VG_(HT_count_nodes) (gs_addresses));
const int nr_watchpoints
- = (gs_watches == NULL ? -1 : VG_(HT_count_nodes) (gs_watches));
+ = (gs_watches == NULL ? -1 : (int) VG_(sizeXA) (gs_watches));
remote_utils_output_status();
VG_(umsg)
("nr of calls to gdbserver: %d\n"
diff --git a/main/coregrind/m_gdbserver/mips-cp0-valgrind-s1.xml b/main/coregrind/m_gdbserver/mips-cp0-valgrind-s1.xml
new file mode 100644
index 0000000..b775194
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-cp0-valgrind-s1.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.mips.cp0.valgrind.s1">
+ <reg name="statuss1" bitsize="32" regnum="32"/>
+ <reg name="badvaddrs1" bitsize="32" regnum="35"/>
+ <reg name="causes1" bitsize="32" regnum="36"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/mips-cp0-valgrind-s2.xml b/main/coregrind/m_gdbserver/mips-cp0-valgrind-s2.xml
new file mode 100644
index 0000000..fc57afa
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-cp0-valgrind-s2.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.mips.cp0.valgrind.s2">
+ <reg name="statuss2" bitsize="32" regnum="32"/>
+ <reg name="badvaddrs2" bitsize="32" regnum="35"/>
+ <reg name="causes2" bitsize="32" regnum="36"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/mips-cp0.xml b/main/coregrind/m_gdbserver/mips-cp0.xml
new file mode 100644
index 0000000..2555b1d
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-cp0.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.mips.cp0">
+ <reg name="status" bitsize="32" regnum="32"/>
+ <reg name="badvaddr" bitsize="32" regnum="35"/>
+ <reg name="cause" bitsize="32" regnum="36"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/mips-cpu-valgrind-s1.xml b/main/coregrind/m_gdbserver/mips-cpu-valgrind-s1.xml
new file mode 100644
index 0000000..3404b43
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-cpu-valgrind-s1.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.mips.cpu.valgrind.s1">
+ <reg name="r0s1" bitsize="32" regnum="0"/>
+ <reg name="r1s1" bitsize="32"/>
+ <reg name="r2s1" bitsize="32"/>
+ <reg name="r3s1" bitsize="32"/>
+ <reg name="r4s1" bitsize="32"/>
+ <reg name="r5s1" bitsize="32"/>
+ <reg name="r6s1" bitsize="32"/>
+ <reg name="r7s1" bitsize="32"/>
+ <reg name="r8s1" bitsize="32"/>
+ <reg name="r9s1" bitsize="32"/>
+ <reg name="r10s1" bitsize="32"/>
+ <reg name="r11s1" bitsize="32"/>
+ <reg name="r12s1" bitsize="32"/>
+ <reg name="r13s1" bitsize="32"/>
+ <reg name="r14s1" bitsize="32"/>
+ <reg name="r15s1" bitsize="32"/>
+ <reg name="r16s1" bitsize="32"/>
+ <reg name="r17s1" bitsize="32"/>
+ <reg name="r18s1" bitsize="32"/>
+ <reg name="r19s1" bitsize="32"/>
+ <reg name="r20s1" bitsize="32"/>
+ <reg name="r21s1" bitsize="32"/>
+ <reg name="r22s1" bitsize="32"/>
+ <reg name="r23s1" bitsize="32"/>
+ <reg name="r24s1" bitsize="32"/>
+ <reg name="r25s1" bitsize="32"/>
+ <reg name="r26s1" bitsize="32"/>
+ <reg name="r27s1" bitsize="32"/>
+ <reg name="r28s1" bitsize="32"/>
+ <reg name="r29s1" bitsize="32"/>
+ <reg name="r30s1" bitsize="32"/>
+ <reg name="r31s1" bitsize="32"/>
+
+ <reg name="los1" bitsize="32" regnum="33"/>
+ <reg name="his1" bitsize="32" regnum="34"/>
+ <reg name="pcs1" bitsize="32" regnum="37"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/mips-cpu-valgrind-s2.xml b/main/coregrind/m_gdbserver/mips-cpu-valgrind-s2.xml
new file mode 100644
index 0000000..13b1640
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-cpu-valgrind-s2.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.mips.cpu.valgrind.s2">
+ <reg name="r0s2" bitsize="32" regnum="0"/>
+ <reg name="r1s2" bitsize="32"/>
+ <reg name="r2s2" bitsize="32"/>
+ <reg name="r3s2" bitsize="32"/>
+ <reg name="r4s2" bitsize="32"/>
+ <reg name="r5s2" bitsize="32"/>
+ <reg name="r6s2" bitsize="32"/>
+ <reg name="r7s2" bitsize="32"/>
+ <reg name="r8s2" bitsize="32"/>
+ <reg name="r9s2" bitsize="32"/>
+ <reg name="r10s2" bitsize="32"/>
+ <reg name="r11s2" bitsize="32"/>
+ <reg name="r12s2" bitsize="32"/>
+ <reg name="r13s2" bitsize="32"/>
+ <reg name="r14s2" bitsize="32"/>
+ <reg name="r15s2" bitsize="32"/>
+ <reg name="r16s2" bitsize="32"/>
+ <reg name="r17s2" bitsize="32"/>
+ <reg name="r18s2" bitsize="32"/>
+ <reg name="r19s2" bitsize="32"/>
+ <reg name="r20s2" bitsize="32"/>
+ <reg name="r21s2" bitsize="32"/>
+ <reg name="r22s2" bitsize="32"/>
+ <reg name="r23s2" bitsize="32"/>
+ <reg name="r24s2" bitsize="32"/>
+ <reg name="r25s2" bitsize="32"/>
+ <reg name="r26s2" bitsize="32"/>
+ <reg name="r27s2" bitsize="32"/>
+ <reg name="r28s2" bitsize="32"/>
+ <reg name="r29s2" bitsize="32"/>
+ <reg name="r30s2" bitsize="32"/>
+ <reg name="r31s2" bitsize="32"/>
+
+ <reg name="los2" bitsize="32" regnum="33"/>
+ <reg name="his2" bitsize="32" regnum="34"/>
+ <reg name="pcs2" bitsize="32" regnum="37"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/mips-cpu.xml b/main/coregrind/m_gdbserver/mips-cpu.xml
new file mode 100644
index 0000000..62bfe03
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-cpu.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.mips.cpu">
+ <reg name="r0" bitsize="32" regnum="0"/>
+ <reg name="r1" bitsize="32"/>
+ <reg name="r2" bitsize="32"/>
+ <reg name="r3" bitsize="32"/>
+ <reg name="r4" bitsize="32"/>
+ <reg name="r5" bitsize="32"/>
+ <reg name="r6" bitsize="32"/>
+ <reg name="r7" bitsize="32"/>
+ <reg name="r8" bitsize="32"/>
+ <reg name="r9" bitsize="32"/>
+ <reg name="r10" bitsize="32"/>
+ <reg name="r11" bitsize="32"/>
+ <reg name="r12" bitsize="32"/>
+ <reg name="r13" bitsize="32"/>
+ <reg name="r14" bitsize="32"/>
+ <reg name="r15" bitsize="32"/>
+ <reg name="r16" bitsize="32"/>
+ <reg name="r17" bitsize="32"/>
+ <reg name="r18" bitsize="32"/>
+ <reg name="r19" bitsize="32"/>
+ <reg name="r20" bitsize="32"/>
+ <reg name="r21" bitsize="32"/>
+ <reg name="r22" bitsize="32"/>
+ <reg name="r23" bitsize="32"/>
+ <reg name="r24" bitsize="32"/>
+ <reg name="r25" bitsize="32"/>
+ <reg name="r26" bitsize="32"/>
+ <reg name="r27" bitsize="32"/>
+ <reg name="r28" bitsize="32"/>
+ <reg name="r29" bitsize="32"/>
+ <reg name="r30" bitsize="32"/>
+ <reg name="r31" bitsize="32"/>
+
+ <reg name="lo" bitsize="32" regnum="33"/>
+ <reg name="hi" bitsize="32" regnum="34"/>
+ <reg name="pc" bitsize="32" regnum="37"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/mips-fpu-valgrind-s1.xml b/main/coregrind/m_gdbserver/mips-fpu-valgrind-s1.xml
new file mode 100644
index 0000000..3c84e9d
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-fpu-valgrind-s1.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.mips.fpu.valgrind.s1">
+ <reg name="f0s1" bitsize="32" type="ieee_single" regnum="38"/>
+ <reg name="f1s1" bitsize="32" type="ieee_single"/>
+ <reg name="f2s1" bitsize="32" type="ieee_single"/>
+ <reg name="f3s1" bitsize="32" type="ieee_single"/>
+ <reg name="f4s1" bitsize="32" type="ieee_single"/>
+ <reg name="f5s1" bitsize="32" type="ieee_single"/>
+ <reg name="f6s1" bitsize="32" type="ieee_single"/>
+ <reg name="f7s1" bitsize="32" type="ieee_single"/>
+ <reg name="f8s1" bitsize="32" type="ieee_single"/>
+ <reg name="f9s1" bitsize="32" type="ieee_single"/>
+ <reg name="f10s1" bitsize="32" type="ieee_single"/>
+ <reg name="f11s1" bitsize="32" type="ieee_single"/>
+ <reg name="f12s1" bitsize="32" type="ieee_single"/>
+ <reg name="f13s1" bitsize="32" type="ieee_single"/>
+ <reg name="f14s1" bitsize="32" type="ieee_single"/>
+ <reg name="f15s1" bitsize="32" type="ieee_single"/>
+ <reg name="f16s1" bitsize="32" type="ieee_single"/>
+ <reg name="f17s1" bitsize="32" type="ieee_single"/>
+ <reg name="f18s1" bitsize="32" type="ieee_single"/>
+ <reg name="f19s1" bitsize="32" type="ieee_single"/>
+ <reg name="f20s1" bitsize="32" type="ieee_single"/>
+ <reg name="f21s1" bitsize="32" type="ieee_single"/>
+ <reg name="f22s1" bitsize="32" type="ieee_single"/>
+ <reg name="f23s1" bitsize="32" type="ieee_single"/>
+ <reg name="f24s1" bitsize="32" type="ieee_single"/>
+ <reg name="f25s1" bitsize="32" type="ieee_single"/>
+ <reg name="f26s1" bitsize="32" type="ieee_single"/>
+ <reg name="f27s1" bitsize="32" type="ieee_single"/>
+ <reg name="f28s1" bitsize="32" type="ieee_single"/>
+ <reg name="f29s1" bitsize="32" type="ieee_single"/>
+ <reg name="f30s1" bitsize="32" type="ieee_single"/>
+ <reg name="f31s1" bitsize="32" type="ieee_single"/>
+
+ <reg name="fcsrs1" bitsize="32" group="float"/>
+ <reg name="firs1" bitsize="32" group="float"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/mips-fpu-valgrind-s2.xml b/main/coregrind/m_gdbserver/mips-fpu-valgrind-s2.xml
new file mode 100644
index 0000000..3a50143
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-fpu-valgrind-s2.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.mips.fpu.valgrind.s2">
+ <reg name="f0s2" bitsize="32" type="ieee_single" regnum="38"/>
+ <reg name="f1s2" bitsize="32" type="ieee_single"/>
+ <reg name="f2s2" bitsize="32" type="ieee_single"/>
+ <reg name="f3s2" bitsize="32" type="ieee_single"/>
+ <reg name="f4s2" bitsize="32" type="ieee_single"/>
+ <reg name="f5s2" bitsize="32" type="ieee_single"/>
+ <reg name="f6s2" bitsize="32" type="ieee_single"/>
+ <reg name="f7s2" bitsize="32" type="ieee_single"/>
+ <reg name="f8s2" bitsize="32" type="ieee_single"/>
+ <reg name="f9s2" bitsize="32" type="ieee_single"/>
+ <reg name="f10s2" bitsize="32" type="ieee_single"/>
+ <reg name="f11s2" bitsize="32" type="ieee_single"/>
+ <reg name="f12s2" bitsize="32" type="ieee_single"/>
+ <reg name="f13s2" bitsize="32" type="ieee_single"/>
+ <reg name="f14s2" bitsize="32" type="ieee_single"/>
+ <reg name="f15s2" bitsize="32" type="ieee_single"/>
+ <reg name="f16s2" bitsize="32" type="ieee_single"/>
+ <reg name="f17s2" bitsize="32" type="ieee_single"/>
+ <reg name="f18s2" bitsize="32" type="ieee_single"/>
+ <reg name="f19s2" bitsize="32" type="ieee_single"/>
+ <reg name="f20s2" bitsize="32" type="ieee_single"/>
+ <reg name="f21s2" bitsize="32" type="ieee_single"/>
+ <reg name="f22s2" bitsize="32" type="ieee_single"/>
+ <reg name="f23s2" bitsize="32" type="ieee_single"/>
+ <reg name="f24s2" bitsize="32" type="ieee_single"/>
+ <reg name="f25s2" bitsize="32" type="ieee_single"/>
+ <reg name="f26s2" bitsize="32" type="ieee_single"/>
+ <reg name="f27s2" bitsize="32" type="ieee_single"/>
+ <reg name="f28s2" bitsize="32" type="ieee_single"/>
+ <reg name="f29s2" bitsize="32" type="ieee_single"/>
+ <reg name="f30s2" bitsize="32" type="ieee_single"/>
+ <reg name="f31s2" bitsize="32" type="ieee_single"/>
+
+ <reg name="fcsrs2" bitsize="32" group="float"/>
+ <reg name="firs2" bitsize="32" group="float"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/mips-fpu.xml b/main/coregrind/m_gdbserver/mips-fpu.xml
new file mode 100644
index 0000000..fc371c6
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-fpu.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.mips.fpu">
+ <reg name="f0" bitsize="32" type="ieee_single" regnum="38"/>
+ <reg name="f1" bitsize="32" type="ieee_single"/>
+ <reg name="f2" bitsize="32" type="ieee_single"/>
+ <reg name="f3" bitsize="32" type="ieee_single"/>
+ <reg name="f4" bitsize="32" type="ieee_single"/>
+ <reg name="f5" bitsize="32" type="ieee_single"/>
+ <reg name="f6" bitsize="32" type="ieee_single"/>
+ <reg name="f7" bitsize="32" type="ieee_single"/>
+ <reg name="f8" bitsize="32" type="ieee_single"/>
+ <reg name="f9" bitsize="32" type="ieee_single"/>
+ <reg name="f10" bitsize="32" type="ieee_single"/>
+ <reg name="f11" bitsize="32" type="ieee_single"/>
+ <reg name="f12" bitsize="32" type="ieee_single"/>
+ <reg name="f13" bitsize="32" type="ieee_single"/>
+ <reg name="f14" bitsize="32" type="ieee_single"/>
+ <reg name="f15" bitsize="32" type="ieee_single"/>
+ <reg name="f16" bitsize="32" type="ieee_single"/>
+ <reg name="f17" bitsize="32" type="ieee_single"/>
+ <reg name="f18" bitsize="32" type="ieee_single"/>
+ <reg name="f19" bitsize="32" type="ieee_single"/>
+ <reg name="f20" bitsize="32" type="ieee_single"/>
+ <reg name="f21" bitsize="32" type="ieee_single"/>
+ <reg name="f22" bitsize="32" type="ieee_single"/>
+ <reg name="f23" bitsize="32" type="ieee_single"/>
+ <reg name="f24" bitsize="32" type="ieee_single"/>
+ <reg name="f25" bitsize="32" type="ieee_single"/>
+ <reg name="f26" bitsize="32" type="ieee_single"/>
+ <reg name="f27" bitsize="32" type="ieee_single"/>
+ <reg name="f28" bitsize="32" type="ieee_single"/>
+ <reg name="f29" bitsize="32" type="ieee_single"/>
+ <reg name="f30" bitsize="32" type="ieee_single"/>
+ <reg name="f31" bitsize="32" type="ieee_single"/>
+
+ <reg name="fcsr" bitsize="32" group="float"/>
+ <reg name="fir" bitsize="32" group="float"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/mips-linux-valgrind.xml b/main/coregrind/m_gdbserver/mips-linux-valgrind.xml
new file mode 100644
index 0000000..b18c623
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-linux-valgrind.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>mips</architecture>
+ <osabi>GNU/Linux</osabi>
+ <xi:include href="mips-cpu.xml"/>
+ <xi:include href="mips-cp0.xml"/>
+ <xi:include href="mips-fpu.xml"/>
+ <xi:include href="mips-cpu-valgrind-s1.xml"/>
+ <xi:include href="mips-cp0-valgrind-s1.xml"/>
+ <xi:include href="mips-fpu-valgrind-s1.xml"/>
+ <xi:include href="mips-cpu-valgrind-s2.xml"/>
+ <xi:include href="mips-cp0-valgrind-s2.xml"/>
+ <xi:include href="mips-fpu-valgrind-s2.xml"/>
+
+ <feature name="org.gnu.gdb.mips.linux">
+ <reg name="restart" bitsize="32" group="system"/>
+ </feature>
+</target>
diff --git a/main/coregrind/m_gdbserver/mips-linux.xml b/main/coregrind/m_gdbserver/mips-linux.xml
new file mode 100644
index 0000000..73fb432
--- /dev/null
+++ b/main/coregrind/m_gdbserver/mips-linux.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>mips</architecture>
+ <osabi>GNU/Linux</osabi>
+ <xi:include href="mips-cpu.xml"/>
+ <xi:include href="mips-cp0.xml"/>
+ <xi:include href="mips-fpu.xml"/>
+
+ <feature name="org.gnu.gdb.mips.linux">
+ <reg name="restart" bitsize="32" group="system"/>
+ </feature>
+</target>
diff --git a/main/coregrind/m_gdbserver/power-core-valgrind-s1.xml b/main/coregrind/m_gdbserver/power-core-valgrind-s1.xml
new file mode 100644
index 0000000..b667df8
--- /dev/null
+++ b/main/coregrind/m_gdbserver/power-core-valgrind-s1.xml
@@ -0,0 +1,49 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.core-valgrind-s1">
+ <reg name="r0s1" bitsize="32" type="uint32"/>
+ <reg name="r1s1" bitsize="32" type="uint32"/>
+ <reg name="r2s1" bitsize="32" type="uint32"/>
+ <reg name="r3s1" bitsize="32" type="uint32"/>
+ <reg name="r4s1" bitsize="32" type="uint32"/>
+ <reg name="r5s1" bitsize="32" type="uint32"/>
+ <reg name="r6s1" bitsize="32" type="uint32"/>
+ <reg name="r7s1" bitsize="32" type="uint32"/>
+ <reg name="r8s1" bitsize="32" type="uint32"/>
+ <reg name="r9s1" bitsize="32" type="uint32"/>
+ <reg name="r10s1" bitsize="32" type="uint32"/>
+ <reg name="r11s1" bitsize="32" type="uint32"/>
+ <reg name="r12s1" bitsize="32" type="uint32"/>
+ <reg name="r13s1" bitsize="32" type="uint32"/>
+ <reg name="r14s1" bitsize="32" type="uint32"/>
+ <reg name="r15s1" bitsize="32" type="uint32"/>
+ <reg name="r16s1" bitsize="32" type="uint32"/>
+ <reg name="r17s1" bitsize="32" type="uint32"/>
+ <reg name="r18s1" bitsize="32" type="uint32"/>
+ <reg name="r19s1" bitsize="32" type="uint32"/>
+ <reg name="r20s1" bitsize="32" type="uint32"/>
+ <reg name="r21s1" bitsize="32" type="uint32"/>
+ <reg name="r22s1" bitsize="32" type="uint32"/>
+ <reg name="r23s1" bitsize="32" type="uint32"/>
+ <reg name="r24s1" bitsize="32" type="uint32"/>
+ <reg name="r25s1" bitsize="32" type="uint32"/>
+ <reg name="r26s1" bitsize="32" type="uint32"/>
+ <reg name="r27s1" bitsize="32" type="uint32"/>
+ <reg name="r28s1" bitsize="32" type="uint32"/>
+ <reg name="r29s1" bitsize="32" type="uint32"/>
+ <reg name="r30s1" bitsize="32" type="uint32"/>
+ <reg name="r31s1" bitsize="32" type="uint32"/>
+
+ <reg name="pcs1" bitsize="32" type="code_ptr" regnum="64"/>
+ <reg name="msrs1" bitsize="32" type="uint32"/>
+ <reg name="crs1" bitsize="32" type="uint32"/>
+ <reg name="lrs1" bitsize="32" type="code_ptr"/>
+ <reg name="ctrs1" bitsize="32" type="uint32"/>
+ <reg name="xers1" bitsize="32" type="uint32"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/power-core-valgrind-s2.xml b/main/coregrind/m_gdbserver/power-core-valgrind-s2.xml
new file mode 100644
index 0000000..c361117
--- /dev/null
+++ b/main/coregrind/m_gdbserver/power-core-valgrind-s2.xml
@@ -0,0 +1,49 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.core-valgrind-s2">
+ <reg name="r0s2" bitsize="32" type="uint32"/>
+ <reg name="r1s2" bitsize="32" type="uint32"/>
+ <reg name="r2s2" bitsize="32" type="uint32"/>
+ <reg name="r3s2" bitsize="32" type="uint32"/>
+ <reg name="r4s2" bitsize="32" type="uint32"/>
+ <reg name="r5s2" bitsize="32" type="uint32"/>
+ <reg name="r6s2" bitsize="32" type="uint32"/>
+ <reg name="r7s2" bitsize="32" type="uint32"/>
+ <reg name="r8s2" bitsize="32" type="uint32"/>
+ <reg name="r9s2" bitsize="32" type="uint32"/>
+ <reg name="r10s2" bitsize="32" type="uint32"/>
+ <reg name="r11s2" bitsize="32" type="uint32"/>
+ <reg name="r12s2" bitsize="32" type="uint32"/>
+ <reg name="r13s2" bitsize="32" type="uint32"/>
+ <reg name="r14s2" bitsize="32" type="uint32"/>
+ <reg name="r15s2" bitsize="32" type="uint32"/>
+ <reg name="r16s2" bitsize="32" type="uint32"/>
+ <reg name="r17s2" bitsize="32" type="uint32"/>
+ <reg name="r18s2" bitsize="32" type="uint32"/>
+ <reg name="r19s2" bitsize="32" type="uint32"/>
+ <reg name="r20s2" bitsize="32" type="uint32"/>
+ <reg name="r21s2" bitsize="32" type="uint32"/>
+ <reg name="r22s2" bitsize="32" type="uint32"/>
+ <reg name="r23s2" bitsize="32" type="uint32"/>
+ <reg name="r24s2" bitsize="32" type="uint32"/>
+ <reg name="r25s2" bitsize="32" type="uint32"/>
+ <reg name="r26s2" bitsize="32" type="uint32"/>
+ <reg name="r27s2" bitsize="32" type="uint32"/>
+ <reg name="r28s2" bitsize="32" type="uint32"/>
+ <reg name="r29s2" bitsize="32" type="uint32"/>
+ <reg name="r30s2" bitsize="32" type="uint32"/>
+ <reg name="r31s2" bitsize="32" type="uint32"/>
+
+ <reg name="pcs2" bitsize="32" type="code_ptr" regnum="64"/>
+ <reg name="msrs2" bitsize="32" type="uint32"/>
+ <reg name="crs2" bitsize="32" type="uint32"/>
+ <reg name="lrs2" bitsize="32" type="code_ptr"/>
+ <reg name="ctrs2" bitsize="32" type="uint32"/>
+ <reg name="xers2" bitsize="32" type="uint32"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/power-fpu-valgrind-s1.xml b/main/coregrind/m_gdbserver/power-fpu-valgrind-s1.xml
index 01b852e..00d9108 100644
--- a/main/coregrind/m_gdbserver/power-fpu-valgrind-s1.xml
+++ b/main/coregrind/m_gdbserver/power-fpu-valgrind-s1.xml
@@ -7,38 +7,38 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.power.fpu-valgrind-s1">
- <reg name="f0s1" bitsize="64" type="ieee_double" regnum="32"/>
- <reg name="f1s1" bitsize="64" type="ieee_double"/>
- <reg name="f2s1" bitsize="64" type="ieee_double"/>
- <reg name="f3s1" bitsize="64" type="ieee_double"/>
- <reg name="f4s1" bitsize="64" type="ieee_double"/>
- <reg name="f5s1" bitsize="64" type="ieee_double"/>
- <reg name="f6s1" bitsize="64" type="ieee_double"/>
- <reg name="f7s1" bitsize="64" type="ieee_double"/>
- <reg name="f8s1" bitsize="64" type="ieee_double"/>
- <reg name="f9s1" bitsize="64" type="ieee_double"/>
- <reg name="f10s1" bitsize="64" type="ieee_double"/>
- <reg name="f11s1" bitsize="64" type="ieee_double"/>
- <reg name="f12s1" bitsize="64" type="ieee_double"/>
- <reg name="f13s1" bitsize="64" type="ieee_double"/>
- <reg name="f14s1" bitsize="64" type="ieee_double"/>
- <reg name="f15s1" bitsize="64" type="ieee_double"/>
- <reg name="f16s1" bitsize="64" type="ieee_double"/>
- <reg name="f17s1" bitsize="64" type="ieee_double"/>
- <reg name="f18s1" bitsize="64" type="ieee_double"/>
- <reg name="f19s1" bitsize="64" type="ieee_double"/>
- <reg name="f20s1" bitsize="64" type="ieee_double"/>
- <reg name="f21s1" bitsize="64" type="ieee_double"/>
- <reg name="f22s1" bitsize="64" type="ieee_double"/>
- <reg name="f23s1" bitsize="64" type="ieee_double"/>
- <reg name="f24s1" bitsize="64" type="ieee_double"/>
- <reg name="f25s1" bitsize="64" type="ieee_double"/>
- <reg name="f26s1" bitsize="64" type="ieee_double"/>
- <reg name="f27s1" bitsize="64" type="ieee_double"/>
- <reg name="f28s1" bitsize="64" type="ieee_double"/>
- <reg name="f29s1" bitsize="64" type="ieee_double"/>
- <reg name="f30s1" bitsize="64" type="ieee_double"/>
- <reg name="f31s1" bitsize="64" type="ieee_double"/>
+ <reg name="f0s1" bitsize="64" type="uint64" regnum="32"/>
+ <reg name="f1s1" bitsize="64" type="uint64"/>
+ <reg name="f2s1" bitsize="64" type="uint64"/>
+ <reg name="f3s1" bitsize="64" type="uint64"/>
+ <reg name="f4s1" bitsize="64" type="uint64"/>
+ <reg name="f5s1" bitsize="64" type="uint64"/>
+ <reg name="f6s1" bitsize="64" type="uint64"/>
+ <reg name="f7s1" bitsize="64" type="uint64"/>
+ <reg name="f8s1" bitsize="64" type="uint64"/>
+ <reg name="f9s1" bitsize="64" type="uint64"/>
+ <reg name="f10s1" bitsize="64" type="uint64"/>
+ <reg name="f11s1" bitsize="64" type="uint64"/>
+ <reg name="f12s1" bitsize="64" type="uint64"/>
+ <reg name="f13s1" bitsize="64" type="uint64"/>
+ <reg name="f14s1" bitsize="64" type="uint64"/>
+ <reg name="f15s1" bitsize="64" type="uint64"/>
+ <reg name="f16s1" bitsize="64" type="uint64"/>
+ <reg name="f17s1" bitsize="64" type="uint64"/>
+ <reg name="f18s1" bitsize="64" type="uint64"/>
+ <reg name="f19s1" bitsize="64" type="uint64"/>
+ <reg name="f20s1" bitsize="64" type="uint64"/>
+ <reg name="f21s1" bitsize="64" type="uint64"/>
+ <reg name="f22s1" bitsize="64" type="uint64"/>
+ <reg name="f23s1" bitsize="64" type="uint64"/>
+ <reg name="f24s1" bitsize="64" type="uint64"/>
+ <reg name="f25s1" bitsize="64" type="uint64"/>
+ <reg name="f26s1" bitsize="64" type="uint64"/>
+ <reg name="f27s1" bitsize="64" type="uint64"/>
+ <reg name="f28s1" bitsize="64" type="uint64"/>
+ <reg name="f29s1" bitsize="64" type="uint64"/>
+ <reg name="f30s1" bitsize="64" type="uint64"/>
+ <reg name="f31s1" bitsize="64" type="uint64"/>
<reg name="fpscrs1" bitsize="32" group="float" regnum="70"/>
</feature>
diff --git a/main/coregrind/m_gdbserver/power-fpu-valgrind-s2.xml b/main/coregrind/m_gdbserver/power-fpu-valgrind-s2.xml
index 2db1a4a..a12fa6e 100644
--- a/main/coregrind/m_gdbserver/power-fpu-valgrind-s2.xml
+++ b/main/coregrind/m_gdbserver/power-fpu-valgrind-s2.xml
@@ -7,38 +7,38 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.power.fpu-valgrind-s2">
- <reg name="f0s2" bitsize="64" type="ieee_double" regnum="32"/>
- <reg name="f1s2" bitsize="64" type="ieee_double"/>
- <reg name="f2s2" bitsize="64" type="ieee_double"/>
- <reg name="f3s2" bitsize="64" type="ieee_double"/>
- <reg name="f4s2" bitsize="64" type="ieee_double"/>
- <reg name="f5s2" bitsize="64" type="ieee_double"/>
- <reg name="f6s2" bitsize="64" type="ieee_double"/>
- <reg name="f7s2" bitsize="64" type="ieee_double"/>
- <reg name="f8s2" bitsize="64" type="ieee_double"/>
- <reg name="f9s2" bitsize="64" type="ieee_double"/>
- <reg name="f10s2" bitsize="64" type="ieee_double"/>
- <reg name="f11s2" bitsize="64" type="ieee_double"/>
- <reg name="f12s2" bitsize="64" type="ieee_double"/>
- <reg name="f13s2" bitsize="64" type="ieee_double"/>
- <reg name="f14s2" bitsize="64" type="ieee_double"/>
- <reg name="f15s2" bitsize="64" type="ieee_double"/>
- <reg name="f16s2" bitsize="64" type="ieee_double"/>
- <reg name="f17s2" bitsize="64" type="ieee_double"/>
- <reg name="f18s2" bitsize="64" type="ieee_double"/>
- <reg name="f19s2" bitsize="64" type="ieee_double"/>
- <reg name="f20s2" bitsize="64" type="ieee_double"/>
- <reg name="f21s2" bitsize="64" type="ieee_double"/>
- <reg name="f22s2" bitsize="64" type="ieee_double"/>
- <reg name="f23s2" bitsize="64" type="ieee_double"/>
- <reg name="f24s2" bitsize="64" type="ieee_double"/>
- <reg name="f25s2" bitsize="64" type="ieee_double"/>
- <reg name="f26s2" bitsize="64" type="ieee_double"/>
- <reg name="f27s2" bitsize="64" type="ieee_double"/>
- <reg name="f28s2" bitsize="64" type="ieee_double"/>
- <reg name="f29s2" bitsize="64" type="ieee_double"/>
- <reg name="f30s2" bitsize="64" type="ieee_double"/>
- <reg name="f31s2" bitsize="64" type="ieee_double"/>
+ <reg name="f0s2" bitsize="64" type="uint64" regnum="32"/>
+ <reg name="f1s2" bitsize="64" type="uint64"/>
+ <reg name="f2s2" bitsize="64" type="uint64"/>
+ <reg name="f3s2" bitsize="64" type="uint64"/>
+ <reg name="f4s2" bitsize="64" type="uint64"/>
+ <reg name="f5s2" bitsize="64" type="uint64"/>
+ <reg name="f6s2" bitsize="64" type="uint64"/>
+ <reg name="f7s2" bitsize="64" type="uint64"/>
+ <reg name="f8s2" bitsize="64" type="uint64"/>
+ <reg name="f9s2" bitsize="64" type="uint64"/>
+ <reg name="f10s2" bitsize="64" type="uint64"/>
+ <reg name="f11s2" bitsize="64" type="uint64"/>
+ <reg name="f12s2" bitsize="64" type="uint64"/>
+ <reg name="f13s2" bitsize="64" type="uint64"/>
+ <reg name="f14s2" bitsize="64" type="uint64"/>
+ <reg name="f15s2" bitsize="64" type="uint64"/>
+ <reg name="f16s2" bitsize="64" type="uint64"/>
+ <reg name="f17s2" bitsize="64" type="uint64"/>
+ <reg name="f18s2" bitsize="64" type="uint64"/>
+ <reg name="f19s2" bitsize="64" type="uint64"/>
+ <reg name="f20s2" bitsize="64" type="uint64"/>
+ <reg name="f21s2" bitsize="64" type="uint64"/>
+ <reg name="f22s2" bitsize="64" type="uint64"/>
+ <reg name="f23s2" bitsize="64" type="uint64"/>
+ <reg name="f24s2" bitsize="64" type="uint64"/>
+ <reg name="f25s2" bitsize="64" type="uint64"/>
+ <reg name="f26s2" bitsize="64" type="uint64"/>
+ <reg name="f27s2" bitsize="64" type="uint64"/>
+ <reg name="f28s2" bitsize="64" type="uint64"/>
+ <reg name="f29s2" bitsize="64" type="uint64"/>
+ <reg name="f30s2" bitsize="64" type="uint64"/>
+ <reg name="f31s2" bitsize="64" type="uint64"/>
<reg name="fpscrs2" bitsize="32" group="float" regnum="70"/>
</feature>
diff --git a/main/coregrind/m_gdbserver/regcache.c b/main/coregrind/m_gdbserver/regcache.c
index a920231..477c208 100644
--- a/main/coregrind/m_gdbserver/regcache.c
+++ b/main/coregrind/m_gdbserver/regcache.c
@@ -54,7 +54,7 @@
/* FIXME - fetch registers for INF */
if (fetch && regcache->registers_valid == 0) {
- fetch_inferior_registers (0);
+ valgrind_fetch_registers (0);
regcache->registers_valid = 1;
}
@@ -72,7 +72,7 @@
struct thread_info *saved_inferior = current_inferior;
current_inferior = thread;
- store_inferior_registers (-1);
+ valgrind_store_registers (-1);
current_inferior = saved_inferior;
}
diff --git a/main/coregrind/m_gdbserver/remote-utils.c b/main/coregrind/m_gdbserver/remote-utils.c
index d1ae548..009f327 100644
--- a/main/coregrind/m_gdbserver/remote-utils.c
+++ b/main/coregrind/m_gdbserver/remote-utils.c
@@ -196,7 +196,7 @@
void safe_mknod (char *nod)
{
SysRes m;
- m = VG_(mknod) (nod, VKI_S_IFIFO|0666, 0);
+ m = VG_(mknod) (nod, VKI_S_IFIFO|0600, 0);
if (sr_isError (m)) {
if (sr_Err (m) == VKI_EEXIST) {
if (VG_(clo_verbosity) > 1) {
@@ -224,10 +224,11 @@
const HChar *user, *host;
int save_fcntl_flags, len;
VgdbShared vgdbinit =
- {0, 0, 0, (Addr) VG_(invoke_gdbserver),
+ {0, 0, (Addr) VG_(invoke_gdbserver),
(Addr) VG_(threads), sizeof(ThreadState),
offsetof(ThreadState, status),
- offsetof(ThreadState, os_state) + offsetof(ThreadOSstate, lwpid)};
+ offsetof(ThreadState, os_state) + offsetof(ThreadOSstate, lwpid),
+ 0};
const int pid = VG_(getpid)();
const int name_default = strcmp(name, VG_(vgdb_prefix_default)()) == 0;
Addr addr_shared;
@@ -269,7 +270,7 @@
"don't want to do, unless you know exactly what you're doing,\n"
"or are doing some strange experiment):\n"
" %s/../../bin/vgdb --pid=%d%s%s ...command...\n",
- VG_LIBDIR,
+ VG_(libdir),
pid, (name_default ? "" : " --vgdb-prefix="),
(name_default ? "" : name));
}
@@ -282,7 +283,7 @@
"and then give GDB the following command\n"
" target remote | %s/../../bin/vgdb --pid=%d%s%s\n",
VG_(args_the_exename),
- VG_LIBDIR,
+ VG_(libdir),
pid, (name_default ? "" : " --vgdb-prefix="),
(name_default ? "" : name)
);
@@ -306,7 +307,7 @@
pid_from_to_creator = pid;
- o = VG_(open) (shared_mem, VKI_O_CREAT|VKI_O_RDWR, 0666);
+ o = VG_(open) (shared_mem, VKI_O_CREAT|VKI_O_RDWR, 0600);
if (sr_isError (o)) {
sr_perror(o, "cannot create shared_mem file %s\n", shared_mem);
fatal("");
@@ -541,6 +542,29 @@
return i;
}
+/* builds an image of bin according to byte order of the architecture
+ Useful for register and int image */
+char* heximage (char *buf, char *bin, int count)
+{
+#if defined(VGA_x86) || defined(VGA_amd64)
+ char rev[count];
+ /* note: no need for trailing \0, length is known with count */
+ int i;
+ for (i = 0; i < count; i++)
+ rev[i] = bin[count - i - 1];
+ hexify (buf, rev, count);
+#else
+ hexify (buf, bin, count);
+#endif
+ return buf;
+}
+
+void* C2v(CORE_ADDR addr)
+{
+ return (void*) addr;
+}
+
+
/* Convert BUFFER, binary data at least LEN bytes long, into escaped
binary data in OUT_BUF. Set *OUT_LEN to the length of the data
encoded in OUT_BUF, and return the number of bytes in OUT_BUF
@@ -728,7 +752,7 @@
/* Check for an input interrupt while we're here. */
if (cc == '\003')
- (*the_target->send_signal) (VKI_SIGINT);
+ dlog(1, "Received 0x03 character (SIGINT)\n");
}
while (cc != '+');
@@ -961,15 +985,14 @@
if (status == 'T') {
const char **regp = gdbserver_expedite_regs;
- if (the_target->stopped_by_watchpoint != NULL
- && (*the_target->stopped_by_watchpoint) ()) {
+ if (valgrind_stopped_by_watchpoint()) {
CORE_ADDR addr;
int i;
strncpy (buf, "watch:", 6);
buf += 6;
- addr = (*the_target->stopped_data_address) ();
+ addr = valgrind_stopped_data_address ();
/* Convert each byte of the address into two hexadecimal chars.
Note that we take sizeof (void *) instead of sizeof (addr);
@@ -1079,13 +1102,13 @@
HChar *
VG_(vgdb_prefix_default)(void)
{
- const HChar *tmpdir;
- HChar *prefix;
+ static HChar *prefix;
- tmpdir = VG_(tmpdir)();
- prefix = malloc(strlen(tmpdir) + strlen("/vgdb-pipe") + 1);
- strcpy(prefix, tmpdir);
- strcat(prefix, "/vgdb-pipe");
-
+ if (prefix == NULL) {
+ const HChar *tmpdir = VG_(tmpdir)();
+ prefix = malloc(strlen(tmpdir) + strlen("/vgdb-pipe") + 1);
+ strcpy(prefix, tmpdir);
+ strcat(prefix, "/vgdb-pipe");
+ }
return prefix;
}
diff --git a/main/coregrind/m_gdbserver/s390-acr-valgrind-s1.xml b/main/coregrind/m_gdbserver/s390-acr-valgrind-s1.xml
new file mode 100644
index 0000000..77b63b1
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390-acr-valgrind-s1.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.acr-valgrind-s1">
+ <reg name="acr0s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr1s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr2s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr3s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr4s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr5s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr6s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr7s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr8s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr9s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr10s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr11s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr12s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr13s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr14s1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr15s1" bitsize="32" type="uint32" group="access"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390-acr-valgrind-s2.xml b/main/coregrind/m_gdbserver/s390-acr-valgrind-s2.xml
new file mode 100644
index 0000000..5124e48
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390-acr-valgrind-s2.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.acr-valgrind-s2">
+ <reg name="acr0s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr1s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr2s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr3s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr4s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr5s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr6s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr7s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr8s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr9s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr10s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr11s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr12s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr13s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr14s2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr15s2" bitsize="32" type="uint32" group="access"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390-acr.xml b/main/coregrind/m_gdbserver/s390-acr.xml
new file mode 100644
index 0000000..a7e9a17
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390-acr.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.acr">
+ <reg name="acr0" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr1" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr2" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr3" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr4" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr5" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr6" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr7" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr8" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr9" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr10" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr11" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr12" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr13" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr14" bitsize="32" type="uint32" group="access"/>
+ <reg name="acr15" bitsize="32" type="uint32" group="access"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390-fpr-valgrind-s1.xml b/main/coregrind/m_gdbserver/s390-fpr-valgrind-s1.xml
new file mode 100644
index 0000000..afc2b95
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390-fpr-valgrind-s1.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.fpr-valgrind-s1">
+ <reg name="fpcs1" bitsize="32" type="uint32" group="float"/>
+ <reg name="f0s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f1s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f2s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f3s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f4s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f5s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f6s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f7s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f8s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f9s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f10s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f11s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f12s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f13s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f14s1" bitsize="64" type="uint64" group="float"/>
+ <reg name="f15s1" bitsize="64" type="uint64" group="float"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390-fpr-valgrind-s2.xml b/main/coregrind/m_gdbserver/s390-fpr-valgrind-s2.xml
new file mode 100644
index 0000000..7a74ce6
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390-fpr-valgrind-s2.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.fpr-valgrind-s2">
+ <reg name="fpcs2" bitsize="32" type="uint32" group="float"/>
+ <reg name="f0s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f1s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f2s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f3s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f4s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f5s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f6s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f7s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f8s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f9s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f10s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f11s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f12s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f13s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f14s2" bitsize="64" type="uint64" group="float"/>
+ <reg name="f15s2" bitsize="64" type="uint64" group="float"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390-fpr.xml b/main/coregrind/m_gdbserver/s390-fpr.xml
new file mode 100644
index 0000000..1919b60
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390-fpr.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.fpr">
+ <reg name="fpc" bitsize="32" type="uint32" group="float"/>
+ <reg name="f0" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f1" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f2" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f3" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f4" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f5" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f6" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f7" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f8" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f9" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f10" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f11" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f12" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f13" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f14" bitsize="64" type="ieee_double" group="float"/>
+ <reg name="f15" bitsize="64" type="ieee_double" group="float"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390x-core64-valgrind-s1.xml b/main/coregrind/m_gdbserver/s390x-core64-valgrind-s1.xml
new file mode 100644
index 0000000..ee19b13
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390x-core64-valgrind-s1.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.core-valgrind-s1">
+ <reg name="pswms1" bitsize="64" type="uint64" group="psw"/>
+ <reg name="pswas1" bitsize="64" type="uint64" group="psw"/>
+ <reg name="r0s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r1s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r2s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r3s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r4s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r5s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r6s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r7s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r8s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r9s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r10s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r11s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r12s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r13s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r14s1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r15s1" bitsize="64" type="uint64" group="general"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390x-core64-valgrind-s2.xml b/main/coregrind/m_gdbserver/s390x-core64-valgrind-s2.xml
new file mode 100644
index 0000000..90b373b
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390x-core64-valgrind-s2.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.core-valgrind-s2">
+ <reg name="pswms2" bitsize="64" type="uint64" group="psw"/>
+ <reg name="pswas2" bitsize="64" type="uint64" group="psw"/>
+ <reg name="r0s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r1s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r2s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r3s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r4s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r5s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r6s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r7s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r8s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r9s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r10s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r11s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r12s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r13s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r14s2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r15s2" bitsize="64" type="uint64" group="general"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390x-core64.xml b/main/coregrind/m_gdbserver/s390x-core64.xml
new file mode 100644
index 0000000..06f786c
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390x-core64.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.core">
+ <reg name="pswm" bitsize="64" type="uint64" group="psw"/>
+ <reg name="pswa" bitsize="64" type="uint64" group="psw"/>
+ <reg name="r0" bitsize="64" type="uint64" group="general"/>
+ <reg name="r1" bitsize="64" type="uint64" group="general"/>
+ <reg name="r2" bitsize="64" type="uint64" group="general"/>
+ <reg name="r3" bitsize="64" type="uint64" group="general"/>
+ <reg name="r4" bitsize="64" type="uint64" group="general"/>
+ <reg name="r5" bitsize="64" type="uint64" group="general"/>
+ <reg name="r6" bitsize="64" type="uint64" group="general"/>
+ <reg name="r7" bitsize="64" type="uint64" group="general"/>
+ <reg name="r8" bitsize="64" type="uint64" group="general"/>
+ <reg name="r9" bitsize="64" type="uint64" group="general"/>
+ <reg name="r10" bitsize="64" type="uint64" group="general"/>
+ <reg name="r11" bitsize="64" type="uint64" group="general"/>
+ <reg name="r12" bitsize="64" type="uint64" group="general"/>
+ <reg name="r13" bitsize="64" type="uint64" group="general"/>
+ <reg name="r14" bitsize="64" type="uint64" group="general"/>
+ <reg name="r15" bitsize="64" type="uint64" group="general"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390x-generic-valgrind.xml b/main/coregrind/m_gdbserver/s390x-generic-valgrind.xml
new file mode 100644
index 0000000..6457582
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390x-generic-valgrind.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- S/390 64-bit user-level code. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>s390:64-bit</architecture>
+ <xi:include href="s390x-core64.xml"/>
+ <xi:include href="s390-acr.xml"/>
+ <xi:include href="s390-fpr.xml"/>
+ <xi:include href="s390x-linux64.xml"/>
+ <xi:include href="s390x-core64-valgrind-s1.xml"/>
+ <xi:include href="s390-acr-valgrind-s1.xml"/>
+ <xi:include href="s390-fpr-valgrind-s1.xml"/>
+ <xi:include href="s390x-linux64-valgrind-s1.xml"/>
+ <xi:include href="s390x-core64-valgrind-s2.xml"/>
+ <xi:include href="s390-acr-valgrind-s2.xml"/>
+ <xi:include href="s390-fpr-valgrind-s2.xml"/>
+ <xi:include href="s390x-linux64-valgrind-s2.xml"/>
+</target>
diff --git a/main/coregrind/m_gdbserver/s390x-generic.xml b/main/coregrind/m_gdbserver/s390x-generic.xml
new file mode 100644
index 0000000..c005a3b
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390x-generic.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- S/390 64-bit user-level code. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>s390:64-bit</architecture>
+ <xi:include href="s390x-core64.xml"/>
+ <xi:include href="s390-acr.xml"/>
+ <xi:include href="s390-fpr.xml"/>
+ <xi:include href="s390x-linux64.xml"/>
+</target>
diff --git a/main/coregrind/m_gdbserver/s390x-linux64-valgrind-s1.xml b/main/coregrind/m_gdbserver/s390x-linux64-valgrind-s1.xml
new file mode 100644
index 0000000..23eed21
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390x-linux64-valgrind-s1.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- S/390 64-bit user-level code. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.linux-valgrind-s1">
+ <reg name="orig_r2s1" bitsize="64" type="uint64" group="system"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390x-linux64-valgrind-s2.xml b/main/coregrind/m_gdbserver/s390x-linux64-valgrind-s2.xml
new file mode 100644
index 0000000..22ac591
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390x-linux64-valgrind-s2.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- S/390 64-bit user-level code. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.linux-valgrind-s2">
+ <reg name="orig_r2s2" bitsize="64" type="uint64" group="system"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/s390x-linux64.xml b/main/coregrind/m_gdbserver/s390x-linux64.xml
new file mode 100644
index 0000000..7e2ec89
--- /dev/null
+++ b/main/coregrind/m_gdbserver/s390x-linux64.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- S/390 64-bit user-level code. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.linux">
+ <reg name="orig_r2" bitsize="64" type="uint64" group="system"/>
+</feature>
diff --git a/main/coregrind/m_gdbserver/server.c b/main/coregrind/m_gdbserver/server.c
index a1a2608..661041e 100644
--- a/main/coregrind/m_gdbserver/server.c
+++ b/main/coregrind/m_gdbserver/server.c
@@ -34,15 +34,17 @@
unsigned long thread_from_wait;
unsigned long old_thread_from_wait;
-int pass_signals[TARGET_SIGNAL_LAST];
+int pass_signals[TARGET_SIGNAL_LAST]; /* indexed by gdb signal nr */
/* for a gdbserver integrated in valgrind, resuming the process consists
in returning the control to valgrind.
+ The guess process resumes its execution.
Then at the next error or break or ..., valgrind calls gdbserver again.
- A resume packet must then be built.
- resume_packet_needed records the fact that the next call to gdbserver
+ A resume reply packet must then be built to inform GDB that the
+ resume request is finished.
+ resume_reply_packet_needed records the fact that the next call to gdbserver
must send a resume packet to gdb. */
-static Bool resume_packet_needed = False;
+static Bool resume_reply_packet_needed = False;
VG_MINIMAL_JMP_BUF(toplevel);
@@ -171,7 +173,8 @@
if (int_value) { VG_(gdb_printf) (
"debugging valgrind internals monitor commands:\n"
" v.info gdbserver_status : show gdbserver status\n"
-" v.info memory : show valgrind heap memory stats\n"
+" v.info memory [aspacemgr] : show valgrind heap memory stats\n"
+" (with aspacemgr arg, also shows valgrind segments on log ouput)\n"
" v.info scheduler : show valgrind thread state and stacktrace\n"
" v.set debuglog <level> : set valgrind debug log level to <level>\n"
" v.translate <addr> [<traceflags>] : debug translation of <addr> with <traceflags>\n"
@@ -246,8 +249,9 @@
VG_(show_all_errors)(/* verbosity */ 2, /* xml */ False);
break;
case 1: // n_errs_found
- VG_(gdb_printf) ("n_errs_found %d (vgdb-error %d)\n",
+ VG_(gdb_printf) ("n_errs_found %d n_errs_shown %d (vgdb-error %d)\n",
VG_(get_n_errs_found) (),
+ VG_(get_n_errs_shown) (),
VG_(dyn_vgdb_error));
break;
case 2: // last_error
@@ -260,6 +264,18 @@
VG_(print_all_arena_stats) ();
if (VG_(clo_profile_heap))
VG_(print_arena_cc_analysis) ();
+ wcmd = strtok_r (NULL, " ", &ssaveptr);
+ if (wcmd != NULL) {
+ switch (VG_(keyword_id) ("aspacemgr", wcmd, kwd_report_all)) {
+ case -2:
+ case -1: break;
+ case 0:
+ VG_(am_show_nsegments) (0, "gdbserver v.info memory aspacemgr");
+ break;
+ default: tl_assert (0);
+ }
+ }
+
ret = 1;
break;
case 5: /* scheduler */
@@ -411,7 +427,8 @@
if (to == NULL) to = end;
decode_address (&sig, from, to - from);
pass_signals[(int)sig] = 1;
- dlog(1, "pass_signal %d\n", (int)sig);
+ dlog(1, "pass_signal gdb_nr %d %s\n",
+ (int)sig, target_signal_to_name(sig));
from = to;
if (*from == ';') from++;
}
@@ -515,8 +532,7 @@
}
}
- if ( ((*the_target->target_xml)() != NULL
- || (*the_target->shadow_target_xml)() != NULL)
+ if (valgrind_target_xml(VG_(clo_vgdb_shadow_registers)) != NULL
&& strncmp ("qXfer:features:read:", arg_own_buf, 20) == 0) {
CORE_ADDR ofs;
unsigned int len, doc_len;
@@ -532,19 +548,11 @@
}
if (strcmp (annex, "target.xml") == 0) {
- annex = NULL; // to replace it by the corresponding filename.
-
- /* If VG_(clo_vgdb_shadow_registers), try to use
- shadow_target_xml. Fallback to target_xml
- if not defined. */
- if (VG_(clo_vgdb_shadow_registers)) {
- annex = (*the_target->shadow_target_xml)();
- if (annex != NULL)
- /* Ensure the shadow registers are initialized. */
- initialize_shadow_low(True);
+ annex = valgrind_target_xml(VG_(clo_vgdb_shadow_registers));
+ if (annex != NULL && VG_(clo_vgdb_shadow_registers)) {
+ /* Ensure the shadow registers are initialized. */
+ initialize_shadow_low(True);
}
- if (annex == NULL)
- annex = (*the_target->target_xml)();
if (annex == NULL) {
strcpy (arg_own_buf, "E00");
return;
@@ -552,7 +560,7 @@
}
{
- char doc[VG_(strlen)(VG_(libdir)) + 1 + VG_(strlen)(annex)];
+ char doc[VG_(strlen)(VG_(libdir)) + 1 + VG_(strlen)(annex) + 1];
struct vg_stat stat_doc;
char toread[len];
int len_read;
@@ -652,8 +660,7 @@
if (VG_(client_auxv))
strcat (arg_own_buf, ";qXfer:auxv:read+");
- if ((*the_target->target_xml)() != NULL
- || (*the_target->shadow_target_xml)() != NULL) {
+ if (valgrind_target_xml(VG_(clo_vgdb_shadow_registers)) != NULL) {
strcat (arg_own_buf, ";qXfer:features:read+");
/* if a new gdb connects to us, we have to reset the register
set to the normal register sets to allow this new gdb to
@@ -692,21 +699,16 @@
struct thread_resume resume_info[2];
int n = 0;
- if (step || sig || (cont_thread != 0 && cont_thread != -1)) {
- resume_info[0].thread
- = ((struct inferior_list_entry *) current_inferior)->id;
+ if (step || sig) {
resume_info[0].step = step;
resume_info[0].sig = sig;
- resume_info[0].leave_stopped = 0;
n++;
}
- resume_info[n].thread = -1;
resume_info[n].step = 0;
resume_info[n].sig = 0;
- resume_info[n].leave_stopped = (cont_thread != 0 && cont_thread != -1);
- resume_packet_needed = True;
- (*the_target->resume) (resume_info);
+ resume_reply_packet_needed = True;
+ valgrind_resume (resume_info);
}
/* server_main global variables */
@@ -717,9 +719,13 @@
{
dlog(1, "gdbserver_init gdbserver embedded in valgrind: %s\n", version);
noack_mode = False;
- initialize_low ();
- own_buf = malloc (PBUFSIZ);
- mem_buf = malloc (PBUFSIZ);
+ valgrind_initialize_target ();
+ // After a fork, gdbserver_init can be called again.
+ // We do not have to re-malloc the buffers in such a case.
+ if (own_buf == NULL)
+ own_buf = malloc (PBUFSIZ);
+ if (mem_buf == NULL)
+ mem_buf = malloc (PBUFSIZ);
}
void gdbserver_terminate (void)
@@ -742,7 +748,7 @@
unsigned int len;
CORE_ADDR mem_addr;
- zignal = mywait (&status);
+ zignal = valgrind_wait (&status);
if (VG_MINIMAL_SETJMP(toplevel)) {
dlog(0, "error caused VG_MINIMAL_LONGJMP to server_main\n");
}
@@ -751,8 +757,10 @@
int packet_len;
int new_packet_len = -1;
- if (resume_packet_needed) {
- resume_packet_needed = False;
+ if (resume_reply_packet_needed) {
+ /* Send the resume reply to reply to last GDB resume
+ request. */
+ resume_reply_packet_needed = False;
prepare_resume_reply (own_buf, status, zignal);
putpkt (own_buf);
}
@@ -785,7 +793,7 @@
remote_finish (reset_after_error);
remote_open (VG_(clo_vgdb_prefix));
myresume (0, 0);
- resume_packet_needed = False;
+ resume_reply_packet_needed = False;
return;
case '!':
/* We can not use the extended protocol with valgrind,
@@ -871,14 +879,14 @@
}
case 'm':
decode_m_packet (&own_buf[1], &mem_addr, &len);
- if (read_inferior_memory (mem_addr, mem_buf, len) == 0)
+ if (valgrind_read_memory (mem_addr, mem_buf, len) == 0)
convert_int_to_ascii (mem_buf, own_buf, len);
else
write_enn (own_buf);
break;
case 'M':
decode_M_packet (&own_buf[1], &mem_addr, &len, mem_buf);
- if (write_inferior_memory (mem_addr, mem_buf, len) == 0)
+ if (valgrind_write_memory (mem_addr, mem_buf, len) == 0)
write_ok (own_buf);
else
write_enn (own_buf);
@@ -886,7 +894,7 @@
case 'X':
if (decode_X_packet (&own_buf[1], packet_len - 1,
&mem_addr, &len, mem_buf) < 0
- || write_inferior_memory (mem_addr, mem_buf, len) != 0)
+ || valgrind_write_memory (mem_addr, mem_buf, len) != 0)
write_enn (own_buf);
else
write_ok (own_buf);
@@ -924,15 +932,13 @@
int zlen = strtol (lenptr + 1, &dataptr, 16);
char type = own_buf[1];
- if (the_target->insert_watchpoint == NULL
- || (type < '0' || type > '4')) {
- /* No watchpoint support or not a watchpoint command;
- unrecognized either way. */
+ if (type < '0' || type > '4') {
+ /* Watchpoint command type unrecognized. */
own_buf[0] = '\0';
} else {
int res;
- res = (*the_target->insert_watchpoint) (type, addr, zlen);
+ res = valgrind_insert_watchpoint (type, addr, zlen);
if (res == 0)
write_ok (own_buf);
else if (res == 1)
@@ -950,15 +956,13 @@
int zlen = strtol (lenptr + 1, &dataptr, 16);
char type = own_buf[1];
- if (the_target->remove_watchpoint == NULL
- || (type < '0' || type > '4')) {
- /* No watchpoint support or not a watchpoint command;
- unrecognized either way. */
+ if (type < '0' || type > '4') {
+ /* Watchpoint command type unrecognized. */
own_buf[0] = '\0';
} else {
int res;
- res = (*the_target->remove_watchpoint) (type, addr, zlen);
+ res = valgrind_remove_watchpoint (type, addr, zlen);
if (res == 0)
write_ok (own_buf);
else if (res == 1)
@@ -982,7 +986,7 @@
break;
}
- if (mythread_alive (thread_id))
+ if (valgrind_thread_alive (thread_id))
write_ok (own_buf);
else
write_enn (own_buf);
@@ -1036,6 +1040,6 @@
remote_finish (reset_after_error);
remote_open (VG_(clo_vgdb_prefix));
myresume (0, 0);
- resume_packet_needed = False;
+ resume_reply_packet_needed = False;
return;
}
diff --git a/main/coregrind/m_gdbserver/server.h b/main/coregrind/m_gdbserver/server.h
index dc1b128..077a658 100644
--- a/main/coregrind/m_gdbserver/server.h
+++ b/main/coregrind/m_gdbserver/server.h
@@ -107,34 +107,6 @@
If debug info not found for this pc, assumes arm */
extern Addr thumb_pc (Addr pc);
-/* True if gdbserver is single stepping the valgrind process */
-extern Bool valgrind_single_stepping(void);
-
-/* Set Valgrind in single stepping mode or not according to Bool. */
-extern void valgrind_set_single_stepping(Bool);
-
-/* gets the addr at which a (possible) break must be ignored once.
- If there is no such break to be ignored once, 0 is returned.
- This is needed for the following case:
- The user sets a break at address AAA.
- The break is encountered. Then the user does stepi
- (i.e. step one instruction).
- In such a case, the already encountered break must be ignored
- to ensure the stepi will advance by one instruction: a "break"
- is implemented in valgrind by some helper code just after the
- instruction mark at which the break is set. This helper code
- verifies if either there is a break at the current PC
- or if we are in stepping mode. If we are in stepping mode,
- the already encountered break must be ignored once to advance
- to the next instruction.
- ??? need to check if this is *really* needed. */
-extern Addr valgrind_get_ignore_break_once(void);
-
-/* When addr > 0, ensures the next stop reply packet informs
- gdb about the encountered watchpoint.
- Use addr 0x0 to reset. */
-extern void VG_(set_watchpoint_stop_address) (Addr addr);
-
/* when invoked by vgdb using ptrace, contains the tid chosen
by vgdb (if vgdb gives a tid different of 0: a 0 tid by
vgdb means use the running_tid if there is one running
@@ -230,32 +202,25 @@
gdbserver by calling call_gdbserver.
On return, call gdbserver_deliver_signal to effectively
deliver the signal or not. */
-extern void gdbserver_signal_encountered (Int sigNo);
+extern void gdbserver_signal_encountered (Int vki_sigNo);
/* between these two calls, call call_gdbserver */
/* If gdbserver_deliver_signal True, then gdb did not ask
to ignore the signal, so signal can be delivered to the guest. */
-extern Bool gdbserver_deliver_signal (Int sigNo);
+extern Bool gdbserver_deliver_signal (Int vki_sigNo);
/* To optimise signal handling, gdb can instruct gdbserver to
- not stop on some signals. In the below, a 1 indicates the signal
+ not stop on some signals. In the below, a 1 indicates the gdb_nr signal
has to be passed directly to the guest, without asking gdb.
A 0 indicates gdb has to be consulted to see if signal has
or has not to be passed. The gdb consultation is to
be done using the above two functions. */
-extern int pass_signals[];
+extern int pass_signals[]; /* indexed by gdb signal nr */
#include "target.h"
/* Target-specific functions */
-void initialize_low (void);
-
-/* initialize or re-initialize the register set of the low target.
- if shadow_mode, then (re-)define the normal and valgrind shadow registers
- else (re-)define only the normal registers. */
-void initialize_shadow_low (Bool shadow_mode);
-
/* From inferiors.c. */
extern struct inferior_list all_threads;
@@ -323,6 +288,14 @@
int unhexify (char *bin, const char *hex, int count);
int hexify (char *hex, const char *bin, int count);
+/* heximage builds an image of bin according to byte order of the architecture
+ Useful for register and int image */
+char* heximage (char *buf, char *bin, int count);
+
+/* convert from CORE_ADDR to void* */
+void* C2v(CORE_ADDR addr);
+
+
int remote_escape_output (const gdb_byte *buffer, int len,
gdb_byte *out_buf, int *out_len,
int out_maxlen);
diff --git a/main/coregrind/m_gdbserver/signals.c b/main/coregrind/m_gdbserver/signals.c
index 07b0c24..ee60ccd 100644
--- a/main/coregrind/m_gdbserver/signals.c
+++ b/main/coregrind/m_gdbserver/signals.c
@@ -466,6 +466,22 @@
return TARGET_SIGNAL_INFO;
#endif
+#if defined (VKI_SIGRTMIN)
+ if (hostsig >= VKI_SIGRTMIN && hostsig < VKI_SIGRTMAX) {
+ /* This block of TARGET_SIGNAL_REALTIME value is in order. */
+ if (33 <= hostsig && hostsig <= 63)
+ return (enum target_signal)
+ (hostsig - 33 + (int) TARGET_SIGNAL_REALTIME_33);
+ else if (hostsig == 32)
+ return TARGET_SIGNAL_REALTIME_32;
+ else if (64 <= hostsig && hostsig <= 127)
+ return (enum target_signal)
+ (hostsig - 64 + (int) TARGET_SIGNAL_REALTIME_64);
+ }
+#endif
+
+ error ("Valgrind GDBSERVER bug: (target_signal_from_host):"
+ " unrecognized vki signal %d\n", hostsig);
return TARGET_SIGNAL_UNKNOWN;
}
@@ -476,7 +492,7 @@
static
int do_target_signal_to_host (enum target_signal oursig,
- int *oursig_ok)
+ int *oursig_ok)
{
*oursig_ok = 1;
switch (oursig) {
@@ -700,6 +716,32 @@
#endif
default:
+#if defined (VKI_SIGRTMIN)
+ {
+ int retsig = 0;
+
+ if (oursig >= TARGET_SIGNAL_REALTIME_33
+ && oursig <= TARGET_SIGNAL_REALTIME_63) {
+ /* This block of signals is continuous, and
+ TARGET_SIGNAL_REALTIME_33 is 33 by definition. */
+ retsig = (int) oursig - (int) TARGET_SIGNAL_REALTIME_33 + 33;
+ } else if (oursig == TARGET_SIGNAL_REALTIME_32) {
+ /* TARGET_SIGNAL_REALTIME_32 isn't contiguous with
+ TARGET_SIGNAL_REALTIME_33. It is 32 by definition. */
+ retsig = 32;
+ } else if (oursig >= TARGET_SIGNAL_REALTIME_64
+ && oursig <= TARGET_SIGNAL_REALTIME_127) {
+ /* This block of signals is continuous, and
+ TARGET_SIGNAL_REALTIME_64 is 64 by definition. */
+ retsig = (int) oursig - (int) TARGET_SIGNAL_REALTIME_64 + 64;
+ }
+
+ if (retsig >= VKI_SIGRTMIN && retsig < VKI_SIGRTMAX)
+ return retsig;
+ }
+#endif
+ error ("Valgrind GDBSERVER bug: (do_target_signal_to_host):"
+ " unrecognized target signal %d\n", oursig);
*oursig_ok = 0;
return 0;
}
diff --git a/main/coregrind/m_gdbserver/target.c b/main/coregrind/m_gdbserver/target.c
index ae61c94..165a717 100644
--- a/main/coregrind/m_gdbserver/target.c
+++ b/main/coregrind/m_gdbserver/target.c
@@ -23,8 +23,524 @@
Boston, MA 02110-1301, USA. */
#include "server.h"
+#include "target.h"
+#include "regdef.h"
+#include "regcache.h"
+#include "valgrind_low.h"
+#include "gdb/signals.h"
+#include "pub_core_aspacemgr.h"
+#include "pub_tool_machine.h"
+#include "pub_core_threadstate.h"
+#include "pub_core_transtab.h"
+#include "pub_core_gdbserver.h"
+#include "pub_tool_debuginfo.h"
-struct target_ops *the_target;
+
+/* the_low_target defines the architecture specific aspects depending
+ on the cpu */
+static struct valgrind_target_ops the_low_target;
+
+static
+char *image_ptid(unsigned long ptid)
+{
+ static char result[100];
+ VG_(sprintf) (result, "id %ld", ptid);
+ return result;
+}
+#define get_thread(inf) ((struct thread_info *)(inf))
+static
+void remove_thread_if_not_in_vg_threads (struct inferior_list_entry *inf)
+{
+ struct thread_info *thread = get_thread (inf);
+ if (!VG_(lwpid_to_vgtid)(thread_to_gdb_id(thread))) {
+ dlog(1, "removing gdb ptid %s\n",
+ image_ptid(thread_to_gdb_id(thread)));
+ remove_thread (thread);
+ }
+}
+
+/* synchronize threads known by valgrind and threads known by gdbserver */
+static
+void valgrind_update_threads (int pid)
+{
+ ThreadId tid;
+ ThreadState *ts;
+ unsigned long ptid;
+ struct thread_info *ti;
+
+ /* call remove_thread for all gdb threads not in valgrind threads */
+ for_each_inferior (&all_threads, remove_thread_if_not_in_vg_threads);
+
+ /* call add_thread for all valgrind threads not known in gdb all_threads */
+ for (tid = 1; tid < VG_N_THREADS; tid++) {
+
+#define LOCAL_THREAD_TRACE " ti* %p vgtid %d status %s as gdb ptid %s lwpid %d\n", \
+ ti, tid, VG_(name_of_ThreadStatus) (ts->status), \
+ image_ptid (ptid), ts->os_state.lwpid
+
+ if (VG_(is_valid_tid) (tid)) {
+ ts = VG_(get_ThreadState) (tid);
+ ptid = ts->os_state.lwpid;
+ ti = gdb_id_to_thread (ptid);
+ if (!ti) {
+ /* we do not report the threads which are not yet fully
+ initialized otherwise this creates duplicated threads
+ in gdb: once with pid xxx lwpid 0, then after that
+ with pid xxx lwpid yyy. */
+ if (ts->status != VgTs_Init) {
+ dlog(1, "adding_thread" LOCAL_THREAD_TRACE);
+ add_thread (ptid, ts, ptid);
+ }
+ } else {
+ dlog(2, "(known thread)" LOCAL_THREAD_TRACE);
+ }
+ }
+#undef LOCAL_THREAD_TRACE
+ }
+}
+
+static
+struct reg* build_shadow_arch (struct reg *reg_defs, int n) {
+ int i, r;
+ static char *postfix[3] = { "", "s1", "s2" };
+ struct reg *new_regs = malloc(3 * n * sizeof(reg_defs[0]));
+ int reg_set_len = reg_defs[n-1].offset + reg_defs[n-1].size;
+
+ for (i = 0; i < 3; i++) {
+ for (r = 0; r < n; r++) {
+ new_regs[i*n + r].name = malloc(strlen(reg_defs[r].name)
+ + strlen (postfix[i]) + 1);
+ strcpy (new_regs[i*n + r].name, reg_defs[r].name);
+ strcat (new_regs[i*n + r].name, postfix[i]);
+ new_regs[i*n + r].offset = i*reg_set_len + reg_defs[r].offset;
+ new_regs[i*n + r].size = reg_defs[r].size;
+ dlog(1,
+ "%10s Nr %d offset(bit) %d offset(byte) %d size(bit) %d\n",
+ new_regs[i*n + r].name, i*n + r, new_regs[i*n + r].offset,
+ (new_regs[i*n + r].offset) / 8, new_regs[i*n + r].size);
+ }
+ }
+
+ return new_regs;
+}
+
+
+static CORE_ADDR stopped_data_address = 0;
+void VG_(set_watchpoint_stop_address) (Addr addr)
+{
+ stopped_data_address = addr;
+}
+
+int valgrind_stopped_by_watchpoint (void)
+{
+ return stopped_data_address != 0;
+}
+
+CORE_ADDR valgrind_stopped_data_address (void)
+{
+ return stopped_data_address;
+}
+
+/* pc at which we last stopped */
+static CORE_ADDR stop_pc;
+
+/* pc at which we resume.
+ If stop_pc != resume_pc, it means
+ gdb/gdbserver has changed the pc so as to have either
+ a "continue by jumping at that address"
+ or a "continue at that address to call some code from gdb".
+*/
+static CORE_ADDR resume_pc;
+
+static int vki_signal_to_report;
+
+void gdbserver_signal_encountered (Int vki_sigNo)
+{
+ vki_signal_to_report = vki_sigNo;
+}
+
+static int vki_signal_to_deliver;
+Bool gdbserver_deliver_signal (Int vki_sigNo)
+{
+ return vki_sigNo == vki_signal_to_deliver;
+}
+
+static
+char* sym (Addr addr)
+{
+ static char buf[200];
+ VG_(describe_IP) (addr, buf, 200);
+ return buf;
+}
+
+ThreadId vgdb_interrupted_tid = 0;
+
+/* 0 => not single stepping.
+ 1 => single stepping asked by gdb
+ 2 => single stepping asked by valgrind (watchpoint) */
+static int stepping = 0;
+
+Addr valgrind_get_ignore_break_once(void)
+{
+ if (valgrind_single_stepping())
+ return resume_pc;
+ else
+ return 0;
+}
+
+void valgrind_set_single_stepping(Bool set)
+{
+ if (set)
+ stepping = 2;
+ else
+ stepping = 0;
+}
+
+Bool valgrind_single_stepping(void)
+{
+ if (stepping)
+ return True;
+ else
+ return False;
+}
+
+int valgrind_thread_alive (unsigned long tid)
+{
+ struct thread_info *ti = gdb_id_to_thread(tid);
+ ThreadState *tst;
+
+ if (ti != NULL) {
+ tst = (ThreadState *) inferior_target_data (ti);
+ return tst->status != VgTs_Zombie;
+ }
+ else {
+ return 0;
+ }
+}
+
+void valgrind_resume (struct thread_resume *resume_info)
+{
+ dlog(1,
+ "resume_info step %d sig %d stepping %d\n",
+ resume_info->step,
+ resume_info->sig,
+ stepping);
+ if (valgrind_stopped_by_watchpoint()) {
+ dlog(1, "clearing watchpoint stopped_data_address %p\n",
+ C2v(stopped_data_address));
+ VG_(set_watchpoint_stop_address) ((Addr) 0);
+ }
+ vki_signal_to_deliver = resume_info->sig;
+
+ stepping = resume_info->step;
+ resume_pc = (*the_low_target.get_pc) ();
+ if (resume_pc != stop_pc) {
+ dlog(1,
+ "stop_pc %p changed to be resume_pc %s\n",
+ C2v(stop_pc), sym(resume_pc));
+ }
+ regcache_invalidate();
+}
+
+unsigned char valgrind_wait (char *ourstatus)
+{
+ int pid;
+ unsigned long wptid;
+ ThreadState *tst;
+ enum target_signal sig;
+
+ pid = VG_(getpid) ();
+ dlog(1, "enter valgrind_wait pid %d\n", pid);
+
+ regcache_invalidate();
+ valgrind_update_threads(pid);
+
+ /* in valgrind, we consider that a wait always succeeds with STOPPED 'T'
+ and with a signal TRAP (i.e. a breakpoint), unless there is
+ a signal to report. */
+ *ourstatus = 'T';
+ if (vki_signal_to_report == 0)
+ sig = TARGET_SIGNAL_TRAP;
+ else {
+ sig = target_signal_from_host(vki_signal_to_report);
+ vki_signal_to_report = 0;
+ }
+
+ if (vgdb_interrupted_tid != 0)
+ tst = VG_(get_ThreadState) (vgdb_interrupted_tid);
+ else
+ tst = VG_(get_ThreadState) (VG_(running_tid));
+ wptid = tst->os_state.lwpid;
+ /* we can only change the current_inferior when the wptid references
+ an existing thread. Otherwise, we are still in the init phase.
+ (hack similar to main thread hack in valgrind_update_threads) */
+ if (tst->os_state.lwpid)
+ current_inferior = gdb_id_to_thread (wptid);
+ stop_pc = (*the_low_target.get_pc) ();
+
+ dlog(1,
+ "exit valgrind_wait returns ptid %s stop_pc %s signal %d\n",
+ image_ptid (wptid), sym (stop_pc), sig);
+ return sig;
+}
+
+/* Fetch one register from valgrind VEX guest state. */
+static
+void fetch_register (int regno)
+{
+ int size;
+ ThreadState *tst = (ThreadState *) inferior_target_data (current_inferior);
+ ThreadId tid = tst->tid;
+
+ if (regno >= the_low_target.num_regs) {
+ dlog(0, "error fetch_register regno %d max %d\n",
+ regno, the_low_target.num_regs);
+ return;
+ }
+ size = register_size (regno);
+ if (size > 0) {
+ Bool mod;
+ char buf [size];
+ VG_(memset) (buf, 0, size); // registers not fetched will be seen as 0.
+ (*the_low_target.transfer_register) (tid, regno, buf,
+ valgrind_to_gdbserver, size, &mod);
+ // Note: the *mod received from transfer_register is not interesting.
+ // We are interested to see if the register data in the register cache is modified.
+ supply_register (regno, buf, &mod);
+ if (mod && VG_(debugLog_getLevel)() > 1) {
+ char bufimage [2*size + 1];
+ heximage (bufimage, buf, size);
+ dlog(2, "fetched register %d size %d name %s value %s tid %d status %s\n",
+ regno, size, the_low_target.reg_defs[regno].name, bufimage,
+ tid, VG_(name_of_ThreadStatus) (tst->status));
+ }
+ }
+}
+
+/* Fetch all registers, or just one, from the child process. */
+static
+void usr_fetch_inferior_registers (int regno)
+{
+ if (regno == -1 || regno == 0)
+ for (regno = 0; regno < the_low_target.num_regs; regno++)
+ fetch_register (regno);
+ else
+ fetch_register (regno);
+}
+
+/* Store our register values back into the inferior.
+ If REGNO is -1, do this for all registers.
+ Otherwise, REGNO specifies which register (so we can save time). */
+static
+void usr_store_inferior_registers (int regno)
+{
+ int size;
+ ThreadState *tst = (ThreadState *) inferior_target_data (current_inferior);
+ ThreadId tid = tst->tid;
+
+ if (regno >= 0) {
+
+ if (regno >= the_low_target.num_regs) {
+ dlog(0, "error store_register regno %d max %d\n",
+ regno, the_low_target.num_regs);
+ return;
+ }
+
+ size = register_size (regno);
+ if (size > 0) {
+ Bool mod;
+ Addr old_SP, new_SP;
+ char buf[size];
+
+ if (regno == the_low_target.stack_pointer_regno) {
+ /* When the stack pointer register is changed such that
+ the stack is extended, we better inform the tool of the
+ stack increase. This is needed in particular to avoid
+ spurious Memcheck errors during Inferior calls. So, we
+ save in old_SP the SP before the change. A change of
+ stack pointer is also assumed to have initialised this
+ new stack space. For the typical example of an inferior
+ call, gdb writes arguments on the stack, and then
+ changes the stack pointer. As the stack increase tool
+ function might mark it as undefined, we have to call it
+ at the good moment. */
+ VG_(memset) ((void *) &old_SP, 0, size);
+ (*the_low_target.transfer_register) (tid, regno, (void *) &old_SP,
+ valgrind_to_gdbserver, size, &mod);
+ }
+
+ VG_(memset) (buf, 0, size);
+ collect_register (regno, buf);
+ (*the_low_target.transfer_register) (tid, regno, buf,
+ gdbserver_to_valgrind, size, &mod);
+ if (mod && VG_(debugLog_getLevel)() > 1) {
+ char bufimage [2*size + 1];
+ heximage (bufimage, buf, size);
+ dlog(2,
+ "stored register %d size %d name %s value %s "
+ "tid %d status %s\n",
+ regno, size, the_low_target.reg_defs[regno].name, bufimage,
+ tid, VG_(name_of_ThreadStatus) (tst->status));
+ }
+ if (regno == the_low_target.stack_pointer_regno) {
+ VG_(memcpy) (&new_SP, buf, size);
+ if (old_SP > new_SP) {
+ Word delta = (Word)new_SP - (Word)old_SP;
+ dlog(1,
+ " stack increase by stack pointer changed from %p to %p "
+ "delta %ld\n",
+ (void*) old_SP, (void *) new_SP,
+ delta);
+ VG_TRACK( new_mem_stack_w_ECU, new_SP, -delta, 0 );
+ VG_TRACK( new_mem_stack, new_SP, -delta );
+ VG_TRACK( post_mem_write, Vg_CoreClientReq, tid,
+ new_SP, -delta);
+ }
+ }
+ }
+ }
+ else {
+ for (regno = 0; regno < the_low_target.num_regs; regno++)
+ usr_store_inferior_registers (regno);
+ }
+}
+
+void valgrind_fetch_registers (int regno)
+{
+ usr_fetch_inferior_registers (regno);
+}
+
+void valgrind_store_registers (int regno)
+{
+ usr_store_inferior_registers (regno);
+}
+
+int valgrind_read_memory (CORE_ADDR memaddr, unsigned char *myaddr, int len)
+{
+ const void *sourceaddr = C2v (memaddr);
+ dlog(2, "reading memory %p size %d\n", sourceaddr, len);
+ if (!VG_(am_is_valid_for_client_or_free_or_resvn) ((Addr) sourceaddr,
+ len, VKI_PROT_READ)) {
+ dlog(1, "error reading memory %p size %d\n", sourceaddr, len);
+ return -1;
+ }
+ VG_(memcpy) (myaddr, sourceaddr, len);
+ return 0;
+}
+
+int valgrind_write_memory (CORE_ADDR memaddr, const unsigned char *myaddr, int len)
+{
+ void *targetaddr = C2v (memaddr);
+ dlog(2, "writing memory %p size %d\n", targetaddr, len);
+ if (!VG_(am_is_valid_for_client_or_free_or_resvn) ((Addr)targetaddr,
+ len, VKI_PROT_WRITE)) {
+ dlog(1, "error writing memory %p size %d\n", targetaddr, len);
+ return -1;
+ }
+ if (len > 0) {
+ VG_(memcpy) (targetaddr, myaddr, len);
+ if (VG_(tdict).track_post_mem_write) {
+ /* Inform the tool of the post memwrite. Note that we do the
+ minimum necessary to avoid complains from e.g.
+ memcheck. The idea is that the debugger is as least
+ intrusive as possible. So, we do not inform of the pre
+ mem write (and in any case, this would cause problems with
+ memcheck that does not like our CorePart in
+ pre_mem_write. */
+ ThreadState *tst =
+ (ThreadState *) inferior_target_data (current_inferior);
+ ThreadId tid = tst->tid;
+ VG_(tdict).track_post_mem_write( Vg_CoreClientReq, tid,
+ (Addr) targetaddr, len );
+ }
+ }
+ return 0;
+}
+
+/* insert or remove a breakpoint */
+static
+int valgrind_point (Bool insert, char type, CORE_ADDR addr, int len)
+{
+ PointKind kind;
+ switch (type) {
+ case '0': /* implemented by inserting checks at each instruction in sb */
+ kind = software_breakpoint;
+ break;
+ case '1': /* hw breakpoint, same implementation as sw breakpoint */
+ kind = hardware_breakpoint;
+ break;
+ case '2':
+ kind = write_watchpoint;
+ break;
+ case '3':
+ kind = read_watchpoint;
+ break;
+ case '4':
+ kind = access_watchpoint;
+ break;
+ default:
+ vg_assert (0);
+ }
+
+ /* Attention: gdbserver convention differs: 0 means ok; 1 means not ok */
+ if (VG_(gdbserver_point) (kind, insert, addr, len))
+ return 0;
+ else
+ return 1; /* error or unsupported */
+}
+
+char* valgrind_target_xml (Bool shadow_mode)
+{
+ return (*the_low_target.target_xml) (shadow_mode);
+}
+
+int valgrind_insert_watchpoint (char type, CORE_ADDR addr, int len)
+{
+ return valgrind_point (/* insert */ True, type, addr, len);
+}
+
+int valgrind_remove_watchpoint (char type, CORE_ADDR addr, int len)
+{
+ return valgrind_point (/* insert*/ False, type, addr, len);
+}
+
+/* returns a pointer to the architecture state corresponding to
+ the provided register set: 0 => normal guest registers,
+ 1 => shadow1
+ 2 => shadow2
+*/
+VexGuestArchState* get_arch (int set, ThreadState* tst)
+{
+ switch (set) {
+ case 0: return &tst->arch.vex;
+ case 1: return &tst->arch.vex_shadow1;
+ case 2: return &tst->arch.vex_shadow2;
+ default: vg_assert(0);
+ }
+}
+
+static int non_shadow_num_regs = 0;
+static struct reg *non_shadow_reg_defs = NULL;
+void initialize_shadow_low(Bool shadow_mode)
+{
+ if (non_shadow_reg_defs == NULL) {
+ non_shadow_reg_defs = the_low_target.reg_defs;
+ non_shadow_num_regs = the_low_target.num_regs;
+ }
+
+ regcache_invalidate();
+ if (the_low_target.reg_defs != non_shadow_reg_defs) {
+ free (the_low_target.reg_defs);
+ }
+ if (shadow_mode) {
+ the_low_target.num_regs = 3 * non_shadow_num_regs;
+ the_low_target.reg_defs = build_shadow_arch (non_shadow_reg_defs, non_shadow_num_regs);
+ } else {
+ the_low_target.num_regs = non_shadow_num_regs;
+ the_low_target.reg_defs = non_shadow_reg_defs;
+ }
+ set_register_cache (the_low_target.reg_defs, the_low_target.num_regs);
+}
void set_desired_inferior (int use_general)
{
@@ -61,40 +577,6 @@
}
}
-int read_inferior_memory (CORE_ADDR memaddr, unsigned char *myaddr, int len)
-{
- int res;
- res = (*the_target->read_memory) (memaddr, myaddr, len);
- return res;
-}
-
-int write_inferior_memory (CORE_ADDR memaddr, const unsigned char *myaddr,
- int len)
-{
- /* Lacking cleanups, there is some potential for a memory leak if the
- write fails and we go through error(). Make sure that no more than
- one buffer is ever pending by making BUFFER static. */
- static unsigned char *buffer = 0;
- int res;
-
- if (buffer != NULL)
- free (buffer);
-
- buffer = malloc (len);
- VG_(memcpy) (buffer, myaddr, len);
- res = (*the_target->write_memory) (memaddr, buffer, len);
- free (buffer);
- buffer = NULL;
-
- return res;
-}
-
-void set_target_ops (struct target_ops *target)
-{
- the_target = (struct target_ops *) malloc (sizeof (*the_target));
- VG_(memcpy) (the_target, target, sizeof (*the_target));
-}
-
void* VG_(dmemcpy) ( void *d, const void *s, SizeT sz, Bool *mod )
{
if (VG_(memcmp) (d, s, sz)) {
@@ -119,3 +601,24 @@
else
vg_assert (0);
}
+
+void valgrind_initialize_target(void)
+{
+#if defined(VGA_x86)
+ x86_init_architecture(&the_low_target);
+#elif defined(VGA_amd64)
+ amd64_init_architecture(&the_low_target);
+#elif defined(VGA_arm)
+ arm_init_architecture(&the_low_target);
+#elif defined(VGA_ppc32)
+ ppc32_init_architecture(&the_low_target);
+#elif defined(VGA_ppc64)
+ ppc64_init_architecture(&the_low_target);
+#elif defined(VGA_s390x)
+ s390x_init_architecture(&the_low_target);
+#elif defined(VGA_mips32)
+ mips32_init_architecture(&the_low_target);
+#else
+ architecture missing in target.c valgrind_initialize_target
+#endif
+}
diff --git a/main/coregrind/m_gdbserver/target.h b/main/coregrind/m_gdbserver/target.h
index d657438..2cd41fd 100644
--- a/main/coregrind/m_gdbserver/target.h
+++ b/main/coregrind/m_gdbserver/target.h
@@ -1,6 +1,7 @@
-/* Target operations for the remote server for GDB.
- Copyright (C) 2002, 2003, 2004, 2005
+/* Target operations for the Valgrind remote server for GDB.
+ Copyright (C) 2002, 2003, 2004, 2005, 2012
Free Software Foundation, Inc.
+ Philippe Waroquiers.
Contributed by MontaVista Software.
@@ -25,18 +26,54 @@
#ifndef TARGET_H
#define TARGET_H
-/* This structure describes how to resume a particular thread (or
- all threads) based on the client's request. If thread is -1, then
- this entry applies to all threads. These are generally passed around
- as an array, and terminated by a thread == -1 entry. */
+/* This file defines the architecture independent Valgrind gdbserver
+ high level operations such as read memory, get/set registers, ...
+ These high level operations are called by the gdbserver
+ protocol implementation (e.g. typically server.c).
+
+ For some of these high level operations, target.c will call
+ low level operations dependent on the architecture.
+
+ For example, getting or setting the registers will work on a
+ register cache. The exact details of the registers (how much,
+ their size, etc) is not defined by target.c or the register cache.
+
+ Such architecture dependent information is defined by
+ valgrind_low.h/valgrind-low-xxxxx.c providing 'low level operations'
+ specific to the xxxxx architecture (for example,
+ valgrind-low-x86.c, valgrind-low-armc.c). */
+
+/* -------------------------------------------------------------------------- */
+/* ------------------------ Initialisation ---------------------------------- */
+/* -------------------------------------------------------------------------- */
+
+/* Initialize the Valgrind high target. This will in turn
+ initialise the low (architecture specific) target. */
+extern void valgrind_initialize_target(void);
+
+/* initialize or re-initialize the register set of the low target.
+ if shadow_mode, then (re-)define the normal and valgrind shadow registers
+ else (re-)define only the normal registers. */
+extern void initialize_shadow_low (Bool shadow_mode);
+
+/* Returns the name of the xml target description file.
+ returns NULL if no xml target description available.
+ if shadow_mode, then returns the xml target description
+ with the shadow registers
+ else returns the xml target description only for
+ the normal registers. */
+extern char* valgrind_target_xml (Bool shadow_mode);
+
+
+/* -------------------------------------------------------------------------- */
+/* --------------------------- Execution control ---------------------------- */
+/* -------------------------------------------------------------------------- */
+
+/* This structure describes how to resume the execution.
+ Currently, there is no way to resume only a specific thread. */
struct thread_resume
{
- unsigned long thread;
-
- /* If non-zero, leave this thread stopped. */
- int leave_stopped;
-
/* If non-zero, we want to single-step. */
int step;
@@ -44,114 +81,133 @@
int sig;
};
-struct target_ops
-{
- /* Return 1 iff the thread with process ID PID is alive. */
+/* Prepare to Resume (i.e. restart) the guest.
+ The resume info indicates how the resume will be done.
+ In case GDB has changed the program counter, valgrind_resume
+ will also ensure that the execution will be resumed at this
+ new program counter.
+ The Resume is really only executed once the gdbserver
+ returns (giving back the control to Valgrind). */
+extern void valgrind_resume (struct thread_resume *resume_info);
- int (*thread_alive) (unsigned long pid);
+/* When Valgrind gets the control, it will execute the guest
+ process till there is a reason to call the gdbserver
+ again (e.g. because a breakpoint is encountered or the
+ tool reports an error).
+ In such case, the executionof guest code stops, and the
+ control is given to gdbserver. Gdbserver will send a resume
+ reply packet to GDB.
- /* Resume the inferior process. */
+ valgrind_wait gets from Valgrind data structures the
+ information needed produce the resume reply for GDB:
+ a.o. OURSTATUS will be filled in with a response code to send to GDB.
- void (*resume) (struct thread_resume *resume_info);
+ Returns the signal which caused the process to stop, in the
+ remote protocol numbering (e.g. TARGET_SIGNAL_STOP), or the
+ exit code as an integer if *OURSTATUS is 'W'. */
+extern unsigned char valgrind_wait (char *outstatus);
- /* Wait for the inferior process to change state.
+/* When execution is stopped and gdbserver has control, more
+ info about the stop reason can be retrieved using the following
+ functions. */
- STATUS will be filled in with a response code to send to GDB.
+/* gets the addr at which a (possible) break must be ignored once.
+ If there is no such break to be ignored once, 0 is returned.
+ This is needed for the following case:
+ The user sets a break at address AAA.
+ The break is encountered. Then the user does stepi
+ (i.e. step one instruction).
+ In such a case, the already encountered break must be ignored
+ to ensure the stepi will advance by one instruction: a "break"
+ is implemented in valgrind by some helper code just after the
+ instruction mark at which the break is set. This helper code
+ verifies if either there is a break at the current PC
+ or if we are in stepping mode. If we are in stepping mode,
+ the already encountered break must be ignored once to advance
+ to the next instruction.
+ ??? need to check if this is *really* needed. */
+extern Addr valgrind_get_ignore_break_once(void);
- Returns the signal which caused the process to stop, in the
- remote protocol numbering (e.g. TARGET_SIGNAL_STOP), or the
- exit code as an integer if *STATUS is 'W'. */
+/* When addr > 0, ensures the next resume reply packet informs
+ gdb about the encountered watchpoint.
+ valgrind_stopped_by_watchpoint() will return 1 till reset.
+ Use addr 0x0 to reset. */
+extern void VG_(set_watchpoint_stop_address) (Addr addr);
- unsigned char (*wait) (char *status);
+/* Returns 1 if target was stopped due to a watchpoint hit, 0 otherwise. */
+extern int valgrind_stopped_by_watchpoint (void);
- /* Fetch registers from the inferior process.
+/* Returns the address associated with the watchpoint that hit, if any;
+ returns 0 otherwise. */
+extern CORE_ADDR valgrind_stopped_data_address (void);
- If REGNO is -1, fetch all registers; otherwise, fetch at least REGNO. */
+/* True if gdbserver is single stepping the valgrind process */
+extern Bool valgrind_single_stepping(void);
- void (*fetch_registers) (int regno);
+/* Set Valgrind in single stepping mode or not according to Bool. */
+extern void valgrind_set_single_stepping(Bool);
- /* Store registers to the inferior process.
+/* -------------------------------------------------------------------------- */
+/* ----------------- Examining/modifying data while stopped ----------------- */
+/* -------------------------------------------------------------------------- */
- If REGNO is -1, store all registers; otherwise, store at least REGNO. */
+/* Return 1 iff the thread with ID tid is alive. */
+extern int valgrind_thread_alive (unsigned long tid);
- void (*store_registers) (int regno);
+/* Allows to controls the thread (current_inferior) used for following
+ valgrind_(fetch|store)_registers calls.
+ If USE_GENERAL,
+ current_inferior is set to general_thread
+ else
+ current_inferior is set to step_thread or else cont_thread.
+ If the above gives no valid thread, then current_inferior is
+ set to the first valid thread. */
+extern void set_desired_inferior (int use_general);
- /* Read memory from the inferior process. This should generally be
- called through read_inferior_memory, which handles breakpoint shadowing.
+/* Fetch registers from the current_inferior thread.
+ If REGNO is -1, fetch all registers; otherwise, fetch at least REGNO. */
+extern void valgrind_fetch_registers (int regno);
- Read LEN bytes at MEMADDR into a buffer at MYADDR.
-
- Returns 0 on success and errno on failure. */
+/* Store registers to the current_inferior thread.
+ If REGNO is -1, store all registers; otherwise, store at least REGNO. */
+extern void valgrind_store_registers (int regno);
- int (*read_memory) (CORE_ADDR memaddr, unsigned char *myaddr, int len);
- /* Write memory to the inferior process. This should generally be
- called through write_inferior_memory, which handles breakpoint shadowing.
- Write LEN bytes from the buffer at MYADDR to MEMADDR.
+/* Read memory from the inferior process.
+ Read LEN bytes at MEMADDR into a buffer at MYADDR.
+ Returns 0 on success and errno on failure. */
+extern int valgrind_read_memory (CORE_ADDR memaddr,
+ unsigned char *myaddr, int len);
- Returns 0 on success and errno on failure. */
+/* Write memory to the inferior process.
+ Write LEN bytes from the buffer at MYADDR to MEMADDR.
+ Returns 0 on success and errno on failure. */
+extern int valgrind_write_memory (CORE_ADDR memaddr,
+ const unsigned char *myaddr, int len);
- int (*write_memory) (CORE_ADDR memaddr, const unsigned char *myaddr,
- int len);
- /* Send a signal to the inferior process, however is appropriate. */
- void (*send_signal) (int);
+/* Insert and remove a hardware watchpoint.
+ Returns 0 on success, -1 on failure and 1 on unsupported.
+ The type is coded as follows:
+ 2 = write watchpoint
+ 3 = read watchpoint
+ 4 = access watchpoint
+*/
+extern int valgrind_insert_watchpoint (char type, CORE_ADDR addr, int len);
+extern int valgrind_remove_watchpoint (char type, CORE_ADDR addr, int len);
- /* Returns the name of the xml target description file.
- returns NULL if no xml target description available. */
- char* (*target_xml)(void);
- /* Same but describes also the shadow registers. */
- char* (*shadow_target_xml)(void);
+/* -------------------------------------------------------------------------- */
+/* ----------- Utils functions for low level arch specific files ------------ */
+/* -------------------------------------------------------------------------- */
- /* Insert and remove a hardware watchpoint.
- Returns 0 on success, -1 on failure and 1 on unsupported.
- The type is coded as follows:
- 2 = write watchpoint
- 3 = read watchpoint
- 4 = access watchpoint
- */
-
- int (*insert_watchpoint) (char type, CORE_ADDR addr, int len);
- int (*remove_watchpoint) (char type, CORE_ADDR addr, int len);
-
- /* Returns 1 if target was stopped due to a watchpoint hit, 0 otherwise. */
-
- int (*stopped_by_watchpoint) (void);
-
- /* Returns the address associated with the watchpoint that hit, if any;
- returns 0 otherwise. */
-
- CORE_ADDR (*stopped_data_address) (void);
-
-};
-
-extern struct target_ops *the_target;
-
-void set_target_ops (struct target_ops *);
-
-#define detach_inferior() \
- (*the_target->detach) ()
-
-#define mythread_alive(pid) \
- (*the_target->thread_alive) (pid)
-
-#define fetch_inferior_registers(regno) \
- (*the_target->fetch_registers) (regno)
-
-#define store_inferior_registers(regno) \
- (*the_target->store_registers) (regno)
-
-#define mywait(statusp) \
- (*the_target->wait) (statusp)
-
-int read_inferior_memory (CORE_ADDR memaddr, unsigned char *myaddr, int len);
-
-int write_inferior_memory (CORE_ADDR memaddr, const unsigned char *myaddr,
- int len);
-
-void set_desired_inferior (int id);
+/* returns a pointer to the architecture state corresponding to
+ the provided register set: 0 => normal guest registers,
+ 1 => shadow1
+ 2 => shadow2
+*/
+extern VexGuestArchState* get_arch (int set, ThreadState* tst);
/* like memcpy but first check if content of destination and source
differs. If no difference, no copy is done, *mod set to False.
@@ -173,4 +229,6 @@
SizeT sz,
Bool *mod);
+
+
#endif /* TARGET_H */
diff --git a/main/coregrind/m_gdbserver/valgrind-low-amd64.c b/main/coregrind/m_gdbserver/valgrind-low-amd64.c
index 0dc0382..7de55a0 100644
--- a/main/coregrind/m_gdbserver/valgrind-low-amd64.c
+++ b/main/coregrind/m_gdbserver/valgrind-low-amd64.c
@@ -27,7 +27,7 @@
#include "regcache.h"
#include "pub_core_aspacemgr.h"
-#include "pub_tool_machine.h"
+#include "pub_core_machine.h"
#include "pub_core_threadstate.h"
#include "pub_core_transtab.h"
#include "pub_core_gdbserver.h"
@@ -41,7 +41,7 @@
/* below loosely inspired from file generated with gdb regdat.sh */
-struct reg regs[] = {
+static struct reg regs[] = {
{ "rax", 0, 64 },
{ "rbx", 64, 64 },
{ "rcx", 128, 64 },
@@ -100,11 +100,29 @@
{ "xmm15", 4128, 128 },
{ "mxcsr", 4256, 32 },
#if defined(VGO_linux)
- { "orig_rax", 4288, 64 }
+ { "orig_rax", 4288, 64 },
#endif
+ { "ymm0h", 4352, 128 }, // The ymm?h registers only to be given to GDB
+ { "ymm1h", 4480, 128 }, // if Valgrind is running with AVX instructions.
+ { "ymm2h", 4608, 128 },
+ { "ymm3h", 4736, 128 },
+ { "ymm4h", 4864, 128 },
+ { "ymm5h", 4992, 128 },
+ { "ymm6h", 5120, 128 },
+ { "ymm7h", 5248, 128 },
+ { "ymm8h", 5376, 128 },
+ { "ymm9h", 5504, 128 },
+ { "ymm10h", 5632, 128 },
+ { "ymm11h", 5760, 128 },
+ { "ymm12h", 5888, 128 },
+ { "ymm13h", 6016, 128 },
+ { "ymm14h", 6144, 128 },
+ { "ymm15h", 6272, 128 }
};
static const char *expedite_regs[] = { "rbp", "rsp", "rip", 0 };
-#define num_regs (sizeof (regs) / sizeof (regs[0]))
+#define max_num_regs (sizeof (regs) / sizeof (regs[0]))
+static int dyn_num_regs; // if no AVX, we have to give less registers to gdb.
+
static
CORE_ADDR get_pc (void)
@@ -135,8 +153,8 @@
transfer_direction dir, int size, Bool *mod)
{
ThreadState* tst = VG_(get_ThreadState)(tid);
- int set = abs_regno / num_regs;
- int regno = abs_regno % num_regs;
+ int set = abs_regno / dyn_num_regs;
+ int regno = abs_regno % dyn_num_regs;
*mod = False;
VexGuestAMD64State* amd64 = (VexGuestAMD64State*) get_arch (set, tst);
@@ -160,16 +178,7 @@
case 13: VG_(transfer) (&amd64->guest_R13, buf, dir, size, mod); break;
case 14: VG_(transfer) (&amd64->guest_R14, buf, dir, size, mod); break;
case 15: VG_(transfer) (&amd64->guest_R15, buf, dir, size, mod); break;
- case 16:
- VG_(transfer) (&amd64->guest_RIP, buf, dir, size, mod);
- if (*mod && VG_(debugLog_getLevel)() > 2) {
- char bufimage [2*sizeof(amd64->guest_IP_AT_SYSCALL) + 1];
- heximage (bufimage,
- (char *) &amd64->guest_IP_AT_SYSCALL,
- sizeof(amd64->guest_IP_AT_SYSCALL));
- dlog(3, "guest_IP_AT_SYSCALL %s\n", bufimage);
- }
- break;
+ case 16: VG_(transfer) (&amd64->guest_RIP, buf, dir, size, mod); break;
case 17:
if (dir == valgrind_to_gdbserver) {
ULong rflags;
@@ -251,22 +260,22 @@
case 37: *mod = False; break; // GDBTD ??? equivalent of foseg
case 38: *mod = False; break; // GDBTD ??? equivalent of fooff
case 39: *mod = False; break; // GDBTD ??? equivalent of fop
- case 40: VG_(transfer) (&amd64->guest_XMM0, buf, dir, size, mod); break;
- case 41: VG_(transfer) (&amd64->guest_XMM1, buf, dir, size, mod); break;
- case 42: VG_(transfer) (&amd64->guest_XMM2, buf, dir, size, mod); break;
- case 43: VG_(transfer) (&amd64->guest_XMM3, buf, dir, size, mod); break;
- case 44: VG_(transfer) (&amd64->guest_XMM4, buf, dir, size, mod); break;
- case 45: VG_(transfer) (&amd64->guest_XMM5, buf, dir, size, mod); break;
- case 46: VG_(transfer) (&amd64->guest_XMM6, buf, dir, size, mod); break;
- case 47: VG_(transfer) (&amd64->guest_XMM7, buf, dir, size, mod); break;
- case 48: VG_(transfer) (&amd64->guest_XMM8, buf, dir, size, mod); break;
- case 49: VG_(transfer) (&amd64->guest_XMM9, buf, dir, size, mod); break;
- case 50: VG_(transfer) (&amd64->guest_XMM10, buf, dir, size, mod); break;
- case 51: VG_(transfer) (&amd64->guest_XMM11, buf, dir, size, mod); break;
- case 52: VG_(transfer) (&amd64->guest_XMM12, buf, dir, size, mod); break;
- case 53: VG_(transfer) (&amd64->guest_XMM13, buf, dir, size, mod); break;
- case 54: VG_(transfer) (&amd64->guest_XMM14, buf, dir, size, mod); break;
- case 55: VG_(transfer) (&amd64->guest_XMM15, buf, dir, size, mod); break;
+ case 40: VG_(transfer) (&amd64->guest_YMM0[0], buf, dir, size, mod); break;
+ case 41: VG_(transfer) (&amd64->guest_YMM1[0], buf, dir, size, mod); break;
+ case 42: VG_(transfer) (&amd64->guest_YMM2[0], buf, dir, size, mod); break;
+ case 43: VG_(transfer) (&amd64->guest_YMM3[0], buf, dir, size, mod); break;
+ case 44: VG_(transfer) (&amd64->guest_YMM4[0], buf, dir, size, mod); break;
+ case 45: VG_(transfer) (&amd64->guest_YMM5[0], buf, dir, size, mod); break;
+ case 46: VG_(transfer) (&amd64->guest_YMM6[0], buf, dir, size, mod); break;
+ case 47: VG_(transfer) (&amd64->guest_YMM7[0], buf, dir, size, mod); break;
+ case 48: VG_(transfer) (&amd64->guest_YMM8[0], buf, dir, size, mod); break;
+ case 49: VG_(transfer) (&amd64->guest_YMM9[0], buf, dir, size, mod); break;
+ case 50: VG_(transfer) (&amd64->guest_YMM10[0], buf, dir, size, mod); break;
+ case 51: VG_(transfer) (&amd64->guest_YMM11[0], buf, dir, size, mod); break;
+ case 52: VG_(transfer) (&amd64->guest_YMM12[0], buf, dir, size, mod); break;
+ case 53: VG_(transfer) (&amd64->guest_YMM13[0], buf, dir, size, mod); break;
+ case 54: VG_(transfer) (&amd64->guest_YMM14[0], buf, dir, size, mod); break;
+ case 55: VG_(transfer) (&amd64->guest_YMM15[0], buf, dir, size, mod); break;
case 56:
if (dir == valgrind_to_gdbserver) {
// vex only models the rounding bits (see libvex_guest_x86.h)
@@ -278,29 +287,83 @@
}
break;
case 57: *mod = False; break; // GDBTD???? VEX equivalent { "orig_rax"},
+ case 58: VG_(transfer) (&amd64->guest_YMM0[4], buf, dir, size, mod); break;
+ case 59: VG_(transfer) (&amd64->guest_YMM1[4], buf, dir, size, mod); break;
+ case 60: VG_(transfer) (&amd64->guest_YMM2[4], buf, dir, size, mod); break;
+ case 61: VG_(transfer) (&amd64->guest_YMM3[4], buf, dir, size, mod); break;
+ case 62: VG_(transfer) (&amd64->guest_YMM4[4], buf, dir, size, mod); break;
+ case 63: VG_(transfer) (&amd64->guest_YMM5[4], buf, dir, size, mod); break;
+ case 64: VG_(transfer) (&amd64->guest_YMM6[4], buf, dir, size, mod); break;
+ case 65: VG_(transfer) (&amd64->guest_YMM7[4], buf, dir, size, mod); break;
+ case 66: VG_(transfer) (&amd64->guest_YMM8[4], buf, dir, size, mod); break;
+ case 67: VG_(transfer) (&amd64->guest_YMM9[4], buf, dir, size, mod); break;
+ case 68: VG_(transfer) (&amd64->guest_YMM10[4], buf, dir, size, mod); break;
+ case 69: VG_(transfer) (&amd64->guest_YMM11[4], buf, dir, size, mod); break;
+ case 70: VG_(transfer) (&amd64->guest_YMM12[4], buf, dir, size, mod); break;
+ case 71: VG_(transfer) (&amd64->guest_YMM13[4], buf, dir, size, mod); break;
+ case 72: VG_(transfer) (&amd64->guest_YMM14[4], buf, dir, size, mod); break;
+ case 73: VG_(transfer) (&amd64->guest_YMM15[4], buf, dir, size, mod); break;
default: vg_assert(0);
}
}
+static
+Bool have_avx(void)
+{
+ VexArch va;
+ VexArchInfo vai;
+ VG_(machine_get_VexArchInfo) (&va, &vai);
+ return (vai.hwcaps & VEX_HWCAPS_AMD64_AVX ? True : False);
+}
+static
+char* target_xml (Bool shadow_mode)
+{
+ if (shadow_mode) {
+#if defined(VGO_linux)
+ if (have_avx())
+ return "amd64-avx-linux-valgrind.xml";
+ else
+ return "amd64-linux-valgrind.xml";
+#else
+ if (have_avx())
+ return "amd64-avx-coresse-valgrind.xml";
+ else
+ return "amd64-coresse-valgrind.xml";
+#endif
+ } else {
+#if defined(VGO_linux)
+ if (have_avx())
+ return "amd64-avx-linux.xml";
+ else
+ return NULL;
+#else
+ if (have_avx())
+ return "amd64-avx-coresse.xml";
+ else
+ return NULL;
+#endif
+ }
+}
+
static struct valgrind_target_ops low_target = {
- num_regs,
+ -1, // Must be computed at init time.
regs,
7, //RSP
transfer_register,
get_pc,
set_pc,
"amd64",
- NULL, // target_xml not needed.
-#if defined(VGO_linux)
- "amd64-linux-valgrind.xml"
-#else
- "amd64-coresse-valgrind.xml"
-#endif
+ target_xml
};
void amd64_init_architecture (struct valgrind_target_ops *target)
{
*target = low_target;
- set_register_cache (regs, num_regs);
+ if (have_avx())
+ dyn_num_regs = max_num_regs;
+ else
+ dyn_num_regs = max_num_regs - 16; // remove the AVX "high" registers.
+ target->num_regs = dyn_num_regs;
+ set_register_cache (regs, dyn_num_regs);
gdbserver_expedite_regs = expedite_regs;
}
diff --git a/main/coregrind/m_gdbserver/valgrind-low-arm.c b/main/coregrind/m_gdbserver/valgrind-low-arm.c
index 5767793..a3ea36f 100644
--- a/main/coregrind/m_gdbserver/valgrind-low-arm.c
+++ b/main/coregrind/m_gdbserver/valgrind-low-arm.c
@@ -37,7 +37,7 @@
#include "libvex_guest_arm.h"
-struct reg regs[] = {
+static struct reg regs[] = {
{ "r0", 0, 32 },
{ "r1", 32, 32 },
{ "r2", 64, 32 },
@@ -277,6 +277,16 @@
}
}
+static
+char* target_xml (Bool shadow_mode)
+{
+ if (shadow_mode) {
+ return "arm-with-vfpv3-valgrind.xml";
+ } else {
+ return "arm-with-vfpv3.xml";
+ }
+}
+
static struct valgrind_target_ops low_target = {
num_regs,
regs,
@@ -285,8 +295,7 @@
get_pc,
set_pc,
"arm",
- "arm-with-vfpv3.xml",
- "arm-with-vfpv3-valgrind.xml"
+ target_xml
};
void arm_init_architecture (struct valgrind_target_ops *target)
diff --git a/main/coregrind/m_gdbserver/valgrind-low-mips32.c b/main/coregrind/m_gdbserver/valgrind-low-mips32.c
new file mode 100644
index 0000000..cf2d603
--- /dev/null
+++ b/main/coregrind/m_gdbserver/valgrind-low-mips32.c
@@ -0,0 +1,258 @@
+/* Low level interface to valgrind, for the remote server for GDB integrated
+ in valgrind.
+ Copyright (C) 2012
+ Free Software Foundation, Inc.
+
+ This file is part of VALGRIND.
+ It has been inspired from a file from gdbserver in gdb 6.6.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#include "server.h"
+#include "target.h"
+#include "regdef.h"
+#include "regcache.h"
+
+#include "pub_core_aspacemgr.h"
+#include "pub_tool_machine.h"
+#include "pub_core_threadstate.h"
+#include "pub_core_transtab.h"
+#include "pub_core_gdbserver.h"
+
+#include "valgrind_low.h"
+
+#include "libvex_guest_mips32.h"
+
+static struct reg regs[] = {
+ { "r0", 0, 32 },
+ { "r1", 32, 32 },
+ { "r2", 64, 32 },
+ { "r3", 96, 32 },
+ { "r4", 128, 32 },
+ { "r5", 160, 32 },
+ { "r6", 192, 32 },
+ { "r7", 224, 32 },
+ { "r8", 256, 32 },
+ { "r9", 288, 32 },
+ { "r10", 320, 32 },
+ { "r11", 352, 32 },
+ { "r12", 384, 32 },
+ { "r13", 416, 32 },
+ { "r14", 448, 32 },
+ { "r15", 480, 32 },
+ { "r16", 512, 32 },
+ { "r17", 544, 32 },
+ { "r18", 576, 32 },
+ { "r19", 608, 32 },
+ { "r20", 640, 32 },
+ { "r21", 672, 32 },
+ { "r22", 704, 32 },
+ { "r23", 736, 32 },
+ { "r24", 768, 32 },
+ { "r25", 800, 32 },
+ { "r26", 832, 32 },
+ { "r27", 864, 32 },
+ { "r28", 896, 32 },
+ { "r29", 928, 32 },
+ { "r30", 960, 32 },
+ { "r31", 992, 32 },
+ { "status", 1024, 32 },
+ { "lo", 1056, 32 },
+ { "hi", 1088, 32 },
+ { "badvaddr", 1120, 32 },
+ { "cause", 1152, 32 },
+ { "pc", 1184, 32 },
+ { "f0", 1216, 32 },
+ { "f1", 1248, 32 },
+ { "f2", 1280, 32 },
+ { "f3", 1312, 32 },
+ { "f4", 1344, 32 },
+ { "f5", 1376, 32 },
+ { "f6", 1408, 32 },
+ { "f7", 1440, 32 },
+ { "f8", 1472, 32 },
+ { "f9", 1504, 32 },
+ { "f10", 1536, 32 },
+ { "f11", 1568, 32 },
+ { "f12", 1600, 32 },
+ { "f13", 1632, 32 },
+ { "f14", 1664, 32 },
+ { "f15", 1696, 32 },
+ { "f16", 1728, 32 },
+ { "f17", 1760, 32 },
+ { "f18", 1792, 32 },
+ { "f19", 1824, 32 },
+ { "f20", 1856, 32 },
+ { "f21", 1888, 32 },
+ { "f22", 1920, 32 },
+ { "f23", 1952, 32 },
+ { "f24", 1984, 32 },
+ { "f25", 2016, 32 },
+ { "f26", 2048, 32 },
+ { "f27", 2080, 32 },
+ { "f28", 2112, 32 },
+ { "f29", 2144, 32 },
+ { "f30", 2176, 32 },
+ { "f31", 2208, 32 },
+ { "fcsr", 2240, 32 },
+ { "fir", 2272, 32 },
+ { "restart", 2304, 32 },
+};
+
+#define num_regs (sizeof (regs) / sizeof (regs[0]))
+
+static const char *expedite_regs[] = { "r29", "pc", 0 };
+
+static
+CORE_ADDR get_pc (void)
+{
+ unsigned long pc;
+
+ collect_register_by_name ("pc", &pc);
+
+ dlog(1, "stop pc is %p\n", (void *) pc);
+ return pc;
+}
+
+static
+void set_pc (CORE_ADDR newpc)
+{
+ Bool mod;
+ supply_register_by_name ("pc", &newpc, &mod);
+ if (mod)
+ dlog(1, "set pc to %p\n", C2v (newpc));
+ else
+ dlog(1, "set pc not changed %p\n", C2v (newpc));
+}
+
+/* store registers in the guest state (gdbserver_to_valgrind)
+ or fetch register from the guest state (valgrind_to_gdbserver). */
+static
+void transfer_register (ThreadId tid, int abs_regno, void * buf,
+ transfer_direction dir, int size, Bool *mod)
+{
+ ThreadState* tst = VG_(get_ThreadState)(tid);
+ int set = abs_regno / num_regs;
+ int regno = abs_regno % num_regs;
+ *mod = False;
+
+ VexGuestMIPS32State* mips1 = (VexGuestMIPS32State*) get_arch (set, tst);
+
+ switch (regno) {
+ case 0: VG_(transfer) (&mips1->guest_r0, buf, dir, size, mod); break;
+ case 1: VG_(transfer) (&mips1->guest_r1, buf, dir, size, mod); break;
+ case 2: VG_(transfer) (&mips1->guest_r2, buf, dir, size, mod); break;
+ case 3: VG_(transfer) (&mips1->guest_r3, buf, dir, size, mod); break;
+ case 4: VG_(transfer) (&mips1->guest_r4, buf, dir, size, mod); break;
+ case 5: VG_(transfer) (&mips1->guest_r5, buf, dir, size, mod); break;
+ case 6: VG_(transfer) (&mips1->guest_r6, buf, dir, size, mod); break;
+ case 7: VG_(transfer) (&mips1->guest_r7, buf, dir, size, mod); break;
+ case 8: VG_(transfer) (&mips1->guest_r8, buf, dir, size, mod); break;
+ case 9: VG_(transfer) (&mips1->guest_r9, buf, dir, size, mod); break;
+ case 10: VG_(transfer) (&mips1->guest_r10, buf, dir, size, mod); break;
+ case 11: VG_(transfer) (&mips1->guest_r11, buf, dir, size, mod); break;
+ case 12: VG_(transfer) (&mips1->guest_r12, buf, dir, size, mod); break;
+ case 13: VG_(transfer) (&mips1->guest_r13, buf, dir, size, mod); break;
+ case 14: VG_(transfer) (&mips1->guest_r14, buf, dir, size, mod); break;
+ case 15: VG_(transfer) (&mips1->guest_r15, buf, dir, size, mod); break;
+ case 16: VG_(transfer) (&mips1->guest_r16, buf, dir, size, mod); break;
+ case 17: VG_(transfer) (&mips1->guest_r17, buf, dir, size, mod); break;
+ case 18: VG_(transfer) (&mips1->guest_r18, buf, dir, size, mod); break;
+ case 19: VG_(transfer) (&mips1->guest_r19, buf, dir, size, mod); break;
+ case 20: VG_(transfer) (&mips1->guest_r20, buf, dir, size, mod); break;
+ case 21: VG_(transfer) (&mips1->guest_r21, buf, dir, size, mod); break;
+ case 22: VG_(transfer) (&mips1->guest_r22, buf, dir, size, mod); break;
+ case 23: VG_(transfer) (&mips1->guest_r23, buf, dir, size, mod); break;
+ case 24: VG_(transfer) (&mips1->guest_r24, buf, dir, size, mod); break;
+ case 25: VG_(transfer) (&mips1->guest_r25, buf, dir, size, mod); break;
+ case 26: VG_(transfer) (&mips1->guest_r26, buf, dir, size, mod); break;
+ case 27: VG_(transfer) (&mips1->guest_r27, buf, dir, size, mod); break;
+ case 28: VG_(transfer) (&mips1->guest_r28, buf, dir, size, mod); break;
+ case 29: VG_(transfer) (&mips1->guest_r29, buf, dir, size, mod); break;
+ case 30: VG_(transfer) (&mips1->guest_r30, buf, dir, size, mod); break;
+ case 31: VG_(transfer) (&mips1->guest_r31, buf, dir, size, mod); break;
+ case 32: *mod = False; break; // GDBTD???? VEX { "status", 1024, 32 },
+ case 33: VG_(transfer) (&mips1->guest_LO, buf, dir, size, mod); break;
+ case 34: VG_(transfer) (&mips1->guest_HI, buf, dir, size, mod); break;
+ case 35: *mod = False; break; // GDBTD???? VEX { "badvaddr", 1120, 32 },
+ case 36: *mod = False; break; // GDBTD???? VEX { "cause", 1152, 32 },
+ case 37: VG_(transfer) (&mips1->guest_PC, buf, dir, size, mod); break;
+ case 38: VG_(transfer) (&mips1->guest_f0, buf, dir, size, mod); break;
+ case 39: VG_(transfer) (&mips1->guest_f1, buf, dir, size, mod); break;
+ case 40: VG_(transfer) (&mips1->guest_f2, buf, dir, size, mod); break;
+ case 41: VG_(transfer) (&mips1->guest_f3, buf, dir, size, mod); break;
+ case 42: VG_(transfer) (&mips1->guest_f4, buf, dir, size, mod); break;
+ case 43: VG_(transfer) (&mips1->guest_f5, buf, dir, size, mod); break;
+ case 44: VG_(transfer) (&mips1->guest_f6, buf, dir, size, mod); break;
+ case 45: VG_(transfer) (&mips1->guest_f7, buf, dir, size, mod); break;
+ case 46: VG_(transfer) (&mips1->guest_f8, buf, dir, size, mod); break;
+ case 47: VG_(transfer) (&mips1->guest_f9, buf, dir, size, mod); break;
+ case 48: VG_(transfer) (&mips1->guest_f10, buf, dir, size, mod); break;
+ case 49: VG_(transfer) (&mips1->guest_f11, buf, dir, size, mod); break;
+ case 50: VG_(transfer) (&mips1->guest_f12, buf, dir, size, mod); break;
+ case 51: VG_(transfer) (&mips1->guest_f13, buf, dir, size, mod); break;
+ case 52: VG_(transfer) (&mips1->guest_f14, buf, dir, size, mod); break;
+ case 53: VG_(transfer) (&mips1->guest_f15, buf, dir, size, mod); break;
+ case 54: VG_(transfer) (&mips1->guest_f16, buf, dir, size, mod); break;
+ case 55: VG_(transfer) (&mips1->guest_f17, buf, dir, size, mod); break;
+ case 56: VG_(transfer) (&mips1->guest_f18, buf, dir, size, mod); break;
+ case 57: VG_(transfer) (&mips1->guest_f19, buf, dir, size, mod); break;
+ case 58: VG_(transfer) (&mips1->guest_f20, buf, dir, size, mod); break;
+ case 59: VG_(transfer) (&mips1->guest_f21, buf, dir, size, mod); break;
+ case 60: VG_(transfer) (&mips1->guest_f22, buf, dir, size, mod); break;
+ case 61: VG_(transfer) (&mips1->guest_f23, buf, dir, size, mod); break;
+ case 62: VG_(transfer) (&mips1->guest_f24, buf, dir, size, mod); break;
+ case 63: VG_(transfer) (&mips1->guest_f25, buf, dir, size, mod); break;
+ case 64: VG_(transfer) (&mips1->guest_f26, buf, dir, size, mod); break;
+ case 65: VG_(transfer) (&mips1->guest_f27, buf, dir, size, mod); break;
+ case 66: VG_(transfer) (&mips1->guest_f28, buf, dir, size, mod); break;
+ case 67: VG_(transfer) (&mips1->guest_f29, buf, dir, size, mod); break;
+ case 68: VG_(transfer) (&mips1->guest_f30, buf, dir, size, mod); break;
+ case 69: VG_(transfer) (&mips1->guest_f31, buf, dir, size, mod); break;
+ case 70: VG_(transfer) (&mips1->guest_FCSR, buf, dir, size, mod); break;
+ case 71: VG_(transfer) (&mips1->guest_FIR, buf, dir, size, mod); break;
+ case 72: *mod = False; break; // GDBTD???? VEX{ "restart", 2304, 32 },
+ default: VG_(printf)("regno: %d\n", regno); vg_assert(0);
+ }
+}
+
+static
+char* target_xml (Bool shadow_mode)
+{
+ if (shadow_mode) {
+ return "mips-linux-valgrind.xml";
+ } else {
+ return "mips-linux.xml";
+ }
+}
+
+static struct valgrind_target_ops low_target = {
+ num_regs,
+ regs,
+ 29, //sp = r29, which is register offset 29 in regs
+ transfer_register,
+ get_pc,
+ set_pc,
+ "mips",
+ target_xml
+};
+
+void mips32_init_architecture (struct valgrind_target_ops *target)
+{
+ *target = low_target;
+ set_register_cache (regs, num_regs);
+ gdbserver_expedite_regs = expedite_regs;
+}
diff --git a/main/coregrind/m_gdbserver/valgrind-low-ppc32.c b/main/coregrind/m_gdbserver/valgrind-low-ppc32.c
index a7e282e..9f2f36e 100644
--- a/main/coregrind/m_gdbserver/valgrind-low-ppc32.c
+++ b/main/coregrind/m_gdbserver/valgrind-low-ppc32.c
@@ -39,7 +39,7 @@
/* this is only the basic set of registers.
Need to look at what is the exact ppc32 model to support.
*/
-struct reg regs[] = {
+static struct reg regs[] = {
{ "r0", 0, 32 },
{ "r1", 32, 32 },
{ "r2", 64, 32 },
@@ -322,6 +322,16 @@
}
}
+static
+char* target_xml (Bool shadow_mode)
+{
+ if (shadow_mode) {
+ return "powerpc-altivec32l-valgrind.xml";
+ } else {
+ return "powerpc-altivec32l.xml";
+ }
+}
+
static struct valgrind_target_ops low_target = {
num_regs,
regs,
@@ -330,8 +340,7 @@
get_pc,
set_pc,
"ppc32",
- "powerpc-altivec32l.xml",
- "powerpc-altivec32l-valgrind.xml"
+ target_xml
};
void ppc32_init_architecture (struct valgrind_target_ops *target)
diff --git a/main/coregrind/m_gdbserver/valgrind-low-ppc64.c b/main/coregrind/m_gdbserver/valgrind-low-ppc64.c
index f2fdbec..9b1a358 100644
--- a/main/coregrind/m_gdbserver/valgrind-low-ppc64.c
+++ b/main/coregrind/m_gdbserver/valgrind-low-ppc64.c
@@ -36,7 +36,7 @@
#include "libvex_guest_ppc64.h"
-struct reg regs[] = {
+static struct reg regs[] = {
{ "r0", 0, 64 },
{ "r1", 64, 64 },
{ "r2", 128, 64 },
@@ -319,6 +319,16 @@
}
}
+static
+char* target_xml (Bool shadow_mode)
+{
+ if (shadow_mode) {
+ return "powerpc-altivec64l-valgrind.xml";
+ } else {
+ return "powerpc-altivec64l.xml";
+ }
+}
+
static struct valgrind_target_ops low_target = {
num_regs,
regs,
@@ -327,8 +337,7 @@
get_pc,
set_pc,
"ppc64",
- "powerpc-altivec64l.xml",
- "powerpc-altivec64l-valgrind.xml"
+ target_xml
};
void ppc64_init_architecture (struct valgrind_target_ops *target)
diff --git a/main/coregrind/m_gdbserver/valgrind-low-s390x.c b/main/coregrind/m_gdbserver/valgrind-low-s390x.c
index baa3ffc..017a402 100644
--- a/main/coregrind/m_gdbserver/valgrind-low-s390x.c
+++ b/main/coregrind/m_gdbserver/valgrind-low-s390x.c
@@ -36,7 +36,7 @@
#include "libvex_guest_s390x.h"
-struct reg regs[] = {
+static struct reg regs[] = {
{ "pswm", 0, 64 },
{ "pswa", 64, 64 },
{ "r0", 128, 64 },
@@ -88,6 +88,7 @@
{ "f13", 2528, 64 },
{ "f14", 2592, 64 },
{ "f15", 2656, 64 },
+ { "orig_r2", 2720, 64 },
};
static const char *expedite_regs[] = { "r14", "r15", "pswa", 0 };
#define num_regs (sizeof (regs) / sizeof (regs[0]))
@@ -181,10 +182,21 @@
case 48: VG_(transfer) (&s390x->guest_f13, buf, dir, size, mod); break;
case 49: VG_(transfer) (&s390x->guest_f14, buf, dir, size, mod); break;
case 50: VG_(transfer) (&s390x->guest_f15, buf, dir, size, mod); break;
+ case 51: *mod = False; break; //GDBTD??? { "orig_r2", 0, 64 },
default: vg_assert(0);
}
}
+static
+char* target_xml (Bool shadow_mode)
+{
+ if (shadow_mode) {
+ return "s390x-generic-valgrind.xml";
+ } else {
+ return "s390x-generic.xml";
+ }
+}
+
static struct valgrind_target_ops low_target = {
num_regs,
regs,
@@ -193,8 +205,7 @@
get_pc,
set_pc,
"s390x",
- NULL, // target_xml not needed.
- NULL // no xml shadow target description (yet?)
+ target_xml
};
void s390x_init_architecture (struct valgrind_target_ops *target)
diff --git a/main/coregrind/m_gdbserver/valgrind-low-x86.c b/main/coregrind/m_gdbserver/valgrind-low-x86.c
index 89ef329..50d3193 100644
--- a/main/coregrind/m_gdbserver/valgrind-low-x86.c
+++ b/main/coregrind/m_gdbserver/valgrind-low-x86.c
@@ -137,16 +137,7 @@
case 5: VG_(transfer) (&x86->guest_EBP, buf, dir, size, mod); break;
case 6: VG_(transfer) (&x86->guest_ESI, buf, dir, size, mod); break;
case 7: VG_(transfer) (&x86->guest_EDI, buf, dir, size, mod); break;
- case 8:
- VG_(transfer) (&x86->guest_EIP, buf, dir, size, mod);
- if (*mod && VG_(debugLog_getLevel)() > 2) {
- char bufimage [2*sizeof(x86->guest_IP_AT_SYSCALL) + 1];
- heximage (bufimage,
- (char *) &x86->guest_IP_AT_SYSCALL,
- sizeof(x86->guest_IP_AT_SYSCALL));
- dlog(3, "guest_IP_AT_SYSCALL %s\n", bufimage);
- }
- break;
+ case 8: VG_(transfer) (&x86->guest_EIP, buf, dir, size, mod); break;
case 9:
if (dir == valgrind_to_gdbserver) {
UInt eflags;
@@ -252,6 +243,20 @@
}
}
+static
+char* target_xml (Bool shadow_mode)
+{
+ if (shadow_mode) {
+#if defined(VGO_linux)
+ return "i386-linux-valgrind.xml";
+#else
+ return "i386-coresse-valgrind.xml";
+#endif
+ } else {
+ return NULL;
+ }
+}
+
static struct valgrind_target_ops low_target = {
num_regs,
regs,
@@ -260,12 +265,7 @@
get_pc,
set_pc,
"i386",
- NULL, // target_xml not needed.
-#if defined(VGO_linux)
- "i386-linux-valgrind.xml"
-#else
- "i386-coresse-valgrind.xml"
-#endif
+ target_xml
};
void x86_init_architecture (struct valgrind_target_ops *target)
diff --git a/main/coregrind/m_gdbserver/valgrind-low.c b/main/coregrind/m_gdbserver/valgrind-low.c
deleted file mode 100644
index 5d3f708..0000000
--- a/main/coregrind/m_gdbserver/valgrind-low.c
+++ /dev/null
@@ -1,639 +0,0 @@
-/* Low level interface to valgrind, for the remote server for GDB integrated
- in valgrind.
- Copyright (C) 2011
- Free Software Foundation, Inc.
-
- This file is part of VALGRIND.
- It has been inspired from a file from gdbserver in gdb 6.6.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA. */
-
-#include "server.h"
-#include "target.h"
-#include "regdef.h"
-#include "regcache.h"
-#include "valgrind_low.h"
-#include "gdb/signals.h"
-#include "pub_core_aspacemgr.h"
-#include "pub_tool_machine.h"
-#include "pub_core_threadstate.h"
-#include "pub_core_transtab.h"
-#include "pub_core_gdbserver.h"
-#include "pub_tool_debuginfo.h"
-
-/* the_low_target defines the architecture specific aspects depending
- on the cpu */
-static struct valgrind_target_ops the_low_target;
-
-/* builds an image of bin according to byte order of the architecture
- Useful for register and int image */
-char* heximage (char *buf, char *bin, int count)
-{
-#if defined(VGA_x86) || defined(VGA_amd64)
- char rev[count];
- /* note: no need for trailing \0, length is known with count */
- int i;
- for (i = 0; i < count; i++)
- rev[i] = bin[count - i - 1];
- hexify (buf, rev, count);
-#else
- hexify (buf, bin, count);
-#endif
- return buf;
-}
-
-void* C2v(CORE_ADDR addr)
-{
- return (void*) addr;
-}
-
-static
-char *image_ptid(unsigned long ptid)
-{
- static char result[100];
- VG_(sprintf) (result, "id %ld", ptid);
- return result;
-}
-#define get_thread(inf) ((struct thread_info *)(inf))
-static
-void remove_thread_if_not_in_vg_threads (struct inferior_list_entry *inf)
-{
- struct thread_info *thread = get_thread (inf);
- if (!VG_(lwpid_to_vgtid)(thread_to_gdb_id(thread))) {
- dlog(1, "removing gdb ptid %s\n",
- image_ptid(thread_to_gdb_id(thread)));
- remove_thread (thread);
- }
-}
-
-/* synchronize threads known by valgrind and threads known by gdbserver */
-static
-void valgrind_update_threads (int pid)
-{
- ThreadId tid;
- ThreadState *ts;
- unsigned long ptid;
- struct thread_info *ti;
-
- /* call remove_thread for all gdb threads not in valgrind threads */
- for_each_inferior (&all_threads, remove_thread_if_not_in_vg_threads);
-
- /* call add_thread for all valgrind threads not known in gdb all_threads */
- for (tid = 1; tid < VG_N_THREADS; tid++) {
-
-#define LOCAL_THREAD_TRACE " ti* %p vgtid %d status %s as gdb ptid %s lwpid %d\n", \
- ti, tid, VG_(name_of_ThreadStatus) (ts->status), \
- image_ptid (ptid), ts->os_state.lwpid
-
- if (VG_(is_valid_tid) (tid)) {
- ts = VG_(get_ThreadState) (tid);
- ptid = ts->os_state.lwpid;
- ti = gdb_id_to_thread (ptid);
- if (!ti) {
- /* we do not report the threads which are not yet fully
- initialized otherwise this creates duplicated threads
- in gdb: once with pid xxx lwpid 0, then after that
- with pid xxx lwpid yyy. */
- if (ts->status != VgTs_Init) {
- dlog(1, "adding_thread" LOCAL_THREAD_TRACE);
- add_thread (ptid, ts, ptid);
- }
- } else {
- dlog(2, "(known thread)" LOCAL_THREAD_TRACE);
- }
- }
-#undef LOCAL_THREAD_TRACE
- }
-}
-
-/* Return nonzero if the given thread is still alive. */
-static
-int valgrind_thread_alive (unsigned long tid)
-{
- struct thread_info *ti = gdb_id_to_thread(tid);
- ThreadState *tst;
-
- if (ti != NULL) {
- tst = (ThreadState *) inferior_target_data (ti);
- return tst->status != VgTs_Zombie;
- }
- else {
- return 0;
- }
-}
-
-/* allocate and build a register structure containing the shadow registers.
- reg_defs is the normal registers, n is their numbers */
-static
-struct reg* build_shadow_arch (struct reg *reg_defs, int n) {
- int i, r;
- static char *postfix[3] = { "", "s1", "s2" };
- struct reg *new_regs = malloc(3 * n * sizeof(reg_defs[0]));
- int reg_set_len = reg_defs[n-1].offset + reg_defs[n-1].size;
-
- for (i = 0; i < 3; i++) {
- for (r = 0; r < n; r++) {
- new_regs[i*n + r].name = malloc(strlen(reg_defs[r].name)
- + strlen (postfix[i]) + 1);
- strcpy (new_regs[i*n + r].name, reg_defs[r].name);
- strcat (new_regs[i*n + r].name, postfix[i]);
- new_regs[i*n + r].offset = i*reg_set_len + reg_defs[r].offset;
- new_regs[i*n + r].size = reg_defs[r].size;
- dlog(1,
- "%10s Nr %d offset(bit) %d offset(byte) %d size(bit) %d\n",
- new_regs[i*n + r].name, i*n + r, new_regs[i*n + r].offset,
- (new_regs[i*n + r].offset) / 8, new_regs[i*n + r].size);
- }
- }
-
- return new_regs;
-}
-
-/* Fetch one register from valgrind VEX guest state. */
-static
-void fetch_register (int regno)
-{
- int size;
- ThreadState *tst = (ThreadState *) inferior_target_data (current_inferior);
- ThreadId tid = tst->tid;
-
- if (regno >= the_low_target.num_regs) {
- dlog(0, "error fetch_register regno %d max %d\n",
- regno, the_low_target.num_regs);
- return;
- }
- size = register_size (regno);
- if (size > 0) {
- Bool mod;
- char buf [size];
- VG_(memset) (buf, 0, size); // registers not fetched will be seen as 0.
- (*the_low_target.transfer_register) (tid, regno, buf,
- valgrind_to_gdbserver, size, &mod);
- // Note: the *mod received from transfer_register is not interesting.
- // We are interested to see if the register data in the register cache is modified.
- supply_register (regno, buf, &mod);
- if (mod && VG_(debugLog_getLevel)() > 1) {
- char bufimage [2*size + 1];
- heximage (bufimage, buf, size);
- dlog(2, "fetched register %d size %d name %s value %s tid %d status %s\n",
- regno, size, the_low_target.reg_defs[regno].name, bufimage,
- tid, VG_(name_of_ThreadStatus) (tst->status));
- }
- }
-}
-
-/* Fetch all registers, or just one, from the child process. */
-static
-void usr_fetch_inferior_registers (int regno)
-{
- if (regno == -1 || regno == 0)
- for (regno = 0; regno < the_low_target.num_regs; regno++)
- fetch_register (regno);
- else
- fetch_register (regno);
-}
-
-/* Store our register values back into the inferior.
- If REGNO is -1, do this for all registers.
- Otherwise, REGNO specifies which register (so we can save time). */
-static
-void usr_store_inferior_registers (int regno)
-{
- int size;
- ThreadState *tst = (ThreadState *) inferior_target_data (current_inferior);
- ThreadId tid = tst->tid;
-
- if (regno >= 0) {
-
- if (regno >= the_low_target.num_regs) {
- dlog(0, "error store_register regno %d max %d\n",
- regno, the_low_target.num_regs);
- return;
- }
-
- size = register_size (regno);
- if (size > 0) {
- Bool mod;
- Addr old_SP, new_SP;
- char buf[size];
-
- if (regno == the_low_target.stack_pointer_regno) {
- /* When the stack pointer register is changed such that
- the stack is extended, we better inform the tool of the
- stack increase. This is needed in particular to avoid
- spurious Memcheck errors during Inferior calls. So, we
- save in old_SP the SP before the change. A change of
- stack pointer is also assumed to have initialised this
- new stack space. For the typical example of an inferior
- call, gdb writes arguments on the stack, and then
- changes the stack pointer. As the stack increase tool
- function might mark it as undefined, we have to call it
- at the good moment. */
- VG_(memset) ((void *) &old_SP, 0, size);
- (*the_low_target.transfer_register) (tid, regno, (void *) &old_SP,
- valgrind_to_gdbserver, size, &mod);
- }
-
- VG_(memset) (buf, 0, size);
- collect_register (regno, buf);
- (*the_low_target.transfer_register) (tid, regno, buf,
- gdbserver_to_valgrind, size, &mod);
- if (mod && VG_(debugLog_getLevel)() > 1) {
- char bufimage [2*size + 1];
- heximage (bufimage, buf, size);
- dlog(2,
- "stored register %d size %d name %s value %s "
- "tid %d status %s\n",
- regno, size, the_low_target.reg_defs[regno].name, bufimage,
- tid, VG_(name_of_ThreadStatus) (tst->status));
- }
- if (regno == the_low_target.stack_pointer_regno) {
- VG_(memcpy) (&new_SP, buf, size);
- if (old_SP > new_SP) {
- Word delta = (Word)new_SP - (Word)old_SP;
- dlog(1,
- " stack increase by stack pointer changed from %p to %p "
- "delta %ld\n",
- (void*) old_SP, (void *) new_SP,
- delta);
- VG_TRACK( new_mem_stack_w_ECU, new_SP, -delta, 0 );
- VG_TRACK( new_mem_stack, new_SP, -delta );
- if (VG_(tdict).track_post_mem_write) {
- VG_(tdict).track_post_mem_write( Vg_CoreClientReq, tid,
- new_SP, -delta);
- }
- }
- }
- }
- }
- else {
- for (regno = 0; regno < the_low_target.num_regs; regno++)
- usr_store_inferior_registers (regno);
- }
-}
-
-static
-void valgrind_fetch_registers (int regno)
-{
- usr_fetch_inferior_registers (regno);
-}
-
-static
-void valgrind_store_registers (int regno)
-{
- usr_store_inferior_registers (regno);
-}
-
-/* Copy LEN bytes from inferior's memory starting at MEMADDR
- to debugger memory starting at MYADDR. */
-
-static
-int valgrind_read_memory (CORE_ADDR memaddr, unsigned char *myaddr, int len)
-{
- const void *sourceaddr = C2v (memaddr);
- dlog(2, "reading memory %p size %d\n", sourceaddr, len);
- if (!VG_(am_is_valid_for_client_or_free_or_resvn) ((Addr) sourceaddr,
- len, VKI_PROT_READ)) {
- dlog(1, "error reading memory %p size %d\n", sourceaddr, len);
- return -1;
- }
- VG_(memcpy) (myaddr, sourceaddr, len);
- return 0;
-}
-
-/* Copy LEN bytes of data from debugger memory at MYADDR
- to inferior's memory at MEMADDR.
- On failure (cannot write the inferior)
- returns the value of errno. */
-
-static
-int valgrind_write_memory (CORE_ADDR memaddr, const unsigned char *myaddr, int len)
-{
- void *targetaddr = C2v (memaddr);
- dlog(2, "writing memory %p size %d\n", targetaddr, len);
- if (!VG_(am_is_valid_for_client_or_free_or_resvn) ((Addr)targetaddr,
- len, VKI_PROT_WRITE)) {
- dlog(1, "error writing memory %p size %d\n", targetaddr, len);
- return -1;
- }
- if (len > 0) {
- VG_(memcpy) (targetaddr, myaddr, len);
- if (VG_(tdict).track_post_mem_write) {
- /* Inform the tool of the post memwrite. Note that we do the
- minimum necessary to avoid complains from e.g.
- memcheck. The idea is that the debugger is as least
- intrusive as possible. So, we do not inform of the pre
- mem write (and in any case, this would cause problems with
- memcheck that does not like our CorePart in
- pre_mem_write. */
- ThreadState *tst = (ThreadState *) inferior_target_data (current_inferior);
- ThreadId tid = tst->tid;
- VG_(tdict).track_post_mem_write( Vg_CoreClientReq, tid, (Addr) targetaddr, len );
- }
- }
- return 0;
-}
-
-/* insert or remove a breakpoint */
-static
-int valgrind_point (Bool insert, char type, CORE_ADDR addr, int len)
-{
- PointKind kind;
- switch (type) {
- case '0': /* implemented by inserting checks at each instruction in sb */
- kind = software_breakpoint;
- break;
- case '1': /* hw breakpoint, same implementation as sw breakpoint */
- kind = hardware_breakpoint;
- break;
- case '2':
- kind = write_watchpoint;
- break;
- case '3':
- kind = read_watchpoint;
- break;
- case '4':
- kind = access_watchpoint;
- break;
- default:
- vg_assert (0);
- }
-
- /* Attention: gdbserver convention differs: 0 means ok; 1 means not ok */
- if (VG_(gdbserver_point) (kind, insert, addr, len))
- return 0;
- else
- return 1; /* error or unsupported */
-}
-
-static
-void valgrind_send_signal (int sig)
-{
- dlog(1, "valgrind_send_signal %d called ????\n", sig);
-}
-
-static
-char* valgrind_target_xml (void)
-{
- return (char *) the_low_target.target_xml;
-}
-
-static
-char* valgrind_shadow_target_xml (void)
-{
- return (char *) the_low_target.shadow_target_xml;
-}
-
-static
-int valgrind_insert_point (char type, CORE_ADDR addr, int len)
-{
- return valgrind_point (/* insert */ True, type, addr, len);
-}
-
-static
-int valgrind_remove_point (char type, CORE_ADDR addr, int len)
-{
- return valgrind_point (/* insert*/ False, type, addr, len);
-}
-
-static CORE_ADDR stopped_data_address = 0;
-void VG_(set_watchpoint_stop_address) (Addr addr)
-{
- stopped_data_address = addr;
-}
-
-static
-int valgrind_stopped_by_watchpoint (void)
-{
- return stopped_data_address != 0;
-}
-
-static
-CORE_ADDR valgrind_stopped_data_address (void)
-{
- return stopped_data_address;
-}
-
-/* pc at which we last stopped */
-static CORE_ADDR stop_pc;
-
-/* pc at which we resume.
- If stop_pc != resume_pc, it means
- gdb/gdbserver has changed the pc so as to have either
- a "continue by jumping at that address"
- or a "continue at that address to call some code from gdb".
-*/
-static CORE_ADDR resume_pc;
-
-static int signal_to_report;
-
-void gdbserver_signal_encountered (Int sigNo)
-{
- signal_to_report = sigNo;
-}
-
-static int signal_to_deliver;
-Bool gdbserver_deliver_signal (Int sigNo)
-{
- return sigNo == signal_to_deliver;
-}
-
-static
-char* sym (Addr addr)
-{
- static char buf[200];
- VG_(describe_IP) (addr, buf, 200);
- return buf;
-}
-
-ThreadId vgdb_interrupted_tid = 0;
-/* called to wait for the process to stop */
-static
-unsigned char valgrind_wait (char *ourstatus)
-{
- int pid;
- unsigned long wptid;
- ThreadState *tst;
- enum target_signal sig;
-
- pid = VG_(getpid) ();
- dlog(1, "enter valgrind_wait pid %d\n", pid);
-
- regcache_invalidate();
- valgrind_update_threads(pid);
-
- /* in valgrind, we consider that a wait always succeeds with STOPPED 'T'
- and with a signal TRAP (i.e. a breakpoint), unless there is
- a signal to report. */
- *ourstatus = 'T';
- if (signal_to_report == 0)
- sig = TARGET_SIGNAL_TRAP;
- else
- sig = target_signal_from_host(signal_to_report);
-
- if (vgdb_interrupted_tid != 0)
- tst = VG_(get_ThreadState) (vgdb_interrupted_tid);
- else
- tst = VG_(get_ThreadState) (VG_(running_tid));
- wptid = tst->os_state.lwpid;
- /* we can only change the current_inferior when the wptid references
- an existing thread. Otherwise, we are still in the init phase.
- (hack similar to main thread hack in valgrind_update_threads) */
- if (tst->os_state.lwpid)
- current_inferior = gdb_id_to_thread (wptid);
- stop_pc = (*the_low_target.get_pc) ();
-
- dlog(1,
- "exit valgrind_wait returns ptid %s stop_pc %s signal %d\n",
- image_ptid (wptid), sym (stop_pc), sig);
- return sig;
-}
-
-/* 0 => not single stepping.
- 1 => single stepping asked by gdb
- 2 => single stepping asked by valgrind (watchpoint) */
-static int stepping = 0;
-
-/* called when the process is to be resumed */
-static
-void valgrind_resume (struct thread_resume *resume_info)
-{
- dlog(1,
- "resume_info thread %ld leave_stopped %d step %d sig %d stepping %d\n",
- resume_info->thread,
- resume_info->leave_stopped,
- resume_info->step,
- resume_info->sig,
- stepping);
- if (valgrind_stopped_by_watchpoint()) {
- dlog(1, "clearing watchpoint stopped_data_address %p\n",
- C2v(stopped_data_address));
- VG_(set_watchpoint_stop_address) ((Addr) 0);
- }
- signal_to_deliver = resume_info->sig;
-
- stepping = resume_info->step;
- resume_pc = (*the_low_target.get_pc) ();
- if (resume_pc != stop_pc) {
- dlog(1,
- "stop_pc %p changed to be resume_pc %s\n",
- C2v(stop_pc), sym(resume_pc));
- }
- regcache_invalidate();
-}
-
-Addr valgrind_get_ignore_break_once(void)
-{
- if (valgrind_single_stepping())
- return resume_pc;
- else
- return 0;
-}
-
-
-void valgrind_set_single_stepping(Bool set)
-{
- if (set)
- stepping = 2;
- else
- stepping = 0;
-}
-
-Bool valgrind_single_stepping(void)
-{
- if (stepping)
- return True;
- else
- return False;
-}
-
-static struct target_ops valgrind_target_ops = {
- valgrind_thread_alive,
- valgrind_resume,
- valgrind_wait,
- valgrind_fetch_registers,
- valgrind_store_registers,
- valgrind_read_memory,
- valgrind_write_memory,
- valgrind_send_signal,
- valgrind_target_xml,
- valgrind_shadow_target_xml,
- valgrind_insert_point,
- valgrind_remove_point,
- valgrind_stopped_by_watchpoint,
- valgrind_stopped_data_address,
-};
-
-
-/* returns a pointer to the architecture state corresponding to
- the provided register set: 0 => normal guest registers,
- 1 => shadow1
- 2 => shadow2
-*/
-VexGuestArchState* get_arch (int set, ThreadState* tst)
-{
- switch (set) {
- case 0: return &tst->arch.vex;
- case 1: return &tst->arch.vex_shadow1;
- case 2: return &tst->arch.vex_shadow2;
- default: vg_assert(0);
- }
-}
-
-static int non_shadow_num_regs = 0;
-static struct reg *non_shadow_reg_defs = NULL;
-void initialize_shadow_low(Bool shadow_mode)
-{
- if (non_shadow_reg_defs == NULL) {
- non_shadow_reg_defs = the_low_target.reg_defs;
- non_shadow_num_regs = the_low_target.num_regs;
- }
-
- regcache_invalidate();
- if (the_low_target.reg_defs != non_shadow_reg_defs) {
- free (the_low_target.reg_defs);
- }
- if (shadow_mode) {
- the_low_target.num_regs = 3 * non_shadow_num_regs;
- the_low_target.reg_defs = build_shadow_arch (non_shadow_reg_defs, non_shadow_num_regs);
- } else {
- the_low_target.num_regs = non_shadow_num_regs;
- the_low_target.reg_defs = non_shadow_reg_defs;
- }
- set_register_cache (the_low_target.reg_defs, the_low_target.num_regs);
-}
-
-void initialize_low(void)
-{
- set_target_ops (&valgrind_target_ops);
-
-#if defined(VGA_x86)
- x86_init_architecture(&the_low_target);
-#elif defined(VGA_amd64)
- amd64_init_architecture(&the_low_target);
-#elif defined(VGA_arm)
- arm_init_architecture(&the_low_target);
-#elif defined(VGA_ppc32)
- ppc32_init_architecture(&the_low_target);
-#elif defined(VGA_ppc64)
- ppc64_init_architecture(&the_low_target);
-#elif defined(VGA_s390x)
- s390x_init_architecture(&the_low_target);
-#else
- architecture missing in valgrind-low.c
-#endif
-
-}
diff --git a/main/coregrind/m_gdbserver/valgrind_low.h b/main/coregrind/m_gdbserver/valgrind_low.h
index 6817110..0348895 100644
--- a/main/coregrind/m_gdbserver/valgrind_low.h
+++ b/main/coregrind/m_gdbserver/valgrind_low.h
@@ -54,38 +54,25 @@
or NULL not to answer. */
const char *arch_string;
- /* Description of the set of registers.
+ /* Returns the target xml description of the set of registers.
For some architectures (e.g. arm), it is mandatory
to give a description of the registers, otherwise
gdb does not understand the reply to the 'g' packet
- (which is used to get the registers). */
- const char *target_xml;
+ (which is used to get the registers).
+ If shadow_mode, returns a target xml description
+ including the two shadow registers sets.
+ This is mandatory to use the option --vgdb-shadow-registers=yes.
+ Returns NULL if there is no target xml file*/
+ char* (*target_xml) (Bool shadow_mode);
- /* Same as target_xml, but describes also the two shadow
- registers set.
- This is mandatory to use the option --vgdb-shadow-registers=yes. */
- const char *shadow_target_xml;
};
-
-/* convert from CORE_ADDR to void* */
-extern void* C2v(CORE_ADDR addr);
-
-/* builds an image of bin according to byte order of the architecture
- Useful for register and int image */
-extern char* heximage (char *buf, char *bin, int count);
-
-/* returns a pointer to the architecture state corresponding to
- the provided register set: 0 => normal guest registers,
- 1 => shadow1
- 2 => shadow2 */
-VexGuestArchState* get_arch (int set, ThreadState* tst);
-
extern void x86_init_architecture (struct valgrind_target_ops *target);
extern void amd64_init_architecture (struct valgrind_target_ops *target);
extern void arm_init_architecture (struct valgrind_target_ops *target);
extern void ppc32_init_architecture (struct valgrind_target_ops *target);
extern void ppc64_init_architecture (struct valgrind_target_ops *target);
extern void s390x_init_architecture (struct valgrind_target_ops *target);
+extern void mips32_init_architecture (struct valgrind_target_ops *target);
#endif
diff --git a/main/coregrind/m_hashtable.c b/main/coregrind/m_hashtable.c
index 0aa2ad6..96b8902 100644
--- a/main/coregrind/m_hashtable.c
+++ b/main/coregrind/m_hashtable.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -249,7 +249,7 @@
return NULL;
}
-void VG_(HT_destruct)(VgHashTable table)
+void VG_(HT_destruct)(VgHashTable table, void(*freenode_fn)(void*))
{
UInt i;
VgHashNode *node, *node_next;
@@ -257,7 +257,7 @@
for (i = 0; i < table->n_chains; i++) {
for (node = table->chains[i]; node != NULL; node = node_next) {
node_next = node->next;
- VG_(free)(node);
+ freenode_fn(node);
}
}
VG_(free)(table->chains);
diff --git a/main/coregrind/m_initimg/initimg-darwin.c b/main/coregrind/m_initimg/initimg-darwin.c
index d21347d..5fa13aa 100644
--- a/main/coregrind/m_initimg/initimg-darwin.c
+++ b/main/coregrind/m_initimg/initimg-darwin.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_initimg/initimg-linux.c b/main/coregrind/m_initimg/initimg-linux.c
index ec59696..f4db0b6 100644
--- a/main/coregrind/m_initimg/initimg-linux.c
+++ b/main/coregrind/m_initimg/initimg-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -668,8 +668,10 @@
/* When gdbserver sends the auxv to gdb, the AT_BASE has
to be ignored, as otherwise gdb adds this offset
to loaded shared libs, causing wrong address
- relocation e.g. when inserting breaks. */
- /* Android linker needs AT_BASE. Fixing Valgrind by breaking vgdb. */
+ relocation e.g. when inserting breaks.
+ However, ignoring AT_BASE makes V crash on Android 4.1.
+ So, keep the AT_BASE on android for now.
+ ??? Need to dig in depth about AT_BASE/GDB interaction */
# if !defined(VGPV_arm_linux_android)
auxv->a_type = AT_IGNORE;
# endif
@@ -693,6 +695,15 @@
"ARM has-neon from-auxv: %s\n",
has_neon ? "YES" : "NO");
VG_(machine_arm_set_has_NEON)( has_neon );
+ #define VKI_HWCAP_TLS 32768
+ Bool has_tls = (auxv->u.a_val & VKI_HWCAP_TLS) > 0;
+ VG_(debugLog)(2, "initimg",
+ "ARM has-tls from-auxv: %s\n",
+ has_tls ? "YES" : "NO");
+ /* If real hw sets properly HWCAP_TLS, we might
+ use this info to decide to really execute set_tls syscall
+ in syswrap-arm-linux.c rather than to base this on
+ conditional compilation. */
}
# endif
break;
@@ -989,10 +1000,11 @@
arch->vex.guest_EIP = iifii.initial_client_IP;
/* initialise %cs, %ds and %ss to point at the operating systems
- default code, data and stack segments */
+ default code, data and stack segments. Also %es (see #291253). */
asm volatile("movw %%cs, %0" : : "m" (arch->vex.guest_CS));
asm volatile("movw %%ds, %0" : : "m" (arch->vex.guest_DS));
asm volatile("movw %%ss, %0" : : "m" (arch->vex.guest_SS));
+ asm volatile("movw %%es, %0" : : "m" (arch->vex.guest_ES));
# elif defined(VGP_amd64_linux)
vg_assert(0 == sizeof(VexGuestAMD64State) % 16);
@@ -1063,13 +1075,39 @@
is also done by the kernel for the fpc during execve. */
LibVEX_GuestS390X_initialise(&arch->vex);
- /* Zero out the shadow area. */
- VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestS390XState));
- VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestS390XState));
+ /* Mark all registers as undefined ... */
+ VG_(memset)(&arch->vex_shadow1, 0xFF, sizeof(VexGuestS390XState));
+ VG_(memset)(&arch->vex_shadow2, 0x00, sizeof(VexGuestS390XState));
+ /* ... except SP, FPC, and IA */
+ VG_(memset)((UChar *)&arch->vex_shadow1 + VG_O_STACK_PTR, 0x00, 8);
+ VG_(memset)((UChar *)&arch->vex_shadow1 + VG_O_FPC_REG, 0x00, 4);
+ VG_(memset)((UChar *)&arch->vex_shadow1 + VG_O_INSTR_PTR, 0x00, 8);
/* Put essential stuff into the new state. */
arch->vex.guest_SP = iifii.initial_client_SP;
arch->vex.guest_IA = iifii.initial_client_IP;
+ /* See sys_execve in <linux>/arch/s390/kernel/process.c */
+ arch->vex.guest_fpc = 0;
+
+ /* Tell the tool about the registers we just wrote */
+ VG_TRACK(post_reg_write, Vg_CoreStartup, /*tid*/1, VG_O_STACK_PTR, 8);
+ VG_TRACK(post_reg_write, Vg_CoreStartup, /*tid*/1, VG_O_FPC_REG, 4);
+ VG_TRACK(post_reg_write, Vg_CoreStartup, /*tid*/1, VG_O_INSTR_PTR, 8);
+ return;
+
+# elif defined(VGP_mips32_linux)
+ vg_assert(0 == sizeof(VexGuestMIPS32State) % 16);
+ /* Zero out the initial state, and set up the simulated FPU in a
+ sane way. */
+ LibVEX_GuestMIPS32_initialise(&arch->vex);
+
+ /* Zero out the shadow areas. */
+ VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestMIPS32State));
+ VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestMIPS32State));
+
+ arch->vex.guest_r29 = iifii.initial_client_SP;
+ arch->vex.guest_PC = iifii.initial_client_IP;
+ arch->vex.guest_r31 = iifii.initial_client_SP;
# else
# error Unknown platform
diff --git a/main/coregrind/m_initimg/initimg-pathscan.c b/main/coregrind/m_initimg/initimg-pathscan.c
index 380e580..6065b83 100644
--- a/main/coregrind/m_initimg/initimg-pathscan.c
+++ b/main/coregrind/m_initimg/initimg-pathscan.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_libcassert.c b/main/coregrind/m_libcassert.c
index 1f5b95c..3d9482b 100644
--- a/main/coregrind/m_libcassert.c
+++ b/main/coregrind/m_libcassert.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -152,6 +152,31 @@
(srP)->misc.S390X.r_fp = fp; \
(srP)->misc.S390X.r_lr = lr; \
}
+#elif defined(VGP_mips32_linux)
+# define GET_STARTREGS(srP) \
+ { UInt pc, sp, fp, ra, gp; \
+ asm("move $8, $31;" /* t0 = ra */ \
+ "bal m_libcassert_get_ip;" /* ra = pc */ \
+ "m_libcassert_get_ip:\n" \
+ "move %0, $31;" \
+ "move $31, $8;" /* restore lr */ \
+ "move %1, $29;" \
+ "move %2, $30;" \
+ "move %3, $31;" \
+ "move %4, $28;" \
+ : "=r" (pc), \
+ "=r" (sp), \
+ "=r" (fp), \
+ "=r" (ra), \
+ "=r" (gp) \
+ : /* reads none */ \
+ : "$8" /* trashed */ ); \
+ (srP)->r_pc = (ULong)pc - 8; \
+ (srP)->r_sp = (ULong)sp; \
+ (srP)->misc.MIPS32.r30 = (ULong)fp; \
+ (srP)->misc.MIPS32.r31 = (ULong)ra; \
+ (srP)->misc.MIPS32.r28 = (ULong)gp; \
+ }
#else
# error Unknown platform
#endif
diff --git a/main/coregrind/m_libcbase.c b/main/coregrind/m_libcbase.c
index c7a1892..866bb78 100644
--- a/main/coregrind/m_libcbase.c
+++ b/main/coregrind/m_libcbase.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -303,13 +303,12 @@
Int VG_(strcmp) ( const Char* s1, const Char* s2 )
{
while (True) {
- if (*s1 == 0 && *s2 == 0) return 0;
- if (*s1 == 0) return -1;
- if (*s2 == 0) return 1;
-
if (*(UChar*)s1 < *(UChar*)s2) return -1;
if (*(UChar*)s1 > *(UChar*)s2) return 1;
+ /* *s1 == *s2 */
+ if (*s1 == 0) return 0;
+
s1++; s2++;
}
}
@@ -319,12 +318,11 @@
while (True) {
UChar c1 = (UChar)VG_(tolower)(*s1);
UChar c2 = (UChar)VG_(tolower)(*s2);
- if (c1 == 0 && c2 == 0) return 0;
- if (c1 == 0) return -1;
- if (c2 == 0) return 1;
-
if (c1 < c2) return -1;
if (c1 > c2) return 1;
+
+ /* c1 == c2 */
+ if (c1 == 0) return 0;
s1++; s2++;
}
@@ -335,12 +333,11 @@
SizeT n = 0;
while (True) {
if (n >= nmax) return 0;
- if (*s1 == 0 && *s2 == 0) return 0;
- if (*s1 == 0) return -1;
- if (*s2 == 0) return 1;
-
if (*(UChar*)s1 < *(UChar*)s2) return -1;
if (*(UChar*)s1 > *(UChar*)s2) return 1;
+
+ /* *s1 == *s2 */
+ if (*s1 == 0) return 0;
s1++; s2++; n++;
}
@@ -355,13 +352,12 @@
if (n >= nmax) return 0;
c1 = (UChar)VG_(tolower)(*s1);
c2 = (UChar)VG_(tolower)(*s2);
- if (c1 == 0 && c2 == 0) return 0;
- if (c1 == 0) return -1;
- if (c2 == 0) return 1;
-
if (c1 < c2) return -1;
if (c1 > c2) return 1;
+ /* c1 == c2 */
+ if (c1 == 0) return 0;
+
s1++; s2++; n++;
}
}
diff --git a/main/coregrind/m_libcfile.c b/main/coregrind/m_libcfile.c
index 111834d..51e8de8 100644
--- a/main/coregrind/m_libcfile.c
+++ b/main/coregrind/m_libcfile.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -194,7 +194,17 @@
Int VG_(pipe) ( Int fd[2] )
{
-# if defined(VGO_linux)
+# if defined(VGP_mips32_linux)
+ /* __NR_pipe has a strange return convention on mips32-linux. */
+ SysRes res = VG_(do_syscall0)(__NR_pipe);
+ if (!sr_isError(res)) {
+ fd[0] = (Int)sr_Res(res);
+ fd[1] = (Int)sr_ResEx(res);
+ return 0;
+ } else {
+ return -1;
+ }
+# elif defined(VGO_linux)
SysRes res = VG_(do_syscall1)(__NR_pipe, (UWord)fd);
return sr_isError(res) ? -1 : 0;
# elif defined(VGO_darwin)
@@ -232,17 +242,9 @@
# error "Unknown plat"
# endif
/* if you change the error-reporting conventions of this, also
- change VG_(pread) and all other usage points. */
+ change all usage points. */
}
-extern Int VG_(ftruncate) ( Int fd, OffT length ) {
-#if defined (VGO_linux)
- SysRes res = VG_(do_syscall2)(__NR_ftruncate, fd, length);
- return sr_isError(res) ? (-1) : sr_Res(res);
-#else
- return -1; /*UNIMPLEMENTED*/
-#endif
-}
/* stat/fstat support. It's uggerly. We have impedance-match into a
'struct vg_stat' in order to have a single structure that callers
@@ -454,10 +456,16 @@
return True;
}
-Int VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout)
+Int VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout)
{
SysRes res;
+# if defined(VGO_linux)
res = VG_(do_syscall3)(__NR_poll, (UWord)fds, nfds, timeout);
+# elif defined(VGO_darwin)
+ res = VG_(do_syscall3)(__NR_poll_nocancel, (UWord)fds, nfds, timeout);
+# else
+# error "Unknown OS"
+# endif
return sr_isError(res) ? -1 : sr_Res(res);
}
@@ -583,24 +591,47 @@
return 0;
}
-/* DDD: Note this moves (or at least, is believed to move) the file
- pointer on Linux but doesn't on Darwin. This inconsistency should
- be fixed. (In other words, why isn't the Linux version implemented
- in terms of pread()?) */
SysRes VG_(pread) ( Int fd, void* buf, Int count, OffT offset )
{
SysRes res;
-# if defined(VGO_linux)
- OffT off = VG_(lseek)( fd, offset, VKI_SEEK_SET);
- if (off < 0)
- return VG_(mk_SysRes_Error)( VKI_EINVAL );
- res = VG_(do_syscall3)(__NR_read, fd, (UWord)buf, count );
+ // on 32 bits platforms, we receive a 32 bits OffT but
+ // we must extend it to pass a long long 64 bits.
+# if defined(VGP_x86_linux)
+ vg_assert(sizeof(OffT) == 4);
+ res = VG_(do_syscall5)(__NR_pread64, fd, (UWord)buf, count,
+ offset, 0); // Little endian long long
+ return res;
+# elif defined(VGP_arm_linux)
+ vg_assert(sizeof(OffT) == 4);
+ res = VG_(do_syscall5)(__NR_pread64, fd, (UWord)buf, count,
+ 0, offset); // Big endian long long
+ return res;
+# elif defined(VGP_ppc32_linux)
+ vg_assert(sizeof(OffT) == 4);
+ res = VG_(do_syscall6)(__NR_pread64, fd, (UWord)buf, count,
+ 0, // Padding needed on PPC32
+ 0, offset); // Big endian long long
+ return res;
+# elif defined(VGP_mips32_linux) && VKI_LITTLE_ENDIAN
+ vg_assert(sizeof(OffT) == 4);
+ res = VG_(do_syscall6)(__NR_pread64, fd, (UWord)buf, count,
+ 0, offset, 0);
+ return res;
+# elif defined(VGP_mips32_linux) && VKI_BIG_ENDIAN
+ vg_assert(sizeof(OffT) == 4);
+ res = VG_(do_syscall6)(__NR_pread64, fd, (UWord)buf, count,
+ 0, 0, offset);
+ return res;
+# elif defined(VGP_amd64_linux) \
+ || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
+ res = VG_(do_syscall4)(__NR_pread64, fd, (UWord)buf, count, offset);
return res;
# elif defined(VGP_amd64_darwin)
+ vg_assert(sizeof(OffT) == 8);
res = VG_(do_syscall4)(__NR_pread_nocancel, fd, (UWord)buf, count, offset);
return res;
# elif defined(VGP_x86_darwin)
- /* ppc32-darwin is the same, but with the args inverted */
+ vg_assert(sizeof(OffT) == 8);
res = VG_(do_syscall5)(__NR_pread_nocancel, fd, (UWord)buf, count,
offset & 0xffffffff, offset >> 32);
return res;
@@ -832,7 +863,8 @@
res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_SOCKET, (UWord)&args);
return sr_isError(res) ? -1 : sr_Res(res);
-# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux)
+# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
+ || defined(VGP_mips32_linux)
SysRes res;
res = VG_(do_syscall3)(__NR_socket, domain, type, protocol );
return sr_isError(res) ? -1 : sr_Res(res);
@@ -870,7 +902,8 @@
res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_CONNECT, (UWord)&args);
return sr_isError(res) ? -1 : sr_Res(res);
-# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux)
+# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
+ || defined(VGP_mips32_linux)
SysRes res;
res = VG_(do_syscall3)(__NR_connect, sockfd, (UWord)serv_addr, addrlen);
return sr_isError(res) ? -1 : sr_Res(res);
@@ -908,7 +941,8 @@
res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_SEND, (UWord)&args);
return sr_isError(res) ? -1 : sr_Res(res);
-# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux)
+# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
+ || defined(VGP_mips32_linux)
SysRes res;
res = VG_(do_syscall6)(__NR_sendto, sd, (UWord)msg,
count, VKI_MSG_NOSIGNAL, 0,0);
@@ -927,7 +961,8 @@
Int VG_(getsockname) ( Int sd, struct vki_sockaddr *name, Int *namelen)
{
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
+ || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \
+ || defined(VGP_mips32_linux)
SysRes res;
UWord args[3];
args[0] = sd;
@@ -956,7 +991,8 @@
Int VG_(getpeername) ( Int sd, struct vki_sockaddr *name, Int *namelen)
{
# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
+ || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \
+ || defined(VGP_mips32_linux)
SysRes res;
UWord args[3];
args[0] = sd;
@@ -997,7 +1033,8 @@
res = VG_(do_syscall2)(__NR_socketcall, VKI_SYS_GETSOCKOPT, (UWord)&args);
return sr_isError(res) ? -1 : sr_Res(res);
-# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux)
+# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
+ || defined(VGP_mips32_linux)
SysRes res;
res = VG_(do_syscall5)( __NR_getsockopt,
(UWord)sd, (UWord)level, (UWord)optname,
diff --git a/main/coregrind/m_libcprint.c b/main/coregrind/m_libcprint.c
index b9b24f6..bfa3488 100644
--- a/main/coregrind/m_libcprint.c
+++ b/main/coregrind/m_libcprint.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -396,11 +396,16 @@
// Print one '>' in front of the messages for each level of
// self-hosting being performed.
+ // Do not print such '>' if sim hint "no-inner-prefix" given
+ // (useful to run regression tests in an outer/inner setup
+ // and avoid the diff failing due to these unexpected '>').
depth = RUNNING_ON_VALGRIND;
- if (depth > 10)
- depth = 10; // ?!?!
- for (i = 0; i < depth; i++) {
- b->buf[b->buf_used++] = '>';
+ if (depth > 0 && !VG_(strstr)(VG_(clo_sim_hints), "no-inner-prefix")) {
+ if (depth > 10)
+ depth = 10; // ?!?!
+ for (i = 0; i < depth; i++) {
+ b->buf[b->buf_used++] = '>';
+ }
}
if (Vg_FailMsg == b->kind) {
diff --git a/main/coregrind/m_libcproc.c b/main/coregrind/m_libcproc.c
index 891ee4e..136426b 100644
--- a/main/coregrind/m_libcproc.c
+++ b/main/coregrind/m_libcproc.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -29,16 +29,14 @@
*/
#include "pub_core_basics.h"
+#include "pub_core_machine.h" // For VG_(machine_get_VexArchInfo)
#include "pub_core_vki.h"
#include "pub_core_vkiscnums.h"
#include "pub_core_libcbase.h"
#include "pub_core_libcassert.h"
-#include "pub_core_libcfile.h"
#include "pub_core_libcprint.h"
#include "pub_core_libcproc.h"
#include "pub_core_libcsignal.h"
-#include "pub_core_tooliface.h"
-#include "pub_core_options.h"
#include "pub_core_seqmatch.h"
#include "pub_core_mallocfree.h"
#include "pub_core_syscall.h"
@@ -243,12 +241,18 @@
// - LD_PRELOAD is on Linux, not on Darwin, not sure about AIX
// - DYLD_INSERT_LIBRARIES and DYLD_SHARED_REGION are Darwin-only
for (i = 0; envp[i] != NULL; i++) {
- if (VG_(strncmp)(envp[i], "LD_PRELOAD=", 11) == 0)
- ld_preload_str = VG_(arena_strdup)(VG_AR_CORE, "libcproc.erves.1", &envp[i][11]);
- if (VG_(strncmp)(envp[i], "LD_LIBRARY_PATH=", 16) == 0)
- ld_library_path_str = VG_(arena_strdup)(VG_AR_CORE, "libcproc.erves.2", &envp[i][16]);
- if (VG_(strncmp)(envp[i], "DYLD_INSERT_LIBRARIES=", 22) == 0)
- dyld_insert_libraries_str = VG_(arena_strdup)(VG_AR_CORE, "libcproc.erves.3", &envp[i][22]);
+ if (VG_(strncmp)(envp[i], "LD_PRELOAD=", 11) == 0) {
+ envp[i] = VG_(arena_strdup)(VG_AR_CORE, "libcproc.erves.1", envp[i]);
+ ld_preload_str = &envp[i][11];
+ }
+ if (VG_(strncmp)(envp[i], "LD_LIBRARY_PATH=", 16) == 0) {
+ envp[i] = VG_(arena_strdup)(VG_AR_CORE, "libcproc.erves.2", envp[i]);
+ ld_library_path_str = &envp[i][16];
+ }
+ if (VG_(strncmp)(envp[i], "DYLD_INSERT_LIBRARIES=", 22) == 0) {
+ envp[i] = VG_(arena_strdup)(VG_AR_CORE, "libcproc.erves.3", envp[i]);
+ dyld_insert_libraries_str = &envp[i][22];
+ }
}
buf = VG_(arena_malloc)(VG_AR_CORE, "libcproc.erves.4",
@@ -545,7 +549,8 @@
# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \
|| defined(VGP_arm_linux) \
- || defined(VGO_darwin) || defined(VGP_s390x_linux)
+ || defined(VGO_darwin) || defined(VGP_s390x_linux) \
+ || defined(VGP_mips32_linux)
SysRes sres;
sres = VG_(do_syscall2)(__NR_getgroups, size, (Addr)list);
if (sr_isError(sres))
@@ -703,45 +708,74 @@
(*atforks[i].parent)(tid);
}
-// Defined in m_main.c
-void print_preamble(Bool logging_to_fd, const char* toolname);
-
-Char* VG_(clo_log_fname_unexpanded) = NULL;
-Char* VG_(clo_xml_fname_unexpanded) = NULL;
-
-// If --log-file=ABC%pXYZ is specified, we'd like to have separate log files
-// for each forked child.
-// If %p is present in the --log-file option, this function creates
-// a new log file and redirects the child's output to it.
-static void open_new_logfile_for_forked_child(void)
-{
- Int tmp_fd = -1;
-
- if (VG_(log_output_sink).is_socket == False && VG_(clo_log_fname_unexpanded) != NULL) {
- tmp_fd = reopen_output_fd(False);
- VG_(log_output_sink).fd = VG_(safe_fd)(tmp_fd);
- }
-
- if (VG_(xml_output_sink).is_socket == False && VG_(clo_xml_fname_unexpanded) != NULL) {
- tmp_fd = reopen_output_fd(True);
- VG_(xml_output_sink).fd = VG_(safe_fd)(tmp_fd);
- }
-
- print_preamble(False, NULL);
-}
-
void VG_(do_atfork_child)(ThreadId tid)
{
Int i;
- open_new_logfile_for_forked_child();
-
for (i = 0; i < n_atfork; i++)
if (atforks[i].child != NULL)
(*atforks[i].child)(tid);
}
+/* ---------------------------------------------------------------------
+ icache invalidation
+ ------------------------------------------------------------------ */
+
+void VG_(invalidate_icache) ( void *ptr, SizeT nbytes )
+{
+# if defined(VGA_ppc32) || defined(VGA_ppc64)
+ Addr startaddr = (Addr) ptr;
+ Addr endaddr = startaddr + nbytes;
+ Addr cls;
+ Addr addr;
+ VexArchInfo vai;
+
+ if (nbytes == 0) return;
+ vg_assert(nbytes > 0);
+
+ VG_(machine_get_VexArchInfo)( NULL, &vai );
+ cls = vai.ppc_cache_line_szB;
+
+ /* Stay sane .. */
+ vg_assert(cls == 32 || cls == 64 || cls == 128);
+
+ startaddr &= ~(cls - 1);
+ for (addr = startaddr; addr < endaddr; addr += cls) {
+ __asm__ __volatile__("dcbst 0,%0" : : "r" (addr));
+ }
+ __asm__ __volatile__("sync");
+ for (addr = startaddr; addr < endaddr; addr += cls) {
+ __asm__ __volatile__("icbi 0,%0" : : "r" (addr));
+ }
+ __asm__ __volatile__("sync; isync");
+
+# elif defined(VGA_x86)
+ /* no need to do anything, hardware provides coherence */
+
+# elif defined(VGA_amd64)
+ /* no need to do anything, hardware provides coherence */
+
+# elif defined(VGA_s390x)
+ /* no need to do anything, hardware provides coherence */
+
+# elif defined(VGP_arm_linux)
+ /* ARM cache flushes are privileged, so we must defer to the kernel. */
+ Addr startaddr = (Addr) ptr;
+ Addr endaddr = startaddr + nbytes;
+ VG_(do_syscall2)(__NR_ARM_cacheflush, startaddr, endaddr);
+
+# elif defined(VGA_mips32)
+ SysRes sres = VG_(do_syscall3)(__NR_cacheflush, (UWord) ptr,
+ (UWord) nbytes, (UWord) 3);
+ vg_assert( sres._isError == 0 );
+
+# else
+# error "Unknown ARCH"
+# endif
+}
+
+
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_libcsetjmp.c b/main/coregrind/m_libcsetjmp.c
index 6b9160c..2b016a9 100644
--- a/main/coregrind/m_libcsetjmp.c
+++ b/main/coregrind/m_libcsetjmp.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2011 Mozilla Inc
+ Copyright (C) 2010-2012 Mozilla Inc
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/coregrind/m_libcsignal.c b/main/coregrind/m_libcsignal.c
index 6f65e4d..4015634 100644
--- a/main/coregrind/m_libcsignal.c
+++ b/main/coregrind/m_libcsignal.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_mach/mach_basics.c b/main/coregrind/m_mach/mach_basics.c
index 7f9336f..7c73c77 100644
--- a/main/coregrind/m_mach/mach_basics.c
+++ b/main/coregrind/m_mach/mach_basics.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Apple Inc.
+ Copyright (C) 2005-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_mach/mach_traps-amd64-darwin.S b/main/coregrind/m_mach/mach_traps-amd64-darwin.S
index d90cc61..e305ccf 100644
--- a/main/coregrind/m_mach/mach_traps-amd64-darwin.S
+++ b/main/coregrind/m_mach/mach_traps-amd64-darwin.S
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2011 Apple Inc.
+ Copyright (C) 2007-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_mach/mach_traps-x86-darwin.S b/main/coregrind/m_mach/mach_traps-x86-darwin.S
index 32f106f..d77094a 100644
--- a/main/coregrind/m_mach/mach_traps-x86-darwin.S
+++ b/main/coregrind/m_mach/mach_traps-x86-darwin.S
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2011 Apple Inc.
+ Copyright (C) 2006-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_machine.c b/main/coregrind/m_machine.c
index 9126096..82c5751 100644
--- a/main/coregrind/m_machine.c
+++ b/main/coregrind/m_machine.c
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -103,6 +103,15 @@
= VG_(threads)[tid].arch.vex.guest_r11;
regs->misc.S390X.r_lr
= VG_(threads)[tid].arch.vex.guest_r14;
+# elif defined(VGA_mips32)
+ regs->r_pc = VG_(threads)[tid].arch.vex.guest_PC;
+ regs->r_sp = VG_(threads)[tid].arch.vex.guest_r29;
+ regs->misc.MIPS32.r30
+ = VG_(threads)[tid].arch.vex.guest_r30;
+ regs->misc.MIPS32.r31
+ = VG_(threads)[tid].arch.vex.guest_r31;
+ regs->misc.MIPS32.r28
+ = VG_(threads)[tid].arch.vex.guest_r28;
# else
# error "Unknown arch"
# endif
@@ -132,6 +141,9 @@
# elif defined(VGP_s390x_linux)
VG_(threads)[tid].arch.vex_shadow1.guest_r2 = s1res;
VG_(threads)[tid].arch.vex_shadow2.guest_r2 = s2res;
+# elif defined(VGP_mips32_linux)
+ VG_(threads)[tid].arch.vex_shadow1.guest_r2 = s1res;
+ VG_(threads)[tid].arch.vex_shadow2.guest_r2 = s2res;
# else
# error "Unknown plat"
# endif
@@ -186,115 +198,148 @@
}
-static void apply_to_GPs_of_tid(VexGuestArchState* vex, void (*f)(Addr))
+static void apply_to_GPs_of_tid(ThreadId tid, void (*f)(ThreadId, HChar*, Addr))
{
+ VexGuestArchState* vex = &(VG_(get_ThreadState)(tid)->arch.vex);
#if defined(VGA_x86)
- (*f)(vex->guest_EAX);
- (*f)(vex->guest_ECX);
- (*f)(vex->guest_EDX);
- (*f)(vex->guest_EBX);
- (*f)(vex->guest_ESI);
- (*f)(vex->guest_EDI);
- (*f)(vex->guest_ESP);
- (*f)(vex->guest_EBP);
+ (*f)(tid, "EAX", vex->guest_EAX);
+ (*f)(tid, "ECX", vex->guest_ECX);
+ (*f)(tid, "EDX", vex->guest_EDX);
+ (*f)(tid, "EBX", vex->guest_EBX);
+ (*f)(tid, "ESI", vex->guest_ESI);
+ (*f)(tid, "EDI", vex->guest_EDI);
+ (*f)(tid, "ESP", vex->guest_ESP);
+ (*f)(tid, "EBP", vex->guest_EBP);
#elif defined(VGA_amd64)
- (*f)(vex->guest_RAX);
- (*f)(vex->guest_RCX);
- (*f)(vex->guest_RDX);
- (*f)(vex->guest_RBX);
- (*f)(vex->guest_RSI);
- (*f)(vex->guest_RDI);
- (*f)(vex->guest_RSP);
- (*f)(vex->guest_RBP);
- (*f)(vex->guest_R8);
- (*f)(vex->guest_R9);
- (*f)(vex->guest_R10);
- (*f)(vex->guest_R11);
- (*f)(vex->guest_R12);
- (*f)(vex->guest_R13);
- (*f)(vex->guest_R14);
- (*f)(vex->guest_R15);
+ (*f)(tid, "RAX", vex->guest_RAX);
+ (*f)(tid, "RCX", vex->guest_RCX);
+ (*f)(tid, "RDX", vex->guest_RDX);
+ (*f)(tid, "RBX", vex->guest_RBX);
+ (*f)(tid, "RSI", vex->guest_RSI);
+ (*f)(tid, "RDI", vex->guest_RDI);
+ (*f)(tid, "RSP", vex->guest_RSP);
+ (*f)(tid, "RBP", vex->guest_RBP);
+ (*f)(tid, "R8" , vex->guest_R8 );
+ (*f)(tid, "R9" , vex->guest_R9 );
+ (*f)(tid, "R10", vex->guest_R10);
+ (*f)(tid, "R11", vex->guest_R11);
+ (*f)(tid, "R12", vex->guest_R12);
+ (*f)(tid, "R13", vex->guest_R13);
+ (*f)(tid, "R14", vex->guest_R14);
+ (*f)(tid, "R15", vex->guest_R15);
#elif defined(VGA_ppc32) || defined(VGA_ppc64)
- (*f)(vex->guest_GPR0);
- (*f)(vex->guest_GPR1);
- (*f)(vex->guest_GPR2);
- (*f)(vex->guest_GPR3);
- (*f)(vex->guest_GPR4);
- (*f)(vex->guest_GPR5);
- (*f)(vex->guest_GPR6);
- (*f)(vex->guest_GPR7);
- (*f)(vex->guest_GPR8);
- (*f)(vex->guest_GPR9);
- (*f)(vex->guest_GPR10);
- (*f)(vex->guest_GPR11);
- (*f)(vex->guest_GPR12);
- (*f)(vex->guest_GPR13);
- (*f)(vex->guest_GPR14);
- (*f)(vex->guest_GPR15);
- (*f)(vex->guest_GPR16);
- (*f)(vex->guest_GPR17);
- (*f)(vex->guest_GPR18);
- (*f)(vex->guest_GPR19);
- (*f)(vex->guest_GPR20);
- (*f)(vex->guest_GPR21);
- (*f)(vex->guest_GPR22);
- (*f)(vex->guest_GPR23);
- (*f)(vex->guest_GPR24);
- (*f)(vex->guest_GPR25);
- (*f)(vex->guest_GPR26);
- (*f)(vex->guest_GPR27);
- (*f)(vex->guest_GPR28);
- (*f)(vex->guest_GPR29);
- (*f)(vex->guest_GPR30);
- (*f)(vex->guest_GPR31);
- (*f)(vex->guest_CTR);
- (*f)(vex->guest_LR);
+ (*f)(tid, "GPR0" , vex->guest_GPR0 );
+ (*f)(tid, "GPR1" , vex->guest_GPR1 );
+ (*f)(tid, "GPR2" , vex->guest_GPR2 );
+ (*f)(tid, "GPR3" , vex->guest_GPR3 );
+ (*f)(tid, "GPR4" , vex->guest_GPR4 );
+ (*f)(tid, "GPR5" , vex->guest_GPR5 );
+ (*f)(tid, "GPR6" , vex->guest_GPR6 );
+ (*f)(tid, "GPR7" , vex->guest_GPR7 );
+ (*f)(tid, "GPR8" , vex->guest_GPR8 );
+ (*f)(tid, "GPR9" , vex->guest_GPR9 );
+ (*f)(tid, "GPR10", vex->guest_GPR10);
+ (*f)(tid, "GPR11", vex->guest_GPR11);
+ (*f)(tid, "GPR12", vex->guest_GPR12);
+ (*f)(tid, "GPR13", vex->guest_GPR13);
+ (*f)(tid, "GPR14", vex->guest_GPR14);
+ (*f)(tid, "GPR15", vex->guest_GPR15);
+ (*f)(tid, "GPR16", vex->guest_GPR16);
+ (*f)(tid, "GPR17", vex->guest_GPR17);
+ (*f)(tid, "GPR18", vex->guest_GPR18);
+ (*f)(tid, "GPR19", vex->guest_GPR19);
+ (*f)(tid, "GPR20", vex->guest_GPR20);
+ (*f)(tid, "GPR21", vex->guest_GPR21);
+ (*f)(tid, "GPR22", vex->guest_GPR22);
+ (*f)(tid, "GPR23", vex->guest_GPR23);
+ (*f)(tid, "GPR24", vex->guest_GPR24);
+ (*f)(tid, "GPR25", vex->guest_GPR25);
+ (*f)(tid, "GPR26", vex->guest_GPR26);
+ (*f)(tid, "GPR27", vex->guest_GPR27);
+ (*f)(tid, "GPR28", vex->guest_GPR28);
+ (*f)(tid, "GPR29", vex->guest_GPR29);
+ (*f)(tid, "GPR30", vex->guest_GPR30);
+ (*f)(tid, "GPR31", vex->guest_GPR31);
+ (*f)(tid, "CTR" , vex->guest_CTR );
+ (*f)(tid, "LR" , vex->guest_LR );
#elif defined(VGA_arm)
- (*f)(vex->guest_R0);
- (*f)(vex->guest_R1);
- (*f)(vex->guest_R2);
- (*f)(vex->guest_R3);
- (*f)(vex->guest_R4);
- (*f)(vex->guest_R5);
- (*f)(vex->guest_R6);
- (*f)(vex->guest_R8);
- (*f)(vex->guest_R9);
- (*f)(vex->guest_R10);
- (*f)(vex->guest_R11);
- (*f)(vex->guest_R12);
- (*f)(vex->guest_R13);
- (*f)(vex->guest_R14);
+ (*f)(tid, "R0" , vex->guest_R0 );
+ (*f)(tid, "R1" , vex->guest_R1 );
+ (*f)(tid, "R2" , vex->guest_R2 );
+ (*f)(tid, "R3" , vex->guest_R3 );
+ (*f)(tid, "R4" , vex->guest_R4 );
+ (*f)(tid, "R5" , vex->guest_R5 );
+ (*f)(tid, "R6" , vex->guest_R6 );
+ (*f)(tid, "R8" , vex->guest_R8 );
+ (*f)(tid, "R9" , vex->guest_R9 );
+ (*f)(tid, "R10", vex->guest_R10);
+ (*f)(tid, "R11", vex->guest_R11);
+ (*f)(tid, "R12", vex->guest_R12);
+ (*f)(tid, "R13", vex->guest_R13);
+ (*f)(tid, "R14", vex->guest_R14);
#elif defined(VGA_s390x)
- (*f)(vex->guest_r0);
- (*f)(vex->guest_r1);
- (*f)(vex->guest_r2);
- (*f)(vex->guest_r3);
- (*f)(vex->guest_r4);
- (*f)(vex->guest_r5);
- (*f)(vex->guest_r6);
- (*f)(vex->guest_r7);
- (*f)(vex->guest_r8);
- (*f)(vex->guest_r9);
- (*f)(vex->guest_r10);
- (*f)(vex->guest_r11);
- (*f)(vex->guest_r12);
- (*f)(vex->guest_r13);
- (*f)(vex->guest_r14);
- (*f)(vex->guest_r15);
+ (*f)(tid, "r0" , vex->guest_r0 );
+ (*f)(tid, "r1" , vex->guest_r1 );
+ (*f)(tid, "r2" , vex->guest_r2 );
+ (*f)(tid, "r3" , vex->guest_r3 );
+ (*f)(tid, "r4" , vex->guest_r4 );
+ (*f)(tid, "r5" , vex->guest_r5 );
+ (*f)(tid, "r6" , vex->guest_r6 );
+ (*f)(tid, "r7" , vex->guest_r7 );
+ (*f)(tid, "r8" , vex->guest_r8 );
+ (*f)(tid, "r9" , vex->guest_r9 );
+ (*f)(tid, "r10", vex->guest_r10);
+ (*f)(tid, "r11", vex->guest_r11);
+ (*f)(tid, "r12", vex->guest_r12);
+ (*f)(tid, "r13", vex->guest_r13);
+ (*f)(tid, "r14", vex->guest_r14);
+ (*f)(tid, "r15", vex->guest_r15);
+#elif defined(VGA_mips32)
+ (*f)(tid, "r0" , vex->guest_r0 );
+ (*f)(tid, "r1" , vex->guest_r1 );
+ (*f)(tid, "r2" , vex->guest_r2 );
+ (*f)(tid, "r3" , vex->guest_r3 );
+ (*f)(tid, "r4" , vex->guest_r4 );
+ (*f)(tid, "r5" , vex->guest_r5 );
+ (*f)(tid, "r6" , vex->guest_r6 );
+ (*f)(tid, "r7" , vex->guest_r7 );
+ (*f)(tid, "r8" , vex->guest_r8 );
+ (*f)(tid, "r9" , vex->guest_r9 );
+ (*f)(tid, "r10", vex->guest_r10);
+ (*f)(tid, "r11", vex->guest_r11);
+ (*f)(tid, "r12", vex->guest_r12);
+ (*f)(tid, "r13", vex->guest_r13);
+ (*f)(tid, "r14", vex->guest_r14);
+ (*f)(tid, "r15", vex->guest_r15);
+ (*f)(tid, "r16", vex->guest_r16);
+ (*f)(tid, "r17", vex->guest_r17);
+ (*f)(tid, "r18", vex->guest_r18);
+ (*f)(tid, "r19", vex->guest_r19);
+ (*f)(tid, "r20", vex->guest_r20);
+ (*f)(tid, "r21", vex->guest_r21);
+ (*f)(tid, "r22", vex->guest_r22);
+ (*f)(tid, "r23", vex->guest_r23);
+ (*f)(tid, "r24", vex->guest_r24);
+ (*f)(tid, "r25", vex->guest_r25);
+ (*f)(tid, "r26", vex->guest_r26);
+ (*f)(tid, "r27", vex->guest_r27);
+ (*f)(tid, "r28", vex->guest_r28);
+ (*f)(tid, "r29", vex->guest_r29);
+ (*f)(tid, "r30", vex->guest_r30);
+ (*f)(tid, "r31", vex->guest_r31);
#else
# error Unknown arch
#endif
}
-void VG_(apply_to_GP_regs)(void (*f)(UWord))
+void VG_(apply_to_GP_regs)(void (*f)(ThreadId, HChar*, UWord))
{
ThreadId tid;
for (tid = 1; tid < VG_N_THREADS; tid++) {
if (VG_(is_valid_tid)(tid)) {
- ThreadState* tst = VG_(get_ThreadState)(tid);
- apply_to_GPs_of_tid(&(tst->arch.vex), f);
+ apply_to_GPs_of_tid(tid, f);
}
}
}
@@ -356,35 +401,7 @@
(2) from the AT_SYSINFO entries the kernel gave us (ppc32 cache
line size). It's a bit nasty in the sense that there's no obvious
way to stop uses of some of this info before it's ready to go.
-
- Current dependencies are:
-
- x86: initially: call VG_(machine_get_hwcaps)
-
- then safe to use VG_(machine_get_VexArchInfo)
- and VG_(machine_x86_have_mxcsr)
- -------------
- amd64: initially: call VG_(machine_get_hwcaps)
-
- then safe to use VG_(machine_get_VexArchInfo)
- -------------
- ppc32: initially: call VG_(machine_get_hwcaps)
- call VG_(machine_ppc32_set_clszB)
-
- then safe to use VG_(machine_get_VexArchInfo)
- and VG_(machine_ppc32_has_FP)
- and VG_(machine_ppc32_has_VMX)
- -------------
- ppc64: initially: call VG_(machine_get_hwcaps)
- call VG_(machine_ppc64_set_clszB)
-
- then safe to use VG_(machine_get_VexArchInfo)
- and VG_(machine_ppc64_has_VMX)
-
- -------------
- s390x: initially: call VG_(machine_get_hwcaps)
-
- then safe to use VG_(machine_get_VexArchInfo)
+ See pub_core_machine.h for more information about that.
VG_(machine_get_hwcaps) may use signals (although it attempts to
leave signal state unchanged) and therefore should only be
@@ -395,7 +412,7 @@
static Bool hwcaps_done = False;
/* --- all archs --- */
-static VexArch va;
+static VexArch va = VexArch_INVALID;
static VexArchInfo vai;
#if defined(VGA_x86)
@@ -495,7 +512,8 @@
processor 0: version = FF, identification = 0117C9, machine = 2064
- and return the machine model or VEX_S390X_MODEL_INVALID on error. */
+ and return the machine model. If the machine model could not be determined
+ or it is an unknown model, return VEX_S390X_MODEL_UNKNOWN. */
static UInt VG_(get_machine_model)(void)
{
@@ -522,7 +540,7 @@
/* Slurp contents of /proc/cpuinfo into FILE_BUF */
fd = VG_(open)( "/proc/cpuinfo", 0, VKI_S_IRUSR );
- if ( sr_isError(fd) ) return VEX_S390X_MODEL_INVALID;
+ if ( sr_isError(fd) ) return VEX_S390X_MODEL_UNKNOWN;
fh = sr_Res(fd);
@@ -555,7 +573,7 @@
VG_(close)(fh);
/* Parse file */
- model = VEX_S390X_MODEL_INVALID;
+ model = VEX_S390X_MODEL_UNKNOWN;
for (p = file_buf; *p; ++p) {
/* Beginning of line */
if (VG_(strncmp)( p, "processor", sizeof "processor" - 1 ) != 0) continue;
@@ -587,13 +605,72 @@
}
VG_(free)( file_buf );
- VG_(debugLog)(1, "machine", "model = %s\n", model_map[model].name);
-
+ VG_(debugLog)(1, "machine", "model = %s\n",
+ model == VEX_S390X_MODEL_UNKNOWN ? "UNKNOWN"
+ : model_map[model].name);
return model;
}
#endif /* VGA_s390x */
+#ifdef VGA_mips32
+
+/* Read /proc/cpuinfo and return the machine model. */
+static UInt VG_(get_machine_model)(void)
+{
+ char *search_MIPS_str = "MIPS";
+ char *search_Broadcom_str = "Broadcom";
+ Int n, fh;
+ SysRes fd;
+ SizeT num_bytes, file_buf_size;
+ HChar *file_buf;
+
+ /* Slurp contents of /proc/cpuinfo into FILE_BUF */
+ fd = VG_(open)( "/proc/cpuinfo", 0, VKI_S_IRUSR );
+ if ( sr_isError(fd) ) return -1;
+
+ fh = sr_Res(fd);
+
+ /* Determine the size of /proc/cpuinfo.
+ Work around broken-ness in /proc file system implementation.
+ fstat returns a zero size for /proc/cpuinfo although it is
+ claimed to be a regular file. */
+ num_bytes = 0;
+ file_buf_size = 1000;
+ file_buf = VG_(malloc)("cpuinfo", file_buf_size + 1);
+ while (42) {
+ n = VG_(read)(fh, file_buf, file_buf_size);
+ if (n < 0) break;
+
+ num_bytes += n;
+ if (n < file_buf_size) break; /* reached EOF */
+ }
+
+ if (n < 0) num_bytes = 0; /* read error; ignore contents */
+
+ if (num_bytes > file_buf_size) {
+ VG_(free)( file_buf );
+ VG_(lseek)( fh, 0, VKI_SEEK_SET );
+ file_buf = VG_(malloc)( "cpuinfo", num_bytes + 1 );
+ n = VG_(read)( fh, file_buf, num_bytes );
+ if (n < 0) num_bytes = 0;
+ }
+
+ file_buf[num_bytes] = '\0';
+ VG_(close)(fh);
+
+ /* Parse file */
+ if (VG_(strstr) (file_buf, search_Broadcom_str) != NULL)
+ return VEX_PRID_COMP_BROADCOM;
+ if (VG_(strstr) (file_buf, search_MIPS_str) != NULL)
+ return VEX_PRID_COMP_MIPS;
+
+ /* Did not find string in the proc file. */
+ return -1;
+}
+
+#endif
+
/* Determine what insn set and insn set variant the host has, and
record it. To be called once at system startup. Returns False if
this a CPU incapable of running Valgrind. */
@@ -678,7 +755,7 @@
#elif defined(VGA_amd64)
{ Bool have_sse3, have_cx8, have_cx16;
- Bool have_lzcnt;
+ Bool have_lzcnt, have_avx /*, have_fma*/;
UInt eax, ebx, ecx, edx, max_extended;
UChar vstr[13];
vstr[0] = 0;
@@ -707,9 +784,33 @@
// we assume that SSE1 and SSE2 are available by default
have_sse3 = (ecx & (1<<0)) != 0; /* True => have sse3 insns */
- // ssse3 is ecx:9
- // sse41 is ecx:19
- // sse42 is ecx:20
+ // ssse3 is ecx:9
+ // sse41 is ecx:19
+ // sse42 is ecx:20
+
+ // osxsave is ecx:27
+ // avx is ecx:28
+ // fma is ecx:12
+ have_avx = False;
+ /* have_fma = False; */
+ if ( (ecx & ((1<<27)|(1<<28))) == ((1<<27)|(1<<28)) ) {
+ /* processor supports AVX instructions and XGETBV is enabled
+ by OS */
+ ULong w;
+ __asm__ __volatile__("movq $0,%%rcx ; "
+ ".byte 0x0F,0x01,0xD0 ; " /* xgetbv */
+ "movq %%rax,%0"
+ :/*OUT*/"=r"(w) :/*IN*/
+ :/*TRASH*/"rdx","rcx");
+ if ((w & 6) == 6) {
+ /* OS has enabled both XMM and YMM state support */
+ have_avx = True;
+ /* have_fma = (ecx & (1<<12)) != 0; */
+ /* have_fma: Probably correct, but gcc complains due to
+ unusedness. &*/
+ }
+ }
+
/* cmpxchg8b is a minimum requirement now; if we don't have it we
must simply give up. But all CPUs since Pentium-I have it, so
@@ -730,9 +831,10 @@
}
va = VexArchAMD64;
- vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0)
- | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0)
- | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0);
+ vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0)
+ | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0)
+ | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0)
+ | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0);
return True;
}
@@ -748,7 +850,7 @@
vki_sigaction_fromK_t saved_sigill_act, saved_sigfpe_act;
vki_sigaction_toK_t tmp_sigill_act, tmp_sigfpe_act;
- volatile Bool have_F, have_V, have_FX, have_GX, have_VX;
+ volatile Bool have_F, have_V, have_FX, have_GX, have_VX, have_DFP;
Int r;
/* This is a kludge. Really we ought to back-convert saved_act
@@ -835,6 +937,13 @@
__asm__ __volatile__(".long 0xf0000564"); /* xsabsdp XT,XB */
}
+ /* Check for Decimal Floating Point (DFP) support. */
+ have_DFP = True;
+ if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
+ have_DFP = False;
+ } else {
+ __asm__ __volatile__(".long 0xee4e8005"); /* dadd FRT,FRA, FRB */
+ }
/* determine dcbz/dcbzl sizes while we still have the signal
* handlers registered */
@@ -846,9 +955,9 @@
vg_assert(r == 0);
r = VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
vg_assert(r == 0);
- VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d\n",
+ VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d\n",
(Int)have_F, (Int)have_V, (Int)have_FX,
- (Int)have_GX, (Int)have_VX);
+ (Int)have_GX, (Int)have_VX, (Int)have_DFP);
/* Make FP a prerequisite for VMX (bogusly so), and for FX and GX. */
if (have_V && !have_F)
have_V = False;
@@ -868,6 +977,8 @@
if (have_FX) vai.hwcaps |= VEX_HWCAPS_PPC32_FX;
if (have_GX) vai.hwcaps |= VEX_HWCAPS_PPC32_GX;
if (have_VX) vai.hwcaps |= VEX_HWCAPS_PPC32_VX;
+ if (have_DFP) vai.hwcaps |= VEX_HWCAPS_PPC32_DFP;
+
/* But we're not done yet: VG_(machine_ppc32_set_clszB) must be
called before we're ready to go. */
@@ -881,7 +992,7 @@
vki_sigaction_fromK_t saved_sigill_act, saved_sigfpe_act;
vki_sigaction_toK_t tmp_sigill_act, tmp_sigfpe_act;
- volatile Bool have_F, have_V, have_FX, have_GX, have_VX;
+ volatile Bool have_F, have_V, have_FX, have_GX, have_VX, have_DFP;
Int r;
/* This is a kludge. Really we ought to back-convert saved_act
@@ -960,6 +1071,14 @@
__asm__ __volatile__(".long 0xf0000564"); /* xsabsdp XT,XB */
}
+ /* Check for Decimal Floating Point (DFP) support. */
+ have_DFP = True;
+ if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
+ have_DFP = False;
+ } else {
+ __asm__ __volatile__(".long 0xee4e8005"); /* dadd FRT,FRA, FRB */
+ }
+
/* determine dcbz/dcbzl sizes while we still have the signal
* handlers registered */
find_ppc_dcbz_sz(&vai);
@@ -967,9 +1086,9 @@
VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL);
VG_(sigaction)(VKI_SIGFPE, &saved_sigfpe_act, NULL);
VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
- VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d\n",
+ VG_(debugLog)(1, "machine", "F %d V %d FX %d GX %d VX %d DFP %d\n",
(Int)have_F, (Int)have_V, (Int)have_FX,
- (Int)have_GX, (Int)have_VX);
+ (Int)have_GX, (Int)have_VX, (Int)have_DFP);
/* on ppc64, if we don't even have FP, just give up. */
if (!have_F)
return False;
@@ -983,6 +1102,7 @@
if (have_FX) vai.hwcaps |= VEX_HWCAPS_PPC64_FX;
if (have_GX) vai.hwcaps |= VEX_HWCAPS_PPC64_GX;
if (have_VX) vai.hwcaps |= VEX_HWCAPS_PPC64_VX;
+ if (have_DFP) vai.hwcaps |= VEX_HWCAPS_PPC64_DFP;
/* But we're not done yet: VG_(machine_ppc64_set_clszB) must be
called before we're ready to go. */
@@ -997,6 +1117,7 @@
vki_sigaction_toK_t tmp_sigill_act;
volatile Bool have_LDISP, have_EIMM, have_GIE, have_DFP, have_FGX;
+ volatile Bool have_STFLE, have_ETF2, have_ETF3;
Int r, model;
/* Unblock SIGILL and stash away the old action for that signal */
@@ -1064,6 +1185,27 @@
__asm__ __volatile__(".long 0xb3cd0000" : : : "r0"); /* lgdr r0,f0 */
}
+ /* Detect presence of the ETF2-enhancement facility using the
+ STFLE insn. Note, that STFLE and ETF2 were introduced at the same
+ time, so the absence of STLFE implies the absence of ETF2. */
+ have_STFLE = True;
+ have_ETF2 = False;
+ have_ETF3 = False;
+ if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
+ have_STFLE = False;
+ } else {
+ ULong hoststfle[1];
+ register ULong reg0 asm("0") = 0; /* one double word available */
+
+ __asm__ __volatile__(" .insn s,0xb2b00000,%0\n" /* stfle */
+ : "=m" (hoststfle), "+d"(reg0)
+ : : "cc", "memory");
+ if (hoststfle[0] & (1ULL << (63 - 24)))
+ have_ETF2 = True;
+ if (hoststfle[0] & (1ULL << (63 - 30)))
+ have_ETF3 = True;
+ }
+
/* Restore signals */
r = VG_(sigaction)(VKI_SIGILL, &saved_sigill_act, NULL);
vg_assert(r == 0);
@@ -1073,11 +1215,13 @@
model = VG_(get_machine_model)();
- VG_(debugLog)(1, "machine", "machine %d LDISP %d EIMM %d GIE %d DFP %d "
- "FGX %d\n", model, have_LDISP, have_EIMM, have_GIE,
- have_DFP, have_FGX);
+ /* If the model is "unknown" don't treat this as an error. Assume
+ this is a brand-new machine model for which we don't have the
+ identification yet. Keeping fingers crossed. */
- if (model == VEX_S390X_MODEL_INVALID) return False;
+ VG_(debugLog)(1, "machine", "machine %d LDISP %d EIMM %d GIE %d DFP %d "
+ "FGX %d STFLE %d ETF2 %d ETF3 %d\n", model, have_LDISP, have_EIMM,
+ have_GIE, have_DFP, have_FGX, have_STFLE, have_ETF2, have_ETF3);
vai.hwcaps = model;
if (have_LDISP) {
@@ -1090,6 +1234,9 @@
if (have_GIE) vai.hwcaps |= VEX_HWCAPS_S390X_GIE;
if (have_DFP) vai.hwcaps |= VEX_HWCAPS_S390X_DFP;
if (have_FGX) vai.hwcaps |= VEX_HWCAPS_S390X_FGX;
+ if (have_ETF2) vai.hwcaps |= VEX_HWCAPS_S390X_ETF2;
+ if (have_ETF3) vai.hwcaps |= VEX_HWCAPS_S390X_ETF3;
+ if (have_STFLE) vai.hwcaps |= VEX_HWCAPS_S390X_STFLE;
VG_(debugLog)(1, "machine", "hwcaps = 0x%x\n", vai.hwcaps);
@@ -1205,6 +1352,17 @@
return True;
}
+#elif defined(VGA_mips32)
+ {
+ va = VexArchMIPS32;
+ UInt model = VG_(get_machine_model)();
+ if (model== -1)
+ return False;
+
+ vai.hwcaps = model;
+ return True;
+ }
+
#else
# error "Unknown arch"
#endif
@@ -1272,6 +1430,71 @@
}
+/* Returns the size of the largest guest register that we will
+ simulate in this run. This depends on both the guest architecture
+ and on the specific capabilities we are simulating for that guest
+ (eg, AVX or non-AVX ?, for amd64). Should return either 4, 8, 16
+ or 32. General rule: if in doubt, return a value larger than
+ reality.
+
+ This information is needed by Cachegrind and Callgrind to decide
+ what the minimum cache line size they are prepared to simulate is.
+ Basically require that the minimum cache line size is at least as
+ large as the largest register that might get transferred to/from
+ memory, so as to guarantee that any such transaction can straddle
+ at most 2 cache lines.
+*/
+Int VG_(machine_get_size_of_largest_guest_register) ( void )
+{
+ vg_assert(hwcaps_done);
+ /* Once hwcaps_done is True, we can fish around inside va/vai to
+ find the information we need. */
+
+# if defined(VGA_x86)
+ vg_assert(va == VexArchX86);
+ /* We don't support AVX, so 32 is out. At the other end, even if
+ we don't support any SSE, the X87 can generate 10 byte
+ transfers, so let's say 16 to be on the safe side. Hence the
+ answer is always 16. */
+ return 16;
+
+# elif defined(VGA_amd64)
+ /* if AVX then 32 else 16 */
+ return (vai.hwcaps & VEX_HWCAPS_AMD64_AVX) ? 32 : 16;
+
+# elif defined(VGA_ppc32)
+ /* 8 if boring; 16 if signs of Altivec or other exotic stuff */
+ if (vai.hwcaps & VEX_HWCAPS_PPC32_V) return 16;
+ if (vai.hwcaps & VEX_HWCAPS_PPC32_VX) return 16;
+ if (vai.hwcaps & VEX_HWCAPS_PPC32_DFP) return 16;
+ return 8;
+
+# elif defined(VGA_ppc64)
+ /* 8 if boring; 16 if signs of Altivec or other exotic stuff */
+ if (vai.hwcaps & VEX_HWCAPS_PPC64_V) return 16;
+ if (vai.hwcaps & VEX_HWCAPS_PPC64_VX) return 16;
+ if (vai.hwcaps & VEX_HWCAPS_PPC64_DFP) return 16;
+ return 8;
+
+# elif defined(VGA_s390x)
+ return 8;
+
+# elif defined(VGA_arm)
+ /* Really it depends whether or not we have NEON, but let's just
+ assume we always do. */
+ return 16;
+
+# elif defined(VGA_mips32)
+ /* The guest state implies 4, but that can't really be true, can
+ it? */
+ return 8;
+
+# else
+# error "Unknown arch"
+# endif
+}
+
+
// Given a pointer to a function as obtained by "& functionname" in C,
// produce a pointer to the actual entry point for the function.
void* VG_(fnptr_to_fnentry)( void* f )
@@ -1279,7 +1502,7 @@
# if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \
|| defined(VGP_arm_linux) \
|| defined(VGP_ppc32_linux) || defined(VGO_darwin) \
- || defined(VGP_s390x_linux)
+ || defined(VGP_s390x_linux) || defined(VGP_mips32_linux)
return f;
# elif defined(VGP_ppc64_linux)
/* ppc64-linux uses the AIX scheme, in which f is a pointer to a
diff --git a/main/coregrind/m_main.c b/main/coregrind/m_main.c
index 2dc7d0e..9ac8387 100644
--- a/main/coregrind/m_main.c
+++ b/main/coregrind/m_main.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -65,6 +65,10 @@
#include "pub_core_translate.h" // For VG_(translate)
#include "pub_core_trampoline.h"
#include "pub_core_transtab.h"
+#include "pub_tool_inner.h"
+#if defined(ENABLE_INNER_CLIENT_REQUEST)
+#include "valgrind.h"
+#endif
/*====================================================================*/
@@ -157,7 +161,9 @@
" [use current 'ulimit' value]\n"
"\n"
" user options for Valgrind tools that replace malloc:\n"
-" --alignment=<number> set minimum alignment of heap allocations [%ld]\n"
+" --alignment=<number> set minimum alignment of heap allocations [%s]\n"
+" --redzone-size=<number> set minimum size of redzones added before/after\n"
+" heap blocks (in bytes). [%s]\n"
"\n"
" uncommon user options for all Valgrind tools:\n"
" --fullpath-after= (with nothing after the '=')\n"
@@ -180,12 +186,18 @@
" --run-libc-freeres=no|yes free up glibc memory at exit on Linux? [yes]\n"
" --sim-hints=hint1,hint2,... known hints:\n"
" lax-ioctls, enable-outer, fuse-compatible [none]\n"
+" --fair-sched=no|yes|try schedule threads fairly on multicore systems [no]\n"
" --kernel-variant=variant1,variant2,... known variants: bproc [none]\n"
" handle non-standard kernel variants\n"
" --show-emwarns=no|yes show warnings about emulation limits? [no]\n"
" --require-text-symbol=:sonamepattern:symbolpattern abort run if the\n"
" stated shared object doesn't have the stated\n"
" text symbol. Patterns can contain ? and *.\n"
+" --soname-synonyms=syn1=pattern1,syn2=pattern2,... synonym soname\n"
+" specify patterns for function wrapping or replacement.\n"
+" To use a non-libc malloc library that is\n"
+" in the main exe: --soname-synonyms=somalloc=NONE\n"
+" in libxyzzy.so: --soname-synonyms=somalloc=libxyzzy.so\n"
"\n";
Char* usage2 =
@@ -197,6 +209,7 @@
" --trace-flags=<XXXXXXXX> show generated code? (X = 0|1) [00000000]\n"
" --profile-flags=<XXXXXXXX> ditto, but for profiling (X = 0|1) [00000000]\n"
" --trace-notbelow=<number> only show BBs above <number> [999999999]\n"
+" --trace-notabove=<number> only show BBs below <number> [0]\n"
" --trace-syscalls=no|yes show all system calls? [no]\n"
" --trace-signals=no|yes show signal handling details? [no]\n"
" --trace-symtab=no|yes show symbol table details? [no]\n"
@@ -208,6 +221,8 @@
" --trace-redir=no|yes show redirection details? [no]\n"
" --trace-sched=no|yes show thread scheduler details? [no]\n"
" --profile-heap=no|yes profile Valgrind's own space use\n"
+" --core-redzone=<number> set minimum size of redzones added before/after\n"
+" heap blocks allocated for Valgrind internal use (in bytes) [4]\n"
" --wait-for-gdb=yes|no pause on startup to wait for gdb attach\n"
" --sym-offsets=yes|no show syms in form 'name+offset' ? [no]\n"
" --command-line-only=no|yes only use command line options [no]\n"
@@ -215,7 +230,9 @@
" Vex options for all Valgrind tools:\n"
" --vex-iropt-verbosity=<0..9> [0]\n"
" --vex-iropt-level=<0..2> [2]\n"
-" --vex-iropt-precise-memory-exns=no|yes [no]\n"
+" --vex-iropt-register-updates=unwindregs-at-mem-access\n"
+" |allregs-at-mem-access\n"
+" |allregs-at-each-insn [unwindregs-at-mem-access]\n"
" --vex-iropt-unroll-thresh=<0..400> [120]\n"
" --vex-guest-max-insns=<1..100> [50]\n"
" --vex-guest-chase-thresh=<0..99> [10]\n"
@@ -229,7 +246,7 @@
" 0000 0100 show selecting insns\n"
" 0000 0010 show after reg-alloc\n"
" 0000 0001 show final assembly\n"
-" (Nb: you need --trace-notbelow with --trace-flags for full details)\n"
+" (Nb: you need --trace-notbelow and/or --trace-notabove with --trace-flags for full details)\n"
"\n"
" debugging options for Valgrind tools that report errors\n"
" --dump-error=<number> show translation for basic block associated\n"
@@ -244,22 +261,36 @@
" Extra options read from ~/.valgrindrc, $VALGRIND_OPTS, ./.valgrindrc\n"
"\n"
" %s is %s\n"
-" Valgrind is Copyright (C) 2000-2011, and GNU GPL'd, by Julian Seward et al.\n"
-" LibVEX is Copyright (C) 2004-2011, and GNU GPL'd, by OpenWorks LLP et al.\n"
+" Valgrind is Copyright (C) 2000-2012, and GNU GPL'd, by Julian Seward et al.\n"
+" LibVEX is Copyright (C) 2004-2012, and GNU GPL'd, by OpenWorks LLP et al.\n"
"\n"
" Bug reports, feedback, admiration, abuse, etc, to: %s.\n"
"\n";
Char* gdb_path = GDB_PATH;
+ Char default_alignment[30];
+ Char default_redzone_size[30];
// Ensure the message goes to stdout
VG_(log_output_sink).fd = 1;
VG_(log_output_sink).is_socket = False;
- /* 'usage1' expects two int, two char* argument, and one SizeT argument. */
+ if (VG_(needs).malloc_replacement) {
+ VG_(sprintf)(default_alignment, "%d", VG_MIN_MALLOC_SZB);
+ VG_(sprintf)(default_redzone_size, "%lu", VG_(tdict).tool_client_redzone_szB);
+ } else {
+ VG_(strcpy)(default_alignment, "not used by this tool");
+ VG_(strcpy)(default_redzone_size, "not used by this tool");
+ }
+ /* 'usage1' a type as described after each arg. */
VG_(printf)(usage1,
- VG_(clo_vgdb_error), gdb_path, VG_MIN_MALLOC_SZB,
- VG_(clo_vgdb_poll), VG_(vgdb_prefix_default)());
+ VG_(clo_vgdb_error) /* int */,
+ gdb_path /* char* */,
+ default_alignment /* char* */,
+ default_redzone_size /* char* */,
+ VG_(clo_vgdb_poll) /* int */,
+ VG_(vgdb_prefix_default)() /* char* */
+ );
if (VG_(details).name) {
VG_(printf)(" user options for %s:\n", VG_(details).name);
if (VG_(needs).command_line_options)
@@ -293,6 +324,7 @@
- get the toolname (--tool=)
- set VG_(clo_max_stackframe) (--max-stackframe=)
- set VG_(clo_main_stacksize) (--main-stacksize=)
+ - set VG_(clo_sim_hints) (--sim-hints=)
That's all it does. The main command line processing is done below
by main_process_cmd_line_options. Note that
@@ -333,67 +365,14 @@
// before main_process_cmd_line_options().
else if VG_INT_CLO(str, "--max-stackframe", VG_(clo_max_stackframe)) {}
else if VG_INT_CLO(str, "--main-stacksize", VG_(clo_main_stacksize)) {}
+
+ // Set up VG_(clo_sim_hints). This is needed a.o. for an inner
+ // running in an outer, to have "no-inner-prefix" enabled
+ // as early as possible.
+ else if VG_STR_CLO (str, "--sim-hints", VG_(clo_sim_hints)) {}
}
}
-Int reopen_output_fd(Bool xml) {
- // Returns FD
- Char *filename = NULL;
- Char *fsname_unexpanded = xml ? VG_(clo_xml_fname_unexpanded) :
- VG_(clo_log_fname_unexpanded);
- const Char *output_type = xml ? "xml" : "log";
- Int ret = -1;
- SysRes sres;
-
- vg_assert(fsname_unexpanded != NULL);
- vg_assert(VG_(strlen)(fsname_unexpanded) <= 900); /* paranoia */
-
- // Nb: we overwrite an existing file of this name without asking
- // any questions.
- filename = VG_(expand_file_name)(xml ? "--xml-file" : "--log-file",
- fsname_unexpanded);
- sres = VG_(open)(filename,
- VKI_O_CREAT|VKI_O_WRONLY|VKI_O_TRUNC,
- VKI_S_IRUSR|VKI_S_IWUSR);
- if (!sr_isError(sres)) {
- ret = sr_Res(sres);
- if (xml)
- VG_(clo_xml_fname_expanded) = filename;
- else
- VG_(clo_log_fname_expanded) = filename;
-
- /* strdup here is probably paranoid overkill, but ... */
- // TODO: do we need to do anything with it?
- /* *fsname_unexpanded = VG_(strdup)( "main.mpclo.2",
- xml_fsname_unexpanded ); */
- } else {
- VG_(message)(Vg_UserMsg,
- "Can't create %s file '%s' (%s); giving up!\n",
- output_type, filename, VG_(strerror)(sr_Err(sres)));
- VG_(fmsg_bad_option)("--[xml|log]-file=<file>",
- "--[xml|log]-file=<file> (didn't work out for some reason.)");
- /*NOTREACHED*/
- }
-
- return ret;
-}
-
-static Int move_fd_into_safe_range(Int fd, Bool xml) {
- OutputSink *sink = xml ? &(VG_(xml_output_sink)) : &(VG_(log_output_sink));
- // Move fd into the safe range, so it doesn't conflict with any app fds.
- fd = VG_(fcntl)(fd, VKI_F_DUPFD, VG_(fd_hard_limit));
- if (fd < 0) {
- VG_(printf)("valgrind: failed to move %s file fd "
- "into safe range, using stderr\n", xml ? "XML" : "log");
- sink->fd = 2; // stderr
- sink->is_socket = False;
- } else {
- sink->fd = fd;
- VG_(fcntl)(fd, VKI_F_SETFD, VKI_FD_CLOEXEC);
- }
- return fd;
-}
-
/* The main processing for command line options. See comments above
on early_process_cmd_line_options.
@@ -420,11 +399,13 @@
*/
static
void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
+ /*OUT*/Char** xml_fname_unexpanded,
const HChar* toolname )
{
// VG_(clo_log_fd) is used by all the messaging. It starts as 2 (stderr)
// and we cannot change it until we know what we are changing it to is
// ok. So we have tmp_log_fd to hold the tmp fd prior to that point.
+ SysRes sres;
Int i, tmp_log_fd, tmp_xml_fd;
Int toolname_len = VG_(strlen)(toolname);
Char* tmp_str; // Used in a couple of places.
@@ -506,7 +487,25 @@
else if VG_STREQ( arg, "-d") {}
else if VG_STREQN(16, arg, "--max-stackframe") {}
else if VG_STREQN(16, arg, "--main-stacksize") {}
+ else if VG_STREQN(11, arg, "--sim-hints") {}
else if VG_STREQN(14, arg, "--profile-heap") {}
+ else if VG_STREQN(14, arg, "--core-redzone-size") {}
+ else if VG_STREQN(14, arg, "--redzone-size") {}
+
+ /* Obsolete options. Report an error and exit */
+ else if VG_STREQN(34, arg, "--vex-iropt-precise-memory-exns=no") {
+ VG_(fmsg_bad_option)
+ (arg,
+ "--vex-iropt-precise-memory-exns is obsolete\n"
+ "Use --vex-iropt-register-updates=unwindregs-at-mem-access instead\n");
+ }
+ else if VG_STREQN(35, arg, "--vex-iropt-precise-memory-exns=yes") {
+ VG_(fmsg_bad_option)
+ (arg,
+ "--vex-iropt-precise-memory-exns is obsolete\n"
+ "Use --vex-iropt-register-updates=allregs-at-mem-access instead\n"
+ " (or --vex-iropt-register-updates=allregs-at-each-insn)\n");
+ }
// These options are new.
else if (VG_STREQ(arg, "-v") ||
@@ -523,7 +522,12 @@
else if VG_XACT_CLO(arg, "--vgdb=no", VG_(clo_vgdb), Vg_VgdbNo) {}
else if VG_XACT_CLO(arg, "--vgdb=yes", VG_(clo_vgdb), Vg_VgdbYes) {}
- else if VG_XACT_CLO(arg, "--vgdb=full", VG_(clo_vgdb), Vg_VgdbFull) {}
+ else if VG_XACT_CLO(arg, "--vgdb=full", VG_(clo_vgdb), Vg_VgdbFull) {
+ /* automatically updates register values at each insn
+ with --vgdb=full */
+ VG_(clo_vex_control).iropt_register_updates
+ = VexRegUpdAllregsAtEachInsn;
+ }
else if VG_INT_CLO (arg, "--vgdb-poll", VG_(clo_vgdb_poll)) {}
else if VG_INT_CLO (arg, "--vgdb-error", VG_(clo_vgdb_error)) {}
else if VG_STR_CLO (arg, "--vgdb-prefix", VG_(clo_vgdb_prefix)) {}
@@ -531,6 +535,7 @@
VG_(clo_vgdb_shadow_registers)) {}
else if VG_BOOL_CLO(arg, "--db-attach", VG_(clo_db_attach)) {}
else if VG_BOOL_CLO(arg, "--demangle", VG_(clo_demangle)) {}
+ else if VG_STR_CLO (arg, "--soname-synonyms",VG_(clo_soname_synonyms)) {}
else if VG_BOOL_CLO(arg, "--error-limit", VG_(clo_error_limit)) {}
else if VG_INT_CLO (arg, "--error-exitcode", VG_(clo_error_exitcode)) {}
else if VG_BOOL_CLO(arg, "--show-emwarns", VG_(clo_show_emwarns)) {}
@@ -542,6 +547,17 @@
else if VG_BOOL_CLO(arg, "--trace-children", VG_(clo_trace_children)) {}
else if VG_BOOL_CLO(arg, "--child-silent-after-fork",
VG_(clo_child_silent_after_fork)) {}
+ else if VG_STR_CLO(arg, "--fair-sched", tmp_str) {
+ if (VG_(strcmp)(tmp_str, "yes") == 0)
+ VG_(clo_fair_sched) = enable_fair_sched;
+ else if (VG_(strcmp)(tmp_str, "try") == 0)
+ VG_(clo_fair_sched) = try_fair_sched;
+ else if (VG_(strcmp)(tmp_str, "no") == 0)
+ VG_(clo_fair_sched) = disable_fair_sched;
+ else
+ VG_(fmsg_bad_option)(arg, "");
+
+ }
else if VG_BOOL_CLO(arg, "--trace-sched", VG_(clo_trace_sched)) {}
else if VG_BOOL_CLO(arg, "--trace-signals", VG_(clo_trace_signals)) {}
else if VG_BOOL_CLO(arg, "--trace-symtab", VG_(clo_trace_symtab)) {}
@@ -558,7 +574,6 @@
else if VG_BOOL_CLO(arg, "--trace-syscalls", VG_(clo_trace_syscalls)) {}
else if VG_BOOL_CLO(arg, "--wait-for-gdb", VG_(clo_wait_for_gdb)) {}
else if VG_STR_CLO (arg, "--db-command", VG_(clo_db_command)) {}
- else if VG_STR_CLO (arg, "--sim-hints", VG_(clo_sim_hints)) {}
else if VG_BOOL_CLO(arg, "--sym-offsets", VG_(clo_sym_offsets)) {}
else if VG_BOOL_CLO(arg, "--read-var-info", VG_(clo_read_var_info)) {}
@@ -578,8 +593,6 @@
VG_(clo_smc_check),
Vg_SmcAllNonFile);
- else if VG_STR_CLO (arg, "--memfs-malloc-path", VG_(clo_memfs_malloc_path)) {}
- else if VG_INT_CLO (arg, "--memfs-page-size", VG_(clo_memfs_page_size)) {}
else if VG_STR_CLO (arg, "--kernel-variant", VG_(clo_kernel_variant)) {}
else if VG_BOOL_CLO(arg, "--dsymutil", VG_(clo_dsymutil)) {}
@@ -593,8 +606,18 @@
VG_(clo_vex_control).iropt_verbosity, 0, 10) {}
else if VG_BINT_CLO(arg, "--vex-iropt-level",
VG_(clo_vex_control).iropt_level, 0, 2) {}
- else if VG_BOOL_CLO(arg, "--vex-iropt-precise-memory-exns",
- VG_(clo_vex_control).iropt_precise_memory_exns) {}
+ else if VG_XACT_CLO(arg,
+ "--vex-iropt-register-updates=unwindregs-at-mem-access",
+ VG_(clo_vex_control).iropt_register_updates,
+ VexRegUpdUnwindregsAtMemAccess);
+ else if VG_XACT_CLO(arg,
+ "--vex-iropt-register-updates=allregs-at-mem-access",
+ VG_(clo_vex_control).iropt_register_updates,
+ VexRegUpdAllregsAtMemAccess);
+ else if VG_XACT_CLO(arg,
+ "--vex-iropt-register-updates=allregs-at-each-insn",
+ VG_(clo_vex_control).iropt_register_updates,
+ VexRegUpdAllregsAtEachInsn);
else if VG_BINT_CLO(arg, "--vex-iropt-unroll-thresh",
VG_(clo_vex_control).iropt_unroll_thresh, 0, 400) {}
else if VG_BINT_CLO(arg, "--vex-guest-max-insns",
@@ -615,13 +638,9 @@
else if VG_STR_CLO(arg, "--log-file", log_fsname_unexpanded) {
log_to = VgLogTo_File;
- VG_(clo_log_fname_unexpanded) =
- VG_(strdup)("", log_fsname_unexpanded);
}
else if VG_STR_CLO(arg, "--xml-file", xml_fsname_unexpanded) {
xml_to = VgLogTo_File;
- VG_(clo_xml_fname_unexpanded) =
- VG_(strdup)("", xml_fsname_unexpanded);
}
else if VG_STR_CLO(arg, "--log-socket", log_fsname_unexpanded) {
@@ -722,6 +741,8 @@
else if VG_INT_CLO (arg, "--trace-notbelow", VG_(clo_trace_notbelow)) {}
+ else if VG_INT_CLO (arg, "--trace-notabove", VG_(clo_trace_notabove)) {}
+
else if VG_XACT_CLO(arg, "--gen-suppressions=no",
VG_(clo_gen_suppressions), 0) {}
else if VG_XACT_CLO(arg, "--gen-suppressions=yes",
@@ -729,8 +750,6 @@
else if VG_XACT_CLO(arg, "--gen-suppressions=all",
VG_(clo_gen_suppressions), 2) {}
- else if VG_STR_CLO(arg, "--nacl-file", VG_(clo_nacl_file)) {}
-
else if ( ! VG_(needs).command_line_options
|| ! VG_TDICT_CALL(tool_process_cmd_line_option, arg) ) {
VG_(fmsg_bad_option)(arg, "");
@@ -758,15 +777,39 @@
if (VG_(clo_verbosity) < 0)
VG_(clo_verbosity) = 0;
+ if (VG_(clo_trace_notbelow) == -1) {
+ if (VG_(clo_trace_notabove) == -1) {
+ /* [] */
+ VG_(clo_trace_notbelow) = 2147483647;
+ VG_(clo_trace_notabove) = 0;
+ } else {
+ /* [0 .. notabove] */
+ VG_(clo_trace_notbelow) = 0;
+ }
+ } else {
+ if (VG_(clo_trace_notabove) == -1) {
+ /* [notbelow .. ] */
+ VG_(clo_trace_notabove) = 2147483647;
+ } else {
+ /* [notbelow .. notabove] */
+ }
+ }
+
VG_(dyn_vgdb_error) = VG_(clo_vgdb_error);
+ if (VG_(clo_gen_suppressions) > 0 &&
+ !VG_(needs).core_errors && !VG_(needs).tool_errors) {
+ VG_(fmsg_bad_option)("--gen-suppressions=yes",
+ "Can't use --gen-suppressions= with %s\n"
+ "because it doesn't generate errors.\n", VG_(details).name);
+ }
+
/* If XML output is requested, check that the tool actually
supports it. */
if (VG_(clo_xml) && !VG_(needs).xml_output) {
VG_(clo_xml) = False;
- VG_(message)(Vg_UserMsg,
+ VG_(fmsg_bad_option)("--xml=yes",
"%s does not support XML output.\n", VG_(details).name);
- VG_(fmsg_bad_option)("--xml=yes", "\n");
/*NOTREACHED*/
}
@@ -850,7 +893,27 @@
break;
case VgLogTo_File: {
- tmp_log_fd = reopen_output_fd(False);
+ Char* logfilename;
+
+ vg_assert(log_fsname_unexpanded != NULL);
+ vg_assert(VG_(strlen)(log_fsname_unexpanded) <= 900); /* paranoia */
+
+ // Nb: we overwrite an existing file of this name without asking
+ // any questions.
+ logfilename = VG_(expand_file_name)("--log-file",
+ log_fsname_unexpanded);
+ sres = VG_(open)(logfilename,
+ VKI_O_CREAT|VKI_O_WRONLY|VKI_O_TRUNC,
+ VKI_S_IRUSR|VKI_S_IWUSR);
+ if (!sr_isError(sres)) {
+ tmp_log_fd = sr_Res(sres);
+ VG_(clo_log_fname_expanded) = logfilename;
+ } else {
+ VG_(fmsg)("can't create log file '%s': %s\n",
+ logfilename, VG_(strerror)(sr_Err(sres)));
+ VG_(exit)(1);
+ /*NOTREACHED*/
+ }
break;
}
@@ -889,7 +952,30 @@
break;
case VgLogTo_File: {
- tmp_xml_fd = reopen_output_fd(True);
+ Char* xmlfilename;
+
+ vg_assert(xml_fsname_unexpanded != NULL);
+ vg_assert(VG_(strlen)(xml_fsname_unexpanded) <= 900); /* paranoia */
+
+ // Nb: we overwrite an existing file of this name without asking
+ // any questions.
+ xmlfilename = VG_(expand_file_name)("--xml-file",
+ xml_fsname_unexpanded);
+ sres = VG_(open)(xmlfilename,
+ VKI_O_CREAT|VKI_O_WRONLY|VKI_O_TRUNC,
+ VKI_S_IRUSR|VKI_S_IWUSR);
+ if (!sr_isError(sres)) {
+ tmp_xml_fd = sr_Res(sres);
+ VG_(clo_xml_fname_expanded) = xmlfilename;
+ /* strdup here is probably paranoid overkill, but ... */
+ *xml_fname_unexpanded = VG_(strdup)( "main.mpclo.2",
+ xml_fsname_unexpanded );
+ } else {
+ VG_(fmsg)("can't create XML file '%s': %s\n",
+ xmlfilename, VG_(strerror)(sr_Err(sres)));
+ VG_(exit)(1);
+ /*NOTREACHED*/
+ }
break;
}
@@ -935,7 +1021,18 @@
// Finalise the output fds: the log fd ..
if (tmp_log_fd >= 0) {
- tmp_log_fd = move_fd_into_safe_range(tmp_log_fd, False);
+ // Move log_fd into the safe range, so it doesn't conflict with
+ // any app fds.
+ tmp_log_fd = VG_(fcntl)(tmp_log_fd, VKI_F_DUPFD, VG_(fd_hard_limit));
+ if (tmp_log_fd < 0) {
+ VG_(message)(Vg_UserMsg, "valgrind: failed to move logfile fd "
+ "into safe range, using stderr\n");
+ VG_(log_output_sink).fd = 2; // stderr
+ VG_(log_output_sink).is_socket = False;
+ } else {
+ VG_(log_output_sink).fd = tmp_log_fd;
+ VG_(fcntl)(VG_(log_output_sink).fd, VKI_F_SETFD, VKI_FD_CLOEXEC);
+ }
} else {
// If they said --log-fd=-1, don't print anything. Plausible for use in
// regression testing suites that use client requests to count errors.
@@ -946,7 +1043,18 @@
// Finalise the output fds: and the XML fd ..
if (tmp_xml_fd >= 0) {
- tmp_xml_fd = move_fd_into_safe_range(tmp_xml_fd, True);
+ // Move xml_fd into the safe range, so it doesn't conflict with
+ // any app fds.
+ tmp_xml_fd = VG_(fcntl)(tmp_xml_fd, VKI_F_DUPFD, VG_(fd_hard_limit));
+ if (tmp_xml_fd < 0) {
+ VG_(message)(Vg_UserMsg, "valgrind: failed to move XML file fd "
+ "into safe range, using stderr\n");
+ VG_(xml_output_sink).fd = 2; // stderr
+ VG_(xml_output_sink).is_socket = False;
+ } else {
+ VG_(xml_output_sink).fd = tmp_xml_fd;
+ VG_(fcntl)(VG_(xml_output_sink).fd, VKI_F_SETFD, VKI_FD_CLOEXEC);
+ }
} else {
// If they said --xml-fd=-1, don't print anything. Plausible for use in
// regression testing suites that use client requests to count errors.
@@ -1019,7 +1127,7 @@
/*=== Printing the preamble ===*/
/*====================================================================*/
-// Print the command, escaping any chars that require it.
+// Print the argument, escaping any chars that require it.
static void umsg_arg(const Char* arg)
{
SizeT len = VG_(strlen)(arg);
@@ -1027,29 +1135,25 @@
Int i;
for (i = 0; i < len; i++) {
if (VG_(strchr)(special, arg[i])) {
- VG_(umsg)("\\"); // escape with a backslash if necessary
+ VG_(umsg)("\\"); // escape with a backslash if necessary
}
VG_(umsg)("%c", arg[i]);
}
}
// Send output to the XML-stream and escape any XML meta-characters.
-static void xml_arg(const Char* arg) {
- VG_(printf_xml)("%t", arg);
+static void xml_arg(const Char* arg)
+{
+ VG_(printf_xml)("%pS", arg);
}
/* Ok, the logging sink is running now. Print a suitable preamble.
If logging to file or a socket, write details of parent PID and
command line args, to help people trying to interpret the
results of a run which encompasses multiple processes. */
-// TODO(timurrrr): we add a non-static declaration of this function since
-// we need it in coregrind/m_libcproc.c
-// NOTE: Keep this definition in sync with coregrind/m_libcproc.c
-// in case of merge conflict.
-// Should we move it to some header file?
-void print_preamble ( Bool logging_to_fd, const HChar* toolname );
-
-void print_preamble ( Bool logging_to_fd, const HChar* toolname )
+static void print_preamble ( Bool logging_to_fd,
+ Char* xml_fname_unexpanded,
+ const HChar* toolname )
{
Int i;
HChar* xpre = VG_(clo_xml) ? " <line>" : "";
@@ -1060,15 +1164,9 @@
void (*umsg_or_xml_arg)( const Char* )
= VG_(clo_xml) ? xml_arg : umsg_arg;
- static const char* last_toolname = NULL;
vg_assert( VG_(args_for_client) );
vg_assert( VG_(args_for_valgrind) );
-
- // This way you may pass toolname == NULL provided the first invocation
- // with toolname != NULL takes place in valgrind_main().
- toolname = (toolname == NULL ? last_toolname : toolname);
vg_assert( toolname );
- last_toolname = toolname;
if (VG_(clo_xml)) {
VG_(printf_xml)("<?xml version=\"1.0\"?>\n");
@@ -1080,7 +1178,7 @@
VG_(printf_xml)("\n");
}
- if (VG_(clo_xml) || VG_(clo_verbosity) > 0) {
+ if (VG_(clo_xml) || VG_(clo_verbosity > 0)) {
if (VG_(clo_xml))
VG_(printf_xml)("<preamble>\n");
@@ -1117,7 +1215,7 @@
// favour utility and simplicity over aesthetics.
umsg_or_xml("%sCommand: ", xpre);
if (VG_(args_the_exename))
- umsg_or_xml_arg(VG_(args_the_exename));
+ umsg_or_xml_arg(VG_(args_the_exename));
for (i = 0; i < VG_(sizeXA)( VG_(args_for_client) ); i++) {
HChar* s = *(HChar**)VG_(indexXA)( VG_(args_for_client), i );
@@ -1136,7 +1234,6 @@
}
else
if (VG_(clo_xml)) {
- Char *xml_fname_unexpanded = VG_(clo_xml_fname_unexpanded);
VG_(printf_xml)("\n");
VG_(printf_xml)("<pid>%d</pid>\n", VG_(getpid)());
VG_(printf_xml)("<ppid>%d</ppid>\n", VG_(getppid)());
@@ -1189,6 +1286,15 @@
else if (VG_(clo_verbosity) > 0)
VG_(umsg)("\n");
+# if defined(VGO_darwin) && DARWIN_VERS == DARWIN_10_8
+ /* Uh, this doesn't play nice with XML output. */
+ umsg_or_xml( "WARNING: Support on MacOS 10.8 is experimental and mostly broken.\n");
+ umsg_or_xml( "WARNING: Expect incorrect results, assertions and crashes.\n");
+ umsg_or_xml( "WARNING: In particular, Memcheck on 32-bit programs will fail to\n");
+ umsg_or_xml( "WARNING: detect any errors associated with heap-allocated data.\n");
+ umsg_or_xml( "\n" );
+# endif
+
if (VG_(clo_verbosity) > 1) {
SysRes fd;
VexArch vex_arch;
@@ -1270,10 +1376,6 @@
VG_(printf)("fd limits: host, before: cur %lu max %lu\n",
(UWord)rl.rlim_cur, (UWord)rl.rlim_max);
- /* kcc: workaround for a Linux Kernel bug */
- if (rl.rlim_cur > 1000000)
- rl.rlim_cur = 1000000;
-
/* Work out where to move the soft limit to. */
if (rl.rlim_cur + N_RESERVED_FDS <= rl.rlim_max) {
rl.rlim_cur = rl.rlim_cur + N_RESERVED_FDS;
@@ -1438,10 +1540,24 @@
Int need_help = 0; // 0 = no, 1 = --help, 2 = --help-debug
ThreadId tid_main = VG_INVALID_THREADID;
Bool logging_to_fd = False;
+ Char* xml_fname_unexpanded = NULL;
Int loglevel, i;
struct vki_rlimit zero = { 0, 0 };
XArray* addr2dihandle = NULL;
+ // For an inner Valgrind, register the interim stack asap.
+ // This is needed to allow the outer valgrind to do stacktraces during init.
+ // Note that this stack is not unregistered when the main thread
+ // is switching to the (real) stack. Unregistering this would imply
+ // to save the stack id in a global variable, and have a "if"
+ // in run_a_thread_NORETURN to do the unregistration only for the
+ // main thread. This unregistration is not worth this complexity.
+ INNER_REQUEST
+ ((void) VALGRIND_STACK_REGISTER
+ (&VG_(interim_stack).bytes[0],
+ &VG_(interim_stack).bytes[0] + sizeof(VG_(interim_stack))));
+
+
//============================================================
//
// Nb: startup is complex. Prerequisites are shown at every step.
@@ -1470,14 +1586,18 @@
//--------------------------------------------------------------
/* Start the debugging-log system ASAP. First find out how many
"-d"s were specified. This is a pre-scan of the command line. Also
- get --profile-heap=yes which is needed by the time we start up dynamic
- memory management. */
+ get --profile-heap=yes, --core-redzone-size, --redzone-size which are
+ needed by the time we start up dynamic memory management. */
loglevel = 0;
for (i = 1; i < argc; i++) {
if (argv[i][0] != '-') break;
if VG_STREQ(argv[i], "--") break;
if VG_STREQ(argv[i], "-d") loglevel++;
if VG_BOOL_CLO(argv[i], "--profile-heap", VG_(clo_profile_heap)) {}
+ if VG_BINT_CLO(argv[i], "--core-redzone-size", VG_(clo_core_redzone_size),
+ 0, MAX_CLO_REDZONE_SZB) {}
+ if VG_BINT_CLO(argv[i], "--redzone-size", VG_(clo_redzone_size),
+ 0, MAX_CLO_REDZONE_SZB) {}
}
/* ... and start the debug logger. Now we can safely emit logging
@@ -1493,7 +1613,24 @@
VG_(debugLog)(1, "main", "Checking current stack is plausible\n");
{ HChar* limLo = (HChar*)(&VG_(interim_stack).bytes[0]);
HChar* limHi = limLo + sizeof(VG_(interim_stack));
- HChar* aLocal = (HChar*)&zero; /* any auto local will do */
+ HChar* volatile
+ aLocal = (HChar*)&limLo; /* any auto local will do */
+ /* Re "volatile": Apple clang version 4.0
+ (tags/Apple/clang-421.0.57) (based on LLVM 3.1svn)" appeared
+ to miscompile the following check, causing run to abort at
+ this point (in 64-bit mode) even though aLocal is within limLo
+ .. limHi. But in fact clang is within its rights to do
+ strange things here. "The reason is that the comparisons
+ aLocal < limLo and aLocal >= limHi cause undefined behaviour
+ (according to c99 6.5.8) because they compare pointers that do
+ not point into the same aggregate." Adding "volatile" appears
+ to fix it because "The compiler would have to prove that there
+ is undefined behavior in order to exploit it. But as a
+ volatile variable can change its value in ways invisible to
+ the compiler, the compiler must make the conservative
+ assumption that it points into the same aggregate as the other
+ pointer its compared against. I.e. the behaviour is possibly
+ defined." (Analysis by Florian Krohm). */
if (aLocal < limLo || aLocal >= limHi) {
/* something's wrong. Stop. */
VG_(debugLog)(0, "main", "Root stack %p to %p, a local %p\n",
@@ -1524,8 +1661,10 @@
// p: logging, plausible-stack
//--------------------------------------------------------------
VG_(debugLog)(1, "main", "Starting the address space manager\n");
- vg_assert(VKI_PAGE_SIZE == 4096 || VKI_PAGE_SIZE == 65536);
- vg_assert(VKI_MAX_PAGE_SIZE == 4096 || VKI_MAX_PAGE_SIZE == 65536);
+ vg_assert(VKI_PAGE_SIZE == 4096 || VKI_PAGE_SIZE == 65536
+ || VKI_PAGE_SIZE == 16384);
+ vg_assert(VKI_MAX_PAGE_SIZE == 4096 || VKI_MAX_PAGE_SIZE == 65536
+ || VKI_MAX_PAGE_SIZE == 16384);
vg_assert(VKI_PAGE_SIZE <= VKI_MAX_PAGE_SIZE);
vg_assert(VKI_PAGE_SIZE == (1 << VKI_PAGE_SHIFT));
vg_assert(VKI_MAX_PAGE_SIZE == (1 << VKI_MAX_PAGE_SHIFT));
@@ -1535,7 +1674,7 @@
//--------------------------------------------------------------
// Start up the dynamic memory manager
// p: address space management
- // p: getting --profile-heap
+ // p: getting --profile-heap,--core-redzone-size,--redzone-size
// In fact m_mallocfree is self-initialising, so there's no
// initialisation call to do. Instead, try a simple malloc/
// free pair right now to check that nothing is broken.
@@ -1801,7 +1940,8 @@
VG_(debugLog)(1, "main",
"(main_) Process Valgrind's command line options, "
"setup logging\n");
- main_process_cmd_line_options ( &logging_to_fd, toolname );
+ main_process_cmd_line_options ( &logging_to_fd, &xml_fname_unexpanded,
+ toolname );
//--------------------------------------------------------------
// Zeroise the millisecond counter by doing a first read of it.
@@ -1814,10 +1954,10 @@
// p: tl_pre_clo_init [for 'VG_(details).name' and friends]
// p: main_process_cmd_line_options()
// [for VG_(clo_verbosity), VG_(clo_xml),
- // logging_to_fd]
+ // logging_to_fd, xml_fname_unexpanded]
//--------------------------------------------------------------
VG_(debugLog)(1, "main", "Print the preamble...\n");
- print_preamble(logging_to_fd, toolname);
+ print_preamble(logging_to_fd, xml_fname_unexpanded, toolname);
VG_(debugLog)(1, "main", "...finished the preamble\n");
//--------------------------------------------------------------
@@ -1869,15 +2009,17 @@
VG_(printf)("pid=%d, entering delay loop\n", VG_(getpid)());
# if defined(VGP_x86_linux)
- iters = 5;
+ iters = 10;
# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux)
iters = 10;
# elif defined(VGP_ppc32_linux)
iters = 5;
# elif defined(VGP_arm_linux)
- iters = 1;
+ iters = 5;
# elif defined(VGP_s390x_linux)
iters = 10;
+# elif defined(VGP_mips32_linux)
+ iters = 10;
# elif defined(VGO_darwin)
iters = 3;
# else
@@ -1997,6 +2139,8 @@
VG_(printf_xml)( "\n" );
}
+ VG_(init_Threads)();
+
//--------------------------------------------------------------
// Initialise the scheduler (phase 1) [generates tid_main]
// p: none, afaics
@@ -2455,6 +2599,10 @@
# if defined(VGP_ppc64_linux)
VG_(threads)[tid].arch.vex.guest_GPR2 = r2;
# endif
+ /* mips-linux note: we need to set t9 */
+# if defined(VGP_mips32_linux)
+ VG_(threads)[tid].arch.vex.guest_r25 = __libc_freeres_wrapper;
+# endif
/* Block all blockable signals by copying the real block state into
the thread's block state*/
@@ -2676,7 +2824,14 @@
call _start_in_C_linux, passing it the initial SP. */
"\tmr 3,1\n"
"\tmr 1,16\n"
- "\tbl ._start_in_C_linux\n"
+ "\tlis 14, _start_in_C_linux@highest\n"
+ "\tori 14,14,_start_in_C_linux@higher\n"
+ "\tsldi 14,14,32\n"
+ "\toris 14,14,_start_in_C_linux@h\n"
+ "\tori 14,14,_start_in_C_linux@l\n"
+ "\tld 14,0(14)\n"
+ "\tmtctr 14\n"
+ "\tbctrl\n"
"\tnop\n"
"\ttrap\n"
);
@@ -2743,6 +2898,50 @@
"\t.word "VG_STRINGIFY(VG_STACK_GUARD_SZB)"\n"
"\t.word "VG_STRINGIFY(VG_STACK_ACTIVE_SZB)"\n"
);
+#elif defined(VGP_mips32_linux)
+asm("\n"
+ "\t.type _gp_disp,@object\n"
+ ".text\n"
+ "\t.globl __start\n"
+ "\t.type __start,@function\n"
+ "__start:\n"
+
+ "\tbal 1f\n"
+ "\tnop\n"
+
+ "1:\n"
+
+ "\tlui $28, %hi(_gp_disp)\n"
+ "\taddiu $28, $28, %lo(_gp_disp)\n"
+ "\taddu $28, $28, $31\n"
+ /* t1/$9 <- Addr(interim_stack) */
+ "\tlui $9, %hi(vgPlain_interim_stack)\n"
+ /* t1/$9 <- Addr(interim_stack) */
+ "\taddiu $9, %lo(vgPlain_interim_stack)\n"
+
+
+ "\tli $10, "VG_STRINGIFY(VG_STACK_GUARD_SZB)"\n"
+ "\tli $11, "VG_STRINGIFY(VG_STACK_ACTIVE_SZB)"\n"
+
+ "\taddu $9, $9, $10\n"
+ "\taddu $9, $9, $11\n"
+ "\tli $12, 0xFFFFFFF0\n"
+ "\tand $9, $9, $12\n"
+ /* now t1/$9 = &vgPlain_interim_stack + VG_STACK_GUARD_SZB +
+ VG_STACK_ACTIVE_SZB rounded down to the nearest 16-byte
+ boundary. And $29 is the original SP. Set the SP to t1 and
+ call _start_in_C, passing it the initial SP. */
+
+ "\tmove $4, $29\n" // a0 <- $sp (_start_in_C first arg)
+ "\tmove $29, $9\n" // $sp <- t1 (new sp)
+
+ "\tlui $25, %hi(_start_in_C_linux)\n"
+ "\taddiu $25, %lo(_start_in_C_linux)\n"
+
+ "\tbal _start_in_C_linux\n"
+ "\tbreak 0x7\n"
+ ".previous\n"
+);
#else
# error "Unknown linux platform"
#endif
@@ -2755,8 +2954,12 @@
/* --- !!! --- EXTERNAL HEADERS end --- !!! --- */
/* Avoid compiler warnings: this fn _is_ used, but labelling it
- 'static' causes gcc to complain it isn't. */
+ 'static' causes gcc to complain it isn't.
+ attribute 'used' also ensures the code is not eliminated at link
+ time */
+__attribute__ ((used))
void _start_in_C_linux ( UWord* pArgc );
+__attribute__ ((used))
void _start_in_C_linux ( UWord* pArgc )
{
Int r;
@@ -2836,6 +3039,7 @@
"\tandl $~15, %eax\n"
/* install it, and collect the original one */
"\txchgl %eax, %esp\n"
+ "\tsubl $12, %esp\n" // keep stack 16 aligned; see #295428
/* call _start_in_C_darwin, passing it the startup %esp */
"\tpushl %eax\n"
"\tcall __start_in_C_darwin\n"
diff --git a/main/coregrind/m_mallocfree.c b/main/coregrind/m_mallocfree.c
index a6c794c..b7f0a4a 100644
--- a/main/coregrind/m_mallocfree.c
+++ b/main/coregrind/m_mallocfree.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -35,7 +35,6 @@
#include "pub_core_libcbase.h"
#include "pub_core_aspacemgr.h"
#include "pub_core_libcassert.h"
-#include "pub_core_libcfile.h"
#include "pub_core_libcprint.h"
#include "pub_core_mallocfree.h"
#include "pub_core_options.h"
@@ -43,9 +42,11 @@
#include "pub_core_threadstate.h" // For VG_INVALID_THREADID
#include "pub_core_transtab.h"
#include "pub_core_tooliface.h"
-#include "valgrind.h"
-//zz#include "memcheck/memcheck.h"
+#include "pub_tool_inner.h"
+#if defined(ENABLE_INNER_CLIENT_REQUEST)
+#include "memcheck/memcheck.h"
+#endif
// #define DEBUG_MALLOC // turn on heavyweight debugging machinery
// #define VERBOSE_MALLOC // make verbose, esp. in debugging machinery
@@ -268,6 +269,10 @@
return bszB & (~SIZE_T_0x1);
}
+// Forward definition.
+static
+void ensure_mm_init ( ArenaId aid );
+
// return either 0 or sizeof(ULong) depending on whether or not
// heap profiling is engaged
#define hp_overhead_szB() set_at_init_hp_overhead_szB
@@ -490,24 +495,44 @@
return & vg_arena[arena];
}
-// Initialise an arena. rz_szB is the minimum redzone size; it might be
-// made bigger to ensure that VG_MIN_MALLOC_SZB is observed.
+SizeT VG_(malloc_effective_client_redzone_size)(void)
+{
+ vg_assert(VG_(needs).malloc_replacement);
+ ensure_mm_init (VG_AR_CLIENT);
+ /* ensure_mm_init will call arena_init if not yet done.
+ This then ensures that the arena redzone size is properly
+ initialised. */
+ return arenaId_to_ArenaP(VG_AR_CLIENT)->rz_szB;
+}
+
+// Initialise an arena. rz_szB is the (default) minimum redzone size;
+// It might be overriden by VG_(clo_redzone_size) or VG_(clo_core_redzone_size).
+// it might be made bigger to ensure that VG_MIN_MALLOC_SZB is observed.
static
void arena_init ( ArenaId aid, Char* name, SizeT rz_szB,
SizeT min_sblock_szB, SizeT min_unsplittable_sblock_szB )
{
SizeT i;
Arena* a = arenaId_to_ArenaP(aid);
+
+ // Ensure default redzones are a reasonable size.
+ vg_assert(rz_szB <= MAX_REDZONE_SZB);
- // Ensure redzones are a reasonable size. They must always be at least
- // the size of a pointer, for holding the prev/next pointer (see the layout
- // details at the top of this file).
- vg_assert(rz_szB < 128);
+ /* Override the default redzone size if a clo value was given.
+ Note that the clo value can be significantly bigger than MAX_REDZONE_SZB
+ to allow the user to chase horrible bugs using up to 1 page
+ of protection. */
+ if (VG_AR_CLIENT == aid) {
+ if (VG_(clo_redzone_size) != -1)
+ rz_szB = VG_(clo_redzone_size);
+ } else {
+ if (VG_(clo_core_redzone_size) != rz_szB)
+ rz_szB = VG_(clo_core_redzone_size);
+ }
+
+ // Redzones must always be at least the size of a pointer, for holding the
+ // prev/next pointer (see the layout details at the top of this file).
if (rz_szB < sizeof(void*)) rz_szB = sizeof(void*);
-
- vg_assert((min_sblock_szB % VKI_PAGE_SIZE) == 0);
- a->name = name;
- a->clientmem = ( VG_AR_CLIENT == aid ? True : False );
// The size of the low and high admin sections in a block must be a
// multiple of VG_MIN_MALLOC_SZB. So we round up the asked-for
@@ -516,6 +541,13 @@
while (0 != overhead_szB_lo(a) % VG_MIN_MALLOC_SZB) a->rz_szB++;
vg_assert(overhead_szB_lo(a) - hp_overhead_szB() == overhead_szB_hi(a));
+ // Here we have established the effective redzone size.
+
+
+ vg_assert((min_sblock_szB % VKI_PAGE_SIZE) == 0);
+ a->name = name;
+ a->clientmem = ( VG_AR_CLIENT == aid ? True : False );
+
a->min_sblock_szB = min_sblock_szB;
a->min_unsplittable_sblock_szB = min_unsplittable_sblock_szB;
for (i = 0; i < N_MALLOC_LISTS; i++) a->freelist[i] = NULL;
@@ -548,14 +580,15 @@
"%llu/%llu unsplit/split sb unmmap'd, "
"%8ld/%8ld max/curr, "
"%10llu/%10llu totalloc-blocks/bytes,"
- " %10llu searches\n",
+ " %10llu searches %lu rzB\n",
a->name,
a->stats__bytes_mmaped_max, a->stats__bytes_mmaped,
a->stats__nreclaim_unsplit, a->stats__nreclaim_split,
a->stats__bytes_on_loan_max,
a->stats__bytes_on_loan,
a->stats__tot_blocks, a->stats__tot_bytes,
- a->stats__nsearches
+ a->stats__nsearches,
+ a->rz_szB
);
}
}
@@ -614,8 +647,7 @@
// Check and set the client arena redzone size
if (VG_(needs).malloc_replacement) {
client_rz_szB = VG_(tdict).tool_client_redzone_szB;
- // 128 is no special figure, just something not too big
- if (client_rz_szB > 128) {
+ if (client_rz_szB > MAX_REDZONE_SZB) {
VG_(printf)( "\nTool error:\n"
" specified redzone size is too big (%llu)\n",
(ULong)client_rz_szB);
@@ -640,13 +672,20 @@
VG_(clo_profile_heap) ? VG_MIN_MALLOC_SZB : 0;
// Initialise the non-client arenas
// Similarly to client arena, big allocations will be unsplittable.
- arena_init ( VG_AR_CORE, "core", 4, 1048576, 1048576+1 );
- arena_init ( VG_AR_TOOL, "tool", 4, 4194304, 4194304+1 );
- arena_init ( VG_AR_DINFO, "dinfo", 4, 1048576, 1048576+1 );
- arena_init ( VG_AR_DEMANGLE, "demangle", 4, 65536, 65536+1 );
- arena_init ( VG_AR_EXECTXT, "exectxt", 4, 1048576, 1048576+1 );
- arena_init ( VG_AR_ERRORS, "errors", 4, 65536, 65536+1 );
- arena_init ( VG_AR_TTAUX, "ttaux", 4, 65536, 65536+1 );
+ arena_init ( VG_AR_CORE, "core", CORE_REDZONE_DEFAULT_SZB,
+ 1048576, 1048576+1 );
+ arena_init ( VG_AR_TOOL, "tool", CORE_REDZONE_DEFAULT_SZB,
+ 4194304, 4194304+1 );
+ arena_init ( VG_AR_DINFO, "dinfo", CORE_REDZONE_DEFAULT_SZB,
+ 1048576, 1048576+1 );
+ arena_init ( VG_AR_DEMANGLE, "demangle", CORE_REDZONE_DEFAULT_SZB,
+ 65536, 65536+1 );
+ arena_init ( VG_AR_EXECTXT, "exectxt", CORE_REDZONE_DEFAULT_SZB,
+ 1048576, 1048576+1 );
+ arena_init ( VG_AR_ERRORS, "errors", CORE_REDZONE_DEFAULT_SZB,
+ 65536, 65536+1 );
+ arena_init ( VG_AR_TTAUX, "ttaux", CORE_REDZONE_DEFAULT_SZB,
+ 65536, 65536+1 );
nonclient_inited = True;
}
@@ -710,68 +749,6 @@
return (void*)(a - (a % align) + align);
}
-// Support for memfs (tmpfs or hugetlbfs) allocation.
-// The code is tcmalloc memfs allocator does a similar thing:
-// http://code.google.com/p/google-perftools/source/browse/trunk/src/memfs_malloc.cc
-
-static int memfs_fd = -1;
-static SizeT memfs_base = 0;
-static SizeT memfs_page_size = 0;
-
-static void MemfsOpen(void) {
- if (VG_(clo_memfs_malloc_path) && memfs_fd == -1) {
- VG_(printf)("MemfsOpen: attempting to open memfs mount: %s; "
- "memfs page size=%d ", VG_(clo_memfs_malloc_path),
- VG_(clo_memfs_page_size));
- SysRes sres = VG_(open)(VG_(clo_memfs_malloc_path),
- VKI_O_RDWR | VKI_O_CREAT | VKI_O_TRUNC, 0666);
- if (!sr_isError(sres)) {
- memfs_fd = sr_Res(sres);
- tl_assert(memfs_fd >= 0);
- VG_(printf)("... ok\n");
- memfs_page_size = VG_(clo_memfs_page_size) * 1024;
- } else {
- VG_(clo_memfs_malloc_path) = NULL;
- VG_(printf)("... failed\n");
- }
- }
-}
-
-static SizeT MemfsRoundUp(SizeT size) {
- SizeT new_size = size;
- if (memfs_page_size != 0) {
- new_size = ((size + memfs_page_size - 1) / memfs_page_size)
- * memfs_page_size;
- }
- return new_size;
-}
-
-static SysRes MemfsAlloc(SizeT size) {
- VG_(printf)("MemfsAlloc: size=%ld base=%ld ", size, memfs_base);
-
- /* Make sure the file is large enough.
- Not needed for hugetlbfs, but needed for tmpfs and regular files. */
- VG_(ftruncate)(memfs_fd, memfs_base + size);
-
- SysRes sres = VG_(am_mmap_file_float_valgrind_flags)
- (size, VKI_PROT_WRITE|VKI_PROT_READ, VKI_MAP_SHARED, memfs_fd, memfs_base);
-
- memfs_base += size;
-
- // try to access mem to fail early if something is wrong.
- char *mem = (char*)sr_Res(sres);
- mem[0] = 0;
- mem[size / 2] = 0;
- mem[size - 1] = 0;
-
- if (sr_isError(sres)) {
- VG_(printf)("... failed\n");
- } else {
- VG_(printf)("... ok; res=%p\n", (void*)sr_Res(sres));
- }
- return sres;
-}
-
// Forward definition.
static
void deferred_reclaimSuperblock ( Arena* a, Superblock* sb);
@@ -800,28 +777,21 @@
if (cszB < a->min_sblock_szB) cszB = a->min_sblock_szB;
cszB = VG_PGROUNDUP(cszB);
-
+
if (cszB >= a->min_unsplittable_sblock_szB)
unsplittable = True;
else
unsplittable = False;
- MemfsOpen();
- cszB = MemfsRoundUp(cszB);
-
if (a->clientmem) {
// client allocation -- return 0 to client if it fails
- if (memfs_fd >= 0) {
- sres = MemfsAlloc(cszB);
- } else {
- if (unsplittable)
- sres = VG_(am_mmap_anon_float_client)
- ( cszB, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC );
- else
- sres = VG_(am_sbrk_anon_float_client)
- ( cszB, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC );
- }
+ if (unsplittable)
+ sres = VG_(am_mmap_anon_float_client)
+ ( cszB, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC );
+ else
+ sres = VG_(am_sbrk_anon_float_client)
+ ( cszB, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC );
if (sr_isError(sres))
return 0;
sb = (Superblock*)(AddrH)sr_Res(sres);
@@ -833,14 +803,10 @@
);
} else {
// non-client allocation -- abort if it fails
- if (memfs_fd >= 0) {
- sres = MemfsAlloc(cszB);
- } else {
- if (unsplittable)
- sres = VG_(am_mmap_anon_float_valgrind)( cszB );
- else
- sres = VG_(am_sbrk_anon_float_valgrind)( cszB );
- }
+ if (unsplittable)
+ sres = VG_(am_mmap_anon_float_valgrind)( cszB );
+ else
+ sres = VG_(am_sbrk_anon_float_valgrind)( cszB );
if (sr_isError(sres)) {
VG_(out_of_memory_NORETURN)("newSuperblock", cszB);
/* NOTREACHED */
@@ -850,7 +816,7 @@
}
}
vg_assert(NULL != sb);
- //zzVALGRIND_MAKE_MEM_UNDEFINED(sb, cszB);
+ INNER_REQUEST(VALGRIND_MAKE_MEM_UNDEFINED(sb, cszB));
vg_assert(0 == (Addr)sb % VG_MIN_MALLOC_SZB);
sb->n_payload_bytes = cszB - sizeof(Superblock);
sb->unsplittable = (unsplittable ? sb : NULL);
@@ -1116,6 +1082,12 @@
// The lo and hi size fields will be checked (indirectly) by the call
// to get_rz_hi_byte().
if (!a->clientmem && is_inuse_block(b)) {
+ // In the inner, for memcheck sake, temporarily mark redzone accessible.
+ INNER_REQUEST(VALGRIND_MAKE_MEM_DEFINED
+ (b + hp_overhead_szB() + sizeof(SizeT), a->rz_szB));
+ INNER_REQUEST(VALGRIND_MAKE_MEM_DEFINED
+ (b + get_bszB(b)
+ - sizeof(SizeT) - a->rz_szB, a->rz_szB));
for (i = 0; i < a->rz_szB; i++) {
if (get_rz_lo_byte(b, i) !=
(UByte)(((Addr)b&0xff) ^ REDZONE_LO_MASK))
@@ -1124,6 +1096,11 @@
(UByte)(((Addr)b&0xff) ^ REDZONE_HI_MASK))
{BLEAT("redzone-hi");return False;}
}
+ INNER_REQUEST(VALGRIND_MAKE_MEM_NOACCESS
+ (b + hp_overhead_szB() + sizeof(SizeT), a->rz_szB));
+ INNER_REQUEST(VALGRIND_MAKE_MEM_NOACCESS
+ (b + get_bszB(b)
+ - sizeof(SizeT) - a->rz_szB, a->rz_szB));
}
return True;
# undef BLEAT
@@ -1318,10 +1295,11 @@
VG_(printf)(
"-------- Arena \"%s\": %lu/%lu max/curr mmap'd, "
"%llu/%llu unsplit/split sb unmmap'd, "
- "%lu/%lu max/curr on_loan --------\n",
+ "%lu/%lu max/curr on_loan %lu rzB --------\n",
a->name, a->stats__bytes_mmaped_max, a->stats__bytes_mmaped,
a->stats__nreclaim_unsplit, a->stats__nreclaim_split,
- a->stats__bytes_on_loan_max, a->stats__bytes_on_loan
+ a->stats__bytes_on_loan_max, a->stats__bytes_on_loan,
+ a->rz_szB
);
for (j = 0; j < a->sblocks_used; ++j) {
@@ -1412,7 +1390,7 @@
{
SizeT pszB = bszB_to_pszB(a, bszB);
vg_assert(b_lno == pszB_to_listNo(pszB));
- //zzVALGRIND_MAKE_MEM_UNDEFINED(b, bszB);
+ INNER_REQUEST(VALGRIND_MAKE_MEM_UNDEFINED(b, bszB));
// Set the size fields and indicate not-in-use.
set_bszB(b, mk_free_bszB(bszB));
@@ -1441,7 +1419,7 @@
{
UInt i;
vg_assert(bszB >= min_useful_bszB(a));
- //zzVALGRIND_MAKE_MEM_UNDEFINED(b, bszB);
+ INNER_REQUEST(VALGRIND_MAKE_MEM_UNDEFINED(b, bszB));
set_bszB(b, mk_inuse_bszB(bszB));
set_prev_b(b, NULL); // Take off freelist
set_next_b(b, NULL); // ditto
@@ -1668,7 +1646,26 @@
v = get_block_payload(a, b);
vg_assert( (((Addr)v) & (VG_MIN_MALLOC_SZB-1)) == 0 );
- /* VALGRIND_MALLOCLIKE_BLOCK(v, req_pszB, 0, False); */
+ // Which size should we pass to VALGRIND_MALLOCLIKE_BLOCK ?
+ // We have 2 possible options:
+ // 1. The final resulting usable size.
+ // 2. The initial (non-aligned) req_pszB.
+ // Memcheck implements option 2 easily, as the initial requested size
+ // is maintained in the mc_chunk data structure.
+ // This is not as easy in the core, as there is no such structure.
+ // (note: using the aligned req_pszB is not simpler than 2, as
+ // requesting an aligned req_pszB might still be satisfied by returning
+ // a (slightly) bigger block than requested if the remaining part of
+ // of a free block is not big enough to make a free block by itself).
+ // Implement Sol 2 can be done the following way:
+ // After having called VALGRIND_MALLOCLIKE_BLOCK, the non accessible
+ // redzone just after the block can be used to determine the
+ // initial requested size.
+ // Currently, not implemented => we use Option 1.
+ INNER_REQUEST
+ (VALGRIND_MALLOCLIKE_BLOCK(v,
+ VG_(arena_malloc_usable_size)(aid, v),
+ a->rz_szB, False));
/* For debugging/testing purposes, fill the newly allocated area
with a definite value in an attempt to shake out any
@@ -1862,6 +1859,31 @@
deferred_reclaimSuperblock (a, sb);
}
+ // Inform that ptr has been released. We give redzone size
+ // 0 instead of a->rz_szB as proper accessibility is done just after.
+ INNER_REQUEST(VALGRIND_FREELIKE_BLOCK(ptr, 0));
+
+ // We need to (re-)establish the minimum accessibility needed
+ // for free list management. E.g. if block ptr has been put in a free
+ // list and a neighbour block is released afterwards, the
+ // "lo" and "hi" portions of the block ptr will be accessed to
+ // glue the 2 blocks together.
+ // We could mark the whole block as not accessible, and each time
+ // transiently mark accessible the needed lo/hi parts. Not done as this
+ // is quite complex, for very little expected additional bug detection.
+ // fully unaccessible. Note that the below marks the (possibly) merged
+ // block, not the block corresponding to the ptr argument.
+
+ // First mark the whole block unaccessible.
+ INNER_REQUEST(VALGRIND_MAKE_MEM_NOACCESS(b, b_bszB));
+ // Then mark the relevant administrative headers as defined.
+ // No need to mark the heap profile portion as defined, this is not
+ // used for free blocks.
+ INNER_REQUEST(VALGRIND_MAKE_MEM_DEFINED(b + hp_overhead_szB(),
+ sizeof(SizeT) + sizeof(void*)));
+ INNER_REQUEST(VALGRIND_MAKE_MEM_DEFINED(b + b_bszB
+ - sizeof(SizeT) - sizeof(void*),
+ sizeof(SizeT) + sizeof(void*)));
} else {
// b must be first block (i.e. no unused bytes at the beginning)
vg_assert((Block*)sb_start == b);
@@ -1870,6 +1892,12 @@
other_b = b + b_bszB;
vg_assert(other_b-1 == (Block*)sb_end);
+ // Inform that ptr has been released. Redzone size value
+ // is not relevant (so we give 0 instead of a->rz_szB)
+ // as it is expected that the aspacemgr munmap will be used by
+ // outer to mark the whole superblock as unaccessible.
+ INNER_REQUEST(VALGRIND_FREELIKE_BLOCK(ptr, 0));
+
// Reclaim immediately the unsplittable superblock sb.
reclaimSuperblock (a, sb);
}
@@ -1878,7 +1906,6 @@
sanity_check_malloc_arena(aid);
# endif
- //zzVALGRIND_FREELIKE_BLOCK(ptr, 0);
}
@@ -1932,10 +1959,11 @@
// this allocation; it isn't optional.
vg_assert(cc);
+ // Check that the requested alignment has a plausible size.
// Check that the requested alignment seems reasonable; that is, is
// a power of 2.
if (req_alignB < VG_MIN_MALLOC_SZB
- || req_alignB > 1048576
+ || req_alignB > 16 * 1024 * 1024
|| VG_(log2)( req_alignB ) == -1 /* not a power of 2 */) {
VG_(printf)("VG_(arena_memalign)(%p, %lu, %lu)\n"
"bad alignment value %lu\n"
@@ -1971,6 +1999,11 @@
/* Give up if we couldn't allocate enough space */
if (base_p == 0)
return 0;
+ /* base_p was marked as allocated by VALGRIND_MALLOCLIKE_BLOCK
+ inside VG_(arena_malloc). We need to indicate it is free, then
+ we need to mark it undefined to allow the below code to access is. */
+ INNER_REQUEST(VALGRIND_FREELIKE_BLOCK(base_p, a->rz_szB));
+ INNER_REQUEST(VALGRIND_MAKE_MEM_UNDEFINED(base_p, base_pszB_req));
/* Block ptr for the block we are going to split. */
base_b = get_payload_block ( a, base_p );
@@ -2023,7 +2056,8 @@
vg_assert( (((Addr)align_p) % req_alignB) == 0 );
- //zzVALGRIND_MALLOCLIKE_BLOCK(align_p, req_pszB, 0, False);
+ INNER_REQUEST(VALGRIND_MALLOCLIKE_BLOCK(align_p,
+ req_pszB, a->rz_szB, False));
return align_p;
}
@@ -2115,8 +2149,6 @@
VG_(memset)(p, 0, size);
- //zzVALGRIND_MALLOCLIKE_BLOCK(p, size, 0, True);
-
return p;
}
diff --git a/main/coregrind/m_options.c b/main/coregrind/m_options.c
index 3cd806b..a1de249 100644
--- a/main/coregrind/m_options.c
+++ b/main/coregrind/m_options.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -47,7 +47,11 @@
Bool VG_(clo_error_limit) = True;
Int VG_(clo_error_exitcode) = 0;
+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
+VgVgdb VG_(clo_vgdb) = Vg_VgdbNo; // currently disabled on Android
+#else
VgVgdb VG_(clo_vgdb) = Vg_VgdbYes;
+#endif
Int VG_(clo_vgdb_poll) = 5000;
Int VG_(clo_vgdb_error) = 999999999;
HChar* VG_(clo_vgdb_prefix) = NULL;
@@ -62,6 +66,7 @@
Bool VG_(clo_xml) = False;
HChar* VG_(clo_xml_user_comment) = NULL;
Bool VG_(clo_demangle) = True;
+HChar* VG_(clo_soname_synonyms) = NULL;
Bool VG_(clo_trace_children) = False;
HChar* VG_(clo_trace_children_skip) = NULL;
HChar* VG_(clo_trace_children_skip_by_arg) = NULL;
@@ -76,7 +81,8 @@
Char* VG_(clo_fullpath_after)[VG_CLO_MAX_FULLPATH_AFTER];
UChar VG_(clo_trace_flags) = 0; // 00000000b
UChar VG_(clo_profile_flags) = 0; // 00000000b
-Int VG_(clo_trace_notbelow) = 999999999;
+Int VG_(clo_trace_notbelow) = -1; // unspecified
+Int VG_(clo_trace_notabove) = -1; // unspecified
Bool VG_(clo_trace_syscalls) = False;
Bool VG_(clo_trace_signals) = False;
Bool VG_(clo_trace_symtab) = False;
@@ -86,8 +92,14 @@
Bool VG_(clo_debug_dump_line) = False;
Bool VG_(clo_debug_dump_frames) = False;
Bool VG_(clo_trace_redir) = False;
+enum FairSchedType
+ VG_(clo_fair_sched) = disable_fair_sched;
Bool VG_(clo_trace_sched) = False;
Bool VG_(clo_profile_heap) = False;
+Int VG_(clo_core_redzone_size) = CORE_REDZONE_DEFAULT_SZB;
+// A value != -1 overrides the tool-specific value
+// VG_(needs_malloc_replacement).tool_client_redzone_szB
+Int VG_(clo_redzone_size) = -1;
Int VG_(clo_dump_error) = 0;
Int VG_(clo_backtrace_size) = 12;
Char* VG_(clo_sim_hints) = NULL;
@@ -106,9 +118,6 @@
VgSmc VG_(clo_smc_check) = Vg_SmcStack;
HChar* VG_(clo_kernel_variant) = NULL;
Bool VG_(clo_dsymutil) = False;
-Char* VG_(clo_nacl_file) = NULL;
-Char* VG_(clo_memfs_malloc_path) = NULL;
-Int VG_(clo_memfs_page_size) = 2048; /* 2M */
/*====================================================================*/
diff --git a/main/coregrind/m_oset.c b/main/coregrind/m_oset.c
index ea09b52..acb724e 100644
--- a/main/coregrind/m_oset.c
+++ b/main/coregrind/m_oset.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -80,6 +80,7 @@
#include "pub_core_libcassert.h"
#include "pub_core_libcprint.h"
#include "pub_core_oset.h"
+#include "pub_tool_poolalloc.h"
/*--------------------------------------------------------------------*/
/*--- Types and constants ---*/
@@ -114,6 +115,8 @@
OSetAlloc_t alloc; // allocator
HChar* cc; // cc for allocator
OSetFree_t free; // deallocator
+ PoolAlloc* node_pa; // (optional) pool allocator for nodes.
+ SizeT maxEltSize; // for node_pa, must be > 0. Otherwise unused.
Word nElems; // number of elements in the tree
AvlNode* root; // root node
@@ -302,6 +305,57 @@
t->alloc = _alloc;
t->cc = _cc;
t->free = _free;
+ t->node_pa = NULL;
+ t->maxEltSize = 0; // Just in case it would be wrongly used.
+ t->nElems = 0;
+ t->root = NULL;
+ stackClear(t);
+
+ return t;
+}
+
+AvlTree* VG_(OSetGen_Create_With_Pool)(PtrdiffT _keyOff, OSetCmp_t _cmp,
+ OSetAlloc_t _alloc, HChar* _cc,
+ OSetFree_t _free,
+ SizeT _poolSize,
+ SizeT _maxEltSize)
+{
+ AvlTree* t;
+
+ t = VG_(OSetGen_Create) (_keyOff, _cmp,
+ _alloc, _cc,
+ _free);
+
+ vg_assert (_poolSize > 0);
+ vg_assert (_maxEltSize > 0);
+ t->maxEltSize = _maxEltSize;
+ t->node_pa = VG_(newPA)(sizeof(AvlNode)
+ + VG_ROUNDUP(_maxEltSize, sizeof(void*)),
+ _poolSize,
+ t->alloc,
+ _cc,
+ t->free);
+ VG_(addRefPA) (t->node_pa);
+
+ return t;
+}
+
+AvlTree* VG_(OSetGen_EmptyClone) (AvlTree* os)
+{
+ AvlTree* t;
+
+ vg_assert(os);
+
+ t = os->alloc(os->cc, sizeof(AvlTree));
+ t->keyOff = os->keyOff;
+ t->cmp = os->cmp;
+ t->alloc = os->alloc;
+ t->cc = os->cc;
+ t->free = os->free;
+ t->node_pa = os->node_pa;
+ if (t->node_pa)
+ VG_(addRefPA) (t->node_pa);
+ t->maxEltSize = os->maxEltSize;
t->nElems = 0;
t->root = NULL;
stackClear(t);
@@ -318,34 +372,48 @@
// Destructor, frees up all memory held by remaining nodes.
void VG_(OSetGen_Destroy)(AvlTree* t)
{
- AvlNode* n = NULL;
- Int i = 0;
- Word sz = 0;
-
+ Bool has_node_pa;
vg_assert(t);
- stackClear(t);
- if (t->root)
- stackPush(t, t->root, 1);
- /* Free all the AvlNodes. This is a post-order traversal, because we */
- /* must free all children of a node before the node itself. */
- while (stackPop(t, &n, &i)) {
- switch (i) {
- case 1:
- stackPush(t, n, 2);
- if (n->left) stackPush(t, n->left, 1);
- break;
- case 2:
- stackPush(t, n, 3);
- if (n->right) stackPush(t, n->right, 1);
- break;
- case 3:
- t->free(n);
- sz++;
- break;
+ has_node_pa = t->node_pa != NULL;
+
+ /*
+ * If we are the only remaining user of this pool allocator, release all
+ * the elements by deleting the pool allocator. That's more efficient than
+ * deleting tree nodes one by one.
+ */
+ if (!has_node_pa || VG_(releasePA)(t->node_pa) > 0) {
+ AvlNode* n = NULL;
+ Int i = 0;
+ Word sz = 0;
+
+ stackClear(t);
+ if (t->root)
+ stackPush(t, t->root, 1);
+
+ /* Free all the AvlNodes. This is a post-order traversal, because we */
+ /* must free all children of a node before the node itself. */
+ while (stackPop(t, &n, &i)) {
+ switch (i) {
+ case 1:
+ stackPush(t, n, 2);
+ if (n->left) stackPush(t, n->left, 1);
+ break;
+ case 2:
+ stackPush(t, n, 3);
+ if (n->right) stackPush(t, n->right, 1);
+ break;
+ case 3:
+ if (has_node_pa)
+ VG_(freeEltPA) (t->node_pa, n);
+ else
+ t->free(n);
+ sz++;
+ break;
+ }
}
+ vg_assert(sz == t->nElems);
}
- vg_assert(sz == t->nElems);
/* Free the AvlTree itself. */
t->free(t);
@@ -359,9 +427,15 @@
// Allocate and initialise a new node.
void* VG_(OSetGen_AllocNode)(AvlTree* t, SizeT elemSize)
{
+ AvlNode* n;
Int nodeSize = sizeof(AvlNode) + elemSize;
- AvlNode* n = t->alloc( t->cc, nodeSize );
vg_assert(elemSize > 0);
+ if (t->node_pa) {
+ vg_assert(elemSize <= t->maxEltSize);
+ n = VG_(allocEltPA) (t->node_pa);
+ } else {
+ n = t->alloc( t->cc, nodeSize );
+ }
VG_(memset)(n, 0, nodeSize);
n->magic = OSET_MAGIC;
return elem_of_node(n);
@@ -369,7 +443,10 @@
void VG_(OSetGen_FreeNode)(AvlTree* t, void* e)
{
- t->free( node_of_elem(e) );
+ if (t->node_pa)
+ VG_(freeEltPA) (t->node_pa, node_of_elem (e));
+ else
+ t->free( node_of_elem(e) );
}
/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_poolalloc.c b/main/coregrind/m_poolalloc.c
new file mode 100644
index 0000000..a236a0b
--- /dev/null
+++ b/main/coregrind/m_poolalloc.c
@@ -0,0 +1,149 @@
+/*------------------------------------------------------------------------*/
+/*--- A simple pool (memory) allocator implementation. m_poolalloc.c --- */
+/*------------------------------------------------------------------------*/
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2011-2012 OpenWorks LLP info@open-works.co.uk,
+ Philippe Waroquiers philippe.waroquiers@skynet.be
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "pub_core_basics.h"
+#include "pub_core_libcbase.h"
+#include "pub_core_libcassert.h"
+#include "pub_tool_xarray.h"
+#include "pub_tool_poolalloc.h" /* self */
+
+struct _PoolAlloc {
+ UWord nrRef; /* nr reference to this pool allocator */
+ UWord elemSzB; /* element size */
+ UWord nPerPool; /* # elems per pool */
+ void* (*alloc)(HChar*, SizeT); /* pool allocator */
+ HChar* cc; /* pool allocator's cc */
+ void (*free)(void*); /* pool allocator's free-er */
+ /* XArray of void* (pointers to pools). The pools themselves.
+ Each element is a pointer to a block of size (elemSzB *
+ nPerPool) bytes. */
+ XArray* pools;
+ /* next free element. Is a pointer to an element in one of the
+ pools pointed to by .pools */
+ void* nextFree;
+};
+
+PoolAlloc* VG_(newPA) ( UWord elemSzB,
+ UWord nPerPool,
+ void* (*alloc)(HChar*, SizeT),
+ HChar* cc,
+ void (*free_fn)(void*) )
+{
+ PoolAlloc* pa;
+ vg_assert(0 == (elemSzB % sizeof(UWord)));
+ vg_assert(elemSzB >= sizeof(UWord));
+ vg_assert(nPerPool >= 100); /* let's say */
+ vg_assert(alloc);
+ vg_assert(cc);
+ vg_assert(free_fn);
+ pa = alloc(cc, sizeof(*pa));
+ vg_assert(pa);
+ VG_(memset)(pa, 0, sizeof(*pa));
+ pa->nrRef = 0;
+ pa->elemSzB = elemSzB;
+ pa->nPerPool = nPerPool;
+ pa->pools = NULL;
+ pa->alloc = alloc;
+ pa->cc = cc;
+ pa->free = free_fn;
+ pa->pools = VG_(newXA)( alloc, cc, free_fn, sizeof(void*) );
+ pa->nextFree = NULL;
+ vg_assert(pa->pools);
+ return pa;
+}
+
+void VG_(deletePA) ( PoolAlloc* pa)
+{
+ Word i;
+ vg_assert(pa->nrRef == 0);
+ for (i = 0; i < VG_(sizeXA) (pa->pools); i++)
+ pa->free (*(UWord **)VG_(indexXA) ( pa->pools, i ));
+ VG_(deleteXA) (pa->pools);
+ pa->free (pa);
+}
+
+/* The freelist is empty. Allocate a new pool and put all the new
+ elements in it onto the freelist. */
+__attribute__((noinline))
+static void pal_add_new_pool ( PoolAlloc* pa )
+{
+ Word i;
+ UWord* pool;
+ vg_assert(pa);
+ vg_assert(pa->nextFree == NULL);
+ pool = pa->alloc( pa->cc, pa->elemSzB * pa->nPerPool );
+ vg_assert(pool);
+ /* extend the freelist through the new pool. Place the freelist
+ pointer in the first word of each element. That's why the
+ element size must be at least one word. */
+ for (i = pa->nPerPool-1; i >= 0; i--) {
+ UChar* elemC = ((UChar*)pool) + i * pa->elemSzB;
+ UWord* elem = (UWord*)elemC;
+ vg_assert(0 == (((UWord)elem) % sizeof(UWord)));
+ *elem = (UWord)pa->nextFree;
+ pa->nextFree = elem;
+ }
+ /* and add to our collection of pools */
+ VG_(addToXA)( pa->pools, &pool );
+}
+
+void* VG_(allocEltPA) ( PoolAlloc* pa)
+{
+ UWord* elem;
+ if (UNLIKELY(pa->nextFree == NULL)) {
+ pal_add_new_pool(pa);
+ }
+ elem = pa->nextFree;
+ pa->nextFree = (void*)*elem;
+ *elem = 0; /* unnecessary, but just to be on the safe side */
+ return elem;
+}
+
+void VG_(freeEltPA) ( PoolAlloc* pa, void* p)
+{
+ UWord* elem = (UWord*)p;
+ *elem = (UWord)pa->nextFree;
+ pa->nextFree = elem;
+}
+
+
+void VG_(addRefPA) ( PoolAlloc* pa)
+{
+ pa->nrRef++;
+}
+
+UWord VG_(releasePA)(PoolAlloc* pa)
+{
+ UWord nrRef;
+
+ vg_assert(pa->nrRef > 0);
+ nrRef = --pa->nrRef;
+ if (nrRef == 0)
+ VG_(deletePA)(pa);
+ return nrRef;
+}
diff --git a/main/coregrind/m_redir.c b/main/coregrind/m_redir.c
index ab3ad29..43df9d2 100644
--- a/main/coregrind/m_redir.c
+++ b/main/coregrind/m_redir.c
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
- Copyright (C) 2003-2011 Jeremy Fitzhardinge
+ Copyright (C) 2003-2012 Jeremy Fitzhardinge
jeremy@goop.org
This program is free software; you can redistribute it and/or
@@ -36,6 +36,8 @@
#include "pub_core_libcbase.h"
#include "pub_core_libcassert.h"
#include "pub_core_libcprint.h"
+#include "pub_core_vki.h"
+#include "pub_core_libcfile.h"
#include "pub_core_seqmatch.h"
#include "pub_core_mallocfree.h"
#include "pub_core_options.h"
@@ -49,6 +51,7 @@
#include "pub_core_xarray.h"
#include "pub_core_clientstate.h" // VG_(client___libc_freeres_wrapper)
#include "pub_core_demangle.h" // VG_(maybe_Z_demangle)
+#include "pub_core_libcproc.h" // VG_(libdir)
#include "config.h" /* GLIBC_2_* */
@@ -364,6 +367,18 @@
dinfo_free(names);
}
+static HChar const* advance_to_equal ( HChar const* c ) {
+ while (*c && *c != '=') {
+ ++c;
+ }
+ return c;
+}
+static HChar const* advance_to_comma ( HChar const* c ) {
+ while (*c && *c != ',') {
+ ++c;
+ }
+ return c;
+}
/* Notify m_redir of the arrival of a new DebugInfo. This is fairly
complex, but the net effect is to (1) add a new entry to the
@@ -397,6 +412,82 @@
newdi_soname = VG_(DebugInfo_get_soname)(newdi);
vg_assert(newdi_soname != NULL);
+#ifdef ENABLE_INNER
+ {
+ /* When an outer Valgrind is executing an inner Valgrind, the
+ inner "sees" in its address space the mmap-ed vgpreload files
+ of the outer. The inner must avoid interpreting the
+ redirections given in the outer vgpreload mmap-ed files.
+ Otherwise, some tool combinations badly fail.
+
+ Example: outer memcheck tool executing an inner none tool.
+
+ If inner none interprets the outer malloc redirection, the
+ inner will redirect malloc to a memcheck function it does not
+ have (as the redirection target is from the outer). With
+ such a failed redirection, a call to malloc inside the inner
+ will then result in a "no-operation" (and so no memory will
+ be allocated).
+
+ When running as an inner, no redirection will be done
+ for a vgpreload file if this file is not located in the
+ inner VALGRIND_LIB directory.
+
+ Recognising a vgpreload file based on a filename pattern
+ is a kludge. An alternate solution would be to change
+ the _vgr prefix according to outer/inner/client.
+ */
+ const UChar* newdi_filename = VG_(DebugInfo_get_filename)(newdi);
+ const UChar* newdi_basename = VG_(basename) (newdi_filename);
+ if (VG_(strncmp) (newdi_basename, "vgpreload_", 10) == 0) {
+ /* This looks like a vgpreload file => check if this file
+ is from the inner VALGRIND_LIB.
+ We do this check using VG_(stat) + dev/inode comparison
+ as vg-in-place defines a VALGRIND_LIB with symlinks
+ pointing to files inside the valgrind build directories. */
+ struct vg_stat newdi_stat;
+ SysRes newdi_res;
+ Char in_vglib_filename[VKI_PATH_MAX];
+ struct vg_stat in_vglib_stat;
+ SysRes in_vglib_res;
+
+ newdi_res = VG_(stat)(newdi_filename, &newdi_stat);
+
+ VG_(strncpy) (in_vglib_filename, VG_(libdir), VKI_PATH_MAX);
+ VG_(strncat) (in_vglib_filename, "/", VKI_PATH_MAX);
+ VG_(strncat) (in_vglib_filename, newdi_basename, VKI_PATH_MAX);
+ in_vglib_res = VG_(stat)(in_vglib_filename, &in_vglib_stat);
+
+ /* If we find newdi_basename in inner VALGRIND_LIB
+ but newdi_filename is not the same file, then we do
+ not execute the redirection. */
+ if (!sr_isError(in_vglib_res)
+ && !sr_isError(newdi_res)
+ && (newdi_stat.dev != in_vglib_stat.dev
+ || newdi_stat.ino != in_vglib_stat.ino)) {
+ /* <inner VALGRIND_LIB>/newdi_basename is an existing file
+ and is different of newdi_filename.
+ So, we do not execute newdi_filename redirection. */
+ if ( VG_(clo_verbosity) > 1 ) {
+ VG_(message)( Vg_DebugMsg,
+ "Skipping vgpreload redir in %s"
+ " (not from VALGRIND_LIB_INNER)\n",
+ newdi_filename);
+ }
+ return;
+ } else {
+ if ( VG_(clo_verbosity) > 1 ) {
+ VG_(message)( Vg_DebugMsg,
+ "Executing vgpreload redir in %s"
+ " (from VALGRIND_LIB_INNER)\n",
+ newdi_filename);
+ }
+ }
+ }
+ }
+#endif
+
+
/* stay sane: we don't already have this. */
for (ts = topSpecs; ts; ts = ts->next)
vg_assert(ts->seginfo != newdi);
@@ -437,6 +528,48 @@
the following loop, and complain at that point. */
continue;
}
+
+ if (0 == VG_(strncmp) (demangled_sopatt,
+ VG_SO_SYN_PREFIX, VG_SO_SYN_PREFIX_LEN)) {
+ /* This is a redirection for handling lib so synonyms. If we
+ have a matching lib synonym, then replace the sopatt.
+ Otherwise, just ignore this redirection spec. */
+
+ if (!VG_(clo_soname_synonyms))
+ continue; // No synonyms => skip the redir.
+
+ /* Search for a matching synonym=newname*/
+ SizeT const sopatt_syn_len
+ = VG_(strlen)(demangled_sopatt+VG_SO_SYN_PREFIX_LEN);
+ HChar const* last = VG_(clo_soname_synonyms);
+
+ while (*last) {
+ HChar const* first = last;
+ last = advance_to_equal(first);
+
+ if ((last - first) == sopatt_syn_len
+ && 0 == VG_(strncmp)(demangled_sopatt+VG_SO_SYN_PREFIX_LEN,
+ first,
+ sopatt_syn_len)) {
+ // Found the demangle_sopatt synonym => replace it
+ first = last + 1;
+ last = advance_to_comma(first);
+ VG_(strncpy)(demangled_sopatt, first, last - first);
+ demangled_sopatt[last - first] = '\0';
+ break;
+ }
+
+ last = advance_to_comma(last);
+ if (*last == ',')
+ last++;
+ }
+
+ // If we have not replaced the sopatt, then skip the redir.
+ if (0 == VG_(strncmp) (demangled_sopatt,
+ VG_SO_SYN_PREFIX, VG_SO_SYN_PREFIX_LEN))
+ continue;
+ }
+
spec = dinfo_zalloc("redir.rnnD.1", sizeof(Spec));
vg_assert(spec);
spec->from_sopatt = dinfo_strdup("redir.rnnD.2", demangled_sopatt);
@@ -731,6 +864,7 @@
# if defined(VGP_amd64_linux)
&& act.from_addr != 0xFFFFFFFFFF600000ULL
&& act.from_addr != 0xFFFFFFFFFF600400ULL
+ && act.from_addr != 0xFFFFFFFFFF600800ULL
# endif
) {
what = "redirection from-address is in non-executable area";
@@ -1089,11 +1223,15 @@
/* Redirect vsyscalls to local versions */
add_hardwired_active(
0xFFFFFFFFFF600000ULL,
- (Addr)&VG_(amd64_linux_REDIR_FOR_vgettimeofday)
+ (Addr)&VG_(amd64_linux_REDIR_FOR_vgettimeofday)
);
- add_hardwired_active(
+ add_hardwired_active(
0xFFFFFFFFFF600400ULL,
- (Addr)&VG_(amd64_linux_REDIR_FOR_vtime)
+ (Addr)&VG_(amd64_linux_REDIR_FOR_vtime)
+ );
+ add_hardwired_active(
+ 0xFFFFFFFFFF600800ULL,
+ (Addr)&VG_(amd64_linux_REDIR_FOR_vgetcpu)
);
/* If we're using memcheck, use these intercepts right from
@@ -1220,6 +1358,17 @@
# elif defined(VGP_s390x_linux)
/* nothing so far */
+# elif defined(VGP_mips32_linux)
+ if (0==VG_(strcmp)("Memcheck", VG_(details).name)) {
+
+ /* this is mandatory - can't sanely continue without it */
+ add_hardwired_spec(
+ "ld.so.3", "strlen",
+ (Addr)&VG_(mips32_linux_REDIR_FOR_strlen),
+ complain_about_stripped_glibc_ldso
+ );
+ }
+
# else
# error Unknown platform
# endif
@@ -1463,11 +1612,15 @@
VG_(message)(Vg_DebugMsg, "<<\n");
VG_(message)(Vg_DebugMsg, " ------ REDIR STATE %s ------\n", who);
for (ts = topSpecs; ts; ts = ts->next) {
- VG_(message)(Vg_DebugMsg,
- " TOPSPECS of soname %s\n",
- ts->seginfo
- ? (HChar*)VG_(DebugInfo_get_soname)(ts->seginfo)
- : "(hardwired)" );
+ if (ts->seginfo)
+ VG_(message)(Vg_DebugMsg,
+ " TOPSPECS of soname %s filename %s\n",
+ (HChar*)VG_(DebugInfo_get_soname)(ts->seginfo),
+ (HChar*)VG_(DebugInfo_get_filename)(ts->seginfo));
+ else
+ VG_(message)(Vg_DebugMsg,
+ " TOPSPECS of soname (hardwired)\n");
+
for (sp = ts->specs; sp; sp = sp->next)
show_spec(" ", sp);
}
diff --git a/main/coregrind/m_replacemalloc/replacemalloc_core.c b/main/coregrind/m_replacemalloc/replacemalloc_core.c
index baaa3be..98de3e5 100644
--- a/main/coregrind/m_replacemalloc/replacemalloc_core.c
+++ b/main/coregrind/m_replacemalloc/replacemalloc_core.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_replacemalloc/vg_replace_malloc.c b/main/coregrind/m_replacemalloc/vg_replace_malloc.c
index c12fbe6..9173e3c 100644
--- a/main/coregrind/m_replacemalloc/vg_replace_malloc.c
+++ b/main/coregrind/m_replacemalloc/vg_replace_malloc.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -119,6 +119,9 @@
# if defined(VGPV_arm_linux_android)
__asm__ __volatile__(".word 0xFFFFFFFF");
while (1) {}
+# elif defined(VGPV_x86_linux_android)
+ __asm__ __volatile__("ud2");
+ while (1) {}
# else
extern __attribute__ ((__noreturn__)) void _exit(int status);
_exit(x);
@@ -256,15 +259,22 @@
// Each of these lines generates a replacement function:
// (from_so, from_fn, v's replacement)
+// For some lines, we will also define a replacement function
+// whose only purpose is to be a soname synonym place holder
+// that can be replaced using --soname-synonyms.
+#define SO_SYN_MALLOC VG_SO_SYN(somalloc)
// malloc
#if defined(VGO_linux)
ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, malloc, malloc);
ALLOC_or_NULL(VG_Z_LIBC_SONAME, malloc, malloc);
+ ALLOC_or_NULL(SO_SYN_MALLOC, malloc, malloc);
#elif defined(VGO_darwin)
ALLOC_or_NULL(VG_Z_LIBC_SONAME, malloc, malloc);
- ZONEALLOC_or_NULL(VG_Z_LIBC_SONAME, malloc_zone_malloc, malloc);
+ ALLOC_or_NULL(SO_SYN_MALLOC, malloc, malloc);
+ ZONEALLOC_or_NULL(VG_Z_LIBC_SONAME, malloc_zone_malloc, malloc);
+ ZONEALLOC_or_NULL(SO_SYN_MALLOC, malloc_zone_malloc, malloc);
#endif
@@ -281,54 +291,58 @@
#if VG_WORDSIZE == 4
ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znwj, __builtin_new);
ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znwj, __builtin_new);
+ ALLOC_or_BOMB(SO_SYN_MALLOC, _Znwj, __builtin_new);
#endif
// operator new(unsigned long), GNU mangling
#if VG_WORDSIZE == 8
ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znwm, __builtin_new);
ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znwm, __builtin_new);
+ ALLOC_or_BOMB(SO_SYN_MALLOC, _Znwm, __builtin_new);
#endif
#elif defined(VGO_darwin)
- // glider: hereafter we uncomment the interceptors for operator new
- // and operator delete, see https://bugs.kde.org/show_bug.cgi?id=286849
// operator new(unsigned int), GNU mangling
#if VG_WORDSIZE == 4
- ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znwj, __builtin_new);
- ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znwj, __builtin_new);
+ //ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znwj, __builtin_new);
+ //ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znwj, __builtin_new);
#endif
// operator new(unsigned long), GNU mangling
#if 1 // FIXME: is this right?
- ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znwm, __builtin_new);
- ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znwm, __builtin_new);
+ //ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znwm, __builtin_new);
+ //ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znwm, __builtin_new);
#endif
-
+
#endif
+
/*---------------------- new nothrow ----------------------*/
-// operator new(unsigned, std::nothrow_t const&), GNU mangling
#if defined(VGO_linux)
// operator new(unsigned, std::nothrow_t const&), GNU mangling
#if VG_WORDSIZE == 4
ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnwjRKSt9nothrow_t, __builtin_new);
ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnwjRKSt9nothrow_t, __builtin_new);
+ ALLOC_or_NULL(SO_SYN_MALLOC, _ZnwjRKSt9nothrow_t, __builtin_new);
#endif
// operator new(unsigned long, std::nothrow_t const&), GNU mangling
#if VG_WORDSIZE == 8
ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnwmRKSt9nothrow_t, __builtin_new);
ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnwmRKSt9nothrow_t, __builtin_new);
+ ALLOC_or_NULL(SO_SYN_MALLOC, _ZnwmRKSt9nothrow_t, __builtin_new);
#endif
+
#elif defined(VGO_darwin)
// operator new(unsigned, std::nothrow_t const&), GNU mangling
#if VG_WORDSIZE == 4
- ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnwjRKSt9nothrow_t, __builtin_new);
- ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnwjRKSt9nothrow_t, __builtin_new);
+ //ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnwjRKSt9nothrow_t, __builtin_new);
+ //ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnwjRKSt9nothrow_t, __builtin_new);
#endif
// operator new(unsigned long, std::nothrow_t const&), GNU mangling
#if 1 // FIXME: is this right?
- ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnwmRKSt9nothrow_t, __builtin_new);
- ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnwmRKSt9nothrow_t, __builtin_new);
+ //ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnwmRKSt9nothrow_t, __builtin_new);
+ //ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnwmRKSt9nothrow_t, __builtin_new);
#endif
+
#endif
@@ -342,23 +356,25 @@
#if VG_WORDSIZE == 4
ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znaj, __builtin_vec_new );
ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znaj, __builtin_vec_new );
+ ALLOC_or_BOMB(SO_SYN_MALLOC, _Znaj, __builtin_vec_new );
#endif
// operator new[](unsigned long), GNU mangling
#if VG_WORDSIZE == 8
ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znam, __builtin_vec_new );
ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znam, __builtin_vec_new );
+ ALLOC_or_BOMB(SO_SYN_MALLOC, _Znam, __builtin_vec_new );
#endif
#elif defined(VGO_darwin)
// operator new[](unsigned int), GNU mangling
#if VG_WORDSIZE == 4
- ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znaj, __builtin_vec_new );
- ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znaj, __builtin_vec_new );
+ //ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znaj, __builtin_vec_new );
+ //ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znaj, __builtin_vec_new );
#endif
// operator new[](unsigned long), GNU mangling
#if 1 // FIXME: is this right?
- ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znam, __builtin_vec_new );
- ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znam, __builtin_vec_new );
+ //ALLOC_or_BOMB(VG_Z_LIBSTDCXX_SONAME, _Znam, __builtin_vec_new );
+ //ALLOC_or_BOMB(VG_Z_LIBC_SONAME, _Znam, __builtin_vec_new );
#endif
#endif
@@ -371,22 +387,25 @@
#if VG_WORDSIZE == 4
ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnajRKSt9nothrow_t, __builtin_vec_new );
ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnajRKSt9nothrow_t, __builtin_vec_new );
+ ALLOC_or_NULL(SO_SYN_MALLOC, _ZnajRKSt9nothrow_t, __builtin_vec_new );
#endif
// operator new[](unsigned long, std::nothrow_t const&), GNU mangling
#if VG_WORDSIZE == 8
ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnamRKSt9nothrow_t, __builtin_vec_new );
ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnamRKSt9nothrow_t, __builtin_vec_new );
+ ALLOC_or_NULL(SO_SYN_MALLOC, _ZnamRKSt9nothrow_t, __builtin_vec_new );
#endif
+
#elif defined(VGO_darwin)
// operator new[](unsigned, std::nothrow_t const&), GNU mangling
#if VG_WORDSIZE == 4
- ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnajRKSt9nothrow_t, __builtin_vec_new );
- ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnajRKSt9nothrow_t, __builtin_vec_new );
+ //ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnajRKSt9nothrow_t, __builtin_vec_new );
+ //ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnajRKSt9nothrow_t, __builtin_vec_new );
#endif
// operator new[](unsigned long, std::nothrow_t const&), GNU mangling
#if 1 // FIXME: is this right?
- ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnamRKSt9nothrow_t, __builtin_vec_new );
- ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnamRKSt9nothrow_t, __builtin_vec_new );
+ //ALLOC_or_NULL(VG_Z_LIBSTDCXX_SONAME, _ZnamRKSt9nothrow_t, __builtin_vec_new );
+ //ALLOC_or_NULL(VG_Z_LIBC_SONAME, _ZnamRKSt9nothrow_t, __builtin_vec_new );
#endif
#endif
@@ -421,13 +440,17 @@
(void)VALGRIND_NON_SIMD_CALL1( info.tl_##vg_replacement, p ); \
}
+
#if defined(VGO_linux)
FREE(VG_Z_LIBSTDCXX_SONAME, free, free );
FREE(VG_Z_LIBC_SONAME, free, free );
+ FREE(SO_SYN_MALLOC, free, free );
#elif defined(VGO_darwin)
FREE(VG_Z_LIBC_SONAME, free, free );
+ FREE(SO_SYN_MALLOC, free, free );
ZONEFREE(VG_Z_LIBC_SONAME, malloc_zone_free, free );
+ ZONEFREE(SO_SYN_MALLOC, malloc_zone_free, free );
#endif
@@ -438,6 +461,7 @@
#if defined(VGO_linux)
FREE(VG_Z_LIBSTDCXX_SONAME, cfree, free );
FREE(VG_Z_LIBC_SONAME, cfree, free );
+ FREE(SO_SYN_MALLOC, cfree, free );
#elif defined(VGO_darwin)
//FREE(VG_Z_LIBSTDCXX_SONAME, cfree, free );
@@ -455,11 +479,12 @@
// operator delete(void*), GNU mangling
FREE(VG_Z_LIBSTDCXX_SONAME, _ZdlPv, __builtin_delete );
FREE(VG_Z_LIBC_SONAME, _ZdlPv, __builtin_delete );
+ FREE(SO_SYN_MALLOC, _ZdlPv, __builtin_delete );
#elif defined(VGO_darwin)
// operator delete(void*), GNU mangling
- FREE(VG_Z_LIBSTDCXX_SONAME, _ZdlPv, __builtin_delete );
- FREE(VG_Z_LIBC_SONAME, _ZdlPv, __builtin_delete );
+ //FREE(VG_Z_LIBSTDCXX_SONAME, _ZdlPv, __builtin_delete );
+ //FREE(VG_Z_LIBC_SONAME, _ZdlPv, __builtin_delete );
#endif
@@ -470,11 +495,12 @@
// operator delete(void*, std::nothrow_t const&), GNU mangling
FREE(VG_Z_LIBSTDCXX_SONAME, _ZdlPvRKSt9nothrow_t, __builtin_delete );
FREE(VG_Z_LIBC_SONAME, _ZdlPvRKSt9nothrow_t, __builtin_delete );
+ FREE(SO_SYN_MALLOC, _ZdlPvRKSt9nothrow_t, __builtin_delete );
#elif defined(VGO_darwin)
// operator delete(void*, std::nothrow_t const&), GNU mangling
- FREE(VG_Z_LIBSTDCXX_SONAME, _ZdlPvRKSt9nothrow_t, __builtin_delete );
- FREE(VG_Z_LIBC_SONAME, _ZdlPvRKSt9nothrow_t, __builtin_delete );
+ //FREE(VG_Z_LIBSTDCXX_SONAME, _ZdlPvRKSt9nothrow_t, __builtin_delete );
+ //FREE(VG_Z_LIBC_SONAME, _ZdlPvRKSt9nothrow_t, __builtin_delete );
#endif
@@ -488,14 +514,15 @@
// operator delete[](void*), GNU mangling
FREE(VG_Z_LIBSTDCXX_SONAME, _ZdaPv, __builtin_vec_delete );
FREE(VG_Z_LIBC_SONAME, _ZdaPv, __builtin_vec_delete );
+ FREE(SO_SYN_MALLOC, _ZdaPv, __builtin_vec_delete );
#elif defined(VGO_darwin)
// operator delete[](void*), not mangled (for gcc 2.96)
- FREE(VG_Z_LIBSTDCXX_SONAME, __builtin_vec_delete, __builtin_vec_delete );
- FREE(VG_Z_LIBC_SONAME, __builtin_vec_delete, __builtin_vec_delete );
+ //FREE(VG_Z_LIBSTDCXX_SONAME, __builtin_vec_delete, __builtin_vec_delete );
+ //FREE(VG_Z_LIBC_SONAME, __builtin_vec_delete, __builtin_vec_delete );
// operator delete[](void*), GNU mangling
- FREE(VG_Z_LIBSTDCXX_SONAME, _ZdaPv, __builtin_vec_delete );
- FREE(VG_Z_LIBC_SONAME, _ZdaPv, __builtin_vec_delete );
+ //FREE(VG_Z_LIBSTDCXX_SONAME, _ZdaPv, __builtin_vec_delete );
+ //FREE(VG_Z_LIBC_SONAME, _ZdaPv, __builtin_vec_delete );
#endif
@@ -506,11 +533,12 @@
// operator delete[](void*, std::nothrow_t const&), GNU mangling
FREE(VG_Z_LIBSTDCXX_SONAME, _ZdaPvRKSt9nothrow_t, __builtin_vec_delete );
FREE(VG_Z_LIBC_SONAME, _ZdaPvRKSt9nothrow_t, __builtin_vec_delete );
+ FREE(SO_SYN_MALLOC, _ZdaPvRKSt9nothrow_t, __builtin_vec_delete );
#elif defined(VGO_darwin)
// operator delete[](void*, std::nothrow_t const&), GNU mangling
-FREE(VG_Z_LIBSTDCXX_SONAME, _ZdaPvRKSt9nothrow_t, __builtin_vec_delete );
-FREE(VG_Z_LIBC_SONAME, _ZdaPvRKSt9nothrow_t, __builtin_vec_delete );
+ //FREE(VG_Z_LIBSTDCXX_SONAME, _ZdaPvRKSt9nothrow_t, __builtin_vec_delete );
+ //FREE(VG_Z_LIBC_SONAME, _ZdaPvRKSt9nothrow_t, __builtin_vec_delete );
#endif
@@ -563,10 +591,13 @@
#if defined(VGO_linux)
CALLOC(VG_Z_LIBC_SONAME, calloc);
+ CALLOC(SO_SYN_MALLOC, calloc);
#elif defined(VGO_darwin)
CALLOC(VG_Z_LIBC_SONAME, calloc);
+ CALLOC(SO_SYN_MALLOC, calloc);
ZONECALLOC(VG_Z_LIBC_SONAME, malloc_zone_calloc);
+ ZONECALLOC(SO_SYN_MALLOC, malloc_zone_calloc);
#endif
@@ -629,10 +660,13 @@
#if defined(VGO_linux)
REALLOC(VG_Z_LIBC_SONAME, realloc);
+ REALLOC(SO_SYN_MALLOC, realloc);
#elif defined(VGO_darwin)
REALLOC(VG_Z_LIBC_SONAME, realloc);
+ REALLOC(SO_SYN_MALLOC, realloc);
ZONEREALLOC(VG_Z_LIBC_SONAME, malloc_zone_realloc);
+ ZONEREALLOC(SO_SYN_MALLOC, malloc_zone_realloc);
#endif
@@ -691,10 +725,13 @@
#if defined(VGO_linux)
MEMALIGN(VG_Z_LIBC_SONAME, memalign);
+ MEMALIGN(SO_SYN_MALLOC, memalign);
#elif defined(VGO_darwin)
MEMALIGN(VG_Z_LIBC_SONAME, memalign);
+ MEMALIGN(SO_SYN_MALLOC, memalign);
ZONEMEMALIGN(VG_Z_LIBC_SONAME, malloc_zone_memalign);
+ ZONEMEMALIGN(SO_SYN_MALLOC, malloc_zone_memalign);
#endif
@@ -729,10 +766,13 @@
#if defined(VGO_linux)
VALLOC(VG_Z_LIBC_SONAME, valloc);
+ VALLOC(SO_SYN_MALLOC, valloc);
#elif defined(VGO_darwin)
VALLOC(VG_Z_LIBC_SONAME, valloc);
+ VALLOC(SO_SYN_MALLOC, valloc);
ZONEVALLOC(VG_Z_LIBC_SONAME, malloc_zone_valloc);
+ ZONEVALLOC(SO_SYN_MALLOC, malloc_zone_valloc);
#endif
@@ -753,9 +793,10 @@
#if defined(VGO_linux)
MALLOPT(VG_Z_LIBC_SONAME, mallopt);
+ MALLOPT(SO_SYN_MALLOC, mallopt);
#elif defined(VGO_darwin)
- MALLOPT(VG_Z_LIBC_SONAME, mallopt);
+ //MALLOPT(VG_Z_LIBC_SONAME, mallopt);
#endif
@@ -795,6 +836,7 @@
#if defined(VGO_linux)
MALLOC_TRIM(VG_Z_LIBC_SONAME, malloc_trim);
+ MALLOC_TRIM(SO_SYN_MALLOC, malloc_trim);
#elif defined(VGO_darwin)
//MALLOC_TRIM(VG_Z_LIBC_SONAME, malloc_trim);
@@ -819,11 +861,8 @@
|| (alignment & (alignment - 1)) != 0) \
return VKI_EINVAL; \
\
- /* Round up to minimum alignment if necessary. */ \
- if (alignment < VG_MIN_MALLOC_SZB) \
- alignment = VG_MIN_MALLOC_SZB; \
- \
- mem = (void*)VALGRIND_NON_SIMD_CALL2( info.tl_memalign, alignment, size); \
+ mem = VG_REPLACE_FUNCTION_EZU(10110,VG_Z_LIBC_SONAME,memalign) \
+ (alignment, size); \
\
if (mem != NULL) { \
*memptr = mem; \
@@ -835,6 +874,7 @@
#if defined(VGO_linux)
POSIX_MEMALIGN(VG_Z_LIBC_SONAME, posix_memalign);
+ POSIX_MEMALIGN(SO_SYN_MALLOC, posix_memalign);
#elif defined(VGO_darwin)
//POSIX_MEMALIGN(VG_Z_LIBC_SONAME, posix_memalign);
@@ -864,11 +904,18 @@
#if defined(VGO_linux)
MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, malloc_usable_size);
+ MALLOC_USABLE_SIZE(SO_SYN_MALLOC, malloc_usable_size);
MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, malloc_size);
+ MALLOC_USABLE_SIZE(SO_SYN_MALLOC, malloc_size);
+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
+ MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, dlmalloc_usable_size);
+ MALLOC_USABLE_SIZE(SO_SYN_MALLOC, dlmalloc_usable_size);
+# endif
#elif defined(VGO_darwin)
//MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, malloc_usable_size);
MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, malloc_size);
+ MALLOC_USABLE_SIZE(SO_SYN_MALLOC, malloc_size);
#endif
@@ -915,6 +962,7 @@
#if defined(VGO_linux)
MALLOC_STATS(VG_Z_LIBC_SONAME, malloc_stats);
+ MALLOC_STATS(SO_SYN_MALLOC, malloc_stats);
#elif defined(VGO_darwin)
//MALLOC_STATS(VG_Z_LIBC_SONAME, malloc_stats);
@@ -941,6 +989,7 @@
#if defined(VGO_linux)
MALLINFO(VG_Z_LIBC_SONAME, mallinfo);
+ MALLINFO(SO_SYN_MALLOC, mallinfo);
#elif defined(VGO_darwin)
//MALLINFO(VG_Z_LIBC_SONAME, mallinfo);
@@ -950,13 +999,25 @@
/*------------------ Darwin zone stuff ------------------*/
-
#if defined(VGO_darwin)
+static size_t my_malloc_size ( void* zone, void* ptr )
+{
+ /* Implement "malloc_size" by handing the request through to the
+ tool's .tl_usable_size method. */
+ if (!init_done) init();
+ size_t res = (size_t)VALGRIND_NON_SIMD_CALL1(
+ info.tl_malloc_usable_size, ptr);
+ return res;
+}
+
+/* Note that the (void*) casts below are a kludge which stops
+ compilers complaining about the fact that the the replacement
+ functions aren't really of the right type. */
static vki_malloc_zone_t vg_default_zone = {
NULL, // reserved1
NULL, // reserved2
- NULL, // GrP fixme: malloc_size
+ (void*)my_malloc_size, // JRS fixme: is this right?
(void*)VG_REPLACE_FUNCTION_EZU(10020,VG_Z_LIBC_SONAME,malloc_zone_malloc),
(void*)VG_REPLACE_FUNCTION_EZU(10060,VG_Z_LIBC_SONAME,malloc_zone_calloc),
(void*)VG_REPLACE_FUNCTION_EZU(10130,VG_Z_LIBC_SONAME,malloc_zone_valloc),
@@ -973,6 +1034,7 @@
NULL, /* pressure_relief */
};
+
#define DEFAULT_ZONE(soname, fnname) \
\
void *VG_REPLACE_FUNCTION_EZU(10210,soname,fnname) ( void ); \
@@ -982,6 +1044,8 @@
}
DEFAULT_ZONE(VG_Z_LIBC_SONAME, malloc_default_zone);
+DEFAULT_ZONE(SO_SYN_MALLOC, malloc_default_zone);
+
#define ZONE_FROM_PTR(soname, fnname) \
\
@@ -992,6 +1056,7 @@
}
ZONE_FROM_PTR(VG_Z_LIBC_SONAME, malloc_zone_from_ptr);
+ZONE_FROM_PTR(SO_SYN_MALLOC, malloc_zone_from_ptr);
// GrP fixme bypass libc's use of zone->introspect->check
@@ -1007,120 +1072,6 @@
#endif /* defined(VGO_darwin) */
-void I_WRAP_SONAME_FNNAME_ZZ(NONE, NaClSandboxMemoryStartForValgrind) (void *mem_start);
-void I_WRAP_SONAME_FNNAME_ZZ(NONE, NaClSandboxMemoryStartForValgrind) (void *mem_start) {
- OrigFn fn;
- VALGRIND_GET_ORIG_FN(fn);
- CALL_FN_v_W(fn, mem_start);
- int res;
- VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__NACL_MEM_START, mem_start, 0, 0, 0, 0);
-}
-
-int I_WRAP_SONAME_FNNAME_ZZ(NONE, NaClFileNameForValgrind) (char *file);
-int I_WRAP_SONAME_FNNAME_ZZ(NONE, NaClFileNameForValgrind) (char *file) {
- OrigFn fn;
- int ret;
- VALGRIND_GET_ORIG_FN(fn);
- CALL_FN_W_W(ret, fn, file);
- int res;
- VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__NACL_FILE, file, 0, 0, 0, 0);
- return ret;
-}
-
-void I_WRAP_SONAME_FNNAME_ZZ(NONE, NaClFileMappingForValgrind) (UWord vma, UWord size, UWord file_offset);
-void I_WRAP_SONAME_FNNAME_ZZ(NONE, NaClFileMappingForValgrind) (UWord vma, UWord size, UWord file_offset) {
- OrigFn fn;
- VALGRIND_GET_ORIG_FN(fn);
- CALL_FN_v_WWW(fn, vma, size, file_offset);
- int res;
- VALGRIND_DO_CLIENT_REQUEST(res, 0, VG_USERREQ__NACL_MMAP, vma, size, file_offset, 0, 0);
-}
-
-/* Handle tcmalloc (http://code.google.com/p/google-perftools/) */
-
-/* tc_ functions (used when tcmalloc is running in release mode) */
-ALLOC_or_NULL(NONE,tc_malloc,malloc);
-ALLOC_or_BOMB(NONE,tc_new,__builtin_new);
-ALLOC_or_NULL(NONE,tc_new_nothrow,__builtin_new);
-ALLOC_or_BOMB(NONE,tc_newarray,__builtin_vec_new);
-ALLOC_or_NULL(NONE,tc_newarray_nothrow,__builtin_vec_new);
-FREE(NONE,tc_free,free);
-FREE(NONE,tc_cfree,free);
-FREE(NONE,tc_delete,__builtin_delete);
-FREE(NONE,tc_delete_nothrow,__builtin_delete);
-FREE(NONE,tc_deletearray,__builtin_vec_delete);
-FREE(NONE,tc_deletearray_nothrow,__builtin_vec_delete);
-CALLOC(NONE,tc_calloc);
-REALLOC(NONE,tc_realloc);
-VALLOC(NONE,tc_valloc);
-MEMALIGN(NONE,tc_memalign);
-MALLOPT(NONE,tc_mallopt);
-POSIX_MEMALIGN(NONE,tc_posix_memalign);
-MALLOC_USABLE_SIZE(NONE,tc_malloc_size);
-MALLINFO(NONE,tc_mallinfo);
-
-/* Python */
-ALLOC_or_NULL(NONE, PyObject_Malloc, malloc);
-FREE(NONE, PyObject_Free, free);
-REALLOC(NONE, PyObject_Realloc);
-
-/* Interceptors for custom malloc functions in user code
- (NONE, malloc). We need these to intercept tcmalloc in debug builds.
- TODO(kcc): get rid of these once we have tc_malloc/tc_new/etc
- in tcmalloc's debugallocation.cc
- */
-ALLOC_or_NULL(NONE, malloc, malloc);
-ALLOC_or_BOMB(NONE, _Znwj, __builtin_new);
-ALLOC_or_BOMB(NONE, _Znwm, __builtin_new);
-ALLOC_or_NULL(NONE, _ZnwjRKSt9nothrow_t, __builtin_new);
-ALLOC_or_NULL(NONE, _ZnwmRKSt9nothrow_t, __builtin_new);
-ALLOC_or_BOMB(NONE, _Znaj, __builtin_vec_new);
-ALLOC_or_BOMB(NONE, _Znam, __builtin_vec_new);
-ALLOC_or_NULL(NONE, _ZnajRKSt9nothrow_t, __builtin_vec_new);
-ALLOC_or_NULL(NONE, _ZnamRKSt9nothrow_t, __builtin_vec_new);
-FREE(NONE, free, free );
-FREE(NONE, cfree, free );
-FREE(NONE, _ZdlPv, __builtin_delete );
-FREE(NONE, _ZdlPvRKSt9nothrow_t, __builtin_delete );
-FREE(NONE, _ZdaPv, __builtin_vec_delete );
-FREE(NONE, _ZdaPvRKSt9nothrow_t, __builtin_vec_delete );
-CALLOC(NONE, calloc);
-REALLOC(NONE, realloc);
-MEMALIGN(NONE, memalign);
-VALLOC(NONE, valloc);
-MALLOPT(NONE, mallopt);
-MALLOC_TRIM(NONE, malloc_trim);
-POSIX_MEMALIGN(NONE, posix_memalign);
-MALLOC_USABLE_SIZE(NONE, malloc_usable_size);
-MALLINFO(NONE, mallinfo);
-
-// TODO(kcc): these are interceptors for bash's malloc.
-// The bash interpretor has functions malloc() and sh_malloc()
-// as well as free() and sh_free(). And sometimes they are called
-// inconsistently (malloc, then sh_free).
-// So, if we intercept malloc/free, we also need to intercept
-// sh_malloc/sh_free.
-//
-// Standard valgrind does not intercept user's malloc, so it does not have this
-// problem.
-//
-// Get rid of these once we are able to intercept tcmalloc
-// w/o intercepting (NONE,malloc)
-ALLOC_or_NULL(NONE, sh_malloc, malloc);
-FREE(NONE, sh_free, free );
-FREE(NONE, sh_cfree, free );
-CALLOC(NONE, sh_calloc);
-REALLOC(NONE, sh_realloc);
-MEMALIGN(NONE, sh_memalign);
-VALLOC(NONE, sh_valloc);
-
-/*------- alternative to RUNNING_ON_VALGRIND client request -----*/
-
-#define ANN_FUNC0(ret_ty, f) \
- ret_ty I_WRAP_SONAME_FNNAME_ZZ(NONE,f)(void); \
- ret_ty I_WRAP_SONAME_FNNAME_ZZ(NONE,f)(void)
-
-ANN_FUNC0(int, RunningOnValgrind) { return 1; }
/*------------------ (startup related) ------------------*/
@@ -1129,7 +1080,6 @@
__attribute__((constructor))
static void init(void)
{
-
// This doesn't look thread-safe, but it should be ok... Bart says:
//
// Every program I know of calls malloc() at least once before calling
diff --git a/main/coregrind/m_scheduler/priv_sched-lock-impl.h b/main/coregrind/m_scheduler/priv_sched-lock-impl.h
new file mode 100644
index 0000000..2eb1b89
--- /dev/null
+++ b/main/coregrind/m_scheduler/priv_sched-lock-impl.h
@@ -0,0 +1,51 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Private scheduler lock header. priv_sched-lock-impl.h ---*/
+/*--- ---*/
+/*--- Scheduler lock implementation details. ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2011 Bart Van Assche <bvanassche@acm.org>.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __PRIV_SCHED_LOCK_IMPL_H
+#define __PRIV_SCHED_LOCK_IMPL_H
+
+struct sched_lock_ops {
+ const Char *(*get_sched_lock_name)(void);
+ struct sched_lock *(*create_sched_lock)(void);
+ void (*destroy_sched_lock)(struct sched_lock *p);
+ int (*get_sched_lock_owner)(struct sched_lock *p);
+ void (*acquire_sched_lock)(struct sched_lock *p);
+ void (*release_sched_lock)(struct sched_lock *p);
+};
+
+extern const struct sched_lock_ops ML_(generic_sched_lock_ops);
+extern const struct sched_lock_ops ML_(linux_ticket_lock_ops);
+
+#endif // __PRIV_SCHED_LOCK_IMPL_H
+
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_scheduler/priv_sched-lock.h b/main/coregrind/m_scheduler/priv_sched-lock.h
new file mode 100644
index 0000000..c411735
--- /dev/null
+++ b/main/coregrind/m_scheduler/priv_sched-lock.h
@@ -0,0 +1,51 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Private scheduler lock header. priv_sched-lock.h ---*/
+/*--- ---*/
+/*--- Scheduler lock API. ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2011 Bart Van Assche <bvanassche@acm.org>.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __PRIV_SCHED_LOCK_H
+#define __PRIV_SCHED_LOCK_H
+
+struct sched_lock;
+
+enum SchedLockType { sched_lock_generic, sched_lock_ticket };
+
+Bool ML_(set_sched_lock_impl)(const enum SchedLockType t);
+const Char *ML_(get_sched_lock_name)(void);
+struct sched_lock *ML_(create_sched_lock)(void);
+void ML_(destroy_sched_lock)(struct sched_lock *p);
+int ML_(get_sched_lock_owner)(struct sched_lock *p);
+void ML_(acquire_sched_lock)(struct sched_lock *p);
+void ML_(release_sched_lock)(struct sched_lock *p);
+
+#endif // __PRIV_SCHED_LOCK_H
+
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_scheduler/priv_sema.h b/main/coregrind/m_scheduler/priv_sema.h
index d439b09..d044322 100644
--- a/main/coregrind/m_scheduler/priv_sema.h
+++ b/main/coregrind/m_scheduler/priv_sema.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_scheduler/sched-lock-generic.c b/main/coregrind/m_scheduler/sched-lock-generic.c
new file mode 100644
index 0000000..be01fff
--- /dev/null
+++ b/main/coregrind/m_scheduler/sched-lock-generic.c
@@ -0,0 +1,87 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Generic scheduler lock implementation sched-lock-generic.c ---*/
+/*--- ---*/
+/*--- This implementation does not guarantee fair scheduling on ---*/
+/*--- multicore systems but is sufficient to make the Valgrind ---*/
+/*--- scheduler work reasonably. ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2011 Bart Van Assche <bvanassche@acm.org>.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "pub_core_basics.h"
+#include "pub_tool_mallocfree.h"
+#include "priv_sema.h"
+#include "priv_sched-lock.h"
+#include "priv_sched-lock-impl.h"
+
+struct sched_lock {
+ vg_sema_t sema;
+};
+
+static const Char *get_sched_lock_name(void)
+{
+ return "generic";
+}
+
+static struct sched_lock *create_sched_lock(void)
+{
+ struct sched_lock *p;
+
+ p = VG_(malloc)("sched_lock", sizeof(*p));
+ if (p)
+ ML_(sema_init)(&p->sema);
+ return p;
+}
+
+static void destroy_sched_lock(struct sched_lock *p)
+{
+ ML_(sema_deinit)(&p->sema);
+ VG_(free)(p);
+}
+
+static int get_sched_lock_owner(struct sched_lock *p)
+{
+ return p->sema.owner_lwpid;
+}
+
+static void acquire_sched_lock(struct sched_lock *p)
+{
+ ML_(sema_down)(&p->sema, False);
+}
+
+static void release_sched_lock(struct sched_lock *p)
+{
+ ML_(sema_up)(&p->sema, False);
+}
+
+const struct sched_lock_ops ML_(generic_sched_lock_ops) = {
+ .get_sched_lock_name = get_sched_lock_name,
+ .create_sched_lock = create_sched_lock,
+ .destroy_sched_lock = destroy_sched_lock,
+ .get_sched_lock_owner = get_sched_lock_owner,
+ .acquire_sched_lock = acquire_sched_lock,
+ .release_sched_lock = release_sched_lock,
+};
diff --git a/main/coregrind/m_scheduler/sched-lock.c b/main/coregrind/m_scheduler/sched-lock.c
new file mode 100644
index 0000000..f6fdb4d
--- /dev/null
+++ b/main/coregrind/m_scheduler/sched-lock.c
@@ -0,0 +1,96 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Scheduler lock support functions sched-lock.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2011 Bart Van Assche <bvanassche@acm.org>.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "config.h"
+#include "pub_core_basics.h"
+#include "pub_tool_libcbase.h"
+#include "pub_tool_mallocfree.h"
+#include "priv_sema.h"
+#include "priv_sched-lock.h"
+#include "priv_sched-lock-impl.h"
+
+static struct sched_lock_ops const *sched_lock_ops =
+ &ML_(generic_sched_lock_ops);
+
+static struct sched_lock_ops const *const sched_lock_impl[] = {
+ [sched_lock_generic] = &ML_(generic_sched_lock_ops),
+#ifdef ENABLE_LINUX_TICKET_LOCK
+ [sched_lock_ticket] = &ML_(linux_ticket_lock_ops),
+#endif
+};
+
+/**
+ * Define which scheduler lock implementation to use.
+ *
+ * @param[in] t Scheduler lock type.
+ *
+ * @return True if and only if this function succeeded.
+ *
+ * @note Must be called before any other sched_lock*() function is invoked.
+ */
+Bool ML_(set_sched_lock_impl)(const enum SchedLockType t)
+{
+ struct sched_lock_ops const *p = NULL;
+
+ if ((unsigned)t < sizeof(sched_lock_impl)/sizeof(sched_lock_impl[0]))
+ p = sched_lock_impl[t];
+ if (p)
+ sched_lock_ops = p;
+ return !!p;
+}
+
+const Char *ML_(get_sched_lock_name)(void)
+{
+ return (sched_lock_ops->get_sched_lock_name)();
+}
+
+struct sched_lock *ML_(create_sched_lock)(void)
+{
+ return (sched_lock_ops->create_sched_lock)();
+}
+
+void ML_(destroy_sched_lock)(struct sched_lock *p)
+{
+ return (sched_lock_ops->destroy_sched_lock)(p);
+}
+
+int ML_(get_sched_lock_owner)(struct sched_lock *p)
+{
+ return (sched_lock_ops->get_sched_lock_owner)(p);
+}
+
+void ML_(acquire_sched_lock)(struct sched_lock *p)
+{
+ return (sched_lock_ops->acquire_sched_lock)(p);
+}
+
+void ML_(release_sched_lock)(struct sched_lock *p)
+{
+ return (sched_lock_ops->release_sched_lock)(p);
+}
diff --git a/main/coregrind/m_scheduler/scheduler.c b/main/coregrind/m_scheduler/scheduler.c
index ce8bf3b..4366124 100644
--- a/main/coregrind/m_scheduler/scheduler.c
+++ b/main/coregrind/m_scheduler/scheduler.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -55,7 +55,8 @@
the OS handles threading and signalling are abstracted away and
implemented elsewhere. [Some of the functions have worked their
way back for the moment, until we do an OS port in earnest...]
- */
+*/
+
#include "pub_core_basics.h"
#include "pub_core_debuglog.h"
@@ -89,7 +90,7 @@
#include "pub_core_translate.h" // For VG_(translate)()
#include "pub_core_transtab.h"
#include "pub_core_debuginfo.h" // VG_(di_notify_pdb_debuginfo)
-#include "priv_sema.h"
+#include "priv_sched-lock.h"
#include "pub_core_scheduler.h" // self
#include "pub_core_redir.h"
@@ -108,9 +109,6 @@
/* If False, a fault is Valgrind-internal (ie, a bug) */
Bool VG_(in_generated_code) = False;
-/* Counts downwards in VG_(run_innerloop). */
-UInt VG_(dispatch_ctr);
-
/* 64-bit counter for the number of basic blocks done. */
static ULong bbs_done = 0;
@@ -130,6 +128,17 @@
static ULong n_scheduling_events_MINOR = 0;
static ULong n_scheduling_events_MAJOR = 0;
+/* Stats: number of XIndirs, and number that missed in the fast
+ cache. */
+static ULong stats__n_xindirs = 0;
+static ULong stats__n_xindir_misses = 0;
+
+/* And 32-bit temp bins for the above, so that 32-bit platforms don't
+ have to do 64 bit incs on the hot path through
+ VG_(cp_disp_xindir). */
+/*global*/ UInt VG_(stats__n_xindirs_32) = 0;
+/*global*/ UInt VG_(stats__n_xindir_misses_32) = 0;
+
/* Sanity checking counts. */
static UInt sanity_fast_count = 0;
static UInt sanity_slow_count = 0;
@@ -137,7 +146,12 @@
void VG_(print_scheduler_stats)(void)
{
VG_(message)(Vg_DebugMsg,
- "scheduler: %'llu jumps (bb entries).\n", bbs_done );
+ "scheduler: %'llu event checks.\n", bbs_done );
+ VG_(message)(Vg_DebugMsg,
+ "scheduler: %'llu indir transfers, %'llu misses (1 in %llu)\n",
+ stats__n_xindirs, stats__n_xindir_misses,
+ stats__n_xindirs / (stats__n_xindir_misses
+ ? stats__n_xindir_misses : 1));
VG_(message)(Vg_DebugMsg,
"scheduler: %'llu/%'llu major/minor sched events.\n",
n_scheduling_events_MAJOR, n_scheduling_events_MINOR);
@@ -146,14 +160,11 @@
sanity_fast_count, sanity_slow_count );
}
-/* CPU semaphore, so that threads can run exclusively */
-static vg_sema_t the_BigLock;
+/*
+ * Mutual exclusion object used to serialize threads.
+ */
+static struct sched_lock *the_BigLock;
-// Base address of the NaCl sandbox.
-UWord nacl_head;
-
-// Path to NaCl nexe.
-char *nacl_file;
/* ---------------------------------------------------------------------
Helper functions for the scheduler.
@@ -184,25 +195,33 @@
HChar* name_of_sched_event ( UInt event )
{
switch (event) {
- case VEX_TRC_JMP_SYS_SYSCALL: return "SYSCALL";
- case VEX_TRC_JMP_SYS_INT32: return "INT32";
- case VEX_TRC_JMP_SYS_INT128: return "INT128";
- case VEX_TRC_JMP_SYS_INT129: return "INT129";
- case VEX_TRC_JMP_SYS_INT130: return "INT130";
- case VEX_TRC_JMP_SYS_SYSENTER: return "SYSENTER";
- case VEX_TRC_JMP_CLIENTREQ: return "CLIENTREQ";
- case VEX_TRC_JMP_YIELD: return "YIELD";
- case VEX_TRC_JMP_YIELD_NOREDIR: return "YIELD_NOREDIR";
- case VEX_TRC_JMP_NODECODE: return "NODECODE";
- case VEX_TRC_JMP_MAPFAIL: return "MAPFAIL";
- case VEX_TRC_JMP_NOREDIR: return "NOREDIR";
- case VEX_TRC_JMP_EMWARN: return "EMWARN";
- case VEX_TRC_JMP_TINVAL: return "TINVAL";
- case VG_TRC_INVARIANT_FAILED: return "INVFAILED";
- case VG_TRC_INNER_COUNTERZERO: return "COUNTERZERO";
- case VG_TRC_INNER_FASTMISS: return "FASTMISS";
- case VG_TRC_FAULT_SIGNAL: return "FAULTSIGNAL";
- default: return "??UNKNOWN??";
+ case VEX_TRC_JMP_TINVAL: return "TINVAL";
+ case VEX_TRC_JMP_NOREDIR: return "NOREDIR";
+ case VEX_TRC_JMP_SIGTRAP: return "SIGTRAP";
+ case VEX_TRC_JMP_SIGSEGV: return "SIGSEGV";
+ case VEX_TRC_JMP_SIGBUS: return "SIGBUS";
+ case VEX_TRC_JMP_EMWARN: return "EMWARN";
+ case VEX_TRC_JMP_EMFAIL: return "EMFAIL";
+ case VEX_TRC_JMP_CLIENTREQ: return "CLIENTREQ";
+ case VEX_TRC_JMP_YIELD: return "YIELD";
+ case VEX_TRC_JMP_NODECODE: return "NODECODE";
+ case VEX_TRC_JMP_MAPFAIL: return "MAPFAIL";
+ case VEX_TRC_JMP_SYS_SYSCALL: return "SYSCALL";
+ case VEX_TRC_JMP_SYS_INT32: return "INT32";
+ case VEX_TRC_JMP_SYS_INT128: return "INT128";
+ case VEX_TRC_JMP_SYS_INT129: return "INT129";
+ case VEX_TRC_JMP_SYS_INT130: return "INT130";
+ case VEX_TRC_JMP_SYS_SYSENTER: return "SYSENTER";
+ case VEX_TRC_JMP_BORING: return "VEX_BORING";
+
+ case VG_TRC_BORING: return "VG_BORING";
+ case VG_TRC_INNER_FASTMISS: return "FASTMISS";
+ case VG_TRC_INNER_COUNTERZERO: return "COUNTERZERO";
+ case VG_TRC_FAULT_SIGNAL: return "FAULTSIGNAL";
+ case VG_TRC_INVARIANT_FAILED: return "INVFAILED";
+ case VG_TRC_CHAIN_ME_TO_SLOW_EP: return "CHAIN_ME_SLOW";
+ case VG_TRC_CHAIN_ME_TO_FAST_EP: return "CHAIN_ME_FAST";
+ default: return "??UNKNOWN??";
}
}
@@ -247,7 +266,7 @@
/* First, acquire the_BigLock. We can't do anything else safely
prior to this point. Even doing debug printing prior to this
point is, technically, wrong. */
- ML_(sema_down)(&the_BigLock, False/*not LL*/);
+ VG_(acquire_BigLock_LL)(NULL);
tst = VG_(get_ThreadState)(tid);
@@ -303,19 +322,37 @@
/* Release the_BigLock; this will reschedule any runnable
thread. */
- ML_(sema_up)(&the_BigLock, False/*not LL*/);
+ VG_(release_BigLock_LL)(NULL);
+}
+
+static void init_BigLock(void)
+{
+ vg_assert(!the_BigLock);
+ the_BigLock = ML_(create_sched_lock)();
+}
+
+static void deinit_BigLock(void)
+{
+ ML_(destroy_sched_lock)(the_BigLock);
+ the_BigLock = NULL;
}
/* See pub_core_scheduler.h for description */
void VG_(acquire_BigLock_LL) ( HChar* who )
{
- ML_(sema_down)(&the_BigLock, True/*LL*/);
+ ML_(acquire_sched_lock)(the_BigLock);
}
/* See pub_core_scheduler.h for description */
void VG_(release_BigLock_LL) ( HChar* who )
{
- ML_(sema_up)(&the_BigLock, True/*LL*/);
+ ML_(release_sched_lock)(the_BigLock);
+}
+
+Bool VG_(owns_BigLock_LL) ( ThreadId tid )
+{
+ return (ML_(get_sched_lock_owner)(the_BigLock)
+ == VG_(threads)[tid].os_state.lwpid);
}
@@ -337,7 +374,7 @@
if (VG_(clo_trace_sched))
print_sched_event(tid, "release lock in VG_(exit_thread)");
- ML_(sema_up)(&the_BigLock, False/*not LL*/);
+ VG_(release_BigLock_LL)(NULL);
}
/* If 'tid' is blocked in a syscall, send it SIGVGKILL so as to get it
@@ -524,9 +561,9 @@
}
/* re-init and take the sema */
- ML_(sema_deinit)(&the_BigLock);
- ML_(sema_init)(&the_BigLock);
- ML_(sema_down)(&the_BigLock, False/*not LL*/);
+ deinit_BigLock();
+ init_BigLock();
+ VG_(acquire_BigLock_LL)(NULL);
}
@@ -541,7 +578,21 @@
VG_(debugLog)(1,"sched","sched_init_phase1\n");
- ML_(sema_init)(&the_BigLock);
+ if (VG_(clo_fair_sched) != disable_fair_sched
+ && !ML_(set_sched_lock_impl)(sched_lock_ticket)
+ && VG_(clo_fair_sched) == enable_fair_sched)
+ {
+ VG_(printf)("Error: fair scheduling is not supported on this system.\n");
+ VG_(exit)(1);
+ }
+
+ if (VG_(clo_verbosity) > 1) {
+ VG_(message)(Vg_DebugMsg,
+ "Scheduler: using %s scheduler lock implementation.\n",
+ ML_(get_sched_lock_name)());
+ }
+
+ init_BigLock();
for (i = 0 /* NB; not 1 */; i < VG_N_THREADS; i++) {
/* Paranoia .. completely zero it out. */
@@ -672,14 +723,34 @@
vg_assert(sz_spill == LibVEX_N_SPILL_BYTES);
vg_assert(a_vex + 3 * sz_vex == a_spill);
-# if defined(VGA_amd64)
- /* x86/amd64 XMM regs must form an array, ie, have no
- holes in between. */
+# if defined(VGA_x86)
+ /* x86 XMM regs must form an array, ie, have no holes in
+ between. */
vg_assert(
- (offsetof(VexGuestAMD64State,guest_XMM16)
- - offsetof(VexGuestAMD64State,guest_XMM0))
- == (17/*#regs*/-1) * 16/*bytes per reg*/
+ (offsetof(VexGuestX86State,guest_XMM7)
+ - offsetof(VexGuestX86State,guest_XMM0))
+ == (8/*#regs*/-1) * 16/*bytes per reg*/
);
+ vg_assert(VG_IS_16_ALIGNED(offsetof(VexGuestX86State,guest_XMM0)));
+ vg_assert(VG_IS_8_ALIGNED(offsetof(VexGuestX86State,guest_FPREG)));
+ vg_assert(8 == offsetof(VexGuestX86State,guest_EAX));
+ vg_assert(VG_IS_4_ALIGNED(offsetof(VexGuestX86State,guest_EAX)));
+ vg_assert(VG_IS_4_ALIGNED(offsetof(VexGuestX86State,guest_EIP)));
+# endif
+
+# if defined(VGA_amd64)
+ /* amd64 YMM regs must form an array, ie, have no holes in
+ between. */
+ vg_assert(
+ (offsetof(VexGuestAMD64State,guest_YMM16)
+ - offsetof(VexGuestAMD64State,guest_YMM0))
+ == (17/*#regs*/-1) * 32/*bytes per reg*/
+ );
+ vg_assert(VG_IS_16_ALIGNED(offsetof(VexGuestAMD64State,guest_YMM0)));
+ vg_assert(VG_IS_8_ALIGNED(offsetof(VexGuestAMD64State,guest_FPREG)));
+ vg_assert(16 == offsetof(VexGuestAMD64State,guest_RAX));
+ vg_assert(VG_IS_8_ALIGNED(offsetof(VexGuestAMD64State,guest_RAX)));
+ vg_assert(VG_IS_8_ALIGNED(offsetof(VexGuestAMD64State,guest_RIP)));
# endif
# if defined(VGA_ppc32) || defined(VGA_ppc64)
@@ -696,10 +767,10 @@
# if defined(VGA_arm)
/* arm guest_state VFP regs must be 8 byte aligned for
- loads/stores. */
- vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex.guest_D0));
- vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow1.guest_D0));
- vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow2.guest_D0));
+ loads/stores. Let's use 16 just to be on the safe side. */
+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_D0));
+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_D0));
+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_D0));
/* be extra paranoid .. */
vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex.guest_D1));
vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow1.guest_D1));
@@ -709,6 +780,10 @@
# if defined(VGA_s390x)
/* no special requirements */
# endif
+
+# if defined(VGA_mips32)
+ /* no special requirements */
+# endif
}
// NO_VGDB_POLL value ensures vgdb is not polled, while
@@ -727,30 +802,89 @@
}
/* Run the thread tid for a while, and return a VG_TRC_* value
- indicating why VG_(run_innerloop) stopped. */
-static UInt run_thread_for_a_while ( ThreadId tid )
+ indicating why VG_(disp_run_translations) stopped, and possibly an
+ auxiliary word. Also, only allow the thread to run for at most
+ *dispatchCtrP events. If (as is the normal case) use_alt_host_addr
+ is False, we are running ordinary redir'd translations, and we
+ should therefore start by looking up the guest next IP in TT. If
+ it is True then we ignore the guest next IP and just run from
+ alt_host_addr, which presumably points at host code for a no-redir
+ translation.
+
+ Return results are placed in two_words. two_words[0] is set to the
+ TRC. In the case where that is VG_TRC_CHAIN_ME_TO_{SLOW,FAST}_EP,
+ the address to patch is placed in two_words[1].
+*/
+static
+void run_thread_for_a_while ( /*OUT*/HWord* two_words,
+ /*MOD*/Int* dispatchCtrP,
+ ThreadId tid,
+ HWord alt_host_addr,
+ Bool use_alt_host_addr )
{
- volatile UWord jumped;
- volatile ThreadState* tst = NULL; /* stop gcc complaining */
- volatile UInt trc;
- volatile Int dispatch_ctr_SAVED;
- volatile Int done_this_time;
+ volatile HWord jumped = 0;
+ volatile ThreadState* tst = NULL; /* stop gcc complaining */
+ volatile Int done_this_time = 0;
+ volatile HWord host_code_addr = 0;
/* Paranoia */
vg_assert(VG_(is_valid_tid)(tid));
vg_assert(VG_(is_running_thread)(tid));
vg_assert(!VG_(is_exiting)(tid));
+ vg_assert(*dispatchCtrP > 0);
tst = VG_(get_ThreadState)(tid);
do_pre_run_checks( (ThreadState*)tst );
/* end Paranoia */
- trc = 0;
- dispatch_ctr_SAVED = VG_(dispatch_ctr);
+ /* Futz with the XIndir stats counters. */
+ vg_assert(VG_(stats__n_xindirs_32) == 0);
+ vg_assert(VG_(stats__n_xindir_misses_32) == 0);
+
+ /* Clear return area. */
+ two_words[0] = two_words[1] = 0;
+
+ /* Figure out where we're starting from. */
+ if (use_alt_host_addr) {
+ /* unusual case -- no-redir translation */
+ host_code_addr = alt_host_addr;
+ } else {
+ /* normal case -- redir translation */
+ UInt cno = (UInt)VG_TT_FAST_HASH((Addr)tst->arch.vex.VG_INSTR_PTR);
+ if (LIKELY(VG_(tt_fast)[cno].guest == (Addr)tst->arch.vex.VG_INSTR_PTR))
+ host_code_addr = VG_(tt_fast)[cno].host;
+ else {
+ AddrH res = 0;
+ /* not found in VG_(tt_fast). Searching here the transtab
+ improves the performance compared to returning directly
+ to the scheduler. */
+ Bool found = VG_(search_transtab)(&res, NULL, NULL,
+ (Addr)tst->arch.vex.VG_INSTR_PTR,
+ True/*upd cache*/
+ );
+ if (LIKELY(found)) {
+ host_code_addr = res;
+ } else {
+ /* At this point, we know that we intended to start at a
+ normal redir translation, but it was not found. In
+ which case we can return now claiming it's not
+ findable. */
+ two_words[0] = VG_TRC_INNER_FASTMISS; /* hmm, is that right? */
+ return;
+ }
+ }
+ }
+ /* We have either a no-redir or a redir translation. */
+ vg_assert(host_code_addr != 0); /* implausible */
/* there should be no undealt-with signals */
//vg_assert(VG_(threads)[tid].siginfo.si_signo == 0);
+ /* Set up event counter stuff for the run. */
+ tst->arch.vex.host_EvC_COUNTER = *dispatchCtrP;
+ tst->arch.vex.host_EvC_FAILADDR
+ = (HWord)VG_(fnptr_to_fnentry)( &VG_(disp_cp_evcheck_fail) );
+
if (0) {
vki_sigset_t m;
Int i, err = VG_(sigprocmask)(VKI_SIG_SETMASK, NULL, &m);
@@ -762,6 +896,8 @@
VG_(printf)("\n");
}
+ /* Set up return-value area. */
+
// Tell the tool this thread is about to run client code
VG_TRACK( start_client_code, tid, bbs_done );
@@ -771,26 +907,46 @@
SCHEDSETJMP(
tid,
jumped,
- trc = (UInt)VG_(run_innerloop)( (void*)&tst->arch.vex,
- VG_(clo_profile_flags) > 0 ? 1 : 0 )
+ VG_(disp_run_translations)(
+ two_words,
+ (void*)&tst->arch.vex,
+ host_code_addr
+ )
);
vg_assert(VG_(in_generated_code) == True);
VG_(in_generated_code) = False;
- if (jumped != (UWord)0) {
+ if (jumped != (HWord)0) {
/* We get here if the client took a fault that caused our signal
handler to longjmp. */
- vg_assert(trc == 0);
- trc = VG_TRC_FAULT_SIGNAL;
+ vg_assert(two_words[0] == 0 && two_words[1] == 0); // correct?
+ two_words[0] = VG_TRC_FAULT_SIGNAL;
+ two_words[1] = 0;
block_signals();
}
- done_this_time = (Int)dispatch_ctr_SAVED - (Int)VG_(dispatch_ctr) - 0;
+ /* Merge the 32-bit XIndir/miss counters into the 64 bit versions,
+ and zero out the 32-bit ones in preparation for the next run of
+ generated code. */
+ stats__n_xindirs += (ULong)VG_(stats__n_xindirs_32);
+ VG_(stats__n_xindirs_32) = 0;
+ stats__n_xindir_misses += (ULong)VG_(stats__n_xindir_misses_32);
+ VG_(stats__n_xindir_misses_32) = 0;
+
+ /* Inspect the event counter. */
+ vg_assert((Int)tst->arch.vex.host_EvC_COUNTER >= -1);
+ vg_assert(tst->arch.vex.host_EvC_FAILADDR
+ == (HWord)VG_(fnptr_to_fnentry)( &VG_(disp_cp_evcheck_fail)) );
+
+ done_this_time = *dispatchCtrP - ((Int)tst->arch.vex.host_EvC_COUNTER + 1);
vg_assert(done_this_time >= 0);
bbs_done += (ULong)done_this_time;
+ *dispatchCtrP -= done_this_time;
+ vg_assert(*dispatchCtrP >= 0);
+
// Tell the tool this thread has stopped running client code
VG_TRACK( stop_client_code, tid, bbs_done );
@@ -804,89 +960,16 @@
VG_(gdbserver) (tid);
}
- return trc;
-}
-
-
-/* Run a no-redir translation just once, and return the resulting
- VG_TRC_* value. */
-static UInt run_noredir_translation ( Addr hcode, ThreadId tid )
-{
- volatile UWord jumped;
- volatile ThreadState* tst;
- volatile UWord argblock[4];
- volatile UInt retval;
-
- /* Paranoia */
- vg_assert(VG_(is_valid_tid)(tid));
- vg_assert(VG_(is_running_thread)(tid));
- vg_assert(!VG_(is_exiting)(tid));
-
- tst = VG_(get_ThreadState)(tid);
- do_pre_run_checks( (ThreadState*)tst );
- /* end Paranoia */
-
-# if defined(VGA_ppc32) || defined(VGA_ppc64)
- /* I don't think we need to clear this thread's guest_RESVN here,
- because we can only get here if run_thread_for_a_while() has
- been used immediately before, on this same thread. */
-# endif
-
- /* There can be 3 outcomes from VG_(run_a_noredir_translation):
-
- - a signal occurred and the sighandler longjmp'd. Then both [2]
- and [3] are unchanged - hence zero.
-
- - translation ran normally, set [2] (next guest IP) and set [3]
- to whatever [1] was beforehand, indicating a normal (boring)
- jump to the next block.
-
- - translation ran normally, set [2] (next guest IP) and set [3]
- to something different from [1] beforehand, which indicates a
- TRC_ value.
- */
- argblock[0] = (UWord)hcode;
- argblock[1] = (UWord)&VG_(threads)[tid].arch.vex;
- argblock[2] = 0; /* next guest IP is written here */
- argblock[3] = 0; /* guest state ptr afterwards is written here */
-
- // Tell the tool this thread is about to run client code
- VG_TRACK( start_client_code, tid, bbs_done );
-
- vg_assert(VG_(in_generated_code) == False);
- VG_(in_generated_code) = True;
-
- SCHEDSETJMP(
- tid,
- jumped,
- VG_(run_a_noredir_translation)( &argblock[0] )
- );
-
- VG_(in_generated_code) = False;
-
- if (jumped != (UWord)0) {
- /* We get here if the client took a fault that caused our signal
- handler to longjmp. */
- vg_assert(argblock[2] == 0); /* next guest IP was not written */
- vg_assert(argblock[3] == 0); /* trc was not written */
- block_signals();
- retval = VG_TRC_FAULT_SIGNAL;
+ /* TRC value and possible auxiliary patch-address word are already
+ in two_words[0] and [1] respectively, as a result of the call to
+ VG_(run_innerloop). */
+ /* Stay sane .. */
+ if (two_words[0] == VG_TRC_CHAIN_ME_TO_SLOW_EP
+ || two_words[0] == VG_TRC_CHAIN_ME_TO_FAST_EP) {
+ vg_assert(two_words[1] != 0); /* we have a legit patch addr */
} else {
- /* store away the guest program counter */
- VG_(set_IP)( tid, argblock[2] );
- if (argblock[3] == argblock[1])
- /* the guest state pointer afterwards was unchanged */
- retval = VG_TRC_BORING;
- else
- retval = (UInt)argblock[3];
+ vg_assert(two_words[1] == 0); /* nobody messed with it */
}
-
- bbs_done++;
-
- // Tell the tool this thread has stopped running client code
- VG_TRACK( stop_client_code, tid, bbs_done );
-
- return retval;
}
@@ -901,13 +984,15 @@
/* Trivial event. Miss in the fast-cache. Do a full
lookup for it. */
- found = VG_(search_transtab)( NULL, ip, True/*upd_fast_cache*/ );
+ found = VG_(search_transtab)( NULL, NULL, NULL,
+ ip, True/*upd_fast_cache*/ );
if (UNLIKELY(!found)) {
/* Not found; we need to request a translation. */
if (VG_(translate)( tid, ip, /*debug*/False, 0/*not verbose*/,
bbs_done, True/*allow redirection*/ )) {
- found = VG_(search_transtab)( NULL, ip, True );
- vg_assert2(found, "VG_TRC_INNER_FASTMISS: missing tt_fast entry");
+ found = VG_(search_transtab)( NULL, NULL, NULL,
+ ip, True );
+ vg_assert2(found, "handle_tt_miss: missing tt_fast entry");
} else {
// If VG_(translate)() fails, it's because it had to throw a
@@ -919,6 +1004,43 @@
}
}
+static
+void handle_chain_me ( ThreadId tid, void* place_to_chain, Bool toFastEP )
+{
+ Bool found = False;
+ Addr ip = VG_(get_IP)(tid);
+ UInt to_sNo = (UInt)-1;
+ UInt to_tteNo = (UInt)-1;
+
+ found = VG_(search_transtab)( NULL, &to_sNo, &to_tteNo,
+ ip, False/*dont_upd_fast_cache*/ );
+ if (!found) {
+ /* Not found; we need to request a translation. */
+ if (VG_(translate)( tid, ip, /*debug*/False, 0/*not verbose*/,
+ bbs_done, True/*allow redirection*/ )) {
+ found = VG_(search_transtab)( NULL, &to_sNo, &to_tteNo,
+ ip, False );
+ vg_assert2(found, "handle_chain_me: missing tt_fast entry");
+ } else {
+ // If VG_(translate)() fails, it's because it had to throw a
+ // signal because the client jumped to a bad address. That
+ // means that either a signal has been set up for delivery,
+ // or the thread has been marked for termination. Either
+ // way, we just need to go back into the scheduler loop.
+ return;
+ }
+ }
+ vg_assert(found);
+ vg_assert(to_sNo != -1);
+ vg_assert(to_tteNo != -1);
+
+ /* So, finally we know where to patch through to. Do the patching
+ and update the various admin tables that allow it to be undone
+ in the case that the destination block gets deleted. */
+ VG_(tt_tc_do_chaining)( place_to_chain,
+ to_sNo, to_tteNo, toFastEP );
+}
+
static void handle_syscall(ThreadId tid, UInt trc)
{
ThreadState * volatile tst = VG_(get_ThreadState)(tid);
@@ -950,9 +1072,15 @@
/* tid just requested a jump to the noredir version of its current
program counter. So make up that translation if needed, run it,
- and return the resulting thread return code. */
-static UInt/*trc*/ handle_noredir_jump ( ThreadId tid )
+ and return the resulting thread return code in two_words[]. */
+static
+void handle_noredir_jump ( /*OUT*/HWord* two_words,
+ /*MOD*/Int* dispatchCtrP,
+ ThreadId tid )
{
+ /* Clear return area. */
+ two_words[0] = two_words[1] = 0;
+
AddrH hcode = 0;
Addr ip = VG_(get_IP)(tid);
@@ -964,14 +1092,14 @@
found = VG_(search_unredir_transtab)( &hcode, ip );
vg_assert2(found, "unredir translation missing after creation?!");
-
} else {
// If VG_(translate)() fails, it's because it had to throw a
// signal because the client jumped to a bad address. That
// means that either a signal has been set up for delivery,
// or the thread has been marked for termination. Either
// way, we just need to go back into the scheduler loop.
- return VG_TRC_BORING;
+ two_words[0] = VG_TRC_BORING;
+ return;
}
}
@@ -979,8 +1107,10 @@
vg_assert(found);
vg_assert(hcode != 0);
- /* Otherwise run it and return the resulting VG_TRC_* value. */
- return run_noredir_translation( hcode, tid );
+ /* Otherwise run it and return the resulting VG_TRC_* value. */
+ vg_assert(*dispatchCtrP > 0); /* so as to guarantee progress */
+ run_thread_for_a_while( two_words, dispatchCtrP, tid,
+ hcode, True/*use hcode*/ );
}
@@ -992,7 +1122,9 @@
*/
VgSchedReturnCode VG_(scheduler) ( ThreadId tid )
{
- UInt trc = VG_TRC_BORING;
+ /* Holds the remaining size of this thread's "timeslice". */
+ Int dispatch_ctr = 0;
+
ThreadState *tst = VG_(get_ThreadState)(tid);
static Bool vgdb_startup_action_done = False;
@@ -1051,11 +1183,12 @@
vg_assert(VG_(is_running_thread)(tid));
- VG_(dispatch_ctr) = SCHEDULING_QUANTUM + 1;
+ dispatch_ctr = SCHEDULING_QUANTUM;
while (!VG_(is_exiting)(tid)) {
- if (VG_(dispatch_ctr) == 1) {
+ vg_assert(dispatch_ctr >= 0);
+ if (dispatch_ctr == 0) {
/* Our slice is done, so yield the CPU to another thread. On
Linux, this doesn't sleep between sleeping and running,
@@ -1078,8 +1211,6 @@
"VG_(scheduler):timeslice");
/* ------------ now we don't have The Lock ------------ */
- VG_(do_syscall0)(__NR_sched_yield);
-
VG_(acquire_BigLock)(tid, "VG_(scheduler):timeslice");
/* ------------ now we do have The Lock ------------ */
@@ -1104,7 +1235,8 @@
exceed zero before entering the innerloop. Also also, the
decrement is done before the bb is actually run, so you
always get at least one decrement even if nothing happens. */
- VG_(dispatch_ctr) = SCHEDULING_QUANTUM + 1;
+ // FIXME is this right?
+ dispatch_ctr = SCHEDULING_QUANTUM;
/* paranoia ... */
vg_assert(tst->tid == tid);
@@ -1116,21 +1248,20 @@
if (0)
VG_(message)(Vg_DebugMsg, "thread %d: running for %d bbs\n",
- tid, VG_(dispatch_ctr) - 1 );
+ tid, dispatch_ctr - 1 );
- if (trc == VEX_TRC_JMP_YIELD_NOREDIR) {
- trc = handle_noredir_jump(tid);
- } else {
- trc = run_thread_for_a_while ( tid );
- }
+ HWord trc[2]; /* "two_words" */
+ run_thread_for_a_while( &trc[0],
+ &dispatch_ctr,
+ tid, 0/*ignored*/, False );
if (VG_(clo_trace_sched) && VG_(clo_verbosity) > 2) {
- Char buf[50];
- VG_(sprintf)(buf, "TRC: %s", name_of_sched_event(trc));
+ HChar buf[50];
+ VG_(sprintf)(buf, "TRC: %s", name_of_sched_event(trc[0]));
print_sched_event(tid, buf);
}
- if (trc == VEX_TRC_JMP_NOREDIR) {
+ if (trc[0] == VEX_TRC_JMP_NOREDIR) {
/* If we got a request to run a no-redir version of
something, do so now -- handle_noredir_jump just (creates
and) runs that one translation. The flip side is that the
@@ -1138,20 +1269,61 @@
request -- that would be nonsensical. It can, however,
return VG_TRC_BORING, which just means keep going as
normal. */
- trc = handle_noredir_jump(tid);
- vg_assert(trc != VEX_TRC_JMP_NOREDIR);
+ /* Note that the fact that we need to continue with a
+ no-redir jump is not recorded anywhere else in this
+ thread's state. So we *must* execute the block right now
+ -- we can't fail to execute it and later resume with it,
+ because by then we'll have forgotten the fact that it
+ should be run as no-redir, but will get run as a normal
+ potentially-redir'd, hence screwing up. This really ought
+ to be cleaned up, by noting in the guest state that the
+ next block to be executed should be no-redir. Then we can
+ suspend and resume at any point, which isn't the case at
+ the moment. */
+ handle_noredir_jump( &trc[0],
+ &dispatch_ctr,
+ tid );
+ vg_assert(trc[0] != VEX_TRC_JMP_NOREDIR);
+
+ /* This can't be allowed to happen, since it means the block
+ didn't execute, and we have no way to resume-as-noredir
+ after we get more timeslice. But I don't think it ever
+ can, since handle_noredir_jump will assert if the counter
+ is zero on entry. */
+ vg_assert(trc[0] != VG_TRC_INNER_COUNTERZERO);
+
+ /* A no-redir translation can't return with a chain-me
+ request, since chaining in the no-redir cache is too
+ complex. */
+ vg_assert(trc[0] != VG_TRC_CHAIN_ME_TO_SLOW_EP
+ && trc[0] != VG_TRC_CHAIN_ME_TO_FAST_EP);
}
- switch (trc) {
+ switch (trc[0]) {
+ case VEX_TRC_JMP_BORING:
+ /* assisted dispatch, no event. Used by no-redir
+ translations to force return to the scheduler. */
case VG_TRC_BORING:
/* no special event, just keep going. */
break;
case VG_TRC_INNER_FASTMISS:
- vg_assert(VG_(dispatch_ctr) > 1);
+ vg_assert(dispatch_ctr > 0);
handle_tt_miss(tid);
break;
-
+
+ case VG_TRC_CHAIN_ME_TO_SLOW_EP: {
+ if (0) VG_(printf)("sched: CHAIN_TO_SLOW_EP: %p\n", (void*)trc[1] );
+ handle_chain_me(tid, (void*)trc[1], False);
+ break;
+ }
+
+ case VG_TRC_CHAIN_ME_TO_FAST_EP: {
+ if (0) VG_(printf)("sched: CHAIN_TO_FAST_EP: %p\n", (void*)trc[1] );
+ handle_chain_me(tid, (void*)trc[1], True);
+ break;
+ }
+
case VEX_TRC_JMP_CLIENTREQ:
do_client_request(tid);
break;
@@ -1160,7 +1332,7 @@
case VEX_TRC_JMP_SYS_INT129: /* x86-darwin */
case VEX_TRC_JMP_SYS_INT130: /* x86-darwin */
case VEX_TRC_JMP_SYS_SYSCALL: /* amd64-linux, ppc32-linux, amd64-darwin */
- handle_syscall(tid, trc);
+ handle_syscall(tid, trc[0]);
if (VG_(clo_sanity_level) > 2)
VG_(sanity_check_general)(True); /* sanity-check every syscall */
break;
@@ -1173,17 +1345,13 @@
before swapping to another. That means that short term
spins waiting for hardware to poke memory won't cause a
thread swap. */
- if (VG_(dispatch_ctr) > 2000)
- VG_(dispatch_ctr) = 2000;
+ if (dispatch_ctr > 2000)
+ dispatch_ctr = 2000;
break;
- case VEX_TRC_JMP_YIELD_NOREDIR:
- VG_(dispatch_ctr) = 1;
- break;
-
case VG_TRC_INNER_COUNTERZERO:
/* Timeslice is out. Let a new thread be scheduled. */
- vg_assert(VG_(dispatch_ctr) == 1);
+ vg_assert(dispatch_ctr == 0);
break;
case VG_TRC_FAULT_SIGNAL:
@@ -1256,11 +1424,12 @@
VG_(synth_sigbus)(tid);
break;
- case VEX_TRC_JMP_NODECODE:
+ case VEX_TRC_JMP_NODECODE: {
+ Addr addr = VG_(get_IP)(tid);
+
VG_(umsg)(
- "valgrind: Unrecognised instruction at address %#lx.\n",
- VG_(get_IP)(tid));
- VG_(get_and_pp_StackTrace)(tid, 50);
+ "valgrind: Unrecognised instruction at address %#lx.\n", addr);
+ VG_(get_and_pp_StackTrace)(tid, VG_(clo_backtrace_size));
#define M(a) VG_(umsg)(a "\n");
M("Your program just tried to execute an instruction that Valgrind" );
M("did not recognise. There are two possible reasons for this." );
@@ -1273,9 +1442,25 @@
M("Either way, Valgrind will now raise a SIGILL signal which will" );
M("probably kill your program." );
#undef M
- VG_(synth_sigill)(tid, VG_(get_IP)(tid));
- break;
+#if defined(VGA_s390x)
+ /* Now that the complaint is out we need to adjust the guest_IA. The
+ reason is that -- after raising the exception -- execution will
+ continue with the insn that follows the invalid insn. As the first
+ 2 bits of the invalid insn determine its length in the usual way,
+ we can compute the address of the next insn here and adjust the
+ guest_IA accordingly. This adjustment is essential and tested by
+ none/tests/s390x/op_exception.c (which would loop forever
+ otherwise) */
+ UChar byte = ((UChar *)addr)[0];
+ UInt insn_length = ((((byte >> 6) + 1) >> 1) + 1) << 1;
+ Addr next_insn_addr = addr + insn_length;
+
+ VG_(set_IP)(tid, next_insn_addr);
+#endif
+ VG_(synth_sigill)(tid, addr);
+ break;
+ }
case VEX_TRC_JMP_TINVAL:
VG_(discard_translations)(
(Addr64)VG_(threads)[tid].arch.vex.guest_TISTART,
@@ -1319,7 +1504,7 @@
/* return address in client edx */
VG_(threads)[tid].arch.vex.guest_EIP
= VG_(threads)[tid].arch.vex.guest_EDX;
- handle_syscall(tid, trc);
+ handle_syscall(tid, trc[0]);
# else
vg_assert2(0, "VG_(scheduler), phase 3: "
"sysenter_x86 on non-x86 platform?!?!");
@@ -1328,7 +1513,7 @@
default:
vg_assert2(0, "VG_(scheduler), phase 3: "
- "unexpected thread return code (%u)", trc);
+ "unexpected thread return code (%u)", trc[0]);
/* NOTREACHED */
break;
@@ -1393,6 +1578,9 @@
#elif defined (VGA_s390x)
# define VG_CLREQ_ARGS guest_r2
# define VG_CLREQ_RET guest_r3
+#elif defined(VGA_mips32)
+# define VG_CLREQ_ARGS guest_r12
+# define VG_CLREQ_RET guest_r11
#else
# error Unknown arch
#endif
@@ -1685,69 +1873,6 @@
goto my_default;
}
- case VG_USERREQ__NACL_MEM_START: {
- Addr mem_start = arg[1];
- nacl_head = mem_start;
- VG_(printf)("*********************** NaCl mem_start: %p\n", (void*)mem_start);
-
- // At this point all segments in the sandbox belong to nacl_file (the
- // first untrusted binary loaded by sel_ldr), and have correct
- // permissions. Read its debug info.
- NSegment* seg = VG_(am_find_nsegment)(mem_start);
- int fnIdx = -1;
- while (seg) {
- if (seg->kind == SkFileC) {
- if (fnIdx == seg->fnIdx || fnIdx == -1) {
- fnIdx = seg->fnIdx;
- VG_(printf)("Segment at %p belongs to the loader\n", (void*)seg->start);
- VG_(di_notify_mmap)(seg->start, False, /*glider: don't use fd*/-1);
- }
- }
- seg = VG_(am_next_nsegment)((NSegment*)seg, True);
- }
- goto my_default;
- }
-
- case VG_USERREQ__NACL_FILE: {
- VG_(printf)("*********************** NaCl nacl_file: %s\n", (void*)arg[1]);
- nacl_file = (char*) arg[1];
- goto my_default;
- }
-
- case VG_USERREQ__NACL_MMAP: {
- // Simulate an mmap().
- UWord vma = arg[1]; // Base VMA of the mapping.
- UWord size = arg[2]; // Size of the mapping.
- UWord file_offset = arg[3]; // File offset.
- UWord access = arg[4]; // Access.
- UWord clone_vma = arg[5]; // Another mapping of the same; only used to find the file name.
- if (!access)
- access = VKI_PROT_READ | VKI_PROT_EXEC;
- VG_(printf)("*********************** NaCl nacl_mmap: %lx %lx %lx %lx\n", vma, size, file_offset, clone_vma);
-
- char* file_name = NULL;
- if (clone_vma) {
- NSegment* seg = VG_(am_find_nsegment)(clone_vma);
- file_name = VG_(am_get_filename)(seg);
- VG_(printf)("*********************** NaCl DSO file_name: %s\n", file_name);
- }
-
- UWord vma_end = vma + size;
- UWord vma_aligned = VG_PGROUNDDN(vma);
- UWord vma_end_aligned = VG_PGROUNDUP(vma_end);
- size = vma_end_aligned - vma_aligned;
- file_offset -= vma - vma_aligned;
- VG_(am_notify_fake_client_mmap)(vma_aligned, size, access,
- 0, file_name ? file_name : (VG_(clo_nacl_file) ? VG_(clo_nacl_file) : nacl_file), file_offset);
- // If file_name == NULL, then this is the main (sel_ldr-mapped) nexe,
- // and has incorrect permissions at this point. In that case, wait for
- // NACL_MEM_START to read the debug info.
- if (file_name)
- VG_(di_notify_mmap)(vma_aligned, False, /*glider: don't use fd*/-1);
- goto my_default;
- }
-
-
default:
my_default:
if (os_client_request(tid, arg)) {
@@ -1837,15 +1962,12 @@
bad = True;
}
-#if !defined(VGO_darwin)
- // GrP fixme
- if (lwpid != the_BigLock.owner_lwpid) {
+ if (lwpid != ML_(get_sched_lock_owner)(the_BigLock)) {
VG_(message)(Vg_DebugMsg,
"Thread (LWPID) %d doesn't own the_BigLock\n",
tid);
bad = True;
}
-#endif
/* Periodically show the state of all threads, for debugging
purposes. */
diff --git a/main/coregrind/m_scheduler/sema.c b/main/coregrind/m_scheduler/sema.c
index 90097b7..bbdcf19 100644
--- a/main/coregrind/m_scheduler/sema.c
+++ b/main/coregrind/m_scheduler/sema.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -34,6 +34,10 @@
#include "pub_core_libcassert.h"
#include "pub_core_libcfile.h"
#include "pub_core_libcproc.h" // For VG_(gettid)()
+#include "pub_tool_inner.h"
+#if defined(ENABLE_INNER_CLIENT_REQUEST)
+#include "helgrind/helgrind.h"
+#endif
#include "priv_sema.h"
/*
@@ -72,6 +76,9 @@
buf[0] = sema_char;
buf[1] = 0;
sema_char++;
+ INNER_REQUEST(ANNOTATE_RWLOCK_CREATE(sema));
+ INNER_REQUEST(ANNOTATE_BENIGN_RACE_SIZED(&sema->owner_lwpid,
+ sizeof(sema->owner_lwpid), ""));
res = VG_(write)(sema->pipe[1], buf, 1);
vg_assert(res == 1);
}
@@ -80,6 +87,7 @@
{
vg_assert(sema->owner_lwpid != -1); /* must be initialised */
vg_assert(sema->pipe[0] != sema->pipe[1]);
+ INNER_REQUEST(ANNOTATE_RWLOCK_DESTROY(sema));
VG_(close)(sema->pipe[0]);
VG_(close)(sema->pipe[1]);
sema->pipe[0] = sema->pipe[1] = -1;
@@ -99,6 +107,7 @@
again:
buf[0] = buf[1] = 0;
ret = VG_(read)(sema->pipe[0], buf, 1);
+ INNER_REQUEST(ANNOTATE_RWLOCK_ACQUIRED(sema, /*is_w*/1));
if (ret != 1)
VG_(debugLog)(0, "scheduler",
@@ -131,6 +140,7 @@
sema->owner_lwpid = 0;
+ INNER_REQUEST(ANNOTATE_RWLOCK_RELEASED(sema, /*is_w*/1));
ret = VG_(write)(sema->pipe[1], buf, 1);
if (ret != 1)
diff --git a/main/coregrind/m_scheduler/ticket-lock-linux.c b/main/coregrind/m_scheduler/ticket-lock-linux.c
new file mode 100644
index 0000000..e28841c
--- /dev/null
+++ b/main/coregrind/m_scheduler/ticket-lock-linux.c
@@ -0,0 +1,196 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Linux ticket lock implementation ticket-lock-linux.c ---*/
+/*--- ---*/
+/*--- Guarantees fair scheduling even if multiple threads are ---*/
+/*--- runnable at the same time on a multicore system. Has been ---*/
+/*--- observed to cause a slow-down compared to the generic ---*/
+/*--- scheduler lock with CPU frequency scaling enabled. Makes ---*/
+/*--- Valgrind slightly faster if CPU frequency scaling has been ---*/
+/*--- disabled. See also http://bugs.kde.org/show_bug.cgi?id=270006---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2011 Bart Van Assche <bvanassche@acm.org>.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include "pub_core_basics.h"
+#include "pub_core_libcassert.h"
+#include "pub_core_libcbase.h" // VG_(memset)()
+#include "pub_core_libcprint.h"
+#include "pub_core_syscall.h"
+#include "pub_core_vki.h"
+#include "pub_core_vkiscnums.h" // __NR_futex
+#include "pub_tool_libcproc.h"
+#include "pub_tool_mallocfree.h"
+#include "pub_tool_threadstate.h"
+#include "pub_tool_inner.h"
+#if defined(ENABLE_INNER_CLIENT_REQUEST)
+#include "helgrind/helgrind.h"
+#endif
+#include "priv_sched-lock.h"
+#include "priv_sched-lock-impl.h"
+
+#define TL_FUTEX_COUNT_LOG2 4
+#define TL_FUTEX_COUNT (1U << TL_FUTEX_COUNT_LOG2)
+#define TL_FUTEX_MASK (TL_FUTEX_COUNT - 1)
+
+struct sched_lock {
+ volatile unsigned head;
+ volatile unsigned tail;
+ volatile unsigned futex[TL_FUTEX_COUNT];
+ int owner;
+};
+
+#if 1
+static Bool s_debug;
+#else
+static Bool s_debug = True;
+#endif
+
+static const Char *get_sched_lock_name(void)
+{
+ return "ticket lock";
+}
+
+static struct sched_lock *create_sched_lock(void)
+{
+ struct sched_lock *p;
+
+ p = VG_(malloc)("sched_lock", sizeof(*p));
+ if (p) {
+ // The futex syscall requires that a futex takes four bytes.
+ vg_assert(sizeof(p->futex[0]) == 4);
+
+ p->head = 0;
+ p->tail = 0;
+ VG_(memset)((void*)p->futex, 0, sizeof(p->futex));
+ p->owner = 0;
+ }
+ INNER_REQUEST(ANNOTATE_RWLOCK_CREATE(p));
+ INNER_REQUEST(ANNOTATE_BENIGN_RACE_SIZED(&p->futex, sizeof(p->futex), ""));
+ return p;
+}
+
+static void destroy_sched_lock(struct sched_lock *p)
+{
+ INNER_REQUEST(ANNOTATE_RWLOCK_DESTROY(p));
+ VG_(free)(p);
+}
+
+static int get_sched_lock_owner(struct sched_lock *p)
+{
+ return p->owner;
+}
+
+/*
+ * Acquire ticket lock. Increment the tail of the queue and use the original
+ * value as the ticket value. Wait until the head of the queue equals the
+ * ticket value. The futex used to wait depends on the ticket value in order
+ * to avoid that all threads get woken up every time a ticket lock is
+ * released. That last effect is sometimes called the "thundering herd"
+ * effect.
+ *
+ * See also Nick Piggin, x86: FIFO ticket spinlocks, Linux kernel mailing list
+ * (http://lkml.org/lkml/2007/11/1/125) for more info.
+ */
+static void acquire_sched_lock(struct sched_lock *p)
+{
+ unsigned ticket, futex_value;
+ volatile unsigned *futex;
+ SysRes sres;
+
+ ticket = __sync_fetch_and_add(&p->tail, 1);
+ futex = &p->futex[ticket & TL_FUTEX_MASK];
+ if (s_debug)
+ VG_(printf)("[%d/%d] acquire: ticket %d\n", VG_(getpid)(),
+ VG_(gettid)(), ticket);
+ for (;;) {
+ futex_value = *futex;
+ __sync_synchronize();
+ if (ticket == p->head)
+ break;
+ if (s_debug)
+ VG_(printf)("[%d/%d] acquire: ticket %d - waiting until"
+ " futex[%ld] != %d\n", VG_(getpid)(),
+ VG_(gettid)(), ticket, (long)(futex - p->futex),
+ futex_value);
+ sres = VG_(do_syscall3)(__NR_futex, (UWord)futex,
+ VKI_FUTEX_WAIT | VKI_FUTEX_PRIVATE_FLAG,
+ futex_value);
+ if (sr_isError(sres) && sres._val != VKI_EAGAIN) {
+ VG_(printf)("futex_wait() returned error code %ld\n", sres._val);
+ vg_assert(False);
+ }
+ }
+ __sync_synchronize();
+ INNER_REQUEST(ANNOTATE_RWLOCK_ACQUIRED(p, /*is_w*/1));
+ vg_assert(p->owner == 0);
+ p->owner = VG_(gettid)();
+}
+
+/*
+ * Release a ticket lock by incrementing the head of the queue. Only generate
+ * a thread wakeup signal if at least one thread is waiting. If the queue tail
+ * matches the wakeup_ticket value, no threads have to be woken up.
+ *
+ * Note: tail will only be read after head has been incremented since both are
+ * declared as volatile and since the __sync...() functions imply a memory
+ * barrier.
+ */
+static void release_sched_lock(struct sched_lock *p)
+{
+ unsigned wakeup_ticket, futex_value;
+ volatile unsigned *futex;
+ SysRes sres;
+
+ vg_assert(p->owner != 0);
+ p->owner = 0;
+ INNER_REQUEST(ANNOTATE_RWLOCK_RELEASED(p, /*is_w*/1));
+ wakeup_ticket = __sync_fetch_and_add(&p->head, 1) + 1;
+ if (p->tail != wakeup_ticket) {
+ futex = &p->futex[wakeup_ticket & TL_FUTEX_MASK];
+ futex_value = __sync_fetch_and_add(futex, 1);
+ if (s_debug)
+ VG_(printf)("[%d/%d] release: waking up ticket %d (futex[%ld] = %d)"
+ "\n", VG_(getpid)(), VG_(gettid)(), wakeup_ticket,
+ (long)(futex - p->futex), futex_value);
+ sres = VG_(do_syscall3)(__NR_futex, (UWord)futex,
+ VKI_FUTEX_WAKE | VKI_FUTEX_PRIVATE_FLAG,
+ 0x7fffffff);
+ vg_assert(!sr_isError(sres));
+ } else {
+ if (s_debug)
+ VG_(printf)("[%d/%d] release: no thread is waiting for ticket %d\n",
+ VG_(getpid)(), VG_(gettid)(), wakeup_ticket);
+ }
+}
+
+const struct sched_lock_ops ML_(linux_ticket_lock_ops) = {
+ .get_sched_lock_name = get_sched_lock_name,
+ .create_sched_lock = create_sched_lock,
+ .destroy_sched_lock = destroy_sched_lock,
+ .get_sched_lock_owner = get_sched_lock_owner,
+ .acquire_sched_lock = acquire_sched_lock,
+ .release_sched_lock = release_sched_lock,
+};
diff --git a/main/coregrind/m_seqmatch.c b/main/coregrind/m_seqmatch.c
index 9a5c004..35f0f62 100644
--- a/main/coregrind/m_seqmatch.c
+++ b/main/coregrind/m_seqmatch.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks Ltd
+ Copyright (C) 2008-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -45,7 +45,8 @@
void* input, SizeT szbInput, UWord nInput, UWord ixInput,
Bool (*pIsStar)(void*),
Bool (*pIsQuery)(void*),
- Bool (*pattEQinp)(void*,void*)
+ Bool (*pattEQinp)(void*,void*,void*,UWord),
+ void* inputCompleter
)
{
/* This is the spec, written in my favourite formal specification
@@ -102,7 +103,8 @@
if (VG_(generic_match)( matchAll,
patt, szbPatt, nPatt, ixPatt+1,
input,szbInput,nInput, ixInput+0,
- pIsStar,pIsQuery,pattEQinp) ) {
+ pIsStar,pIsQuery,pattEQinp,
+ inputCompleter) ) {
return True;
}
// but we can tail-recurse for the second call
@@ -129,7 +131,7 @@
//
// ma (p:ps) (i:is) = p == i && ma ps is
if (havePatt && haveInput) {
- if (!pattEQinp(currPatt,currInput)) return False;
+ if (!pattEQinp(currPatt,currInput,inputCompleter,ixInput)) return False;
ixPatt++; ixInput++; goto tailcall;
}
@@ -163,7 +165,8 @@
*/
static Bool charIsStar ( void* pV ) { return *(Char*)pV == '*'; }
static Bool charIsQuery ( void* pV ) { return *(Char*)pV == '?'; }
-static Bool char_p_EQ_i ( void* pV, void* cV ) {
+static Bool char_p_EQ_i ( void* pV, void* cV,
+ void* null_completer, UWord ixcV ) {
Char p = *(Char*)pV;
Char c = *(Char*)cV;
vg_assert(p != '*' && p != '?');
@@ -175,7 +178,8 @@
True/* match-all */,
(void*)patt, sizeof(UChar), VG_(strlen)(patt), 0,
(void*)input, sizeof(UChar), VG_(strlen)(input), 0,
- charIsStar, charIsQuery, char_p_EQ_i
+ charIsStar, charIsQuery, char_p_EQ_i,
+ NULL
);
}
diff --git a/main/coregrind/m_sigframe/sigframe-amd64-darwin.c b/main/coregrind/m_sigframe/sigframe-amd64-darwin.c
index 1cf8cd3..6a21f28 100644
--- a/main/coregrind/m_sigframe/sigframe-amd64-darwin.c
+++ b/main/coregrind/m_sigframe/sigframe-amd64-darwin.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2011 OpenWorks Ltd
+ Copyright (C) 2006-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -124,12 +124,14 @@
sp_top_of_frame &= ~0xfUL;
rsp = sp_top_of_frame - sizeof(struct hacky_sigframe);
+ rsp -= 8; /* ELF ABI says that rsp+8 must be 16 aligned on
+ entry to a function. */
tst = VG_(get_ThreadState)(tid);
if (!extend(tst, rsp, sp_top_of_frame - rsp))
return;
- vg_assert(VG_IS_16_ALIGNED(rsp));
+ vg_assert(VG_IS_16_ALIGNED(rsp+8));
frame = (struct hacky_sigframe *) rsp;
@@ -182,7 +184,8 @@
if (VG_(clo_trace_signals))
VG_(message)(Vg_DebugMsg,
- "sigframe_create (thread %d): next EIP=%#lx, next ESP=%#lx",
+ "sigframe_create (thread %d): "
+ "next EIP=%#lx, next ESP=%#lx\n",
tid, (Addr)handler, (Addr)frame );
}
@@ -203,11 +206,14 @@
rsp = VG_(get_SP)(tid);
/* why -8 ? because the signal handler's return will have popped
- the return address of the stack; and the return address is the
+ the return address off the stack; and the return address is the
lowest-addressed element of hacky_sigframe. */
frame = (struct hacky_sigframe*)(rsp - 8);
vg_assert(frame->magicPI == 0x31415927);
- vg_assert(VG_IS_16_ALIGNED(frame));
+
+ /* This +8 is because of the -8 referred to in the ELF ABI comment
+ in VG_(sigframe_create) just above. */
+ vg_assert(VG_IS_16_ALIGNED((Addr)frame + 8));
/* restore the entire guest state, and shadows, from the
frame. Note, as per comments above, this is a kludge - should
@@ -221,7 +227,8 @@
if (VG_(clo_trace_signals))
VG_(message)(Vg_DebugMsg,
- "sigframe_destroy (thread %d): valid magic; next RIP=%#llx",
+ "sigframe_destroy (thread %d): "
+ "valid magic; next RIP=%#llx\n",
tid, tst->arch.vex.guest_RIP);
VG_TRACK( die_mem_stack_signal,
diff --git a/main/coregrind/m_sigframe/sigframe-amd64-linux.c b/main/coregrind/m_sigframe/sigframe-amd64-linux.c
index bef5d82..60f70b3 100644
--- a/main/coregrind/m_sigframe/sigframe-amd64-linux.c
+++ b/main/coregrind/m_sigframe/sigframe-amd64-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_sigframe/sigframe-arm-linux.c b/main/coregrind/m_sigframe/sigframe-arm-linux.c
index 441c351..06069e4 100644
--- a/main/coregrind/m_sigframe/sigframe-arm-linux.c
+++ b/main/coregrind/m_sigframe/sigframe-arm-linux.c
@@ -8,11 +8,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2004-2011 Paul Mackerras
+ Copyright (C) 2004-2012 Paul Mackerras
paulus@samba.org
- Copyright (C) 2008-2011 Evan Geller
+ Copyright (C) 2008-2012 Evan Geller
gaze@bea.ms
This program is free software; you can redistribute it and/or
@@ -259,7 +259,12 @@
tst->arch.vex.guest_R0 = sigNo;
if (flags & VKI_SA_RESTORER)
- tst->arch.vex.guest_R14 = (Addr) restorer;
+ tst->arch.vex.guest_R14 = (Addr)restorer;
+ else
+ tst->arch.vex.guest_R14
+ = (flags & VKI_SA_SIGINFO)
+ ? (Addr)&VG_(arm_linux_SUBST_FOR_rt_sigreturn)
+ : (Addr)&VG_(arm_linux_SUBST_FOR_sigreturn);
tst->arch.vex.guest_R15T = (Addr) handler; /* R15 == PC */
}
diff --git a/main/coregrind/m_sigframe/sigframe-mips32-linux.c b/main/coregrind/m_sigframe/sigframe-mips32-linux.c
new file mode 100644
index 0000000..c711a6a
--- /dev/null
+++ b/main/coregrind/m_sigframe/sigframe-mips32-linux.c
@@ -0,0 +1,398 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Create/destroy signal delivery frames. ---*/
+/*--- sigframe-mips32-linux.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#if defined(VGP_mips32_linux)
+
+#include "pub_core_basics.h"
+#include "pub_core_vki.h"
+#include "pub_core_vkiscnums.h"
+#include "pub_core_libcsetjmp.h" // to keep _threadstate.h happy
+#include "pub_core_threadstate.h"
+#include "pub_core_aspacemgr.h"
+#include "pub_core_libcbase.h"
+#include "pub_core_libcassert.h"
+#include "pub_core_libcprint.h"
+#include "pub_core_machine.h"
+#include "pub_core_options.h"
+#include "pub_core_sigframe.h"
+#include "pub_core_signals.h"
+#include "pub_core_tooliface.h"
+#include "pub_core_trampoline.h"
+#include "pub_core_transtab.h" // VG_(discard_translations)
+
+struct vg_sig_private
+{
+ UInt magicPI;
+ UInt sigNo_private;
+ VexGuestMIPS32State vex_shadow1;
+ VexGuestMIPS32State vex_shadow2;
+};
+
+struct sigframe
+{
+ UInt sf_ass[4]; /* argument save space for o32 */
+ UInt sf_pad[2]; /* Was: signal trampoline */
+ struct vki_sigcontext sf_sc;
+ vki_sigset_t sf_mask;
+ struct vg_sig_private priv;
+};
+
+struct rt_sigframe
+{
+ UInt rs_ass[4]; /* argument save space for o32 */
+ UInt rs_pad[2]; /* Was: signal trampoline */
+ vki_siginfo_t rs_info;
+ struct vki_ucontext rs_uc;
+ struct vg_sig_private priv;
+};
+
+/* Extend the stack segment downwards if needed so as to ensure the
+ new signal frames are mapped to something. Return a Bool
+ indicating whether or not the operation was successful.
+*/
+static Bool extend ( ThreadState *tst, Addr addr, SizeT size )
+{
+ ThreadId tid = tst->tid;
+ NSegment const* stackseg = NULL;
+
+ if (VG_(extend_stack)(addr, tst->client_stack_szB))
+ {
+ stackseg = VG_(am_find_nsegment)(addr);
+ }
+
+ if (stackseg == NULL || !stackseg->hasR || !stackseg->hasW)
+ {
+ VG_(message)(Vg_UserMsg,
+ "Can't extend stack to %#lx during signal delivery for thread %d:\n",
+ addr, tid );
+ if (stackseg == NULL)
+ VG_(message)( Vg_UserMsg, " no stack segment\n" );
+ else
+ VG_(message)( Vg_UserMsg, " too small or bad protection modes\n" );
+
+ /* set SIGSEGV to default handler */
+ VG_(set_default_handler)( VKI_SIGSEGV );
+ VG_(synth_fault_mapping)( tid, addr );
+
+ /* The whole process should be about to die, since the default
+ action of SIGSEGV to kill the whole process. */
+ return False;
+ }
+
+ /* For tracking memory events, indicate the entire frame has been
+ allocated. */
+ VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB,
+ size + VG_STACK_REDZONE_SZB, tid );
+
+ return True;
+}
+
+static
+void setup_sigcontext2 ( ThreadState* tst, struct vki_sigcontext **sc1, const vki_siginfo_t *si)
+{
+
+ struct vki_sigcontext *sc = *sc1;
+
+ VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, "signal frame mcontext",
+ (Addr)sc, sizeof(unsigned long long)*34 );
+ sc->sc_regs[1] = tst->arch.vex.guest_r1;
+ sc->sc_regs[2] = tst->arch.vex.guest_r2;
+ sc->sc_regs[3] = tst->arch.vex.guest_r3;
+ sc->sc_regs[4] = tst->arch.vex.guest_r4;
+ sc->sc_regs[5] = tst->arch.vex.guest_r5;
+ sc->sc_regs[6] = tst->arch.vex.guest_r6;
+ sc->sc_regs[7] = tst->arch.vex.guest_r7;
+ sc->sc_regs[8] = tst->arch.vex.guest_r8;
+ sc->sc_regs[9] = tst->arch.vex.guest_r9;
+ sc->sc_regs[10] = tst->arch.vex.guest_r10;
+ sc->sc_regs[11] = tst->arch.vex.guest_r11;
+ sc->sc_regs[12] = tst->arch.vex.guest_r12;
+ sc->sc_regs[13] = tst->arch.vex.guest_r13;
+ sc->sc_regs[14] = tst->arch.vex.guest_r14;
+ sc->sc_regs[15] = tst->arch.vex.guest_r15;
+ sc->sc_regs[16] = tst->arch.vex.guest_r16;
+ sc->sc_regs[17] = tst->arch.vex.guest_r17;
+ sc->sc_regs[18] = tst->arch.vex.guest_r18;
+ sc->sc_regs[19] = tst->arch.vex.guest_r19;
+ sc->sc_regs[20] = tst->arch.vex.guest_r20;
+ sc->sc_regs[21] = tst->arch.vex.guest_r21;
+ sc->sc_regs[22] = tst->arch.vex.guest_r22;
+ sc->sc_regs[23] = tst->arch.vex.guest_r23;
+ sc->sc_regs[24] = tst->arch.vex.guest_r24;
+ sc->sc_regs[25] = tst->arch.vex.guest_r25;
+ sc->sc_regs[26] = tst->arch.vex.guest_r26;
+ sc->sc_regs[27] = tst->arch.vex.guest_r27;
+ sc->sc_regs[28] = tst->arch.vex.guest_r28;
+ sc->sc_regs[29] = tst->arch.vex.guest_r29;
+ sc->sc_regs[30] = tst->arch.vex.guest_r30;
+ sc->sc_regs[31] = tst->arch.vex.guest_r31;
+ sc->sc_pc = tst->arch.vex.guest_PC;
+ sc->sc_mdhi = tst->arch.vex.guest_HI;
+ sc->sc_mdlo = tst->arch.vex.guest_LO;
+}
+
+/* EXPORTED */
+void VG_(sigframe_create)( ThreadId tid,
+ Addr sp_top_of_frame,
+ const vki_siginfo_t *siginfo,
+ const struct vki_ucontext *siguc,
+ void *handler,
+ UInt flags,
+ const vki_sigset_t *mask,
+ void *restorer )
+{
+ Addr sp;
+ ThreadState* tst = VG_(get_ThreadState)(tid);
+ Addr faultaddr;
+ Int sigNo = siginfo->si_signo;
+ struct vg_sig_private *priv;
+
+ /* Stack must be 8-byte aligned */
+ sp_top_of_frame &= ~0xf;
+
+ if (flags & VKI_SA_SIGINFO)
+ {
+ sp = sp_top_of_frame - sizeof(struct rt_sigframe);
+ }
+ else
+ {
+ sp = sp_top_of_frame - sizeof(struct sigframe);
+ }
+
+ tst = VG_(get_ThreadState)(tid);
+ if (!extend(tst, sp, sp_top_of_frame - sp))
+ return;
+
+ vg_assert(VG_IS_8_ALIGNED(sp));
+
+ /* SIGILL defines addr to be the faulting address */
+
+ faultaddr = (Addr)siginfo->_sifields._sigfault._addr;
+ if (sigNo == VKI_SIGILL && siginfo->si_code > 0)
+ faultaddr = tst->arch.vex.guest_PC;
+
+ if (flags & VKI_SA_SIGINFO)
+ {
+ struct rt_sigframe *frame = (struct rt_sigframe *) sp;
+ struct vki_ucontext *ucp = &frame->rs_uc;
+ if (VG_(clo_trace_signals))
+ VG_(printf)("rt_sigframe\n");
+ /* Create siginfo. */
+ VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal frame siginfo",
+ (Addr)&frame->rs_info, sizeof(frame->rs_info) );
+
+ VG_(memcpy)(&frame->rs_info, siginfo, sizeof(*siginfo));
+
+ VG_TRACK( post_mem_write, Vg_CoreSignal, tid,
+ (Addr)&frame->rs_info, sizeof(frame->rs_info) );
+
+ /* Create the ucontext. */
+ VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal frame ucontext",
+ (Addr)ucp, offsetof(struct vki_ucontext, uc_mcontext) );
+
+ ucp->uc_flags = 0;
+ ucp->uc_link = 0;
+ ucp->uc_stack = tst->altstack;
+
+ VG_TRACK( post_mem_write, Vg_CoreSignal, tid, (Addr)ucp,
+ offsetof(struct vki_ucontext, uc_mcontext) );
+
+ struct vki_sigcontext *scp = &(frame->rs_uc.uc_mcontext);
+ setup_sigcontext2(tst, &(scp), siginfo);
+
+ ucp->uc_sigmask = tst->sig_mask;
+
+ priv = &frame->priv;
+
+ /*
+ * Arguments to signal handler:
+ *
+ * a0 = signal number
+ * a1 = 0 (should be cause)
+ * a2 = pointer to ucontext
+ *
+ * $25 and c0_epc point to the signal handler, $29 points to
+ * the struct rt_sigframe.
+ */
+
+ tst->arch.vex.guest_r4 = siginfo->si_signo;
+ tst->arch.vex.guest_r5 = (Addr) &frame->rs_info;
+ tst->arch.vex.guest_r6 = (Addr) &frame->rs_uc;
+ tst->arch.vex.guest_r29 = (Addr) frame;
+ tst->arch.vex.guest_r25 = (Addr) handler;
+
+ if (flags & VKI_SA_RESTORER)
+ {
+ tst->arch.vex.guest_r31 = (Addr) restorer;
+ }
+ else
+ {
+ tst->arch.vex.guest_r31 = (Addr)&VG_(mips32_linux_SUBST_FOR_rt_sigreturn);
+ }
+
+ }
+ else
+ {
+ if (VG_(clo_trace_signals))
+ VG_(printf)("sigframe\n");
+ struct sigframe *frame = (struct sigframe *) sp;
+ struct vki_sigcontext *scp = &(frame->sf_sc);
+ setup_sigcontext2(tst, &(scp), siginfo);
+ frame->sf_mask = tst->sig_mask;
+ priv = &frame->priv;
+ /*
+ * Arguments to signal handler:
+ *
+ * a0 = signal number
+ * a1 = 0 (should be cause)
+ * a2 = pointer to struct sigcontext
+ *
+ * $25 and c0_epc point to the signal handler, $29 points to the
+ * struct sigframe.
+ */
+ tst->arch.vex.guest_r4 = siginfo->si_signo;
+ tst->arch.vex.guest_r5 = 0;
+ tst->arch.vex.guest_r6 = (Addr) &frame->sf_sc;
+ tst->arch.vex.guest_r29 = (Addr) frame;
+ tst->arch.vex.guest_r25 = (Addr) handler;
+
+ if (flags & VKI_SA_RESTORER)
+ {
+ tst->arch.vex.guest_r31 = (Addr) restorer;
+ }
+ else
+ {
+ tst->arch.vex.guest_r31 = (Addr)&VG_(mips32_linux_SUBST_FOR_sigreturn);
+ }
+ }
+
+ priv->magicPI = 0x31415927;
+ priv->sigNo_private = sigNo;
+ priv->vex_shadow1 = tst->arch.vex_shadow1;
+ priv->vex_shadow2 = tst->arch.vex_shadow2;
+ /* Set the thread so it will next run the handler. */
+ /* tst->m_sp = sp; also notify the tool we've updated SP */
+ VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR, sizeof(Addr));
+ if (VG_(clo_trace_signals))
+ VG_(printf)("handler = %p\n", handler);
+ tst->arch.vex.guest_PC = (Addr) handler;
+ /* This thread needs to be marked runnable, but we leave that the
+ caller to do. */
+}
+
+/* EXPORTED */
+void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
+{
+ ThreadState *tst;
+ struct vg_sig_private *priv1;
+ Addr sp;
+ UInt frame_size;
+ struct vki_sigcontext *mc;
+ Int sigNo;
+ Bool has_siginfo = isRT;
+
+ vg_assert(VG_(is_valid_tid)(tid));
+ tst = VG_(get_ThreadState)(tid);
+ sp = tst->arch.vex.guest_r29;
+ if (has_siginfo)
+ {
+ struct rt_sigframe *frame = (struct rt_sigframe *)sp;
+ struct vki_ucontext *ucp = &frame->rs_uc;
+ frame_size = sizeof(*frame);
+ mc = &ucp->uc_mcontext;
+ priv1 = &frame->priv;
+ vg_assert(priv1->magicPI == 0x31415927);
+ sigNo = priv1->sigNo_private;
+ }
+ else
+ {
+ struct sigframe *frame = (struct sigframe *)sp;
+ frame_size = sizeof(*frame);
+ mc = &(frame->sf_sc);
+ priv1 = &frame->priv;
+ vg_assert(priv1->magicPI == 0x31415927);
+ tst->sig_mask = frame->sf_mask;
+ tst->tmp_sig_mask = tst->sig_mask;
+ sigNo = priv1->sigNo_private;
+ }
+ //restore regs
+ tst->arch.vex.guest_r1 = mc->sc_regs[1];
+ tst->arch.vex.guest_r2 = mc->sc_regs[2];
+ tst->arch.vex.guest_r3 = mc->sc_regs[3];
+ tst->arch.vex.guest_r4 = mc->sc_regs[4];
+ tst->arch.vex.guest_r5 = mc->sc_regs[5];
+ tst->arch.vex.guest_r6 = mc->sc_regs[6];
+ tst->arch.vex.guest_r7 = mc->sc_regs[7];
+ tst->arch.vex.guest_r8 = mc->sc_regs[8];
+ tst->arch.vex.guest_r9 = mc->sc_regs[9];
+ tst->arch.vex.guest_r10 = mc->sc_regs[10];
+ tst->arch.vex.guest_r11 = mc->sc_regs[11];
+ tst->arch.vex.guest_r12 = mc->sc_regs[12];
+ tst->arch.vex.guest_r13= mc->sc_regs[13];
+ tst->arch.vex.guest_r14 = mc->sc_regs[14];
+ tst->arch.vex.guest_r15 = mc->sc_regs[15];
+ tst->arch.vex.guest_r16 = mc->sc_regs[16];
+ tst->arch.vex.guest_r17 = mc->sc_regs[17];
+ tst->arch.vex.guest_r18 = mc->sc_regs[18];
+ tst->arch.vex.guest_r19 = mc->sc_regs[19];
+ tst->arch.vex.guest_r20 = mc->sc_regs[20];
+ tst->arch.vex.guest_r21 = mc->sc_regs[21];
+ tst->arch.vex.guest_r22 = mc->sc_regs[22];
+ tst->arch.vex.guest_r23 = mc->sc_regs[23];
+ tst->arch.vex.guest_r24 = mc->sc_regs[24];
+ tst->arch.vex.guest_r25 = mc->sc_regs[25];
+ tst->arch.vex.guest_r26 = mc->sc_regs[26];
+ tst->arch.vex.guest_r27 = mc->sc_regs[27];
+ tst->arch.vex.guest_r28 = mc->sc_regs[28];
+ tst->arch.vex.guest_r30 = mc->sc_regs[30];
+ tst->arch.vex.guest_PC = mc->sc_pc;
+ tst->arch.vex.guest_r31 = mc->sc_regs[31];
+ tst->arch.vex.guest_r29 = mc->sc_regs[29];
+
+ tst->arch.vex.guest_HI = mc->sc_mdhi;
+ tst->arch.vex.guest_LO = mc->sc_mdlo;
+ tst->arch.vex_shadow1 = priv1->vex_shadow1;
+ tst->arch.vex_shadow2 = priv1->vex_shadow2;
+
+ VG_TRACK(die_mem_stack_signal, sp, frame_size);
+ if (VG_(clo_trace_signals))
+ VG_(message)( Vg_DebugMsg,
+ "VG_(signal_return) (thread %d): isRT=%d valid magic; EIP=%#x\n",
+ tid, isRT, tst->arch.vex.guest_PC);
+ /* tell the tools */
+ VG_TRACK( post_deliver_signal, tid, sigNo );
+}
+
+#endif // defined(VGP_mips32_linux)
+
+/*--------------------------------------------------------------------*/
+/*--- end sigframe-mips32-linux.c ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_sigframe/sigframe-ppc32-linux.c b/main/coregrind/m_sigframe/sigframe-ppc32-linux.c
index 736ce4f..5fa3686 100644
--- a/main/coregrind/m_sigframe/sigframe-ppc32-linux.c
+++ b/main/coregrind/m_sigframe/sigframe-ppc32-linux.c
@@ -8,9 +8,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2004-2011 Paul Mackerras
+ Copyright (C) 2004-2012 Paul Mackerras
paulus@samba.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_sigframe/sigframe-ppc64-linux.c b/main/coregrind/m_sigframe/sigframe-ppc64-linux.c
index 44bb269..d1bb91a 100644
--- a/main/coregrind/m_sigframe/sigframe-ppc64-linux.c
+++ b/main/coregrind/m_sigframe/sigframe-ppc64-linux.c
@@ -8,9 +8,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2004-2011 Paul Mackerras
+ Copyright (C) 2004-2012 Paul Mackerras
paulus@samba.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_sigframe/sigframe-s390x-linux.c b/main/coregrind/m_sigframe/sigframe-s390x-linux.c
index 9d3afca..1c703fe 100644
--- a/main/coregrind/m_sigframe/sigframe-s390x-linux.c
+++ b/main/coregrind/m_sigframe/sigframe-s390x-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/coregrind/m_sigframe/sigframe-x86-darwin.c b/main/coregrind/m_sigframe/sigframe-x86-darwin.c
index 79dd413..adcbd0e 100644
--- a/main/coregrind/m_sigframe/sigframe-x86-darwin.c
+++ b/main/coregrind/m_sigframe/sigframe-x86-darwin.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2011 OpenWorks Ltd
+ Copyright (C) 2006-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -127,12 +127,14 @@
sp_top_of_frame &= ~0xf;
esp = sp_top_of_frame - sizeof(struct hacky_sigframe);
+ esp -= 4; /* ELF ABI says that esp+4 must be 16 aligned on
+ entry to a function. */
tst = VG_(get_ThreadState)(tid);
if (!extend(tst, esp, sp_top_of_frame - esp))
return;
- vg_assert(VG_IS_16_ALIGNED(esp));
+ vg_assert(VG_IS_16_ALIGNED(esp+4));
frame = (struct hacky_sigframe *) esp;
@@ -182,7 +184,8 @@
if (VG_(clo_trace_signals))
VG_(message)(Vg_DebugMsg,
- "sigframe_create (thread %d): next EIP=%#lx, next ESP=%#lx",
+ "sigframe_create (thread %d): "
+ "next EIP=%#lx, next ESP=%#lx\n",
tid, (Addr)handler, (Addr)frame );
}
@@ -203,11 +206,14 @@
esp = VG_(get_SP)(tid);
/* why -4 ? because the signal handler's return will have popped
- the return address of the stack; and the return address is the
+ the return address off the stack; and the return address is the
lowest-addressed element of hacky_sigframe. */
frame = (struct hacky_sigframe*)(esp - 4);
vg_assert(frame->magicPI == 0x31415927);
- vg_assert(VG_IS_16_ALIGNED(frame));
+
+ /* This +8 is because of the -4 referred to in the ELF ABI comment
+ in VG_(sigframe_create) just above. */
+ vg_assert(VG_IS_16_ALIGNED((Addr)frame + 4));
/* restore the entire guest state, and shadows, from the
frame. Note, as per comments above, this is a kludge - should
@@ -221,7 +227,8 @@
if (VG_(clo_trace_signals))
VG_(message)(Vg_DebugMsg,
- "sigframe_destroy (thread %d): valid magic; next EIP=%#x",
+ "sigframe_destroy (thread %d): "
+ "valid magic; next EIP=%#x\n",
tid, tst->arch.vex.guest_EIP);
VG_TRACK( die_mem_stack_signal,
diff --git a/main/coregrind/m_sigframe/sigframe-x86-linux.c b/main/coregrind/m_sigframe/sigframe-x86-linux.c
index b931e5f..0551f21 100644
--- a/main/coregrind/m_sigframe/sigframe-x86-linux.c
+++ b/main/coregrind/m_sigframe/sigframe-x86-linux.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_signals.c b/main/coregrind/m_signals.c
index fa2a124..368c149 100644
--- a/main/coregrind/m_signals.c
+++ b/main/coregrind/m_signals.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -240,8 +240,6 @@
static void sigvgkill_handler ( Int sigNo, vki_siginfo_t *info,
struct vki_ucontext * );
-static const Char *signame(Int sigNo);
-
/* Maximum usable signal. */
Int VG_(max_signal) = _VKI_NSIG;
@@ -449,19 +447,57 @@
#elif defined(VGP_amd64_darwin)
static inline Addr VG_UCONTEXT_INSTR_PTR( void* ucV ) {
- I_die_here;
+ ucontext_t* uc = (ucontext_t*)ucV;
+ struct __darwin_mcontext64* mc = uc->uc_mcontext;
+ struct __darwin_x86_thread_state64* ss = &mc->__ss;
+ return ss->__rip;
}
static inline Addr VG_UCONTEXT_STACK_PTR( void* ucV ) {
- I_die_here;
+ ucontext_t* uc = (ucontext_t*)ucV;
+ struct __darwin_mcontext64* mc = uc->uc_mcontext;
+ struct __darwin_x86_thread_state64* ss = &mc->__ss;
+ return ss->__rsp;
}
static inline SysRes VG_UCONTEXT_SYSCALL_SYSRES( void* ucV,
UWord scclass ) {
- I_die_here;
+ /* This is copied from the x86-darwin case. I'm not sure if it
+ is correct. */
+ ucontext_t* uc = (ucontext_t*)ucV;
+ struct __darwin_mcontext64* mc = uc->uc_mcontext;
+ struct __darwin_x86_thread_state64* ss = &mc->__ss;
+ /* duplicates logic in m_syswrap.getSyscallStatusFromGuestState */
+ ULong carry = 1 & ss->__rflags;
+ ULong err = 0;
+ ULong wLO = 0;
+ ULong wHI = 0;
+ switch (scclass) {
+ case VG_DARWIN_SYSCALL_CLASS_UNIX:
+ err = carry;
+ wLO = ss->__rax;
+ wHI = ss->__rdx;
+ break;
+ case VG_DARWIN_SYSCALL_CLASS_MACH:
+ wLO = ss->__rax;
+ break;
+ case VG_DARWIN_SYSCALL_CLASS_MDEP:
+ wLO = ss->__rax;
+ break;
+ default:
+ vg_assert(0);
+ break;
+ }
+ return VG_(mk_SysRes_amd64_darwin)( scclass, err ? True : False,
+ wHI, wLO );
}
static inline
void VG_UCONTEXT_TO_UnwindStartRegs( UnwindStartRegs* srP,
void* ucV ) {
- I_die_here;
+ ucontext_t* uc = (ucontext_t*)ucV;
+ struct __darwin_mcontext64* mc = uc->uc_mcontext;
+ struct __darwin_x86_thread_state64* ss = &mc->__ss;
+ srP->r_pc = (ULong)(ss->__rip);
+ srP->r_sp = (ULong)(ss->__rsp);
+ srP->misc.AMD64.r_rbp = (ULong)(ss->__rbp);
}
#elif defined(VGP_s390x_linux)
@@ -480,6 +516,25 @@
(srP)->misc.S390X.r_lr = (uc)->uc_mcontext.regs.gprs[14]; \
}
+#elif defined(VGP_mips32_linux)
+# define VG_UCONTEXT_INSTR_PTR(uc) ((UWord)(((uc)->uc_mcontext.sc_pc)))
+# define VG_UCONTEXT_STACK_PTR(uc) ((UWord)((uc)->uc_mcontext.sc_regs[29]))
+# define VG_UCONTEXT_FRAME_PTR(uc) ((uc)->uc_mcontext.sc_regs[30])
+# define VG_UCONTEXT_SYSCALL_NUM(uc) ((uc)->uc_mcontext.sc_regs[2])
+# define VG_UCONTEXT_SYSCALL_SYSRES(uc) \
+ /* Convert the value in uc_mcontext.rax into a SysRes. */ \
+ VG_(mk_SysRes_mips32_linux)( (uc)->uc_mcontext.sc_regs[2], \
+ (uc)->uc_mcontext.sc_regs[3], \
+ (uc)->uc_mcontext.sc_regs[7])
+
+# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \
+ { (srP)->r_pc = (uc)->uc_mcontext.sc_pc; \
+ (srP)->r_sp = (uc)->uc_mcontext.sc_regs[29]; \
+ (srP)->misc.MIPS32.r30 = (uc)->uc_mcontext.sc_regs[30]; \
+ (srP)->misc.MIPS32.r31 = (uc)->uc_mcontext.sc_regs[31]; \
+ (srP)->misc.MIPS32.r28 = (uc)->uc_mcontext.sc_regs[28]; \
+ }
+
#else
# error Unknown platform
@@ -741,6 +796,7 @@
#if defined(VGP_x86_linux)
# define _MY_SIGRETURN(name) \
".text\n" \
+ ".globl my_sigreturn\n" \
"my_sigreturn:\n" \
" movl $" #name ", %eax\n" \
" int $0x80\n" \
@@ -749,6 +805,7 @@
#elif defined(VGP_amd64_linux)
# define _MY_SIGRETURN(name) \
".text\n" \
+ ".globl my_sigreturn\n" \
"my_sigreturn:\n" \
" movq $" #name ", %rax\n" \
" syscall\n" \
@@ -757,6 +814,7 @@
#elif defined(VGP_ppc32_linux)
# define _MY_SIGRETURN(name) \
".text\n" \
+ ".globl my_sigreturn\n" \
"my_sigreturn:\n" \
" li 0, " #name "\n" \
" sc\n" \
@@ -780,6 +838,7 @@
#elif defined(VGP_arm_linux)
# define _MY_SIGRETURN(name) \
".text\n" \
+ ".globl my_sigreturn\n" \
"my_sigreturn:\n\t" \
" mov r7, #" #name "\n\t" \
" svc 0x00000000\n" \
@@ -788,6 +847,7 @@
#elif defined(VGP_x86_darwin)
# define _MY_SIGRETURN(name) \
".text\n" \
+ ".globl my_sigreturn\n" \
"my_sigreturn:\n" \
"movl $" VG_STRINGIFY(__NR_DARWIN_FAKE_SIGRETURN) ",%eax\n" \
"int $0x80"
@@ -796,16 +856,26 @@
// DDD: todo
# define _MY_SIGRETURN(name) \
".text\n" \
+ ".globl my_sigreturn\n" \
"my_sigreturn:\n" \
"ud2\n"
#elif defined(VGP_s390x_linux)
# define _MY_SIGRETURN(name) \
".text\n" \
+ ".globl my_sigreturn\n" \
"my_sigreturn:\n" \
" svc " #name "\n" \
".previous\n"
+#elif defined(VGP_mips32_linux)
+# define _MY_SIGRETURN(name) \
+ ".text\n" \
+ "my_sigreturn:\n" \
+ " li $2, " #name "\n" /* apparently $2 is v0 */ \
+ " syscall\n" \
+ ".previous\n"
+
#else
# error Unknown platform
#endif
@@ -848,7 +918,8 @@
ksa.ksa_handler = skss.skss_per_sig[sig].skss_handler;
ksa.sa_flags = skss.skss_per_sig[sig].skss_flags;
# if !defined(VGP_ppc32_linux) && \
- !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin)
+ !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin) && \
+ !defined(VGP_mips32_linux)
ksa.sa_restorer = my_sigreturn;
# endif
/* Re above ifdef (also the assertion below), PaulM says:
@@ -881,7 +952,8 @@
vg_assert(ksa_old.sa_flags
== skss_old.skss_per_sig[sig].skss_flags);
# if !defined(VGP_ppc32_linux) && \
- !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin)
+ !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin) && \
+ !defined(VGP_mips32_linux)
vg_assert(ksa_old.sa_restorer
== my_sigreturn);
# endif
@@ -1042,18 +1114,18 @@
bad_signo_reserved:
if (VG_(showing_core_errors)() && !VG_(clo_xml)) {
VG_(umsg)("Warning: ignored attempt to set %s handler in sigaction();\n",
- signame(signo));
+ VG_(signame)(signo));
VG_(umsg)(" the %s signal is used internally by Valgrind\n",
- signame(signo));
+ VG_(signame)(signo));
}
return VG_(mk_SysRes_Error)( VKI_EINVAL );
bad_sigkill_or_sigstop:
if (VG_(showing_core_errors)() && !VG_(clo_xml)) {
VG_(umsg)("Warning: ignored attempt to set %s handler in sigaction();\n",
- signame(signo));
+ VG_(signame)(signo));
VG_(umsg)(" the %s signal is uncatchable\n",
- signame(signo));
+ VG_(signame)(signo));
}
return VG_(mk_SysRes_Error)( VKI_EINVAL );
}
@@ -1234,7 +1306,7 @@
if (VG_(clo_trace_signals))
VG_(dmsg)("delivering signal %d (%s) to thread %d: "
"on ALT STACK (%p-%p; %ld bytes)\n",
- sigNo, signame(sigNo), tid, tst->altstack.ss_sp,
+ sigNo, VG_(signame)(sigNo), tid, tst->altstack.ss_sp,
(UChar *)tst->altstack.ss_sp + tst->altstack.ss_size,
(Word)tst->altstack.ss_size );
@@ -1262,7 +1334,7 @@
}
-static const Char *signame(Int sigNo)
+const Char *VG_(signame)(Int sigNo)
{
static Char buf[20];
@@ -1486,7 +1558,7 @@
VG_(umsg)(
"\n"
"Process terminating with default action of signal %d (%s)%s\n",
- sigNo, signame(sigNo), core ? ": dumping core" : "");
+ sigNo, VG_(signame)(sigNo), core ? ": dumping core" : "");
/* Be helpful - decode some more details about this fault */
if (is_signal_from_kernel(tid, sigNo, info->si_code)) {
@@ -1566,10 +1638,45 @@
obviously stupid place (not mapped readable) that would
likely cause a segfault. */
if (VG_(is_valid_tid)(tid)) {
+ Word first_ip_delta = 0;
+#if defined(VGO_linux)
+ /* Make sure that the address stored in the stack pointer is
+ located in a mapped page. That is not necessarily so. E.g.
+ consider the scenario where the stack pointer was decreased
+ and now has a value that is just below the end of a page that has
+ not been mapped yet. In that case VG_(am_is_valid_for_client)
+ will consider the address of the stack pointer invalid and that
+ would cause a back-trace of depth 1 to be printed, instead of a
+ full back-trace. */
+ if (tid == 1) { // main thread
+ Addr esp = VG_(get_SP)(tid);
+ Addr base = VG_PGROUNDDN(esp - VG_STACK_REDZONE_SZB);
+ if (VG_(extend_stack)(base, VG_(threads)[tid].client_stack_szB)) {
+ if (VG_(clo_trace_signals))
+ VG_(dmsg)(" -> extended stack base to %#lx\n",
+ VG_PGROUNDDN(esp));
+ }
+ }
+#endif
+#if defined(VGA_s390x)
+ if (sigNo == VKI_SIGILL) {
+ /* The guest instruction address has been adjusted earlier to
+ point to the insn following the one that could not be decoded.
+ When printing the back-trace here we need to undo that
+ adjustment so the first line in the back-trace reports the
+ correct address. */
+ Addr addr = (Addr)info->VKI_SIGINFO_si_addr;
+ UChar byte = ((UChar *)addr)[0];
+ Int insn_length = ((((byte >> 6) + 1) >> 1) + 1) << 1;
+
+ first_ip_delta = -insn_length;
+ }
+#endif
ExeContext* ec = VG_(am_is_valid_for_client)
(VG_(get_SP)(tid), sizeof(Addr), VKI_PROT_READ)
- ? VG_(record_ExeContext)( tid, 0/*first_ip_delta*/ )
- : VG_(record_depth_1_ExeContext)( tid );
+ ? VG_(record_ExeContext)( tid, first_ip_delta )
+ : VG_(record_depth_1_ExeContext)( tid,
+ first_ip_delta );
vg_assert(ec);
VG_(pp_ExeContext)( ec );
}
@@ -1631,7 +1738,7 @@
if (VG_(clo_trace_signals))
VG_(dmsg)("delivering signal %d (%s):%d to thread %d\n",
- sigNo, signame(sigNo), info->si_code, tid );
+ sigNo, VG_(signame)(sigNo), info->si_code, tid );
if (sigNo == VG_SIGVGKILL) {
/* If this is a SIGVGKILL, we're expecting it to interrupt any
@@ -1812,6 +1919,27 @@
info.si_signo = VKI_SIGTRAP;
info.si_code = VKI_TRAP_BRKPT; /* tjh: only ever called for a brkpt ins */
+# if defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
+ /* This is for teq on mips. Teq on mips for ins: 0xXXX1f4
+ * cases VKI_SIGFPE not VKI_SIGTRAP
+ */
+ // JRS 2012-Jun-06: commented out until we know we need it
+ // This isn't a clean solution; need something that avoids looking
+ // at the guest code.
+ //UInt *ins = (void*)(vgPlain_threads[tid].arch.vex.guest_PC-4);
+ //UInt tcode = (((*ins) >> 6) & ((1 << 10) - 1));
+ //if (tcode == VKI_BRK_OVERFLOW || tcode == VKI_BRK_DIVZERO) {
+ // if (tcode == VKI_BRK_DIVZERO)
+ // info.si_code = VKI_FPE_INTDIV;
+ // else
+ // info.si_code = VKI_FPE_INTOVF;
+ // info.si_signo = VKI_SIGFPE;
+ // info.si_errno = 0;
+ // info.VKI_SIGINFO_si_addr
+ // = (void*)(vgPlain_threads[tid].arch.vex.guest_PC-4);
+ //}
+# endif
+
# if defined(VGP_x86_linux) || defined(VGP_amd64_linux)
uc.uc_mcontext.trapno = 3; /* tjh: this is the x86 trap number
for a breakpoint trap... */
@@ -2148,7 +2276,7 @@
signal and what we should do about it, we really can't
continue unless we get it. */
VG_(umsg)("Signal %d (%s) appears to have lost its siginfo; "
- "I can't go on.\n", sigNo, signame(sigNo));
+ "I can't go on.\n", sigNo, VG_(signame)(sigNo));
VG_(printf)(
" This may be because one of your programs has consumed your ration of\n"
" siginfo structures. For more information, see:\n"
@@ -2300,7 +2428,7 @@
*/
VG_(dmsg)("VALGRIND INTERNAL ERROR: Valgrind received "
"a signal %d (%s) - exiting\n",
- sigNo, signame(sigNo));
+ sigNo, VG_(signame)(sigNo));
VG_(dmsg)("si_code=%x; Faulting address: %p; sp: %#lx\n",
info->si_code, info->VKI_SIGINFO_si_addr,
diff --git a/main/coregrind/m_sparsewa.c b/main/coregrind/m_sparsewa.c
index 13bdd18..56cef89 100644
--- a/main/coregrind/m_sparsewa.c
+++ b/main/coregrind/m_sparsewa.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks Ltd
+ Copyright (C) 2008-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -435,33 +435,21 @@
static UWord swa_sizeSWA_wrk ( void* nd )
{
Int i;
- UWord sum = 0;
if (*(UWord*)nd == LevelN_MAGIC) {
+ UWord sum = 0;
LevelN* levelN = (LevelN*)nd;
for (i = 0; i < 256; i++) {
if (levelN->child[i]) {
sum += swa_sizeSWA_wrk( levelN->child[i] );
}
- }
+ }
+ return sum;
} else {
Level0* level0;
vg_assert(*(UWord*)nd == Level0_MAGIC);
level0 = (Level0*)nd;
- for (i = 0; i < 256/8; i += 2) {
- UWord x = level0->inUse[i+0]; /* assume zero-extend */
- UWord y = level0->inUse[i+1]; /* assume zero-extend */
- /* do 'sum += popcount(x) + popcount(y)' for byte-sized x, y */
- /* unroll the loop twice so as to expose more ILP */
- x = (x & 0x55) + ((x >> 1) & 0x55);
- y = (y & 0x55) + ((y >> 1) & 0x55);
- x = (x & 0x33) + ((x >> 2) & 0x33);
- y = (y & 0x33) + ((y >> 2) & 0x33);
- x = (x & 0x0F) + ((x >> 4) & 0x0F);
- y = (y & 0x0F) + ((y >> 4) & 0x0F);
- sum += x + y;
- }
+ return level0->nInUse;
}
- return sum;
}
UWord VG_(sizeSWA) ( SparseWA* swa )
{
diff --git a/main/coregrind/m_stacks.c b/main/coregrind/m_stacks.c
index 0014b60..000aaa9 100644
--- a/main/coregrind/m_stacks.c
+++ b/main/coregrind/m_stacks.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_stacktrace.c b/main/coregrind/m_stacktrace.c
index ed337cf..fcbb230 100644
--- a/main/coregrind/m_stacktrace.c
+++ b/main/coregrind/m_stacktrace.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -253,14 +253,6 @@
if (fp_max >= sizeof(Addr))
fp_max -= sizeof(Addr);
- extern unsigned long nacl_head;
-
- if (nacl_head && uregs.xip > nacl_head && uregs.xip < nacl_head + (1ULL << 32)) {
- fp_min = nacl_head + 0x10000;
- fp_max = nacl_head + (1ULL << 32) - 1;
- }
-
-
if (debug)
VG_(printf)("max_n_ips=%d fp_min=0x%lx fp_max_orig=0x%lx, "
"fp_max=0x%lx ip=0x%lx fp=0x%lx\n",
@@ -583,6 +575,87 @@
#if defined(VGP_arm_linux)
+static Bool in_same_fn ( Addr a1, Addr a2 )
+{
+# define M_VG_ERRTXT 500
+ UChar buf_a1[M_VG_ERRTXT], buf_a2[M_VG_ERRTXT];
+ /* The following conditional looks grossly inefficient and
+ surely could be majorly improved, with not much effort. */
+ if (VG_(get_fnname_raw) (a1, buf_a1, M_VG_ERRTXT))
+ if (VG_(get_fnname_raw) (a2, buf_a2, M_VG_ERRTXT))
+ if (VG_(strncmp)(buf_a1, buf_a2, M_VG_ERRTXT))
+ return True;
+# undef M_VG_ERRTXT
+ return False;
+}
+
+static Bool in_same_page ( Addr a1, Addr a2 ) {
+ return (a1 & ~0xFFF) == (a2 & ~0xFFF);
+}
+
+static Addr abs_diff ( Addr a1, Addr a2 ) {
+ return (Addr)(a1 > a2 ? a1 - a2 : a2 - a1);
+}
+
+static Bool has_XT_perms ( Addr a )
+{
+ NSegment const* seg = VG_(am_find_nsegment)(a);
+ return seg && seg->hasX && seg->hasT;
+}
+
+static Bool looks_like_Thumb_call32 ( UShort w0, UShort w1 )
+{
+ if (0)
+ VG_(printf)("isT32call %04x %04x\n", (UInt)w0, (UInt)w1);
+ // BL simm26
+ if ((w0 & 0xF800) == 0xF000 && (w1 & 0xC000) == 0xC000) return True;
+ // BLX simm26
+ if ((w0 & 0xF800) == 0xF000 && (w1 & 0xC000) == 0xC000) return True;
+ return False;
+}
+
+static Bool looks_like_Thumb_call16 ( UShort w0 )
+{
+ return False;
+}
+
+static Bool looks_like_ARM_call ( UInt a0 )
+{
+ if (0)
+ VG_(printf)("isA32call %08x\n", a0);
+ // Leading E forces unconditional only -- fix
+ if ((a0 & 0xFF000000) == 0xEB000000) return True;
+ return False;
+}
+
+static Bool looks_like_RA ( Addr ra )
+{
+ /* 'ra' is a plausible return address if it points to
+ an instruction after a call insn. */
+ Bool isT = (ra & 1);
+ if (isT) {
+ // returning to Thumb code
+ ra &= ~1;
+ ra -= 4;
+ if (has_XT_perms(ra)) {
+ UShort w0 = *(UShort*)ra;
+ UShort w1 = in_same_page(ra, ra+2) ? *(UShort*)(ra+2) : 0;
+ if (looks_like_Thumb_call16(w1) || looks_like_Thumb_call32(w0,w1))
+ return True;
+ }
+ } else {
+ // ARM
+ ra &= ~3;
+ ra -= 4;
+ if (has_XT_perms(ra)) {
+ UInt a0 = *(UInt*)ra;
+ if (looks_like_ARM_call(a0))
+ return True;
+ }
+ }
+ return False;
+}
+
UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
/*OUT*/Addr* ips, UInt max_n_ips,
/*OUT*/Addr* sps, /*OUT*/Addr* fps,
@@ -645,6 +718,7 @@
i = 1;
/* Loop unwinding the stack. */
+ Bool do_stack_scan = False;
while (True) {
if (debug) {
@@ -666,9 +740,48 @@
continue;
}
/* No luck. We have to give up. */
+ do_stack_scan = True;
break;
}
+ if (0/*DISABLED BY DEFAULT*/ && do_stack_scan && i < max_n_ips && i <= 2) {
+ Int nByStackScan = 0;
+ Addr lr = uregs.r14;
+ Addr sp = uregs.r13 & ~3;
+ Addr pc = uregs.r15;
+ // First see if LR contains
+ // something that could be a valid return address.
+ if (!in_same_fn(lr, pc) && looks_like_RA(lr)) {
+ // take it only if 'cand' isn't obviously a duplicate
+ // of the last found IP value
+ Addr cand = (lr & 0xFFFFFFFE) - 1;
+ if (abs_diff(cand, ips[i-1]) > 1) {
+ if (sps) sps[i] = 0;
+ if (fps) fps[i] = 0;
+ ips[i++] = cand;
+ nByStackScan++;
+ }
+ }
+ while (in_same_page(sp, uregs.r13)) {
+ if (i >= max_n_ips)
+ break;
+ // we're in the same page; fairly safe to keep going
+ UWord w = *(UWord*)(sp & ~0x3);
+ if (looks_like_RA(w)) {
+ Addr cand = (w & 0xFFFFFFFE) - 1;
+ // take it only if 'cand' isn't obviously a duplicate
+ // of the last found IP value
+ if (abs_diff(cand, ips[i-1]) > 1) {
+ if (sps) sps[i] = 0;
+ if (fps) fps[i] = 0;
+ ips[i++] = cand;
+ if (++nByStackScan >= 5) break;
+ }
+ }
+ sp += 4;
+ }
+ }
+
n_found = i;
return n_found;
}
@@ -676,7 +789,9 @@
#endif
/* ------------------------ s390x ------------------------- */
+
#if defined(VGP_s390x_linux)
+
UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
/*OUT*/Addr* ips, UInt max_n_ips,
/*OUT*/Addr* sps, /*OUT*/Addr* fps,
@@ -752,8 +867,157 @@
n_found = i;
return n_found;
}
+
#endif
+/* ------------------------ mips 32------------------------- */
+
+#if defined(VGP_mips32_linux)
+
+UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
+ /*OUT*/Addr* ips, UInt max_n_ips,
+ /*OUT*/Addr* sps, /*OUT*/Addr* fps,
+ UnwindStartRegs* startRegs,
+ Addr fp_max_orig )
+{
+ Bool debug = False;
+ Int i;
+ Addr fp_max;
+ UInt n_found = 0;
+
+ vg_assert(sizeof(Addr) == sizeof(UWord));
+ vg_assert(sizeof(Addr) == sizeof(void*));
+
+ D3UnwindRegs uregs;
+ uregs.pc = startRegs->r_pc;
+ uregs.sp = startRegs->r_sp;
+ Addr fp_min = uregs.sp;
+
+ uregs.fp = startRegs->misc.MIPS32.r30;
+ uregs.ra = startRegs->misc.MIPS32.r31;
+
+ /* Snaffle IPs from the client's stack into ips[0 .. max_n_ips-1],
+ stopping when the trail goes cold, which we guess to be
+ when FP is not a reasonable stack location. */
+
+ fp_max = VG_PGROUNDUP(fp_max_orig);
+ if (fp_max >= sizeof(Addr))
+ fp_max -= sizeof(Addr);
+
+ if (debug)
+ VG_(printf)("max_n_ips=%d fp_min=0x%lx fp_max_orig=0x%lx, "
+ "fp_max=0x%lx pc=0x%lx sp=0x%lx fp=0x%lx\n",
+ max_n_ips, fp_min, fp_max_orig, fp_max,
+ uregs.pc, uregs.sp, uregs.fp);
+
+ if (sps) sps[0] = uregs.sp;
+ if (fps) fps[0] = uregs.fp;
+ ips[0] = uregs.pc;
+ i = 1;
+
+ /* Loop unwinding the stack. */
+
+ while (True) {
+ if (debug) {
+ VG_(printf)("i: %d, pc: 0x%lx, sp: 0x%lx, ra: 0x%lx\n",
+ i, uregs.pc, uregs.sp, uregs.ra);
+ }
+ if (i >= max_n_ips)
+ break;
+
+ if (VG_(use_CF_info)( &uregs, fp_min, fp_max )) {
+ if (debug)
+ VG_(printf)("USING CFI: pc: 0x%lx, sp: 0x%lx, ra: 0x%lx\n",
+ uregs.pc, uregs.sp, uregs.ra);
+ if (0 == uregs.pc || 1 == uregs.pc) break;
+ if (sps) sps[i] = uregs.sp;
+ if (fps) fps[i] = uregs.fp;
+ ips[i++] = uregs.pc - 4;
+ uregs.pc = uregs.pc - 4;
+ continue;
+ }
+
+ int seen_sp_adjust = 0;
+ long frame_offset = 0;
+ PtrdiffT offset;
+ if (VG_(get_inst_offset_in_function)(uregs.pc, &offset)) {
+ Addr start_pc = uregs.pc - offset;
+ Addr limit_pc = uregs.pc;
+ Addr cur_pc;
+ for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += 4) {
+ unsigned long inst, high_word, low_word;
+ unsigned long * cur_inst;
+ int reg;
+ /* Fetch the instruction. */
+ cur_inst = (unsigned long *)cur_pc;
+ inst = *((UInt *) cur_inst);
+ if(debug)
+ VG_(printf)("cur_pc: 0x%lx, inst: 0x%lx\n", cur_pc, inst);
+
+ /* Save some code by pre-extracting some useful fields. */
+ high_word = (inst >> 16) & 0xffff;
+ low_word = inst & 0xffff;
+ reg = high_word & 0x1f;
+
+ if (high_word == 0x27bd /* addiu $sp,$sp,-i */
+ || high_word == 0x23bd /* addi $sp,$sp,-i */
+ || high_word == 0x67bd) { /* daddiu $sp,$sp,-i */
+ if (low_word & 0x8000) /* negative stack adjustment? */
+ frame_offset += 0x10000 - low_word;
+ else
+ /* Exit loop if a positive stack adjustment is found, which
+ usually means that the stack cleanup code in the function
+ epilogue is reached. */
+ break;
+ seen_sp_adjust = 1;
+ }
+ }
+ if(debug)
+ VG_(printf)("offset: 0x%lx\n", frame_offset);
+ }
+ if (seen_sp_adjust) {
+ if (0 == uregs.pc || 1 == uregs.pc) break;
+ if (uregs.pc == uregs.ra - 8) break;
+ if (sps) {
+ sps[i] = uregs.sp + frame_offset;
+ }
+ uregs.sp = uregs.sp + frame_offset;
+
+ if (fps) {
+ fps[i] = fps[0];
+ uregs.fp = fps[0];
+ }
+ if (0 == uregs.ra || 1 == uregs.ra) break;
+ uregs.pc = uregs.ra - 8;
+ ips[i++] = uregs.ra - 8;
+ continue;
+ }
+
+ if (i == 1) {
+ if (sps) {
+ sps[i] = sps[0];
+ uregs.sp = sps[0];
+ }
+ if (fps) {
+ fps[i] = fps[0];
+ uregs.fp = fps[0];
+ }
+ if (0 == uregs.ra || 1 == uregs.ra) break;
+ uregs.pc = uregs.ra - 8;
+ ips[i++] = uregs.ra - 8;
+ continue;
+ }
+ /* No luck. We have to give up. */
+ break;
+ }
+
+ n_found = i;
+ return n_found;
+}
+
+#endif
+
+
/*------------------------------------------------------------*/
/*--- ---*/
/*--- END platform-dependent unwinder worker functions ---*/
diff --git a/main/coregrind/m_start-amd64-darwin.S b/main/coregrind/m_start-amd64-darwin.S
deleted file mode 100644
index e69de29..0000000
--- a/main/coregrind/m_start-amd64-darwin.S
+++ /dev/null
diff --git a/main/coregrind/m_start-x86-darwin.S b/main/coregrind/m_start-x86-darwin.S
deleted file mode 100644
index e69de29..0000000
--- a/main/coregrind/m_start-x86-darwin.S
+++ /dev/null
diff --git a/main/coregrind/m_syscall.c b/main/coregrind/m_syscall.c
index fc06c25..668d08b 100644
--- a/main/coregrind/m_syscall.c
+++ b/main/coregrind/m_syscall.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -62,6 +62,7 @@
SysRes VG_(mk_SysRes_x86_linux) ( Int val ) {
SysRes res;
+ res._valEx = 0; /* unused except on mips-linux */
res._isError = val >= -4095 && val <= -1;
if (res._isError) {
res._val = (UInt)(-val);
@@ -74,6 +75,7 @@
/* Similarly .. */
SysRes VG_(mk_SysRes_amd64_linux) ( Long val ) {
SysRes res;
+ res._valEx = 0; /* unused except on mips-linux */
res._isError = val >= -4095 && val <= -1;
if (res._isError) {
res._val = (ULong)(-val);
@@ -87,6 +89,7 @@
/* Note this must be in the bottom bit of the second arg */
SysRes VG_(mk_SysRes_ppc32_linux) ( UInt val, UInt cr0so ) {
SysRes res;
+ res._valEx = 0; /* unused except on mips-linux */
res._isError = (cr0so & 1) != 0;
res._val = val;
return res;
@@ -95,6 +98,7 @@
/* As per ppc32 version, cr0.so must be in l.s.b. of 2nd arg */
SysRes VG_(mk_SysRes_ppc64_linux) ( ULong val, ULong cr0so ) {
SysRes res;
+ res._valEx = 0; /* unused except on mips-linux */
res._isError = (cr0so & 1) != 0;
res._val = val;
return res;
@@ -102,6 +106,7 @@
SysRes VG_(mk_SysRes_s390x_linux) ( Long val ) {
SysRes res;
+ res._valEx = 0; /* unused except on mips-linux */
res._isError = val >= -4095 && val <= -1;
if (res._isError) {
res._val = -val;
@@ -113,6 +118,7 @@
SysRes VG_(mk_SysRes_arm_linux) ( Int val ) {
SysRes res;
+ res._valEx = 0; /* unused except on mips-linux */
res._isError = val >= -4095 && val <= -1;
if (res._isError) {
res._val = (UInt)(-val);
@@ -122,9 +128,19 @@
return res;
}
+/* MIPS uses a3 != 0 to flag an error */
+SysRes VG_(mk_SysRes_mips32_linux) ( UWord v0, UWord v1, UWord a3 ) {
+ SysRes res;
+ res._isError = (a3 != (UWord)0);
+ res._val = v0;
+ res._valEx = v1;
+ return res;
+}
+
/* Generic constructors. */
SysRes VG_(mk_SysRes_Error) ( UWord err ) {
SysRes r;
+ r._valEx = 0; /* unused except on mips-linux */
r._isError = True;
r._val = err;
return r;
@@ -132,6 +148,7 @@
SysRes VG_(mk_SysRes_Success) ( UWord res ) {
SysRes r;
+ r._valEx = 0; /* unused except on mips-linux */
r._isError = False;
r._val = res;
return r;
@@ -255,6 +272,7 @@
);
asm(
".text\n"
+".globl do_syscall_WRK\n"
"do_syscall_WRK:\n"
" push %esi\n"
" push %edi\n"
@@ -296,6 +314,7 @@
);
asm(
".text\n"
+".globl do_syscall_WRK\n"
"do_syscall_WRK:\n"
/* Convert function calling convention --> syscall calling
convention */
@@ -330,6 +349,7 @@
);
asm(
".text\n"
+".globl do_syscall_WRK\n"
"do_syscall_WRK:\n"
" mr 0,3\n"
" mr 3,4\n"
@@ -396,6 +416,7 @@
);
asm(
".text\n"
+".globl do_syscall_WRK\n"
"do_syscall_WRK:\n"
" push {r4, r5, r7}\n"
" ldr r4, [sp, #12]\n"
@@ -571,6 +592,40 @@
return (UWord) (__svcres);
}
+#elif defined(VGP_mips32_linux)
+/* Incoming args (syscall number + up to 6 args) come in a0 - a3 and stack.
+
+ The syscall number goes in v0. The args are passed to the syscall in
+ the regs a0 - a3 and stack, i.e. the kernel's syscall calling convention.
+
+ (a3 != 0) flags an error.
+ We return the syscall return value in v0.
+ MIPS version
+*/
+extern int do_syscall_WRK (
+ int a1, int a2, int a3,
+ int a4, int a5, int a6, int syscall_no, UWord *err,
+ UWord *valHi, UWord* valLo
+ );
+asm(
+".globl do_syscall_WRK\n"
+".ent do_syscall_WRK\n"
+".text\n"
+"do_syscall_WRK:\n"
+" lw $2, 24($29)\n"
+" syscall\n"
+" lw $8, 28($29)\n"
+" sw $7, ($8)\n"
+" lw $8, 32($29)\n"
+" sw $3, ($8)\n" // store valHi
+" lw $8, 36($29)\n"
+" sw $2, ($8)\n" // store valLo
+" jr $31\n"
+" nop\n"
+".previous\n"
+".end do_syscall_WRK\n"
+);
+
#else
# error Unknown platform
#endif
@@ -678,6 +733,13 @@
}
return VG_(mk_SysRes_s390x_linux)( val );
+
+#elif defined(VGP_mips32_linux)
+ UWord err = 0;
+ UWord valHi = 0;
+ UWord valLo = 0;
+ (void) do_syscall_WRK(a1,a2,a3,a4,a5,a6, sysno,&err,&valHi,&valLo);
+ return VG_(mk_SysRes_mips32_linux)( valLo, valHi, (ULong)err );
#else
# error Unknown platform
#endif
@@ -695,28 +757,51 @@
const HChar* VG_(strerror) ( UWord errnum )
{
switch (errnum) {
- case VKI_EPERM: return "Operation not permitted";
- case VKI_ENOENT: return "No such file or directory";
- case VKI_ESRCH: return "No such process";
- case VKI_EINTR: return "Interrupted system call";
- case VKI_EBADF: return "Bad file number";
- case VKI_EAGAIN: return "Try again";
- case VKI_ENOMEM: return "Out of memory";
- case VKI_EACCES: return "Permission denied";
- case VKI_EFAULT: return "Bad address";
- case VKI_EEXIST: return "File exists";
- case VKI_EINVAL: return "Invalid argument";
- case VKI_EMFILE: return "Too many open files";
- case VKI_ENOSYS: return "Function not implemented";
- case VKI_EOVERFLOW: return "Value too large for defined data type";
+ case VKI_EPERM: return "Operation not permitted";
+ case VKI_ENOENT: return "No such file or directory";
+ case VKI_ESRCH: return "No such process";
+ case VKI_EINTR: return "Interrupted system call";
+ case VKI_EIO: return "Input/output error";
+ case VKI_ENXIO: return "No such device or address";
+ case VKI_E2BIG: return "Argument list too long";
+ case VKI_ENOEXEC: return "Exec format error";
+ case VKI_EBADF: return "Bad file descriptor";
+ case VKI_ECHILD: return "No child processes";
+ case VKI_EAGAIN: return "Resource temporarily unavailable";
+ case VKI_ENOMEM: return "Cannot allocate memory";
+ case VKI_EACCES: return "Permission denied";
+ case VKI_EFAULT: return "Bad address";
+ case VKI_ENOTBLK: return "Block device required";
+ case VKI_EBUSY: return "Device or resource busy";
+ case VKI_EEXIST: return "File exists";
+ case VKI_EXDEV: return "Invalid cross-device link";
+ case VKI_ENODEV: return "No such device";
+ case VKI_ENOTDIR: return "Not a directory";
+ case VKI_EISDIR: return "Is a directory";
+ case VKI_EINVAL: return "Invalid argument";
+ case VKI_ENFILE: return "Too many open files in system";
+ case VKI_EMFILE: return "Too many open files";
+ case VKI_ENOTTY: return "Inappropriate ioctl for device";
+ case VKI_ETXTBSY: return "Text file busy";
+ case VKI_EFBIG: return "File too large";
+ case VKI_ENOSPC: return "No space left on device";
+ case VKI_ESPIPE: return "Illegal seek";
+ case VKI_EROFS: return "Read-only file system";
+ case VKI_EMLINK: return "Too many links";
+ case VKI_EPIPE: return "Broken pipe";
+ case VKI_EDOM: return "Numerical argument out of domain";
+ case VKI_ERANGE: return "Numerical result out of range";
+
+ case VKI_ENOSYS: return "Function not implemented";
+ case VKI_EOVERFLOW: return "Value too large for defined data type";
# if defined(VKI_ERESTARTSYS)
case VKI_ERESTARTSYS: return "ERESTARTSYS";
# endif
- default: return "VG_(strerror): unknown error";
+ default: return "VG_(strerror): unknown error";
}
}
/*--------------------------------------------------------------------*/
-/*--- end ---*/
+/*--- end ---*/
/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_syswrap/priv_syswrap-darwin.h b/main/coregrind/m_syswrap/priv_syswrap-darwin.h
index f811f29..ec012c0 100644
--- a/main/coregrind/m_syswrap/priv_syswrap-darwin.h
+++ b/main/coregrind/m_syswrap/priv_syswrap-darwin.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Apple Inc.
+ Copyright (C) 2005-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -324,7 +324,7 @@
DECL_TEMPLATE(darwin, shmdt); // 264
DECL_TEMPLATE(darwin, shmget); // 265
DECL_TEMPLATE(darwin, shm_open); // 266
-// NYI shm_unlink 267
+DECL_TEMPLATE(darwin, shm_unlink); // 267
DECL_TEMPLATE(darwin, sem_open); // 268
DECL_TEMPLATE(darwin, sem_close); // 269
DECL_TEMPLATE(darwin, sem_unlink); // 270
@@ -559,6 +559,16 @@
DECL_TEMPLATE(darwin, mach_msg_thread);
// Mach traps
+#if DARWIN_VERS == DARWIN_10_8
+DECL_TEMPLATE(darwin, mach__10);
+DECL_TEMPLATE(darwin, mach__12);
+DECL_TEMPLATE(darwin, mach__14);
+DECL_TEMPLATE(darwin, mach__16);
+DECL_TEMPLATE(darwin, mach__18);
+DECL_TEMPLATE(darwin, mach__19);
+DECL_TEMPLATE(darwin, mach__20);
+DECL_TEMPLATE(darwin, mach__21);
+#endif /* DARWIN_VERS == DARWIN_10_8 */
DECL_TEMPLATE(darwin, mach_msg_unhandled);
DECL_TEMPLATE(darwin, mach_msg);
DECL_TEMPLATE(darwin, mach_reply_port);
diff --git a/main/coregrind/m_syswrap/priv_syswrap-generic.h b/main/coregrind/m_syswrap/priv_syswrap-generic.h
index f2c9744..ceefeaf 100644
--- a/main/coregrind/m_syswrap/priv_syswrap-generic.h
+++ b/main/coregrind/m_syswrap/priv_syswrap-generic.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -235,9 +235,9 @@
extern void ML_(generic_POST_sys_getsockname) ( TId, SR, UW, UW, UW );
extern void ML_(generic_PRE_sys_getpeername) ( TId, UW, UW, UW );
extern void ML_(generic_POST_sys_getpeername) ( TId, SR, UW, UW, UW );
-extern void ML_(generic_PRE_sys_sendmsg) ( TId, UW, UW );
-extern void ML_(generic_PRE_sys_recvmsg) ( TId, UW, UW );
-extern void ML_(generic_POST_sys_recvmsg) ( TId, UW, UW );
+extern void ML_(generic_PRE_sys_sendmsg) ( TId, Char *, struct vki_msghdr * );
+extern void ML_(generic_PRE_sys_recvmsg) ( TId, Char *, struct vki_msghdr * );
+extern void ML_(generic_POST_sys_recvmsg) ( TId, Char *, struct vki_msghdr *, UInt );
extern void ML_(generic_PRE_sys_semop) ( TId, UW, UW, UW );
extern void ML_(generic_PRE_sys_semtimedop) ( TId, UW, UW, UW, UW );
diff --git a/main/coregrind/m_syswrap/priv_syswrap-linux-variants.h b/main/coregrind/m_syswrap/priv_syswrap-linux-variants.h
index 8143373..047ea13 100644
--- a/main/coregrind/m_syswrap/priv_syswrap-linux-variants.h
+++ b/main/coregrind/m_syswrap/priv_syswrap-linux-variants.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_syswrap/priv_syswrap-linux.h b/main/coregrind/m_syswrap/priv_syswrap-linux.h
index 1d0f5b7..d674c00 100644
--- a/main/coregrind/m_syswrap/priv_syswrap-linux.h
+++ b/main/coregrind/m_syswrap/priv_syswrap-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -50,10 +50,15 @@
DECL_TEMPLATE(linux, sys_perf_event_open);
DECL_TEMPLATE(linux, sys_preadv);
DECL_TEMPLATE(linux, sys_pwritev);
+DECL_TEMPLATE(linux, sys_sendmmsg);
+DECL_TEMPLATE(linux, sys_recvmmsg);
DECL_TEMPLATE(linux, sys_dup3);
DECL_TEMPLATE(linux, sys_getcpu);
DECL_TEMPLATE(linux, sys_splice);
+DECL_TEMPLATE(linux, sys_tee);
+DECL_TEMPLATE(linux, sys_vmsplice);
DECL_TEMPLATE(linux, sys_readahead);
+DECL_TEMPLATE(linux, sys_move_pages);
// POSIX, but various sub-cases differ between Linux and Darwin.
DECL_TEMPLATE(linux, sys_fcntl);
@@ -263,6 +268,10 @@
// Linux-specific (oprofile-related)
DECL_TEMPLATE(linux, sys_lookup_dcookie); // (*/32/64) L
+// Linux-specific (new in Linux 3.2)
+DECL_TEMPLATE(linux, sys_process_vm_readv);
+DECL_TEMPLATE(linux, sys_process_vm_writev);
+
/* ---------------------------------------------------------------------
Wrappers for sockets and ipc-ery. These are split into standalone
procedures because x86-linux hides them inside multiplexors
diff --git a/main/coregrind/m_syswrap/priv_syswrap-main.h b/main/coregrind/m_syswrap/priv_syswrap-main.h
index 40ff55d..1fbf8a4 100644
--- a/main/coregrind/m_syswrap/priv_syswrap-main.h
+++ b/main/coregrind/m_syswrap/priv_syswrap-main.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_syswrap/priv_types_n_macros.h b/main/coregrind/m_syswrap/priv_types_n_macros.h
index 8069cbd..70752ab 100644
--- a/main/coregrind/m_syswrap/priv_types_n_macros.h
+++ b/main/coregrind/m_syswrap/priv_types_n_macros.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -98,6 +98,15 @@
Int o_arg6;
Int uu_arg7;
Int uu_arg8;
+# elif defined(VGP_mips32_linux)
+ Int o_arg1;
+ Int o_arg2;
+ Int o_arg3;
+ Int o_arg4;
+ Int s_arg5;
+ Int s_arg6;
+ Int uu_arg7;
+ Int uu_arg8;
# elif defined(VGP_x86_darwin)
Int s_arg1;
Int s_arg2;
@@ -167,6 +176,16 @@
fixed sized table exposed to the caller, but that's too inflexible;
hence now use a function which can do arbitrary messing around to
find the required entry. */
+#if defined(VGP_mips32_linux)
+ /* Up to 6 parameters, 4 in registers 2 on stack. */
+# define PRA1(s,t,a) PRRAn(1,s,t,a)
+# define PRA2(s,t,a) PRRAn(2,s,t,a)
+# define PRA3(s,t,a) PRRAn(3,s,t,a)
+# define PRA4(s,t,a) PRRAn(4,s,t,a)
+# define PRA5(s,t,a) PSRAn(5,s,t,a)
+# define PRA6(s,t,a) PSRAn(6,s,t,a)
+
+#endif
#if defined(VGO_linux)
extern
SyscallTableEntry* ML_(get_linux_syscall_entry)( UInt sysno );
@@ -359,7 +378,16 @@
PRAn == "pre-read-argument"
*/
-#if defined(VGO_linux)
+#if defined(VGP_mips32_linux)
+ /* Up to 6 parameters, 4 in registers 2 on stack. */
+# define PRA1(s,t,a) PRRAn(1,s,t,a)
+# define PRA2(s,t,a) PRRAn(2,s,t,a)
+# define PRA3(s,t,a) PRRAn(3,s,t,a)
+# define PRA4(s,t,a) PRRAn(4,s,t,a)
+# define PRA5(s,t,a) PSRAn(5,s,t,a)
+# define PRA6(s,t,a) PSRAn(6,s,t,a)
+
+#elif defined(VGO_linux) && !defined(VGP_mips32_linux)
/* Up to 6 parameters, all in registers. */
# define PRA1(s,t,a) PRRAn(1,s,t,a)
# define PRA2(s,t,a) PRRAn(2,s,t,a)
@@ -480,6 +508,18 @@
since the least significant parts of the guest register are stored
in memory at the highest address.
*/
+#if (defined(VGP_mips32_linux) && defined (_MIPSEB))
+ #define PSRAn_BE(n,s,t,a) \
+ do { \
+ Addr next = layout->s_arg##n + sizeof(UWord) + \
+ VG_(get_SP)(tid); \
+ vg_assert(sizeof(t) <= sizeof(UWord)); \
+ VG_(tdict).track_pre_mem_read( \
+ Vg_CoreSysCallArgInMem, tid, s"("#a")", \
+ next-sizeof(t), sizeof(t) \
+ ); \
+ } while (0)
+#else
#define PSRAn_BE(n,s,t,a) \
do { \
Addr next = layout->o_arg##n + sizeof(UWord) + \
@@ -490,6 +530,7 @@
next-sizeof(t), sizeof(t) \
); \
} while (0)
+#endif
#if defined(VG_BIGENDIAN)
# define PSRAn(n,s,t,a) PSRAn_BE(n,s,t,a)
diff --git a/main/coregrind/m_syswrap/syscall-amd64-darwin.S b/main/coregrind/m_syswrap/syscall-amd64-darwin.S
index bc88336..48ffad4 100644
--- a/main/coregrind/m_syswrap/syscall-amd64-darwin.S
+++ b/main/coregrind/m_syswrap/syscall-amd64-darwin.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_syswrap/syscall-amd64-linux.S b/main/coregrind/m_syswrap/syscall-amd64-linux.S
index 7147dba..1b46f3e 100644
--- a/main/coregrind/m_syswrap/syscall-amd64-linux.S
+++ b/main/coregrind/m_syswrap/syscall-amd64-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_syswrap/syscall-arm-linux.S b/main/coregrind/m_syswrap/syscall-arm-linux.S
index 0696b6a..6f18518 100644
--- a/main/coregrind/m_syswrap/syscall-arm-linux.S
+++ b/main/coregrind/m_syswrap/syscall-arm-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 Evan Geller (gaze@bea.ms)
+ Copyright (C) 2008-2012 Evan Geller (gaze@bea.ms)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/coregrind/m_syswrap/syscall-mips32-linux.S b/main/coregrind/m_syswrap/syscall-mips32-linux.S
new file mode 100644
index 0000000..6a550aa
--- /dev/null
+++ b/main/coregrind/m_syswrap/syscall-mips32-linux.S
@@ -0,0 +1,215 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Support for doing system calls. syscall-mips32-linux.S ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#if defined(VGP_mips32_linux)
+
+#include "pub_core_basics_asm.h"
+#include "pub_core_vkiscnums_asm.h"
+#include "libvex_guest_offsets.h"
+
+
+/*----------------------------------------------------------------*/
+/*
+ Perform a syscall for the client. This will run a syscall
+ with the client's specific per-thread signal mask.
+
+ The structure of this function is such that, if the syscall is
+ interrupted by a signal, we can determine exactly what
+ execution state we were in with respect to the execution of
+ the syscall by examining the value of IP in the signal
+ handler. This means that we can always do the appropriate
+ thing to precisely emulate the kernel's signal/syscall
+ interactions.
+
+ The syscall number is taken from the argument, even though it
+ should also be in regs->v0. The syscall result is written
+ back to regs->v0 on completion.
+
+ Returns 0 if the syscall was successfully called (even if the
+ syscall itself failed), or a nonzero error code in the lowest
+ 8 bits if one of the sigprocmasks failed (there's no way to
+ determine which one failed). And there's no obvious way to
+ recover from that either, but nevertheless we want to know.
+
+ VG_(fixup_guest_state_after_syscall_interrupted) does the
+ thread state fixup in the case where we were interrupted by a
+ signal.
+
+ Prototype:
+
+ UWord ML_(do_syscall_for_client_WRK)(
+ Int syscallno, // $4 - a0
+ void* guest_state, // $5 - a1
+ const vki_sigset_t *sysmask, // $6 - a2
+ const vki_sigset_t *postmask, // $7 - a3
+ Int nsigwords) // stack
+*/
+/* from vki_arch.h */
+#define VKI_SIG_SETMASK 3
+
+.globl ML_(do_syscall_for_client_WRK)
+ML_(do_syscall_for_client_WRK):
+
+ subu $29, $29, 56 #set up the steck frame,
+ sw $4, 52($29)
+ sw $5, 48($29)
+ sw $6, 44($29)
+ sw $7, 40($29)
+ sw $31, 36($29)
+ sw $30, 32($29)
+ sw $16, 28($29)
+ sw $17, 24($29)
+ sw $18, 20($29)
+ sw $19, 16($29)
+ sw $20, 12($29)
+ sw $21, 8($29)
+ sw $22, 4($29)
+ sw $23, 0($29)
+ addu $30, $29, 56
+
+
+ /* Set the signal mask which should be current during the syscall. */
+
+1: li $2, __NR_rt_sigprocmask
+ li $4, VKI_SIG_SETMASK
+ move $5, $6 /* sysmask */
+ move $6, $7 /* postmask */
+ lw $7, 72($29) /* nsigwords */
+ syscall
+ nop
+
+# TODO: this should remain, keep it just for now
+ bnez $7, 7f
+ nop
+
+ lw $8, 48($29) /* t0 == ThreadState */
+
+ lw $2, 52($29) /* v0 == syscallno */
+ lw $4, OFFSET_mips32_r4($8)
+ lw $5, OFFSET_mips32_r5($8)
+ lw $6, OFFSET_mips32_r6($8)
+ lw $7, OFFSET_mips32_r7($8)
+ subu $29, $29, 24 #set up the steck frame,
+ lw $9, OFFSET_mips32_r29($8)
+ lw $10, 16($9)
+ sw $10, 16($29)
+ lw $10, 20($9)
+ sw $10, 20($29)
+
+2: syscall
+
+3: addu $29, $29, 24 #set up the steck frame,
+
+ lw $8, 48($29) /* t0 == ThreadState */
+ sw $2, OFFSET_mips32_r2($8)
+ sw $3, OFFSET_mips32_r3($8)
+ sw $7, OFFSET_mips32_r7($8)
+
+4: li $2, __NR_rt_sigprocmask
+ li $4, VKI_SIG_SETMASK
+ lw $5, 40($29)
+ li $6, 0
+ lw $7, 72($29) /* nsigwords */
+ syscall
+ nop
+
+ bnez $7, 7f
+ nop
+
+ /* Success */
+ li $2, 0
+
+5: lw $4, 52($29)
+ lw $5, 48($29)
+ lw $6, 44($29)
+ lw $7, 40($29)
+ lw $31, 36($29)
+ lw $30, 32($29)
+ lw $16, 28($29)
+ lw $17, 24($29)
+ lw $18, 20($29)
+ lw $19, 16($29)
+ lw $20, 12($29)
+ lw $21, 8($29)
+ lw $22, 4($29)
+ lw $23, 0($29)
+ addu $29, $29, 56 #release the stack frame.
+
+ jr $31
+ nop
+
+7: /* Failure: return 0x8000 | error code */
+ li $2, 0x8000
+
+ lw $4, 52($29)
+ lw $5, 48($29)
+ lw $6, 44($29)
+ lw $7, 40($29)
+ lw $31, 36($29)
+ lw $30, 32($29)
+ lw $16, 28($29)
+ lw $17, 24($29)
+ lw $18, 20($29)
+ lw $19, 16($29)
+ lw $20, 12($29)
+ lw $21, 8($29)
+ lw $22, 4($29)
+ lw $23, 0($29)
+ addu $29, $29, 56 #release the stack frame.
+
+ jr $31
+ nop
+
+.section .rodata
+/* export the ranges so that
+ VG_(fixup_guest_state_after_syscall_interrupted) can do the
+ right thing */
+
+.globl ML_(blksys_setup)
+.globl ML_(blksys_restart)
+.globl ML_(blksys_complete)
+.globl ML_(blksys_committed)
+.globl ML_(blksys_finished)
+ML_(blksys_setup): .long 1b
+ML_(blksys_restart): .long 2b
+ML_(blksys_complete): .long 3b
+ML_(blksys_committed): .long 4b
+ML_(blksys_finished): .long 5b
+.previous
+/* Let the linker know we don't need an executable stack */
+.section .note.GNU-stack,"",%progbits
+
+
+
+#endif // defined(VGP_mips32_linux)
+
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_syswrap/syscall-ppc32-linux.S b/main/coregrind/m_syswrap/syscall-ppc32-linux.S
index 90b4a73..9a11126 100644
--- a/main/coregrind/m_syswrap/syscall-ppc32-linux.S
+++ b/main/coregrind/m_syswrap/syscall-ppc32-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Paul Mackerras (paulus@samba.org)
+ Copyright (C) 2005-2012 Paul Mackerras (paulus@samba.org)
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/coregrind/m_syswrap/syscall-ppc64-linux.S b/main/coregrind/m_syswrap/syscall-ppc64-linux.S
index 9fecd04..f3a1392 100644
--- a/main/coregrind/m_syswrap/syscall-ppc64-linux.S
+++ b/main/coregrind/m_syswrap/syscall-ppc64-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Paul Mackerras <paulus@samba.org>
+ Copyright (C) 2005-2012 Paul Mackerras <paulus@samba.org>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/coregrind/m_syswrap/syscall-s390x-linux.S b/main/coregrind/m_syswrap/syscall-s390x-linux.S
index 72cf740..e31e701 100644
--- a/main/coregrind/m_syswrap/syscall-s390x-linux.S
+++ b/main/coregrind/m_syswrap/syscall-s390x-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/coregrind/m_syswrap/syscall-x86-darwin.S b/main/coregrind/m_syswrap/syscall-x86-darwin.S
index 9e90c8a..8955250 100644
--- a/main/coregrind/m_syswrap/syscall-x86-darwin.S
+++ b/main/coregrind/m_syswrap/syscall-x86-darwin.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_syswrap/syscall-x86-linux.S b/main/coregrind/m_syswrap/syscall-x86-linux.S
index 594c5c6..2b440d7 100644
--- a/main/coregrind/m_syswrap/syscall-x86-linux.S
+++ b/main/coregrind/m_syswrap/syscall-x86-linux.S
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_syswrap/syswrap-aix5.c b/main/coregrind/m_syswrap/syswrap-aix5.c
deleted file mode 100644
index 4fa273f..0000000
--- a/main/coregrind/m_syswrap/syswrap-aix5.c
+++ /dev/null
@@ -1,2591 +0,0 @@
-
-/*--------------------------------------------------------------------*/
-/*--- AIX5-specific syscalls. syswrap-aix5.c ---*/
-/*--------------------------------------------------------------------*/
-
-/*
- This file is part of Valgrind, a dynamic binary instrumentation
- framework.
-
- Copyright (C) 2006-2010 OpenWorks LLP
- info@open-works.co.uk
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-
- Neither the names of the U.S. Department of Energy nor the
- University of California nor the names of its contributors may be
- used to endorse or promote products derived from this software
- without prior written permission.
-*/
-
-#if defined(VGO_aix5)
-
-#include "pub_core_basics.h"
-#include "pub_core_vki.h"
-#include "pub_core_vkiscnums.h"
-#include "pub_core_threadstate.h"
-#include "pub_core_aspacemgr.h"
-#include "pub_core_debuginfo.h" // VG_(di_notify_*)
-#include "pub_core_transtab.h" // VG_(discard_translations)
-#include "pub_core_xarray.h"
-#include "pub_core_clientstate.h"
-#include "pub_core_debuglog.h"
-#include "pub_core_libcbase.h"
-#include "pub_core_libcassert.h"
-#include "pub_core_libcfile.h"
-#include "pub_core_libcprint.h"
-#include "pub_core_libcproc.h"
-#include "pub_core_libcsignal.h"
-#include "pub_core_mallocfree.h"
-#include "pub_core_tooliface.h"
-#include "pub_core_options.h"
-#include "pub_core_scheduler.h"
-#include "pub_core_signals.h"
-#include "pub_core_syscall.h"
-#include "pub_core_sigframe.h" // VG_(sigframe_destroy)
-#include "pub_core_syswrap.h"
-#include "pub_core_stacktrace.h"
-
-#include "priv_types_n_macros.h"
-#include "priv_syswrap-aix5.h"
-
-
-
-/* ---------------------------------------------------------------------
- Misc helpers
- ------------------------------------------------------------------ */
-
-/* Allocate a stack for this thread, if it doesn't already have one.
- They're allocated lazily, and never freed. Returns the initial stack
- pointer value to use, or 0 if allocation failed. */
-Addr ML_(allocstack)(ThreadId tid)
-{
- ThreadState* tst = VG_(get_ThreadState)(tid);
- VgStack* stack;
- Addr initial_SP;
-
- /* Either the stack_base and stack_init_SP are both zero (in which
- case a stack hasn't been allocated) or they are both non-zero,
- in which case it has. */
-
- if (tst->os_state.valgrind_stack_base == 0)
- vg_assert(tst->os_state.valgrind_stack_init_SP == 0);
-
- if (tst->os_state.valgrind_stack_base != 0)
- vg_assert(tst->os_state.valgrind_stack_init_SP != 0);
-
- /* If no stack is present, allocate one. */
- if (tst->os_state.valgrind_stack_base == 0) {
- stack = VG_(am_alloc_VgStack)( &initial_SP );
- if (stack) {
- /* Leave some space above SP because AIX's ABI stores
- stuff there. */
- initial_SP -= 256;
- vg_assert(initial_SP > (Addr)stack);
- tst->os_state.valgrind_stack_base = (Addr)stack;
- tst->os_state.valgrind_stack_init_SP = initial_SP;
- } else {
- return 0; /* allocation of stack failed */
- }
- }
-
- if (0)
- VG_(printf)( "stack for tid %d at %p; init_SP=%p\n",
- tid,
- (void*)tst->os_state.valgrind_stack_base,
- (void*)tst->os_state.valgrind_stack_init_SP );
-
- return tst->os_state.valgrind_stack_init_SP;
-}
-
-
-/* If we know or believe a module load/unload event has happened, get
- aspacem to re-read /proc/../map to update its picture of what text
- and data segments are present. This also notifies all the usual
- parties that need to know about address space changes. */
-
-void ML_(aix5_rescan_procmap_after_load_or_unload) ( void )
-{
- AixCodeSegChange* changes;
- Int changes_size, changes_used, i;
-
- /* Find out how many AixCodeSegChange records we will need, and
- acquire them. */
- changes_size = VG_(am_aix5_reread_procmap_howmany_directives)();
- changes = VG_(arena_malloc)(VG_AR_CORE, "syswrap-aix5.arpalou.1",
- changes_size * sizeof(AixCodeSegChange));
- vg_assert(changes);
-
- /* Now re-read /proc/<pid>/map and acquire a change set */
- VG_(am_aix5_reread_procmap)( changes, &changes_used );
- vg_assert(changes_used >= 0 && changes_used <= changes_size);
-
- /* And notify all parties of the changes. */
- for (i = 0; i < changes_used; i++) {
- ULong di_handle = VG_(di_aix5_notify_segchange)(
- changes[i].code_start,
- changes[i].code_len,
- changes[i].data_start,
- changes[i].data_len,
- changes[i].file_name,
- changes[i].mem_name,
- changes[i].is_mainexe,
- changes[i].acquire
- );
-
- if (changes[i].acquire) {
- VG_TRACK( new_mem_mmap,
- changes[i].code_start, changes[i].code_len,
- /*r*/True, /*w*/False, /*x*/True, di_handle );
- VG_TRACK( new_mem_mmap,
- changes[i].data_start, changes[i].data_len,
- /*r*/True, /*w*/True, /*x*/False, 0/*or di_handle?*/ );
- } else {
- VG_TRACK( die_mem_munmap,
- changes[i].code_start, changes[i].code_len );
- VG_TRACK( die_mem_munmap,
- changes[i].data_start, changes[i].data_len );
- VG_(discard_translations)(
- changes[i].code_start, changes[i].code_len,
- "POST(sys___loadx/sys__kload)(code)" );
- VG_(discard_translations)(
- changes[i].data_start, changes[i].data_len,
- "POST(sys___loadx/sys__kload)(data)" );
- }
- }
-
- VG_(arena_free)(VG_AR_CORE, changes);
-}
-
-
-/* Mess with the given thread's pc/toc so that it is entering
- pthread_exit() with argument PTHREAD_CANCELED. Returns True if ok,
- False if it failed to do so, due to not being able to find
- pthread_exit() by searching symbol tables. */
-Bool ML_(aix5_force_thread_into_pthread_exit)( ThreadId tid )
-{
- Addr ent = 0, toc = 0;
- Bool found;
- ThreadState* tst = VG_(get_ThreadState)(tid);
- found = VG_(lookup_symbol_SLOW)("libpthread*.a(*.o)", "pthread_exit",
- &ent, &toc);
- if (found) {
- if (0)
- VG_(printf)("THREAD CANCELED, new cia,toc = %#lx,%#lx\n", ent, toc);
- tst->arch.vex.guest_CIA = ent;
- tst->arch.vex.guest_GPR2 = toc;
- tst->arch.vex.guest_GPR3 = (Word)(-1); /* == PTHREAD_CANCELED */
- /* If the thread is blocked in a syscall, we better bop it on
- the head with SIGVGKILL in order to get it out of said
- syscall. */
- if (tst->status == VgTs_WaitSys) {
- if (VG_(clo_trace_syscalls))
- VG_(printf)("(sending SIGVGKILL to tid %d)", (Int)tid);
- VG_(get_thread_out_of_syscall)( tid );
- }
- return True; /* ok */
- } else {
- // urk. Now we're hosed. Let the caller figure out what to do.
- return False; /* failed */
- }
-}
-
-
-/* For various reasons, on AIX we may have to just give up if
- continuing is too difficult (eg, risk of future deadlock). This
- sets up the process state to exit straight away, but does not
- actually itself exit. */
-void ML_(aix5_set_threadstate_for_emergency_exit)(ThreadId tid, HChar* why)
-{
- ThreadState* tst = VG_(get_ThreadState)(tid);
- /* Set the thread's status to be exiting and taking out the
- entire process, then claim that the syscall succeeded. */
- tst->exitreason = VgSrc_ExitProcess;
- tst->os_state.exitcode = 1;
- if (!VG_(clo_xml)) {
- VG_(message)(Vg_UserMsg,
- "WARNING: AIX: %s\n", why);
- VG_(message)(Vg_UserMsg,
- "WARNING: (too difficult to continue past this point).\n");
- VG_(get_and_pp_StackTrace)(tid, 10);
- }
-}
-
-
-/* Update aspacem etc on conclusion of a successful sbrk/__libc_sbrk
- call. 2006-08-24: this was not completed because I don't
- understand what sbrk/__libc_sbrk are doing. */
-
-static void handle_sbrk ( Word delta )
-{
- return;
- /*NOTREACHED*/
- if (delta > 0) {
- /* Map in VG_(brk_limit) for delta */
- /* using notify_mmap ? */
- VG_(brk_limit) += delta;
- }
- if (delta < 0) {
- Addr tmp = VG_(brk_limit);
- VG_(brk_limit) += delta;
- /* Can't move below original starting point */
- if (VG_(brk_limit) < VG_(brk_base))
- VG_(brk_limit) = VG_(brk_base);
- if (VG_(brk_limit) < tmp)
- /* Unmap VG_(brk_limit) for tmp - VG_(brk_limit) */
- /* using notify_munmap ? */
- ;
- }
- if (VG_(clo_trace_syscalls))
- VG_(printf)("new brk: 0x%010llx-0x%010llx (size %lld)\n",
- (ULong)VG_(brk_base),
- (ULong)VG_(brk_limit),
- (ULong)VG_(brk_limit) - (ULong)VG_(brk_base));
-}
-
-
-/* --- !!! --- EXTERNAL HEADERS start --- !!! --- */
-#include <sys/thread.h>
-#include <sys/poll.h>
-#include <sys/times.h>
-#include <sys/shm.h>
-#include <semaphore.h>
-#include <sys/statfs.h>
-#include <sys/utsname.h>
-/* --- !!! --- EXTERNAL HEADERS end --- !!! --- */
-
-HChar* ML_(aix5debugstuff_pc_to_fnname) ( Addr pc )
-{
- Bool ok;
- static HChar name[100];
- ok = VG_(get_fnname_w_offset)(pc, name, 100);
- if (!ok) VG_(strcpy)(name, "???");
- return &name[0];
-}
-
-static void aix5debugstuff_show_sigset ( vki_sigset_t* set )
-{
- Int i;
- UChar* p = (UChar*)set;
- for (i = 0; i < sizeof(vki_sigset_t); i++)
- VG_(printf)("%02x", (Int)p[i]);
-}
-
-static HChar* aix5debugstuff_name_of_tstate_flag ( UWord flag )
-{
- Int i, nset;
- nset = 0;
- for (i = 0; i < 8*sizeof(UWord); i++)
- if (flag & (1U << i))
- nset++;
- vg_assert(nset == 1);
- switch (flag) {
- case TSTATE_LOCAL: return "LOCAL";
- case TSTATE_CANCEL_DEFER: return "CANCEL_DEFER";
- case TSTATE_CANCEL_DISABLE: return "CANCEL_DISABLE";
- case TSTATE_CANCEL_PENDING: return "CANCEL_PENDING";
- case TSTATE_CANCEL_CHKPT: return "CANCEL_CHKPT";
- case TSTATE_INTR: return "INTR";
- case TSTATE_EXEMPT: return "EXEMPT";
-#ifdef TSTATE_PROFILING_OFF
- case TSTATE_PROFILING_OFF: return "PROFILING_OFF";
-#endif
- case TSTATE_SUSPEND: return "SUSPEND";
- case TSTATE_CONT: return "CONT";
-#ifdef TSTATE_CREDS
- case TSTATE_CREDS: return "CREDS";
-#endif
-#ifdef TSTATE_PROCHANDLERS
- case TSTATE_PROCHANDLERS: return "PROCHANDLERS";
-#endif
- case TSTATE_ADVH: return "ADVH";
- case TSTATE_SYNCH: return "SYNCH";
- case TSTATE_USCHED: return "USCHED";
- case TSTATE_DEFAULT_SCHED: return "DEFAULT_SCHED";
-#ifdef TSTATE_INHERIT_SCHED
- case TSTATE_INHERIT_SCHED: return "INHERIT_SCHED";
-#endif
-#ifdef TSTATE_LOCAL_INIT
- case TSTATE_LOCAL_INIT: return "LOCAL_INIT";
-#endif
-#ifdef TSTATE_LOCAL_TERM
- case TSTATE_LOCAL_TERM: return "LOCAL_TERM";
-#endif
-#ifdef TSTATE_LOCAL_MCHANGE
- case TSTATE_LOCAL_MCHANGE: return "LOCAL_MCHANGE";
-#endif
- case TSTATE_CHANGE_ALL: return "CHANGE_ALL";
-#ifdef TSTATE_CHANGE_PTID
- case TSTATE_CHANGE_PTID: return "CHANGE_PTID";
-#endif
-#ifdef TSTATE_CHANGE_PROFILE
- case TSTATE_CHANGE_PROFILE: return "CHANGE_PROFILE";
-#endif
-#ifdef TSTATE_CHANGE_SSTACK
- case TSTATE_CHANGE_SSTACK: return "CHANGE_SSTACK";
-#endif
- case TSTATE_CHANGE_ERRNOP: return "CHANGE_ERRNOP";
- case TSTATE_CHANGE_SIGMASK: return "CHANGE_SIGMASK";
- case TSTATE_CHANGE_PSIG: return "CHANGE_PSIG";
- case TSTATE_CHANGE_SCHED: return "CHANGE_SCHED";
- case TSTATE_CHANGE_FLAGS: return "CHANGE_FLAGS";
- case TSTATE_CHANGE_USERDATA: return "CHANGE_USERDATA";
- default: return "???";
- }
-}
-
-void ML_(aix5debugstuff_show_tstate_flags) ( UWord w )
-{
- const Int step = 5;
- Int i, j;
- UWord m;
- j = 0;
- for (i = 0; i < 8*sizeof(UWord); i++) {
- m = 1U << i;
- if ((w & m) == 0)
- continue;
- if ((j % step) == 0)
- VG_(printf)(" ");
- VG_(printf)("%s ", aix5debugstuff_name_of_tstate_flag(w & m));
- if ((j % step) == step-1 && j > 0)
- VG_(printf)("\n");
- j++;
- }
- if (((j-1) % step) != step-1 && j > 0)
- VG_(printf)("\n");
-}
-
-void ML_(aix5debugstuff_show_tstate) ( Addr tsA, HChar* who )
-{
- Int i;
- const Int step = sizeof(void*)==8 ? 3 : 5;
- struct tstate* ts = (struct tstate*)tsA;
- VG_(printf)("\n{ ========= %s =========\n", who);
- for (i = 0; i < _NGPRS; i++) {
- if ((i % step) == 0)
- VG_(printf)(" [%2d] ", i);
- if (sizeof(void*)==8)
- VG_(printf)("%016llx ", (ULong)ts->mst.gpr[i]);
- else
- VG_(printf)("%08llx ", (ULong)ts->mst.gpr[i]);
- if ((i == _NGPRS-1) || ((i % step) == step-1 && i > 0))
- VG_(printf)("\n");
- }
- VG_(printf)(" [iar] %#llx %s\n", (ULong)ts->mst.iar,
- ML_(aix5debugstuff_pc_to_fnname)(ts->mst.iar));
-
- VG_(printf)(" errnop_addr %p\n", ts->errnop_addr);
-
- VG_(printf)(" sigmask ");
- aix5debugstuff_show_sigset( (vki_sigset_t*)&ts->sigmask );
- VG_(printf)("\n");
-
- VG_(printf)(" psig ");
- aix5debugstuff_show_sigset( (vki_sigset_t*)&ts->psig );
- VG_(printf)("\n");
-
- VG_(printf)(" policy %d\n", ts->policy);
- VG_(printf)(" priority %d\n", ts->priority);
- VG_(printf)(" flags 0x%x\n", ts->flags);
- ML_(aix5debugstuff_show_tstate_flags)( (UWord)ts->flags );
- VG_(printf)(" flagmask 0x%x\n", ts->flagmask);
- VG_(printf)(" userdata %p\n", (void*)ts->userdata);
- VG_(printf)(" fpinfo %d\n", ts->fpinfo);
- VG_(printf)(" fpscrx %d\n", ts->fpscrx);
- VG_(printf)(" sigaltstack ??\n");
- VG_(printf)(" thread_control_p 0x%llx\n", (ULong)ts->thread_control_p);
-// AIX 5.1 does not seem to have these members
-// VG_(printf)(" prbase %p\n", (void*)ts->prbase);
-// VG_(printf)(" credp %p\n", (void*)ts->credp);
-// VG_(printf)(" ptid %d\n", (int)ts->ptid);
-// VG_(printf)(" tct_clock %d\n", (int)ts->tct_clock);
- UInt* p = (UInt*)tsA;
- for (i = 0; i < sizeof(struct tstate)/sizeof(UInt); i++) {
- HChar* s = ML_(aix5debugstuff_pc_to_fnname)( (Addr)p[i] );
- if (0==VG_(strcmp)(s,"???"))
- continue;
- VG_(printf)(" [%d] %x %s\n", i, p[i], s);
- }
- VG_(printf)("}\n");
-}
-
-/* ---------------------------------------------------------------------
- PRE/POST wrappers for arch-generic, AIX5-specific syscalls. Note:
- in fact AIX5 doesn't share any wrappers with Linux since it's
- difficult to get syswrap-generic.c to compile on AIX. Hence in
- fact this file also serves the role of syswrap-generic.c for AIX.
- This could probably be improved at the cost of some extra effort.
- ------------------------------------------------------------------ */
-
-// Nb: See the comment above the generic PRE/POST wrappers in
-// m_syswrap/syswrap-generic.c for notes about how they work.
-
-#define PRE(name) DEFN_PRE_TEMPLATE(aix5, name)
-#define POST(name) DEFN_POST_TEMPLATE(aix5, name)
-
-
-// How to make __libc_sbrk appear to fail, from libc's point of view:
-// SysRes r;
-// r.res = -1; /* significant to libc */
-// r.err = VKI_ENOMEM; /* not significant to libc */
-// SET_STATUS_from_SysRes( r );
-// return;
-
-PRE(sys___libc_sbrk)
-{
- PRINT("__libc_sbrk (BOGUS HANDLER)( %#lx )",ARG1);
- PRE_REG_READ1(long, "__libc_sbrk", long, arg1);
- /* After a zero sbrk, disallow aspacem from doing sbrk, since libc
- might rely on the value returned by this syscall. */
- /* 1 Oct 06: not currently used (aspacemgr-aix5.c ignores it) */
- VG_(am_aix5_sbrk_allowed) = toBool(ARG1 != 0);
- /* Disallow libc from moving the brk backwards as that might trash
- SkPreAlloc sections acquired by aspacem from previous uses of
- sbrk. */
- if (ARG1 < 0)
- ARG1 = 0;
- /* Do this as a sync syscall, so the sbrk_allowed flag gets turned
- back on ASAP. Typically libc does sbrk(0) and then sbrk(x > 0)
- in quick succession. Although surely it should hold some kind
- of lock at that point, else it cannot safely use the result from
- the first sbrk call to influence the second one? */
- *flags &= ~SfMayBlock;
-}
-POST(sys___libc_sbrk)
-{
- vg_assert(SUCCESS);
- handle_sbrk(ARG1);
-}
-
-/* __loadx is handled in the platform-specific files. */
-
-PRE(sys___msleep)
-{
- PRINT("__msleep (BOGUS HANDLER) ( %#lx )", ARG1);
- PRE_REG_READ1(long, "msleep", void*, arg1);
-}
-
-/* __unload is handled in the platform-specific files. */
-
-PRE(sys__clock_settime)
-{
- PRINT("_clock_settime (UNDOCUMENTED) ( %ld, %#lx )", ARG1, ARG2);
- PRE_REG_READ2(int, "_clock_settime", int, arg1, int, arg2);
-}
-
-PRE(sys__exit)
-{
- ThreadState* tst;
- /* simple; just make this thread exit */
- PRINT("_exit( %ld )", ARG1);
- PRE_REG_READ1(void, "exit", int, exitcode);
-
- tst = VG_(get_ThreadState)(tid);
- /* Set the thread's status to be exiting and taking out the entire
- process, then claim that the syscall succeeded. */
- tst->exitreason = VgSrc_ExitProcess;
- tst->os_state.exitcode = ARG1;
- SET_STATUS_Success(0);
-}
-
-PRE(sys__fp_fpscrx_sc)
-{
- PRINT("_fp_fpscrx_sc (BOGUS HANDLER)");
-}
-
-PRE(sys__getpgrp)
-{
- PRINT("_getpgrp (BOGUS HANDLER)");
-}
-
-PRE(sys__getpid)
-{
- PRINT("_getpid ( )");
-}
-
-PRE(sys__getppid)
-{
- PRINT("_getppid ( )");
-}
-
-PRE(sys__getpriority)
-{
- PRINT("_getpriority (BOGUS HANDLER)");
-}
-
-PRE(sys__nsleep)
-{
- *flags |= SfMayBlock;
- PRINT("_nsleep( %#lx, %#lx )", ARG1, ARG2);
- PRE_REG_READ2(void, "_nsleep", struct timestruc_t*, arg1,
- struct timestruc_t*, arg2);
- /* In 64-bit mode, struct ends in 4 padding bytes. Hence: */
- if (ARG1)
- PRE_MEM_READ("_nsleep(arg1)",
- ARG1,
- sizeof(void*)==4 ? sizeof(struct timestruc_t)
- : sizeof(struct timestruc_t)-4 );
- if (ARG2)
- PRE_MEM_WRITE("_nsleep(arg2)", ARG2, sizeof(struct timestruc_t));
-}
-POST(sys__nsleep)
-{
- if (ARG2)
- POST_MEM_WRITE(ARG2, sizeof(struct timestruc_t));
-}
-
-PRE(sys__pause)
-{
- *flags |= SfMayBlock;
- PRINT("_pause ( )");
- PRE_REG_READ0(long, "pause");
-}
-
-PRE(sys__poll)
-{
- UInt i;
- struct pollfd* ufds = (struct pollfd *)ARG1;
- *flags |= SfMayBlock;
- PRINT("_poll ( %#lx, %ld, %ld )\n", ARG1,ARG2,ARG3);
- PRE_REG_READ3(long, "_poll",
- struct pollfd *, ufds, unsigned int, nfds, long, timeout);
-
- for (i = 0; i < ARG2; i++) {
- PRE_MEM_READ( "poll(ufds.fd)",
- (Addr)(&ufds[i].fd), sizeof(ufds[i].fd) );
- PRE_MEM_READ( "poll(ufds.events)",
- (Addr)(&ufds[i].events), sizeof(ufds[i].events) );
- PRE_MEM_WRITE( "poll(ufds.reventss)",
- (Addr)(&ufds[i].revents), sizeof(ufds[i].revents) );
- }
-}
-POST(sys__poll)
-{
- if (RES > 0) {
- UInt i;
- struct pollfd* ufds = (struct pollfd *)ARG1;
- for (i = 0; i < ARG2; i++)
- POST_MEM_WRITE( (Addr)(&ufds[i].revents), sizeof(ufds[i].revents) );
- }
-}
-
-PRE(sys__select)
-{
- UInt nfds, nmqids;
- *flags |= SfMayBlock;
- /* XXX: copy of generic; I don't know if this is right or not. */
- PRINT("_select ( %ld, %#lx, %#lx, %#lx, %#lx )", ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ5(long, "_select",
- int, n, struct sellist *, readfds,
- struct sellist *, writefds,
- struct sellist *, exceptfds,
- struct timeval *, timeout);
- nfds = ((UInt)ARG1) & 0xFFFF;
- nmqids = (((UInt)ARG1) >> 16) & 0xFFFF;
-
- // XXX: this possibly understates how much memory is read.
- if (ARG2 != 0)
- PRE_MEM_READ( "select(readfds)",
- ARG2, nfds/8 /* __FD_SETSIZE/8 */ );
- if (ARG3 != 0)
- PRE_MEM_READ( "select(writefds)",
- ARG3, nfds/8 /* __FD_SETSIZE/8 */ );
- if (ARG4 != 0)
- PRE_MEM_READ( "select(exceptfds)",
- ARG4, nfds/8 /* __FD_SETSIZE/8 */ );
- if (ARG5 != 0)
- PRE_MEM_READ( "select(timeout)", ARG5,
- /* in 64-bit mode, struct timeval has 4 bytes of
- padding at the end, which tend to not be
- initialised. */
- sizeof(void*)==4 ? sizeof(struct timeval)
- : sizeof(struct timeval)-4
- );
-}
-
-PRE(sys__sem_wait)
-{
- *flags |= SfMayBlock;
- PRINT("_sem_wait (BOGUS HANDLER) ( %#lx, %#lx, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "_sem_wait", void*, arg1, void*, arg2, long, arg3 );
- /* Not sure what the two pointer args are. Hence no proper handler.*/
-}
-
-PRE(sys__setpgid)
-{
- PRINT("setpgid ( %ld, %ld )", ARG1, ARG2);
- PRE_REG_READ2(int, "setpgid", int, pid, int, pgid);
-}
-
-PRE(sys__setsid)
-{
- PRINT("setsid ( )");
-}
-
-PRE(sys__sigaction) /* COL, more or less */
-{
- PRINT("_sigaction ( %ld, %#lx, %#lx )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "_sigaction",
- int, signum, const struct sigaction *, act,
- struct sigaction *, oldact);
-
- if (ARG2 != 0) {
- struct vki_sigaction *sa = (struct vki_sigaction *)ARG2;
- PRE_MEM_READ( "_sigaction(act->sa_handler)",
- (Addr)&sa->ksa_handler, sizeof(sa->ksa_handler));
- PRE_MEM_READ( "_sigaction(act->sa_mask)",
- (Addr)&sa->sa_mask, sizeof(sa->sa_mask));
- PRE_MEM_READ( "rt_sigaction(act->sa_flags)",
- (Addr)&sa->sa_flags, sizeof(sa->sa_flags));
- }
- if (ARG3 != 0)
- PRE_MEM_WRITE( "rt_sigaction(oldact)", ARG3, sizeof(struct vki_sigaction));
-
- SET_STATUS_from_SysRes(
- VG_(do_sys_sigaction)(ARG1, (const struct vki_sigaction *)ARG2,
- (struct vki_sigaction *)ARG3)
- );
-}
-POST(sys__sigaction)
-{
- vg_assert(SUCCESS);
- if (RES == 0 && ARG3 != 0)
- POST_MEM_WRITE( ARG3, sizeof(struct vki_sigaction));
-}
-
-PRE(sys__thread_self)
-{
- PRINT("_thread_self ( )");
-}
-
-PRE(sys__thread_setsched)
-{
- PRINT("_thread_setsched ( %ld, %ld, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "_thread_setsched", long, arg1, long, arg2, long, arg3);
-}
-
-PRE(sys_access)
-{
- PRINT("access ( %#lx(%s), %ld )", ARG1,(Char*)ARG1, ARG2);
- PRE_REG_READ2(int, "access", char*, pathname, int, mode);
- PRE_MEM_RASCIIZ( "access(pathname)", ARG1 );
-}
-
-PRE(sys_accessx)
-{
- PRINT("accessx ( %#lx(%s), %ld, %ld )", ARG1,(Char*)ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "accessx", char*, pathname, int, mode, int, who);
- PRE_MEM_RASCIIZ( "accessx(pathname)", ARG1 );
-}
-
-PRE(sys_appgetrlimit)
-{
- /* Note: assumes kernel struct == libc struct */
- PRINT("appgetrlimit ( %ld, %#lx )", ARG1, ARG2);
- PRE_REG_READ2(int, "appgetrlimit", int, arg1, struct rlimit*, arg2);
- PRE_MEM_WRITE( "appgetrlimit(buf)", ARG2, sizeof(struct rlimit) );
-}
-POST(sys_appgetrlimit)
-{
- POST_MEM_WRITE( ARG2, sizeof(struct rlimit) );
-}
-
-PRE(sys_appgetrusage)
-{
- /* Note: assumes kernel struct == libc struct */
- PRINT("appgetrusage ( %ld, %#lx )", ARG1, ARG2);
- PRE_REG_READ2(int, "appgetrusage", int, arg1, struct rusage*, arg2);
- PRE_MEM_WRITE( "appgetrusage(buf)", ARG2, sizeof(struct rusage) );
-}
-POST(sys_appgetrusage)
-{
- POST_MEM_WRITE( ARG2, sizeof(struct rusage) );
-}
-
-PRE(sys_apprestimer)
-{
- PRINT("apprestimer (BOGUS HANDLER)");
-}
-
-PRE(sys_appsetrlimit)
-{
- PRINT("appsetrlimit (BOGUS HANDLER)");
-}
-
-PRE(sys_appulimit)
-{
- PRINT("appulimit ( %ld, %ld )", ARG1, ARG2);
- PRE_REG_READ2(long, "appulimit", long, arg1, long, arg2);
-}
-
-PRE(sys_bind)
-{
- PRINT("bind ( %ld, %#lx, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "bind", int, socket,
- void*, address, int, addresslen);
- /* Hmm. This isn't really right - see pre_mem_read_sockaddr. */
- PRE_MEM_READ( "bind(address)", ARG2, ARG3 );
-}
-
-PRE(sys_chdir)
-{
- PRINT("chdir ( %#lx(%s) )", ARG1,(Char*)ARG1);
- PRE_REG_READ1(long, "chdir", const char *, path);
- PRE_MEM_RASCIIZ( "chdir(path)", ARG1 );
-}
-
-PRE(sys_chmod)
-{
- PRINT("chmod ( %#lx(%s), 0x%lx )", ARG1,(Char*)ARG1, ARG2 );
- PRE_REG_READ2(int, "chmod", char*, path, int, mode);
- PRE_MEM_RASCIIZ( "chmod(path)", ARG1 );
-}
-
-PRE(sys_chown)
-{
- PRINT("chown ( %#lx(%s), %ld, %ld )", ARG1,(Char*)ARG1, ARG2, ARG3 );
- PRE_REG_READ3(int, "chown", char*, path, int, owner, int, group);
- PRE_MEM_RASCIIZ( "chown(path)", ARG1 );
-}
-
-PRE(sys_close)
-{
- PRINT("close ( %ld )", ARG1);
- PRE_REG_READ1(void, "close", UInt, fd);
- /* If doing -d style logging (which is to fd=2), don't allow that
- to be closed. */
- if (ARG1 == 2/*stderr*/ && VG_(debugLog_getLevel)() > 0)
- SET_STATUS_Failure( VKI_EBADF );
-}
-
-PRE(sys_connext)
-{
- /* apparently undocumented. I don't know what it does. */
- /* Although /usr/include/net/proto_uipc.h does mention it.
- Args are apparently (int, caddr_t, int). I suspect the
- first arg is a fd and the third a flags value. */
- PRINT("connext (UNDOCUMENTED)( %ld, %#lx, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "connext", int, arg1, caddr_t*, arg2, int, arg3);
-}
-
-//--- PRE(sys_execve) ---//
-// Pre_read a char** argument.
-static void pre_argv_envp(Addr a, ThreadId tid, Char* s1, Char* s2)
-{
- while (True) {
- Addr a_deref;
- Addr* a_p = (Addr*)a;
- PRE_MEM_READ( s1, (Addr)a_p, sizeof(Addr) );
- a_deref = *a_p;
- if (0 == a_deref)
- break;
- PRE_MEM_RASCIIZ( s2, a_deref );
- a += sizeof(char*);
- }
-}
-static SysRes simple_pre_exec_check ( const HChar* exe_name,
- Bool trace_this_child )
-{
- Int fd, ret;
- SysRes res;
- Bool setuid_allowed;
-
- // Check it's readable
- res = VG_(open)(exe_name, VKI_O_RDONLY, 0);
- if (res.isError) {
- return res;
- }
- fd = res.res;
- VG_(close)(fd);
-
- // Check we have execute permissions. We allow setuid executables
- // to be run only in the case when we are not simulating them, that
- // is, they to be run natively.
- setuid_allowed = trace_this_child ? False : True;
- ret = VG_(check_executable)(NULL/*&is_setuid*/,
- (HChar*)exe_name, setuid_allowed);
- if (0 != ret) {
- return VG_(mk_SysRes_Error)(ret);
- }
- return VG_(mk_SysRes_Success)(0);
-}
-PRE(sys_execve)
-{
- Char* path = NULL; /* path to executable */
- Char** envp = NULL;
- Char** argv = NULL;
- Char** arg2copy;
- Char* launcher_basename = NULL;
- ThreadState* tst;
- Int i, j, tot_args;
- SysRes res;
- Bool trace_this_child;
-
- PRINT("sys_execve ( %#lx(%s), %#lx, %#lx )", ARG1, (Char*)ARG1, ARG2, ARG3);
- PRE_REG_READ3(vki_off_t, "execve",
- char *, filename, char **, argv, char **, envp);
- PRE_MEM_RASCIIZ( "execve(filename)", ARG1 );
- if (ARG2 != 0)
- pre_argv_envp( ARG2, tid, "execve(argv)", "execve(argv[i])" );
- if (ARG3 != 0)
- pre_argv_envp( ARG3, tid, "execve(envp)", "execve(envp[i])" );
-
- vg_assert(VG_(is_valid_tid)(tid));
- tst = VG_(get_ThreadState)(tid);
-
- /* Erk. If the exec fails, then the following will have made a
- mess of things which makes it hard for us to continue. The
- right thing to do is piece everything together again in
- POST(execve), but that's close to impossible. Instead, we make
- an effort to check that the execve will work before actually
- doing it. */
-
- /* Check that the name at least begins in client-accessible storage. */
- /* XXX: causes execve to fail for non-memcheck tools, presumably
- because ARG1 is thought to not to being in client-accessible
- storage due to inadequate address space tracking. May or may
- not be due to non-tracking of brk. */
- //if (!VG_(am_is_valid_for_client)( ARG1, 1, VKI_PROT_READ )) {
- // SET_STATUS_Failure( VKI_EFAULT );
- // return;
- //}
- if (ARG1 == 0 /* obviously bogus */) {
- SET_STATUS_Failure( VKI_EFAULT );
- }
-
- // Decide whether or not we want to follow along
- trace_this_child = VG_(should_we_trace_this_child)( (HChar**)ARG2 );
-
- // Do the important checks: it is a file, is executable, permissions are
- // ok, etc.
- res = simple_pre_exec_check( (const HChar*)ARG1, trace_this_child );
- if (res.isError) {
- SET_STATUS_Failure( res.err );
- return;
- }
-
- /* If we're tracing the child, and the launcher name looks bogus
- (possibly because launcher.c couldn't figure it out, see
- comments therein) then we have no option but to fail. */
- if (trace_this_child
- && (VG_(name_of_launcher) == NULL
- || VG_(name_of_launcher)[0] != '/')) {
- SET_STATUS_Failure( VKI_ECHILD ); /* "No child processes" */
- return;
- }
-
- /* After this point, we can't recover if the execve fails. */
- VG_(debugLog)(1, "syswrap", "Exec of %s\n", (Char*)ARG1);
-
- /* Resistance is futile. Nuke all other threads. POSIX mandates
- this. (Really, nuke them all, since the new process will make
- its own new thread.) */
- VG_(nuke_all_threads_except)( tid, VgSrc_ExitThread );
- VG_(reap_threads)(tid);
-
- // Set up the child's exe path.
- //
- if (trace_this_child) {
-
- // We want to exec the launcher. Get its pre-remembered path.
- path = VG_(name_of_launcher);
- // VG_(name_of_launcher) should have been acquired by m_main at
- // startup.
- vg_assert(path);
-
- launcher_basename = VG_(strrchr)(path, '/');
- if (launcher_basename == NULL || launcher_basename[1] == 0) {
- launcher_basename = path; // hmm, tres dubious
- } else {
- launcher_basename++;
- }
-
- } else {
- path = (Char*)ARG1;
- }
-
- // Set up the child's environment.
- //
- // Remove the valgrind-specific stuff from the environment so the
- // child doesn't get vgpreload_core.so, vgpreload_<tool>.so, etc.
- // This is done unconditionally, since if we are tracing the child,
- // the child valgrind will set up the appropriate client environment.
- // Nb: we make a copy of the environment before trying to mangle it
- // as it might be in read-only memory (this was bug #101881).
- //
- // Then, if tracing the child, set VALGRIND_LIB for it.
- //
- if (ARG3 == 0) {
- envp = NULL;
- } else {
- envp = VG_(env_clone)( (Char**)ARG3 );
- if (envp == NULL) goto hosed;
- VG_(env_remove_valgrind_env_stuff)( envp );
- }
-
- if (trace_this_child) {
- // Set VALGRIND_LIB in ARG3 (the environment)
- VG_(env_setenv)( &envp, VALGRIND_LIB, VG_(libdir));
- }
-
- // Set up the child's args. If not tracing it, they are
- // simply ARG2. Otherwise, they are
- //
- // [launcher_basename] ++ VG_(args_for_valgrind) ++ [ARG1] ++ ARG2[1..]
- //
- // except that the first VG_(args_for_valgrind_noexecpass) args
- // are omitted.
- //
- if (!trace_this_child) {
- argv = (Char**)ARG2;
- } else {
- vg_assert( VG_(args_for_valgrind_noexecpass) >= 0 );
- vg_assert( VG_(args_for_valgrind_noexecpass)
- <= VG_(sizeXA)( VG_(args_for_valgrind) ) );
- /* how many args in total will there be? */
- // launcher basename
- tot_args = 1;
- // V's args
- tot_args += VG_(sizeXA)( VG_(args_for_valgrind) );
- tot_args -= VG_(args_for_valgrind_noexecpass);
- // name of client exe
- tot_args++;
- // args for client exe, skipping [0]
- arg2copy = (Char**)ARG2;
- if (arg2copy && arg2copy[0]) {
- for (i = 1; arg2copy[i]; i++)
- tot_args++;
- }
- // allocate
- argv = VG_(malloc)( "syswrap-aix5.pre_sys_execve.1",
- (tot_args+1) * sizeof(HChar*) );
- if (argv == 0) goto hosed;
- // copy
- j = 0;
- argv[j++] = launcher_basename;
- for (i = 0; i < VG_(sizeXA)( VG_(args_for_valgrind) ); i++) {
- if (i < VG_(args_for_valgrind_noexecpass))
- continue;
- argv[j++] = * (HChar**) VG_(indexXA)( VG_(args_for_valgrind), i );
- }
- argv[j++] = (Char*)ARG1;
- if (arg2copy && arg2copy[0])
- for (i = 1; arg2copy[i]; i++)
- argv[j++] = arg2copy[i];
- argv[j++] = NULL;
- // check
- vg_assert(j == tot_args+1);
- }
-
- /* restore the DATA rlimit for the child */
- VG_(setrlimit)(VKI_RLIMIT_DATA, &VG_(client_rlimit_data));
-
- /*
- Set the signal state up for exec.
-
- We need to set the real signal state to make sure the exec'd
- process gets SIG_IGN properly.
-
- Also set our real sigmask to match the client's sigmask so that
- the exec'd child will get the right mask. First we need to
- clear out any pending signals so they they don't get delivered,
- which would confuse things.
-
- XXX This is a bug - the signals should remain pending, and be
- delivered to the new process after exec. There's also a
- race-condition, since if someone delivers us a signal between
- the sigprocmask and the execve, we'll still get the signal. Oh
- well.
- */
- {
- vki_sigset_t allsigs;
- vki_siginfo_t info;
-
- for (i = 1; i < VG_(max_signal); i++) {
- struct vki_sigaction sa;
- VG_(do_sys_sigaction)(i, NULL, &sa);
- if (sa.ksa_handler == VKI_SIG_IGN)
- VG_(sigaction)(i, &sa, NULL);
- else {
- sa.ksa_handler = VKI_SIG_DFL;
- VG_(sigaction)(i, &sa, NULL);
- }
- }
-
- VG_(sigfillset)(&allsigs);
- while(VG_(sigtimedwait_zero)(&allsigs, &info) > 0)
- ;
-
- VG_(sigprocmask)(VKI_SIG_SETMASK, &tst->sig_mask, NULL);
- }
-
- if (0) {
- Char **cpp;
- VG_(printf)("exec: %s\n", path);
- for (cpp = argv; cpp && *cpp; cpp++)
- VG_(printf)("argv: %s\n", *cpp);
- if (0)
- for (cpp = envp; cpp && *cpp; cpp++)
- VG_(printf)("env: %s\n", *cpp);
- }
-
- SET_STATUS_from_SysRes(
- VG_(do_syscall3)(__NR_execve, (UWord)path, (UWord)argv, (UWord)envp)
- );
-
- /* If we got here, then the execve failed. We've already made way
- too much of a mess to continue, so we have to abort. */
- hosed:
- vg_assert(FAILURE);
- VG_(message)(Vg_UserMsg, "execve(%#lx(%s), %#lx, %#lx) failed, errno %ld\n",
- ARG1, (Char*)ARG1, ARG2, ARG3, ERR);
- VG_(message)(Vg_UserMsg, "EXEC FAILED: I can't recover from "
- "execve() failing, so I'm dying.\n");
- VG_(message)(Vg_UserMsg, "Add more stringent tests in PRE(sys_execve), "
- "or work out how to recover.\n");
- VG_(exit)(101);
-}
-
-PRE(sys_finfo)
-{
- PRINT("finfo ( %#lx(%s), %ld, %#lx, %ld )",
- ARG1,(Char*)ARG1, ARG2, ARG3, ARG4);
- PRE_REG_READ4(int, "finfo",
- char*, Path1, int, cmd, void*, buffer, int, length);
- PRE_MEM_RASCIIZ( "finfo(Path1)", ARG1 );
- PRE_MEM_WRITE( "finfo(buffer)", ARG3, ARG4 );
-}
-POST(sys_finfo)
-{
- POST_MEM_WRITE( ARG3, ARG4 );
-}
-
-PRE(sys_fstatfs)
-{
- PRINT("sys_fstatfs ( %ld, %#lx )", ARG1, ARG2);
- PRE_REG_READ2(UWord, "fstatfs", UWord, fd, struct statfs *, buf);
- PRE_MEM_WRITE( "fstatfs(buf)", ARG2, sizeof(struct statfs) );
-}
-POST(sys_fstatfs)
-{
- POST_MEM_WRITE( ARG2, sizeof(struct statfs) );
-}
-
-PRE(sys_fstatx)
-{
- PRINT("fstatx ( %ld, %#lx, %ld, %ld )", ARG1, ARG2, ARG3, ARG4 );
- PRE_REG_READ4(Word, "fstatx", UWord, fd, void*, buf,
- UWord, len, UWord, cmd);
- PRE_MEM_WRITE( "fstatx(buf)", ARG2, ARG3 );
-}
-POST(sys_fstatx)
-{
- POST_MEM_WRITE( ARG2, ARG3 );
-}
-
-PRE(sys_fsync)
-{
- PRINT("fsync ( %ld )", ARG1);
- PRE_REG_READ1(int, "fsync", int, fd);
-}
-
-PRE(sys_getdirent)
-{
- *flags |= SfMayBlock;
- /* this is pretty much like 'read':
- getdirent(fd, buffer, nbytes) -> # actually read */
- PRINT("getdirent ( %ld, %#lx, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(Word, "getdirent", UWord, fd, UChar*, buf, UWord, count);
- PRE_MEM_WRITE( "getdirent(buf)", ARG2, ARG3 );
-}
-POST(sys_getdirent)
-{
- vg_assert(SUCCESS);
- POST_MEM_WRITE( ARG2, RES );
-}
-
-PRE(sys_getdirent64)
-{
- /* same as getdirent, from our point of view? */
- *flags |= SfMayBlock;
- /* this is pretty much like 'read':
- getdirent(fd, buffer, nbytes) -> # actually read */
- PRINT("getdirent64 ( %ld, %#lx, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(Word, "getdirent64", UWord, fd, UChar*, buf, UWord, count);
- PRE_MEM_WRITE( "getdirent64(buf)", ARG2, ARG3 );
-}
-POST(sys_getdirent64)
-{
- vg_assert(SUCCESS);
- POST_MEM_WRITE( ARG2, RES );
-}
-
-PRE(sys_getdomainname)
-{
- PRINT("getdomainname ( %#lx, %ld )", ARG1, ARG2 );
- PRE_MEM_WRITE( "getdomainname(buf)", ARG1, ARG2 );
-}
-POST(sys_getdomainname)
-{
- POST_MEM_WRITE( ARG1, ARG2 );
-}
-
-PRE(sys_getgidx)
-{
- PRINT("getgidx ( %ld )", ARG1);
- PRE_REG_READ1(UInt, "getgidx", long, arg1);
-}
-
-PRE(sys_getgroups)
-{
- PRINT("getgroups ( %ld, %#lx )", ARG1, ARG2);
- PRE_REG_READ2(long, "getgroups", int, size, gid_t *, list);
- if (ARG1 > 0)
- PRE_MEM_WRITE( "getgroups(list)", ARG2, ARG1 * sizeof(gid_t) );
-}
-POST(sys_getgroups)
-{
- vg_assert(SUCCESS);
- if (ARG1 > 0 && RES > 0)
- POST_MEM_WRITE( ARG2, RES * sizeof(gid_t) );
-}
-
-PRE(sys_gethostname)
-{
- PRINT("gethostname ( %#lx, %ld )", ARG1, ARG2);
- PRE_MEM_WRITE( "gethostname(buf)", ARG1, ARG2 );
-}
-POST(sys_gethostname)
-{
- POST_MEM_WRITE( ARG1, ARG2 );
-}
-
-PRE(sys_getpriv)
-{
- PRINT("getpriv (UNDOCUMENTED)(%ld, %#lx, %ld)", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "getpriv", int, arg1, void*, arg2, int, arg3);
- PRE_MEM_WRITE( "getpriv(arg2)", ARG2, 8 );
-}
-POST(sys_getpriv)
-{
- if (ARG2)
- POST_MEM_WRITE(ARG2, 8);
-}
-
-/* Note that this is used for both sys_getprocs and sys_getprocs64. I
- think that's correct - from the man page, the calling conventions
- look identical. */
-PRE(sys_getprocs)
-{
- PRINT("getprocs ( %#lx, %ld, %#lx, %ld, %#lx, %ld )",
- ARG1, ARG2, ARG3, ARG4, ARG5, ARG6 );
- PRE_REG_READ6(int, "getprocs",
- void*, processbuffer, long, processize,
- void*, filebuffer, long, filesize,
- void*, indexpointer, long, count);
-
- /* (processbuffer, processsize, filebuffer, filesize,
- indexpointer, count) */
- PRE_MEM_READ( "getprocs(IndexPointer)", ARG5, sizeof(UInt) );
- if (ARG1)
- PRE_MEM_WRITE( "getprocs(ProcessBuffer)", ARG1, ARG2 * ARG6 );
- if (ARG3)
- PRE_MEM_WRITE( "getprocs(FileBuffer)", ARG3, ARG4 * ARG6 );
-}
-POST(sys_getprocs)
-{
- vg_assert(SUCCESS);
- if (ARG1)
- POST_MEM_WRITE( ARG1, ARG2 * ARG6 );
- if (ARG3)
- POST_MEM_WRITE( ARG3, ARG4 * ARG6 );
-}
-
-PRE(sys_getrpid)
-{
- PRINT("getrpid ( %ld, %ld, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "getrpid", long, arg1, long, arg2, long, arg3);
-}
-
-PRE(sys_getsockopt)
-{
- PRINT("getsockopt ( %ld, %ld, %ld, %#lx, %#lx )",
- ARG1, ARG2, ARG3, ARG4, ARG5);
- PRE_REG_READ5(int, "getsockopt", int, socket, int, level,
- int, optionname,
- void*, optionval, int*, optionlen);
- if (ARG5) {
- PRE_MEM_READ( "getsockopt(optionlen)", ARG5, sizeof(UInt) );
- PRE_MEM_WRITE( "getsockopt(optionval)", ARG4, *(UInt*)ARG5 );
- }
-}
-POST(sys_getsockopt)
-{
- if (ARG5) {
- POST_MEM_WRITE( ARG5, sizeof(UInt) );
- POST_MEM_WRITE( ARG4, *(UInt*)ARG5 );
- }
-}
-
-PRE(sys_gettimerid)
-{
- PRINT("gettimerid ( %ld, %ld )", ARG1, ARG2);
- PRE_REG_READ2(int, "gettimerid", int, timertype, int, notifytype);
-}
-
-PRE(sys_getuidx)
-{
- PRINT("getuidx ( %ld )", ARG1);
- PRE_REG_READ1(UInt, "getuidx", UInt, arg1);
-}
-
-PRE(sys_incinterval)
-{
- PRINT("incinterval ( %ld, %#lx, %#lx )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "incinterval", int, timerid,
- struct itimerstruc_t*, value,
- struct itimerstruc_t*, ovalue);
- if (ARG2)
- PRE_MEM_READ( "incinterval(value)",
- ARG2, sizeof(struct itimerstruc_t));
- if (ARG3)
- PRE_MEM_WRITE( "incinterval(value)",
- ARG3, sizeof(struct itimerstruc_t));
-}
-POST(sys_incinterval)
-{
- if (ARG3)
- POST_MEM_WRITE( ARG3, sizeof(struct itimerstruc_t));
-}
-
-PRE(sys_kfcntl)
-{
- *flags |= SfMayBlock;
- switch (ARG2) {
- // These ones ignore ARG3.
- case F_GETFD:
- case F_GETFL:
- case F_GETOWN:
- PRINT("kfcntl ( %ld, %ld )", ARG1,ARG2);
- PRE_REG_READ2(long, "fcntl", unsigned int, fd, unsigned int, cmd);
- break;
-
- // These ones use ARG3 as "arg".
- case F_DUPFD:
- case F_SETFD:
- case F_SETFL:
- case F_SETOWN:
- PRINT("kfcntl[ARG3=='arg'] ( %ld, %ld, %ld )", ARG1,ARG2,ARG3);
- PRE_REG_READ3(long, "fcntl",
- unsigned int, fd, unsigned int, cmd, unsigned long, arg);
- break;
-
- // These ones use ARG3 as "lock".
-# if !defined(VGP_ppc64_aix5)
- case F_GETLK:
- case F_SETLK:
- case F_SETLKW:
-# endif
- case F_GETLK64:
- case F_SETLK64:
- case F_SETLKW64:
- PRINT("kfcntl[ARG3=='lock'] ( %ld, %ld, %#lx )", ARG1,ARG2,ARG3);
- PRE_REG_READ3(long, "fcntl",
- unsigned int, fd, unsigned int, cmd,
- struct flock64 *, lock);
- if (ARG3 && (ARG2 == F_GETLK || ARG2 == F_GETLK64))
- PRE_MEM_READ( "kfcntl(F_GETLK)", ARG3, sizeof(struct flock64) );
- break;
- }
-}
-POST(sys_kfcntl)
-{
- // if (ARG2 == VKI_F_DUPFD) {
- // if (!ML_(fd_allowed)(RES, "fcntl(DUPFD)", tid, True)) {
- // VG_(close)(RES);
- // SET_STATUS_Failure( VKI_EMFILE );
- // } else {
- // if (VG_(clo_track_fds))
- // record_fd_open_named(tid, RES);
- // }
- // }
- if (ARG3 && (ARG2 == F_GETLK || ARG2 == F_GETLK64))
- POST_MEM_WRITE( ARG3, sizeof(struct flock64) );
-}
-
-/* COG; can this be moved inside the pre-handler? */
-static vki_sigset_t fork_saved_mask;
-PRE(sys_kfork) /* COPY OF GENERIC */
-{
- vki_sigset_t mask;
-
- PRINT("kfork ( )");
- PRE_REG_READ0(long, "fork");
-
- /* Block all signals during fork, so that we can fix things up in
- the child without being interrupted. */
- VG_(sigfillset)(&mask);
- VG_(sigprocmask)(VKI_SIG_SETMASK, &mask, &fork_saved_mask);
-
- VG_(do_atfork_pre)(tid);
-
- SET_STATUS_from_SysRes( VG_(do_syscall0)(__NR_fork) );
-
- if (SUCCESS && RES == 0) {
- /* child */
- VG_(do_atfork_child)(tid);
-
- /* restore signal mask */
- VG_(sigprocmask)(VKI_SIG_SETMASK, &fork_saved_mask, NULL);
-
- /* If --child-silent-after-fork=yes was specified, set the
- logging file descriptor to an 'impossible' value. This is
- noticed by send_bytes_to_logging_sink in m_libcprint.c, which
- duly stops writing any further logging output. */
- if (!VG_(logging_to_socket) && VG_(clo_child_silent_after_fork))
- VG_(clo_log_fd) = -1;
- }
- else
- if (SUCCESS && RES > 0) {
- /* parent */
- VG_(do_atfork_parent)(tid);
-
- PRINT(" fork: process %d created child %lu\n", VG_(getpid)(), RES);
-
- /* restore signal mask */
- VG_(sigprocmask)(VKI_SIG_SETMASK, &fork_saved_mask, NULL);
- }
-}
-
-PRE(sys_kftruncate)
-{
- PRINT("kftruncate (BOGUS HANDLER)");
-}
-
-PRE(sys_kgetsidx)
-{
- PRINT("kgetsidx ( %ld )", ARG1);
- PRE_REG_READ1(Word, "kgetsidx", Word, arg1);
-}
-
-PRE(sys_kill)
-{
- PRINT("kill ( %ld, %ld )", ARG1, ARG2);
- PRE_REG_READ2(int, "kill", int, pid, int, signal);
-}
-
-PRE(sys_kioctl)
-{
- *flags |= SfMayBlock;
- PRINT("kioctl ( %ld, %#lx, %#lx, %#lx )", ARG1, ARG2, ARG3, ARG4);
- PRE_REG_READ4(Word, "ioctl", Word, fd,
- Word, command, Word, arg, Word, ext);
- switch (ARG2 /* request */) {
- case 0x5800/*TXISATTY*/:
- case 0x5801/*TXTTYNAME*/:
- break;
- case 0x412:/*no idea what any of these are*/
- case 0x430:
- case 0x431:
- case 0x432:
- case 0x441:
- case 0x442:
- case 0x462:
- case 0x480:
- case 0x482:
- case 0x738:
- case 0x736:
- case 0x73B:
- case 0x73C:
- case 0x73D:
- case 0x73E:
- case 0x5401:
- case 0x5403:
- case 0xFF01/*no_idea_at_all_what_this_is*/:
- break;
- /* We don't have any specific information on it, so
- try to do something reasonable based on direction and
- size bits.
-
- According to Simon Hausmann, _IOC_READ means the kernel
- writes a value to the ioctl value passed from the user
- space and the other way around with _IOC_WRITE. */
- default: {
- UInt dir = _VKI_IOC_DIR(ARG2);
- UInt size = _VKI_IOC_SIZE(ARG2);
- if (VG_(strstr)(VG_(clo_sim_hints), "lax-ioctls") != NULL) {
- /*
- * Be very lax about ioctl handling; the only
- * assumption is that the size is correct. Doesn't
- * require the full buffer to be initialized when
- * writing. Without this, using some device
- * drivers with a large number of strange ioctl
- * commands becomes very tiresome.
- */
- } else if (/* size == 0 || */ dir == _VKI_IOC_NONE) {
- static Int moans = 5;
- if (moans > 0 && !VG_(clo_xml)) {
- moans--;
- VG_(message)(Vg_UserMsg,
- "Warning: noted but unhandled ioctl 0x%lx"
- " with no size/direction hints\n",
- ARG2);
- VG_(message)(Vg_UserMsg,
- " This could cause spurious value errors"
- " to appear.\n");
- VG_(message)(Vg_UserMsg,
- " See README_MISSING_SYSCALL_OR_IOCTL for "
- "guidance on writing a proper wrapper.\n" );
- }
- } else {
- if ((dir & _VKI_IOC_WRITE) && size > 0)
- PRE_MEM_READ( "ioctl(generic)", ARG3, size);
- if ((dir & _VKI_IOC_READ) && size > 0)
- PRE_MEM_WRITE( "ioctl(generic)", ARG3, size);
- }
- break;
- }
- } /* switch */
-}
-POST(sys_kioctl)
-{
- switch (ARG2 /*request*/) {
- case 0xFF01:
- /* 100% kludge. I have no idea what this ioctl is. IOCINFO
- ? But at a guess I'd say it returns some kind of info
- from the kernel. */
- if (ARG3) POST_MEM_WRITE(ARG3, 16);
- break;
- case 0x738: /* Shows up in MPI applications. */
- if (ARG3) POST_MEM_WRITE(ARG3, 4*sizeof(Word));
- break;
- case 0x736: /* Shows up in MPI applications. */
- case 0x73B: /* Shows up in MPI applications. */
- case 0x73C: /* Shows up in MPI applications. */
- if (ARG3) POST_MEM_WRITE(ARG3, 16);
- /* in fact only 4 needed, but being conservative */
- break;
-
- case 0x5401:
- /* some kind of tty thing */
- if (ARG3) POST_MEM_WRITE(ARG3, 32);
- break;
-
- case 0x5801/*TXTTYNAME*/:
- /* who knows if this is right. Presumably an ascii string is
- written into the buffer specified by ARG3, but how long is
- that buffer? */
- if (ARG3) POST_MEM_WRITE(ARG3, 16);
- break;
-
- case 0x412:
- case 0x430:
- case 0x431:
- case 0x432:
- case 0x441:
- case 0x442:
- case 0x462:
- case 0x480:
- case 0x482:
- case 0x73D:
- case 0x73E:
- case 0x5800/*TXISATTY*/:
- case 0x5403:
- break;
- /* We don't have any specific information on it, so
- try to do something reasonable based on direction and
- size bits.
-
- According to Simon Hausmann, _IOC_READ means the kernel
- writes a value to the ioctl value passed from the user
- space and the other way around with _IOC_WRITE. */
- default: {
- UInt dir = _VKI_IOC_DIR(ARG2);
- UInt size = _VKI_IOC_SIZE(ARG2);
- if (size > 0 && (dir & _VKI_IOC_READ)
- && RES == 0
- && ARG3 != (Addr)NULL)
- POST_MEM_WRITE(ARG3, size);
- break;
- }
- }
-}
-
-PRE(sys_klseek)
-{
- PRINT("klseek ( %ld, %ld, %ld, %#lx )", ARG1, ARG2, ARG3, ARG4);
- PRE_REG_READ4(long, "klseek",
- long, fd, long, offset, long, whence, void*, arg4);
- /* XXX: looks like 4th arg is a pointer to something. Is it
- read or written by the kernel? */
-}
-
-PRE(sys_knlist)
-{
- PRINT("knlist (BOGUS HANDLER)");
-}
-
-PRE(sys_kpread)
-{
- *flags |= SfMayBlock;
- PRINT("sys_kpread ( %ld, %#lx, %llu, %lld )",
- ARG1, ARG2, (ULong)ARG3, (ULong)ARG4);
- PRE_REG_READ4(ssize_t, "kpread",
- unsigned int, fd, char *, buf,
- vki_size_t, count, long, offset);
- PRE_MEM_WRITE( "kpread(buf)", ARG2, ARG3 );
-}
-POST(sys_kpread)
-{
- vg_assert(SUCCESS);
- if (RES > 0) {
- POST_MEM_WRITE( ARG2, RES );
- }
-}
-
-PRE(sys_kread)
-{
- *flags |= SfMayBlock;
- PRINT("sys_read ( %ld, %#lx, %llu )", ARG1, ARG2, (ULong)ARG3);
- PRE_REG_READ3(ssize_t, "read",
- unsigned int, fd, char *, buf, vki_size_t, count);
- //zz if (!ML_(fd_allowed)(ARG1, "read", tid, False))
- //zz SET_STATUS_Failure( VKI_EBADF );
- //zz else
- PRE_MEM_WRITE( "read(buf)", ARG2, ARG3 );
-}
-POST(sys_kread)
-{
- vg_assert(SUCCESS);
- POST_MEM_WRITE( ARG2, RES );
-}
-
-PRE(sys_kreadv)
-{
- Int i;
- struct vki_iovec * vec;
- *flags |= SfMayBlock;
- /* ssize_t readvx ( int fd, struct iovec*, int iovCount, int extension ) */
- PRINT("kreadv ( %ld, %#lx, %ld, %#lx )", ARG1, ARG2, ARG3, ARG4);
- PRE_REG_READ4(ssize_t, "kreadv",
- unsigned long, fd, const struct iovec *, vector,
- unsigned long, iovCount, unsigned long, extension);
- //zz if (!ML_(fd_allowed)(ARG1, "readv", tid, False)) {
- //zz SET_STATUS_Failure( VKI_EBADF );
- //zz } else {
- PRE_MEM_READ( "kreadv(vector)", ARG2, ARG3 * sizeof(struct vki_iovec) );
- if (ARG2 != 0) {
- /* ToDo: don't do any of the following if the vector is invalid */
- vec = (struct vki_iovec *)ARG2;
- for (i = 0; i < (Int)ARG3; i++)
- PRE_MEM_WRITE( "kreadv(vector[...])",
- (Addr)vec[i].iov_base, vec[i].iov_len );
- }
- //zz }
-}
-POST(sys_kreadv)
-{
- vg_assert(SUCCESS);
- if (RES > 0) {
- Int i;
- struct vki_iovec * vec = (struct vki_iovec *)ARG2;
- Int remains = RES;
-
- /* RES holds the number of bytes read. */
- for (i = 0; i < (Int)ARG3; i++) {
- Int nReadThisBuf = vec[i].iov_len;
- if (nReadThisBuf > remains) nReadThisBuf = remains;
- POST_MEM_WRITE( (Addr)vec[i].iov_base, nReadThisBuf );
- remains -= nReadThisBuf;
- if (remains < 0) VG_(core_panic)("readv: remains < 0");
- }
- }
-}
-
-PRE(sys_kthread_ctl)
-{
- *flags |= SfMayBlock;
- PRINT("kthread_ctl (BOGUS HANDLER)");
-}
-
-PRE(sys_ktruncate)
-{
- PRINT("ktruncate( %#lx(%s), %lx, %lx )", ARG1,(Char*)ARG1, ARG2, ARG3 );
- PRE_REG_READ3(int, "ktruncate", char*, path, long, arg2, long, arg3 );
- PRE_MEM_RASCIIZ( "ktruncate(path)", ARG1 );
-}
-
-PRE(sys_kwaitpid)
-{
- /* Note: args 1 and 2 (status, pid) opposite way round
- from generic handler */
- *flags |= SfMayBlock;
- PRINT("kwaitpid ( %#lx, %ld, %ld, %#lx, %#lx )", ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ3(long, "waitpid",
- unsigned int *, status, int, pid, int, options);
-
- if (ARG1 != (Addr)NULL)
- PRE_MEM_WRITE( "kwaitpid(status)", ARG1, sizeof(int) );
-}
-POST(sys_kwaitpid)
-{
- if (ARG1 != (Addr)NULL)
- POST_MEM_WRITE( ARG1, sizeof(int) );
-}
-
-PRE(sys_kwrite)
-{
- //zz Bool ok;
- *flags |= SfMayBlock;
- PRINT("sys_kwrite ( %ld, %#lx, %llu )", ARG1, ARG2, (ULong)ARG3);
- PRE_REG_READ3(ssize_t, "kwrite",
- unsigned int, fd, const char *, buf, vki_size_t, count);
- /* check to see if it is allowed. If not, try for an exemption from
- --sim-hints=enable-outer (used for self hosting). */
- //zz ok = ML_(fd_allowed)(ARG1, "write", tid, False);
- //zz if (!ok && ARG1 == 2/*stderr*/
- //zz && VG_(strstr)(VG_(clo_sim_hints),"enable-outer"))
- //zz ok = True;
- //zz if (!ok)
- //zz SET_STATUS_Failure( VKI_EBADF );
- //zz else
- PRE_MEM_READ( "write(buf)", ARG2, ARG3 );
-}
-
-PRE(sys_kwritev)
-{
- PRINT("kwritev (BOGUS HANDLER)");
-}
-
-PRE(sys_listen)
-{
- PRINT("listen (BOGUS HANDLER)");
-}
-
-PRE(sys_loadbind)
-{
- PRINT("loadbind( %ld, %#lx, %#lx )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "loadbind", int, flag,
- void*, ExportPointer, void*, ImportPointer);
-}
-
-PRE(sys_loadquery)
-{
- /* loadquery ( int flags, void* buffer, unsigned int bufferlength ) */
- PRINT("loadquery ( %#lx, %#lx, %ld )", ARG1, ARG2, ARG3);
- PRE_MEM_WRITE( "loadquery(buf)", ARG2, ARG3 );
-}
-POST(sys_loadquery)
-{
- vg_assert(SUCCESS);
- POST_MEM_WRITE( ARG2, ARG3 );
-}
-
-PRE(sys_lseek)
-{
- PRINT("lseek (%ld, %ld, %ld)", ARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "lseek", long, fd, long, offset, long, whence);
-}
-
-PRE(sys_mkdir)
-{
- PRINT("mkdir (%#lx(%s), %#lx)", ARG1,(Char*)ARG1, ARG2);
- PRE_REG_READ2(int, "mkdir", char*, path, int, mode);
- PRE_MEM_RASCIIZ( "mkdir(path)", ARG1 );
-}
-
-PRE(sys_mmap)
-{
- PRINT("mmap ( %#lx, %ld, %#lx, %#lx, %ld, %ld )",
- ARG1, ARG2, ARG3, ARG4, ARG5, ARG6);
- PRE_REG_READ6(void*, "mmap", void*, addr, int, len,
- int, prot, int, flags, int, fd, int, off);
-}
-POST(sys_mmap)
-{
- vg_assert(SUCCESS);
- Addr addr = (Addr)RES;
- UWord len = (UWord)ARG2;
- UWord prot = (UWord)ARG3;
- UWord flags = (UWord)ARG4;
- Bool r = (prot & VKI_PROT_READ) > 0;
- Bool w = (prot & VKI_PROT_WRITE) > 0;
- Bool x = (prot & VKI_PROT_EXEC) > 0;
- VG_TRACK( new_mem_mmap, addr, len, r,w,x, 0/*di_handle*/ );
- Bool d = VG_(am_notify_client_mmap)( addr, len, prot, flags,
- 0/*fake fd*/, 0/*fake offset*/);
- if (d)
- VG_(discard_translations)( addr, len, "POST(sys_mmap)" );
-}
-
-PRE(sys_mntctl)
-{
- PRINT("mntctl ( %ld, %ld, %#lx )", ARG1, ARG2, ARG3 );
- PRE_REG_READ3(long, "mntctl", long, command, long, size, char*, buffer);
- PRE_MEM_WRITE( "mntctl(buffer)", ARG3, ARG2 );
-}
-POST(sys_mntctl)
-{
- vg_assert(SUCCESS);
- if (RES == 0) {
- /* Buffer too small. First word is the real required size. */
- POST_MEM_WRITE( ARG3, sizeof(Word) );
- } else {
- /* RES is the number of struct vmount's written to the buf. But
- these are variable length and to find the end would require
- inspecting each in turn. So be simple and just mark the
- entire buffer as defined. */
- POST_MEM_WRITE( ARG3, ARG2 );
- }
-}
-
-PRE(sys_mprotect)
-{
- PRINT("mprotect (BOGUS HANDLER)( %#lx, %ld, %#lx )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "mprotect", void*, addr, long, len, long, prot);
-}
-POST(sys_mprotect)
-{
- Bool d;
- vg_assert(SUCCESS);
- Addr addr = ARG1;
- UWord len = ARG2;
- UWord prot = ARG3;
- d = VG_(am_notify_mprotect)( addr, len, prot );
- if (d)
- VG_(discard_translations)( addr, len, "POST(sys_mprotect)" );
-}
-
-PRE(sys_munmap)
-{
- PRINT("munmap ( %#lx, %ld )", ARG1, ARG2);
- PRE_REG_READ2(int, "munmap", void*, addr, long, len);
-}
-POST(sys_munmap)
-{
- Bool d;
- vg_assert(SUCCESS);
- Addr addr = ARG1;
- UWord len = ARG2;
- VG_TRACK( die_mem_munmap, addr, len );
- d = VG_(am_notify_munmap)( addr, len );
- if (d)
- VG_(discard_translations)( addr, len, "POST(sys_munmap)" );
-}
-
-PRE(sys_naccept)
-{
- PRINT("naccept (%ld, %#lx, %#lx)", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "naccept", int, socket, char*, addr, int*, addrlen);
- PRE_MEM_READ( "naccept(addrlen)", ARG3, sizeof(UInt) );
- PRE_MEM_WRITE( "naccept(addr)", ARG2, *(UInt*)ARG3 );
-}
-POST(sys_naccept)
-{
- POST_MEM_WRITE( ARG3, sizeof(UInt) );
- POST_MEM_WRITE( ARG2, *(UInt*)ARG3 );
-}
-
-PRE(sys_ngetpeername)
-{
- PRINT("ngetpeername ( %ld, %#lx, %#lx )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "ngetpeername", int, fd, char*, name, int*, namelen);
- PRE_MEM_READ( "ngetpeername(namelen)", ARG3, sizeof(UInt) );
- PRE_MEM_WRITE( "ngetpeername(name)", ARG2, *(UInt*)ARG3 );
-}
-POST(sys_ngetpeername)
-{
- POST_MEM_WRITE( ARG3, sizeof(UInt) );
- POST_MEM_WRITE( ARG2, *(UInt*)ARG3 );
-}
-
-PRE(sys_ngetsockname)
-{
- PRINT("ngetsockname ( %ld, %#lx, %#lx )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "ngetsockname", int, fd, char*, name, int*, namelen);
- PRE_MEM_READ( "ngetsockname(namelen)", ARG3, sizeof(UInt) );
- PRE_MEM_WRITE( "ngetsockname(name)", ARG2, *(UInt*)ARG3 );
-}
-POST(sys_ngetsockname)
-{
- POST_MEM_WRITE( ARG3, sizeof(UInt) );
- POST_MEM_WRITE( ARG2, *(UInt*)ARG3 );
-}
-
-PRE(sys_nrecvfrom)
-{
- *flags |= SfMayBlock;
- PRINT("nrecvfrom ( %ld, %#lx, %ld, %ld, %#lx, %#lx )",
- ARG1, ARG2, ARG3, ARG4, ARG5, ARG6 );
- PRE_REG_READ6(ssize_t, "nrecvfrom",
- int, s, void*, buf, size_t, len, int, flags,
- void*, from, UInt*, fromlen);
- PRE_MEM_WRITE( "nrecvfrom(buf)", ARG2, ARG3 );
- if (ARG5) {
- PRE_MEM_READ( "nrecvfrom(fromlen)", ARG6, sizeof(UInt) );
- PRE_MEM_WRITE( "nrecvfrom(from)", ARG5, *(UInt*)ARG6 );
- }
-}
-POST(sys_nrecvfrom)
-{
- POST_MEM_WRITE( ARG2, RES );
- if (ARG5) {
- POST_MEM_WRITE(ARG6, sizeof(UInt));
- POST_MEM_WRITE(ARG5, *(UInt*)ARG6);
- }
-}
-
-PRE(sys_nrecvmsg)
-{
- *flags |= SfMayBlock;
- PRINT("nrecvmsg(BOGUS HANDLER)( %ld, %#lx, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "nrecvmsg", long, arg1, void*, arg2, long, arg3);
-}
-
-PRE(sys_nsendmsg)
-{
- *flags |= SfMayBlock;
- PRINT("nsendmsg(BOGUS HANDLER)( %ld, %#lx, %ld )", ARG1, ARG2, ARG3);
-}
-
-PRE(sys_open) /* XXX CoG */
-{
- //zz HChar name[30];
- //zz SysRes sres;
-
- if (ARG2 & VKI_O_CREAT) {
- // 3-arg version
- PRINT("sys_open ( %#lx(%s), %#lx, %ld )",ARG1,(Char*)ARG1,ARG2,ARG3);
- PRE_REG_READ3(long, "open",
- const char *, filename, int, flags, int, mode);
- } else {
- // 2-arg version
- PRINT("sys_open ( %#lx(%s), %#lx )",ARG1,(Char*)ARG1,ARG2);
- PRE_REG_READ2(long, "open",
- const char *, filename, int, flags);
- }
- PRE_MEM_RASCIIZ( "open(filename)", ARG1 );
-
- //zz /* Handle the case where the open is of /proc/self/cmdline or
- //zz /proc/<pid>/cmdline, and just give it a copy of the fd for the
- //zz fake file we cooked up at startup (in m_main). Also, seek the
- //zz cloned fd back to the start. */
- //zz
- //zz VG_(sprintf)(name, "/proc/%d/cmdline", VG_(getpid)());
- //zz if (ML_(safe_to_deref)( (void*)ARG1, 1 )
- //zz && (VG_(strcmp)((Char *)ARG1, name) == 0
- //zz || VG_(strcmp)((Char *)ARG1, "/proc/self/cmdline") == 0)) {
- //zz sres = VG_(dup)( VG_(cl_cmdline_fd) );
- //zz SET_STATUS_from_SysRes( sres );
- //zz if (!sres.isError) {
- //zz OffT off = VG_(lseek)( sres.res, 0, VKI_SEEK_SET );
- //zz if (off < 0)
- //zz SET_STATUS_Failure( VKI_EMFILE );
- //zz }
- //zz return;
- //zz }
-
- /* Otherwise handle normally */
- *flags |= SfMayBlock;
-}
-POST(sys_open)
-{
- vg_assert(SUCCESS);
- //zz if (!ML_(fd_allowed)(RES, "open", tid, True)) {
- //zz VG_(close)(RES);
- //zz SET_STATUS_Failure( VKI_EMFILE );
- //zz } else {
- //zz if (VG_(clo_track_fds))
- //zz ML_(record_fd_open_with_given_name)(tid, RES, (Char*)ARG1);
- //zz }
-}
-
-PRE(sys_pipe)
-{
- PRINT("sys_pipe ( %#lx )", ARG1);
- PRE_REG_READ1(int, "pipe", int *, filedes);
- PRE_MEM_WRITE( "pipe(filedes)", ARG1, 2*sizeof(int) );
-}
-POST(sys_pipe)
-{
- //zz Int *p = (Int *)ARG1;
-
- //zz if (!ML_(fd_allowed)(p[0], "pipe", tid, True) ||
- //zz !ML_(fd_allowed)(p[1], "pipe", tid, True)) {
- //zz VG_(close)(p[0]);
- //zz VG_(close)(p[1]);
- //zz SET_STATUS_Failure( VKI_EMFILE );
- //zz } else {
- POST_MEM_WRITE( ARG1, 2*sizeof(int) );
- //zz if (VG_(clo_track_fds)) {
- //zz ML_(record_fd_open_nameless)(tid, p[0]);
- //zz ML_(record_fd_open_nameless)(tid, p[1]);
- //zz }
- //zz }
-}
-
-PRE(sys_privcheck)
-{
- PRINT("privcheck ( %ld )", ARG1);
- PRE_REG_READ1(int, "privcheck", int, arg1);
-}
-
-PRE(sys_readlink)
-{
- PRINT("readlink ( 0x%lx(%s),0x%lx,%ld )", ARG1,(Char*)ARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "readlink",
- const char *, path, char *, buf, int, bufsiz);
- PRE_MEM_RASCIIZ( "readlink(path)", ARG1 );
- PRE_MEM_WRITE( "readlink(buf)", ARG2,ARG3 );
-}
-POST(sys_readlink)
-{
- POST_MEM_WRITE( ARG2, RES + 1 );
-}
-
-PRE(sys_recv)
-{
- *flags |= SfMayBlock;
- PRINT("recv ( %ld, %#lx, %ld, %ld )",
- ARG1, ARG2, ARG3, ARG4);
- PRE_REG_READ4(int, "recv", int, fd, void*, buf, int, len, int, flags);
- PRE_MEM_WRITE( "recv(buf)", ARG2, ARG3);
-}
-POST(sys_recv)
-{
- if (RES > 0)
- POST_MEM_WRITE(ARG2, RES);
-}
-
-PRE(sys_rename)
-{
- *flags |= SfMayBlock;
- PRINT( "rename ( %#lx(%s), %#lx(%s) )", ARG1,(Char*)ARG1, ARG2,(Char*)ARG2 );
- PRE_REG_READ2(int, "rename", char*, frompath, char*, topath);
- PRE_MEM_RASCIIZ( "rename(frompath)", ARG1 );
- PRE_MEM_RASCIIZ( "rename(topath)", ARG2 );
-}
-
-PRE(sys_sbrk)
-{
- PRINT("sbrk (BOGUS HANDLER)( %#lx )", ARG1);
- PRE_REG_READ1(long, "sbrk", long, arg1);
- /* After a zero sbrk, disallow aspacem from doing sbrk, since libc
- might rely on the value returned by this syscall. */
- /* 1 Oct 06: not currently used (aspacemgr-aix5.c ignores it) */
- VG_(am_aix5_sbrk_allowed) = toBool(ARG1 != 0);
- /* Disallow libc from moving the brk backwards as that might trash
- SkPreAlloc sections acquired by aspacem from previous uses of
- sbrk. */
- if (ARG1 < 0)
- ARG1 = 0;
- /* Do this as a sync syscall, so the sbrk_allowed flag gets turned
- back on ASAP. Typically libc does sbrk(0) and then sbrk(x > 0)
- in quick succession. Although surely it should hold some kind
- of lock at that point, else it cannot safely use the result from
- the first sbrk call to influence the second one? */
- *flags &= ~SfMayBlock;
-}
-POST(sys_sbrk)
-{
- vg_assert(SUCCESS);
- handle_sbrk(ARG1);
-}
-
-PRE(sys_sched_get_priority_max)
-{
- PRINT("sched_get_priority_max ( %ld )", ARG1);
- PRE_REG_READ1(int, "sched_get_priority_max", int, arg1);
-}
-
-PRE(sys_sem_destroy)
-{
- PRINT("sem_destroy ( %#lx )", ARG1);
- PRE_REG_READ1(int, "sem_destroy", sem_t*, sem);
- PRE_MEM_READ( "sem_destroy(sem)", ARG1, sizeof(sem_t) );
-}
-
-PRE(sys_sem_init)
-{
- PRINT("sem_init ( %#lx, %ld, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "sem_init", sem_t*, sem, int, pshared, int, value);
- PRE_MEM_WRITE( "sem_init(sem)", ARG1, sizeof(sem_t) );
-}
-POST(sys_sem_init)
-{
- POST_MEM_WRITE( ARG1, sizeof(sem_t) );
-}
-
-PRE(sys_sem_post)
-{
- PRINT("sem_post ( %#lx )", ARG1);
- PRE_REG_READ1(int, "sem_post", sem_t*, sem);
- PRE_MEM_READ("sem_post(sem)", ARG1, sizeof(sem_t));
-}
-POST(sys_sem_post)
-{
- POST_MEM_WRITE(ARG1, sizeof(sem_t));
-}
-
-PRE(sys_send)
-{
- *flags |= SfMayBlock;
- PRINT("send (BOGUS HANDLER)( %ld, %#lx, %ld, %ld )",
- ARG1, ARG2, ARG3, ARG4);
-}
-
-PRE(sys_setgid)
-{
- PRINT("setgid ( %ld )", ARG1);
- PRE_REG_READ1(void, "setgid", int, uid);
-}
-
-PRE(sys_setsockopt)
-{
- PRINT("setsockopt ( %ld, %ld, %ld, %#lx, %ld )",
- ARG1,ARG2,ARG3,ARG4,ARG5 );
- PRE_REG_READ5(long, "setsockopt",
- long, socket, long, level, long, optionname,
- void*, optionvalue, long, optlen);
- if (ARG4)
- PRE_MEM_READ( "setsockopt(optionvalue)", ARG4, ARG5 );
-}
-
-PRE(sys_setuid)
-{
- PRINT("setuid ( %ld )", ARG1);
- PRE_REG_READ1(void, "setuid", int, uid);
-}
-
-static UWord get_shm_size ( Word shmid )
-{
- SysRes res;
- struct shmid_ds buf;
- vg_assert(__NR_AIX5_shmctl != __NR_AIX5_UNKNOWN);
- res = VG_(do_syscall3)(__NR_AIX5_shmctl, shmid, IPC_STAT, (UWord)&buf);
- if (0)
- VG_(printf)("XXX: shm_size(%ld) = %ld %ld\n", shmid, res.res, res.err);
- if (res.isError) {
- if (0)
- VG_(printf)("XXX: shm_size(shmid = %ld): FAILED\n", shmid);
- return 0* 4096;
- } else {
- return buf.shm_segsz;
- }
- /* fails with 22 and 13 (22 = EINVAL, Invalid argument,
- 13 = EACCES, Permission denied) */
- /* shmat (4, 0x0, 0x1800) --> Success(0x40000000)
- XXX: shm_size(4) = -1 22
- shmat: seg size = 0
- XXX: shm_size(4) = -1 22
-
- shmat (5, 0x0, 0x1800) --> Success(0x50000000)
- XXX: shm_size(5) = -1 13
- shmat: seg size = 0
- XXX: shm_size(5) = -1 13
-
- shmat (4, 0x0, 0x1800) --> Success(0x40000000)
- XXX: shm_size(4) = -1 22
- shmat: seg size = 0
- XXX: shm_size(4) = -1 22
- */
-}
-PRE(sys_shmat)
-{
- UWord segmentSize;
- /* void* shmat ( int shmid, const void* shmaddr, int flags ) */
- PRINT("shmat (%ld, %#lx, %#lx)", ARG1, ARG2, ARG3);
- PRE_REG_READ3(void*, "shmat", int, shmid, void*, shmaddr, int, flags);
- segmentSize = get_shm_size( ARG1 );
- if (0) VG_(printf)("shmat: seg size = %lu\n", segmentSize);
-}
-POST(sys_shmat)
-{
- UInt segmentSize;
- vg_assert(SUCCESS);
- vg_assert(RES != -1L);
- segmentSize = get_shm_size ( ARG1 );
- if ( segmentSize > 0 ) {
- UInt prot = VKI_PROT_READ|VKI_PROT_WRITE;
- Bool d;
-
- if (ARG2 & SHM_RDONLY)
- prot &= ~VKI_PROT_WRITE;
-
- d = VG_(am_notify_client_shmat)( RES, VG_PGROUNDUP(segmentSize), prot );
-
- /* we don't distinguish whether it's read-only or
- * read-write -- it doesn't matter really. */
- VG_TRACK( new_mem_mmap, RES, segmentSize, True, True, False, 0/*di_handle*/ );
- if (d)
- VG_(discard_translations)( (Addr64)RES,
- (ULong)VG_PGROUNDUP(segmentSize),
- "ML_(generic_POST_sys_shmat)" );
- }
-}
-
-PRE(sys_shmctl)
-{
- PRINT("shmctl ( %ld, %ld, %#lx )", ARG1, ARG2, ARG3 );
- PRE_REG_READ3(int, "shmctl", int, shmid, int, command, void*, buffer);
- if (ARG3)
- PRE_MEM_WRITE( "shmctl(buffer)", ARG3, sizeof(struct shmid_ds) );
-}
-POST(sys_shmctl)
-{
- if ((ARG3) && ARG2 == IPC_STAT)
- POST_MEM_WRITE( ARG3, sizeof(struct shmid_ds) );
-}
-
-PRE(sys_shmdt)
-{
- PRINT("shmdt ( %#lx )", ARG1);
- PRE_REG_READ1(long, "shmdt", void*, address);
-}
-POST(sys_shmdt)
-{
- NSegment const*const s = VG_(am_find_nsegment)(ARG1);
-
- if (s != NULL) {
- Addr s_start = s->start;
- SizeT s_len = s->end+1 - s->start;
- Bool d;
-
- vg_assert(s->kind == SkShmC && s->start == ARG1);
-
- d = VG_(am_notify_munmap)(s_start, s_len);
- /* s is now invalid; do not use after here */
- VG_TRACK( die_mem_munmap, s_start, s_len );
- if (d)
- VG_(discard_translations)( (Addr64)s_start,
- (ULong)s_len,
- "ML_(generic_POST_sys_shmdt)" );
- }
-}
-
-PRE(sys_shmget)
-{
- PRINT("shmget ( %ld, %ld, %ld )", ARG1, ARG2, ARG3 );
- PRE_REG_READ3(int, "shmget", key_t, key, size_t, size, int, shmFlag);
-}
-
-PRE(sys_shutdown)
-{
- PRINT("shutdown (BOGUS HANDLER)");
-}
-
-PRE(sys_sigcleanup)
-{
- PRINT("sigcleanup (UNDOCUMENTED)");
-}
-
-PRE(sys_sigprocmask)
-{
- PRINT("sigprocmask ( %ld, %#lx, %#lx )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(long, "sigprocmask",
- int, how, vki_sigset_t *, set, vki_sigset_t *, oldset);
- if (ARG2 != 0)
- PRE_MEM_READ( "sigprocmask(set)", ARG2, sizeof(vki_sigset_t));
- if (ARG3 != 0)
- PRE_MEM_WRITE( "sigprocmask(oldset)", ARG3, sizeof(vki_sigset_t));
-
- SET_STATUS_from_SysRes(
- VG_(do_sys_sigprocmask) ( tid, ARG1, (vki_sigset_t*)ARG2,
- (vki_sigset_t*)ARG3 )
- );
-
- if (SUCCESS)
- *flags |= SfPollAfter;
-}
-POST(sys_sigprocmask)
-{
- vg_assert(SUCCESS);
- if (RES == 0 && ARG3 != 0)
- POST_MEM_WRITE( ARG3, sizeof(vki_sigset_t));
-}
-
-PRE(sys_socket)
-{
- PRINT("socket ( %ld, %ld, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "socket", int, domain, int, type, int, protocol);
-}
-
-PRE(sys_statfs)
-{
- PRINT("sys_statfs ( %#lx(%s), %#lx )",ARG1,(Char*)ARG1,ARG2);
- PRE_REG_READ2(long, "statfs", const char *, path, struct statfs *, buf);
- PRE_MEM_RASCIIZ( "statfs(path)", ARG1 );
- PRE_MEM_WRITE( "statfs(buf)", ARG2, sizeof(struct statfs) );
-}
-POST(sys_statfs)
-{
- POST_MEM_WRITE( ARG2, sizeof(struct statfs) );
-}
-
-PRE(sys_statx)
-{
- PRINT("statx ( %#lx(%s), %#lx, %ld, %ld )", ARG1,(Char*)ARG1,ARG2,ARG3,ARG4);
- PRE_MEM_RASCIIZ( "statx(file_name)", ARG1 );
- PRE_REG_READ4(Word, "statx", UWord, fd, void*, buf,
- UWord, len, UWord, cmd);
- PRE_MEM_WRITE( "statx(buf)", ARG2, ARG3 );
-}
-POST(sys_statx)
-{
- POST_MEM_WRITE( ARG2, ARG3 );
-}
-
-PRE(sys_symlink)
-{
- PRINT("symlink (BOGUS HANDLER)");
-}
-
-PRE(sys_sys_parm)
-{
- PRINT("sys_parm (%ld, %ld, %#lx)", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "sys_parm", int, cmd, int, cmdflag,
- struct vario*, parmp);
- /* this is a bit of a kludge, but if parmp has uninitialised areas
- and we're doing SYSP_SET, lots of errors will be tiresomely
- reported. Hence just ignore the definedness of the area and
- only check addressability. */
- PRE_MEM_WRITE( "sys_parm(parmp)", ARG3, sizeof(struct vario));
-}
-POST(sys_sys_parm)
-{
- if (ARG1 == SYSP_GET)
- POST_MEM_WRITE( ARG3, sizeof(struct vario) );
-}
-
-PRE(sys_sysconfig)
-{
- PRINT("sysconfig ( %ld, %#lx, %ld )", ARG1, ARG2, ARG3);
- PRE_REG_READ3(int, "sysconfig", int, cmd, void*, parmp, int, parmlen);
- /* It may be that the area is read sometimes as well as written,
- but for the same reasons as sys_parm, just check addressibility,
- not definedness. */
- PRE_MEM_WRITE( "sysconfig(parmp)", ARG2, ARG3 );
-}
-POST(sys_sysconfig)
-{
- POST_MEM_WRITE( ARG2, ARG3 );
-}
-
-PRE(sys_thread_create)
-{
- *flags |= SfMayBlock;
- PRINT("thread_create ( )");
-}
-POST(sys_thread_create)
-{
- vg_assert(SUCCESS);
- if (0) VG_(printf)("new lwpid is %ld\n", RES);
-
- /* Allocate a new thread slot (which sets it to VgTs_Init), and
- record the lwpid in it, so can later find it again when handling
- sys_thread_setstate for that lwpid. */
-
- ThreadId ctid = VG_(alloc_ThreadState)();
- ThreadState* ctst = VG_(get_ThreadState)(ctid);
-
- vg_assert(ctst->status == VgTs_Init);
-
- { /* Clear all os_state fields except for the vg stack ones, so any
- existing stack gets reused. */
- Addr v_s_b = ctst->os_state.valgrind_stack_base;
- Addr v_s_i_SP = ctst->os_state.valgrind_stack_init_SP;
- VG_(memset)(&ctst->os_state, 0, sizeof(ThreadOSstate));
- ctst->os_state.valgrind_stack_base = v_s_b;
- ctst->os_state.valgrind_stack_init_SP = v_s_i_SP;
- }
- ctst->os_state.lwpid = RES;
-}
-
-PRE(sys_thread_init)
-{
- *flags |= SfMayBlock;
- PRE_REG_READ2(long, "thread_init", long, arg1, long, arg2);
- PRINT("thread_init (BOGUS HANDLER) ( %#lx, %#lx )", ARG1, ARG2);
-}
-
-PRE(sys_thread_kill)
-{
- Int target_lwpid, my_lwpid;
- PRINT("thread_kill ( %ld, %ld )", ARG1, ARG2);
-
- if ( ((Word)ARG1) == (Word)(-1)
- && ARG2 == VKI_SIGSEGV ) {
- /* too difficult to continue; give up. */
- ML_(aix5_set_threadstate_for_emergency_exit)
- (tid, "exiting due to thread_kill(..,SIGSEGV) to process");
- SET_STATUS_Success(0);
- return;
- }
-
- /* Check to see if this kill gave us a pending signal */
- *flags |= SfPollAfter;
-
- target_lwpid = (Int)ARG1;
- my_lwpid = VG_(gettid)();
- /* we still hold the lock. Do deadlock-avoidance stuff. */
- if (target_lwpid == my_lwpid) {
- /* sending a signal to myself, which may be fatal. Therefore
- drop the lock so that if the signal kills me, some other
- thread can pick it up. */
- *flags |= SfMayBlock;
- } else {
- /* sending a signal to some other thread, which may kill it;
- therefore I'd better hold on to the lock to ensure that the
- target doesn't get killed whilst holding it. */
- }
-}
-
-/* thread_setmymask_fast is handled on a per platform basis */
-
-PRE(sys_thread_setmystate)
-{
- *flags |= SfMayBlock;
- /* args: struct tstate *, struct tstate *
- I assume: first is new state, if not NULL.
- Second is place to write the previous state, if not NULL.
- (in the style of sigaction) */
- PRINT("thread_setmystate (BOGUS HANDLER) ( %#lx, %#lx )",
- ARG1, ARG2 );
- PRE_REG_READ2(long, "thread_setmystate",
- struct tstate *, newstate,
- struct tstate *, oldstate );
- if (ARG1)
- PRE_MEM_READ( "thread_setmystate(arg1)", ARG1, sizeof(struct tstate) );
- if (ARG2)
- PRE_MEM_WRITE( "thread_setmystate(arg2)", ARG2, sizeof(struct tstate) );
- if (1 && VG_(clo_trace_syscalls) && ARG1)
- ML_(aix5debugstuff_show_tstate)(ARG1, "thread_setmystate (NEW)");
-
- struct tstate* newts = (struct tstate*)ARG1;
- struct tstate* oldts = (struct tstate*)ARG2;
-
- /* Are we just messing with the signal mask? If so intercept it
- and do it ourselves. Same idea as handling for
- thread_setmymask_fast in 32-bit mode. */
- if (newts && newts->flags == TSTATE_CHANGE_SIGMASK) {
- vki_sigset_t* newset = newts ? (vki_sigset_t*)&newts->sigmask : NULL;
- vki_sigset_t* oldset = oldts ? (vki_sigset_t*)&oldts->sigmask : NULL;
- SET_STATUS_from_SysRes(
- VG_(do_sys_sigprocmask) ( tid, VKI_SIG_SETMASK, newset, oldset )
- );
- *flags &= ~SfMayBlock;
- return;
- }
-}
-POST(sys_thread_setmystate)
-{
- if (ARG2)
- POST_MEM_WRITE( ARG2, sizeof(struct tstate) );
- if (0 && VG_(clo_trace_syscalls) && ARG2)
- ML_(aix5debugstuff_show_tstate)(ARG2, "thread_setmystate (OLD)");
-}
-
-PRE(sys_thread_setmystate_fast)
-{
- UWord how = ARG1;
- /* args: ?? */
- PRINT("thread_setmystate_fast (BOGUS HANDLER)"
- "(%#lx,%#lx(%s),%#lx(%s))",
- ARG1,
- ARG2, ML_(aix5debugstuff_pc_to_fnname)(ARG2),
- ARG3, ML_(aix5debugstuff_pc_to_fnname)(ARG3)
- );
- PRE_REG_READ3(long, "thread_setmystate_fast",
- long, arg1, long, arg2, long, arg3);
- if (1 && VG_(clo_trace_syscalls))
- ML_(aix5debugstuff_show_tstate_flags)( how );
-
- if (how & TSTATE_CHANGE_FLAGS) {
- /* Messing with cancellation type/state. Pay attention. */
- Bool async = (how & TSTATE_CANCEL_DEFER) == 0;
- Bool disabled = (how & TSTATE_CANCEL_DISABLE) > 0;
- ThreadState* tst = VG_(get_ThreadState)(tid);
- if (VG_(clo_trace_syscalls))
- VG_(printf)("(cancellation state -> %s %s)",
- async ? "ASYNC" : "DEFER",
- disabled ? "DISABLED" : " ENABLED");
- tst->os_state.cancel_async = async;
- tst->os_state.cancel_disabled = disabled;
- /* If cancellation has been enabled for this thread and there is
- a request outstanding, honour it now. */
- if ((!disabled)
- && tst->os_state.cancel_progress == Canc_Requested) {
- if (VG_(clo_trace_syscalls))
- VG_(printf)("(honouring previous cancellation request)");
- tst->os_state.cancel_progress = Canc_Actioned;
- Bool ok = ML_(aix5_force_thread_into_pthread_exit)(tid);
- if (!ok) {
- /* now at serious risk of deadlock/livelock. Give up
- rather than continue. */
- ML_(aix5_set_threadstate_for_emergency_exit)
- (tid, "pthread_cancel(case1): "
- "cannot find pthread_exit; aborting");
- SET_STATUS_Success(0);
- return;
- }
- }
- SET_STATUS_Success(0);
- return;
- }
-
- /* In all other cases, hand to kernel. */
- *flags |= SfMayBlock;
-}
-
-/* thread_setstate is handled in syswrap-ppc{32,64}-aix5.c. */
-
-PRE(sys_thread_terminate_unlock)
-{
- ThreadState* tst;
- /* simple; just make this thread exit */
- PRINT("thread_terminate_unlock( %#lx )", ARG1);
- PRE_REG_READ1(void, "thread_terminate_unlock", void*, exitcode);
- tst = VG_(get_ThreadState)(tid);
- /* Drop the lock we were holding, since we're not really going to
- exit the host thread with thread_terminate_unlock. */
- if (0) VG_(printf)("XXXXX dropping lock\n");
- if (1) VG_(do_syscall1)(__NR_AIX5_thread_unlock, ARG1);
- /* Set the thread's status to be exiting, then claim that the
- syscall succeeded. */
- tst->exitreason = VgSrc_ExitThread;
- tst->os_state.exitcode = 0;
- SET_STATUS_Success(0);
-}
-
-PRE(sys_thread_tsleep)
-{
- *flags |= SfMayBlock;
- PRINT("thread_tsleep (BOGUS HANDLER)( %ld, %#lx, %#lx, %#lx )",
- ARG1, ARG2, ARG3, ARG4 );
-}
-
-PRE(sys_thread_tsleep_event)
-{
- *flags |= SfMayBlock;
- PRINT("thread_tsleep_event (UNDOCUMENTED)( %#lx, %#lx, %ld, %#lx )",
- ARG1, ARG2, ARG3, ARG4 );
-}
-
-PRE(sys_thread_twakeup)
-{
- *flags |= SfMayBlock;
- PRINT("thread_twakeup (BOGUS HANDLER)( tid=%ld, val=%#lx )", ARG1, ARG2 );
-}
-
-PRE(sys_thread_twakeup_event)
-{
- *flags |= SfMayBlock;
- PRINT("thread_twakeup_event (BOGUS HANDLER)( %#lx, %ld, %ld )",
- ARG1, ARG2, ARG3 );
-}
-
-PRE(sys_thread_unlock)
-{
- *flags |= SfMayBlock;
- PRINT("thread_unlock (BOGUS HANDLER)" );
-}
-
-PRE(sys_thread_waitlock)
-{
- *flags |= SfMayBlock;
- PRINT("thread_waitlock (BOGUS HANDLER)" );
-}
-
-PRE(sys_thread_waitlock_)
-{
- *flags |= SfMayBlock;
- PRINT("thread_waitlock_ (BOGUS HANDLER)" );
-}
-
-PRE(sys_times)
-{
- PRINT("times ( %#lx )", ARG1);
- PRE_REG_READ1(long, "times", struct tms *, buffer);
- PRE_MEM_WRITE("times(buf)", ARG1, sizeof(struct tms) );
-}
-POST(sys_times)
-{
- POST_MEM_WRITE( ARG1, sizeof(struct tms) );
-}
-
-PRE(sys_umask)
-{
- PRINT("umask (BOGUS HANDLER)");
-}
-
-PRE(sys_uname)
-{
- PRINT("uname ( %#lx )", ARG1);
- PRE_MEM_WRITE( "uname(Name)", ARG1, sizeof(struct utsname));
-}
-POST(sys_uname)
-{
- vg_assert(SUCCESS);
- POST_MEM_WRITE( ARG1, sizeof(struct utsname));
-}
-
-PRE(sys_unlink)
-{
- PRINT("unlink ( %#lx(%s) )", ARG1, (Char*)ARG1 );
- PRE_REG_READ1(int, "unlink", char*, path);
- PRE_MEM_RASCIIZ( "unlink(path)", ARG1 );
-}
-
-PRE(sys_utimes)
-{
- PRINT("utimes ( %#lx(%s), %#lx )", ARG1,(Char*)ARG1, ARG2);
- PRE_REG_READ2(int, "utimes", char*, path, struct timeval*, times);
- PRE_MEM_RASCIIZ( "utimes(path)", ARG1 );
- PRE_MEM_READ( "utimes(times)", ARG2, 2 * sizeof(struct vki_timeval) );
-}
-
-PRE(sys_vmgetinfo)
-{
- PRINT("vmgetinfo ( %#lx, %ld, %ld )", ARG1, ARG2, ARG3 );
- PRE_REG_READ3(int, "vmgetinfo", void*, out, int, command, int, arg);
- /* It looks like libc's vmgetinfo just hands stuff through to the
- syscall. The man page says that the interpretation of ARG3(arg)
- depends on ARG2(cmd); nevertheless in all cases basically this
- writes the buffer (ARG1, ARG3). */
- PRE_MEM_WRITE("vmgetinfo(buf)", ARG1, ARG3);
-}
-POST(sys_vmgetinfo)
-{
- vg_assert(SUCCESS);
- POST_MEM_WRITE(ARG1, ARG3);
-}
-
-PRE(sys_yield)
-{
- *flags |= SfMayBlock;
- PRINT("yield ( )");
-}
-
-#undef PRE
-#undef POST
-
-#endif // defined(VGO_aix5)
-
-/*--------------------------------------------------------------------*/
-/*--- end ---*/
-/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_syswrap/syswrap-amd64-darwin.c b/main/coregrind/m_syswrap/syswrap-amd64-darwin.c
index 0863abf..ec1ea01 100644
--- a/main/coregrind/m_syswrap/syswrap-amd64-darwin.c
+++ b/main/coregrind/m_syswrap/syswrap-amd64-darwin.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Apple Inc.
+ Copyright (C) 2005-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -97,8 +97,23 @@
VexGuestAMD64State *vex)
{
// DDD: #warning GrP fixme fp state
-
- VG_(memcpy)(&mach->__fpu_xmm0, &vex->guest_XMM0, 16 * sizeof(mach->__fpu_xmm0));
+ // JRS: what about the YMMHI bits? Are they important?
+ VG_(memcpy)(&mach->__fpu_xmm0, &vex->guest_YMM0, sizeof(mach->__fpu_xmm0));
+ VG_(memcpy)(&mach->__fpu_xmm1, &vex->guest_YMM1, sizeof(mach->__fpu_xmm1));
+ VG_(memcpy)(&mach->__fpu_xmm2, &vex->guest_YMM2, sizeof(mach->__fpu_xmm2));
+ VG_(memcpy)(&mach->__fpu_xmm3, &vex->guest_YMM3, sizeof(mach->__fpu_xmm3));
+ VG_(memcpy)(&mach->__fpu_xmm4, &vex->guest_YMM4, sizeof(mach->__fpu_xmm4));
+ VG_(memcpy)(&mach->__fpu_xmm5, &vex->guest_YMM5, sizeof(mach->__fpu_xmm5));
+ VG_(memcpy)(&mach->__fpu_xmm6, &vex->guest_YMM6, sizeof(mach->__fpu_xmm6));
+ VG_(memcpy)(&mach->__fpu_xmm7, &vex->guest_YMM7, sizeof(mach->__fpu_xmm7));
+ VG_(memcpy)(&mach->__fpu_xmm8, &vex->guest_YMM8, sizeof(mach->__fpu_xmm8));
+ VG_(memcpy)(&mach->__fpu_xmm9, &vex->guest_YMM9, sizeof(mach->__fpu_xmm9));
+ VG_(memcpy)(&mach->__fpu_xmm10, &vex->guest_YMM10, sizeof(mach->__fpu_xmm10));
+ VG_(memcpy)(&mach->__fpu_xmm11, &vex->guest_YMM11, sizeof(mach->__fpu_xmm11));
+ VG_(memcpy)(&mach->__fpu_xmm12, &vex->guest_YMM12, sizeof(mach->__fpu_xmm12));
+ VG_(memcpy)(&mach->__fpu_xmm13, &vex->guest_YMM13, sizeof(mach->__fpu_xmm13));
+ VG_(memcpy)(&mach->__fpu_xmm14, &vex->guest_YMM14, sizeof(mach->__fpu_xmm14));
+ VG_(memcpy)(&mach->__fpu_xmm15, &vex->guest_YMM15, sizeof(mach->__fpu_xmm15));
}
@@ -159,8 +174,23 @@
VexGuestAMD64State *vex)
{
// DDD: #warning GrP fixme fp state
-
- VG_(memcpy)(&vex->guest_XMM0, &mach->__fpu_xmm0, 16 * sizeof(mach->__fpu_xmm0));
+ // JRS: what about the YMMHI bits? Are they important?
+ VG_(memcpy)(&vex->guest_YMM0, &mach->__fpu_xmm0, sizeof(mach->__fpu_xmm0));
+ VG_(memcpy)(&vex->guest_YMM1, &mach->__fpu_xmm1, sizeof(mach->__fpu_xmm1));
+ VG_(memcpy)(&vex->guest_YMM2, &mach->__fpu_xmm2, sizeof(mach->__fpu_xmm2));
+ VG_(memcpy)(&vex->guest_YMM3, &mach->__fpu_xmm3, sizeof(mach->__fpu_xmm3));
+ VG_(memcpy)(&vex->guest_YMM4, &mach->__fpu_xmm4, sizeof(mach->__fpu_xmm4));
+ VG_(memcpy)(&vex->guest_YMM5, &mach->__fpu_xmm5, sizeof(mach->__fpu_xmm5));
+ VG_(memcpy)(&vex->guest_YMM6, &mach->__fpu_xmm6, sizeof(mach->__fpu_xmm6));
+ VG_(memcpy)(&vex->guest_YMM7, &mach->__fpu_xmm7, sizeof(mach->__fpu_xmm7));
+ VG_(memcpy)(&vex->guest_YMM8, &mach->__fpu_xmm8, sizeof(mach->__fpu_xmm8));
+ VG_(memcpy)(&vex->guest_YMM9, &mach->__fpu_xmm9, sizeof(mach->__fpu_xmm9));
+ VG_(memcpy)(&vex->guest_YMM10, &mach->__fpu_xmm10, sizeof(mach->__fpu_xmm10));
+ VG_(memcpy)(&vex->guest_YMM11, &mach->__fpu_xmm11, sizeof(mach->__fpu_xmm11));
+ VG_(memcpy)(&vex->guest_YMM12, &mach->__fpu_xmm12, sizeof(mach->__fpu_xmm12));
+ VG_(memcpy)(&vex->guest_YMM13, &mach->__fpu_xmm13, sizeof(mach->__fpu_xmm13));
+ VG_(memcpy)(&vex->guest_YMM14, &mach->__fpu_xmm14, sizeof(mach->__fpu_xmm14));
+ VG_(memcpy)(&vex->guest_YMM15, &mach->__fpu_xmm15, sizeof(mach->__fpu_xmm15));
}
@@ -418,7 +448,7 @@
idea why. */
# if DARWIN_VERS <= DARWIN_10_6
UWord magic_delta = 0;
-# elif DARWIN_VERS == DARWIN_10_7
+# elif DARWIN_VERS >= DARWIN_10_7
UWord magic_delta = 0x60;
# endif
diff --git a/main/coregrind/m_syswrap/syswrap-amd64-linux.c b/main/coregrind/m_syswrap/syswrap-amd64-linux.c
index 935eefb..035f7b8 100644
--- a/main/coregrind/m_syswrap/syswrap-amd64-linux.c
+++ b/main/coregrind/m_syswrap/syswrap-amd64-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -142,6 +142,7 @@
vki_modify_ldt_t * );
asm(
".text\n"
+".globl do_syscall_clone_amd64_linux\n"
"do_syscall_clone_amd64_linux:\n"
// set up child stack, temporarily preserving fn and arg
" subq $16, %rsi\n" // make space on stack
@@ -289,6 +290,7 @@
know that this thread has come into existence. If the clone
fails, we'll send out a ll_exit notification for it at the out:
label below, to clean up. */
+ vg_assert(VG_(owns_BigLock_LL)(ptid));
VG_TRACK ( pre_thread_ll_create, ptid, ctid );
if (flags & VKI_CLONE_SETTLS) {
@@ -397,21 +399,35 @@
ULong cloneflags;
PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
- PRE_REG_READ5(int, "clone",
+ PRE_REG_READ2(int, "clone",
unsigned long, flags,
- void *, child_stack,
- int *, parent_tidptr,
- int *, child_tidptr,
- void *, tlsaddr);
+ void *, child_stack);
if (ARG1 & VKI_CLONE_PARENT_SETTID) {
+ if (VG_(tdict).track_pre_reg_read) {
+ PRA3("clone", int *, parent_tidptr);
+ }
PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int));
if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), VKI_PROT_WRITE)) {
SET_STATUS_Failure( VKI_EFAULT );
return;
}
}
+ if (ARG1 & VKI_CLONE_SETTLS) {
+ if (VG_(tdict).track_pre_reg_read) {
+ PRA4("clone", vki_modify_ldt_t *, tlsinfo);
+ }
+ PRE_MEM_READ("clone(tlsinfo)", ARG4, sizeof(vki_modify_ldt_t));
+ if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t),
+ VKI_PROT_READ)) {
+ SET_STATUS_Failure( VKI_EFAULT );
+ return;
+ }
+ }
if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
+ if (VG_(tdict).track_pre_reg_read) {
+ PRA5("clone", int *, child_tidptr);
+ }
PRE_MEM_WRITE("clone(child_tidptr)", ARG4, sizeof(Int));
if (!VG_(am_is_valid_for_client)(ARG4, sizeof(Int), VKI_PROT_WRITE)) {
SET_STATUS_Failure( VKI_EFAULT );
@@ -747,7 +763,7 @@
PRINT("sys_sendmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3);
PRE_REG_READ3(long, "sendmsg",
int, s, const struct msghdr *, msg, int, flags);
- ML_(generic_PRE_sys_sendmsg)(tid, ARG1,ARG2);
+ ML_(generic_PRE_sys_sendmsg)(tid, "msg", (struct vki_msghdr *)ARG2);
}
PRE(sys_recvmsg)
@@ -755,11 +771,11 @@
*flags |= SfMayBlock;
PRINT("sys_recvmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3);
PRE_REG_READ3(long, "recvmsg", int, s, struct msghdr *, msg, int, flags);
- ML_(generic_PRE_sys_recvmsg)(tid, ARG1,ARG2);
+ ML_(generic_PRE_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2);
}
POST(sys_recvmsg)
{
- ML_(generic_POST_sys_recvmsg)(tid, ARG1,ARG2);
+ ML_(generic_POST_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2, RES);
}
PRE(sys_shutdown)
@@ -1384,10 +1400,10 @@
LINXY(__NR_get_robust_list, sys_get_robust_list), // 274
LINX_(__NR_splice, sys_splice), // 275
-// LINX_(__NR_tee, sys_ni_syscall), // 276
+ LINX_(__NR_tee, sys_tee), // 276
LINX_(__NR_sync_file_range, sys_sync_file_range), // 277
-// LINX_(__NR_vmsplice, sys_ni_syscall), // 278
-// LINX_(__NR_move_pages, sys_ni_syscall), // 279
+ LINXY(__NR_vmsplice, sys_vmsplice), // 278
+ LINXY(__NR_move_pages, sys_move_pages), // 279
LINX_(__NR_utimensat, sys_utimensat), // 280
LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 281
@@ -1411,18 +1427,22 @@
LINX_(__NR_pwritev, sys_pwritev), // 296
LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 297
LINXY(__NR_perf_event_open, sys_perf_event_open), // 298
-// LINX_(__NR_recvmmsg, sys_ni_syscall), // 299
+ LINXY(__NR_recvmmsg, sys_recvmmsg), // 299
// LINX_(__NR_fanotify_init, sys_ni_syscall), // 300
// LINX_(__NR_fanotify_mark, sys_ni_syscall), // 301
- LINXY(__NR_prlimit64, sys_prlimit64) // 302
+ LINXY(__NR_prlimit64, sys_prlimit64), // 302
// LINX_(__NR_name_to_handle_at, sys_ni_syscall), // 303
// LINX_(__NR_open_by_handle_at, sys_ni_syscall), // 304
// LINX_(__NR_clock_adjtime, sys_ni_syscall), // 305
// LINX_(__NR_syncfs, sys_ni_syscall), // 306
-// LINX_(__NR_sendmmsg, sys_ni_syscall), // 307
+ LINXY(__NR_sendmmsg, sys_sendmmsg), // 307
// LINX_(__NR_setns, sys_ni_syscall), // 308
+ LINXY(__NR_getcpu, sys_getcpu), // 309
+
+ LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 310
+ LINX_(__NR_process_vm_writev, sys_process_vm_writev) // 311
};
SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno )
diff --git a/main/coregrind/m_syswrap/syswrap-arm-linux.c b/main/coregrind/m_syswrap/syswrap-arm-linux.c
index 08aef53..fbb242a 100644
--- a/main/coregrind/m_syswrap/syswrap-arm-linux.c
+++ b/main/coregrind/m_syswrap/syswrap-arm-linux.c
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2008-2011 Evan Geller
+ Copyright (C) 2008-2012 Evan Geller
gaze@bea.ms
This program is free software; you can redistribute it and/or
@@ -114,6 +114,7 @@
void* tls );
asm(
".text\n"
+".globl do_syscall_clone_arm_linux\n"
"do_syscall_clone_arm_linux:\n"
/*Setup child stack */
@@ -150,6 +151,7 @@
// forward declarations
static void setup_child ( ThreadArchState*, ThreadArchState* );
+static void assign_guest_tls(ThreadId ctid, Addr tlsptr);
static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr );
/*
@@ -228,12 +230,12 @@
ctst->client_stack_szB = 0;
}
+ vg_assert(VG_(owns_BigLock_LL)(ptid));
VG_TRACK ( pre_thread_ll_create, ptid, ctid );
if (flags & VKI_CLONE_SETTLS) {
- res = sys_set_tls(ctid, child_tls);
- if (sr_isError(res))
- goto out;
+ /* Just assign the tls pointer in the guest TPIDRURO. */
+ assign_guest_tls(ctid, child_tls);
}
flags &= ~VKI_CLONE_SETTLS;
@@ -280,10 +282,53 @@
child->vex_shadow2 = parent->vex_shadow2;
}
-static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr )
+static void assign_guest_tls(ThreadId tid, Addr tlsptr)
{
VG_(threads)[tid].arch.vex.guest_TPIDRURO = tlsptr;
+}
+
+/* Assigns tlsptr to the guest TPIDRURO.
+ If needed for the specific hardware, really executes
+ the set_tls syscall.
+*/
+static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr )
+{
+ assign_guest_tls(tid, tlsptr);
+#if defined(ANDROID_HARDWARE_emulator)
+ /* Android emulator does not provide an hw tls register.
+ So, the tls register is emulated by the kernel.
+ This emulated value is set by the __NR_ARM_set_tls syscall.
+ The emulated value must be read by the kernel helper function
+ located at 0xffff0fe0.
+
+ The emulated tlsptr is located at 0xffff0ff0
+ (so slightly after the kernel helper function).
+ Note that applications are not supposed to read this directly.
+
+ For compatibility : if there is a hw tls register, the kernel
+ will put at 0xffff0fe0 the instructions to read it, so
+ as to have old applications calling the kernel helper
+ working properly.
+
+ For having emulated guest TLS working correctly with
+ Valgrind, it is needed to execute the syscall to set
+ the emulated TLS value in addition to the assignment
+ of TPIDRURO.
+
+ Note: the below means that if we need thread local storage
+ for Valgrind host, then there will be a conflict between
+ the need of the guest tls and of the host tls.
+ If all the guest code would cleanly call 0xffff0fe0,
+ then we might maybe intercept this. However, at least
+ __libc_preinit reads directly 0xffff0ff0.
+ */
+ /* ??? might call the below if auxv->u.a_val & VKI_HWCAP_TLS ???
+ Unclear if real hardware having tls hw register sets
+ VKI_HWCAP_TLS. */
+ return VG_(do_syscall1) (__NR_ARM_set_tls, tlsptr);
+#else
return VG_(mk_SysRes_Success)( 0 );
+#endif
}
/* ---------------------------------------------------------------------
@@ -305,6 +350,7 @@
DECL_TEMPLATE(arm_linux, sys_getsockopt);
DECL_TEMPLATE(arm_linux, sys_connect);
DECL_TEMPLATE(arm_linux, sys_accept);
+DECL_TEMPLATE(arm_linux, sys_accept4);
DECL_TEMPLATE(arm_linux, sys_sendto);
DECL_TEMPLATE(arm_linux, sys_recvfrom);
//XXX: Semaphore code ripped from AMD64.
@@ -391,6 +437,13 @@
break;
}
+ case VKI_SYS_ACCEPT4: {
+ /*int accept(int s, struct sockaddr *add, int *addrlen, int flags)*/
+ PRE_MEM_READ( "socketcall.accept4(args)", ARG2, 4*sizeof(Addr) );
+ ML_(generic_PRE_sys_accept)( tid, ARG2_0, ARG2_1, ARG2_2 );
+ break;
+ }
+
case VKI_SYS_SENDTO:
/* int sendto(int s, const void *msg, int len,
unsigned int flags,
@@ -472,7 +525,7 @@
* (after all it's glibc providing the arguments array)
PRE_MEM_READ( "socketcall.sendmsg(args)", ARG2, 3*sizeof(Addr) );
*/
- ML_(generic_PRE_sys_sendmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_sendmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -483,7 +536,7 @@
* (after all it's glibc providing the arguments array)
PRE_MEM_READ("socketcall.recvmsg(args)", ARG2, 3*sizeof(Addr) );
*/
- ML_(generic_PRE_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -536,7 +589,9 @@
break;
case VKI_SYS_ACCEPT:
+ case VKI_SYS_ACCEPT4:
/* int accept(int s, struct sockaddr *addr, int *addrlen); */
+ /* int accept4(int s, struct sockaddr *addr, int *addrlen, int flags); */
r = ML_(generic_POST_sys_accept)( tid, VG_(mk_SysRes_Success)(RES),
ARG2_0, ARG2_1, ARG2_2 );
SET_STATUS_from_SysRes(r);
@@ -587,7 +642,7 @@
break;
case VKI_SYS_RECVMSG:
- ML_(generic_POST_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_POST_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1, RES );
break;
default:
@@ -666,6 +721,23 @@
SET_STATUS_from_SysRes(r);
}
+PRE(sys_accept4)
+{
+ *flags |= SfMayBlock;
+ PRINT("sys_accept4 ( %ld, %#lx, %ld, %ld )",ARG1,ARG2,ARG3,ARG4);
+ PRE_REG_READ4(long, "accept4",
+ int, s, struct sockaddr *, addr, int, *addrlen, int, flags);
+ ML_(generic_PRE_sys_accept)(tid, ARG1,ARG2,ARG3);
+}
+POST(sys_accept4)
+{
+ SysRes r;
+ vg_assert(SUCCESS);
+ r = ML_(generic_POST_sys_accept)(tid, VG_(mk_SysRes_Success)(RES),
+ ARG1,ARG2,ARG3);
+ SET_STATUS_from_SysRes(r);
+}
+
PRE(sys_sendto)
{
*flags |= SfMayBlock;
@@ -699,7 +771,7 @@
PRINT("sys_sendmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3);
PRE_REG_READ3(long, "sendmsg",
int, s, const struct msghdr *, msg, int, flags);
- ML_(generic_PRE_sys_sendmsg)(tid, ARG1,ARG2);
+ ML_(generic_PRE_sys_sendmsg)(tid, "msg", (struct vki_msghdr *)ARG2);
}
PRE(sys_recvmsg)
@@ -707,11 +779,11 @@
*flags |= SfMayBlock;
PRINT("sys_recvmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3);
PRE_REG_READ3(long, "recvmsg", int, s, struct msghdr *, msg, int, flags);
- ML_(generic_PRE_sys_recvmsg)(tid, ARG1,ARG2);
+ ML_(generic_PRE_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2);
}
POST(sys_recvmsg)
{
- ML_(generic_POST_sys_recvmsg)(tid, ARG1,ARG2);
+ ML_(generic_POST_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2, RES);
}
//XXX: Semaphore code ripped from AMD64.
@@ -1213,6 +1285,7 @@
PRE(sys_set_tls)
{
+ PRINT("set_tls (%lx)",ARG1);
PRE_REG_READ1(long, "set_tls", unsigned long, addr);
SET_STATUS_from_SysRes( sys_set_tls( tid, ARG1 ) );
@@ -1782,14 +1855,14 @@
// LINX_(__NR_tee, sys_ni_syscall), // 315
// LINX_(__NR_vmsplice, sys_ni_syscall), // 316
-// LINX_(__NR_move_pages, sys_ni_syscall), // 317
+ LINXY(__NR_move_pages, sys_move_pages), // 317
// LINX_(__NR_getcpu, sys_ni_syscall), // 318
LINX_(__NR_utimensat, sys_utimensat), // 320
LINXY(__NR_signalfd, sys_signalfd), // 321
LINXY(__NR_timerfd_create, sys_timerfd_create), // 322
LINX_(__NR_eventfd, sys_eventfd), // 323
-// LINX_(__NR_fallocate, sys_ni_syscall), // 324
+
LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 325
LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 326
@@ -1807,11 +1880,20 @@
LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 346
+ LINX_(__NR_fallocate, sys_fallocate), // 352
+
LINXY(__NR_signalfd4, sys_signalfd4), // 355
LINX_(__NR_eventfd2, sys_eventfd2), // 356
-
+ LINXY(__NR_epoll_create1, sys_epoll_create1), // 357
+ LINXY(__NR_dup3, sys_dup3), // 358
LINXY(__NR_pipe2, sys_pipe2), // 359
- LINXY(__NR_inotify_init1, sys_inotify_init1) // 360
+ LINXY(__NR_inotify_init1, sys_inotify_init1), // 360
+ LINXY(__NR_preadv, sys_preadv), // 361
+ LINX_(__NR_pwritev, sys_pwritev), // 362
+ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 363
+ LINXY(__NR_perf_event_open, sys_perf_event_open), // 364
+
+ PLAXY(__NR_accept4, sys_accept4) // 366
};
diff --git a/main/coregrind/m_syswrap/syswrap-darwin.c b/main/coregrind/m_syswrap/syswrap-darwin.c
index 2778957..292ed54 100644
--- a/main/coregrind/m_syswrap/syswrap-darwin.c
+++ b/main/coregrind/m_syswrap/syswrap-darwin.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Apple Inc.
+ Copyright (C) 2005-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -41,7 +41,6 @@
#include "pub_core_debuglog.h"
#include "pub_core_debuginfo.h" // VG_(di_notify_*)
#include "pub_core_transtab.h" // VG_(discard_translations)
-#include "pub_tool_gdbserver.h" // VG_(gdbserver)
#include "pub_core_libcbase.h"
#include "pub_core_libcassert.h"
#include "pub_core_libcfile.h"
@@ -1477,9 +1476,12 @@
static const char *workqop_name(int op)
{
switch (op) {
- case VKI_WQOPS_QUEUE_ADD: return "QUEUE_ADD";
- case VKI_WQOPS_QUEUE_REMOVE: return "QUEUE_REMOVE";
- case VKI_WQOPS_THREAD_RETURN: return "THREAD_RETURN";
+ case VKI_WQOPS_QUEUE_ADD: return "QUEUE_ADD";
+ case VKI_WQOPS_QUEUE_REMOVE: return "QUEUE_REMOVE";
+ case VKI_WQOPS_THREAD_RETURN: return "THREAD_RETURN";
+ case VKI_WQOPS_THREAD_SETCONC: return "THREAD_SETCONC";
+ case VKI_WQOPS_QUEUE_NEWSPISUPP: return "QUEUE_NEWSPISUPP";
+ case VKI_WQOPS_QUEUE_REQTHREADS: return "QUEUE_REQTHREADS";
default: return "?";
}
}
@@ -1498,6 +1500,8 @@
// GrP fixme need anything here?
// GrP fixme may block?
break;
+ case VKI_WQOPS_QUEUE_NEWSPISUPP:
+ break; // JRS don't think we need to do anything here
case VKI_WQOPS_THREAD_RETURN: {
// The interesting case. The kernel will do one of two things:
@@ -1936,6 +1940,21 @@
}
}
+PRE(shm_unlink)
+{
+ *flags |= SfMayBlock;
+ PRINT("shm_unlink ( %#lx(%s) )", ARG1,(char*)ARG1);
+ PRE_REG_READ1(long, "shm_unlink", const char *, pathname);
+ PRE_MEM_RASCIIZ( "shm_unlink(pathname)", ARG1 );
+}
+POST(shm_unlink)
+{
+ /* My reading of the man page suggests that a call may cause memory
+ mappings to change: "if no references exist at the time of the
+ call to shm_unlink(), the resources are reclaimed immediately".
+ So we need to resync here, sigh. */
+ ML_(sync_mappings)("after", "shm_unlink", 0);
+}
PRE(stat_extended)
{
@@ -2814,14 +2833,11 @@
/* Ok. So let's give it a try. */
VG_(debugLog)(1, "syswrap", "Posix_spawn of %s\n", (Char*)ARG2);
- // Terminate gdbserver if it is active.
- if (VG_(clo_vgdb) != Vg_VgdbNo) {
- // If the child will not be traced, we need to terminate gdbserver
- // to cleanup the gdbserver resources (e.g. the FIFO files).
- // If child will be traced, we also terminate gdbserver: the new
- // Valgrind will start a fresh gdbserver after exec.
- VG_(gdbserver) (tid);
- }
+ /* posix_spawn on Darwin is combining the fork and exec in one syscall.
+ So, we should not terminate gdbserver : this is still the parent
+ running, which will terminate its gdbserver when exiting.
+ If the child process is traced, it will start a fresh gdbserver
+ after posix_spawn. */
// Set up the child's exe path.
//
@@ -2939,7 +2955,9 @@
POST(posix_spawn)
{
vg_assert(SUCCESS);
- //POST_MEM_WRITE( ARG1, sizeof(vki_pid_t) );
+ if (ARG1 != 0) {
+ POST_MEM_WRITE( ARG1, sizeof(vki_pid_t) );
+ }
}
@@ -3107,7 +3125,7 @@
PRINT("sendmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3);
PRE_REG_READ3(long, "sendmsg",
int, s, const struct msghdr *, msg, int, flags);
- ML_(generic_PRE_sys_sendmsg)(tid, ARG1,ARG2);
+ ML_(generic_PRE_sys_sendmsg)(tid, "msg", (struct vki_msghdr *)ARG2);
}
@@ -3116,12 +3134,12 @@
*flags |= SfMayBlock;
PRINT("recvmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3);
PRE_REG_READ3(long, "recvmsg", int, s, struct msghdr *, msg, int, flags);
- ML_(generic_PRE_sys_recvmsg)(tid, ARG1,ARG2);
+ ML_(generic_PRE_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2);
}
POST(recvmsg)
{
- ML_(generic_POST_sys_recvmsg)(tid, ARG1,ARG2);
+ ML_(generic_POST_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2, RES);
}
@@ -3521,6 +3539,7 @@
PRE(mmap)
{
// SysRes r;
+ if (0) VG_(am_do_sync_check)("(PRE_MMAP)",__FILE__,__LINE__);
#if VG_WORDSIZE == 4
PRINT("mmap ( %#lx, %lu, %ld, %ld, %ld, %lld )",
@@ -4986,6 +5005,8 @@
PRINT("task_get_special_port(%s, TASK_BOOTSTRAP_PORT)",
name_for_port(MACH_REMOTE));
break;
+#if DARWIN_VERS != DARWIN_10_8
+ /* These disappeared in 10.8 */
case TASK_WIRED_LEDGER_PORT:
PRINT("task_get_special_port(%s, TASK_WIRED_LEDGER_PORT)",
name_for_port(MACH_REMOTE));
@@ -4994,6 +5015,7 @@
PRINT("task_get_special_port(%s, TASK_PAGED_LEDGER_PORT)",
name_for_port(MACH_REMOTE));
break;
+#endif
default:
PRINT("task_get_special_port(%s, %d)",
name_for_port(MACH_REMOTE), req->which_port);
@@ -5032,12 +5054,15 @@
case TASK_HOST_PORT:
assign_port_name(reply->special_port.name, "host");
break;
+#if DARWIN_VERS != DARWIN_10_8
+ /* These disappeared in 10.8 */
case TASK_WIRED_LEDGER_PORT:
assign_port_name(reply->special_port.name, "wired-ledger");
break;
case TASK_PAGED_LEDGER_PORT:
assign_port_name(reply->special_port.name, "paged-ledger");
break;
+#endif
default:
assign_port_name(reply->special_port.name, "special-%p");
break;
@@ -6483,6 +6508,7 @@
// should be in pthread_hijack instead, just before the call to
// start_thread_NORETURN(), call_on_new_stack_0_1(), but we don't have the
// parent tid value there...
+ vg_assert(VG_(owns_BigLock_LL)(tid));
VG_TRACK ( pre_thread_ll_create, tid, tst->tid );
}
@@ -6502,7 +6528,13 @@
if (ARG4) semaphore_signal((semaphore_t)ARG4);
if (ARG1 && ARG2) {
ML_(notify_core_and_tool_of_munmap)(ARG1, ARG2);
+# if DARWIN_VERS == DARWIN_10_8
+ /* JRS 2012 Aug 02: ugly hack: vm_deallocate disappeared from
+ the mig output. Work around it for the time being. */
+ VG_(do_syscall2)(__NR_munmap, ARG1, ARG2);
+# else
vm_deallocate(mach_task_self(), (vm_address_t)ARG1, (vm_size_t)ARG2);
+# endif
}
// Tell V to terminate the thread.
@@ -7810,16 +7842,74 @@
/* ---------------------------------------------------------------------
+ Added for OSX 10.8 (Mountain Lion)
+ ------------------------------------------------------------------ */
+
+#if DARWIN_VERS == DARWIN_10_8
+
+PRE(mach__10)
+{
+ PRINT("mach__10(ARGUMENTS_UNKNOWN)");
+}
+POST(mach__10)
+{
+ ML_(sync_mappings)("after", "mach__10", 0);
+}
+
+PRE(mach__12)
+{
+ PRINT("mach__12(ARGUMENTS_UNKNOWN)");
+}
+POST(mach__12)
+{
+ ML_(sync_mappings)("after", "mach__12", 0);
+}
+
+PRE(mach__14)
+{
+ PRINT("mach__14(ARGUMENTS_UNKNOWN)");
+}
+
+PRE(mach__16)
+{
+ PRINT("mach__16(ARGUMENTS_UNKNOWN)");
+}
+
+PRE(mach__18)
+{
+ PRINT("mach__18(ARGUMENTS_UNKNOWN)");
+}
+
+PRE(mach__19)
+{
+ PRINT("mach__19(ARGUMENTS_UNKNOWN)");
+}
+
+PRE(mach__20)
+{
+ PRINT("mach__20(ARGUMENTS_UNKNOWN)");
+}
+
+PRE(mach__21)
+{
+ PRINT("mach__21(ARGUMENTS_UNKNOWN)");
+}
+
+#endif /* DARWIN_VERS == DARWIN_10_8 */
+
+
+/* ---------------------------------------------------------------------
syscall tables
------------------------------------------------------------------ */
/* Add a Darwin-specific, arch-independent wrapper to a syscall table. */
#define MACX_(sysno, name) WRAPPER_ENTRY_X_(darwin, VG_DARWIN_SYSNO_INDEX(sysno), name)
#define MACXY(sysno, name) WRAPPER_ENTRY_XY(darwin, VG_DARWIN_SYSNO_INDEX(sysno), name)
-#define _____(sysno) GENX_(sysno, sys_ni_syscall)
+#define _____(sysno) GENX_(sysno, sys_ni_syscall) /* UNIX style only */
/*
- _____ : unsupported by the kernel (sys_ni_syscall)
+ _____ : unsupported by the kernel (sys_ni_syscall) (UNIX-style only)
+ unfortunately misused for Mach too, causing assertion failures
// _____ : unimplemented in valgrind
GEN : handlers are in syswrap-generic.c
MAC : handlers are in this file
@@ -8112,7 +8202,7 @@
MACXY(__NR_shmdt, shmdt),
MACX_(__NR_shmget, shmget),
MACXY(__NR_shm_open, shm_open),
-// _____(__NR_shm_unlink),
+ MACXY(__NR_shm_unlink, shm_unlink),
MACX_(__NR_sem_open, sem_open),
MACX_(__NR_sem_close, sem_close),
MACX_(__NR_sem_unlink, sem_unlink),
@@ -8314,18 +8404,51 @@
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(7)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(8)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(9)),
+
+# if DARWIN_VERS == DARWIN_10_8
+ MACXY(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(10), mach__10),
+# else
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(10)),
+# endif
+
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(11)),
+
+# if DARWIN_VERS == DARWIN_10_8
+ MACXY(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(12), mach__12),
+# else
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(12)),
+# endif
+
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(13)),
+
+# if DARWIN_VERS == DARWIN_10_8
+ MACX_(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(14), mach__14),
+# else
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(14)),
+# endif
+
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(15)),
+
+# if DARWIN_VERS == DARWIN_10_8
+ MACX_(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(16), mach__16),
+# else
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(16)),
+# endif
+
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(17)),
+
+# if DARWIN_VERS == DARWIN_10_8
+ MACX_(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(18), mach__18),
+ MACX_(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(19), mach__19),
+ MACX_(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(20), mach__20),
+ MACX_(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(21), mach__21),
+# else
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(18)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(19)),
- _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(20)), // -20
+ _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(20)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(21)),
+# endif
+
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(22)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(23)),
_____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(24)),
diff --git a/main/coregrind/m_syswrap/syswrap-generic.c b/main/coregrind/m_syswrap/syswrap-generic.c
index 8b9c34a..46d4531 100644
--- a/main/coregrind/m_syswrap/syswrap-generic.c
+++ b/main/coregrind/m_syswrap/syswrap-generic.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -161,8 +161,6 @@
static void notify_tool_of_mmap(Addr a, SizeT len, UInt prot, ULong di_handle)
{
- SizeT fourgig = (1ULL << 32);
- SizeT guardpage = 10 * fourgig;
Bool rr, ww, xx;
/* 'a' is the return value from a real kernel mmap, hence: */
@@ -174,12 +172,6 @@
ww = toBool(prot & VKI_PROT_WRITE);
xx = toBool(prot & VKI_PROT_EXEC);
-#ifdef VGA_amd64
- if (len >= fourgig + 2 * guardpage) {
- VG_(printf)("Valgrind: ignoring NaCl's mmap(84G)\n");
- return;
- }
-#endif // VGA_amd64
VG_TRACK( new_mem_mmap, a, len, rr, ww, xx, di_handle );
}
@@ -411,16 +403,8 @@
non-fixed, which is not what we want */
advised = VG_(am_get_advisory_client_simple)( needA, needL, &ok );
if (ok) {
- /* VG_(am_get_advisory_client_simple) (first arg == 0, meaning
- this-or-nothing) is too lenient, and may allow us to trash
- the next segment along. So make very sure that the proposed
- new area really is free. This is perhaps overly
- conservative, but it fixes #129866. */
- NSegment const* segLo = VG_(am_find_nsegment)( needA );
- NSegment const* segHi = VG_(am_find_nsegment)( needA + needL - 1 );
- if (segLo == NULL || segHi == NULL
- || segLo != segHi || segLo->kind != SkFree)
- ok = False;
+ /* Fixes bug #129866. */
+ ok = VG_(am_covered_by_single_free_segment) ( needA, needL );
}
if (ok && advised == needA) {
ok = VG_(am_extend_map_client)( &d, (NSegment*)old_seg, needL );
@@ -474,15 +458,8 @@
non-fixed, which is not what we want */
advised = VG_(am_get_advisory_client_simple)( needA, needL, &ok );
if (ok) {
- /* VG_(am_get_advisory_client_simple) (first arg == 0, meaning
- this-or-nothing) is too lenient, and may allow us to trash
- the next segment along. So make very sure that the proposed
- new area really is free. */
- NSegment const* segLo = VG_(am_find_nsegment)( needA );
- NSegment const* segHi = VG_(am_find_nsegment)( needA + needL - 1 );
- if (segLo == NULL || segHi == NULL
- || segLo != segHi || segLo->kind != SkFree)
- ok = False;
+ /* Fixes bug #129866. */
+ ok = VG_(am_covered_by_single_free_segment) ( needA, needL );
}
if (!ok || advised != needA)
goto eNOMEM;
@@ -839,7 +816,7 @@
Char *msg, Addr base, SizeT size )
{
Char *outmsg = strdupcat ( "di.syswrap.pmrs.1",
- "socketcall.sendmsg", msg, VG_AR_CORE );
+ "sendmsg", msg, VG_AR_CORE );
PRE_MEM_READ( outmsg, base, size );
VG_(arena_free) ( VG_AR_CORE, outmsg );
}
@@ -849,7 +826,7 @@
Char *msg, Addr base, SizeT size )
{
Char *outmsg = strdupcat ( "di.syswrap.pmwr.1",
- "socketcall.recvmsg", msg, VG_AR_CORE );
+ "recvmsg", msg, VG_AR_CORE );
if ( read )
PRE_MEM_READ( outmsg, base, size );
else
@@ -867,45 +844,62 @@
static
void msghdr_foreachfield (
- ThreadId tid,
- struct vki_msghdr *msg,
+ ThreadId tid,
+ Char *name,
+ struct vki_msghdr *msg,
+ UInt length,
void (*foreach_func)( ThreadId, Bool, Char *, Addr, SizeT )
)
{
+ Char *fieldName;
+
if ( !msg )
return;
- foreach_func ( tid, True, "(msg)", (Addr)&msg->msg_name, sizeof( msg->msg_name ) );
- foreach_func ( tid, True, "(msg)", (Addr)&msg->msg_namelen, sizeof( msg->msg_namelen ) );
- foreach_func ( tid, True, "(msg)", (Addr)&msg->msg_iov, sizeof( msg->msg_iov ) );
- foreach_func ( tid, True, "(msg)", (Addr)&msg->msg_iovlen, sizeof( msg->msg_iovlen ) );
- foreach_func ( tid, True, "(msg)", (Addr)&msg->msg_control, sizeof( msg->msg_control ) );
- foreach_func ( tid, True, "(msg)", (Addr)&msg->msg_controllen, sizeof( msg->msg_controllen ) );
- foreach_func ( tid, False, "(msg)", (Addr)&msg->msg_flags, sizeof( msg->msg_flags ) );
+ fieldName = VG_(arena_malloc) ( VG_AR_CORE, "di.syswrap.mfef", VG_(strlen)(name) + 32 );
- if ( msg->msg_name )
- foreach_func ( tid, False,
- "(msg.msg_name)",
+ VG_(sprintf) ( fieldName, "(%s)", name );
+
+ foreach_func ( tid, True, fieldName, (Addr)&msg->msg_name, sizeof( msg->msg_name ) );
+ foreach_func ( tid, True, fieldName, (Addr)&msg->msg_namelen, sizeof( msg->msg_namelen ) );
+ foreach_func ( tid, True, fieldName, (Addr)&msg->msg_iov, sizeof( msg->msg_iov ) );
+ foreach_func ( tid, True, fieldName, (Addr)&msg->msg_iovlen, sizeof( msg->msg_iovlen ) );
+ foreach_func ( tid, True, fieldName, (Addr)&msg->msg_control, sizeof( msg->msg_control ) );
+ foreach_func ( tid, True, fieldName, (Addr)&msg->msg_controllen, sizeof( msg->msg_controllen ) );
+ foreach_func ( tid, False, fieldName, (Addr)&msg->msg_flags, sizeof( msg->msg_flags ) );
+
+ if ( msg->msg_name ) {
+ VG_(sprintf) ( fieldName, "(%s.msg_name)", name );
+ foreach_func ( tid, False, fieldName,
(Addr)msg->msg_name, msg->msg_namelen );
+ }
if ( msg->msg_iov ) {
struct vki_iovec *iov = msg->msg_iov;
UInt i;
- foreach_func ( tid, True,
- "(msg.msg_iov)",
+ VG_(sprintf) ( fieldName, "(%s.msg_iov)", name );
+
+ foreach_func ( tid, True, fieldName,
(Addr)iov, msg->msg_iovlen * sizeof( struct vki_iovec ) );
- for ( i = 0; i < msg->msg_iovlen; ++i, ++iov )
- foreach_func ( tid, False,
- "(msg.msg_iov[i])",
- (Addr)iov->iov_base, iov->iov_len );
+ for ( i = 0; i < msg->msg_iovlen; ++i, ++iov ) {
+ UInt iov_len = iov->iov_len <= length ? iov->iov_len : length;
+ VG_(sprintf) ( fieldName, "(%s.msg_iov[%u])", name, i );
+ foreach_func ( tid, False, fieldName,
+ (Addr)iov->iov_base, iov_len );
+ length = length - iov_len;
+ }
}
- if ( msg->msg_control )
- foreach_func ( tid, False,
- "(msg.msg_control)",
+ if ( msg->msg_control )
+ {
+ VG_(sprintf) ( fieldName, "(%s.msg_control)", name );
+ foreach_func ( tid, False, fieldName,
(Addr)msg->msg_control, msg->msg_controllen );
+ }
+
+ VG_(arena_free) ( VG_AR_CORE, fieldName );
}
static void check_cmsg_for_fds(ThreadId tid, struct vki_msghdr *msg)
@@ -1513,31 +1507,23 @@
/* ------ */
void
-ML_(generic_PRE_sys_sendmsg) ( ThreadId tid,
- UWord arg0, UWord arg1 )
+ML_(generic_PRE_sys_sendmsg) ( ThreadId tid, Char *name, struct vki_msghdr *msg )
{
- /* int sendmsg(int s, const struct msghdr *msg, int flags); */
- struct vki_msghdr *msg = (struct vki_msghdr *)arg1;
- msghdr_foreachfield ( tid, msg, pre_mem_read_sendmsg );
+ msghdr_foreachfield ( tid, name, msg, ~0, pre_mem_read_sendmsg );
}
/* ------ */
void
-ML_(generic_PRE_sys_recvmsg) ( ThreadId tid,
- UWord arg0, UWord arg1 )
+ML_(generic_PRE_sys_recvmsg) ( ThreadId tid, Char *name, struct vki_msghdr *msg )
{
- /* int recvmsg(int s, struct msghdr *msg, int flags); */
- struct vki_msghdr *msg = (struct vki_msghdr *)arg1;
- msghdr_foreachfield ( tid, msg, pre_mem_write_recvmsg );
+ msghdr_foreachfield ( tid, name, msg, ~0, pre_mem_write_recvmsg );
}
void
-ML_(generic_POST_sys_recvmsg) ( ThreadId tid,
- UWord arg0, UWord arg1 )
+ML_(generic_POST_sys_recvmsg) ( ThreadId tid, Char *name, struct vki_msghdr *msg, UInt length )
{
- struct vki_msghdr *msg = (struct vki_msghdr *)arg1;
- msghdr_foreachfield( tid, msg, post_mem_write_recvmsg );
+ msghdr_foreachfield( tid, name, msg, length, post_mem_write_recvmsg );
check_cmsg_for_fds( tid, msg );
}
@@ -1714,7 +1700,7 @@
/* ------ */
static
-UInt get_shm_size ( Int shmid )
+SizeT get_shm_size ( Int shmid )
{
#ifdef __NR_shmctl
# ifdef VKI_IPC_64
@@ -1739,7 +1725,7 @@
if (sr_isError(__res))
return 0;
- return buf.shm_segsz;
+ return (SizeT) buf.shm_segsz;
}
UWord
@@ -1747,7 +1733,7 @@
UWord arg0, UWord arg1, UWord arg2 )
{
/* void *shmat(int shmid, const void *shmaddr, int shmflg); */
- UInt segmentSize = get_shm_size ( arg0 );
+ SizeT segmentSize = get_shm_size ( arg0 );
UWord tmp;
Bool ok;
if (arg1 == 0) {
@@ -1782,7 +1768,7 @@
UWord res,
UWord arg0, UWord arg1, UWord arg2 )
{
- UInt segmentSize = VG_PGROUNDUP(get_shm_size(arg0));
+ SizeT segmentSize = VG_PGROUNDUP(get_shm_size(arg0));
if ( segmentSize > 0 ) {
UInt prot = VKI_PROT_READ|VKI_PROT_WRITE;
Bool d;
@@ -2567,6 +2553,7 @@
SET_STATUS_Failure( VKI_EFAULT );
return;
}
+
// debug-only printing
if (0) {
VG_(printf)("ARG1 = %p(%s)\n", (void*)ARG1, (HChar*)ARG1);
@@ -2649,11 +2636,6 @@
} else {
path = (Char*)ARG1;
- if (VG_(clo_xml)) {
- VG_(printf_xml)("\n<execv/>\n\n</valgrindoutput>\n\n");
- } else {
- VG_(umsg)("execv called - the tool will now quit\n");
- }
}
// Set up the child's environment.
@@ -3935,7 +3917,11 @@
arg1 &= ~_RLIMIT_POSIX_FLAG;
#endif
- if (arg1 == VKI_RLIMIT_NOFILE) {
+ if (ARG2 &&
+ ((struct vki_rlimit *)ARG2)->rlim_cur > ((struct vki_rlimit *)ARG2)->rlim_max) {
+ SET_STATUS_Failure( VKI_EINVAL );
+ }
+ else if (arg1 == VKI_RLIMIT_NOFILE) {
if (((struct vki_rlimit *)ARG2)->rlim_cur > VG_(fd_hard_limit) ||
((struct vki_rlimit *)ARG2)->rlim_max != VG_(fd_hard_limit)) {
SET_STATUS_Failure( VKI_EPERM );
@@ -4206,3 +4192,4 @@
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
+
diff --git a/main/coregrind/m_syswrap/syswrap-linux-variants.c b/main/coregrind/m_syswrap/syswrap-linux-variants.c
index 2c8d8c4..c516a08 100644
--- a/main/coregrind/m_syswrap/syswrap-linux-variants.c
+++ b/main/coregrind/m_syswrap/syswrap-linux-variants.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_syswrap/syswrap-linux.c b/main/coregrind/m_syswrap/syswrap-linux.c
index 3925e24..2f1155f 100644
--- a/main/coregrind/m_syswrap/syswrap-linux.c
+++ b/main/coregrind/m_syswrap/syswrap-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -47,6 +47,7 @@
#include "pub_core_libcprint.h"
#include "pub_core_libcproc.h"
#include "pub_core_libcsignal.h"
+#include "pub_core_machine.h" // VG_(get_SP)
#include "pub_core_mallocfree.h"
#include "pub_core_tooliface.h"
#include "pub_core_options.h"
@@ -54,6 +55,10 @@
#include "pub_core_signals.h"
#include "pub_core_syscall.h"
#include "pub_core_syswrap.h"
+#include "pub_tool_inner.h"
+#if defined(ENABLE_INNER_CLIENT_REQUEST)
+#include "valgrind.h"
+#endif
#include "priv_types_n_macros.h"
#include "priv_syswrap-generic.h"
@@ -123,6 +128,9 @@
VgSchedReturnCode src;
Int c;
ThreadState* tst;
+#ifdef ENABLE_INNER_CLIENT_REQUEST
+ Int registered_vgstack_id;
+#endif
VG_(debugLog)(1, "syswrap-linux",
"run_a_thread_NORETURN(tid=%lld): pre-thread_wrapper\n",
@@ -131,6 +139,19 @@
tst = VG_(get_ThreadState)(tid);
vg_assert(tst);
+ /* An thread has two stacks:
+ * the simulated stack (used by the synthetic cpu. Guest process
+ is using this stack).
+ * the valgrind stack (used by the real cpu. Valgrind code is running
+ on this stack).
+ When Valgrind runs as an inner, it must signals that its (real) stack
+ is the stack to use by the outer to e.g. do stacktraces.
+ */
+ INNER_REQUEST
+ (registered_vgstack_id
+ = VALGRIND_STACK_REGISTER (tst->os_state.valgrind_stack_base,
+ tst->os_state.valgrind_stack_init_SP));
+
/* Run the thread all the way through. */
src = thread_wrapper(tid);
@@ -190,6 +211,8 @@
VG_(exit_thread)(tid);
vg_assert(tst->status == VgTs_Zombie);
+ INNER_REQUEST (VALGRIND_STACK_DEREGISTER (registered_vgstack_id));
+
/* We have to use this sequence to terminate the thread to
prevent a subtle race. If VG_(exit_thread)() had left the
ThreadState as Empty, then it could have been reallocated,
@@ -200,13 +223,15 @@
assembler. */
#if defined(VGP_x86_linux)
asm volatile (
+ "pushl %%ebx\n"
"movl %1, %0\n" /* set tst->status = VgTs_Empty */
"movl %2, %%eax\n" /* set %eax = __NR_exit */
"movl %3, %%ebx\n" /* set %ebx = tst->os_state.exitcode */
"int $0x80\n" /* exit(tst->os_state.exitcode) */
+ "popl %%ebx\n"
: "=m" (tst->status)
: "n" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode)
- : "eax"/*, "ebx"*/ // EBX is a PIC register.
+ : "eax"
);
#elif defined(VGP_amd64_linux)
asm volatile (
@@ -249,6 +274,17 @@
: "d" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode)
: "2"
);
+#elif defined(VGP_mips32_linux)
+ asm volatile (
+ "sw %1, %0\n\t" /* set tst->status = VgTs_Empty */
+ "li $2, %2\n\t" /* set v0 = __NR_exit */
+ "lw $4, %3\n\t" /* set a0 = tst->os_state.exitcode */
+ "syscall\n\t" /* exit(tst->os_state.exitcode) */
+ "nop"
+ : "=m" (tst->status)
+ : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode)
+ : "cc", "memory" , "v0", "a0"
+ );
#else
# error Unknown platform
#endif
@@ -320,6 +356,18 @@
"entering VG_(main_thread_wrapper_NORETURN)\n");
sp = ML_(allocstack)(tid);
+#if defined(ENABLE_INNER_CLIENT_REQUEST)
+ {
+ // we must register the main thread stack before the call
+ // to ML_(call_on_new_stack_0_1), otherwise the outer valgrind
+ // reports 'write error' on the non registered stack.
+ ThreadState* tst = VG_(get_ThreadState)(tid);
+ INNER_REQUEST
+ ((void)
+ VALGRIND_STACK_REGISTER (tst->os_state.valgrind_stack_base,
+ tst->os_state.valgrind_stack_init_SP));
+ }
+#endif
#if defined(VGP_ppc32_linux)
/* make a stack frame */
@@ -380,7 +428,7 @@
VG_(clone) stuff */
#if defined(VGP_x86_linux) \
|| defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
- || defined(VGP_arm_linux)
+ || defined(VGP_arm_linux) || defined(VGP_mips32_linux)
res = VG_(do_syscall5)( __NR_clone, flags,
(UWord)NULL, (UWord)parent_tidptr,
(UWord)NULL, (UWord)child_tidptr );
@@ -962,9 +1010,20 @@
struct timespec *, utime, vki_u32 *, uaddr2);
break;
case VKI_FUTEX_WAIT_BITSET:
- PRE_REG_READ6(long, "futex",
- vki_u32 *, futex, int, op, int, val,
- struct timespec *, utime, int, dummy, int, val3);
+ /* Check that the address at least begins in client-accessible area. */
+ if (!VG_(am_is_valid_for_client)( ARG1, 1, VKI_PROT_READ )) {
+ SET_STATUS_Failure( VKI_EFAULT );
+ return;
+ }
+ if (*(vki_u32 *)ARG1 != ARG3) {
+ PRE_REG_READ5(long, "futex",
+ vki_u32 *, futex, int, op, int, val,
+ struct timespec *, utime, int, dummy);
+ } else {
+ PRE_REG_READ6(long, "futex",
+ vki_u32 *, futex, int, op, int, val,
+ struct timespec *, utime, int, dummy, int, val3);
+ }
break;
case VKI_FUTEX_WAKE_BITSET:
PRE_REG_READ6(long, "futex",
@@ -1285,30 +1344,74 @@
PRE_MEM_READ( "rlimit64(new_rlim)", ARG3, sizeof(struct vki_rlimit64) );
if (ARG4)
PRE_MEM_WRITE( "rlimit64(old_rlim)", ARG4, sizeof(struct vki_rlimit64) );
+
+ if (ARG3 &&
+ ((struct vki_rlimit64 *)ARG3)->rlim_cur > ((struct vki_rlimit64 *)ARG3)->rlim_max) {
+ SET_STATUS_Failure( VKI_EINVAL );
+ }
+ else if (ARG1 == 0 || ARG1 == VG_(getpid)()) {
+ switch (ARG2) {
+ case VKI_RLIMIT_NOFILE:
+ SET_STATUS_Success( 0 );
+ if (ARG4) {
+ ((struct vki_rlimit64 *)ARG4)->rlim_cur = VG_(fd_soft_limit);
+ ((struct vki_rlimit64 *)ARG4)->rlim_max = VG_(fd_hard_limit);
+ }
+ if (ARG3) {
+ if (((struct vki_rlimit64 *)ARG3)->rlim_cur > VG_(fd_hard_limit) ||
+ ((struct vki_rlimit64 *)ARG3)->rlim_max != VG_(fd_hard_limit)) {
+ SET_STATUS_Failure( VKI_EPERM );
+ }
+ else {
+ VG_(fd_soft_limit) = ((struct vki_rlimit64 *)ARG3)->rlim_cur;
+ }
+ }
+ break;
+
+ case VKI_RLIMIT_DATA:
+ SET_STATUS_Success( 0 );
+ if (ARG4) {
+ ((struct vki_rlimit64 *)ARG4)->rlim_cur = VG_(client_rlimit_data).rlim_cur;
+ ((struct vki_rlimit64 *)ARG4)->rlim_max = VG_(client_rlimit_data).rlim_max;
+ }
+ if (ARG3) {
+ if (((struct vki_rlimit64 *)ARG3)->rlim_cur > VG_(client_rlimit_data).rlim_max ||
+ ((struct vki_rlimit64 *)ARG3)->rlim_max > VG_(client_rlimit_data).rlim_max) {
+ SET_STATUS_Failure( VKI_EPERM );
+ }
+ else {
+ VG_(client_rlimit_data).rlim_cur = ((struct vki_rlimit64 *)ARG3)->rlim_cur;
+ VG_(client_rlimit_data).rlim_max = ((struct vki_rlimit64 *)ARG3)->rlim_max;
+ }
+ }
+ break;
+
+ case VKI_RLIMIT_STACK:
+ SET_STATUS_Success( 0 );
+ if (ARG4) {
+ ((struct vki_rlimit64 *)ARG4)->rlim_cur = VG_(client_rlimit_stack).rlim_cur;
+ ((struct vki_rlimit64 *)ARG4)->rlim_max = VG_(client_rlimit_stack).rlim_max;
+ }
+ if (ARG3) {
+ if (((struct vki_rlimit64 *)ARG3)->rlim_cur > VG_(client_rlimit_stack).rlim_max ||
+ ((struct vki_rlimit64 *)ARG3)->rlim_max > VG_(client_rlimit_stack).rlim_max) {
+ SET_STATUS_Failure( VKI_EPERM );
+ }
+ else {
+ VG_(threads)[tid].client_stack_szB = ((struct vki_rlimit64 *)ARG3)->rlim_cur;
+ VG_(client_rlimit_stack).rlim_cur = ((struct vki_rlimit64 *)ARG3)->rlim_cur;
+ VG_(client_rlimit_stack).rlim_max = ((struct vki_rlimit64 *)ARG3)->rlim_max;
+ }
+ }
+ break;
+ }
+ }
}
POST(sys_prlimit64)
{
- if (ARG4) {
+ if (ARG4)
POST_MEM_WRITE( ARG4, sizeof(struct vki_rlimit64) );
-
- switch (ARG2) {
- case VKI_RLIMIT_NOFILE:
- ((struct vki_rlimit64 *)ARG4)->rlim_cur = VG_(fd_soft_limit);
- ((struct vki_rlimit64 *)ARG4)->rlim_max = VG_(fd_hard_limit);
- break;
-
- case VKI_RLIMIT_DATA:
- ((struct vki_rlimit64 *)ARG4)->rlim_cur = VG_(client_rlimit_data).rlim_cur;
- ((struct vki_rlimit64 *)ARG4)->rlim_max = VG_(client_rlimit_data).rlim_max;
- break;
-
- case VKI_RLIMIT_STACK:
- ((struct vki_rlimit64 *)ARG4)->rlim_cur = VG_(client_rlimit_stack).rlim_cur;
- ((struct vki_rlimit64 *)ARG4)->rlim_max = VG_(client_rlimit_stack).rlim_max;
- break;
- }
- }
}
/* ---------------------------------------------------------------------
@@ -2705,6 +2808,24 @@
POST_MEM_WRITE( ARG3, sizeof(struct vki_getcpu_cache) );
}
+PRE(sys_move_pages)
+{
+ PRINT("sys_move_pages ( %ld, %ld, %#lx, %#lx, %#lx, %lx )",
+ ARG1,ARG2,ARG3,ARG4,ARG5,ARG6);
+ PRE_REG_READ6(int, "move_pages",
+ vki_pid_t, pid, unsigned long, nr_pages, const void **, pages,
+ const int *, nodes, int *, status, int, flags);
+ PRE_MEM_READ("move_pages(pages)", ARG3, ARG2 * sizeof(void *));
+ if (ARG4)
+ PRE_MEM_READ("move_pages(nodes)", ARG4, ARG2 * sizeof(int));
+ PRE_MEM_WRITE("move_pages(status)", ARG5, ARG2 * sizeof(int));
+}
+
+POST(sys_move_pages)
+{
+ POST_MEM_WRITE(ARG5, ARG2 * sizeof(int));
+}
+
/* ---------------------------------------------------------------------
utime wrapper
------------------------------------------------------------------ */
@@ -2773,7 +2894,8 @@
// This wrapper is only suitable for 32-bit architectures.
// (XXX: so how is it that PRE(sys_sigpending) above doesn't need
// conditional compilation like this?)
-#if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) || defined(VGP_arm_linux)
+#if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
+ || defined(VGP_arm_linux) || defined(VGP_mips32_linux)
PRE(sys_sigprocmask)
{
vki_old_sigset_t* set;
@@ -3472,6 +3594,139 @@
}
/* ---------------------------------------------------------------------
+ process_vm_{read,write}v wrappers
+ ------------------------------------------------------------------ */
+
+PRE(sys_process_vm_readv)
+{
+ PRINT("sys_process_vm_readv ( %lu, %#lx, %lu, %#lx, %lu, %lu )",
+ ARG1, ARG2, ARG3, ARG4, ARG5, ARG6);
+ PRE_REG_READ6(ssize_t, "process_vm_readv",
+ vki_pid_t, pid,
+ const struct iovec *, lvec,
+ unsigned long, liovcnt,
+ const struct iovec *, rvec,
+ unsigned long, riovcnt,
+ unsigned long, flags);
+ PRE_MEM_READ( "process_vm_readv(lvec)",
+ ARG2, ARG3 * sizeof(struct vki_iovec) );
+ PRE_MEM_READ( "process_vm_readv(rvec)",
+ ARG4, ARG5 * sizeof(struct vki_iovec) );
+ if (ARG2 != 0) {
+ /* TODO: Don't do any of the following if lvec is invalid */
+ const struct vki_iovec *vec = (const struct vki_iovec *)ARG2;
+ UInt i;
+ for (i = 0; i < ARG3; i++)
+ PRE_MEM_WRITE( "process_vm_readv(lvec[...])",
+ (Addr)vec[i].iov_base, vec[i].iov_len );
+ }
+}
+
+POST(sys_process_vm_readv)
+{
+ const struct vki_iovec *vec = (const struct vki_iovec *)ARG2;
+ UInt remains = RES;
+ UInt i;
+ for (i = 0; i < ARG3; i++) {
+ UInt nReadThisBuf = vec[i].iov_len <= remains ?
+ vec[i].iov_len : remains;
+ POST_MEM_WRITE( (Addr)vec[i].iov_base, nReadThisBuf );
+ remains -= nReadThisBuf;
+ }
+}
+
+PRE(sys_process_vm_writev)
+{
+ PRINT("sys_process_vm_writev ( %lu, %#lx, %lu, %#lx, %lu, %lu )",
+ ARG1, ARG2, ARG3, ARG4, ARG5, ARG6);
+ PRE_REG_READ6(ssize_t, "process_vm_writev",
+ vki_pid_t, pid,
+ const struct iovec *, lvec,
+ unsigned long, liovcnt,
+ const struct iovec *, rvec,
+ unsigned long, riovcnt,
+ unsigned long, flags);
+ PRE_MEM_READ( "process_vm_writev(lvec)",
+ ARG2, ARG3 * sizeof(struct vki_iovec) );
+ PRE_MEM_READ( "process_vm_writev(rvec)",
+ ARG4, ARG5 * sizeof(struct vki_iovec) );
+ if (ARG2 != 0) {
+ /* TODO: Don't do any of the following if lvec is invalid */
+ const struct vki_iovec *vec = (const struct vki_iovec *)ARG2;
+ UInt i;
+ for (i = 0; i < ARG3; i++)
+ PRE_MEM_READ( "process_vm_writev(lvec[...])",
+ (Addr)vec[i].iov_base, vec[i].iov_len );
+ }
+}
+
+/* ---------------------------------------------------------------------
+ {send,recv}mmsg wrappers
+ ------------------------------------------------------------------ */
+
+PRE(sys_sendmmsg)
+{
+ struct vki_mmsghdr *mmsg = (struct vki_mmsghdr *)ARG2;
+ Char name[32];
+ UInt i;
+ *flags |= SfMayBlock;
+ PRINT("sys_sendmmsg ( %ld, %#lx, %ld, %ld )",ARG1,ARG2,ARG3,ARG4);
+ PRE_REG_READ4(long, "sendmmsg",
+ int, s, const struct mmsghdr *, mmsg, int, vlen, int, flags);
+ for (i = 0; i < ARG3; i++) {
+ VG_(sprintf)(name, "mmsg[%u].msg_hdr", i);
+ ML_(generic_PRE_sys_sendmsg)(tid, name, &mmsg[i].msg_hdr);
+ VG_(sprintf)(name, "sendmmsg(mmsg[%u].msg_len)", i);
+ PRE_MEM_WRITE( name, (Addr)&mmsg[i].msg_len, sizeof(mmsg[i].msg_len) );
+ }
+}
+
+POST(sys_sendmmsg)
+{
+ if (RES > 0) {
+ struct vki_mmsghdr *mmsg = (struct vki_mmsghdr *)ARG2;
+ UInt i;
+ for (i = 0; i < RES; i++) {
+ POST_MEM_WRITE( (Addr)&mmsg[i].msg_len, sizeof(mmsg[i].msg_len) );
+ }
+ }
+}
+
+PRE(sys_recvmmsg)
+{
+ struct vki_mmsghdr *mmsg = (struct vki_mmsghdr *)ARG2;
+ Char name[32];
+ UInt i;
+ *flags |= SfMayBlock;
+ PRINT("sys_recvmmsg ( %ld, %#lx, %ld, %ld, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5);
+ PRE_REG_READ5(long, "recvmmsg",
+ int, s, struct mmsghdr *, mmsg, int, vlen,
+ int, flags, struct timespec *, timeout);
+ for (i = 0; i < ARG3; i++) {
+ VG_(sprintf)(name, "mmsg[%u].msg_hdr", i);
+ ML_(generic_PRE_sys_recvmsg)(tid, name, &mmsg[i].msg_hdr);
+ VG_(sprintf)(name, "recvmmsg(mmsg[%u].msg_len)", i);
+ PRE_MEM_WRITE( name, (Addr)&mmsg[i].msg_len, sizeof(mmsg[i].msg_len) );
+ }
+ if (ARG5)
+ PRE_MEM_READ( "recvmmsg(timeout)", ARG5, sizeof(struct vki_timespec) );
+}
+
+POST(sys_recvmmsg)
+{
+ if (RES > 0) {
+ struct vki_mmsghdr *mmsg = (struct vki_mmsghdr *)ARG2;
+ Char name[32];
+ UInt i;
+ for (i = 0; i < RES; i++) {
+ VG_(sprintf)(name, "mmsg[%u].msg_hdr", i);
+ ML_(generic_POST_sys_recvmsg)(tid, name, &mmsg[i].msg_hdr, mmsg[i].msg_len);
+ POST_MEM_WRITE( (Addr)&mmsg[i].msg_len, sizeof(mmsg[i].msg_len) );
+ }
+ }
+}
+
+/* ---------------------------------------------------------------------
key retention service wrappers
------------------------------------------------------------------ */
@@ -3685,7 +3940,7 @@
*flags |= SfMayBlock;
PRINT("sys_splice ( %ld, %#lx, %ld, %#lx, %ld, %ld )",
ARG1,ARG2,ARG3,ARG4,ARG5,ARG6);
- PRE_REG_READ6(int32_t, "splice",
+ PRE_REG_READ6(vki_ssize_t, "splice",
int, fd_in, vki_loff_t *, off_in,
int, fd_out, vki_loff_t *, off_out,
vki_size_t, len, unsigned int, flags);
@@ -3700,6 +3955,64 @@
}
}
+PRE(sys_tee)
+{
+ *flags |= SfMayBlock;
+ PRINT("sys_tree ( %ld, %ld, %ld, %ld )", ARG1,ARG2,ARG3,ARG4);
+ PRE_REG_READ4(vki_ssize_t, "tee",
+ int, fd_in, int, fd_out,
+ vki_size_t, len, unsigned int, flags);
+ if (!ML_(fd_allowed)(ARG1, "tee(fd_in)", tid, False) ||
+ !ML_(fd_allowed)(ARG2, "tee(fd_out)", tid, False)) {
+ SET_STATUS_Failure( VKI_EBADF );
+ }
+}
+
+PRE(sys_vmsplice)
+{
+ Int fdfl;
+ *flags |= SfMayBlock;
+ PRINT("sys_vmsplice ( %ld, %#lx, %ld, %ld )",
+ ARG1,ARG2,ARG3,ARG4);
+ PRE_REG_READ4(vki_ssize_t, "splice",
+ int, fd, struct vki_iovec *, iov,
+ unsigned long, nr_segs, unsigned int, flags);
+ if (!ML_(fd_allowed)(ARG1, "vmsplice(fd)", tid, False)) {
+ SET_STATUS_Failure( VKI_EBADF );
+ } else if ((fdfl = VG_(fcntl)(ARG1, VKI_F_GETFL, 0)) < 0) {
+ SET_STATUS_Failure( VKI_EBADF );
+ } else {
+ const struct vki_iovec *iov;
+ PRE_MEM_READ( "vmsplice(iov)", ARG2, sizeof(struct vki_iovec) * ARG3 );
+ for (iov = (struct vki_iovec *)ARG2;
+ iov < (struct vki_iovec *)ARG2 + ARG3; iov++)
+ {
+ if ((fdfl & (VKI_O_WRONLY|VKI_O_RDWR)) != 0)
+ PRE_MEM_READ( "vmsplice(iov[...])", (Addr)iov->iov_base, iov->iov_len );
+ else if ((fdfl & VKI_O_RDONLY) != 0)
+ PRE_MEM_WRITE( "vmsplice(iov[...])", (Addr)iov->iov_base, iov->iov_len );
+ }
+ }
+}
+
+POST(sys_vmsplice)
+{
+ vg_assert(SUCCESS);
+ if (RES > 0) {
+ Int fdfl = VG_(fcntl)(ARG1, VKI_F_GETFL, 0);
+ vg_assert(fdfl >= 0);
+ if ((fdfl & VKI_O_RDONLY) != 0)
+ {
+ const struct vki_iovec *iov;
+ for (iov = (struct vki_iovec *)ARG2;
+ iov < (struct vki_iovec *)ARG2 + ARG3; iov++)
+ {
+ POST_MEM_WRITE( (Addr)iov->iov_base, iov->iov_len );
+ }
+ }
+ }
+}
+
/* ---------------------------------------------------------------------
oprofile-related wrappers
------------------------------------------------------------------ */
@@ -3790,6 +4103,22 @@
struct flock64 *, lock);
break;
+ case VKI_F_SETOWN_EX:
+ PRINT("sys_fcntl[F_SETOWN_EX] ( %ld, %ld, %ld )", ARG1,ARG2,ARG3);
+ PRE_REG_READ3(long, "fcntl",
+ unsigned int, fd, unsigned int, cmd,
+ struct vki_f_owner_ex *, arg);
+ PRE_MEM_READ("fcntl(F_SETOWN_EX)", ARG3, sizeof(struct vki_f_owner_ex));
+ break;
+
+ case VKI_F_GETOWN_EX:
+ PRINT("sys_fcntl[F_GETOWN_EX] ( %ld, %ld, %ld )", ARG1,ARG2,ARG3);
+ PRE_REG_READ3(long, "fcntl",
+ unsigned int, fd, unsigned int, cmd,
+ struct vki_f_owner_ex *, arg);
+ PRE_MEM_WRITE("fcntl(F_GETOWN_EX)", ARG3, sizeof(struct vki_f_owner_ex));
+ break;
+
default:
PRINT("sys_fcntl[UNKNOWN] ( %ld, %ld, %ld )", ARG1,ARG2,ARG3);
I_die_here;
@@ -3824,6 +4153,8 @@
if (VG_(clo_track_fds))
ML_(record_fd_open_named)(tid, RES);
}
+ } else if (ARG2 == VKI_F_GETOWN_EX) {
+ POST_MEM_WRITE(ARG3, sizeof(struct vki_f_owner_ex));
}
}
@@ -3869,6 +4200,22 @@
unsigned int, fd, unsigned int, cmd,
struct flock64 *, lock);
break;
+
+ case VKI_F_SETOWN_EX:
+ PRINT("sys_fcntl[F_SETOWN_EX] ( %ld, %ld, %ld )", ARG1,ARG2,ARG3);
+ PRE_REG_READ3(long, "fcntl",
+ unsigned int, fd, unsigned int, cmd,
+ struct vki_f_owner_ex *, arg);
+ PRE_MEM_READ("fcntl(F_SETOWN_EX)", ARG3, sizeof(struct vki_f_owner_ex));
+ break;
+
+ case VKI_F_GETOWN_EX:
+ PRINT("sys_fcntl[F_GETOWN_EX] ( %ld, %ld, %ld )", ARG1,ARG2,ARG3);
+ PRE_REG_READ3(long, "fcntl",
+ unsigned int, fd, unsigned int, cmd,
+ struct vki_f_owner_ex *, arg);
+ PRE_MEM_WRITE("fcntl(F_GETOWN_EX)", ARG3, sizeof(struct vki_f_owner_ex));
+ break;
}
# if defined(VGP_x86_linux)
@@ -3899,6 +4246,8 @@
if (VG_(clo_track_fds))
ML_(record_fd_open_named)(tid, RES);
}
+ } else if (ARG2 == VKI_F_GETOWN_EX) {
+ POST_MEM_WRITE(ARG3, sizeof(struct vki_f_owner_ex));
}
}
@@ -3929,6 +4278,18 @@
case VKI_SNDRV_TIMER_IOCTL_STOP:
case VKI_SNDRV_TIMER_IOCTL_CONTINUE:
case VKI_SNDRV_TIMER_IOCTL_PAUSE:
+
+ /* SCSI no operand */
+ case VKI_SCSI_IOCTL_DOORLOCK:
+ case VKI_SCSI_IOCTL_DOORUNLOCK:
+
+ /* KVM ioctls that dont check for a numeric value as parameter */
+ case VKI_KVM_S390_ENABLE_SIE:
+ case VKI_KVM_S390_INITIAL_RESET:
+
+ /* User input device creation */
+ case VKI_UI_DEV_CREATE:
+ case VKI_UI_DEV_DESTROY:
PRINT("sys_ioctl ( %ld, 0x%lx )",ARG1,ARG2);
PRE_REG_READ2(long, "ioctl",
unsigned int, fd, unsigned int, request);
@@ -4203,6 +4564,13 @@
(Addr)&((struct vki_ifreq *)ARG3)->ifr_map,
sizeof(((struct vki_ifreq *)ARG3)->ifr_map) );
break;
+ case VKI_SIOCSHWTSTAMP: /* Set hardware time stamping */
+ PRE_MEM_RASCIIZ( "ioctl(SIOCSHWTSTAMP)",
+ (Addr)((struct vki_ifreq *)ARG3)->vki_ifr_name );
+ PRE_MEM_READ( "ioctl(SIOCSHWTSTAMP)",
+ (Addr)((struct vki_ifreq *)ARG3)->vki_ifr_data,
+ sizeof(struct vki_hwtstamp_config) );
+ break;
case VKI_SIOCSIFTXQLEN: /* Set the tx queue length */
PRE_MEM_RASCIIZ( "ioctl(SIOCSIFTXQLEN)",
(Addr)((struct vki_ifreq *)ARG3)->vki_ifr_name );
@@ -4414,6 +4782,14 @@
VKI_SIZEOF_STRUCT_HD_DRIVEID );
break;
+ /* SCSI */
+ case VKI_SCSI_IOCTL_GET_IDLUN: /* 0x5382 */
+ PRE_MEM_WRITE( "ioctl(SCSI_IOCTL_GET_IDLUN)", ARG3, sizeof(struct vki_scsi_idlun));
+ break;
+ case VKI_SCSI_IOCTL_GET_BUS_NUMBER: /* 0x5386 */
+ PRE_MEM_WRITE( "ioctl(SCSI_IOCTL_GET_BUS_NUMBER)", ARG3, sizeof(int));
+ break;
+
/* CD ROM stuff (??) */
case VKI_CDROM_GET_MCN:
PRE_MEM_READ( "ioctl(CDROM_GET_MCN)", ARG3,
@@ -4477,6 +4853,8 @@
case VKI_CDROM_DRIVE_STATUS: /* 0x5326 */
case VKI_CDROM_CLEAR_OPTIONS: /* 0x5321 */
break;
+ case VKI_CDROM_GET_CAPABILITY: /* 0x5331 */
+ break;
case VKI_FIGETBSZ:
PRE_MEM_WRITE( "ioctl(FIGETBSZ)", ARG3, sizeof(unsigned long));
@@ -4938,6 +5316,21 @@
case VKI_I2C_FUNCS:
PRE_MEM_WRITE( "ioctl(I2C_FUNCS)", ARG3, sizeof(unsigned long) );
break;
+ case VKI_I2C_RDWR:
+ if ( ARG3 ) {
+ struct vki_i2c_rdwr_ioctl_data *vkui = (struct vki_i2c_rdwr_ioctl_data *)ARG3;
+ UInt i;
+ PRE_MEM_READ("ioctl(I2C_RDWR)", (Addr)vkui, sizeof(struct vki_i2c_rdwr_ioctl_data));
+ for (i=0; i < vkui->nmsgs; i++) {
+ struct vki_i2c_msg *msg = vkui->msgs + i;
+ PRE_MEM_READ("ioctl(I2C_RDWR).msgs", (Addr)msg, sizeof(struct vki_i2c_msg));
+ if (msg->flags & VKI_I2C_M_RD)
+ PRE_MEM_WRITE("ioctl(I2C_RDWR).msgs.buf", (Addr)msg->buf, msg->len);
+ else
+ PRE_MEM_READ("ioctl(I2C_RDWR).msgs.buf", (Addr)msg->buf, msg->len);
+ }
+ }
+ break;
/* Wireless extensions ioctls */
case VKI_SIOCSIWCOMMIT:
@@ -5032,7 +5425,21 @@
}
break;
-# if defined(VGPV_arm_linux_android)
+ /* User input device creation */
+ case VKI_UI_SET_EVBIT:
+ case VKI_UI_SET_KEYBIT:
+ case VKI_UI_SET_RELBIT:
+ case VKI_UI_SET_ABSBIT:
+ case VKI_UI_SET_MSCBIT:
+ case VKI_UI_SET_LEDBIT:
+ case VKI_UI_SET_SNDBIT:
+ case VKI_UI_SET_FFBIT:
+ case VKI_UI_SET_SWBIT:
+ case VKI_UI_SET_PROPBIT:
+ /* These just take an int by value */
+ break;
+
+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
/* ashmem */
case VKI_ASHMEM_GET_SIZE:
case VKI_ASHMEM_SET_SIZE:
@@ -5098,7 +5505,27 @@
PRE_FIELD_WRITE("ioctl(BINDER_VERSION)", bv->protocol_version);
}
break;
-# endif /* defined(VGPV_arm_linux_android) */
+# endif /* defined(VGPV_*_linux_android) */
+
+ case VKI_HCIINQUIRY:
+ if (ARG3) {
+ struct vki_hci_inquiry_req* ir = (struct vki_hci_inquiry_req*)ARG3;
+ PRE_MEM_READ("ioctl(HCIINQUIRY)",
+ (Addr)ARG3, sizeof(struct vki_hci_inquiry_req));
+ PRE_MEM_WRITE("ioctl(HCIINQUIRY)",
+ (Addr)ARG3 + sizeof(struct vki_hci_inquiry_req),
+ ir->num_rsp * sizeof(struct vki_inquiry_info));
+ }
+ break;
+
+ /* KVM ioctls that check for a numeric value as parameter */
+ case VKI_KVM_GET_API_VERSION:
+ case VKI_KVM_CREATE_VM:
+ case VKI_KVM_GET_VCPU_MMAP_SIZE:
+ case VKI_KVM_CHECK_EXTENSION:
+ case VKI_KVM_CREATE_VCPU:
+ case VKI_KVM_RUN:
+ break;
default:
/* EVIOC* are variable length and return size written on success */
@@ -5138,7 +5565,7 @@
/* --- BEGIN special IOCTL handlers for specific Android hardware --- */
-# if defined(VGPV_arm_linux_android)
+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
# if defined(ANDROID_HARDWARE_nexus_s)
@@ -5173,11 +5600,13 @@
*/
if (1) {
/* blunt-instrument approach */
- if (0) VG_(printf)("QQQQQQQQQQ c01c quick hack actioned (%08lx, %08lx)\n", ARG2, ARG3);
+ if (0) VG_(printf)("QQQQQQQQQQ c01c quick hack actioned"
+ " (%08lx, %08lx)\n", ARG2, ARG3);
POST_MEM_WRITE(ARG3, 256);
} else {
/* be a bit more sophisticated */
- if (0) VG_(printf)("QQQQQQQQQQ c01c quick hack actioned (%08lx, %08lx) (fancy)\n", ARG2, ARG3);
+ if (0) VG_(printf)("QQQQQQQQQQ c01c quick hack actioned"
+ " (%08lx, %08lx) (fancy)\n", ARG2, ARG3);
POST_MEM_WRITE(ARG3, 28);
UInt* word = (UInt*)ARG3;
if (word && word[2] && word[3] < 0x200/*stay sane*/)
@@ -5197,6 +5626,14 @@
}
/* END Nexus S specific ioctls */
+
+# elif defined(ANDROID_HARDWARE_generic) || defined(ANDROID_HARDWARE_emulator)
+
+ /* BEGIN generic/emulator specific ioctls */
+ /* currently none are known */
+ /* END generic/emulator specific ioctls */
+
+
# else /* no ANDROID_HARDWARE_anything defined */
# warning ""
@@ -5205,6 +5642,8 @@
# warning "building for. Currently known values are"
# warning ""
# warning " ANDROID_HARDWARE_nexus_s Samsung Nexus S"
+# warning " ANDROID_HARDWARE_generic Generic device (eg, Pandaboard)"
+# warning " ANDROID_HARDWARE_emulator x86 or arm emulator"
# warning ""
# warning "Make sure you exactly follow the steps in README.android."
# warning ""
@@ -5212,7 +5651,7 @@
# endif /* cases for ANDROID_HARDWARE_blah */
-# endif /* defined(VGPV_arm_linux_android) */
+# endif /* defined(VGPV_*_linux_android) */
/* --- END special IOCTL handlers for specific Android hardware --- */
@@ -5407,6 +5846,7 @@
case VKI_SIOCSIFFLAGS: /* set flags */
case VKI_SIOCSIFMAP: /* Set device parameters */
+ case VKI_SIOCSHWTSTAMP: /* Set hardware time stamping */
case VKI_SIOCSIFTXQLEN: /* Set the tx queue length */
case VKI_SIOCSIFDSTADDR: /* set remote PA address */
case VKI_SIOCSIFBRDADDR: /* set broadcast PA address */
@@ -5504,6 +5944,10 @@
case VKI_SNDRV_TIMER_IOCTL_STOP:
case VKI_SNDRV_TIMER_IOCTL_CONTINUE:
case VKI_SNDRV_TIMER_IOCTL_PAUSE:
+
+ /* SCSI no operand */
+ case VKI_SCSI_IOCTL_DOORLOCK:
+ case VKI_SCSI_IOCTL_DOORUNLOCK:
break;
/* Real Time Clock (/dev/rtc) ioctls */
@@ -5570,6 +6014,14 @@
POST_MEM_WRITE(ARG3, VKI_SIZEOF_STRUCT_HD_DRIVEID );
break;
+ /* SCSI */
+ case VKI_SCSI_IOCTL_GET_IDLUN: /* 0x5382 */
+ POST_MEM_WRITE(ARG3, sizeof(struct vki_scsi_idlun));
+ break;
+ case VKI_SCSI_IOCTL_GET_BUS_NUMBER: /* 0x5386 */
+ POST_MEM_WRITE(ARG3, sizeof(int));
+ break;
+
/* CD ROM stuff (??) */
case VKI_CDROMSUBCHNL:
POST_MEM_WRITE(ARG3, sizeof(struct vki_cdrom_subchnl));
@@ -5603,6 +6055,8 @@
case VKI_CDROM_DRIVE_STATUS: /* 0x5326 */
case VKI_CDROM_CLEAR_OPTIONS: /* 0x5321 */
break;
+ case VKI_CDROM_GET_CAPABILITY: /* 0x5331 */
+ break;
case VKI_FIGETBSZ:
POST_MEM_WRITE(ARG3, sizeof(unsigned long));
@@ -5911,6 +6365,17 @@
case VKI_I2C_FUNCS:
POST_MEM_WRITE( ARG3, sizeof(unsigned long) );
break;
+ case VKI_I2C_RDWR:
+ if ( ARG3 ) {
+ struct vki_i2c_rdwr_ioctl_data *vkui = (struct vki_i2c_rdwr_ioctl_data *)ARG3;
+ UInt i;
+ for (i=0; i < vkui->nmsgs; i++) {
+ struct vki_i2c_msg *msg = vkui->msgs + i;
+ if (msg->flags & VKI_I2C_M_RD)
+ POST_MEM_WRITE((Addr)msg->buf, msg->len);
+ }
+ }
+ break;
/* Wireless extensions ioctls */
case VKI_SIOCSIWCOMMIT:
@@ -5997,7 +6462,7 @@
}
break;
-# if defined(VGPV_arm_linux_android)
+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
/* ashmem */
case VKI_ASHMEM_GET_SIZE:
case VKI_ASHMEM_SET_SIZE:
@@ -6038,7 +6503,26 @@
POST_FIELD_WRITE(bv->protocol_version);
}
break;
-# endif /* defined(VGPV_arm_linux_android) */
+# endif /* defined(VGPV_*_linux_android) */
+
+ case VKI_HCIINQUIRY:
+ if (ARG3) {
+ struct vki_hci_inquiry_req* ir = (struct vki_hci_inquiry_req*)ARG3;
+ POST_MEM_WRITE((Addr)ARG3 + sizeof(struct vki_hci_inquiry_req),
+ ir->num_rsp * sizeof(struct vki_inquiry_info));
+ }
+ break;
+
+ /* KVM ioctls that only write the system call return value */
+ case VKI_KVM_GET_API_VERSION:
+ case VKI_KVM_CREATE_VM:
+ case VKI_KVM_CHECK_EXTENSION:
+ case VKI_KVM_GET_VCPU_MMAP_SIZE:
+ case VKI_KVM_S390_ENABLE_SIE:
+ case VKI_KVM_CREATE_VCPU:
+ case VKI_KVM_RUN:
+ case VKI_KVM_S390_INITIAL_RESET:
+ break;
default:
/* EVIOC* are variable length and return size written on success */
diff --git a/main/coregrind/m_syswrap/syswrap-main.c b/main/coregrind/m_syswrap/syswrap-main.c
index 991e009..f696f51 100644
--- a/main/coregrind/m_syswrap/syswrap-main.c
+++ b/main/coregrind/m_syswrap/syswrap-main.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -68,6 +68,7 @@
ppc32 r0 r3 r4 r5 r6 r7 r8 n/a n/a r3+CR0.SO (== ARG1)
ppc64 r0 r3 r4 r5 r6 r7 r8 n/a n/a r3+CR0.SO (== ARG1)
arm r7 r0 r1 r2 r3 r4 r5 n/a n/a r0 (== ARG1)
+ mips v0 a0 a1 a2 a3 stack stack n/a n/a v0 (== NUM)
On s390x the svc instruction is used for system calls. The system call
number is encoded in the instruction (8 bit immediate field). Since Linux
@@ -462,6 +463,29 @@
canonical->arg7 = 0;
canonical->arg8 = 0;
+#elif defined(VGP_mips32_linux)
+ VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla;
+ canonical->sysno = gst->guest_r2; // v0
+ if (canonical->sysno != __NR_syscall) {
+ canonical->arg1 = gst->guest_r4; // a0
+ canonical->arg2 = gst->guest_r5; // a1
+ canonical->arg3 = gst->guest_r6; // a2
+ canonical->arg4 = gst->guest_r7; // a3
+ canonical->arg5 = *((UInt*) (gst->guest_r29 + 16)); // 16(guest_SP/sp)
+ canonical->arg6 = *((UInt*) (gst->guest_r29 + 20)); // 20(sp)
+ canonical->arg8 = 0;
+ } else {
+ // Fixme hack handle syscall()
+ canonical->sysno = gst->guest_r4; // a0
+ canonical->arg1 = gst->guest_r5; // a1
+ canonical->arg2 = gst->guest_r6; // a2
+ canonical->arg3 = gst->guest_r7; // a3
+ canonical->arg4 = *((UInt*) (gst->guest_r29 + 16)); // 16(guest_SP/sp)
+ canonical->arg5 = *((UInt*) (gst->guest_r29 + 20)); // 20(guest_SP/sp)
+ canonical->arg6 = *((UInt*) (gst->guest_r29 + 24)); // 24(guest_SP/sp)
+ canonical->arg8 = __NR_syscall;
+ }
+
#elif defined(VGP_x86_darwin)
VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla;
UWord *stack = (UWord *)gst->guest_ESP;
@@ -695,6 +719,27 @@
gst->guest_r6 = canonical->arg5;
gst->guest_r7 = canonical->arg6;
+#elif defined(VGP_mips32_linux)
+ VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla;
+ if (canonical->arg8 != __NR_syscall) {
+ gst->guest_r2 = canonical->sysno;
+ gst->guest_r4 = canonical->arg1;
+ gst->guest_r5 = canonical->arg2;
+ gst->guest_r6 = canonical->arg3;
+ gst->guest_r7 = canonical->arg4;
+ *((UInt*) (gst->guest_r29 + 16)) = canonical->arg5; // 16(guest_GPR29/sp)
+ *((UInt*) (gst->guest_r29 + 20)) = canonical->arg6; // 20(sp)
+ } else {
+ canonical->arg8 = 0;
+ gst->guest_r2 = __NR_syscall;
+ gst->guest_r4 = canonical->sysno;
+ gst->guest_r5 = canonical->arg1;
+ gst->guest_r6 = canonical->arg2;
+ gst->guest_r7 = canonical->arg3;
+ *((UInt*) (gst->guest_r29 + 16)) = canonical->arg4; // 16(guest_GPR29/sp)
+ *((UInt*) (gst->guest_r29 + 20)) = canonical->arg5; // 20(sp)
+ *((UInt*) (gst->guest_r29 + 24)) = canonical->arg6; // 24(sp)
+ }
#else
# error "putSyscallArgsIntoGuestState: unknown arch"
#endif
@@ -733,6 +778,14 @@
canonical->sres = VG_(mk_SysRes_arm_linux)( gst->guest_R0 );
canonical->what = SsComplete;
+# elif defined(VGP_mips32_linux)
+ VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla;
+ UInt v0 = gst->guest_r2; // v0
+ UInt v1 = gst->guest_r3; // v1
+ UInt a3 = gst->guest_r7; // a3
+ canonical->sres = VG_(mk_SysRes_mips32_linux)( v0, v1, a3 );
+ canonical->what = SsComplete;
+
# elif defined(VGP_x86_darwin)
/* duplicates logic in m_signals.VG_UCONTEXT_SYSCALL_SYSRES */
VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla;
@@ -965,6 +1018,24 @@
gst->guest_r2 = sr_Res(canonical->sres);
}
+# elif defined(VGP_mips32_linux)
+ VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla;
+ vg_assert(canonical->what == SsComplete);
+ if (sr_isError(canonical->sres)) {
+ gst->guest_r2 = (Int)sr_Err(canonical->sres);
+ gst->guest_r7 = (Int)sr_Err(canonical->sres);
+ } else {
+ gst->guest_r2 = sr_Res(canonical->sres);
+ gst->guest_r3 = sr_ResEx(canonical->sres);
+ gst->guest_r7 = (Int)sr_Err(canonical->sres);
+ }
+ VG_TRACK( post_reg_write, Vg_CoreSysCall, tid,
+ OFFSET_mips32_r2, sizeof(UWord) );
+ VG_TRACK( post_reg_write, Vg_CoreSysCall, tid,
+ OFFSET_mips32_r3, sizeof(UWord) );
+ VG_TRACK( post_reg_write, Vg_CoreSysCall, tid,
+ OFFSET_mips32_r7, sizeof(UWord) );
+
# else
# error "putSyscallStatusIntoGuestState: unknown arch"
# endif
@@ -1033,6 +1104,17 @@
layout->uu_arg7 = -1; /* impossible value */
layout->uu_arg8 = -1; /* impossible value */
+#elif defined(VGP_mips32_linux)
+ layout->o_sysno = OFFSET_mips32_r2;
+ layout->o_arg1 = OFFSET_mips32_r4;
+ layout->o_arg2 = OFFSET_mips32_r5;
+ layout->o_arg3 = OFFSET_mips32_r6;
+ layout->o_arg4 = OFFSET_mips32_r7;
+ layout->s_arg5 = sizeof(UWord) * 4;
+ layout->s_arg6 = sizeof(UWord) * 5;
+ layout->uu_arg7 = -1; /* impossible value */
+ layout->uu_arg8 = -1; /* impossible value */
+
#elif defined(VGP_x86_darwin)
layout->o_sysno = OFFSET_x86_EAX;
// syscall parameters are on stack in C convention
@@ -1887,11 +1969,45 @@
vg_assert(p[0] == 0x0A);
}
+
+#elif defined(VGP_mips32_linux)
+
+ arch->vex.guest_PC -= 4; // sizeof(mips instr)
+
+ /* Make sure our caller is actually sane, and we're really backing
+ back over a syscall.
+
+ syscall == 00 00 00 0C
+ big endian
+ syscall == 0C 00 00 00
+ */
+ {
+ UChar *p = (UChar *)(arch->vex.guest_PC);
+# if defined (VG_LITTLEENDIAN)
+ if (p[0] != 0x0c || p[1] != 0x00 || p[2] != 0x00 || p[3] != 0x00)
+ VG_(message)(Vg_DebugMsg,
+ "?! restarting over syscall at %#x %02x %02x %02x %02x\n",
+ arch->vex.guest_PC, p[0], p[1], p[2], p[3]);
+
+ vg_assert(p[0] == 0x0c && p[1] == 0x00 && p[2] == 0x00 && p[3] == 0x00);
+# elif defined (VG_BIGENDIAN)
+ if (p[0] != 0x00 || p[1] != 0x00 || p[2] != 0x00 || p[3] != 0x0c)
+ VG_(message)(Vg_DebugMsg,
+ "?! restarting over syscall at %#x %02x %02x %02x %02x\n",
+ arch->vex.guest_PC, p[0], p[1], p[2], p[3]);
+
+ vg_assert(p[0] == 0x00 && p[1] == 0x00 && p[2] == 0x00 && p[3] == 0x0c);
+# else
+# error "Unknown endianness"
+# endif
+ }
+
#else
# error "ML_(fixup_guest_state_to_restart_syscall): unknown plat"
#endif
}
+
/*
Fix up the guest state when a syscall is interrupted by a signal
and so has been forced to return 'sysret'.
@@ -1902,7 +2018,7 @@
1. unblock signals
2. perform syscall
- 3. save result to guest state (EAX, RAX, R3+CR0.SO)
+ 3. save result to guest state (EAX, RAX, R3+CR0.SO, R0, V0)
4. re-block signals
If a signal
diff --git a/main/coregrind/m_syswrap/syswrap-mips32-linux.c b/main/coregrind/m_syswrap/syswrap-mips32-linux.c
new file mode 100644
index 0000000..184a2bf
--- /dev/null
+++ b/main/coregrind/m_syswrap/syswrap-mips32-linux.c
@@ -0,0 +1,1766 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Platform-specific syscalls stuff. syswrap-mips32-linux.c ----*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#if defined(VGP_mips32_linux)
+#include "pub_core_basics.h"
+#include "pub_core_vki.h"
+#include "pub_core_vkiscnums.h"
+#include "pub_core_libcsetjmp.h" // to keep _threadstate.h happy
+#include "pub_core_threadstate.h"
+#include "pub_core_aspacemgr.h"
+#include "pub_core_debuglog.h"
+#include "pub_core_libcbase.h"
+#include "pub_core_libcassert.h"
+#include "pub_core_libcprint.h"
+#include "pub_core_libcproc.h"
+#include "pub_core_libcsignal.h"
+#include "pub_core_options.h"
+#include "pub_core_scheduler.h"
+#include "pub_core_sigframe.h" // For VG_(sigframe_destroy)()
+#include "pub_core_signals.h"
+#include "pub_core_syscall.h"
+#include "pub_core_syswrap.h"
+#include "pub_core_tooliface.h"
+#include "pub_core_stacks.h" // VG_(register_stack)
+#include "pub_core_transtab.h" // VG_(discard_translations)
+#include "priv_types_n_macros.h"
+#include "priv_syswrap-generic.h" /* for decls of generic wrappers */
+#include "priv_syswrap-linux.h" /* for decls of linux-ish wrappers */
+#include "priv_syswrap-main.h"
+
+#include "pub_core_debuginfo.h" // VG_(di_notify_*)
+#include "pub_core_xarray.h"
+#include "pub_core_clientstate.h" // VG_(brk_base), VG_(brk_limit)
+#include "pub_core_errormgr.h"
+#include "pub_tool_gdbserver.h" // VG_(gdbserver)
+#include "pub_core_libcfile.h"
+#include "pub_core_machine.h" // VG_(get_SP)
+#include "pub_core_mallocfree.h"
+#include "pub_core_stacktrace.h" // For VG_(get_and_pp_StackTrace)()
+#include "pub_core_ume.h"
+
+#include "priv_syswrap-generic.h"
+
+#include "config.h"
+
+#include <errno.h>
+
+/* ---------------------------------------------------------------------
+ clone() handling
+ ------------------------------------------------------------------ */
+/* Call f(arg1), but first switch stacks, using 'stack' as the new
+ stack, and use 'retaddr' as f's return-to address. Also, clear all
+ the integer registers before entering f.*/
+
+__attribute__ ((noreturn))
+void ML_ (call_on_new_stack_0_1) (Addr stack, Addr retaddr,
+ void (*f) (Word), Word arg1);
+// a0 = stack
+// a1 = retaddr
+// a2 = f
+// a3 = arg1
+asm (
+".text\n"
+".globl vgModuleLocal_call_on_new_stack_0_1\n"
+"vgModuleLocal_call_on_new_stack_0_1:\n"
+" move $29, $4\n\t" // stack to %sp
+" move $25, $6\n\t" // f to t9/$25
+" move $4, $7\n\t" // arg1 to $a0
+" li $2, 0\n\t" // zero all GP regs
+" li $3, 0\n\t"
+" li $5, 0\n\t"
+" li $6, 0\n\t"
+" li $7, 0\n\t"
+
+" li $12, 0\n\t"
+" li $13, 0\n\t"
+" li $14, 0\n\t"
+" li $15, 0\n\t"
+" li $16, 0\n\t"
+" li $17, 0\n\t"
+" li $18, 0\n\t"
+" li $19, 0\n\t"
+" li $20, 0\n\t"
+" li $21, 0\n\t"
+" li $22, 0\n\t"
+" li $23, 0\n\t"
+" li $24, 0\n\t"
+" jr $25\n\t" // jump to dst
+" break 0x7\n" // should never get here
+".previous\n"
+);
+
+/*
+ Perform a clone system call. clone is strange because it has
+ fork()-like return-twice semantics, so it needs special
+ handling here.
+ Upon entry, we have:
+ int (fn)(void*) in $a0 0
+ void* child_stack in $a1 4
+ int flags in $a2 8
+ void* arg in $a3 12
+ pid_t* child_tid in stack 16
+ pid_t* parent_tid in stack 20
+ void* tls_ptr in stack 24
+
+ System call requires:
+ int $__NR_clone in $v0
+ int flags in $a0 0
+ void* child_stack in $a1 4
+ pid_t* parent_tid in $a2 8
+ void* tls_ptr in $a3 12
+ pid_t* child_tid in stack 16
+
+ int clone(int (*fn)(void *arg), void *child_stack, int flags, void *arg,
+ void *parent_tidptr, void *tls, void *child_tidptr)
+
+ Returns an Int encoded in the linux-mips way, not a SysRes.
+ */
+#define __NR_CLONE VG_STRINGIFY(__NR_clone)
+#define __NR_EXIT VG_STRINGIFY(__NR_exit)
+
+//extern
+UInt do_syscall_clone_mips_linux (Word (*fn) (void *), //a0 0 32
+ void *stack, //a1 4 36
+ Int flags, //a2 8 40
+ void *arg, //a3 12 44
+ Int * child_tid, //stack 16 48
+ Int * parent_tid, //stack 20 52
+ Int tls); //stack 24 56
+asm (
+".text\n"
+" .globl do_syscall_clone_mips_linux\n"
+" do_syscall_clone_mips_linux:\n"
+" subu $29,$29,32\n\t"
+" sw $31, 0($29)\n\t"
+" sw $2, 4($29)\n\t"
+" sw $3, 8($29)\n\t"
+" sw $30, 12($29)\n\t"
+" sw $28, 28($29)\n\t"
+ /* set up child stack with function and arg */
+ /* syscall arg 2 child_stack is already in a1 */
+" subu $5, $5, 32\n\t" /* make space on stack */
+" sw $4, 0($5)\n\t" /* fn */
+" sw $7, 4($5)\n\t" /* fn arg */
+" sw $6, 8($5)\n\t"
+ /* get other args to clone */
+
+" move $4, $a2\n\t" /* a0 = flags */
+" lw $6, 52($29)\n\t" /* a2 = parent_tid */
+" lw $7, 48($29)\n\t" /* a3 = child_tid */
+" sw $7, 16($29)\n\t" /* 16(sp) = child_tid */
+" lw $7, 56($29)\n\t" /* a3 = tls_ptr */
+ /* do the system call */
+
+" li $2, " __NR_CLONE "\n\t" /* __NR_clone */
+" syscall\n\t"
+" nop\n\t"
+
+" bnez $7, .Lerror\n\t"
+" nop\n\t"
+" beqz $2, .Lstart\n\t"
+" nop\n\t"
+
+" lw $31, 0($sp)\n\t"
+" nop\n\t"
+" lw $30, 12($sp)\n\t"
+" nop\n\t"
+" addu $29,$29,32\n\t" /* free stack */
+" nop\n\t"
+" jr $31\n\t"
+" nop\n\t"
+
+".Lerror:\n\t"
+" li $31, 5\n\t"
+" jr $31\n\t"
+" nop\n\t"
+
+".Lstart:\n\t"
+" lw $4, 4($29)\n\t"
+" nop\n\t"
+" lw $25, 0($29)\n\t"
+" nop\n\t"
+" jalr $25\n\t"
+" nop\n\t"
+
+" move $4, $2\n\t" /* retval from fn is in $v0 */
+" li $2, " __NR_EXIT "\n\t" /* NR_exit */
+" syscall\n\t"
+" nop\n\t"
+" .previous\n"
+);
+
+#undef __NR_CLONE
+#undef __NR_EXIT
+
+// forward declarations
+
+static void setup_child (ThreadArchState *, ThreadArchState *);
+static SysRes sys_set_tls (ThreadId tid, Addr tlsptr);
+/*
+ When a client clones, we need to keep track of the new thread. This means:
+ 1. allocate a ThreadId+ThreadState+stack for the the thread
+ 2. initialize the thread's new VCPU state
+ 3. create the thread using the same args as the client requested,
+ but using the scheduler entrypoint for IP, and a separate stack
+ for SP.
+ */
+
+static SysRes do_clone (ThreadId ptid,
+ UInt flags, Addr sp,
+ Int * parent_tidptr,
+ Int * child_tidptr,
+ Addr child_tls)
+{
+ const Bool debug = False;
+ ThreadId ctid = VG_ (alloc_ThreadState) ();
+ ThreadState * ptst = VG_ (get_ThreadState) (ptid);
+ ThreadState * ctst = VG_ (get_ThreadState) (ctid);
+ UInt ret = 0;
+ UWord * stack;
+ NSegment const *seg;
+ SysRes res;
+ vki_sigset_t blockall, savedmask;
+
+ VG_ (sigfillset) (&blockall);
+ vg_assert (VG_ (is_running_thread) (ptid));
+ vg_assert (VG_ (is_valid_tid) (ctid));
+ stack = (UWord *) ML_ (allocstack) (ctid);
+ if (stack == NULL) {
+ res = VG_ (mk_SysRes_Error) (VKI_ENOMEM);
+ goto out;
+ }
+ setup_child (&ctst->arch, &ptst->arch);
+
+ /* on MIPS we need to set V0 and A3 to zero */
+ ctst->arch.vex.guest_r2 = 0;
+ ctst->arch.vex.guest_r7 = 0;
+ if (sp != 0)
+ ctst->arch.vex.guest_r29 = sp;
+
+ ctst->os_state.parent = ptid;
+ ctst->sig_mask = ptst->sig_mask;
+ ctst->tmp_sig_mask = ptst->sig_mask;
+
+ /* Start the child with its threadgroup being the same as the
+ parent's. This is so that any exit_group calls that happen
+ after the child is created but before it sets its
+ os_state.threadgroup field for real (in thread_wrapper in
+ syswrap-linux.c), really kill the new thread. a.k.a this avoids
+ a race condition in which the thread is unkillable (via
+ exit_group) because its threadgroup is not set. The race window
+ is probably only a few hundred or a few thousand cycles long.
+ See #226116. */
+
+ ctst->os_state.threadgroup = ptst->os_state.threadgroup;
+ seg = VG_ (am_find_nsegment) ((Addr) sp);
+
+ if (seg && seg->kind != SkResvn) {
+ ctst->client_stack_highest_word = (Addr) VG_PGROUNDUP (sp);
+ ctst->client_stack_szB = ctst->client_stack_highest_word - seg->start;
+ VG_ (register_stack) (seg->start, ctst->client_stack_highest_word);
+ if (debug)
+ VG_ (printf) ("tid %d: guessed client stack range %#lx-%#lx\n",
+
+ ctid, seg->start, VG_PGROUNDUP (sp));
+ } else {
+ VG_ (message) (Vg_UserMsg,
+ "!? New thread %d starts with sp+%#lx) unmapped\n",
+ ctid, sp);
+ ctst->client_stack_szB = 0;
+ }
+
+ VG_TRACK (pre_thread_ll_create, ptid, ctid);
+ if (flags & VKI_CLONE_SETTLS) {
+ if (debug)
+ VG_(printf)("clone child has SETTLS: tls at %#lx\n", child_tls);
+ ctst->arch.vex.guest_r27 = child_tls;
+ res = sys_set_tls(ctid, child_tls);
+ if (sr_isError(res))
+ goto out;
+ ctst->arch.vex.guest_r27 = child_tls;
+ }
+
+ flags &= ~VKI_CLONE_SETTLS;
+ VG_ (sigprocmask) (VKI_SIG_SETMASK, &blockall, &savedmask);
+ /* Create the new thread */
+ ret = do_syscall_clone_mips_linux (ML_ (start_thread_NORETURN),
+ stack, flags, &VG_ (threads)[ctid],
+ child_tidptr, parent_tidptr,
+ 0 /*child_tls*/);
+
+ /* High half word64 is syscall return value. Low half is
+ the entire CR, from which we need to extract CR0.SO. */
+ if (debug)
+ VG_(printf)("ret: 0x%x\n", ret);
+
+ res = VG_ (mk_SysRes_mips32_linux) (/*val */ ret, 0, /*errflag */ 0);
+
+ VG_ (sigprocmask) (VKI_SIG_SETMASK, &savedmask, NULL);
+
+ out:
+ if (sr_isError (res)) {
+ VG_(cleanup_thread) (&ctst->arch);
+ ctst->status = VgTs_Empty;
+ VG_TRACK (pre_thread_ll_exit, ctid);
+ }
+ ptst->arch.vex.guest_r2 = 0;
+
+ return res;
+}
+
+/* ---------------------------------------------------------------------
+ More thread stuff
+ ------------------------------------------------------------------ */
+
+// MIPS doesn't have any architecture specific thread stuff that
+// needs to be cleaned up da li ????!!!!???
+void
+VG_ (cleanup_thread) (ThreadArchState * arch) { }
+
+void
+setup_child ( /*OUT*/ ThreadArchState * child,
+ /*IN*/ ThreadArchState * parent)
+{
+ /* We inherit our parent's guest state. */
+ child->vex = parent->vex;
+ child->vex_shadow1 = parent->vex_shadow1;
+ child->vex_shadow2 = parent->vex_shadow2;
+}
+
+SysRes sys_set_tls ( ThreadId tid, Addr tlsptr )
+{
+ VG_(threads)[tid].arch.vex.guest_ULR = tlsptr;
+ return VG_(mk_SysRes_Success)( 0 );
+}
+
+/* ---------------------------------------------------------------------
+ PRE/POST wrappers for mips/Linux-specific syscalls
+ ------------------------------------------------------------------ */
+#define PRE(name) DEFN_PRE_TEMPLATE(mips_linux, name)
+#define POST(name) DEFN_POST_TEMPLATE(mips_linux, name)
+
+/* Add prototypes for the wrappers declared here, so that gcc doesn't
+ harass us for not having prototypes. Really this is a kludge --
+ the right thing to do is to make these wrappers 'static' since they
+ aren't visible outside this file, but that requires even more macro
+ magic. */
+//DECL_TEMPLATE (mips_linux, sys_syscall);
+DECL_TEMPLATE (mips_linux, sys_socketcall);
+DECL_TEMPLATE (mips_linux, sys_socket);
+DECL_TEMPLATE (mips_linux, sys_setsockopt);
+DECL_TEMPLATE (mips_linux, sys_getsockopt);
+DECL_TEMPLATE (mips_linux, sys_connect);
+DECL_TEMPLATE (mips_linux, sys_accept);
+DECL_TEMPLATE (mips_linux, sys_sendto);
+DECL_TEMPLATE (mips_linux, sys_recvfrom);
+DECL_TEMPLATE (mips_linux, sys_ipc);
+DECL_TEMPLATE (mips_linux, sys_semget);
+DECL_TEMPLATE (mips_linux, sys_semop);
+DECL_TEMPLATE (mips_linux, sys_semctl);
+DECL_TEMPLATE (mips_linux, sys_semtimedop);
+DECL_TEMPLATE (mips_linux, sys_shmget);
+DECL_TEMPLATE (mips_linux, sys_shmdt);
+DECL_TEMPLATE (mips_linux, sys_shmctl);
+DECL_TEMPLATE (mips_linux, sys_sendmsg);
+DECL_TEMPLATE (mips_linux, sys_recvmsg);
+DECL_TEMPLATE (mips_linux, sys_msgget);
+DECL_TEMPLATE (mips_linux, sys_msgrcv);
+DECL_TEMPLATE (mips_linux, sys_msgsnd);
+DECL_TEMPLATE (mips_linux, sys_msgctl);
+DECL_TEMPLATE (mips_linux, sys_shutdown);
+DECL_TEMPLATE (mips_linux, sys_bind);
+DECL_TEMPLATE (mips_linux, sys_listen);
+DECL_TEMPLATE (mips_linux, sys_getsockname);
+DECL_TEMPLATE (mips_linux, sys_getpeername);
+DECL_TEMPLATE (mips_linux, sys_socketpair);
+DECL_TEMPLATE (mips_linux, sys_send);
+DECL_TEMPLATE (mips_linux, sys_recv);
+DECL_TEMPLATE (mips_linux, sys_mmap);
+DECL_TEMPLATE (mips_linux, sys_mmap2);
+DECL_TEMPLATE (mips_linux, sys_stat64);
+DECL_TEMPLATE (mips_linux, sys_lstat64);
+DECL_TEMPLATE (mips_linux, sys_fstatat64);
+DECL_TEMPLATE (mips_linux, sys_fstat64);
+DECL_TEMPLATE (mips_linux, sys_clone);
+DECL_TEMPLATE (mips_linux, sys_sigreturn);
+DECL_TEMPLATE (mips_linux, sys_rt_sigreturn);
+DECL_TEMPLATE (mips_linux, sys_cacheflush);
+DECL_TEMPLATE (mips_linux, sys_set_thread_area);
+DECL_TEMPLATE (mips_linux, sys_pipe);
+
+PRE (sys_socketcall)
+{
+# define ARG2_0 (((UWord*)ARG2)[0])
+# define ARG2_1 (((UWord*)ARG2)[1])
+# define ARG2_2 (((UWord*)ARG2)[2])
+# define ARG2_3 (((UWord*)ARG2)[3])
+# define ARG2_4 (((UWord*)ARG2)[4])
+# define ARG2_5 (((UWord*)ARG2)[5])
+ *flags |= SfMayBlock;
+ PRINT ("sys_socketcall ( %ld, %#lx )", ARG1, ARG2);
+ PRE_REG_READ2 (long, "socketcall", int, call, unsigned long *, args);
+ switch (ARG1 /* request */ )
+ {
+ case VKI_SYS_SOCKETPAIR:
+ /* int socketpair(int d, int type, int protocol, int sv[2]); */
+ PRE_MEM_READ ("socketcall.socketpair(args)", ARG2,
+ 4 * sizeof (Addr));
+ ML_ (generic_PRE_sys_socketpair) (tid, ARG2_0, ARG2_1, ARG2_2, ARG2_3);
+ break;
+ case VKI_SYS_SOCKET:
+ /* int socket(int domain, int type, int protocol); */
+ PRE_MEM_READ ("socketcall.socket(args)", ARG2, 3 * sizeof (Addr));
+ break;
+ case VKI_SYS_BIND:
+ /* int bind(int sockfd, struct sockaddr *my_addr,
+ int addrlen); */
+ PRE_MEM_READ ("socketcall.bind(args)", ARG2, 3 * sizeof (Addr));
+ ML_ (generic_PRE_sys_bind) (tid, ARG2_0, ARG2_1, ARG2_2);
+ break;
+ case VKI_SYS_LISTEN:
+ /* int listen(int s, int backlog); */
+ PRE_MEM_READ ("socketcall.listen(args)", ARG2, 2 * sizeof (Addr));
+ break;
+ case VKI_SYS_ACCEPT:
+ {
+ /* int accept(int s, struct sockaddr *addr, int *addrlen); */
+ PRE_MEM_READ ("socketcall.accept(args)", ARG2, 3 * sizeof (Addr));
+ ML_ (generic_PRE_sys_accept) (tid, ARG2_0, ARG2_1, ARG2_2);
+ break;
+ }
+ case VKI_SYS_SENDTO:
+ /* int sendto(int s, const void *msg, int len,
+ unsigned int flags,
+ const struct sockaddr *to, int tolen); */
+ PRE_MEM_READ ("socketcall.sendto(args)", ARG2, 6 * sizeof (Addr));
+ ML_ (generic_PRE_sys_sendto) (tid, ARG2_0, ARG2_1, ARG2_2, ARG2_3,
+ ARG2_4, ARG2_5);
+ break;
+ case VKI_SYS_SEND:
+ /* int send(int s, const void *msg, size_t len, int flags); */
+ PRE_MEM_READ ("socketcall.send(args)", ARG2, 4 * sizeof (Addr));
+ ML_ (generic_PRE_sys_send) (tid, ARG2_0, ARG2_1, ARG2_2);
+ break;
+ case VKI_SYS_RECVFROM:
+ /* int recvfrom(int s, void *buf, int len, unsigned int flags,
+ struct sockaddr *from, int *fromlen); */
+ PRE_MEM_READ ("socketcall.recvfrom(args)", ARG2, 6 * sizeof (Addr));
+ ML_ (generic_PRE_sys_recvfrom) (tid, ARG2_0, ARG2_1, ARG2_2,
+ ARG2_3, ARG2_4, ARG2_5);
+ break;
+ case VKI_SYS_RECV:
+ /* int recv(int s, void *buf, int len, unsigned int flags); */
+ /* man 2 recv says:
+ The recv call is normally used only on a connected socket
+ (see connect(2)) and is identical to recvfrom with a NULL
+ from parameter.
+ */
+ PRE_MEM_READ ("socketcall.recv(args)", ARG2, 4 * sizeof (Addr));
+ ML_ (generic_PRE_sys_recv) (tid, ARG2_0, ARG2_1, ARG2_2);
+ break;
+ case VKI_SYS_CONNECT:
+ /* int connect(int sockfd,
+ struct sockaddr *serv_addr, int addrlen ); */
+ PRE_MEM_READ ("socketcall.connect(args)", ARG2, 3 * sizeof (Addr));
+ ML_ (generic_PRE_sys_connect) (tid, ARG2_0, ARG2_1, ARG2_2);
+ break;
+ case VKI_SYS_SETSOCKOPT:
+ /* int setsockopt(int s, int level, int optname,
+ const void *optval, int optlen); */
+ PRE_MEM_READ ("socketcall.setsockopt(args)", ARG2, 5 * sizeof (Addr));
+ ML_ (generic_PRE_sys_setsockopt) (tid, ARG2_0, ARG2_1, ARG2_2,
+ ARG2_3, ARG2_4);
+ break;
+ case VKI_SYS_GETSOCKOPT:
+ /* int getsockopt(int s, int level, int optname,
+ void *optval, socklen_t *optlen); */
+ PRE_MEM_READ ("socketcall.getsockopt(args)", ARG2, 5 * sizeof (Addr));
+ ML_ (linux_PRE_sys_getsockopt) (tid, ARG2_0, ARG2_1, ARG2_2, ARG2_3, ARG2_4);
+ break;
+ case VKI_SYS_GETSOCKNAME:
+ /* int getsockname(int s, struct sockaddr* name, int* namelen) */
+ PRE_MEM_READ ("socketcall.getsockname(args)", ARG2, 3 * sizeof (Addr));
+ ML_ (generic_PRE_sys_getsockname) (tid, ARG2_0, ARG2_1, ARG2_2);
+ break;
+ case VKI_SYS_GETPEERNAME:
+ /* int getpeername(int s, struct sockaddr* name, int* namelen) */
+ PRE_MEM_READ ("socketcall.getpeername(args)", ARG2, 3 * sizeof (Addr));
+ ML_ (generic_PRE_sys_getpeername) (tid, ARG2_0, ARG2_1, ARG2_2);
+ break;
+ case VKI_SYS_SHUTDOWN:
+ /* int shutdown(int s, int how); */
+ PRE_MEM_READ ("socketcall.shutdown(args)", ARG2, 2 * sizeof (Addr));
+ break;
+ case VKI_SYS_SENDMSG:
+ {
+ /* int sendmsg(int s, const struct msghdr *msg, int flags); */
+ /* this causes warnings, and I don't get why. glibc bug?
+ * (after all it's glibc providing the arguments array)
+ PRE_MEM_READ( "socketcall.sendmsg(args)", ARG2, 3*sizeof(Addr) );
+ */
+ ML_ (generic_PRE_sys_sendmsg) (tid, (UChar *)ARG2_0, (struct vki_msghdr *)ARG2_1);
+ break;
+ }
+ case VKI_SYS_RECVMSG:
+ {
+ /* int recvmsg(int s, struct msghdr *msg, int flags); */
+ /* this causes warnings, and I don't get why. glibc bug?
+ * (after all it's glibc providing the arguments array)
+ PRE_MEM_READ("socketcall.recvmsg(args)", ARG2, 3*sizeof(Addr) );
+ */
+ ML_ (generic_PRE_sys_recvmsg) (tid, (UChar *)ARG2_0,
+ (struct vki_msghdr *)ARG2_1);
+ break;
+ }
+ default:
+ VG_ (message) (Vg_DebugMsg, "Warning: unhandled socketcall 0x%lx", ARG1);
+ SET_STATUS_Failure (VKI_EINVAL);
+ break;
+ }
+# undef ARG2_0
+# undef ARG2_1
+# undef ARG2_2
+# undef ARG2_3
+# undef ARG2_4
+# undef ARG2_5
+}
+
+POST (sys_socketcall)
+{
+# define ARG2_0 (((UWord*)ARG2)[0])
+# define ARG2_1 (((UWord*)ARG2)[1])
+# define ARG2_2 (((UWord*)ARG2)[2])
+# define ARG2_3 (((UWord*)ARG2)[3])
+# define ARG2_4 (((UWord*)ARG2)[4])
+# define ARG2_5 (((UWord*)ARG2)[5])
+ SysRes r;
+ vg_assert (SUCCESS);
+ switch (ARG1 /* request */ )
+ {
+ case VKI_SYS_SOCKETPAIR:
+ r = ML_ (generic_POST_sys_socketpair) ( tid,
+ VG_ (mk_SysRes_Success) (RES),
+ ARG2_0, ARG2_1, ARG2_2, ARG2_3);
+ SET_STATUS_from_SysRes (r);
+ break;
+ case VKI_SYS_SOCKET:
+ r = ML_ (generic_POST_sys_socket) (tid, VG_ (mk_SysRes_Success) (RES));
+ SET_STATUS_from_SysRes (r);
+ break;
+ case VKI_SYS_BIND:
+ /* int bind(int sockfd, struct sockaddr *my_addr, int addrlen); */
+ break;
+ case VKI_SYS_LISTEN:
+ /* int listen(int s, int backlog); */
+ break;
+ case VKI_SYS_ACCEPT:
+ /* int accept(int s, struct sockaddr *addr, int *addrlen); */
+ r = ML_ (generic_POST_sys_accept) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG2_0, ARG2_1, ARG2_2);
+ SET_STATUS_from_SysRes (r);
+ break;
+ case VKI_SYS_SENDTO:
+ break;
+ case VKI_SYS_SEND:
+ break;
+ case VKI_SYS_RECVFROM:
+ ML_ (generic_POST_sys_recvfrom) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG2_0, ARG2_1, ARG2_2, ARG2_3,
+ ARG2_4, ARG2_5);
+ break;
+ case VKI_SYS_RECV:
+ ML_ (generic_POST_sys_recv) (tid, RES, ARG2_0, ARG2_1, ARG2_2);
+ break;
+ case VKI_SYS_CONNECT:
+ break;
+ case VKI_SYS_SETSOCKOPT:
+ break;
+ case VKI_SYS_GETSOCKOPT:
+ ML_ (linux_POST_sys_getsockopt) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG2_0, ARG2_1, ARG2_2,
+ ARG2_3, ARG2_4);
+ break;
+ case VKI_SYS_GETSOCKNAME:
+ ML_ (generic_POST_sys_getsockname) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG2_0, ARG2_1, ARG2_2);
+ break;
+ case VKI_SYS_GETPEERNAME:
+ ML_ (generic_POST_sys_getpeername) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG2_0, ARG2_1, ARG2_2);
+ break;
+ case VKI_SYS_SHUTDOWN:
+ break;
+ case VKI_SYS_SENDMSG:
+ break;
+ case VKI_SYS_RECVMSG:
+ ML_(generic_PRE_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
+ break;
+ default:
+ VG_ (message) (Vg_DebugMsg, "FATAL: unhandled socketcall 0x%lx", ARG1);
+ VG_ (core_panic) ("... bye!\n");
+ break;
+ /*NOTREACHED*/
+ }
+# undef ARG2_0
+# undef ARG2_1
+# undef ARG2_2
+# undef ARG2_3
+# undef ARG2_4
+# undef ARG2_5
+}
+
+PRE (sys_socket)
+{
+ PRINT ("sys_socket ( %ld, %ld, %ld )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "socket", int, domain, int, type, int, protocol);
+}
+
+POST (sys_socket)
+{
+ SysRes r;
+ vg_assert (SUCCESS);
+ r = ML_ (generic_POST_sys_socket) (tid, VG_ (mk_SysRes_Success) (RES));
+ SET_STATUS_from_SysRes (r);
+}
+
+PRE (sys_setsockopt)
+{
+ PRINT ("sys_setsockopt ( %ld, %ld, %ld, %#lx, %ld )", ARG1, ARG2, ARG3,
+ ARG4, ARG5);
+ PRE_REG_READ5 (long, "setsockopt", int, s, int, level, int, optname,
+ const void *, optval, int, optlen);
+ ML_ (generic_PRE_sys_setsockopt) (tid, ARG1, ARG2, ARG3, ARG4, ARG5);
+}
+
+PRE (sys_getsockopt)
+{
+ PRINT ("sys_getsockopt ( %ld, %ld, %ld, %#lx, %#lx )", ARG1, ARG2, ARG3,
+ ARG4, ARG5);
+ PRE_REG_READ5 (long, "getsockopt", int, s, int, level, int, optname,
+ void *, optval, int, *optlen);
+ ML_ (linux_PRE_sys_getsockopt) (tid, ARG1, ARG2, ARG3, ARG4, ARG5);
+}
+
+POST (sys_getsockopt)
+{
+ vg_assert (SUCCESS);
+ ML_ (linux_POST_sys_getsockopt) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG1, ARG2, ARG3, ARG4, ARG5);
+}
+
+PRE(sys_connect)
+{
+ *flags |= SfMayBlock;
+ PRINT("sys_connect ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3);
+ PRE_REG_READ3(long, "connect",
+ int, sockfd, struct sockaddr *, serv_addr, int, addrlen);
+ ML_(generic_PRE_sys_connect)(tid, ARG1,ARG2,ARG3);
+}
+
+PRE (sys_accept)
+{
+ *flags |= SfMayBlock;
+ PRINT ("sys_accept ( %ld, %#lx, %ld )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "accept", int, s, struct sockaddr *, addr, int,
+ *addrlen);
+ ML_ (generic_PRE_sys_accept) (tid, ARG1, ARG2, ARG3);
+}
+
+POST (sys_accept)
+{
+ SysRes r;
+ vg_assert (SUCCESS);
+ r =
+ ML_ (generic_POST_sys_accept) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG1, ARG2, ARG3);
+ SET_STATUS_from_SysRes (r);
+}
+
+PRE (sys_sendto)
+{
+ *flags |= SfMayBlock;
+ PRINT ("sys_sendto ( %ld, %#lx, %ld, %lu, %#lx, %ld )", ARG1, ARG2, ARG3,
+ ARG4, ARG5, ARG6);
+ PRE_REG_READ6 (long, "sendto", int, s, const void *, msg, int, len,
+ unsigned int, flags, const struct sockaddr *, to, int,
+ tolen);
+ ML_ (generic_PRE_sys_sendto) (tid, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6);
+}
+
+PRE (sys_recvfrom)
+{
+ *flags |= SfMayBlock;
+ PRINT ("sys_recvfrom ( %ld, %#lx, %ld, %lu, %#lx, %#lx )", ARG1, ARG2,
+ ARG3, ARG4, ARG5, ARG6);
+ PRE_REG_READ6 (long, "recvfrom", int, s, void *, buf, int, len,
+ unsigned int, flags,
+ struct sockaddr *, from, int *, fromlen);
+ ML_ (generic_PRE_sys_recvfrom) (tid, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6);
+}
+
+POST (sys_recvfrom)
+{
+ vg_assert (SUCCESS);
+ ML_ (generic_POST_sys_recvfrom) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG1, ARG2, ARG3, ARG4, ARG5, ARG6);
+}
+
+PRE(sys_sendmsg)
+{
+ *flags |= SfMayBlock;
+ PRINT("sys_sendmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3);
+ PRE_REG_READ3(long, "sendmsg",
+ int, s, const struct msghdr *, msg, int, flags);
+ ML_(generic_PRE_sys_sendmsg)(tid, "msg", (struct vki_msghdr *)ARG2);
+}
+
+PRE(sys_recvmsg)
+{
+ *flags |= SfMayBlock;
+ PRINT("sys_recvmsg ( %ld, %#lx, %ld )",ARG1,ARG2,ARG3);
+ PRE_REG_READ3(long, "recvmsg", int, s, struct msghdr *, msg, int, flags);
+ ML_(generic_PRE_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2);
+}
+POST(sys_recvmsg)
+{
+ ML_(generic_POST_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2, RES);
+}
+
+PRE (sys_semget)
+{
+ PRINT ("sys_semget ( %ld, %ld, %ld )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "semget", vki_key_t, key, int, nsems, int, semflg);
+}
+
+PRE (sys_semop)
+{
+ *flags |= SfMayBlock;
+ PRINT ("sys_semop ( %ld, %#lx, %lu )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "semop", int, semid, struct sembuf *, sops,
+ unsigned, nsoops);
+ ML_ (generic_PRE_sys_semop) (tid, ARG1, ARG2, ARG3);
+}
+
+PRE (sys_semctl)
+{
+ switch (ARG3 & ~VKI_IPC_64)
+ {
+ case VKI_IPC_INFO:
+ case VKI_SEM_INFO:
+ PRINT ("sys_semctl ( %ld, %ld, %ld, %#lx )", ARG1, ARG2, ARG3, ARG4);
+ PRE_REG_READ4 (long, "semctl",
+ int, semid, int, semnum, int, cmd,
+ struct seminfo *, arg);
+ break;
+ case VKI_IPC_STAT:
+ case VKI_SEM_STAT:
+ case VKI_IPC_SET:
+ PRINT ("sys_semctl ( %ld, %ld, %ld, %#lx )", ARG1, ARG2, ARG3, ARG4);
+ PRE_REG_READ4 (long, "semctl", int, semid, int, semnum, int, cmd,
+ struct semid_ds *, arg);
+ break;
+ case VKI_GETALL:
+ case VKI_SETALL:
+ PRINT ("sys_semctl ( %ld, %ld, %ld, %#lx )", ARG1, ARG2, ARG3, ARG4);
+ PRE_REG_READ4 (long, "semctl", int, semid, int, semnum, int, cmd,
+ unsigned short *, arg);
+ break;
+ default:
+ PRINT ("sys_semctl ( %ld, %ld, %ld )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "semctl", int, semid, int, semnum, int, cmd);
+ break;
+ }
+ ML_ (generic_PRE_sys_semctl) (tid, ARG1, ARG2, ARG3, ARG4);
+}
+
+POST (sys_semctl)
+{
+ ML_ (generic_POST_sys_semctl) (tid, RES, ARG1, ARG2, ARG3, ARG4);
+}
+
+PRE (sys_semtimedop)
+{
+ *flags |= SfMayBlock;
+ PRINT ("sys_semtimedop ( %ld, %#lx, %lu, %#lx )", ARG1, ARG2, ARG3, ARG4);
+ PRE_REG_READ4 (long, "semtimedop", int, semid, struct sembuf *, sops,
+ unsigned, nsoops,
+ struct timespec *, timeout);
+ ML_ (generic_PRE_sys_semtimedop) (tid, ARG1, ARG2, ARG3, ARG4);
+}
+
+PRE (sys_msgget)
+{
+ PRINT ("sys_msgget ( %ld, %ld )", ARG1, ARG2);
+ PRE_REG_READ2 (long, "msgget", vki_key_t, key, int, msgflg);
+}
+
+PRE (sys_msgsnd)
+{
+ PRINT ("sys_msgsnd ( %ld, %#lx, %ld, %ld )", ARG1, ARG2, ARG3, ARG4);
+ PRE_REG_READ4 (long, "msgsnd", int, msqid, struct msgbuf *, msgp,
+ vki_size_t, msgsz, int, msgflg);
+ ML_ (linux_PRE_sys_msgsnd) (tid, ARG1, ARG2, ARG3, ARG4);
+ if ((ARG4 & VKI_IPC_NOWAIT) == 0)
+ *flags |= SfMayBlock;
+}
+
+PRE (sys_msgrcv)
+{
+ PRINT ("sys_msgrcv ( %ld, %#lx, %ld, %ld, %ld )", ARG1, ARG2, ARG3, ARG4,
+ ARG5);
+ PRE_REG_READ5 (long, "msgrcv", int, msqid, struct msgbuf *, msgp,
+ vki_size_t, msgsz, long, msgytp, int, msgflg);
+ ML_ (linux_PRE_sys_msgrcv) (tid, ARG1, ARG2, ARG3, ARG4, ARG5);
+ if ((ARG4 & VKI_IPC_NOWAIT) == 0)
+ *flags |= SfMayBlock;
+}
+
+POST (sys_msgrcv)
+{
+ ML_ (linux_POST_sys_msgrcv) (tid, RES, ARG1, ARG2, ARG3, ARG4, ARG5);
+}
+
+PRE (sys_msgctl)
+{
+ PRINT ("sys_msgctl ( %ld, %ld, %#lx )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "msgctl", int, msqid, int, cmd, struct msqid_ds *, buf);
+ ML_ (linux_PRE_sys_msgctl) (tid, ARG1, ARG2, ARG3);
+}
+
+POST (sys_msgctl)
+{
+ ML_ (linux_POST_sys_msgctl) (tid, RES, ARG1, ARG2, ARG3);
+}
+
+PRE (sys_shmget)
+{
+ PRINT ("sys_shmget ( %ld, %ld, %ld )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "shmget", vki_key_t, key, vki_size_t, size, int,
+ shmflg);
+}
+
+PRE (sys_shmdt)
+{
+ PRINT ("sys_shmdt ( %#lx )", ARG1);
+ PRE_REG_READ1 (long, "shmdt", const void *, shmaddr);
+ if (!ML_ (generic_PRE_sys_shmdt) (tid, ARG1))
+ SET_STATUS_Failure (VKI_EINVAL);
+}
+
+POST (sys_shmdt)
+
+{
+ ML_ (generic_POST_sys_shmdt) (tid, RES, ARG1);
+}
+
+PRE (sys_shmctl)
+{
+ PRINT ("sys_shmctl ( %ld, %ld, %#lx )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "shmctl", int, shmid, int, cmd, struct shmid_ds *, buf);
+ ML_ (generic_PRE_sys_shmctl) (tid, ARG1, ARG2, ARG3);
+}
+
+POST (sys_shmctl)
+{
+ ML_ (generic_POST_sys_shmctl) (tid, RES, ARG1, ARG2, ARG3);
+}
+
+PRE (sys_shutdown)
+{
+ *flags |= SfMayBlock;
+ PRINT ("sys_shutdown ( %ld, %ld )", ARG1, ARG2);
+ PRE_REG_READ2 (int, "shutdown", int, s, int, how);
+}
+
+PRE (sys_bind)
+{
+ PRINT ("sys_bind ( %ld, %#lx, %ld )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "bind", int, sockfd, struct sockaddr *, my_addr,
+ int, addrlen);
+ ML_ (generic_PRE_sys_bind) (tid, ARG1, ARG2, ARG3);
+}
+
+PRE (sys_listen)
+{
+ PRINT ("sys_listen ( %ld, %ld )", ARG1, ARG2);
+ PRE_REG_READ2 (long, "listen", int, s, int, backlog);
+}
+
+PRE (sys_getsockname)
+{
+ PRINT ("sys_getsockname ( %ld, %#lx, %#lx )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "getsockname", int, s, struct sockaddr *, name,
+ int *, namelen);
+ ML_ (generic_PRE_sys_getsockname) (tid, ARG1, ARG2, ARG3);
+}
+
+POST (sys_getsockname)
+{
+ vg_assert (SUCCESS);
+ ML_ (generic_POST_sys_getsockname) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG1, ARG2, ARG3);
+}
+
+PRE (sys_getpeername)
+{
+ PRINT ("sys_getpeername ( %ld, %#lx, %#lx )", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "getpeername", int, s, struct sockaddr *, name,
+ int *, namelen);
+ ML_ (generic_PRE_sys_getpeername) (tid, ARG1, ARG2, ARG3);
+}
+
+POST (sys_getpeername)
+{
+ vg_assert (SUCCESS);
+ ML_ (generic_POST_sys_getpeername) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG1, ARG2, ARG3);
+}
+
+PRE (sys_socketpair)
+{
+ PRINT ("sys_socketpair ( %ld, %ld, %ld, %#lx )", ARG1, ARG2, ARG3, ARG4);
+ PRE_REG_READ4 (long, "socketpair", int, d, int, type, int,
+ protocol, int *, sv);
+ ML_ (generic_PRE_sys_socketpair) (tid, ARG1, ARG2, ARG3, ARG4);
+}
+
+POST (sys_socketpair)
+{
+ vg_assert (SUCCESS);
+ ML_ (generic_POST_sys_socketpair) (tid, VG_ (mk_SysRes_Success) (RES),
+ ARG1, ARG2, ARG3, ARG4);
+}
+
+PRE (sys_send)
+{
+ *flags |= SfMayBlock;
+ PRINT ("sys_send ( %ld, %#lx, %ld, %lu )", ARG1, ARG2, ARG3, ARG4);
+ PRE_REG_READ4 (long, "send", int, s, const void *, msg, int, len,
+ unsigned int, flags);
+ ML_ (generic_PRE_sys_send) (tid, ARG1, ARG2, ARG3);
+}
+
+PRE (sys_recv)
+{
+ *flags |= SfMayBlock;
+ PRINT ("sys_recv ( %ld, %#lx, %ld, %lu )", ARG1, ARG2, ARG3, ARG4);
+ PRE_REG_READ4 (long, "recv", int, s, void *, buf, int, len,
+ unsigned int, flags);
+ ML_ (generic_PRE_sys_recv) (tid, ARG1, ARG2, ARG3);
+}
+
+POST (sys_recv)
+{
+ ML_ (generic_POST_sys_recv) (tid, RES, ARG1, ARG2, ARG3);
+}
+
+PRE (sys_mmap2)
+{
+ SysRes r;
+ // Exactly like old_mmap() except:
+ // - all 6 args are passed in regs, rather than in a memory-block.
+ // - the file offset is specified in pagesize units rather than bytes,
+ // so that it can be used for files bigger than 2^32 bytes.
+ // pagesize or 4K-size units in offset?
+ vg_assert (VKI_PAGE_SIZE == 4096 || VKI_PAGE_SIZE == 4096 * 4
+ || VKI_PAGE_SIZE == 4096 * 16);
+ PRINT ("sys_mmap2 ( %#lx, %llu, %ld, %ld, %ld, %ld )", ARG1, (ULong) ARG2,
+ ARG3, ARG4,
+ ARG5, ARG6);
+ PRE_REG_READ6 (long, "mmap2", unsigned long, start, unsigned long, length,
+ unsigned long, prot, unsigned long, flags,
+ unsigned long, fd, unsigned long, offset);
+ r =
+ ML_ (generic_PRE_sys_mmap) (tid, ARG1, ARG2, ARG3, ARG4, ARG5,
+ VKI_PAGE_SIZE * (Off64T) ARG6);
+ SET_STATUS_from_SysRes (r);
+}
+
+PRE (sys_mmap)
+{
+ SysRes r;
+ //vg_assert(VKI_PAGE_SIZE == 4096);
+ PRINT ("sys_mmap ( %#lx, %llu, %lu, %lu, %lu, %ld )", ARG1, (ULong) ARG2,
+ ARG3, ARG4, ARG5, ARG6);
+ PRE_REG_READ6 (long, "mmap", unsigned long, start, vki_size_t, length,
+ int, prot, int, flags, int, fd, unsigned long, offset);
+ r =
+ ML_ (generic_PRE_sys_mmap) (tid, ARG1, ARG2, ARG3, ARG4, ARG5,
+ (Off64T) ARG6);
+ SET_STATUS_from_SysRes (r);
+}
+
+// XXX: lstat64/fstat64/stat64 are generic, but not necessarily
+// applicable to every architecture -- I think only to 32-bit archs.
+// We're going to need something like linux/core_os32.h for such
+// things, eventually, I think. --njn
+
+PRE (sys_lstat64)
+{
+ PRINT ("sys_lstat64 ( %#lx(%s), %#lx )", ARG1, (char *) ARG1, ARG2);
+ PRE_REG_READ2 (long, "lstat64", char *, file_name, struct stat64 *, buf);
+ PRE_MEM_RASCIIZ ("lstat64(file_name)", ARG1);
+ PRE_MEM_WRITE ("lstat64(buf)", ARG2, sizeof (struct vki_stat64));
+}
+
+POST (sys_lstat64)
+{
+ vg_assert (SUCCESS);
+ if (RES == 0)
+ {
+ POST_MEM_WRITE (ARG2, sizeof (struct vki_stat64));
+ }
+}
+
+PRE (sys_stat64)
+{
+ PRINT ("sys_stat64 ( %#lx(%s), %#lx )", ARG1, (char *) ARG1, ARG2);
+ PRE_REG_READ2 (long, "stat64", char *, file_name, struct stat64 *, buf);
+ PRE_MEM_RASCIIZ ("stat64(file_name)", ARG1);
+ PRE_MEM_WRITE ("stat64(buf)", ARG2, sizeof (struct vki_stat64));
+}
+
+POST (sys_stat64)
+{
+ POST_MEM_WRITE (ARG2, sizeof (struct vki_stat64));
+}
+
+PRE (sys_fstatat64)
+{
+ PRINT ("sys_fstatat64 ( %ld, %#lx(%s), %#lx )", ARG1, ARG2, (char *) ARG2,
+ ARG3);
+ PRE_REG_READ3 (long, "fstatat64", int, dfd, char *, file_name,
+ struct stat64 *, buf);
+ PRE_MEM_RASCIIZ ("fstatat64(file_name)", ARG2);
+ PRE_MEM_WRITE ("fstatat64(buf)", ARG3, sizeof (struct vki_stat64));
+}
+
+POST (sys_fstatat64)
+{
+ POST_MEM_WRITE (ARG3, sizeof (struct vki_stat64));
+}
+
+PRE (sys_fstat64)
+{
+ PRINT ("sys_fstat64 ( %ld, %#lx )", ARG1, ARG2);
+ PRE_REG_READ2 (long, "fstat64", unsigned long, fd, struct stat64 *, buf);
+ PRE_MEM_WRITE ("fstat64(buf)", ARG2, sizeof (struct vki_stat64));
+}
+
+POST (sys_fstat64)
+{
+ POST_MEM_WRITE (ARG2, sizeof (struct vki_stat64));
+}
+
+static Addr
+deref_Addr (ThreadId tid, Addr a, Char * s)
+{
+ Addr * a_p = (Addr *) a;
+ PRE_MEM_READ (s, (Addr) a_p, sizeof (Addr));
+ return *a_p;
+}
+
+PRE (sys_ipc)
+{
+ PRINT ("sys_ipc ( %ld, %ld, %ld, %ld, %#lx, %ld )", ARG1, ARG2, ARG3,
+ ARG4, ARG5, ARG6);
+ // XXX: this is simplistic -- some args are not used in all circumstances.
+ PRE_REG_READ6 (int, "ipc", vki_uint, call, int, first, int, second, int,
+ third, void *, ptr, long, fifth)
+ switch (ARG1 /* call */ )
+ {
+ case VKI_SEMOP:
+ ML_ (generic_PRE_sys_semop) (tid, ARG2, ARG5, ARG3);
+ *flags |= SfMayBlock;
+ break;
+ case VKI_SEMGET:
+ break;
+ case VKI_SEMCTL:
+ {
+ UWord arg = deref_Addr (tid, ARG5, "semctl(arg)");
+ ML_ (generic_PRE_sys_semctl) (tid, ARG2, ARG3, ARG4, arg);
+ break;
+ }
+ case VKI_SEMTIMEDOP:
+ ML_ (generic_PRE_sys_semtimedop) (tid, ARG2, ARG5, ARG3, ARG6);
+ *flags |= SfMayBlock;
+ break;
+ case VKI_MSGSND:
+ ML_ (linux_PRE_sys_msgsnd) (tid, ARG2, ARG5, ARG3, ARG4);
+ if ((ARG4 & VKI_IPC_NOWAIT) == 0)
+ *flags |= SfMayBlock;
+ break;
+ case VKI_MSGRCV:
+ {
+ Addr msgp;
+ Word msgtyp;
+ msgp = deref_Addr (tid,
+ (Addr)(&((struct vki_ipc_kludge *)ARG5)->msgp),
+ "msgrcv(msgp)");
+ msgtyp = deref_Addr (tid,
+ (Addr) (&((struct vki_ipc_kludge *)ARG5)->msgtyp),
+ "msgrcv(msgp)");
+ ML_ (linux_PRE_sys_msgrcv) (tid, ARG2, msgp, ARG3, msgtyp, ARG4);
+ if ((ARG4 & VKI_IPC_NOWAIT) == 0)
+ *flags |= SfMayBlock;
+ break;
+ }
+ case VKI_MSGGET:
+ break;
+ case VKI_MSGCTL:
+ ML_ (linux_PRE_sys_msgctl) (tid, ARG2, ARG3, ARG5);
+ break;
+ case VKI_SHMAT:
+ {
+ PRE_MEM_WRITE ("shmat(raddr)", ARG4, sizeof (Addr));
+ break;
+ }
+ case VKI_SHMDT:
+ if (!ML_ (generic_PRE_sys_shmdt) (tid, ARG5))
+ SET_STATUS_Failure (VKI_EINVAL);
+ break;
+ case VKI_SHMGET:
+ break;
+ case VKI_SHMCTL: /* IPCOP_shmctl */
+ ML_ (generic_PRE_sys_shmctl) (tid, ARG2, ARG3, ARG5);
+ break;
+ default:
+ VG_ (message) (Vg_DebugMsg, "FATAL: unhandled syscall(ipc) %ld\n",
+ ARG1);
+ VG_ (core_panic) ("... bye!\n");
+ break;
+ /*NOTREACHED*/
+ }
+}
+
+POST (sys_ipc)
+{
+ vg_assert (SUCCESS);
+ switch (ARG1 /* call */ )
+ {
+ case VKI_SEMOP:
+ case VKI_SEMGET:
+ break;
+ case VKI_SEMCTL:
+ {
+ UWord arg = deref_Addr (tid, ARG5, "semctl(arg)");
+ ML_ (generic_PRE_sys_semctl) (tid, ARG2, ARG3, ARG4, arg);
+ break;
+ }
+ case VKI_SEMTIMEDOP:
+ case VKI_MSGSND:
+ break;
+ case VKI_MSGRCV:
+ {
+ Addr msgp;
+ Word msgtyp;
+ msgp = deref_Addr (tid, (Addr) (&((struct vki_ipc_kludge *)
+ ARG5)->msgp),
+ "msgrcv(msgp)");
+ msgtyp = deref_Addr (tid,
+ (Addr) (&((struct vki_ipc_kludge *) ARG5)->msgtyp),
+ "msgrcv(msgp)");
+ ML_ (linux_POST_sys_msgrcv)(tid, RES, ARG2, msgp, ARG3, msgtyp, ARG4);
+ break;
+ }
+ case VKI_MSGGET:
+ break;
+ case VKI_MSGCTL:
+ ML_ (linux_POST_sys_msgctl) (tid, RES, ARG2, ARG3, ARG5);
+ break;
+ case VKI_SHMAT:
+ {
+ Addr addr;
+ /* force readability. before the syscall it is
+ * indeed uninitialized, as can be seen in
+ * glibc/sysdeps/unix/sysv/linux/shmat.c */
+ POST_MEM_WRITE (ARG4, sizeof (Addr));
+ addr = deref_Addr (tid, ARG4, "shmat(addr)");
+ ML_ (generic_POST_sys_shmat) (tid, addr, ARG2, ARG5, ARG3);
+ break;
+ }
+ case VKI_SHMDT:
+ ML_ (generic_POST_sys_shmdt) (tid, RES, ARG5);
+ break;
+ case VKI_SHMGET:
+ break;
+ case VKI_SHMCTL:
+ ML_ (generic_POST_sys_shmctl) (tid, RES, ARG2, ARG3, ARG5);
+ break;
+ default:
+ VG_ (message) (Vg_DebugMsg, "FATAL: unhandled syscall(ipc) %ld\n",
+ ARG1);
+ VG_ (core_panic) ("... bye!\n");
+ break;
+ /*NOTREACHED*/
+ }
+}
+
+PRE (sys_clone)
+ {
+ Bool badarg = False;
+ UInt cloneflags;
+ PRINT ("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )", ARG1, ARG2, ARG3,
+ ARG4, ARG5);
+ PRE_REG_READ2 (int, "clone", unsigned long, flags, void *, child_stack);
+ if (ARG1 & VKI_CLONE_PARENT_SETTID)
+ {
+ if (VG_ (tdict).track_pre_reg_read)
+ {
+ PRA3 ("clone", int *, parent_tidptr);
+ }
+ PRE_MEM_WRITE ("clone(parent_tidptr)", ARG3, sizeof (Int));
+ if (!VG_ (am_is_valid_for_client)(ARG3, sizeof (Int), VKI_PROT_WRITE))
+ {
+ badarg = True;
+ }
+ }
+ if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
+ {
+ if (VG_ (tdict).track_pre_reg_read)
+ {
+ PRA5 ("clone", int *, child_tidptr);
+ }
+ PRE_MEM_WRITE ("clone(child_tidptr)", ARG5, sizeof (Int));
+ if (!VG_ (am_is_valid_for_client)(ARG5, sizeof (Int), VKI_PROT_WRITE))
+ {
+ badarg = True;
+ }
+ }
+ if (badarg)
+ {
+ SET_STATUS_Failure (VKI_EFAULT);
+ return;
+ }
+ cloneflags = ARG1;
+ if (!ML_ (client_signal_OK) (ARG1 & VKI_CSIGNAL))
+ {
+ SET_STATUS_Failure (VKI_EINVAL);
+ return;
+ }
+ /* Only look at the flags we really care about */
+ switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS
+ |VKI_CLONE_FILES | VKI_CLONE_VFORK))
+ {
+ case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES:
+ /* thread creation */
+ PRINT ("sys_clone1 ( %#lx, %#lx, %#lx, %#lx, %#lx )",
+ ARG1, ARG2, ARG3, ARG4, ARG5);
+ SET_STATUS_from_SysRes (do_clone (tid,
+ ARG1, /* flags */
+ (Addr) ARG2, /* child SP */
+ (Int *) ARG3, /* parent_tidptr */
+ (Int *) ARG5, /* child_tidptr */
+ (Addr) ARG4)); /* child_tls */
+
+ break;
+ case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */
+ /* FALLTHROUGH - assume vfork == fork */
+ cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM);
+ case 0: /* plain fork */
+ SET_STATUS_from_SysRes (ML_ (do_fork_clone) (tid,
+ cloneflags, /* flags */
+ (Int *) ARG3, /* parent_tidptr */
+ (Int *) ARG5)); /* child_tidptr */
+ break;
+ default:
+ /* should we just ENOSYS? */
+ VG_ (message) (Vg_UserMsg, "Unsupported clone() flags: 0x%lx\n", ARG1);
+ VG_ (message) (Vg_UserMsg, "\n");
+ VG_ (message) (Vg_UserMsg, "The only supported clone() uses are:\n");
+ VG_ (message) (Vg_UserMsg,
+ " - via a threads library (LinuxThreads or NPTL)\n");
+ VG_ (message) (Vg_UserMsg,
+ " - via the implementation of fork or vfork\n");
+ VG_ (unimplemented)("Valgrind does not support general clone().");
+ }
+ if (SUCCESS)
+ {
+ if (ARG1 & VKI_CLONE_PARENT_SETTID)
+ POST_MEM_WRITE (ARG3, sizeof (Int));
+ if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID))
+ POST_MEM_WRITE (ARG5, sizeof (Int));
+ /* Thread creation was successful; let the child have the chance
+ * to run */
+ *flags |= SfYieldAfter;
+ }
+}
+
+PRE (sys_sigreturn)
+{
+ ThreadState * tst;
+ PRINT ("sys_sigreturn ( )");
+ vg_assert (VG_ (is_valid_tid) (tid));
+ vg_assert (tid >= 1 && tid < VG_N_THREADS);
+ vg_assert (VG_ (is_running_thread) (tid));
+ tst = VG_ (get_ThreadState) (tid);
+ VG_ (sigframe_destroy) (tid, False);
+ /* Tell the driver not to update the guest state with the "result",
+ and set a bogus result to keep it happy. */
+ *flags |= SfNoWriteResult;
+ SET_STATUS_Success (0);
+ /* Check to see if any signals arose as a result of this. */
+ *flags |= SfPollAfter;
+}
+
+PRE (sys_rt_sigreturn)
+{
+ PRINT ("rt_sigreturn ( )");
+ vg_assert (VG_ (is_valid_tid) (tid));
+ vg_assert (tid >= 1 && tid < VG_N_THREADS);
+ vg_assert (VG_ (is_running_thread) (tid));
+ /* Restore register state from frame and remove it */
+ VG_ (sigframe_destroy) (tid, True);
+ /* Tell the driver not to update the guest state with the "result",
+ and set a bogus result to keep it happy. */
+ *flags |= SfNoWriteResult;
+ SET_STATUS_Success (0);
+ /* Check to see if any signals arose as a result of this. */
+ *flags |= SfPollAfter;
+}
+
+PRE (sys_set_thread_area)
+{
+ PRINT ("set_thread_area (%lx)", ARG1);
+ PRE_REG_READ1(long, "set_thread_area", unsigned long, addr);
+ SET_STATUS_from_SysRes( sys_set_tls( tid, ARG1 ) );
+}
+
+/* Very much MIPS specific */
+PRE (sys_cacheflush)
+{
+ PRINT ("cacheflush (%lx, %#lx, %#lx)", ARG1, ARG2, ARG3);
+ PRE_REG_READ3 (long, "cacheflush", void *, addrlow, void *, addrhigh, int,
+ flags);
+ VG_ (discard_translations) ((Addr64) ARG1, ((ULong) ARG2) - ((ULong) ARG1) +
+ 1ULL /*paranoia */ , "PRE(sys_cacheflush)");
+ SET_STATUS_Success (0);
+}
+
+PRE(sys_pipe)
+{
+ PRINT("sys_pipe ( %#lx )", ARG1);
+ PRE_REG_READ1(int, "pipe", int *, filedes);
+ PRE_MEM_WRITE( "pipe(filedes)", ARG1, 2*sizeof(int) );
+}
+
+POST(sys_pipe)
+{
+ Int p0, p1;
+ vg_assert(SUCCESS);
+ p0 = RES;
+ p1 = sr_ResEx(status->sres);
+
+ if (!ML_(fd_allowed)(p0, "pipe", tid, True) ||
+ !ML_(fd_allowed)(p1, "pipe", tid, True)) {
+ VG_(close)(p0);
+ VG_(close)(p1);
+ SET_STATUS_Failure( VKI_EMFILE );
+ } else {
+ if (VG_(clo_track_fds)) {
+ ML_(record_fd_open_nameless)(tid, p0);
+ ML_(record_fd_open_nameless)(tid, p1);
+ }
+ }
+}
+
+#undef PRE
+#undef POST
+
+/* ---------------------------------------------------------------------
+ The mips/Linux syscall table
+ ------------------------------------------------------------------ */
+#define PLAX_(sysno, name) WRAPPER_ENTRY_X_(mips_linux, sysno, name)
+#define PLAXY(sysno, name) WRAPPER_ENTRY_XY(mips_linux, sysno, name)
+
+// This table maps from __NR_xxx syscall numbers (from
+// linux/include/asm-mips/unistd.h) to the appropriate PRE/POST sys_foo()
+// wrappers on mips (as per sys_call_table in linux/arch/mips/kernel/entry.S).
+//
+
+// For those syscalls not handled by Valgrind, the annotation indicate its
+// arch/OS combination, eg. */* (generic), */Linux (Linux only), ?/?
+// (unknown).
+
+static SyscallTableEntry syscall_main_table[] = {
+ //PLAXY (__NR_syscall, sys_syscall), // 0
+ GENX_ (__NR_exit, sys_exit), // 1
+ GENX_ (__NR_fork, sys_fork), // 2
+ GENXY (__NR_read, sys_read), // 3
+ GENX_ (__NR_write, sys_write), // 4
+ GENXY (__NR_open, sys_open), // 5
+ GENXY (__NR_close, sys_close), // 6
+ GENXY (__NR_waitpid, sys_waitpid), // 7
+ GENXY (__NR_creat, sys_creat), // 8
+ GENX_ (__NR_link, sys_link), // 9
+ GENX_ (__NR_unlink, sys_unlink), // 10
+ GENX_ (__NR_execve, sys_execve), // 11
+ GENX_ (__NR_chdir, sys_chdir), // 12
+ GENXY (__NR_time, sys_time), // 13
+ GENX_ (__NR_mknod, sys_mknod), // 14
+ GENX_ (__NR_chmod, sys_chmod), // 15
+ GENX_ (__NR_lchown, sys_lchown), // 16
+ LINX_ (__NR_lseek, sys_lseek), // 19
+ GENX_ (__NR_getpid, sys_getpid), // 20
+ LINX_ (__NR_mount, sys_mount), // 21
+ LINX_ (__NR_umount, sys_oldumount), // 22
+ GENX_ (__NR_setuid, sys_setuid), // 23 ## P
+ GENX_ (__NR_getuid, sys_getuid), // 24 ## P
+ //.. // (__NR_stime, sys_stime),
+ //.. PLAXY(__NR_ptrace, sys_ptrace), // 26
+ GENX_ (__NR_alarm, sys_alarm), // 27
+ //.. // (__NR_oldfstat, sys_fstat),
+ GENX_ (__NR_pause, sys_pause), // 29
+ LINX_ (__NR_utime, sys_utime), // 30
+ //.. GENX_(__NR_stty, sys_ni_syscall), // 31
+ //.. GENX_(__NR_gtty, sys_ni_syscall), // 32
+ GENX_ (__NR_access, sys_access), // 33
+ //.. GENX_(__NR_nice, sys_nice), // 34
+ //.. GENX_(__NR_ftime, sys_ni_syscall), // 35
+ //.. GENX_(__NR_sync, sys_sync), // 36
+ GENX_ (__NR_kill, sys_kill), // 37
+ GENX_ (__NR_rename, sys_rename), // 38
+ GENX_ (__NR_mkdir, sys_mkdir), // 39
+ GENX_ (__NR_rmdir, sys_rmdir), // 40
+ GENXY (__NR_dup, sys_dup), // 41
+ PLAXY (__NR_pipe, sys_pipe), // 42
+ GENXY (__NR_times, sys_times), // 43
+ //.. GENX_(__NR_prof, sys_ni_syscall), // 44
+ //..
+ GENX_ (__NR_brk, sys_brk), // 45
+ GENX_ (__NR_setgid, sys_setgid), // 46
+ GENX_ (__NR_getgid, sys_getgid), // 47
+ //.. // (__NR_signal, sys_signal), // 48 */* (ANSI C)
+ GENX_ (__NR_geteuid, sys_geteuid), // 49
+ GENX_ (__NR_getegid, sys_getegid), // 50
+ //.. GENX_(__NR_acct, sys_acct), // 51
+ LINX_ (__NR_umount2, sys_umount), // 52
+ //.. GENX_(__NR_lock, sys_ni_syscall), // 53
+ LINXY (__NR_ioctl, sys_ioctl), // 54
+ LINXY (__NR_fcntl, sys_fcntl), // 55
+ //.. GENX_(__NR_mpx, sys_ni_syscall), // 56
+ GENX_ (__NR_setpgid, sys_setpgid), // 57
+ //.. GENX_(__NR_ulimit, sys_ni_syscall), // 58
+ //.. // (__NR_oldolduname, sys_olduname), // 59
+ GENX_ (__NR_umask, sys_umask), // 60
+ GENX_ (__NR_chroot, sys_chroot), // 61
+ //.. // (__NR_ustat, sys_ustat) // 62 SVr4 -- deprecated
+ GENXY (__NR_dup2, sys_dup2), // 63
+ GENX_ (__NR_getppid, sys_getppid), // 64
+ GENX_ (__NR_getpgrp, sys_getpgrp), // 65
+ GENX_ (__NR_setsid, sys_setsid), // 66
+ // PLAXY(__NR_sigaction, sys_sigaction), // 67
+ //.. // (__NR_sgetmask, sys_sgetmask), // 68 */* (ANSI C)
+ //.. // (__NR_ssetmask, sys_ssetmask), // 69 */* (ANSI C)
+ //..
+ GENX_ (__NR_setreuid, sys_setreuid), // 70
+ GENX_ (__NR_setregid, sys_setregid), // 71
+ // PLAX_(__NR_sigsuspend, sys_sigsuspend), // 72
+ LINXY (__NR_sigpending, sys_sigpending), // 73
+ //.. // (__NR_sethostname, sys_sethostname), // 74 */*
+ //..
+ GENX_ (__NR_setrlimit, sys_setrlimit), // 75
+ //.. GENXY(__NR_getrlimit, sys_old_getrlimit), // 76
+ GENXY (__NR_getrusage, sys_getrusage), // 77
+ GENXY (__NR_gettimeofday, sys_gettimeofday), // 78
+ //.. GENX_(__NR_settimeofday, sys_settimeofday), // 79
+ //..
+ GENXY (__NR_getgroups, sys_getgroups), // 80
+ GENX_ (__NR_setgroups, sys_setgroups), // 81
+ //.. PLAX_(__NR_select, old_select), // 82
+ GENX_ (__NR_symlink, sys_symlink), // 83
+ //.. // (__NR_oldlstat, sys_lstat), // 84 -- obsolete
+ //..
+ GENX_ (__NR_readlink, sys_readlink), // 85
+ //.. // (__NR_uselib, sys_uselib), // 86 */Linux
+ //.. // (__NR_swapon, sys_swapon), // 87 */Linux
+ //.. // (__NR_reboot, sys_reboot), // 88 */Linux
+ //.. // (__NR_readdir, old_readdir), // 89 -- superseded
+ PLAX_ (__NR_mmap, sys_mmap), // 90
+ GENXY (__NR_munmap, sys_munmap), // 91
+ GENX_ (__NR_truncate, sys_truncate), // 92
+ GENX_ (__NR_ftruncate, sys_ftruncate), // 93
+ GENX_ (__NR_fchmod, sys_fchmod), // 94
+ GENX_ (__NR_fchown, sys_fchown), // 95
+ GENX_ (__NR_getpriority, sys_getpriority), // 96
+ GENX_ (__NR_setpriority, sys_setpriority), // 97
+ //.. GENX_(__NR_profil, sys_ni_syscall), // 98
+ GENXY (__NR_statfs, sys_statfs), // 99
+ //..
+ GENXY (__NR_fstatfs, sys_fstatfs), // 100
+ //.. LINX_(__NR_ioperm, sys_ioperm), // 101
+ PLAXY (__NR_socketcall, sys_socketcall), // 102
+ LINXY (__NR_syslog, sys_syslog), // 103
+ GENXY (__NR_setitimer, sys_setitimer), // 104
+ //..
+ //.. GENXY(__NR_getitimer, sys_getitimer), // 105
+ GENXY (__NR_stat, sys_newstat), // 106
+ GENXY (__NR_lstat, sys_newlstat), // 107
+ GENXY (__NR_fstat, sys_newfstat), // 108
+ //.. // (__NR_olduname, sys_uname), // 109 -- obsolete
+ //..
+ //.. GENX_(__NR_iopl, sys_iopl), // 110
+ //.. LINX_(__NR_vhangup, sys_vhangup), // 111
+ //.. GENX_(__NR_idle, sys_ni_syscall), // 112
+ //.. // (__NR_vm86old, sys_vm86old), // 113 x86/Linux-only
+ GENXY (__NR_wait4, sys_wait4), // 114
+ //..
+ //.. // (__NR_swapoff, sys_swapoff), // 115 */Linux
+ LINXY (__NR_sysinfo, sys_sysinfo), // 116
+ PLAXY (__NR_ipc, sys_ipc), // 117
+ GENX_ (__NR_fsync, sys_fsync), // 118
+ PLAX_ (__NR_sigreturn, sys_sigreturn), // 119 ?/Linux
+ //..
+ PLAX_ (__NR_clone, sys_clone), // 120
+ //.. // (__NR_setdomainname, sys_setdomainname), // 121 */*(?)
+ GENXY (__NR_uname, sys_newuname), // 122
+ //.. PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123
+ //.. LINXY(__NR_adjtimex, sys_adjtimex), // 124
+ //..
+ GENXY (__NR_mprotect, sys_mprotect), // 125
+ LINXY (__NR_sigprocmask, sys_sigprocmask), // 126
+ //.. // Nb: create_module() was removed 2.4-->2.6
+ //.. GENX_(__NR_create_module, sys_ni_syscall), // 127
+ //.. GENX_(__NR_init_module, sys_init_module), // 128
+ //.. // (__NR_delete_module, sys_delete_module), // 129 (*/Linux)?
+ //..
+ //.. // Nb: get_kernel_syms() was removed 2.4-->2.6
+ //.. GENX_(__NR_get_kernel_syms, sys_ni_syscall), // 130
+ //.. LINX_(__NR_quotactl, sys_quotactl), // 131
+ GENX_ (__NR_getpgid, sys_getpgid), // 132
+ GENX_ (__NR_fchdir, sys_fchdir), // 133
+ //.. // (__NR_bdflush, sys_bdflush), // 134 */Linux
+ //..
+ //.. // (__NR_sysfs, sys_sysfs), // 135 SVr4
+ LINX_ (__NR_personality, sys_personality), // 136
+ //.. GENX_(__NR_afs_syscall, sys_ni_syscall), // 137
+ LINX_ (__NR_setfsuid, sys_setfsuid), // 138
+ LINX_ (__NR_setfsgid, sys_setfsgid), // 139
+ LINXY (__NR__llseek, sys_llseek), // 140
+ GENXY (__NR_getdents, sys_getdents), // 141
+ GENX_ (__NR__newselect, sys_select), // 142
+ GENX_ (__NR_flock, sys_flock), // 143
+ GENX_ (__NR_msync, sys_msync), // 144
+ //..
+ GENXY (__NR_readv, sys_readv), // 145
+ GENX_ (__NR_writev, sys_writev), // 146
+ PLAX_ (__NR_cacheflush, sys_cacheflush), // 147
+ GENX_ (__NR_getsid, sys_getsid), // 151
+ GENX_ (__NR_fdatasync, sys_fdatasync), // 152
+ LINXY (__NR__sysctl, sys_sysctl), // 153
+ //..
+ GENX_ (__NR_mlock, sys_mlock), // 154
+ GENX_ (__NR_munlock, sys_munlock), // 155
+ GENX_ (__NR_mlockall, sys_mlockall), // 156
+ LINX_ (__NR_munlockall, sys_munlockall), // 157
+ //.. LINXY(__NR_sched_setparam, sys_sched_setparam), // 158
+ //..
+ LINXY (__NR_sched_getparam, sys_sched_getparam), // 159
+ LINX_ (__NR_sched_setscheduler, sys_sched_setscheduler), // 160
+ LINX_ (__NR_sched_getscheduler, sys_sched_getscheduler), // 161
+ LINX_ (__NR_sched_yield, sys_sched_yield), // 162
+ LINX_ (__NR_sched_get_priority_max, sys_sched_get_priority_max), // 163
+ LINX_ (__NR_sched_get_priority_min, sys_sched_get_priority_min), // 164
+ //.. //LINX?(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 165 */*
+ GENXY (__NR_nanosleep, sys_nanosleep), // 166
+ GENX_ (__NR_mremap, sys_mremap), // 167
+ PLAXY (__NR_accept, sys_accept), // 168
+ PLAX_ (__NR_bind, sys_bind), // 169
+ PLAX_ (__NR_connect, sys_connect), // 170
+ PLAXY (__NR_getpeername, sys_getpeername), // 171
+ PLAXY (__NR_getsockname, sys_getsockname), // 172
+ PLAXY (__NR_getsockopt, sys_getsockopt), // 173
+ PLAX_ (__NR_listen, sys_listen), // 174
+ PLAXY (__NR_recv, sys_recv), // 175
+ PLAXY (__NR_recvfrom, sys_recvfrom), // 176
+ PLAXY (__NR_recvmsg, sys_recvmsg), // 177
+ PLAX_ (__NR_send, sys_send), // 178
+ PLAX_ (__NR_sendmsg, sys_sendmsg), // 179
+ PLAX_ (__NR_sendto, sys_sendto), // 180
+ PLAX_ (__NR_setsockopt, sys_setsockopt), // 181
+ PLAXY (__NR_socket, sys_socket), // 183
+ PLAXY (__NR_socketpair, sys_socketpair), // 184
+ LINX_ (__NR_setresuid, sys_setresuid), // 185
+ LINXY (__NR_getresuid, sys_getresuid), // 186
+ //.. GENX_(__NR_query_module, sys_ni_syscall), //
+ GENXY (__NR_poll, sys_poll), // 188
+ //.. // (__NR_nfsservctl, sys_nfsservctl), // 168 */Linux
+ //..
+ LINX_ (__NR_setresgid, sys_setresgid), // 190
+ LINXY (__NR_getresgid, sys_getresgid), // 191
+ LINXY (__NR_prctl, sys_prctl), // 192
+ PLAX_ (__NR_rt_sigreturn, sys_rt_sigreturn), // 193
+ LINXY (__NR_rt_sigaction, sys_rt_sigaction), // 194
+ LINXY (__NR_rt_sigprocmask, sys_rt_sigprocmask), // 195
+ LINXY (__NR_rt_sigpending, sys_rt_sigpending), // 196
+ LINXY (__NR_rt_sigtimedwait, sys_rt_sigtimedwait), // 197
+ LINXY (__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 198
+ LINX_ (__NR_rt_sigsuspend, sys_rt_sigsuspend), // 199
+ GENXY (__NR_pread64, sys_pread64), // 200
+ GENX_ (__NR_pwrite64, sys_pwrite64), // 201
+ GENX_ (__NR_chown, sys_chown), // 202
+ GENXY (__NR_getcwd, sys_getcwd), // 203
+ LINXY (__NR_capget, sys_capget), // 204
+ //..
+ //.. LINX_(__NR_capset, sys_capset), // 205
+ GENXY (__NR_sigaltstack, sys_sigaltstack), // 206
+ LINXY (__NR_sendfile, sys_sendfile), // 207
+ //.. GENXY(__NR_getpmsg, sys_getpmsg), // 208
+ //.. GENX_(__NR_putpmsg, sys_putpmsg), // 209
+ // Nb: we treat vfork as fork
+ // GENX_(__NR_vfork, sys_fork), //
+ GENXY (__NR_getrlimit, sys_getrlimit), // 76
+ //__NR_readahead // 191 ppc/Linux only?
+ PLAX_ (__NR_mmap2, sys_mmap2), // 210
+ // GENX_(__NR_truncate64, sys_truncate64), // 211
+ GENX_ (__NR_ftruncate64, sys_ftruncate64), // 212
+ //..
+ PLAXY (__NR_stat64, sys_stat64), // 213
+ PLAXY (__NR_lstat64, sys_lstat64), // 214
+ PLAXY (__NR_fstat64, sys_fstat64), // 215
+ GENXY (__NR_getdents64, sys_getdents64), // 219
+ //.. // (__NR_pivot_root, sys_pivot_root), //
+ LINXY (__NR_fcntl64, sys_fcntl64), // 220
+ GENX_ (__NR_madvise, sys_madvise), // 218
+ GENXY (__NR_mincore, sys_mincore), // 217
+ LINX_ (__NR_gettid, sys_gettid), // 222
+ //.. LINX_(__NR_tkill, sys_tkill), // 208 */Linux
+ //.. LINX_(__NR_setxattr, sys_setxattr), // 209
+ //.. LINX_(__NR_lsetxattr, sys_lsetxattr), // 210
+ //.. LINX_(__NR_fsetxattr, sys_fsetxattr), // 211
+ LINXY (__NR_getxattr, sys_getxattr), // 227
+ LINXY (__NR_lgetxattr, sys_lgetxattr), // 228
+ LINXY (__NR_fgetxattr, sys_fgetxattr), // 229
+ LINXY (__NR_listxattr, sys_listxattr), // 230
+ LINXY (__NR_llistxattr, sys_llistxattr), // 231
+ LINXY (__NR_flistxattr, sys_flistxattr), // 232
+ LINX_ (__NR_removexattr, sys_removexattr), // 233
+ LINX_ (__NR_lremovexattr, sys_lremovexattr), // 234
+ LINX_ (__NR_fremovexattr, sys_fremovexattr), // 235
+ LINXY (__NR_futex, sys_futex), // 238
+ LINX_ (__NR_sched_setaffinity, sys_sched_setaffinity), // 239
+ LINXY (__NR_sched_getaffinity, sys_sched_getaffinity), // 240
+ /* 224 currently unused */
+ // __NR_tuxcall //
+ LINXY (__NR_sendfile64, sys_sendfile64), // 237
+ //..
+ LINX_ (__NR_io_setup, sys_io_setup), // 241
+ LINX_ (__NR_io_destroy, sys_io_destroy), // 242
+ LINXY (__NR_io_getevents, sys_io_getevents), // 243
+ LINX_ (__NR_io_submit, sys_io_submit), // 244
+ LINXY (__NR_io_cancel, sys_io_cancel), // 245
+ //..
+ LINX_ (__NR_set_tid_address, sys_set_tid_address), // 252
+ LINX_ (__NR_fadvise64, sys_fadvise64), // 254
+ LINX_ (__NR_exit_group, sys_exit_group), // 246
+ //.. GENXY(__NR_lookup_dcookie, sys_lookup_dcookie), // 247
+ LINXY (__NR_epoll_create, sys_epoll_create), // 248
+ LINX_ (__NR_epoll_ctl, sys_epoll_ctl), // 249
+ LINXY (__NR_epoll_wait, sys_epoll_wait), // 250
+ //.. // (__NR_remap_file_pages, sys_remap_file_pages), // 239 */Linux
+ LINXY (__NR_timer_create, sys_timer_create), // 257
+ LINXY (__NR_timer_settime, sys_timer_settime), // 258
+ LINXY (__NR_timer_gettime, sys_timer_gettime), // 259
+ LINX_ (__NR_timer_getoverrun, sys_timer_getoverrun), // 260
+ LINX_ (__NR_timer_delete, sys_timer_delete), // 261
+ LINX_ (__NR_clock_settime, sys_clock_settime), // 262
+ LINXY (__NR_clock_gettime, sys_clock_gettime), // 263
+ LINXY (__NR_clock_getres, sys_clock_getres), // 264
+ LINXY (__NR_clock_nanosleep, sys_clock_nanosleep), // 265
+ // __NR_swapcontext //
+ LINXY (__NR_tgkill, sys_tgkill), // 266 */Linux
+ //.. GENX_(__NR_utimes, sys_utimes), // 267
+ GENXY (__NR_statfs64, sys_statfs64), // 255
+ GENXY (__NR_fstatfs64, sys_fstatfs64), // 256
+ LINXY (__NR_get_mempolicy, sys_get_mempolicy), // 269
+ LINX_ (__NR_set_mempolicy, sys_set_mempolicy), // 270
+ LINXY (__NR_mq_open, sys_mq_open), // 271
+ LINX_ (__NR_mq_unlink, sys_mq_unlink), // 272
+ LINX_ (__NR_mq_timedsend, sys_mq_timedsend), // 273
+ LINXY (__NR_mq_timedreceive, sys_mq_timedreceive), // 274
+ LINX_ (__NR_mq_notify, sys_mq_notify), // 275
+ LINXY (__NR_mq_getsetattr, sys_mq_getsetattr), // 276
+ // __NR_kexec_load //
+ LINX_ (__NR_inotify_init, sys_inotify_init), // 275
+ LINX_ (__NR_inotify_add_watch, sys_inotify_add_watch), // 276
+ LINX_ (__NR_inotify_rm_watch, sys_inotify_rm_watch), // 277
+ PLAX_ (__NR_set_thread_area, sys_set_thread_area), // 283
+ LINXY (__NR_openat, sys_openat), // 288
+ LINX_ (__NR_mkdirat, sys_mkdirat), // 289
+ LINX_ (__NR_mknodat, sys_mknodat), // 290
+ LINX_ (__NR_fchownat, sys_fchownat), // 291
+ LINX_ (__NR_futimesat, sys_futimesat), // 292
+ PLAXY (__NR_fstatat64, sys_fstatat64), // 293
+ LINX_ (__NR_unlinkat, sys_unlinkat), // 294
+ LINX_ (__NR_renameat, sys_renameat), // 295
+ LINX_ (__NR_linkat, sys_linkat), // 296
+ LINX_ (__NR_symlinkat, sys_symlinkat), // 297
+ LINX_ (__NR_readlinkat, sys_readlinkat), // 298
+ LINX_ (__NR_fchmodat, sys_fchmodat), // 299
+ LINX_ (__NR_faccessat, sys_faccessat), // 300
+ LINXY (__NR_ppoll, sys_ppoll), // 302
+ LINX_ (__NR_set_robust_list, sys_set_robust_list), // 309
+ LINXY (__NR_get_robust_list, sys_get_robust_list), // 310
+ LINXY (__NR_epoll_pwait, sys_epoll_pwait), // 313
+ LINX_ (__NR_utimensat, sys_utimensat), // 316
+ LINX_ (__NR_fallocate, sys_fallocate), // 320
+ LINXY (__NR_timerfd_create, sys_timerfd_create), // 321
+ LINXY (__NR_timerfd_gettime, sys_timerfd_gettime), // 322
+ LINXY (__NR_timerfd_settime, sys_timerfd_settime), // 323
+ LINXY (__NR_signalfd4, sys_signalfd4), // 324
+ LINX_ (__NR_eventfd2, sys_eventfd2), // 325
+ LINXY (__NR_pipe2, sys_pipe2), // 328
+ LINXY (__NR_inotify_init1, sys_inotify_init1), // 329
+ LINXY (__NR_prlimit64, sys_prlimit64) // 338
+};
+
+SyscallTableEntry* ML_(get_linux_syscall_entry) (UInt sysno)
+{
+ const UInt syscall_main_table_size
+ = sizeof (syscall_main_table) / sizeof (syscall_main_table[0]);
+ /* Is it in the contiguous initial section of the table? */
+ if (sysno < syscall_main_table_size)
+ {
+ SyscallTableEntry * sys = &syscall_main_table[sysno];
+ if (sys->before == NULL)
+ return NULL; /* no entry */
+ else
+ return sys;
+ }
+ /* Can't find a wrapper */
+ return NULL;
+}
+
+#endif // defined(VGP_mips32_linux)
+
+/*--------------------------------------------------------------------*/
+/*--- end syswrap-mips-linux.c ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/m_syswrap/syswrap-ppc32-linux.c b/main/coregrind/m_syswrap/syswrap-ppc32-linux.c
index 6a62867..3d7ab5e 100644
--- a/main/coregrind/m_syswrap/syswrap-ppc32-linux.c
+++ b/main/coregrind/m_syswrap/syswrap-ppc32-linux.c
@@ -7,8 +7,8 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote <njn@valgrind.org>
- Copyright (C) 2005-2011 Cerion Armour-Brown <cerion@open-works.co.uk>
+ Copyright (C) 2005-2012 Nicholas Nethercote <njn@valgrind.org>
+ Copyright (C) 2005-2012 Cerion Armour-Brown <cerion@open-works.co.uk>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -158,6 +158,7 @@
vki_modify_ldt_t * );
asm(
".text\n"
+".globl do_syscall_clone_ppc32_linux\n"
"do_syscall_clone_ppc32_linux:\n"
" stwu 1,-32(1)\n"
" stw 29,20(1)\n"
@@ -335,6 +336,7 @@
know that this thread has come into existence. If the clone
fails, we'll send out a ll_exit notification for it at the out:
label below, to clean up. */
+ vg_assert(VG_(owns_BigLock_LL)(ptid));
VG_TRACK ( pre_thread_ll_create, ptid, ctid );
if (flags & VKI_CLONE_SETTLS) {
@@ -556,7 +558,7 @@
* (after all it's glibc providing the arguments array)
PRE_MEM_READ( "socketcall.sendmsg(args)", ARG2, 3*sizeof(Addr) );
*/
- ML_(generic_PRE_sys_sendmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_sendmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -567,7 +569,7 @@
* (after all it's glibc providing the arguments array)
PRE_MEM_READ("socketcall.recvmsg(args)", ARG2, 3*sizeof(Addr) );
*/
- ML_(generic_PRE_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -672,7 +674,7 @@
break;
case VKI_SYS_RECVMSG:
- ML_(generic_POST_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_POST_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1, RES );
break;
default:
@@ -1806,7 +1808,7 @@
LINX_(__NR_faccessat, sys_faccessat), // 298
LINX_(__NR_set_robust_list, sys_set_robust_list), // 299
LINXY(__NR_get_robust_list, sys_get_robust_list), // 300
-// LINX_(__NR_move_pages, sys_ni_syscall), // 301
+ LINXY(__NR_move_pages, sys_move_pages), // 301
LINXY(__NR_getcpu, sys_getcpu), // 302
LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 303
LINX_(__NR_utimensat, sys_utimensat), // 304
@@ -1827,7 +1829,10 @@
LINXY(__NR_perf_event_open, sys_perf_event_open), // 319
LINXY(__NR_preadv, sys_preadv), // 320
LINX_(__NR_pwritev, sys_pwritev), // 321
- LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo) // 322
+ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 322
+
+ LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 351
+ LINX_(__NR_process_vm_writev, sys_process_vm_writev) // 352
};
SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno )
diff --git a/main/coregrind/m_syswrap/syswrap-ppc64-linux.c b/main/coregrind/m_syswrap/syswrap-ppc64-linux.c
index fbb5ba5..0d84fd4 100644
--- a/main/coregrind/m_syswrap/syswrap-ppc64-linux.c
+++ b/main/coregrind/m_syswrap/syswrap-ppc64-linux.c
@@ -7,8 +7,8 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote <njn@valgrind.org>
- Copyright (C) 2005-2011 Cerion Armour-Brown <cerion@open-works.co.uk>
+ Copyright (C) 2005-2012 Nicholas Nethercote <njn@valgrind.org>
+ Copyright (C) 2005-2012 Cerion Armour-Brown <cerion@open-works.co.uk>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -363,6 +363,7 @@
know that this thread has come into existence. If the clone
fails, we'll send out a ll_exit notification for it at the out:
label below, to clean up. */
+ vg_assert(VG_(owns_BigLock_LL)(ptid));
VG_TRACK ( pre_thread_ll_create, ptid, ctid );
if (flags & VKI_CLONE_SETTLS) {
@@ -583,7 +584,7 @@
* (after all it's glibc providing the arguments array)
PRE_MEM_READ( "socketcall.sendmsg(args)", ARG2, 3*sizeof(Addr) );
*/
- ML_(generic_PRE_sys_sendmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_sendmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -594,7 +595,7 @@
* (after all it's glibc providing the arguments array)
PRE_MEM_READ("socketcall.recvmsg(args)", ARG2, 3*sizeof(Addr) );
*/
- ML_(generic_PRE_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -700,7 +701,7 @@
break;
case VKI_SYS_RECVMSG:
- ML_(generic_POST_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_POST_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1, RES );
break;
default:
@@ -1446,7 +1447,7 @@
LINX_(__NR_faccessat, sys_faccessat), // 298
LINX_(__NR_set_robust_list, sys_set_robust_list), // 299
LINXY(__NR_get_robust_list, sys_get_robust_list), // 300
-// LINX_(__NR_move_pages, sys_ni_syscall), // 301
+ LINXY(__NR_move_pages, sys_move_pages), // 301
LINXY(__NR_getcpu, sys_getcpu), // 302
LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 303
LINX_(__NR_utimensat, sys_utimensat), // 304
@@ -1467,7 +1468,10 @@
LINXY(__NR_perf_event_open, sys_perf_event_open), // 319
LINXY(__NR_preadv, sys_preadv), // 320
LINX_(__NR_pwritev, sys_pwritev), // 321
- LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo) // 322
+ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 322
+
+ LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 351
+ LINX_(__NR_process_vm_writev, sys_process_vm_writev) // 352
};
SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno )
diff --git a/main/coregrind/m_syswrap/syswrap-s390x-linux.c b/main/coregrind/m_syswrap/syswrap-s390x-linux.c
index 4880226..64c4496 100644
--- a/main/coregrind/m_syswrap/syswrap-s390x-linux.c
+++ b/main/coregrind/m_syswrap/syswrap-s390x-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -151,6 +151,7 @@
asm(
" .text\n"
" .align 4\n"
+ ".globl do_syscall_clone_s390x_linux\n"
"do_syscall_clone_s390x_linux:\n"
" lg %r1, 160(%r15)\n" // save fn from parent stack into r1
" lg %r0, 168(%r15)\n" // save arg from parent stack into r0
@@ -287,6 +288,7 @@
know that this thread has come into existence. If the clone
fails, we'll send out a ll_exit notification for it at the out:
label below, to clean up. */
+ vg_assert(VG_(owns_BigLock_LL)(ptid));
VG_TRACK ( pre_thread_ll_create, ptid, ctid );
if (flags & VKI_CLONE_SETTLS) {
@@ -625,7 +627,7 @@
SET_STATUS_Failure( VKI_EFAULT );
break;
}
- ML_(generic_PRE_sys_sendmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_sendmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -636,7 +638,7 @@
SET_STATUS_Failure( VKI_EFAULT );
break;
}
- ML_(generic_PRE_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_recvmsg)( tid, "msg2", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -740,7 +742,7 @@
break;
case VKI_SYS_RECVMSG:
- ML_(generic_POST_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_POST_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1, RES );
break;
default:
@@ -963,6 +965,13 @@
}
}
+ /* The kernel simply copies reg6 (ARG5) into AR0 and AR1, no checks */
+ if (ARG2 & VKI_CLONE_SETTLS) {
+ if (VG_(tdict).track_pre_reg_read) {
+ PRA5("clone", Addr, tlsinfo);
+ }
+ }
+
cloneflags = ARG2;
if (!ML_(client_signal_OK)(ARG2 & VKI_CSIGNAL)) {
@@ -1503,6 +1512,16 @@
// ?????(__NR_rt_tgsigqueueinfo, ),
LINXY(__NR_perf_event_open, sys_perf_event_open), // 331
+// ?????(__NR_fanotify_init, ), // 332
+// ?????(__NR_fanotify_mark, ), // 333
+ LINXY(__NR_prlimit64, sys_prlimit64), // 334
+// ?????(__NR_name_to_handle_at, ), // 335
+// ?????(__NR_open_by_handle_at, ), // 336
+// ?????(__NR_clock_adjtime, ), // 337
+// ?????(__NR_syncfs, ), // 338
+// ?????(__NR_setns, ), // 339
+ LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 340
+ LINX_(__NR_process_vm_writev, sys_process_vm_writev), // 341
};
SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno )
diff --git a/main/coregrind/m_syswrap/syswrap-x86-darwin.c b/main/coregrind/m_syswrap/syswrap-x86-darwin.c
index 5045e20..1a90d8f 100644
--- a/main/coregrind/m_syswrap/syswrap-x86-darwin.c
+++ b/main/coregrind/m_syswrap/syswrap-x86-darwin.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Apple Inc.
+ Copyright (C) 2005-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -401,6 +401,7 @@
set the mask correctly when we finally get there. */
VG_(sigfillset)(&blockall);
VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, NULL);
+
if (reuse) {
/* For whatever reason, tst->os_state.pthread appear to have a
@@ -408,7 +409,7 @@
idea why. */
# if DARWIN_VERS <= DARWIN_10_6
UWord magic_delta = 0;
-# elif DARWIN_VERS == DARWIN_10_7
+# elif DARWIN_VERS >= DARWIN_10_7
UWord magic_delta = 0x48;
# endif
@@ -436,16 +437,6 @@
vex = &tst->arch.vex;
allocstack(tst->tid);
LibVEX_GuestX86_initialise(vex);
- /* Tell threading tools the new thread exists. FIXME: we need
- to know the identity (tid) of the parent thread, in order
- that threading tools can make a dependency edge from it to
- this thread. But we don't know what the parent thread is.
- Hence pass 1 (the root thread). This is completely wrong in
- general, and could cause large numbers of false races to be
- reported. In fact, it's positively dangerous; we don't even
- know if thread 1 is still alive, and the thread checkers are
- likely to assert if it isn't. */
- VG_TRACK(pre_thread_ll_create, 1/*BOGUS*/, tst->tid);
}
// Set thread's registers
@@ -463,7 +454,6 @@
stacksize = 512*1024; // wq stacks are always DEFAULT_STACK_SIZE
stack = VG_PGROUNDUP(sp) - stacksize;
- VG_TRACK(workq_task_start, tst->tid, workitem);
if (reuse) {
// Continue V's thread back in the scheduler.
// The client thread is of course in another location entirely.
@@ -488,11 +478,7 @@
tst->client_stack_highest_word = stack+stacksize;
tst->client_stack_szB = stacksize;
- // tell the tool that we are at a point after the new thread
- // has its registers set up (so we can take a stack snapshot),
- // but before it has executed any instructions (or, really,
- // before it has done any memory references).
- VG_TRACK(pre_thread_first_insn, tst->tid);
+ // GrP fixme scheduler lock?!
// pthread structure
ML_(notify_core_and_tool_of_mmap)(
diff --git a/main/coregrind/m_syswrap/syswrap-x86-linux.c b/main/coregrind/m_syswrap/syswrap-x86-linux.c
index b0b821f..5009c68 100644
--- a/main/coregrind/m_syswrap/syswrap-x86-linux.c
+++ b/main/coregrind/m_syswrap/syswrap-x86-linux.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -142,6 +142,7 @@
vki_modify_ldt_t * );
asm(
".text\n"
+".globl do_syscall_clone_x86_linux\n"
"do_syscall_clone_x86_linux:\n"
" push %ebx\n"
" push %edi\n"
@@ -303,6 +304,7 @@
if we don't state the new thread exists prior to that point.
If the clone fails, we'll send out a ll_exit notification for it
at the out: label below, to clean up. */
+ vg_assert(VG_(owns_BigLock_LL)(ptid));
VG_TRACK ( pre_thread_ll_create, ptid, ctid );
if (flags & VKI_CLONE_SETTLS) {
@@ -1576,7 +1578,7 @@
* (after all it's glibc providing the arguments array)
PRE_MEM_READ( "socketcall.sendmsg(args)", ARG2, 3*sizeof(Addr) );
*/
- ML_(generic_PRE_sys_sendmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_sendmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -1587,7 +1589,7 @@
* (after all it's glibc providing the arguments array)
PRE_MEM_READ("socketcall.recvmsg(args)", ARG2, 3*sizeof(Addr) );
*/
- ML_(generic_PRE_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
+ ML_(generic_PRE_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1 );
break;
}
@@ -1693,8 +1695,8 @@
break;
case VKI_SYS_RECVMSG:
- ML_(generic_POST_sys_recvmsg)( tid, ARG2_0, ARG2_1 );
- break;
+ ML_(generic_POST_sys_recvmsg)( tid, "msg", (struct vki_msghdr *)ARG2_1, RES );
+ break;
default:
VG_(message)(Vg_DebugMsg,"FATAL: unhandled socketcall 0x%lx\n",ARG1);
@@ -2193,9 +2195,9 @@
LINX_(__NR_splice, sys_splice), // 313
LINX_(__NR_sync_file_range, sys_sync_file_range), // 314
-// LINX_(__NR_tee, sys_ni_syscall), // 315
-// LINX_(__NR_vmsplice, sys_ni_syscall), // 316
-// LINX_(__NR_move_pages, sys_ni_syscall), // 317
+ LINX_(__NR_tee, sys_tee), // 315
+ LINXY(__NR_vmsplice, sys_vmsplice), // 316
+ LINXY(__NR_move_pages, sys_move_pages), // 317
LINXY(__NR_getcpu, sys_getcpu), // 318
LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 319
@@ -2219,18 +2221,20 @@
LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 335
LINXY(__NR_perf_event_open, sys_perf_event_open), // 336
-// LINX_(__NR_recvmmsg, sys_ni_syscall), // 337
+ LINXY(__NR_recvmmsg, sys_recvmmsg), // 337
// LINX_(__NR_fanotify_init, sys_ni_syscall), // 338
// LINX_(__NR_fanotify_mark, sys_ni_syscall), // 339
- LINXY(__NR_prlimit64, sys_prlimit64) // 340
+ LINXY(__NR_prlimit64, sys_prlimit64), // 340
// LINX_(__NR_name_to_handle_at, sys_ni_syscall), // 341
// LINX_(__NR_open_by_handle_at, sys_ni_syscall), // 342
// LINX_(__NR_clock_adjtime, sys_ni_syscall), // 343
// LINX_(__NR_syncfs, sys_ni_syscall), // 344
-// LINX_(__NR_sendmmsg, sys_ni_syscall), // 345
+ LINXY(__NR_sendmmsg, sys_sendmmsg), // 345
// LINX_(__NR_setns, sys_ni_syscall), // 346
+ LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 347
+ LINX_(__NR_process_vm_writev, sys_process_vm_writev) // 348
};
SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno )
diff --git a/main/coregrind/m_threadstate.c b/main/coregrind/m_threadstate.c
index d2f6aca..3cd9478 100644
--- a/main/coregrind/m_threadstate.c
+++ b/main/coregrind/m_threadstate.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -33,6 +33,10 @@
#include "pub_core_libcsetjmp.h" // to keep _threadstate.h happy
#include "pub_core_threadstate.h"
#include "pub_core_libcassert.h"
+#include "pub_tool_inner.h"
+#if defined(ENABLE_INNER_CLIENT_REQUEST)
+#include "helgrind/helgrind.h"
+#endif
/*------------------------------------------------------------*/
/*--- Data structures. ---*/
@@ -40,12 +44,27 @@
ThreadId VG_(running_tid) = VG_INVALID_THREADID;
-ThreadState VG_(threads)[VG_N_THREADS];
+ThreadState VG_(threads)[VG_N_THREADS] __attribute__((aligned(16)));
/*------------------------------------------------------------*/
/*--- Operations. ---*/
/*------------------------------------------------------------*/
+void VG_(init_Threads)(void)
+{
+ ThreadId tid;
+
+ for (tid = 1; tid < VG_N_THREADS; tid++) {
+ INNER_REQUEST(
+ ANNOTATE_BENIGN_RACE_SIZED(&VG_(threads)[tid].status,
+ sizeof(VG_(threads)[tid].status), ""));
+ INNER_REQUEST(
+ ANNOTATE_BENIGN_RACE_SIZED(&VG_(threads)[tid].os_state.exitcode,
+ sizeof(VG_(threads)[tid].os_state.exitcode),
+ ""));
+ }
+}
+
const HChar* VG_(name_of_ThreadStatus) ( ThreadStatus status )
{
switch (status) {
diff --git a/main/coregrind/m_tooliface.c b/main/coregrind/m_tooliface.c
index 9199961..be9f116 100644
--- a/main/coregrind/m_tooliface.c
+++ b/main/coregrind/m_tooliface.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Nicholas Nethercote
+ Copyright (C) 2000-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -408,7 +408,6 @@
DEF0(track_stop_client_code, ThreadId, ULong)
DEF0(track_pre_thread_ll_create, ThreadId, ThreadId)
-DEF0(track_workq_task_start, ThreadId, Addr)
DEF0(track_pre_thread_first_insn, ThreadId)
DEF0(track_pre_thread_ll_exit, ThreadId)
diff --git a/main/coregrind/m_trampoline.S b/main/coregrind/m_trampoline.S
index bc22700..d41e2d6 100644
--- a/main/coregrind/m_trampoline.S
+++ b/main/coregrind/m_trampoline.S
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -189,6 +189,16 @@
.LfnE3:
.size VG_(amd64_linux_REDIR_FOR_vtime), .-.LfnB3
+.global VG_(amd64_linux_REDIR_FOR_vgetcpu)
+.type VG_(amd64_linux_REDIR_FOR_vgetcpu), @function
+VG_(amd64_linux_REDIR_FOR_vgetcpu):
+.LfnB4:
+ movq $__NR_getcpu, %rax
+ syscall
+ ret
+.LfnE4:
+.size VG_(amd64_linux_REDIR_FOR_vgetcpu), .-.LfnB4
+
/* There's no particular reason that this needs to be handwritten
assembly, but since that's what this file contains, here's a
simple strlen implementation (written in C and compiled by gcc.)
@@ -196,7 +206,7 @@
.global VG_(amd64_linux_REDIR_FOR_strlen)
.type VG_(amd64_linux_REDIR_FOR_strlen), @function
VG_(amd64_linux_REDIR_FOR_strlen):
-.LfnB4:
+.LfnB5:
xorl %eax, %eax
cmpb $0, (%rdi)
movq %rdi, %rdx
@@ -207,11 +217,11 @@
movq %rdx, %rax
subq %rdi, %rax
.L41: ret
-.LfnE4:
+.LfnE5:
.size VG_(amd64_linux_REDIR_FOR_strlen), .-VG_(amd64_linux_REDIR_FOR_strlen)
-/* A CIE for the above three functions, followed by their FDEs */
+/* A CIE for the above four functions, followed by their FDEs */
.section .eh_frame,"a",@progbits
.Lframe1:
.long .LEcie1-.LScie1
@@ -258,6 +268,15 @@
.uleb128 0x0
.align 8
.LEfde4:
+.LSfde5:
+ .long .LEfde5-.LASfde5
+.LASfde5:
+ .long .LASfde5-.Lframe1
+ .long .LfnB5
+ .long .LfnE5-.LfnB5
+ .uleb128 0x0
+ .align 8
+.LEfde5:
.previous
.global VG_(trampoline_stuff_end)
@@ -517,6 +536,22 @@
.global VG_(trampoline_stuff_start)
VG_(trampoline_stuff_start):
+.global VG_(arm_linux_SUBST_FOR_sigreturn)
+.type VG_(arm_linux_SUBST_FOR_sigreturn),#function
+VG_(arm_linux_SUBST_FOR_sigreturn):
+ mov r7, # __NR_sigreturn
+ svc #0
+ .long 0xFFFFFFFF /*illegal insn*/
+.size VG_(arm_linux_SUBST_FOR_sigreturn), .-VG_(arm_linux_SUBST_FOR_sigreturn)
+
+.global VG_(arm_linux_SUBST_FOR_rt_sigreturn)
+.type VG_(arm_linux_SUBST_FOR_rt_sigreturn),#function
+VG_(arm_linux_SUBST_FOR_rt_sigreturn):
+ mov r7, # __NR_rt_sigreturn
+ svc #0
+ .long 0xFFFFFFFF /*illegal insn*/
+.size VG_(arm_linux_SUBST_FOR_rt_sigreturn), .-VG_(arm_linux_SUBST_FOR_rt_sigreturn)
+
.global VG_(arm_linux_REDIR_FOR_strlen)
VG_(arm_linux_REDIR_FOR_strlen):
mov r2, r0
@@ -986,6 +1021,64 @@
VG_(trampoline_stuff_end):
.fill 2048, 2, 0x0000
+/*---------------------- mips32-linux ----------------------*/
+#else
+#if defined(VGP_mips32_linux)
+
+# define UD2_16 trap ; trap ; trap; trap
+# define UD2_64 UD2_16 ; UD2_16 ; UD2_16 ; UD2_16
+# define UD2_256 UD2_64 ; UD2_64 ; UD2_64 ; UD2_64
+# define UD2_1024 UD2_256 ; UD2_256 ; UD2_256 ; UD2_256
+# define UD2_PAGE UD2_1024 ; UD2_1024 ; UD2_1024 ; UD2_1024
+
+
+.global VG_(trampoline_stuff_start)
+VG_(trampoline_stuff_start):
+
+.global VG_(mips32_linux_SUBST_FOR_sigreturn)
+VG_(mips32_linux_SUBST_FOR_sigreturn):
+ li $v0,__NR_sigreturn
+ syscall
+ nop
+ .long 0 /*illegal insn*/
+
+.global VG_(mips32_linux_SUBST_FOR_rt_sigreturn)
+VG_(mips32_linux_SUBST_FOR_rt_sigreturn):
+ li $v0,__NR_rt_sigreturn
+ syscall
+ nop
+ .long 0 /*illegal insn*/
+
+/* There's no particular reason that this needs to be handwritten
+ assembly, but since that's what this file contains, here's a
+ simple strlen implementation (written in C and compiled by gcc.)
+*/
+.global VG_(mips32_linux_REDIR_FOR_strlen)
+.type VG_(mips32_linux_REDIR_FOR_strlen), @function
+VG_(mips32_linux_REDIR_FOR_strlen):
+ li $v0, 0
+ //la $a0, string
+ j strlen_cond
+ strlen_loop:
+ addi $v0, $v0, 1
+ addi $a0, $a0, 1
+ strlen_cond:
+ lbu $t0, ($a0)
+ bne $t0, $zero, strlen_loop
+ jr $ra
+
+.size VG_(mips32_linux_REDIR_FOR_strlen), .-VG_(mips32_linux_REDIR_FOR_strlen)
+
+.global VG_(trampoline_stuff_end)
+VG_(trampoline_stuff_end):
+
+
+# undef UD2_16
+# undef UD2_64
+# undef UD2_256
+# undef UD2_1024
+# undef UD2_PAGE
+
/*---------------- unknown ----------------*/
#else
# error Unknown platform
@@ -997,6 +1090,7 @@
#endif
#endif
#endif
+#endif
#if defined(VGO_linux)
/* Let the linker know we don't need an executable stack */
diff --git a/main/coregrind/m_translate.c b/main/coregrind/m_translate.c
index 41ba2b8..b3c98dc 100644
--- a/main/coregrind/m_translate.c
+++ b/main/coregrind/m_translate.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -262,7 +262,7 @@
IRType gWordTy,
IRType hWordTy )
{
- Int i, j, minoff_ST, maxoff_ST, sizeof_SP, offset_SP;
+ Int i, j, k, minoff_ST, maxoff_ST, sizeof_SP, offset_SP;
Int first_SP, last_SP, first_Put, last_Put;
IRDirty *dcall, *d;
IRStmt* st;
@@ -280,6 +280,7 @@
bb->tyenv = deepCopyIRTypeEnv(sb_in->tyenv);
bb->next = deepCopyIRExpr(sb_in->next);
bb->jumpkind = sb_in->jumpkind;
+ bb->offsIP = sb_in->offsIP;
delta = 0;
@@ -333,6 +334,8 @@
dcall->fxState[0].fx = Ifx_Read; \
dcall->fxState[0].offset = layout->offset_SP; \
dcall->fxState[0].size = layout->sizeof_SP; \
+ dcall->fxState[0].nRepeats = 0; \
+ dcall->fxState[0].repeatLen = 0; \
\
addStmtToIRSB( bb, IRStmt_Dirty(dcall) ); \
\
@@ -361,6 +364,8 @@
dcall->fxState[0].fx = Ifx_Read; \
dcall->fxState[0].offset = layout->offset_SP; \
dcall->fxState[0].size = layout->sizeof_SP; \
+ dcall->fxState[0].nRepeats = 0; \
+ dcall->fxState[0].repeatLen = 0; \
\
addStmtToIRSB( bb, IRStmt_Dirty(dcall) ); \
\
@@ -585,7 +590,7 @@
deal with SP changing in weird ways (well, we can, but not at
this time of night). */
if (st->tag == Ist_PutI) {
- descr = st->Ist.PutI.descr;
+ descr = st->Ist.PutI.details->descr;
minoff_ST = descr->base;
maxoff_ST = descr->base
+ descr->nElems * sizeofIRType(descr->elemTy) - 1;
@@ -596,13 +601,16 @@
if (st->tag == Ist_Dirty) {
d = st->Ist.Dirty.details;
for (j = 0; j < d->nFxState; j++) {
- minoff_ST = d->fxState[j].offset;
- maxoff_ST = d->fxState[j].offset + d->fxState[j].size - 1;
if (d->fxState[j].fx == Ifx_Read || d->fxState[j].fx == Ifx_None)
continue;
- if (!(offset_SP > maxoff_ST
- || (offset_SP + sizeof_SP - 1) < minoff_ST))
- goto complain;
+ /* Enumerate the described state segments */
+ for (k = 0; k < 1 + d->fxState[j].nRepeats; k++) {
+ minoff_ST = d->fxState[j].offset + k * d->fxState[j].repeatLen;
+ maxoff_ST = minoff_ST + d->fxState[j].size - 1;
+ if (!(offset_SP > maxoff_ST
+ || (offset_SP + sizeof_SP - 1) < minoff_ST))
+ goto complain;
+ }
}
}
@@ -718,7 +726,7 @@
static Bool translations_allowable_from_seg ( NSegment const* seg )
{
-# if defined(VGA_x86) || defined(VGA_s390x)
+# if defined(VGA_x86) || defined(VGA_s390x) || defined(VGA_mips32)
Bool allowR = True;
# else
Bool allowR = False;
@@ -905,6 +913,7 @@
Int offB_REDIR_SP = offsetof(VexGuestPPC64State,guest_REDIR_SP);
Int offB_REDIR_STACK = offsetof(VexGuestPPC64State,guest_REDIR_STACK);
Int offB_EMWARN = offsetof(VexGuestPPC64State,guest_EMWARN);
+ Int offB_CIA = offsetof(VexGuestPPC64State,guest_CIA);
Bool is64 = True;
IRType ty_Word = Ity_I64;
IROp op_CmpNE = Iop_CmpNE64;
@@ -918,6 +927,7 @@
Int offB_REDIR_SP = offsetof(VexGuestPPC32State,guest_REDIR_SP);
Int offB_REDIR_STACK = offsetof(VexGuestPPC32State,guest_REDIR_STACK);
Int offB_EMWARN = offsetof(VexGuestPPC32State,guest_EMWARN);
+ Int offB_CIA = offsetof(VexGuestPPC32State,guest_CIA);
Bool is64 = False;
IRType ty_Word = Ity_I32;
IROp op_CmpNE = Iop_CmpNE32;
@@ -969,7 +979,8 @@
mkU(0)
),
Ijk_EmFail,
- is64 ? IRConst_U64(0) : IRConst_U32(0)
+ is64 ? IRConst_U64(0) : IRConst_U32(0),
+ offB_CIA
)
);
@@ -980,8 +991,8 @@
/* PutI/GetI have I32-typed indexes regardless of guest word size */
addStmtToIRSB(
bb,
- IRStmt_PutI(descr, narrowTo32(bb->tyenv,IRExpr_RdTmp(t1)), 0, e)
- );
+ IRStmt_PutI(mkIRPutI(descr,
+ narrowTo32(bb->tyenv,IRExpr_RdTmp(t1)), 0, e)));
}
@@ -996,6 +1007,7 @@
Int offB_REDIR_SP = offsetof(VexGuestPPC64State,guest_REDIR_SP);
Int offB_REDIR_STACK = offsetof(VexGuestPPC64State,guest_REDIR_STACK);
Int offB_EMWARN = offsetof(VexGuestPPC64State,guest_EMWARN);
+ Int offB_CIA = offsetof(VexGuestPPC64State,guest_CIA);
Bool is64 = True;
IRType ty_Word = Ity_I64;
IROp op_CmpNE = Iop_CmpNE64;
@@ -1007,6 +1019,7 @@
Int offB_REDIR_SP = offsetof(VexGuestPPC32State,guest_REDIR_SP);
Int offB_REDIR_STACK = offsetof(VexGuestPPC32State,guest_REDIR_STACK);
Int offB_EMWARN = offsetof(VexGuestPPC32State,guest_EMWARN);
+ Int offB_CIA = offsetof(VexGuestPPC32State,guest_CIA);
Bool is64 = False;
IRType ty_Word = Ity_I32;
IROp op_CmpNE = Iop_CmpNE32;
@@ -1048,7 +1061,8 @@
mkU(0)
),
Ijk_EmFail,
- is64 ? IRConst_U64(0) : IRConst_U32(0)
+ is64 ? IRConst_U64(0) : IRConst_U32(0),
+ offB_CIA
)
);
@@ -1099,6 +1113,7 @@
# if defined(VGP_ppc64_linux)
Int offB_GPR2 = offsetof(VexGuestPPC64State,guest_GPR2);
Int offB_LR = offsetof(VexGuestPPC64State,guest_LR);
+ Int offB_CIA = offsetof(VexGuestPPC64State,guest_CIA);
IRTemp old_R2 = newIRTemp( bb->tyenv, Ity_I64 );
IRTemp old_LR = newIRTemp( bb->tyenv, Ity_I64 );
/* Restore R2 */
@@ -1112,8 +1127,8 @@
blr (hence Ijk_Ret); so we should just mark this jump as Boring,
else one _Call will have resulted in two _Rets. */
bb->jumpkind = Ijk_Boring;
- bb->next = IRExpr_Binop(Iop_And64, IRExpr_RdTmp(old_LR), mkU64(~(3ULL)));
-
+ bb->next = IRExpr_Binop(Iop_And64, IRExpr_RdTmp(old_LR), mkU64(~(3ULL)));
+ bb->offsIP = offB_CIA;
# else
# error Platform is not TOC-afflicted, fortunately
# endif
@@ -1173,6 +1188,12 @@
nraddr_szB == 8 ? mkU64(0) : mkU32(0)
)
);
+# if defined(VGP_mips32_linux)
+ // t9 needs to be set to point to the start of the redirected function.
+ VgCallbackClosure* closure = (VgCallbackClosure*)closureV;
+ Int offB_GPR25 = offsetof(VexGuestMIPS32State,guest_r25);
+ addStmtToIRSB( bb, IRStmt_Put( offB_GPR25, mkU32( closure->readdr )) );
+# endif
# if defined(VG_PLAT_USES_PPCTOC)
{ VgCallbackClosure* closure = (VgCallbackClosure*)closureV;
addStmtToIRSB(
@@ -1209,6 +1230,11 @@
: IRExpr_Const(IRConst_U32( (UInt)closure->nraddr ))
)
);
+# if defined(VGP_mips32_linux)
+ // t9 needs to be set to point to the start of the redirected function.
+ Int offB_GPR25 = offsetof(VexGuestMIPS32State,guest_r25);
+ addStmtToIRSB( bb, IRStmt_Put( offB_GPR25, mkU32( closure->readdr )) );
+# endif
# if defined(VGP_ppc64_linux)
addStmtToIRSB(
bb,
@@ -1318,12 +1344,12 @@
if ((kind == T_Redir_Wrap || kind == T_Redir_Replace)
&& (VG_(clo_verbosity) >= 2 || VG_(clo_trace_redir))) {
Bool ok;
- Char name1[64] = "";
- Char name2[64] = "";
+ Char name1[512] = "";
+ Char name2[512] = "";
name1[0] = name2[0] = 0;
- ok = VG_(get_fnname_w_offset)(nraddr, name1, 64);
+ ok = VG_(get_fnname_w_offset)(nraddr, name1, 512);
if (!ok) VG_(strcpy)(name1, "???");
- ok = VG_(get_fnname_w_offset)(addr, name2, 64);
+ ok = VG_(get_fnname_w_offset)(addr, name2, 512);
if (!ok) VG_(strcpy)(name2, "???");
VG_(message)(Vg_DebugMsg,
"REDIR: 0x%llx (%s) redirected to 0x%llx (%s)\n",
@@ -1337,8 +1363,8 @@
/* If doing any code printing, print a basic block start marker */
if (VG_(clo_trace_flags) || debugging_translation) {
- Char fnname[64] = "UNKNOWN_FUNCTION";
- VG_(get_fnname_w_offset)(addr, fnname, 64);
+ Char fnname[512] = "UNKNOWN_FUNCTION";
+ VG_(get_fnname_w_offset)(addr, fnname, 512);
const UChar* objname = "UNKNOWN_OBJECT";
OffT objoff = 0;
DebugInfo* di = VG_(find_DebugInfo)( addr );
@@ -1348,7 +1374,7 @@
}
vg_assert(objname);
VG_(printf)(
- "==== SB %d (exec'd %lld) [tid %d] 0x%llx %s %s+0x%llx\n",
+ "==== SB %d (evchecks %lld) [tid %d] 0x%llx %s %s+0x%llx\n",
VG_(get_bbs_translated)(), bbs_done, (Int)tid, addr,
fnname, objname, (ULong)objoff
);
@@ -1394,6 +1420,7 @@
}
else
if ( (VG_(clo_trace_flags) > 0
+ && VG_(get_bbs_translated)() <= VG_(clo_trace_notabove)
&& VG_(get_bbs_translated)() >= VG_(clo_trace_notbelow) )) {
verbosity = VG_(clo_trace_flags);
}
@@ -1461,11 +1488,10 @@
vta.arch_host = vex_arch;
vta.archinfo_host = vex_archinfo;
vta.abiinfo_both = vex_abiinfo;
+ vta.callback_opaque = (void*)&closure;
vta.guest_bytes = (UChar*)ULong_to_Ptr(addr);
vta.guest_bytes_addr = (Addr64)addr;
- vta.callback_opaque = (void*)&closure;
vta.chase_into_ok = chase_into_ok;
- vta.preamble_function = preamble_fn;
vta.guest_extents = &vge;
vta.host_bytes = tmpbuf;
vta.host_bytes_size = N_TMPBUF;
@@ -1486,59 +1512,48 @@
IRSB*,VexGuestLayout*,VexGuestExtents*,
IRType,IRType)
= (IRSB*(*)(void*,IRSB*,VexGuestLayout*,VexGuestExtents*,IRType,IRType))f;
- vta.instrument1 = g;
+ vta.instrument1 = g;
}
/* No need for type kludgery here. */
- vta.instrument2 = need_to_handle_SP_assignment()
- ? vg_SP_update_pass
- : NULL;
- vta.finaltidy = VG_(needs).final_IR_tidy_pass
- ? VG_(tdict).tool_final_IR_tidy_pass
- : NULL;
- vta.needs_self_check = needs_self_check;
- vta.traceflags = verbosity;
+ vta.instrument2 = need_to_handle_SP_assignment()
+ ? vg_SP_update_pass
+ : NULL;
+ vta.finaltidy = VG_(needs).final_IR_tidy_pass
+ ? VG_(tdict).tool_final_IR_tidy_pass
+ : NULL;
+ vta.needs_self_check = needs_self_check;
+ vta.preamble_function = preamble_fn;
+ vta.traceflags = verbosity;
+ vta.addProfInc = VG_(clo_profile_flags) > 0
+ && kind != T_NoRedir;
- /* Set up the dispatch-return info. For archs without a link
- register, vex generates a jump back to the specified dispatch
- address. Else, it just generates a branch-to-LR. */
+ /* Set up the dispatch continuation-point info. If this is a
+ no-redir translation then it cannot be chained, and the chain-me
+ points are set to NULL to indicate that. The indir point must
+ also be NULL, since we can't allow this translation to do an
+ indir transfer -- that would take it back into the main
+ translation cache too.
-# if defined(VGA_x86) || defined(VGA_amd64)
- if (!allow_redirection) {
- /* It's a no-redir translation. Will be run with the
- nonstandard dispatcher VG_(run_a_noredir_translation) and so
- needs a nonstandard return point. */
- vta.dispatch_assisted
- = (void*) &VG_(run_a_noredir_translation__return_point);
- vta.dispatch_unassisted
- = vta.dispatch_assisted;
+ All this is because no-redir translations live outside the main
+ translation cache (in a secondary one) and chaining them would
+ involve more adminstrative complexity that isn't worth the
+ hassle, because we don't expect them to get used often. So
+ don't bother. */
+ if (allow_redirection) {
+ vta.disp_cp_chain_me_to_slowEP
+ = VG_(fnptr_to_fnentry)( &VG_(disp_cp_chain_me_to_slowEP) );
+ vta.disp_cp_chain_me_to_fastEP
+ = VG_(fnptr_to_fnentry)( &VG_(disp_cp_chain_me_to_fastEP) );
+ vta.disp_cp_xindir
+ = VG_(fnptr_to_fnentry)( &VG_(disp_cp_xindir) );
+ } else {
+ vta.disp_cp_chain_me_to_slowEP = NULL;
+ vta.disp_cp_chain_me_to_fastEP = NULL;
+ vta.disp_cp_xindir = NULL;
}
- else
- if (VG_(clo_profile_flags) > 0) {
- /* normal translation; although we're profiling. */
- vta.dispatch_assisted
- = (void*) &VG_(run_innerloop__dispatch_assisted_profiled);
- vta.dispatch_unassisted
- = (void*) &VG_(run_innerloop__dispatch_unassisted_profiled);
- }
- else {
- /* normal translation and we're not profiling (the normal case) */
- vta.dispatch_assisted
- = (void*) &VG_(run_innerloop__dispatch_assisted_unprofiled);
- vta.dispatch_unassisted
- = (void*) &VG_(run_innerloop__dispatch_unassisted_unprofiled);
- }
-
-# elif defined(VGA_ppc32) || defined(VGA_ppc64) \
- || defined(VGA_arm) || defined(VGA_s390x)
- /* See comment in libvex.h. This target uses a
- return-to-link-register scheme to get back to the dispatcher, so
- both fields are NULL. */
- vta.dispatch_assisted = NULL;
- vta.dispatch_unassisted = NULL;
-
-# else
-# error "Unknown arch"
-# endif
+ /* This doesn't involve chaining and so is always allowable. */
+ vta.disp_cp_xassisted
+ = VG_(fnptr_to_fnentry)( &VG_(disp_cp_xassisted) );
/* Sheesh. Finally, actually _do_ the translation! */
tres = LibVEX_Translate ( &vta );
@@ -1581,8 +1596,12 @@
nraddr,
(Addr)(&tmpbuf[0]),
tmpbuf_used,
- tres.n_sc_extents > 0 );
+ tres.n_sc_extents > 0,
+ tres.offs_profInc,
+ tres.n_guest_instrs,
+ vex_arch );
} else {
+ vg_assert(tres.offs_profInc == -1); /* -1 == unset */
VG_(add_to_unredir_transtab)( &vge,
nraddr,
(Addr)(&tmpbuf[0]),
diff --git a/main/coregrind/m_transtab.c b/main/coregrind/m_transtab.c
index fac0b1f..6eb169c 100644
--- a/main/coregrind/m_transtab.c
+++ b/main/coregrind/m_transtab.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -31,8 +31,10 @@
#include "pub_core_basics.h"
#include "pub_core_debuglog.h"
-#include "pub_core_machine.h" // For VG(machine_get_VexArchInfo)
+#include "pub_core_machine.h" // For VG_(machine_get_VexArchInfo)
#include "pub_core_libcbase.h"
+#include "pub_core_vki.h" // to keep pub_core_libproc.h happy, sigh
+#include "pub_core_libcproc.h" // VG_(invalidate_icache)
#include "pub_core_libcassert.h"
#include "pub_core_libcprint.h"
#include "pub_core_options.h"
@@ -40,12 +42,8 @@
#include "pub_core_transtab.h"
#include "pub_core_aspacemgr.h"
#include "pub_core_mallocfree.h" // VG_(out_of_memory_NORETURN)
-
-// JRS FIXME get rid of this somehow
-#if defined(VGP_arm_linux)
-# include "pub_core_vkiscnums.h" // __ARM_NR_cacheflush
-# include "pub_core_syscall.h" // VG_(do_syscallN)
-#endif
+#include "pub_core_xarray.h"
+#include "pub_core_dispatch.h" // For VG_(disp_cp*) addresses
/* #define DEBUG_TRANSTAB */
@@ -66,7 +64,7 @@
fits in a UShort, leaving room for 0xFFFF(EC2TTE_DELETED) to denote
'deleted') and it is strongly recommended not to change this.
65521 is the largest prime <= 65535. */
-#define N_TTES_PER_SECTOR /*30011*/ /*40009*/ 65521
+#define N_TTES_PER_SECTOR /*10007*/ /*30011*/ /*40009*/ 65521
/* Because each sector contains a hash table of TTEntries, we need to
specify the maximum allowable loading, after which the sector is
@@ -91,6 +89,46 @@
/*------------------ TYPES ------------------*/
+/* In edges ("to-me") in the graph created by chaining. */
+typedef
+ struct {
+ UInt from_sNo; /* sector number */
+ UInt from_tteNo; /* TTE number in given sector */
+ UInt from_offs; /* code offset from TCEntry::tcptr where the patch is */
+ Bool to_fastEP; /* Is the patch to a fast or slow entry point? */
+ }
+ InEdge;
+
+
+/* Out edges ("from-me") in the graph created by chaining. */
+typedef
+ struct {
+ UInt to_sNo; /* sector number */
+ UInt to_tteNo; /* TTE number in given sector */
+ UInt from_offs; /* code offset in owning translation where patch is */
+ }
+ OutEdge;
+
+
+#define N_FIXED_IN_EDGE_ARR 3
+typedef
+ struct {
+ UInt n_fixed; /* 0 .. N_FIXED_IN_EDGE_ARR */
+ InEdge fixed[N_FIXED_IN_EDGE_ARR];
+ XArray* var; /* XArray* of InEdgeArr */
+ }
+ InEdgeArr;
+
+#define N_FIXED_OUT_EDGE_ARR 2
+typedef
+ struct {
+ UInt n_fixed; /* 0 .. N_FIXED_OUT_EDGE_ARR */
+ OutEdge fixed[N_FIXED_OUT_EDGE_ARR];
+ XArray* var; /* XArray* of OutEdgeArr */
+ }
+ OutEdgeArr;
+
+
/* A translation-table entry. This indicates precisely which areas of
guest code are included in the translation, and contains all other
auxiliary info too. */
@@ -102,7 +140,7 @@
Count is an entry count for the translation and is
incremented by 1 every time the translation is used, if we
are profiling. */
- UInt count;
+ ULong count;
UShort weight;
/* Status of the slot. Note, we need to be able to do lazy
@@ -143,15 +181,121 @@
// sec->ec2tte[ tte2ec_ec[i] ][ tte2ec_ix[i] ]
// should be the index
// of this TTEntry in the containing Sector's tt array.
+
+ /* Admin information for chaining. 'in_edges' is a set of the
+ patch points which jump to this translation -- hence are
+ predecessors in the control flow graph. 'out_edges' points
+ to successors in the control flow graph -- translations to
+ which this one has a patched jump. In short these are just
+ backwards and forwards edges in the graph of patched-together
+ blocks. The 'in_edges' contain slightly more info, enough
+ that we can undo the chaining of each mentioned patch point.
+ The 'out_edges' list exists only so that we can visit the
+ 'in_edges' entries of all blocks we're patched through to, in
+ order to remove ourselves from then when we're deleted. */
+
+ /* A translation can disappear for two reasons:
+ 1. erased (as part of the oldest sector cleanup) when the
+ youngest sector is full.
+ 2. discarded due to calls to VG_(discard_translations).
+ VG_(discard_translations) sets the status of the
+ translation to 'Deleted'.
+ A.o., the gdbserver discards one or more translations
+ when a breakpoint is inserted or removed at an Addr,
+ or when single stepping mode is enabled/disabled
+ or when a translation is instrumented for gdbserver
+ (all the target jumps of this translation are
+ invalidated).
+
+ So, it is possible that the translation A to be patched
+ (to obtain a patched jump from A to B) is invalidated
+ after B is translated and before A is patched.
+ In case a translation is erased or discarded, the patching
+ cannot be done. VG_(tt_tc_do_chaining) and find_TTEntry_from_hcode
+ are checking the 'from' translation still exists before
+ doing the patching.
+
+ Is it safe to erase or discard the current translation E being
+ executed ? Amazing, but yes, it is safe.
+ Here is the explanation:
+
+ The translation E being executed can only be erased if a new
+ translation N is being done. A new translation is done only
+ if the host addr is a not yet patched jump to another
+ translation. In such a case, the guest address of N is
+ assigned to the PC in the VEX state. Control is returned
+ to the scheduler. N will be translated. This can erase the
+ translation E (in case of sector full). VG_(tt_tc_do_chaining)
+ will not do the chaining to a non found translation E.
+ The execution will continue at the current guest PC
+ (i.e. the translation N).
+ => it is safe to erase the current translation being executed.
+
+ The current translation E being executed can also be discarded
+ (e.g. by gdbserver). VG_(discard_translations) will mark
+ this translation E as Deleted, but the translation itself
+ is not erased. In particular, its host code can only
+ be overwritten or erased in case a new translation is done.
+ A new translation will only be done if a not yet translated
+ jump is to be executed. The execution of the Deleted translation
+ E will continue till a non patched jump is encountered.
+ This situation is then similar to the 'erasing' case above :
+ the current translation E can be erased or overwritten, as the
+ execution will continue at the new translation N.
+
+ */
+
+ /* It is possible, although very unlikely, that a block A has
+ more than one patched jump to block B. This could happen if
+ (eg) A finishes "jcond B; jmp B".
+
+ This means in turn that B's in_edges set can list A more than
+ once (twice in this example). However, each such entry must
+ have a different from_offs, since a patched jump can only
+ jump to one place at once (it's meaningless for it to have
+ multiple destinations.) IOW, the successor and predecessor
+ edges in the graph are not uniquely determined by a
+ TTEntry --> TTEntry pair, but rather by a
+ (TTEntry,offset) --> TTEntry triple.
+
+ If A has multiple edges to B then B will mention A multiple
+ times in its in_edges. To make things simpler, we then
+ require that A mentions B exactly the same number of times in
+ its out_edges. Furthermore, a matching out-in pair must have
+ the same offset (from_offs). This facilitates sanity
+ checking, and it facilitates establishing the invariant that
+ a out_edges set may not have duplicates when using the
+ equality defined by (TTEntry,offset). Hence the out_edges
+ and in_edges sets really do have both have set semantics.
+
+ eg if A has been patched to B at offsets 42 and 87 (in A)
+ then A.out_edges = { (B,42), (B,87) } (in any order)
+ and B.in_edges = { (A,42), (A,87) } (in any order)
+
+ Hence for each node pair P->Q in the graph, there's a 1:1
+ mapping between P.out_edges and Q.in_edges.
+ */
+ InEdgeArr in_edges;
+ OutEdgeArr out_edges;
}
TTEntry;
+/* A structure used for mapping host code addresses back to the
+ relevant TTEntry. Used when doing chaining, for finding the
+ TTEntry to which some arbitrary patch address belongs. */
+typedef
+ struct {
+ UChar* start;
+ UInt len;
+ UInt tteNo;
+ }
+ HostExtent;
+
/* Finally, a sector itself. Each sector contains an array of
TCEntries, which hold code, and an array of TTEntries, containing
all required administrative info. Profiling is supported using the
- TTEntry .count and .weight fields, if required. Each sector is
- independent in that no cross-sector references are allowed.
+ TTEntry .count and .weight fields, if required.
If the sector is not in use, all three pointers are NULL and
tt_n_inuse is zero.
@@ -181,6 +325,11 @@
Int ec2tte_size[ECLASS_N];
Int ec2tte_used[ECLASS_N];
UShort* ec2tte[ECLASS_N];
+
+ /* The host extents. The [start, +len) ranges are constructed
+ in strictly non-overlapping order, so we can binary search
+ them at any time. */
+ XArray* host_extents; /* XArray* of HostExtent */
}
Sector;
@@ -238,30 +387,6 @@
*/
/*global*/ __attribute__((aligned(16)))
FastCacheEntry VG_(tt_fast)[VG_TT_FAST_SIZE];
-/*
-#define TRANSTAB_BOGUS_GUEST_ADDR ((Addr)1)
-*/
-
-/* For profiling, we have a parallel array of pointers to .count
- fields in TT entries. Again, these pointers must be invalidated
- when translations disappear. A NULL pointer suffices to indicate
- an unused slot.
-
- When not profiling (the normal case, VG_(clo_profile_flags) == 0),
- all tt_fastN entries are set to NULL at startup and never read nor
- written after that.
-
- When profiling (VG_(clo_profile_flags) > 0), tt_fast and tt_fastN
- change together: if tt_fast[i].guest is TRANSTAB_BOGUS_GUEST_ADDR
- then the corresponding tt_fastN[i] must be null. If
- tt_fast[i].guest is any other value, then tt_fastN[i] *must* point
- to the .count field of the corresponding TT entry.
-
- tt_fast and tt_fastN are referred to from assembly code
- (dispatch.S).
-*/
-/*global*/ UInt* VG_(tt_fastN)[VG_TT_FAST_SIZE];
-
/* Make sure we're not used before initialisation. */
static Bool init_done = False;
@@ -270,27 +395,498 @@
/*------------------ STATS DECLS ------------------*/
/* Number of fast-cache updates and flushes done. */
-ULong n_fast_flushes = 0;
-ULong n_fast_updates = 0;
+static ULong n_fast_flushes = 0;
+static ULong n_fast_updates = 0;
/* Number of full lookups done. */
-ULong n_full_lookups = 0;
-ULong n_lookup_probes = 0;
+static ULong n_full_lookups = 0;
+static ULong n_lookup_probes = 0;
/* Number/osize/tsize of translations entered; also the number of
those for which self-checking was requested. */
-ULong n_in_count = 0;
-ULong n_in_osize = 0;
-ULong n_in_tsize = 0;
-ULong n_in_sc_count = 0;
+static ULong n_in_count = 0;
+static ULong n_in_osize = 0;
+static ULong n_in_tsize = 0;
+static ULong n_in_sc_count = 0;
/* Number/osize of translations discarded due to lack of space. */
-ULong n_dump_count = 0;
-ULong n_dump_osize = 0;
+static ULong n_dump_count = 0;
+static ULong n_dump_osize = 0;
/* Number/osize of translations discarded due to requests to do so. */
-ULong n_disc_count = 0;
-ULong n_disc_osize = 0;
+static ULong n_disc_count = 0;
+static ULong n_disc_osize = 0;
+
+
+/*-------------------------------------------------------------*/
+/*--- Misc ---*/
+/*-------------------------------------------------------------*/
+
+static void* ttaux_malloc ( HChar* tag, SizeT n )
+{
+ return VG_(arena_malloc)(VG_AR_TTAUX, tag, n);
+}
+
+static void ttaux_free ( void* p )
+{
+ VG_(arena_free)(VG_AR_TTAUX, p);
+}
+
+
+/*-------------------------------------------------------------*/
+/*--- Chaining support ---*/
+/*-------------------------------------------------------------*/
+
+static inline TTEntry* index_tte ( UInt sNo, UInt tteNo )
+{
+ vg_assert(sNo < N_SECTORS);
+ vg_assert(tteNo < N_TTES_PER_SECTOR);
+ Sector* s = §ors[sNo];
+ vg_assert(s->tt);
+ TTEntry* tte = &s->tt[tteNo];
+ vg_assert(tte->status == InUse);
+ return tte;
+}
+
+static void InEdge__init ( InEdge* ie )
+{
+ ie->from_sNo = -1; /* invalid */
+ ie->from_tteNo = 0;
+ ie->from_offs = 0;
+ ie->to_fastEP = False;
+}
+
+static void OutEdge__init ( OutEdge* oe )
+{
+ oe->to_sNo = -1; /* invalid */
+ oe->to_tteNo = 0;
+ oe->from_offs = 0;
+}
+
+static void TTEntry__init ( TTEntry* tte )
+{
+ VG_(memset)(tte, 0, sizeof(*tte));
+}
+
+static UWord InEdgeArr__size ( InEdgeArr* iea )
+{
+ if (iea->var) {
+ vg_assert(iea->n_fixed == 0);
+ return VG_(sizeXA)(iea->var);
+ } else {
+ vg_assert(iea->n_fixed <= N_FIXED_IN_EDGE_ARR);
+ return iea->n_fixed;
+ }
+}
+
+static void InEdgeArr__makeEmpty ( InEdgeArr* iea )
+{
+ if (iea->var) {
+ vg_assert(iea->n_fixed == 0);
+ VG_(deleteXA)(iea->var);
+ iea->var = NULL;
+ } else {
+ vg_assert(iea->n_fixed <= N_FIXED_IN_EDGE_ARR);
+ iea->n_fixed = 0;
+ }
+}
+
+static
+InEdge* InEdgeArr__index ( InEdgeArr* iea, UWord i )
+{
+ if (iea->var) {
+ vg_assert(iea->n_fixed == 0);
+ return (InEdge*)VG_(indexXA)(iea->var, i);
+ } else {
+ vg_assert(i < iea->n_fixed);
+ return &iea->fixed[i];
+ }
+}
+
+static
+void InEdgeArr__deleteIndex ( InEdgeArr* iea, UWord i )
+{
+ if (iea->var) {
+ vg_assert(iea->n_fixed == 0);
+ VG_(removeIndexXA)(iea->var, i);
+ } else {
+ vg_assert(i < iea->n_fixed);
+ for (; i+1 < iea->n_fixed; i++) {
+ iea->fixed[i] = iea->fixed[i+1];
+ }
+ iea->n_fixed--;
+ }
+}
+
+static
+void InEdgeArr__add ( InEdgeArr* iea, InEdge* ie )
+{
+ if (iea->var) {
+ vg_assert(iea->n_fixed == 0);
+ VG_(addToXA)(iea->var, ie);
+ } else {
+ vg_assert(iea->n_fixed <= N_FIXED_IN_EDGE_ARR);
+ if (iea->n_fixed == N_FIXED_IN_EDGE_ARR) {
+ /* The fixed array is full, so we have to initialise an
+ XArray and copy the fixed array into it. */
+ iea->var = VG_(newXA)(ttaux_malloc, "transtab.IEA__add",
+ ttaux_free,
+ sizeof(InEdge));
+ UWord i;
+ for (i = 0; i < iea->n_fixed; i++) {
+ VG_(addToXA)(iea->var, &iea->fixed[i]);
+ }
+ VG_(addToXA)(iea->var, ie);
+ iea->n_fixed = 0;
+ } else {
+ /* Just add to the fixed array. */
+ iea->fixed[iea->n_fixed++] = *ie;
+ }
+ }
+}
+
+static UWord OutEdgeArr__size ( OutEdgeArr* oea )
+{
+ if (oea->var) {
+ vg_assert(oea->n_fixed == 0);
+ return VG_(sizeXA)(oea->var);
+ } else {
+ vg_assert(oea->n_fixed <= N_FIXED_OUT_EDGE_ARR);
+ return oea->n_fixed;
+ }
+}
+
+static void OutEdgeArr__makeEmpty ( OutEdgeArr* oea )
+{
+ if (oea->var) {
+ vg_assert(oea->n_fixed == 0);
+ VG_(deleteXA)(oea->var);
+ oea->var = NULL;
+ } else {
+ vg_assert(oea->n_fixed <= N_FIXED_OUT_EDGE_ARR);
+ oea->n_fixed = 0;
+ }
+}
+
+static
+OutEdge* OutEdgeArr__index ( OutEdgeArr* oea, UWord i )
+{
+ if (oea->var) {
+ vg_assert(oea->n_fixed == 0);
+ return (OutEdge*)VG_(indexXA)(oea->var, i);
+ } else {
+ vg_assert(i < oea->n_fixed);
+ return &oea->fixed[i];
+ }
+}
+
+static
+void OutEdgeArr__deleteIndex ( OutEdgeArr* oea, UWord i )
+{
+ if (oea->var) {
+ vg_assert(oea->n_fixed == 0);
+ VG_(removeIndexXA)(oea->var, i);
+ } else {
+ vg_assert(i < oea->n_fixed);
+ for (; i+1 < oea->n_fixed; i++) {
+ oea->fixed[i] = oea->fixed[i+1];
+ }
+ oea->n_fixed--;
+ }
+}
+
+static
+void OutEdgeArr__add ( OutEdgeArr* oea, OutEdge* oe )
+{
+ if (oea->var) {
+ vg_assert(oea->n_fixed == 0);
+ VG_(addToXA)(oea->var, oe);
+ } else {
+ vg_assert(oea->n_fixed <= N_FIXED_OUT_EDGE_ARR);
+ if (oea->n_fixed == N_FIXED_OUT_EDGE_ARR) {
+ /* The fixed array is full, so we have to initialise an
+ XArray and copy the fixed array into it. */
+ oea->var = VG_(newXA)(ttaux_malloc, "transtab.OEA__add",
+ ttaux_free,
+ sizeof(OutEdge));
+ UWord i;
+ for (i = 0; i < oea->n_fixed; i++) {
+ VG_(addToXA)(oea->var, &oea->fixed[i]);
+ }
+ VG_(addToXA)(oea->var, oe);
+ oea->n_fixed = 0;
+ } else {
+ /* Just add to the fixed array. */
+ oea->fixed[oea->n_fixed++] = *oe;
+ }
+ }
+}
+
+static
+Int HostExtent__cmpOrd ( void* v1, void* v2 )
+{
+ HostExtent* hx1 = (HostExtent*)v1;
+ HostExtent* hx2 = (HostExtent*)v2;
+ if (hx1->start + hx1->len <= hx2->start) return -1;
+ if (hx2->start + hx2->len <= hx1->start) return 1;
+ return 0; /* partial overlap */
+}
+
+static __attribute__((noinline))
+Bool find_TTEntry_from_hcode( /*OUT*/UInt* from_sNo,
+ /*OUT*/UInt* from_tteNo,
+ void* hcode )
+{
+ Int i;
+
+ /* Search order logic copied from VG_(search_transtab). */
+ for (i = 0; i < N_SECTORS; i++) {
+ Int sno = sector_search_order[i];
+ if (UNLIKELY(sno == -1))
+ return False; /* run out of sectors to search */
+
+ Sector* sec = §ors[sno];
+ XArray* /* of HostExtent */ host_extents = sec->host_extents;
+ vg_assert(host_extents);
+
+ HostExtent key;
+ VG_(memset)(&key, 0, sizeof(key));
+ key.start = hcode;
+ key.len = 1;
+ Word firstW = -1, lastW = -1;
+ Bool found = VG_(lookupXA_UNSAFE)(
+ host_extents, &key, &firstW, &lastW,
+ (Int(*)(void*,void*))HostExtent__cmpOrd
+ );
+ vg_assert(firstW == lastW); // always true, even if not found
+ if (found) {
+ HostExtent* hx = VG_(indexXA)(host_extents, firstW);
+ UInt tteNo = hx->tteNo;
+ /* Do some additional sanity checks. */
+ vg_assert(tteNo <= N_TTES_PER_SECTOR);
+ /* Entry might have been invalidated. Consider this
+ as not found. */
+ if (sec->tt[tteNo].status == Deleted)
+ return False;
+ vg_assert(sec->tt[tteNo].status == InUse);
+ /* Can only half check that the found TTEntry contains hcode,
+ due to not having a length value for the hcode in the
+ TTEntry. */
+ vg_assert((UChar*)sec->tt[tteNo].tcptr <= (UChar*)hcode);
+ /* Looks plausible */
+ *from_sNo = sno;
+ *from_tteNo = (UInt)tteNo;
+ return True;
+ }
+ }
+ return False;
+}
+
+
+/* Figure out whether or not hcode is jitted code present in the main
+ code cache (but not in the no-redir cache). Used for sanity
+ checking. */
+static Bool is_in_the_main_TC ( void* hcode )
+{
+ Int i, sno;
+ for (i = 0; i < N_SECTORS; i++) {
+ sno = sector_search_order[i];
+ if (sno == -1)
+ break; /* run out of sectors to search */
+ if ((UChar*)hcode >= (UChar*)sectors[sno].tc
+ && (UChar*)hcode <= (UChar*)sectors[sno].tc_next
+ + sizeof(ULong) - 1)
+ return True;
+ }
+ return False;
+}
+
+
+/* Fulfill a chaining request, and record admin info so we
+ can undo it later, if required.
+*/
+void VG_(tt_tc_do_chaining) ( void* from__patch_addr,
+ UInt to_sNo,
+ UInt to_tteNo,
+ Bool to_fastEP )
+{
+ /* Get the CPU info established at startup. */
+ VexArch vex_arch = VexArch_INVALID;
+ VG_(machine_get_VexArchInfo)( &vex_arch, NULL );
+
+ // host_code is where we're patching to. So it needs to
+ // take into account, whether we're jumping to the slow
+ // or fast entry point. By definition, the fast entry point
+ // is exactly one event check's worth of code along from
+ // the slow (tcptr) entry point.
+ TTEntry* to_tte = index_tte(to_sNo, to_tteNo);
+ void* host_code = ((UChar*)to_tte->tcptr)
+ + (to_fastEP ? LibVEX_evCheckSzB(vex_arch) : 0);
+
+ // stay sane -- the patch point (dst) is in this sector's code cache
+ vg_assert( (UChar*)host_code >= (UChar*)sectors[to_sNo].tc );
+ vg_assert( (UChar*)host_code <= (UChar*)sectors[to_sNo].tc_next
+ + sizeof(ULong) - 1 );
+
+ /* Find the TTEntry for the from__ code. This isn't simple since
+ we only know the patch address, which is going to be somewhere
+ inside the from_ block. */
+ UInt from_sNo = (UInt)-1;
+ UInt from_tteNo = (UInt)-1;
+ Bool from_found
+ = find_TTEntry_from_hcode( &from_sNo, &from_tteNo,
+ from__patch_addr );
+ if (!from_found) {
+ // The from code might have been discarded due to sector re-use
+ // or marked Deleted due to translation invalidation.
+ // In such a case, don't do the chaining.
+ VG_(debugLog)(1,"transtab",
+ "host code %p not found (discarded? sector recycled?)"
+ " => no chaining done\n",
+ from__patch_addr);
+ return;
+ }
+
+ TTEntry* from_tte = index_tte(from_sNo, from_tteNo);
+
+ /* Get VEX to do the patching itself. We have to hand it off
+ since it is host-dependent. */
+ VexInvalRange vir
+ = LibVEX_Chain(
+ vex_arch,
+ from__patch_addr,
+ VG_(fnptr_to_fnentry)(
+ to_fastEP ? &VG_(disp_cp_chain_me_to_fastEP)
+ : &VG_(disp_cp_chain_me_to_slowEP)),
+ (void*)host_code
+ );
+ VG_(invalidate_icache)( (void*)vir.start, vir.len );
+
+ /* Now do the tricky bit -- update the ch_succs and ch_preds info
+ for the two translations involved, so we can undo the chaining
+ later, which we will have to do if the to_ block gets removed
+ for whatever reason. */
+
+ /* This is the new from_ -> to_ link to add. */
+ InEdge ie;
+ InEdge__init(&ie);
+ ie.from_sNo = from_sNo;
+ ie.from_tteNo = from_tteNo;
+ ie.to_fastEP = to_fastEP;
+ HWord from_offs = (HWord)( (UChar*)from__patch_addr
+ - (UChar*)from_tte->tcptr );
+ vg_assert(from_offs < 100000/* let's say */);
+ ie.from_offs = (UInt)from_offs;
+
+ /* This is the new to_ -> from_ backlink to add. */
+ OutEdge oe;
+ OutEdge__init(&oe);
+ oe.to_sNo = to_sNo;
+ oe.to_tteNo = to_tteNo;
+ oe.from_offs = (UInt)from_offs;
+
+ /* Add .. */
+ InEdgeArr__add(&to_tte->in_edges, &ie);
+ OutEdgeArr__add(&from_tte->out_edges, &oe);
+}
+
+
+/* Unchain one patch, as described by the specified InEdge. For
+ sanity check purposes only (to check that the patched location is
+ as expected) it also requires the fast and slow entry point
+ addresses of the destination block (that is, the block that owns
+ this InEdge). */
+__attribute__((noinline))
+static void unchain_one ( VexArch vex_arch,
+ InEdge* ie,
+ void* to_fastEPaddr, void* to_slowEPaddr )
+{
+ vg_assert(ie);
+ TTEntry* tte
+ = index_tte(ie->from_sNo, ie->from_tteNo);
+ UChar* place_to_patch
+ = ((HChar*)tte->tcptr) + ie->from_offs;
+ UChar* disp_cp_chain_me
+ = VG_(fnptr_to_fnentry)(
+ ie->to_fastEP ? &VG_(disp_cp_chain_me_to_fastEP)
+ : &VG_(disp_cp_chain_me_to_slowEP)
+ );
+ UChar* place_to_jump_to_EXPECTED
+ = ie->to_fastEP ? to_fastEPaddr : to_slowEPaddr;
+
+ // stay sane: both src and dst for this unchaining are
+ // in the main code cache
+ vg_assert( is_in_the_main_TC(place_to_patch) ); // src
+ vg_assert( is_in_the_main_TC(place_to_jump_to_EXPECTED) ); // dst
+ // dst check is ok because LibVEX_UnChain checks that
+ // place_to_jump_to_EXPECTED really is the current dst, and
+ // asserts if it isn't.
+ VexInvalRange vir
+ = LibVEX_UnChain( vex_arch, place_to_patch,
+ place_to_jump_to_EXPECTED, disp_cp_chain_me );
+ VG_(invalidate_icache)( (void*)vir.start, vir.len );
+}
+
+
+/* The specified block is about to be deleted. Update the preds and
+ succs of its associated blocks accordingly. This includes undoing
+ any chained jumps to this block. */
+static
+void unchain_in_preparation_for_deletion ( VexArch vex_arch,
+ UInt here_sNo, UInt here_tteNo )
+{
+ if (0)
+ VG_(printf)("QQQ unchain_in_prep %u.%u\n", here_sNo, here_tteNo);
+ UWord i, j, n, m;
+ Int evCheckSzB = LibVEX_evCheckSzB(vex_arch);
+ TTEntry* here_tte = index_tte(here_sNo, here_tteNo);
+ vg_assert(here_tte->status == InUse);
+
+ /* Visit all InEdges owned by here_tte. */
+ n = InEdgeArr__size(&here_tte->in_edges);
+ for (i = 0; i < n; i++) {
+ InEdge* ie = InEdgeArr__index(&here_tte->in_edges, i);
+ // Undo the chaining.
+ UChar* here_slow_EP = (UChar*)here_tte->tcptr;
+ UChar* here_fast_EP = here_slow_EP + evCheckSzB;
+ unchain_one(vex_arch, ie, here_fast_EP, here_slow_EP);
+ // Find the corresponding entry in the "from" node's out_edges,
+ // and remove it.
+ TTEntry* from_tte = index_tte(ie->from_sNo, ie->from_tteNo);
+ m = OutEdgeArr__size(&from_tte->out_edges);
+ vg_assert(m > 0); // it must have at least one entry
+ for (j = 0; j < m; j++) {
+ OutEdge* oe = OutEdgeArr__index(&from_tte->out_edges, j);
+ if (oe->to_sNo == here_sNo && oe->to_tteNo == here_tteNo
+ && oe->from_offs == ie->from_offs)
+ break;
+ }
+ vg_assert(j < m); // "oe must be findable"
+ OutEdgeArr__deleteIndex(&from_tte->out_edges, j);
+ }
+
+ /* Visit all OutEdges owned by here_tte. */
+ n = OutEdgeArr__size(&here_tte->out_edges);
+ for (i = 0; i < n; i++) {
+ OutEdge* oe = OutEdgeArr__index(&here_tte->out_edges, i);
+ // Find the corresponding entry in the "to" node's in_edges,
+ // and remove it.
+ TTEntry* to_tte = index_tte(oe->to_sNo, oe->to_tteNo);
+ m = InEdgeArr__size(&to_tte->in_edges);
+ vg_assert(m > 0); // it must have at least one entry
+ for (j = 0; j < m; j++) {
+ InEdge* ie = InEdgeArr__index(&to_tte->in_edges, j);
+ if (ie->from_sNo == here_sNo && ie->from_tteNo == here_tteNo
+ && ie->from_offs == oe->from_offs)
+ break;
+ }
+ vg_assert(j < m); // "ie must be findable"
+ InEdgeArr__deleteIndex(&to_tte->in_edges, j);
+ }
+
+ InEdgeArr__makeEmpty(&here_tte->in_edges);
+ OutEdgeArr__makeEmpty(&here_tte->out_edges);
+}
/*-------------------------------------------------------------*/
@@ -398,12 +994,12 @@
old_sz = sec->ec2tte_size[ec];
old_ar = sec->ec2tte[ec];
new_sz = old_sz==0 ? 8 : old_sz<64 ? 2*old_sz : (3*old_sz)/2;
- new_ar = VG_(arena_malloc)(VG_AR_TTAUX, "transtab.aECN.1",
- new_sz * sizeof(UShort));
+ new_ar = ttaux_malloc("transtab.aECN.1",
+ new_sz * sizeof(UShort));
for (i = 0; i < old_sz; i++)
new_ar[i] = old_ar[i];
if (old_ar)
- VG_(arena_free)(VG_AR_TTAUX, old_ar);
+ ttaux_free(old_ar);
sec->ec2tte_size[ec] = new_sz;
sec->ec2tte[ec] = new_ar;
@@ -575,7 +1171,6 @@
/* forwards */
static Bool sanity_check_redir_tt_tc ( void );
-static Bool sanity_check_fastcache ( void );
static Bool sanity_check_sector_search_order ( void )
{
@@ -630,8 +1225,6 @@
}
if ( !sanity_check_redir_tt_tc() )
return False;
- if ( !sanity_check_fastcache() )
- return False;
if ( !sanity_check_sector_search_order() )
return False;
return True;
@@ -669,13 +1262,11 @@
return k32 % N_TTES_PER_SECTOR;
}
-static void setFastCacheEntry ( Addr64 key, ULong* tcptr, UInt* count )
+static void setFastCacheEntry ( Addr64 key, ULong* tcptr )
{
UInt cno = (UInt)VG_TT_FAST_HASH(key);
VG_(tt_fast)[cno].guest = (Addr)key;
VG_(tt_fast)[cno].host = (Addr)tcptr;
- if (VG_(clo_profile_flags) > 0)
- VG_(tt_fastN)[cno] = count;
n_fast_updates++;
/* This shouldn't fail. It should be assured by m_translate
which should reject any attempt to make translation of code
@@ -683,23 +1274,7 @@
vg_assert(VG_(tt_fast)[cno].guest != TRANSTAB_BOGUS_GUEST_ADDR);
}
-/* Invalidate the fast cache's counter array, VG_(tt_fastN). */
-static void invalidateFastNCache ( void )
-{
- UInt j;
- vg_assert(VG_TT_FAST_SIZE > 0 && (VG_TT_FAST_SIZE % 4) == 0);
- for (j = 0; j < VG_TT_FAST_SIZE; j += 4) {
- VG_(tt_fastN)[j+0] = NULL;
- VG_(tt_fastN)[j+1] = NULL;
- VG_(tt_fastN)[j+2] = NULL;
- VG_(tt_fastN)[j+3] = NULL;
- }
- vg_assert(j == VG_TT_FAST_SIZE);
-}
-
-/* Invalidate the fast cache VG_(tt_fast). If profiling, also
- invalidate the fast cache's counter array VG_(tt_fastN), otherwise
- don't touch it. */
+/* Invalidate the fast cache VG_(tt_fast). */
static void invalidateFastCache ( void )
{
UInt j;
@@ -713,41 +1288,14 @@
VG_(tt_fast)[j+3].guest = TRANSTAB_BOGUS_GUEST_ADDR;
}
- if (VG_(clo_profile_flags) > 0)
- invalidateFastNCache();
-
vg_assert(j == VG_TT_FAST_SIZE);
n_fast_flushes++;
}
-static Bool sanity_check_fastcache ( void )
-{
- UInt j;
- if (0) VG_(printf)("sanity check fastcache\n");
- if (VG_(clo_profile_flags) > 0) {
- /* profiling */
- for (j = 0; j < VG_TT_FAST_SIZE; j++) {
- if (VG_(tt_fastN)[j] == NULL
- && VG_(tt_fast)[j].guest != TRANSTAB_BOGUS_GUEST_ADDR)
- return False;
- if (VG_(tt_fastN)[j] != NULL
- && VG_(tt_fast)[j].guest == TRANSTAB_BOGUS_GUEST_ADDR)
- return False;
- }
- } else {
- /* not profiling */
- for (j = 0; j < VG_TT_FAST_SIZE; j++) {
- if (VG_(tt_fastN)[j] != NULL)
- return False;
- }
- }
- return True;
-}
-
static void initialiseSector ( Int sno )
{
- Int i;
- SysRes sres;
+ Int i;
+ SysRes sres;
Sector* sec;
vg_assert(isValidSector(sno));
@@ -768,6 +1316,7 @@
vg_assert(sec->ec2tte_used[i] == 0);
vg_assert(sec->ec2tte[i] == NULL);
}
+ vg_assert(sec->host_extents == NULL);
VG_(debugLog)(1,"transtab", "allocate sector %d\n", sno);
@@ -793,6 +1342,12 @@
sec->tt[i].n_tte2ec = 0;
}
+ /* Set up the host_extents array. */
+ sec->host_extents
+ = VG_(newXA)(ttaux_malloc, "transtab.initialiseSector(host_extents)",
+ ttaux_free,
+ sizeof(HostExtent));
+
/* Add an entry in the sector_search_order */
for (i = 0; i < N_SECTORS; i++) {
if (sector_search_order[i] == -1)
@@ -812,7 +1367,11 @@
vg_assert(sec->tc_next != NULL);
n_dump_count += sec->tt_n_inuse;
+ VexArch vex_arch = VexArch_INVALID;
+ VG_(machine_get_VexArchInfo)( &vex_arch, NULL );
+
/* Visit each just-about-to-be-abandoned translation. */
+ if (0) VG_(printf)("QQQ unlink-entire-sector: %d START\n", sno);
for (i = 0; i < N_TTES_PER_SECTOR; i++) {
if (sec->tt[i].status == InUse) {
vg_assert(sec->tt[i].n_tte2ec >= 1);
@@ -824,12 +1383,14 @@
sec->tt[i].entry,
sec->tt[i].vge );
}
+ unchain_in_preparation_for_deletion(vex_arch, sno, i);
} else {
vg_assert(sec->tt[i].n_tte2ec == 0);
}
sec->tt[i].status = Empty;
sec->tt[i].n_tte2ec = 0;
}
+ if (0) VG_(printf)("QQQ unlink-entire-sector: %d END\n", sno);
/* Free up the eclass structures. */
for (i = 0; i < ECLASS_N; i++) {
@@ -838,13 +1399,18 @@
vg_assert(sec->ec2tte[i] == NULL);
} else {
vg_assert(sec->ec2tte[i] != NULL);
- VG_(arena_free)(VG_AR_TTAUX, sec->ec2tte[i]);
+ ttaux_free(sec->ec2tte[i]);
sec->ec2tte[i] = NULL;
sec->ec2tte_size[i] = 0;
sec->ec2tte_used[i] = 0;
}
}
+ /* Empty out the host extents array. */
+ vg_assert(sec->host_extents != NULL);
+ VG_(dropTailXA)(sec->host_extents, VG_(sizeXA)(sec->host_extents));
+ vg_assert(VG_(sizeXA)(sec->host_extents) == 0);
+
/* Sanity check: ensure it is already in
sector_search_order[]. */
for (i = 0; i < N_SECTORS; i++) {
@@ -867,54 +1433,6 @@
}
}
-static void invalidate_icache ( void *ptr, Int nbytes )
-{
-# if defined(VGA_ppc32) || defined(VGA_ppc64)
- Addr startaddr = (Addr) ptr;
- Addr endaddr = startaddr + nbytes;
- Addr cls;
- Addr addr;
- VexArchInfo vai;
-
- if (nbytes == 0) return;
- vg_assert(nbytes > 0);
-
- VG_(machine_get_VexArchInfo)( NULL, &vai );
- cls = vai.ppc_cache_line_szB;
-
- /* Stay sane .. */
- vg_assert(cls == 32 || cls == 64 || cls == 128);
-
- startaddr &= ~(cls - 1);
- for (addr = startaddr; addr < endaddr; addr += cls) {
- __asm__ __volatile__("dcbst 0,%0" : : "r" (addr));
- }
- __asm__ __volatile__("sync");
- for (addr = startaddr; addr < endaddr; addr += cls) {
- __asm__ __volatile__("icbi 0,%0" : : "r" (addr));
- }
- __asm__ __volatile__("sync; isync");
-
-# elif defined(VGA_x86)
- /* no need to do anything, hardware provides coherence */
-
-# elif defined(VGA_amd64)
- /* no need to do anything, hardware provides coherence */
-
-# elif defined(VGA_s390x)
- /* no need to do anything, hardware provides coherence */
-
-# elif defined(VGP_arm_linux)
- /* ARM cache flushes are privileged, so we must defer to the kernel. */
- Addr startaddr = (Addr) ptr;
- Addr endaddr = startaddr + nbytes;
- VG_(do_syscall2)(__NR_ARM_cacheflush, startaddr, endaddr);
-
-# else
-# error "Unknown ARCH"
-# endif
-}
-
/* Add a translation of vge to TT/TC. The translation is temporarily
in code[0 .. code_len-1].
@@ -926,7 +1444,10 @@
Addr64 entry,
AddrH code,
UInt code_len,
- Bool is_self_checking )
+ Bool is_self_checking,
+ Int offs_profInc,
+ UInt n_guest_instrs,
+ VexArch arch_host )
{
Int tcAvailQ, reqdQ, y, i;
ULong *tcptr, *tcptr2;
@@ -939,6 +1460,9 @@
/* 60000: should agree with N_TMPBUF in m_translate.c. */
vg_assert(code_len > 0 && code_len < 60000);
+ /* Generally stay sane */
+ vg_assert(n_guest_instrs < 200); /* it can be zero, tho */
+
if (0)
VG_(printf)("add_to_transtab(entry = 0x%llx, len = %d)\n",
entry, code_len);
@@ -1002,13 +1526,10 @@
dstP = (UChar*)tcptr;
srcP = (UChar*)code;
- for (i = 0; i < code_len; i++)
- dstP[i] = srcP[i];
+ VG_(memcpy)(dstP, srcP, code_len);
sectors[y].tc_next += reqdQ;
sectors[y].tt_n_inuse++;
- invalidate_icache( dstP, code_len );
-
/* more paranoia */
tcptr2 = sectors[y].tc_next;
vg_assert(tcptr2 >= §ors[y].tc[0]);
@@ -1027,15 +1548,45 @@
i = 0;
}
+ TTEntry__init(§ors[y].tt[i]);
sectors[y].tt[i].status = InUse;
sectors[y].tt[i].tcptr = tcptr;
sectors[y].tt[i].count = 0;
- sectors[y].tt[i].weight = 1;
+ sectors[y].tt[i].weight = n_guest_instrs == 0 ? 1 : n_guest_instrs;
sectors[y].tt[i].vge = *vge;
sectors[y].tt[i].entry = entry;
+ /* Patch in the profile counter location, if necessary. */
+ if (offs_profInc != -1) {
+ vg_assert(offs_profInc >= 0 && offs_profInc < code_len);
+ VexInvalRange vir
+ = LibVEX_PatchProfInc( arch_host,
+ dstP + offs_profInc,
+ §ors[y].tt[i].count );
+ VG_(invalidate_icache)( (void*)vir.start, vir.len );
+ }
+
+ VG_(invalidate_icache)( dstP, code_len );
+
+ /* Add this entry to the host_extents map, checking that we're
+ adding in order. */
+ { HostExtent hx;
+ hx.start = (UChar*)tcptr;
+ hx.len = code_len;
+ hx.tteNo = i;
+ vg_assert(hx.len > 0); /* bsearch fails w/ zero length entries */
+ XArray* hx_array = sectors[y].host_extents;
+ vg_assert(hx_array);
+ Word n = VG_(sizeXA)(hx_array);
+ if (n > 0) {
+ HostExtent* hx_prev = (HostExtent*)VG_(indexXA)(hx_array, n-1);
+ vg_assert(hx_prev->start + hx_prev->len <= hx.start);
+ }
+ VG_(addToXA)(hx_array, &hx);
+ }
+
/* Update the fast-cache. */
- setFastCacheEntry( entry, tcptr, §ors[y].tt[i].count );
+ setFastCacheEntry( entry, tcptr );
/* Note the eclass numbers for this translation. */
upd_eclasses_after_add( §ors[y], i );
@@ -1046,7 +1597,9 @@
requested, a successful search can also cause the fast-caches to be
updated.
*/
-Bool VG_(search_transtab) ( /*OUT*/AddrH* result,
+Bool VG_(search_transtab) ( /*OUT*/AddrH* res_hcode,
+ /*OUT*/UInt* res_sNo,
+ /*OUT*/UInt* res_tteNo,
Addr64 guest_addr,
Bool upd_cache )
{
@@ -1076,10 +1629,13 @@
/* found it */
if (upd_cache)
setFastCacheEntry(
- guest_addr, sectors[sno].tt[k].tcptr,
- §ors[sno].tt[k].count );
- if (result)
- *result = (AddrH)sectors[sno].tt[k].tcptr;
+ guest_addr, sectors[sno].tt[k].tcptr );
+ if (res_hcode)
+ *res_hcode = (AddrH)sectors[sno].tt[k].tcptr;
+ if (res_sNo)
+ *res_sNo = sno;
+ if (res_tteNo)
+ *res_tteNo = k;
/* pull this one one step closer to the front. For large
apps this more or less halves the number of required
probes. */
@@ -1147,16 +1703,23 @@
/* Delete a tt entry, and update all the eclass data accordingly. */
-static void delete_tte ( /*MOD*/Sector* sec, Int tteno )
+static void delete_tte ( /*MOD*/Sector* sec, UInt secNo, Int tteno,
+ VexArch vex_arch )
{
Int i, ec_num, ec_idx;
TTEntry* tte;
+ /* sec and secNo are mutually redundant; cross-check. */
+ vg_assert(sec == §ors[secNo]);
+
vg_assert(tteno >= 0 && tteno < N_TTES_PER_SECTOR);
tte = &sec->tt[tteno];
vg_assert(tte->status == InUse);
vg_assert(tte->n_tte2ec >= 1 && tte->n_tte2ec <= 3);
+ /* Unchain .. */
+ unchain_in_preparation_for_deletion(vex_arch, secNo, tteno);
+
/* Deal with the ec-to-tte links first. */
for (i = 0; i < tte->n_tte2ec; i++) {
ec_num = (Int)tte->tte2ec_ec[i];
@@ -1192,9 +1755,10 @@
only consider translations in the specified eclass. */
static
-Bool delete_translations_in_sector_eclass ( /*MOD*/Sector* sec,
+Bool delete_translations_in_sector_eclass ( /*MOD*/Sector* sec, UInt secNo,
Addr64 guest_start, ULong range,
- Int ec )
+ Int ec,
+ VexArch vex_arch )
{
Int i;
UShort tteno;
@@ -1218,7 +1782,7 @@
if (overlaps( guest_start, range, &tte->vge )) {
anyDeld = True;
- delete_tte( sec, (Int)tteno );
+ delete_tte( sec, secNo, (Int)tteno, vex_arch );
}
}
@@ -1231,8 +1795,9 @@
slow way, by inspecting all translations in sec. */
static
-Bool delete_translations_in_sector ( /*MOD*/Sector* sec,
- Addr64 guest_start, ULong range )
+Bool delete_translations_in_sector ( /*MOD*/Sector* sec, UInt secNo,
+ Addr64 guest_start, ULong range,
+ VexArch vex_arch )
{
Int i;
Bool anyDeld = False;
@@ -1241,7 +1806,7 @@
if (sec->tt[i].status == InUse
&& overlaps( guest_start, range, &sec->tt[i].vge )) {
anyDeld = True;
- delete_tte( sec, i );
+ delete_tte( sec, secNo, i, vex_arch );
}
}
@@ -1271,6 +1836,9 @@
if (range == 0)
return;
+ VexArch vex_arch = VexArch_INVALID;
+ VG_(machine_get_VexArchInfo)( &vex_arch, NULL );
+
/* There are two different ways to do this.
If the range fits within a single address-range equivalence
@@ -1310,9 +1878,13 @@
if (sec->tc == NULL)
continue;
anyDeleted |= delete_translations_in_sector_eclass(
- sec, guest_start, range, ec );
+ sec, sno, guest_start, range, ec,
+ vex_arch
+ );
anyDeleted |= delete_translations_in_sector_eclass(
- sec, guest_start, range, ECLASS_MISC );
+ sec, sno, guest_start, range, ECLASS_MISC,
+ vex_arch
+ );
}
} else {
@@ -1327,7 +1899,7 @@
if (sec->tc == NULL)
continue;
anyDeleted |= delete_translations_in_sector(
- sec, guest_start, range );
+ sec, sno, guest_start, range, vex_arch );
}
}
@@ -1483,7 +2055,7 @@
for (j = 0; j < code_len; j++)
dstP[j] = srcP[j];
- invalidate_icache( dstP, code_len );
+ VG_(invalidate_icache)( dstP, code_len );
unredir_tt[i].inUse = True;
unredir_tt[i].vge = *vge;
@@ -1573,18 +2145,15 @@
sectors[i].ec2tte_used[j] = 0;
sectors[i].ec2tte[j] = NULL;
}
+ sectors[i].host_extents = NULL;
}
/* Initialise the sector_search_order hint table. */
for (i = 0; i < N_SECTORS; i++)
sector_search_order[i] = -1;
- /* Initialise the fast caches. If not profiling (the usual case),
- we have to explicitly invalidate the fastN cache as
- invalidateFastCache() won't do that for us. */
+ /* Initialise the fast cache. */
invalidateFastCache();
- if (VG_(clo_profile_flags) == 0)
- invalidateFastNCache();
/* and the unredir tt/tc */
init_unredir_tt_tc();
diff --git a/main/coregrind/m_ume/elf.c b/main/coregrind/m_ume/elf.c
index d4732ab..4cc4df6 100644
--- a/main/coregrind/m_ume/elf.c
+++ b/main/coregrind/m_ume/elf.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -43,7 +43,6 @@
#include "pub_core_mallocfree.h" // VG_(malloc), VG_(free)
#include "pub_core_syscall.h" // VG_(strerror)
#include "pub_core_ume.h" // self
-#include "pub_tool_libcproc.h" // VG_(getenv)
#include "priv_ume.h"
@@ -394,18 +393,7 @@
if (iph->p_type != PT_LOAD || iph->p_memsz == 0)
continue;
-#ifdef ANDROID
- // On older versions of Android, the first LOAD segment of
- // /system/bin/linker has vaddr=0, memsz=0, but subsequent
- // segments start at 0xb0001000.
- //
- // On newer versions of Android, the linker is ET_DYN and
- // we don't have to worry about iph->p_vaddr
- if (!baseaddr_set
- && (iph->p_vaddr || (interp->e.e_type == ET_DYN))) {
-#else
if (!baseaddr_set) {
-#endif
interp_addr = iph->p_vaddr;
/* interp_align = iph->p_align; */ /* UNUSED */
baseaddr_set = 1;
@@ -498,16 +486,8 @@
VG_(free)(interp->p);
VG_(free)(interp);
- } else {
- Char *exit_if_static = VG_(getenv)("VALGRIND_EXIT_IF_STATIC");
- if (exit_if_static && VG_(strcmp)(exit_if_static, "0") != 0) {
- VG_(printf)("******* You are running Valgrind on a static binary: %s\n",
- name);
- VG_(printf)("******* This is not supported, exiting\n");
- VG_(exit)(1);
- }
+ } else
entry = (void *)(ebase + e->e.e_entry);
- }
info->exe_base = minaddr + ebase;
info->exe_end = maxaddr + ebase;
diff --git a/main/coregrind/m_ume/macho.c b/main/coregrind/m_ume/macho.c
index b1fd26f..e2a587b 100644
--- a/main/coregrind/m_ume/macho.c
+++ b/main/coregrind/m_ume/macho.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Apple Inc.
+ Copyright (C) 2005-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -76,12 +76,22 @@
static void check_mmap(SysRes res, Addr base, SizeT len, HChar* who)
{
if (sr_isError(res)) {
- VG_(printf)("valgrind: mmap(0x%llx, %lld) failed in UME (%s).\n",
+ VG_(printf)("valgrind: mmap-FIXED(0x%llx, %lld) failed in UME (%s).\n",
(ULong)base, (Long)len, who);
VG_(exit)(1);
}
}
+#if DARWIN_VERS == DARWIN_10_8
+static void check_mmap_float(SysRes res, SizeT len, HChar* who)
+{
+ if (sr_isError(res)) {
+ VG_(printf)("valgrind: mmap-FLOAT(size=%lld) failed in UME (%s).\n",
+ (Long)len, who);
+ VG_(exit)(1);
+ }
+}
+#endif
static int
load_thin_file(int fd, vki_off_t offset, vki_off_t size, unsigned long filetype,
@@ -370,6 +380,46 @@
}
+/* Allocates a stack mapping at a V-chosen address. Pertains to
+ LC_MAIN commands, which seem to have appeared in OSX 10.8.
+
+ This is a really nasty hack -- allocates 64M+stack size, then
+ deallocates the 64M, to guarantee that the stack is at least 64M
+ above zero. */
+#if DARWIN_VERS == DARWIN_10_8
+static int
+handle_lcmain ( vki_uint8_t **out_stack_start,
+ vki_uint8_t **out_stack_end,
+ vki_size_t requested_size )
+{
+ if (requested_size == 0) {
+ requested_size = default_stack_size();
+ }
+ requested_size = VG_PGROUNDUP(requested_size);
+
+ const vki_size_t HACK = 64 * 1024 * 1024;
+ requested_size += HACK;
+
+ SysRes res = VG_(am_mmap_anon_float_client)(requested_size,
+ VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC);
+ check_mmap_float(res, requested_size, "handle_lcmain");
+ vg_assert(!sr_isError(res));
+ *out_stack_start = (vki_uint8_t*)sr_Res(res);
+ *out_stack_end = *out_stack_start + requested_size;
+
+ Bool need_discard = False;
+ res = VG_(am_munmap_client)(&need_discard, (Addr)*out_stack_start, HACK);
+ if (sr_isError(res)) return -1;
+ vg_assert(!need_discard); // True == wtf?
+
+ *out_stack_start += HACK;
+
+ return 0;
+}
+#endif /* DARWIN_VERS == DARWIN_10_8 */
+
+
+
/*
Processes an LC_LOAD_DYLINKER command.
Returns 0 on success, -1 on any error.
@@ -432,6 +482,7 @@
vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end,
vki_uint8_t **out_text, vki_uint8_t **out_entry, vki_uint8_t **out_linker_entry)
{
+ VG_(debugLog)(1, "ume", "load_thin_file: begin: %s\n", filename);
struct MACH_HEADER mh;
vki_uint8_t *headers;
vki_uint8_t *headers_end;
@@ -487,7 +538,7 @@
print("couldn't read load commands from executable\n");
return -1;
}
- headers_end = headers + size;
+ headers_end = headers + len;
// Map some segments into client memory:
@@ -506,6 +557,23 @@
}
switch (lc->cmd) {
+
+#if DARWIN_VERS == DARWIN_10_8
+ case LC_MAIN: { /* New in 10.8 */
+ struct entry_point_command* epcmd
+ = (struct entry_point_command*)lc;
+ if (stack_start || stack_end) {
+ print("bad executable (multiple indications of stack)");
+ return -1;
+ }
+ err = handle_lcmain ( &stack_start, &stack_end, epcmd->stacksize );
+ if (err) return -1;
+ VG_(debugLog)(2, "ume", "lc_main: created stack %p-%p\n",
+ stack_start, stack_end);
+ break;
+ }
+# endif
+
case LC_SEGMENT_CMD:
if (lc->cmdsize < sizeof(struct SEGMENT_COMMAND)) {
print("bad executable (invalid load commands)\n");
@@ -582,7 +650,7 @@
// a text segment
// an entry point (static or linker)
if (!stack_end || !stack_start) {
- print("bad executable (no stack)\n");
+ VG_(printf)("bad executable %s (no stack)\n", filename);
return -1;
}
if (!text) {
@@ -609,6 +677,7 @@
if (out_entry) *out_entry = entry;
if (out_linker_entry) *out_linker_entry = linker_entry;
+ VG_(debugLog)(1, "ume", "load_thin_file: success: %s\n", filename);
return 0;
}
diff --git a/main/coregrind/m_ume/main.c b/main/coregrind/m_ume/main.c
index 1250182..65b7ba5 100644
--- a/main/coregrind/m_ume/main.c
+++ b/main/coregrind/m_ume/main.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -199,7 +199,7 @@
// will refuse to (eg. scripts lacking a "#!" prefix).
static Int do_exec_shell_followup(Int ret, HChar* exe_name, ExeInfo* info)
{
-# if defined(VGPV_arm_linux_android)
+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
Char* default_interp_name = "/system/bin/sh";
# else
Char* default_interp_name = "/bin/sh";
diff --git a/main/coregrind/m_ume/priv_ume.h b/main/coregrind/m_ume/priv_ume.h
index 83b8678..be7b09c 100644
--- a/main/coregrind/m_ume/priv_ume.h
+++ b/main/coregrind/m_ume/priv_ume.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_ume/script.c b/main/coregrind/m_ume/script.c
index c1a6514..53e3190 100644
--- a/main/coregrind/m_ume/script.c
+++ b/main/coregrind/m_ume/script.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_vki.c b/main/coregrind/m_vki.c
index 94417aa..d44ebdc 100644
--- a/main/coregrind/m_vki.c
+++ b/main/coregrind/m_vki.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_vkiscnums.c b/main/coregrind/m_vkiscnums.c
index a47cb63..dbd1f84 100644
--- a/main/coregrind/m_vkiscnums.c
+++ b/main/coregrind/m_vkiscnums.c
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/m_wordfm.c b/main/coregrind/m_wordfm.c
index e64715a..f386ea8 100644
--- a/main/coregrind/m_wordfm.c
+++ b/main/coregrind/m_wordfm.c
@@ -9,13 +9,13 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2011 Julian Seward
+ Copyright (C) 2007-2012 Julian Seward
jseward@acm.org
This code is based on previous work by Nicholas Nethercote
(coregrind/m_oset.c) which is
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
which in turn was derived partially from:
diff --git a/main/coregrind/m_xarray.c b/main/coregrind/m_xarray.c
index 8859cec..bac4ab8 100644
--- a/main/coregrind/m_xarray.c
+++ b/main/coregrind/m_xarray.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2011 OpenWorks LLP
+ Copyright (C) 2007-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -311,6 +311,20 @@
xa->usedsizeE -= n;
}
+void VG_(removeIndexXA)( XArray* xao, Word n )
+{
+ struct _XArray* xa = (struct _XArray*)xao;
+ vg_assert(xa);
+ vg_assert(n >= 0);
+ vg_assert(n < xa->usedsizeE);
+ if (n+1 < xa->usedsizeE) {
+ VG_(memmove)( ((char*)xa->arr) + (n+0) * xa->elemSzB,
+ ((char*)xa->arr) + (n+1) * xa->elemSzB,
+ (xa->usedsizeE - n - 1) * xa->elemSzB );
+ }
+ xa->usedsizeE--;
+}
+
void VG_(getContentsXA_UNSAFE)( XArray* xao,
/*OUT*/void** ctsP,
/*OUT*/Word* usedP )
diff --git a/main/coregrind/pub_core_aspacehl.h b/main/coregrind/pub_core_aspacehl.h
index 20b5288..8aa7c55 100644
--- a/main/coregrind/pub_core_aspacehl.h
+++ b/main/coregrind/pub_core_aspacehl.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2009-2011 Julian Seward
+ Copyright (C) 2009-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_aspacemgr.h b/main/coregrind/pub_core_aspacemgr.h
index 38c78ef..45cac3c 100644
--- a/main/coregrind/pub_core_aspacemgr.h
+++ b/main/coregrind/pub_core_aspacemgr.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -151,6 +151,17 @@
extern Addr VG_(am_get_advisory_client_simple)
( Addr start, SizeT len, /*OUT*/Bool* ok );
+/* Returns True if [start, start + len - 1] is covered by a single
+ free segment, otherwise returns False.
+ This allows to check the following case:
+ VG_(am_get_advisory_client_simple) (first arg == 0, meaning
+ this-or-nothing) is too lenient, and may allow us to trash
+ the next segment along. So make very sure that the proposed
+ new area really is free. This is perhaps overly
+ conservative, but it fixes #129866. */
+extern Bool VG_(am_covered_by_single_free_segment)
+ ( Addr start, SizeT len);
+
/* Notifies aspacem that the client completed an mmap successfully.
The segment array is updated accordingly. If the returned Bool is
True, the caller should immediately discard translations from the
@@ -158,9 +169,6 @@
extern Bool VG_(am_notify_client_mmap)
( Addr a, SizeT len, UInt prot, UInt flags, Int fd, Off64T offset );
-extern Bool VG_(am_notify_fake_client_mmap)
- ( Addr a, SizeT len, UInt prot, UInt flags, HChar* fileName, Off64T offset );
-
/* Notifies aspacem that the client completed a shmat successfully.
The segment array is updated accordingly. If the returned Bool is
True, the caller should immediately discard translations from the
@@ -246,8 +254,6 @@
mapping in object files to read their debug info. */
extern SysRes VG_(am_mmap_file_float_valgrind)
( SizeT length, UInt prot, Int fd, Off64T offset );
-extern SysRes VG_(am_mmap_file_float_valgrind_flags)
- ( SizeT length, UInt prot, UInt flags, Int fd, Off64T offset );
/* Map shared a file at an unconstrained address for V, and update the
segment array accordingly. This is used by V for communicating
@@ -337,7 +343,8 @@
// stacks. The address space manager provides and suitably
// protects such stacks.
-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
+ || defined(VGP_mips32_linux)
# define VG_STACK_GUARD_SZB 65536 // 1 or 16 pages
# define VG_STACK_ACTIVE_SZB (4096 * 256) // 1Mb
#else
diff --git a/main/coregrind/pub_core_basics.h b/main/coregrind/pub_core_basics.h
index f0861d4..4431b38 100644
--- a/main/coregrind/pub_core_basics.h
+++ b/main/coregrind/pub_core_basics.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -60,6 +60,8 @@
# include "libvex_guest_arm.h"
#elif defined(VGA_s390x)
# include "libvex_guest_s390x.h"
+#elif defined(VGA_mips32)
+# include "libvex_guest_mips32.h"
#else
# error Unknown arch
#endif
@@ -83,8 +85,8 @@
typedef
struct {
- ULong r_pc; /* x86:EIP, amd64:RIP, ppc:CIA, arm:R15 */
- ULong r_sp; /* x86:ESP, amd64:RSP, ppc:R1, arm:R13 */
+ ULong r_pc; /* x86:EIP, amd64:RIP, ppc:CIA, arm:R15, mips:pc */
+ ULong r_sp; /* x86:ESP, amd64:RSP, ppc:R1, arm:R13, mips:sp */
union {
struct {
UInt r_ebp;
@@ -108,6 +110,11 @@
ULong r_fp;
ULong r_lr;
} S390X;
+ struct {
+ UInt r30; /* Stack frame pointer or subroutine variable */
+ UInt r31; /* Return address of the last subroutine call */
+ UInt r28;
+ } MIPS32;
} misc;
}
UnwindStartRegs;
diff --git a/main/coregrind/pub_core_basics_asm.h b/main/coregrind/pub_core_basics_asm.h
index a060734..293ee8d 100644
--- a/main/coregrind/pub_core_basics_asm.h
+++ b/main/coregrind/pub_core_basics_asm.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_clientstate.h b/main/coregrind/pub_core_clientstate.h
index 4f4c912..d71de46 100644
--- a/main/coregrind/pub_core_clientstate.h
+++ b/main/coregrind/pub_core_clientstate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_clreq.h b/main/coregrind/pub_core_clreq.h
index 475e8b6..4fb712d 100644
--- a/main/coregrind/pub_core_clreq.h
+++ b/main/coregrind/pub_core_clreq.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -53,13 +53,6 @@
/* Add a target for an indirect function redirection. */
VG_USERREQ__ADD_IFUNC_TARGET = 0x3104,
- /* NaCl mem_start */
- VG_USERREQ__NACL_MEM_START = 0x3105,
- /* NaCl nacl_file */
- VG_USERREQ__NACL_FILE = 0x3106,
- /* NaCl nacl_file */
- VG_USERREQ__NACL_MMAP = 0x3107,
-
} Vg_InternalClientRequest;
// Function for printing from code within Valgrind, but which runs on the
diff --git a/main/coregrind/pub_core_commandline.h b/main/coregrind/pub_core_commandline.h
index 8279100..422080c 100644
--- a/main/coregrind/pub_core_commandline.h
+++ b/main/coregrind/pub_core_commandline.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_coredump.h b/main/coregrind/pub_core_coredump.h
index a8a8744..b2caa56 100644
--- a/main/coregrind/pub_core_coredump.h
+++ b/main/coregrind/pub_core_coredump.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_cpuid.h b/main/coregrind/pub_core_cpuid.h
index 7cceaef..7f1d750 100644
--- a/main/coregrind/pub_core_cpuid.h
+++ b/main/coregrind/pub_core_cpuid.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_debugger.h b/main/coregrind/pub_core_debugger.h
index b149cad..c82e60e 100644
--- a/main/coregrind/pub_core_debugger.h
+++ b/main/coregrind/pub_core_debugger.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_debuginfo.h b/main/coregrind/pub_core_debuginfo.h
index fa1b129..a74cd36 100644
--- a/main/coregrind/pub_core_debuginfo.h
+++ b/main/coregrind/pub_core_debuginfo.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -72,7 +72,7 @@
/* this should really return ULong, as per VG_(di_notify_mmap). */
extern void VG_(di_notify_pdb_debuginfo)( Int fd, Addr avma,
SizeT total_size,
- PtrdiffT unknown_purpose__reloc );
+ PtrdiffT bias );
/* this should also really return ULong */
extern void VG_(di_notify_vm_protect)( Addr a, SizeT len, UInt prot );
@@ -93,6 +93,12 @@
extern
Bool VG_(get_fnname_no_cxx_demangle) ( Addr a, Char* buf, Int nbuf );
+/* mips-linux only: find the offset of current address. This is needed for
+ stack unwinding for MIPS.
+*/
+extern
+Bool VG_(get_inst_offset_in_function)( Addr a, /*OUT*/PtrdiffT* offset );
+
/* Use DWARF2/3 CFA information to do one step of stack unwinding.
D3UnwindRegs holds the current register values, and is
@@ -114,6 +120,10 @@
typedef
struct { Addr ia; Addr sp; Addr fp; Addr lr;}
D3UnwindRegs;
+#elif defined(VGA_mips32)
+typedef
+ struct { Addr pc; Addr sp; Addr fp; Addr ra; }
+ D3UnwindRegs;
#else
# error "Unsupported arch"
#endif
diff --git a/main/coregrind/pub_core_debuglog.h b/main/coregrind/pub_core_debuglog.h
index 6ec7020..6b2a5a3 100644
--- a/main/coregrind/pub_core_debuglog.h
+++ b/main/coregrind/pub_core_debuglog.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_demangle.h b/main/coregrind/pub_core_demangle.h
index 2300874..79346d3 100644
--- a/main/coregrind/pub_core_demangle.h
+++ b/main/coregrind/pub_core_demangle.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_dispatch.h b/main/coregrind/pub_core_dispatch.h
index 6de7fcf..8438556 100644
--- a/main/coregrind/pub_core_dispatch.h
+++ b/main/coregrind/pub_core_dispatch.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -41,56 +41,38 @@
#include "pub_core_dispatch_asm.h"
-/* This subroutine is called from the C world. It is passed
- a pointer to the VEX guest state (arch.vex). It must run code
- from the instruction pointer in the guest state, and exit when
- VG_(dispatch_ctr) reaches zero, or we need to defer to the scheduler.
+/* Run translations, with the given guest state, and starting by
+ running the host code at 'host_addr'. It is almost always the case
+ that host_addr is the translation for guest_state.guest_IP, that
+ is, host_addr is what it would be if we looked up the address of
+ the translation corresponding to guest_state.guest_IP.
+
+ The only case where this isn't true is where we're running a
+ no-redir translation. In this case host_addr is the address of the
+ alternative (non-redirected) translation for guest_state.guest_IP.
+
The return value must indicate why it returned back to the scheduler.
It can also be exited if the executing code throws a non-resumable
signal, for example SIGSEGV, in which case control longjmp()s back past
here.
- If do_profiling is nonzero, the profile counters arrays should be
- updated for each translation run.
-
- This code simply handles the common case fast -- when the translation
- address is found in the translation cache. For anything else, the
- scheduler does the work.
-
- NOTE, VG_(run_innerloop) MUST NOT BE USED for noredir translations.
- Instead use VG_(run_a_noredir_translation).
+ two_words holds the return values (two words). First is
+ a TRC value. Second is generally unused, except in the case
+ where we have to return a chain-me request.
*/
-extern
-UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
-#if defined(VGA_x86) || defined(VGA_amd64)
-/* We need to locate a couple of labels inside VG_(run_innerloop), so
- that Vex can add branches to them from generated code. Hence the
- following somewhat bogus decls. At least on x86 and amd64. ppc32
- and ppc64 use straightforward bl-blr to get from dispatcher to
- translation and back and so do not need these labels. */
-extern Addr VG_(run_innerloop__dispatch_unassisted_unprofiled);
-extern Addr VG_(run_innerloop__dispatch_assisted_unprofiled);
-extern Addr VG_(run_innerloop__dispatch_unassisted_profiled);
-extern Addr VG_(run_innerloop__dispatch_assisted_profiled);
-#endif
+void VG_(disp_run_translations)( HWord* two_words,
+ void* guest_state,
+ Addr host_addr );
-
-/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
- and 2 to carry results:
- 0: input: ptr to translation
- 1: input: ptr to guest state
- 2: output: next guest PC
- 3: output: guest state pointer afterwards (== thread return code)
- MUST NOT BE USED for non-noredir (normal) translations.
-*/
-extern void VG_(run_a_noredir_translation) ( volatile UWord* argblock );
-#if defined(VGA_x86) || defined(VGA_amd64)
-/* We need to a label inside VG_(run_a_noredir_translation), so that
- Vex can add branches to them from generated code. Hence the
- following somewhat bogus decl. */
-extern Addr VG_(run_a_noredir_translation__return_point);
-#endif
-
+/* We need to know addresses of the continuation-point (cp_) labels so
+ we can tell VEX what they are. They will get baked into the code
+ VEX generates. The type is entirely mythical, but we need to
+ state _some_ type, so as to keep gcc happy. */
+void VG_(disp_cp_chain_me_to_slowEP)(void);
+void VG_(disp_cp_chain_me_to_fastEP)(void);
+void VG_(disp_cp_xindir)(void);
+void VG_(disp_cp_xassisted)(void);
+void VG_(disp_cp_evcheck_fail)(void);
#endif // __PUB_CORE_DISPATCH_H
diff --git a/main/coregrind/pub_core_dispatch_asm.h b/main/coregrind/pub_core_dispatch_asm.h
index 3e7b4a2..2375894 100644
--- a/main/coregrind/pub_core_dispatch_asm.h
+++ b/main/coregrind/pub_core_dispatch_asm.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -43,16 +43,20 @@
/* And some more of our own. These must not have the same values as
those from libvex_trc_values.h. (viz, 60 or below is safe).
+ (The following comment is no longer relevant, but is retained
+ for historical purposes.)
These values *must* be odd (have bit 0 set) because the dispatchers
(coregrind/m_dispatch/dispatch-*-*.S) use this fact to distinguish
a TRC value from the unchanged baseblock pointer -- which has 0 as
its lowest bit.
*/
-#define VG_TRC_BORING 29 /* no event; just keep going */
-#define VG_TRC_INNER_FASTMISS 37 /* TRC only; means fast-cache miss. */
-#define VG_TRC_INNER_COUNTERZERO 41 /* TRC only; means bb ctr == 0 */
-#define VG_TRC_FAULT_SIGNAL 43 /* TRC only; got sigsegv/sigbus */
-#define VG_TRC_INVARIANT_FAILED 47 /* TRC only; invariant violation */
+#define VG_TRC_BORING 29 /* no event; just keep going */
+#define VG_TRC_INNER_FASTMISS 37 /* TRC only; means fast-cache miss. */
+#define VG_TRC_INNER_COUNTERZERO 41 /* TRC only; means bb ctr == 0 */
+#define VG_TRC_FAULT_SIGNAL 43 /* TRC only; got sigsegv/sigbus */
+#define VG_TRC_INVARIANT_FAILED 47 /* TRC only; invariant violation */
+#define VG_TRC_CHAIN_ME_TO_SLOW_EP 49 /* TRC only; chain to slow EP */
+#define VG_TRC_CHAIN_ME_TO_FAST_EP 51 /* TRC only; chain to fast EP */
#endif // __PUB_CORE_DISPATCH_ASM_H
diff --git a/main/coregrind/pub_core_errormgr.h b/main/coregrind/pub_core_errormgr.h
index c9f5aa9..aec16a4 100644
--- a/main/coregrind/pub_core_errormgr.h
+++ b/main/coregrind/pub_core_errormgr.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -67,6 +67,7 @@
extern Bool VG_(showing_core_errors) ( void );
extern UInt VG_(get_n_errs_found) ( void );
+extern UInt VG_(get_n_errs_shown) ( void );
extern void VG_(print_errormgr_stats) ( void );
diff --git a/main/coregrind/pub_core_execontext.h b/main/coregrind/pub_core_execontext.h
index 7dac88a..8150719 100644
--- a/main/coregrind/pub_core_execontext.h
+++ b/main/coregrind/pub_core_execontext.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -41,7 +41,7 @@
#include "pub_tool_execontext.h"
/* The maximum number of calls we're prepared to save in an ExeContext. */
-#define VG_DEEPEST_BACKTRACE 50
+#define VG_DEEPEST_BACKTRACE 500
// Print stats (informational only).
extern void VG_(print_ExeContext_stats) ( void );
diff --git a/main/coregrind/pub_core_gdbserver.h b/main/coregrind/pub_core_gdbserver.h
index 481162c..f542b5b 100644
--- a/main/coregrind/pub_core_gdbserver.h
+++ b/main/coregrind/pub_core_gdbserver.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2011 Philippe Waroquiers
+ Copyright (C) 2011-2012 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -143,10 +143,6 @@
typedef
struct {
- // PID of the vgdb that last connected to the Valgrind gdbserver.
- // It will be set by vgdb after connecting.
- int vgdb_pid;
-
// nr of bytes vgdb has written to valgrind
volatile int written_by_vgdb;
// nr of bytes seen by valgrind
@@ -161,13 +157,15 @@
int sizeof_ThreadState;
int offset_status;
int offset_lwpid;
+
+ // PID of the vgdb that last connected to the Valgrind gdbserver.
+ // It will be set by vgdb after connecting.
+ int vgdb_pid;
} VgdbShared32;
/* Same as VgdbShared32 but for 64 bits arch. */
typedef
struct {
- int vgdb_pid;
-
volatile int written_by_vgdb;
volatile int seen_by_valgrind;
@@ -177,6 +175,8 @@
int sizeof_ThreadState;
int offset_status;
int offset_lwpid;
+
+ int vgdb_pid;
} VgdbShared64;
// The below typedef makes the life of valgrind easier.
diff --git a/main/coregrind/pub_core_hashtable.h b/main/coregrind/pub_core_hashtable.h
index 0c92da1..d7dd060 100644
--- a/main/coregrind/pub_core_hashtable.h
+++ b/main/coregrind/pub_core_hashtable.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_initimg.h b/main/coregrind/pub_core_initimg.h
index 9c6dbfa..d82e36c 100644
--- a/main/coregrind/pub_core_initimg.h
+++ b/main/coregrind/pub_core_initimg.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_libcassert.h b/main/coregrind/pub_core_libcassert.h
index c0a34a7..d86cbab 100644
--- a/main/coregrind/pub_core_libcassert.h
+++ b/main/coregrind/pub_core_libcassert.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_libcbase.h b/main/coregrind/pub_core_libcbase.h
index 182591a..0c4d676 100644
--- a/main/coregrind/pub_core_libcbase.h
+++ b/main/coregrind/pub_core_libcbase.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_libcfile.h b/main/coregrind/pub_core_libcfile.h
index 3b407c8..265b280 100644
--- a/main/coregrind/pub_core_libcfile.h
+++ b/main/coregrind/pub_core_libcfile.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -41,7 +41,6 @@
/* Move an fd into the Valgrind-safe range */
extern Int VG_(safe_fd) ( Int oldfd );
-extern Int reopen_output_fd(Bool xml);
extern Int VG_(fcntl) ( Int fd, Int cmd, Addr arg );
/* Convert an fd into a filename */
diff --git a/main/coregrind/pub_core_libcprint.h b/main/coregrind/pub_core_libcprint.h
index 5f08425..4870771 100644
--- a/main/coregrind/pub_core_libcprint.h
+++ b/main/coregrind/pub_core_libcprint.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_libcproc.h b/main/coregrind/pub_core_libcproc.h
index cd9c18a..c200c92 100644
--- a/main/coregrind/pub_core_libcproc.h
+++ b/main/coregrind/pub_core_libcproc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -84,6 +84,10 @@
extern void VG_(do_atfork_parent) ( ThreadId tid );
extern void VG_(do_atfork_child) ( ThreadId tid );
+// icache invalidation
+extern void VG_(invalidate_icache) ( void *ptr, SizeT nbytes );
+
+
#endif // __PUB_CORE_LIBCPROC_H
/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/pub_core_libcsetjmp.h b/main/coregrind/pub_core_libcsetjmp.h
index fec29b3..830065e 100644
--- a/main/coregrind/pub_core_libcsetjmp.h
+++ b/main/coregrind/pub_core_libcsetjmp.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2011 Mozilla Inc
+ Copyright (C) 2010-2012 Mozilla Inc
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/coregrind/pub_core_libcsignal.h b/main/coregrind/pub_core_libcsignal.h
index 47d71d4..6c02967 100644
--- a/main/coregrind/pub_core_libcsignal.h
+++ b/main/coregrind/pub_core_libcsignal.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_mach.h b/main/coregrind/pub_core_mach.h
index 745655a..53e7c6e 100644
--- a/main/coregrind/pub_core_mach.h
+++ b/main/coregrind/pub_core_mach.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Apple Inc.
+ Copyright (C) 2005-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_machine.h b/main/coregrind/pub_core_machine.h
index ee65b97..ded9b9a 100644
--- a/main/coregrind/pub_core_machine.h
+++ b/main/coregrind/pub_core_machine.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -75,6 +75,17 @@
# define VG_ELF_MACHINE EM_S390
# define VG_ELF_CLASS ELFCLASS64
# undef VG_PLAT_USES_PPCTOC
+#elif defined(VGP_mips32_linux)
+# if defined (VG_LITTLEENDIAN)
+# define VG_ELF_DATA2XXX ELFDATA2LSB
+# elif defined (VG_BIGENDIAN)
+# define VG_ELF_DATA2XXX ELFDATA2MSB
+# else
+# error "Unknown endianness"
+# endif
+# define VG_ELF_MACHINE EM_MIPS
+# define VG_ELF_CLASS ELFCLASS32
+# undef VG_PLAT_USES_PPCTOC
#else
# error Unknown platform
#endif
@@ -103,6 +114,11 @@
# define VG_INSTR_PTR guest_IA
# define VG_STACK_PTR guest_SP
# define VG_FRAME_PTR guest_FP
+# define VG_FPC_REG guest_fpc
+#elif defined(VGA_mips32)
+# define VG_INSTR_PTR guest_PC
+# define VG_STACK_PTR guest_r29
+# define VG_FRAME_PTR guest_r30
#else
# error Unknown arch
#endif
@@ -111,6 +127,7 @@
// Offsets for the Vex state
#define VG_O_STACK_PTR (offsetof(VexGuestArchState, VG_STACK_PTR))
#define VG_O_INSTR_PTR (offsetof(VexGuestArchState, VG_INSTR_PTR))
+#define VG_O_FPC_REG (offsetof(VexGuestArchState, VG_FPC_REG))
//-------------------------------------------------------------
@@ -167,6 +184,10 @@
call VG_(machine_arm_set_has_NEON)
then safe to use VG_(machine_get_VexArchInfo)
+ -------------
+ s390x: initially: call VG_(machine_get_hwcaps)
+
+ then safe to use VG_(machine_get_VexArchInfo)
VG_(machine_get_hwcaps) may use signals (although it attempts to
leave signal state unchanged) and therefore should only be
diff --git a/main/coregrind/pub_core_mallocfree.h b/main/coregrind/pub_core_mallocfree.h
index c192f19..3349b2b 100644
--- a/main/coregrind/pub_core_mallocfree.h
+++ b/main/coregrind/pub_core_mallocfree.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -80,6 +80,7 @@
defined(VGP_ppc32_linux) || \
defined(VGP_ppc64_linux) || \
defined(VGP_s390x_linux) || \
+ defined(VGP_mips32_linux) || \
defined(VGP_x86_darwin) || \
defined(VGP_amd64_darwin)
# define VG_MIN_MALLOC_SZB 16
diff --git a/main/coregrind/pub_core_options.h b/main/coregrind/pub_core_options.h
index 11b220a..c22580a 100644
--- a/main/coregrind/pub_core_options.h
+++ b/main/coregrind/pub_core_options.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -86,6 +86,10 @@
/* Automatically attempt to demangle C++ names? default: YES */
extern Bool VG_(clo_demangle);
/* Simulate child processes? default: NO */
+/* Soname synonyms : a string containing a list of pairs
+ xxxxx=yyyyy separated by commas.
+ E.g. --soname-synonyms=somalloc=libtcmalloc*.so*,solibtruc=NONE */
+extern HChar* VG_(clo_soname_synonyms);
extern Bool VG_(clo_trace_children);
/* String containing comma-separated patterns for executable names
that should not be traced into even when --trace-children=yes */
@@ -107,9 +111,6 @@
extern Char* VG_(clo_log_fname_expanded);
extern Char* VG_(clo_xml_fname_expanded);
-extern Char* VG_(clo_log_fname_unexpanded);
-extern Char* VG_(clo_xml_fname_unexpanded);
-
/* Add timestamps to log messages? default: NO */
extern Bool VG_(clo_time_stamp);
@@ -129,8 +130,10 @@
extern UChar VG_(clo_trace_flags);
/* DEBUG: do bb profiling? default: 00000000 ( == NO ) */
extern UChar VG_(clo_profile_flags);
-/* DEBUG: if tracing codegen, be quiet until after this bb ( 0 ) */
+/* DEBUG: if tracing codegen, be quiet until after this bb */
extern Int VG_(clo_trace_notbelow);
+/* DEBUG: if tracing codegen, be quiet after this bb */
+extern Int VG_(clo_trace_notabove);
/* DEBUG: print system calls? default: NO */
extern Bool VG_(clo_trace_syscalls);
/* DEBUG: print signal details? default: NO */
@@ -149,10 +152,25 @@
extern Bool VG_(clo_debug_dump_frames);
/* DEBUG: print redirection details? default: NO */
extern Bool VG_(clo_trace_redir);
+/* Enable fair scheduling on multicore systems? default: NO */
+enum FairSchedType { disable_fair_sched, enable_fair_sched, try_fair_sched };
+extern enum FairSchedType VG_(clo_fair_sched);
/* DEBUG: print thread scheduling events? default: NO */
extern Bool VG_(clo_trace_sched);
/* DEBUG: do heap profiling? default: NO */
extern Bool VG_(clo_profile_heap);
+#define MAX_REDZONE_SZB 128
+// Maximum for the default values for core arenas and for client
+// arena given by the tool.
+// 128 is no special figure, just something not too big
+#define MAX_CLO_REDZONE_SZB 4096
+// We allow the user to increase the redzone size to 4Kb :
+// This allows "off by one" in an array of pages to be detected.
+#define CORE_REDZONE_DEFAULT_SZB 4
+extern Int VG_(clo_core_redzone_size);
+// VG_(clo_redzone_size) has default value -1, indicating to keep
+// the tool provided value.
+extern Int VG_(clo_redzone_size);
/* DEBUG: display gory details for the k'th most popular error.
default: Infinity. */
extern Int VG_(clo_dump_error);
@@ -162,12 +180,8 @@
extern Bool VG_(clo_sym_offsets);
/* Read DWARF3 variable info even if tool doesn't ask for it? */
extern Bool VG_(clo_read_var_info);
-
-/* Mountpoint for memfs */
-extern Char* VG_(clo_memfs_malloc_path);
-/* Size of memfs page in Kbytes */
-extern Int VG_(clo_memfs_page_size);
-
+/* Which prefix to strip from full source file paths, if any. */
+extern Char* VG_(clo_prefix_to_strip);
/* An array of strings harvested from --require-text-symbol=
flags.
@@ -252,10 +266,6 @@
.dSYM directories as necessary? */
extern Bool VG_(clo_dsymutil);
-/* NaCl nexe to read symbols from. Overrides the filename NaCl reports, if
- any. */
-extern Char* VG_(clo_nacl_file);
-
/* Should we trace into this child executable (across execve etc) ?
This involves considering --trace-children=,
--trace-children-skip=, --trace-children-skip-by-arg=, and the name
diff --git a/main/coregrind/pub_core_oset.h b/main/coregrind/pub_core_oset.h
index dc6db25..2606122 100644
--- a/main/coregrind/pub_core_oset.h
+++ b/main/coregrind/pub_core_oset.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_redir.h b/main/coregrind/pub_core_redir.h
index 2533f2b..67fe802 100644
--- a/main/coregrind/pub_core_redir.h
+++ b/main/coregrind/pub_core_redir.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_replacemalloc.h b/main/coregrind/pub_core_replacemalloc.h
index 2c62275..e0eabb0 100644
--- a/main/coregrind/pub_core_replacemalloc.h
+++ b/main/coregrind/pub_core_replacemalloc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_scheduler.h b/main/coregrind/pub_core_scheduler.h
index 8d3d97c..8104562 100644
--- a/main/coregrind/pub_core_scheduler.h
+++ b/main/coregrind/pub_core_scheduler.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -78,6 +78,9 @@
/* Matching function to acquire_BigLock_LL. */
extern void VG_(release_BigLock_LL) ( HChar* who );
+/* Whether the specified thread owns the big lock. */
+extern Bool VG_(owns_BigLock_LL) ( ThreadId tid );
+
/* Yield the CPU for a while. Drops/acquires the lock using the
normal (non _LL) functions. */
extern void VG_(vg_yield)(void);
diff --git a/main/coregrind/pub_core_seqmatch.h b/main/coregrind/pub_core_seqmatch.h
index 097678f..58325df 100644
--- a/main/coregrind/pub_core_seqmatch.h
+++ b/main/coregrind/pub_core_seqmatch.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks Ltd
+ Copyright (C) 2008-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_sigframe.h b/main/coregrind/pub_core_sigframe.h
index 7d85759..67b864d 100644
--- a/main/coregrind/pub_core_sigframe.h
+++ b/main/coregrind/pub_core_sigframe.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_signals.h b/main/coregrind/pub_core_signals.h
index dae2c3f..5faa128 100644
--- a/main/coregrind/pub_core_signals.h
+++ b/main/coregrind/pub_core_signals.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -40,6 +40,9 @@
/* Highest signal the kernel will let us use */
extern Int VG_(max_signal);
+/* Returns the name of the vki signal sigNo */
+extern const Char *VG_(signame)(Int sigNo);
+
/* Use high signals because native pthreads wants to use low */
#define VG_SIGVGKILL (VG_(max_signal)-0)
#define VG_SIGVGRTUSERMAX (VG_(max_signal)-1)
diff --git a/main/coregrind/pub_core_sparsewa.h b/main/coregrind/pub_core_sparsewa.h
index 34f7b16..c871a2a 100644
--- a/main/coregrind/pub_core_sparsewa.h
+++ b/main/coregrind/pub_core_sparsewa.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks Ltd
+ Copyright (C) 2008-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_stacks.h b/main/coregrind/pub_core_stacks.h
index f3b249d..eefd8a5 100644
--- a/main/coregrind/pub_core_stacks.h
+++ b/main/coregrind/pub_core_stacks.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_stacktrace.h b/main/coregrind/pub_core_stacktrace.h
index dc35bd8..36c7fd8 100644
--- a/main/coregrind/pub_core_stacktrace.h
+++ b/main/coregrind/pub_core_stacktrace.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_syscall.h b/main/coregrind/pub_core_syscall.h
index 1b6d35f..9cd0ea8 100644
--- a/main/coregrind/pub_core_syscall.h
+++ b/main/coregrind/pub_core_syscall.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -79,6 +79,8 @@
extern SysRes VG_(mk_SysRes_amd64_darwin)( UChar scclass, Bool isErr,
ULong wHI, ULong wLO );
extern SysRes VG_(mk_SysRes_s390x_linux) ( Long val );
+extern SysRes VG_(mk_SysRes_mips32_linux)( UWord v0, UWord v1,
+ UWord a3 );
extern SysRes VG_(mk_SysRes_Error) ( UWord val );
extern SysRes VG_(mk_SysRes_Success) ( UWord val );
diff --git a/main/coregrind/pub_core_syswrap.h b/main/coregrind/pub_core_syswrap.h
index b2cebae..04a22df 100644
--- a/main/coregrind/pub_core_syswrap.h
+++ b/main/coregrind/pub_core_syswrap.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_threadstate.h b/main/coregrind/pub_core_threadstate.h
index e49926e..0bd9927 100644
--- a/main/coregrind/pub_core_threadstate.h
+++ b/main/coregrind/pub_core_threadstate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -87,6 +87,8 @@
typedef VexGuestARMState VexGuestArchState;
#elif defined(VGA_s390x)
typedef VexGuestS390XState VexGuestArchState;
+#elif defined(VGA_mips32)
+ typedef VexGuestMIPS32State VexGuestArchState;
#else
# error Unknown architecture
#endif
@@ -373,6 +375,9 @@
/*--- Basic operations on the thread table. ---*/
/*------------------------------------------------------------*/
+/* Initialize the m_threadstate module. */
+void VG_(init_Threads)(void);
+
// Convert a ThreadStatus to a string.
const HChar* VG_(name_of_ThreadStatus) ( ThreadStatus status );
diff --git a/main/coregrind/pub_core_tooliface.h b/main/coregrind/pub_core_tooliface.h
index af86c90..4689db8 100644
--- a/main/coregrind/pub_core_tooliface.h
+++ b/main/coregrind/pub_core_tooliface.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -226,7 +226,6 @@
void (*track_stop_client_code) (ThreadId, ULong);
void (*track_pre_thread_ll_create)(ThreadId, ThreadId);
- void (*track_workq_task_start)(ThreadId, Addr);
void (*track_pre_thread_first_insn)(ThreadId);
void (*track_pre_thread_ll_exit) (ThreadId);
diff --git a/main/coregrind/pub_core_trampoline.h b/main/coregrind/pub_core_trampoline.h
index 87fd868..209213f 100644
--- a/main/coregrind/pub_core_trampoline.h
+++ b/main/coregrind/pub_core_trampoline.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -67,6 +67,7 @@
extern Addr VG_(amd64_linux_SUBST_FOR_rt_sigreturn);
extern Addr VG_(amd64_linux_REDIR_FOR_vgettimeofday);
extern Addr VG_(amd64_linux_REDIR_FOR_vtime);
+extern Addr VG_(amd64_linux_REDIR_FOR_vgetcpu);
extern UInt VG_(amd64_linux_REDIR_FOR_strlen)( void* );
#endif
@@ -93,6 +94,8 @@
#endif
#if defined(VGP_arm_linux)
+extern Addr VG_(arm_linux_SUBST_FOR_sigreturn);
+extern Addr VG_(arm_linux_SUBST_FOR_rt_sigreturn);
extern UInt VG_(arm_linux_REDIR_FOR_strlen)( void* );
//extern void* VG_(arm_linux_REDIR_FOR_index) ( void*, Int );
extern void* VG_(arm_linux_REDIR_FOR_memcpy)( void*, void*, Int );
@@ -124,6 +127,12 @@
extern Addr VG_(s390x_linux_SUBST_FOR_rt_sigreturn);
#endif
+#if defined(VGP_mips32_linux)
+extern Addr VG_(mips32_linux_SUBST_FOR_sigreturn);
+extern Addr VG_(mips32_linux_SUBST_FOR_rt_sigreturn);
+extern UInt VG_(mips32_linux_REDIR_FOR_strlen)( void* );
+#endif
+
#endif // __PUB_CORE_TRAMPOLINE_H
/*--------------------------------------------------------------------*/
diff --git a/main/coregrind/pub_core_translate.h b/main/coregrind/pub_core_translate.h
index c6c2405..c399d58 100644
--- a/main/coregrind/pub_core_translate.h
+++ b/main/coregrind/pub_core_translate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_transtab.h b/main/coregrind/pub_core_transtab.h
index 34ffee9..61e7e8c 100644
--- a/main/coregrind/pub_core_transtab.h
+++ b/main/coregrind/pub_core_transtab.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -39,9 +39,8 @@
#include "pub_core_transtab_asm.h"
-/* The fast-cache for tt-lookup, and for finding counters. Unused
- entries are denoted by .guest == 1, which is assumed to be a bogus
- address for all guest code. */
+/* The fast-cache for tt-lookup. Unused entries are denoted by .guest
+ == 1, which is assumed to be a bogus address for all guest code. */
typedef
struct {
Addr guest;
@@ -54,8 +53,6 @@
#define TRANSTAB_BOGUS_GUEST_ADDR ((Addr)1)
-extern UInt* VG_(tt_fastN)[VG_TT_FAST_SIZE];
-
extern void VG_(init_tt_tc) ( void );
extern
@@ -63,9 +60,20 @@
Addr64 entry,
AddrH code,
UInt code_len,
- Bool is_self_checking );
+ Bool is_self_checking,
+ Int offs_profInc,
+ UInt n_guest_instrs,
+ VexArch arch_host );
-extern Bool VG_(search_transtab) ( /*OUT*/AddrH* result,
+extern
+void VG_(tt_tc_do_chaining) ( void* from__patch_addr,
+ UInt to_sNo,
+ UInt to_tteNo,
+ Bool to_fastEP );
+
+extern Bool VG_(search_transtab) ( /*OUT*/AddrH* res_hcode,
+ /*OUT*/UInt* res_sNo,
+ /*OUT*/UInt* res_tteNo,
Addr64 guest_addr,
Bool upd_cache );
diff --git a/main/coregrind/pub_core_transtab_asm.h b/main/coregrind/pub_core_transtab_asm.h
index 6d43a7a..6473294 100644
--- a/main/coregrind/pub_core_transtab_asm.h
+++ b/main/coregrind/pub_core_transtab_asm.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -42,8 +42,9 @@
ever be used. So instead the function is '(address >>u
2)[VG_TT_FAST_BITS-1 : 0]' on those targets.
- On ARM we do like ppc32/ppc64, although that will have to be
- revisited when we come to implement Thumb.
+ On ARM we shift by 1, since Thumb insns can be of size 2, hence to
+ minimise collisions and maximise cache utilisation we need to take
+ into account all but the least significant bit.
On s390x the rightmost bit of an instruction address is zero.
For best table utilization shift the address to the right by 1 bit. */
@@ -61,7 +62,7 @@
#elif defined(VGA_s390x) || defined(VGA_arm)
# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 1) & VG_TT_FAST_MASK)
-#elif defined(VGA_ppc32) || defined(VGA_ppc64)
+#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_mips32)
# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK)
#else
diff --git a/main/coregrind/pub_core_ume.h b/main/coregrind/pub_core_ume.h
index 4228033..a9a438e 100644
--- a/main/coregrind/pub_core_ume.h
+++ b/main/coregrind/pub_core_ume.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_vki.h b/main/coregrind/pub_core_vki.h
index f314e76..457d0f6 100644
--- a/main/coregrind/pub_core_vki.h
+++ b/main/coregrind/pub_core_vki.h
@@ -8,11 +8,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_vkiscnums.h b/main/coregrind/pub_core_vkiscnums.h
index 9b0da60..e2d6e23 100644
--- a/main/coregrind/pub_core_vkiscnums.h
+++ b/main/coregrind/pub_core_vkiscnums.h
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_vkiscnums_asm.h b/main/coregrind/pub_core_vkiscnums_asm.h
index 739adab..6b52acb 100644
--- a/main/coregrind/pub_core_vkiscnums_asm.h
+++ b/main/coregrind/pub_core_vkiscnums_asm.h
@@ -7,11 +7,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/pub_core_wordfm.h b/main/coregrind/pub_core_wordfm.h
index 425ed4c..8a71059 100644
--- a/main/coregrind/pub_core_wordfm.h
+++ b/main/coregrind/pub_core_wordfm.h
@@ -9,13 +9,13 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2011 Julian Seward
+ Copyright (C) 2007-2012 Julian Seward
jseward@acm.org
This code is based on previous work by Nicholas Nethercote
(coregrind/m_oset.c) which is
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
which in turn was derived partially from:
diff --git a/main/coregrind/pub_core_xarray.h b/main/coregrind/pub_core_xarray.h
index 80aedf1..b69dffb 100644
--- a/main/coregrind/pub_core_xarray.h
+++ b/main/coregrind/pub_core_xarray.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2011 OpenWorks LLP
+ Copyright (C) 2007-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/coregrind/vg_preloaded.c b/main/coregrind/vg_preloaded.c
index e6f1e02..aec1656 100644
--- a/main/coregrind/vg_preloaded.c
+++ b/main/coregrind/vg_preloaded.c
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -56,8 +56,8 @@
void VG_NOTIFY_ON_LOAD(freeres)( void );
void VG_NOTIFY_ON_LOAD(freeres)( void )
{
-# if !defined(__UCLIBC__) && !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android)
-
+# if !defined(__UCLIBC__) \
+ && !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android)
extern void __libc_freeres(void);
__libc_freeres();
# endif
diff --git a/main/coregrind/vgdb.c b/main/coregrind/vgdb.c
index fcbf8a9..ec98eef 100644
--- a/main/coregrind/vgdb.c
+++ b/main/coregrind/vgdb.c
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2011 Philippe Waroquiers
+ Copyright (C) 2011-2012 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -80,7 +80,8 @@
can be "waken up". PTRACEINVOKER implies some architecture
specific code and/or some OS specific code. */
#if defined(VGA_arm) || defined(VGA_x86) || defined(VGA_amd64) \
- || defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x)
+ || defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x) \
+ || defined(VGP_mips32_linux)
#define PTRACEINVOKER
#else
I_die_here : (PTRACEINVOKER) architecture missing in vgdb.c
@@ -181,25 +182,27 @@
const char *tmpdir;
tmpdir = getenv("TMPDIR");
- if (tmpdir == NULL || *tmpdir == '\0') tmpdir = VG_TMPDIR;
- if (tmpdir == NULL || *tmpdir == '\0') tmpdir = "/tmp"; /* fallback */
+ if (tmpdir == NULL || *tmpdir == '\0')
+ tmpdir = VG_TMPDIR;
+ if (tmpdir == NULL || *tmpdir == '\0')
+ tmpdir = "/tmp"; /* fallback */
return tmpdir;
}
-/* Return the path prefix for the named pipes (FIFOs) used by vgdb/gdb
+/* Return the default path prefix for the named pipes (FIFOs) used by vgdb/gdb
to communicate with valgrind */
static
char *vgdb_prefix_default(void)
{
- const char *tmpdir;
- HChar *prefix;
-
- tmpdir = vgdb_tmpdir();
- prefix = vmalloc(strlen(tmpdir) + strlen("/vgdb-pipe") + 1);
- strcpy(prefix, tmpdir);
- strcat(prefix, "/vgdb-pipe");
+ static HChar *prefix;
+ if (prefix == NULL) {
+ const char *tmpdir = vgdb_tmpdir();
+ prefix = vmalloc(strlen(tmpdir) + strlen("/vgdb-pipe") + 1);
+ strcpy(prefix, tmpdir);
+ strcat(prefix, "/vgdb-pipe");
+ }
return prefix;
}
@@ -340,7 +343,7 @@
to inferior's memory at MEMADDR.
On failure (cannot write the inferior)
returns the value of errno. */
-
+__attribute__((unused)) /* not used on all platforms */
static
int ptrace_write_memory (pid_t inferior_pid, CORE_ADDR memaddr,
const unsigned char *myaddr, int len)
@@ -437,8 +440,10 @@
if (WIFSTOPPED(status))
APPEND ("WIFSTOPPED %d ", WSTOPSIG(status));
+#ifdef WIFCONTINUED
if (WIFCONTINUED(status))
APPEND ("WIFCONTINUED ");
+#endif
return result;
#undef APPEND
@@ -919,6 +924,8 @@
sp = user_mod.regs.gpr[1];
#elif defined(VGA_s390x)
sp = user_mod.regs.gprs[15];
+#elif defined(VGA_mips32)
+ sp = user_mod.regs[29*2];
#else
I_die_here : (sp) architecture missing in vgdb.c
#endif
@@ -991,6 +998,19 @@
#elif defined(VGA_s390x)
XERROR(0, "(fn32) s390x has no 32bits implementation");
+#elif defined(VGA_mips32)
+ /* put check arg in register 4 */
+ user_mod.regs[4*2] = check;
+ user_mod.regs[4*2+1] = 0xffffffff; // sign extend $a0
+ /* This sign extension is needed when vgdb 32 bits runs
+ on a 64 bits OS. */
+ /* put NULL return address in ra */
+ user_mod.regs[31*2] = bad_return;
+ user_mod.regs[31*2+1] = 0;
+ user_mod.regs[34*2] = shared32->invoke_gdbserver;
+ user_mod.regs[34*2+1] = 0;
+ user_mod.regs[25*2] = shared32->invoke_gdbserver;
+ user_mod.regs[25*2+1] = 0;
#else
I_die_here : architecture missing in vgdb.c
#endif
@@ -1070,6 +1090,8 @@
user_mod.regs.gprs[15] = sp;
/* set program counter */
user_mod.regs.psw.addr = shared64->invoke_gdbserver;
+#elif defined(VGA_mips32)
+ assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe
#else
I_die_here: architecture missing in vgdb.c
#endif
@@ -1364,7 +1386,7 @@
static
Bool read_from_gdb_write_to_pid(int to_pid)
{
- char buf[PBUFSIZ];
+ char buf[PBUFSIZ+1]; // +1 for trailing \0
int nrread;
nrread = read_buf(from_gdb, buf, "from gdb on stdin");
@@ -1388,7 +1410,7 @@
static
Bool read_from_pid_write_to_gdb(int from_pid)
{
- char buf[PBUFSIZ];
+ char buf[PBUFSIZ+1]; // +1 for trailing \0
int nrread;
nrread = read_buf(from_pid, buf, "from pid");
@@ -1493,14 +1515,14 @@
static int
readchar (int fd)
{
- static unsigned char buf[PBUFSIZ];
+ static unsigned char buf[PBUFSIZ+1]; // +1 for trailing \0
static int bufcnt = 0;
static unsigned char *bufp;
if (bufcnt-- > 0)
return *bufp++;
- bufcnt = read (fd, buf, sizeof (buf));
+ bufcnt = read_buf (fd, buf, "static buf readchar");
if (bufcnt <= 0) {
if (bufcnt == 0) {
@@ -1619,7 +1641,7 @@
sigpipe++;
} else if (signum == SIGALRM) {
sigalrm++;
-#if defined(VGPV_arm_linux_android)
+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
/* Android has no pthread_cancel. As it also does not have
PTRACE_INVOKER, there is no need for cleanup action.
So, we just do nothing. */
@@ -1810,10 +1832,10 @@
if (!read_from_gdb_write_to_pid(to_pid))
shutting_down = True;
break;
- case FROM_PID:
- if (!read_from_pid_write_to_gdb(from_pid))
- shutting_down = True;
- break;
+ case FROM_PID:
+ if (!read_from_pid_write_to_gdb(from_pid))
+ shutting_down = True;
+ break;
default: XERROR(0, "unexpected POLLIN on %s\n",
ppConnectionKind(ck));
}
@@ -1874,7 +1896,7 @@
unsigned char hex[3];
unsigned char cksum;
unsigned char *hexcommand;
- unsigned char buf[PBUFSIZ];
+ unsigned char buf[PBUFSIZ+1]; // +1 for trailing \0
int buflen;
int nc;
@@ -2151,19 +2173,19 @@
errno = 0; /* avoid complain if vgdb_dir is empty */
while ((f = readdir (vgdb_dir))) {
struct stat st;
- char pathname[strlen(vgdb_dir_name) + strlen(f->d_name)];
+ char pathname[strlen(vgdb_dir_name) + strlen(f->d_name) + 1];
char *wrongpid;
int newpid;
strcpy (pathname, vgdb_dir_name);
strcat (pathname, f->d_name);
- DEBUG(3, "trying %s\n", pathname);
+ DEBUG(3, "checking pathname is FIFO %s\n", pathname);
if (stat (pathname, &st) != 0) {
if (debuglevel >= 3)
ERROR (errno, "vgdb error: stat %s searching vgdb fifo\n",
pathname);
} else if (S_ISFIFO (st.st_mode)) {
- DEBUG(3, "trying %s\n", pathname);
+ DEBUG(3, "trying FIFO %s\n", pathname);
if (strncmp (pathname, vgdb_format,
strlen (vgdb_format)) == 0) {
newpid = strtol(pathname + strlen (vgdb_format),
diff --git a/main/drd/Makefile.am b/main/drd/Makefile.am
index fd63505..153b384 100644
--- a/main/drd/Makefile.am
+++ b/main/drd/Makefile.am
@@ -54,7 +54,6 @@
DRD_SOURCES_COMMON = \
drd_barrier.c \
- drd_bitmap2_node.c \
drd_clientobj.c \
drd_clientreq.c \
drd_cond.c \
diff --git a/main/drd/Makefile.in b/main/drd/Makefile.in
new file mode 100644
index 0000000..4093422
--- /dev/null
+++ b/main/drd/Makefile.in
@@ -0,0 +1,1800 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
+ $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+
+# On Android we must ask for non-executable stack, not sure why.
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_2 = -Wl,-z,noexecstack
+noinst_PROGRAMS = drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
+ $(am__EXEEXT_1) \
+ vgpreload_drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
+ $(am__EXEEXT_2)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_3 = drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = vgpreload_drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_5 = drd_darwin_intercepts.c
+subdir = drd
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_2 = vgpreload_drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+PROGRAMS = $(noinst_PROGRAMS)
+am__objects_1 = \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.$(OBJEXT) \
+ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.$(OBJEXT)
+am_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = \
+ $(am_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
+am__drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = drd_barrier.c \
+ drd_clientobj.c drd_clientreq.c drd_cond.c \
+ drd_cond_initializer.c drd_error.c drd_hb.c drd_load_store.c \
+ drd_main.c drd_malloc_wrappers.c drd_mutex.c drd_rwlock.c \
+ drd_semaphore.c drd_suppression.c
+am__objects_2 = \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.$(OBJEXT) \
+ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_2)
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+ $(am_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
+am__vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES_DIST = \
+ drd_pthread_intercepts.c drd_qtcore_intercepts.c \
+ drd_strmem_intercepts.c drd_darwin_intercepts.c
+@VGCONF_OS_IS_DARWIN_TRUE@am__objects_3 = vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.$(OBJEXT)
+am__objects_4 = vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.$(OBJEXT) \
+ vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.$(OBJEXT) \
+ vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.$(OBJEXT) \
+ $(am__objects_3)
+am_vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = \
+ $(am__objects_4)
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = \
+ $(am_vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am__vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES_DIST = \
+ drd_pthread_intercepts.c drd_qtcore_intercepts.c \
+ drd_strmem_intercepts.c drd_darwin_intercepts.c
+@VGCONF_OS_IS_DARWIN_TRUE@am__objects_5 = vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.$(OBJEXT)
+am__objects_6 = vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.$(OBJEXT) \
+ vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.$(OBJEXT) \
+ vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.$(OBJEXT) \
+ $(am__objects_5)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_6)
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS = \
+ $(am_vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES) \
+ $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES) \
+ $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES)
+DIST_SOURCES = $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(am__drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST) \
+ $(am__vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES_DIST) \
+ $(am__vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES_DIST)
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
+am__vpath_adj = case $$p in \
+ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
+ *) f=$$p;; \
+ esac;
+am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;
+am__install_max = 40
+am__nobase_strip_setup = \
+ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`
+am__nobase_strip = \
+ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"
+am__nobase_list = $(am__nobase_strip_setup); \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \
+ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \
+ if (++n[$$2] == $(am__install_max)) \
+ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \
+ END { for (dir in files) print dir, files[dir] }'
+am__base_list = \
+ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \
+ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'
+am__installdirs = "$(DESTDIR)$(pkgincludedir)"
+HEADERS = $(noinst_HEADERS) $(pkginclude_HEADERS)
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DIST_SUBDIRS = $(SUBDIRS)
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+SUBDIRS = . tests
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+#----------------------------------------------------------------------------
+# <tool>-<platform> stuff
+#----------------------------------------------------------------------------
+TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+
+TOOL_LDADD_COMMON = -lgcc
+TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) $(TOOL_LDADD_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
+
+
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+ -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_X86_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_AMD64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_PPC32_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_PPC64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_ARM_LINUX = $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
+ $(am__append_2)
+TOOL_LDFLAGS_S390X_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_X86_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386
+
+TOOL_LDFLAGS_AMD64_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+
+
+# MIPS Linux default start symbol is __start, not _start like on x86 or amd
+TOOL_LDFLAGS_MIPS32_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
+ @FLAG_M32@
+
+
+# NB for 64-bit darwin. We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them). Although such setting is probably
+# better done in link_tool_exe.c.
+#
+# -Wl,-pagezero_size,0x100000000
+
+#----------------------------------------------------------------------------
+# vgpreload_<tool>-<platform>.a stuff
+#----------------------------------------------------------------------------
+LIBREPLACEMALLOC_X86_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-linux.a
+
+LIBREPLACEMALLOC_AMD64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-linux.a
+
+LIBREPLACEMALLOC_PPC32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a
+
+LIBREPLACEMALLOC_PPC64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a
+
+LIBREPLACEMALLOC_ARM_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a
+
+LIBREPLACEMALLOC_X86_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-darwin.a
+
+LIBREPLACEMALLOC_AMD64_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-darwin.a
+
+LIBREPLACEMALLOC_S390X_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-s390x-linux.a
+
+LIBREPLACEMALLOC_MIPS32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips32-linux.a
+
+LIBREPLACEMALLOC_LDFLAGS_X86_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_X86_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_AMD64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC32_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_ARM_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_X86_DARWIN = \
+ $(LIBREPLACEMALLOC_X86_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_DARWIN = \
+ $(LIBREPLACEMALLOC_AMD64_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_S390X_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_S390X_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_MIPS32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_MIPS32_LINUX) \
+ -Wl,--no-whole-archive
+
+EXTRA_DIST = docs/drd-manual.xml docs/drd-xml-output.xsd
+
+#----------------------------------------------------------------------------
+# Headers, flags
+#----------------------------------------------------------------------------
+pkginclude_HEADERS = drd.h
+noinst_HEADERS = \
+ drd_barrier.h \
+ drd_basics.h \
+ drd_bitmap.c \
+ drd_bitmap.h \
+ drd_clientobj.h \
+ drd_clientreq.h \
+ drd_cond.h \
+ drd_error.h \
+ drd_hb.h \
+ drd_load_store.h \
+ drd_malloc_wrappers.h \
+ drd_mutex.h \
+ drd_rwlock.h \
+ drd_segment.c \
+ drd_segment.h \
+ drd_semaphore.h \
+ drd_suppression.h \
+ drd_thread.c \
+ drd_thread.h \
+ drd_thread_bitmap.h \
+ drd_vc.c \
+ drd_vc.h \
+ pub_drd_bitmap.h
+
+DRD_CFLAGS = \
+ @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@ \
+ -O2 \
+ @FLAG_W_EXTRA@ \
+ -Wformat-nonliteral \
+ -Wno-inline \
+ -Wno-unused-parameter
+
+DRD_SOURCES_COMMON = \
+ drd_barrier.c \
+ drd_clientobj.c \
+ drd_clientreq.c \
+ drd_cond.c \
+ drd_cond_initializer.c \
+ drd_error.c \
+ drd_hb.c \
+ drd_load_store.c \
+ drd_main.c \
+ drd_malloc_wrappers.c \
+ drd_mutex.c \
+ drd_rwlock.c \
+ drd_semaphore.c \
+ drd_suppression.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+ $(DRD_SOURCES_COMMON)
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(DRD_CFLAGS)
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@)
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
+ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
+ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+ @VALT_LOAD_ADDRESS_PRI@ \
+ $(LINK) \
+ $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+ $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(DRD_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) $(DRD_CFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
+VGPRELOAD_DRD_SOURCES_COMMON = drd_pthread_intercepts.c \
+ drd_qtcore_intercepts.c drd_strmem_intercepts.c \
+ $(am__append_5)
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \
+ $(VGPRELOAD_DRD_SOURCES_COMMON)
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(AM_CFLAGS_PIC) $(DRD_CFLAGS)
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \
+ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_PRI_CAPS@)
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
+ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
+ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(VGPRELOAD_DRD_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) $(AM_CFLAGS_PIC) $(DRD_CFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign drd/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign drd/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-noinstPROGRAMS:
+ -test -z "$(noinst_PROGRAMS)" || rm -f $(noinst_PROGRAMS)
+drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT): $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT)
+ $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD) $(LIBS)
+drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT): $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+ $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD) $(LIBS)
+vgpreload_drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD) $(LIBS)
+vgpreload_drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.o: drd_barrier.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.o `test -f 'drd_barrier.c' || echo '$(srcdir)/'`drd_barrier.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_barrier.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.o `test -f 'drd_barrier.c' || echo '$(srcdir)/'`drd_barrier.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.obj: drd_barrier.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.obj `if test -f 'drd_barrier.c'; then $(CYGPATH_W) 'drd_barrier.c'; else $(CYGPATH_W) '$(srcdir)/drd_barrier.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_barrier.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_barrier.obj `if test -f 'drd_barrier.c'; then $(CYGPATH_W) 'drd_barrier.c'; else $(CYGPATH_W) '$(srcdir)/drd_barrier.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.o: drd_clientobj.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.o `test -f 'drd_clientobj.c' || echo '$(srcdir)/'`drd_clientobj.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_clientobj.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.o `test -f 'drd_clientobj.c' || echo '$(srcdir)/'`drd_clientobj.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.obj: drd_clientobj.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.obj `if test -f 'drd_clientobj.c'; then $(CYGPATH_W) 'drd_clientobj.c'; else $(CYGPATH_W) '$(srcdir)/drd_clientobj.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_clientobj.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.obj `if test -f 'drd_clientobj.c'; then $(CYGPATH_W) 'drd_clientobj.c'; else $(CYGPATH_W) '$(srcdir)/drd_clientobj.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.o: drd_clientreq.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.o `test -f 'drd_clientreq.c' || echo '$(srcdir)/'`drd_clientreq.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_clientreq.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.o `test -f 'drd_clientreq.c' || echo '$(srcdir)/'`drd_clientreq.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.obj: drd_clientreq.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.obj `if test -f 'drd_clientreq.c'; then $(CYGPATH_W) 'drd_clientreq.c'; else $(CYGPATH_W) '$(srcdir)/drd_clientreq.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_clientreq.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.obj `if test -f 'drd_clientreq.c'; then $(CYGPATH_W) 'drd_clientreq.c'; else $(CYGPATH_W) '$(srcdir)/drd_clientreq.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.o: drd_cond.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.o `test -f 'drd_cond.c' || echo '$(srcdir)/'`drd_cond.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_cond.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.o `test -f 'drd_cond.c' || echo '$(srcdir)/'`drd_cond.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.obj: drd_cond.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.obj `if test -f 'drd_cond.c'; then $(CYGPATH_W) 'drd_cond.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_cond.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.obj `if test -f 'drd_cond.c'; then $(CYGPATH_W) 'drd_cond.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o: drd_cond_initializer.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o `test -f 'drd_cond_initializer.c' || echo '$(srcdir)/'`drd_cond_initializer.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_cond_initializer.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o `test -f 'drd_cond_initializer.c' || echo '$(srcdir)/'`drd_cond_initializer.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj: drd_cond_initializer.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj `if test -f 'drd_cond_initializer.c'; then $(CYGPATH_W) 'drd_cond_initializer.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond_initializer.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_cond_initializer.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj `if test -f 'drd_cond_initializer.c'; then $(CYGPATH_W) 'drd_cond_initializer.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond_initializer.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o: drd_error.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o `test -f 'drd_error.c' || echo '$(srcdir)/'`drd_error.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_error.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o `test -f 'drd_error.c' || echo '$(srcdir)/'`drd_error.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.obj: drd_error.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.obj `if test -f 'drd_error.c'; then $(CYGPATH_W) 'drd_error.c'; else $(CYGPATH_W) '$(srcdir)/drd_error.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_error.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.obj `if test -f 'drd_error.c'; then $(CYGPATH_W) 'drd_error.c'; else $(CYGPATH_W) '$(srcdir)/drd_error.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.o: drd_hb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.o `test -f 'drd_hb.c' || echo '$(srcdir)/'`drd_hb.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_hb.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.o `test -f 'drd_hb.c' || echo '$(srcdir)/'`drd_hb.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.obj: drd_hb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.obj `if test -f 'drd_hb.c'; then $(CYGPATH_W) 'drd_hb.c'; else $(CYGPATH_W) '$(srcdir)/drd_hb.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_hb.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.obj `if test -f 'drd_hb.c'; then $(CYGPATH_W) 'drd_hb.c'; else $(CYGPATH_W) '$(srcdir)/drd_hb.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.o: drd_load_store.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.o `test -f 'drd_load_store.c' || echo '$(srcdir)/'`drd_load_store.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_load_store.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.o `test -f 'drd_load_store.c' || echo '$(srcdir)/'`drd_load_store.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.obj: drd_load_store.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.obj `if test -f 'drd_load_store.c'; then $(CYGPATH_W) 'drd_load_store.c'; else $(CYGPATH_W) '$(srcdir)/drd_load_store.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_load_store.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.obj `if test -f 'drd_load_store.c'; then $(CYGPATH_W) 'drd_load_store.c'; else $(CYGPATH_W) '$(srcdir)/drd_load_store.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.o: drd_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.o `test -f 'drd_main.c' || echo '$(srcdir)/'`drd_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_main.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.o `test -f 'drd_main.c' || echo '$(srcdir)/'`drd_main.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.obj: drd_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.obj `if test -f 'drd_main.c'; then $(CYGPATH_W) 'drd_main.c'; else $(CYGPATH_W) '$(srcdir)/drd_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_main.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_main.obj `if test -f 'drd_main.c'; then $(CYGPATH_W) 'drd_main.c'; else $(CYGPATH_W) '$(srcdir)/drd_main.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.o: drd_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.o `test -f 'drd_malloc_wrappers.c' || echo '$(srcdir)/'`drd_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_malloc_wrappers.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.o `test -f 'drd_malloc_wrappers.c' || echo '$(srcdir)/'`drd_malloc_wrappers.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.obj: drd_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.obj `if test -f 'drd_malloc_wrappers.c'; then $(CYGPATH_W) 'drd_malloc_wrappers.c'; else $(CYGPATH_W) '$(srcdir)/drd_malloc_wrappers.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_malloc_wrappers.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_malloc_wrappers.obj `if test -f 'drd_malloc_wrappers.c'; then $(CYGPATH_W) 'drd_malloc_wrappers.c'; else $(CYGPATH_W) '$(srcdir)/drd_malloc_wrappers.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.o: drd_mutex.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.o `test -f 'drd_mutex.c' || echo '$(srcdir)/'`drd_mutex.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_mutex.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.o `test -f 'drd_mutex.c' || echo '$(srcdir)/'`drd_mutex.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.obj: drd_mutex.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.obj `if test -f 'drd_mutex.c'; then $(CYGPATH_W) 'drd_mutex.c'; else $(CYGPATH_W) '$(srcdir)/drd_mutex.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_mutex.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_mutex.obj `if test -f 'drd_mutex.c'; then $(CYGPATH_W) 'drd_mutex.c'; else $(CYGPATH_W) '$(srcdir)/drd_mutex.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.o: drd_rwlock.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.o `test -f 'drd_rwlock.c' || echo '$(srcdir)/'`drd_rwlock.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_rwlock.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.o `test -f 'drd_rwlock.c' || echo '$(srcdir)/'`drd_rwlock.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.obj: drd_rwlock.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.obj `if test -f 'drd_rwlock.c'; then $(CYGPATH_W) 'drd_rwlock.c'; else $(CYGPATH_W) '$(srcdir)/drd_rwlock.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_rwlock.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_rwlock.obj `if test -f 'drd_rwlock.c'; then $(CYGPATH_W) 'drd_rwlock.c'; else $(CYGPATH_W) '$(srcdir)/drd_rwlock.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.o: drd_semaphore.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.o `test -f 'drd_semaphore.c' || echo '$(srcdir)/'`drd_semaphore.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_semaphore.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.o `test -f 'drd_semaphore.c' || echo '$(srcdir)/'`drd_semaphore.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.obj: drd_semaphore.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.obj `if test -f 'drd_semaphore.c'; then $(CYGPATH_W) 'drd_semaphore.c'; else $(CYGPATH_W) '$(srcdir)/drd_semaphore.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_semaphore.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_semaphore.obj `if test -f 'drd_semaphore.c'; then $(CYGPATH_W) 'drd_semaphore.c'; else $(CYGPATH_W) '$(srcdir)/drd_semaphore.c'; fi`
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.o: drd_suppression.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.o `test -f 'drd_suppression.c' || echo '$(srcdir)/'`drd_suppression.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_suppression.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.o `test -f 'drd_suppression.c' || echo '$(srcdir)/'`drd_suppression.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.obj: drd_suppression.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.obj `if test -f 'drd_suppression.c'; then $(CYGPATH_W) 'drd_suppression.c'; else $(CYGPATH_W) '$(srcdir)/drd_suppression.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_suppression.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_suppression.obj `if test -f 'drd_suppression.c'; then $(CYGPATH_W) 'drd_suppression.c'; else $(CYGPATH_W) '$(srcdir)/drd_suppression.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.o: drd_barrier.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.o `test -f 'drd_barrier.c' || echo '$(srcdir)/'`drd_barrier.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_barrier.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.o `test -f 'drd_barrier.c' || echo '$(srcdir)/'`drd_barrier.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.obj: drd_barrier.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.obj `if test -f 'drd_barrier.c'; then $(CYGPATH_W) 'drd_barrier.c'; else $(CYGPATH_W) '$(srcdir)/drd_barrier.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_barrier.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.obj `if test -f 'drd_barrier.c'; then $(CYGPATH_W) 'drd_barrier.c'; else $(CYGPATH_W) '$(srcdir)/drd_barrier.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.o: drd_clientobj.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.o `test -f 'drd_clientobj.c' || echo '$(srcdir)/'`drd_clientobj.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_clientobj.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.o `test -f 'drd_clientobj.c' || echo '$(srcdir)/'`drd_clientobj.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.obj: drd_clientobj.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.obj `if test -f 'drd_clientobj.c'; then $(CYGPATH_W) 'drd_clientobj.c'; else $(CYGPATH_W) '$(srcdir)/drd_clientobj.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_clientobj.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.obj `if test -f 'drd_clientobj.c'; then $(CYGPATH_W) 'drd_clientobj.c'; else $(CYGPATH_W) '$(srcdir)/drd_clientobj.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.o: drd_clientreq.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.o `test -f 'drd_clientreq.c' || echo '$(srcdir)/'`drd_clientreq.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_clientreq.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.o `test -f 'drd_clientreq.c' || echo '$(srcdir)/'`drd_clientreq.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.obj: drd_clientreq.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.obj `if test -f 'drd_clientreq.c'; then $(CYGPATH_W) 'drd_clientreq.c'; else $(CYGPATH_W) '$(srcdir)/drd_clientreq.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_clientreq.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.obj `if test -f 'drd_clientreq.c'; then $(CYGPATH_W) 'drd_clientreq.c'; else $(CYGPATH_W) '$(srcdir)/drd_clientreq.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.o: drd_cond.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.o `test -f 'drd_cond.c' || echo '$(srcdir)/'`drd_cond.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_cond.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.o `test -f 'drd_cond.c' || echo '$(srcdir)/'`drd_cond.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.obj: drd_cond.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.obj `if test -f 'drd_cond.c'; then $(CYGPATH_W) 'drd_cond.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_cond.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.obj `if test -f 'drd_cond.c'; then $(CYGPATH_W) 'drd_cond.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o: drd_cond_initializer.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o `test -f 'drd_cond_initializer.c' || echo '$(srcdir)/'`drd_cond_initializer.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_cond_initializer.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o `test -f 'drd_cond_initializer.c' || echo '$(srcdir)/'`drd_cond_initializer.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj: drd_cond_initializer.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj `if test -f 'drd_cond_initializer.c'; then $(CYGPATH_W) 'drd_cond_initializer.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond_initializer.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_cond_initializer.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj `if test -f 'drd_cond_initializer.c'; then $(CYGPATH_W) 'drd_cond_initializer.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond_initializer.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o: drd_error.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o `test -f 'drd_error.c' || echo '$(srcdir)/'`drd_error.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_error.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o `test -f 'drd_error.c' || echo '$(srcdir)/'`drd_error.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.obj: drd_error.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.obj `if test -f 'drd_error.c'; then $(CYGPATH_W) 'drd_error.c'; else $(CYGPATH_W) '$(srcdir)/drd_error.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_error.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.obj `if test -f 'drd_error.c'; then $(CYGPATH_W) 'drd_error.c'; else $(CYGPATH_W) '$(srcdir)/drd_error.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.o: drd_hb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.o `test -f 'drd_hb.c' || echo '$(srcdir)/'`drd_hb.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_hb.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.o `test -f 'drd_hb.c' || echo '$(srcdir)/'`drd_hb.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.obj: drd_hb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.obj `if test -f 'drd_hb.c'; then $(CYGPATH_W) 'drd_hb.c'; else $(CYGPATH_W) '$(srcdir)/drd_hb.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_hb.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.obj `if test -f 'drd_hb.c'; then $(CYGPATH_W) 'drd_hb.c'; else $(CYGPATH_W) '$(srcdir)/drd_hb.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.o: drd_load_store.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.o `test -f 'drd_load_store.c' || echo '$(srcdir)/'`drd_load_store.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_load_store.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.o `test -f 'drd_load_store.c' || echo '$(srcdir)/'`drd_load_store.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.obj: drd_load_store.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.obj `if test -f 'drd_load_store.c'; then $(CYGPATH_W) 'drd_load_store.c'; else $(CYGPATH_W) '$(srcdir)/drd_load_store.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_load_store.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.obj `if test -f 'drd_load_store.c'; then $(CYGPATH_W) 'drd_load_store.c'; else $(CYGPATH_W) '$(srcdir)/drd_load_store.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.o: drd_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.o `test -f 'drd_main.c' || echo '$(srcdir)/'`drd_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_main.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.o `test -f 'drd_main.c' || echo '$(srcdir)/'`drd_main.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.obj: drd_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.obj `if test -f 'drd_main.c'; then $(CYGPATH_W) 'drd_main.c'; else $(CYGPATH_W) '$(srcdir)/drd_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_main.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_main.obj `if test -f 'drd_main.c'; then $(CYGPATH_W) 'drd_main.c'; else $(CYGPATH_W) '$(srcdir)/drd_main.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.o: drd_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.o `test -f 'drd_malloc_wrappers.c' || echo '$(srcdir)/'`drd_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_malloc_wrappers.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.o `test -f 'drd_malloc_wrappers.c' || echo '$(srcdir)/'`drd_malloc_wrappers.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.obj: drd_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.obj `if test -f 'drd_malloc_wrappers.c'; then $(CYGPATH_W) 'drd_malloc_wrappers.c'; else $(CYGPATH_W) '$(srcdir)/drd_malloc_wrappers.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_malloc_wrappers.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_malloc_wrappers.obj `if test -f 'drd_malloc_wrappers.c'; then $(CYGPATH_W) 'drd_malloc_wrappers.c'; else $(CYGPATH_W) '$(srcdir)/drd_malloc_wrappers.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.o: drd_mutex.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.o `test -f 'drd_mutex.c' || echo '$(srcdir)/'`drd_mutex.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_mutex.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.o `test -f 'drd_mutex.c' || echo '$(srcdir)/'`drd_mutex.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.obj: drd_mutex.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.obj `if test -f 'drd_mutex.c'; then $(CYGPATH_W) 'drd_mutex.c'; else $(CYGPATH_W) '$(srcdir)/drd_mutex.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_mutex.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_mutex.obj `if test -f 'drd_mutex.c'; then $(CYGPATH_W) 'drd_mutex.c'; else $(CYGPATH_W) '$(srcdir)/drd_mutex.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.o: drd_rwlock.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.o `test -f 'drd_rwlock.c' || echo '$(srcdir)/'`drd_rwlock.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_rwlock.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.o `test -f 'drd_rwlock.c' || echo '$(srcdir)/'`drd_rwlock.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.obj: drd_rwlock.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.obj `if test -f 'drd_rwlock.c'; then $(CYGPATH_W) 'drd_rwlock.c'; else $(CYGPATH_W) '$(srcdir)/drd_rwlock.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_rwlock.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_rwlock.obj `if test -f 'drd_rwlock.c'; then $(CYGPATH_W) 'drd_rwlock.c'; else $(CYGPATH_W) '$(srcdir)/drd_rwlock.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.o: drd_semaphore.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.o `test -f 'drd_semaphore.c' || echo '$(srcdir)/'`drd_semaphore.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_semaphore.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.o `test -f 'drd_semaphore.c' || echo '$(srcdir)/'`drd_semaphore.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.obj: drd_semaphore.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.obj `if test -f 'drd_semaphore.c'; then $(CYGPATH_W) 'drd_semaphore.c'; else $(CYGPATH_W) '$(srcdir)/drd_semaphore.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_semaphore.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_semaphore.obj `if test -f 'drd_semaphore.c'; then $(CYGPATH_W) 'drd_semaphore.c'; else $(CYGPATH_W) '$(srcdir)/drd_semaphore.c'; fi`
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.o: drd_suppression.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.o `test -f 'drd_suppression.c' || echo '$(srcdir)/'`drd_suppression.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_suppression.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.o `test -f 'drd_suppression.c' || echo '$(srcdir)/'`drd_suppression.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.obj: drd_suppression.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.obj `if test -f 'drd_suppression.c'; then $(CYGPATH_W) 'drd_suppression.c'; else $(CYGPATH_W) '$(srcdir)/drd_suppression.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_suppression.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_suppression.obj `if test -f 'drd_suppression.c'; then $(CYGPATH_W) 'drd_suppression.c'; else $(CYGPATH_W) '$(srcdir)/drd_suppression.c'; fi`
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.o: drd_pthread_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.o `test -f 'drd_pthread_intercepts.c' || echo '$(srcdir)/'`drd_pthread_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_pthread_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.o `test -f 'drd_pthread_intercepts.c' || echo '$(srcdir)/'`drd_pthread_intercepts.c
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.obj: drd_pthread_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.obj `if test -f 'drd_pthread_intercepts.c'; then $(CYGPATH_W) 'drd_pthread_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_pthread_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_pthread_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.obj `if test -f 'drd_pthread_intercepts.c'; then $(CYGPATH_W) 'drd_pthread_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_pthread_intercepts.c'; fi`
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.o: drd_qtcore_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.o `test -f 'drd_qtcore_intercepts.c' || echo '$(srcdir)/'`drd_qtcore_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_qtcore_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.o `test -f 'drd_qtcore_intercepts.c' || echo '$(srcdir)/'`drd_qtcore_intercepts.c
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj: drd_qtcore_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj `if test -f 'drd_qtcore_intercepts.c'; then $(CYGPATH_W) 'drd_qtcore_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_qtcore_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_qtcore_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj `if test -f 'drd_qtcore_intercepts.c'; then $(CYGPATH_W) 'drd_qtcore_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_qtcore_intercepts.c'; fi`
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.o: drd_strmem_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.o `test -f 'drd_strmem_intercepts.c' || echo '$(srcdir)/'`drd_strmem_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_strmem_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.o `test -f 'drd_strmem_intercepts.c' || echo '$(srcdir)/'`drd_strmem_intercepts.c
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.obj: drd_strmem_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.obj `if test -f 'drd_strmem_intercepts.c'; then $(CYGPATH_W) 'drd_strmem_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_strmem_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_strmem_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.obj `if test -f 'drd_strmem_intercepts.c'; then $(CYGPATH_W) 'drd_strmem_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_strmem_intercepts.c'; fi`
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.o: drd_darwin_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.o `test -f 'drd_darwin_intercepts.c' || echo '$(srcdir)/'`drd_darwin_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_darwin_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.o `test -f 'drd_darwin_intercepts.c' || echo '$(srcdir)/'`drd_darwin_intercepts.c
+
+vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.obj: drd_darwin_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.obj `if test -f 'drd_darwin_intercepts.c'; then $(CYGPATH_W) 'drd_darwin_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_darwin_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_darwin_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_darwin_intercepts.obj `if test -f 'drd_darwin_intercepts.c'; then $(CYGPATH_W) 'drd_darwin_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_darwin_intercepts.c'; fi`
+
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.o: drd_pthread_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.o `test -f 'drd_pthread_intercepts.c' || echo '$(srcdir)/'`drd_pthread_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_pthread_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.o `test -f 'drd_pthread_intercepts.c' || echo '$(srcdir)/'`drd_pthread_intercepts.c
+
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.obj: drd_pthread_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.obj `if test -f 'drd_pthread_intercepts.c'; then $(CYGPATH_W) 'drd_pthread_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_pthread_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_pthread_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_pthread_intercepts.obj `if test -f 'drd_pthread_intercepts.c'; then $(CYGPATH_W) 'drd_pthread_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_pthread_intercepts.c'; fi`
+
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.o: drd_qtcore_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.o `test -f 'drd_qtcore_intercepts.c' || echo '$(srcdir)/'`drd_qtcore_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_qtcore_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.o `test -f 'drd_qtcore_intercepts.c' || echo '$(srcdir)/'`drd_qtcore_intercepts.c
+
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj: drd_qtcore_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj `if test -f 'drd_qtcore_intercepts.c'; then $(CYGPATH_W) 'drd_qtcore_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_qtcore_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_qtcore_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_qtcore_intercepts.obj `if test -f 'drd_qtcore_intercepts.c'; then $(CYGPATH_W) 'drd_qtcore_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_qtcore_intercepts.c'; fi`
+
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.o: drd_strmem_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.o `test -f 'drd_strmem_intercepts.c' || echo '$(srcdir)/'`drd_strmem_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_strmem_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.o `test -f 'drd_strmem_intercepts.c' || echo '$(srcdir)/'`drd_strmem_intercepts.c
+
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.obj: drd_strmem_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.obj `if test -f 'drd_strmem_intercepts.c'; then $(CYGPATH_W) 'drd_strmem_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_strmem_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_strmem_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_strmem_intercepts.obj `if test -f 'drd_strmem_intercepts.c'; then $(CYGPATH_W) 'drd_strmem_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_strmem_intercepts.c'; fi`
+
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.o: drd_darwin_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.o `test -f 'drd_darwin_intercepts.c' || echo '$(srcdir)/'`drd_darwin_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_darwin_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.o `test -f 'drd_darwin_intercepts.c' || echo '$(srcdir)/'`drd_darwin_intercepts.c
+
+vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.obj: drd_darwin_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.Tpo -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.obj `if test -f 'drd_darwin_intercepts.c'; then $(CYGPATH_W) 'drd_darwin_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_darwin_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.Tpo $(DEPDIR)/vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='drd_darwin_intercepts.c' object='vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-drd_darwin_intercepts.obj `if test -f 'drd_darwin_intercepts.c'; then $(CYGPATH_W) 'drd_darwin_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/drd_darwin_intercepts.c'; fi`
+install-pkgincludeHEADERS: $(pkginclude_HEADERS)
+ @$(NORMAL_INSTALL)
+ test -z "$(pkgincludedir)" || $(MKDIR_P) "$(DESTDIR)$(pkgincludedir)"
+ @list='$(pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ for p in $$list; do \
+ if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+ echo "$$d$$p"; \
+ done | $(am__base_list) | \
+ while read files; do \
+ echo " $(INSTALL_HEADER) $$files '$(DESTDIR)$(pkgincludedir)'"; \
+ $(INSTALL_HEADER) $$files "$(DESTDIR)$(pkgincludedir)" || exit $$?; \
+ done
+
+uninstall-pkgincludeHEADERS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
+ test -n "$$files" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(pkgincludedir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(pkgincludedir)" && rm -f $$files
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+check: check-recursive
+all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
+installdirs: installdirs-recursive
+installdirs-am:
+ for dir in "$(DESTDIR)$(pkgincludedir)"; do \
+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ done
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-generic clean-local clean-noinstPROGRAMS \
+ mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am: install-pkgincludeHEADERS
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am: install-exec-local
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am: uninstall-pkgincludeHEADERS
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+ install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am all-local check check-am clean clean-generic \
+ clean-local clean-noinstPROGRAMS ctags ctags-recursive \
+ distclean distclean-compile distclean-generic distclean-tags \
+ distdir dvi dvi-am html html-am info info-am install \
+ install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-exec-local \
+ install-html install-html-am install-info install-info-am \
+ install-man install-pdf install-pdf-am \
+ install-pkgincludeHEADERS install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ installdirs-am maintainer-clean maintainer-clean-generic \
+ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \
+ ps ps-am tags tags-recursive uninstall uninstall-am \
+ uninstall-pkgincludeHEADERS
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+#----------------------------------------------------------------------------
+# General stuff
+#----------------------------------------------------------------------------
+
+all-local: inplace-noinst_PROGRAMS inplace-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/drd/TODO.txt b/main/drd/TODO.txt
deleted file mode 100644
index e69de29..0000000
--- a/main/drd/TODO.txt
+++ /dev/null
diff --git a/main/drd/Testing.txt b/main/drd/Testing.txt
deleted file mode 100644
index 4581a06..0000000
--- a/main/drd/Testing.txt
+++ /dev/null
@@ -1,89 +0,0 @@
-How to test DRD
-~~~~~~~~~~~~~~~
-
-1. Start with compiling DRD.
-
-2. Check as follows that all global symbols in DRD have been wrapped by the
- DRD_() macro (output must be empty):
- ( cd drd && nm -A drd*.o|grep ' T '|grep -v ' T vgDrd_' )
-
-3. Check as follows that all global symbols in the preloaded shared library
- are redirected functions (output must contain one symbol that starts with
- a double underscore, something like __i686.get_pc_thunk.bx):
- ( cd drd && nm -A vgpreload*.o|grep ' T '|grep -v ' T _vg' )
-
-4. Verify that all files needed for the regression tests are included in
- drd/tests/Makefile.am:
- (
- cd drd/tests;
- for f in *.vgtest *.exp*; do grep -q "$f" Makefile.am || echo $f; done
- )
-
-5. Verify that all files referenced in EXTRA_DIST in drd/tests/Makefile.am
- exist:
- (
- cd drd/tests;
- for e in $(awk '/\\$/{n=$0; sub("\\\\$", "", n); if (line != "")\
- { line = line " " n } else { line=n }} \
- /[^\\]$/{if (line != ""){print line;line=""};print}' < Makefile.am \
- | sed -n 's/^EXTRA_DIST *=//p' | sed 's/..noinst_SCRIPTS.//')
- do
- [ -e "$e" ] || echo "$e"
- done
- )
-
-6. Run the regression tests as follows:
- perl tests/vg_regtest drd
-
-7. Run the regression tests that were developed for Thread Sanitizer:
- ./vg-in-place --tool=drd --check-stack-var=yes drd/tests/tsan_unittest 2>&1|less
-
-8. Test the slowdown for matinv for various matrix sizes via the script
- drd/scripts/run-matinv (must be about 25 for i == 1 and about
- 50 for i == 10 with n == 200).
-
-9. Test whether DRD works with standard KDE applications and whether it does
- not print any false positives. Test this both with KDE3 and KDE4 on Linux:
- ./vg-in-place --tool=drd --read-var-info=yes kate
- ./vg-in-place --tool=drd --read-var-info=yes --check-stack-var=yes kate
- ./vg-in-place --tool=drd --read-var-info=yes --trace-children=yes knode
- ./vg-in-place --tool=drd --read-var-info=yes --check-stack-var=yes --trace-children=yes knode
- ./vg-in-place --tool=drd --read-var-info=yes --check-stack-var=yes /usr/bin/designer
-
- and on Darwin:
- ./vg-in-place --tool=drd --trace-fork-join=yes --show-confl-seg=no --gen-suppressions=all /Applications/Utilities/Terminal.app/Contents/MacOS/Terminal
- ./vg-in-place --tool=drd --trace-fork-join=yes --show-confl-seg=no --gen-suppressions=all /Applications/Safari.app/Contents/MacOS/Safari
-
-10. Test whether DRD works with standard GNOME applications. Expect
- race reports triggered by ORBit_RootObject_duplicate() and after
- having closed the GNOME terminal window:
- ./vg-in-place --tool=drd --read-var-info=yes --trace-children=yes gnome-terminal
-
-11. Rerun the GraphicsMagick test suite:
- 1. Recompile gcc via drd/scripts/download-and-build-gcc.
- 2. Replace the distro-provided libgomp.so* by the newly compiled versions:
- cp $HOME/gcc-.../lib/libgomp.so.1.0.0.0 /usr/lib
- cp $HOME/gcc-.../lib64/libgomp.so.1.0.0.0 /usr/lib64
- rpm --verify libgomp43-32bit
- rpm --verify libgomp43
- 3. Build and install Valgrind in /usr:
- ./autogen.sh && ./configure --prefix=/usr CC=$HOME/gcc-4.4.0/bin/gcc \
- && make -s && make -s install
- 4. Download the GraphicsMagick source code:
- cvs -d :pserver:anonymous@cvs.graphicsmagick.org:/GraphicsMagick login
- cvs -d :pserver:anonymous@cvs.graphicsmagick.org:/GraphicsMagick co GraphicsMagick
- cd GraphicsMagick
- ./configure
- export OMP_NUM_THREADS=4
- make -j2 -s MEMCHECK="$HOME/software/valgrind/vg-in-place --tool=drd --check-stack-var=yes --read-var-info=yes --quiet" check
- 5. Expected result: 776 tests / 23 expected failures / 147m24s user time
- on a E8400 CPU @ 3 GHz.
-
-12. Test DRD with Firefox. First build and install Firefox 3:
- drd/scripts/download-and-build-firefox
- Now run the following command:
- LD_LIBRARY_PATH=$HOME/software/mozilla-build/dist/lib: ./vg-in-place --tool=drd --check-stack-var=yes --trace-children=yes --show-confl-seg=no $HOME/software/mozilla-build/dist/bin/firefox-bin
-
-13. Verify that the XML output matches the DRD XML output XSD.
-
- drd/tests/verify-xml-output
diff --git a/main/drd/docs/drd-manual.xml b/main/drd/docs/drd-manual.xml
index 79c39d3..a94d612 100644
--- a/main/drd/docs/drd-manual.xml
+++ b/main/drd/docs/drd-manual.xml
@@ -529,6 +529,18 @@
</varlistentry>
<varlistentry>
<term>
+ <option><![CDATA[--ptrace-addr=<address> [default: none]]]></option>
+ </term>
+ <listitem>
+ <para>
+ Trace all load and store activity for the specified address and keep
+ doing that even after the memory at that address has been freed and
+ reallocated.
+ </para>
+ </listitem>
+ </varlistentry>
+ <varlistentry>
+ <term>
<option><![CDATA[--trace-alloc=<yes|no> [default: no]]]></option>
</term>
<listitem>
@@ -1006,6 +1018,14 @@
</listitem>
<listitem>
<para>
+ The macro <literal>DRD_STOP_TRACING_VAR(x)</literal>. Stop tracing load
+ and store activity for the address range starting
+ at <literal>&x</literal> and occupying <literal>sizeof(x)</literal>
+ bytes.
+ </para>
+ </listitem>
+ <listitem>
+ <para>
The macro <literal>ANNOTATE_TRACE_MEMORY(&x)</literal>. Trace all
load and store activity that touches at least the single byte at the
address <literal>&x</literal>.
@@ -1727,12 +1747,6 @@
</listitem>
<listitem>
<para>
- When address tracing is enabled, no information on atomic stores
- will be displayed.
- </para>
- </listitem>
- <listitem>
- <para>
If you compile the DRD source code yourself, you need GCC 3.0 or
later. GCC 2.95 is not supported.
</para>
diff --git a/main/drd/docs/drd-xml-output.xsd b/main/drd/docs/drd-xml-output.xsd
new file mode 100644
index 0000000..1243473
--- /dev/null
+++ b/main/drd/docs/drd-xml-output.xsd
@@ -0,0 +1,238 @@
+<?xml version="1.0" encoding="utf-8"?>
+<xs:schema elementFormDefault="qualified" xmlns:xs="http://www.w3.org/2001/XMLSchema">
+ <!-- Header printed by Valgrind tool as multiple lines of text -->
+ <xs:complexType name="vgPreamble">
+ <xs:sequence>
+ <xs:element name="line" type="xs:string"
+ minOccurs="0" maxOccurs="unbounded"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <!-- Name and value of an environment variable used in XML output file name via %q{...} -->
+ <xs:complexType name="vgLogfileQual">
+ <xs:sequence>
+ <xs:element name="var" type="xs:string"/>
+ <xs:element name="value" type="xs:string"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <!-- User comment specified via xml-user-comment=... -->
+ <xs:complexType name="vgUserComment">
+ <xs:sequence>
+ <xs:any processContents="lax" minOccurs="0" maxOccurs="unbounded"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <!-- Executable path and arguments -->
+ <xs:complexType name="vgExeAndArgs">
+ <xs:sequence>
+ <xs:element name="exe" type="xs:string"/>
+ <xs:element name="arg" type="xs:string"
+ minOccurs="0" maxOccurs="unbounded"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <!-- Valgrind tool and client executable path and arguments -->
+ <xs:complexType name="vgArgs">
+ <xs:sequence>
+ <xs:element name="vargv" type="vgExeAndArgs"/>
+ <xs:element name="argv" type="vgExeAndArgs"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:simpleType name="vgSchedState">
+ <xs:restriction base="xs:string">
+ <xs:enumeration value="RUNNING"/>
+ <xs:enumeration value="FINISHED"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <!-- Valgrind scheduler state and time at which a state has been reached -->
+ <xs:complexType name="vgSchedulerStatus">
+ <xs:sequence>
+ <xs:element name="state" type="vgSchedState"/>
+ <xs:element name="time" type="xs:string"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:complexType name="vgSupprFrame">
+ <xs:choice>
+ <xs:element name="fun" type="xs:string"/>
+ <xs:element name="obj" type="xs:string"/>
+ </xs:choice>
+ </xs:complexType>
+
+ <!-- Client call stack -->
+ <xs:complexType name="vgStack">
+ <xs:sequence>
+ <xs:element name="frame" minOccurs="0" maxOccurs="unbounded">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="ip" type="xs:string"/>
+ <xs:element name="obj" type="xs:string" minOccurs="0"/>
+ <xs:element name="fn" type="xs:string" minOccurs="0"/>
+ <xs:element name="dir" type="xs:string" minOccurs="0"/>
+ <xs:element name="file" type="xs:string" minOccurs="0"/>
+ <xs:element name="line" type="xs:string" minOccurs="0"/>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:complexType name="vgErrorCount">
+ <xs:sequence>
+ <xs:element name="pair" minOccurs="0" maxOccurs="unbounded">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="count" type="xs:integer"/>
+ <xs:element name="unique" type="xs:string"/>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:complexType name="vgSuppCount">
+ <xs:sequence>
+ <xs:element name="pair" minOccurs="0" maxOccurs="unbounded">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="count" type="xs:integer"/>
+ <xs:element name="name" type="xs:string"/>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:simpleType name="drdErrorKind">
+ <xs:restriction base="xs:string">
+ <xs:enumeration value="ConflictingAccess"/>
+ <xs:enumeration value="MutexErr"/>
+ <xs:enumeration value="CondErr"/>
+ <xs:enumeration value="CondDestrErr"/>
+ <xs:enumeration value="CondRaceErr"/>
+ <xs:enumeration value="CondWaitErr"/>
+ <xs:enumeration value="SemaphoreErr"/>
+ <xs:enumeration value="BarrierErr"/>
+ <xs:enumeration value="RwlockErr"/>
+ <xs:enumeration value="HoldtimeErr"/>
+ <xs:enumeration value="GenericErr"/>
+ <xs:enumeration value="InvalidThreadId"/>
+ <xs:enumeration value="UnimpHgClReq"/>
+ <xs:enumeration value="UnimpDrdClReq"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <!-- Same as drdErrorKind but with the "drd:" prefix -->
+ <xs:simpleType name="drdSuppressionKind">
+ <xs:restriction base="xs:string">
+ <xs:enumeration value="drd:ConflictingAccess"/>
+ <xs:enumeration value="drd:MutexErr"/>
+ <xs:enumeration value="drd:CondErr"/>
+ <xs:enumeration value="drd:CondDestrErr"/>
+ <xs:enumeration value="drd:CondRaceErr"/>
+ <xs:enumeration value="drd:CondWaitErr"/>
+ <xs:enumeration value="drd:SemaphoreErr"/>
+ <xs:enumeration value="drd:BarrierErr"/>
+ <xs:enumeration value="drd:RwlockErr"/>
+ <xs:enumeration value="drd:HoldtimeErr"/>
+ <xs:enumeration value="drd:GenericErr"/>
+ <xs:enumeration value="drd:InvalidThreadId"/>
+ <xs:enumeration value="drd:UnimpHgClReq"/>
+ <xs:enumeration value="drd:UnimpDrdClReq"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <!-- Single line of trace information with an optional call stack -->
+ <xs:complexType name="drdTrace">
+ <xs:sequence>
+ <xs:element name="text" type="xs:string"/>
+ <xs:element name="stack" type="vgStack" minOccurs="0"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <!-- Context information about a DRD error -->
+ <xs:complexType name="drdContext">
+ <xs:sequence>
+ <xs:element name="what" type="xs:string" minOccurs="0"/>
+ <xs:element name="address" type="xs:string" minOccurs="0"/>
+ <xs:element name="stack" type="vgStack"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:complexType name="drdSuppression">
+ <xs:sequence>
+ <xs:element name="sname" type="xs:string"/>
+ <xs:element name="skind" type="drdSuppressionKind"/>
+ <xs:element name="skaux" type="xs:string" minOccurs="0"/>
+ <xs:element name="sframe" type="vgSupprFrame"
+ minOccurs="0" maxOccurs="unbounded"/>
+ <xs:element name="rawtext" type="xs:string"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:complexType name="drdError">
+ <xs:sequence>
+ <xs:element name="unique" type="xs:string"/>
+ <xs:element name="tid" type="xs:integer"/>
+ <xs:element name="kind" type="drdErrorKind"/>
+ <xs:element name="acquired_at" type="drdContext" minOccurs="0"/>
+ <xs:element name="what" type="xs:string"/>
+ <xs:element name="stack" type="vgStack"/>
+ <xs:element name="auxwhat" type="xs:string" minOccurs="0"/>
+ <xs:element name="allocation_context" type="drdContext" minOccurs="0"/>
+ <xs:element name="confl_wait_call" type="drdContext"
+ minOccurs="0"/>
+ <xs:element name="first_observed_at" type="drdContext"
+ minOccurs="0" maxOccurs="3"/>
+ <xs:element name="xauxwhat" minOccurs="0">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="text" type="xs:string"/>
+ <xs:element name="file" type="xs:string"/>
+ <xs:element name="line" type="xs:integer"/>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ <xs:element name="other_segment_start" minOccurs="0">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="stack" type="vgStack" minOccurs="0"/>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ <xs:element name="other_segment_end" minOccurs="0">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="stack" type="vgStack" minOccurs="0"/>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ <xs:element name="suppression" type="drdSuppression" minOccurs="0"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:element name="valgrindoutput">
+ <xs:complexType>
+ <xs:choice maxOccurs="unbounded">
+ <xs:element name="protocolversion" type="xs:string"/>
+ <xs:element name="protocoltool" type="xs:string"/>
+ <xs:element name="preamble" type="vgPreamble"/>
+ <xs:element name="pid" type="xs:string"/>
+ <xs:element name="ppid" type="xs:string"/>
+ <xs:element name="tool" type="xs:string"/>
+ <xs:element name="logfilequalifier" type="vgLogfileQual" minOccurs="0"/>
+ <xs:element name="usercomment" type="vgUserComment" minOccurs="0"/>
+ <xs:element name="args" type="vgArgs"/>
+ <xs:element name="trace" type="drdTrace"/>
+ <xs:element name="error" type="drdError"
+ minOccurs="0" maxOccurs="unbounded"/>
+ <xs:element name="status" type="vgSchedulerStatus"/>
+ <xs:element name="errorcounts" type="vgErrorCount"/>
+ <xs:element name="suppcounts" type="vgSuppCount" minOccurs="0"/>
+ </xs:choice>
+ </xs:complexType>
+ </xs:element>
+</xs:schema>
diff --git a/main/drd/drd.h b/main/drd/drd.h
index 5f21aab..c3537d2 100644
--- a/main/drd/drd.h
+++ b/main/drd/drd.h
@@ -1,5 +1,3 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
-
/*
----------------------------------------------------------------
@@ -14,7 +12,7 @@
This file is part of DRD, a Valgrind tool for verification of
multithreaded programs.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -87,7 +85,7 @@
&(x), sizeof(x), 0, 0, 0)
/**
- * Tell DRD to trace all memory accesses on the specified variable.
+ * Tell DRD to trace all memory accesses for the specified variable
* until the memory that was allocated for the variable is freed.
*/
#define DRD_TRACE_VAR(x) \
@@ -95,6 +93,13 @@
&(x), sizeof(x), 0, 0, 0)
/**
+ * Tell DRD to stop tracing memory accesses for the specified variable.
+ */
+#define DRD_STOP_TRACING_VAR(x) \
+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DRD_STOP_TRACE_ADDR, \
+ &(x), sizeof(x), 0, 0, 0)
+
+/**
* @defgroup RaceDetectionAnnotations Data race detection annotations.
*
* @see See also the source file <a href="http://code.google.com/p/data-race-test/source/browse/trunk/dynamic_annotations/dynamic_annotations.h</a>
@@ -103,6 +108,8 @@
*/
/*@{*/
+#ifndef __HELGRIND_H
+
/**
* Tell DRD to insert a happens-before mark. addr is the address of an object
* that is not a pthread synchronization object.
@@ -123,6 +130,36 @@
VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DRD_ANNOTATE_HAPPENS_AFTER, \
addr, 0, 0, 0, 0)
+#else /* __HELGRIND_H */
+
+#undef ANNOTATE_CONDVAR_LOCK_WAIT
+#undef ANNOTATE_CONDVAR_WAIT
+#undef ANNOTATE_CONDVAR_SIGNAL
+#undef ANNOTATE_CONDVAR_SIGNAL_ALL
+#undef ANNOTATE_PURE_HAPPENS_BEFORE_MUTEX
+#undef ANNOTATE_PUBLISH_MEMORY_RANGE
+#undef ANNOTATE_BARRIER_INIT
+#undef ANNOTATE_BARRIER_WAIT_BEFORE
+#undef ANNOTATE_BARRIER_WAIT_AFTER
+#undef ANNOTATE_BARRIER_DESTROY
+#undef ANNOTATE_PCQ_CREATE
+#undef ANNOTATE_PCQ_DESTROY
+#undef ANNOTATE_PCQ_PUT
+#undef ANNOTATE_PCQ_GET
+#undef ANNOTATE_BENIGN_RACE
+#undef ANNOTATE_BENIGN_RACE_SIZED
+#undef ANNOTATE_IGNORE_READS_BEGIN
+#undef ANNOTATE_IGNORE_READS_END
+#undef ANNOTATE_IGNORE_WRITES_BEGIN
+#undef ANNOTATE_IGNORE_WRITES_END
+#undef ANNOTATE_IGNORE_READS_AND_WRITES_BEGIN
+#undef ANNOTATE_IGNORE_READS_AND_WRITES_END
+#undef ANNOTATE_NEW_MEMORY
+#undef ANNOTATE_TRACE_MEMORY
+#undef ANNOTATE_THREAD_NAME
+
+#endif /* __HELGRIND_H */
+
/**
* Tell DRD that waiting on the condition variable at address cv has succeeded
* and a lock on the mutex at address mtx is now held. Since DRD always inserts
@@ -176,6 +213,8 @@
/** Deprecated -- don't use this annotation. */
#define ANNOTATE_SWAP_MEMORY_RANGE(addr, size) do { } while(0)
+#ifndef __HELGRIND_H
+
/** Tell DRD that a reader-writer lock object has been initialized. */
#define ANNOTATE_RWLOCK_CREATE(rwlock) \
VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DRD_ANNOTATE_RWLOCK_CREATE, \
@@ -195,6 +234,8 @@
VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DRD_ANNOTATE_RWLOCK_ACQUIRED, \
rwlock, is_w, 0, 0, 0)
+#endif /* __HELGRIND_H */
+
/**
* Tell DRD that a reader lock has been acquired on a reader-writer
* synchronization object.
@@ -207,6 +248,8 @@
*/
#define ANNOTATE_WRITERLOCK_ACQUIRED(rwlock) ANNOTATE_RWLOCK_ACQUIRED(rwlock, 1)
+#ifndef __HELGRIND_H
+
/**
* Tell DRD that a reader-writer lock is about to be released. is_w == 1 means
* that a write lock is about to be released, is_w == 0 means that a read lock
@@ -216,6 +259,8 @@
VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DRD_ANNOTATE_RWLOCK_RELEASED, \
rwlock, is_w, 0, 0, 0);
+#endif /* __HELGRIND_H */
+
/**
* Tell DRD that a reader lock is about to be released.
*/
diff --git a/main/drd/drd_barrier.c b/main/drd/drd_barrier.c
index a6e9e6a..06da0ec 100644
--- a/main/drd/drd_barrier.c
+++ b/main/drd/drd_barrier.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -473,15 +472,14 @@
{
VectorClock old_vc;
- DRD_(vc_copy)(&old_vc, &DRD_(g_threadinfo)[tid].last->vc);
+ DRD_(vc_copy)(&old_vc, DRD_(thread_get_vc)(tid));
VG_(OSetGen_ResetIter)(oset);
for ( ; (r = VG_(OSetGen_Next)(oset)) != 0; )
{
if (r != q)
{
tl_assert(r->sg);
- DRD_(vc_combine)(&DRD_(g_threadinfo)[tid].last->vc,
- &r->sg->vc);
+ DRD_(vc_combine)(DRD_(thread_get_vc)(tid), &r->sg->vc);
}
}
DRD_(thread_update_conflict_set)(tid, &old_vc);
diff --git a/main/drd/drd_barrier.h b/main/drd/drd_barrier.h
index 0af536b..2db082e 100644
--- a/main/drd/drd_barrier.h
+++ b/main/drd/drd_barrier.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_basics.h b/main/drd/drd_basics.h
index fda3b89..f15b59c 100644
--- a/main/drd/drd_basics.h
+++ b/main/drd/drd_basics.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of DRD, a thread error detector.
- Copyright (C) 2009-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2009-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_bitmap.c b/main/drd/drd_bitmap.c
index 3297967..c5e8a1d 100644
--- a/main/drd/drd_bitmap.c
+++ b/main/drd/drd_bitmap.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -46,6 +45,7 @@
/* Local variables. */
+static OSet* s_bm2_set_template;
static ULong s_bitmap_creation_count;
static ULong s_bitmap_merge_count;
static ULong s_bitmap2_merge_count;
@@ -53,6 +53,21 @@
/* Function definitions. */
+void DRD_(bm_module_init)(void)
+{
+ tl_assert(!s_bm2_set_template);
+ s_bm2_set_template
+ = VG_(OSetGen_Create_With_Pool)(0, 0, VG_(malloc), "drd.bitmap.bn.2",
+ VG_(free), 512, sizeof(struct bitmap2));
+}
+
+void DRD_(bm_module_cleanup)(void)
+{
+ tl_assert(s_bm2_set_template);
+ VG_(OSetGen_Destroy)(s_bm2_set_template);
+ s_bm2_set_template = NULL;
+}
+
struct bitmap* DRD_(bm_new)()
{
struct bitmap* bm;
@@ -91,8 +106,7 @@
bm->cache[i].a1 = ~(UWord)1;
bm->cache[i].bm2 = 0;
}
- bm->oset = VG_(OSetGen_Create)(0, 0, DRD_(bm2_alloc_node),
- "drd.bitmap.bn.2", DRD_(bm2_free_node));
+ bm->oset = VG_(OSetGen_EmptyClone)(s_bm2_set_template);
s_bitmap_creation_count++;
}
@@ -328,6 +342,29 @@
return DRD_(bm_has_any_store)(bm, a1, a2);
}
+Bool DRD_(bm_has_any_load_g)(struct bitmap* const bm)
+{
+ struct bitmap2* bm2;
+
+ tl_assert(bm);
+
+ VG_(OSetGen_ResetIter)(bm->oset);
+ for ( ; (bm2 = VG_(OSetGen_Next)(bm->oset)) != NULL; ) {
+ Addr b_start;
+ Addr b_end;
+ UWord b0;
+ const struct bitmap1* const p1 = &bm2->bm1;
+
+ b_start = make_address(bm2->addr, 0);
+ b_end = make_address(bm2->addr + 1, 0);
+
+ for (b0 = address_lsb(b_start); b0 <= address_lsb(b_end - 1); b0++)
+ if (bm0_is_set(p1->bm0_r, b0))
+ return True;
+ }
+ return False;
+}
+
Bool
DRD_(bm_has_any_load)(struct bitmap* const bm, const Addr a1, const Addr a2)
{
diff --git a/main/drd/drd_bitmap.h b/main/drd/drd_bitmap.h
index 85bb767..b8a59f6 100644
--- a/main/drd/drd_bitmap.h
+++ b/main/drd/drd_bitmap.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -137,7 +136,8 @@
#define BITS_PER_UWORD (8U * sizeof(UWord))
/** Log2 of BITS_PER_UWORD. */
-#if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_arm)
+#if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_arm) \
+ || defined(VGA_mips32)
#define BITS_PER_BITS_PER_UWORD 5
#elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_s390x)
#define BITS_PER_BITS_PER_UWORD 6
diff --git a/main/drd/drd_bitmap2_node.c b/main/drd/drd_bitmap2_node.c
deleted file mode 100644
index 9be00aa..0000000
--- a/main/drd/drd_bitmap2_node.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
-/*
- This file is part of drd, a thread error detector.
-
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307, USA.
-
- The GNU General Public License is contained in the file COPYING.
-*/
-
-/*
- * Block allocator for second-level bitmap nodes. Each node consists of
- * an OSetGen node and a struct bitmap2. The code below allocates
- * NODES_PER_CHUNK nodes at a time.
- */
-
-
-#include "drd_basics.h" /* DRD_() */
-#include "drd_bitmap.h" /* struct bitmap2 */
-#include "pub_drd_bitmap.h"
-#include "pub_tool_basics.h" /* Addr, SizeT */
-#include "pub_tool_libcassert.h" /* tl_assert() */
-#include "pub_tool_libcbase.h" /* VG_ROUNDUP() */
-#include "pub_tool_libcprint.h" /* VG_(message)() */
-#include "pub_tool_mallocfree.h" /* VG_(malloc), VG_(free) */
-
-
-#define NODES_PER_CHUNCK 512
-
-
-/* Local type definitions. */
-
-struct block_allocator_chunk {
- struct block_allocator_chunk* next;
- struct block_allocator_chunk* prev;
- int nallocated;
- void* data;
- void* data_end;
- void* first_free;
-};
-
-
-/* Local variables. */
-
-static SizeT s_root_node_size;
-static SizeT s_bm2_node_size;
-static struct block_allocator_chunk* s_first;
-
-
-/* Function definitions. */
-
-/**
- * Allocate a new chunk and insert it at the start of the doubly-linked list
- * s_first.
- */
-static struct block_allocator_chunk* allocate_new_chunk(void)
-{
- struct block_allocator_chunk* p;
- int i;
-
- tl_assert(s_bm2_node_size > 0);
-
- p = VG_(malloc)("drd.bitmap.bac",
- sizeof(*p) + NODES_PER_CHUNCK * s_bm2_node_size);
- tl_assert(p);
- p->next = s_first;
- if (s_first)
- p->next->prev = p;
- s_first = p;
- p->prev = 0;
- p->nallocated = 0;
- p->data = (char*)p + sizeof(*p);
- tl_assert(p->data);
- p->data_end = (char*)(p->data) + NODES_PER_CHUNCK * s_bm2_node_size;
- p->first_free = p->data;
- for (i = 0; i < NODES_PER_CHUNCK - 1; i++)
- {
- *(void**)((char*)(p->data) + i * s_bm2_node_size)
- = (char*)(p->data) + (i + 1) * s_bm2_node_size;
- }
- tl_assert(i == NODES_PER_CHUNCK - 1);
- *(void**)((char*)(p->data) + i * s_bm2_node_size) = NULL;
-
- return p;
-}
-
-/** Free a chunk and remove it from the list of chunks. */
-static void free_chunk(struct block_allocator_chunk* const p)
-{
- tl_assert(p);
- tl_assert(p->nallocated == 0);
-
- if (p == s_first)
- s_first = p->next;
- else if (p->prev)
- p->prev->next = p->next;
- if (p->next)
- p->next->prev = p->prev;
- VG_(free)(p);
-}
-
-/** Allocate a node. */
-void* DRD_(bm2_alloc_node)(HChar* const ec, const SizeT szB)
-{
- /*
- * If szB < sizeof(struct bitmap2) then this function has been called to
- * allocate an AVL tree root node. Otherwise it has been called to allocate
- * an AVL tree branch or leaf node.
- */
- if (s_root_node_size == 0)
- s_root_node_size = szB;
- if (szB == s_root_node_size)
- return VG_(malloc)(ec, szB);
-
- while (True)
- {
- struct block_allocator_chunk* p;
-
- if (s_bm2_node_size == 0)
- s_bm2_node_size = szB;
- else
- tl_assert(s_bm2_node_size == szB);
-
- for (p = s_first; p; p = p->next)
- {
- if (p->first_free)
- {
- void* result;
-
- p->nallocated++;
- result = p->first_free;
- p->first_free = *(void**)(p->first_free);
- return result;
- }
- }
-
- allocate_new_chunk();
- }
-}
-
-/** Free a node. */
-void DRD_(bm2_free_node)(void* const bm2)
-{
- struct block_allocator_chunk* p;
-
- tl_assert(bm2);
-
- if (s_bm2_node_size > 0) {
- for (p = s_first; p; p = p->next) {
- if (p->data <= bm2 && bm2 < p->data_end) {
- /* Free a non-root AVL tree node. */
- tl_assert(((char*)bm2 - (char*)(p->data)) % s_bm2_node_size == 0);
- *(void**)bm2 = p->first_free;
- p->first_free = bm2;
- tl_assert(p->nallocated >= 1);
- if (--(p->nallocated) == 0)
- free_chunk(p);
- return;
- }
- }
- }
- /* Free the memory that was allocated for an AVL tree root node. */
- VG_(free)(bm2);
-}
diff --git a/main/drd/drd_clientobj.c b/main/drd/drd_clientobj.c
index 43198cb..1e9876b 100644
--- a/main/drd/drd_clientobj.c
+++ b/main/drd/drd_clientobj.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_clientobj.h b/main/drd/drd_clientobj.h
index 11e39f6..f177d85 100644
--- a/main/drd/drd_clientobj.h
+++ b/main/drd/drd_clientobj.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_clientreq.c b/main/drd/drd_clientreq.c
index ba0a5a4..49e1f11 100644
--- a/main/drd/drd_clientreq.c
+++ b/main/drd/drd_clientreq.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -70,6 +69,12 @@
* DRD's handler for Valgrind client requests. The code below handles both
* DRD's public and tool-internal client requests.
*/
+#if defined(VGP_mips32_linux)
+ /* There is a cse related issue in gcc for MIPS. Optimization level
+ has to be lowered, so cse related optimizations are not
+ included. */
+ __attribute__((optimize("O1")))
+#endif
static Bool handle_client_request(ThreadId vg_tid, UWord* arg, UWord* ret)
{
UWord result = 0;
@@ -221,7 +226,7 @@
break;
case VG_USERREQ__DRD_START_TRACE_ADDR:
- DRD_(start_tracing_address_range)(arg[1], arg[1] + arg[2]);
+ DRD_(start_tracing_address_range)(arg[1], arg[1] + arg[2], False);
break;
case VG_USERREQ__DRD_STOP_TRACE_ADDR:
diff --git a/main/drd/drd_clientreq.h b/main/drd/drd_clientreq.h
index 3b8d1d5..bdf54b3 100644
--- a/main/drd/drd_clientreq.h
+++ b/main/drd/drd_clientreq.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_cond.c b/main/drd/drd_cond.c
index 023d463..12d39a1 100644
--- a/main/drd/drd_cond.c
+++ b/main/drd/drd_cond.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_cond.h b/main/drd/drd_cond.h
index 4e82411..35f564e 100644
--- a/main/drd/drd_cond.h
+++ b/main/drd/drd_cond.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_darwin_intercepts.c b/main/drd/drd_darwin_intercepts.c
index 0dec939..d1c2651 100644
--- a/main/drd/drd_darwin_intercepts.c
+++ b/main/drd/drd_darwin_intercepts.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -44,7 +43,7 @@
{
void* res;
OrigFn fn;
-
+
VALGRIND_GET_ORIG_FN(fn);
ANNOTATE_IGNORE_READS_AND_WRITES_BEGIN();
diff --git a/main/drd/drd_error.c b/main/drd/drd_error.c
index 1a8c9d3..1447e36 100644
--- a/main/drd/drd_error.c
+++ b/main/drd/drd_error.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_error.h b/main/drd/drd_error.h
index d11b599..e6ed640 100644
--- a/main/drd/drd_error.h
+++ b/main/drd/drd_error.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_hb.c b/main/drd/drd_hb.c
index a05265a..b59b6bb 100644
--- a/main/drd/drd_hb.c
+++ b/main/drd/drd_hb.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -211,14 +210,14 @@
* Combine all vector clocks that were stored because of happens-before
* annotations with the vector clock of the current thread.
*/
- DRD_(vc_copy)(&old_vc, &DRD_(g_threadinfo)[tid].last->vc);
+ DRD_(vc_copy)(&old_vc, DRD_(thread_get_vc)(tid));
VG_(OSetGen_ResetIter)(p->oset);
for ( ; (q = VG_(OSetGen_Next)(p->oset)) != 0; )
{
if (q->tid != tid)
{
tl_assert(q->sg);
- DRD_(vc_combine)(&DRD_(g_threadinfo)[tid].last->vc, &q->sg->vc);
+ DRD_(vc_combine)(DRD_(thread_get_vc)(tid), &q->sg->vc);
}
}
DRD_(thread_update_conflict_set)(tid, &old_vc);
diff --git a/main/drd/drd_hb.h b/main/drd/drd_hb.h
index 7b69082..e0c8b18 100644
--- a/main/drd/drd_hb.h
+++ b/main/drd/drd_hb.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_load_store.c b/main/drd/drd_load_store.c
index 09800c3..9900820 100644
--- a/main/drd/drd_load_store.c
+++ b/main/drd/drd_load_store.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -50,6 +49,8 @@
#define STACK_POINTER_OFFSET OFFSET_arm_R13
#elif defined(VGA_s390x)
#define STACK_POINTER_OFFSET OFFSET_s390x_r15
+#elif defined(VGA_mips32)
+#define STACK_POINTER_OFFSET OFFSET_mips32_r29
#else
#error Unknown architecture.
#endif
@@ -86,19 +87,36 @@
}
void DRD_(trace_mem_access)(const Addr addr, const SizeT size,
- const BmAccessTypeT access_type)
+ const BmAccessTypeT access_type,
+ const HWord stored_value_hi,
+ const HWord stored_value_lo)
{
if (DRD_(is_any_traced)(addr, addr + size))
{
char* vc;
vc = DRD_(vc_aprint)(DRD_(thread_get_vc)(DRD_(thread_get_running_tid)()));
- DRD_(trace_msg_w_bt)("%s 0x%lx size %ld (thread %d / vc %s)",
- access_type == eLoad ? "load "
- : access_type == eStore ? "store"
- : access_type == eStart ? "start"
- : access_type == eEnd ? "end " : "????",
- addr, size, DRD_(thread_get_running_tid)(), vc);
+ if (access_type == eStore && size <= sizeof(HWord)) {
+ DRD_(trace_msg_w_bt)("store 0x%lx size %ld val %ld/0x%lx (thread %d /"
+ " vc %s)", addr, size, stored_value_lo,
+ stored_value_lo, DRD_(thread_get_running_tid)(),
+ vc);
+ } else if (access_type == eStore && size > sizeof(HWord)) {
+ ULong sv;
+
+ tl_assert(sizeof(HWord) == 4);
+ sv = ((ULong)stored_value_hi << 32) | stored_value_lo;
+ DRD_(trace_msg_w_bt)("store 0x%lx size %ld val %lld/0x%llx (thread %d"
+ " / vc %s)", addr, size, sv, sv,
+ DRD_(thread_get_running_tid)(), vc);
+ } else {
+ DRD_(trace_msg_w_bt)("%s 0x%lx size %ld (thread %d / vc %s)",
+ access_type == eLoad ? "load "
+ : access_type == eStore ? "store"
+ : access_type == eStart ? "start"
+ : access_type == eEnd ? "end " : "????",
+ addr, size, DRD_(thread_get_running_tid)(), vc);
+ }
VG_(free)(vc);
tl_assert(DRD_(DrdThreadIdToVgThreadId)(DRD_(thread_get_running_tid)())
== VG_(get_running_tid)());
@@ -107,32 +125,47 @@
static VG_REGPARM(2) void drd_trace_mem_load(const Addr addr, const SizeT size)
{
- return DRD_(trace_mem_access)(addr, size, eLoad);
+ return DRD_(trace_mem_access)(addr, size, eLoad, 0, 0);
}
-static VG_REGPARM(2) void drd_trace_mem_store(const Addr addr,const SizeT size)
+static VG_REGPARM(3) void drd_trace_mem_store(const Addr addr,const SizeT size,
+ const HWord stored_value_hi,
+ const HWord stored_value_lo)
{
- return DRD_(trace_mem_access)(addr, size, eStore);
+ return DRD_(trace_mem_access)(addr, size, eStore, stored_value_hi,
+ stored_value_lo);
}
static void drd_report_race(const Addr addr, const SizeT size,
const BmAccessTypeT access_type)
{
- DataRaceErrInfo drei;
+ ThreadId vg_tid;
- drei.tid = DRD_(thread_get_running_tid)();
- drei.addr = addr;
- drei.size = size;
- drei.access_type = access_type;
- VG_(maybe_record_error)(VG_(get_running_tid)(),
- DataRaceErr,
- VG_(get_IP)(VG_(get_running_tid)()),
- "Conflicting access",
- &drei);
+ vg_tid = VG_(get_running_tid)();
+ if (!DRD_(get_check_stack_accesses)()
+ && DRD_(thread_address_on_any_stack)(addr)) {
+#if 0
+ GenericErrInfo GEI = {
+ .tid = DRD_(thread_get_running_tid)(),
+ .addr = addr,
+ };
+ VG_(maybe_record_error)(vg_tid, GenericErr, VG_(get_IP)(vg_tid),
+ "--check-stack-var=no skips checking stack"
+ " variables shared over threads",
+ &GEI);
+#endif
+ } else {
+ DataRaceErrInfo drei = {
+ .tid = DRD_(thread_get_running_tid)(),
+ .addr = addr,
+ .size = size,
+ .access_type = access_type,
+ };
+ VG_(maybe_record_error)(vg_tid, DataRaceErr, VG_(get_IP)(vg_tid),
+ "Conflicting access", &drei);
- if (s_first_race_only)
- {
- DRD_(start_suppression)(addr, addr + size, "first race only");
+ if (s_first_race_only)
+ DRD_(start_suppression)(addr, addr + size, "first race only");
}
}
@@ -248,9 +281,9 @@
{
if (DRD_(running_thread_is_recording_stores)()
&& (s_check_stack_accesses
- || ! DRD_(thread_address_on_stack)(addr))
+ || !DRD_(thread_address_on_stack)(addr))
&& bm_access_store_4_triggers_conflict(addr)
- && ! DRD_(is_suppressed)(addr, addr + 4))
+ && !DRD_(is_suppressed)(addr, addr + 4))
{
drd_report_race(addr, 4, eStore);
}
@@ -300,27 +333,144 @@
return result;
}
-static void instrument_load(IRSB* const bb,
- IRExpr* const addr_expr,
+static const IROp u_widen_irop[5][9] = {
+ [Ity_I1 - Ity_I1] = { [4] = Iop_1Uto32, [8] = Iop_1Uto64 },
+ [Ity_I8 - Ity_I1] = { [4] = Iop_8Uto32, [8] = Iop_8Uto64 },
+ [Ity_I16 - Ity_I1] = { [4] = Iop_16Uto32, [8] = Iop_16Uto64 },
+ [Ity_I32 - Ity_I1] = { [8] = Iop_32Uto64 },
+};
+
+/**
+ * Instrument the client code to trace a memory load (--trace-addr).
+ */
+static IRExpr* instr_trace_mem_load(IRSB* const bb, IRExpr* addr_expr,
+ const HWord size)
+{
+ IRTemp tmp;
+
+ tmp = newIRTemp(bb->tyenv, typeOfIRExpr(bb->tyenv, addr_expr));
+ addStmtToIRSB(bb, IRStmt_WrTmp(tmp, addr_expr));
+ addr_expr = IRExpr_RdTmp(tmp);
+
+ addStmtToIRSB(bb,
+ IRStmt_Dirty(
+ unsafeIRDirty_0_N(/*regparms*/2,
+ "drd_trace_mem_load",
+ VG_(fnptr_to_fnentry)
+ (drd_trace_mem_load),
+ mkIRExprVec_2(addr_expr, mkIRExpr_HWord(size)))));
+
+ return addr_expr;
+}
+
+/**
+ * Instrument the client code to trace a memory store (--trace-addr).
+ */
+static void instr_trace_mem_store(IRSB* const bb, IRExpr* const addr_expr,
+ IRExpr* data_expr_hi, IRExpr* data_expr_lo)
+{
+ IRType ty_data_expr;
+ HWord size;
+
+ tl_assert(sizeof(HWord) == 4 || sizeof(HWord) == 8);
+ tl_assert(!data_expr_hi || typeOfIRExpr(bb->tyenv, data_expr_hi) == Ity_I32);
+
+ ty_data_expr = typeOfIRExpr(bb->tyenv, data_expr_lo);
+ size = sizeofIRType(ty_data_expr);
+
+#if 0
+ // Test code
+ if (ty_data_expr == Ity_I32) {
+ IRTemp tmp = newIRTemp(bb->tyenv, Ity_F32);
+ data_expr_lo = IRExpr_Unop(Iop_ReinterpI32asF32, data_expr_lo);
+ addStmtToIRSB(bb, IRStmt_WrTmp(tmp, data_expr_lo));
+ data_expr_lo = IRExpr_RdTmp(tmp);
+ ty_data_expr = Ity_F32;
+ } else if (ty_data_expr == Ity_I64) {
+ IRTemp tmp = newIRTemp(bb->tyenv, Ity_F64);
+ data_expr_lo = IRExpr_Unop(Iop_ReinterpI64asF64, data_expr_lo);
+ addStmtToIRSB(bb, IRStmt_WrTmp(tmp, data_expr_lo));
+ data_expr_lo = IRExpr_RdTmp(tmp);
+ ty_data_expr = Ity_F64;
+ }
+#endif
+
+ if (ty_data_expr == Ity_F32) {
+ IRTemp tmp = newIRTemp(bb->tyenv, Ity_I32);
+ addStmtToIRSB(bb, IRStmt_WrTmp(tmp, IRExpr_Unop(Iop_ReinterpF32asI32,
+ data_expr_lo)));
+ data_expr_lo = IRExpr_RdTmp(tmp);
+ ty_data_expr = Ity_I32;
+ } else if (ty_data_expr == Ity_F64) {
+ IRTemp tmp = newIRTemp(bb->tyenv, Ity_I64);
+ addStmtToIRSB(bb, IRStmt_WrTmp(tmp, IRExpr_Unop(Iop_ReinterpF64asI64,
+ data_expr_lo)));
+ data_expr_lo = IRExpr_RdTmp(tmp);
+ ty_data_expr = Ity_I64;
+ }
+
+ if (size == sizeof(HWord)
+ && (ty_data_expr == Ity_I32 || ty_data_expr == Ity_I64))
+ {
+ /* No conversion necessary */
+ } else {
+ IROp widen_op;
+
+ if (Ity_I1 <= ty_data_expr
+ && ty_data_expr
+ < Ity_I1 + sizeof(u_widen_irop)/sizeof(u_widen_irop[0]))
+ {
+ widen_op = u_widen_irop[ty_data_expr - Ity_I1][sizeof(HWord)];
+ if (!widen_op)
+ widen_op = Iop_INVALID;
+ } else {
+ widen_op = Iop_INVALID;
+ }
+ if (widen_op != Iop_INVALID) {
+ IRTemp tmp;
+
+ /* Widen the integer expression to a HWord */
+ tmp = newIRTemp(bb->tyenv, sizeof(HWord) == 4 ? Ity_I32 : Ity_I64);
+ addStmtToIRSB(bb,
+ IRStmt_WrTmp(tmp, IRExpr_Unop(widen_op, data_expr_lo)));
+ data_expr_lo = IRExpr_RdTmp(tmp);
+ } else if (size > sizeof(HWord) && !data_expr_hi
+ && ty_data_expr == Ity_I64) {
+ IRTemp tmp;
+
+ tl_assert(sizeof(HWord) == 4);
+ tl_assert(size == 8);
+ tmp = newIRTemp(bb->tyenv, Ity_I32);
+ addStmtToIRSB(bb,
+ IRStmt_WrTmp(tmp,
+ IRExpr_Unop(Iop_64HIto32, data_expr_lo)));
+ data_expr_hi = IRExpr_RdTmp(tmp);
+ tmp = newIRTemp(bb->tyenv, Ity_I32);
+ addStmtToIRSB(bb, IRStmt_WrTmp(tmp,
+ IRExpr_Unop(Iop_64to32, data_expr_lo)));
+ data_expr_lo = IRExpr_RdTmp(tmp);
+ } else {
+ data_expr_lo = mkIRExpr_HWord(0);
+ }
+ }
+ addStmtToIRSB(bb,
+ IRStmt_Dirty(
+ unsafeIRDirty_0_N(/*regparms*/3,
+ "drd_trace_mem_store",
+ VG_(fnptr_to_fnentry)(drd_trace_mem_store),
+ mkIRExprVec_4(addr_expr, mkIRExpr_HWord(size),
+ data_expr_hi ? data_expr_hi
+ : mkIRExpr_HWord(0), data_expr_lo))));
+}
+
+static void instrument_load(IRSB* const bb, IRExpr* const addr_expr,
const HWord size)
{
IRExpr* size_expr;
IRExpr** argv;
IRDirty* di;
- if (UNLIKELY(DRD_(any_address_is_traced)()))
- {
- addStmtToIRSB(bb,
- IRStmt_Dirty(
- unsafeIRDirty_0_N(/*regparms*/2,
- "drd_trace_load",
- VG_(fnptr_to_fnentry)
- (drd_trace_mem_load),
- mkIRExprVec_2(addr_expr,
- mkIRExpr_HWord(size)))));
- }
-
- if (! s_check_stack_accesses && is_stack_access(bb, addr_expr))
+ if (!s_check_stack_accesses && is_stack_access(bb, addr_expr))
return;
switch (size)
@@ -365,27 +515,24 @@
addStmtToIRSB(bb, IRStmt_Dirty(di));
}
-static void instrument_store(IRSB* const bb,
- IRExpr* const addr_expr,
- const HWord size)
+static void instrument_store(IRSB* const bb, IRExpr* addr_expr,
+ IRExpr* const data_expr)
{
IRExpr* size_expr;
IRExpr** argv;
IRDirty* di;
+ HWord size;
- if (UNLIKELY(DRD_(any_address_is_traced)()))
- {
- addStmtToIRSB(bb,
- IRStmt_Dirty(
- unsafeIRDirty_0_N(/*regparms*/2,
- "drd_trace_store",
- VG_(fnptr_to_fnentry)
- (drd_trace_mem_store),
- mkIRExprVec_2(addr_expr,
- mkIRExpr_HWord(size)))));
+ size = sizeofIRType(typeOfIRExpr(bb->tyenv, data_expr));
+
+ if (UNLIKELY(DRD_(any_address_is_traced)())) {
+ IRTemp tmp = newIRTemp(bb->tyenv, typeOfIRExpr(bb->tyenv, addr_expr));
+ addStmtToIRSB(bb, IRStmt_WrTmp(tmp, addr_expr));
+ addr_expr = IRExpr_RdTmp(tmp);
+ instr_trace_mem_store(bb, addr_expr, NULL, data_expr);
}
- if (! s_check_stack_accesses && is_stack_access(bb, addr_expr))
+ if (!s_check_stack_accesses && is_stack_access(bb, addr_expr))
return;
switch (size)
@@ -448,6 +595,7 @@
bb->tyenv = deepCopyIRTypeEnv(bb_in->tyenv);
bb->next = deepCopyIRExpr(bb_in->next);
bb->jumpkind = bb_in->jumpkind;
+ bb->offsIP = bb_in->offsIP;
for (i = 0; i < bb_in->stmts_used; i++)
{
@@ -482,23 +630,20 @@
case Ist_Store:
if (instrument)
- {
- instrument_store(bb,
- st->Ist.Store.addr,
- sizeofIRType(typeOfIRExpr(bb->tyenv,
- st->Ist.Store.data)));
- }
+ instrument_store(bb, st->Ist.Store.addr, st->Ist.Store.data);
addStmtToIRSB(bb, st);
break;
case Ist_WrTmp:
- if (instrument)
- {
+ if (instrument) {
const IRExpr* const data = st->Ist.WrTmp.data;
- if (data->tag == Iex_Load)
- {
- instrument_load(bb,
- data->Iex.Load.addr,
+ IRExpr* addr_expr = data->Iex.Load.addr;
+ if (data->tag == Iex_Load) {
+ if (UNLIKELY(DRD_(any_address_is_traced)())) {
+ addr_expr = instr_trace_mem_load(bb, addr_expr,
+ sizeofIRType(data->Iex.Load.ty));
+ }
+ instrument_load(bb, data->Iex.Load.addr,
sizeofIRType(data->Iex.Load.ty));
}
}
@@ -506,8 +651,7 @@
break;
case Ist_Dirty:
- if (instrument)
- {
+ if (instrument) {
IRDirty* d = st->Ist.Dirty.details;
IREffect const mFx = d->mFx;
switch (mFx) {
@@ -545,8 +689,7 @@
break;
case Ist_CAS:
- if (instrument)
- {
+ if (instrument) {
/*
* Treat compare-and-swap as a read. By handling atomic
* instructions as read instructions no data races are reported
@@ -557,34 +700,43 @@
*/
Int dataSize;
IRCAS* cas = st->Ist.CAS.details;
+
tl_assert(cas->addr != NULL);
tl_assert(cas->dataLo != NULL);
dataSize = sizeofIRType(typeOfIRExpr(bb->tyenv, cas->dataLo));
if (cas->dataHi != NULL)
dataSize *= 2; /* since it's a doubleword-CAS */
+
+ if (UNLIKELY(DRD_(any_address_is_traced)()))
+ instr_trace_mem_store(bb, cas->addr, cas->dataHi, cas->dataLo);
+
instrument_load(bb, cas->addr, dataSize);
}
addStmtToIRSB(bb, st);
break;
case Ist_LLSC: {
- /* Ignore store-conditionals, and handle load-linked's
- exactly like normal loads. */
+ /*
+ * Ignore store-conditionals (except for tracing), and handle
+ * load-linked's exactly like normal loads.
+ */
IRType dataTy;
- if (st->Ist.LLSC.storedata == NULL)
- {
+
+ if (st->Ist.LLSC.storedata == NULL) {
/* LL */
dataTy = typeOfIRTemp(bb_in->tyenv, st->Ist.LLSC.result);
if (instrument) {
- instrument_load(bb,
- st->Ist.LLSC.addr,
- sizeofIRType(dataTy));
+ IRExpr* addr_expr = st->Ist.LLSC.addr;
+ if (UNLIKELY(DRD_(any_address_is_traced)()))
+ addr_expr = instr_trace_mem_load(bb, addr_expr,
+ sizeofIRType(dataTy));
+
+ instrument_load(bb, addr_expr, sizeofIRType(dataTy));
}
- }
- else
- {
+ } else {
/* SC */
- /*ignore */
+ instr_trace_mem_store(bb, st->Ist.LLSC.addr, NULL,
+ st->Ist.LLSC.storedata);
}
addStmtToIRSB(bb, st);
break;
diff --git a/main/drd/drd_load_store.h b/main/drd/drd_load_store.h
index c67e285..1d8d008 100644
--- a/main/drd/drd_load_store.h
+++ b/main/drd/drd_load_store.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -47,7 +46,9 @@
IRType const gWordTy,
IRType const hWordTy);
void DRD_(trace_mem_access)(const Addr addr, const SizeT size,
- const BmAccessTypeT access_type);
+ const BmAccessTypeT access_type,
+ const HWord stored_value_hi,
+ const HWord stored_value_lo);
VG_REGPARM(2) void DRD_(trace_load)(Addr addr, SizeT size);
VG_REGPARM(2) void DRD_(trace_store)(Addr addr, SizeT size);
void DRD_(clean_memory)(const Addr a1, const SizeT len);
diff --git a/main/drd/drd_main.c b/main/drd/drd_main.c
index d18a26c..5e86f81 100644
--- a/main/drd/drd_main.c
+++ b/main/drd/drd_main.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -91,6 +90,7 @@
int trace_semaphore = -1;
int trace_suppression = -1;
Char* trace_address = 0;
+ Char* ptrace_address = 0;
if VG_BOOL_CLO(arg, "--check-stack-var", check_stack_accesses) {}
else if VG_INT_CLO (arg, "--join-list-vol", join_list_vol) {}
@@ -120,6 +120,7 @@
else if VG_BOOL_CLO(arg, "--trace-suppr", trace_suppression) {}
else if VG_BOOL_CLO(arg, "--var-info", s_var_info) {}
else if VG_INT_CLO (arg, "--exclusive-threshold", exclusive_threshold_ms) {}
+ else if VG_STR_CLO (arg, "--ptrace-addr", ptrace_address) {}
else if VG_INT_CLO (arg, "--shared-threshold", shared_threshold_ms) {}
else if VG_STR_CLO (arg, "--trace-addr", trace_address) {}
else
@@ -152,10 +153,13 @@
DRD_(thread_set_segment_merge_interval)(segment_merge_interval);
if (show_confl_seg != -1)
DRD_(set_show_conflicting_segments)(show_confl_seg);
- if (trace_address)
- {
+ if (trace_address) {
const Addr addr = VG_(strtoll16)(trace_address, 0);
- DRD_(start_tracing_address_range)(addr, addr + 1);
+ DRD_(start_tracing_address_range)(addr, addr + 1, False);
+ }
+ if (ptrace_address) {
+ const Addr addr = VG_(strtoll16)(ptrace_address, 0);
+ DRD_(start_tracing_address_range)(addr, addr + 1, True);
}
if (trace_barrier != -1)
DRD_(barrier_set_trace)(trace_barrier);
@@ -218,7 +222,11 @@
" --show-stack-usage=yes|no Print stack usage at thread exit time [no].\n"
"\n"
" drd options for monitoring process behavior:\n"
-" --trace-addr=<address> Trace all load and store activity for the.\n"
+" --ptrace-addr=<address> Trace all load and store activity for the\n"
+" specified address and keep doing that even after\n"
+" the memory at that address has been freed and\n"
+" reallocated [off].\n"
+" --trace-addr=<address> Trace all load and store activity for the\n"
" specified address [off].\n"
" --trace-alloc=yes|no Trace all memory allocations and deallocations\n"" [no].\n"
" --trace-barrier=yes|no Trace all barrier activity [no].\n"
@@ -317,12 +325,25 @@
a1, len, DRD_(running_thread_inside_pthread_create)()
? " (inside pthread_create())" : "");
+#if 0
if (!is_stack_mem && DRD_(g_free_is_write))
DRD_(thread_stop_using_mem)(a1, a2);
+#else
+ /*
+ * Sometimes it happens that a client starts using a memory range that has
+ * been accessed before but for which drd_stop_using_mem() has not been
+ * called for the entire range. It is not yet clear whether this is an
+ * out-of-range access by the client, an issue in the Valgrind core or an
+ * issue in DRD. Avoid that this issue triggers false positive reports by
+ * always clearing accesses for newly allocated memory ranges. See also
+ * http://bugs.kde.org/show_bug.cgi?id=297147.
+ */
+ DRD_(thread_stop_using_mem)(a1, a2);
+#endif
if (UNLIKELY(DRD_(any_address_is_traced)()))
{
- DRD_(trace_mem_access)(a1, len, eStart);
+ DRD_(trace_mem_access)(a1, len, eStart, 0, 0);
}
if (UNLIKELY(DRD_(running_thread_inside_pthread_create)()))
@@ -354,7 +375,7 @@
tl_assert(a1 <= a2);
if (UNLIKELY(DRD_(any_address_is_traced)()))
- DRD_(trace_mem_access)(a1, len, eEnd);
+ DRD_(trace_mem_access)(a1, len, eEnd, 0, 0);
if (!is_stack_mem && s_trace_alloc)
DRD_(trace_msg)("Stopped using memory range 0x%lx + %ld",
@@ -388,6 +409,8 @@
drd_start_using_mem(a1, len, is_stack_memory);
}
+static const Bool trace_sectsuppr = False;
+
/**
* Suppress data race reports on all addresses contained in .plt and
* .got.plt sections inside the address range [ a, a + len [. The data in
@@ -402,23 +425,23 @@
{
const DebugInfo* di;
-#if 0
- VG_(printf)("Evaluating range @ 0x%lx size %ld\n", a, len);
-#endif
+ if (trace_sectsuppr)
+ VG_(dmsg)("Evaluating range @ 0x%lx size %ld\n", a, len);
- for (di = VG_(next_DebugInfo)(0); di; di = VG_(next_DebugInfo)(di))
- {
+ for (di = VG_(next_DebugInfo)(0); di; di = VG_(next_DebugInfo)(di)) {
Addr avma;
SizeT size;
+ if (trace_sectsuppr)
+ VG_(dmsg)("Examining %s / %s\n", VG_(DebugInfo_get_filename)(di),
+ VG_(DebugInfo_get_soname)(di));
+
avma = VG_(DebugInfo_get_plt_avma)(di);
size = VG_(DebugInfo_get_plt_size)(di);
tl_assert((avma && size) || (avma == 0 && size == 0));
- if (size > 0)
- {
-#if 0
- VG_(printf)("Suppressing .plt @ 0x%lx size %ld\n", avma, size);
-#endif
+ if (size > 0) {
+ if (trace_sectsuppr)
+ VG_(dmsg)("Suppressing .plt @ 0x%lx size %ld\n", avma, size);
tl_assert(VG_(DebugInfo_sect_kind)(NULL, 0, avma) == Vg_SectPLT);
DRD_(start_suppression)(avma, avma + size, ".plt");
}
@@ -426,11 +449,9 @@
avma = VG_(DebugInfo_get_gotplt_avma)(di);
size = VG_(DebugInfo_get_gotplt_size)(di);
tl_assert((avma && size) || (avma == 0 && size == 0));
- if (size > 0)
- {
-#if 0
- VG_(printf)("Suppressing .got.plt @ 0x%lx size %ld\n", avma, size);
-#endif
+ if (size > 0) {
+ if (trace_sectsuppr)
+ VG_(dmsg)("Suppressing .got.plt @ 0x%lx size %ld\n", avma, size);
tl_assert(VG_(DebugInfo_sect_kind)(NULL, 0, avma) == Vg_SectGOTPLT);
DRD_(start_suppression)(avma, avma + size, ".gotplt");
}
@@ -449,29 +470,44 @@
DRD_(suppress_relocation_conflicts)(a, len);
}
-/* Called by the core when the stack of a thread grows, to indicate that */
-/* the addresses in range [ a, a + len [ may now be used by the client. */
-/* Assumption: stacks grow downward. */
+/**
+ * Called by the core when the stack of a thread grows, to indicate that
+ * the addresses in range [ a, a + len [ may now be used by the client.
+ * Assumption: stacks grow downward.
+ */
static __inline__
-void drd_start_using_mem_stack(const Addr a, const SizeT len)
+void drd_start_using_mem_stack2(const DrdThreadId tid, const Addr a,
+ const SizeT len)
{
- DRD_(thread_set_stack_min)(DRD_(thread_get_running_tid)(),
- a - VG_STACK_REDZONE_SZB);
- drd_start_using_mem(a - VG_STACK_REDZONE_SZB,
- len + VG_STACK_REDZONE_SZB,
+ DRD_(thread_set_stack_min)(tid, a - VG_STACK_REDZONE_SZB);
+ drd_start_using_mem(a - VG_STACK_REDZONE_SZB, len + VG_STACK_REDZONE_SZB,
True);
}
-/* Called by the core when the stack of a thread shrinks, to indicate that */
-/* the addresses [ a, a + len [ are no longer accessible for the client. */
-/* Assumption: stacks grow downward. */
+static __inline__
+void drd_start_using_mem_stack(const Addr a, const SizeT len)
+{
+ drd_start_using_mem_stack2(DRD_(thread_get_running_tid)(), a, len);
+}
+
+/**
+ * Called by the core when the stack of a thread shrinks, to indicate that
+ * the addresses [ a, a + len [ are no longer accessible for the client.
+ * Assumption: stacks grow downward.
+ */
+static __inline__
+void drd_stop_using_mem_stack2(const DrdThreadId tid, const Addr a,
+ const SizeT len)
+{
+ DRD_(thread_set_stack_min)(tid, a + len - VG_STACK_REDZONE_SZB);
+ drd_stop_using_mem(a - VG_STACK_REDZONE_SZB, len + VG_STACK_REDZONE_SZB,
+ True);
+}
+
static __inline__
void drd_stop_using_mem_stack(const Addr a, const SizeT len)
{
- DRD_(thread_set_stack_min)(DRD_(thread_get_running_tid)(),
- a + len - VG_STACK_REDZONE_SZB);
- drd_stop_using_mem(a - VG_STACK_REDZONE_SZB, len + VG_STACK_REDZONE_SZB,
- True);
+ drd_stop_using_mem_stack2(DRD_(thread_get_running_tid)(), a, len);
}
static
@@ -580,17 +616,24 @@
}
}
-/* Called by Valgrind's core before any loads or stores are performed on */
-/* the context of thread "created". At startup, this function is called */
-/* with arguments (0,1). */
+/**
+ * Called by Valgrind's core before any loads or stores are performed on
+ * the context of thread "created".
+ */
static
void drd_post_thread_create(const ThreadId vg_created)
{
DrdThreadId drd_created;
+ Addr stack_max;
tl_assert(vg_created != VG_INVALID_THREADID);
drd_created = DRD_(thread_post_create)(vg_created);
+
+ /* Set up red zone before the code in glibc's clone.S is run. */
+ stack_max = DRD_(thread_get_stack_max)(drd_created);
+ drd_start_using_mem_stack2(drd_created, stack_max, 0);
+
if (DRD_(thread_get_trace_fork_join)())
{
DRD_(trace_msg)("drd_post_thread_create created = %d", drd_created);
@@ -609,9 +652,15 @@
{
DrdThreadId drd_tid;
- tl_assert(VG_(get_running_tid)() == vg_tid);
+ /*
+ * Ignore if invoked because thread creation failed. See e.g.
+ * coregrind/m_syswrap/syswrap-amd64-linux.c
+ */
+ if (VG_(get_running_tid)() != vg_tid)
+ return;
drd_tid = DRD_(VgThreadIdToDrdThreadId)(vg_tid);
+ tl_assert(drd_tid != DRD_INVALID_THREADID);
if (DRD_(thread_get_trace_fork_join)())
{
DRD_(trace_msg)("drd_thread_finished tid = %d%s", drd_tid,
@@ -737,6 +786,8 @@
DRD_(get_mutex_lock_count)());
DRD_(print_malloc_stats)();
}
+
+ DRD_(bm_module_cleanup)();
}
static
@@ -746,7 +797,7 @@
VG_(details_name) ("drd");
VG_(details_version) (NULL);
VG_(details_description) ("a thread error detector");
- VG_(details_copyright_author)("Copyright (C) 2006-2011, and GNU GPL'd,"
+ VG_(details_copyright_author)("Copyright (C) 2006-2012, and GNU GPL'd,"
" by Bart Van Assche.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
@@ -789,12 +840,16 @@
DRD_(register_malloc_wrappers)(drd_start_using_mem_w_ecu,
drd_stop_using_nonstack_mem);
+ DRD_(bm_module_init)();
+
DRD_(clientreq_init)();
DRD_(suppression_init)();
DRD_(clientobj_init)();
+ DRD_(thread_init)();
+
{
Char* const smi = VG_(getenv)("DRD_SEGMENT_MERGING_INTERVAL");
if (smi)
diff --git a/main/drd/drd_malloc_wrappers.c b/main/drd/drd_malloc_wrappers.c
index 026b3b8..95f0627 100644
--- a/main/drd/drd_malloc_wrappers.c
+++ b/main/drd/drd_malloc_wrappers.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -132,10 +131,10 @@
if (mc)
{
tl_assert(p == mc->data);
- if (dealloc)
- VG_(cli_free)((void*)p);
if (mc->size > 0)
s_stop_using_mem_callback(mc->data, mc->size);
+ if (dealloc)
+ VG_(cli_free)((void*)p);
VG_(HT_remove)(s_malloc_list, (UWord)p);
VG_(free)(mc);
return True;
@@ -229,9 +228,9 @@
VG_(memcpy)(p_new, p_old, mc->size);
/* Free old memory. */
- VG_(cli_free)(p_old);
if (mc->size > 0)
s_stop_using_mem_callback(mc->data, mc->size);
+ VG_(cli_free)(p_old);
VG_(HT_remove)(s_malloc_list, (UWord)p_old);
/* Update state information. */
diff --git a/main/drd/drd_malloc_wrappers.h b/main/drd/drd_malloc_wrappers.h
index e10fb27..aaff883 100644
--- a/main/drd/drd_malloc_wrappers.h
+++ b/main/drd/drd_malloc_wrappers.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_mutex.c b/main/drd/drd_mutex.c
index c9392ee..a3347e9 100644
--- a/main/drd/drd_mutex.c
+++ b/main/drd/drd_mutex.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_mutex.h b/main/drd/drd_mutex.h
index d2c05d3..41bd87f 100644
--- a/main/drd/drd_mutex.h
+++ b/main/drd/drd_mutex.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_pthread_intercepts.c b/main/drd/drd_pthread_intercepts.c
index f34540f..bf3f134 100644
--- a/main/drd/drd_pthread_intercepts.c
+++ b/main/drd/drd_pthread_intercepts.c
@@ -1,5 +1,3 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
-
/*--------------------------------------------------------------------*/
/*--- Client-space code for DRD. drd_pthread_intercepts.c ---*/
/*--------------------------------------------------------------------*/
@@ -7,7 +5,7 @@
/*
This file is part of DRD, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -138,7 +136,9 @@
/* Local data structures. */
typedef struct {
- volatile int counter;
+ pthread_mutex_t mutex;
+ int counter;
+ int waiters;
} DrdSema;
typedef struct
@@ -146,7 +146,7 @@
void* (*start)(void*);
void* arg;
int detachstate;
- DrdSema wrapper_started;
+ DrdSema* wrapper_started;
} DrdPosixThreadArgs;
@@ -182,44 +182,58 @@
static void DRD_(sema_init)(DrdSema* sema)
{
DRD_IGNORE_VAR(sema->counter);
+ pthread_mutex_init(&sema->mutex, NULL);
sema->counter = 0;
+ sema->waiters = 0;
}
static void DRD_(sema_destroy)(DrdSema* sema)
{
+ pthread_mutex_destroy(&sema->mutex);
}
static void DRD_(sema_down)(DrdSema* sema)
{
int res = ENOSYS;
- while (sema->counter == 0) {
+ pthread_mutex_lock(&sema->mutex);
+ if (sema->counter == 0) {
+ sema->waiters++;
+ while (sema->counter == 0) {
+ pthread_mutex_unlock(&sema->mutex);
#ifdef HAVE_USABLE_LINUX_FUTEX_H
- if (syscall(__NR_futex, (UWord)&sema->counter,
- FUTEX_WAIT | FUTEX_PRIVATE_FLAG, 0) == 0)
- res = 0;
- else
- res = errno;
+ if (syscall(__NR_futex, (UWord)&sema->counter,
+ FUTEX_WAIT | FUTEX_PRIVATE_FLAG, 0) == 0)
+ res = 0;
+ else
+ res = errno;
#endif
- /*
- * Invoke sched_yield() on non-Linux systems, if the futex syscall has
- * not been invoked or if this code has been built on a Linux system
- * where __NR_futex is defined and is run on a Linux system that does
- * not support the futex syscall.
- */
- if (res != 0 && res != EWOULDBLOCK)
- sched_yield();
+ /*
+ * Invoke sched_yield() on non-Linux systems, if the futex syscall has
+ * not been invoked or if this code has been built on a Linux system
+ * where __NR_futex is defined and is run on a Linux system that does
+ * not support the futex syscall.
+ */
+ if (res != 0 && res != EWOULDBLOCK)
+ sched_yield();
+ pthread_mutex_lock(&sema->mutex);
+ }
+ sema->waiters--;
}
sema->counter--;
+ pthread_mutex_unlock(&sema->mutex);
}
static void DRD_(sema_up)(DrdSema* sema)
{
+ pthread_mutex_lock(&sema->mutex);
sema->counter++;
#ifdef HAVE_USABLE_LINUX_FUTEX_H
- syscall(__NR_futex, (UWord)&sema->counter,
- FUTEX_WAKE | FUTEX_PRIVATE_FLAG, 1);
+ if (sema->waiters > 0)
+ syscall(__NR_futex, (UWord)&sema->counter,
+ FUTEX_WAKE | FUTEX_PRIVATE_FLAG, 1);
#endif
+ pthread_mutex_unlock(&sema->mutex);
}
/**
@@ -336,7 +350,7 @@
* DRD_(set_joinable)() have been invoked to avoid a race with
* a pthread_detach() invocation for this thread from another thread.
*/
- DRD_(sema_up)(&arg_ptr->wrapper_started);
+ DRD_(sema_up)(arg_copy.wrapper_started);
return (arg_copy.start)(arg_copy.arg);
}
@@ -432,13 +446,15 @@
{
int ret;
OrigFn fn;
+ DrdSema wrapper_started;
DrdPosixThreadArgs thread_args;
VALGRIND_GET_ORIG_FN(fn);
+ DRD_(sema_init)(&wrapper_started);
thread_args.start = start;
thread_args.arg = arg;
- DRD_(sema_init)(&thread_args.wrapper_started);
+ thread_args.wrapper_started = &wrapper_started;
/*
* Find out whether the thread will be started as a joinable thread
* or as a detached thread. If no thread attributes have been specified,
@@ -457,13 +473,12 @@
CALL_FN_W_WWWW(ret, fn, thread, attr, DRD_(thread_wrapper), &thread_args);
DRD_(left_pthread_create)();
- if (ret == 0)
- {
+ if (ret == 0) {
/* Wait until the thread wrapper started. */
- DRD_(sema_down)(&thread_args.wrapper_started);
+ DRD_(sema_down)(&wrapper_started);
}
- DRD_(sema_destroy)(&thread_args.wrapper_started);
+ DRD_(sema_destroy)(&wrapper_started);
VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DRD_START_NEW_SEGMENT,
pthread_self(), 0, 0, 0, 0);
@@ -518,6 +533,28 @@
PTH_FUNCS(int, pthreadZudetach, pthread_detach_intercept,
(pthread_t thread), (thread));
+// Don't intercept pthread_cancel() because pthread_cancel_init() loads
+// libgcc.so. That library is loaded by calling _dl_open(). The function
+// dl_open_worker() looks up from which object the caller is calling in
+// GL(dn_ns)[]. Since the DRD intercepts are linked into vgpreload_drd-*.so
+// and since that object file is not loaded through glibc, glibc does not
+// have any information about that object. That results in the following
+// segmentation fault on at least Fedora 17 x86_64:
+// Process terminating with default action of signal 11 (SIGSEGV)
+// General Protection Fault
+// at 0x4006B75: _dl_map_object_from_fd (dl-load.c:1580)
+// by 0x4008312: _dl_map_object (dl-load.c:2355)
+// by 0x4012FFB: dl_open_worker (dl-open.c:226)
+// by 0x400ECB5: _dl_catch_error (dl-error.c:178)
+// by 0x4012B2B: _dl_open (dl-open.c:652)
+// by 0x5184511: do_dlopen (dl-libc.c:89)
+// by 0x400ECB5: _dl_catch_error (dl-error.c:178)
+// by 0x51845D1: __libc_dlopen_mode (dl-libc.c:48)
+// by 0x4E4A703: pthread_cancel_init (unwind-forcedunwind.c:53)
+// by 0x4E476F2: pthread_cancel (pthread_cancel.c:40)
+// by 0x4C2C050: pthread_cancel (drd_pthread_intercepts.c:547)
+// by 0x400B3A: main (bar_bad.c:83)
+#if 0
// NOTE: be careful to intercept only pthread_cancel() and not
// pthread_cancel_init() on Linux.
@@ -537,6 +574,7 @@
PTH_FUNCS(int, pthreadZucancel, pthread_cancel_intercept,
(pthread_t thread), (thread))
+#endif
static __always_inline
int pthread_once_intercept(pthread_once_t *once_control,
diff --git a/main/drd/drd_qtcore_intercepts.c b/main/drd/drd_qtcore_intercepts.c
index bd55fa4..2dd7ced 100644
--- a/main/drd/drd_qtcore_intercepts.c
+++ b/main/drd/drd_qtcore_intercepts.c
@@ -1,5 +1,3 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
-
/*--------------------------------------------------------------------*/
/*--- Client-space code for drd. drd_qtcore_intercepts.c ---*/
/*--------------------------------------------------------------------*/
@@ -7,7 +5,7 @@
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_rwlock.c b/main/drd/drd_rwlock.c
index 8e13c66..e06c277 100644
--- a/main/drd/drd_rwlock.c
+++ b/main/drd/drd_rwlock.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -172,22 +171,16 @@
struct rwlock_thread_info* q;
VectorClock old_vc;
- DRD_(vc_copy)(&old_vc, &DRD_(g_threadinfo)[tid].last->vc);
+ DRD_(vc_copy)(&old_vc, DRD_(thread_get_vc)(tid));
VG_(OSetGen_ResetIter)(p->thread_info);
- for ( ; (q = VG_(OSetGen_Next)(p->thread_info)) != 0; )
- {
- if (q->tid != tid)
- {
+ for ( ; (q = VG_(OSetGen_Next)(p->thread_info)) != 0; ) {
+ if (q->tid != tid) {
if (q->latest_wrlocked_segment)
- {
- DRD_(vc_combine)(&DRD_(g_threadinfo)[tid].last->vc,
+ DRD_(vc_combine)(DRD_(thread_get_vc)(tid),
&q->latest_wrlocked_segment->vc);
- }
if (readers_too && q->latest_rdlocked_segment)
- {
- DRD_(vc_combine)(&DRD_(g_threadinfo)[tid].last->vc,
+ DRD_(vc_combine)(DRD_(thread_get_vc)(tid),
&q->latest_rdlocked_segment->vc);
- }
}
}
DRD_(thread_update_conflict_set)(tid, &old_vc);
diff --git a/main/drd/drd_rwlock.h b/main/drd/drd_rwlock.h
index 2914027..7c5a04d 100644
--- a/main/drd/drd_rwlock.h
+++ b/main/drd/drd_rwlock.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_segment.c b/main/drd/drd_segment.c
index a8d1145..775bcd7 100644
--- a/main/drd/drd_segment.c
+++ b/main/drd/drd_segment.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -35,6 +34,11 @@
#include "pub_tool_threadstate.h" // VG_INVALID_THREADID
+/* Global variables. */
+
+Segment* DRD_(g_sg_list);
+
+
/* Local variables. */
static ULong s_segment_merge_count;
@@ -69,8 +73,10 @@
creator_sg = (creator != DRD_INVALID_THREADID
? DRD_(thread_get_segment)(creator) : 0);
- sg->next = 0;
- sg->prev = 0;
+ sg->g_next = NULL;
+ sg->g_prev = NULL;
+ sg->thr_next = NULL;
+ sg->thr_prev = NULL;
sg->tid = created;
sg->refcnt = 1;
@@ -120,6 +126,11 @@
sg = VG_(malloc)("drd.segment.sn.1", sizeof(*sg));
tl_assert(sg);
sg_init(sg, creator, created);
+ if (DRD_(g_sg_list)) {
+ DRD_(g_sg_list)->g_prev = sg;
+ sg->g_next = DRD_(g_sg_list);
+ }
+ DRD_(g_sg_list) = sg;
return sg;
}
@@ -138,6 +149,12 @@
s_segments_alive_count--;
tl_assert(sg);
+ if (sg->g_next)
+ sg->g_next->g_prev = sg->g_prev;
+ if (sg->g_prev)
+ sg->g_prev->g_next = sg->g_next;
+ else
+ DRD_(g_sg_list) = sg->g_next;
DRD_(sg_cleanup)(sg);
VG_(free)(sg);
}
diff --git a/main/drd/drd_segment.h b/main/drd/drd_segment.h
index 8eeceb9..d2d787a 100644
--- a/main/drd/drd_segment.h
+++ b/main/drd/drd_segment.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -42,9 +41,11 @@
typedef struct segment
{
+ struct segment* g_next;
+ struct segment* g_prev;
/** Pointers to next and previous segments executed by the same thread. */
- struct segment* next;
- struct segment* prev;
+ struct segment* thr_next;
+ struct segment* thr_prev;
DrdThreadId tid;
/** Reference count: number of pointers that point to this segment. */
int refcnt;
@@ -59,6 +60,7 @@
struct bitmap bm;
} Segment;
+extern Segment* DRD_(g_sg_list);
Segment* DRD_(sg_new)(const DrdThreadId creator, const DrdThreadId created);
static int DRD_(sg_get_refcnt)(const Segment* const sg);
diff --git a/main/drd/drd_semaphore.c b/main/drd/drd_semaphore.c
index 0b7065f..226c5ea 100644
--- a/main/drd/drd_semaphore.c
+++ b/main/drd/drd_semaphore.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -340,8 +339,7 @@
/**
* Called after sem_wait() finished.
- * @note Do not rely on the value of 'waited' -- some glibc versions do
- * not set it correctly.
+ * @note Some C libraries do not set the 'waited' value correctly.
*/
void DRD_(semaphore_post_wait)(const DrdThreadId tid, const Addr semaphore,
const Bool waited)
@@ -349,16 +347,17 @@
struct semaphore_info* p;
Segment* sg;
+ tl_assert(waited == 0 || waited == 1);
p = semaphore_get(semaphore);
if (s_trace_semaphore)
- DRD_(trace_msg)("[%d] sem_wait 0x%lx value %u -> %u",
+ DRD_(trace_msg)("[%d] sem_wait 0x%lx value %u -> %u%s",
DRD_(thread_get_running_tid)(), semaphore,
- p ? p->value : 0, p ? p->value - 1 : 0);
+ p ? p->value : 0, p ? p->value - waited : 0,
+ waited ? "" : " (did not wait)");
- if (p)
- {
+ if (p) {
p->waiters--;
- p->value--;
+ p->value -= waited;
}
/*
@@ -379,6 +378,9 @@
return;
}
+ if (!waited)
+ return;
+
if (p->waits_to_skip > 0)
p->waits_to_skip--;
else
diff --git a/main/drd/drd_semaphore.h b/main/drd/drd_semaphore.h
index 07ebf39..2ebc130 100644
--- a/main/drd/drd_semaphore.h
+++ b/main/drd/drd_semaphore.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_strmem_intercepts.c b/main/drd/drd_strmem_intercepts.c
index f944ef6..d5fb6e1 100644
--- a/main/drd/drd_strmem_intercepts.c
+++ b/main/drd/drd_strmem_intercepts.c
@@ -1,5 +1,3 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
-
/*--------------------------------------------------------------------*/
/*--- Replacements for strlen() and strnlen(), which run on the ---*/
/*--- simulated CPU. ---*/
@@ -11,7 +9,7 @@
from memchec/mc_replace_strmem.c, which has the following copyright
notice:
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/drd/drd_suppression.c b/main/drd/drd_suppression.c
index bf00411..282ce7a 100644
--- a/main/drd/drd_suppression.c
+++ b/main/drd/drd_suppression.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -38,52 +37,49 @@
/* Local variables. */
-static struct bitmap* DRD_(s_suppressed);
-static struct bitmap* DRD_(s_traced);
-static Bool DRD_(s_trace_suppression);
+static struct bitmap* s_suppressed;
+static struct bitmap* s_traced;
+static Bool s_trace_suppression;
/* Function definitions. */
void DRD_(suppression_set_trace)(const Bool trace_suppression)
{
- DRD_(s_trace_suppression) = trace_suppression;
+ s_trace_suppression = trace_suppression;
}
void DRD_(suppression_init)(void)
{
- tl_assert(DRD_(s_suppressed) == 0);
- tl_assert(DRD_(s_traced) == 0);
- DRD_(s_suppressed) = DRD_(bm_new)();
- DRD_(s_traced) = DRD_(bm_new)();
- tl_assert(DRD_(s_suppressed));
- tl_assert(DRD_(s_traced));
+ tl_assert(s_suppressed == 0);
+ tl_assert(s_traced == 0);
+ s_suppressed = DRD_(bm_new)();
+ s_traced = DRD_(bm_new)();
+ tl_assert(s_suppressed);
+ tl_assert(s_traced);
}
void DRD_(start_suppression)(const Addr a1, const Addr a2,
const char* const reason)
{
- if (DRD_(s_trace_suppression))
- {
+ if (s_trace_suppression)
VG_(message)(Vg_DebugMsg, "start suppression of 0x%lx sz %ld (%s)\n",
a1, a2 - a1, reason);
- }
tl_assert(a1 <= a2);
- DRD_(bm_access_range_store)(DRD_(s_suppressed), a1, a2);
+ DRD_(bm_access_range_store)(s_suppressed, a1, a2);
}
void DRD_(finish_suppression)(const Addr a1, const Addr a2)
{
- if (DRD_(s_trace_suppression))
- {
+ if (s_trace_suppression) {
VG_(message)(Vg_DebugMsg, "finish suppression of 0x%lx sz %ld\n",
a1, a2 - a1);
VG_(get_and_pp_StackTrace)(VG_(get_running_tid)(), 12);
}
tl_assert(a1 <= a2);
- DRD_(bm_clear_store)(DRD_(s_suppressed), a1, a2);
+ DRD_(bm_clear_store)(s_suppressed, a1, a2);
}
/**
@@ -93,7 +89,7 @@
*/
Bool DRD_(is_suppressed)(const Addr a1, const Addr a2)
{
- return DRD_(bm_has)(DRD_(s_suppressed), a1, a2, eStore);
+ return DRD_(bm_has)(s_suppressed, a1, a2, eStore);
}
/**
@@ -103,56 +99,71 @@
*/
Bool DRD_(is_any_suppressed)(const Addr a1, const Addr a2)
{
- return DRD_(bm_has_any_store)(DRD_(s_suppressed), a1, a2);
+ return DRD_(bm_has_any_store)(s_suppressed, a1, a2);
}
void DRD_(mark_hbvar)(const Addr a1)
{
- DRD_(bm_access_range_load)(DRD_(s_suppressed), a1, a1 + 1);
+ DRD_(bm_access_range_load)(s_suppressed, a1, a1 + 1);
}
Bool DRD_(range_contains_suppression_or_hbvar)(const Addr a1, const Addr a2)
{
- return DRD_(bm_has_any_access)(DRD_(s_suppressed), a1, a2);
+ return DRD_(bm_has_any_access)(s_suppressed, a1, a2);
}
-void DRD_(start_tracing_address_range)(const Addr a1, const Addr a2)
+/**
+ * Start tracing memory accesses in the range [a1,a2). If persistent == True,
+ * keep tracing even after memory deallocation and reallocation.
+ */
+void DRD_(start_tracing_address_range)(const Addr a1, const Addr a2,
+ const Bool persistent)
{
tl_assert(a1 <= a2);
- DRD_(bm_access_range_load)(DRD_(s_traced), a1, a2);
- if (! DRD_(g_any_address_traced))
- {
+ if (s_trace_suppression)
+ VG_(message)(Vg_DebugMsg, "start_tracing(0x%lx, %ld) %s\n",
+ a1, a2 - a1, persistent ? "persistent" : "non-persistent");
+
+ DRD_(bm_access_range_load)(s_traced, a1, a2);
+ if (persistent)
+ DRD_(bm_access_range_store)(s_traced, a1, a2);
+ if (!DRD_(g_any_address_traced) && a1 < a2)
DRD_(g_any_address_traced) = True;
- }
}
+/**
+ * Stop tracing memory accesses in the range [a1,a2).
+ */
void DRD_(stop_tracing_address_range)(const Addr a1, const Addr a2)
{
tl_assert(a1 <= a2);
- DRD_(bm_clear_load)(DRD_(s_traced), a1, a2);
- if (DRD_(g_any_address_traced))
- {
- DRD_(g_any_address_traced)
- = DRD_(bm_has_any_load)(DRD_(s_traced), 0, ~(Addr)0);
+ if (s_trace_suppression)
+ VG_(message)(Vg_DebugMsg, "stop_tracing(0x%lx, %ld)\n",
+ a1, a2 - a1);
+
+ if (DRD_(g_any_address_traced)) {
+ DRD_(bm_clear)(s_traced, a1, a2);
+ DRD_(g_any_address_traced) = DRD_(bm_has_any_load_g)(s_traced);
}
}
Bool DRD_(is_any_traced)(const Addr a1, const Addr a2)
{
- return DRD_(bm_has_any_load)(DRD_(s_traced), a1, a2);
+ return DRD_(bm_has_any_access)(s_traced, a1, a2);
}
+/**
+ * Stop using the memory range [a1,a2). Stop tracing memory accesses to
+ * non-persistent address ranges.
+ */
void DRD_(suppression_stop_using_mem)(const Addr a1, const Addr a2)
{
- if (DRD_(s_trace_suppression))
- {
+ if (s_trace_suppression) {
Addr b;
- for (b = a1; b < a2; b++)
- {
- if (DRD_(bm_has_1)(DRD_(s_suppressed), b, eStore))
- {
+ for (b = a1; b < a2; b++) {
+ if (DRD_(bm_has_1)(s_suppressed, b, eStore)) {
VG_(message)(Vg_DebugMsg,
"stop_using_mem(0x%lx, %ld) finish suppression of"
" 0x%lx\n", a1, a2 - a1, b);
@@ -161,6 +172,6 @@
}
tl_assert(a1);
tl_assert(a1 <= a2);
- DRD_(bm_clear)(DRD_(s_suppressed), a1, a2);
- DRD_(bm_clear)(DRD_(s_traced), a1, a2);
+ DRD_(bm_clear)(s_suppressed, a1, a2);
+ DRD_(bm_clear_load)(s_traced, a1, a2);
}
diff --git a/main/drd/drd_suppression.h b/main/drd/drd_suppression.h
index 94cc34f..0fe8bdf 100644
--- a/main/drd/drd_suppression.h
+++ b/main/drd/drd_suppression.h
@@ -1,4 +1,3 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
#ifndef __PUB_CORE_DRD_H
#define __PUB_CORE_DRD_H
@@ -19,7 +18,8 @@
Bool DRD_(is_any_suppressed)(const Addr a1, const Addr a2);
void DRD_(mark_hbvar)(const Addr a1);
Bool DRD_(range_contains_suppression_or_hbvar)(const Addr a1, const Addr a2);
-void DRD_(start_tracing_address_range)(const Addr a1, const Addr a2);
+void DRD_(start_tracing_address_range)(const Addr a1, const Addr a2,
+ const Bool persistent);
void DRD_(stop_tracing_address_range)(const Addr a1, const Addr a2);
Bool DRD_(is_any_traced)(const Addr a1, const Addr a2);
void DRD_(suppression_stop_using_mem)(const Addr a1, const Addr a2);
diff --git a/main/drd/drd_thread.c b/main/drd/drd_thread.c
index 93fe6a2..adc6f62 100644
--- a/main/drd/drd_thread.c
+++ b/main/drd/drd_thread.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -141,6 +140,10 @@
s_join_list_vol = jlv;
}
+void DRD_(thread_init)(void)
+{
+}
+
/**
* Convert Valgrind's ThreadId into a DrdThreadId.
*
@@ -194,8 +197,8 @@
DRD_(g_threadinfo)[i].pthread_create_nesting_level = 0;
DRD_(g_threadinfo)[i].synchr_nesting = 0;
DRD_(g_threadinfo)[i].deletion_seq = s_deletion_tail - 1;
- tl_assert(DRD_(g_threadinfo)[i].first == 0);
- tl_assert(DRD_(g_threadinfo)[i].last == 0);
+ tl_assert(DRD_(g_threadinfo)[i].sg_first == NULL);
+ tl_assert(DRD_(g_threadinfo)[i].sg_last == NULL);
tl_assert(DRD_(IsValidDrdThreadId)(i));
@@ -291,8 +294,8 @@
tl_assert(0 <= (int)created && created < DRD_N_THREADS
&& created != DRD_INVALID_THREADID);
- tl_assert(DRD_(g_threadinfo)[created].first == 0);
- tl_assert(DRD_(g_threadinfo)[created].last == 0);
+ tl_assert(DRD_(g_threadinfo)[created].sg_first == NULL);
+ tl_assert(DRD_(g_threadinfo)[created].sg_last == NULL);
/* Create an initial segment for the newly created thread. */
thread_append_segment(created, DRD_(sg_new)(creator, created));
@@ -491,11 +494,10 @@
tl_assert(DRD_(IsValidDrdThreadId)(tid));
tl_assert(DRD_(g_threadinfo)[tid].synchr_nesting >= 0);
- for (sg = DRD_(g_threadinfo)[tid].last; sg; sg = sg_prev)
- {
- sg_prev = sg->prev;
- sg->prev = 0;
- sg->next = 0;
+ for (sg = DRD_(g_threadinfo)[tid].sg_last; sg; sg = sg_prev) {
+ sg_prev = sg->thr_prev;
+ sg->thr_next = NULL;
+ sg->thr_prev = NULL;
DRD_(sg_put)(sg);
}
DRD_(g_threadinfo)[tid].valid = False;
@@ -505,10 +507,10 @@
DRD_(g_threadinfo)[tid].detached_posix_thread = False;
else
tl_assert(!DRD_(g_threadinfo)[tid].detached_posix_thread);
- DRD_(g_threadinfo)[tid].first = 0;
- DRD_(g_threadinfo)[tid].last = 0;
+ DRD_(g_threadinfo)[tid].sg_first = NULL;
+ DRD_(g_threadinfo)[tid].sg_last = NULL;
- tl_assert(! DRD_(IsValidDrdThreadId)(tid));
+ tl_assert(!DRD_(IsValidDrdThreadId)(tid));
}
/**
@@ -553,7 +555,7 @@
if (DRD_(IsValidDrdThreadId(i)))
DRD_(thread_delete)(i, True);
tl_assert(!DRD_(IsValidDrdThreadId(i)));
- }
+ }
}
/** Called just before pthread_cancel(). */
@@ -595,6 +597,12 @@
}
/** Store the thread mode: joinable or detached. */
+#if defined(VGP_mips32_linux)
+ /* There is a cse related issue in gcc for MIPS. Optimization level
+ has to be lowered, so cse related optimizations are not
+ included.*/
+ __attribute__((optimize("O1")))
+#endif
void DRD_(thread_set_joinable)(const DrdThreadId tid, const Bool joinable)
{
tl_assert(0 <= (int)tid && tid < DRD_N_THREADS
@@ -743,13 +751,14 @@
tl_assert(DRD_(sane_ThreadInfo)(&DRD_(g_threadinfo)[tid]));
#endif
- sg->prev = DRD_(g_threadinfo)[tid].last;
- sg->next = 0;
- if (DRD_(g_threadinfo)[tid].last)
- DRD_(g_threadinfo)[tid].last->next = sg;
- DRD_(g_threadinfo)[tid].last = sg;
- if (DRD_(g_threadinfo)[tid].first == 0)
- DRD_(g_threadinfo)[tid].first = sg;
+ // add at tail
+ sg->thr_prev = DRD_(g_threadinfo)[tid].sg_last;
+ sg->thr_next = NULL;
+ if (DRD_(g_threadinfo)[tid].sg_last)
+ DRD_(g_threadinfo)[tid].sg_last->thr_next = sg;
+ DRD_(g_threadinfo)[tid].sg_last = sg;
+ if (DRD_(g_threadinfo)[tid].sg_first == NULL)
+ DRD_(g_threadinfo)[tid].sg_first = sg;
#ifdef ENABLE_DRD_CONSISTENCY_CHECKS
tl_assert(DRD_(sane_ThreadInfo)(&DRD_(g_threadinfo)[tid]));
@@ -770,14 +779,14 @@
tl_assert(DRD_(sane_ThreadInfo)(&DRD_(g_threadinfo)[tid]));
#endif
- if (sg->prev)
- sg->prev->next = sg->next;
- if (sg->next)
- sg->next->prev = sg->prev;
- if (sg == DRD_(g_threadinfo)[tid].first)
- DRD_(g_threadinfo)[tid].first = sg->next;
- if (sg == DRD_(g_threadinfo)[tid].last)
- DRD_(g_threadinfo)[tid].last = sg->prev;
+ if (sg->thr_prev)
+ sg->thr_prev->thr_next = sg->thr_next;
+ if (sg->thr_next)
+ sg->thr_next->thr_prev = sg->thr_prev;
+ if (sg == DRD_(g_threadinfo)[tid].sg_first)
+ DRD_(g_threadinfo)[tid].sg_first = sg->thr_next;
+ if (sg == DRD_(g_threadinfo)[tid].sg_last)
+ DRD_(g_threadinfo)[tid].sg_last = sg->thr_prev;
DRD_(sg_put)(sg);
#ifdef ENABLE_DRD_CONSISTENCY_CHECKS
@@ -791,10 +800,13 @@
*/
VectorClock* DRD_(thread_get_vc)(const DrdThreadId tid)
{
+ Segment* latest_sg;
+
tl_assert(0 <= (int)tid && tid < DRD_N_THREADS
&& tid != DRD_INVALID_THREADID);
- tl_assert(DRD_(g_threadinfo)[tid].last);
- return &DRD_(g_threadinfo)[tid].last->vc;
+ latest_sg = DRD_(g_threadinfo)[tid].sg_last;
+ tl_assert(latest_sg);
+ return &latest_sg->vc;
}
/**
@@ -802,13 +814,16 @@
*/
void DRD_(thread_get_latest_segment)(Segment** sg, const DrdThreadId tid)
{
+ Segment* latest_sg;
+
tl_assert(sg);
tl_assert(0 <= (int)tid && tid < DRD_N_THREADS
&& tid != DRD_INVALID_THREADID);
- tl_assert(DRD_(g_threadinfo)[tid].last);
+ latest_sg = DRD_(g_threadinfo)[tid].sg_last;
+ tl_assert(latest_sg);
DRD_(sg_put)(*sg);
- *sg = DRD_(sg_get)(DRD_(g_threadinfo)[tid].last);
+ *sg = DRD_(sg_get)(latest_sg);
}
/**
@@ -826,9 +841,8 @@
first = True;
for (i = 0; i < DRD_N_THREADS; i++)
{
- latest_sg = DRD_(g_threadinfo)[i].last;
- if (latest_sg)
- {
+ latest_sg = DRD_(g_threadinfo)[i].sg_last;
+ if (latest_sg) {
if (first)
DRD_(vc_assign)(vc, &latest_sg->vc);
else
@@ -852,9 +866,8 @@
first = True;
for (i = 0; i < DRD_N_THREADS; i++)
{
- latest_sg = DRD_(g_threadinfo)[i].last;
- if (latest_sg)
- {
+ latest_sg = DRD_(g_threadinfo)[i].sg_last;
+ if (latest_sg) {
if (first)
DRD_(vc_assign)(vc, &latest_sg->vc);
else
@@ -895,12 +908,13 @@
DRD_(vc_cleanup)(&thread_vc_max);
}
- for (i = 0; i < DRD_N_THREADS; i++)
- {
+ for (i = 0; i < DRD_N_THREADS; i++) {
Segment* sg;
Segment* sg_next;
- for (sg = DRD_(g_threadinfo)[i].first;
- sg && (sg_next = sg->next) && DRD_(vc_lte)(&sg->vc, &thread_vc_min);
+
+ for (sg = DRD_(g_threadinfo)[i].sg_first;
+ sg && (sg_next = sg->thr_next)
+ && DRD_(vc_lte)(&sg->vc, &thread_vc_min);
sg = sg_next)
{
thread_discard_segment(i, sg);
@@ -944,29 +958,25 @@
{
unsigned i;
- tl_assert(sg1->next);
- tl_assert(sg2->next);
- tl_assert(sg1->next == sg2);
+ tl_assert(sg1->thr_next);
+ tl_assert(sg2->thr_next);
+ tl_assert(sg1->thr_next == sg2);
tl_assert(DRD_(vc_lte)(&sg1->vc, &sg2->vc));
for (i = 0; i < DRD_N_THREADS; i++)
{
Segment* sg;
- for (sg = DRD_(g_threadinfo)[i].first; sg; sg = sg->next)
- {
- if (! sg->next || DRD_(sg_get_refcnt)(sg) > 1)
- {
+ for (sg = DRD_(g_threadinfo)[i].sg_first; sg; sg = sg->thr_next) {
+ if (!sg->thr_next || DRD_(sg_get_refcnt)(sg) > 1) {
if (DRD_(vc_lte)(&sg2->vc, &sg->vc))
break;
if (DRD_(vc_lte)(&sg1->vc, &sg->vc))
return False;
}
}
- for (sg = DRD_(g_threadinfo)[i].last; sg; sg = sg->prev)
- {
- if (! sg->next || DRD_(sg_get_refcnt)(sg) > 1)
- {
+ for (sg = DRD_(g_threadinfo)[i].sg_last; sg; sg = sg->thr_prev) {
+ if (!sg->thr_next || DRD_(sg_get_refcnt)(sg) > 1) {
if (DRD_(vc_lte)(&sg->vc, &sg1->vc))
break;
if (DRD_(vc_lte)(&sg->vc, &sg2->vc))
@@ -1010,17 +1020,17 @@
tl_assert(DRD_(sane_ThreadInfo)(&DRD_(g_threadinfo)[i]));
#endif
- for (sg = DRD_(g_threadinfo)[i].first; sg; sg = sg->next)
- {
- if (DRD_(sg_get_refcnt)(sg) == 1
- && sg->next
- && DRD_(sg_get_refcnt)(sg->next) == 1
- && sg->next->next
- && thread_consistent_segment_ordering(i, sg, sg->next))
- {
- /* Merge sg and sg->next into sg. */
- DRD_(sg_merge)(sg, sg->next);
- thread_discard_segment(i, sg->next);
+ for (sg = DRD_(g_threadinfo)[i].sg_first; sg; sg = sg->thr_next) {
+ if (DRD_(sg_get_refcnt)(sg) == 1 && sg->thr_next) {
+ Segment* const sg_next = sg->thr_next;
+ if (DRD_(sg_get_refcnt)(sg_next) == 1
+ && sg_next->thr_next
+ && thread_consistent_segment_ordering(i, sg, sg_next))
+ {
+ /* Merge sg and sg_next into sg. */
+ DRD_(sg_merge)(sg, sg_next);
+ thread_discard_segment(i, sg_next);
+ }
}
}
@@ -1043,7 +1053,7 @@
&& tid != DRD_INVALID_THREADID);
tl_assert(thread_conflict_set_up_to_date(DRD_(g_drd_running_tid)));
- last_sg = DRD_(g_threadinfo)[tid].last;
+ last_sg = DRD_(g_threadinfo)[tid].sg_last;
new_sg = DRD_(sg_new)(tid, tid);
thread_append_segment(tid, new_sg);
if (tid == DRD_(g_drd_running_tid) && last_sg)
@@ -1070,42 +1080,41 @@
&& joiner != DRD_INVALID_THREADID);
tl_assert(0 <= (int)joinee && joinee < DRD_N_THREADS
&& joinee != DRD_INVALID_THREADID);
- tl_assert(DRD_(g_threadinfo)[joiner].last);
- tl_assert(DRD_(g_threadinfo)[joinee].last);
+ tl_assert(DRD_(g_threadinfo)[joiner].sg_first);
+ tl_assert(DRD_(g_threadinfo)[joiner].sg_last);
+ tl_assert(DRD_(g_threadinfo)[joinee].sg_first);
+ tl_assert(DRD_(g_threadinfo)[joinee].sg_last);
if (DRD_(sg_get_trace)())
{
char *str1, *str2;
- str1 = DRD_(vc_aprint)(&DRD_(g_threadinfo)[joiner].last->vc);
- str2 = DRD_(vc_aprint)(&DRD_(g_threadinfo)[joinee].last->vc);
+ str1 = DRD_(vc_aprint)(DRD_(thread_get_vc)(joiner));
+ str2 = DRD_(vc_aprint)(DRD_(thread_get_vc)(joinee));
VG_(message)(Vg_DebugMsg, "Before join: joiner %s, joinee %s\n",
str1, str2);
VG_(free)(str1);
VG_(free)(str2);
}
- if (joiner == DRD_(g_drd_running_tid))
- {
+ if (joiner == DRD_(g_drd_running_tid)) {
VectorClock old_vc;
- DRD_(vc_copy)(&old_vc, &DRD_(g_threadinfo)[joiner].last->vc);
- DRD_(vc_combine)(&DRD_(g_threadinfo)[joiner].last->vc,
- &DRD_(g_threadinfo)[joinee].last->vc);
+ DRD_(vc_copy)(&old_vc, DRD_(thread_get_vc)(joiner));
+ DRD_(vc_combine)(DRD_(thread_get_vc)(joiner),
+ DRD_(thread_get_vc)(joinee));
DRD_(thread_update_conflict_set)(joiner, &old_vc);
s_update_conflict_set_join_count++;
DRD_(vc_cleanup)(&old_vc);
- }
- else
- {
- DRD_(vc_combine)(&DRD_(g_threadinfo)[joiner].last->vc,
- &DRD_(g_threadinfo)[joinee].last->vc);
+ } else {
+ DRD_(vc_combine)(DRD_(thread_get_vc)(joiner),
+ DRD_(thread_get_vc)(joinee));
}
thread_discard_ordered_segments();
- if (DRD_(sg_get_trace)())
- {
+ if (DRD_(sg_get_trace)()) {
char* str;
- str = DRD_(vc_aprint)(&DRD_(g_threadinfo)[joiner].last->vc);
+
+ str = DRD_(vc_aprint)(DRD_(thread_get_vc)(joiner));
VG_(message)(Vg_DebugMsg, "After join: %s\n", str);
VG_(free)(str);
}
@@ -1121,21 +1130,20 @@
tl_assert(0 <= (int)tid && tid < DRD_N_THREADS
&& tid != DRD_INVALID_THREADID);
- tl_assert(DRD_(g_threadinfo)[tid].last);
+ tl_assert(DRD_(g_threadinfo)[tid].sg_first);
+ tl_assert(DRD_(g_threadinfo)[tid].sg_last);
tl_assert(sg);
tl_assert(vc);
- if (tid != sg->tid)
- {
+ if (tid != sg->tid) {
VectorClock old_vc;
- DRD_(vc_copy)(&old_vc, &DRD_(g_threadinfo)[tid].last->vc);
- DRD_(vc_combine)(&DRD_(g_threadinfo)[tid].last->vc, vc);
- if (DRD_(sg_get_trace)())
- {
+ DRD_(vc_copy)(&old_vc, DRD_(thread_get_vc)(tid));
+ DRD_(vc_combine)(DRD_(thread_get_vc)(tid), vc);
+ if (DRD_(sg_get_trace)()) {
char *str1, *str2;
str1 = DRD_(vc_aprint)(&old_vc);
- str2 = DRD_(vc_aprint)(&DRD_(g_threadinfo)[tid].last->vc);
+ str2 = DRD_(vc_aprint)(DRD_(thread_get_vc)(tid));
VG_(message)(Vg_DebugMsg, "thread %d: vc %s -> %s\n", tid, str1, str2);
VG_(free)(str1);
VG_(free)(str2);
@@ -1147,10 +1155,8 @@
s_update_conflict_set_sync_count++;
DRD_(vc_cleanup)(&old_vc);
- }
- else
- {
- tl_assert(DRD_(vc_lte)(vc, &DRD_(g_threadinfo)[tid].last->vc));
+ } else {
+ tl_assert(DRD_(vc_lte)(vc, DRD_(thread_get_vc)(tid)));
}
}
@@ -1186,12 +1192,10 @@
*/
void DRD_(thread_stop_using_mem)(const Addr a1, const Addr a2)
{
- unsigned i;
Segment* p;
- for (i = 0; i < DRD_N_THREADS; i++)
- for (p = DRD_(g_threadinfo)[i].first; p; p = p->next)
- DRD_(bm_clear)(DRD_(sg_bm)(p), a1, a2);
+ for (p = DRD_(g_sg_list); p; p = p->g_next)
+ DRD_(bm_clear)(DRD_(sg_bm)(p), a1, a2);
DRD_(bm_clear)(DRD_(g_conflict_set), a1, a2);
}
@@ -1228,8 +1232,8 @@
for (i = 0; i < DRD_N_THREADS; i++)
{
- if (DRD_(g_threadinfo)[i].first)
- {
+ p = DRD_(g_threadinfo)[i].sg_first;
+ if (p) {
VG_(printf)("**************\n"
"* thread %3d (%d/%d/%d/%d/0x%lx/%d) *\n"
"**************\n",
@@ -1240,10 +1244,8 @@
DRD_(g_threadinfo)[i].posix_thread_exists,
DRD_(g_threadinfo)[i].pt_threadid,
DRD_(g_threadinfo)[i].detached_posix_thread);
- for (p = DRD_(g_threadinfo)[i].first; p; p = p->next)
- {
+ for ( ; p; p = p->thr_next)
DRD_(sg_print)(p);
- }
}
}
}
@@ -1279,13 +1281,11 @@
&& tid != DRD_INVALID_THREADID);
tl_assert(p);
- for (i = 0; i < DRD_N_THREADS; i++)
- {
- if (i != tid)
- {
+ for (i = 0; i < DRD_N_THREADS; i++) {
+ if (i != tid) {
Segment* q;
- for (q = DRD_(g_threadinfo)[i].last; q; q = q->prev)
- {
+
+ for (q = DRD_(g_threadinfo)[i].sg_last; q; q = q->thr_prev) {
/*
* Since q iterates over the segments of thread i in order of
* decreasing vector clocks, if q->vc <= p->vc, then
@@ -1294,11 +1294,11 @@
*/
if (DRD_(vc_lte)(&q->vc, &p->vc))
break;
- if (! DRD_(vc_lte)(&p->vc, &q->vc))
- {
+ if (!DRD_(vc_lte)(&p->vc, &q->vc)) {
if (DRD_(bm_has_conflict_with)(DRD_(sg_bm)(q), addr, addr + size,
- access_type))
- {
+ access_type)) {
+ Segment* q_next;
+
tl_assert(q->stacktrace);
if (VG_(clo_xml))
VG_(printf_xml)(" <other_segment_start>\n");
@@ -1312,7 +1312,8 @@
else
VG_(message)(Vg_UserMsg,
"Other segment end (thread %d)\n", i);
- show_call_stack(i, q->next ? q->next->stacktrace : 0);
+ q_next = q->thr_next;
+ show_call_stack(i, q_next ? q_next->stacktrace : 0);
if (VG_(clo_xml))
VG_(printf_xml)(" </other_segment_end>\n");
}
@@ -1333,13 +1334,10 @@
tl_assert(0 <= (int)tid && tid < DRD_N_THREADS
&& tid != DRD_INVALID_THREADID);
- for (p = DRD_(g_threadinfo)[tid].first; p; p = p->next)
- {
+ for (p = DRD_(g_threadinfo)[tid].sg_first; p; p = p->thr_next) {
if (DRD_(bm_has)(DRD_(sg_bm)(p), addr, addr + size, access_type))
- {
thread_report_conflicting_segments_segment(tid, addr, size,
access_type, p);
- }
}
}
@@ -1394,33 +1392,28 @@
s_conflict_set_bitmap2_creation_count
-= DRD_(bm_get_bitmap2_creation_count)();
- if (*conflict_set)
- {
+ if (*conflict_set) {
DRD_(bm_cleanup)(*conflict_set);
DRD_(bm_init)(*conflict_set);
- }
- else
- {
+ } else {
*conflict_set = DRD_(bm_new)();
}
- if (s_trace_conflict_set)
- {
+ if (s_trace_conflict_set) {
char* str;
- str = DRD_(vc_aprint)(&DRD_(g_threadinfo)[tid].last->vc);
+ str = DRD_(vc_aprint)(DRD_(thread_get_vc)(tid));
VG_(message)(Vg_DebugMsg,
"computing conflict set for thread %d with vc %s\n",
tid, str);
VG_(free)(str);
}
- p = DRD_(g_threadinfo)[tid].last;
+ p = DRD_(g_threadinfo)[tid].sg_last;
{
unsigned j;
- if (s_trace_conflict_set)
- {
+ if (s_trace_conflict_set) {
char* vc;
vc = DRD_(vc_aprint)(&p->vc);
@@ -1429,18 +1422,14 @@
VG_(free)(vc);
}
- for (j = 0; j < DRD_N_THREADS; j++)
- {
- if (j != tid && DRD_(IsValidDrdThreadId)(j))
- {
+ for (j = 0; j < DRD_N_THREADS; j++) {
+ if (j != tid && DRD_(IsValidDrdThreadId)(j)) {
Segment* q;
- for (q = DRD_(g_threadinfo)[j].last; q; q = q->prev)
- {
- if (! DRD_(vc_lte)(&q->vc, &p->vc)
- && ! DRD_(vc_lte)(&p->vc, &q->vc))
- {
- if (s_trace_conflict_set)
- {
+
+ for (q = DRD_(g_threadinfo)[j].sg_last; q; q = q->thr_prev) {
+ if (!DRD_(vc_lte)(&q->vc, &p->vc)
+ && !DRD_(vc_lte)(&p->vc, &q->vc)) {
+ if (s_trace_conflict_set) {
char* str;
str = DRD_(vc_aprint)(&q->vc);
@@ -1450,11 +1439,8 @@
VG_(free)(str);
}
DRD_(bm_merge2)(*conflict_set, DRD_(sg_bm)(q));
- }
- else
- {
- if (s_trace_conflict_set)
- {
+ } else {
+ if (s_trace_conflict_set) {
char* str;
str = DRD_(vc_aprint)(&q->vc);
@@ -1474,8 +1460,7 @@
s_conflict_set_bitmap2_creation_count
+= DRD_(bm_get_bitmap2_creation_count)();
- if (s_trace_conflict_set_bm)
- {
+ if (s_trace_conflict_set_bm) {
VG_(message)(Vg_DebugMsg, "[%d] new conflict set:\n", tid);
DRD_(bm_print)(*conflict_set);
VG_(message)(Vg_DebugMsg, "[%d] end of new conflict set.\n", tid);
@@ -1500,18 +1485,17 @@
tl_assert(tid == DRD_(g_drd_running_tid));
tl_assert(DRD_(g_conflict_set));
- if (s_trace_conflict_set)
- {
+ if (s_trace_conflict_set) {
char* str;
- str = DRD_(vc_aprint)(&DRD_(g_threadinfo)[tid].last->vc);
+ str = DRD_(vc_aprint)(DRD_(thread_get_vc)(tid));
VG_(message)(Vg_DebugMsg,
"updating conflict set for thread %d with vc %s\n",
tid, str);
VG_(free)(str);
}
- new_vc = &DRD_(g_threadinfo)[tid].last->vc;
+ new_vc = DRD_(thread_get_vc)(tid);
tl_assert(DRD_(vc_lte)(old_vc, new_vc));
DRD_(bm_unmark)(DRD_(g_conflict_set));
@@ -1523,9 +1507,9 @@
if (j == tid || ! DRD_(IsValidDrdThreadId)(j))
continue;
- for (q = DRD_(g_threadinfo)[j].last;
+ for (q = DRD_(g_threadinfo)[j].sg_last;
q && !DRD_(vc_lte)(&q->vc, new_vc);
- q = q->prev) {
+ q = q->thr_prev) {
const Bool included_in_old_conflict_set
= !DRD_(vc_lte)(old_vc, &q->vc);
const Bool included_in_new_conflict_set
@@ -1546,7 +1530,7 @@
DRD_(bm_mark)(DRD_(g_conflict_set), DRD_(sg_bm)(q));
}
- for ( ; q && !DRD_(vc_lte)(&q->vc, old_vc); q = q->prev) {
+ for ( ; q && !DRD_(vc_lte)(&q->vc, old_vc); q = q->thr_prev) {
const Bool included_in_old_conflict_set
= !DRD_(vc_lte)(old_vc, &q->vc);
const Bool included_in_new_conflict_set
@@ -1571,15 +1555,13 @@
DRD_(bm_clear_marked)(DRD_(g_conflict_set));
- p = DRD_(g_threadinfo)[tid].last;
- for (j = 0; j < DRD_N_THREADS; j++)
- {
- if (j != tid && DRD_(IsValidDrdThreadId)(j))
- {
+ p = DRD_(g_threadinfo)[tid].sg_last;
+ for (j = 0; j < DRD_N_THREADS; j++) {
+ if (j != tid && DRD_(IsValidDrdThreadId)(j)) {
Segment* q;
- for (q = DRD_(g_threadinfo)[j].last;
+ for (q = DRD_(g_threadinfo)[j].sg_last;
q && !DRD_(vc_lte)(&q->vc, &p->vc);
- q = q->prev) {
+ q = q->thr_prev) {
if (!DRD_(vc_lte)(&p->vc, &q->vc))
DRD_(bm_merge2_marked)(DRD_(g_conflict_set), DRD_(sg_bm)(q));
}
diff --git a/main/drd/drd_thread.h b/main/drd/drd_thread.h
index b5f2843..68e2917 100644
--- a/main/drd/drd_thread.h
+++ b/main/drd/drd_thread.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -67,8 +66,8 @@
/** Per-thread information managed by DRD. */
typedef struct
{
- Segment* first; /**< Pointer to first segment. */
- Segment* last; /**< Pointer to last segment. */
+ struct segment* sg_first;/**< Segment list. */
+ struct segment* sg_last;
ThreadId vg_threadid; /**< Valgrind thread ID. */
PThreadId pt_threadid; /**< POSIX thread ID. */
Addr stack_min_min; /**< Lowest value stack pointer ever had. */
@@ -131,6 +130,7 @@
void DRD_(thread_set_segment_merge_interval)(const int i);
void DRD_(thread_set_join_list_vol)(const int jlv);
+void DRD_(thread_init)(void);
DrdThreadId DRD_(VgThreadIdToDrdThreadId)(const ThreadId tid);
DrdThreadId DRD_(NewVgThreadIdToDrdThreadId)(const ThreadId tid);
DrdThreadId DRD_(PtThreadIdToDrdThreadId)(const PThreadId tid);
@@ -343,9 +343,9 @@
#ifdef ENABLE_DRD_CONSISTENCY_CHECKS
tl_assert(0 <= (int)tid && tid < DRD_N_THREADS
&& tid != DRD_INVALID_THREADID);
- tl_assert(DRD_(g_threadinfo)[tid].last);
+ tl_assert(DRD_(g_threadinfo)[tid].sg_last);
#endif
- return DRD_(g_threadinfo)[tid].last;
+ return DRD_(g_threadinfo)[tid].sg_last;
}
/** Return a pointer to the latest segment for the running thread. */
diff --git a/main/drd/drd_thread_bitmap.h b/main/drd/drd_thread_bitmap.h
index 1303d14..98d7948 100644
--- a/main/drd/drd_thread_bitmap.h
+++ b/main/drd/drd_thread_bitmap.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_vc.c b/main/drd/drd_vc.c
index 88d541f..f1d34d1 100644
--- a/main/drd/drd_vc.c
+++ b/main/drd/drd_vc.c
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/drd_vc.h b/main/drd/drd_vc.h
index 7ce2c65..096ad88 100644
--- a/main/drd/drd_vc.h
+++ b/main/drd/drd_vc.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/drd/pub_drd_bitmap.h b/main/drd/pub_drd_bitmap.h
index 80a02bc..4ea9d80 100644
--- a/main/drd/pub_drd_bitmap.h
+++ b/main/drd/pub_drd_bitmap.h
@@ -1,8 +1,7 @@
-/* -*- mode: C; c-basic-offset: 3; indent-tabs-mode: nil; -*- */
/*
This file is part of drd, a thread error detector.
- Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>.
+ Copyright (C) 2006-2012 Bart Van Assche <bvanassche@acm.org>.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -76,6 +75,8 @@
/* Function declarations. */
+void DRD_(bm_module_init)(void);
+void DRD_(bm_module_cleanup)(void);
struct bitmap* DRD_(bm_new)(void);
void DRD_(bm_delete)(struct bitmap* const bm);
void DRD_(bm_init)(struct bitmap* const bm);
@@ -98,6 +99,7 @@
Bool DRD_(bm_has)(struct bitmap* const bm,
const Addr a1, const Addr a2,
const BmAccessTypeT access_type);
+Bool DRD_(bm_has_any_load_g)(struct bitmap* const bm);
Bool DRD_(bm_has_any_load)(struct bitmap* const bm,
const Addr a1, const Addr a2);
Bool DRD_(bm_has_any_store)(struct bitmap* const bm,
@@ -148,7 +150,4 @@
ULong DRD_(bm_get_bitmap2_creation_count)(void);
ULong DRD_(bm_get_bitmap2_merge_count)(void);
-void* DRD_(bm2_alloc_node)(HChar* const ec, const SizeT szB);
-void DRD_(bm2_free_node)(void* const bm2);
-
#endif /* __PUB_DRD_BITMAP_H */
diff --git a/main/drd/scripts/download-and-build-firefox b/main/drd/scripts/download-and-build-firefox
deleted file mode 100755
index 84d5778..0000000
--- a/main/drd/scripts/download-and-build-firefox
+++ /dev/null
@@ -1,62 +0,0 @@
-#!/bin/bash
-
-# See also http://developer.mozilla.org/en/docs/Build_Documentation
-SRCURL="ftp://ftp.mozilla.org/pub/mozilla.org/firefox/releases/3.0/source"
-
-SRCDIR="$HOME/software"
-SRC="$SRCDIR/mozilla"
-DOWNLOADS="$SRCDIR/downloads"
-BUILD="${SRC}-build"
-TAR="firefox-3.0-source.tar.bz2"
-PREFIX="$HOME/firefox3"
-MOZCONFIG="$BUILD/mozconfig-firefox"
-export MOZCONFIG
-export LC_ALL=C
-export MAKEFLAGS="-j$(($(grep -c '^processor' /proc/cpuinfo) + 1))"
-
-if [ ! -e /usr/include/dbus-1.0/dbus/dbus-glib.h ]; then
- echo "Please install the dbus-1-glib-devel package first."
- exit 1
-fi
-
-if [ ! -e /usr/include/libIDL-2.0/libIDL/IDL.h ]; then
- echo "Please install the libidl-devel package first."
- exit 1
-fi
-
-if [ ! -e /usr/include/valgrind/valgrind.h ]; then
- echo "Please install the valgrind-devel package first."
- exit 1
-fi
-
-rm -rf ${BUILD} || exit $?
-rm -rf ${PREFIX} || exit $?
-mkdir -p ${DOWNLOADS} || exit $?
-mkdir -p ${BUILD} || exit $?
-cd ${BUILD} || exit $?
-
-if [ ! -e $DOWNLOADS/$TAR ]; then
- ( cd $DOWNLOADS && wget -q $SRCURL/$TAR )
-fi
-
-if [ ! -e $SRC ]; then
- ( cd $SRCDIR && tar -xjf $DOWNLOADS/$TAR )
-fi
-
-cat <<EOF >$MOZCONFIG
-. $SRC/browser/config/mozconfig
-mk_add_options MOZ_OBJDIR="$BUILD"
-ac_add_app_options browser --enable-application=browser
-ac_add_options --disable-optimize
-ac_add_options --disable-tests
-ac_add_options --enable-debug
-ac_add_options --enable-optimize="-O1 -g -pipe"
-ac_add_options --enable-static
-ac_add_options --prefix $PREFIX
-ac_add_options --with-valgrind
-EOF
-
-${SRC}/configure
-
-make -s -j2 || exit $?
-# make -s install || exit $?
diff --git a/main/drd/scripts/download-and-build-gcc b/main/drd/scripts/download-and-build-gcc
deleted file mode 100755
index 8b8cd4d..0000000
--- a/main/drd/scripts/download-and-build-gcc
+++ /dev/null
@@ -1,73 +0,0 @@
-#!/bin/bash
-
-# Make sure that libgmp and libmpfr are installed before you run this script.
-# On Debian systems, e.g. Ubuntu, you can install these libraries as follows:
-# sudo apt-get install libgmp3-dev libmpfr-dev. In openSUSE these packages
-# are called gmp-devel and mpfr-devel.
-
-
-GCC_VERSION=4.5.0
-FSF_MIRROR=ftp://ftp.easynet.be/gnu
-SRCDIR=$HOME/software
-DOWNLOADS=$SRCDIR/downloads
-SRC=$HOME/software/gcc-${GCC_VERSION}
-BUILD=${SRC}-build
-TAR=gcc-${GCC_VERSION}.tar.bz2
-PREFIX=$HOME/gcc-${GCC_VERSION}
-GMP_PREFIX=/usr
-#GMP_PREFIX=$HOME/gmp-5.0.1
-MPFR_PREFIX=/usr
-#MPFR_PREFIX=$HOME/mpfr-2.4.2
-MPC_PREFIX=/usr
-#MPC_PREFIX=$HOME/mpc-0.8.1
-export LC_ALL=C
-export MAKEFLAGS="-j$(($(grep -c '^processor' /proc/cpuinfo) + 1))"
-
-if [ ! -e $GMP_PREFIX/include/gmp.h ]; then
- echo "Please install the gmp library development package first."
- exit 1
-fi
-
-if [ ! -e $MPFR_PREFIX/include/mpfr.h ]; then
- echo "Please install the mpfr library development package first."
- exit 1
-fi
-
-if [ ! -e $MPC_PREFIX/include/mpc.h ]; then
- echo "Please install the mpc library development package first."
- exit 1
-fi
-
-rm -rf ${BUILD} || exit $?
-rm -rf ${PREFIX} || exit $?
-mkdir -p ${DOWNLOADS} || exit $?
-mkdir -p ${BUILD} || exit $?
-cd ${BUILD} || exit $?
-
-if [ ! -e $DOWNLOADS/$TAR ]; then
-(
- if cd $DOWNLOADS; then
- wget -q $FSF_MIRROR/gcc/gcc-${GCC_VERSION}/$TAR \
- || { wget -q -O- $FSF_MIRROR/gcc/gcc-${GCC_VERSION}/${TAR%bz2}gz \
- | gzip -cd | bzip2 -9 >${TAR}; }
- fi
-)
-fi
-
-if [ ! -e $SRC ]; then
- ( cd $SRCDIR && tar -xjf $DOWNLOADS/$TAR )
-fi
-
-${SRC}/configure \
- --disable-linux-futex \
- --disable-mudflap \
- --disable-nls \
- --enable-languages=c,c++ \
- --enable-threads=posix \
- --enable-tls \
- --prefix=$PREFIX \
- --with-gmp=$GMP_PREFIX \
- --with-mpfr=$MPFR_PREFIX \
- --with-mpc=$MPC_PREFIX
-
-time { make -s && make -s install; }
diff --git a/main/drd/scripts/measurement-functions b/main/drd/scripts/measurement-functions
deleted file mode 100644
index 3c2c878..0000000
--- a/main/drd/scripts/measurement-functions
+++ /dev/null
@@ -1,146 +0,0 @@
-#!/bin/bash
-
-########################
-# Function definitions #
-########################
-
-## Print the logarithm base 2 of $1 on stdout.
-function log2 {
- local i
-
- for ((i=0;i<64;i++))
- do
- if [ $((2**i)) = "$1" ]; then
- echo $i
- return 0
- fi
- done
- echo error
- return 1
-}
-
-## Print the size of the level 2 cache in bytes on stdout.
-function get_cache_size {
- local s
- if [ -e /sys/devices/system/cpu/cpu0/cache/index2/size ]; then
- s="$(</sys/devices/system/cpu/cpu0/cache/index2/size)"
- else
- s="$(cat /proc/cpuinfo|while read a b c d e ; do if [ "$a" = cache -a "$b" = size ]; then echo $d $e; break; fi; done)"
- s="${s%B}"
- fi
- if [ "${s%M}" != "$s" ]; then
- echo $((${s%M}*1024*1024))
- elif [ "${s%K}" != "$s" ]; then
- echo $((${s%K}*1024))
- else
- echo $s
- fi
-}
-
-## Read zero or more lines from stdin, and print the average and standard
-# deviation per column. n is the number of lines, m the number of columns.
-# Each line must have the same number of columns.
-function avgstddev {
- awk '{n++;m=NF;for(i=1;i<=NF;i++){sum[i]+=$i;sumsq[i]+=$i*$i}}END{for(i=1;i<=m;i++){d=sumsq[i]/n-sum[i]*sum[i]/n/n;printf "%.2f %.2f ",sum[i]/n,(d>=0.0001?sqrt(d):0.01)}}'
-}
-
-## Query the virtual memory size for the last invocation of command $1 from
-# the information logged by the kernel (BSD process accounting).
-function query_cmd_vsz {
- local pacct
-
- if [ ! -e /usr/sbin/dump-acct ]; then
- echo "Error: userspace tools for BSD process accounting have not been" >&2
- echo "installed. Please install the acct package (Debian systems)." >&2
- return 1
- fi
-
- if ! { dump-acct -h 2>&1 | grep -q -w format; }; then
- echo "Error: the installed version of dump-acct is not recent enough." >&2
- return 1
- fi
-
- if [ -e /var/log/account/pacct ]; then
- pacct=/var/log/account/pacct
- elif [ -e /var/account/pacct ]; then
- pacct=/var/account/pacct
- else
- echo "Where is the pacct file ?" >&2
- return 1
- fi
- /usr/sbin/dump-acct "${pacct}" | \
- grep -- "^$(basename "$1").*|v3|" | \
- cut -f8 -d'|' | \
- tail -n 1 | \
- { read vsz; echo ${vsz:-0}; }
-}
-
-## Query the virtual memory size for the last invocation of command $1 from
-# the information logged by the kernel (BSD process accounting).
-function query_vsz {
- local cmd tool
-
- cmd="$(basename "$1")"
- if [ "${cmd}" = "vg-in-place" ]; then
- tool="tool-not-found"
- for arg in "${@}"
- do
- if [ "${arg#--tool=}" != "${arg}" ]; then
- tool="${arg#--tool=}"
- break
- fi
- done
- vsz_tool="$(query_cmd_vsz "${tool}")"
- awk "END{print $(query_cmd_vsz ${cmd}) + ${vsz_tool:-0}}" \
- </dev/null
- else
- query_cmd_vsz "${cmd}"
- fi
-}
-
-## Echo all arguments on stderr, run the command passed in $1 .. ${$#} three
-# times, pass the output of ${test_input} -p${p} to the command, write the
-# command output to the file specified in ${test_output}, and print the
-# runtime of the command on stdout.
-function measure_runtime {
- local i
-
- echo "$@" >&2
- if [ "${test_output}" != "" ]; then
- echo "$@" >"${test_output}"
- fi
- for ((i=0;i<3;i++))
- do
- echo -n "$("${test_input:-true}" $p | \
- /usr/bin/time --format="%e" "$@" 2>&1 | \
- tee -a "${test_output:-/dev/null}" | \
- tail -n 1) "
- query_vsz "$@"
- done
-}
-
-## Print the average runtime of the command passed in $5 .. ${$#}, the ratio
-# of the runtime to $1 +/- $2 and the ratio of the VSZ to $3 +/- $4.
-function print_runtime_ratio {
- local tmp avg1="$1" stddev1="$2" vsz1="$3" vszdev1="$4"
- local avg2 stddev2 vsz2 vszdev2
-
- if [ "${avg1}" = "" -o "${stddev1}" = "" -o "${vsz1}" = "" -o "${vszdev1}" = "" ]; then
- echo "Error: invalid arguments ($@)."
- exit 1
- fi
-
- shift
- shift
- shift
- shift
-
- tmp="/tmp/test-timing.$$"
- rm -f "${tmp}"
-
- measure_runtime "$@" | avgstddev > "$tmp"
- read avg2 stddev2 vsz2 vszdev2 < "$tmp"
- echo "Average time: ${avg2} +/- ${stddev2} seconds / VSZ ${vsz2} +/- ${vszdev2} KB"
- awk "END{printf "'"'"Ratio = %.2f +/- %.2f; VSZ ratio: %.2f +/- %.2f\n"'"'", ${avg2}/${avg1}, ${avg2}/${avg1}*(${stddev1}/${avg1}+${stddev2}/${avg2}), ${vsz2}/${vsz1}, ${vsz2}/${vsz1}*(${vszdev1}/${vsz1}+${vszdev2}/${vsz2})}" </dev/null
-}
-
diff --git a/main/drd/scripts/ppc-cross/crosstool-patches/powerpc-kernel-compilation.patch b/main/drd/scripts/ppc-cross/crosstool-patches/powerpc-kernel-compilation.patch
deleted file mode 100644
index 0e0d1df..0000000
--- a/main/drd/scripts/ppc-cross/crosstool-patches/powerpc-kernel-compilation.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- orig/crosstool-0.43/crosstool.sh 2006-12-07 01:17:40.000000000 +0100
-+++ crosstool-0.43/crosstool.sh 2009-08-29 09:46:10.000000000 +0200
-@@ -226,8 +226,8 @@
- ia64*) ARCH=ia64 ;;
- mips*) ARCH=mips ;;
- m68k*) ARCH=m68k ;;
-- powerpc64*) ARCH=ppc64 ;;
-- powerpc*) ARCH=ppc ;;
-+ powerpc64*) ARCH=powerpc ;;
-+ powerpc*) ARCH=powerpc ;;
- ppc*) abort "Target $TARGET incompatible with binutils and gcc regression tests; use target powerpc-* or powerpc64-* instead";;
- s390*) ARCH=s390 ;;
- sh*) ARCH=sh ;;
diff --git a/main/drd/scripts/ppc-cross/download-and-build-ppc-crosscompiler b/main/drd/scripts/ppc-cross/download-and-build-ppc-crosscompiler
deleted file mode 100755
index 8b132bb..0000000
--- a/main/drd/scripts/ppc-cross/download-and-build-ppc-crosscompiler
+++ /dev/null
@@ -1,167 +0,0 @@
-#!/bin/bash
-
-############################################################################
-#
-# Script for generating a PowerPC cross compiler using crosstool.
-#
-# Copyright (C) 2009 Bart Van Assche <bvanassche@acm.org>.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation, version 2
-# of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-############################################################################
-
-#########################
-# Function definitions #
-#########################
-
-# Print an error message and exit.
-abort() {
- echo "build failed: $@"
- exit 1
-}
-
-# Print command-line help.
-usage() {
- cat <<EOF
-Usage: $0 [-h] [-t crosstools-directory] [gcc-version glibc-version]
-EOF
-}
-
-# Extract and run crosstool for the specified gcc and glibc versions.
-generate_cross_compiler() {
- export GCC_DIR=gcc-$1
- export GLIBC_DIR=glibc-$2
-
- export GLIBCTHREADS_FILENAME=glibc-linuxthreads-$2
- # glibc-crypt is only needed for glibc 2.1.x and earlier glibc versions.
- unset GLIBCCRYPT_FILENAME
- if [ "${2#2.1.}" != "${2}" ]; then
- GLIBCCRYPT_FILENAME=glibc-crypt-2.1
- fi
- export GLIBCCRYPT_FILENAME
- unset GCC_CORE_DIR
- if [ "${1#4.}" != "${1}" -a "${2#2.[12].}" != "$2" ]; then
- # Use gcc 2.95.3 for compiling glibc 2.1.* and glibc 2.2.*.
- GCC_CORE_DIR=gcc-2.95.3
- else
- GCC_CORE_DIR=gcc-3.3.6
- fi
- export GCC_CORE_DIR
-
- export GCC_EXTRA_CONFIG="--disable-linux-futex --disable-mudflap --disable-nls"
- #GLIBC_ADDON_OPTIONS=
-
- # gcc 4.x aborts with a syntax error on glibc's inline functions if you do
- # not specify -fgnu89-inline.
- #if [ "${1#4.}" != "${1}" ]; then
- # export TARGET_FLAGS="$TARGET_FLAGS -fgnu89-inline"
- #fi
-
- if ! /bin/rm -rf $RESULT_TOP/${GCC_DIR}-${GLIBC_DIR}; then
- abort "Need write permission in $RESULT_TOP/${GCC_DIR}-${GLIBC_DIR}"
- fi
- if ! /bin/mkdir -p $RESULT_TOP/$GCC_DIR-$GLIBC_DIR/$TARGET; then
- abort "Need write permission in $RESULT_TOP/${GCC_DIR}-${GLIBC_DIR}/$TARGET"
- fi
-
- /bin/rm -rf $CROSSTOOL_FOLDER
- if [ ! -e $TARBALLS_DIR/crosstool-${CROSSTOOL_VERSION}.tar.gz ]; then
- (
- if cd $TARBALLS_DIR; then
- wget -q -nc "http://kegel.com/crosstool/crosstool-${CROSSTOOL_VERSION}.tar.gz"
- fi
- )
- fi
- /bin/tar -zxf $TARBALLS_DIR/crosstool-${CROSSTOOL_VERSION}.tar.gz
- /bin/tar -C patches -cf - . | /bin/tar -C $CROSSTOOL_FOLDER/patches -xf -
- (
- cd $CROSSTOOL_FOLDER
- for f in ../crosstool-patches/*
- do
- patch -p1 -f < "$f" || exit $?
- done
- ./all.sh --notest
- )
- # /bin/rm -rf $CROSSTOOL_FOLDER
-}
-
-
-#########################
-# Argument processing #
-#########################
-
-if [ "$SHELL" = "/bin/tcsh" ]; then
- abort "tcsh is not supported."
-fi
-
-set -- $(/usr/bin/getopt ht: "$@")
-while [ "${1#-}" != "${1}" ]; do
- case "$1" in
- -h) usage; exit 1;;
- -t) result_top="$2"; shift; shift;;
- --) shift;;
- esac
-done
-
-#########################
-# Settings #
-#########################
-
-set -e # Exit immediately if a simple command fails.
-set -x # Enable echo mode.
-
-# Variables that are ignored by crosstool.
-
-CROSSTOOL_VERSION=0.43
-CROSSTOOL_FOLDER=$PWD/crosstool-$CROSSTOOL_VERSION
-KERNEL_VERSION=2.6.22
-export LC_ALL=C
-
-
-# Variables that are used by the crosstool script as input.
-
-# Directory where cross-compilation tools will be installed.
-export RESULT_TOP=${result_top:-$HOME/x86_64-ppc}
-# Directory where the tool tar files can be found.
-export TARBALLS_DIR=$HOME/software/downloads
-# Target architecture: Pentium CPU, Linux OS.
-export TARGET=powerpc-linux
-# Compilation flags for target tools such as glibc.
-export TARGET_CFLAGS="-O"
-# Binutils version.
-export BINUTILS_DIR=binutils-2.16.1
-# Languages that must be supported by the gcc cross-compiler.
-export GCC_LANGUAGES="c,c++"
-# GDB version.
-export GDB_DIR=gdb-6.8
-# Linux kernel version.
-export LINUX_DIR=linux-$KERNEL_VERSION
-# Linux kernel config.
-export KERNELCONFIG=$PWD/kernel-config/$KERNEL_VERSION/.config
-# Make flags
-export PARALLELMFLAGS="-s -j3"
-
-##############################
-# Cross-compiler generation. #
-##############################
-
-if ! /bin/mkdir -p $RESULT_TOP; then
- abort "You need write permission in $RESULT_TOP"
-fi
-
-if [ "$#" = 0 ]; then
- generate_cross_compiler 4.1.1 2.3.6
-elif [ "$#" = 2 ]; then
- generate_cross_compiler "$1" "$2"
-else
- usage
- abort "Wrong number of arguments."
-fi
diff --git a/main/drd/scripts/ppc-cross/kernel-config/2.6.22/.config b/main/drd/scripts/ppc-cross/kernel-config/2.6.22/.config
deleted file mode 100644
index 76ef3f9..0000000
--- a/main/drd/scripts/ppc-cross/kernel-config/2.6.22/.config
+++ /dev/null
@@ -1,3352 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22-5.20070920bsc
-# Tue Sep 25 10:40:57 2007
-#
-CONFIG_PPC64=y
-
-#
-# Processor support
-#
-# CONFIG_POWER4_ONLY is not set
-CONFIG_POWER3=y
-CONFIG_POWER4=y
-CONFIG_PPC_FPU=y
-CONFIG_ALTIVEC=y
-CONFIG_PPC_STD_MMU=y
-CONFIG_PPC_MM_SLICES=y
-CONFIG_VIRT_CPU_ACCOUNTING=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=128
-CONFIG_64BIT=y
-CONFIG_PPC_MERGE=y
-CONFIG_MMU=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_IRQ_PER_CPU=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_ARCH_HAS_ILOG2_U32=y
-CONFIG_ARCH_HAS_ILOG2_U64=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_PPC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_COMPAT=y
-CONFIG_SYSVIPC_COMPAT=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_PPC_OF=y
-CONFIG_PPC_UDBG_16550=y
-CONFIG_GENERIC_TBSYNC=y
-CONFIG_AUDIT_ARCH=y
-CONFIG_GENERIC_BUG=y
-# CONFIG_DEFAULT_UIMAGE is not set
-CONFIG_PPC64_SWSUSP=y
-# CONFIG_PPC_DCR_NATIVE is not set
-CONFIG_PPC_DCR_MMIO=y
-CONFIG_PPC_DCR=y
-CONFIG_PPC_OF_PLATFORM_PCI=y
-
-#
-# Hardware Performance Monitoring support
-#
-CONFIG_PERFMON=y
-# CONFIG_PERFMON_DEBUG is not set
-CONFIG_PERFMON_POWER5=m
-CONFIG_PERFMON_CELL=m
-CONFIG_PERFMON_CELL_HW_SMPL=m
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_IPC_NS=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_UTS_NS=y
-CONFIG_AUDIT=y
-CONFIG_AUDITSYSCALL=y
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_CPUSETS=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_MODULE_VERIFY_ELF=y
-CONFIG_MODULE_SIG=y
-# CONFIG_MODULE_SIG_FORCE is not set
-CONFIG_MODULE_VERIFY=y
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-
-#
-# Process debugging support
-#
-CONFIG_PTRACE=y
-CONFIG_UTRACE=y
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-CONFIG_BLK_DEV_IO_TRACE=y
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-
-#
-# Platform support
-#
-CONFIG_PPC_MULTIPLATFORM=y
-# CONFIG_EMBEDDED6xx is not set
-# CONFIG_PPC_82xx is not set
-# CONFIG_PPC_83xx is not set
-# CONFIG_PPC_86xx is not set
-CONFIG_PPC_PSERIES=y
-CONFIG_PPC_SPLPAR=y
-CONFIG_EEH=y
-CONFIG_SCANLOG=y
-CONFIG_LPARCFG=y
-CONFIG_PPC_ISERIES=y
-
-#
-# iSeries device drivers
-#
-CONFIG_VIODASD=m
-CONFIG_VIOCD=m
-CONFIG_VIOTAPE=m
-CONFIG_VIOPATH=y
-# CONFIG_PPC_MPC52xx is not set
-# CONFIG_PPC_MPC5200 is not set
-CONFIG_PPC_PMAC=y
-CONFIG_PPC_PMAC64=y
-CONFIG_PPC_MAPLE=y
-# CONFIG_PPC_PASEMI is not set
-CONFIG_PPC_CELLEB=y
-CONFIG_PPC_PS3=y
-
-#
-# PS3 Platform Options
-#
-CONFIG_PS3_ADVANCED=y
-CONFIG_PS3_HTAB_SIZE=20
-# CONFIG_PS3_DYNAMIC_DMA is not set
-CONFIG_PS3_USE_LPAR_ADDR=y
-CONFIG_PS3_VUART=y
-CONFIG_PS3_PS3AV=y
-CONFIG_PS3_SYS_MANAGER=y
-CONFIG_PS3_STORAGE=m
-CONFIG_PS3_DISK=m
-CONFIG_PS3_ROM=m
-CONFIG_PS3_FLASH=m
-CONFIG_PPC_CELL=y
-CONFIG_PPC_CELL_NATIVE=y
-CONFIG_PPC_IBM_CELL_BLADE=y
-
-#
-# Cell Broadband Engine options
-#
-CONFIG_SPU_FS=m
-CONFIG_SPU_BASE=y
-CONFIG_CBE_RAS=y
-CONFIG_CBE_THERM=m
-CONFIG_CBE_CPUFREQ=m
-CONFIG_CBE_CPUFREQ_PMI=m
-# CONFIG_PQ2ADS is not set
-CONFIG_PPC_NATIVE=y
-CONFIG_UDBG_RTAS_CONSOLE=y
-CONFIG_PPC_UDBG_BEAT=y
-CONFIG_PPC_SYSTEMSIM=y
-# CONFIG_SYSTEMSIM_IDLE is not set
-# CONFIG_SYSTEMSIM_BOOT is not set
-CONFIG_XICS=y
-CONFIG_MPIC=y
-# CONFIG_MPIC_WEIRD is not set
-CONFIG_PPC_I8259=y
-CONFIG_U3_DART=y
-CONFIG_PPC_RTAS=y
-CONFIG_RTAS_ERROR_LOGGING=y
-CONFIG_RTAS_PROC=y
-CONFIG_RTAS_FLASH=y
-CONFIG_PPC_PMI=m
-CONFIG_MMIO_NVRAM=y
-CONFIG_MPIC_U3_HT_IRQS=y
-CONFIG_IBMVIO=y
-CONFIG_IBMEBUS=y
-# CONFIG_PPC_MPC106 is not set
-CONFIG_PPC_970_NAP=y
-CONFIG_PPC_INDIRECT_IO=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-CONFIG_CPU_FREQ_DEBUG=y
-CONFIG_CPU_FREQ_STAT=m
-CONFIG_CPU_FREQ_STAT_DETAILS=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-
-#
-# CPU Frequency drivers
-#
-CONFIG_CPU_FREQ_PMAC64=y
-# CONFIG_CPM2 is not set
-CONFIG_AXON_RAM=m
-
-#
-# Kernel options
-#
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_300 is not set
-CONFIG_HZ_1000=y
-CONFIG_HZ=1000
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-# CONFIG_PREEMPT is not set
-CONFIG_PREEMPT_BKL=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=y
-CONFIG_FORCE_MAX_ZONEORDER=9
-CONFIG_IOMMU_VMERGE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_KEXEC=y
-# CONFIG_CRASH_DUMP is not set
-CONFIG_IRQ_ALL_CPUS=y
-CONFIG_NUMA=y
-CONFIG_NODES_SHIFT=4
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_SELECT_MEMORY_MODEL=y
-# CONFIG_FLATMEM_MANUAL is not set
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_NEED_MULTIPLE_NODES=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_MEMORY_HOTPLUG=y
-
-#
-# Memory hotplug is currently incompatible with Software Suspend
-#
-CONFIG_MEMORY_HOTPLUG_SPARSE=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MIGRATION=y
-CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_ARCH_MEMORY_PROBE=y
-CONFIG_NODES_SPAN_OTHER_NODES=y
-CONFIG_PPC_HAS_HASH_64K=y
-CONFIG_PPC_64K_PAGES=y
-CONFIG_SCHED_SMT=y
-CONFIG_PROC_DEVICETREE=y
-# CONFIG_CMDLINE_BOOL is not set
-CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-CONFIG_PM_DEBUG=y
-# CONFIG_DISABLE_CONSOLE_SUSPEND is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-CONFIG_SOFTWARE_SUSPEND=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_SUSPEND_SMP=y
-# CONFIG_SECCOMP is not set
-# CONFIG_WANT_DEVICE_TREE is not set
-CONFIG_ISA_DMA_API=y
-
-#
-# Bus options
-#
-CONFIG_ZONE_DMA=y
-CONFIG_GENERIC_ISA_DMA=y
-# CONFIG_PPC_INDIRECT_PCI is not set
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_HOTPLUG_PCI_PCIE=m
-# CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODE is not set
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_PCI_MSI=y
-# CONFIG_PCI_DEBUG is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=y
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=y
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
-CONFIG_CARDBUS=y
-
-#
-# PC-card bridges
-#
-CONFIG_YENTA=y
-CONFIG_YENTA_O2=y
-CONFIG_YENTA_RICOH=y
-CONFIG_YENTA_TI=y
-CONFIG_YENTA_ENE_TUNE=y
-CONFIG_YENTA_TOSHIBA=y
-CONFIG_PD6729=m
-CONFIG_I82092=m
-CONFIG_PCCARD_NONSTATIC=y
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_FAKE=m
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-CONFIG_HOTPLUG_PCI_SHPC=m
-# CONFIG_HOTPLUG_PCI_RPA is not set
-CONFIG_KERNEL_START=0xc000000000000000
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=y
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_ASK_IP_FIB_HASH=y
-# CONFIG_IP_FIB_TRIE is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
-CONFIG_IP_ROUTE_VERBOSE=y
-# CONFIG_IP_PNP is not set
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=m
-CONFIG_INET_TCP_DIAG=m
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_BIC=m
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_VEGAS=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-# CONFIG_DEFAULT_BIC is not set
-CONFIG_DEFAULT_CUBIC=y
-# CONFIG_DEFAULT_HTCP is not set
-# CONFIG_DEFAULT_VEGAS is not set
-# CONFIG_DEFAULT_WESTWOOD is not set
-# CONFIG_DEFAULT_RENO is not set
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-CONFIG_IP_VS=m
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IPV6=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=y
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_BEET=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_NETLABEL=y
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-CONFIG_BRIDGE_NETFILTER=y
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK_ENABLED=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV4=m
-# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_TOS=m
-CONFIG_IP_NF_MATCH_RECENT=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_OWNER=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PROTO_GRE=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-
-#
-# IPv6: Netfilter Configuration (EXPERIMENTAL)
-#
-CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_OWNER=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_LOG=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_RAW=m
-
-#
-# DECnet: Netfilter Configuration
-#
-# CONFIG_DECNET_NF_GRABULATOR is not set
-
-#
-# Bridge: Netfilter Configuration
-#
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_ULOG=m
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-CONFIG_IP_DCCP_ACKVEC=y
-
-#
-# DCCP CCIDs Configuration (EXPERIMENTAL)
-#
-CONFIG_IP_DCCP_CCID2=m
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=m
-CONFIG_IP_DCCP_TFRC_LIB=m
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_CCID3_RTO=100
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-CONFIG_NET_DCCPPROBE=m
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_MSG is not set
-# CONFIG_SCTP_DBG_OBJCNT is not set
-# CONFIG_SCTP_HMAC_NONE is not set
-# CONFIG_SCTP_HMAC_SHA1 is not set
-CONFIG_SCTP_HMAC_MD5=y
-CONFIG_TIPC=m
-# CONFIG_TIPC_ADVANCED is not set
-# CONFIG_TIPC_DEBUG is not set
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-# CONFIG_ATM_MPOA is not set
-CONFIG_ATM_BR2684=m
-# CONFIG_ATM_BR2684_IPFILTER is not set
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_DECNET=m
-CONFIG_DECNET_ROUTER=y
-CONFIG_LLC=y
-# CONFIG_LLC2 is not set
-CONFIG_IPX=m
-# CONFIG_IPX_INTERN is not set
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-CONFIG_WAN_ROUTER=m
-
-#
-# QoS and/or fair queueing
-#
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_FIFO=y
-
-#
-# Queueing/Scheduling
-#
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_INGRESS=m
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_ROUTE=y
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_PEDIT=m
-CONFIG_NET_ACT_SIMP=m
-CONFIG_NET_CLS_IND=y
-CONFIG_NET_ESTIMATOR=y
-
-#
-# Network testing
-#
-CONFIG_NET_PKTGEN=m
-# CONFIG_NET_TCPPROBE is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_IRDA=m
-
-#
-# IrDA protocols
-#
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-# CONFIG_IRDA_ULTRA is not set
-
-#
-# IrDA options
-#
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-# CONFIG_IRDA_DEBUG is not set
-
-#
-# Infrared-port device drivers
-#
-
-#
-# SIR device drivers
-#
-CONFIG_IRTTY_SIR=m
-
-#
-# Dongle support
-#
-CONFIG_DONGLE=y
-CONFIG_ESI_DONGLE=m
-CONFIG_ACTISYS_DONGLE=m
-CONFIG_TEKRAM_DONGLE=m
-CONFIG_TOIM3232_DONGLE=m
-CONFIG_LITELINK_DONGLE=m
-CONFIG_MA600_DONGLE=m
-CONFIG_GIRBIL_DONGLE=m
-CONFIG_MCP2120_DONGLE=m
-CONFIG_OLD_BELKIN_DONGLE=m
-CONFIG_ACT200L_DONGLE=m
-CONFIG_KINGSUN_DONGLE=m
-
-#
-# Old SIR device drivers
-#
-
-#
-# Old Serial dongle support
-#
-
-#
-# FIR device drivers
-#
-CONFIG_USB_IRDA=m
-CONFIG_SIGMATEL_FIR=m
-CONFIG_NSC_FIR=m
-CONFIG_WINBOND_FIR=m
-CONFIG_SMC_IRCC_FIR=m
-CONFIG_ALI_FIR=m
-CONFIG_VLSI_FIR=m
-CONFIG_VIA_FIR=m
-CONFIG_MCS_FIR=m
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIUSB=m
-CONFIG_BT_HCIUSB_SCO=y
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIBTUART=m
-CONFIG_BT_HCIVHCI=m
-# CONFIG_AF_RXRPC is not set
-CONFIG_FIB_RULES=y
-
-#
-# Wireless
-#
-CONFIG_CFG80211=m
-CONFIG_WIRELESS_EXT=y
-CONFIG_MAC80211=m
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_DEBUG is not set
-CONFIG_IEEE80211=m
-CONFIG_IEEE80211_DEBUG=y
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_CRYPT_TKIP=m
-CONFIG_IEEE80211_SOFTMAC=m
-CONFIG_IEEE80211_SOFTMAC_DEBUG=y
-CONFIG_RFKILL=m
-CONFIG_RFKILL_INPUT=m
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_DEBUG_DRIVER is not set
-CONFIG_DEBUG_DEVRES=y
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-CONFIG_MTD=m
-# CONFIG_MTD_DEBUG is not set
-CONFIG_MTD_CONCAT=m
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
-# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=m
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_PHYSMAP_OF=m
-CONFIG_MTD_PCI=m
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-CONFIG_MTD_PMC551=m
-# CONFIG_MTD_PMC551_BUGFIX is not set
-# CONFIG_MTD_PMC551_DEBUG is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=m
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-CONFIG_MTD_NAND_ECC_SMC=y
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-CONFIG_MTD_NAND_IDS=m
-CONFIG_MTD_NAND_DISKONCHIP=m
-# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
-# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
-# CONFIG_MTD_NAND_CAFE is not set
-CONFIG_MTD_NAND_NANDSIM=m
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# UBI - Unsorted block images
-#
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_RESERVE=1
-# CONFIG_MTD_UBI_GLUEBI is not set
-
-#
-# UBI debugging options
-#
-# CONFIG_MTD_UBI_DEBUG is not set
-
-#
-# Parallel port support
-#
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_SERIAL=m
-# CONFIG_PARPORT_PC_FIFO is not set
-# CONFIG_PARPORT_PC_SUPERIO is not set
-CONFIG_PARPORT_PC_PCMCIA=m
-# CONFIG_PARPORT_GSC is not set
-# CONFIG_PARPORT_AX88796 is not set
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
-CONFIG_BLK_DEV_FD=m
-CONFIG_PARIDE=m
-
-#
-# Parallel IDE high-level drivers
-#
-CONFIG_PARIDE_PD=m
-CONFIG_PARIDE_PCD=m
-CONFIG_PARIDE_PF=m
-CONFIG_PARIDE_PT=m
-CONFIG_PARIDE_PG=m
-
-#
-# Parallel IDE protocol modules
-#
-CONFIG_PARIDE_ATEN=m
-CONFIG_PARIDE_BPCK=m
-CONFIG_PARIDE_COMM=m
-CONFIG_PARIDE_DSTR=m
-CONFIG_PARIDE_FIT2=m
-CONFIG_PARIDE_FIT3=m
-CONFIG_PARIDE_EPAT=m
-CONFIG_PARIDE_EPATC8=y
-CONFIG_PARIDE_EPIA=m
-CONFIG_PARIDE_FRIQ=m
-CONFIG_PARIDE_FRPW=m
-CONFIG_PARIDE_KBIC=m
-CONFIG_PARIDE_KTTI=m
-CONFIG_PARIDE_ON20=m
-CONFIG_PARIDE_ON26=m
-# CONFIG_BLK_CPQ_DA is not set
-CONFIG_BLK_CPQ_CISS_DA=m
-CONFIG_CISS_SCSI_TAPE=y
-CONFIG_BLK_DEV_DAC960=m
-CONFIG_BLK_DEV_UMEM=m
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_SX8=m
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=4096
-CONFIG_BLK_DEV_SYSTEMSIM=y
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
-
-#
-# Misc devices
-#
-# CONFIG_PHANTOM is not set
-CONFIG_EEPROM_93CX6=m
-# CONFIG_SGI_IOC4 is not set
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-CONFIG_IDEDISK_MULTI_MODE=y
-# CONFIG_BLK_DEV_IDECS is not set
-CONFIG_BLK_DEV_DELKIN=m
-CONFIG_BLK_DEV_IDECD=m
-# CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDEFLOPPY=m
-# CONFIG_BLK_DEV_IDESCSI is not set
-CONFIG_IDE_TASK_IOCTL=y
-# CONFIG_IDE_PROC_FS is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPCI is not set
-# CONFIG_IDEPCI_PCIBUS_ORDER is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_ONLYDISK is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-# CONFIG_BLK_DEV_CMD64X is not set
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
-# CONFIG_BLK_DEV_PIIX is not set
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SL82C105 is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-# CONFIG_BLK_DEV_CELLEB is not set
-CONFIG_BLK_DEV_IDE_PMAC=y
-CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST=y
-CONFIG_BLK_DEV_IDEDMA_PMAC=y
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=m
-CONFIG_SCSI_TGT=m
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-
-#
-# SCSI low-level drivers
-#
-CONFIG_ISCSI_TCP=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
-CONFIG_AIC7XXX_RESET_DELAY_MS=15000
-# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
-CONFIG_AIC7XXX_DEBUG_MASK=0
-# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC7XXX_OLD=m
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=4
-CONFIG_AIC79XX_RESET_DELAY_MS=15000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-CONFIG_SCSI_ARCMSR=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_HPTIOP=m
-# CONFIG_SCSI_BUSLOGIC is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_EATA is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-CONFIG_SCSI_GDTH=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_IBMVSCSI=m
-CONFIG_SCSI_IBMVSCSIS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-CONFIG_SCSI_IPR_TRACE=y
-CONFIG_SCSI_IPR_DUMP=y
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_SCSI_LPFC=m
-CONFIG_SCSI_DC395x=m
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_SCSI_SRP=m
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_FDOMAIN is not set
-CONFIG_PCMCIA_QLOGIC=m
-CONFIG_PCMCIA_SYM53C500=m
-CONFIG_ATA=m
-CONFIG_ATA_NONSTANDARD=y
-CONFIG_SATA_AHCI=m
-CONFIG_SATA_SVW=m
-CONFIG_ATA_PIIX=m
-CONFIG_SATA_MV=m
-CONFIG_SATA_NV=m
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_PROMISE=m
-CONFIG_SATA_SX4=m
-CONFIG_SATA_SIL=m
-CONFIG_SATA_SIL24=m
-CONFIG_SATA_SIS=m
-CONFIG_SATA_ULI=m
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-CONFIG_SATA_INIC162X=m
-CONFIG_PATA_ALI=m
-CONFIG_PATA_AMD=m
-CONFIG_PATA_ARTOP=m
-CONFIG_PATA_ATIIXP=m
-CONFIG_PATA_CMD640_PCI=m
-CONFIG_PATA_CMD64X=m
-CONFIG_PATA_CS5520=m
-CONFIG_PATA_CS5530=m
-CONFIG_PATA_CYPRESS=m
-CONFIG_PATA_EFAR=m
-CONFIG_ATA_GENERIC=m
-CONFIG_PATA_HPT366=m
-CONFIG_PATA_HPT37X=m
-CONFIG_PATA_HPT3X2N=m
-CONFIG_PATA_HPT3X3=m
-CONFIG_PATA_IT821X=m
-CONFIG_PATA_IT8213=m
-CONFIG_PATA_JMICRON=m
-CONFIG_PATA_TRIFLEX=m
-CONFIG_PATA_MARVELL=m
-CONFIG_PATA_MPIIX=m
-CONFIG_PATA_OLDPIIX=m
-CONFIG_PATA_NETCELL=m
-CONFIG_PATA_NS87410=m
-CONFIG_PATA_OPTI=m
-CONFIG_PATA_OPTIDMA=m
-CONFIG_PATA_PCMCIA=m
-CONFIG_PATA_PDC_OLD=m
-# CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RZ1000 is not set
-# CONFIG_PATA_SC1200 is not set
-CONFIG_PATA_SERVERWORKS=m
-CONFIG_PATA_PDC2027X=m
-CONFIG_PATA_SIL680=m
-CONFIG_PATA_SIS=m
-CONFIG_PATA_VIA=m
-CONFIG_PATA_WINBOND=m
-# CONFIG_PATA_SCC is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=y
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_DEBUG=y
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-# CONFIG_DM_DELAY is not set
-
-#
-# Fusion MPT device support
-#
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=40
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LAN=m
-
-#
-# IEEE 1394 (FireWire) support
-#
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-CONFIG_MACINTOSH_DRIVERS=y
-CONFIG_ADB_PMU=y
-CONFIG_ADB_PMU_LED=y
-CONFIG_ADB_PMU_LED_IDE=y
-CONFIG_PMAC_SMU=y
-CONFIG_MAC_EMUMOUSEBTN=y
-CONFIG_THERM_PM72=y
-CONFIG_WINDFARM=y
-CONFIG_WINDFARM_PM81=y
-CONFIG_WINDFARM_PM91=y
-CONFIG_WINDFARM_PM112=y
-CONFIG_PMAC_RACKMETER=m
-CONFIG_NETDEVICES=y
-CONFIG_IFB=m
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-# CONFIG_ARCNET is not set
-CONFIG_PHYLIB=m
-
-#
-# MII PHY device drivers
-#
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_FIXED_PHY=m
-CONFIG_FIXED_MII_10_FDX=y
-CONFIG_FIXED_MII_100_FDX=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_VORTEX=m
-CONFIG_TYPHOON=m
-CONFIG_NET_TULIP=y
-CONFIG_DE2104X=m
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-CONFIG_TULIP_MMIO=y
-# CONFIG_TULIP_NAPI is not set
-CONFIG_DE4X5=m
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-CONFIG_PCMCIA_XIRCOM=m
-# CONFIG_HP100 is not set
-CONFIG_IBMVETH=m
-CONFIG_SYSTEMSIM_NET=m
-CONFIG_NET_PCI=y
-CONFIG_PCNET32=m
-CONFIG_PCNET32_NAPI=y
-CONFIG_AMD8111_ETH=m
-CONFIG_AMD8111E_NAPI=y
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_ADAPTEC_STARFIRE_NAPI=y
-CONFIG_B44=m
-CONFIG_FORCEDETH=m
-CONFIG_FORCEDETH_NAPI=y
-# CONFIG_DGRS is not set
-# CONFIG_EEPRO100 is not set
-CONFIG_E100=m
-CONFIG_FEALNX=m
-CONFIG_NATSEMI=m
-CONFIG_NE2K_PCI=m
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-# CONFIG_8139TOO_TUNE_TWISTER is not set
-CONFIG_8139TOO_8129=y
-# CONFIG_8139_OLD_RX_RESET is not set
-CONFIG_SIS900=m
-CONFIG_EPIC100=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_RHINE_NAPI=y
-CONFIG_SC92031=m
-CONFIG_NET_POCKET=y
-CONFIG_DE600=m
-CONFIG_DE620=m
-CONFIG_NETDEV_1000=y
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-CONFIG_DL2K=m
-CONFIG_E1000=m
-CONFIG_E1000_NAPI=y
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
-CONFIG_NS83820=m
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_R8169=m
-CONFIG_R8169_NAPI=y
-CONFIG_R8169_VLAN=y
-CONFIG_SIS190=m
-CONFIG_SKGE=m
-CONFIG_SKY2=m
-# CONFIG_SK98LIN is not set
-CONFIG_VIA_VELOCITY=m
-CONFIG_TIGON3=m
-CONFIG_BNX2=m
-CONFIG_SPIDER_NET=m
-CONFIG_GELIC_NET=m
-CONFIG_GELIC_WIRELESS=y
-CONFIG_QLA3XXX=m
-CONFIG_ATL1=m
-CONFIG_NETDEV_10000=y
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T1_NAPI=y
-CONFIG_CHELSIO_T3=m
-CONFIG_EHEA=m
-CONFIG_IXGB=m
-CONFIG_IXGB_NAPI=y
-CONFIG_S2IO=m
-CONFIG_S2IO_NAPI=y
-CONFIG_MYRI10GE=m
-CONFIG_NETXEN_NIC=m
-# CONFIG_PASEMI_MAC is not set
-CONFIG_MLX4_CORE=m
-CONFIG_MLX4_DEBUG=y
-CONFIG_TR=y
-CONFIG_IBMOL=m
-CONFIG_3C359=m
-# CONFIG_TMS380TR is not set
-
-#
-# Wireless LAN
-#
-CONFIG_WLAN_PRE80211=y
-# CONFIG_STRIP is not set
-CONFIG_PCMCIA_WAVELAN=m
-CONFIG_PCMCIA_NETWAVE=m
-CONFIG_WLAN_80211=y
-# CONFIG_PCMCIA_RAYCS is not set
-# CONFIG_IPW2100 is not set
-# CONFIG_IPW2200 is not set
-# CONFIG_LIBERTAS is not set
-CONFIG_AIRO=m
-CONFIG_HERMES=m
-CONFIG_APPLE_AIRPORT=m
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_PCI_HERMES=m
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_PCMCIA_HERMES=m
-CONFIG_PCMCIA_SPECTRUM=m
-CONFIG_AIRO_CS=m
-CONFIG_PCMCIA_ATMEL=m
-CONFIG_PCMCIA_WL3501=m
-CONFIG_PRISM54=m
-CONFIG_USB_ZD1201=m
-CONFIG_RTL8187=m
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_HOSTAP_CS=m
-CONFIG_BCM43XX=m
-CONFIG_BCM43XX_DEBUG=y
-CONFIG_BCM43XX_DMA=y
-CONFIG_BCM43XX_PIO=y
-CONFIG_BCM43XX_DMA_AND_PIO_MODE=y
-# CONFIG_BCM43XX_DMA_MODE is not set
-# CONFIG_BCM43XX_PIO_MODE is not set
-# CONFIG_ZD1211RW is not set
-
-#
-# USB Network Adapters
-#
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET_MII=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_3C589=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_PCMCIA_AXNET=m
-# CONFIG_WAN is not set
-CONFIG_ATM_DRIVERS=y
-# CONFIG_ATM_DUMMY is not set
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-# CONFIG_ATM_FIRESTREAM is not set
-# CONFIG_ATM_ZATM is not set
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-# CONFIG_ATM_AMBASSADOR is not set
-# CONFIG_ATM_HORIZON is not set
-CONFIG_ATM_FORE200E_MAYBE=m
-# CONFIG_ATM_FORE200E_PCA is not set
-CONFIG_ATM_HE=m
-# CONFIG_ATM_HE_USE_SUNI is not set
-CONFIG_ISERIES_VETH=m
-CONFIG_FDDI=y
-# CONFIG_DEFXX is not set
-CONFIG_SKFP=m
-# CONFIG_HIPPI is not set
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-# CONFIG_PPP_BSDCOMP is not set
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_PPPOATM=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLHC=m
-CONFIG_SLIP_SMART=y
-# CONFIG_SLIP_MODE_SLIP6 is not set
-CONFIG_NET_FC=y
-# CONFIG_SHAPER is not set
-CONFIG_NETCONSOLE=m
-CONFIG_NETPOLL=y
-CONFIG_NETPOLL_TRAP=y
-CONFIG_NET_POLL_CONTROLLER=y
-
-#
-# ISDN subsystem
-#
-CONFIG_ISDN=m
-
-#
-# Old ISDN4Linux
-#
-CONFIG_ISDN_I4L=m
-CONFIG_ISDN_PPP=y
-CONFIG_ISDN_PPP_VJ=y
-CONFIG_ISDN_MPP=y
-CONFIG_IPPP_FILTER=y
-# CONFIG_ISDN_PPP_BSDCOMP is not set
-CONFIG_ISDN_AUDIO=y
-CONFIG_ISDN_TTY_FAX=y
-
-#
-# ISDN feature submodules
-#
-CONFIG_ISDN_DIVERSION=m
-
-#
-# ISDN4Linux hardware drivers
-#
-
-#
-# Passive cards
-#
-CONFIG_ISDN_DRV_HISAX=m
-
-#
-# D-channel protocol features
-#
-CONFIG_HISAX_EURO=y
-CONFIG_DE_AOC=y
-CONFIG_HISAX_NO_SENDCOMPLETE=y
-CONFIG_HISAX_NO_LLC=y
-CONFIG_HISAX_NO_KEYPAD=y
-CONFIG_HISAX_1TR6=y
-CONFIG_HISAX_NI1=y
-CONFIG_HISAX_MAX_CARDS=8
-
-#
-# HiSax supported cards
-#
-CONFIG_HISAX_16_3=y
-CONFIG_HISAX_S0BOX=y
-CONFIG_HISAX_AVM_A1_PCMCIA=y
-CONFIG_HISAX_ELSA=y
-CONFIG_HISAX_DIEHLDIVA=y
-CONFIG_HISAX_SEDLBAUER=y
-CONFIG_HISAX_NICCY=y
-CONFIG_HISAX_BKM_A4T=y
-CONFIG_HISAX_SCT_QUADRO=y
-CONFIG_HISAX_GAZEL=y
-CONFIG_HISAX_W6692=y
-CONFIG_HISAX_HFC_SX=y
-# CONFIG_HISAX_DEBUG is not set
-
-#
-# HiSax PCMCIA card service modules
-#
-CONFIG_HISAX_SEDLBAUER_CS=m
-CONFIG_HISAX_ELSA_CS=m
-CONFIG_HISAX_AVM_A1_CS=m
-CONFIG_HISAX_TELES_CS=m
-
-#
-# HiSax sub driver modules
-#
-CONFIG_HISAX_ST5481=m
-# CONFIG_HISAX_HFCUSB is not set
-CONFIG_HISAX_HFC4S8S=m
-CONFIG_HISAX_FRITZ_PCIPNP=m
-CONFIG_HISAX_HDLC=y
-
-#
-# Active cards
-#
-
-#
-# Siemens Gigaset
-#
-CONFIG_ISDN_DRV_GIGASET=m
-CONFIG_GIGASET_BASE=m
-CONFIG_GIGASET_M105=m
-CONFIG_GIGASET_M101=m
-# CONFIG_GIGASET_DEBUG is not set
-# CONFIG_GIGASET_UNDOCREQ is not set
-
-#
-# CAPI subsystem
-#
-CONFIG_ISDN_CAPI=m
-CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y
-# CONFIG_CAPI_TRACE is not set
-CONFIG_ISDN_CAPI_MIDDLEWARE=y
-CONFIG_ISDN_CAPI_CAPI20=m
-CONFIG_ISDN_CAPI_CAPIFS_BOOL=y
-CONFIG_ISDN_CAPI_CAPIFS=m
-CONFIG_ISDN_CAPI_CAPIDRV=m
-
-#
-# CAPI hardware drivers
-#
-
-#
-# Active AVM cards
-#
-CONFIG_CAPI_AVM=y
-CONFIG_ISDN_DRV_AVMB1_B1PCI=m
-CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y
-CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m
-CONFIG_ISDN_DRV_AVMB1_AVM_CS=m
-CONFIG_ISDN_DRV_AVMB1_T1PCI=m
-CONFIG_ISDN_DRV_AVMB1_C4=m
-
-#
-# Active Eicon DIVA Server cards
-#
-CONFIG_CAPI_EICON=y
-CONFIG_ISDN_DIVAS=m
-CONFIG_ISDN_DIVAS_BRIPCI=y
-CONFIG_ISDN_DIVAS_PRIPCI=y
-CONFIG_ISDN_DIVAS_DIVACAPI=m
-CONFIG_ISDN_DIVAS_USERIDI=m
-CONFIG_ISDN_DIVAS_MAINT=m
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_POLLDEV=m
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=y
-CONFIG_JOYSTICK_IFORCE_232=y
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-CONFIG_TABLET_USB_GTCO=m
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_WACOM=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_MK712=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_UCB1400=m
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_PCSPKR is not set
-CONFIG_INPUT_ATI_REMOTE=m
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_UINPUT=m
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_PARKBD is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_RAW=m
-CONFIG_GAMEPORT=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_GAMEPORT_EMU10K1=m
-CONFIG_GAMEPORT_FM801=m
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_COMPUTONE is not set
-CONFIG_ROCKETPORT=m
-CONFIG_CYCLADES=m
-# CONFIG_CYZ_INTR is not set
-# CONFIG_DIGIEPCA is not set
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-# CONFIG_MOXA_SMARTIO_NEW is not set
-# CONFIG_ISI is not set
-CONFIG_SYNCLINK=m
-CONFIG_SYNCLINKMP=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_N_HDLC=m
-# CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_RIO is not set
-# CONFIG_STALDRV is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_PMACZILOG=m
-CONFIG_SERIAL_ICOM=m
-CONFIG_SERIAL_TXX9=y
-CONFIG_HAS_TXX9_SERIAL=y
-CONFIG_SERIAL_TXX9_NR_UARTS=6
-CONFIG_SERIAL_TXX9_CONSOLE=y
-CONFIG_SERIAL_JSM=m
-CONFIG_SERIAL_OF_PLATFORM=m
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_CRASH is not set
-CONFIG_PRINTER=m
-CONFIG_LP_CONSOLE=y
-CONFIG_PPDEV=m
-CONFIG_TIPAR=m
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_CONSOLE=y
-CONFIG_HVC_ISERIES=y
-# CONFIG_HVC_FSS is not set
-# CONFIG_PPC_EARLY_DEBUG_FSS is not set
-CONFIG_HVC_RTAS=y
-CONFIG_HVC_BEAT=y
-CONFIG_HVCS=m
-
-#
-# IPMI
-#
-CONFIG_IPMI_HANDLER=m
-# CONFIG_IPMI_PANIC_EVENT is not set
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_WATCHDOG_RTAS=m
-
-#
-# PCI-based Watchdog Cards
-#
-CONFIG_PCIPCWATCHDOG=m
-CONFIG_WDTPCI=m
-CONFIG_WDT_501_PCI=y
-
-#
-# USB-based Watchdog Cards
-#
-CONFIG_USBPCWATCHDOG=m
-CONFIG_HW_RANDOM=y
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
-CONFIG_R3964=m
-# CONFIG_APPLICOM is not set
-CONFIG_AGP=y
-CONFIG_AGP_UNINORTH=y
-CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
-CONFIG_DRM_R128=m
-CONFIG_DRM_RADEON=m
-CONFIG_DRM_MGA=m
-CONFIG_DRM_SIS=m
-CONFIG_DRM_VIA=m
-CONFIG_DRM_SAVAGE=m
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-CONFIG_CARDMAN_4000=m
-CONFIG_CARDMAN_4040=m
-# CONFIG_RAW_DRIVER is not set
-CONFIG_HANGCHECK_TIMER=m
-
-#
-# TPM devices
-#
-CONFIG_TCG_TPM=m
-CONFIG_TCG_ATMEL=m
-CONFIG_DEVPORT=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=m
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCF=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_I810 is not set
-# CONFIG_I2C_PIIX4 is not set
-CONFIG_I2C_ISA=m
-CONFIG_I2C_POWERMAC=y
-CONFIG_I2C_NFORCE2=m
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PARPORT_LIGHT=m
-CONFIG_I2C_PROSAVAGE=m
-CONFIG_I2C_SAVAGE4=m
-CONFIG_I2C_SIMTEC=m
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-CONFIG_I2C_STUB=m
-# CONFIG_I2C_TINY_USB is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-CONFIG_I2C_VOODOO3=m
-
-#
-# Miscellaneous I2C Chip support
-#
-CONFIG_SENSORS_DS1337=m
-CONFIG_SENSORS_DS1374=m
-CONFIG_SENSORS_EEPROM=m
-CONFIG_SENSORS_PCF8574=m
-CONFIG_SENSORS_PCA9539=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_SENSORS_MAX6875=m
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-CONFIG_HWMON=m
-CONFIG_HWMON_VID=m
-CONFIG_SENSORS_ABITUGURU=m
-CONFIG_SENSORS_AD7418=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_ASB100=m
-CONFIG_SENSORS_ATXP1=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_F71805F=m
-CONFIG_SENSORS_FSCHER=m
-CONFIG_SENSORS_FSCPOS=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_MAX6650=m
-CONFIG_SENSORS_PC87360=m
-CONFIG_SENSORS_PC87427=m
-CONFIG_SENSORS_SIS5595=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_SMSC47M192=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_VIA686A=m
-CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_SENSORS_W83627EHF=m
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_SM501=m
-
-#
-# Multimedia devices
-#
-CONFIG_VIDEO_DEV=m
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-
-#
-# Encoders/decoders and other helper chips
-#
-
-#
-# Audio decoders
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-CONFIG_VIDEO_TDA9875=m
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS53L32A=m
-CONFIG_VIDEO_TLV320AIC23B=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-
-#
-# Video decoders
-#
-CONFIG_VIDEO_BT819=m
-CONFIG_VIDEO_BT856=m
-CONFIG_VIDEO_BT866=m
-CONFIG_VIDEO_KS0127=m
-CONFIG_VIDEO_OV7670=m
-CONFIG_VIDEO_SAA7110=m
-CONFIG_VIDEO_SAA7111=m
-CONFIG_VIDEO_SAA7114=m
-CONFIG_VIDEO_SAA711X=m
-CONFIG_VIDEO_SAA7191=m
-CONFIG_VIDEO_TVP5150=m
-CONFIG_VIDEO_VPX3220=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_CX25840=m
-
-#
-# MPEG video encoders
-#
-CONFIG_VIDEO_CX2341X=m
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-CONFIG_VIDEO_SAA7185=m
-CONFIG_VIDEO_ADV7170=m
-CONFIG_VIDEO_ADV7175=m
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-# CONFIG_VIDEO_VIVI is not set
-CONFIG_VIDEO_BT848=m
-CONFIG_VIDEO_BT848_DVB=y
-CONFIG_VIDEO_SAA6588=m
-CONFIG_VIDEO_BWQCAM=m
-CONFIG_VIDEO_CQCAM=m
-CONFIG_VIDEO_W9966=m
-CONFIG_VIDEO_CPIA=m
-CONFIG_VIDEO_CPIA_PP=m
-CONFIG_VIDEO_CPIA_USB=m
-CONFIG_VIDEO_CPIA2=m
-CONFIG_VIDEO_SAA5246A=m
-CONFIG_VIDEO_SAA5249=m
-CONFIG_TUNER_3036=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_MXB=m
-CONFIG_VIDEO_DPC=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_IVTV=m
-# CONFIG_VIDEO_CAFE_CCIC is not set
-CONFIG_V4L_USB_DRIVERS=y
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_29XXX=y
-CONFIG_VIDEO_PVRUSB2_24XXX=y
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_USBVISION=m
-CONFIG_VIDEO_USBVIDEO=m
-CONFIG_USB_VICAM=m
-CONFIG_USB_IBMCAM=m
-CONFIG_USB_KONICAWC=m
-CONFIG_USB_QUICKCAM_MESSENGER=m
-CONFIG_USB_ET61X251=m
-CONFIG_VIDEO_OVCAMCHIP=m
-CONFIG_USB_W9968CF=m
-CONFIG_USB_OV511=m
-CONFIG_USB_SE401=m
-CONFIG_USB_SN9C102=m
-CONFIG_USB_STV680=m
-CONFIG_USB_ZC0301=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_ZR364XX=m
-# CONFIG_RADIO_ADAPTERS is not set
-CONFIG_DVB_CORE=m
-CONFIG_DVB_CORE_ATTACH=y
-CONFIG_DVB_CAPTURE_DRIVERS=y
-
-#
-# Supported SAA7146 based PCI Adapters
-#
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_BUDGET_PATCH=m
-
-#
-# Supported USB Adapters
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_AU6610=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
-CONFIG_DVB_CINERGYT2=m
-CONFIG_DVB_CINERGYT2_TUNING=y
-CONFIG_DVB_CINERGYT2_STREAM_URB_COUNT=32
-CONFIG_DVB_CINERGYT2_STREAM_BUF_SIZE=512
-CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250
-CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y
-CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100
-
-#
-# Supported FlexCopII (B2C2) Adapters
-#
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
-
-#
-# Supported BT878 Adapters
-#
-CONFIG_DVB_BT8XX=m
-
-#
-# Supported Pluto2 Adapters
-#
-CONFIG_DVB_PLUTO2=m
-
-#
-# Supported DVB Frontends
-#
-
-#
-# Customise DVB Frontends
-#
-# CONFIG_DVB_FE_CUSTOMISE is not set
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_TDA10086=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP8870=m
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-
-#
-# Tuners/PLL support
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TDA827X=m
-CONFIG_DVB_TUNER_QT1010=m
-CONFIG_DVB_TUNER_MT2060=m
-
-#
-# Miscellaneous devices
-#
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_ISL6421=m
-CONFIG_DVB_TUA6100=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_VIDEO_TUNER=m
-CONFIG_VIDEO_BUF=m
-CONFIG_VIDEO_BUF_DVB=m
-CONFIG_VIDEO_BTCX=m
-CONFIG_VIDEO_IR=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_DAB=y
-CONFIG_USB_DABUSB=m
-
-#
-# Graphics support
-#
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_LCD_CLASS_DEVICE=m
-
-#
-# Display device support
-#
-CONFIG_DISPLAY_SUPPORT=m
-
-#
-# Display hardware drivers
-#
-CONFIG_VGASTATE=y
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB_DDC=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SVGALIB=m
-CONFIG_FB_MACMODES=y
-CONFIG_FB_BACKLIGHT=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-
-#
-# Frame buffer hardware drivers
-#
-CONFIG_FB_CIRRUS=m
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_CYBER2000 is not set
-CONFIG_FB_OF=y
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_VGA16 is not set
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_NVIDIA=y
-CONFIG_FB_NVIDIA_I2C=y
-# CONFIG_FB_NVIDIA_DEBUG is not set
-CONFIG_FB_NVIDIA_BACKLIGHT=y
-CONFIG_FB_RIVA=m
-# CONFIG_FB_RIVA_I2C is not set
-# CONFIG_FB_RIVA_DEBUG is not set
-CONFIG_FB_RIVA_BACKLIGHT=y
-CONFIG_FB_MATROX=y
-CONFIG_FB_MATROX_MILLENIUM=y
-CONFIG_FB_MATROX_MYSTIQUE=y
-CONFIG_FB_MATROX_G=y
-CONFIG_FB_MATROX_I2C=m
-CONFIG_FB_MATROX_MAVEN=m
-CONFIG_FB_MATROX_MULTIHEAD=y
-CONFIG_FB_RADEON=y
-CONFIG_FB_RADEON_I2C=y
-CONFIG_FB_RADEON_BACKLIGHT=y
-# CONFIG_FB_RADEON_DEBUG is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-CONFIG_FB_S3=m
-CONFIG_FB_SAVAGE=m
-CONFIG_FB_SAVAGE_I2C=y
-CONFIG_FB_SAVAGE_ACCEL=y
-# CONFIG_FB_SIS is not set
-CONFIG_FB_NEOMAGIC=m
-CONFIG_FB_KYRO=m
-CONFIG_FB_3DFX=m
-CONFIG_FB_3DFX_ACCEL=y
-CONFIG_FB_VOODOO1=m
-# CONFIG_FB_VT8623 is not set
-CONFIG_FB_TRIDENT=m
-CONFIG_FB_TRIDENT_ACCEL=y
-# CONFIG_FB_ARK is not set
-# CONFIG_FB_PM3 is not set
-CONFIG_FB_SM501=m
-CONFIG_FB_IBM_GXT4500=y
-CONFIG_FB_PS3=y
-CONFIG_FB_PS3_DEFAULT_SIZE_M=18
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-CONFIG_VGACON_SOFT_SCROLLBACK=y
-CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
-CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DYNAMIC_MINORS=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_VX_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-# CONFIG_SND_SERIAL_U16550 is not set
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-
-#
-# PCI devices
-#
-CONFIG_SND_AD1889=m
-CONFIG_SND_ALS300=m
-CONFIG_SND_ALS4000=m
-CONFIG_SND_ALI5451=m
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AZT3328=m
-CONFIG_SND_BT87X=m
-# CONFIG_SND_BT87X_OVERCLOCK is not set
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_EMU10K1=m
-CONFIG_SND_EMU10K1X=m
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-CONFIG_SND_ES1938=m
-CONFIG_SND_ES1968=m
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_FM801_TEA575X=m
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-CONFIG_SND_ICE1712=m
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_KORG1212_FIRMWARE_IN_KERNEL=y
-CONFIG_SND_MAESTRO3=m
-CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL=y
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-CONFIG_SND_SONICVIBES=m
-CONFIG_SND_TRIDENT=m
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
-CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL=y
-CONFIG_SND_AC97_POWER_SAVE=y
-
-#
-# ALSA PowerMac devices
-#
-CONFIG_SND_POWERMAC=m
-CONFIG_SND_POWERMAC_AUTO_DRC=y
-
-#
-# ALSA PowerPC devices
-#
-CONFIG_SND_PS3=m
-CONFIG_SND_PS3_DEFAULT_START_DELAY=1000
-
-#
-# Apple Onboard Audio driver
-#
-CONFIG_SND_AOA=m
-CONFIG_SND_AOA_FABRIC_LAYOUT=m
-CONFIG_SND_AOA_ONYX=m
-CONFIG_SND_AOA_TAS=m
-CONFIG_SND_AOA_TOONIE=m
-CONFIG_SND_AOA_SOUNDBUS=m
-CONFIG_SND_AOA_SOUNDBUS_I2S=m
-
-#
-# USB devices
-#
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_USX2Y=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-
-#
-# PCMCIA devices
-#
-# CONFIG_SND_VXPOCKET is not set
-# CONFIG_SND_PDAUDIOCF is not set
-
-#
-# System on Chip audio support
-#
-# CONFIG_SND_SOC is not set
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-CONFIG_USB_HIDINPUT_POWERBOOK=y
-CONFIG_HID_FF=y
-CONFIG_HID_PID=y
-CONFIG_LOGITECH_FF=y
-CONFIG_PANTHERLORD_FF=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_USB_HIDDEV=y
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_SPLIT_ISO=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PPC_OF=y
-CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
-CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
-CONFIG_USB_OHCI_HCD_PCI=y
-CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
-CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_SL811_CS=m
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-# CONFIG_USB_STORAGE_ISD200 is not set
-CONFIG_USB_STORAGE_DPCM=y
-CONFIG_USB_STORAGE_USBAT=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_USB_STORAGE_ALAUDA=y
-CONFIG_USB_STORAGE_KARMA=y
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_MON=y
-
-#
-# USB port drivers
-#
-CONFIG_USB_USS720=m
-
-#
-# USB Serial Converter support
-#
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_AIRPRIME=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP2101=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_FUNSOFT=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KEYSPAN_MPR=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19=y
-CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_HP4X=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_DEBUG=m
-CONFIG_USB_EZUSB=y
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_AUERSWALD=m
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_BERRY_CHARGE=m
-CONFIG_USB_LED=m
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-CONFIG_USB_PHIDGET=m
-CONFIG_USB_PHIDGETKIT=m
-CONFIG_USB_PHIDGETMOTORCONTROL=m
-CONFIG_USB_PHIDGETSERVO=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_SISUSBVGA_CON=y
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-CONFIG_MMC=m
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD Card Drivers
-#
-CONFIG_MMC_BLOCK=m
-
-#
-# MMC/SD Host Controller Drivers
-#
-CONFIG_MMC_SDHCI=m
-CONFIG_MMC_WBSD=m
-CONFIG_MMC_TIFM_SD=m
-
-#
-# LED devices
-#
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_IDE_DISK=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-
-#
-# InfiniBand support
-#
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_MTHCA=m
-CONFIG_INFINIBAND_MTHCA_DEBUG=y
-CONFIG_INFINIBAND_IPATH=m
-CONFIG_INFINIBAND_EHCA=m
-CONFIG_INFINIBAND_AMSO1100=m
-# CONFIG_INFINIBAND_AMSO1100_DEBUG is not set
-CONFIG_INFINIBAND_CXGB3=m
-# CONFIG_INFINIBAND_CXGB3_DEBUG is not set
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_INFINIBAND_IPOIB=m
-# CONFIG_INFINIBAND_IPOIB_CM is not set
-CONFIG_INFINIBAND_IPOIB_DEBUG=y
-CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_ISER=m
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-CONFIG_EDAC=m
-
-#
-# Reporting subsystems
-#
-CONFIG_EDAC_DEBUG=y
-CONFIG_EDAC_MM_EDAC=m
-CONFIG_EDAC_CELL=m
-CONFIG_EDAC_POLL=y
-
-#
-# Real Time Clock
-#
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_DRV_DS1307=m
-CONFIG_RTC_DRV_DS1672=m
-CONFIG_RTC_DRV_MAX6900=m
-CONFIG_RTC_DRV_RS5C372=m
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_X1205=m
-CONFIG_RTC_DRV_PCF8563=m
-CONFIG_RTC_DRV_PCF8583=m
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-CONFIG_RTC_DRV_DS1553=m
-CONFIG_RTC_DRV_DS1742=m
-# CONFIG_RTC_DRV_M48T86 is not set
-CONFIG_RTC_DRV_V3020=m
-
-#
-# on-CPU RTC drivers
-#
-
-#
-# DMA Engine support
-#
-CONFIG_DMA_ENGINE=y
-
-#
-# DMA Clients
-#
-CONFIG_NET_DMA=y
-
-#
-# DMA Devices
-#
-CONFIG_INTEL_IOATDMA=m
-
-#
-# Auxiliary Display support
-#
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT2_FS_XIP=y
-CONFIG_FS_XIP=y
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=m
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-CONFIG_REISERFS_PROC_INFO=y
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-# CONFIG_JFS_DEBUG is not set
-# CONFIG_JFS_STATISTICS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_SECURITY=y
-CONFIG_XFS_POSIX_ACL=y
-# CONFIG_XFS_RT is not set
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_NOLOCK=m
-CONFIG_GFS2_FS_LOCKING_DLM=m
-CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_DEBUG_MASKLOG is not set
-CONFIG_MINIX_FS=m
-CONFIG_ROMFS_FS=m
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_QUOTA=y
-# CONFIG_QFMT_V1 is not set
-CONFIG_QFMT_V2=y
-CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_GENERIC_ACL=y
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-# CONFIG_BEFS_DEBUG is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-# CONFIG_SQUASHFS_VMALLOC is not set
-CONFIG_VXFS_FS=m
-# CONFIG_HPFS_FS is not set
-CONFIG_QNX4FS_FS=m
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-# CONFIG_UFS_FS_WRITE is not set
-# CONFIG_UFS_DEBUG is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_DIRECTIO=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BIND34=y
-CONFIG_RPCSEC_GSS_KRB5=m
-CONFIG_RPCSEC_GSS_SPKM3=m
-# CONFIG_SMB_FS is not set
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-CONFIG_NCP_FS=m
-CONFIG_NCPFS_PACKET_SIGNING=y
-CONFIG_NCPFS_IOCTL_LOCKING=y
-CONFIG_NCPFS_STRONG=y
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-CONFIG_NCPFS_SMALLDOS=y
-CONFIG_NCPFS_NLS=y
-CONFIG_NCPFS_EXTRAS=y
-CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
-# CONFIG_AFS_FS is not set
-CONFIG_9P_FS=m
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-# CONFIG_ATARI_PARTITION is not set
-CONFIG_MAC_PARTITION=y
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-CONFIG_SUN_PARTITION=y
-CONFIG_KARMA_PARTITION=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_DEBUG=y
-# CONFIG_UCC_SLOW is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=m
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-
-#
-# Instrumentation Support
-#
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=m
-CONFIG_OPROFILE_CELL=y
-CONFIG_KPROBES=y
-
-#
-# Kernel hacking
-#
-# CONFIG_DEBUG_IGNORE_QUIET is not set
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-CONFIG_HEADERS_CHECK=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_SOFTLOCKUP=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-CONFIG_DEBUG_LIST=y
-# CONFIG_FORCED_INLINING is not set
-CONFIG_BOOT_DELAY=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_LKDTM is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_DEBUG_STACKOVERFLOW=y
-CONFIG_DEBUG_STACK_USAGE=y
-CONFIG_HCALL_STATS=y
-CONFIG_DEBUGGER=y
-CONFIG_XMON=y
-CONFIG_XMON_DEFAULT=y
-CONFIG_XMON_DISASSEMBLY=y
-CONFIG_IRQSTACKS=y
-CONFIG_BOOTX_TEXT=y
-# CONFIG_PPC_EARLY_DEBUG is not set
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_SECURITY=y
-CONFIG_SECURITY_NETWORK=y
-CONFIG_SECURITY_NETWORK_XFRM=y
-CONFIG_SECURITY_CAPABILITIES=y
-# CONFIG_SECURITY_ROOTPLUG is not set
-CONFIG_SECURITY_SELINUX=y
-CONFIG_SECURITY_SELINUX_BOOTPARAM=y
-CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
-CONFIG_SECURITY_SELINUX_DISABLE=y
-CONFIG_SECURITY_SELINUX_DEVELOP=y
-CONFIG_SECURITY_SELINUX_AVC_STATS=y
-CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
-# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set
-# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
-CONFIG_KEYS_COMPAT=y
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_MPILIB=y
-CONFIG_CRYPTO_SIGNATURE=y
-CONFIG_CRYPTO_SIGNATURE_DSA=y
-
-#
-# Hardware crypto devices
-#
diff --git a/main/drd/scripts/run-matinv b/main/drd/scripts/run-matinv
deleted file mode 100755
index a115528..0000000
--- a/main/drd/scripts/run-matinv
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/bash
-
-########################
-# Function definitions #
-########################
-
-source "$(dirname $0)/measurement-functions"
-
-########################
-# Script body #
-########################
-
-DRD_SCRIPTS_DIR="$(dirname $0)"
-if [ "${DRD_SCRIPTS_DIR:0:1}" != "/" ]; then
- DRD_SCRIPTS_DIR="$PWD/$DRD_SCRIPTS_DIR"
-fi
-
-VG="${DRD_SCRIPTS_DIR}/../../vg-in-place"
-MATINV="${DRD_SCRIPTS_DIR}/../../drd/tests/matinv"
-
-
-for n in 200 400
-do
- tmp="/tmp/test-timing.$$"
- rm -f "${tmp}"
-
- measure_runtime ${MATINV} $n | avgstddev > "$tmp"
- read avg1 stddev1 vsz1 vszdev1 < "$tmp"
- echo "Average time: ${avg1} +/- ${stddev1} seconds." \
- " VSZ: ${vsz1} +/- ${vszdev1} KB"
-
- for i in 1 10
- do
- print_runtime_ratio ${avg1} ${stddev1} ${vsz1} ${vszdev1} \
- ${VG} --tool=none ${MATINV} $n -t$i
- print_runtime_ratio ${avg1} ${stddev1} ${vsz1} ${vszdev1} \
- ${VG} --tool=drd ${MATINV} $n -t$i
- done
-done
diff --git a/main/drd/scripts/run-splash2 b/main/drd/scripts/run-splash2
deleted file mode 100755
index b85aa17..0000000
--- a/main/drd/scripts/run-splash2
+++ /dev/null
@@ -1,246 +0,0 @@
-#!/bin/bash
-
-########################
-# Function definitions #
-########################
-
-source "$(dirname $0)/measurement-functions"
-
-function run_test {
- local tmp avg1 stddev1 avg2 stddev2 avg4 stddev4 p
-
- tmp="/tmp/test-timing.$$"
-
- rm -f "${tmp}"
- p=1
- test_output="${1}-p${p}.out" measure_runtime "$@" -p${psep}${p} "${test_args}" | avgstddev > "$tmp"
- read avg1 stddev1 vsz1 vszdev1 rest < "$tmp"
- echo "Average time: ${avg1} +/- ${stddev1} seconds." \
- " VSZ: ${vsz1} +/- ${vszdev1} KB"
-
- if [ "${rest}" != "" ]; then
- echo "Internal error ($rest)"
- exit 1
- fi
-
- rm -f "${tmp}"
- p=2
- test_output="${1}-p${p}.out" measure_runtime "$@" -p${psep}${p} "${test_args}" | avgstddev > "$tmp"
- read avg2 stddev2 vsz2 vszdev2 rest < "$tmp"
- echo "Average time: ${avg2} +/- ${stddev2} seconds." \
- " VSZ: ${vsz2} +/- ${vszdev2} KB"
-
- if [ "${rest}" != "" ]; then
- echo "Internal error ($rest)"
- exit 1
- fi
-
- rm -f "${tmp}"
- p=4
- test_output="${1}-p${p}.out" measure_runtime "$@" -p${psep}${p} "${test_args}" | avgstddev > "$tmp"
- read avg4 stddev4 vsz4 vszdev4 rest < "$tmp"
- echo "Average time: ${avg4} +/- ${stddev4} seconds." \
- " VSZ: ${vsz4} +/- ${vszdev4} KB"
- rm -f "$tmp"
-
- if [ "${rest}" != "" ]; then
- echo "Internal error ($rest)"
- exit 1
- fi
-
- p=1
- test_output="/dev/null" \
- print_runtime_ratio "${avg1}" "${stddev1}" "${vsz1}" "${vszdev1}" "$VG" --tool=none "$@" -p${psep}${p} "${test_args}"
-
- p=4
- test_output="/dev/null" \
- print_runtime_ratio "${avg4}" "${stddev4}" "${vsz4}" "${vszdev4}" "$VG" --tool=none "$@" -p${psep}${p} "${test_args}"
-
- p=4
- test_output="${1}-drd-with-stack-var-4.out" \
- print_runtime_ratio "${avg4}" "${stddev4}" "${vsz4}" "${vszdev4}" \
- "$VG" --tool=drd --first-race-only=yes --check-stack-var=yes \
- --drd-stats=yes "$@" -p${psep}${p} "${test_args}"
-
- p=4
- test_output="${1}-drd-without-stack-var-4.out" \
- print_runtime_ratio "${avg4}" "${stddev4}" "${vsz4}" "${vszdev4}" \
- "$VG" --tool=drd --first-race-only=yes --check-stack-var=no \
- --drd-stats=yes "$@" -p${psep}${p} "${test_args}"
-
- p=4
- test_output="${1}-helgrind-4-none.out" \
- print_runtime_ratio "${avg4}" "${stddev4}" "${vsz4}" "${vszdev4}" "$VG" --tool=helgrind --history-level=none "$@" -p${psep}${p} "${test_args}"
-
- p=4
- test_output="${1}-helgrind-4-approx.out" \
- print_runtime_ratio "${avg4}" "${stddev4}" "${vsz4}" "${vszdev4}" "$VG" --tool=helgrind --history-level=approx "$@" -p${psep}${p} "${test_args}"
-
- p=4
- test_output="${1}-helgrind-4-full.out" \
- print_runtime_ratio "${avg4}" "${stddev4}" "${vsz4}" "${vszdev4}" "$VG" --tool=helgrind --history-level=full "$@" -p${psep}${p} "${test_args}"
-
- echo ''
-}
-
-
-########################
-# Script body #
-########################
-
-DRD_SCRIPTS_DIR="$(dirname $0)"
-if [ "${DRD_SCRIPTS_DIR:0:1}" != "/" ]; then
- DRD_SCRIPTS_DIR="$PWD/$DRD_SCRIPTS_DIR"
-fi
-
-SPLASH2="${DRD_SCRIPTS_DIR}/../splash2"
-if [ ! -e "${SPLASH2}" ]; then
- echo "Error: splash2 directory not found (${SPLASH2})."
- exit 1
-fi
-
-if [ "$VG" = "" ]; then
- VG="${DRD_SCRIPTS_DIR}/../../vg-in-place"
-fi
-
-if [ ! -e "$VG" ]; then
- echo "Could not find $VG."
- exit 1
-fi
-
-######################################################################################################################
-# Meaning of the different colums:
-# 1. SPLASH2 test name.
-# 2. Execution time in seconds for native run with argument -p1.
-# 3. Virtual memory size in KB for the native run with argument -p1.
-# 4. Execution time in seconds for native run with argument -p2.
-# 5. Virtual memory size in KB for the native run with argument -p2.
-# 6. Execution time in seconds for native run with argument -p4.
-# 7. Virtual memory size in KB for the native run with argument -p4.
-# 8. Execution time ratio for --tool=none -p1 versus -p1.
-# 9. Virtual memory size ratio for --tool=none -p1 versus -p1.
-# 10. Execution time ratio for --tool=none -p4 versus -p4.
-# 11. Virtual memory size ratio for --tool=none -p4 versus -p4.
-# 12. Execution time ratio for --tool=drd --check-stack-var=yes -p4 versus -p4.
-# 13. Virtual memory size ratio for --tool=drd --check-stack-var=yes -p4 versus -p4.
-# 14. Execution time ratio for --tool=drd --check-stack-var=no -p4 versus -p4.
-# 15. Virtual memory size ratio for --tool=drd --check-stack-var=no -p4 versus -p4.
-# 16. Execution time ratio for --tool=helgrind --history-level=none -p4 versus -p4.
-# 17. Virtual memory size ratio for --tool=helgrind --history-level=none -p4 versus -p4.
-# 18. Execution time ratio for --tool=helgrind --history-level=approx -p4 versus -p4.
-# 19. Virtual memory size ratio for --tool=helgrind --history-level=approx -p4 versus -p4.
-# 20. Execution time ratio for --tool=helgrind --history-level=full -p4 versus -p4.
-# 21. Virtual memory size ratio for --tool=helgrind --history-level=full -p4 versus -p4.
-# 22. Execution time ratio for Intel Thread Checker -p4 versus -p4.
-# 23. Execution time ratio for Intel Thread Checker -p4 versus -p4.
-#
-# Notes:
-# - Both Helgrind and DRD use a granularity of one byte for data race detection.
-# - Helgrind does detect data races on stack variables. DRD only detects
-# data races on stack variables with --check-stack-var=yes.
-# - The ITC tests have been run on a 4-way 2.5 GHz Pentium 4 workstation, most
-# likely running a 32-bit OS. Not yet clear to me: which OS ? Which
-# granularity does ITC use ? And which m4 macro's have been used by ITC as
-# implementation of the synchronization primitives ?
-#
-# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
-################################################################################################################################################
-# Results: native native native none none DRD DRD HG HG HG ITC ITC
-# -p1 -p2 -p4 -p1 -p4 -p4 -p4+f -p4 -p4 -p4 -p4 -p4+f
-# ..............................................................................................................................................
-# Cholesky 0.11 12016 0.06 22016 0.55 41328 10.3 4.92 1.7 2.14 15 2.61 8 2.61 10 3.96 10 3.96 15 6.14 239 82
-# FFT 0.02 6692 0.02 14888 0.02 31621 17.0 8.01 20.0 2.48 114 3.15 64 3.28 81 4.52 81 4.52 116 5.56 90 41
-# LU, contiguous 0.08 4100 0.05 12304 0.06 28712 11.1 12.44 18.5 2.64 104 3.18 70 3.18 87 4.84 89 4.84 118 5.55 428 128
-# Ocean, contiguous 0.23 16848 0.19 25384 0.23 42528 6.3 3.78 8.3 2.11 87 2.82 62 4.02 71 3.75 71 3.75 195 5.96 90 28
-# Radix 0.21 15136 0.14 23336 0.15 39728 12.6 4.10 22.3 2.19 61 2.87 41 2.94 52 4.03 52 4.03 85 6.13 222 56
-# Raytrace 0.63 207104 0.49 215296 0.49 231680 8.9 1.23 12.9 1.20 385 1.38 86 2.10 158 3.70 160 3.70 222 4.15 172 53
-# Water-n2 0.18 10696 0.09 27072 0.11 59832 12.5 5.46 26.7 1.80 3092 3.03 263 3.06 92 3.28 92 3.28 92 3.55 189 39
-# Water-sp 0.20 4444 0.15 13536 0.10 30269 10.6 11.56 27.0 2.52 405 3.29 69 3.42 95 4.59 95 4.59 97 4.73 183 34
-# ..............................................................................................................................................
-# geometric mean 0.14 13024 0.10 25669 0.14 47655 10.8 5.26 13.5 2.08 161 2.71 59 3.03 66 4.05 66 4.05 95 5.13 180 51
-# ..............................................................................................................................................
-# Hardware: dual-core Intel Core2 Duo E6750, 2.66 GHz, 4 MB L2 cache, 2 GB RAM.
-# Software: openSUSE 11.0 (64-bit edition), runlevel 3, kernel 2.6.30.1, gcc 4.3.1, 32 bit SPLASH-2 executables, valgrind trunk r10648.
-################################################################################################################################################
-
-####
-# Notes:
-# - The ITC performance numbers in the above table originate from table 1 in
-# the following paper:
-# Paul Sack, Brian E. Bliss, Zhiqiang Ma, Paul Petersen, Josep Torrellas,
-# Accurate and efficient filtering for the Intel thread checker race
-# detector, Proceedings of the 1st workshop on Architectural and system
-# support for improving software dependability, San Jose, California,
-# 2006. Pages: 34 - 41.
-# - The input parameters for benchmarks below originate from table 1 in the
-# following paper:
-# The SPLASH-2 programs: characterization and methodological considerations
-# Woo, S.C.; Ohara, M.; Torrie, E.; Singh, J.P.; Gupta, A.
-# 1995. Proceedings of the 22nd Annual International Symposium on Computer
-# Architecture, 22-24 Jun 1995, Page(s): 24 - 36.
-# ftp://www-flash.stanford.edu/pub/splash2/splash2_isca95.ps.Z
-####
-
-cache_size=$(get_cache_size)
-log2_cache_size=$(log2 ${cache_size})
-
-# Cholesky
-(
- cd ${SPLASH2}/codes/kernels/cholesky/inputs
- for f in *Z
- do
- gzip -cd <$f >${f%.Z}
- done
- test_args=tk15.O run_test ../CHOLESKY -C$((cache_size))
-)
-
-# FFT
-run_test ${SPLASH2}/codes/kernels/fft/FFT -t -l$((log2_cache_size/2)) -m16
-
-# LU, contiguous blocks.
-run_test ${SPLASH2}/codes/kernels/lu/contiguous_blocks/LU -n512
-
-# LU, non-contiguous blocks.
-#run_test ${SPLASH2}/codes/kernels/lu/non_contiguous_blocks/LU -n512
-
-# Ocean
-run_test ${SPLASH2}/codes/apps/ocean/contiguous_partitions/OCEAN -n258
-#run_test ${SPLASH2}/codes/apps/ocean/non_contiguous_partitions/OCEAN -n258
-
-# Radiosity. Runs fine on a 32-bit OS, but deadlocks on a 64-bit OS. Not clear to me why.
-if [ $(uname -p) = "i686" ]; then
- psep=' ' run_test ${SPLASH2}/codes/apps/radiosity/RADIOSITY -batch -room -ae 5000.0 -en 0.050 -bf 0.10
-fi
-
-# Radix
-run_test ${SPLASH2}/codes/kernels/radix/RADIX -n$((2**20)) -r1024
-
-# Raytrace
-(
- cd ${SPLASH2}/codes/apps/raytrace/inputs
- rm -f *.env *.geo *.rl
- for f in *Z
- do
- gzip -cd <$f >${f%.Z}
- done
- cd ..
- test_args=inputs/car.env psep='' run_test ./RAYTRACE -m64
-)
-
-# Water-n2
-(
- cd ${SPLASH2}/codes/apps/water-nsquared
- test_input=${DRD_SCRIPTS_DIR}/run-splash2-water-input psep=' ' run_test ./WATER-NSQUARED
-)
-
-# Water-sp
-(
- cd ${SPLASH2}/codes/apps/water-spatial
- test_input=${DRD_SCRIPTS_DIR}/run-splash2-water-input psep=' ' run_test ./WATER-SPATIAL
-)
-
-
-
-# Local variables:
-# compile-command: "./run-splash2"
-# End:
diff --git a/main/drd/scripts/run-splash2-water-input b/main/drd/scripts/run-splash2-water-input
deleted file mode 100755
index 7a735ec..0000000
--- a/main/drd/scripts/run-splash2-water-input
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/bin/bash
-
-## Generate input for water-n2 and water-sp. Argument $1 is the number of
-# processors.
-
-# File format:
-# TSTEP NMOL NSTEP NORDER
-# NSAVE NRST NPRINT NFMC
-# NumProcs CUTOFF
-
-cat <<EOF
- 1.5e-16 512 3 6
--1 3000 3 0
-${1} 6.212752
-EOF
diff --git a/main/drd/tests/Makefile.am b/main/drd/tests/Makefile.am
index f13e4cf..e7f1f3a 100644
--- a/main/drd/tests/Makefile.am
+++ b/main/drd/tests/Makefile.am
@@ -58,9 +58,11 @@
annotate_ignore_write.vgtest \
annotate_ignore_write2.stderr.exp \
annotate_ignore_write2.vgtest \
- annotate_trace_memory.stderr.exp \
+ annotate_trace_memory.stderr.exp-32bit \
+ annotate_trace_memory.stderr.exp-64bit \
annotate_trace_memory.vgtest \
- annotate_trace_memory_xml.stderr.exp \
+ annotate_trace_memory_xml.stderr.exp-32bit \
+ annotate_trace_memory_xml.stderr.exp-64bit \
annotate_trace_memory_xml.vgtest \
annotate_static.stderr.exp \
annotate_static.vgtest \
@@ -219,13 +221,17 @@
sigalrm.vgtest \
sigaltstack.stderr.exp \
sigaltstack.vgtest \
+ std_thread.stderr.exp \
+ std_thread.vgtest \
tc01_simple_race.stderr.exp \
tc01_simple_race.vgtest \
tc02_simple_tls.stderr.exp \
tc02_simple_tls.vgtest \
tc03_re_excl.stderr.exp \
tc03_re_excl.vgtest \
- tc04_free_lock.stderr.exp \
+ tc04_free_lock.stderr.exp-x86 \
+ tc04_free_lock.stderr.exp-ppc \
+ tc04_free_lock.stderr.exp-s390 \
tc04_free_lock.vgtest \
tc05_simple_race.stderr.exp \
tc05_simple_race.vgtest \
@@ -237,8 +243,10 @@
tc08_hbl2.stderr.exp \
tc08_hbl2.stdout.exp \
tc08_hbl2.vgtest \
- tc09_bad_unlock.stderr.exp \
+ tc09_bad_unlock.stderr.exp-x86 \
+ tc09_bad_unlock.stderr.exp-ppc \
tc09_bad_unlock.stderr.exp-glibc2.8 \
+ tc09_bad_unlock.stderr.exp-s390 \
tc09_bad_unlock.vgtest \
tc10_rec_lock.stderr.exp \
tc10_rec_lock.vgtest \
@@ -339,12 +347,22 @@
circular_buffer
endif
+if HAVE_BUILTIN_ATOMIC64
+check_PROGRAMS += \
+ annotate_trace_memory
+endif
+
if HAVE_BUILTIN_ATOMIC_CXX
check_PROGRAMS += \
annotate_smart_pointer \
tsan_unittest
endif
+if HAVE_SHARED_POINTER_ANNOTATION
+check_PROGRAMS += \
+ std_thread
+endif
+
if HAVE_OPENMP
check_PROGRAMS += omp_matinv omp_prime omp_printf
endif
@@ -415,3 +433,6 @@
if HAVE_PTHREAD_BARRIER
matinv_LDADD = $(LDADD) -lm
endif
+
+std_thread_SOURCES = std_thread.cpp
+std_thread_CXXFLAGS = $(AM_CXXFLAGS) -std=c++0x
diff --git a/main/drd/tests/Makefile.in b/main/drd/tests/Makefile.in
new file mode 100644
index 0000000..03d91de
--- /dev/null
+++ b/main/drd/tests/Makefile.in
@@ -0,0 +1,1745 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(noinst_HEADERS) \
+ $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = annotate_hb_err$(EXEEXT) annotate_hb_race$(EXEEXT) \
+ annotate_ignore_rw$(EXEEXT) annotate_ignore_write$(EXEEXT) \
+ annotate_publish_hg$(EXEEXT) annotate_static$(EXEEXT) \
+ bug-235681$(EXEEXT) custom_alloc$(EXEEXT) fp_race$(EXEEXT) \
+ free_is_write$(EXEEXT) hold_lock$(EXEEXT) \
+ linuxthreads_det$(EXEEXT) memory_allocation$(EXEEXT) \
+ monitor_example$(EXEEXT) new_delete$(EXEEXT) \
+ pth_broadcast$(EXEEXT) pth_cancel_locked$(EXEEXT) \
+ pth_cleanup_handler$(EXEEXT) pth_cond_race$(EXEEXT) \
+ pth_create_chain$(EXEEXT) pth_detached$(EXEEXT) \
+ pth_detached_sem$(EXEEXT) pth_detached3$(EXEEXT) \
+ pth_inconsistent_cond_wait$(EXEEXT) pth_mutex_reinit$(EXEEXT) \
+ pth_process_shared_mutex$(EXEEXT) \
+ pth_uninitialized_cond$(EXEEXT) recursive_mutex$(EXEEXT) \
+ rwlock_race$(EXEEXT) rwlock_test$(EXEEXT) \
+ rwlock_type_checking$(EXEEXT) sem_as_mutex$(EXEEXT) \
+ sem_open$(EXEEXT) sigalrm$(EXEEXT) thread_name$(EXEEXT) \
+ threaded-fork$(EXEEXT) trylock$(EXEEXT) unit_bitmap$(EXEEXT) \
+ unit_vc$(EXEEXT) $(am__EXEEXT_1) $(am__EXEEXT_2) \
+ $(am__EXEEXT_3) $(am__EXEEXT_4) $(am__EXEEXT_5) \
+ $(am__EXEEXT_6) $(am__EXEEXT_7) $(am__EXEEXT_8) \
+ $(am__EXEEXT_9)
+@HAVE_BOOST_1_35_TRUE@am__append_3 = boost_thread
+@HAVE_BUILTIN_ATOMIC_TRUE@am__append_4 = \
+@HAVE_BUILTIN_ATOMIC_TRUE@ annotate_barrier \
+@HAVE_BUILTIN_ATOMIC_TRUE@ annotate_rwlock \
+@HAVE_BUILTIN_ATOMIC_TRUE@ atomic_var \
+@HAVE_BUILTIN_ATOMIC_TRUE@ circular_buffer
+
+@HAVE_BUILTIN_ATOMIC64_TRUE@am__append_5 = \
+@HAVE_BUILTIN_ATOMIC64_TRUE@ annotate_trace_memory
+
+@HAVE_BUILTIN_ATOMIC_CXX_TRUE@am__append_6 = \
+@HAVE_BUILTIN_ATOMIC_CXX_TRUE@ annotate_smart_pointer \
+@HAVE_BUILTIN_ATOMIC_CXX_TRUE@ tsan_unittest
+
+@HAVE_SHARED_POINTER_ANNOTATION_TRUE@am__append_7 = \
+@HAVE_SHARED_POINTER_ANNOTATION_TRUE@ std_thread
+
+@HAVE_OPENMP_TRUE@am__append_8 = omp_matinv omp_prime omp_printf
+@HAVE_PTHREAD_BARRIER_TRUE@am__append_9 = matinv pth_barrier pth_barrier_race pth_barrier_reinit \
+@HAVE_PTHREAD_BARRIER_TRUE@ pth_barrier_thr_cr
+
+@HAVE_PTHREAD_CREATE_GLIBC_2_0_TRUE@am__append_10 = pth_create_glibc_2_0
+@HAVE_PTHREAD_SPINLOCK_TRUE@am__append_11 = pth_spinlock
+subdir = drd/tests
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@HAVE_BOOST_1_35_TRUE@am__EXEEXT_1 = boost_thread$(EXEEXT)
+@HAVE_BUILTIN_ATOMIC_TRUE@am__EXEEXT_2 = annotate_barrier$(EXEEXT) \
+@HAVE_BUILTIN_ATOMIC_TRUE@ annotate_rwlock$(EXEEXT) \
+@HAVE_BUILTIN_ATOMIC_TRUE@ atomic_var$(EXEEXT) \
+@HAVE_BUILTIN_ATOMIC_TRUE@ circular_buffer$(EXEEXT)
+@HAVE_BUILTIN_ATOMIC64_TRUE@am__EXEEXT_3 = \
+@HAVE_BUILTIN_ATOMIC64_TRUE@ annotate_trace_memory$(EXEEXT)
+@HAVE_BUILTIN_ATOMIC_CXX_TRUE@am__EXEEXT_4 = \
+@HAVE_BUILTIN_ATOMIC_CXX_TRUE@ annotate_smart_pointer$(EXEEXT) \
+@HAVE_BUILTIN_ATOMIC_CXX_TRUE@ tsan_unittest$(EXEEXT)
+@HAVE_SHARED_POINTER_ANNOTATION_TRUE@am__EXEEXT_5 = \
+@HAVE_SHARED_POINTER_ANNOTATION_TRUE@ std_thread$(EXEEXT)
+@HAVE_OPENMP_TRUE@am__EXEEXT_6 = omp_matinv$(EXEEXT) \
+@HAVE_OPENMP_TRUE@ omp_prime$(EXEEXT) omp_printf$(EXEEXT)
+@HAVE_PTHREAD_BARRIER_TRUE@am__EXEEXT_7 = matinv$(EXEEXT) \
+@HAVE_PTHREAD_BARRIER_TRUE@ pth_barrier$(EXEEXT) \
+@HAVE_PTHREAD_BARRIER_TRUE@ pth_barrier_race$(EXEEXT) \
+@HAVE_PTHREAD_BARRIER_TRUE@ pth_barrier_reinit$(EXEEXT) \
+@HAVE_PTHREAD_BARRIER_TRUE@ pth_barrier_thr_cr$(EXEEXT)
+@HAVE_PTHREAD_CREATE_GLIBC_2_0_TRUE@am__EXEEXT_8 = pth_create_glibc_2_0$(EXEEXT)
+@HAVE_PTHREAD_SPINLOCK_TRUE@am__EXEEXT_9 = pth_spinlock$(EXEEXT)
+annotate_barrier_SOURCES = annotate_barrier.c
+annotate_barrier_OBJECTS = annotate_barrier.$(OBJEXT)
+annotate_barrier_LDADD = $(LDADD)
+annotate_barrier_DEPENDENCIES =
+annotate_hb_err_SOURCES = annotate_hb_err.c
+annotate_hb_err_OBJECTS = annotate_hb_err.$(OBJEXT)
+annotate_hb_err_LDADD = $(LDADD)
+annotate_hb_err_DEPENDENCIES =
+annotate_hb_race_SOURCES = annotate_hb_race.c
+annotate_hb_race_OBJECTS = annotate_hb_race.$(OBJEXT)
+annotate_hb_race_LDADD = $(LDADD)
+annotate_hb_race_DEPENDENCIES =
+annotate_ignore_rw_SOURCES = annotate_ignore_rw.c
+annotate_ignore_rw_OBJECTS = annotate_ignore_rw.$(OBJEXT)
+annotate_ignore_rw_LDADD = $(LDADD)
+annotate_ignore_rw_DEPENDENCIES =
+annotate_ignore_write_SOURCES = annotate_ignore_write.c
+annotate_ignore_write_OBJECTS = annotate_ignore_write.$(OBJEXT)
+annotate_ignore_write_LDADD = $(LDADD)
+annotate_ignore_write_DEPENDENCIES =
+annotate_publish_hg_SOURCES = annotate_publish_hg.c
+annotate_publish_hg_OBJECTS = annotate_publish_hg.$(OBJEXT)
+annotate_publish_hg_LDADD = $(LDADD)
+annotate_publish_hg_DEPENDENCIES =
+annotate_rwlock_SOURCES = annotate_rwlock.c
+annotate_rwlock_OBJECTS = annotate_rwlock.$(OBJEXT)
+annotate_rwlock_LDADD = $(LDADD)
+annotate_rwlock_DEPENDENCIES =
+am__annotate_smart_pointer_SOURCES_DIST = annotate_smart_pointer.cpp
+@HAVE_BUILTIN_ATOMIC_TRUE@am_annotate_smart_pointer_OBJECTS = \
+@HAVE_BUILTIN_ATOMIC_TRUE@ annotate_smart_pointer.$(OBJEXT)
+annotate_smart_pointer_OBJECTS = $(am_annotate_smart_pointer_OBJECTS)
+annotate_smart_pointer_LDADD = $(LDADD)
+annotate_smart_pointer_DEPENDENCIES =
+am_annotate_static_OBJECTS = annotate_static.$(OBJEXT)
+annotate_static_OBJECTS = $(am_annotate_static_OBJECTS)
+annotate_static_LDADD = $(LDADD)
+annotate_static_DEPENDENCIES =
+annotate_trace_memory_SOURCES = annotate_trace_memory.c
+annotate_trace_memory_OBJECTS = annotate_trace_memory.$(OBJEXT)
+annotate_trace_memory_LDADD = $(LDADD)
+annotate_trace_memory_DEPENDENCIES =
+atomic_var_SOURCES = atomic_var.c
+atomic_var_OBJECTS = atomic_var.$(OBJEXT)
+atomic_var_LDADD = $(LDADD)
+atomic_var_DEPENDENCIES =
+am__boost_thread_SOURCES_DIST = boost_thread.cpp
+@HAVE_BOOST_1_35_TRUE@am_boost_thread_OBJECTS = \
+@HAVE_BOOST_1_35_TRUE@ boost_thread-boost_thread.$(OBJEXT)
+boost_thread_OBJECTS = $(am_boost_thread_OBJECTS)
+am__DEPENDENCIES_1 =
+@HAVE_BOOST_1_35_TRUE@boost_thread_DEPENDENCIES = \
+@HAVE_BOOST_1_35_TRUE@ $(am__DEPENDENCIES_1)
+boost_thread_LINK = $(CXXLD) $(boost_thread_CXXFLAGS) $(CXXFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+bug_235681_SOURCES = bug-235681.c
+bug_235681_OBJECTS = bug-235681.$(OBJEXT)
+bug_235681_LDADD = $(LDADD)
+bug_235681_DEPENDENCIES =
+circular_buffer_SOURCES = circular_buffer.c
+circular_buffer_OBJECTS = circular_buffer.$(OBJEXT)
+circular_buffer_LDADD = $(LDADD)
+circular_buffer_DEPENDENCIES =
+custom_alloc_SOURCES = custom_alloc.c
+custom_alloc_OBJECTS = custom_alloc.$(OBJEXT)
+custom_alloc_LDADD = $(LDADD)
+custom_alloc_DEPENDENCIES =
+fp_race_SOURCES = fp_race.c
+fp_race_OBJECTS = fp_race.$(OBJEXT)
+fp_race_LDADD = $(LDADD)
+fp_race_DEPENDENCIES =
+free_is_write_SOURCES = free_is_write.c
+free_is_write_OBJECTS = free_is_write.$(OBJEXT)
+free_is_write_LDADD = $(LDADD)
+free_is_write_DEPENDENCIES =
+hold_lock_SOURCES = hold_lock.c
+hold_lock_OBJECTS = hold_lock.$(OBJEXT)
+hold_lock_LDADD = $(LDADD)
+hold_lock_DEPENDENCIES =
+linuxthreads_det_SOURCES = linuxthreads_det.c
+linuxthreads_det_OBJECTS = linuxthreads_det.$(OBJEXT)
+linuxthreads_det_LDADD = $(LDADD)
+linuxthreads_det_DEPENDENCIES =
+matinv_SOURCES = matinv.c
+matinv_OBJECTS = matinv.$(OBJEXT)
+@HAVE_PTHREAD_BARRIER_TRUE@matinv_DEPENDENCIES = \
+@HAVE_PTHREAD_BARRIER_TRUE@ $(am__DEPENDENCIES_1)
+memory_allocation_SOURCES = memory_allocation.c
+memory_allocation_OBJECTS = memory_allocation.$(OBJEXT)
+memory_allocation_LDADD = $(LDADD)
+memory_allocation_DEPENDENCIES =
+am_monitor_example_OBJECTS = monitor_example.$(OBJEXT)
+monitor_example_OBJECTS = $(am_monitor_example_OBJECTS)
+monitor_example_LDADD = $(LDADD)
+monitor_example_DEPENDENCIES =
+am_new_delete_OBJECTS = new_delete.$(OBJEXT)
+new_delete_OBJECTS = $(am_new_delete_OBJECTS)
+new_delete_LDADD = $(LDADD)
+new_delete_DEPENDENCIES =
+omp_matinv_SOURCES = omp_matinv.c
+omp_matinv_OBJECTS = omp_matinv-omp_matinv.$(OBJEXT)
+@HAVE_OPENMP_TRUE@omp_matinv_DEPENDENCIES = $(am__DEPENDENCIES_1)
+omp_matinv_LINK = $(CCLD) $(omp_matinv_CFLAGS) $(CFLAGS) \
+ $(omp_matinv_LDFLAGS) $(LDFLAGS) -o $@
+omp_prime_SOURCES = omp_prime.c
+omp_prime_OBJECTS = omp_prime-omp_prime.$(OBJEXT)
+@HAVE_OPENMP_TRUE@omp_prime_DEPENDENCIES = $(am__DEPENDENCIES_1)
+omp_prime_LINK = $(CCLD) $(omp_prime_CFLAGS) $(CFLAGS) \
+ $(omp_prime_LDFLAGS) $(LDFLAGS) -o $@
+omp_printf_SOURCES = omp_printf.c
+omp_printf_OBJECTS = omp_printf-omp_printf.$(OBJEXT)
+@HAVE_OPENMP_TRUE@omp_printf_DEPENDENCIES = $(am__DEPENDENCIES_1)
+omp_printf_LINK = $(CCLD) $(omp_printf_CFLAGS) $(CFLAGS) \
+ $(omp_printf_LDFLAGS) $(LDFLAGS) -o $@
+pth_barrier_SOURCES = pth_barrier.c
+pth_barrier_OBJECTS = pth_barrier.$(OBJEXT)
+pth_barrier_LDADD = $(LDADD)
+pth_barrier_DEPENDENCIES =
+pth_barrier_race_SOURCES = pth_barrier_race.c
+pth_barrier_race_OBJECTS = pth_barrier_race.$(OBJEXT)
+pth_barrier_race_LDADD = $(LDADD)
+pth_barrier_race_DEPENDENCIES =
+pth_barrier_reinit_SOURCES = pth_barrier_reinit.c
+pth_barrier_reinit_OBJECTS = pth_barrier_reinit.$(OBJEXT)
+pth_barrier_reinit_LDADD = $(LDADD)
+pth_barrier_reinit_DEPENDENCIES =
+pth_barrier_thr_cr_SOURCES = pth_barrier_thr_cr.c
+pth_barrier_thr_cr_OBJECTS = pth_barrier_thr_cr.$(OBJEXT)
+pth_barrier_thr_cr_LDADD = $(LDADD)
+pth_barrier_thr_cr_DEPENDENCIES =
+pth_broadcast_SOURCES = pth_broadcast.c
+pth_broadcast_OBJECTS = pth_broadcast.$(OBJEXT)
+pth_broadcast_LDADD = $(LDADD)
+pth_broadcast_DEPENDENCIES =
+pth_cancel_locked_SOURCES = pth_cancel_locked.c
+pth_cancel_locked_OBJECTS = pth_cancel_locked.$(OBJEXT)
+pth_cancel_locked_LDADD = $(LDADD)
+pth_cancel_locked_DEPENDENCIES =
+pth_cleanup_handler_SOURCES = pth_cleanup_handler.c
+pth_cleanup_handler_OBJECTS = \
+ pth_cleanup_handler-pth_cleanup_handler.$(OBJEXT)
+pth_cleanup_handler_LDADD = $(LDADD)
+pth_cleanup_handler_DEPENDENCIES =
+pth_cleanup_handler_LINK = $(CCLD) $(pth_cleanup_handler_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+pth_cond_race_SOURCES = pth_cond_race.c
+pth_cond_race_OBJECTS = pth_cond_race.$(OBJEXT)
+pth_cond_race_LDADD = $(LDADD)
+pth_cond_race_DEPENDENCIES =
+pth_create_chain_SOURCES = pth_create_chain.c
+pth_create_chain_OBJECTS = pth_create_chain.$(OBJEXT)
+pth_create_chain_LDADD = $(LDADD)
+pth_create_chain_DEPENDENCIES =
+pth_create_glibc_2_0_SOURCES = pth_create_glibc_2_0.c
+pth_create_glibc_2_0_OBJECTS = pth_create_glibc_2_0.$(OBJEXT)
+pth_create_glibc_2_0_LDADD = $(LDADD)
+pth_create_glibc_2_0_DEPENDENCIES =
+pth_detached_SOURCES = pth_detached.c
+pth_detached_OBJECTS = pth_detached.$(OBJEXT)
+pth_detached_LDADD = $(LDADD)
+pth_detached_DEPENDENCIES =
+pth_detached3_SOURCES = pth_detached3.c
+pth_detached3_OBJECTS = pth_detached3.$(OBJEXT)
+pth_detached3_LDADD = $(LDADD)
+pth_detached3_DEPENDENCIES =
+pth_detached_sem_SOURCES = pth_detached_sem.c
+pth_detached_sem_OBJECTS = pth_detached_sem.$(OBJEXT)
+pth_detached_sem_LDADD = $(LDADD)
+pth_detached_sem_DEPENDENCIES =
+pth_inconsistent_cond_wait_SOURCES = pth_inconsistent_cond_wait.c
+pth_inconsistent_cond_wait_OBJECTS = \
+ pth_inconsistent_cond_wait.$(OBJEXT)
+pth_inconsistent_cond_wait_LDADD = $(LDADD)
+pth_inconsistent_cond_wait_DEPENDENCIES =
+pth_mutex_reinit_SOURCES = pth_mutex_reinit.c
+pth_mutex_reinit_OBJECTS = pth_mutex_reinit.$(OBJEXT)
+pth_mutex_reinit_LDADD = $(LDADD)
+pth_mutex_reinit_DEPENDENCIES =
+pth_process_shared_mutex_SOURCES = pth_process_shared_mutex.c
+pth_process_shared_mutex_OBJECTS = pth_process_shared_mutex.$(OBJEXT)
+pth_process_shared_mutex_LDADD = $(LDADD)
+pth_process_shared_mutex_DEPENDENCIES =
+pth_spinlock_SOURCES = pth_spinlock.c
+pth_spinlock_OBJECTS = pth_spinlock.$(OBJEXT)
+pth_spinlock_LDADD = $(LDADD)
+pth_spinlock_DEPENDENCIES =
+pth_uninitialized_cond_SOURCES = pth_uninitialized_cond.c
+pth_uninitialized_cond_OBJECTS = pth_uninitialized_cond.$(OBJEXT)
+pth_uninitialized_cond_LDADD = $(LDADD)
+pth_uninitialized_cond_DEPENDENCIES =
+recursive_mutex_SOURCES = recursive_mutex.c
+recursive_mutex_OBJECTS = recursive_mutex.$(OBJEXT)
+recursive_mutex_LDADD = $(LDADD)
+recursive_mutex_DEPENDENCIES =
+rwlock_race_SOURCES = rwlock_race.c
+rwlock_race_OBJECTS = rwlock_race.$(OBJEXT)
+rwlock_race_LDADD = $(LDADD)
+rwlock_race_DEPENDENCIES =
+rwlock_test_SOURCES = rwlock_test.c
+rwlock_test_OBJECTS = rwlock_test.$(OBJEXT)
+rwlock_test_LDADD = $(LDADD)
+rwlock_test_DEPENDENCIES =
+rwlock_type_checking_SOURCES = rwlock_type_checking.c
+rwlock_type_checking_OBJECTS = rwlock_type_checking.$(OBJEXT)
+rwlock_type_checking_LDADD = $(LDADD)
+rwlock_type_checking_DEPENDENCIES =
+sem_as_mutex_SOURCES = sem_as_mutex.c
+sem_as_mutex_OBJECTS = sem_as_mutex.$(OBJEXT)
+sem_as_mutex_LDADD = $(LDADD)
+sem_as_mutex_DEPENDENCIES =
+sem_open_SOURCES = sem_open.c
+sem_open_OBJECTS = sem_open.$(OBJEXT)
+sem_open_LDADD = $(LDADD)
+sem_open_DEPENDENCIES =
+sigalrm_SOURCES = sigalrm.c
+sigalrm_OBJECTS = sigalrm.$(OBJEXT)
+sigalrm_LDADD = $(LDADD)
+sigalrm_DEPENDENCIES =
+am_std_thread_OBJECTS = std_thread-std_thread.$(OBJEXT)
+std_thread_OBJECTS = $(am_std_thread_OBJECTS)
+std_thread_LDADD = $(LDADD)
+std_thread_DEPENDENCIES =
+std_thread_LINK = $(CXXLD) $(std_thread_CXXFLAGS) $(CXXFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+thread_name_SOURCES = thread_name.c
+thread_name_OBJECTS = thread_name.$(OBJEXT)
+thread_name_LDADD = $(LDADD)
+thread_name_DEPENDENCIES =
+threaded_fork_SOURCES = threaded-fork.c
+threaded_fork_OBJECTS = threaded-fork.$(OBJEXT)
+threaded_fork_LDADD = $(LDADD)
+threaded_fork_DEPENDENCIES =
+trylock_SOURCES = trylock.c
+trylock_OBJECTS = trylock.$(OBJEXT)
+trylock_LDADD = $(LDADD)
+trylock_DEPENDENCIES =
+am_tsan_unittest_OBJECTS = tsan_unittest-tsan_unittest.$(OBJEXT)
+tsan_unittest_OBJECTS = $(am_tsan_unittest_OBJECTS)
+tsan_unittest_LDADD = $(LDADD)
+tsan_unittest_DEPENDENCIES =
+tsan_unittest_LINK = $(CXXLD) $(tsan_unittest_CXXFLAGS) $(CXXFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+unit_bitmap_SOURCES = unit_bitmap.c
+unit_bitmap_OBJECTS = unit_bitmap-unit_bitmap.$(OBJEXT)
+unit_bitmap_DEPENDENCIES =
+unit_bitmap_LINK = $(CCLD) $(unit_bitmap_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+unit_vc_SOURCES = unit_vc.c
+unit_vc_OBJECTS = unit_vc-unit_vc.$(OBJEXT)
+unit_vc_DEPENDENCIES =
+unit_vc_LINK = $(CCLD) $(unit_vc_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+CXXCOMPILE = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS)
+CXXLD = $(CXX)
+CXXLINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+SOURCES = annotate_barrier.c annotate_hb_err.c annotate_hb_race.c \
+ annotate_ignore_rw.c annotate_ignore_write.c \
+ annotate_publish_hg.c annotate_rwlock.c \
+ $(annotate_smart_pointer_SOURCES) $(annotate_static_SOURCES) \
+ annotate_trace_memory.c atomic_var.c $(boost_thread_SOURCES) \
+ bug-235681.c circular_buffer.c custom_alloc.c fp_race.c \
+ free_is_write.c hold_lock.c linuxthreads_det.c matinv.c \
+ memory_allocation.c $(monitor_example_SOURCES) \
+ $(new_delete_SOURCES) omp_matinv.c omp_prime.c omp_printf.c \
+ pth_barrier.c pth_barrier_race.c pth_barrier_reinit.c \
+ pth_barrier_thr_cr.c pth_broadcast.c pth_cancel_locked.c \
+ pth_cleanup_handler.c pth_cond_race.c pth_create_chain.c \
+ pth_create_glibc_2_0.c pth_detached.c pth_detached3.c \
+ pth_detached_sem.c pth_inconsistent_cond_wait.c \
+ pth_mutex_reinit.c pth_process_shared_mutex.c pth_spinlock.c \
+ pth_uninitialized_cond.c recursive_mutex.c rwlock_race.c \
+ rwlock_test.c rwlock_type_checking.c sem_as_mutex.c sem_open.c \
+ sigalrm.c $(std_thread_SOURCES) thread_name.c threaded-fork.c \
+ trylock.c $(tsan_unittest_SOURCES) unit_bitmap.c unit_vc.c
+DIST_SOURCES = annotate_barrier.c annotate_hb_err.c annotate_hb_race.c \
+ annotate_ignore_rw.c annotate_ignore_write.c \
+ annotate_publish_hg.c annotate_rwlock.c \
+ $(am__annotate_smart_pointer_SOURCES_DIST) \
+ $(annotate_static_SOURCES) annotate_trace_memory.c \
+ atomic_var.c $(am__boost_thread_SOURCES_DIST) bug-235681.c \
+ circular_buffer.c custom_alloc.c fp_race.c free_is_write.c \
+ hold_lock.c linuxthreads_det.c matinv.c memory_allocation.c \
+ $(monitor_example_SOURCES) $(new_delete_SOURCES) omp_matinv.c \
+ omp_prime.c omp_printf.c pth_barrier.c pth_barrier_race.c \
+ pth_barrier_reinit.c pth_barrier_thr_cr.c pth_broadcast.c \
+ pth_cancel_locked.c pth_cleanup_handler.c pth_cond_race.c \
+ pth_create_chain.c pth_create_glibc_2_0.c pth_detached.c \
+ pth_detached3.c pth_detached_sem.c \
+ pth_inconsistent_cond_wait.c pth_mutex_reinit.c \
+ pth_process_shared_mutex.c pth_spinlock.c \
+ pth_uninitialized_cond.c recursive_mutex.c rwlock_race.c \
+ rwlock_test.c rwlock_type_checking.c sem_as_mutex.c sem_open.c \
+ sigalrm.c $(std_thread_SOURCES) thread_name.c threaded-fork.c \
+ trylock.c $(tsan_unittest_SOURCES) unit_bitmap.c unit_vc.c
+HEADERS = $(noinst_HEADERS)
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI) \
+ @FLAG_W_EXTRA@ -Wno-inline -Wno-unused-parameter
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI) \
+ @FLAG_W_EXTRA@ -Wno-inline -Wno-unused-parameter
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+ compare_error_count_with \
+ filter_annotate_barrier_xml \
+ filter_error_count \
+ filter_error_summary \
+ filter_stderr \
+ filter_stderr_and_thread_no \
+ filter_stderr_and_thread_no_and_offset \
+ filter_thread_no \
+ filter_xml_and_thread_no \
+ run_openmp_test \
+ supported_libpthread \
+ supported_sem_init
+
+noinst_HEADERS = \
+ tsan_thread_wrappers_pthread.h \
+ unified_annotations.h
+
+EXTRA_DIST = \
+ annotate_barrier.stderr.exp \
+ annotate_barrier.vgtest \
+ annotate_barrier_xml.stderr.exp \
+ annotate_barrier_xml.vgtest \
+ annotate_hb_err.stderr.exp \
+ annotate_hb_err.vgtest \
+ annotate_hb_race.stderr.exp \
+ annotate_hb_race.vgtest \
+ annotate_hbefore.stderr.exp \
+ annotate_hbefore.vgtest \
+ annotate_order_1.stderr.exp \
+ annotate_order_1.vgtest \
+ annotate_order_2.stderr.exp \
+ annotate_order_2.vgtest \
+ annotate_order_3.stderr.exp \
+ annotate_order_3.vgtest \
+ annotate_publish_hg.stderr.exp \
+ annotate_publish_hg.vgtest \
+ annotate_smart_pointer.stderr.exp \
+ annotate_smart_pointer.vgtest \
+ annotate_smart_pointer2.stderr.exp \
+ annotate_smart_pointer2.vgtest \
+ annotate_spinlock.stderr.exp \
+ annotate_spinlock.vgtest \
+ annotate_rwlock.stderr.exp \
+ annotate_rwlock.vgtest \
+ annotate_rwlock_hg.stderr.exp \
+ annotate_rwlock_hg.vgtest \
+ annotate_ignore_read.stderr.exp \
+ annotate_ignore_read.vgtest \
+ annotate_ignore_rw.stderr.exp \
+ annotate_ignore_rw.vgtest \
+ annotate_ignore_rw2.stderr.exp \
+ annotate_ignore_rw2.vgtest \
+ annotate_ignore_write.stderr.exp \
+ annotate_ignore_write.vgtest \
+ annotate_ignore_write2.stderr.exp \
+ annotate_ignore_write2.vgtest \
+ annotate_trace_memory.stderr.exp-32bit \
+ annotate_trace_memory.stderr.exp-64bit \
+ annotate_trace_memory.vgtest \
+ annotate_trace_memory_xml.stderr.exp-32bit \
+ annotate_trace_memory_xml.stderr.exp-64bit \
+ annotate_trace_memory_xml.vgtest \
+ annotate_static.stderr.exp \
+ annotate_static.vgtest \
+ atomic_var.stderr.exp \
+ atomic_var.vgtest \
+ bar_bad.stderr.exp \
+ bar_bad.vgtest \
+ bar_bad_xml.stderr.exp \
+ bar_bad_xml.vgtest \
+ bar_trivial.stderr.exp \
+ bar_trivial.stdout.exp \
+ bar_trivial.vgtest \
+ boost_thread.stderr.exp \
+ boost_thread.vgtest \
+ bug-235681.stderr.exp \
+ bug-235681.vgtest \
+ circular_buffer.stderr.exp \
+ circular_buffer.vgtest \
+ custom_alloc.stderr.exp \
+ custom_alloc.vgtest \
+ custom_alloc_fiw.stderr.exp \
+ custom_alloc_fiw.vgtest \
+ fp_race.stderr.exp \
+ fp_race.vgtest \
+ fp_race2.stderr.exp \
+ fp_race2.vgtest \
+ fp_race_xml.stderr.exp \
+ fp_race_xml.vgtest \
+ free_is_write.stderr.exp \
+ free_is_write.vgtest \
+ free_is_write2.stderr.exp \
+ free_is_write2.vgtest \
+ hg01_all_ok.stderr.exp \
+ hg01_all_ok.vgtest \
+ hg02_deadlock.stderr.exp \
+ hg02_deadlock.vgtest \
+ hg03_inherit.stderr.exp \
+ hg03_inherit.vgtest \
+ hg04_race.stderr.exp \
+ hg04_race.vgtest \
+ hg05_race2.stderr.exp \
+ hg05_race2.stderr.exp-powerpc \
+ hg05_race2.vgtest \
+ hg06_readshared.stderr.exp \
+ hg06_readshared.vgtest \
+ hold_lock_1.stderr.exp \
+ hold_lock_1.vgtest \
+ hold_lock_2.stderr.exp \
+ hold_lock_2.vgtest \
+ linuxthreads_det.stderr.exp \
+ linuxthreads_det.stderr.exp-linuxthreads \
+ linuxthreads_det.stdout.exp \
+ linuxthreads_det.stdout.exp-linuxthreads \
+ linuxthreads_det.vgtest \
+ matinv.stderr.exp \
+ matinv.stdout.exp \
+ matinv.vgtest \
+ memory_allocation.stderr.exp \
+ memory_allocation.vgtest \
+ monitor_example.stderr.exp \
+ monitor_example.vgtest \
+ new_delete.stderr.exp \
+ new_delete.vgtest \
+ omp_matinv.stderr.exp \
+ omp_matinv.stdout.exp \
+ omp_matinv.vgtest \
+ omp_matinv_racy.stderr.exp \
+ omp_matinv_racy.stdout.exp \
+ omp_matinv_racy.vgtest \
+ omp_prime_racy.stderr.exp \
+ omp_prime_racy.vgtest \
+ omp_printf.stderr.exp \
+ omp_printf.vgtest \
+ pth_barrier.stderr.exp \
+ pth_barrier.vgtest \
+ pth_barrier2.stderr.exp \
+ pth_barrier2.vgtest \
+ pth_barrier3.stderr.exp \
+ pth_barrier3.vgtest \
+ pth_barrier_race.stderr.exp \
+ pth_barrier_race.vgtest \
+ pth_barrier_reinit.stderr.exp \
+ pth_barrier_reinit.vgtest \
+ pth_barrier_thr_cr.stderr.exp \
+ pth_barrier_thr_cr.vgtest \
+ pth_barrier_thr_cr.supp \
+ pth_broadcast.stderr.exp \
+ pth_broadcast.vgtest \
+ pth_cancel_locked.stderr.exp \
+ pth_cancel_locked.stderr.exp-darwin \
+ pth_cancel_locked.vgtest \
+ pth_cleanup_handler.stderr.exp \
+ pth_cleanup_handler.vgtest \
+ pth_cond_race.stderr.exp \
+ pth_cond_race.vgtest \
+ pth_cond_race2.stderr.exp \
+ pth_cond_race2.vgtest \
+ pth_cond_race3.stderr.exp \
+ pth_cond_race3.vgtest \
+ pth_create_chain.stderr.exp \
+ pth_create_chain.vgtest \
+ pth_create_glibc_2_0.stderr.exp \
+ pth_create_glibc_2_0.vgtest \
+ pth_detached.stderr.exp \
+ pth_detached.stdout.exp \
+ pth_detached.vgtest \
+ pth_detached2.stderr.exp \
+ pth_detached2.stdout.exp \
+ pth_detached2.vgtest \
+ pth_detached3.stderr.exp1 \
+ pth_detached3.stderr.exp2 \
+ pth_detached3.vgtest \
+ pth_detached_sem.stderr.exp \
+ pth_detached_sem.stdout.exp \
+ pth_detached_sem.vgtest \
+ pth_inconsistent_cond_wait.stderr.exp1 \
+ pth_inconsistent_cond_wait.stderr.exp2 \
+ pth_inconsistent_cond_wait.vgtest \
+ pth_mutex_reinit.stderr.exp \
+ pth_mutex_reinit.vgtest \
+ pth_once.stderr.exp \
+ pth_once.vgtest \
+ pth_process_shared_mutex.stderr.exp \
+ pth_process_shared_mutex.vgtest \
+ pth_spinlock.stderr.exp \
+ pth_spinlock.vgtest \
+ pth_uninitialized_cond.stderr.exp \
+ pth_uninitialized_cond.vgtest \
+ read_and_free_race.stderr.exp \
+ read_and_free_race.vgtest \
+ recursive_mutex.stderr.exp-linux \
+ recursive_mutex.stderr.exp-darwin \
+ recursive_mutex.vgtest \
+ rwlock_race.stderr.exp \
+ rwlock_race.stderr.exp2 \
+ rwlock_race.vgtest \
+ rwlock_test.stderr.exp \
+ rwlock_test.vgtest \
+ rwlock_type_checking.stderr.exp \
+ rwlock_type_checking.vgtest \
+ sem_as_mutex.stderr.exp \
+ sem_as_mutex.vgtest \
+ sem_as_mutex2.stderr.exp \
+ sem_as_mutex2.vgtest \
+ sem_as_mutex3.stderr.exp \
+ sem_as_mutex3.vgtest \
+ sem_open.stderr.exp \
+ sem_open.vgtest \
+ sem_open2.stderr.exp \
+ sem_open2.vgtest \
+ sem_open3.stderr.exp \
+ sem_open3.vgtest \
+ sem_open_traced.stderr.exp \
+ sem_open_traced.vgtest \
+ sigalrm.stderr.exp \
+ sigalrm.vgtest \
+ sigaltstack.stderr.exp \
+ sigaltstack.vgtest \
+ std_thread.stderr.exp \
+ std_thread.vgtest \
+ tc01_simple_race.stderr.exp \
+ tc01_simple_race.vgtest \
+ tc02_simple_tls.stderr.exp \
+ tc02_simple_tls.vgtest \
+ tc03_re_excl.stderr.exp \
+ tc03_re_excl.vgtest \
+ tc04_free_lock.stderr.exp-x86 \
+ tc04_free_lock.stderr.exp-ppc \
+ tc04_free_lock.stderr.exp-s390 \
+ tc04_free_lock.vgtest \
+ tc05_simple_race.stderr.exp \
+ tc05_simple_race.vgtest \
+ tc06_two_races.stderr.exp \
+ tc06_two_races.vgtest \
+ tc07_hbl1.stderr.exp \
+ tc07_hbl1.stdout.exp \
+ tc07_hbl1.vgtest \
+ tc08_hbl2.stderr.exp \
+ tc08_hbl2.stdout.exp \
+ tc08_hbl2.vgtest \
+ tc09_bad_unlock.stderr.exp-x86 \
+ tc09_bad_unlock.stderr.exp-ppc \
+ tc09_bad_unlock.stderr.exp-glibc2.8 \
+ tc09_bad_unlock.stderr.exp-s390 \
+ tc09_bad_unlock.vgtest \
+ tc10_rec_lock.stderr.exp \
+ tc10_rec_lock.vgtest \
+ tc11_XCHG.stderr.exp tc11_XCHG.stdout.exp \
+ tc11_XCHG.vgtest \
+ tc12_rwl_trivial.stderr.exp \
+ tc12_rwl_trivial.vgtest \
+ tc13_laog1.stderr.exp \
+ tc13_laog1.vgtest \
+ tc15_laog_lockdel.stderr.exp \
+ tc15_laog_lockdel.vgtest \
+ tc16_byterace.stderr.exp \
+ tc16_byterace.vgtest \
+ tc17_sembar.stderr.exp \
+ tc17_sembar.vgtest \
+ tc18_semabuse.stderr.exp \
+ tc18_semabuse.vgtest \
+ tc19_shadowmem.stderr.exp-32bit \
+ tc19_shadowmem.stderr.exp-64bit \
+ tc19_shadowmem.vgtest \
+ tc21_pthonce.stderr.exp \
+ tc21_pthonce.stdout.exp \
+ tc21_pthonce.vgtest \
+ tc22_exit_w_lock.stderr.exp-32bit \
+ tc22_exit_w_lock.stderr.exp-64bit \
+ tc22_exit_w_lock.vgtest \
+ tc23_bogus_condwait.stderr.exp-linux-x86 \
+ tc23_bogus_condwait.stderr.exp-linux-ppc \
+ tc23_bogus_condwait.stderr.exp-darwin-x86 \
+ tc23_bogus_condwait.stderr.exp-darwin-amd64 \
+ tc23_bogus_condwait.vgtest \
+ tc24_nonzero_sem.stderr.exp \
+ tc24_nonzero_sem.vgtest \
+ thread_name.stderr.exp \
+ thread_name.vgtest \
+ thread_name_xml.stderr.exp \
+ thread_name_xml.vgtest \
+ threaded-fork.stderr.exp \
+ threaded-fork.vgtest \
+ trylock.stderr.exp \
+ trylock.vgtest \
+ unit_bitmap.stderr.exp \
+ unit_bitmap.vgtest \
+ unit_vc.stderr.exp \
+ unit_vc.vgtest
+
+LDADD = -lpthread
+monitor_example_SOURCES = monitor_example.cpp
+new_delete_SOURCES = new_delete.cpp
+pth_cleanup_handler_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_EMPTY_BODY@
+tsan_unittest_SOURCES = tsan_unittest.cpp
+tsan_unittest_CXXFLAGS = $(AM_CXXFLAGS) \
+ -DTHREAD_WRAPPERS='"tsan_thread_wrappers_pthread.h"'
+
+unit_bitmap_CFLAGS = $(AM_CFLAGS) -O2 \
+ -DENABLE_DRD_CONSISTENCY_CHECKS \
+ @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+
+unit_bitmap_LDADD = # nothing, i.e. not -lpthread
+unit_vc_CFLAGS = $(AM_CFLAGS) -DENABLE_DRD_CONSISTENCY_CHECKS
+unit_vc_LDADD = # nothing, i.e. not -lpthread
+@HAVE_BOOST_1_35_TRUE@boost_thread_SOURCES = boost_thread.cpp
+@HAVE_BOOST_1_35_TRUE@boost_thread_CXXFLAGS = $(AM_CXXFLAGS) $(BOOST_CFLAGS)
+@HAVE_BOOST_1_35_TRUE@boost_thread_LDADD = $(BOOST_LIBS)
+@HAVE_BUILTIN_ATOMIC_TRUE@annotate_smart_pointer_SOURCES = annotate_smart_pointer.cpp
+annotate_static_SOURCES = annotate_static.cpp
+@HAVE_OPENMP_TRUE@omp_matinv_CFLAGS = $(AM_CFLAGS) -fopenmp
+@HAVE_OPENMP_TRUE@omp_matinv_LDFLAGS = -fopenmp
+@HAVE_OPENMP_TRUE@omp_matinv_LDADD = $(LDADD) -lm
+@HAVE_OPENMP_TRUE@omp_prime_CFLAGS = $(AM_CFLAGS) -fopenmp
+@HAVE_OPENMP_TRUE@omp_prime_LDFLAGS = -fopenmp
+@HAVE_OPENMP_TRUE@omp_prime_LDADD = $(LDADD) -lm
+@HAVE_OPENMP_TRUE@omp_printf_CFLAGS = $(AM_CFLAGS) -fopenmp
+@HAVE_OPENMP_TRUE@omp_printf_LDFLAGS = -fopenmp
+@HAVE_OPENMP_TRUE@omp_printf_LDADD = $(LDADD) -lm
+@HAVE_PTHREAD_BARRIER_TRUE@matinv_LDADD = $(LDADD) -lm
+std_thread_SOURCES = std_thread.cpp
+std_thread_CXXFLAGS = $(AM_CXXFLAGS) -std=c++0x
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .cpp .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign drd/tests/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign drd/tests/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+annotate_barrier$(EXEEXT): $(annotate_barrier_OBJECTS) $(annotate_barrier_DEPENDENCIES)
+ @rm -f annotate_barrier$(EXEEXT)
+ $(LINK) $(annotate_barrier_OBJECTS) $(annotate_barrier_LDADD) $(LIBS)
+annotate_hb_err$(EXEEXT): $(annotate_hb_err_OBJECTS) $(annotate_hb_err_DEPENDENCIES)
+ @rm -f annotate_hb_err$(EXEEXT)
+ $(LINK) $(annotate_hb_err_OBJECTS) $(annotate_hb_err_LDADD) $(LIBS)
+annotate_hb_race$(EXEEXT): $(annotate_hb_race_OBJECTS) $(annotate_hb_race_DEPENDENCIES)
+ @rm -f annotate_hb_race$(EXEEXT)
+ $(LINK) $(annotate_hb_race_OBJECTS) $(annotate_hb_race_LDADD) $(LIBS)
+annotate_ignore_rw$(EXEEXT): $(annotate_ignore_rw_OBJECTS) $(annotate_ignore_rw_DEPENDENCIES)
+ @rm -f annotate_ignore_rw$(EXEEXT)
+ $(LINK) $(annotate_ignore_rw_OBJECTS) $(annotate_ignore_rw_LDADD) $(LIBS)
+annotate_ignore_write$(EXEEXT): $(annotate_ignore_write_OBJECTS) $(annotate_ignore_write_DEPENDENCIES)
+ @rm -f annotate_ignore_write$(EXEEXT)
+ $(LINK) $(annotate_ignore_write_OBJECTS) $(annotate_ignore_write_LDADD) $(LIBS)
+annotate_publish_hg$(EXEEXT): $(annotate_publish_hg_OBJECTS) $(annotate_publish_hg_DEPENDENCIES)
+ @rm -f annotate_publish_hg$(EXEEXT)
+ $(LINK) $(annotate_publish_hg_OBJECTS) $(annotate_publish_hg_LDADD) $(LIBS)
+annotate_rwlock$(EXEEXT): $(annotate_rwlock_OBJECTS) $(annotate_rwlock_DEPENDENCIES)
+ @rm -f annotate_rwlock$(EXEEXT)
+ $(LINK) $(annotate_rwlock_OBJECTS) $(annotate_rwlock_LDADD) $(LIBS)
+annotate_smart_pointer$(EXEEXT): $(annotate_smart_pointer_OBJECTS) $(annotate_smart_pointer_DEPENDENCIES)
+ @rm -f annotate_smart_pointer$(EXEEXT)
+ $(CXXLINK) $(annotate_smart_pointer_OBJECTS) $(annotate_smart_pointer_LDADD) $(LIBS)
+annotate_static$(EXEEXT): $(annotate_static_OBJECTS) $(annotate_static_DEPENDENCIES)
+ @rm -f annotate_static$(EXEEXT)
+ $(CXXLINK) $(annotate_static_OBJECTS) $(annotate_static_LDADD) $(LIBS)
+annotate_trace_memory$(EXEEXT): $(annotate_trace_memory_OBJECTS) $(annotate_trace_memory_DEPENDENCIES)
+ @rm -f annotate_trace_memory$(EXEEXT)
+ $(LINK) $(annotate_trace_memory_OBJECTS) $(annotate_trace_memory_LDADD) $(LIBS)
+atomic_var$(EXEEXT): $(atomic_var_OBJECTS) $(atomic_var_DEPENDENCIES)
+ @rm -f atomic_var$(EXEEXT)
+ $(LINK) $(atomic_var_OBJECTS) $(atomic_var_LDADD) $(LIBS)
+boost_thread$(EXEEXT): $(boost_thread_OBJECTS) $(boost_thread_DEPENDENCIES)
+ @rm -f boost_thread$(EXEEXT)
+ $(boost_thread_LINK) $(boost_thread_OBJECTS) $(boost_thread_LDADD) $(LIBS)
+bug-235681$(EXEEXT): $(bug_235681_OBJECTS) $(bug_235681_DEPENDENCIES)
+ @rm -f bug-235681$(EXEEXT)
+ $(LINK) $(bug_235681_OBJECTS) $(bug_235681_LDADD) $(LIBS)
+circular_buffer$(EXEEXT): $(circular_buffer_OBJECTS) $(circular_buffer_DEPENDENCIES)
+ @rm -f circular_buffer$(EXEEXT)
+ $(LINK) $(circular_buffer_OBJECTS) $(circular_buffer_LDADD) $(LIBS)
+custom_alloc$(EXEEXT): $(custom_alloc_OBJECTS) $(custom_alloc_DEPENDENCIES)
+ @rm -f custom_alloc$(EXEEXT)
+ $(LINK) $(custom_alloc_OBJECTS) $(custom_alloc_LDADD) $(LIBS)
+fp_race$(EXEEXT): $(fp_race_OBJECTS) $(fp_race_DEPENDENCIES)
+ @rm -f fp_race$(EXEEXT)
+ $(LINK) $(fp_race_OBJECTS) $(fp_race_LDADD) $(LIBS)
+free_is_write$(EXEEXT): $(free_is_write_OBJECTS) $(free_is_write_DEPENDENCIES)
+ @rm -f free_is_write$(EXEEXT)
+ $(LINK) $(free_is_write_OBJECTS) $(free_is_write_LDADD) $(LIBS)
+hold_lock$(EXEEXT): $(hold_lock_OBJECTS) $(hold_lock_DEPENDENCIES)
+ @rm -f hold_lock$(EXEEXT)
+ $(LINK) $(hold_lock_OBJECTS) $(hold_lock_LDADD) $(LIBS)
+linuxthreads_det$(EXEEXT): $(linuxthreads_det_OBJECTS) $(linuxthreads_det_DEPENDENCIES)
+ @rm -f linuxthreads_det$(EXEEXT)
+ $(LINK) $(linuxthreads_det_OBJECTS) $(linuxthreads_det_LDADD) $(LIBS)
+matinv$(EXEEXT): $(matinv_OBJECTS) $(matinv_DEPENDENCIES)
+ @rm -f matinv$(EXEEXT)
+ $(LINK) $(matinv_OBJECTS) $(matinv_LDADD) $(LIBS)
+memory_allocation$(EXEEXT): $(memory_allocation_OBJECTS) $(memory_allocation_DEPENDENCIES)
+ @rm -f memory_allocation$(EXEEXT)
+ $(LINK) $(memory_allocation_OBJECTS) $(memory_allocation_LDADD) $(LIBS)
+monitor_example$(EXEEXT): $(monitor_example_OBJECTS) $(monitor_example_DEPENDENCIES)
+ @rm -f monitor_example$(EXEEXT)
+ $(CXXLINK) $(monitor_example_OBJECTS) $(monitor_example_LDADD) $(LIBS)
+new_delete$(EXEEXT): $(new_delete_OBJECTS) $(new_delete_DEPENDENCIES)
+ @rm -f new_delete$(EXEEXT)
+ $(CXXLINK) $(new_delete_OBJECTS) $(new_delete_LDADD) $(LIBS)
+omp_matinv$(EXEEXT): $(omp_matinv_OBJECTS) $(omp_matinv_DEPENDENCIES)
+ @rm -f omp_matinv$(EXEEXT)
+ $(omp_matinv_LINK) $(omp_matinv_OBJECTS) $(omp_matinv_LDADD) $(LIBS)
+omp_prime$(EXEEXT): $(omp_prime_OBJECTS) $(omp_prime_DEPENDENCIES)
+ @rm -f omp_prime$(EXEEXT)
+ $(omp_prime_LINK) $(omp_prime_OBJECTS) $(omp_prime_LDADD) $(LIBS)
+omp_printf$(EXEEXT): $(omp_printf_OBJECTS) $(omp_printf_DEPENDENCIES)
+ @rm -f omp_printf$(EXEEXT)
+ $(omp_printf_LINK) $(omp_printf_OBJECTS) $(omp_printf_LDADD) $(LIBS)
+pth_barrier$(EXEEXT): $(pth_barrier_OBJECTS) $(pth_barrier_DEPENDENCIES)
+ @rm -f pth_barrier$(EXEEXT)
+ $(LINK) $(pth_barrier_OBJECTS) $(pth_barrier_LDADD) $(LIBS)
+pth_barrier_race$(EXEEXT): $(pth_barrier_race_OBJECTS) $(pth_barrier_race_DEPENDENCIES)
+ @rm -f pth_barrier_race$(EXEEXT)
+ $(LINK) $(pth_barrier_race_OBJECTS) $(pth_barrier_race_LDADD) $(LIBS)
+pth_barrier_reinit$(EXEEXT): $(pth_barrier_reinit_OBJECTS) $(pth_barrier_reinit_DEPENDENCIES)
+ @rm -f pth_barrier_reinit$(EXEEXT)
+ $(LINK) $(pth_barrier_reinit_OBJECTS) $(pth_barrier_reinit_LDADD) $(LIBS)
+pth_barrier_thr_cr$(EXEEXT): $(pth_barrier_thr_cr_OBJECTS) $(pth_barrier_thr_cr_DEPENDENCIES)
+ @rm -f pth_barrier_thr_cr$(EXEEXT)
+ $(LINK) $(pth_barrier_thr_cr_OBJECTS) $(pth_barrier_thr_cr_LDADD) $(LIBS)
+pth_broadcast$(EXEEXT): $(pth_broadcast_OBJECTS) $(pth_broadcast_DEPENDENCIES)
+ @rm -f pth_broadcast$(EXEEXT)
+ $(LINK) $(pth_broadcast_OBJECTS) $(pth_broadcast_LDADD) $(LIBS)
+pth_cancel_locked$(EXEEXT): $(pth_cancel_locked_OBJECTS) $(pth_cancel_locked_DEPENDENCIES)
+ @rm -f pth_cancel_locked$(EXEEXT)
+ $(LINK) $(pth_cancel_locked_OBJECTS) $(pth_cancel_locked_LDADD) $(LIBS)
+pth_cleanup_handler$(EXEEXT): $(pth_cleanup_handler_OBJECTS) $(pth_cleanup_handler_DEPENDENCIES)
+ @rm -f pth_cleanup_handler$(EXEEXT)
+ $(pth_cleanup_handler_LINK) $(pth_cleanup_handler_OBJECTS) $(pth_cleanup_handler_LDADD) $(LIBS)
+pth_cond_race$(EXEEXT): $(pth_cond_race_OBJECTS) $(pth_cond_race_DEPENDENCIES)
+ @rm -f pth_cond_race$(EXEEXT)
+ $(LINK) $(pth_cond_race_OBJECTS) $(pth_cond_race_LDADD) $(LIBS)
+pth_create_chain$(EXEEXT): $(pth_create_chain_OBJECTS) $(pth_create_chain_DEPENDENCIES)
+ @rm -f pth_create_chain$(EXEEXT)
+ $(LINK) $(pth_create_chain_OBJECTS) $(pth_create_chain_LDADD) $(LIBS)
+pth_create_glibc_2_0$(EXEEXT): $(pth_create_glibc_2_0_OBJECTS) $(pth_create_glibc_2_0_DEPENDENCIES)
+ @rm -f pth_create_glibc_2_0$(EXEEXT)
+ $(LINK) $(pth_create_glibc_2_0_OBJECTS) $(pth_create_glibc_2_0_LDADD) $(LIBS)
+pth_detached$(EXEEXT): $(pth_detached_OBJECTS) $(pth_detached_DEPENDENCIES)
+ @rm -f pth_detached$(EXEEXT)
+ $(LINK) $(pth_detached_OBJECTS) $(pth_detached_LDADD) $(LIBS)
+pth_detached3$(EXEEXT): $(pth_detached3_OBJECTS) $(pth_detached3_DEPENDENCIES)
+ @rm -f pth_detached3$(EXEEXT)
+ $(LINK) $(pth_detached3_OBJECTS) $(pth_detached3_LDADD) $(LIBS)
+pth_detached_sem$(EXEEXT): $(pth_detached_sem_OBJECTS) $(pth_detached_sem_DEPENDENCIES)
+ @rm -f pth_detached_sem$(EXEEXT)
+ $(LINK) $(pth_detached_sem_OBJECTS) $(pth_detached_sem_LDADD) $(LIBS)
+pth_inconsistent_cond_wait$(EXEEXT): $(pth_inconsistent_cond_wait_OBJECTS) $(pth_inconsistent_cond_wait_DEPENDENCIES)
+ @rm -f pth_inconsistent_cond_wait$(EXEEXT)
+ $(LINK) $(pth_inconsistent_cond_wait_OBJECTS) $(pth_inconsistent_cond_wait_LDADD) $(LIBS)
+pth_mutex_reinit$(EXEEXT): $(pth_mutex_reinit_OBJECTS) $(pth_mutex_reinit_DEPENDENCIES)
+ @rm -f pth_mutex_reinit$(EXEEXT)
+ $(LINK) $(pth_mutex_reinit_OBJECTS) $(pth_mutex_reinit_LDADD) $(LIBS)
+pth_process_shared_mutex$(EXEEXT): $(pth_process_shared_mutex_OBJECTS) $(pth_process_shared_mutex_DEPENDENCIES)
+ @rm -f pth_process_shared_mutex$(EXEEXT)
+ $(LINK) $(pth_process_shared_mutex_OBJECTS) $(pth_process_shared_mutex_LDADD) $(LIBS)
+pth_spinlock$(EXEEXT): $(pth_spinlock_OBJECTS) $(pth_spinlock_DEPENDENCIES)
+ @rm -f pth_spinlock$(EXEEXT)
+ $(LINK) $(pth_spinlock_OBJECTS) $(pth_spinlock_LDADD) $(LIBS)
+pth_uninitialized_cond$(EXEEXT): $(pth_uninitialized_cond_OBJECTS) $(pth_uninitialized_cond_DEPENDENCIES)
+ @rm -f pth_uninitialized_cond$(EXEEXT)
+ $(LINK) $(pth_uninitialized_cond_OBJECTS) $(pth_uninitialized_cond_LDADD) $(LIBS)
+recursive_mutex$(EXEEXT): $(recursive_mutex_OBJECTS) $(recursive_mutex_DEPENDENCIES)
+ @rm -f recursive_mutex$(EXEEXT)
+ $(LINK) $(recursive_mutex_OBJECTS) $(recursive_mutex_LDADD) $(LIBS)
+rwlock_race$(EXEEXT): $(rwlock_race_OBJECTS) $(rwlock_race_DEPENDENCIES)
+ @rm -f rwlock_race$(EXEEXT)
+ $(LINK) $(rwlock_race_OBJECTS) $(rwlock_race_LDADD) $(LIBS)
+rwlock_test$(EXEEXT): $(rwlock_test_OBJECTS) $(rwlock_test_DEPENDENCIES)
+ @rm -f rwlock_test$(EXEEXT)
+ $(LINK) $(rwlock_test_OBJECTS) $(rwlock_test_LDADD) $(LIBS)
+rwlock_type_checking$(EXEEXT): $(rwlock_type_checking_OBJECTS) $(rwlock_type_checking_DEPENDENCIES)
+ @rm -f rwlock_type_checking$(EXEEXT)
+ $(LINK) $(rwlock_type_checking_OBJECTS) $(rwlock_type_checking_LDADD) $(LIBS)
+sem_as_mutex$(EXEEXT): $(sem_as_mutex_OBJECTS) $(sem_as_mutex_DEPENDENCIES)
+ @rm -f sem_as_mutex$(EXEEXT)
+ $(LINK) $(sem_as_mutex_OBJECTS) $(sem_as_mutex_LDADD) $(LIBS)
+sem_open$(EXEEXT): $(sem_open_OBJECTS) $(sem_open_DEPENDENCIES)
+ @rm -f sem_open$(EXEEXT)
+ $(LINK) $(sem_open_OBJECTS) $(sem_open_LDADD) $(LIBS)
+sigalrm$(EXEEXT): $(sigalrm_OBJECTS) $(sigalrm_DEPENDENCIES)
+ @rm -f sigalrm$(EXEEXT)
+ $(LINK) $(sigalrm_OBJECTS) $(sigalrm_LDADD) $(LIBS)
+std_thread$(EXEEXT): $(std_thread_OBJECTS) $(std_thread_DEPENDENCIES)
+ @rm -f std_thread$(EXEEXT)
+ $(std_thread_LINK) $(std_thread_OBJECTS) $(std_thread_LDADD) $(LIBS)
+thread_name$(EXEEXT): $(thread_name_OBJECTS) $(thread_name_DEPENDENCIES)
+ @rm -f thread_name$(EXEEXT)
+ $(LINK) $(thread_name_OBJECTS) $(thread_name_LDADD) $(LIBS)
+threaded-fork$(EXEEXT): $(threaded_fork_OBJECTS) $(threaded_fork_DEPENDENCIES)
+ @rm -f threaded-fork$(EXEEXT)
+ $(LINK) $(threaded_fork_OBJECTS) $(threaded_fork_LDADD) $(LIBS)
+trylock$(EXEEXT): $(trylock_OBJECTS) $(trylock_DEPENDENCIES)
+ @rm -f trylock$(EXEEXT)
+ $(LINK) $(trylock_OBJECTS) $(trylock_LDADD) $(LIBS)
+tsan_unittest$(EXEEXT): $(tsan_unittest_OBJECTS) $(tsan_unittest_DEPENDENCIES)
+ @rm -f tsan_unittest$(EXEEXT)
+ $(tsan_unittest_LINK) $(tsan_unittest_OBJECTS) $(tsan_unittest_LDADD) $(LIBS)
+unit_bitmap$(EXEEXT): $(unit_bitmap_OBJECTS) $(unit_bitmap_DEPENDENCIES)
+ @rm -f unit_bitmap$(EXEEXT)
+ $(unit_bitmap_LINK) $(unit_bitmap_OBJECTS) $(unit_bitmap_LDADD) $(LIBS)
+unit_vc$(EXEEXT): $(unit_vc_OBJECTS) $(unit_vc_DEPENDENCIES)
+ @rm -f unit_vc$(EXEEXT)
+ $(unit_vc_LINK) $(unit_vc_OBJECTS) $(unit_vc_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_barrier.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_hb_err.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_hb_race.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_ignore_rw.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_ignore_write.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_publish_hg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_rwlock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_smart_pointer.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_static.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_trace_memory.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/atomic_var.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/boost_thread-boost_thread.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug-235681.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/circular_buffer.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/custom_alloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fp_race.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/free_is_write.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hold_lock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/linuxthreads_det.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/matinv.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memory_allocation.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/monitor_example.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/new_delete.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/omp_matinv-omp_matinv.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/omp_prime-omp_prime.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/omp_printf-omp_printf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_barrier.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_barrier_race.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_barrier_reinit.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_barrier_thr_cr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_broadcast.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_cancel_locked.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_cleanup_handler-pth_cleanup_handler.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_cond_race.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_create_chain.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_create_glibc_2_0.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_detached.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_detached3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_detached_sem.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_inconsistent_cond_wait.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_mutex_reinit.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_process_shared_mutex.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_spinlock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_uninitialized_cond.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/recursive_mutex.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rwlock_race.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rwlock_test.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rwlock_type_checking.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sem_as_mutex.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sem_open.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigalrm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/std_thread-std_thread.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/thread_name.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/threaded-fork.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/trylock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tsan_unittest-tsan_unittest.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/unit_bitmap-unit_bitmap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/unit_vc-unit_vc.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+omp_matinv-omp_matinv.o: omp_matinv.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_matinv_CFLAGS) $(CFLAGS) -MT omp_matinv-omp_matinv.o -MD -MP -MF $(DEPDIR)/omp_matinv-omp_matinv.Tpo -c -o omp_matinv-omp_matinv.o `test -f 'omp_matinv.c' || echo '$(srcdir)/'`omp_matinv.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/omp_matinv-omp_matinv.Tpo $(DEPDIR)/omp_matinv-omp_matinv.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='omp_matinv.c' object='omp_matinv-omp_matinv.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_matinv_CFLAGS) $(CFLAGS) -c -o omp_matinv-omp_matinv.o `test -f 'omp_matinv.c' || echo '$(srcdir)/'`omp_matinv.c
+
+omp_matinv-omp_matinv.obj: omp_matinv.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_matinv_CFLAGS) $(CFLAGS) -MT omp_matinv-omp_matinv.obj -MD -MP -MF $(DEPDIR)/omp_matinv-omp_matinv.Tpo -c -o omp_matinv-omp_matinv.obj `if test -f 'omp_matinv.c'; then $(CYGPATH_W) 'omp_matinv.c'; else $(CYGPATH_W) '$(srcdir)/omp_matinv.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/omp_matinv-omp_matinv.Tpo $(DEPDIR)/omp_matinv-omp_matinv.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='omp_matinv.c' object='omp_matinv-omp_matinv.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_matinv_CFLAGS) $(CFLAGS) -c -o omp_matinv-omp_matinv.obj `if test -f 'omp_matinv.c'; then $(CYGPATH_W) 'omp_matinv.c'; else $(CYGPATH_W) '$(srcdir)/omp_matinv.c'; fi`
+
+omp_prime-omp_prime.o: omp_prime.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_prime_CFLAGS) $(CFLAGS) -MT omp_prime-omp_prime.o -MD -MP -MF $(DEPDIR)/omp_prime-omp_prime.Tpo -c -o omp_prime-omp_prime.o `test -f 'omp_prime.c' || echo '$(srcdir)/'`omp_prime.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/omp_prime-omp_prime.Tpo $(DEPDIR)/omp_prime-omp_prime.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='omp_prime.c' object='omp_prime-omp_prime.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_prime_CFLAGS) $(CFLAGS) -c -o omp_prime-omp_prime.o `test -f 'omp_prime.c' || echo '$(srcdir)/'`omp_prime.c
+
+omp_prime-omp_prime.obj: omp_prime.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_prime_CFLAGS) $(CFLAGS) -MT omp_prime-omp_prime.obj -MD -MP -MF $(DEPDIR)/omp_prime-omp_prime.Tpo -c -o omp_prime-omp_prime.obj `if test -f 'omp_prime.c'; then $(CYGPATH_W) 'omp_prime.c'; else $(CYGPATH_W) '$(srcdir)/omp_prime.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/omp_prime-omp_prime.Tpo $(DEPDIR)/omp_prime-omp_prime.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='omp_prime.c' object='omp_prime-omp_prime.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_prime_CFLAGS) $(CFLAGS) -c -o omp_prime-omp_prime.obj `if test -f 'omp_prime.c'; then $(CYGPATH_W) 'omp_prime.c'; else $(CYGPATH_W) '$(srcdir)/omp_prime.c'; fi`
+
+omp_printf-omp_printf.o: omp_printf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_printf_CFLAGS) $(CFLAGS) -MT omp_printf-omp_printf.o -MD -MP -MF $(DEPDIR)/omp_printf-omp_printf.Tpo -c -o omp_printf-omp_printf.o `test -f 'omp_printf.c' || echo '$(srcdir)/'`omp_printf.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/omp_printf-omp_printf.Tpo $(DEPDIR)/omp_printf-omp_printf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='omp_printf.c' object='omp_printf-omp_printf.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_printf_CFLAGS) $(CFLAGS) -c -o omp_printf-omp_printf.o `test -f 'omp_printf.c' || echo '$(srcdir)/'`omp_printf.c
+
+omp_printf-omp_printf.obj: omp_printf.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_printf_CFLAGS) $(CFLAGS) -MT omp_printf-omp_printf.obj -MD -MP -MF $(DEPDIR)/omp_printf-omp_printf.Tpo -c -o omp_printf-omp_printf.obj `if test -f 'omp_printf.c'; then $(CYGPATH_W) 'omp_printf.c'; else $(CYGPATH_W) '$(srcdir)/omp_printf.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/omp_printf-omp_printf.Tpo $(DEPDIR)/omp_printf-omp_printf.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='omp_printf.c' object='omp_printf-omp_printf.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(omp_printf_CFLAGS) $(CFLAGS) -c -o omp_printf-omp_printf.obj `if test -f 'omp_printf.c'; then $(CYGPATH_W) 'omp_printf.c'; else $(CYGPATH_W) '$(srcdir)/omp_printf.c'; fi`
+
+pth_cleanup_handler-pth_cleanup_handler.o: pth_cleanup_handler.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pth_cleanup_handler_CFLAGS) $(CFLAGS) -MT pth_cleanup_handler-pth_cleanup_handler.o -MD -MP -MF $(DEPDIR)/pth_cleanup_handler-pth_cleanup_handler.Tpo -c -o pth_cleanup_handler-pth_cleanup_handler.o `test -f 'pth_cleanup_handler.c' || echo '$(srcdir)/'`pth_cleanup_handler.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/pth_cleanup_handler-pth_cleanup_handler.Tpo $(DEPDIR)/pth_cleanup_handler-pth_cleanup_handler.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pth_cleanup_handler.c' object='pth_cleanup_handler-pth_cleanup_handler.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pth_cleanup_handler_CFLAGS) $(CFLAGS) -c -o pth_cleanup_handler-pth_cleanup_handler.o `test -f 'pth_cleanup_handler.c' || echo '$(srcdir)/'`pth_cleanup_handler.c
+
+pth_cleanup_handler-pth_cleanup_handler.obj: pth_cleanup_handler.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pth_cleanup_handler_CFLAGS) $(CFLAGS) -MT pth_cleanup_handler-pth_cleanup_handler.obj -MD -MP -MF $(DEPDIR)/pth_cleanup_handler-pth_cleanup_handler.Tpo -c -o pth_cleanup_handler-pth_cleanup_handler.obj `if test -f 'pth_cleanup_handler.c'; then $(CYGPATH_W) 'pth_cleanup_handler.c'; else $(CYGPATH_W) '$(srcdir)/pth_cleanup_handler.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/pth_cleanup_handler-pth_cleanup_handler.Tpo $(DEPDIR)/pth_cleanup_handler-pth_cleanup_handler.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pth_cleanup_handler.c' object='pth_cleanup_handler-pth_cleanup_handler.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pth_cleanup_handler_CFLAGS) $(CFLAGS) -c -o pth_cleanup_handler-pth_cleanup_handler.obj `if test -f 'pth_cleanup_handler.c'; then $(CYGPATH_W) 'pth_cleanup_handler.c'; else $(CYGPATH_W) '$(srcdir)/pth_cleanup_handler.c'; fi`
+
+unit_bitmap-unit_bitmap.o: unit_bitmap.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(unit_bitmap_CFLAGS) $(CFLAGS) -MT unit_bitmap-unit_bitmap.o -MD -MP -MF $(DEPDIR)/unit_bitmap-unit_bitmap.Tpo -c -o unit_bitmap-unit_bitmap.o `test -f 'unit_bitmap.c' || echo '$(srcdir)/'`unit_bitmap.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/unit_bitmap-unit_bitmap.Tpo $(DEPDIR)/unit_bitmap-unit_bitmap.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='unit_bitmap.c' object='unit_bitmap-unit_bitmap.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(unit_bitmap_CFLAGS) $(CFLAGS) -c -o unit_bitmap-unit_bitmap.o `test -f 'unit_bitmap.c' || echo '$(srcdir)/'`unit_bitmap.c
+
+unit_bitmap-unit_bitmap.obj: unit_bitmap.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(unit_bitmap_CFLAGS) $(CFLAGS) -MT unit_bitmap-unit_bitmap.obj -MD -MP -MF $(DEPDIR)/unit_bitmap-unit_bitmap.Tpo -c -o unit_bitmap-unit_bitmap.obj `if test -f 'unit_bitmap.c'; then $(CYGPATH_W) 'unit_bitmap.c'; else $(CYGPATH_W) '$(srcdir)/unit_bitmap.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/unit_bitmap-unit_bitmap.Tpo $(DEPDIR)/unit_bitmap-unit_bitmap.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='unit_bitmap.c' object='unit_bitmap-unit_bitmap.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(unit_bitmap_CFLAGS) $(CFLAGS) -c -o unit_bitmap-unit_bitmap.obj `if test -f 'unit_bitmap.c'; then $(CYGPATH_W) 'unit_bitmap.c'; else $(CYGPATH_W) '$(srcdir)/unit_bitmap.c'; fi`
+
+unit_vc-unit_vc.o: unit_vc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(unit_vc_CFLAGS) $(CFLAGS) -MT unit_vc-unit_vc.o -MD -MP -MF $(DEPDIR)/unit_vc-unit_vc.Tpo -c -o unit_vc-unit_vc.o `test -f 'unit_vc.c' || echo '$(srcdir)/'`unit_vc.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/unit_vc-unit_vc.Tpo $(DEPDIR)/unit_vc-unit_vc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='unit_vc.c' object='unit_vc-unit_vc.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(unit_vc_CFLAGS) $(CFLAGS) -c -o unit_vc-unit_vc.o `test -f 'unit_vc.c' || echo '$(srcdir)/'`unit_vc.c
+
+unit_vc-unit_vc.obj: unit_vc.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(unit_vc_CFLAGS) $(CFLAGS) -MT unit_vc-unit_vc.obj -MD -MP -MF $(DEPDIR)/unit_vc-unit_vc.Tpo -c -o unit_vc-unit_vc.obj `if test -f 'unit_vc.c'; then $(CYGPATH_W) 'unit_vc.c'; else $(CYGPATH_W) '$(srcdir)/unit_vc.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/unit_vc-unit_vc.Tpo $(DEPDIR)/unit_vc-unit_vc.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='unit_vc.c' object='unit_vc-unit_vc.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(unit_vc_CFLAGS) $(CFLAGS) -c -o unit_vc-unit_vc.obj `if test -f 'unit_vc.c'; then $(CYGPATH_W) 'unit_vc.c'; else $(CYGPATH_W) '$(srcdir)/unit_vc.c'; fi`
+
+.cpp.o:
+@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ $<
+
+.cpp.obj:
+@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+boost_thread-boost_thread.o: boost_thread.cpp
+@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(boost_thread_CXXFLAGS) $(CXXFLAGS) -MT boost_thread-boost_thread.o -MD -MP -MF $(DEPDIR)/boost_thread-boost_thread.Tpo -c -o boost_thread-boost_thread.o `test -f 'boost_thread.cpp' || echo '$(srcdir)/'`boost_thread.cpp
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/boost_thread-boost_thread.Tpo $(DEPDIR)/boost_thread-boost_thread.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='boost_thread.cpp' object='boost_thread-boost_thread.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(boost_thread_CXXFLAGS) $(CXXFLAGS) -c -o boost_thread-boost_thread.o `test -f 'boost_thread.cpp' || echo '$(srcdir)/'`boost_thread.cpp
+
+boost_thread-boost_thread.obj: boost_thread.cpp
+@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(boost_thread_CXXFLAGS) $(CXXFLAGS) -MT boost_thread-boost_thread.obj -MD -MP -MF $(DEPDIR)/boost_thread-boost_thread.Tpo -c -o boost_thread-boost_thread.obj `if test -f 'boost_thread.cpp'; then $(CYGPATH_W) 'boost_thread.cpp'; else $(CYGPATH_W) '$(srcdir)/boost_thread.cpp'; fi`
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/boost_thread-boost_thread.Tpo $(DEPDIR)/boost_thread-boost_thread.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='boost_thread.cpp' object='boost_thread-boost_thread.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(boost_thread_CXXFLAGS) $(CXXFLAGS) -c -o boost_thread-boost_thread.obj `if test -f 'boost_thread.cpp'; then $(CYGPATH_W) 'boost_thread.cpp'; else $(CYGPATH_W) '$(srcdir)/boost_thread.cpp'; fi`
+
+std_thread-std_thread.o: std_thread.cpp
+@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(std_thread_CXXFLAGS) $(CXXFLAGS) -MT std_thread-std_thread.o -MD -MP -MF $(DEPDIR)/std_thread-std_thread.Tpo -c -o std_thread-std_thread.o `test -f 'std_thread.cpp' || echo '$(srcdir)/'`std_thread.cpp
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/std_thread-std_thread.Tpo $(DEPDIR)/std_thread-std_thread.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='std_thread.cpp' object='std_thread-std_thread.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(std_thread_CXXFLAGS) $(CXXFLAGS) -c -o std_thread-std_thread.o `test -f 'std_thread.cpp' || echo '$(srcdir)/'`std_thread.cpp
+
+std_thread-std_thread.obj: std_thread.cpp
+@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(std_thread_CXXFLAGS) $(CXXFLAGS) -MT std_thread-std_thread.obj -MD -MP -MF $(DEPDIR)/std_thread-std_thread.Tpo -c -o std_thread-std_thread.obj `if test -f 'std_thread.cpp'; then $(CYGPATH_W) 'std_thread.cpp'; else $(CYGPATH_W) '$(srcdir)/std_thread.cpp'; fi`
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/std_thread-std_thread.Tpo $(DEPDIR)/std_thread-std_thread.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='std_thread.cpp' object='std_thread-std_thread.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(std_thread_CXXFLAGS) $(CXXFLAGS) -c -o std_thread-std_thread.obj `if test -f 'std_thread.cpp'; then $(CYGPATH_W) 'std_thread.cpp'; else $(CYGPATH_W) '$(srcdir)/std_thread.cpp'; fi`
+
+tsan_unittest-tsan_unittest.o: tsan_unittest.cpp
+@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tsan_unittest_CXXFLAGS) $(CXXFLAGS) -MT tsan_unittest-tsan_unittest.o -MD -MP -MF $(DEPDIR)/tsan_unittest-tsan_unittest.Tpo -c -o tsan_unittest-tsan_unittest.o `test -f 'tsan_unittest.cpp' || echo '$(srcdir)/'`tsan_unittest.cpp
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/tsan_unittest-tsan_unittest.Tpo $(DEPDIR)/tsan_unittest-tsan_unittest.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='tsan_unittest.cpp' object='tsan_unittest-tsan_unittest.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tsan_unittest_CXXFLAGS) $(CXXFLAGS) -c -o tsan_unittest-tsan_unittest.o `test -f 'tsan_unittest.cpp' || echo '$(srcdir)/'`tsan_unittest.cpp
+
+tsan_unittest-tsan_unittest.obj: tsan_unittest.cpp
+@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tsan_unittest_CXXFLAGS) $(CXXFLAGS) -MT tsan_unittest-tsan_unittest.obj -MD -MP -MF $(DEPDIR)/tsan_unittest-tsan_unittest.Tpo -c -o tsan_unittest-tsan_unittest.obj `if test -f 'tsan_unittest.cpp'; then $(CYGPATH_W) 'tsan_unittest.cpp'; else $(CYGPATH_W) '$(srcdir)/tsan_unittest.cpp'; fi`
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/tsan_unittest-tsan_unittest.Tpo $(DEPDIR)/tsan_unittest-tsan_unittest.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='tsan_unittest.cpp' object='tsan_unittest-tsan_unittest.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tsan_unittest_CXXFLAGS) $(CXXFLAGS) -c -o tsan_unittest-tsan_unittest.obj `if test -f 'tsan_unittest.cpp'; then $(CYGPATH_W) 'tsan_unittest.cpp'; else $(CYGPATH_W) '$(srcdir)/tsan_unittest.cpp'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS) $(HEADERS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/drd/tests/annotate_barrier_xml.stderr.exp b/main/drd/tests/annotate_barrier_xml.stderr.exp
new file mode 100644
index 0000000..52e4950
--- /dev/null
+++ b/main/drd/tests/annotate_barrier_xml.stderr.exp
@@ -0,0 +1,332 @@
+<?xml version="1.0"?>
+
+<valgrindoutput>
+
+<protocolversion>4</protocolversion>
+<protocoltool>drd</protocoltool>
+
+<preamble>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+</preamble>
+
+<pid>...</pid>
+<ppid>...</ppid>
+<tool>drd</tool>
+
+<args>
+ <vargv>...</vargv>
+ <argv>
+ <exe>./annotate_barrier</exe>
+ <arg>2</arg>
+ <arg>1</arg>
+ <arg>1</arg>
+ </argv>
+</args>
+
+<status>
+ <state>RUNNING</state>
+ <time>...</time>
+</status>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>UnimpDrdClReq</kind>
+ <what>The annotation macro ANNOTATE_BARRIER_INIT has not yet been implemented in <valgrind/drd.h></what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>barrier_init</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>barriers_and_races</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>UnimpDrdClReq</kind>
+ <what>The annotation macro ANNOTATE_BARRIER_WAIT_BEFORE has not yet been implemented in <valgrind/drd.h></what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>barrier_wait</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>threadfunc</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>UnimpDrdClReq</kind>
+ <what>The annotation macro ANNOTATE_BARRIER_WAIT_AFTER has not yet been implemented in <valgrind/drd.h></what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>barrier_wait</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>threadfunc</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>UnimpDrdClReq</kind>
+ <what>The annotation macro ANNOTATE_BARRIER_WAIT_BEFORE has not yet been implemented in <valgrind/drd.h></what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>barrier_wait</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>threadfunc</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>ConflictingAccess</kind>
+ <what>Conflicting store by thread 2 at 0x........ size 4</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>threadfunc</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>start_thread</fn>
+ </frame>
+ </stack>
+ <auxwhat>Address 0x........ is at offset 0 from 0x.........</auxwhat>
+ <allocation_context>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>malloc</fn>
+ <dir>...</dir>
+ <file>vg_replace_malloc.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>barriers_and_races</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </allocation_context>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>UnimpDrdClReq</kind>
+ <what>The annotation macro ANNOTATE_BARRIER_WAIT_AFTER has not yet been implemented in <valgrind/drd.h></what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>barrier_wait</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>threadfunc</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>UnimpDrdClReq</kind>
+ <what>The annotation macro ANNOTATE_BARRIER_DESTROY has not yet been implemented in <valgrind/drd.h></what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>barrier_destroy</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>barriers_and_races</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_barrier.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+Done.
+
+<status>
+ <state>FINISHED</state>
+ <time>...</time>
+</status>
+
+<errorcounts>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+</errorcounts>
+
+<suppcounts>...</suppcounts>
+
+</valgrindoutput>
+
diff --git a/main/drd/tests/annotate_barrier_xml.vgtest b/main/drd/tests/annotate_barrier_xml.vgtest
new file mode 100644
index 0000000..1cab159
--- /dev/null
+++ b/main/drd/tests/annotate_barrier_xml.vgtest
@@ -0,0 +1,4 @@
+prereq: test -e annotate_barrier && ./supported_libpthread
+vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no --num-callers=3 --xml=yes --xml-fd=2
+prog: annotate_barrier 2 1 1
+stderr_filter: filter_annotate_barrier_xml
diff --git a/main/drd/tests/annotate_hb_err.c b/main/drd/tests/annotate_hb_err.c
index 3ed15b9..0013eaf 100644
--- a/main/drd/tests/annotate_hb_err.c
+++ b/main/drd/tests/annotate_hb_err.c
@@ -45,9 +45,3 @@
fprintf(stderr, "Done.\n");
return 0;
}
-
-/*
- * Local variables:
- * c-basic-offset: 2
- * End:
- */
diff --git a/main/drd/tests/annotate_hb_race.c b/main/drd/tests/annotate_hb_race.c
index 14970f1..4aa5a38 100644
--- a/main/drd/tests/annotate_hb_race.c
+++ b/main/drd/tests/annotate_hb_race.c
@@ -46,9 +46,3 @@
return 0;
}
-
-/*
- * Local variables:
- * c-basic-offset: 2
- * End:
- */
diff --git a/main/drd/tests/annotate_hbefore.vgtest b/main/drd/tests/annotate_hbefore.vgtest
index d898915..e01bcde 100644
--- a/main/drd/tests/annotate_hbefore.vgtest
+++ b/main/drd/tests/annotate_hbefore.vgtest
@@ -1,4 +1,4 @@
prereq: test -e ../../helgrind/tests/annotate_hbefore && ./supported_libpthread
-vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no
+vgopts: --fair-sched=try --read-var-info=yes --check-stack-var=yes --show-confl-seg=no
prog: ../../helgrind/tests/annotate_hbefore
stderr_filter: filter_stderr
diff --git a/main/drd/tests/annotate_smart_pointer.cpp b/main/drd/tests/annotate_smart_pointer.cpp
index 862ecb0..bcf3a78 100755
--- a/main/drd/tests/annotate_smart_pointer.cpp
+++ b/main/drd/tests/annotate_smart_pointer.cpp
@@ -330,7 +330,3 @@
std::cerr << "Done.\n";
return 0;
}
-
-// Local variables:
-// c-basic-offset: 2
-// End:
diff --git a/main/drd/tests/annotate_smart_pointer2.stderr.exp b/main/drd/tests/annotate_smart_pointer2.stderr.exp
new file mode 100644
index 0000000..e53ae1c
--- /dev/null
+++ b/main/drd/tests/annotate_smart_pointer2.stderr.exp
@@ -0,0 +1,13 @@
+
+Conflicting store by thread x at 0x........ size 4
+ at 0x........: counter::~counter() (annotate_smart_pointer.cpp:?)
+ by 0x........: smart_ptr<counter>::set(counter*, AtomicInt32*) (annotate_smart_pointer.cpp:?)
+ by 0x........: smart_ptr<counter>::operator=(counter*) (annotate_smart_pointer.cpp:?)
+ by 0x........: main (annotate_smart_pointer.cpp:?)
+Address 0x........ is at offset ... from 0x......... Allocation context:
+ at 0x........: ...operator new... (vg_replace_malloc.c:...)
+ by 0x........: main (annotate_smart_pointer.cpp:?)
+
+Done.
+
+ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/annotate_smart_pointer2.vgtest b/main/drd/tests/annotate_smart_pointer2.vgtest
new file mode 100644
index 0000000..7556ce4
--- /dev/null
+++ b/main/drd/tests/annotate_smart_pointer2.vgtest
@@ -0,0 +1,5 @@
+prereq: test -e annotate_smart_pointer && ./supported_libpthread
+vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no
+prog: annotate_smart_pointer
+args: 1 1 0
+stderr_filter: filter_stderr_and_thread_no_and_offset
diff --git a/main/drd/tests/annotate_trace_memory.c b/main/drd/tests/annotate_trace_memory.c
new file mode 100644
index 0000000..697f0a8
--- /dev/null
+++ b/main/drd/tests/annotate_trace_memory.c
@@ -0,0 +1,49 @@
+#include <stdio.h>
+#include <inttypes.h>
+#include "../../drd/drd.h"
+
+volatile float f;
+volatile double d;
+volatile int8_t i8;
+volatile int16_t i16;
+volatile int32_t i32;
+volatile int64_t i64;
+
+int main(int argc, char** argv)
+{
+ DRD_TRACE_VAR(f);
+ DRD_TRACE_VAR(d);
+ DRD_TRACE_VAR(i8);
+ DRD_TRACE_VAR(i16);
+ DRD_TRACE_VAR(i32);
+ DRD_TRACE_VAR(i64);
+
+ fprintf(stderr, "float\n");
+ f = 1;
+ f += 2;
+ fprintf(stderr, "double\n");
+ d = 3;
+ d += 4;
+ fprintf(stderr, "uint8_t\n");
+ i8 = 5;
+ i8 += 6;
+ fprintf(stderr, "uint16_t\n");
+ i16 = 7;
+ i16++;
+ fprintf(stderr, "uint32_t\n");
+ i32 = 8;
+ __sync_add_and_fetch(&i32, 1);
+ fprintf(stderr, "uint64_t\n");
+ i64 = 9;
+ __sync_add_and_fetch(&i64, 0x12345678ULL);
+
+ DRD_STOP_TRACING_VAR(f);
+ DRD_STOP_TRACING_VAR(d);
+ DRD_STOP_TRACING_VAR(i8);
+ DRD_STOP_TRACING_VAR(i16);
+ DRD_STOP_TRACING_VAR(i32);
+ DRD_STOP_TRACING_VAR(i64);
+
+ fprintf(stderr, "Done.\n");
+ return 0;
+}
diff --git a/main/drd/tests/annotate_trace_memory.stderr.exp b/main/drd/tests/annotate_trace_memory.stderr.exp
deleted file mode 100644
index 9c48a6e..0000000
--- a/main/drd/tests/annotate_trace_memory.stderr.exp
+++ /dev/null
@@ -1,20 +0,0 @@
-
-FLAGS [phb=1, fm=0]
-test01: positive
-store 0x........ size 4 (thread x / vc ...)
- at 0x........: test01::Worker() (tsan_unittest.cpp:?)
- by 0x........: MyThread::ThreadBody(MyThread*) (tsan_thread_wrappers_pthread.h:?)
-store 0x........ size 4 (thread x / vc ...)
- at 0x........: test01::Parent() (tsan_unittest.cpp:?)
- by 0x........: test01::Run() (tsan_unittest.cpp:?)
-Conflicting store by thread x at 0x........ size 4
- at 0x........: test01::Parent() (tsan_unittest.cpp:?)
- by 0x........: test01::Run() (tsan_unittest.cpp:?)
-Allocation context: BSS section of tsan_unittest
-
-load 0x........ size 4 (thread x / vc ...)
- at 0x........: test01::Run() (tsan_unittest.cpp:?)
- by 0x........: main (tsan_unittest.cpp:?)
- GLOB=2
-
-ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/annotate_trace_memory.stderr.exp-32bit b/main/drd/tests/annotate_trace_memory.stderr.exp-32bit
new file mode 100644
index 0000000..4e44e60
--- /dev/null
+++ b/main/drd/tests/annotate_trace_memory.stderr.exp-32bit
@@ -0,0 +1,50 @@
+
+float
+store 0x........ size 4 val 1065353216/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 4 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 4 val 1077936128/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+double
+store 0x........ size 8 val 4613937818241073152/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 8 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 8 val 4619567317775286272/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+uint8_t
+store 0x........ size 1 val 5/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 1 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 1 val 11/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+uint16_t
+store 0x........ size 2 val 7/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 2 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 2 val 8/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+uint32_t
+store 0x........ size 4 val 8/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 4 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 4 val 9/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+uint64_t
+store 0x........ size 4 val 9/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 4 val 0/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 4 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 4 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 4 val 305419905/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+Done.
+
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/annotate_trace_memory.stderr.exp-64bit b/main/drd/tests/annotate_trace_memory.stderr.exp-64bit
new file mode 100644
index 0000000..fe85132
--- /dev/null
+++ b/main/drd/tests/annotate_trace_memory.stderr.exp-64bit
@@ -0,0 +1,46 @@
+
+float
+store 0x........ size 4 val 1065353216/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 4 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 4 val 1077936128/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+double
+store 0x........ size 8 val 4613937818241073152/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 8 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 8 val 4619567317775286272/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+uint8_t
+store 0x........ size 1 val 5/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 1 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 1 val 11/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+uint16_t
+store 0x........ size 2 val 7/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 2 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 2 val 8/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+uint32_t
+store 0x........ size 4 val 8/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 4 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 4 val 9/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+uint64_t
+store 0x........ size 8 val 9/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+load 0x........ size 8 (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+store 0x........ size 8 val 305419905/0x........ (thread x / vc ...)
+ at 0x........: main (annotate_trace_memory.c:?)
+Done.
+
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/annotate_trace_memory.vgtest b/main/drd/tests/annotate_trace_memory.vgtest
index e7d23e2..20d5a51 100644
--- a/main/drd/tests/annotate_trace_memory.vgtest
+++ b/main/drd/tests/annotate_trace_memory.vgtest
@@ -1,5 +1,4 @@
-prereq: test -e tsan_unittest && ./supported_libpthread
+prereq: test -e annotate_trace_memory && ./supported_libpthread
vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no --num-callers=2
-prog: tsan_unittest
-args: 1
+prog: annotate_trace_memory
stderr_filter: filter_stderr_and_thread_no
diff --git a/main/drd/tests/annotate_trace_memory_xml.stderr.exp-32bit b/main/drd/tests/annotate_trace_memory_xml.stderr.exp-32bit
new file mode 100644
index 0000000..751c622
--- /dev/null
+++ b/main/drd/tests/annotate_trace_memory_xml.stderr.exp-32bit
@@ -0,0 +1,290 @@
+<?xml version="1.0"?>
+
+<valgrindoutput>
+
+<protocolversion>4</protocolversion>
+<protocoltool>drd</protocoltool>
+
+<preamble>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+</preamble>
+
+<pid>...</pid>
+<ppid>...</ppid>
+<tool>drd</tool>
+
+<args>
+ <vargv>...</vargv>
+ <argv>
+ <exe>./annotate_trace_memory</exe>
+ </argv>
+</args>
+
+<status>
+ <state>RUNNING</state>
+ <time>...</time>
+</status>
+
+float
+ <trace><text>store 0x........ size 4 val 1065353216/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 4 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 4 val 1077936128/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+double
+ <trace><text>store 0x........ size 8 val 4613937818241073152/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 8 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 8 val 4619567317775286272/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+uint8_t
+ <trace><text>store 0x........ size 1 val 5/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 1 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 1 val 11/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+uint16_t
+ <trace><text>store 0x........ size 2 val 7/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 2 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 2 val 8/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+uint32_t
+ <trace><text>store 0x........ size 4 val 8/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 4 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 4 val 9/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+uint64_t
+ <trace><text>store 0x........ size 4 val 9/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 4 val 0/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 4 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 4 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 4 val 305419905/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+Done.
+
+<status>
+ <state>FINISHED</state>
+ <time>...</time>
+</status>
+
+<errorcounts>
+</errorcounts>
+
+<suppcounts>...</suppcounts>
+
+</valgrindoutput>
+
diff --git a/main/drd/tests/annotate_trace_memory_xml.stderr.exp-64bit b/main/drd/tests/annotate_trace_memory_xml.stderr.exp-64bit
new file mode 100644
index 0000000..8a62b6c
--- /dev/null
+++ b/main/drd/tests/annotate_trace_memory_xml.stderr.exp-64bit
@@ -0,0 +1,266 @@
+<?xml version="1.0"?>
+
+<valgrindoutput>
+
+<protocolversion>4</protocolversion>
+<protocoltool>drd</protocoltool>
+
+<preamble>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+</preamble>
+
+<pid>...</pid>
+<ppid>...</ppid>
+<tool>drd</tool>
+
+<args>
+ <vargv>...</vargv>
+ <argv>
+ <exe>./annotate_trace_memory</exe>
+ </argv>
+</args>
+
+<status>
+ <state>RUNNING</state>
+ <time>...</time>
+</status>
+
+float
+ <trace><text>store 0x........ size 4 val 1065353216/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 4 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 4 val 1077936128/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+double
+ <trace><text>store 0x........ size 8 val 4613937818241073152/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 8 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 8 val 4619567317775286272/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+uint8_t
+ <trace><text>store 0x........ size 1 val 5/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 1 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 1 val 11/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+uint16_t
+ <trace><text>store 0x........ size 2 val 7/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 2 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 2 val 8/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+uint32_t
+ <trace><text>store 0x........ size 4 val 8/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 4 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 4 val 9/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+uint64_t
+ <trace><text>store 0x........ size 8 val 9/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>load 0x........ size 8 (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+ <trace><text>store 0x........ size 8 val 305419905/0x........ (thread x / vc ...)</text>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>annotate_trace_memory.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </trace>
+Done.
+
+<status>
+ <state>FINISHED</state>
+ <time>...</time>
+</status>
+
+<errorcounts>
+</errorcounts>
+
+<suppcounts>...</suppcounts>
+
+</valgrindoutput>
+
diff --git a/main/drd/tests/annotate_trace_memory_xml.vgtest b/main/drd/tests/annotate_trace_memory_xml.vgtest
new file mode 100644
index 0000000..48da0cb
--- /dev/null
+++ b/main/drd/tests/annotate_trace_memory_xml.vgtest
@@ -0,0 +1,4 @@
+prereq: test -e annotate_trace_memory && ./supported_libpthread
+vgopts: --read-var-info=yes --check-stack-var=yes --show-confl-seg=no --num-callers=2 --xml=yes --xml-fd=2
+prog: annotate_trace_memory
+stderr_filter: ./filter_xml_and_thread_no
diff --git a/main/drd/tests/bar_bad_xml.stderr.exp b/main/drd/tests/bar_bad_xml.stderr.exp
new file mode 100644
index 0000000..acb9656
--- /dev/null
+++ b/main/drd/tests/bar_bad_xml.stderr.exp
@@ -0,0 +1,315 @@
+<?xml version="1.0"?>
+
+<valgrindoutput>
+
+<protocolversion>4</protocolversion>
+<protocoltool>drd</protocoltool>
+
+<preamble>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+</preamble>
+
+<pid>...</pid>
+<ppid>...</ppid>
+<tool>drd</tool>
+
+<args>
+ <vargv>...</vargv>
+ <argv>
+ <exe>./../../helgrind/tests/bar_bad</exe>
+ </argv>
+</args>
+
+<status>
+ <state>RUNNING</state>
+ <time>...</time>
+</status>
+
+
+initialise a barrier with zero count
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>BarrierErr</kind>
+ <what>pthread_barrier_init: 'count' argument is zero: barrier 0x........</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_barrier_init</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+initialise a barrier twice
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>BarrierErr</kind>
+ <what>Barrier reinitialization: barrier 0x........</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_barrier_init</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ <first_observed_at>
+ <what>barrier</what>
+ <address>0x........</address>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_barrier_init</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </first_observed_at>
+</error>
+
+
+initialise a barrier which has threads waiting on it
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>BarrierErr</kind>
+ <what>Barrier reinitialization: barrier 0x........</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_barrier_init</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ <first_observed_at>
+ <what>barrier</what>
+ <address>0x........</address>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_barrier_init</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </first_observed_at>
+</error>
+
+
+destroy a barrier that has waiting threads
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>BarrierErr</kind>
+ <what>Destruction of a barrier with active waiters: barrier 0x........</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_barrier_destroy</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ <first_observed_at>
+ <what>barrier</what>
+ <address>0x........</address>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_barrier_init</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </first_observed_at>
+</error>
+
+
+destroy a barrier that was never initialised
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>GenericErr</kind>
+ <what>Not a barrier</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_barrier_destroy</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>BarrierErr</kind>
+ <what>Destruction of barrier that is being waited upon: barrier 0x........</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>free</fn>
+ <dir>...</dir>
+ <file>vg_replace_malloc.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ <first_observed_at>
+ <what>barrier</what>
+ <address>0x........</address>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_barrier_init</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>bar_bad.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ </first_observed_at>
+</error>
+
+
+<status>
+ <state>FINISHED</state>
+ <time>...</time>
+</status>
+
+<errorcounts>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+</errorcounts>
+
+<suppcounts>...</suppcounts>
+
+</valgrindoutput>
+
diff --git a/main/drd/tests/bar_bad_xml.vgtest b/main/drd/tests/bar_bad_xml.vgtest
new file mode 100644
index 0000000..d626dc3
--- /dev/null
+++ b/main/drd/tests/bar_bad_xml.vgtest
@@ -0,0 +1,4 @@
+prereq: test -e ../../helgrind/tests/bar_bad && ./supported_libpthread
+vgopts: --xml=yes --xml-fd=2
+prog: ../../helgrind/tests/bar_bad
+stderr_filter: ../../memcheck/tests/filter_xml
diff --git a/main/drd/tests/custom_alloc_fiw.stderr.exp b/main/drd/tests/custom_alloc_fiw.stderr.exp
new file mode 100644
index 0000000..ef056f1
--- /dev/null
+++ b/main/drd/tests/custom_alloc_fiw.stderr.exp
@@ -0,0 +1,12 @@
+
+--free-is-write=yes is incompatible with custom memory allocator client requests
+ at 0x........: custom_alloc (custom_alloc.c:?)
+ by 0x........: main (custom_alloc.c:?)
+
+--free-is-write=yes is incompatible with custom memory allocator client requests
+ at 0x........: custom_alloc (custom_alloc.c:?)
+ by 0x........: make_leak (custom_alloc.c:?)
+ by 0x........: main (custom_alloc.c:?)
+
+
+ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/custom_alloc_fiw.vgtest b/main/drd/tests/custom_alloc_fiw.vgtest
new file mode 100644
index 0000000..26b9cf3
--- /dev/null
+++ b/main/drd/tests/custom_alloc_fiw.vgtest
@@ -0,0 +1,2 @@
+vgopts: --free-is-write=yes
+prog: custom_alloc
diff --git a/main/drd/tests/filter_stderr b/main/drd/tests/filter_stderr
index 4e82940..a1a5959 100755
--- a/main/drd/tests/filter_stderr
+++ b/main/drd/tests/filter_stderr
@@ -32,6 +32,7 @@
-e "s/ (\([a-zA-Z_]*\.h\):[0-9]*)/ (\1:?)/" \
-e "s/ (\([a-zA-Z_]*\.cpp\):[0-9]*)/ (\1:?)/" \
-e "s/\( name [^ ]*\)-[0-9]*\( oflag \)/\1\2/" \
+-e '/^ by 0x[0-9a-fA-F]*: process_dl_debug (in \/lib[0-9]*\/ld-[0-9.]*\.so)$/d' \
-e "/^For counts of detected and suppressed errors, rerun with: -v$/d" |
# Remove the message that more than hundred errors have been detected
diff --git a/main/drd/tests/filter_xml_and_thread_no b/main/drd/tests/filter_xml_and_thread_no
index 4e65091..a9f7ac1 100644
--- a/main/drd/tests/filter_xml_and_thread_no
+++ b/main/drd/tests/filter_xml_and_thread_no
@@ -1,3 +1,5 @@
#! /bin/sh
-../../memcheck/tests/filter_xml | ./filter_thread_no
+../../memcheck/tests/filter_xml |
+./filter_thread_no |
+sed 's/ vc: \[[0-9:, ]*\]/ vc: [ ... ]/g'
diff --git a/main/drd/tests/fp_race_xml.stderr.exp b/main/drd/tests/fp_race_xml.stderr.exp
new file mode 100644
index 0000000..73a530e
--- /dev/null
+++ b/main/drd/tests/fp_race_xml.stderr.exp
@@ -0,0 +1,104 @@
+<?xml version="1.0"?>
+
+<valgrindoutput>
+
+<protocolversion>4</protocolversion>
+<protocoltool>drd</protocoltool>
+
+<preamble>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+</preamble>
+
+<pid>...</pid>
+<ppid>...</ppid>
+<tool>drd</tool>
+
+<args>
+ <vargv>...</vargv>
+ <argv>
+ <exe>./fp_race</exe>
+ </argv>
+</args>
+
+<status>
+ <state>RUNNING</state>
+ <time>...</time>
+</status>
+
+ <trace><text>drd_pre_thread_create creator = 0, created = 1</text></trace>
+ <trace><text>drd_post_thread_create created = 1</text></trace>
+ <trace><text>drd_pre_thread_create creator = 1, created = 2</text></trace>
+ <trace><text>drd_post_thread_create created = 2</text></trace>
+ <trace><text>drd_thread_finished tid = 2</text></trace>
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>ConflictingAccess</kind>
+ <what>Conflicting load by thread x at 0x........ size 8</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>fp_race.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ <auxwhat>Location 0x........ is 0 bytes inside local var "s_d3"</auxwhat>
+ <xauxwhat><text>declared at fp_race.c:24, in frame #? of thread x</text> <file>fp_race.c</file> <line>...</line> </xauxwhat>
+ <other_segment_start>
+ </other_segment_start>
+ <other_segment_end>
+ </other_segment_end>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>ConflictingAccess</kind>
+ <what>Conflicting store by thread x at 0x........ size 8</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>fp_race.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ <auxwhat>Location 0x........ is 0 bytes inside local var "s_d3"</auxwhat>
+ <xauxwhat><text>declared at fp_race.c:24, in frame #? of thread x</text> <file>fp_race.c</file> <line>...</line> </xauxwhat>
+ <other_segment_start>
+ </other_segment_start>
+ <other_segment_end>
+ </other_segment_end>
+</error>
+
+ <trace><text>drd_post_thread_join joiner = 1, joinee = 2, new vc: [ ... ]</text></trace>
+ <trace><text>drd_thread_finished tid = 1</text></trace>
+
+<status>
+ <state>FINISHED</state>
+ <time>...</time>
+</status>
+
+<errorcounts>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+</errorcounts>
+
+<suppcounts>...</suppcounts>
+
+</valgrindoutput>
+
diff --git a/main/drd/tests/fp_race_xml.vgtest b/main/drd/tests/fp_race_xml.vgtest
new file mode 100644
index 0000000..712404c
--- /dev/null
+++ b/main/drd/tests/fp_race_xml.vgtest
@@ -0,0 +1,4 @@
+prereq: ./supported_libpthread
+vgopts: --read-var-info=yes --xml=yes --xml-fd=2 --trace-fork-join=yes
+prog: fp_race
+stderr_filter: ./filter_xml_and_thread_no
diff --git a/main/drd/tests/free_is_write.c b/main/drd/tests/free_is_write.c
index 899a853..056e417 100644
--- a/main/drd/tests/free_is_write.c
+++ b/main/drd/tests/free_is_write.c
@@ -62,9 +62,3 @@
return 0;
}
-
-/*
- * Local variables:
- * c-basic-offset: 2
- * End:
- */
diff --git a/main/drd/tests/pth_barrier_thr_cr.c b/main/drd/tests/pth_barrier_thr_cr.c
new file mode 100644
index 0000000..ab14f90
--- /dev/null
+++ b/main/drd/tests/pth_barrier_thr_cr.c
@@ -0,0 +1,58 @@
+/*
+ * Test program that triggers pthread_barrier_wait() where each
+ * pthread_barrier_wait() call is invoked by another thread. This is the only
+ * test program that triggers the code guarded by if (q->thread_finished) in
+ * DRD_(barrier_pre_wait)().
+ */
+
+#define _GNU_SOURCE
+
+#include <assert.h>
+#include <pthread.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+static pthread_barrier_t* s_barrier;
+
+static void* thread(void* arg)
+{
+ write(STDOUT_FILENO, ".", 1);
+ pthread_barrier_wait(s_barrier);
+ return NULL;
+}
+
+int main(int argc, char** argv)
+{
+ pthread_t *tid;
+ int barriers = argc > 1 ? atoi(argv[1]) : 20;
+ int barrier_participants = 2;
+ int thread_count = barriers * barrier_participants;
+ int res, i;
+
+ s_barrier = malloc(sizeof(*s_barrier));
+ res = pthread_barrier_init(s_barrier, NULL, barrier_participants);
+ assert(res == 0);
+
+ tid = malloc(thread_count * sizeof(*tid));
+ assert(tid);
+ for (i = 0; i < thread_count; i++) {
+ res = pthread_create(&tid[i], NULL, thread, NULL);
+ assert(res == 0);
+ }
+ for (i = 0; i < thread_count; i++) {
+ res = pthread_join(tid[i], NULL);
+ assert(res == 0);
+ }
+ free(tid);
+
+ res = pthread_barrier_destroy(s_barrier);
+ assert(res == 0);
+ free(s_barrier);
+ s_barrier = NULL;
+
+ write(STDOUT_FILENO, "\n", 1);
+ fprintf(stderr, "Done.\n");
+
+ return 0;
+}
diff --git a/main/drd/tests/pth_barrier_thr_cr.stderr.exp b/main/drd/tests/pth_barrier_thr_cr.stderr.exp
new file mode 100644
index 0000000..d16127f
--- /dev/null
+++ b/main/drd/tests/pth_barrier_thr_cr.stderr.exp
@@ -0,0 +1,4 @@
+
+Done.
+
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/pth_barrier_thr_cr.supp b/main/drd/tests/pth_barrier_thr_cr.supp
new file mode 100644
index 0000000..7746043
--- /dev/null
+++ b/main/drd/tests/pth_barrier_thr_cr.supp
@@ -0,0 +1,5 @@
+{
+ number-of-concurrent-pthead_barrier_wait()-calls-exceeds-barrier-count
+ drd:BarrierErr
+ fun:pthread_barrier_wait
+}
diff --git a/main/drd/tests/pth_barrier_thr_cr.vgtest b/main/drd/tests/pth_barrier_thr_cr.vgtest
new file mode 100644
index 0000000..013e856
--- /dev/null
+++ b/main/drd/tests/pth_barrier_thr_cr.vgtest
@@ -0,0 +1,5 @@
+prereq: test -e pth_barrier_thr_cr && ./supported_libpthread
+vgopts: --suppressions=pth_barrier_thr_cr.supp
+prog: pth_barrier_thr_cr
+args: 50
+stdout_filter: ../../tests/filter_sink
diff --git a/main/drd/tests/pth_cleanup_handler.c b/main/drd/tests/pth_cleanup_handler.c
index ada1750..0fb3d07 100644
--- a/main/drd/tests/pth_cleanup_handler.c
+++ b/main/drd/tests/pth_cleanup_handler.c
@@ -39,7 +39,7 @@
pthread_t pt1, pt2;
// Make sure the program exits in case a deadlock has been triggered.
- alarm(2);
+ alarm(20);
if (pthread_mutex_init(&s_mutex, NULL) != 0)
{
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/drd/tests/pth_detached.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/drd/tests/pth_detached.stdout.exp
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/drd/tests/pth_detached2.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/drd/tests/pth_detached2.stdout.exp
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/drd/tests/pth_detached_sem.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/drd/tests/pth_detached_sem.stdout.exp
diff --git a/main/drd/tests/read_after_free.c b/main/drd/tests/read_after_free.c
deleted file mode 100644
index 1319cb2..0000000
--- a/main/drd/tests/read_after_free.c
+++ /dev/null
@@ -1,45 +0,0 @@
-#define _GNU_SOURCE 1
-
-#include <assert.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <pthread.h>
-
-static char* s_mem;
-static volatile int s_freed;
-
-static void* thread_func(void* arg)
-{
- // Busy-wait until pthread_create() has finished.
- while (s_freed == 0)
- pthread_yield();
- free(s_mem);
- __sync_add_and_fetch(&s_freed, 1);
- return NULL;
-}
-
-int main(int argc, char** argv)
-{
- pthread_t tid;
- int quiet;
- char result;
-
- quiet = argc > 1;
-
- s_mem = malloc(10);
- if (!quiet)
- fprintf(stderr, "Pointer to allocated memory: %p\n", s_mem);
- assert(s_mem);
- pthread_create(&tid, NULL, thread_func, NULL);
- __sync_add_and_fetch(&s_freed, 1);
- // Busy-wait until the memory has been freed.
- while (s_freed == 1)
- pthread_yield();
- // Read-after-free.
- result = s_mem[0];
- if (!quiet)
- fprintf(stderr, "Read-after-free result: %d\n", result);
- pthread_join(tid, NULL);
- fprintf(stderr, "Done.\n");
- return 0;
-}
diff --git a/main/drd/tests/read_after_free.stderr.exp b/main/drd/tests/read_after_free.stderr.exp
deleted file mode 100644
index 7463c72..0000000
--- a/main/drd/tests/read_after_free.stderr.exp
+++ /dev/null
@@ -1,8 +0,0 @@
-
-Conflicting load by thread 1 at 0x........ size 1
- at 0x........: main (read_after_free.c:?)
-Allocation context: unknown.
-
-Done.
-
-ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/read_after_free.vgtest b/main/drd/tests/read_after_free.vgtest
deleted file mode 100644
index c8b1c2b..0000000
--- a/main/drd/tests/read_after_free.vgtest
+++ /dev/null
@@ -1,4 +0,0 @@
-prereq: test -e read_after_free && ./supported_libpthread
-vgopts: --read-var-info=yes --check-stack-var=yes --free-is-write=yes --show-confl-seg=no
-prog: read_after_free
-args: -q
diff --git a/main/drd/tests/read_and_free_race.stderr.exp b/main/drd/tests/read_and_free_race.stderr.exp
new file mode 100644
index 0000000..83b1f01
--- /dev/null
+++ b/main/drd/tests/read_and_free_race.stderr.exp
@@ -0,0 +1,14 @@
+
+Start.
+Thread 2:
+Conflicting store by thread 2 at 0x........ size 10
+ at 0x........: free (vg_replace_malloc.c:...)
+ by 0x........: thread_func (free_is_write.c:?)
+ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?)
+Address 0x........ is at offset 0 from 0x......... Allocation context:
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (free_is_write.c:?)
+
+Done.
+
+ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/read_and_free_race.vgtest b/main/drd/tests/read_and_free_race.vgtest
new file mode 100644
index 0000000..eac2d09
--- /dev/null
+++ b/main/drd/tests/read_and_free_race.vgtest
@@ -0,0 +1,2 @@
+prog: ../../helgrind/tests/free_is_write
+vgopts: --free-is-write=yes --num-callers=3 --show-confl-seg=no
diff --git a/main/drd/tests/sigalrm.c b/main/drd/tests/sigalrm.c
index 38b979c..85987ab 100644
--- a/main/drd/tests/sigalrm.c
+++ b/main/drd/tests/sigalrm.c
@@ -72,7 +72,10 @@
sigaction(SIGALRM, &sa, 0);
}
- pthread_create(&threadid, 0, thread_func, 0);
+ if (pthread_create(&threadid, 0, thread_func, 0) != 0) {
+ fprintf(stderr, "Thread creation failed\n");
+ return 1;
+ }
// Wait until the thread is inside clock_nanosleep().
tsDelay.tv_sec = 0;
tsDelay.tv_nsec = 20 * 1000 * 1000;
diff --git a/main/drd/tests/std_thread.cpp b/main/drd/tests/std_thread.cpp
new file mode 100644
index 0000000..e4487d4
--- /dev/null
+++ b/main/drd/tests/std_thread.cpp
@@ -0,0 +1,23 @@
+// Test whether no race conditions are reported on std::thread. Note: since
+// the implementation of std::thread uses the shared pointer implementation,
+// that implementation has to be annotated in order to avoid false positives.
+// See also http://gcc.gnu.org/onlinedocs/libstdc++/manual/debug.html for more
+// information.
+
+#include "../../drd/drd.h"
+#define _GLIBCXX_SYNCHRONIZATION_HAPPENS_BEFORE(addr) \
+ ANNOTATE_HAPPENS_BEFORE(addr)
+#define _GLIBCXX_SYNCHRONIZATION_HAPPENS_AFTER(addr) \
+ ANNOTATE_HAPPENS_AFTER(addr)
+#define _GLIBCXX_EXTERN_TEMPLATE -1
+
+#include <iostream>
+#include <thread>
+
+int main(int argc, char** argv)
+{
+ std::thread t( []() { } );
+ t.join();
+ std::cerr << "Done.\n";
+ return 0;
+}
diff --git a/main/drd/tests/std_thread.stderr.exp b/main/drd/tests/std_thread.stderr.exp
new file mode 100644
index 0000000..d16127f
--- /dev/null
+++ b/main/drd/tests/std_thread.stderr.exp
@@ -0,0 +1,4 @@
+
+Done.
+
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/std_thread.vgtest b/main/drd/tests/std_thread.vgtest
new file mode 100644
index 0000000..e6264c2
--- /dev/null
+++ b/main/drd/tests/std_thread.vgtest
@@ -0,0 +1,4 @@
+prereq: false && test -e std_thread && ./supported_libpthread
+vgopts: --check-stack-var=yes --show-confl-seg=no
+prog: std_thread
+stderr_filter: filter_stderr
diff --git a/main/drd/tests/tc04_free_lock.stderr.exp-ppc b/main/drd/tests/tc04_free_lock.stderr.exp-ppc
new file mode 100644
index 0000000..50304a0
--- /dev/null
+++ b/main/drd/tests/tc04_free_lock.stderr.exp-ppc
@@ -0,0 +1,34 @@
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: free (vg_replace_malloc.c:...)
+ by 0x........: main (tc04_free_lock.c:24)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc04_free_lock.c:20)
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: bar (tc04_free_lock.c:38)
+ by 0x........: main (tc04_free_lock.c:26)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_lock (drd_pthread_intercepts.c:?)
+ by 0x........: bar (tc04_free_lock.c:38)
+ by 0x........: main (tc04_free_lock.c:26)
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: foo (tc04_free_lock.c:47)
+ by 0x........: main (tc04_free_lock.c:27)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: foo (tc04_free_lock.c:46)
+ by 0x........: main (tc04_free_lock.c:27)
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: bar (tc04_free_lock.c:38)
+ by 0x........: main (tc04_free_lock.c:28)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_lock (drd_pthread_intercepts.c:?)
+ by 0x........: bar (tc04_free_lock.c:38)
+ by 0x........: main (tc04_free_lock.c:28)
+
+
+ERROR SUMMARY: 4 errors from 4 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/tc04_free_lock.stderr.exp-s390 b/main/drd/tests/tc04_free_lock.stderr.exp-s390
new file mode 100644
index 0000000..041ae3c
--- /dev/null
+++ b/main/drd/tests/tc04_free_lock.stderr.exp-s390
@@ -0,0 +1,26 @@
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: free (vg_replace_malloc.c:...)
+ by 0x........: main (tc04_free_lock.c:24)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc04_free_lock.c:20)
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: bar (tc04_free_lock.c:40)
+ by 0x........: ???
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_lock (drd_pthread_intercepts.c:?)
+ by 0x........: bar (tc04_free_lock.c:38)
+ by 0x........: main (tc04_free_lock.c:26)
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: foo (tc04_free_lock.c:49)
+ by 0x........: ???
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: foo (tc04_free_lock.c:46)
+ by 0x........: main (tc04_free_lock.c:27)
+
+
+ERROR SUMMARY: 4 errors from 3 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/tc04_free_lock.stderr.exp b/main/drd/tests/tc04_free_lock.stderr.exp-x86
similarity index 100%
rename from main/drd/tests/tc04_free_lock.stderr.exp
rename to main/drd/tests/tc04_free_lock.stderr.exp-x86
diff --git a/main/drd/tests/tc04_free_lock.vgtest b/main/drd/tests/tc04_free_lock.vgtest
index c8ae55c..5507a63 100644
--- a/main/drd/tests/tc04_free_lock.vgtest
+++ b/main/drd/tests/tc04_free_lock.vgtest
@@ -1,3 +1,4 @@
prereq: ./supported_libpthread
vgopts: --check-stack-var=yes
prog: ../../helgrind/tests/tc04_free_lock
+stderr_filter: filter_stderr
diff --git a/main/drd/tests/tc09_bad_unlock.stderr.exp-ppc b/main/drd/tests/tc09_bad_unlock.stderr.exp-ppc
new file mode 100644
index 0000000..0be4db6
--- /dev/null
+++ b/main/drd/tests/tc09_bad_unlock.stderr.exp-ppc
@@ -0,0 +1,59 @@
+
+Mutex not locked by calling thread: mutex 0x........, recursion count 0, owner 1.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:27)
+ by 0x........: main (tc09_bad_unlock.c:49)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:23)
+ by 0x........: main (tc09_bad_unlock.c:49)
+
+Thread 2:
+Mutex not locked by calling thread: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: child_fn (tc09_bad_unlock.c:11)
+ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:31)
+ by 0x........: main (tc09_bad_unlock.c:49)
+
+Thread 1:
+The object at address 0x........ is not a mutex.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:41)
+ by 0x........: main (tc09_bad_unlock.c:49)
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: nearly_main (tc09_bad_unlock.c:41)
+ by 0x........: main (tc09_bad_unlock.c:49)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:31)
+ by 0x........: main (tc09_bad_unlock.c:49)
+
+---------------------
+Mutex not locked by calling thread: mutex 0x........, recursion count 0, owner 1.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:27)
+ by 0x........: main (tc09_bad_unlock.c:50)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:23)
+ by 0x........: main (tc09_bad_unlock.c:50)
+
+The object at address 0x........ is not a mutex.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:41)
+ by 0x........: main (tc09_bad_unlock.c:50)
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: nearly_main (tc09_bad_unlock.c:41)
+ by 0x........: main (tc09_bad_unlock.c:50)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:31)
+ by 0x........: main (tc09_bad_unlock.c:50)
+
+
+ERROR SUMMARY: 8 errors from 7 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/tc09_bad_unlock.stderr.exp-s390 b/main/drd/tests/tc09_bad_unlock.stderr.exp-s390
new file mode 100644
index 0000000..dd84c81
--- /dev/null
+++ b/main/drd/tests/tc09_bad_unlock.stderr.exp-s390
@@ -0,0 +1,51 @@
+
+Mutex not locked by calling thread: mutex 0x........, recursion count 0, owner 1.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:27)
+ by 0x........: main (tc09_bad_unlock.c:49)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:23)
+ by 0x........: main (tc09_bad_unlock.c:49)
+
+Thread 2:
+Mutex not locked by calling thread: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: child_fn (tc09_bad_unlock.c:11)
+ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:31)
+ by 0x........: main (tc09_bad_unlock.c:49)
+
+Thread 1:
+The object at address 0x........ is not a mutex.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:41)
+ by 0x........: main (tc09_bad_unlock.c:49)
+
+Destroying locked mutex: mutex 0x........, recursion count 1, owner 1.
+ at 0x........: nearly_main (tc09_bad_unlock.c:45)
+ by 0x........: ???
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:31)
+ by 0x........: main (tc09_bad_unlock.c:49)
+
+---------------------
+Mutex not locked by calling thread: mutex 0x........, recursion count 0, owner 1.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:27)
+ by 0x........: main (tc09_bad_unlock.c:50)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:23)
+ by 0x........: main (tc09_bad_unlock.c:50)
+
+The object at address 0x........ is not a mutex.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: nearly_main (tc09_bad_unlock.c:41)
+ by 0x........: main (tc09_bad_unlock.c:50)
+
+
+ERROR SUMMARY: 8 errors from 6 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/tc09_bad_unlock.stderr.exp b/main/drd/tests/tc09_bad_unlock.stderr.exp-x86
similarity index 100%
rename from main/drd/tests/tc09_bad_unlock.stderr.exp
rename to main/drd/tests/tc09_bad_unlock.stderr.exp-x86
diff --git a/main/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-amd64 b/main/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-amd64
new file mode 100644
index 0000000..d305391
--- /dev/null
+++ b/main/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-amd64
@@ -0,0 +1,76 @@
+
+The object at address 0x........ is not a mutex.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:69)
+
+Mutex not locked: mutex 0x........, recursion count 0, owner 0.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:72)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:51)
+
+Thread 3:
+Probably a race condition: condition variable 0x........ has been signaled but the associated mutex 0x........ is not locked by the signalling thread.
+ at 0x........: pthread_cond_signal (drd_pthread_intercepts.c:?)
+ by 0x........: rescue_me (tc23_bogus_condwait.c:20)
+ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?)
+cond 0x........ was first observed at:
+ at 0x........: pthread_cond_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:56)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:51)
+
+Thread 1:
+The object at address 0x........ is not a mutex.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:75)
+rwlock 0x........ was first observed at:
+ at 0x........: pthread_rwlock_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:57)
+
+Mutex not locked by calling thread: mutex 0x........, recursion count 1, owner 2.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:78)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:53)
+
+Thread 3:
+Probably a race condition: condition variable 0x........ has been signaled but the associated mutex 0x........ is not locked by the signalling thread.
+ at 0x........: pthread_cond_signal (drd_pthread_intercepts.c:?)
+ by 0x........: rescue_me (tc23_bogus_condwait.c:24)
+ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?)
+cond 0x........ was first observed at:
+ at 0x........: pthread_cond_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:56)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:53)
+
+Thread 1:
+The impossible happened: mutex is locked simultaneously by two threads: mutex 0x........, recursion count 1, owner 2.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:78)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:53)
+
+Thread 2:
+Mutex not locked by calling thread: mutex 0x........, recursion count 2, owner 1.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: grab_the_lock (tc23_bogus_condwait.c:42)
+ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:53)
+
+Assertion failed: (!r), function main, file tc23_bogus_condwait.c, line 86.
+
+Process terminating with default action of signal 6 (SIGABRT)
+ at 0x........: __kill (in /...libc...)
+ by 0x........: __assert_rtn (in /...libc...)
+ by 0x........: main (tc23_bogus_condwait.c:86)
+
+ERROR SUMMARY: 10 errors from 8 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-x86 b/main/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-x86
new file mode 100644
index 0000000..577e146
--- /dev/null
+++ b/main/drd/tests/tc23_bogus_condwait.stderr.exp-darwin-x86
@@ -0,0 +1,70 @@
+
+The object at address 0x........ is not a mutex.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:69)
+
+Mutex not locked: mutex 0x........, recursion count 0, owner 0.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:72)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:51)
+
+Thread 3:
+Probably a race condition: condition variable 0x........ has been signaled but the associated mutex 0x........ is not locked by the signalling thread.
+ at 0x........: pthread_cond_signal (drd_pthread_intercepts.c:?)
+ by 0x........: rescue_me (tc23_bogus_condwait.c:20)
+ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?)
+cond 0x........ was first observed at:
+ at 0x........: pthread_cond_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:56)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:51)
+
+Thread 1:
+The object at address 0x........ is not a mutex.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:75)
+rwlock 0x........ was first observed at:
+ at 0x........: pthread_rwlock_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:57)
+
+Mutex not locked by calling thread: mutex 0x........, recursion count 1, owner 2.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:78)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:53)
+
+Thread 3:
+Probably a race condition: condition variable 0x........ has been signaled but the associated mutex 0x........ is not locked by the signalling thread.
+ at 0x........: pthread_cond_signal (drd_pthread_intercepts.c:?)
+ by 0x........: rescue_me (tc23_bogus_condwait.c:24)
+ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?)
+cond 0x........ was first observed at:
+ at 0x........: pthread_cond_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:56)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:53)
+
+Thread 1:
+The impossible happened: mutex is locked simultaneously by two threads: mutex 0x........, recursion count 1, owner 2.
+ at 0x........: pthread_cond_wait (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:78)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:53)
+
+Thread 2:
+Mutex not locked by calling thread: mutex 0x........, recursion count 2, owner 1.
+ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?)
+ by 0x........: grab_the_lock (tc23_bogus_condwait.c:42)
+ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?)
+mutex 0x........ was first observed at:
+ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?)
+ by 0x........: main (tc23_bogus_condwait.c:53)
+
+
+ERROR SUMMARY: 10 errors from 8 contexts (suppressed: 0 from 0)
diff --git a/main/drd/tests/thread_name_xml.stderr.exp b/main/drd/tests/thread_name_xml.stderr.exp
new file mode 100644
index 0000000..36b5360
--- /dev/null
+++ b/main/drd/tests/thread_name_xml.stderr.exp
@@ -0,0 +1,443 @@
+<?xml version="1.0"?>
+
+<valgrindoutput>
+
+<protocolversion>4</protocolversion>
+<protocoltool>drd</protocoltool>
+
+<preamble>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+</preamble>
+
+<pid>...</pid>
+<ppid>...</ppid>
+<tool>drd</tool>
+
+<args>
+ <vargv>...</vargv>
+ <argv>
+ <exe>./thread_name</exe>
+ </argv>
+</args>
+
+<status>
+ <state>RUNNING</state>
+ <time>...</time>
+</status>
+
+
+thread_func instance 1
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+thread_func instance 2
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+thread_func instance 3
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+thread_func instance 4
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+thread_func instance 5
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+thread_func instance 6
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+thread_func instance 7
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+thread_func instance 8
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+thread_func instance 9
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+thread_func instance 10
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>MutexErr</kind>
+ <what>The object at address 0x........ is not a mutex.</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>pthread_mutex_unlock</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>thread_func</fn>
+ <dir>...</dir>
+ <file>thread_name.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>vgDrd_thread_wrapper</fn>
+ <dir>...</dir>
+ <file>drd_pthread_intercepts.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+
+<status>
+ <state>FINISHED</state>
+ <time>...</time>
+</status>
+
+<errorcounts>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+</errorcounts>
+
+<suppcounts>...</suppcounts>
+
+</valgrindoutput>
+
diff --git a/main/drd/tests/thread_name_xml.vgtest b/main/drd/tests/thread_name_xml.vgtest
new file mode 100644
index 0000000..f931e48
--- /dev/null
+++ b/main/drd/tests/thread_name_xml.vgtest
@@ -0,0 +1,4 @@
+prereq: test -e thread_name && ./supported_libpthread
+vgopts: --read-var-info=yes --check-stack-var=yes --num-callers=3 --xml=yes --xml-fd=2
+prog: thread_name
+stderr_filter: ../../memcheck/tests/filter_xml
diff --git a/main/drd/tests/unified_annotations.h b/main/drd/tests/unified_annotations.h
index 13259d6..4973e8f 100644
--- a/main/drd/tests/unified_annotations.h
+++ b/main/drd/tests/unified_annotations.h
@@ -62,9 +62,3 @@
#endif /* _UNIFIED_ANNOTATIONS_H_ */
-
-/*
- * Local variables:
- * c-basic-offset: 2
- * End:
- */
diff --git a/main/drd/tests/unit_bitmap.c b/main/drd/tests/unit_bitmap.c
index e48d238..6de61ac 100644
--- a/main/drd/tests/unit_bitmap.c
+++ b/main/drd/tests/unit_bitmap.c
@@ -6,9 +6,11 @@
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
+
+#include "coregrind/m_xarray.c"
+#include "coregrind/m_poolalloc.c"
#include "coregrind/m_oset.c"
#include "drd/drd_bitmap.c"
-#include "drd/drd_bitmap2_node.c"
#include "drd/pub_drd_bitmap.h"
@@ -46,6 +48,8 @@
{ return memset(s, c, sz); }
void* VG_(memcpy)(void *d, const void *s, SizeT sz)
{ return memcpy(d, s, sz); }
+void* VG_(memmove)(void *d, const void *s, SizeT sz)
+{ return memmove(d, s, sz); }
Int VG_(memcmp)(const void* s1, const void* s2, SizeT n)
{ return memcmp(s1, s2, n); }
UInt VG_(printf)(const HChar *format, ...)
@@ -54,7 +58,13 @@
{ UInt ret; va_list vargs; va_start(vargs, format); ret = vprintf(format, vargs); va_end(vargs); printf("\n"); return ret; }
Bool DRD_(is_suppressed)(const Addr a1, const Addr a2)
{ assert(0); }
-
+void VG_(vcbprintf)(void(*char_sink)(HChar, void* opaque),
+ void* opaque,
+ const HChar* format, va_list vargs)
+{ assert(0); }
+void VG_(ssort)( void* base, SizeT nmemb, SizeT size,
+ Int (*compar)(void*, void*) )
+{ assert(0); }
/* Actual unit test */
@@ -335,9 +345,11 @@
fprintf(stderr, "Start of DRD BM unit test.\n");
+ DRD_(bm_module_init)();
bm_test1();
bm_test2();
bm_test3(outer_loop_step, inner_loop_step);
+ DRD_(bm_module_cleanup)();
fprintf(stderr, "End of DRD BM unit test.\n");
diff --git a/main/helgrind/Makefile.in b/main/helgrind/Makefile.in
new file mode 100644
index 0000000..2e31b77
--- /dev/null
+++ b/main/helgrind/Makefile.in
@@ -0,0 +1,1405 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
+ $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+
+# On Android we must ask for non-executable stack, not sure why.
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_2 = -Wl,-z,noexecstack
+noinst_PROGRAMS = helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
+ $(am__EXEEXT_1) \
+ vgpreload_helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
+ $(am__EXEEXT_2)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_3 = helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = vgpreload_helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+subdir = helgrind
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_2 = vgpreload_helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+PROGRAMS = $(noinst_PROGRAMS)
+am__objects_1 = \
+ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.$(OBJEXT)
+am_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = \
+ $(am_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
+am__helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = hg_basics.c \
+ hg_errors.c hg_lock_n_thread.c hg_main.c hg_wordset.c \
+ libhb_core.c
+am__objects_2 = \
+ helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.$(OBJEXT) \
+ helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_2)
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+ $(am_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
+am__objects_3 = vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.$(OBJEXT)
+am_vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = \
+ $(am__objects_3)
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = $(am_vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am__vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES_DIST = \
+ hg_intercepts.c
+am__objects_4 = vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_4)
+vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS = $(am_vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES) \
+ $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES) \
+ $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES)
+DIST_SOURCES = $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(am__helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST) \
+ $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES) \
+ $(am__vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES_DIST)
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
+am__vpath_adj = case $$p in \
+ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
+ *) f=$$p;; \
+ esac;
+am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;
+am__install_max = 40
+am__nobase_strip_setup = \
+ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`
+am__nobase_strip = \
+ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"
+am__nobase_list = $(am__nobase_strip_setup); \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \
+ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \
+ if (++n[$$2] == $(am__install_max)) \
+ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \
+ END { for (dir in files) print dir, files[dir] }'
+am__base_list = \
+ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \
+ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'
+am__installdirs = "$(DESTDIR)$(pkgincludedir)"
+HEADERS = $(noinst_HEADERS) $(pkginclude_HEADERS)
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DIST_SUBDIRS = $(SUBDIRS)
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+SUBDIRS = . tests
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+#----------------------------------------------------------------------------
+# <tool>-<platform> stuff
+#----------------------------------------------------------------------------
+TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+
+TOOL_LDADD_COMMON = -lgcc
+TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) $(TOOL_LDADD_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
+
+
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+ -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_X86_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_AMD64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_PPC32_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_PPC64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_ARM_LINUX = $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
+ $(am__append_2)
+TOOL_LDFLAGS_S390X_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_X86_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386
+
+TOOL_LDFLAGS_AMD64_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+
+
+# MIPS Linux default start symbol is __start, not _start like on x86 or amd
+TOOL_LDFLAGS_MIPS32_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
+ @FLAG_M32@
+
+
+# NB for 64-bit darwin. We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them). Although such setting is probably
+# better done in link_tool_exe.c.
+#
+# -Wl,-pagezero_size,0x100000000
+
+#----------------------------------------------------------------------------
+# vgpreload_<tool>-<platform>.a stuff
+#----------------------------------------------------------------------------
+LIBREPLACEMALLOC_X86_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-linux.a
+
+LIBREPLACEMALLOC_AMD64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-linux.a
+
+LIBREPLACEMALLOC_PPC32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a
+
+LIBREPLACEMALLOC_PPC64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a
+
+LIBREPLACEMALLOC_ARM_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a
+
+LIBREPLACEMALLOC_X86_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-darwin.a
+
+LIBREPLACEMALLOC_AMD64_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-darwin.a
+
+LIBREPLACEMALLOC_S390X_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-s390x-linux.a
+
+LIBREPLACEMALLOC_MIPS32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips32-linux.a
+
+LIBREPLACEMALLOC_LDFLAGS_X86_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_X86_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_AMD64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC32_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_ARM_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_X86_DARWIN = \
+ $(LIBREPLACEMALLOC_X86_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_DARWIN = \
+ $(LIBREPLACEMALLOC_AMD64_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_S390X_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_S390X_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_MIPS32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_MIPS32_LINUX) \
+ -Wl,--no-whole-archive
+
+EXTRA_DIST = \
+ docs/hg-manual.xml \
+ README_MSMProp2.txt \
+ README_YARD.txt
+
+
+#----------------------------------------------------------------------------
+# Headers, etc
+#----------------------------------------------------------------------------
+pkginclude_HEADERS = helgrind.h
+noinst_HEADERS = \
+ hg_basics.h \
+ hg_errors.h \
+ hg_lock_n_thread.h \
+ hg_wordset.h \
+ libhb.h
+
+HELGRIND_SOURCES_COMMON = \
+ hg_basics.c \
+ hg_errors.c \
+ hg_lock_n_thread.c \
+ hg_main.c \
+ hg_wordset.c \
+ libhb_core.c
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+ $(HELGRIND_SOURCES_COMMON)
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) -O2
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@)
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
+ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
+ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+ @VALT_LOAD_ADDRESS_PRI@ \
+ $(LINK) \
+ $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+ $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(HELGRIND_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) -O2
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
+VGPRELOAD_HELGRIND_SOURCES_COMMON = hg_intercepts.c
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \
+ $(VGPRELOAD_HELGRIND_SOURCES_COMMON)
+
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(AM_CFLAGS_PIC)
+
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \
+ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_PRI_CAPS@)
+
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
+ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
+ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(VGPRELOAD_HELGRIND_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) $(AM_CFLAGS_PIC)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign helgrind/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign helgrind/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-noinstPROGRAMS:
+ -test -z "$(noinst_PROGRAMS)" || rm -f $(noinst_PROGRAMS)
+helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT): $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT)
+ $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD) $(LIBS)
+helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT): $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+ $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD) $(LIBS)
+vgpreload_helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD) $(LIBS)
+vgpreload_helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.o: hg_basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.o `test -f 'hg_basics.c' || echo '$(srcdir)/'`hg_basics.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_basics.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.o `test -f 'hg_basics.c' || echo '$(srcdir)/'`hg_basics.c
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.obj: hg_basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.obj `if test -f 'hg_basics.c'; then $(CYGPATH_W) 'hg_basics.c'; else $(CYGPATH_W) '$(srcdir)/hg_basics.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_basics.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_basics.obj `if test -f 'hg_basics.c'; then $(CYGPATH_W) 'hg_basics.c'; else $(CYGPATH_W) '$(srcdir)/hg_basics.c'; fi`
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.o: hg_errors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.o `test -f 'hg_errors.c' || echo '$(srcdir)/'`hg_errors.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_errors.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.o `test -f 'hg_errors.c' || echo '$(srcdir)/'`hg_errors.c
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.obj: hg_errors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.obj `if test -f 'hg_errors.c'; then $(CYGPATH_W) 'hg_errors.c'; else $(CYGPATH_W) '$(srcdir)/hg_errors.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_errors.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_errors.obj `if test -f 'hg_errors.c'; then $(CYGPATH_W) 'hg_errors.c'; else $(CYGPATH_W) '$(srcdir)/hg_errors.c'; fi`
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.o: hg_lock_n_thread.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.o `test -f 'hg_lock_n_thread.c' || echo '$(srcdir)/'`hg_lock_n_thread.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_lock_n_thread.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.o `test -f 'hg_lock_n_thread.c' || echo '$(srcdir)/'`hg_lock_n_thread.c
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.obj: hg_lock_n_thread.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.obj `if test -f 'hg_lock_n_thread.c'; then $(CYGPATH_W) 'hg_lock_n_thread.c'; else $(CYGPATH_W) '$(srcdir)/hg_lock_n_thread.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_lock_n_thread.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_lock_n_thread.obj `if test -f 'hg_lock_n_thread.c'; then $(CYGPATH_W) 'hg_lock_n_thread.c'; else $(CYGPATH_W) '$(srcdir)/hg_lock_n_thread.c'; fi`
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.o: hg_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.o `test -f 'hg_main.c' || echo '$(srcdir)/'`hg_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_main.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.o `test -f 'hg_main.c' || echo '$(srcdir)/'`hg_main.c
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.obj: hg_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.obj `if test -f 'hg_main.c'; then $(CYGPATH_W) 'hg_main.c'; else $(CYGPATH_W) '$(srcdir)/hg_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_main.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_main.obj `if test -f 'hg_main.c'; then $(CYGPATH_W) 'hg_main.c'; else $(CYGPATH_W) '$(srcdir)/hg_main.c'; fi`
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.o: hg_wordset.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.o `test -f 'hg_wordset.c' || echo '$(srcdir)/'`hg_wordset.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_wordset.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.o `test -f 'hg_wordset.c' || echo '$(srcdir)/'`hg_wordset.c
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.obj: hg_wordset.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.obj `if test -f 'hg_wordset.c'; then $(CYGPATH_W) 'hg_wordset.c'; else $(CYGPATH_W) '$(srcdir)/hg_wordset.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_wordset.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-hg_wordset.obj `if test -f 'hg_wordset.c'; then $(CYGPATH_W) 'hg_wordset.c'; else $(CYGPATH_W) '$(srcdir)/hg_wordset.c'; fi`
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.o: libhb_core.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.o `test -f 'libhb_core.c' || echo '$(srcdir)/'`libhb_core.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='libhb_core.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.o `test -f 'libhb_core.c' || echo '$(srcdir)/'`libhb_core.c
+
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.obj: libhb_core.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.Tpo -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.obj `if test -f 'libhb_core.c'; then $(CYGPATH_W) 'libhb_core.c'; else $(CYGPATH_W) '$(srcdir)/libhb_core.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='libhb_core.c' object='helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-libhb_core.obj `if test -f 'libhb_core.c'; then $(CYGPATH_W) 'libhb_core.c'; else $(CYGPATH_W) '$(srcdir)/libhb_core.c'; fi`
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.o: hg_basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.o `test -f 'hg_basics.c' || echo '$(srcdir)/'`hg_basics.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_basics.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.o `test -f 'hg_basics.c' || echo '$(srcdir)/'`hg_basics.c
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.obj: hg_basics.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.obj `if test -f 'hg_basics.c'; then $(CYGPATH_W) 'hg_basics.c'; else $(CYGPATH_W) '$(srcdir)/hg_basics.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_basics.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_basics.obj `if test -f 'hg_basics.c'; then $(CYGPATH_W) 'hg_basics.c'; else $(CYGPATH_W) '$(srcdir)/hg_basics.c'; fi`
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.o: hg_errors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.o `test -f 'hg_errors.c' || echo '$(srcdir)/'`hg_errors.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_errors.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.o `test -f 'hg_errors.c' || echo '$(srcdir)/'`hg_errors.c
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.obj: hg_errors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.obj `if test -f 'hg_errors.c'; then $(CYGPATH_W) 'hg_errors.c'; else $(CYGPATH_W) '$(srcdir)/hg_errors.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_errors.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_errors.obj `if test -f 'hg_errors.c'; then $(CYGPATH_W) 'hg_errors.c'; else $(CYGPATH_W) '$(srcdir)/hg_errors.c'; fi`
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.o: hg_lock_n_thread.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.o `test -f 'hg_lock_n_thread.c' || echo '$(srcdir)/'`hg_lock_n_thread.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_lock_n_thread.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.o `test -f 'hg_lock_n_thread.c' || echo '$(srcdir)/'`hg_lock_n_thread.c
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.obj: hg_lock_n_thread.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.obj `if test -f 'hg_lock_n_thread.c'; then $(CYGPATH_W) 'hg_lock_n_thread.c'; else $(CYGPATH_W) '$(srcdir)/hg_lock_n_thread.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_lock_n_thread.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_lock_n_thread.obj `if test -f 'hg_lock_n_thread.c'; then $(CYGPATH_W) 'hg_lock_n_thread.c'; else $(CYGPATH_W) '$(srcdir)/hg_lock_n_thread.c'; fi`
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.o: hg_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.o `test -f 'hg_main.c' || echo '$(srcdir)/'`hg_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_main.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.o `test -f 'hg_main.c' || echo '$(srcdir)/'`hg_main.c
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.obj: hg_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.obj `if test -f 'hg_main.c'; then $(CYGPATH_W) 'hg_main.c'; else $(CYGPATH_W) '$(srcdir)/hg_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_main.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_main.obj `if test -f 'hg_main.c'; then $(CYGPATH_W) 'hg_main.c'; else $(CYGPATH_W) '$(srcdir)/hg_main.c'; fi`
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.o: hg_wordset.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.o `test -f 'hg_wordset.c' || echo '$(srcdir)/'`hg_wordset.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_wordset.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.o `test -f 'hg_wordset.c' || echo '$(srcdir)/'`hg_wordset.c
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.obj: hg_wordset.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.obj `if test -f 'hg_wordset.c'; then $(CYGPATH_W) 'hg_wordset.c'; else $(CYGPATH_W) '$(srcdir)/hg_wordset.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_wordset.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-hg_wordset.obj `if test -f 'hg_wordset.c'; then $(CYGPATH_W) 'hg_wordset.c'; else $(CYGPATH_W) '$(srcdir)/hg_wordset.c'; fi`
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.o: libhb_core.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.o -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.o `test -f 'libhb_core.c' || echo '$(srcdir)/'`libhb_core.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='libhb_core.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.o `test -f 'libhb_core.c' || echo '$(srcdir)/'`libhb_core.c
+
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.obj: libhb_core.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.obj -MD -MP -MF $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.Tpo -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.obj `if test -f 'libhb_core.c'; then $(CYGPATH_W) 'libhb_core.c'; else $(CYGPATH_W) '$(srcdir)/libhb_core.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.Tpo $(DEPDIR)/helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='libhb_core.c' object='helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-libhb_core.obj `if test -f 'libhb_core.c'; then $(CYGPATH_W) 'libhb_core.c'; else $(CYGPATH_W) '$(srcdir)/libhb_core.c'; fi`
+
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.o: hg_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.Tpo -c -o vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.o `test -f 'hg_intercepts.c' || echo '$(srcdir)/'`hg_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.Tpo $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_intercepts.c' object='vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.o `test -f 'hg_intercepts.c' || echo '$(srcdir)/'`hg_intercepts.c
+
+vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.obj: hg_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.Tpo -c -o vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.obj `if test -f 'hg_intercepts.c'; then $(CYGPATH_W) 'hg_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/hg_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.Tpo $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_intercepts.c' object='vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.obj `if test -f 'hg_intercepts.c'; then $(CYGPATH_W) 'hg_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/hg_intercepts.c'; fi`
+
+vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.o: hg_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.o -MD -MP -MF $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.Tpo -c -o vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.o `test -f 'hg_intercepts.c' || echo '$(srcdir)/'`hg_intercepts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.Tpo $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_intercepts.c' object='vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.o `test -f 'hg_intercepts.c' || echo '$(srcdir)/'`hg_intercepts.c
+
+vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.obj: hg_intercepts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.obj -MD -MP -MF $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.Tpo -c -o vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.obj `if test -f 'hg_intercepts.c'; then $(CYGPATH_W) 'hg_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/hg_intercepts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.Tpo $(DEPDIR)/vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='hg_intercepts.c' object='vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-hg_intercepts.obj `if test -f 'hg_intercepts.c'; then $(CYGPATH_W) 'hg_intercepts.c'; else $(CYGPATH_W) '$(srcdir)/hg_intercepts.c'; fi`
+install-pkgincludeHEADERS: $(pkginclude_HEADERS)
+ @$(NORMAL_INSTALL)
+ test -z "$(pkgincludedir)" || $(MKDIR_P) "$(DESTDIR)$(pkgincludedir)"
+ @list='$(pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ for p in $$list; do \
+ if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+ echo "$$d$$p"; \
+ done | $(am__base_list) | \
+ while read files; do \
+ echo " $(INSTALL_HEADER) $$files '$(DESTDIR)$(pkgincludedir)'"; \
+ $(INSTALL_HEADER) $$files "$(DESTDIR)$(pkgincludedir)" || exit $$?; \
+ done
+
+uninstall-pkgincludeHEADERS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
+ test -n "$$files" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(pkgincludedir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(pkgincludedir)" && rm -f $$files
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+check: check-recursive
+all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
+installdirs: installdirs-recursive
+installdirs-am:
+ for dir in "$(DESTDIR)$(pkgincludedir)"; do \
+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ done
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-generic clean-local clean-noinstPROGRAMS \
+ mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am: install-pkgincludeHEADERS
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am: install-exec-local
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am: uninstall-pkgincludeHEADERS
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+ install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am all-local check check-am clean clean-generic \
+ clean-local clean-noinstPROGRAMS ctags ctags-recursive \
+ distclean distclean-compile distclean-generic distclean-tags \
+ distdir dvi dvi-am html html-am info info-am install \
+ install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-exec-local \
+ install-html install-html-am install-info install-info-am \
+ install-man install-pdf install-pdf-am \
+ install-pkgincludeHEADERS install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ installdirs-am maintainer-clean maintainer-clean-generic \
+ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \
+ ps ps-am tags tags-recursive uninstall uninstall-am \
+ uninstall-pkgincludeHEADERS
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+#----------------------------------------------------------------------------
+# General stuff
+#----------------------------------------------------------------------------
+
+all-local: inplace-noinst_PROGRAMS inplace-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/helgrind/docs/hg-manual.xml b/main/helgrind/docs/hg-manual.xml
index 043e26c..a2c58a9 100644
--- a/main/helgrind/docs/hg-manual.xml
+++ b/main/helgrind/docs/hg-manual.xml
@@ -656,7 +656,9 @@
"<computeroutput>This conflicts with a previous
write</computeroutput>". This shows a previous access which also
accessed the stated address, and which is believed to be racing
-against the access in the first call stack.</para>
+against the access in the first call stack. Note that this second
+call stack is limited to a maximum of 8 entries to limit the
+memory usage.</para>
<para>Finally, Helgrind may attempt to give a description of the
raced-on address in source level terms. In this example, it
@@ -1099,7 +1101,9 @@
Helgrind collects enough information about "old" accesses that
it can produce two stack traces in a race report -- both the
stack trace for the current access, and the trace for the
- older, conflicting access.</para>
+ older, conflicting access. To limit memory usage, "old" accesses
+ stack traces are limited to a maximum of 8 entries, even if
+ <option>--num-callers</option> value is bigger.</para>
<para>Collecting such information is expensive in both speed and
memory, particularly for programs that do many inter-thread
synchronisation events (locks, unlocks, etc). Without such
diff --git a/main/helgrind/helgrind.h b/main/helgrind/helgrind.h
index 8645866..9fd203b 100644
--- a/main/helgrind/helgrind.h
+++ b/main/helgrind/helgrind.h
@@ -11,7 +11,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks LLP
+ Copyright (C) 2007-2012 OpenWorks LLP
info@open-works.co.uk
Redistribution and use in source and binary forms, with or without
@@ -603,7 +603,7 @@
/* Same as ANNOTATE_BENIGN_RACE(address, description), but applies to
the memory range [address, address+size). */
#define ANNOTATE_BENIGN_RACE_SIZED(address, size, description) \
- _HG_CLIENTREQ_UNIMP("ANNOTATE_BENIGN_RACE_SIZED")
+ VALGRIND_HG_DISABLE_CHECKING(address, size)
/* Request the analysis tool to ignore all reads in the current thread
until ANNOTATE_IGNORE_READS_END is called. Useful to ignore
diff --git a/main/helgrind/hg_basics.c b/main/helgrind/hg_basics.c
index c4afc46..fdb935d 100644
--- a/main/helgrind/hg_basics.c
+++ b/main/helgrind/hg_basics.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks Ltd
+ Copyright (C) 2007-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/helgrind/hg_basics.h b/main/helgrind/hg_basics.h
index d5585e2..aba074b 100644
--- a/main/helgrind/hg_basics.h
+++ b/main/helgrind/hg_basics.h
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks Ltd
+ Copyright (C) 2007-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/helgrind/hg_errors.c b/main/helgrind/hg_errors.c
index abe3a0d..1d7d50e 100644
--- a/main/helgrind/hg_errors.c
+++ b/main/helgrind/hg_errors.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks Ltd
+ Copyright (C) 2007-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/helgrind/hg_errors.h b/main/helgrind/hg_errors.h
index 91f00d5..e5abb35 100644
--- a/main/helgrind/hg_errors.h
+++ b/main/helgrind/hg_errors.h
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks Ltd
+ Copyright (C) 2007-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/helgrind/hg_intercepts.c b/main/helgrind/hg_intercepts.c
index 206221e..ba44b6b 100644
--- a/main/helgrind/hg_intercepts.c
+++ b/main/helgrind/hg_intercepts.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks LLP
+ Copyright (C) 2007-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -2450,8 +2450,14 @@
http://bugs.kde.org/show_bug.cgi?id=139776
*/
MEMCPY(NONE, _intel_fast_memcpy)
+
#elif defined(VGO_darwin)
- MEMCPY(VG_Z_LIBC_SONAME, memcpy)
+# if DARWIN_VERS <= DARWIN_10_6
+ MEMCPY(VG_Z_LIBC_SONAME, memcpy)
+# endif
+ MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse3x) /* memcpy$VARIANT$sse3x */
+ MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse42) /* memcpy$VARIANT$sse42 */
+
#endif
diff --git a/main/helgrind/hg_lock_n_thread.c b/main/helgrind/hg_lock_n_thread.c
index 5509907..5316ab2 100644
--- a/main/helgrind/hg_lock_n_thread.c
+++ b/main/helgrind/hg_lock_n_thread.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks Ltd
+ Copyright (C) 2007-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/helgrind/hg_lock_n_thread.h b/main/helgrind/hg_lock_n_thread.h
index 4579891..7f8524f 100644
--- a/main/helgrind/hg_lock_n_thread.h
+++ b/main/helgrind/hg_lock_n_thread.h
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks Ltd
+ Copyright (C) 2007-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/helgrind/hg_main.c b/main/helgrind/hg_main.c
index c1324db..ca9745a 100644
--- a/main/helgrind/hg_main.c
+++ b/main/helgrind/hg_main.c
@@ -8,10 +8,10 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks LLP
+ Copyright (C) 2007-2012 OpenWorks LLP
info@open-works.co.uk
- Copyright (C) 2007-2011 Apple, Inc.
+ Copyright (C) 2007-2012 Apple, Inc.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -102,7 +102,7 @@
static void all__sanity_check ( Char* who ); /* fwds */
-#define HG_CLI__MALLOC_REDZONE_SZB 16 /* let's say */
+#define HG_CLI__DEFAULT_MALLOC_REDZONE_SZB 16 /* let's say */
// 0 for none, 1 for dump at end of run
#define SHOW_DATA_STRUCTURES 0
@@ -2139,17 +2139,41 @@
}
}
-static void map_cond_to_CVInfo_delete ( void* cond ) {
+static CVInfo* map_cond_to_CVInfo_lookup_NO_alloc ( void* cond ) {
+ UWord key, val;
+ map_cond_to_CVInfo_INIT();
+ if (VG_(lookupFM)( map_cond_to_CVInfo, &key, &val, (UWord)cond )) {
+ tl_assert(key == (UWord)cond);
+ return (CVInfo*)val;
+ } else {
+ return NULL;
+ }
+}
+
+static void map_cond_to_CVInfo_delete ( ThreadId tid, void* cond ) {
+ Thread* thr;
UWord keyW, valW;
+
+ thr = map_threads_maybe_lookup( tid );
+ tl_assert(thr); /* cannot fail - Thread* must already exist */
+
map_cond_to_CVInfo_INIT();
if (VG_(delFromFM)( map_cond_to_CVInfo, &keyW, &valW, (UWord)cond )) {
CVInfo* cvi = (CVInfo*)valW;
tl_assert(keyW == (UWord)cond);
tl_assert(cvi);
tl_assert(cvi->so);
+ if (cvi->nWaiters > 0) {
+ HG_(record_error_Misc)(thr,
+ "pthread_cond_destroy:"
+ " destruction of condition variable being waited upon");
+ }
libhb_so_dealloc(cvi->so);
cvi->mx_ga = 0;
HG_(free)(cvi);
+ } else {
+ HG_(record_error_Misc)(thr,
+ "pthread_cond_destroy: destruction of unknown cond var");
}
}
@@ -2320,7 +2344,17 @@
// error-if: cond is also associated with a different mutex
- cvi = map_cond_to_CVInfo_lookup_or_alloc( cond );
+ cvi = map_cond_to_CVInfo_lookup_NO_alloc( cond );
+ if (!cvi) {
+ /* This could be either a bug in helgrind or the guest application
+ that did an error (e.g. cond var was destroyed by another thread.
+ Let's assume helgrind is perfect ...
+ Note that this is similar to drd behaviour. */
+ HG_(record_error_Misc)(thr, "condition variable has been destroyed while"
+ " being waited upon");
+ return;
+ }
+
tl_assert(cvi);
tl_assert(cvi->so);
tl_assert(cvi->nWaiters > 0);
@@ -2351,7 +2385,7 @@
"(ctid=%d, cond=%p)\n",
(Int)tid, (void*)cond );
- map_cond_to_CVInfo_delete( cond );
+ map_cond_to_CVInfo_delete( tid, cond );
}
@@ -4317,6 +4351,7 @@
bbOut->tyenv = deepCopyIRTypeEnv(bbIn->tyenv);
bbOut->next = deepCopyIRExpr(bbIn->next);
bbOut->jumpkind = bbIn->jumpkind;
+ bbOut->offsIP = bbIn->offsIP;
// Copy verbatim any IR preamble preceding the first IMark
i = 0;
@@ -5083,7 +5118,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a thread error detector");
VG_(details_copyright_author)(
- "Copyright (C) 2007-2011, and GNU GPL'd, by OpenWorks LLP et al.");
+ "Copyright (C) 2007-2012, and GNU GPL'd, by OpenWorks LLP et al.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 320 );
@@ -5124,7 +5159,7 @@
hg_cli____builtin_vec_delete,
hg_cli__realloc,
hg_cli_malloc_usable_size,
- HG_CLI__MALLOC_REDZONE_SZB );
+ HG_CLI__DEFAULT_MALLOC_REDZONE_SZB );
/* 21 Dec 08: disabled this; it mostly causes H to start more
slowly and use significantly more memory, without very often
diff --git a/main/helgrind/hg_wordset.c b/main/helgrind/hg_wordset.c
index ef76c80..5e14a62 100644
--- a/main/helgrind/hg_wordset.c
+++ b/main/helgrind/hg_wordset.c
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks LLP
+ Copyright (C) 2007-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/helgrind/hg_wordset.h b/main/helgrind/hg_wordset.h
index 7f96988..c918d7c 100644
--- a/main/helgrind/hg_wordset.h
+++ b/main/helgrind/hg_wordset.h
@@ -8,7 +8,7 @@
This file is part of Helgrind, a Valgrind tool for detecting errors
in threaded programs.
- Copyright (C) 2007-2011 OpenWorks LLP
+ Copyright (C) 2007-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/helgrind/libhb.h b/main/helgrind/libhb.h
index 51ec2c8..589b789 100644
--- a/main/helgrind/libhb.h
+++ b/main/helgrind/libhb.h
@@ -9,7 +9,7 @@
This file is part of LibHB, a library for implementing and checking
the happens-before relationship in concurrent programs.
- Copyright (C) 2008-2011 OpenWorks Ltd
+ Copyright (C) 2008-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/helgrind/libhb_core.c b/main/helgrind/libhb_core.c
index 9be904e..41636b1 100644
--- a/main/helgrind/libhb_core.c
+++ b/main/helgrind/libhb_core.c
@@ -9,7 +9,7 @@
This file is part of LibHB, a library for implementing and checking
the happens-before relationship in concurrent programs.
- Copyright (C) 2008-2011 OpenWorks Ltd
+ Copyright (C) 2008-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -31,6 +31,7 @@
*/
#include "pub_tool_basics.h"
+#include "pub_tool_poolalloc.h"
#include "pub_tool_libcassert.h"
#include "pub_tool_libcbase.h"
#include "pub_tool_libcprint.h"
@@ -3814,108 +3815,6 @@
/////////////////////////////////////////////////////////
// //
-// A simple group (memory) allocator //
-// //
-/////////////////////////////////////////////////////////
-
-//////////////// BEGIN general group allocator
-typedef
- struct {
- UWord elemSzB; /* element size */
- UWord nPerGroup; /* # elems per group */
- void* (*alloc)(HChar*, SizeT); /* group allocator */
- HChar* cc; /* group allocator's cc */
- void (*free)(void*); /* group allocator's free-er (unused) */
- /* XArray of void* (pointers to groups). The groups themselves.
- Each element is a pointer to a block of size (elemSzB *
- nPerGroup) bytes. */
- XArray* groups;
- /* next free element. Is a pointer to an element in one of the
- groups pointed to by .groups. */
- void* nextFree;
- }
- GroupAlloc;
-
-static void init_GroupAlloc ( /*MOD*/GroupAlloc* ga,
- UWord elemSzB,
- UWord nPerGroup,
- void* (*alloc)(HChar*, SizeT),
- HChar* cc,
- void (*free)(void*) )
-{
- tl_assert(0 == (elemSzB % sizeof(UWord)));
- tl_assert(elemSzB >= sizeof(UWord));
- tl_assert(nPerGroup >= 100); /* let's say */
- tl_assert(alloc);
- tl_assert(cc);
- tl_assert(free);
- tl_assert(ga);
- VG_(memset)(ga, 0, sizeof(*ga));
- ga->elemSzB = elemSzB;
- ga->nPerGroup = nPerGroup;
- ga->groups = NULL;
- ga->alloc = alloc;
- ga->cc = cc;
- ga->free = free;
- ga->groups = VG_(newXA)( alloc, cc, free, sizeof(void*) );
- ga->nextFree = NULL;
- tl_assert(ga->groups);
-}
-
-/* The freelist is empty. Allocate a new group and put all the new
- elements in it onto the freelist. */
-__attribute__((noinline))
-static void gal_add_new_group ( GroupAlloc* ga )
-{
- Word i;
- UWord* group;
- tl_assert(ga);
- tl_assert(ga->nextFree == NULL);
- group = ga->alloc( ga->cc, ga->elemSzB * ga->nPerGroup );
- tl_assert(group);
- /* extend the freelist through the new group. Place the freelist
- pointer in the first word of each element. That's why the
- element size must be at least one word. */
- for (i = ga->nPerGroup-1; i >= 0; i--) {
- UChar* elemC = ((UChar*)group) + i * ga->elemSzB;
- UWord* elem = (UWord*)elemC;
- tl_assert(0 == (((UWord)elem) % sizeof(UWord)));
- *elem = (UWord)ga->nextFree;
- ga->nextFree = elem;
- }
- /* and add to our collection of groups */
- VG_(addToXA)( ga->groups, &group );
-}
-
-inline static void* gal_Alloc ( GroupAlloc* ga )
-{
- UWord* elem;
- if (UNLIKELY(ga->nextFree == NULL)) {
- gal_add_new_group(ga);
- }
- elem = ga->nextFree;
- ga->nextFree = (void*)*elem;
- *elem = 0; /* unnecessary, but just to be on the safe side */
- return elem;
-}
-
-inline static void* gal_Alloc_w_size_check ( GroupAlloc* ga, SizeT n )
-{
- tl_assert(n == ga->elemSzB);
- return gal_Alloc( ga );
-}
-
-inline static void gal_Free ( GroupAlloc* ga, void* p )
-{
- UWord* elem = (UWord*)p;
- *elem = (UWord)ga->nextFree;
- ga->nextFree = elem;
-}
-//////////////// END general group allocator
-
-
-/////////////////////////////////////////////////////////
-// //
// Change-event map2 //
// //
/////////////////////////////////////////////////////////
@@ -3962,7 +3861,7 @@
Investigations also suggest this is very workload and scheduling
sensitive. Therefore a dynamic sizing would be better.
- However, dynamic sizing would defeat the use of a GroupAllocator
+ However, dynamic sizing would defeat the use of a PoolAllocator
for OldRef structures. And that's important for performance. So
it's not straightforward to do.
*/
@@ -4039,18 +3938,18 @@
}
-//////////// BEGIN RCEC group allocator
-static GroupAlloc rcec_group_allocator;
+//////////// BEGIN RCEC pool allocator
+static PoolAlloc* rcec_pool_allocator;
static RCEC* alloc_RCEC ( void ) {
- return gal_Alloc ( &rcec_group_allocator );
+ return VG_(allocEltPA) ( rcec_pool_allocator );
}
static void free_RCEC ( RCEC* rcec ) {
tl_assert(rcec->magic == RCEC_MAGIC);
- gal_Free( &rcec_group_allocator, rcec );
+ VG_(freeEltPA)( rcec_pool_allocator, rcec );
}
-//////////// END RCEC group allocator
+//////////// END RCEC pool allocator
/* Find 'ec' in the RCEC list whose head pointer lives at 'headp' and
@@ -4203,18 +4102,18 @@
OldRef;
-//////////// BEGIN OldRef group allocator
-static GroupAlloc oldref_group_allocator;
+//////////// BEGIN OldRef pool allocator
+static PoolAlloc* oldref_pool_allocator;
static OldRef* alloc_OldRef ( void ) {
- return gal_Alloc ( &oldref_group_allocator );
+ return VG_(allocEltPA) ( oldref_pool_allocator );
}
static void free_OldRef ( OldRef* r ) {
tl_assert(r->magic == OldRef_MAGIC);
- gal_Free( &oldref_group_allocator, r );
+ VG_(freeEltPA)( oldref_pool_allocator, r );
}
-//////////// END OldRef group allocator
+//////////// END OldRef pool allocator
static SparseWA* oldrefTree = NULL; /* SparseWA* OldRef* */
@@ -4499,13 +4398,14 @@
{
Word i;
- /* Context (RCEC) group allocator */
- init_GroupAlloc ( &rcec_group_allocator,
- sizeof(RCEC),
- 1000 /* RCECs per group */,
- HG_(zalloc),
- "libhb.event_map_init.1 (RCEC groups)",
- HG_(free) );
+ /* Context (RCEC) pool allocator */
+ rcec_pool_allocator = VG_(newPA) (
+ sizeof(RCEC),
+ 1000 /* RCECs per pool */,
+ HG_(zalloc),
+ "libhb.event_map_init.1 (RCEC pools)",
+ HG_(free)
+ );
/* Context table */
tl_assert(!contextTab);
@@ -4515,13 +4415,14 @@
for (i = 0; i < N_RCEC_TAB; i++)
contextTab[i] = NULL;
- /* Oldref group allocator */
- init_GroupAlloc ( &oldref_group_allocator,
- sizeof(OldRef),
- 1000 /* OldRefs per group */,
- HG_(zalloc),
- "libhb.event_map_init.3 (OldRef groups)",
- HG_(free) );
+ /* Oldref pool allocator */
+ oldref_pool_allocator = VG_(newPA)(
+ sizeof(OldRef),
+ 1000 /* OldRefs per pool */,
+ HG_(zalloc),
+ "libhb.event_map_init.3 (OldRef pools)",
+ HG_(free)
+ );
/* Oldref tree */
tl_assert(!oldrefTree);
diff --git a/main/helgrind/tests/Makefile.am b/main/helgrind/tests/Makefile.am
index 3271a54..77c17f5 100644
--- a/main/helgrind/tests/Makefile.am
+++ b/main/helgrind/tests/Makefile.am
@@ -40,6 +40,8 @@
pth_barrier1.vgtest pth_barrier1.stdout.exp pth_barrier1.stderr.exp \
pth_barrier2.vgtest pth_barrier2.stdout.exp pth_barrier2.stderr.exp \
pth_barrier3.vgtest pth_barrier3.stdout.exp pth_barrier3.stderr.exp \
+ pth_destroy_cond.vgtest \
+ pth_destroy_cond.stdout.exp pth_destroy_cond.stderr.exp \
pth_spinlock.vgtest pth_spinlock.stdout.exp pth_spinlock.stderr.exp \
rwlock_race.vgtest rwlock_race.stdout.exp rwlock_race.stderr.exp \
rwlock_test.vgtest rwlock_test.stdout.exp rwlock_test.stderr.exp \
@@ -106,6 +108,7 @@
locked_vs_unlocked1 \
locked_vs_unlocked2 \
locked_vs_unlocked3 \
+ pth_destroy_cond \
t2t \
tc01_simple_race \
tc02_simple_tls \
@@ -185,8 +188,3 @@
else
annotate_hbefore_CFLAGS = $(AM_CFLAGS)
endif
-
-if VGCONF_OS_IS_LINUX
-cond_timedwait_invalid_LDADD = -lrt
-endif
-
diff --git a/main/helgrind/tests/Makefile.in b/main/helgrind/tests/Makefile.in
new file mode 100644
index 0000000..193c071
--- /dev/null
+++ b/main/helgrind/tests/Makefile.in
@@ -0,0 +1,1236 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = annotate_hbefore$(EXEEXT) \
+ cond_timedwait_invalid$(EXEEXT) free_is_write$(EXEEXT) \
+ hg01_all_ok$(EXEEXT) hg02_deadlock$(EXEEXT) \
+ hg03_inherit$(EXEEXT) hg04_race$(EXEEXT) hg05_race2$(EXEEXT) \
+ hg06_readshared$(EXEEXT) locked_vs_unlocked1$(EXEEXT) \
+ locked_vs_unlocked2$(EXEEXT) locked_vs_unlocked3$(EXEEXT) \
+ pth_destroy_cond$(EXEEXT) t2t$(EXEEXT) \
+ tc01_simple_race$(EXEEXT) tc02_simple_tls$(EXEEXT) \
+ tc03_re_excl$(EXEEXT) tc04_free_lock$(EXEEXT) \
+ tc05_simple_race$(EXEEXT) tc06_two_races$(EXEEXT) \
+ tc07_hbl1$(EXEEXT) tc08_hbl2$(EXEEXT) tc09_bad_unlock$(EXEEXT) \
+ tc10_rec_lock$(EXEEXT) tc11_XCHG$(EXEEXT) \
+ tc12_rwl_trivial$(EXEEXT) tc13_laog1$(EXEEXT) \
+ tc14_laog_dinphils$(EXEEXT) tc15_laog_lockdel$(EXEEXT) \
+ tc16_byterace$(EXEEXT) tc17_sembar$(EXEEXT) \
+ tc18_semabuse$(EXEEXT) tc19_shadowmem$(EXEEXT) \
+ tc21_pthonce$(EXEEXT) tc23_bogus_condwait$(EXEEXT) \
+ tc24_nonzero_sem$(EXEEXT) $(am__EXEEXT_1) $(am__EXEEXT_2) \
+ $(am__EXEEXT_3) $(am__EXEEXT_4)
+
+# DDD: it seg faults, and then the Valgrind exit path hangs
+# JRS 29 July 09: it craps out in the stack unwinder, in
+#==13480== at 0xF00B81FF: ??? f00b8180 VG_(get_StackTrace_wrk)
+#==13480== by 0xF00B83F8: ??? f00b8340 VG_(get_StackTrace)
+#==13480== by 0xF009FE19: ??? f009fd70 record_ExeContext_wrk
+#==13480== by 0xF009D92E: ??? f009d8c0 construct_error
+#==13480== by 0xF009F001: ??? f009eef0 VG_(maybe_record_error)
+#==13480== by 0xF0081F80: ??? f0081f00 HG_(record_error_misc)
+#==13480== by 0xF0089C00: ??? f0089b80 evh__pre_thread_ll_exit
+#==13480== by 0xF01111D1: ??? f0111070 run_a_thread_NORETURN
+#==13480== by 0xF0111512: ??? f0111500 start_thread_NORETURN
+# when the thread being unwound is at __bsdthread_terminate+0
+#
+# Like Tom says, the stack unwinder protection is bollocks.
+# We should junk all previous schemes and simply get the
+# stack unwinder to consult aspacem at each frame (cache-accelerated,
+# of course) to check each page it visits is accessible.
+#
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_FALSE@am__append_3 = \
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_FALSE@ tc22_exit_w_lock
+
+@HAVE_PTHREAD_BARRIER_TRUE@am__append_4 = bar_bad bar_trivial
+@HAVE_PTHREAD_MUTEX_TIMEDLOCK_TRUE@am__append_5 = tc20_verifywrap
+@HAVE_BUILTIN_ATOMIC_TRUE@am__append_6 = annotate_rwlock
+subdir = helgrind/tests
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_FALSE@am__EXEEXT_1 = tc22_exit_w_lock$(EXEEXT)
+@HAVE_PTHREAD_BARRIER_TRUE@am__EXEEXT_2 = bar_bad$(EXEEXT) \
+@HAVE_PTHREAD_BARRIER_TRUE@ bar_trivial$(EXEEXT)
+@HAVE_PTHREAD_MUTEX_TIMEDLOCK_TRUE@am__EXEEXT_3 = \
+@HAVE_PTHREAD_MUTEX_TIMEDLOCK_TRUE@ tc20_verifywrap$(EXEEXT)
+@HAVE_BUILTIN_ATOMIC_TRUE@am__EXEEXT_4 = annotate_rwlock$(EXEEXT)
+annotate_hbefore_SOURCES = annotate_hbefore.c
+annotate_hbefore_OBJECTS = \
+ annotate_hbefore-annotate_hbefore.$(OBJEXT)
+annotate_hbefore_LDADD = $(LDADD)
+annotate_hbefore_DEPENDENCIES =
+annotate_hbefore_LINK = $(CCLD) $(annotate_hbefore_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+annotate_rwlock_SOURCES = annotate_rwlock.c
+annotate_rwlock_OBJECTS = annotate_rwlock.$(OBJEXT)
+annotate_rwlock_LDADD = $(LDADD)
+annotate_rwlock_DEPENDENCIES =
+bar_bad_SOURCES = bar_bad.c
+bar_bad_OBJECTS = bar_bad.$(OBJEXT)
+bar_bad_LDADD = $(LDADD)
+bar_bad_DEPENDENCIES =
+bar_trivial_SOURCES = bar_trivial.c
+bar_trivial_OBJECTS = bar_trivial.$(OBJEXT)
+bar_trivial_LDADD = $(LDADD)
+bar_trivial_DEPENDENCIES =
+cond_timedwait_invalid_SOURCES = cond_timedwait_invalid.c
+cond_timedwait_invalid_OBJECTS = cond_timedwait_invalid.$(OBJEXT)
+cond_timedwait_invalid_LDADD = $(LDADD)
+cond_timedwait_invalid_DEPENDENCIES =
+free_is_write_SOURCES = free_is_write.c
+free_is_write_OBJECTS = free_is_write.$(OBJEXT)
+free_is_write_LDADD = $(LDADD)
+free_is_write_DEPENDENCIES =
+hg01_all_ok_SOURCES = hg01_all_ok.c
+hg01_all_ok_OBJECTS = hg01_all_ok.$(OBJEXT)
+hg01_all_ok_LDADD = $(LDADD)
+hg01_all_ok_DEPENDENCIES =
+hg02_deadlock_SOURCES = hg02_deadlock.c
+hg02_deadlock_OBJECTS = hg02_deadlock.$(OBJEXT)
+hg02_deadlock_LDADD = $(LDADD)
+hg02_deadlock_DEPENDENCIES =
+hg03_inherit_SOURCES = hg03_inherit.c
+hg03_inherit_OBJECTS = hg03_inherit.$(OBJEXT)
+hg03_inherit_LDADD = $(LDADD)
+hg03_inherit_DEPENDENCIES =
+hg04_race_SOURCES = hg04_race.c
+hg04_race_OBJECTS = hg04_race.$(OBJEXT)
+hg04_race_LDADD = $(LDADD)
+hg04_race_DEPENDENCIES =
+hg05_race2_SOURCES = hg05_race2.c
+hg05_race2_OBJECTS = hg05_race2.$(OBJEXT)
+hg05_race2_LDADD = $(LDADD)
+hg05_race2_DEPENDENCIES =
+hg06_readshared_SOURCES = hg06_readshared.c
+hg06_readshared_OBJECTS = hg06_readshared.$(OBJEXT)
+hg06_readshared_LDADD = $(LDADD)
+hg06_readshared_DEPENDENCIES =
+locked_vs_unlocked1_SOURCES = locked_vs_unlocked1.c
+locked_vs_unlocked1_OBJECTS = locked_vs_unlocked1.$(OBJEXT)
+locked_vs_unlocked1_LDADD = $(LDADD)
+locked_vs_unlocked1_DEPENDENCIES =
+locked_vs_unlocked2_SOURCES = locked_vs_unlocked2.c
+locked_vs_unlocked2_OBJECTS = locked_vs_unlocked2.$(OBJEXT)
+locked_vs_unlocked2_LDADD = $(LDADD)
+locked_vs_unlocked2_DEPENDENCIES =
+locked_vs_unlocked3_SOURCES = locked_vs_unlocked3.c
+locked_vs_unlocked3_OBJECTS = locked_vs_unlocked3.$(OBJEXT)
+locked_vs_unlocked3_LDADD = $(LDADD)
+locked_vs_unlocked3_DEPENDENCIES =
+pth_destroy_cond_SOURCES = pth_destroy_cond.c
+pth_destroy_cond_OBJECTS = pth_destroy_cond.$(OBJEXT)
+pth_destroy_cond_LDADD = $(LDADD)
+pth_destroy_cond_DEPENDENCIES =
+t2t_SOURCES = t2t.c
+t2t_OBJECTS = t2t.$(OBJEXT)
+t2t_LDADD = $(LDADD)
+t2t_DEPENDENCIES =
+tc01_simple_race_SOURCES = tc01_simple_race.c
+tc01_simple_race_OBJECTS = tc01_simple_race.$(OBJEXT)
+tc01_simple_race_LDADD = $(LDADD)
+tc01_simple_race_DEPENDENCIES =
+tc02_simple_tls_SOURCES = tc02_simple_tls.c
+tc02_simple_tls_OBJECTS = tc02_simple_tls.$(OBJEXT)
+tc02_simple_tls_LDADD = $(LDADD)
+tc02_simple_tls_DEPENDENCIES =
+tc03_re_excl_SOURCES = tc03_re_excl.c
+tc03_re_excl_OBJECTS = tc03_re_excl.$(OBJEXT)
+tc03_re_excl_LDADD = $(LDADD)
+tc03_re_excl_DEPENDENCIES =
+tc04_free_lock_SOURCES = tc04_free_lock.c
+tc04_free_lock_OBJECTS = tc04_free_lock.$(OBJEXT)
+tc04_free_lock_LDADD = $(LDADD)
+tc04_free_lock_DEPENDENCIES =
+tc05_simple_race_SOURCES = tc05_simple_race.c
+tc05_simple_race_OBJECTS = tc05_simple_race.$(OBJEXT)
+tc05_simple_race_LDADD = $(LDADD)
+tc05_simple_race_DEPENDENCIES =
+tc06_two_races_SOURCES = tc06_two_races.c
+tc06_two_races_OBJECTS = tc06_two_races.$(OBJEXT)
+tc06_two_races_LDADD = $(LDADD)
+tc06_two_races_DEPENDENCIES =
+tc07_hbl1_SOURCES = tc07_hbl1.c
+tc07_hbl1_OBJECTS = tc07_hbl1-tc07_hbl1.$(OBJEXT)
+tc07_hbl1_LDADD = $(LDADD)
+tc07_hbl1_DEPENDENCIES =
+tc07_hbl1_LINK = $(CCLD) $(tc07_hbl1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+tc08_hbl2_SOURCES = tc08_hbl2.c
+tc08_hbl2_OBJECTS = tc08_hbl2-tc08_hbl2.$(OBJEXT)
+tc08_hbl2_LDADD = $(LDADD)
+tc08_hbl2_DEPENDENCIES =
+tc08_hbl2_LINK = $(CCLD) $(tc08_hbl2_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+tc09_bad_unlock_SOURCES = tc09_bad_unlock.c
+tc09_bad_unlock_OBJECTS = tc09_bad_unlock.$(OBJEXT)
+tc09_bad_unlock_LDADD = $(LDADD)
+tc09_bad_unlock_DEPENDENCIES =
+tc10_rec_lock_SOURCES = tc10_rec_lock.c
+tc10_rec_lock_OBJECTS = tc10_rec_lock.$(OBJEXT)
+tc10_rec_lock_LDADD = $(LDADD)
+tc10_rec_lock_DEPENDENCIES =
+tc11_XCHG_SOURCES = tc11_XCHG.c
+tc11_XCHG_OBJECTS = tc11_XCHG.$(OBJEXT)
+tc11_XCHG_LDADD = $(LDADD)
+tc11_XCHG_DEPENDENCIES =
+tc12_rwl_trivial_SOURCES = tc12_rwl_trivial.c
+tc12_rwl_trivial_OBJECTS = tc12_rwl_trivial.$(OBJEXT)
+tc12_rwl_trivial_LDADD = $(LDADD)
+tc12_rwl_trivial_DEPENDENCIES =
+tc13_laog1_SOURCES = tc13_laog1.c
+tc13_laog1_OBJECTS = tc13_laog1.$(OBJEXT)
+tc13_laog1_LDADD = $(LDADD)
+tc13_laog1_DEPENDENCIES =
+tc14_laog_dinphils_SOURCES = tc14_laog_dinphils.c
+tc14_laog_dinphils_OBJECTS = tc14_laog_dinphils.$(OBJEXT)
+tc14_laog_dinphils_LDADD = $(LDADD)
+tc14_laog_dinphils_DEPENDENCIES =
+tc15_laog_lockdel_SOURCES = tc15_laog_lockdel.c
+tc15_laog_lockdel_OBJECTS = tc15_laog_lockdel.$(OBJEXT)
+tc15_laog_lockdel_LDADD = $(LDADD)
+tc15_laog_lockdel_DEPENDENCIES =
+tc16_byterace_SOURCES = tc16_byterace.c
+tc16_byterace_OBJECTS = tc16_byterace.$(OBJEXT)
+tc16_byterace_LDADD = $(LDADD)
+tc16_byterace_DEPENDENCIES =
+tc17_sembar_SOURCES = tc17_sembar.c
+tc17_sembar_OBJECTS = tc17_sembar.$(OBJEXT)
+tc17_sembar_LDADD = $(LDADD)
+tc17_sembar_DEPENDENCIES =
+tc18_semabuse_SOURCES = tc18_semabuse.c
+tc18_semabuse_OBJECTS = tc18_semabuse.$(OBJEXT)
+tc18_semabuse_LDADD = $(LDADD)
+tc18_semabuse_DEPENDENCIES =
+tc19_shadowmem_SOURCES = tc19_shadowmem.c
+tc19_shadowmem_OBJECTS = tc19_shadowmem.$(OBJEXT)
+tc19_shadowmem_LDADD = $(LDADD)
+tc19_shadowmem_DEPENDENCIES =
+tc20_verifywrap_SOURCES = tc20_verifywrap.c
+tc20_verifywrap_OBJECTS = tc20_verifywrap.$(OBJEXT)
+tc20_verifywrap_LDADD = $(LDADD)
+tc20_verifywrap_DEPENDENCIES =
+tc21_pthonce_SOURCES = tc21_pthonce.c
+tc21_pthonce_OBJECTS = tc21_pthonce.$(OBJEXT)
+tc21_pthonce_LDADD = $(LDADD)
+tc21_pthonce_DEPENDENCIES =
+tc22_exit_w_lock_SOURCES = tc22_exit_w_lock.c
+tc22_exit_w_lock_OBJECTS = tc22_exit_w_lock.$(OBJEXT)
+tc22_exit_w_lock_LDADD = $(LDADD)
+tc22_exit_w_lock_DEPENDENCIES =
+tc23_bogus_condwait_SOURCES = tc23_bogus_condwait.c
+tc23_bogus_condwait_OBJECTS = tc23_bogus_condwait.$(OBJEXT)
+tc23_bogus_condwait_LDADD = $(LDADD)
+tc23_bogus_condwait_DEPENDENCIES =
+tc24_nonzero_sem_SOURCES = tc24_nonzero_sem.c
+tc24_nonzero_sem_OBJECTS = tc24_nonzero_sem.$(OBJEXT)
+tc24_nonzero_sem_LDADD = $(LDADD)
+tc24_nonzero_sem_DEPENDENCIES =
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = annotate_hbefore.c annotate_rwlock.c bar_bad.c bar_trivial.c \
+ cond_timedwait_invalid.c free_is_write.c hg01_all_ok.c \
+ hg02_deadlock.c hg03_inherit.c hg04_race.c hg05_race2.c \
+ hg06_readshared.c locked_vs_unlocked1.c locked_vs_unlocked2.c \
+ locked_vs_unlocked3.c pth_destroy_cond.c t2t.c \
+ tc01_simple_race.c tc02_simple_tls.c tc03_re_excl.c \
+ tc04_free_lock.c tc05_simple_race.c tc06_two_races.c \
+ tc07_hbl1.c tc08_hbl2.c tc09_bad_unlock.c tc10_rec_lock.c \
+ tc11_XCHG.c tc12_rwl_trivial.c tc13_laog1.c \
+ tc14_laog_dinphils.c tc15_laog_lockdel.c tc16_byterace.c \
+ tc17_sembar.c tc18_semabuse.c tc19_shadowmem.c \
+ tc20_verifywrap.c tc21_pthonce.c tc22_exit_w_lock.c \
+ tc23_bogus_condwait.c tc24_nonzero_sem.c
+DIST_SOURCES = annotate_hbefore.c annotate_rwlock.c bar_bad.c \
+ bar_trivial.c cond_timedwait_invalid.c free_is_write.c \
+ hg01_all_ok.c hg02_deadlock.c hg03_inherit.c hg04_race.c \
+ hg05_race2.c hg06_readshared.c locked_vs_unlocked1.c \
+ locked_vs_unlocked2.c locked_vs_unlocked3.c pth_destroy_cond.c \
+ t2t.c tc01_simple_race.c tc02_simple_tls.c tc03_re_excl.c \
+ tc04_free_lock.c tc05_simple_race.c tc06_two_races.c \
+ tc07_hbl1.c tc08_hbl2.c tc09_bad_unlock.c tc10_rec_lock.c \
+ tc11_XCHG.c tc12_rwl_trivial.c tc13_laog1.c \
+ tc14_laog_dinphils.c tc15_laog_lockdel.c tc16_byterace.c \
+ tc17_sembar.c tc18_semabuse.c tc19_shadowmem.c \
+ tc20_verifywrap.c tc21_pthonce.c tc22_exit_w_lock.c \
+ tc23_bogus_condwait.c tc24_nonzero_sem.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr \
+ filter_helgrind \
+ filter_xml
+
+EXTRA_DIST = \
+ annotate_hbefore.vgtest annotate_hbefore.stdout.exp \
+ annotate_hbefore.stderr.exp \
+ annotate_rwlock.vgtest annotate_rwlock.stdout.exp \
+ annotate_rwlock.stderr.exp \
+ annotate_smart_pointer.vgtest annotate_smart_pointer.stdout.exp \
+ annotate_smart_pointer.stderr.exp \
+ cond_timedwait_invalid.vgtest cond_timedwait_invalid.stdout.exp \
+ cond_timedwait_invalid.stderr.exp \
+ bar_bad.vgtest bar_bad.stdout.exp bar_bad.stderr.exp \
+ bar_trivial.vgtest bar_trivial.stdout.exp bar_trivial.stderr.exp \
+ free_is_write.vgtest free_is_write.stdout.exp \
+ free_is_write.stderr.exp \
+ hg01_all_ok.vgtest hg01_all_ok.stdout.exp hg01_all_ok.stderr.exp \
+ hg02_deadlock.vgtest hg02_deadlock.stdout.exp hg02_deadlock.stderr.exp \
+ hg03_inherit.vgtest hg03_inherit.stdout.exp hg03_inherit.stderr.exp \
+ hg04_race.vgtest hg04_race.stdout.exp hg04_race.stderr.exp \
+ hg05_race2.vgtest hg05_race2.stdout.exp hg05_race2.stderr.exp \
+ hg06_readshared.vgtest hg06_readshared.stdout.exp \
+ hg06_readshared.stderr.exp \
+ locked_vs_unlocked1_fwd.vgtest \
+ locked_vs_unlocked1_fwd.stderr.exp \
+ locked_vs_unlocked1_fwd.stdout.exp \
+ locked_vs_unlocked1_rev.vgtest \
+ locked_vs_unlocked1_rev.stderr.exp \
+ locked_vs_unlocked1_rev.stdout.exp \
+ locked_vs_unlocked2.vgtest \
+ locked_vs_unlocked2.stderr.exp \
+ locked_vs_unlocked2.stdout.exp \
+ locked_vs_unlocked3.vgtest \
+ locked_vs_unlocked3.stderr.exp \
+ locked_vs_unlocked3.stdout.exp \
+ pth_barrier1.vgtest pth_barrier1.stdout.exp pth_barrier1.stderr.exp \
+ pth_barrier2.vgtest pth_barrier2.stdout.exp pth_barrier2.stderr.exp \
+ pth_barrier3.vgtest pth_barrier3.stdout.exp pth_barrier3.stderr.exp \
+ pth_destroy_cond.vgtest \
+ pth_destroy_cond.stdout.exp pth_destroy_cond.stderr.exp \
+ pth_spinlock.vgtest pth_spinlock.stdout.exp pth_spinlock.stderr.exp \
+ rwlock_race.vgtest rwlock_race.stdout.exp rwlock_race.stderr.exp \
+ rwlock_test.vgtest rwlock_test.stdout.exp rwlock_test.stderr.exp \
+ t2t_laog.vgtest t2t_laog.stdout.exp t2t_laog.stderr.exp \
+ tc01_simple_race.vgtest tc01_simple_race.stdout.exp \
+ tc01_simple_race.stderr.exp \
+ tc02_simple_tls.vgtest tc02_simple_tls.stdout.exp \
+ tc02_simple_tls.stderr.exp \
+ tc03_re_excl.vgtest tc03_re_excl.stdout.exp \
+ tc03_re_excl.stderr.exp \
+ tc04_free_lock.vgtest tc04_free_lock.stdout.exp \
+ tc04_free_lock.stderr.exp \
+ tc05_simple_race.vgtest tc05_simple_race.stdout.exp \
+ tc05_simple_race.stderr.exp \
+ tc06_two_races.vgtest tc06_two_races.stdout.exp \
+ tc06_two_races.stderr.exp \
+ tc06_two_races_xml.vgtest tc06_two_races_xml.stdout.exp \
+ tc06_two_races_xml.stderr.exp \
+ tc07_hbl1.vgtest tc07_hbl1.stdout.exp tc07_hbl1.stderr.exp \
+ tc08_hbl2.vgtest tc08_hbl2.stdout.exp tc08_hbl2.stderr.exp \
+ tc09_bad_unlock.vgtest tc09_bad_unlock.stdout.exp \
+ tc09_bad_unlock.stderr.exp \
+ tc10_rec_lock.vgtest tc10_rec_lock.stdout.exp tc10_rec_lock.stderr.exp \
+ tc11_XCHG.vgtest tc11_XCHG.stdout.exp tc11_XCHG.stderr.exp \
+ tc12_rwl_trivial.vgtest tc12_rwl_trivial.stdout.exp \
+ tc12_rwl_trivial.stderr.exp \
+ tc12_rwl_trivial.stderr.exp-darwin970 \
+ tc13_laog1.vgtest tc13_laog1.stdout.exp tc13_laog1.stderr.exp \
+ tc14_laog_dinphils.vgtest tc14_laog_dinphils.stdout.exp \
+ tc14_laog_dinphils.stderr.exp \
+ tc15_laog_lockdel.vgtest tc15_laog_lockdel.stdout.exp \
+ tc15_laog_lockdel.stderr.exp \
+ tc16_byterace.vgtest tc16_byterace.stdout.exp \
+ tc16_byterace.stderr.exp \
+ tc17_sembar.vgtest tc17_sembar.stdout.exp \
+ tc17_sembar.stderr.exp \
+ tc18_semabuse.vgtest tc18_semabuse.stdout.exp \
+ tc18_semabuse.stderr.exp \
+ tc19_shadowmem.vgtest tc19_shadowmem.stdout.exp \
+ tc19_shadowmem.stderr.exp \
+ tc20_verifywrap.vgtest tc20_verifywrap.stdout.exp \
+ tc20_verifywrap.stderr.exp \
+ tc21_pthonce.vgtest tc21_pthonce.stdout.exp tc21_pthonce.stderr.exp \
+ tc22_exit_w_lock.vgtest tc22_exit_w_lock.stdout.exp \
+ tc22_exit_w_lock.stderr.exp \
+ tc22_exit_w_lock.stderr.exp-kfail-x86 \
+ tc23_bogus_condwait.vgtest tc23_bogus_condwait.stdout.exp \
+ tc23_bogus_condwait.stderr.exp \
+ tc24_nonzero_sem.vgtest tc24_nonzero_sem.stdout.exp \
+ tc24_nonzero_sem.stderr.exp
+
+@VGCONF_OS_IS_DARWIN_FALSE@annotate_hbefore_CFLAGS = $(AM_CFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@annotate_hbefore_CFLAGS = $(AM_CFLAGS) -mdynamic-no-pic
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_FALSE@annotate_hbefore_CFLAGS = $(AM_CFLAGS)
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@annotate_hbefore_CFLAGS = $(AM_CFLAGS) -mcpu=cortex-a8
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_FALSE@tc07_hbl1_CFLAGS = $(AM_CFLAGS)
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@tc07_hbl1_CFLAGS = $(AM_CFLAGS) -mcpu=cortex-a8
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_FALSE@tc08_hbl2_CFLAGS = $(AM_CFLAGS)
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@tc08_hbl2_CFLAGS = $(AM_CFLAGS) -mcpu=cortex-a8
+LDADD = -lpthread
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign helgrind/tests/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign helgrind/tests/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+annotate_hbefore$(EXEEXT): $(annotate_hbefore_OBJECTS) $(annotate_hbefore_DEPENDENCIES)
+ @rm -f annotate_hbefore$(EXEEXT)
+ $(annotate_hbefore_LINK) $(annotate_hbefore_OBJECTS) $(annotate_hbefore_LDADD) $(LIBS)
+annotate_rwlock$(EXEEXT): $(annotate_rwlock_OBJECTS) $(annotate_rwlock_DEPENDENCIES)
+ @rm -f annotate_rwlock$(EXEEXT)
+ $(LINK) $(annotate_rwlock_OBJECTS) $(annotate_rwlock_LDADD) $(LIBS)
+bar_bad$(EXEEXT): $(bar_bad_OBJECTS) $(bar_bad_DEPENDENCIES)
+ @rm -f bar_bad$(EXEEXT)
+ $(LINK) $(bar_bad_OBJECTS) $(bar_bad_LDADD) $(LIBS)
+bar_trivial$(EXEEXT): $(bar_trivial_OBJECTS) $(bar_trivial_DEPENDENCIES)
+ @rm -f bar_trivial$(EXEEXT)
+ $(LINK) $(bar_trivial_OBJECTS) $(bar_trivial_LDADD) $(LIBS)
+cond_timedwait_invalid$(EXEEXT): $(cond_timedwait_invalid_OBJECTS) $(cond_timedwait_invalid_DEPENDENCIES)
+ @rm -f cond_timedwait_invalid$(EXEEXT)
+ $(LINK) $(cond_timedwait_invalid_OBJECTS) $(cond_timedwait_invalid_LDADD) $(LIBS)
+free_is_write$(EXEEXT): $(free_is_write_OBJECTS) $(free_is_write_DEPENDENCIES)
+ @rm -f free_is_write$(EXEEXT)
+ $(LINK) $(free_is_write_OBJECTS) $(free_is_write_LDADD) $(LIBS)
+hg01_all_ok$(EXEEXT): $(hg01_all_ok_OBJECTS) $(hg01_all_ok_DEPENDENCIES)
+ @rm -f hg01_all_ok$(EXEEXT)
+ $(LINK) $(hg01_all_ok_OBJECTS) $(hg01_all_ok_LDADD) $(LIBS)
+hg02_deadlock$(EXEEXT): $(hg02_deadlock_OBJECTS) $(hg02_deadlock_DEPENDENCIES)
+ @rm -f hg02_deadlock$(EXEEXT)
+ $(LINK) $(hg02_deadlock_OBJECTS) $(hg02_deadlock_LDADD) $(LIBS)
+hg03_inherit$(EXEEXT): $(hg03_inherit_OBJECTS) $(hg03_inherit_DEPENDENCIES)
+ @rm -f hg03_inherit$(EXEEXT)
+ $(LINK) $(hg03_inherit_OBJECTS) $(hg03_inherit_LDADD) $(LIBS)
+hg04_race$(EXEEXT): $(hg04_race_OBJECTS) $(hg04_race_DEPENDENCIES)
+ @rm -f hg04_race$(EXEEXT)
+ $(LINK) $(hg04_race_OBJECTS) $(hg04_race_LDADD) $(LIBS)
+hg05_race2$(EXEEXT): $(hg05_race2_OBJECTS) $(hg05_race2_DEPENDENCIES)
+ @rm -f hg05_race2$(EXEEXT)
+ $(LINK) $(hg05_race2_OBJECTS) $(hg05_race2_LDADD) $(LIBS)
+hg06_readshared$(EXEEXT): $(hg06_readshared_OBJECTS) $(hg06_readshared_DEPENDENCIES)
+ @rm -f hg06_readshared$(EXEEXT)
+ $(LINK) $(hg06_readshared_OBJECTS) $(hg06_readshared_LDADD) $(LIBS)
+locked_vs_unlocked1$(EXEEXT): $(locked_vs_unlocked1_OBJECTS) $(locked_vs_unlocked1_DEPENDENCIES)
+ @rm -f locked_vs_unlocked1$(EXEEXT)
+ $(LINK) $(locked_vs_unlocked1_OBJECTS) $(locked_vs_unlocked1_LDADD) $(LIBS)
+locked_vs_unlocked2$(EXEEXT): $(locked_vs_unlocked2_OBJECTS) $(locked_vs_unlocked2_DEPENDENCIES)
+ @rm -f locked_vs_unlocked2$(EXEEXT)
+ $(LINK) $(locked_vs_unlocked2_OBJECTS) $(locked_vs_unlocked2_LDADD) $(LIBS)
+locked_vs_unlocked3$(EXEEXT): $(locked_vs_unlocked3_OBJECTS) $(locked_vs_unlocked3_DEPENDENCIES)
+ @rm -f locked_vs_unlocked3$(EXEEXT)
+ $(LINK) $(locked_vs_unlocked3_OBJECTS) $(locked_vs_unlocked3_LDADD) $(LIBS)
+pth_destroy_cond$(EXEEXT): $(pth_destroy_cond_OBJECTS) $(pth_destroy_cond_DEPENDENCIES)
+ @rm -f pth_destroy_cond$(EXEEXT)
+ $(LINK) $(pth_destroy_cond_OBJECTS) $(pth_destroy_cond_LDADD) $(LIBS)
+t2t$(EXEEXT): $(t2t_OBJECTS) $(t2t_DEPENDENCIES)
+ @rm -f t2t$(EXEEXT)
+ $(LINK) $(t2t_OBJECTS) $(t2t_LDADD) $(LIBS)
+tc01_simple_race$(EXEEXT): $(tc01_simple_race_OBJECTS) $(tc01_simple_race_DEPENDENCIES)
+ @rm -f tc01_simple_race$(EXEEXT)
+ $(LINK) $(tc01_simple_race_OBJECTS) $(tc01_simple_race_LDADD) $(LIBS)
+tc02_simple_tls$(EXEEXT): $(tc02_simple_tls_OBJECTS) $(tc02_simple_tls_DEPENDENCIES)
+ @rm -f tc02_simple_tls$(EXEEXT)
+ $(LINK) $(tc02_simple_tls_OBJECTS) $(tc02_simple_tls_LDADD) $(LIBS)
+tc03_re_excl$(EXEEXT): $(tc03_re_excl_OBJECTS) $(tc03_re_excl_DEPENDENCIES)
+ @rm -f tc03_re_excl$(EXEEXT)
+ $(LINK) $(tc03_re_excl_OBJECTS) $(tc03_re_excl_LDADD) $(LIBS)
+tc04_free_lock$(EXEEXT): $(tc04_free_lock_OBJECTS) $(tc04_free_lock_DEPENDENCIES)
+ @rm -f tc04_free_lock$(EXEEXT)
+ $(LINK) $(tc04_free_lock_OBJECTS) $(tc04_free_lock_LDADD) $(LIBS)
+tc05_simple_race$(EXEEXT): $(tc05_simple_race_OBJECTS) $(tc05_simple_race_DEPENDENCIES)
+ @rm -f tc05_simple_race$(EXEEXT)
+ $(LINK) $(tc05_simple_race_OBJECTS) $(tc05_simple_race_LDADD) $(LIBS)
+tc06_two_races$(EXEEXT): $(tc06_two_races_OBJECTS) $(tc06_two_races_DEPENDENCIES)
+ @rm -f tc06_two_races$(EXEEXT)
+ $(LINK) $(tc06_two_races_OBJECTS) $(tc06_two_races_LDADD) $(LIBS)
+tc07_hbl1$(EXEEXT): $(tc07_hbl1_OBJECTS) $(tc07_hbl1_DEPENDENCIES)
+ @rm -f tc07_hbl1$(EXEEXT)
+ $(tc07_hbl1_LINK) $(tc07_hbl1_OBJECTS) $(tc07_hbl1_LDADD) $(LIBS)
+tc08_hbl2$(EXEEXT): $(tc08_hbl2_OBJECTS) $(tc08_hbl2_DEPENDENCIES)
+ @rm -f tc08_hbl2$(EXEEXT)
+ $(tc08_hbl2_LINK) $(tc08_hbl2_OBJECTS) $(tc08_hbl2_LDADD) $(LIBS)
+tc09_bad_unlock$(EXEEXT): $(tc09_bad_unlock_OBJECTS) $(tc09_bad_unlock_DEPENDENCIES)
+ @rm -f tc09_bad_unlock$(EXEEXT)
+ $(LINK) $(tc09_bad_unlock_OBJECTS) $(tc09_bad_unlock_LDADD) $(LIBS)
+tc10_rec_lock$(EXEEXT): $(tc10_rec_lock_OBJECTS) $(tc10_rec_lock_DEPENDENCIES)
+ @rm -f tc10_rec_lock$(EXEEXT)
+ $(LINK) $(tc10_rec_lock_OBJECTS) $(tc10_rec_lock_LDADD) $(LIBS)
+tc11_XCHG$(EXEEXT): $(tc11_XCHG_OBJECTS) $(tc11_XCHG_DEPENDENCIES)
+ @rm -f tc11_XCHG$(EXEEXT)
+ $(LINK) $(tc11_XCHG_OBJECTS) $(tc11_XCHG_LDADD) $(LIBS)
+tc12_rwl_trivial$(EXEEXT): $(tc12_rwl_trivial_OBJECTS) $(tc12_rwl_trivial_DEPENDENCIES)
+ @rm -f tc12_rwl_trivial$(EXEEXT)
+ $(LINK) $(tc12_rwl_trivial_OBJECTS) $(tc12_rwl_trivial_LDADD) $(LIBS)
+tc13_laog1$(EXEEXT): $(tc13_laog1_OBJECTS) $(tc13_laog1_DEPENDENCIES)
+ @rm -f tc13_laog1$(EXEEXT)
+ $(LINK) $(tc13_laog1_OBJECTS) $(tc13_laog1_LDADD) $(LIBS)
+tc14_laog_dinphils$(EXEEXT): $(tc14_laog_dinphils_OBJECTS) $(tc14_laog_dinphils_DEPENDENCIES)
+ @rm -f tc14_laog_dinphils$(EXEEXT)
+ $(LINK) $(tc14_laog_dinphils_OBJECTS) $(tc14_laog_dinphils_LDADD) $(LIBS)
+tc15_laog_lockdel$(EXEEXT): $(tc15_laog_lockdel_OBJECTS) $(tc15_laog_lockdel_DEPENDENCIES)
+ @rm -f tc15_laog_lockdel$(EXEEXT)
+ $(LINK) $(tc15_laog_lockdel_OBJECTS) $(tc15_laog_lockdel_LDADD) $(LIBS)
+tc16_byterace$(EXEEXT): $(tc16_byterace_OBJECTS) $(tc16_byterace_DEPENDENCIES)
+ @rm -f tc16_byterace$(EXEEXT)
+ $(LINK) $(tc16_byterace_OBJECTS) $(tc16_byterace_LDADD) $(LIBS)
+tc17_sembar$(EXEEXT): $(tc17_sembar_OBJECTS) $(tc17_sembar_DEPENDENCIES)
+ @rm -f tc17_sembar$(EXEEXT)
+ $(LINK) $(tc17_sembar_OBJECTS) $(tc17_sembar_LDADD) $(LIBS)
+tc18_semabuse$(EXEEXT): $(tc18_semabuse_OBJECTS) $(tc18_semabuse_DEPENDENCIES)
+ @rm -f tc18_semabuse$(EXEEXT)
+ $(LINK) $(tc18_semabuse_OBJECTS) $(tc18_semabuse_LDADD) $(LIBS)
+tc19_shadowmem$(EXEEXT): $(tc19_shadowmem_OBJECTS) $(tc19_shadowmem_DEPENDENCIES)
+ @rm -f tc19_shadowmem$(EXEEXT)
+ $(LINK) $(tc19_shadowmem_OBJECTS) $(tc19_shadowmem_LDADD) $(LIBS)
+tc20_verifywrap$(EXEEXT): $(tc20_verifywrap_OBJECTS) $(tc20_verifywrap_DEPENDENCIES)
+ @rm -f tc20_verifywrap$(EXEEXT)
+ $(LINK) $(tc20_verifywrap_OBJECTS) $(tc20_verifywrap_LDADD) $(LIBS)
+tc21_pthonce$(EXEEXT): $(tc21_pthonce_OBJECTS) $(tc21_pthonce_DEPENDENCIES)
+ @rm -f tc21_pthonce$(EXEEXT)
+ $(LINK) $(tc21_pthonce_OBJECTS) $(tc21_pthonce_LDADD) $(LIBS)
+tc22_exit_w_lock$(EXEEXT): $(tc22_exit_w_lock_OBJECTS) $(tc22_exit_w_lock_DEPENDENCIES)
+ @rm -f tc22_exit_w_lock$(EXEEXT)
+ $(LINK) $(tc22_exit_w_lock_OBJECTS) $(tc22_exit_w_lock_LDADD) $(LIBS)
+tc23_bogus_condwait$(EXEEXT): $(tc23_bogus_condwait_OBJECTS) $(tc23_bogus_condwait_DEPENDENCIES)
+ @rm -f tc23_bogus_condwait$(EXEEXT)
+ $(LINK) $(tc23_bogus_condwait_OBJECTS) $(tc23_bogus_condwait_LDADD) $(LIBS)
+tc24_nonzero_sem$(EXEEXT): $(tc24_nonzero_sem_OBJECTS) $(tc24_nonzero_sem_DEPENDENCIES)
+ @rm -f tc24_nonzero_sem$(EXEEXT)
+ $(LINK) $(tc24_nonzero_sem_OBJECTS) $(tc24_nonzero_sem_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_hbefore-annotate_hbefore.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/annotate_rwlock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bar_bad.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bar_trivial.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cond_timedwait_invalid.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/free_is_write.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hg01_all_ok.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hg02_deadlock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hg03_inherit.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hg04_race.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hg05_race2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hg06_readshared.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/locked_vs_unlocked1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/locked_vs_unlocked2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/locked_vs_unlocked3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_destroy_cond.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/t2t.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc01_simple_race.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc02_simple_tls.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc03_re_excl.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc04_free_lock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc05_simple_race.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc06_two_races.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc07_hbl1-tc07_hbl1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc08_hbl2-tc08_hbl2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc09_bad_unlock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc10_rec_lock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc11_XCHG.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc12_rwl_trivial.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc13_laog1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc14_laog_dinphils.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc15_laog_lockdel.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc16_byterace.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc17_sembar.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc18_semabuse.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc19_shadowmem.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc20_verifywrap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc21_pthonce.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc22_exit_w_lock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc23_bogus_condwait.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc24_nonzero_sem.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+annotate_hbefore-annotate_hbefore.o: annotate_hbefore.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(annotate_hbefore_CFLAGS) $(CFLAGS) -MT annotate_hbefore-annotate_hbefore.o -MD -MP -MF $(DEPDIR)/annotate_hbefore-annotate_hbefore.Tpo -c -o annotate_hbefore-annotate_hbefore.o `test -f 'annotate_hbefore.c' || echo '$(srcdir)/'`annotate_hbefore.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/annotate_hbefore-annotate_hbefore.Tpo $(DEPDIR)/annotate_hbefore-annotate_hbefore.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='annotate_hbefore.c' object='annotate_hbefore-annotate_hbefore.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(annotate_hbefore_CFLAGS) $(CFLAGS) -c -o annotate_hbefore-annotate_hbefore.o `test -f 'annotate_hbefore.c' || echo '$(srcdir)/'`annotate_hbefore.c
+
+annotate_hbefore-annotate_hbefore.obj: annotate_hbefore.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(annotate_hbefore_CFLAGS) $(CFLAGS) -MT annotate_hbefore-annotate_hbefore.obj -MD -MP -MF $(DEPDIR)/annotate_hbefore-annotate_hbefore.Tpo -c -o annotate_hbefore-annotate_hbefore.obj `if test -f 'annotate_hbefore.c'; then $(CYGPATH_W) 'annotate_hbefore.c'; else $(CYGPATH_W) '$(srcdir)/annotate_hbefore.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/annotate_hbefore-annotate_hbefore.Tpo $(DEPDIR)/annotate_hbefore-annotate_hbefore.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='annotate_hbefore.c' object='annotate_hbefore-annotate_hbefore.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(annotate_hbefore_CFLAGS) $(CFLAGS) -c -o annotate_hbefore-annotate_hbefore.obj `if test -f 'annotate_hbefore.c'; then $(CYGPATH_W) 'annotate_hbefore.c'; else $(CYGPATH_W) '$(srcdir)/annotate_hbefore.c'; fi`
+
+tc07_hbl1-tc07_hbl1.o: tc07_hbl1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tc07_hbl1_CFLAGS) $(CFLAGS) -MT tc07_hbl1-tc07_hbl1.o -MD -MP -MF $(DEPDIR)/tc07_hbl1-tc07_hbl1.Tpo -c -o tc07_hbl1-tc07_hbl1.o `test -f 'tc07_hbl1.c' || echo '$(srcdir)/'`tc07_hbl1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc07_hbl1-tc07_hbl1.Tpo $(DEPDIR)/tc07_hbl1-tc07_hbl1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='tc07_hbl1.c' object='tc07_hbl1-tc07_hbl1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tc07_hbl1_CFLAGS) $(CFLAGS) -c -o tc07_hbl1-tc07_hbl1.o `test -f 'tc07_hbl1.c' || echo '$(srcdir)/'`tc07_hbl1.c
+
+tc07_hbl1-tc07_hbl1.obj: tc07_hbl1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tc07_hbl1_CFLAGS) $(CFLAGS) -MT tc07_hbl1-tc07_hbl1.obj -MD -MP -MF $(DEPDIR)/tc07_hbl1-tc07_hbl1.Tpo -c -o tc07_hbl1-tc07_hbl1.obj `if test -f 'tc07_hbl1.c'; then $(CYGPATH_W) 'tc07_hbl1.c'; else $(CYGPATH_W) '$(srcdir)/tc07_hbl1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc07_hbl1-tc07_hbl1.Tpo $(DEPDIR)/tc07_hbl1-tc07_hbl1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='tc07_hbl1.c' object='tc07_hbl1-tc07_hbl1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tc07_hbl1_CFLAGS) $(CFLAGS) -c -o tc07_hbl1-tc07_hbl1.obj `if test -f 'tc07_hbl1.c'; then $(CYGPATH_W) 'tc07_hbl1.c'; else $(CYGPATH_W) '$(srcdir)/tc07_hbl1.c'; fi`
+
+tc08_hbl2-tc08_hbl2.o: tc08_hbl2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tc08_hbl2_CFLAGS) $(CFLAGS) -MT tc08_hbl2-tc08_hbl2.o -MD -MP -MF $(DEPDIR)/tc08_hbl2-tc08_hbl2.Tpo -c -o tc08_hbl2-tc08_hbl2.o `test -f 'tc08_hbl2.c' || echo '$(srcdir)/'`tc08_hbl2.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc08_hbl2-tc08_hbl2.Tpo $(DEPDIR)/tc08_hbl2-tc08_hbl2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='tc08_hbl2.c' object='tc08_hbl2-tc08_hbl2.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tc08_hbl2_CFLAGS) $(CFLAGS) -c -o tc08_hbl2-tc08_hbl2.o `test -f 'tc08_hbl2.c' || echo '$(srcdir)/'`tc08_hbl2.c
+
+tc08_hbl2-tc08_hbl2.obj: tc08_hbl2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tc08_hbl2_CFLAGS) $(CFLAGS) -MT tc08_hbl2-tc08_hbl2.obj -MD -MP -MF $(DEPDIR)/tc08_hbl2-tc08_hbl2.Tpo -c -o tc08_hbl2-tc08_hbl2.obj `if test -f 'tc08_hbl2.c'; then $(CYGPATH_W) 'tc08_hbl2.c'; else $(CYGPATH_W) '$(srcdir)/tc08_hbl2.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc08_hbl2-tc08_hbl2.Tpo $(DEPDIR)/tc08_hbl2-tc08_hbl2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='tc08_hbl2.c' object='tc08_hbl2-tc08_hbl2.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tc08_hbl2_CFLAGS) $(CFLAGS) -c -o tc08_hbl2-tc08_hbl2.obj `if test -f 'tc08_hbl2.c'; then $(CYGPATH_W) 'tc08_hbl2.c'; else $(CYGPATH_W) '$(srcdir)/tc08_hbl2.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/helgrind/tests/annotate_hbefore.c b/main/helgrind/tests/annotate_hbefore.c
index 5f96942..cd58cef 100644
--- a/main/helgrind/tests/annotate_hbefore.c
+++ b/main/helgrind/tests/annotate_hbefore.c
@@ -186,6 +186,38 @@
return cc == 0;
}
+#elif defined(VGA_mips32)
+
+// mips
+/* return 1 if success, 0 if failure */
+UWord do_acasW ( UWord* addr, UWord expected, UWord nyu )
+{
+ UWord old, success;
+ UWord block[3] = { (UWord)addr, nyu, expected};
+
+ __asm__ __volatile__(
+ ".set noreorder" "\n\t"
+ "lw $t0, 0(%1)" "\n\t"
+ "lw $t2, 8(%1)" "\n\t"
+ "lw $t3, 4(%1)" "\n\t"
+ "ll $t1, 0($t0)" "\n\t"
+ "bne $t1, $t2, exit_0" "\n\t"
+ "sc $t3, 0($t0)" "\n\t"
+ "move %0, $t3" "\n\t"
+ "b exit" "\n\t"
+ "nop" "\n\t"
+ "exit_0:" "\n\t"
+ "move %0, $0" "\n\t"
+ "exit:" "\n\t"
+ : /*out*/ "=r"(success)
+ : /*in*/ "r"(&block[0])
+ : /*trash*/ "t0", "t1", "t2", "t3", "memory"
+ );
+
+ assert(success == 0 || success == 1);
+ return success;
+}
+
#endif
void atomic_incW ( UWord* w )
@@ -235,10 +267,18 @@
int shared_var = 0; // is not raced upon
-void delay500ms ( void )
+void delayXms ( int i )
{
- struct timespec ts = { 0, 500 * 1000 * 1000 };
- nanosleep(&ts, NULL);
+ struct timespec ts = { 0, 1 * 1000 * 1000 };
+ // We do the sleep in small pieces to have scheduling
+ // events ensuring a fair switch between threads, even
+ // without --fair-sched=yes. This is a.o. needed for
+ // running this test under an outer helgrind or an outer
+ // sgcheck.
+ while (i > 0) {
+ nanosleep(&ts, NULL);
+ i--;
+ }
}
void do_wait ( UWord* w )
@@ -246,7 +286,7 @@
UWord w0 = *w;
UWord volatile * wV = w;
while (*wV == w0)
- ;
+ delayXms(1); // small sleeps, ensuring context switches
ANNOTATE_HAPPENS_AFTER(w);
}
@@ -261,11 +301,11 @@
void* thread_fn1 ( void* arg )
{
UWord* w = (UWord*)arg;
- delay500ms(); // ensure t2 gets to its wait first
+ delayXms(500); // ensure t2 gets to its wait first
shared_var = 1; // first access
do_signal(w); // cause h-b edge to second thread
- delay500ms();
+ delayXms(500);
return NULL;
}
@@ -275,7 +315,7 @@
do_wait(w); // wait for h-b edge from first thread
shared_var = 2; // second access
- delay500ms();
+ delayXms(500);
return NULL;
}
diff --git a/main/helgrind/tests/annotate_hbefore.vgtest b/main/helgrind/tests/annotate_hbefore.vgtest
index 1e37939..2142f0a 100644
--- a/main/helgrind/tests/annotate_hbefore.vgtest
+++ b/main/helgrind/tests/annotate_hbefore.vgtest
@@ -1,2 +1,2 @@
-vgopts: -q
+vgopts: -q --fair-sched=try
prog: annotate_hbefore
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/helgrind/tests/annotate_smart_pointer.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/helgrind/tests/annotate_smart_pointer.stdout.exp
diff --git a/main/helgrind/tests/cond_timedwait_invalid.c b/main/helgrind/tests/cond_timedwait_invalid.c
index a8d0448..8c3bd86 100644
--- a/main/helgrind/tests/cond_timedwait_invalid.c
+++ b/main/helgrind/tests/cond_timedwait_invalid.c
@@ -1,4 +1,4 @@
-#include "config.h"
+
#include <time.h>
#include <pthread.h>
#include <assert.h>
@@ -10,12 +10,12 @@
pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
pthread_cond_t cond = PTHREAD_COND_INITIALIZER;
-#ifdef HAVE_CLOCK_GETTIME
- assert(clock_gettime(CLOCK_REALTIME, &abstime)==0);
-#else
+
+
+
abstime.tv_sec = time(NULL) + 2;
abstime.tv_nsec = 0;
-#endif
+
abstime.tv_nsec += 1000000000;
assert(pthread_mutex_lock(&mutex)==0);
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/helgrind/tests/cond_timedwait_invalid.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/helgrind/tests/cond_timedwait_invalid.stdout.exp
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/helgrind/tests/free_is_write.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/helgrind/tests/free_is_write.stdout.exp
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/helgrind/tests/locked_vs_unlocked1_fwd.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/helgrind/tests/locked_vs_unlocked1_fwd.stdout.exp
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/helgrind/tests/locked_vs_unlocked1_rev.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/helgrind/tests/locked_vs_unlocked1_rev.stdout.exp
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/helgrind/tests/locked_vs_unlocked2.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/helgrind/tests/locked_vs_unlocked2.stdout.exp
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/helgrind/tests/locked_vs_unlocked3.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/helgrind/tests/locked_vs_unlocked3.stdout.exp
diff --git a/main/helgrind/tests/pth_destroy_cond.c b/main/helgrind/tests/pth_destroy_cond.c
new file mode 100644
index 0000000..54f4f43
--- /dev/null
+++ b/main/helgrind/tests/pth_destroy_cond.c
@@ -0,0 +1,39 @@
+#include <stdio.h>
+#include <pthread.h>
+#include <errno.h>
+// test program from johan.walles (bug 295590)
+// This test verifies that helgrind detects (and does not crash) when
+// the guest application wrongly destroys a cond var being waited
+// upon.
+pthread_mutex_t mutex;
+pthread_cond_t cond;
+pthread_t thread;
+int ready = 0;
+
+void *ThreadFunction(void *ptr)
+{
+ pthread_mutex_lock(&mutex);
+ ready = 1;
+ pthread_cond_signal(&cond);
+ pthread_cond_destroy(&cond); // ERROR!!!
+ pthread_mutex_unlock(&mutex);
+ return NULL;
+}
+
+int main()
+{
+ pthread_mutex_init(&mutex, NULL);
+ pthread_cond_init(&cond, NULL);
+
+ pthread_mutex_lock(&mutex);
+ pthread_create(&thread, NULL, ThreadFunction, (void*) NULL);
+ while (!ready) { // to insure ourselves against spurious wakeups
+ pthread_cond_wait(&cond, &mutex);
+ }
+ pthread_mutex_unlock(&mutex);
+
+ pthread_join(thread, NULL);
+ pthread_mutex_destroy(&mutex);
+ printf("finished\n");
+ return 0;
+}
diff --git a/main/helgrind/tests/pth_destroy_cond.stderr.exp b/main/helgrind/tests/pth_destroy_cond.stderr.exp
new file mode 100644
index 0000000..4f9eeb7
--- /dev/null
+++ b/main/helgrind/tests/pth_destroy_cond.stderr.exp
@@ -0,0 +1,28 @@
+---Thread-Announcement------------------------------------------
+
+Thread #x was created
+ ...
+ by 0x........: pthread_create_WRK (hg_intercepts.c:...)
+ by 0x........: pthread_create@* (hg_intercepts.c:...)
+ by 0x........: main (pth_destroy_cond.c:29)
+
+----------------------------------------------------------------
+
+Thread #x: pthread_cond_destroy: destruction of condition variable being waited upon
+ at 0x........: pthread_cond_destroy_WRK (hg_intercepts.c:...)
+ by 0x........: pthread_cond_destroy@* (hg_intercepts.c:...)
+ by 0x........: ThreadFunction (pth_destroy_cond.c:18)
+ by 0x........: mythread_wrapper (hg_intercepts.c:...)
+ ...
+
+---Thread-Announcement------------------------------------------
+
+Thread #x is the program's root thread
+
+----------------------------------------------------------------
+
+Thread #x: condition variable has been destroyed while being waited upon
+ at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...)
+ by 0x........: pthread_cond_wait@* (hg_intercepts.c:...)
+ by 0x........: main (pth_destroy_cond.c:31)
+
diff --git a/main/helgrind/tests/pth_destroy_cond.stdout.exp b/main/helgrind/tests/pth_destroy_cond.stdout.exp
new file mode 100644
index 0000000..f656398
--- /dev/null
+++ b/main/helgrind/tests/pth_destroy_cond.stdout.exp
@@ -0,0 +1 @@
+finished
diff --git a/main/helgrind/tests/pth_destroy_cond.vgtest b/main/helgrind/tests/pth_destroy_cond.vgtest
new file mode 100644
index 0000000..3f1fdf4
--- /dev/null
+++ b/main/helgrind/tests/pth_destroy_cond.vgtest
@@ -0,0 +1,3 @@
+prog: pth_destroy_cond
+vgopts: -q
+stderr_filter_args: pth_destroy_cond.c
diff --git a/main/helgrind/tests/tc07_hbl1.c b/main/helgrind/tests/tc07_hbl1.c
index e5b11c4..92c74e0 100644
--- a/main/helgrind/tests/tc07_hbl1.c
+++ b/main/helgrind/tests/tc07_hbl1.c
@@ -14,6 +14,7 @@
#undef PLAT_ppc64_linux
#undef PLAT_arm_linux
#undef PLAT_s390x_linux
+#undef PLAT_mips32_linux
#if defined(__APPLE__) && defined(__i386__)
# define PLAT_x86_darwin 1
@@ -31,6 +32,8 @@
# define PLAT_arm_linux 1
#elif defined(__linux__) && defined(__s390x__)
# define PLAT_s390x_linux 1
+#elif defined(__linux__) && defined(__mips__)
+# define PLAT_mips32_linux 1
#endif
#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux) \
@@ -71,6 +74,20 @@
" jl 1b\n" \
: "+m" (_lval) :: "cc", "1","2" \
)
+#elif defined(PLAT_mips32_linux)
+# define INC(_lval,_lqual) \
+ __asm__ __volatile__ ( \
+ "1:\n" \
+ " move $8, %0\n" \
+ " ll $9, 0($8)\n" \
+ " addiu $9, $9, 1\n" \
+ " sc $9, 0($8)\n" \
+ " li $10, 1\n" \
+ " bne $9, $10, 1b\n" \
+ " nop\n" \
+ : /*out*/ : /*in*/ "r"(&(_lval)) \
+ : /*trash*/ "$8", "$9", "$10", "cc", "memory" \
+ )
#else
# error "Fix Me for this platform"
#endif
diff --git a/main/helgrind/tests/tc08_hbl2.c b/main/helgrind/tests/tc08_hbl2.c
index 8cc682b..b39f9ee 100644
--- a/main/helgrind/tests/tc08_hbl2.c
+++ b/main/helgrind/tests/tc08_hbl2.c
@@ -30,6 +30,7 @@
#undef PLAT_ppc64_linux
#undef PLAT_arm_linux
#undef PLAT_s390x_linux
+#undef PLAT_mips32_linux
#if defined(__APPLE__) && defined(__i386__)
# define PLAT_x86_darwin 1
@@ -47,6 +48,8 @@
# define PLAT_arm_linux 1
#elif defined(__linux__) && defined(__s390x__)
# define PLAT_s390x_linux 1
+#elif defined(__linux__) && defined(__mips__)
+# define PLAT_mips32_linux 1
#endif
@@ -88,6 +91,19 @@
" jl 1b\n" \
: "+m" (_lval) :: "cc", "0","1" \
)
+#elif defined(PLAT_mips32_linux)
+# define INC(_lval,_lqual) \
+ __asm__ __volatile__ ( \
+ "L1xyzzy1" _lqual":\n" \
+ " move $8, %0\n" \
+ " ll $9, 0($t0)\n" \
+ " addi $9, $9, 1\n" \
+ " sc $9, 0($t0)\n" \
+ " li $10, 1\n" \
+ " bne $9, $10, L1xyzzy1" _lqual \
+ : /*out*/ : /*in*/ "r"(&(_lval)) \
+ : /*trash*/ "$8", "$9", "$10", "cc", "memory" \
+ )
#else
# error "Fix Me for this platform"
#endif
diff --git a/main/helgrind/tests/tc11_XCHG.c b/main/helgrind/tests/tc11_XCHG.c
index ac85d82..fadc774 100644
--- a/main/helgrind/tests/tc11_XCHG.c
+++ b/main/helgrind/tests/tc11_XCHG.c
@@ -17,6 +17,7 @@
#undef PLAT_ppc64_linux
#undef PLAT_arm_linux
#undef PLAT_s390x_linux
+#undef PLAT_mips32_linux
#if defined(__APPLE__) && defined(__i386__)
# define PLAT_x86_darwin 1
@@ -34,6 +35,8 @@
# define PLAT_arm_linux 1
#elif defined(__linux__) && defined(__s390x__)
# define PLAT_s390x_linux 1
+#elif defined(__linux__) && defined(__mips__)
+# define PLAT_mips32_linux 1
#endif
@@ -71,6 +74,22 @@
# define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \
XCHG_M_R(_addr,_lval)
+#elif defined(PLAT_mips32_linux) || defined(PLAT_mips64_linux)
+# define XCHG_M_R(_addr,_lval) \
+ __asm__ __volatile__( \
+ "move $12, %2\n" \
+ "move $13, %1\n" \
+ "ll $14, 0($13)\n" \
+ "sc $12, 0($13)\n" \
+ "move %0, $14\n" \
+ : /*out*/ "=r"(_lval) \
+ : /*in*/ "r"(&_addr), "r"(_lval) \
+ : "$12", "$13", "$14", "memory", "cc" \
+ )
+
+# define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \
+ XCHG_M_R(_addr,_lval)
+
#elif defined(PLAT_ppc32_linux) || defined(PLAT_ppc64_linux) \
|| defined(PLAT_arm_linux)
# if defined(HAVE_BUILTIN_ATOMIC)
diff --git a/main/include/Makefile.am b/main/include/Makefile.am
index 9f3f4a0..ade27c2 100644
--- a/main/include/Makefile.am
+++ b/main/include/Makefile.am
@@ -13,7 +13,9 @@
pub_tool_errormgr.h \
pub_tool_execontext.h \
pub_tool_gdbserver.h \
+ pub_tool_poolalloc.h \
pub_tool_hashtable.h \
+ pub_tool_inner.h \
pub_tool_libcbase.h \
pub_tool_libcassert.h \
pub_tool_libcfile.h \
@@ -47,16 +49,19 @@
vki/vki-posixtypes-x86-linux.h \
vki/vki-posixtypes-arm-linux.h \
vki/vki-posixtypes-s390x-linux.h \
+ vki/vki-posixtypes-mips32-linux.h \
vki/vki-amd64-linux.h \
vki/vki-ppc32-linux.h \
vki/vki-ppc64-linux.h \
vki/vki-x86-linux.h \
vki/vki-arm-linux.h \
vki/vki-s390x-linux.h \
+ vki/vki-mips32-linux.h \
vki/vki-scnums-amd64-linux.h \
vki/vki-scnums-ppc32-linux.h \
vki/vki-scnums-ppc64-linux.h \
vki/vki-scnums-x86-linux.h \
vki/vki-scnums-arm-linux.h \
vki/vki-scnums-s390x-linux.h \
+ vki/vki-scnums-mips32-linux.h \
vki/vki-scnums-darwin.h
diff --git a/main/include/Makefile.in b/main/include/Makefile.in
new file mode 100644
index 0000000..4bd99e0
--- /dev/null
+++ b/main/include/Makefile.in
@@ -0,0 +1,537 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+subdir = include
+DIST_COMMON = $(nobase_pkginclude_HEADERS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+SOURCES =
+DIST_SOURCES =
+am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
+am__vpath_adj = case $$p in \
+ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
+ *) f=$$p;; \
+ esac;
+am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;
+am__install_max = 40
+am__nobase_strip_setup = \
+ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`
+am__nobase_strip = \
+ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"
+am__nobase_list = $(am__nobase_strip_setup); \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \
+ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \
+ if (++n[$$2] == $(am__install_max)) \
+ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \
+ END { for (dir in files) print dir, files[dir] }'
+am__base_list = \
+ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \
+ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'
+am__installdirs = "$(DESTDIR)$(pkgincludedir)"
+HEADERS = $(nobase_pkginclude_HEADERS)
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+
+# The "nobase" means that the vki/ path on some of them will be preserved
+# when they are installed into $(includedir)/valgrind.
+nobase_pkginclude_HEADERS = \
+ pub_tool_basics.h \
+ pub_tool_basics_asm.h \
+ pub_tool_aspacehl.h \
+ pub_tool_aspacemgr.h \
+ pub_tool_clientstate.h \
+ pub_tool_clreq.h \
+ pub_tool_cpuid.h \
+ pub_tool_debuginfo.h \
+ pub_tool_errormgr.h \
+ pub_tool_execontext.h \
+ pub_tool_gdbserver.h \
+ pub_tool_poolalloc.h \
+ pub_tool_hashtable.h \
+ pub_tool_inner.h \
+ pub_tool_libcbase.h \
+ pub_tool_libcassert.h \
+ pub_tool_libcfile.h \
+ pub_tool_libcprint.h \
+ pub_tool_libcproc.h \
+ pub_tool_libcsetjmp.h \
+ pub_tool_libcsignal.h \
+ pub_tool_machine.h \
+ pub_tool_mallocfree.h \
+ pub_tool_options.h \
+ pub_tool_oset.h \
+ pub_tool_redir.h \
+ pub_tool_replacemalloc.h \
+ pub_tool_seqmatch.h \
+ pub_tool_signals.h \
+ pub_tool_sparsewa.h \
+ pub_tool_stacktrace.h \
+ pub_tool_threadstate.h \
+ pub_tool_tooliface.h \
+ pub_tool_vki.h \
+ pub_tool_vkiscnums.h \
+ pub_tool_vkiscnums_asm.h \
+ pub_tool_wordfm.h \
+ pub_tool_xarray.h \
+ valgrind.h \
+ vki/vki-linux.h \
+ vki/vki-darwin.h \
+ vki/vki-posixtypes-amd64-linux.h \
+ vki/vki-posixtypes-ppc32-linux.h \
+ vki/vki-posixtypes-ppc64-linux.h \
+ vki/vki-posixtypes-x86-linux.h \
+ vki/vki-posixtypes-arm-linux.h \
+ vki/vki-posixtypes-s390x-linux.h \
+ vki/vki-posixtypes-mips32-linux.h \
+ vki/vki-amd64-linux.h \
+ vki/vki-ppc32-linux.h \
+ vki/vki-ppc64-linux.h \
+ vki/vki-x86-linux.h \
+ vki/vki-arm-linux.h \
+ vki/vki-s390x-linux.h \
+ vki/vki-mips32-linux.h \
+ vki/vki-scnums-amd64-linux.h \
+ vki/vki-scnums-ppc32-linux.h \
+ vki/vki-scnums-ppc64-linux.h \
+ vki/vki-scnums-x86-linux.h \
+ vki/vki-scnums-arm-linux.h \
+ vki/vki-scnums-s390x-linux.h \
+ vki/vki-scnums-mips32-linux.h \
+ vki/vki-scnums-darwin.h
+
+all: all-am
+
+.SUFFIXES:
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign include/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign include/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+install-nobase_pkgincludeHEADERS: $(nobase_pkginclude_HEADERS)
+ @$(NORMAL_INSTALL)
+ test -z "$(pkgincludedir)" || $(MKDIR_P) "$(DESTDIR)$(pkgincludedir)"
+ @list='$(nobase_pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ $(am__nobase_list) | while read dir files; do \
+ xfiles=; for file in $$files; do \
+ if test -f "$$file"; then xfiles="$$xfiles $$file"; \
+ else xfiles="$$xfiles $(srcdir)/$$file"; fi; done; \
+ test -z "$$xfiles" || { \
+ test "x$$dir" = x. || { \
+ echo "$(MKDIR_P) '$(DESTDIR)$(pkgincludedir)/$$dir'"; \
+ $(MKDIR_P) "$(DESTDIR)$(pkgincludedir)/$$dir"; }; \
+ echo " $(INSTALL_HEADER) $$xfiles '$(DESTDIR)$(pkgincludedir)/$$dir'"; \
+ $(INSTALL_HEADER) $$xfiles "$(DESTDIR)$(pkgincludedir)/$$dir" || exit $$?; }; \
+ done
+
+uninstall-nobase_pkgincludeHEADERS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(nobase_pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ $(am__nobase_strip_setup); files=`$(am__nobase_strip)`; \
+ test -n "$$files" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(pkgincludedir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(pkgincludedir)" && rm -f $$files
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+check: check-am
+all-am: Makefile $(HEADERS)
+installdirs:
+ for dir in "$(DESTDIR)$(pkgincludedir)"; do \
+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ done
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-generic mostlyclean-am
+
+distclean: distclean-am
+ -rm -f Makefile
+distclean-am: clean-am distclean-generic distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am: install-nobase_pkgincludeHEADERS
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am: uninstall-nobase_pkgincludeHEADERS
+
+.MAKE: install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \
+ ctags distclean distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man \
+ install-nobase_pkgincludeHEADERS install-pdf install-pdf-am \
+ install-ps install-ps-am install-strip installcheck \
+ installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-generic pdf \
+ pdf-am ps ps-am tags uninstall uninstall-am \
+ uninstall-nobase_pkgincludeHEADERS
+
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/include/pub_tool_aspacehl.h b/main/include/pub_tool_aspacehl.h
index 6114631..82cebad 100644
--- a/main/include/pub_tool_aspacehl.h
+++ b/main/include/pub_tool_aspacehl.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2009-2011 Julian Seward
+ Copyright (C) 2009-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_aspacemgr.h b/main/include/pub_tool_aspacemgr.h
index a2862c7..3f02cfc 100644
--- a/main/include/pub_tool_aspacemgr.h
+++ b/main/include/pub_tool_aspacemgr.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_basics.h b/main/include/pub_tool_basics.h
index ae7bae6..92c0697 100644
--- a/main/include/pub_tool_basics.h
+++ b/main/include/pub_tool_basics.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -163,6 +163,7 @@
typedef
struct {
UWord _val;
+ UWord _valEx; // only used on mips-linux
Bool _isError;
}
SysRes;
@@ -197,6 +198,9 @@
static inline UWord sr_Res ( SysRes sr ) {
return sr._isError ? 0 : sr._val;
}
+static inline UWord sr_ResEx ( SysRes sr ) {
+ return sr._isError ? 0 : sr._valEx;
+}
static inline UWord sr_ResHI ( SysRes sr ) {
return 0;
}
@@ -264,9 +268,11 @@
#undef VG_BIGENDIAN
#undef VG_LITTLEENDIAN
-#if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm)
+#if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm) \
+ || (defined(VGA_mips32) && defined (_MIPSEL))
# define VG_LITTLEENDIAN 1
-#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x)
+#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x) \
+ || (defined(VGA_mips32) && defined (_MIPSEB))
# define VG_BIGENDIAN 1
#else
# error Unknown arch
@@ -276,7 +282,8 @@
#if defined(VGA_x86)
# define VG_REGPARM(n) __attribute__((regparm(n)))
#elif defined(VGA_amd64) || defined(VGA_ppc32) \
- || defined(VGA_ppc64) || defined(VGA_arm) || defined(VGA_s390x)
+ || defined(VGA_ppc64) || defined(VGA_arm) || defined(VGA_s390x) \
+ || defined(VGA_mips32)
# define VG_REGPARM(n) /* */
#else
# error Unknown arch
diff --git a/main/include/pub_tool_basics_asm.h b/main/include/pub_tool_basics_asm.h
index a22be33..d96f41b 100644
--- a/main/include/pub_tool_basics_asm.h
+++ b/main/include/pub_tool_basics_asm.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_clientstate.h b/main/include/pub_tool_clientstate.h
index 76bf115..d2d8a06 100644
--- a/main/include/pub_tool_clientstate.h
+++ b/main/include/pub_tool_clientstate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_clreq.h b/main/include/pub_tool_clreq.h
index 7643fb2..cd8f4c9 100644
--- a/main/include/pub_tool_clreq.h
+++ b/main/include/pub_tool_clreq.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_cpuid.h b/main/include/pub_tool_cpuid.h
index 1307546..149131a 100644
--- a/main/include/pub_tool_cpuid.h
+++ b/main/include/pub_tool_cpuid.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_debuginfo.h b/main/include/pub_tool_debuginfo.h
index c0c96bf..0604c9b 100644
--- a/main/include/pub_tool_debuginfo.h
+++ b/main/include/pub_tool_debuginfo.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_errormgr.h b/main/include/pub_tool_errormgr.h
index 3d80ebf..c36487b 100644
--- a/main/include/pub_tool_errormgr.h
+++ b/main/include/pub_tool_errormgr.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_execontext.h b/main/include/pub_tool_execontext.h
index 13df963..ec890e4 100644
--- a/main/include/pub_tool_execontext.h
+++ b/main/include/pub_tool_execontext.h
@@ -6,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -67,7 +67,7 @@
// might cause a segfault. In this case we can at least safely
// produce a one-element stack trace, which is better than nothing.
extern
-ExeContext* VG_(record_depth_1_ExeContext)( ThreadId tid );
+ExeContext* VG_(record_depth_1_ExeContext)(ThreadId tid, Word first_ip_delta);
// Apply a function to every element in the ExeContext. The parameter 'n'
// gives the index of the passed ip. Doesn't go below main() unless
diff --git a/main/include/pub_tool_gdbserver.h b/main/include/pub_tool_gdbserver.h
index 87ba3e2..b49e681 100644
--- a/main/include/pub_tool_gdbserver.h
+++ b/main/include/pub_tool_gdbserver.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2011-2011 Philippe Waroquiers
+ Copyright (C) 2011-2012 Philippe Waroquiers
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/include/pub_tool_hashtable.h b/main/include/pub_tool_hashtable.h
index d2a0d4a..f844c88 100644
--- a/main/include/pub_tool_hashtable.h
+++ b/main/include/pub_tool_hashtable.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -90,8 +90,9 @@
assurance. */
extern void* VG_(HT_Next) ( VgHashTable table );
-/* Destroy a table. */
-extern void VG_(HT_destruct) ( VgHashTable t );
+/* Destroy a table and deallocates the memory used by the nodes using
+ freenode_fn.*/
+extern void VG_(HT_destruct) ( VgHashTable t, void(*freenode_fn)(void*) );
#endif // __PUB_TOOL_HASHTABLE_H
diff --git a/main/include/pub_tool_inner.h b/main/include/pub_tool_inner.h
new file mode 100644
index 0000000..88c9b35
--- /dev/null
+++ b/main/include/pub_tool_inner.h
@@ -0,0 +1,72 @@
+
+/*--------------------------------------------------------------------*/
+/*--- Utilities for inner Valgrind pub_tool_inner.h ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2012-2012 Philippe Waroquiers
+ philippe.waroquiers@skynet.be
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __PUB_TOOL_INNER_H
+#define __PUB_TOOL_INNER_H
+
+//--------------------------------------------------------------------
+// PURPOSE: This header should be imported by every file in Valgrind
+// which needs specific behaviour when running as an "inner" Valgrind.
+// Valgrind can self-host itself (i.e. Valgrind can run Valgrind) :
+// The outer Valgrind executes the inner Valgrind.
+// For more details, see README_DEVELOPPERS.
+//--------------------------------------------------------------------
+
+#include "config.h"
+
+// The code of the inner Valgrind (core or tool code) contains client
+// requests (e.g. from helgrind.h, memcheck.h, ...) to help the
+// outer Valgrind finding (relevant) errors in the inner Valgrind.
+// Such client requests should only be compiled in for an inner Valgrind.
+// Use the macro INNER_REQUEST to allow a central enabling/disabling
+// of these client requests.
+#if defined(ENABLE_INNER)
+
+// By default, the client requests
+// undefine the below to have an inner Valgrind without any annotation.
+#define ENABLE_INNER_CLIENT_REQUEST 1
+
+#if defined(ENABLE_INNER_CLIENT_REQUEST)
+#define INNER_REQUEST(__zza) __zza
+#else
+#define INNER_REQUEST(__zza) do {} while (0)
+#endif
+
+#else
+
+#define INNER_REQUEST(__zza) do {} while (0)
+
+#endif
+
+#endif // __PUB_TOOL_INNER_H
+
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/include/pub_tool_libcassert.h b/main/include/pub_tool_libcassert.h
index 0aa2cb3..ea38c97 100644
--- a/main/include/pub_tool_libcassert.h
+++ b/main/include/pub_tool_libcassert.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_libcbase.h b/main/include/pub_tool_libcbase.h
index 8034116..14c917b 100644
--- a/main/include/pub_tool_libcbase.h
+++ b/main/include/pub_tool_libcbase.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_libcfile.h b/main/include/pub_tool_libcfile.h
index 0acdc71..9777a3d 100644
--- a/main/include/pub_tool_libcfile.h
+++ b/main/include/pub_tool_libcfile.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -78,7 +78,6 @@
extern Int VG_(write) ( Int fd, const void* buf, Int count);
extern Int VG_(pipe) ( Int fd[2] );
extern Off64T VG_(lseek) ( Int fd, Off64T offset, Int whence );
-extern Int VG_(ftruncate) ( Int fd, OffT length );
extern SysRes VG_(stat) ( const Char* file_name, struct vg_stat* buf );
extern Int VG_(fstat) ( Int fd, struct vg_stat* buf );
diff --git a/main/include/pub_tool_libcprint.h b/main/include/pub_tool_libcprint.h
index 697bff3..0dc9224 100644
--- a/main/include/pub_tool_libcprint.h
+++ b/main/include/pub_tool_libcprint.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_libcproc.h b/main/include/pub_tool_libcproc.h
index 190bd5a..c580f51 100644
--- a/main/include/pub_tool_libcproc.h
+++ b/main/include/pub_tool_libcproc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_libcsetjmp.h b/main/include/pub_tool_libcsetjmp.h
index 3c25365..22f560b 100644
--- a/main/include/pub_tool_libcsetjmp.h
+++ b/main/include/pub_tool_libcsetjmp.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2010-2011 Mozilla Inc
+ Copyright (C) 2010-2012 Mozilla Inc
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/include/pub_tool_libcsignal.h b/main/include/pub_tool_libcsignal.h
index 33043a0..bc5bc9c 100644
--- a/main/include/pub_tool_libcsignal.h
+++ b/main/include/pub_tool_libcsignal.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_machine.h b/main/include/pub_tool_machine.h
index c86fff0..026db6b 100644
--- a/main/include/pub_tool_machine.h
+++ b/main/include/pub_tool_machine.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -83,6 +83,12 @@
# define VG_CLREQ_SZB 19
# define VG_STACK_REDZONE_SZB 128
+#elif defined(VGP_mips32_linux)
+# define VG_MIN_INSTR_SZB 4
+# define VG_MAX_INSTR_SZB 4
+# define VG_CLREQ_SZB 20
+# define VG_STACK_REDZONE_SZB 0
+
#else
# error Unknown platform
#endif
@@ -121,7 +127,8 @@
// current threads.
// This is very Memcheck-specific -- it's used to find the roots when
// doing leak checking.
-extern void VG_(apply_to_GP_regs)(void (*f)(UWord val));
+extern void VG_(apply_to_GP_regs)(void (*f)(ThreadId tid,
+ HChar* regname, UWord val));
// This iterator lets you inspect each live thread's stack bounds.
// Returns False at the end. 'tid' is the iterator and you can only
@@ -151,6 +158,12 @@
// ppc64-linux it isn't (sigh).
extern void* VG_(fnptr_to_fnentry)( void* );
+/* Returns the size of the largest guest register that we will
+ simulate in this run. This depends on both the guest architecture
+ and on the specific capabilities we are simulating for that guest
+ (eg, AVX or non-AVX ?, for amd64). */
+extern Int VG_(machine_get_size_of_largest_guest_register) ( void );
+
#endif // __PUB_TOOL_MACHINE_H
/*--------------------------------------------------------------------*/
diff --git a/main/include/pub_tool_mallocfree.h b/main/include/pub_tool_mallocfree.h
index a71a1ff..2121665 100644
--- a/main/include/pub_tool_mallocfree.h
+++ b/main/include/pub_tool_mallocfree.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -47,6 +47,14 @@
// possibly some more due to rounding up.
extern SizeT VG_(malloc_usable_size)( void* p );
+// If tool is replacing malloc for the client, the below returns
+// the effective client redzone as derived from the default
+// provided by the tool, VG_(clo_redzone_size) and the minimum
+// redzone required by m_mallocfree.c.
+// It is an error to call this before VG_(needs_malloc_replacement) has
+// been called.
+extern SizeT VG_(malloc_effective_client_redzone_size)(void);
+
// TODO: move somewhere else
// Call here to bomb the system when out of memory (mmap anon fails)
__attribute__((noreturn))
diff --git a/main/include/pub_tool_options.h b/main/include/pub_tool_options.h
index c37c7be..fd90f44 100644
--- a/main/include/pub_tool_options.h
+++ b/main/include/pub_tool_options.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_oset.h b/main/include/pub_tool_oset.h
index 204e54b..2f8152d 100644
--- a/main/include/pub_tool_oset.h
+++ b/main/include/pub_tool_oset.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -160,11 +160,18 @@
// - cmp The comparison function between keys and elements, or NULL
// if the OSet should use fast comparisons.
// - alloc The allocation function used for allocating the OSet itself;
-// it's also called for each invocation of
-// VG_(OSetGen_AllocNode)().
+// If a pool allocator is used, it's called to allocate pool of
+// nodes.
+// If no pool allocator is used, it's called for each
+// invocation of VG_(OSetGen_AllocNode)().
// - cc Cost centre string used by 'alloc'.
-// - free The deallocation function used by VG_(OSetGen_FreeNode)() and
+// - free If no pool allocator is used, this is the deallocation
+// function used by VG_(OSetGen_FreeNode)() and
// VG_(OSetGen_Destroy)().
+// If a pool allocator is used, the memory used by the nodes is
+// deallocated when the pool is deleted.
+// (for more details about pool allocators, see pub_tool_poolalloc.h).
+//
//
// If cmp is NULL, keyOff must be zero. This is checked.
//
@@ -174,9 +181,13 @@
// called.
//
// * AllocNode: Allocate and zero memory for a node to go into the OSet.
-// Uses the alloc function given to VG_(OSetGen_Create)() to allocated a
-// node which is big enough for both an element and the OSet metadata.
+// If a pool allocator is used, it uses the pool allocator to allocate a node.
+// Otherwise, uses the alloc function given to VG_(OSetGen_Create)() to
+// allocate a node which is big enough for both an element and the OSet
+// metadata.
// Not all elements in one OSet have to be the same size.
+// However, if a pool allocator is used, elements will all have a size equal
+// to the max user data size given at creation + the node meta data size.
//
// Note that the element allocated will be at most word-aligned, which may
// be less aligned than the element type would normally be.
@@ -187,12 +198,48 @@
extern OSet* VG_(OSetGen_Create) ( PtrdiffT keyOff, OSetCmp_t cmp,
OSetAlloc_t alloc, HChar* cc,
- OSetFree_t _free );
+ OSetFree_t _free);
+
+
+extern OSet* VG_(OSetGen_Create_With_Pool) ( PtrdiffT keyOff, OSetCmp_t cmp,
+ OSetAlloc_t alloc, HChar* cc,
+ OSetFree_t _free,
+ SizeT poolSize,
+ SizeT maxEltSize);
+// Same as VG_(OSetGen_Create) but created OSet will use a pool allocator to
+// allocate the nodes.
+// The node size is the sum of a fixed small meta data size needed for OSet
+// + the size of the user data element.
+// The maximum size for the user data element is specified by maxEltSize.
+// (if poolSize is 0, maxEltSize is not relevant for the OSet).
+// It is interesting to use a pool allocator when an OSet has many elements,
+// and these elements have a small fixed size, or have a variable size, but
+// always <= than a (small) maximum value.
+// In such a case, allocating the nodes in pools reduces significantly
+// the memory overhead needed by each node.
+// When a node is freed (i.e. OsetGen_Freenode is called), the node is
+// put back in the pool allocator free list (for sub-sequent re-use by
+// Osetgen_Allocnode). Note that the pool memory is only released when
+// the pool is destroyed : calls to VG_(OSetGen_Free) do not cause
+// any calls to OsetFree_t _free function.
+// If there are several OSet managing similar such elements, it might be
+// interesting to use a shared pool for these OSet.
+// To have multiple OSets sharing a pool allocator, create the first OSet
+// with VG_(OSetGen_Create). Create subsequent OSet with
+// VG_(OSetGen_EmptyClone).
+
extern void VG_(OSetGen_Destroy) ( OSet* os );
extern void* VG_(OSetGen_AllocNode) ( OSet* os, SizeT elemSize );
extern void VG_(OSetGen_FreeNode) ( OSet* os, void* elem );
-/*--------------------------------------------------------------------*/
+extern OSet* VG_(OSetGen_EmptyClone) (OSet* os);
+// Creates a new empty OSet.
+// The new OSet will have the same characteristics as os.
+// If os uses a pool allocator, this pool allocator will be shared with
+// the new OSet. A shared pool allocator is only deleted (and its memory is
+// released) when the last OSet using the shared pool is destroyed.
+
+/*-------------------------------------------------------------------*/
/*--- Operations on OSets (Gen) ---*/
/*--------------------------------------------------------------------*/
diff --git a/main/include/pub_tool_poolalloc.h b/main/include/pub_tool_poolalloc.h
new file mode 100644
index 0000000..bc50daa
--- /dev/null
+++ b/main/include/pub_tool_poolalloc.h
@@ -0,0 +1,92 @@
+
+/*--------------------------------------------------------------------*/
+/*--- A simple pool (memory) allocator. pub_tool_poolalloc.h ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2011-2012 OpenWorks LLP info@open-works.co.uk,
+ Philippe Waroquiers philippe.waroquiers@skynet.be
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __PUB_TOOL_GROUPALLOC_H
+#define __PUB_TOOL_GROUPALLOC_H
+
+//--------------------------------------------------------------------
+// PURPOSE: Provides efficient allocation and free of elements of
+// the same size.
+// This pool allocator manages elements alloc/free by allocating
+// "pools" of many elements from a lower level allocator (typically
+// pub_tool_mallocfree.h).
+// Single elements can then be allocated and released from these pools.
+// A pool allocator is faster and has less memory overhead than
+// calling directly pub_tool_mallocfree.h
+// Note: the pools of elements are not freed, even if all the
+// single elements have been freed. The only way to free the underlying
+// pools of elements is to delete the pool allocator.
+//--------------------------------------------------------------------
+
+
+typedef struct _PoolAlloc PoolAlloc;
+
+/* Create new PoolAlloc, using given allocation and free function, and
+ for elements of the specified size. Alloc fn must not fail (that
+ is, if it returns it must have succeeded.) */
+PoolAlloc* VG_(newPA) ( UWord elemSzB,
+ UWord nPerPool,
+ void* (*alloc)(HChar*, SizeT),
+ HChar* cc,
+ void (*free_fn)(void*) );
+
+
+/* Free all memory associated with a PoolAlloc. */
+extern void VG_(deletePA) ( PoolAlloc* pa);
+
+/* Allocates an element from pa. */
+extern void* VG_(allocEltPA) ( PoolAlloc* pa);
+
+/* Free element of pa. */
+extern void VG_(freeEltPA) ( PoolAlloc* pa, void* p);
+
+/* A pool allocator can be shared between multiple data structures.
+ For example, multiple OSet* can allocate/free nodes from the same
+ pool allocator.
+ The Pool Allocator provides support to use a ref counter
+ to detect a pool allocator is not needed anymore.
+ It is the caller responsibility to delete the PA if the ref counter
+ drops to 0. In other words, this just helps the caller to manage
+ the PA memory destruction but it does not fully manage it.
+ Note that the usage of pool reference counting is optional. */
+
+// VG_(addRefPA) indicates there is a new reference to pa.
+extern void VG_(addRefPA) ( PoolAlloc* pa);
+
+// VG_(releasePA) decrements the pa reference count and deletes the pa if that
+// reference count has dropped to zero. Returns the new value of the reference
+// count.
+extern UWord VG_(releasePA) ( PoolAlloc* pa);
+
+#endif // __PUB_TOOL_POOLALLOC_
+
+/*--------------------------------------------------------------------*/
+/*--- end pub_tool_poolalloc.h ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/include/pub_tool_redir.h b/main/include/pub_tool_redir.h
index 738f433..e4ea7c0 100644
--- a/main/include/pub_tool_redir.h
+++ b/main/include/pub_tool_redir.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -246,7 +246,7 @@
#elif defined(VGO_darwin) && (DARWIN_VERS <= DARWIN_10_6)
# define VG_Z_LIBC_SONAME libSystemZdZaZddylib // libSystem.*.dylib
-#elif defined(VGO_darwin) && (DARWIN_VERS == DARWIN_10_7)
+#elif defined(VGO_darwin) && (DARWIN_VERS >= DARWIN_10_7)
# define VG_Z_LIBC_SONAME libsystemZucZaZddylib // libsystem_c*.dylib
#else
@@ -300,6 +300,11 @@
#endif
+// Prefix for synonym soname synonym handling
+#define VG_SO_SYN(name) VgSoSyn##name
+#define VG_SO_SYN_PREFIX "VgSoSyn"
+#define VG_SO_SYN_PREFIX_LEN 7
+
#endif // __PUB_TOOL_REDIR_H
/*--------------------------------------------------------------------*/
diff --git a/main/include/pub_tool_replacemalloc.h b/main/include/pub_tool_replacemalloc.h
index 1f07ac4..3b6b927 100644
--- a/main/include/pub_tool_replacemalloc.h
+++ b/main/include/pub_tool_replacemalloc.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_seqmatch.h b/main/include/pub_tool_seqmatch.h
index cb025ec..c095599 100644
--- a/main/include/pub_tool_seqmatch.h
+++ b/main/include/pub_tool_seqmatch.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks Ltd
+ Copyright (C) 2008-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -69,6 +69,12 @@
equal. Note that the pattern element is guaranteed to be neither
(conceptually) '*' nor '?', so it must be a literal (in the sense
that all the input sequence elements are literal).
+
+ input might be lazily constructed when pattEQinp is called.
+ For lazily constructing the input element, the two last arguments
+ of pattEQinp are the inputCompleter and the index of the input
+ element to complete.
+ inputCompleter can be NULL.
*/
Bool VG_(generic_match) (
Bool matchAll,
@@ -76,7 +82,8 @@
void* input, SizeT szbInput, UWord nInput, UWord ixInput,
Bool (*pIsStar)(void*),
Bool (*pIsQuery)(void*),
- Bool (*pattEQinp)(void*,void*)
+ Bool (*pattEQinp)(void*,void*,void*,UWord),
+ void* inputCompleter
);
/* Mini-regexp function. Searches for 'pat' in 'str'. Supports
diff --git a/main/include/pub_tool_signals.h b/main/include/pub_tool_signals.h
index 0596315..e540636 100644
--- a/main/include/pub_tool_signals.h
+++ b/main/include/pub_tool_signals.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_sparsewa.h b/main/include/pub_tool_sparsewa.h
index 5505a50..3c411b9 100644
--- a/main/include/pub_tool_sparsewa.h
+++ b/main/include/pub_tool_sparsewa.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 OpenWorks Ltd
+ Copyright (C) 2008-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_stacktrace.h b/main/include/pub_tool_stacktrace.h
index fef6865..8501e0a 100644
--- a/main/include/pub_tool_stacktrace.h
+++ b/main/include/pub_tool_stacktrace.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_threadstate.h b/main/include/pub_tool_threadstate.h
index 8fc3369..a2a41a5 100644
--- a/main/include/pub_tool_threadstate.h
+++ b/main/include/pub_tool_threadstate.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -36,11 +36,7 @@
scheduler algorithms is surely O(N) in the number of threads, since
that's simple, at least. And (in practice) we hope that most
programs do not need many threads. */
-#if defined(VGO_darwin) || defined(ANDROID)
#define VG_N_THREADS 500
-#else
-#define VG_N_THREADS 10000
-#endif
/* Special magic value for an invalid ThreadId. It corresponds to
LinuxThreads using zero as the initial value for
diff --git a/main/include/pub_tool_tooliface.h b/main/include/pub_tool_tooliface.h
index da521c4..a30961c 100644
--- a/main/include/pub_tool_tooliface.h
+++ b/main/include/pub_tool_tooliface.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -663,7 +663,6 @@
ll_exit (in the child's context)
*/
void VG_(track_pre_thread_ll_create) (void(*f)(ThreadId tid, ThreadId child));
-void VG_(track_workq_task_start) (void(*f)(ThreadId tid, Addr workitem));
void VG_(track_pre_thread_first_insn)(void(*f)(ThreadId tid));
void VG_(track_pre_thread_ll_exit) (void(*f)(ThreadId tid));
diff --git a/main/include/pub_tool_vki.h b/main/include/pub_tool_vki.h
index 921c159..a0996f9 100644
--- a/main/include/pub_tool_vki.h
+++ b/main/include/pub_tool_vki.h
@@ -8,11 +8,11 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_vkiscnums.h b/main/include/pub_tool_vkiscnums.h
index 4303d17..5eff7ae 100644
--- a/main/include/pub_tool_vkiscnums.h
+++ b/main/include/pub_tool_vkiscnums.h
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
diff --git a/main/include/pub_tool_vkiscnums_asm.h b/main/include/pub_tool_vkiscnums_asm.h
index 018cb19..dece742 100644
--- a/main/include/pub_tool_vkiscnums_asm.h
+++ b/main/include/pub_tool_vkiscnums_asm.h
@@ -7,9 +7,9 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
- Copyright (C) 2006-2011 OpenWorks LLP
+ Copyright (C) 2006-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -51,6 +51,9 @@
#elif defined(VGP_arm_linux)
# include "vki/vki-scnums-arm-linux.h"
+#elif defined(VGP_mips32_linux)
+# include "vki/vki-scnums-mips32-linux.h"
+
#elif defined(VGP_x86_darwin) || defined(VGP_amd64_darwin)
# include "vki/vki-scnums-darwin.h"
diff --git a/main/include/pub_tool_wordfm.h b/main/include/pub_tool_wordfm.h
index bdc325b..ea6c5f3 100644
--- a/main/include/pub_tool_wordfm.h
+++ b/main/include/pub_tool_wordfm.h
@@ -9,13 +9,13 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2011 Julian Seward
+ Copyright (C) 2007-2012 Julian Seward
jseward@acm.org
This code is based on previous work by Nicholas Nethercote
(coregrind/m_oset.c) which is
- Copyright (C) 2005-2011 Nicholas Nethercote
+ Copyright (C) 2005-2012 Nicholas Nethercote
njn@valgrind.org
which in turn was derived partially from:
diff --git a/main/include/pub_tool_xarray.h b/main/include/pub_tool_xarray.h
index 9b69987..2e1b7d4 100644
--- a/main/include/pub_tool_xarray.h
+++ b/main/include/pub_tool_xarray.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2011 OpenWorks LLP
+ Copyright (C) 2007-2012 OpenWorks LLP
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -117,6 +117,12 @@
is the number of elements remaining in the XArray. */
extern void VG_(dropHeadXA) ( XArray*, Word );
+/* Remove the specified element of an XArray, and slide all elements
+ beyond it back one place. This is an O(N) operation, where N is
+ the number of elements after the specified element, in the
+ array. */
+extern void VG_(removeIndexXA)( XArray*, Word );
+
/* Make a new, completely independent copy of the given XArray, using
the existing allocation function to allocate the new space.
Returns NULL if the allocation function didn't manage to allocate
diff --git a/main/include/valgrind.h b/main/include/valgrind.h
index 222a58e..cc2cf3d 100644
--- a/main/include/valgrind.h
+++ b/main/include/valgrind.h
@@ -12,7 +12,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward. All rights reserved.
+ Copyright (C) 2000-2012 Julian Seward. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
@@ -89,7 +89,7 @@
|| (__VALGRIND_MAJOR__ == 3 && __VALGRIND_MINOR__ >= 6))
*/
#define __VALGRIND_MAJOR__ 3
-#define __VALGRIND_MINOR__ 6
+#define __VALGRIND_MINOR__ 8
#include <stdarg.h>
@@ -117,6 +117,7 @@
#undef PLAT_ppc64_linux
#undef PLAT_arm_linux
#undef PLAT_s390x_linux
+#undef PLAT_mips32_linux
#if defined(__APPLE__) && defined(__i386__)
@@ -138,6 +139,8 @@
# define PLAT_arm_linux 1
#elif defined(__linux__) && defined(__s390__) && defined(__s390x__)
# define PLAT_s390x_linux 1
+#elif defined(__linux__) && defined(__mips__)
+# define PLAT_mips32_linux 1
#else
/* If we're not compiling for our target platform, don't generate
any inline asms. */
@@ -665,6 +668,70 @@
#endif /* PLAT_s390x_linux */
+/* ------------------------- mips32-linux ---------------- */
+
+#if defined(PLAT_mips32_linux)
+
+typedef
+ struct {
+ unsigned int nraddr; /* where's the code? */
+ }
+ OrigFn;
+
+/* .word 0x342
+ * .word 0x742
+ * .word 0xC2
+ * .word 0x4C2*/
+#define __SPECIAL_INSTRUCTION_PREAMBLE \
+ "srl $0, $0, 13\n\t" \
+ "srl $0, $0, 29\n\t" \
+ "srl $0, $0, 3\n\t" \
+ "srl $0, $0, 19\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
+ _zzq_default, _zzq_request, \
+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+ __extension__ \
+ ({ volatile unsigned int _zzq_args[6]; \
+ volatile unsigned int _zzq_result; \
+ _zzq_args[0] = (unsigned int)(_zzq_request); \
+ _zzq_args[1] = (unsigned int)(_zzq_arg1); \
+ _zzq_args[2] = (unsigned int)(_zzq_arg2); \
+ _zzq_args[3] = (unsigned int)(_zzq_arg3); \
+ _zzq_args[4] = (unsigned int)(_zzq_arg4); \
+ _zzq_args[5] = (unsigned int)(_zzq_arg5); \
+ __asm__ volatile("move $11, %1\n\t" /*default*/ \
+ "move $12, %2\n\t" /*ptr*/ \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* T3 = client_request ( T4 ) */ \
+ "or $13, $13, $13\n\t" \
+ "move %0, $11\n\t" /*result*/ \
+ : "=r" (_zzq_result) \
+ : "r" (_zzq_default), "r" (&_zzq_args[0]) \
+ : "cc","memory", "t3", "t4"); \
+ _zzq_result; \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %t9 = guest_NRADDR */ \
+ "or $14, $14, $14\n\t" \
+ "move %0, $11" /*result*/ \
+ : "=r" (__addr) \
+ : \
+ : "cc", "memory" , "t3" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+#define VALGRIND_CALL_NOREDIR_T9 \
+ __SPECIAL_INSTRUCTION_PREAMBLE \
+ /* call-noredir *%t9 */ \
+ "or $15, $15, $15\n\t"
+#endif /* PLAT_mips32_linux */
+
/* Insert assembly code for other platforms here... */
#endif /* NVALGRIND */
@@ -715,6 +782,18 @@
macros. The type of the argument _lval is OrigFn. */
#define VALGRIND_GET_ORIG_FN(_lval) VALGRIND_GET_NR_CONTEXT(_lval)
+/* Also provide end-user facilities for function replacement, rather
+ than wrapping. A replacement function differs from a wrapper in
+ that it has no way to get hold of the original function being
+ called, and hence no way to call onwards to it. In a replacement
+ function, VALGRIND_GET_ORIG_FN always returns zero. */
+
+#define I_REPLACE_SONAME_FNNAME_ZU(soname,fnname) \
+ VG_CONCAT4(_vgr00000ZU_,soname,_,fnname)
+
+#define I_REPLACE_SONAME_FNNAME_ZZ(soname,fnname) \
+ VG_CONCAT4(_vgr00000ZZ_,soname,_,fnname)
+
/* Derivatives of the main macros below, for calling functions
returning void. */
@@ -758,6 +837,17 @@
as gcc can already see that, plus causes gcc to bomb. */
#define __CALLER_SAVED_REGS /*"eax"*/ "ecx", "edx"
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+#define VALGRIND_ALIGN_STACK \
+ "movl %%esp,%%edi\n\t" \
+ "andl $0xfffffff0,%%esp\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "movl %%edi,%%esp\n\t"
+
/* These CALL_FN_ macros assume that on x86-linux, sizeof(unsigned
long) == 4. */
@@ -768,11 +858,13 @@
volatile unsigned long _res; \
_argvec[0] = (unsigned long)_orig.nraddr; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -785,14 +877,15 @@
_argvec[0] = (unsigned long)_orig.nraddr; \
_argvec[1] = (unsigned long)(arg1); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"subl $12, %%esp\n\t" \
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $16, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -806,15 +899,16 @@
_argvec[1] = (unsigned long)(arg1); \
_argvec[2] = (unsigned long)(arg2); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"subl $8, %%esp\n\t" \
"pushl 8(%%eax)\n\t" \
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $16, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -829,16 +923,17 @@
_argvec[2] = (unsigned long)(arg2); \
_argvec[3] = (unsigned long)(arg3); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"subl $4, %%esp\n\t" \
"pushl 12(%%eax)\n\t" \
"pushl 8(%%eax)\n\t" \
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $16, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -854,16 +949,17 @@
_argvec[3] = (unsigned long)(arg3); \
_argvec[4] = (unsigned long)(arg4); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"pushl 16(%%eax)\n\t" \
"pushl 12(%%eax)\n\t" \
"pushl 8(%%eax)\n\t" \
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $16, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -880,6 +976,7 @@
_argvec[4] = (unsigned long)(arg4); \
_argvec[5] = (unsigned long)(arg5); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"subl $12, %%esp\n\t" \
"pushl 20(%%eax)\n\t" \
"pushl 16(%%eax)\n\t" \
@@ -888,10 +985,10 @@
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $32, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -909,6 +1006,7 @@
_argvec[5] = (unsigned long)(arg5); \
_argvec[6] = (unsigned long)(arg6); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"subl $8, %%esp\n\t" \
"pushl 24(%%eax)\n\t" \
"pushl 20(%%eax)\n\t" \
@@ -918,10 +1016,10 @@
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $32, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -941,6 +1039,7 @@
_argvec[6] = (unsigned long)(arg6); \
_argvec[7] = (unsigned long)(arg7); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"subl $4, %%esp\n\t" \
"pushl 28(%%eax)\n\t" \
"pushl 24(%%eax)\n\t" \
@@ -951,10 +1050,10 @@
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $32, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -975,6 +1074,7 @@
_argvec[7] = (unsigned long)(arg7); \
_argvec[8] = (unsigned long)(arg8); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"pushl 32(%%eax)\n\t" \
"pushl 28(%%eax)\n\t" \
"pushl 24(%%eax)\n\t" \
@@ -985,10 +1085,10 @@
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $32, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1010,6 +1110,7 @@
_argvec[8] = (unsigned long)(arg8); \
_argvec[9] = (unsigned long)(arg9); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"subl $12, %%esp\n\t" \
"pushl 36(%%eax)\n\t" \
"pushl 32(%%eax)\n\t" \
@@ -1022,10 +1123,10 @@
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $48, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1048,6 +1149,7 @@
_argvec[9] = (unsigned long)(arg9); \
_argvec[10] = (unsigned long)(arg10); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"subl $8, %%esp\n\t" \
"pushl 40(%%eax)\n\t" \
"pushl 36(%%eax)\n\t" \
@@ -1061,10 +1163,10 @@
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $48, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1089,6 +1191,7 @@
_argvec[10] = (unsigned long)(arg10); \
_argvec[11] = (unsigned long)(arg11); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"subl $4, %%esp\n\t" \
"pushl 44(%%eax)\n\t" \
"pushl 40(%%eax)\n\t" \
@@ -1103,10 +1206,10 @@
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $48, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1132,6 +1235,7 @@
_argvec[11] = (unsigned long)(arg11); \
_argvec[12] = (unsigned long)(arg12); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"pushl 48(%%eax)\n\t" \
"pushl 44(%%eax)\n\t" \
"pushl 40(%%eax)\n\t" \
@@ -1146,10 +1250,10 @@
"pushl 4(%%eax)\n\t" \
"movl (%%eax), %%eax\n\t" /* target->%eax */ \
VALGRIND_CALL_NOREDIR_EAX \
- "addl $48, %%esp\n" \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=a" (_res) \
: /*in*/ "a" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "edi" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1237,6 +1341,16 @@
# define VALGRIND_CFI_EPILOGUE
#endif
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+#define VALGRIND_ALIGN_STACK \
+ "movq %%rsp,%%r14\n\t" \
+ "andq $0xfffffffffffffff0,%%rsp\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "movq %%r14,%%rsp\n\t"
/* These CALL_FN_ macros assume that on amd64-linux, sizeof(unsigned
long) == 8. */
@@ -1262,432 +1376,439 @@
with the stack pointer doesn't give a danger of non-unwindable
stack. */
-#define CALL_FN_W_v(lval, orig) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[1]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_W(lval, orig, arg1) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[2]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[3]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[4]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[5]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "movq 32(%%rax), %%rcx\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[6]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "movq 40(%%rax), %%r8\n\t" \
- "movq 32(%%rax), %%rcx\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[7]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "movq 48(%%rax), %%r9\n\t" \
- "movq 40(%%rax), %%r8\n\t" \
- "movq 32(%%rax), %%rcx\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[8]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $136,%%rsp\n\t" \
- "pushq 56(%%rax)\n\t" \
- "movq 48(%%rax), %%r9\n\t" \
- "movq 40(%%rax), %%r8\n\t" \
- "movq 32(%%rax), %%rcx\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $8, %%rsp\n" \
- "addq $136,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $136,%%rsp\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7,arg8) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[9]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "pushq 64(%%rax)\n\t" \
- "pushq 56(%%rax)\n\t" \
- "movq 48(%%rax), %%r9\n\t" \
- "movq 40(%%rax), %%r8\n\t" \
- "movq 32(%%rax), %%rcx\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $16, %%rsp\n" \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7,arg8,arg9) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[10]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- _argvec[9] = (unsigned long)(arg9); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $136,%%rsp\n\t" \
- "pushq 72(%%rax)\n\t" \
- "pushq 64(%%rax)\n\t" \
- "pushq 56(%%rax)\n\t" \
- "movq 48(%%rax), %%r9\n\t" \
- "movq 40(%%rax), %%r8\n\t" \
- "movq 32(%%rax), %%rcx\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $24, %%rsp\n" \
- "addq $136,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $136,%%rsp\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7,arg8,arg9,arg10) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[11]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- _argvec[9] = (unsigned long)(arg9); \
- _argvec[10] = (unsigned long)(arg10); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "pushq 80(%%rax)\n\t" \
- "pushq 72(%%rax)\n\t" \
- "pushq 64(%%rax)\n\t" \
- "pushq 56(%%rax)\n\t" \
- "movq 48(%%rax), %%r9\n\t" \
- "movq 40(%%rax), %%r8\n\t" \
- "movq 32(%%rax), %%rcx\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $32, %%rsp\n" \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "pushq 80(%%rax)\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7,arg8,arg9,arg10,arg11) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[12]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- _argvec[9] = (unsigned long)(arg9); \
- _argvec[10] = (unsigned long)(arg10); \
- _argvec[11] = (unsigned long)(arg11); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $136,%%rsp\n\t" \
- "pushq 88(%%rax)\n\t" \
- "pushq 80(%%rax)\n\t" \
- "pushq 72(%%rax)\n\t" \
- "pushq 64(%%rax)\n\t" \
- "pushq 56(%%rax)\n\t" \
- "movq 48(%%rax), %%r9\n\t" \
- "movq 40(%%rax), %%r8\n\t" \
- "movq 32(%%rax), %%rcx\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $40, %%rsp\n" \
- "addq $136,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $136,%%rsp\n\t" \
+ "pushq 88(%%rax)\n\t" \
+ "pushq 80(%%rax)\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
-#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
- arg7,arg8,arg9,arg10,arg11,arg12) \
- do { \
- volatile OrigFn _orig = (orig); \
- volatile unsigned long _argvec[13]; \
- volatile unsigned long _res; \
- _argvec[0] = (unsigned long)_orig.nraddr; \
- _argvec[1] = (unsigned long)(arg1); \
- _argvec[2] = (unsigned long)(arg2); \
- _argvec[3] = (unsigned long)(arg3); \
- _argvec[4] = (unsigned long)(arg4); \
- _argvec[5] = (unsigned long)(arg5); \
- _argvec[6] = (unsigned long)(arg6); \
- _argvec[7] = (unsigned long)(arg7); \
- _argvec[8] = (unsigned long)(arg8); \
- _argvec[9] = (unsigned long)(arg9); \
- _argvec[10] = (unsigned long)(arg10); \
- _argvec[11] = (unsigned long)(arg11); \
- _argvec[12] = (unsigned long)(arg12); \
- __asm__ volatile( \
- VALGRIND_CFI_PROLOGUE \
- "subq $128,%%rsp\n\t" \
- "pushq 96(%%rax)\n\t" \
- "pushq 88(%%rax)\n\t" \
- "pushq 80(%%rax)\n\t" \
- "pushq 72(%%rax)\n\t" \
- "pushq 64(%%rax)\n\t" \
- "pushq 56(%%rax)\n\t" \
- "movq 48(%%rax), %%r9\n\t" \
- "movq 40(%%rax), %%r8\n\t" \
- "movq 32(%%rax), %%rcx\n\t" \
- "movq 24(%%rax), %%rdx\n\t" \
- "movq 16(%%rax), %%rsi\n\t" \
- "movq 8(%%rax), %%rdi\n\t" \
- "movq (%%rax), %%rax\n\t" /* target->%rax */ \
- VALGRIND_CALL_NOREDIR_RAX \
- "addq $48, %%rsp\n" \
- "addq $128,%%rsp\n\t" \
- VALGRIND_CFI_EPILOGUE \
- : /*out*/ "=a" (_res) \
- : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15" \
- ); \
- lval = (__typeof__(lval)) _res; \
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10,arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ VALGRIND_CFI_PROLOGUE \
+ VALGRIND_ALIGN_STACK \
+ "subq $128,%%rsp\n\t" \
+ "pushq 96(%%rax)\n\t" \
+ "pushq 88(%%rax)\n\t" \
+ "pushq 80(%%rax)\n\t" \
+ "pushq 72(%%rax)\n\t" \
+ "pushq 64(%%rax)\n\t" \
+ "pushq 56(%%rax)\n\t" \
+ "movq 48(%%rax), %%r9\n\t" \
+ "movq 40(%%rax), %%r8\n\t" \
+ "movq 32(%%rax), %%rcx\n\t" \
+ "movq 24(%%rax), %%rdx\n\t" \
+ "movq 16(%%rax), %%rsi\n\t" \
+ "movq 8(%%rax), %%rdi\n\t" \
+ "movq (%%rax), %%rax\n\t" /* target->%rax */ \
+ VALGRIND_CALL_NOREDIR_RAX \
+ VALGRIND_RESTORE_STACK \
+ VALGRIND_CFI_EPILOGUE \
+ : /*out*/ "=a" (_res) \
+ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r14", "r15" \
+ ); \
+ lval = (__typeof__(lval)) _res; \
} while (0)
#endif /* PLAT_amd64_linux || PLAT_amd64_darwin */
@@ -1726,6 +1847,17 @@
"r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
"r11", "r12", "r13"
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+#define VALGRIND_ALIGN_STACK \
+ "mr 28,1\n\t" \
+ "rlwinm 1,1,0,0,27\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "mr 1,28\n\t"
+
/* These CALL_FN_ macros assume that on ppc32-linux,
sizeof(unsigned long) == 4. */
@@ -1736,13 +1868,15 @@
volatile unsigned long _res; \
_argvec[0] = (unsigned long)_orig.nraddr; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1755,14 +1889,16 @@
_argvec[0] = (unsigned long)_orig.nraddr; \
_argvec[1] = (unsigned long)arg1; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"lwz 3,4(11)\n\t" /* arg1->r3 */ \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1776,15 +1912,17 @@
_argvec[1] = (unsigned long)arg1; \
_argvec[2] = (unsigned long)arg2; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"lwz 3,4(11)\n\t" /* arg1->r3 */ \
"lwz 4,8(11)\n\t" \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1799,16 +1937,18 @@
_argvec[2] = (unsigned long)arg2; \
_argvec[3] = (unsigned long)arg3; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"lwz 3,4(11)\n\t" /* arg1->r3 */ \
"lwz 4,8(11)\n\t" \
"lwz 5,12(11)\n\t" \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1824,6 +1964,7 @@
_argvec[3] = (unsigned long)arg3; \
_argvec[4] = (unsigned long)arg4; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"lwz 3,4(11)\n\t" /* arg1->r3 */ \
"lwz 4,8(11)\n\t" \
@@ -1831,10 +1972,11 @@
"lwz 6,16(11)\n\t" /* arg4->r6 */ \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1851,6 +1993,7 @@
_argvec[4] = (unsigned long)arg4; \
_argvec[5] = (unsigned long)arg5; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"lwz 3,4(11)\n\t" /* arg1->r3 */ \
"lwz 4,8(11)\n\t" \
@@ -1859,10 +2002,11 @@
"lwz 7,20(11)\n\t" \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1880,6 +2024,7 @@
_argvec[5] = (unsigned long)arg5; \
_argvec[6] = (unsigned long)arg6; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"lwz 3,4(11)\n\t" /* arg1->r3 */ \
"lwz 4,8(11)\n\t" \
@@ -1889,10 +2034,11 @@
"lwz 8,24(11)\n\t" \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1912,6 +2058,7 @@
_argvec[6] = (unsigned long)arg6; \
_argvec[7] = (unsigned long)arg7; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"lwz 3,4(11)\n\t" /* arg1->r3 */ \
"lwz 4,8(11)\n\t" \
@@ -1922,10 +2069,11 @@
"lwz 9,28(11)\n\t" \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1946,6 +2094,7 @@
_argvec[7] = (unsigned long)arg7; \
_argvec[8] = (unsigned long)arg8; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"lwz 3,4(11)\n\t" /* arg1->r3 */ \
"lwz 4,8(11)\n\t" \
@@ -1957,10 +2106,11 @@
"lwz 10,32(11)\n\t" /* arg8->r10 */ \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -1982,6 +2132,7 @@
_argvec[8] = (unsigned long)arg8; \
_argvec[9] = (unsigned long)arg9; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"addi 1,1,-16\n\t" \
/* arg9 */ \
@@ -1998,11 +2149,11 @@
"lwz 10,32(11)\n\t" /* arg8->r10 */ \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
- "addi 1,1,16\n\t" \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2025,6 +2176,7 @@
_argvec[9] = (unsigned long)arg9; \
_argvec[10] = (unsigned long)arg10; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"addi 1,1,-16\n\t" \
/* arg10 */ \
@@ -2044,11 +2196,11 @@
"lwz 10,32(11)\n\t" /* arg8->r10 */ \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
- "addi 1,1,16\n\t" \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2072,6 +2224,7 @@
_argvec[10] = (unsigned long)arg10; \
_argvec[11] = (unsigned long)arg11; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"addi 1,1,-32\n\t" \
/* arg11 */ \
@@ -2094,11 +2247,11 @@
"lwz 10,32(11)\n\t" /* arg8->r10 */ \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
- "addi 1,1,32\n\t" \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2123,6 +2276,7 @@
_argvec[11] = (unsigned long)arg11; \
_argvec[12] = (unsigned long)arg12; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"addi 1,1,-32\n\t" \
/* arg12 */ \
@@ -2148,11 +2302,11 @@
"lwz 10,32(11)\n\t" /* arg8->r10 */ \
"lwz 11,0(11)\n\t" /* target->r11 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
- "addi 1,1,32\n\t" \
+ VALGRIND_RESTORE_STACK \
"mr %0,3" \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2172,6 +2326,17 @@
"r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
"r11", "r12", "r13"
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+#define VALGRIND_ALIGN_STACK \
+ "mr 28,1\n\t" \
+ "rldicr 1,1,0,59\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "mr 1,28\n\t"
+
/* These CALL_FN_ macros assume that on ppc64-linux, sizeof(unsigned
long) == 8. */
@@ -2184,6 +2349,7 @@
_argvec[1] = (unsigned long)_orig.r2; \
_argvec[2] = (unsigned long)_orig.nraddr; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2191,10 +2357,11 @@
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
- "ld 2,-16(11)" /* restore tocptr */ \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2209,6 +2376,7 @@
_argvec[2] = (unsigned long)_orig.nraddr; \
_argvec[2+1] = (unsigned long)arg1; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2217,10 +2385,11 @@
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
- "ld 2,-16(11)" /* restore tocptr */ \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2236,6 +2405,7 @@
_argvec[2+1] = (unsigned long)arg1; \
_argvec[2+2] = (unsigned long)arg2; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2245,10 +2415,11 @@
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
- "ld 2,-16(11)" /* restore tocptr */ \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2265,6 +2436,7 @@
_argvec[2+2] = (unsigned long)arg2; \
_argvec[2+3] = (unsigned long)arg3; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2275,10 +2447,11 @@
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
- "ld 2,-16(11)" /* restore tocptr */ \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2296,6 +2469,7 @@
_argvec[2+3] = (unsigned long)arg3; \
_argvec[2+4] = (unsigned long)arg4; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2307,10 +2481,11 @@
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
- "ld 2,-16(11)" /* restore tocptr */ \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2329,6 +2504,7 @@
_argvec[2+4] = (unsigned long)arg4; \
_argvec[2+5] = (unsigned long)arg5; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2341,10 +2517,11 @@
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
- "ld 2,-16(11)" /* restore tocptr */ \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2364,6 +2541,7 @@
_argvec[2+5] = (unsigned long)arg5; \
_argvec[2+6] = (unsigned long)arg6; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2377,10 +2555,11 @@
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
- "ld 2,-16(11)" /* restore tocptr */ \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2402,6 +2581,7 @@
_argvec[2+6] = (unsigned long)arg6; \
_argvec[2+7] = (unsigned long)arg7; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2416,10 +2596,11 @@
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
- "ld 2,-16(11)" /* restore tocptr */ \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2442,6 +2623,7 @@
_argvec[2+7] = (unsigned long)arg7; \
_argvec[2+8] = (unsigned long)arg8; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2457,10 +2639,11 @@
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11 \
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
- "ld 2,-16(11)" /* restore tocptr */ \
+ "ld 2,-16(11)\n\t" /* restore tocptr */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2484,6 +2667,7 @@
_argvec[2+8] = (unsigned long)arg8; \
_argvec[2+9] = (unsigned long)arg9; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2505,10 +2689,10 @@
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
"ld 2,-16(11)\n\t" /* restore tocptr */ \
- "addi 1,1,128" /* restore frame */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2533,6 +2717,7 @@
_argvec[2+9] = (unsigned long)arg9; \
_argvec[2+10] = (unsigned long)arg10; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2557,10 +2742,10 @@
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
"ld 2,-16(11)\n\t" /* restore tocptr */ \
- "addi 1,1,128" /* restore frame */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2586,6 +2771,7 @@
_argvec[2+10] = (unsigned long)arg10; \
_argvec[2+11] = (unsigned long)arg11; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2613,10 +2799,10 @@
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
"ld 2,-16(11)\n\t" /* restore tocptr */ \
- "addi 1,1,144" /* restore frame */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2643,6 +2829,7 @@
_argvec[2+11] = (unsigned long)arg11; \
_argvec[2+12] = (unsigned long)arg12; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"mr 11,%1\n\t" \
"std 2,-16(11)\n\t" /* save tocptr */ \
"ld 2,-8(11)\n\t" /* use nraddr's tocptr */ \
@@ -2673,10 +2860,10 @@
"mr 11,%1\n\t" \
"mr %0,3\n\t" \
"ld 2,-16(11)\n\t" /* restore tocptr */ \
- "addi 1,1,144" /* restore frame */ \
+ VALGRIND_RESTORE_STACK \
: /*out*/ "=r" (_res) \
: /*in*/ "r" (&_argvec[2]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2690,6 +2877,27 @@
/* These regs are trashed by the hidden call. */
#define __CALLER_SAVED_REGS "r0", "r1", "r2", "r3","r4","r14"
+/* Macros to save and align the stack before making a function
+ call and restore it afterwards as gcc may not keep the stack
+ pointer aligned if it doesn't realise calls are being made
+ to other functions. */
+
+/* This is a bit tricky. We store the original stack pointer in r10
+ as it is callee-saves. gcc doesn't allow the use of r11 for some
+ reason. Also, we can't directly "bic" the stack pointer in thumb
+ mode since r13 isn't an allowed register number in that context.
+ So use r4 as a temporary, since that is about to get trashed
+ anyway, just after each use of this macro. Side effect is we need
+ to be very careful about any future changes, since
+ VALGRIND_ALIGN_STACK simply assumes r4 is usable. */
+#define VALGRIND_ALIGN_STACK \
+ "mov r10, sp\n\t" \
+ "mov r4, sp\n\t" \
+ "bic r4, r4, #7\n\t" \
+ "mov sp, r4\n\t"
+#define VALGRIND_RESTORE_STACK \
+ "mov sp, r10\n\t"
+
/* These CALL_FN_ macros assume that on arm-linux, sizeof(unsigned
long) == 4. */
@@ -2700,12 +2908,14 @@
volatile unsigned long _res; \
_argvec[0] = (unsigned long)_orig.nraddr; \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0\n" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2718,13 +2928,15 @@
_argvec[0] = (unsigned long)_orig.nraddr; \
_argvec[1] = (unsigned long)(arg1); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"ldr r0, [%1, #4] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0\n" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2738,14 +2950,16 @@
_argvec[1] = (unsigned long)(arg1); \
_argvec[2] = (unsigned long)(arg2); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"ldr r0, [%1, #4] \n\t" \
"ldr r1, [%1, #8] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0\n" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2760,15 +2974,17 @@
_argvec[2] = (unsigned long)(arg2); \
_argvec[3] = (unsigned long)(arg3); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"ldr r0, [%1, #4] \n\t" \
"ldr r1, [%1, #8] \n\t" \
"ldr r2, [%1, #12] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0\n" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2784,16 +3000,18 @@
_argvec[3] = (unsigned long)(arg3); \
_argvec[4] = (unsigned long)(arg4); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"ldr r0, [%1, #4] \n\t" \
"ldr r1, [%1, #8] \n\t" \
"ldr r2, [%1, #12] \n\t" \
"ldr r3, [%1, #16] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2810,6 +3028,8 @@
_argvec[4] = (unsigned long)(arg4); \
_argvec[5] = (unsigned long)(arg5); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #4 \n\t" \
"ldr r0, [%1, #20] \n\t" \
"push {r0} \n\t" \
"ldr r0, [%1, #4] \n\t" \
@@ -2818,11 +3038,11 @@
"ldr r3, [%1, #16] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
- "add sp, sp, #4 \n\t" \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2840,6 +3060,7 @@
_argvec[5] = (unsigned long)(arg5); \
_argvec[6] = (unsigned long)(arg6); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"ldr r0, [%1, #20] \n\t" \
"ldr r1, [%1, #24] \n\t" \
"push {r0, r1} \n\t" \
@@ -2849,11 +3070,11 @@
"ldr r3, [%1, #16] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
- "add sp, sp, #8 \n\t" \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2873,6 +3094,8 @@
_argvec[6] = (unsigned long)(arg6); \
_argvec[7] = (unsigned long)(arg7); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #4 \n\t" \
"ldr r0, [%1, #20] \n\t" \
"ldr r1, [%1, #24] \n\t" \
"ldr r2, [%1, #28] \n\t" \
@@ -2883,11 +3106,11 @@
"ldr r3, [%1, #16] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
- "add sp, sp, #12 \n\t" \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2908,6 +3131,7 @@
_argvec[7] = (unsigned long)(arg7); \
_argvec[8] = (unsigned long)(arg8); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"ldr r0, [%1, #20] \n\t" \
"ldr r1, [%1, #24] \n\t" \
"ldr r2, [%1, #28] \n\t" \
@@ -2919,11 +3143,11 @@
"ldr r3, [%1, #16] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
- "add sp, sp, #16 \n\t" \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2945,6 +3169,8 @@
_argvec[8] = (unsigned long)(arg8); \
_argvec[9] = (unsigned long)(arg9); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #4 \n\t" \
"ldr r0, [%1, #20] \n\t" \
"ldr r1, [%1, #24] \n\t" \
"ldr r2, [%1, #28] \n\t" \
@@ -2957,11 +3183,11 @@
"ldr r3, [%1, #16] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
- "add sp, sp, #20 \n\t" \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -2984,6 +3210,7 @@
_argvec[9] = (unsigned long)(arg9); \
_argvec[10] = (unsigned long)(arg10); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"ldr r0, [%1, #40] \n\t" \
"push {r0} \n\t" \
"ldr r0, [%1, #20] \n\t" \
@@ -2998,11 +3225,11 @@
"ldr r3, [%1, #16] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
- "add sp, sp, #24 \n\t" \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -3027,6 +3254,8 @@
_argvec[10] = (unsigned long)(arg10); \
_argvec[11] = (unsigned long)(arg11); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
+ "sub sp, sp, #4 \n\t" \
"ldr r0, [%1, #40] \n\t" \
"ldr r1, [%1, #44] \n\t" \
"push {r0, r1} \n\t" \
@@ -3042,11 +3271,11 @@
"ldr r3, [%1, #16] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
- "add sp, sp, #28 \n\t" \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory",__CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -3072,6 +3301,7 @@
_argvec[11] = (unsigned long)(arg11); \
_argvec[12] = (unsigned long)(arg12); \
__asm__ volatile( \
+ VALGRIND_ALIGN_STACK \
"ldr r0, [%1, #40] \n\t" \
"ldr r1, [%1, #44] \n\t" \
"ldr r2, [%1, #48] \n\t" \
@@ -3088,11 +3318,11 @@
"ldr r3, [%1, #16] \n\t" \
"ldr r4, [%1] \n\t" /* target->r4 */ \
VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4 \
- "add sp, sp, #32 \n\t" \
+ VALGRIND_RESTORE_STACK \
"mov %0, r0" \
: /*out*/ "=r" (_res) \
: /*in*/ "0" (&_argvec[0]) \
- : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \
); \
lval = (__typeof__(lval)) _res; \
} while (0)
@@ -3126,8 +3356,10 @@
# define VALGRIND_CFI_EPILOGUE
#endif
-
-
+/* Nb: On s390 the stack pointer is properly aligned *at all times*
+ according to the s390 GCC maintainer. (The ABI specification is not
+ precise in this regard.) Therefore, VALGRIND_ALIGN_STACK and
+ VALGRIND_RESTORE_STACK are not defined here. */
/* These regs are trashed by the hidden call. Note that we overwrite
r14 in s390_irgen_noredir (VEX/priv/guest_s390_irgen.c) to give the
@@ -3136,6 +3368,14 @@
#define __CALLER_SAVED_REGS "0","1","2","3","4","5","14", \
"f0","f1","f2","f3","f4","f5","f6","f7"
+/* Nb: Although r11 is modified in the asm snippets below (inside
+ VALGRIND_CFI_PROLOGUE) it is not listed in the clobber section, for
+ two reasons:
+ (1) r11 is restored in VALGRIND_CFI_EPILOGUE, so effectively it is not
+ modified
+ (2) GCC will complain that r11 cannot appear inside a clobber section,
+ when compiled with -O -fno-omit-frame-pointer
+ */
#define CALL_FN_W_v(lval, orig) \
do { \
@@ -3577,6 +3817,545 @@
#endif /* PLAT_s390x_linux */
+/* ------------------------- mips-linux ------------------------- */
+
+#if defined(PLAT_mips32_linux)
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS "$2", "$3", "$4", "$5", "$6", \
+"$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+"$25", "$31"
+
+/* These CALL_FN_ macros assume that on mips-linux, sizeof(unsigned
+ long) == 4. */
+
+#define CALL_FN_W_v(lval, orig) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[1]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16\n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[2]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $a0, 4(%1) \n\t" /* arg1*/ \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[3]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[4]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[5]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "subu $29, $29, 16 \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $a3, 16(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 16 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $29, $29, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[6]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "lw $a0, 20(%1) \n\t" \
+ "subu $sp, $sp, 24\n\t" \
+ "sw $a0, 16($sp) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $a3, 16(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $29, $29, 24 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $sp, $sp, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[7]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "lw $a0, 20(%1) \n\t" \
+ "subu $sp, $sp, 32\n\t" \
+ "sw $a0, 16($sp) \n\t" \
+ "lw $a0, 24(%1) \n\t" \
+ "nop\n\t" \
+ "sw $a0, 20($sp) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $a3, 16(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $sp, $sp, 32 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $sp, $sp, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[8]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "lw $a0, 20(%1) \n\t" \
+ "subu $sp, $sp, 32\n\t" \
+ "sw $a0, 16($sp) \n\t" \
+ "lw $a0, 24(%1) \n\t" \
+ "sw $a0, 20($sp) \n\t" \
+ "lw $a0, 28(%1) \n\t" \
+ "sw $a0, 24($sp) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $a3, 16(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $sp, $sp, 32 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $sp, $sp, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[9]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "lw $a0, 20(%1) \n\t" \
+ "subu $sp, $sp, 40\n\t" \
+ "sw $a0, 16($sp) \n\t" \
+ "lw $a0, 24(%1) \n\t" \
+ "sw $a0, 20($sp) \n\t" \
+ "lw $a0, 28(%1) \n\t" \
+ "sw $a0, 24($sp) \n\t" \
+ "lw $a0, 32(%1) \n\t" \
+ "sw $a0, 28($sp) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $a3, 16(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $sp, $sp, 40 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $sp, $sp, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[10]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "lw $a0, 20(%1) \n\t" \
+ "subu $sp, $sp, 40\n\t" \
+ "sw $a0, 16($sp) \n\t" \
+ "lw $a0, 24(%1) \n\t" \
+ "sw $a0, 20($sp) \n\t" \
+ "lw $a0, 28(%1) \n\t" \
+ "sw $a0, 24($sp) \n\t" \
+ "lw $a0, 32(%1) \n\t" \
+ "sw $a0, 28($sp) \n\t" \
+ "lw $a0, 36(%1) \n\t" \
+ "sw $a0, 32($sp) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $a3, 16(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $sp, $sp, 40 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $sp, $sp, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
+ arg7,arg8,arg9,arg10) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[11]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "lw $a0, 20(%1) \n\t" \
+ "subu $sp, $sp, 48\n\t" \
+ "sw $a0, 16($sp) \n\t" \
+ "lw $a0, 24(%1) \n\t" \
+ "sw $a0, 20($sp) \n\t" \
+ "lw $a0, 28(%1) \n\t" \
+ "sw $a0, 24($sp) \n\t" \
+ "lw $a0, 32(%1) \n\t" \
+ "sw $a0, 28($sp) \n\t" \
+ "lw $a0, 36(%1) \n\t" \
+ "sw $a0, 32($sp) \n\t" \
+ "lw $a0, 40(%1) \n\t" \
+ "sw $a0, 36($sp) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $a3, 16(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $sp, $sp, 48 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $sp, $sp, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[12]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "lw $a0, 20(%1) \n\t" \
+ "subu $sp, $sp, 48\n\t" \
+ "sw $a0, 16($sp) \n\t" \
+ "lw $a0, 24(%1) \n\t" \
+ "sw $a0, 20($sp) \n\t" \
+ "lw $a0, 28(%1) \n\t" \
+ "sw $a0, 24($sp) \n\t" \
+ "lw $a0, 32(%1) \n\t" \
+ "sw $a0, 28($sp) \n\t" \
+ "lw $a0, 36(%1) \n\t" \
+ "sw $a0, 32($sp) \n\t" \
+ "lw $a0, 40(%1) \n\t" \
+ "sw $a0, 36($sp) \n\t" \
+ "lw $a0, 44(%1) \n\t" \
+ "sw $a0, 40($sp) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $a3, 16(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $sp, $sp, 48 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $sp, $sp, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \
+ arg6,arg7,arg8,arg9,arg10, \
+ arg11,arg12) \
+ do { \
+ volatile OrigFn _orig = (orig); \
+ volatile unsigned long _argvec[13]; \
+ volatile unsigned long _res; \
+ _argvec[0] = (unsigned long)_orig.nraddr; \
+ _argvec[1] = (unsigned long)(arg1); \
+ _argvec[2] = (unsigned long)(arg2); \
+ _argvec[3] = (unsigned long)(arg3); \
+ _argvec[4] = (unsigned long)(arg4); \
+ _argvec[5] = (unsigned long)(arg5); \
+ _argvec[6] = (unsigned long)(arg6); \
+ _argvec[7] = (unsigned long)(arg7); \
+ _argvec[8] = (unsigned long)(arg8); \
+ _argvec[9] = (unsigned long)(arg9); \
+ _argvec[10] = (unsigned long)(arg10); \
+ _argvec[11] = (unsigned long)(arg11); \
+ _argvec[12] = (unsigned long)(arg12); \
+ __asm__ volatile( \
+ "subu $29, $29, 8 \n\t" \
+ "sw $gp, 0($sp) \n\t" \
+ "sw $ra, 4($sp) \n\t" \
+ "lw $a0, 20(%1) \n\t" \
+ "subu $sp, $sp, 56\n\t" \
+ "sw $a0, 16($sp) \n\t" \
+ "lw $a0, 24(%1) \n\t" \
+ "sw $a0, 20($sp) \n\t" \
+ "lw $a0, 28(%1) \n\t" \
+ "sw $a0, 24($sp) \n\t" \
+ "lw $a0, 32(%1) \n\t" \
+ "sw $a0, 28($sp) \n\t" \
+ "lw $a0, 36(%1) \n\t" \
+ "sw $a0, 32($sp) \n\t" \
+ "lw $a0, 40(%1) \n\t" \
+ "sw $a0, 36($sp) \n\t" \
+ "lw $a0, 44(%1) \n\t" \
+ "sw $a0, 40($sp) \n\t" \
+ "lw $a0, 48(%1) \n\t" \
+ "sw $a0, 44($sp) \n\t" \
+ "lw $a0, 4(%1) \n\t" \
+ "lw $a1, 8(%1) \n\t" \
+ "lw $a2, 12(%1) \n\t" \
+ "lw $a3, 16(%1) \n\t" \
+ "lw $t9, 0(%1) \n\t" /* target->t9 */ \
+ VALGRIND_CALL_NOREDIR_T9 \
+ "addu $sp, $sp, 56 \n\t" \
+ "lw $gp, 0($sp) \n\t" \
+ "lw $ra, 4($sp) \n\t" \
+ "addu $sp, $sp, 8 \n\t" \
+ "move %0, $v0\n" \
+ : /*out*/ "=r" (_res) \
+ : /*in*/ "0" (&_argvec[0]) \
+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS \
+ ); \
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+#endif /* PLAT_mips32_linux */
+
/* ------------------------------------------------------------------ */
/* ARCHITECTURE INDEPENDENT MACROS for CLIENT REQUESTS. */
@@ -3701,7 +4480,7 @@
is the number of characters printed, excluding the "**<pid>** " part at the
start and the backtrace (if present). */
-#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+#if defined(__GNUC__) || defined(__INTEL_COMPILER) && !defined(_MSC_VER)
/* Modern GCC will optimize the static routine out if unused,
and unused attribute will shut down warnings about it. */
static int VALGRIND_PRINTF(const char *format, ...)
@@ -3741,7 +4520,7 @@
#endif /* NVALGRIND */
}
-#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+#if defined(__GNUC__) || defined(__INTEL_COMPILER) && !defined(_MSC_VER)
static int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
__attribute__((format(__printf__, 1, 2), __unused__));
#endif
@@ -4056,5 +4835,6 @@
#undef PLAT_ppc64_linux
#undef PLAT_arm_linux
#undef PLAT_s390x_linux
+#undef PLAT_mips32_linux
#endif /* __VALGRIND_H */
diff --git a/main/include/vki/vki-amd64-linux.h b/main/include/vki/vki-amd64-linux.h
index 8c0bcba..479f0de 100644
--- a/main/include/vki/vki-amd64-linux.h
+++ b/main/include/vki/vki-amd64-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -268,6 +268,18 @@
#define VKI_F_SETSIG 10 /* for sockets. */
#define VKI_F_GETSIG 11 /* for sockets. */
+#define VKI_F_SETOWN_EX 15
+#define VKI_F_GETOWN_EX 16
+
+#define VKI_F_OWNER_TID 0
+#define VKI_F_OWNER_PID 1
+#define VKI_F_OWNER_PGRP 2
+
+struct vki_f_owner_ex {
+ int type;
+ __vki_kernel_pid_t pid;
+};
+
#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */
#define VKI_F_LINUX_SPECIFIC_BASE 1024
@@ -546,11 +558,13 @@
// type for x86 (the final 'lm' field is added); I'm not sure about the
// significance of that... --njn
-#if 0
/* [[Nb: This is the structure passed to the modify_ldt syscall. Just so as
to confuse and annoy everyone, this is _not_ the same as an
VgLdtEntry and has to be translated into such. The logic for doing
so, in vg_ldt.c, is copied from the kernel sources.]] */
+/* Note also that a comment in ldt.h indicates that the below
+ contains several fields ignored on 64bit, and that modify_ldt
+ is rather for 32bit. */
struct vki_user_desc {
unsigned int entry_number;
unsigned long base_addr;
@@ -566,9 +580,6 @@
// [[Nb: for our convenience within Valgrind, use a more specific name]]
typedef struct vki_user_desc vki_modify_ldt_t;
-#endif
-
-typedef void vki_modify_ldt_t;
//----------------------------------------------------------------------
// From linux-2.6.11.2/include/asm-x86_64/ipcbuf.h
diff --git a/main/include/vki/vki-arm-linux.h b/main/include/vki/vki-arm-linux.h
index a77e2eb..ab094b3 100644
--- a/main/include/vki/vki-arm-linux.h
+++ b/main/include/vki/vki-arm-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -270,6 +270,18 @@
#define VKI_F_SETLK64 13
#define VKI_F_SETLKW64 14
+#define VKI_F_SETOWN_EX 15
+#define VKI_F_GETOWN_EX 16
+
+#define VKI_F_OWNER_TID 0
+#define VKI_F_OWNER_PID 1
+#define VKI_F_OWNER_PGRP 2
+
+struct vki_f_owner_ex {
+ int type;
+ __vki_kernel_pid_t pid;
+};
+
/* for F_[GET|SET]FL */
#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */
@@ -598,7 +610,7 @@
vki_stack_t uc_stack;
struct vki_sigcontext uc_mcontext;
vki_sigset_t uc_sigmask; /* mask last for extensibility */
- int __unused1[32 - (sizeof (vki_sigset_t) / sizeof (int))];
+ int __unused[32 - (sizeof (vki_sigset_t) / sizeof (int))];
unsigned long uc_regspace[128] __attribute__((__aligned__(8)));
};
diff --git a/main/include/vki/vki-darwin.h b/main/include/vki/vki-darwin.h
index dfc883d..d87a72a 100644
--- a/main/include/vki/vki-darwin.h
+++ b/main/include/vki/vki-darwin.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2011 Apple Inc.
+ Copyright (C) 2007-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
@@ -829,9 +829,12 @@
// Libc/pthreads/pthread.c
-#define VKI_WQOPS_QUEUE_ADD 1
-#define VKI_WQOPS_QUEUE_REMOVE 2
-#define VKI_WQOPS_THREAD_RETURN 4
+#define VKI_WQOPS_QUEUE_ADD 1
+#define VKI_WQOPS_QUEUE_REMOVE 2
+#define VKI_WQOPS_THREAD_RETURN 4
+#define VKI_WQOPS_THREAD_SETCONC 8
+#define VKI_WQOPS_QUEUE_NEWSPISUPP 16 /* check for newer SPI support */
+#define VKI_WQOPS_QUEUE_REQTHREADS 32 /* request number of threads of a prio */
#include <sys/ttycom.h>
diff --git a/main/include/vki/vki-linux.h b/main/include/vki/vki-linux.h
index cab1986..c18195e 100644
--- a/main/include/vki/vki-linux.h
+++ b/main/include/vki/vki-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -91,6 +91,8 @@
# include "vki-posixtypes-arm-linux.h"
#elif defined(VGA_s390x)
# include "vki-posixtypes-s390x-linux.h"
+#elif defined(VGA_mips32)
+# include "vki-posixtypes-mips32-linux.h"
#else
# error Unknown platform
#endif
@@ -105,7 +107,14 @@
* 'expr' is false. Can be used in a context where no comma expressions
* are allowed.
*/
-#define VKI_STATIC_ASSERT(expr) (sizeof(int [-!(expr)]))
+#ifdef __cplusplus
+template <bool b> struct vki_static_assert { int m_bitfield:(2*b-1); };
+#define VKI_STATIC_ASSERT(expr) \
+ (sizeof(vki_static_assert<(expr)>) - sizeof(int))
+#else
+#define VKI_STATIC_ASSERT(expr) (sizeof(struct { int:-!(expr); }))
+#endif
+
//----------------------------------------------------------------------
// Based on _IOC_TYPECHECK() from linux-2.6.34/asm-generic/ioctl.h
//----------------------------------------------------------------------
@@ -123,6 +132,14 @@
# define __user
//----------------------------------------------------------------------
+// From linux/include/linux/compiler-gcc.h
+//----------------------------------------------------------------------
+
+#ifdef __GNUC__
+#define __vki_packed __attribute__((packed))
+#endif
+
+//----------------------------------------------------------------------
// From linux-2.6.8.1/include/linux/posix_types.h
//----------------------------------------------------------------------
@@ -196,6 +213,8 @@
# include "vki-arm-linux.h"
#elif defined(VGA_s390x)
# include "vki-s390x-linux.h"
+#elif defined(VGA_mips32)
+# include "vki-mips32-linux.h"
#else
# error Unknown platform
#endif
@@ -211,6 +230,8 @@
typedef __vki_u16 vki_uint16_t;
typedef __vki_u32 vki_uint32_t;
+typedef __vki_u16 __vki_le16;
+
//----------------------------------------------------------------------
// From linux-2.6.8.1/include/linux/limits.h
//----------------------------------------------------------------------
@@ -366,6 +387,8 @@
// From linux-2.6.8.1/include/asm-generic/siginfo.h
//----------------------------------------------------------------------
+// Some archs, such as MIPS, have non-standard vki_siginfo.
+#ifndef HAVE_ARCH_SIGINFO_T
typedef union vki_sigval {
int sival_int;
void __user *sival_ptr;
@@ -445,6 +468,7 @@
} _sigpoll;
} _sifields;
} vki_siginfo_t;
+#endif
#define __VKI_SI_FAULT 0
@@ -598,6 +622,11 @@
unsigned msg_flags;
};
+struct vki_mmsghdr {
+ struct vki_msghdr msg_hdr;
+ unsigned msg_len;
+};
+
struct vki_cmsghdr {
__vki_kernel_size_t cmsg_len; /* data byte count, including hdr */
int cmsg_level; /* originating protocol */
@@ -1151,22 +1180,43 @@
#define VKI_ENOENT 2 /* No such file or directory */
#define VKI_ESRCH 3 /* No such process */
#define VKI_EINTR 4 /* Interrupted system call */
-#define VKI_ENOEXEC 8 /* Exec format error */
+#define VKI_EIO 5 /* I/O error */
+#define VKI_ENXIO 6 /* No such device or address */
+#define VKI_E2BIG 7 /* Argument list too long */
+#define VKI_ENOEXEC 8 /* Exec format error */
#define VKI_EBADF 9 /* Bad file number */
-#define VKI_ECHILD 10 /* No child processes */
-#define VKI_EAGAIN 11 /* Try again */
-#define VKI_EWOULDBLOCK VKI_EAGAIN
+#define VKI_ECHILD 10 /* No child processes */
+#define VKI_EAGAIN 11 /* Try again */
#define VKI_ENOMEM 12 /* Out of memory */
#define VKI_EACCES 13 /* Permission denied */
#define VKI_EFAULT 14 /* Bad address */
+#define VKI_ENOTBLK 15 /* Block device required */
+#define VKI_EBUSY 16 /* Device or resource busy */
#define VKI_EEXIST 17 /* File exists */
+#define VKI_EXDEV 18 /* Cross-device link */
+#define VKI_ENODEV 19 /* No such device */
+#define VKI_ENOTDIR 20 /* Not a directory */
+#define VKI_EISDIR 21 /* Is a directory */
#define VKI_EINVAL 22 /* Invalid argument */
+#define VKI_ENFILE 23 /* File table overflow */
#define VKI_EMFILE 24 /* Too many open files */
+#define VKI_ENOTTY 25 /* Not a typewriter */
+#define VKI_ETXTBSY 26 /* Text file busy */
+#define VKI_EFBIG 27 /* File too large */
+#define VKI_ENOSPC 28 /* No space left on device */
+#define VKI_ESPIPE 29 /* Illegal seek */
+#define VKI_EROFS 30 /* Read-only file system */
+#define VKI_EMLINK 31 /* Too many links */
+#define VKI_EPIPE 32 /* Broken pipe */
+#define VKI_EDOM 33 /* Math argument out of domain of func */
+#define VKI_ERANGE 34 /* Math result not representable */
//----------------------------------------------------------------------
// From linux-2.6.8.1/include/asm-generic/errno.h
//----------------------------------------------------------------------
+#define VKI_EWOULDBLOCK VKI_EAGAIN
+
#define VKI_ENOSYS 38 /* Function not implemented */
#define VKI_EOVERFLOW 75 /* Value too large for defined data type */
@@ -1320,7 +1370,7 @@
vki_size_t __user *oldlenp;
void __user *newval;
vki_size_t newlen;
- unsigned long __unused1[4];
+ unsigned long __unused[4];
};
//----------------------------------------------------------------------
@@ -1572,6 +1622,8 @@
#define VKI_SIOCGIFMAP 0x8970 /* Get device parameters */
#define VKI_SIOCSIFMAP 0x8971 /* Set device parameters */
+#define VKI_SIOCSHWTSTAMP 0x89B0 /* Set hardware time stamping */
+
//----------------------------------------------------------------------
// From linux-2.6.8.1/include/linux/ppdev.h
//----------------------------------------------------------------------
@@ -1723,32 +1775,47 @@
#define VKI_SG_SET_COMMAND_Q 0x2271 /* Change queuing state with 0 or 1 */
//----------------------------------------------------------------------
+// From linux-2.6.34/include/scsi/scsi.h and scsi/scsi_ioctl.h
+//----------------------------------------------------------------------
+
+#define VKI_SCSI_IOCTL_DOORLOCK 0x5380 /* Lock the eject mechanism. */
+#define VKI_SCSI_IOCTL_DOORUNLOCK 0x5381 /* Unlock the mechanism. */
+#define VKI_SCSI_IOCTL_GET_IDLUN 0x5382
+#define VKI_SCSI_IOCTL_GET_BUS_NUMBER 0x5386
+
+struct vki_scsi_idlun {
+ __vki_u32 dev_id;
+ __vki_u32 host_unique_id;
+};
+
+//----------------------------------------------------------------------
// From linux-2.6.8.1/include/linux/cdrom.h
//----------------------------------------------------------------------
-#define VKI_CDROMPLAYMSF 0x5303 /* Play Audio MSF (struct cdrom_msf) */
-#define VKI_CDROMREADTOCHDR 0x5305 /* Read TOC header
- (struct cdrom_tochdr) */
-#define VKI_CDROMREADTOCENTRY 0x5306 /* Read TOC entry
- (struct cdrom_tocentry) */
-#define VKI_CDROMSUBCHNL 0x530b /* Read subchannel data
- (struct cdrom_subchnl) */
-#define VKI_CDROMREADMODE2 0x530c /* Read CDROM mode 2 data (2336 Bytes)
- (struct cdrom_read) */
-#define VKI_CDROMREADAUDIO 0x530e /* (struct cdrom_read_audio) */
-#define VKI_CDROMMULTISESSION 0x5310 /* Obtain the start-of-last-session
- address of multi session disks
- (struct cdrom_multisession) */
-#define VKI_CDROM_GET_MCN 0x5311 /* Obtain the "Universal Product Code"
- if available (struct cdrom_mcn) */
-#define VKI_CDROMVOLREAD 0x5313 /* Get the drive's volume setting
- (struct cdrom_volctrl) */
-#define VKI_CDROMREADRAW 0x5314 /* read data in raw mode (2352 Bytes)
- (struct cdrom_read) */
-#define VKI_CDROM_CLEAR_OPTIONS 0x5321 /* Clear behavior options */
-#define VKI_CDROM_DRIVE_STATUS 0x5326 /* Get tray position, etc. */
+#define VKI_CDROMPLAYMSF 0x5303 /* Play Audio MSF (struct cdrom_msf) */
+#define VKI_CDROMREADTOCHDR 0x5305 /* Read TOC header
+ (struct cdrom_tochdr) */
+#define VKI_CDROMREADTOCENTRY 0x5306 /* Read TOC entry
+ (struct cdrom_tocentry) */
+#define VKI_CDROMSUBCHNL 0x530b /* Read subchannel data
+ (struct cdrom_subchnl) */
+#define VKI_CDROMREADMODE2 0x530c /* Read CDROM mode 2 data (2336 Bytes)
+ (struct cdrom_read) */
+#define VKI_CDROMREADAUDIO 0x530e /* (struct cdrom_read_audio) */
+#define VKI_CDROMMULTISESSION 0x5310 /* Obtain the start-of-last-session
+ address of multi session disks
+ (struct cdrom_multisession) */
+#define VKI_CDROM_GET_MCN 0x5311 /* Obtain the "Universal Product Code"
+ if available (struct cdrom_mcn) */
+#define VKI_CDROMVOLREAD 0x5313 /* Get the drive's volume setting
+ (struct cdrom_volctrl) */
+#define VKI_CDROMREADRAW 0x5314 /* read data in raw mode (2352 Bytes)
+ (struct cdrom_read) */
+#define VKI_CDROM_CLEAR_OPTIONS 0x5321 /* Clear behavior options */
+#define VKI_CDROM_DRIVE_STATUS 0x5326 /* Get tray position, etc. */
+#define VKI_CDROM_GET_CAPABILITY 0x5331 /* get capabilities */
-#define VKI_CDROM_SEND_PACKET 0x5393 /* send a packet to the drive */
+#define VKI_CDROM_SEND_PACKET 0x5393 /* send a packet to the drive */
struct vki_cdrom_msf0
{
@@ -2421,8 +2488,28 @@
/* is already taken! */
#define VKI_I2C_TENBIT 0x0704 /* 0 for 7 bit addrs, != 0 for 10 bit */
#define VKI_I2C_FUNCS 0x0705 /* Get the adapter functionality */
+#define VKI_I2C_RDWR 0x0707 /* Combined R/W transfer (one STOP only) */
#define VKI_I2C_PEC 0x0708 /* != 0 for SMBus PEC */
+struct vki_i2c_msg {
+ __vki_u16 addr; /* slave address */
+ __vki_u16 flags;
+#define VKI_I2C_M_TEN 0x0010 /* this is a ten bit chip address */
+#define VKI_I2C_M_RD 0x0001 /* read data, from slave to master */
+#define VKI_I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define VKI_I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define VKI_I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define VKI_I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define VKI_I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
+ __vki_u16 len; /* msg length */
+ __vki_u8 *buf; /* pointer to msg data */
+};
+
+struct vki_i2c_rdwr_ioctl_data {
+ struct vki_i2c_msg *msgs; /* pointers to i2c_msgs */
+ __vki_u32 nmsgs; /* number of i2c_msgs */
+};
+
//----------------------------------------------------------------------
// From linux-2.6.20.1/include/linux/keyctl.h
//----------------------------------------------------------------------
@@ -2757,7 +2844,7 @@
// From kernel/common/include/linux/ashmem.h
//----------------------------------------------------------------------
-#if defined(VGPV_arm_linux_android)
+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
#define VKI_ASHMEM_NAME_LEN 256
@@ -2812,7 +2899,115 @@
#define VKI_BINDER_THREAD_EXIT _VKI_IOW('b', 8, int)
#define VKI_BINDER_VERSION _VKI_IOWR('b', 9, struct vki_binder_version)
-#endif /* defined(VGPV_arm_linux_android) */
+#endif /* defined(VGPV_*_linux_android) */
+
+//----------------------------------------------------------------------
+// From linux-3.0.4/include/net/bluetooth/bluetooth.h
+//----------------------------------------------------------------------
+
+typedef struct {
+ __vki_u8 b[6];
+} __vki_packed vki_bdaddr_t;
+
+//----------------------------------------------------------------------
+// From linux-3.0.4/include/net/bluetooth/hci.h
+//----------------------------------------------------------------------
+
+#define VKI_HCIDEVUP _VKI_IOW('H', 201, int)
+#define VKI_HCIDEVDOWN _VKI_IOW('H', 202, int)
+#define VKI_HCIDEVRESET _VKI_IOW('H', 203, int)
+#define VKI_HCIDEVRESTAT _VKI_IOW('H', 204, int)
+
+#define VKI_HCIGETDEVLIST _VKI_IOR('H', 210, int)
+#define VKI_HCIGETDEVINFO _VKI_IOR('H', 211, int)
+#define VKI_HCIGETCONNLIST _VKI_IOR('H', 212, int)
+#define VKI_HCIGETCONNINFO _VKI_IOR('H', 213, int)
+#define VKI_HCIGETAUTHINFO _VKI_IOR('H', 215, int)
+
+#define VKI_HCISETRAW _VKI_IOW('H', 220, int)
+#define VKI_HCISETSCAN _VKI_IOW('H', 221, int)
+#define VKI_HCISETAUTH _VKI_IOW('H', 222, int)
+#define VKI_HCISETENCRYPT _VKI_IOW('H', 223, int)
+#define VKI_HCISETPTYPE _VKI_IOW('H', 224, int)
+#define VKI_HCISETLINKPOL _VKI_IOW('H', 225, int)
+#define VKI_HCISETLINKMODE _VKI_IOW('H', 226, int)
+#define VKI_HCISETACLMTU _VKI_IOW('H', 227, int)
+#define VKI_HCISETSCOMTU _VKI_IOW('H', 228, int)
+
+#define VKI_HCIBLOCKADDR _VKI_IOW('H', 230, int)
+#define VKI_HCIUNBLOCKADDR _VKI_IOW('H', 231, int)
+
+#define VKI_HCIINQUIRY _VKI_IOR('H', 240, int)
+
+struct vki_inquiry_info {
+ vki_bdaddr_t bdaddr;
+ __vki_u8 pscan_rep_mode;
+ __vki_u8 pscan_period_mode;
+ __vki_u8 pscan_mode;
+ __vki_u8 dev_class[3];
+ __vki_le16 clock_offset;
+} __vki_packed;
+
+struct vki_hci_inquiry_req {
+ __vki_u16 dev_id;
+ __vki_u16 flags;
+ __vki_u8 lap[3];
+ __vki_u8 length;
+ __vki_u8 num_rsp;
+};
+
+//----------------------------------------------------------------------
+// From linux-3.4/include/linux/kvm.h
+//----------------------------------------------------------------------
+#define KVMIO 0xAE
+
+#define VKI_KVM_GET_API_VERSION _VKI_IO(KVMIO, 0x00)
+#define VKI_KVM_CREATE_VM _VKI_IO(KVMIO, 0x01) /* returns a VM fd */
+#define VKI_KVM_CHECK_EXTENSION _VKI_IO(KVMIO, 0x03)
+#define VKI_KVM_GET_VCPU_MMAP_SIZE _VKI_IO(KVMIO, 0x04) /* in bytes */
+#define VKI_KVM_S390_ENABLE_SIE _VKI_IO(KVMIO, 0x06)
+#define VKI_KVM_CREATE_VCPU _VKI_IO(KVMIO, 0x41)
+#define VKI_KVM_SET_NR_MMU_PAGES _VKI_IO(KVMIO, 0x44)
+#define VKI_KVM_GET_NR_MMU_PAGES _VKI_IO(KVMIO, 0x45)
+#define VKI_KVM_SET_TSS_ADDR _VKI_IO(KVMIO, 0x47)
+#define VKI_KVM_CREATE_IRQCHIP _VKI_IO(KVMIO, 0x60)
+#define VKI_KVM_CREATE_PIT _VKI_IO(KVMIO, 0x64)
+#define VKI_KVM_REINJECT_CONTROL _VKI_IO(KVMIO, 0x71)
+#define VKI_KVM_SET_BOOT_CPU_ID _VKI_IO(KVMIO, 0x78)
+#define VKI_KVM_SET_TSC_KHZ _VKI_IO(KVMIO, 0xa2)
+#define VKI_KVM_GET_TSC_KHZ _VKI_IO(KVMIO, 0xa3)
+#define VKI_KVM_RUN _VKI_IO(KVMIO, 0x80)
+#define VKI_KVM_S390_INITIAL_RESET _VKI_IO(KVMIO, 0x97)
+#define VKI_KVM_NMI _VKI_IO(KVMIO, 0x9a)
+
+//----------------------------------------------------------------------
+// From linux-2.6/include/linux/net_stamp.h
+//----------------------------------------------------------------------
+
+struct vki_hwtstamp_config {
+ int flags;
+ int tx_type;
+ int rx_filter;
+};
+
+//----------------------------------------------------------------------
+// From linux-2.6.12-rc2/include/linux/uinput.h
+//----------------------------------------------------------------------
+
+#define VKI_UINPUT_IOCTL_BASE 'U'
+#define VKI_UI_DEV_CREATE _VKI_IO(VKI_UINPUT_IOCTL_BASE, 1)
+#define VKI_UI_DEV_DESTROY _VKI_IO(VKI_UINPUT_IOCTL_BASE, 2)
+
+#define VKI_UI_SET_EVBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 100, int)
+#define VKI_UI_SET_KEYBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 101, int)
+#define VKI_UI_SET_RELBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 102, int)
+#define VKI_UI_SET_ABSBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 103, int)
+#define VKI_UI_SET_MSCBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 104, int)
+#define VKI_UI_SET_LEDBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 105, int)
+#define VKI_UI_SET_SNDBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 106, int)
+#define VKI_UI_SET_FFBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 107, int)
+#define VKI_UI_SET_SWBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 109, int)
+#define VKI_UI_SET_PROPBIT _VKI_IOW(VKI_UINPUT_IOCTL_BASE, 110, int)
#endif // __VKI_LINUX_H
diff --git a/main/include/vki/vki-mips32-linux.h b/main/include/vki/vki-mips32-linux.h
new file mode 100644
index 0000000..e5a48ff
--- /dev/null
+++ b/main/include/vki/vki-mips32-linux.h
@@ -0,0 +1,971 @@
+
+/*--------------------------------------------------------------------*/
+/*--- mips/Linux-specific kernel interface. vki-mips32-linux.h ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __VKI_MIPS32_LINUX_H
+#define __VKI_MIPS32_LINUX_H
+
+#include <config.h>
+
+// mips endian
+#if defined (_MIPSEL)
+#define VKI_LITTLE_ENDIAN 1
+#elif defined (_MIPSEB)
+#define VKI_BIG_ENDIAN 1
+#endif
+
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-generic/int-ll64.h
+//----------------------------------------------------------------------
+
+typedef __signed__ char __vki_s8;
+typedef unsigned char __vki_u8;
+
+typedef __signed__ short __vki_s16;
+typedef unsigned short __vki_u16;
+
+typedef __signed__ int __vki_s32;
+typedef unsigned int __vki_u32;
+
+typedef __signed char vki_s8;
+typedef unsigned char vki_u8;
+
+typedef __signed short vki_s16;
+typedef unsigned short vki_u16;
+
+typedef __signed int vki_s32;
+typedef unsigned int vki_u32;
+
+typedef __signed__ long long __vki_s64;
+typedef unsigned long long __vki_u64;
+
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/page.h
+//----------------------------------------------------------------------
+
+/* PAGE_SHIFT determines the page size */
+#define VKI_PAGE_SHIFT MIPS_PAGE_SHIFT
+#define VKI_PAGE_SIZE (1UL << VKI_PAGE_SHIFT)
+#define VKI_PAGE_MASK (~(VKI_PAGE_SIZE-1))
+#define VKI_MAX_PAGE_SHIFT VKI_PAGE_SHIFT
+#define VKI_MAX_PAGE_SIZE VKI_PAGE_SIZE
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/arch/mips/include/asm-generic/shmparam.h
+//----------------------------------------------------------------------
+
+#define VKI_SHMLBA SHM_ALIGNMENT
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm/signal.h
+//----------------------------------------------------------------------
+
+#define VKI_MINSIGSTKSZ 2048
+
+#define VKI_SIG_BLOCK 1 /* for blocking signals */
+#define VKI_SIG_UNBLOCK 2 /* for unblocking signals */
+#define VKI_SIG_SETMASK 3 /* for setting the signal mask */
+
+/* Type of a signal handler. */
+typedef void __vki_signalfn_t(int);
+typedef __vki_signalfn_t __user *__vki_sighandler_t;
+
+typedef void __vki_restorefn_t(void);
+typedef __vki_restorefn_t __user *__vki_sigrestore_t;
+
+#define VKI_SIG_DFL ((__vki_sighandler_t)0) /* default signal handling */
+#define VKI_SIG_IGN ((__vki_sighandler_t)1) /* ignore signal */
+
+#define _VKI_NSIG 128
+#define _VKI_NSIG_BPW 32
+#define _VKI_NSIG_WORDS (_VKI_NSIG / _VKI_NSIG_BPW)
+
+typedef unsigned long vki_old_sigset_t; /* at least 32 bits */
+
+typedef struct {
+ unsigned long sig[_VKI_NSIG_WORDS];
+} vki_sigset_t;
+
+#define VKI_SIGHUP 1 /* Hangup (POSIX). */
+#define VKI_SIGINT 2 /* Interrupt (ANSI). */
+#define VKI_SIGQUIT 3 /* Quit (POSIX). */
+#define VKI_SIGILL 4 /* Illegal instruction (ANSI). */
+#define VKI_SIGTRAP 5 /* Trace trap (POSIX). */
+#define VKI_SIGIOT 6 /* IOT trap (4.2 BSD). */
+#define VKI_SIGABRT VKI_SIGIOT /* Abort (ANSI). */
+#define VKI_SIGEMT 7
+#define VKI_SIGFPE 8 /* Floating-point exception (ANSI). */
+#define VKI_SIGKILL 9 /* Kill, unblockable (POSIX). */
+#define VKI_SIGBUS 10 /* BUS error (4.2 BSD). */
+#define VKI_SIGSEGV 11 /* Segmentation violation (ANSI). */
+#define VKI_SIGSYS 12
+#define VKI_SIGPIPE 13 /* Broken pipe (POSIX). */
+#define VKI_SIGALRM 14 /* Alarm clock (POSIX). */
+#define VKI_SIGTERM 15 /* Termination (ANSI). */
+#define VKI_SIGUSR1 16 /* User-defined signal 1 (POSIX). */
+#define VKI_SIGUSR2 17 /* User-defined signal 2 (POSIX). */
+#define VKI_SIGCHLD 18 /* Child status has changed (POSIX). */
+#define VKI_SIGCLD VKI_SIGCHLD /* Same as SIGCHLD (System V). */
+#define VKI_SIGPWR 19 /* Power failure restart (System V). */
+#define VKI_SIGWINCH 20 /* Window size change (4.3 BSD, Sun). */
+#define VKI_SIGURG 21 /* Urgent condition on socket (4.2 BSD). */
+#define VKI_SIGIO 22 /* I/O now possible (4.2 BSD). */
+#define VKI_SIGPOLL VKI_SIGIO /* Pollable event occurred (System V). */
+#define VKI_SIGSTOP 23 /* Stop, unblockable (POSIX). */
+#define VKI_SIGTSTP 24 /* Keyboard stop (POSIX). */
+#define VKI_SIGCONT 25 /* Continue (POSIX). */
+#define VKI_SIGTTIN 26 /* Background read from tty (POSIX). */
+#define VKI_SIGTTOU 27 /* Background write to tty (POSIX). */
+#define VKI_SIGVTALRM 28 /* Virtual alarm clock (4.2 BSD). */
+#define VKI_SIGPROF 29 /* Profiling alarm clock (4.2 BSD). */
+#define VKI_SIGXCPU 30 /* CPU limit exceeded (4.2 BSD). */
+#define VKI_SIGXFSZ 31 /* File size limit exceeded (4.2 BSD). */
+
+/* These should not be considered constants from userland. */
+#define VKI_SIGRTMIN 32
+// [[This was (_NSIG-1) in 2.4.X... not sure if it matters.]]
+#define VKI_SIGRTMAX _VKI_NSIG
+
+#define VKI_SA_ONSTACK 0x08000000
+#define VKI_SA_RESETHAND 0x80000000
+#define VKI_SA_RESTART 0x10000000
+#define VKI_SA_SIGINFO 0x00000008
+#define VKI_SA_NODEFER 0x40000000
+#define VKI_SA_NOCLDWAIT 0x00010000
+#define VKI_SA_NOCLDSTOP 0x00000001
+
+#define VKI_SA_NOMASK VKI_SA_NODEFER
+#define VKI_SA_ONESHOT VKI_SA_RESETHAND
+//#define VKI_SA_INTERRUPT 0x20000000 /* dummy -- ignored */
+
+#define VKI_SA_RESTORER 0x04000000
+
+#define VKI_SS_ONSTACK 1
+#define VKI_SS_DISABLE 2
+
+struct vki_old_sigaction {
+ // [[Nb: a 'k' prefix is added to "sa_handler" because
+ // bits/sigaction.h (which gets dragged in somehow via signal.h)
+ // #defines it as something else. Since that is done for glibc's
+ // purposes, which we don't care about here, we use our own name.]]
+ unsigned long sa_flags;
+ __vki_sighandler_t ksa_handler;
+ vki_old_sigset_t sa_mask;
+ __vki_sigrestore_t sa_restorer;
+};
+
+struct vki_sigaction {
+ unsigned int sa_flags;
+ __vki_sighandler_t sa_handler;
+ vki_sigset_t sa_mask;
+};
+
+
+struct vki_sigaction_base {
+ // [[See comment about extra 'k' above]]
+ unsigned long sa_flags;
+ __vki_sighandler_t ksa_handler;
+
+ vki_sigset_t sa_mask; /* mask last for extensibility */
+ __vki_sigrestore_t sa_restorer;
+};
+
+/* On Linux we use the same type for passing sigactions to
+ and from the kernel. Hence: */
+typedef struct vki_sigaction_base vki_sigaction_toK_t;
+typedef struct vki_sigaction_base vki_sigaction_fromK_t;
+
+typedef struct vki_sigaltstack {
+ void __user *ss_sp;
+ vki_size_t ss_size;
+ int ss_flags;
+
+} vki_stack_t;
+
+
+//----------------------------------------------------------------------
+// From 2.6.35.5/include/asm-mips/sigcontext.h
+//----------------------------------------------------------------------
+
+struct _vki_fpreg {
+ unsigned short significand[4];
+ unsigned short exponent;
+};
+
+struct _vki_fpxreg {
+ unsigned short significand[4];
+ unsigned short exponent;
+ unsigned short padding[3];
+};
+
+struct _vki_xmmreg {
+ unsigned long element[4];
+};
+
+struct _vki_fpstate {
+ /* Regular FPU environment */
+ unsigned long cw;
+ unsigned long sw;
+ unsigned long tag;
+ unsigned long ipoff;
+ unsigned long cssel;
+ unsigned long dataoff;
+ unsigned long datasel;
+ struct _vki_fpreg _st[8];
+ unsigned short status;
+ unsigned short magic; /* 0xffff = regular FPU data only */
+
+ /* FXSR FPU environment */
+ unsigned long _fxsr_env[6]; /* FXSR FPU env is ignored */
+ unsigned long mxcsr;
+ unsigned long reserved;
+ struct _vki_fpxreg _fxsr_st[8]; /* FXSR FPU reg data is ignored */
+ struct _vki_xmmreg _xmm[8];
+ unsigned long padding[56];
+};
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/sigcontext.h
+//----------------------------------------------------------------------
+
+struct vki_sigcontext {
+ unsigned int sc_regmask; /* Unused */
+ unsigned int sc_status; /* Unused */
+ unsigned long long sc_pc;
+ unsigned long long sc_regs[32];
+ unsigned long long sc_fpregs[32];
+ unsigned int sc_acx; /* Was sc_ownedfp */
+ unsigned int sc_fpc_csr;
+ unsigned int sc_fpc_eir; /* Unused */
+ unsigned int sc_used_math;
+ unsigned int sc_dsp; /* dsp status, was sc_ssflags */
+ unsigned long long sc_mdhi;
+ unsigned long long sc_mdlo;
+ unsigned long sc_hi1; /* Was sc_cause */
+ unsigned long sc_lo1; /* Was sc_badvaddr */
+ unsigned long sc_hi2; /* Was sc_sigset[4] */
+ unsigned long sc_lo2;
+ unsigned long sc_hi3;
+ unsigned long sc_lo3;
+};
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/mman.h
+//----------------------------------------------------------------------
+
+#define VKI_PROT_NONE 0x0 /* No page permissions */
+#define VKI_PROT_READ 0x1 /* page can be read */
+#define VKI_PROT_WRITE 0x2 /* page can be written */
+#define VKI_PROT_EXEC 0x4 /* page can be executed */
+#define VKI_PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
+#define VKI_PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
+
+#define VKI_MAP_SHARED 0x001 /* Share changes */
+#define VKI_MAP_PRIVATE 0x002 /* Changes are private */
+#define VKI_MAP_FIXED 0x010 /* Interpret addr exactly */
+
+#define VKI_MAP_NORESERVE 0x0400 /* don't reserve swap pages */
+
+/* These are linux-specific */
+#define VKI_MAP_NORESERVE 0x0400 /* don't check for reservations */
+#define VKI_MAP_ANONYMOUS 0x0800 /* don't use a file */
+#define VKI_MAP_GROWSDOWN 0x1000 /* stack-like segment */
+#define VKI_MAP_DENYWRITE 0x2000 /* ETXTBSY */
+#define VKI_MAP_EXECUTABLE 0x4000 /* mark it as an executable */
+#define VKI_MAP_LOCKED 0x8000 /* pages are locked */
+#define VKI_MAP_POPULATE 0x10000 /* populate (prefault) pagetables */
+#define VKI_MAP_NONBLOCK 0x20000 /* do not block on IO */
+
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/fcntl.h
+//----------------------------------------------------------------------
+
+#define VKI_O_RDONLY 00
+#define VKI_O_WRONLY 01
+#define VKI_O_RDWR 02
+
+#define VKI_O_CREAT 0x0100 /* not fcntl */
+#define VKI_O_EXCL 0x0400 /* not fcntl */
+
+#define VKI_O_TRUNC 0x0200 /* not fcntl */
+
+#define VKI_O_APPEND 0x0008
+#define VKI_O_NONBLOCK 0x0080
+#define VKI_O_LARGEFILE 0x2000
+
+#define VKI_AT_FDCWD -100
+
+#define VKI_F_DUPFD 0 /* dup */
+#define VKI_F_GETFD 1 /* get close_on_exec */
+#define VKI_F_SETFD 2 /* set/clear close_on_exec */
+#define VKI_F_GETFL 3 /* get file->f_flags */
+#define VKI_F_SETFL 4 /* set file->f_flags */
+
+#define VKI_F_GETLK 14
+#define VKI_F_SETLK 6
+#define VKI_F_SETLKW 7
+
+#define VKI_F_SETOWN 24 /* for sockets. */
+#define VKI_F_GETOWN 23 /* for sockets. */
+#define VKI_F_SETSIG 10 /* for sockets. */
+#define VKI_F_GETSIG 11 /* for sockets. */
+
+#define VKI_F_SETOWN_EX 15
+#define VKI_F_GETOWN_EX 16
+
+#define VKI_F_GETLK64 33 /* using 'struct flock64' */
+#define VKI_F_SETLK64 34
+#define VKI_F_SETLKW64 35
+
+/* for F_[GET|SET]FL */
+#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */
+
+#define VKI_F_LINUX_SPECIFIC_BASE 1024
+
+struct vki_f_owner_ex {
+ int type;
+ __vki_kernel_pid_t pid;
+};
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/resource.h
+//----------------------------------------------------------------------
+
+#define VKI_RLIMIT_DATA 2 /* max data size */
+#define VKI_RLIMIT_STACK 3 /* max stack size */
+#define VKI_RLIMIT_CORE 4 /* max core file size */
+#define VKI_RLIMIT_NOFILE 5 /* max number of open files */
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/socket.h
+//----------------------------------------------------------------------
+
+#define VKI_SOL_SOCKET 0xffff
+#define VKI_SO_TYPE 0x1008
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-i386/sockios.h
+//----------------------------------------------------------------------
+
+#define VKI_SIOCSPGRP 0x8902
+#define VKI_SIOCGPGRP 0x8904
+#define VKI_SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
+#define VKI_SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/stat.h
+//----------------------------------------------------------------------
+
+struct vki_stat {
+ unsigned st_dev;
+ long st_pad1[3]; /* Reserved for network id */
+ unsigned long st_ino;
+ unsigned int st_mode;
+ unsigned long st_nlink;
+ unsigned int st_uid;
+ unsigned int st_gid;
+ unsigned st_rdev;
+ long st_pad2[2];
+ long st_size;
+ long st_pad3;
+ /*
+ * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+ * but we don't have it under Linux.
+ */
+ long st_atime;
+ long st_atime_nsec;
+ long st_mtime;
+ long st_mtime_nsec;
+ long st_ctime;
+ long st_ctime_nsec;
+ long st_blksize;
+ long st_blocks;
+ long st_pad4[14];
+};
+
+/*
+ * This matches struct stat64 in glibc2.1, hence the absolutely insane
+ * amounts of padding around dev_t's. The memory layout is the same as of
+ * struct stat of the 64-bit kernel.
+ */
+
+struct vki_stat64 {
+ unsigned long st_dev;
+ unsigned long st_pad0[3]; /* Reserved for st_dev expansion */
+
+ unsigned long long st_ino;
+
+ unsigned int st_mode;
+ unsigned long st_nlink;
+
+ unsigned int st_uid;
+ unsigned int st_gid;
+
+ unsigned long st_rdev;
+ unsigned long st_pad1[3]; /* Reserved for st_rdev expansion */
+
+ long long st_size;
+
+ /*
+ * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+ * but we don't have it under Linux.
+ */
+ long st_atime;
+ unsigned long st_atime_nsec; /* Reserved for st_atime expansion */
+
+ long st_mtime;
+ unsigned long st_mtime_nsec; /* Reserved for st_mtime expansion */
+
+ long st_ctime;
+ unsigned long st_ctime_nsec; /* Reserved for st_ctime expansion */
+
+ unsigned long st_blksize;
+ unsigned long st_pad2;
+
+ long long st_blocks;
+};
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/statfs.h
+//----------------------------------------------------------------------
+
+struct vki_statfs {
+ long f_type;
+ long f_bsize;
+ long f_frsize; /* Fragment size - unsupported */
+ long f_blocks;
+ long f_bfree;
+ long f_files;
+ long f_ffree;
+ long f_bavail;
+
+ /* Linux specials */
+ __vki_kernel_fsid_t f_fsid;
+ long f_namelen;
+ long f_spare[6];
+};
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/termios.h
+//----------------------------------------------------------------------
+
+struct vki_winsize {
+ unsigned short ws_row;
+ unsigned short ws_col;
+ unsigned short ws_xpixel;
+ unsigned short ws_ypixel;
+};
+
+#define NCC 8
+#define NCCS 23
+struct vki_termio {
+ unsigned short c_iflag; /* input mode flags */
+ unsigned short c_oflag; /* output mode flags */
+ unsigned short c_cflag; /* control mode flags */
+ unsigned short c_lflag; /* local mode flags */
+ char c_line; /* line discipline */
+ unsigned char c_cc[NCCS]; /* control characters */
+};
+
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/termbits.h
+//----------------------------------------------------------------------
+
+typedef unsigned char vki_cc_t;
+typedef unsigned long vki_speed_t;
+typedef unsigned long vki_tcflag_t;
+
+struct vki_termios {
+ vki_tcflag_t c_iflag; /* input mode flags */
+ vki_tcflag_t c_oflag; /* output mode flags */
+ vki_tcflag_t c_cflag; /* control mode flags */
+ vki_tcflag_t c_lflag; /* local mode flags */
+ vki_cc_t c_line; /* line discipline */
+ vki_cc_t c_cc[NCCS]; /* control characters */
+};
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/ioctl.h
+//----------------------------------------------------------------------
+
+#define _VKI_IOC_NRBITS 8
+#define _VKI_IOC_TYPEBITS 8
+#define _VKI_IOC_SIZEBITS 14
+#define _VKI_IOC_DIRBITS 2
+
+#define _VKI_IOC_NRMASK ((1 << _VKI_IOC_NRBITS)-1)
+#define _VKI_IOC_TYPEMASK ((1 << _VKI_IOC_TYPEBITS)-1)
+#define _VKI_IOC_SIZEMASK ((1 << _VKI_IOC_SIZEBITS)-1)
+#define _VKI_IOC_DIRMASK ((1 << _VKI_IOC_DIRBITS)-1)
+
+#define _VKI_IOC_NRSHIFT 0
+#define _VKI_IOC_TYPESHIFT (_VKI_IOC_NRSHIFT+_VKI_IOC_NRBITS)
+#define _VKI_IOC_SIZESHIFT (_VKI_IOC_TYPESHIFT+_VKI_IOC_TYPEBITS)
+#define _VKI_IOC_DIRSHIFT (_VKI_IOC_SIZESHIFT+_VKI_IOC_SIZEBITS)
+
+#define _VKI_IOC_NONE 1U
+#define _VKI_IOC_WRITE 2U
+#define _VKI_IOC_READ 4U
+
+#define _VKI_IOC(dir,type,nr,size) \
+ (((dir) << _VKI_IOC_DIRSHIFT) | \
+ ((type) << _VKI_IOC_TYPESHIFT) | \
+ ((nr) << _VKI_IOC_NRSHIFT) | \
+ ((size) << _VKI_IOC_SIZESHIFT))
+
+/* provoke compile error for invalid uses of size argument */
+extern unsigned int __VKI_invalid_size_argument_for_IOC;
+/* used to create numbers */
+#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
+#define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size)))
+#define _VKI_IOW(type,nr,size) _VKI_IOC(_VKI_IOC_WRITE,(type),(nr),(_VKI_IOC_TYPECHECK(size)))
+#define _VKI_IOWR(type,nr,size) _VKI_IOC(_VKI_IOC_READ|_VKI_IOC_WRITE,(type),(nr),(_VKI_IOC_TYPECHECK(size)))
+
+/* used to decode ioctl numbers.. */
+#define _VKI_IOC_DIR(nr) (((nr) >> _VKI_IOC_DIRSHIFT) & _VKI_IOC_DIRMASK)
+#define _VKI_IOC_TYPE(nr) (((nr) >> _VKI_IOC_TYPESHIFT) & _VKI_IOC_TYPEMASK)
+#define _VKI_IOC_NR(nr) (((nr) >> _VKI_IOC_NRSHIFT) & _VKI_IOC_NRMASK)
+#define _VKI_IOC_SIZE(nr) (((nr) >> _VKI_IOC_SIZESHIFT) & _VKI_IOC_SIZEMASK)
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/ioctls.h
+//----------------------------------------------------------------------
+
+#define VKI_TCGETA 0x5401
+#define VKI_TCSETA 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
+#define VKI_TCSETAW 0x5403
+#define VKI_TCSETAF 0x5404
+
+#define VKI_TCSBRK 0x5405
+#define VKI_TCXONC 0x5406
+#define VKI_TCFLSH 0x5407
+
+#define VKI_TCGETS 0x540d
+#define VKI_TCSETS 0x540e
+#define VKI_TCSETSW 0x540f
+#define VKI_TCSETSF 0x5410
+
+#define VKI_TIOCEXCL 0x740d /* set exclusive use of tty */
+#define VKI_TIOCNXCL 0x740e /* reset exclusive use of tty */
+#define VKI_TIOCOUTQ 0x7472 /* output queue size */
+#define VKI_TIOCSTI 0x5472 /* simulate terminal input */
+#define VKI_TIOCMGET 0x741d /* get all modem bits */
+#define VKI_TIOCMBIS 0x741b /* bis modem bits */
+#define VKI_TIOCMBIC 0x741c /* bic modem bits */
+#define VKI_TIOCMSET 0x741a /* set all modem bits */
+#define VKI_TIOCPKT 0x5470 /* pty: set/clear packet mode */
+#define VKI_TIOCPKT_DATA 0x00 /* data packet */
+#define VKI_TIOCPKT_FLUSHREAD 0x01 /* flush packet */
+#define VKI_TIOCPKT_FLUSHWRITE 0x02 /* flush packet */
+#define VKI_TIOCPKT_STOP 0x04 /* stop output */
+#define VKI_TIOCPKT_START 0x08 /* start output */
+#define VKI_TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */
+#define VKI_TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */
+/* #define TIOCPKT_IOCTL 0x40 state change of pty driver */
+#define VKI_TIOCSWINSZ _VKI_IOW('t', 103, struct vki_winsize) /* set window size */
+#define VKI_TIOCGWINSZ _VKI_IOR('t', 104, struct vki_winsize) /* get window size */
+#define VKI_TIOCNOTTY 0x5471 /* void tty association */
+#define VKI_TIOCSETD 0x7401
+#define VKI_TIOCGETD 0x7400
+
+#define VKI_FIOCLEX 0x6601
+#define VKI_FIONCLEX 0x6602
+#define VKI_FIOASYNC 0x667d
+#define VKI_FIONBIO 0x667e
+#define VKI_FIOQSIZE 0x667f
+
+#define VKI_TIOCGLTC 0x7474 /* get special local chars */
+#define VKI_TIOCSLTC 0x7475 /* set special local chars */
+#define VKI_TIOCSPGRP _VKI_IOW('t', 118, int) /* set pgrp of tty */
+#define VKI_TIOCGPGRP _VKI_IOR('t', 119, int) /* get pgrp of tty */
+#define VKI_TIOCCONS _VKI_IOW('t', 120, int) /* become virtual console */
+
+#define VKI_FIONREAD 0x467f
+#define VKI_TIOCINQ FIONREAD
+
+#define VKI_TIOCGETP 0x7408
+#define VKI_TIOCSETP 0x7409
+#define VKI_TIOCSETN 0x740a /* TIOCSETP wo flush */
+
+#define VKI_TIOCSBRK 0x5427 /* BSD compatibility */
+#define VKI_TIOCCBRK 0x5428 /* BSD compatibility */
+#define VKI_TIOCGSID 0x7416 /* Return the session ID of FD */
+#define VKI_TIOCGPTN _VKI_IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define VKI_TIOCSPTLCK _VKI_IOW('T',0x31, int) /* Lock/unlock Pty */
+
+/* I hope the range from 0x5480 on is free ... */
+#define VKI_TIOCSCTTY 0x5480 /* become controlling tty */
+#define VKI_TIOCGSOFTCAR 0x5481
+#define VKI_TIOCSSOFTCAR 0x5482
+#define VKI_TIOCLINUX 0x5483
+#define VKI_TIOCGSERIAL 0x5484
+#define VKI_TIOCSSERIAL 0x5485
+#define VKI_TCSBRKP 0x5486 /* Needed for POSIX tcsendbreak() */
+#define VKI_TIOCSERCONFIG 0x5488
+#define VKI_TIOCSERGWILD 0x5489
+#define VKI_TIOCSERSWILD 0x548a
+#define VKI_TIOCGLCKTRMIOS 0x548b
+#define VKI_TIOCSLCKTRMIOS 0x548c
+#define VKI_TIOCSERGSTRUCT 0x548d /* For debugging only */
+#define VKI_TIOCSERGETLSR 0x548e /* Get line status register */
+#define VKI_TIOCSERGETMULTI 0x548f /* Get multiport config */
+#define VKI_TIOCSERSETMULTI 0x5490 /* Set multiport config */
+#define VKI_TIOCMIWAIT 0x5491 /* wait for a change on serial input line(s) */
+#define VKI_TIOCGICOUNT 0x5492 /* read serial port inline interrupt counts */
+#define VKI_TIOCGHAYESESP 0x5493 /* Get Hayes ESP configuration */
+#define VKI_TIOCSHAYESESP 0x5494 /* Set Hayes ESP configuration */
+
+//----------------------------------------------------------------------
+// From asm-generic/poll.h
+//----------------------------------------------------------------------
+
+/* These are specified by iBCS2 */
+#define VKI_POLLIN 0x0001
+
+struct vki_pollfd {
+ int fd;
+ short events;
+ short revents;
+};
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/ucontext.h
+//----------------------------------------------------------------------
+
+struct vki_ucontext {
+ unsigned long uc_flags;
+ struct vki_ucontext *uc_link;
+ vki_stack_t uc_stack;
+ struct vki_sigcontext uc_mcontext;
+ vki_sigset_t uc_sigmask; /* mask last for extensibility */
+};
+
+// CAB: TODO
+typedef void vki_modify_ldt_t;
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/ipcbuf.h
+//----------------------------------------------------------------------
+
+struct vki_ipc64_perm
+{
+ __vki_kernel_key_t key;
+ __vki_kernel_uid_t uid;
+ __vki_kernel_gid_t gid;
+ __vki_kernel_uid_t cuid;
+ __vki_kernel_gid_t cgid;
+ __vki_kernel_mode_t mode;
+ unsigned short seq;
+ unsigned short __pad1;
+ unsigned long __unused1;
+ unsigned long __unused2;
+};
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/sembuf.h
+//----------------------------------------------------------------------
+
+struct vki_semid64_ds {
+ struct vki_ipc64_perm sem_perm; /* permissions .. see ipc.h */
+ __vki_kernel_time_t sem_otime; /* last semop time */
+ __vki_kernel_time_t sem_ctime; /* last change time */
+ unsigned long sem_nsems; /* no. of semaphores in array */
+ unsigned long __unused1;
+ unsigned long __unused2;
+};
+
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/msgbuf.h
+//----------------------------------------------------------------------
+
+struct vki_msqid64_ds {
+ struct vki_ipc64_perm msg_perm;
+ __vki_kernel_time_t msg_stime; /* last msgsnd time */
+ unsigned long __unused1;
+ __vki_kernel_time_t msg_rtime; /* last msgrcv time */
+ unsigned long __unused2;
+ __vki_kernel_time_t msg_ctime; /* last change time */
+ unsigned long __unused3;
+ unsigned long msg_cbytes; /* current number of bytes on queue */
+ unsigned long msg_qnum; /* number of messages in queue */
+ unsigned long msg_qbytes; /* max number of bytes on queue */
+ __vki_kernel_pid_t msg_lspid; /* pid of last msgsnd */
+ __vki_kernel_pid_t msg_lrpid; /* last receive pid */
+ unsigned long __unused4;
+ unsigned long __unused5;
+};
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/ipc.h
+//----------------------------------------------------------------------
+
+struct vki_ipc_kludge {
+ struct vki_msgbuf __user *msgp;
+ long msgtyp;
+};
+
+#define VKI_SEMOP 1
+#define VKI_SEMGET 2
+#define VKI_SEMCTL 3
+#define VKI_SEMTIMEDOP 4
+#define VKI_MSGSND 11
+#define VKI_MSGRCV 12
+#define VKI_MSGGET 13
+#define VKI_MSGCTL 14
+#define VKI_SHMAT 21
+#define VKI_SHMDT 22
+#define VKI_SHMGET 23
+#define VKI_SHMCTL 24
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/shmbuf.h
+//----------------------------------------------------------------------
+
+struct vki_shmid64_ds {
+ struct vki_ipc64_perm shm_perm; /* operation perms */
+ vki_size_t shm_segsz; /* size of segment (bytes) */
+ __vki_kernel_time_t shm_atime; /* last attach time */
+ __vki_kernel_time_t shm_dtime; /* last detach time */
+ __vki_kernel_time_t shm_ctime; /* last change time */
+ __vki_kernel_pid_t shm_cpid; /* pid of creator */
+ __vki_kernel_pid_t shm_lpid; /* pid of last operator */
+ unsigned long shm_nattch; /* no. of current attaches */
+ unsigned long __unused1;
+ unsigned long __unused2;
+};
+
+struct vki_shminfo64 {
+ unsigned long shmmax;
+ unsigned long shmmin;
+ unsigned long shmmni;
+ unsigned long shmseg;
+ unsigned long shmall;
+ unsigned long __unused1;
+ unsigned long __unused2;
+ unsigned long __unused3;
+ unsigned long __unused4;
+};
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/ptrace.h
+//----------------------------------------------------------------------
+
+struct vki_pt_regs {
+#ifdef CONFIG_32BIT
+ /* Pad bytes for argument save space on the stack. */
+ unsigned long pad0[6];
+#endif
+ /* Saved main processor registers. */
+ unsigned long regs[32];
+
+ /* Saved special registers. */
+ unsigned long cp0_status;
+ unsigned long hi;
+ unsigned long lo;
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+ unsigned long acx;
+#endif
+ unsigned long cp0_badvaddr;
+ unsigned long cp0_cause;
+ unsigned long cp0_epc;
+#ifdef CONFIG_MIPS_MT_SMTC
+ unsigned long cp0_tcstatus;
+#endif /* CONFIG_MIPS_MT_SMTC */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ unsigned long long mpl[3]; /* MTM{0,1,2} */
+ unsigned long long mtp[3]; /* MTP{0,1,2} */
+#endif
+} __attribute__ ((aligned (8)));
+
+
+#define vki_user_regs_struct vki_pt_regs
+
+#define MIPS_lo lo
+#define MIPS_hi hi
+//#define MIPS_pc regs[32]
+#define MIPS_r31 regs[31]
+#define MIPS_r30 regs[30]
+#define MIPS_r29 regs[29]
+#define MIPS_r28 regs[28]
+#define MIPS_r27 regs[27]
+#define MIPS_r26 regs[26]
+#define MIPS_r25 regs[25]
+#define MIPS_r24 regs[24]
+#define MIPS_r23 regs[23]
+#define MIPS_r22 regs[22]
+#define MIPS_r21 regs[21]
+#define MIPS_r20 regs[20]
+#define MIPS_r19 regs[19]
+#define MIPS_r18 regs[18]
+#define MIPS_r17 regs[17]
+#define MIPS_r16 regs[16]
+#define MIPS_r15 regs[15]
+#define MIPS_r14 regs[14]
+#define MIPS_r13 regs[13]
+#define MIPS_r12 regs[12]
+#define MIPS_r11 regs[11]
+#define MIPS_r10 regs[10]
+#define MIPS_r9 regs[9]
+#define MIPS_r8 regs[8]
+#define MIPS_r7 regs[7]
+#define MIPS_r6 regs[6]
+#define MIPS_r5 regs[5]
+#define MIPS_r4 regs[4]
+#define MIPS_r3 regs[3]
+#define MIPS_r2 regs[2]
+#define MIPS_r1 regs[1]
+#define MIPS_r0 regs[0]
+
+#define VKI_PTRACE_GETREGS 12
+#define VKI_PTRACE_SETREGS 13
+#define VKI_PTRACE_GETFPREGS 14
+#define VKI_PTRACE_SETFPREGS 15
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/elf.h
+//----------------------------------------------------------------------
+typedef unsigned long vki_elf_greg_t;
+
+#define VKI_ELF_NGREG (sizeof (struct vki_user_regs_struct) / sizeof(vki_elf_greg_t))
+#define VKI_ELF_NFPREG 33 /* includes fpscr */
+
+typedef vki_elf_greg_t vki_elf_gregset_t[VKI_ELF_NGREG];
+
+typedef double vki_elf_fpreg_t;
+typedef vki_elf_fpreg_t vki_elf_fpregset_t[VKI_ELF_NFPREG];
+
+typedef struct vki_user_fxsr_struct vki_elf_fpxregset_t;
+
+#define VKI_AT_SYSINFO 32
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-generic/siginfo.h
+//----------------------------------------------------------------------
+#define HAVE_ARCH_SIGINFO_T
+
+typedef union vki_sigval {
+ int sival_int;
+ void __user *sival_ptr;
+} vki_sigval_t;
+
+#ifndef __VKI_ARCH_SI_PREAMBLE_SIZE
+#define __VKI_ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
+#endif
+
+#define VKI_SI_MAX_SIZE 128
+
+#ifndef VKI_SI_PAD_SIZE
+#define VKI_SI_PAD_SIZE ((VKI_SI_MAX_SIZE - __VKI_ARCH_SI_PREAMBLE_SIZE) / sizeof(int))
+#endif
+
+#ifndef __VKI_ARCH_SI_UID_T
+#define __VKI_ARCH_SI_UID_T vki_uid_t
+#endif
+
+#ifndef __VKI_ARCH_SI_BAND_T
+#define __VKI_ARCH_SI_BAND_T long
+#endif
+
+typedef struct vki_siginfo {
+ int si_signo;
+ int si_code;
+ int si_errno;
+ int __pad0[VKI_SI_MAX_SIZE / sizeof(int) - VKI_SI_PAD_SIZE - 3];
+
+ union {
+ int _pad[VKI_SI_PAD_SIZE];
+
+ /* kill() */
+ struct {
+ vki_pid_t _pid; /* sender's pid */
+ __VKI_ARCH_SI_UID_T _uid; /* sender's uid */
+ } _kill;
+
+ /* POSIX.1b timers */
+ struct {
+ vki_timer_t _tid; /* timer id */
+ int _overrun; /* overrun count */
+ char _pad[sizeof( __VKI_ARCH_SI_UID_T) - sizeof(int)];
+ vki_sigval_t _sigval; /* same as below */
+ int _sys_private; /* not to be passed to user */
+ } _timer;
+
+ /* POSIX.1b signals */
+ struct {
+ vki_pid_t _pid; /* sender's pid */
+ __VKI_ARCH_SI_UID_T _uid; /* sender's uid */
+ vki_sigval_t _sigval;
+ } _rt;
+
+ /* SIGCHLD */
+ struct {
+ vki_pid_t _pid; /* which child */
+ __VKI_ARCH_SI_UID_T _uid; /* sender's uid */
+ int _status; /* exit code */
+ vki_clock_t _utime;
+ vki_clock_t _stime;
+ } _sigchld;
+
+ /* IRIX SIGCHLD */
+ struct {
+ vki_pid_t _pid; /* which child */
+ vki_clock_t _utime;
+ int _status; /* exit code */
+ vki_clock_t _stime;
+ } _irix_sigchld;
+
+ /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+ struct {
+ void __user *_addr; /* faulting insn/memory ref. */
+#ifdef __ARCH_SI_TRAPNO
+ int _trapno; /* TRAP # which caused the signal */
+#endif
+ } _sigfault;
+
+ /* SIGPOLL, SIGXFSZ (To do ...) */
+ struct {
+ __VKI_ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
+ int _fd;
+ } _sigpoll;
+ } _sifields;
+} vki_siginfo_t;
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm/break.h
+//----------------------------------------------------------------------
+#define VKI_BRK_OVERFLOW 6 /* Overflow check */
+#define VKI_BRK_DIVZERO 7 /* Divide by zero check */
+
+#endif // __VKI_MIPS32_LINUX_H
+
+
+/*--------------------------------------------------------------------*/
+/*--- end vki-mips32-linux.h ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/include/vki/vki-posixtypes-amd64-linux.h b/main/include/vki/vki-posixtypes-amd64-linux.h
index 32a2fc9..4d0f1d4 100644
--- a/main/include/vki/vki-posixtypes-amd64-linux.h
+++ b/main/include/vki/vki-posixtypes-amd64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/vki/vki-posixtypes-arm-linux.h b/main/include/vki/vki-posixtypes-arm-linux.h
index e9f910b..d20c7ce 100644
--- a/main/include/vki/vki-posixtypes-arm-linux.h
+++ b/main/include/vki/vki-posixtypes-arm-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/vki/vki-posixtypes-mips32-linux.h b/main/include/vki/vki-posixtypes-mips32-linux.h
new file mode 100644
index 0000000..45d3ebf
--- /dev/null
+++ b/main/include/vki/vki-posixtypes-mips32-linux.h
@@ -0,0 +1,68 @@
+
+/*--------------------------------------------------------------------*/
+/*--- mips/Linux-specific kernel interface: posix types. ---*/
+/*--- vki-posixtypes-mips32-linux.h ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __VKI_POSIXTYPES_MIPS32_LINUX_H
+#define __VKI_POSIXTYPES_MIPS32_LINUX_H
+
+//----------------------------------------------------------------------
+// From linux-2.6.35.5/include/asm-mips/posix_types.h
+//----------------------------------------------------------------------
+
+typedef unsigned int __vki_kernel_mode_t;
+typedef long __vki_kernel_off_t;
+typedef int __vki_kernel_pid_t;
+typedef int __vki_kernel_ipc_pid_t;
+typedef unsigned int __vki_kernel_uid_t;
+typedef unsigned int __vki_kernel_gid_t;
+typedef unsigned int __vki_kernel_size_t;
+typedef long __vki_kernel_time_t;
+typedef long __vki_kernel_suseconds_t;
+typedef long __vki_kernel_clock_t;
+typedef int __vki_kernel_timer_t;
+typedef int __vki_kernel_clockid_t;
+typedef char * __vki_kernel_caddr_t;
+typedef unsigned int __vki_kernel_uid32_t;
+typedef unsigned int __vki_kernel_gid32_t;
+
+typedef unsigned int __vki_kernel_old_uid_t;
+typedef unsigned int __vki_kernel_old_gid_t;
+
+typedef long long __vki_kernel_loff_t;
+
+typedef struct {
+ int val[2];
+} __vki_kernel_fsid_t;
+
+#endif // __VKI_POSIXTYPES_MIPS32_LINUX_H
+
+/*--------------------------------------------------------------------*/
+/*--- end vki-posixtypes-mips32-linux.h ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/include/vki/vki-posixtypes-ppc32-linux.h b/main/include/vki/vki-posixtypes-ppc32-linux.h
index a5c4524..bf93eae 100644
--- a/main/include/vki/vki-posixtypes-ppc32-linux.h
+++ b/main/include/vki/vki-posixtypes-ppc32-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Julian Seward
+ Copyright (C) 2005-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/vki/vki-posixtypes-ppc64-linux.h b/main/include/vki/vki-posixtypes-ppc64-linux.h
index 2b002e5..6697758 100644
--- a/main/include/vki/vki-posixtypes-ppc64-linux.h
+++ b/main/include/vki/vki-posixtypes-ppc64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Julian Seward
+ Copyright (C) 2005-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/vki/vki-posixtypes-s390x-linux.h b/main/include/vki/vki-posixtypes-s390x-linux.h
index 1dc753e..f2c9e53 100644
--- a/main/include/vki/vki-posixtypes-s390x-linux.h
+++ b/main/include/vki/vki-posixtypes-s390x-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
diff --git a/main/include/vki/vki-posixtypes-x86-linux.h b/main/include/vki/vki-posixtypes-x86-linux.h
index 2bb3025..e6c6235 100644
--- a/main/include/vki/vki-posixtypes-x86-linux.h
+++ b/main/include/vki/vki-posixtypes-x86-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
diff --git a/main/include/vki/vki-ppc32-linux.h b/main/include/vki/vki-ppc32-linux.h
index d0c5ba6..76b6a06 100644
--- a/main/include/vki/vki-ppc32-linux.h
+++ b/main/include/vki/vki-ppc32-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Julian Seward
+ Copyright (C) 2005-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -337,6 +337,18 @@
#define VKI_F_SETLK64 13
#define VKI_F_SETLKW64 14
+#define VKI_F_SETOWN_EX 15
+#define VKI_F_GETOWN_EX 16
+
+#define VKI_F_OWNER_TID 0
+#define VKI_F_OWNER_PID 1
+#define VKI_F_OWNER_PGRP 2
+
+struct vki_f_owner_ex {
+ int type;
+ __vki_kernel_pid_t pid;
+};
+
/* for F_[GET|SET]FL */
#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */
diff --git a/main/include/vki/vki-ppc64-linux.h b/main/include/vki/vki-ppc64-linux.h
index 6e50b5b..7202a59 100644
--- a/main/include/vki/vki-ppc64-linux.h
+++ b/main/include/vki/vki-ppc64-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Julian Seward
+ Copyright (C) 2005-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -386,6 +386,18 @@
#define VKI_F_SETSIG 10 /* for sockets. */
#define VKI_F_GETSIG 11 /* for sockets. */
+#define VKI_F_SETOWN_EX 15
+#define VKI_F_GETOWN_EX 16
+
+#define VKI_F_OWNER_TID 0
+#define VKI_F_OWNER_PID 1
+#define VKI_F_OWNER_PGRP 2
+
+struct vki_f_owner_ex {
+ int type;
+ __vki_kernel_pid_t pid;
+};
+
/* for F_[GET|SET]FL */
#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */
diff --git a/main/include/vki/vki-s390x-linux.h b/main/include/vki/vki-s390x-linux.h
index 2b5b861..8aa2ae4 100644
--- a/main/include/vki/vki-s390x-linux.h
+++ b/main/include/vki/vki-s390x-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -332,6 +332,18 @@
#define VKI_F_SETSIG 10 /* for sockets. */
#define VKI_F_GETSIG 11 /* for sockets. */
+#define VKI_F_SETOWN_EX 15
+#define VKI_F_GETOWN_EX 16
+
+#define VKI_F_OWNER_TID 0
+#define VKI_F_OWNER_PID 1
+#define VKI_F_OWNER_PGRP 2
+
+struct vki_f_owner_ex {
+ int type;
+ __vki_kernel_pid_t pid;
+};
+
#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */
#define VKI_F_LINUX_SPECIFIC_BASE 1024
diff --git a/main/include/vki/vki-scnums-amd64-linux.h b/main/include/vki/vki-scnums-amd64-linux.h
index 81db239..85ade42 100644
--- a/main/include/vki/vki-scnums-amd64-linux.h
+++ b/main/include/vki/vki-scnums-amd64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -32,7 +32,7 @@
#ifndef __VKI_SCNUMS_AMD64_LINUX_H
#define __VKI_SCNUMS_AMD64_LINUX_H
-// From linux-2.6.9/include/asm-x86_64/unistd.h
+// Derived from linux-2.6/arch/x86/syscalls/syscall_64.tbl
#define __NR_read 0
#define __NR_write 1
@@ -390,6 +390,9 @@
#define __NR_syncfs 306
#define __NR_sendmmsg 307
#define __NR_setns 308
+#define __NR_getcpu 309
+#define __NR_process_vm_readv 310
+#define __NR_process_vm_writev 311
#endif /* __VKI_SCNUMS_AMD64_LINUX_H */
diff --git a/main/include/vki/vki-scnums-arm-linux.h b/main/include/vki/vki-scnums-arm-linux.h
index 0a184fa..6a629cf 100644
--- a/main/include/vki/vki-scnums-arm-linux.h
+++ b/main/include/vki/vki-scnums-arm-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2008-2011 Evan Geller
+ Copyright (C) 2008-2012 Evan Geller
gaze@bea.ms
This program is free software; you can redistribute it and/or
@@ -32,7 +32,7 @@
#ifndef __VKI_SCNUMS_ARM_LINUX_H
#define __VKI_SCNUMS_ARM_LINUX_H
-// From linux-2.6.26.2/include/asm-arm/unistd.h
+// From linux-2.6/arch/arm/include/asm/unistd.h
#define __NR_restart_syscall 0
#define __NR_exit 1
@@ -412,6 +412,8 @@
#define __NR_syncfs 373
#define __NR_sendmmsg 374
#define __NR_setns 375
+#define __NR_process_vm_readv 376
+#define __NR_process_vm_writev 377
diff --git a/main/include/vki/vki-scnums-darwin.h b/main/include/vki/vki-scnums-darwin.h
index 516b97c..0e3801b 100644
--- a/main/include/vki/vki-scnums-darwin.h
+++ b/main/include/vki/vki-scnums-darwin.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2007-2011 Apple Inc.
+ Copyright (C) 2007-2012 Apple Inc.
Greg Parker gparker@apple.com
This program is free software; you can redistribute it and/or
diff --git a/main/include/vki/vki-scnums-mips32-linux.h b/main/include/vki/vki-scnums-mips32-linux.h
new file mode 100644
index 0000000..cdcac7b
--- /dev/null
+++ b/main/include/vki/vki-scnums-mips32-linux.h
@@ -0,0 +1,398 @@
+
+/*--------------------------------------------------------------------*/
+/*--- System call numbers for mips32-linux. ---*/
+/*--- vki-scnums-mips32-linux.h ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2012 RT-RK
+ mips-valgrind@rt-rk.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __VKI_SCNUMS_MIPS32_LINUX_H
+#define __VKI_SCNUMS_MIPS32_LINUX_H
+
+// From linux-2.6.35.5/include/asm-mips/unistd.h
+/*
+ * Linux o32 style syscalls are in the range from 4000 to 4999.
+ */
+#define __NR_Linux 4000
+#define __NR_syscall (__NR_Linux + 0)
+#define __NR_exit (__NR_Linux + 1)
+#define __NR_fork (__NR_Linux + 2)
+#define __NR_read (__NR_Linux + 3)
+#define __NR_write (__NR_Linux + 4)
+#define __NR_open (__NR_Linux + 5)
+#define __NR_close (__NR_Linux + 6)
+#define __NR_waitpid (__NR_Linux + 7)
+#define __NR_creat (__NR_Linux + 8)
+#define __NR_link (__NR_Linux + 9)
+#define __NR_unlink (__NR_Linux + 10)
+#define __NR_execve (__NR_Linux + 11)
+#define __NR_chdir (__NR_Linux + 12)
+#define __NR_time (__NR_Linux + 13)
+#define __NR_mknod (__NR_Linux + 14)
+#define __NR_chmod (__NR_Linux + 15)
+#define __NR_lchown (__NR_Linux + 16)
+#define __NR_break (__NR_Linux + 17)
+#define __NR_unused18 (__NR_Linux + 18)
+#define __NR_lseek (__NR_Linux + 19)
+#define __NR_getpid (__NR_Linux + 20)
+#define __NR_mount (__NR_Linux + 21)
+#define __NR_umount (__NR_Linux + 22)
+#define __NR_setuid (__NR_Linux + 23)
+#define __NR_getuid (__NR_Linux + 24)
+#define __NR_stime (__NR_Linux + 25)
+#define __NR_ptrace (__NR_Linux + 26)
+#define __NR_alarm (__NR_Linux + 27)
+#define __NR_unused28 (__NR_Linux + 28)
+#define __NR_pause (__NR_Linux + 29)
+#define __NR_utime (__NR_Linux + 30)
+#define __NR_stty (__NR_Linux + 31)
+#define __NR_gtty (__NR_Linux + 32)
+#define __NR_access (__NR_Linux + 33)
+#define __NR_nice (__NR_Linux + 34)
+#define __NR_ftime (__NR_Linux + 35)
+#define __NR_sync (__NR_Linux + 36)
+#define __NR_kill (__NR_Linux + 37)
+#define __NR_rename (__NR_Linux + 38)
+#define __NR_mkdir (__NR_Linux + 39)
+#define __NR_rmdir (__NR_Linux + 40)
+#define __NR_dup (__NR_Linux + 41)
+#define __NR_pipe (__NR_Linux + 42)
+#define __NR_times (__NR_Linux + 43)
+#define __NR_prof (__NR_Linux + 44)
+#define __NR_brk (__NR_Linux + 45)
+#define __NR_setgid (__NR_Linux + 46)
+#define __NR_getgid (__NR_Linux + 47)
+#define __NR_signal (__NR_Linux + 48)
+#define __NR_geteuid (__NR_Linux + 49)
+#define __NR_getegid (__NR_Linux + 50)
+#define __NR_acct (__NR_Linux + 51)
+#define __NR_umount2 (__NR_Linux + 52)
+#define __NR_lock (__NR_Linux + 53)
+#define __NR_ioctl (__NR_Linux + 54)
+#define __NR_fcntl (__NR_Linux + 55)
+#define __NR_mpx (__NR_Linux + 56)
+#define __NR_setpgid (__NR_Linux + 57)
+#define __NR_ulimit (__NR_Linux + 58)
+#define __NR_unused59 (__NR_Linux + 59)
+#define __NR_umask (__NR_Linux + 60)
+#define __NR_chroot (__NR_Linux + 61)
+#define __NR_ustat (__NR_Linux + 62)
+#define __NR_dup2 (__NR_Linux + 63)
+#define __NR_getppid (__NR_Linux + 64)
+#define __NR_getpgrp (__NR_Linux + 65)
+#define __NR_setsid (__NR_Linux + 66)
+#define __NR_sigaction (__NR_Linux + 67)
+#define __NR_sgetmask (__NR_Linux + 68)
+#define __NR_ssetmask (__NR_Linux + 69)
+#define __NR_setreuid (__NR_Linux + 70)
+#define __NR_setregid (__NR_Linux + 71)
+#define __NR_sigsuspend (__NR_Linux + 72)
+#define __NR_sigpending (__NR_Linux + 73)
+#define __NR_sethostname (__NR_Linux + 74)
+#define __NR_setrlimit (__NR_Linux + 75)
+#define __NR_getrlimit (__NR_Linux + 76)
+#define __NR_getrusage (__NR_Linux + 77)
+#define __NR_gettimeofday (__NR_Linux + 78)
+#define __NR_settimeofday (__NR_Linux + 79)
+#define __NR_getgroups (__NR_Linux + 80)
+#define __NR_setgroups (__NR_Linux + 81)
+#define __NR_reserved82 (__NR_Linux + 82)
+#define __NR_symlink (__NR_Linux + 83)
+#define __NR_unused84 (__NR_Linux + 84)
+#define __NR_readlink (__NR_Linux + 85)
+#define __NR_uselib (__NR_Linux + 86)
+#define __NR_swapon (__NR_Linux + 87)
+#define __NR_reboot (__NR_Linux + 88)
+#define __NR_readdir (__NR_Linux + 89)
+#define __NR_mmap (__NR_Linux + 90)
+#define __NR_munmap (__NR_Linux + 91)
+#define __NR_truncate (__NR_Linux + 92)
+#define __NR_ftruncate (__NR_Linux + 93)
+#define __NR_fchmod (__NR_Linux + 94)
+#define __NR_fchown (__NR_Linux + 95)
+#define __NR_getpriority (__NR_Linux + 96)
+#define __NR_setpriority (__NR_Linux + 97)
+#define __NR_profil (__NR_Linux + 98)
+#define __NR_statfs (__NR_Linux + 99)
+#define __NR_fstatfs (__NR_Linux + 100)
+#define __NR_ioperm (__NR_Linux + 101)
+#define __NR_socketcall (__NR_Linux + 102)
+#define __NR_syslog (__NR_Linux + 103)
+#define __NR_setitimer (__NR_Linux + 104)
+#define __NR_getitimer (__NR_Linux + 105)
+#define __NR_stat (__NR_Linux + 106)
+#define __NR_lstat (__NR_Linux + 107)
+#define __NR_fstat (__NR_Linux + 108)
+#define __NR_unused109 (__NR_Linux + 109)
+#define __NR_iopl (__NR_Linux + 110)
+#define __NR_vhangup (__NR_Linux + 111)
+#define __NR_idle (__NR_Linux + 112)
+#define __NR_vm86 (__NR_Linux + 113)
+#define __NR_wait4 (__NR_Linux + 114)
+#define __NR_swapoff (__NR_Linux + 115)
+#define __NR_sysinfo (__NR_Linux + 116)
+#define __NR_ipc (__NR_Linux + 117)
+#define __NR_fsync (__NR_Linux + 118)
+#define __NR_sigreturn (__NR_Linux + 119)
+#define __NR_clone (__NR_Linux + 120)
+#define __NR_setdomainname (__NR_Linux + 121)
+#define __NR_uname (__NR_Linux + 122)
+#define __NR_modify_ldt (__NR_Linux + 123)
+#define __NR_adjtimex (__NR_Linux + 124)
+#define __NR_mprotect (__NR_Linux + 125)
+#define __NR_sigprocmask (__NR_Linux + 126)
+#define __NR_create_module (__NR_Linux + 127)
+#define __NR_init_module (__NR_Linux + 128)
+#define __NR_delete_module (__NR_Linux + 129)
+#define __NR_get_kernel_syms (__NR_Linux + 130)
+#define __NR_quotactl (__NR_Linux + 131)
+#define __NR_getpgid (__NR_Linux + 132)
+#define __NR_fchdir (__NR_Linux + 133)
+#define __NR_bdflush (__NR_Linux + 134)
+#define __NR_sysfs (__NR_Linux + 135)
+#define __NR_personality (__NR_Linux + 136)
+#define __NR_afs_syscall (__NR_Linux + 137)
+#define __NR_setfsuid (__NR_Linux + 138)
+#define __NR_setfsgid (__NR_Linux + 139)
+#define __NR__llseek (__NR_Linux + 140)
+#define __NR_getdents (__NR_Linux + 141)
+#define __NR__newselect (__NR_Linux + 142)
+#define __NR_flock (__NR_Linux + 143)
+#define __NR_msync (__NR_Linux + 144)
+#define __NR_readv (__NR_Linux + 145)
+#define __NR_writev (__NR_Linux + 146)
+#define __NR_cacheflush (__NR_Linux + 147)
+#define __NR_cachectl (__NR_Linux + 148)
+#define __NR_sysmips (__NR_Linux + 149)
+#define __NR_unused150 (__NR_Linux + 150)
+#define __NR_getsid (__NR_Linux + 151)
+#define __NR_fdatasync (__NR_Linux + 152)
+#define __NR__sysctl (__NR_Linux + 153)
+#define __NR_mlock (__NR_Linux + 154)
+#define __NR_munlock (__NR_Linux + 155)
+#define __NR_mlockall (__NR_Linux + 156)
+#define __NR_munlockall (__NR_Linux + 157)
+#define __NR_sched_setparam (__NR_Linux + 158)
+#define __NR_sched_getparam (__NR_Linux + 159)
+#define __NR_sched_setscheduler (__NR_Linux + 160)
+#define __NR_sched_getscheduler (__NR_Linux + 161)
+#define __NR_sched_yield (__NR_Linux + 162)
+#define __NR_sched_get_priority_max (__NR_Linux + 163)
+#define __NR_sched_get_priority_min (__NR_Linux + 164)
+#define __NR_sched_rr_get_interval (__NR_Linux + 165)
+#define __NR_nanosleep (__NR_Linux + 166)
+#define __NR_mremap (__NR_Linux + 167)
+#define __NR_accept (__NR_Linux + 168)
+#define __NR_bind (__NR_Linux + 169)
+#define __NR_connect (__NR_Linux + 170)
+#define __NR_getpeername (__NR_Linux + 171)
+#define __NR_getsockname (__NR_Linux + 172)
+#define __NR_getsockopt (__NR_Linux + 173)
+#define __NR_listen (__NR_Linux + 174)
+#define __NR_recv (__NR_Linux + 175)
+#define __NR_recvfrom (__NR_Linux + 176)
+#define __NR_recvmsg (__NR_Linux + 177)
+#define __NR_send (__NR_Linux + 178)
+#define __NR_sendmsg (__NR_Linux + 179)
+#define __NR_sendto (__NR_Linux + 180)
+#define __NR_setsockopt (__NR_Linux + 181)
+#define __NR_shutdown (__NR_Linux + 182)
+#define __NR_socket (__NR_Linux + 183)
+#define __NR_socketpair (__NR_Linux + 184)
+#define __NR_setresuid (__NR_Linux + 185)
+#define __NR_getresuid (__NR_Linux + 186)
+#define __NR_query_module (__NR_Linux + 187)
+#define __NR_poll (__NR_Linux + 188)
+#define __NR_nfsservctl (__NR_Linux + 189)
+#define __NR_setresgid (__NR_Linux + 190)
+#define __NR_getresgid (__NR_Linux + 191)
+#define __NR_prctl (__NR_Linux + 192)
+#define __NR_rt_sigreturn (__NR_Linux + 193)
+#define __NR_rt_sigaction (__NR_Linux + 194)
+#define __NR_rt_sigprocmask (__NR_Linux + 195)
+#define __NR_rt_sigpending (__NR_Linux + 196)
+#define __NR_rt_sigtimedwait (__NR_Linux + 197)
+#define __NR_rt_sigqueueinfo (__NR_Linux + 198)
+#define __NR_rt_sigsuspend (__NR_Linux + 199)
+#define __NR_pread64 (__NR_Linux + 200)
+#define __NR_pwrite64 (__NR_Linux + 201)
+#define __NR_chown (__NR_Linux + 202)
+#define __NR_getcwd (__NR_Linux + 203)
+#define __NR_capget (__NR_Linux + 204)
+#define __NR_capset (__NR_Linux + 205)
+#define __NR_sigaltstack (__NR_Linux + 206)
+#define __NR_sendfile (__NR_Linux + 207)
+#define __NR_getpmsg (__NR_Linux + 208)
+#define __NR_putpmsg (__NR_Linux + 209)
+#define __NR_mmap2 (__NR_Linux + 210)
+#define __NR_truncate64 (__NR_Linux + 211)
+#define __NR_ftruncate64 (__NR_Linux + 212)
+#define __NR_stat64 (__NR_Linux + 213)
+#define __NR_lstat64 (__NR_Linux + 214)
+#define __NR_fstat64 (__NR_Linux + 215)
+#define __NR_pivot_root (__NR_Linux + 216)
+#define __NR_mincore (__NR_Linux + 217)
+#define __NR_madvise (__NR_Linux + 218)
+#define __NR_getdents64 (__NR_Linux + 219)
+#define __NR_fcntl64 (__NR_Linux + 220)
+#define __NR_reserved221 (__NR_Linux + 221)
+#define __NR_gettid (__NR_Linux + 222)
+#define __NR_readahead (__NR_Linux + 223)
+#define __NR_setxattr (__NR_Linux + 224)
+#define __NR_lsetxattr (__NR_Linux + 225)
+#define __NR_fsetxattr (__NR_Linux + 226)
+#define __NR_getxattr (__NR_Linux + 227)
+#define __NR_lgetxattr (__NR_Linux + 228)
+#define __NR_fgetxattr (__NR_Linux + 229)
+#define __NR_listxattr (__NR_Linux + 230)
+#define __NR_llistxattr (__NR_Linux + 231)
+#define __NR_flistxattr (__NR_Linux + 232)
+#define __NR_removexattr (__NR_Linux + 233)
+#define __NR_lremovexattr (__NR_Linux + 234)
+#define __NR_fremovexattr (__NR_Linux + 235)
+#define __NR_tkill (__NR_Linux + 236)
+#define __NR_sendfile64 (__NR_Linux + 237)
+#define __NR_futex (__NR_Linux + 238)
+#define __NR_sched_setaffinity (__NR_Linux + 239)
+#define __NR_sched_getaffinity (__NR_Linux + 240)
+#define __NR_io_setup (__NR_Linux + 241)
+#define __NR_io_destroy (__NR_Linux + 242)
+#define __NR_io_getevents (__NR_Linux + 243)
+#define __NR_io_submit (__NR_Linux + 244)
+#define __NR_io_cancel (__NR_Linux + 245)
+#define __NR_exit_group (__NR_Linux + 246)
+#define __NR_lookup_dcookie (__NR_Linux + 247)
+#define __NR_epoll_create (__NR_Linux + 248)
+#define __NR_epoll_ctl (__NR_Linux + 249)
+#define __NR_epoll_wait (__NR_Linux + 250)
+#define __NR_remap_file_pages (__NR_Linux + 251)
+#define __NR_set_tid_address (__NR_Linux + 252)
+#define __NR_restart_syscall (__NR_Linux + 253)
+#define __NR_fadvise64 (__NR_Linux + 254)
+#define __NR_statfs64 (__NR_Linux + 255)
+#define __NR_fstatfs64 (__NR_Linux + 256)
+#define __NR_timer_create (__NR_Linux + 257)
+#define __NR_timer_settime (__NR_Linux + 258)
+#define __NR_timer_gettime (__NR_Linux + 259)
+#define __NR_timer_getoverrun (__NR_Linux + 260)
+#define __NR_timer_delete (__NR_Linux + 261)
+#define __NR_clock_settime (__NR_Linux + 262)
+#define __NR_clock_gettime (__NR_Linux + 263)
+#define __NR_clock_getres (__NR_Linux + 264)
+#define __NR_clock_nanosleep (__NR_Linux + 265)
+#define __NR_tgkill (__NR_Linux + 266)
+#define __NR_utimes (__NR_Linux + 267)
+#define __NR_mbind (__NR_Linux + 268)
+#define __NR_get_mempolicy (__NR_Linux + 269)
+#define __NR_set_mempolicy (__NR_Linux + 270)
+#define __NR_mq_open (__NR_Linux + 271)
+#define __NR_mq_unlink (__NR_Linux + 272)
+#define __NR_mq_timedsend (__NR_Linux + 273)
+#define __NR_mq_timedreceive (__NR_Linux + 274)
+#define __NR_mq_notify (__NR_Linux + 275)
+#define __NR_mq_getsetattr (__NR_Linux + 276)
+#define __NR_vserver (__NR_Linux + 277)
+#define __NR_waitid (__NR_Linux + 278)
+/* #define __NR_sys_setaltroot (__NR_Linux + 279) */
+#define __NR_add_key (__NR_Linux + 280)
+#define __NR_request_key (__NR_Linux + 281)
+#define __NR_keyctl (__NR_Linux + 282)
+#define __NR_set_thread_area (__NR_Linux + 283)
+#define __NR_inotify_init (__NR_Linux + 284)
+#define __NR_inotify_add_watch (__NR_Linux + 285)
+#define __NR_inotify_rm_watch (__NR_Linux + 286)
+#define __NR_migrate_pages (__NR_Linux + 287)
+#define __NR_openat (__NR_Linux + 288)
+#define __NR_mkdirat (__NR_Linux + 289)
+#define __NR_mknodat (__NR_Linux + 290)
+#define __NR_fchownat (__NR_Linux + 291)
+#define __NR_futimesat (__NR_Linux + 292)
+#define __NR_fstatat64 (__NR_Linux + 293)
+#define __NR_unlinkat (__NR_Linux + 294)
+#define __NR_renameat (__NR_Linux + 295)
+#define __NR_linkat (__NR_Linux + 296)
+#define __NR_symlinkat (__NR_Linux + 297)
+#define __NR_readlinkat (__NR_Linux + 298)
+#define __NR_fchmodat (__NR_Linux + 299)
+#define __NR_faccessat (__NR_Linux + 300)
+#define __NR_pselect6 (__NR_Linux + 301)
+#define __NR_ppoll (__NR_Linux + 302)
+#define __NR_unshare (__NR_Linux + 303)
+#define __NR_splice (__NR_Linux + 304)
+#define __NR_sync_file_range (__NR_Linux + 305)
+#define __NR_tee (__NR_Linux + 306)
+#define __NR_vmsplice (__NR_Linux + 307)
+#define __NR_move_pages (__NR_Linux + 308)
+#define __NR_set_robust_list (__NR_Linux + 309)
+#define __NR_get_robust_list (__NR_Linux + 310)
+#define __NR_kexec_load (__NR_Linux + 311)
+#define __NR_getcpu (__NR_Linux + 312)
+#define __NR_epoll_pwait (__NR_Linux + 313)
+#define __NR_ioprio_set (__NR_Linux + 314)
+#define __NR_ioprio_get (__NR_Linux + 315)
+#define __NR_utimensat (__NR_Linux + 316)
+#define __NR_signalfd (__NR_Linux + 317)
+#define __NR_timerfd (__NR_Linux + 318)
+#define __NR_eventfd (__NR_Linux + 319)
+#define __NR_fallocate (__NR_Linux + 320)
+#define __NR_timerfd_create (__NR_Linux + 321)
+#define __NR_timerfd_gettime (__NR_Linux + 322)
+#define __NR_timerfd_settime (__NR_Linux + 323)
+#define __NR_signalfd4 (__NR_Linux + 324)
+#define __NR_eventfd2 (__NR_Linux + 325)
+#define __NR_epoll_create1 (__NR_Linux + 326)
+#define __NR_dup3 (__NR_Linux + 327)
+#define __NR_pipe2 (__NR_Linux + 328)
+#define __NR_inotify_init1 (__NR_Linux + 329)
+#define __NR_preadv (__NR_Linux + 330)
+#define __NR_pwritev (__NR_Linux + 331)
+#define __NR_rt_tgsigqueueinfo (__NR_Linux + 332)
+#define __NR_perf_event_open (__NR_Linux + 333)
+#define __NR_accept4 (__NR_Linux + 334)
+#define __NR_recvmmsg (__NR_Linux + 335)
+#define __NR_fanotify_init (__NR_Linux + 336)
+#define __NR_fanotify_mark (__NR_Linux + 337)
+#define __NR_prlimit64 (__NR_Linux + 338)
+#define __NR_name_to_handle_at (__NR_Linux + 339)
+#define __NR_open_by_handle_at (__NR_Linux + 340)
+#define __NR_clock_adjtime (__NR_Linux + 341)
+#define __NR_syncfs (__NR_Linux + 342)
+
+/*
+ * Offset of the last Linux o32 flavoured syscall
+ */
+#define __NR_Linux_syscalls 334
+
+
+#define __NR_O32_Linux 4000
+#define __NR_O32_Linux_syscalls 334
+
+
+#endif /* __VKI_SCNUMS_MIPS32_LINUX_H */
+
+/*--------------------------------------------------------------------*/
+/*--- end vki-scnums-mips32-linux.h ---*/
+/*--------------------------------------------------------------------*/
diff --git a/main/include/vki/vki-scnums-ppc32-linux.h b/main/include/vki/vki-scnums-ppc32-linux.h
index 3eb20ba..e865eb5 100644
--- a/main/include/vki/vki-scnums-ppc32-linux.h
+++ b/main/include/vki/vki-scnums-ppc32-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Julian Seward
+ Copyright (C) 2005-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -32,7 +32,7 @@
#ifndef __VKI_SCNUMS_PPC32_LINUX_H
#define __VKI_SCNUMS_PPC32_LINUX_H
-// From linux-2.6.9/include/asm-ppc/unistd.h
+// From linux-2.6/arc/powerpc/include/asm/unistd.h
#define __NR_restart_syscall 0
#define __NR_exit 1
@@ -393,6 +393,8 @@
#define __NR_syncfs 348
#define __NR_sendmmsg 349
#define __NR_setns 350
+#define __NR_process_vm_readv 351
+#define __NR_process_vm_writev 352
#endif /* __VKI_SCNUMS_PPC32_LINUX_H */
diff --git a/main/include/vki/vki-scnums-ppc64-linux.h b/main/include/vki/vki-scnums-ppc64-linux.h
index 75c5b82..f7030f2 100644
--- a/main/include/vki/vki-scnums-ppc64-linux.h
+++ b/main/include/vki/vki-scnums-ppc64-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2005-2011 Julian Seward
+ Copyright (C) 2005-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -32,7 +32,7 @@
#ifndef __VKI_SCNUMS_PPC64_LINUX_H
#define __VKI_SCNUMS_PPC64_LINUX_H
-// From linux-2.6.16-rc4/include/asm-powerpc/unistd.h
+// From linux-2.6/arc/powerpc/include/asm/unistd.h
#define __NR_restart_syscall 0
#define __NR_exit 1
@@ -385,6 +385,8 @@
#define __NR_syncfs 348
#define __NR_sendmmsg 349
#define __NR_setns 350
+#define __NR_process_vm_readv 351
+#define __NR_process_vm_writev 352
#endif /* __VKI_SCNUMS_PPC64_LINUX_H */
diff --git a/main/include/vki/vki-scnums-s390x-linux.h b/main/include/vki/vki-scnums-s390x-linux.h
index 348d36a..3ccb65d 100644
--- a/main/include/vki/vki-scnums-s390x-linux.h
+++ b/main/include/vki/vki-scnums-s390x-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright IBM Corp. 2010-2011
+ Copyright IBM Corp. 2010-2012
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
@@ -34,7 +34,7 @@
#define __VKI_SCNUMS_S390X_LINUX_H
//----------------------------------------------------------------------
-// From linux-2.6.39.2/include/asm-s390/unistd.h
+// From linux-2.6/arch/s390/include/asm/unistd.h
//----------------------------------------------------------------------
/*
@@ -304,7 +304,10 @@
#define __NR_open_by_handle_at 336
#define __NR_clock_adjtime 337
#define __NR_syncfs 338
-#define NR_syscalls 339
+#define __NR_setns 339
+#define __NR_process_vm_readv 340
+#define __NR_process_vm_writev 341
+#define NR_syscalls 342
/*
* There are some system calls that are not present on 64 bit, some
diff --git a/main/include/vki/vki-scnums-x86-linux.h b/main/include/vki/vki-scnums-x86-linux.h
index 9bdd86d..a1a3be6 100644
--- a/main/include/vki/vki-scnums-x86-linux.h
+++ b/main/include/vki/vki-scnums-x86-linux.h
@@ -8,7 +8,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -32,7 +32,7 @@
#ifndef __VKI_SCNUMS_X86_LINUX_H
#define __VKI_SCNUMS_X86_LINUX_H
-// From linux-2.6.9/include/asm-i386/unistd.h
+// Derived from linux-2.6/arch/x86/syscalls/syscall_32.tbl
#define __NR_restart_syscall 0
#define __NR_exit 1
@@ -381,6 +381,8 @@
#define __NR_syncfs 344
#define __NR_sendmmsg 345
#define __NR_setns 346
+#define __NR_process_vm_readv 347
+#define __NR_process_vm_writev 348
#endif /* __VKI_SCNUMS_X86_LINUX_H */
diff --git a/main/include/vki/vki-x86-linux.h b/main/include/vki/vki-x86-linux.h
index 2a14104..fbcdf8e 100644
--- a/main/include/vki/vki-x86-linux.h
+++ b/main/include/vki/vki-x86-linux.h
@@ -7,7 +7,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -308,6 +308,18 @@
#define VKI_F_SETLK64 13
#define VKI_F_SETLKW64 14
+#define VKI_F_SETOWN_EX 15
+#define VKI_F_GETOWN_EX 16
+
+#define VKI_F_OWNER_TID 0
+#define VKI_F_OWNER_PID 1
+#define VKI_F_OWNER_PGRP 2
+
+struct vki_f_owner_ex {
+ int type;
+ __vki_kernel_pid_t pid;
+};
+
/* for F_[GET|SET]FL */
#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */
diff --git a/main/massif/Makefile.am b/main/massif/Makefile.am
index 94bcd68..6c26780 100644
--- a/main/massif/Makefile.am
+++ b/main/massif/Makefile.am
@@ -1,7 +1,5 @@
include $(top_srcdir)/Makefile.tool.am
-SUBDIRS += perf
-
EXTRA_DIST = \
docs/ms-manual.xml \
docs/ms_print-manpage.xml
diff --git a/main/massif/Makefile.in b/main/massif/Makefile.in
new file mode 100644
index 0000000..3e0ae16
--- /dev/null
+++ b/main/massif/Makefile.in
@@ -0,0 +1,1202 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(srcdir)/ms_print.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+
+# On Android we must ask for non-executable stack, not sure why.
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_2 = -Wl,-z,noexecstack
+noinst_PROGRAMS = massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
+ $(am__EXEEXT_1) \
+ vgpreload_massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
+ $(am__EXEEXT_2)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_3 = massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = vgpreload_massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+subdir = massif
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES = ms_print
+CONFIG_CLEAN_VPATH_FILES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_2 = vgpreload_massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+PROGRAMS = $(noinst_PROGRAMS)
+am__objects_1 = \
+ massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.$(OBJEXT)
+am_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = \
+ $(am_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
+am__massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = ms_main.c
+am__objects_2 = \
+ massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_2)
+massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+ $(am_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
+am_vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS =
+vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = $(am_vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am_vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS =
+vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS = $(am_vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
+am__vpath_adj = case $$p in \
+ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
+ *) f=$$p;; \
+ esac;
+am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;
+am__install_max = 40
+am__nobase_strip_setup = \
+ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`
+am__nobase_strip = \
+ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"
+am__nobase_list = $(am__nobase_strip_setup); \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \
+ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \
+ if (++n[$$2] == $(am__install_max)) \
+ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \
+ END { for (dir in files) print dir, files[dir] }'
+am__base_list = \
+ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \
+ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'
+am__installdirs = "$(DESTDIR)$(bindir)"
+SCRIPTS = $(bin_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES) \
+ $(vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES) \
+ $(vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES)
+DIST_SOURCES = $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(am__massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST) \
+ $(vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES) \
+ $(vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES)
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DIST_SUBDIRS = $(SUBDIRS)
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+SUBDIRS = . tests
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+#----------------------------------------------------------------------------
+# <tool>-<platform> stuff
+#----------------------------------------------------------------------------
+TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+
+TOOL_LDADD_COMMON = -lgcc
+TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) $(TOOL_LDADD_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
+
+
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+ -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_X86_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_AMD64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_PPC32_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_PPC64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_ARM_LINUX = $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
+ $(am__append_2)
+TOOL_LDFLAGS_S390X_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_X86_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386
+
+TOOL_LDFLAGS_AMD64_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+
+
+# MIPS Linux default start symbol is __start, not _start like on x86 or amd
+TOOL_LDFLAGS_MIPS32_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
+ @FLAG_M32@
+
+
+# NB for 64-bit darwin. We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them). Although such setting is probably
+# better done in link_tool_exe.c.
+#
+# -Wl,-pagezero_size,0x100000000
+
+#----------------------------------------------------------------------------
+# vgpreload_<tool>-<platform>.a stuff
+#----------------------------------------------------------------------------
+LIBREPLACEMALLOC_X86_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-linux.a
+
+LIBREPLACEMALLOC_AMD64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-linux.a
+
+LIBREPLACEMALLOC_PPC32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a
+
+LIBREPLACEMALLOC_PPC64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a
+
+LIBREPLACEMALLOC_ARM_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a
+
+LIBREPLACEMALLOC_X86_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-darwin.a
+
+LIBREPLACEMALLOC_AMD64_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-darwin.a
+
+LIBREPLACEMALLOC_S390X_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-s390x-linux.a
+
+LIBREPLACEMALLOC_MIPS32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips32-linux.a
+
+LIBREPLACEMALLOC_LDFLAGS_X86_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_X86_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_AMD64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC32_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_ARM_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_X86_DARWIN = \
+ $(LIBREPLACEMALLOC_X86_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_DARWIN = \
+ $(LIBREPLACEMALLOC_AMD64_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_S390X_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_S390X_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_MIPS32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_MIPS32_LINUX) \
+ -Wl,--no-whole-archive
+
+EXTRA_DIST = \
+ docs/ms-manual.xml \
+ docs/ms_print-manpage.xml
+
+
+#----------------------------------------------------------------------------
+# Headers, etc
+#----------------------------------------------------------------------------
+bin_SCRIPTS = ms_print
+MASSIF_SOURCES_COMMON = ms_main.c
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+ $(MASSIF_SOURCES_COMMON)
+
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@)
+
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
+ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
+
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
+ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+ @VALT_LOAD_ADDRESS_PRI@ \
+ $(LINK) \
+ $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+ $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(MASSIF_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
+vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES =
+vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(AM_CFLAGS_PIC)
+
+vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \
+ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_PRI_CAPS@)
+
+vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
+ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
+ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) $(AM_CFLAGS_PIC)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign massif/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign massif/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+ms_print: $(top_builddir)/config.status $(srcdir)/ms_print.in
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+
+clean-noinstPROGRAMS:
+ -test -z "$(noinst_PROGRAMS)" || rm -f $(noinst_PROGRAMS)
+massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT): $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT)
+ $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD) $(LIBS)
+massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT): $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+ $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD) $(LIBS)
+vgpreload_massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK) $(vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD) $(LIBS)
+vgpreload_massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK) $(vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD) $(LIBS)
+install-binSCRIPTS: $(bin_SCRIPTS)
+ @$(NORMAL_INSTALL)
+ test -z "$(bindir)" || $(MKDIR_P) "$(DESTDIR)$(bindir)"
+ @list='$(bin_SCRIPTS)'; test -n "$(bindir)" || list=; \
+ for p in $$list; do \
+ if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+ if test -f "$$d$$p"; then echo "$$d$$p"; echo "$$p"; else :; fi; \
+ done | \
+ sed -e 'p;s,.*/,,;n' \
+ -e 'h;s|.*|.|' \
+ -e 'p;x;s,.*/,,;$(transform)' | sed 'N;N;N;s,\n, ,g' | \
+ $(AWK) 'BEGIN { files["."] = ""; dirs["."] = 1; } \
+ { d=$$3; if (dirs[d] != 1) { print "d", d; dirs[d] = 1 } \
+ if ($$2 == $$4) { files[d] = files[d] " " $$1; \
+ if (++n[d] == $(am__install_max)) { \
+ print "f", d, files[d]; n[d] = 0; files[d] = "" } } \
+ else { print "f", d "/" $$4, $$1 } } \
+ END { for (d in files) print "f", d, files[d] }' | \
+ while read type dir files; do \
+ if test "$$dir" = .; then dir=; else dir=/$$dir; fi; \
+ test -z "$$files" || { \
+ echo " $(INSTALL_SCRIPT) $$files '$(DESTDIR)$(bindir)$$dir'"; \
+ $(INSTALL_SCRIPT) $$files "$(DESTDIR)$(bindir)$$dir" || exit $$?; \
+ } \
+ ; done
+
+uninstall-binSCRIPTS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(bin_SCRIPTS)'; test -n "$(bindir)" || exit 0; \
+ files=`for p in $$list; do echo "$$p"; done | \
+ sed -e 's,.*/,,;$(transform)'`; \
+ test -n "$$list" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(bindir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(bindir)" && rm -f $$files
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.o: ms_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.o -MD -MP -MF $(DEPDIR)/massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.Tpo -c -o massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.o `test -f 'ms_main.c' || echo '$(srcdir)/'`ms_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.Tpo $(DEPDIR)/massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='ms_main.c' object='massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.o `test -f 'ms_main.c' || echo '$(srcdir)/'`ms_main.c
+
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.obj: ms_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.obj -MD -MP -MF $(DEPDIR)/massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.Tpo -c -o massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.obj `if test -f 'ms_main.c'; then $(CYGPATH_W) 'ms_main.c'; else $(CYGPATH_W) '$(srcdir)/ms_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.Tpo $(DEPDIR)/massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='ms_main.c' object='massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@-ms_main.obj `if test -f 'ms_main.c'; then $(CYGPATH_W) 'ms_main.c'; else $(CYGPATH_W) '$(srcdir)/ms_main.c'; fi`
+
+massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.o: ms_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.o -MD -MP -MF $(DEPDIR)/massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.Tpo -c -o massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.o `test -f 'ms_main.c' || echo '$(srcdir)/'`ms_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.Tpo $(DEPDIR)/massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='ms_main.c' object='massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.o `test -f 'ms_main.c' || echo '$(srcdir)/'`ms_main.c
+
+massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.obj: ms_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.obj -MD -MP -MF $(DEPDIR)/massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.Tpo -c -o massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.obj `if test -f 'ms_main.c'; then $(CYGPATH_W) 'ms_main.c'; else $(CYGPATH_W) '$(srcdir)/ms_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.Tpo $(DEPDIR)/massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='ms_main.c' object='massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.obj `if test -f 'ms_main.c'; then $(CYGPATH_W) 'ms_main.c'; else $(CYGPATH_W) '$(srcdir)/ms_main.c'; fi`
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+check: check-recursive
+all-am: Makefile $(PROGRAMS) $(SCRIPTS) all-local
+installdirs: installdirs-recursive
+installdirs-am:
+ for dir in "$(DESTDIR)$(bindir)"; do \
+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ done
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-generic clean-local clean-noinstPROGRAMS \
+ mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am: install-binSCRIPTS install-exec-local
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am: uninstall-binSCRIPTS
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+ install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am all-local check check-am clean clean-generic \
+ clean-local clean-noinstPROGRAMS ctags ctags-recursive \
+ distclean distclean-compile distclean-generic distclean-tags \
+ distdir dvi dvi-am html html-am info info-am install \
+ install-am install-binSCRIPTS install-data install-data-am \
+ install-dvi install-dvi-am install-exec install-exec-am \
+ install-exec-local install-html install-html-am install-info \
+ install-info-am install-man install-pdf install-pdf-am \
+ install-ps install-ps-am install-strip installcheck \
+ installcheck-am installdirs installdirs-am maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags tags-recursive \
+ uninstall uninstall-am uninstall-binSCRIPTS
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+#----------------------------------------------------------------------------
+# General stuff
+#----------------------------------------------------------------------------
+
+all-local: inplace-noinst_PROGRAMS inplace-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/massif/ms_main.c b/main/massif/ms_main.c
index d134ab1..4dc97b4 100644
--- a/main/massif/ms_main.c
+++ b/main/massif/ms_main.c
@@ -6,7 +6,7 @@
This file is part of Massif, a Valgrind tool for profiling memory
usage of programs.
- Copyright (C) 2003-2011 Nicholas Nethercote
+ Copyright (C) 2003-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -1884,8 +1884,15 @@
static
void ms_new_mem_brk ( Addr a, SizeT len, ThreadId tid )
{
- tl_assert(VG_IS_PAGE_ALIGNED(len));
- ms_record_page_mem(a, len);
+ // brk limit is not necessarily aligned on a page boundary.
+ // If new memory being brk-ed implies to allocate a new page,
+ // then call ms_record_page_mem with page aligned parameters
+ // otherwise just ignore.
+ Addr old_bottom_page = VG_PGROUNDDN(a - 1);
+ Addr new_top_page = VG_PGROUNDDN(a + len - 1);
+ if (old_bottom_page != new_top_page)
+ ms_record_page_mem(VG_PGROUNDDN(a),
+ (new_top_page - old_bottom_page));
}
static
@@ -1906,8 +1913,14 @@
static
void ms_die_mem_brk( Addr a, SizeT len )
{
- tl_assert(VG_IS_PAGE_ALIGNED(len));
- ms_unrecord_page_mem(a, len);
+ // Call ms_unrecord_page_mem only if one or more pages are de-allocated.
+ // See ms_new_mem_brk for more details.
+ Addr new_bottom_page = VG_PGROUNDDN(a - 1);
+ Addr old_top_page = VG_PGROUNDDN(a + len - 1);
+ if (old_top_page != new_bottom_page)
+ ms_unrecord_page_mem(VG_PGROUNDDN(a),
+ (old_top_page - new_bottom_page));
+
}
//------------------------------------------------------------//
@@ -2568,7 +2581,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a heap profiler");
VG_(details_copyright_author)(
- "Copyright (C) 2003-2011, and GNU GPL'd, by Nicholas Nethercote");
+ "Copyright (C) 2003-2012, and GNU GPL'd, by Nicholas Nethercote");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 330 );
diff --git a/main/massif/perf/Makefile.am b/main/massif/perf/Makefile.am
deleted file mode 100644
index 8e6fb42..0000000
--- a/main/massif/perf/Makefile.am
+++ /dev/null
@@ -1,12 +0,0 @@
-
-include $(top_srcdir)/Makefile.tool-tests.am
-
-EXTRA_DIST = \
- many-xpts.vgperf
-
-check_PROGRAMS = \
- many-xpts
-
-AM_CFLAGS += -O $(AM_FLAG_M3264_PRI)
-AM_CXXFLAGS += -O $(AM_FLAG_M3264_PRI)
-
diff --git a/main/massif/perf/many-xpts.c b/main/massif/perf/many-xpts.c
deleted file mode 100644
index e5e3e86..0000000
--- a/main/massif/perf/many-xpts.c
+++ /dev/null
@@ -1,52 +0,0 @@
-#include <stdlib.h>
-
-#define nth_bit(x, n) ((x >> n) & 1)
-#define Fn(N, Np1) \
- void* a##N(int x) { return ( nth_bit(x, N) ? a##Np1(x) : a##Np1(x) ); }
-
-// This test allocates a lot of heap memory, and every allocation features a
-// different stack trace -- the stack traces are effectively a
-// representation of the number 'i', where each function represents a bit in
-// 'i', and if it's a 1 the first function is called, and if it's a 0 the
-// second function is called.
-
-void* a999(int x)
-{
- return malloc(100);
-}
-
-Fn(17, 999)
-Fn(16, 17)
-Fn(15, 16)
-Fn(14, 15)
-Fn(13, 14)
-Fn(12, 13)
-Fn(11, 12)
-Fn(10, 11)
-Fn( 9, 10)
-Fn( 8, 9)
-Fn( 7, 8)
-Fn( 6, 7)
-Fn( 5, 6)
-Fn( 4, 5)
-Fn( 3, 4)
-Fn( 2, 3)
-Fn( 1, 2)
-Fn( 0, 1)
-
-int main(void)
-{
- int i;
-
- // Create a large XTree.
- for (i = 0; i < (1 << 18); i++)
- a0(i);
-
- // Do a lot of allocations so it gets dup'd a lot of times.
- for (i = 0; i < 100000; i++) {
- free(a1(234));
- free(a2(111));
- }
-
- return 0;
-}
diff --git a/main/massif/perf/many-xpts.vgperf b/main/massif/perf/many-xpts.vgperf
deleted file mode 100644
index d6ce056..0000000
--- a/main/massif/perf/many-xpts.vgperf
+++ /dev/null
@@ -1,2 +0,0 @@
-prog: many-xpts
-vgopts: --time-unit=B --depth=100
diff --git a/main/massif/tests/Makefile.am b/main/massif/tests/Makefile.am
index bfdb842..c6caf30 100644
--- a/main/massif/tests/Makefile.am
+++ b/main/massif/tests/Makefile.am
@@ -28,6 +28,7 @@
null.post.exp null.stderr.exp null.vgtest \
one.post.exp one.post.exp2 one.stderr.exp one.vgtest \
overloaded-new.post.exp overloaded-new.stderr.exp overloaded-new.vgtest \
+ pages_as_heap.stderr.exp pages_as_heap.vgtest \
peak.post.exp peak.stderr.exp peak.vgtest \
peak2.post.exp peak2.stderr.exp peak2.vgtest \
realloc.post.exp realloc.stderr.exp realloc.vgtest \
@@ -57,6 +58,7 @@
null \
one \
overloaded-new \
+ pages_as_heap \
peak \
realloc \
thresholds \
diff --git a/main/massif/tests/Makefile.in b/main/massif/tests/Makefile.in
new file mode 100644
index 0000000..e1d3640
--- /dev/null
+++ b/main/massif/tests/Makefile.in
@@ -0,0 +1,916 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = alloc-fns$(EXEEXT) basic$(EXEEXT) big-alloc$(EXEEXT) \
+ culling1$(EXEEXT) culling2$(EXEEXT) custom_alloc$(EXEEXT) \
+ deep$(EXEEXT) ignored$(EXEEXT) ignoring$(EXEEXT) \
+ insig$(EXEEXT) long-names$(EXEEXT) long-time$(EXEEXT) \
+ malloc_usable$(EXEEXT) new-cpp$(EXEEXT) null$(EXEEXT) \
+ one$(EXEEXT) overloaded-new$(EXEEXT) pages_as_heap$(EXEEXT) \
+ peak$(EXEEXT) realloc$(EXEEXT) thresholds$(EXEEXT) \
+ zero$(EXEEXT)
+subdir = massif/tests
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+alloc_fns_SOURCES = alloc-fns.c
+alloc_fns_OBJECTS = alloc-fns.$(OBJEXT)
+alloc_fns_LDADD = $(LDADD)
+basic_SOURCES = basic.c
+basic_OBJECTS = basic.$(OBJEXT)
+basic_LDADD = $(LDADD)
+big_alloc_SOURCES = big-alloc.c
+big_alloc_OBJECTS = big-alloc.$(OBJEXT)
+big_alloc_LDADD = $(LDADD)
+culling1_SOURCES = culling1.c
+culling1_OBJECTS = culling1.$(OBJEXT)
+culling1_LDADD = $(LDADD)
+culling2_SOURCES = culling2.c
+culling2_OBJECTS = culling2.$(OBJEXT)
+culling2_LDADD = $(LDADD)
+custom_alloc_SOURCES = custom_alloc.c
+custom_alloc_OBJECTS = custom_alloc.$(OBJEXT)
+custom_alloc_LDADD = $(LDADD)
+deep_SOURCES = deep.c
+deep_OBJECTS = deep.$(OBJEXT)
+deep_LDADD = $(LDADD)
+ignored_SOURCES = ignored.c
+ignored_OBJECTS = ignored.$(OBJEXT)
+ignored_LDADD = $(LDADD)
+ignoring_SOURCES = ignoring.c
+ignoring_OBJECTS = ignoring.$(OBJEXT)
+ignoring_LDADD = $(LDADD)
+insig_SOURCES = insig.c
+insig_OBJECTS = insig.$(OBJEXT)
+insig_LDADD = $(LDADD)
+long_names_SOURCES = long-names.c
+long_names_OBJECTS = long-names.$(OBJEXT)
+long_names_LDADD = $(LDADD)
+long_time_SOURCES = long-time.c
+long_time_OBJECTS = long-time.$(OBJEXT)
+long_time_LDADD = $(LDADD)
+malloc_usable_SOURCES = malloc_usable.c
+malloc_usable_OBJECTS = malloc_usable.$(OBJEXT)
+malloc_usable_LDADD = $(LDADD)
+am_new_cpp_OBJECTS = new-cpp.$(OBJEXT)
+new_cpp_OBJECTS = $(am_new_cpp_OBJECTS)
+new_cpp_LDADD = $(LDADD)
+null_SOURCES = null.c
+null_OBJECTS = null.$(OBJEXT)
+null_LDADD = $(LDADD)
+one_SOURCES = one.c
+one_OBJECTS = one.$(OBJEXT)
+one_LDADD = $(LDADD)
+am_overloaded_new_OBJECTS = overloaded-new.$(OBJEXT)
+overloaded_new_OBJECTS = $(am_overloaded_new_OBJECTS)
+overloaded_new_LDADD = $(LDADD)
+pages_as_heap_SOURCES = pages_as_heap.c
+pages_as_heap_OBJECTS = pages_as_heap.$(OBJEXT)
+pages_as_heap_LDADD = $(LDADD)
+peak_SOURCES = peak.c
+peak_OBJECTS = peak.$(OBJEXT)
+peak_LDADD = $(LDADD)
+realloc_SOURCES = realloc.c
+realloc_OBJECTS = realloc.$(OBJEXT)
+realloc_LDADD = $(LDADD)
+thresholds_SOURCES = thresholds.c
+thresholds_OBJECTS = thresholds.$(OBJEXT)
+thresholds_LDADD = $(LDADD)
+zero_SOURCES = zero.c
+zero_OBJECTS = zero.$(OBJEXT)
+zero_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+CXXCOMPILE = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS)
+CXXLD = $(CXX)
+CXXLINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+SOURCES = alloc-fns.c basic.c big-alloc.c culling1.c culling2.c \
+ custom_alloc.c deep.c ignored.c ignoring.c insig.c \
+ long-names.c long-time.c malloc_usable.c $(new_cpp_SOURCES) \
+ null.c one.c $(overloaded_new_SOURCES) pages_as_heap.c peak.c \
+ realloc.c thresholds.c zero.c
+DIST_SOURCES = alloc-fns.c basic.c big-alloc.c culling1.c culling2.c \
+ custom_alloc.c deep.c ignored.c ignoring.c insig.c \
+ long-names.c long-time.c malloc_usable.c $(new_cpp_SOURCES) \
+ null.c one.c $(overloaded_new_SOURCES) pages_as_heap.c peak.c \
+ realloc.c thresholds.c zero.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr filter_verbose
+EXTRA_DIST = \
+ alloc-fns-A.post.exp alloc-fns-A.stderr.exp alloc-fns-A.vgtest \
+ alloc-fns-B.post.exp alloc-fns-B.stderr.exp alloc-fns-B.vgtest \
+ basic.post.exp basic.stderr.exp basic.vgtest \
+ basic2.post.exp basic2.stderr.exp basic2.vgtest \
+ big-alloc.post.exp big-alloc.post.exp-64bit \
+ big-alloc.stderr.exp big-alloc.vgtest \
+ deep-A.post.exp deep-A.stderr.exp deep-A.vgtest \
+ deep-B.post.exp deep-B.stderr.exp deep-B.vgtest \
+ deep-C.post.exp deep-C.stderr.exp deep-C.vgtest \
+ deep-D.post.exp deep-D.stderr.exp deep-D.vgtest \
+ culling1.stderr.exp culling1.vgtest \
+ culling2.stderr.exp culling2.vgtest \
+ custom_alloc.post.exp custom_alloc.stderr.exp custom_alloc.vgtest \
+ ignored.post.exp ignored.stderr.exp ignored.vgtest \
+ ignoring.post.exp ignoring.stderr.exp ignoring.vgtest \
+ insig.post.exp insig.stderr.exp insig.vgtest \
+ long-names.post.exp long-names.stderr.exp long-names.vgtest \
+ long-time.post.exp long-time.stderr.exp long-time.vgtest \
+ malloc_usable.stderr.exp malloc_usable.vgtest \
+ new-cpp.post.exp new-cpp.stderr.exp new-cpp.vgtest \
+ no-stack-no-heap.post.exp no-stack-no-heap.stderr.exp no-stack-no-heap.vgtest \
+ null.post.exp null.stderr.exp null.vgtest \
+ one.post.exp one.post.exp2 one.stderr.exp one.vgtest \
+ overloaded-new.post.exp overloaded-new.stderr.exp overloaded-new.vgtest \
+ pages_as_heap.stderr.exp pages_as_heap.vgtest \
+ peak.post.exp peak.stderr.exp peak.vgtest \
+ peak2.post.exp peak2.stderr.exp peak2.vgtest \
+ realloc.post.exp realloc.stderr.exp realloc.vgtest \
+ thresholds_0_0.post.exp thresholds_0_0.stderr.exp thresholds_0_0.vgtest \
+ thresholds_0_10.post.exp thresholds_0_10.stderr.exp thresholds_0_10.vgtest \
+ thresholds_10_0.post.exp thresholds_10_0.stderr.exp thresholds_10_0.vgtest \
+ thresholds_5_0.post.exp thresholds_5_0.stderr.exp thresholds_5_0.vgtest \
+ thresholds_5_10.post.exp thresholds_5_10.stderr.exp thresholds_5_10.vgtest \
+ thresholds_10_10.post.exp thresholds_10_10.stderr.exp thresholds_10_10.vgtest \
+ zero1.post.exp zero1.stderr.exp zero1.vgtest \
+ zero2.post.exp zero2.stderr.exp zero2.vgtest
+
+
+# C++ tests
+new_cpp_SOURCES = new-cpp.cpp
+overloaded_new_SOURCES = overloaded-new.cpp
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .cpp .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign massif/tests/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign massif/tests/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+alloc-fns$(EXEEXT): $(alloc_fns_OBJECTS) $(alloc_fns_DEPENDENCIES)
+ @rm -f alloc-fns$(EXEEXT)
+ $(LINK) $(alloc_fns_OBJECTS) $(alloc_fns_LDADD) $(LIBS)
+basic$(EXEEXT): $(basic_OBJECTS) $(basic_DEPENDENCIES)
+ @rm -f basic$(EXEEXT)
+ $(LINK) $(basic_OBJECTS) $(basic_LDADD) $(LIBS)
+big-alloc$(EXEEXT): $(big_alloc_OBJECTS) $(big_alloc_DEPENDENCIES)
+ @rm -f big-alloc$(EXEEXT)
+ $(LINK) $(big_alloc_OBJECTS) $(big_alloc_LDADD) $(LIBS)
+culling1$(EXEEXT): $(culling1_OBJECTS) $(culling1_DEPENDENCIES)
+ @rm -f culling1$(EXEEXT)
+ $(LINK) $(culling1_OBJECTS) $(culling1_LDADD) $(LIBS)
+culling2$(EXEEXT): $(culling2_OBJECTS) $(culling2_DEPENDENCIES)
+ @rm -f culling2$(EXEEXT)
+ $(LINK) $(culling2_OBJECTS) $(culling2_LDADD) $(LIBS)
+custom_alloc$(EXEEXT): $(custom_alloc_OBJECTS) $(custom_alloc_DEPENDENCIES)
+ @rm -f custom_alloc$(EXEEXT)
+ $(LINK) $(custom_alloc_OBJECTS) $(custom_alloc_LDADD) $(LIBS)
+deep$(EXEEXT): $(deep_OBJECTS) $(deep_DEPENDENCIES)
+ @rm -f deep$(EXEEXT)
+ $(LINK) $(deep_OBJECTS) $(deep_LDADD) $(LIBS)
+ignored$(EXEEXT): $(ignored_OBJECTS) $(ignored_DEPENDENCIES)
+ @rm -f ignored$(EXEEXT)
+ $(LINK) $(ignored_OBJECTS) $(ignored_LDADD) $(LIBS)
+ignoring$(EXEEXT): $(ignoring_OBJECTS) $(ignoring_DEPENDENCIES)
+ @rm -f ignoring$(EXEEXT)
+ $(LINK) $(ignoring_OBJECTS) $(ignoring_LDADD) $(LIBS)
+insig$(EXEEXT): $(insig_OBJECTS) $(insig_DEPENDENCIES)
+ @rm -f insig$(EXEEXT)
+ $(LINK) $(insig_OBJECTS) $(insig_LDADD) $(LIBS)
+long-names$(EXEEXT): $(long_names_OBJECTS) $(long_names_DEPENDENCIES)
+ @rm -f long-names$(EXEEXT)
+ $(LINK) $(long_names_OBJECTS) $(long_names_LDADD) $(LIBS)
+long-time$(EXEEXT): $(long_time_OBJECTS) $(long_time_DEPENDENCIES)
+ @rm -f long-time$(EXEEXT)
+ $(LINK) $(long_time_OBJECTS) $(long_time_LDADD) $(LIBS)
+malloc_usable$(EXEEXT): $(malloc_usable_OBJECTS) $(malloc_usable_DEPENDENCIES)
+ @rm -f malloc_usable$(EXEEXT)
+ $(LINK) $(malloc_usable_OBJECTS) $(malloc_usable_LDADD) $(LIBS)
+new-cpp$(EXEEXT): $(new_cpp_OBJECTS) $(new_cpp_DEPENDENCIES)
+ @rm -f new-cpp$(EXEEXT)
+ $(CXXLINK) $(new_cpp_OBJECTS) $(new_cpp_LDADD) $(LIBS)
+null$(EXEEXT): $(null_OBJECTS) $(null_DEPENDENCIES)
+ @rm -f null$(EXEEXT)
+ $(LINK) $(null_OBJECTS) $(null_LDADD) $(LIBS)
+one$(EXEEXT): $(one_OBJECTS) $(one_DEPENDENCIES)
+ @rm -f one$(EXEEXT)
+ $(LINK) $(one_OBJECTS) $(one_LDADD) $(LIBS)
+overloaded-new$(EXEEXT): $(overloaded_new_OBJECTS) $(overloaded_new_DEPENDENCIES)
+ @rm -f overloaded-new$(EXEEXT)
+ $(CXXLINK) $(overloaded_new_OBJECTS) $(overloaded_new_LDADD) $(LIBS)
+pages_as_heap$(EXEEXT): $(pages_as_heap_OBJECTS) $(pages_as_heap_DEPENDENCIES)
+ @rm -f pages_as_heap$(EXEEXT)
+ $(LINK) $(pages_as_heap_OBJECTS) $(pages_as_heap_LDADD) $(LIBS)
+peak$(EXEEXT): $(peak_OBJECTS) $(peak_DEPENDENCIES)
+ @rm -f peak$(EXEEXT)
+ $(LINK) $(peak_OBJECTS) $(peak_LDADD) $(LIBS)
+realloc$(EXEEXT): $(realloc_OBJECTS) $(realloc_DEPENDENCIES)
+ @rm -f realloc$(EXEEXT)
+ $(LINK) $(realloc_OBJECTS) $(realloc_LDADD) $(LIBS)
+thresholds$(EXEEXT): $(thresholds_OBJECTS) $(thresholds_DEPENDENCIES)
+ @rm -f thresholds$(EXEEXT)
+ $(LINK) $(thresholds_OBJECTS) $(thresholds_LDADD) $(LIBS)
+zero$(EXEEXT): $(zero_OBJECTS) $(zero_DEPENDENCIES)
+ @rm -f zero$(EXEEXT)
+ $(LINK) $(zero_OBJECTS) $(zero_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/alloc-fns.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/basic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/big-alloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/culling1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/culling2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/custom_alloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/deep.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ignored.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ignoring.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insig.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/long-names.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/long-time.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/malloc_usable.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/new-cpp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/null.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/one.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/overloaded-new.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pages_as_heap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/peak.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/realloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/thresholds.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/zero.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+.cpp.o:
+@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ $<
+
+.cpp.obj:
+@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/massif/tests/big-alloc.post.exp-64bit b/main/massif/tests/big-alloc.post.exp-64bit
new file mode 100644
index 0000000..8ba7e8e
--- /dev/null
+++ b/main/massif/tests/big-alloc.post.exp-64bit
@@ -0,0 +1,54 @@
+--------------------------------------------------------------------------------
+Command: ./big-alloc
+Massif arguments: --stacks=no --time-unit=B --massif-out-file=massif.out --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook --ignore-fn=get_or_create_key_element
+ms_print arguments: massif.out
+--------------------------------------------------------------------------------
+
+
+ MB
+100.0^ :
+ | :
+ | @@@@@@@:
+ | @ :
+ | :::::::@ :
+ | : @ :
+ | :::::::: @ :
+ | : : @ :
+ | :::::::: : @ :
+ | : : : @ :
+ | :::::::: : : @ :
+ | : : : : @ :
+ | ::::::::: : : : @ :
+ | : : : : : @ :
+ | :::::::: : : : : @ :
+ | : : : : : : @ :
+ | :::::::: : : : : : @ :
+ | : : : : : : : @ :
+ | :::::::: : : : : : : @ :
+ | : : : : : : : : @ :
+ 0 +----------------------------------------------------------------------->MB
+ 0 100.0
+
+Number of snapshots: 11
+ Detailed snapshots: [9]
+
+--------------------------------------------------------------------------------
+ n time(B) total(B) useful-heap(B) extra-heap(B) stacks(B)
+--------------------------------------------------------------------------------
+ 0 0 0 0 0 0
+ 1 10,489,800 10,489,800 10,485,760 4,040 0
+ 2 20,979,600 20,979,600 20,971,520 8,080 0
+ 3 31,469,400 31,469,400 31,457,280 12,120 0
+ 4 41,959,200 41,959,200 41,943,040 16,160 0
+ 5 52,449,000 52,449,000 52,428,800 20,200 0
+ 6 62,938,800 62,938,800 62,914,560 24,240 0
+ 7 73,428,600 73,428,600 73,400,320 28,280 0
+ 8 83,918,400 83,918,400 83,886,080 32,320 0
+ 9 94,408,200 94,408,200 94,371,840 36,360 0
+99.96% (94,371,840B) (heap allocation functions) malloc/new/new[], --alloc-fns, etc.
+->99.96% (94,371,840B) 0x........: main (big-alloc.c:12)
+
+--------------------------------------------------------------------------------
+ n time(B) total(B) useful-heap(B) extra-heap(B) stacks(B)
+--------------------------------------------------------------------------------
+ 10 104,898,000 104,898,000 104,857,600 40,400 0
diff --git a/main/massif/tests/pages_as_heap.c b/main/massif/tests/pages_as_heap.c
new file mode 100644
index 0000000..04d5ecc
--- /dev/null
+++ b/main/massif/tests/pages_as_heap.c
@@ -0,0 +1,32 @@
+#include <stdio.h>
+#include <unistd.h>
+
+#define MAX 20000
+
+int main () {
+ int i;
+ int inc_dec;
+ int delta;
+ int brk_stat;
+
+ // loop to first increase, then decrease
+ for (inc_dec = 1; inc_dec >= -1; inc_dec-=2) {
+ // loop to increase(decrease) with small then big delta
+ for (delta = 1; delta <= 400; delta+=399) {
+ if (0) printf("initial brk value for inc_dec %d delta %d: %p\n",
+ inc_dec, delta, sbrk(0));
+ for (i=0; i<MAX; i++) {
+ brk_stat = brk(sbrk(0) + inc_dec * delta);
+ if (brk_stat == -1) {
+ printf("brk value at failure: %p\n", sbrk(0));
+ perror ("brk() failed!\n");
+ return 0;
+ }
+ }
+ if (0) printf("resulting brk value for inc_dec %d delta %d: %p\n",
+ inc_dec, delta, sbrk(0));
+ }
+ }
+
+ return 0;
+}
diff --git a/main/massif/tests/pages_as_heap.stderr.exp b/main/massif/tests/pages_as_heap.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/massif/tests/pages_as_heap.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/massif/tests/pages_as_heap.vgtest b/main/massif/tests/pages_as_heap.vgtest
new file mode 100644
index 0000000..7834460
--- /dev/null
+++ b/main/massif/tests/pages_as_heap.vgtest
@@ -0,0 +1,6 @@
+prog: pages_as_heap
+vgopts: --stacks=no --time-unit=B --heap-admin=0 --pages-as-heap=yes --massif-out-file=massif.out --detailed-freq=3
+vgopts: --ignore-fn=mmap
+# would be nice to test that pages as heap works properly using
+# post: perl ../../massif/ms_print massif.out | ../../tests/filter_addresses
+cleanup: rm massif.out
diff --git a/main/memcheck/Makefile.am b/main/memcheck/Makefile.am
index 5f8fd2e..172fe41 100644
--- a/main/memcheck/Makefile.am
+++ b/main/memcheck/Makefile.am
@@ -1,7 +1,5 @@
include $(top_srcdir)/Makefile.tool.am
-SUBDIRS += perf
-
EXTRA_DIST = docs/mc-manual.xml docs/mc-tech-docs.xml
#----------------------------------------------------------------------------
@@ -71,6 +69,9 @@
$(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
endif
+# mc_main.c contains the helper function for memcheck that get called
+# all the time. To maximise performance compile with -fomit-frame-pointer
+# Primary beneficiary is x86.
mc_main.o: CFLAGS += -fomit-frame-pointer
#----------------------------------------------------------------------------
@@ -114,5 +115,10 @@
$(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
endif
+# mc_replace_strmem.c runs on the simulated CPU, and it often appears
+# in stack traces shown to the user. It is built with
+# -fno-omit-frame-pointer so as to guarantee robust backtraces on x86,
+# on which CFI based unwinding is not the "normal" case and so is
+# sometimes fragile.
mc_replace_strmem.o: CFLAGS += -fno-omit-frame-pointer
diff --git a/main/memcheck/Makefile.in b/main/memcheck/Makefile.in
new file mode 100644
index 0000000..ea3214c
--- /dev/null
+++ b/main/memcheck/Makefile.in
@@ -0,0 +1,1411 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
+ $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+
+# On Android we must ask for non-executable stack, not sure why.
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_2 = -Wl,-z,noexecstack
+noinst_PROGRAMS = memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
+ $(am__EXEEXT_1) \
+ vgpreload_memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
+ $(am__EXEEXT_2)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_3 = memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = vgpreload_memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+subdir = memcheck
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_2 = vgpreload_memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+PROGRAMS = $(noinst_PROGRAMS)
+am__objects_1 = \
+ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.$(OBJEXT)
+am_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = \
+ $(am_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
+am__memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = \
+ mc_leakcheck.c mc_malloc_wrappers.c mc_main.c mc_translate.c \
+ mc_machine.c mc_errors.c
+am__objects_2 = \
+ memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.$(OBJEXT) \
+ memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_2)
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+ $(am_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
+am__objects_3 = vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.$(OBJEXT)
+am_vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = \
+ $(am__objects_3)
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = $(am_vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am__vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES_DIST = \
+ mc_replace_strmem.c
+am__objects_4 = vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_4)
+vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS = $(am_vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS)
+vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD = $(LDADD)
+vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK = $(CCLD) \
+ $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) \
+ $(CFLAGS) \
+ $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES) \
+ $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES) \
+ $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES)
+DIST_SOURCES = $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(am__memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST) \
+ $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES) \
+ $(am__vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES_DIST)
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
+am__vpath_adj = case $$p in \
+ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
+ *) f=$$p;; \
+ esac;
+am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`;
+am__install_max = 40
+am__nobase_strip_setup = \
+ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`
+am__nobase_strip = \
+ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||"
+am__nobase_list = $(am__nobase_strip_setup); \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \
+ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \
+ if (++n[$$2] == $(am__install_max)) \
+ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \
+ END { for (dir in files) print dir, files[dir] }'
+am__base_list = \
+ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \
+ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g'
+am__installdirs = "$(DESTDIR)$(pkgincludedir)"
+HEADERS = $(noinst_HEADERS) $(pkginclude_HEADERS)
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DIST_SUBDIRS = $(SUBDIRS)
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+SUBDIRS = . tests
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+#----------------------------------------------------------------------------
+# <tool>-<platform> stuff
+#----------------------------------------------------------------------------
+TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+
+TOOL_LDADD_COMMON = -lgcc
+TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) $(TOOL_LDADD_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
+
+
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+ -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_X86_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_AMD64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_PPC32_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_PPC64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_ARM_LINUX = $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
+ $(am__append_2)
+TOOL_LDFLAGS_S390X_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_X86_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386
+
+TOOL_LDFLAGS_AMD64_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+
+
+# MIPS Linux default start symbol is __start, not _start like on x86 or amd
+TOOL_LDFLAGS_MIPS32_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
+ @FLAG_M32@
+
+
+# NB for 64-bit darwin. We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them). Although such setting is probably
+# better done in link_tool_exe.c.
+#
+# -Wl,-pagezero_size,0x100000000
+
+#----------------------------------------------------------------------------
+# vgpreload_<tool>-<platform>.a stuff
+#----------------------------------------------------------------------------
+LIBREPLACEMALLOC_X86_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-linux.a
+
+LIBREPLACEMALLOC_AMD64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-linux.a
+
+LIBREPLACEMALLOC_PPC32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a
+
+LIBREPLACEMALLOC_PPC64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a
+
+LIBREPLACEMALLOC_ARM_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a
+
+LIBREPLACEMALLOC_X86_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-darwin.a
+
+LIBREPLACEMALLOC_AMD64_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-darwin.a
+
+LIBREPLACEMALLOC_S390X_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-s390x-linux.a
+
+LIBREPLACEMALLOC_MIPS32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips32-linux.a
+
+LIBREPLACEMALLOC_LDFLAGS_X86_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_X86_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_AMD64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC32_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_ARM_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_X86_DARWIN = \
+ $(LIBREPLACEMALLOC_X86_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_DARWIN = \
+ $(LIBREPLACEMALLOC_AMD64_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_S390X_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_S390X_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_MIPS32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_MIPS32_LINUX) \
+ -Wl,--no-whole-archive
+
+EXTRA_DIST = docs/mc-manual.xml docs/mc-tech-docs.xml
+
+#----------------------------------------------------------------------------
+# Headers
+#----------------------------------------------------------------------------
+pkginclude_HEADERS = \
+ memcheck.h
+
+noinst_HEADERS = \
+ mc_include.h
+
+MEMCHECK_SOURCES_COMMON = \
+ mc_leakcheck.c \
+ mc_malloc_wrappers.c \
+ mc_main.c \
+ mc_translate.c \
+ mc_machine.c \
+ mc_errors.c
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+ $(MEMCHECK_SOURCES_COMMON)
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) -O2
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@)
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
+ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
+ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+ @VALT_LOAD_ADDRESS_PRI@ \
+ $(LINK) \
+ $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+ $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(MEMCHECK_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) -O2
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
+VGPRELOAD_MEMCHECK_SOURCES_COMMON = mc_replace_strmem.c
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \
+ $(VGPRELOAD_MEMCHECK_SOURCES_COMMON)
+
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) $(AM_CFLAGS_PIC) -O2
+
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \
+ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_PRI_CAPS@)
+
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
+ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
+ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(VGPRELOAD_MEMCHECK_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) $(AM_CFLAGS_PIC) -O2
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-noinstPROGRAMS:
+ -test -z "$(noinst_PROGRAMS)" || rm -f $(noinst_PROGRAMS)
+memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT): $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT)
+ $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD) $(LIBS)
+memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT): $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+ $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD) $(LIBS)
+vgpreload_memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LINK) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD) $(LIBS)
+vgpreload_memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT): $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES)
+ @rm -f vgpreload_memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so$(EXEEXT)
+ $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LINK) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_OBJECTS) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.o: mc_leakcheck.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.o `test -f 'mc_leakcheck.c' || echo '$(srcdir)/'`mc_leakcheck.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_leakcheck.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.o `test -f 'mc_leakcheck.c' || echo '$(srcdir)/'`mc_leakcheck.c
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.obj: mc_leakcheck.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.obj `if test -f 'mc_leakcheck.c'; then $(CYGPATH_W) 'mc_leakcheck.c'; else $(CYGPATH_W) '$(srcdir)/mc_leakcheck.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_leakcheck.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_leakcheck.obj `if test -f 'mc_leakcheck.c'; then $(CYGPATH_W) 'mc_leakcheck.c'; else $(CYGPATH_W) '$(srcdir)/mc_leakcheck.c'; fi`
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.o: mc_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.o `test -f 'mc_malloc_wrappers.c' || echo '$(srcdir)/'`mc_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_malloc_wrappers.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.o `test -f 'mc_malloc_wrappers.c' || echo '$(srcdir)/'`mc_malloc_wrappers.c
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.obj: mc_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.obj `if test -f 'mc_malloc_wrappers.c'; then $(CYGPATH_W) 'mc_malloc_wrappers.c'; else $(CYGPATH_W) '$(srcdir)/mc_malloc_wrappers.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_malloc_wrappers.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_malloc_wrappers.obj `if test -f 'mc_malloc_wrappers.c'; then $(CYGPATH_W) 'mc_malloc_wrappers.c'; else $(CYGPATH_W) '$(srcdir)/mc_malloc_wrappers.c'; fi`
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.o: mc_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.o `test -f 'mc_main.c' || echo '$(srcdir)/'`mc_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_main.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.o `test -f 'mc_main.c' || echo '$(srcdir)/'`mc_main.c
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.obj: mc_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.obj `if test -f 'mc_main.c'; then $(CYGPATH_W) 'mc_main.c'; else $(CYGPATH_W) '$(srcdir)/mc_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_main.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_main.obj `if test -f 'mc_main.c'; then $(CYGPATH_W) 'mc_main.c'; else $(CYGPATH_W) '$(srcdir)/mc_main.c'; fi`
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.o: mc_translate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.o `test -f 'mc_translate.c' || echo '$(srcdir)/'`mc_translate.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_translate.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.o `test -f 'mc_translate.c' || echo '$(srcdir)/'`mc_translate.c
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.obj: mc_translate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.obj `if test -f 'mc_translate.c'; then $(CYGPATH_W) 'mc_translate.c'; else $(CYGPATH_W) '$(srcdir)/mc_translate.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_translate.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_translate.obj `if test -f 'mc_translate.c'; then $(CYGPATH_W) 'mc_translate.c'; else $(CYGPATH_W) '$(srcdir)/mc_translate.c'; fi`
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.o: mc_machine.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.o `test -f 'mc_machine.c' || echo '$(srcdir)/'`mc_machine.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_machine.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.o `test -f 'mc_machine.c' || echo '$(srcdir)/'`mc_machine.c
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.obj: mc_machine.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.obj `if test -f 'mc_machine.c'; then $(CYGPATH_W) 'mc_machine.c'; else $(CYGPATH_W) '$(srcdir)/mc_machine.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_machine.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_machine.obj `if test -f 'mc_machine.c'; then $(CYGPATH_W) 'mc_machine.c'; else $(CYGPATH_W) '$(srcdir)/mc_machine.c'; fi`
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.o: mc_errors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.o `test -f 'mc_errors.c' || echo '$(srcdir)/'`mc_errors.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_errors.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.o `test -f 'mc_errors.c' || echo '$(srcdir)/'`mc_errors.c
+
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.obj: mc_errors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.Tpo -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.obj `if test -f 'mc_errors.c'; then $(CYGPATH_W) 'mc_errors.c'; else $(CYGPATH_W) '$(srcdir)/mc_errors.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_errors.c' object='memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@-mc_errors.obj `if test -f 'mc_errors.c'; then $(CYGPATH_W) 'mc_errors.c'; else $(CYGPATH_W) '$(srcdir)/mc_errors.c'; fi`
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.o: mc_leakcheck.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.o `test -f 'mc_leakcheck.c' || echo '$(srcdir)/'`mc_leakcheck.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_leakcheck.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.o `test -f 'mc_leakcheck.c' || echo '$(srcdir)/'`mc_leakcheck.c
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.obj: mc_leakcheck.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.obj `if test -f 'mc_leakcheck.c'; then $(CYGPATH_W) 'mc_leakcheck.c'; else $(CYGPATH_W) '$(srcdir)/mc_leakcheck.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_leakcheck.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_leakcheck.obj `if test -f 'mc_leakcheck.c'; then $(CYGPATH_W) 'mc_leakcheck.c'; else $(CYGPATH_W) '$(srcdir)/mc_leakcheck.c'; fi`
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.o: mc_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.o `test -f 'mc_malloc_wrappers.c' || echo '$(srcdir)/'`mc_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_malloc_wrappers.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.o `test -f 'mc_malloc_wrappers.c' || echo '$(srcdir)/'`mc_malloc_wrappers.c
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.obj: mc_malloc_wrappers.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.obj `if test -f 'mc_malloc_wrappers.c'; then $(CYGPATH_W) 'mc_malloc_wrappers.c'; else $(CYGPATH_W) '$(srcdir)/mc_malloc_wrappers.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_malloc_wrappers.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_malloc_wrappers.obj `if test -f 'mc_malloc_wrappers.c'; then $(CYGPATH_W) 'mc_malloc_wrappers.c'; else $(CYGPATH_W) '$(srcdir)/mc_malloc_wrappers.c'; fi`
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.o: mc_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.o `test -f 'mc_main.c' || echo '$(srcdir)/'`mc_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_main.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.o `test -f 'mc_main.c' || echo '$(srcdir)/'`mc_main.c
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.obj: mc_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.obj `if test -f 'mc_main.c'; then $(CYGPATH_W) 'mc_main.c'; else $(CYGPATH_W) '$(srcdir)/mc_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_main.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_main.obj `if test -f 'mc_main.c'; then $(CYGPATH_W) 'mc_main.c'; else $(CYGPATH_W) '$(srcdir)/mc_main.c'; fi`
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.o: mc_translate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.o `test -f 'mc_translate.c' || echo '$(srcdir)/'`mc_translate.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_translate.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.o `test -f 'mc_translate.c' || echo '$(srcdir)/'`mc_translate.c
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.obj: mc_translate.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.obj `if test -f 'mc_translate.c'; then $(CYGPATH_W) 'mc_translate.c'; else $(CYGPATH_W) '$(srcdir)/mc_translate.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_translate.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_translate.obj `if test -f 'mc_translate.c'; then $(CYGPATH_W) 'mc_translate.c'; else $(CYGPATH_W) '$(srcdir)/mc_translate.c'; fi`
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.o: mc_machine.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.o `test -f 'mc_machine.c' || echo '$(srcdir)/'`mc_machine.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_machine.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.o `test -f 'mc_machine.c' || echo '$(srcdir)/'`mc_machine.c
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.obj: mc_machine.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.obj `if test -f 'mc_machine.c'; then $(CYGPATH_W) 'mc_machine.c'; else $(CYGPATH_W) '$(srcdir)/mc_machine.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_machine.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_machine.obj `if test -f 'mc_machine.c'; then $(CYGPATH_W) 'mc_machine.c'; else $(CYGPATH_W) '$(srcdir)/mc_machine.c'; fi`
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.o: mc_errors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.o -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.o `test -f 'mc_errors.c' || echo '$(srcdir)/'`mc_errors.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_errors.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.o `test -f 'mc_errors.c' || echo '$(srcdir)/'`mc_errors.c
+
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.obj: mc_errors.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.obj -MD -MP -MF $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.Tpo -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.obj `if test -f 'mc_errors.c'; then $(CYGPATH_W) 'mc_errors.c'; else $(CYGPATH_W) '$(srcdir)/mc_errors.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.Tpo $(DEPDIR)/memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_errors.c' object='memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@-mc_errors.obj `if test -f 'mc_errors.c'; then $(CYGPATH_W) 'mc_errors.c'; else $(CYGPATH_W) '$(srcdir)/mc_errors.c'; fi`
+
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.o: mc_replace_strmem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.o -MD -MP -MF $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.Tpo -c -o vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.o `test -f 'mc_replace_strmem.c' || echo '$(srcdir)/'`mc_replace_strmem.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.Tpo $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_replace_strmem.c' object='vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.o `test -f 'mc_replace_strmem.c' || echo '$(srcdir)/'`mc_replace_strmem.c
+
+vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.obj: mc_replace_strmem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.obj -MD -MP -MF $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.Tpo -c -o vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.obj `if test -f 'mc_replace_strmem.c'; then $(CYGPATH_W) 'mc_replace_strmem.c'; else $(CYGPATH_W) '$(srcdir)/mc_replace_strmem.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.Tpo $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_replace_strmem.c' object='vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.obj `if test -f 'mc_replace_strmem.c'; then $(CYGPATH_W) 'mc_replace_strmem.c'; else $(CYGPATH_W) '$(srcdir)/mc_replace_strmem.c'; fi`
+
+vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.o: mc_replace_strmem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.o -MD -MP -MF $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.Tpo -c -o vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.o `test -f 'mc_replace_strmem.c' || echo '$(srcdir)/'`mc_replace_strmem.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.Tpo $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_replace_strmem.c' object='vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.o `test -f 'mc_replace_strmem.c' || echo '$(srcdir)/'`mc_replace_strmem.c
+
+vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.obj: mc_replace_strmem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -MT vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.obj -MD -MP -MF $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.Tpo -c -o vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.obj `if test -f 'mc_replace_strmem.c'; then $(CYGPATH_W) 'mc_replace_strmem.c'; else $(CYGPATH_W) '$(srcdir)/mc_replace_strmem.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.Tpo $(DEPDIR)/vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='mc_replace_strmem.c' object='vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS) $(CPPFLAGS) $(vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS) $(CFLAGS) -c -o vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so-mc_replace_strmem.obj `if test -f 'mc_replace_strmem.c'; then $(CYGPATH_W) 'mc_replace_strmem.c'; else $(CYGPATH_W) '$(srcdir)/mc_replace_strmem.c'; fi`
+install-pkgincludeHEADERS: $(pkginclude_HEADERS)
+ @$(NORMAL_INSTALL)
+ test -z "$(pkgincludedir)" || $(MKDIR_P) "$(DESTDIR)$(pkgincludedir)"
+ @list='$(pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ for p in $$list; do \
+ if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+ echo "$$d$$p"; \
+ done | $(am__base_list) | \
+ while read files; do \
+ echo " $(INSTALL_HEADER) $$files '$(DESTDIR)$(pkgincludedir)'"; \
+ $(INSTALL_HEADER) $$files "$(DESTDIR)$(pkgincludedir)" || exit $$?; \
+ done
+
+uninstall-pkgincludeHEADERS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(pkginclude_HEADERS)'; test -n "$(pkgincludedir)" || list=; \
+ files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
+ test -n "$$files" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(pkgincludedir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(pkgincludedir)" && rm -f $$files
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+check: check-recursive
+all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
+installdirs: installdirs-recursive
+installdirs-am:
+ for dir in "$(DESTDIR)$(pkgincludedir)"; do \
+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ done
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-generic clean-local clean-noinstPROGRAMS \
+ mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am: install-pkgincludeHEADERS
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am: install-exec-local
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am: uninstall-pkgincludeHEADERS
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+ install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am all-local check check-am clean clean-generic \
+ clean-local clean-noinstPROGRAMS ctags ctags-recursive \
+ distclean distclean-compile distclean-generic distclean-tags \
+ distdir dvi dvi-am html html-am info info-am install \
+ install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-exec-local \
+ install-html install-html-am install-info install-info-am \
+ install-man install-pdf install-pdf-am \
+ install-pkgincludeHEADERS install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ installdirs-am maintainer-clean maintainer-clean-generic \
+ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \
+ ps ps-am tags tags-recursive uninstall uninstall-am \
+ uninstall-pkgincludeHEADERS
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+#----------------------------------------------------------------------------
+# General stuff
+#----------------------------------------------------------------------------
+
+all-local: inplace-noinst_PROGRAMS inplace-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS
+
+# mc_main.c contains the helper function for memcheck that get called
+# all the time. To maximise performance compile with -fomit-frame-pointer
+# Primary beneficiary is x86.
+mc_main.o: CFLAGS += -fomit-frame-pointer
+
+# mc_replace_strmem.c runs on the simulated CPU, and it often appears
+# in stack traces shown to the user. It is built with
+# -fno-omit-frame-pointer so as to guarantee robust backtraces on x86,
+# on which CFI based unwinding is not the "normal" case and so is
+# sometimes fragile.
+mc_replace_strmem.o: CFLAGS += -fno-omit-frame-pointer
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/docs/mc-manual.xml b/main/memcheck/docs/mc-manual.xml
index 9a82b5a..53568d9 100644
--- a/main/memcheck/docs/mc-manual.xml
+++ b/main/memcheck/docs/mc-manual.xml
@@ -855,7 +855,10 @@
byte. This can be useful when trying to shake out obscure
memory corruption problems. The allocated area is still
regarded by Memcheck as undefined -- this option only affects its
- contents.
+ contents. Note that <option>--malloc-fill</option> does not
+ affect a block of memory when it is used as argument
+ to client requests VALGRIND_MEMPOOL_ALLOC or
+ VALGRIND_MALLOCLIKE_BLOCK.
</para>
</listitem>
</varlistentry>
@@ -871,7 +874,9 @@
specified byte value. This can be useful when trying to shake out
obscure memory corruption problems. The freed area is still
regarded by Memcheck as not valid for access -- this option only
- affects its contents.
+ affects its contents. Note that <option>--free-fill</option> does not
+ affect a block of memory when it is used as argument to
+ client requests VALGRIND_MEMPOOL_FREE or VALGRIND_FREELIKE_BLOCK.
</para>
</listitem>
</varlistentry>
@@ -1372,7 +1377,7 @@
(default 1) bytes at <addr> has the specified accessibility.
It then outputs a description of <addr>. In the following
example, a detailed description is available because the
- option <option>--read-var-info=yes</option> was given Valgrind at
+ option <option>--read-var-info=yes</option> was given at Valgrind
startup:
</para>
<programlisting><![CDATA[
@@ -1388,9 +1393,10 @@
<para><varname>leak_check [full*|summary]
[reachable|possibleleak*|definiteleak]
[increased*|changed|any]
+ [unlimited*|limited <max_loss_records_output>]
</varname>
performs a leak check. The <varname>*</varname> in the arguments
- indicates the default value. </para>
+ indicates the default values. </para>
<para> If the first argument is <varname>summary</varname>, only a
summary of the leak search is given; otherwise a full leak report
@@ -1399,7 +1405,12 @@
the number of blocks leaked and their total size. When a full
report is requested, the next two arguments further specify what
kind of leaks to report. A leak's details are shown if they match
- both the second and third argument.
+ both the second and third argument. A full leak report might
+ output detailed information for many leaks. The nr of leaks for
+ which information is output can be controlled using
+ the <varname>limited</varname> argument followed by the maximum nr
+ of leak records to output. If this maximum is reached, the leak
+ search outputs the records with the biggest number of bytes.
</para>
<para>The second argument controls what kind of blocks are shown for
@@ -1428,7 +1439,7 @@
</para>
<para>The following example shows usage of the
- <varname>leak_check monitor</varname> command on
+ <varname>leak_check</varname> monitor command on
the <varname>memcheck/tests/leak-cases.c</varname> regression
test. The first command outputs one entry having an increase in
the leaked bytes. The second command is the same as the first
@@ -1437,31 +1448,31 @@
there was no increase since the previous leak search.</para>
<programlisting><![CDATA[
(gdb) monitor leak_check full possibleleak increased
-==14729== 16 (+16) bytes in 1 (+1) blocks are possibly lost in loss record 13 of 16
-==14729== at 0x4006E9E: malloc (vg_replace_malloc.c:236)
-==14729== by 0x80484D5: mk (leak-cases.c:52)
-==14729== by 0x804855F: f (leak-cases.c:81)
-==14729== by 0x80488F5: main (leak-cases.c:107)
-==14729==
-==14729== LEAK SUMMARY:
-==14729== definitely lost: 32 (+0) bytes in 2 (+0) blocks
-==14729== indirectly lost: 16 (+0) bytes in 1 (+0) blocks
-==14729== possibly lost: 32 (+16) bytes in 2 (+1) blocks
-==14729== still reachable: 96 (+16) bytes in 6 (+1) blocks
-==14729== suppressed: 0 (+0) bytes in 0 (+0) blocks
-==14729== Reachable blocks (those to which a pointer was found) are not shown.
-==14729== To see them, add 'reachable any' args to leak_check
-==14729==
+==19520== 16 (+16) bytes in 1 (+1) blocks are possibly lost in loss record 9 of 12
+==19520== at 0x40070B4: malloc (vg_replace_malloc.c:263)
+==19520== by 0x80484D5: mk (leak-cases.c:52)
+==19520== by 0x804855F: f (leak-cases.c:81)
+==19520== by 0x80488E0: main (leak-cases.c:107)
+==19520==
+==19520== LEAK SUMMARY:
+==19520== definitely lost: 32 (+0) bytes in 2 (+0) blocks
+==19520== indirectly lost: 16 (+0) bytes in 1 (+0) blocks
+==19520== possibly lost: 32 (+16) bytes in 2 (+1) blocks
+==19520== still reachable: 96 (+16) bytes in 6 (+1) blocks
+==19520== suppressed: 0 (+0) bytes in 0 (+0) blocks
+==19520== Reachable blocks (those to which a pointer was found) are not shown.
+==19520== To see them, add 'reachable any' args to leak_check
+==19520==
(gdb) mo l
-==14729== LEAK SUMMARY:
-==14729== definitely lost: 32 (+0) bytes in 2 (+0) blocks
-==14729== indirectly lost: 16 (+0) bytes in 1 (+0) blocks
-==14729== possibly lost: 32 (+0) bytes in 2 (+0) blocks
-==14729== still reachable: 96 (+0) bytes in 6 (+0) blocks
-==14729== suppressed: 0 (+0) bytes in 0 (+0) blocks
-==14729== Reachable blocks (those to which a pointer was found) are not shown.
-==14729== To see them, add 'reachable any' args to leak_check
-==14729==
+==19520== LEAK SUMMARY:
+==19520== definitely lost: 32 (+0) bytes in 2 (+0) blocks
+==19520== indirectly lost: 16 (+0) bytes in 1 (+0) blocks
+==19520== possibly lost: 32 (+0) bytes in 2 (+0) blocks
+==19520== still reachable: 96 (+0) bytes in 6 (+0) blocks
+==19520== suppressed: 0 (+0) bytes in 0 (+0) blocks
+==19520== Reachable blocks (those to which a pointer was found) are not shown.
+==19520== To see them, add 'reachable any' args to leak_check
+==19520==
(gdb)
]]></programlisting>
<para>Note that when using Valgrind's gdbserver, it is not
@@ -1474,6 +1485,144 @@
abbreviation: <computeroutput>mo l f r a</computeroutput>).
</para>
</listitem>
+
+ <listitem>
+ <para><varname>block_list <loss_record_nr> </varname>
+ shows the list of blocks belonging to <loss_record_nr>.
+ </para>
+
+ <para> A leak search merges the allocated blocks in loss records :
+ a loss record re-groups all blocks having the same state (for
+ example, Definitely Lost) and the same allocation backtrace.
+ Each loss record is identified in the leak search result
+ by a loss record number.
+ The <varname>block_list</varname> command shows the loss record information
+ followed by the addresses and sizes of the blocks which have been
+ merged in the loss record.
+ </para>
+
+ <para> If a directly lost block causes some other blocks to be indirectly
+ lost, the block_list command will also show these indirectly lost blocks.
+ The indirectly lost blocks will be indented according to the level of indirection
+ between the directly lost block and the indirectly lost block(s).
+ Each indirectly lost block is followed by the reference of its loss record.
+ </para>
+
+ <para> The block_list command can be used on the results of a leak search as long
+ as no block has been freed after this leak search: as soon as the program frees
+ a block, a new leak search is needed before block_list can be used again.
+ </para>
+
+ <para>
+ In the below example, the program leaks a tree structure by losing the pointer to
+ the block A (top of the tree).
+ So, the block A is directly lost, causing an indirect
+ loss of blocks B to G. The first block_list command shows the loss record of A
+ (a definitely lost block with address 0x4028028, size 16). The addresses and sizes
+ of the indirectly lost blocks due to block A are shown below the block A.
+ The second command shows the details of one of the indirect loss records output
+ by the first command.
+ </para>
+<programlisting><![CDATA[
+ A
+ / \
+ B C
+ / \ / \
+ D E F G
+]]></programlisting>
+
+<programlisting><![CDATA[
+(gdb) bt
+#0 main () at leak-tree.c:69
+(gdb) monitor leak_check full any
+==19552== 112 (16 direct, 96 indirect) bytes in 1 blocks are definitely lost in loss record 7 of 7
+==19552== at 0x40070B4: malloc (vg_replace_malloc.c:263)
+==19552== by 0x80484D5: mk (leak-tree.c:28)
+==19552== by 0x80484FC: f (leak-tree.c:41)
+==19552== by 0x8048856: main (leak-tree.c:63)
+==19552==
+==19552== LEAK SUMMARY:
+==19552== definitely lost: 16 bytes in 1 blocks
+==19552== indirectly lost: 96 bytes in 6 blocks
+==19552== possibly lost: 0 bytes in 0 blocks
+==19552== still reachable: 0 bytes in 0 blocks
+==19552== suppressed: 0 bytes in 0 blocks
+==19552==
+(gdb) monitor block_list 7
+==19552== 112 (16 direct, 96 indirect) bytes in 1 blocks are definitely lost in loss record 7 of 7
+==19552== at 0x40070B4: malloc (vg_replace_malloc.c:263)
+==19552== by 0x80484D5: mk (leak-tree.c:28)
+==19552== by 0x80484FC: f (leak-tree.c:41)
+==19552== by 0x8048856: main (leak-tree.c:63)
+==19552== 0x4028028[16]
+==19552== 0x4028068[16] indirect loss record 1
+==19552== 0x40280E8[16] indirect loss record 3
+==19552== 0x4028128[16] indirect loss record 4
+==19552== 0x40280A8[16] indirect loss record 2
+==19552== 0x4028168[16] indirect loss record 5
+==19552== 0x40281A8[16] indirect loss record 6
+(gdb) mo b 2
+==19552== 16 bytes in 1 blocks are indirectly lost in loss record 2 of 7
+==19552== at 0x40070B4: malloc (vg_replace_malloc.c:263)
+==19552== by 0x80484D5: mk (leak-tree.c:28)
+==19552== by 0x8048519: f (leak-tree.c:43)
+==19552== by 0x8048856: main (leak-tree.c:63)
+==19552== 0x40280A8[16]
+==19552== 0x4028168[16] indirect loss record 5
+==19552== 0x40281A8[16] indirect loss record 6
+(gdb)
+
+]]></programlisting>
+
+ </listitem>
+
+ <listitem>
+ <para><varname>who_points_at <addr> [<len>]</varname>
+ shows all the locations where a pointer to addr is found.
+ If len is equal to 1, the command only shows the locations pointing
+ exactly at addr (i.e. the "start pointers" to addr).
+ If len is > 1, "interior pointers" pointing at the len first bytes
+ will also be shown.
+ </para>
+
+ <para>The locations searched for are the same as the locations
+ used in the leak search. So, <varname>who_points_at</varname> can a.o.
+ be used to show why the leak search still can reach a block, or can
+ search for dangling pointers to a freed block.
+ Each location pointing at addr (or pointing inside addr if interior pointers
+ are being searched for) will be described.
+ </para>
+
+ <para>In the below example, the pointers to the 'tree block A' (see example
+ in command <varname>block_list</varname>) is shown before the tree was leaked.
+ The descriptions are detailed as the option <option>--read-var-info=yes</option>
+ was given at Valgrind startup. The second call shows the pointers (start and interior
+ pointers) to block G. The block G (0x40281A8) is reachable via block C (0x40280a8)
+ and register ECX of tid 1 (tid is the Valgrind thread id).
+ It is "interior reachable" via the register EBX.
+ </para>
+
+<programlisting><![CDATA[
+(gdb) monitor who_points_at 0x4028028
+==20852== Searching for pointers to 0x4028028
+==20852== *0x8049e20 points at 0x4028028
+==20852== Location 0x8049e20 is 0 bytes inside global var "t"
+==20852== declared at leak-tree.c:35
+(gdb) monitor who_points_at 0x40281A8 16
+==20852== Searching for pointers pointing in 16 bytes from 0x40281a8
+==20852== *0x40280ac points at 0x40281a8
+==20852== Address 0x40280ac is 4 bytes inside a block of size 16 alloc'd
+==20852== at 0x40070B4: malloc (vg_replace_malloc.c:263)
+==20852== by 0x80484D5: mk (leak-tree.c:28)
+==20852== by 0x8048519: f (leak-tree.c:43)
+==20852== by 0x8048856: main (leak-tree.c:63)
+==20852== tid 1 register ECX points at 0x40281a8
+==20852== tid 1 register EBX interior points at 2 bytes inside 0x40281a8
+(gdb)
+]]></programlisting>
+ </listitem>
+
+
</itemizedlist>
</sect1>
diff --git a/main/memcheck/mc_errors.c b/main/memcheck/mc_errors.c
index 8eb445a..5447263 100644
--- a/main/memcheck/mc_errors.c
+++ b/main/memcheck/mc_errors.c
@@ -8,7 +8,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -31,6 +31,7 @@
#include "pub_tool_basics.h"
#include "pub_tool_gdbserver.h"
+#include "pub_tool_poolalloc.h" // For mc_include.h
#include "pub_tool_hashtable.h" // For mc_include.h
#include "pub_tool_libcbase.h"
#include "pub_tool_libcassert.h"
@@ -43,8 +44,6 @@
#include "pub_tool_threadstate.h"
#include "pub_tool_debuginfo.h" // VG_(get_dataname_and_offset)
#include "pub_tool_xarray.h"
-#include "pub_tool_vki.h"
-#include "pub_tool_libcfile.h"
#include "mc_include.h"
@@ -448,6 +447,95 @@
return buf;
}
+static void pp_LossRecord(UInt n_this_record, UInt n_total_records,
+ LossRecord* lr, Bool xml)
+{
+ // char arrays to produce the indication of increase/decrease in case
+ // of delta_mode != LCD_Any
+ char d_bytes[20];
+ char d_direct_bytes[20];
+ char d_indirect_bytes[20];
+ char d_num_blocks[20];
+
+ MC_(snprintf_delta) (d_bytes, 20,
+ lr->szB + lr->indirect_szB,
+ lr->old_szB + lr->old_indirect_szB,
+ MC_(detect_memory_leaks_last_delta_mode));
+ MC_(snprintf_delta) (d_direct_bytes, 20,
+ lr->szB,
+ lr->old_szB,
+ MC_(detect_memory_leaks_last_delta_mode));
+ MC_(snprintf_delta) (d_indirect_bytes, 20,
+ lr->indirect_szB,
+ lr->old_indirect_szB,
+ MC_(detect_memory_leaks_last_delta_mode));
+ MC_(snprintf_delta) (d_num_blocks, 20,
+ (SizeT) lr->num_blocks,
+ (SizeT) lr->old_num_blocks,
+ MC_(detect_memory_leaks_last_delta_mode));
+
+ if (xml) {
+ emit(" <kind>%s</kind>\n", xml_leak_kind(lr->key.state));
+ if (lr->indirect_szB > 0) {
+ emit( " <xwhat>\n" );
+ emit( " <text>%'lu%s (%'lu%s direct, %'lu%s indirect) bytes "
+ "in %'u%s blocks"
+ " are %s in loss record %'u of %'u</text>\n",
+ lr->szB + lr->indirect_szB, d_bytes,
+ lr->szB, d_direct_bytes,
+ lr->indirect_szB, d_indirect_bytes,
+ lr->num_blocks, d_num_blocks,
+ str_leak_lossmode(lr->key.state),
+ n_this_record, n_total_records );
+ // Nb: don't put commas in these XML numbers
+ emit( " <leakedbytes>%lu</leakedbytes>\n",
+ lr->szB + lr->indirect_szB );
+ emit( " <leakedblocks>%u</leakedblocks>\n", lr->num_blocks );
+ emit( " </xwhat>\n" );
+ } else {
+ emit( " <xwhat>\n" );
+ emit( " <text>%'lu%s bytes in %'u%s blocks"
+ " are %s in loss record %'u of %'u</text>\n",
+ lr->szB, d_direct_bytes,
+ lr->num_blocks, d_num_blocks,
+ str_leak_lossmode(lr->key.state),
+ n_this_record, n_total_records );
+ emit( " <leakedbytes>%ld</leakedbytes>\n", lr->szB);
+ emit( " <leakedblocks>%d</leakedblocks>\n", lr->num_blocks);
+ emit( " </xwhat>\n" );
+ }
+ VG_(pp_ExeContext)(lr->key.allocated_at);
+ } else { /* ! if (xml) */
+ if (lr->indirect_szB > 0) {
+ emit(
+ "%'lu%s (%'lu%s direct, %'lu%s indirect) bytes in %'u%s blocks"
+ " are %s in loss record %'u of %'u\n",
+ lr->szB + lr->indirect_szB, d_bytes,
+ lr->szB, d_direct_bytes,
+ lr->indirect_szB, d_indirect_bytes,
+ lr->num_blocks, d_num_blocks,
+ str_leak_lossmode(lr->key.state),
+ n_this_record, n_total_records
+ );
+ } else {
+ emit(
+ "%'lu%s bytes in %'u%s blocks are %s in loss record %'u of %'u\n",
+ lr->szB, d_direct_bytes,
+ lr->num_blocks, d_num_blocks,
+ str_leak_lossmode(lr->key.state),
+ n_this_record, n_total_records
+ );
+ }
+ VG_(pp_ExeContext)(lr->key.allocated_at);
+ } /* if (xml) */
+}
+
+void MC_(pp_LossRecord)(UInt n_this_record, UInt n_total_records,
+ LossRecord* l)
+{
+ pp_LossRecord (n_this_record, n_total_records, l, /* xml */ False);
+}
+
void MC_(pp_Error) ( Error* err )
{
const Bool xml = VG_(clo_xml); /* a shorthand */
@@ -718,84 +806,7 @@
UInt n_this_record = extra->Err.Leak.n_this_record;
UInt n_total_records = extra->Err.Leak.n_total_records;
LossRecord* lr = extra->Err.Leak.lr;
- // char arrays to produce the indication of increase/decrease in case
- // of delta_mode != LCD_Any
- char d_bytes[20];
- char d_direct_bytes[20];
- char d_indirect_bytes[20];
- char d_num_blocks[20];
-
- MC_(snprintf_delta) (d_bytes, 20,
- lr->szB + lr->indirect_szB,
- lr->old_szB + lr->old_indirect_szB,
- MC_(detect_memory_leaks_last_delta_mode));
- MC_(snprintf_delta) (d_direct_bytes, 20,
- lr->szB,
- lr->old_szB,
- MC_(detect_memory_leaks_last_delta_mode));
- MC_(snprintf_delta) (d_indirect_bytes, 20,
- lr->indirect_szB,
- lr->old_indirect_szB,
- MC_(detect_memory_leaks_last_delta_mode));
- MC_(snprintf_delta) (d_num_blocks, 20,
- (SizeT) lr->num_blocks,
- (SizeT) lr->old_num_blocks,
- MC_(detect_memory_leaks_last_delta_mode));
-
- if (xml) {
- emit(" <kind>%s</kind>\n", xml_leak_kind(lr->key.state));
- if (lr->indirect_szB > 0) {
- emit( " <xwhat>\n" );
- emit( " <text>%'lu%s (%'lu%s direct, %'lu%s indirect) bytes "
- "in %'u%s blocks"
- " are %s in loss record %'u of %'u</text>\n",
- lr->szB + lr->indirect_szB, d_bytes,
- lr->szB, d_direct_bytes,
- lr->indirect_szB, d_indirect_bytes,
- lr->num_blocks, d_num_blocks,
- str_leak_lossmode(lr->key.state),
- n_this_record, n_total_records );
- // Nb: don't put commas in these XML numbers
- emit( " <leakedbytes>%lu</leakedbytes>\n",
- lr->szB + lr->indirect_szB );
- emit( " <leakedblocks>%u</leakedblocks>\n", lr->num_blocks );
- emit( " </xwhat>\n" );
- } else {
- emit( " <xwhat>\n" );
- emit( " <text>%'lu%s bytes in %'u%s blocks"
- " are %s in loss record %'u of %'u</text>\n",
- lr->szB, d_direct_bytes,
- lr->num_blocks, d_num_blocks,
- str_leak_lossmode(lr->key.state),
- n_this_record, n_total_records );
- emit( " <leakedbytes>%ld</leakedbytes>\n", lr->szB);
- emit( " <leakedblocks>%d</leakedblocks>\n", lr->num_blocks);
- emit( " </xwhat>\n" );
- }
- VG_(pp_ExeContext)(lr->key.allocated_at);
- } else { /* ! if (xml) */
- if (lr->indirect_szB > 0) {
- emit(
- "%'lu%s (%'lu%s direct, %'lu%s indirect) bytes in %'u%s blocks"
- " are %s in loss record %'u of %'u\n",
- lr->szB + lr->indirect_szB, d_bytes,
- lr->szB, d_direct_bytes,
- lr->indirect_szB, d_indirect_bytes,
- lr->num_blocks, d_num_blocks,
- str_leak_lossmode(lr->key.state),
- n_this_record, n_total_records
- );
- } else {
- emit(
- "%'lu%s bytes in %'u%s blocks are %s in loss record %'u of %'u\n",
- lr->szB, d_direct_bytes,
- lr->num_blocks, d_num_blocks,
- str_leak_lossmode(lr->key.state),
- n_this_record, n_total_records
- );
- }
- VG_(pp_ExeContext)(lr->key.allocated_at);
- } /* if (xml) */
+ pp_LossRecord (n_this_record, n_total_records, lr, xml);
break;
}
@@ -804,30 +815,6 @@
VG_(get_error_kind)(err));
VG_(tool_panic)("unknown error code in mc_pp_Error)");
}
-
- if (MC_(clo_summary_file)) {
- /* Each time we report a warning, we replace the contents of the summary
- * file with one line indicating the number of reported warnings.
- * This way, at the end of memcheck execution we will have a file with
- * one line saying
- * Memcheck: XX warnings reported
- * If there were no warnings, the file will not be changed.
- * If memcheck crashes, the file will still contain the last summary.
- * */
- static int n_warnings = 0;
- char buf[100];
- SysRes sres = VG_(open)(MC_(clo_summary_file),
- VKI_O_WRONLY|VKI_O_CREAT|VKI_O_TRUNC,
- VKI_S_IRUSR|VKI_S_IWUSR);
- if (sr_isError(sres)) {
- VG_(tool_panic)("can not open the summary file");
- }
- n_warnings++;
- VG_(snprintf)(buf, sizeof(buf), "Memcheck: %d warning(s) reported\n",
- n_warnings);
- VG_(write)(sr_Res(sres), buf, VG_(strlen)(buf));
- VG_(close)(sr_Res(sres));
- }
}
/*------------------------------------------------------------*/
@@ -1095,7 +1082,7 @@
Bool addr_is_in_MC_Chunk_default_REDZONE_SZB(MC_Chunk* mc, Addr a)
{
return VG_(addr_is_in_block)( a, mc->data, mc->szB,
- MC_MALLOC_REDZONE_SZB );
+ MC_(Malloc_Redzone_SzB) );
}
static
Bool addr_is_in_MC_Chunk_with_REDZONE_SZB(MC_Chunk* mc, Addr a, SizeT rzB)
@@ -1128,6 +1115,30 @@
if (mempool_block_maybe_describe( a, ai )) {
return;
}
+ /* Blocks allocated by memcheck malloc functions are either
+ on the recently freed list or on the malloc-ed list.
+ Custom blocks can be on both : a recently freed block might
+ have been just re-allocated.
+ So, first search the malloc-ed block, as the most recent
+ block is the probable cause of error.
+ We however detect and report that this is a recently re-allocated
+ block. */
+ /* -- Search for a currently malloc'd block which might bracket it. -- */
+ VG_(HT_ResetIter)(MC_(malloc_list));
+ while ( (mc = VG_(HT_Next)(MC_(malloc_list))) ) {
+ if (addr_is_in_MC_Chunk_default_REDZONE_SZB(mc, a)) {
+ ai->tag = Addr_Block;
+ ai->Addr.Block.block_kind = Block_Mallocd;
+ if (MC_(get_freed_block_bracketting)( a ))
+ ai->Addr.Block.block_desc = "recently re-allocated block";
+ else
+ ai->Addr.Block.block_desc = "block";
+ ai->Addr.Block.block_szB = mc->szB;
+ ai->Addr.Block.rwoffset = (Word)a - (Word)mc->data;
+ ai->Addr.Block.lastchange = mc->where;
+ return;
+ }
+ }
/* -- Search for a recently freed block which might bracket it. -- */
mc = MC_(get_freed_block_bracketting)( a );
if (mc) {
@@ -1139,19 +1150,6 @@
ai->Addr.Block.lastchange = mc->where;
return;
}
- /* -- Search for a currently malloc'd block which might bracket it. -- */
- VG_(HT_ResetIter)(MC_(malloc_list));
- while ( (mc = VG_(HT_Next)(MC_(malloc_list))) ) {
- if (addr_is_in_MC_Chunk_default_REDZONE_SZB(mc, a)) {
- ai->tag = Addr_Block;
- ai->Addr.Block.block_kind = Block_Mallocd;
- ai->Addr.Block.block_desc = "block";
- ai->Addr.Block.block_szB = mc->szB;
- ai->Addr.Block.rwoffset = (Word)a - (Word)mc->data;
- ai->Addr.Block.lastchange = mc->where;
- return;
- }
- }
/* -- Perhaps the variable type/location data describes it? -- */
ai->Addr.Variable.descr1
= VG_(newXA)( VG_(malloc), "mc.da.descr1",
@@ -1405,10 +1403,6 @@
// Unaddressable read/write attempt at given size
Addr1Supp, Addr2Supp, Addr4Supp, Addr8Supp, Addr16Supp,
- // https://bugs.kde.org/show_bug.cgi?id=256525
- UnaddrSupp, // Matches Addr*.
- UninitSupp, // Matches Value*, Param and Cond.
-
JumpSupp, // Jump to unaddressable target
FreeSupp, // Invalid or mismatching free
OverlapSupp, // Overlapping blocks in memcpy(), strcpy(), etc
@@ -1441,12 +1435,6 @@
else if (VG_STREQ(name, "Value4")) skind = Value4Supp;
else if (VG_STREQ(name, "Value8")) skind = Value8Supp;
else if (VG_STREQ(name, "Value16")) skind = Value16Supp;
- // https://bugs.kde.org/show_bug.cgi?id=256525
- else if (VG_STREQ(name, "Unaddressable")) skind = UnaddrSupp;
- else if (VG_STREQ(name, "Unaddr")) skind = UnaddrSupp;
- else if (VG_STREQ(name, "Uninitialised")) skind = UninitSupp;
- else if (VG_STREQ(name, "Uninitialized")) skind = UninitSupp;
- else if (VG_STREQ(name, "Uninit")) skind = UninitSupp;
else
return False;
@@ -1506,16 +1494,6 @@
addr_case:
return (ekind == Err_Addr && extra->Err.Addr.szB == su_szB);
- // https://bugs.kde.org/show_bug.cgi?id=256525
- case UnaddrSupp:
- return (ekind == Err_Addr ||
- (ekind == Err_MemParam && extra->Err.MemParam.isAddrErr));
-
- case UninitSupp:
- return (ekind == Err_Cond || ekind == Err_Value ||
- ekind == Err_RegParam ||
- (ekind == Err_MemParam && !extra->Err.MemParam.isAddrErr));
-
case JumpSupp:
return (ekind == Err_Jump);
diff --git a/main/memcheck/mc_include.h b/main/memcheck/mc_include.h
index cc76957..abb59db 100644
--- a/main/memcheck/mc_include.h
+++ b/main/memcheck/mc_include.h
@@ -8,7 +8,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -42,8 +42,12 @@
/*--- Tracking the heap ---*/
/*------------------------------------------------------------*/
-/* We want at least a 64B redzone on client heap blocks for Memcheck */
-#define MC_MALLOC_REDZONE_SZB 64
+/* By default, we want at least a 16B redzone on client heap blocks
+ for Memcheck.
+ The default can be modified by --redzone-size. */
+#define MC_MALLOC_DEFAULT_REDZONE_SZB 16
+// effective redzone, as (possibly) modified by --redzone-size:
+extern SizeT MC_(Malloc_Redzone_SzB);
/* For malloc()/new/new[] vs. free()/delete/delete[] mismatch checking. */
typedef
@@ -101,6 +105,9 @@
is found. */
MC_Chunk* MC_(get_freed_block_bracketting)( Addr a );
+/* For efficient pooled alloc/free of the MC_Chunk. */
+extern PoolAlloc* MC_(chunk_poolalloc);
+
/* For tracking malloc'd blocks. Nb: it's quite important that it's a
VgHashTable, because VgHashTable allows duplicate keys without complaint.
This can occur if a user marks a malloc() block as also a custom block with
@@ -118,6 +125,8 @@
void MC_(copy_address_range_state) ( Addr src, Addr dst, SizeT len );
void MC_(print_malloc_stats) ( void );
+/* nr of free operations done */
+SizeT MC_(get_cmalloc_n_frees) ( void );
void* MC_(malloc) ( ThreadId tid, SizeT n );
void* MC_(__builtin_new) ( ThreadId tid, SizeT n );
@@ -251,6 +260,7 @@
}
Reachedness;
+
/* For VALGRIND_COUNT_LEAKS client request */
extern SizeT MC_(bytes_leaked);
extern SizeT MC_(bytes_indirect);
@@ -311,15 +321,25 @@
Bool show_reachable;
Bool show_possibly_lost;
LeakCheckDeltaMode deltamode;
+ UInt max_loss_records_output; // limit on the nr of loss records output.
Bool requested_by_monitor_command; // True when requested by gdb/vgdb.
}
LeakCheckParams;
-void MC_(detect_memory_leaks) ( ThreadId tid, LeakCheckParams lcp);
+void MC_(detect_memory_leaks) ( ThreadId tid, LeakCheckParams * lcp);
// maintains the lcp.deltamode given in the last call to detect_memory_leaks
extern LeakCheckDeltaMode MC_(detect_memory_leaks_last_delta_mode);
+// prints the list of blocks corresponding to the given loss_record_nr.
+// Returns True if loss_record_nr identifies a correct loss record from last leak search.
+// Returns False otherwise.
+Bool MC_(print_block_list) ( UInt loss_record_nr);
+
+// Prints the addresses/registers/... at which a pointer to
+// the given range [address, address+szB[ is found.
+void MC_(who_points_at) ( Addr address, SizeT szB);
+
// if delta_mode == LCD_Any, prints in buf an empty string
// otherwise prints a delta in the layout " (+%'lu)" or " (-%'lu)"
extern char * MC_(snprintf_delta) (char * buf, Int size,
@@ -330,8 +350,9 @@
Bool MC_(is_valid_aligned_word) ( Addr a );
Bool MC_(is_within_valid_secondary) ( Addr a );
-void MC_(pp_LeakError)(UInt n_this_record, UInt n_total_records,
- LossRecord* l);
+// Prints as user msg a description of the given loss record.
+void MC_(pp_LossRecord)(UInt n_this_record, UInt n_total_records,
+ LossRecord* l);
/*------------------------------------------------------------*/
@@ -441,9 +462,6 @@
extern Bool MC_(clo_show_reachable);
/* In leak check, show possibly-lost blocks? default: YES */
-extern Bool MC_(clo_show_possible);
-
-/* In leak check, show possibly-lost blocks? default: YES */
extern Bool MC_(clo_show_possibly_lost);
/* Assume accesses immediately below %esp are due to gcc-2.96 bugs.
@@ -484,9 +502,6 @@
*/
extern Int MC_(clo_mc_level);
-// Print a short summary to a separate file.
-extern const char* MC_(clo_summary_file);
-
/*------------------------------------------------------------*/
/*--- Instrumentation ---*/
@@ -538,11 +553,13 @@
VG_REGPARM(2) void MC_(helperc_b_store4) ( Addr a, UWord d32 );
VG_REGPARM(2) void MC_(helperc_b_store8) ( Addr a, UWord d32 );
VG_REGPARM(2) void MC_(helperc_b_store16)( Addr a, UWord d32 );
+VG_REGPARM(2) void MC_(helperc_b_store32)( Addr a, UWord d32 );
VG_REGPARM(1) UWord MC_(helperc_b_load1) ( Addr a );
VG_REGPARM(1) UWord MC_(helperc_b_load2) ( Addr a );
VG_REGPARM(1) UWord MC_(helperc_b_load4) ( Addr a );
VG_REGPARM(1) UWord MC_(helperc_b_load8) ( Addr a );
VG_REGPARM(1) UWord MC_(helperc_b_load16)( Addr a );
+VG_REGPARM(1) UWord MC_(helperc_b_load32)( Addr a );
/* Functions defined in mc_translate.c */
IRSB* MC_(instrument) ( VgCallbackClosure* closure,
diff --git a/main/memcheck/mc_leakcheck.c b/main/memcheck/mc_leakcheck.c
index 09013ed..6252b2a 100644
--- a/main/memcheck/mc_leakcheck.c
+++ b/main/memcheck/mc_leakcheck.c
@@ -7,7 +7,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -42,7 +42,8 @@
#include "pub_tool_mallocfree.h"
#include "pub_tool_options.h"
#include "pub_tool_oset.h"
-#include "pub_tool_signals.h"
+#include "pub_tool_poolalloc.h"
+#include "pub_tool_signals.h" // Needed for mc_include.h
#include "pub_tool_libcsetjmp.h" // setjmp facilities
#include "pub_tool_tooliface.h" // Needed for mc_include.h
@@ -425,19 +426,39 @@
struct {
UInt state:2; // Reachedness.
UInt pending:1; // Scan pending.
- SizeT indirect_szB : (sizeof(SizeT)*8)-3; // If Unreached, how many bytes
- // are unreachable from here.
+ union {
+ SizeT indirect_szB : (sizeof(SizeT)*8)-3; // If Unreached, how many bytes
+ // are unreachable from here.
+ SizeT clique : (sizeof(SizeT)*8)-3; // if IndirectLeak, clique leader
+ // to which it belongs.
+ } IorC;
}
LC_Extra;
// An array holding pointers to every chunk we're checking. Sorted by address.
+// lc_chunks is initialised during leak search. It is kept after leak search
+// to support printing the list of blocks belonging to a loss record.
+// lc_chunk array can only be used validly till the next "free" operation
+// (as a free operation potentially destroys one or more chunks).
+// To detect lc_chunk is valid, we store the nr of frees operations done
+// when lc_chunk was build : lc_chunks (and lc_extras) stays valid as
+// long as no free operations has been done since lc_chunks building.
static MC_Chunk** lc_chunks;
// How many chunks we're dealing with.
static Int lc_n_chunks;
+static SizeT lc_chunks_n_frees_marker;
+// This has the same number of entries as lc_chunks, and each entry
+// in lc_chunks corresponds with the entry here (ie. lc_chunks[i] and
+// lc_extras[i] describe the same block).
+static LC_Extra* lc_extras;
+
// chunks will be converted and merged in loss record, maintained in lr_table
// lr_table elements are kept from one leak_search to another to implement
// the "print new/changed leaks" client request
static OSet* lr_table;
+// Array of sorted loss record (produced during last leak search).
+static LossRecord** lr_array;
+
// DeltaMode used the last time we called detect_memory_leaks.
// The recorded leak errors must be output using a logic based on this delta_mode.
@@ -445,11 +466,6 @@
LeakCheckDeltaMode MC_(detect_memory_leaks_last_delta_mode);
-// This has the same number of entries as lc_chunks, and each entry
-// in lc_chunks corresponds with the entry here (ie. lc_chunks[i] and
-// lc_extras[i] describe the same block).
-static LC_Extra* lc_extras;
-
// Records chunks that are currently being processed. Each element in the
// stack is an index into lc_chunks and lc_extras. Its size is
// 'lc_n_chunks' because in the worst case that's how many chunks could be
@@ -477,7 +493,6 @@
SizeT MC_(blocks_reachable) = 0;
SizeT MC_(blocks_suppressed) = 0;
-
// Determines if a pointer is to a chunk. Returns the chunk number et al
// via call-by-reference.
static Bool
@@ -487,7 +502,10 @@
MC_Chunk* ch;
LC_Extra* ex;
- // Quick filter.
+ // Quick filter. Note: implemented with am, not with get_vabits2
+ // as ptr might be random data pointing anywhere. On 64 bit
+ // platforms, getting va bits for random data can be quite costly
+ // due to the secondary map.
if (!VG_(am_is_valid_for_client)(ptr, 1, VKI_PROT_READ)) {
return False;
} else {
@@ -548,62 +566,6 @@
}
}
-// Partial fix for https://bugs.kde.org/show_bug.cgi?id=280271
-// Only used in valgrind-variant now.
-static Bool vv_lc_is_start_pointer(Addr ptr, MC_Chunk* chunk)
-{
- // Pointers to the start of the chunk are indeed start-pointers
- if (ptr == chunk->data)
- return True;
-
- // Below are a few heuristics to reduce the number of false positive
- // "possibly lost" reports on C++ types by treating some interior-pointers
- // as start-pointers (inspired by the Dr. Memory article at CGO2011).
-
- // Shortcut: heuristics assume 'ptr' is word-aligned.
- if (ptr != VG_ROUNDUP(ptr, sizeof(Addr)))
- return False;
-
- if (ptr == chunk->data + sizeof(Addr)) {
- // Pointer to a new[]-allocated buffer?
- SizeT sz_from_header = *(SizeT*)chunk->data,
- expected_sz = chunk->szB - sizeof(Addr);
- if (sz_from_header > 0 && sz_from_header <= expected_sz &&
- expected_sz % sz_from_header == 0)
- return True;
- }
-
- if (ptr == chunk->data + 3*sizeof(Addr)) {
- // Pointer to std::string internals?
- SizeT assumed_len = *(SizeT*)chunk->data,
- assumed_capacity = *((SizeT*)chunk->data + 1);
- if (assumed_len <= assumed_capacity) {
- // std::string
- if (chunk->szB - 3*sizeof(SizeT) == assumed_capacity + 1)
- return True;
-
- // std::basic_string<unsigned short> a.k.a. string16
- if (chunk->szB - 3*sizeof(SizeT) == 2*(assumed_capacity + 1))
- return True;
-
- // std::basic_string<wchar_t> on Linux
- if (chunk->szB - 3*sizeof(SizeT) == 4*(assumed_capacity + 1))
- return True;
- }
- }
-
- if (ptr == chunk->data + 2*sizeof(Addr)) {
- // Pointer to a nss_ZAlloc-allocated buffer?
- // It adds a header like this: 'struct { void *ptr; uint32 size };'
- SizeT sz_from_header = *(UInt*)(chunk->data + sizeof(Addr)),
- expected_sz = chunk->szB - 2*sizeof(Addr);
- tl_assert(sizeof(UInt) == 4);
- if (sz_from_header == expected_sz)
- return True;
- }
-
- return False;
-}
// If 'ptr' is pointing to a heap-allocated block which hasn't been seen
// before, push it onto the mark stack.
@@ -621,8 +583,7 @@
// - Unreached --> Possible
// - Unreached --> Reachable
// - Possible --> Reachable
- if (vv_lc_is_start_pointer(ptr, ch) &&
- is_prior_definite && ex->state != Reachable) {
+ if (ptr == ch->data && is_prior_definite && ex->state != Reachable) {
// 'ptr' points to the start of the block, and the prior node is
// definite, which means that this block is definitely reachable.
ex->state = Reachable;
@@ -643,7 +604,7 @@
}
static void
-lc_push_if_a_chunk_ptr_register(Addr ptr)
+lc_push_if_a_chunk_ptr_register(ThreadId tid, HChar* regname, Addr ptr)
{
lc_push_without_clique_if_a_chunk_ptr(ptr, /*is_prior_definite*/True);
}
@@ -652,7 +613,7 @@
// before, push it onto the mark stack. Clique is the index of the
// clique leader.
static void
-lc_push_with_clique_if_a_chunk_ptr(Addr ptr, Int clique)
+lc_push_with_clique_if_a_chunk_ptr(Addr ptr, Int clique, Int cur_clique)
{
Int ch_no;
MC_Chunk* ch;
@@ -670,7 +631,6 @@
// Note that, unlike reachable blocks, we currently don't distinguish
// between start-pointers and interior-pointers here. We probably
// should, though.
- ex->state = IndirectLeak;
lc_push(ch_no, ch);
// Add the block to the clique, and add its size to the
@@ -678,28 +638,29 @@
// itself a clique leader, it isn't any more, so add its
// indirect_szB to the new clique leader.
if (VG_DEBUG_CLIQUE) {
- if (ex->indirect_szB > 0)
+ if (ex->IorC.indirect_szB > 0)
VG_(printf)(" clique %d joining clique %d adding %lu+%lu\n",
ch_no, clique, (unsigned long)ch->szB,
- (unsigned long)ex->indirect_szB);
+ (unsigned long)ex->IorC.indirect_szB);
else
VG_(printf)(" block %d joining clique %d adding %lu\n",
ch_no, clique, (unsigned long)ch->szB);
}
- lc_extras[clique].indirect_szB += ch->szB;
- lc_extras[clique].indirect_szB += ex->indirect_szB;
- ex->indirect_szB = 0; // Shouldn't matter.
+ lc_extras[clique].IorC.indirect_szB += ch->szB;
+ lc_extras[clique].IorC.indirect_szB += ex->IorC.indirect_szB;
+ ex->state = IndirectLeak;
+ ex->IorC.clique = (SizeT) cur_clique;
}
}
static void
-lc_push_if_a_chunk_ptr(Addr ptr, Int clique, Bool is_prior_definite)
+lc_push_if_a_chunk_ptr(Addr ptr, Int clique, Int cur_clique, Bool is_prior_definite)
{
if (-1 == clique)
lc_push_without_clique_if_a_chunk_ptr(ptr, is_prior_definite);
else
- lc_push_with_clique_if_a_chunk_ptr(ptr, clique);
+ lc_push_with_clique_if_a_chunk_ptr(ptr, clique, cur_clique);
}
@@ -714,13 +675,44 @@
VG_MINIMAL_LONGJMP(memscan_jmpbuf);
}
+// lc_scan_memory has 2 modes:
+//
+// 1. Leak check mode (searched == 0).
+// -----------------------------------
// Scan a block of memory between [start, start+len). This range may
// be bogus, inaccessable, or otherwise strange; we deal with it. For each
// valid aligned word we assume it's a pointer to a chunk a push the chunk
// onto the mark stack if so.
+// clique is the "highest level clique" in which indirectly leaked blocks have
+// to be collected. cur_clique is the current "lower" level clique through which
+// the memory to be scanned has been found.
+// Example: in the below tree if A is leaked, the top level clique will
+// be A, while lower level cliques will be B and C.
+/*
+ A
+ / \
+ B C
+ / \ / \
+ D E F G
+*/
+// Proper handling of top and lowest level clique allows block_list of a loss
+// record to describe the hierarchy of indirectly leaked blocks.
+//
+// 2. Search ptr mode (searched != 0).
+// -----------------------------------
+// In this mode, searches for pointers to a specific address range
+// In such a case, lc_scan_memory just scans [start..start+len[ for pointers to searched
+// and outputs the places where searched is found. It does not recursively scans the
+// found memory.
static void
-lc_scan_memory(Addr start, SizeT len, Bool is_prior_definite, Int clique)
+lc_scan_memory(Addr start, SizeT len, Bool is_prior_definite, Int clique, Int cur_clique,
+ Addr searched, SizeT szB)
{
+ /* memory scan is based on the assumption that valid pointers are aligned
+ on a multiple of sizeof(Addr). So, we can (and must) skip the begin and
+ end portions of the block if they are not aligned on sizeof(Addr):
+ These cannot be a valid pointer, and calls to MC_(is_valid_aligned_word)
+ will assert for a non aligned address. */
Addr ptr = VG_ROUNDUP(start, sizeof(Addr));
Addr end = VG_ROUNDDN(start+len, sizeof(Addr));
vki_sigset_t sigmask;
@@ -731,46 +723,90 @@
VG_(sigprocmask)(VKI_SIG_SETMASK, NULL, &sigmask);
VG_(set_fault_catcher)(scan_all_valid_memory_catcher);
- // We might be in the middle of a page. Do a cheap check to see if
- // it's valid; if not, skip onto the next page.
- if (!VG_(am_is_valid_for_client)(ptr, sizeof(Addr), VKI_PROT_READ))
+ /* Optimisation: the loop below will check for each begin
+ of SM chunk if the chunk is fully unaddressable. The idea is to
+ skip efficiently such fully unaddressable SM chunks.
+ So, we preferrably start the loop on a chunk boundary.
+ If the chunk is not fully unaddressable, we might be in
+ an unaddressable page. Again, the idea is to skip efficiently
+ such unaddressable page : this is the "else" part.
+ We use an "else" so that two consecutive fully unaddressable
+ SM chunks will be skipped efficiently: first one is skipped
+ by this piece of code. The next SM chunk will be skipped inside
+ the loop. */
+ if ( ! MC_(is_within_valid_secondary)(ptr) ) {
+ // Skip an invalid SM chunk till the beginning of the next SM Chunk.
+ ptr = VG_ROUNDUP(ptr+1, SM_SIZE);
+ } else if (!VG_(am_is_valid_for_client)(ptr, sizeof(Addr), VKI_PROT_READ)) {
+ // else we are in a (at least partially) valid SM chunk.
+ // We might be in the middle of an unreadable page.
+ // Do a cheap check to see if it's valid;
+ // if not, skip onto the next page.
ptr = VG_PGROUNDUP(ptr+1); // First page is bad - skip it.
+ }
+ /* This optimisation and below loop is based on some relationships between
+ VKI_PAGE_SIZE, SM_SIZE and sizeof(Addr) which are asserted in
+ MC_(detect_memory_leaks). */
while (ptr < end) {
Addr addr;
// Skip invalid chunks.
- if ( ! MC_(is_within_valid_secondary)(ptr) ) {
- ptr = VG_ROUNDUP(ptr+1, SM_SIZE);
- continue;
+ if (UNLIKELY((ptr % SM_SIZE) == 0)) {
+ if (! MC_(is_within_valid_secondary)(ptr) ) {
+ ptr = VG_ROUNDUP(ptr+1, SM_SIZE);
+ continue;
+ }
}
// Look to see if this page seems reasonable.
- if ((ptr % VKI_PAGE_SIZE) == 0) {
+ if (UNLIKELY((ptr % VKI_PAGE_SIZE) == 0)) {
if (!VG_(am_is_valid_for_client)(ptr, sizeof(Addr), VKI_PROT_READ)) {
ptr += VKI_PAGE_SIZE; // Bad page - skip it.
continue;
}
+ // aspacemgr indicates the page is readable and belongs to client.
+ // We still probe the page explicitely in case aspacemgr is
+ // desynchronised with the real page mappings.
+ // Such a desynchronisation can happen due to an aspacemgr bug.
+ // Note that if the application is using mprotect(NONE), then
+ // a page can be unreadable but have addressable and defined
+ // VA bits (see mc_main.c function mc_new_mem_mprotect).
+ if (VG_MINIMAL_SETJMP(memscan_jmpbuf) == 0) {
+ // Try a read in the beginning of the page ...
+ Addr test = *(volatile Addr *)ptr;
+ __asm__ __volatile__("": :"r"(test) : "cc","memory");
+ } else {
+ // Catch read error ...
+ // We need to restore the signal mask, because we were
+ // longjmped out of a signal handler.
+ VG_(sigprocmask)(VKI_SIG_SETMASK, &sigmask, NULL);
+ ptr += VKI_PAGE_SIZE; // Bad page - skip it.
+ continue;
+ }
}
- if (VG_MINIMAL_SETJMP(memscan_jmpbuf) == 0) {
- if ( MC_(is_valid_aligned_word)(ptr) ) {
- lc_scanned_szB += sizeof(Addr);
- addr = *(Addr *)ptr;
- // If we get here, the scanned word is in valid memory. Now
- // let's see if its contents point to a chunk.
- lc_push_if_a_chunk_ptr(addr, clique, is_prior_definite);
- } else if (0 && VG_DEBUG_LEAKCHECK) {
- VG_(printf)("%#lx not valid\n", ptr);
+ if ( MC_(is_valid_aligned_word)(ptr) ) {
+ lc_scanned_szB += sizeof(Addr);
+ addr = *(Addr *)ptr;
+ // If we get here, the scanned word is in valid memory. Now
+ // let's see if its contents point to a chunk.
+ if (UNLIKELY(searched)) {
+ if (addr >= searched && addr < searched + szB) {
+ if (addr == searched)
+ VG_(umsg)("*%#lx points at %#lx\n", ptr, searched);
+ else
+ VG_(umsg)("*%#lx interior points at %lu bytes inside %#lx\n",
+ ptr, (long unsigned) addr - searched, searched);
+ MC_(pp_describe_addr) (ptr);
+ }
+ } else {
+ lc_push_if_a_chunk_ptr(addr, clique, cur_clique, is_prior_definite);
}
- ptr += sizeof(Addr);
- } else {
- // We need to restore the signal mask, because we were
- // longjmped out of a signal handler.
- VG_(sigprocmask)(VKI_SIG_SETMASK, &sigmask, NULL);
-
- ptr = VG_PGROUNDUP(ptr+1); // Bad page - skip it.
+ } else if (0 && VG_DEBUG_LEAKCHECK) {
+ VG_(printf)("%#lx not valid\n", ptr);
}
+ ptr += sizeof(Addr);
}
VG_(sigprocmask)(VKI_SIG_SETMASK, &sigmask, NULL);
@@ -791,7 +827,8 @@
is_prior_definite = ( Possible != lc_extras[top].state );
lc_scan_memory(lc_chunks[top]->data, lc_chunks[top]->szB,
- is_prior_definite, clique);
+ is_prior_definite, clique, (clique == -1 ? -1 : top),
+ /*searched*/ 0, 0);
}
}
@@ -838,10 +875,86 @@
return 0;
}
-static void print_results(ThreadId tid, LeakCheckParams lcp)
-{
+// allocates or reallocates lr_array, and set its elements to the loss records
+// contains in lr_table.
+static Int get_lr_array_from_lr_table(void) {
Int i, n_lossrecords;
- LossRecord** lr_array;
+ LossRecord* lr;
+
+ n_lossrecords = VG_(OSetGen_Size)(lr_table);
+
+ // (re-)create the array of pointers to the loss records.
+ // lr_array is kept to allow producing the block list from gdbserver.
+ if (lr_array != NULL)
+ VG_(free)(lr_array);
+ lr_array = VG_(malloc)("mc.pr.2", n_lossrecords * sizeof(LossRecord*));
+ i = 0;
+ VG_(OSetGen_ResetIter)(lr_table);
+ while ( (lr = VG_(OSetGen_Next)(lr_table)) ) {
+ lr_array[i++] = lr;
+ }
+ tl_assert(i == n_lossrecords);
+ return n_lossrecords;
+}
+
+
+static void get_printing_rules(LeakCheckParams* lcp,
+ LossRecord* lr,
+ Bool* count_as_error,
+ Bool* print_record)
+{
+ // Rules for printing:
+ // - We don't show suppressed loss records ever (and that's controlled
+ // within the error manager).
+ // - We show non-suppressed loss records that are not "reachable" if
+ // --leak-check=yes.
+ // - We show all non-suppressed loss records if --leak-check=yes and
+ // --show-reachable=yes.
+ //
+ // Nb: here "reachable" means Reachable *or* IndirectLeak; note that
+ // this is different to "still reachable" used elsewhere because it
+ // includes indirectly lost blocks!
+
+ Bool delta_considered;
+
+ switch (lcp->deltamode) {
+ case LCD_Any:
+ delta_considered = lr->num_blocks > 0;
+ break;
+ case LCD_Increased:
+ delta_considered
+ = lr->szB > lr->old_szB
+ || lr->indirect_szB > lr->old_indirect_szB
+ || lr->num_blocks > lr->old_num_blocks;
+ break;
+ case LCD_Changed:
+ delta_considered = lr->szB != lr->old_szB
+ || lr->indirect_szB != lr->old_indirect_szB
+ || lr->num_blocks != lr->old_num_blocks;
+ break;
+ default:
+ tl_assert(0);
+ }
+
+ *print_record = lcp->mode == LC_Full && delta_considered &&
+ ( lcp->show_reachable ||
+ Unreached == lr->key.state ||
+ ( lcp->show_possibly_lost &&
+ Possible == lr->key.state ) );
+ // We don't count a leaks as errors with lcp->mode==LC_Summary.
+ // Otherwise you can get high error counts with few or no error
+ // messages, which can be confusing. Also, you could argue that
+ // indirect leaks should be counted as errors, but it seems better to
+ // make the counting criteria similar to the printing criteria. So we
+ // don't count them.
+ *count_as_error = lcp->mode == LC_Full && delta_considered &&
+ ( Unreached == lr->key.state ||
+ Possible == lr->key.state );
+}
+
+static void print_results(ThreadId tid, LeakCheckParams* lcp)
+{
+ Int i, n_lossrecords, start_lr_output_scan;
LossRecord* lr;
Bool is_suppressed;
SizeT old_bytes_leaked = MC_(bytes_leaked); /* to report delta in summary */
@@ -867,6 +980,29 @@
VG_(malloc), "mc.pr.1",
VG_(free));
+ // If we have loss records from a previous search, reset values to have
+ // proper printing of the deltas between previous search and this search.
+ n_lossrecords = get_lr_array_from_lr_table();
+ for (i = 0; i < n_lossrecords; i++) {
+ if (lr_array[i]->num_blocks == 0) {
+ // remove from lr_table the old loss_records with 0 bytes found
+ VG_(OSetGen_Remove) (lr_table, &lr_array[i]->key);
+ VG_(OSetGen_FreeNode)(lr_table, lr_array[i]);
+ } else {
+ // move the leak sizes to old_* and zero the current sizes
+ // for next leak search
+ lr_array[i]->old_szB = lr_array[i]->szB;
+ lr_array[i]->old_indirect_szB = lr_array[i]->indirect_szB;
+ lr_array[i]->old_num_blocks = lr_array[i]->num_blocks;
+ lr_array[i]->szB = 0;
+ lr_array[i]->indirect_szB = 0;
+ lr_array[i]->num_blocks = 0;
+ }
+ }
+ // lr_array now contains "invalid" loss records => free it.
+ // lr_array will be re-created below with the kept and new loss records.
+ VG_(free) (lr_array);
+ lr_array = NULL;
// Convert the chunks into loss records, merging them where appropriate.
for (i = 0; i < lc_n_chunks; i++) {
@@ -883,7 +1019,8 @@
// loss record's details in-situ. This is safe because we don't
// change the elements used as the OSet key.
old_lr->szB += ch->szB;
- old_lr->indirect_szB += ex->indirect_szB;
+ if (ex->state == Unreached)
+ old_lr->indirect_szB += ex->IorC.indirect_szB;
old_lr->num_blocks++;
} else {
// No existing loss record matches this chunk. Create a new loss
@@ -891,7 +1028,10 @@
lr = VG_(OSetGen_AllocNode)(lr_table, sizeof(LossRecord));
lr->key = lrkey;
lr->szB = ch->szB;
- lr->indirect_szB = ex->indirect_szB;
+ if (ex->state == Unreached)
+ lr->indirect_szB = ex->IorC.indirect_szB;
+ else
+ lr->indirect_szB = 0;
lr->num_blocks = 1;
lr->old_szB = 0;
lr->old_indirect_szB = 0;
@@ -899,16 +1039,10 @@
VG_(OSetGen_Insert)(lr_table, lr);
}
}
- n_lossrecords = VG_(OSetGen_Size)(lr_table);
- // Create an array of pointers to the loss records.
- lr_array = VG_(malloc)("mc.pr.2", n_lossrecords * sizeof(LossRecord*));
- i = 0;
- VG_(OSetGen_ResetIter)(lr_table);
- while ( (lr = VG_(OSetGen_Next)(lr_table)) ) {
- lr_array[i++] = lr;
- }
- tl_assert(i == n_lossrecords);
+ // (re-)create the array of pointers to the (new) loss records.
+ n_lossrecords = get_lr_array_from_lr_table ();
+ tl_assert(VG_(OSetGen_Size)(lr_table) == n_lossrecords);
// Sort the array by loss record sizes.
VG_(ssort)(lr_array, n_lossrecords, sizeof(LossRecord*),
@@ -921,61 +1055,40 @@
MC_(blocks_reachable) = MC_(bytes_reachable) = 0;
MC_(blocks_suppressed) = MC_(bytes_suppressed) = 0;
- // Print the loss records (in size order) and collect summary stats.
- for (i = 0; i < n_lossrecords; i++) {
- Bool count_as_error, print_record, delta_considered;
- // Rules for printing:
- // - We don't show suppressed loss records ever (and that's controlled
- // within the error manager).
- // - We show non-suppressed loss records that are not "reachable" if
- // --leak-check=yes.
- // - We show all non-suppressed loss records if --leak-check=yes and
- // --show-reachable=yes.
- //
- // Nb: here "reachable" means Reachable *or* IndirectLeak; note that
- // this is different to "still reachable" used elsewhere because it
- // includes indirectly lost blocks!
- //
- lr = lr_array[i];
- switch (lcp.deltamode) {
- case LCD_Any:
- delta_considered = lr->num_blocks > 0;
- break;
- case LCD_Increased:
- delta_considered
- = lr_array[i]->szB > lr_array[i]->old_szB
- || lr_array[i]->indirect_szB > lr_array[i]->old_indirect_szB
- || lr->num_blocks > lr->old_num_blocks;
- break;
- case LCD_Changed:
- delta_considered = lr_array[i]->szB != lr_array[i]->old_szB
- || lr_array[i]->indirect_szB != lr_array[i]->old_indirect_szB
- || lr->num_blocks != lr->old_num_blocks;
- break;
- default:
- tl_assert(0);
+ // If there is a maximum nr of loss records we can output, then first
+ // compute from where the output scan has to start.
+ // By default, start from the first loss record. Compute a higher
+ // value if there is a maximum to respect. We need to print the last
+ // records, as the one with the biggest sizes are more interesting.
+ start_lr_output_scan = 0;
+ if (lcp->mode == LC_Full && lcp->max_loss_records_output < n_lossrecords) {
+ Int nr_printable_records = 0;
+ for (i = n_lossrecords - 1; i >= 0 && start_lr_output_scan == 0; i--) {
+ Bool count_as_error, print_record;
+ lr = lr_array[i];
+ get_printing_rules (lcp, lr, &count_as_error, &print_record);
+ // Do not use get_printing_rules results for is_suppressed, as we
+ // only want to check if the record would be suppressed.
+ is_suppressed =
+ MC_(record_leak_error) ( tid, i+1, n_lossrecords, lr,
+ False /* print_record */,
+ False /* count_as_error */);
+ if (print_record && !is_suppressed) {
+ nr_printable_records++;
+ if (nr_printable_records == lcp->max_loss_records_output)
+ start_lr_output_scan = i;
+ }
}
+ }
- print_record = lcp.mode == LC_Full && delta_considered &&
- ( lcp.show_reachable ||
- Unreached == lr->key.state ||
- ( lcp.show_possibly_lost &&
- Possible == lr->key.state ) );
- // We don't count a leaks as errors with lcp.mode==LC_Summary.
- // Otherwise you can get high error counts with few or no error
- // messages, which can be confusing. Also, you could argue that
- // indirect leaks should be counted as errors, but it seems better to
- // make the counting criteria similar to the printing criteria. So we
- // don't count them.
- count_as_error = lcp.mode == LC_Full && delta_considered &&
- ( Unreached == lr->key.state ||
- Possible == lr->key.state );
- if ((Reachable == lr->key.state && !MC_(clo_show_reachable)) ||
- (Possible == lr->key.state && !MC_(clo_show_possibly_lost)))
- is_suppressed = False;
- else
- is_suppressed = MC_(record_leak_error)(tid, i+1, n_lossrecords, lr,
- print_record, count_as_error);
+ // Print the loss records (in size order) and collect summary stats.
+ for (i = start_lr_output_scan; i < n_lossrecords; i++) {
+ Bool count_as_error, print_record;
+ lr = lr_array[i];
+ get_printing_rules(lcp, lr, &count_as_error, &print_record);
+ is_suppressed =
+ MC_(record_leak_error) ( tid, i+1, n_lossrecords, lr, print_record,
+ count_as_error );
if (is_suppressed) {
MC_(blocks_suppressed) += lr->num_blocks;
@@ -1002,25 +1115,6 @@
}
}
- for (i = 0; i < n_lossrecords; i++)
- {
- if (lr->num_blocks == 0)
- // remove from lr_table the old loss_records with 0 bytes found
- VG_(OSetGen_Remove) (lr_table, &lr_array[i]->key);
- else
- {
- // move the leak sizes to old_* and zero the current sizes
- // for next leak search
- lr_array[i]->old_szB = lr_array[i]->szB;
- lr_array[i]->old_indirect_szB = lr_array[i]->indirect_szB;
- lr_array[i]->old_num_blocks = lr_array[i]->num_blocks;
- lr_array[i]->szB = 0;
- lr_array[i]->indirect_szB = 0;
- lr_array[i]->num_blocks = 0;
- }
- }
- VG_(free)(lr_array);
-
if (VG_(clo_verbosity) > 0 && !VG_(clo_xml)) {
char d_bytes[20];
char d_blocks[20];
@@ -1028,44 +1122,44 @@
VG_(umsg)("LEAK SUMMARY:\n");
VG_(umsg)(" definitely lost: %'lu%s bytes in %'lu%s blocks\n",
MC_(bytes_leaked),
- MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_leaked), old_bytes_leaked, lcp.deltamode),
+ MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_leaked), old_bytes_leaked, lcp->deltamode),
MC_(blocks_leaked),
- MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_leaked), old_blocks_leaked, lcp.deltamode));
+ MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_leaked), old_blocks_leaked, lcp->deltamode));
VG_(umsg)(" indirectly lost: %'lu%s bytes in %'lu%s blocks\n",
MC_(bytes_indirect),
- MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_indirect), old_bytes_indirect, lcp.deltamode),
+ MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_indirect), old_bytes_indirect, lcp->deltamode),
MC_(blocks_indirect),
- MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_indirect), old_blocks_indirect, lcp.deltamode) );
+ MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_indirect), old_blocks_indirect, lcp->deltamode) );
VG_(umsg)(" possibly lost: %'lu%s bytes in %'lu%s blocks\n",
MC_(bytes_dubious),
- MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_dubious), old_bytes_dubious, lcp.deltamode),
+ MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_dubious), old_bytes_dubious, lcp->deltamode),
MC_(blocks_dubious),
- MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_dubious), old_blocks_dubious, lcp.deltamode) );
+ MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_dubious), old_blocks_dubious, lcp->deltamode) );
VG_(umsg)(" still reachable: %'lu%s bytes in %'lu%s blocks\n",
MC_(bytes_reachable),
- MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_reachable), old_bytes_reachable, lcp.deltamode),
+ MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_reachable), old_bytes_reachable, lcp->deltamode),
MC_(blocks_reachable),
- MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_reachable), old_blocks_reachable, lcp.deltamode) );
+ MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_reachable), old_blocks_reachable, lcp->deltamode) );
VG_(umsg)(" suppressed: %'lu%s bytes in %'lu%s blocks\n",
MC_(bytes_suppressed),
- MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_suppressed), old_bytes_suppressed, lcp.deltamode),
+ MC_(snprintf_delta) (d_bytes, 20, MC_(bytes_suppressed), old_bytes_suppressed, lcp->deltamode),
MC_(blocks_suppressed),
- MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_suppressed), old_blocks_suppressed, lcp.deltamode) );
- if (lcp.mode != LC_Full &&
+ MC_(snprintf_delta) (d_blocks, 20, MC_(blocks_suppressed), old_blocks_suppressed, lcp->deltamode) );
+ if (lcp->mode != LC_Full &&
(MC_(blocks_leaked) + MC_(blocks_indirect) +
MC_(blocks_dubious) + MC_(blocks_reachable)) > 0) {
- if (lcp.requested_by_monitor_command)
+ if (lcp->requested_by_monitor_command)
VG_(umsg)("To see details of leaked memory, give 'full' arg to leak_check\n");
else
VG_(umsg)("Rerun with --leak-check=full to see details "
"of leaked memory\n");
}
- if (lcp.mode == LC_Full &&
- MC_(blocks_reachable) > 0 && !lcp.show_reachable)
+ if (lcp->mode == LC_Full &&
+ MC_(blocks_reachable) > 0 && !lcp->show_reachable)
{
VG_(umsg)("Reachable blocks (those to which a pointer "
"was found) are not shown.\n");
- if (lcp.requested_by_monitor_command)
+ if (lcp->requested_by_monitor_command)
VG_(umsg)("To see them, add 'reachable any' args to leak_check\n");
else
VG_(umsg)("To see them, rerun with: --leak-check=full "
@@ -1075,29 +1169,197 @@
}
}
+// print recursively all indirectly leaked blocks collected in clique.
+static void print_clique (Int clique, UInt level)
+{
+ Int ind;
+ Int i, n_lossrecords;;
+
+ n_lossrecords = VG_(OSetGen_Size)(lr_table);
+
+ for (ind = 0; ind < lc_n_chunks; ind++) {
+ LC_Extra* ind_ex = &(lc_extras)[ind];
+ if (ind_ex->state == IndirectLeak && ind_ex->IorC.clique == (SizeT) clique) {
+ MC_Chunk* ind_ch = lc_chunks[ind];
+ LossRecord* ind_lr;
+ LossRecordKey ind_lrkey;
+ Int lr_i;
+ ind_lrkey.state = ind_ex->state;
+ ind_lrkey.allocated_at = ind_ch->where;
+ ind_lr = VG_(OSetGen_Lookup)(lr_table, &ind_lrkey);
+ for (lr_i = 0; lr_i < n_lossrecords; lr_i++)
+ if (ind_lr == lr_array[lr_i])
+ break;
+ for (i = 0; i < level; i++)
+ VG_(umsg)(" ");
+ VG_(umsg)("%p[%lu] indirect loss record %d\n",
+ (void *)ind_ch->data, (unsigned long)ind_ch->szB,
+ lr_i+1); // lr_i+1 for user numbering.
+ if (lr_i >= n_lossrecords)
+ VG_(umsg)
+ ("error: no indirect loss record found for %p[%lu]?????\n",
+ (void *)ind_ch->data, (unsigned long)ind_ch->szB);
+ print_clique(ind, level+1);
+ }
+ }
+ }
+
+Bool MC_(print_block_list) ( UInt loss_record_nr)
+{
+ Int i, n_lossrecords;
+ LossRecord* lr;
+
+ if (lr_table == NULL || lc_chunks == NULL || lc_extras == NULL) {
+ VG_(umsg)("Can't print block list : no valid leak search result\n");
+ return False;
+ }
+
+ if (lc_chunks_n_frees_marker != MC_(get_cmalloc_n_frees)()) {
+ VG_(umsg)("Can't print obsolete block list : redo a leak search first\n");
+ return False;
+ }
+
+ n_lossrecords = VG_(OSetGen_Size)(lr_table);
+ if (loss_record_nr >= n_lossrecords)
+ return False; // Invalid loss record nr.
+
+ tl_assert (lr_array);
+ lr = lr_array[loss_record_nr];
+
+ // (re-)print the loss record details.
+ // (+1 on loss_record_nr as user numbering for loss records starts at 1).
+ MC_(pp_LossRecord)(loss_record_nr+1, n_lossrecords, lr);
+
+ // Match the chunks with loss records.
+ for (i = 0; i < lc_n_chunks; i++) {
+ MC_Chunk* ch = lc_chunks[i];
+ LC_Extra* ex = &(lc_extras)[i];
+ LossRecord* old_lr;
+ LossRecordKey lrkey;
+ lrkey.state = ex->state;
+ lrkey.allocated_at = ch->where;
+
+ old_lr = VG_(OSetGen_Lookup)(lr_table, &lrkey);
+ if (old_lr) {
+ // We found an existing loss record matching this chunk.
+ // If this is the loss record we are looking for, then output the pointer.
+ if (old_lr == lr_array[loss_record_nr]) {
+ VG_(umsg)("%p[%lu]\n",
+ (void *)ch->data, (unsigned long) ch->szB);
+ if (ex->state != Reachable) {
+ // We can print the clique in all states, except Reachable.
+ // In Unreached state, lc_chunk[i] is the clique leader.
+ // In IndirectLeak, lc_chunk[i] might have been a clique leader
+ // which was later collected in another clique.
+ // For Possible, lc_chunk[i] might be the top of a clique
+ // or an intermediate clique.
+ print_clique(i, 1);
+ }
+ }
+ } else {
+ // No existing loss record matches this chunk ???
+ VG_(umsg)("error: no loss record found for %p[%lu]?????\n",
+ (void *)ch->data, (unsigned long) ch->szB);
+ }
+ }
+ return True;
+}
+
+// If searched = 0, scan memory root set, pushing onto the mark stack the blocks
+// encountered.
+// Otherwise (searched != 0), scan the memory root set searching for ptr pointing
+// inside [searched, searched+szB[.
+static void scan_memory_root_set(Addr searched, SizeT szB)
+{
+ Int i;
+ Int n_seg_starts;
+ Addr* seg_starts = VG_(get_segment_starts)( &n_seg_starts );
+
+ tl_assert(seg_starts && n_seg_starts > 0);
+
+ lc_scanned_szB = 0;
+
+ // VG_(am_show_nsegments)( 0, "leakcheck");
+ for (i = 0; i < n_seg_starts; i++) {
+ SizeT seg_size;
+ NSegment const* seg = VG_(am_find_nsegment)( seg_starts[i] );
+ tl_assert(seg);
+
+ if (seg->kind != SkFileC && seg->kind != SkAnonC) continue;
+ if (!(seg->hasR && seg->hasW)) continue;
+ if (seg->isCH) continue;
+
+ // Don't poke around in device segments as this may cause
+ // hangs. Exclude /dev/zero just in case someone allocated
+ // memory by explicitly mapping /dev/zero.
+ if (seg->kind == SkFileC
+ && (VKI_S_ISCHR(seg->mode) || VKI_S_ISBLK(seg->mode))) {
+ HChar* dev_name = VG_(am_get_filename)( (NSegment*)seg );
+ if (dev_name && 0 == VG_(strcmp)(dev_name, "/dev/zero")) {
+ // Don't skip /dev/zero.
+ } else {
+ // Skip this device mapping.
+ continue;
+ }
+ }
+
+ if (0)
+ VG_(printf)("ACCEPT %2d %#lx %#lx\n", i, seg->start, seg->end);
+
+ // Scan the segment. We use -1 for the clique number, because this
+ // is a root-set.
+ seg_size = seg->end - seg->start + 1;
+ if (VG_(clo_verbosity) > 2) {
+ VG_(message)(Vg_DebugMsg,
+ " Scanning root segment: %#lx..%#lx (%lu)\n",
+ seg->start, seg->end, seg_size);
+ }
+ lc_scan_memory(seg->start, seg_size, /*is_prior_definite*/True,
+ /*clique*/-1, /*cur_clique*/-1,
+ searched, szB);
+ }
+ VG_(free)(seg_starts);
+}
+
/*------------------------------------------------------------*/
/*--- Top-level entry point. ---*/
/*------------------------------------------------------------*/
-void MC_(detect_memory_leaks) ( ThreadId tid, LeakCheckParams lcp)
+void MC_(detect_memory_leaks) ( ThreadId tid, LeakCheckParams* lcp)
{
Int i, j;
- tl_assert(lcp.mode != LC_Off);
+ tl_assert(lcp->mode != LC_Off);
- MC_(detect_memory_leaks_last_delta_mode) = lcp.deltamode;
+ // Verify some assertions which are used in lc_scan_memory.
+ tl_assert((VKI_PAGE_SIZE % sizeof(Addr)) == 0);
+ tl_assert((SM_SIZE % sizeof(Addr)) == 0);
+ // Above two assertions are critical, while below assertion
+ // ensures that the optimisation in the loop is done in the
+ // correct order : the loop checks for (big) SM chunk skipping
+ // before checking for (smaller) page skipping.
+ tl_assert((SM_SIZE % VKI_PAGE_SIZE) == 0);
+
+
+ MC_(detect_memory_leaks_last_delta_mode) = lcp->deltamode;
// Get the chunks, stop if there were none.
+ if (lc_chunks) {
+ VG_(free)(lc_chunks);
+ lc_chunks = NULL;
+ }
lc_chunks = find_active_chunks(&lc_n_chunks);
+ lc_chunks_n_frees_marker = MC_(get_cmalloc_n_frees)();
if (lc_n_chunks == 0) {
tl_assert(lc_chunks == NULL);
if (lr_table != NULL) {
- // forget the previous recorded LossRecords as next leak search will in any case
- // just create new leaks.
+ // forget the previous recorded LossRecords as next leak search
+ // can in any case just create new leaks.
// Maybe it would be better to rather call print_result ?
- // (at least when leak decrease are requested)
+ // (at least when leak decreases are requested)
// This will then output all LossRecords with a size decreasing to 0
VG_(OSetGen_Destroy) (lr_table);
+ lr_table = NULL;
}
if (VG_(clo_verbosity) >= 1 && !VG_(clo_xml)) {
VG_(umsg)("All heap blocks were freed -- no leaks are possible\n");
@@ -1165,20 +1427,28 @@
lc_n_chunks--;
} else {
- VG_(umsg)("Block 0x%lx..0x%lx overlaps with block 0x%lx..0x%lx",
+ VG_(umsg)("Block 0x%lx..0x%lx overlaps with block 0x%lx..0x%lx\n",
start1, end1, start2, end2);
+ VG_(umsg)("Blocks allocation contexts:\n"),
+ VG_(pp_ExeContext)( ch1->where);
+ VG_(umsg)("\n"),
+ VG_(pp_ExeContext)( ch2->where);
VG_(umsg)("This is usually caused by using VALGRIND_MALLOCLIKE_BLOCK");
- VG_(umsg)("in an inappropriate way.");
+ VG_(umsg)("in an inappropriate way.\n");
tl_assert (0);
}
}
// Initialise lc_extras.
+ if (lc_extras) {
+ VG_(free)(lc_extras);
+ lc_extras = NULL;
+ }
lc_extras = VG_(malloc)( "mc.dml.2", lc_n_chunks * sizeof(LC_Extra) );
for (i = 0; i < lc_n_chunks; i++) {
lc_extras[i].state = Unreached;
lc_extras[i].pending = False;
- lc_extras[i].indirect_szB = 0;
+ lc_extras[i].IorC.indirect_szB = 0;
}
// Initialise lc_markstack.
@@ -1196,52 +1466,7 @@
// Scan the memory root-set, pushing onto the mark stack any blocks
// pointed to.
- {
- Int n_seg_starts;
- Addr* seg_starts = VG_(get_segment_starts)( &n_seg_starts );
-
- tl_assert(seg_starts && n_seg_starts > 0);
-
- lc_scanned_szB = 0;
-
- // VG_(am_show_nsegments)( 0, "leakcheck");
- for (i = 0; i < n_seg_starts; i++) {
- SizeT seg_size;
- NSegment const* seg = VG_(am_find_nsegment)( seg_starts[i] );
- tl_assert(seg);
-
- if (seg->kind != SkFileC && seg->kind != SkAnonC) continue;
- if (!(seg->hasR && seg->hasW)) continue;
- if (seg->isCH) continue;
-
- // Don't poke around in device segments as this may cause
- // hangs. Exclude /dev/zero just in case someone allocated
- // memory by explicitly mapping /dev/zero.
- if (seg->kind == SkFileC
- && (VKI_S_ISCHR(seg->mode) || VKI_S_ISBLK(seg->mode))) {
- HChar* dev_name = VG_(am_get_filename)( (NSegment*)seg );
- if (dev_name && 0 == VG_(strcmp)(dev_name, "/dev/zero")) {
- // Don't skip /dev/zero.
- } else {
- // Skip this device mapping.
- continue;
- }
- }
-
- if (0)
- VG_(printf)("ACCEPT %2d %#lx %#lx\n", i, seg->start, seg->end);
-
- // Scan the segment. We use -1 for the clique number, because this
- // is a root-set.
- seg_size = seg->end - seg->start + 1;
- if (VG_(clo_verbosity) > 2) {
- VG_(message)(Vg_DebugMsg,
- " Scanning root segment: %#lx..%#lx (%lu)\n",
- seg->start, seg->end, seg_size);
- }
- lc_scan_memory(seg->start, seg_size, /*is_prior_definite*/True, -1);
- }
- }
+ scan_memory_root_set(/*searched*/0, 0);
// Scan GP registers for chunk pointers.
VG_(apply_to_GP_regs)(lc_push_if_a_chunk_ptr_register);
@@ -1278,7 +1503,7 @@
// Push this Unreached block onto the stack and process it.
lc_push(i, ch);
- lc_process_markstack(i);
+ lc_process_markstack(/*clique*/i);
tl_assert(lc_markstack_top == -1);
tl_assert(ex->state == Unreached);
@@ -1287,11 +1512,65 @@
print_results( tid, lcp);
- VG_(free) ( lc_chunks );
- VG_(free) ( lc_extras );
VG_(free) ( lc_markstack );
+ lc_markstack = NULL;
+ // lc_chunks, lc_extras, lr_array and lr_table are kept (needed if user
+ // calls MC_(print_block_list)). lr_table also used for delta leak reporting
+ // between this leak search and the next leak search.
+}
+
+static Addr searched_wpa;
+static SizeT searched_szB;
+static void
+search_address_in_GP_reg(ThreadId tid, HChar* regname, Addr addr_in_reg)
+{
+ if (addr_in_reg >= searched_wpa
+ && addr_in_reg < searched_wpa + searched_szB) {
+ if (addr_in_reg == searched_wpa)
+ VG_(umsg)
+ ("tid %d register %s pointing at %#lx\n",
+ tid, regname, searched_wpa);
+ else
+ VG_(umsg)
+ ("tid %d register %s interior pointing %lu bytes inside %#lx\n",
+ tid, regname, (long unsigned) addr_in_reg - searched_wpa,
+ searched_wpa);
+ }
+}
+
+void MC_(who_points_at) ( Addr address, SizeT szB)
+{
+ MC_Chunk** chunks;
+ Int n_chunks;
+ Int i;
+
+ if (szB == 1)
+ VG_(umsg) ("Searching for pointers to %#lx\n", address);
+ else
+ VG_(umsg) ("Searching for pointers pointing in %lu bytes from %#lx\n",
+ szB, address);
+
+ // Scan memory root-set, searching for ptr pointing in address[szB]
+ scan_memory_root_set(address, szB);
+
+ // Scan active malloc-ed chunks
+ chunks = find_active_chunks(&n_chunks);
+ for (i = 0; i < n_chunks; i++) {
+ lc_scan_memory(chunks[i]->data, chunks[i]->szB,
+ /*is_prior_definite*/True,
+ /*clique*/-1, /*cur_clique*/-1,
+ address, szB);
+ }
+ VG_(free) ( chunks );
+
+ // Scan GP registers for pointers to address range.
+ searched_wpa = address;
+ searched_szB = szB;
+ VG_(apply_to_GP_regs)(search_address_in_GP_reg);
+
}
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
+
diff --git a/main/memcheck/mc_machine.c b/main/memcheck/mc_machine.c
index df84c5f..6ab257b 100644
--- a/main/memcheck/mc_machine.c
+++ b/main/memcheck/mc_machine.c
@@ -9,7 +9,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2008-2011 OpenWorks Ltd
+ Copyright (C) 2008-2012 OpenWorks Ltd
info@open-works.co.uk
This program is free software; you can redistribute it and/or
@@ -36,6 +36,7 @@
*/
#include "pub_tool_basics.h"
+#include "pub_tool_poolalloc.h" // For mc_include.h
#include "pub_tool_hashtable.h" // For mc_include.h
#include "pub_tool_libcassert.h"
#include "pub_tool_libcprint.h"
@@ -75,6 +76,11 @@
# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestARMState)
#endif
+#if defined(VGA_mips32)
+# include "libvex_guest_mips32.h"
+# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestMIPS32State)
+#endif
+
static inline Bool host_is_big_endian ( void ) {
UInt x = 0x11223344;
return 0x1122 == *(UShort*)(&x);
@@ -192,7 +198,8 @@
if (o == GOF(CIA) && sz == 8) return -1;
if (o == GOF(IP_AT_SYSCALL) && sz == 8) return -1; /* slot unused */
- if (o == GOF(FPROUND) && sz == 4) return -1;
+ if (o == GOF(FPROUND) && sz == 1) return -1;
+ if (o == GOF(DFPROUND) && sz == 1) return -1;
if (o == GOF(EMWARN) && sz == 4) return -1;
if (o == GOF(TISTART) && sz == 8) return -1;
if (o == GOF(TILEN) && sz == 8) return -1;
@@ -391,7 +398,8 @@
if (o == GOF(CIA) && sz == 4) return -1;
if (o == GOF(IP_AT_SYSCALL) && sz == 4) return -1; /* slot unused */
- if (o == GOF(FPROUND) && sz == 4) return -1;
+ if (o == GOF(FPROUND) && sz == 1) return -1;
+ if (o == GOF(DFPROUND) && sz == 1) return -1;
if (o == GOF(VRSAVE) && sz == 4) return -1;
if (o == GOF(EMWARN) && sz == 4) return -1;
if (o == GOF(TISTART) && sz == 4) return -1;
@@ -608,23 +616,23 @@
if (o == GOF(FC3210) && szB == 8) return -1;
/* XMM registers */
- if (o >= GOF(XMM0) && o+sz <= GOF(XMM0) +SZB(XMM0)) return GOF(XMM0);
- if (o >= GOF(XMM1) && o+sz <= GOF(XMM1) +SZB(XMM1)) return GOF(XMM1);
- if (o >= GOF(XMM2) && o+sz <= GOF(XMM2) +SZB(XMM2)) return GOF(XMM2);
- if (o >= GOF(XMM3) && o+sz <= GOF(XMM3) +SZB(XMM3)) return GOF(XMM3);
- if (o >= GOF(XMM4) && o+sz <= GOF(XMM4) +SZB(XMM4)) return GOF(XMM4);
- if (o >= GOF(XMM5) && o+sz <= GOF(XMM5) +SZB(XMM5)) return GOF(XMM5);
- if (o >= GOF(XMM6) && o+sz <= GOF(XMM6) +SZB(XMM6)) return GOF(XMM6);
- if (o >= GOF(XMM7) && o+sz <= GOF(XMM7) +SZB(XMM7)) return GOF(XMM7);
- if (o >= GOF(XMM8) && o+sz <= GOF(XMM8) +SZB(XMM8)) return GOF(XMM8);
- if (o >= GOF(XMM9) && o+sz <= GOF(XMM9) +SZB(XMM9)) return GOF(XMM9);
- if (o >= GOF(XMM10) && o+sz <= GOF(XMM10)+SZB(XMM10)) return GOF(XMM10);
- if (o >= GOF(XMM11) && o+sz <= GOF(XMM11)+SZB(XMM11)) return GOF(XMM11);
- if (o >= GOF(XMM12) && o+sz <= GOF(XMM12)+SZB(XMM12)) return GOF(XMM12);
- if (o >= GOF(XMM13) && o+sz <= GOF(XMM13)+SZB(XMM13)) return GOF(XMM13);
- if (o >= GOF(XMM14) && o+sz <= GOF(XMM14)+SZB(XMM14)) return GOF(XMM14);
- if (o >= GOF(XMM15) && o+sz <= GOF(XMM15)+SZB(XMM15)) return GOF(XMM15);
- if (o >= GOF(XMM16) && o+sz <= GOF(XMM16)+SZB(XMM16)) return GOF(XMM16);
+ if (o >= GOF(YMM0) && o+sz <= GOF(YMM0) +SZB(YMM0)) return GOF(YMM0);
+ if (o >= GOF(YMM1) && o+sz <= GOF(YMM1) +SZB(YMM1)) return GOF(YMM1);
+ if (o >= GOF(YMM2) && o+sz <= GOF(YMM2) +SZB(YMM2)) return GOF(YMM2);
+ if (o >= GOF(YMM3) && o+sz <= GOF(YMM3) +SZB(YMM3)) return GOF(YMM3);
+ if (o >= GOF(YMM4) && o+sz <= GOF(YMM4) +SZB(YMM4)) return GOF(YMM4);
+ if (o >= GOF(YMM5) && o+sz <= GOF(YMM5) +SZB(YMM5)) return GOF(YMM5);
+ if (o >= GOF(YMM6) && o+sz <= GOF(YMM6) +SZB(YMM6)) return GOF(YMM6);
+ if (o >= GOF(YMM7) && o+sz <= GOF(YMM7) +SZB(YMM7)) return GOF(YMM7);
+ if (o >= GOF(YMM8) && o+sz <= GOF(YMM8) +SZB(YMM8)) return GOF(YMM8);
+ if (o >= GOF(YMM9) && o+sz <= GOF(YMM9) +SZB(YMM9)) return GOF(YMM9);
+ if (o >= GOF(YMM10) && o+sz <= GOF(YMM10)+SZB(YMM10)) return GOF(YMM10);
+ if (o >= GOF(YMM11) && o+sz <= GOF(YMM11)+SZB(YMM11)) return GOF(YMM11);
+ if (o >= GOF(YMM12) && o+sz <= GOF(YMM12)+SZB(YMM12)) return GOF(YMM12);
+ if (o >= GOF(YMM13) && o+sz <= GOF(YMM13)+SZB(YMM13)) return GOF(YMM13);
+ if (o >= GOF(YMM14) && o+sz <= GOF(YMM14)+SZB(YMM14)) return GOF(YMM14);
+ if (o >= GOF(YMM15) && o+sz <= GOF(YMM15)+SZB(YMM15)) return GOF(YMM15);
+ if (o >= GOF(YMM16) && o+sz <= GOF(YMM16)+SZB(YMM16)) return GOF(YMM16);
/* MMX accesses to FP regs. Need to allow for 32-bit references
due to dirty helpers for frstor etc, which reference the entire
@@ -810,6 +818,7 @@
if (o == GOF(IP_AT_SYSCALL)) return -1;
if (o == GOF(fpc)) return -1;
if (o == GOF(IA)) return -1;
+ if (o == GOF(IA) + 4) return -1;
if (o == GOF(SYSNO)) return -1;
VG_(printf)("MC_(get_otrack_shadow_offset)(s390x)(off=%d,sz=%d)\n",
offset,szB);
@@ -935,6 +944,117 @@
# undef GOF
# undef SZB
+ /* --------------------- mips32 --------------------- */
+
+# elif defined(VGA_mips32)
+
+# define GOF(_fieldname) \
+ (offsetof(VexGuestMIPS32State,guest_##_fieldname))
+# define SZB(_fieldname) \
+ (sizeof(((VexGuestMIPS32State*)0)->guest_##_fieldname))
+
+ Int o = offset;
+ Int sz = szB;
+ tl_assert(sz > 0);
+# if defined (VG_LITTLEENDIAN)
+ tl_assert(host_is_little_endian());
+# elif defined (VG_BIGENDIAN)
+ tl_assert(host_is_big_endian());
+# else
+# error "Unknown endianness"
+# endif
+
+ if (o == GOF(r0) && sz == 4) return o;
+ if (o == GOF(r1) && sz == 4) return o;
+ if (o == GOF(r2) && sz == 4) return o;
+ if (o == GOF(r3) && sz == 4) return o;
+ if (o == GOF(r4) && sz == 4) return o;
+ if (o == GOF(r5) && sz == 4) return o;
+ if (o == GOF(r6) && sz == 4) return o;
+ if (o == GOF(r7) && sz == 4) return o;
+ if (o == GOF(r8) && sz == 4) return o;
+ if (o == GOF(r9) && sz == 4) return o;
+ if (o == GOF(r10) && sz == 4) return o;
+ if (o == GOF(r11) && sz == 4) return o;
+ if (o == GOF(r12) && sz == 4) return o;
+ if (o == GOF(r13) && sz == 4) return o;
+ if (o == GOF(r14) && sz == 4) return o;
+ if (o == GOF(r15) && sz == 4) return o;
+ if (o == GOF(r16) && sz == 4) return o;
+ if (o == GOF(r17) && sz == 4) return o;
+ if (o == GOF(r18) && sz == 4) return o;
+ if (o == GOF(r19) && sz == 4) return o;
+ if (o == GOF(r20) && sz == 4) return o;
+ if (o == GOF(r21) && sz == 4) return o;
+ if (o == GOF(r22) && sz == 4) return o;
+ if (o == GOF(r23) && sz == 4) return o;
+ if (o == GOF(r24) && sz == 4) return o;
+ if (o == GOF(r25) && sz == 4) return o;
+ if (o == GOF(r26) && sz == 4) return o;
+ if (o == GOF(r27) && sz == 4) return o;
+ if (o == GOF(r28) && sz == 4) return o;
+ if (o == GOF(r29) && sz == 4) return o;
+ if (o == GOF(r30) && sz == 4) return o;
+ if (o == GOF(r31) && sz == 4) return o;
+ if (o == GOF(PC) && sz == 4) return -1; /* slot unused */
+
+ if (o == GOF(HI) && sz == 4) return o;
+ if (o == GOF(LO) && sz == 4) return o;
+
+ if (o == GOF(FIR) && sz == 4) return -1; /* slot unused */
+ if (o == GOF(FCCR) && sz == 4) return -1; /* slot unused */
+ if (o == GOF(FEXR) && sz == 4) return -1; /* slot unused */
+ if (o == GOF(FENR) && sz == 4) return -1; /* slot unused */
+ if (o == GOF(FCSR) && sz == 4) return -1; /* slot unused */
+ if (o == GOF(ULR) && sz == 4) return -1;
+
+ if (o == GOF(EMWARN) && sz == 4) return -1; /* slot unused */
+ if (o == GOF(TISTART) && sz == 4) return -1; /* slot unused */
+ if (o == GOF(TILEN) && sz == 4) return -1; /* slot unused */
+ if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */
+
+ if (o >= GOF(f0) && o+sz <= GOF(f0) +SZB(f0)) return GOF(f0);
+ if (o >= GOF(f1) && o+sz <= GOF(f1) +SZB(f1)) return GOF(f1);
+ if (o >= GOF(f2) && o+sz <= GOF(f2) +SZB(f2)) return GOF(f2);
+ if (o >= GOF(f3) && o+sz <= GOF(f3) +SZB(f3)) return GOF(f3);
+ if (o >= GOF(f4) && o+sz <= GOF(f4) +SZB(f4)) return GOF(f4);
+ if (o >= GOF(f5) && o+sz <= GOF(f5) +SZB(f5)) return GOF(f5);
+ if (o >= GOF(f6) && o+sz <= GOF(f6) +SZB(f6)) return GOF(f6);
+ if (o >= GOF(f7) && o+sz <= GOF(f7) +SZB(f7)) return GOF(f7);
+ if (o >= GOF(f8) && o+sz <= GOF(f8) +SZB(f8)) return GOF(f8);
+ if (o >= GOF(f9) && o+sz <= GOF(f9) +SZB(f9)) return GOF(f9);
+ if (o >= GOF(f10) && o+sz <= GOF(f10)+SZB(f10)) return GOF(f10);
+ if (o >= GOF(f11) && o+sz <= GOF(f11)+SZB(f11)) return GOF(f11);
+ if (o >= GOF(f12) && o+sz <= GOF(f12)+SZB(f12)) return GOF(f12);
+ if (o >= GOF(f13) && o+sz <= GOF(f13)+SZB(f13)) return GOF(f13);
+ if (o >= GOF(f14) && o+sz <= GOF(f14)+SZB(f14)) return GOF(f14);
+ if (o >= GOF(f15) && o+sz <= GOF(f15)+SZB(f15)) return GOF(f15);
+
+ if (o >= GOF(f16) && o+sz <= GOF(f16)+SZB(f16)) return GOF(f16);
+ if (o >= GOF(f17) && o+sz <= GOF(f17) +SZB(f17)) return GOF(f17);
+ if (o >= GOF(f18) && o+sz <= GOF(f18) +SZB(f18)) return GOF(f18);
+ if (o >= GOF(f19) && o+sz <= GOF(f19) +SZB(f19)) return GOF(f19);
+ if (o >= GOF(f20) && o+sz <= GOF(f20) +SZB(f20)) return GOF(f20);
+ if (o >= GOF(f21) && o+sz <= GOF(f21) +SZB(f21)) return GOF(f21);
+ if (o >= GOF(f22) && o+sz <= GOF(f22) +SZB(f22)) return GOF(f22);
+ if (o >= GOF(f23) && o+sz <= GOF(f23) +SZB(f23)) return GOF(f23);
+ if (o >= GOF(f24) && o+sz <= GOF(f24) +SZB(f24)) return GOF(f24);
+ if (o >= GOF(f25) && o+sz <= GOF(f25) +SZB(f25)) return GOF(f25);
+ if (o >= GOF(f26) && o+sz <= GOF(f26)+SZB(f26)) return GOF(f26);
+ if (o >= GOF(f27) && o+sz <= GOF(f27)+SZB(f27)) return GOF(f27);
+ if (o >= GOF(f28) && o+sz <= GOF(f28)+SZB(f28)) return GOF(f28);
+ if (o >= GOF(f29) && o+sz <= GOF(f29)+SZB(f29)) return GOF(f29);
+ if (o >= GOF(f30) && o+sz <= GOF(f30)+SZB(f30)) return GOF(f30);
+ if (o >= GOF(f31) && o+sz <= GOF(f31)+SZB(f31)) return GOF(f31);
+
+ if ((o > GOF(NRADDR)) && (o <= GOF(NRADDR) +12 )) return -1; /*padding registers*/
+
+ VG_(printf)("MC_(get_otrack_shadow_offset)(mips)(off=%d,sz=%d)\n",
+ offset,szB);
+ tl_assert(0);
+# undef GOF
+# undef SZB
+
# else
# error "FIXME: not implemented for this architecture"
# endif
@@ -1018,7 +1138,6 @@
/* --------------------- arm --------------------- */
# elif defined(VGA_arm)
-
VG_(printf)("get_reg_array_equiv_int_type(arm): unhandled: ");
ppIRRegArray(arr);
VG_(printf)("\n");
@@ -1029,6 +1148,14 @@
/* Should never het here because s390x does not use Ist_PutI
and Iex_GetI. */
tl_assert(0);
+
+/* --------------------- mips32 --------------------- */
+# elif defined(VGA_mips32)
+ VG_(printf)("get_reg_array_equiv_int_type(mips32): unhandled: ");
+ ppIRRegArray(arr);
+ VG_(printf)("\n");
+ tl_assert(0);
+
# else
# error "FIXME: not implemented for this architecture"
# endif
diff --git a/main/memcheck/mc_main.c b/main/memcheck/mc_main.c
index 1d40411..44055ee 100644
--- a/main/memcheck/mc_main.c
+++ b/main/memcheck/mc_main.c
@@ -9,7 +9,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -33,6 +33,7 @@
#include "pub_tool_basics.h"
#include "pub_tool_aspacemgr.h"
#include "pub_tool_gdbserver.h"
+#include "pub_tool_poolalloc.h"
#include "pub_tool_hashtable.h" // For mc_include.h
#include "pub_tool_libcbase.h"
#include "pub_tool_libcassert.h"
@@ -49,15 +50,6 @@
#include "memcheck.h" /* for client requests */
-/* We really want this frame-pointer-less on all platforms, since the
- helper functions are small and called very frequently. By default
- on x86-linux, though, Makefile.all.am doesn't specify it, so do it
- here. Requires gcc >= 4.4, unfortunately. */
-#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
-# pragma GCC optimize("-fomit-frame-pointer")
-#endif
-
-
/* Set to 1 to do a little more sanity checking */
#define VG_DEBUG_MEMORY 0
@@ -175,10 +167,10 @@
#else
-/* Just handle the first 256G fast and the rest via auxiliary
+/* Just handle the first 32G fast and the rest via auxiliary
primaries. If you change this, Memcheck will assert at startup.
See the definition of UNALIGNED_OR_HIGH for extensive comments. */
-# define N_PRIMARY_BITS 22
+# define N_PRIMARY_BITS 19
#endif
@@ -836,16 +828,10 @@
//
// To avoid the stale nodes building up too much, we periodically (once the
// table reaches a certain size) garbage collect (GC) the table by
-// traversing it and evicting any "sufficiently stale" nodes, ie. nodes that
-// are stale and haven't been touched for a certain number of collections.
+// traversing it and evicting any nodes not having PDB.
// If more than a certain proportion of nodes survived, we increase the
// table size so that GCs occur less often.
//
-// (So this a bit different to a traditional GC, where you definitely want
-// to remove any dead nodes. It's more like we have a resizable cache and
-// we're trying to find the right balance how many elements to evict and how
-// big to make the cache.)
-//
// This policy is designed to avoid bad table bloat in the worst case where
// a program creates huge numbers of stale PDBs -- we would get this bloat
// if we had no GC -- while handling well the case where a node becomes
@@ -855,6 +841,27 @@
// lot of them in later again. The "sufficiently stale" approach avoids
// this. (If a program has many live PDBs, performance will just suck,
// there's no way around that.)
+//
+// Further comments, JRS 14 Feb 2012. It turns out that the policy of
+// holding on to stale entries for 2 GCs before discarding them can lead
+// to massive space leaks. So we're changing to an arrangement where
+// lines are evicted as soon as they are observed to be stale during a
+// GC. This also has a side benefit of allowing the sufficiently_stale
+// field to be removed from the SecVBitNode struct, reducing its size by
+// 8 bytes, which is a substantial space saving considering that the
+// struct was previously 32 or so bytes, on a 64 bit target.
+//
+// In order to try and mitigate the problem that the "sufficiently stale"
+// heuristic was designed to avoid, the table size is allowed to drift
+// up ("DRIFTUP") slowly to 80000, even if the residency is low. This
+// means that nodes will exist in the table longer on average, and hopefully
+// will be deleted and re-added less frequently.
+//
+// The previous scaling up mechanism (now called STEPUP) is retained:
+// if residency exceeds 50%, the table is scaled up, although by a
+// factor sqrt(2) rather than 2 as before. This effectively doubles the
+// frequency of GCs when there are many PDBs at reduces the tendency of
+// stale PDBs to reside for long periods in the table.
static OSet* secVBitTable;
@@ -871,19 +878,29 @@
// row), but often not. So we choose something intermediate.
#define BYTES_PER_SEC_VBIT_NODE 16
-// We make the table bigger if more than this many nodes survive a GC.
-#define MAX_SURVIVOR_PROPORTION 0.5
+// We make the table bigger by a factor of STEPUP_GROWTH_FACTOR if
+// more than this many nodes survive a GC.
+#define STEPUP_SURVIVOR_PROPORTION 0.5
+#define STEPUP_GROWTH_FACTOR 1.414213562
-// Each time we make the table bigger, we increase it by this much.
-#define TABLE_GROWTH_FACTOR 2
+// If the above heuristic doesn't apply, then we may make the table
+// slightly bigger, by a factor of DRIFTUP_GROWTH_FACTOR, if more than
+// this many nodes survive a GC, _and_ the total table size does
+// not exceed a fixed limit. The numbers are somewhat arbitrary, but
+// work tolerably well on long Firefox runs. The scaleup ratio of 1.5%
+// effectively although gradually reduces residency and increases time
+// between GCs for programs with small numbers of PDBs. The 80000 limit
+// effectively limits the table size to around 2MB for programs with
+// small numbers of PDBs, whilst giving a reasonably long lifetime to
+// entries, to try and reduce the costs resulting from deleting and
+// re-adding of entries.
+#define DRIFTUP_SURVIVOR_PROPORTION 0.15
+#define DRIFTUP_GROWTH_FACTOR 1.015
+#define DRIFTUP_MAX_SIZE 80000
-// This defines "sufficiently stale" -- any node that hasn't been touched in
-// this many GCs will be removed.
-#define MAX_STALE_AGE 2
-
// We GC the table when it gets this many nodes in it, ie. it's effectively
// the table size. It can change.
-static Int secVBitLimit = 1024;
+static Int secVBitLimit = 1000;
// The number of GCs done, used to age sec-V-bit nodes for eviction.
// Because it's unsigned, wrapping doesn't matter -- the right answer will
@@ -894,16 +911,20 @@
struct {
Addr a;
UChar vbits8[BYTES_PER_SEC_VBIT_NODE];
- UInt last_touched;
}
SecVBitNode;
static OSet* createSecVBitTable(void)
{
- return VG_(OSetGen_Create)( offsetof(SecVBitNode, a),
- NULL, // use fast comparisons
- VG_(malloc), "mc.cSVT.1 (sec VBit table)",
- VG_(free) );
+ OSet* newSecVBitTable;
+ newSecVBitTable = VG_(OSetGen_Create_With_Pool)
+ ( offsetof(SecVBitNode, a),
+ NULL, // use fast comparisons
+ VG_(malloc), "mc.cSVT.1 (sec VBit table)",
+ VG_(free),
+ 1000,
+ sizeof(SecVBitNode));
+ return newSecVBitTable;
}
static void gcSecVBitTable(void)
@@ -920,30 +941,20 @@
// Traverse the table, moving fresh nodes into the new table.
VG_(OSetGen_ResetIter)(secVBitTable);
while ( (n = VG_(OSetGen_Next)(secVBitTable)) ) {
- Bool keep = False;
- if ( (GCs_done - n->last_touched) <= MAX_STALE_AGE ) {
- // Keep node if it's been touched recently enough (regardless of
- // freshness/staleness).
- keep = True;
- } else {
- // Keep node if any of its bytes are non-stale. Using
- // get_vabits2() for the lookup is not very efficient, but I don't
- // think it matters.
- for (i = 0; i < BYTES_PER_SEC_VBIT_NODE; i++) {
- if (VA_BITS2_PARTDEFINED == get_vabits2(n->a + i)) {
- keep = True; // Found a non-stale byte, so keep
- break;
- }
+ // Keep node if any of its bytes are non-stale. Using
+ // get_vabits2() for the lookup is not very efficient, but I don't
+ // think it matters.
+ for (i = 0; i < BYTES_PER_SEC_VBIT_NODE; i++) {
+ if (VA_BITS2_PARTDEFINED == get_vabits2(n->a + i)) {
+ // Found a non-stale byte, so keep =>
+ // Insert a copy of the node into the new table.
+ SecVBitNode* n2 =
+ VG_(OSetGen_AllocNode)(secVBitTable2, sizeof(SecVBitNode));
+ *n2 = *n;
+ VG_(OSetGen_Insert)(secVBitTable2, n2);
+ break;
}
}
-
- if ( keep ) {
- // Insert a copy of the node into the new table.
- SecVBitNode* n2 =
- VG_(OSetGen_AllocNode)(secVBitTable2, sizeof(SecVBitNode));
- *n2 = *n;
- VG_(OSetGen_Insert)(secVBitTable2, n2);
- }
}
// Get the before and after sizes.
@@ -955,17 +966,29 @@
secVBitTable = secVBitTable2;
if (VG_(clo_verbosity) > 1) {
- Char percbuf[6];
+ Char percbuf[7];
VG_(percentify)(n_survivors, n_nodes, 1, 6, percbuf);
VG_(message)(Vg_DebugMsg, "memcheck GC: %d nodes, %d survivors (%s)\n",
n_nodes, n_survivors, percbuf);
}
// Increase table size if necessary.
- if (n_survivors > (secVBitLimit * MAX_SURVIVOR_PROPORTION)) {
- secVBitLimit *= TABLE_GROWTH_FACTOR;
+ if ((Double)n_survivors
+ > ((Double)secVBitLimit * STEPUP_SURVIVOR_PROPORTION)) {
+ secVBitLimit = (Int)((Double)secVBitLimit * (Double)STEPUP_GROWTH_FACTOR);
if (VG_(clo_verbosity) > 1)
- VG_(message)(Vg_DebugMsg, "memcheck GC: increase table size to %d\n",
+ VG_(message)(Vg_DebugMsg,
+ "memcheck GC: %d new table size (stepup)\n",
+ secVBitLimit);
+ }
+ else
+ if (secVBitLimit < DRIFTUP_MAX_SIZE
+ && (Double)n_survivors
+ > ((Double)secVBitLimit * DRIFTUP_SURVIVOR_PROPORTION)) {
+ secVBitLimit = (Int)((Double)secVBitLimit * (Double)DRIFTUP_GROWTH_FACTOR);
+ if (VG_(clo_verbosity) > 1)
+ VG_(message)(Vg_DebugMsg,
+ "memcheck GC: %d new table size (driftup)\n",
secVBitLimit);
}
}
@@ -994,9 +1017,14 @@
tl_assert(V_BITS8_DEFINED != vbits8 && V_BITS8_UNDEFINED != vbits8);
if (n) {
n->vbits8[amod] = vbits8; // update
- n->last_touched = GCs_done;
sec_vbits_updates++;
} else {
+ // Do a table GC if necessary. Nb: do this before creating and
+ // inserting the new node, to avoid erroneously GC'ing the new node.
+ if (secVBitLimit == VG_(OSetGen_Size)(secVBitTable)) {
+ gcSecVBitTable();
+ }
+
// New node: assign the specific byte, make the rest invalid (they
// should never be read as-is, but be cautious).
n = VG_(OSetGen_AllocNode)(secVBitTable, sizeof(SecVBitNode));
@@ -1005,13 +1033,6 @@
n->vbits8[i] = V_BITS8_UNDEFINED;
}
n->vbits8[amod] = vbits8;
- n->last_touched = GCs_done;
-
- // Do a table GC if necessary. Nb: do this before inserting the new
- // node, to avoid erroneously GC'ing the new node.
- if (secVBitLimit == VG_(OSetGen_Size)(secVBitTable)) {
- gcSecVBitTable();
- }
// Insert the new node.
VG_(OSetGen_Insert)(secVBitTable, n);
@@ -1111,19 +1132,6 @@
__attribute__((noinline))
ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian )
{
- /* Make up a 64-bit result V word, which contains the loaded data for
- valid addresses and Defined for invalid addresses. Iterate over
- the bytes in the word, from the most significant down to the
- least. */
- ULong vbits64 = V_BITS64_UNDEFINED;
- SizeT szB = nBits / 8;
- SSizeT i; // Must be signed.
- SizeT n_addrs_bad = 0;
- Addr ai;
- Bool partial_load_exemption_applies;
- UChar vbits8;
- Bool ok;
-
PROF_EVENT(30, "mc_LOADVn_slow");
/* ------------ BEGIN semi-fast cases ------------ */
@@ -1158,37 +1166,92 @@
}
/* ------------ END semi-fast cases ------------ */
+ ULong vbits64 = V_BITS64_UNDEFINED; /* result */
+ ULong pessim64 = V_BITS64_DEFINED; /* only used when p-l-ok=yes */
+ SSizeT szB = nBits / 8;
+ SSizeT i; /* Must be signed. */
+ SizeT n_addrs_bad = 0;
+ Addr ai;
+ UChar vbits8;
+ Bool ok;
+
tl_assert(nBits == 64 || nBits == 32 || nBits == 16 || nBits == 8);
+ /* Make up a 64-bit result V word, which contains the loaded data
+ for valid addresses and Defined for invalid addresses. Iterate
+ over the bytes in the word, from the most significant down to
+ the least. The vbits to return are calculated into vbits64.
+ Also compute the pessimising value to be used when
+ --partial-loads-ok=yes. n_addrs_bad is redundant (the relevant
+ info can be gleaned from pessim64) but is used as a
+ cross-check. */
for (i = szB-1; i >= 0; i--) {
PROF_EVENT(31, "mc_LOADVn_slow(loop)");
ai = a + byte_offset_w(szB, bigendian, i);
ok = get_vbits8(ai, &vbits8);
- if (!ok) n_addrs_bad++;
vbits64 <<= 8;
vbits64 |= vbits8;
+ if (!ok) n_addrs_bad++;
+ pessim64 <<= 8;
+ pessim64 |= (ok ? V_BITS8_DEFINED : V_BITS8_UNDEFINED);
}
- /* This is a hack which avoids producing errors for code which
- insists in stepping along byte strings in aligned word-sized
- chunks, and there is a partially defined word at the end. (eg,
- optimised strlen). Such code is basically broken at least WRT
- semantics of ANSI C, but sometimes users don't have the option
- to fix it, and so this option is provided. Note it is now
- defaulted to not-engaged.
+ /* In the common case, all the addresses involved are valid, so we
+ just return the computed V bits and have done. */
+ if (LIKELY(n_addrs_bad == 0))
+ return vbits64;
- A load from a partially-addressible place is allowed if:
- - the command-line flag is set
+ /* If there's no possibility of getting a partial-loads-ok
+ exemption, report the error and quit. */
+ if (!MC_(clo_partial_loads_ok)) {
+ MC_(record_address_error)( VG_(get_running_tid)(), a, szB, False );
+ return vbits64;
+ }
+
+ /* The partial-loads-ok excemption might apply. Find out if it
+ does. If so, don't report an addressing error, but do return
+ Undefined for the bytes that are out of range, so as to avoid
+ false negatives. If it doesn't apply, just report an addressing
+ error in the usual way. */
+
+ /* Some code steps along byte strings in aligned word-sized chunks
+ even when there is only a partially defined word at the end (eg,
+ optimised strlen). This is allowed by the memory model of
+ modern machines, since an aligned load cannot span two pages and
+ thus cannot "partially fault". Despite such behaviour being
+ declared undefined by ANSI C/C++.
+
+ Therefore, a load from a partially-addressible place is allowed
+ if all of the following hold:
+ - the command-line flag is set [by default, it isn't]
- it's a word-sized, word-aligned load
- at least one of the addresses in the word *is* valid
- */
- partial_load_exemption_applies
- = MC_(clo_partial_loads_ok) && szB == VG_WORDSIZE
- && VG_IS_WORD_ALIGNED(a)
- && n_addrs_bad < VG_WORDSIZE;
- if (n_addrs_bad > 0 && !partial_load_exemption_applies)
- MC_(record_address_error)( VG_(get_running_tid)(), a, szB, False );
+ Since this suppresses the addressing error, we avoid false
+ negatives by marking bytes undefined when they come from an
+ invalid address.
+ */
+
+ /* "at least one of the addresses is invalid" */
+ tl_assert(pessim64 != V_BITS64_DEFINED);
+
+ if (szB == VG_WORDSIZE && VG_IS_WORD_ALIGNED(a)
+ && n_addrs_bad < VG_WORDSIZE) {
+ /* Exemption applies. Use the previously computed pessimising
+ value for vbits64 and return the combined result, but don't
+ flag an addressing error. The pessimising value is Defined
+ for valid addresses and Undefined for invalid addresses. */
+ /* for assumption that doing bitwise or implements UifU */
+ tl_assert(V_BIT_UNDEFINED == 1 && V_BIT_DEFINED == 0);
+ /* (really need "UifU" here...)
+ vbits64 UifU= pessim64 (is pessimised by it, iow) */
+ vbits64 |= pessim64;
+ return vbits64;
+ }
+
+ /* Exemption doesn't apply. Flag an addressing error in the normal
+ way. */
+ MC_(record_address_error)( VG_(get_running_tid)(), a, szB, False );
return vbits64;
}
@@ -1460,7 +1523,8 @@
PROF_EVENT(160, "set_address_range_perms-loop64K-free-dist-sm");
// Free the non-distinguished sec-map that we're replacing. This
// case happens moderately often, enough to be worthwhile.
- VG_(am_munmap_valgrind)((Addr)*sm_ptr, sizeof(SecMap));
+ SysRes sres = VG_(am_munmap_valgrind)((Addr)*sm_ptr, sizeof(SecMap));
+ tl_assert2(! sr_isError(sres), "SecMap valgrind munmap failure\n");
}
update_SM_counts(*sm_ptr, example_dsm);
// Make the sec-map entry point to the example DSM
@@ -2144,7 +2208,7 @@
ocacheL2
= VG_(OSetGen_Create)( offsetof(OCacheLine,tag),
NULL, /* fast cmp */
- ocacheL2_malloc, "mc.ioL2", ocacheL2_free );
+ ocacheL2_malloc, "mc.ioL2", ocacheL2_free);
tl_assert(ocacheL2);
stats__ocacheL2_n_nodes = 0;
}
@@ -3854,19 +3918,19 @@
Int offset, SizeT size )
{
Int sh2off;
- UChar area[6];
+ UInt area[3];
UInt otag;
sh2off = MC_(get_otrack_shadow_offset)( offset, size );
if (sh2off == -1)
return 0; /* This piece of guest state is not tracked */
tl_assert(sh2off >= 0);
tl_assert(0 == (sh2off % 4));
- area[0] = 0x31;
- area[5] = 0x27;
- VG_(get_shadow_regs_area)( tid, &area[1], 2/*shadowno*/,sh2off,4 );
- tl_assert(area[0] == 0x31);
- tl_assert(area[5] == 0x27);
- otag = *(UInt*)&area[1];
+ area[0] = 0x31313131;
+ area[2] = 0x27272727;
+ VG_(get_shadow_regs_area)( tid, (UChar *)&area[1], 2/*shadowno*/,sh2off,4 );
+ tl_assert(area[0] == 0x31313131);
+ tl_assert(area[2] == 0x27272727);
+ otag = area[1];
return otag;
}
@@ -3879,7 +3943,7 @@
static void mc_post_reg_write ( CorePart part, ThreadId tid,
PtrdiffT offset, SizeT size)
{
-# define MAX_REG_WRITE_SIZE 1664
+# define MAX_REG_WRITE_SIZE 1696
UChar area[MAX_REG_WRITE_SIZE];
tl_assert(size <= MAX_REG_WRITE_SIZE);
VG_(memset)(area, V_BITS8_DEFINED, size);
@@ -4580,8 +4644,7 @@
Bool MC_(is_within_valid_secondary) ( Addr a )
{
SecMap* sm = maybe_get_secmap_for ( a );
- if (sm == NULL || sm == &sm_distinguished[SM_DIST_NOACCESS]
- || MC_(in_ignored_range)(a)) {
+ if (sm == NULL || sm == &sm_distinguished[SM_DIST_NOACCESS]) {
/* Definitely not in use. */
return False;
} else {
@@ -4596,12 +4659,16 @@
{
tl_assert(sizeof(UWord) == 4 || sizeof(UWord) == 8);
tl_assert(VG_IS_WORD_ALIGNED(a));
- if (is_mem_defined( a, sizeof(UWord), NULL, NULL) == MC_Ok
- && !MC_(in_ignored_range)(a)) {
- return True;
- } else {
+ if (get_vabits8_for_aligned_word32 (a) != VA_BITS8_DEFINED)
return False;
+ if (sizeof(UWord) == 8) {
+ if (get_vabits8_for_aligned_word32 (a + 4) != VA_BITS8_DEFINED)
+ return False;
}
+ if (UNLIKELY(MC_(in_ignored_range)(a)))
+ return False;
+ else
+ return True;
}
@@ -4769,8 +4836,6 @@
Int MC_(clo_malloc_fill) = -1;
Int MC_(clo_free_fill) = -1;
Int MC_(clo_mc_level) = 2;
-const char* MC_(clo_summary_file) = NULL;
-
static Bool mc_process_cmd_line_options(Char* arg)
{
@@ -4844,9 +4909,6 @@
else if VG_XACT_CLO(arg, "--leak-resolution=high",
MC_(clo_leak_resolution), Vg_HighRes) {}
- else if VG_STR_CLO(arg, "--summary-file", tmp_str) {
- MC_(clo_summary_file) = VG_(strdup)("clo_summary_file", tmp_str);
- }
else if VG_STR_CLO(arg, "--ignore-ranges", tmp_str) {
Int i;
Bool ok = parse_ignore_ranges(tmp_str);
@@ -5021,9 +5083,17 @@
" and outputs a description of <addr>\n"
" leak_check [full*|summary] [reachable|possibleleak*|definiteleak]\n"
" [increased*|changed|any]\n"
+" [unlimited*|limited <max_loss_records_output>]\n"
" * = defaults\n"
" Examples: leak_check\n"
" leak_check summary any\n"
+" leak_check full reachable any limited 100\n"
+" block_list <loss_record_nr>\n"
+" after a leak search, shows the list of blocks of <loss_record_nr>\n"
+" who_points_at <addr> [<len>]\n"
+" shows places pointing inside <len> (default 1) bytes at <addr>\n"
+" (with len 1, only shows \"start pointers\" pointing exactly to <addr>,\n"
+" with len > 1, will also show \"interior pointers\")\n"
"\n");
}
@@ -5041,7 +5111,8 @@
starts with the same first letter(s) as an already existing
command. This ensures a shorter abbreviation for the user. */
switch (VG_(keyword_id)
- ("help get_vbits leak_check make_memory check_memory",
+ ("help get_vbits leak_check make_memory check_memory "
+ "block_list who_points_at",
wcmd, kwd_report_duplicated_matches)) {
case -2: /* multiple matches */
return True;
@@ -5063,8 +5134,10 @@
(address+i, (Addr) &vbits, 1,
False, /* get them */
False /* is client request */ );
+ /* we are before the first character on next line, print a \n. */
if ((i % 32) == 0 && i != 0)
VG_(gdb_printf) ("\n");
+ /* we are before the next block of 4 starts, print a space. */
else if ((i % 4) == 0 && i != 0)
VG_(gdb_printf) (" ");
if (res == 1) {
@@ -5075,8 +5148,7 @@
VG_(gdb_printf) ("__");
}
}
- if ((i % 80) != 0)
- VG_(gdb_printf) ("\n");
+ VG_(gdb_printf) ("\n");
if (unaddressable) {
VG_(gdb_printf)
("Address %p len %ld has %d bytes unaddressable\n",
@@ -5094,6 +5166,7 @@
lcp.show_reachable = False;
lcp.show_possibly_lost = True;
lcp.deltamode = LCD_Increased;
+ lcp.max_loss_records_output = 999999999;
lcp.requested_by_monitor_command = True;
for (kw = VG_(strtok_r) (NULL, " ", &ssaveptr);
@@ -5102,7 +5175,8 @@
switch (VG_(keyword_id)
("full summary "
"reachable possibleleak definiteleak "
- "increased changed any",
+ "increased changed any "
+ "unlimited limited ",
kw, kwd_report_all)) {
case -2: err++; break;
case -1: err++; break;
@@ -5125,12 +5199,34 @@
lcp.deltamode = LCD_Changed; break;
case 7: /* any */
lcp.deltamode = LCD_Any; break;
+ case 8: /* unlimited */
+ lcp.max_loss_records_output = 999999999; break;
+ case 9: { /* limited */
+ int int_value;
+ char* endptr;
+
+ wcmd = VG_(strtok_r) (NULL, " ", &ssaveptr);
+ if (wcmd == NULL) {
+ int_value = 0;
+ endptr = "empty"; /* to report an error below */
+ } else {
+ int_value = VG_(strtoll10) (wcmd, (Char **)&endptr);
+ }
+ if (*endptr != '\0')
+ VG_(gdb_printf) ("missing or malformed integer value\n");
+ else if (int_value > 0)
+ lcp.max_loss_records_output = (UInt) int_value;
+ else
+ VG_(gdb_printf) ("max_loss_records_output must be >= 1, got %d\n",
+ int_value);
+ break;
+ }
default:
tl_assert (0);
}
}
if (!err)
- MC_(detect_memory_leaks)(tid, lcp);
+ MC_(detect_memory_leaks)(tid, &lcp);
return True;
}
@@ -5222,6 +5318,35 @@
return True;
}
+ case 5: { /* block_list */
+ Char* wl;
+ Char *endptr;
+ UInt lr_nr = 0;
+ wl = VG_(strtok_r) (NULL, " ", &ssaveptr);
+ lr_nr = VG_(strtoull10) (wl, &endptr);
+ if (wl != NULL && *endptr != '\0') {
+ VG_(gdb_printf) ("malformed integer\n");
+ } else {
+ // lr_nr-1 as what is shown to the user is 1 more than the index in lr_array.
+ if (lr_nr == 0 || ! MC_(print_block_list) (lr_nr-1))
+ VG_(gdb_printf) ("invalid loss record nr\n");
+ }
+ return True;
+ }
+
+ case 6: { /* who_points_at */
+ Addr address;
+ SizeT szB = 1;
+
+ VG_(strtok_get_address_and_size) (&address, &szB, &ssaveptr);
+ if (address == (Addr) 0) {
+ VG_(gdb_printf) ("Cannot search who points at 0x0\n");
+ return True;
+ }
+ MC_(who_points_at) (address, szB);
+ return True;
+ }
+
default:
tl_assert(0);
return False;
@@ -5321,9 +5446,10 @@
"Warning: unknown memcheck leak search deltamode\n");
lcp.deltamode = LCD_Any;
}
+ lcp.max_loss_records_output = 999999999;
lcp.requested_by_monitor_command = False;
- MC_(detect_memory_leaks)(tid, lcp);
+ MC_(detect_memory_leaks)(tid, &lcp);
*ret = 0; /* return value is meaningless */
break;
}
@@ -5334,7 +5460,7 @@
break;
case VG_USERREQ__MAKE_MEM_UNDEFINED:
- make_mem_undefined_w_tid_and_okind ( arg[1], arg[2], tid,
+ make_mem_undefined_w_tid_and_okind ( arg[1], arg[2], tid,
MC_OKIND_USER );
*ret = -1;
break;
@@ -5423,11 +5549,15 @@
case VG_USERREQ__MALLOCLIKE_BLOCK: {
Addr p = (Addr)arg[1];
SizeT sizeB = arg[2];
- //UInt rzB = arg[3]; XXX: unused!
+ UInt rzB = arg[3];
Bool is_zeroed = (Bool)arg[4];
MC_(new_block) ( tid, p, sizeB, /*ignored*/0, is_zeroed,
MC_AllocCustom, MC_(malloc_list) );
+ if (rzB > 0) {
+ MC_(make_mem_noaccess) ( p - rzB, rzB);
+ MC_(make_mem_noaccess) ( p + sizeB, rzB);
+ }
return True;
}
case VG_USERREQ__RESIZEINPLACE_BLOCK: {
@@ -5733,6 +5863,16 @@
return (UWord)oBoth;
}
+UWord VG_REGPARM(1) MC_(helperc_b_load32)( Addr a ) {
+ UInt oQ0 = (UInt)MC_(helperc_b_load8)( a + 0 );
+ UInt oQ1 = (UInt)MC_(helperc_b_load8)( a + 8 );
+ UInt oQ2 = (UInt)MC_(helperc_b_load8)( a + 16 );
+ UInt oQ3 = (UInt)MC_(helperc_b_load8)( a + 24 );
+ UInt oAll = merge_origins(merge_origins(oQ0, oQ1),
+ merge_origins(oQ2, oQ3));
+ return (UWord)oAll;
+}
+
/*--------------------------------------------*/
/*--- Origin tracking: store handlers ---*/
@@ -5845,6 +5985,13 @@
MC_(helperc_b_store8)( a + 8, d32 );
}
+void VG_REGPARM(2) MC_(helperc_b_store32)( Addr a, UWord d32 ) {
+ MC_(helperc_b_store8)( a + 0, d32 );
+ MC_(helperc_b_store8)( a + 8, d32 );
+ MC_(helperc_b_store8)( a + 16, d32 );
+ MC_(helperc_b_store8)( a + 24, d32 );
+}
+
/*--------------------------------------------*/
/*--- Origin tracking: sarp handlers ---*/
@@ -5921,7 +6068,14 @@
static void mc_post_clo_init ( void )
{
- // timurrrr: removed the check for VG_(clo_xml) here.
+ /* If we've been asked to emit XML, mash around various other
+ options so as to constrain the output somewhat. */
+ if (VG_(clo_xml)) {
+ /* Extract as much info as possible from the leak checker. */
+ /* MC_(clo_show_reachable) = True; */
+ MC_(clo_leak_check) = LC_Full;
+ }
+
if (MC_(clo_freelist_big_blocks) >= MC_(clo_freelist_vol))
VG_(message)(Vg_UserMsg,
"Warning: --freelist-big-blocks value %lld has no effect\n"
@@ -5971,6 +6125,10 @@
tl_assert(ocacheL1 == NULL);
tl_assert(ocacheL2 == NULL);
}
+
+ /* Do not check definedness of guest state if --undef-value-errors=no */
+ if (MC_(clo_mc_level) >= 2)
+ VG_(track_pre_reg_read) ( mc_pre_reg_read );
}
static void print_SM_info(char* type, int n_SMs)
@@ -5993,8 +6151,9 @@
lcp.show_reachable = MC_(clo_show_reachable);
lcp.show_possibly_lost = MC_(clo_show_possibly_lost);
lcp.deltamode = LCD_Any;
+ lcp.max_loss_records_output = 999999999;
lcp.requested_by_monitor_command = False;
- MC_(detect_memory_leaks)(1/*bogus ThreadId*/, lcp);
+ MC_(detect_memory_leaks)(1/*bogus ThreadId*/, &lcp);
} else {
if (VG_(clo_verbosity) == 1 && !VG_(clo_xml)) {
VG_(umsg)(
@@ -6050,10 +6209,13 @@
// Three DSMs, plus the non-DSM ones
max_SMs_szB = (3 + max_non_DSM_SMs) * sizeof(SecMap);
// The 3*sizeof(Word) bytes is the AVL node metadata size.
- // The 4*sizeof(Word) bytes is the malloc metadata size.
- // Hardwiring these sizes in sucks, but I don't see how else to do it.
+ // The VG_ROUNDUP is because the OSet pool allocator will/must align
+ // the elements on pointer size.
+ // Note that the pool allocator has some additional small overhead
+ // which is not counted in the below.
+ // Hardwiring this logic sucks, but I don't see how else to do it.
max_secVBit_szB = max_secVBit_nodes *
- (sizeof(SecVBitNode) + 3*sizeof(Word) + 4*sizeof(Word));
+ (3*sizeof(Word) + VG_ROUNDUP(sizeof(SecVBitNode), sizeof(void*)));
max_shmem_szB = sizeof(primary_map) + max_SMs_szB + max_secVBit_szB;
VG_(message)(Vg_DebugMsg,
@@ -6134,7 +6296,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("a memory error detector");
VG_(details_copyright_author)(
- "Copyright (C) 2002-2011, and GNU GPL'd, by Julian Seward et al.");
+ "Copyright (C) 2002-2012, and GNU GPL'd, by Julian Seward et al.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 640 );
@@ -6173,7 +6335,8 @@
MC_(__builtin_vec_delete),
MC_(realloc),
MC_(malloc_usable_size),
- MC_MALLOC_REDZONE_SZB );
+ MC_MALLOC_DEFAULT_REDZONE_SZB );
+ MC_(Malloc_Redzone_SzB) = VG_(malloc_effective_client_redzone_size)();
VG_(needs_xml_output) ();
@@ -6267,15 +6430,17 @@
VG_(track_pre_mem_write) ( check_mem_is_addressable );
VG_(track_post_mem_write) ( mc_post_mem_write );
- if (MC_(clo_mc_level) >= 2)
- VG_(track_pre_reg_read) ( mc_pre_reg_read );
-
VG_(track_post_reg_write) ( mc_post_reg_write );
VG_(track_post_reg_write_clientcall_return)( mc_post_reg_write_clientcall );
VG_(needs_watchpoint) ( mc_mark_unaddressable_for_watchpoint );
init_shadow_memory();
+ MC_(chunk_poolalloc) = VG_(newPA) (sizeof(MC_Chunk),
+ 1000,
+ VG_(malloc),
+ "mc.cMC.1 (MC_Chunk pools)",
+ VG_(free));
MC_(malloc_list) = VG_(HT_construct)( "MC_(malloc_list)" );
MC_(mempool_list) = VG_(HT_construct)( "MC_(mempool_list)" );
init_prof_mem();
@@ -6317,11 +6482,11 @@
tl_assert(sizeof(Addr) == 8);
tl_assert(sizeof(UWord) == 8);
tl_assert(sizeof(Word) == 8);
- tl_assert(MAX_PRIMARY_ADDRESS == 0x3FFFFFFFFFULL);
- tl_assert(MASK(1) == 0xFFFFFFC000000000ULL);
- tl_assert(MASK(2) == 0xFFFFFFC000000001ULL);
- tl_assert(MASK(4) == 0xFFFFFFC000000003ULL);
- tl_assert(MASK(8) == 0xFFFFFFC000000007ULL);
+ tl_assert(MAX_PRIMARY_ADDRESS == 0x7FFFFFFFFULL);
+ tl_assert(MASK(1) == 0xFFFFFFF800000000ULL);
+ tl_assert(MASK(2) == 0xFFFFFFF800000001ULL);
+ tl_assert(MASK(4) == 0xFFFFFFF800000003ULL);
+ tl_assert(MASK(8) == 0xFFFFFFF800000007ULL);
# endif
}
diff --git a/main/memcheck/mc_malloc_wrappers.c b/main/memcheck/mc_malloc_wrappers.c
index db3fc9f..ca45c47 100644
--- a/main/memcheck/mc_malloc_wrappers.c
+++ b/main/memcheck/mc_malloc_wrappers.c
@@ -8,7 +8,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -31,6 +31,7 @@
#include "pub_tool_basics.h"
#include "pub_tool_execontext.h"
+#include "pub_tool_poolalloc.h"
#include "pub_tool_hashtable.h"
#include "pub_tool_libcbase.h"
#include "pub_tool_libcassert.h"
@@ -62,13 +63,23 @@
/*--- Tracking malloc'd and free'd blocks ---*/
/*------------------------------------------------------------*/
+SizeT MC_(Malloc_Redzone_SzB) = -10000000; // If used before set, should BOMB
+
/* Record malloc'd blocks. */
VgHashTable MC_(malloc_list) = NULL;
/* Memory pools: a hash table of MC_Mempools. Search key is
MC_Mempool::pool. */
VgHashTable MC_(mempool_list) = NULL;
-
+
+/* Pool allocator for MC_Chunk. */
+PoolAlloc *MC_(chunk_poolalloc) = NULL;
+static
+MC_Chunk* create_MC_Chunk ( ExeContext* ec, Addr p, SizeT szB,
+ MC_AllocKind kind);
+static inline
+void delete_MC_Chunk (MC_Chunk* mc);
+
/* Records blocks after freeing. */
/* Blocks freed by the client are queued in one of two lists of
freed blocks not yet physically freed:
@@ -131,6 +142,7 @@
while (VG_(free_queue_volume) > MC_(clo_freelist_vol)
&& freed_list_start[i] != NULL) {
MC_Chunk* mc1;
+
tl_assert(freed_list_end[i] != NULL);
mc1 = freed_list_start[i];
@@ -147,11 +159,12 @@
freed_list_start[i] = mc1->next;
}
mc1->next = NULL; /* just paranoia */
+
/* free MC_Chunk */
if (MC_AllocCustom != mc1->allockind)
VG_(cli_free) ( (void*)(mc1->data) );
- VG_(free) ( mc1 );
- }
+ delete_MC_Chunk ( mc1 );
+ }
}
}
@@ -163,7 +176,7 @@
mc = freed_list_start[i];
while (mc) {
if (VG_(addr_is_in_block)( a, mc->data, mc->szB,
- MC_MALLOC_REDZONE_SZB ))
+ MC_(Malloc_Redzone_SzB) ))
return mc;
mc = mc->next;
}
@@ -177,7 +190,7 @@
MC_Chunk* create_MC_Chunk ( ExeContext* ec, Addr p, SizeT szB,
MC_AllocKind kind)
{
- MC_Chunk* mc = VG_(malloc)("mc.cMC.1 (a MC_Chunk)", sizeof(MC_Chunk));
+ MC_Chunk* mc = VG_(allocEltPA)(MC_(chunk_poolalloc));
mc->data = p;
mc->szB = szB;
mc->allockind = kind;
@@ -198,6 +211,12 @@
return mc;
}
+static inline
+void delete_MC_Chunk (MC_Chunk* mc)
+{
+ VG_(freeEltPA) (MC_(chunk_poolalloc), mc);
+}
+
/*------------------------------------------------------------*/
/*--- client_malloc(), etc ---*/
/*------------------------------------------------------------*/
@@ -236,8 +255,6 @@
{
ExeContext* ec;
- cmalloc_n_mallocs ++;
-
// Allocate and zero if necessary
if (p) {
tl_assert(MC_AllocCustom == kind);
@@ -256,7 +273,8 @@
}
}
- // Only update this stat if allocation succeeded.
+ // Only update stats if allocation succeeded.
+ cmalloc_n_mallocs ++;
cmalloc_bs_mallocd += (ULong)szB;
ec = VG_(record_ExeContext)(tid, 0/*first_ip_delta*/);
@@ -328,7 +346,9 @@
static
void die_and_free_mem ( ThreadId tid, MC_Chunk* mc, SizeT rzB )
{
- if (MC_(clo_free_fill) != -1) {
+ /* Note: we do not free fill the custom allocs produced
+ by MEMPOOL or by MALLOC/FREELIKE_BLOCK requests. */
+ if (MC_(clo_free_fill) != -1 && MC_AllocCustom != mc->allockind ) {
tl_assert(MC_(clo_free_fill) >= 0x00 && MC_(clo_free_fill) <= 0xFF);
VG_(memset)((void*)mc->data, MC_(clo_free_fill), mc->szB);
}
@@ -369,19 +389,19 @@
void MC_(free) ( ThreadId tid, void* p )
{
MC_(handle_free)(
- tid, (Addr)p, MC_MALLOC_REDZONE_SZB, MC_AllocMalloc );
+ tid, (Addr)p, MC_(Malloc_Redzone_SzB), MC_AllocMalloc );
}
void MC_(__builtin_delete) ( ThreadId tid, void* p )
{
MC_(handle_free)(
- tid, (Addr)p, MC_MALLOC_REDZONE_SZB, MC_AllocNew);
+ tid, (Addr)p, MC_(Malloc_Redzone_SzB), MC_AllocNew);
}
void MC_(__builtin_vec_delete) ( ThreadId tid, void* p )
{
MC_(handle_free)(
- tid, (Addr)p, MC_MALLOC_REDZONE_SZB, MC_AllocNewVec);
+ tid, (Addr)p, MC_(Malloc_Redzone_SzB), MC_AllocNewVec);
}
void* MC_(realloc) ( ThreadId tid, void* p_old, SizeT new_szB )
@@ -390,13 +410,13 @@
void* p_new;
SizeT old_szB;
+ if (complain_about_silly_args(new_szB, "realloc"))
+ return NULL;
+
cmalloc_n_frees ++;
cmalloc_n_mallocs ++;
cmalloc_bs_mallocd += (ULong)new_szB;
- if (complain_about_silly_args(new_szB, "realloc"))
- return NULL;
-
/* Remove the old block */
mc = VG_(HT_remove) ( MC_(malloc_list), (UWord)p_old );
if (mc == NULL) {
@@ -436,10 +456,10 @@
tl_assert(ec);
/* Retained part is copied, red zones set as normal */
- MC_(make_mem_noaccess)( a_new-MC_MALLOC_REDZONE_SZB,
- MC_MALLOC_REDZONE_SZB );
+ MC_(make_mem_noaccess)( a_new-MC_(Malloc_Redzone_SzB),
+ MC_(Malloc_Redzone_SzB) );
MC_(copy_address_range_state) ( (Addr)p_old, a_new, new_szB );
- MC_(make_mem_noaccess) ( a_new+new_szB, MC_MALLOC_REDZONE_SZB );
+ MC_(make_mem_noaccess) ( a_new+new_szB, MC_(Malloc_Redzone_SzB));
/* Copy from old to new */
VG_(memcpy)((void*)a_new, p_old, new_szB);
@@ -454,7 +474,7 @@
/* Nb: we have to allocate a new MC_Chunk for the new memory rather
than recycling the old one, so that any erroneous accesses to the
old memory are reported. */
- die_and_free_mem ( tid, mc, MC_MALLOC_REDZONE_SZB );
+ die_and_free_mem ( tid, mc, MC_(Malloc_Redzone_SzB) );
// Allocate a new chunk.
mc = create_MC_Chunk( ec, a_new, new_szB, MC_AllocMalloc );
@@ -479,12 +499,12 @@
tl_assert(VG_(is_plausible_ECU)(ecu));
/* First half kept and copied, second half new, red zones as normal */
- MC_(make_mem_noaccess)( a_new-MC_MALLOC_REDZONE_SZB,
- MC_MALLOC_REDZONE_SZB );
+ MC_(make_mem_noaccess)( a_new-MC_(Malloc_Redzone_SzB),
+ MC_(Malloc_Redzone_SzB) );
MC_(copy_address_range_state) ( (Addr)p_old, a_new, mc->szB );
MC_(make_mem_undefined_w_otag)( a_new+mc->szB, new_szB-mc->szB,
ecu | MC_OKIND_HEAP );
- MC_(make_mem_noaccess) ( a_new+new_szB, MC_MALLOC_REDZONE_SZB );
+ MC_(make_mem_noaccess) ( a_new+new_szB, MC_(Malloc_Redzone_SzB) );
/* Possibly fill new area with specified junk */
if (MC_(clo_malloc_fill) != -1) {
@@ -507,7 +527,7 @@
/* Nb: we have to allocate a new MC_Chunk for the new memory rather
than recycling the old one, so that any erroneous accesses to the
old memory are reported. */
- die_and_free_mem ( tid, mc, MC_MALLOC_REDZONE_SZB );
+ die_and_free_mem ( tid, mc, MC_(Malloc_Redzone_SzB) );
// Allocate a new chunk.
mc = create_MC_Chunk( ec, a_new, new_szB, MC_AllocMalloc );
@@ -641,7 +661,7 @@
MC_(make_mem_noaccess)(mc->data-mp->rzB, mc->szB + 2*mp->rzB );
}
// Destroy the chunk table
- VG_(HT_destruct)(mp->chunks);
+ VG_(HT_destruct)(mp->chunks, (void (*)(void *))delete_MC_Chunk);
VG_(free)(mp);
}
@@ -749,6 +769,14 @@
if (MP_DETAILED_SANITY_CHECKS) check_mempool_sane(mp);
MC_(new_block)(tid, addr, szB, /*ignored*/0, mp->is_zeroed,
MC_AllocCustom, mp->chunks);
+ if (mp->rzB > 0) {
+ // This is not needed if the user application has properly
+ // marked the superblock noaccess when defining the mempool.
+ // We however still mark the redzones noaccess to still catch
+ // some bugs if user forgot.
+ MC_(make_mem_noaccess) ( addr - mp->rzB, mp->rzB);
+ MC_(make_mem_noaccess) ( addr + szB, mp->rzB);
+ }
if (MP_DETAILED_SANITY_CHECKS) check_mempool_sane(mp);
}
}
@@ -1002,6 +1030,12 @@
);
}
+SizeT MC_(get_cmalloc_n_frees) ( void )
+{
+ return cmalloc_n_frees;
+}
+
+
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
diff --git a/main/memcheck/mc_replace_strmem.c b/main/memcheck/mc_replace_strmem.c
index 6d2deb3..02072da 100644
--- a/main/memcheck/mc_replace_strmem.c
+++ b/main/memcheck/mc_replace_strmem.c
@@ -9,7 +9,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -31,6 +31,7 @@
*/
#include "pub_tool_basics.h"
+#include "pub_tool_poolalloc.h"
#include "pub_tool_hashtable.h"
#include "pub_tool_redir.h"
#include "pub_tool_tooliface.h"
@@ -94,6 +95,8 @@
20330 STRCSPN
20340 STRSPN
20350 STRCASESTR
+ 20360 MEMRCHR
+ 20370 WCSLEN
*/
@@ -140,6 +143,9 @@
# if defined(VGPV_arm_linux_android)
__asm__ __volatile__(".word 0xFFFFFFFF");
while (1) {}
+# elif defined(VGPV_x86_linux_android)
+ __asm__ __volatile__("ud2");
+ while (1) {}
# else
extern __attribute__ ((__noreturn__)) void _exit(int status);
_exit(x);
@@ -177,12 +183,15 @@
STRRCHR(VG_Z_LIBC_SONAME, rindex)
STRRCHR(VG_Z_LIBC_SONAME, __GI_strrchr)
STRRCHR(VG_Z_LD_LINUX_SO_2, rindex)
+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
+ STRRCHR(NONE, __dl_strrchr); /* in /system/bin/linker */
+#endif
#elif defined(VGO_darwin)
//STRRCHR(VG_Z_LIBC_SONAME, strrchr)
- STRRCHR(VG_Z_LIBC_SONAME, rindex)
- STRRCHR(VG_Z_DYLD, strrchr)
- STRRCHR(VG_Z_DYLD, rindex)
+ //STRRCHR(VG_Z_LIBC_SONAME, rindex)
+ //STRRCHR(VG_Z_DYLD, strrchr)
+ //STRRCHR(VG_Z_DYLD, rindex)
STRRCHR(VG_Z_LIBC_SONAME, strrchr)
#endif
@@ -217,9 +226,9 @@
#elif defined(VGO_darwin)
//STRCHR(VG_Z_LIBC_SONAME, strchr)
- STRCHR(VG_Z_LIBC_SONAME, index)
- STRCHR(VG_Z_DYLD, strchr)
- STRCHR(VG_Z_DYLD, index)
+ //STRCHR(VG_Z_LIBC_SONAME, index)
+ //STRCHR(VG_Z_DYLD, strchr)
+ //STRCHR(VG_Z_DYLD, index)
STRCHR(VG_Z_LIBC_SONAME, strchr)
#endif
@@ -255,7 +264,7 @@
STRCAT(VG_Z_LIBC_SONAME, __GI_strcat)
#elif defined(VGO_darwin)
- STRCAT(VG_Z_LIBC_SONAME, strcat)
+ //STRCAT(VG_Z_LIBC_SONAME, strcat)
#endif
@@ -291,8 +300,8 @@
STRNCAT(VG_Z_LIBC_SONAME, strncat)
#elif defined(VGO_darwin)
- STRNCAT(VG_Z_LIBC_SONAME, strncat)
- STRNCAT(VG_Z_DYLD, strncat)
+ //STRNCAT(VG_Z_LIBC_SONAME, strncat)
+ //STRNCAT(VG_Z_DYLD, strncat)
#endif
@@ -339,7 +348,7 @@
#elif defined(VGO_darwin)
//STRLCAT(VG_Z_LIBC_SONAME, strlcat)
- STRLCAT(VG_Z_DYLD, strlcat)
+ //STRLCAT(VG_Z_DYLD, strlcat)
STRLCAT(VG_Z_LIBC_SONAME, strlcat)
#endif
@@ -363,7 +372,7 @@
STRNLEN(VG_Z_LIBC_SONAME, __GI_strnlen)
#elif defined(VGO_darwin)
- STRNLEN(VG_Z_LIBC_SONAME, strnlen)
+ //STRNLEN(VG_Z_LIBC_SONAME, strnlen)
#endif
@@ -389,7 +398,7 @@
#if defined(VGO_linux)
STRLEN(VG_Z_LIBC_SONAME, strlen)
STRLEN(VG_Z_LIBC_SONAME, __GI_strlen)
-# if defined(VGPV_arm_linux_android)
+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
STRLEN(NONE, __dl_strlen); /* in /system/bin/linker */
# endif
@@ -431,7 +440,7 @@
#elif defined(VGO_darwin)
//STRCPY(VG_Z_LIBC_SONAME, strcpy)
- STRCPY(VG_Z_DYLD, strcpy)
+ //STRCPY(VG_Z_DYLD, strcpy)
STRCPY(VG_Z_LIBC_SONAME, strcpy)
#endif
@@ -465,7 +474,7 @@
#elif defined(VGO_darwin)
//STRNCPY(VG_Z_LIBC_SONAME, strncpy)
- STRNCPY(VG_Z_DYLD, strncpy)
+ //STRNCPY(VG_Z_DYLD, strncpy)
STRNCPY(VG_Z_LIBC_SONAME, strncpy)
#endif
@@ -500,9 +509,13 @@
#if defined(VGO_linux)
+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
+ STRLCPY(VG_Z_LIBC_SONAME, strlcpy);
+#endif
+
#elif defined(VGO_darwin)
//STRLCPY(VG_Z_LIBC_SONAME, strlcpy)
- STRLCPY(VG_Z_DYLD, strlcpy)
+ //STRLCPY(VG_Z_DYLD, strlcpy)
STRLCPY(VG_Z_LIBC_SONAME, strlcpy)
#endif
@@ -536,7 +549,7 @@
#elif defined(VGO_darwin)
//STRNCMP(VG_Z_LIBC_SONAME, strncmp)
- STRNCMP(VG_Z_DYLD, strncmp)
+ //STRNCMP(VG_Z_DYLD, strncmp)
STRNCMP(VG_Z_LIBC_SONAME, strncmp)
#endif
@@ -566,13 +579,13 @@
}
#if defined(VGO_linux)
-# if !defined(VGPV_arm_linux_android)
+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android)
STRCASECMP(VG_Z_LIBC_SONAME, strcasecmp)
STRCASECMP(VG_Z_LIBC_SONAME, __GI_strcasecmp)
# endif
#elif defined(VGO_darwin)
- STRCASECMP(VG_Z_LIBC_SONAME, strcasecmp)
+ //STRCASECMP(VG_Z_LIBC_SONAME, strcasecmp)
#endif
@@ -603,14 +616,14 @@
}
#if defined(VGO_linux)
-# if !defined(VGPV_arm_linux_android)
+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android)
STRNCASECMP(VG_Z_LIBC_SONAME, strncasecmp)
STRNCASECMP(VG_Z_LIBC_SONAME, __GI_strncasecmp)
# endif
#elif defined(VGO_darwin)
- STRNCASECMP(VG_Z_LIBC_SONAME, strncasecmp)
- STRNCASECMP(VG_Z_DYLD, strncasecmp)
+ //STRNCASECMP(VG_Z_LIBC_SONAME, strncasecmp)
+ //STRNCASECMP(VG_Z_DYLD, strncasecmp)
#endif
@@ -644,7 +657,7 @@
STRCASECMP_L(VG_Z_LIBC_SONAME, __GI___strcasecmp_l)
#elif defined(VGO_darwin)
- STRCASECMP_L(VG_Z_LIBC_SONAME, strcasecmp_l)
+ //STRCASECMP_L(VG_Z_LIBC_SONAME, strcasecmp_l)
#endif
@@ -677,10 +690,11 @@
#if defined(VGO_linux)
STRNCASECMP_L(VG_Z_LIBC_SONAME, strncasecmp_l)
STRNCASECMP_L(VG_Z_LIBC_SONAME, __GI_strncasecmp_l)
+ STRNCASECMP_L(VG_Z_LIBC_SONAME, __GI___strncasecmp_l)
#elif defined(VGO_darwin)
- STRNCASECMP_L(VG_Z_LIBC_SONAME, strncasecmp_l)
- STRNCASECMP_L(VG_Z_DYLD, strncasecmp_l)
+ //STRNCASECMP_L(VG_Z_LIBC_SONAME, strncasecmp_l)
+ //STRNCASECMP_L(VG_Z_DYLD, strncasecmp_l)
#endif
@@ -712,7 +726,7 @@
STRCMP(VG_Z_LIBC_SONAME, __GI_strcmp)
STRCMP(VG_Z_LD_LINUX_X86_64_SO_2, strcmp)
STRCMP(VG_Z_LD64_SO_1, strcmp)
-# if defined(VGPV_arm_linux_android)
+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)
STRCMP(NONE, __dl_strcmp); /* in /system/bin/linker */
# endif
@@ -743,8 +757,34 @@
MEMCHR(VG_Z_LIBC_SONAME, memchr)
#elif defined(VGO_darwin)
- MEMCHR(VG_Z_LIBC_SONAME, memchr)
- MEMCHR(VG_Z_DYLD, memchr)
+ //MEMCHR(VG_Z_LIBC_SONAME, memchr)
+ //MEMCHR(VG_Z_DYLD, memchr)
+
+#endif
+
+
+/*---------------------- memrchr ----------------------*/
+
+#define MEMRCHR(soname, fnname) \
+ void* VG_REPLACE_FUNCTION_EZU(20360,soname,fnname) \
+ (const void *s, int c, SizeT n); \
+ void* VG_REPLACE_FUNCTION_EZU(20360,soname,fnname) \
+ (const void *s, int c, SizeT n) \
+ { \
+ SizeT i; \
+ UChar c0 = (UChar)c; \
+ UChar* p = (UChar*)s; \
+ for (i = 0; i < n; i++) \
+ if (p[n-1-i] == c0) return (void*)(&p[n-1-i]); \
+ return NULL; \
+ }
+
+#if defined(VGO_linux)
+ MEMRCHR(VG_Z_LIBC_SONAME, memrchr)
+
+#elif defined(VGO_darwin)
+ //MEMRCHR(VG_Z_LIBC_SONAME, memrchr)
+ //MEMRCHR(VG_Z_DYLD, memrchr)
#endif
@@ -849,9 +889,9 @@
MEMCPY(NONE, ZuintelZufastZumemcpy)
#elif defined(VGO_darwin)
- // glider: see https://bugs.kde.org/show_bug.cgi?id=285662
- MEMCPY(VG_Z_LIBC_SONAME, memcpy)
- MEMCPY(VG_Z_DYLD, memcpy)
+# if DARWIN_VERS <= DARWIN_10_6
+ MEMCPY(VG_Z_LIBC_SONAME, memcpy)
+# endif
MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse3x) /* memcpy$VARIANT$sse3x */
MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse42) /* memcpy$VARIANT$sse42 */
@@ -891,10 +931,10 @@
MEMCMP(VG_Z_LD_SO_1, bcmp)
#elif defined(VGO_darwin)
- MEMCMP(VG_Z_LIBC_SONAME, memcmp)
- MEMCMP(VG_Z_LIBC_SONAME, bcmp)
- MEMCMP(VG_Z_DYLD, memcmp)
- MEMCMP(VG_Z_DYLD, bcmp)
+ //MEMCMP(VG_Z_LIBC_SONAME, memcmp)
+ //MEMCMP(VG_Z_LIBC_SONAME, bcmp)
+ //MEMCMP(VG_Z_DYLD, memcmp)
+ //MEMCMP(VG_Z_DYLD, bcmp)
#endif
@@ -933,8 +973,8 @@
STPCPY(VG_Z_LD_LINUX_X86_64_SO_2, stpcpy)
#elif defined(VGO_darwin)
- STPCPY(VG_Z_LIBC_SONAME, stpcpy)
- STPCPY(VG_Z_DYLD, stpcpy)
+ //STPCPY(VG_Z_LIBC_SONAME, stpcpy)
+ //STPCPY(VG_Z_DYLD, stpcpy)
#endif
@@ -968,7 +1008,7 @@
#elif defined(VGO_darwin)
//MEMSET(VG_Z_LIBC_SONAME, memset)
- MEMSET(VG_Z_DYLD, memset)
+ //MEMSET(VG_Z_DYLD, memset)
MEMSET(VG_Z_LIBC_SONAME, memset)
#endif
@@ -980,11 +1020,12 @@
#if defined(VGO_linux)
MEMMOVE(VG_Z_LIBC_SONAME, memmove)
+ MEMMOVE(VG_Z_LIBC_SONAME, __GI_memmove)
#elif defined(VGO_darwin)
- // glider: see https://bugs.kde.org/show_bug.cgi?id=285662
- MEMMOVE(VG_Z_LIBC_SONAME, memmove)
- MEMMOVE(VG_Z_DYLD, memmove)
+# if DARWIN_VERS <= DARWIN_10_6
+ MEMMOVE(VG_Z_LIBC_SONAME, memmove)
+# endif
MEMMOVE(VG_Z_LIBC_SONAME, memmoveZDVARIANTZDsse3x) /* memmove$VARIANT$sse3x */
MEMMOVE(VG_Z_LIBC_SONAME, memmoveZDVARIANTZDsse42) /* memmove$VARIANT$sse42 */
@@ -1013,15 +1054,15 @@
} \
}
-// kcc: enabled bcopy interceptor on non-mac targets.
-BCOPY(VG_Z_LIBC_SONAME, bcopy)
#if defined(VGO_linux)
#elif defined(VGO_darwin)
//BCOPY(VG_Z_LIBC_SONAME, bcopy)
- BCOPY(VG_Z_DYLD, bcopy)
+ //BCOPY(VG_Z_DYLD, bcopy)
+
#endif
+
/*-------------------- memmove_chk --------------------*/
/* glibc 2.5 variant of memmove which checks the dest is big enough.
@@ -1223,7 +1264,7 @@
GLIBC25_MEMPCPY(VG_Z_LD_SO_1, mempcpy) /* ld.so.1 */
#elif defined(VGO_darwin)
- GLIBC25_MEMPCPY(VG_Z_LIBC_SONAME, mempcpy)
+ //GLIBC25_MEMPCPY(VG_Z_LIBC_SONAME, mempcpy)
#endif
@@ -1495,7 +1536,35 @@
}
#if defined(VGO_linux)
- STRCASESTR(VG_Z_LIBC_SONAME, strcasestr)
+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android)
+ STRCASESTR(VG_Z_LIBC_SONAME, strcasestr)
+# endif
+
+#elif defined(VGO_darwin)
+
+#endif
+
+
+/*---------------------- wcslen ----------------------*/
+
+// This is a wchar_t equivalent to strlen. Unfortunately
+// we don't have wchar_t available here, but it looks like
+// a 32 bit int on Linux. I don't know if that is also
+// valid on MacOSX.
+
+#define WCSLEN(soname, fnname) \
+ SizeT VG_REPLACE_FUNCTION_EZU(20370,soname,fnname) \
+ ( const UInt* str ); \
+ SizeT VG_REPLACE_FUNCTION_EZU(20370,soname,fnname) \
+ ( const UInt* str ) \
+ { \
+ SizeT i = 0; \
+ while (str[i] != 0) i++; \
+ return i; \
+ }
+
+#if defined(VGO_linux)
+ WCSLEN(VG_Z_LIBC_SONAME, wcslen)
#elif defined(VGO_darwin)
diff --git a/main/memcheck/mc_translate.c b/main/memcheck/mc_translate.c
index fcd79ca..89a99d1 100644
--- a/main/memcheck/mc_translate.c
+++ b/main/memcheck/mc_translate.c
@@ -8,7 +8,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2011 Julian Seward
+ Copyright (C) 2000-2012 Julian Seward
jseward@acm.org
This program is free software; you can redistribute it and/or
@@ -30,6 +30,7 @@
*/
#include "pub_tool_basics.h"
+#include "pub_tool_poolalloc.h" // For mc_include.h
#include "pub_tool_hashtable.h" // For mc_include.h
#include "pub_tool_libcassert.h"
#include "pub_tool_libcprint.h"
@@ -187,7 +188,13 @@
/* MODIFIED: indicates whether "bogus" literals have so far been
found. Starts off False, and may change to True. */
- Bool bogusLiterals;
+ Bool bogusLiterals;
+
+ /* READONLY: indicates whether we should use expensive
+ interpretations of integer adds, since unfortunately LLVM
+ uses them to do ORs in some circumstances. Defaulted to True
+ on MacOS and False everywhere else. */
+ Bool useLLVMworkarounds;
/* READONLY: the guest layout. This indicates which parts of
the guest state should be regarded as 'always defined'. */
@@ -351,7 +358,7 @@
/* Shadow state is always accessed using integer types. This returns
an integer type with the same size (as per sizeofIRType) as the
given type. The only valid shadow types are Bit, I8, I16, I32,
- I64, I128, V128. */
+ I64, I128, V128, V256. */
static IRType shadowTypeV ( IRType ty )
{
@@ -363,9 +370,13 @@
case Ity_I64:
case Ity_I128: return ty;
case Ity_F32: return Ity_I32;
+ case Ity_D32: return Ity_I32;
case Ity_F64: return Ity_I64;
+ case Ity_D64: return Ity_I64;
case Ity_F128: return Ity_I128;
+ case Ity_D128: return Ity_I128;
case Ity_V128: return Ity_V128;
+ case Ity_V256: return Ity_V256;
default: ppIRType(ty);
VG_(tool_panic)("memcheck:shadowTypeV");
}
@@ -432,6 +443,7 @@
TempKind k;
IRTemp t;
IRType tyE = typeOfIRExpr(mce->sb->tyenv, e);
+
tl_assert(tyE == ty); /* so 'ty' is redundant (!) */
switch (cat) {
case 'V': k = VSh; break;
@@ -450,14 +462,17 @@
/*------------------------------------------------------------*/
/*--- Helper functions for 128-bit ops ---*/
/*------------------------------------------------------------*/
+
static IRExpr *i128_const_zero(void)
{
- return binop(Iop_64HLto128, IRExpr_Const(IRConst_U64(0)),
- IRExpr_Const(IRConst_U64(0)));
+ IRAtom* z64 = IRExpr_Const(IRConst_U64(0));
+ return binop(Iop_64HLto128, z64, z64);
}
-/* There are no 128-bit loads and/or stores. So we do not need to worry
- about that in expr2vbits_Load */
+/* There are no I128-bit loads and/or stores [as generated by any
+ current front ends]. So we do not need to worry about that in
+ expr2vbits_Load */
+
/*------------------------------------------------------------*/
/*--- Constructing definedness primitive ops ---*/
@@ -495,6 +510,12 @@
return assignNew('V', mce, Ity_V128, binop(Iop_AndV128, a1, a2));
}
+static IRAtom* mkDifDV256 ( MCEnv* mce, IRAtom* a1, IRAtom* a2 ) {
+ tl_assert(isShadowAtom(mce,a1));
+ tl_assert(isShadowAtom(mce,a2));
+ return assignNew('V', mce, Ity_V256, binop(Iop_AndV256, a1, a2));
+}
+
/* --------- Undefined-if-either-undefined --------- */
static IRAtom* mkUifU8 ( MCEnv* mce, IRAtom* a1, IRAtom* a2 ) {
@@ -541,6 +562,12 @@
return assignNew('V', mce, Ity_V128, binop(Iop_OrV128, a1, a2));
}
+static IRAtom* mkUifUV256 ( MCEnv* mce, IRAtom* a1, IRAtom* a2 ) {
+ tl_assert(isShadowAtom(mce,a1));
+ tl_assert(isShadowAtom(mce,a2));
+ return assignNew('V', mce, Ity_V256, binop(Iop_OrV256, a1, a2));
+}
+
static IRAtom* mkUifU ( MCEnv* mce, IRType vty, IRAtom* a1, IRAtom* a2 ) {
switch (vty) {
case Ity_I8: return mkUifU8(mce, a1, a2);
@@ -622,6 +649,14 @@
return assignNew('V', mce, Ity_V128, binop(Iop_OrV128, data, vbits));
}
+static IRAtom* mkImproveANDV256 ( MCEnv* mce, IRAtom* data, IRAtom* vbits )
+{
+ tl_assert(isOriginalAtom(mce, data));
+ tl_assert(isShadowAtom(mce, vbits));
+ tl_assert(sameKindedAtoms(data, vbits));
+ return assignNew('V', mce, Ity_V256, binop(Iop_OrV256, data, vbits));
+}
+
/* ImproveOR(data, vbits) = ~data OR vbits. Defined (0) data 1s give
defined (0); all other -> undefined (1).
*/
@@ -685,6 +720,18 @@
vbits) );
}
+static IRAtom* mkImproveORV256 ( MCEnv* mce, IRAtom* data, IRAtom* vbits )
+{
+ tl_assert(isOriginalAtom(mce, data));
+ tl_assert(isShadowAtom(mce, vbits));
+ tl_assert(sameKindedAtoms(data, vbits));
+ return assignNew(
+ 'V', mce, Ity_V256,
+ binop(Iop_OrV256,
+ assignNew('V', mce, Ity_V256, unop(Iop_NotV256, data)),
+ vbits) );
+}
+
/* --------- Pessimising casts. --------- */
/* The function returns an expression of type DST_TY. If any of the VBITS
@@ -695,8 +742,8 @@
{
IRType src_ty;
IRAtom* tmp1;
+
/* Note, dst_ty is a shadow type, not an original type. */
- /* First of all, collapse vbits down to a single bit. */
tl_assert(isShadowAtom(mce,vbits));
src_ty = typeOfIRExpr(mce->sb->tyenv, vbits);
@@ -708,11 +755,20 @@
return assignNew('V', mce, Ity_I64, unop(Iop_CmpwNEZ64, vbits));
if (src_ty == Ity_I32 && dst_ty == Ity_I64) {
+ /* PCast the arg, then clone it. */
IRAtom* tmp = assignNew('V', mce, Ity_I32, unop(Iop_CmpwNEZ32, vbits));
return assignNew('V', mce, Ity_I64, binop(Iop_32HLto64, tmp, tmp));
}
+ if (src_ty == Ity_I64 && dst_ty == Ity_I32) {
+ /* PCast the arg. This gives all 0s or all 1s. Then throw away
+ the top half. */
+ IRAtom* tmp = assignNew('V', mce, Ity_I64, unop(Iop_CmpwNEZ64, vbits));
+ return assignNew('V', mce, Ity_I32, unop(Iop_64to32, tmp));
+ }
+
/* Else do it the slow way .. */
+ /* First of all, collapse vbits down to a single bit. */
tmp1 = NULL;
switch (src_ty) {
case Ity_I1:
@@ -1012,12 +1068,16 @@
static void setHelperAnns ( MCEnv* mce, IRDirty* di ) {
di->nFxState = 2;
- di->fxState[0].fx = Ifx_Read;
- di->fxState[0].offset = mce->layout->offset_SP;
- di->fxState[0].size = mce->layout->sizeof_SP;
- di->fxState[1].fx = Ifx_Read;
- di->fxState[1].offset = mce->layout->offset_IP;
- di->fxState[1].size = mce->layout->sizeof_IP;
+ di->fxState[0].fx = Ifx_Read;
+ di->fxState[0].offset = mce->layout->offset_SP;
+ di->fxState[0].size = mce->layout->sizeof_SP;
+ di->fxState[0].nRepeats = 0;
+ di->fxState[0].repeatLen = 0;
+ di->fxState[1].fx = Ifx_Read;
+ di->fxState[1].offset = mce->layout->offset_IP;
+ di->fxState[1].size = mce->layout->sizeof_IP;
+ di->fxState[1].nRepeats = 0;
+ di->fxState[1].repeatLen = 0;
}
@@ -1031,7 +1091,7 @@
value to an existing shadow tmp as this breaks SSAness -- resulting
in the post-instrumentation sanity checker spluttering in disapproval.
*/
-static void complainIfUndefined ( MCEnv* mce, IRAtom* atom )
+static void complainIfUndefined ( MCEnv* mce, IRAtom* atom, IRExpr *guard )
{
IRAtom* vatom;
IRType ty;
@@ -1163,6 +1223,17 @@
di = unsafeIRDirty_0_N( nargs/*regparms*/, nm,
VG_(fnptr_to_fnentry)( fn ), args );
di->guard = cond;
+
+ /* If the complaint is to be issued under a guard condition, AND that
+ guard condition. */
+ if (guard) {
+ IRAtom *g1 = assignNew('V', mce, Ity_I32, unop(Iop_1Uto32, di->guard));
+ IRAtom *g2 = assignNew('V', mce, Ity_I32, unop(Iop_1Uto32, guard));
+ IRAtom *e = assignNew('V', mce, Ity_I32, binop(Iop_And32, g1, g2));
+
+ di->guard = assignNew('V', mce, Ity_I1, unop(Iop_32to1, e));
+ }
+
setHelperAnns( mce, di );
stmt( 'V', mce, IRStmt_Dirty(di));
@@ -1219,10 +1290,11 @@
supplied V bits to the shadow state. We can pass in either an
original atom or a V-atom, but not both. In the former case the
relevant V-bits are then generated from the original.
+ We assume here, that the definedness of GUARD has already been checked.
*/
static
void do_shadow_PUT ( MCEnv* mce, Int offset,
- IRAtom* atom, IRAtom* vatom )
+ IRAtom* atom, IRAtom* vatom, IRExpr *guard )
{
IRType ty;
@@ -1250,7 +1322,17 @@
/* complainIfUndefined(mce, atom); */
} else {
/* Do a plain shadow Put. */
- stmt( 'V', mce, IRStmt_Put( offset + mce->layout->total_sizeB, vatom ) );
+ if (guard) {
+ /* If the guard expression evaluates to false we simply Put the value
+ that is already stored in the guest state slot */
+ IRAtom *cond, *iffalse;
+
+ cond = assignNew('V', mce, Ity_I8, unop(Iop_1Uto8, guard));
+ iffalse = assignNew('V', mce, ty,
+ IRExpr_Get(offset + mce->layout->total_sizeB, ty));
+ vatom = assignNew('V', mce, ty, IRExpr_Mux0X(cond, iffalse, vatom));
+ }
+ stmt( 'V', mce, IRStmt_Put( offset + mce->layout->total_sizeB, vatom ));
}
}
@@ -1259,13 +1341,15 @@
given GETI (passed in in pieces).
*/
static
-void do_shadow_PUTI ( MCEnv* mce,
- IRRegArray* descr,
- IRAtom* ix, Int bias, IRAtom* atom )
+void do_shadow_PUTI ( MCEnv* mce, IRPutI *puti)
{
IRAtom* vatom;
IRType ty, tyS;
Int arrSize;;
+ IRRegArray* descr = puti->descr;
+ IRAtom* ix = puti->ix;
+ Int bias = puti->bias;
+ IRAtom* atom = puti->data;
// Don't do shadow PUTIs if we're not doing undefined value checking.
// Their absence lets Vex's optimiser remove all the shadow computation
@@ -1281,7 +1365,7 @@
arrSize = descr->nElems * sizeofIRType(ty);
tl_assert(ty != Ity_I1);
tl_assert(isOriginalAtom(mce,ix));
- complainIfUndefined(mce,ix);
+ complainIfUndefined(mce, ix, NULL);
if (isAlwaysDefd(mce, descr->base, arrSize)) {
/* later: no ... */
/* emit code to emit a complaint if any of the vbits are 1. */
@@ -1292,7 +1376,7 @@
IRRegArray* new_descr
= mkIRRegArray( descr->base + mce->layout->total_sizeB,
tyS, descr->nElems);
- stmt( 'V', mce, IRStmt_PutI( new_descr, ix, bias, vatom ));
+ stmt( 'V', mce, IRStmt_PutI( mkIRPutI(new_descr, ix, bias, vatom) ));
}
}
@@ -1330,7 +1414,7 @@
Int arrSize = descr->nElems * sizeofIRType(ty);
tl_assert(ty != Ity_I1);
tl_assert(isOriginalAtom(mce,ix));
- complainIfUndefined(mce,ix);
+ complainIfUndefined(mce, ix, NULL);
if (isAlwaysDefd(mce, descr->base, arrSize)) {
/* Always defined, return all zeroes of the relevant type */
return definedOfType(tyS);
@@ -1781,6 +1865,16 @@
return assignNew('V', mce, Ity_V128, unop(Iop_CmpNEZ64x2, at));
}
+static IRAtom* mkPCast64x4 ( MCEnv* mce, IRAtom* at )
+{
+ return assignNew('V', mce, Ity_V256, unop(Iop_CmpNEZ64x4, at));
+}
+
+static IRAtom* mkPCast32x8 ( MCEnv* mce, IRAtom* at )
+{
+ return assignNew('V', mce, Ity_V256, unop(Iop_CmpNEZ32x8, at));
+}
+
static IRAtom* mkPCast32x2 ( MCEnv* mce, IRAtom* at )
{
return assignNew('V', mce, Ity_I64, unop(Iop_CmpNEZ32x2, at));
@@ -1955,6 +2049,50 @@
return at;
}
+/* --- ... and ... 64Fx4 versions of the same ... --- */
+
+static
+IRAtom* binary64Fx4 ( MCEnv* mce, IRAtom* vatomX, IRAtom* vatomY )
+{
+ IRAtom* at;
+ tl_assert(isShadowAtom(mce, vatomX));
+ tl_assert(isShadowAtom(mce, vatomY));
+ at = mkUifUV256(mce, vatomX, vatomY);
+ at = assignNew('V', mce, Ity_V256, mkPCast64x4(mce, at));
+ return at;
+}
+
+static
+IRAtom* unary64Fx4 ( MCEnv* mce, IRAtom* vatomX )
+{
+ IRAtom* at;
+ tl_assert(isShadowAtom(mce, vatomX));
+ at = assignNew('V', mce, Ity_V256, mkPCast64x4(mce, vatomX));
+ return at;
+}
+
+/* --- ... and ... 32Fx8 versions of the same ... --- */
+
+static
+IRAtom* binary32Fx8 ( MCEnv* mce, IRAtom* vatomX, IRAtom* vatomY )
+{
+ IRAtom* at;
+ tl_assert(isShadowAtom(mce, vatomX));
+ tl_assert(isShadowAtom(mce, vatomY));
+ at = mkUifUV256(mce, vatomX, vatomY);
+ at = assignNew('V', mce, Ity_V256, mkPCast32x8(mce, at));
+ return at;
+}
+
+static
+IRAtom* unary32Fx8 ( MCEnv* mce, IRAtom* vatomX )
+{
+ IRAtom* at;
+ tl_assert(isShadowAtom(mce, vatomX));
+ at = assignNew('V', mce, Ity_V256, mkPCast32x8(mce, vatomX));
+ return at;
+}
+
/* --- --- Vector saturated narrowing --- --- */
/* We used to do something very clever here, but on closer inspection
@@ -2288,6 +2426,11 @@
/* I32(rm) x F32 x F32 x F32 -> F32 */
return mkLazy4(mce, Ity_I32, vatom1, vatom2, vatom3, vatom4);
+ /* V256-bit data-steering */
+ case Iop_64x4toV256:
+ return assignNew('V', mce, Ity_V256,
+ IRExpr_Qop(op, vatom1, vatom2, vatom3, vatom4));
+
default:
ppIROp(op);
VG_(tool_panic)("memcheck:expr2vbits_Qop");
@@ -2315,18 +2458,27 @@
tl_assert(sameKindedAtoms(atom3,vatom3));
switch (op) {
case Iop_AddF128:
+ case Iop_AddD128:
case Iop_SubF128:
+ case Iop_SubD128:
case Iop_MulF128:
+ case Iop_MulD128:
case Iop_DivF128:
- /* I32(rm) x F128 x F128 -> F128 */
+ case Iop_DivD128:
+ case Iop_QuantizeD128:
+ /* I32(rm) x F128/D128 x F128/D128 -> F128/D128 */
return mkLazy3(mce, Ity_I128, vatom1, vatom2, vatom3);
case Iop_AddF64:
+ case Iop_AddD64:
case Iop_AddF64r32:
case Iop_SubF64:
+ case Iop_SubD64:
case Iop_SubF64r32:
case Iop_MulF64:
+ case Iop_MulD64:
case Iop_MulF64r32:
case Iop_DivF64:
+ case Iop_DivD64:
case Iop_DivF64r32:
case Iop_ScaleF64:
case Iop_Yl2xF64:
@@ -2334,7 +2486,8 @@
case Iop_AtanF64:
case Iop_PRemF64:
case Iop_PRem1F64:
- /* I32(rm) x F64 x F64 -> F64 */
+ case Iop_QuantizeD64:
+ /* I32(rm) x F64/D64 x F64/D64 -> F64/D64 */
return mkLazy3(mce, Ity_I64, vatom1, vatom2, vatom3);
case Iop_PRemC3210F64:
case Iop_PRem1C3210F64:
@@ -2346,16 +2499,22 @@
case Iop_DivF32:
/* I32(rm) x F32 x F32 -> I32 */
return mkLazy3(mce, Ity_I32, vatom1, vatom2, vatom3);
+ case Iop_SignificanceRoundD64:
+ /* IRRoundingModeDFP(I32) x I8 x D64 -> D64 */
+ return mkLazy3(mce, Ity_I64, vatom1, vatom2, vatom3);
+ case Iop_SignificanceRoundD128:
+ /* IRRoundingModeDFP(I32) x I8 x D128 -> D128 */
+ return mkLazy3(mce, Ity_I128, vatom1, vatom2, vatom3);
case Iop_ExtractV128:
- complainIfUndefined(mce, atom3);
+ complainIfUndefined(mce, atom3, NULL);
return assignNew('V', mce, Ity_V128, triop(op, vatom1, vatom2, atom3));
case Iop_Extract64:
- complainIfUndefined(mce, atom3);
+ complainIfUndefined(mce, atom3, NULL);
return assignNew('V', mce, Ity_I64, triop(op, vatom1, vatom2, atom3));
case Iop_SetElem8x8:
case Iop_SetElem16x4:
case Iop_SetElem32x2:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I64, triop(op, vatom1, atom2, vatom3));
default:
ppIROp(op);
@@ -2395,6 +2554,7 @@
case Iop_HSub16Sx2:
case Iop_QAdd16Sx2:
case Iop_QSub16Sx2:
+ case Iop_QSub16Ux2:
return binary16Ix2(mce, vatom1, vatom2);
case Iop_Add8x4:
@@ -2421,7 +2581,7 @@
case Iop_ShlN32x2:
case Iop_ShlN8x8:
/* Same scheme as with all other shifts. */
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2));
case Iop_QNarrowBin32Sto16Sx4:
@@ -2504,25 +2664,25 @@
case Iop_QShlN8Sx8:
case Iop_QShlN8x8:
case Iop_QSalN8x8:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast8x8(mce, vatom1);
case Iop_QShlN16Sx4:
case Iop_QShlN16x4:
case Iop_QSalN16x4:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast16x4(mce, vatom1);
case Iop_QShlN32Sx2:
case Iop_QShlN32x2:
case Iop_QSalN32x2:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast32x2(mce, vatom1);
case Iop_QShlN64Sx1:
case Iop_QShlN64x1:
case Iop_QSalN64x1:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast32x2(mce, vatom1);
case Iop_PwMax32Sx2:
@@ -2531,38 +2691,48 @@
case Iop_PwMin32Ux2:
case Iop_PwMax32Fx2:
case Iop_PwMin32Fx2:
- return assignNew('V', mce, Ity_I64, binop(Iop_PwMax32Ux2, mkPCast32x2(mce, vatom1),
- mkPCast32x2(mce, vatom2)));
+ return assignNew('V', mce, Ity_I64,
+ binop(Iop_PwMax32Ux2,
+ mkPCast32x2(mce, vatom1),
+ mkPCast32x2(mce, vatom2)));
case Iop_PwMax16Sx4:
case Iop_PwMax16Ux4:
case Iop_PwMin16Sx4:
case Iop_PwMin16Ux4:
- return assignNew('V', mce, Ity_I64, binop(Iop_PwMax16Ux4, mkPCast16x4(mce, vatom1),
- mkPCast16x4(mce, vatom2)));
+ return assignNew('V', mce, Ity_I64,
+ binop(Iop_PwMax16Ux4,
+ mkPCast16x4(mce, vatom1),
+ mkPCast16x4(mce, vatom2)));
case Iop_PwMax8Sx8:
case Iop_PwMax8Ux8:
case Iop_PwMin8Sx8:
case Iop_PwMin8Ux8:
- return assignNew('V', mce, Ity_I64, binop(Iop_PwMax8Ux8, mkPCast8x8(mce, vatom1),
- mkPCast8x8(mce, vatom2)));
+ return assignNew('V', mce, Ity_I64,
+ binop(Iop_PwMax8Ux8,
+ mkPCast8x8(mce, vatom1),
+ mkPCast8x8(mce, vatom2)));
case Iop_PwAdd32x2:
case Iop_PwAdd32Fx2:
return mkPCast32x2(mce,
- assignNew('V', mce, Ity_I64, binop(Iop_PwAdd32x2, mkPCast32x2(mce, vatom1),
- mkPCast32x2(mce, vatom2))));
+ assignNew('V', mce, Ity_I64,
+ binop(Iop_PwAdd32x2,
+ mkPCast32x2(mce, vatom1),
+ mkPCast32x2(mce, vatom2))));
case Iop_PwAdd16x4:
return mkPCast16x4(mce,
- assignNew('V', mce, Ity_I64, binop(op, mkPCast16x4(mce, vatom1),
- mkPCast16x4(mce, vatom2))));
+ assignNew('V', mce, Ity_I64,
+ binop(op, mkPCast16x4(mce, vatom1),
+ mkPCast16x4(mce, vatom2))));
case Iop_PwAdd8x8:
return mkPCast8x8(mce,
- assignNew('V', mce, Ity_I64, binop(op, mkPCast8x8(mce, vatom1),
- mkPCast8x8(mce, vatom2))));
+ assignNew('V', mce, Ity_I64,
+ binop(op, mkPCast8x8(mce, vatom1),
+ mkPCast8x8(mce, vatom2))));
case Iop_Shl8x8:
case Iop_Shr8x8:
@@ -2609,13 +2779,13 @@
return assignNew('V', mce, Ity_I64, binop(op, vatom1, vatom2));
case Iop_GetElem8x8:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I8, binop(op, vatom1, atom2));
case Iop_GetElem16x4:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I16, binop(op, vatom1, atom2));
case Iop_GetElem32x2:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I32, binop(op, vatom1, atom2));
/* Perm8x8: rearrange values in left arg using steering values
@@ -2645,7 +2815,7 @@
/* Same scheme as with all other shifts. Note: 22 Oct 05:
this is wrong now, scalar shifts are done properly lazily.
Vector shifts should be fixed too. */
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2));
/* V x V shifts/rotates are done using the standard lazy scheme. */
@@ -2692,14 +2862,14 @@
case Iop_F32ToFixed32Sx4_RZ:
case Iop_Fixed32UToF32x4_RN:
case Iop_Fixed32SToF32x4_RN:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast32x4(mce, vatom1);
case Iop_F32ToFixed32Ux2_RZ:
case Iop_F32ToFixed32Sx2_RZ:
case Iop_Fixed32UToF32x2_RN:
case Iop_Fixed32SToF32x2_RN:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast32x2(mce, vatom1);
case Iop_QSub8Ux16:
@@ -2856,25 +3026,25 @@
case Iop_QShlN8Sx16:
case Iop_QShlN8x16:
case Iop_QSalN8x16:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast8x16(mce, vatom1);
case Iop_QShlN16Sx8:
case Iop_QShlN16x8:
case Iop_QSalN16x8:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast16x8(mce, vatom1);
case Iop_QShlN32Sx4:
case Iop_QShlN32x4:
case Iop_QSalN32x4:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast32x4(mce, vatom1);
case Iop_QShlN64Sx2:
case Iop_QShlN64x2:
case Iop_QSalN64x2:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return mkPCast32x4(mce, vatom1);
case Iop_Mull32Sx2:
@@ -2937,27 +3107,33 @@
return assignNew('V', mce, Ity_V128, binop(op, vatom1, vatom2));
case Iop_GetElem8x16:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I8, binop(op, vatom1, atom2));
case Iop_GetElem16x8:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I16, binop(op, vatom1, atom2));
case Iop_GetElem32x4:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I32, binop(op, vatom1, atom2));
case Iop_GetElem64x2:
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2));
/* Perm8x16: rearrange values in left arg using steering values
from right arg. So rearrange the vbits in the same way but
- pessimise wrt steering values. */
+ pessimise wrt steering values. Perm32x4 ditto. */
case Iop_Perm8x16:
return mkUifUV128(
mce,
assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),
mkPCast8x16(mce, vatom2)
);
+ case Iop_Perm32x4:
+ return mkUifUV128(
+ mce,
+ assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),
+ mkPCast32x4(mce, vatom2)
+ );
/* These two take the lower half of each 16-bit lane, sign/zero
extend it to 32, and multiply together, producing a 32x4
@@ -2999,13 +3175,35 @@
/* Same scheme as with all other shifts. Note: 10 Nov 05:
this is wrong now, scalar shifts are done properly lazily.
Vector shifts should be fixed too. */
- complainIfUndefined(mce, atom2);
+ complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2));
/* I128-bit data-steering */
case Iop_64HLto128:
return assignNew('V', mce, Ity_I128, binop(op, vatom1, vatom2));
+ /* V256-bit SIMD */
+
+ case Iop_Add64Fx4:
+ case Iop_Sub64Fx4:
+ case Iop_Mul64Fx4:
+ case Iop_Div64Fx4:
+ case Iop_Max64Fx4:
+ case Iop_Min64Fx4:
+ return binary64Fx4(mce, vatom1, vatom2);
+
+ case Iop_Add32Fx8:
+ case Iop_Sub32Fx8:
+ case Iop_Mul32Fx8:
+ case Iop_Div32Fx8:
+ case Iop_Max32Fx8:
+ case Iop_Min32Fx8:
+ return binary32Fx8(mce, vatom1, vatom2);
+
+ /* V256-bit data-steering */
+ case Iop_V128HLtoV256:
+ return assignNew('V', mce, Ity_V256, binop(op, vatom1, vatom2));
+
/* Scalar floating point */
case Iop_F32toI64S:
@@ -3030,6 +3228,23 @@
/* I32(rm) x I64/F64 -> I64/F64 */
return mkLazy2(mce, Ity_I64, vatom1, vatom2);
+ case Iop_ShlD64:
+ case Iop_ShrD64:
+ case Iop_RoundD64toInt:
+ /* I32(DFP rm) x D64 -> D64 */
+ return mkLazy2(mce, Ity_I64, vatom1, vatom2);
+
+ case Iop_ShlD128:
+ case Iop_ShrD128:
+ case Iop_RoundD128toInt:
+ /* I32(DFP rm) x D128 -> D128 */
+ return mkLazy2(mce, Ity_I128, vatom1, vatom2);
+
+ case Iop_D64toI64S:
+ case Iop_I64StoD64:
+ /* I64(DFP rm) x I64 -> D64 */
+ return mkLazy2(mce, Ity_I64, vatom1, vatom2);
+
case Iop_RoundF32toInt:
case Iop_SqrtF32:
/* I32(rm) x I32/F32 -> I32/F32 */
@@ -3050,10 +3265,14 @@
case Iop_F128toI64S: /* IRRoundingMode(I32) x F128 -> signed I64 */
case Iop_F128toF64: /* IRRoundingMode(I32) x F128 -> F64 */
+ case Iop_D128toD64: /* IRRoundingModeDFP(I64) x D128 -> D64 */
+ case Iop_D128toI64S: /* IRRoundingModeDFP(I64) x D128 -> signed I64 */
return mkLazy2(mce, Ity_I64, vatom1, vatom2);
case Iop_F64HLtoF128:
- return assignNew('V', mce, Ity_I128, binop(Iop_64HLto128, vatom1, vatom2));
+ case Iop_D64HLtoD128:
+ return assignNew('V', mce, Ity_I128,
+ binop(Iop_64HLto128, vatom1, vatom2));
case Iop_F64toI32U:
case Iop_F64toI32S:
@@ -3062,13 +3281,27 @@
/* First arg is I32 (rounding mode), second is F64 (data). */
return mkLazy2(mce, Ity_I32, vatom1, vatom2);
+ case Iop_D64toD32:
+ /* First arg is I64 (DFProunding mode), second is D64 (data). */
+ return mkLazy2(mce, Ity_I64, vatom1, vatom2);
+
case Iop_F64toI16S:
/* First arg is I32 (rounding mode), second is F64 (data). */
return mkLazy2(mce, Ity_I16, vatom1, vatom2);
+ case Iop_InsertExpD64:
+ /* I64 x I64 -> D64 */
+ return mkLazy2(mce, Ity_I64, vatom1, vatom2);
+
+ case Iop_InsertExpD128:
+ /* I64 x I128 -> D128 */
+ return mkLazy2(mce, Ity_I128, vatom1, vatom2);
+
case Iop_CmpF32:
case Iop_CmpF64:
case Iop_CmpF128:
+ case Iop_CmpD64:
+ case Iop_CmpD128:
return mkLazy2(mce, Ity_I32, vatom1, vatom2);
/* non-FP after here */
@@ -3091,21 +3324,24 @@
case Iop_MullU64: {
IRAtom* vLo64 = mkLeft64(mce, mkUifU64(mce, vatom1,vatom2));
IRAtom* vHi64 = mkPCastTo(mce, Ity_I64, vLo64);
- return assignNew('V', mce, Ity_I128, binop(Iop_64HLto128, vHi64, vLo64));
+ return assignNew('V', mce, Ity_I128,
+ binop(Iop_64HLto128, vHi64, vLo64));
}
case Iop_MullS32:
case Iop_MullU32: {
IRAtom* vLo32 = mkLeft32(mce, mkUifU32(mce, vatom1,vatom2));
IRAtom* vHi32 = mkPCastTo(mce, Ity_I32, vLo32);
- return assignNew('V', mce, Ity_I64, binop(Iop_32HLto64, vHi32, vLo32));
+ return assignNew('V', mce, Ity_I64,
+ binop(Iop_32HLto64, vHi32, vLo32));
}
case Iop_MullS16:
case Iop_MullU16: {
IRAtom* vLo16 = mkLeft16(mce, mkUifU16(mce, vatom1,vatom2));
IRAtom* vHi16 = mkPCastTo(mce, Ity_I16, vLo16);
- return assignNew('V', mce, Ity_I32, binop(Iop_16HLto32, vHi16, vLo16));
+ return assignNew('V', mce, Ity_I32,
+ binop(Iop_16HLto32, vHi16, vLo16));
}
case Iop_MullS8:
@@ -3120,6 +3356,8 @@
case Iop_DivU32:
case Iop_DivU32E:
case Iop_DivS32E:
+ case Iop_QAdd32S: /* could probably do better */
+ case Iop_QSub32S: /* could probably do better */
return mkLazy2(mce, Ity_I32, vatom1, vatom2);
case Iop_DivS64:
@@ -3129,7 +3367,7 @@
return mkLazy2(mce, Ity_I64, vatom1, vatom2);
case Iop_Add32:
- if (mce->bogusLiterals)
+ if (mce->bogusLiterals || mce->useLLVMworkarounds)
return expensiveAddSub(mce,True,Ity_I32,
vatom1,vatom2, atom1,atom2);
else
@@ -3152,7 +3390,7 @@
return doCmpORD(mce, op, vatom1,vatom2, atom1,atom2);
case Iop_Add64:
- if (mce->bogusLiterals)
+ if (mce->bogusLiterals || mce->useLLVMworkarounds)
return expensiveAddSub(mce,True,Ity_I64,
vatom1,vatom2, atom1,atom2);
else
@@ -3225,6 +3463,9 @@
case Iop_Shl8: case Iop_Shr8:
return scalarShift( mce, Ity_I8, op, vatom1,vatom2, atom1,atom2 );
+ case Iop_AndV256:
+ uifu = mkUifUV256; difd = mkDifDV256;
+ and_or_ty = Ity_V256; improve = mkImproveANDV256; goto do_And_Or;
case Iop_AndV128:
uifu = mkUifUV128; difd = mkDifDV128;
and_or_ty = Ity_V128; improve = mkImproveANDV128; goto do_And_Or;
@@ -3241,6 +3482,9 @@
uifu = mkUifU8; difd = mkDifD8;
and_or_ty = Ity_I8; improve = mkImproveAND8; goto do_And_Or;
+ case Iop_OrV256:
+ uifu = mkUifUV256; difd = mkDifDV256;
+ and_or_ty = Ity_V256; improve = mkImproveORV256; goto do_And_Or;
case Iop_OrV128:
uifu = mkUifUV128; difd = mkDifDV128;
and_or_ty = Ity_V128; improve = mkImproveORV128; goto do_And_Or;
@@ -3276,6 +3520,8 @@
return mkUifU64(mce, vatom1, vatom2);
case Iop_XorV128:
return mkUifUV128(mce, vatom1, vatom2);
+ case Iop_XorV256:
+ return mkUifUV256(mce, vatom1, vatom2);
default:
ppIROp(op);
@@ -3297,6 +3543,14 @@
case Iop_Sqrt64F0x2:
return unary64F0x2(mce, vatom);
+ case Iop_Sqrt32Fx8:
+ case Iop_RSqrt32Fx8:
+ case Iop_Recip32Fx8:
+ return unary32Fx8(mce, vatom);
+
+ case Iop_Sqrt64Fx4:
+ return unary64Fx4(mce, vatom);
+
case Iop_Sqrt32Fx4:
case Iop_RSqrt32Fx4:
case Iop_Recip32Fx4:
@@ -3339,11 +3593,14 @@
case Iop_Reverse64_8x16:
case Iop_Reverse64_16x8:
case Iop_Reverse64_32x4:
+ case Iop_V256toV128_1: case Iop_V256toV128_0:
return assignNew('V', mce, Ity_V128, unop(op, vatom));
case Iop_F128HItoF64: /* F128 -> high half of F128 */
+ case Iop_D128HItoD64: /* D128 -> high half of D128 */
return assignNew('V', mce, Ity_I64, unop(Iop_128HIto64, vatom));
case Iop_F128LOtoF64: /* F128 -> low half of F128 */
+ case Iop_D128LOtoD64: /* D128 -> low half of D128 */
return assignNew('V', mce, Ity_I64, unop(Iop_128to64, vatom));
case Iop_NegF128:
@@ -3354,6 +3611,7 @@
case Iop_I64StoF128: /* signed I64 -> F128 */
case Iop_F32toF128: /* F32 -> F128 */
case Iop_F64toF128: /* F64 -> F128 */
+ case Iop_I64StoD128: /* signed I64 -> D128 */
return mkPCastTo(mce, Ity_I128, vatom);
case Iop_F32toF64:
@@ -3368,8 +3626,16 @@
case Iop_RoundF64toF64_ZERO:
case Iop_Clz64:
case Iop_Ctz64:
+ case Iop_D32toD64:
+ case Iop_ExtractExpD64: /* D64 -> I64 */
+ case Iop_ExtractExpD128: /* D128 -> I64 */
+ case Iop_DPBtoBCD:
+ case Iop_BCDtoDPB:
return mkPCastTo(mce, Ity_I64, vatom);
+ case Iop_D64toD128:
+ return mkPCastTo(mce, Ity_I128, vatom);
+
case Iop_Clz32:
case Iop_Ctz32:
case Iop_TruncF64asF32:
@@ -3398,6 +3664,8 @@
case Iop_Reverse64_8x8:
case Iop_Reverse64_16x4:
case Iop_Reverse64_32x2:
+ case Iop_V256to64_0: case Iop_V256to64_1:
+ case Iop_V256to64_2: case Iop_V256to64_3:
return assignNew('V', mce, Ity_I64, unop(op, vatom));
case Iop_I16StoF32:
@@ -3437,6 +3705,9 @@
case Iop_ReinterpI64asF64:
case Iop_ReinterpI32asF32:
case Iop_ReinterpF32asI32:
+ case Iop_ReinterpI64asD64:
+ case Iop_ReinterpD64asI64:
+ case Iop_NotV256:
case Iop_NotV128:
case Iop_Not64:
case Iop_Not32:
@@ -3570,7 +3841,7 @@
/* First, emit a definedness test for the address. This also sets
the address (shadow) to 'defined' following the test. */
- complainIfUndefined( mce, addr );
+ complainIfUndefined( mce, addr, NULL );
/* Now cook up a call to the relevant helper function, to read the
data V bits from shadow memory. */
@@ -3644,7 +3915,6 @@
IREndness end, IRType ty,
IRAtom* addr, UInt bias )
{
- IRAtom *v64hi, *v64lo;
tl_assert(end == Iend_LE || end == Iend_BE);
switch (shadowTypeV(ty)) {
case Ity_I8:
@@ -3652,23 +3922,65 @@
case Ity_I32:
case Ity_I64:
return expr2vbits_Load_WRK(mce, end, ty, addr, bias);
- case Ity_V128:
+ case Ity_V128: {
+ IRAtom *v64hi, *v64lo;
if (end == Iend_LE) {
- v64lo = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias);
+ v64lo = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+0);
v64hi = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+8);
} else {
- v64hi = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias);
+ v64hi = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+0);
v64lo = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+8);
}
return assignNew( 'V', mce,
Ity_V128,
binop(Iop_64HLtoV128, v64hi, v64lo));
+ }
+ case Ity_V256: {
+ /* V256-bit case -- phrased in terms of 64 bit units (Qs),
+ with Q3 being the most significant lane. */
+ if (end == Iend_BE) goto unhandled;
+ IRAtom* v64Q0 = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+0);
+ IRAtom* v64Q1 = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+8);
+ IRAtom* v64Q2 = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+16);
+ IRAtom* v64Q3 = expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+24);
+ return assignNew( 'V', mce,
+ Ity_V256,
+ IRExpr_Qop(Iop_64x4toV256,
+ v64Q3, v64Q2, v64Q1, v64Q0));
+ }
+ unhandled:
default:
VG_(tool_panic)("expr2vbits_Load");
}
}
+/* If there is no guard expression or the guard is always TRUE this function
+ behaves like expr2vbits_Load. If the guard is not true at runtime, an
+ all-bits-defined bit pattern will be returned.
+ It is assumed that definedness of GUARD has already been checked at the call
+ site. */
+static
+IRAtom* expr2vbits_guarded_Load ( MCEnv* mce,
+ IREndness end, IRType ty,
+ IRAtom* addr, UInt bias, IRAtom *guard )
+{
+ if (guard) {
+ IRAtom *cond, *iffalse, *iftrue;
+
+ cond = assignNew('V', mce, Ity_I8, unop(Iop_1Uto8, guard));
+ iftrue = assignNew('V', mce, ty,
+ expr2vbits_Load(mce, end, ty, addr, bias));
+ iffalse = assignNew('V', mce, ty, definedOfType(ty));
+
+ return assignNew('V', mce, ty, IRExpr_Mux0X(cond, iffalse, iftrue));
+ }
+
+ /* No guard expression or unconditional load */
+ return expr2vbits_Load(mce, end, ty, addr, bias);
+}
+
+
static
IRAtom* expr2vbits_Mux0X ( MCEnv* mce,
IRAtom* cond, IRAtom* expr0, IRAtom* exprX )
@@ -3718,16 +4030,17 @@
case Iex_Qop:
return expr2vbits_Qop(
mce,
- e->Iex.Qop.op,
- e->Iex.Qop.arg1, e->Iex.Qop.arg2,
- e->Iex.Qop.arg3, e->Iex.Qop.arg4
+ e->Iex.Qop.details->op,
+ e->Iex.Qop.details->arg1, e->Iex.Qop.details->arg2,
+ e->Iex.Qop.details->arg3, e->Iex.Qop.details->arg4
);
case Iex_Triop:
return expr2vbits_Triop(
mce,
- e->Iex.Triop.op,
- e->Iex.Triop.arg1, e->Iex.Triop.arg2, e->Iex.Triop.arg3
+ e->Iex.Triop.details->op,
+ e->Iex.Triop.details->arg1, e->Iex.Triop.details->arg2,
+ e->Iex.Triop.details->arg3
);
case Iex_Binop:
@@ -3862,7 +4175,9 @@
// shadow computation ops that precede it.
if (MC_(clo_mc_level) == 1) {
switch (ty) {
- case Ity_V128: // V128 weirdness
+ case Ity_V256: // V256 weirdness -- used four times
+ c = IRConst_V256(V_BITS32_DEFINED); break;
+ case Ity_V128: // V128 weirdness -- used twice
c = IRConst_V128(V_BITS16_DEFINED); break;
case Ity_I64: c = IRConst_U64 (V_BITS64_DEFINED); break;
case Ity_I32: c = IRConst_U32 (V_BITS32_DEFINED); break;
@@ -3875,12 +4190,13 @@
/* First, emit a definedness test for the address. This also sets
the address (shadow) to 'defined' following the test. */
- complainIfUndefined( mce, addr );
+ complainIfUndefined( mce, addr, guard );
/* Now decide which helper function to call to write the data V
bits into shadow memory. */
if (end == Iend_LE) {
switch (ty) {
+ case Ity_V256: /* we'll use the helper four times */
case Ity_V128: /* we'll use the helper twice */
case Ity_I64: helper = &MC_(helperc_STOREV64le);
hname = "MC_(helperc_STOREV64le)";
@@ -3911,11 +4227,81 @@
case Ity_I8: helper = &MC_(helperc_STOREV8);
hname = "MC_(helperc_STOREV8)";
break;
+ /* Note, no V256 case here, because no big-endian target that
+ we support, has 256 vectors. */
default: VG_(tool_panic)("memcheck:do_shadow_Store(BE)");
}
}
- if (ty == Ity_V128) {
+ if (UNLIKELY(ty == Ity_V256)) {
+
+ /* V256-bit case -- phrased in terms of 64 bit units (Qs), with
+ Q3 being the most significant lane. */
+ /* These are the offsets of the Qs in memory. */
+ Int offQ0, offQ1, offQ2, offQ3;
+
+ /* Various bits for constructing the 4 lane helper calls */
+ IRDirty *diQ0, *diQ1, *diQ2, *diQ3;
+ IRAtom *addrQ0, *addrQ1, *addrQ2, *addrQ3;
+ IRAtom *vdataQ0, *vdataQ1, *vdataQ2, *vdataQ3;
+ IRAtom *eBiasQ0, *eBiasQ1, *eBiasQ2, *eBiasQ3;
+
+ if (end == Iend_LE) {
+ offQ0 = 0; offQ1 = 8; offQ2 = 16; offQ3 = 24;
+ } else {
+ offQ3 = 0; offQ2 = 8; offQ1 = 16; offQ0 = 24;
+ }
+
+ eBiasQ0 = tyAddr==Ity_I32 ? mkU32(bias+offQ0) : mkU64(bias+offQ0);
+ addrQ0 = assignNew('V', mce, tyAddr, binop(mkAdd, addr, eBiasQ0) );
+ vdataQ0 = assignNew('V', mce, Ity_I64, unop(Iop_V256to64_0, vdata));
+ diQ0 = unsafeIRDirty_0_N(
+ 1/*regparms*/,
+ hname, VG_(fnptr_to_fnentry)( helper ),
+ mkIRExprVec_2( addrQ0, vdataQ0 )
+ );
+
+ eBiasQ1 = tyAddr==Ity_I32 ? mkU32(bias+offQ1) : mkU64(bias+offQ1);
+ addrQ1 = assignNew('V', mce, tyAddr, binop(mkAdd, addr, eBiasQ1) );
+ vdataQ1 = assignNew('V', mce, Ity_I64, unop(Iop_V256to64_1, vdata));
+ diQ1 = unsafeIRDirty_0_N(
+ 1/*regparms*/,
+ hname, VG_(fnptr_to_fnentry)( helper ),
+ mkIRExprVec_2( addrQ1, vdataQ1 )
+ );
+
+ eBiasQ2 = tyAddr==Ity_I32 ? mkU32(bias+offQ2) : mkU64(bias+offQ2);
+ addrQ2 = assignNew('V', mce, tyAddr, binop(mkAdd, addr, eBiasQ2) );
+ vdataQ2 = assignNew('V', mce, Ity_I64, unop(Iop_V256to64_2, vdata));
+ diQ2 = unsafeIRDirty_0_N(
+ 1/*regparms*/,
+ hname, VG_(fnptr_to_fnentry)( helper ),
+ mkIRExprVec_2( addrQ2, vdataQ2 )
+ );
+
+ eBiasQ3 = tyAddr==Ity_I32 ? mkU32(bias+offQ3) : mkU64(bias+offQ3);
+ addrQ3 = assignNew('V', mce, tyAddr, binop(mkAdd, addr, eBiasQ3) );
+ vdataQ3 = assignNew('V', mce, Ity_I64, unop(Iop_V256to64_3, vdata));
+ diQ3 = unsafeIRDirty_0_N(
+ 1/*regparms*/,
+ hname, VG_(fnptr_to_fnentry)( helper ),
+ mkIRExprVec_2( addrQ3, vdataQ3 )
+ );
+
+ if (guard)
+ diQ0->guard = diQ1->guard = diQ2->guard = diQ3->guard = guard;
+
+ setHelperAnns( mce, diQ0 );
+ setHelperAnns( mce, diQ1 );
+ setHelperAnns( mce, diQ2 );
+ setHelperAnns( mce, diQ3 );
+ stmt( 'V', mce, IRStmt_Dirty(diQ0) );
+ stmt( 'V', mce, IRStmt_Dirty(diQ1) );
+ stmt( 'V', mce, IRStmt_Dirty(diQ2) );
+ stmt( 'V', mce, IRStmt_Dirty(diQ3) );
+
+ }
+ else if (UNLIKELY(ty == Ity_V128)) {
/* V128-bit case */
/* See comment in next clause re 64-bit regparms */
@@ -4015,7 +4401,7 @@
static
void do_shadow_Dirty ( MCEnv* mce, IRDirty* d )
{
- Int i, n, toDo, gSz, gOff;
+ Int i, k, n, toDo, gSz, gOff;
IRAtom *src, *here, *curr;
IRType tySrc, tyDst;
IRTemp dst;
@@ -4031,12 +4417,13 @@
# endif
/* First check the guard. */
- complainIfUndefined(mce, d->guard);
+ complainIfUndefined(mce, d->guard, NULL);
/* Now round up all inputs and PCast over them. */
curr = definedOfType(Ity_I32);
- /* Inputs: unmasked args */
+ /* Inputs: unmasked args
+ Note: arguments are evaluated REGARDLESS of the guard expression */
for (i = 0; d->args[i]; i++) {
if (d->cee->mcx_mask & (1<<i)) {
/* ignore this arg */
@@ -4052,34 +4439,46 @@
if (d->fxState[i].fx == Ifx_Write)
continue;
- /* Ignore any sections marked as 'always defined'. */
- if (isAlwaysDefd(mce, d->fxState[i].offset, d->fxState[i].size )) {
- if (0)
- VG_(printf)("memcheck: Dirty gst: ignored off %d, sz %d\n",
- d->fxState[i].offset, d->fxState[i].size );
- continue;
- }
+ /* Enumerate the described state segments */
+ for (k = 0; k < 1 + d->fxState[i].nRepeats; k++) {
+ gOff = d->fxState[i].offset + k * d->fxState[i].repeatLen;
+ gSz = d->fxState[i].size;
- /* This state element is read or modified. So we need to
- consider it. If larger than 8 bytes, deal with it in 8-byte
- chunks. */
- gSz = d->fxState[i].size;
- gOff = d->fxState[i].offset;
- tl_assert(gSz > 0);
- while (True) {
- if (gSz == 0) break;
- n = gSz <= 8 ? gSz : 8;
- /* update 'curr' with UifU of the state slice
- gOff .. gOff+n-1 */
- tySrc = szToITy( n );
- src = assignNew( 'V', mce, tySrc,
- shadow_GET(mce, gOff, tySrc ) );
- here = mkPCastTo( mce, Ity_I32, src );
- curr = mkUifU32(mce, here, curr);
- gSz -= n;
- gOff += n;
- }
+ /* Ignore any sections marked as 'always defined'. */
+ if (isAlwaysDefd(mce, gOff, gSz)) {
+ if (0)
+ VG_(printf)("memcheck: Dirty gst: ignored off %d, sz %d\n",
+ gOff, gSz);
+ continue;
+ }
+ /* This state element is read or modified. So we need to
+ consider it. If larger than 8 bytes, deal with it in
+ 8-byte chunks. */
+ while (True) {
+ tl_assert(gSz >= 0);
+ if (gSz == 0) break;
+ n = gSz <= 8 ? gSz : 8;
+ /* update 'curr' with UifU of the state slice
+ gOff .. gOff+n-1 */
+ tySrc = szToITy( n );
+
+ /* Observe the guard expression. If it is false use an
+ all-bits-defined bit pattern */
+ IRAtom *cond, *iffalse, *iftrue;
+
+ cond = assignNew('V', mce, Ity_I8, unop(Iop_1Uto8, d->guard));
+ iftrue = assignNew('V', mce, tySrc, shadow_GET(mce, gOff, tySrc));
+ iffalse = assignNew('V', mce, tySrc, definedOfType(tySrc));
+ src = assignNew('V', mce, tySrc,
+ IRExpr_Mux0X(cond, iffalse, iftrue));
+
+ here = mkPCastTo( mce, Ity_I32, src );
+ curr = mkUifU32(mce, here, curr);
+ gSz -= n;
+ gOff += n;
+ }
+ }
}
/* Inputs: memory. First set up some info needed regardless of
@@ -4092,7 +4491,7 @@
should remove all but this test. */
IRType tyAddr;
tl_assert(d->mAddr);
- complainIfUndefined(mce, d->mAddr);
+ complainIfUndefined(mce, d->mAddr, d->guard);
tyAddr = typeOfIRExpr(mce->sb->tyenv, d->mAddr);
tl_assert(tyAddr == Ity_I32 || tyAddr == Ity_I64);
@@ -4109,8 +4508,8 @@
while (toDo >= 4) {
here = mkPCastTo(
mce, Ity_I32,
- expr2vbits_Load ( mce, end, Ity_I32,
- d->mAddr, d->mSize - toDo )
+ expr2vbits_guarded_Load ( mce, end, Ity_I32, d->mAddr,
+ d->mSize - toDo, d->guard )
);
curr = mkUifU32(mce, here, curr);
toDo -= 4;
@@ -4119,13 +4518,23 @@
while (toDo >= 2) {
here = mkPCastTo(
mce, Ity_I32,
- expr2vbits_Load ( mce, end, Ity_I16,
- d->mAddr, d->mSize - toDo )
+ expr2vbits_guarded_Load ( mce, end, Ity_I16, d->mAddr,
+ d->mSize - toDo, d->guard )
);
curr = mkUifU32(mce, here, curr);
toDo -= 2;
}
- tl_assert(toDo == 0); /* also need to handle 1-byte excess */
+ /* chew off the remaining 8-bit chunk, if any */
+ if (toDo == 1) {
+ here = mkPCastTo(
+ mce, Ity_I32,
+ expr2vbits_guarded_Load ( mce, end, Ity_I8, d->mAddr,
+ d->mSize - toDo, d->guard )
+ );
+ curr = mkUifU32(mce, here, curr);
+ toDo -= 1;
+ }
+ tl_assert(toDo == 0);
}
/* Whew! So curr is a 32-bit V-value summarising pessimistically
@@ -4144,26 +4553,32 @@
tl_assert(d->fxState[i].fx != Ifx_None);
if (d->fxState[i].fx == Ifx_Read)
continue;
- /* Ignore any sections marked as 'always defined'. */
- if (isAlwaysDefd(mce, d->fxState[i].offset, d->fxState[i].size ))
- continue;
- /* This state element is written or modified. So we need to
- consider it. If larger than 8 bytes, deal with it in 8-byte
- chunks. */
- gSz = d->fxState[i].size;
- gOff = d->fxState[i].offset;
- tl_assert(gSz > 0);
- while (True) {
- if (gSz == 0) break;
- n = gSz <= 8 ? gSz : 8;
- /* Write suitably-casted 'curr' to the state slice
- gOff .. gOff+n-1 */
- tyDst = szToITy( n );
- do_shadow_PUT( mce, gOff,
- NULL, /* original atom */
- mkPCastTo( mce, tyDst, curr ) );
- gSz -= n;
- gOff += n;
+
+ /* Enumerate the described state segments */
+ for (k = 0; k < 1 + d->fxState[i].nRepeats; k++) {
+ gOff = d->fxState[i].offset + k * d->fxState[i].repeatLen;
+ gSz = d->fxState[i].size;
+
+ /* Ignore any sections marked as 'always defined'. */
+ if (isAlwaysDefd(mce, gOff, gSz))
+ continue;
+
+ /* This state element is written or modified. So we need to
+ consider it. If larger than 8 bytes, deal with it in
+ 8-byte chunks. */
+ while (True) {
+ tl_assert(gSz >= 0);
+ if (gSz == 0) break;
+ n = gSz <= 8 ? gSz : 8;
+ /* Write suitably-casted 'curr' to the state slice
+ gOff .. gOff+n-1 */
+ tyDst = szToITy( n );
+ do_shadow_PUT( mce, gOff,
+ NULL, /* original atom */
+ mkPCastTo( mce, tyDst, curr ), d->guard );
+ gSz -= n;
+ gOff += n;
+ }
}
}
@@ -4176,7 +4591,7 @@
do_shadow_Store( mce, end, d->mAddr, d->mSize - toDo,
NULL, /* original data */
mkPCastTo( mce, Ity_I32, curr ),
- NULL/*guard*/ );
+ d->guard );
toDo -= 4;
}
/* chew off 16-bit chunks */
@@ -4184,10 +4599,18 @@
do_shadow_Store( mce, end, d->mAddr, d->mSize - toDo,
NULL, /* original data */
mkPCastTo( mce, Ity_I16, curr ),
- NULL/*guard*/ );
+ d->guard );
toDo -= 2;
}
- tl_assert(toDo == 0); /* also need to handle 1-byte excess */
+ /* chew off the remaining 8-bit chunk, if any */
+ if (toDo == 1) {
+ do_shadow_Store( mce, end, d->mAddr, d->mSize - toDo,
+ NULL, /* original data */
+ mkPCastTo( mce, Ity_I8, curr ),
+ d->guard );
+ toDo -= 1;
+ }
+ tl_assert(toDo == 0);
}
}
@@ -4794,14 +5217,14 @@
return isBogusAtom(e->Iex.Binop.arg1)
|| isBogusAtom(e->Iex.Binop.arg2);
case Iex_Triop:
- return isBogusAtom(e->Iex.Triop.arg1)
- || isBogusAtom(e->Iex.Triop.arg2)
- || isBogusAtom(e->Iex.Triop.arg3);
+ return isBogusAtom(e->Iex.Triop.details->arg1)
+ || isBogusAtom(e->Iex.Triop.details->arg2)
+ || isBogusAtom(e->Iex.Triop.details->arg3);
case Iex_Qop:
- return isBogusAtom(e->Iex.Qop.arg1)
- || isBogusAtom(e->Iex.Qop.arg2)
- || isBogusAtom(e->Iex.Qop.arg3)
- || isBogusAtom(e->Iex.Qop.arg4);
+ return isBogusAtom(e->Iex.Qop.details->arg1)
+ || isBogusAtom(e->Iex.Qop.details->arg2)
+ || isBogusAtom(e->Iex.Qop.details->arg3)
+ || isBogusAtom(e->Iex.Qop.details->arg4);
case Iex_Mux0X:
return isBogusAtom(e->Iex.Mux0X.cond)
|| isBogusAtom(e->Iex.Mux0X.expr0)
@@ -4829,8 +5252,8 @@
case Ist_Put:
return isBogusAtom(st->Ist.Put.data);
case Ist_PutI:
- return isBogusAtom(st->Ist.PutI.ix)
- || isBogusAtom(st->Ist.PutI.data);
+ return isBogusAtom(st->Ist.PutI.details->ix)
+ || isBogusAtom(st->Ist.PutI.details->data);
case Ist_Store:
return isBogusAtom(st->Ist.Store.addr)
|| isBogusAtom(st->Ist.Store.data);
@@ -4907,6 +5330,20 @@
mce.hWordTy = hWordTy;
mce.bogusLiterals = False;
+ /* Do expensive interpretation for Iop_Add32 and Iop_Add64 on
+ Darwin. 10.7 is mostly built with LLVM, which uses these for
+ bitfield inserts, and we get a lot of false errors if the cheap
+ interpretation is used, alas. Could solve this much better if
+ we knew which of such adds came from x86/amd64 LEA instructions,
+ since these are the only ones really needing the expensive
+ interpretation, but that would require some way to tag them in
+ the _toIR.c front ends, which is a lot of faffing around. So
+ for now just use the slow and blunt-instrument solution. */
+ mce.useLLVMworkarounds = False;
+# if defined(VGO_darwin)
+ mce.useLLVMworkarounds = True;
+# endif
+
mce.tmpMap = VG_(newXA)( VG_(malloc), "mc.MC_(instrument).1", VG_(free),
sizeof(TempMapEnt));
for (i = 0; i < sb_in->tyenv->types_used; i++) {
@@ -5041,15 +5478,11 @@
do_shadow_PUT( &mce,
st->Ist.Put.offset,
st->Ist.Put.data,
- NULL /* shadow atom */ );
+ NULL /* shadow atom */, NULL /* guard */ );
break;
case Ist_PutI:
- do_shadow_PUTI( &mce,
- st->Ist.PutI.descr,
- st->Ist.PutI.ix,
- st->Ist.PutI.bias,
- st->Ist.PutI.data );
+ do_shadow_PUTI( &mce, st->Ist.PutI.details);
break;
case Ist_Store:
@@ -5061,7 +5494,7 @@
break;
case Ist_Exit:
- complainIfUndefined( &mce, st->Ist.Exit.guard );
+ complainIfUndefined( &mce, st->Ist.Exit.guard, NULL );
break;
case Ist_IMark:
@@ -5132,7 +5565,7 @@
VG_(printf)("\n\n");
}
- complainIfUndefined( &mce, sb_in->next );
+ complainIfUndefined( &mce, sb_in->next, NULL );
if (0 && verboze) {
for (j = first_stmt; j < sb_out->stmts_used; j++) {
@@ -5363,6 +5796,9 @@
case 16: hFun = (void*)&MC_(helperc_b_load16);
hName = "MC_(helperc_b_load16)";
break;
+ case 32: hFun = (void*)&MC_(helperc_b_load32);
+ hName = "MC_(helperc_b_load32)";
+ break;
default:
VG_(printf)("mc_translate.c: gen_load_b: unhandled szB == %d\n", szB);
tl_assert(0);
@@ -5385,6 +5821,23 @@
}
}
+static IRAtom* gen_guarded_load_b ( MCEnv* mce, Int szB, IRAtom* baseaddr,
+ Int offset, IRAtom* guard )
+{
+ if (guard) {
+ IRAtom *cond, *iffalse, *iftrue;
+
+ cond = assignNew('B', mce, Ity_I8, unop(Iop_1Uto8, guard));
+ iftrue = assignNew('B', mce, Ity_I32,
+ gen_load_b(mce, szB, baseaddr, offset));
+ iffalse = mkU32(0);
+
+ return assignNew('B', mce, Ity_I32, IRExpr_Mux0X(cond, iffalse, iftrue));
+ }
+
+ return gen_load_b(mce, szB, baseaddr, offset);
+}
+
/* Generate a shadow store. guard :: Ity_I1 controls whether the
store really happens; NULL means it unconditionally does. */
static void gen_store_b ( MCEnv* mce, Int szB,
@@ -5425,6 +5878,9 @@
case 16: hFun = (void*)&MC_(helperc_b_store16);
hName = "MC_(helperc_b_store16)";
break;
+ case 32: hFun = (void*)&MC_(helperc_b_store32);
+ hName = "MC_(helperc_b_store32)";
+ break;
default:
tl_assert(0);
}
@@ -5530,17 +5986,17 @@
return gen_maxU32( mce, b1, gen_maxU32( mce, b2, b3 ));
}
case Iex_Qop: {
- IRAtom* b1 = schemeE( mce, e->Iex.Qop.arg1 );
- IRAtom* b2 = schemeE( mce, e->Iex.Qop.arg2 );
- IRAtom* b3 = schemeE( mce, e->Iex.Qop.arg3 );
- IRAtom* b4 = schemeE( mce, e->Iex.Qop.arg4 );
+ IRAtom* b1 = schemeE( mce, e->Iex.Qop.details->arg1 );
+ IRAtom* b2 = schemeE( mce, e->Iex.Qop.details->arg2 );
+ IRAtom* b3 = schemeE( mce, e->Iex.Qop.details->arg3 );
+ IRAtom* b4 = schemeE( mce, e->Iex.Qop.details->arg4 );
return gen_maxU32( mce, gen_maxU32( mce, b1, b2 ),
gen_maxU32( mce, b3, b4 ) );
}
case Iex_Triop: {
- IRAtom* b1 = schemeE( mce, e->Iex.Triop.arg1 );
- IRAtom* b2 = schemeE( mce, e->Iex.Triop.arg2 );
- IRAtom* b3 = schemeE( mce, e->Iex.Triop.arg3 );
+ IRAtom* b1 = schemeE( mce, e->Iex.Triop.details->arg1 );
+ IRAtom* b2 = schemeE( mce, e->Iex.Triop.details->arg2 );
+ IRAtom* b3 = schemeE( mce, e->Iex.Triop.details->arg3 );
return gen_maxU32( mce, b1, gen_maxU32( mce, b2, b3 ) );
}
case Iex_Binop: {
@@ -5595,7 +6051,7 @@
static void do_origins_Dirty ( MCEnv* mce, IRDirty* d )
{
// This is a hacked version of do_shadow_Dirty
- Int i, n, toDo, gSz, gOff;
+ Int i, k, n, toDo, gSz, gOff;
IRAtom *here, *curr;
IRTemp dst;
@@ -5604,7 +6060,8 @@
/* Now round up all inputs and maxU32 over them. */
- /* Inputs: unmasked args */
+ /* Inputs: unmasked args
+ Note: arguments are evaluated REGARDLESS of the guard expression */
for (i = 0; d->args[i]; i++) {
if (d->cee->mcx_mask & (1<<i)) {
/* ignore this arg */
@@ -5620,38 +6077,49 @@
if (d->fxState[i].fx == Ifx_Write)
continue;
- /* Ignore any sections marked as 'always defined'. */
- if (isAlwaysDefd(mce, d->fxState[i].offset, d->fxState[i].size )) {
- if (0)
- VG_(printf)("memcheck: Dirty gst: ignored off %d, sz %d\n",
- d->fxState[i].offset, d->fxState[i].size );
- continue;
- }
+ /* Enumerate the described state segments */
+ for (k = 0; k < 1 + d->fxState[i].nRepeats; k++) {
+ gOff = d->fxState[i].offset + k * d->fxState[i].repeatLen;
+ gSz = d->fxState[i].size;
- /* This state element is read or modified. So we need to
- consider it. If larger than 4 bytes, deal with it in 4-byte
- chunks. */
- gSz = d->fxState[i].size;
- gOff = d->fxState[i].offset;
- tl_assert(gSz > 0);
- while (True) {
- Int b_offset;
- if (gSz == 0) break;
- n = gSz <= 4 ? gSz : 4;
- /* update 'curr' with maxU32 of the state slice
- gOff .. gOff+n-1 */
- b_offset = MC_(get_otrack_shadow_offset)(gOff, 4);
- if (b_offset != -1) {
- here = assignNew( 'B',mce,
- Ity_I32,
- IRExpr_Get(b_offset + 2*mce->layout->total_sizeB,
- Ity_I32));
- curr = gen_maxU32( mce, curr, here );
+ /* Ignore any sections marked as 'always defined'. */
+ if (isAlwaysDefd(mce, gOff, gSz)) {
+ if (0)
+ VG_(printf)("memcheck: Dirty gst: ignored off %d, sz %d\n",
+ gOff, gSz);
+ continue;
}
- gSz -= n;
- gOff += n;
- }
+ /* This state element is read or modified. So we need to
+ consider it. If larger than 4 bytes, deal with it in
+ 4-byte chunks. */
+ while (True) {
+ Int b_offset;
+ tl_assert(gSz >= 0);
+ if (gSz == 0) break;
+ n = gSz <= 4 ? gSz : 4;
+ /* update 'curr' with maxU32 of the state slice
+ gOff .. gOff+n-1 */
+ b_offset = MC_(get_otrack_shadow_offset)(gOff, 4);
+ if (b_offset != -1) {
+ /* Observe the guard expression. If it is false use 0, i.e.
+ nothing is known about the origin */
+ IRAtom *cond, *iffalse, *iftrue;
+
+ cond = assignNew( 'B', mce, Ity_I8, unop(Iop_1Uto8, d->guard));
+ iffalse = mkU32(0);
+ iftrue = assignNew( 'B', mce, Ity_I32,
+ IRExpr_Get(b_offset
+ + 2*mce->layout->total_sizeB,
+ Ity_I32));
+ here = assignNew( 'B', mce, Ity_I32,
+ IRExpr_Mux0X(cond, iffalse, iftrue));
+ curr = gen_maxU32( mce, curr, here );
+ }
+ gSz -= n;
+ gOff += n;
+ }
+ }
}
/* Inputs: memory */
@@ -5674,17 +6142,26 @@
but nevertheless choose an endianness which is hopefully
native to the platform. */
while (toDo >= 4) {
- here = gen_load_b( mce, 4, d->mAddr, d->mSize - toDo );
+ here = gen_guarded_load_b( mce, 4, d->mAddr, d->mSize - toDo,
+ d->guard );
curr = gen_maxU32( mce, curr, here );
toDo -= 4;
}
/* handle possible 16-bit excess */
while (toDo >= 2) {
- here = gen_load_b( mce, 2, d->mAddr, d->mSize - toDo );
+ here = gen_guarded_load_b( mce, 2, d->mAddr, d->mSize - toDo,
+ d->guard );
curr = gen_maxU32( mce, curr, here );
toDo -= 2;
}
- tl_assert(toDo == 0); /* also need to handle 1-byte excess */
+ /* chew off the remaining 8-bit chunk, if any */
+ if (toDo == 1) {
+ here = gen_guarded_load_b( mce, 1, d->mAddr, d->mSize - toDo,
+ d->guard );
+ curr = gen_maxU32( mce, curr, here );
+ toDo -= 1;
+ }
+ tl_assert(toDo == 0);
}
/* Whew! So curr is a 32-bit B-value which should give an origin
@@ -5703,28 +6180,47 @@
if (d->fxState[i].fx == Ifx_Read)
continue;
- /* Ignore any sections marked as 'always defined'. */
- if (isAlwaysDefd(mce, d->fxState[i].offset, d->fxState[i].size ))
- continue;
+ /* Enumerate the described state segments */
+ for (k = 0; k < 1 + d->fxState[i].nRepeats; k++) {
+ gOff = d->fxState[i].offset + k * d->fxState[i].repeatLen;
+ gSz = d->fxState[i].size;
- /* This state element is written or modified. So we need to
- consider it. If larger than 4 bytes, deal with it in 4-byte
- chunks. */
- gSz = d->fxState[i].size;
- gOff = d->fxState[i].offset;
- tl_assert(gSz > 0);
- while (True) {
- Int b_offset;
- if (gSz == 0) break;
- n = gSz <= 4 ? gSz : 4;
- /* Write 'curr' to the state slice gOff .. gOff+n-1 */
- b_offset = MC_(get_otrack_shadow_offset)(gOff, 4);
- if (b_offset != -1) {
- stmt( 'B', mce, IRStmt_Put(b_offset + 2*mce->layout->total_sizeB,
- curr ));
+ /* Ignore any sections marked as 'always defined'. */
+ if (isAlwaysDefd(mce, gOff, gSz))
+ continue;
+
+ /* This state element is written or modified. So we need to
+ consider it. If larger than 4 bytes, deal with it in
+ 4-byte chunks. */
+ while (True) {
+ Int b_offset;
+ tl_assert(gSz >= 0);
+ if (gSz == 0) break;
+ n = gSz <= 4 ? gSz : 4;
+ /* Write 'curr' to the state slice gOff .. gOff+n-1 */
+ b_offset = MC_(get_otrack_shadow_offset)(gOff, 4);
+ if (b_offset != -1) {
+ if (d->guard) {
+ /* If the guard expression evaluates to false we simply Put
+ the value that is already stored in the guest state slot */
+ IRAtom *cond, *iffalse;
+
+ cond = assignNew('B', mce, Ity_I8,
+ unop(Iop_1Uto8, d->guard));
+ iffalse = assignNew('B', mce, Ity_I32,
+ IRExpr_Get(b_offset +
+ 2*mce->layout->total_sizeB,
+ Ity_I32));
+ curr = assignNew('V', mce, Ity_I32,
+ IRExpr_Mux0X(cond, iffalse, curr));
+ }
+ stmt( 'B', mce, IRStmt_Put(b_offset
+ + 2*mce->layout->total_sizeB,
+ curr ));
+ }
+ gSz -= n;
+ gOff += n;
}
- gSz -= n;
- gOff += n;
}
}
@@ -5735,16 +6231,22 @@
/* chew off 32-bit chunks */
while (toDo >= 4) {
gen_store_b( mce, 4, d->mAddr, d->mSize - toDo, curr,
- NULL/*guard*/ );
+ d->guard );
toDo -= 4;
}
/* handle possible 16-bit excess */
while (toDo >= 2) {
gen_store_b( mce, 2, d->mAddr, d->mSize - toDo, curr,
- NULL/*guard*/ );
+ d->guard );
toDo -= 2;
}
- tl_assert(toDo == 0); /* also need to handle 1-byte excess */
+ /* chew off the remaining 8-bit chunk, if any */
+ if (toDo == 1) {
+ gen_store_b( mce, 1, d->mAddr, d->mSize - toDo, curr,
+ d->guard );
+ toDo -= 1;
+ }
+ tl_assert(toDo == 0);
}
}
@@ -5783,9 +6285,10 @@
break;
case Ist_PutI: {
+ IRPutI *puti = st->Ist.PutI.details;
IRRegArray* descr_b;
IRAtom *t1, *t2, *t3, *t4;
- IRRegArray* descr = st->Ist.PutI.descr;
+ IRRegArray* descr = puti->descr;
IRType equivIntTy
= MC_(get_otrack_reg_array_equiv_int_type)(descr);
/* If this array is unshadowable for whatever reason,
@@ -5800,12 +6303,12 @@
/* Compute a value to Put - the conjoinment of the origin for
the data to be Put-ted (obviously) and of the index value
(not so obviously). */
- t1 = schemeE( mce, st->Ist.PutI.data );
- t2 = schemeE( mce, st->Ist.PutI.ix );
+ t1 = schemeE( mce, puti->data );
+ t2 = schemeE( mce, puti->ix );
t3 = gen_maxU32( mce, t1, t2 );
t4 = zWidenFrom32( mce, equivIntTy, t3 );
- stmt( 'B', mce, IRStmt_PutI( descr_b, st->Ist.PutI.ix,
- st->Ist.PutI.bias, t4 ));
+ stmt( 'B', mce, IRStmt_PutI( mkIRPutI(descr_b, puti->ix,
+ puti->bias, t4) ));
break;
}
diff --git a/main/memcheck/memcheck.h b/main/memcheck/memcheck.h
index 68474b4..fcc7644 100644
--- a/main/memcheck/memcheck.h
+++ b/main/memcheck/memcheck.h
@@ -13,7 +13,7 @@
This file is part of MemCheck, a heavyweight Valgrind tool for
detecting memory errors.
- Copyright (C) 2000-2011 Julian Seward. All rights reserved.
+ Copyright (C) 2000-2012 Julian Seward. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
diff --git a/main/memcheck/perf/Makefile.am b/main/memcheck/perf/Makefile.am
deleted file mode 100644
index ab6a5c7..0000000
--- a/main/memcheck/perf/Makefile.am
+++ /dev/null
@@ -1,11 +0,0 @@
-
-include $(top_srcdir)/Makefile.tool-tests.am
-
-EXTRA_DIST = \
- many-loss-records.vgperf
-
-check_PROGRAMS = \
- many-loss-records
-
-AM_CFLAGS += -O $(AM_FLAG_M3264_PRI)
-AM_CXXFLAGS += -O $(AM_FLAG_M3264_PRI)
diff --git a/main/memcheck/perf/many-loss-records.c b/main/memcheck/perf/many-loss-records.c
deleted file mode 100644
index 5296e31..0000000
--- a/main/memcheck/perf/many-loss-records.c
+++ /dev/null
@@ -1,214 +0,0 @@
-// Performance test for the leak checker from bug #191182.
-// Nb: it must be run with --leak-resolution=high to show the quadratic
-// behaviour caused by the large number of loss records.
-// By Philippe Waroquiers.
-//
-// On my machine, before being fixed, building the loss record list took about
-// 36 seconds, and sorting + printing it took about 20 seconds. After being
-// fixed it took about 2 seconds, and the leak checking was only a small
-// fraction of that. --njn
-
-#include <stdlib.h>
-#include <strings.h>
-#include <stdio.h>
-#include <math.h>
-
-/* parameters */
-
-/* we will create stack_fan_out ^ stack_depth different call stacks */
-int stack_fan_out = 15;
-int stack_depth = 4;
-
-/* for each call stack, allocate malloc_fan blocks */
-int malloc_fan = 4;
-
-/* for each call stack, allocate data structures having malloc_depth
- indirection at each malloc-ed level */
-int malloc_depth = 2;
-
-/* in addition to the pointer needed to maintain the levels; some more
- bytes are allocated simulating the data stored in the data structure */
-int malloc_data = 5;
-
-/* every n top blocks, 1 block and all its children will be freed instead of
- being kept */
-int free_every_n = 2;
-
-/* every n release block operation, 1 block and its children will be leaked */
-int leak_every_n = 250;
-
-
-
-struct Chunk {
- struct Chunk* child;
- char s[];
-};
-
-struct Chunk** topblocks;
-int freetop = 0;
-
-/* statistics */
-long total_malloced = 0;
-int blocknr = 0;
-int blockfreed = 0;
-int blockleaked = 0;
-int total_stacks = 0;
-int releaseop = 0;
-
-void free_chunks (struct Chunk ** mem)
-{
- if (*mem == 0)
- return;
-
- free_chunks ((&(*mem)->child));
-
- blockfreed++;
- free (*mem);
- *mem = 0;
-}
-
-void release (struct Chunk ** mem)
-{
- releaseop++;
-
- if (releaseop % leak_every_n == 0) {
- blockleaked++;
- *mem = 0; // lose the pointer without free-ing the blocks
- } else {
- free_chunks (mem);
- }
-}
-
-void call_stack (int level)
-{
- int call_fan_out = 1;
-
- if (level == stack_depth) {
- int sz = sizeof(struct Chunk*) + malloc_data;
- int d;
- int f;
-
- for (f = 0; f < malloc_fan; f++) {
- struct Chunk *new = NULL; // shut gcc up
- struct Chunk *prev = NULL;
-
- for (d = 0; d < malloc_depth; d++) {
- new = malloc (sz);
- total_malloced += sz;
- blocknr++;
- new->child = prev;
- prev = new;
- }
- topblocks[freetop] = new;
-
- if (freetop % free_every_n == 0) {
- release (&topblocks[freetop]);
- }
- freetop++;
- }
-
- total_stacks++;
-
- } else {
- /* Nb: don't common these up into a loop! We need different code
- locations to exercise the problem. */
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- call_stack (level + 1);
- if (call_fan_out == stack_fan_out) return;
- call_fan_out++;
-
- printf ("maximum stack_fan_out exceeded\n");
- }
-}
-
-int main()
-{
- int d;
- int stacks = 1;
- for (d = 0; d < stack_depth; d++)
- stacks *= stack_fan_out;
- printf ("will generate %d different stacks\n", stacks);
- topblocks = malloc(sizeof(struct Chunk*) * stacks * malloc_fan);
- call_stack (0);
- printf ("total stacks %d\n", total_stacks);
- printf ("total bytes malloc-ed: %ld\n", total_malloced);
- printf ("total blocks malloc-ed: %d\n", blocknr);
- printf ("total blocks free-ed: %d\n", blockfreed);
- printf ("total blocks leak-ed: %d\n", blockleaked);
- return 0;
-}
diff --git a/main/memcheck/perf/many-loss-records.vgperf b/main/memcheck/perf/many-loss-records.vgperf
deleted file mode 100644
index 37d4f49..0000000
--- a/main/memcheck/perf/many-loss-records.vgperf
+++ /dev/null
@@ -1,2 +0,0 @@
-prog: many-loss-records
-vgopts: --leak-check=yes --leak-resolution=high
diff --git a/main/memcheck/tests/Makefile.am b/main/memcheck/tests/Makefile.am
index 02f0df1..52ac386 100644
--- a/main/memcheck/tests/Makefile.am
+++ b/main/memcheck/tests/Makefile.am
@@ -10,13 +10,15 @@
if VGCONF_ARCHS_INCLUDE_AMD64
SUBDIRS += amd64
endif
-
if VGCONF_ARCHS_INCLUDE_PPC32
SUBDIRS += ppc32
endif
if VGCONF_ARCHS_INCLUDE_PPC64
SUBDIRS += ppc64
endif
+if VGCONF_ARCHS_INCLUDE_S390X
+SUBDIRS += s390x
+endif
# OS-specific tests
if VGCONF_OS_IS_LINUX
@@ -34,7 +36,7 @@
SUBDIRS += amd64-linux
endif
-DIST_SUBDIRS = x86 amd64 ppc32 ppc64 linux darwin x86-linux amd64-linux .
+DIST_SUBDIRS = x86 amd64 ppc32 ppc64 s390x linux darwin x86-linux amd64-linux .
dist_noinst_SCRIPTS = \
filter_addressable \
@@ -47,6 +49,7 @@
noinst_HEADERS = leak.h
EXTRA_DIST = \
+ accounting.stderr.exp accounting.vgtest \
addressable.stderr.exp addressable.stdout.exp addressable.vgtest \
atomic_incs.stderr.exp atomic_incs.vgtest \
atomic_incs.stdout.exp-32bit atomic_incs.stdout.exp-64bit \
@@ -54,6 +57,7 @@
badaddrvalue.stdout.exp badaddrvalue.vgtest \
badfree-2trace.stderr.exp badfree-2trace.vgtest \
badfree.stderr.exp badfree.vgtest \
+ badfree3.stderr.exp badfree3.vgtest \
badjump.stderr.exp badjump.vgtest \
badjump2.stderr.exp badjump2.vgtest \
badjump.stderr.exp-kfail \
@@ -64,15 +68,22 @@
big_blocks_freed_list.stderr.exp big_blocks_freed_list.vgtest \
brk2.stderr.exp brk2.vgtest \
buflen_check.stderr.exp buflen_check.vgtest buflen_check.stderr.exp-kfail \
+ bug287260.stderr.exp bug287260.vgtest \
calloc-overflow.stderr.exp calloc-overflow.vgtest\
clientperm.stderr.exp \
clientperm.stdout.exp clientperm.vgtest \
+ clireq_nofill.stderr.exp \
+ clireq_nofill.stdout.exp clireq_nofill.vgtest \
+ clo_redzone_default.vgtest clo_redzone_128.vgtest \
+ clo_redzone_default.stderr.exp clo_redzone_128.stderr.exp \
custom_alloc.stderr.exp custom_alloc.vgtest custom_alloc.stderr.exp-s390x-mvc \
custom-overlap.stderr.exp custom-overlap.vgtest \
+ deep-backtrace.vgtest deep-backtrace.stderr.exp \
deep_templates.vgtest \
deep_templates.stdout.exp deep_templates.stderr.exp \
describe-block.stderr.exp describe-block.vgtest \
doublefree.stderr.exp doublefree.vgtest \
+ dw4.vgtest dw4.stderr.exp dw4.stdout.exp \
err_disable1.vgtest err_disable1.stderr.exp \
err_disable2.vgtest err_disable2.stderr.exp \
err_disable3.vgtest err_disable3.stderr.exp \
@@ -171,11 +182,13 @@
sh-mem-random.stderr.exp sh-mem-random.stdout.exp64 \
sh-mem-random.stdout.exp sh-mem-random.vgtest \
sigaltstack.stderr.exp sigaltstack.vgtest \
- sigkill.stderr.exp sigkill.stderr.exp-darwin sigkill.vgtest \
+ sigkill.stderr.exp sigkill.stderr.exp-darwin sigkill.stderr.exp-mips32 \
+ sigkill.vgtest \
signal2.stderr.exp signal2.stdout.exp signal2.vgtest \
sigprocmask.stderr.exp sigprocmask.stderr.exp2 sigprocmask.vgtest \
+ static_malloc.stderr.exp static_malloc.vgtest \
strchr.stderr.exp strchr.stderr.exp2 strchr.stderr.exp-darwin \
- strchr.vgtest \
+ strchr.stderr.exp3 strchr.vgtest \
str_tester.stderr.exp str_tester.vgtest \
supp-dir.vgtest supp-dir.stderr.exp \
supp_unknown.stderr.exp supp_unknown.vgtest supp_unknown.supp \
@@ -183,16 +196,21 @@
supp1.stderr.exp supp1.vgtest \
supp2.stderr.exp supp2.vgtest \
supp.supp \
- suppfree.stderr.exp suppfree.vgtest \
+ suppfree.stderr.exp suppfree.supp suppfree.vgtest \
+ test-plo-no.vgtest test-plo-no.stdout.exp \
+ test-plo-no.stderr.exp-le64 test-plo-no.stderr.exp-le32 \
+ test-plo-yes.vgtest test-plo-yes.stdout.exp \
+ test-plo-yes.stderr.exp-le64 test-plo-yes.stderr.exp-le32 \
+ test-plo-no.stderr.exp-s390x-mvc \
trivialleak.stderr.exp trivialleak.vgtest trivialleak.stderr.exp2 \
unit_libcbase.stderr.exp unit_libcbase.vgtest \
unit_oset.stderr.exp unit_oset.stdout.exp unit_oset.vgtest \
- varinfo1.vgtest varinfo1.stdout.exp varinfo1.stderr.exp varinfo1.stderr.exp-ppc64\
- varinfo2.vgtest varinfo2.stdout.exp varinfo2.stderr.exp varinfo2.stderr.exp-ppc64\
- varinfo3.vgtest varinfo3.stdout.exp varinfo3.stderr.exp varinfo3.stderr.exp-ppc64\
- varinfo4.vgtest varinfo4.stdout.exp varinfo4.stderr.exp varinfo4.stderr.exp-ppc64\
- varinfo5.vgtest varinfo5.stdout.exp varinfo5.stderr.exp varinfo5.stderr.exp-ppc64\
- varinfo6.vgtest varinfo6.stdout.exp varinfo6.stderr.exp varinfo6.stderr.exp-ppc64\
+ varinfo1.vgtest varinfo1.stdout.exp varinfo1.stderr.exp varinfo1.stderr.exp-ppc64 \
+ varinfo2.vgtest varinfo2.stdout.exp varinfo2.stderr.exp varinfo2.stderr.exp-ppc64 \
+ varinfo3.vgtest varinfo3.stdout.exp varinfo3.stderr.exp varinfo3.stderr.exp-ppc64 \
+ varinfo4.vgtest varinfo4.stdout.exp varinfo4.stderr.exp varinfo4.stderr.exp-ppc64 \
+ varinfo5.vgtest varinfo5.stdout.exp varinfo5.stderr.exp varinfo5.stderr.exp-ppc64 \
+ varinfo6.vgtest varinfo6.stdout.exp varinfo6.stderr.exp varinfo6.stderr.exp-ppc64 \
vcpu_bz2.stdout.exp vcpu_bz2.stderr.exp vcpu_bz2.vgtest \
vcpu_fbench.stdout.exp vcpu_fbench.stderr.exp vcpu_fbench.vgtest \
vcpu_fnfns.stdout.exp vcpu_fnfns.stdout.exp-glibc28-amd64 \
@@ -210,6 +228,7 @@
xml1.stderr.exp xml1.stdout.exp xml1.vgtest xml1.stderr.exp-s390x-mvc
check_PROGRAMS = \
+ accounting \
addressable \
atomic_incs \
badaddrvalue badfree badjump badjump2 \
@@ -219,10 +238,14 @@
big_blocks_freed_list \
brk2 \
buflen_check \
+ bug287260 \
calloc-overflow \
clientperm \
+ clireq_nofill \
+ clo_redzone \
custom_alloc \
custom-overlap \
+ deep-backtrace \
deep_templates \
describe-block \
doublefree error_counts errs1 exitprog execve1 execve2 erringfds \
@@ -257,10 +280,11 @@
realloc1 realloc2 realloc3 \
sbfragment \
sh-mem sh-mem-random \
- sigaltstack signal2 sigprocmask sigkill \
+ sigaltstack signal2 sigprocmask static_malloc sigkill \
strchr \
str_tester \
supp_unknown supp1 supp2 suppfree \
+ test-plo \
trivialleak \
unit_libcbase unit_oset \
varinfo1 varinfo2 varinfo3 varinfo4 \
@@ -270,13 +294,16 @@
wrap1 wrap2 wrap3 wrap4 wrap5 wrap6 wrap7 wrap7so.so wrap8 \
writev1
+if DWARF4
+check_PROGRAMS += dw4
+endif
AM_CFLAGS += $(AM_FLAG_M3264_PRI)
AM_CXXFLAGS += $(AM_FLAG_M3264_PRI)
if VGCONF_PLATFORMS_INCLUDE_ARM_LINUX
-AM_CFLAGS += -mfloat-abi=softfp
-AM_CXXFLAGS += -mfloat-abi=softfp
+#AM_CFLAGS += -mfloat-abi=softfp
+#AM_CXXFLAGS += -mfloat-abi=softfp
endif
if VGCONF_OS_IS_DARWIN
@@ -288,6 +315,8 @@
deep_templates_SOURCES = deep_templates.cpp
deep_templates_CXXFLAGS = $(AM_CFLAGS) -O -gstabs
+dw4_CFLAGS = $(AM_CFLAGS) -gdwarf-4 -fdebug-types-section
+
err_disable3_LDADD = -lpthread
err_disable4_LDADD = -lpthread
diff --git a/main/memcheck/tests/Makefile.in b/main/memcheck/tests/Makefile.in
new file mode 100644
index 0000000..d0f42f3
--- /dev/null
+++ b/main/memcheck/tests/Makefile.in
@@ -0,0 +1,2587 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(noinst_HEADERS) \
+ $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Arch-specific tests.
+@VGCONF_ARCHS_INCLUDE_X86_TRUE@am__append_3 = x86
+@VGCONF_ARCHS_INCLUDE_AMD64_TRUE@am__append_4 = amd64
+@VGCONF_ARCHS_INCLUDE_PPC32_TRUE@am__append_5 = ppc32
+@VGCONF_ARCHS_INCLUDE_PPC64_TRUE@am__append_6 = ppc64
+@VGCONF_ARCHS_INCLUDE_S390X_TRUE@am__append_7 = s390x
+
+# OS-specific tests
+@VGCONF_OS_IS_LINUX_TRUE@am__append_8 = linux
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_9 = darwin
+
+# Platform-specific tests
+@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_10 = x86-linux
+@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_11 = amd64-linux
+check_PROGRAMS = accounting$(EXEEXT) addressable$(EXEEXT) \
+ atomic_incs$(EXEEXT) badaddrvalue$(EXEEXT) badfree$(EXEEXT) \
+ badjump$(EXEEXT) badjump2$(EXEEXT) badloop$(EXEEXT) \
+ badpoll$(EXEEXT) badrw$(EXEEXT) big_blocks_freed_list$(EXEEXT) \
+ brk2$(EXEEXT) buflen_check$(EXEEXT) bug287260$(EXEEXT) \
+ calloc-overflow$(EXEEXT) clientperm$(EXEEXT) \
+ clireq_nofill$(EXEEXT) clo_redzone$(EXEEXT) \
+ custom_alloc$(EXEEXT) custom-overlap$(EXEEXT) \
+ deep-backtrace$(EXEEXT) deep_templates$(EXEEXT) \
+ describe-block$(EXEEXT) doublefree$(EXEEXT) \
+ error_counts$(EXEEXT) errs1$(EXEEXT) exitprog$(EXEEXT) \
+ execve1$(EXEEXT) execve2$(EXEEXT) erringfds$(EXEEXT) \
+ err_disable1$(EXEEXT) err_disable2$(EXEEXT) \
+ err_disable3$(EXEEXT) err_disable4$(EXEEXT) \
+ file_locking$(EXEEXT) fprw$(EXEEXT) fwrite$(EXEEXT) \
+ inits$(EXEEXT) inline$(EXEEXT) holey_buffer_too_small$(EXEEXT) \
+ leak-0$(EXEEXT) leak-cases$(EXEEXT) leak-cycle$(EXEEXT) \
+ leak-delta$(EXEEXT) leak-pool$(EXEEXT) leak-tree$(EXEEXT) \
+ long_namespace_xml$(EXEEXT) long-supps$(EXEEXT) \
+ mallinfo$(EXEEXT) malloc_free_fill$(EXEEXT) \
+ malloc_usable$(EXEEXT) malloc1$(EXEEXT) malloc2$(EXEEXT) \
+ malloc3$(EXEEXT) manuel1$(EXEEXT) manuel2$(EXEEXT) \
+ manuel3$(EXEEXT) match-overrun$(EXEEXT) memalign_test$(EXEEXT) \
+ memalign2$(EXEEXT) memcmptest$(EXEEXT) mempool$(EXEEXT) \
+ mempool2$(EXEEXT) mmaptest$(EXEEXT) mismatches$(EXEEXT) \
+ new_override$(EXEEXT) metadata$(EXEEXT) nanoleak_supp$(EXEEXT) \
+ nanoleak2$(EXEEXT) new_nothrow$(EXEEXT) noisy_child$(EXEEXT) \
+ null_socket$(EXEEXT) origin1-yes$(EXEEXT) \
+ origin2-not-quite$(EXEEXT) origin3-no$(EXEEXT) \
+ origin4-many$(EXEEXT) origin5-bz2$(EXEEXT) origin6-fp$(EXEEXT) \
+ overlap$(EXEEXT) partiallydefinedeq$(EXEEXT) \
+ partial_load$(EXEEXT) pdb-realloc$(EXEEXT) \
+ pdb-realloc2$(EXEEXT) pipe$(EXEEXT) pointer-trace$(EXEEXT) \
+ post-syscall$(EXEEXT) realloc1$(EXEEXT) realloc2$(EXEEXT) \
+ realloc3$(EXEEXT) sbfragment$(EXEEXT) sh-mem$(EXEEXT) \
+ sh-mem-random$(EXEEXT) sigaltstack$(EXEEXT) signal2$(EXEEXT) \
+ sigprocmask$(EXEEXT) static_malloc$(EXEEXT) sigkill$(EXEEXT) \
+ strchr$(EXEEXT) str_tester$(EXEEXT) supp_unknown$(EXEEXT) \
+ supp1$(EXEEXT) supp2$(EXEEXT) suppfree$(EXEEXT) \
+ test-plo$(EXEEXT) trivialleak$(EXEEXT) unit_libcbase$(EXEEXT) \
+ unit_oset$(EXEEXT) varinfo1$(EXEEXT) varinfo2$(EXEEXT) \
+ varinfo3$(EXEEXT) varinfo4$(EXEEXT) varinfo5$(EXEEXT) \
+ varinfo5so.so$(EXEEXT) varinfo6$(EXEEXT) vcpu_fbench$(EXEEXT) \
+ vcpu_fnfns$(EXEEXT) xml1$(EXEEXT) wrap1$(EXEEXT) \
+ wrap2$(EXEEXT) wrap3$(EXEEXT) wrap4$(EXEEXT) wrap5$(EXEEXT) \
+ wrap6$(EXEEXT) wrap7$(EXEEXT) wrap7so.so$(EXEEXT) \
+ wrap8$(EXEEXT) writev1$(EXEEXT) $(am__EXEEXT_1)
+@DWARF4_TRUE@am__append_12 = dw4
+subdir = memcheck/tests
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@DWARF4_TRUE@am__EXEEXT_1 = dw4$(EXEEXT)
+accounting_SOURCES = accounting.c
+accounting_OBJECTS = accounting.$(OBJEXT)
+accounting_LDADD = $(LDADD)
+addressable_SOURCES = addressable.c
+addressable_OBJECTS = addressable.$(OBJEXT)
+addressable_LDADD = $(LDADD)
+atomic_incs_SOURCES = atomic_incs.c
+atomic_incs_OBJECTS = atomic_incs-atomic_incs.$(OBJEXT)
+atomic_incs_LDADD = $(LDADD)
+atomic_incs_LINK = $(CCLD) $(atomic_incs_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+badaddrvalue_SOURCES = badaddrvalue.c
+badaddrvalue_OBJECTS = badaddrvalue.$(OBJEXT)
+badaddrvalue_LDADD = $(LDADD)
+badfree_SOURCES = badfree.c
+badfree_OBJECTS = badfree.$(OBJEXT)
+badfree_LDADD = $(LDADD)
+badjump_SOURCES = badjump.c
+badjump_OBJECTS = badjump.$(OBJEXT)
+badjump_LDADD = $(LDADD)
+badjump2_SOURCES = badjump2.c
+badjump2_OBJECTS = badjump2.$(OBJEXT)
+badjump2_LDADD = $(LDADD)
+badloop_SOURCES = badloop.c
+badloop_OBJECTS = badloop.$(OBJEXT)
+badloop_LDADD = $(LDADD)
+badpoll_SOURCES = badpoll.c
+badpoll_OBJECTS = badpoll.$(OBJEXT)
+badpoll_LDADD = $(LDADD)
+badrw_SOURCES = badrw.c
+badrw_OBJECTS = badrw.$(OBJEXT)
+badrw_LDADD = $(LDADD)
+big_blocks_freed_list_SOURCES = big_blocks_freed_list.c
+big_blocks_freed_list_OBJECTS = big_blocks_freed_list.$(OBJEXT)
+big_blocks_freed_list_LDADD = $(LDADD)
+brk2_SOURCES = brk2.c
+brk2_OBJECTS = brk2.$(OBJEXT)
+brk2_LDADD = $(LDADD)
+buflen_check_SOURCES = buflen_check.c
+buflen_check_OBJECTS = buflen_check.$(OBJEXT)
+buflen_check_LDADD = $(LDADD)
+bug287260_SOURCES = bug287260.c
+bug287260_OBJECTS = bug287260.$(OBJEXT)
+bug287260_LDADD = $(LDADD)
+calloc_overflow_SOURCES = calloc-overflow.c
+calloc_overflow_OBJECTS = calloc-overflow.$(OBJEXT)
+calloc_overflow_LDADD = $(LDADD)
+clientperm_SOURCES = clientperm.c
+clientperm_OBJECTS = clientperm.$(OBJEXT)
+clientperm_LDADD = $(LDADD)
+clireq_nofill_SOURCES = clireq_nofill.c
+clireq_nofill_OBJECTS = clireq_nofill.$(OBJEXT)
+clireq_nofill_LDADD = $(LDADD)
+clo_redzone_SOURCES = clo_redzone.c
+clo_redzone_OBJECTS = clo_redzone.$(OBJEXT)
+clo_redzone_LDADD = $(LDADD)
+custom_overlap_SOURCES = custom-overlap.c
+custom_overlap_OBJECTS = custom-overlap.$(OBJEXT)
+custom_overlap_LDADD = $(LDADD)
+custom_alloc_SOURCES = custom_alloc.c
+custom_alloc_OBJECTS = custom_alloc.$(OBJEXT)
+custom_alloc_LDADD = $(LDADD)
+deep_backtrace_SOURCES = deep-backtrace.c
+deep_backtrace_OBJECTS = deep-backtrace.$(OBJEXT)
+deep_backtrace_LDADD = $(LDADD)
+am_deep_templates_OBJECTS = deep_templates-deep_templates.$(OBJEXT)
+deep_templates_OBJECTS = $(am_deep_templates_OBJECTS)
+deep_templates_LDADD = $(LDADD)
+deep_templates_LINK = $(CXXLD) $(deep_templates_CXXFLAGS) $(CXXFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+describe_block_SOURCES = describe-block.c
+describe_block_OBJECTS = describe-block.$(OBJEXT)
+describe_block_LDADD = $(LDADD)
+doublefree_SOURCES = doublefree.c
+doublefree_OBJECTS = doublefree.$(OBJEXT)
+doublefree_LDADD = $(LDADD)
+dw4_SOURCES = dw4.c
+dw4_OBJECTS = dw4-dw4.$(OBJEXT)
+dw4_LDADD = $(LDADD)
+dw4_LINK = $(CCLD) $(dw4_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o \
+ $@
+err_disable1_SOURCES = err_disable1.c
+err_disable1_OBJECTS = err_disable1.$(OBJEXT)
+err_disable1_LDADD = $(LDADD)
+err_disable2_SOURCES = err_disable2.c
+err_disable2_OBJECTS = err_disable2.$(OBJEXT)
+err_disable2_LDADD = $(LDADD)
+err_disable3_SOURCES = err_disable3.c
+err_disable3_OBJECTS = err_disable3.$(OBJEXT)
+err_disable3_DEPENDENCIES =
+err_disable4_SOURCES = err_disable4.c
+err_disable4_OBJECTS = err_disable4.$(OBJEXT)
+err_disable4_DEPENDENCIES =
+erringfds_SOURCES = erringfds.c
+erringfds_OBJECTS = erringfds.$(OBJEXT)
+erringfds_LDADD = $(LDADD)
+error_counts_SOURCES = error_counts.c
+error_counts_OBJECTS = error_counts-error_counts.$(OBJEXT)
+error_counts_LDADD = $(LDADD)
+error_counts_LINK = $(CCLD) $(error_counts_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+errs1_SOURCES = errs1.c
+errs1_OBJECTS = errs1.$(OBJEXT)
+errs1_LDADD = $(LDADD)
+execve1_SOURCES = execve1.c
+execve1_OBJECTS = execve1-execve1.$(OBJEXT)
+execve1_LDADD = $(LDADD)
+execve1_LINK = $(CCLD) $(execve1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+execve2_SOURCES = execve2.c
+execve2_OBJECTS = execve2-execve2.$(OBJEXT)
+execve2_LDADD = $(LDADD)
+execve2_LINK = $(CCLD) $(execve2_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+exitprog_SOURCES = exitprog.c
+exitprog_OBJECTS = exitprog.$(OBJEXT)
+exitprog_LDADD = $(LDADD)
+file_locking_SOURCES = file_locking.c
+file_locking_OBJECTS = file_locking.$(OBJEXT)
+file_locking_LDADD = $(LDADD)
+fprw_SOURCES = fprw.c
+fprw_OBJECTS = fprw.$(OBJEXT)
+fprw_LDADD = $(LDADD)
+fwrite_SOURCES = fwrite.c
+fwrite_OBJECTS = fwrite.$(OBJEXT)
+fwrite_LDADD = $(LDADD)
+holey_buffer_too_small_SOURCES = holey_buffer_too_small.c
+holey_buffer_too_small_OBJECTS = holey_buffer_too_small.$(OBJEXT)
+holey_buffer_too_small_LDADD = $(LDADD)
+inits_SOURCES = inits.c
+inits_OBJECTS = inits-inits.$(OBJEXT)
+inits_LDADD = $(LDADD)
+inits_LINK = $(CCLD) $(inits_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+inline_SOURCES = inline.c
+inline_OBJECTS = inline.$(OBJEXT)
+inline_LDADD = $(LDADD)
+leak_0_SOURCES = leak-0.c
+leak_0_OBJECTS = leak-0.$(OBJEXT)
+leak_0_LDADD = $(LDADD)
+leak_cases_SOURCES = leak-cases.c
+leak_cases_OBJECTS = leak-cases.$(OBJEXT)
+leak_cases_LDADD = $(LDADD)
+leak_cycle_SOURCES = leak-cycle.c
+leak_cycle_OBJECTS = leak-cycle.$(OBJEXT)
+leak_cycle_LDADD = $(LDADD)
+leak_delta_SOURCES = leak-delta.c
+leak_delta_OBJECTS = leak-delta.$(OBJEXT)
+leak_delta_LDADD = $(LDADD)
+leak_pool_SOURCES = leak-pool.c
+leak_pool_OBJECTS = leak-pool.$(OBJEXT)
+leak_pool_LDADD = $(LDADD)
+leak_tree_SOURCES = leak-tree.c
+leak_tree_OBJECTS = leak-tree.$(OBJEXT)
+leak_tree_LDADD = $(LDADD)
+long_supps_SOURCES = long-supps.c
+long_supps_OBJECTS = long-supps.$(OBJEXT)
+long_supps_LDADD = $(LDADD)
+am_long_namespace_xml_OBJECTS = long_namespace_xml.$(OBJEXT)
+long_namespace_xml_OBJECTS = $(am_long_namespace_xml_OBJECTS)
+long_namespace_xml_LDADD = $(LDADD)
+mallinfo_SOURCES = mallinfo.c
+mallinfo_OBJECTS = mallinfo.$(OBJEXT)
+mallinfo_LDADD = $(LDADD)
+malloc1_SOURCES = malloc1.c
+malloc1_OBJECTS = malloc1.$(OBJEXT)
+malloc1_LDADD = $(LDADD)
+malloc2_SOURCES = malloc2.c
+malloc2_OBJECTS = malloc2.$(OBJEXT)
+malloc2_LDADD = $(LDADD)
+malloc3_SOURCES = malloc3.c
+malloc3_OBJECTS = malloc3.$(OBJEXT)
+malloc3_LDADD = $(LDADD)
+malloc_free_fill_SOURCES = malloc_free_fill.c
+malloc_free_fill_OBJECTS = malloc_free_fill.$(OBJEXT)
+malloc_free_fill_LDADD = $(LDADD)
+malloc_usable_SOURCES = malloc_usable.c
+malloc_usable_OBJECTS = malloc_usable.$(OBJEXT)
+malloc_usable_LDADD = $(LDADD)
+manuel1_SOURCES = manuel1.c
+manuel1_OBJECTS = manuel1-manuel1.$(OBJEXT)
+manuel1_LDADD = $(LDADD)
+manuel1_LINK = $(CCLD) $(manuel1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+manuel2_SOURCES = manuel2.c
+manuel2_OBJECTS = manuel2.$(OBJEXT)
+manuel2_LDADD = $(LDADD)
+manuel3_SOURCES = manuel3.c
+manuel3_OBJECTS = manuel3.$(OBJEXT)
+manuel3_LDADD = $(LDADD)
+match_overrun_SOURCES = match-overrun.c
+match_overrun_OBJECTS = match-overrun.$(OBJEXT)
+match_overrun_LDADD = $(LDADD)
+memalign2_SOURCES = memalign2.c
+memalign2_OBJECTS = memalign2.$(OBJEXT)
+memalign2_LDADD = $(LDADD)
+memalign_test_SOURCES = memalign_test.c
+memalign_test_OBJECTS = memalign_test.$(OBJEXT)
+memalign_test_LDADD = $(LDADD)
+memcmptest_SOURCES = memcmptest.c
+memcmptest_OBJECTS = memcmptest-memcmptest.$(OBJEXT)
+memcmptest_LDADD = $(LDADD)
+memcmptest_LINK = $(CCLD) $(memcmptest_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+mempool_SOURCES = mempool.c
+mempool_OBJECTS = mempool.$(OBJEXT)
+mempool_LDADD = $(LDADD)
+mempool2_SOURCES = mempool2.c
+mempool2_OBJECTS = mempool2.$(OBJEXT)
+mempool2_LDADD = $(LDADD)
+metadata_SOURCES = metadata.c
+metadata_OBJECTS = metadata.$(OBJEXT)
+metadata_LDADD = $(LDADD)
+am_mismatches_OBJECTS = mismatches.$(OBJEXT)
+mismatches_OBJECTS = $(am_mismatches_OBJECTS)
+mismatches_LDADD = $(LDADD)
+mmaptest_SOURCES = mmaptest.c
+mmaptest_OBJECTS = mmaptest.$(OBJEXT)
+mmaptest_LDADD = $(LDADD)
+nanoleak2_SOURCES = nanoleak2.c
+nanoleak2_OBJECTS = nanoleak2.$(OBJEXT)
+nanoleak2_LDADD = $(LDADD)
+nanoleak_supp_SOURCES = nanoleak_supp.c
+nanoleak_supp_OBJECTS = nanoleak_supp.$(OBJEXT)
+nanoleak_supp_LDADD = $(LDADD)
+am_new_nothrow_OBJECTS = new_nothrow.$(OBJEXT)
+new_nothrow_OBJECTS = $(am_new_nothrow_OBJECTS)
+new_nothrow_LDADD = $(LDADD)
+am_new_override_OBJECTS = new_override.$(OBJEXT)
+new_override_OBJECTS = $(am_new_override_OBJECTS)
+new_override_LDADD = $(LDADD)
+noisy_child_SOURCES = noisy_child.c
+noisy_child_OBJECTS = noisy_child.$(OBJEXT)
+noisy_child_LDADD = $(LDADD)
+null_socket_SOURCES = null_socket.c
+null_socket_OBJECTS = null_socket.$(OBJEXT)
+null_socket_LDADD = $(LDADD)
+origin1_yes_SOURCES = origin1-yes.c
+origin1_yes_OBJECTS = origin1-yes.$(OBJEXT)
+origin1_yes_LDADD = $(LDADD)
+origin2_not_quite_SOURCES = origin2-not-quite.c
+origin2_not_quite_OBJECTS = \
+ origin2_not_quite-origin2-not-quite.$(OBJEXT)
+origin2_not_quite_LDADD = $(LDADD)
+origin2_not_quite_LINK = $(CCLD) $(origin2_not_quite_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+origin3_no_SOURCES = origin3-no.c
+origin3_no_OBJECTS = origin3_no-origin3-no.$(OBJEXT)
+origin3_no_LDADD = $(LDADD)
+origin3_no_LINK = $(CCLD) $(origin3_no_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+origin4_many_SOURCES = origin4-many.c
+origin4_many_OBJECTS = origin4_many-origin4-many.$(OBJEXT)
+origin4_many_LDADD = $(LDADD)
+origin4_many_LINK = $(CCLD) $(origin4_many_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+origin5_bz2_SOURCES = origin5-bz2.c
+origin5_bz2_OBJECTS = origin5_bz2-origin5-bz2.$(OBJEXT)
+origin5_bz2_LDADD = $(LDADD)
+origin5_bz2_LINK = $(CCLD) $(origin5_bz2_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+origin6_fp_SOURCES = origin6-fp.c
+origin6_fp_OBJECTS = origin6_fp-origin6-fp.$(OBJEXT)
+origin6_fp_LDADD = $(LDADD)
+origin6_fp_LINK = $(CCLD) $(origin6_fp_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+overlap_SOURCES = overlap.c
+overlap_OBJECTS = overlap-overlap.$(OBJEXT)
+overlap_LDADD = $(LDADD)
+overlap_LINK = $(CCLD) $(overlap_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+partial_load_SOURCES = partial_load.c
+partial_load_OBJECTS = partial_load.$(OBJEXT)
+partial_load_LDADD = $(LDADD)
+partiallydefinedeq_SOURCES = partiallydefinedeq.c
+partiallydefinedeq_OBJECTS = partiallydefinedeq.$(OBJEXT)
+partiallydefinedeq_LDADD = $(LDADD)
+pdb_realloc_SOURCES = pdb-realloc.c
+pdb_realloc_OBJECTS = pdb-realloc.$(OBJEXT)
+pdb_realloc_LDADD = $(LDADD)
+pdb_realloc2_SOURCES = pdb-realloc2.c
+pdb_realloc2_OBJECTS = pdb-realloc2.$(OBJEXT)
+pdb_realloc2_LDADD = $(LDADD)
+pipe_SOURCES = pipe.c
+pipe_OBJECTS = pipe.$(OBJEXT)
+pipe_LDADD = $(LDADD)
+pointer_trace_SOURCES = pointer-trace.c
+pointer_trace_OBJECTS = pointer-trace.$(OBJEXT)
+pointer_trace_LDADD = $(LDADD)
+post_syscall_SOURCES = post-syscall.c
+post_syscall_OBJECTS = post-syscall.$(OBJEXT)
+post_syscall_LDADD = $(LDADD)
+realloc1_SOURCES = realloc1.c
+realloc1_OBJECTS = realloc1.$(OBJEXT)
+realloc1_LDADD = $(LDADD)
+realloc2_SOURCES = realloc2.c
+realloc2_OBJECTS = realloc2.$(OBJEXT)
+realloc2_LDADD = $(LDADD)
+realloc3_SOURCES = realloc3.c
+realloc3_OBJECTS = realloc3.$(OBJEXT)
+realloc3_LDADD = $(LDADD)
+sbfragment_SOURCES = sbfragment.c
+sbfragment_OBJECTS = sbfragment.$(OBJEXT)
+sbfragment_LDADD = $(LDADD)
+sh_mem_SOURCES = sh-mem.c
+sh_mem_OBJECTS = sh-mem.$(OBJEXT)
+sh_mem_LDADD = $(LDADD)
+sh_mem_random_SOURCES = sh-mem-random.c
+sh_mem_random_OBJECTS = sh-mem-random.$(OBJEXT)
+sh_mem_random_LDADD = $(LDADD)
+sigaltstack_SOURCES = sigaltstack.c
+sigaltstack_OBJECTS = sigaltstack.$(OBJEXT)
+sigaltstack_LDADD = $(LDADD)
+sigkill_SOURCES = sigkill.c
+sigkill_OBJECTS = sigkill.$(OBJEXT)
+sigkill_LDADD = $(LDADD)
+signal2_SOURCES = signal2.c
+signal2_OBJECTS = signal2.$(OBJEXT)
+signal2_LDADD = $(LDADD)
+sigprocmask_SOURCES = sigprocmask.c
+sigprocmask_OBJECTS = sigprocmask.$(OBJEXT)
+sigprocmask_LDADD = $(LDADD)
+static_malloc_SOURCES = static_malloc.c
+static_malloc_OBJECTS = static_malloc.$(OBJEXT)
+static_malloc_LDADD = $(LDADD)
+str_tester_SOURCES = str_tester.c
+str_tester_OBJECTS = str_tester-str_tester.$(OBJEXT)
+str_tester_LDADD = $(LDADD)
+str_tester_LINK = $(CCLD) $(str_tester_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+strchr_SOURCES = strchr.c
+strchr_OBJECTS = strchr.$(OBJEXT)
+strchr_LDADD = $(LDADD)
+am_supp1_OBJECTS = supp.$(OBJEXT)
+supp1_OBJECTS = $(am_supp1_OBJECTS)
+supp1_LDADD = $(LDADD)
+am_supp2_OBJECTS = supp.$(OBJEXT)
+supp2_OBJECTS = $(am_supp2_OBJECTS)
+supp2_LDADD = $(LDADD)
+am_supp_unknown_OBJECTS = badjump.$(OBJEXT)
+supp_unknown_OBJECTS = $(am_supp_unknown_OBJECTS)
+supp_unknown_LDADD = $(LDADD)
+suppfree_SOURCES = suppfree.c
+suppfree_OBJECTS = suppfree.$(OBJEXT)
+suppfree_LDADD = $(LDADD)
+test_plo_SOURCES = test-plo.c
+test_plo_OBJECTS = test-plo.$(OBJEXT)
+test_plo_LDADD = $(LDADD)
+trivialleak_SOURCES = trivialleak.c
+trivialleak_OBJECTS = trivialleak.$(OBJEXT)
+trivialleak_LDADD = $(LDADD)
+unit_libcbase_SOURCES = unit_libcbase.c
+unit_libcbase_OBJECTS = unit_libcbase.$(OBJEXT)
+unit_libcbase_LDADD = $(LDADD)
+unit_oset_SOURCES = unit_oset.c
+unit_oset_OBJECTS = unit_oset.$(OBJEXT)
+unit_oset_LDADD = $(LDADD)
+varinfo1_SOURCES = varinfo1.c
+varinfo1_OBJECTS = varinfo1-varinfo1.$(OBJEXT)
+varinfo1_LDADD = $(LDADD)
+varinfo1_LINK = $(CCLD) $(varinfo1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+varinfo2_SOURCES = varinfo2.c
+varinfo2_OBJECTS = varinfo2-varinfo2.$(OBJEXT)
+varinfo2_LDADD = $(LDADD)
+varinfo2_LINK = $(CCLD) $(varinfo2_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+varinfo3_SOURCES = varinfo3.c
+varinfo3_OBJECTS = varinfo3-varinfo3.$(OBJEXT)
+varinfo3_LDADD = $(LDADD)
+varinfo3_LINK = $(CCLD) $(varinfo3_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+varinfo4_SOURCES = varinfo4.c
+varinfo4_OBJECTS = varinfo4-varinfo4.$(OBJEXT)
+varinfo4_LDADD = $(LDADD)
+varinfo4_LINK = $(CCLD) $(varinfo4_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am_varinfo5_OBJECTS = varinfo5-varinfo5.$(OBJEXT)
+varinfo5_OBJECTS = $(am_varinfo5_OBJECTS)
+varinfo5_LINK = $(CCLD) $(varinfo5_CFLAGS) $(CFLAGS) \
+ $(varinfo5_LDFLAGS) $(LDFLAGS) -o $@
+am_varinfo5so_so_OBJECTS = varinfo5so_so-varinfo5so.$(OBJEXT)
+varinfo5so_so_OBJECTS = $(am_varinfo5so_so_OBJECTS)
+varinfo5so_so_LDADD = $(LDADD)
+varinfo5so_so_LINK = $(CCLD) $(varinfo5so_so_CFLAGS) $(CFLAGS) \
+ $(varinfo5so_so_LDFLAGS) $(LDFLAGS) -o $@
+varinfo6_SOURCES = varinfo6.c
+varinfo6_OBJECTS = varinfo6-varinfo6.$(OBJEXT)
+varinfo6_LDADD = $(LDADD)
+varinfo6_LINK = $(CCLD) $(varinfo6_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+vcpu_fbench_SOURCES = vcpu_fbench.c
+vcpu_fbench_OBJECTS = vcpu_fbench-vcpu_fbench.$(OBJEXT)
+vcpu_fbench_LDADD = $(LDADD)
+vcpu_fbench_LINK = $(CCLD) $(vcpu_fbench_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+vcpu_fnfns_SOURCES = vcpu_fnfns.c
+vcpu_fnfns_OBJECTS = vcpu_fnfns-vcpu_fnfns.$(OBJEXT)
+vcpu_fnfns_DEPENDENCIES =
+vcpu_fnfns_LINK = $(CCLD) $(vcpu_fnfns_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+wrap1_SOURCES = wrap1.c
+wrap1_OBJECTS = wrap1.$(OBJEXT)
+wrap1_LDADD = $(LDADD)
+wrap2_SOURCES = wrap2.c
+wrap2_OBJECTS = wrap2.$(OBJEXT)
+wrap2_LDADD = $(LDADD)
+wrap3_SOURCES = wrap3.c
+wrap3_OBJECTS = wrap3.$(OBJEXT)
+wrap3_LDADD = $(LDADD)
+wrap4_SOURCES = wrap4.c
+wrap4_OBJECTS = wrap4.$(OBJEXT)
+wrap4_LDADD = $(LDADD)
+wrap5_SOURCES = wrap5.c
+wrap5_OBJECTS = wrap5.$(OBJEXT)
+wrap5_LDADD = $(LDADD)
+wrap6_SOURCES = wrap6.c
+wrap6_OBJECTS = wrap6-wrap6.$(OBJEXT)
+wrap6_LDADD = $(LDADD)
+wrap6_LINK = $(CCLD) $(wrap6_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am_wrap7_OBJECTS = wrap7.$(OBJEXT)
+wrap7_OBJECTS = $(am_wrap7_OBJECTS)
+wrap7_LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(wrap7_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am_wrap7so_so_OBJECTS = wrap7so_so-wrap7so.$(OBJEXT)
+wrap7so_so_OBJECTS = $(am_wrap7so_so_OBJECTS)
+wrap7so_so_LDADD = $(LDADD)
+wrap7so_so_LINK = $(CCLD) $(wrap7so_so_CFLAGS) $(CFLAGS) \
+ $(wrap7so_so_LDFLAGS) $(LDFLAGS) -o $@
+wrap8_SOURCES = wrap8.c
+wrap8_OBJECTS = wrap8.$(OBJEXT)
+wrap8_LDADD = $(LDADD)
+writev1_SOURCES = writev1.c
+writev1_OBJECTS = writev1.$(OBJEXT)
+writev1_LDADD = $(LDADD)
+xml1_SOURCES = xml1.c
+xml1_OBJECTS = xml1.$(OBJEXT)
+xml1_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+CXXCOMPILE = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS)
+CXXLD = $(CXX)
+CXXLINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+SOURCES = accounting.c addressable.c atomic_incs.c badaddrvalue.c \
+ badfree.c badjump.c badjump2.c badloop.c badpoll.c badrw.c \
+ big_blocks_freed_list.c brk2.c buflen_check.c bug287260.c \
+ calloc-overflow.c clientperm.c clireq_nofill.c clo_redzone.c \
+ custom-overlap.c custom_alloc.c deep-backtrace.c \
+ $(deep_templates_SOURCES) describe-block.c doublefree.c dw4.c \
+ err_disable1.c err_disable2.c err_disable3.c err_disable4.c \
+ erringfds.c error_counts.c errs1.c execve1.c execve2.c \
+ exitprog.c file_locking.c fprw.c fwrite.c \
+ holey_buffer_too_small.c inits.c inline.c leak-0.c \
+ leak-cases.c leak-cycle.c leak-delta.c leak-pool.c leak-tree.c \
+ long-supps.c $(long_namespace_xml_SOURCES) mallinfo.c \
+ malloc1.c malloc2.c malloc3.c malloc_free_fill.c \
+ malloc_usable.c manuel1.c manuel2.c manuel3.c match-overrun.c \
+ memalign2.c memalign_test.c memcmptest.c mempool.c mempool2.c \
+ metadata.c $(mismatches_SOURCES) mmaptest.c nanoleak2.c \
+ nanoleak_supp.c $(new_nothrow_SOURCES) $(new_override_SOURCES) \
+ noisy_child.c null_socket.c origin1-yes.c origin2-not-quite.c \
+ origin3-no.c origin4-many.c origin5-bz2.c origin6-fp.c \
+ overlap.c partial_load.c partiallydefinedeq.c pdb-realloc.c \
+ pdb-realloc2.c pipe.c pointer-trace.c post-syscall.c \
+ realloc1.c realloc2.c realloc3.c sbfragment.c sh-mem.c \
+ sh-mem-random.c sigaltstack.c sigkill.c signal2.c \
+ sigprocmask.c static_malloc.c str_tester.c strchr.c \
+ $(supp1_SOURCES) $(supp2_SOURCES) $(supp_unknown_SOURCES) \
+ suppfree.c test-plo.c trivialleak.c unit_libcbase.c \
+ unit_oset.c varinfo1.c varinfo2.c varinfo3.c varinfo4.c \
+ $(varinfo5_SOURCES) $(varinfo5so_so_SOURCES) varinfo6.c \
+ vcpu_fbench.c vcpu_fnfns.c wrap1.c wrap2.c wrap3.c wrap4.c \
+ wrap5.c wrap6.c $(wrap7_SOURCES) $(wrap7so_so_SOURCES) wrap8.c \
+ writev1.c xml1.c
+DIST_SOURCES = accounting.c addressable.c atomic_incs.c badaddrvalue.c \
+ badfree.c badjump.c badjump2.c badloop.c badpoll.c badrw.c \
+ big_blocks_freed_list.c brk2.c buflen_check.c bug287260.c \
+ calloc-overflow.c clientperm.c clireq_nofill.c clo_redzone.c \
+ custom-overlap.c custom_alloc.c deep-backtrace.c \
+ $(deep_templates_SOURCES) describe-block.c doublefree.c dw4.c \
+ err_disable1.c err_disable2.c err_disable3.c err_disable4.c \
+ erringfds.c error_counts.c errs1.c execve1.c execve2.c \
+ exitprog.c file_locking.c fprw.c fwrite.c \
+ holey_buffer_too_small.c inits.c inline.c leak-0.c \
+ leak-cases.c leak-cycle.c leak-delta.c leak-pool.c leak-tree.c \
+ long-supps.c $(long_namespace_xml_SOURCES) mallinfo.c \
+ malloc1.c malloc2.c malloc3.c malloc_free_fill.c \
+ malloc_usable.c manuel1.c manuel2.c manuel3.c match-overrun.c \
+ memalign2.c memalign_test.c memcmptest.c mempool.c mempool2.c \
+ metadata.c $(mismatches_SOURCES) mmaptest.c nanoleak2.c \
+ nanoleak_supp.c $(new_nothrow_SOURCES) $(new_override_SOURCES) \
+ noisy_child.c null_socket.c origin1-yes.c origin2-not-quite.c \
+ origin3-no.c origin4-many.c origin5-bz2.c origin6-fp.c \
+ overlap.c partial_load.c partiallydefinedeq.c pdb-realloc.c \
+ pdb-realloc2.c pipe.c pointer-trace.c post-syscall.c \
+ realloc1.c realloc2.c realloc3.c sbfragment.c sh-mem.c \
+ sh-mem-random.c sigaltstack.c sigkill.c signal2.c \
+ sigprocmask.c static_malloc.c str_tester.c strchr.c \
+ $(supp1_SOURCES) $(supp2_SOURCES) $(supp_unknown_SOURCES) \
+ suppfree.c test-plo.c trivialleak.c unit_libcbase.c \
+ unit_oset.c varinfo1.c varinfo2.c varinfo3.c varinfo4.c \
+ $(varinfo5_SOURCES) $(varinfo5so_so_SOURCES) varinfo6.c \
+ vcpu_fbench.c vcpu_fnfns.c wrap1.c wrap2.c wrap3.c wrap4.c \
+ wrap5.c wrap6.c $(wrap7_SOURCES) $(wrap7so_so_SOURCES) wrap8.c \
+ writev1.c xml1.c
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+HEADERS = $(noinst_HEADERS)
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+SUBDIRS = . $(am__append_3) $(am__append_4) $(am__append_5) \
+ $(am__append_6) $(am__append_7) $(am__append_8) \
+ $(am__append_9) $(am__append_10) $(am__append_11)
+DIST_SUBDIRS = x86 amd64 ppc32 ppc64 s390x linux darwin x86-linux amd64-linux .
+dist_noinst_SCRIPTS = \
+ filter_addressable \
+ filter_allocs \
+ filter_leak_cases_possible \
+ filter_stderr filter_xml \
+ filter_varinfo3 \
+ filter_memcheck
+
+noinst_HEADERS = leak.h
+EXTRA_DIST = \
+ accounting.stderr.exp accounting.vgtest \
+ addressable.stderr.exp addressable.stdout.exp addressable.vgtest \
+ atomic_incs.stderr.exp atomic_incs.vgtest \
+ atomic_incs.stdout.exp-32bit atomic_incs.stdout.exp-64bit \
+ badaddrvalue.stderr.exp \
+ badaddrvalue.stdout.exp badaddrvalue.vgtest \
+ badfree-2trace.stderr.exp badfree-2trace.vgtest \
+ badfree.stderr.exp badfree.vgtest \
+ badfree3.stderr.exp badfree3.vgtest \
+ badjump.stderr.exp badjump.vgtest \
+ badjump2.stderr.exp badjump2.vgtest \
+ badjump.stderr.exp-kfail \
+ badjump2.stderr.exp-kfail \
+ badloop.stderr.exp badloop.vgtest \
+ badpoll.stderr.exp badpoll.vgtest \
+ badrw.stderr.exp badrw.vgtest badrw.stderr.exp-s390x-mvc \
+ big_blocks_freed_list.stderr.exp big_blocks_freed_list.vgtest \
+ brk2.stderr.exp brk2.vgtest \
+ buflen_check.stderr.exp buflen_check.vgtest buflen_check.stderr.exp-kfail \
+ bug287260.stderr.exp bug287260.vgtest \
+ calloc-overflow.stderr.exp calloc-overflow.vgtest\
+ clientperm.stderr.exp \
+ clientperm.stdout.exp clientperm.vgtest \
+ clireq_nofill.stderr.exp \
+ clireq_nofill.stdout.exp clireq_nofill.vgtest \
+ clo_redzone_default.vgtest clo_redzone_128.vgtest \
+ clo_redzone_default.stderr.exp clo_redzone_128.stderr.exp \
+ custom_alloc.stderr.exp custom_alloc.vgtest custom_alloc.stderr.exp-s390x-mvc \
+ custom-overlap.stderr.exp custom-overlap.vgtest \
+ deep-backtrace.vgtest deep-backtrace.stderr.exp \
+ deep_templates.vgtest \
+ deep_templates.stdout.exp deep_templates.stderr.exp \
+ describe-block.stderr.exp describe-block.vgtest \
+ doublefree.stderr.exp doublefree.vgtest \
+ dw4.vgtest dw4.stderr.exp dw4.stdout.exp \
+ err_disable1.vgtest err_disable1.stderr.exp \
+ err_disable2.vgtest err_disable2.stderr.exp \
+ err_disable3.vgtest err_disable3.stderr.exp \
+ err_disable4.vgtest err_disable4.stderr.exp \
+ erringfds.stderr.exp erringfds.stdout.exp erringfds.vgtest \
+ error_counts.stderr.exp error_counts.vgtest \
+ errs1.stderr.exp errs1.vgtest \
+ exitprog.stderr.exp exitprog.vgtest \
+ execve1.stderr.exp execve1.vgtest execve1.stderr.exp-kfail \
+ execve2.stderr.exp execve2.vgtest execve2.stderr.exp-kfail \
+ file_locking.stderr.exp file_locking.vgtest \
+ fprw.stderr.exp fprw.vgtest \
+ fwrite.stderr.exp fwrite.vgtest fwrite.stderr.exp-kfail \
+ holey_buffer_too_small.vgtest holey_buffer_too_small.stdout.exp \
+ holey_buffer_too_small.stderr.exp \
+ inits.stderr.exp inits.vgtest \
+ inline.stderr.exp inline.stdout.exp inline.vgtest \
+ leak-0.vgtest leak-0.stderr.exp \
+ leak-cases-full.vgtest leak-cases-full.stderr.exp \
+ leak-cases-possible.vgtest leak-cases-possible.stderr.exp \
+ leak-cases-summary.vgtest leak-cases-summary.stderr.exp \
+ leak-cycle.vgtest leak-cycle.stderr.exp \
+ leak-delta.vgtest leak-delta.stderr.exp \
+ leak-pool-0.vgtest leak-pool-0.stderr.exp \
+ leak-pool-1.vgtest leak-pool-1.stderr.exp \
+ leak-pool-2.vgtest leak-pool-2.stderr.exp \
+ leak-pool-3.vgtest leak-pool-3.stderr.exp \
+ leak-pool-4.vgtest leak-pool-4.stderr.exp \
+ leak-pool-5.vgtest leak-pool-5.stderr.exp \
+ leak-tree.vgtest leak-tree.stderr.exp \
+ long_namespace_xml.vgtest long_namespace_xml.stdout.exp \
+ long_namespace_xml.stderr.exp \
+ long-supps.vgtest long-supps.stderr.exp long-supps.supp \
+ mallinfo.stderr.exp mallinfo.vgtest \
+ malloc_free_fill.vgtest \
+ malloc_free_fill.stderr.exp \
+ malloc_usable.stderr.exp malloc_usable.vgtest \
+ malloc1.stderr.exp malloc1.vgtest \
+ malloc2.stderr.exp malloc2.vgtest \
+ malloc3.stderr.exp malloc3.stdout.exp malloc3.vgtest \
+ manuel1.stderr.exp manuel1.stdout.exp manuel1.vgtest \
+ manuel2.stderr.exp manuel2.stderr.exp64 manuel2.stdout.exp manuel2.vgtest \
+ manuel3.stderr.exp manuel3.vgtest \
+ match-overrun.stderr.exp match-overrun.vgtest match-overrun.supp \
+ memalign_test.stderr.exp memalign_test.vgtest \
+ memalign2.stderr.exp memalign2.vgtest \
+ memcmptest.stderr.exp memcmptest.stderr.exp2 \
+ memcmptest.stdout.exp memcmptest.vgtest \
+ mempool.stderr.exp mempool.vgtest \
+ mempool2.stderr.exp mempool2.vgtest \
+ metadata.stderr.exp metadata.stdout.exp metadata.vgtest \
+ mismatches.stderr.exp mismatches.vgtest \
+ mmaptest.stderr.exp mmaptest.vgtest \
+ nanoleak_supp.stderr.exp nanoleak_supp.vgtest nanoleak.supp \
+ nanoleak2.stderr.exp nanoleak2.vgtest \
+ new_nothrow.stderr.exp new_nothrow.vgtest \
+ new_override.stderr.exp new_override.stdout.exp new_override.vgtest \
+ noisy_child.vgtest noisy_child.stderr.exp noisy_child.stdout.exp \
+ null_socket.stderr.exp null_socket.vgtest \
+ origin1-yes.vgtest origin1-yes.stdout.exp origin1-yes.stderr.exp \
+ origin2-not-quite.vgtest origin2-not-quite.stdout.exp \
+ origin2-not-quite.stderr.exp \
+ origin3-no.vgtest origin3-no.stdout.exp \
+ origin3-no.stderr.exp \
+ origin4-many.vgtest origin4-many.stdout.exp \
+ origin4-many.stderr.exp \
+ origin5-bz2.vgtest origin5-bz2.stdout.exp \
+ origin5-bz2.stderr.exp-glibc25-x86 \
+ origin5-bz2.stderr.exp-glibc25-amd64 \
+ origin5-bz2.stderr.exp-glibc27-ppc64 \
+ origin5-bz2.stderr.exp-glibc212-s390x \
+ origin5-bz2.stderr.exp-glibc234-s390x \
+ origin6-fp.vgtest origin6-fp.stdout.exp \
+ origin6-fp.stderr.exp-glibc25-amd64 \
+ origin6-fp.stderr.exp-glibc27-ppc64 \
+ overlap.stderr.exp overlap.stdout.exp overlap.vgtest \
+ partiallydefinedeq.vgtest partiallydefinedeq.stderr.exp \
+ partiallydefinedeq.stderr.exp4 \
+ partiallydefinedeq.stderr.exp3 \
+ partiallydefinedeq.stderr.exp2 \
+ partiallydefinedeq.stdout.exp \
+ partial_load_ok.vgtest partial_load_ok.stderr.exp partial_load_ok.stderr.exp64 \
+ partial_load_dflt.vgtest partial_load_dflt.stderr.exp partial_load_dflt.stderr.exp64 \
+ partial_load_dflt.stderr.expr-s390x-mvc \
+ pdb-realloc.stderr.exp pdb-realloc.vgtest \
+ pdb-realloc2.stderr.exp pdb-realloc2.stdout.exp pdb-realloc2.vgtest \
+ pipe.stderr.exp pipe.vgtest \
+ pointer-trace.vgtest \
+ pointer-trace.stderr.exp \
+ post-syscall.stderr.exp post-syscall.vgtest \
+ realloc1.stderr.exp realloc1.vgtest \
+ realloc2.stderr.exp realloc2.vgtest \
+ realloc3.stderr.exp realloc3.vgtest \
+ sbfragment.stdout.exp sbfragment.stderr.exp sbfragment.vgtest \
+ sh-mem.stderr.exp sh-mem.vgtest \
+ sh-mem-random.stderr.exp sh-mem-random.stdout.exp64 \
+ sh-mem-random.stdout.exp sh-mem-random.vgtest \
+ sigaltstack.stderr.exp sigaltstack.vgtest \
+ sigkill.stderr.exp sigkill.stderr.exp-darwin sigkill.stderr.exp-mips32 \
+ sigkill.vgtest \
+ signal2.stderr.exp signal2.stdout.exp signal2.vgtest \
+ sigprocmask.stderr.exp sigprocmask.stderr.exp2 sigprocmask.vgtest \
+ static_malloc.stderr.exp static_malloc.vgtest \
+ strchr.stderr.exp strchr.stderr.exp2 strchr.stderr.exp-darwin \
+ strchr.stderr.exp3 strchr.vgtest \
+ str_tester.stderr.exp str_tester.vgtest \
+ supp-dir.vgtest supp-dir.stderr.exp \
+ supp_unknown.stderr.exp supp_unknown.vgtest supp_unknown.supp \
+ supp_unknown.stderr.exp-kfail \
+ supp1.stderr.exp supp1.vgtest \
+ supp2.stderr.exp supp2.vgtest \
+ supp.supp \
+ suppfree.stderr.exp suppfree.supp suppfree.vgtest \
+ test-plo-no.vgtest test-plo-no.stdout.exp \
+ test-plo-no.stderr.exp-le64 test-plo-no.stderr.exp-le32 \
+ test-plo-yes.vgtest test-plo-yes.stdout.exp \
+ test-plo-yes.stderr.exp-le64 test-plo-yes.stderr.exp-le32 \
+ test-plo-no.stderr.exp-s390x-mvc \
+ trivialleak.stderr.exp trivialleak.vgtest trivialleak.stderr.exp2 \
+ unit_libcbase.stderr.exp unit_libcbase.vgtest \
+ unit_oset.stderr.exp unit_oset.stdout.exp unit_oset.vgtest \
+ varinfo1.vgtest varinfo1.stdout.exp varinfo1.stderr.exp varinfo1.stderr.exp-ppc64 \
+ varinfo2.vgtest varinfo2.stdout.exp varinfo2.stderr.exp varinfo2.stderr.exp-ppc64 \
+ varinfo3.vgtest varinfo3.stdout.exp varinfo3.stderr.exp varinfo3.stderr.exp-ppc64 \
+ varinfo4.vgtest varinfo4.stdout.exp varinfo4.stderr.exp varinfo4.stderr.exp-ppc64 \
+ varinfo5.vgtest varinfo5.stdout.exp varinfo5.stderr.exp varinfo5.stderr.exp-ppc64 \
+ varinfo6.vgtest varinfo6.stdout.exp varinfo6.stderr.exp varinfo6.stderr.exp-ppc64 \
+ vcpu_bz2.stdout.exp vcpu_bz2.stderr.exp vcpu_bz2.vgtest \
+ vcpu_fbench.stdout.exp vcpu_fbench.stderr.exp vcpu_fbench.vgtest \
+ vcpu_fnfns.stdout.exp vcpu_fnfns.stdout.exp-glibc28-amd64 \
+ vcpu_fnfns.stdout.exp-darwin vcpu_fnfns.stderr.exp vcpu_fnfns.vgtest \
+ wrap1.vgtest wrap1.stdout.exp wrap1.stderr.exp \
+ wrap2.vgtest wrap2.stdout.exp wrap2.stderr.exp \
+ wrap3.vgtest wrap3.stdout.exp wrap3.stderr.exp \
+ wrap4.vgtest wrap4.stdout.exp wrap4.stderr.exp \
+ wrap5.vgtest wrap5.stdout.exp wrap5.stderr.exp \
+ wrap6.vgtest wrap6.stdout.exp wrap6.stderr.exp \
+ wrap7.vgtest wrap7.stdout.exp wrap7.stderr.exp \
+ wrap8.vgtest wrap8.stdout.exp wrap8.stderr.exp \
+ wrap8.stdout.exp2 wrap8.stderr.exp2 \
+ writev1.stderr.exp writev1.vgtest \
+ xml1.stderr.exp xml1.stdout.exp xml1.vgtest xml1.stderr.exp-s390x-mvc
+
+@VGCONF_OS_IS_DARWIN_FALSE@atomic_incs_CFLAGS = $(AM_CFLAGS)
+
+#AM_CFLAGS += -mfloat-abi=softfp
+#AM_CXXFLAGS += -mfloat-abi=softfp
+@VGCONF_OS_IS_DARWIN_TRUE@atomic_incs_CFLAGS = $(AM_CFLAGS) -mdynamic-no-pic
+deep_templates_SOURCES = deep_templates.cpp
+deep_templates_CXXFLAGS = $(AM_CFLAGS) -O -gstabs
+dw4_CFLAGS = $(AM_CFLAGS) -gdwarf-4 -fdebug-types-section
+err_disable3_LDADD = -lpthread
+err_disable4_LDADD = -lpthread
+error_counts_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@
+execve1_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+execve2_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+inits_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@
+long_namespace_xml_SOURCES = long_namespace_xml.cpp
+manuel1_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@
+memcmptest_CFLAGS = $(AM_CFLAGS) -fno-builtin-memcmp
+mismatches_SOURCES = mismatches.cpp
+new_nothrow_SOURCES = new_nothrow.cpp
+new_override_SOURCES = new_override.cpp
+origin2_not_quite_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@
+origin3_no_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@
+
+# This requires optimisation in order to get just one resulting error.
+origin4_many_CFLAGS = $(AM_CFLAGS) -O
+
+# Apply -O so as to run in reasonable time.
+origin5_bz2_CFLAGS = $(AM_CFLAGS) -O -Wno-inline
+origin6_fp_CFLAGS = $(AM_CFLAGS) -O
+
+# Don't allow GCC to inline memcpy() and strcpy(),
+# because then we can't intercept it
+overlap_CFLAGS = $(AM_CFLAGS) -fno-builtin-memcpy -fno-builtin-strcpy
+str_tester_CFLAGS = $(AM_CFLAGS) -Wno-shadow
+supp_unknown_SOURCES = badjump.c
+supp1_SOURCES = supp.c
+supp2_SOURCES = supp.c
+vcpu_bz2_CFLAGS = $(AM_CFLAGS) -O2
+vcpu_fbench_CFLAGS = $(AM_CFLAGS) -O2
+vcpu_fnfns_CFLAGS = $(AM_CFLAGS) -O2
+vcpu_fnfns_LDADD = -lm
+wrap6_CFLAGS = $(AM_CFLAGS) -O2
+
+# To make it a bit more realistic, have some optimisation enabled
+# for the varinfo tests. We still expect sane results.
+varinfo1_CFLAGS = $(AM_CFLAGS) -O
+varinfo2_CFLAGS = $(AM_CFLAGS) -O -Wno-shadow
+varinfo3_CFLAGS = $(AM_CFLAGS) -O
+varinfo4_CFLAGS = $(AM_CFLAGS) -O
+varinfo5_CFLAGS = $(AM_CFLAGS) -O
+varinfo6_CFLAGS = $(AM_CFLAGS) -O
+
+# Build shared object for varinfo5
+varinfo5_SOURCES = varinfo5.c
+varinfo5_DEPENDENCIES = varinfo5so.so
+@VGCONF_OS_IS_DARWIN_FALSE@varinfo5_LDADD = varinfo5so.so
+@VGCONF_OS_IS_DARWIN_TRUE@varinfo5_LDADD = `pwd`/varinfo5so.so
+@VGCONF_OS_IS_DARWIN_FALSE@varinfo5_LDFLAGS = $(AM_FLAG_M3264_PRI) \
+@VGCONF_OS_IS_DARWIN_FALSE@ -Wl,-rpath,$(top_builddir)/memcheck/tests
+
+@VGCONF_OS_IS_DARWIN_TRUE@varinfo5_LDFLAGS = $(AM_FLAG_M3264_PRI)
+varinfo5so_so_SOURCES = varinfo5so.c
+varinfo5so_so_CFLAGS = $(AM_CFLAGS) -fpic -O -Wno-shadow
+@VGCONF_OS_IS_DARWIN_FALSE@varinfo5so_so_LDFLAGS = -fpic $(AM_FLAG_M3264_PRI) -shared \
+@VGCONF_OS_IS_DARWIN_FALSE@ -Wl,-soname -Wl,varinfo5so.so
+
+@VGCONF_OS_IS_DARWIN_TRUE@varinfo5so_so_LDFLAGS = -fpic $(AM_FLAG_M3264_PRI) -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -dynamiclib -all_load
+
+
+# Build shared object for wrap7
+wrap7_SOURCES = wrap7.c
+wrap7_DEPENDENCIES = wrap7so.so
+@VGCONF_OS_IS_DARWIN_FALSE@wrap7_LDADD = wrap7so.so
+@VGCONF_OS_IS_DARWIN_TRUE@wrap7_LDADD = `pwd`/wrap7so.so
+@VGCONF_OS_IS_DARWIN_FALSE@wrap7_LDFLAGS = $(AM_FLAG_M3264_PRI) \
+@VGCONF_OS_IS_DARWIN_FALSE@ -Wl,-rpath,$(top_builddir)/memcheck/tests
+
+@VGCONF_OS_IS_DARWIN_TRUE@wrap7_LDFLAGS = $(AM_FLAG_M3264_PRI)
+wrap7so_so_SOURCES = wrap7so.c
+wrap7so_so_CFLAGS = $(AM_CFLAGS) -fpic
+@VGCONF_OS_IS_DARWIN_FALSE@wrap7so_so_LDFLAGS = -fpic $(AM_FLAG_M3264_PRI) -shared \
+@VGCONF_OS_IS_DARWIN_FALSE@ -Wl,-soname -Wl,wrap7so.so
+
+@VGCONF_OS_IS_DARWIN_TRUE@wrap7so_so_LDFLAGS = -fpic $(AM_FLAG_M3264_PRI) -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -dynamiclib -all_load
+
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .cpp .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+accounting$(EXEEXT): $(accounting_OBJECTS) $(accounting_DEPENDENCIES)
+ @rm -f accounting$(EXEEXT)
+ $(LINK) $(accounting_OBJECTS) $(accounting_LDADD) $(LIBS)
+addressable$(EXEEXT): $(addressable_OBJECTS) $(addressable_DEPENDENCIES)
+ @rm -f addressable$(EXEEXT)
+ $(LINK) $(addressable_OBJECTS) $(addressable_LDADD) $(LIBS)
+atomic_incs$(EXEEXT): $(atomic_incs_OBJECTS) $(atomic_incs_DEPENDENCIES)
+ @rm -f atomic_incs$(EXEEXT)
+ $(atomic_incs_LINK) $(atomic_incs_OBJECTS) $(atomic_incs_LDADD) $(LIBS)
+badaddrvalue$(EXEEXT): $(badaddrvalue_OBJECTS) $(badaddrvalue_DEPENDENCIES)
+ @rm -f badaddrvalue$(EXEEXT)
+ $(LINK) $(badaddrvalue_OBJECTS) $(badaddrvalue_LDADD) $(LIBS)
+badfree$(EXEEXT): $(badfree_OBJECTS) $(badfree_DEPENDENCIES)
+ @rm -f badfree$(EXEEXT)
+ $(LINK) $(badfree_OBJECTS) $(badfree_LDADD) $(LIBS)
+badjump$(EXEEXT): $(badjump_OBJECTS) $(badjump_DEPENDENCIES)
+ @rm -f badjump$(EXEEXT)
+ $(LINK) $(badjump_OBJECTS) $(badjump_LDADD) $(LIBS)
+badjump2$(EXEEXT): $(badjump2_OBJECTS) $(badjump2_DEPENDENCIES)
+ @rm -f badjump2$(EXEEXT)
+ $(LINK) $(badjump2_OBJECTS) $(badjump2_LDADD) $(LIBS)
+badloop$(EXEEXT): $(badloop_OBJECTS) $(badloop_DEPENDENCIES)
+ @rm -f badloop$(EXEEXT)
+ $(LINK) $(badloop_OBJECTS) $(badloop_LDADD) $(LIBS)
+badpoll$(EXEEXT): $(badpoll_OBJECTS) $(badpoll_DEPENDENCIES)
+ @rm -f badpoll$(EXEEXT)
+ $(LINK) $(badpoll_OBJECTS) $(badpoll_LDADD) $(LIBS)
+badrw$(EXEEXT): $(badrw_OBJECTS) $(badrw_DEPENDENCIES)
+ @rm -f badrw$(EXEEXT)
+ $(LINK) $(badrw_OBJECTS) $(badrw_LDADD) $(LIBS)
+big_blocks_freed_list$(EXEEXT): $(big_blocks_freed_list_OBJECTS) $(big_blocks_freed_list_DEPENDENCIES)
+ @rm -f big_blocks_freed_list$(EXEEXT)
+ $(LINK) $(big_blocks_freed_list_OBJECTS) $(big_blocks_freed_list_LDADD) $(LIBS)
+brk2$(EXEEXT): $(brk2_OBJECTS) $(brk2_DEPENDENCIES)
+ @rm -f brk2$(EXEEXT)
+ $(LINK) $(brk2_OBJECTS) $(brk2_LDADD) $(LIBS)
+buflen_check$(EXEEXT): $(buflen_check_OBJECTS) $(buflen_check_DEPENDENCIES)
+ @rm -f buflen_check$(EXEEXT)
+ $(LINK) $(buflen_check_OBJECTS) $(buflen_check_LDADD) $(LIBS)
+bug287260$(EXEEXT): $(bug287260_OBJECTS) $(bug287260_DEPENDENCIES)
+ @rm -f bug287260$(EXEEXT)
+ $(LINK) $(bug287260_OBJECTS) $(bug287260_LDADD) $(LIBS)
+calloc-overflow$(EXEEXT): $(calloc_overflow_OBJECTS) $(calloc_overflow_DEPENDENCIES)
+ @rm -f calloc-overflow$(EXEEXT)
+ $(LINK) $(calloc_overflow_OBJECTS) $(calloc_overflow_LDADD) $(LIBS)
+clientperm$(EXEEXT): $(clientperm_OBJECTS) $(clientperm_DEPENDENCIES)
+ @rm -f clientperm$(EXEEXT)
+ $(LINK) $(clientperm_OBJECTS) $(clientperm_LDADD) $(LIBS)
+clireq_nofill$(EXEEXT): $(clireq_nofill_OBJECTS) $(clireq_nofill_DEPENDENCIES)
+ @rm -f clireq_nofill$(EXEEXT)
+ $(LINK) $(clireq_nofill_OBJECTS) $(clireq_nofill_LDADD) $(LIBS)
+clo_redzone$(EXEEXT): $(clo_redzone_OBJECTS) $(clo_redzone_DEPENDENCIES)
+ @rm -f clo_redzone$(EXEEXT)
+ $(LINK) $(clo_redzone_OBJECTS) $(clo_redzone_LDADD) $(LIBS)
+custom-overlap$(EXEEXT): $(custom_overlap_OBJECTS) $(custom_overlap_DEPENDENCIES)
+ @rm -f custom-overlap$(EXEEXT)
+ $(LINK) $(custom_overlap_OBJECTS) $(custom_overlap_LDADD) $(LIBS)
+custom_alloc$(EXEEXT): $(custom_alloc_OBJECTS) $(custom_alloc_DEPENDENCIES)
+ @rm -f custom_alloc$(EXEEXT)
+ $(LINK) $(custom_alloc_OBJECTS) $(custom_alloc_LDADD) $(LIBS)
+deep-backtrace$(EXEEXT): $(deep_backtrace_OBJECTS) $(deep_backtrace_DEPENDENCIES)
+ @rm -f deep-backtrace$(EXEEXT)
+ $(LINK) $(deep_backtrace_OBJECTS) $(deep_backtrace_LDADD) $(LIBS)
+deep_templates$(EXEEXT): $(deep_templates_OBJECTS) $(deep_templates_DEPENDENCIES)
+ @rm -f deep_templates$(EXEEXT)
+ $(deep_templates_LINK) $(deep_templates_OBJECTS) $(deep_templates_LDADD) $(LIBS)
+describe-block$(EXEEXT): $(describe_block_OBJECTS) $(describe_block_DEPENDENCIES)
+ @rm -f describe-block$(EXEEXT)
+ $(LINK) $(describe_block_OBJECTS) $(describe_block_LDADD) $(LIBS)
+doublefree$(EXEEXT): $(doublefree_OBJECTS) $(doublefree_DEPENDENCIES)
+ @rm -f doublefree$(EXEEXT)
+ $(LINK) $(doublefree_OBJECTS) $(doublefree_LDADD) $(LIBS)
+dw4$(EXEEXT): $(dw4_OBJECTS) $(dw4_DEPENDENCIES)
+ @rm -f dw4$(EXEEXT)
+ $(dw4_LINK) $(dw4_OBJECTS) $(dw4_LDADD) $(LIBS)
+err_disable1$(EXEEXT): $(err_disable1_OBJECTS) $(err_disable1_DEPENDENCIES)
+ @rm -f err_disable1$(EXEEXT)
+ $(LINK) $(err_disable1_OBJECTS) $(err_disable1_LDADD) $(LIBS)
+err_disable2$(EXEEXT): $(err_disable2_OBJECTS) $(err_disable2_DEPENDENCIES)
+ @rm -f err_disable2$(EXEEXT)
+ $(LINK) $(err_disable2_OBJECTS) $(err_disable2_LDADD) $(LIBS)
+err_disable3$(EXEEXT): $(err_disable3_OBJECTS) $(err_disable3_DEPENDENCIES)
+ @rm -f err_disable3$(EXEEXT)
+ $(LINK) $(err_disable3_OBJECTS) $(err_disable3_LDADD) $(LIBS)
+err_disable4$(EXEEXT): $(err_disable4_OBJECTS) $(err_disable4_DEPENDENCIES)
+ @rm -f err_disable4$(EXEEXT)
+ $(LINK) $(err_disable4_OBJECTS) $(err_disable4_LDADD) $(LIBS)
+erringfds$(EXEEXT): $(erringfds_OBJECTS) $(erringfds_DEPENDENCIES)
+ @rm -f erringfds$(EXEEXT)
+ $(LINK) $(erringfds_OBJECTS) $(erringfds_LDADD) $(LIBS)
+error_counts$(EXEEXT): $(error_counts_OBJECTS) $(error_counts_DEPENDENCIES)
+ @rm -f error_counts$(EXEEXT)
+ $(error_counts_LINK) $(error_counts_OBJECTS) $(error_counts_LDADD) $(LIBS)
+errs1$(EXEEXT): $(errs1_OBJECTS) $(errs1_DEPENDENCIES)
+ @rm -f errs1$(EXEEXT)
+ $(LINK) $(errs1_OBJECTS) $(errs1_LDADD) $(LIBS)
+execve1$(EXEEXT): $(execve1_OBJECTS) $(execve1_DEPENDENCIES)
+ @rm -f execve1$(EXEEXT)
+ $(execve1_LINK) $(execve1_OBJECTS) $(execve1_LDADD) $(LIBS)
+execve2$(EXEEXT): $(execve2_OBJECTS) $(execve2_DEPENDENCIES)
+ @rm -f execve2$(EXEEXT)
+ $(execve2_LINK) $(execve2_OBJECTS) $(execve2_LDADD) $(LIBS)
+exitprog$(EXEEXT): $(exitprog_OBJECTS) $(exitprog_DEPENDENCIES)
+ @rm -f exitprog$(EXEEXT)
+ $(LINK) $(exitprog_OBJECTS) $(exitprog_LDADD) $(LIBS)
+file_locking$(EXEEXT): $(file_locking_OBJECTS) $(file_locking_DEPENDENCIES)
+ @rm -f file_locking$(EXEEXT)
+ $(LINK) $(file_locking_OBJECTS) $(file_locking_LDADD) $(LIBS)
+fprw$(EXEEXT): $(fprw_OBJECTS) $(fprw_DEPENDENCIES)
+ @rm -f fprw$(EXEEXT)
+ $(LINK) $(fprw_OBJECTS) $(fprw_LDADD) $(LIBS)
+fwrite$(EXEEXT): $(fwrite_OBJECTS) $(fwrite_DEPENDENCIES)
+ @rm -f fwrite$(EXEEXT)
+ $(LINK) $(fwrite_OBJECTS) $(fwrite_LDADD) $(LIBS)
+holey_buffer_too_small$(EXEEXT): $(holey_buffer_too_small_OBJECTS) $(holey_buffer_too_small_DEPENDENCIES)
+ @rm -f holey_buffer_too_small$(EXEEXT)
+ $(LINK) $(holey_buffer_too_small_OBJECTS) $(holey_buffer_too_small_LDADD) $(LIBS)
+inits$(EXEEXT): $(inits_OBJECTS) $(inits_DEPENDENCIES)
+ @rm -f inits$(EXEEXT)
+ $(inits_LINK) $(inits_OBJECTS) $(inits_LDADD) $(LIBS)
+inline$(EXEEXT): $(inline_OBJECTS) $(inline_DEPENDENCIES)
+ @rm -f inline$(EXEEXT)
+ $(LINK) $(inline_OBJECTS) $(inline_LDADD) $(LIBS)
+leak-0$(EXEEXT): $(leak_0_OBJECTS) $(leak_0_DEPENDENCIES)
+ @rm -f leak-0$(EXEEXT)
+ $(LINK) $(leak_0_OBJECTS) $(leak_0_LDADD) $(LIBS)
+leak-cases$(EXEEXT): $(leak_cases_OBJECTS) $(leak_cases_DEPENDENCIES)
+ @rm -f leak-cases$(EXEEXT)
+ $(LINK) $(leak_cases_OBJECTS) $(leak_cases_LDADD) $(LIBS)
+leak-cycle$(EXEEXT): $(leak_cycle_OBJECTS) $(leak_cycle_DEPENDENCIES)
+ @rm -f leak-cycle$(EXEEXT)
+ $(LINK) $(leak_cycle_OBJECTS) $(leak_cycle_LDADD) $(LIBS)
+leak-delta$(EXEEXT): $(leak_delta_OBJECTS) $(leak_delta_DEPENDENCIES)
+ @rm -f leak-delta$(EXEEXT)
+ $(LINK) $(leak_delta_OBJECTS) $(leak_delta_LDADD) $(LIBS)
+leak-pool$(EXEEXT): $(leak_pool_OBJECTS) $(leak_pool_DEPENDENCIES)
+ @rm -f leak-pool$(EXEEXT)
+ $(LINK) $(leak_pool_OBJECTS) $(leak_pool_LDADD) $(LIBS)
+leak-tree$(EXEEXT): $(leak_tree_OBJECTS) $(leak_tree_DEPENDENCIES)
+ @rm -f leak-tree$(EXEEXT)
+ $(LINK) $(leak_tree_OBJECTS) $(leak_tree_LDADD) $(LIBS)
+long-supps$(EXEEXT): $(long_supps_OBJECTS) $(long_supps_DEPENDENCIES)
+ @rm -f long-supps$(EXEEXT)
+ $(LINK) $(long_supps_OBJECTS) $(long_supps_LDADD) $(LIBS)
+long_namespace_xml$(EXEEXT): $(long_namespace_xml_OBJECTS) $(long_namespace_xml_DEPENDENCIES)
+ @rm -f long_namespace_xml$(EXEEXT)
+ $(CXXLINK) $(long_namespace_xml_OBJECTS) $(long_namespace_xml_LDADD) $(LIBS)
+mallinfo$(EXEEXT): $(mallinfo_OBJECTS) $(mallinfo_DEPENDENCIES)
+ @rm -f mallinfo$(EXEEXT)
+ $(LINK) $(mallinfo_OBJECTS) $(mallinfo_LDADD) $(LIBS)
+malloc1$(EXEEXT): $(malloc1_OBJECTS) $(malloc1_DEPENDENCIES)
+ @rm -f malloc1$(EXEEXT)
+ $(LINK) $(malloc1_OBJECTS) $(malloc1_LDADD) $(LIBS)
+malloc2$(EXEEXT): $(malloc2_OBJECTS) $(malloc2_DEPENDENCIES)
+ @rm -f malloc2$(EXEEXT)
+ $(LINK) $(malloc2_OBJECTS) $(malloc2_LDADD) $(LIBS)
+malloc3$(EXEEXT): $(malloc3_OBJECTS) $(malloc3_DEPENDENCIES)
+ @rm -f malloc3$(EXEEXT)
+ $(LINK) $(malloc3_OBJECTS) $(malloc3_LDADD) $(LIBS)
+malloc_free_fill$(EXEEXT): $(malloc_free_fill_OBJECTS) $(malloc_free_fill_DEPENDENCIES)
+ @rm -f malloc_free_fill$(EXEEXT)
+ $(LINK) $(malloc_free_fill_OBJECTS) $(malloc_free_fill_LDADD) $(LIBS)
+malloc_usable$(EXEEXT): $(malloc_usable_OBJECTS) $(malloc_usable_DEPENDENCIES)
+ @rm -f malloc_usable$(EXEEXT)
+ $(LINK) $(malloc_usable_OBJECTS) $(malloc_usable_LDADD) $(LIBS)
+manuel1$(EXEEXT): $(manuel1_OBJECTS) $(manuel1_DEPENDENCIES)
+ @rm -f manuel1$(EXEEXT)
+ $(manuel1_LINK) $(manuel1_OBJECTS) $(manuel1_LDADD) $(LIBS)
+manuel2$(EXEEXT): $(manuel2_OBJECTS) $(manuel2_DEPENDENCIES)
+ @rm -f manuel2$(EXEEXT)
+ $(LINK) $(manuel2_OBJECTS) $(manuel2_LDADD) $(LIBS)
+manuel3$(EXEEXT): $(manuel3_OBJECTS) $(manuel3_DEPENDENCIES)
+ @rm -f manuel3$(EXEEXT)
+ $(LINK) $(manuel3_OBJECTS) $(manuel3_LDADD) $(LIBS)
+match-overrun$(EXEEXT): $(match_overrun_OBJECTS) $(match_overrun_DEPENDENCIES)
+ @rm -f match-overrun$(EXEEXT)
+ $(LINK) $(match_overrun_OBJECTS) $(match_overrun_LDADD) $(LIBS)
+memalign2$(EXEEXT): $(memalign2_OBJECTS) $(memalign2_DEPENDENCIES)
+ @rm -f memalign2$(EXEEXT)
+ $(LINK) $(memalign2_OBJECTS) $(memalign2_LDADD) $(LIBS)
+memalign_test$(EXEEXT): $(memalign_test_OBJECTS) $(memalign_test_DEPENDENCIES)
+ @rm -f memalign_test$(EXEEXT)
+ $(LINK) $(memalign_test_OBJECTS) $(memalign_test_LDADD) $(LIBS)
+memcmptest$(EXEEXT): $(memcmptest_OBJECTS) $(memcmptest_DEPENDENCIES)
+ @rm -f memcmptest$(EXEEXT)
+ $(memcmptest_LINK) $(memcmptest_OBJECTS) $(memcmptest_LDADD) $(LIBS)
+mempool$(EXEEXT): $(mempool_OBJECTS) $(mempool_DEPENDENCIES)
+ @rm -f mempool$(EXEEXT)
+ $(LINK) $(mempool_OBJECTS) $(mempool_LDADD) $(LIBS)
+mempool2$(EXEEXT): $(mempool2_OBJECTS) $(mempool2_DEPENDENCIES)
+ @rm -f mempool2$(EXEEXT)
+ $(LINK) $(mempool2_OBJECTS) $(mempool2_LDADD) $(LIBS)
+metadata$(EXEEXT): $(metadata_OBJECTS) $(metadata_DEPENDENCIES)
+ @rm -f metadata$(EXEEXT)
+ $(LINK) $(metadata_OBJECTS) $(metadata_LDADD) $(LIBS)
+mismatches$(EXEEXT): $(mismatches_OBJECTS) $(mismatches_DEPENDENCIES)
+ @rm -f mismatches$(EXEEXT)
+ $(CXXLINK) $(mismatches_OBJECTS) $(mismatches_LDADD) $(LIBS)
+mmaptest$(EXEEXT): $(mmaptest_OBJECTS) $(mmaptest_DEPENDENCIES)
+ @rm -f mmaptest$(EXEEXT)
+ $(LINK) $(mmaptest_OBJECTS) $(mmaptest_LDADD) $(LIBS)
+nanoleak2$(EXEEXT): $(nanoleak2_OBJECTS) $(nanoleak2_DEPENDENCIES)
+ @rm -f nanoleak2$(EXEEXT)
+ $(LINK) $(nanoleak2_OBJECTS) $(nanoleak2_LDADD) $(LIBS)
+nanoleak_supp$(EXEEXT): $(nanoleak_supp_OBJECTS) $(nanoleak_supp_DEPENDENCIES)
+ @rm -f nanoleak_supp$(EXEEXT)
+ $(LINK) $(nanoleak_supp_OBJECTS) $(nanoleak_supp_LDADD) $(LIBS)
+new_nothrow$(EXEEXT): $(new_nothrow_OBJECTS) $(new_nothrow_DEPENDENCIES)
+ @rm -f new_nothrow$(EXEEXT)
+ $(CXXLINK) $(new_nothrow_OBJECTS) $(new_nothrow_LDADD) $(LIBS)
+new_override$(EXEEXT): $(new_override_OBJECTS) $(new_override_DEPENDENCIES)
+ @rm -f new_override$(EXEEXT)
+ $(CXXLINK) $(new_override_OBJECTS) $(new_override_LDADD) $(LIBS)
+noisy_child$(EXEEXT): $(noisy_child_OBJECTS) $(noisy_child_DEPENDENCIES)
+ @rm -f noisy_child$(EXEEXT)
+ $(LINK) $(noisy_child_OBJECTS) $(noisy_child_LDADD) $(LIBS)
+null_socket$(EXEEXT): $(null_socket_OBJECTS) $(null_socket_DEPENDENCIES)
+ @rm -f null_socket$(EXEEXT)
+ $(LINK) $(null_socket_OBJECTS) $(null_socket_LDADD) $(LIBS)
+origin1-yes$(EXEEXT): $(origin1_yes_OBJECTS) $(origin1_yes_DEPENDENCIES)
+ @rm -f origin1-yes$(EXEEXT)
+ $(LINK) $(origin1_yes_OBJECTS) $(origin1_yes_LDADD) $(LIBS)
+origin2-not-quite$(EXEEXT): $(origin2_not_quite_OBJECTS) $(origin2_not_quite_DEPENDENCIES)
+ @rm -f origin2-not-quite$(EXEEXT)
+ $(origin2_not_quite_LINK) $(origin2_not_quite_OBJECTS) $(origin2_not_quite_LDADD) $(LIBS)
+origin3-no$(EXEEXT): $(origin3_no_OBJECTS) $(origin3_no_DEPENDENCIES)
+ @rm -f origin3-no$(EXEEXT)
+ $(origin3_no_LINK) $(origin3_no_OBJECTS) $(origin3_no_LDADD) $(LIBS)
+origin4-many$(EXEEXT): $(origin4_many_OBJECTS) $(origin4_many_DEPENDENCIES)
+ @rm -f origin4-many$(EXEEXT)
+ $(origin4_many_LINK) $(origin4_many_OBJECTS) $(origin4_many_LDADD) $(LIBS)
+origin5-bz2$(EXEEXT): $(origin5_bz2_OBJECTS) $(origin5_bz2_DEPENDENCIES)
+ @rm -f origin5-bz2$(EXEEXT)
+ $(origin5_bz2_LINK) $(origin5_bz2_OBJECTS) $(origin5_bz2_LDADD) $(LIBS)
+origin6-fp$(EXEEXT): $(origin6_fp_OBJECTS) $(origin6_fp_DEPENDENCIES)
+ @rm -f origin6-fp$(EXEEXT)
+ $(origin6_fp_LINK) $(origin6_fp_OBJECTS) $(origin6_fp_LDADD) $(LIBS)
+overlap$(EXEEXT): $(overlap_OBJECTS) $(overlap_DEPENDENCIES)
+ @rm -f overlap$(EXEEXT)
+ $(overlap_LINK) $(overlap_OBJECTS) $(overlap_LDADD) $(LIBS)
+partial_load$(EXEEXT): $(partial_load_OBJECTS) $(partial_load_DEPENDENCIES)
+ @rm -f partial_load$(EXEEXT)
+ $(LINK) $(partial_load_OBJECTS) $(partial_load_LDADD) $(LIBS)
+partiallydefinedeq$(EXEEXT): $(partiallydefinedeq_OBJECTS) $(partiallydefinedeq_DEPENDENCIES)
+ @rm -f partiallydefinedeq$(EXEEXT)
+ $(LINK) $(partiallydefinedeq_OBJECTS) $(partiallydefinedeq_LDADD) $(LIBS)
+pdb-realloc$(EXEEXT): $(pdb_realloc_OBJECTS) $(pdb_realloc_DEPENDENCIES)
+ @rm -f pdb-realloc$(EXEEXT)
+ $(LINK) $(pdb_realloc_OBJECTS) $(pdb_realloc_LDADD) $(LIBS)
+pdb-realloc2$(EXEEXT): $(pdb_realloc2_OBJECTS) $(pdb_realloc2_DEPENDENCIES)
+ @rm -f pdb-realloc2$(EXEEXT)
+ $(LINK) $(pdb_realloc2_OBJECTS) $(pdb_realloc2_LDADD) $(LIBS)
+pipe$(EXEEXT): $(pipe_OBJECTS) $(pipe_DEPENDENCIES)
+ @rm -f pipe$(EXEEXT)
+ $(LINK) $(pipe_OBJECTS) $(pipe_LDADD) $(LIBS)
+pointer-trace$(EXEEXT): $(pointer_trace_OBJECTS) $(pointer_trace_DEPENDENCIES)
+ @rm -f pointer-trace$(EXEEXT)
+ $(LINK) $(pointer_trace_OBJECTS) $(pointer_trace_LDADD) $(LIBS)
+post-syscall$(EXEEXT): $(post_syscall_OBJECTS) $(post_syscall_DEPENDENCIES)
+ @rm -f post-syscall$(EXEEXT)
+ $(LINK) $(post_syscall_OBJECTS) $(post_syscall_LDADD) $(LIBS)
+realloc1$(EXEEXT): $(realloc1_OBJECTS) $(realloc1_DEPENDENCIES)
+ @rm -f realloc1$(EXEEXT)
+ $(LINK) $(realloc1_OBJECTS) $(realloc1_LDADD) $(LIBS)
+realloc2$(EXEEXT): $(realloc2_OBJECTS) $(realloc2_DEPENDENCIES)
+ @rm -f realloc2$(EXEEXT)
+ $(LINK) $(realloc2_OBJECTS) $(realloc2_LDADD) $(LIBS)
+realloc3$(EXEEXT): $(realloc3_OBJECTS) $(realloc3_DEPENDENCIES)
+ @rm -f realloc3$(EXEEXT)
+ $(LINK) $(realloc3_OBJECTS) $(realloc3_LDADD) $(LIBS)
+sbfragment$(EXEEXT): $(sbfragment_OBJECTS) $(sbfragment_DEPENDENCIES)
+ @rm -f sbfragment$(EXEEXT)
+ $(LINK) $(sbfragment_OBJECTS) $(sbfragment_LDADD) $(LIBS)
+sh-mem$(EXEEXT): $(sh_mem_OBJECTS) $(sh_mem_DEPENDENCIES)
+ @rm -f sh-mem$(EXEEXT)
+ $(LINK) $(sh_mem_OBJECTS) $(sh_mem_LDADD) $(LIBS)
+sh-mem-random$(EXEEXT): $(sh_mem_random_OBJECTS) $(sh_mem_random_DEPENDENCIES)
+ @rm -f sh-mem-random$(EXEEXT)
+ $(LINK) $(sh_mem_random_OBJECTS) $(sh_mem_random_LDADD) $(LIBS)
+sigaltstack$(EXEEXT): $(sigaltstack_OBJECTS) $(sigaltstack_DEPENDENCIES)
+ @rm -f sigaltstack$(EXEEXT)
+ $(LINK) $(sigaltstack_OBJECTS) $(sigaltstack_LDADD) $(LIBS)
+sigkill$(EXEEXT): $(sigkill_OBJECTS) $(sigkill_DEPENDENCIES)
+ @rm -f sigkill$(EXEEXT)
+ $(LINK) $(sigkill_OBJECTS) $(sigkill_LDADD) $(LIBS)
+signal2$(EXEEXT): $(signal2_OBJECTS) $(signal2_DEPENDENCIES)
+ @rm -f signal2$(EXEEXT)
+ $(LINK) $(signal2_OBJECTS) $(signal2_LDADD) $(LIBS)
+sigprocmask$(EXEEXT): $(sigprocmask_OBJECTS) $(sigprocmask_DEPENDENCIES)
+ @rm -f sigprocmask$(EXEEXT)
+ $(LINK) $(sigprocmask_OBJECTS) $(sigprocmask_LDADD) $(LIBS)
+static_malloc$(EXEEXT): $(static_malloc_OBJECTS) $(static_malloc_DEPENDENCIES)
+ @rm -f static_malloc$(EXEEXT)
+ $(LINK) $(static_malloc_OBJECTS) $(static_malloc_LDADD) $(LIBS)
+str_tester$(EXEEXT): $(str_tester_OBJECTS) $(str_tester_DEPENDENCIES)
+ @rm -f str_tester$(EXEEXT)
+ $(str_tester_LINK) $(str_tester_OBJECTS) $(str_tester_LDADD) $(LIBS)
+strchr$(EXEEXT): $(strchr_OBJECTS) $(strchr_DEPENDENCIES)
+ @rm -f strchr$(EXEEXT)
+ $(LINK) $(strchr_OBJECTS) $(strchr_LDADD) $(LIBS)
+supp1$(EXEEXT): $(supp1_OBJECTS) $(supp1_DEPENDENCIES)
+ @rm -f supp1$(EXEEXT)
+ $(LINK) $(supp1_OBJECTS) $(supp1_LDADD) $(LIBS)
+supp2$(EXEEXT): $(supp2_OBJECTS) $(supp2_DEPENDENCIES)
+ @rm -f supp2$(EXEEXT)
+ $(LINK) $(supp2_OBJECTS) $(supp2_LDADD) $(LIBS)
+supp_unknown$(EXEEXT): $(supp_unknown_OBJECTS) $(supp_unknown_DEPENDENCIES)
+ @rm -f supp_unknown$(EXEEXT)
+ $(LINK) $(supp_unknown_OBJECTS) $(supp_unknown_LDADD) $(LIBS)
+suppfree$(EXEEXT): $(suppfree_OBJECTS) $(suppfree_DEPENDENCIES)
+ @rm -f suppfree$(EXEEXT)
+ $(LINK) $(suppfree_OBJECTS) $(suppfree_LDADD) $(LIBS)
+test-plo$(EXEEXT): $(test_plo_OBJECTS) $(test_plo_DEPENDENCIES)
+ @rm -f test-plo$(EXEEXT)
+ $(LINK) $(test_plo_OBJECTS) $(test_plo_LDADD) $(LIBS)
+trivialleak$(EXEEXT): $(trivialleak_OBJECTS) $(trivialleak_DEPENDENCIES)
+ @rm -f trivialleak$(EXEEXT)
+ $(LINK) $(trivialleak_OBJECTS) $(trivialleak_LDADD) $(LIBS)
+unit_libcbase$(EXEEXT): $(unit_libcbase_OBJECTS) $(unit_libcbase_DEPENDENCIES)
+ @rm -f unit_libcbase$(EXEEXT)
+ $(LINK) $(unit_libcbase_OBJECTS) $(unit_libcbase_LDADD) $(LIBS)
+unit_oset$(EXEEXT): $(unit_oset_OBJECTS) $(unit_oset_DEPENDENCIES)
+ @rm -f unit_oset$(EXEEXT)
+ $(LINK) $(unit_oset_OBJECTS) $(unit_oset_LDADD) $(LIBS)
+varinfo1$(EXEEXT): $(varinfo1_OBJECTS) $(varinfo1_DEPENDENCIES)
+ @rm -f varinfo1$(EXEEXT)
+ $(varinfo1_LINK) $(varinfo1_OBJECTS) $(varinfo1_LDADD) $(LIBS)
+varinfo2$(EXEEXT): $(varinfo2_OBJECTS) $(varinfo2_DEPENDENCIES)
+ @rm -f varinfo2$(EXEEXT)
+ $(varinfo2_LINK) $(varinfo2_OBJECTS) $(varinfo2_LDADD) $(LIBS)
+varinfo3$(EXEEXT): $(varinfo3_OBJECTS) $(varinfo3_DEPENDENCIES)
+ @rm -f varinfo3$(EXEEXT)
+ $(varinfo3_LINK) $(varinfo3_OBJECTS) $(varinfo3_LDADD) $(LIBS)
+varinfo4$(EXEEXT): $(varinfo4_OBJECTS) $(varinfo4_DEPENDENCIES)
+ @rm -f varinfo4$(EXEEXT)
+ $(varinfo4_LINK) $(varinfo4_OBJECTS) $(varinfo4_LDADD) $(LIBS)
+varinfo5$(EXEEXT): $(varinfo5_OBJECTS) $(varinfo5_DEPENDENCIES)
+ @rm -f varinfo5$(EXEEXT)
+ $(varinfo5_LINK) $(varinfo5_OBJECTS) $(varinfo5_LDADD) $(LIBS)
+varinfo5so.so$(EXEEXT): $(varinfo5so_so_OBJECTS) $(varinfo5so_so_DEPENDENCIES)
+ @rm -f varinfo5so.so$(EXEEXT)
+ $(varinfo5so_so_LINK) $(varinfo5so_so_OBJECTS) $(varinfo5so_so_LDADD) $(LIBS)
+varinfo6$(EXEEXT): $(varinfo6_OBJECTS) $(varinfo6_DEPENDENCIES)
+ @rm -f varinfo6$(EXEEXT)
+ $(varinfo6_LINK) $(varinfo6_OBJECTS) $(varinfo6_LDADD) $(LIBS)
+vcpu_fbench$(EXEEXT): $(vcpu_fbench_OBJECTS) $(vcpu_fbench_DEPENDENCIES)
+ @rm -f vcpu_fbench$(EXEEXT)
+ $(vcpu_fbench_LINK) $(vcpu_fbench_OBJECTS) $(vcpu_fbench_LDADD) $(LIBS)
+vcpu_fnfns$(EXEEXT): $(vcpu_fnfns_OBJECTS) $(vcpu_fnfns_DEPENDENCIES)
+ @rm -f vcpu_fnfns$(EXEEXT)
+ $(vcpu_fnfns_LINK) $(vcpu_fnfns_OBJECTS) $(vcpu_fnfns_LDADD) $(LIBS)
+wrap1$(EXEEXT): $(wrap1_OBJECTS) $(wrap1_DEPENDENCIES)
+ @rm -f wrap1$(EXEEXT)
+ $(LINK) $(wrap1_OBJECTS) $(wrap1_LDADD) $(LIBS)
+wrap2$(EXEEXT): $(wrap2_OBJECTS) $(wrap2_DEPENDENCIES)
+ @rm -f wrap2$(EXEEXT)
+ $(LINK) $(wrap2_OBJECTS) $(wrap2_LDADD) $(LIBS)
+wrap3$(EXEEXT): $(wrap3_OBJECTS) $(wrap3_DEPENDENCIES)
+ @rm -f wrap3$(EXEEXT)
+ $(LINK) $(wrap3_OBJECTS) $(wrap3_LDADD) $(LIBS)
+wrap4$(EXEEXT): $(wrap4_OBJECTS) $(wrap4_DEPENDENCIES)
+ @rm -f wrap4$(EXEEXT)
+ $(LINK) $(wrap4_OBJECTS) $(wrap4_LDADD) $(LIBS)
+wrap5$(EXEEXT): $(wrap5_OBJECTS) $(wrap5_DEPENDENCIES)
+ @rm -f wrap5$(EXEEXT)
+ $(LINK) $(wrap5_OBJECTS) $(wrap5_LDADD) $(LIBS)
+wrap6$(EXEEXT): $(wrap6_OBJECTS) $(wrap6_DEPENDENCIES)
+ @rm -f wrap6$(EXEEXT)
+ $(wrap6_LINK) $(wrap6_OBJECTS) $(wrap6_LDADD) $(LIBS)
+wrap7$(EXEEXT): $(wrap7_OBJECTS) $(wrap7_DEPENDENCIES)
+ @rm -f wrap7$(EXEEXT)
+ $(wrap7_LINK) $(wrap7_OBJECTS) $(wrap7_LDADD) $(LIBS)
+wrap7so.so$(EXEEXT): $(wrap7so_so_OBJECTS) $(wrap7so_so_DEPENDENCIES)
+ @rm -f wrap7so.so$(EXEEXT)
+ $(wrap7so_so_LINK) $(wrap7so_so_OBJECTS) $(wrap7so_so_LDADD) $(LIBS)
+wrap8$(EXEEXT): $(wrap8_OBJECTS) $(wrap8_DEPENDENCIES)
+ @rm -f wrap8$(EXEEXT)
+ $(LINK) $(wrap8_OBJECTS) $(wrap8_LDADD) $(LIBS)
+writev1$(EXEEXT): $(writev1_OBJECTS) $(writev1_DEPENDENCIES)
+ @rm -f writev1$(EXEEXT)
+ $(LINK) $(writev1_OBJECTS) $(writev1_LDADD) $(LIBS)
+xml1$(EXEEXT): $(xml1_OBJECTS) $(xml1_DEPENDENCIES)
+ @rm -f xml1$(EXEEXT)
+ $(LINK) $(xml1_OBJECTS) $(xml1_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/accounting.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/addressable.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/atomic_incs-atomic_incs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/badaddrvalue.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/badfree.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/badjump.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/badjump2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/badloop.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/badpoll.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/badrw.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/big_blocks_freed_list.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/brk2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/buflen_check.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug287260.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/calloc-overflow.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clientperm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clireq_nofill.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clo_redzone.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/custom-overlap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/custom_alloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/deep-backtrace.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/deep_templates-deep_templates.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/describe-block.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/doublefree.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dw4-dw4.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/err_disable1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/err_disable2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/err_disable3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/err_disable4.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/erringfds.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/error_counts-error_counts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/errs1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/execve1-execve1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/execve2-execve2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/exitprog.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/file_locking.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fprw.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fwrite.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/holey_buffer_too_small.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/inits-inits.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/inline.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/leak-0.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/leak-cases.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/leak-cycle.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/leak-delta.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/leak-pool.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/leak-tree.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/long-supps.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/long_namespace_xml.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mallinfo.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/malloc1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/malloc2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/malloc3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/malloc_free_fill.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/malloc_usable.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/manuel1-manuel1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/manuel2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/manuel3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/match-overrun.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memalign2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memalign_test.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memcmptest-memcmptest.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mempool.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mempool2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/metadata.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mismatches.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mmaptest.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nanoleak2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nanoleak_supp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/new_nothrow.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/new_override.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/noisy_child.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/null_socket.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/origin1-yes.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/origin2_not_quite-origin2-not-quite.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/origin3_no-origin3-no.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/origin4_many-origin4-many.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/origin5_bz2-origin5-bz2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/origin6_fp-origin6-fp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/overlap-overlap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/partial_load.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/partiallydefinedeq.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pdb-realloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pdb-realloc2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pipe.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pointer-trace.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/post-syscall.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/realloc1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/realloc2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/realloc3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sbfragment.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh-mem-random.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh-mem.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigaltstack.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigkill.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/signal2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigprocmask.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/static_malloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/str_tester-str_tester.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/strchr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/supp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/suppfree.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test-plo.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/trivialleak.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/unit_libcbase.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/unit_oset.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/varinfo1-varinfo1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/varinfo2-varinfo2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/varinfo3-varinfo3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/varinfo4-varinfo4.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/varinfo5-varinfo5.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/varinfo5so_so-varinfo5so.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/varinfo6-varinfo6.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vcpu_fbench-vcpu_fbench.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vcpu_fnfns-vcpu_fnfns.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wrap1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wrap2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wrap3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wrap4.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wrap5.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wrap6-wrap6.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wrap7.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wrap7so_so-wrap7so.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wrap8.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/writev1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xml1.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+atomic_incs-atomic_incs.o: atomic_incs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(atomic_incs_CFLAGS) $(CFLAGS) -MT atomic_incs-atomic_incs.o -MD -MP -MF $(DEPDIR)/atomic_incs-atomic_incs.Tpo -c -o atomic_incs-atomic_incs.o `test -f 'atomic_incs.c' || echo '$(srcdir)/'`atomic_incs.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/atomic_incs-atomic_incs.Tpo $(DEPDIR)/atomic_incs-atomic_incs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='atomic_incs.c' object='atomic_incs-atomic_incs.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(atomic_incs_CFLAGS) $(CFLAGS) -c -o atomic_incs-atomic_incs.o `test -f 'atomic_incs.c' || echo '$(srcdir)/'`atomic_incs.c
+
+atomic_incs-atomic_incs.obj: atomic_incs.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(atomic_incs_CFLAGS) $(CFLAGS) -MT atomic_incs-atomic_incs.obj -MD -MP -MF $(DEPDIR)/atomic_incs-atomic_incs.Tpo -c -o atomic_incs-atomic_incs.obj `if test -f 'atomic_incs.c'; then $(CYGPATH_W) 'atomic_incs.c'; else $(CYGPATH_W) '$(srcdir)/atomic_incs.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/atomic_incs-atomic_incs.Tpo $(DEPDIR)/atomic_incs-atomic_incs.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='atomic_incs.c' object='atomic_incs-atomic_incs.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(atomic_incs_CFLAGS) $(CFLAGS) -c -o atomic_incs-atomic_incs.obj `if test -f 'atomic_incs.c'; then $(CYGPATH_W) 'atomic_incs.c'; else $(CYGPATH_W) '$(srcdir)/atomic_incs.c'; fi`
+
+dw4-dw4.o: dw4.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(dw4_CFLAGS) $(CFLAGS) -MT dw4-dw4.o -MD -MP -MF $(DEPDIR)/dw4-dw4.Tpo -c -o dw4-dw4.o `test -f 'dw4.c' || echo '$(srcdir)/'`dw4.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/dw4-dw4.Tpo $(DEPDIR)/dw4-dw4.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='dw4.c' object='dw4-dw4.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(dw4_CFLAGS) $(CFLAGS) -c -o dw4-dw4.o `test -f 'dw4.c' || echo '$(srcdir)/'`dw4.c
+
+dw4-dw4.obj: dw4.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(dw4_CFLAGS) $(CFLAGS) -MT dw4-dw4.obj -MD -MP -MF $(DEPDIR)/dw4-dw4.Tpo -c -o dw4-dw4.obj `if test -f 'dw4.c'; then $(CYGPATH_W) 'dw4.c'; else $(CYGPATH_W) '$(srcdir)/dw4.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/dw4-dw4.Tpo $(DEPDIR)/dw4-dw4.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='dw4.c' object='dw4-dw4.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(dw4_CFLAGS) $(CFLAGS) -c -o dw4-dw4.obj `if test -f 'dw4.c'; then $(CYGPATH_W) 'dw4.c'; else $(CYGPATH_W) '$(srcdir)/dw4.c'; fi`
+
+error_counts-error_counts.o: error_counts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(error_counts_CFLAGS) $(CFLAGS) -MT error_counts-error_counts.o -MD -MP -MF $(DEPDIR)/error_counts-error_counts.Tpo -c -o error_counts-error_counts.o `test -f 'error_counts.c' || echo '$(srcdir)/'`error_counts.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/error_counts-error_counts.Tpo $(DEPDIR)/error_counts-error_counts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='error_counts.c' object='error_counts-error_counts.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(error_counts_CFLAGS) $(CFLAGS) -c -o error_counts-error_counts.o `test -f 'error_counts.c' || echo '$(srcdir)/'`error_counts.c
+
+error_counts-error_counts.obj: error_counts.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(error_counts_CFLAGS) $(CFLAGS) -MT error_counts-error_counts.obj -MD -MP -MF $(DEPDIR)/error_counts-error_counts.Tpo -c -o error_counts-error_counts.obj `if test -f 'error_counts.c'; then $(CYGPATH_W) 'error_counts.c'; else $(CYGPATH_W) '$(srcdir)/error_counts.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/error_counts-error_counts.Tpo $(DEPDIR)/error_counts-error_counts.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='error_counts.c' object='error_counts-error_counts.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(error_counts_CFLAGS) $(CFLAGS) -c -o error_counts-error_counts.obj `if test -f 'error_counts.c'; then $(CYGPATH_W) 'error_counts.c'; else $(CYGPATH_W) '$(srcdir)/error_counts.c'; fi`
+
+execve1-execve1.o: execve1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve1_CFLAGS) $(CFLAGS) -MT execve1-execve1.o -MD -MP -MF $(DEPDIR)/execve1-execve1.Tpo -c -o execve1-execve1.o `test -f 'execve1.c' || echo '$(srcdir)/'`execve1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/execve1-execve1.Tpo $(DEPDIR)/execve1-execve1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='execve1.c' object='execve1-execve1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve1_CFLAGS) $(CFLAGS) -c -o execve1-execve1.o `test -f 'execve1.c' || echo '$(srcdir)/'`execve1.c
+
+execve1-execve1.obj: execve1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve1_CFLAGS) $(CFLAGS) -MT execve1-execve1.obj -MD -MP -MF $(DEPDIR)/execve1-execve1.Tpo -c -o execve1-execve1.obj `if test -f 'execve1.c'; then $(CYGPATH_W) 'execve1.c'; else $(CYGPATH_W) '$(srcdir)/execve1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/execve1-execve1.Tpo $(DEPDIR)/execve1-execve1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='execve1.c' object='execve1-execve1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve1_CFLAGS) $(CFLAGS) -c -o execve1-execve1.obj `if test -f 'execve1.c'; then $(CYGPATH_W) 'execve1.c'; else $(CYGPATH_W) '$(srcdir)/execve1.c'; fi`
+
+execve2-execve2.o: execve2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve2_CFLAGS) $(CFLAGS) -MT execve2-execve2.o -MD -MP -MF $(DEPDIR)/execve2-execve2.Tpo -c -o execve2-execve2.o `test -f 'execve2.c' || echo '$(srcdir)/'`execve2.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/execve2-execve2.Tpo $(DEPDIR)/execve2-execve2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='execve2.c' object='execve2-execve2.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve2_CFLAGS) $(CFLAGS) -c -o execve2-execve2.o `test -f 'execve2.c' || echo '$(srcdir)/'`execve2.c
+
+execve2-execve2.obj: execve2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve2_CFLAGS) $(CFLAGS) -MT execve2-execve2.obj -MD -MP -MF $(DEPDIR)/execve2-execve2.Tpo -c -o execve2-execve2.obj `if test -f 'execve2.c'; then $(CYGPATH_W) 'execve2.c'; else $(CYGPATH_W) '$(srcdir)/execve2.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/execve2-execve2.Tpo $(DEPDIR)/execve2-execve2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='execve2.c' object='execve2-execve2.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve2_CFLAGS) $(CFLAGS) -c -o execve2-execve2.obj `if test -f 'execve2.c'; then $(CYGPATH_W) 'execve2.c'; else $(CYGPATH_W) '$(srcdir)/execve2.c'; fi`
+
+inits-inits.o: inits.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(inits_CFLAGS) $(CFLAGS) -MT inits-inits.o -MD -MP -MF $(DEPDIR)/inits-inits.Tpo -c -o inits-inits.o `test -f 'inits.c' || echo '$(srcdir)/'`inits.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/inits-inits.Tpo $(DEPDIR)/inits-inits.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='inits.c' object='inits-inits.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(inits_CFLAGS) $(CFLAGS) -c -o inits-inits.o `test -f 'inits.c' || echo '$(srcdir)/'`inits.c
+
+inits-inits.obj: inits.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(inits_CFLAGS) $(CFLAGS) -MT inits-inits.obj -MD -MP -MF $(DEPDIR)/inits-inits.Tpo -c -o inits-inits.obj `if test -f 'inits.c'; then $(CYGPATH_W) 'inits.c'; else $(CYGPATH_W) '$(srcdir)/inits.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/inits-inits.Tpo $(DEPDIR)/inits-inits.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='inits.c' object='inits-inits.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(inits_CFLAGS) $(CFLAGS) -c -o inits-inits.obj `if test -f 'inits.c'; then $(CYGPATH_W) 'inits.c'; else $(CYGPATH_W) '$(srcdir)/inits.c'; fi`
+
+manuel1-manuel1.o: manuel1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(manuel1_CFLAGS) $(CFLAGS) -MT manuel1-manuel1.o -MD -MP -MF $(DEPDIR)/manuel1-manuel1.Tpo -c -o manuel1-manuel1.o `test -f 'manuel1.c' || echo '$(srcdir)/'`manuel1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/manuel1-manuel1.Tpo $(DEPDIR)/manuel1-manuel1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='manuel1.c' object='manuel1-manuel1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(manuel1_CFLAGS) $(CFLAGS) -c -o manuel1-manuel1.o `test -f 'manuel1.c' || echo '$(srcdir)/'`manuel1.c
+
+manuel1-manuel1.obj: manuel1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(manuel1_CFLAGS) $(CFLAGS) -MT manuel1-manuel1.obj -MD -MP -MF $(DEPDIR)/manuel1-manuel1.Tpo -c -o manuel1-manuel1.obj `if test -f 'manuel1.c'; then $(CYGPATH_W) 'manuel1.c'; else $(CYGPATH_W) '$(srcdir)/manuel1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/manuel1-manuel1.Tpo $(DEPDIR)/manuel1-manuel1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='manuel1.c' object='manuel1-manuel1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(manuel1_CFLAGS) $(CFLAGS) -c -o manuel1-manuel1.obj `if test -f 'manuel1.c'; then $(CYGPATH_W) 'manuel1.c'; else $(CYGPATH_W) '$(srcdir)/manuel1.c'; fi`
+
+memcmptest-memcmptest.o: memcmptest.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(memcmptest_CFLAGS) $(CFLAGS) -MT memcmptest-memcmptest.o -MD -MP -MF $(DEPDIR)/memcmptest-memcmptest.Tpo -c -o memcmptest-memcmptest.o `test -f 'memcmptest.c' || echo '$(srcdir)/'`memcmptest.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcmptest-memcmptest.Tpo $(DEPDIR)/memcmptest-memcmptest.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='memcmptest.c' object='memcmptest-memcmptest.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(memcmptest_CFLAGS) $(CFLAGS) -c -o memcmptest-memcmptest.o `test -f 'memcmptest.c' || echo '$(srcdir)/'`memcmptest.c
+
+memcmptest-memcmptest.obj: memcmptest.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(memcmptest_CFLAGS) $(CFLAGS) -MT memcmptest-memcmptest.obj -MD -MP -MF $(DEPDIR)/memcmptest-memcmptest.Tpo -c -o memcmptest-memcmptest.obj `if test -f 'memcmptest.c'; then $(CYGPATH_W) 'memcmptest.c'; else $(CYGPATH_W) '$(srcdir)/memcmptest.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/memcmptest-memcmptest.Tpo $(DEPDIR)/memcmptest-memcmptest.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='memcmptest.c' object='memcmptest-memcmptest.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(memcmptest_CFLAGS) $(CFLAGS) -c -o memcmptest-memcmptest.obj `if test -f 'memcmptest.c'; then $(CYGPATH_W) 'memcmptest.c'; else $(CYGPATH_W) '$(srcdir)/memcmptest.c'; fi`
+
+origin2_not_quite-origin2-not-quite.o: origin2-not-quite.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin2_not_quite_CFLAGS) $(CFLAGS) -MT origin2_not_quite-origin2-not-quite.o -MD -MP -MF $(DEPDIR)/origin2_not_quite-origin2-not-quite.Tpo -c -o origin2_not_quite-origin2-not-quite.o `test -f 'origin2-not-quite.c' || echo '$(srcdir)/'`origin2-not-quite.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin2_not_quite-origin2-not-quite.Tpo $(DEPDIR)/origin2_not_quite-origin2-not-quite.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin2-not-quite.c' object='origin2_not_quite-origin2-not-quite.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin2_not_quite_CFLAGS) $(CFLAGS) -c -o origin2_not_quite-origin2-not-quite.o `test -f 'origin2-not-quite.c' || echo '$(srcdir)/'`origin2-not-quite.c
+
+origin2_not_quite-origin2-not-quite.obj: origin2-not-quite.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin2_not_quite_CFLAGS) $(CFLAGS) -MT origin2_not_quite-origin2-not-quite.obj -MD -MP -MF $(DEPDIR)/origin2_not_quite-origin2-not-quite.Tpo -c -o origin2_not_quite-origin2-not-quite.obj `if test -f 'origin2-not-quite.c'; then $(CYGPATH_W) 'origin2-not-quite.c'; else $(CYGPATH_W) '$(srcdir)/origin2-not-quite.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin2_not_quite-origin2-not-quite.Tpo $(DEPDIR)/origin2_not_quite-origin2-not-quite.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin2-not-quite.c' object='origin2_not_quite-origin2-not-quite.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin2_not_quite_CFLAGS) $(CFLAGS) -c -o origin2_not_quite-origin2-not-quite.obj `if test -f 'origin2-not-quite.c'; then $(CYGPATH_W) 'origin2-not-quite.c'; else $(CYGPATH_W) '$(srcdir)/origin2-not-quite.c'; fi`
+
+origin3_no-origin3-no.o: origin3-no.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin3_no_CFLAGS) $(CFLAGS) -MT origin3_no-origin3-no.o -MD -MP -MF $(DEPDIR)/origin3_no-origin3-no.Tpo -c -o origin3_no-origin3-no.o `test -f 'origin3-no.c' || echo '$(srcdir)/'`origin3-no.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin3_no-origin3-no.Tpo $(DEPDIR)/origin3_no-origin3-no.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin3-no.c' object='origin3_no-origin3-no.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin3_no_CFLAGS) $(CFLAGS) -c -o origin3_no-origin3-no.o `test -f 'origin3-no.c' || echo '$(srcdir)/'`origin3-no.c
+
+origin3_no-origin3-no.obj: origin3-no.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin3_no_CFLAGS) $(CFLAGS) -MT origin3_no-origin3-no.obj -MD -MP -MF $(DEPDIR)/origin3_no-origin3-no.Tpo -c -o origin3_no-origin3-no.obj `if test -f 'origin3-no.c'; then $(CYGPATH_W) 'origin3-no.c'; else $(CYGPATH_W) '$(srcdir)/origin3-no.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin3_no-origin3-no.Tpo $(DEPDIR)/origin3_no-origin3-no.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin3-no.c' object='origin3_no-origin3-no.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin3_no_CFLAGS) $(CFLAGS) -c -o origin3_no-origin3-no.obj `if test -f 'origin3-no.c'; then $(CYGPATH_W) 'origin3-no.c'; else $(CYGPATH_W) '$(srcdir)/origin3-no.c'; fi`
+
+origin4_many-origin4-many.o: origin4-many.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin4_many_CFLAGS) $(CFLAGS) -MT origin4_many-origin4-many.o -MD -MP -MF $(DEPDIR)/origin4_many-origin4-many.Tpo -c -o origin4_many-origin4-many.o `test -f 'origin4-many.c' || echo '$(srcdir)/'`origin4-many.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin4_many-origin4-many.Tpo $(DEPDIR)/origin4_many-origin4-many.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin4-many.c' object='origin4_many-origin4-many.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin4_many_CFLAGS) $(CFLAGS) -c -o origin4_many-origin4-many.o `test -f 'origin4-many.c' || echo '$(srcdir)/'`origin4-many.c
+
+origin4_many-origin4-many.obj: origin4-many.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin4_many_CFLAGS) $(CFLAGS) -MT origin4_many-origin4-many.obj -MD -MP -MF $(DEPDIR)/origin4_many-origin4-many.Tpo -c -o origin4_many-origin4-many.obj `if test -f 'origin4-many.c'; then $(CYGPATH_W) 'origin4-many.c'; else $(CYGPATH_W) '$(srcdir)/origin4-many.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin4_many-origin4-many.Tpo $(DEPDIR)/origin4_many-origin4-many.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin4-many.c' object='origin4_many-origin4-many.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin4_many_CFLAGS) $(CFLAGS) -c -o origin4_many-origin4-many.obj `if test -f 'origin4-many.c'; then $(CYGPATH_W) 'origin4-many.c'; else $(CYGPATH_W) '$(srcdir)/origin4-many.c'; fi`
+
+origin5_bz2-origin5-bz2.o: origin5-bz2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin5_bz2_CFLAGS) $(CFLAGS) -MT origin5_bz2-origin5-bz2.o -MD -MP -MF $(DEPDIR)/origin5_bz2-origin5-bz2.Tpo -c -o origin5_bz2-origin5-bz2.o `test -f 'origin5-bz2.c' || echo '$(srcdir)/'`origin5-bz2.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin5_bz2-origin5-bz2.Tpo $(DEPDIR)/origin5_bz2-origin5-bz2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin5-bz2.c' object='origin5_bz2-origin5-bz2.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin5_bz2_CFLAGS) $(CFLAGS) -c -o origin5_bz2-origin5-bz2.o `test -f 'origin5-bz2.c' || echo '$(srcdir)/'`origin5-bz2.c
+
+origin5_bz2-origin5-bz2.obj: origin5-bz2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin5_bz2_CFLAGS) $(CFLAGS) -MT origin5_bz2-origin5-bz2.obj -MD -MP -MF $(DEPDIR)/origin5_bz2-origin5-bz2.Tpo -c -o origin5_bz2-origin5-bz2.obj `if test -f 'origin5-bz2.c'; then $(CYGPATH_W) 'origin5-bz2.c'; else $(CYGPATH_W) '$(srcdir)/origin5-bz2.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin5_bz2-origin5-bz2.Tpo $(DEPDIR)/origin5_bz2-origin5-bz2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin5-bz2.c' object='origin5_bz2-origin5-bz2.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin5_bz2_CFLAGS) $(CFLAGS) -c -o origin5_bz2-origin5-bz2.obj `if test -f 'origin5-bz2.c'; then $(CYGPATH_W) 'origin5-bz2.c'; else $(CYGPATH_W) '$(srcdir)/origin5-bz2.c'; fi`
+
+origin6_fp-origin6-fp.o: origin6-fp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin6_fp_CFLAGS) $(CFLAGS) -MT origin6_fp-origin6-fp.o -MD -MP -MF $(DEPDIR)/origin6_fp-origin6-fp.Tpo -c -o origin6_fp-origin6-fp.o `test -f 'origin6-fp.c' || echo '$(srcdir)/'`origin6-fp.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin6_fp-origin6-fp.Tpo $(DEPDIR)/origin6_fp-origin6-fp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin6-fp.c' object='origin6_fp-origin6-fp.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin6_fp_CFLAGS) $(CFLAGS) -c -o origin6_fp-origin6-fp.o `test -f 'origin6-fp.c' || echo '$(srcdir)/'`origin6-fp.c
+
+origin6_fp-origin6-fp.obj: origin6-fp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin6_fp_CFLAGS) $(CFLAGS) -MT origin6_fp-origin6-fp.obj -MD -MP -MF $(DEPDIR)/origin6_fp-origin6-fp.Tpo -c -o origin6_fp-origin6-fp.obj `if test -f 'origin6-fp.c'; then $(CYGPATH_W) 'origin6-fp.c'; else $(CYGPATH_W) '$(srcdir)/origin6-fp.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/origin6_fp-origin6-fp.Tpo $(DEPDIR)/origin6_fp-origin6-fp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='origin6-fp.c' object='origin6_fp-origin6-fp.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(origin6_fp_CFLAGS) $(CFLAGS) -c -o origin6_fp-origin6-fp.obj `if test -f 'origin6-fp.c'; then $(CYGPATH_W) 'origin6-fp.c'; else $(CYGPATH_W) '$(srcdir)/origin6-fp.c'; fi`
+
+overlap-overlap.o: overlap.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(overlap_CFLAGS) $(CFLAGS) -MT overlap-overlap.o -MD -MP -MF $(DEPDIR)/overlap-overlap.Tpo -c -o overlap-overlap.o `test -f 'overlap.c' || echo '$(srcdir)/'`overlap.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/overlap-overlap.Tpo $(DEPDIR)/overlap-overlap.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='overlap.c' object='overlap-overlap.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(overlap_CFLAGS) $(CFLAGS) -c -o overlap-overlap.o `test -f 'overlap.c' || echo '$(srcdir)/'`overlap.c
+
+overlap-overlap.obj: overlap.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(overlap_CFLAGS) $(CFLAGS) -MT overlap-overlap.obj -MD -MP -MF $(DEPDIR)/overlap-overlap.Tpo -c -o overlap-overlap.obj `if test -f 'overlap.c'; then $(CYGPATH_W) 'overlap.c'; else $(CYGPATH_W) '$(srcdir)/overlap.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/overlap-overlap.Tpo $(DEPDIR)/overlap-overlap.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='overlap.c' object='overlap-overlap.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(overlap_CFLAGS) $(CFLAGS) -c -o overlap-overlap.obj `if test -f 'overlap.c'; then $(CYGPATH_W) 'overlap.c'; else $(CYGPATH_W) '$(srcdir)/overlap.c'; fi`
+
+str_tester-str_tester.o: str_tester.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(str_tester_CFLAGS) $(CFLAGS) -MT str_tester-str_tester.o -MD -MP -MF $(DEPDIR)/str_tester-str_tester.Tpo -c -o str_tester-str_tester.o `test -f 'str_tester.c' || echo '$(srcdir)/'`str_tester.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/str_tester-str_tester.Tpo $(DEPDIR)/str_tester-str_tester.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='str_tester.c' object='str_tester-str_tester.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(str_tester_CFLAGS) $(CFLAGS) -c -o str_tester-str_tester.o `test -f 'str_tester.c' || echo '$(srcdir)/'`str_tester.c
+
+str_tester-str_tester.obj: str_tester.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(str_tester_CFLAGS) $(CFLAGS) -MT str_tester-str_tester.obj -MD -MP -MF $(DEPDIR)/str_tester-str_tester.Tpo -c -o str_tester-str_tester.obj `if test -f 'str_tester.c'; then $(CYGPATH_W) 'str_tester.c'; else $(CYGPATH_W) '$(srcdir)/str_tester.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/str_tester-str_tester.Tpo $(DEPDIR)/str_tester-str_tester.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='str_tester.c' object='str_tester-str_tester.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(str_tester_CFLAGS) $(CFLAGS) -c -o str_tester-str_tester.obj `if test -f 'str_tester.c'; then $(CYGPATH_W) 'str_tester.c'; else $(CYGPATH_W) '$(srcdir)/str_tester.c'; fi`
+
+varinfo1-varinfo1.o: varinfo1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo1_CFLAGS) $(CFLAGS) -MT varinfo1-varinfo1.o -MD -MP -MF $(DEPDIR)/varinfo1-varinfo1.Tpo -c -o varinfo1-varinfo1.o `test -f 'varinfo1.c' || echo '$(srcdir)/'`varinfo1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo1-varinfo1.Tpo $(DEPDIR)/varinfo1-varinfo1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo1.c' object='varinfo1-varinfo1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo1_CFLAGS) $(CFLAGS) -c -o varinfo1-varinfo1.o `test -f 'varinfo1.c' || echo '$(srcdir)/'`varinfo1.c
+
+varinfo1-varinfo1.obj: varinfo1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo1_CFLAGS) $(CFLAGS) -MT varinfo1-varinfo1.obj -MD -MP -MF $(DEPDIR)/varinfo1-varinfo1.Tpo -c -o varinfo1-varinfo1.obj `if test -f 'varinfo1.c'; then $(CYGPATH_W) 'varinfo1.c'; else $(CYGPATH_W) '$(srcdir)/varinfo1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo1-varinfo1.Tpo $(DEPDIR)/varinfo1-varinfo1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo1.c' object='varinfo1-varinfo1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo1_CFLAGS) $(CFLAGS) -c -o varinfo1-varinfo1.obj `if test -f 'varinfo1.c'; then $(CYGPATH_W) 'varinfo1.c'; else $(CYGPATH_W) '$(srcdir)/varinfo1.c'; fi`
+
+varinfo2-varinfo2.o: varinfo2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo2_CFLAGS) $(CFLAGS) -MT varinfo2-varinfo2.o -MD -MP -MF $(DEPDIR)/varinfo2-varinfo2.Tpo -c -o varinfo2-varinfo2.o `test -f 'varinfo2.c' || echo '$(srcdir)/'`varinfo2.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo2-varinfo2.Tpo $(DEPDIR)/varinfo2-varinfo2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo2.c' object='varinfo2-varinfo2.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo2_CFLAGS) $(CFLAGS) -c -o varinfo2-varinfo2.o `test -f 'varinfo2.c' || echo '$(srcdir)/'`varinfo2.c
+
+varinfo2-varinfo2.obj: varinfo2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo2_CFLAGS) $(CFLAGS) -MT varinfo2-varinfo2.obj -MD -MP -MF $(DEPDIR)/varinfo2-varinfo2.Tpo -c -o varinfo2-varinfo2.obj `if test -f 'varinfo2.c'; then $(CYGPATH_W) 'varinfo2.c'; else $(CYGPATH_W) '$(srcdir)/varinfo2.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo2-varinfo2.Tpo $(DEPDIR)/varinfo2-varinfo2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo2.c' object='varinfo2-varinfo2.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo2_CFLAGS) $(CFLAGS) -c -o varinfo2-varinfo2.obj `if test -f 'varinfo2.c'; then $(CYGPATH_W) 'varinfo2.c'; else $(CYGPATH_W) '$(srcdir)/varinfo2.c'; fi`
+
+varinfo3-varinfo3.o: varinfo3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo3_CFLAGS) $(CFLAGS) -MT varinfo3-varinfo3.o -MD -MP -MF $(DEPDIR)/varinfo3-varinfo3.Tpo -c -o varinfo3-varinfo3.o `test -f 'varinfo3.c' || echo '$(srcdir)/'`varinfo3.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo3-varinfo3.Tpo $(DEPDIR)/varinfo3-varinfo3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo3.c' object='varinfo3-varinfo3.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo3_CFLAGS) $(CFLAGS) -c -o varinfo3-varinfo3.o `test -f 'varinfo3.c' || echo '$(srcdir)/'`varinfo3.c
+
+varinfo3-varinfo3.obj: varinfo3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo3_CFLAGS) $(CFLAGS) -MT varinfo3-varinfo3.obj -MD -MP -MF $(DEPDIR)/varinfo3-varinfo3.Tpo -c -o varinfo3-varinfo3.obj `if test -f 'varinfo3.c'; then $(CYGPATH_W) 'varinfo3.c'; else $(CYGPATH_W) '$(srcdir)/varinfo3.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo3-varinfo3.Tpo $(DEPDIR)/varinfo3-varinfo3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo3.c' object='varinfo3-varinfo3.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo3_CFLAGS) $(CFLAGS) -c -o varinfo3-varinfo3.obj `if test -f 'varinfo3.c'; then $(CYGPATH_W) 'varinfo3.c'; else $(CYGPATH_W) '$(srcdir)/varinfo3.c'; fi`
+
+varinfo4-varinfo4.o: varinfo4.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo4_CFLAGS) $(CFLAGS) -MT varinfo4-varinfo4.o -MD -MP -MF $(DEPDIR)/varinfo4-varinfo4.Tpo -c -o varinfo4-varinfo4.o `test -f 'varinfo4.c' || echo '$(srcdir)/'`varinfo4.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo4-varinfo4.Tpo $(DEPDIR)/varinfo4-varinfo4.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo4.c' object='varinfo4-varinfo4.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo4_CFLAGS) $(CFLAGS) -c -o varinfo4-varinfo4.o `test -f 'varinfo4.c' || echo '$(srcdir)/'`varinfo4.c
+
+varinfo4-varinfo4.obj: varinfo4.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo4_CFLAGS) $(CFLAGS) -MT varinfo4-varinfo4.obj -MD -MP -MF $(DEPDIR)/varinfo4-varinfo4.Tpo -c -o varinfo4-varinfo4.obj `if test -f 'varinfo4.c'; then $(CYGPATH_W) 'varinfo4.c'; else $(CYGPATH_W) '$(srcdir)/varinfo4.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo4-varinfo4.Tpo $(DEPDIR)/varinfo4-varinfo4.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo4.c' object='varinfo4-varinfo4.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo4_CFLAGS) $(CFLAGS) -c -o varinfo4-varinfo4.obj `if test -f 'varinfo4.c'; then $(CYGPATH_W) 'varinfo4.c'; else $(CYGPATH_W) '$(srcdir)/varinfo4.c'; fi`
+
+varinfo5-varinfo5.o: varinfo5.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo5_CFLAGS) $(CFLAGS) -MT varinfo5-varinfo5.o -MD -MP -MF $(DEPDIR)/varinfo5-varinfo5.Tpo -c -o varinfo5-varinfo5.o `test -f 'varinfo5.c' || echo '$(srcdir)/'`varinfo5.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo5-varinfo5.Tpo $(DEPDIR)/varinfo5-varinfo5.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo5.c' object='varinfo5-varinfo5.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo5_CFLAGS) $(CFLAGS) -c -o varinfo5-varinfo5.o `test -f 'varinfo5.c' || echo '$(srcdir)/'`varinfo5.c
+
+varinfo5-varinfo5.obj: varinfo5.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo5_CFLAGS) $(CFLAGS) -MT varinfo5-varinfo5.obj -MD -MP -MF $(DEPDIR)/varinfo5-varinfo5.Tpo -c -o varinfo5-varinfo5.obj `if test -f 'varinfo5.c'; then $(CYGPATH_W) 'varinfo5.c'; else $(CYGPATH_W) '$(srcdir)/varinfo5.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo5-varinfo5.Tpo $(DEPDIR)/varinfo5-varinfo5.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo5.c' object='varinfo5-varinfo5.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo5_CFLAGS) $(CFLAGS) -c -o varinfo5-varinfo5.obj `if test -f 'varinfo5.c'; then $(CYGPATH_W) 'varinfo5.c'; else $(CYGPATH_W) '$(srcdir)/varinfo5.c'; fi`
+
+varinfo5so_so-varinfo5so.o: varinfo5so.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo5so_so_CFLAGS) $(CFLAGS) -MT varinfo5so_so-varinfo5so.o -MD -MP -MF $(DEPDIR)/varinfo5so_so-varinfo5so.Tpo -c -o varinfo5so_so-varinfo5so.o `test -f 'varinfo5so.c' || echo '$(srcdir)/'`varinfo5so.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo5so_so-varinfo5so.Tpo $(DEPDIR)/varinfo5so_so-varinfo5so.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo5so.c' object='varinfo5so_so-varinfo5so.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo5so_so_CFLAGS) $(CFLAGS) -c -o varinfo5so_so-varinfo5so.o `test -f 'varinfo5so.c' || echo '$(srcdir)/'`varinfo5so.c
+
+varinfo5so_so-varinfo5so.obj: varinfo5so.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo5so_so_CFLAGS) $(CFLAGS) -MT varinfo5so_so-varinfo5so.obj -MD -MP -MF $(DEPDIR)/varinfo5so_so-varinfo5so.Tpo -c -o varinfo5so_so-varinfo5so.obj `if test -f 'varinfo5so.c'; then $(CYGPATH_W) 'varinfo5so.c'; else $(CYGPATH_W) '$(srcdir)/varinfo5so.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo5so_so-varinfo5so.Tpo $(DEPDIR)/varinfo5so_so-varinfo5so.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo5so.c' object='varinfo5so_so-varinfo5so.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo5so_so_CFLAGS) $(CFLAGS) -c -o varinfo5so_so-varinfo5so.obj `if test -f 'varinfo5so.c'; then $(CYGPATH_W) 'varinfo5so.c'; else $(CYGPATH_W) '$(srcdir)/varinfo5so.c'; fi`
+
+varinfo6-varinfo6.o: varinfo6.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo6_CFLAGS) $(CFLAGS) -MT varinfo6-varinfo6.o -MD -MP -MF $(DEPDIR)/varinfo6-varinfo6.Tpo -c -o varinfo6-varinfo6.o `test -f 'varinfo6.c' || echo '$(srcdir)/'`varinfo6.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo6-varinfo6.Tpo $(DEPDIR)/varinfo6-varinfo6.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo6.c' object='varinfo6-varinfo6.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo6_CFLAGS) $(CFLAGS) -c -o varinfo6-varinfo6.o `test -f 'varinfo6.c' || echo '$(srcdir)/'`varinfo6.c
+
+varinfo6-varinfo6.obj: varinfo6.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo6_CFLAGS) $(CFLAGS) -MT varinfo6-varinfo6.obj -MD -MP -MF $(DEPDIR)/varinfo6-varinfo6.Tpo -c -o varinfo6-varinfo6.obj `if test -f 'varinfo6.c'; then $(CYGPATH_W) 'varinfo6.c'; else $(CYGPATH_W) '$(srcdir)/varinfo6.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/varinfo6-varinfo6.Tpo $(DEPDIR)/varinfo6-varinfo6.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='varinfo6.c' object='varinfo6-varinfo6.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(varinfo6_CFLAGS) $(CFLAGS) -c -o varinfo6-varinfo6.obj `if test -f 'varinfo6.c'; then $(CYGPATH_W) 'varinfo6.c'; else $(CYGPATH_W) '$(srcdir)/varinfo6.c'; fi`
+
+vcpu_fbench-vcpu_fbench.o: vcpu_fbench.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vcpu_fbench_CFLAGS) $(CFLAGS) -MT vcpu_fbench-vcpu_fbench.o -MD -MP -MF $(DEPDIR)/vcpu_fbench-vcpu_fbench.Tpo -c -o vcpu_fbench-vcpu_fbench.o `test -f 'vcpu_fbench.c' || echo '$(srcdir)/'`vcpu_fbench.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vcpu_fbench-vcpu_fbench.Tpo $(DEPDIR)/vcpu_fbench-vcpu_fbench.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vcpu_fbench.c' object='vcpu_fbench-vcpu_fbench.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vcpu_fbench_CFLAGS) $(CFLAGS) -c -o vcpu_fbench-vcpu_fbench.o `test -f 'vcpu_fbench.c' || echo '$(srcdir)/'`vcpu_fbench.c
+
+vcpu_fbench-vcpu_fbench.obj: vcpu_fbench.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vcpu_fbench_CFLAGS) $(CFLAGS) -MT vcpu_fbench-vcpu_fbench.obj -MD -MP -MF $(DEPDIR)/vcpu_fbench-vcpu_fbench.Tpo -c -o vcpu_fbench-vcpu_fbench.obj `if test -f 'vcpu_fbench.c'; then $(CYGPATH_W) 'vcpu_fbench.c'; else $(CYGPATH_W) '$(srcdir)/vcpu_fbench.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vcpu_fbench-vcpu_fbench.Tpo $(DEPDIR)/vcpu_fbench-vcpu_fbench.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vcpu_fbench.c' object='vcpu_fbench-vcpu_fbench.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vcpu_fbench_CFLAGS) $(CFLAGS) -c -o vcpu_fbench-vcpu_fbench.obj `if test -f 'vcpu_fbench.c'; then $(CYGPATH_W) 'vcpu_fbench.c'; else $(CYGPATH_W) '$(srcdir)/vcpu_fbench.c'; fi`
+
+vcpu_fnfns-vcpu_fnfns.o: vcpu_fnfns.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vcpu_fnfns_CFLAGS) $(CFLAGS) -MT vcpu_fnfns-vcpu_fnfns.o -MD -MP -MF $(DEPDIR)/vcpu_fnfns-vcpu_fnfns.Tpo -c -o vcpu_fnfns-vcpu_fnfns.o `test -f 'vcpu_fnfns.c' || echo '$(srcdir)/'`vcpu_fnfns.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vcpu_fnfns-vcpu_fnfns.Tpo $(DEPDIR)/vcpu_fnfns-vcpu_fnfns.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vcpu_fnfns.c' object='vcpu_fnfns-vcpu_fnfns.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vcpu_fnfns_CFLAGS) $(CFLAGS) -c -o vcpu_fnfns-vcpu_fnfns.o `test -f 'vcpu_fnfns.c' || echo '$(srcdir)/'`vcpu_fnfns.c
+
+vcpu_fnfns-vcpu_fnfns.obj: vcpu_fnfns.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vcpu_fnfns_CFLAGS) $(CFLAGS) -MT vcpu_fnfns-vcpu_fnfns.obj -MD -MP -MF $(DEPDIR)/vcpu_fnfns-vcpu_fnfns.Tpo -c -o vcpu_fnfns-vcpu_fnfns.obj `if test -f 'vcpu_fnfns.c'; then $(CYGPATH_W) 'vcpu_fnfns.c'; else $(CYGPATH_W) '$(srcdir)/vcpu_fnfns.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vcpu_fnfns-vcpu_fnfns.Tpo $(DEPDIR)/vcpu_fnfns-vcpu_fnfns.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vcpu_fnfns.c' object='vcpu_fnfns-vcpu_fnfns.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vcpu_fnfns_CFLAGS) $(CFLAGS) -c -o vcpu_fnfns-vcpu_fnfns.obj `if test -f 'vcpu_fnfns.c'; then $(CYGPATH_W) 'vcpu_fnfns.c'; else $(CYGPATH_W) '$(srcdir)/vcpu_fnfns.c'; fi`
+
+wrap6-wrap6.o: wrap6.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(wrap6_CFLAGS) $(CFLAGS) -MT wrap6-wrap6.o -MD -MP -MF $(DEPDIR)/wrap6-wrap6.Tpo -c -o wrap6-wrap6.o `test -f 'wrap6.c' || echo '$(srcdir)/'`wrap6.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/wrap6-wrap6.Tpo $(DEPDIR)/wrap6-wrap6.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='wrap6.c' object='wrap6-wrap6.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(wrap6_CFLAGS) $(CFLAGS) -c -o wrap6-wrap6.o `test -f 'wrap6.c' || echo '$(srcdir)/'`wrap6.c
+
+wrap6-wrap6.obj: wrap6.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(wrap6_CFLAGS) $(CFLAGS) -MT wrap6-wrap6.obj -MD -MP -MF $(DEPDIR)/wrap6-wrap6.Tpo -c -o wrap6-wrap6.obj `if test -f 'wrap6.c'; then $(CYGPATH_W) 'wrap6.c'; else $(CYGPATH_W) '$(srcdir)/wrap6.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/wrap6-wrap6.Tpo $(DEPDIR)/wrap6-wrap6.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='wrap6.c' object='wrap6-wrap6.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(wrap6_CFLAGS) $(CFLAGS) -c -o wrap6-wrap6.obj `if test -f 'wrap6.c'; then $(CYGPATH_W) 'wrap6.c'; else $(CYGPATH_W) '$(srcdir)/wrap6.c'; fi`
+
+wrap7so_so-wrap7so.o: wrap7so.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(wrap7so_so_CFLAGS) $(CFLAGS) -MT wrap7so_so-wrap7so.o -MD -MP -MF $(DEPDIR)/wrap7so_so-wrap7so.Tpo -c -o wrap7so_so-wrap7so.o `test -f 'wrap7so.c' || echo '$(srcdir)/'`wrap7so.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/wrap7so_so-wrap7so.Tpo $(DEPDIR)/wrap7so_so-wrap7so.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='wrap7so.c' object='wrap7so_so-wrap7so.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(wrap7so_so_CFLAGS) $(CFLAGS) -c -o wrap7so_so-wrap7so.o `test -f 'wrap7so.c' || echo '$(srcdir)/'`wrap7so.c
+
+wrap7so_so-wrap7so.obj: wrap7so.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(wrap7so_so_CFLAGS) $(CFLAGS) -MT wrap7so_so-wrap7so.obj -MD -MP -MF $(DEPDIR)/wrap7so_so-wrap7so.Tpo -c -o wrap7so_so-wrap7so.obj `if test -f 'wrap7so.c'; then $(CYGPATH_W) 'wrap7so.c'; else $(CYGPATH_W) '$(srcdir)/wrap7so.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/wrap7so_so-wrap7so.Tpo $(DEPDIR)/wrap7so_so-wrap7so.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='wrap7so.c' object='wrap7so_so-wrap7so.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(wrap7so_so_CFLAGS) $(CFLAGS) -c -o wrap7so_so-wrap7so.obj `if test -f 'wrap7so.c'; then $(CYGPATH_W) 'wrap7so.c'; else $(CYGPATH_W) '$(srcdir)/wrap7so.c'; fi`
+
+.cpp.o:
+@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ $<
+
+.cpp.obj:
+@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+deep_templates-deep_templates.o: deep_templates.cpp
+@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(deep_templates_CXXFLAGS) $(CXXFLAGS) -MT deep_templates-deep_templates.o -MD -MP -MF $(DEPDIR)/deep_templates-deep_templates.Tpo -c -o deep_templates-deep_templates.o `test -f 'deep_templates.cpp' || echo '$(srcdir)/'`deep_templates.cpp
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/deep_templates-deep_templates.Tpo $(DEPDIR)/deep_templates-deep_templates.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='deep_templates.cpp' object='deep_templates-deep_templates.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(deep_templates_CXXFLAGS) $(CXXFLAGS) -c -o deep_templates-deep_templates.o `test -f 'deep_templates.cpp' || echo '$(srcdir)/'`deep_templates.cpp
+
+deep_templates-deep_templates.obj: deep_templates.cpp
+@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(deep_templates_CXXFLAGS) $(CXXFLAGS) -MT deep_templates-deep_templates.obj -MD -MP -MF $(DEPDIR)/deep_templates-deep_templates.Tpo -c -o deep_templates-deep_templates.obj `if test -f 'deep_templates.cpp'; then $(CYGPATH_W) 'deep_templates.cpp'; else $(CYGPATH_W) '$(srcdir)/deep_templates.cpp'; fi`
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/deep_templates-deep_templates.Tpo $(DEPDIR)/deep_templates-deep_templates.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='deep_templates.cpp' object='deep_templates-deep_templates.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(deep_templates_CXXFLAGS) $(CXXFLAGS) -c -o deep_templates-deep_templates.obj `if test -f 'deep_templates.cpp'; then $(CYGPATH_W) 'deep_templates.cpp'; else $(CYGPATH_W) '$(srcdir)/deep_templates.cpp'; fi`
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-recursive
+all-am: Makefile $(SCRIPTS) $(HEADERS)
+installdirs: installdirs-recursive
+installdirs-am:
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) check-am \
+ ctags-recursive install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags \
+ ctags-recursive distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ installdirs-am maintainer-clean maintainer-clean-generic \
+ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \
+ ps ps-am tags tags-recursive uninstall uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/accounting.c b/main/memcheck/tests/accounting.c
new file mode 100644
index 0000000..1654bb0
--- /dev/null
+++ b/main/memcheck/tests/accounting.c
@@ -0,0 +1,25 @@
+/*
+ * test case for valgrind realloc() bug
+ */
+
+#include <stdlib.h>
+#include <assert.h>
+
+int
+main(void)
+{
+ void *p;
+ void *r;
+
+ p = malloc(1);
+ assert(p != NULL);
+
+ r = realloc(p, -1);
+ assert(r == NULL);
+
+ free(p);
+
+ return 0;
+}
+
+
diff --git a/main/memcheck/tests/accounting.stderr.exp b/main/memcheck/tests/accounting.stderr.exp
new file mode 100644
index 0000000..fb31e6d
--- /dev/null
+++ b/main/memcheck/tests/accounting.stderr.exp
@@ -0,0 +1,11 @@
+
+Warning: silly arg (-1) to realloc()
+
+HEAP SUMMARY:
+ in use at exit: 0 bytes in 0 blocks
+ total heap usage: 1 allocs, 1 frees, 1 bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/accounting.vgtest b/main/memcheck/tests/accounting.vgtest
new file mode 100644
index 0000000..7918b5c
--- /dev/null
+++ b/main/memcheck/tests/accounting.vgtest
@@ -0,0 +1 @@
+prog: accounting
diff --git a/main/memcheck/tests/amd64-linux/Makefile.in b/main/memcheck/tests/amd64-linux/Makefile.in
new file mode 100644
index 0000000..e153da6
--- /dev/null
+++ b/main/memcheck/tests/amd64-linux/Makefile.in
@@ -0,0 +1,723 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = defcfaexpr$(EXEEXT) int3-amd64$(EXEEXT)
+subdir = memcheck/tests/amd64-linux
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+am_defcfaexpr_OBJECTS = defcfaexpr.$(OBJEXT)
+defcfaexpr_OBJECTS = $(am_defcfaexpr_OBJECTS)
+defcfaexpr_LDADD = $(LDADD)
+int3_amd64_SOURCES = int3-amd64.c
+int3_amd64_OBJECTS = int3-amd64.$(OBJEXT)
+int3_amd64_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+CPPASCOMPILE = $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CCASFLAGS) $(CCASFLAGS)
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(defcfaexpr_SOURCES) int3-amd64.c
+DIST_SOURCES = $(defcfaexpr_SOURCES) int3-amd64.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+ filter_stderr filter_defcfaexpr
+
+EXTRA_DIST = \
+ defcfaexpr.vgtest defcfaexpr.stderr.exp \
+ int3-amd64.vgtest int3-amd64.stderr.exp int3-amd64.stdout.exp
+
+defcfaexpr_SOURCES = defcfaexpr.S
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .S .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/amd64-linux/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/amd64-linux/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+defcfaexpr$(EXEEXT): $(defcfaexpr_OBJECTS) $(defcfaexpr_DEPENDENCIES)
+ @rm -f defcfaexpr$(EXEEXT)
+ $(LINK) $(defcfaexpr_OBJECTS) $(defcfaexpr_LDADD) $(LIBS)
+int3-amd64$(EXEEXT): $(int3_amd64_OBJECTS) $(int3_amd64_DEPENDENCIES)
+ @rm -f int3-amd64$(EXEEXT)
+ $(LINK) $(int3_amd64_OBJECTS) $(int3_amd64_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/defcfaexpr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/int3-amd64.Po@am__quote@
+
+.S.o:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ $<
+
+.S.obj:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/amd64/int3-amd64.stderr.exp b/main/memcheck/tests/amd64-linux/int3-amd64.stderr.exp
similarity index 100%
rename from main/memcheck/tests/amd64/int3-amd64.stderr.exp
rename to main/memcheck/tests/amd64-linux/int3-amd64.stderr.exp
diff --git a/main/memcheck/tests/amd64/Makefile.in b/main/memcheck/tests/amd64/Makefile.in
new file mode 100644
index 0000000..1270ca6
--- /dev/null
+++ b/main/memcheck/tests/amd64/Makefile.in
@@ -0,0 +1,774 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = bt_everything$(EXEEXT) bug132146$(EXEEXT) \
+ bug279698$(EXEEXT) fxsave-amd64$(EXEEXT) more_x87_fp$(EXEEXT) \
+ sse_memory$(EXEEXT) xor-undef-amd64$(EXEEXT)
+subdir = memcheck/tests/amd64
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+bt_everything_SOURCES = bt_everything.c
+bt_everything_OBJECTS = bt_everything.$(OBJEXT)
+bt_everything_LDADD = $(LDADD)
+bug132146_SOURCES = bug132146.c
+bug132146_OBJECTS = bug132146.$(OBJEXT)
+bug132146_LDADD = $(LDADD)
+bug279698_SOURCES = bug279698.c
+bug279698_OBJECTS = bug279698.$(OBJEXT)
+bug279698_LDADD = $(LDADD)
+fxsave_amd64_SOURCES = fxsave-amd64.c
+fxsave_amd64_OBJECTS = fxsave-amd64.$(OBJEXT)
+fxsave_amd64_LDADD = $(LDADD)
+more_x87_fp_SOURCES = more_x87_fp.c
+more_x87_fp_OBJECTS = more_x87_fp-more_x87_fp.$(OBJEXT)
+more_x87_fp_DEPENDENCIES =
+more_x87_fp_LINK = $(CCLD) $(more_x87_fp_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+sse_memory_SOURCES = sse_memory.c
+sse_memory_OBJECTS = sse_memory.$(OBJEXT)
+sse_memory_LDADD = $(LDADD)
+xor_undef_amd64_SOURCES = xor-undef-amd64.c
+xor_undef_amd64_OBJECTS = xor-undef-amd64.$(OBJEXT)
+xor_undef_amd64_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = bt_everything.c bug132146.c bug279698.c fxsave-amd64.c \
+ more_x87_fp.c sse_memory.c xor-undef-amd64.c
+DIST_SOURCES = bt_everything.c bug132146.c bug279698.c fxsave-amd64.c \
+ more_x87_fp.c sse_memory.c xor-undef-amd64.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+INSN_TESTS = insn_basic insn_mmx insn_sse insn_sse2 insn_fpu
+EXTRA_DIST = \
+ $(addsuffix .stderr.exp,$(INSN_TESTS)) \
+ $(addsuffix .stdout.exp,$(INSN_TESTS)) \
+ $(addsuffix .vgtest,$(INSN_TESTS)) \
+ bt_everything.stderr.exp bt_everything.stdout.exp \
+ bt_everything.vgtest \
+ bug132146.vgtest bug132146.stderr.exp bug132146.stdout.exp \
+ bug279698.vgtest bug279698.stderr.exp bug279698.stdout.exp \
+ fxsave-amd64.vgtest fxsave-amd64.stdout.exp fxsave-amd64.stderr.exp \
+ more_x87_fp.stderr.exp more_x87_fp.stdout.exp more_x87_fp.vgtest \
+ sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest \
+ xor-undef-amd64.stderr.exp xor-undef-amd64.stdout.exp \
+ xor-undef-amd64.vgtest
+
+more_x87_fp_CFLAGS = $(AM_CFLAGS) -O -ffast-math -mfpmath=387 \
+ -mfancy-math-387
+
+more_x87_fp_LDADD = -lm
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/amd64/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/amd64/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+bt_everything$(EXEEXT): $(bt_everything_OBJECTS) $(bt_everything_DEPENDENCIES)
+ @rm -f bt_everything$(EXEEXT)
+ $(LINK) $(bt_everything_OBJECTS) $(bt_everything_LDADD) $(LIBS)
+bug132146$(EXEEXT): $(bug132146_OBJECTS) $(bug132146_DEPENDENCIES)
+ @rm -f bug132146$(EXEEXT)
+ $(LINK) $(bug132146_OBJECTS) $(bug132146_LDADD) $(LIBS)
+bug279698$(EXEEXT): $(bug279698_OBJECTS) $(bug279698_DEPENDENCIES)
+ @rm -f bug279698$(EXEEXT)
+ $(LINK) $(bug279698_OBJECTS) $(bug279698_LDADD) $(LIBS)
+fxsave-amd64$(EXEEXT): $(fxsave_amd64_OBJECTS) $(fxsave_amd64_DEPENDENCIES)
+ @rm -f fxsave-amd64$(EXEEXT)
+ $(LINK) $(fxsave_amd64_OBJECTS) $(fxsave_amd64_LDADD) $(LIBS)
+more_x87_fp$(EXEEXT): $(more_x87_fp_OBJECTS) $(more_x87_fp_DEPENDENCIES)
+ @rm -f more_x87_fp$(EXEEXT)
+ $(more_x87_fp_LINK) $(more_x87_fp_OBJECTS) $(more_x87_fp_LDADD) $(LIBS)
+sse_memory$(EXEEXT): $(sse_memory_OBJECTS) $(sse_memory_DEPENDENCIES)
+ @rm -f sse_memory$(EXEEXT)
+ $(LINK) $(sse_memory_OBJECTS) $(sse_memory_LDADD) $(LIBS)
+xor-undef-amd64$(EXEEXT): $(xor_undef_amd64_OBJECTS) $(xor_undef_amd64_DEPENDENCIES)
+ @rm -f xor-undef-amd64$(EXEEXT)
+ $(LINK) $(xor_undef_amd64_OBJECTS) $(xor_undef_amd64_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bt_everything.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132146.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug279698.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxsave-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/more_x87_fp-more_x87_fp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sse_memory.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xor-undef-amd64.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+more_x87_fp-more_x87_fp.o: more_x87_fp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(more_x87_fp_CFLAGS) $(CFLAGS) -MT more_x87_fp-more_x87_fp.o -MD -MP -MF $(DEPDIR)/more_x87_fp-more_x87_fp.Tpo -c -o more_x87_fp-more_x87_fp.o `test -f 'more_x87_fp.c' || echo '$(srcdir)/'`more_x87_fp.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/more_x87_fp-more_x87_fp.Tpo $(DEPDIR)/more_x87_fp-more_x87_fp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='more_x87_fp.c' object='more_x87_fp-more_x87_fp.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(more_x87_fp_CFLAGS) $(CFLAGS) -c -o more_x87_fp-more_x87_fp.o `test -f 'more_x87_fp.c' || echo '$(srcdir)/'`more_x87_fp.c
+
+more_x87_fp-more_x87_fp.obj: more_x87_fp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(more_x87_fp_CFLAGS) $(CFLAGS) -MT more_x87_fp-more_x87_fp.obj -MD -MP -MF $(DEPDIR)/more_x87_fp-more_x87_fp.Tpo -c -o more_x87_fp-more_x87_fp.obj `if test -f 'more_x87_fp.c'; then $(CYGPATH_W) 'more_x87_fp.c'; else $(CYGPATH_W) '$(srcdir)/more_x87_fp.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/more_x87_fp-more_x87_fp.Tpo $(DEPDIR)/more_x87_fp-more_x87_fp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='more_x87_fp.c' object='more_x87_fp-more_x87_fp.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(more_x87_fp_CFLAGS) $(CFLAGS) -c -o more_x87_fp-more_x87_fp.obj `if test -f 'more_x87_fp.c'; then $(CYGPATH_W) 'more_x87_fp.c'; else $(CYGPATH_W) '$(srcdir)/more_x87_fp.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/amd64/defcfaexpr.S b/main/memcheck/tests/amd64/defcfaexpr.S
deleted file mode 100644
index e69de29..0000000
--- a/main/memcheck/tests/amd64/defcfaexpr.S
+++ /dev/null
diff --git a/main/memcheck/tests/amd64/defcfaexpr.stderr.exp b/main/memcheck/tests/amd64/defcfaexpr.stderr.exp
deleted file mode 100644
index e69de29..0000000
--- a/main/memcheck/tests/amd64/defcfaexpr.stderr.exp
+++ /dev/null
diff --git a/main/memcheck/tests/amd64/defcfaexpr.vgtest b/main/memcheck/tests/amd64/defcfaexpr.vgtest
deleted file mode 100644
index e69de29..0000000
--- a/main/memcheck/tests/amd64/defcfaexpr.vgtest
+++ /dev/null
diff --git a/main/memcheck/tests/amd64/filter_defcfaexpr b/main/memcheck/tests/amd64/filter_defcfaexpr
deleted file mode 100755
index e69de29..0000000
--- a/main/memcheck/tests/amd64/filter_defcfaexpr
+++ /dev/null
diff --git a/main/memcheck/tests/amd64/int3-amd64.c b/main/memcheck/tests/amd64/int3-amd64.c
deleted file mode 100644
index e69de29..0000000
--- a/main/memcheck/tests/amd64/int3-amd64.c
+++ /dev/null
diff --git a/main/memcheck/tests/amd64/int3-amd64.vgtest b/main/memcheck/tests/amd64/int3-amd64.vgtest
deleted file mode 100644
index e69de29..0000000
--- a/main/memcheck/tests/amd64/int3-amd64.vgtest
+++ /dev/null
diff --git a/main/memcheck/tests/atomic_incs.c b/main/memcheck/tests/atomic_incs.c
index 80cf810..ac1e775 100644
--- a/main/memcheck/tests/atomic_incs.c
+++ b/main/memcheck/tests/atomic_incs.c
@@ -110,6 +110,48 @@
: "+m" (*p), "+m" (dummy)
: "d" (n)
: "cc", "memory", "0", "1");
+#elif defined(VGA_mips32)
+#if defined (_MIPSEL)
+ unsigned int block[3]
+ = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
+ do {
+ __asm__ __volatile__(
+ "move $t0, %0" "\n\t"
+ "lw $t1, 0($t0)" "\n\t" // p
+ "lw $t2, 4($t0)" "\n\t" // n
+ "ll $t3, 0($t1)" "\n\t"
+ "addu $t3, $t3, $t2" "\n\t"
+ "andi $t3, $t3, 0xFF" "\n\t"
+ "sc $t3, 0($t1)" "\n\t"
+ "sw $t3, 8($t0)" "\n\t"
+ : /*out*/
+ : /*in*/ "r"(&block[0])
+ : /*trash*/ "memory", "cc", "t0", "t1", "t2", "t3"
+ );
+ } while (block[2] != 1);
+#elif defined (_MIPSEB)
+ unsigned int block[3]
+ = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
+ do {
+ __asm__ __volatile__(
+ "move $t0, %0" "\n\t"
+ "lw $t1, 0($t0)" "\n\t" // p
+ "lw $t2, 4($t0)" "\n\t" // n
+ "li $t4, 0x000000FF" "\n\t"
+ "ll $t3, 0($t1)" "\n\t"
+ "addu $t3, $t3, $t2" "\n\t"
+ "and $t3, $t3, $t4" "\n\t"
+ "wsbh $t4, $t3" "\n\t"
+ "rotr $t4, $t4, 16" "\n\t"
+ "or $t3, $t4, $t3" "\n\t"
+ "sc $t3, 0($t1)" "\n\t"
+ "sw $t3, 8($t0)" "\n\t"
+ : /*out*/
+ : /*in*/ "r"(&block[0])
+ : /*trash*/ "memory", "cc", "t0", "t1", "t2", "t3", "t4"
+ );
+ } while (block[2] != 1);
+#endif
#else
# error "Unsupported arch"
#endif
@@ -203,6 +245,43 @@
: "+m" (*p), "+m" (dummy)
: "d" (n)
: "cc", "memory", "0", "1");
+#elif defined(VGA_mips32)
+#if defined (_MIPSEL)
+ unsigned int block[3]
+ = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
+ do {
+ __asm__ __volatile__(
+ "move $t0, %0" "\n\t"
+ "lw $t1, 0($t0)" "\n\t" // p
+ "lw $t2, 4($t0)" "\n\t" // n
+ "ll $t3, 0($t1)" "\n\t"
+ "addu $t3, $t3, $t2" "\n\t"
+ "andi $t3, $t3, 0xFFFF" "\n\t"
+ "sc $t3, 0($t1)" "\n\t"
+ "sw $t3, 8($t0)" "\n\t"
+ : /*out*/
+ : /*in*/ "r"(&block[0])
+ : /*trash*/ "memory", "cc", "t0", "t1", "t2", "t3"
+ );
+ } while (block[2] != 1);
+#elif defined (_MIPSEB)
+ unsigned int block[3]
+ = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
+ do {
+ __asm__ __volatile__(
+ "move $t0, %0" "\n\t"
+ "lw $t1, 0($t0)" "\n\t" // p
+ "li $t2, 32694" "\n\t" // n
+ "li $t3, 0x1" "\n\t"
+ "sll $t2, $t2, 16" "\n\t"
+ "sw $t2, 0($t1)" "\n\t"
+ "sw $t3, 8($t0)" "\n\t"
+ : /*out*/
+ : /*in*/ "r"(&block[0])
+ : /*trash*/ "memory", "cc", "t0", "t1", "t2", "t3"
+ );
+ } while (block[2] != 1);
+#endif
#else
# error "Unsupported arch"
#endif
@@ -289,6 +368,23 @@
: "+m" (*p)
: "d" (n)
: "cc", "memory", "0", "1");
+#elif defined(VGA_mips32)
+ unsigned int block[3]
+ = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
+ do {
+ __asm__ __volatile__(
+ "move $t0, %0" "\n\t"
+ "lw $t1, 0($t0)" "\n\t" // p
+ "lw $t2, 4($t0)" "\n\t" // n
+ "ll $t3, 0($t1)" "\n\t"
+ "addu $t3, $t3, $t2" "\n\t"
+ "sc $t3, 0($t1)" "\n\t"
+ "sw $t3, 8($t0)" "\n\t"
+ : /*out*/
+ : /*in*/ "r"(&block[0])
+ : /*trash*/ "memory", "cc", "t0", "t1", "t2", "t3"
+ );
+ } while (block[2] != 1);
#else
# error "Unsupported arch"
#endif
@@ -296,7 +392,7 @@
__attribute__((noinline)) void atomic_add_64bit ( long long int* p, int n )
{
-#if defined(VGA_x86) || defined(VGA_ppc32)
+#if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_mips32)
/* do nothing; is not supported */
#elif defined(VGA_amd64)
// this is a bit subtle. It relies on the fact that, on a 64-bit platform,
diff --git a/main/memcheck/tests/badfree3.stderr.exp b/main/memcheck/tests/badfree3.stderr.exp
new file mode 100644
index 0000000..f276c35
--- /dev/null
+++ b/main/memcheck/tests/badfree3.stderr.exp
@@ -0,0 +1,10 @@
+Invalid free() / delete / delete[] / realloc()
+ at 0x........: free (coregrind/vg_replace_malloc.c:...)
+ by 0x........: main (memcheck/tests/badfree.c:12)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Invalid free() / delete / delete[] / realloc()
+ at 0x........: free (coregrind/vg_replace_malloc.c:...)
+ by 0x........: main (memcheck/tests/badfree.c:15)
+ Address 0x........ is on thread 1's stack
+
diff --git a/main/memcheck/tests/badfree3.vgtest b/main/memcheck/tests/badfree3.vgtest
new file mode 100644
index 0000000..f51a291
--- /dev/null
+++ b/main/memcheck/tests/badfree3.vgtest
@@ -0,0 +1,3 @@
+prog: badfree
+vgopts: -q --fullpath-after=${PWD}/
+stderr_filter_args: badfree.c
diff --git a/main/memcheck/tests/badjump.stderr.exp-kfail b/main/memcheck/tests/badjump.stderr.exp-kfail
new file mode 100644
index 0000000..1cecc0a
--- /dev/null
+++ b/main/memcheck/tests/badjump.stderr.exp-kfail
@@ -0,0 +1,23 @@
+
+Jump to the invalid address stated on the next line
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+
+Process terminating with default action of signal 11 (SIGSEGV)
+ Access not within mapped region at address 0x........
+ ...
+ If you believe this happened as a result of a stack
+ overflow in your program's main thread (unlikely but
+ possible), you can try to increase the size of the
+ main thread stack using the --main-stacksize= flag.
+ The main thread stack size used in this run was ....
+
+HEAP SUMMARY:
+ in use at exit: ... bytes in ... blocks
+ total heap usage: ... allocs, ... frees, ... bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/badjump2.c b/main/memcheck/tests/badjump2.c
index 47a6829..ad7329f 100644
--- a/main/memcheck/tests/badjump2.c
+++ b/main/memcheck/tests/badjump2.c
@@ -13,7 +13,7 @@
static
void SIGSEGV_handler(int signum)
{
- __builtin_longjmp(myjmpbuf, 1);
+ longjmp(myjmpbuf, 1);
}
int main(void)
@@ -33,7 +33,7 @@
res = sigaction( SIGSEGV, &sigsegv_new, &sigsegv_saved );
assert(res == 0);
- if (__builtin_setjmp(myjmpbuf) == 0) {
+ if (setjmp(myjmpbuf) == 0) {
// Jump to zero; will cause seg fault
#if defined(__powerpc64__)
unsigned long int fn[3];
diff --git a/main/memcheck/tests/badjump2.stderr.exp-kfail b/main/memcheck/tests/badjump2.stderr.exp-kfail
new file mode 100644
index 0000000..35ce6f0
--- /dev/null
+++ b/main/memcheck/tests/badjump2.stderr.exp-kfail
@@ -0,0 +1,5 @@
+Jump to the invalid address stated on the next line
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Signal caught, as expected
diff --git a/main/memcheck/tests/badrw.stderr.exp-s390x-mvc b/main/memcheck/tests/badrw.stderr.exp-s390x-mvc
new file mode 100644
index 0000000..8189364
--- /dev/null
+++ b/main/memcheck/tests/badrw.stderr.exp-s390x-mvc
@@ -0,0 +1,36 @@
+Invalid read of size 1
+ at 0x........: main (badrw.c:19)
+ Address 0x........ is 4 bytes before a block of size 10 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (badrw.c:5)
+
+Invalid write of size 1
+ at 0x........: main (badrw.c:20)
+ Address 0x........ is 4 bytes before a block of size 10 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (badrw.c:5)
+
+Invalid read of size 1
+ at 0x........: main (badrw.c:22)
+ Address 0x........ is 4 bytes before a block of size 10 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (badrw.c:5)
+
+Invalid write of size 1
+ at 0x........: main (badrw.c:23)
+ Address 0x........ is 4 bytes before a block of size 10 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (badrw.c:5)
+
+Invalid read of size 1
+ at 0x........: main (badrw.c:25)
+ Address 0x........ is 1 bytes before a block of size 10 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (badrw.c:5)
+
+Invalid write of size 1
+ at 0x........: main (badrw.c:26)
+ Address 0x........ is 1 bytes before a block of size 10 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (badrw.c:5)
+
diff --git a/main/memcheck/tests/buflen_check.stderr.exp-kfail b/main/memcheck/tests/buflen_check.stderr.exp-kfail
new file mode 100644
index 0000000..24d1f21
--- /dev/null
+++ b/main/memcheck/tests/buflen_check.stderr.exp-kfail
@@ -0,0 +1,10 @@
+Syscall param socketcall.getsockname(name) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param socketcall.getsockname(namelen_in) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+getsockname(1) failed
+getsockname(2) failed
diff --git a/main/memcheck/tests/bug287260.c b/main/memcheck/tests/bug287260.c
new file mode 100644
index 0000000..79574f8
--- /dev/null
+++ b/main/memcheck/tests/bug287260.c
@@ -0,0 +1,16 @@
+#include <stdio.h>
+
+typedef struct {
+ unsigned int stuff : 21;
+ signed int rotation : 10;
+} Oink;
+
+int
+main (int argc, char **argv)
+{
+ volatile Oink r;
+
+ r.rotation = 45;
+ fprintf (stderr, "%d\n", r.rotation);
+ return 0;
+}
diff --git a/main/memcheck/tests/bug287260.stderr.exp b/main/memcheck/tests/bug287260.stderr.exp
new file mode 100644
index 0000000..a9d58bf
--- /dev/null
+++ b/main/memcheck/tests/bug287260.stderr.exp
@@ -0,0 +1,11 @@
+
+45
+
+HEAP SUMMARY:
+ in use at exit: 0 bytes in 0 blocks
+ total heap usage: 0 allocs, 0 frees, 0 bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/bug287260.vgtest b/main/memcheck/tests/bug287260.vgtest
new file mode 100644
index 0000000..928ef80
--- /dev/null
+++ b/main/memcheck/tests/bug287260.vgtest
@@ -0,0 +1 @@
+prog: bug287260
diff --git a/main/memcheck/tests/clireq_nofill.c b/main/memcheck/tests/clireq_nofill.c
new file mode 100644
index 0000000..6d2c45c
--- /dev/null
+++ b/main/memcheck/tests/clireq_nofill.c
@@ -0,0 +1,42 @@
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "valgrind.h"
+#include "../memcheck.h"
+
+struct super { int x; };
+static struct super superblock = { 12345 };
+
+/* run with `valgrind -q --malloc-fill=0xaf --free-fill=0xdb` */
+int main(int argc, char **argv)
+{
+ unsigned char *s;
+ VALGRIND_CREATE_MEMPOOL(&superblock, /*rzB=*/0, /*is_zeroed=*/0);
+ s = malloc(40);
+ assert(s);
+ assert(*s == 0xaf);
+ *s = 0x05;
+ VALGRIND_MEMPOOL_ALLOC(&superblock, s, 40);
+ printf("*s=%#hhx after MEMPOOL_ALLOC\n", *s);
+ VALGRIND_MEMPOOL_FREE(&superblock, s);
+ printf("*s=%#hhx after MEMPOOL_FREE\n", *s);
+ VALGRIND_MEMPOOL_ALLOC(&superblock, s, 40);
+ printf("*s=%#hhx after second MEMPOOL_ALLOC\n", *s);
+ free(s);
+ VALGRIND_DESTROY_MEMPOOL(&superblock);
+
+ s = malloc(40);
+ assert(s);
+ assert(*s == 0xaf);
+ *s = 0x05;
+ VALGRIND_MALLOCLIKE_BLOCK(s, 40, 0/*rzB*/, 0/*is_zeroed*/);
+ printf("*s=%#hhx after MALLOCLIKE_BLOCK\n", *s);
+ VALGRIND_FREELIKE_BLOCK(s, 0/*rzB*/);
+ printf("*s=%#hhx after FREELIKE_BLOCK\n", *s);
+ VALGRIND_MALLOCLIKE_BLOCK(s, 40, 0/*rzB*/, 0/*is_zeroed*/);
+ printf("*s=%#hhx after second MALLOCLIKE_BLOCK\n", *s);
+
+ return 0;
+}
+
diff --git a/main/memcheck/tests/clireq_nofill.stderr.exp b/main/memcheck/tests/clireq_nofill.stderr.exp
new file mode 100644
index 0000000..42a9711
--- /dev/null
+++ b/main/memcheck/tests/clireq_nofill.stderr.exp
@@ -0,0 +1,12 @@
+Invalid read of size 1
+ at 0x........: main (clireq_nofill.c:23)
+ Address 0x........ is 0 bytes inside a recently re-allocated block of size 40 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (clireq_nofill.c:16)
+
+Invalid read of size 1
+ at 0x........: main (clireq_nofill.c:36)
+ Address 0x........ is 0 bytes inside a recently re-allocated block of size 40 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (clireq_nofill.c:29)
+
diff --git a/main/memcheck/tests/clireq_nofill.stdout.exp b/main/memcheck/tests/clireq_nofill.stdout.exp
new file mode 100644
index 0000000..731d8aa
--- /dev/null
+++ b/main/memcheck/tests/clireq_nofill.stdout.exp
@@ -0,0 +1,6 @@
+*s=0x5 after MEMPOOL_ALLOC
+*s=0x5 after MEMPOOL_FREE
+*s=0x5 after second MEMPOOL_ALLOC
+*s=0x5 after MALLOCLIKE_BLOCK
+*s=0x5 after FREELIKE_BLOCK
+*s=0x5 after second MALLOCLIKE_BLOCK
diff --git a/main/memcheck/tests/clireq_nofill.vgtest b/main/memcheck/tests/clireq_nofill.vgtest
new file mode 100644
index 0000000..f834bf9
--- /dev/null
+++ b/main/memcheck/tests/clireq_nofill.vgtest
@@ -0,0 +1,2 @@
+prog: clireq_nofill
+vgopts: -q --undef-value-errors=no --malloc-fill=0xaf --free-fill=0xdb
diff --git a/main/memcheck/tests/clo_redzone.c b/main/memcheck/tests/clo_redzone.c
new file mode 100644
index 0000000..5733ffa
--- /dev/null
+++ b/main/memcheck/tests/clo_redzone.c
@@ -0,0 +1,17 @@
+#include <stdio.h>
+#include <stdlib.h>
+int main()
+{
+ __attribute__((unused)) char *p = malloc (1);
+ char *b1 = malloc (128);
+ char *b2 = malloc (128);
+ fprintf (stderr, "b1 %p b2 %p\n", b1, b2);
+
+ // Try to land in b2 from b1, causing no error
+ // with the default redzone-size, but having
+ // an error with a bigger redzone-size.
+ // We need to choose a value which lands in b2
+ // on 32 bits and 64 bits.
+ b1[127 + 70] = 'a';
+ return 0;
+}
diff --git a/main/memcheck/tests/clo_redzone_128.stderr.exp b/main/memcheck/tests/clo_redzone_128.stderr.exp
new file mode 100644
index 0000000..08b360d
--- /dev/null
+++ b/main/memcheck/tests/clo_redzone_128.stderr.exp
@@ -0,0 +1,7 @@
+b1 0x........ b2 0x........
+Invalid write of size 1
+ ...
+ Address 0x........ is 69 bytes after a block of size 128 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ ...
+
diff --git a/main/memcheck/tests/clo_redzone_128.vgtest b/main/memcheck/tests/clo_redzone_128.vgtest
new file mode 100644
index 0000000..6b7b2a6
--- /dev/null
+++ b/main/memcheck/tests/clo_redzone_128.vgtest
@@ -0,0 +1,2 @@
+vgopts: --leak-check=no -q --redzone-size=128
+prog: clo_redzone
diff --git a/main/memcheck/tests/clo_redzone_default.stderr.exp b/main/memcheck/tests/clo_redzone_default.stderr.exp
new file mode 100644
index 0000000..f86f233
--- /dev/null
+++ b/main/memcheck/tests/clo_redzone_default.stderr.exp
@@ -0,0 +1 @@
+b1 0x........ b2 0x........
diff --git a/main/memcheck/tests/clo_redzone_default.vgtest b/main/memcheck/tests/clo_redzone_default.vgtest
new file mode 100644
index 0000000..fc63752
--- /dev/null
+++ b/main/memcheck/tests/clo_redzone_default.vgtest
@@ -0,0 +1,2 @@
+vgopts: --leak-check=no -q
+prog: clo_redzone
diff --git a/main/memcheck/tests/custom_alloc.c b/main/memcheck/tests/custom_alloc.c
index 2f91c6f..56cf94b 100644
--- a/main/memcheck/tests/custom_alloc.c
+++ b/main/memcheck/tests/custom_alloc.c
@@ -54,6 +54,44 @@
VALGRIND_FREELIKE_BLOCK( p, RZ );
}
+static void checkredzone(void)
+{
+ /* check that accessing the redzone of a MALLOCLIKE block
+ is detected when the superblock was not marked as no access. */
+ char superblock[1 + RZ + 20 + RZ + 1];
+ char *p = 1 + RZ + superblock;
+ assert(RZ > 0);
+
+ // Indicate we have allocated p from our superblock:
+ VALGRIND_MALLOCLIKE_BLOCK( p, 20, RZ, /*is_zeroed*/1 );
+ p[0] = 0;
+ p[-1] = p[0]; // error expected
+ p[-RZ] = p[0]; // error expected
+ p[-RZ-1] = p[0]; // no error expected
+
+ p[19] = 0;
+ p[19 + 1] = p[0]; // error expected
+ p[19 + RZ] = p[0]; // error expected
+ p[19 + RZ + 1] = p[0]; // no error expected
+
+ VALGRIND_FREELIKE_BLOCK( p, RZ );
+
+ // Now, indicate we have re-allocated p from our superblock
+ // but with only a size 10.
+ VALGRIND_MALLOCLIKE_BLOCK( p, 10, RZ, /*is_zeroed*/1 );
+ p[0] = 0;
+ p[-1] = p[0]; // error expected
+ p[-RZ] = p[0]; // error expected
+ p[-RZ-1] = p[0]; // no error expected
+
+ p[9] = 0;
+ p[9 + 1] = p[0]; // error expected
+ p[9 + RZ] = p[0]; // error expected
+ p[9 + RZ + 1] = p[0]; // no error expected
+
+ VALGRIND_FREELIKE_BLOCK( p, RZ );
+
+}
@@ -104,16 +142,14 @@
make_leak();
x = array[0]; // use after free (ok without MALLOCLIKE/MAKE_MEM_NOACCESS)
- // (nb: initialised because is_zeroed==1 above)
- // unfortunately not identified as being in a free'd
- // block because the freeing of the block and shadow
- // chunk isn't postponed.
// Bug 137073: passing 0 to MALLOCLIKE_BLOCK was causing an assertion
// failure. Test for this (and likewise for FREELIKE_BLOCK).
VALGRIND_MALLOCLIKE_BLOCK(0,0,0,0);
VALGRIND_FREELIKE_BLOCK(0,0);
-
+
+ checkredzone();
+
return x;
// leak from make_leak()
diff --git a/main/memcheck/tests/custom_alloc.stderr.exp b/main/memcheck/tests/custom_alloc.stderr.exp
index bb55f8c..fcff3ec 100644
--- a/main/memcheck/tests/custom_alloc.stderr.exp
+++ b/main/memcheck/tests/custom_alloc.stderr.exp
@@ -1,45 +1,108 @@
Invalid write of size 4
- at 0x........: main (custom_alloc.c:79)
+ at 0x........: main (custom_alloc.c:117)
Address 0x........ is 0 bytes after a block of size 40 alloc'd
at 0x........: custom_alloc (custom_alloc.c:47)
- by 0x........: main (custom_alloc.c:76)
+ by 0x........: main (custom_alloc.c:114)
Invalid write of size 4
- at 0x........: main (custom_alloc.c:83)
+ at 0x........: main (custom_alloc.c:121)
Address 0x........ is 0 bytes after a block of size 20 alloc'd
at 0x........: custom_alloc (custom_alloc.c:47)
- by 0x........: main (custom_alloc.c:76)
+ by 0x........: main (custom_alloc.c:114)
Conditional jump or move depends on uninitialised value(s)
- at 0x........: main (custom_alloc.c:90)
+ at 0x........: main (custom_alloc.c:128)
Invalid write of size 4
- at 0x........: main (custom_alloc.c:93)
+ at 0x........: main (custom_alloc.c:131)
Address 0x........ is 0 bytes after a block of size 28 alloc'd
at 0x........: custom_alloc (custom_alloc.c:47)
- by 0x........: main (custom_alloc.c:76)
+ by 0x........: main (custom_alloc.c:114)
Invalid free() / delete / delete[] / realloc()
- at 0x........: main (custom_alloc.c:96)
+ at 0x........: main (custom_alloc.c:134)
Address 0x........ is 4 bytes inside a block of size 28 alloc'd
at 0x........: custom_alloc (custom_alloc.c:47)
- by 0x........: main (custom_alloc.c:76)
+ by 0x........: main (custom_alloc.c:114)
Invalid free() / delete / delete[] / realloc()
at 0x........: custom_free (custom_alloc.c:54)
- by 0x........: main (custom_alloc.c:100)
+ by 0x........: main (custom_alloc.c:138)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
Mismatched free() / delete / delete []
at 0x........: custom_free (custom_alloc.c:54)
- by 0x........: main (custom_alloc.c:103)
+ by 0x........: main (custom_alloc.c:141)
Address 0x........ is 0 bytes inside a block of size 40 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: main (custom_alloc.c:102)
+ by 0x........: main (custom_alloc.c:140)
Invalid read of size 4
- at 0x........: main (custom_alloc.c:106)
+ at 0x........: main (custom_alloc.c:144)
Address 0x........ is 0 bytes inside a block of size 28 free'd
at 0x........: custom_free (custom_alloc.c:54)
- by 0x........: main (custom_alloc.c:98)
+ by 0x........: main (custom_alloc.c:136)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:68)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 1 bytes before a block of size 20 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:66)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:69)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 8 bytes before a block of size 20 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:66)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:73)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 0 bytes after a block of size 20 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:66)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:74)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 7 bytes after a block of size 20 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:66)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:83)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 1 bytes before a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:84)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 8 bytes before a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:88)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 0 bytes after a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:89)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 7 bytes after a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:90)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 8 bytes after a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
diff --git a/main/memcheck/tests/custom_alloc.stderr.exp-s390x-mvc b/main/memcheck/tests/custom_alloc.stderr.exp-s390x-mvc
new file mode 100644
index 0000000..6618a89
--- /dev/null
+++ b/main/memcheck/tests/custom_alloc.stderr.exp-s390x-mvc
@@ -0,0 +1,108 @@
+Invalid write of size 4
+ at 0x........: main (custom_alloc.c:117)
+ Address 0x........ is 0 bytes after a block of size 40 alloc'd
+ at 0x........: custom_alloc (custom_alloc.c:47)
+ by 0x........: main (custom_alloc.c:114)
+
+Invalid write of size 4
+ at 0x........: main (custom_alloc.c:121)
+ Address 0x........ is 0 bytes after a block of size 20 alloc'd
+ at 0x........: custom_alloc (custom_alloc.c:47)
+ by 0x........: main (custom_alloc.c:114)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: main (custom_alloc.c:128)
+
+Invalid write of size 4
+ at 0x........: main (custom_alloc.c:131)
+ Address 0x........ is 0 bytes after a block of size 28 alloc'd
+ at 0x........: custom_alloc (custom_alloc.c:47)
+ by 0x........: main (custom_alloc.c:114)
+
+Invalid free() / delete / delete[] / realloc()
+ at 0x........: main (custom_alloc.c:134)
+ Address 0x........ is 4 bytes inside a block of size 28 alloc'd
+ at 0x........: custom_alloc (custom_alloc.c:47)
+ by 0x........: main (custom_alloc.c:114)
+
+Invalid free() / delete / delete[] / realloc()
+ at 0x........: custom_free (custom_alloc.c:54)
+ by 0x........: main (custom_alloc.c:138)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Mismatched free() / delete / delete []
+ at 0x........: custom_free (custom_alloc.c:54)
+ by 0x........: main (custom_alloc.c:141)
+ Address 0x........ is 0 bytes inside a block of size 40 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (custom_alloc.c:140)
+
+Invalid read of size 1
+ at 0x........: main (custom_alloc.c:144)
+ Address 0x........ is 0 bytes inside a block of size 28 free'd
+ at 0x........: custom_free (custom_alloc.c:54)
+ by 0x........: main (custom_alloc.c:136)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:68)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 1 bytes before a block of size 20 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:66)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:69)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 8 bytes before a block of size 20 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:66)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:73)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 0 bytes after a block of size 20 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:66)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:74)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 7 bytes after a block of size 20 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:66)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:83)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 1 bytes before a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:84)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 8 bytes before a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:88)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 0 bytes after a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:89)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 7 bytes after a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
+
+Invalid write of size 1
+ at 0x........: checkredzone (custom_alloc.c:90)
+ by 0x........: main (custom_alloc.c:151)
+ Address 0x........ is 8 bytes after a recently re-allocated block of size 10 alloc'd
+ at 0x........: checkredzone (custom_alloc.c:81)
+ by 0x........: main (custom_alloc.c:151)
+
diff --git a/main/memcheck/tests/darwin/Makefile.in b/main/memcheck/tests/darwin/Makefile.in
new file mode 100644
index 0000000..60a51ef
--- /dev/null
+++ b/main/memcheck/tests/darwin/Makefile.in
@@ -0,0 +1,754 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(noinst_HEADERS) \
+ $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = aio$(EXEEXT) env$(EXEEXT) pth-supp$(EXEEXT) \
+ scalar$(EXEEXT) scalar_fork$(EXEEXT) scalar_nocancel$(EXEEXT) \
+ scalar_vfork$(EXEEXT)
+subdir = memcheck/tests/darwin
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+aio_SOURCES = aio.c
+aio_OBJECTS = aio.$(OBJEXT)
+aio_LDADD = $(LDADD)
+env_SOURCES = env.c
+env_OBJECTS = env.$(OBJEXT)
+env_LDADD = $(LDADD)
+pth_supp_SOURCES = pth-supp.c
+pth_supp_OBJECTS = pth-supp.$(OBJEXT)
+pth_supp_LDADD = $(LDADD)
+scalar_SOURCES = scalar.c
+scalar_OBJECTS = scalar.$(OBJEXT)
+scalar_LDADD = $(LDADD)
+scalar_fork_SOURCES = scalar_fork.c
+scalar_fork_OBJECTS = scalar_fork.$(OBJEXT)
+scalar_fork_LDADD = $(LDADD)
+scalar_nocancel_SOURCES = scalar_nocancel.c
+scalar_nocancel_OBJECTS = scalar_nocancel.$(OBJEXT)
+scalar_nocancel_LDADD = $(LDADD)
+scalar_vfork_SOURCES = scalar_vfork.c
+scalar_vfork_OBJECTS = scalar_vfork.$(OBJEXT)
+scalar_vfork_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = aio.c env.c pth-supp.c scalar.c scalar_fork.c \
+ scalar_nocancel.c scalar_vfork.c
+DIST_SOURCES = aio.c env.c pth-supp.c scalar.c scalar_fork.c \
+ scalar_nocancel.c scalar_vfork.c
+HEADERS = $(noinst_HEADERS)
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI) \
+ $(FLAG_MMMX) $(FLAG_MSSE)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI) \
+ $(FLAG_MMMX) $(FLAG_MSSE)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) $(AM_FLAG_M3264_PRI)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+noinst_HEADERS = scalar.h
+EXTRA_DIST = \
+ aio.stderr.exp aio.vgtest \
+ env.stderr.exp env.vgtest \
+ pth-supp.stderr.exp pth-supp.vgtest \
+ scalar.stderr.exp scalar.vgtest \
+ scalar_fork.stderr.exp scalar_fork.vgtest \
+ scalar_nocancel.stderr.exp scalar_nocancel.vgtest \
+ scalar_vfork.stderr.exp scalar_vfork.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/darwin/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/darwin/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+aio$(EXEEXT): $(aio_OBJECTS) $(aio_DEPENDENCIES)
+ @rm -f aio$(EXEEXT)
+ $(LINK) $(aio_OBJECTS) $(aio_LDADD) $(LIBS)
+env$(EXEEXT): $(env_OBJECTS) $(env_DEPENDENCIES)
+ @rm -f env$(EXEEXT)
+ $(LINK) $(env_OBJECTS) $(env_LDADD) $(LIBS)
+pth-supp$(EXEEXT): $(pth_supp_OBJECTS) $(pth_supp_DEPENDENCIES)
+ @rm -f pth-supp$(EXEEXT)
+ $(LINK) $(pth_supp_OBJECTS) $(pth_supp_LDADD) $(LIBS)
+scalar$(EXEEXT): $(scalar_OBJECTS) $(scalar_DEPENDENCIES)
+ @rm -f scalar$(EXEEXT)
+ $(LINK) $(scalar_OBJECTS) $(scalar_LDADD) $(LIBS)
+scalar_fork$(EXEEXT): $(scalar_fork_OBJECTS) $(scalar_fork_DEPENDENCIES)
+ @rm -f scalar_fork$(EXEEXT)
+ $(LINK) $(scalar_fork_OBJECTS) $(scalar_fork_LDADD) $(LIBS)
+scalar_nocancel$(EXEEXT): $(scalar_nocancel_OBJECTS) $(scalar_nocancel_DEPENDENCIES)
+ @rm -f scalar_nocancel$(EXEEXT)
+ $(LINK) $(scalar_nocancel_OBJECTS) $(scalar_nocancel_LDADD) $(LIBS)
+scalar_vfork$(EXEEXT): $(scalar_vfork_OBJECTS) $(scalar_vfork_DEPENDENCIES)
+ @rm -f scalar_vfork$(EXEEXT)
+ $(LINK) $(scalar_vfork_OBJECTS) $(scalar_vfork_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aio.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/env.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth-supp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar_fork.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar_nocancel.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar_vfork.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS) $(HEADERS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/deep-backtrace.c b/main/memcheck/tests/deep-backtrace.c
new file mode 100644
index 0000000..a883cdb
--- /dev/null
+++ b/main/memcheck/tests/deep-backtrace.c
@@ -0,0 +1,499 @@
+int f1(int *p) { return *p; }
+int f2(int *p) { return f1(p); }
+int f3(int *p) { return f2(p); }
+int f4(int *p) { return f3(p); }
+int f5(int *p) { return f4(p); }
+int f6(int *p) { return f5(p); }
+int f7(int *p) { return f6(p); }
+int f8(int *p) { return f7(p); }
+int f9(int *p) { return f8(p); }
+int f10(int *p) { return f9(p); }
+int f11(int *p) { return f10(p); }
+int f12(int *p) { return f11(p); }
+int f13(int *p) { return f12(p); }
+int f14(int *p) { return f13(p); }
+int f15(int *p) { return f14(p); }
+int f16(int *p) { return f15(p); }
+int f17(int *p) { return f16(p); }
+int f18(int *p) { return f17(p); }
+int f19(int *p) { return f18(p); }
+int f20(int *p) { return f19(p); }
+int f21(int *p) { return f20(p); }
+int f22(int *p) { return f21(p); }
+int f23(int *p) { return f22(p); }
+int f24(int *p) { return f23(p); }
+int f25(int *p) { return f24(p); }
+int f26(int *p) { return f25(p); }
+int f27(int *p) { return f26(p); }
+int f28(int *p) { return f27(p); }
+int f29(int *p) { return f28(p); }
+int f30(int *p) { return f29(p); }
+int f31(int *p) { return f30(p); }
+int f32(int *p) { return f31(p); }
+int f33(int *p) { return f32(p); }
+int f34(int *p) { return f33(p); }
+int f35(int *p) { return f34(p); }
+int f36(int *p) { return f35(p); }
+int f37(int *p) { return f36(p); }
+int f38(int *p) { return f37(p); }
+int f39(int *p) { return f38(p); }
+int f40(int *p) { return f39(p); }
+int f41(int *p) { return f40(p); }
+int f42(int *p) { return f41(p); }
+int f43(int *p) { return f42(p); }
+int f44(int *p) { return f43(p); }
+int f45(int *p) { return f44(p); }
+int f46(int *p) { return f45(p); }
+int f47(int *p) { return f46(p); }
+int f48(int *p) { return f47(p); }
+int f49(int *p) { return f48(p); }
+int f50(int *p) { return f49(p); }
+int f51(int *p) { return f50(p); }
+int f52(int *p) { return f51(p); }
+int f53(int *p) { return f52(p); }
+int f54(int *p) { return f53(p); }
+int f55(int *p) { return f54(p); }
+int f56(int *p) { return f55(p); }
+int f57(int *p) { return f56(p); }
+int f58(int *p) { return f57(p); }
+int f59(int *p) { return f58(p); }
+int f60(int *p) { return f59(p); }
+int f61(int *p) { return f60(p); }
+int f62(int *p) { return f61(p); }
+int f63(int *p) { return f62(p); }
+int f64(int *p) { return f63(p); }
+int f65(int *p) { return f64(p); }
+int f66(int *p) { return f65(p); }
+int f67(int *p) { return f66(p); }
+int f68(int *p) { return f67(p); }
+int f69(int *p) { return f68(p); }
+int f70(int *p) { return f69(p); }
+int f71(int *p) { return f70(p); }
+int f72(int *p) { return f71(p); }
+int f73(int *p) { return f72(p); }
+int f74(int *p) { return f73(p); }
+int f75(int *p) { return f74(p); }
+int f76(int *p) { return f75(p); }
+int f77(int *p) { return f76(p); }
+int f78(int *p) { return f77(p); }
+int f79(int *p) { return f78(p); }
+int f80(int *p) { return f79(p); }
+int f81(int *p) { return f80(p); }
+int f82(int *p) { return f81(p); }
+int f83(int *p) { return f82(p); }
+int f84(int *p) { return f83(p); }
+int f85(int *p) { return f84(p); }
+int f86(int *p) { return f85(p); }
+int f87(int *p) { return f86(p); }
+int f88(int *p) { return f87(p); }
+int f89(int *p) { return f88(p); }
+int f90(int *p) { return f89(p); }
+int f91(int *p) { return f90(p); }
+int f92(int *p) { return f91(p); }
+int f93(int *p) { return f92(p); }
+int f94(int *p) { return f93(p); }
+int f95(int *p) { return f94(p); }
+int f96(int *p) { return f95(p); }
+int f97(int *p) { return f96(p); }
+int f98(int *p) { return f97(p); }
+int f99(int *p) { return f98(p); }
+int f100(int *p) { return f99(p); }
+int f101(int *p) { return f100(p); }
+int f102(int *p) { return f101(p); }
+int f103(int *p) { return f102(p); }
+int f104(int *p) { return f103(p); }
+int f105(int *p) { return f104(p); }
+int f106(int *p) { return f105(p); }
+int f107(int *p) { return f106(p); }
+int f108(int *p) { return f107(p); }
+int f109(int *p) { return f108(p); }
+int f110(int *p) { return f109(p); }
+int f111(int *p) { return f110(p); }
+int f112(int *p) { return f111(p); }
+int f113(int *p) { return f112(p); }
+int f114(int *p) { return f113(p); }
+int f115(int *p) { return f114(p); }
+int f116(int *p) { return f115(p); }
+int f117(int *p) { return f116(p); }
+int f118(int *p) { return f117(p); }
+int f119(int *p) { return f118(p); }
+int f120(int *p) { return f119(p); }
+int f121(int *p) { return f120(p); }
+int f122(int *p) { return f121(p); }
+int f123(int *p) { return f122(p); }
+int f124(int *p) { return f123(p); }
+int f125(int *p) { return f124(p); }
+int f126(int *p) { return f125(p); }
+int f127(int *p) { return f126(p); }
+int f128(int *p) { return f127(p); }
+int f129(int *p) { return f128(p); }
+int f130(int *p) { return f129(p); }
+int f131(int *p) { return f130(p); }
+int f132(int *p) { return f131(p); }
+int f133(int *p) { return f132(p); }
+int f134(int *p) { return f133(p); }
+int f135(int *p) { return f134(p); }
+int f136(int *p) { return f135(p); }
+int f137(int *p) { return f136(p); }
+int f138(int *p) { return f137(p); }
+int f139(int *p) { return f138(p); }
+int f140(int *p) { return f139(p); }
+int f141(int *p) { return f140(p); }
+int f142(int *p) { return f141(p); }
+int f143(int *p) { return f142(p); }
+int f144(int *p) { return f143(p); }
+int f145(int *p) { return f144(p); }
+int f146(int *p) { return f145(p); }
+int f147(int *p) { return f146(p); }
+int f148(int *p) { return f147(p); }
+int f149(int *p) { return f148(p); }
+int f150(int *p) { return f149(p); }
+int f151(int *p) { return f150(p); }
+int f152(int *p) { return f151(p); }
+int f153(int *p) { return f152(p); }
+int f154(int *p) { return f153(p); }
+int f155(int *p) { return f154(p); }
+int f156(int *p) { return f155(p); }
+int f157(int *p) { return f156(p); }
+int f158(int *p) { return f157(p); }
+int f159(int *p) { return f158(p); }
+int f160(int *p) { return f159(p); }
+int f161(int *p) { return f160(p); }
+int f162(int *p) { return f161(p); }
+int f163(int *p) { return f162(p); }
+int f164(int *p) { return f163(p); }
+int f165(int *p) { return f164(p); }
+int f166(int *p) { return f165(p); }
+int f167(int *p) { return f166(p); }
+int f168(int *p) { return f167(p); }
+int f169(int *p) { return f168(p); }
+int f170(int *p) { return f169(p); }
+int f171(int *p) { return f170(p); }
+int f172(int *p) { return f171(p); }
+int f173(int *p) { return f172(p); }
+int f174(int *p) { return f173(p); }
+int f175(int *p) { return f174(p); }
+int f176(int *p) { return f175(p); }
+int f177(int *p) { return f176(p); }
+int f178(int *p) { return f177(p); }
+int f179(int *p) { return f178(p); }
+int f180(int *p) { return f179(p); }
+int f181(int *p) { return f180(p); }
+int f182(int *p) { return f181(p); }
+int f183(int *p) { return f182(p); }
+int f184(int *p) { return f183(p); }
+int f185(int *p) { return f184(p); }
+int f186(int *p) { return f185(p); }
+int f187(int *p) { return f186(p); }
+int f188(int *p) { return f187(p); }
+int f189(int *p) { return f188(p); }
+int f190(int *p) { return f189(p); }
+int f191(int *p) { return f190(p); }
+int f192(int *p) { return f191(p); }
+int f193(int *p) { return f192(p); }
+int f194(int *p) { return f193(p); }
+int f195(int *p) { return f194(p); }
+int f196(int *p) { return f195(p); }
+int f197(int *p) { return f196(p); }
+int f198(int *p) { return f197(p); }
+int f199(int *p) { return f198(p); }
+int f200(int *p) { return f199(p); }
+int f201(int *p) { return f200(p); }
+int f202(int *p) { return f201(p); }
+int f203(int *p) { return f202(p); }
+int f204(int *p) { return f203(p); }
+int f205(int *p) { return f204(p); }
+int f206(int *p) { return f205(p); }
+int f207(int *p) { return f206(p); }
+int f208(int *p) { return f207(p); }
+int f209(int *p) { return f208(p); }
+int f210(int *p) { return f209(p); }
+int f211(int *p) { return f210(p); }
+int f212(int *p) { return f211(p); }
+int f213(int *p) { return f212(p); }
+int f214(int *p) { return f213(p); }
+int f215(int *p) { return f214(p); }
+int f216(int *p) { return f215(p); }
+int f217(int *p) { return f216(p); }
+int f218(int *p) { return f217(p); }
+int f219(int *p) { return f218(p); }
+int f220(int *p) { return f219(p); }
+int f221(int *p) { return f220(p); }
+int f222(int *p) { return f221(p); }
+int f223(int *p) { return f222(p); }
+int f224(int *p) { return f223(p); }
+int f225(int *p) { return f224(p); }
+int f226(int *p) { return f225(p); }
+int f227(int *p) { return f226(p); }
+int f228(int *p) { return f227(p); }
+int f229(int *p) { return f228(p); }
+int f230(int *p) { return f229(p); }
+int f231(int *p) { return f230(p); }
+int f232(int *p) { return f231(p); }
+int f233(int *p) { return f232(p); }
+int f234(int *p) { return f233(p); }
+int f235(int *p) { return f234(p); }
+int f236(int *p) { return f235(p); }
+int f237(int *p) { return f236(p); }
+int f238(int *p) { return f237(p); }
+int f239(int *p) { return f238(p); }
+int f240(int *p) { return f239(p); }
+int f241(int *p) { return f240(p); }
+int f242(int *p) { return f241(p); }
+int f243(int *p) { return f242(p); }
+int f244(int *p) { return f243(p); }
+int f245(int *p) { return f244(p); }
+int f246(int *p) { return f245(p); }
+int f247(int *p) { return f246(p); }
+int f248(int *p) { return f247(p); }
+int f249(int *p) { return f248(p); }
+int f250(int *p) { return f249(p); }
+int f251(int *p) { return f250(p); }
+int f252(int *p) { return f251(p); }
+int f253(int *p) { return f252(p); }
+int f254(int *p) { return f253(p); }
+int f255(int *p) { return f254(p); }
+int f256(int *p) { return f255(p); }
+int f257(int *p) { return f256(p); }
+int f258(int *p) { return f257(p); }
+int f259(int *p) { return f258(p); }
+int f260(int *p) { return f259(p); }
+int f261(int *p) { return f260(p); }
+int f262(int *p) { return f261(p); }
+int f263(int *p) { return f262(p); }
+int f264(int *p) { return f263(p); }
+int f265(int *p) { return f264(p); }
+int f266(int *p) { return f265(p); }
+int f267(int *p) { return f266(p); }
+int f268(int *p) { return f267(p); }
+int f269(int *p) { return f268(p); }
+int f270(int *p) { return f269(p); }
+int f271(int *p) { return f270(p); }
+int f272(int *p) { return f271(p); }
+int f273(int *p) { return f272(p); }
+int f274(int *p) { return f273(p); }
+int f275(int *p) { return f274(p); }
+int f276(int *p) { return f275(p); }
+int f277(int *p) { return f276(p); }
+int f278(int *p) { return f277(p); }
+int f279(int *p) { return f278(p); }
+int f280(int *p) { return f279(p); }
+int f281(int *p) { return f280(p); }
+int f282(int *p) { return f281(p); }
+int f283(int *p) { return f282(p); }
+int f284(int *p) { return f283(p); }
+int f285(int *p) { return f284(p); }
+int f286(int *p) { return f285(p); }
+int f287(int *p) { return f286(p); }
+int f288(int *p) { return f287(p); }
+int f289(int *p) { return f288(p); }
+int f290(int *p) { return f289(p); }
+int f291(int *p) { return f290(p); }
+int f292(int *p) { return f291(p); }
+int f293(int *p) { return f292(p); }
+int f294(int *p) { return f293(p); }
+int f295(int *p) { return f294(p); }
+int f296(int *p) { return f295(p); }
+int f297(int *p) { return f296(p); }
+int f298(int *p) { return f297(p); }
+int f299(int *p) { return f298(p); }
+int f300(int *p) { return f299(p); }
+int f301(int *p) { return f300(p); }
+int f302(int *p) { return f301(p); }
+int f303(int *p) { return f302(p); }
+int f304(int *p) { return f303(p); }
+int f305(int *p) { return f304(p); }
+int f306(int *p) { return f305(p); }
+int f307(int *p) { return f306(p); }
+int f308(int *p) { return f307(p); }
+int f309(int *p) { return f308(p); }
+int f310(int *p) { return f309(p); }
+int f311(int *p) { return f310(p); }
+int f312(int *p) { return f311(p); }
+int f313(int *p) { return f312(p); }
+int f314(int *p) { return f313(p); }
+int f315(int *p) { return f314(p); }
+int f316(int *p) { return f315(p); }
+int f317(int *p) { return f316(p); }
+int f318(int *p) { return f317(p); }
+int f319(int *p) { return f318(p); }
+int f320(int *p) { return f319(p); }
+int f321(int *p) { return f320(p); }
+int f322(int *p) { return f321(p); }
+int f323(int *p) { return f322(p); }
+int f324(int *p) { return f323(p); }
+int f325(int *p) { return f324(p); }
+int f326(int *p) { return f325(p); }
+int f327(int *p) { return f326(p); }
+int f328(int *p) { return f327(p); }
+int f329(int *p) { return f328(p); }
+int f330(int *p) { return f329(p); }
+int f331(int *p) { return f330(p); }
+int f332(int *p) { return f331(p); }
+int f333(int *p) { return f332(p); }
+int f334(int *p) { return f333(p); }
+int f335(int *p) { return f334(p); }
+int f336(int *p) { return f335(p); }
+int f337(int *p) { return f336(p); }
+int f338(int *p) { return f337(p); }
+int f339(int *p) { return f338(p); }
+int f340(int *p) { return f339(p); }
+int f341(int *p) { return f340(p); }
+int f342(int *p) { return f341(p); }
+int f343(int *p) { return f342(p); }
+int f344(int *p) { return f343(p); }
+int f345(int *p) { return f344(p); }
+int f346(int *p) { return f345(p); }
+int f347(int *p) { return f346(p); }
+int f348(int *p) { return f347(p); }
+int f349(int *p) { return f348(p); }
+int f350(int *p) { return f349(p); }
+int f351(int *p) { return f350(p); }
+int f352(int *p) { return f351(p); }
+int f353(int *p) { return f352(p); }
+int f354(int *p) { return f353(p); }
+int f355(int *p) { return f354(p); }
+int f356(int *p) { return f355(p); }
+int f357(int *p) { return f356(p); }
+int f358(int *p) { return f357(p); }
+int f359(int *p) { return f358(p); }
+int f360(int *p) { return f359(p); }
+int f361(int *p) { return f360(p); }
+int f362(int *p) { return f361(p); }
+int f363(int *p) { return f362(p); }
+int f364(int *p) { return f363(p); }
+int f365(int *p) { return f364(p); }
+int f366(int *p) { return f365(p); }
+int f367(int *p) { return f366(p); }
+int f368(int *p) { return f367(p); }
+int f369(int *p) { return f368(p); }
+int f370(int *p) { return f369(p); }
+int f371(int *p) { return f370(p); }
+int f372(int *p) { return f371(p); }
+int f373(int *p) { return f372(p); }
+int f374(int *p) { return f373(p); }
+int f375(int *p) { return f374(p); }
+int f376(int *p) { return f375(p); }
+int f377(int *p) { return f376(p); }
+int f378(int *p) { return f377(p); }
+int f379(int *p) { return f378(p); }
+int f380(int *p) { return f379(p); }
+int f381(int *p) { return f380(p); }
+int f382(int *p) { return f381(p); }
+int f383(int *p) { return f382(p); }
+int f384(int *p) { return f383(p); }
+int f385(int *p) { return f384(p); }
+int f386(int *p) { return f385(p); }
+int f387(int *p) { return f386(p); }
+int f388(int *p) { return f387(p); }
+int f389(int *p) { return f388(p); }
+int f390(int *p) { return f389(p); }
+int f391(int *p) { return f390(p); }
+int f392(int *p) { return f391(p); }
+int f393(int *p) { return f392(p); }
+int f394(int *p) { return f393(p); }
+int f395(int *p) { return f394(p); }
+int f396(int *p) { return f395(p); }
+int f397(int *p) { return f396(p); }
+int f398(int *p) { return f397(p); }
+int f399(int *p) { return f398(p); }
+int f400(int *p) { return f399(p); }
+int f401(int *p) { return f400(p); }
+int f402(int *p) { return f401(p); }
+int f403(int *p) { return f402(p); }
+int f404(int *p) { return f403(p); }
+int f405(int *p) { return f404(p); }
+int f406(int *p) { return f405(p); }
+int f407(int *p) { return f406(p); }
+int f408(int *p) { return f407(p); }
+int f409(int *p) { return f408(p); }
+int f410(int *p) { return f409(p); }
+int f411(int *p) { return f410(p); }
+int f412(int *p) { return f411(p); }
+int f413(int *p) { return f412(p); }
+int f414(int *p) { return f413(p); }
+int f415(int *p) { return f414(p); }
+int f416(int *p) { return f415(p); }
+int f417(int *p) { return f416(p); }
+int f418(int *p) { return f417(p); }
+int f419(int *p) { return f418(p); }
+int f420(int *p) { return f419(p); }
+int f421(int *p) { return f420(p); }
+int f422(int *p) { return f421(p); }
+int f423(int *p) { return f422(p); }
+int f424(int *p) { return f423(p); }
+int f425(int *p) { return f424(p); }
+int f426(int *p) { return f425(p); }
+int f427(int *p) { return f426(p); }
+int f428(int *p) { return f427(p); }
+int f429(int *p) { return f428(p); }
+int f430(int *p) { return f429(p); }
+int f431(int *p) { return f430(p); }
+int f432(int *p) { return f431(p); }
+int f433(int *p) { return f432(p); }
+int f434(int *p) { return f433(p); }
+int f435(int *p) { return f434(p); }
+int f436(int *p) { return f435(p); }
+int f437(int *p) { return f436(p); }
+int f438(int *p) { return f437(p); }
+int f439(int *p) { return f438(p); }
+int f440(int *p) { return f439(p); }
+int f441(int *p) { return f440(p); }
+int f442(int *p) { return f441(p); }
+int f443(int *p) { return f442(p); }
+int f444(int *p) { return f443(p); }
+int f445(int *p) { return f444(p); }
+int f446(int *p) { return f445(p); }
+int f447(int *p) { return f446(p); }
+int f448(int *p) { return f447(p); }
+int f449(int *p) { return f448(p); }
+int f450(int *p) { return f449(p); }
+int f451(int *p) { return f450(p); }
+int f452(int *p) { return f451(p); }
+int f453(int *p) { return f452(p); }
+int f454(int *p) { return f453(p); }
+int f455(int *p) { return f454(p); }
+int f456(int *p) { return f455(p); }
+int f457(int *p) { return f456(p); }
+int f458(int *p) { return f457(p); }
+int f459(int *p) { return f458(p); }
+int f460(int *p) { return f459(p); }
+int f461(int *p) { return f460(p); }
+int f462(int *p) { return f461(p); }
+int f463(int *p) { return f462(p); }
+int f464(int *p) { return f463(p); }
+int f465(int *p) { return f464(p); }
+int f466(int *p) { return f465(p); }
+int f467(int *p) { return f466(p); }
+int f468(int *p) { return f467(p); }
+int f469(int *p) { return f468(p); }
+int f470(int *p) { return f469(p); }
+int f471(int *p) { return f470(p); }
+int f472(int *p) { return f471(p); }
+int f473(int *p) { return f472(p); }
+int f474(int *p) { return f473(p); }
+int f475(int *p) { return f474(p); }
+int f476(int *p) { return f475(p); }
+int f477(int *p) { return f476(p); }
+int f478(int *p) { return f477(p); }
+int f479(int *p) { return f478(p); }
+int f480(int *p) { return f479(p); }
+int f481(int *p) { return f480(p); }
+int f482(int *p) { return f481(p); }
+int f483(int *p) { return f482(p); }
+int f484(int *p) { return f483(p); }
+int f485(int *p) { return f484(p); }
+int f486(int *p) { return f485(p); }
+int f487(int *p) { return f486(p); }
+int f488(int *p) { return f487(p); }
+int f489(int *p) { return f488(p); }
+int f490(int *p) { return f489(p); }
+int f491(int *p) { return f490(p); }
+int f492(int *p) { return f491(p); }
+int f493(int *p) { return f492(p); }
+int f494(int *p) { return f493(p); }
+int f495(int *p) { return f494(p); }
+int f496(int *p) { return f495(p); }
+int f497(int *p) { return f496(p); }
+int f498(int *p) { return f497(p); }
+int main() { return f498(0); }
diff --git a/main/memcheck/tests/deep-backtrace.stderr.exp b/main/memcheck/tests/deep-backtrace.stderr.exp
new file mode 100644
index 0000000..4809e47
--- /dev/null
+++ b/main/memcheck/tests/deep-backtrace.stderr.exp
@@ -0,0 +1,1009 @@
+Invalid read of size 4
+ at 0x........: f1 (deep-backtrace.c:1)
+ by 0x........: f2 (deep-backtrace.c:2)
+ by 0x........: f3 (deep-backtrace.c:3)
+ by 0x........: f4 (deep-backtrace.c:4)
+ by 0x........: f5 (deep-backtrace.c:5)
+ by 0x........: f6 (deep-backtrace.c:6)
+ by 0x........: f7 (deep-backtrace.c:7)
+ by 0x........: f8 (deep-backtrace.c:8)
+ by 0x........: f9 (deep-backtrace.c:9)
+ by 0x........: f10 (deep-backtrace.c:10)
+ by 0x........: f11 (deep-backtrace.c:11)
+ by 0x........: f12 (deep-backtrace.c:12)
+ by 0x........: f13 (deep-backtrace.c:13)
+ by 0x........: f14 (deep-backtrace.c:14)
+ by 0x........: f15 (deep-backtrace.c:15)
+ by 0x........: f16 (deep-backtrace.c:16)
+ by 0x........: f17 (deep-backtrace.c:17)
+ by 0x........: f18 (deep-backtrace.c:18)
+ by 0x........: f19 (deep-backtrace.c:19)
+ by 0x........: f20 (deep-backtrace.c:20)
+ by 0x........: f21 (deep-backtrace.c:21)
+ by 0x........: f22 (deep-backtrace.c:22)
+ by 0x........: f23 (deep-backtrace.c:23)
+ by 0x........: f24 (deep-backtrace.c:24)
+ by 0x........: f25 (deep-backtrace.c:25)
+ by 0x........: f26 (deep-backtrace.c:26)
+ by 0x........: f27 (deep-backtrace.c:27)
+ by 0x........: f28 (deep-backtrace.c:28)
+ by 0x........: f29 (deep-backtrace.c:29)
+ by 0x........: f30 (deep-backtrace.c:30)
+ by 0x........: f31 (deep-backtrace.c:31)
+ by 0x........: f32 (deep-backtrace.c:32)
+ by 0x........: f33 (deep-backtrace.c:33)
+ by 0x........: f34 (deep-backtrace.c:34)
+ by 0x........: f35 (deep-backtrace.c:35)
+ by 0x........: f36 (deep-backtrace.c:36)
+ by 0x........: f37 (deep-backtrace.c:37)
+ by 0x........: f38 (deep-backtrace.c:38)
+ by 0x........: f39 (deep-backtrace.c:39)
+ by 0x........: f40 (deep-backtrace.c:40)
+ by 0x........: f41 (deep-backtrace.c:41)
+ by 0x........: f42 (deep-backtrace.c:42)
+ by 0x........: f43 (deep-backtrace.c:43)
+ by 0x........: f44 (deep-backtrace.c:44)
+ by 0x........: f45 (deep-backtrace.c:45)
+ by 0x........: f46 (deep-backtrace.c:46)
+ by 0x........: f47 (deep-backtrace.c:47)
+ by 0x........: f48 (deep-backtrace.c:48)
+ by 0x........: f49 (deep-backtrace.c:49)
+ by 0x........: f50 (deep-backtrace.c:50)
+ by 0x........: f51 (deep-backtrace.c:51)
+ by 0x........: f52 (deep-backtrace.c:52)
+ by 0x........: f53 (deep-backtrace.c:53)
+ by 0x........: f54 (deep-backtrace.c:54)
+ by 0x........: f55 (deep-backtrace.c:55)
+ by 0x........: f56 (deep-backtrace.c:56)
+ by 0x........: f57 (deep-backtrace.c:57)
+ by 0x........: f58 (deep-backtrace.c:58)
+ by 0x........: f59 (deep-backtrace.c:59)
+ by 0x........: f60 (deep-backtrace.c:60)
+ by 0x........: f61 (deep-backtrace.c:61)
+ by 0x........: f62 (deep-backtrace.c:62)
+ by 0x........: f63 (deep-backtrace.c:63)
+ by 0x........: f64 (deep-backtrace.c:64)
+ by 0x........: f65 (deep-backtrace.c:65)
+ by 0x........: f66 (deep-backtrace.c:66)
+ by 0x........: f67 (deep-backtrace.c:67)
+ by 0x........: f68 (deep-backtrace.c:68)
+ by 0x........: f69 (deep-backtrace.c:69)
+ by 0x........: f70 (deep-backtrace.c:70)
+ by 0x........: f71 (deep-backtrace.c:71)
+ by 0x........: f72 (deep-backtrace.c:72)
+ by 0x........: f73 (deep-backtrace.c:73)
+ by 0x........: f74 (deep-backtrace.c:74)
+ by 0x........: f75 (deep-backtrace.c:75)
+ by 0x........: f76 (deep-backtrace.c:76)
+ by 0x........: f77 (deep-backtrace.c:77)
+ by 0x........: f78 (deep-backtrace.c:78)
+ by 0x........: f79 (deep-backtrace.c:79)
+ by 0x........: f80 (deep-backtrace.c:80)
+ by 0x........: f81 (deep-backtrace.c:81)
+ by 0x........: f82 (deep-backtrace.c:82)
+ by 0x........: f83 (deep-backtrace.c:83)
+ by 0x........: f84 (deep-backtrace.c:84)
+ by 0x........: f85 (deep-backtrace.c:85)
+ by 0x........: f86 (deep-backtrace.c:86)
+ by 0x........: f87 (deep-backtrace.c:87)
+ by 0x........: f88 (deep-backtrace.c:88)
+ by 0x........: f89 (deep-backtrace.c:89)
+ by 0x........: f90 (deep-backtrace.c:90)
+ by 0x........: f91 (deep-backtrace.c:91)
+ by 0x........: f92 (deep-backtrace.c:92)
+ by 0x........: f93 (deep-backtrace.c:93)
+ by 0x........: f94 (deep-backtrace.c:94)
+ by 0x........: f95 (deep-backtrace.c:95)
+ by 0x........: f96 (deep-backtrace.c:96)
+ by 0x........: f97 (deep-backtrace.c:97)
+ by 0x........: f98 (deep-backtrace.c:98)
+ by 0x........: f99 (deep-backtrace.c:99)
+ by 0x........: f100 (deep-backtrace.c:100)
+ by 0x........: f101 (deep-backtrace.c:101)
+ by 0x........: f102 (deep-backtrace.c:102)
+ by 0x........: f103 (deep-backtrace.c:103)
+ by 0x........: f104 (deep-backtrace.c:104)
+ by 0x........: f105 (deep-backtrace.c:105)
+ by 0x........: f106 (deep-backtrace.c:106)
+ by 0x........: f107 (deep-backtrace.c:107)
+ by 0x........: f108 (deep-backtrace.c:108)
+ by 0x........: f109 (deep-backtrace.c:109)
+ by 0x........: f110 (deep-backtrace.c:110)
+ by 0x........: f111 (deep-backtrace.c:111)
+ by 0x........: f112 (deep-backtrace.c:112)
+ by 0x........: f113 (deep-backtrace.c:113)
+ by 0x........: f114 (deep-backtrace.c:114)
+ by 0x........: f115 (deep-backtrace.c:115)
+ by 0x........: f116 (deep-backtrace.c:116)
+ by 0x........: f117 (deep-backtrace.c:117)
+ by 0x........: f118 (deep-backtrace.c:118)
+ by 0x........: f119 (deep-backtrace.c:119)
+ by 0x........: f120 (deep-backtrace.c:120)
+ by 0x........: f121 (deep-backtrace.c:121)
+ by 0x........: f122 (deep-backtrace.c:122)
+ by 0x........: f123 (deep-backtrace.c:123)
+ by 0x........: f124 (deep-backtrace.c:124)
+ by 0x........: f125 (deep-backtrace.c:125)
+ by 0x........: f126 (deep-backtrace.c:126)
+ by 0x........: f127 (deep-backtrace.c:127)
+ by 0x........: f128 (deep-backtrace.c:128)
+ by 0x........: f129 (deep-backtrace.c:129)
+ by 0x........: f130 (deep-backtrace.c:130)
+ by 0x........: f131 (deep-backtrace.c:131)
+ by 0x........: f132 (deep-backtrace.c:132)
+ by 0x........: f133 (deep-backtrace.c:133)
+ by 0x........: f134 (deep-backtrace.c:134)
+ by 0x........: f135 (deep-backtrace.c:135)
+ by 0x........: f136 (deep-backtrace.c:136)
+ by 0x........: f137 (deep-backtrace.c:137)
+ by 0x........: f138 (deep-backtrace.c:138)
+ by 0x........: f139 (deep-backtrace.c:139)
+ by 0x........: f140 (deep-backtrace.c:140)
+ by 0x........: f141 (deep-backtrace.c:141)
+ by 0x........: f142 (deep-backtrace.c:142)
+ by 0x........: f143 (deep-backtrace.c:143)
+ by 0x........: f144 (deep-backtrace.c:144)
+ by 0x........: f145 (deep-backtrace.c:145)
+ by 0x........: f146 (deep-backtrace.c:146)
+ by 0x........: f147 (deep-backtrace.c:147)
+ by 0x........: f148 (deep-backtrace.c:148)
+ by 0x........: f149 (deep-backtrace.c:149)
+ by 0x........: f150 (deep-backtrace.c:150)
+ by 0x........: f151 (deep-backtrace.c:151)
+ by 0x........: f152 (deep-backtrace.c:152)
+ by 0x........: f153 (deep-backtrace.c:153)
+ by 0x........: f154 (deep-backtrace.c:154)
+ by 0x........: f155 (deep-backtrace.c:155)
+ by 0x........: f156 (deep-backtrace.c:156)
+ by 0x........: f157 (deep-backtrace.c:157)
+ by 0x........: f158 (deep-backtrace.c:158)
+ by 0x........: f159 (deep-backtrace.c:159)
+ by 0x........: f160 (deep-backtrace.c:160)
+ by 0x........: f161 (deep-backtrace.c:161)
+ by 0x........: f162 (deep-backtrace.c:162)
+ by 0x........: f163 (deep-backtrace.c:163)
+ by 0x........: f164 (deep-backtrace.c:164)
+ by 0x........: f165 (deep-backtrace.c:165)
+ by 0x........: f166 (deep-backtrace.c:166)
+ by 0x........: f167 (deep-backtrace.c:167)
+ by 0x........: f168 (deep-backtrace.c:168)
+ by 0x........: f169 (deep-backtrace.c:169)
+ by 0x........: f170 (deep-backtrace.c:170)
+ by 0x........: f171 (deep-backtrace.c:171)
+ by 0x........: f172 (deep-backtrace.c:172)
+ by 0x........: f173 (deep-backtrace.c:173)
+ by 0x........: f174 (deep-backtrace.c:174)
+ by 0x........: f175 (deep-backtrace.c:175)
+ by 0x........: f176 (deep-backtrace.c:176)
+ by 0x........: f177 (deep-backtrace.c:177)
+ by 0x........: f178 (deep-backtrace.c:178)
+ by 0x........: f179 (deep-backtrace.c:179)
+ by 0x........: f180 (deep-backtrace.c:180)
+ by 0x........: f181 (deep-backtrace.c:181)
+ by 0x........: f182 (deep-backtrace.c:182)
+ by 0x........: f183 (deep-backtrace.c:183)
+ by 0x........: f184 (deep-backtrace.c:184)
+ by 0x........: f185 (deep-backtrace.c:185)
+ by 0x........: f186 (deep-backtrace.c:186)
+ by 0x........: f187 (deep-backtrace.c:187)
+ by 0x........: f188 (deep-backtrace.c:188)
+ by 0x........: f189 (deep-backtrace.c:189)
+ by 0x........: f190 (deep-backtrace.c:190)
+ by 0x........: f191 (deep-backtrace.c:191)
+ by 0x........: f192 (deep-backtrace.c:192)
+ by 0x........: f193 (deep-backtrace.c:193)
+ by 0x........: f194 (deep-backtrace.c:194)
+ by 0x........: f195 (deep-backtrace.c:195)
+ by 0x........: f196 (deep-backtrace.c:196)
+ by 0x........: f197 (deep-backtrace.c:197)
+ by 0x........: f198 (deep-backtrace.c:198)
+ by 0x........: f199 (deep-backtrace.c:199)
+ by 0x........: f200 (deep-backtrace.c:200)
+ by 0x........: f201 (deep-backtrace.c:201)
+ by 0x........: f202 (deep-backtrace.c:202)
+ by 0x........: f203 (deep-backtrace.c:203)
+ by 0x........: f204 (deep-backtrace.c:204)
+ by 0x........: f205 (deep-backtrace.c:205)
+ by 0x........: f206 (deep-backtrace.c:206)
+ by 0x........: f207 (deep-backtrace.c:207)
+ by 0x........: f208 (deep-backtrace.c:208)
+ by 0x........: f209 (deep-backtrace.c:209)
+ by 0x........: f210 (deep-backtrace.c:210)
+ by 0x........: f211 (deep-backtrace.c:211)
+ by 0x........: f212 (deep-backtrace.c:212)
+ by 0x........: f213 (deep-backtrace.c:213)
+ by 0x........: f214 (deep-backtrace.c:214)
+ by 0x........: f215 (deep-backtrace.c:215)
+ by 0x........: f216 (deep-backtrace.c:216)
+ by 0x........: f217 (deep-backtrace.c:217)
+ by 0x........: f218 (deep-backtrace.c:218)
+ by 0x........: f219 (deep-backtrace.c:219)
+ by 0x........: f220 (deep-backtrace.c:220)
+ by 0x........: f221 (deep-backtrace.c:221)
+ by 0x........: f222 (deep-backtrace.c:222)
+ by 0x........: f223 (deep-backtrace.c:223)
+ by 0x........: f224 (deep-backtrace.c:224)
+ by 0x........: f225 (deep-backtrace.c:225)
+ by 0x........: f226 (deep-backtrace.c:226)
+ by 0x........: f227 (deep-backtrace.c:227)
+ by 0x........: f228 (deep-backtrace.c:228)
+ by 0x........: f229 (deep-backtrace.c:229)
+ by 0x........: f230 (deep-backtrace.c:230)
+ by 0x........: f231 (deep-backtrace.c:231)
+ by 0x........: f232 (deep-backtrace.c:232)
+ by 0x........: f233 (deep-backtrace.c:233)
+ by 0x........: f234 (deep-backtrace.c:234)
+ by 0x........: f235 (deep-backtrace.c:235)
+ by 0x........: f236 (deep-backtrace.c:236)
+ by 0x........: f237 (deep-backtrace.c:237)
+ by 0x........: f238 (deep-backtrace.c:238)
+ by 0x........: f239 (deep-backtrace.c:239)
+ by 0x........: f240 (deep-backtrace.c:240)
+ by 0x........: f241 (deep-backtrace.c:241)
+ by 0x........: f242 (deep-backtrace.c:242)
+ by 0x........: f243 (deep-backtrace.c:243)
+ by 0x........: f244 (deep-backtrace.c:244)
+ by 0x........: f245 (deep-backtrace.c:245)
+ by 0x........: f246 (deep-backtrace.c:246)
+ by 0x........: f247 (deep-backtrace.c:247)
+ by 0x........: f248 (deep-backtrace.c:248)
+ by 0x........: f249 (deep-backtrace.c:249)
+ by 0x........: f250 (deep-backtrace.c:250)
+ by 0x........: f251 (deep-backtrace.c:251)
+ by 0x........: f252 (deep-backtrace.c:252)
+ by 0x........: f253 (deep-backtrace.c:253)
+ by 0x........: f254 (deep-backtrace.c:254)
+ by 0x........: f255 (deep-backtrace.c:255)
+ by 0x........: f256 (deep-backtrace.c:256)
+ by 0x........: f257 (deep-backtrace.c:257)
+ by 0x........: f258 (deep-backtrace.c:258)
+ by 0x........: f259 (deep-backtrace.c:259)
+ by 0x........: f260 (deep-backtrace.c:260)
+ by 0x........: f261 (deep-backtrace.c:261)
+ by 0x........: f262 (deep-backtrace.c:262)
+ by 0x........: f263 (deep-backtrace.c:263)
+ by 0x........: f264 (deep-backtrace.c:264)
+ by 0x........: f265 (deep-backtrace.c:265)
+ by 0x........: f266 (deep-backtrace.c:266)
+ by 0x........: f267 (deep-backtrace.c:267)
+ by 0x........: f268 (deep-backtrace.c:268)
+ by 0x........: f269 (deep-backtrace.c:269)
+ by 0x........: f270 (deep-backtrace.c:270)
+ by 0x........: f271 (deep-backtrace.c:271)
+ by 0x........: f272 (deep-backtrace.c:272)
+ by 0x........: f273 (deep-backtrace.c:273)
+ by 0x........: f274 (deep-backtrace.c:274)
+ by 0x........: f275 (deep-backtrace.c:275)
+ by 0x........: f276 (deep-backtrace.c:276)
+ by 0x........: f277 (deep-backtrace.c:277)
+ by 0x........: f278 (deep-backtrace.c:278)
+ by 0x........: f279 (deep-backtrace.c:279)
+ by 0x........: f280 (deep-backtrace.c:280)
+ by 0x........: f281 (deep-backtrace.c:281)
+ by 0x........: f282 (deep-backtrace.c:282)
+ by 0x........: f283 (deep-backtrace.c:283)
+ by 0x........: f284 (deep-backtrace.c:284)
+ by 0x........: f285 (deep-backtrace.c:285)
+ by 0x........: f286 (deep-backtrace.c:286)
+ by 0x........: f287 (deep-backtrace.c:287)
+ by 0x........: f288 (deep-backtrace.c:288)
+ by 0x........: f289 (deep-backtrace.c:289)
+ by 0x........: f290 (deep-backtrace.c:290)
+ by 0x........: f291 (deep-backtrace.c:291)
+ by 0x........: f292 (deep-backtrace.c:292)
+ by 0x........: f293 (deep-backtrace.c:293)
+ by 0x........: f294 (deep-backtrace.c:294)
+ by 0x........: f295 (deep-backtrace.c:295)
+ by 0x........: f296 (deep-backtrace.c:296)
+ by 0x........: f297 (deep-backtrace.c:297)
+ by 0x........: f298 (deep-backtrace.c:298)
+ by 0x........: f299 (deep-backtrace.c:299)
+ by 0x........: f300 (deep-backtrace.c:300)
+ by 0x........: f301 (deep-backtrace.c:301)
+ by 0x........: f302 (deep-backtrace.c:302)
+ by 0x........: f303 (deep-backtrace.c:303)
+ by 0x........: f304 (deep-backtrace.c:304)
+ by 0x........: f305 (deep-backtrace.c:305)
+ by 0x........: f306 (deep-backtrace.c:306)
+ by 0x........: f307 (deep-backtrace.c:307)
+ by 0x........: f308 (deep-backtrace.c:308)
+ by 0x........: f309 (deep-backtrace.c:309)
+ by 0x........: f310 (deep-backtrace.c:310)
+ by 0x........: f311 (deep-backtrace.c:311)
+ by 0x........: f312 (deep-backtrace.c:312)
+ by 0x........: f313 (deep-backtrace.c:313)
+ by 0x........: f314 (deep-backtrace.c:314)
+ by 0x........: f315 (deep-backtrace.c:315)
+ by 0x........: f316 (deep-backtrace.c:316)
+ by 0x........: f317 (deep-backtrace.c:317)
+ by 0x........: f318 (deep-backtrace.c:318)
+ by 0x........: f319 (deep-backtrace.c:319)
+ by 0x........: f320 (deep-backtrace.c:320)
+ by 0x........: f321 (deep-backtrace.c:321)
+ by 0x........: f322 (deep-backtrace.c:322)
+ by 0x........: f323 (deep-backtrace.c:323)
+ by 0x........: f324 (deep-backtrace.c:324)
+ by 0x........: f325 (deep-backtrace.c:325)
+ by 0x........: f326 (deep-backtrace.c:326)
+ by 0x........: f327 (deep-backtrace.c:327)
+ by 0x........: f328 (deep-backtrace.c:328)
+ by 0x........: f329 (deep-backtrace.c:329)
+ by 0x........: f330 (deep-backtrace.c:330)
+ by 0x........: f331 (deep-backtrace.c:331)
+ by 0x........: f332 (deep-backtrace.c:332)
+ by 0x........: f333 (deep-backtrace.c:333)
+ by 0x........: f334 (deep-backtrace.c:334)
+ by 0x........: f335 (deep-backtrace.c:335)
+ by 0x........: f336 (deep-backtrace.c:336)
+ by 0x........: f337 (deep-backtrace.c:337)
+ by 0x........: f338 (deep-backtrace.c:338)
+ by 0x........: f339 (deep-backtrace.c:339)
+ by 0x........: f340 (deep-backtrace.c:340)
+ by 0x........: f341 (deep-backtrace.c:341)
+ by 0x........: f342 (deep-backtrace.c:342)
+ by 0x........: f343 (deep-backtrace.c:343)
+ by 0x........: f344 (deep-backtrace.c:344)
+ by 0x........: f345 (deep-backtrace.c:345)
+ by 0x........: f346 (deep-backtrace.c:346)
+ by 0x........: f347 (deep-backtrace.c:347)
+ by 0x........: f348 (deep-backtrace.c:348)
+ by 0x........: f349 (deep-backtrace.c:349)
+ by 0x........: f350 (deep-backtrace.c:350)
+ by 0x........: f351 (deep-backtrace.c:351)
+ by 0x........: f352 (deep-backtrace.c:352)
+ by 0x........: f353 (deep-backtrace.c:353)
+ by 0x........: f354 (deep-backtrace.c:354)
+ by 0x........: f355 (deep-backtrace.c:355)
+ by 0x........: f356 (deep-backtrace.c:356)
+ by 0x........: f357 (deep-backtrace.c:357)
+ by 0x........: f358 (deep-backtrace.c:358)
+ by 0x........: f359 (deep-backtrace.c:359)
+ by 0x........: f360 (deep-backtrace.c:360)
+ by 0x........: f361 (deep-backtrace.c:361)
+ by 0x........: f362 (deep-backtrace.c:362)
+ by 0x........: f363 (deep-backtrace.c:363)
+ by 0x........: f364 (deep-backtrace.c:364)
+ by 0x........: f365 (deep-backtrace.c:365)
+ by 0x........: f366 (deep-backtrace.c:366)
+ by 0x........: f367 (deep-backtrace.c:367)
+ by 0x........: f368 (deep-backtrace.c:368)
+ by 0x........: f369 (deep-backtrace.c:369)
+ by 0x........: f370 (deep-backtrace.c:370)
+ by 0x........: f371 (deep-backtrace.c:371)
+ by 0x........: f372 (deep-backtrace.c:372)
+ by 0x........: f373 (deep-backtrace.c:373)
+ by 0x........: f374 (deep-backtrace.c:374)
+ by 0x........: f375 (deep-backtrace.c:375)
+ by 0x........: f376 (deep-backtrace.c:376)
+ by 0x........: f377 (deep-backtrace.c:377)
+ by 0x........: f378 (deep-backtrace.c:378)
+ by 0x........: f379 (deep-backtrace.c:379)
+ by 0x........: f380 (deep-backtrace.c:380)
+ by 0x........: f381 (deep-backtrace.c:381)
+ by 0x........: f382 (deep-backtrace.c:382)
+ by 0x........: f383 (deep-backtrace.c:383)
+ by 0x........: f384 (deep-backtrace.c:384)
+ by 0x........: f385 (deep-backtrace.c:385)
+ by 0x........: f386 (deep-backtrace.c:386)
+ by 0x........: f387 (deep-backtrace.c:387)
+ by 0x........: f388 (deep-backtrace.c:388)
+ by 0x........: f389 (deep-backtrace.c:389)
+ by 0x........: f390 (deep-backtrace.c:390)
+ by 0x........: f391 (deep-backtrace.c:391)
+ by 0x........: f392 (deep-backtrace.c:392)
+ by 0x........: f393 (deep-backtrace.c:393)
+ by 0x........: f394 (deep-backtrace.c:394)
+ by 0x........: f395 (deep-backtrace.c:395)
+ by 0x........: f396 (deep-backtrace.c:396)
+ by 0x........: f397 (deep-backtrace.c:397)
+ by 0x........: f398 (deep-backtrace.c:398)
+ by 0x........: f399 (deep-backtrace.c:399)
+ by 0x........: f400 (deep-backtrace.c:400)
+ by 0x........: f401 (deep-backtrace.c:401)
+ by 0x........: f402 (deep-backtrace.c:402)
+ by 0x........: f403 (deep-backtrace.c:403)
+ by 0x........: f404 (deep-backtrace.c:404)
+ by 0x........: f405 (deep-backtrace.c:405)
+ by 0x........: f406 (deep-backtrace.c:406)
+ by 0x........: f407 (deep-backtrace.c:407)
+ by 0x........: f408 (deep-backtrace.c:408)
+ by 0x........: f409 (deep-backtrace.c:409)
+ by 0x........: f410 (deep-backtrace.c:410)
+ by 0x........: f411 (deep-backtrace.c:411)
+ by 0x........: f412 (deep-backtrace.c:412)
+ by 0x........: f413 (deep-backtrace.c:413)
+ by 0x........: f414 (deep-backtrace.c:414)
+ by 0x........: f415 (deep-backtrace.c:415)
+ by 0x........: f416 (deep-backtrace.c:416)
+ by 0x........: f417 (deep-backtrace.c:417)
+ by 0x........: f418 (deep-backtrace.c:418)
+ by 0x........: f419 (deep-backtrace.c:419)
+ by 0x........: f420 (deep-backtrace.c:420)
+ by 0x........: f421 (deep-backtrace.c:421)
+ by 0x........: f422 (deep-backtrace.c:422)
+ by 0x........: f423 (deep-backtrace.c:423)
+ by 0x........: f424 (deep-backtrace.c:424)
+ by 0x........: f425 (deep-backtrace.c:425)
+ by 0x........: f426 (deep-backtrace.c:426)
+ by 0x........: f427 (deep-backtrace.c:427)
+ by 0x........: f428 (deep-backtrace.c:428)
+ by 0x........: f429 (deep-backtrace.c:429)
+ by 0x........: f430 (deep-backtrace.c:430)
+ by 0x........: f431 (deep-backtrace.c:431)
+ by 0x........: f432 (deep-backtrace.c:432)
+ by 0x........: f433 (deep-backtrace.c:433)
+ by 0x........: f434 (deep-backtrace.c:434)
+ by 0x........: f435 (deep-backtrace.c:435)
+ by 0x........: f436 (deep-backtrace.c:436)
+ by 0x........: f437 (deep-backtrace.c:437)
+ by 0x........: f438 (deep-backtrace.c:438)
+ by 0x........: f439 (deep-backtrace.c:439)
+ by 0x........: f440 (deep-backtrace.c:440)
+ by 0x........: f441 (deep-backtrace.c:441)
+ by 0x........: f442 (deep-backtrace.c:442)
+ by 0x........: f443 (deep-backtrace.c:443)
+ by 0x........: f444 (deep-backtrace.c:444)
+ by 0x........: f445 (deep-backtrace.c:445)
+ by 0x........: f446 (deep-backtrace.c:446)
+ by 0x........: f447 (deep-backtrace.c:447)
+ by 0x........: f448 (deep-backtrace.c:448)
+ by 0x........: f449 (deep-backtrace.c:449)
+ by 0x........: f450 (deep-backtrace.c:450)
+ by 0x........: f451 (deep-backtrace.c:451)
+ by 0x........: f452 (deep-backtrace.c:452)
+ by 0x........: f453 (deep-backtrace.c:453)
+ by 0x........: f454 (deep-backtrace.c:454)
+ by 0x........: f455 (deep-backtrace.c:455)
+ by 0x........: f456 (deep-backtrace.c:456)
+ by 0x........: f457 (deep-backtrace.c:457)
+ by 0x........: f458 (deep-backtrace.c:458)
+ by 0x........: f459 (deep-backtrace.c:459)
+ by 0x........: f460 (deep-backtrace.c:460)
+ by 0x........: f461 (deep-backtrace.c:461)
+ by 0x........: f462 (deep-backtrace.c:462)
+ by 0x........: f463 (deep-backtrace.c:463)
+ by 0x........: f464 (deep-backtrace.c:464)
+ by 0x........: f465 (deep-backtrace.c:465)
+ by 0x........: f466 (deep-backtrace.c:466)
+ by 0x........: f467 (deep-backtrace.c:467)
+ by 0x........: f468 (deep-backtrace.c:468)
+ by 0x........: f469 (deep-backtrace.c:469)
+ by 0x........: f470 (deep-backtrace.c:470)
+ by 0x........: f471 (deep-backtrace.c:471)
+ by 0x........: f472 (deep-backtrace.c:472)
+ by 0x........: f473 (deep-backtrace.c:473)
+ by 0x........: f474 (deep-backtrace.c:474)
+ by 0x........: f475 (deep-backtrace.c:475)
+ by 0x........: f476 (deep-backtrace.c:476)
+ by 0x........: f477 (deep-backtrace.c:477)
+ by 0x........: f478 (deep-backtrace.c:478)
+ by 0x........: f479 (deep-backtrace.c:479)
+ by 0x........: f480 (deep-backtrace.c:480)
+ by 0x........: f481 (deep-backtrace.c:481)
+ by 0x........: f482 (deep-backtrace.c:482)
+ by 0x........: f483 (deep-backtrace.c:483)
+ by 0x........: f484 (deep-backtrace.c:484)
+ by 0x........: f485 (deep-backtrace.c:485)
+ by 0x........: f486 (deep-backtrace.c:486)
+ by 0x........: f487 (deep-backtrace.c:487)
+ by 0x........: f488 (deep-backtrace.c:488)
+ by 0x........: f489 (deep-backtrace.c:489)
+ by 0x........: f490 (deep-backtrace.c:490)
+ by 0x........: f491 (deep-backtrace.c:491)
+ by 0x........: f492 (deep-backtrace.c:492)
+ by 0x........: f493 (deep-backtrace.c:493)
+ by 0x........: f494 (deep-backtrace.c:494)
+ by 0x........: f495 (deep-backtrace.c:495)
+ by 0x........: f496 (deep-backtrace.c:496)
+ by 0x........: f497 (deep-backtrace.c:497)
+ by 0x........: f498 (deep-backtrace.c:498)
+ by 0x........: main (deep-backtrace.c:499)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+
+Process terminating with default action of signal 11 (SIGSEGV)
+ Access not within mapped region at address 0x........
+ at 0x........: f1 (deep-backtrace.c:1)
+ by 0x........: f2 (deep-backtrace.c:2)
+ by 0x........: f3 (deep-backtrace.c:3)
+ by 0x........: f4 (deep-backtrace.c:4)
+ by 0x........: f5 (deep-backtrace.c:5)
+ by 0x........: f6 (deep-backtrace.c:6)
+ by 0x........: f7 (deep-backtrace.c:7)
+ by 0x........: f8 (deep-backtrace.c:8)
+ by 0x........: f9 (deep-backtrace.c:9)
+ by 0x........: f10 (deep-backtrace.c:10)
+ by 0x........: f11 (deep-backtrace.c:11)
+ by 0x........: f12 (deep-backtrace.c:12)
+ by 0x........: f13 (deep-backtrace.c:13)
+ by 0x........: f14 (deep-backtrace.c:14)
+ by 0x........: f15 (deep-backtrace.c:15)
+ by 0x........: f16 (deep-backtrace.c:16)
+ by 0x........: f17 (deep-backtrace.c:17)
+ by 0x........: f18 (deep-backtrace.c:18)
+ by 0x........: f19 (deep-backtrace.c:19)
+ by 0x........: f20 (deep-backtrace.c:20)
+ by 0x........: f21 (deep-backtrace.c:21)
+ by 0x........: f22 (deep-backtrace.c:22)
+ by 0x........: f23 (deep-backtrace.c:23)
+ by 0x........: f24 (deep-backtrace.c:24)
+ by 0x........: f25 (deep-backtrace.c:25)
+ by 0x........: f26 (deep-backtrace.c:26)
+ by 0x........: f27 (deep-backtrace.c:27)
+ by 0x........: f28 (deep-backtrace.c:28)
+ by 0x........: f29 (deep-backtrace.c:29)
+ by 0x........: f30 (deep-backtrace.c:30)
+ by 0x........: f31 (deep-backtrace.c:31)
+ by 0x........: f32 (deep-backtrace.c:32)
+ by 0x........: f33 (deep-backtrace.c:33)
+ by 0x........: f34 (deep-backtrace.c:34)
+ by 0x........: f35 (deep-backtrace.c:35)
+ by 0x........: f36 (deep-backtrace.c:36)
+ by 0x........: f37 (deep-backtrace.c:37)
+ by 0x........: f38 (deep-backtrace.c:38)
+ by 0x........: f39 (deep-backtrace.c:39)
+ by 0x........: f40 (deep-backtrace.c:40)
+ by 0x........: f41 (deep-backtrace.c:41)
+ by 0x........: f42 (deep-backtrace.c:42)
+ by 0x........: f43 (deep-backtrace.c:43)
+ by 0x........: f44 (deep-backtrace.c:44)
+ by 0x........: f45 (deep-backtrace.c:45)
+ by 0x........: f46 (deep-backtrace.c:46)
+ by 0x........: f47 (deep-backtrace.c:47)
+ by 0x........: f48 (deep-backtrace.c:48)
+ by 0x........: f49 (deep-backtrace.c:49)
+ by 0x........: f50 (deep-backtrace.c:50)
+ by 0x........: f51 (deep-backtrace.c:51)
+ by 0x........: f52 (deep-backtrace.c:52)
+ by 0x........: f53 (deep-backtrace.c:53)
+ by 0x........: f54 (deep-backtrace.c:54)
+ by 0x........: f55 (deep-backtrace.c:55)
+ by 0x........: f56 (deep-backtrace.c:56)
+ by 0x........: f57 (deep-backtrace.c:57)
+ by 0x........: f58 (deep-backtrace.c:58)
+ by 0x........: f59 (deep-backtrace.c:59)
+ by 0x........: f60 (deep-backtrace.c:60)
+ by 0x........: f61 (deep-backtrace.c:61)
+ by 0x........: f62 (deep-backtrace.c:62)
+ by 0x........: f63 (deep-backtrace.c:63)
+ by 0x........: f64 (deep-backtrace.c:64)
+ by 0x........: f65 (deep-backtrace.c:65)
+ by 0x........: f66 (deep-backtrace.c:66)
+ by 0x........: f67 (deep-backtrace.c:67)
+ by 0x........: f68 (deep-backtrace.c:68)
+ by 0x........: f69 (deep-backtrace.c:69)
+ by 0x........: f70 (deep-backtrace.c:70)
+ by 0x........: f71 (deep-backtrace.c:71)
+ by 0x........: f72 (deep-backtrace.c:72)
+ by 0x........: f73 (deep-backtrace.c:73)
+ by 0x........: f74 (deep-backtrace.c:74)
+ by 0x........: f75 (deep-backtrace.c:75)
+ by 0x........: f76 (deep-backtrace.c:76)
+ by 0x........: f77 (deep-backtrace.c:77)
+ by 0x........: f78 (deep-backtrace.c:78)
+ by 0x........: f79 (deep-backtrace.c:79)
+ by 0x........: f80 (deep-backtrace.c:80)
+ by 0x........: f81 (deep-backtrace.c:81)
+ by 0x........: f82 (deep-backtrace.c:82)
+ by 0x........: f83 (deep-backtrace.c:83)
+ by 0x........: f84 (deep-backtrace.c:84)
+ by 0x........: f85 (deep-backtrace.c:85)
+ by 0x........: f86 (deep-backtrace.c:86)
+ by 0x........: f87 (deep-backtrace.c:87)
+ by 0x........: f88 (deep-backtrace.c:88)
+ by 0x........: f89 (deep-backtrace.c:89)
+ by 0x........: f90 (deep-backtrace.c:90)
+ by 0x........: f91 (deep-backtrace.c:91)
+ by 0x........: f92 (deep-backtrace.c:92)
+ by 0x........: f93 (deep-backtrace.c:93)
+ by 0x........: f94 (deep-backtrace.c:94)
+ by 0x........: f95 (deep-backtrace.c:95)
+ by 0x........: f96 (deep-backtrace.c:96)
+ by 0x........: f97 (deep-backtrace.c:97)
+ by 0x........: f98 (deep-backtrace.c:98)
+ by 0x........: f99 (deep-backtrace.c:99)
+ by 0x........: f100 (deep-backtrace.c:100)
+ by 0x........: f101 (deep-backtrace.c:101)
+ by 0x........: f102 (deep-backtrace.c:102)
+ by 0x........: f103 (deep-backtrace.c:103)
+ by 0x........: f104 (deep-backtrace.c:104)
+ by 0x........: f105 (deep-backtrace.c:105)
+ by 0x........: f106 (deep-backtrace.c:106)
+ by 0x........: f107 (deep-backtrace.c:107)
+ by 0x........: f108 (deep-backtrace.c:108)
+ by 0x........: f109 (deep-backtrace.c:109)
+ by 0x........: f110 (deep-backtrace.c:110)
+ by 0x........: f111 (deep-backtrace.c:111)
+ by 0x........: f112 (deep-backtrace.c:112)
+ by 0x........: f113 (deep-backtrace.c:113)
+ by 0x........: f114 (deep-backtrace.c:114)
+ by 0x........: f115 (deep-backtrace.c:115)
+ by 0x........: f116 (deep-backtrace.c:116)
+ by 0x........: f117 (deep-backtrace.c:117)
+ by 0x........: f118 (deep-backtrace.c:118)
+ by 0x........: f119 (deep-backtrace.c:119)
+ by 0x........: f120 (deep-backtrace.c:120)
+ by 0x........: f121 (deep-backtrace.c:121)
+ by 0x........: f122 (deep-backtrace.c:122)
+ by 0x........: f123 (deep-backtrace.c:123)
+ by 0x........: f124 (deep-backtrace.c:124)
+ by 0x........: f125 (deep-backtrace.c:125)
+ by 0x........: f126 (deep-backtrace.c:126)
+ by 0x........: f127 (deep-backtrace.c:127)
+ by 0x........: f128 (deep-backtrace.c:128)
+ by 0x........: f129 (deep-backtrace.c:129)
+ by 0x........: f130 (deep-backtrace.c:130)
+ by 0x........: f131 (deep-backtrace.c:131)
+ by 0x........: f132 (deep-backtrace.c:132)
+ by 0x........: f133 (deep-backtrace.c:133)
+ by 0x........: f134 (deep-backtrace.c:134)
+ by 0x........: f135 (deep-backtrace.c:135)
+ by 0x........: f136 (deep-backtrace.c:136)
+ by 0x........: f137 (deep-backtrace.c:137)
+ by 0x........: f138 (deep-backtrace.c:138)
+ by 0x........: f139 (deep-backtrace.c:139)
+ by 0x........: f140 (deep-backtrace.c:140)
+ by 0x........: f141 (deep-backtrace.c:141)
+ by 0x........: f142 (deep-backtrace.c:142)
+ by 0x........: f143 (deep-backtrace.c:143)
+ by 0x........: f144 (deep-backtrace.c:144)
+ by 0x........: f145 (deep-backtrace.c:145)
+ by 0x........: f146 (deep-backtrace.c:146)
+ by 0x........: f147 (deep-backtrace.c:147)
+ by 0x........: f148 (deep-backtrace.c:148)
+ by 0x........: f149 (deep-backtrace.c:149)
+ by 0x........: f150 (deep-backtrace.c:150)
+ by 0x........: f151 (deep-backtrace.c:151)
+ by 0x........: f152 (deep-backtrace.c:152)
+ by 0x........: f153 (deep-backtrace.c:153)
+ by 0x........: f154 (deep-backtrace.c:154)
+ by 0x........: f155 (deep-backtrace.c:155)
+ by 0x........: f156 (deep-backtrace.c:156)
+ by 0x........: f157 (deep-backtrace.c:157)
+ by 0x........: f158 (deep-backtrace.c:158)
+ by 0x........: f159 (deep-backtrace.c:159)
+ by 0x........: f160 (deep-backtrace.c:160)
+ by 0x........: f161 (deep-backtrace.c:161)
+ by 0x........: f162 (deep-backtrace.c:162)
+ by 0x........: f163 (deep-backtrace.c:163)
+ by 0x........: f164 (deep-backtrace.c:164)
+ by 0x........: f165 (deep-backtrace.c:165)
+ by 0x........: f166 (deep-backtrace.c:166)
+ by 0x........: f167 (deep-backtrace.c:167)
+ by 0x........: f168 (deep-backtrace.c:168)
+ by 0x........: f169 (deep-backtrace.c:169)
+ by 0x........: f170 (deep-backtrace.c:170)
+ by 0x........: f171 (deep-backtrace.c:171)
+ by 0x........: f172 (deep-backtrace.c:172)
+ by 0x........: f173 (deep-backtrace.c:173)
+ by 0x........: f174 (deep-backtrace.c:174)
+ by 0x........: f175 (deep-backtrace.c:175)
+ by 0x........: f176 (deep-backtrace.c:176)
+ by 0x........: f177 (deep-backtrace.c:177)
+ by 0x........: f178 (deep-backtrace.c:178)
+ by 0x........: f179 (deep-backtrace.c:179)
+ by 0x........: f180 (deep-backtrace.c:180)
+ by 0x........: f181 (deep-backtrace.c:181)
+ by 0x........: f182 (deep-backtrace.c:182)
+ by 0x........: f183 (deep-backtrace.c:183)
+ by 0x........: f184 (deep-backtrace.c:184)
+ by 0x........: f185 (deep-backtrace.c:185)
+ by 0x........: f186 (deep-backtrace.c:186)
+ by 0x........: f187 (deep-backtrace.c:187)
+ by 0x........: f188 (deep-backtrace.c:188)
+ by 0x........: f189 (deep-backtrace.c:189)
+ by 0x........: f190 (deep-backtrace.c:190)
+ by 0x........: f191 (deep-backtrace.c:191)
+ by 0x........: f192 (deep-backtrace.c:192)
+ by 0x........: f193 (deep-backtrace.c:193)
+ by 0x........: f194 (deep-backtrace.c:194)
+ by 0x........: f195 (deep-backtrace.c:195)
+ by 0x........: f196 (deep-backtrace.c:196)
+ by 0x........: f197 (deep-backtrace.c:197)
+ by 0x........: f198 (deep-backtrace.c:198)
+ by 0x........: f199 (deep-backtrace.c:199)
+ by 0x........: f200 (deep-backtrace.c:200)
+ by 0x........: f201 (deep-backtrace.c:201)
+ by 0x........: f202 (deep-backtrace.c:202)
+ by 0x........: f203 (deep-backtrace.c:203)
+ by 0x........: f204 (deep-backtrace.c:204)
+ by 0x........: f205 (deep-backtrace.c:205)
+ by 0x........: f206 (deep-backtrace.c:206)
+ by 0x........: f207 (deep-backtrace.c:207)
+ by 0x........: f208 (deep-backtrace.c:208)
+ by 0x........: f209 (deep-backtrace.c:209)
+ by 0x........: f210 (deep-backtrace.c:210)
+ by 0x........: f211 (deep-backtrace.c:211)
+ by 0x........: f212 (deep-backtrace.c:212)
+ by 0x........: f213 (deep-backtrace.c:213)
+ by 0x........: f214 (deep-backtrace.c:214)
+ by 0x........: f215 (deep-backtrace.c:215)
+ by 0x........: f216 (deep-backtrace.c:216)
+ by 0x........: f217 (deep-backtrace.c:217)
+ by 0x........: f218 (deep-backtrace.c:218)
+ by 0x........: f219 (deep-backtrace.c:219)
+ by 0x........: f220 (deep-backtrace.c:220)
+ by 0x........: f221 (deep-backtrace.c:221)
+ by 0x........: f222 (deep-backtrace.c:222)
+ by 0x........: f223 (deep-backtrace.c:223)
+ by 0x........: f224 (deep-backtrace.c:224)
+ by 0x........: f225 (deep-backtrace.c:225)
+ by 0x........: f226 (deep-backtrace.c:226)
+ by 0x........: f227 (deep-backtrace.c:227)
+ by 0x........: f228 (deep-backtrace.c:228)
+ by 0x........: f229 (deep-backtrace.c:229)
+ by 0x........: f230 (deep-backtrace.c:230)
+ by 0x........: f231 (deep-backtrace.c:231)
+ by 0x........: f232 (deep-backtrace.c:232)
+ by 0x........: f233 (deep-backtrace.c:233)
+ by 0x........: f234 (deep-backtrace.c:234)
+ by 0x........: f235 (deep-backtrace.c:235)
+ by 0x........: f236 (deep-backtrace.c:236)
+ by 0x........: f237 (deep-backtrace.c:237)
+ by 0x........: f238 (deep-backtrace.c:238)
+ by 0x........: f239 (deep-backtrace.c:239)
+ by 0x........: f240 (deep-backtrace.c:240)
+ by 0x........: f241 (deep-backtrace.c:241)
+ by 0x........: f242 (deep-backtrace.c:242)
+ by 0x........: f243 (deep-backtrace.c:243)
+ by 0x........: f244 (deep-backtrace.c:244)
+ by 0x........: f245 (deep-backtrace.c:245)
+ by 0x........: f246 (deep-backtrace.c:246)
+ by 0x........: f247 (deep-backtrace.c:247)
+ by 0x........: f248 (deep-backtrace.c:248)
+ by 0x........: f249 (deep-backtrace.c:249)
+ by 0x........: f250 (deep-backtrace.c:250)
+ by 0x........: f251 (deep-backtrace.c:251)
+ by 0x........: f252 (deep-backtrace.c:252)
+ by 0x........: f253 (deep-backtrace.c:253)
+ by 0x........: f254 (deep-backtrace.c:254)
+ by 0x........: f255 (deep-backtrace.c:255)
+ by 0x........: f256 (deep-backtrace.c:256)
+ by 0x........: f257 (deep-backtrace.c:257)
+ by 0x........: f258 (deep-backtrace.c:258)
+ by 0x........: f259 (deep-backtrace.c:259)
+ by 0x........: f260 (deep-backtrace.c:260)
+ by 0x........: f261 (deep-backtrace.c:261)
+ by 0x........: f262 (deep-backtrace.c:262)
+ by 0x........: f263 (deep-backtrace.c:263)
+ by 0x........: f264 (deep-backtrace.c:264)
+ by 0x........: f265 (deep-backtrace.c:265)
+ by 0x........: f266 (deep-backtrace.c:266)
+ by 0x........: f267 (deep-backtrace.c:267)
+ by 0x........: f268 (deep-backtrace.c:268)
+ by 0x........: f269 (deep-backtrace.c:269)
+ by 0x........: f270 (deep-backtrace.c:270)
+ by 0x........: f271 (deep-backtrace.c:271)
+ by 0x........: f272 (deep-backtrace.c:272)
+ by 0x........: f273 (deep-backtrace.c:273)
+ by 0x........: f274 (deep-backtrace.c:274)
+ by 0x........: f275 (deep-backtrace.c:275)
+ by 0x........: f276 (deep-backtrace.c:276)
+ by 0x........: f277 (deep-backtrace.c:277)
+ by 0x........: f278 (deep-backtrace.c:278)
+ by 0x........: f279 (deep-backtrace.c:279)
+ by 0x........: f280 (deep-backtrace.c:280)
+ by 0x........: f281 (deep-backtrace.c:281)
+ by 0x........: f282 (deep-backtrace.c:282)
+ by 0x........: f283 (deep-backtrace.c:283)
+ by 0x........: f284 (deep-backtrace.c:284)
+ by 0x........: f285 (deep-backtrace.c:285)
+ by 0x........: f286 (deep-backtrace.c:286)
+ by 0x........: f287 (deep-backtrace.c:287)
+ by 0x........: f288 (deep-backtrace.c:288)
+ by 0x........: f289 (deep-backtrace.c:289)
+ by 0x........: f290 (deep-backtrace.c:290)
+ by 0x........: f291 (deep-backtrace.c:291)
+ by 0x........: f292 (deep-backtrace.c:292)
+ by 0x........: f293 (deep-backtrace.c:293)
+ by 0x........: f294 (deep-backtrace.c:294)
+ by 0x........: f295 (deep-backtrace.c:295)
+ by 0x........: f296 (deep-backtrace.c:296)
+ by 0x........: f297 (deep-backtrace.c:297)
+ by 0x........: f298 (deep-backtrace.c:298)
+ by 0x........: f299 (deep-backtrace.c:299)
+ by 0x........: f300 (deep-backtrace.c:300)
+ by 0x........: f301 (deep-backtrace.c:301)
+ by 0x........: f302 (deep-backtrace.c:302)
+ by 0x........: f303 (deep-backtrace.c:303)
+ by 0x........: f304 (deep-backtrace.c:304)
+ by 0x........: f305 (deep-backtrace.c:305)
+ by 0x........: f306 (deep-backtrace.c:306)
+ by 0x........: f307 (deep-backtrace.c:307)
+ by 0x........: f308 (deep-backtrace.c:308)
+ by 0x........: f309 (deep-backtrace.c:309)
+ by 0x........: f310 (deep-backtrace.c:310)
+ by 0x........: f311 (deep-backtrace.c:311)
+ by 0x........: f312 (deep-backtrace.c:312)
+ by 0x........: f313 (deep-backtrace.c:313)
+ by 0x........: f314 (deep-backtrace.c:314)
+ by 0x........: f315 (deep-backtrace.c:315)
+ by 0x........: f316 (deep-backtrace.c:316)
+ by 0x........: f317 (deep-backtrace.c:317)
+ by 0x........: f318 (deep-backtrace.c:318)
+ by 0x........: f319 (deep-backtrace.c:319)
+ by 0x........: f320 (deep-backtrace.c:320)
+ by 0x........: f321 (deep-backtrace.c:321)
+ by 0x........: f322 (deep-backtrace.c:322)
+ by 0x........: f323 (deep-backtrace.c:323)
+ by 0x........: f324 (deep-backtrace.c:324)
+ by 0x........: f325 (deep-backtrace.c:325)
+ by 0x........: f326 (deep-backtrace.c:326)
+ by 0x........: f327 (deep-backtrace.c:327)
+ by 0x........: f328 (deep-backtrace.c:328)
+ by 0x........: f329 (deep-backtrace.c:329)
+ by 0x........: f330 (deep-backtrace.c:330)
+ by 0x........: f331 (deep-backtrace.c:331)
+ by 0x........: f332 (deep-backtrace.c:332)
+ by 0x........: f333 (deep-backtrace.c:333)
+ by 0x........: f334 (deep-backtrace.c:334)
+ by 0x........: f335 (deep-backtrace.c:335)
+ by 0x........: f336 (deep-backtrace.c:336)
+ by 0x........: f337 (deep-backtrace.c:337)
+ by 0x........: f338 (deep-backtrace.c:338)
+ by 0x........: f339 (deep-backtrace.c:339)
+ by 0x........: f340 (deep-backtrace.c:340)
+ by 0x........: f341 (deep-backtrace.c:341)
+ by 0x........: f342 (deep-backtrace.c:342)
+ by 0x........: f343 (deep-backtrace.c:343)
+ by 0x........: f344 (deep-backtrace.c:344)
+ by 0x........: f345 (deep-backtrace.c:345)
+ by 0x........: f346 (deep-backtrace.c:346)
+ by 0x........: f347 (deep-backtrace.c:347)
+ by 0x........: f348 (deep-backtrace.c:348)
+ by 0x........: f349 (deep-backtrace.c:349)
+ by 0x........: f350 (deep-backtrace.c:350)
+ by 0x........: f351 (deep-backtrace.c:351)
+ by 0x........: f352 (deep-backtrace.c:352)
+ by 0x........: f353 (deep-backtrace.c:353)
+ by 0x........: f354 (deep-backtrace.c:354)
+ by 0x........: f355 (deep-backtrace.c:355)
+ by 0x........: f356 (deep-backtrace.c:356)
+ by 0x........: f357 (deep-backtrace.c:357)
+ by 0x........: f358 (deep-backtrace.c:358)
+ by 0x........: f359 (deep-backtrace.c:359)
+ by 0x........: f360 (deep-backtrace.c:360)
+ by 0x........: f361 (deep-backtrace.c:361)
+ by 0x........: f362 (deep-backtrace.c:362)
+ by 0x........: f363 (deep-backtrace.c:363)
+ by 0x........: f364 (deep-backtrace.c:364)
+ by 0x........: f365 (deep-backtrace.c:365)
+ by 0x........: f366 (deep-backtrace.c:366)
+ by 0x........: f367 (deep-backtrace.c:367)
+ by 0x........: f368 (deep-backtrace.c:368)
+ by 0x........: f369 (deep-backtrace.c:369)
+ by 0x........: f370 (deep-backtrace.c:370)
+ by 0x........: f371 (deep-backtrace.c:371)
+ by 0x........: f372 (deep-backtrace.c:372)
+ by 0x........: f373 (deep-backtrace.c:373)
+ by 0x........: f374 (deep-backtrace.c:374)
+ by 0x........: f375 (deep-backtrace.c:375)
+ by 0x........: f376 (deep-backtrace.c:376)
+ by 0x........: f377 (deep-backtrace.c:377)
+ by 0x........: f378 (deep-backtrace.c:378)
+ by 0x........: f379 (deep-backtrace.c:379)
+ by 0x........: f380 (deep-backtrace.c:380)
+ by 0x........: f381 (deep-backtrace.c:381)
+ by 0x........: f382 (deep-backtrace.c:382)
+ by 0x........: f383 (deep-backtrace.c:383)
+ by 0x........: f384 (deep-backtrace.c:384)
+ by 0x........: f385 (deep-backtrace.c:385)
+ by 0x........: f386 (deep-backtrace.c:386)
+ by 0x........: f387 (deep-backtrace.c:387)
+ by 0x........: f388 (deep-backtrace.c:388)
+ by 0x........: f389 (deep-backtrace.c:389)
+ by 0x........: f390 (deep-backtrace.c:390)
+ by 0x........: f391 (deep-backtrace.c:391)
+ by 0x........: f392 (deep-backtrace.c:392)
+ by 0x........: f393 (deep-backtrace.c:393)
+ by 0x........: f394 (deep-backtrace.c:394)
+ by 0x........: f395 (deep-backtrace.c:395)
+ by 0x........: f396 (deep-backtrace.c:396)
+ by 0x........: f397 (deep-backtrace.c:397)
+ by 0x........: f398 (deep-backtrace.c:398)
+ by 0x........: f399 (deep-backtrace.c:399)
+ by 0x........: f400 (deep-backtrace.c:400)
+ by 0x........: f401 (deep-backtrace.c:401)
+ by 0x........: f402 (deep-backtrace.c:402)
+ by 0x........: f403 (deep-backtrace.c:403)
+ by 0x........: f404 (deep-backtrace.c:404)
+ by 0x........: f405 (deep-backtrace.c:405)
+ by 0x........: f406 (deep-backtrace.c:406)
+ by 0x........: f407 (deep-backtrace.c:407)
+ by 0x........: f408 (deep-backtrace.c:408)
+ by 0x........: f409 (deep-backtrace.c:409)
+ by 0x........: f410 (deep-backtrace.c:410)
+ by 0x........: f411 (deep-backtrace.c:411)
+ by 0x........: f412 (deep-backtrace.c:412)
+ by 0x........: f413 (deep-backtrace.c:413)
+ by 0x........: f414 (deep-backtrace.c:414)
+ by 0x........: f415 (deep-backtrace.c:415)
+ by 0x........: f416 (deep-backtrace.c:416)
+ by 0x........: f417 (deep-backtrace.c:417)
+ by 0x........: f418 (deep-backtrace.c:418)
+ by 0x........: f419 (deep-backtrace.c:419)
+ by 0x........: f420 (deep-backtrace.c:420)
+ by 0x........: f421 (deep-backtrace.c:421)
+ by 0x........: f422 (deep-backtrace.c:422)
+ by 0x........: f423 (deep-backtrace.c:423)
+ by 0x........: f424 (deep-backtrace.c:424)
+ by 0x........: f425 (deep-backtrace.c:425)
+ by 0x........: f426 (deep-backtrace.c:426)
+ by 0x........: f427 (deep-backtrace.c:427)
+ by 0x........: f428 (deep-backtrace.c:428)
+ by 0x........: f429 (deep-backtrace.c:429)
+ by 0x........: f430 (deep-backtrace.c:430)
+ by 0x........: f431 (deep-backtrace.c:431)
+ by 0x........: f432 (deep-backtrace.c:432)
+ by 0x........: f433 (deep-backtrace.c:433)
+ by 0x........: f434 (deep-backtrace.c:434)
+ by 0x........: f435 (deep-backtrace.c:435)
+ by 0x........: f436 (deep-backtrace.c:436)
+ by 0x........: f437 (deep-backtrace.c:437)
+ by 0x........: f438 (deep-backtrace.c:438)
+ by 0x........: f439 (deep-backtrace.c:439)
+ by 0x........: f440 (deep-backtrace.c:440)
+ by 0x........: f441 (deep-backtrace.c:441)
+ by 0x........: f442 (deep-backtrace.c:442)
+ by 0x........: f443 (deep-backtrace.c:443)
+ by 0x........: f444 (deep-backtrace.c:444)
+ by 0x........: f445 (deep-backtrace.c:445)
+ by 0x........: f446 (deep-backtrace.c:446)
+ by 0x........: f447 (deep-backtrace.c:447)
+ by 0x........: f448 (deep-backtrace.c:448)
+ by 0x........: f449 (deep-backtrace.c:449)
+ by 0x........: f450 (deep-backtrace.c:450)
+ by 0x........: f451 (deep-backtrace.c:451)
+ by 0x........: f452 (deep-backtrace.c:452)
+ by 0x........: f453 (deep-backtrace.c:453)
+ by 0x........: f454 (deep-backtrace.c:454)
+ by 0x........: f455 (deep-backtrace.c:455)
+ by 0x........: f456 (deep-backtrace.c:456)
+ by 0x........: f457 (deep-backtrace.c:457)
+ by 0x........: f458 (deep-backtrace.c:458)
+ by 0x........: f459 (deep-backtrace.c:459)
+ by 0x........: f460 (deep-backtrace.c:460)
+ by 0x........: f461 (deep-backtrace.c:461)
+ by 0x........: f462 (deep-backtrace.c:462)
+ by 0x........: f463 (deep-backtrace.c:463)
+ by 0x........: f464 (deep-backtrace.c:464)
+ by 0x........: f465 (deep-backtrace.c:465)
+ by 0x........: f466 (deep-backtrace.c:466)
+ by 0x........: f467 (deep-backtrace.c:467)
+ by 0x........: f468 (deep-backtrace.c:468)
+ by 0x........: f469 (deep-backtrace.c:469)
+ by 0x........: f470 (deep-backtrace.c:470)
+ by 0x........: f471 (deep-backtrace.c:471)
+ by 0x........: f472 (deep-backtrace.c:472)
+ by 0x........: f473 (deep-backtrace.c:473)
+ by 0x........: f474 (deep-backtrace.c:474)
+ by 0x........: f475 (deep-backtrace.c:475)
+ by 0x........: f476 (deep-backtrace.c:476)
+ by 0x........: f477 (deep-backtrace.c:477)
+ by 0x........: f478 (deep-backtrace.c:478)
+ by 0x........: f479 (deep-backtrace.c:479)
+ by 0x........: f480 (deep-backtrace.c:480)
+ by 0x........: f481 (deep-backtrace.c:481)
+ by 0x........: f482 (deep-backtrace.c:482)
+ by 0x........: f483 (deep-backtrace.c:483)
+ by 0x........: f484 (deep-backtrace.c:484)
+ by 0x........: f485 (deep-backtrace.c:485)
+ by 0x........: f486 (deep-backtrace.c:486)
+ by 0x........: f487 (deep-backtrace.c:487)
+ by 0x........: f488 (deep-backtrace.c:488)
+ by 0x........: f489 (deep-backtrace.c:489)
+ by 0x........: f490 (deep-backtrace.c:490)
+ by 0x........: f491 (deep-backtrace.c:491)
+ by 0x........: f492 (deep-backtrace.c:492)
+ by 0x........: f493 (deep-backtrace.c:493)
+ by 0x........: f494 (deep-backtrace.c:494)
+ by 0x........: f495 (deep-backtrace.c:495)
+ by 0x........: f496 (deep-backtrace.c:496)
+ by 0x........: f497 (deep-backtrace.c:497)
+ by 0x........: f498 (deep-backtrace.c:498)
+ by 0x........: main (deep-backtrace.c:499)
+ If you believe this happened as a result of a stack
+ overflow in your program's main thread (unlikely but
+ possible), you can try to increase the size of the
+ main thread stack using the --main-stacksize= flag.
+ The main thread stack size used in this run was ....
diff --git a/main/memcheck/tests/deep-backtrace.vgtest b/main/memcheck/tests/deep-backtrace.vgtest
new file mode 100644
index 0000000..ebeccf9
--- /dev/null
+++ b/main/memcheck/tests/deep-backtrace.vgtest
@@ -0,0 +1,2 @@
+prog: deep-backtrace
+vgopts: -q --num-callers=500
diff --git a/main/memcheck/tests/dw4.c b/main/memcheck/tests/dw4.c
new file mode 100644
index 0000000..8aac54d
--- /dev/null
+++ b/main/memcheck/tests/dw4.c
@@ -0,0 +1,54 @@
+
+/* Check of variable location identification when using .debug_types. */
+
+/* Relevant compile flags are:
+
+ -Wall -g -I$prefix/include/valgrind -gdwarf-4 -fdebug-types-section
+
+ eg -Wall -g -I`pwd`/Inst/include/valgrind -gdwarf-4 -fdebug-types-section
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "memcheck/memcheck.h"
+
+/* Cause memcheck to complain about the address "a" and so to print
+ its best guess as to what "a" actually is. a must be
+ addressible. */
+
+void croak ( void* aV )
+{
+ char* a = (char*)aV;
+ char* undefp = malloc(1);
+ char saved = *a;
+ assert(undefp);
+ *a = *undefp;
+ VALGRIND_CHECK_MEM_IS_DEFINED(a, 1);
+ *a = saved;
+ free(undefp);
+}
+
+struct s1
+{
+ char c;
+ short s;
+ int i;
+ long l;
+ float f;
+ double d;
+};
+
+struct s1 S2[30];
+
+int main ( void )
+{
+ struct s1 local;
+ struct s1* onheap = malloc(sizeof (struct s1));
+ assert(onheap);
+ croak(&onheap->i);
+
+ croak( &S2[0].i );
+ croak( &local.i );
+ return 0;
+}
diff --git a/main/memcheck/tests/dw4.stderr.exp b/main/memcheck/tests/dw4.stderr.exp
new file mode 100644
index 0000000..192ad0e
--- /dev/null
+++ b/main/memcheck/tests/dw4.stderr.exp
@@ -0,0 +1,19 @@
+Uninitialised byte(s) found during client check request
+ at 0x........: croak (dw4.c:27)
+ by 0x........: main (dw4.c:49)
+ Address 0x........ is 4 bytes inside a block of size 32 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (dw4.c:47)
+
+Uninitialised byte(s) found during client check request
+ at 0x........: croak (dw4.c:27)
+ by 0x........: main (dw4.c:51)
+ Location 0x........ is 0 bytes inside S2[0].i,
+ a global variable declared at dw4.c:42
+
+Uninitialised byte(s) found during client check request
+ at 0x........: croak (dw4.c:27)
+ by 0x........: main (dw4.c:52)
+ Location 0x........ is 0 bytes inside local.i,
+ declared at dw4.c:46, in frame #1 of thread 1
+
diff --git a/main/memcheck/tests/amd64/int3-amd64.stdout.exp b/main/memcheck/tests/dw4.stdout.exp
similarity index 100%
rename from main/memcheck/tests/amd64/int3-amd64.stdout.exp
rename to main/memcheck/tests/dw4.stdout.exp
diff --git a/main/memcheck/tests/dw4.vgtest b/main/memcheck/tests/dw4.vgtest
new file mode 100644
index 0000000..e904dbd
--- /dev/null
+++ b/main/memcheck/tests/dw4.vgtest
@@ -0,0 +1,3 @@
+prereq: test -e dw4
+prog: dw4
+vgopts: --read-var-info=yes -q
diff --git a/main/memcheck/tests/execve2.stderr.exp-kfail b/main/memcheck/tests/execve2.stderr.exp-kfail
new file mode 100644
index 0000000..9e86cbd
--- /dev/null
+++ b/main/memcheck/tests/execve2.stderr.exp-kfail
@@ -0,0 +1,4 @@
+Syscall param execve(filename) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
diff --git a/main/memcheck/tests/filter_leak_cases_possible b/main/memcheck/tests/filter_leak_cases_possible
index 4d77990..bc3722e 100755
--- a/main/memcheck/tests/filter_leak_cases_possible
+++ b/main/memcheck/tests/filter_leak_cases_possible
@@ -1,8 +1,4 @@
#! /bin/sh
-./filter_stderr |
-sed -e 's/^leaked.*$//' -e 's/^dubious.*$//' -e 's/^reachable.*$//' -e 's/^suppressed:.*$//'
-#! /bin/sh
-
./filter_stderr "$@" |
sed -e 's/^leaked.*$//' -e 's/^dubious.*$//' -e 's/^reachable.*$//' -e 's/^suppressed:.*$//'
diff --git a/main/memcheck/tests/fwrite.stderr.exp-kfail b/main/memcheck/tests/fwrite.stderr.exp-kfail
new file mode 100644
index 0000000..01cac98
--- /dev/null
+++ b/main/memcheck/tests/fwrite.stderr.exp-kfail
@@ -0,0 +1,6 @@
+Syscall param write(buf) points to uninitialised byte(s)
+ ...
+ Address 0x........ is 0 bytes inside a block of size 10 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (fwrite.c:7)
+
diff --git a/main/memcheck/tests/leak-cases-possible.stderr.exp b/main/memcheck/tests/leak-cases-possible.stderr.exp
index 4e94206..78ad60f 100644
--- a/main/memcheck/tests/leak-cases-possible.stderr.exp
+++ b/main/memcheck/tests/leak-cases-possible.stderr.exp
@@ -20,25 +20,3 @@
by 0x........: f (leak-cases.c:91)
by 0x........: main (leak-cases.c:107)
-
-
-
-
-16 bytes in 1 blocks are definitely lost in loss record ... of ...
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: mk (leak-cases.c:52)
- by 0x........: f (leak-cases.c:74)
- by 0x........: main (leak-cases.c:107)
-
-32 (16 direct, 16 indirect) bytes in 1 blocks are definitely lost in loss record ... of ...
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: mk (leak-cases.c:52)
- by 0x........: f (leak-cases.c:76)
- by 0x........: main (leak-cases.c:107)
-
-32 (16 direct, 16 indirect) bytes in 1 blocks are definitely lost in loss record ... of ...
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: mk (leak-cases.c:52)
- by 0x........: f (leak-cases.c:91)
- by 0x........: main (leak-cases.c:107)
-
diff --git a/main/memcheck/tests/leak-cases-possible.vgtest b/main/memcheck/tests/leak-cases-possible.vgtest
index e9d7d51..54c80e5 100644
--- a/main/memcheck/tests/leak-cases-possible.vgtest
+++ b/main/memcheck/tests/leak-cases-possible.vgtest
@@ -1,7 +1,4 @@
prog: leak-cases
vgopts: -q --leak-check=full --leak-resolution=high --show-possibly-lost=no
stderr_filter: filter_leak_cases_possible
-prog: leak-cases
-vgopts: -q --leak-check=full --leak-resolution=high --show-possibly-lost=no
-stderr_filter: filter_leak_cases_possible
stderr_filter_args: leak-cases.c
diff --git a/main/memcheck/tests/linux/Makefile.in b/main/memcheck/tests/linux/Makefile.in
new file mode 100644
index 0000000..d38ad6e
--- /dev/null
+++ b/main/memcheck/tests/linux/Makefile.in
@@ -0,0 +1,779 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = brk$(EXEEXT) capget$(EXEEXT) lsframe1$(EXEEXT) \
+ lsframe2$(EXEEXT) sigqueue$(EXEEXT) stack_changes$(EXEEXT) \
+ stack_switch$(EXEEXT) syscalls-2007$(EXEEXT) \
+ syslog-syscall$(EXEEXT) timerfd-syscall$(EXEEXT)
+subdir = memcheck/tests/linux
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+brk_SOURCES = brk.c
+brk_OBJECTS = brk.$(OBJEXT)
+brk_LDADD = $(LDADD)
+capget_SOURCES = capget.c
+capget_OBJECTS = capget.$(OBJEXT)
+capget_LDADD = $(LDADD)
+lsframe1_SOURCES = lsframe1.c
+lsframe1_OBJECTS = lsframe1.$(OBJEXT)
+lsframe1_LDADD = $(LDADD)
+lsframe2_SOURCES = lsframe2.c
+lsframe2_OBJECTS = lsframe2.$(OBJEXT)
+lsframe2_LDADD = $(LDADD)
+sigqueue_SOURCES = sigqueue.c
+sigqueue_OBJECTS = sigqueue.$(OBJEXT)
+sigqueue_LDADD = $(LDADD)
+stack_changes_SOURCES = stack_changes.c
+stack_changes_OBJECTS = stack_changes.$(OBJEXT)
+stack_changes_LDADD = $(LDADD)
+stack_switch_SOURCES = stack_switch.c
+stack_switch_OBJECTS = stack_switch.$(OBJEXT)
+stack_switch_DEPENDENCIES =
+syscalls_2007_SOURCES = syscalls-2007.c
+syscalls_2007_OBJECTS = syscalls-2007.$(OBJEXT)
+syscalls_2007_LDADD = $(LDADD)
+syslog_syscall_SOURCES = syslog-syscall.c
+syslog_syscall_OBJECTS = syslog-syscall.$(OBJEXT)
+syslog_syscall_LDADD = $(LDADD)
+timerfd_syscall_SOURCES = timerfd-syscall.c
+timerfd_syscall_OBJECTS = timerfd-syscall.$(OBJEXT)
+timerfd_syscall_DEPENDENCIES =
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = brk.c capget.c lsframe1.c lsframe2.c sigqueue.c \
+ stack_changes.c stack_switch.c syscalls-2007.c \
+ syslog-syscall.c timerfd-syscall.c
+DIST_SOURCES = brk.c capget.c lsframe1.c lsframe2.c sigqueue.c \
+ stack_changes.c stack_switch.c syscalls-2007.c \
+ syslog-syscall.c timerfd-syscall.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ brk.stderr.exp brk.vgtest \
+ capget.vgtest capget.stderr.exp capget.stderr.exp2 \
+ lsframe1.vgtest lsframe1.stdout.exp lsframe1.stderr.exp \
+ lsframe2.vgtest lsframe2.stdout.exp lsframe2.stderr.exp \
+ sigqueue.vgtest sigqueue.stderr.exp \
+ stack_changes.stderr.exp stack_changes.stdout.exp \
+ stack_changes.stdout.exp2 stack_changes.vgtest \
+ stack_switch.stderr.exp stack_switch.vgtest \
+ syscalls-2007.vgtest syscalls-2007.stderr.exp \
+ syslog-syscall.vgtest syslog-syscall.stderr.exp \
+ timerfd-syscall.vgtest timerfd-syscall.stderr.exp \
+ with-space.stderr.exp with-space.stdout.exp with-space.vgtest
+
+stack_switch_LDADD = -lpthread
+timerfd_syscall_LDADD = -lrt
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/linux/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/linux/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+brk$(EXEEXT): $(brk_OBJECTS) $(brk_DEPENDENCIES)
+ @rm -f brk$(EXEEXT)
+ $(LINK) $(brk_OBJECTS) $(brk_LDADD) $(LIBS)
+capget$(EXEEXT): $(capget_OBJECTS) $(capget_DEPENDENCIES)
+ @rm -f capget$(EXEEXT)
+ $(LINK) $(capget_OBJECTS) $(capget_LDADD) $(LIBS)
+lsframe1$(EXEEXT): $(lsframe1_OBJECTS) $(lsframe1_DEPENDENCIES)
+ @rm -f lsframe1$(EXEEXT)
+ $(LINK) $(lsframe1_OBJECTS) $(lsframe1_LDADD) $(LIBS)
+lsframe2$(EXEEXT): $(lsframe2_OBJECTS) $(lsframe2_DEPENDENCIES)
+ @rm -f lsframe2$(EXEEXT)
+ $(LINK) $(lsframe2_OBJECTS) $(lsframe2_LDADD) $(LIBS)
+sigqueue$(EXEEXT): $(sigqueue_OBJECTS) $(sigqueue_DEPENDENCIES)
+ @rm -f sigqueue$(EXEEXT)
+ $(LINK) $(sigqueue_OBJECTS) $(sigqueue_LDADD) $(LIBS)
+stack_changes$(EXEEXT): $(stack_changes_OBJECTS) $(stack_changes_DEPENDENCIES)
+ @rm -f stack_changes$(EXEEXT)
+ $(LINK) $(stack_changes_OBJECTS) $(stack_changes_LDADD) $(LIBS)
+stack_switch$(EXEEXT): $(stack_switch_OBJECTS) $(stack_switch_DEPENDENCIES)
+ @rm -f stack_switch$(EXEEXT)
+ $(LINK) $(stack_switch_OBJECTS) $(stack_switch_LDADD) $(LIBS)
+syscalls-2007$(EXEEXT): $(syscalls_2007_OBJECTS) $(syscalls_2007_DEPENDENCIES)
+ @rm -f syscalls-2007$(EXEEXT)
+ $(LINK) $(syscalls_2007_OBJECTS) $(syscalls_2007_LDADD) $(LIBS)
+syslog-syscall$(EXEEXT): $(syslog_syscall_OBJECTS) $(syslog_syscall_DEPENDENCIES)
+ @rm -f syslog-syscall$(EXEEXT)
+ $(LINK) $(syslog_syscall_OBJECTS) $(syslog_syscall_LDADD) $(LIBS)
+timerfd-syscall$(EXEEXT): $(timerfd_syscall_OBJECTS) $(timerfd_syscall_DEPENDENCIES)
+ @rm -f timerfd-syscall$(EXEEXT)
+ $(LINK) $(timerfd_syscall_OBJECTS) $(timerfd_syscall_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/brk.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/capget.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lsframe1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lsframe2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigqueue.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stack_changes.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stack_switch.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syscalls-2007.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syslog-syscall.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/timerfd-syscall.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/linux/capget.stderr.exp2 b/main/memcheck/tests/linux/capget.stderr.exp2
new file mode 100644
index 0000000..7aef7a2
--- /dev/null
+++ b/main/memcheck/tests/linux/capget.stderr.exp2
@@ -0,0 +1,15 @@
+
+Running as root
+capget result:
+effective 0x........
+permitted 0x........
+inheritable 0
+
+HEAP SUMMARY:
+ in use at exit: ... bytes in ... blocks
+ total heap usage: ... allocs, ... frees, ... bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/linux/syscalls-2007.c b/main/memcheck/tests/linux/syscalls-2007.c
new file mode 100644
index 0000000..b61c6d5
--- /dev/null
+++ b/main/memcheck/tests/linux/syscalls-2007.c
@@ -0,0 +1,83 @@
+/**
+ * Test program for some Linux syscalls introduced during 2006 and 2007:
+ * - epoll_pwait() was introduced in the 2.6.19 kernel, released in November
+ * 2006.
+ * - utimensat(), eventfd(), timerfd() and signalfd() were introduced in the
+ * 2.6.22 kernel, released in July 2007.
+ *
+ * See also http://bugs.kde.org/show_bug.cgi?id=160907.
+ */
+
+#define _GNU_SOURCE
+
+#include "../../config.h"
+#include <fcntl.h>
+#include <signal.h>
+#include <stdint.h>
+#if defined(HAVE_SYS_EPOLL_H)
+#include <sys/epoll.h>
+#endif
+#if defined(HAVE_SYS_EVENTFD_H)
+#include <sys/eventfd.h>
+#endif
+#if defined(HAVE_SYS_POLL_H)
+#include <sys/poll.h>
+#endif
+#if defined(HAVE_SYS_SIGNALFD_H)
+#include <sys/signalfd.h>
+#endif
+#include <sys/stat.h>
+#include <unistd.h>
+
+int main (void)
+{
+#if defined(HAVE_SIGNALFD) && defined(HAVE_EVENTFD) \
+ && defined(HAVE_EVENTFD_READ) && defined(HAVE_PPOLL)
+ {
+ sigset_t mask;
+ int fd, fd2;
+ eventfd_t ev;
+ struct timespec ts = { .tv_sec = 1, .tv_nsec = 0 };
+ struct pollfd pfd[2];
+
+ sigemptyset (&mask);
+ sigaddset (&mask, SIGUSR1);
+ fd = signalfd (-1, &mask, 0);
+ sigaddset (&mask, SIGUSR2);
+ fd = signalfd (fd, &mask, 0);
+ fd2 = eventfd (5, 0);
+ eventfd_read (fd2, &ev);
+ pfd[0].fd = fd;
+ pfd[0].events = POLLIN|POLLOUT;
+ pfd[1].fd = fd2;
+ pfd[1].events = POLLIN|POLLOUT;
+ ppoll (pfd, 2, &ts, &mask);
+ }
+#endif
+
+#if defined(HAVE_UTIMENSAT)
+ unlink("/tmp/valgrind-utimensat-test");
+ close (creat ("/tmp/valgrind-utimensat-test", S_IRUSR | S_IWUSR));
+ {
+ struct timespec ts2[2] = { [0].tv_sec = 10000000, [1].tv_sec = 20000000 };
+ utimensat (AT_FDCWD, "/tmp/valgrind-utimensat-test", ts2, 0);
+ }
+ unlink("/tmp/valgrind-utimensat-test");
+#endif
+
+#if defined(HAVE_EPOLL_CREATE) && defined(HAVE_EPOLL_PWAIT)
+ {
+ int fd3;
+ struct epoll_event evs[10];
+ sigset_t mask;
+
+ sigemptyset (&mask);
+ sigaddset (&mask, SIGUSR1);
+ sigaddset (&mask, SIGUSR2);
+ fd3 = epoll_create (10);
+ epoll_pwait (fd3, evs, 10, 0, &mask);
+ }
+#endif
+
+ return 0;
+}
diff --git a/main/memcheck/tests/linux/syscalls-2007.stderr.exp b/main/memcheck/tests/linux/syscalls-2007.stderr.exp
new file mode 100644
index 0000000..d0330e5
--- /dev/null
+++ b/main/memcheck/tests/linux/syscalls-2007.stderr.exp
@@ -0,0 +1,10 @@
+
+
+HEAP SUMMARY:
+ in use at exit: ... bytes in ... blocks
+ total heap usage: ... allocs, ... frees, ... bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/linux/syscalls-2007.vgtest b/main/memcheck/tests/linux/syscalls-2007.vgtest
new file mode 100644
index 0000000..7ba82c4
--- /dev/null
+++ b/main/memcheck/tests/linux/syscalls-2007.vgtest
@@ -0,0 +1,2 @@
+prog: syscalls-2007
+stderr_filter: ../filter_allocs
diff --git a/main/memcheck/tests/linux/syslog-syscall.c b/main/memcheck/tests/linux/syslog-syscall.c
new file mode 100644
index 0000000..1143722
--- /dev/null
+++ b/main/memcheck/tests/linux/syslog-syscall.c
@@ -0,0 +1,23 @@
+/** Test program for the syslog() system call.
+ * From the syslog(2) man page:
+ * If you need the libc function syslog() (which talks to syslogd(8)),
+ * then look at syslog(3). The system call of this name is about control-
+ * ling the kernel printk() buffer, and the glibc version is called
+ * klogctl().
+ */
+
+#include "../../config.h"
+#include <stdio.h>
+#if defined(HAVE_SYS_KLOG_H)
+#include <sys/klog.h>
+#endif
+
+int main(int argc, char** argv)
+{
+ int number_of_unread_characters;
+#if defined HAVE_KLOGCTL
+ number_of_unread_characters = klogctl(9, 0, 0);
+#endif
+ fprintf(stderr, "Done.\n");
+ return 0 * number_of_unread_characters;
+}
diff --git a/main/memcheck/tests/linux/syslog-syscall.stderr.exp b/main/memcheck/tests/linux/syslog-syscall.stderr.exp
new file mode 100644
index 0000000..c8fe7b9
--- /dev/null
+++ b/main/memcheck/tests/linux/syslog-syscall.stderr.exp
@@ -0,0 +1,11 @@
+
+Done.
+
+HEAP SUMMARY:
+ in use at exit: ... bytes in ... blocks
+ total heap usage: ... allocs, ... frees, ... bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/linux/syslog-syscall.vgtest b/main/memcheck/tests/linux/syslog-syscall.vgtest
new file mode 100644
index 0000000..c96ccf1
--- /dev/null
+++ b/main/memcheck/tests/linux/syslog-syscall.vgtest
@@ -0,0 +1,2 @@
+prog: syslog-syscall
+stderr_filter: ../filter_allocs
diff --git a/main/memcheck/tests/linux/timerfd-syscall.stdout.exp b/main/memcheck/tests/linux/timerfd-syscall.stdout.exp
deleted file mode 100644
index e69de29..0000000
--- a/main/memcheck/tests/linux/timerfd-syscall.stdout.exp
+++ /dev/null
diff --git a/main/memcheck/tests/match-overrun.supp b/main/memcheck/tests/match-overrun.supp
index 2f5893c..1a7271f 100644
--- a/main/memcheck/tests/match-overrun.supp
+++ b/main/memcheck/tests/match-overrun.supp
@@ -1,4 +1,19 @@
{
+ nonmatching1
+ Memcheck:Addr4
+ fun:a123456789*
+ fun:nonmatching
+ fun:main
+}
+{
+ nonmatching2
+ Memcheck:Addr4
+ fun:a123456789*
+ fun:main
+ fun:nonmatching
+}
+
+{
test
Memcheck:Addr4
fun:a123456789*
diff --git a/main/memcheck/tests/memalign2.c b/main/memcheck/tests/memalign2.c
index 12aa047..b35a70e 100644
--- a/main/memcheck/tests/memalign2.c
+++ b/main/memcheck/tests/memalign2.c
@@ -76,6 +76,8 @@
p = memalign(4096, 100); assert(0 == (long)p % 4096);
p = memalign(4097, 100); assert(0 == (long)p % 8192);
+ p = memalign(4 * 1024 * 1024, 100); assert(0 == (long)p % (4 * 1024 * 1024));
+ p = memalign(16 * 1024 * 1024, 100); assert(0 == (long)p % (16 * 1024 * 1024));
# define PM(a,b,c) posix_memalign((void**)a, b, c)
@@ -88,15 +90,17 @@
assert(0 == res && 0 == (long)p % sizeof(void*));
res = PM(&p, 31, 100); assert(EINVAL == res);
- res = PM(&p, 32, 100); assert(0 == res &&
- 0 == (long)p % 32);
+ res = PM(&p, 32, 100); assert(0 == res && 0 == (long)p % 32);
res = PM(&p, 33, 100); assert(EINVAL == res);
res = PM(&p, 4095, 100); assert(EINVAL == res);
- res = PM(&p, 4096, 100); assert(0 == res &&
- 0 == (long)p % 4096);
+ res = PM(&p, 4096, 100); assert(0 == res && 0 == (long)p % 4096);
res = PM(&p, 4097, 100); assert(EINVAL == res);
+ res = PM(&p, 4 * 1024 * 1024, 100); assert(0 == res
+ && 0 == (long)p % (4 * 1024 * 1024));
+ res = PM(&p, 16 * 1024 * 1024, 100); assert(0 == res
+ && 0 == (long)p % (16 * 1024 * 1024));
# endif
return 0;
diff --git a/main/memcheck/tests/memalign_test.c b/main/memcheck/tests/memalign_test.c
index a9c8784..38e165d 100644
--- a/main/memcheck/tests/memalign_test.c
+++ b/main/memcheck/tests/memalign_test.c
@@ -10,7 +10,7 @@
int i;
unsigned long pszB = sysconf(_SC_PAGE_SIZE);
assert(sizeof(long) == sizeof(void*));
- assert(pszB == 4096 || pszB == 65536);
+ assert(pszB == 4096 || pszB == 16384 || pszB == 65536);
for (i = 0; i < 10; i++) {
a[i] = valloc(11111 * (i+1));
diff --git a/main/memcheck/tests/mempool2.c b/main/memcheck/tests/mempool2.c
index 9404ade..256ff05 100644
--- a/main/memcheck/tests/mempool2.c
+++ b/main/memcheck/tests/mempool2.c
@@ -158,6 +158,28 @@
"\n------ double free in mmap-backed pool ------\n\n");
VALGRIND_MEMPOOL_FREE(p2, x2);
+ {
+ // test that redzone are still protected even if the user forgets
+ // to mark the superblock noaccess.
+ char superblock[100];
+
+ VALGRIND_CREATE_MEMPOOL(superblock, REDZONE_SIZE, 0);
+ // User should mark the superblock no access to benefit
+ // from full Valgrind memcheck protection.
+ // VALGRIND_MEMPOOL_ALLOC will however still ensure the
+ // redzones are protected.
+ VALGRIND_MEMPOOL_ALLOC(superblock, superblock+30, 10);
+
+ res += superblock[30]; // valid
+ res += superblock[39]; // valid
+
+ fprintf(stderr,
+ "\n------ 2 invalid access in 'no no-access superblock' ---\n\n");
+ res += superblock[29]; // invalid
+ res += superblock[40]; // invalid
+
+ VALGRIND_DESTROY_MEMPOOL(superblock);
+ }
// claim res is used, so gcc can't nuke this all
__asm__ __volatile__("" : : "r"(res));
diff --git a/main/memcheck/tests/mempool2.stderr.exp b/main/memcheck/tests/mempool2.stderr.exp
index 76d84ad..4426018 100644
--- a/main/memcheck/tests/mempool2.stderr.exp
+++ b/main/memcheck/tests/mempool2.stderr.exp
@@ -3,57 +3,57 @@
Invalid read of size 1
at 0x........: test (mempool2.c:135)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Address 0x........ is 1 bytes before a block of size 10 client-defined
at 0x........: allocate (mempool2.c:108)
by 0x........: test (mempool2.c:130)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Invalid read of size 1
at 0x........: test (mempool2.c:136)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Address 0x........ is 0 bytes after a block of size 10 client-defined
at 0x........: allocate (mempool2.c:108)
by 0x........: test (mempool2.c:130)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
------ out of range reads in mmap-backed pool ------
Invalid read of size 1
at 0x........: test (mempool2.c:140)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Address 0x........ is 1 bytes before a block of size 20 client-defined
at 0x........: allocate (mempool2.c:108)
by 0x........: test (mempool2.c:131)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Invalid read of size 1
at 0x........: test (mempool2.c:141)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Address 0x........ is 0 bytes after a block of size 20 client-defined
at 0x........: allocate (mempool2.c:108)
by 0x........: test (mempool2.c:131)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
------ read free in malloc-backed pool ------
Illegal memory pool address
at 0x........: test (mempool2.c:145)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Address 0x........ is 0 bytes inside a block of size 32 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: make_pool (mempool2.c:46)
by 0x........: test (mempool2.c:122)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
------ read free in mmap-backed pool ------
Illegal memory pool address
at 0x........: test (mempool2.c:150)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
@@ -61,21 +61,38 @@
Illegal memory pool address
at 0x........: test (mempool2.c:155)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Address 0x........ is 0 bytes inside a block of size 32 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: make_pool (mempool2.c:46)
by 0x........: test (mempool2.c:122)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
------ double free in mmap-backed pool ------
Illegal memory pool address
at 0x........: test (mempool2.c:159)
- by 0x........: main (mempool2.c:174)
+ by 0x........: main (mempool2.c:196)
Address 0x........ is not stack'd, malloc'd or (recently) free'd
+------ 2 invalid access in 'no no-access superblock' ---
+
+Invalid read of size 1
+ at 0x........: test (mempool2.c:178)
+ by 0x........: main (mempool2.c:196)
+ Address 0x........ is 1 bytes before a block of size 10 client-defined
+ at 0x........: test (mempool2.c:171)
+ by 0x........: main (mempool2.c:196)
+
+Invalid read of size 1
+ at 0x........: test (mempool2.c:179)
+ by 0x........: main (mempool2.c:196)
+ Address 0x........ is 0 bytes after a block of size 10 client-defined
+ at 0x........: test (mempool2.c:171)
+ by 0x........: main (mempool2.c:196)
+
+
------ done ------
diff --git a/main/memcheck/tests/nanoleak.supp b/main/memcheck/tests/nanoleak.supp
index 731ca6a..0724f58 100644
--- a/main/memcheck/tests/nanoleak.supp
+++ b/main/memcheck/tests/nanoleak.supp
@@ -1,7 +1,7 @@
{
this_is_the_nanoleak_suppression_name
Memcheck:Leak
- fun:malloc
+ fun:m?lloc
fun:main
}
diff --git a/main/memcheck/tests/origin5-bz2.c b/main/memcheck/tests/origin5-bz2.c
index 7c79882..45006eb 100644
--- a/main/memcheck/tests/origin5-bz2.c
+++ b/main/memcheck/tests/origin5-bz2.c
@@ -4651,7 +4651,7 @@
/*---------------------------------------------------*/
-static
+static __attribute__((noinline))
Bool copy_input_until_stop ( EState* s )
{
Bool progress_in = False;
diff --git a/main/memcheck/tests/origin5-bz2.stderr.exp-glibc212-s390x b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc212-s390x
new file mode 100644
index 0000000..bc21245
--- /dev/null
+++ b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc212-s390x
@@ -0,0 +1,136 @@
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: main (origin5-bz2.c:6481)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2820)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2823)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2854)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2858)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2859)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2963)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2964)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: fallbackSort (origin5-bz2.c:2269)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3116)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: fallbackSort (origin5-bz2.c:2275)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3116)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: main (origin5-bz2.c:6512)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
diff --git a/main/memcheck/tests/origin5-bz2.stderr.exp-glibc234-s390x b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc234-s390x
new file mode 100644
index 0000000..ea6481d
--- /dev/null
+++ b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc234-s390x
@@ -0,0 +1,125 @@
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: main (origin5-bz2.c:6481)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2820)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2823)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2854)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2858)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2963)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: mainSort (origin5-bz2.c:2964)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: fallbackSort (origin5-bz2.c:2269)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3116)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Use of uninitialised value of size 8
+ at 0x........: fallbackSort (origin5-bz2.c:2275)
+ by 0x........: BZ2_blockSort (origin5-bz2.c:3116)
+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034)
+ by 0x........: handle_compress (origin5-bz2.c:4753)
+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
+ by 0x........: main (origin5-bz2.c:6484)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: main (origin5-bz2.c:6512)
+ Uninitialised value was created by a client request
+ at 0x........: main (origin5-bz2.c:6479)
+
diff --git a/main/memcheck/tests/origin5-bz2.stderr.exp-glibc25-amd64 b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc25-amd64
index 32b90da..ea6481d 100644
--- a/main/memcheck/tests/origin5-bz2.stderr.exp-glibc25-amd64
+++ b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc25-amd64
@@ -4,7 +4,8 @@
at 0x........: main (origin5-bz2.c:6479)
Conditional jump or move depends on uninitialised value(s)
- at 0x........: handle_compress (origin5-bz2.c:4686)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
@@ -12,7 +13,8 @@
at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
- at 0x........: handle_compress (origin5-bz2.c:4686)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
@@ -20,7 +22,8 @@
at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 8
- at 0x........: handle_compress (origin5-bz2.c:4686)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
diff --git a/main/memcheck/tests/origin5-bz2.stderr.exp-glibc25-x86 b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc25-x86
index 1044e4a..49e1b4c 100644
--- a/main/memcheck/tests/origin5-bz2.stderr.exp-glibc25-x86
+++ b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc25-x86
@@ -4,7 +4,8 @@
at 0x........: main (origin5-bz2.c:6479)
Conditional jump or move depends on uninitialised value(s)
- at 0x........: handle_compress (origin5-bz2.c:4686)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
@@ -12,7 +13,8 @@
at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 4
- at 0x........: handle_compress (origin5-bz2.c:4686)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
@@ -20,7 +22,8 @@
at 0x........: main (origin5-bz2.c:6479)
Use of uninitialised value of size 4
- at 0x........: handle_compress (origin5-bz2.c:4686)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
diff --git a/main/memcheck/tests/origin5-bz2.stderr.exp-glibc27-ppc64 b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc27-ppc64
index e0958e4..cd1a70d 100644
--- a/main/memcheck/tests/origin5-bz2.stderr.exp-glibc27-ppc64
+++ b/main/memcheck/tests/origin5-bz2.stderr.exp-glibc27-ppc64
@@ -4,7 +4,8 @@
at 0x........: main (origin5-bz2.c:6481)
Conditional jump or move depends on uninitialised value(s)
- at 0x........: handle_compress (origin5-bz2.c:4686)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
@@ -12,7 +13,8 @@
at 0x........: main (origin5-bz2.c:6481)
Use of uninitialised value of size 8
- at 0x........: handle_compress (origin5-bz2.c:4686)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
@@ -20,7 +22,8 @@
at 0x........: main (origin5-bz2.c:6481)
Use of uninitialised value of size 8
- at 0x........: handle_compress (origin5-bz2.c:4686)
+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686)
+ by 0x........: handle_compress (origin5-bz2.c:4750)
by 0x........: BZ2_bzCompress (origin5-bz2.c:4822)
by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630)
by 0x........: main (origin5-bz2.c:6484)
diff --git a/main/memcheck/tests/partial_load_dflt.stderr.expr-s390x-mvc b/main/memcheck/tests/partial_load_dflt.stderr.expr-s390x-mvc
new file mode 100644
index 0000000..250cc57
--- /dev/null
+++ b/main/memcheck/tests/partial_load_dflt.stderr.expr-s390x-mvc
@@ -0,0 +1,34 @@
+
+Invalid read of size 1
+ at 0x........: main (partial_load.c:16)
+ Address 0x........ is 0 bytes after a block of size 7 alloc'd
+ at 0x........: calloc (vg_replace_malloc.c:...)
+ by 0x........: main (partial_load.c:14)
+
+Invalid read of size 8
+ at 0x........: main (partial_load.c:23)
+ Address 0x........ is 1 bytes inside a block of size 8 alloc'd
+ at 0x........: calloc (vg_replace_malloc.c:...)
+ by 0x........: main (partial_load.c:20)
+
+Invalid read of size 2
+ at 0x........: main (partial_load.c:30)
+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
+ at 0x........: calloc (vg_replace_malloc.c:...)
+ by 0x........: main (partial_load.c:28)
+
+Invalid read of size 8
+ at 0x........: main (partial_load.c:37)
+ Address 0x........ is 0 bytes inside a block of size 8 free'd
+ at 0x........: free (vg_replace_malloc.c:...)
+ by 0x........: main (partial_load.c:36)
+
+
+HEAP SUMMARY:
+ in use at exit: ... bytes in ... blocks
+ total heap usage: ... allocs, ... frees, ... bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+ERROR SUMMARY: 4 errors from 4 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/partiallydefinedeq.stderr.exp3 b/main/memcheck/tests/partiallydefinedeq.stderr.exp3
new file mode 100644
index 0000000..227c060
--- /dev/null
+++ b/main/memcheck/tests/partiallydefinedeq.stderr.exp3
@@ -0,0 +1,20 @@
+
+On s390 we might see 2 or 3 errors.
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: foo (partiallydefinedeq.c:15)
+ by 0x........: main (partiallydefinedeq.c:37)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: foo (partiallydefinedeq.c:15)
+ by 0x........: main (partiallydefinedeq.c:52)
+
+
+HEAP SUMMARY:
+ in use at exit: ... bytes in ... blocks
+ total heap usage: ... allocs, ... frees, ... bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+Use --track-origins=yes to see where uninitialised values come from
+ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/partiallydefinedeq.stderr.exp4 b/main/memcheck/tests/partiallydefinedeq.stderr.exp4
new file mode 100644
index 0000000..adfe8a9
--- /dev/null
+++ b/main/memcheck/tests/partiallydefinedeq.stderr.exp4
@@ -0,0 +1,24 @@
+
+On s390 we might see 2 or 3 errors.
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: foo (partiallydefinedeq.c:15)
+ by 0x........: main (partiallydefinedeq.c:37)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: foo (partiallydefinedeq.c:15)
+ by 0x........: main (partiallydefinedeq.c:45)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: foo (partiallydefinedeq.c:15)
+ by 0x........: main (partiallydefinedeq.c:52)
+
+
+HEAP SUMMARY:
+ in use at exit: ... bytes in ... blocks
+ total heap usage: ... allocs, ... frees, ... bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+Use --track-origins=yes to see where uninitialised values come from
+ERROR SUMMARY: 3 errors from 3 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/ppc32/Makefile.in b/main/memcheck/tests/ppc32/Makefile.in
new file mode 100644
index 0000000..17f526e
--- /dev/null
+++ b/main/memcheck/tests/ppc32/Makefile.in
@@ -0,0 +1,715 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = power_ISA2_05$(EXEEXT)
+subdir = memcheck/tests/ppc32
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+power_ISA2_05_SOURCES = power_ISA2_05.c
+power_ISA2_05_OBJECTS = power_ISA2_05-power_ISA2_05.$(OBJEXT)
+power_ISA2_05_LDADD = $(LDADD)
+power_ISA2_05_LINK = $(CCLD) $(power_ISA2_05_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = power_ISA2_05.c
+DIST_SOURCES = power_ISA2_05.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = $(noinst_SCRIPTS) \
+ power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest
+
+power_ISA2_05_CFLAGS = $(AM_CFLAGS) $(WERROR) -Winline -Wall -Wshadow -g \
+ -I$(top_srcdir)/include @FLAG_M32@
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/ppc32/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/ppc32/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+power_ISA2_05$(EXEEXT): $(power_ISA2_05_OBJECTS) $(power_ISA2_05_DEPENDENCIES)
+ @rm -f power_ISA2_05$(EXEEXT)
+ $(power_ISA2_05_LINK) $(power_ISA2_05_OBJECTS) $(power_ISA2_05_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/power_ISA2_05-power_ISA2_05.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+power_ISA2_05-power_ISA2_05.o: power_ISA2_05.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(power_ISA2_05_CFLAGS) $(CFLAGS) -MT power_ISA2_05-power_ISA2_05.o -MD -MP -MF $(DEPDIR)/power_ISA2_05-power_ISA2_05.Tpo -c -o power_ISA2_05-power_ISA2_05.o `test -f 'power_ISA2_05.c' || echo '$(srcdir)/'`power_ISA2_05.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/power_ISA2_05-power_ISA2_05.Tpo $(DEPDIR)/power_ISA2_05-power_ISA2_05.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='power_ISA2_05.c' object='power_ISA2_05-power_ISA2_05.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(power_ISA2_05_CFLAGS) $(CFLAGS) -c -o power_ISA2_05-power_ISA2_05.o `test -f 'power_ISA2_05.c' || echo '$(srcdir)/'`power_ISA2_05.c
+
+power_ISA2_05-power_ISA2_05.obj: power_ISA2_05.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(power_ISA2_05_CFLAGS) $(CFLAGS) -MT power_ISA2_05-power_ISA2_05.obj -MD -MP -MF $(DEPDIR)/power_ISA2_05-power_ISA2_05.Tpo -c -o power_ISA2_05-power_ISA2_05.obj `if test -f 'power_ISA2_05.c'; then $(CYGPATH_W) 'power_ISA2_05.c'; else $(CYGPATH_W) '$(srcdir)/power_ISA2_05.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/power_ISA2_05-power_ISA2_05.Tpo $(DEPDIR)/power_ISA2_05-power_ISA2_05.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='power_ISA2_05.c' object='power_ISA2_05-power_ISA2_05.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(power_ISA2_05_CFLAGS) $(CFLAGS) -c -o power_ISA2_05-power_ISA2_05.obj `if test -f 'power_ISA2_05.c'; then $(CYGPATH_W) 'power_ISA2_05.c'; else $(CYGPATH_W) '$(srcdir)/power_ISA2_05.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/ppc32/filter_stderr b/main/memcheck/tests/ppc32/filter_stderr
index e58b720..a778e97 100755
--- a/main/memcheck/tests/ppc32/filter_stderr
+++ b/main/memcheck/tests/ppc32/filter_stderr
@@ -1,15 +1,3 @@
#! /bin/sh
-../filter_stderr
-#! /bin/sh
-
-../filter_stderr
-#! /bin/sh
-
-../filter_stderr
-#! /bin/sh
-
-../filter_stderr
-#! /bin/sh
-
../filter_stderr "$@"
diff --git a/main/memcheck/tests/ppc32/power_ISA2_05.c b/main/memcheck/tests/ppc32/power_ISA2_05.c
index b122f96..f85b547 100644
--- a/main/memcheck/tests/ppc32/power_ISA2_05.c
+++ b/main/memcheck/tests/ppc32/power_ISA2_05.c
@@ -40,7 +40,7 @@
void test_lfiwax()
{
unsigned long base;
- unsigned long offset;
+ // unsigned long offset;
typedef struct {
unsigned int hi;
@@ -50,9 +50,8 @@
int_pair_t *ip;
foo = -1024.0;
base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
+
+ __asm__ volatile ("lfiwax %0, 0, %1":"=f" (FRT1):"r"(base));
ip = (int_pair_t *) & FRT1;
printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
@@ -66,7 +65,7 @@
** FPp+1= rightmost 64 bits stored at DS(RA)
** FPp must be an even float register
*/
-int test_double_pair_instrs()
+void test_double_pair_instrs()
{
typedef struct {
double hi;
@@ -75,14 +74,6 @@
/* the following decls are for alignment */
int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
unsigned long base;
unsigned long offset;
@@ -130,11 +121,6 @@
__asm__ volatile ("stfdpx 10, 20, 21");
printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
}
@@ -170,11 +156,10 @@
}
/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
+void test_reservation()
{
int RT;
- int i, j;
unsigned long base;
unsigned long offset;
long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
@@ -193,835 +178,7 @@
__asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
printf("ldarx => %x\n", RT);
#endif
- return i + j;
-}
-
-int main(void)
-{
- (void) test_reservation();
- test_fcpsgn();
- (void) test_double_pair_instrs();
- test_lfiwax();
- test_parity_instrs();
- return 0;
-}
-#include <stdio.h>
-
-double foo = -1.0;
-double FRT1;
-double FRT2;
-int base256(int val)
-{
-/* interpret the bitstream representing val as a base 256 number for testing
- * the parity instrs
- */
- int sum = 0;
- int scale = 1;
- int i;
-
- for (i = 0; i < 8; i++) {
- int bit = val & 1;
- sum = sum + bit * scale;
- val <<= 1;
- scale *= 256;
- }
- return sum;
-}
-
-void test_parity_instrs()
-{
- unsigned long long_word;
- unsigned int word;
- int i, parity;
-
- for (i = 0; i < 50; i++) {
- word = base256(i);
- long_word = word;
- __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word));
- printf("prtyd (%x) => parity=%x\n", i, parity);
- __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word));
- printf("prtyw (%x) => parity=%x\n", i, parity);
- }
-}
-
-void test_lfiwax()
-{
- unsigned long base;
- unsigned long offset;
-
- typedef struct {
- unsigned int hi;
- unsigned int lo;
- } int_pair_t;
-
- int_pair_t *ip;
- foo = -1024.0;
- base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
- ip = (int_pair_t *) & FRT1;
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
-
-
-}
-
-
-
-/* lfdp FPp, DS(RA) : load float double pair
-** FPp = leftmost 64 bits stored at DS(RA)
-** FPp+1= rightmost 64 bits stored at DS(RA)
-** FPp must be an even float register
-*/
-int test_double_pair_instrs()
-{
- typedef struct {
- double hi;
- double lo;
- } dbl_pair_t;
-
- /* the following decls are for alignment */
- int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
- dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
- unsigned long base;
- unsigned long offset;
-
- for (i = 0; i < 3; i++) {
- dbl_pair[i].hi = -1024.0 + i;
- dbl_pair[i].lo = 1024.0 + i + 1;
- }
-
- __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2);
-
-
- FRT1 = 2.2048;
- FRT2 = -4.1024;
- __asm__ volatile ("fmr 10, %0"::"f" (FRT1));
- __asm__ volatile ("fmr 11, %0"::"f" (FRT2));
- __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1]));
- printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo);
-
- FRT1 = 0.0;
- FRT2 = -1.0;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lfdpx 10, 20, 21");
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2);
-
- FRT1 = 8.2048;
- FRT2 = -16.1024;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[2] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- __asm__ volatile ("stfdpx 10, 20, 21");
- printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
-}
-
-
-/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
-void test_fcpsgn()
-{
- double A[] = {
- 10.101010,
- -0.0,
- 0.0,
- -10.101010
- };
-
- double B[] = {
- 11.111111,
- -0.0,
- 0.0,
- -11.111111
- };
-
- double FRT, FRA, FRB;
- int i, j;
-
- for (i = 0; i < 4; i++) {
- FRA = A[i];
- for (j = 0; j < 4; j++) {
- FRB = B[j];
- __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
- "f"(FRB));
- printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);
- }
- }
-}
-
-/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
-{
-
- int RT;
- int i, j;
- unsigned long base;
- unsigned long offset;
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
-
-
- base = (unsigned long) &arr;
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
- printf("lwarx => %x\n", RT);
-
-#ifdef __powerpc64__
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
- printf("ldarx => %x\n", RT);
-#endif
- return i + j;
-}
-
-int main(void)
-{
- (void) test_reservation();
- test_fcpsgn();
- (void) test_double_pair_instrs();
- test_lfiwax();
- test_parity_instrs();
- return 0;
-}
-#include <stdio.h>
-
-double foo = -1.0;
-double FRT1;
-double FRT2;
-int base256(int val)
-{
-/* interpret the bitstream representing val as a base 256 number for testing
- * the parity instrs
- */
- int sum = 0;
- int scale = 1;
- int i;
-
- for (i = 0; i < 8; i++) {
- int bit = val & 1;
- sum = sum + bit * scale;
- val <<= 1;
- scale *= 256;
- }
- return sum;
-}
-
-void test_parity_instrs()
-{
- unsigned long long_word;
- unsigned int word;
- int i, parity;
-
- for (i = 0; i < 50; i++) {
- word = base256(i);
- long_word = word;
- __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word));
- printf("prtyd (%x) => parity=%x\n", i, parity);
- __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word));
- printf("prtyw (%x) => parity=%x\n", i, parity);
- }
-}
-
-void test_lfiwax()
-{
- unsigned long base;
- unsigned long offset;
-
- typedef struct {
- unsigned int hi;
- unsigned int lo;
- } int_pair_t;
-
- int_pair_t *ip;
- foo = -1024.0;
- base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
- ip = (int_pair_t *) & FRT1;
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
-
-
-}
-
-
-
-/* lfdp FPp, DS(RA) : load float double pair
-** FPp = leftmost 64 bits stored at DS(RA)
-** FPp+1= rightmost 64 bits stored at DS(RA)
-** FPp must be an even float register
-*/
-int test_double_pair_instrs()
-{
- typedef struct {
- double hi;
- double lo;
- } dbl_pair_t;
-
- /* the following decls are for alignment */
- int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
- dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
- unsigned long base;
- unsigned long offset;
-
- for (i = 0; i < 3; i++) {
- dbl_pair[i].hi = -1024.0 + i;
- dbl_pair[i].lo = 1024.0 + i + 1;
- }
-
- __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2);
-
-
- FRT1 = 2.2048;
- FRT2 = -4.1024;
- __asm__ volatile ("fmr 10, %0"::"f" (FRT1));
- __asm__ volatile ("fmr 11, %0"::"f" (FRT2));
- __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1]));
- printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo);
-
- FRT1 = 0.0;
- FRT2 = -1.0;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lfdpx 10, 20, 21");
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2);
-
- FRT1 = 8.2048;
- FRT2 = -16.1024;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[2] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- __asm__ volatile ("stfdpx 10, 20, 21");
- printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
-}
-
-
-/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
-void test_fcpsgn()
-{
- double A[] = {
- 10.101010,
- -0.0,
- 0.0,
- -10.101010
- };
-
- double B[] = {
- 11.111111,
- -0.0,
- 0.0,
- -11.111111
- };
-
- double FRT, FRA, FRB;
- int i, j;
-
- for (i = 0; i < 4; i++) {
- FRA = A[i];
- for (j = 0; j < 4; j++) {
- FRB = B[j];
- __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
- "f"(FRB));
- printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);
- }
- }
-}
-
-/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
-{
-
- int RT;
- int i, j;
- unsigned long base;
- unsigned long offset;
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
-
-
- base = (unsigned long) &arr;
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
- printf("lwarx => %x\n", RT);
-
-#ifdef __powerpc64__
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
- printf("ldarx => %x\n", RT);
-#endif
- return i + j;
-}
-
-int main(void)
-{
- (void) test_reservation();
- test_fcpsgn();
- (void) test_double_pair_instrs();
- test_lfiwax();
- test_parity_instrs();
- return 0;
-}
-#include <stdio.h>
-
-double foo = -1.0;
-double FRT1;
-double FRT2;
-int base256(int val)
-{
-/* interpret the bitstream representing val as a base 256 number for testing
- * the parity instrs
- */
- int sum = 0;
- int scale = 1;
- int i;
-
- for (i = 0; i < 8; i++) {
- int bit = val & 1;
- sum = sum + bit * scale;
- val <<= 1;
- scale *= 256;
- }
- return sum;
-}
-
-void test_parity_instrs()
-{
- unsigned long long_word;
- unsigned int word;
- int i, parity;
-
- for (i = 0; i < 50; i++) {
- word = base256(i);
- long_word = word;
- __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word));
- printf("prtyd (%x) => parity=%x\n", i, parity);
- __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word));
- printf("prtyw (%x) => parity=%x\n", i, parity);
- }
-}
-
-void test_lfiwax()
-{
- unsigned long base;
- unsigned long offset;
-
- typedef struct {
- unsigned int hi;
- unsigned int lo;
- } int_pair_t;
-
- int_pair_t *ip;
- foo = -1024.0;
- base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
- ip = (int_pair_t *) & FRT1;
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
-
-
-}
-
-
-
-/* lfdp FPp, DS(RA) : load float double pair
-** FPp = leftmost 64 bits stored at DS(RA)
-** FPp+1= rightmost 64 bits stored at DS(RA)
-** FPp must be an even float register
-*/
-int test_double_pair_instrs()
-{
- typedef struct {
- double hi;
- double lo;
- } dbl_pair_t;
-
- /* the following decls are for alignment */
- int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
- dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
- unsigned long base;
- unsigned long offset;
-
- for (i = 0; i < 3; i++) {
- dbl_pair[i].hi = -1024.0 + i;
- dbl_pair[i].lo = 1024.0 + i + 1;
- }
-
- __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2);
-
-
- FRT1 = 2.2048;
- FRT2 = -4.1024;
- __asm__ volatile ("fmr 10, %0"::"f" (FRT1));
- __asm__ volatile ("fmr 11, %0"::"f" (FRT2));
- __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1]));
- printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo);
-
- FRT1 = 0.0;
- FRT2 = -1.0;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lfdpx 10, 20, 21");
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2);
-
- FRT1 = 8.2048;
- FRT2 = -16.1024;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[2] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- __asm__ volatile ("stfdpx 10, 20, 21");
- printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
-}
-
-
-/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
-void test_fcpsgn()
-{
- double A[] = {
- 10.101010,
- -0.0,
- 0.0,
- -10.101010
- };
-
- double B[] = {
- 11.111111,
- -0.0,
- 0.0,
- -11.111111
- };
-
- double FRT, FRA, FRB;
- int i, j;
-
- for (i = 0; i < 4; i++) {
- FRA = A[i];
- for (j = 0; j < 4; j++) {
- FRB = B[j];
- __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
- "f"(FRB));
- printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);
- }
- }
-}
-
-/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
-{
-
- int RT;
- int i, j;
- unsigned long base;
- unsigned long offset;
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
-
-
- base = (unsigned long) &arr;
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
- printf("lwarx => %x\n", RT);
-
-#ifdef __powerpc64__
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
- printf("ldarx => %x\n", RT);
-#endif
- return i + j;
-}
-
-int main(void)
-{
- (void) test_reservation();
- test_fcpsgn();
- (void) test_double_pair_instrs();
- test_lfiwax();
- test_parity_instrs();
- return 0;
-}
-#include <stdio.h>
-
-double foo = -1.0;
-double FRT1;
-double FRT2;
-int base256(int val)
-{
-/* interpret the bitstream representing val as a base 256 number for testing
- * the parity instrs
- */
- int sum = 0;
- int scale = 1;
- int i;
-
- for (i = 0; i < 8; i++) {
- int bit = val & 1;
- sum = sum + bit * scale;
- val <<= 1;
- scale *= 256;
- }
- return sum;
-}
-
-void test_parity_instrs()
-{
- unsigned long long_word;
- unsigned int word;
- int i, parity;
-
- for (i = 0; i < 50; i++) {
- word = base256(i);
- long_word = word;
- __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word));
- printf("prtyd (%x) => parity=%x\n", i, parity);
- __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word));
- printf("prtyw (%x) => parity=%x\n", i, parity);
- }
-}
-
-void test_lfiwax()
-{
- unsigned long base;
- unsigned long offset;
-
- typedef struct {
- unsigned int hi;
- unsigned int lo;
- } int_pair_t;
-
- int_pair_t *ip;
- foo = -1024.0;
- base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
- ip = (int_pair_t *) & FRT1;
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
-
-
-}
-
-
-
-/* lfdp FPp, DS(RA) : load float double pair
-** FPp = leftmost 64 bits stored at DS(RA)
-** FPp+1= rightmost 64 bits stored at DS(RA)
-** FPp must be an even float register
-*/
-int test_double_pair_instrs()
-{
- typedef struct {
- double hi;
- double lo;
- } dbl_pair_t;
-
- /* the following decls are for alignment */
- int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
- dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
- unsigned long base;
- unsigned long offset;
-
- for (i = 0; i < 3; i++) {
- dbl_pair[i].hi = -1024.0 + i;
- dbl_pair[i].lo = 1024.0 + i + 1;
- }
-
- __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2);
-
-
- FRT1 = 2.2048;
- FRT2 = -4.1024;
- __asm__ volatile ("fmr 10, %0"::"f" (FRT1));
- __asm__ volatile ("fmr 11, %0"::"f" (FRT2));
- __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1]));
- printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo);
-
- FRT1 = 0.0;
- FRT2 = -1.0;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lfdpx 10, 20, 21");
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2);
-
- FRT1 = 8.2048;
- FRT2 = -16.1024;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[2] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- __asm__ volatile ("stfdpx 10, 20, 21");
- printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
-}
-
-
-/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
-void test_fcpsgn()
-{
- double A[] = {
- 10.101010,
- -0.0,
- 0.0,
- -10.101010
- };
-
- double B[] = {
- 11.111111,
- -0.0,
- 0.0,
- -11.111111
- };
-
- double FRT, FRA, FRB;
- int i, j;
-
- for (i = 0; i < 4; i++) {
- FRA = A[i];
- for (j = 0; j < 4; j++) {
- FRB = B[j];
- __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
- "f"(FRB));
- printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);
- }
- }
-}
-
-/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
-{
-
- int RT;
- int i, j;
- unsigned long base;
- unsigned long offset;
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
-
-
- base = (unsigned long) &arr;
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
- printf("lwarx => %x\n", RT);
-#ifdef __powerpc64__
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
- printf("ldarx => %x\n", RT);
-#endif
- return i + j;
}
int main(void)
diff --git a/main/memcheck/tests/ppc32/power_ISA2_05.stderr.exp b/main/memcheck/tests/ppc32/power_ISA2_05.stderr.exp
index 543b8f8..c22dd7f 100644
--- a/main/memcheck/tests/ppc32/power_ISA2_05.stderr.exp
+++ b/main/memcheck/tests/ppc32/power_ISA2_05.stderr.exp
@@ -8,43 +8,3 @@
For counts of detected and suppressed errors, rerun with: -v
ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
-
-
-HEAP SUMMARY:
- in use at exit: 0 bytes in 0 blocks
- total heap usage: 0 allocs, 0 frees, 0 bytes allocated
-
-For a detailed leak analysis, rerun with: --leak-check=full
-
-For counts of detected and suppressed errors, rerun with: -v
-ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
-
-
-HEAP SUMMARY:
- in use at exit: 0 bytes in 0 blocks
- total heap usage: 0 allocs, 0 frees, 0 bytes allocated
-
-For a detailed leak analysis, rerun with: --leak-check=full
-
-For counts of detected and suppressed errors, rerun with: -v
-ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
-
-
-HEAP SUMMARY:
- in use at exit: 0 bytes in 0 blocks
- total heap usage: 0 allocs, 0 frees, 0 bytes allocated
-
-For a detailed leak analysis, rerun with: --leak-check=full
-
-For counts of detected and suppressed errors, rerun with: -v
-ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
-
-
-HEAP SUMMARY:
- in use at exit: 0 bytes in 0 blocks
- total heap usage: 0 allocs, 0 frees, 0 bytes allocated
-
-For a detailed leak analysis, rerun with: --leak-check=full
-
-For counts of detected and suppressed errors, rerun with: -v
-ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/ppc32/power_ISA2_05.stdout.exp b/main/memcheck/tests/ppc32/power_ISA2_05.stdout.exp
index 2f6ddf1..5513960 100644
--- a/main/memcheck/tests/ppc32/power_ISA2_05.stdout.exp
+++ b/main/memcheck/tests/ppc32/power_ISA2_05.stdout.exp
@@ -120,491 +120,3 @@
prtyw (30) => parity=0
prtyd (31) => parity=1
prtyw (31) => parity=1
-lwarx => bad0beef
-fcpsgn sign=10.101010, base=11.111111 => 11.111111
-fcpsgn sign=10.101010, base=-0.000000 => 0.000000
-fcpsgn sign=10.101010, base=0.000000 => 0.000000
-fcpsgn sign=10.101010, base=-11.111111 => 11.111111
-fcpsgn sign=-0.000000, base=11.111111 => -11.111111
-fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
-fcpsgn sign=0.000000, base=11.111111 => 11.111111
-fcpsgn sign=0.000000, base=-0.000000 => 0.000000
-fcpsgn sign=0.000000, base=0.000000 => 0.000000
-fcpsgn sign=0.000000, base=-11.111111 => 11.111111
-fcpsgn sign=-10.101010, base=11.111111 => -11.111111
-fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
-lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
-stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
-prtyd (0) => parity=0
-prtyw (0) => parity=0
-prtyd (1) => parity=1
-prtyw (1) => parity=1
-prtyd (2) => parity=0
-prtyw (2) => parity=0
-prtyd (3) => parity=1
-prtyw (3) => parity=1
-prtyd (4) => parity=0
-prtyw (4) => parity=0
-prtyd (5) => parity=1
-prtyw (5) => parity=1
-prtyd (6) => parity=0
-prtyw (6) => parity=0
-prtyd (7) => parity=1
-prtyw (7) => parity=1
-prtyd (8) => parity=0
-prtyw (8) => parity=0
-prtyd (9) => parity=1
-prtyw (9) => parity=1
-prtyd (a) => parity=0
-prtyw (a) => parity=0
-prtyd (b) => parity=1
-prtyw (b) => parity=1
-prtyd (c) => parity=0
-prtyw (c) => parity=0
-prtyd (d) => parity=1
-prtyw (d) => parity=1
-prtyd (e) => parity=0
-prtyw (e) => parity=0
-prtyd (f) => parity=1
-prtyw (f) => parity=1
-prtyd (10) => parity=0
-prtyw (10) => parity=0
-prtyd (11) => parity=1
-prtyw (11) => parity=1
-prtyd (12) => parity=0
-prtyw (12) => parity=0
-prtyd (13) => parity=1
-prtyw (13) => parity=1
-prtyd (14) => parity=0
-prtyw (14) => parity=0
-prtyd (15) => parity=1
-prtyw (15) => parity=1
-prtyd (16) => parity=0
-prtyw (16) => parity=0
-prtyd (17) => parity=1
-prtyw (17) => parity=1
-prtyd (18) => parity=0
-prtyw (18) => parity=0
-prtyd (19) => parity=1
-prtyw (19) => parity=1
-prtyd (1a) => parity=0
-prtyw (1a) => parity=0
-prtyd (1b) => parity=1
-prtyw (1b) => parity=1
-prtyd (1c) => parity=0
-prtyw (1c) => parity=0
-prtyd (1d) => parity=1
-prtyw (1d) => parity=1
-prtyd (1e) => parity=0
-prtyw (1e) => parity=0
-prtyd (1f) => parity=1
-prtyw (1f) => parity=1
-prtyd (20) => parity=0
-prtyw (20) => parity=0
-prtyd (21) => parity=1
-prtyw (21) => parity=1
-prtyd (22) => parity=0
-prtyw (22) => parity=0
-prtyd (23) => parity=1
-prtyw (23) => parity=1
-prtyd (24) => parity=0
-prtyw (24) => parity=0
-prtyd (25) => parity=1
-prtyw (25) => parity=1
-prtyd (26) => parity=0
-prtyw (26) => parity=0
-prtyd (27) => parity=1
-prtyw (27) => parity=1
-prtyd (28) => parity=0
-prtyw (28) => parity=0
-prtyd (29) => parity=1
-prtyw (29) => parity=1
-prtyd (2a) => parity=0
-prtyw (2a) => parity=0
-prtyd (2b) => parity=1
-prtyw (2b) => parity=1
-prtyd (2c) => parity=0
-prtyw (2c) => parity=0
-prtyd (2d) => parity=1
-prtyw (2d) => parity=1
-prtyd (2e) => parity=0
-prtyw (2e) => parity=0
-prtyd (2f) => parity=1
-prtyw (2f) => parity=1
-prtyd (30) => parity=0
-prtyw (30) => parity=0
-prtyd (31) => parity=1
-prtyw (31) => parity=1
-lwarx => bad0beef
-fcpsgn sign=10.101010, base=11.111111 => 11.111111
-fcpsgn sign=10.101010, base=-0.000000 => 0.000000
-fcpsgn sign=10.101010, base=0.000000 => 0.000000
-fcpsgn sign=10.101010, base=-11.111111 => 11.111111
-fcpsgn sign=-0.000000, base=11.111111 => -11.111111
-fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
-fcpsgn sign=0.000000, base=11.111111 => 11.111111
-fcpsgn sign=0.000000, base=-0.000000 => 0.000000
-fcpsgn sign=0.000000, base=0.000000 => 0.000000
-fcpsgn sign=0.000000, base=-11.111111 => 11.111111
-fcpsgn sign=-10.101010, base=11.111111 => -11.111111
-fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
-lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
-stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
-prtyd (0) => parity=0
-prtyw (0) => parity=0
-prtyd (1) => parity=1
-prtyw (1) => parity=1
-prtyd (2) => parity=0
-prtyw (2) => parity=0
-prtyd (3) => parity=1
-prtyw (3) => parity=1
-prtyd (4) => parity=0
-prtyw (4) => parity=0
-prtyd (5) => parity=1
-prtyw (5) => parity=1
-prtyd (6) => parity=0
-prtyw (6) => parity=0
-prtyd (7) => parity=1
-prtyw (7) => parity=1
-prtyd (8) => parity=0
-prtyw (8) => parity=0
-prtyd (9) => parity=1
-prtyw (9) => parity=1
-prtyd (a) => parity=0
-prtyw (a) => parity=0
-prtyd (b) => parity=1
-prtyw (b) => parity=1
-prtyd (c) => parity=0
-prtyw (c) => parity=0
-prtyd (d) => parity=1
-prtyw (d) => parity=1
-prtyd (e) => parity=0
-prtyw (e) => parity=0
-prtyd (f) => parity=1
-prtyw (f) => parity=1
-prtyd (10) => parity=0
-prtyw (10) => parity=0
-prtyd (11) => parity=1
-prtyw (11) => parity=1
-prtyd (12) => parity=0
-prtyw (12) => parity=0
-prtyd (13) => parity=1
-prtyw (13) => parity=1
-prtyd (14) => parity=0
-prtyw (14) => parity=0
-prtyd (15) => parity=1
-prtyw (15) => parity=1
-prtyd (16) => parity=0
-prtyw (16) => parity=0
-prtyd (17) => parity=1
-prtyw (17) => parity=1
-prtyd (18) => parity=0
-prtyw (18) => parity=0
-prtyd (19) => parity=1
-prtyw (19) => parity=1
-prtyd (1a) => parity=0
-prtyw (1a) => parity=0
-prtyd (1b) => parity=1
-prtyw (1b) => parity=1
-prtyd (1c) => parity=0
-prtyw (1c) => parity=0
-prtyd (1d) => parity=1
-prtyw (1d) => parity=1
-prtyd (1e) => parity=0
-prtyw (1e) => parity=0
-prtyd (1f) => parity=1
-prtyw (1f) => parity=1
-prtyd (20) => parity=0
-prtyw (20) => parity=0
-prtyd (21) => parity=1
-prtyw (21) => parity=1
-prtyd (22) => parity=0
-prtyw (22) => parity=0
-prtyd (23) => parity=1
-prtyw (23) => parity=1
-prtyd (24) => parity=0
-prtyw (24) => parity=0
-prtyd (25) => parity=1
-prtyw (25) => parity=1
-prtyd (26) => parity=0
-prtyw (26) => parity=0
-prtyd (27) => parity=1
-prtyw (27) => parity=1
-prtyd (28) => parity=0
-prtyw (28) => parity=0
-prtyd (29) => parity=1
-prtyw (29) => parity=1
-prtyd (2a) => parity=0
-prtyw (2a) => parity=0
-prtyd (2b) => parity=1
-prtyw (2b) => parity=1
-prtyd (2c) => parity=0
-prtyw (2c) => parity=0
-prtyd (2d) => parity=1
-prtyw (2d) => parity=1
-prtyd (2e) => parity=0
-prtyw (2e) => parity=0
-prtyd (2f) => parity=1
-prtyw (2f) => parity=1
-prtyd (30) => parity=0
-prtyw (30) => parity=0
-prtyd (31) => parity=1
-prtyw (31) => parity=1
-lwarx => bad0beef
-fcpsgn sign=10.101010, base=11.111111 => 11.111111
-fcpsgn sign=10.101010, base=-0.000000 => 0.000000
-fcpsgn sign=10.101010, base=0.000000 => 0.000000
-fcpsgn sign=10.101010, base=-11.111111 => 11.111111
-fcpsgn sign=-0.000000, base=11.111111 => -11.111111
-fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
-fcpsgn sign=0.000000, base=11.111111 => 11.111111
-fcpsgn sign=0.000000, base=-0.000000 => 0.000000
-fcpsgn sign=0.000000, base=0.000000 => 0.000000
-fcpsgn sign=0.000000, base=-11.111111 => 11.111111
-fcpsgn sign=-10.101010, base=11.111111 => -11.111111
-fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
-lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
-stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
-prtyd (0) => parity=0
-prtyw (0) => parity=0
-prtyd (1) => parity=1
-prtyw (1) => parity=1
-prtyd (2) => parity=0
-prtyw (2) => parity=0
-prtyd (3) => parity=1
-prtyw (3) => parity=1
-prtyd (4) => parity=0
-prtyw (4) => parity=0
-prtyd (5) => parity=1
-prtyw (5) => parity=1
-prtyd (6) => parity=0
-prtyw (6) => parity=0
-prtyd (7) => parity=1
-prtyw (7) => parity=1
-prtyd (8) => parity=0
-prtyw (8) => parity=0
-prtyd (9) => parity=1
-prtyw (9) => parity=1
-prtyd (a) => parity=0
-prtyw (a) => parity=0
-prtyd (b) => parity=1
-prtyw (b) => parity=1
-prtyd (c) => parity=0
-prtyw (c) => parity=0
-prtyd (d) => parity=1
-prtyw (d) => parity=1
-prtyd (e) => parity=0
-prtyw (e) => parity=0
-prtyd (f) => parity=1
-prtyw (f) => parity=1
-prtyd (10) => parity=0
-prtyw (10) => parity=0
-prtyd (11) => parity=1
-prtyw (11) => parity=1
-prtyd (12) => parity=0
-prtyw (12) => parity=0
-prtyd (13) => parity=1
-prtyw (13) => parity=1
-prtyd (14) => parity=0
-prtyw (14) => parity=0
-prtyd (15) => parity=1
-prtyw (15) => parity=1
-prtyd (16) => parity=0
-prtyw (16) => parity=0
-prtyd (17) => parity=1
-prtyw (17) => parity=1
-prtyd (18) => parity=0
-prtyw (18) => parity=0
-prtyd (19) => parity=1
-prtyw (19) => parity=1
-prtyd (1a) => parity=0
-prtyw (1a) => parity=0
-prtyd (1b) => parity=1
-prtyw (1b) => parity=1
-prtyd (1c) => parity=0
-prtyw (1c) => parity=0
-prtyd (1d) => parity=1
-prtyw (1d) => parity=1
-prtyd (1e) => parity=0
-prtyw (1e) => parity=0
-prtyd (1f) => parity=1
-prtyw (1f) => parity=1
-prtyd (20) => parity=0
-prtyw (20) => parity=0
-prtyd (21) => parity=1
-prtyw (21) => parity=1
-prtyd (22) => parity=0
-prtyw (22) => parity=0
-prtyd (23) => parity=1
-prtyw (23) => parity=1
-prtyd (24) => parity=0
-prtyw (24) => parity=0
-prtyd (25) => parity=1
-prtyw (25) => parity=1
-prtyd (26) => parity=0
-prtyw (26) => parity=0
-prtyd (27) => parity=1
-prtyw (27) => parity=1
-prtyd (28) => parity=0
-prtyw (28) => parity=0
-prtyd (29) => parity=1
-prtyw (29) => parity=1
-prtyd (2a) => parity=0
-prtyw (2a) => parity=0
-prtyd (2b) => parity=1
-prtyw (2b) => parity=1
-prtyd (2c) => parity=0
-prtyw (2c) => parity=0
-prtyd (2d) => parity=1
-prtyw (2d) => parity=1
-prtyd (2e) => parity=0
-prtyw (2e) => parity=0
-prtyd (2f) => parity=1
-prtyw (2f) => parity=1
-prtyd (30) => parity=0
-prtyw (30) => parity=0
-prtyd (31) => parity=1
-prtyw (31) => parity=1
-lwarx => bad0beef
-fcpsgn sign=10.101010, base=11.111111 => 11.111111
-fcpsgn sign=10.101010, base=-0.000000 => 0.000000
-fcpsgn sign=10.101010, base=0.000000 => 0.000000
-fcpsgn sign=10.101010, base=-11.111111 => 11.111111
-fcpsgn sign=-0.000000, base=11.111111 => -11.111111
-fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
-fcpsgn sign=0.000000, base=11.111111 => 11.111111
-fcpsgn sign=0.000000, base=-0.000000 => 0.000000
-fcpsgn sign=0.000000, base=0.000000 => 0.000000
-fcpsgn sign=0.000000, base=-11.111111 => 11.111111
-fcpsgn sign=-10.101010, base=11.111111 => -11.111111
-fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
-lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
-stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
-prtyd (0) => parity=0
-prtyw (0) => parity=0
-prtyd (1) => parity=1
-prtyw (1) => parity=1
-prtyd (2) => parity=0
-prtyw (2) => parity=0
-prtyd (3) => parity=1
-prtyw (3) => parity=1
-prtyd (4) => parity=0
-prtyw (4) => parity=0
-prtyd (5) => parity=1
-prtyw (5) => parity=1
-prtyd (6) => parity=0
-prtyw (6) => parity=0
-prtyd (7) => parity=1
-prtyw (7) => parity=1
-prtyd (8) => parity=0
-prtyw (8) => parity=0
-prtyd (9) => parity=1
-prtyw (9) => parity=1
-prtyd (a) => parity=0
-prtyw (a) => parity=0
-prtyd (b) => parity=1
-prtyw (b) => parity=1
-prtyd (c) => parity=0
-prtyw (c) => parity=0
-prtyd (d) => parity=1
-prtyw (d) => parity=1
-prtyd (e) => parity=0
-prtyw (e) => parity=0
-prtyd (f) => parity=1
-prtyw (f) => parity=1
-prtyd (10) => parity=0
-prtyw (10) => parity=0
-prtyd (11) => parity=1
-prtyw (11) => parity=1
-prtyd (12) => parity=0
-prtyw (12) => parity=0
-prtyd (13) => parity=1
-prtyw (13) => parity=1
-prtyd (14) => parity=0
-prtyw (14) => parity=0
-prtyd (15) => parity=1
-prtyw (15) => parity=1
-prtyd (16) => parity=0
-prtyw (16) => parity=0
-prtyd (17) => parity=1
-prtyw (17) => parity=1
-prtyd (18) => parity=0
-prtyw (18) => parity=0
-prtyd (19) => parity=1
-prtyw (19) => parity=1
-prtyd (1a) => parity=0
-prtyw (1a) => parity=0
-prtyd (1b) => parity=1
-prtyw (1b) => parity=1
-prtyd (1c) => parity=0
-prtyw (1c) => parity=0
-prtyd (1d) => parity=1
-prtyw (1d) => parity=1
-prtyd (1e) => parity=0
-prtyw (1e) => parity=0
-prtyd (1f) => parity=1
-prtyw (1f) => parity=1
-prtyd (20) => parity=0
-prtyw (20) => parity=0
-prtyd (21) => parity=1
-prtyw (21) => parity=1
-prtyd (22) => parity=0
-prtyw (22) => parity=0
-prtyd (23) => parity=1
-prtyw (23) => parity=1
-prtyd (24) => parity=0
-prtyw (24) => parity=0
-prtyd (25) => parity=1
-prtyw (25) => parity=1
-prtyd (26) => parity=0
-prtyw (26) => parity=0
-prtyd (27) => parity=1
-prtyw (27) => parity=1
-prtyd (28) => parity=0
-prtyw (28) => parity=0
-prtyd (29) => parity=1
-prtyw (29) => parity=1
-prtyd (2a) => parity=0
-prtyw (2a) => parity=0
-prtyd (2b) => parity=1
-prtyw (2b) => parity=1
-prtyd (2c) => parity=0
-prtyw (2c) => parity=0
-prtyd (2d) => parity=1
-prtyw (2d) => parity=1
-prtyd (2e) => parity=0
-prtyw (2e) => parity=0
-prtyd (2f) => parity=1
-prtyw (2f) => parity=1
-prtyd (30) => parity=0
-prtyw (30) => parity=0
-prtyd (31) => parity=1
-prtyw (31) => parity=1
diff --git a/main/memcheck/tests/ppc32/power_ISA2_05.vgtest b/main/memcheck/tests/ppc32/power_ISA2_05.vgtest
index f1a91ea..712ec3b 100644
--- a/main/memcheck/tests/ppc32/power_ISA2_05.vgtest
+++ b/main/memcheck/tests/ppc32/power_ISA2_05.vgtest
@@ -1,5 +1 @@
prog: power_ISA2_05
-prog: power_ISA2_05
-prog: power_ISA2_05
-prog: power_ISA2_05
-prog: power_ISA2_05
diff --git a/main/memcheck/tests/ppc64/Makefile.in b/main/memcheck/tests/ppc64/Makefile.in
new file mode 100644
index 0000000..c0d9560
--- /dev/null
+++ b/main/memcheck/tests/ppc64/Makefile.in
@@ -0,0 +1,715 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = power_ISA2_05$(EXEEXT)
+subdir = memcheck/tests/ppc64
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+power_ISA2_05_SOURCES = power_ISA2_05.c
+power_ISA2_05_OBJECTS = power_ISA2_05-power_ISA2_05.$(OBJEXT)
+power_ISA2_05_LDADD = $(LDADD)
+power_ISA2_05_LINK = $(CCLD) $(power_ISA2_05_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = power_ISA2_05.c
+DIST_SOURCES = power_ISA2_05.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = $(noinst_SCRIPTS) \
+ power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest
+
+power_ISA2_05_CFLAGS = $(AM_CFLAGS) $(WERROR) -Winline -Wall -Wshadow -g \
+ -I$(top_srcdir)/include @FLAG_M64@
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/ppc64/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/ppc64/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+power_ISA2_05$(EXEEXT): $(power_ISA2_05_OBJECTS) $(power_ISA2_05_DEPENDENCIES)
+ @rm -f power_ISA2_05$(EXEEXT)
+ $(power_ISA2_05_LINK) $(power_ISA2_05_OBJECTS) $(power_ISA2_05_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/power_ISA2_05-power_ISA2_05.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+power_ISA2_05-power_ISA2_05.o: power_ISA2_05.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(power_ISA2_05_CFLAGS) $(CFLAGS) -MT power_ISA2_05-power_ISA2_05.o -MD -MP -MF $(DEPDIR)/power_ISA2_05-power_ISA2_05.Tpo -c -o power_ISA2_05-power_ISA2_05.o `test -f 'power_ISA2_05.c' || echo '$(srcdir)/'`power_ISA2_05.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/power_ISA2_05-power_ISA2_05.Tpo $(DEPDIR)/power_ISA2_05-power_ISA2_05.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='power_ISA2_05.c' object='power_ISA2_05-power_ISA2_05.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(power_ISA2_05_CFLAGS) $(CFLAGS) -c -o power_ISA2_05-power_ISA2_05.o `test -f 'power_ISA2_05.c' || echo '$(srcdir)/'`power_ISA2_05.c
+
+power_ISA2_05-power_ISA2_05.obj: power_ISA2_05.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(power_ISA2_05_CFLAGS) $(CFLAGS) -MT power_ISA2_05-power_ISA2_05.obj -MD -MP -MF $(DEPDIR)/power_ISA2_05-power_ISA2_05.Tpo -c -o power_ISA2_05-power_ISA2_05.obj `if test -f 'power_ISA2_05.c'; then $(CYGPATH_W) 'power_ISA2_05.c'; else $(CYGPATH_W) '$(srcdir)/power_ISA2_05.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/power_ISA2_05-power_ISA2_05.Tpo $(DEPDIR)/power_ISA2_05-power_ISA2_05.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='power_ISA2_05.c' object='power_ISA2_05-power_ISA2_05.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(power_ISA2_05_CFLAGS) $(CFLAGS) -c -o power_ISA2_05-power_ISA2_05.obj `if test -f 'power_ISA2_05.c'; then $(CYGPATH_W) 'power_ISA2_05.c'; else $(CYGPATH_W) '$(srcdir)/power_ISA2_05.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/ppc64/filter_stderr b/main/memcheck/tests/ppc64/filter_stderr
index e58b720..a778e97 100755
--- a/main/memcheck/tests/ppc64/filter_stderr
+++ b/main/memcheck/tests/ppc64/filter_stderr
@@ -1,15 +1,3 @@
#! /bin/sh
-../filter_stderr
-#! /bin/sh
-
-../filter_stderr
-#! /bin/sh
-
-../filter_stderr
-#! /bin/sh
-
-../filter_stderr
-#! /bin/sh
-
../filter_stderr "$@"
diff --git a/main/memcheck/tests/ppc64/power_ISA2_05.c b/main/memcheck/tests/ppc64/power_ISA2_05.c
index b122f96..dcf0e7a 100644
--- a/main/memcheck/tests/ppc64/power_ISA2_05.c
+++ b/main/memcheck/tests/ppc64/power_ISA2_05.c
@@ -40,7 +40,6 @@
void test_lfiwax()
{
unsigned long base;
- unsigned long offset;
typedef struct {
unsigned int hi;
@@ -50,9 +49,8 @@
int_pair_t *ip;
foo = -1024.0;
base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
+
+ __asm__ volatile ("lfiwax %0, 0, %1":"=f" (FRT1):"r"(base));
ip = (int_pair_t *) & FRT1;
printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
@@ -66,7 +64,7 @@
** FPp+1= rightmost 64 bits stored at DS(RA)
** FPp must be an even float register
*/
-int test_double_pair_instrs()
+void test_double_pair_instrs()
{
typedef struct {
double hi;
@@ -75,14 +73,6 @@
/* the following decls are for alignment */
int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
unsigned long base;
unsigned long offset;
@@ -130,11 +120,6 @@
__asm__ volatile ("stfdpx 10, 20, 21");
printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
}
@@ -170,11 +155,10 @@
}
/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
+void test_reservation()
{
int RT;
- int i, j;
unsigned long base;
unsigned long offset;
long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
@@ -193,835 +177,7 @@
__asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
printf("ldarx => %x\n", RT);
#endif
- return i + j;
-}
-
-int main(void)
-{
- (void) test_reservation();
- test_fcpsgn();
- (void) test_double_pair_instrs();
- test_lfiwax();
- test_parity_instrs();
- return 0;
-}
-#include <stdio.h>
-
-double foo = -1.0;
-double FRT1;
-double FRT2;
-int base256(int val)
-{
-/* interpret the bitstream representing val as a base 256 number for testing
- * the parity instrs
- */
- int sum = 0;
- int scale = 1;
- int i;
-
- for (i = 0; i < 8; i++) {
- int bit = val & 1;
- sum = sum + bit * scale;
- val <<= 1;
- scale *= 256;
- }
- return sum;
-}
-
-void test_parity_instrs()
-{
- unsigned long long_word;
- unsigned int word;
- int i, parity;
-
- for (i = 0; i < 50; i++) {
- word = base256(i);
- long_word = word;
- __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word));
- printf("prtyd (%x) => parity=%x\n", i, parity);
- __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word));
- printf("prtyw (%x) => parity=%x\n", i, parity);
- }
-}
-
-void test_lfiwax()
-{
- unsigned long base;
- unsigned long offset;
-
- typedef struct {
- unsigned int hi;
- unsigned int lo;
- } int_pair_t;
-
- int_pair_t *ip;
- foo = -1024.0;
- base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
- ip = (int_pair_t *) & FRT1;
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
-
-
-}
-
-
-
-/* lfdp FPp, DS(RA) : load float double pair
-** FPp = leftmost 64 bits stored at DS(RA)
-** FPp+1= rightmost 64 bits stored at DS(RA)
-** FPp must be an even float register
-*/
-int test_double_pair_instrs()
-{
- typedef struct {
- double hi;
- double lo;
- } dbl_pair_t;
-
- /* the following decls are for alignment */
- int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
- dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
- unsigned long base;
- unsigned long offset;
-
- for (i = 0; i < 3; i++) {
- dbl_pair[i].hi = -1024.0 + i;
- dbl_pair[i].lo = 1024.0 + i + 1;
- }
-
- __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2);
-
-
- FRT1 = 2.2048;
- FRT2 = -4.1024;
- __asm__ volatile ("fmr 10, %0"::"f" (FRT1));
- __asm__ volatile ("fmr 11, %0"::"f" (FRT2));
- __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1]));
- printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo);
-
- FRT1 = 0.0;
- FRT2 = -1.0;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lfdpx 10, 20, 21");
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2);
-
- FRT1 = 8.2048;
- FRT2 = -16.1024;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[2] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- __asm__ volatile ("stfdpx 10, 20, 21");
- printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
-}
-
-
-/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
-void test_fcpsgn()
-{
- double A[] = {
- 10.101010,
- -0.0,
- 0.0,
- -10.101010
- };
-
- double B[] = {
- 11.111111,
- -0.0,
- 0.0,
- -11.111111
- };
-
- double FRT, FRA, FRB;
- int i, j;
-
- for (i = 0; i < 4; i++) {
- FRA = A[i];
- for (j = 0; j < 4; j++) {
- FRB = B[j];
- __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
- "f"(FRB));
- printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);
- }
- }
-}
-
-/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
-{
-
- int RT;
- int i, j;
- unsigned long base;
- unsigned long offset;
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
-
-
- base = (unsigned long) &arr;
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
- printf("lwarx => %x\n", RT);
-
-#ifdef __powerpc64__
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
- printf("ldarx => %x\n", RT);
-#endif
- return i + j;
-}
-
-int main(void)
-{
- (void) test_reservation();
- test_fcpsgn();
- (void) test_double_pair_instrs();
- test_lfiwax();
- test_parity_instrs();
- return 0;
-}
-#include <stdio.h>
-
-double foo = -1.0;
-double FRT1;
-double FRT2;
-int base256(int val)
-{
-/* interpret the bitstream representing val as a base 256 number for testing
- * the parity instrs
- */
- int sum = 0;
- int scale = 1;
- int i;
-
- for (i = 0; i < 8; i++) {
- int bit = val & 1;
- sum = sum + bit * scale;
- val <<= 1;
- scale *= 256;
- }
- return sum;
-}
-
-void test_parity_instrs()
-{
- unsigned long long_word;
- unsigned int word;
- int i, parity;
-
- for (i = 0; i < 50; i++) {
- word = base256(i);
- long_word = word;
- __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word));
- printf("prtyd (%x) => parity=%x\n", i, parity);
- __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word));
- printf("prtyw (%x) => parity=%x\n", i, parity);
- }
-}
-
-void test_lfiwax()
-{
- unsigned long base;
- unsigned long offset;
-
- typedef struct {
- unsigned int hi;
- unsigned int lo;
- } int_pair_t;
-
- int_pair_t *ip;
- foo = -1024.0;
- base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
- ip = (int_pair_t *) & FRT1;
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
-
-
-}
-
-
-
-/* lfdp FPp, DS(RA) : load float double pair
-** FPp = leftmost 64 bits stored at DS(RA)
-** FPp+1= rightmost 64 bits stored at DS(RA)
-** FPp must be an even float register
-*/
-int test_double_pair_instrs()
-{
- typedef struct {
- double hi;
- double lo;
- } dbl_pair_t;
-
- /* the following decls are for alignment */
- int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
- dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
- unsigned long base;
- unsigned long offset;
-
- for (i = 0; i < 3; i++) {
- dbl_pair[i].hi = -1024.0 + i;
- dbl_pair[i].lo = 1024.0 + i + 1;
- }
-
- __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2);
-
-
- FRT1 = 2.2048;
- FRT2 = -4.1024;
- __asm__ volatile ("fmr 10, %0"::"f" (FRT1));
- __asm__ volatile ("fmr 11, %0"::"f" (FRT2));
- __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1]));
- printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo);
-
- FRT1 = 0.0;
- FRT2 = -1.0;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lfdpx 10, 20, 21");
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2);
-
- FRT1 = 8.2048;
- FRT2 = -16.1024;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[2] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- __asm__ volatile ("stfdpx 10, 20, 21");
- printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
-}
-
-
-/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
-void test_fcpsgn()
-{
- double A[] = {
- 10.101010,
- -0.0,
- 0.0,
- -10.101010
- };
-
- double B[] = {
- 11.111111,
- -0.0,
- 0.0,
- -11.111111
- };
-
- double FRT, FRA, FRB;
- int i, j;
-
- for (i = 0; i < 4; i++) {
- FRA = A[i];
- for (j = 0; j < 4; j++) {
- FRB = B[j];
- __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
- "f"(FRB));
- printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);
- }
- }
-}
-
-/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
-{
-
- int RT;
- int i, j;
- unsigned long base;
- unsigned long offset;
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
-
-
- base = (unsigned long) &arr;
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
- printf("lwarx => %x\n", RT);
-
-#ifdef __powerpc64__
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
- printf("ldarx => %x\n", RT);
-#endif
- return i + j;
-}
-
-int main(void)
-{
- (void) test_reservation();
- test_fcpsgn();
- (void) test_double_pair_instrs();
- test_lfiwax();
- test_parity_instrs();
- return 0;
-}
-#include <stdio.h>
-
-double foo = -1.0;
-double FRT1;
-double FRT2;
-int base256(int val)
-{
-/* interpret the bitstream representing val as a base 256 number for testing
- * the parity instrs
- */
- int sum = 0;
- int scale = 1;
- int i;
-
- for (i = 0; i < 8; i++) {
- int bit = val & 1;
- sum = sum + bit * scale;
- val <<= 1;
- scale *= 256;
- }
- return sum;
-}
-
-void test_parity_instrs()
-{
- unsigned long long_word;
- unsigned int word;
- int i, parity;
-
- for (i = 0; i < 50; i++) {
- word = base256(i);
- long_word = word;
- __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word));
- printf("prtyd (%x) => parity=%x\n", i, parity);
- __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word));
- printf("prtyw (%x) => parity=%x\n", i, parity);
- }
-}
-
-void test_lfiwax()
-{
- unsigned long base;
- unsigned long offset;
-
- typedef struct {
- unsigned int hi;
- unsigned int lo;
- } int_pair_t;
-
- int_pair_t *ip;
- foo = -1024.0;
- base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
- ip = (int_pair_t *) & FRT1;
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
-
-
-}
-
-
-
-/* lfdp FPp, DS(RA) : load float double pair
-** FPp = leftmost 64 bits stored at DS(RA)
-** FPp+1= rightmost 64 bits stored at DS(RA)
-** FPp must be an even float register
-*/
-int test_double_pair_instrs()
-{
- typedef struct {
- double hi;
- double lo;
- } dbl_pair_t;
-
- /* the following decls are for alignment */
- int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
- dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
- unsigned long base;
- unsigned long offset;
-
- for (i = 0; i < 3; i++) {
- dbl_pair[i].hi = -1024.0 + i;
- dbl_pair[i].lo = 1024.0 + i + 1;
- }
-
- __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2);
-
-
- FRT1 = 2.2048;
- FRT2 = -4.1024;
- __asm__ volatile ("fmr 10, %0"::"f" (FRT1));
- __asm__ volatile ("fmr 11, %0"::"f" (FRT2));
- __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1]));
- printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo);
-
- FRT1 = 0.0;
- FRT2 = -1.0;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lfdpx 10, 20, 21");
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2);
-
- FRT1 = 8.2048;
- FRT2 = -16.1024;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[2] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- __asm__ volatile ("stfdpx 10, 20, 21");
- printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
-}
-
-
-/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
-void test_fcpsgn()
-{
- double A[] = {
- 10.101010,
- -0.0,
- 0.0,
- -10.101010
- };
-
- double B[] = {
- 11.111111,
- -0.0,
- 0.0,
- -11.111111
- };
-
- double FRT, FRA, FRB;
- int i, j;
-
- for (i = 0; i < 4; i++) {
- FRA = A[i];
- for (j = 0; j < 4; j++) {
- FRB = B[j];
- __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
- "f"(FRB));
- printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);
- }
- }
-}
-
-/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
-{
-
- int RT;
- int i, j;
- unsigned long base;
- unsigned long offset;
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
-
-
- base = (unsigned long) &arr;
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
- printf("lwarx => %x\n", RT);
-
-#ifdef __powerpc64__
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
- printf("ldarx => %x\n", RT);
-#endif
- return i + j;
-}
-
-int main(void)
-{
- (void) test_reservation();
- test_fcpsgn();
- (void) test_double_pair_instrs();
- test_lfiwax();
- test_parity_instrs();
- return 0;
-}
-#include <stdio.h>
-
-double foo = -1.0;
-double FRT1;
-double FRT2;
-int base256(int val)
-{
-/* interpret the bitstream representing val as a base 256 number for testing
- * the parity instrs
- */
- int sum = 0;
- int scale = 1;
- int i;
-
- for (i = 0; i < 8; i++) {
- int bit = val & 1;
- sum = sum + bit * scale;
- val <<= 1;
- scale *= 256;
- }
- return sum;
-}
-
-void test_parity_instrs()
-{
- unsigned long long_word;
- unsigned int word;
- int i, parity;
-
- for (i = 0; i < 50; i++) {
- word = base256(i);
- long_word = word;
- __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word));
- printf("prtyd (%x) => parity=%x\n", i, parity);
- __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word));
- printf("prtyw (%x) => parity=%x\n", i, parity);
- }
-}
-
-void test_lfiwax()
-{
- unsigned long base;
- unsigned long offset;
-
- typedef struct {
- unsigned int hi;
- unsigned int lo;
- } int_pair_t;
-
- int_pair_t *ip;
- foo = -1024.0;
- base = (unsigned long) &foo;
- offset = 0;
- __asm__ volatile ("lfiwax %0, %1, %2":"=f" (FRT1):"r"(base),
- "r"(offset));
- ip = (int_pair_t *) & FRT1;
- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
-
-
-}
-
-
-
-/* lfdp FPp, DS(RA) : load float double pair
-** FPp = leftmost 64 bits stored at DS(RA)
-** FPp+1= rightmost 64 bits stored at DS(RA)
-** FPp must be an even float register
-*/
-int test_double_pair_instrs()
-{
- typedef struct {
- double hi;
- double lo;
- } dbl_pair_t;
-
- /* the following decls are for alignment */
- int i;
- int j;
- int k;
- int l;
-#ifdef __powerpc64__
- int m;
- int n;
- int o;
-#endif
- dbl_pair_t dbl_pair[3]; /* must be quad word aligned */
- unsigned long base;
- unsigned long offset;
-
- for (i = 0; i < 3; i++) {
- dbl_pair[i].hi = -1024.0 + i;
- dbl_pair[i].lo = 1024.0 + i + 1;
- }
-
- __asm__ volatile ("lfdp 10, %0"::"m" (dbl_pair[0]));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[0].hi, dbl_pair[0].lo, FRT1, FRT2);
-
-
- FRT1 = 2.2048;
- FRT2 = -4.1024;
- __asm__ volatile ("fmr 10, %0"::"f" (FRT1));
- __asm__ volatile ("fmr 11, %0"::"f" (FRT2));
- __asm__ volatile ("stfdp 10, %0"::"m" (dbl_pair[1]));
- printf("stfdp (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[1].hi, dbl_pair[1].lo);
-
- FRT1 = 0.0;
- FRT2 = -1.0;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lfdpx 10, 20, 21");
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- printf("lfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- dbl_pair[1].hi, dbl_pair[1].lo, FRT1, FRT2);
-
- FRT1 = 8.2048;
- FRT2 = -16.1024;
- base = (unsigned long) &dbl_pair;
- offset = (unsigned long) &dbl_pair[2] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("fmr %0, 10":"=f" (FRT1));
- __asm__ volatile ("fmr %0, 11":"=f" (FRT2));
- __asm__ volatile ("stfdpx 10, 20, 21");
- printf("stfdpx (%f, %f) => F_hi=%f, F_lo=%f\n",
- FRT1, FRT2, dbl_pair[2].hi, dbl_pair[2].lo);
-#ifdef __powerpc64__
- return i + j + k + l + m + n + o;
-#else
- return i + j + k + l;
-#endif
-}
-
-
-/* The contents of FRB with bit set 0 set to bit 0 of FRA copied into FRT */
-void test_fcpsgn()
-{
- double A[] = {
- 10.101010,
- -0.0,
- 0.0,
- -10.101010
- };
-
- double B[] = {
- 11.111111,
- -0.0,
- 0.0,
- -11.111111
- };
-
- double FRT, FRA, FRB;
- int i, j;
-
- for (i = 0; i < 4; i++) {
- FRA = A[i];
- for (j = 0; j < 4; j++) {
- FRB = B[j];
- __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA),
- "f"(FRB));
- printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT);
- }
- }
-}
-
-/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
-int test_reservation()
-{
-
- int RT;
- int i, j;
- unsigned long base;
- unsigned long offset;
- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
-
-
- base = (unsigned long) &arr;
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 20, 0, %0"::"r" (base));
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
- printf("lwarx => %x\n", RT);
-#ifdef __powerpc64__
- offset = (unsigned long) &arr[1] - base;
- __asm__ volatile ("or 21, 0, %0"::"r" (offset));
- __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
- printf("ldarx => %x\n", RT);
-#endif
- return i + j;
}
int main(void)
diff --git a/main/memcheck/tests/ppc64/power_ISA2_05.stderr.exp b/main/memcheck/tests/ppc64/power_ISA2_05.stderr.exp
index 543b8f8..c22dd7f 100644
--- a/main/memcheck/tests/ppc64/power_ISA2_05.stderr.exp
+++ b/main/memcheck/tests/ppc64/power_ISA2_05.stderr.exp
@@ -8,43 +8,3 @@
For counts of detected and suppressed errors, rerun with: -v
ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
-
-
-HEAP SUMMARY:
- in use at exit: 0 bytes in 0 blocks
- total heap usage: 0 allocs, 0 frees, 0 bytes allocated
-
-For a detailed leak analysis, rerun with: --leak-check=full
-
-For counts of detected and suppressed errors, rerun with: -v
-ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
-
-
-HEAP SUMMARY:
- in use at exit: 0 bytes in 0 blocks
- total heap usage: 0 allocs, 0 frees, 0 bytes allocated
-
-For a detailed leak analysis, rerun with: --leak-check=full
-
-For counts of detected and suppressed errors, rerun with: -v
-ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
-
-
-HEAP SUMMARY:
- in use at exit: 0 bytes in 0 blocks
- total heap usage: 0 allocs, 0 frees, 0 bytes allocated
-
-For a detailed leak analysis, rerun with: --leak-check=full
-
-For counts of detected and suppressed errors, rerun with: -v
-ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
-
-
-HEAP SUMMARY:
- in use at exit: 0 bytes in 0 blocks
- total heap usage: 0 allocs, 0 frees, 0 bytes allocated
-
-For a detailed leak analysis, rerun with: --leak-check=full
-
-For counts of detected and suppressed errors, rerun with: -v
-ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/ppc64/power_ISA2_05.stdout.exp b/main/memcheck/tests/ppc64/power_ISA2_05.stdout.exp
index 363d022..3297838 100644
--- a/main/memcheck/tests/ppc64/power_ISA2_05.stdout.exp
+++ b/main/memcheck/tests/ppc64/power_ISA2_05.stdout.exp
@@ -19,499 +19,7 @@
lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-stfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
-prtyd (0) => parity=0
-prtyw (0) => parity=0
-prtyd (1) => parity=1
-prtyw (1) => parity=1
-prtyd (2) => parity=0
-prtyw (2) => parity=0
-prtyd (3) => parity=1
-prtyw (3) => parity=1
-prtyd (4) => parity=0
-prtyw (4) => parity=0
-prtyd (5) => parity=1
-prtyw (5) => parity=1
-prtyd (6) => parity=0
-prtyw (6) => parity=0
-prtyd (7) => parity=1
-prtyw (7) => parity=1
-prtyd (8) => parity=0
-prtyw (8) => parity=0
-prtyd (9) => parity=1
-prtyw (9) => parity=1
-prtyd (a) => parity=0
-prtyw (a) => parity=0
-prtyd (b) => parity=1
-prtyw (b) => parity=1
-prtyd (c) => parity=0
-prtyw (c) => parity=0
-prtyd (d) => parity=1
-prtyw (d) => parity=1
-prtyd (e) => parity=0
-prtyw (e) => parity=0
-prtyd (f) => parity=1
-prtyw (f) => parity=1
-prtyd (10) => parity=0
-prtyw (10) => parity=0
-prtyd (11) => parity=1
-prtyw (11) => parity=1
-prtyd (12) => parity=0
-prtyw (12) => parity=0
-prtyd (13) => parity=1
-prtyw (13) => parity=1
-prtyd (14) => parity=0
-prtyw (14) => parity=0
-prtyd (15) => parity=1
-prtyw (15) => parity=1
-prtyd (16) => parity=0
-prtyw (16) => parity=0
-prtyd (17) => parity=1
-prtyw (17) => parity=1
-prtyd (18) => parity=0
-prtyw (18) => parity=0
-prtyd (19) => parity=1
-prtyw (19) => parity=1
-prtyd (1a) => parity=0
-prtyw (1a) => parity=0
-prtyd (1b) => parity=1
-prtyw (1b) => parity=1
-prtyd (1c) => parity=0
-prtyw (1c) => parity=0
-prtyd (1d) => parity=1
-prtyw (1d) => parity=1
-prtyd (1e) => parity=0
-prtyw (1e) => parity=0
-prtyd (1f) => parity=1
-prtyw (1f) => parity=1
-prtyd (20) => parity=0
-prtyw (20) => parity=0
-prtyd (21) => parity=1
-prtyw (21) => parity=1
-prtyd (22) => parity=0
-prtyw (22) => parity=0
-prtyd (23) => parity=1
-prtyw (23) => parity=1
-prtyd (24) => parity=0
-prtyw (24) => parity=0
-prtyd (25) => parity=1
-prtyw (25) => parity=1
-prtyd (26) => parity=0
-prtyw (26) => parity=0
-prtyd (27) => parity=1
-prtyw (27) => parity=1
-prtyd (28) => parity=0
-prtyw (28) => parity=0
-prtyd (29) => parity=1
-prtyw (29) => parity=1
-prtyd (2a) => parity=0
-prtyw (2a) => parity=0
-prtyd (2b) => parity=1
-prtyw (2b) => parity=1
-prtyd (2c) => parity=0
-prtyw (2c) => parity=0
-prtyd (2d) => parity=1
-prtyw (2d) => parity=1
-prtyd (2e) => parity=0
-prtyw (2e) => parity=0
-prtyd (2f) => parity=1
-prtyw (2f) => parity=1
-prtyd (30) => parity=0
-prtyw (30) => parity=0
-prtyd (31) => parity=1
-prtyw (31) => parity=1
-lwarx => 0
-ldarx => bad0beef
-fcpsgn sign=10.101010, base=11.111111 => 11.111111
-fcpsgn sign=10.101010, base=-0.000000 => 0.000000
-fcpsgn sign=10.101010, base=0.000000 => 0.000000
-fcpsgn sign=10.101010, base=-11.111111 => 11.111111
-fcpsgn sign=-0.000000, base=11.111111 => -11.111111
-fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
-fcpsgn sign=0.000000, base=11.111111 => 11.111111
-fcpsgn sign=0.000000, base=-0.000000 => 0.000000
-fcpsgn sign=0.000000, base=0.000000 => 0.000000
-fcpsgn sign=0.000000, base=-11.111111 => 11.111111
-fcpsgn sign=-10.101010, base=11.111111 => -11.111111
-fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
-lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
-stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-stfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
-prtyd (0) => parity=0
-prtyw (0) => parity=0
-prtyd (1) => parity=1
-prtyw (1) => parity=1
-prtyd (2) => parity=0
-prtyw (2) => parity=0
-prtyd (3) => parity=1
-prtyw (3) => parity=1
-prtyd (4) => parity=0
-prtyw (4) => parity=0
-prtyd (5) => parity=1
-prtyw (5) => parity=1
-prtyd (6) => parity=0
-prtyw (6) => parity=0
-prtyd (7) => parity=1
-prtyw (7) => parity=1
-prtyd (8) => parity=0
-prtyw (8) => parity=0
-prtyd (9) => parity=1
-prtyw (9) => parity=1
-prtyd (a) => parity=0
-prtyw (a) => parity=0
-prtyd (b) => parity=1
-prtyw (b) => parity=1
-prtyd (c) => parity=0
-prtyw (c) => parity=0
-prtyd (d) => parity=1
-prtyw (d) => parity=1
-prtyd (e) => parity=0
-prtyw (e) => parity=0
-prtyd (f) => parity=1
-prtyw (f) => parity=1
-prtyd (10) => parity=0
-prtyw (10) => parity=0
-prtyd (11) => parity=1
-prtyw (11) => parity=1
-prtyd (12) => parity=0
-prtyw (12) => parity=0
-prtyd (13) => parity=1
-prtyw (13) => parity=1
-prtyd (14) => parity=0
-prtyw (14) => parity=0
-prtyd (15) => parity=1
-prtyw (15) => parity=1
-prtyd (16) => parity=0
-prtyw (16) => parity=0
-prtyd (17) => parity=1
-prtyw (17) => parity=1
-prtyd (18) => parity=0
-prtyw (18) => parity=0
-prtyd (19) => parity=1
-prtyw (19) => parity=1
-prtyd (1a) => parity=0
-prtyw (1a) => parity=0
-prtyd (1b) => parity=1
-prtyw (1b) => parity=1
-prtyd (1c) => parity=0
-prtyw (1c) => parity=0
-prtyd (1d) => parity=1
-prtyw (1d) => parity=1
-prtyd (1e) => parity=0
-prtyw (1e) => parity=0
-prtyd (1f) => parity=1
-prtyw (1f) => parity=1
-prtyd (20) => parity=0
-prtyw (20) => parity=0
-prtyd (21) => parity=1
-prtyw (21) => parity=1
-prtyd (22) => parity=0
-prtyw (22) => parity=0
-prtyd (23) => parity=1
-prtyw (23) => parity=1
-prtyd (24) => parity=0
-prtyw (24) => parity=0
-prtyd (25) => parity=1
-prtyw (25) => parity=1
-prtyd (26) => parity=0
-prtyw (26) => parity=0
-prtyd (27) => parity=1
-prtyw (27) => parity=1
-prtyd (28) => parity=0
-prtyw (28) => parity=0
-prtyd (29) => parity=1
-prtyw (29) => parity=1
-prtyd (2a) => parity=0
-prtyw (2a) => parity=0
-prtyd (2b) => parity=1
-prtyw (2b) => parity=1
-prtyd (2c) => parity=0
-prtyw (2c) => parity=0
-prtyd (2d) => parity=1
-prtyw (2d) => parity=1
-prtyd (2e) => parity=0
-prtyw (2e) => parity=0
-prtyd (2f) => parity=1
-prtyw (2f) => parity=1
-prtyd (30) => parity=0
-prtyw (30) => parity=0
-prtyd (31) => parity=1
-prtyw (31) => parity=1
-lwarx => 0
-ldarx => bad0beef
-fcpsgn sign=10.101010, base=11.111111 => 11.111111
-fcpsgn sign=10.101010, base=-0.000000 => 0.000000
-fcpsgn sign=10.101010, base=0.000000 => 0.000000
-fcpsgn sign=10.101010, base=-11.111111 => 11.111111
-fcpsgn sign=-0.000000, base=11.111111 => -11.111111
-fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
-fcpsgn sign=0.000000, base=11.111111 => 11.111111
-fcpsgn sign=0.000000, base=-0.000000 => 0.000000
-fcpsgn sign=0.000000, base=0.000000 => 0.000000
-fcpsgn sign=0.000000, base=-11.111111 => 11.111111
-fcpsgn sign=-10.101010, base=11.111111 => -11.111111
-fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
-lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
-stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-stfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
-prtyd (0) => parity=0
-prtyw (0) => parity=0
-prtyd (1) => parity=1
-prtyw (1) => parity=1
-prtyd (2) => parity=0
-prtyw (2) => parity=0
-prtyd (3) => parity=1
-prtyw (3) => parity=1
-prtyd (4) => parity=0
-prtyw (4) => parity=0
-prtyd (5) => parity=1
-prtyw (5) => parity=1
-prtyd (6) => parity=0
-prtyw (6) => parity=0
-prtyd (7) => parity=1
-prtyw (7) => parity=1
-prtyd (8) => parity=0
-prtyw (8) => parity=0
-prtyd (9) => parity=1
-prtyw (9) => parity=1
-prtyd (a) => parity=0
-prtyw (a) => parity=0
-prtyd (b) => parity=1
-prtyw (b) => parity=1
-prtyd (c) => parity=0
-prtyw (c) => parity=0
-prtyd (d) => parity=1
-prtyw (d) => parity=1
-prtyd (e) => parity=0
-prtyw (e) => parity=0
-prtyd (f) => parity=1
-prtyw (f) => parity=1
-prtyd (10) => parity=0
-prtyw (10) => parity=0
-prtyd (11) => parity=1
-prtyw (11) => parity=1
-prtyd (12) => parity=0
-prtyw (12) => parity=0
-prtyd (13) => parity=1
-prtyw (13) => parity=1
-prtyd (14) => parity=0
-prtyw (14) => parity=0
-prtyd (15) => parity=1
-prtyw (15) => parity=1
-prtyd (16) => parity=0
-prtyw (16) => parity=0
-prtyd (17) => parity=1
-prtyw (17) => parity=1
-prtyd (18) => parity=0
-prtyw (18) => parity=0
-prtyd (19) => parity=1
-prtyw (19) => parity=1
-prtyd (1a) => parity=0
-prtyw (1a) => parity=0
-prtyd (1b) => parity=1
-prtyw (1b) => parity=1
-prtyd (1c) => parity=0
-prtyw (1c) => parity=0
-prtyd (1d) => parity=1
-prtyw (1d) => parity=1
-prtyd (1e) => parity=0
-prtyw (1e) => parity=0
-prtyd (1f) => parity=1
-prtyw (1f) => parity=1
-prtyd (20) => parity=0
-prtyw (20) => parity=0
-prtyd (21) => parity=1
-prtyw (21) => parity=1
-prtyd (22) => parity=0
-prtyw (22) => parity=0
-prtyd (23) => parity=1
-prtyw (23) => parity=1
-prtyd (24) => parity=0
-prtyw (24) => parity=0
-prtyd (25) => parity=1
-prtyw (25) => parity=1
-prtyd (26) => parity=0
-prtyw (26) => parity=0
-prtyd (27) => parity=1
-prtyw (27) => parity=1
-prtyd (28) => parity=0
-prtyw (28) => parity=0
-prtyd (29) => parity=1
-prtyw (29) => parity=1
-prtyd (2a) => parity=0
-prtyw (2a) => parity=0
-prtyd (2b) => parity=1
-prtyw (2b) => parity=1
-prtyd (2c) => parity=0
-prtyw (2c) => parity=0
-prtyd (2d) => parity=1
-prtyw (2d) => parity=1
-prtyd (2e) => parity=0
-prtyw (2e) => parity=0
-prtyd (2f) => parity=1
-prtyw (2f) => parity=1
-prtyd (30) => parity=0
-prtyw (30) => parity=0
-prtyd (31) => parity=1
-prtyw (31) => parity=1
-lwarx => 0
-ldarx => bad0beef
-fcpsgn sign=10.101010, base=11.111111 => 11.111111
-fcpsgn sign=10.101010, base=-0.000000 => 0.000000
-fcpsgn sign=10.101010, base=0.000000 => 0.000000
-fcpsgn sign=10.101010, base=-11.111111 => 11.111111
-fcpsgn sign=-0.000000, base=11.111111 => -11.111111
-fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
-fcpsgn sign=0.000000, base=11.111111 => 11.111111
-fcpsgn sign=0.000000, base=-0.000000 => 0.000000
-fcpsgn sign=0.000000, base=0.000000 => 0.000000
-fcpsgn sign=0.000000, base=-11.111111 => 11.111111
-fcpsgn sign=-10.101010, base=11.111111 => -11.111111
-fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
-lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
-stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-stfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
-prtyd (0) => parity=0
-prtyw (0) => parity=0
-prtyd (1) => parity=1
-prtyw (1) => parity=1
-prtyd (2) => parity=0
-prtyw (2) => parity=0
-prtyd (3) => parity=1
-prtyw (3) => parity=1
-prtyd (4) => parity=0
-prtyw (4) => parity=0
-prtyd (5) => parity=1
-prtyw (5) => parity=1
-prtyd (6) => parity=0
-prtyw (6) => parity=0
-prtyd (7) => parity=1
-prtyw (7) => parity=1
-prtyd (8) => parity=0
-prtyw (8) => parity=0
-prtyd (9) => parity=1
-prtyw (9) => parity=1
-prtyd (a) => parity=0
-prtyw (a) => parity=0
-prtyd (b) => parity=1
-prtyw (b) => parity=1
-prtyd (c) => parity=0
-prtyw (c) => parity=0
-prtyd (d) => parity=1
-prtyw (d) => parity=1
-prtyd (e) => parity=0
-prtyw (e) => parity=0
-prtyd (f) => parity=1
-prtyw (f) => parity=1
-prtyd (10) => parity=0
-prtyw (10) => parity=0
-prtyd (11) => parity=1
-prtyw (11) => parity=1
-prtyd (12) => parity=0
-prtyw (12) => parity=0
-prtyd (13) => parity=1
-prtyw (13) => parity=1
-prtyd (14) => parity=0
-prtyw (14) => parity=0
-prtyd (15) => parity=1
-prtyw (15) => parity=1
-prtyd (16) => parity=0
-prtyw (16) => parity=0
-prtyd (17) => parity=1
-prtyw (17) => parity=1
-prtyd (18) => parity=0
-prtyw (18) => parity=0
-prtyd (19) => parity=1
-prtyw (19) => parity=1
-prtyd (1a) => parity=0
-prtyw (1a) => parity=0
-prtyd (1b) => parity=1
-prtyw (1b) => parity=1
-prtyd (1c) => parity=0
-prtyw (1c) => parity=0
-prtyd (1d) => parity=1
-prtyw (1d) => parity=1
-prtyd (1e) => parity=0
-prtyw (1e) => parity=0
-prtyd (1f) => parity=1
-prtyw (1f) => parity=1
-prtyd (20) => parity=0
-prtyw (20) => parity=0
-prtyd (21) => parity=1
-prtyw (21) => parity=1
-prtyd (22) => parity=0
-prtyw (22) => parity=0
-prtyd (23) => parity=1
-prtyw (23) => parity=1
-prtyd (24) => parity=0
-prtyw (24) => parity=0
-prtyd (25) => parity=1
-prtyw (25) => parity=1
-prtyd (26) => parity=0
-prtyw (26) => parity=0
-prtyd (27) => parity=1
-prtyw (27) => parity=1
-prtyd (28) => parity=0
-prtyw (28) => parity=0
-prtyd (29) => parity=1
-prtyw (29) => parity=1
-prtyd (2a) => parity=0
-prtyw (2a) => parity=0
-prtyd (2b) => parity=1
-prtyw (2b) => parity=1
-prtyd (2c) => parity=0
-prtyw (2c) => parity=0
-prtyd (2d) => parity=1
-prtyw (2d) => parity=1
-prtyd (2e) => parity=0
-prtyw (2e) => parity=0
-prtyd (2f) => parity=1
-prtyw (2f) => parity=1
-prtyd (30) => parity=0
-prtyw (30) => parity=0
-prtyd (31) => parity=1
-prtyw (31) => parity=1
-lwarx => 0
-ldarx => bad0beef
-fcpsgn sign=10.101010, base=11.111111 => 11.111111
-fcpsgn sign=10.101010, base=-0.000000 => 0.000000
-fcpsgn sign=10.101010, base=0.000000 => 0.000000
-fcpsgn sign=10.101010, base=-11.111111 => 11.111111
-fcpsgn sign=-0.000000, base=11.111111 => -11.111111
-fcpsgn sign=-0.000000, base=-0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=0.000000 => -0.000000
-fcpsgn sign=-0.000000, base=-11.111111 => -11.111111
-fcpsgn sign=0.000000, base=11.111111 => 11.111111
-fcpsgn sign=0.000000, base=-0.000000 => 0.000000
-fcpsgn sign=0.000000, base=0.000000 => 0.000000
-fcpsgn sign=0.000000, base=-11.111111 => 11.111111
-fcpsgn sign=-10.101010, base=11.111111 => -11.111111
-fcpsgn sign=-10.101010, base=-0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=0.000000 => -0.000000
-fcpsgn sign=-10.101010, base=-11.111111 => -11.111111
-lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
-stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
-stfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
+stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
prtyd (0) => parity=0
prtyw (0) => parity=0
diff --git a/main/memcheck/tests/ppc64/power_ISA2_05.vgtest b/main/memcheck/tests/ppc64/power_ISA2_05.vgtest
index 21bbbdb..7f0006a 100644
--- a/main/memcheck/tests/ppc64/power_ISA2_05.vgtest
+++ b/main/memcheck/tests/ppc64/power_ISA2_05.vgtest
@@ -1,10 +1,2 @@
prog: power_ISA2_05
vgopts: --workaround-gcc296-bugs=yes
-prog: power_ISA2_05
-vgopts: --workaround-gcc296-bugs=yes
-prog: power_ISA2_05
-vgopts: --workaround-gcc296-bugs=yes
-prog: power_ISA2_05
-vgopts: --workaround-gcc296-bugs=yes
-prog: power_ISA2_05
-vgopts: --workaround-gcc296-bugs=yes
diff --git a/main/memcheck/tests/s390x/Makefile.am b/main/memcheck/tests/s390x/Makefile.am
new file mode 100644
index 0000000..1fb8d7f
--- /dev/null
+++ b/main/memcheck/tests/s390x/Makefile.am
@@ -0,0 +1,16 @@
+include $(top_srcdir)/Makefile.tool-tests.am
+
+dist_noinst_SCRIPTS = filter_stderr
+
+INSN_TESTS = cs csg cds cdsg cu21 cu42
+
+check_PROGRAMS = $(INSN_TESTS)
+
+EXTRA_DIST = \
+ $(addsuffix .stderr.exp,$(INSN_TESTS)) \
+ $(addsuffix .stdout.exp,$(INSN_TESTS)) \
+ $(addsuffix .vgtest,$(INSN_TESTS))
+
+AM_CFLAGS += @FLAG_M64@
+AM_CXXFLAGS += @FLAG_M64@
+AM_CCASFLAGS += @FLAG_M64@
diff --git a/main/memcheck/tests/s390x/Makefile.in b/main/memcheck/tests/s390x/Makefile.in
new file mode 100644
index 0000000..d588e11
--- /dev/null
+++ b/main/memcheck/tests/s390x/Makefile.in
@@ -0,0 +1,736 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = $(am__EXEEXT_1)
+subdir = memcheck/tests/s390x
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+am__EXEEXT_1 = cs$(EXEEXT) csg$(EXEEXT) cds$(EXEEXT) cdsg$(EXEEXT) \
+ cu21$(EXEEXT) cu42$(EXEEXT)
+cds_SOURCES = cds.c
+cds_OBJECTS = cds.$(OBJEXT)
+cds_LDADD = $(LDADD)
+cdsg_SOURCES = cdsg.c
+cdsg_OBJECTS = cdsg.$(OBJEXT)
+cdsg_LDADD = $(LDADD)
+cs_SOURCES = cs.c
+cs_OBJECTS = cs.$(OBJEXT)
+cs_LDADD = $(LDADD)
+csg_SOURCES = csg.c
+csg_OBJECTS = csg.$(OBJEXT)
+csg_LDADD = $(LDADD)
+cu21_SOURCES = cu21.c
+cu21_OBJECTS = cu21.$(OBJEXT)
+cu21_LDADD = $(LDADD)
+cu42_SOURCES = cu42.c
+cu42_OBJECTS = cu42.$(OBJEXT)
+cu42_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = cds.c cdsg.c cs.c csg.c cu21.c cu42.c
+DIST_SOURCES = cds.c cdsg.c cs.c csg.c cu21.c cu42.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+INSN_TESTS = cs csg cds cdsg cu21 cu42
+EXTRA_DIST = \
+ $(addsuffix .stderr.exp,$(INSN_TESTS)) \
+ $(addsuffix .stdout.exp,$(INSN_TESTS)) \
+ $(addsuffix .vgtest,$(INSN_TESTS))
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/s390x/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/s390x/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+cds$(EXEEXT): $(cds_OBJECTS) $(cds_DEPENDENCIES)
+ @rm -f cds$(EXEEXT)
+ $(LINK) $(cds_OBJECTS) $(cds_LDADD) $(LIBS)
+cdsg$(EXEEXT): $(cdsg_OBJECTS) $(cdsg_DEPENDENCIES)
+ @rm -f cdsg$(EXEEXT)
+ $(LINK) $(cdsg_OBJECTS) $(cdsg_LDADD) $(LIBS)
+cs$(EXEEXT): $(cs_OBJECTS) $(cs_DEPENDENCIES)
+ @rm -f cs$(EXEEXT)
+ $(LINK) $(cs_OBJECTS) $(cs_LDADD) $(LIBS)
+csg$(EXEEXT): $(csg_OBJECTS) $(csg_DEPENDENCIES)
+ @rm -f csg$(EXEEXT)
+ $(LINK) $(csg_OBJECTS) $(csg_LDADD) $(LIBS)
+cu21$(EXEEXT): $(cu21_OBJECTS) $(cu21_DEPENDENCIES)
+ @rm -f cu21$(EXEEXT)
+ $(LINK) $(cu21_OBJECTS) $(cu21_LDADD) $(LIBS)
+cu42$(EXEEXT): $(cu42_OBJECTS) $(cu42_DEPENDENCIES)
+ @rm -f cu42$(EXEEXT)
+ $(LINK) $(cu42_OBJECTS) $(cu42_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cds.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cdsg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/csg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu21.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu42.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/s390x/cds.c b/main/memcheck/tests/s390x/cds.c
new file mode 100644
index 0000000..ec5c533
--- /dev/null
+++ b/main/memcheck/tests/s390x/cds.c
@@ -0,0 +1,82 @@
+#include <stdint.h>
+#include <stdio.h>
+
+typedef struct {
+ uint64_t high;
+ uint64_t low;
+} quad_word;
+
+void
+test(quad_word op1_init, uint64_t op2_init, quad_word op3_init)
+{
+ int cc; // unused
+ quad_word op1 = op1_init;
+ uint64_t op2 = op2_init;
+ quad_word op3 = op3_init;
+
+ __asm__ volatile (
+ "lmg %%r0,%%r1,%1\n\t"
+ "lmg %%r2,%%r3,%3\n\t"
+ "cds %%r0,%%r2,%2\n\t" // cds 1st,3rd,2nd
+ "stmg %%r0,%%r1,%1\n" // store r0,r1 to op1
+ "stmg %%r2,%%r3,%3\n" // store r2,r3 to op3
+ : "=d" (cc), "+QS" (op1), "+QS" (op2), "+QS" (op3)
+ :
+ : "r0", "r1", "r2", "r3", "cc");
+
+}
+
+// Return a quad-word that only bits low[32:63] are undefined
+quad_word
+make_undefined(void)
+{
+ quad_word val;
+
+ val.high = 0;
+ val.low |= 0xFFFFFFFF00000000ull;
+
+ return val;
+}
+
+void op1_undefined(void)
+{
+ quad_word op1, op3;
+ uint64_t op2;
+
+ // op1 undefined
+ op1 = make_undefined();
+ op2 = 42;
+ op3.high = op3.low = 0xdeadbeefdeadbabeull;
+ test(op1, op2, op3); // complaint
+}
+
+void op2_undefined(void)
+{
+ quad_word op1, op3;
+ uint64_t op2;
+
+ op1.high = op1.low = 42;
+ // op2 undefined
+ op3.high = op3.low = 0xdeadbeefdeadbabeull;
+ test(op1, op2, op3); // complaint
+}
+
+void op3_undefined(void)
+{
+ quad_word op1, op3;
+ uint64_t op2;
+
+ op1.high = op1.low = 42;
+ op2 = 100;
+ op3 = make_undefined();
+ test(op1, op2, op3); // no complaint; op3 is just copied around
+}
+
+int main ()
+{
+ op1_undefined();
+ op2_undefined();
+ op3_undefined();
+
+ return 0;
+}
diff --git a/main/memcheck/tests/s390x/cds.stderr.exp b/main/memcheck/tests/s390x/cds.stderr.exp
new file mode 100644
index 0000000..e72de94
--- /dev/null
+++ b/main/memcheck/tests/s390x/cds.stderr.exp
@@ -0,0 +1,10 @@
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: test (cds.c:17)
+ by 0x........: op1_undefined (cds.c:50)
+ by 0x........: main (cds.c:77)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: test (cds.c:17)
+ by 0x........: op2_undefined (cds.c:61)
+ by 0x........: main (cds.c:78)
+
diff --git a/main/memcheck/tests/amd64/int3-amd64.stdout.exp b/main/memcheck/tests/s390x/cds.stdout.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stdout.exp
copy to main/memcheck/tests/s390x/cds.stdout.exp
diff --git a/main/memcheck/tests/s390x/cds.vgtest b/main/memcheck/tests/s390x/cds.vgtest
new file mode 100644
index 0000000..5195887
--- /dev/null
+++ b/main/memcheck/tests/s390x/cds.vgtest
@@ -0,0 +1,2 @@
+prog: cds
+vgopts: -q
diff --git a/main/memcheck/tests/s390x/cdsg.c b/main/memcheck/tests/s390x/cdsg.c
new file mode 100644
index 0000000..ff0ae8c
--- /dev/null
+++ b/main/memcheck/tests/s390x/cdsg.c
@@ -0,0 +1,69 @@
+#include <stdint.h>
+#include <stdio.h>
+
+typedef struct {
+ uint64_t high;
+ uint64_t low;
+} __attribute__((aligned(16))) quad_word;
+
+
+/* CDSG needs quad-word alignment */
+quad_word _op1, _op2, _op3;
+
+void
+test(quad_word op1_init, quad_word op2_init, quad_word op3_init)
+{
+ int cc; // unused
+ _op1 = op1_init;
+ _op2 = op2_init;
+ _op3 = op3_init;
+
+ __asm__ volatile (
+ "lmg %%r0,%%r1,%1\n\t"
+ "lmg %%r2,%%r3,%3\n\t"
+ "cdsg %%r0,%%r2,%2\n\t" // cdsg 1st,3rd,2nd
+ "stmg %%r0,%%r1,%1\n" // store r0,r1 to op1
+ "stmg %%r2,%%r3,%3\n" // store r2,r3 to op3
+ : "=d"(cc), "+QS" (_op1), "+QS" (_op2), "+QS" (_op3)
+ :
+ : "r0", "r1", "r2", "r3", "cc");
+}
+
+void op1_undefined(void)
+{
+ quad_word op1, op2, op3;
+
+ // op1 undefined
+ op2.high = op2.low = 42;
+ op3.high = op3.low = 0xdeadbeefdeadbabeull;
+ test(op1, op2, op3); // complaint
+}
+
+void op2_undefined(void)
+{
+ quad_word op1, op2, op3;
+
+ op1.high = op1.low = 42;
+ // op2 undefined
+ op3.high = op3.low = 0xdeadbeefdeadbabeull;
+ test(op1, op2, op3); // complaint
+}
+
+void op3_undefined(void)
+{
+ quad_word op1, op2, op3;
+
+ op1.high = op1.low = 42;
+ op2 = op1;
+ // op3 undefined
+ test(op1, op2, op3); // no complaint; op3 is just copied around
+}
+
+int main ()
+{
+ op1_undefined();
+ op2_undefined();
+ op3_undefined();
+
+ return 0;
+}
diff --git a/main/memcheck/tests/s390x/cdsg.stderr.exp b/main/memcheck/tests/s390x/cdsg.stderr.exp
new file mode 100644
index 0000000..3c71e21
--- /dev/null
+++ b/main/memcheck/tests/s390x/cdsg.stderr.exp
@@ -0,0 +1,10 @@
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: test (cdsg.c:21)
+ by 0x........: op1_undefined (cdsg.c:39)
+ by 0x........: main (cdsg.c:64)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: test (cdsg.c:21)
+ by 0x........: op2_undefined (cdsg.c:49)
+ by 0x........: main (cdsg.c:65)
+
diff --git a/main/memcheck/tests/amd64/int3-amd64.stdout.exp b/main/memcheck/tests/s390x/cdsg.stdout.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stdout.exp
copy to main/memcheck/tests/s390x/cdsg.stdout.exp
diff --git a/main/memcheck/tests/s390x/cdsg.vgtest b/main/memcheck/tests/s390x/cdsg.vgtest
new file mode 100644
index 0000000..598fd68
--- /dev/null
+++ b/main/memcheck/tests/s390x/cdsg.vgtest
@@ -0,0 +1,2 @@
+prog: cdsg
+vgopts: -q
diff --git a/main/memcheck/tests/s390x/cs.c b/main/memcheck/tests/s390x/cs.c
new file mode 100644
index 0000000..9a298ce
--- /dev/null
+++ b/main/memcheck/tests/s390x/cs.c
@@ -0,0 +1,32 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+void
+test(int32_t op1_init, int32_t op2_init, int32_t op3_init)
+{
+ register int32_t op1 asm("8") = op1_init;
+ register int32_t op3 asm("9") = op3_init;
+
+ int32_t op2 = op2_init;
+ int cc = 1;
+
+ __asm__ volatile (
+ "cs 8,9,%1\n\t"
+ "ipm %0\n\t"
+ "srl %0,28\n\t"
+ : "=d" (cc), "+Q" (op2), "+d"(op1), "+d"(op3)
+ :
+ : "cc");
+}
+
+int main ()
+{
+ int op1, op2, op3;
+
+ test(op1, 0x10000000, 0x12345678); // complaint
+ test(0x10000000, op2, 0x12345678); // complaint
+ test(0x10000000, 0x01000000, op3); // no complaint
+
+ return 0;
+}
diff --git a/main/memcheck/tests/s390x/cs.stderr.exp b/main/memcheck/tests/s390x/cs.stderr.exp
new file mode 100644
index 0000000..e45dc99
--- /dev/null
+++ b/main/memcheck/tests/s390x/cs.stderr.exp
@@ -0,0 +1,8 @@
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: test (cs.c:14)
+ by 0x........: main (cs.c:27)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: test (cs.c:14)
+ by 0x........: main (cs.c:28)
+
diff --git a/main/memcheck/tests/amd64/int3-amd64.stdout.exp b/main/memcheck/tests/s390x/cs.stdout.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stdout.exp
copy to main/memcheck/tests/s390x/cs.stdout.exp
diff --git a/main/memcheck/tests/s390x/cs.vgtest b/main/memcheck/tests/s390x/cs.vgtest
new file mode 100644
index 0000000..323cce8
--- /dev/null
+++ b/main/memcheck/tests/s390x/cs.vgtest
@@ -0,0 +1,2 @@
+prog: cs
+vgopts: -q
diff --git a/main/memcheck/tests/s390x/csg.c b/main/memcheck/tests/s390x/csg.c
new file mode 100644
index 0000000..7f9d8c8
--- /dev/null
+++ b/main/memcheck/tests/s390x/csg.c
@@ -0,0 +1,32 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+void
+test(int64_t op1_init, int64_t op2_init, int64_t op3_init)
+{
+ register int64_t op1 asm("8") = op1_init;
+ register int64_t op3 asm("9") = op3_init;
+
+ int64_t op2 = op2_init;
+ int cc = 1;
+
+ __asm__ volatile (
+ "csg 8,9,%1\n\t"
+ "ipm %0\n\t"
+ "srl %0,28\n\t"
+ : "=d" (cc), "+Q" (op2), "+d"(op1), "+d"(op3)
+ :
+ : "cc");
+}
+
+int main ()
+{
+ int64_t op1, op2, op3;
+
+ test(op1, 0x1000000000000000ull, 0x1234567887654321ull); // complaint
+ test(0x1000000000000000ull, op2, 0x1234567887654321ull); // complaint
+ test(0x1000000000000000ull, 0x1000000000000000ull, op3); // no complaint
+
+ return 0;
+}
diff --git a/main/memcheck/tests/s390x/csg.stderr.exp b/main/memcheck/tests/s390x/csg.stderr.exp
new file mode 100644
index 0000000..fda2021
--- /dev/null
+++ b/main/memcheck/tests/s390x/csg.stderr.exp
@@ -0,0 +1,8 @@
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: test (csg.c:14)
+ by 0x........: main (csg.c:27)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: test (csg.c:14)
+ by 0x........: main (csg.c:28)
+
diff --git a/main/memcheck/tests/amd64/int3-amd64.stdout.exp b/main/memcheck/tests/s390x/csg.stdout.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stdout.exp
copy to main/memcheck/tests/s390x/csg.stdout.exp
diff --git a/main/memcheck/tests/s390x/csg.vgtest b/main/memcheck/tests/s390x/csg.vgtest
new file mode 100644
index 0000000..6de75c1
--- /dev/null
+++ b/main/memcheck/tests/s390x/csg.vgtest
@@ -0,0 +1,2 @@
+prog: csg
+vgopts: -q
diff --git a/main/memcheck/tests/s390x/cu21.c b/main/memcheck/tests/s390x/cu21.c
new file mode 100644
index 0000000..dd9654b
--- /dev/null
+++ b/main/memcheck/tests/s390x/cu21.c
@@ -0,0 +1,122 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "../../../none/tests/s390x/opcodes.h"
+
+/* Define various input buffers. */
+
+/* U+0000 to U+007f: Result is 1 byte for each uint16_t */
+uint16_t pattern1[] = {
+ 0x0000, 0x007f, /* corner cases */
+ 0x0047, 0x0056, 0x0045, 0x0021, 0x007b, 0x003a /* misc */
+};
+
+/* U+0080 to U+07ff: Result is 2 bytes for each uint16_t */
+uint16_t pattern2[] = {
+ 0x0080, 0x07ff, /* corner cases */
+ 0x07df, 0x008f, 0x0100, 0x017f, 0x052f, 0x0600, 0x06ff /* misc */
+};
+
+/* U+0800 to U+d7ff: Result is 3 bytes for each uint16_t
+ U+dc00 to U+ffff: Result is 3 bytes for each uint16_t */
+uint16_t pattern3[] = {
+ 0x0800, 0xd7ff, /* corner cases */
+ 0xdc00, 0xffff, /* corner cases */
+ 0x083f, 0x1a21, 0x1b10, 0x2200, 0x225e, 0x22c9, 0xe001 /* misc */
+};
+
+/* U+d800 to U+dbff: Result is 4 bytes for each uint16_t pair */
+uint16_t pattern4[] = {
+ 0xd800, 0xdc00, /* left corner case */
+ 0xdbff, 0xdfff, /* right corner case */
+ 0xdada, 0xdddd, 0xdeaf, 0xdcdc /* misc */
+};
+
+
+void
+do_cu21(uint8_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ /* build up the register pairs */
+ register uint16_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint8_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU21(0,2,4)
+ : "+d"(dest), "+d"(source), "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+ return;
+}
+
+int main()
+{
+ /*------------------------------------------------------------*/
+ /* Write to a too small buffer */
+ /*------------------------------------------------------------*/
+
+ /* Write 2 bytes into buffer of length 1 */
+ do_cu21(malloc(1), 10, pattern2, 2); // complaint (2 bytes)
+
+ /* Write 2 bytes into buffer of length 2 */
+ do_cu21(malloc(2), 10, pattern2, 2); // no complaint
+
+ /* Write 3 bytes into buffer of length 1 */
+ do_cu21(malloc(1), 10, pattern3, 2); // 2 complaints (3 = 2+1)
+
+ /* Write 3 bytes into buffer of length 2 */
+ do_cu21(malloc(2), 10, pattern3, 2); // complaint (1 byte)
+
+ /* Write 3 bytes into buffer of length 3 */
+ do_cu21(malloc(3), 10, pattern3, 2); // no complaint
+
+ /* Write 4 bytes into buffer of length 1 */
+ do_cu21(malloc(1), 10, pattern4, 4); // complaint (4 bytes)
+
+ /* Write 4 bytes into buffer of length 2 */
+ do_cu21(malloc(2), 10, pattern4, 4); // complaint (4 bytes)
+
+ /* Write 4 bytes into buffer of length 3 */
+ do_cu21(malloc(3), 10, pattern4, 4); // complaint (4 bytes)
+
+ /* Write 4 bytes into buffer of length 4 */
+ do_cu21(malloc(4), 10, pattern4, 4); // no complaint
+
+ /*------------------------------------------------------------*/
+ /* Read uninitialised data */
+ /*------------------------------------------------------------*/
+ uint8_t *input = malloc(10);
+
+ /* Input buffer is completely uninitialised */
+ do_cu21(malloc(4), 4, (void *)input, 2); // complaint
+
+ /* Read 2 bytes from input buffer. First byte is uninitialised */
+ input = malloc(10);
+ input[1] = 0x0;
+ do_cu21(malloc(4), 4, (void *)input, 2); // complaint
+
+ /* Read 2 bytes from input buffer. Second byte is uninitialised */
+ input = malloc(10);
+ input[0] = 0x0;
+ do_cu21(malloc(4), 4, (void *)input, 2); // complaint
+
+ /* Read 2 bytes from input buffer. All bytes are initialised */
+ input = malloc(10);
+ input[0] = input[1] = 0x0;
+ do_cu21(malloc(4), 4, (void *)input, 2); // no complaint
+
+ /* Read 4 bytes from input buffer. This iterates once. In the 1st
+ iteration all input bytes are initialised in the 2nd iteration all
+ input bytes are uninitialised. */
+ input = malloc(10);
+ input[0] = input[1] = 0x0;
+ do_cu21(malloc(4), 4, (void *)input, 4); // complaint
+
+ /* Write to NULL */
+ // do_cu21(NULL, 10, pattern1, sizeof pattern1); // complaint
+
+ return 0;
+}
diff --git a/main/memcheck/tests/s390x/cu21.stderr.exp b/main/memcheck/tests/s390x/cu21.stderr.exp
new file mode 100644
index 0000000..25563f2
--- /dev/null
+++ b/main/memcheck/tests/s390x/cu21.stderr.exp
@@ -0,0 +1,65 @@
+Invalid write of size 2
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:62)
+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu21.c:62)
+
+Invalid write of size 2
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:68)
+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu21.c:68)
+
+Invalid write of size 1
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:68)
+ Address 0x........ is 1 bytes after a block of size 1 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu21.c:68)
+
+Invalid write of size 1
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:71)
+ Address 0x........ is 0 bytes after a block of size 2 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu21.c:71)
+
+Invalid write of size 4
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:77)
+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu21.c:77)
+
+Invalid write of size 4
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:80)
+ Address 0x........ is 0 bytes inside a block of size 2 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu21.c:80)
+
+Invalid write of size 4
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:83)
+ Address 0x........ is 0 bytes inside a block of size 3 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu21.c:83)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:94)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:99)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:104)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu21 (cu21.c:45)
+ by 0x........: main (cu21.c:116)
+
diff --git a/main/memcheck/tests/amd64/int3-amd64.stdout.exp b/main/memcheck/tests/s390x/cu21.stdout.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stdout.exp
copy to main/memcheck/tests/s390x/cu21.stdout.exp
diff --git a/main/memcheck/tests/s390x/cu21.vgtest b/main/memcheck/tests/s390x/cu21.vgtest
new file mode 100644
index 0000000..10e7606
--- /dev/null
+++ b/main/memcheck/tests/s390x/cu21.vgtest
@@ -0,0 +1,2 @@
+prog: cu21
+vgopts: -q
diff --git a/main/memcheck/tests/s390x/cu42.c b/main/memcheck/tests/s390x/cu42.c
new file mode 100644
index 0000000..185b0dd
--- /dev/null
+++ b/main/memcheck/tests/s390x/cu42.c
@@ -0,0 +1,111 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "../../../none/tests/s390x/opcodes.h"
+
+/* Define various input buffers. */
+
+/* U+0000 to U+d7ff: Result is 2 bytes for each uint32_t
+ U+dc00 to U+ffff: Result is 2 bytes for each uint32_t */
+uint32_t pattern2[] = {
+ 0x0000, 0xd7ff, /* corner cases */
+ 0xdc00, 0xffff, /* corner cases */
+ 0xabba, 0xf00d, 0xd00f, 0x1234 /* misc */
+};
+
+/* U+00010000 to U+0010ffff: Result is 4 bytes for each uint32_t */
+uint32_t pattern4[] = {
+ 0x00010000, 0x0010ffff, /* corner cases */
+ 0x00010123, 0x00023456, 0x000789ab, 0x00100000 /* misc */
+};
+
+static void
+do_cu42(uint16_t *dst, uint64_t dst_len, uint32_t *src, uint64_t src_len)
+{
+ /* build up the register pairs */
+ register uint32_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint16_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU42(2,4)
+ : "+d"(dest), "+d"(source), "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+}
+
+int main()
+{
+ /*------------------------------------------------------------*/
+ /* Write to a too small buffer */
+ /*------------------------------------------------------------*/
+
+ /* Write 2 bytes into buffer of length 1 */
+ do_cu42(malloc(1), 10, pattern2, 4); // complaint (2 bytes)
+
+ /* Write 2 bytes into buffer of length 2 */
+ do_cu42(malloc(2), 10, pattern2, 4); // no complaint
+
+ /* Write 4 bytes into buffer of length 1 */
+ do_cu42(malloc(1), 10, pattern4, 4); // complaint (4 bytes)
+
+ /* Write 4 bytes into buffer of length 2 */
+ do_cu42(malloc(2), 10, pattern4, 4); // complaint (4 bytes)
+
+ /* Write 4 bytes into buffer of length 3 */
+ do_cu42(malloc(3), 10, pattern4, 4); // complaint (4 bytes)
+
+ /* Write 4 bytes into buffer of length 4 */
+ do_cu42(malloc(4), 10, pattern4, 4); // no complaint
+
+ /*------------------------------------------------------------*/
+ /* Read uninitialised data */
+ /*------------------------------------------------------------*/
+ uint16_t buf[100];
+ uint8_t *input;
+
+ /* Input buffer is completely uninitialised */
+ input = malloc(10);
+ do_cu42(buf, sizeof buf, (void *)input, 4); // complaint
+
+ /* Read 4 bytes from input buffer. First byte is uninitialised */
+ input = malloc(10);
+ input[1] = input[2] = input[3] = 0x0;
+ do_cu42(buf, sizeof buf, (void *)input, 4); // complaint
+
+ /* Read 4 bytes from input buffer. Second byte is uninitialised */
+ input = malloc(10);
+ input[0] = input[2] = input[3] = 0x0;
+ do_cu42(buf, sizeof buf, (void *)input, 4); // complaint
+
+ /* Read 4 bytes from input buffer. Third byte is uninitialised */
+ input = malloc(10);
+ input[0] = input[1] = input[3] = 0x0;
+ do_cu42(buf, sizeof buf, (void *)input, 4); // complaint
+
+ /* Read 4 bytes from input buffer. Fourth byte is uninitialised */
+ input = malloc(10);
+ input[0] = input[1] = input[2] = 0x0;
+ do_cu42(buf, sizeof buf, (void *)input, 4); // complaint
+
+ /* Read 4 bytes from input buffer. All bytes are initialised */
+ input = malloc(10);
+ memset(input, 0, 4);
+ do_cu42(buf, sizeof buf, (void *)input, 4); // no complaint
+
+ /* Read 8 bytes from input buffer. This iterates once. In the 1st
+ iteration all input bytes are initialised in the 2nd iteration all
+ input bytes are uninitialised. */
+ input = malloc(10);
+ memset(input, 0, 4);
+ do_cu42(buf, sizeof buf, (void *)input, 8); // complaint
+
+
+ /* Write to NULL */
+ // do_cu42(NULL, 10, pattern1, sizeof pattern1); // complaint
+
+ return 0;
+}
diff --git a/main/memcheck/tests/s390x/cu42.stderr.exp b/main/memcheck/tests/s390x/cu42.stderr.exp
new file mode 100644
index 0000000..246b22a
--- /dev/null
+++ b/main/memcheck/tests/s390x/cu42.stderr.exp
@@ -0,0 +1,52 @@
+Invalid write of size 2
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:47)
+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu42.c:47)
+
+Invalid write of size 4
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:53)
+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu42.c:53)
+
+Invalid write of size 4
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:56)
+ Address 0x........ is 0 bytes inside a block of size 2 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu42.c:56)
+
+Invalid write of size 4
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:59)
+ Address 0x........ is 0 bytes inside a block of size 3 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (cu42.c:59)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:72)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:77)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:82)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:87)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:92)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: do_cu42 (cu42.c:31)
+ by 0x........: main (cu42.c:104)
+
diff --git a/main/memcheck/tests/amd64/int3-amd64.stdout.exp b/main/memcheck/tests/s390x/cu42.stdout.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stdout.exp
copy to main/memcheck/tests/s390x/cu42.stdout.exp
diff --git a/main/memcheck/tests/s390x/cu42.vgtest b/main/memcheck/tests/s390x/cu42.vgtest
new file mode 100644
index 0000000..c1d9551
--- /dev/null
+++ b/main/memcheck/tests/s390x/cu42.vgtest
@@ -0,0 +1,2 @@
+prog: cu42
+vgopts: -q
diff --git a/main/memcheck/tests/s390x/filter_stderr b/main/memcheck/tests/s390x/filter_stderr
new file mode 100755
index 0000000..a778e97
--- /dev/null
+++ b/main/memcheck/tests/s390x/filter_stderr
@@ -0,0 +1,3 @@
+#! /bin/sh
+
+../filter_stderr "$@"
diff --git a/main/memcheck/tests/sigkill.stderr.exp-mips32 b/main/memcheck/tests/sigkill.stderr.exp-mips32
new file mode 100644
index 0000000..de4a860
--- /dev/null
+++ b/main/memcheck/tests/sigkill.stderr.exp-mips32
@@ -0,0 +1,197 @@
+
+setting signal 1: Success
+getting signal 1: Success
+
+setting signal 2: Success
+getting signal 2: Success
+
+setting signal 3: Success
+getting signal 3: Success
+
+setting signal 4: Success
+getting signal 4: Success
+
+setting signal 5: Success
+getting signal 5: Success
+
+setting signal 6: Success
+getting signal 6: Success
+
+setting signal 7: Success
+getting signal 7: Success
+
+setting signal 8: Success
+getting signal 8: Success
+
+setting signal 9: Warning: ignored attempt to set SIGKILL handler in sigaction();
+ the SIGKILL signal is uncatchable
+Invalid argument
+getting signal 9: Success
+
+setting signal 10: Success
+getting signal 10: Success
+
+setting signal 11: Success
+getting signal 11: Success
+
+setting signal 12: Success
+getting signal 12: Success
+
+setting signal 13: Success
+getting signal 13: Success
+
+setting signal 14: Success
+getting signal 14: Success
+
+setting signal 15: Success
+getting signal 15: Success
+
+setting signal 16: Success
+getting signal 16: Success
+
+setting signal 17: Success
+getting signal 17: Success
+
+setting signal 18: Success
+getting signal 18: Success
+
+setting signal 19: Success
+getting signal 19: Success
+
+setting signal 20: Success
+getting signal 20: Success
+
+setting signal 21: Success
+getting signal 21: Success
+
+setting signal 22: Success
+getting signal 22: Success
+
+setting signal 23: Warning: ignored attempt to set SIGSTOP handler in sigaction();
+ the SIGSTOP signal is uncatchable
+Invalid argument
+getting signal 23: Success
+
+setting signal 24: Success
+getting signal 24: Success
+
+setting signal 25: Success
+getting signal 25: Success
+
+setting signal 26: Success
+getting signal 26: Success
+
+setting signal 27: Success
+getting signal 27: Success
+
+setting signal 28: Success
+getting signal 28: Success
+
+setting signal 29: Success
+getting signal 29: Success
+
+setting signal 30: Success
+getting signal 30: Success
+
+setting signal 31: Success
+getting signal 31: Success
+
+setting signal 34: Success
+getting signal 34: Success
+
+setting signal 35: Success
+getting signal 35: Success
+
+setting signal 36: Success
+getting signal 36: Success
+
+setting signal 37: Success
+getting signal 37: Success
+
+setting signal 38: Success
+getting signal 38: Success
+
+setting signal 39: Success
+getting signal 39: Success
+
+setting signal 40: Success
+getting signal 40: Success
+
+setting signal 41: Success
+getting signal 41: Success
+
+setting signal 42: Success
+getting signal 42: Success
+
+setting signal 43: Success
+getting signal 43: Success
+
+setting signal 44: Success
+getting signal 44: Success
+
+setting signal 45: Success
+getting signal 45: Success
+
+setting signal 46: Success
+getting signal 46: Success
+
+setting signal 47: Success
+getting signal 47: Success
+
+setting signal 48: Success
+getting signal 48: Success
+
+setting signal 49: Success
+getting signal 49: Success
+
+setting signal 50: Success
+getting signal 50: Success
+
+setting signal 51: Success
+getting signal 51: Success
+
+setting signal 52: Success
+getting signal 52: Success
+
+setting signal 53: Success
+getting signal 53: Success
+
+setting signal 54: Success
+getting signal 54: Success
+
+setting signal 55: Success
+getting signal 55: Success
+
+setting signal 56: Success
+getting signal 56: Success
+
+setting signal 57: Success
+getting signal 57: Success
+
+setting signal 58: Success
+getting signal 58: Success
+
+setting signal 59: Success
+getting signal 59: Success
+
+setting signal 60: Success
+getting signal 60: Success
+
+setting signal 61: Success
+getting signal 61: Success
+
+setting signal 62: Success
+getting signal 62: Success
+
+setting signal 65: Success
+getting signal 65: Success
+
+
+HEAP SUMMARY:
+ in use at exit: ... bytes in ... blocks
+ total heap usage: ... allocs, ... frees, ... bytes allocated
+
+For a detailed leak analysis, rerun with: --leak-check=full
+
+For counts of detected and suppressed errors, rerun with: -v
+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0)
diff --git a/main/memcheck/tests/static_malloc.c b/main/memcheck/tests/static_malloc.c
new file mode 100644
index 0000000..22def9e
--- /dev/null
+++ b/main/memcheck/tests/static_malloc.c
@@ -0,0 +1,21 @@
+#include <stdio.h>
+
+static char buf[10000];
+static int bufi = 0;
+void* malloc(size_t i) {
+ bufi += i;
+ return buf + bufi - i;
+}
+
+void free(void*ptr) {
+}
+
+int main (void)
+{
+ char *p;
+ p = malloc(10);
+ p = malloc(123);
+ free(p);
+ return 0;
+}
+
diff --git a/main/memcheck/tests/static_malloc.stderr.exp b/main/memcheck/tests/static_malloc.stderr.exp
new file mode 100644
index 0000000..5090107
--- /dev/null
+++ b/main/memcheck/tests/static_malloc.stderr.exp
@@ -0,0 +1,4 @@
+10 bytes in 1 blocks are definitely lost in loss record ... of ...
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (static_malloc.c:16)
+
diff --git a/main/memcheck/tests/static_malloc.vgtest b/main/memcheck/tests/static_malloc.vgtest
new file mode 100644
index 0000000..7d3a455
--- /dev/null
+++ b/main/memcheck/tests/static_malloc.vgtest
@@ -0,0 +1,2 @@
+prog: static_malloc
+vgopts: -q --leak-check=full --soname-synonyms=somalloc=NONE
diff --git a/main/memcheck/tests/strchr.stderr.exp3 b/main/memcheck/tests/strchr.stderr.exp3
new file mode 100644
index 0000000..9f90e69
--- /dev/null
+++ b/main/memcheck/tests/strchr.stderr.exp3
@@ -0,0 +1,12 @@
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: __GI_strchr (mc_replace_strmem.c:211)
+ by 0x........: main (strchr.c:15)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: __GI_strchr (mc_replace_strmem.c:211)
+ by 0x........: main (strchr.c:15)
+
+Conditional jump or move depends on uninitialised value(s)
+ at 0x........: __GI_strrchr (mc_replace_strmem.c:...)
+ by 0x........: main (strchr.c:16)
+
diff --git a/main/memcheck/tests/supp_unknown.stderr.exp-kfail b/main/memcheck/tests/supp_unknown.stderr.exp-kfail
new file mode 100644
index 0000000..8a8d02f
--- /dev/null
+++ b/main/memcheck/tests/supp_unknown.stderr.exp-kfail
@@ -0,0 +1,9 @@
+
+Process terminating with default action of signal 11 (SIGSEGV)
+ Access not within mapped region at address 0x........
+ ...
+ If you believe this happened as a result of a stack
+ overflow in your program's main thread (unlikely but
+ possible), you can try to increase the size of the
+ main thread stack using the --main-stacksize= flag.
+ The main thread stack size used in this run was ....
diff --git a/main/memcheck/tests/suppfree.supp b/main/memcheck/tests/suppfree.supp
new file mode 100644
index 0000000..fd4724a
--- /dev/null
+++ b/main/memcheck/tests/suppfree.supp
@@ -0,0 +1,57 @@
+{
+ nonmatching1
+ Memcheck:Free
+ fun:free
+ fun:dd
+ fun:ccc
+ fun:bbb
+ fun:aaa
+ fun:main
+}
+
+{
+ nonmatching2
+ Memcheck:Free
+ fun:free
+ fun:ddd
+ fun:cc
+ fun:bbb
+ fun:aaa
+ fun:main
+}
+
+{
+ nonmatching3
+ Memcheck:Free
+ fun:free
+ fun:ddd
+ fun:ccc
+ fun:xxxxxxxx
+ fun:bbb
+ fun:aaa
+ fun:main
+}
+
+{
+ nonmatching4
+ Memcheck:Free
+ fun:free
+ fun:ddd
+ fun:ccc
+ ...
+ fun:bbb
+ fun:aaa
+ fun:main
+ fun:nonmatching
+}
+
+{
+ nonmatching5
+ Memcheck:Free
+ fun:free
+ fun:ddd
+ obj:nonmatching
+ fun:bbb
+ fun:aaa
+ fun:main
+}
diff --git a/main/memcheck/tests/suppfree.vgtest b/main/memcheck/tests/suppfree.vgtest
index a7789c3..dbdfec7 100644
--- a/main/memcheck/tests/suppfree.vgtest
+++ b/main/memcheck/tests/suppfree.vgtest
@@ -1,2 +1,2 @@
prog: suppfree
-vgopts: -q
+vgopts: --suppressions=suppfree.supp -q
diff --git a/main/memcheck/tests/test-plo-no.stderr.exp-le32 b/main/memcheck/tests/test-plo-no.stderr.exp-le32
new file mode 100644
index 0000000..d473e5a
--- /dev/null
+++ b/main/memcheck/tests/test-plo-no.stderr.exp-le32
@@ -0,0 +1,18 @@
+Invalid read of size 4
+ ...
+ Address 0x........ is 4 bytes inside a block of size 5 alloc'd
+ at 0x........: memalign (vg_replace_malloc.c:...)
+ ...
+
+Invalid read of size 4
+ ...
+ Address 0x........ is 4 bytes inside a block of size 5 alloc'd
+ at 0x........: memalign (vg_replace_malloc.c:...)
+ ...
+
+Invalid read of size 4
+ ...
+ Address 0x........ is 4 bytes inside a block of size 12 free'd
+ at 0x........: free (vg_replace_malloc.c:...)
+ ...
+
diff --git a/main/memcheck/tests/test-plo-no.stderr.exp-le64 b/main/memcheck/tests/test-plo-no.stderr.exp-le64
new file mode 100644
index 0000000..0099d1b
--- /dev/null
+++ b/main/memcheck/tests/test-plo-no.stderr.exp-le64
@@ -0,0 +1,18 @@
+Invalid read of size 8
+ ...
+ Address 0x........ is 0 bytes inside a block of size 5 alloc'd
+ at 0x........: memalign (vg_replace_malloc.c:...)
+ ...
+
+Invalid read of size 8
+ ...
+ Address 0x........ is 0 bytes inside a block of size 5 alloc'd
+ at 0x........: memalign (vg_replace_malloc.c:...)
+ ...
+
+Invalid read of size 8
+ ...
+ Address 0x........ is 8 bytes inside a block of size 24 free'd
+ at 0x........: free (vg_replace_malloc.c:...)
+ ...
+
diff --git a/main/memcheck/tests/test-plo-no.stderr.exp-s390x-mvc b/main/memcheck/tests/test-plo-no.stderr.exp-s390x-mvc
new file mode 100644
index 0000000..d050e0b
--- /dev/null
+++ b/main/memcheck/tests/test-plo-no.stderr.exp-s390x-mvc
@@ -0,0 +1,18 @@
+Invalid read of size 1
+ ...
+ Address 0x........ is 0 bytes after a block of size 5 alloc'd
+ at 0x........: memalign (vg_replace_malloc.c:...)
+ ...
+
+Invalid read of size 1
+ ...
+ Address 0x........ is 0 bytes after a block of size 5 alloc'd
+ at 0x........: memalign (vg_replace_malloc.c:...)
+ ...
+
+Invalid read of size 1
+ ...
+ Address 0x........ is 8 bytes inside a block of size 24 free'd
+ at 0x........: free (vg_replace_malloc.c:...)
+ ...
+
diff --git a/main/memcheck/tests/amd64/int3-amd64.stdout.exp b/main/memcheck/tests/test-plo-no.stdout.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stdout.exp
copy to main/memcheck/tests/test-plo-no.stdout.exp
diff --git a/main/memcheck/tests/test-plo-no.vgtest b/main/memcheck/tests/test-plo-no.vgtest
new file mode 100644
index 0000000..247a134
--- /dev/null
+++ b/main/memcheck/tests/test-plo-no.vgtest
@@ -0,0 +1,2 @@
+prog: test-plo
+vgopts: -q
diff --git a/main/memcheck/tests/test-plo-yes.stderr.exp-le32 b/main/memcheck/tests/test-plo-yes.stderr.exp-le32
new file mode 100644
index 0000000..9d3388c
--- /dev/null
+++ b/main/memcheck/tests/test-plo-yes.stderr.exp-le32
@@ -0,0 +1,9 @@
+Conditional jump or move depends on uninitialised value(s)
+ ...
+
+Invalid read of size 4
+ ...
+ Address 0x........ is 4 bytes inside a block of size 12 free'd
+ at 0x........: free (vg_replace_malloc.c:...)
+ ...
+
diff --git a/main/memcheck/tests/test-plo-yes.stderr.exp-le64 b/main/memcheck/tests/test-plo-yes.stderr.exp-le64
new file mode 100644
index 0000000..22fc3c0
--- /dev/null
+++ b/main/memcheck/tests/test-plo-yes.stderr.exp-le64
@@ -0,0 +1,9 @@
+Conditional jump or move depends on uninitialised value(s)
+ ...
+
+Invalid read of size 8
+ ...
+ Address 0x........ is 8 bytes inside a block of size 24 free'd
+ at 0x........: free (vg_replace_malloc.c:...)
+ ...
+
diff --git a/main/memcheck/tests/amd64/int3-amd64.stdout.exp b/main/memcheck/tests/test-plo-yes.stdout.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stdout.exp
copy to main/memcheck/tests/test-plo-yes.stdout.exp
diff --git a/main/memcheck/tests/test-plo-yes.vgtest b/main/memcheck/tests/test-plo-yes.vgtest
new file mode 100644
index 0000000..94422ad
--- /dev/null
+++ b/main/memcheck/tests/test-plo-yes.vgtest
@@ -0,0 +1,3 @@
+prereq: test ! `../../tests/arch_test ppc32` && ! `../../tests/arch_test ppc64` && ! `../../tests/arch_test s390x`
+prog: test-plo
+vgopts: -q --partial-loads-ok=yes
diff --git a/main/memcheck/tests/test-plo.c b/main/memcheck/tests/test-plo.c
new file mode 100644
index 0000000..5d4da6b
--- /dev/null
+++ b/main/memcheck/tests/test-plo.c
@@ -0,0 +1,86 @@
+#include "tests/malloc.h"
+#include <stdio.h>
+#include <assert.h>
+
+typedef unsigned long long int ULong;
+typedef unsigned long int UWord;
+
+__attribute__((noinline))
+static int my_ffsll ( ULong x )
+{
+ int i;
+ for (i = 0; i < 64; i++) {
+ if ((x & 1ULL) == 1ULL)
+ break;
+ x >>= 1;
+ }
+ return i+1;
+}
+
+/* Find length of string, assuming it is aligned and shorter than 8
+ characters. Little-endian only. */
+__attribute__((noinline))
+static int aligned_strlen(char *s)
+{
+ /* This is for 64-bit platforms */
+ assert(sizeof(ULong) == 8);
+ /* ..and only works for aligned input */
+ assert(((unsigned long)s & 0x7) == 0);
+
+ /* read 8 bytes */
+ ULong val = *(ULong*)s;
+ /* Subtract one from each byte */
+ ULong val2 = val - 0x0101010101010101ULL;
+ /* Find lowest byte whose high bit changed */
+ val2 ^= val;
+ val2 &= 0x8080808080808080ULL;
+
+ return (my_ffsll(val2) / 8) - 1;
+}
+
+__attribute__((noinline)) void foo ( int x )
+{
+ __asm__ __volatile__("":::"memory");
+}
+
+int
+main(int argc, char *argv[])
+{
+ char *buf = memalign16(5);
+ buf[0] = 'a';
+ buf[1] = 'b';
+ buf[2] = 'c';
+ buf[3] = 'd';
+ buf[4] = '\0';
+
+ /* --partial-loads-ok=no: expect addr error (here) */
+ /* --partial-loads-ok=yes: expect no error */
+ if (aligned_strlen(buf) == 4)
+ foo(44);
+
+ /* --partial-loads-ok=no: expect addr error (here) */
+ /* --partial-loads-ok=yes: expect value error (in my_ffsll) */
+ buf[4] = 'x';
+ if (aligned_strlen(buf) == 0)
+ foo(37);
+
+ free(buf);
+
+ /* Also, we need to check that a completely out-of-range,
+ word-sized load gives an addressing error regardless of the
+ start of --partial-loads-ok=. *And* that the resulting
+ value is completely defined. */
+ UWord* words = malloc(3 * sizeof(UWord));
+ free(words);
+
+ /* Should ALWAYS give an addr error. */
+ UWord w = words[1];
+
+ /* Should NEVER give an error (you might expect a value one, but no.) */
+ if (w == 0x31415927) {
+ fprintf(stderr,
+ "Elvis is alive and well and living in Milton Keynes.\n");
+ }
+
+ return 0;
+}
diff --git a/main/memcheck/tests/unit_oset.c b/main/memcheck/tests/unit_oset.c
index f06f582..854edf1 100644
--- a/main/memcheck/tests/unit_oset.c
+++ b/main/memcheck/tests/unit_oset.c
@@ -27,7 +27,16 @@
#define vgPlain_printf printf
#define vgPlain_memset memset
#define vgPlain_memcpy memcpy
+#define vgPlain_memmove memmove
+// Crudely replace some functions (in m_xarray.c, but not needed for
+// this unit test) by (hopefully) failing asserts.
+#define vgPlain_ssort(a,b,c,d) assert(a)
+#define vgPlain_vcbprintf(a,b,...) assert(a == b)
+#include "coregrind/m_xarray.c"
+#undef vgPlain_ssort
+#undef vgPlain_vcbprintf
+#include "coregrind/m_poolalloc.c"
#include "coregrind/m_oset.c"
#define NN 1000 // Size of OSets being created
@@ -73,19 +82,13 @@
return *(Word*)vkey - *(Word*)velem;
}
-void example1(void)
+void example1singleset(OSet* oset, char *descr)
{
Int i, n;
Word v, prev;
Word* vs[NN];
Word *pv;
- // Create a static OSet of Ints. This one uses fast (built-in)
- // comparisons.
- OSet* oset = VG_(OSetGen_Create)(0,
- NULL,
- allocate_node, "oset_test.1", free_node);
-
// Try some operations on an empty OSet to ensure they don't screw up.
vg_assert( ! VG_(OSetGen_Contains)(oset, &v) );
vg_assert( ! VG_(OSetGen_Lookup)(oset, &v) );
@@ -201,12 +204,53 @@
}
// Print the list
- OSet_Print(oset, "oset1", wordToStr);
+ OSet_Print(oset, descr, wordToStr);
+
+}
+
+void example1(void)
+{
+ OSet *oset, *oset_empty_clone;
+
+ // Create a static OSet of Ints. This one uses fast (built-in)
+ // comparisons.
+
+ // First a single oset, no pool allocator.
+ oset = VG_(OSetGen_Create)(0,
+ NULL,
+ allocate_node, "oset_test.1", free_node);
+ example1singleset(oset, "single oset, no pool allocator");
// Destroy the OSet
VG_(OSetGen_Destroy)(oset);
-}
+ // Then same, but with a group allocator
+ oset = VG_(OSetGen_Create_With_Pool)(0,
+ NULL,
+ allocate_node, "oset_test.1",
+ free_node,
+ 101, sizeof(Word));
+ example1singleset(oset, "single oset, pool allocator");
+
+ // Destroy the OSet
+ VG_(OSetGen_Destroy)(oset);
+
+
+ // Then two sets, sharing a group allocator.
+ oset = VG_(OSetGen_Create_With_Pool)
+ (0,
+ NULL,
+ allocate_node, "oset_test.1", free_node,
+ 101, sizeof(Word));
+ oset_empty_clone = VG_(OSetGen_EmptyClone) (oset);
+ example1singleset(oset, "oset, shared pool");
+ example1singleset(oset_empty_clone, "cloned oset, shared pool");
+ // Destroy both OSet
+
+ VG_(OSetGen_Destroy)(oset_empty_clone);
+ VG_(OSetGen_Destroy)(oset);
+
+}
void example1b(void)
{
diff --git a/main/memcheck/tests/unit_oset.stdout.exp b/main/memcheck/tests/unit_oset.stdout.exp
index 81251cc..5ceb862 100644
--- a/main/memcheck/tests/unit_oset.stdout.exp
+++ b/main/memcheck/tests/unit_oset.stdout.exp
@@ -1,4 +1,4 @@
--- start oset1 ----------------
+-- start single oset, no pool allocator ----------------
.. .. .. .. .. .. .. .. .. 1998
.. .. .. .. .. .. .. .. 1996
.. .. .. .. .. .. .. .. .. .. 1994
@@ -996,7 +996,3004 @@
.. .. .. .. .. .. .. .. .. 4
.. .. .. .. .. .. .. .. 2
.. .. .. .. .. .. .. .. .. 0
--- end oset1 ----------------
+-- end single oset, no pool allocator ----------------
+-- start single oset, pool allocator ----------------
+.. .. .. .. .. .. .. .. .. 1998
+.. .. .. .. .. .. .. .. 1996
+.. .. .. .. .. .. .. .. .. .. 1994
+.. .. .. .. .. .. .. .. .. 1992
+.. .. .. .. .. .. .. .. .. .. 1990
+.. .. .. .. .. .. .. 1988
+.. .. .. .. .. .. .. .. .. 1986
+.. .. .. .. .. .. .. .. .. .. 1984
+.. .. .. .. .. .. .. .. 1982
+.. .. .. .. .. .. .. .. .. .. 1980
+.. .. .. .. .. .. .. .. .. 1978
+.. .. .. .. .. .. .. .. .. .. 1976
+.. .. .. .. .. .. 1974
+.. .. .. .. .. .. .. .. .. .. 1972
+.. .. .. .. .. .. .. .. .. 1970
+.. .. .. .. .. .. .. .. .. .. 1968
+.. .. .. .. .. .. .. .. 1966
+.. .. .. .. .. .. .. .. .. .. 1964
+.. .. .. .. .. .. .. .. .. 1962
+.. .. .. .. .. .. .. 1960
+.. .. .. .. .. .. .. .. .. .. 1958
+.. .. .. .. .. .. .. .. .. 1956
+.. .. .. .. .. .. .. .. 1954
+.. .. .. .. .. .. .. .. .. .. 1952
+.. .. .. .. .. .. .. .. .. 1950
+.. .. .. .. .. .. .. .. .. .. 1948
+.. .. .. .. .. 1946
+.. .. .. .. .. .. .. .. .. 1944
+.. .. .. .. .. .. .. .. 1942
+.. .. .. .. .. .. .. 1940
+.. .. .. .. .. .. .. .. .. .. 1938
+.. .. .. .. .. .. .. .. .. 1936
+.. .. .. .. .. .. .. .. 1934
+.. .. .. .. .. .. .. .. .. 1932
+.. .. .. .. .. .. 1930
+.. .. .. .. .. .. .. .. .. 1928
+.. .. .. .. .. .. .. .. .. .. 1926
+.. .. .. .. .. .. .. .. 1924
+.. .. .. .. .. .. .. .. .. .. 1922
+.. .. .. .. .. .. .. .. .. 1920
+.. .. .. .. .. .. .. .. .. .. 1918
+.. .. .. .. .. .. .. 1916
+.. .. .. .. .. .. .. .. .. 1914
+.. .. .. .. .. .. .. .. 1912
+.. .. .. .. .. .. .. .. .. .. 1910
+.. .. .. .. .. .. .. .. .. 1908
+.. .. .. .. .. .. .. .. .. .. 1906
+.. .. .. .. 1904
+.. .. .. .. .. .. .. .. .. 1902
+.. .. .. .. .. .. .. .. 1900
+.. .. .. .. .. .. .. 1898
+.. .. .. .. .. .. .. .. .. 1896
+.. .. .. .. .. .. .. .. 1894
+.. .. .. .. .. .. .. .. .. 1892
+.. .. .. .. .. .. 1890
+.. .. .. .. .. .. .. .. .. .. 1888
+.. .. .. .. .. .. .. .. .. 1886
+.. .. .. .. .. .. .. .. .. .. 1884
+.. .. .. .. .. .. .. .. 1882
+.. .. .. .. .. .. .. .. .. 1880
+.. .. .. .. .. .. .. 1878
+.. .. .. .. .. .. .. .. 1876
+.. .. .. .. .. .. .. .. .. 1874
+.. .. .. .. .. 1872
+.. .. .. .. .. .. .. .. .. .. 1870
+.. .. .. .. .. .. .. .. .. 1868
+.. .. .. .. .. .. .. .. .. .. 1866
+.. .. .. .. .. .. .. .. 1864
+.. .. .. .. .. .. .. .. .. 1862
+.. .. .. .. .. .. .. .. .. .. 1860
+.. .. .. .. .. .. .. 1858
+.. .. .. .. .. .. .. .. .. 1856
+.. .. .. .. .. .. .. .. 1854
+.. .. .. .. .. .. .. .. .. 1852
+.. .. .. .. .. .. 1848
+.. .. .. .. .. .. .. .. .. 1846
+.. .. .. .. .. .. .. .. 1844
+.. .. .. .. .. .. .. .. .. .. 1842
+.. .. .. .. .. .. .. .. .. 1840
+.. .. .. .. .. .. .. 1838
+.. .. .. .. .. .. .. .. .. .. 1836
+.. .. .. .. .. .. .. .. .. 1834
+.. .. .. .. .. .. .. .. .. .. 1832
+.. .. .. .. .. .. .. .. 1830
+.. .. .. .. .. .. .. .. .. .. 1828
+.. .. .. .. .. .. .. .. .. 1826
+.. .. .. .. .. .. .. .. .. .. 1824
+.. .. .. 1822
+.. .. .. .. .. .. .. .. 1820
+.. .. .. .. .. .. .. .. .. 1818
+.. .. .. .. .. .. .. 1816
+.. .. .. .. .. .. .. .. 1814
+.. .. .. .. .. .. 1812
+.. .. .. .. .. .. .. .. 1810
+.. .. .. .. .. .. .. .. .. 1808
+.. .. .. .. .. .. .. 1806
+.. .. .. .. .. .. .. .. 1804
+.. .. .. .. .. 1802
+.. .. .. .. .. .. .. .. 1800
+.. .. .. .. .. .. .. .. .. 1798
+.. .. .. .. .. .. .. 1796
+.. .. .. .. .. .. .. .. 1794
+.. .. .. .. .. .. 1792
+.. .. .. .. .. .. .. .. 1790
+.. .. .. .. .. .. .. .. .. 1788
+.. .. .. .. .. .. .. 1786
+.. .. .. .. .. .. .. .. .. 1784
+.. .. .. .. .. .. .. .. 1782
+.. .. .. .. .. .. .. .. .. 1780
+.. .. .. .. 1778
+.. .. .. .. .. .. .. .. .. 1776
+.. .. .. .. .. .. .. .. 1774
+.. .. .. .. .. .. .. 1772
+.. .. .. .. .. .. .. .. 1770
+.. .. .. .. .. .. 1768
+.. .. .. .. .. .. .. .. .. 1766
+.. .. .. .. .. .. .. .. 1764
+.. .. .. .. .. .. .. .. .. 1762
+.. .. .. .. .. .. .. 1760
+.. .. .. .. .. .. .. .. .. 1758
+.. .. .. .. .. .. .. .. 1756
+.. .. .. .. .. 1754
+.. .. .. .. .. .. .. .. 1752
+.. .. .. .. .. .. .. 1750
+.. .. .. .. .. .. .. .. .. 1748
+.. .. .. .. .. .. .. .. 1746
+.. .. .. .. .. .. 1744
+.. .. .. .. .. .. .. .. .. 1742
+.. .. .. .. .. .. .. .. 1740
+.. .. .. .. .. .. .. .. .. 1738
+.. .. .. .. .. .. .. 1736
+.. .. .. .. .. .. .. .. .. 1734
+.. .. .. .. .. .. .. .. .. .. 1732
+.. .. .. .. .. .. .. .. 1730
+.. .. .. .. .. .. .. .. .. 1728
+.. .. 1726
+.. .. .. .. .. .. .. .. .. 1724
+.. .. .. .. .. .. .. .. 1722
+.. .. .. .. .. .. .. .. .. 1720
+.. .. .. .. .. .. .. .. .. .. 1718
+.. .. .. .. .. .. .. 1716
+.. .. .. .. .. .. .. .. .. 1714
+.. .. .. .. .. .. .. .. 1712
+.. .. .. .. .. .. 1710
+.. .. .. .. .. .. .. .. .. 1708
+.. .. .. .. .. .. .. .. 1706
+.. .. .. .. .. .. .. 1704
+.. .. .. .. .. .. .. .. .. 1702
+.. .. .. .. .. .. .. .. .. .. 1700
+.. .. .. .. .. .. .. .. 1698
+.. .. .. .. .. .. .. .. .. 1696
+.. .. .. .. .. 1694
+.. .. .. .. .. .. .. .. 1692
+.. .. .. .. .. .. .. .. .. 1690
+.. .. .. .. .. .. .. 1688
+.. .. .. .. .. .. .. .. .. 1686
+.. .. .. .. .. .. .. .. 1684
+.. .. .. .. .. .. .. .. .. 1682
+.. .. .. .. .. .. 1680
+.. .. .. .. .. .. .. .. 1678
+.. .. .. .. .. .. .. 1676
+.. .. .. .. 1674
+.. .. .. .. .. .. .. .. 1672
+.. .. .. .. .. .. .. 1670
+.. .. .. .. .. .. .. .. 1668
+.. .. .. .. .. .. 1666
+.. .. .. .. .. .. .. .. .. 1664
+.. .. .. .. .. .. .. .. 1662
+.. .. .. .. .. .. .. 1660
+.. .. .. .. .. .. .. .. 1658
+.. .. .. .. .. 1656
+.. .. .. .. .. .. .. .. .. 1654
+.. .. .. .. .. .. .. .. 1652
+.. .. .. .. .. .. .. 1650
+.. .. .. .. .. .. .. .. .. 1648
+.. .. .. .. .. .. .. .. 1646
+.. .. .. .. .. .. .. .. .. 1644
+.. .. .. .. .. .. 1642
+.. .. .. .. .. .. .. .. 1640
+.. .. .. .. .. .. .. .. .. 1638
+.. .. .. .. .. .. .. 1636
+.. .. .. .. .. .. .. .. .. 1634
+.. .. .. .. .. .. .. .. 1632
+.. .. .. .. .. .. .. .. .. 1630
+.. .. .. 1628
+.. .. .. .. .. .. .. .. 1626
+.. .. .. .. .. .. .. 1624
+.. .. .. .. .. .. 1622
+.. .. .. .. .. .. .. .. 1620
+.. .. .. .. .. .. .. 1618
+.. .. .. .. .. .. .. .. .. 1616
+.. .. .. .. .. .. .. .. 1614
+.. .. .. .. .. 1612
+.. .. .. .. .. .. .. .. .. 1610
+.. .. .. .. .. .. .. .. 1608
+.. .. .. .. .. .. .. 1606
+.. .. .. .. .. .. .. .. .. 1604
+.. .. .. .. .. .. .. .. 1602
+.. .. .. .. .. .. .. .. .. 1600
+.. .. .. .. .. .. 1598
+.. .. .. .. .. .. .. .. 1596
+.. .. .. .. .. .. .. .. .. 1594
+.. .. .. .. .. .. .. 1592
+.. .. .. .. .. .. .. .. 1590
+.. .. .. .. 1588
+.. .. .. .. .. .. .. .. 1586
+.. .. .. .. .. .. .. 1584
+.. .. .. .. .. .. .. .. .. 1582
+.. .. .. .. .. .. .. .. 1580
+.. .. .. .. .. .. 1578
+.. .. .. .. .. .. .. .. 1576
+.. .. .. .. .. .. .. 1574
+.. .. .. .. .. .. .. .. 1572
+.. .. .. .. .. .. .. .. .. 1570
+.. .. .. .. .. 1568
+.. .. .. .. .. .. .. .. 1566
+.. .. .. .. .. .. .. 1564
+.. .. .. .. .. .. .. .. .. 1562
+.. .. .. .. .. .. .. .. 1560
+.. .. .. .. .. .. .. .. .. 1558
+.. .. .. .. .. .. 1556
+.. .. .. .. .. .. .. .. 1554
+.. .. .. .. .. .. .. 1552
+.. .. .. .. .. .. .. .. 1550
+.. 1548
+.. .. .. .. .. .. .. .. 1546
+.. .. .. .. .. .. .. 1544
+.. .. .. .. .. .. .. .. 1542
+.. .. .. .. .. .. 1540
+.. .. .. .. .. .. .. .. .. 1538
+.. .. .. .. .. .. .. .. 1536
+.. .. .. .. .. .. .. 1534
+.. .. .. .. .. .. .. .. 1532
+.. .. .. .. .. 1530
+.. .. .. .. .. .. .. .. .. 1528
+.. .. .. .. .. .. .. .. 1526
+.. .. .. .. .. .. .. 1524
+.. .. .. .. .. .. .. .. 1522
+.. .. .. .. .. .. .. .. .. 1520
+.. .. .. .. .. .. 1518
+.. .. .. .. .. .. .. .. 1516
+.. .. .. .. .. .. .. 1514
+.. .. .. .. .. .. .. .. .. 1512
+.. .. .. .. .. .. .. .. 1510
+.. .. .. .. 1508
+.. .. .. .. .. .. .. .. 1506
+.. .. .. .. .. .. .. 1504
+.. .. .. .. .. .. .. .. 1502
+.. .. .. .. .. .. 1500
+.. .. .. .. .. .. .. 1498
+.. .. .. .. .. .. .. .. 1496
+.. .. .. .. .. 1494
+.. .. .. .. .. .. .. 1492
+.. .. .. .. .. .. .. .. 1490
+.. .. .. .. .. .. 1488
+.. .. .. .. .. .. .. .. .. 1486
+.. .. .. .. .. .. .. .. 1484
+.. .. .. .. .. .. .. .. .. 1482
+.. .. .. .. .. .. .. 1480
+.. .. .. .. .. .. .. .. .. 1478
+.. .. .. .. .. .. .. .. 1476
+.. .. .. .. .. .. .. .. .. 1474
+.. .. .. 1472
+.. .. .. .. .. .. .. .. .. .. 1470
+.. .. .. .. .. .. .. .. .. 1468
+.. .. .. .. .. .. .. .. .. .. 1466
+.. .. .. .. .. .. .. .. 1464
+.. .. .. .. .. .. .. .. .. 1462
+.. .. .. .. .. .. .. 1460
+.. .. .. .. .. .. .. .. .. .. 1458
+.. .. .. .. .. .. .. .. .. 1456
+.. .. .. .. .. .. .. .. .. .. 1454
+.. .. .. .. .. .. .. .. 1452
+.. .. .. .. .. .. .. .. .. 1450
+.. .. .. .. .. .. .. .. .. .. 1448
+.. .. .. .. .. .. 1446
+.. .. .. .. .. .. .. .. .. 1444
+.. .. .. .. .. .. .. .. 1442
+.. .. .. .. .. .. .. .. .. 1440
+.. .. .. .. .. .. .. 1438
+.. .. .. .. .. .. .. .. 1436
+.. .. .. .. .. 1434
+.. .. .. .. .. .. .. .. .. 1432
+.. .. .. .. .. .. .. .. 1430
+.. .. .. .. .. .. .. .. .. 1428
+.. .. .. .. .. .. .. 1426
+.. .. .. .. .. .. .. .. .. .. 1424
+.. .. .. .. .. .. .. .. .. 1422
+.. .. .. .. .. .. .. .. .. .. 1420
+.. .. .. .. .. .. .. .. 1418
+.. .. .. .. .. .. .. .. .. .. 1416
+.. .. .. .. .. .. .. .. .. 1414
+.. .. .. .. .. .. 1412
+.. .. .. .. .. .. .. .. .. 1410
+.. .. .. .. .. .. .. .. 1408
+.. .. .. .. .. .. .. .. .. 1406
+.. .. .. .. .. .. .. .. .. .. 1404
+.. .. .. .. .. .. .. 1402
+.. .. .. .. .. .. .. .. .. .. 1400
+.. .. .. .. .. .. .. .. .. 1398
+.. .. .. .. .. .. .. .. .. .. 1396
+.. .. .. .. .. .. .. .. 1394
+.. .. .. .. .. .. .. .. .. .. 1392
+.. .. .. .. .. .. .. .. .. 1390
+.. .. .. .. 1388
+.. .. .. .. .. .. .. .. .. .. 1386
+.. .. .. .. .. .. .. .. .. 1384
+.. .. .. .. .. .. .. .. 1382
+.. .. .. .. .. .. .. .. .. .. 1380
+.. .. .. .. .. .. .. .. .. 1378
+.. .. .. .. .. .. .. .. .. .. 1376
+.. .. .. .. .. .. .. 1374
+.. .. .. .. .. .. .. .. 1372
+.. .. .. .. .. .. .. .. .. 1370
+.. .. .. .. .. .. 1368
+.. .. .. .. .. .. .. .. .. .. 1366
+.. .. .. .. .. .. .. .. .. 1364
+.. .. .. .. .. .. .. .. .. .. 1362
+.. .. .. .. .. .. .. .. 1360
+.. .. .. .. .. .. .. .. .. 1358
+.. .. .. .. .. .. .. 1356
+.. .. .. .. .. .. .. .. .. 1354
+.. .. .. .. .. .. .. .. .. .. 1352
+.. .. .. .. .. .. .. .. 1350
+.. .. .. .. .. .. .. .. .. .. 1348
+.. .. .. .. .. .. .. .. .. 1346
+.. .. .. .. .. .. .. .. .. .. 1344
+.. .. .. .. .. 1342
+.. .. .. .. .. .. .. .. .. .. 1340
+.. .. .. .. .. .. .. .. .. 1338
+.. .. .. .. .. .. .. .. 1336
+.. .. .. .. .. .. .. .. .. .. 1334
+.. .. .. .. .. .. .. .. .. 1332
+.. .. .. .. .. .. .. .. .. .. 1330
+.. .. .. .. .. .. .. 1328
+.. .. .. .. .. .. .. .. .. .. 1326
+.. .. .. .. .. .. .. .. .. 1324
+.. .. .. .. .. .. .. .. .. .. 1322
+.. .. .. .. .. .. .. .. 1320
+.. .. .. .. .. .. .. .. .. 1318
+.. .. .. .. .. .. .. .. .. .. 1316
+.. .. .. .. .. .. 1314
+.. .. .. .. .. .. .. .. 1312
+.. .. .. .. .. .. .. .. .. 1310
+.. .. .. .. .. .. .. 1308
+.. .. .. .. .. .. .. .. .. .. 1306
+.. .. .. .. .. .. .. .. .. 1304
+.. .. .. .. .. .. .. .. .. .. 1302
+.. .. .. .. .. .. .. .. 1300
+.. .. .. .. .. .. .. .. .. 1298
+.. .. .. .. .. .. .. .. .. .. 1296
+.. .. 1294
+.. .. .. .. .. .. .. .. .. 1292
+.. .. .. .. .. .. .. .. 1290
+.. .. .. .. .. .. .. 1288
+.. .. .. .. .. .. .. .. .. 1286
+.. .. .. .. .. .. .. .. 1284
+.. .. .. .. .. .. .. .. .. 1282
+.. .. .. .. .. .. 1280
+.. .. .. .. .. .. .. .. 1278
+.. .. .. .. .. .. .. 1276
+.. .. .. .. .. 1274
+.. .. .. .. .. .. .. .. 1272
+.. .. .. .. .. .. .. .. .. 1270
+.. .. .. .. .. .. .. 1268
+.. .. .. .. .. .. .. .. .. 1266
+.. .. .. .. .. .. .. .. 1264
+.. .. .. .. .. .. .. .. .. 1262
+.. .. .. .. .. .. 1260
+.. .. .. .. .. .. .. .. .. 1258
+.. .. .. .. .. .. .. .. 1256
+.. .. .. .. .. .. .. 1254
+.. .. .. .. .. .. .. .. .. .. 1252
+.. .. .. .. .. .. .. .. .. 1250
+.. .. .. .. .. .. .. .. 1248
+.. .. .. .. .. .. .. .. .. 1246
+.. .. .. .. .. .. .. .. .. .. 1244
+.. .. .. .. 1242
+.. .. .. .. .. .. .. .. .. 1240
+.. .. .. .. .. .. .. .. 1238
+.. .. .. .. .. .. .. .. .. 1236
+.. .. .. .. .. .. .. 1234
+.. .. .. .. .. .. .. .. 1232
+.. .. .. .. .. .. 1230
+.. .. .. .. .. .. .. .. .. 1228
+.. .. .. .. .. .. .. .. 1226
+.. .. .. .. .. .. .. 1224
+.. .. .. .. .. .. .. .. .. 1222
+.. .. .. .. .. .. .. .. 1220
+.. .. .. .. .. .. .. .. .. 1218
+.. .. .. .. .. 1216
+.. .. .. .. .. .. .. .. .. 1214
+.. .. .. .. .. .. .. .. 1212
+.. .. .. .. .. .. .. .. .. 1210
+.. .. .. .. .. .. .. 1208
+.. .. .. .. .. .. .. .. 1206
+.. .. .. .. .. .. 1204
+.. .. .. .. .. .. .. .. .. 1202
+.. .. .. .. .. .. .. .. .. .. 1200
+.. .. .. .. .. .. .. .. 1198
+.. .. .. .. .. .. .. .. .. 1196
+.. .. .. .. .. .. .. 1194
+.. .. .. .. .. .. .. .. .. 1192
+.. .. .. .. .. .. .. .. 1190
+.. .. .. .. .. .. .. .. .. 1188
+.. .. .. 1186
+.. .. .. .. .. .. .. .. .. 1184
+.. .. .. .. .. .. .. .. .. .. 1182
+.. .. .. .. .. .. .. .. 1180
+.. .. .. .. .. .. .. .. .. 1178
+.. .. .. .. .. .. .. 1176
+.. .. .. .. .. .. .. .. .. 1174
+.. .. .. .. .. .. .. .. .. .. 1172
+.. .. .. .. .. .. .. .. 1170
+.. .. .. .. .. .. .. .. .. 1168
+.. .. .. .. .. .. 1166
+.. .. .. .. .. .. .. .. .. .. 1164
+.. .. .. .. .. .. .. .. .. 1162
+.. .. .. .. .. .. .. .. 1160
+.. .. .. .. .. .. .. .. .. 1158
+.. .. .. .. .. .. .. .. .. .. 1156
+.. .. .. .. .. .. .. 1152
+.. .. .. .. .. .. .. .. .. 1150
+.. .. .. .. .. .. .. .. .. .. 1148
+.. .. .. .. .. .. .. .. 1146
+.. .. .. .. .. .. .. .. .. 1144
+.. .. .. .. .. 1142
+.. .. .. .. .. .. .. .. .. 1140
+.. .. .. .. .. .. .. .. 1138
+.. .. .. .. .. .. .. .. .. 1136
+.. .. .. .. .. .. .. 1134
+.. .. .. .. .. .. .. .. .. 1132
+.. .. .. .. .. .. .. .. 1130
+.. .. .. .. .. .. .. .. .. 1128
+.. .. .. .. .. .. .. .. .. .. 1126
+.. .. .. .. .. .. 1124
+.. .. .. .. .. .. .. .. .. 1122
+.. .. .. .. .. .. .. .. 1120
+.. .. .. .. .. .. .. .. .. 1118
+.. .. .. .. .. .. .. .. .. .. 1116
+.. .. .. .. .. .. .. 1114
+.. .. .. .. .. .. .. .. 1112
+.. .. .. .. .. .. .. .. .. 1110
+.. .. .. .. 1108
+.. .. .. .. .. .. .. .. .. 1106
+.. .. .. .. .. .. .. .. 1104
+.. .. .. .. .. .. .. .. .. 1102
+.. .. .. .. .. .. .. 1100
+.. .. .. .. .. .. .. .. .. 1098
+.. .. .. .. .. .. .. .. .. .. 1096
+.. .. .. .. .. .. .. .. 1094
+.. .. .. .. .. .. .. .. .. 1092
+.. .. .. .. .. .. 1090
+.. .. .. .. .. .. .. .. 1088
+.. .. .. .. .. .. .. .. .. 1086
+.. .. .. .. .. .. .. 1084
+.. .. .. .. .. .. .. .. 1082
+.. .. .. .. .. .. .. .. .. 1080
+.. .. .. .. .. 1078
+.. .. .. .. .. .. .. .. 1076
+.. .. .. .. .. .. .. 1074
+.. .. .. .. .. .. .. .. 1072
+.. .. .. .. .. .. .. .. .. 1070
+.. .. .. .. .. .. 1068
+.. .. .. .. .. .. .. 1066
+.. .. .. .. .. .. .. .. 1064
+1062
+.. .. .. .. .. .. .. .. .. 1060
+.. .. .. .. .. .. .. .. 1058
+.. .. .. .. .. .. .. .. .. 1056
+.. .. .. .. .. .. .. 1054
+.. .. .. .. .. .. .. .. .. 1052
+.. .. .. .. .. .. .. .. 1050
+.. .. .. .. .. .. .. .. .. .. 1048
+.. .. .. .. .. .. .. .. .. 1046
+.. .. .. .. .. .. 1044
+.. .. .. .. .. .. .. .. .. .. 1042
+.. .. .. .. .. .. .. .. .. .. .. 1040
+.. .. .. .. .. .. .. .. .. 1038
+.. .. .. .. .. .. .. .. .. .. .. 1036
+.. .. .. .. .. .. .. .. .. .. 1034
+.. .. .. .. .. .. .. .. .. .. .. 1032
+.. .. .. .. .. .. .. .. 1030
+.. .. .. .. .. .. .. .. .. .. 1028
+.. .. .. .. .. .. .. .. .. 1026
+.. .. .. .. .. .. .. .. .. .. 1024
+.. .. .. .. .. .. .. 1022
+.. .. .. .. .. .. .. .. .. .. 1020
+.. .. .. .. .. .. .. .. .. 1018
+.. .. .. .. .. .. .. .. .. .. 1016
+.. .. .. .. .. .. .. .. 1014
+.. .. .. .. .. .. .. .. .. .. 1012
+.. .. .. .. .. .. .. .. .. 1010
+.. .. .. .. .. .. .. .. .. .. 1008
+.. .. .. .. .. 1006
+.. .. .. .. .. .. .. .. .. 1004
+.. .. .. .. .. .. .. .. 1002
+.. .. .. .. .. .. .. .. .. 1000
+.. .. .. .. .. .. .. 998
+.. .. .. .. .. .. .. .. .. .. 996
+.. .. .. .. .. .. .. .. .. 994
+.. .. .. .. .. .. .. .. .. .. 992
+.. .. .. .. .. .. .. .. 990
+.. .. .. .. .. .. .. .. .. 988
+.. .. .. .. .. .. 986
+.. .. .. .. .. .. .. .. .. .. 984
+.. .. .. .. .. .. .. .. .. 982
+.. .. .. .. .. .. .. .. .. .. 980
+.. .. .. .. .. .. .. .. 978
+.. .. .. .. .. .. .. .. .. 976
+.. .. .. .. .. .. .. .. .. .. 974
+.. .. .. .. .. .. .. 972
+.. .. .. .. .. .. .. .. .. 970
+.. .. .. .. .. .. .. .. 968
+.. .. .. .. .. .. .. .. .. 966
+.. .. .. .. 964
+.. .. .. .. .. .. .. .. .. 962
+.. .. .. .. .. .. .. .. .. .. 960
+.. .. .. .. .. .. .. .. 958
+.. .. .. .. .. .. .. .. .. 956
+.. .. .. .. .. .. .. 954
+.. .. .. .. .. .. .. .. 952
+.. .. .. .. .. .. .. .. .. 950
+.. .. .. .. .. .. 948
+.. .. .. .. .. .. .. .. .. 946
+.. .. .. .. .. .. .. .. .. .. 944
+.. .. .. .. .. .. .. .. 942
+.. .. .. .. .. .. .. .. .. 940
+.. .. .. .. .. .. .. 938
+.. .. .. .. .. .. .. .. .. .. 936
+.. .. .. .. .. .. .. .. .. 934
+.. .. .. .. .. .. .. .. 932
+.. .. .. .. .. .. .. .. .. .. 930
+.. .. .. .. .. .. .. .. .. 928
+.. .. .. .. .. .. .. .. .. .. 926
+.. .. .. .. .. 924
+.. .. .. .. .. .. .. .. .. 922
+.. .. .. .. .. .. .. .. 920
+.. .. .. .. .. .. .. .. .. .. 918
+.. .. .. .. .. .. .. .. .. 916
+.. .. .. .. .. .. .. 914
+.. .. .. .. .. .. .. .. .. 912
+.. .. .. .. .. .. .. .. 910
+.. .. .. .. .. .. 908
+.. .. .. .. .. .. .. .. 906
+.. .. .. .. .. .. .. 904
+.. .. .. .. .. .. .. .. .. 900
+.. .. .. .. .. .. .. .. 898
+.. .. .. 896
+.. .. .. .. .. .. .. .. .. 894
+.. .. .. .. .. .. .. .. 892
+.. .. .. .. .. .. .. .. .. 890
+.. .. .. .. .. .. .. .. .. .. 888
+.. .. .. .. .. .. .. 886
+.. .. .. .. .. .. .. .. .. .. 884
+.. .. .. .. .. .. .. .. .. 882
+.. .. .. .. .. .. .. .. .. .. .. 880
+.. .. .. .. .. .. .. .. .. .. 878
+.. .. .. .. .. .. .. .. 876
+.. .. .. .. .. .. .. .. .. .. 874
+.. .. .. .. .. .. .. .. .. 872
+.. .. .. .. .. .. .. .. .. .. 870
+.. .. .. .. .. .. 868
+.. .. .. .. .. .. .. .. .. .. 866
+.. .. .. .. .. .. .. .. .. 864
+.. .. .. .. .. .. .. .. 862
+.. .. .. .. .. .. .. .. .. 860
+.. .. .. .. .. .. .. .. .. .. 858
+.. .. .. .. .. .. .. 856
+.. .. .. .. .. .. .. .. .. 854
+.. .. .. .. .. .. .. .. 852
+.. .. .. .. .. .. .. .. .. 850
+.. .. .. .. .. .. .. .. .. .. 848
+.. .. .. .. .. 846
+.. .. .. .. .. .. .. .. .. .. 844
+.. .. .. .. .. .. .. .. .. 842
+.. .. .. .. .. .. .. .. 840
+.. .. .. .. .. .. .. .. .. 838
+.. .. .. .. .. .. .. 836
+.. .. .. .. .. .. .. .. .. 834
+.. .. .. .. .. .. .. .. .. .. 832
+.. .. .. .. .. .. .. .. 830
+.. .. .. .. .. .. .. .. .. 828
+.. .. .. .. .. .. 826
+.. .. .. .. .. .. .. .. .. 824
+.. .. .. .. .. .. .. .. 822
+.. .. .. .. .. .. .. 820
+.. .. .. .. .. .. .. .. .. .. 818
+.. .. .. .. .. .. .. .. .. 816
+.. .. .. .. .. .. .. .. 814
+.. .. .. .. .. .. .. .. .. .. 812
+.. .. .. .. .. .. .. .. .. 810
+.. .. .. .. 808
+.. .. .. .. .. .. .. .. .. 806
+.. .. .. .. .. .. .. .. 804
+.. .. .. .. .. .. .. 802
+.. .. .. .. .. .. .. .. .. 800
+.. .. .. .. .. .. .. .. 798
+.. .. .. .. .. .. .. .. .. 796
+.. .. .. .. .. .. 794
+.. .. .. .. .. .. .. .. .. 792
+.. .. .. .. .. .. .. .. 790
+.. .. .. .. .. .. .. .. .. 788
+.. .. .. .. .. .. .. 786
+.. .. .. .. .. .. .. .. 784
+.. .. .. .. .. .. .. .. .. 782
+.. .. .. .. .. 780
+.. .. .. .. .. .. .. .. .. .. 778
+.. .. .. .. .. .. .. .. .. 776
+.. .. .. .. .. .. .. .. .. .. 774
+.. .. .. .. .. .. .. .. 772
+.. .. .. .. .. .. .. .. .. 770
+.. .. .. .. .. .. .. 768
+.. .. .. .. .. .. .. .. .. .. 766
+.. .. .. .. .. .. .. .. .. 764
+.. .. .. .. .. .. .. .. 762
+.. .. .. .. .. .. .. .. .. .. 760
+.. .. .. .. .. .. .. .. .. 758
+.. .. .. .. .. .. .. .. .. .. 756
+.. .. .. .. .. .. 754
+.. .. .. .. .. .. .. .. .. .. 752
+.. .. .. .. .. .. .. .. .. 750
+.. .. .. .. .. .. .. .. .. .. 748
+.. .. .. .. .. .. .. .. 746
+.. .. .. .. .. .. .. .. .. .. 744
+.. .. .. .. .. .. .. .. .. 742
+.. .. .. .. .. .. .. .. .. .. 740
+.. .. .. .. .. .. .. 738
+.. .. .. .. .. .. .. .. .. 736
+.. .. .. .. .. .. .. .. 734
+.. .. .. .. .. .. .. .. .. 732
+.. .. .. .. .. .. .. .. .. .. 730
+.. .. 728
+.. .. .. .. .. .. .. .. 726
+.. .. .. .. .. .. .. .. .. 724
+.. .. .. .. .. .. .. 722
+.. .. .. .. .. .. .. .. .. 720
+.. .. .. .. .. .. .. .. .. .. 718
+.. .. .. .. .. .. .. .. 716
+.. .. .. .. .. .. .. .. .. 714
+.. .. .. .. .. .. 712
+.. .. .. .. .. .. .. .. .. 710
+.. .. .. .. .. .. .. .. 708
+.. .. .. .. .. .. .. 706
+.. .. .. .. .. .. .. .. .. 704
+.. .. .. .. .. .. .. .. 702
+.. .. .. .. .. .. .. .. .. 700
+.. .. .. .. .. 698
+.. .. .. .. .. .. .. .. 696
+.. .. .. .. .. .. .. 694
+.. .. .. .. .. .. .. .. 692
+.. .. .. .. .. .. .. .. .. 690
+.. .. .. .. .. .. 688
+.. .. .. .. .. .. .. 686
+.. .. .. .. .. .. .. .. 684
+.. .. .. .. 682
+.. .. .. .. .. .. .. .. 680
+.. .. .. .. .. .. .. 678
+.. .. .. .. .. .. 676
+.. .. .. .. .. .. .. .. 674
+.. .. .. .. .. .. .. 672
+.. .. .. .. .. .. .. .. 670
+.. .. .. .. .. 668
+.. .. .. .. .. .. .. .. .. 666
+.. .. .. .. .. .. .. .. 664
+.. .. .. .. .. .. .. .. .. 662
+.. .. .. .. .. .. .. 660
+.. .. .. .. .. .. .. .. 658
+.. .. .. .. .. .. 656
+.. .. .. .. .. .. .. .. .. 654
+.. .. .. .. .. .. .. .. 652
+.. .. .. .. .. .. .. .. .. 650
+.. .. .. .. .. .. .. 648
+.. .. .. .. .. .. .. .. 646
+.. .. .. .. .. .. .. .. .. 644
+.. .. .. 642
+.. .. .. .. .. .. .. .. .. 640
+.. .. .. .. .. .. .. .. 638
+.. .. .. .. .. .. .. 636
+.. .. .. .. .. .. .. .. .. 634
+.. .. .. .. .. .. .. .. 632
+.. .. .. .. .. .. .. .. .. 630
+.. .. .. .. .. .. 628
+.. .. .. .. .. .. .. .. .. 626
+.. .. .. .. .. .. .. .. 624
+.. .. .. .. .. .. .. .. .. 622
+.. .. .. .. .. .. .. 620
+.. .. .. .. .. .. .. .. .. 618
+.. .. .. .. .. .. .. .. 616
+.. .. .. .. .. 614
+.. .. .. .. .. .. .. .. .. 612
+.. .. .. .. .. .. .. .. 610
+.. .. .. .. .. .. .. .. .. .. 608
+.. .. .. .. .. .. .. .. .. 606
+.. .. .. .. .. .. .. .. .. .. 604
+.. .. .. .. .. .. .. 602
+.. .. .. .. .. .. .. .. .. 600
+.. .. .. .. .. .. .. .. 598
+.. .. .. .. .. .. 596
+.. .. .. .. .. .. .. .. .. 594
+.. .. .. .. .. .. .. .. 592
+.. .. .. .. .. .. .. .. .. 590
+.. .. .. .. .. .. .. 588
+.. .. .. .. .. .. .. .. .. .. 586
+.. .. .. .. .. .. .. .. .. 584
+.. .. .. .. .. .. .. .. 582
+.. .. .. .. .. .. .. .. .. 580
+.. .. .. .. 578
+.. .. .. .. .. .. .. .. .. 576
+.. .. .. .. .. .. .. .. 574
+.. .. .. .. .. .. .. .. .. 572
+.. .. .. .. .. .. .. 570
+.. .. .. .. .. .. .. .. .. .. 568
+.. .. .. .. .. .. .. .. .. 566
+.. .. .. .. .. .. .. .. .. .. 564
+.. .. .. .. .. .. .. .. 562
+.. .. .. .. .. .. .. .. .. 560
+.. .. .. .. .. .. .. .. .. .. 558
+.. .. .. .. .. .. 556
+.. .. .. .. .. .. .. .. .. 554
+.. .. .. .. .. .. .. .. 552
+.. .. .. .. .. .. .. 550
+.. .. .. .. .. .. .. .. .. 548
+.. .. .. .. .. .. .. .. 546
+.. .. .. .. .. 544
+.. .. .. .. .. .. .. .. 542
+.. .. .. .. .. .. .. .. .. 540
+.. .. .. .. .. .. .. 538
+.. .. .. .. .. .. .. .. .. 536
+.. .. .. .. .. .. .. .. 534
+.. .. .. .. .. .. .. .. .. 532
+.. .. .. .. .. .. 530
+.. .. .. .. .. .. .. .. 528
+.. .. .. .. .. .. .. 526
+.. .. .. .. .. .. .. .. 524
+.. 522
+.. .. .. .. .. .. .. .. .. .. 520
+.. .. .. .. .. .. .. .. .. 518
+.. .. .. .. .. .. .. .. 516
+.. .. .. .. .. .. .. .. .. 514
+.. .. .. .. .. .. .. .. .. .. 512
+.. .. .. .. .. .. .. 510
+.. .. .. .. .. .. .. .. .. 508
+.. .. .. .. .. .. .. .. 506
+.. .. .. .. .. .. .. .. .. 504
+.. .. .. .. .. .. 502
+.. .. .. .. .. .. .. .. .. .. 500
+.. .. .. .. .. .. .. .. .. 498
+.. .. .. .. .. .. .. .. 496
+.. .. .. .. .. .. .. .. .. 494
+.. .. .. .. .. .. .. 492
+.. .. .. .. .. .. .. .. .. .. 490
+.. .. .. .. .. .. .. .. .. 488
+.. .. .. .. .. .. .. .. 486
+.. .. .. .. .. .. .. .. .. 484
+.. .. .. .. .. 482
+.. .. .. .. .. .. .. .. .. 480
+.. .. .. .. .. .. .. .. 478
+.. .. .. .. .. .. .. .. .. 476
+.. .. .. .. .. .. .. 474
+.. .. .. .. .. .. .. .. 472
+.. .. .. .. .. .. 470
+.. .. .. .. .. .. .. .. 468
+.. .. .. .. .. .. .. 466
+.. .. .. .. .. .. .. .. 464
+.. .. .. .. 462
+.. .. .. .. .. .. .. .. .. .. 460
+.. .. .. .. .. .. .. .. .. 458
+.. .. .. .. .. .. .. .. .. .. 456
+.. .. .. .. .. .. .. .. 454
+.. .. .. .. .. .. .. .. .. .. 452
+.. .. .. .. .. .. .. .. .. 450
+.. .. .. .. .. .. .. .. .. .. 448
+.. .. .. .. .. .. .. 446
+.. .. .. .. .. .. .. .. 444
+.. .. .. .. .. .. .. .. .. 442
+.. .. .. .. .. .. 440
+.. .. .. .. .. .. .. .. .. .. 438
+.. .. .. .. .. .. .. .. .. 436
+.. .. .. .. .. .. .. .. .. .. 434
+.. .. .. .. .. .. .. .. 432
+.. .. .. .. .. .. .. .. .. 430
+.. .. .. .. .. .. .. 428
+.. .. .. .. .. .. .. .. 426
+.. .. .. .. .. .. .. .. .. 424
+.. .. .. .. .. 422
+.. .. .. .. .. .. .. .. .. 420
+.. .. .. .. .. .. .. .. .. .. 418
+.. .. .. .. .. .. .. .. 416
+.. .. .. .. .. .. .. .. .. .. 414
+.. .. .. .. .. .. .. .. .. 412
+.. .. .. .. .. .. .. 410
+.. .. .. .. .. .. .. .. .. 408
+.. .. .. .. .. .. .. .. .. .. 406
+.. .. .. .. .. .. .. .. 404
+.. .. .. .. .. .. .. .. .. 402
+.. .. .. .. .. .. .. .. .. .. 400
+.. .. .. .. .. .. 398
+.. .. .. .. .. .. .. .. .. 396
+.. .. .. .. .. .. .. .. 394
+.. .. .. .. .. .. .. .. .. 392
+.. .. .. .. .. .. .. .. .. .. 390
+.. .. .. .. .. .. .. 388
+.. .. .. .. .. .. .. .. .. .. 386
+.. .. .. .. .. .. .. .. .. 384
+.. .. .. .. .. .. .. .. 382
+.. .. .. .. .. .. .. .. .. .. 380
+.. .. .. .. .. .. .. .. .. 378
+.. .. .. .. .. .. .. .. .. .. 376
+.. .. .. 374
+.. .. .. .. .. .. .. .. 372
+.. .. .. .. .. .. .. 370
+.. .. .. .. .. .. 368
+.. .. .. .. .. .. .. .. 366
+.. .. .. .. .. .. .. .. .. 364
+.. .. .. .. .. .. .. 362
+.. .. .. .. .. .. .. .. 360
+.. .. .. .. .. 358
+.. .. .. .. .. .. .. .. 356
+.. .. .. .. .. .. .. .. .. 354
+.. .. .. .. .. .. .. 352
+.. .. .. .. .. .. .. .. .. 350
+.. .. .. .. .. .. .. .. 348
+.. .. .. .. .. .. .. .. .. 346
+.. .. .. .. .. .. 344
+.. .. .. .. .. .. .. .. .. 342
+.. .. .. .. .. .. .. .. 340
+.. .. .. .. .. .. .. .. .. 338
+.. .. .. .. .. .. .. 336
+.. .. .. .. .. .. .. .. .. 334
+.. .. .. .. .. .. .. .. 332
+.. .. .. .. .. .. .. .. .. 330
+.. .. .. .. 328
+.. .. .. .. .. .. .. .. .. 326
+.. .. .. .. .. .. .. .. 324
+.. .. .. .. .. .. .. 322
+.. .. .. .. .. .. .. .. 320
+.. .. .. .. .. .. 318
+.. .. .. .. .. .. .. .. .. 316
+.. .. .. .. .. .. .. .. 314
+.. .. .. .. .. .. .. .. .. .. 312
+.. .. .. .. .. .. .. .. .. 310
+.. .. .. .. .. .. .. .. .. .. 308
+.. .. .. .. .. .. .. 306
+.. .. .. .. .. .. .. .. .. .. 304
+.. .. .. .. .. .. .. .. .. 302
+.. .. .. .. .. .. .. .. 300
+.. .. .. .. .. .. .. .. .. 298
+.. .. .. .. .. 296
+.. .. .. .. .. .. .. .. .. 294
+.. .. .. .. .. .. .. .. 292
+.. .. .. .. .. .. .. .. .. 290
+.. .. .. .. .. .. .. 288
+.. .. .. .. .. .. .. .. 286
+.. .. .. .. .. .. 284
+.. .. .. .. .. .. .. .. .. 282
+.. .. .. .. .. .. .. .. 280
+.. .. .. .. .. .. .. .. .. 278
+.. .. .. .. .. .. .. 276
+.. .. .. .. .. .. .. .. .. .. 274
+.. .. .. .. .. .. .. .. .. 272
+.. .. .. .. .. .. .. .. 270
+.. .. .. .. .. .. .. .. .. 268
+.. .. 266
+.. .. .. .. .. .. .. .. .. 264
+.. .. .. .. .. .. .. .. 262
+.. .. .. .. .. .. .. .. .. 260
+.. .. .. .. .. .. .. 258
+.. .. .. .. .. .. .. .. .. 256
+.. .. .. .. .. .. .. .. 254
+.. .. .. .. .. .. .. .. .. 252
+.. .. .. .. .. .. 250
+.. .. .. .. .. .. .. .. .. 248
+.. .. .. .. .. .. .. .. 246
+.. .. .. .. .. .. .. .. .. 244
+.. .. .. .. .. .. .. 242
+.. .. .. .. .. .. .. .. 240
+.. .. .. .. .. 238
+.. .. .. .. .. .. .. .. .. 236
+.. .. .. .. .. .. .. .. 234
+.. .. .. .. .. .. .. .. .. 232
+.. .. .. .. .. .. .. 230
+.. .. .. .. .. .. .. .. 228
+.. .. .. .. .. .. 226
+.. .. .. .. .. .. .. .. .. .. 224
+.. .. .. .. .. .. .. .. .. 222
+.. .. .. .. .. .. .. .. 220
+.. .. .. .. .. .. .. .. .. .. 218
+.. .. .. .. .. .. .. .. .. 216
+.. .. .. .. .. .. .. 214
+.. .. .. .. .. .. .. .. .. 212
+.. .. .. .. .. .. .. .. 210
+.. .. .. .. 208
+.. .. .. .. .. .. .. .. .. .. 206
+.. .. .. .. .. .. .. .. .. 204
+.. .. .. .. .. .. .. .. .. .. 202
+.. .. .. .. .. .. .. .. 200
+.. .. .. .. .. .. .. .. .. .. 198
+.. .. .. .. .. .. .. .. .. 196
+.. .. .. .. .. .. .. 194
+.. .. .. .. .. .. .. .. .. 192
+.. .. .. .. .. .. .. .. .. .. 190
+.. .. .. .. .. .. .. .. 188
+.. .. .. .. .. .. .. .. .. 186
+.. .. .. .. .. .. 184
+.. .. .. .. .. .. .. .. .. 182
+.. .. .. .. .. .. .. .. 180
+.. .. .. .. .. .. .. .. .. 178
+.. .. .. .. .. .. .. 176
+.. .. .. .. .. .. .. .. .. .. 174
+.. .. .. .. .. .. .. .. .. 172
+.. .. .. .. .. .. .. .. 170
+.. .. .. .. .. .. .. .. .. .. 168
+.. .. .. .. .. .. .. .. .. 166
+.. .. .. .. .. .. .. .. .. .. 164
+.. .. .. .. .. 162
+.. .. .. .. .. .. .. .. .. 160
+.. .. .. .. .. .. .. .. 158
+.. .. .. .. .. .. .. .. .. 156
+.. .. .. .. .. .. .. 154
+.. .. .. .. .. .. .. .. 152
+.. .. .. .. .. .. .. .. .. 150
+.. .. .. .. .. .. 148
+.. .. .. .. .. .. .. .. 146
+.. .. .. .. .. .. .. .. .. 144
+.. .. .. .. .. .. .. 142
+.. .. .. .. .. .. .. .. .. 140
+.. .. .. .. .. .. .. .. 138
+.. .. .. .. .. .. .. .. .. .. 136
+.. .. .. .. .. .. .. .. .. 134
+.. .. .. 132
+.. .. .. .. .. .. .. .. 130
+.. .. .. .. .. .. .. 128
+.. .. .. .. .. .. .. .. .. 126
+.. .. .. .. .. .. .. .. 124
+.. .. .. .. .. .. 122
+.. .. .. .. .. .. .. .. .. 120
+.. .. .. .. .. .. .. .. 118
+.. .. .. .. .. .. .. 116
+.. .. .. .. .. .. .. .. .. 114
+.. .. .. .. .. .. .. .. 112
+.. .. .. .. .. .. .. .. .. 110
+.. .. .. .. .. 108
+.. .. .. .. .. .. .. .. .. 106
+.. .. .. .. .. .. .. .. 104
+.. .. .. .. .. .. .. .. .. 102
+.. .. .. .. .. .. .. 100
+.. .. .. .. .. .. .. .. .. 98
+.. .. .. .. .. .. .. .. 96
+.. .. .. .. .. .. .. .. .. 94
+.. .. .. .. .. .. .. .. .. .. 92
+.. .. .. .. .. .. 90
+.. .. .. .. .. .. .. .. .. 88
+.. .. .. .. .. .. .. .. 86
+.. .. .. .. .. .. .. .. .. 84
+.. .. .. .. .. .. .. 82
+.. .. .. .. .. .. .. .. .. 80
+.. .. .. .. .. .. .. .. 78
+.. .. .. .. 76
+.. .. .. .. .. .. .. .. .. 74
+.. .. .. .. .. .. .. .. 72
+.. .. .. .. .. .. .. .. .. 70
+.. .. .. .. .. .. .. 68
+.. .. .. .. .. .. .. .. .. .. 66
+.. .. .. .. .. .. .. .. .. 64
+.. .. .. .. .. .. .. .. .. .. 62
+.. .. .. .. .. .. .. .. 60
+.. .. .. .. .. .. .. .. .. 58
+.. .. .. .. .. .. 56
+.. .. .. .. .. .. .. .. .. 54
+.. .. .. .. .. .. .. .. 52
+.. .. .. .. .. .. .. .. .. 50
+.. .. .. .. .. .. .. 48
+.. .. .. .. .. .. .. .. .. 46
+.. .. .. .. .. .. .. .. 44
+.. .. .. .. .. .. .. .. .. 42
+.. .. .. .. .. 40
+.. .. .. .. .. .. .. .. .. .. 38
+.. .. .. .. .. .. .. .. .. 36
+.. .. .. .. .. .. .. .. 34
+.. .. .. .. .. .. .. .. .. 32
+.. .. .. .. .. .. .. 30
+.. .. .. .. .. .. .. .. .. 28
+.. .. .. .. .. .. .. .. 26
+.. .. .. .. .. .. .. .. .. 24
+.. .. .. .. .. .. .. .. .. .. 22
+.. .. .. .. .. .. 20
+.. .. .. .. .. .. .. .. .. .. 18
+.. .. .. .. .. .. .. .. .. 16
+.. .. .. .. .. .. .. .. .. .. 14
+.. .. .. .. .. .. .. .. 12
+.. .. .. .. .. .. .. .. .. 10
+.. .. .. .. .. .. .. .. .. .. 8
+.. .. .. .. .. .. .. 6
+.. .. .. .. .. .. .. .. .. 4
+.. .. .. .. .. .. .. .. 2
+.. .. .. .. .. .. .. .. .. 0
+-- end single oset, pool allocator ----------------
+-- start oset, shared pool ----------------
+.. .. .. .. .. .. .. .. .. 1998
+.. .. .. .. .. .. .. .. 1996
+.. .. .. .. .. .. .. .. .. .. 1994
+.. .. .. .. .. .. .. .. .. 1992
+.. .. .. .. .. .. .. .. .. .. 1990
+.. .. .. .. .. .. .. 1988
+.. .. .. .. .. .. .. .. .. 1986
+.. .. .. .. .. .. .. .. .. .. 1984
+.. .. .. .. .. .. .. .. 1982
+.. .. .. .. .. .. .. .. .. .. 1980
+.. .. .. .. .. .. .. .. .. 1978
+.. .. .. .. .. .. .. .. .. .. 1976
+.. .. .. .. .. .. 1974
+.. .. .. .. .. .. .. .. .. .. 1972
+.. .. .. .. .. .. .. .. .. 1970
+.. .. .. .. .. .. .. .. .. .. 1968
+.. .. .. .. .. .. .. .. 1966
+.. .. .. .. .. .. .. .. .. .. 1964
+.. .. .. .. .. .. .. .. .. 1962
+.. .. .. .. .. .. .. 1960
+.. .. .. .. .. .. .. .. .. .. 1958
+.. .. .. .. .. .. .. .. .. 1956
+.. .. .. .. .. .. .. .. 1954
+.. .. .. .. .. .. .. .. .. .. 1952
+.. .. .. .. .. .. .. .. .. 1950
+.. .. .. .. .. .. .. .. .. .. 1948
+.. .. .. .. .. 1946
+.. .. .. .. .. .. .. .. .. 1944
+.. .. .. .. .. .. .. .. 1942
+.. .. .. .. .. .. .. 1940
+.. .. .. .. .. .. .. .. .. .. 1938
+.. .. .. .. .. .. .. .. .. 1936
+.. .. .. .. .. .. .. .. 1934
+.. .. .. .. .. .. .. .. .. 1932
+.. .. .. .. .. .. 1930
+.. .. .. .. .. .. .. .. .. 1928
+.. .. .. .. .. .. .. .. .. .. 1926
+.. .. .. .. .. .. .. .. 1924
+.. .. .. .. .. .. .. .. .. .. 1922
+.. .. .. .. .. .. .. .. .. 1920
+.. .. .. .. .. .. .. .. .. .. 1918
+.. .. .. .. .. .. .. 1916
+.. .. .. .. .. .. .. .. .. 1914
+.. .. .. .. .. .. .. .. 1912
+.. .. .. .. .. .. .. .. .. .. 1910
+.. .. .. .. .. .. .. .. .. 1908
+.. .. .. .. .. .. .. .. .. .. 1906
+.. .. .. .. 1904
+.. .. .. .. .. .. .. .. .. 1902
+.. .. .. .. .. .. .. .. 1900
+.. .. .. .. .. .. .. 1898
+.. .. .. .. .. .. .. .. .. 1896
+.. .. .. .. .. .. .. .. 1894
+.. .. .. .. .. .. .. .. .. 1892
+.. .. .. .. .. .. 1890
+.. .. .. .. .. .. .. .. .. .. 1888
+.. .. .. .. .. .. .. .. .. 1886
+.. .. .. .. .. .. .. .. .. .. 1884
+.. .. .. .. .. .. .. .. 1882
+.. .. .. .. .. .. .. .. .. 1880
+.. .. .. .. .. .. .. 1878
+.. .. .. .. .. .. .. .. 1876
+.. .. .. .. .. .. .. .. .. 1874
+.. .. .. .. .. 1872
+.. .. .. .. .. .. .. .. .. .. 1870
+.. .. .. .. .. .. .. .. .. 1868
+.. .. .. .. .. .. .. .. .. .. 1866
+.. .. .. .. .. .. .. .. 1864
+.. .. .. .. .. .. .. .. .. 1862
+.. .. .. .. .. .. .. .. .. .. 1860
+.. .. .. .. .. .. .. 1858
+.. .. .. .. .. .. .. .. .. 1856
+.. .. .. .. .. .. .. .. 1854
+.. .. .. .. .. .. .. .. .. 1852
+.. .. .. .. .. .. 1848
+.. .. .. .. .. .. .. .. .. 1846
+.. .. .. .. .. .. .. .. 1844
+.. .. .. .. .. .. .. .. .. .. 1842
+.. .. .. .. .. .. .. .. .. 1840
+.. .. .. .. .. .. .. 1838
+.. .. .. .. .. .. .. .. .. .. 1836
+.. .. .. .. .. .. .. .. .. 1834
+.. .. .. .. .. .. .. .. .. .. 1832
+.. .. .. .. .. .. .. .. 1830
+.. .. .. .. .. .. .. .. .. .. 1828
+.. .. .. .. .. .. .. .. .. 1826
+.. .. .. .. .. .. .. .. .. .. 1824
+.. .. .. 1822
+.. .. .. .. .. .. .. .. 1820
+.. .. .. .. .. .. .. .. .. 1818
+.. .. .. .. .. .. .. 1816
+.. .. .. .. .. .. .. .. 1814
+.. .. .. .. .. .. 1812
+.. .. .. .. .. .. .. .. 1810
+.. .. .. .. .. .. .. .. .. 1808
+.. .. .. .. .. .. .. 1806
+.. .. .. .. .. .. .. .. 1804
+.. .. .. .. .. 1802
+.. .. .. .. .. .. .. .. 1800
+.. .. .. .. .. .. .. .. .. 1798
+.. .. .. .. .. .. .. 1796
+.. .. .. .. .. .. .. .. 1794
+.. .. .. .. .. .. 1792
+.. .. .. .. .. .. .. .. 1790
+.. .. .. .. .. .. .. .. .. 1788
+.. .. .. .. .. .. .. 1786
+.. .. .. .. .. .. .. .. .. 1784
+.. .. .. .. .. .. .. .. 1782
+.. .. .. .. .. .. .. .. .. 1780
+.. .. .. .. 1778
+.. .. .. .. .. .. .. .. .. 1776
+.. .. .. .. .. .. .. .. 1774
+.. .. .. .. .. .. .. 1772
+.. .. .. .. .. .. .. .. 1770
+.. .. .. .. .. .. 1768
+.. .. .. .. .. .. .. .. .. 1766
+.. .. .. .. .. .. .. .. 1764
+.. .. .. .. .. .. .. .. .. 1762
+.. .. .. .. .. .. .. 1760
+.. .. .. .. .. .. .. .. .. 1758
+.. .. .. .. .. .. .. .. 1756
+.. .. .. .. .. 1754
+.. .. .. .. .. .. .. .. 1752
+.. .. .. .. .. .. .. 1750
+.. .. .. .. .. .. .. .. .. 1748
+.. .. .. .. .. .. .. .. 1746
+.. .. .. .. .. .. 1744
+.. .. .. .. .. .. .. .. .. 1742
+.. .. .. .. .. .. .. .. 1740
+.. .. .. .. .. .. .. .. .. 1738
+.. .. .. .. .. .. .. 1736
+.. .. .. .. .. .. .. .. .. 1734
+.. .. .. .. .. .. .. .. .. .. 1732
+.. .. .. .. .. .. .. .. 1730
+.. .. .. .. .. .. .. .. .. 1728
+.. .. 1726
+.. .. .. .. .. .. .. .. .. 1724
+.. .. .. .. .. .. .. .. 1722
+.. .. .. .. .. .. .. .. .. 1720
+.. .. .. .. .. .. .. .. .. .. 1718
+.. .. .. .. .. .. .. 1716
+.. .. .. .. .. .. .. .. .. 1714
+.. .. .. .. .. .. .. .. 1712
+.. .. .. .. .. .. 1710
+.. .. .. .. .. .. .. .. .. 1708
+.. .. .. .. .. .. .. .. 1706
+.. .. .. .. .. .. .. 1704
+.. .. .. .. .. .. .. .. .. 1702
+.. .. .. .. .. .. .. .. .. .. 1700
+.. .. .. .. .. .. .. .. 1698
+.. .. .. .. .. .. .. .. .. 1696
+.. .. .. .. .. 1694
+.. .. .. .. .. .. .. .. 1692
+.. .. .. .. .. .. .. .. .. 1690
+.. .. .. .. .. .. .. 1688
+.. .. .. .. .. .. .. .. .. 1686
+.. .. .. .. .. .. .. .. 1684
+.. .. .. .. .. .. .. .. .. 1682
+.. .. .. .. .. .. 1680
+.. .. .. .. .. .. .. .. 1678
+.. .. .. .. .. .. .. 1676
+.. .. .. .. 1674
+.. .. .. .. .. .. .. .. 1672
+.. .. .. .. .. .. .. 1670
+.. .. .. .. .. .. .. .. 1668
+.. .. .. .. .. .. 1666
+.. .. .. .. .. .. .. .. .. 1664
+.. .. .. .. .. .. .. .. 1662
+.. .. .. .. .. .. .. 1660
+.. .. .. .. .. .. .. .. 1658
+.. .. .. .. .. 1656
+.. .. .. .. .. .. .. .. .. 1654
+.. .. .. .. .. .. .. .. 1652
+.. .. .. .. .. .. .. 1650
+.. .. .. .. .. .. .. .. .. 1648
+.. .. .. .. .. .. .. .. 1646
+.. .. .. .. .. .. .. .. .. 1644
+.. .. .. .. .. .. 1642
+.. .. .. .. .. .. .. .. 1640
+.. .. .. .. .. .. .. .. .. 1638
+.. .. .. .. .. .. .. 1636
+.. .. .. .. .. .. .. .. .. 1634
+.. .. .. .. .. .. .. .. 1632
+.. .. .. .. .. .. .. .. .. 1630
+.. .. .. 1628
+.. .. .. .. .. .. .. .. 1626
+.. .. .. .. .. .. .. 1624
+.. .. .. .. .. .. 1622
+.. .. .. .. .. .. .. .. 1620
+.. .. .. .. .. .. .. 1618
+.. .. .. .. .. .. .. .. .. 1616
+.. .. .. .. .. .. .. .. 1614
+.. .. .. .. .. 1612
+.. .. .. .. .. .. .. .. .. 1610
+.. .. .. .. .. .. .. .. 1608
+.. .. .. .. .. .. .. 1606
+.. .. .. .. .. .. .. .. .. 1604
+.. .. .. .. .. .. .. .. 1602
+.. .. .. .. .. .. .. .. .. 1600
+.. .. .. .. .. .. 1598
+.. .. .. .. .. .. .. .. 1596
+.. .. .. .. .. .. .. .. .. 1594
+.. .. .. .. .. .. .. 1592
+.. .. .. .. .. .. .. .. 1590
+.. .. .. .. 1588
+.. .. .. .. .. .. .. .. 1586
+.. .. .. .. .. .. .. 1584
+.. .. .. .. .. .. .. .. .. 1582
+.. .. .. .. .. .. .. .. 1580
+.. .. .. .. .. .. 1578
+.. .. .. .. .. .. .. .. 1576
+.. .. .. .. .. .. .. 1574
+.. .. .. .. .. .. .. .. 1572
+.. .. .. .. .. .. .. .. .. 1570
+.. .. .. .. .. 1568
+.. .. .. .. .. .. .. .. 1566
+.. .. .. .. .. .. .. 1564
+.. .. .. .. .. .. .. .. .. 1562
+.. .. .. .. .. .. .. .. 1560
+.. .. .. .. .. .. .. .. .. 1558
+.. .. .. .. .. .. 1556
+.. .. .. .. .. .. .. .. 1554
+.. .. .. .. .. .. .. 1552
+.. .. .. .. .. .. .. .. 1550
+.. 1548
+.. .. .. .. .. .. .. .. 1546
+.. .. .. .. .. .. .. 1544
+.. .. .. .. .. .. .. .. 1542
+.. .. .. .. .. .. 1540
+.. .. .. .. .. .. .. .. .. 1538
+.. .. .. .. .. .. .. .. 1536
+.. .. .. .. .. .. .. 1534
+.. .. .. .. .. .. .. .. 1532
+.. .. .. .. .. 1530
+.. .. .. .. .. .. .. .. .. 1528
+.. .. .. .. .. .. .. .. 1526
+.. .. .. .. .. .. .. 1524
+.. .. .. .. .. .. .. .. 1522
+.. .. .. .. .. .. .. .. .. 1520
+.. .. .. .. .. .. 1518
+.. .. .. .. .. .. .. .. 1516
+.. .. .. .. .. .. .. 1514
+.. .. .. .. .. .. .. .. .. 1512
+.. .. .. .. .. .. .. .. 1510
+.. .. .. .. 1508
+.. .. .. .. .. .. .. .. 1506
+.. .. .. .. .. .. .. 1504
+.. .. .. .. .. .. .. .. 1502
+.. .. .. .. .. .. 1500
+.. .. .. .. .. .. .. 1498
+.. .. .. .. .. .. .. .. 1496
+.. .. .. .. .. 1494
+.. .. .. .. .. .. .. 1492
+.. .. .. .. .. .. .. .. 1490
+.. .. .. .. .. .. 1488
+.. .. .. .. .. .. .. .. .. 1486
+.. .. .. .. .. .. .. .. 1484
+.. .. .. .. .. .. .. .. .. 1482
+.. .. .. .. .. .. .. 1480
+.. .. .. .. .. .. .. .. .. 1478
+.. .. .. .. .. .. .. .. 1476
+.. .. .. .. .. .. .. .. .. 1474
+.. .. .. 1472
+.. .. .. .. .. .. .. .. .. .. 1470
+.. .. .. .. .. .. .. .. .. 1468
+.. .. .. .. .. .. .. .. .. .. 1466
+.. .. .. .. .. .. .. .. 1464
+.. .. .. .. .. .. .. .. .. 1462
+.. .. .. .. .. .. .. 1460
+.. .. .. .. .. .. .. .. .. .. 1458
+.. .. .. .. .. .. .. .. .. 1456
+.. .. .. .. .. .. .. .. .. .. 1454
+.. .. .. .. .. .. .. .. 1452
+.. .. .. .. .. .. .. .. .. 1450
+.. .. .. .. .. .. .. .. .. .. 1448
+.. .. .. .. .. .. 1446
+.. .. .. .. .. .. .. .. .. 1444
+.. .. .. .. .. .. .. .. 1442
+.. .. .. .. .. .. .. .. .. 1440
+.. .. .. .. .. .. .. 1438
+.. .. .. .. .. .. .. .. 1436
+.. .. .. .. .. 1434
+.. .. .. .. .. .. .. .. .. 1432
+.. .. .. .. .. .. .. .. 1430
+.. .. .. .. .. .. .. .. .. 1428
+.. .. .. .. .. .. .. 1426
+.. .. .. .. .. .. .. .. .. .. 1424
+.. .. .. .. .. .. .. .. .. 1422
+.. .. .. .. .. .. .. .. .. .. 1420
+.. .. .. .. .. .. .. .. 1418
+.. .. .. .. .. .. .. .. .. .. 1416
+.. .. .. .. .. .. .. .. .. 1414
+.. .. .. .. .. .. 1412
+.. .. .. .. .. .. .. .. .. 1410
+.. .. .. .. .. .. .. .. 1408
+.. .. .. .. .. .. .. .. .. 1406
+.. .. .. .. .. .. .. .. .. .. 1404
+.. .. .. .. .. .. .. 1402
+.. .. .. .. .. .. .. .. .. .. 1400
+.. .. .. .. .. .. .. .. .. 1398
+.. .. .. .. .. .. .. .. .. .. 1396
+.. .. .. .. .. .. .. .. 1394
+.. .. .. .. .. .. .. .. .. .. 1392
+.. .. .. .. .. .. .. .. .. 1390
+.. .. .. .. 1388
+.. .. .. .. .. .. .. .. .. .. 1386
+.. .. .. .. .. .. .. .. .. 1384
+.. .. .. .. .. .. .. .. 1382
+.. .. .. .. .. .. .. .. .. .. 1380
+.. .. .. .. .. .. .. .. .. 1378
+.. .. .. .. .. .. .. .. .. .. 1376
+.. .. .. .. .. .. .. 1374
+.. .. .. .. .. .. .. .. 1372
+.. .. .. .. .. .. .. .. .. 1370
+.. .. .. .. .. .. 1368
+.. .. .. .. .. .. .. .. .. .. 1366
+.. .. .. .. .. .. .. .. .. 1364
+.. .. .. .. .. .. .. .. .. .. 1362
+.. .. .. .. .. .. .. .. 1360
+.. .. .. .. .. .. .. .. .. 1358
+.. .. .. .. .. .. .. 1356
+.. .. .. .. .. .. .. .. .. 1354
+.. .. .. .. .. .. .. .. .. .. 1352
+.. .. .. .. .. .. .. .. 1350
+.. .. .. .. .. .. .. .. .. .. 1348
+.. .. .. .. .. .. .. .. .. 1346
+.. .. .. .. .. .. .. .. .. .. 1344
+.. .. .. .. .. 1342
+.. .. .. .. .. .. .. .. .. .. 1340
+.. .. .. .. .. .. .. .. .. 1338
+.. .. .. .. .. .. .. .. 1336
+.. .. .. .. .. .. .. .. .. .. 1334
+.. .. .. .. .. .. .. .. .. 1332
+.. .. .. .. .. .. .. .. .. .. 1330
+.. .. .. .. .. .. .. 1328
+.. .. .. .. .. .. .. .. .. .. 1326
+.. .. .. .. .. .. .. .. .. 1324
+.. .. .. .. .. .. .. .. .. .. 1322
+.. .. .. .. .. .. .. .. 1320
+.. .. .. .. .. .. .. .. .. 1318
+.. .. .. .. .. .. .. .. .. .. 1316
+.. .. .. .. .. .. 1314
+.. .. .. .. .. .. .. .. 1312
+.. .. .. .. .. .. .. .. .. 1310
+.. .. .. .. .. .. .. 1308
+.. .. .. .. .. .. .. .. .. .. 1306
+.. .. .. .. .. .. .. .. .. 1304
+.. .. .. .. .. .. .. .. .. .. 1302
+.. .. .. .. .. .. .. .. 1300
+.. .. .. .. .. .. .. .. .. 1298
+.. .. .. .. .. .. .. .. .. .. 1296
+.. .. 1294
+.. .. .. .. .. .. .. .. .. 1292
+.. .. .. .. .. .. .. .. 1290
+.. .. .. .. .. .. .. 1288
+.. .. .. .. .. .. .. .. .. 1286
+.. .. .. .. .. .. .. .. 1284
+.. .. .. .. .. .. .. .. .. 1282
+.. .. .. .. .. .. 1280
+.. .. .. .. .. .. .. .. 1278
+.. .. .. .. .. .. .. 1276
+.. .. .. .. .. 1274
+.. .. .. .. .. .. .. .. 1272
+.. .. .. .. .. .. .. .. .. 1270
+.. .. .. .. .. .. .. 1268
+.. .. .. .. .. .. .. .. .. 1266
+.. .. .. .. .. .. .. .. 1264
+.. .. .. .. .. .. .. .. .. 1262
+.. .. .. .. .. .. 1260
+.. .. .. .. .. .. .. .. .. 1258
+.. .. .. .. .. .. .. .. 1256
+.. .. .. .. .. .. .. 1254
+.. .. .. .. .. .. .. .. .. .. 1252
+.. .. .. .. .. .. .. .. .. 1250
+.. .. .. .. .. .. .. .. 1248
+.. .. .. .. .. .. .. .. .. 1246
+.. .. .. .. .. .. .. .. .. .. 1244
+.. .. .. .. 1242
+.. .. .. .. .. .. .. .. .. 1240
+.. .. .. .. .. .. .. .. 1238
+.. .. .. .. .. .. .. .. .. 1236
+.. .. .. .. .. .. .. 1234
+.. .. .. .. .. .. .. .. 1232
+.. .. .. .. .. .. 1230
+.. .. .. .. .. .. .. .. .. 1228
+.. .. .. .. .. .. .. .. 1226
+.. .. .. .. .. .. .. 1224
+.. .. .. .. .. .. .. .. .. 1222
+.. .. .. .. .. .. .. .. 1220
+.. .. .. .. .. .. .. .. .. 1218
+.. .. .. .. .. 1216
+.. .. .. .. .. .. .. .. .. 1214
+.. .. .. .. .. .. .. .. 1212
+.. .. .. .. .. .. .. .. .. 1210
+.. .. .. .. .. .. .. 1208
+.. .. .. .. .. .. .. .. 1206
+.. .. .. .. .. .. 1204
+.. .. .. .. .. .. .. .. .. 1202
+.. .. .. .. .. .. .. .. .. .. 1200
+.. .. .. .. .. .. .. .. 1198
+.. .. .. .. .. .. .. .. .. 1196
+.. .. .. .. .. .. .. 1194
+.. .. .. .. .. .. .. .. .. 1192
+.. .. .. .. .. .. .. .. 1190
+.. .. .. .. .. .. .. .. .. 1188
+.. .. .. 1186
+.. .. .. .. .. .. .. .. .. 1184
+.. .. .. .. .. .. .. .. .. .. 1182
+.. .. .. .. .. .. .. .. 1180
+.. .. .. .. .. .. .. .. .. 1178
+.. .. .. .. .. .. .. 1176
+.. .. .. .. .. .. .. .. .. 1174
+.. .. .. .. .. .. .. .. .. .. 1172
+.. .. .. .. .. .. .. .. 1170
+.. .. .. .. .. .. .. .. .. 1168
+.. .. .. .. .. .. 1166
+.. .. .. .. .. .. .. .. .. .. 1164
+.. .. .. .. .. .. .. .. .. 1162
+.. .. .. .. .. .. .. .. 1160
+.. .. .. .. .. .. .. .. .. 1158
+.. .. .. .. .. .. .. .. .. .. 1156
+.. .. .. .. .. .. .. 1152
+.. .. .. .. .. .. .. .. .. 1150
+.. .. .. .. .. .. .. .. .. .. 1148
+.. .. .. .. .. .. .. .. 1146
+.. .. .. .. .. .. .. .. .. 1144
+.. .. .. .. .. 1142
+.. .. .. .. .. .. .. .. .. 1140
+.. .. .. .. .. .. .. .. 1138
+.. .. .. .. .. .. .. .. .. 1136
+.. .. .. .. .. .. .. 1134
+.. .. .. .. .. .. .. .. .. 1132
+.. .. .. .. .. .. .. .. 1130
+.. .. .. .. .. .. .. .. .. 1128
+.. .. .. .. .. .. .. .. .. .. 1126
+.. .. .. .. .. .. 1124
+.. .. .. .. .. .. .. .. .. 1122
+.. .. .. .. .. .. .. .. 1120
+.. .. .. .. .. .. .. .. .. 1118
+.. .. .. .. .. .. .. .. .. .. 1116
+.. .. .. .. .. .. .. 1114
+.. .. .. .. .. .. .. .. 1112
+.. .. .. .. .. .. .. .. .. 1110
+.. .. .. .. 1108
+.. .. .. .. .. .. .. .. .. 1106
+.. .. .. .. .. .. .. .. 1104
+.. .. .. .. .. .. .. .. .. 1102
+.. .. .. .. .. .. .. 1100
+.. .. .. .. .. .. .. .. .. 1098
+.. .. .. .. .. .. .. .. .. .. 1096
+.. .. .. .. .. .. .. .. 1094
+.. .. .. .. .. .. .. .. .. 1092
+.. .. .. .. .. .. 1090
+.. .. .. .. .. .. .. .. 1088
+.. .. .. .. .. .. .. .. .. 1086
+.. .. .. .. .. .. .. 1084
+.. .. .. .. .. .. .. .. 1082
+.. .. .. .. .. .. .. .. .. 1080
+.. .. .. .. .. 1078
+.. .. .. .. .. .. .. .. 1076
+.. .. .. .. .. .. .. 1074
+.. .. .. .. .. .. .. .. 1072
+.. .. .. .. .. .. .. .. .. 1070
+.. .. .. .. .. .. 1068
+.. .. .. .. .. .. .. 1066
+.. .. .. .. .. .. .. .. 1064
+1062
+.. .. .. .. .. .. .. .. .. 1060
+.. .. .. .. .. .. .. .. 1058
+.. .. .. .. .. .. .. .. .. 1056
+.. .. .. .. .. .. .. 1054
+.. .. .. .. .. .. .. .. .. 1052
+.. .. .. .. .. .. .. .. 1050
+.. .. .. .. .. .. .. .. .. .. 1048
+.. .. .. .. .. .. .. .. .. 1046
+.. .. .. .. .. .. 1044
+.. .. .. .. .. .. .. .. .. .. 1042
+.. .. .. .. .. .. .. .. .. .. .. 1040
+.. .. .. .. .. .. .. .. .. 1038
+.. .. .. .. .. .. .. .. .. .. .. 1036
+.. .. .. .. .. .. .. .. .. .. 1034
+.. .. .. .. .. .. .. .. .. .. .. 1032
+.. .. .. .. .. .. .. .. 1030
+.. .. .. .. .. .. .. .. .. .. 1028
+.. .. .. .. .. .. .. .. .. 1026
+.. .. .. .. .. .. .. .. .. .. 1024
+.. .. .. .. .. .. .. 1022
+.. .. .. .. .. .. .. .. .. .. 1020
+.. .. .. .. .. .. .. .. .. 1018
+.. .. .. .. .. .. .. .. .. .. 1016
+.. .. .. .. .. .. .. .. 1014
+.. .. .. .. .. .. .. .. .. .. 1012
+.. .. .. .. .. .. .. .. .. 1010
+.. .. .. .. .. .. .. .. .. .. 1008
+.. .. .. .. .. 1006
+.. .. .. .. .. .. .. .. .. 1004
+.. .. .. .. .. .. .. .. 1002
+.. .. .. .. .. .. .. .. .. 1000
+.. .. .. .. .. .. .. 998
+.. .. .. .. .. .. .. .. .. .. 996
+.. .. .. .. .. .. .. .. .. 994
+.. .. .. .. .. .. .. .. .. .. 992
+.. .. .. .. .. .. .. .. 990
+.. .. .. .. .. .. .. .. .. 988
+.. .. .. .. .. .. 986
+.. .. .. .. .. .. .. .. .. .. 984
+.. .. .. .. .. .. .. .. .. 982
+.. .. .. .. .. .. .. .. .. .. 980
+.. .. .. .. .. .. .. .. 978
+.. .. .. .. .. .. .. .. .. 976
+.. .. .. .. .. .. .. .. .. .. 974
+.. .. .. .. .. .. .. 972
+.. .. .. .. .. .. .. .. .. 970
+.. .. .. .. .. .. .. .. 968
+.. .. .. .. .. .. .. .. .. 966
+.. .. .. .. 964
+.. .. .. .. .. .. .. .. .. 962
+.. .. .. .. .. .. .. .. .. .. 960
+.. .. .. .. .. .. .. .. 958
+.. .. .. .. .. .. .. .. .. 956
+.. .. .. .. .. .. .. 954
+.. .. .. .. .. .. .. .. 952
+.. .. .. .. .. .. .. .. .. 950
+.. .. .. .. .. .. 948
+.. .. .. .. .. .. .. .. .. 946
+.. .. .. .. .. .. .. .. .. .. 944
+.. .. .. .. .. .. .. .. 942
+.. .. .. .. .. .. .. .. .. 940
+.. .. .. .. .. .. .. 938
+.. .. .. .. .. .. .. .. .. .. 936
+.. .. .. .. .. .. .. .. .. 934
+.. .. .. .. .. .. .. .. 932
+.. .. .. .. .. .. .. .. .. .. 930
+.. .. .. .. .. .. .. .. .. 928
+.. .. .. .. .. .. .. .. .. .. 926
+.. .. .. .. .. 924
+.. .. .. .. .. .. .. .. .. 922
+.. .. .. .. .. .. .. .. 920
+.. .. .. .. .. .. .. .. .. .. 918
+.. .. .. .. .. .. .. .. .. 916
+.. .. .. .. .. .. .. 914
+.. .. .. .. .. .. .. .. .. 912
+.. .. .. .. .. .. .. .. 910
+.. .. .. .. .. .. 908
+.. .. .. .. .. .. .. .. 906
+.. .. .. .. .. .. .. 904
+.. .. .. .. .. .. .. .. .. 900
+.. .. .. .. .. .. .. .. 898
+.. .. .. 896
+.. .. .. .. .. .. .. .. .. 894
+.. .. .. .. .. .. .. .. 892
+.. .. .. .. .. .. .. .. .. 890
+.. .. .. .. .. .. .. .. .. .. 888
+.. .. .. .. .. .. .. 886
+.. .. .. .. .. .. .. .. .. .. 884
+.. .. .. .. .. .. .. .. .. 882
+.. .. .. .. .. .. .. .. .. .. .. 880
+.. .. .. .. .. .. .. .. .. .. 878
+.. .. .. .. .. .. .. .. 876
+.. .. .. .. .. .. .. .. .. .. 874
+.. .. .. .. .. .. .. .. .. 872
+.. .. .. .. .. .. .. .. .. .. 870
+.. .. .. .. .. .. 868
+.. .. .. .. .. .. .. .. .. .. 866
+.. .. .. .. .. .. .. .. .. 864
+.. .. .. .. .. .. .. .. 862
+.. .. .. .. .. .. .. .. .. 860
+.. .. .. .. .. .. .. .. .. .. 858
+.. .. .. .. .. .. .. 856
+.. .. .. .. .. .. .. .. .. 854
+.. .. .. .. .. .. .. .. 852
+.. .. .. .. .. .. .. .. .. 850
+.. .. .. .. .. .. .. .. .. .. 848
+.. .. .. .. .. 846
+.. .. .. .. .. .. .. .. .. .. 844
+.. .. .. .. .. .. .. .. .. 842
+.. .. .. .. .. .. .. .. 840
+.. .. .. .. .. .. .. .. .. 838
+.. .. .. .. .. .. .. 836
+.. .. .. .. .. .. .. .. .. 834
+.. .. .. .. .. .. .. .. .. .. 832
+.. .. .. .. .. .. .. .. 830
+.. .. .. .. .. .. .. .. .. 828
+.. .. .. .. .. .. 826
+.. .. .. .. .. .. .. .. .. 824
+.. .. .. .. .. .. .. .. 822
+.. .. .. .. .. .. .. 820
+.. .. .. .. .. .. .. .. .. .. 818
+.. .. .. .. .. .. .. .. .. 816
+.. .. .. .. .. .. .. .. 814
+.. .. .. .. .. .. .. .. .. .. 812
+.. .. .. .. .. .. .. .. .. 810
+.. .. .. .. 808
+.. .. .. .. .. .. .. .. .. 806
+.. .. .. .. .. .. .. .. 804
+.. .. .. .. .. .. .. 802
+.. .. .. .. .. .. .. .. .. 800
+.. .. .. .. .. .. .. .. 798
+.. .. .. .. .. .. .. .. .. 796
+.. .. .. .. .. .. 794
+.. .. .. .. .. .. .. .. .. 792
+.. .. .. .. .. .. .. .. 790
+.. .. .. .. .. .. .. .. .. 788
+.. .. .. .. .. .. .. 786
+.. .. .. .. .. .. .. .. 784
+.. .. .. .. .. .. .. .. .. 782
+.. .. .. .. .. 780
+.. .. .. .. .. .. .. .. .. .. 778
+.. .. .. .. .. .. .. .. .. 776
+.. .. .. .. .. .. .. .. .. .. 774
+.. .. .. .. .. .. .. .. 772
+.. .. .. .. .. .. .. .. .. 770
+.. .. .. .. .. .. .. 768
+.. .. .. .. .. .. .. .. .. .. 766
+.. .. .. .. .. .. .. .. .. 764
+.. .. .. .. .. .. .. .. 762
+.. .. .. .. .. .. .. .. .. .. 760
+.. .. .. .. .. .. .. .. .. 758
+.. .. .. .. .. .. .. .. .. .. 756
+.. .. .. .. .. .. 754
+.. .. .. .. .. .. .. .. .. .. 752
+.. .. .. .. .. .. .. .. .. 750
+.. .. .. .. .. .. .. .. .. .. 748
+.. .. .. .. .. .. .. .. 746
+.. .. .. .. .. .. .. .. .. .. 744
+.. .. .. .. .. .. .. .. .. 742
+.. .. .. .. .. .. .. .. .. .. 740
+.. .. .. .. .. .. .. 738
+.. .. .. .. .. .. .. .. .. 736
+.. .. .. .. .. .. .. .. 734
+.. .. .. .. .. .. .. .. .. 732
+.. .. .. .. .. .. .. .. .. .. 730
+.. .. 728
+.. .. .. .. .. .. .. .. 726
+.. .. .. .. .. .. .. .. .. 724
+.. .. .. .. .. .. .. 722
+.. .. .. .. .. .. .. .. .. 720
+.. .. .. .. .. .. .. .. .. .. 718
+.. .. .. .. .. .. .. .. 716
+.. .. .. .. .. .. .. .. .. 714
+.. .. .. .. .. .. 712
+.. .. .. .. .. .. .. .. .. 710
+.. .. .. .. .. .. .. .. 708
+.. .. .. .. .. .. .. 706
+.. .. .. .. .. .. .. .. .. 704
+.. .. .. .. .. .. .. .. 702
+.. .. .. .. .. .. .. .. .. 700
+.. .. .. .. .. 698
+.. .. .. .. .. .. .. .. 696
+.. .. .. .. .. .. .. 694
+.. .. .. .. .. .. .. .. 692
+.. .. .. .. .. .. .. .. .. 690
+.. .. .. .. .. .. 688
+.. .. .. .. .. .. .. 686
+.. .. .. .. .. .. .. .. 684
+.. .. .. .. 682
+.. .. .. .. .. .. .. .. 680
+.. .. .. .. .. .. .. 678
+.. .. .. .. .. .. 676
+.. .. .. .. .. .. .. .. 674
+.. .. .. .. .. .. .. 672
+.. .. .. .. .. .. .. .. 670
+.. .. .. .. .. 668
+.. .. .. .. .. .. .. .. .. 666
+.. .. .. .. .. .. .. .. 664
+.. .. .. .. .. .. .. .. .. 662
+.. .. .. .. .. .. .. 660
+.. .. .. .. .. .. .. .. 658
+.. .. .. .. .. .. 656
+.. .. .. .. .. .. .. .. .. 654
+.. .. .. .. .. .. .. .. 652
+.. .. .. .. .. .. .. .. .. 650
+.. .. .. .. .. .. .. 648
+.. .. .. .. .. .. .. .. 646
+.. .. .. .. .. .. .. .. .. 644
+.. .. .. 642
+.. .. .. .. .. .. .. .. .. 640
+.. .. .. .. .. .. .. .. 638
+.. .. .. .. .. .. .. 636
+.. .. .. .. .. .. .. .. .. 634
+.. .. .. .. .. .. .. .. 632
+.. .. .. .. .. .. .. .. .. 630
+.. .. .. .. .. .. 628
+.. .. .. .. .. .. .. .. .. 626
+.. .. .. .. .. .. .. .. 624
+.. .. .. .. .. .. .. .. .. 622
+.. .. .. .. .. .. .. 620
+.. .. .. .. .. .. .. .. .. 618
+.. .. .. .. .. .. .. .. 616
+.. .. .. .. .. 614
+.. .. .. .. .. .. .. .. .. 612
+.. .. .. .. .. .. .. .. 610
+.. .. .. .. .. .. .. .. .. .. 608
+.. .. .. .. .. .. .. .. .. 606
+.. .. .. .. .. .. .. .. .. .. 604
+.. .. .. .. .. .. .. 602
+.. .. .. .. .. .. .. .. .. 600
+.. .. .. .. .. .. .. .. 598
+.. .. .. .. .. .. 596
+.. .. .. .. .. .. .. .. .. 594
+.. .. .. .. .. .. .. .. 592
+.. .. .. .. .. .. .. .. .. 590
+.. .. .. .. .. .. .. 588
+.. .. .. .. .. .. .. .. .. .. 586
+.. .. .. .. .. .. .. .. .. 584
+.. .. .. .. .. .. .. .. 582
+.. .. .. .. .. .. .. .. .. 580
+.. .. .. .. 578
+.. .. .. .. .. .. .. .. .. 576
+.. .. .. .. .. .. .. .. 574
+.. .. .. .. .. .. .. .. .. 572
+.. .. .. .. .. .. .. 570
+.. .. .. .. .. .. .. .. .. .. 568
+.. .. .. .. .. .. .. .. .. 566
+.. .. .. .. .. .. .. .. .. .. 564
+.. .. .. .. .. .. .. .. 562
+.. .. .. .. .. .. .. .. .. 560
+.. .. .. .. .. .. .. .. .. .. 558
+.. .. .. .. .. .. 556
+.. .. .. .. .. .. .. .. .. 554
+.. .. .. .. .. .. .. .. 552
+.. .. .. .. .. .. .. 550
+.. .. .. .. .. .. .. .. .. 548
+.. .. .. .. .. .. .. .. 546
+.. .. .. .. .. 544
+.. .. .. .. .. .. .. .. 542
+.. .. .. .. .. .. .. .. .. 540
+.. .. .. .. .. .. .. 538
+.. .. .. .. .. .. .. .. .. 536
+.. .. .. .. .. .. .. .. 534
+.. .. .. .. .. .. .. .. .. 532
+.. .. .. .. .. .. 530
+.. .. .. .. .. .. .. .. 528
+.. .. .. .. .. .. .. 526
+.. .. .. .. .. .. .. .. 524
+.. 522
+.. .. .. .. .. .. .. .. .. .. 520
+.. .. .. .. .. .. .. .. .. 518
+.. .. .. .. .. .. .. .. 516
+.. .. .. .. .. .. .. .. .. 514
+.. .. .. .. .. .. .. .. .. .. 512
+.. .. .. .. .. .. .. 510
+.. .. .. .. .. .. .. .. .. 508
+.. .. .. .. .. .. .. .. 506
+.. .. .. .. .. .. .. .. .. 504
+.. .. .. .. .. .. 502
+.. .. .. .. .. .. .. .. .. .. 500
+.. .. .. .. .. .. .. .. .. 498
+.. .. .. .. .. .. .. .. 496
+.. .. .. .. .. .. .. .. .. 494
+.. .. .. .. .. .. .. 492
+.. .. .. .. .. .. .. .. .. .. 490
+.. .. .. .. .. .. .. .. .. 488
+.. .. .. .. .. .. .. .. 486
+.. .. .. .. .. .. .. .. .. 484
+.. .. .. .. .. 482
+.. .. .. .. .. .. .. .. .. 480
+.. .. .. .. .. .. .. .. 478
+.. .. .. .. .. .. .. .. .. 476
+.. .. .. .. .. .. .. 474
+.. .. .. .. .. .. .. .. 472
+.. .. .. .. .. .. 470
+.. .. .. .. .. .. .. .. 468
+.. .. .. .. .. .. .. 466
+.. .. .. .. .. .. .. .. 464
+.. .. .. .. 462
+.. .. .. .. .. .. .. .. .. .. 460
+.. .. .. .. .. .. .. .. .. 458
+.. .. .. .. .. .. .. .. .. .. 456
+.. .. .. .. .. .. .. .. 454
+.. .. .. .. .. .. .. .. .. .. 452
+.. .. .. .. .. .. .. .. .. 450
+.. .. .. .. .. .. .. .. .. .. 448
+.. .. .. .. .. .. .. 446
+.. .. .. .. .. .. .. .. 444
+.. .. .. .. .. .. .. .. .. 442
+.. .. .. .. .. .. 440
+.. .. .. .. .. .. .. .. .. .. 438
+.. .. .. .. .. .. .. .. .. 436
+.. .. .. .. .. .. .. .. .. .. 434
+.. .. .. .. .. .. .. .. 432
+.. .. .. .. .. .. .. .. .. 430
+.. .. .. .. .. .. .. 428
+.. .. .. .. .. .. .. .. 426
+.. .. .. .. .. .. .. .. .. 424
+.. .. .. .. .. 422
+.. .. .. .. .. .. .. .. .. 420
+.. .. .. .. .. .. .. .. .. .. 418
+.. .. .. .. .. .. .. .. 416
+.. .. .. .. .. .. .. .. .. .. 414
+.. .. .. .. .. .. .. .. .. 412
+.. .. .. .. .. .. .. 410
+.. .. .. .. .. .. .. .. .. 408
+.. .. .. .. .. .. .. .. .. .. 406
+.. .. .. .. .. .. .. .. 404
+.. .. .. .. .. .. .. .. .. 402
+.. .. .. .. .. .. .. .. .. .. 400
+.. .. .. .. .. .. 398
+.. .. .. .. .. .. .. .. .. 396
+.. .. .. .. .. .. .. .. 394
+.. .. .. .. .. .. .. .. .. 392
+.. .. .. .. .. .. .. .. .. .. 390
+.. .. .. .. .. .. .. 388
+.. .. .. .. .. .. .. .. .. .. 386
+.. .. .. .. .. .. .. .. .. 384
+.. .. .. .. .. .. .. .. 382
+.. .. .. .. .. .. .. .. .. .. 380
+.. .. .. .. .. .. .. .. .. 378
+.. .. .. .. .. .. .. .. .. .. 376
+.. .. .. 374
+.. .. .. .. .. .. .. .. 372
+.. .. .. .. .. .. .. 370
+.. .. .. .. .. .. 368
+.. .. .. .. .. .. .. .. 366
+.. .. .. .. .. .. .. .. .. 364
+.. .. .. .. .. .. .. 362
+.. .. .. .. .. .. .. .. 360
+.. .. .. .. .. 358
+.. .. .. .. .. .. .. .. 356
+.. .. .. .. .. .. .. .. .. 354
+.. .. .. .. .. .. .. 352
+.. .. .. .. .. .. .. .. .. 350
+.. .. .. .. .. .. .. .. 348
+.. .. .. .. .. .. .. .. .. 346
+.. .. .. .. .. .. 344
+.. .. .. .. .. .. .. .. .. 342
+.. .. .. .. .. .. .. .. 340
+.. .. .. .. .. .. .. .. .. 338
+.. .. .. .. .. .. .. 336
+.. .. .. .. .. .. .. .. .. 334
+.. .. .. .. .. .. .. .. 332
+.. .. .. .. .. .. .. .. .. 330
+.. .. .. .. 328
+.. .. .. .. .. .. .. .. .. 326
+.. .. .. .. .. .. .. .. 324
+.. .. .. .. .. .. .. 322
+.. .. .. .. .. .. .. .. 320
+.. .. .. .. .. .. 318
+.. .. .. .. .. .. .. .. .. 316
+.. .. .. .. .. .. .. .. 314
+.. .. .. .. .. .. .. .. .. .. 312
+.. .. .. .. .. .. .. .. .. 310
+.. .. .. .. .. .. .. .. .. .. 308
+.. .. .. .. .. .. .. 306
+.. .. .. .. .. .. .. .. .. .. 304
+.. .. .. .. .. .. .. .. .. 302
+.. .. .. .. .. .. .. .. 300
+.. .. .. .. .. .. .. .. .. 298
+.. .. .. .. .. 296
+.. .. .. .. .. .. .. .. .. 294
+.. .. .. .. .. .. .. .. 292
+.. .. .. .. .. .. .. .. .. 290
+.. .. .. .. .. .. .. 288
+.. .. .. .. .. .. .. .. 286
+.. .. .. .. .. .. 284
+.. .. .. .. .. .. .. .. .. 282
+.. .. .. .. .. .. .. .. 280
+.. .. .. .. .. .. .. .. .. 278
+.. .. .. .. .. .. .. 276
+.. .. .. .. .. .. .. .. .. .. 274
+.. .. .. .. .. .. .. .. .. 272
+.. .. .. .. .. .. .. .. 270
+.. .. .. .. .. .. .. .. .. 268
+.. .. 266
+.. .. .. .. .. .. .. .. .. 264
+.. .. .. .. .. .. .. .. 262
+.. .. .. .. .. .. .. .. .. 260
+.. .. .. .. .. .. .. 258
+.. .. .. .. .. .. .. .. .. 256
+.. .. .. .. .. .. .. .. 254
+.. .. .. .. .. .. .. .. .. 252
+.. .. .. .. .. .. 250
+.. .. .. .. .. .. .. .. .. 248
+.. .. .. .. .. .. .. .. 246
+.. .. .. .. .. .. .. .. .. 244
+.. .. .. .. .. .. .. 242
+.. .. .. .. .. .. .. .. 240
+.. .. .. .. .. 238
+.. .. .. .. .. .. .. .. .. 236
+.. .. .. .. .. .. .. .. 234
+.. .. .. .. .. .. .. .. .. 232
+.. .. .. .. .. .. .. 230
+.. .. .. .. .. .. .. .. 228
+.. .. .. .. .. .. 226
+.. .. .. .. .. .. .. .. .. .. 224
+.. .. .. .. .. .. .. .. .. 222
+.. .. .. .. .. .. .. .. 220
+.. .. .. .. .. .. .. .. .. .. 218
+.. .. .. .. .. .. .. .. .. 216
+.. .. .. .. .. .. .. 214
+.. .. .. .. .. .. .. .. .. 212
+.. .. .. .. .. .. .. .. 210
+.. .. .. .. 208
+.. .. .. .. .. .. .. .. .. .. 206
+.. .. .. .. .. .. .. .. .. 204
+.. .. .. .. .. .. .. .. .. .. 202
+.. .. .. .. .. .. .. .. 200
+.. .. .. .. .. .. .. .. .. .. 198
+.. .. .. .. .. .. .. .. .. 196
+.. .. .. .. .. .. .. 194
+.. .. .. .. .. .. .. .. .. 192
+.. .. .. .. .. .. .. .. .. .. 190
+.. .. .. .. .. .. .. .. 188
+.. .. .. .. .. .. .. .. .. 186
+.. .. .. .. .. .. 184
+.. .. .. .. .. .. .. .. .. 182
+.. .. .. .. .. .. .. .. 180
+.. .. .. .. .. .. .. .. .. 178
+.. .. .. .. .. .. .. 176
+.. .. .. .. .. .. .. .. .. .. 174
+.. .. .. .. .. .. .. .. .. 172
+.. .. .. .. .. .. .. .. 170
+.. .. .. .. .. .. .. .. .. .. 168
+.. .. .. .. .. .. .. .. .. 166
+.. .. .. .. .. .. .. .. .. .. 164
+.. .. .. .. .. 162
+.. .. .. .. .. .. .. .. .. 160
+.. .. .. .. .. .. .. .. 158
+.. .. .. .. .. .. .. .. .. 156
+.. .. .. .. .. .. .. 154
+.. .. .. .. .. .. .. .. 152
+.. .. .. .. .. .. .. .. .. 150
+.. .. .. .. .. .. 148
+.. .. .. .. .. .. .. .. 146
+.. .. .. .. .. .. .. .. .. 144
+.. .. .. .. .. .. .. 142
+.. .. .. .. .. .. .. .. .. 140
+.. .. .. .. .. .. .. .. 138
+.. .. .. .. .. .. .. .. .. .. 136
+.. .. .. .. .. .. .. .. .. 134
+.. .. .. 132
+.. .. .. .. .. .. .. .. 130
+.. .. .. .. .. .. .. 128
+.. .. .. .. .. .. .. .. .. 126
+.. .. .. .. .. .. .. .. 124
+.. .. .. .. .. .. 122
+.. .. .. .. .. .. .. .. .. 120
+.. .. .. .. .. .. .. .. 118
+.. .. .. .. .. .. .. 116
+.. .. .. .. .. .. .. .. .. 114
+.. .. .. .. .. .. .. .. 112
+.. .. .. .. .. .. .. .. .. 110
+.. .. .. .. .. 108
+.. .. .. .. .. .. .. .. .. 106
+.. .. .. .. .. .. .. .. 104
+.. .. .. .. .. .. .. .. .. 102
+.. .. .. .. .. .. .. 100
+.. .. .. .. .. .. .. .. .. 98
+.. .. .. .. .. .. .. .. 96
+.. .. .. .. .. .. .. .. .. 94
+.. .. .. .. .. .. .. .. .. .. 92
+.. .. .. .. .. .. 90
+.. .. .. .. .. .. .. .. .. 88
+.. .. .. .. .. .. .. .. 86
+.. .. .. .. .. .. .. .. .. 84
+.. .. .. .. .. .. .. 82
+.. .. .. .. .. .. .. .. .. 80
+.. .. .. .. .. .. .. .. 78
+.. .. .. .. 76
+.. .. .. .. .. .. .. .. .. 74
+.. .. .. .. .. .. .. .. 72
+.. .. .. .. .. .. .. .. .. 70
+.. .. .. .. .. .. .. 68
+.. .. .. .. .. .. .. .. .. .. 66
+.. .. .. .. .. .. .. .. .. 64
+.. .. .. .. .. .. .. .. .. .. 62
+.. .. .. .. .. .. .. .. 60
+.. .. .. .. .. .. .. .. .. 58
+.. .. .. .. .. .. 56
+.. .. .. .. .. .. .. .. .. 54
+.. .. .. .. .. .. .. .. 52
+.. .. .. .. .. .. .. .. .. 50
+.. .. .. .. .. .. .. 48
+.. .. .. .. .. .. .. .. .. 46
+.. .. .. .. .. .. .. .. 44
+.. .. .. .. .. .. .. .. .. 42
+.. .. .. .. .. 40
+.. .. .. .. .. .. .. .. .. .. 38
+.. .. .. .. .. .. .. .. .. 36
+.. .. .. .. .. .. .. .. 34
+.. .. .. .. .. .. .. .. .. 32
+.. .. .. .. .. .. .. 30
+.. .. .. .. .. .. .. .. .. 28
+.. .. .. .. .. .. .. .. 26
+.. .. .. .. .. .. .. .. .. 24
+.. .. .. .. .. .. .. .. .. .. 22
+.. .. .. .. .. .. 20
+.. .. .. .. .. .. .. .. .. .. 18
+.. .. .. .. .. .. .. .. .. 16
+.. .. .. .. .. .. .. .. .. .. 14
+.. .. .. .. .. .. .. .. 12
+.. .. .. .. .. .. .. .. .. 10
+.. .. .. .. .. .. .. .. .. .. 8
+.. .. .. .. .. .. .. 6
+.. .. .. .. .. .. .. .. .. 4
+.. .. .. .. .. .. .. .. 2
+.. .. .. .. .. .. .. .. .. 0
+-- end oset, shared pool ----------------
+-- start cloned oset, shared pool ----------------
+.. .. .. .. .. .. .. .. .. 1998
+.. .. .. .. .. .. .. .. 1996
+.. .. .. .. .. .. .. .. .. .. 1994
+.. .. .. .. .. .. .. .. .. 1992
+.. .. .. .. .. .. .. .. .. .. 1990
+.. .. .. .. .. .. .. 1988
+.. .. .. .. .. .. .. .. .. 1986
+.. .. .. .. .. .. .. .. .. .. 1984
+.. .. .. .. .. .. .. .. 1982
+.. .. .. .. .. .. .. .. .. .. 1980
+.. .. .. .. .. .. .. .. .. 1978
+.. .. .. .. .. .. .. .. .. .. 1976
+.. .. .. .. .. .. 1974
+.. .. .. .. .. .. .. .. .. .. 1972
+.. .. .. .. .. .. .. .. .. 1970
+.. .. .. .. .. .. .. .. .. .. 1968
+.. .. .. .. .. .. .. .. 1966
+.. .. .. .. .. .. .. .. .. .. 1964
+.. .. .. .. .. .. .. .. .. 1962
+.. .. .. .. .. .. .. 1960
+.. .. .. .. .. .. .. .. .. .. 1958
+.. .. .. .. .. .. .. .. .. 1956
+.. .. .. .. .. .. .. .. 1954
+.. .. .. .. .. .. .. .. .. .. 1952
+.. .. .. .. .. .. .. .. .. 1950
+.. .. .. .. .. .. .. .. .. .. 1948
+.. .. .. .. .. 1946
+.. .. .. .. .. .. .. .. .. 1944
+.. .. .. .. .. .. .. .. 1942
+.. .. .. .. .. .. .. 1940
+.. .. .. .. .. .. .. .. .. .. 1938
+.. .. .. .. .. .. .. .. .. 1936
+.. .. .. .. .. .. .. .. 1934
+.. .. .. .. .. .. .. .. .. 1932
+.. .. .. .. .. .. 1930
+.. .. .. .. .. .. .. .. .. 1928
+.. .. .. .. .. .. .. .. .. .. 1926
+.. .. .. .. .. .. .. .. 1924
+.. .. .. .. .. .. .. .. .. .. 1922
+.. .. .. .. .. .. .. .. .. 1920
+.. .. .. .. .. .. .. .. .. .. 1918
+.. .. .. .. .. .. .. 1916
+.. .. .. .. .. .. .. .. .. 1914
+.. .. .. .. .. .. .. .. 1912
+.. .. .. .. .. .. .. .. .. .. 1910
+.. .. .. .. .. .. .. .. .. 1908
+.. .. .. .. .. .. .. .. .. .. 1906
+.. .. .. .. 1904
+.. .. .. .. .. .. .. .. .. 1902
+.. .. .. .. .. .. .. .. 1900
+.. .. .. .. .. .. .. 1898
+.. .. .. .. .. .. .. .. .. 1896
+.. .. .. .. .. .. .. .. 1894
+.. .. .. .. .. .. .. .. .. 1892
+.. .. .. .. .. .. 1890
+.. .. .. .. .. .. .. .. .. .. 1888
+.. .. .. .. .. .. .. .. .. 1886
+.. .. .. .. .. .. .. .. .. .. 1884
+.. .. .. .. .. .. .. .. 1882
+.. .. .. .. .. .. .. .. .. 1880
+.. .. .. .. .. .. .. 1878
+.. .. .. .. .. .. .. .. 1876
+.. .. .. .. .. .. .. .. .. 1874
+.. .. .. .. .. 1872
+.. .. .. .. .. .. .. .. .. .. 1870
+.. .. .. .. .. .. .. .. .. 1868
+.. .. .. .. .. .. .. .. .. .. 1866
+.. .. .. .. .. .. .. .. 1864
+.. .. .. .. .. .. .. .. .. 1862
+.. .. .. .. .. .. .. .. .. .. 1860
+.. .. .. .. .. .. .. 1858
+.. .. .. .. .. .. .. .. .. 1856
+.. .. .. .. .. .. .. .. 1854
+.. .. .. .. .. .. .. .. .. 1852
+.. .. .. .. .. .. 1848
+.. .. .. .. .. .. .. .. .. 1846
+.. .. .. .. .. .. .. .. 1844
+.. .. .. .. .. .. .. .. .. .. 1842
+.. .. .. .. .. .. .. .. .. 1840
+.. .. .. .. .. .. .. 1838
+.. .. .. .. .. .. .. .. .. .. 1836
+.. .. .. .. .. .. .. .. .. 1834
+.. .. .. .. .. .. .. .. .. .. 1832
+.. .. .. .. .. .. .. .. 1830
+.. .. .. .. .. .. .. .. .. .. 1828
+.. .. .. .. .. .. .. .. .. 1826
+.. .. .. .. .. .. .. .. .. .. 1824
+.. .. .. 1822
+.. .. .. .. .. .. .. .. 1820
+.. .. .. .. .. .. .. .. .. 1818
+.. .. .. .. .. .. .. 1816
+.. .. .. .. .. .. .. .. 1814
+.. .. .. .. .. .. 1812
+.. .. .. .. .. .. .. .. 1810
+.. .. .. .. .. .. .. .. .. 1808
+.. .. .. .. .. .. .. 1806
+.. .. .. .. .. .. .. .. 1804
+.. .. .. .. .. 1802
+.. .. .. .. .. .. .. .. 1800
+.. .. .. .. .. .. .. .. .. 1798
+.. .. .. .. .. .. .. 1796
+.. .. .. .. .. .. .. .. 1794
+.. .. .. .. .. .. 1792
+.. .. .. .. .. .. .. .. 1790
+.. .. .. .. .. .. .. .. .. 1788
+.. .. .. .. .. .. .. 1786
+.. .. .. .. .. .. .. .. .. 1784
+.. .. .. .. .. .. .. .. 1782
+.. .. .. .. .. .. .. .. .. 1780
+.. .. .. .. 1778
+.. .. .. .. .. .. .. .. .. 1776
+.. .. .. .. .. .. .. .. 1774
+.. .. .. .. .. .. .. 1772
+.. .. .. .. .. .. .. .. 1770
+.. .. .. .. .. .. 1768
+.. .. .. .. .. .. .. .. .. 1766
+.. .. .. .. .. .. .. .. 1764
+.. .. .. .. .. .. .. .. .. 1762
+.. .. .. .. .. .. .. 1760
+.. .. .. .. .. .. .. .. .. 1758
+.. .. .. .. .. .. .. .. 1756
+.. .. .. .. .. 1754
+.. .. .. .. .. .. .. .. 1752
+.. .. .. .. .. .. .. 1750
+.. .. .. .. .. .. .. .. .. 1748
+.. .. .. .. .. .. .. .. 1746
+.. .. .. .. .. .. 1744
+.. .. .. .. .. .. .. .. .. 1742
+.. .. .. .. .. .. .. .. 1740
+.. .. .. .. .. .. .. .. .. 1738
+.. .. .. .. .. .. .. 1736
+.. .. .. .. .. .. .. .. .. 1734
+.. .. .. .. .. .. .. .. .. .. 1732
+.. .. .. .. .. .. .. .. 1730
+.. .. .. .. .. .. .. .. .. 1728
+.. .. 1726
+.. .. .. .. .. .. .. .. .. 1724
+.. .. .. .. .. .. .. .. 1722
+.. .. .. .. .. .. .. .. .. 1720
+.. .. .. .. .. .. .. .. .. .. 1718
+.. .. .. .. .. .. .. 1716
+.. .. .. .. .. .. .. .. .. 1714
+.. .. .. .. .. .. .. .. 1712
+.. .. .. .. .. .. 1710
+.. .. .. .. .. .. .. .. .. 1708
+.. .. .. .. .. .. .. .. 1706
+.. .. .. .. .. .. .. 1704
+.. .. .. .. .. .. .. .. .. 1702
+.. .. .. .. .. .. .. .. .. .. 1700
+.. .. .. .. .. .. .. .. 1698
+.. .. .. .. .. .. .. .. .. 1696
+.. .. .. .. .. 1694
+.. .. .. .. .. .. .. .. 1692
+.. .. .. .. .. .. .. .. .. 1690
+.. .. .. .. .. .. .. 1688
+.. .. .. .. .. .. .. .. .. 1686
+.. .. .. .. .. .. .. .. 1684
+.. .. .. .. .. .. .. .. .. 1682
+.. .. .. .. .. .. 1680
+.. .. .. .. .. .. .. .. 1678
+.. .. .. .. .. .. .. 1676
+.. .. .. .. 1674
+.. .. .. .. .. .. .. .. 1672
+.. .. .. .. .. .. .. 1670
+.. .. .. .. .. .. .. .. 1668
+.. .. .. .. .. .. 1666
+.. .. .. .. .. .. .. .. .. 1664
+.. .. .. .. .. .. .. .. 1662
+.. .. .. .. .. .. .. 1660
+.. .. .. .. .. .. .. .. 1658
+.. .. .. .. .. 1656
+.. .. .. .. .. .. .. .. .. 1654
+.. .. .. .. .. .. .. .. 1652
+.. .. .. .. .. .. .. 1650
+.. .. .. .. .. .. .. .. .. 1648
+.. .. .. .. .. .. .. .. 1646
+.. .. .. .. .. .. .. .. .. 1644
+.. .. .. .. .. .. 1642
+.. .. .. .. .. .. .. .. 1640
+.. .. .. .. .. .. .. .. .. 1638
+.. .. .. .. .. .. .. 1636
+.. .. .. .. .. .. .. .. .. 1634
+.. .. .. .. .. .. .. .. 1632
+.. .. .. .. .. .. .. .. .. 1630
+.. .. .. 1628
+.. .. .. .. .. .. .. .. 1626
+.. .. .. .. .. .. .. 1624
+.. .. .. .. .. .. 1622
+.. .. .. .. .. .. .. .. 1620
+.. .. .. .. .. .. .. 1618
+.. .. .. .. .. .. .. .. .. 1616
+.. .. .. .. .. .. .. .. 1614
+.. .. .. .. .. 1612
+.. .. .. .. .. .. .. .. .. 1610
+.. .. .. .. .. .. .. .. 1608
+.. .. .. .. .. .. .. 1606
+.. .. .. .. .. .. .. .. .. 1604
+.. .. .. .. .. .. .. .. 1602
+.. .. .. .. .. .. .. .. .. 1600
+.. .. .. .. .. .. 1598
+.. .. .. .. .. .. .. .. 1596
+.. .. .. .. .. .. .. .. .. 1594
+.. .. .. .. .. .. .. 1592
+.. .. .. .. .. .. .. .. 1590
+.. .. .. .. 1588
+.. .. .. .. .. .. .. .. 1586
+.. .. .. .. .. .. .. 1584
+.. .. .. .. .. .. .. .. .. 1582
+.. .. .. .. .. .. .. .. 1580
+.. .. .. .. .. .. 1578
+.. .. .. .. .. .. .. .. 1576
+.. .. .. .. .. .. .. 1574
+.. .. .. .. .. .. .. .. 1572
+.. .. .. .. .. .. .. .. .. 1570
+.. .. .. .. .. 1568
+.. .. .. .. .. .. .. .. 1566
+.. .. .. .. .. .. .. 1564
+.. .. .. .. .. .. .. .. .. 1562
+.. .. .. .. .. .. .. .. 1560
+.. .. .. .. .. .. .. .. .. 1558
+.. .. .. .. .. .. 1556
+.. .. .. .. .. .. .. .. 1554
+.. .. .. .. .. .. .. 1552
+.. .. .. .. .. .. .. .. 1550
+.. 1548
+.. .. .. .. .. .. .. .. 1546
+.. .. .. .. .. .. .. 1544
+.. .. .. .. .. .. .. .. 1542
+.. .. .. .. .. .. 1540
+.. .. .. .. .. .. .. .. .. 1538
+.. .. .. .. .. .. .. .. 1536
+.. .. .. .. .. .. .. 1534
+.. .. .. .. .. .. .. .. 1532
+.. .. .. .. .. 1530
+.. .. .. .. .. .. .. .. .. 1528
+.. .. .. .. .. .. .. .. 1526
+.. .. .. .. .. .. .. 1524
+.. .. .. .. .. .. .. .. 1522
+.. .. .. .. .. .. .. .. .. 1520
+.. .. .. .. .. .. 1518
+.. .. .. .. .. .. .. .. 1516
+.. .. .. .. .. .. .. 1514
+.. .. .. .. .. .. .. .. .. 1512
+.. .. .. .. .. .. .. .. 1510
+.. .. .. .. 1508
+.. .. .. .. .. .. .. .. 1506
+.. .. .. .. .. .. .. 1504
+.. .. .. .. .. .. .. .. 1502
+.. .. .. .. .. .. 1500
+.. .. .. .. .. .. .. 1498
+.. .. .. .. .. .. .. .. 1496
+.. .. .. .. .. 1494
+.. .. .. .. .. .. .. 1492
+.. .. .. .. .. .. .. .. 1490
+.. .. .. .. .. .. 1488
+.. .. .. .. .. .. .. .. .. 1486
+.. .. .. .. .. .. .. .. 1484
+.. .. .. .. .. .. .. .. .. 1482
+.. .. .. .. .. .. .. 1480
+.. .. .. .. .. .. .. .. .. 1478
+.. .. .. .. .. .. .. .. 1476
+.. .. .. .. .. .. .. .. .. 1474
+.. .. .. 1472
+.. .. .. .. .. .. .. .. .. .. 1470
+.. .. .. .. .. .. .. .. .. 1468
+.. .. .. .. .. .. .. .. .. .. 1466
+.. .. .. .. .. .. .. .. 1464
+.. .. .. .. .. .. .. .. .. 1462
+.. .. .. .. .. .. .. 1460
+.. .. .. .. .. .. .. .. .. .. 1458
+.. .. .. .. .. .. .. .. .. 1456
+.. .. .. .. .. .. .. .. .. .. 1454
+.. .. .. .. .. .. .. .. 1452
+.. .. .. .. .. .. .. .. .. 1450
+.. .. .. .. .. .. .. .. .. .. 1448
+.. .. .. .. .. .. 1446
+.. .. .. .. .. .. .. .. .. 1444
+.. .. .. .. .. .. .. .. 1442
+.. .. .. .. .. .. .. .. .. 1440
+.. .. .. .. .. .. .. 1438
+.. .. .. .. .. .. .. .. 1436
+.. .. .. .. .. 1434
+.. .. .. .. .. .. .. .. .. 1432
+.. .. .. .. .. .. .. .. 1430
+.. .. .. .. .. .. .. .. .. 1428
+.. .. .. .. .. .. .. 1426
+.. .. .. .. .. .. .. .. .. .. 1424
+.. .. .. .. .. .. .. .. .. 1422
+.. .. .. .. .. .. .. .. .. .. 1420
+.. .. .. .. .. .. .. .. 1418
+.. .. .. .. .. .. .. .. .. .. 1416
+.. .. .. .. .. .. .. .. .. 1414
+.. .. .. .. .. .. 1412
+.. .. .. .. .. .. .. .. .. 1410
+.. .. .. .. .. .. .. .. 1408
+.. .. .. .. .. .. .. .. .. 1406
+.. .. .. .. .. .. .. .. .. .. 1404
+.. .. .. .. .. .. .. 1402
+.. .. .. .. .. .. .. .. .. .. 1400
+.. .. .. .. .. .. .. .. .. 1398
+.. .. .. .. .. .. .. .. .. .. 1396
+.. .. .. .. .. .. .. .. 1394
+.. .. .. .. .. .. .. .. .. .. 1392
+.. .. .. .. .. .. .. .. .. 1390
+.. .. .. .. 1388
+.. .. .. .. .. .. .. .. .. .. 1386
+.. .. .. .. .. .. .. .. .. 1384
+.. .. .. .. .. .. .. .. 1382
+.. .. .. .. .. .. .. .. .. .. 1380
+.. .. .. .. .. .. .. .. .. 1378
+.. .. .. .. .. .. .. .. .. .. 1376
+.. .. .. .. .. .. .. 1374
+.. .. .. .. .. .. .. .. 1372
+.. .. .. .. .. .. .. .. .. 1370
+.. .. .. .. .. .. 1368
+.. .. .. .. .. .. .. .. .. .. 1366
+.. .. .. .. .. .. .. .. .. 1364
+.. .. .. .. .. .. .. .. .. .. 1362
+.. .. .. .. .. .. .. .. 1360
+.. .. .. .. .. .. .. .. .. 1358
+.. .. .. .. .. .. .. 1356
+.. .. .. .. .. .. .. .. .. 1354
+.. .. .. .. .. .. .. .. .. .. 1352
+.. .. .. .. .. .. .. .. 1350
+.. .. .. .. .. .. .. .. .. .. 1348
+.. .. .. .. .. .. .. .. .. 1346
+.. .. .. .. .. .. .. .. .. .. 1344
+.. .. .. .. .. 1342
+.. .. .. .. .. .. .. .. .. .. 1340
+.. .. .. .. .. .. .. .. .. 1338
+.. .. .. .. .. .. .. .. 1336
+.. .. .. .. .. .. .. .. .. .. 1334
+.. .. .. .. .. .. .. .. .. 1332
+.. .. .. .. .. .. .. .. .. .. 1330
+.. .. .. .. .. .. .. 1328
+.. .. .. .. .. .. .. .. .. .. 1326
+.. .. .. .. .. .. .. .. .. 1324
+.. .. .. .. .. .. .. .. .. .. 1322
+.. .. .. .. .. .. .. .. 1320
+.. .. .. .. .. .. .. .. .. 1318
+.. .. .. .. .. .. .. .. .. .. 1316
+.. .. .. .. .. .. 1314
+.. .. .. .. .. .. .. .. 1312
+.. .. .. .. .. .. .. .. .. 1310
+.. .. .. .. .. .. .. 1308
+.. .. .. .. .. .. .. .. .. .. 1306
+.. .. .. .. .. .. .. .. .. 1304
+.. .. .. .. .. .. .. .. .. .. 1302
+.. .. .. .. .. .. .. .. 1300
+.. .. .. .. .. .. .. .. .. 1298
+.. .. .. .. .. .. .. .. .. .. 1296
+.. .. 1294
+.. .. .. .. .. .. .. .. .. 1292
+.. .. .. .. .. .. .. .. 1290
+.. .. .. .. .. .. .. 1288
+.. .. .. .. .. .. .. .. .. 1286
+.. .. .. .. .. .. .. .. 1284
+.. .. .. .. .. .. .. .. .. 1282
+.. .. .. .. .. .. 1280
+.. .. .. .. .. .. .. .. 1278
+.. .. .. .. .. .. .. 1276
+.. .. .. .. .. 1274
+.. .. .. .. .. .. .. .. 1272
+.. .. .. .. .. .. .. .. .. 1270
+.. .. .. .. .. .. .. 1268
+.. .. .. .. .. .. .. .. .. 1266
+.. .. .. .. .. .. .. .. 1264
+.. .. .. .. .. .. .. .. .. 1262
+.. .. .. .. .. .. 1260
+.. .. .. .. .. .. .. .. .. 1258
+.. .. .. .. .. .. .. .. 1256
+.. .. .. .. .. .. .. 1254
+.. .. .. .. .. .. .. .. .. .. 1252
+.. .. .. .. .. .. .. .. .. 1250
+.. .. .. .. .. .. .. .. 1248
+.. .. .. .. .. .. .. .. .. 1246
+.. .. .. .. .. .. .. .. .. .. 1244
+.. .. .. .. 1242
+.. .. .. .. .. .. .. .. .. 1240
+.. .. .. .. .. .. .. .. 1238
+.. .. .. .. .. .. .. .. .. 1236
+.. .. .. .. .. .. .. 1234
+.. .. .. .. .. .. .. .. 1232
+.. .. .. .. .. .. 1230
+.. .. .. .. .. .. .. .. .. 1228
+.. .. .. .. .. .. .. .. 1226
+.. .. .. .. .. .. .. 1224
+.. .. .. .. .. .. .. .. .. 1222
+.. .. .. .. .. .. .. .. 1220
+.. .. .. .. .. .. .. .. .. 1218
+.. .. .. .. .. 1216
+.. .. .. .. .. .. .. .. .. 1214
+.. .. .. .. .. .. .. .. 1212
+.. .. .. .. .. .. .. .. .. 1210
+.. .. .. .. .. .. .. 1208
+.. .. .. .. .. .. .. .. 1206
+.. .. .. .. .. .. 1204
+.. .. .. .. .. .. .. .. .. 1202
+.. .. .. .. .. .. .. .. .. .. 1200
+.. .. .. .. .. .. .. .. 1198
+.. .. .. .. .. .. .. .. .. 1196
+.. .. .. .. .. .. .. 1194
+.. .. .. .. .. .. .. .. .. 1192
+.. .. .. .. .. .. .. .. 1190
+.. .. .. .. .. .. .. .. .. 1188
+.. .. .. 1186
+.. .. .. .. .. .. .. .. .. 1184
+.. .. .. .. .. .. .. .. .. .. 1182
+.. .. .. .. .. .. .. .. 1180
+.. .. .. .. .. .. .. .. .. 1178
+.. .. .. .. .. .. .. 1176
+.. .. .. .. .. .. .. .. .. 1174
+.. .. .. .. .. .. .. .. .. .. 1172
+.. .. .. .. .. .. .. .. 1170
+.. .. .. .. .. .. .. .. .. 1168
+.. .. .. .. .. .. 1166
+.. .. .. .. .. .. .. .. .. .. 1164
+.. .. .. .. .. .. .. .. .. 1162
+.. .. .. .. .. .. .. .. 1160
+.. .. .. .. .. .. .. .. .. 1158
+.. .. .. .. .. .. .. .. .. .. 1156
+.. .. .. .. .. .. .. 1152
+.. .. .. .. .. .. .. .. .. 1150
+.. .. .. .. .. .. .. .. .. .. 1148
+.. .. .. .. .. .. .. .. 1146
+.. .. .. .. .. .. .. .. .. 1144
+.. .. .. .. .. 1142
+.. .. .. .. .. .. .. .. .. 1140
+.. .. .. .. .. .. .. .. 1138
+.. .. .. .. .. .. .. .. .. 1136
+.. .. .. .. .. .. .. 1134
+.. .. .. .. .. .. .. .. .. 1132
+.. .. .. .. .. .. .. .. 1130
+.. .. .. .. .. .. .. .. .. 1128
+.. .. .. .. .. .. .. .. .. .. 1126
+.. .. .. .. .. .. 1124
+.. .. .. .. .. .. .. .. .. 1122
+.. .. .. .. .. .. .. .. 1120
+.. .. .. .. .. .. .. .. .. 1118
+.. .. .. .. .. .. .. .. .. .. 1116
+.. .. .. .. .. .. .. 1114
+.. .. .. .. .. .. .. .. 1112
+.. .. .. .. .. .. .. .. .. 1110
+.. .. .. .. 1108
+.. .. .. .. .. .. .. .. .. 1106
+.. .. .. .. .. .. .. .. 1104
+.. .. .. .. .. .. .. .. .. 1102
+.. .. .. .. .. .. .. 1100
+.. .. .. .. .. .. .. .. .. 1098
+.. .. .. .. .. .. .. .. .. .. 1096
+.. .. .. .. .. .. .. .. 1094
+.. .. .. .. .. .. .. .. .. 1092
+.. .. .. .. .. .. 1090
+.. .. .. .. .. .. .. .. 1088
+.. .. .. .. .. .. .. .. .. 1086
+.. .. .. .. .. .. .. 1084
+.. .. .. .. .. .. .. .. 1082
+.. .. .. .. .. .. .. .. .. 1080
+.. .. .. .. .. 1078
+.. .. .. .. .. .. .. .. 1076
+.. .. .. .. .. .. .. 1074
+.. .. .. .. .. .. .. .. 1072
+.. .. .. .. .. .. .. .. .. 1070
+.. .. .. .. .. .. 1068
+.. .. .. .. .. .. .. 1066
+.. .. .. .. .. .. .. .. 1064
+1062
+.. .. .. .. .. .. .. .. .. 1060
+.. .. .. .. .. .. .. .. 1058
+.. .. .. .. .. .. .. .. .. 1056
+.. .. .. .. .. .. .. 1054
+.. .. .. .. .. .. .. .. .. 1052
+.. .. .. .. .. .. .. .. 1050
+.. .. .. .. .. .. .. .. .. .. 1048
+.. .. .. .. .. .. .. .. .. 1046
+.. .. .. .. .. .. 1044
+.. .. .. .. .. .. .. .. .. .. 1042
+.. .. .. .. .. .. .. .. .. .. .. 1040
+.. .. .. .. .. .. .. .. .. 1038
+.. .. .. .. .. .. .. .. .. .. .. 1036
+.. .. .. .. .. .. .. .. .. .. 1034
+.. .. .. .. .. .. .. .. .. .. .. 1032
+.. .. .. .. .. .. .. .. 1030
+.. .. .. .. .. .. .. .. .. .. 1028
+.. .. .. .. .. .. .. .. .. 1026
+.. .. .. .. .. .. .. .. .. .. 1024
+.. .. .. .. .. .. .. 1022
+.. .. .. .. .. .. .. .. .. .. 1020
+.. .. .. .. .. .. .. .. .. 1018
+.. .. .. .. .. .. .. .. .. .. 1016
+.. .. .. .. .. .. .. .. 1014
+.. .. .. .. .. .. .. .. .. .. 1012
+.. .. .. .. .. .. .. .. .. 1010
+.. .. .. .. .. .. .. .. .. .. 1008
+.. .. .. .. .. 1006
+.. .. .. .. .. .. .. .. .. 1004
+.. .. .. .. .. .. .. .. 1002
+.. .. .. .. .. .. .. .. .. 1000
+.. .. .. .. .. .. .. 998
+.. .. .. .. .. .. .. .. .. .. 996
+.. .. .. .. .. .. .. .. .. 994
+.. .. .. .. .. .. .. .. .. .. 992
+.. .. .. .. .. .. .. .. 990
+.. .. .. .. .. .. .. .. .. 988
+.. .. .. .. .. .. 986
+.. .. .. .. .. .. .. .. .. .. 984
+.. .. .. .. .. .. .. .. .. 982
+.. .. .. .. .. .. .. .. .. .. 980
+.. .. .. .. .. .. .. .. 978
+.. .. .. .. .. .. .. .. .. 976
+.. .. .. .. .. .. .. .. .. .. 974
+.. .. .. .. .. .. .. 972
+.. .. .. .. .. .. .. .. .. 970
+.. .. .. .. .. .. .. .. 968
+.. .. .. .. .. .. .. .. .. 966
+.. .. .. .. 964
+.. .. .. .. .. .. .. .. .. 962
+.. .. .. .. .. .. .. .. .. .. 960
+.. .. .. .. .. .. .. .. 958
+.. .. .. .. .. .. .. .. .. 956
+.. .. .. .. .. .. .. 954
+.. .. .. .. .. .. .. .. 952
+.. .. .. .. .. .. .. .. .. 950
+.. .. .. .. .. .. 948
+.. .. .. .. .. .. .. .. .. 946
+.. .. .. .. .. .. .. .. .. .. 944
+.. .. .. .. .. .. .. .. 942
+.. .. .. .. .. .. .. .. .. 940
+.. .. .. .. .. .. .. 938
+.. .. .. .. .. .. .. .. .. .. 936
+.. .. .. .. .. .. .. .. .. 934
+.. .. .. .. .. .. .. .. 932
+.. .. .. .. .. .. .. .. .. .. 930
+.. .. .. .. .. .. .. .. .. 928
+.. .. .. .. .. .. .. .. .. .. 926
+.. .. .. .. .. 924
+.. .. .. .. .. .. .. .. .. 922
+.. .. .. .. .. .. .. .. 920
+.. .. .. .. .. .. .. .. .. .. 918
+.. .. .. .. .. .. .. .. .. 916
+.. .. .. .. .. .. .. 914
+.. .. .. .. .. .. .. .. .. 912
+.. .. .. .. .. .. .. .. 910
+.. .. .. .. .. .. 908
+.. .. .. .. .. .. .. .. 906
+.. .. .. .. .. .. .. 904
+.. .. .. .. .. .. .. .. .. 900
+.. .. .. .. .. .. .. .. 898
+.. .. .. 896
+.. .. .. .. .. .. .. .. .. 894
+.. .. .. .. .. .. .. .. 892
+.. .. .. .. .. .. .. .. .. 890
+.. .. .. .. .. .. .. .. .. .. 888
+.. .. .. .. .. .. .. 886
+.. .. .. .. .. .. .. .. .. .. 884
+.. .. .. .. .. .. .. .. .. 882
+.. .. .. .. .. .. .. .. .. .. .. 880
+.. .. .. .. .. .. .. .. .. .. 878
+.. .. .. .. .. .. .. .. 876
+.. .. .. .. .. .. .. .. .. .. 874
+.. .. .. .. .. .. .. .. .. 872
+.. .. .. .. .. .. .. .. .. .. 870
+.. .. .. .. .. .. 868
+.. .. .. .. .. .. .. .. .. .. 866
+.. .. .. .. .. .. .. .. .. 864
+.. .. .. .. .. .. .. .. 862
+.. .. .. .. .. .. .. .. .. 860
+.. .. .. .. .. .. .. .. .. .. 858
+.. .. .. .. .. .. .. 856
+.. .. .. .. .. .. .. .. .. 854
+.. .. .. .. .. .. .. .. 852
+.. .. .. .. .. .. .. .. .. 850
+.. .. .. .. .. .. .. .. .. .. 848
+.. .. .. .. .. 846
+.. .. .. .. .. .. .. .. .. .. 844
+.. .. .. .. .. .. .. .. .. 842
+.. .. .. .. .. .. .. .. 840
+.. .. .. .. .. .. .. .. .. 838
+.. .. .. .. .. .. .. 836
+.. .. .. .. .. .. .. .. .. 834
+.. .. .. .. .. .. .. .. .. .. 832
+.. .. .. .. .. .. .. .. 830
+.. .. .. .. .. .. .. .. .. 828
+.. .. .. .. .. .. 826
+.. .. .. .. .. .. .. .. .. 824
+.. .. .. .. .. .. .. .. 822
+.. .. .. .. .. .. .. 820
+.. .. .. .. .. .. .. .. .. .. 818
+.. .. .. .. .. .. .. .. .. 816
+.. .. .. .. .. .. .. .. 814
+.. .. .. .. .. .. .. .. .. .. 812
+.. .. .. .. .. .. .. .. .. 810
+.. .. .. .. 808
+.. .. .. .. .. .. .. .. .. 806
+.. .. .. .. .. .. .. .. 804
+.. .. .. .. .. .. .. 802
+.. .. .. .. .. .. .. .. .. 800
+.. .. .. .. .. .. .. .. 798
+.. .. .. .. .. .. .. .. .. 796
+.. .. .. .. .. .. 794
+.. .. .. .. .. .. .. .. .. 792
+.. .. .. .. .. .. .. .. 790
+.. .. .. .. .. .. .. .. .. 788
+.. .. .. .. .. .. .. 786
+.. .. .. .. .. .. .. .. 784
+.. .. .. .. .. .. .. .. .. 782
+.. .. .. .. .. 780
+.. .. .. .. .. .. .. .. .. .. 778
+.. .. .. .. .. .. .. .. .. 776
+.. .. .. .. .. .. .. .. .. .. 774
+.. .. .. .. .. .. .. .. 772
+.. .. .. .. .. .. .. .. .. 770
+.. .. .. .. .. .. .. 768
+.. .. .. .. .. .. .. .. .. .. 766
+.. .. .. .. .. .. .. .. .. 764
+.. .. .. .. .. .. .. .. 762
+.. .. .. .. .. .. .. .. .. .. 760
+.. .. .. .. .. .. .. .. .. 758
+.. .. .. .. .. .. .. .. .. .. 756
+.. .. .. .. .. .. 754
+.. .. .. .. .. .. .. .. .. .. 752
+.. .. .. .. .. .. .. .. .. 750
+.. .. .. .. .. .. .. .. .. .. 748
+.. .. .. .. .. .. .. .. 746
+.. .. .. .. .. .. .. .. .. .. 744
+.. .. .. .. .. .. .. .. .. 742
+.. .. .. .. .. .. .. .. .. .. 740
+.. .. .. .. .. .. .. 738
+.. .. .. .. .. .. .. .. .. 736
+.. .. .. .. .. .. .. .. 734
+.. .. .. .. .. .. .. .. .. 732
+.. .. .. .. .. .. .. .. .. .. 730
+.. .. 728
+.. .. .. .. .. .. .. .. 726
+.. .. .. .. .. .. .. .. .. 724
+.. .. .. .. .. .. .. 722
+.. .. .. .. .. .. .. .. .. 720
+.. .. .. .. .. .. .. .. .. .. 718
+.. .. .. .. .. .. .. .. 716
+.. .. .. .. .. .. .. .. .. 714
+.. .. .. .. .. .. 712
+.. .. .. .. .. .. .. .. .. 710
+.. .. .. .. .. .. .. .. 708
+.. .. .. .. .. .. .. 706
+.. .. .. .. .. .. .. .. .. 704
+.. .. .. .. .. .. .. .. 702
+.. .. .. .. .. .. .. .. .. 700
+.. .. .. .. .. 698
+.. .. .. .. .. .. .. .. 696
+.. .. .. .. .. .. .. 694
+.. .. .. .. .. .. .. .. 692
+.. .. .. .. .. .. .. .. .. 690
+.. .. .. .. .. .. 688
+.. .. .. .. .. .. .. 686
+.. .. .. .. .. .. .. .. 684
+.. .. .. .. 682
+.. .. .. .. .. .. .. .. 680
+.. .. .. .. .. .. .. 678
+.. .. .. .. .. .. 676
+.. .. .. .. .. .. .. .. 674
+.. .. .. .. .. .. .. 672
+.. .. .. .. .. .. .. .. 670
+.. .. .. .. .. 668
+.. .. .. .. .. .. .. .. .. 666
+.. .. .. .. .. .. .. .. 664
+.. .. .. .. .. .. .. .. .. 662
+.. .. .. .. .. .. .. 660
+.. .. .. .. .. .. .. .. 658
+.. .. .. .. .. .. 656
+.. .. .. .. .. .. .. .. .. 654
+.. .. .. .. .. .. .. .. 652
+.. .. .. .. .. .. .. .. .. 650
+.. .. .. .. .. .. .. 648
+.. .. .. .. .. .. .. .. 646
+.. .. .. .. .. .. .. .. .. 644
+.. .. .. 642
+.. .. .. .. .. .. .. .. .. 640
+.. .. .. .. .. .. .. .. 638
+.. .. .. .. .. .. .. 636
+.. .. .. .. .. .. .. .. .. 634
+.. .. .. .. .. .. .. .. 632
+.. .. .. .. .. .. .. .. .. 630
+.. .. .. .. .. .. 628
+.. .. .. .. .. .. .. .. .. 626
+.. .. .. .. .. .. .. .. 624
+.. .. .. .. .. .. .. .. .. 622
+.. .. .. .. .. .. .. 620
+.. .. .. .. .. .. .. .. .. 618
+.. .. .. .. .. .. .. .. 616
+.. .. .. .. .. 614
+.. .. .. .. .. .. .. .. .. 612
+.. .. .. .. .. .. .. .. 610
+.. .. .. .. .. .. .. .. .. .. 608
+.. .. .. .. .. .. .. .. .. 606
+.. .. .. .. .. .. .. .. .. .. 604
+.. .. .. .. .. .. .. 602
+.. .. .. .. .. .. .. .. .. 600
+.. .. .. .. .. .. .. .. 598
+.. .. .. .. .. .. 596
+.. .. .. .. .. .. .. .. .. 594
+.. .. .. .. .. .. .. .. 592
+.. .. .. .. .. .. .. .. .. 590
+.. .. .. .. .. .. .. 588
+.. .. .. .. .. .. .. .. .. .. 586
+.. .. .. .. .. .. .. .. .. 584
+.. .. .. .. .. .. .. .. 582
+.. .. .. .. .. .. .. .. .. 580
+.. .. .. .. 578
+.. .. .. .. .. .. .. .. .. 576
+.. .. .. .. .. .. .. .. 574
+.. .. .. .. .. .. .. .. .. 572
+.. .. .. .. .. .. .. 570
+.. .. .. .. .. .. .. .. .. .. 568
+.. .. .. .. .. .. .. .. .. 566
+.. .. .. .. .. .. .. .. .. .. 564
+.. .. .. .. .. .. .. .. 562
+.. .. .. .. .. .. .. .. .. 560
+.. .. .. .. .. .. .. .. .. .. 558
+.. .. .. .. .. .. 556
+.. .. .. .. .. .. .. .. .. 554
+.. .. .. .. .. .. .. .. 552
+.. .. .. .. .. .. .. 550
+.. .. .. .. .. .. .. .. .. 548
+.. .. .. .. .. .. .. .. 546
+.. .. .. .. .. 544
+.. .. .. .. .. .. .. .. 542
+.. .. .. .. .. .. .. .. .. 540
+.. .. .. .. .. .. .. 538
+.. .. .. .. .. .. .. .. .. 536
+.. .. .. .. .. .. .. .. 534
+.. .. .. .. .. .. .. .. .. 532
+.. .. .. .. .. .. 530
+.. .. .. .. .. .. .. .. 528
+.. .. .. .. .. .. .. 526
+.. .. .. .. .. .. .. .. 524
+.. 522
+.. .. .. .. .. .. .. .. .. .. 520
+.. .. .. .. .. .. .. .. .. 518
+.. .. .. .. .. .. .. .. 516
+.. .. .. .. .. .. .. .. .. 514
+.. .. .. .. .. .. .. .. .. .. 512
+.. .. .. .. .. .. .. 510
+.. .. .. .. .. .. .. .. .. 508
+.. .. .. .. .. .. .. .. 506
+.. .. .. .. .. .. .. .. .. 504
+.. .. .. .. .. .. 502
+.. .. .. .. .. .. .. .. .. .. 500
+.. .. .. .. .. .. .. .. .. 498
+.. .. .. .. .. .. .. .. 496
+.. .. .. .. .. .. .. .. .. 494
+.. .. .. .. .. .. .. 492
+.. .. .. .. .. .. .. .. .. .. 490
+.. .. .. .. .. .. .. .. .. 488
+.. .. .. .. .. .. .. .. 486
+.. .. .. .. .. .. .. .. .. 484
+.. .. .. .. .. 482
+.. .. .. .. .. .. .. .. .. 480
+.. .. .. .. .. .. .. .. 478
+.. .. .. .. .. .. .. .. .. 476
+.. .. .. .. .. .. .. 474
+.. .. .. .. .. .. .. .. 472
+.. .. .. .. .. .. 470
+.. .. .. .. .. .. .. .. 468
+.. .. .. .. .. .. .. 466
+.. .. .. .. .. .. .. .. 464
+.. .. .. .. 462
+.. .. .. .. .. .. .. .. .. .. 460
+.. .. .. .. .. .. .. .. .. 458
+.. .. .. .. .. .. .. .. .. .. 456
+.. .. .. .. .. .. .. .. 454
+.. .. .. .. .. .. .. .. .. .. 452
+.. .. .. .. .. .. .. .. .. 450
+.. .. .. .. .. .. .. .. .. .. 448
+.. .. .. .. .. .. .. 446
+.. .. .. .. .. .. .. .. 444
+.. .. .. .. .. .. .. .. .. 442
+.. .. .. .. .. .. 440
+.. .. .. .. .. .. .. .. .. .. 438
+.. .. .. .. .. .. .. .. .. 436
+.. .. .. .. .. .. .. .. .. .. 434
+.. .. .. .. .. .. .. .. 432
+.. .. .. .. .. .. .. .. .. 430
+.. .. .. .. .. .. .. 428
+.. .. .. .. .. .. .. .. 426
+.. .. .. .. .. .. .. .. .. 424
+.. .. .. .. .. 422
+.. .. .. .. .. .. .. .. .. 420
+.. .. .. .. .. .. .. .. .. .. 418
+.. .. .. .. .. .. .. .. 416
+.. .. .. .. .. .. .. .. .. .. 414
+.. .. .. .. .. .. .. .. .. 412
+.. .. .. .. .. .. .. 410
+.. .. .. .. .. .. .. .. .. 408
+.. .. .. .. .. .. .. .. .. .. 406
+.. .. .. .. .. .. .. .. 404
+.. .. .. .. .. .. .. .. .. 402
+.. .. .. .. .. .. .. .. .. .. 400
+.. .. .. .. .. .. 398
+.. .. .. .. .. .. .. .. .. 396
+.. .. .. .. .. .. .. .. 394
+.. .. .. .. .. .. .. .. .. 392
+.. .. .. .. .. .. .. .. .. .. 390
+.. .. .. .. .. .. .. 388
+.. .. .. .. .. .. .. .. .. .. 386
+.. .. .. .. .. .. .. .. .. 384
+.. .. .. .. .. .. .. .. 382
+.. .. .. .. .. .. .. .. .. .. 380
+.. .. .. .. .. .. .. .. .. 378
+.. .. .. .. .. .. .. .. .. .. 376
+.. .. .. 374
+.. .. .. .. .. .. .. .. 372
+.. .. .. .. .. .. .. 370
+.. .. .. .. .. .. 368
+.. .. .. .. .. .. .. .. 366
+.. .. .. .. .. .. .. .. .. 364
+.. .. .. .. .. .. .. 362
+.. .. .. .. .. .. .. .. 360
+.. .. .. .. .. 358
+.. .. .. .. .. .. .. .. 356
+.. .. .. .. .. .. .. .. .. 354
+.. .. .. .. .. .. .. 352
+.. .. .. .. .. .. .. .. .. 350
+.. .. .. .. .. .. .. .. 348
+.. .. .. .. .. .. .. .. .. 346
+.. .. .. .. .. .. 344
+.. .. .. .. .. .. .. .. .. 342
+.. .. .. .. .. .. .. .. 340
+.. .. .. .. .. .. .. .. .. 338
+.. .. .. .. .. .. .. 336
+.. .. .. .. .. .. .. .. .. 334
+.. .. .. .. .. .. .. .. 332
+.. .. .. .. .. .. .. .. .. 330
+.. .. .. .. 328
+.. .. .. .. .. .. .. .. .. 326
+.. .. .. .. .. .. .. .. 324
+.. .. .. .. .. .. .. 322
+.. .. .. .. .. .. .. .. 320
+.. .. .. .. .. .. 318
+.. .. .. .. .. .. .. .. .. 316
+.. .. .. .. .. .. .. .. 314
+.. .. .. .. .. .. .. .. .. .. 312
+.. .. .. .. .. .. .. .. .. 310
+.. .. .. .. .. .. .. .. .. .. 308
+.. .. .. .. .. .. .. 306
+.. .. .. .. .. .. .. .. .. .. 304
+.. .. .. .. .. .. .. .. .. 302
+.. .. .. .. .. .. .. .. 300
+.. .. .. .. .. .. .. .. .. 298
+.. .. .. .. .. 296
+.. .. .. .. .. .. .. .. .. 294
+.. .. .. .. .. .. .. .. 292
+.. .. .. .. .. .. .. .. .. 290
+.. .. .. .. .. .. .. 288
+.. .. .. .. .. .. .. .. 286
+.. .. .. .. .. .. 284
+.. .. .. .. .. .. .. .. .. 282
+.. .. .. .. .. .. .. .. 280
+.. .. .. .. .. .. .. .. .. 278
+.. .. .. .. .. .. .. 276
+.. .. .. .. .. .. .. .. .. .. 274
+.. .. .. .. .. .. .. .. .. 272
+.. .. .. .. .. .. .. .. 270
+.. .. .. .. .. .. .. .. .. 268
+.. .. 266
+.. .. .. .. .. .. .. .. .. 264
+.. .. .. .. .. .. .. .. 262
+.. .. .. .. .. .. .. .. .. 260
+.. .. .. .. .. .. .. 258
+.. .. .. .. .. .. .. .. .. 256
+.. .. .. .. .. .. .. .. 254
+.. .. .. .. .. .. .. .. .. 252
+.. .. .. .. .. .. 250
+.. .. .. .. .. .. .. .. .. 248
+.. .. .. .. .. .. .. .. 246
+.. .. .. .. .. .. .. .. .. 244
+.. .. .. .. .. .. .. 242
+.. .. .. .. .. .. .. .. 240
+.. .. .. .. .. 238
+.. .. .. .. .. .. .. .. .. 236
+.. .. .. .. .. .. .. .. 234
+.. .. .. .. .. .. .. .. .. 232
+.. .. .. .. .. .. .. 230
+.. .. .. .. .. .. .. .. 228
+.. .. .. .. .. .. 226
+.. .. .. .. .. .. .. .. .. .. 224
+.. .. .. .. .. .. .. .. .. 222
+.. .. .. .. .. .. .. .. 220
+.. .. .. .. .. .. .. .. .. .. 218
+.. .. .. .. .. .. .. .. .. 216
+.. .. .. .. .. .. .. 214
+.. .. .. .. .. .. .. .. .. 212
+.. .. .. .. .. .. .. .. 210
+.. .. .. .. 208
+.. .. .. .. .. .. .. .. .. .. 206
+.. .. .. .. .. .. .. .. .. 204
+.. .. .. .. .. .. .. .. .. .. 202
+.. .. .. .. .. .. .. .. 200
+.. .. .. .. .. .. .. .. .. .. 198
+.. .. .. .. .. .. .. .. .. 196
+.. .. .. .. .. .. .. 194
+.. .. .. .. .. .. .. .. .. 192
+.. .. .. .. .. .. .. .. .. .. 190
+.. .. .. .. .. .. .. .. 188
+.. .. .. .. .. .. .. .. .. 186
+.. .. .. .. .. .. 184
+.. .. .. .. .. .. .. .. .. 182
+.. .. .. .. .. .. .. .. 180
+.. .. .. .. .. .. .. .. .. 178
+.. .. .. .. .. .. .. 176
+.. .. .. .. .. .. .. .. .. .. 174
+.. .. .. .. .. .. .. .. .. 172
+.. .. .. .. .. .. .. .. 170
+.. .. .. .. .. .. .. .. .. .. 168
+.. .. .. .. .. .. .. .. .. 166
+.. .. .. .. .. .. .. .. .. .. 164
+.. .. .. .. .. 162
+.. .. .. .. .. .. .. .. .. 160
+.. .. .. .. .. .. .. .. 158
+.. .. .. .. .. .. .. .. .. 156
+.. .. .. .. .. .. .. 154
+.. .. .. .. .. .. .. .. 152
+.. .. .. .. .. .. .. .. .. 150
+.. .. .. .. .. .. 148
+.. .. .. .. .. .. .. .. 146
+.. .. .. .. .. .. .. .. .. 144
+.. .. .. .. .. .. .. 142
+.. .. .. .. .. .. .. .. .. 140
+.. .. .. .. .. .. .. .. 138
+.. .. .. .. .. .. .. .. .. .. 136
+.. .. .. .. .. .. .. .. .. 134
+.. .. .. 132
+.. .. .. .. .. .. .. .. 130
+.. .. .. .. .. .. .. 128
+.. .. .. .. .. .. .. .. .. 126
+.. .. .. .. .. .. .. .. 124
+.. .. .. .. .. .. 122
+.. .. .. .. .. .. .. .. .. 120
+.. .. .. .. .. .. .. .. 118
+.. .. .. .. .. .. .. 116
+.. .. .. .. .. .. .. .. .. 114
+.. .. .. .. .. .. .. .. 112
+.. .. .. .. .. .. .. .. .. 110
+.. .. .. .. .. 108
+.. .. .. .. .. .. .. .. .. 106
+.. .. .. .. .. .. .. .. 104
+.. .. .. .. .. .. .. .. .. 102
+.. .. .. .. .. .. .. 100
+.. .. .. .. .. .. .. .. .. 98
+.. .. .. .. .. .. .. .. 96
+.. .. .. .. .. .. .. .. .. 94
+.. .. .. .. .. .. .. .. .. .. 92
+.. .. .. .. .. .. 90
+.. .. .. .. .. .. .. .. .. 88
+.. .. .. .. .. .. .. .. 86
+.. .. .. .. .. .. .. .. .. 84
+.. .. .. .. .. .. .. 82
+.. .. .. .. .. .. .. .. .. 80
+.. .. .. .. .. .. .. .. 78
+.. .. .. .. 76
+.. .. .. .. .. .. .. .. .. 74
+.. .. .. .. .. .. .. .. 72
+.. .. .. .. .. .. .. .. .. 70
+.. .. .. .. .. .. .. 68
+.. .. .. .. .. .. .. .. .. .. 66
+.. .. .. .. .. .. .. .. .. 64
+.. .. .. .. .. .. .. .. .. .. 62
+.. .. .. .. .. .. .. .. 60
+.. .. .. .. .. .. .. .. .. 58
+.. .. .. .. .. .. 56
+.. .. .. .. .. .. .. .. .. 54
+.. .. .. .. .. .. .. .. 52
+.. .. .. .. .. .. .. .. .. 50
+.. .. .. .. .. .. .. 48
+.. .. .. .. .. .. .. .. .. 46
+.. .. .. .. .. .. .. .. 44
+.. .. .. .. .. .. .. .. .. 42
+.. .. .. .. .. 40
+.. .. .. .. .. .. .. .. .. .. 38
+.. .. .. .. .. .. .. .. .. 36
+.. .. .. .. .. .. .. .. 34
+.. .. .. .. .. .. .. .. .. 32
+.. .. .. .. .. .. .. 30
+.. .. .. .. .. .. .. .. .. 28
+.. .. .. .. .. .. .. .. 26
+.. .. .. .. .. .. .. .. .. 24
+.. .. .. .. .. .. .. .. .. .. 22
+.. .. .. .. .. .. 20
+.. .. .. .. .. .. .. .. .. .. 18
+.. .. .. .. .. .. .. .. .. 16
+.. .. .. .. .. .. .. .. .. .. 14
+.. .. .. .. .. .. .. .. 12
+.. .. .. .. .. .. .. .. .. 10
+.. .. .. .. .. .. .. .. .. .. 8
+.. .. .. .. .. .. .. 6
+.. .. .. .. .. .. .. .. .. 4
+.. .. .. .. .. .. .. .. 2
+.. .. .. .. .. .. .. .. .. 0
+-- end cloned oset, shared pool ----------------
-- start oset1b ----------------
.. .. .. .. .. .. .. .. .. 1998
.. .. .. .. .. .. .. .. 1996
diff --git a/main/memcheck/tests/x86-linux/Makefile.in b/main/memcheck/tests/x86-linux/Makefile.in
new file mode 100644
index 0000000..b7cf830
--- /dev/null
+++ b/main/memcheck/tests/x86-linux/Makefile.in
@@ -0,0 +1,759 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(noinst_HEADERS) \
+ $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = bug133694$(EXEEXT) int3-x86$(EXEEXT) scalar$(EXEEXT) \
+ scalar_exit_group$(EXEEXT) scalar_fork$(EXEEXT) \
+ scalar_supp$(EXEEXT) scalar_vfork$(EXEEXT)
+subdir = memcheck/tests/x86-linux
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+bug133694_SOURCES = bug133694.c
+bug133694_OBJECTS = bug133694.$(OBJEXT)
+bug133694_LDADD = $(LDADD)
+int3_x86_SOURCES = int3-x86.c
+int3_x86_OBJECTS = int3-x86.$(OBJEXT)
+int3_x86_LDADD = $(LDADD)
+scalar_SOURCES = scalar.c
+scalar_OBJECTS = scalar.$(OBJEXT)
+scalar_LDADD = $(LDADD)
+scalar_exit_group_SOURCES = scalar_exit_group.c
+scalar_exit_group_OBJECTS = scalar_exit_group.$(OBJEXT)
+scalar_exit_group_LDADD = $(LDADD)
+scalar_fork_SOURCES = scalar_fork.c
+scalar_fork_OBJECTS = scalar_fork.$(OBJEXT)
+scalar_fork_LDADD = $(LDADD)
+scalar_supp_SOURCES = scalar_supp.c
+scalar_supp_OBJECTS = scalar_supp.$(OBJEXT)
+scalar_supp_LDADD = $(LDADD)
+scalar_vfork_SOURCES = scalar_vfork.c
+scalar_vfork_OBJECTS = scalar_vfork.$(OBJEXT)
+scalar_vfork_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = bug133694.c int3-x86.c scalar.c scalar_exit_group.c \
+ scalar_fork.c scalar_supp.c scalar_vfork.c
+DIST_SOURCES = bug133694.c int3-x86.c scalar.c scalar_exit_group.c \
+ scalar_fork.c scalar_supp.c scalar_vfork.c
+HEADERS = $(noinst_HEADERS)
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+ filter_scalar_exit_group \
+ filter_stderr
+
+noinst_HEADERS = scalar.h
+EXTRA_DIST = \
+ bug133694.vgtest bug133694.stderr.exp bug133694.stdout.exp \
+ int3-x86.vgtest int3-x86.stderr.exp int3-x86.stdout.exp \
+ scalar.stderr.exp scalar.vgtest \
+ scalar_fork.stderr.exp scalar_fork.vgtest \
+ scalar_exit_group.stderr.exp \
+ scalar_exit_group.vgtest \
+ scalar_supp.stderr.exp \
+ scalar_supp.vgtest scalar_supp.supp \
+ scalar_vfork.stderr.exp scalar_vfork.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/x86-linux/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/x86-linux/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+bug133694$(EXEEXT): $(bug133694_OBJECTS) $(bug133694_DEPENDENCIES)
+ @rm -f bug133694$(EXEEXT)
+ $(LINK) $(bug133694_OBJECTS) $(bug133694_LDADD) $(LIBS)
+int3-x86$(EXEEXT): $(int3_x86_OBJECTS) $(int3_x86_DEPENDENCIES)
+ @rm -f int3-x86$(EXEEXT)
+ $(LINK) $(int3_x86_OBJECTS) $(int3_x86_LDADD) $(LIBS)
+scalar$(EXEEXT): $(scalar_OBJECTS) $(scalar_DEPENDENCIES)
+ @rm -f scalar$(EXEEXT)
+ $(LINK) $(scalar_OBJECTS) $(scalar_LDADD) $(LIBS)
+scalar_exit_group$(EXEEXT): $(scalar_exit_group_OBJECTS) $(scalar_exit_group_DEPENDENCIES)
+ @rm -f scalar_exit_group$(EXEEXT)
+ $(LINK) $(scalar_exit_group_OBJECTS) $(scalar_exit_group_LDADD) $(LIBS)
+scalar_fork$(EXEEXT): $(scalar_fork_OBJECTS) $(scalar_fork_DEPENDENCIES)
+ @rm -f scalar_fork$(EXEEXT)
+ $(LINK) $(scalar_fork_OBJECTS) $(scalar_fork_LDADD) $(LIBS)
+scalar_supp$(EXEEXT): $(scalar_supp_OBJECTS) $(scalar_supp_DEPENDENCIES)
+ @rm -f scalar_supp$(EXEEXT)
+ $(LINK) $(scalar_supp_OBJECTS) $(scalar_supp_LDADD) $(LIBS)
+scalar_vfork$(EXEEXT): $(scalar_vfork_OBJECTS) $(scalar_vfork_DEPENDENCIES)
+ @rm -f scalar_vfork$(EXEEXT)
+ $(LINK) $(scalar_vfork_OBJECTS) $(scalar_vfork_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug133694.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/int3-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar_exit_group.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar_fork.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar_supp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scalar_vfork.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS) $(HEADERS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/x86-linux/scalar.c b/main/memcheck/tests/x86-linux/scalar.c
index 2bc1fa5..55c64fa 100644
--- a/main/memcheck/tests/x86-linux/scalar.c
+++ b/main/memcheck/tests/x86-linux/scalar.c
@@ -5,7 +5,7 @@
#include <unistd.h>
#include <sched.h>
#include <signal.h>
-
+#include <linux/mman.h> // MREMAP_FIXED
// Here we are trying to trigger every syscall error (scalar errors and
// memory errors) for every syscall. We do this by passing a lot of bogus
@@ -1257,6 +1257,14 @@
GO(__NR_epoll_create1, "1s 0m");
SY(__NR_epoll_create1, x0); SUCC_OR_FAIL;
+ // __NR_process_vm_readv 347
+ GO(__NR_process_vm_readv, "6s 2m");
+ SY(__NR_process_vm_readv, x0, x0, x0+1, x0, x0+1, x0); FAIL;
+
+ // __NR_process_vm_writev 348
+ GO(__NR_process_vm_writev, "6s 2m");
+ SY(__NR_process_vm_writev, x0, x0, x0+1, x0, x0+1, x0); FAIL;
+
// no such syscall...
GO(9999, "1e");
SY(9999); FAIL;
diff --git a/main/memcheck/tests/x86-linux/scalar.stderr.exp b/main/memcheck/tests/x86-linux/scalar.stderr.exp
index 894bcb9..54616db 100644
--- a/main/memcheck/tests/x86-linux/scalar.stderr.exp
+++ b/main/memcheck/tests/x86-linux/scalar.stderr.exp
@@ -2116,7 +2116,9 @@
Syscall param rt_sigaction(act->sa_mask) points to unaddressable byte(s)
...
by 0x........: main (scalar.c:776)
- Address 0x........ is not stack'd, malloc'd or (recently) free'd
+ Address 0x........ is 16 bytes after a block of size 4 alloc'd
+ at 0x........: malloc (vg_replace_malloc.c:...)
+ by 0x........: main (scalar.c:30)
Syscall param rt_sigaction(act->sa_flags) points to unaddressable byte(s)
...
@@ -3978,6 +3980,80 @@
by 0x........: main (scalar.c:1258)
-----------------------------------------------------
+347:__NR_process_vm_readv 6s 2m
+-----------------------------------------------------
+Syscall param process_vm_readv(pid) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1262)
+
+Syscall param process_vm_readv(lvec) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1262)
+
+Syscall param process_vm_readv(liovcnt) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1262)
+
+Syscall param process_vm_readv(rvec) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1262)
+
+Syscall param process_vm_readv(riovcnt) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1262)
+
+Syscall param process_vm_readv(flags) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1262)
+
+Syscall param process_vm_readv(lvec) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:1262)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param process_vm_readv(rvec) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:1262)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+-----------------------------------------------------
+348:__NR_process_vm_writev 6s 2m
+-----------------------------------------------------
+Syscall param process_vm_writev(pid) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1266)
+
+Syscall param process_vm_writev(lvec) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1266)
+
+Syscall param process_vm_writev(liovcnt) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1266)
+
+Syscall param process_vm_writev(rvec) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1266)
+
+Syscall param process_vm_writev(riovcnt) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1266)
+
+Syscall param process_vm_writev(flags) contains uninitialised byte(s)
+ ...
+ by 0x........: main (scalar.c:1266)
+
+Syscall param process_vm_writev(lvec) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:1266)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param process_vm_writev(rvec) points to unaddressable byte(s)
+ ...
+ by 0x........: main (scalar.c:1266)
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+-----------------------------------------------------
9999: 9999 1e
-----------------------------------------------------
WARNING: unhandled syscall: 9999
@@ -3990,5 +4066,5 @@
-----------------------------------------------------
Syscall param exit(status) contains uninitialised byte(s)
...
- by 0x........: main (scalar.c:1266)
+ by 0x........: main (scalar.c:1274)
diff --git a/main/memcheck/tests/x86/Makefile.in b/main/memcheck/tests/x86/Makefile.in
new file mode 100644
index 0000000..effd1cc
--- /dev/null
+++ b/main/memcheck/tests/x86/Makefile.in
@@ -0,0 +1,857 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = bug152022$(EXEEXT) espindola2$(EXEEXT) \
+ fpeflags$(EXEEXT) fprem$(EXEEXT) fxsave$(EXEEXT) \
+ more_x86_fp$(EXEEXT) pushfpopf$(EXEEXT) pushfw_x86$(EXEEXT) \
+ pushpopmem$(EXEEXT) sse_memory$(EXEEXT) tronical$(EXEEXT) \
+ xor-undef-x86$(EXEEXT)
+subdir = memcheck/tests/x86
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+bug152022_SOURCES = bug152022.c
+bug152022_OBJECTS = bug152022.$(OBJEXT)
+bug152022_LDADD = $(LDADD)
+espindola2_SOURCES = espindola2.c
+espindola2_OBJECTS = espindola2.$(OBJEXT)
+espindola2_LDADD = $(LDADD)
+fpeflags_SOURCES = fpeflags.c
+fpeflags_OBJECTS = fpeflags-fpeflags.$(OBJEXT)
+fpeflags_LDADD = $(LDADD)
+fpeflags_LINK = $(CCLD) $(fpeflags_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+fprem_SOURCES = fprem.c
+fprem_OBJECTS = fprem.$(OBJEXT)
+fprem_LDADD = $(LDADD)
+fxsave_SOURCES = fxsave.c
+fxsave_OBJECTS = fxsave.$(OBJEXT)
+fxsave_LDADD = $(LDADD)
+more_x86_fp_SOURCES = more_x86_fp.c
+more_x86_fp_OBJECTS = more_x86_fp.$(OBJEXT)
+more_x86_fp_DEPENDENCIES =
+am_pushfpopf_OBJECTS = pushfpopf_c.$(OBJEXT) pushfpopf_s.$(OBJEXT)
+pushfpopf_OBJECTS = $(am_pushfpopf_OBJECTS)
+pushfpopf_LDADD = $(LDADD)
+pushfw_x86_SOURCES = pushfw_x86.c
+pushfw_x86_OBJECTS = pushfw_x86.$(OBJEXT)
+pushfw_x86_LDADD = $(LDADD)
+pushpopmem_SOURCES = pushpopmem.c
+pushpopmem_OBJECTS = pushpopmem-pushpopmem.$(OBJEXT)
+pushpopmem_LDADD = $(LDADD)
+pushpopmem_LINK = $(CCLD) $(pushpopmem_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+sse_memory_SOURCES = sse_memory.c
+sse_memory_OBJECTS = sse_memory.$(OBJEXT)
+sse_memory_LDADD = $(LDADD)
+am_tronical_OBJECTS = tronical.$(OBJEXT)
+tronical_OBJECTS = $(am_tronical_OBJECTS)
+tronical_LDADD = $(LDADD)
+xor_undef_x86_SOURCES = xor-undef-x86.c
+xor_undef_x86_OBJECTS = xor-undef-x86.$(OBJEXT)
+xor_undef_x86_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+CPPASCOMPILE = $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CCASFLAGS) $(CCASFLAGS)
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = bug152022.c espindola2.c fpeflags.c fprem.c fxsave.c \
+ more_x86_fp.c $(pushfpopf_SOURCES) pushfw_x86.c pushpopmem.c \
+ sse_memory.c $(tronical_SOURCES) xor-undef-x86.c
+DIST_SOURCES = bug152022.c espindola2.c fpeflags.c fprem.c fxsave.c \
+ more_x86_fp.c $(pushfpopf_SOURCES) pushfw_x86.c pushpopmem.c \
+ sse_memory.c $(tronical_SOURCES) xor-undef-x86.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr filter_pushfpopf filter_tronical
+INSN_TESTS = insn_basic insn_fpu insn_cmov insn_mmx insn_mmxext insn_sse insn_sse2
+EXTRA_DIST = \
+ bug152022.vgtest bug152022.stderr.exp bug152022.stdout.exp \
+ espindola2.vgtest espindola2.stderr.exp \
+ fpeflags.stderr.exp fpeflags.vgtest \
+ fxsave.vgtest fxsave.stdout.exp fxsave.stderr.exp \
+ $(addsuffix .stderr.exp,$(INSN_TESTS)) \
+ $(addsuffix .stdout.exp,$(INSN_TESTS)) \
+ $(addsuffix .vgtest,$(INSN_TESTS)) \
+ pushfpopf.stderr.exp pushfpopf.stdout.exp pushfpopf.vgtest \
+ pushfw_x86.vgtest pushfw_x86.stdout.exp pushfw_x86.stderr.exp \
+ pushpopmem.stderr.exp pushpopmem.stdout.exp pushpopmem.vgtest \
+ sse1_memory.stderr.exp sse1_memory.stdout.exp sse1_memory.vgtest \
+ sse2_memory.stderr.exp sse2_memory.stdout.exp sse2_memory.vgtest \
+ tronical.stderr.exp tronical.vgtest \
+ more_x86_fp.stderr.exp more_x86_fp.stdout.exp more_x86_fp.vgtest \
+ fprem.stderr.exp fprem.stdout.exp fprem.vgtest \
+ xor-undef-x86.stderr.exp xor-undef-x86.stdout.exp \
+ xor-undef-x86.vgtest
+
+
+# fpeflags must use these flags -- bug only occurred with them.
+fpeflags_CFLAGS = $(AM_CFLAGS) -march=i686
+pushfpopf_SOURCES = pushfpopf_c.c pushfpopf_s.S
+@VGCONF_OS_IS_DARWIN_FALSE@pushpopmem_CFLAGS = $(AM_CFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@pushpopmem_CFLAGS = $(AM_CFLAGS) -mdynamic-no-pic
+tronical_SOURCES = tronical.S
+more_x86_fp_LDADD = -lm
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .S .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/x86/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign memcheck/tests/x86/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+bug152022$(EXEEXT): $(bug152022_OBJECTS) $(bug152022_DEPENDENCIES)
+ @rm -f bug152022$(EXEEXT)
+ $(LINK) $(bug152022_OBJECTS) $(bug152022_LDADD) $(LIBS)
+espindola2$(EXEEXT): $(espindola2_OBJECTS) $(espindola2_DEPENDENCIES)
+ @rm -f espindola2$(EXEEXT)
+ $(LINK) $(espindola2_OBJECTS) $(espindola2_LDADD) $(LIBS)
+fpeflags$(EXEEXT): $(fpeflags_OBJECTS) $(fpeflags_DEPENDENCIES)
+ @rm -f fpeflags$(EXEEXT)
+ $(fpeflags_LINK) $(fpeflags_OBJECTS) $(fpeflags_LDADD) $(LIBS)
+fprem$(EXEEXT): $(fprem_OBJECTS) $(fprem_DEPENDENCIES)
+ @rm -f fprem$(EXEEXT)
+ $(LINK) $(fprem_OBJECTS) $(fprem_LDADD) $(LIBS)
+fxsave$(EXEEXT): $(fxsave_OBJECTS) $(fxsave_DEPENDENCIES)
+ @rm -f fxsave$(EXEEXT)
+ $(LINK) $(fxsave_OBJECTS) $(fxsave_LDADD) $(LIBS)
+more_x86_fp$(EXEEXT): $(more_x86_fp_OBJECTS) $(more_x86_fp_DEPENDENCIES)
+ @rm -f more_x86_fp$(EXEEXT)
+ $(LINK) $(more_x86_fp_OBJECTS) $(more_x86_fp_LDADD) $(LIBS)
+pushfpopf$(EXEEXT): $(pushfpopf_OBJECTS) $(pushfpopf_DEPENDENCIES)
+ @rm -f pushfpopf$(EXEEXT)
+ $(LINK) $(pushfpopf_OBJECTS) $(pushfpopf_LDADD) $(LIBS)
+pushfw_x86$(EXEEXT): $(pushfw_x86_OBJECTS) $(pushfw_x86_DEPENDENCIES)
+ @rm -f pushfw_x86$(EXEEXT)
+ $(LINK) $(pushfw_x86_OBJECTS) $(pushfw_x86_LDADD) $(LIBS)
+pushpopmem$(EXEEXT): $(pushpopmem_OBJECTS) $(pushpopmem_DEPENDENCIES)
+ @rm -f pushpopmem$(EXEEXT)
+ $(pushpopmem_LINK) $(pushpopmem_OBJECTS) $(pushpopmem_LDADD) $(LIBS)
+sse_memory$(EXEEXT): $(sse_memory_OBJECTS) $(sse_memory_DEPENDENCIES)
+ @rm -f sse_memory$(EXEEXT)
+ $(LINK) $(sse_memory_OBJECTS) $(sse_memory_LDADD) $(LIBS)
+tronical$(EXEEXT): $(tronical_OBJECTS) $(tronical_DEPENDENCIES)
+ @rm -f tronical$(EXEEXT)
+ $(LINK) $(tronical_OBJECTS) $(tronical_LDADD) $(LIBS)
+xor-undef-x86$(EXEEXT): $(xor_undef_x86_OBJECTS) $(xor_undef_x86_DEPENDENCIES)
+ @rm -f xor-undef-x86$(EXEEXT)
+ $(LINK) $(xor_undef_x86_OBJECTS) $(xor_undef_x86_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug152022.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/espindola2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fpeflags-fpeflags.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fprem.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxsave.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/more_x86_fp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pushfpopf_c.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pushfpopf_s.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pushfw_x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pushpopmem-pushpopmem.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sse_memory.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tronical.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xor-undef-x86.Po@am__quote@
+
+.S.o:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ $<
+
+.S.obj:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+fpeflags-fpeflags.o: fpeflags.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fpeflags_CFLAGS) $(CFLAGS) -MT fpeflags-fpeflags.o -MD -MP -MF $(DEPDIR)/fpeflags-fpeflags.Tpo -c -o fpeflags-fpeflags.o `test -f 'fpeflags.c' || echo '$(srcdir)/'`fpeflags.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/fpeflags-fpeflags.Tpo $(DEPDIR)/fpeflags-fpeflags.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fpeflags.c' object='fpeflags-fpeflags.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fpeflags_CFLAGS) $(CFLAGS) -c -o fpeflags-fpeflags.o `test -f 'fpeflags.c' || echo '$(srcdir)/'`fpeflags.c
+
+fpeflags-fpeflags.obj: fpeflags.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fpeflags_CFLAGS) $(CFLAGS) -MT fpeflags-fpeflags.obj -MD -MP -MF $(DEPDIR)/fpeflags-fpeflags.Tpo -c -o fpeflags-fpeflags.obj `if test -f 'fpeflags.c'; then $(CYGPATH_W) 'fpeflags.c'; else $(CYGPATH_W) '$(srcdir)/fpeflags.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/fpeflags-fpeflags.Tpo $(DEPDIR)/fpeflags-fpeflags.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fpeflags.c' object='fpeflags-fpeflags.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fpeflags_CFLAGS) $(CFLAGS) -c -o fpeflags-fpeflags.obj `if test -f 'fpeflags.c'; then $(CYGPATH_W) 'fpeflags.c'; else $(CYGPATH_W) '$(srcdir)/fpeflags.c'; fi`
+
+pushpopmem-pushpopmem.o: pushpopmem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pushpopmem_CFLAGS) $(CFLAGS) -MT pushpopmem-pushpopmem.o -MD -MP -MF $(DEPDIR)/pushpopmem-pushpopmem.Tpo -c -o pushpopmem-pushpopmem.o `test -f 'pushpopmem.c' || echo '$(srcdir)/'`pushpopmem.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/pushpopmem-pushpopmem.Tpo $(DEPDIR)/pushpopmem-pushpopmem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pushpopmem.c' object='pushpopmem-pushpopmem.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pushpopmem_CFLAGS) $(CFLAGS) -c -o pushpopmem-pushpopmem.o `test -f 'pushpopmem.c' || echo '$(srcdir)/'`pushpopmem.c
+
+pushpopmem-pushpopmem.obj: pushpopmem.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pushpopmem_CFLAGS) $(CFLAGS) -MT pushpopmem-pushpopmem.obj -MD -MP -MF $(DEPDIR)/pushpopmem-pushpopmem.Tpo -c -o pushpopmem-pushpopmem.obj `if test -f 'pushpopmem.c'; then $(CYGPATH_W) 'pushpopmem.c'; else $(CYGPATH_W) '$(srcdir)/pushpopmem.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/pushpopmem-pushpopmem.Tpo $(DEPDIR)/pushpopmem-pushpopmem.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pushpopmem.c' object='pushpopmem-pushpopmem.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pushpopmem_CFLAGS) $(CFLAGS) -c -o pushpopmem-pushpopmem.obj `if test -f 'pushpopmem.c'; then $(CYGPATH_W) 'pushpopmem.c'; else $(CYGPATH_W) '$(srcdir)/pushpopmem.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/memcheck/tests/x86/more_x86_fp.c b/main/memcheck/tests/x86/more_x86_fp.c
index edbc7be..e672703 100644
--- a/main/memcheck/tests/x86/more_x86_fp.c
+++ b/main/memcheck/tests/x86/more_x86_fp.c
@@ -105,7 +105,7 @@
for(i=0;i<4;i++) {
int16_t tmp = (fpuc & ~0x0c00) | (i << 10);
asm volatile ("fldcw %0" : : "m" (tmp));
- asm volatile ("fist %0" : "=m" (wa) : "t" (a));
+ asm volatile ("fists %0" : "=m" (wa) : "t" (a));
asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
diff --git a/main/memcheck/tests/xml1.stderr.exp-s390x-mvc b/main/memcheck/tests/xml1.stderr.exp-s390x-mvc
new file mode 100644
index 0000000..ee34823
--- /dev/null
+++ b/main/memcheck/tests/xml1.stderr.exp-s390x-mvc
@@ -0,0 +1,435 @@
+<?xml version="1.0"?>
+
+<valgrindoutput>
+
+<protocolversion>4</protocolversion>
+<protocoltool>memcheck</protocoltool>
+
+<preamble>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+</preamble>
+
+<pid>...</pid>
+<ppid>...</ppid>
+<tool>memcheck</tool>
+
+<args>
+ <vargv>...</vargv>
+ <argv>
+ <exe>./xml1</exe>
+ </argv>
+</args>
+
+<status>
+ <state>RUNNING</state>
+ <time>...</time>
+</status>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>InvalidRead</kind>
+ <what>Invalid read of size 1</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame3</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame2</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame1</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ <auxwhat>Address 0x........ is 0 bytes after a block of size 40 alloc'd</auxwhat>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>malloc</fn>
+ <dir>...</dir>
+ <file>vg_replace_malloc.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame3</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame2</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame1</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>UninitCondition</kind>
+ <what>Conditional jump or move depends on uninitialised value(s)</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame3</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame2</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame1</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>UninitValue</kind>
+ <what>Use of uninitialised value of size N</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame3</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame2</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame1</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>InvalidFree</kind>
+ <what>Invalid free() / delete / delete[] / realloc()</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>free</fn>
+ <dir>...</dir>
+ <file>vg_replace_malloc.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame3</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame2</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame1</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ <auxwhat>Address 0x........ is 0 bytes inside a block of size 40 free'd</auxwhat>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>free</fn>
+ <dir>...</dir>
+ <file>vg_replace_malloc.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame3</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame2</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame1</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>InvalidFree</kind>
+ <what>Invalid free() / delete / delete[] / realloc()</what>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>free</fn>
+ <dir>...</dir>
+ <file>vg_replace_malloc.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame3</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame2</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame1</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+ <auxwhat>Address 0x........ is on thread 1's stack</auxwhat>
+</error>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>SyscallParam</kind>
+ <what>Syscall param exit(status) contains uninitialised byte(s)</what>
+</error>
+
+
+<status>
+ <state>FINISHED</state>
+ <time>...</time>
+</status>
+
+<error>
+ <unique>0x........</unique>
+ <tid>...</tid>
+ <kind>Leak_DefinitelyLost</kind>
+ <xwhat>
+ <text>396 bytes in 1 blocks are definitely lost in loss record ... of ...</text>
+ <leakedbytes>396</leakedbytes>
+ <leakedblocks>1</leakedblocks>
+ </xwhat>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>malloc</fn>
+ <dir>...</dir>
+ <file>vg_replace_malloc.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame3</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame2</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>frame1</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>xml1.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</error>
+
+<errorcounts>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+ <pair>
+ <count>...</count>
+ <unique>0x........</unique>
+ </pair>
+</errorcounts>
+
+<suppcounts>...</suppcounts>
+
+</valgrindoutput>
+
diff --git a/main/none/Makefile.in b/main/none/Makefile.in
new file mode 100644
index 0000000..8839f46
--- /dev/null
+++ b/main/none/Makefile.in
@@ -0,0 +1,1069 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+
+# On Android we must ask for non-executable stack, not sure why.
+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_2 = -Wl,-z,noexecstack
+noinst_PROGRAMS = none-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
+ $(am__EXEEXT_1)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_3 = none-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
+subdir = none
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = none-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+PROGRAMS = $(noinst_PROGRAMS)
+am__objects_1 = none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.$(OBJEXT)
+am_none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = \
+ $(am_none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
+am__none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = nl_main.c
+am__objects_2 = none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.$(OBJEXT)
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am_none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__objects_2)
+none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS = \
+ $(am_none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES)
+DIST_SOURCES = $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES) \
+ $(am__none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST)
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DIST_SUBDIRS = $(SUBDIRS)
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+SUBDIRS = . tests
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+#----------------------------------------------------------------------------
+# <tool>-<platform> stuff
+#----------------------------------------------------------------------------
+TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/VEX/libvex-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+
+TOOL_LDADD_COMMON = -lgcc
+TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) $(TOOL_LDADD_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
+
+
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+ -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_X86_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_AMD64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_PPC32_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+TOOL_LDFLAGS_PPC64_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_ARM_LINUX = $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
+ $(am__append_2)
+TOOL_LDFLAGS_S390X_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+TOOL_LDFLAGS_X86_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386
+
+TOOL_LDFLAGS_AMD64_DARWIN = \
+ $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+
+
+# MIPS Linux default start symbol is __start, not _start like on x86 or amd
+TOOL_LDFLAGS_MIPS32_LINUX = \
+ -static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
+ @FLAG_M32@
+
+
+# NB for 64-bit darwin. We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them). Although such setting is probably
+# better done in link_tool_exe.c.
+#
+# -Wl,-pagezero_size,0x100000000
+
+#----------------------------------------------------------------------------
+# vgpreload_<tool>-<platform>.a stuff
+#----------------------------------------------------------------------------
+LIBREPLACEMALLOC_X86_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-linux.a
+
+LIBREPLACEMALLOC_AMD64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-linux.a
+
+LIBREPLACEMALLOC_PPC32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a
+
+LIBREPLACEMALLOC_PPC64_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a
+
+LIBREPLACEMALLOC_ARM_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a
+
+LIBREPLACEMALLOC_X86_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-darwin.a
+
+LIBREPLACEMALLOC_AMD64_DARWIN = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-amd64-darwin.a
+
+LIBREPLACEMALLOC_S390X_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-s390x-linux.a
+
+LIBREPLACEMALLOC_MIPS32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips32-linux.a
+
+LIBREPLACEMALLOC_LDFLAGS_X86_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_X86_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_AMD64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC32_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_PPC64_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_ARM_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_X86_DARWIN = \
+ $(LIBREPLACEMALLOC_X86_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_AMD64_DARWIN = \
+ $(LIBREPLACEMALLOC_AMD64_DARWIN)
+
+LIBREPLACEMALLOC_LDFLAGS_S390X_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_S390X_LINUX) \
+ -Wl,--no-whole-archive
+
+LIBREPLACEMALLOC_LDFLAGS_MIPS32_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_MIPS32_LINUX) \
+ -Wl,--no-whole-archive
+
+EXTRA_DIST = docs/nl-manual.xml
+NONE_SOURCES_COMMON = nl_main.c
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+ $(NONE_SOURCES_COMMON)
+
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
+ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS = \
+ $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES = \
+ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@)
+
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
+ $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
+
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
+ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+ @VALT_LOAD_ADDRESS_PRI@ \
+ $(LINK) \
+ $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+ $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(NONE_SOURCES_COMMON)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(AM_CFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-noinstPROGRAMS:
+ -test -z "$(noinst_PROGRAMS)" || rm -f $(noinst_PROGRAMS)
+none-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT): $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f none-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT)
+ $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD) $(LIBS)
+none-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT): $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES)
+ @rm -f none-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
+ $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.o: nl_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.o -MD -MP -MF $(DEPDIR)/none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.Tpo -c -o none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.o `test -f 'nl_main.c' || echo '$(srcdir)/'`nl_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.Tpo $(DEPDIR)/none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='nl_main.c' object='none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.o `test -f 'nl_main.c' || echo '$(srcdir)/'`nl_main.c
+
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.obj: nl_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.obj -MD -MP -MF $(DEPDIR)/none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.Tpo -c -o none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.obj `if test -f 'nl_main.c'; then $(CYGPATH_W) 'nl_main.c'; else $(CYGPATH_W) '$(srcdir)/nl_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.Tpo $(DEPDIR)/none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='nl_main.c' object='none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.obj `if test -f 'nl_main.c'; then $(CYGPATH_W) 'nl_main.c'; else $(CYGPATH_W) '$(srcdir)/nl_main.c'; fi`
+
+none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.o: nl_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.o -MD -MP -MF $(DEPDIR)/none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.Tpo -c -o none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.o `test -f 'nl_main.c' || echo '$(srcdir)/'`nl_main.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.Tpo $(DEPDIR)/none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='nl_main.c' object='none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.o `test -f 'nl_main.c' || echo '$(srcdir)/'`nl_main.c
+
+none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.obj: nl_main.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.obj -MD -MP -MF $(DEPDIR)/none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.Tpo -c -o none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.obj `if test -f 'nl_main.c'; then $(CYGPATH_W) 'nl_main.c'; else $(CYGPATH_W) '$(srcdir)/nl_main.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.Tpo $(DEPDIR)/none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='nl_main.c' object='none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.obj `if test -f 'nl_main.c'; then $(CYGPATH_W) 'nl_main.c'; else $(CYGPATH_W) '$(srcdir)/nl_main.c'; fi`
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+check: check-recursive
+all-am: Makefile $(PROGRAMS) all-local
+installdirs: installdirs-recursive
+installdirs-am:
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-generic clean-local clean-noinstPROGRAMS \
+ mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am: install-exec-local
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+ install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am all-local check check-am clean clean-generic \
+ clean-local clean-noinstPROGRAMS ctags ctags-recursive \
+ distclean distclean-compile distclean-generic distclean-tags \
+ distdir dvi dvi-am html html-am info info-am install \
+ install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-exec-local \
+ install-html install-html-am install-info install-info-am \
+ install-man install-pdf install-pdf-am install-ps \
+ install-ps-am install-strip installcheck installcheck-am \
+ installdirs installdirs-am maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags tags-recursive \
+ uninstall uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+#----------------------------------------------------------------------------
+# General stuff
+#----------------------------------------------------------------------------
+
+all-local: inplace-noinst_PROGRAMS inplace-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/nl_main.c b/main/none/nl_main.c
index 4c1bb18..19647cd 100644
--- a/main/none/nl_main.c
+++ b/main/none/nl_main.c
@@ -7,7 +7,7 @@
This file is part of Nulgrind, the minimal Valgrind tool,
which does no instrumentation or analysis.
- Copyright (C) 2002-2011 Nicholas Nethercote
+ Copyright (C) 2002-2012 Nicholas Nethercote
njn@valgrind.org
This program is free software; you can redistribute it and/or
@@ -55,7 +55,7 @@
VG_(details_version) (NULL);
VG_(details_description) ("the minimal Valgrind tool");
VG_(details_copyright_author)(
- "Copyright (C) 2002-2011, and GNU GPL'd, by Nicholas Nethercote.");
+ "Copyright (C) 2002-2012, and GNU GPL'd, by Nicholas Nethercote.");
VG_(details_bug_reports_to) (VG_BUGS_TO);
VG_(details_avg_translation_sizeB) ( 275 );
diff --git a/main/none/tests/Makefile.am b/main/none/tests/Makefile.am
index a9c498f..2c70374 100644
--- a/main/none/tests/Makefile.am
+++ b/main/none/tests/Makefile.am
@@ -22,6 +22,9 @@
if VGCONF_ARCHS_INCLUDE_S390X
SUBDIRS += s390x
endif
+if VGCONF_ARCHS_INCLUDE_MIPS32
+SUBDIRS += mips32
+endif
# OS-specific tests
if VGCONF_OS_IS_LINUX
@@ -36,7 +39,7 @@
SUBDIRS += x86-linux
endif
-DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm s390x linux darwin x86-linux .
+DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm s390x mips32 linux darwin x86-linux .
dist_noinst_SCRIPTS = \
filter_cmdline0 \
@@ -46,14 +49,17 @@
filter_none_discards \
filter_shell_output \
filter_stderr \
- filter_timestamp
+ filter_timestamp \
+ allexec_prepare_prereq
noinst_HEADERS = fdleak.h
EXTRA_DIST = \
+ allexec32.stdout.exp allexec32.stderr.exp allexec32.vgtest\
+ allexec64.stdout.exp allexec64.stderr.exp allexec64.vgtest\
ansi.stderr.exp ansi.vgtest \
args.stderr.exp args.stdout.exp args.vgtest \
- async-sigs.stderr.exp async-sigs.vgtest \
+ async-sigs.stderr.exp async-sigs.stderr.exp-mips32 async-sigs.vgtest \
bitfield1.stderr.exp bitfield1.vgtest \
bug129866.vgtest bug129866.stderr.exp bug129866.stdout.exp \
closeall.stderr.exp closeall.vgtest \
@@ -89,6 +95,7 @@
fork.stderr.exp fork.stdout.exp fork.vgtest \
fucomip.stderr.exp fucomip.vgtest \
gxx304.stderr.exp gxx304.vgtest \
+ ifunc.stderr.exp ifunc.stdout.exp ifunc.vgtest \
manythreads.stdout.exp manythreads.stderr.exp manythreads.vgtest \
map_unaligned.stderr.exp map_unaligned.vgtest \
map_unmap.stderr.exp map_unmap.stdout.exp map_unmap.vgtest \
@@ -97,6 +104,7 @@
mq.stderr.exp mq.vgtest \
munmap_exe.stderr.exp munmap_exe.vgtest \
nestedfns.stderr.exp nestedfns.stdout.exp nestedfns.vgtest \
+ nodir.stderr.exp nodir.vgtest \
pending.stdout.exp pending.stderr.exp pending.vgtest \
procfs-linux.stderr.exp-with-readlinkat \
procfs-linux.stderr.exp-without-readlinkat \
@@ -127,11 +135,12 @@
res_search.stderr.exp res_search.stdout.exp res_search.vgtest \
resolv.stderr.exp resolv.stdout.exp resolv.vgtest \
rlimit_nofile.stderr.exp rlimit_nofile.stdout.exp rlimit_nofile.vgtest \
+ rlimit64_nofile.stderr.exp rlimit64_nofile.stdout.exp rlimit64_nofile.vgtest \
selfrun.stderr.exp selfrun.stdout.exp selfrun.vgtest \
sem.stderr.exp sem.stdout.exp sem.vgtest \
semlimit.stderr.exp semlimit.stdout.exp semlimit.vgtest \
shell shell.vgtest shell.stderr.exp shell.stderr.exp-dash \
- shell.stdout.exp \
+ shell.stdout.exp shell.stderr.exp-dash2 \
shell_badinterp shell_badinterp.vgtest shell_badinterp.stderr.exp \
shell_binaryfile shell_binaryfile.vgtest shell_binaryfile.stderr.exp \
shell_dir.vgtest shell_dir.stderr.exp \
@@ -157,7 +166,8 @@
threadederrno.vgtest \
timestamp.stderr.exp timestamp.vgtest \
tls.vgtest tls.stderr.exp tls.stdout.exp \
- vgprintf.stderr.exp vgprintf.vgtest
+ vgprintf.stderr.exp vgprintf.vgtest \
+ process_vm_readv_writev.stderr.exp process_vm_readv_writev.vgtest
check_PROGRAMS = \
ansi args \
@@ -195,7 +205,8 @@
valgrind_cpp_test \
vgprintf \
coolo_sigaction \
- gxx304
+ gxx304 \
+ process_vm_readv_writev
# DDD:
# - manythreads and thread-exits have lots of this:
@@ -212,7 +223,14 @@
manythreads \
thread-exits
endif
+# This doesn't appear to be compilable on Darwin.
+if ! VGCONF_OS_IS_DARWIN
+ check_PROGRAMS += rlimit64_nofile
+endif
+if BUILD_IFUNC_TESTS
+ check_PROGRAMS += ifunc
+endif
AM_CFLAGS += $(AM_FLAG_M3264_PRI)
AM_CXXFLAGS += $(AM_FLAG_M3264_PRI)
diff --git a/main/none/tests/Makefile.in b/main/none/tests/Makefile.in
new file mode 100644
index 0000000..62b8a07
--- /dev/null
+++ b/main/none/tests/Makefile.in
@@ -0,0 +1,1761 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(noinst_HEADERS) \
+ $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
+ $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Arch-specific tests.
+@VGCONF_ARCHS_INCLUDE_X86_TRUE@am__append_3 = x86
+@VGCONF_ARCHS_INCLUDE_AMD64_TRUE@am__append_4 = amd64
+@VGCONF_ARCHS_INCLUDE_PPC32_TRUE@am__append_5 = ppc32
+@VGCONF_ARCHS_INCLUDE_PPC64_TRUE@am__append_6 = ppc64
+@VGCONF_ARCHS_INCLUDE_ARM_TRUE@am__append_7 = arm
+@VGCONF_ARCHS_INCLUDE_S390X_TRUE@am__append_8 = s390x
+@VGCONF_ARCHS_INCLUDE_MIPS32_TRUE@am__append_9 = mips32
+
+# OS-specific tests
+@VGCONF_OS_IS_LINUX_TRUE@am__append_10 = linux
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_11 = darwin
+
+# Platform-specific tests
+@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_12 = x86-linux
+check_PROGRAMS = ansi$(EXEEXT) args$(EXEEXT) async-sigs$(EXEEXT) \
+ bitfield1$(EXEEXT) bug129866$(EXEEXT) closeall$(EXEEXT) \
+ coolo_strlen$(EXEEXT) discard$(EXEEXT) exec-sigmask$(EXEEXT) \
+ execve$(EXEEXT) faultstatus$(EXEEXT) fcntl_setown$(EXEEXT) \
+ fdleak_cmsg$(EXEEXT) fdleak_creat$(EXEEXT) fdleak_dup$(EXEEXT) \
+ fdleak_dup2$(EXEEXT) fdleak_fcntl$(EXEEXT) \
+ fdleak_ipv4$(EXEEXT) fdleak_open$(EXEEXT) fdleak_pipe$(EXEEXT) \
+ fdleak_socketpair$(EXEEXT) floored$(EXEEXT) fork$(EXEEXT) \
+ fucomip$(EXEEXT) mmap_fcntl_bug$(EXEEXT) munmap_exe$(EXEEXT) \
+ map_unaligned$(EXEEXT) map_unmap$(EXEEXT) mq$(EXEEXT) \
+ nestedfns$(EXEEXT) pending$(EXEEXT) \
+ procfs-cmdline-exe$(EXEEXT) pth_atfork1$(EXEEXT) \
+ pth_blockedsig$(EXEEXT) pth_cancel1$(EXEEXT) \
+ pth_cancel2$(EXEEXT) pth_cvsimple$(EXEEXT) pth_empty$(EXEEXT) \
+ pth_exit$(EXEEXT) pth_exit2$(EXEEXT) pth_mutexspeed$(EXEEXT) \
+ pth_once$(EXEEXT) pth_rwlock$(EXEEXT) pth_stackalign$(EXEEXT) \
+ rcrl$(EXEEXT) readline1$(EXEEXT) require-text-symbol$(EXEEXT) \
+ res_search$(EXEEXT) resolv$(EXEEXT) rlimit_nofile$(EXEEXT) \
+ selfrun$(EXEEXT) sem$(EXEEXT) semlimit$(EXEEXT) \
+ sha1_test$(EXEEXT) shortpush$(EXEEXT) shorts$(EXEEXT) \
+ stackgrowth$(EXEEXT) sigstackgrowth$(EXEEXT) \
+ syscall-restart1$(EXEEXT) syscall-restart2$(EXEEXT) \
+ syslog$(EXEEXT) system$(EXEEXT) threaded-fork$(EXEEXT) \
+ threadederrno$(EXEEXT) timestamp$(EXEEXT) tls$(EXEEXT) \
+ tls.so$(EXEEXT) tls2.so$(EXEEXT) valgrind_cpp_test$(EXEEXT) \
+ vgprintf$(EXEEXT) coolo_sigaction$(EXEEXT) gxx304$(EXEEXT) \
+ process_vm_readv_writev$(EXEEXT) $(am__EXEEXT_1) \
+ $(am__EXEEXT_2) $(am__EXEEXT_3)
+
+# DDD:
+# - manythreads and thread-exits have lots of this:
+# --61831:0:aspacem sync_check_mapping_callback: segment mismatch:
+# kernel's seg:
+# --61831:0:aspacem start=0x102538000 end=0x1025b7fff prot=3 dev=0 ino=0
+# offset=0 name="(none)"
+# --61831:0:aspacem sync_check_mapping_callback: segment mismatch: V's seg:
+# --61831:0:aspacem NSegment{ , start=0x10067a000, end=0x109a1efff,
+# smode=SmFixed, dev=0, ino=0, offset=0, fnIdx=-1, hasR=0,
+# hasW=0, hasX=0, hasT=0, mark=0, name="(none)"}
+@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_FALSE@am__append_13 = \
+@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_FALSE@ manythreads \
+@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_FALSE@ thread-exits
+
+# This doesn't appear to be compilable on Darwin.
+@VGCONF_OS_IS_DARWIN_FALSE@am__append_14 = rlimit64_nofile
+@BUILD_IFUNC_TESTS_TRUE@am__append_15 = ifunc
+subdir = none/tests
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_FALSE@am__EXEEXT_1 = manythreads$(EXEEXT) \
+@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_FALSE@ thread-exits$(EXEEXT)
+@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_2 = rlimit64_nofile$(EXEEXT)
+@BUILD_IFUNC_TESTS_TRUE@am__EXEEXT_3 = ifunc$(EXEEXT)
+ansi_SOURCES = ansi.c
+ansi_OBJECTS = ansi-ansi.$(OBJEXT)
+ansi_LDADD = $(LDADD)
+ansi_LINK = $(CCLD) $(ansi_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+args_SOURCES = args.c
+args_OBJECTS = args.$(OBJEXT)
+args_LDADD = $(LDADD)
+async_sigs_SOURCES = async-sigs.c
+async_sigs_OBJECTS = async-sigs.$(OBJEXT)
+async_sigs_LDADD = $(LDADD)
+bitfield1_SOURCES = bitfield1.c
+bitfield1_OBJECTS = bitfield1.$(OBJEXT)
+bitfield1_LDADD = $(LDADD)
+bug129866_SOURCES = bug129866.c
+bug129866_OBJECTS = bug129866.$(OBJEXT)
+bug129866_LDADD = $(LDADD)
+closeall_SOURCES = closeall.c
+closeall_OBJECTS = closeall.$(OBJEXT)
+closeall_LDADD = $(LDADD)
+am_coolo_sigaction_OBJECTS = coolo_sigaction.$(OBJEXT)
+coolo_sigaction_OBJECTS = $(am_coolo_sigaction_OBJECTS)
+coolo_sigaction_LDADD = $(LDADD)
+coolo_strlen_SOURCES = coolo_strlen.c
+coolo_strlen_OBJECTS = coolo_strlen.$(OBJEXT)
+coolo_strlen_LDADD = $(LDADD)
+discard_SOURCES = discard.c
+discard_OBJECTS = discard.$(OBJEXT)
+discard_LDADD = $(LDADD)
+exec_sigmask_SOURCES = exec-sigmask.c
+exec_sigmask_OBJECTS = exec-sigmask.$(OBJEXT)
+exec_sigmask_LDADD = $(LDADD)
+execve_SOURCES = execve.c
+execve_OBJECTS = execve-execve.$(OBJEXT)
+execve_LDADD = $(LDADD)
+execve_LINK = $(CCLD) $(execve_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+faultstatus_SOURCES = faultstatus.c
+faultstatus_OBJECTS = faultstatus.$(OBJEXT)
+faultstatus_LDADD = $(LDADD)
+fcntl_setown_SOURCES = fcntl_setown.c
+fcntl_setown_OBJECTS = fcntl_setown.$(OBJEXT)
+fcntl_setown_LDADD = $(LDADD)
+fdleak_cmsg_SOURCES = fdleak_cmsg.c
+fdleak_cmsg_OBJECTS = fdleak_cmsg.$(OBJEXT)
+fdleak_cmsg_LDADD = $(LDADD)
+fdleak_creat_SOURCES = fdleak_creat.c
+fdleak_creat_OBJECTS = fdleak_creat.$(OBJEXT)
+fdleak_creat_LDADD = $(LDADD)
+fdleak_dup_SOURCES = fdleak_dup.c
+fdleak_dup_OBJECTS = fdleak_dup.$(OBJEXT)
+fdleak_dup_LDADD = $(LDADD)
+fdleak_dup2_SOURCES = fdleak_dup2.c
+fdleak_dup2_OBJECTS = fdleak_dup2.$(OBJEXT)
+fdleak_dup2_LDADD = $(LDADD)
+fdleak_fcntl_SOURCES = fdleak_fcntl.c
+fdleak_fcntl_OBJECTS = fdleak_fcntl.$(OBJEXT)
+fdleak_fcntl_LDADD = $(LDADD)
+fdleak_ipv4_SOURCES = fdleak_ipv4.c
+fdleak_ipv4_OBJECTS = fdleak_ipv4.$(OBJEXT)
+fdleak_ipv4_LDADD = $(LDADD)
+fdleak_open_SOURCES = fdleak_open.c
+fdleak_open_OBJECTS = fdleak_open.$(OBJEXT)
+fdleak_open_LDADD = $(LDADD)
+fdleak_pipe_SOURCES = fdleak_pipe.c
+fdleak_pipe_OBJECTS = fdleak_pipe.$(OBJEXT)
+fdleak_pipe_LDADD = $(LDADD)
+fdleak_socketpair_SOURCES = fdleak_socketpair.c
+fdleak_socketpair_OBJECTS = fdleak_socketpair.$(OBJEXT)
+fdleak_socketpair_LDADD = $(LDADD)
+floored_SOURCES = floored.c
+floored_OBJECTS = floored.$(OBJEXT)
+floored_DEPENDENCIES =
+fork_SOURCES = fork.c
+fork_OBJECTS = fork.$(OBJEXT)
+fork_LDADD = $(LDADD)
+fucomip_SOURCES = fucomip.c
+fucomip_OBJECTS = fucomip.$(OBJEXT)
+fucomip_LDADD = $(LDADD)
+am_gxx304_OBJECTS = gxx304.$(OBJEXT)
+gxx304_OBJECTS = $(am_gxx304_OBJECTS)
+gxx304_LDADD = $(LDADD)
+ifunc_SOURCES = ifunc.c
+ifunc_OBJECTS = ifunc.$(OBJEXT)
+ifunc_LDADD = $(LDADD)
+manythreads_SOURCES = manythreads.c
+manythreads_OBJECTS = manythreads.$(OBJEXT)
+manythreads_DEPENDENCIES =
+map_unaligned_SOURCES = map_unaligned.c
+map_unaligned_OBJECTS = map_unaligned.$(OBJEXT)
+map_unaligned_LDADD = $(LDADD)
+map_unmap_SOURCES = map_unmap.c
+map_unmap_OBJECTS = map_unmap.$(OBJEXT)
+map_unmap_LDADD = $(LDADD)
+mmap_fcntl_bug_SOURCES = mmap_fcntl_bug.c
+mmap_fcntl_bug_OBJECTS = mmap_fcntl_bug.$(OBJEXT)
+mmap_fcntl_bug_LDADD = $(LDADD)
+mq_SOURCES = mq.c
+mq_OBJECTS = mq.$(OBJEXT)
+mq_DEPENDENCIES =
+munmap_exe_SOURCES = munmap_exe.c
+munmap_exe_OBJECTS = munmap_exe.$(OBJEXT)
+munmap_exe_LDADD = $(LDADD)
+nestedfns_SOURCES = nestedfns.c
+nestedfns_OBJECTS = nestedfns-nestedfns.$(OBJEXT)
+nestedfns_LDADD = $(LDADD)
+nestedfns_LINK = $(CCLD) $(nestedfns_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+pending_SOURCES = pending.c
+pending_OBJECTS = pending.$(OBJEXT)
+pending_LDADD = $(LDADD)
+process_vm_readv_writev_SOURCES = process_vm_readv_writev.c
+process_vm_readv_writev_OBJECTS = process_vm_readv_writev.$(OBJEXT)
+process_vm_readv_writev_LDADD = $(LDADD)
+procfs_cmdline_exe_SOURCES = procfs-cmdline-exe.c
+procfs_cmdline_exe_OBJECTS = procfs-cmdline-exe.$(OBJEXT)
+procfs_cmdline_exe_LDADD = $(LDADD)
+pth_atfork1_SOURCES = pth_atfork1.c
+pth_atfork1_OBJECTS = pth_atfork1.$(OBJEXT)
+pth_atfork1_DEPENDENCIES =
+pth_blockedsig_SOURCES = pth_blockedsig.c
+pth_blockedsig_OBJECTS = pth_blockedsig.$(OBJEXT)
+pth_blockedsig_DEPENDENCIES =
+pth_cancel1_SOURCES = pth_cancel1.c
+pth_cancel1_OBJECTS = pth_cancel1-pth_cancel1.$(OBJEXT)
+pth_cancel1_DEPENDENCIES =
+pth_cancel1_LINK = $(CCLD) $(pth_cancel1_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+pth_cancel2_SOURCES = pth_cancel2.c
+pth_cancel2_OBJECTS = pth_cancel2.$(OBJEXT)
+pth_cancel2_DEPENDENCIES =
+pth_cvsimple_SOURCES = pth_cvsimple.c
+pth_cvsimple_OBJECTS = pth_cvsimple.$(OBJEXT)
+pth_cvsimple_DEPENDENCIES =
+pth_empty_SOURCES = pth_empty.c
+pth_empty_OBJECTS = pth_empty.$(OBJEXT)
+pth_empty_DEPENDENCIES =
+pth_exit_SOURCES = pth_exit.c
+pth_exit_OBJECTS = pth_exit.$(OBJEXT)
+pth_exit_DEPENDENCIES =
+pth_exit2_SOURCES = pth_exit2.c
+pth_exit2_OBJECTS = pth_exit2.$(OBJEXT)
+pth_exit2_DEPENDENCIES =
+pth_mutexspeed_SOURCES = pth_mutexspeed.c
+pth_mutexspeed_OBJECTS = pth_mutexspeed.$(OBJEXT)
+pth_mutexspeed_DEPENDENCIES =
+pth_once_SOURCES = pth_once.c
+pth_once_OBJECTS = pth_once.$(OBJEXT)
+pth_once_DEPENDENCIES =
+pth_rwlock_SOURCES = pth_rwlock.c
+pth_rwlock_OBJECTS = pth_rwlock.$(OBJEXT)
+pth_rwlock_DEPENDENCIES =
+pth_stackalign_SOURCES = pth_stackalign.c
+pth_stackalign_OBJECTS = pth_stackalign.$(OBJEXT)
+pth_stackalign_DEPENDENCIES =
+rcrl_SOURCES = rcrl.c
+rcrl_OBJECTS = rcrl.$(OBJEXT)
+rcrl_LDADD = $(LDADD)
+readline1_SOURCES = readline1.c
+readline1_OBJECTS = readline1.$(OBJEXT)
+readline1_LDADD = $(LDADD)
+require_text_symbol_SOURCES = require-text-symbol.c
+require_text_symbol_OBJECTS = require-text-symbol.$(OBJEXT)
+require_text_symbol_LDADD = $(LDADD)
+res_search_SOURCES = res_search.c
+res_search_OBJECTS = res_search.$(OBJEXT)
+res_search_DEPENDENCIES =
+resolv_SOURCES = resolv.c
+resolv_OBJECTS = resolv.$(OBJEXT)
+resolv_DEPENDENCIES =
+rlimit64_nofile_SOURCES = rlimit64_nofile.c
+rlimit64_nofile_OBJECTS = rlimit64_nofile.$(OBJEXT)
+rlimit64_nofile_LDADD = $(LDADD)
+rlimit_nofile_SOURCES = rlimit_nofile.c
+rlimit_nofile_OBJECTS = rlimit_nofile.$(OBJEXT)
+rlimit_nofile_LDADD = $(LDADD)
+selfrun_SOURCES = selfrun.c
+selfrun_OBJECTS = selfrun.$(OBJEXT)
+selfrun_LDADD = $(LDADD)
+sem_SOURCES = sem.c
+sem_OBJECTS = sem.$(OBJEXT)
+sem_LDADD = $(LDADD)
+semlimit_SOURCES = semlimit.c
+semlimit_OBJECTS = semlimit.$(OBJEXT)
+semlimit_DEPENDENCIES =
+sha1_test_SOURCES = sha1_test.c
+sha1_test_OBJECTS = sha1_test.$(OBJEXT)
+sha1_test_LDADD = $(LDADD)
+shortpush_SOURCES = shortpush.c
+shortpush_OBJECTS = shortpush.$(OBJEXT)
+shortpush_LDADD = $(LDADD)
+shorts_SOURCES = shorts.c
+shorts_OBJECTS = shorts.$(OBJEXT)
+shorts_LDADD = $(LDADD)
+sigstackgrowth_SOURCES = sigstackgrowth.c
+sigstackgrowth_OBJECTS = sigstackgrowth.$(OBJEXT)
+sigstackgrowth_LDADD = $(LDADD)
+stackgrowth_SOURCES = stackgrowth.c
+stackgrowth_OBJECTS = stackgrowth.$(OBJEXT)
+stackgrowth_LDADD = $(LDADD)
+syscall_restart1_SOURCES = syscall-restart1.c
+syscall_restart1_OBJECTS = syscall-restart1.$(OBJEXT)
+syscall_restart1_LDADD = $(LDADD)
+syscall_restart2_SOURCES = syscall-restart2.c
+syscall_restart2_OBJECTS = syscall-restart2.$(OBJEXT)
+syscall_restart2_LDADD = $(LDADD)
+syslog_SOURCES = syslog.c
+syslog_OBJECTS = syslog.$(OBJEXT)
+syslog_LDADD = $(LDADD)
+system_SOURCES = system.c
+system_OBJECTS = system.$(OBJEXT)
+system_LDADD = $(LDADD)
+thread_exits_SOURCES = thread-exits.c
+thread_exits_OBJECTS = thread-exits.$(OBJEXT)
+thread_exits_DEPENDENCIES =
+threaded_fork_SOURCES = threaded-fork.c
+threaded_fork_OBJECTS = threaded-fork.$(OBJEXT)
+threaded_fork_DEPENDENCIES =
+threadederrno_SOURCES = threadederrno.c
+threadederrno_OBJECTS = threadederrno.$(OBJEXT)
+threadederrno_DEPENDENCIES =
+timestamp_SOURCES = timestamp.c
+timestamp_OBJECTS = timestamp.$(OBJEXT)
+timestamp_LDADD = $(LDADD)
+am_tls_OBJECTS = tls.$(OBJEXT) tls2.$(OBJEXT)
+tls_OBJECTS = $(am_tls_OBJECTS)
+tls_LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(tls_LDFLAGS) $(LDFLAGS) -o \
+ $@
+am_tls_so_OBJECTS = tls_so-tls_so.$(OBJEXT)
+tls_so_OBJECTS = $(am_tls_so_OBJECTS)
+tls_so_LINK = $(CCLD) $(tls_so_CFLAGS) $(CFLAGS) $(tls_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am_tls2_so_OBJECTS = tls2_so.$(OBJEXT)
+tls2_so_OBJECTS = $(am_tls2_so_OBJECTS)
+tls2_so_LDADD = $(LDADD)
+tls2_so_LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(tls2_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am_valgrind_cpp_test_OBJECTS = valgrind_cpp_test.$(OBJEXT)
+valgrind_cpp_test_OBJECTS = $(am_valgrind_cpp_test_OBJECTS)
+valgrind_cpp_test_DEPENDENCIES =
+vgprintf_SOURCES = vgprintf.c
+vgprintf_OBJECTS = vgprintf.$(OBJEXT)
+vgprintf_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+CXXCOMPILE = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS)
+CXXLD = $(CXX)
+CXXLINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+SOURCES = ansi.c args.c async-sigs.c bitfield1.c bug129866.c \
+ closeall.c $(coolo_sigaction_SOURCES) coolo_strlen.c discard.c \
+ exec-sigmask.c execve.c faultstatus.c fcntl_setown.c \
+ fdleak_cmsg.c fdleak_creat.c fdleak_dup.c fdleak_dup2.c \
+ fdleak_fcntl.c fdleak_ipv4.c fdleak_open.c fdleak_pipe.c \
+ fdleak_socketpair.c floored.c fork.c fucomip.c \
+ $(gxx304_SOURCES) ifunc.c manythreads.c map_unaligned.c \
+ map_unmap.c mmap_fcntl_bug.c mq.c munmap_exe.c nestedfns.c \
+ pending.c process_vm_readv_writev.c procfs-cmdline-exe.c \
+ pth_atfork1.c pth_blockedsig.c pth_cancel1.c pth_cancel2.c \
+ pth_cvsimple.c pth_empty.c pth_exit.c pth_exit2.c \
+ pth_mutexspeed.c pth_once.c pth_rwlock.c pth_stackalign.c \
+ rcrl.c readline1.c require-text-symbol.c res_search.c resolv.c \
+ rlimit64_nofile.c rlimit_nofile.c selfrun.c sem.c semlimit.c \
+ sha1_test.c shortpush.c shorts.c sigstackgrowth.c \
+ stackgrowth.c syscall-restart1.c syscall-restart2.c syslog.c \
+ system.c thread-exits.c threaded-fork.c threadederrno.c \
+ timestamp.c $(tls_SOURCES) $(tls_so_SOURCES) \
+ $(tls2_so_SOURCES) $(valgrind_cpp_test_SOURCES) vgprintf.c
+DIST_SOURCES = ansi.c args.c async-sigs.c bitfield1.c bug129866.c \
+ closeall.c $(coolo_sigaction_SOURCES) coolo_strlen.c discard.c \
+ exec-sigmask.c execve.c faultstatus.c fcntl_setown.c \
+ fdleak_cmsg.c fdleak_creat.c fdleak_dup.c fdleak_dup2.c \
+ fdleak_fcntl.c fdleak_ipv4.c fdleak_open.c fdleak_pipe.c \
+ fdleak_socketpair.c floored.c fork.c fucomip.c \
+ $(gxx304_SOURCES) ifunc.c manythreads.c map_unaligned.c \
+ map_unmap.c mmap_fcntl_bug.c mq.c munmap_exe.c nestedfns.c \
+ pending.c process_vm_readv_writev.c procfs-cmdline-exe.c \
+ pth_atfork1.c pth_blockedsig.c pth_cancel1.c pth_cancel2.c \
+ pth_cvsimple.c pth_empty.c pth_exit.c pth_exit2.c \
+ pth_mutexspeed.c pth_once.c pth_rwlock.c pth_stackalign.c \
+ rcrl.c readline1.c require-text-symbol.c res_search.c resolv.c \
+ rlimit64_nofile.c rlimit_nofile.c selfrun.c sem.c semlimit.c \
+ sha1_test.c shortpush.c shorts.c sigstackgrowth.c \
+ stackgrowth.c syscall-restart1.c syscall-restart2.c syslog.c \
+ system.c thread-exits.c threaded-fork.c threadederrno.c \
+ timestamp.c $(tls_SOURCES) $(tls_so_SOURCES) \
+ $(tls2_so_SOURCES) $(valgrind_cpp_test_SOURCES) vgprintf.c
+RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
+ html-recursive info-recursive install-data-recursive \
+ install-dvi-recursive install-exec-recursive \
+ install-html-recursive install-info-recursive \
+ install-pdf-recursive install-ps-recursive install-recursive \
+ installcheck-recursive installdirs-recursive pdf-recursive \
+ ps-recursive uninstall-recursive
+HEADERS = $(noinst_HEADERS)
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \
+ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \
+ distdir
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+SUBDIRS = . $(am__append_3) $(am__append_4) $(am__append_5) \
+ $(am__append_6) $(am__append_7) $(am__append_8) \
+ $(am__append_9) $(am__append_10) $(am__append_11) \
+ $(am__append_12)
+DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm s390x mips32 linux darwin x86-linux .
+dist_noinst_SCRIPTS = \
+ filter_cmdline0 \
+ filter_cmdline1 \
+ filter_fdleak \
+ filter_linenos \
+ filter_none_discards \
+ filter_shell_output \
+ filter_stderr \
+ filter_timestamp \
+ allexec_prepare_prereq
+
+noinst_HEADERS = fdleak.h
+EXTRA_DIST = \
+ allexec32.stdout.exp allexec32.stderr.exp allexec32.vgtest\
+ allexec64.stdout.exp allexec64.stderr.exp allexec64.vgtest\
+ ansi.stderr.exp ansi.vgtest \
+ args.stderr.exp args.stdout.exp args.vgtest \
+ async-sigs.stderr.exp async-sigs.stderr.exp-mips32 async-sigs.vgtest \
+ bitfield1.stderr.exp bitfield1.vgtest \
+ bug129866.vgtest bug129866.stderr.exp bug129866.stdout.exp \
+ closeall.stderr.exp closeall.vgtest \
+ cmdline0.stderr.exp cmdline0.stdout.exp cmdline0.vgtest \
+ cmdline1.stderr.exp cmdline1.stdout.exp cmdline1.vgtest \
+ cmdline2.stderr.exp cmdline2.stdout.exp cmdline2.vgtest \
+ cmdline3.stderr.exp cmdline3.vgtest \
+ cmdline4.stderr.exp cmdline4.vgtest \
+ cmdline5.stderr.exp cmdline5.vgtest \
+ cmdline6.stderr.exp cmdline6.vgtest \
+ cmd-with-special.stderr.exp cmd-with-special.vgtest \
+ coolo_sigaction.stderr.exp \
+ coolo_sigaction.stdout.exp coolo_sigaction.vgtest \
+ coolo_strlen.stderr.exp coolo_strlen.vgtest \
+ discard.stderr.exp discard.stdout.exp \
+ discard.vgtest \
+ empty-exe.vgtest empty-exe.stderr.exp \
+ exec-sigmask.vgtest exec-sigmask.stdout.exp \
+ exec-sigmask.stdout.exp2 exec-sigmask.stdout.exp3 exec-sigmask.stderr.exp \
+ execve.vgtest execve.stdout.exp execve.stderr.exp \
+ faultstatus.vgtest faultstatus.stderr.exp faultstatus.stderr.exp-s390x \
+ fcntl_setown.vgtest fcntl_setown.stdout.exp fcntl_setown.stderr.exp \
+ fdleak_cmsg.stderr.exp fdleak_cmsg.vgtest \
+ fdleak_creat.stderr.exp fdleak_creat.vgtest \
+ fdleak_dup.stderr.exp fdleak_dup.vgtest \
+ fdleak_dup2.stderr.exp fdleak_dup2.vgtest \
+ fdleak_fcntl.stderr.exp fdleak_fcntl.vgtest \
+ fdleak_ipv4.stderr.exp fdleak_ipv4.stdout.exp fdleak_ipv4.vgtest \
+ fdleak_open.stderr.exp fdleak_open.vgtest \
+ fdleak_pipe.stderr.exp fdleak_pipe.vgtest \
+ fdleak_socketpair.stderr.exp fdleak_socketpair.vgtest \
+ floored.stderr.exp floored.stdout.exp floored.vgtest \
+ fork.stderr.exp fork.stdout.exp fork.vgtest \
+ fucomip.stderr.exp fucomip.vgtest \
+ gxx304.stderr.exp gxx304.vgtest \
+ ifunc.stderr.exp ifunc.stdout.exp ifunc.vgtest \
+ manythreads.stdout.exp manythreads.stderr.exp manythreads.vgtest \
+ map_unaligned.stderr.exp map_unaligned.vgtest \
+ map_unmap.stderr.exp map_unmap.stdout.exp map_unmap.vgtest \
+ mmap_fcntl_bug.vgtest mmap_fcntl_bug.stdout.exp \
+ mmap_fcntl_bug.stderr.exp \
+ mq.stderr.exp mq.vgtest \
+ munmap_exe.stderr.exp munmap_exe.vgtest \
+ nestedfns.stderr.exp nestedfns.stdout.exp nestedfns.vgtest \
+ nodir.stderr.exp nodir.vgtest \
+ pending.stdout.exp pending.stderr.exp pending.vgtest \
+ procfs-linux.stderr.exp-with-readlinkat \
+ procfs-linux.stderr.exp-without-readlinkat \
+ procfs-linux.vgtest \
+ procfs-non-linux.stderr.exp procfs-non-linux.vgtest \
+ pth_atfork1.stderr.exp pth_atfork1.stdout.exp pth_atfork1.vgtest \
+ pth_blockedsig.stderr.exp \
+ pth_blockedsig.stdout.exp pth_blockedsig.vgtest \
+ pth_cancel1.stderr.exp pth_cancel1.stdout.exp pth_cancel1.vgtest \
+ pth_cancel2.stderr.exp pth_cancel2.vgtest \
+ pth_cvsimple.stderr.exp pth_cvsimple.stdout.exp pth_cvsimple.vgtest \
+ pth_empty.stderr.exp pth_empty.vgtest \
+ pth_exit.stderr.exp pth_exit.vgtest \
+ pth_exit2.stderr.exp pth_exit2.vgtest \
+ pth_mutexspeed.stderr.exp \
+ pth_mutexspeed.stdout.exp pth_mutexspeed.vgtest \
+ pth_once.stderr.exp pth_once.stdout.exp pth_once.vgtest \
+ pth_rwlock.stderr.exp pth_rwlock.vgtest \
+ pth_stackalign.stderr.exp \
+ pth_stackalign.stdout.exp pth_stackalign.vgtest \
+ rcrl.stderr.exp rcrl.stdout.exp rcrl.vgtest \
+ readline1.stderr.exp readline1.stdout.exp \
+ readline1.vgtest \
+ require-text-symbol-1.vgtest \
+ require-text-symbol-1.stderr.exp \
+ require-text-symbol-2.vgtest \
+ require-text-symbol-2.stderr.exp-libcso6 \
+ res_search.stderr.exp res_search.stdout.exp res_search.vgtest \
+ resolv.stderr.exp resolv.stdout.exp resolv.vgtest \
+ rlimit_nofile.stderr.exp rlimit_nofile.stdout.exp rlimit_nofile.vgtest \
+ rlimit64_nofile.stderr.exp rlimit64_nofile.stdout.exp rlimit64_nofile.vgtest \
+ selfrun.stderr.exp selfrun.stdout.exp selfrun.vgtest \
+ sem.stderr.exp sem.stdout.exp sem.vgtest \
+ semlimit.stderr.exp semlimit.stdout.exp semlimit.vgtest \
+ shell shell.vgtest shell.stderr.exp shell.stderr.exp-dash \
+ shell.stdout.exp shell.stderr.exp-dash2 \
+ shell_badinterp shell_badinterp.vgtest shell_badinterp.stderr.exp \
+ shell_binaryfile shell_binaryfile.vgtest shell_binaryfile.stderr.exp \
+ shell_dir.vgtest shell_dir.stderr.exp \
+ shell_nonexec.vgtest shell_nonexec.stderr.exp \
+ shell_nosuchfile.vgtest shell_nosuchfile.stderr.exp \
+ shell_valid1 shell_valid1.vgtest shell_valid1.stderr.exp \
+ shell_valid2 shell_valid2.vgtest shell_valid2.stderr.exp \
+ shell_valid3 shell_valid3.vgtest shell_valid3.stderr.exp \
+ shell_zerolength shell_zerolength.vgtest shell_zerolength.stderr.exp \
+ shell_zerolength.stderr.exp-dash \
+ sha1_test.stderr.exp sha1_test.vgtest \
+ shortpush.stderr.exp shortpush.vgtest \
+ shorts.stderr.exp shorts.vgtest \
+ sigstackgrowth.stdout.exp sigstackgrowth.stderr.exp sigstackgrowth.vgtest \
+ stackgrowth.stdout.exp stackgrowth.stderr.exp stackgrowth.vgtest \
+ syscall-restart1.vgtest syscall-restart1.stdout.exp syscall-restart1.stderr.exp \
+ syscall-restart2.vgtest syscall-restart2.stdout.exp syscall-restart2.stderr.exp \
+ syslog.vgtest syslog.stderr.exp \
+ system.stderr.exp system.vgtest \
+ thread-exits.stderr.exp thread-exits.stdout.exp thread-exits.vgtest \
+ threaded-fork.stderr.exp threaded-fork.stdout.exp threaded-fork.vgtest \
+ threadederrno.stderr.exp threadederrno.stdout.exp \
+ threadederrno.vgtest \
+ timestamp.stderr.exp timestamp.vgtest \
+ tls.vgtest tls.stderr.exp tls.stdout.exp \
+ vgprintf.stderr.exp vgprintf.vgtest \
+ process_vm_readv_writev.stderr.exp process_vm_readv_writev.vgtest
+
+
+# Extra stuff for C tests
+ansi_CFLAGS = $(AM_CFLAGS) -ansi
+execve_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+floored_LDADD = -lm
+manythreads_LDADD = -lpthread
+@VGCONF_OS_IS_DARWIN_FALSE@nestedfns_CFLAGS = $(AM_CFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@nestedfns_CFLAGS = $(AM_CFLAGS) -fnested-functions
+@VGCONF_OS_IS_DARWIN_FALSE@mq_LDADD = -lrt
+pth_atfork1_LDADD = -lpthread
+pth_blockedsig_LDADD = -lpthread
+pth_cancel1_CFLAGS = $(AM_CFLAGS) -Wno-shadow
+pth_cancel1_LDADD = -lpthread
+pth_cancel2_LDADD = -lpthread
+pth_cvsimple_LDADD = -lpthread
+pth_empty_LDADD = -lpthread
+pth_exit_LDADD = -lpthread
+pth_exit2_LDADD = -lpthread
+pth_mutexspeed_LDADD = -lpthread
+pth_once_LDADD = -lpthread
+pth_rwlock_LDADD = -lpthread
+pth_stackalign_LDADD = -lpthread
+res_search_LDADD = -lresolv -lpthread
+resolv_LDADD = -lresolv -lpthread
+semlimit_LDADD = -lpthread
+thread_exits_LDADD = -lpthread
+threaded_fork_LDADD = -lpthread
+threadederrno_LDADD = -lpthread
+tls_SOURCES = tls.c tls2.c
+tls_DEPENDENCIES = tls.so tls2.so
+tls_LDFLAGS = -Wl,-rpath,$(top_builddir)/none/tests
+tls_LDADD = tls.so tls2.so -lpthread
+tls_so_SOURCES = tls_so.c
+tls_so_DEPENDENCIES = tls2.so
+@VGCONF_OS_IS_DARWIN_FALSE@tls_so_LDFLAGS = -Wl,-rpath,$(top_builddir)/none/tests -shared -fPIC
+@VGCONF_OS_IS_DARWIN_TRUE@tls_so_LDFLAGS = -dynamic -dynamiclib -all_load -fpic
+@VGCONF_OS_IS_DARWIN_FALSE@tls_so_LDADD = tls2.so
+@VGCONF_OS_IS_DARWIN_TRUE@tls_so_LDADD = `pwd`/tls2.so
+tls_so_CFLAGS = $(AM_CFLAGS) -fPIC
+tls2_so_SOURCES = tls2_so.c
+@VGCONF_OS_IS_DARWIN_FALSE@tls2_so_LDFLAGS = -shared
+@VGCONF_OS_IS_DARWIN_TRUE@tls2_so_LDFLAGS = -dynamic -dynamiclib -all_load
+valgrind_cpp_test_SOURCES = valgrind_cpp_test.cpp
+valgrind_cpp_test_LDADD = -lstdc++
+
+# C++ tests
+coolo_sigaction_SOURCES = coolo_sigaction.cpp
+gxx304_SOURCES = gxx304.cpp
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .cpp .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+ansi$(EXEEXT): $(ansi_OBJECTS) $(ansi_DEPENDENCIES)
+ @rm -f ansi$(EXEEXT)
+ $(ansi_LINK) $(ansi_OBJECTS) $(ansi_LDADD) $(LIBS)
+args$(EXEEXT): $(args_OBJECTS) $(args_DEPENDENCIES)
+ @rm -f args$(EXEEXT)
+ $(LINK) $(args_OBJECTS) $(args_LDADD) $(LIBS)
+async-sigs$(EXEEXT): $(async_sigs_OBJECTS) $(async_sigs_DEPENDENCIES)
+ @rm -f async-sigs$(EXEEXT)
+ $(LINK) $(async_sigs_OBJECTS) $(async_sigs_LDADD) $(LIBS)
+bitfield1$(EXEEXT): $(bitfield1_OBJECTS) $(bitfield1_DEPENDENCIES)
+ @rm -f bitfield1$(EXEEXT)
+ $(LINK) $(bitfield1_OBJECTS) $(bitfield1_LDADD) $(LIBS)
+bug129866$(EXEEXT): $(bug129866_OBJECTS) $(bug129866_DEPENDENCIES)
+ @rm -f bug129866$(EXEEXT)
+ $(LINK) $(bug129866_OBJECTS) $(bug129866_LDADD) $(LIBS)
+closeall$(EXEEXT): $(closeall_OBJECTS) $(closeall_DEPENDENCIES)
+ @rm -f closeall$(EXEEXT)
+ $(LINK) $(closeall_OBJECTS) $(closeall_LDADD) $(LIBS)
+coolo_sigaction$(EXEEXT): $(coolo_sigaction_OBJECTS) $(coolo_sigaction_DEPENDENCIES)
+ @rm -f coolo_sigaction$(EXEEXT)
+ $(CXXLINK) $(coolo_sigaction_OBJECTS) $(coolo_sigaction_LDADD) $(LIBS)
+coolo_strlen$(EXEEXT): $(coolo_strlen_OBJECTS) $(coolo_strlen_DEPENDENCIES)
+ @rm -f coolo_strlen$(EXEEXT)
+ $(LINK) $(coolo_strlen_OBJECTS) $(coolo_strlen_LDADD) $(LIBS)
+discard$(EXEEXT): $(discard_OBJECTS) $(discard_DEPENDENCIES)
+ @rm -f discard$(EXEEXT)
+ $(LINK) $(discard_OBJECTS) $(discard_LDADD) $(LIBS)
+exec-sigmask$(EXEEXT): $(exec_sigmask_OBJECTS) $(exec_sigmask_DEPENDENCIES)
+ @rm -f exec-sigmask$(EXEEXT)
+ $(LINK) $(exec_sigmask_OBJECTS) $(exec_sigmask_LDADD) $(LIBS)
+execve$(EXEEXT): $(execve_OBJECTS) $(execve_DEPENDENCIES)
+ @rm -f execve$(EXEEXT)
+ $(execve_LINK) $(execve_OBJECTS) $(execve_LDADD) $(LIBS)
+faultstatus$(EXEEXT): $(faultstatus_OBJECTS) $(faultstatus_DEPENDENCIES)
+ @rm -f faultstatus$(EXEEXT)
+ $(LINK) $(faultstatus_OBJECTS) $(faultstatus_LDADD) $(LIBS)
+fcntl_setown$(EXEEXT): $(fcntl_setown_OBJECTS) $(fcntl_setown_DEPENDENCIES)
+ @rm -f fcntl_setown$(EXEEXT)
+ $(LINK) $(fcntl_setown_OBJECTS) $(fcntl_setown_LDADD) $(LIBS)
+fdleak_cmsg$(EXEEXT): $(fdleak_cmsg_OBJECTS) $(fdleak_cmsg_DEPENDENCIES)
+ @rm -f fdleak_cmsg$(EXEEXT)
+ $(LINK) $(fdleak_cmsg_OBJECTS) $(fdleak_cmsg_LDADD) $(LIBS)
+fdleak_creat$(EXEEXT): $(fdleak_creat_OBJECTS) $(fdleak_creat_DEPENDENCIES)
+ @rm -f fdleak_creat$(EXEEXT)
+ $(LINK) $(fdleak_creat_OBJECTS) $(fdleak_creat_LDADD) $(LIBS)
+fdleak_dup$(EXEEXT): $(fdleak_dup_OBJECTS) $(fdleak_dup_DEPENDENCIES)
+ @rm -f fdleak_dup$(EXEEXT)
+ $(LINK) $(fdleak_dup_OBJECTS) $(fdleak_dup_LDADD) $(LIBS)
+fdleak_dup2$(EXEEXT): $(fdleak_dup2_OBJECTS) $(fdleak_dup2_DEPENDENCIES)
+ @rm -f fdleak_dup2$(EXEEXT)
+ $(LINK) $(fdleak_dup2_OBJECTS) $(fdleak_dup2_LDADD) $(LIBS)
+fdleak_fcntl$(EXEEXT): $(fdleak_fcntl_OBJECTS) $(fdleak_fcntl_DEPENDENCIES)
+ @rm -f fdleak_fcntl$(EXEEXT)
+ $(LINK) $(fdleak_fcntl_OBJECTS) $(fdleak_fcntl_LDADD) $(LIBS)
+fdleak_ipv4$(EXEEXT): $(fdleak_ipv4_OBJECTS) $(fdleak_ipv4_DEPENDENCIES)
+ @rm -f fdleak_ipv4$(EXEEXT)
+ $(LINK) $(fdleak_ipv4_OBJECTS) $(fdleak_ipv4_LDADD) $(LIBS)
+fdleak_open$(EXEEXT): $(fdleak_open_OBJECTS) $(fdleak_open_DEPENDENCIES)
+ @rm -f fdleak_open$(EXEEXT)
+ $(LINK) $(fdleak_open_OBJECTS) $(fdleak_open_LDADD) $(LIBS)
+fdleak_pipe$(EXEEXT): $(fdleak_pipe_OBJECTS) $(fdleak_pipe_DEPENDENCIES)
+ @rm -f fdleak_pipe$(EXEEXT)
+ $(LINK) $(fdleak_pipe_OBJECTS) $(fdleak_pipe_LDADD) $(LIBS)
+fdleak_socketpair$(EXEEXT): $(fdleak_socketpair_OBJECTS) $(fdleak_socketpair_DEPENDENCIES)
+ @rm -f fdleak_socketpair$(EXEEXT)
+ $(LINK) $(fdleak_socketpair_OBJECTS) $(fdleak_socketpair_LDADD) $(LIBS)
+floored$(EXEEXT): $(floored_OBJECTS) $(floored_DEPENDENCIES)
+ @rm -f floored$(EXEEXT)
+ $(LINK) $(floored_OBJECTS) $(floored_LDADD) $(LIBS)
+fork$(EXEEXT): $(fork_OBJECTS) $(fork_DEPENDENCIES)
+ @rm -f fork$(EXEEXT)
+ $(LINK) $(fork_OBJECTS) $(fork_LDADD) $(LIBS)
+fucomip$(EXEEXT): $(fucomip_OBJECTS) $(fucomip_DEPENDENCIES)
+ @rm -f fucomip$(EXEEXT)
+ $(LINK) $(fucomip_OBJECTS) $(fucomip_LDADD) $(LIBS)
+gxx304$(EXEEXT): $(gxx304_OBJECTS) $(gxx304_DEPENDENCIES)
+ @rm -f gxx304$(EXEEXT)
+ $(CXXLINK) $(gxx304_OBJECTS) $(gxx304_LDADD) $(LIBS)
+ifunc$(EXEEXT): $(ifunc_OBJECTS) $(ifunc_DEPENDENCIES)
+ @rm -f ifunc$(EXEEXT)
+ $(LINK) $(ifunc_OBJECTS) $(ifunc_LDADD) $(LIBS)
+manythreads$(EXEEXT): $(manythreads_OBJECTS) $(manythreads_DEPENDENCIES)
+ @rm -f manythreads$(EXEEXT)
+ $(LINK) $(manythreads_OBJECTS) $(manythreads_LDADD) $(LIBS)
+map_unaligned$(EXEEXT): $(map_unaligned_OBJECTS) $(map_unaligned_DEPENDENCIES)
+ @rm -f map_unaligned$(EXEEXT)
+ $(LINK) $(map_unaligned_OBJECTS) $(map_unaligned_LDADD) $(LIBS)
+map_unmap$(EXEEXT): $(map_unmap_OBJECTS) $(map_unmap_DEPENDENCIES)
+ @rm -f map_unmap$(EXEEXT)
+ $(LINK) $(map_unmap_OBJECTS) $(map_unmap_LDADD) $(LIBS)
+mmap_fcntl_bug$(EXEEXT): $(mmap_fcntl_bug_OBJECTS) $(mmap_fcntl_bug_DEPENDENCIES)
+ @rm -f mmap_fcntl_bug$(EXEEXT)
+ $(LINK) $(mmap_fcntl_bug_OBJECTS) $(mmap_fcntl_bug_LDADD) $(LIBS)
+mq$(EXEEXT): $(mq_OBJECTS) $(mq_DEPENDENCIES)
+ @rm -f mq$(EXEEXT)
+ $(LINK) $(mq_OBJECTS) $(mq_LDADD) $(LIBS)
+munmap_exe$(EXEEXT): $(munmap_exe_OBJECTS) $(munmap_exe_DEPENDENCIES)
+ @rm -f munmap_exe$(EXEEXT)
+ $(LINK) $(munmap_exe_OBJECTS) $(munmap_exe_LDADD) $(LIBS)
+nestedfns$(EXEEXT): $(nestedfns_OBJECTS) $(nestedfns_DEPENDENCIES)
+ @rm -f nestedfns$(EXEEXT)
+ $(nestedfns_LINK) $(nestedfns_OBJECTS) $(nestedfns_LDADD) $(LIBS)
+pending$(EXEEXT): $(pending_OBJECTS) $(pending_DEPENDENCIES)
+ @rm -f pending$(EXEEXT)
+ $(LINK) $(pending_OBJECTS) $(pending_LDADD) $(LIBS)
+process_vm_readv_writev$(EXEEXT): $(process_vm_readv_writev_OBJECTS) $(process_vm_readv_writev_DEPENDENCIES)
+ @rm -f process_vm_readv_writev$(EXEEXT)
+ $(LINK) $(process_vm_readv_writev_OBJECTS) $(process_vm_readv_writev_LDADD) $(LIBS)
+procfs-cmdline-exe$(EXEEXT): $(procfs_cmdline_exe_OBJECTS) $(procfs_cmdline_exe_DEPENDENCIES)
+ @rm -f procfs-cmdline-exe$(EXEEXT)
+ $(LINK) $(procfs_cmdline_exe_OBJECTS) $(procfs_cmdline_exe_LDADD) $(LIBS)
+pth_atfork1$(EXEEXT): $(pth_atfork1_OBJECTS) $(pth_atfork1_DEPENDENCIES)
+ @rm -f pth_atfork1$(EXEEXT)
+ $(LINK) $(pth_atfork1_OBJECTS) $(pth_atfork1_LDADD) $(LIBS)
+pth_blockedsig$(EXEEXT): $(pth_blockedsig_OBJECTS) $(pth_blockedsig_DEPENDENCIES)
+ @rm -f pth_blockedsig$(EXEEXT)
+ $(LINK) $(pth_blockedsig_OBJECTS) $(pth_blockedsig_LDADD) $(LIBS)
+pth_cancel1$(EXEEXT): $(pth_cancel1_OBJECTS) $(pth_cancel1_DEPENDENCIES)
+ @rm -f pth_cancel1$(EXEEXT)
+ $(pth_cancel1_LINK) $(pth_cancel1_OBJECTS) $(pth_cancel1_LDADD) $(LIBS)
+pth_cancel2$(EXEEXT): $(pth_cancel2_OBJECTS) $(pth_cancel2_DEPENDENCIES)
+ @rm -f pth_cancel2$(EXEEXT)
+ $(LINK) $(pth_cancel2_OBJECTS) $(pth_cancel2_LDADD) $(LIBS)
+pth_cvsimple$(EXEEXT): $(pth_cvsimple_OBJECTS) $(pth_cvsimple_DEPENDENCIES)
+ @rm -f pth_cvsimple$(EXEEXT)
+ $(LINK) $(pth_cvsimple_OBJECTS) $(pth_cvsimple_LDADD) $(LIBS)
+pth_empty$(EXEEXT): $(pth_empty_OBJECTS) $(pth_empty_DEPENDENCIES)
+ @rm -f pth_empty$(EXEEXT)
+ $(LINK) $(pth_empty_OBJECTS) $(pth_empty_LDADD) $(LIBS)
+pth_exit$(EXEEXT): $(pth_exit_OBJECTS) $(pth_exit_DEPENDENCIES)
+ @rm -f pth_exit$(EXEEXT)
+ $(LINK) $(pth_exit_OBJECTS) $(pth_exit_LDADD) $(LIBS)
+pth_exit2$(EXEEXT): $(pth_exit2_OBJECTS) $(pth_exit2_DEPENDENCIES)
+ @rm -f pth_exit2$(EXEEXT)
+ $(LINK) $(pth_exit2_OBJECTS) $(pth_exit2_LDADD) $(LIBS)
+pth_mutexspeed$(EXEEXT): $(pth_mutexspeed_OBJECTS) $(pth_mutexspeed_DEPENDENCIES)
+ @rm -f pth_mutexspeed$(EXEEXT)
+ $(LINK) $(pth_mutexspeed_OBJECTS) $(pth_mutexspeed_LDADD) $(LIBS)
+pth_once$(EXEEXT): $(pth_once_OBJECTS) $(pth_once_DEPENDENCIES)
+ @rm -f pth_once$(EXEEXT)
+ $(LINK) $(pth_once_OBJECTS) $(pth_once_LDADD) $(LIBS)
+pth_rwlock$(EXEEXT): $(pth_rwlock_OBJECTS) $(pth_rwlock_DEPENDENCIES)
+ @rm -f pth_rwlock$(EXEEXT)
+ $(LINK) $(pth_rwlock_OBJECTS) $(pth_rwlock_LDADD) $(LIBS)
+pth_stackalign$(EXEEXT): $(pth_stackalign_OBJECTS) $(pth_stackalign_DEPENDENCIES)
+ @rm -f pth_stackalign$(EXEEXT)
+ $(LINK) $(pth_stackalign_OBJECTS) $(pth_stackalign_LDADD) $(LIBS)
+rcrl$(EXEEXT): $(rcrl_OBJECTS) $(rcrl_DEPENDENCIES)
+ @rm -f rcrl$(EXEEXT)
+ $(LINK) $(rcrl_OBJECTS) $(rcrl_LDADD) $(LIBS)
+readline1$(EXEEXT): $(readline1_OBJECTS) $(readline1_DEPENDENCIES)
+ @rm -f readline1$(EXEEXT)
+ $(LINK) $(readline1_OBJECTS) $(readline1_LDADD) $(LIBS)
+require-text-symbol$(EXEEXT): $(require_text_symbol_OBJECTS) $(require_text_symbol_DEPENDENCIES)
+ @rm -f require-text-symbol$(EXEEXT)
+ $(LINK) $(require_text_symbol_OBJECTS) $(require_text_symbol_LDADD) $(LIBS)
+res_search$(EXEEXT): $(res_search_OBJECTS) $(res_search_DEPENDENCIES)
+ @rm -f res_search$(EXEEXT)
+ $(LINK) $(res_search_OBJECTS) $(res_search_LDADD) $(LIBS)
+resolv$(EXEEXT): $(resolv_OBJECTS) $(resolv_DEPENDENCIES)
+ @rm -f resolv$(EXEEXT)
+ $(LINK) $(resolv_OBJECTS) $(resolv_LDADD) $(LIBS)
+rlimit64_nofile$(EXEEXT): $(rlimit64_nofile_OBJECTS) $(rlimit64_nofile_DEPENDENCIES)
+ @rm -f rlimit64_nofile$(EXEEXT)
+ $(LINK) $(rlimit64_nofile_OBJECTS) $(rlimit64_nofile_LDADD) $(LIBS)
+rlimit_nofile$(EXEEXT): $(rlimit_nofile_OBJECTS) $(rlimit_nofile_DEPENDENCIES)
+ @rm -f rlimit_nofile$(EXEEXT)
+ $(LINK) $(rlimit_nofile_OBJECTS) $(rlimit_nofile_LDADD) $(LIBS)
+selfrun$(EXEEXT): $(selfrun_OBJECTS) $(selfrun_DEPENDENCIES)
+ @rm -f selfrun$(EXEEXT)
+ $(LINK) $(selfrun_OBJECTS) $(selfrun_LDADD) $(LIBS)
+sem$(EXEEXT): $(sem_OBJECTS) $(sem_DEPENDENCIES)
+ @rm -f sem$(EXEEXT)
+ $(LINK) $(sem_OBJECTS) $(sem_LDADD) $(LIBS)
+semlimit$(EXEEXT): $(semlimit_OBJECTS) $(semlimit_DEPENDENCIES)
+ @rm -f semlimit$(EXEEXT)
+ $(LINK) $(semlimit_OBJECTS) $(semlimit_LDADD) $(LIBS)
+sha1_test$(EXEEXT): $(sha1_test_OBJECTS) $(sha1_test_DEPENDENCIES)
+ @rm -f sha1_test$(EXEEXT)
+ $(LINK) $(sha1_test_OBJECTS) $(sha1_test_LDADD) $(LIBS)
+shortpush$(EXEEXT): $(shortpush_OBJECTS) $(shortpush_DEPENDENCIES)
+ @rm -f shortpush$(EXEEXT)
+ $(LINK) $(shortpush_OBJECTS) $(shortpush_LDADD) $(LIBS)
+shorts$(EXEEXT): $(shorts_OBJECTS) $(shorts_DEPENDENCIES)
+ @rm -f shorts$(EXEEXT)
+ $(LINK) $(shorts_OBJECTS) $(shorts_LDADD) $(LIBS)
+sigstackgrowth$(EXEEXT): $(sigstackgrowth_OBJECTS) $(sigstackgrowth_DEPENDENCIES)
+ @rm -f sigstackgrowth$(EXEEXT)
+ $(LINK) $(sigstackgrowth_OBJECTS) $(sigstackgrowth_LDADD) $(LIBS)
+stackgrowth$(EXEEXT): $(stackgrowth_OBJECTS) $(stackgrowth_DEPENDENCIES)
+ @rm -f stackgrowth$(EXEEXT)
+ $(LINK) $(stackgrowth_OBJECTS) $(stackgrowth_LDADD) $(LIBS)
+syscall-restart1$(EXEEXT): $(syscall_restart1_OBJECTS) $(syscall_restart1_DEPENDENCIES)
+ @rm -f syscall-restart1$(EXEEXT)
+ $(LINK) $(syscall_restart1_OBJECTS) $(syscall_restart1_LDADD) $(LIBS)
+syscall-restart2$(EXEEXT): $(syscall_restart2_OBJECTS) $(syscall_restart2_DEPENDENCIES)
+ @rm -f syscall-restart2$(EXEEXT)
+ $(LINK) $(syscall_restart2_OBJECTS) $(syscall_restart2_LDADD) $(LIBS)
+syslog$(EXEEXT): $(syslog_OBJECTS) $(syslog_DEPENDENCIES)
+ @rm -f syslog$(EXEEXT)
+ $(LINK) $(syslog_OBJECTS) $(syslog_LDADD) $(LIBS)
+system$(EXEEXT): $(system_OBJECTS) $(system_DEPENDENCIES)
+ @rm -f system$(EXEEXT)
+ $(LINK) $(system_OBJECTS) $(system_LDADD) $(LIBS)
+thread-exits$(EXEEXT): $(thread_exits_OBJECTS) $(thread_exits_DEPENDENCIES)
+ @rm -f thread-exits$(EXEEXT)
+ $(LINK) $(thread_exits_OBJECTS) $(thread_exits_LDADD) $(LIBS)
+threaded-fork$(EXEEXT): $(threaded_fork_OBJECTS) $(threaded_fork_DEPENDENCIES)
+ @rm -f threaded-fork$(EXEEXT)
+ $(LINK) $(threaded_fork_OBJECTS) $(threaded_fork_LDADD) $(LIBS)
+threadederrno$(EXEEXT): $(threadederrno_OBJECTS) $(threadederrno_DEPENDENCIES)
+ @rm -f threadederrno$(EXEEXT)
+ $(LINK) $(threadederrno_OBJECTS) $(threadederrno_LDADD) $(LIBS)
+timestamp$(EXEEXT): $(timestamp_OBJECTS) $(timestamp_DEPENDENCIES)
+ @rm -f timestamp$(EXEEXT)
+ $(LINK) $(timestamp_OBJECTS) $(timestamp_LDADD) $(LIBS)
+tls$(EXEEXT): $(tls_OBJECTS) $(tls_DEPENDENCIES)
+ @rm -f tls$(EXEEXT)
+ $(tls_LINK) $(tls_OBJECTS) $(tls_LDADD) $(LIBS)
+tls.so$(EXEEXT): $(tls_so_OBJECTS) $(tls_so_DEPENDENCIES)
+ @rm -f tls.so$(EXEEXT)
+ $(tls_so_LINK) $(tls_so_OBJECTS) $(tls_so_LDADD) $(LIBS)
+tls2.so$(EXEEXT): $(tls2_so_OBJECTS) $(tls2_so_DEPENDENCIES)
+ @rm -f tls2.so$(EXEEXT)
+ $(tls2_so_LINK) $(tls2_so_OBJECTS) $(tls2_so_LDADD) $(LIBS)
+valgrind_cpp_test$(EXEEXT): $(valgrind_cpp_test_OBJECTS) $(valgrind_cpp_test_DEPENDENCIES)
+ @rm -f valgrind_cpp_test$(EXEEXT)
+ $(CXXLINK) $(valgrind_cpp_test_OBJECTS) $(valgrind_cpp_test_LDADD) $(LIBS)
+vgprintf$(EXEEXT): $(vgprintf_OBJECTS) $(vgprintf_DEPENDENCIES)
+ @rm -f vgprintf$(EXEEXT)
+ $(LINK) $(vgprintf_OBJECTS) $(vgprintf_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ansi-ansi.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/args.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/async-sigs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bitfield1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug129866.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/closeall.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coolo_sigaction.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coolo_strlen.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/discard.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/exec-sigmask.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/execve-execve.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/faultstatus.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fcntl_setown.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdleak_cmsg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdleak_creat.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdleak_dup.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdleak_dup2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdleak_fcntl.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdleak_ipv4.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdleak_open.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdleak_pipe.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fdleak_socketpair.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/floored.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fork.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fucomip.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/gxx304.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ifunc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/manythreads.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/map_unaligned.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/map_unmap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mmap_fcntl_bug.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mq.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/munmap_exe.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nestedfns-nestedfns.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pending.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/process_vm_readv_writev.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/procfs-cmdline-exe.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_atfork1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_blockedsig.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_cancel1-pth_cancel1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_cancel2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_cvsimple.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_empty.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_exit.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_exit2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_mutexspeed.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_once.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_rwlock.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_stackalign.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rcrl.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/readline1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/require-text-symbol.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/res_search.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/resolv.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rlimit64_nofile.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rlimit_nofile.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/selfrun.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sem.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/semlimit.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sha1_test.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shortpush.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shorts.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigstackgrowth.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stackgrowth.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syscall-restart1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syscall-restart2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syslog.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/system.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/thread-exits.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/threaded-fork.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/threadederrno.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/timestamp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tls.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tls2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tls2_so.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tls_so-tls_so.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/valgrind_cpp_test.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vgprintf.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+ansi-ansi.o: ansi.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ansi_CFLAGS) $(CFLAGS) -MT ansi-ansi.o -MD -MP -MF $(DEPDIR)/ansi-ansi.Tpo -c -o ansi-ansi.o `test -f 'ansi.c' || echo '$(srcdir)/'`ansi.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/ansi-ansi.Tpo $(DEPDIR)/ansi-ansi.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='ansi.c' object='ansi-ansi.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ansi_CFLAGS) $(CFLAGS) -c -o ansi-ansi.o `test -f 'ansi.c' || echo '$(srcdir)/'`ansi.c
+
+ansi-ansi.obj: ansi.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ansi_CFLAGS) $(CFLAGS) -MT ansi-ansi.obj -MD -MP -MF $(DEPDIR)/ansi-ansi.Tpo -c -o ansi-ansi.obj `if test -f 'ansi.c'; then $(CYGPATH_W) 'ansi.c'; else $(CYGPATH_W) '$(srcdir)/ansi.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/ansi-ansi.Tpo $(DEPDIR)/ansi-ansi.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='ansi.c' object='ansi-ansi.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ansi_CFLAGS) $(CFLAGS) -c -o ansi-ansi.obj `if test -f 'ansi.c'; then $(CYGPATH_W) 'ansi.c'; else $(CYGPATH_W) '$(srcdir)/ansi.c'; fi`
+
+execve-execve.o: execve.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve_CFLAGS) $(CFLAGS) -MT execve-execve.o -MD -MP -MF $(DEPDIR)/execve-execve.Tpo -c -o execve-execve.o `test -f 'execve.c' || echo '$(srcdir)/'`execve.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/execve-execve.Tpo $(DEPDIR)/execve-execve.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='execve.c' object='execve-execve.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve_CFLAGS) $(CFLAGS) -c -o execve-execve.o `test -f 'execve.c' || echo '$(srcdir)/'`execve.c
+
+execve-execve.obj: execve.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve_CFLAGS) $(CFLAGS) -MT execve-execve.obj -MD -MP -MF $(DEPDIR)/execve-execve.Tpo -c -o execve-execve.obj `if test -f 'execve.c'; then $(CYGPATH_W) 'execve.c'; else $(CYGPATH_W) '$(srcdir)/execve.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/execve-execve.Tpo $(DEPDIR)/execve-execve.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='execve.c' object='execve-execve.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(execve_CFLAGS) $(CFLAGS) -c -o execve-execve.obj `if test -f 'execve.c'; then $(CYGPATH_W) 'execve.c'; else $(CYGPATH_W) '$(srcdir)/execve.c'; fi`
+
+nestedfns-nestedfns.o: nestedfns.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(nestedfns_CFLAGS) $(CFLAGS) -MT nestedfns-nestedfns.o -MD -MP -MF $(DEPDIR)/nestedfns-nestedfns.Tpo -c -o nestedfns-nestedfns.o `test -f 'nestedfns.c' || echo '$(srcdir)/'`nestedfns.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/nestedfns-nestedfns.Tpo $(DEPDIR)/nestedfns-nestedfns.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='nestedfns.c' object='nestedfns-nestedfns.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(nestedfns_CFLAGS) $(CFLAGS) -c -o nestedfns-nestedfns.o `test -f 'nestedfns.c' || echo '$(srcdir)/'`nestedfns.c
+
+nestedfns-nestedfns.obj: nestedfns.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(nestedfns_CFLAGS) $(CFLAGS) -MT nestedfns-nestedfns.obj -MD -MP -MF $(DEPDIR)/nestedfns-nestedfns.Tpo -c -o nestedfns-nestedfns.obj `if test -f 'nestedfns.c'; then $(CYGPATH_W) 'nestedfns.c'; else $(CYGPATH_W) '$(srcdir)/nestedfns.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/nestedfns-nestedfns.Tpo $(DEPDIR)/nestedfns-nestedfns.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='nestedfns.c' object='nestedfns-nestedfns.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(nestedfns_CFLAGS) $(CFLAGS) -c -o nestedfns-nestedfns.obj `if test -f 'nestedfns.c'; then $(CYGPATH_W) 'nestedfns.c'; else $(CYGPATH_W) '$(srcdir)/nestedfns.c'; fi`
+
+pth_cancel1-pth_cancel1.o: pth_cancel1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pth_cancel1_CFLAGS) $(CFLAGS) -MT pth_cancel1-pth_cancel1.o -MD -MP -MF $(DEPDIR)/pth_cancel1-pth_cancel1.Tpo -c -o pth_cancel1-pth_cancel1.o `test -f 'pth_cancel1.c' || echo '$(srcdir)/'`pth_cancel1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/pth_cancel1-pth_cancel1.Tpo $(DEPDIR)/pth_cancel1-pth_cancel1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pth_cancel1.c' object='pth_cancel1-pth_cancel1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pth_cancel1_CFLAGS) $(CFLAGS) -c -o pth_cancel1-pth_cancel1.o `test -f 'pth_cancel1.c' || echo '$(srcdir)/'`pth_cancel1.c
+
+pth_cancel1-pth_cancel1.obj: pth_cancel1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pth_cancel1_CFLAGS) $(CFLAGS) -MT pth_cancel1-pth_cancel1.obj -MD -MP -MF $(DEPDIR)/pth_cancel1-pth_cancel1.Tpo -c -o pth_cancel1-pth_cancel1.obj `if test -f 'pth_cancel1.c'; then $(CYGPATH_W) 'pth_cancel1.c'; else $(CYGPATH_W) '$(srcdir)/pth_cancel1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/pth_cancel1-pth_cancel1.Tpo $(DEPDIR)/pth_cancel1-pth_cancel1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='pth_cancel1.c' object='pth_cancel1-pth_cancel1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(pth_cancel1_CFLAGS) $(CFLAGS) -c -o pth_cancel1-pth_cancel1.obj `if test -f 'pth_cancel1.c'; then $(CYGPATH_W) 'pth_cancel1.c'; else $(CYGPATH_W) '$(srcdir)/pth_cancel1.c'; fi`
+
+tls_so-tls_so.o: tls_so.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tls_so_CFLAGS) $(CFLAGS) -MT tls_so-tls_so.o -MD -MP -MF $(DEPDIR)/tls_so-tls_so.Tpo -c -o tls_so-tls_so.o `test -f 'tls_so.c' || echo '$(srcdir)/'`tls_so.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tls_so-tls_so.Tpo $(DEPDIR)/tls_so-tls_so.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='tls_so.c' object='tls_so-tls_so.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tls_so_CFLAGS) $(CFLAGS) -c -o tls_so-tls_so.o `test -f 'tls_so.c' || echo '$(srcdir)/'`tls_so.c
+
+tls_so-tls_so.obj: tls_so.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tls_so_CFLAGS) $(CFLAGS) -MT tls_so-tls_so.obj -MD -MP -MF $(DEPDIR)/tls_so-tls_so.Tpo -c -o tls_so-tls_so.obj `if test -f 'tls_so.c'; then $(CYGPATH_W) 'tls_so.c'; else $(CYGPATH_W) '$(srcdir)/tls_so.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tls_so-tls_so.Tpo $(DEPDIR)/tls_so-tls_so.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='tls_so.c' object='tls_so-tls_so.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tls_so_CFLAGS) $(CFLAGS) -c -o tls_so-tls_so.obj `if test -f 'tls_so.c'; then $(CYGPATH_W) 'tls_so.c'; else $(CYGPATH_W) '$(srcdir)/tls_so.c'; fi`
+
+.cpp.o:
+@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ $<
+
+.cpp.obj:
+@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+# This directory's subdirectories are mostly independent; you can cd
+# into them and run `make' without going through this Makefile.
+# To change the values of `make' variables: instead of editing Makefiles,
+# (1) if the variable is set in `config.status', edit `config.status'
+# (which will cause the Makefiles to be regenerated when you run `make');
+# (2) otherwise, pass the desired values on the `make' command line.
+$(RECURSIVE_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ target=`echo $@ | sed s/-recursive//`; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ dot_seen=yes; \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done; \
+ if test "$$dot_seen" = "no"; then \
+ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+ fi; test -z "$$fail"
+
+$(RECURSIVE_CLEAN_TARGETS):
+ @fail= failcom='exit 1'; \
+ for f in x $$MAKEFLAGS; do \
+ case $$f in \
+ *=* | --[!k]*);; \
+ *k*) failcom='fail=yes';; \
+ esac; \
+ done; \
+ dot_seen=no; \
+ case "$@" in \
+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
+ *) list='$(SUBDIRS)' ;; \
+ esac; \
+ rev=''; for subdir in $$list; do \
+ if test "$$subdir" = "."; then :; else \
+ rev="$$subdir $$rev"; \
+ fi; \
+ done; \
+ rev="$$rev ."; \
+ target=`echo $@ | sed s/-recursive//`; \
+ for subdir in $$rev; do \
+ echo "Making $$target in $$subdir"; \
+ if test "$$subdir" = "."; then \
+ local_target="$$target-am"; \
+ else \
+ local_target="$$target"; \
+ fi; \
+ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+ || eval $$failcom; \
+ done && test -z "$$fail"
+tags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \
+ done
+ctags-recursive:
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \
+ done
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \
+ include_option=--etags-include; \
+ empty_fix=.; \
+ else \
+ include_option=--include; \
+ empty_fix=; \
+ fi; \
+ list='$(SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test ! -f $$subdir/TAGS || \
+ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \
+ fi; \
+ done; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ test -d "$(distdir)/$$subdir" \
+ || $(MKDIR_P) "$(distdir)/$$subdir" \
+ || exit 1; \
+ fi; \
+ done
+ @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
+ if test "$$subdir" = .; then :; else \
+ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \
+ $(am__relativize); \
+ new_distdir=$$reldir; \
+ dir1=$$subdir; dir2="$(top_distdir)"; \
+ $(am__relativize); \
+ new_top_distdir=$$reldir; \
+ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \
+ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \
+ ($(am__cd) $$subdir && \
+ $(MAKE) $(AM_MAKEFLAGS) \
+ top_distdir="$$new_top_distdir" \
+ distdir="$$new_distdir" \
+ am__remove_distdir=: \
+ am__skip_length_check=: \
+ am__skip_mode_fix=: \
+ distdir) \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-recursive
+all-am: Makefile $(SCRIPTS) $(HEADERS)
+installdirs: installdirs-recursive
+installdirs-am:
+install: install-recursive
+install-exec: install-exec-recursive
+install-data: install-data-recursive
+uninstall: uninstall-recursive
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-recursive
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-recursive
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-recursive
+
+dvi-am:
+
+html: html-recursive
+
+html-am:
+
+info: info-recursive
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-recursive
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-recursive
+
+install-html-am:
+
+install-info: install-info-recursive
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-recursive
+
+install-pdf-am:
+
+install-ps: install-ps-recursive
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-recursive
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-recursive
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-recursive
+
+pdf-am:
+
+ps: ps-recursive
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) check-am \
+ ctags-recursive install-am install-strip tags-recursive
+
+.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
+ all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags \
+ ctags-recursive distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ installdirs-am maintainer-clean maintainer-clean-generic \
+ mostlyclean mostlyclean-compile mostlyclean-generic pdf pdf-am \
+ ps ps-am tags tags-recursive uninstall uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/allexec32.stderr.exp b/main/none/tests/allexec32.stderr.exp
new file mode 100644
index 0000000..5cf5d3d
--- /dev/null
+++ b/main/none/tests/allexec32.stderr.exp
@@ -0,0 +1,14 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/main/none/tests/allexec32.stdout.exp b/main/none/tests/allexec32.stdout.exp
new file mode 100644
index 0000000..c6d7337
--- /dev/null
+++ b/main/none/tests/allexec32.stdout.exp
@@ -0,0 +1,14 @@
+./allexec32 will exec ./allexec32
+program exec-ed: ./allexec32
+child exited
+program exec-ed: ./allexec32 constant_arg1 constant_arg2
+child exited
+program exec-ed: ./allexec32
+child exited
+./allexec32 will exec ./allexec64
+program exec-ed: ./allexec64
+child exited
+program exec-ed: ./allexec64 constant_arg1 constant_arg2
+child exited
+program exec-ed: ./allexec64
+child exited
diff --git a/main/none/tests/allexec32.vgtest b/main/none/tests/allexec32.vgtest
new file mode 100644
index 0000000..7fb1249
--- /dev/null
+++ b/main/none/tests/allexec32.vgtest
@@ -0,0 +1,4 @@
+prog: allexec32
+args: exec
+vgopts: --trace-children=yes
+prereq: ./allexec_prepare_prereq
diff --git a/main/none/tests/allexec64.stderr.exp b/main/none/tests/allexec64.stderr.exp
new file mode 100644
index 0000000..5cf5d3d
--- /dev/null
+++ b/main/none/tests/allexec64.stderr.exp
@@ -0,0 +1,14 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/main/none/tests/allexec64.stdout.exp b/main/none/tests/allexec64.stdout.exp
new file mode 100644
index 0000000..865cea0
--- /dev/null
+++ b/main/none/tests/allexec64.stdout.exp
@@ -0,0 +1,14 @@
+./allexec64 will exec ./allexec32
+program exec-ed: ./allexec32
+child exited
+program exec-ed: ./allexec32 constant_arg1 constant_arg2
+child exited
+program exec-ed: ./allexec32
+child exited
+./allexec64 will exec ./allexec64
+program exec-ed: ./allexec64
+child exited
+program exec-ed: ./allexec64 constant_arg1 constant_arg2
+child exited
+program exec-ed: ./allexec64
+child exited
diff --git a/main/none/tests/allexec64.vgtest b/main/none/tests/allexec64.vgtest
new file mode 100644
index 0000000..2cbf113
--- /dev/null
+++ b/main/none/tests/allexec64.vgtest
@@ -0,0 +1,4 @@
+prog: allexec64
+args: exec
+vgopts: --trace-children=yes
+prereq: ./allexec_prepare_prereq
diff --git a/main/none/tests/allexec_prepare_prereq b/main/none/tests/allexec_prepare_prereq
new file mode 100755
index 0000000..d1fa03c
--- /dev/null
+++ b/main/none/tests/allexec_prepare_prereq
@@ -0,0 +1,37 @@
+#! /bin/sh
+
+# prepare the hard or soft link allexec32 and allexec64
+# On 'single arch' compiled Valgrind, allexec32 and allexec64 will point
+# to the same executable.
+# On 'bi-arch', they will point respectively to the executable compiled
+# for the revelant arch.
+# This allows to test the various exec system calls the same way.
+
+
+pair()
+{
+ if ../../tests/arch_test $1 || ../../tests/arch_test $2
+ then
+ if ../../tests/arch_test $1
+ then
+ ln -f $1/allexec allexec32
+ else
+ ln -f -s allexec64 allexec32
+ fi
+ if ../../tests/arch_test $2
+ then
+ ln -f $2/allexec allexec64
+ else
+ ln -f -s allexec32 allexec64
+ fi
+ fi
+}
+
+
+pair x86 amd64
+pair ppc32 ppc64
+pair s390x_unexisting_in_32bits s390x
+pair arm arm_unexisting_in_64bits
+pair mips32 mips_unexisting_in_64bits
+
+exit 0
diff --git a/main/none/tests/amd64/Makefile.am b/main/none/tests/amd64/Makefile.am
index f192645..a3b9686 100644
--- a/main/none/tests/amd64/Makefile.am
+++ b/main/none/tests/amd64/Makefile.am
@@ -13,7 +13,7 @@
INSN_TESTS += insn_ssse3
endif
if BUILD_PCLMULQDQ_TESTS
-INSN_TESTS += insn_pclmulqdq
+ INSN_TESTS += insn_pclmulqdq
endif
# Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS,
@@ -21,7 +21,9 @@
# which failed the BUILD_SSE3_TESTS test in configure.in.
EXTRA_DIST = \
+ aes.vgtest aes.stdout.exp aes.stderr.exp \
amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \
+ avx-1.vgtest avx-1.stdout.exp avx-1.stderr.exp \
asorep.stderr.exp asorep.stdout.exp asorep.vgtest \
bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \
bug132813-amd64.vgtest bug132813-amd64.stdout.exp \
@@ -50,12 +52,18 @@
looper.stderr.exp looper.stdout.exp looper.vgtest \
loopnel.stderr.exp loopnel.stdout.exp loopnel.vgtest \
lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \
+ movbe.stderr.exp movbe.stdout.exp movbe.vgtest \
+ nan80and64.stderr.exp nan80and64.stdout.exp nan80and64.vgtest \
nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \
nibz_bennee_mmap.vgtest \
pcmpstr64.stderr.exp pcmpstr64.stdout.exp \
pcmpstr64.vgtest \
+ pcmpstr64w.stderr.exp pcmpstr64w.stdout.exp \
+ pcmpstr64w.vgtest \
pcmpxstrx64.stderr.exp pcmpxstrx64.stdout.exp \
pcmpxstrx64.vgtest \
+ pcmpxstrx64w.stderr.exp pcmpxstrx64w.stdout.exp \
+ pcmpxstrx64w.vgtest \
rcl-amd64.vgtest rcl-amd64.stdout.exp rcl-amd64.stderr.exp \
redundantRexW.vgtest redundantRexW.stdout.exp \
redundantRexW.stderr.exp \
@@ -71,12 +79,14 @@
xadd.stderr.exp xadd.stdout.exp xadd.vgtest
check_PROGRAMS = \
+ allexec \
amd64locked \
asorep \
bug127521-64 bug132813-amd64 bug132918 \
clc \
cmpxchg \
$(INSN_TESTS) \
+ nan80and64 \
rcl-amd64 \
redundantRexW \
smc1 \
@@ -90,7 +100,17 @@
check_PROGRAMS += lzcnt64
endif
if BUILD_SSE42_TESTS
- check_PROGRAMS += pcmpstr64 pcmpxstrx64 sse4-64 crc32
+ check_PROGRAMS += \
+ pcmpstr64 pcmpxstrx64 sse4-64 crc32 aes \
+ pcmpstr64w pcmpxstrx64w
+endif
+if BUILD_AVX_TESTS
+if BUILD_VPCLMULQDQ_TESTS
+ check_PROGRAMS += avx-1
+endif
+endif
+if BUILD_MOVBE_TESTS
+ check_PROGRAMS += movbe
endif
# DDD: these need to be made to work on Darwin like the x86/ ones were.
@@ -112,6 +132,8 @@
AM_CXXFLAGS += @FLAG_M64@
AM_CCASFLAGS += @FLAG_M64@
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+
# generic C ones
amd64locked_CFLAGS = $(AM_CFLAGS) -O
bug132918_LDADD = -lm
@@ -130,6 +152,7 @@
insn_ssse3_LDADD = -lm
insn_fpu_SOURCES = insn_fpu.def
insn_fpu_LDADD = -lm
+insn_pclmulqdq_SOURCES = insn_pclmulqdq.def
fxtract_LDADD = -lm
.def.c: $(srcdir)/gen_insn_test.pl
diff --git a/main/none/tests/amd64/Makefile.in b/main/none/tests/amd64/Makefile.in
new file mode 100644
index 0000000..02f3c36
--- /dev/null
+++ b/main/none/tests/amd64/Makefile.in
@@ -0,0 +1,1207 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+@BUILD_SSE3_TESTS_TRUE@am__append_3 = insn_sse3
+@BUILD_SSSE3_TESTS_TRUE@am__append_4 = insn_ssse3
+@BUILD_PCLMULQDQ_TESTS_TRUE@am__append_5 = insn_pclmulqdq
+check_PROGRAMS = allexec$(EXEEXT) amd64locked$(EXEEXT) asorep$(EXEEXT) \
+ bug127521-64$(EXEEXT) bug132813-amd64$(EXEEXT) \
+ bug132918$(EXEEXT) clc$(EXEEXT) cmpxchg$(EXEEXT) \
+ $(am__EXEEXT_4) nan80and64$(EXEEXT) rcl-amd64$(EXEEXT) \
+ redundantRexW$(EXEEXT) smc1$(EXEEXT) sbbmisc$(EXEEXT) \
+ nibz_bennee_mmap$(EXEEXT) xadd$(EXEEXT) $(am__EXEEXT_5) \
+ $(am__EXEEXT_6) $(am__EXEEXT_7) $(am__EXEEXT_8) \
+ $(am__EXEEXT_9) $(am__EXEEXT_10)
+@BUILD_SSSE3_TESTS_TRUE@am__append_6 = ssse3_misaligned
+@BUILD_LZCNT_TESTS_TRUE@am__append_7 = lzcnt64
+@BUILD_SSE42_TESTS_TRUE@am__append_8 = \
+@BUILD_SSE42_TESTS_TRUE@ pcmpstr64 pcmpxstrx64 sse4-64 crc32 aes \
+@BUILD_SSE42_TESTS_TRUE@ pcmpstr64w pcmpxstrx64w
+
+@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__append_9 = avx-1
+@BUILD_MOVBE_TESTS_TRUE@am__append_10 = movbe
+
+# DDD: these need to be made to work on Darwin like the x86/ ones were.
+@VGCONF_OS_IS_DARWIN_FALSE@am__append_11 = \
+@VGCONF_OS_IS_DARWIN_FALSE@ bug137714-amd64 \
+@VGCONF_OS_IS_DARWIN_FALSE@ bug156404-amd64 \
+@VGCONF_OS_IS_DARWIN_FALSE@ faultstatus \
+@VGCONF_OS_IS_DARWIN_FALSE@ fcmovnu \
+@VGCONF_OS_IS_DARWIN_FALSE@ fxtract \
+@VGCONF_OS_IS_DARWIN_FALSE@ looper \
+@VGCONF_OS_IS_DARWIN_FALSE@ loopnel \
+@VGCONF_OS_IS_DARWIN_FALSE@ jrcxz \
+@VGCONF_OS_IS_DARWIN_FALSE@ shrld \
+@VGCONF_OS_IS_DARWIN_FALSE@ slahf-amd64
+
+subdir = none/tests/amd64
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@BUILD_SSE3_TESTS_TRUE@am__EXEEXT_1 = insn_sse3$(EXEEXT)
+@BUILD_SSSE3_TESTS_TRUE@am__EXEEXT_2 = insn_ssse3$(EXEEXT)
+@BUILD_PCLMULQDQ_TESTS_TRUE@am__EXEEXT_3 = insn_pclmulqdq$(EXEEXT)
+am__EXEEXT_4 = insn_basic$(EXEEXT) insn_mmx$(EXEEXT) insn_sse$(EXEEXT) \
+ insn_sse2$(EXEEXT) insn_fpu$(EXEEXT) $(am__EXEEXT_1) \
+ $(am__EXEEXT_2) $(am__EXEEXT_3)
+@BUILD_SSSE3_TESTS_TRUE@am__EXEEXT_5 = ssse3_misaligned$(EXEEXT)
+@BUILD_LZCNT_TESTS_TRUE@am__EXEEXT_6 = lzcnt64$(EXEEXT)
+@BUILD_SSE42_TESTS_TRUE@am__EXEEXT_7 = pcmpstr64$(EXEEXT) \
+@BUILD_SSE42_TESTS_TRUE@ pcmpxstrx64$(EXEEXT) sse4-64$(EXEEXT) \
+@BUILD_SSE42_TESTS_TRUE@ crc32$(EXEEXT) aes$(EXEEXT) \
+@BUILD_SSE42_TESTS_TRUE@ pcmpstr64w$(EXEEXT) \
+@BUILD_SSE42_TESTS_TRUE@ pcmpxstrx64w$(EXEEXT)
+@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__EXEEXT_8 = avx-1$(EXEEXT)
+@BUILD_MOVBE_TESTS_TRUE@am__EXEEXT_9 = movbe$(EXEEXT)
+@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_10 = bug137714-amd64$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ bug156404-amd64$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ faultstatus$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ fcmovnu$(EXEEXT) fxtract$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ looper$(EXEEXT) loopnel$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ jrcxz$(EXEEXT) shrld$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ slahf-amd64$(EXEEXT)
+aes_SOURCES = aes.c
+aes_OBJECTS = aes.$(OBJEXT)
+aes_LDADD = $(LDADD)
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+amd64locked_SOURCES = amd64locked.c
+amd64locked_OBJECTS = amd64locked-amd64locked.$(OBJEXT)
+amd64locked_LDADD = $(LDADD)
+amd64locked_LINK = $(CCLD) $(amd64locked_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+asorep_SOURCES = asorep.c
+asorep_OBJECTS = asorep.$(OBJEXT)
+asorep_LDADD = $(LDADD)
+avx_1_SOURCES = avx-1.c
+avx_1_OBJECTS = avx-1.$(OBJEXT)
+avx_1_LDADD = $(LDADD)
+bug127521_64_SOURCES = bug127521-64.c
+bug127521_64_OBJECTS = bug127521-64.$(OBJEXT)
+bug127521_64_LDADD = $(LDADD)
+bug132813_amd64_SOURCES = bug132813-amd64.c
+bug132813_amd64_OBJECTS = bug132813-amd64.$(OBJEXT)
+bug132813_amd64_LDADD = $(LDADD)
+bug132918_SOURCES = bug132918.c
+bug132918_OBJECTS = bug132918.$(OBJEXT)
+bug132918_DEPENDENCIES =
+bug137714_amd64_SOURCES = bug137714-amd64.c
+bug137714_amd64_OBJECTS = bug137714-amd64.$(OBJEXT)
+bug137714_amd64_LDADD = $(LDADD)
+bug156404_amd64_SOURCES = bug156404-amd64.c
+bug156404_amd64_OBJECTS = bug156404-amd64.$(OBJEXT)
+bug156404_amd64_LDADD = $(LDADD)
+clc_SOURCES = clc.c
+clc_OBJECTS = clc.$(OBJEXT)
+clc_LDADD = $(LDADD)
+cmpxchg_SOURCES = cmpxchg.c
+cmpxchg_OBJECTS = cmpxchg.$(OBJEXT)
+cmpxchg_LDADD = $(LDADD)
+crc32_SOURCES = crc32.c
+crc32_OBJECTS = crc32.$(OBJEXT)
+crc32_LDADD = $(LDADD)
+faultstatus_SOURCES = faultstatus.c
+faultstatus_OBJECTS = faultstatus.$(OBJEXT)
+faultstatus_LDADD = $(LDADD)
+fcmovnu_SOURCES = fcmovnu.c
+fcmovnu_OBJECTS = fcmovnu.$(OBJEXT)
+fcmovnu_LDADD = $(LDADD)
+fxtract_SOURCES = fxtract.c
+fxtract_OBJECTS = fxtract-fxtract.$(OBJEXT)
+fxtract_DEPENDENCIES =
+fxtract_LINK = $(CCLD) $(fxtract_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am_insn_basic_OBJECTS = insn_basic.$(OBJEXT)
+insn_basic_OBJECTS = $(am_insn_basic_OBJECTS)
+insn_basic_DEPENDENCIES =
+am_insn_fpu_OBJECTS = insn_fpu.$(OBJEXT)
+insn_fpu_OBJECTS = $(am_insn_fpu_OBJECTS)
+insn_fpu_DEPENDENCIES =
+am_insn_mmx_OBJECTS = insn_mmx.$(OBJEXT)
+insn_mmx_OBJECTS = $(am_insn_mmx_OBJECTS)
+insn_mmx_DEPENDENCIES =
+am_insn_pclmulqdq_OBJECTS = insn_pclmulqdq.$(OBJEXT)
+insn_pclmulqdq_OBJECTS = $(am_insn_pclmulqdq_OBJECTS)
+insn_pclmulqdq_LDADD = $(LDADD)
+am_insn_sse_OBJECTS = insn_sse.$(OBJEXT)
+insn_sse_OBJECTS = $(am_insn_sse_OBJECTS)
+insn_sse_DEPENDENCIES =
+am_insn_sse2_OBJECTS = insn_sse2.$(OBJEXT)
+insn_sse2_OBJECTS = $(am_insn_sse2_OBJECTS)
+insn_sse2_DEPENDENCIES =
+am_insn_sse3_OBJECTS = insn_sse3.$(OBJEXT)
+insn_sse3_OBJECTS = $(am_insn_sse3_OBJECTS)
+insn_sse3_DEPENDENCIES =
+am_insn_ssse3_OBJECTS = insn_ssse3.$(OBJEXT)
+insn_ssse3_OBJECTS = $(am_insn_ssse3_OBJECTS)
+insn_ssse3_DEPENDENCIES =
+jrcxz_SOURCES = jrcxz.c
+jrcxz_OBJECTS = jrcxz.$(OBJEXT)
+jrcxz_LDADD = $(LDADD)
+looper_SOURCES = looper.c
+looper_OBJECTS = looper.$(OBJEXT)
+looper_LDADD = $(LDADD)
+loopnel_SOURCES = loopnel.c
+loopnel_OBJECTS = loopnel.$(OBJEXT)
+loopnel_LDADD = $(LDADD)
+lzcnt64_SOURCES = lzcnt64.c
+lzcnt64_OBJECTS = lzcnt64.$(OBJEXT)
+lzcnt64_LDADD = $(LDADD)
+movbe_SOURCES = movbe.c
+movbe_OBJECTS = movbe.$(OBJEXT)
+movbe_LDADD = $(LDADD)
+nan80and64_SOURCES = nan80and64.c
+nan80and64_OBJECTS = nan80and64.$(OBJEXT)
+nan80and64_LDADD = $(LDADD)
+nibz_bennee_mmap_SOURCES = nibz_bennee_mmap.c
+nibz_bennee_mmap_OBJECTS = nibz_bennee_mmap.$(OBJEXT)
+nibz_bennee_mmap_LDADD = $(LDADD)
+pcmpstr64_SOURCES = pcmpstr64.c
+pcmpstr64_OBJECTS = pcmpstr64.$(OBJEXT)
+pcmpstr64_LDADD = $(LDADD)
+pcmpstr64w_SOURCES = pcmpstr64w.c
+pcmpstr64w_OBJECTS = pcmpstr64w.$(OBJEXT)
+pcmpstr64w_LDADD = $(LDADD)
+pcmpxstrx64_SOURCES = pcmpxstrx64.c
+pcmpxstrx64_OBJECTS = pcmpxstrx64.$(OBJEXT)
+pcmpxstrx64_LDADD = $(LDADD)
+pcmpxstrx64w_SOURCES = pcmpxstrx64w.c
+pcmpxstrx64w_OBJECTS = pcmpxstrx64w.$(OBJEXT)
+pcmpxstrx64w_LDADD = $(LDADD)
+rcl_amd64_SOURCES = rcl-amd64.c
+rcl_amd64_OBJECTS = rcl-amd64.$(OBJEXT)
+rcl_amd64_LDADD = $(LDADD)
+redundantRexW_SOURCES = redundantRexW.c
+redundantRexW_OBJECTS = redundantRexW.$(OBJEXT)
+redundantRexW_LDADD = $(LDADD)
+sbbmisc_SOURCES = sbbmisc.c
+sbbmisc_OBJECTS = sbbmisc.$(OBJEXT)
+sbbmisc_LDADD = $(LDADD)
+shrld_SOURCES = shrld.c
+shrld_OBJECTS = shrld.$(OBJEXT)
+shrld_LDADD = $(LDADD)
+slahf_amd64_SOURCES = slahf-amd64.c
+slahf_amd64_OBJECTS = slahf-amd64.$(OBJEXT)
+slahf_amd64_LDADD = $(LDADD)
+smc1_SOURCES = smc1.c
+smc1_OBJECTS = smc1.$(OBJEXT)
+smc1_LDADD = $(LDADD)
+sse4_64_SOURCES = sse4-64.c
+sse4_64_OBJECTS = sse4-64.$(OBJEXT)
+sse4_64_LDADD = $(LDADD)
+ssse3_misaligned_SOURCES = ssse3_misaligned.c
+ssse3_misaligned_OBJECTS = ssse3_misaligned.$(OBJEXT)
+ssse3_misaligned_LDADD = $(LDADD)
+xadd_SOURCES = xadd.c
+xadd_OBJECTS = xadd.$(OBJEXT)
+xadd_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = aes.c allexec.c amd64locked.c asorep.c avx-1.c \
+ bug127521-64.c bug132813-amd64.c bug132918.c bug137714-amd64.c \
+ bug156404-amd64.c clc.c cmpxchg.c crc32.c faultstatus.c \
+ fcmovnu.c fxtract.c $(insn_basic_SOURCES) $(insn_fpu_SOURCES) \
+ $(insn_mmx_SOURCES) $(insn_pclmulqdq_SOURCES) \
+ $(insn_sse_SOURCES) $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
+ $(insn_ssse3_SOURCES) jrcxz.c looper.c loopnel.c lzcnt64.c \
+ movbe.c nan80and64.c nibz_bennee_mmap.c pcmpstr64.c \
+ pcmpstr64w.c pcmpxstrx64.c pcmpxstrx64w.c rcl-amd64.c \
+ redundantRexW.c sbbmisc.c shrld.c slahf-amd64.c smc1.c \
+ sse4-64.c ssse3_misaligned.c xadd.c
+DIST_SOURCES = aes.c allexec.c amd64locked.c asorep.c avx-1.c \
+ bug127521-64.c bug132813-amd64.c bug132918.c bug137714-amd64.c \
+ bug156404-amd64.c clc.c cmpxchg.c crc32.c faultstatus.c \
+ fcmovnu.c fxtract.c $(insn_basic_SOURCES) $(insn_fpu_SOURCES) \
+ $(insn_mmx_SOURCES) $(insn_pclmulqdq_SOURCES) \
+ $(insn_sse_SOURCES) $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
+ $(insn_ssse3_SOURCES) jrcxz.c looper.c loopnel.c lzcnt64.c \
+ movbe.c nan80and64.c nibz_bennee_mmap.c pcmpstr64.c \
+ pcmpstr64w.c pcmpxstrx64.c pcmpxstrx64w.c rcl-amd64.c \
+ redundantRexW.c sbbmisc.c shrld.c slahf-amd64.c smc1.c \
+ sse4-64.c ssse3_misaligned.c xadd.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_cpuid filter_stderr gen_insn_test.pl
+CLEANFILES = $(addsuffix .c,$(INSN_TESTS))
+INSN_TESTS = insn_basic insn_mmx insn_sse insn_sse2 insn_fpu \
+ $(am__append_3) $(am__append_4) $(am__append_5)
+
+# Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS,
+# to avoid packaging screwups if 'make dist' is run on a machine
+# which failed the BUILD_SSE3_TESTS test in configure.in.
+EXTRA_DIST = \
+ aes.vgtest aes.stdout.exp aes.stderr.exp \
+ amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \
+ avx-1.vgtest avx-1.stdout.exp avx-1.stderr.exp \
+ asorep.stderr.exp asorep.stdout.exp asorep.vgtest \
+ bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \
+ bug132813-amd64.vgtest bug132813-amd64.stdout.exp \
+ bug132813-amd64.stderr.exp \
+ bug137714-amd64.vgtest bug137714-amd64.stdout.exp \
+ bug137714-amd64.stderr.exp \
+ bug132918.vgtest bug132918.stderr.exp bug132918.stdout.exp \
+ bug132918.stdout.exp-older-glibc \
+ bug156404-amd64.vgtest bug156404-amd64.stdout.exp \
+ bug156404-amd64.stderr.exp \
+ clc.vgtest clc.stdout.exp clc.stderr.exp \
+ crc32.vgtest crc32.stdout.exp crc32.stderr.exp \
+ cmpxchg.vgtest cmpxchg.stdout.exp cmpxchg.stderr.exp \
+ faultstatus.disabled faultstatus.stderr.exp \
+ fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \
+ fxtract.vgtest fxtract.stderr.exp fxtract.stdout.exp \
+ fxtract.stdout.exp-older-glibc \
+ $(addsuffix .stderr.exp,$(INSN_TESTS)) \
+ $(addsuffix .stdout.exp,$(INSN_TESTS)) \
+ $(addsuffix .vgtest,$(INSN_TESTS)) \
+ insn_pclmulqdq.vgtest insn_pclmulqdq.stdout.exp \
+ insn_pclmulqdq.stderr.exp \
+ insn_sse3.stdout.exp insn_sse3.stderr.exp insn_sse3.vgtest \
+ insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
+ jrcxz.stderr.exp jrcxz.stdout.exp jrcxz.vgtest \
+ looper.stderr.exp looper.stdout.exp looper.vgtest \
+ loopnel.stderr.exp loopnel.stdout.exp loopnel.vgtest \
+ lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \
+ movbe.stderr.exp movbe.stdout.exp movbe.vgtest \
+ nan80and64.stderr.exp nan80and64.stdout.exp nan80and64.vgtest \
+ nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \
+ nibz_bennee_mmap.vgtest \
+ pcmpstr64.stderr.exp pcmpstr64.stdout.exp \
+ pcmpstr64.vgtest \
+ pcmpstr64w.stderr.exp pcmpstr64w.stdout.exp \
+ pcmpstr64w.vgtest \
+ pcmpxstrx64.stderr.exp pcmpxstrx64.stdout.exp \
+ pcmpxstrx64.vgtest \
+ pcmpxstrx64w.stderr.exp pcmpxstrx64w.stdout.exp \
+ pcmpxstrx64w.vgtest \
+ rcl-amd64.vgtest rcl-amd64.stdout.exp rcl-amd64.stderr.exp \
+ redundantRexW.vgtest redundantRexW.stdout.exp \
+ redundantRexW.stderr.exp \
+ smc1.stderr.exp smc1.stdout.exp smc1.vgtest \
+ sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \
+ shrld.stderr.exp shrld.stdout.exp shrld.vgtest \
+ ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
+ ssse3_misaligned.vgtest \
+ sse4-64.stderr.exp sse4-64.stdout.exp sse4-64.vgtest \
+ sse4-64.stdout.exp-older-glibc \
+ slahf-amd64.stderr.exp slahf-amd64.stdout.exp \
+ slahf-amd64.vgtest \
+ xadd.stderr.exp xadd.stdout.exp xadd.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+
+# generic C ones
+amd64locked_CFLAGS = $(AM_CFLAGS) -O
+bug132918_LDADD = -lm
+fxtract_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_OVERFLOW@
+insn_basic_SOURCES = insn_basic.def
+insn_basic_LDADD = -lm
+insn_mmx_SOURCES = insn_mmx.def
+insn_mmx_LDADD = -lm
+insn_sse_SOURCES = insn_sse.def
+insn_sse_LDADD = -lm
+insn_sse2_SOURCES = insn_sse2.def
+insn_sse2_LDADD = -lm
+insn_sse3_SOURCES = insn_sse3.def
+insn_sse3_LDADD = -lm
+insn_ssse3_SOURCES = insn_ssse3.def
+insn_ssse3_LDADD = -lm
+insn_fpu_SOURCES = insn_fpu.def
+insn_fpu_LDADD = -lm
+insn_pclmulqdq_SOURCES = insn_pclmulqdq.def
+fxtract_LDADD = -lm
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .def .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/amd64/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/amd64/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+aes$(EXEEXT): $(aes_OBJECTS) $(aes_DEPENDENCIES)
+ @rm -f aes$(EXEEXT)
+ $(LINK) $(aes_OBJECTS) $(aes_LDADD) $(LIBS)
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+amd64locked$(EXEEXT): $(amd64locked_OBJECTS) $(amd64locked_DEPENDENCIES)
+ @rm -f amd64locked$(EXEEXT)
+ $(amd64locked_LINK) $(amd64locked_OBJECTS) $(amd64locked_LDADD) $(LIBS)
+asorep$(EXEEXT): $(asorep_OBJECTS) $(asorep_DEPENDENCIES)
+ @rm -f asorep$(EXEEXT)
+ $(LINK) $(asorep_OBJECTS) $(asorep_LDADD) $(LIBS)
+avx-1$(EXEEXT): $(avx_1_OBJECTS) $(avx_1_DEPENDENCIES)
+ @rm -f avx-1$(EXEEXT)
+ $(LINK) $(avx_1_OBJECTS) $(avx_1_LDADD) $(LIBS)
+bug127521-64$(EXEEXT): $(bug127521_64_OBJECTS) $(bug127521_64_DEPENDENCIES)
+ @rm -f bug127521-64$(EXEEXT)
+ $(LINK) $(bug127521_64_OBJECTS) $(bug127521_64_LDADD) $(LIBS)
+bug132813-amd64$(EXEEXT): $(bug132813_amd64_OBJECTS) $(bug132813_amd64_DEPENDENCIES)
+ @rm -f bug132813-amd64$(EXEEXT)
+ $(LINK) $(bug132813_amd64_OBJECTS) $(bug132813_amd64_LDADD) $(LIBS)
+bug132918$(EXEEXT): $(bug132918_OBJECTS) $(bug132918_DEPENDENCIES)
+ @rm -f bug132918$(EXEEXT)
+ $(LINK) $(bug132918_OBJECTS) $(bug132918_LDADD) $(LIBS)
+bug137714-amd64$(EXEEXT): $(bug137714_amd64_OBJECTS) $(bug137714_amd64_DEPENDENCIES)
+ @rm -f bug137714-amd64$(EXEEXT)
+ $(LINK) $(bug137714_amd64_OBJECTS) $(bug137714_amd64_LDADD) $(LIBS)
+bug156404-amd64$(EXEEXT): $(bug156404_amd64_OBJECTS) $(bug156404_amd64_DEPENDENCIES)
+ @rm -f bug156404-amd64$(EXEEXT)
+ $(LINK) $(bug156404_amd64_OBJECTS) $(bug156404_amd64_LDADD) $(LIBS)
+clc$(EXEEXT): $(clc_OBJECTS) $(clc_DEPENDENCIES)
+ @rm -f clc$(EXEEXT)
+ $(LINK) $(clc_OBJECTS) $(clc_LDADD) $(LIBS)
+cmpxchg$(EXEEXT): $(cmpxchg_OBJECTS) $(cmpxchg_DEPENDENCIES)
+ @rm -f cmpxchg$(EXEEXT)
+ $(LINK) $(cmpxchg_OBJECTS) $(cmpxchg_LDADD) $(LIBS)
+crc32$(EXEEXT): $(crc32_OBJECTS) $(crc32_DEPENDENCIES)
+ @rm -f crc32$(EXEEXT)
+ $(LINK) $(crc32_OBJECTS) $(crc32_LDADD) $(LIBS)
+faultstatus$(EXEEXT): $(faultstatus_OBJECTS) $(faultstatus_DEPENDENCIES)
+ @rm -f faultstatus$(EXEEXT)
+ $(LINK) $(faultstatus_OBJECTS) $(faultstatus_LDADD) $(LIBS)
+fcmovnu$(EXEEXT): $(fcmovnu_OBJECTS) $(fcmovnu_DEPENDENCIES)
+ @rm -f fcmovnu$(EXEEXT)
+ $(LINK) $(fcmovnu_OBJECTS) $(fcmovnu_LDADD) $(LIBS)
+fxtract$(EXEEXT): $(fxtract_OBJECTS) $(fxtract_DEPENDENCIES)
+ @rm -f fxtract$(EXEEXT)
+ $(fxtract_LINK) $(fxtract_OBJECTS) $(fxtract_LDADD) $(LIBS)
+insn_basic$(EXEEXT): $(insn_basic_OBJECTS) $(insn_basic_DEPENDENCIES)
+ @rm -f insn_basic$(EXEEXT)
+ $(LINK) $(insn_basic_OBJECTS) $(insn_basic_LDADD) $(LIBS)
+insn_fpu$(EXEEXT): $(insn_fpu_OBJECTS) $(insn_fpu_DEPENDENCIES)
+ @rm -f insn_fpu$(EXEEXT)
+ $(LINK) $(insn_fpu_OBJECTS) $(insn_fpu_LDADD) $(LIBS)
+insn_mmx$(EXEEXT): $(insn_mmx_OBJECTS) $(insn_mmx_DEPENDENCIES)
+ @rm -f insn_mmx$(EXEEXT)
+ $(LINK) $(insn_mmx_OBJECTS) $(insn_mmx_LDADD) $(LIBS)
+insn_pclmulqdq$(EXEEXT): $(insn_pclmulqdq_OBJECTS) $(insn_pclmulqdq_DEPENDENCIES)
+ @rm -f insn_pclmulqdq$(EXEEXT)
+ $(LINK) $(insn_pclmulqdq_OBJECTS) $(insn_pclmulqdq_LDADD) $(LIBS)
+insn_sse$(EXEEXT): $(insn_sse_OBJECTS) $(insn_sse_DEPENDENCIES)
+ @rm -f insn_sse$(EXEEXT)
+ $(LINK) $(insn_sse_OBJECTS) $(insn_sse_LDADD) $(LIBS)
+insn_sse2$(EXEEXT): $(insn_sse2_OBJECTS) $(insn_sse2_DEPENDENCIES)
+ @rm -f insn_sse2$(EXEEXT)
+ $(LINK) $(insn_sse2_OBJECTS) $(insn_sse2_LDADD) $(LIBS)
+insn_sse3$(EXEEXT): $(insn_sse3_OBJECTS) $(insn_sse3_DEPENDENCIES)
+ @rm -f insn_sse3$(EXEEXT)
+ $(LINK) $(insn_sse3_OBJECTS) $(insn_sse3_LDADD) $(LIBS)
+insn_ssse3$(EXEEXT): $(insn_ssse3_OBJECTS) $(insn_ssse3_DEPENDENCIES)
+ @rm -f insn_ssse3$(EXEEXT)
+ $(LINK) $(insn_ssse3_OBJECTS) $(insn_ssse3_LDADD) $(LIBS)
+jrcxz$(EXEEXT): $(jrcxz_OBJECTS) $(jrcxz_DEPENDENCIES)
+ @rm -f jrcxz$(EXEEXT)
+ $(LINK) $(jrcxz_OBJECTS) $(jrcxz_LDADD) $(LIBS)
+looper$(EXEEXT): $(looper_OBJECTS) $(looper_DEPENDENCIES)
+ @rm -f looper$(EXEEXT)
+ $(LINK) $(looper_OBJECTS) $(looper_LDADD) $(LIBS)
+loopnel$(EXEEXT): $(loopnel_OBJECTS) $(loopnel_DEPENDENCIES)
+ @rm -f loopnel$(EXEEXT)
+ $(LINK) $(loopnel_OBJECTS) $(loopnel_LDADD) $(LIBS)
+lzcnt64$(EXEEXT): $(lzcnt64_OBJECTS) $(lzcnt64_DEPENDENCIES)
+ @rm -f lzcnt64$(EXEEXT)
+ $(LINK) $(lzcnt64_OBJECTS) $(lzcnt64_LDADD) $(LIBS)
+movbe$(EXEEXT): $(movbe_OBJECTS) $(movbe_DEPENDENCIES)
+ @rm -f movbe$(EXEEXT)
+ $(LINK) $(movbe_OBJECTS) $(movbe_LDADD) $(LIBS)
+nan80and64$(EXEEXT): $(nan80and64_OBJECTS) $(nan80and64_DEPENDENCIES)
+ @rm -f nan80and64$(EXEEXT)
+ $(LINK) $(nan80and64_OBJECTS) $(nan80and64_LDADD) $(LIBS)
+nibz_bennee_mmap$(EXEEXT): $(nibz_bennee_mmap_OBJECTS) $(nibz_bennee_mmap_DEPENDENCIES)
+ @rm -f nibz_bennee_mmap$(EXEEXT)
+ $(LINK) $(nibz_bennee_mmap_OBJECTS) $(nibz_bennee_mmap_LDADD) $(LIBS)
+pcmpstr64$(EXEEXT): $(pcmpstr64_OBJECTS) $(pcmpstr64_DEPENDENCIES)
+ @rm -f pcmpstr64$(EXEEXT)
+ $(LINK) $(pcmpstr64_OBJECTS) $(pcmpstr64_LDADD) $(LIBS)
+pcmpstr64w$(EXEEXT): $(pcmpstr64w_OBJECTS) $(pcmpstr64w_DEPENDENCIES)
+ @rm -f pcmpstr64w$(EXEEXT)
+ $(LINK) $(pcmpstr64w_OBJECTS) $(pcmpstr64w_LDADD) $(LIBS)
+pcmpxstrx64$(EXEEXT): $(pcmpxstrx64_OBJECTS) $(pcmpxstrx64_DEPENDENCIES)
+ @rm -f pcmpxstrx64$(EXEEXT)
+ $(LINK) $(pcmpxstrx64_OBJECTS) $(pcmpxstrx64_LDADD) $(LIBS)
+pcmpxstrx64w$(EXEEXT): $(pcmpxstrx64w_OBJECTS) $(pcmpxstrx64w_DEPENDENCIES)
+ @rm -f pcmpxstrx64w$(EXEEXT)
+ $(LINK) $(pcmpxstrx64w_OBJECTS) $(pcmpxstrx64w_LDADD) $(LIBS)
+rcl-amd64$(EXEEXT): $(rcl_amd64_OBJECTS) $(rcl_amd64_DEPENDENCIES)
+ @rm -f rcl-amd64$(EXEEXT)
+ $(LINK) $(rcl_amd64_OBJECTS) $(rcl_amd64_LDADD) $(LIBS)
+redundantRexW$(EXEEXT): $(redundantRexW_OBJECTS) $(redundantRexW_DEPENDENCIES)
+ @rm -f redundantRexW$(EXEEXT)
+ $(LINK) $(redundantRexW_OBJECTS) $(redundantRexW_LDADD) $(LIBS)
+sbbmisc$(EXEEXT): $(sbbmisc_OBJECTS) $(sbbmisc_DEPENDENCIES)
+ @rm -f sbbmisc$(EXEEXT)
+ $(LINK) $(sbbmisc_OBJECTS) $(sbbmisc_LDADD) $(LIBS)
+shrld$(EXEEXT): $(shrld_OBJECTS) $(shrld_DEPENDENCIES)
+ @rm -f shrld$(EXEEXT)
+ $(LINK) $(shrld_OBJECTS) $(shrld_LDADD) $(LIBS)
+slahf-amd64$(EXEEXT): $(slahf_amd64_OBJECTS) $(slahf_amd64_DEPENDENCIES)
+ @rm -f slahf-amd64$(EXEEXT)
+ $(LINK) $(slahf_amd64_OBJECTS) $(slahf_amd64_LDADD) $(LIBS)
+smc1$(EXEEXT): $(smc1_OBJECTS) $(smc1_DEPENDENCIES)
+ @rm -f smc1$(EXEEXT)
+ $(LINK) $(smc1_OBJECTS) $(smc1_LDADD) $(LIBS)
+sse4-64$(EXEEXT): $(sse4_64_OBJECTS) $(sse4_64_DEPENDENCIES)
+ @rm -f sse4-64$(EXEEXT)
+ $(LINK) $(sse4_64_OBJECTS) $(sse4_64_LDADD) $(LIBS)
+ssse3_misaligned$(EXEEXT): $(ssse3_misaligned_OBJECTS) $(ssse3_misaligned_DEPENDENCIES)
+ @rm -f ssse3_misaligned$(EXEEXT)
+ $(LINK) $(ssse3_misaligned_OBJECTS) $(ssse3_misaligned_LDADD) $(LIBS)
+xadd$(EXEEXT): $(xadd_OBJECTS) $(xadd_DEPENDENCIES)
+ @rm -f xadd$(EXEEXT)
+ $(LINK) $(xadd_OBJECTS) $(xadd_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aes.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/amd64locked-amd64locked.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/asorep.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avx-1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug127521-64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132813-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132918.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug137714-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug156404-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cmpxchg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/crc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/faultstatus.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fcmovnu.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxtract-fxtract.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_basic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_fpu.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_mmx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_pclmulqdq.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_sse.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_sse2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_sse3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_ssse3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jrcxz.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/looper.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/loopnel.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lzcnt64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/movbe.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nan80and64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nibz_bennee_mmap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pcmpstr64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pcmpstr64w.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pcmpxstrx64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pcmpxstrx64w.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rcl-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/redundantRexW.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sbbmisc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shrld.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/slahf-amd64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/smc1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sse4-64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ssse3_misaligned.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xadd.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+allexec-allexec.o: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.o -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+
+allexec-allexec.obj: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.obj -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+
+amd64locked-amd64locked.o: amd64locked.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(amd64locked_CFLAGS) $(CFLAGS) -MT amd64locked-amd64locked.o -MD -MP -MF $(DEPDIR)/amd64locked-amd64locked.Tpo -c -o amd64locked-amd64locked.o `test -f 'amd64locked.c' || echo '$(srcdir)/'`amd64locked.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/amd64locked-amd64locked.Tpo $(DEPDIR)/amd64locked-amd64locked.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='amd64locked.c' object='amd64locked-amd64locked.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(amd64locked_CFLAGS) $(CFLAGS) -c -o amd64locked-amd64locked.o `test -f 'amd64locked.c' || echo '$(srcdir)/'`amd64locked.c
+
+amd64locked-amd64locked.obj: amd64locked.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(amd64locked_CFLAGS) $(CFLAGS) -MT amd64locked-amd64locked.obj -MD -MP -MF $(DEPDIR)/amd64locked-amd64locked.Tpo -c -o amd64locked-amd64locked.obj `if test -f 'amd64locked.c'; then $(CYGPATH_W) 'amd64locked.c'; else $(CYGPATH_W) '$(srcdir)/amd64locked.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/amd64locked-amd64locked.Tpo $(DEPDIR)/amd64locked-amd64locked.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='amd64locked.c' object='amd64locked-amd64locked.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(amd64locked_CFLAGS) $(CFLAGS) -c -o amd64locked-amd64locked.obj `if test -f 'amd64locked.c'; then $(CYGPATH_W) 'amd64locked.c'; else $(CYGPATH_W) '$(srcdir)/amd64locked.c'; fi`
+
+fxtract-fxtract.o: fxtract.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxtract_CFLAGS) $(CFLAGS) -MT fxtract-fxtract.o -MD -MP -MF $(DEPDIR)/fxtract-fxtract.Tpo -c -o fxtract-fxtract.o `test -f 'fxtract.c' || echo '$(srcdir)/'`fxtract.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/fxtract-fxtract.Tpo $(DEPDIR)/fxtract-fxtract.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fxtract.c' object='fxtract-fxtract.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxtract_CFLAGS) $(CFLAGS) -c -o fxtract-fxtract.o `test -f 'fxtract.c' || echo '$(srcdir)/'`fxtract.c
+
+fxtract-fxtract.obj: fxtract.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxtract_CFLAGS) $(CFLAGS) -MT fxtract-fxtract.obj -MD -MP -MF $(DEPDIR)/fxtract-fxtract.Tpo -c -o fxtract-fxtract.obj `if test -f 'fxtract.c'; then $(CYGPATH_W) 'fxtract.c'; else $(CYGPATH_W) '$(srcdir)/fxtract.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/fxtract-fxtract.Tpo $(DEPDIR)/fxtract-fxtract.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fxtract.c' object='fxtract-fxtract.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxtract_CFLAGS) $(CFLAGS) -c -o fxtract-fxtract.obj `if test -f 'fxtract.c'; then $(CYGPATH_W) 'fxtract.c'; else $(CYGPATH_W) '$(srcdir)/fxtract.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+ -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+.def.c: $(srcdir)/gen_insn_test.pl
+ $(PERL) $(srcdir)/gen_insn_test.pl < $< > $@
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/amd64/aes.c b/main/none/tests/amd64/aes.c
new file mode 100644
index 0000000..a0c83c6
--- /dev/null
+++ b/main/none/tests/amd64/aes.c
@@ -0,0 +1,373 @@
+
+#include <string.h>
+#include <stdio.h>
+#include <assert.h>
+
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef unsigned long long int ULong;
+typedef UChar Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+//typedef unsigned char V128[16];
+typedef
+ union {
+ UChar uChar[16];
+ UInt uInt[4];
+ }
+ V128;
+
+static UChar fromhex(char x) {
+ if (x >= '0' && x <= '9') { return(x - '0'); }
+ else if (x >= 'A' && x <= 'F') { return(x - 'A' + 10); }
+ else if (x >= 'a' && x <= 'f') { return(x - 'a' + 10); }
+ else assert(0);
+}
+
+static void expand ( V128* dst, char* summary )
+{
+ Int i;
+ assert( strlen(summary) == 32 );
+ for (i = 0; i < 16; i++) {
+ UChar xx = 0;
+ UChar x = summary[31-2*i];
+ UChar yy = 0;
+ UChar y = summary[31-2*i-1];
+ xx = fromhex (x);
+ yy = fromhex (y);
+
+ assert(xx < 16);
+ assert(yy < 16);
+ xx = (yy << 4) | xx;
+ assert(xx < 256);
+ dst->uChar[i] = xx;
+ }
+}
+
+static int tohex (int nib)
+{
+ if (nib < 10)
+ return '0' + nib;
+ else
+ return 'a' + nib - 10;
+}
+static void unexpand ( V128* dst, char* summary )
+{
+ Int i;
+ for (i = 0; i < 16; i++) {
+ *summary++ = tohex((dst->uChar[i] >> 4) & 0xf);
+ *summary++ = tohex(dst->uChar[i] & 0xf);
+ }
+ *summary = 0;
+}
+
+static void AESDEC(char *s_argL, char *s_argR, char *s_exp)
+{
+ /*
+ ; xmm1 and xmm2 hold two 128-bit inputs (xmm1 = State; xmm2 = Round key).
+ ; The result is delivered in xmm1.
+ */
+ V128 argL, argR;
+ V128 res;
+ char s_res[33];
+ V128 exp;
+ expand(&argL, s_argL);
+ expand(&argR, s_argR);
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu %1, %%xmm1" "\n\t"
+ "movdqu %2, %%xmm2" "\n\t"
+ "aesdec %%xmm2, %%xmm1" "\n\t"
+ "movdqu %%xmm1, %0" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=m"(res)
+ : "m"/*in*/(argL), "m"/*in*/(argR)
+ : /*trash*/ "xmm1", "xmm2"
+ );
+
+ if (strlen(s_exp) > 0) {
+ expand(&exp, s_exp);
+ assert (0 == memcmp(&res, &exp, 16));
+ }
+ unexpand (&res, s_res);
+ printf ("aesdec %s %s result %s\n", s_argL, s_argR, s_res);
+}
+
+static void AESDECLAST(char *s_argL, char *s_argR, char *s_exp)
+{
+ /*
+ ; xmm1 and xmm2 hold two 128-bit inputs (xmm1 = State; xmm2 = Round key).
+ ; The result is delivered in xmm1.
+ */
+ V128 argL, argR;
+ V128 res;
+ char s_res[33];
+ V128 exp;
+ expand(&argL, s_argL);
+ expand(&argR, s_argR);
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu %1, %%xmm1" "\n\t"
+ "movdqu %2, %%xmm2" "\n\t"
+ "aesdeclast %%xmm2, %%xmm1" "\n\t"
+ "movdqu %%xmm1, %0" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=m"(res)
+ : "m"/*in*/(argL), "m"/*in*/(argR)
+ : /*trash*/ "xmm1", "xmm2"
+ );
+
+ if (strlen(s_exp) > 0) {
+ expand(&exp, s_exp);
+ assert (0 == memcmp(&res, &exp, 16));
+ }
+ unexpand (&res, s_res);
+ printf ("aesdeclast %s %s result %s\n", s_argL, s_argR, s_res);
+}
+
+static void AESENC(char *s_argL, char *s_argR, char *s_exp)
+{
+ /*
+ ; xmm1 and xmm2 hold two 128-bit inputs (xmm1 = State; xmm2 = Round key).
+ ; The result is delivered in xmm1.
+ */
+ V128 argL, argR;
+ V128 res;
+ char s_res[33];
+ V128 exp;
+ expand(&argL, s_argL);
+ expand(&argR, s_argR);
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu %1, %%xmm1" "\n\t"
+ "movdqu %2, %%xmm2" "\n\t"
+ "aesenc %%xmm2, %%xmm1" "\n\t"
+ "movdqu %%xmm1, %0" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=m"(res)
+ : "m"/*in*/(argL), "m"/*in*/(argR)
+ : /*trash*/ "xmm1", "xmm2"
+ );
+
+ if (strlen(s_exp) > 0) {
+ expand(&exp, s_exp);
+ assert (0 == memcmp(&res, &exp, 16));
+ }
+ unexpand (&res, s_res);
+ printf ("aesenc %s %s result %s\n", s_argL, s_argR, s_res);
+}
+
+static void AESENCLAST(char *s_argL, char *s_argR, char *s_exp)
+{
+ /*
+ ; xmm1 and xmm2 hold two 128-bit inputs (xmm1 = State; xmm2 = Round key)
+ ; The result delivered in xmm1
+ */
+ V128 argL, argR;
+ V128 res;
+ char s_res[33];
+ V128 exp;
+ expand(&argL, s_argL);
+ expand(&argR, s_argR);
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu %1, %%xmm1" "\n\t"
+ "movdqu %2, %%xmm2" "\n\t"
+ "aesenclast %%xmm2, %%xmm1" "\n\t"
+ "movdqu %%xmm1, %0" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=m"(res)
+ : "m"/*in*/(argL), "m"/*in*/(argR)
+ : /*trash*/ "xmm1", "xmm2"
+ );
+
+ if (strlen(s_exp) > 0) {
+ expand(&exp, s_exp);
+ assert (0 == memcmp(&res, &exp, 16));
+ }
+ unexpand (&res, s_res);
+ printf ("aesenclast %s %s result %s\n", s_argL, s_argR, s_res);
+}
+
+static void AESIMC(char *s_argR, char *s_exp)
+{
+ /* We test another way to pass input and get results */
+ /* ; argR hold one 128-bit inputs (argR = Round key)
+ ; result delivered in xmm5 */
+
+ V128 argR;
+ V128 res;
+ char s_res[33];
+ V128 exp;
+ expand(&argR, s_argR);
+
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "aesimc %1, %%xmm5" "\n\t"
+ "movdqu %%xmm5, %0" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=m"(res)
+ : "m"/*in*/(argR)
+ : /*trash*/ "xmm5"
+ );
+
+ if (strlen(s_exp) > 0) {
+ expand(&exp, s_exp);
+ assert (0 == memcmp(&res, &exp, 16));
+ }
+ unexpand (&res, s_res);
+ printf ("aesimc %s result %s\n", s_argR, s_res);
+}
+
+static void AESKEYGENASSIST(int imm, char* s_argL, char* s_exp)
+{
+ /*
+ ; xmm2 holds a 128-bit input; imm8 holds the RCON value
+ ; result delivered in xmm1
+ */
+
+ V128 argL;
+ V128 res;
+ char s_res[33];
+ V128 exp;
+ expand(&argL, s_argL);
+ if (imm == 1)
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu %1, %%xmm2" "\n\t"
+ "aeskeygenassist $1,%%xmm2, %%xmm1" "\n\t"
+ "movdqu %%xmm1, %0" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=m"(res)
+ : "m"/*in*/(argL)
+ : /*trash*/ "xmm1", "xmm2"
+ );
+ else if (imm == 2)
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu %1, %%xmm2" "\n\t"
+ "aeskeygenassist $2,%%xmm2, %%xmm1" "\n\t"
+ "movdqu %%xmm1, %0" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=m"(res)
+ : "m"/*in*/(argL)
+ : /*trash*/ "xmm1", "xmm2"
+ );
+ else if (imm == 8)
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu %1, %%xmm2" "\n\t"
+ "aeskeygenassist $8,%%xmm2, %%xmm1" "\n\t"
+ "movdqu %%xmm1, %0" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=m"(res)
+ : "m"/*in*/(argL)
+ : /*trash*/ "xmm1", "xmm2"
+ );
+ else assert (0);
+
+ if (strlen(s_exp) > 0) {
+ expand(&exp, s_exp);
+ assert (0 == memcmp(&res, &exp, 16));
+ }
+ unexpand (&res, s_res);
+ printf ("aeskeygenassist %d %s result %s\n", imm, s_argL, s_res);
+}
+
+typedef struct Aes_Args {
+ char* argL;
+ char* argR;
+ int imm; // only for aeskeygenassist
+} Aes_Args;
+
+/* Just a bunch of various data to compare a native run
+ with a run under Valgrind. */
+static const Aes_Args aes_args[] = {
+ {"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa",
+ "bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb",
+ 8},
+ {"bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb",
+ "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa",
+ 8},
+ {"3243f6a8885a308d313198a2e0370734",
+ "2b7e151628aed2a6abf7158809cf4f3c",
+ 2},
+ {"193de3bea0f4e22b9ac68d2ae9f84808",
+ "d42711aee0bf98f1b8b45de51e415230",
+ 2},
+ {"d4bf5d30e0b452aeb84111f11e2798e5",
+ "046681e5e0cb199a48f8d37a2806264c",
+ 1},
+ {"a0fafe1788542cb123a339392a6c7605",
+ "a49c7ff2689f352b6b5bea43026a5049",
+ 1},
+ {"49ded28945db96f17f39871a7702533b",
+ "49db873b453953897f02d2f177de961a",
+ 8},
+ {"584dcaf11b4b5aacdbe7caa81b6bb0e5",
+ "f2c295f27a96b9435935807a7359f67f",
+ 8},
+ {"aa8f5f0361dde3ef82d24ad26832469a",
+ "ac73cf7befc111df13b5d6b545235ab8",
+ 2},
+ {"acc1d6b8efb55a7b1323cfdf457311b5",
+ "75ec0993200b633353c0cf7cbb25d0dc",
+ 2},
+ {"e9317db5cb322c723d2e895faf090794",
+ "d014f9a8c9ee2589e13f0cc8b6630ca6",
+ 1},
+ {NULL,
+ NULL,
+ 0}
+};
+
+int main ( void )
+{
+ int i;
+
+ /* test the various instructions, using the examples provided
+ in "White Paper Intel Advanced Encryption Standard AES
+ instruction set" January 2010 (26/1/2010)
+ Rev. 3.0
+ by Shay Gueron */
+ AESKEYGENASSIST(1,
+ "3c4fcf098815f7aba6d2ae2816157e2b",
+ "01eb848beb848a013424b5e524b5e434");
+ AESENC("7b5b54657374566563746f725d53475d",
+ "48692853686179295b477565726f6e5d",
+ "a8311c2f9fdba3c58b104b58ded7e595");
+ AESENCLAST("7b5b54657374566563746f725d53475d",
+ "48692853686179295b477565726f6e5d",
+ "c7fb881e938c5964177ec42553fdc611");
+ AESDEC("7b5b54657374566563746f725d53475d",
+ "48692853686179295b477565726f6e5d",
+ "138ac342faea2787b58eb95eb730392a");
+ AESDECLAST("7b5b54657374566563746f725d53475d",
+ "48692853686179295b477565726f6e5d",
+ "c5a391ef6b317f95d410637b72a593d0");
+ /* ??? the AESIMC example given in the Intel White paper
+ seems wrong.
+ The below fails both under Valgrind and natively.
+ AESIMC("48692853686179295b477565726f6e5d",
+ "627a6f6644b109c82b18330a81c3b3e5");
+ So we use the example given for the InvMixColums
+ transformation. */
+ AESIMC("8dcab9dc035006bc8f57161e00cafd8d",
+ "d635a667928b5eaeeec9cc3bc55f5777");
+
+
+ /* and now a bunch of other calls. The below are verified
+ using the aes.stdout.exp (produced by a native run). */
+
+ for (i = 0; aes_args[i].argL != NULL; i++) {
+ AESKEYGENASSIST(aes_args[i].imm, aes_args[i].argL, "");
+ AESENC(aes_args[i].argL, aes_args[i].argR, "");
+ AESENCLAST(aes_args[i].argL, aes_args[i].argR, "");
+ AESDEC(aes_args[i].argL, aes_args[i].argR, "");
+ AESDECLAST(aes_args[i].argL, aes_args[i].argR, "");
+ AESIMC(aes_args[i].argL, "");
+ }
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/amd64/aes.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/amd64/aes.stderr.exp
diff --git a/main/none/tests/amd64/aes.stdout.exp b/main/none/tests/amd64/aes.stdout.exp
new file mode 100644
index 0000000..f9bb2e2
--- /dev/null
+++ b/main/none/tests/amd64/aes.stdout.exp
@@ -0,0 +1,72 @@
+aeskeygenassist 1 3c4fcf098815f7aba6d2ae2816157e2b result 34e4b524e5b52434018a84eb8b84eb01
+aesenc 7b5b54657374566563746f725d53475d 48692853686179295b477565726f6e5d result 95e5d7de584b108bc5a3db9f2f1c31a8
+aesenclast 7b5b54657374566563746f725d53475d 48692853686179295b477565726f6e5d result 11c6fd5325c47e1764598c931e88fbc7
+aesdec 7b5b54657374566563746f725d53475d 48692853686179295b477565726f6e5d result 2a3930b75eb98eb58727eafa42c38a13
+aesdeclast 7b5b54657374566563746f725d53475d 48692853686179295b477565726f6e5d result d093a5727b6310d4957f316bef91a3c5
+aesimc 8dcab9dc035006bc8f57161e00cafd8d result 77575fc53bccc9eeae5e8b9267a635d6
+aeskeygenassist 8 aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa result acacacaca4acacacacacacaca4acacac
+aesenc aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb result 17171717171717171717171717171717
+aesenclast aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb result 17171717171717171717171717171717
+aesdec aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb result d9d9d9d9d9d9d9d9d9d9d9d9d9d9d9d9
+aesdeclast aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb result d9d9d9d9d9d9d9d9d9d9d9d9d9d9d9d9
+aesimc aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa result aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+aeskeygenassist 8 bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb result eaeaeaeae2eaeaeaeaeaeaeae2eaeaea
+aesenc bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa result 40404040404040404040404040404040
+aesenclast bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa result 40404040404040404040404040404040
+aesdec bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa result 54545454545454545454545454545454
+aesdeclast bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa result 54545454545454545454545454545454
+aesimc bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb result bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb
+aeskeygenassist 2 3243f6a8885a308d313198a2e0370734 result 3a46c7c744c7c73ac2421a23401a23c2
+aesenc 3243f6a8885a308d313198a2e0370734 2b7e151628aed2a6abf7158809cf4f3c result 5b21939f0be8c5228779cc82ded0bbe7
+aesenclast 3243f6a8885a308d313198a2e0370734 2b7e151628aed2a6abf7158809cf4f3c result 2409712ab211ed4afb9034efd4d0b9ef
+aesdec 3243f6a8885a308d313198a2e0370734 2b7e151628aed2a6abf7158809cf4f3c result 1a25b0ac361c8eb4fddc79ef4827a878
+aesdeclast 3243f6a8885a308d313198a2e0370734 2b7e151628aed2a6abf7158809cf4f3c result 14998927922d933c12301c89791d508b
+aesimc 3243f6a8885a308d313198a2e0370734 result db530b675db2ba6fa708ae6ed9f66c6c
+aeskeygenassist 2 193de3bea0f4e22b9ac68d2ae9f84808 result e55db4b85fb4b8e5ae1127d41327d4ae
+aesenc 193de3bea0f4e22b9ac68d2ae9f84808 d42711aee0bf98f1b8b45de51e415230 result dcd62e1fbee4a50fc2300ed34b3c9300
+aesenclast 193de3bea0f4e22b9ac68d2ae9f84808 d42711aee0bf98f1b8b45de51e415230 result 000ffeca00c593a60089fe5800439334
+aesdec 193de3bea0f4e22b9ac68d2ae9f84808 d42711aee0bf98f1b8b45de51e415230 result ceb3447b03c44db310640f9d67b7e938
+aesdeclast 193de3bea0f4e22b9ac68d2ae9f84808 d42711aee0bf98f1b8b45de51e415230 result 8f1ffb2970893ffffa2c5e6ef42ae03f
+aesimc 193de3bea0f4e22b9ac68d2ae9f84808 result 8a6ed86d802581dfeac414a7a21dd315
+aeskeygenassist 1 d4bf5d30e0b452aeb84111f11e2798e5 result a182836c83836ca1044c08484d084804
+aesenc d4bf5d30e0b452aeb84111f11e2798e5 046681e5e0cb199a48f8d37a2806264c result bd2484c75918df5c3d46548f45760114
+aesenclast d4bf5d30e0b452aeb84111f11e2798e5 046681e5e0cb199a48f8d37a2806264c result 95a48b60dbd3f03a7e55078ce1c7e5e5
+aesdec d4bf5d30e0b452aeb84111f11e2798e5 046681e5e0cb199a48f8d37a2806264c result cc0387f79017ecef380418f56fefbe69
+aesdeclast d4bf5d30e0b452aeb84111f11e2798e5 046681e5e0cb199a48f8d37a2806264c result 66abc0b251310ce824faf6f9edc99eed
+aesimc d4bf5d30e0b452aeb84111f11e2798e5 result 6881228f0df28f69bae4eb1dd6a65523
+aeskeygenassist 1 a0fafe1788542cb123a339392a6c7605 result 12120a26130a2612f0bb2de0ba2de0f0
+aesenc a0fafe1788542cb123a339392a6c7605 a49c7ff2689f352b6b5bea43026a5049 result 699f68563c8856d00046268c8f25170e
+aesenclast a0fafe1788542cb123a339392a6c7605 a49c7ff2689f352b6b5bea43026a5049 result 22424ae2519b768ee38ecf4e02479660
+aesdec a0fafe1788542cb123a339392a6c7605 a49c7ff2689f352b6b5bea43026a5049 result 16410fdca2b0401cd1e0745e2318f956
+aesdeclast a0fafe1788542cb123a339392a6c7605 a49c7ff2689f352b6b5bea43026a5049 result 7f5c973018e54ffc7d6e272f753ded31
+aesimc a0fafe1788542cb123a339392a6c7605 result daafd9998b920a93560531231bc98bea
+aeskeygenassist 8 49ded28945db96f17f39871a7702533b result a21712d21f12d2a2a7b51d3bbd1d3ba7
+aesenc 49ded28945db96f17f39871a7702533b 49db873b453953897f02d2f177de961a result 7eb10f92ed990efeb1c8aec03eb90798
+aesenclast 49ded28945db96f17f39871a7702533b 49db873b453953897f02d2f177de961a result f881674c53421f8a28e64e979c6ac927
+aesdec 49ded28945db96f17f39871a7702533b 49db873b453953897f02d2f177de961a result c2ea4f805b7fa23f53f6bcb0ccb0a26e
+aesdeclast 49ded28945db96f17f39871a7702533b 49db873b453953897f02d2f177de961a result 53e9411cb2829e17a2b953e1c9b2804b
+aesimc 49ded28945db96f17f39871a7702533b result fa94f98aee746021e71d24278e665a7e
+aeskeygenassist 8 584dcaf11b4b5aacdbe7caa81b6bb0e5 result c27494b97c94b9c2a174e36a7ce36aa1
+aesenc 584dcaf11b4b5aacdbe7caa81b6bb0e5 f2c295f27a96b9435935807a7359f67f result 9363371070b47e1c20f85db0a2e95d3c
+aesenclast 584dcaf11b4b5aacdbe7caa81b6bb0e5 f2c295f27a96b9435935807a7359f67f result a682ea19b83ed6f6d2cde9c35372565d
+aesdec 584dcaf11b4b5aacdbe7caa81b6bb0e5 f2c295f27a96b9435935807a7359f67f result 98438a9b55d66fc8a408075c6411e65d
+aesdeclast 584dcaf11b4b5aacdbe7caa81b6bb0e5 f2c295f27a96b9435935807a7359f67f result 55e695ec157c501de9a99324d9d372b6
+aesimc 584dcaf11b4b5aacdbe7caa81b6bb0e5 result 57919370d34c20e10b86bb9004e4e42a
+aeskeygenassist 2 aa8f5f0361dde3ef82d24ad26832469a result b5d6b513d4b513b57bcf73accd73ac7b
+aesenc aa8f5f0361dde3ef82d24ad26832469a ac73cf7befc111df13b5d6b545235ab8 result dfa13bc2c191383f003da25f392b090b
+aesenclast aa8f5f0361dde3ef82d24ad26832469a ac73cf7befc111df13b5d6b545235ab8 result 008ce2e900c7c65600dee2fc0095c643
+aesdec aa8f5f0361dde3ef82d24ad26832469a ac73cf7befc111df13b5d6b545235ab8 result 39388a643582a19fa61b9f3c8ba80951
+aesdeclast aa8f5f0361dde3ef82d24ad26832469a ac73cf7befc111df13b5d6b545235ab8 result 8fdeea54ca4ec6cbbe4d608dae820c5b
+aesimc aa8f5f0361dde3ef82d24ad26832469a result 75cccaf52bbea0fd78e6311f21815f86
+aeskeygenassist 2 acc1d6b8efb55a7b1323cfdf457311b5 result 9e8a267d88267d9e6cf67891f478916c
+aesenc acc1d6b8efb55a7b1323cfdf457311b5 75ec0993200b633353c0cf7cbb25d0dc result acff63b994d0a2f082425ec02fcf34c0
+aesenclast acc1d6b8efb55a7b1323cfdf457311b5 75ec0993200b633353c0cf7cbb25d0dc result 095af02ae271b83d1295845dff8bcaaa
+aesdec acc1d6b8efb55a7b1323cfdf457311b5 75ec0993200b633353c0cf7cbb25d0dc result f76e85460429f14c12e254a6e6c52680
+aesdeclast acc1d6b8efb55a7b1323cfdf457311b5 75ec0993200b633353c0cf7cbb25d0dc result 0e9af739932c1d32303c848a094fde1d
+aesimc acc1d6b8efb55a7b1323cfdf457311b5 result bdf0449b196aa5f6a2f39ab08010ff6c
+aeskeygenassist 1 e9317db5cb322c723d2e895faf090794 result cfa73127a63127cfd5ffc71efec71ed5
+aesenc e9317db5cb322c723d2e895faf090794 d014f9a8c9ee2589e13f0cc8b6630ca6 result 2d008268600a9fef35a43ab963f1477e
+aesenclast e9317db5cb322c723d2e895faf090794 d014f9a8c9ee2589e13f0cc8b6630ca6 result 84ab40a8077df898c9daefee7d3c25cf
+aesdec e9317db5cb322c723d2e895faf090794 d014f9a8c9ee2589e13f0cc8b6630ca6 result c542e1c7784ea84f7e85c9fe3be30603
+aesdeclast e9317db5cb322c723d2e895faf090794 d014f9a8c9ee2589e13f0cc8b6630ca6 result 411fc23d4c3411b897d7ae227abbd7cb
+aesimc e9317db5cb322c723d2e895faf090794 result 6d0b9ac9808d60a83d4928fb88132ca7
diff --git a/main/none/tests/amd64/aes.vgtest b/main/none/tests/amd64/aes.vgtest
new file mode 100644
index 0000000..9117d69
--- /dev/null
+++ b/main/none/tests/amd64/aes.vgtest
@@ -0,0 +1,3 @@
+prog: aes
+prereq: ../../../tests/x86_amd64_features amd64-sse42
+vgopts: -q
diff --git a/main/none/tests/amd64/allexec.c b/main/none/tests/amd64/allexec.c
new file mode 100644
index 0000000..b7177e8
--- /dev/null
+++ b/main/none/tests/amd64/allexec.c
@@ -0,0 +1,50 @@
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+extern char **environ;
+
+#define S(...) (fprintf(stdout, __VA_ARGS__),fflush(stdout))
+#define FORKEXECWAIT(exec_call) do { \
+ int status;\
+ pid_t child = fork(); \
+ if (child == 0) {exec_call; perror ("exec failed");} \
+ else if (child == -1) perror ("cannot fork\n"); \
+ else if (child != wait (&status)) perror ("error waiting child"); \
+ else S("child exited\n"); \
+ } while (0)
+
+void test_allexec (char *exec)
+{
+ FORKEXECWAIT (execlp(exec, exec, NULL));
+ FORKEXECWAIT (execlp(exec, exec, "constant_arg1", "constant_arg2", NULL));
+ FORKEXECWAIT (execve(exec, NULL, environ));
+}
+
+
+/* If a single argument "exec" is given, will execute itself
+ (in bi-arch, a 32 bit and 64 bit variant) via various exec system calls.
+ Note that this test can only be run after the prerequisite have been
+ prepared by allexec_prepare_prereq, which will a.o. make links
+ for the allexec32 and allexec64 executables. On single arch build,
+ these links points to the same executable to ensure this test works
+ everywhere the same.
+ No arguments or more arguments means just print its args. */
+int main(int argc, char **argv, char **envp)
+{
+ if ( (argc == 2) && (strcmp (argv[1], "exec") == 0)) {
+ S("%s will exec ./allexec32\n", argv[0]);
+ test_allexec ("./allexec32");
+ S("%s will exec ./allexec64\n", argv[0]);
+ test_allexec ("./allexec64");
+ } else {
+ int i;
+ S("program exec-ed:");
+ for (i = 0; i < argc; i++) S(" %s", argv[i]);
+ S("\n");
+ }
+ return 0;
+}
diff --git a/main/none/tests/amd64/avx-1.c b/main/none/tests/amd64/avx-1.c
new file mode 100644
index 0000000..fcc3513
--- /dev/null
+++ b/main/none/tests/amd64/avx-1.c
@@ -0,0 +1,2674 @@
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <malloc.h>
+
+typedef unsigned char UChar;
+typedef unsigned int UInt;
+typedef unsigned long int UWord;
+typedef unsigned long long int ULong;
+
+#define IS_32_ALIGNED(_ptr) (0 == (0x1F & (UWord)(_ptr)))
+
+typedef union { UChar u8[32]; UInt u32[8]; } YMM;
+
+typedef struct { YMM a1; YMM a2; YMM a3; YMM a4; ULong u64; } Block;
+
+void showYMM ( YMM* vec )
+{
+ int i;
+ assert(IS_32_ALIGNED(vec));
+ for (i = 31; i >= 0; i--) {
+ printf("%02x", (UInt)vec->u8[i]);
+ if (i > 0 && 0 == ((i+0) & 7)) printf(".");
+ }
+}
+
+void showBlock ( char* msg, Block* block )
+{
+ printf(" %s\n", msg);
+ printf(" "); showYMM(&block->a1); printf("\n");
+ printf(" "); showYMM(&block->a2); printf("\n");
+ printf(" "); showYMM(&block->a3); printf("\n");
+ printf(" "); showYMM(&block->a4); printf("\n");
+ printf(" %016llx\n", block->u64);
+}
+
+UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+void randBlock ( Block* b )
+{
+ int i;
+ UChar* p = (UChar*)b;
+ for (i = 0; i < sizeof(Block); i++)
+ p[i] = randUChar();
+}
+
+
+/* Generate a function test_NAME, that tests the given insn, in both
+ its mem and reg forms. The reg form of the insn may mention, as
+ operands only %ymm6, %ymm7, %ymm8, %ymm9 and %r14. The mem form of
+ the insn may mention as operands only (%rax), %ymm7, %ymm8, %ymm9
+ and %r14. It's OK for the insn to clobber ymm0, as this is needed
+ for testing PCMPxSTRx. */
+
+#define GEN_test_RandM(_name, _reg_form, _mem_form) \
+ \
+ __attribute__ ((noinline)) static void test_##_name ( void ) \
+ { \
+ Block* b = memalign(32, sizeof(Block)); \
+ randBlock(b); \
+ printf("%s(reg)\n", #_name); \
+ showBlock("before", b); \
+ __asm__ __volatile__( \
+ "vmovdqa 0(%0),%%ymm7" "\n\t" \
+ "vmovdqa 32(%0),%%ymm8" "\n\t" \
+ "vmovdqa 64(%0),%%ymm6" "\n\t" \
+ "vmovdqa 96(%0),%%ymm9" "\n\t" \
+ "movq 128(%0),%%r14" "\n\t" \
+ _reg_form "\n\t" \
+ "vmovdqa %%ymm7, 0(%0)" "\n\t" \
+ "vmovdqa %%ymm8, 32(%0)" "\n\t" \
+ "vmovdqa %%ymm6, 64(%0)" "\n\t" \
+ "vmovdqa %%ymm9, 96(%0)" "\n\t" \
+ "movq %%r14, 128(%0)" "\n\t" \
+ : /*OUT*/ \
+ : /*IN*/"r"(b) \
+ : /*TRASH*/"xmm0","xmm7","xmm8","xmm6","xmm9","r14","memory","cc" \
+ ); \
+ showBlock("after", b); \
+ randBlock(b); \
+ printf("%s(mem)\n", #_name); \
+ showBlock("before", b); \
+ __asm__ __volatile__( \
+ "leaq 0(%0),%%rax" "\n\t" \
+ "vmovdqa 32(%0),%%ymm8" "\n\t" \
+ "vmovdqa 64(%0),%%ymm7" "\n\t" \
+ "vmovdqa 96(%0),%%ymm9" "\n\t" \
+ "movq 128(%0),%%r14" "\n\t" \
+ _mem_form "\n\t" \
+ "vmovdqa %%ymm8, 32(%0)" "\n\t" \
+ "vmovdqa %%ymm7, 64(%0)" "\n\t" \
+ "vmovdqa %%ymm9, 96(%0)" "\n\t" \
+ "movq %%r14, 128(%0)" "\n\t" \
+ : /*OUT*/ \
+ : /*IN*/"r"(b) \
+ : /*TRASH*/"xmm0","xmm8","xmm7","xmm9","r14","rax","memory","cc" \
+ ); \
+ showBlock("after", b); \
+ printf("\n"); \
+ free(b); \
+ }
+
+#define GEN_test_Ronly(_name, _reg_form) \
+ GEN_test_RandM(_name, _reg_form, "")
+#define GEN_test_Monly(_name, _mem_form) \
+ GEN_test_RandM(_name, "", _mem_form)
+
+
+GEN_test_RandM(VPOR_128,
+ "vpor %%xmm6, %%xmm8, %%xmm7",
+ "vpor (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPXOR_128,
+ "vpxor %%xmm6, %%xmm8, %%xmm7",
+ "vpxor (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSUBB_128,
+ "vpsubb %%xmm6, %%xmm8, %%xmm7",
+ "vpsubb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSUBD_128,
+ "vpsubd %%xmm6, %%xmm8, %%xmm7",
+ "vpsubd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPADDD_128,
+ "vpaddd %%xmm6, %%xmm8, %%xmm7",
+ "vpaddd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMOVZXWD_128,
+ "vpmovzxwd %%xmm6, %%xmm8",
+ "vpmovzxwd (%%rax), %%xmm8")
+
+GEN_test_RandM(VPMOVZXBW_128,
+ "vpmovzxbw %%xmm6, %%xmm8",
+ "vpmovzxbw (%%rax), %%xmm8")
+
+GEN_test_RandM(VPBLENDVB_128,
+ "vpblendvb %%xmm9, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendvb %%xmm9, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMINSD_128,
+ "vpminsd %%xmm6, %%xmm8, %%xmm7",
+ "vpminsd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMAXSD_128,
+ "vpmaxsd %%xmm6, %%xmm8, %%xmm7",
+ "vpmaxsd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VANDPD_128,
+ "vandpd %%xmm6, %%xmm8, %%xmm7",
+ "vandpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCVTSI2SD_32,
+ "vcvtsi2sdl %%r14d, %%xmm8, %%xmm7",
+ "vcvtsi2sdl (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCVTSI2SD_64,
+ "vcvtsi2sdq %%r14, %%xmm8, %%xmm7",
+ "vcvtsi2sdq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCVTSI2SS_64,
+ "vcvtsi2ssq %%r14, %%xmm8, %%xmm7",
+ "vcvtsi2ssq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCVTTSD2SI_32,
+ "vcvttsd2si %%xmm8, %%r14d",
+ "vcvttsd2si (%%rax), %%r14d")
+
+GEN_test_RandM(VCVTTSD2SI_64,
+ "vcvttsd2si %%xmm8, %%r14",
+ "vcvttsd2si (%%rax), %%r14")
+
+GEN_test_RandM(VCVTSD2SI_32,
+ "vcvtsd2si %%xmm8, %%r14d",
+ "vcvtsd2si (%%rax), %%r14d")
+
+GEN_test_RandM(VCVTSD2SI_64,
+ "vcvtsd2si %%xmm8, %%r14",
+ "vcvtsd2si (%%rax), %%r14")
+
+GEN_test_RandM(VPSHUFB_128,
+ "vpshufb %%xmm6, %%xmm8, %%xmm7",
+ "vpshufb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCMPSD_128_0x0,
+ "vcmpsd $0, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $0, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x1,
+ "vcmpsd $1, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $1, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x2,
+ "vcmpsd $2, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $2, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x3,
+ "vcmpsd $3, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $3, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x4,
+ "vcmpsd $4, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $4, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x5,
+ "vcmpsd $5, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $5, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x6,
+ "vcmpsd $6, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $6, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x7,
+ "vcmpsd $7, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $7, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0xA,
+ "vcmpsd $0xA, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $0xA, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0xC,
+ "vcmpsd $0xC, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $0xC, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0xD,
+ "vcmpsd $0xD, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $0xD, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0xE,
+ "vcmpsd $0xE, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $0xE, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x11,
+ "vcmpsd $0x11, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $0x11, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x12,
+ "vcmpsd $0x12, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $0x12, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x16,
+ "vcmpsd $0x16, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $0x16, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSD_128_0x1E,
+ "vcmpsd $0x1E, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpsd $0x1E, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VSQRTSD_128,
+ "vsqrtsd %%xmm6, %%xmm8, %%xmm7",
+ "vsqrtsd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VORPS_128,
+ "vorps %%xmm6, %%xmm8, %%xmm7",
+ "vorps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VANDNPS_128,
+ "vandnps %%xmm6, %%xmm8, %%xmm7",
+ "vandnps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMAXSS_128,
+ "vmaxss %%xmm6, %%xmm8, %%xmm7",
+ "vmaxss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMINSS_128,
+ "vminss %%xmm6, %%xmm8, %%xmm7",
+ "vminss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VANDPS_128,
+ "vandps %%xmm6, %%xmm8, %%xmm7",
+ "vandps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCVTSI2SS_128,
+ "vcvtsi2ssl %%r14d, %%xmm8, %%xmm7",
+ "vcvtsi2ssl (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VUNPCKLPS_128,
+ "vunpcklps %%xmm6, %%xmm8, %%xmm7",
+ "vunpcklps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VDIVSS_128,
+ "vdivss %%xmm6, %%xmm8, %%xmm7",
+ "vdivss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VADDSS_128,
+ "vaddss %%xmm6, %%xmm8, %%xmm7",
+ "vaddss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VSUBSS_128,
+ "vsubss %%xmm6, %%xmm8, %%xmm7",
+ "vsubss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMULSS_128,
+ "vmulss %%xmm6, %%xmm8, %%xmm7",
+ "vmulss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPUNPCKLBW_128,
+ "vpunpcklbw %%xmm6, %%xmm8, %%xmm7",
+ "vpunpcklbw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPUNPCKHBW_128,
+ "vpunpckhbw %%xmm6, %%xmm8, %%xmm7",
+ "vpunpckhbw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCVTTSS2SI_32,
+ "vcvttss2si %%xmm8, %%r14d",
+ "vcvttss2si (%%rax), %%r14d")
+
+GEN_test_RandM(VCVTSS2SI_32,
+ "vcvtss2si %%xmm8, %%r14d",
+ "vcvtss2si (%%rax), %%r14d")
+
+GEN_test_RandM(VMOVQ_XMMorMEM64_to_XMM,
+ "vmovq %%xmm7, %%xmm8",
+ "vmovq (%%rax), %%xmm8")
+
+/* NB tests the reg form only */
+GEN_test_Ronly(VMOVQ_XMM_to_IREG64,
+ "vmovq %%xmm7, %%r14")
+
+/* This insn only exists in the reg-reg-reg form. */
+GEN_test_Ronly(VMOVHLPS_128,
+ "vmovhlps %%xmm6, %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPABSD_128,
+ "vpabsd %%xmm6, %%xmm8",
+ "vpabsd (%%rax), %%xmm8")
+
+/* This insn only exists in the reg-reg-reg form. */
+GEN_test_Ronly(VMOVLHPS_128,
+ "vmovlhps %%xmm6, %%xmm8, %%xmm7")
+
+GEN_test_Monly(VMOVNTDQ_128,
+ "vmovntdq %%xmm8, (%%rax)")
+
+GEN_test_Monly(VMOVNTDQ_256,
+ "vmovntdq %%ymm8, (%%rax)")
+
+GEN_test_RandM(VMOVUPS_XMM_to_XMMorMEM,
+ "vmovups %%xmm8, %%xmm7",
+ "vmovups %%xmm9, (%%rax)")
+
+GEN_test_RandM(VMOVQ_IREGorMEM64_to_XMM,
+ "vmovq %%r14, %%xmm7",
+ "vmovq (%%rax), %%xmm9")
+
+GEN_test_RandM(VPCMPESTRM_0x45_128,
+ "vpcmpestrm $0x45, %%xmm7, %%xmm8; movapd %%xmm0, %%xmm9",
+ "vpcmpestrm $0x45, (%%rax), %%xmm8; movapd %%xmm0, %%xmm9")
+
+/* NB tests the reg form only */
+GEN_test_Ronly(VMOVD_XMM_to_IREG32,
+ "vmovd %%xmm7, %%r14d")
+
+GEN_test_RandM(VCVTSD2SS_128,
+ "vcvtsd2ss %%xmm9, %%xmm8, %%xmm7",
+ "vcvtsd2ss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCVTSS2SD_128,
+ "vcvtss2sd %%xmm9, %%xmm8, %%xmm7",
+ "vcvtss2sd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPACKUSWB_128,
+ "vpackuswb %%xmm9, %%xmm8, %%xmm7",
+ "vpackuswb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCVTTSS2SI_64,
+ "vcvttss2si %%xmm8, %%r14",
+ "vcvttss2si (%%rax), %%r14")
+
+GEN_test_RandM(VCVTSS2SI_64,
+ "vcvtss2si %%xmm8, %%r14",
+ "vcvtss2si (%%rax), %%r14")
+
+GEN_test_Ronly(VPMOVMSKB_128,
+ "vpmovmskb %%xmm8, %%r14")
+
+GEN_test_RandM(VPAND_128,
+ "vpand %%xmm9, %%xmm8, %%xmm7",
+ "vpand (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Monly(VMOVHPD_128_StoreForm,
+ "vmovhpd %%xmm8, (%%rax)")
+
+GEN_test_Monly(VMOVHPS_128_StoreForm,
+ "vmovhps %%xmm8, (%%rax)")
+
+GEN_test_RandM(VPCMPEQB_128,
+ "vpcmpeqb %%xmm9, %%xmm8, %%xmm7",
+ "vpcmpeqb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VSHUFPS_0x39_128,
+ "vshufps $0x39, %%xmm9, %%xmm8, %%xmm7",
+ "vshufps $0xC6, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMULPS_128,
+ "vmulps %%xmm9, %%xmm8, %%xmm7",
+ "vmulps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VSUBPS_128,
+ "vsubps %%xmm9, %%xmm8, %%xmm7",
+ "vsubps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VADDPS_128,
+ "vaddps %%xmm9, %%xmm8, %%xmm7",
+ "vaddps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMAXPS_128,
+ "vmaxps %%xmm9, %%xmm8, %%xmm7",
+ "vmaxps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMAXPS_256,
+ "vmaxps %%ymm9, %%ymm8, %%ymm7",
+ "vmaxps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VMAXPD_128,
+ "vmaxpd %%xmm9, %%xmm8, %%xmm7",
+ "vmaxpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMAXPD_256,
+ "vmaxpd %%ymm9, %%ymm8, %%ymm7",
+ "vmaxpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VMINPS_128,
+ "vminps %%xmm9, %%xmm8, %%xmm7",
+ "vminps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMINPS_256,
+ "vminps %%ymm9, %%ymm8, %%ymm7",
+ "vminps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VMINPD_128,
+ "vminpd %%xmm9, %%xmm8, %%xmm7",
+ "vminpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMINPD_256,
+ "vminpd %%ymm9, %%ymm8, %%ymm7",
+ "vminpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VCVTPS2DQ_128,
+ "vcvtps2dq %%xmm8, %%xmm7",
+ "vcvtps2dq (%%rax), %%xmm8")
+
+GEN_test_RandM(VPSHUFLW_0x39_128,
+ "vpshuflw $0x39, %%xmm9, %%xmm7",
+ "vpshuflw $0xC6, (%%rax), %%xmm8")
+
+GEN_test_RandM(VPSHUFHW_0x39_128,
+ "vpshufhw $0x39, %%xmm9, %%xmm7",
+ "vpshufhw $0xC6, (%%rax), %%xmm8")
+
+GEN_test_RandM(VPMULLW_128,
+ "vpmullw %%xmm9, %%xmm8, %%xmm7",
+ "vpmullw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPADDUSW_128,
+ "vpaddusw %%xmm9, %%xmm8, %%xmm7",
+ "vpaddusw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMULHUW_128,
+ "vpmulhuw %%xmm9, %%xmm8, %%xmm7",
+ "vpmulhuw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPADDUSB_128,
+ "vpaddusb %%xmm9, %%xmm8, %%xmm7",
+ "vpaddusb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPUNPCKLWD_128,
+ "vpunpcklwd %%xmm6, %%xmm8, %%xmm7",
+ "vpunpcklwd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPUNPCKHWD_128,
+ "vpunpckhwd %%xmm6, %%xmm8, %%xmm7",
+ "vpunpckhwd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Ronly(VPSLLD_0x05_128,
+ "vpslld $0x5, %%xmm9, %%xmm7")
+
+GEN_test_Ronly(VPSRLD_0x05_128,
+ "vpsrld $0x5, %%xmm9, %%xmm7")
+
+GEN_test_Ronly(VPSRAD_0x05_128,
+ "vpsrad $0x5, %%xmm9, %%xmm7")
+
+GEN_test_RandM(VPSUBUSB_128,
+ "vpsubusb %%xmm9, %%xmm8, %%xmm7",
+ "vpsubusb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSUBSB_128,
+ "vpsubsb %%xmm9, %%xmm8, %%xmm7",
+ "vpsubsb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Ronly(VPSRLDQ_0x05_128,
+ "vpsrldq $0x5, %%xmm9, %%xmm7")
+
+GEN_test_Ronly(VPSLLDQ_0x05_128,
+ "vpslldq $0x5, %%xmm9, %%xmm7")
+
+GEN_test_RandM(VPANDN_128,
+ "vpandn %%xmm9, %%xmm8, %%xmm7",
+ "vpandn (%%rax), %%xmm8, %%xmm7")
+
+/* NB tests the mem form only */
+GEN_test_Monly(VMOVD_XMM_to_MEM32,
+ "vmovd %%xmm7, (%%rax)")
+
+GEN_test_RandM(VPINSRD_128,
+ "vpinsrd $0, %%r14d, %%xmm8, %%xmm7",
+ "vpinsrd $3, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPUNPCKLQDQ_128,
+ "vpunpcklqdq %%xmm6, %%xmm8, %%xmm7",
+ "vpunpcklqdq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Ronly(VPSRLW_0x05_128,
+ "vpsrlw $0x5, %%xmm9, %%xmm7")
+
+GEN_test_Ronly(VPSLLW_0x05_128,
+ "vpsllw $0x5, %%xmm9, %%xmm7")
+
+GEN_test_RandM(VPADDW_128,
+ "vpaddw %%xmm6, %%xmm8, %%xmm7",
+ "vpaddw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPACKSSDW_128,
+ "vpackssdw %%xmm9, %%xmm8, %%xmm7",
+ "vpackssdw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPUNPCKLDQ_128,
+ "vpunpckldq %%xmm6, %%xmm8, %%xmm7",
+ "vpunpckldq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VINSERTPS_0x39_128,
+ "vinsertps $0x39, %%xmm6, %%xmm8, %%xmm7",
+ "vinsertps $0xC6, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Monly(VMOVSD_M64_XMM, "vmovsd (%%rax), %%xmm8")
+
+GEN_test_Monly(VMOVSS_M64_XMM, "vmovss (%%rax), %%xmm8")
+
+GEN_test_Monly(VMOVSD_XMM_M64, "vmovsd %%xmm8, (%%rax)")
+
+GEN_test_Monly(VMOVSS_XMM_M32, "vmovss %%xmm8, (%%rax)")
+
+GEN_test_RandM(VMOVUPD_GtoE_128,
+ "vmovupd %%xmm9, %%xmm6",
+ "vmovupd %%xmm7, (%%rax)")
+
+GEN_test_RandM(VMOVAPD_EtoG_128,
+ "vmovapd %%xmm6, %%xmm8",
+ "vmovapd (%%rax), %%xmm9")
+
+GEN_test_RandM(VMOVAPD_EtoG_256,
+ "vmovapd %%ymm6, %%ymm8",
+ "vmovapd (%%rax), %%ymm9")
+
+GEN_test_RandM(VMOVAPS_EtoG_128,
+ "vmovaps %%xmm6, %%xmm8",
+ "vmovaps (%%rax), %%xmm9")
+
+GEN_test_RandM(VMOVAPS_GtoE_128,
+ "vmovaps %%xmm9, %%xmm6",
+ "vmovaps %%xmm7, (%%rax)")
+
+GEN_test_RandM(VMOVAPS_GtoE_256,
+ "vmovaps %%ymm9, %%ymm6",
+ "vmovaps %%ymm7, (%%rax)")
+
+GEN_test_RandM(VMOVAPD_GtoE_128,
+ "vmovapd %%xmm9, %%xmm6",
+ "vmovapd %%xmm7, (%%rax)")
+
+GEN_test_RandM(VMOVAPD_GtoE_256,
+ "vmovapd %%ymm9, %%ymm6",
+ "vmovapd %%ymm7, (%%rax)")
+
+GEN_test_RandM(VMOVDQU_EtoG_128,
+ "vmovdqu %%xmm6, %%xmm8",
+ "vmovdqu (%%rax), %%xmm9")
+
+GEN_test_RandM(VMOVDQA_EtoG_128,
+ "vmovdqa %%xmm6, %%xmm8",
+ "vmovdqa (%%rax), %%xmm9")
+
+GEN_test_RandM(VMOVDQA_EtoG_256,
+ "vmovdqa %%ymm6, %%ymm8",
+ "vmovdqa (%%rax), %%ymm9")
+
+GEN_test_RandM(VMOVDQU_GtoE_128,
+ "vmovdqu %%xmm9, %%xmm6",
+ "vmovdqu %%xmm7, (%%rax)")
+
+GEN_test_RandM(VMOVDQA_GtoE_128,
+ "vmovdqa %%xmm9, %%xmm6",
+ "vmovdqa %%xmm7, (%%rax)")
+
+GEN_test_RandM(VMOVDQA_GtoE_256,
+ "vmovdqa %%ymm9, %%ymm6",
+ "vmovdqa %%ymm7, (%%rax)")
+
+GEN_test_Monly(VMOVQ_XMM_MEM64, "vmovq %%xmm8, (%%rax)")
+
+GEN_test_RandM(VMOVD_IREGorMEM32_to_XMM,
+ "vmovd %%r14d, %%xmm7",
+ "vmovd (%%rax), %%xmm9")
+
+GEN_test_RandM(VMOVDDUP_XMMorMEM64_to_XMM,
+ "vmovddup %%xmm8, %%xmm7",
+ "vmovddup (%%rax), %%xmm9")
+
+GEN_test_RandM(VCMPSS_128_0x0,
+ "vcmpss $0, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x1,
+ "vcmpss $1, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $1, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x2,
+ "vcmpss $2, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $2, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x3,
+ "vcmpss $3, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $3, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x4,
+ "vcmpss $4, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $4, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x5,
+ "vcmpss $5, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $5, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x6,
+ "vcmpss $6, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $6, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x7,
+ "vcmpss $7, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $7, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0xA,
+ "vcmpss $0xA, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0xA, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0xC,
+ "vcmpss $0xC, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0xC, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0xD,
+ "vcmpss $0xD, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0xD, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0xE,
+ "vcmpss $0xE, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0xE, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x11,
+ "vcmpss $0x11, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0x11, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x12,
+ "vcmpss $0x12, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0x12, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x16,
+ "vcmpss $0x16, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0x16, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VCMPSS_128_0x1E,
+ "vcmpss $0x1E, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0x1E, (%%rax), %%xmm8, %%xmm7")
+
+// The x suffix denotes a 128 -> 64 operation
+GEN_test_RandM(VCVTPD2PS_128,
+ "vcvtpd2psx %%xmm8, %%xmm7",
+ "vcvtpd2psx (%%rax), %%xmm9")
+
+GEN_test_RandM(VEXTRACTF128_0x0,
+ "vextractf128 $0x0, %%ymm7, %%xmm9",
+ "vextractf128 $0x0, %%ymm7, (%%rax)")
+
+GEN_test_RandM(VEXTRACTF128_0x1,
+ "vextractf128 $0x1, %%ymm7, %%xmm9",
+ "vextractf128 $0x1, %%ymm7, (%%rax)")
+
+GEN_test_RandM(VINSERTF128_0x0,
+ "vinsertf128 $0x0, %%xmm9, %%ymm7, %%ymm8",
+ "vinsertf128 $0x0, (%%rax), %%ymm7, %%ymm8")
+
+GEN_test_RandM(VINSERTF128_0x1,
+ "vinsertf128 $0x1, %%xmm9, %%ymm7, %%ymm8",
+ "vinsertf128 $0x1, (%%rax), %%ymm7, %%ymm8")
+
+GEN_test_RandM(VPEXTRD_128_0x0,
+ "vpextrd $0x0, %%xmm7, %%r14d",
+ "vpextrd $0x0, %%xmm7, (%%rax)")
+
+GEN_test_RandM(VPEXTRD_128_0x3,
+ "vpextrd $0x3, %%xmm7, %%r14d",
+ "vpextrd $0x3, %%xmm7, (%%rax)")
+
+GEN_test_RandM(VPCMPEQD_128,
+ "vpcmpeqd %%xmm6, %%xmm8, %%xmm7",
+ "vpcmpeqd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSHUFD_0x39_128,
+ "vpshufd $0x39, %%xmm9, %%xmm8",
+ "vpshufd $0xC6, (%%rax), %%xmm7")
+
+GEN_test_RandM(VMAXSD_128,
+ "vmaxsd %%xmm6, %%xmm8, %%xmm7",
+ "vmaxsd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VDIVSD_128,
+ "vdivsd %%xmm6, %%xmm8, %%xmm7",
+ "vdivsd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMINSD_128,
+ "vminsd %%xmm6, %%xmm8, %%xmm7",
+ "vminsd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VSUBSD_128,
+ "vsubsd %%xmm6, %%xmm8, %%xmm7",
+ "vsubsd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VADDSD_128,
+ "vaddsd %%xmm6, %%xmm8, %%xmm7",
+ "vaddsd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMULSD_128,
+ "vmulsd %%xmm6, %%xmm8, %%xmm7",
+ "vmulsd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VXORPS_128,
+ "vxorps %%xmm6, %%xmm8, %%xmm7",
+ "vxorps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VXORPD_128,
+ "vxorpd %%xmm6, %%xmm8, %%xmm7",
+ "vxorpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VORPD_128,
+ "vorpd %%xmm6, %%xmm8, %%xmm7",
+ "vorpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VANDNPD_128,
+ "vandnpd %%xmm6, %%xmm8, %%xmm7",
+ "vandnpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCVTPS2PD_128,
+ "vcvtps2pd %%xmm6, %%xmm8",
+ "vcvtps2pd (%%rax), %%xmm8")
+
+GEN_test_RandM(VUCOMISD_128,
+ "vucomisd %%xmm6, %%xmm8; pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vucomisd (%%rax), %%xmm8; pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VUCOMISS_128,
+ "vucomiss %%xmm6, %%xmm8; pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vucomiss (%%rax), %%xmm8; pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VPINSRQ_128,
+ "vpinsrq $0, %%r14, %%xmm8, %%xmm7",
+ "vpinsrq $1, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPADDQ_128,
+ "vpaddq %%xmm6, %%xmm8, %%xmm7",
+ "vpaddq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSUBQ_128,
+ "vpsubq %%xmm6, %%xmm8, %%xmm7",
+ "vpsubq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSUBW_128,
+ "vpsubw %%xmm6, %%xmm8, %%xmm7",
+ "vpsubw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMOVUPD_GtoE_256,
+ "vmovupd %%ymm9, %%ymm6",
+ "vmovupd %%ymm7, (%%rax)")
+
+GEN_test_RandM(VMOVUPD_EtoG_256,
+ "vmovupd %%ymm6, %%ymm9",
+ "vmovupd (%%rax), %%ymm7")
+
+GEN_test_RandM(VMULPD_256,
+ "vmulpd %%ymm6, %%ymm8, %%ymm7",
+ "vmulpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VMOVUPD_EtoG_128,
+ "vmovupd %%xmm6, %%xmm9",
+ "vmovupd (%%rax), %%xmm7")
+
+GEN_test_RandM(VADDPD_256,
+ "vaddpd %%ymm6, %%ymm8, %%ymm7",
+ "vaddpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VSUBPD_256,
+ "vsubpd %%ymm6, %%ymm8, %%ymm7",
+ "vsubpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VDIVPD_256,
+ "vdivpd %%ymm6, %%ymm8, %%ymm7",
+ "vdivpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPCMPEQQ_128,
+ "vpcmpeqq %%xmm6, %%xmm8, %%xmm7",
+ "vpcmpeqq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VSUBPD_128,
+ "vsubpd %%xmm6, %%xmm8, %%xmm7",
+ "vsubpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VADDPD_128,
+ "vaddpd %%xmm6, %%xmm8, %%xmm7",
+ "vaddpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VUNPCKLPD_128,
+ "vunpcklpd %%xmm6, %%xmm8, %%xmm7",
+ "vunpcklpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VUNPCKHPD_128,
+ "vunpckhpd %%xmm6, %%xmm8, %%xmm7",
+ "vunpckhpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VUNPCKHPS_128,
+ "vunpckhps %%xmm6, %%xmm8, %%xmm7",
+ "vunpckhps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMOVUPS_EtoG_128,
+ "vmovups %%xmm6, %%xmm8",
+ "vmovups (%%rax), %%xmm9")
+
+GEN_test_RandM(VADDPS_256,
+ "vaddps %%ymm6, %%ymm8, %%ymm7",
+ "vaddps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VSUBPS_256,
+ "vsubps %%ymm6, %%ymm8, %%ymm7",
+ "vsubps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VMULPS_256,
+ "vmulps %%ymm6, %%ymm8, %%ymm7",
+ "vmulps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VDIVPS_256,
+ "vdivps %%ymm6, %%ymm8, %%ymm7",
+ "vdivps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPCMPGTQ_128,
+ "vpcmpgtq %%xmm6, %%xmm8, %%xmm7",
+ "vpcmpgtq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPEXTRQ_128_0x0,
+ "vpextrq $0x0, %%xmm7, %%r14",
+ "vpextrq $0x0, %%xmm7, (%%rax)")
+
+GEN_test_RandM(VPEXTRQ_128_0x1,
+ "vpextrq $0x1, %%xmm7, %%r14",
+ "vpextrq $0x1, %%xmm7, (%%rax)")
+
+GEN_test_Ronly(VPSRLQ_0x05_128,
+ "vpsrlq $0x5, %%xmm9, %%xmm7")
+
+GEN_test_RandM(VPMULUDQ_128,
+ "vpmuludq %%xmm6, %%xmm8, %%xmm7",
+ "vpmuludq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMULDQ_128,
+ "vpmuldq %%xmm6, %%xmm8, %%xmm7",
+ "vpmuldq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Ronly(VPSLLQ_0x05_128,
+ "vpsllq $0x5, %%xmm9, %%xmm7")
+
+GEN_test_RandM(VPMAXUD_128,
+ "vpmaxud %%xmm6, %%xmm8, %%xmm7",
+ "vpmaxud (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMINUD_128,
+ "vpminud %%xmm6, %%xmm8, %%xmm7",
+ "vpminud (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMULLD_128,
+ "vpmulld %%xmm6, %%xmm8, %%xmm7",
+ "vpmulld (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMAXUW_128,
+ "vpmaxuw %%xmm6, %%xmm8, %%xmm7",
+ "vpmaxuw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Ronly(VPEXTRW_128_EregOnly_toG_0x0,
+ "vpextrw $0x0, %%xmm7, %%r14d")
+
+GEN_test_Ronly(VPEXTRW_128_EregOnly_toG_0x7,
+ "vpextrw $0x7, %%xmm7, %%r14d")
+
+GEN_test_RandM(VPMINUW_128,
+ "vpminuw %%xmm6, %%xmm8, %%xmm7",
+ "vpminuw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPHMINPOSUW_128,
+ "vphminposuw %%xmm6, %%xmm8",
+ "vphminposuw (%%rax), %%xmm7")
+
+GEN_test_RandM(VPMAXSW_128,
+ "vpmaxsw %%xmm6, %%xmm8, %%xmm7",
+ "vpmaxsw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMINSW_128,
+ "vpminsw %%xmm6, %%xmm8, %%xmm7",
+ "vpminsw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMAXUB_128,
+ "vpmaxub %%xmm6, %%xmm8, %%xmm7",
+ "vpmaxub (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPEXTRB_GtoE_128_0x0,
+ "vpextrb $0x0, %%xmm8, %%r14",
+ "vpextrb $0x0, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VPEXTRB_GtoE_128_0x1,
+ "vpextrb $0x1, %%xmm8, %%r14",
+ "vpextrb $0x1, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VPEXTRB_GtoE_128_0x2,
+ "vpextrb $0x2, %%xmm8, %%r14",
+ "vpextrb $0x2, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VPEXTRB_GtoE_128_0x3,
+ "vpextrb $0x3, %%xmm8, %%r14",
+ "vpextrb $0x3, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VPEXTRB_GtoE_128_0x4,
+ "vpextrb $0x4, %%xmm8, %%r14",
+ "vpextrb $0x4, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VPEXTRB_GtoE_128_0x9,
+ "vpextrb $0x9, %%xmm8, %%r14",
+ "vpextrb $0x9, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VPEXTRB_GtoE_128_0xE,
+ "vpextrb $0xE, %%xmm8, %%r14",
+ "vpextrb $0xE, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VPEXTRB_GtoE_128_0xF,
+ "vpextrb $0xF, %%xmm8, %%r14",
+ "vpextrb $0xF, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VPMINUB_128,
+ "vpminub %%xmm6, %%xmm8, %%xmm7",
+ "vpminub (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMAXSB_128,
+ "vpmaxsb %%xmm6, %%xmm8, %%xmm7",
+ "vpmaxsb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMINSB_128,
+ "vpminsb %%xmm6, %%xmm8, %%xmm7",
+ "vpminsb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPERM2F128_0x00,
+ "vperm2f128 $0x00, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2f128 $0x00, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2F128_0xFF,
+ "vperm2f128 $0xFF, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2f128 $0xFF, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2F128_0x30,
+ "vperm2f128 $0x30, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2f128 $0x30, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2F128_0x21,
+ "vperm2f128 $0x21, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2f128 $0x21, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2F128_0x12,
+ "vperm2f128 $0x12, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2f128 $0x12, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2F128_0x03,
+ "vperm2f128 $0x03, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2f128 $0x03, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2F128_0x85,
+ "vperm2f128 $0x85, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2f128 $0x85, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VPERM2F128_0x5A,
+ "vperm2f128 $0x5A, %%ymm6, %%ymm8, %%ymm7",
+ "vperm2f128 $0x5A, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPERMILPD_256_0x0,
+ "vpermilpd $0x0, %%ymm6, %%ymm8",
+ "vpermilpd $0x1, (%%rax), %%ymm8")
+GEN_test_RandM(VPERMILPD_256_0xF,
+ "vpermilpd $0xF, %%ymm6, %%ymm8",
+ "vpermilpd $0xE, (%%rax), %%ymm8")
+GEN_test_RandM(VPERMILPD_256_0xA,
+ "vpermilpd $0xA, %%ymm6, %%ymm8",
+ "vpermilpd $0xB, (%%rax), %%ymm8")
+GEN_test_RandM(VPERMILPD_256_0x5,
+ "vpermilpd $0x5, %%ymm6, %%ymm8",
+ "vpermilpd $0x4, (%%rax), %%ymm8")
+
+GEN_test_RandM(VPERMILPD_128_0x0,
+ "vpermilpd $0x0, %%xmm6, %%xmm8",
+ "vpermilpd $0x1, (%%rax), %%xmm8")
+GEN_test_RandM(VPERMILPD_128_0x3,
+ "vpermilpd $0x3, %%xmm6, %%xmm8",
+ "vpermilpd $0x2, (%%rax), %%xmm8")
+
+GEN_test_RandM(VUNPCKLPD_256,
+ "vunpcklpd %%ymm6, %%ymm8, %%ymm7",
+ "vunpcklpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VUNPCKHPD_256,
+ "vunpckhpd %%ymm6, %%ymm8, %%ymm7",
+ "vunpckhpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VSHUFPS_0x39_256,
+ "vshufps $0x39, %%ymm9, %%ymm8, %%ymm7",
+ "vshufps $0xC6, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VUNPCKLPS_256,
+ "vunpcklps %%ymm6, %%ymm8, %%ymm7",
+ "vunpcklps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VUNPCKHPS_256,
+ "vunpckhps %%ymm6, %%ymm8, %%ymm7",
+ "vunpckhps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VXORPD_256,
+ "vxorpd %%ymm6, %%ymm8, %%ymm7",
+ "vxorpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_Monly(VBROADCASTSD_256,
+ "vbroadcastsd (%%rax), %%ymm8")
+
+GEN_test_RandM(VCMPPD_128_0x4,
+ "vcmppd $4, %%xmm6, %%xmm8, %%xmm7",
+ "vcmppd $4, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCMPPD_256_0x4,
+ "vcmppd $4, %%ymm6, %%ymm8, %%ymm7",
+ "vcmppd $4, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VCMPPS_128_0x4,
+ "vcmpps $4, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpps $4, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCMPPS_256_0x4,
+ "vcmpps $4, %%ymm6, %%ymm8, %%ymm7",
+ "vcmpps $4, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VCVTDQ2PD_128,
+ "vcvtdq2pd %%xmm6, %%xmm8",
+ "vcvtdq2pd (%%rax), %%xmm8")
+
+GEN_test_RandM(VDIVPD_128,
+ "vdivpd %%xmm6, %%xmm8, %%xmm7",
+ "vdivpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VANDPD_256,
+ "vandpd %%ymm6, %%ymm8, %%ymm7",
+ "vandpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPMOVSXBW_128,
+ "vpmovsxbw %%xmm6, %%xmm8",
+ "vpmovsxbw (%%rax), %%xmm8")
+
+GEN_test_RandM(VPSUBUSW_128,
+ "vpsubusw %%xmm9, %%xmm8, %%xmm7",
+ "vpsubusw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSUBSW_128,
+ "vpsubsw %%xmm9, %%xmm8, %%xmm7",
+ "vpsubsw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPCMPEQW_128,
+ "vpcmpeqw %%xmm6, %%xmm8, %%xmm7",
+ "vpcmpeqw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPADDB_128,
+ "vpaddb %%xmm6, %%xmm8, %%xmm7",
+ "vpaddb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMOVAPS_EtoG_256,
+ "vmovaps %%ymm6, %%ymm8",
+ "vmovaps (%%rax), %%ymm9")
+
+GEN_test_RandM(VCVTDQ2PD_256,
+ "vcvtdq2pd %%xmm6, %%ymm8",
+ "vcvtdq2pd (%%rax), %%ymm8")
+
+GEN_test_Monly(VMOVHPD_128_LoadForm,
+ "vmovhpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Monly(VMOVHPS_128_LoadForm,
+ "vmovhps (%%rax), %%xmm8, %%xmm7")
+
+// The y suffix denotes a 256 -> 128 operation
+GEN_test_RandM(VCVTPD2PS_256,
+ "vcvtpd2psy %%ymm8, %%xmm7",
+ "vcvtpd2psy (%%rax), %%xmm9")
+
+GEN_test_RandM(VPUNPCKHDQ_128,
+ "vpunpckhdq %%xmm6, %%xmm8, %%xmm7",
+ "vpunpckhdq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Monly(VBROADCASTSS_128,
+ "vbroadcastss (%%rax), %%xmm8")
+
+GEN_test_RandM(VPMOVSXDQ_128,
+ "vpmovsxdq %%xmm6, %%xmm8",
+ "vpmovsxdq (%%rax), %%xmm8")
+
+GEN_test_RandM(VPMOVSXWD_128,
+ "vpmovsxwd %%xmm6, %%xmm8",
+ "vpmovsxwd (%%rax), %%xmm8")
+
+GEN_test_RandM(VDIVPS_128,
+ "vdivps %%xmm9, %%xmm8, %%xmm7",
+ "vdivps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VANDPS_256,
+ "vandps %%ymm6, %%ymm8, %%ymm7",
+ "vandps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VXORPS_256,
+ "vxorps %%ymm6, %%ymm8, %%ymm7",
+ "vxorps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VORPS_256,
+ "vorps %%ymm6, %%ymm8, %%ymm7",
+ "vorps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VANDNPD_256,
+ "vandnpd %%ymm6, %%ymm8, %%ymm7",
+ "vandnpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VANDNPS_256,
+ "vandnps %%ymm6, %%ymm8, %%ymm7",
+ "vandnps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VORPD_256,
+ "vorpd %%ymm6, %%ymm8, %%ymm7",
+ "vorpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPERMILPS_256_0x0F,
+ "vpermilps $0x0F, %%ymm6, %%ymm8",
+ "vpermilps $0x1E, (%%rax), %%ymm8")
+GEN_test_RandM(VPERMILPS_256_0xFA,
+ "vpermilps $0xFA, %%ymm6, %%ymm8",
+ "vpermilps $0xE5, (%%rax), %%ymm8")
+GEN_test_RandM(VPERMILPS_256_0xA3,
+ "vpermilps $0xA3, %%ymm6, %%ymm8",
+ "vpermilps $0xB4, (%%rax), %%ymm8")
+GEN_test_RandM(VPERMILPS_256_0x5A,
+ "vpermilps $0x5A, %%ymm6, %%ymm8",
+ "vpermilps $0x45, (%%rax), %%ymm8")
+
+GEN_test_RandM(VPMULHW_128,
+ "vpmulhw %%xmm9, %%xmm8, %%xmm7",
+ "vpmulhw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPUNPCKHQDQ_128,
+ "vpunpckhqdq %%xmm6, %%xmm8, %%xmm7",
+ "vpunpckhqdq (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Ronly(VPSRAW_0x05_128,
+ "vpsraw $0x5, %%xmm9, %%xmm7")
+
+GEN_test_RandM(VPCMPGTB_128,
+ "vpcmpgtb %%xmm6, %%xmm8, %%xmm7",
+ "vpcmpgtb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPCMPGTW_128,
+ "vpcmpgtw %%xmm6, %%xmm8, %%xmm7",
+ "vpcmpgtw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPCMPGTD_128,
+ "vpcmpgtd %%xmm6, %%xmm8, %%xmm7",
+ "vpcmpgtd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMOVZXBD_128,
+ "vpmovzxbd %%xmm6, %%xmm8",
+ "vpmovzxbd (%%rax), %%xmm8")
+
+GEN_test_RandM(VPMOVSXBD_128,
+ "vpmovsxbd %%xmm6, %%xmm8",
+ "vpmovsxbd (%%rax), %%xmm8")
+
+GEN_test_RandM(VPINSRB_128_1of3,
+ "vpinsrb $0, %%r14d, %%xmm8, %%xmm7",
+ "vpinsrb $3, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPINSRB_128_2of3,
+ "vpinsrb $6, %%r14d, %%xmm8, %%xmm7",
+ "vpinsrb $9, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPINSRB_128_3of3,
+ "vpinsrb $12, %%r14d, %%xmm8, %%xmm7",
+ "vpinsrb $15, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPINSRW_128_1of4,
+ "vpinsrw $0, %%r14d, %%xmm8, %%xmm7",
+ "vpinsrw $3, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPINSRW_128_2of4,
+ "vpinsrw $2, %%r14d, %%xmm8, %%xmm7",
+ "vpinsrw $3, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPINSRW_128_3of4,
+ "vpinsrw $4, %%r14d, %%xmm8, %%xmm7",
+ "vpinsrw $5, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPINSRW_128_4of4,
+ "vpinsrw $6, %%r14d, %%xmm8, %%xmm7",
+ "vpinsrw $7, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCOMISD_128,
+ "vcomisd %%xmm6, %%xmm8; pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vcomisd (%%rax), %%xmm8; pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VCOMISS_128,
+ "vcomiss %%xmm6, %%xmm8; pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vcomiss (%%rax), %%xmm8; pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VMOVUPS_YMM_to_YMMorMEM,
+ "vmovups %%ymm8, %%ymm7",
+ "vmovups %%ymm9, (%%rax)")
+
+GEN_test_RandM(VDPPD_128_1of4,
+ "vdppd $0x00, %%xmm6, %%xmm8, %%xmm7",
+ "vdppd $0xA5, (%%rax), %%xmm9, %%xmm6")
+GEN_test_RandM(VDPPD_128_2of4,
+ "vdppd $0x5A, %%xmm6, %%xmm8, %%xmm7",
+ "vdppd $0xFF, (%%rax), %%xmm9, %%xmm6")
+GEN_test_RandM(VDPPD_128_3of4,
+ "vdppd $0x0F, %%xmm6, %%xmm8, %%xmm7",
+ "vdppd $0x37, (%%rax), %%xmm9, %%xmm6")
+GEN_test_RandM(VDPPD_128_4of4,
+ "vdppd $0xF0, %%xmm6, %%xmm8, %%xmm7",
+ "vdppd $0x73, (%%rax), %%xmm9, %%xmm6")
+
+GEN_test_RandM(VDPPS_128_1of4,
+ "vdpps $0x00, %%xmm6, %%xmm8, %%xmm7",
+ "vdpps $0xA5, (%%rax), %%xmm9, %%xmm6")
+GEN_test_RandM(VDPPS_128_2of4,
+ "vdpps $0x5A, %%xmm6, %%xmm8, %%xmm7",
+ "vdpps $0xFF, (%%rax), %%xmm9, %%xmm6")
+GEN_test_RandM(VDPPS_128_3of4,
+ "vdpps $0x0F, %%xmm6, %%xmm8, %%xmm7",
+ "vdpps $0x37, (%%rax), %%xmm9, %%xmm6")
+GEN_test_RandM(VDPPS_128_4of4,
+ "vdpps $0xF0, %%xmm6, %%xmm8, %%xmm7",
+ "vdpps $0x73, (%%rax), %%xmm9, %%xmm6")
+
+GEN_test_RandM(VDPPS_256_1of4,
+ "vdpps $0x00, %%ymm6, %%ymm8, %%ymm7",
+ "vdpps $0xA5, (%%rax), %%ymm9, %%ymm6")
+GEN_test_RandM(VDPPS_256_2of4,
+ "vdpps $0x5A, %%ymm6, %%ymm8, %%ymm7",
+ "vdpps $0xFF, (%%rax), %%ymm9, %%ymm6")
+GEN_test_RandM(VDPPS_256_3of4,
+ "vdpps $0x0F, %%ymm6, %%ymm8, %%ymm7",
+ "vdpps $0x37, (%%rax), %%ymm9, %%ymm6")
+GEN_test_RandM(VDPPS_256_4of4,
+ "vdpps $0xF0, %%ymm6, %%ymm8, %%ymm7",
+ "vdpps $0x73, (%%rax), %%ymm9, %%ymm6")
+
+GEN_test_Monly(VBROADCASTSS_256,
+ "vbroadcastss (%%rax), %%ymm8")
+
+GEN_test_RandM(VPALIGNR_128_1of3,
+ "vpalignr $0, %%xmm6, %%xmm8, %%xmm7",
+ "vpalignr $3, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPALIGNR_128_2of3,
+ "vpalignr $6, %%xmm6, %%xmm8, %%xmm7",
+ "vpalignr $9, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPALIGNR_128_3of3,
+ "vpalignr $12, %%xmm6, %%xmm8, %%xmm7",
+ "vpalignr $15, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Ronly(VMOVSD_REG_XMM, "vmovsd %%xmm9, %%xmm7, %%xmm8")
+
+GEN_test_Ronly(VMOVSS_REG_XMM, "vmovss %%xmm9, %%xmm7, %%xmm8")
+
+GEN_test_Monly(VMOVLPD_128_M64_XMM_XMM, "vmovlpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Monly(VMOVLPD_128_XMM_M64, "vmovlpd %%xmm7, (%%rax)")
+
+GEN_test_RandM(VSHUFPD_128_1of2,
+ "vshufpd $0, %%xmm9, %%xmm8, %%xmm7",
+ "vshufpd $1, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VSHUFPD_128_2of2,
+ "vshufpd $2, %%xmm9, %%xmm8, %%xmm7",
+ "vshufpd $3, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VSHUFPD_256_1of2,
+ "vshufpd $0x00, %%ymm9, %%ymm8, %%ymm7",
+ "vshufpd $0xFF, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VSHUFPD_256_2of2,
+ "vshufpd $0x5A, %%ymm9, %%ymm8, %%ymm7",
+ "vshufpd $0xA5, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPERMILPS_128_0x00,
+ "vpermilps $0x00, %%xmm6, %%xmm8",
+ "vpermilps $0x01, (%%rax), %%xmm8")
+GEN_test_RandM(VPERMILPS_128_0xFE,
+ "vpermilps $0xFE, %%xmm6, %%xmm8",
+ "vpermilps $0xFF, (%%rax), %%xmm8")
+GEN_test_RandM(VPERMILPS_128_0x30,
+ "vpermilps $0x30, %%xmm6, %%xmm8",
+ "vpermilps $0x03, (%%rax), %%xmm8")
+GEN_test_RandM(VPERMILPS_128_0x21,
+ "vpermilps $0x21, %%xmm6, %%xmm8",
+ "vpermilps $0x12, (%%rax), %%xmm8")
+GEN_test_RandM(VPERMILPS_128_0xD7,
+ "vpermilps $0xD7, %%xmm6, %%xmm8",
+ "vpermilps $0x6C, (%%rax), %%xmm8")
+GEN_test_RandM(VPERMILPS_128_0xB5,
+ "vpermilps $0xB5, %%xmm6, %%xmm8",
+ "vpermilps $0x4A, (%%rax), %%xmm8")
+GEN_test_RandM(VPERMILPS_128_0x85,
+ "vpermilps $0x85, %%xmm6, %%xmm8",
+ "vpermilps $0xDC, (%%rax), %%xmm8")
+GEN_test_RandM(VPERMILPS_128_0x29,
+ "vpermilps $0x29, %%xmm6, %%xmm8",
+ "vpermilps $0x92, (%%rax), %%xmm8")
+
+GEN_test_RandM(VBLENDPS_128_1of3,
+ "vblendps $0, %%xmm6, %%xmm8, %%xmm7",
+ "vblendps $3, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VBLENDPS_128_2of3,
+ "vblendps $6, %%xmm6, %%xmm8, %%xmm7",
+ "vblendps $9, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VBLENDPS_128_3of3,
+ "vblendps $12, %%xmm6, %%xmm8, %%xmm7",
+ "vblendps $15, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VBLENDPD_128_1of2,
+ "vblendpd $0, %%xmm6, %%xmm8, %%xmm7",
+ "vblendpd $1, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VBLENDPD_128_2of2,
+ "vblendpd $2, %%xmm6, %%xmm8, %%xmm7",
+ "vblendpd $3, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VBLENDPD_256_1of3,
+ "vblendpd $0, %%ymm6, %%ymm8, %%ymm7",
+ "vblendpd $3, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VBLENDPD_256_2of3,
+ "vblendpd $6, %%ymm6, %%ymm8, %%ymm7",
+ "vblendpd $9, (%%rax), %%ymm8, %%ymm7")
+GEN_test_RandM(VBLENDPD_256_3of3,
+ "vblendpd $12, %%ymm6, %%ymm8, %%ymm7",
+ "vblendpd $15, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPBLENDW_128_0x00,
+ "vpblendw $0x00, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendw $0x01, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDW_128_0xFE,
+ "vpblendw $0xFE, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendw $0xFF, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDW_128_0x30,
+ "vpblendw $0x30, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendw $0x03, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDW_128_0x21,
+ "vpblendw $0x21, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendw $0x12, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDW_128_0xD7,
+ "vpblendw $0xD7, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendw $0x6C, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDW_128_0xB5,
+ "vpblendw $0xB5, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendw $0x4A, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDW_128_0x85,
+ "vpblendw $0x85, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendw $0xDC, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPBLENDW_128_0x29,
+ "vpblendw $0x29, %%xmm6, %%xmm8, %%xmm7",
+ "vpblendw $0x92, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMOVUPS_EtoG_256,
+ "vmovups %%ymm6, %%ymm9",
+ "vmovups (%%rax), %%ymm7")
+
+GEN_test_RandM(VSQRTSS_128,
+ "vsqrtss %%xmm6, %%xmm8, %%xmm7",
+ "vsqrtss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VSQRTPS_128,
+ "vsqrtps %%xmm6, %%xmm8",
+ "vsqrtps (%%rax), %%xmm8")
+
+GEN_test_RandM(VSQRTPS_256,
+ "vsqrtps %%ymm6, %%ymm8",
+ "vsqrtps (%%rax), %%ymm8")
+
+GEN_test_RandM(VSQRTPD_128,
+ "vsqrtpd %%xmm6, %%xmm8",
+ "vsqrtpd (%%rax), %%xmm8")
+
+GEN_test_RandM(VSQRTPD_256,
+ "vsqrtpd %%ymm6, %%ymm8",
+ "vsqrtpd (%%rax), %%ymm8")
+
+GEN_test_RandM(VRSQRTSS_128,
+ "vrsqrtss %%xmm6, %%xmm8, %%xmm7",
+ "vrsqrtss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VRSQRTPS_128,
+ "vrsqrtps %%xmm6, %%xmm8",
+ "vrsqrtps (%%rax), %%xmm8")
+
+GEN_test_RandM(VRSQRTPS_256,
+ "vrsqrtps %%ymm6, %%ymm8",
+ "vrsqrtps (%%rax), %%ymm8")
+
+GEN_test_RandM(VMOVDQU_GtoE_256,
+ "vmovdqu %%ymm9, %%ymm6",
+ "vmovdqu %%ymm7, (%%rax)")
+
+GEN_test_RandM(VCVTPS2PD_256,
+ "vcvtps2pd %%xmm9, %%ymm6",
+ "vcvtps2pd (%%rax), %%ymm7")
+
+GEN_test_RandM(VCVTTPS2DQ_128,
+ "vcvttps2dq %%xmm9, %%xmm6",
+ "vcvttps2dq (%%rax), %%xmm7")
+
+GEN_test_RandM(VCVTTPS2DQ_256,
+ "vcvttps2dq %%ymm9, %%ymm6",
+ "vcvttps2dq (%%rax), %%ymm7")
+
+GEN_test_RandM(VCVTDQ2PS_128,
+ "vcvtdq2ps %%xmm9, %%xmm6",
+ "vcvtdq2ps (%%rax), %%xmm7")
+
+GEN_test_RandM(VCVTDQ2PS_256,
+ "vcvtdq2ps %%ymm9, %%ymm6",
+ "vcvtdq2ps (%%rax), %%ymm7")
+
+GEN_test_RandM(VCVTTPD2DQ_128,
+ "vcvttpd2dqx %%xmm9, %%xmm6",
+ "vcvttpd2dqx (%%rax), %%xmm7")
+
+GEN_test_RandM(VCVTTPD2DQ_256,
+ "vcvttpd2dqy %%ymm9, %%xmm6",
+ "vcvttpd2dqy (%%rax), %%xmm7")
+
+GEN_test_RandM(VCVTPD2DQ_128,
+ "vcvtpd2dqx %%xmm9, %%xmm6",
+ "vcvtpd2dqx (%%rax), %%xmm7")
+
+GEN_test_RandM(VCVTPD2DQ_256,
+ "vcvtpd2dqy %%ymm9, %%xmm6",
+ "vcvtpd2dqy (%%rax), %%xmm7")
+
+GEN_test_RandM(VMOVSLDUP_128,
+ "vmovsldup %%xmm9, %%xmm6",
+ "vmovsldup (%%rax), %%xmm7")
+
+GEN_test_RandM(VMOVSLDUP_256,
+ "vmovsldup %%ymm9, %%ymm6",
+ "vmovsldup (%%rax), %%ymm7")
+
+GEN_test_RandM(VMOVSHDUP_128,
+ "vmovshdup %%xmm9, %%xmm6",
+ "vmovshdup (%%rax), %%xmm7")
+
+GEN_test_RandM(VMOVSHDUP_256,
+ "vmovshdup %%ymm9, %%ymm6",
+ "vmovshdup (%%rax), %%ymm7")
+
+GEN_test_RandM(VPERMILPS_VAR_128,
+ "vpermilps %%xmm6, %%xmm8, %%xmm7",
+ "vpermilps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPERMILPD_VAR_128,
+ "vpermilpd %%xmm6, %%xmm8, %%xmm7",
+ "vpermilpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPERMILPS_VAR_256,
+ "vpermilps %%ymm6, %%ymm8, %%ymm7",
+ "vpermilps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPERMILPD_VAR_256,
+ "vpermilpd %%ymm6, %%ymm8, %%ymm7",
+ "vpermilpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VPSLLW_128,
+ "andl $15, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsllw %%xmm6, %%xmm8, %%xmm9",
+ "andq $15, 128(%%rax);"
+ "vpsllw 128(%%rax), %%xmm8, %%xmm9")
+
+GEN_test_RandM(VPSRLW_128,
+ "andl $15, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsrlw %%xmm6, %%xmm8, %%xmm9",
+ "andq $15, 128(%%rax);"
+ "vpsrlw 128(%%rax), %%xmm8, %%xmm9")
+
+GEN_test_RandM(VPSRAW_128,
+ "andl $31, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsraw %%xmm6, %%xmm8, %%xmm9",
+ "andq $15, 128(%%rax);"
+ "vpsraw 128(%%rax), %%xmm8, %%xmm9")
+
+GEN_test_RandM(VPSLLD_128,
+ "andl $31, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpslld %%xmm6, %%xmm8, %%xmm9",
+ "andq $31, 128(%%rax);"
+ "vpslld 128(%%rax), %%xmm8, %%xmm9")
+
+GEN_test_RandM(VPSRLD_128,
+ "andl $31, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsrld %%xmm6, %%xmm8, %%xmm9",
+ "andq $31, 128(%%rax);"
+ "vpsrld 128(%%rax), %%xmm8, %%xmm9")
+
+GEN_test_RandM(VPSRAD_128,
+ "andl $31, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsrad %%xmm6, %%xmm8, %%xmm9",
+ "andq $31, 128(%%rax);"
+ "vpsrad 128(%%rax), %%xmm8, %%xmm9")
+
+GEN_test_RandM(VPSLLQ_128,
+ "andl $63, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsllq %%xmm6, %%xmm8, %%xmm9",
+ "andq $63, 128(%%rax);"
+ "vpsllq 128(%%rax), %%xmm8, %%xmm9")
+
+GEN_test_RandM(VPSRLQ_128,
+ "andl $63, %%r14d;"
+ "vmovd %%r14d, %%xmm6;"
+ "vpsrlq %%xmm6, %%xmm8, %%xmm9",
+ "andq $63, 128(%%rax);"
+ "vpsrlq 128(%%rax), %%xmm8, %%xmm9")
+
+GEN_test_RandM(VROUNDPS_128_0x0,
+ "vroundps $0x0, %%xmm8, %%xmm9",
+ "vroundps $0x0, (%%rax), %%xmm9")
+GEN_test_RandM(VROUNDPS_128_0x1,
+ "vroundps $0x1, %%xmm8, %%xmm9",
+ "vroundps $0x1, (%%rax), %%xmm9")
+GEN_test_RandM(VROUNDPS_128_0x2,
+ "vroundps $0x2, %%xmm8, %%xmm9",
+ "vroundps $0x2, (%%rax), %%xmm9")
+GEN_test_RandM(VROUNDPS_128_0x3,
+ "vroundps $0x3, %%xmm8, %%xmm9",
+ "vroundps $0x3, (%%rax), %%xmm9")
+GEN_test_RandM(VROUNDPS_128_0x4,
+ "vroundps $0x4, %%xmm8, %%xmm9",
+ "vroundps $0x4, (%%rax), %%xmm9")
+
+GEN_test_RandM(VROUNDPS_256_0x0,
+ "vroundps $0x0, %%ymm8, %%ymm9",
+ "vroundps $0x0, (%%rax), %%ymm9")
+GEN_test_RandM(VROUNDPS_256_0x1,
+ "vroundps $0x1, %%ymm8, %%ymm9",
+ "vroundps $0x1, (%%rax), %%ymm9")
+GEN_test_RandM(VROUNDPS_256_0x2,
+ "vroundps $0x2, %%ymm8, %%ymm9",
+ "vroundps $0x2, (%%rax), %%ymm9")
+GEN_test_RandM(VROUNDPS_256_0x3,
+ "vroundps $0x3, %%ymm8, %%ymm9",
+ "vroundps $0x3, (%%rax), %%ymm9")
+GEN_test_RandM(VROUNDPS_256_0x4,
+ "vroundps $0x4, %%ymm8, %%ymm9",
+ "vroundps $0x4, (%%rax), %%ymm9")
+
+GEN_test_RandM(VROUNDPD_128_0x0,
+ "vroundpd $0x0, %%xmm8, %%xmm9",
+ "vroundpd $0x0, (%%rax), %%xmm9")
+GEN_test_RandM(VROUNDPD_128_0x1,
+ "vroundpd $0x1, %%xmm8, %%xmm9",
+ "vroundpd $0x1, (%%rax), %%xmm9")
+GEN_test_RandM(VROUNDPD_128_0x2,
+ "vroundpd $0x2, %%xmm8, %%xmm9",
+ "vroundpd $0x2, (%%rax), %%xmm9")
+GEN_test_RandM(VROUNDPD_128_0x3,
+ "vroundpd $0x3, %%xmm8, %%xmm9",
+ "vroundpd $0x3, (%%rax), %%xmm9")
+GEN_test_RandM(VROUNDPD_128_0x4,
+ "vroundpd $0x4, %%xmm8, %%xmm9",
+ "vroundpd $0x4, (%%rax), %%xmm9")
+
+GEN_test_RandM(VROUNDPD_256_0x0,
+ "vroundpd $0x0, %%ymm8, %%ymm9",
+ "vroundpd $0x0, (%%rax), %%ymm9")
+GEN_test_RandM(VROUNDPD_256_0x1,
+ "vroundpd $0x1, %%ymm8, %%ymm9",
+ "vroundpd $0x1, (%%rax), %%ymm9")
+GEN_test_RandM(VROUNDPD_256_0x2,
+ "vroundpd $0x2, %%ymm8, %%ymm9",
+ "vroundpd $0x2, (%%rax), %%ymm9")
+GEN_test_RandM(VROUNDPD_256_0x3,
+ "vroundpd $0x3, %%ymm8, %%ymm9",
+ "vroundpd $0x3, (%%rax), %%ymm9")
+GEN_test_RandM(VROUNDPD_256_0x4,
+ "vroundpd $0x4, %%ymm8, %%ymm9",
+ "vroundpd $0x4, (%%rax), %%ymm9")
+
+GEN_test_RandM(VPMADDWD_128,
+ "vpmaddwd %%xmm6, %%xmm8, %%xmm7",
+ "vpmaddwd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VADDSUBPS_128,
+ "vaddsubps %%xmm6, %%xmm8, %%xmm7",
+ "vaddsubps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VADDSUBPS_256,
+ "vaddsubps %%ymm6, %%ymm8, %%ymm7",
+ "vaddsubps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VADDSUBPD_128,
+ "vaddsubpd %%xmm6, %%xmm8, %%xmm7",
+ "vaddsubpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VADDSUBPD_256,
+ "vaddsubpd %%ymm6, %%ymm8, %%ymm7",
+ "vaddsubpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VROUNDSS_0x0,
+ "vroundss $0x0, %%xmm8, %%xmm6, %%xmm9",
+ "vroundss $0x0, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSS_0x1,
+ "vroundss $0x1, %%xmm8, %%xmm6, %%xmm9",
+ "vroundss $0x1, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSS_0x2,
+ "vroundss $0x2, %%xmm8, %%xmm6, %%xmm9",
+ "vroundss $0x2, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSS_0x3,
+ "vroundss $0x3, %%xmm8, %%xmm6, %%xmm9",
+ "vroundss $0x3, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSS_0x4,
+ "vroundss $0x4, %%xmm8, %%xmm6, %%xmm9",
+ "vroundss $0x4, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSS_0x5,
+ "vroundss $0x5, %%xmm8, %%xmm6, %%xmm9",
+ "vroundss $0x5, (%%rax), %%xmm6, %%xmm9")
+
+GEN_test_RandM(VROUNDSD_0x0,
+ "vroundsd $0x0, %%xmm8, %%xmm6, %%xmm9",
+ "vroundsd $0x0, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSD_0x1,
+ "vroundsd $0x1, %%xmm8, %%xmm6, %%xmm9",
+ "vroundsd $0x1, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSD_0x2,
+ "vroundsd $0x2, %%xmm8, %%xmm6, %%xmm9",
+ "vroundsd $0x2, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSD_0x3,
+ "vroundsd $0x3, %%xmm8, %%xmm6, %%xmm9",
+ "vroundsd $0x3, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSD_0x4,
+ "vroundsd $0x4, %%xmm8, %%xmm6, %%xmm9",
+ "vroundsd $0x4, (%%rax), %%xmm6, %%xmm9")
+GEN_test_RandM(VROUNDSD_0x5,
+ "vroundsd $0x5, %%xmm8, %%xmm6, %%xmm9",
+ "vroundsd $0x5, (%%rax), %%xmm6, %%xmm9")
+
+GEN_test_RandM(VPTEST_128_1,
+ "vptest %%xmm6, %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vptest (%%rax), %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+/* Here we ignore the boilerplate-supplied data and try to do
+ x AND x and x AND NOT x. Not a great test but better
+ than nothing. */
+GEN_test_RandM(VPTEST_128_2,
+ "vmovups %%xmm6, %%xmm8;"
+ "vptest %%xmm6, %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vmovups (%%rax), %%xmm8;"
+ "vcmpeqpd %%xmm8,%%xmm8,%%xmm7;"
+ "vxorpd %%xmm8,%%xmm7,%%xmm8;"
+ "vptest (%%rax), %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VPTEST_256_1,
+ "vptest %%ymm6, %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vptest (%%rax), %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+/* Here we ignore the boilerplate-supplied data and try to do
+ x AND x and x AND NOT x. Not a great test but better
+ than nothing. */
+GEN_test_RandM(VPTEST_256_2,
+ "vmovups %%ymm6, %%ymm8;"
+ "vptest %%ymm6, %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vmovups (%%rax), %%ymm8;"
+ "vcmpeqpd %%xmm8,%%xmm8,%%xmm7;"
+ "subq $1024, %%rsp;"
+ "vmovups %%xmm7,512(%%rsp);"
+ "vmovups %%xmm7,528(%%rsp);"
+ "vmovups 512(%%rsp), %%ymm7;"
+ "addq $1024, %%rsp;"
+ "vxorpd %%ymm8,%%ymm7,%%ymm8;"
+ "vptest (%%rax), %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+
+/* VTESTPS/VTESTPD: test once with all-0 operands, once with
+ one all-0s and one all 1s, and once with random data. */
+
+GEN_test_RandM(VTESTPS_128_1,
+ "vtestps %%xmm6, %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vtestps (%%rax), %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+/* Here we ignore the boilerplate-supplied data and try to do
+ x AND x and x AND NOT x. Not a great test but better
+ than nothing. */
+GEN_test_RandM(VTESTPS_128_2,
+ "vmovups %%xmm6, %%xmm8;"
+ "vtestps %%xmm6, %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vmovups (%%rax), %%xmm8;"
+ "vcmpeqpd %%xmm8,%%xmm8,%%xmm7;"
+ "vxorpd %%xmm8,%%xmm7,%%xmm8;"
+ "vtestps (%%rax), %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VTESTPS_128_3,
+ "vtestps %%xmm8, %%xmm9; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vtestps (%%rax), %%xmm9; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+
+
+
+GEN_test_RandM(VTESTPS_256_1,
+ "vtestps %%ymm6, %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vtestps (%%rax), %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+/* Here we ignore the boilerplate-supplied data and try to do
+ x AND x and x AND NOT x. Not a great test but better
+ than nothing. */
+GEN_test_RandM(VTESTPS_256_2,
+ "vmovups %%ymm6, %%ymm8;"
+ "vtestps %%ymm6, %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vmovups (%%rax), %%ymm8;"
+ "vcmpeqpd %%xmm8,%%xmm8,%%xmm7;"
+ "subq $1024, %%rsp;"
+ "vmovups %%xmm7,512(%%rsp);"
+ "vmovups %%xmm7,528(%%rsp);"
+ "vmovups 512(%%rsp), %%ymm7;"
+ "addq $1024, %%rsp;"
+ "vxorpd %%ymm8,%%ymm7,%%ymm8;"
+ "vtestps (%%rax), %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VTESTPS_256_3,
+ "vtestps %%ymm8, %%ymm9; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vtestps (%%rax), %%ymm9; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+
+
+GEN_test_RandM(VTESTPD_128_1,
+ "vtestpd %%xmm6, %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vtestpd (%%rax), %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+/* Here we ignore the boilerplate-supplied data and try to do
+ x AND x and x AND NOT x. Not a great test but better
+ than nothing. */
+GEN_test_RandM(VTESTPD_128_2,
+ "vmovups %%xmm6, %%xmm8;"
+ "vtestpd %%xmm6, %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vmovups (%%rax), %%xmm8;"
+ "vcmpeqpd %%xmm8,%%xmm8,%%xmm7;"
+ "vxorpd %%xmm8,%%xmm7,%%xmm8;"
+ "vtestpd (%%rax), %%xmm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VTESTPD_128_3,
+ "vtestpd %%xmm8, %%xmm9; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vtestpd (%%rax), %%xmm9; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+
+
+
+GEN_test_RandM(VTESTPD_256_1,
+ "vtestpd %%ymm6, %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vtestpd (%%rax), %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+/* Here we ignore the boilerplate-supplied data and try to do
+ x AND x and x AND NOT x. Not a great test but better
+ than nothing. */
+GEN_test_RandM(VTESTPD_256_2,
+ "vmovups %%ymm6, %%ymm8;"
+ "vtestpd %%ymm6, %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vmovups (%%rax), %%ymm8;"
+ "vcmpeqpd %%xmm8,%%xmm8,%%xmm7;"
+ "subq $1024, %%rsp;"
+ "vmovups %%xmm7,512(%%rsp);"
+ "vmovups %%xmm7,528(%%rsp);"
+ "vmovups 512(%%rsp), %%ymm7;"
+ "addq $1024, %%rsp;"
+ "vxorpd %%ymm8,%%ymm7,%%ymm8;"
+ "vtestpd (%%rax), %%ymm8; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VTESTPD_256_3,
+ "vtestpd %%ymm8, %%ymm9; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14",
+ "vtestpd (%%rax), %%ymm9; "
+ "pushfq; popq %%r14; andq $0x8D5, %%r14")
+
+GEN_test_RandM(VBLENDVPS_128,
+ "vblendvps %%xmm9, %%xmm6, %%xmm8, %%xmm7",
+ "vblendvps %%xmm9, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VBLENDVPS_256,
+ "vblendvps %%ymm9, %%ymm6, %%ymm8, %%ymm7",
+ "vblendvps %%ymm9, (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VBLENDVPD_128,
+ "vblendvpd %%xmm9, %%xmm6, %%xmm8, %%xmm7",
+ "vblendvpd %%xmm9, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VBLENDVPD_256,
+ "vblendvpd %%ymm9, %%ymm6, %%ymm8, %%ymm7",
+ "vblendvpd %%ymm9, (%%rax), %%ymm8, %%ymm7")
+
+
+GEN_test_RandM(VHADDPS_128,
+ "vhaddps %%xmm6, %%xmm8, %%xmm7",
+ "vhaddps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VHADDPS_256,
+ "vhaddps %%ymm6, %%ymm8, %%ymm7",
+ "vhaddps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VHADDPD_128,
+ "vhaddpd %%xmm6, %%xmm8, %%xmm7",
+ "vhaddpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VHADDPD_256,
+ "vhaddpd %%ymm6, %%ymm8, %%ymm7",
+ "vhaddpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VHSUBPS_128,
+ "vhsubps %%xmm6, %%xmm8, %%xmm7",
+ "vhsubps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VHSUBPS_256,
+ "vhsubps %%ymm6, %%ymm8, %%ymm7",
+ "vhsubps (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VHSUBPD_128,
+ "vhsubpd %%xmm6, %%xmm8, %%xmm7",
+ "vhsubpd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VHSUBPD_256,
+ "vhsubpd %%ymm6, %%ymm8, %%ymm7",
+ "vhsubpd (%%rax), %%ymm8, %%ymm7")
+
+GEN_test_RandM(VEXTRACTPS_0x0,
+ "vextractps $0, %%xmm8, %%r14d",
+ "vextractps $0, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VEXTRACTPS_0x1,
+ "vextractps $1, %%xmm8, %%r14d",
+ "vextractps $1, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VEXTRACTPS_0x2,
+ "vextractps $2, %%xmm8, %%r14d",
+ "vextractps $2, %%xmm8, (%%rax)")
+
+GEN_test_RandM(VEXTRACTPS_0x3,
+ "vextractps $3, %%xmm8, %%r14d",
+ "vextractps $3, %%xmm8, (%%rax)")
+
+GEN_test_Monly(VLDDQU_128,
+ "vlddqu 1(%%rax), %%xmm8")
+
+GEN_test_Monly(VLDDQU_256,
+ "vlddqu 1(%%rax), %%ymm8")
+
+GEN_test_Monly(VMOVNTDQA_128,
+ "vmovntdqa (%%rax), %%xmm9")
+
+GEN_test_Monly(VMASKMOVDQU_128,
+ "xchgq %%rax, %%rdi;"
+ "vmaskmovdqu %%xmm8, %%xmm9;"
+ "xchgq %%rax, %%rdi")
+
+GEN_test_Ronly(VMOVMSKPD_128,
+ "vmovmskpd %%xmm9, %%r14d")
+
+GEN_test_Ronly(VMOVMSKPD_256,
+ "vmovmskpd %%ymm9, %%r14d")
+
+GEN_test_Ronly(VMOVMSKPS_128,
+ "vmovmskps %%xmm9, %%r14d")
+
+GEN_test_Ronly(VMOVMSKPS_256,
+ "vmovmskps %%ymm9, %%r14d")
+
+GEN_test_Monly(VMOVNTPD_128,
+ "vmovntpd %%xmm9, (%%rax)")
+
+GEN_test_Monly(VMOVNTPD_256,
+ "vmovntpd %%ymm9, (%%rax)")
+
+GEN_test_Monly(VMOVNTPS_128,
+ "vmovntps %%xmm9, (%%rax)")
+
+GEN_test_Monly(VMOVNTPS_256,
+ "vmovntps %%ymm9, (%%rax)")
+
+GEN_test_RandM(VPACKSSWB_128,
+ "vpacksswb %%xmm6, %%xmm8, %%xmm7",
+ "vpacksswb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPAVGB_128,
+ "vpavgb %%xmm6, %%xmm8, %%xmm7",
+ "vpavgb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPAVGW_128,
+ "vpavgw %%xmm6, %%xmm8, %%xmm7",
+ "vpavgw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPADDSB_128,
+ "vpaddsb %%xmm6, %%xmm8, %%xmm7",
+ "vpaddsb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPADDSW_128,
+ "vpaddsw %%xmm6, %%xmm8, %%xmm7",
+ "vpaddsw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPHADDW_128,
+ "vphaddw %%xmm6, %%xmm8, %%xmm7",
+ "vphaddw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPHADDD_128,
+ "vphaddd %%xmm6, %%xmm8, %%xmm7",
+ "vphaddd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPHADDSW_128,
+ "vphaddsw %%xmm6, %%xmm8, %%xmm7",
+ "vphaddsw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMADDUBSW_128,
+ "vpmaddubsw %%xmm6, %%xmm8, %%xmm7",
+ "vpmaddubsw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPHSUBW_128,
+ "vphsubw %%xmm6, %%xmm8, %%xmm7",
+ "vphsubw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPHSUBD_128,
+ "vphsubd %%xmm6, %%xmm8, %%xmm7",
+ "vphsubd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPHSUBSW_128,
+ "vphsubsw %%xmm6, %%xmm8, %%xmm7",
+ "vphsubsw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPABSB_128,
+ "vpabsb %%xmm6, %%xmm7",
+ "vpabsb (%%rax), %%xmm7")
+
+GEN_test_RandM(VPABSW_128,
+ "vpabsw %%xmm6, %%xmm7",
+ "vpabsw (%%rax), %%xmm7")
+
+GEN_test_RandM(VPMOVSXBQ_128,
+ "vpmovsxbq %%xmm6, %%xmm8",
+ "vpmovsxbq (%%rax), %%xmm8")
+
+GEN_test_RandM(VPMOVSXWQ_128,
+ "vpmovsxwq %%xmm6, %%xmm8",
+ "vpmovsxwq (%%rax), %%xmm8")
+
+GEN_test_RandM(VPACKUSDW_128,
+ "vpackusdw %%xmm6, %%xmm8, %%xmm7",
+ "vpackusdw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMOVZXBQ_128,
+ "vpmovzxbq %%xmm6, %%xmm8",
+ "vpmovzxbq (%%rax), %%xmm8")
+
+GEN_test_RandM(VPMOVZXWQ_128,
+ "vpmovzxwq %%xmm6, %%xmm8",
+ "vpmovzxwq (%%rax), %%xmm8")
+
+GEN_test_RandM(VPMOVZXDQ_128,
+ "vpmovzxdq %%xmm6, %%xmm8",
+ "vpmovzxdq (%%rax), %%xmm8")
+
+GEN_test_RandM(VMPSADBW_128_0x0,
+ "vmpsadbw $0, %%xmm6, %%xmm8, %%xmm7",
+ "vmpsadbw $0, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VMPSADBW_128_0x1,
+ "vmpsadbw $1, %%xmm6, %%xmm8, %%xmm7",
+ "vmpsadbw $1, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VMPSADBW_128_0x2,
+ "vmpsadbw $2, %%xmm6, %%xmm8, %%xmm7",
+ "vmpsadbw $2, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VMPSADBW_128_0x3,
+ "vmpsadbw $3, %%xmm6, %%xmm8, %%xmm7",
+ "vmpsadbw $3, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VMPSADBW_128_0x4,
+ "vmpsadbw $4, %%xmm6, %%xmm8, %%xmm7",
+ "vmpsadbw $4, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VMPSADBW_128_0x5,
+ "vmpsadbw $5, %%xmm6, %%xmm8, %%xmm7",
+ "vmpsadbw $5, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VMPSADBW_128_0x6,
+ "vmpsadbw $6, %%xmm6, %%xmm8, %%xmm7",
+ "vmpsadbw $6, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VMPSADBW_128_0x7,
+ "vmpsadbw $7, %%xmm6, %%xmm8, %%xmm7",
+ "vmpsadbw $7, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VMOVDDUP_YMMorMEM256_to_YMM,
+ "vmovddup %%ymm8, %%ymm7",
+ "vmovddup (%%rax), %%ymm9")
+
+GEN_test_Monly(VMOVLPS_128_M64_XMM_XMM, "vmovlps (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Monly(VMOVLPS_128_XMM_M64, "vmovlps %%xmm7, (%%rax)")
+
+GEN_test_RandM(VRCPSS_128,
+ "vrcpss %%xmm6, %%xmm8, %%xmm7",
+ "vrcpss (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VRCPPS_128,
+ "vrcpps %%xmm6, %%xmm8",
+ "vrcpps (%%rax), %%xmm8")
+
+GEN_test_RandM(VRCPPS_256,
+ "vrcpps %%ymm6, %%ymm8",
+ "vrcpps (%%rax), %%ymm8")
+
+GEN_test_RandM(VPSADBW_128,
+ "vpsadbw %%xmm6, %%xmm8, %%xmm7",
+ "vpsadbw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSIGNB_128,
+ "vpsignb %%xmm6, %%xmm8, %%xmm7",
+ "vpsignb (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSIGNW_128,
+ "vpsignw %%xmm6, %%xmm8, %%xmm7",
+ "vpsignw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPSIGND_128,
+ "vpsignd %%xmm6, %%xmm8, %%xmm7",
+ "vpsignd (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VPMULHRSW_128,
+ "vpmulhrsw %%xmm6, %%xmm8, %%xmm7",
+ "vpmulhrsw (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_Monly(VBROADCASTF128,
+ "vbroadcastf128 (%%rax), %%ymm9")
+
+GEN_test_RandM(VPEXTRW_128_0x0,
+ "vpextrw $0x0, %%xmm7, %%r14d",
+ "vpextrw $0x0, %%xmm7, (%%rax)")
+GEN_test_RandM(VPEXTRW_128_0x1,
+ "vpextrw $0x1, %%xmm7, %%r14d",
+ "vpextrw $0x1, %%xmm7, (%%rax)")
+GEN_test_RandM(VPEXTRW_128_0x2,
+ "vpextrw $0x2, %%xmm7, %%r14d",
+ "vpextrw $0x2, %%xmm7, (%%rax)")
+GEN_test_RandM(VPEXTRW_128_0x3,
+ "vpextrw $0x3, %%xmm7, %%r14d",
+ "vpextrw $0x3, %%xmm7, (%%rax)")
+GEN_test_RandM(VPEXTRW_128_0x4,
+ "vpextrw $0x4, %%xmm7, %%r14d",
+ "vpextrw $0x4, %%xmm7, (%%rax)")
+GEN_test_RandM(VPEXTRW_128_0x5,
+ "vpextrw $0x5, %%xmm7, %%r14d",
+ "vpextrw $0x5, %%xmm7, (%%rax)")
+GEN_test_RandM(VPEXTRW_128_0x6,
+ "vpextrw $0x6, %%xmm7, %%r14d",
+ "vpextrw $0x6, %%xmm7, (%%rax)")
+GEN_test_RandM(VPEXTRW_128_0x7,
+ "vpextrw $0x7, %%xmm7, %%r14d",
+ "vpextrw $0x7, %%xmm7, (%%rax)")
+
+GEN_test_RandM(VAESENC,
+ "vaesenc %%xmm6, %%xmm8, %%xmm7",
+ "vaesenc (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VAESENCLAST,
+ "vaesenclast %%xmm6, %%xmm8, %%xmm7",
+ "vaesenclast (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VAESDEC,
+ "vaesdec %%xmm6, %%xmm8, %%xmm7",
+ "vaesdec (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VAESDECLAST,
+ "vaesdeclast %%xmm6, %%xmm8, %%xmm7",
+ "vaesdeclast (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VAESIMC,
+ "vaesimc %%xmm6, %%xmm7",
+ "vaesimc (%%rax), %%xmm7")
+
+GEN_test_RandM(VAESKEYGENASSIST_0x00,
+ "vaeskeygenassist $0x00, %%xmm6, %%xmm7",
+ "vaeskeygenassist $0x00, (%%rax), %%xmm7")
+GEN_test_RandM(VAESKEYGENASSIST_0x31,
+ "vaeskeygenassist $0x31, %%xmm6, %%xmm7",
+ "vaeskeygenassist $0x31, (%%rax), %%xmm7")
+GEN_test_RandM(VAESKEYGENASSIST_0xB2,
+ "vaeskeygenassist $0xb2, %%xmm6, %%xmm7",
+ "vaeskeygenassist $0xb2, (%%rax), %%xmm7")
+GEN_test_RandM(VAESKEYGENASSIST_0xFF,
+ "vaeskeygenassist $0xFF, %%xmm6, %%xmm7",
+ "vaeskeygenassist $0xFF, (%%rax), %%xmm7")
+
+GEN_test_RandM(VPCLMULQDQ_0x00,
+ "vpclmulqdq $0x00, %%xmm6, %%xmm8, %%xmm7",
+ "vpclmulqdq $0x00, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPCLMULQDQ_0x01,
+ "vpclmulqdq $0x01, %%xmm6, %%xmm8, %%xmm7",
+ "vpclmulqdq $0x01, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPCLMULQDQ_0x10,
+ "vpclmulqdq $0x10, %%xmm6, %%xmm8, %%xmm7",
+ "vpclmulqdq $0x10, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPCLMULQDQ_0x11,
+ "vpclmulqdq $0x11, %%xmm6, %%xmm8, %%xmm7",
+ "vpclmulqdq $0x11, (%%rax), %%xmm8, %%xmm7")
+GEN_test_RandM(VPCLMULQDQ_0xFF,
+ "vpclmulqdq $0xFF, %%xmm6, %%xmm8, %%xmm7",
+ "vpclmulqdq $0xFF, (%%rax), %%xmm8, %%xmm7")
+
+GEN_test_RandM(VCMPSS_128_0x9,
+ "vcmpss $0x9, %%xmm6, %%xmm8, %%xmm7",
+ "vcmpss $0x9, (%%rax), %%xmm8, %%xmm7")
+
+/* Comment duplicated above, for convenient reference:
+ Allowed operands in test insns:
+ Reg form: %ymm6, %ymm7, %ymm8, %ymm9 and %r14.
+ Mem form: (%rax), %ymm7, %ymm8, %ymm9 and %r14.
+ Imm8 etc fields are also allowed, where they make sense.
+*/
+
+#define N_DEFAULT_ITERS 3
+
+// Do the specified test some number of times
+#define DO_N(_iters, _testfn) \
+ do { int i; for (i = 0; i < (_iters); i++) { test_##_testfn(); } } while (0)
+
+// Do the specified test the default number of times
+#define DO_D(_testfn) DO_N(N_DEFAULT_ITERS, _testfn)
+
+
+int main ( void )
+{
+ DO_D( VMOVUPD_EtoG_256 );
+ DO_D( VMOVUPD_GtoE_256 );
+ DO_D( VPSUBW_128 );
+ DO_D( VPSUBQ_128 );
+ DO_D( VPADDQ_128 );
+ DO_D( VPINSRQ_128 );
+ DO_D( VUCOMISS_128 );
+ DO_D( VUCOMISD_128 );
+ DO_D( VCVTPS2PD_128 );
+ DO_D( VANDNPD_128 );
+ DO_D( VORPD_128 );
+ DO_D( VXORPD_128 );
+ DO_D( VXORPS_128 );
+ DO_D( VMULSD_128 );
+ DO_D( VADDSD_128 );
+ DO_D( VMINSD_128 );
+ DO_D( VSUBSD_128 );
+ DO_D( VDIVSD_128 );
+ DO_D( VMAXSD_128 );
+ DO_D( VPSHUFD_0x39_128 );
+ DO_D( VPCMPEQD_128 );
+ DO_D( VPEXTRD_128_0x3 );
+ DO_D( VPEXTRD_128_0x0 );
+ DO_D( VINSERTF128_0x0 );
+ DO_D( VINSERTF128_0x1 );
+ DO_D( VEXTRACTF128_0x0 );
+ DO_D( VEXTRACTF128_0x1 );
+ DO_D( VCVTPD2PS_128 );
+ /* Test all CMPSS variants; this code is tricky. */
+ DO_D( VCMPSS_128_0x0 );
+ DO_D( VCMPSS_128_0x1 );
+ DO_D( VCMPSS_128_0x2 );
+ DO_D( VCMPSS_128_0x3 );
+ DO_D( VCMPSS_128_0x4 );
+ DO_D( VCMPSS_128_0x5 );
+ DO_D( VCMPSS_128_0x6 );
+ DO_D( VCMPSS_128_0x7 );
+ DO_D( VCMPSS_128_0xA );
+ DO_D( VCMPSS_128_0xC );
+ DO_D( VCMPSS_128_0xC );
+ DO_D( VCMPSS_128_0xD );
+ DO_D( VCMPSS_128_0xE );
+ DO_D( VCMPSS_128_0x11 );
+ DO_D( VCMPSS_128_0x12);
+ DO_D( VCMPSS_128_0x16 );
+ DO_D( VCMPSS_128_0x1E );
+ DO_D( VMOVDDUP_XMMorMEM64_to_XMM );
+ DO_D( VMOVD_IREGorMEM32_to_XMM );
+ DO_D( VMOVQ_XMM_MEM64 );
+ DO_D( VMOVDQA_GtoE_256 );
+ DO_D( VMOVDQA_GtoE_128 );
+ DO_D( VMOVDQU_GtoE_128 );
+ DO_D( VMOVDQA_EtoG_256 );
+ DO_D( VMOVDQA_EtoG_128 );
+ DO_D( VMOVDQU_EtoG_128 );
+ DO_D( VMOVAPD_GtoE_128 );
+ DO_D( VMOVAPD_GtoE_256 );
+ DO_D( VMOVAPS_GtoE_128 );
+ DO_D( VMOVAPS_GtoE_256 );
+ DO_D( VMOVAPS_EtoG_128 );
+ DO_D( VMOVAPD_EtoG_256 );
+ DO_D( VMOVAPD_EtoG_128 );
+ DO_D( VMOVUPD_GtoE_128 );
+ DO_D( VMOVSS_XMM_M32 );
+ DO_D( VMOVSD_XMM_M64 );
+ DO_D( VMOVSS_M64_XMM );
+ DO_D( VMOVSD_M64_XMM );
+ DO_D( VINSERTPS_0x39_128 );
+ DO_D( VPUNPCKLDQ_128 );
+ DO_D( VPACKSSDW_128 );
+ DO_D( VPADDW_128 );
+ DO_D( VPSRLW_0x05_128 );
+ DO_D( VPSLLW_0x05_128 );
+ DO_D( VPUNPCKLQDQ_128 );
+ DO_D( VPINSRD_128 );
+ DO_D( VMOVD_XMM_to_MEM32 );
+ DO_D( VPANDN_128 );
+ DO_D( VPSLLDQ_0x05_128 );
+ DO_D( VPSRLDQ_0x05_128 );
+ DO_D( VPSUBUSB_128 );
+ DO_D( VPSUBSB_128 );
+ DO_D( VPSLLD_0x05_128 );
+ DO_D( VPSRLD_0x05_128 );
+ DO_D( VPSRAD_0x05_128 );
+ DO_D( VPUNPCKLWD_128 );
+ DO_D( VPUNPCKHWD_128 );
+ DO_D( VPADDUSB_128 );
+ DO_D( VPMULHUW_128 );
+ DO_D( VPADDUSW_128 );
+ DO_D( VPMULLW_128 );
+ DO_D( VPSHUFHW_0x39_128 );
+ DO_D( VPSHUFLW_0x39_128 );
+ DO_D( VCVTPS2DQ_128 );
+ DO_D( VSUBPS_128 );
+ DO_D( VADDPS_128 );
+ DO_D( VMULPS_128 );
+ DO_D( VMAXPS_128 );
+ DO_D( VMINPS_128 );
+ DO_D( VSHUFPS_0x39_128 );
+ DO_D( VPCMPEQB_128 );
+ DO_D( VMOVHPD_128_StoreForm );
+ DO_D( VPAND_128 );
+ DO_D( VPMOVMSKB_128 );
+ DO_D( VCVTTSS2SI_64 );
+ DO_D( VPACKUSWB_128 );
+ DO_D( VCVTSS2SD_128 );
+ DO_D( VCVTSD2SS_128 );
+ DO_D( VMOVD_XMM_to_IREG32 );
+ DO_D( VPCMPESTRM_0x45_128 );
+ DO_D( VMOVQ_IREGorMEM64_to_XMM );
+ DO_D( VMOVUPS_XMM_to_XMMorMEM );
+ DO_D( VMOVNTDQ_128 );
+ DO_D( VMOVLHPS_128 );
+ DO_D( VPABSD_128 );
+ DO_D( VMOVHLPS_128 );
+ DO_D( VMOVQ_XMM_to_IREG64 );
+ DO_D( VMOVQ_XMMorMEM64_to_XMM );
+ DO_D( VCVTTSS2SI_32 );
+ DO_D( VPUNPCKLBW_128 );
+ DO_D( VPUNPCKHBW_128 );
+ DO_D( VMULSS_128 );
+ DO_D( VSUBSS_128 );
+ DO_D( VADDSS_128 );
+ DO_D( VDIVSS_128 );
+ DO_D( VUNPCKLPS_128 );
+ DO_D( VCVTSI2SS_128 );
+ DO_D( VANDPS_128 );
+ DO_D( VMINSS_128 );
+ DO_D( VMAXSS_128 );
+ DO_D( VANDNPS_128 );
+ DO_D( VORPS_128 );
+ DO_D( VSQRTSD_128 );
+ /* Test all CMPSS variants; this code is tricky. */
+ DO_D( VCMPSD_128_0x0 );
+ DO_D( VCMPSD_128_0x1 );
+ DO_D( VCMPSD_128_0x2 );
+ DO_D( VCMPSD_128_0x3 );
+ DO_D( VCMPSD_128_0x4 );
+ DO_D( VCMPSD_128_0x5 );
+ DO_D( VCMPSD_128_0x6 );
+ DO_D( VCMPSD_128_0x7 );
+ DO_D( VCMPSD_128_0xA );
+ DO_D( VCMPSD_128_0xC );
+ DO_D( VCMPSD_128_0xD );
+ DO_D( VCMPSD_128_0xE );
+ DO_D( VCMPSD_128_0x11 );
+ DO_D( VCMPSD_128_0x12 );
+ DO_D( VCMPSD_128_0x16 );
+ DO_D( VCMPSD_128_0x1E );
+ DO_D( VPSHUFB_128 );
+ DO_D( VCVTTSD2SI_32 );
+ DO_D( VCVTTSD2SI_64 );
+ DO_D( VCVTSI2SS_64 );
+ DO_D( VCVTSI2SD_64 );
+ DO_D( VCVTSI2SD_32 );
+ DO_D( VPOR_128 );
+ DO_D( VPXOR_128 );
+ DO_D( VPSUBB_128 );
+ DO_D( VPSUBD_128 );
+ DO_D( VPADDD_128 );
+ DO_D( VPMOVZXBW_128 );
+ DO_D( VPMOVZXWD_128 );
+ DO_D( VPBLENDVB_128 );
+ DO_D( VPMINSD_128 );
+ DO_D( VPMAXSD_128 );
+ DO_D( VANDPD_128 );
+ DO_D( VMULPD_256 );
+ DO_D( VMOVUPD_EtoG_128 );
+ DO_D( VADDPD_256 );
+ DO_D( VSUBPD_256 );
+ DO_D( VDIVPD_256 );
+ DO_D( VPCMPEQQ_128 );
+ DO_D( VSUBPD_128 );
+ DO_D( VADDPD_128 );
+ DO_D( VUNPCKLPD_128 );
+ DO_D( VUNPCKHPD_128 );
+ DO_D( VUNPCKHPS_128 );
+ DO_D( VMOVUPS_EtoG_128 );
+ DO_D( VADDPS_256 );
+ DO_D( VSUBPS_256 );
+ DO_D( VMULPS_256 );
+ DO_D( VDIVPS_256 );
+ DO_D( VPCMPGTQ_128 );
+ DO_D( VPEXTRQ_128_0x0 );
+ DO_D( VPEXTRQ_128_0x1 );
+ DO_D( VPSRLQ_0x05_128 );
+ DO_D( VPMULUDQ_128 );
+ DO_D( VPSLLQ_0x05_128 );
+ DO_D( VPMAXUD_128 );
+ DO_D( VPMINUD_128 );
+ DO_D( VPMULLD_128 );
+ DO_D( VPMAXUW_128 );
+ DO_D( VPEXTRW_128_EregOnly_toG_0x0 );
+ DO_D( VPEXTRW_128_EregOnly_toG_0x7 );
+ DO_D( VPMINUW_128 );
+ DO_D( VPHMINPOSUW_128 );
+ DO_D( VPMAXSW_128 );
+ DO_D( VPMINSW_128 );
+ DO_D( VPMAXUB_128 );
+ DO_D( VPEXTRB_GtoE_128_0x0 );
+ DO_D( VPEXTRB_GtoE_128_0x1 );
+ DO_D( VPEXTRB_GtoE_128_0x2 );
+ DO_D( VPEXTRB_GtoE_128_0x3 );
+ DO_D( VPEXTRB_GtoE_128_0x4 );
+ DO_D( VPEXTRB_GtoE_128_0x9 );
+ DO_D( VPEXTRB_GtoE_128_0xE );
+ DO_D( VPEXTRB_GtoE_128_0xF );
+ DO_D( VPMINUB_128 );
+ DO_D( VPMAXSB_128 );
+ DO_D( VPMINSB_128 );
+ DO_D( VPERM2F128_0x00 );
+ DO_D( VPERM2F128_0xFF );
+ DO_D( VPERM2F128_0x30 );
+ DO_D( VPERM2F128_0x21 );
+ DO_D( VPERM2F128_0x12 );
+ DO_D( VPERM2F128_0x03 );
+ DO_D( VPERM2F128_0x85 );
+ DO_D( VPERM2F128_0x5A );
+ DO_D( VPERMILPD_256_0x0 );
+ DO_D( VPERMILPD_256_0xF );
+ DO_D( VPERMILPD_256_0xA );
+ DO_D( VPERMILPD_256_0x5 );
+ DO_D( VPERMILPD_128_0x0 );
+ DO_D( VPERMILPD_128_0x3 );
+ DO_D( VUNPCKLPD_256 );
+ DO_D( VUNPCKHPD_256 );
+ DO_D( VSHUFPS_0x39_256 );
+ DO_D( VUNPCKLPS_256 );
+ DO_D( VUNPCKHPS_256 );
+ DO_D( VXORPD_256 );
+ DO_D( VBROADCASTSD_256 );
+ DO_D( VCMPPD_128_0x4 );
+ DO_D( VCVTDQ2PD_128 );
+ DO_D( VDIVPD_128 );
+ DO_D( VANDPD_256 );
+ DO_D( VPMOVSXBW_128 );
+ DO_D( VPSUBUSW_128 );
+ DO_D( VPSUBSW_128 );
+ DO_D( VPCMPEQW_128 );
+ DO_D( VPADDB_128 );
+ DO_D( VMOVAPS_EtoG_256 );
+ DO_D( VCVTDQ2PD_256 );
+ DO_D( VMOVHPD_128_LoadForm );
+ DO_D( VCVTPD2PS_256 );
+ DO_D( VPUNPCKHDQ_128 );
+ DO_D( VBROADCASTSS_128 );
+ DO_D( VPMOVSXDQ_128 );
+ DO_D( VPMOVSXWD_128 );
+ DO_D( VDIVPS_128 );
+ DO_D( VANDPS_256 );
+ DO_D( VXORPS_256 );
+ DO_D( VORPS_256 );
+ DO_D( VANDNPD_256 );
+ DO_D( VANDNPS_256 );
+ DO_D( VORPD_256 );
+ DO_D( VPERMILPS_256_0x0F );
+ DO_D( VPERMILPS_256_0xFA );
+ DO_D( VPERMILPS_256_0xA3 );
+ DO_D( VPERMILPS_256_0x5A );
+ DO_D( VPMULHW_128 );
+ DO_D( VPUNPCKHQDQ_128 );
+ DO_D( VPSRAW_0x05_128 );
+ DO_D( VPCMPGTD_128 );
+ DO_D( VPMOVZXBD_128 );
+ DO_D( VPMOVSXBD_128 );
+ DO_D( VPINSRB_128_1of3 );
+ DO_D( VPINSRB_128_2of3 );
+ DO_D( VPINSRB_128_3of3 );
+ DO_D( VCOMISD_128 );
+ DO_D( VCOMISS_128 );
+ DO_D( VMOVUPS_YMM_to_YMMorMEM );
+ DO_D( VDPPD_128_1of4 );
+ DO_D( VDPPD_128_2of4 );
+ DO_D( VDPPD_128_3of4 );
+ DO_D( VDPPD_128_4of4 );
+ DO_D( VPINSRW_128_1of4 );
+ DO_D( VPINSRW_128_2of4 );
+ DO_D( VPINSRW_128_3of4 );
+ DO_D( VPINSRW_128_4of4 );
+ DO_D( VBROADCASTSS_256 );
+ DO_D( VPALIGNR_128_1of3 );
+ DO_D( VPALIGNR_128_2of3 );
+ DO_D( VPALIGNR_128_3of3 );
+ DO_D( VMOVSD_REG_XMM );
+ DO_D( VMOVSS_REG_XMM );
+ DO_D( VMOVLPD_128_M64_XMM_XMM );
+ DO_D( VMOVLPD_128_XMM_M64 );
+ DO_D( VSHUFPD_128_1of2 );
+ DO_D( VSHUFPD_128_2of2 );
+ DO_D( VSHUFPD_256_1of2 );
+ DO_D( VSHUFPD_256_2of2 );
+ DO_D( VPERMILPS_128_0x00 );
+ DO_D( VPERMILPS_128_0xFE );
+ DO_D( VPERMILPS_128_0x30 );
+ DO_D( VPERMILPS_128_0x21 );
+ DO_D( VPERMILPS_128_0xD7 );
+ DO_D( VPERMILPS_128_0xB5 );
+ DO_D( VPERMILPS_128_0x85 );
+ DO_D( VPERMILPS_128_0x29 );
+ DO_D( VBLENDPS_128_1of3 );
+ DO_D( VBLENDPS_128_2of3 );
+ DO_D( VBLENDPS_128_3of3 );
+ DO_D( VBLENDPD_128_1of2 );
+ DO_D( VBLENDPD_128_2of2 );
+ DO_D( VBLENDPD_256_1of3 );
+ DO_D( VBLENDPD_256_2of3 );
+ DO_D( VBLENDPD_256_3of3 );
+ DO_D( VPBLENDW_128_0x00 );
+ DO_D( VPBLENDW_128_0xFE );
+ DO_D( VPBLENDW_128_0x30 );
+ DO_D( VPBLENDW_128_0x21 );
+ DO_D( VPBLENDW_128_0xD7 );
+ DO_D( VPBLENDW_128_0xB5 );
+ DO_D( VPBLENDW_128_0x85 );
+ DO_D( VPBLENDW_128_0x29 );
+ DO_D( VMOVUPS_EtoG_256 );
+ DO_D( VSQRTSS_128 );
+ DO_D( VSQRTPS_128 );
+ DO_D( VSQRTPS_256 );
+ DO_D( VSQRTPD_128 );
+ DO_D( VSQRTPD_256 );
+ DO_D( VRSQRTSS_128 );
+ DO_D( VRSQRTPS_128 );
+ DO_D( VRSQRTPS_256 );
+ DO_D( VMOVDQU_GtoE_256 );
+ DO_D( VCVTPS2PD_256 );
+ DO_D( VCVTTPS2DQ_128 );
+ DO_D( VCVTTPS2DQ_256 );
+ DO_D( VCVTDQ2PS_128 );
+ DO_D( VCVTDQ2PS_256 );
+ DO_D( VCVTTPD2DQ_128 );
+ DO_D( VCVTTPD2DQ_256 );
+ DO_D( VCVTPD2DQ_128 );
+ DO_D( VCVTPD2DQ_256 );
+ DO_D( VMOVSLDUP_128 );
+ DO_D( VMOVSLDUP_256 );
+ DO_D( VMOVSHDUP_128 );
+ DO_D( VMOVSHDUP_256 );
+ DO_D( VPERMILPS_VAR_128 );
+ DO_D( VPERMILPD_VAR_128 );
+ DO_D( VPERMILPS_VAR_256 );
+ DO_D( VPERMILPD_VAR_256 );
+ DO_D( VPSLLW_128 );
+ DO_D( VPSRLW_128 );
+ DO_D( VPSRAW_128 );
+ DO_D( VPSLLD_128 );
+ DO_D( VPSRLD_128 );
+ DO_D( VPSRAD_128 );
+ DO_D( VPSLLQ_128 );
+ DO_D( VPSRLQ_128 );
+ DO_D( VROUNDPS_128_0x0 );
+ DO_D( VROUNDPS_128_0x1 );
+ DO_D( VROUNDPS_128_0x2 );
+ DO_D( VROUNDPS_128_0x3 );
+ DO_D( VROUNDPS_128_0x4 );
+ DO_D( VROUNDPS_256_0x0 );
+ DO_D( VROUNDPS_256_0x1 );
+ DO_D( VROUNDPS_256_0x2 );
+ DO_D( VROUNDPS_256_0x3 );
+ DO_D( VROUNDPS_256_0x4 );
+ DO_D( VROUNDPD_128_0x0 );
+ DO_D( VROUNDPD_128_0x1 );
+ DO_D( VROUNDPD_128_0x2 );
+ DO_D( VROUNDPD_128_0x3 );
+ DO_D( VROUNDPD_128_0x4 );
+ DO_D( VROUNDPD_256_0x0 );
+ DO_D( VROUNDPD_256_0x1 );
+ DO_D( VROUNDPD_256_0x2 );
+ DO_D( VROUNDPD_256_0x3 );
+ DO_D( VROUNDPD_256_0x4 );
+ DO_D( VROUNDSS_0x0 );
+ DO_D( VROUNDSS_0x1 );
+ DO_D( VROUNDSS_0x2 );
+ DO_D( VROUNDSS_0x3 );
+ DO_D( VROUNDSS_0x4 );
+ DO_D( VROUNDSS_0x5 );
+ DO_D( VROUNDSD_0x0 );
+ DO_D( VROUNDSD_0x1 );
+ DO_D( VROUNDSD_0x2 );
+ DO_D( VROUNDSD_0x3 );
+ DO_D( VROUNDSD_0x4 );
+ DO_D( VROUNDSD_0x5 );
+ DO_D( VPTEST_128_1 );
+ DO_D( VPTEST_128_2 );
+ DO_D( VPTEST_256_1 );
+ DO_D( VPTEST_256_2 );
+ DO_D( VTESTPS_128_1 );
+ DO_D( VTESTPS_128_2 );
+ DO_N( 10, VTESTPS_128_3 );
+ DO_D( VTESTPS_256_1 );
+ DO_D( VTESTPS_256_2 );
+ DO_N( 10, VTESTPS_256_3 );
+ DO_D( VTESTPD_128_1 );
+ DO_D( VTESTPD_128_2 );
+ DO_N( 10, VTESTPD_128_3 );
+ DO_D( VTESTPD_256_1 );
+ DO_D( VTESTPD_256_2 );
+ DO_N( 10, VTESTPD_256_3 );
+ DO_D( VBLENDVPS_128 );
+ DO_D( VBLENDVPS_256 );
+ DO_D( VBLENDVPD_128 );
+ DO_D( VBLENDVPD_256 );
+ DO_D( VPMULDQ_128 );
+ DO_D( VCMPPD_256_0x4 );
+ DO_D( VCMPPS_128_0x4 );
+ DO_D( VCMPPS_256_0x4 );
+ DO_D( VPCMPGTB_128 );
+ DO_D( VPCMPGTW_128 );
+ DO_D( VPMADDWD_128 );
+ DO_D( VADDSUBPS_128 );
+ DO_D( VADDSUBPS_256 );
+ DO_D( VADDSUBPD_128 );
+ DO_D( VADDSUBPD_256 );
+ DO_D( VCVTSS2SI_64 );
+ DO_D( VCVTSS2SI_32 );
+ DO_D( VCVTSD2SI_32 );
+ DO_D( VCVTSD2SI_64 );
+ DO_D( VDPPS_128_1of4 );
+ DO_D( VDPPS_128_2of4 );
+ DO_D( VDPPS_128_3of4 );
+ DO_D( VDPPS_128_4of4 );
+ DO_D( VDPPS_256_1of4 );
+ DO_D( VDPPS_256_2of4 );
+ DO_D( VDPPS_256_3of4 );
+ DO_D( VDPPS_256_4of4 );
+ DO_D( VHADDPS_128 );
+ DO_D( VHADDPS_256 );
+ DO_D( VHADDPD_128 );
+ DO_D( VHADDPD_256 );
+ DO_D( VHSUBPS_128 );
+ DO_D( VHSUBPS_256 );
+ DO_D( VHSUBPD_128 );
+ DO_D( VHSUBPD_256 );
+ DO_D( VEXTRACTPS_0x0 );
+ DO_D( VEXTRACTPS_0x1 );
+ DO_D( VEXTRACTPS_0x2 );
+ DO_D( VEXTRACTPS_0x3 );
+ DO_D( VLDDQU_128 );
+ DO_D( VLDDQU_256 );
+ DO_D( VMAXPS_256 );
+ DO_D( VMAXPD_128 );
+ DO_D( VMAXPD_256 );
+ DO_D( VMINPS_256 );
+ DO_D( VMINPD_128 );
+ DO_D( VMINPD_256 );
+ DO_D( VMOVHPS_128_StoreForm );
+ DO_D( VMOVNTDQ_256 );
+ DO_D( VMOVHPS_128_LoadForm );
+ DO_D( VMOVNTDQA_128 );
+ DO_D( VMASKMOVDQU_128 );
+ DO_D( VMOVMSKPD_128 );
+ DO_D( VMOVMSKPD_256 );
+ DO_D( VMOVMSKPS_128 );
+ DO_D( VMOVMSKPS_256 );
+ DO_D( VMOVNTPD_128 );
+ DO_D( VMOVNTPD_256 );
+ DO_D( VMOVNTPS_128 );
+ DO_D( VMOVNTPS_256 );
+ DO_D( VPACKSSWB_128 );
+ DO_D( VPAVGB_128 );
+ DO_D( VPAVGW_128 );
+ DO_D( VPADDSB_128 );
+ DO_D( VPADDSW_128 );
+ DO_D( VPHADDW_128 );
+ DO_D( VPHADDD_128 );
+ DO_D( VPHADDSW_128 );
+ DO_D( VPMADDUBSW_128 );
+ DO_D( VPHSUBW_128 );
+ DO_D( VPHSUBD_128 );
+ DO_D( VPHSUBSW_128 );
+ DO_D( VPABSB_128 );
+ DO_D( VPABSW_128 );
+ DO_D( VPMOVSXBQ_128 );
+ DO_D( VPMOVSXWQ_128 );
+ DO_D( VPACKUSDW_128 );
+ DO_D( VPMOVZXBQ_128 );
+ DO_D( VPMOVZXWQ_128 );
+ DO_D( VPMOVZXDQ_128 );
+ DO_D( VMPSADBW_128_0x0 );
+ DO_D( VMPSADBW_128_0x1 );
+ DO_D( VMPSADBW_128_0x2 );
+ DO_D( VMPSADBW_128_0x3 );
+ DO_D( VMPSADBW_128_0x4 );
+ DO_D( VMPSADBW_128_0x5 );
+ DO_D( VMPSADBW_128_0x6 );
+ DO_D( VMPSADBW_128_0x7 );
+ DO_D( VMOVDDUP_YMMorMEM256_to_YMM );
+ DO_D( VMOVLPS_128_M64_XMM_XMM );
+ DO_D( VMOVLPS_128_XMM_M64 );
+ DO_D( VRCPSS_128 );
+ DO_D( VRCPPS_128 );
+ DO_D( VRCPPS_256 );
+ DO_D( VPSADBW_128 );
+ DO_D( VPSIGNB_128 );
+ DO_D( VPSIGNW_128 );
+ DO_D( VPSIGND_128 );
+ DO_D( VPMULHRSW_128 );
+ DO_D( VBROADCASTF128 );
+ DO_D( VPEXTRW_128_0x0 );
+ DO_D( VPEXTRW_128_0x1 );
+ DO_D( VPEXTRW_128_0x2 );
+ DO_D( VPEXTRW_128_0x3 );
+ DO_D( VPEXTRW_128_0x4 );
+ DO_D( VPEXTRW_128_0x5 );
+ DO_D( VPEXTRW_128_0x6 );
+ DO_D( VPEXTRW_128_0x7 );
+ DO_D( VAESENC );
+ DO_D( VAESENCLAST );
+ DO_D( VAESDEC );
+ DO_D( VAESDECLAST );
+ DO_D( VAESIMC );
+ DO_D( VAESKEYGENASSIST_0x00 );
+ DO_D( VAESKEYGENASSIST_0x31 );
+ DO_D( VAESKEYGENASSIST_0xB2 );
+ DO_D( VAESKEYGENASSIST_0xFF );
+ DO_D( VPCLMULQDQ_0x00 );
+ DO_D( VPCLMULQDQ_0x01 );
+ DO_D( VPCLMULQDQ_0x10 );
+ DO_D( VPCLMULQDQ_0x11 );
+ DO_D( VPCLMULQDQ_0xFF );
+ DO_D( VCMPSS_128_0x9 );
+ return 0;
+}
+
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/amd64/avx-1.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/amd64/avx-1.stderr.exp
diff --git a/main/none/tests/amd64/avx-1.stdout.exp b/main/none/tests/amd64/avx-1.stdout.exp
new file mode 100644
index 0000000..4a2d9fb
--- /dev/null
+++ b/main/none/tests/amd64/avx-1.stdout.exp
@@ -0,0 +1,42795 @@
+VMOVUPD_EtoG_256(reg)
+ before
+ 7d6528c5fa956a0d.69c3e9a6af27d13b.5175e39d19c9ca1e.98f24a4984175700
+ b6d2fb5aa7bc5127.fe9915e556a044b2.60b160857d45c484.47b8d8c0eeef1e50
+ 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38
+ cb509970b8136c85.d740b80eb7839b97.d89998df5035ed36.4a4bc43968bc40e5
+ 56b01a12b0ca1583
+ after
+ 7d6528c5fa956a0d.69c3e9a6af27d13b.5175e39d19c9ca1e.98f24a4984175700
+ b6d2fb5aa7bc5127.fe9915e556a044b2.60b160857d45c484.47b8d8c0eeef1e50
+ 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38
+ 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38
+ 56b01a12b0ca1583
+VMOVUPD_EtoG_256(mem)
+ before
+ 398e0039cf03663d.5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db
+ cfaff39be272ef40.20a1bb92cbc97fe8.542da4983df76c96.d8bc5c6dee699597
+ f4e06e2205236eb7.6897b536bbe4da8a.369dab4f9465b86e.d182c916cebc2e17
+ 84ededbc53239dcf.95264321bf3b68b2.55c2b9e2c95c9810.407b8d9035449b06
+ 81f2a547be8d1811
+ after
+ 398e0039cf03663d.5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db
+ cfaff39be272ef40.20a1bb92cbc97fe8.542da4983df76c96.d8bc5c6dee699597
+ 398e0039cf03663d.5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db
+ 84ededbc53239dcf.95264321bf3b68b2.55c2b9e2c95c9810.407b8d9035449b06
+ 81f2a547be8d1811
+
+VMOVUPD_EtoG_256(reg)
+ before
+ f0350ca70523e0e4.5ba1ec54e87d39b3.019963bf7459630b.8d69483df7e8c6a9
+ e98ebd1ca893312a.54cae7d5e13dfe91.0a3e0f7c75cb0842.b95ed64d3b13ff64
+ c84ab71340684590.4d325b2d5a70a792.0a5f45c55f1c9202.b76ddefcb0ebfe6e
+ e9b5f3f66b2e58c1.21a6c3476d21f1e5.5f490104ced83ff8.6262dd37727c80f3
+ 96084deb9ed0411e
+ after
+ f0350ca70523e0e4.5ba1ec54e87d39b3.019963bf7459630b.8d69483df7e8c6a9
+ e98ebd1ca893312a.54cae7d5e13dfe91.0a3e0f7c75cb0842.b95ed64d3b13ff64
+ c84ab71340684590.4d325b2d5a70a792.0a5f45c55f1c9202.b76ddefcb0ebfe6e
+ c84ab71340684590.4d325b2d5a70a792.0a5f45c55f1c9202.b76ddefcb0ebfe6e
+ 96084deb9ed0411e
+VMOVUPD_EtoG_256(mem)
+ before
+ 2e2dac0350f6fd1c.a81b6e33c572a86a.acf29b0f395c98b4.63483da65c8c49d0
+ 089b756aa3f77018.61c82534e9bf6f37.c9e25f72d82e582b.73a8f718a8c3ec35
+ ff1f240eb3e1553f.6f07136773a2ead3.56428c5a66a2ec77.ecb42ac54b0966d4
+ ee8536da9dbf68bc.3026343700a654eb.2ddd9db4ffc411c4.28bad218e4ebf159
+ 8404eb7f0cf4ca6f
+ after
+ 2e2dac0350f6fd1c.a81b6e33c572a86a.acf29b0f395c98b4.63483da65c8c49d0
+ 089b756aa3f77018.61c82534e9bf6f37.c9e25f72d82e582b.73a8f718a8c3ec35
+ 2e2dac0350f6fd1c.a81b6e33c572a86a.acf29b0f395c98b4.63483da65c8c49d0
+ ee8536da9dbf68bc.3026343700a654eb.2ddd9db4ffc411c4.28bad218e4ebf159
+ 8404eb7f0cf4ca6f
+
+VMOVUPD_EtoG_256(reg)
+ before
+ 5cdf726562b02dc2.b39925ba7d9d67bc.ff6f850f2c57ea2a.2c810e6dc1a1833d
+ 0c9761367fac55ff.28276f9a6e880c6b.372f015d9242e83d.2ef85b6fc544fd0f
+ f078b65e01737fd2.2bfa8f668c8b14f4.36b2a38dcef18acf.0e0f01a829ba3c66
+ 65ce6d498492e7e7.96df010bf4b23b84.57436a097df30b8d.aa927a03090dfc6d
+ dc4c446c804bf950
+ after
+ 5cdf726562b02dc2.b39925ba7d9d67bc.ff6f850f2c57ea2a.2c810e6dc1a1833d
+ 0c9761367fac55ff.28276f9a6e880c6b.372f015d9242e83d.2ef85b6fc544fd0f
+ f078b65e01737fd2.2bfa8f668c8b14f4.36b2a38dcef18acf.0e0f01a829ba3c66
+ f078b65e01737fd2.2bfa8f668c8b14f4.36b2a38dcef18acf.0e0f01a829ba3c66
+ dc4c446c804bf950
+VMOVUPD_EtoG_256(mem)
+ before
+ 810bdacfab80ee3d.c5e48064a393c8e9.47a34273c10a3c47.f5304f3e3ad1a923
+ 769ab818a5b7985e.6d08ed19fa045f84.1810cd8c109ed568.6ec34f98a2199d3c
+ 95c45b338afcb3df.b984aed62671e865.e6f21d40fc7bc013.1c4a678450562685
+ bc563e0c775bfaed.05a5c205c3659f38.8e17b17da2acb976.5d0f926ce1157eaa
+ 8b5fccbef0e1e256
+ after
+ 810bdacfab80ee3d.c5e48064a393c8e9.47a34273c10a3c47.f5304f3e3ad1a923
+ 769ab818a5b7985e.6d08ed19fa045f84.1810cd8c109ed568.6ec34f98a2199d3c
+ 810bdacfab80ee3d.c5e48064a393c8e9.47a34273c10a3c47.f5304f3e3ad1a923
+ bc563e0c775bfaed.05a5c205c3659f38.8e17b17da2acb976.5d0f926ce1157eaa
+ 8b5fccbef0e1e256
+
+VMOVUPD_GtoE_256(reg)
+ before
+ 048612e51a468e36.c51cdd8f87e12ab4.acb722146c6cbfa9.ea4a022e1d3d7dbb
+ 22cf5e4cfad1bdf5.8de2b4a9d799ff5f.0c05cb6ebd128663.d7568e3e8a3ac80e
+ 4288ae612c0dad40.f0733f448390351b.80ddba7e53e42d12.3208cf9b04b0569c
+ c1fbfd8f4d8698c2.cb9dfb4ea5d18713.6489eab2c96df363.d52c4330a7aae391
+ 9d8e66ea90352a18
+ after
+ 048612e51a468e36.c51cdd8f87e12ab4.acb722146c6cbfa9.ea4a022e1d3d7dbb
+ 22cf5e4cfad1bdf5.8de2b4a9d799ff5f.0c05cb6ebd128663.d7568e3e8a3ac80e
+ c1fbfd8f4d8698c2.cb9dfb4ea5d18713.6489eab2c96df363.d52c4330a7aae391
+ c1fbfd8f4d8698c2.cb9dfb4ea5d18713.6489eab2c96df363.d52c4330a7aae391
+ 9d8e66ea90352a18
+VMOVUPD_GtoE_256(mem)
+ before
+ 66fab2b3db5ce85e.f9754842f9c9ba28.f82a63b15c68b274.14575775bc3a1202
+ 0c3ca578a32bd88e.474289e7cb61501e.54e7f35bc162726a.ec91fe34c7d6c79a
+ 6b1fba2604afb8d5.08aebee85fda964f.bba02737f3c98220.4784d95987cd4ed8
+ 5f706da71bf2425f.9605e2b252c1c868.09217c310baca0c3.837be65197abe268
+ fbc4208894fdc0f5
+ after
+ 6b1fba2604afb8d5.08aebee85fda964f.bba02737f3c98220.4784d95987cd4ed8
+ 0c3ca578a32bd88e.474289e7cb61501e.54e7f35bc162726a.ec91fe34c7d6c79a
+ 6b1fba2604afb8d5.08aebee85fda964f.bba02737f3c98220.4784d95987cd4ed8
+ 5f706da71bf2425f.9605e2b252c1c868.09217c310baca0c3.837be65197abe268
+ fbc4208894fdc0f5
+
+VMOVUPD_GtoE_256(reg)
+ before
+ 0aaa836b194e242c.c5fc3ae904033357.4e92f1b240a12214.1a366d352714867e
+ 0e780c65c22b4ab8.778d9ed6d9eb46ea.8ca3e752c306df00.caab752f630ff07e
+ 627bb6e12d1f6d46.51ef145cb9b83843.ac82c1007a7d3cd8.f54b130cdaa89cef
+ 61ff7d4df3b6ca81.31f01866bd76c58f.0a7c7a27fe917447.77e3c0b6a9ec44fc
+ 2c3ffa1aebe6a4d2
+ after
+ 0aaa836b194e242c.c5fc3ae904033357.4e92f1b240a12214.1a366d352714867e
+ 0e780c65c22b4ab8.778d9ed6d9eb46ea.8ca3e752c306df00.caab752f630ff07e
+ 61ff7d4df3b6ca81.31f01866bd76c58f.0a7c7a27fe917447.77e3c0b6a9ec44fc
+ 61ff7d4df3b6ca81.31f01866bd76c58f.0a7c7a27fe917447.77e3c0b6a9ec44fc
+ 2c3ffa1aebe6a4d2
+VMOVUPD_GtoE_256(mem)
+ before
+ f02b3b25bca27a9c.69505d14b27d9d16.f25b26e0042fa9fa.02dd0e32eecfc5fa
+ 9f7301c1392d8087.d4ba52a206ff21b1.70fbbab6a7f19faf.f0f1798fe3c1699c
+ 15e3c8dc7e9273bf.0088596389c893fd.879d51d4c5c764db.3004b7a97cf69dda
+ 2d460a61a5dd0f6f.47086cc3da642fa7.130d662777beb4a9.1e61c5ec52f79c60
+ 16559ec50352a3d9
+ after
+ 15e3c8dc7e9273bf.0088596389c893fd.879d51d4c5c764db.3004b7a97cf69dda
+ 9f7301c1392d8087.d4ba52a206ff21b1.70fbbab6a7f19faf.f0f1798fe3c1699c
+ 15e3c8dc7e9273bf.0088596389c893fd.879d51d4c5c764db.3004b7a97cf69dda
+ 2d460a61a5dd0f6f.47086cc3da642fa7.130d662777beb4a9.1e61c5ec52f79c60
+ 16559ec50352a3d9
+
+VMOVUPD_GtoE_256(reg)
+ before
+ 742c3e9e2b92eef2.c569453ccd1b0fc4.0784892e9360315b.f0177599dbe14b46
+ 9432a2e46543b956.b819f459105730e9.9a49ac115048d4c4.f987fa170d3ce4dd
+ d2b3c4044ef23fb2.e22093a48a9d2e0b.5da3cfd6aea6558e.0c28728e28dc3c9c
+ 89fba268812abdb2.1e4a9e0958fac555.adddf0eb4808f067.04c857e949cc0fac
+ bc3127138b19183c
+ after
+ 742c3e9e2b92eef2.c569453ccd1b0fc4.0784892e9360315b.f0177599dbe14b46
+ 9432a2e46543b956.b819f459105730e9.9a49ac115048d4c4.f987fa170d3ce4dd
+ 89fba268812abdb2.1e4a9e0958fac555.adddf0eb4808f067.04c857e949cc0fac
+ 89fba268812abdb2.1e4a9e0958fac555.adddf0eb4808f067.04c857e949cc0fac
+ bc3127138b19183c
+VMOVUPD_GtoE_256(mem)
+ before
+ 12305efa0acd1475.1755377e9a786f01.4a6592749579b0f4.e4450ababbfae0f9
+ e1917689e3f6bf86.d70f7fb13667914c.413cead25e27ac14.5f2619b1a20662f0
+ 0420edac31a0d599.2573776df1835e3e.de9a220dce0e75e0.7acb193b9abab2f9
+ 59a93d4f11d611db.5cce191e65591384.ff4cb613013cc685.918107c43ea20cc0
+ 0194ddb82b49abf0
+ after
+ 0420edac31a0d599.2573776df1835e3e.de9a220dce0e75e0.7acb193b9abab2f9
+ e1917689e3f6bf86.d70f7fb13667914c.413cead25e27ac14.5f2619b1a20662f0
+ 0420edac31a0d599.2573776df1835e3e.de9a220dce0e75e0.7acb193b9abab2f9
+ 59a93d4f11d611db.5cce191e65591384.ff4cb613013cc685.918107c43ea20cc0
+ 0194ddb82b49abf0
+
+VPSUBW_128(reg)
+ before
+ 24509983fc3bcc36.baf7e45e9fa43077.da6c63303173ecc9.7e1e22cf15bd5c2f
+ 570037914d04ab3d.05d75ec6f616ee9a.fa99500fef6024ba.39dce32c239cf309
+ f6f2b14fbb3184b2.141625713239066f.17a0dc273ba9f803.0a52741849e54740
+ 5d700527e24d9241.c57eb74d70183523.8fcf04e5b2dca44f.cf4c517ea3a413ff
+ 6295f64a4ce61473
+ after
+ 0000000000000000.0000000000000000.e2f973e8b3b72cb7.2f8a6f14d9b7abc9
+ 570037914d04ab3d.05d75ec6f616ee9a.fa99500fef6024ba.39dce32c239cf309
+ f6f2b14fbb3184b2.141625713239066f.17a0dc273ba9f803.0a52741849e54740
+ 5d700527e24d9241.c57eb74d70183523.8fcf04e5b2dca44f.cf4c517ea3a413ff
+ 6295f64a4ce61473
+VPSUBW_128(mem)
+ before
+ a0fae06860b606c7.e8c72e865de41295.f2db8f44cbbf37e2.bc70c3b3ef84644b
+ 66478ac4fc21a428.f34428d9c8833f5b.78fb29445f3bc8d7.fcd015ff8f2e73a3
+ 8e48704b3c31abc2.da30ef8bc0b5573e.34a901384a97a32f.a93bf6332d650e02
+ f5c90ee73af5d7c0.f9da7f07e00794eb.00b0940ba5e08516.20fd62bd65b57115
+ be625608d5abd787
+ after
+ a0fae06860b606c7.e8c72e865de41295.f2db8f44cbbf37e2.bc70c3b3ef84644b
+ 66478ac4fc21a428.f34428d9c8833f5b.78fb29445f3bc8d7.fcd015ff8f2e73a3
+ 0000000000000000.0000000000000000.86209a00937c90f5.4060524c9faa0f58
+ f5c90ee73af5d7c0.f9da7f07e00794eb.00b0940ba5e08516.20fd62bd65b57115
+ be625608d5abd787
+
+VPSUBW_128(reg)
+ before
+ ddb5cd8016d27d05.7796e0861576e44f.ac8dd5bbc503330e.b9dd5dab8e212ab7
+ db43c391c6b69f3a.f17a6312e7c28d9a.4e94ec120b386f52.3bfcd80321664d3e
+ 125934a781e479d3.3d431279cce48fce.3d3cc0784c2f8563.63d9810079bbabd9
+ df411d2ee2e7467c.38bb69a6e1e9a617.d4d14e592776b1ef.0b40d58cb22d00b1
+ 10fd4e94e9c808f5
+ after
+ 0000000000000000.0000000000000000.11582b9abf09e9ef.d8235703a7aba165
+ db43c391c6b69f3a.f17a6312e7c28d9a.4e94ec120b386f52.3bfcd80321664d3e
+ 125934a781e479d3.3d431279cce48fce.3d3cc0784c2f8563.63d9810079bbabd9
+ df411d2ee2e7467c.38bb69a6e1e9a617.d4d14e592776b1ef.0b40d58cb22d00b1
+ 10fd4e94e9c808f5
+VPSUBW_128(mem)
+ before
+ 4edb6a053a967ecf.9e477892854b43e0.beafe48541dc8da0.6f9f902235982fa0
+ a1a7a4c9c0a51f6b.acb9433f079dacac.abeb000208c90296.69f2843d15223a22
+ e52e79ce9700a7f7.63e279a20368bc8b.db3b370954bcbf24.20162517609f0f22
+ f63a63fedcb4d29c.200d17261638b12a.2a6a07863ec28077.ef56701db49bea4c
+ 31005fb9ada2074b
+ after
+ 4edb6a053a967ecf.9e477892854b43e0.beafe48541dc8da0.6f9f902235982fa0
+ a1a7a4c9c0a51f6b.acb9433f079dacac.abeb000208c90296.69f2843d15223a22
+ 0000000000000000.0000000000000000.ed3c1b7dc6ed74f6.fa53f41bdf8a0a82
+ f63a63fedcb4d29c.200d17261638b12a.2a6a07863ec28077.ef56701db49bea4c
+ 31005fb9ada2074b
+
+VPSUBW_128(reg)
+ before
+ 445ef059e641a1cc.b097e047aacc5b89.3f871736dc9ac535.7446eb65e4e703bb
+ 83bd1e68fb03f57b.ef136b941e54ffe8.1c9c7740ef193457.959960926235021b
+ 4969e55289753f03.8f7980d1535979e5.139832afee423c3d.6930e0fad3ba39c4
+ f4ad41832c22ba11.6c949cea66e687ae.80c745ef729f1792.ccd7e987538166e1
+ 9a5af627ff97439f
+ after
+ 0000000000000000.0000000000000000.0904449100d7f81a.2c697f988e7bc857
+ 83bd1e68fb03f57b.ef136b941e54ffe8.1c9c7740ef193457.959960926235021b
+ 4969e55289753f03.8f7980d1535979e5.139832afee423c3d.6930e0fad3ba39c4
+ f4ad41832c22ba11.6c949cea66e687ae.80c745ef729f1792.ccd7e987538166e1
+ 9a5af627ff97439f
+VPSUBW_128(mem)
+ before
+ af8484c5f3078d2a.ded72f677f96a350.623139cb7207e36c.bf75aa6c1abe0103
+ e6230d4d4add00ad.6431aa6a1e5e366d.4c1cd56194c94a4e.2ced5f927f2b383c
+ 1d010fab20265755.e309aef8a605af13.0821eb96e737777e.237d5fcd3f71f6e8
+ 2feb05cb92ed4f4d.b5a9377eb31749ef.710cf757885d2728.006fa689f61c78b4
+ 1f1030333fb8fa4b
+ after
+ af8484c5f3078d2a.ded72f677f96a350.623139cb7207e36c.bf75aa6c1abe0103
+ e6230d4d4add00ad.6431aa6a1e5e366d.4c1cd56194c94a4e.2ced5f927f2b383c
+ 0000000000000000.0000000000000000.e9eb9b9622c266e2.6d78b526646d3739
+ 2feb05cb92ed4f4d.b5a9377eb31749ef.710cf757885d2728.006fa689f61c78b4
+ 1f1030333fb8fa4b
+
+VPSUBQ_128(reg)
+ before
+ dbacfa35b7d2b75a.f8ad6b99bb3fa4c2.385e4166df2141ad.63a8769192481679
+ 928efefdf9f5ec8d.5313bd01b82612e0.c673c91ec9aed3f8.b9c3e32f2103009d
+ 9f043af6a1aed58f.1ee978efa4b054d2.bc36ca100a4a3a7d.5127ba1c529aa0bf
+ 5e58aa8b4c88ae0d.34fa174f9ce927c4.76f140aa4182b4e7.06a17746411ab40c
+ b3fd9698098ef5b0
+ after
+ 0000000000000000.0000000000000000.0a3cff0ebf64997b.689c2912ce685fde
+ 928efefdf9f5ec8d.5313bd01b82612e0.c673c91ec9aed3f8.b9c3e32f2103009d
+ 9f043af6a1aed58f.1ee978efa4b054d2.bc36ca100a4a3a7d.5127ba1c529aa0bf
+ 5e58aa8b4c88ae0d.34fa174f9ce927c4.76f140aa4182b4e7.06a17746411ab40c
+ b3fd9698098ef5b0
+VPSUBQ_128(mem)
+ before
+ 360794fec60222d6.2ad7482a960fb2b2.7014160ebbdb47e4.51f2275707e17ae4
+ 698bec649583f5aa.61cd123e19cf1e2b.b001f1161e946f5c.a7837c83faf3cb1d
+ 2a541ab7911c2b5a.5e86033374552e23.ce8e2455e0205c58.d5f13a9ab645e140
+ 532f9ae1d7da8010.7c4e1775412d1d47.a8872cb61d8aca05.37885d08d662faf9
+ 2993e139f7d64ff4
+ after
+ 360794fec60222d6.2ad7482a960fb2b2.7014160ebbdb47e4.51f2275707e17ae4
+ 698bec649583f5aa.61cd123e19cf1e2b.b001f1161e946f5c.a7837c83faf3cb1d
+ 0000000000000000.0000000000000000.3feddb0762b92778.5591552cf3125039
+ 532f9ae1d7da8010.7c4e1775412d1d47.a8872cb61d8aca05.37885d08d662faf9
+ 2993e139f7d64ff4
+
+VPSUBQ_128(reg)
+ before
+ 0760c299b42e1fdc.c2e9e9cf82c7aff8.19714a711ce12843.18b88425f2de758f
+ 2d39fd95a9f5a45d.514c816eaff2763f.8f3a9991a2ff8bc2.fceca88e7b281821
+ f76b8d9773b81b24.de24e0a879648e11.3cf6fe426e128171.2ef114ddd37570e8
+ c1426e0dae01c0dd.433f816bfd2bb699.7af177f11da748fc.8b9145fe16d0390f
+ f099b6dd61462ec3
+ after
+ 0000000000000000.0000000000000000.52439b4f34ed0a51.cdfb93b0a7b2a739
+ 2d39fd95a9f5a45d.514c816eaff2763f.8f3a9991a2ff8bc2.fceca88e7b281821
+ f76b8d9773b81b24.de24e0a879648e11.3cf6fe426e128171.2ef114ddd37570e8
+ c1426e0dae01c0dd.433f816bfd2bb699.7af177f11da748fc.8b9145fe16d0390f
+ f099b6dd61462ec3
+VPSUBQ_128(mem)
+ before
+ 37d5e366d0e20c30.e70a9c61f55fce33.5d68e1a25652a804.a77700084a491a0e
+ 3d1148867eb08f81.c50f1401e45b82d3.086a7a39a1e6217d.1dd493f591843454
+ de18612787bc73e3.b79cd05818831869.2112ca1cf9f1dd31.3a542e238fe5d179
+ f7b8ab3708137382.19ffced22c62cba0.822c4c377b82984c.5842cbfee0f72e2a
+ d4ec68f21f468712
+ after
+ 37d5e366d0e20c30.e70a9c61f55fce33.5d68e1a25652a804.a77700084a491a0e
+ 3d1148867eb08f81.c50f1401e45b82d3.086a7a39a1e6217d.1dd493f591843454
+ 0000000000000000.0000000000000000.ab0198974b937979.765d93ed473b1a46
+ f7b8ab3708137382.19ffced22c62cba0.822c4c377b82984c.5842cbfee0f72e2a
+ d4ec68f21f468712
+
+VPSUBQ_128(reg)
+ before
+ 0b9c016be95f18de.62bba1a11cc04c89.478209dbbd84d925.08847c7642a20df9
+ 579f90d5d9cd1c3a.fceebf50e0d0ba24.9c727edf66767ca3.8fe6d7c56a5ff965
+ 1541139c8b1cd0d1.a11d81326f4e7880.761b274ac4c4f0c7.f31ed81010c417bc
+ a1cd852d9cd97050.2d146432e64644c9.30c9028972f8733d.11f7fa4450de2529
+ c33ebc4b44b8ddd8
+ after
+ 0000000000000000.0000000000000000.26575794a1b18bdc.9cc7ffb5599be1a9
+ 579f90d5d9cd1c3a.fceebf50e0d0ba24.9c727edf66767ca3.8fe6d7c56a5ff965
+ 1541139c8b1cd0d1.a11d81326f4e7880.761b274ac4c4f0c7.f31ed81010c417bc
+ a1cd852d9cd97050.2d146432e64644c9.30c9028972f8733d.11f7fa4450de2529
+ c33ebc4b44b8ddd8
+VPSUBQ_128(mem)
+ before
+ e6c097130b5efcf6.5791e2f2a78f3762.7c9fe23c60c5d82b.25c80a060da03fb0
+ 56470887bfdd3daf.94d7265949ca62b4.6a8a793cf9d5f0d1.b3633c2f304791cd
+ ef9f8c927c405d2f.b2ed4ecc1e172df2.d3a0a41fce854ae7.35e7926e777aa43f
+ 8d969e225f9318a0.0e1d55b9c001d4c7.93aee0cffbdea09a.06a10a317fc4b5b3
+ 84db9fe3e4b100d4
+ after
+ e6c097130b5efcf6.5791e2f2a78f3762.7c9fe23c60c5d82b.25c80a060da03fb0
+ 56470887bfdd3daf.94d7265949ca62b4.6a8a793cf9d5f0d1.b3633c2f304791cd
+ 0000000000000000.0000000000000000.edea9700991018a6.8d9b322922a7521d
+ 8d969e225f9318a0.0e1d55b9c001d4c7.93aee0cffbdea09a.06a10a317fc4b5b3
+ 84db9fe3e4b100d4
+
+VPADDQ_128(reg)
+ before
+ 09e14df041cdc14f.0bf7ba2283e22a31.04b4378bce1492e0.8680a7399beeae16
+ f30110c432a534d0.478d5d7e053a4e0c.f0fdf0aee1dda4e8.88e2774acbc13287
+ 9c86e5cb54c59402.1c25022200a7415e.2e467d8e98e7468c.75a0cbeda561e618
+ 62bbc77143b71e92.668b24fb9133bf52.1adad8978cbfb478.29861f0d48dc87f5
+ 805ff098ce3ed14b
+ after
+ 0000000000000000.0000000000000000.1f446e3d7ac4eb74.fe8343387123189f
+ f30110c432a534d0.478d5d7e053a4e0c.f0fdf0aee1dda4e8.88e2774acbc13287
+ 9c86e5cb54c59402.1c25022200a7415e.2e467d8e98e7468c.75a0cbeda561e618
+ 62bbc77143b71e92.668b24fb9133bf52.1adad8978cbfb478.29861f0d48dc87f5
+ 805ff098ce3ed14b
+VPADDQ_128(mem)
+ before
+ 55f9b97953917f46.9fedb2229a090d2c.018b42f3d3ec8415.1004ff355bf02957
+ 861ef69cf4e34e11.b168a24af5479e7b.c9f1d5f8e2de4bd3.6c11edd5a106e2d6
+ ee9b23edcc40fad9.f2789356f1fb0d2b.99885af4db13d1b7.894d9fe1f98d1aa0
+ 683cbc58f8b23fca.bf6982b029b396ea.4f1e4ed5da99d2ee.c5040fc700120f62
+ 7b813bf15120fbc8
+ after
+ 55f9b97953917f46.9fedb2229a090d2c.018b42f3d3ec8415.1004ff355bf02957
+ 861ef69cf4e34e11.b168a24af5479e7b.c9f1d5f8e2de4bd3.6c11edd5a106e2d6
+ 0000000000000000.0000000000000000.cb7d18ecb6cacfe8.7c16ed0afcf70c2d
+ 683cbc58f8b23fca.bf6982b029b396ea.4f1e4ed5da99d2ee.c5040fc700120f62
+ 7b813bf15120fbc8
+
+VPADDQ_128(reg)
+ before
+ 07121ecd88441b7d.d2cc3eca9347d80f.74876ac63afb7562.c67d2c86fa7c09a3
+ c501b4c64209aa2e.0719232dba0b82d5.6e1d4703bf5de53f.d97270f257c73303
+ 109cfa471afbe686.e2ede96f8809f947.077815d35567232e.66c997070e860c39
+ 462deabeada60932.41150c7a1a4df892.9ce5d1a297a56adb.474e1bb03bc55073
+ 5acd7ad9f991bada
+ after
+ 0000000000000000.0000000000000000.75955cd714c5086d.403c07f9664d3f3c
+ c501b4c64209aa2e.0719232dba0b82d5.6e1d4703bf5de53f.d97270f257c73303
+ 109cfa471afbe686.e2ede96f8809f947.077815d35567232e.66c997070e860c39
+ 462deabeada60932.41150c7a1a4df892.9ce5d1a297a56adb.474e1bb03bc55073
+ 5acd7ad9f991bada
+VPADDQ_128(mem)
+ before
+ 79112f6f64f5079c.c201829797974fdd.fe5d063c8be33ce1.89ad76dc21a1f8f1
+ 82e7b65c99fdf3e5.df63bd3c7359f634.f791559ff8d88161.2a1f00ed91e9071d
+ 4f1c8c8db3b639e1.fba1981add7938e3.067d74917c37833e.db866b418009d40a
+ be7a2cefcf2b96bb.70050d9d72825295.09eddffd330cfda3.f82db3448c8c9a65
+ de62d56351fe96da
+ after
+ 79112f6f64f5079c.c201829797974fdd.fe5d063c8be33ce1.89ad76dc21a1f8f1
+ 82e7b65c99fdf3e5.df63bd3c7359f634.f791559ff8d88161.2a1f00ed91e9071d
+ 0000000000000000.0000000000000000.f5ee5bdc84bbbe42.b3cc77c9b38b000e
+ be7a2cefcf2b96bb.70050d9d72825295.09eddffd330cfda3.f82db3448c8c9a65
+ de62d56351fe96da
+
+VPADDQ_128(reg)
+ before
+ e76fcc086aeb0414.a9cd126c0869c6a0.9cdd1a32cd007ff7.daac12cf3a64acbd
+ 6fa194a173e020c0.ede3baf27b7b85bb.d973ba438b80fdb5.56878af3ad4a4cb8
+ d444299809682589.6787a06c436d8e39.8514e93e478d067a.5a4ac156a6cb98bf
+ 71a4885bc70f501c.f18441c67d4b9e45.fa0ba48e9db3d6f2.c0c135e244f24dfe
+ 65b86284a1cb27a3
+ after
+ 0000000000000000.0000000000000000.5e88a381d30e042f.b0d24c4a5415e577
+ 6fa194a173e020c0.ede3baf27b7b85bb.d973ba438b80fdb5.56878af3ad4a4cb8
+ d444299809682589.6787a06c436d8e39.8514e93e478d067a.5a4ac156a6cb98bf
+ 71a4885bc70f501c.f18441c67d4b9e45.fa0ba48e9db3d6f2.c0c135e244f24dfe
+ 65b86284a1cb27a3
+VPADDQ_128(mem)
+ before
+ 26fbc229d962e2d7.a20cab554a62dd24.68a718ec4422710c.95a6e59e2a7fabcb
+ dd55d3bb09c439c9.c3ca90f22dec084f.a9bca1cab4fdc2ba.b330aadc8a7cbfaf
+ 67940f284cfce9a3.3028339e0d3a0c46.8e8f584ceae94e7a.aef4eeb358364f4a
+ a082f55bbf17ae91.45738ec585d726b8.f4ecb95e02f1d179.e33fad8f313a9649
+ af5de4ddb013d258
+ after
+ 26fbc229d962e2d7.a20cab554a62dd24.68a718ec4422710c.95a6e59e2a7fabcb
+ dd55d3bb09c439c9.c3ca90f22dec084f.a9bca1cab4fdc2ba.b330aadc8a7cbfaf
+ 0000000000000000.0000000000000000.1263bab6f92033c6.48d7907ab4fc6b7a
+ a082f55bbf17ae91.45738ec585d726b8.f4ecb95e02f1d179.e33fad8f313a9649
+ af5de4ddb013d258
+
+VPINSRQ_128(reg)
+ before
+ 6c9a8e07714d3d22.64ecfe407d2043c1.5df79fd3324f914f.b79f41ec172107e2
+ 7742a77a11751354.8f9ea7c3a323665c.d6006035af2e8bb7.b3736be34585abe2
+ 2ca02ba32b169299.fd646dd04c2dd191.0bd9cf5599014e9d.c435b32da92a7aa5
+ e70216ec5cbcf49e.8a09cb539549408a.57d0e8a18b5417ad.c6b295b85f1c3056
+ 95b48e6f81658922
+ after
+ 0000000000000000.0000000000000000.d6006035af2e8bb7.95b48e6f81658922
+ 7742a77a11751354.8f9ea7c3a323665c.d6006035af2e8bb7.b3736be34585abe2
+ 2ca02ba32b169299.fd646dd04c2dd191.0bd9cf5599014e9d.c435b32da92a7aa5
+ e70216ec5cbcf49e.8a09cb539549408a.57d0e8a18b5417ad.c6b295b85f1c3056
+ 95b48e6f81658922
+VPINSRQ_128(mem)
+ before
+ 0d07193d2e134034.05b265c33ff4760f.125b3d3899837173.182fa58322b12192
+ 0a79b210803112b9.e0fd139371495497.7124406c74e81e7a.a9430469f9a6aaf9
+ 68d5d5d393ccbadd.d52f1cc78e47c9e3.83314ed9438203c8.655800beacbeec8e
+ 03e6fe7283eff6cb.40947ccd307b129e.244ee56d2260de8c.aaba95edd88623fc
+ d2b5bf6419898df0
+ after
+ 0d07193d2e134034.05b265c33ff4760f.125b3d3899837173.182fa58322b12192
+ 0a79b210803112b9.e0fd139371495497.7124406c74e81e7a.a9430469f9a6aaf9
+ 0000000000000000.0000000000000000.182fa58322b12192.a9430469f9a6aaf9
+ 03e6fe7283eff6cb.40947ccd307b129e.244ee56d2260de8c.aaba95edd88623fc
+ d2b5bf6419898df0
+
+VPINSRQ_128(reg)
+ before
+ 3b947b8f0a536415.b779aada6ea680b0.7d772f10f5706b75.304780122c8b69f0
+ 3fa5c4d84771e518.605a54f56dfe15b7.e82632fc79b30f14.83e79bb67d116120
+ 3b3296ac6d6e4ba4.d95578b09e02700d.ddeb80fe57ce3c26.f9fcb34432fe8249
+ 8c88ed7717d6d466.003692f81dbe4ede.b71315802c502c58.6d5043a8665c8797
+ bdb0c6ce36392d36
+ after
+ 0000000000000000.0000000000000000.e82632fc79b30f14.bdb0c6ce36392d36
+ 3fa5c4d84771e518.605a54f56dfe15b7.e82632fc79b30f14.83e79bb67d116120
+ 3b3296ac6d6e4ba4.d95578b09e02700d.ddeb80fe57ce3c26.f9fcb34432fe8249
+ 8c88ed7717d6d466.003692f81dbe4ede.b71315802c502c58.6d5043a8665c8797
+ bdb0c6ce36392d36
+VPINSRQ_128(mem)
+ before
+ c4e8bba2bda13050.8cf3c5a6e236ba0a.b0c81fb7053f6b55.d4eaedef93c21b55
+ 5dc49b10189f4c14.98bf1ba36919393b.c4d999db7390839e.8fbc05b829b247ca
+ 6610e404623f3cac.0d37eadc490b8fa6.1a337e4f82bd51e7.44d5584589abea63
+ ba97106bb88dbd45.45a92ebc1d99f6f6.8da34afe4ed3935a.4f80e2044f3a41cb
+ 0b0b9f6018e987ae
+ after
+ c4e8bba2bda13050.8cf3c5a6e236ba0a.b0c81fb7053f6b55.d4eaedef93c21b55
+ 5dc49b10189f4c14.98bf1ba36919393b.c4d999db7390839e.8fbc05b829b247ca
+ 0000000000000000.0000000000000000.d4eaedef93c21b55.8fbc05b829b247ca
+ ba97106bb88dbd45.45a92ebc1d99f6f6.8da34afe4ed3935a.4f80e2044f3a41cb
+ 0b0b9f6018e987ae
+
+VPINSRQ_128(reg)
+ before
+ d6c08bc57f47f9ba.34279d2f35968b0a.9d5fe4af824eabd8.f8f577d6f4dd0223
+ 0beca39f21ddd399.b28a073ef6656128.71a6062013b6eaf8.39f583c290e85d6f
+ 05dbe25a9a3951f7.0e8dc8821606fcca.1eca927d6d5eee01.2a6fe8ae3cfe5e6a
+ 22d9446284e6ae81.26fc5ee9b286181e.fe1783322bd1f4a0.a92e2587172ec23f
+ 90ffb3373b81451b
+ after
+ 0000000000000000.0000000000000000.71a6062013b6eaf8.90ffb3373b81451b
+ 0beca39f21ddd399.b28a073ef6656128.71a6062013b6eaf8.39f583c290e85d6f
+ 05dbe25a9a3951f7.0e8dc8821606fcca.1eca927d6d5eee01.2a6fe8ae3cfe5e6a
+ 22d9446284e6ae81.26fc5ee9b286181e.fe1783322bd1f4a0.a92e2587172ec23f
+ 90ffb3373b81451b
+VPINSRQ_128(mem)
+ before
+ bdaf0fabc405a22a.bd31c5237e7128e3.d4a3445ee5f0714d.6ed9d5a9ea9b3880
+ 0a08b6d0cfc59797.3131620a2265f8c8.f64df6cdcb51c286.ca5b844f4549f54e
+ 55d7239077cddd8e.dc2316810c4e5ddd.66c8f02281b3c8f2.6eeb8d90d86668b6
+ 78e7d2d9d92a333d.1854ddf6d8b991ce.01deaf4923243fc0.b6d3ebd9407ecd63
+ fe609a94181e6002
+ after
+ bdaf0fabc405a22a.bd31c5237e7128e3.d4a3445ee5f0714d.6ed9d5a9ea9b3880
+ 0a08b6d0cfc59797.3131620a2265f8c8.f64df6cdcb51c286.ca5b844f4549f54e
+ 0000000000000000.0000000000000000.6ed9d5a9ea9b3880.ca5b844f4549f54e
+ 78e7d2d9d92a333d.1854ddf6d8b991ce.01deaf4923243fc0.b6d3ebd9407ecd63
+ fe609a94181e6002
+
+VUCOMISS_128(reg)
+ before
+ a2de962ffdd15c3e.50063f9610e753cd.4210b3d32431d146.a45cad2eccb0e21a
+ fe98dc158b24fec4.bafee7b33811fa6d.b7a39486894259f1.290e68be98626e2d
+ 6ddc67b25da28240.909c451c6eb3e447.d1587d7aa579647d.6dc05be3a4469f24
+ 4df433720fd7245d.afacd5bdced9cd88.ee7d691b14613094.4d3d038a0b69312c
+ a353dba0ead5df70
+ after
+ a2de962ffdd15c3e.50063f9610e753cd.4210b3d32431d146.a45cad2eccb0e21a
+ fe98dc158b24fec4.bafee7b33811fa6d.b7a39486894259f1.290e68be98626e2d
+ 6ddc67b25da28240.909c451c6eb3e447.d1587d7aa579647d.6dc05be3a4469f24
+ 4df433720fd7245d.afacd5bdced9cd88.ee7d691b14613094.4d3d038a0b69312c
+ 0000000000000000
+VUCOMISS_128(mem)
+ before
+ 4ccc5e105c99661d.f92e3cc13e4f1fc8.f3fa1382738f705b.685c54d57186f6e2
+ 24750ac67ebe825f.cdd47e0b8597b02c.38527c577ae28aed.9c423a145875f514
+ 071b5bad6b52ee61.2533f6bc813a1336.5b808a28feded669.e77b184466b967d6
+ d187cbb340606850.5c979f40cdc58392.364fbbe21b8d12fc.a353e8d137de89d3
+ 2d16a827667197b8
+ after
+ 4ccc5e105c99661d.f92e3cc13e4f1fc8.f3fa1382738f705b.685c54d57186f6e2
+ 24750ac67ebe825f.cdd47e0b8597b02c.38527c577ae28aed.9c423a145875f514
+ 071b5bad6b52ee61.2533f6bc813a1336.5b808a28feded669.e77b184466b967d6
+ d187cbb340606850.5c979f40cdc58392.364fbbe21b8d12fc.a353e8d137de89d3
+ 0000000000000001
+
+VUCOMISS_128(reg)
+ before
+ e11053b38ffdcd30.5e88d8c318f5aa57.d04b750405c33deb.a68d8a6feefdf8d2
+ 1b8ce6e04f0e66e8.8ae9fdca101c70a3.dc9d7472c7c07dee.870474bd92394516
+ 37d75b1941319f8c.3175b6b243e17860.dbd798f8ac487f46.b581f3b7244eb4f5
+ 913db0cc02f1b3c7.2ff97f68cd517cb9.2b46de0152e87ea0.0ccf8549bf47029a
+ 68bca55e8030eb32
+ after
+ e11053b38ffdcd30.5e88d8c318f5aa57.d04b750405c33deb.a68d8a6feefdf8d2
+ 1b8ce6e04f0e66e8.8ae9fdca101c70a3.dc9d7472c7c07dee.870474bd92394516
+ 37d75b1941319f8c.3175b6b243e17860.dbd798f8ac487f46.b581f3b7244eb4f5
+ 913db0cc02f1b3c7.2ff97f68cd517cb9.2b46de0152e87ea0.0ccf8549bf47029a
+ 0000000000000001
+VUCOMISS_128(mem)
+ before
+ a513cfe482162be8.850ae0642ddae046.6041d5d9cb7738db.263641f8552cb7a7
+ 9e9f80c6e2047dea.6f8ae74d5f7960b4.a01933ef595f6af1.2af3bd4b509e6608
+ 312d32f1bb069e61.ab09c2f3335970be.cb4d15989216cc28.91c94f65dfccc66f
+ 3989634f2a294a7c.95d26cc246074b10.bda9f7bf92a71bac.b903f1b29f411487
+ fcefa19f2c8a8cfd
+ after
+ a513cfe482162be8.850ae0642ddae046.6041d5d9cb7738db.263641f8552cb7a7
+ 9e9f80c6e2047dea.6f8ae74d5f7960b4.a01933ef595f6af1.2af3bd4b509e6608
+ 312d32f1bb069e61.ab09c2f3335970be.cb4d15989216cc28.91c94f65dfccc66f
+ 3989634f2a294a7c.95d26cc246074b10.bda9f7bf92a71bac.b903f1b29f411487
+ 0000000000000001
+
+VUCOMISS_128(reg)
+ before
+ b8d75a9620326a7d.927f8ecd4a783d65.8932e026330d2e55.52f8564f761e13a8
+ 470818041ac5e9b2.18db305838ff3248.e3761d8b97fa553a.6508ac365a886f48
+ 06ced856b4d04648.a668c3da0fcbe652.ffe81c5e0d57fc6a.d4a3775f58f0ecba
+ 527594f68adebded.1af4c541ebe715af.39d4db0931b25e92.7a9632b68f624628
+ 32ad5a2818eb39be
+ after
+ b8d75a9620326a7d.927f8ecd4a783d65.8932e026330d2e55.52f8564f761e13a8
+ 470818041ac5e9b2.18db305838ff3248.e3761d8b97fa553a.6508ac365a886f48
+ 06ced856b4d04648.a668c3da0fcbe652.ffe81c5e0d57fc6a.d4a3775f58f0ecba
+ 527594f68adebded.1af4c541ebe715af.39d4db0931b25e92.7a9632b68f624628
+ 0000000000000000
+VUCOMISS_128(mem)
+ before
+ dab3699f129680a9.85484a52397b894a.4f49b178e95f7a8a.ed8854faa096b85e
+ 4d76dd08966fd815.fc95f5d55c34e70e.2034036b2540d210.764f859cf68f4679
+ 66c03150c383fd2d.13a692ea909413e3.6b813705ba95d96d.32746a5ace2a448f
+ 035ee161b2ddaa1e.27c81bff70274976.0afcca34c46a4acc.7c44fda2c4f3ed4e
+ b00b3cdf75747e60
+ after
+ dab3699f129680a9.85484a52397b894a.4f49b178e95f7a8a.ed8854faa096b85e
+ 4d76dd08966fd815.fc95f5d55c34e70e.2034036b2540d210.764f859cf68f4679
+ 66c03150c383fd2d.13a692ea909413e3.6b813705ba95d96d.32746a5ace2a448f
+ 035ee161b2ddaa1e.27c81bff70274976.0afcca34c46a4acc.7c44fda2c4f3ed4e
+ 0000000000000001
+
+VUCOMISD_128(reg)
+ before
+ 2915227d7d3b3371.fe1c6a2981899c14.92478e7f987ac472.db7137e460cce35a
+ 45aeabe876d3472e.35c647934c948f3a.b16fe6d6a518c184.b9abfaffa9c65e42
+ 5e21d38dffc9f743.8228f38b2e093fbc.e08c1f71338e7c57.7f778f72bc6577b1
+ d2bc96d6b1a87f5b.c30eedfc43f567c8.7be936badd663098.0aa27329b5b3ecd2
+ 37f62011aebf77d2
+ after
+ 2915227d7d3b3371.fe1c6a2981899c14.92478e7f987ac472.db7137e460cce35a
+ 45aeabe876d3472e.35c647934c948f3a.b16fe6d6a518c184.b9abfaffa9c65e42
+ 5e21d38dffc9f743.8228f38b2e093fbc.e08c1f71338e7c57.7f778f72bc6577b1
+ d2bc96d6b1a87f5b.c30eedfc43f567c8.7be936badd663098.0aa27329b5b3ecd2
+ 0000000000000001
+VUCOMISD_128(mem)
+ before
+ e0401415c692d5dd.fbc9f1302bfc1b23.d243aed4a862c488.ded3251e3f2e1bf3
+ e34bca20163ac21e.3795df0806520647.8d94b3ff795f1228.6597ea0af6727713
+ 1ae5bf20bcc2f9c2.e06c5cc8e1357d72.cece7967d1f50cd5.6c7f80e89ebd80a5
+ 62d86d00d43737f5.549a65de5531bc50.72bb7bf9cc326fbb.4fd7e326d29b7454
+ 6aed102f2e988dcd
+ after
+ e0401415c692d5dd.fbc9f1302bfc1b23.d243aed4a862c488.ded3251e3f2e1bf3
+ e34bca20163ac21e.3795df0806520647.8d94b3ff795f1228.6597ea0af6727713
+ 1ae5bf20bcc2f9c2.e06c5cc8e1357d72.cece7967d1f50cd5.6c7f80e89ebd80a5
+ 62d86d00d43737f5.549a65de5531bc50.72bb7bf9cc326fbb.4fd7e326d29b7454
+ 0000000000000000
+
+VUCOMISD_128(reg)
+ before
+ 190c026f4f4108bb.97f152ac79a338e2.ed6bf4b500d2fe8f.552735a28721f705
+ b87fb552d02120cc.96fce910c815b7b5.082a07b97ea580d9.54e0244c1dcf60e0
+ a29325444ec512a9.39c5af18dc96719b.022499566a367eda.49b0c2e5ab476577
+ 35954eb164b81a01.5d181eb0d13422c0.35a6a7f8600f343f.11658d574d95c3f7
+ 88c900901dc5368c
+ after
+ 190c026f4f4108bb.97f152ac79a338e2.ed6bf4b500d2fe8f.552735a28721f705
+ b87fb552d02120cc.96fce910c815b7b5.082a07b97ea580d9.54e0244c1dcf60e0
+ a29325444ec512a9.39c5af18dc96719b.022499566a367eda.49b0c2e5ab476577
+ 35954eb164b81a01.5d181eb0d13422c0.35a6a7f8600f343f.11658d574d95c3f7
+ 0000000000000000
+VUCOMISD_128(mem)
+ before
+ 8aa9987b39e47961.cccf2d05af86747e.dec1b4c5c4fa8650.fefa2b0bfdbeddb4
+ f3d1cf04bdfd4aa3.c38dbdaccabb5bcc.988bec41d1f55876.ba6d23fbddcfb6e4
+ 9f0d2317c41d637d.751dfa1352e40c98.674442111330555e.c34a8a359bcdfb7c
+ 6a280fa06b4f801c.40c9e0a4e28cc38e.27b63222a6b73935.76df5c23d344e727
+ 2f76953322c0b892
+ after
+ 8aa9987b39e47961.cccf2d05af86747e.dec1b4c5c4fa8650.fefa2b0bfdbeddb4
+ f3d1cf04bdfd4aa3.c38dbdaccabb5bcc.988bec41d1f55876.ba6d23fbddcfb6e4
+ 9f0d2317c41d637d.751dfa1352e40c98.674442111330555e.c34a8a359bcdfb7c
+ 6a280fa06b4f801c.40c9e0a4e28cc38e.27b63222a6b73935.76df5c23d344e727
+ 0000000000000000
+
+VUCOMISD_128(reg)
+ before
+ 4a5c32cf23cea869.30f00f8bcd9f5fac.7fdf6bcd1740bc59.b4ae395fa797c027
+ 23de2e6573f9f357.cd2f9fc5071aba58.8da998f88c8b32a6.eaf8d1b431daa560
+ 16458560adcdd709.1db23c3834cb4d4d.c8746293ddf96221.a55f780d618fa50b
+ 7fe0332c6ed78e2a.fc4561d270bed6b6.8a8cc509a7178875.c1b1aa5552bf7b54
+ 1ab8e17b2178e568
+ after
+ 4a5c32cf23cea869.30f00f8bcd9f5fac.7fdf6bcd1740bc59.b4ae395fa797c027
+ 23de2e6573f9f357.cd2f9fc5071aba58.8da998f88c8b32a6.eaf8d1b431daa560
+ 16458560adcdd709.1db23c3834cb4d4d.c8746293ddf96221.a55f780d618fa50b
+ 7fe0332c6ed78e2a.fc4561d270bed6b6.8a8cc509a7178875.c1b1aa5552bf7b54
+ 0000000000000001
+VUCOMISD_128(mem)
+ before
+ 8c419b68e9c69d73.bafa353551a25467.46b48a7dd8000fc0.313cbec68670df4e
+ f3185309c7b360a0.23de85e7f3ba676c.d7ca3327879cb597.17d247361590a45a
+ 2a09854ad64de91c.16da21aeefac01e4.8b55d9bb9a9e8466.9a985ec5f0031343
+ 0fe0ad1832a0f513.ef3804f7e2035f7c.3d1ff6252d13375a.14dcfee0b45668b5
+ e2e823f1fc15de5d
+ after
+ 8c419b68e9c69d73.bafa353551a25467.46b48a7dd8000fc0.313cbec68670df4e
+ f3185309c7b360a0.23de85e7f3ba676c.d7ca3327879cb597.17d247361590a45a
+ 2a09854ad64de91c.16da21aeefac01e4.8b55d9bb9a9e8466.9a985ec5f0031343
+ 0fe0ad1832a0f513.ef3804f7e2035f7c.3d1ff6252d13375a.14dcfee0b45668b5
+ 0000000000000001
+
+VCVTPS2PD_128(reg)
+ before
+ 6109ca6565cab2e7.7d69475df9b640b0.0a452b2c674cbddf.cbf508515b068b9e
+ eb8aeda98a0320fe.506fd007449d8620.c34d90bb1a1256ba.10a38a2b40833c5f
+ ddb98a28084c634f.63bfc3013161828e.759b310e98e167b9.e8f5f99ff99706c8
+ 94e09c4d7a2fb985.94259c37dc0df227.7e7d09937d452c87.2eb7cf99a14da407
+ c0b48a0655b1d345
+ after
+ 6109ca6565cab2e7.7d69475df9b640b0.0a452b2c674cbddf.cbf508515b068b9e
+ 0000000000000000.0000000000000000.c51ebf33e0000000.c732e0d900000000
+ ddb98a28084c634f.63bfc3013161828e.759b310e98e167b9.e8f5f99ff99706c8
+ 94e09c4d7a2fb985.94259c37dc0df227.7e7d09937d452c87.2eb7cf99a14da407
+ c0b48a0655b1d345
+VCVTPS2PD_128(mem)
+ before
+ 78baa5d030d04fb1.6a4d20867d3a5b4d.bd6dd8955fad8f17.393d14b564cbe1d0
+ 34939ce54eb5d374.bc4a103eacf98853.bc63f107d94d1889.02284fdfe9fec142
+ ce0cec2fcc6d1cbd.e6246ae1a4f77a42.6cd3657964fa47a9.348ab47fa96b0987
+ 24f10f9cc602e6b6.442729db00c06ec7.a888afd71cbfd9a5.2daf41013f9df44b
+ 48e3f1cf4820c03b
+ after
+ 78baa5d030d04fb1.6a4d20867d3a5b4d.bd6dd8955fad8f17.393d14b564cbe1d0
+ 0000000000000000.0000000000000000.3f27a296a0000000.44997c3a00000000
+ ce0cec2fcc6d1cbd.e6246ae1a4f77a42.6cd3657964fa47a9.348ab47fa96b0987
+ 24f10f9cc602e6b6.442729db00c06ec7.a888afd71cbfd9a5.2daf41013f9df44b
+ 48e3f1cf4820c03b
+
+VCVTPS2PD_128(reg)
+ before
+ e072c1566081a703.100e83175782ed8c.329e49985ce0a08d.4e504c0d1ea88aa7
+ 53a7ab02214be64e.702ec38c9cf9ec6a.0cd7c78555e44c41.38f5b60885c215db
+ fbcfad402a0ab8c9.1e1f4ce7b072a07d.2e1c9d0c8757ad8f.43446bb26e18386e
+ 3637c27a144a5b20.f8ab9814aff9c5f0.f4bac99b8dc50022.4c09e6f9f4b7ac8c
+ 2d0fa3c734a93060
+ after
+ e072c1566081a703.100e83175782ed8c.329e49985ce0a08d.4e504c0d1ea88aa7
+ 0000000000000000.0000000000000000.40688d7640000000.45c3070dc0000000
+ fbcfad402a0ab8c9.1e1f4ce7b072a07d.2e1c9d0c8757ad8f.43446bb26e18386e
+ 3637c27a144a5b20.f8ab9814aff9c5f0.f4bac99b8dc50022.4c09e6f9f4b7ac8c
+ 2d0fa3c734a93060
+VCVTPS2PD_128(mem)
+ before
+ c3241e0a49fd7e17.5e28e61e7d9809fe.d89f25ffb69a16f0.bafd469c03bb81a7
+ eb12d4ad50bc53dc.d1f115970180fe0f.9bc76e95e06250a9.dc31117d86c46bc9
+ 7fa6409c64f46bdc.e9dd4c503b8c7801.1defefc04a5c2f46.b6a224a9b26dfb35
+ 5caddec3a1b08243.033786b7c84ab17d.3be2256e10956ff4.a49c7d8b21406d97
+ 026a179172ccfc9a
+ after
+ c3241e0a49fd7e17.5e28e61e7d9809fe.d89f25ffb69a16f0.bafd469c03bb81a7
+ 0000000000000000.0000000000000000.bf5fa8d380000000.38777034e0000000
+ 7fa6409c64f46bdc.e9dd4c503b8c7801.1defefc04a5c2f46.b6a224a9b26dfb35
+ 5caddec3a1b08243.033786b7c84ab17d.3be2256e10956ff4.a49c7d8b21406d97
+ 026a179172ccfc9a
+
+VCVTPS2PD_128(reg)
+ before
+ 2c59ee263f9ae6eb.5ef02a0e24fd533c.7c4dbf374346e632.cf6e8a894c18cbde
+ 7db5feb724386535.623ea06909e69bf4.ae69f33c480a53ca.b65d9cff1df10031
+ 53ca44aebd31b525.4262bdc16b771596.f6d81f33742433f2.cc7dd6bb9c2cca19
+ 09e4bb78a8121467.db27fc0066bc7f4f.b0e63d866320c355.ed98b4a9e8d6e4c1
+ f57ab3b51afb0c56
+ after
+ 2c59ee263f9ae6eb.5ef02a0e24fd533c.7c4dbf374346e632.cf6e8a894c18cbde
+ 0000000000000000.0000000000000000.c18fbad760000000.bb85994320000000
+ 53ca44aebd31b525.4262bdc16b771596.f6d81f33742433f2.cc7dd6bb9c2cca19
+ 09e4bb78a8121467.db27fc0066bc7f4f.b0e63d866320c355.ed98b4a9e8d6e4c1
+ f57ab3b51afb0c56
+VCVTPS2PD_128(mem)
+ before
+ c0f14ecb50a5fc04.fb4f5f827e66bca6.095bd91417c2934b.39df4ba2b0883fa0
+ 2ac801d7a6e270f6.84562c36ddb9ea8e.a8c8d0e79a950eb5.eb0e45f4f7eae27e
+ 0fca48c537bd2658.02471f026197d9cd.943b5e67093fabba.23c025e6d5d2e99c
+ 4bc49f812043d857.cf6c3250a58dc60d.a980fe7f83ce2785.3d42e9e6e5cb90a6
+ 95de8b5fc4611347
+ after
+ c0f14ecb50a5fc04.fb4f5f827e66bca6.095bd91417c2934b.39df4ba2b0883fa0
+ 0000000000000000.0000000000000000.3f3be97440000000.be1107f400000000
+ 0fca48c537bd2658.02471f026197d9cd.943b5e67093fabba.23c025e6d5d2e99c
+ 4bc49f812043d857.cf6c3250a58dc60d.a980fe7f83ce2785.3d42e9e6e5cb90a6
+ 95de8b5fc4611347
+
+VANDNPD_128(reg)
+ before
+ 87e109bc0d20ad2c.ba8283f87c7f421f.4912638e4626edfa.c3622c1b224d3e43
+ 6f975f6b5d959b00.38d06f14677d22db.cb85ad27dfef8a41.beaf642702c9ac20
+ a94b87d74f4b1970.a17adfc3fe4a32b8.b0100d870c73d98e.7631228f404d2c47
+ 914b7f6c80ce6328.d14c4ff05df12fe2.56017d1a6a3e158c.c6b5e33ff7e57be5
+ 8c072223439e5525
+ after
+ 0000000000000000.0000000000000000.301000800010518e.4010028840040047
+ 6f975f6b5d959b00.38d06f14677d22db.cb85ad27dfef8a41.beaf642702c9ac20
+ a94b87d74f4b1970.a17adfc3fe4a32b8.b0100d870c73d98e.7631228f404d2c47
+ 914b7f6c80ce6328.d14c4ff05df12fe2.56017d1a6a3e158c.c6b5e33ff7e57be5
+ 8c072223439e5525
+VANDNPD_128(mem)
+ before
+ a3f35b2742837634.83e142978babb4d3.a4113b879f7ed584.17a2fb4c94dd7be8
+ e7450a380da0993e.db5accc20d6d491e.f5972073e0fedfcb.5040828927db464e
+ 33c9ac40c2027b6e.f502195aa1a15db4.a2a879a23d7c0ae2.5e270e3ebfc4b369
+ 654abc2d7db4d8f1.2c2526cce3d22e42.8611c200d10412f6.9ba39cd5f625fee5
+ 640027bc6b896370
+ after
+ a3f35b2742837634.83e142978babb4d3.a4113b879f7ed584.17a2fb4c94dd7be8
+ e7450a380da0993e.db5accc20d6d491e.f5972073e0fedfcb.5040828927db464e
+ 0000000000000000.0000000000000000.00001b841f000004.07a27944900439a0
+ 654abc2d7db4d8f1.2c2526cce3d22e42.8611c200d10412f6.9ba39cd5f625fee5
+ 640027bc6b896370
+
+VANDNPD_128(reg)
+ before
+ 168aaa5db77c1eb3.5895b6ea59c26bf2.de0fee83708cf673.7d9e7877b9a3b333
+ 0b8c2426798b6a5d.e77616637239f19e.660b6deae45bf2f5.621a15f41064a8c4
+ a0538e824a418418.f0b95884e5242620.20669f6fdacc5d71.13531763f353aed5
+ 312ce5ddc92aa790.4e2af939ce90c5a5.676d807dee6a7596.6a13f9b17d7d8194
+ 452737c8cbeddc2b
+ after
+ 0000000000000000.0000000000000000.006492051a840d00.11410203e3130611
+ 0b8c2426798b6a5d.e77616637239f19e.660b6deae45bf2f5.621a15f41064a8c4
+ a0538e824a418418.f0b95884e5242620.20669f6fdacc5d71.13531763f353aed5
+ 312ce5ddc92aa790.4e2af939ce90c5a5.676d807dee6a7596.6a13f9b17d7d8194
+ 452737c8cbeddc2b
+VANDNPD_128(mem)
+ before
+ 7f5b4e96f8b07cc6.1a6126a38fd31173.dc95746e47878c59.996a0d80bdc2740e
+ f37bb80620d01d92.b83e4c403ac7fc6a.78c5450f6f173567.11aa41e4e25f9685
+ 7e53f304605c7bbb.651153206692a424.fc88e808604c7cfc.2a781815facd19a8
+ fdaf7a7cd45d516c.7e2538b0aec1474b.46a8d94636311f44.42228e7fa1993723
+ b3f2a08f714e2da1
+ after
+ 7f5b4e96f8b07cc6.1a6126a38fd31173.dc95746e47878c59.996a0d80bdc2740e
+ f37bb80620d01d92.b83e4c403ac7fc6a.78c5450f6f173567.11aa41e4e25f9685
+ 0000000000000000.0000000000000000.8410306000808818.88400c001d80600a
+ fdaf7a7cd45d516c.7e2538b0aec1474b.46a8d94636311f44.42228e7fa1993723
+ b3f2a08f714e2da1
+
+VANDNPD_128(reg)
+ before
+ db3648af097836cf.4a5aca5a97e15cd2.5fc5f55aaedf1f8b.30f295b30ed2d86a
+ 1438844d02a38f59.43215d8ac5f35818.643e888b03796992.9732973d033b649a
+ bc4550d3fa5c74ea.c2d1b1f87b9f006c.e9dcecb049196109.58335bce32797f02
+ 2da9a6af8d2f212e.a4344190d5f211f7.4aeb1e341b4e429f.4dc35e54b697e4cc
+ 53ac1abaaba25024
+ after
+ 0000000000000000.0000000000000000.89c0643048000009.480148c230401b00
+ 1438844d02a38f59.43215d8ac5f35818.643e888b03796992.9732973d033b649a
+ bc4550d3fa5c74ea.c2d1b1f87b9f006c.e9dcecb049196109.58335bce32797f02
+ 2da9a6af8d2f212e.a4344190d5f211f7.4aeb1e341b4e429f.4dc35e54b697e4cc
+ 53ac1abaaba25024
+VANDNPD_128(mem)
+ before
+ 47bb0dec2ea57f37.c5af844c56a6d2d3.c616893fedf747e7.e3b7188215a149fe
+ 03bdb2d65bac2c31.dea5e516f24fc282.024505efe2bb5e68.0f8bd808d4a0b2d2
+ 647b85644dc3143d.d5d5c579fcb62eea.358c328ece4911a6.2cb55931f3d6b9c8
+ 46c4038221f7f388.078c20e1106551b5.3bb68b07cdad1dcc.957f97690fcf998c
+ a6368e1cc3188fca
+ after
+ 47bb0dec2ea57f37.c5af844c56a6d2d3.c616893fedf747e7.e3b7188215a149fe
+ 03bdb2d65bac2c31.dea5e516f24fc282.024505efe2bb5e68.0f8bd808d4a0b2d2
+ 0000000000000000.0000000000000000.c41288100d440187.e03400820101492c
+ 46c4038221f7f388.078c20e1106551b5.3bb68b07cdad1dcc.957f97690fcf998c
+ a6368e1cc3188fca
+
+VORPD_128(reg)
+ before
+ bb263bb7ac3dd62d.8563a61df253853d.ce16f2bacbea6990.f0908c45fcf43e06
+ 2f9b99a465c8ac61.fd23ec1fdce48589.87bf3870c9d1b026.30e6b13676282f82
+ 60e0a4508b474b13.8ad25076fcb5b098.8ed3ed6fa5a46224.d78477c55858ae69
+ a9435828b945f0ef.083a4f0c6dd2c295.409d0d24fbf1bd35.c23659debd8d75ea
+ cbc7d36dc1d5402f
+ after
+ 0000000000000000.0000000000000000.8ffffd7fedf5f226.f7e6f7f77e78afeb
+ 2f9b99a465c8ac61.fd23ec1fdce48589.87bf3870c9d1b026.30e6b13676282f82
+ 60e0a4508b474b13.8ad25076fcb5b098.8ed3ed6fa5a46224.d78477c55858ae69
+ a9435828b945f0ef.083a4f0c6dd2c295.409d0d24fbf1bd35.c23659debd8d75ea
+ cbc7d36dc1d5402f
+VORPD_128(mem)
+ before
+ cf05615f813bcd64.650eb2968b4fd6a0.532863cf4c4877ad.f76b95fa6844fb06
+ a9ba7f9e19ccd6b6.f28eac089ff03bd3.47680aaab4228a0b.10877f5c87275943
+ 37b3aa17a4931751.aa0f44e98eb45934.c0c5bf89c26cb8dc.e73ec9b8f5291397
+ 54bc5db73e9c4e61.ebdd75a5f6276c6e.9a0dfe589133bc4c.d8dc6e794dd364af
+ 3fad6a0b2cb38936
+ after
+ cf05615f813bcd64.650eb2968b4fd6a0.532863cf4c4877ad.f76b95fa6844fb06
+ a9ba7f9e19ccd6b6.f28eac089ff03bd3.47680aaab4228a0b.10877f5c87275943
+ 0000000000000000.0000000000000000.57686beffc6affaf.f7effffeef67fb47
+ 54bc5db73e9c4e61.ebdd75a5f6276c6e.9a0dfe589133bc4c.d8dc6e794dd364af
+ 3fad6a0b2cb38936
+
+VORPD_128(reg)
+ before
+ 78fcbada2d54bed9.dca1146904f43511.0f443ca873d6b22d.b10a44033e825486
+ df175852ed423e44.ab2d4b1812a6898d.7490935e9f4d651f.e1890b76e4653ab7
+ d04842df070a4722.9d2e7eb283be0602.740c78331916c2ee.0656d19da0e92b0a
+ a7dc73ed18371320.8e6e2a227349679c.6d05e6937bbf0446.fc3d11658d19e2ac
+ 9e0a48b8c8011cc8
+ after
+ 0000000000000000.0000000000000000.749cfb7f9f5fe7ff.e7dfdbffe4ed3bbf
+ df175852ed423e44.ab2d4b1812a6898d.7490935e9f4d651f.e1890b76e4653ab7
+ d04842df070a4722.9d2e7eb283be0602.740c78331916c2ee.0656d19da0e92b0a
+ a7dc73ed18371320.8e6e2a227349679c.6d05e6937bbf0446.fc3d11658d19e2ac
+ 9e0a48b8c8011cc8
+VORPD_128(mem)
+ before
+ ca89f0846cae958b.bf1fe8e9bb56dee9.59baca54ff526986.b9c7d9eb61d469d4
+ 5b8587b3952b0921.765d9b3d8cf2e62a.dcdeda3442e5c8ed.b59e4ea568df2b44
+ 2ccb8833608433b6.27e28a572897658e.f2a6d6ae590f40fd.bed6402f2b6e8641
+ 1b276fefe9c6d174.2ef9b0a22bd197c3.76de3baf5fdb8ce1.2ebbabf3470db878
+ 62988b5f5746fb94
+ after
+ ca89f0846cae958b.bf1fe8e9bb56dee9.59baca54ff526986.b9c7d9eb61d469d4
+ 5b8587b3952b0921.765d9b3d8cf2e62a.dcdeda3442e5c8ed.b59e4ea568df2b44
+ 0000000000000000.0000000000000000.ddfeda74fff7e9ef.bddfdfef69df6bd4
+ 1b276fefe9c6d174.2ef9b0a22bd197c3.76de3baf5fdb8ce1.2ebbabf3470db878
+ 62988b5f5746fb94
+
+VORPD_128(reg)
+ before
+ b6badcdef8a78c42.0365b8d34bfc9c8a.e7f00989302dba72.46518421715669c6
+ 876d9bdcc5bca72e.bf51e0cba2325322.ad11927ad336084a.3ccd2df1aa8a93d7
+ 2ffdc2c55b0f8703.2db762c30b75b069.dea946e0b179bef5.361cb20c2785c541
+ 0bb64f05552e696e.2762baa7a1d0708a.d50420276581181f.0f0b8f5d0353bc2f
+ a26641cf5aff34ce
+ after
+ 0000000000000000.0000000000000000.ffb9d6faf37fbeff.3eddbffdaf8fd7d7
+ 876d9bdcc5bca72e.bf51e0cba2325322.ad11927ad336084a.3ccd2df1aa8a93d7
+ 2ffdc2c55b0f8703.2db762c30b75b069.dea946e0b179bef5.361cb20c2785c541
+ 0bb64f05552e696e.2762baa7a1d0708a.d50420276581181f.0f0b8f5d0353bc2f
+ a26641cf5aff34ce
+VORPD_128(mem)
+ before
+ ccf943504995e94a.77e43d084fa5891a.8b20646381504fb2.ed6e1ebb8cda5175
+ 6a8f11cbec2196ce.cfd2893ae6ff22b4.33bbdde4c7ff080c.84323c09c110a7a3
+ 56f6272c5eb0f887.6fce2e08b6c871e8.fc009f148dec59c5.f49e747ba1b05354
+ 6ef8025fbb4dcba1.b32227dc5a8cb261.c3bb28e1f220fb09.9bfcc47ec7469435
+ d399277fd05ca4f2
+ after
+ ccf943504995e94a.77e43d084fa5891a.8b20646381504fb2.ed6e1ebb8cda5175
+ 6a8f11cbec2196ce.cfd2893ae6ff22b4.33bbdde4c7ff080c.84323c09c110a7a3
+ 0000000000000000.0000000000000000.bbbbfde7c7ff4fbe.ed7e3ebbcddaf7f7
+ 6ef8025fbb4dcba1.b32227dc5a8cb261.c3bb28e1f220fb09.9bfcc47ec7469435
+ d399277fd05ca4f2
+
+VXORPD_128(reg)
+ before
+ fac199e95780c036.8c621d512005ca47.f71b72246ed821cc.62b7f4350fa9ad03
+ 6ac01727f93e24ad.8d00f4eca9e2b2a5.97050b4a8f37f9d4.b7c27dfe029229e0
+ 81e19ba751200b05.4e9e031d71f33fe9.ef2cecbc58357726.9ca64127e7e72ccc
+ 997223d4fcb4b3e7.a908c6d194412d3c.5bdb13e5665fd76e.ee30ba9cd9b572f2
+ 892d6649f507b77e
+ after
+ 0000000000000000.0000000000000000.7829e7f6d7028ef2.2b643cd9e575052c
+ 6ac01727f93e24ad.8d00f4eca9e2b2a5.97050b4a8f37f9d4.b7c27dfe029229e0
+ 81e19ba751200b05.4e9e031d71f33fe9.ef2cecbc58357726.9ca64127e7e72ccc
+ 997223d4fcb4b3e7.a908c6d194412d3c.5bdb13e5665fd76e.ee30ba9cd9b572f2
+ 892d6649f507b77e
+VXORPD_128(mem)
+ before
+ 4966c11a56eab69e.0fbdaa1a95855502.7b09baf22fda37cd.37607b3155405557
+ 0baa45fb18692c7b.3f0f2ce5b8203000.a06e5a6e5dc91ac6.de05200cbf652c8e
+ a9c470d95890d444.86b5a6a102107e8e.f40422303b1b9254.ae17ffe2435999be
+ 007fbd9e326c6c23.3ef813ba0fe17c57.53958e24e4db5aa2.02e2121f7aa8d894
+ 36b2573003de24bc
+ after
+ 4966c11a56eab69e.0fbdaa1a95855502.7b09baf22fda37cd.37607b3155405557
+ 0baa45fb18692c7b.3f0f2ce5b8203000.a06e5a6e5dc91ac6.de05200cbf652c8e
+ 0000000000000000.0000000000000000.db67e09c72132d0b.e9655b3dea2579d9
+ 007fbd9e326c6c23.3ef813ba0fe17c57.53958e24e4db5aa2.02e2121f7aa8d894
+ 36b2573003de24bc
+
+VXORPD_128(reg)
+ before
+ a5d2c97f7788bae1.eca9a838c108ae44.c4276f9d7a206608.9aed1b36751530dd
+ ad90647a7432d6af.490cad91217056d5.748db6b4df58784c.a3da435209d5ce30
+ a936258b9666b4d4.f37549976fb022ff.aa75e46ddb16edd0.4b278464bc28f0c8
+ f411072078b28ffa.c6b0f635c6d5ccf1.c32cf63309e40240.6e9f5a58ac1a54d1
+ e80f3f1bf2b5b476
+ after
+ 0000000000000000.0000000000000000.def852d9044e959c.e8fdc736b5fd3ef8
+ ad90647a7432d6af.490cad91217056d5.748db6b4df58784c.a3da435209d5ce30
+ a936258b9666b4d4.f37549976fb022ff.aa75e46ddb16edd0.4b278464bc28f0c8
+ f411072078b28ffa.c6b0f635c6d5ccf1.c32cf63309e40240.6e9f5a58ac1a54d1
+ e80f3f1bf2b5b476
+VXORPD_128(mem)
+ before
+ 9444b197ac07cce3.ec6d05a4b6a1a4cd.9e88325743eb11d5.19fee7710650f247
+ 50072abaf61c5a46.eb961e83edc02ffa.57cb79e901fcadd7.0937b3956de6fb92
+ f727286eebfe18c9.4fd84b29b99a6b2d.cd4345d71d165b24.ef23560adb3157cc
+ 656f27a1a7bbc398.727e8a02b5bb9511.dbbd140db245d8e8.270ecc3cebbd43a2
+ 0d4312973a16fac0
+ after
+ 9444b197ac07cce3.ec6d05a4b6a1a4cd.9e88325743eb11d5.19fee7710650f247
+ 50072abaf61c5a46.eb961e83edc02ffa.57cb79e901fcadd7.0937b3956de6fb92
+ 0000000000000000.0000000000000000.c9434bbe4217bc02.10c954e46bb609d5
+ 656f27a1a7bbc398.727e8a02b5bb9511.dbbd140db245d8e8.270ecc3cebbd43a2
+ 0d4312973a16fac0
+
+VXORPD_128(reg)
+ before
+ fd0f238763c9b9d1.76aaa13e475e17e0.b2d6d57a7db0e953.5f056177dd93e04f
+ 52bffb790361bc82.06a61431e6f4cfcd.692a2afdae04a39e.34e7a802b90e2f84
+ 6a9d96d7b56b3f7e.f02dfb66a188a88b.f4c785f8e443fea0.362f659862c280b3
+ a0f5f10f15717d72.120cd2c993275e44.b0f9e0d5b9fa3702.41a91527f6b99009
+ 302032998e011bb2
+ after
+ 0000000000000000.0000000000000000.9dedaf054a475d3e.02c8cd9adbccaf37
+ 52bffb790361bc82.06a61431e6f4cfcd.692a2afdae04a39e.34e7a802b90e2f84
+ 6a9d96d7b56b3f7e.f02dfb66a188a88b.f4c785f8e443fea0.362f659862c280b3
+ a0f5f10f15717d72.120cd2c993275e44.b0f9e0d5b9fa3702.41a91527f6b99009
+ 302032998e011bb2
+VXORPD_128(mem)
+ before
+ e1613adc48a6dcd9.5015078bc002b309.470f1546d9dbad27.f70c3901ccb48a72
+ 2f38a8db40b290ab.d648d4b952a71df1.6a0141c98eb2505e.264b8be9b6fd329c
+ f571f9829134f354.8dd9540466eef7d3.59b0d13fcfb80416.9a04d2f816626c2c
+ 11d8a7bd5735c0ff.d31583d898627c5e.efe64192b7f7857a.ad810a9a856e74cd
+ bc0f303ba1ad862b
+ after
+ e1613adc48a6dcd9.5015078bc002b309.470f1546d9dbad27.f70c3901ccb48a72
+ 2f38a8db40b290ab.d648d4b952a71df1.6a0141c98eb2505e.264b8be9b6fd329c
+ 0000000000000000.0000000000000000.2d0e548f5769fd79.d147b2e87a49b8ee
+ 11d8a7bd5735c0ff.d31583d898627c5e.efe64192b7f7857a.ad810a9a856e74cd
+ bc0f303ba1ad862b
+
+VXORPS_128(reg)
+ before
+ 23fa3e4706acddf4.5d393078afc3b5d8.03485ea08590e93c.07700db0637e8eb7
+ 3e8e322a4ff6b6d1.b75f0f9fb4e98c0d.78bee0cbc8037a19.7f1bb183ee56dcf9
+ 6917085019174d71.f918c11e83b301c8.90c305c2fe476aa2.31b0aaf9758d2b6b
+ 00e0ba25ff9cdd7e.012ec0e2372ed235.a6a3c9f2c2e8f683.fbfe73fd132e3739
+ b7d0887be445bb91
+ after
+ 0000000000000000.0000000000000000.e87de509364410bb.4eab1b7a9bdbf792
+ 3e8e322a4ff6b6d1.b75f0f9fb4e98c0d.78bee0cbc8037a19.7f1bb183ee56dcf9
+ 6917085019174d71.f918c11e83b301c8.90c305c2fe476aa2.31b0aaf9758d2b6b
+ 00e0ba25ff9cdd7e.012ec0e2372ed235.a6a3c9f2c2e8f683.fbfe73fd132e3739
+ b7d0887be445bb91
+VXORPS_128(mem)
+ before
+ 42f1655f05df749c.5f3646169d10a4a4.a96e8ad5ed65b981.15a929c7b1735a67
+ 792f879592071e89.e266a78d90ffdc91.cea49ae5c06573d8.3b2220ae6674d2fb
+ 36546909a6ca7482.e5bad9f874f6c1ee.4d9b6cfdcd38bc65.725aaa117e7599eb
+ 562d87a75d3333b4.c47fd8c1e480916a.00217c082fed4f55.189dc35e9404ece2
+ 8737670045ac078c
+ after
+ 42f1655f05df749c.5f3646169d10a4a4.a96e8ad5ed65b981.15a929c7b1735a67
+ 792f879592071e89.e266a78d90ffdc91.cea49ae5c06573d8.3b2220ae6674d2fb
+ 0000000000000000.0000000000000000.67ca10302d00ca59.2e8b0969d707889c
+ 562d87a75d3333b4.c47fd8c1e480916a.00217c082fed4f55.189dc35e9404ece2
+ 8737670045ac078c
+
+VXORPS_128(reg)
+ before
+ 1c7493622cfa2597.b6855d5cd44e174a.db00a0567c2a86af.c40047f4038de9d3
+ 349f42f2e67983ac.302a67122627dc71.868b2e22d97fdd69.760648ac6426460c
+ 2906701b0eb55d7a.a1e722b770cb3d54.216a7d91960bd145.f0fdfb1c6ec3212c
+ 58f31949403befab.e5870936cd45f720.08eb890f505a9fef.0fb2dc303e71375e
+ aff067d5f03b44cf
+ after
+ 0000000000000000.0000000000000000.a7e153b34f740c2c.86fbb3b00ae56720
+ 349f42f2e67983ac.302a67122627dc71.868b2e22d97fdd69.760648ac6426460c
+ 2906701b0eb55d7a.a1e722b770cb3d54.216a7d91960bd145.f0fdfb1c6ec3212c
+ 58f31949403befab.e5870936cd45f720.08eb890f505a9fef.0fb2dc303e71375e
+ aff067d5f03b44cf
+VXORPS_128(mem)
+ before
+ ac8519f59f2d04ab.1eb33ae9199674ec.d8d7987a5aa2c601.96584f08a2f98312
+ e23b6d7d6753321d.d592cd65355229e8.56a34b7132ed6522.29fec9e82973b95b
+ 2de0df5a65ba8b51.dadbd02a2efc4a4c.3cb79f06723292b0.1c28f51c80557c76
+ 6a3eec76b56ecb74.89dc3ea5a31f12c3.64df0e25357e07d6.cb24ce0e442a090e
+ 913d502c107e9cd0
+ after
+ ac8519f59f2d04ab.1eb33ae9199674ec.d8d7987a5aa2c601.96584f08a2f98312
+ e23b6d7d6753321d.d592cd65355229e8.56a34b7132ed6522.29fec9e82973b95b
+ 0000000000000000.0000000000000000.8e74d30b684fa323.bfa686e08b8a3a49
+ 6a3eec76b56ecb74.89dc3ea5a31f12c3.64df0e25357e07d6.cb24ce0e442a090e
+ 913d502c107e9cd0
+
+VXORPS_128(reg)
+ before
+ ccbe78e080dd7167.73220ebf7179adb2.3edf14402e48bffa.abe616bb98dc80c1
+ d6f4419831d4c380.2458c320b8e9ef36.55324c696b018a9d.ed9a32b2b658bb9d
+ 0d2ba7bfbfefcfc7.5bab8685a4c94b2d.2a1fe48bf7d8b257.06c5dff7abfe7295
+ cbafa6c1c5b8d1e7.f3e9d3da51267dc3.19f3d7116d5971d5.d234977794db61d6
+ 2cb3d81c8dfb468b
+ after
+ 0000000000000000.0000000000000000.7f2da8e29cd938ca.eb5fed451da6c908
+ d6f4419831d4c380.2458c320b8e9ef36.55324c696b018a9d.ed9a32b2b658bb9d
+ 0d2ba7bfbfefcfc7.5bab8685a4c94b2d.2a1fe48bf7d8b257.06c5dff7abfe7295
+ cbafa6c1c5b8d1e7.f3e9d3da51267dc3.19f3d7116d5971d5.d234977794db61d6
+ 2cb3d81c8dfb468b
+VXORPS_128(mem)
+ before
+ f20e1dd4b168dbe1.6ecc3a09dfbd048c.c8dc260bdc0b4323.7ef922696a0f05c2
+ ff10e3891c30dd04.50cd6006aa89a564.b651fc046084577a.b57fbffe8986a7cb
+ 2f87a429eb5f081f.cfff1221c2a9f018.9914d0b1f99e76f3.1acfac3d674a969c
+ 5e3dde9f39ff175e.45af4ec7c2a82157.4df11effc5645bbb.0937e4909fe80ce0
+ de016364cdeb4644
+ after
+ f20e1dd4b168dbe1.6ecc3a09dfbd048c.c8dc260bdc0b4323.7ef922696a0f05c2
+ ff10e3891c30dd04.50cd6006aa89a564.b651fc046084577a.b57fbffe8986a7cb
+ 0000000000000000.0000000000000000.7e8dda0fbc8f1459.cb869d97e389a209
+ 5e3dde9f39ff175e.45af4ec7c2a82157.4df11effc5645bbb.0937e4909fe80ce0
+ de016364cdeb4644
+
+VMULSD_128(reg)
+ before
+ f57a25258fdf8073.67ff0cd7231ec7ef.10271064461273cb.adb462d8dde2c3fe
+ aaee27407e51f51a.2899aabdc5c8d4fc.8ab45265eb742321.9729192a5f256ae7
+ 59a8632038cce2e4.7cd7343d3907fab1.10a112344c596d04.e61bbedf67380ca3
+ 5df6d73059dd837e.3e8527449ee9f43b.ff3c4b3f064d8c21.7557cde51027645d
+ 22a9c22776ff3042
+ after
+ 0000000000000000.0000000000000000.8ab45265eb742321.3d55c2f06430bdc0
+ aaee27407e51f51a.2899aabdc5c8d4fc.8ab45265eb742321.9729192a5f256ae7
+ 59a8632038cce2e4.7cd7343d3907fab1.10a112344c596d04.e61bbedf67380ca3
+ 5df6d73059dd837e.3e8527449ee9f43b.ff3c4b3f064d8c21.7557cde51027645d
+ 22a9c22776ff3042
+VMULSD_128(mem)
+ before
+ c8dd1991b6cb297d.14227fde7c0f1494.4c6efdbc0d7a7fc6.b1cff9f1b4ddbe23
+ 42bf4f0fec980e3b.d97955953deed0d2.81603593a4c5577d.83a818b6f3943cb7
+ 6e1bdf8d327099a8.084857c13907f4e2.b82548b37fd6378d.d111a5f95efe4589
+ 26bc45f7a76187ef.fcd880ce0be4bb73.cf8ab30ab9b9dc22.f7579b2891a81344
+ 51c6f6af2a1de395
+ after
+ c8dd1991b6cb297d.14227fde7c0f1494.4c6efdbc0d7a7fc6.b1cff9f1b4ddbe23
+ 42bf4f0fec980e3b.d97955953deed0d2.81603593a4c5577d.83a818b6f3943cb7
+ 0000000000000000.0000000000000000.81603593a4c5577d.0000000000000000
+ 26bc45f7a76187ef.fcd880ce0be4bb73.cf8ab30ab9b9dc22.f7579b2891a81344
+ 51c6f6af2a1de395
+
+VMULSD_128(reg)
+ before
+ 3ca9b2f8c2eaf127.4870fd3a6577943d.1378cc285014632f.a05bf3836f7b0267
+ 124ecb70f79979a7.ae01844088bd7bbe.a773373ba32026c3.09648309bc276589
+ 30ff3e8365b8b6c1.363c54f62d3ffa9d.1614be74a19641da.e470df8abcc9c0b3
+ f209069ea7d3e520.baedeb496f09ca07.baa85b3de501ef21.0e4d83f18c6ed012
+ 64c5ec2b482151d1
+ after
+ 0000000000000000.0000000000000000.a773373ba32026c3.ade5a19df010190b
+ 124ecb70f79979a7.ae01844088bd7bbe.a773373ba32026c3.09648309bc276589
+ 30ff3e8365b8b6c1.363c54f62d3ffa9d.1614be74a19641da.e470df8abcc9c0b3
+ f209069ea7d3e520.baedeb496f09ca07.baa85b3de501ef21.0e4d83f18c6ed012
+ 64c5ec2b482151d1
+VMULSD_128(mem)
+ before
+ c0a594220beffe1d.b4b81f2b59754171.17dfc4246b28aa27.f17c0c040cee6e43
+ ffb9f9c3f1e39422.d2588598182a085f.2ae05c723ca7542a.15dacc33b1e8f8ee
+ fecd97fa1709cf0b.a73535507f7e7497.cdba2d21fe93853b.840e9838717bc9cb
+ 97ade8b4986d6b05.919b29bf2bfec2c5.dd3bb51ccef7f987.98666b7ee7341f88
+ ae2d4071b09e34d1
+ after
+ c0a594220beffe1d.b4b81f2b59754171.17dfc4246b28aa27.f17c0c040cee6e43
+ ffb9f9c3f1e39422.d2588598182a085f.2ae05c723ca7542a.15dacc33b1e8f8ee
+ 0000000000000000.0000000000000000.2ae05c723ca7542a.c7677cbd336945e4
+ 97ade8b4986d6b05.919b29bf2bfec2c5.dd3bb51ccef7f987.98666b7ee7341f88
+ ae2d4071b09e34d1
+
+VMULSD_128(reg)
+ before
+ 23ae157d67454552.a7246adc911c233b.ebd55f51b7352d94.362d6f4fc8df6c3a
+ 5136e60ea8b68eb6.0aff985d1d21b4da.1130d272c0b0f3b1.b55dd7a60757997f
+ 9511ad90107c4aa9.9c0bee255989da0e.5ff87f8ee1fa4dc7.34966a0ea86c3d83
+ 4c8b686f3a23b6d9.3a12e81f605f5002.30796011b79f7a83.90a6a371c6291371
+ a557fdbc7d9bd976
+ after
+ 0000000000000000.0000000000000000.1130d272c0b0f3b1.aa04e72a266e47be
+ 5136e60ea8b68eb6.0aff985d1d21b4da.1130d272c0b0f3b1.b55dd7a60757997f
+ 9511ad90107c4aa9.9c0bee255989da0e.5ff87f8ee1fa4dc7.34966a0ea86c3d83
+ 4c8b686f3a23b6d9.3a12e81f605f5002.30796011b79f7a83.90a6a371c6291371
+ a557fdbc7d9bd976
+VMULSD_128(mem)
+ before
+ 4f77f7dceacd49be.d0f01218c3380ef0.bee102374fafd4e3.e2ff7367dd2bb590
+ 6ad00abc28cb1f74.7e8ba7f547468d9a.0543b959418620dc.d0d6b3fdf02b399c
+ d22fb34754a219c5.b2aa237461d97084.eb06887153eff01a.56491d3d8b2a4350
+ 63606f6b895df1dc.c89783ffad7ef35a.4cf4eb6ba0f602c9.cfa6ab954bb50e5b
+ 99375b70cb57d766
+ after
+ 4f77f7dceacd49be.d0f01218c3380ef0.bee102374fafd4e3.e2ff7367dd2bb590
+ 6ad00abc28cb1f74.7e8ba7f547468d9a.0543b959418620dc.d0d6b3fdf02b399c
+ 0000000000000000.0000000000000000.0543b959418620dc.73e6503e89846ca1
+ 63606f6b895df1dc.c89783ffad7ef35a.4cf4eb6ba0f602c9.cfa6ab954bb50e5b
+ 99375b70cb57d766
+
+VADDSD_128(reg)
+ before
+ 0e492839a79cda20.f92eb913e40864e6.1c9fc204c8c052c7.04da5f3444a81014
+ 8c280e5e7c115333.70670d2b81b02e0f.0a0edcee4d2cc878.ef855eb65c10d628
+ 6d1f094ae6417d4c.a4d5e89f7a600a82.ee30cd29d94c9218.e8bf66df043a1230
+ 0f7c166980b89616.7145c55bed24b56c.2450922107afec54.cd54f29957327e59
+ 79127ed27105d7cf
+ after
+ 0000000000000000.0000000000000000.0a0edcee4d2cc878.ef855eb65c10d628
+ 8c280e5e7c115333.70670d2b81b02e0f.0a0edcee4d2cc878.ef855eb65c10d628
+ 6d1f094ae6417d4c.a4d5e89f7a600a82.ee30cd29d94c9218.e8bf66df043a1230
+ 0f7c166980b89616.7145c55bed24b56c.2450922107afec54.cd54f29957327e59
+ 79127ed27105d7cf
+VADDSD_128(mem)
+ before
+ c8c387756fbfd9bd.cc893028e602d73e.b2831f4bf609ebf8.08bc254274de12d8
+ 9635886e6d6a3f50.029353f1b5ac7f6f.455b745cb01a6853.f6be84f8bb673f4f
+ be32fda98514c6b3.0be77b318842c856.059940783863e7a8.4aa3aaaf78d5b065
+ 1e876212d6c92a13.44cea455fc4eef9f.ce09fd8da9f12525.60b794d448b4a0c8
+ 94463cd1c7914d22
+ after
+ c8c387756fbfd9bd.cc893028e602d73e.b2831f4bf609ebf8.08bc254274de12d8
+ 9635886e6d6a3f50.029353f1b5ac7f6f.455b745cb01a6853.f6be84f8bb673f4f
+ 0000000000000000.0000000000000000.455b745cb01a6853.f6be84f8bb673f4f
+ 1e876212d6c92a13.44cea455fc4eef9f.ce09fd8da9f12525.60b794d448b4a0c8
+ 94463cd1c7914d22
+
+VADDSD_128(reg)
+ before
+ 419ca01490f7f11f.910033957a94279b.0a97cbc7ac5e30f5.7b7629851fcfdef3
+ c504bb084073c96c.f268ed1e8d817879.b78debf535fec705.eaad3f4eb709cd41
+ 7bcc8918719010b5.1f8d0a9a2b9cdad6.a8fb004a32b8ef7b.f67abbd38dacaf39
+ bf3e07b2c2da04a6.f33908f372f209e1.392f0631401ae502.7aa91a00bcc34007
+ 5406d6c1605a3bd8
+ after
+ 0000000000000000.0000000000000000.b78debf535fec705.f67abbd38dacaf39
+ c504bb084073c96c.f268ed1e8d817879.b78debf535fec705.eaad3f4eb709cd41
+ 7bcc8918719010b5.1f8d0a9a2b9cdad6.a8fb004a32b8ef7b.f67abbd38dacaf39
+ bf3e07b2c2da04a6.f33908f372f209e1.392f0631401ae502.7aa91a00bcc34007
+ 5406d6c1605a3bd8
+VADDSD_128(mem)
+ before
+ 5e5d6d02967e5ed8.eca72f41cddddee9.493a63177b8ec0c3.c773fa18fab0e446
+ 76795aaf7a3a6332.6053ff312e26dd2d.ff5a95f0647cbcab.ac14d76afd052af4
+ 762819b5269b0613.768d72ee82413c1c.ef651c6c49c9b9c3.455d9993e4a5f1b8
+ 3c3427feb9ab05a7.89a385e564b83663.f729737645807338.ee9c3c004c1c753e
+ 031cbc1bd0f7f431
+ after
+ 5e5d6d02967e5ed8.eca72f41cddddee9.493a63177b8ec0c3.c773fa18fab0e446
+ 76795aaf7a3a6332.6053ff312e26dd2d.ff5a95f0647cbcab.ac14d76afd052af4
+ 0000000000000000.0000000000000000.ff5a95f0647cbcab.c773fa18fab0e446
+ 3c3427feb9ab05a7.89a385e564b83663.f729737645807338.ee9c3c004c1c753e
+ 031cbc1bd0f7f431
+
+VADDSD_128(reg)
+ before
+ e02816510cc1a83d.a26aff774c781a19.f7df3280711908ad.f17116fa75aea535
+ e10d450f9d06ce0f.86961d0dfe0e0295.1a8f772c44efeda7.ba0881e4f45d0ce7
+ 621745bf1e53a253.c283fdabe8787949.50fd4f567ac722fc.2fbc3120de9c6479
+ bf9212cf2c335fb5.33ff1b3c28c23a5e.f376b669ae2ce35a.2a57a09a50746818
+ 88a64c3f65f3d5f0
+ after
+ 0000000000000000.0000000000000000.1a8f772c44efeda7.ba0881e4f45d0ce7
+ e10d450f9d06ce0f.86961d0dfe0e0295.1a8f772c44efeda7.ba0881e4f45d0ce7
+ 621745bf1e53a253.c283fdabe8787949.50fd4f567ac722fc.2fbc3120de9c6479
+ bf9212cf2c335fb5.33ff1b3c28c23a5e.f376b669ae2ce35a.2a57a09a50746818
+ 88a64c3f65f3d5f0
+VADDSD_128(mem)
+ before
+ 2674b1f93a24672c.54caa9aa633342e0.b5d4f4aedaf80203.6146a9d07daa6c6a
+ de8f49b6eb14daf9.7d0a04bc5edd8780.25d002ec19278d62.f4b822f982cef9da
+ 8dc2926092cde983.95a02171b9c06a42.5dbdc3e2025a96a7.091a1f4f5923c556
+ 0fd806e54e5e51f5.fad6fc35116526d2.3a68b37db09eda00.fdb69b3e9f350d8a
+ 2ad99232f0910c21
+ after
+ 2674b1f93a24672c.54caa9aa633342e0.b5d4f4aedaf80203.6146a9d07daa6c6a
+ de8f49b6eb14daf9.7d0a04bc5edd8780.25d002ec19278d62.f4b822f982cef9da
+ 0000000000000000.0000000000000000.25d002ec19278d62.f4b822f982cef9da
+ 0fd806e54e5e51f5.fad6fc35116526d2.3a68b37db09eda00.fdb69b3e9f350d8a
+ 2ad99232f0910c21
+
+VMINSD_128(reg)
+ before
+ edcf0197e7c200c7.409e243038d0ce7b.07f98f74015af8db.989c4ca73ffe1597
+ a2e4e3d92054232a.fde0652d6f311b42.1855d89a262a1b0a.53270c4dcc860398
+ a664346538d4b1f3.206a46c70c8cf676.8836d1131b62cd0b.48d36e5b73435f30
+ 539af0a5cbcde8d1.860844ed2dee1843.b5e8784c7c8c4889.516eeebe4f40e68b
+ 4bc208617c8954d4
+ after
+ 0000000000000000.0000000000000000.1855d89a262a1b0a.48d36e5b73435f30
+ a2e4e3d92054232a.fde0652d6f311b42.1855d89a262a1b0a.53270c4dcc860398
+ a664346538d4b1f3.206a46c70c8cf676.8836d1131b62cd0b.48d36e5b73435f30
+ 539af0a5cbcde8d1.860844ed2dee1843.b5e8784c7c8c4889.516eeebe4f40e68b
+ 4bc208617c8954d4
+VMINSD_128(mem)
+ before
+ 129c392f172a6438.06d4130774cb026e.0b85da88ee6240d4.fab6c9afe737c931
+ 82c8fc163b30d4e2.1b5c9af6cf5b3c77.8baf84856af42855.b2edbeaaf5ec8bae
+ 7711cd0105a75eff.ee7f7fdd7908d297.e250bfd0beb18ef3.3bda55a84439ccad
+ cc4528dc9099beba.db89c02a0d5fff7b.ec35055605a42bda.f0c7891470a9c6d9
+ 2c00565c14c9b5e0
+ after
+ 129c392f172a6438.06d4130774cb026e.0b85da88ee6240d4.fab6c9afe737c931
+ 82c8fc163b30d4e2.1b5c9af6cf5b3c77.8baf84856af42855.b2edbeaaf5ec8bae
+ 0000000000000000.0000000000000000.8baf84856af42855.fab6c9afe737c931
+ cc4528dc9099beba.db89c02a0d5fff7b.ec35055605a42bda.f0c7891470a9c6d9
+ 2c00565c14c9b5e0
+
+VMINSD_128(reg)
+ before
+ 4dd3b8ebcc24d76b.5f2e8993f914b241.3ec6594828ea00ce.852ad4015bd9be35
+ ad8bac2d35466629.0b996d125b24f4bd.738244a36537113d.88fba7bfdd5d0131
+ a9732d8eebbc9fc3.ac524f46d3d3415d.d6087fa761d26d73.d373fa7ba73bb1fa
+ 9ed8377b8811bde8.1e25ab197c2f544b.c3a505c0b746521e.41604a20d37f8abb
+ ae8c119c803647a1
+ after
+ 0000000000000000.0000000000000000.738244a36537113d.d373fa7ba73bb1fa
+ ad8bac2d35466629.0b996d125b24f4bd.738244a36537113d.88fba7bfdd5d0131
+ a9732d8eebbc9fc3.ac524f46d3d3415d.d6087fa761d26d73.d373fa7ba73bb1fa
+ 9ed8377b8811bde8.1e25ab197c2f544b.c3a505c0b746521e.41604a20d37f8abb
+ ae8c119c803647a1
+VMINSD_128(mem)
+ before
+ f5c4cddac86ba5d7.e606c65eabd1fe42.3ddefd787344eab3.96a5d25b031ff9e7
+ f4d4fac6c72a608a.df49d6a4ee899c7e.e449c250d31cbfc2.ab54e2e2e2e9a17d
+ 8688124d9a8034e6.e3ed64baedc4d347.f131748cb8c58fa4.5efe32c3f031858a
+ 87ac92595c78dc16.4f3e6b0b450ee14a.3f6391173f4b1584.0aefbd68c882e0ba
+ 0d727f3f0669eeba
+ after
+ f5c4cddac86ba5d7.e606c65eabd1fe42.3ddefd787344eab3.96a5d25b031ff9e7
+ f4d4fac6c72a608a.df49d6a4ee899c7e.e449c250d31cbfc2.ab54e2e2e2e9a17d
+ 0000000000000000.0000000000000000.e449c250d31cbfc2.ab54e2e2e2e9a17d
+ 87ac92595c78dc16.4f3e6b0b450ee14a.3f6391173f4b1584.0aefbd68c882e0ba
+ 0d727f3f0669eeba
+
+VMINSD_128(reg)
+ before
+ c2d574b34771ed36.d20bf7d72a1e1546.7f87e70291f40032.a9ab95df84b80f8f
+ 84629830272617d9.4573bcb41f7f9ba4.d015d40d6e016dac.0dd5facfa21a36f1
+ b166e8214114a950.baae5dda57a6295a.9c342f9777c16464.45ad3ed3b57d49d5
+ a42d5ff531c8df47.0f895737f09f7c94.4030f30c48c12005.2fffdbd7daec0268
+ a5964fc72c731ed5
+ after
+ 0000000000000000.0000000000000000.d015d40d6e016dac.0dd5facfa21a36f1
+ 84629830272617d9.4573bcb41f7f9ba4.d015d40d6e016dac.0dd5facfa21a36f1
+ b166e8214114a950.baae5dda57a6295a.9c342f9777c16464.45ad3ed3b57d49d5
+ a42d5ff531c8df47.0f895737f09f7c94.4030f30c48c12005.2fffdbd7daec0268
+ a5964fc72c731ed5
+VMINSD_128(mem)
+ before
+ 85401690c81e5949.b803f91594cef469.1ed025b60377507f.18551cd87e8cde3c
+ a9c7aa1cc9fa6eef.4b33b2ee05b02563.c54f4243ae396147.80efa667b5aedab4
+ eff889594c121bf4.b70b87ec21fcaee0.ded12dca0df26a17.d4498d2688b44f1a
+ 319f2e316c731984.5ad5737c833dcb8d.47245f373bad281c.70b1ce7f93297a1a
+ b07164e0739a975f
+ after
+ 85401690c81e5949.b803f91594cef469.1ed025b60377507f.18551cd87e8cde3c
+ a9c7aa1cc9fa6eef.4b33b2ee05b02563.c54f4243ae396147.80efa667b5aedab4
+ 0000000000000000.0000000000000000.c54f4243ae396147.80efa667b5aedab4
+ 319f2e316c731984.5ad5737c833dcb8d.47245f373bad281c.70b1ce7f93297a1a
+ b07164e0739a975f
+
+VSUBSD_128(reg)
+ before
+ f0d64bb3c491e296.4c871592462727ca.8ede7208c800b715.da12557654765782
+ 8c2c7f66219d966a.1d7eba67f53dfff3.b17280fe8bd0af25.74688c737559b274
+ e0bffd642647f088.7e4e9a9b96be5e2b.1ddd99c96939ef69.f2f27f1aba63f61e
+ 48dac018701d2c9c.4cc5301c44b8009d.306bbad4fdc8b28c.2e7caa583d9fdfad
+ 05d28a171d1a294d
+ after
+ 0000000000000000.0000000000000000.b17280fe8bd0af25.74688c739a57e7e9
+ 8c2c7f66219d966a.1d7eba67f53dfff3.b17280fe8bd0af25.74688c737559b274
+ e0bffd642647f088.7e4e9a9b96be5e2b.1ddd99c96939ef69.f2f27f1aba63f61e
+ 48dac018701d2c9c.4cc5301c44b8009d.306bbad4fdc8b28c.2e7caa583d9fdfad
+ 05d28a171d1a294d
+VSUBSD_128(mem)
+ before
+ 53bf994574df8f2a.20cbc3f09aaa8651.64adf8d51b36a175.4467de8de308363b
+ f41055cc5eface6f.c4dc0557417a3954.a0d36eb33845fce0.b61e015fb885b422
+ c592399af877a248.8f5a7fba001a8250.dd020fa0b7f0ce0a.e3dd1fb618cc6bec
+ a00fc29a5d63c6e3.df912f8374159df2.f7085589b343d21f.25ee34ff9e689545
+ d99d3da4e6e56fdb
+ after
+ 53bf994574df8f2a.20cbc3f09aaa8651.64adf8d51b36a175.4467de8de308363b
+ f41055cc5eface6f.c4dc0557417a3954.a0d36eb33845fce0.b61e015fb885b422
+ 0000000000000000.0000000000000000.a0d36eb33845fce0.c467de8de308363b
+ a00fc29a5d63c6e3.df912f8374159df2.f7085589b343d21f.25ee34ff9e689545
+ d99d3da4e6e56fdb
+
+VSUBSD_128(reg)
+ before
+ 5b3835128dd03557.62546ab8a9c9f869.0fcd0f1f38f8c5e5.caafbe5b484ac64a
+ 080a18b62fb42368.e72cafe0fab6f109.7a591efbe94e37d6.32c5c500931264b7
+ 3a5ee3fa671d74b8.0b650cfe693570ed.7e83558122a32f71.0b14e766b0a66893
+ 4e81904cd19865f4.aac9fdff14522f41.7695b11f8084e961.31699e77ba13900a
+ 80906821cd649648
+ after
+ 0000000000000000.0000000000000000.7a591efbe94e37d6.32c5c500931264b7
+ 080a18b62fb42368.e72cafe0fab6f109.7a591efbe94e37d6.32c5c500931264b7
+ 3a5ee3fa671d74b8.0b650cfe693570ed.7e83558122a32f71.0b14e766b0a66893
+ 4e81904cd19865f4.aac9fdff14522f41.7695b11f8084e961.31699e77ba13900a
+ 80906821cd649648
+VSUBSD_128(mem)
+ before
+ d454c04f06a53778.a0bf1d170ab031c7.a026fecd171aec33.bddc2f3f9e7ca053
+ 098322ed80e32fc6.8c6485c6adf116de.c9468c558d9860ec.b1a4ca4f181791f3
+ fbe70be75829395f.6ebcc4c757e84ee4.01f6228492d84a9b.ac397eba8be1f8ec
+ 864df529a983126f.a213d785a3201686.23013c4543e7646a.0ce747ec936710eb
+ 2bf92251cb35169b
+ after
+ d454c04f06a53778.a0bf1d170ab031c7.a026fecd171aec33.bddc2f3f9e7ca053
+ 098322ed80e32fc6.8c6485c6adf116de.c9468c558d9860ec.b1a4ca4f181791f3
+ 0000000000000000.0000000000000000.c9468c558d9860ec.3ddc2f3f9e7ca053
+ 864df529a983126f.a213d785a3201686.23013c4543e7646a.0ce747ec936710eb
+ 2bf92251cb35169b
+
+VSUBSD_128(reg)
+ before
+ 67bd0a55cfd546a9.86815ea08ffe7621.84b4b96d2e26a96f.0d355683bcd06b85
+ 1a7dfb643cd5dcc0.d64fc13628a521a2.70ed65e99385444d.9a5ced2c189f1b19
+ a286f1ebadc1138d.54839bd88d84ce1e.c208da666ec923c9.a6447b2b73612f52
+ 5924e954bf2328bc.dbe96673dca83ac0.d55211505c7e8292.0db77e6cea21645b
+ aa8271db98eb7661
+ after
+ 0000000000000000.0000000000000000.70ed65e99385444d.26447b2b73612f52
+ 1a7dfb643cd5dcc0.d64fc13628a521a2.70ed65e99385444d.9a5ced2c189f1b19
+ a286f1ebadc1138d.54839bd88d84ce1e.c208da666ec923c9.a6447b2b73612f52
+ 5924e954bf2328bc.dbe96673dca83ac0.d55211505c7e8292.0db77e6cea21645b
+ aa8271db98eb7661
+VSUBSD_128(mem)
+ before
+ 5b71d1649acc2190.9ca3dd0d0d8957f8.464ca0f2311c20b5.07170714f9319c52
+ fb4f18f40bcf2013.c74ecb80347fdbee.7379c440a7ec3e28.b3a2b91de06daeb5
+ 65eac47508003017.3773ae1bcf8ff14a.3d3c4e4b5a254e46.354122d6adbff468
+ 770c50d4ac6c0dc7.465c83497b47d5b7.7f61bafe67d20d3b.e93e3eadfdb2aa17
+ 2ae60a0d6cd20b6d
+ after
+ 5b71d1649acc2190.9ca3dd0d0d8957f8.464ca0f2311c20b5.07170714f9319c52
+ fb4f18f40bcf2013.c74ecb80347fdbee.7379c440a7ec3e28.b3a2b91de06daeb5
+ 0000000000000000.0000000000000000.7379c440a7ec3e28.b3a2b91de06daeb5
+ 770c50d4ac6c0dc7.465c83497b47d5b7.7f61bafe67d20d3b.e93e3eadfdb2aa17
+ 2ae60a0d6cd20b6d
+
+VDIVSD_128(reg)
+ before
+ 5685816295ab5417.0b8338fe141e7250.51564476d333c3e1.17b48545ea003632
+ c8679e1814cac1c1.ff19f9de5b231cdd.b4adef0e74ddf675.df012a0cfeb98757
+ dbd8609b86ba8d16.2d9b0d5f9d85c79b.cbad7f7df9d3ab1f.b513253fbf0bbad8
+ ed24c0578608f5c3.73d4f26ff7522fb6.f2a2f02ffea11e8b.73b8f2cb4a028bde
+ f7ba0e9abaa9b898
+ after
+ 0000000000000000.0000000000000000.b4adef0e74ddf675.69dcb0436fed1148
+ c8679e1814cac1c1.ff19f9de5b231cdd.b4adef0e74ddf675.df012a0cfeb98757
+ dbd8609b86ba8d16.2d9b0d5f9d85c79b.cbad7f7df9d3ab1f.b513253fbf0bbad8
+ ed24c0578608f5c3.73d4f26ff7522fb6.f2a2f02ffea11e8b.73b8f2cb4a028bde
+ f7ba0e9abaa9b898
+VDIVSD_128(mem)
+ before
+ 1be6f39a2c0cfb30.5896bbb9b13f3573.ab9223f985960f59.86d73e9120d28a64
+ bd081fb5bb3711d3.7a7b4e2ba2eb89d3.b39f1de9625c24b1.e19a660dfbf22d56
+ b7eb0dd98437b5ac.ad1f741bf6992c8e.65c95a2baab02aea.603563102a8d410e
+ e65d3af1a217a5e8.4fce29f348d45b51.9eda58ac7a9edc2f.5ff5310749300238
+ 3926cc5df566ae80
+ after
+ 1be6f39a2c0cfb30.5896bbb9b13f3573.ab9223f985960f59.86d73e9120d28a64
+ bd081fb5bb3711d3.7a7b4e2ba2eb89d3.b39f1de9625c24b1.e19a660dfbf22d56
+ 0000000000000000.0000000000000000.b39f1de9625c24b1.7ff0000000000000
+ e65d3af1a217a5e8.4fce29f348d45b51.9eda58ac7a9edc2f.5ff5310749300238
+ 3926cc5df566ae80
+
+VDIVSD_128(reg)
+ before
+ 4c13317dcabb7f91.272820e931e49bb2.bad46a21352852c8.3b9f9256ee33f7ac
+ f30a5bd562bcb117.541a3dac4fa95437.4c7d311058224c9e.16e48416217a378f
+ 8a5546d05cf482bf.4afd0c2915728ba3.5f147c2c4d4d8680.0c74abd92f805802
+ 6d42eeda52f02c35.e59e0949a14bfd21.50e746e1b1353c1a.f91d818935501531
+ b9a984144ef62b49
+ after
+ 0000000000000000.0000000000000000.4c7d311058224c9e.4a5fc272670ae88e
+ f30a5bd562bcb117.541a3dac4fa95437.4c7d311058224c9e.16e48416217a378f
+ 8a5546d05cf482bf.4afd0c2915728ba3.5f147c2c4d4d8680.0c74abd92f805802
+ 6d42eeda52f02c35.e59e0949a14bfd21.50e746e1b1353c1a.f91d818935501531
+ b9a984144ef62b49
+VDIVSD_128(mem)
+ before
+ 29e52f65977e5676.f81b4f5fe03bec24.01c8b1f90f4166de.7b408c9b2067aa17
+ 239dff682bf551e3.862d66cca261fe39.7b497f257a5f8205.3d6c48c6356e0b23
+ 849d6e092767dabd.75c32e8b36ee9d20.2debefbafeb20cc3.f0b778ce8cd69cec
+ 28b1fa34a6deaa2f.202ba309356f0684.f47c7da2b845c144.f16c1720c22c991b
+ 9cd9212673fb3d5f
+ after
+ 29e52f65977e5676.f81b4f5fe03bec24.01c8b1f90f4166de.7b408c9b2067aa17
+ 239dff682bf551e3.862d66cca261fe39.7b497f257a5f8205.3d6c48c6356e0b23
+ 0000000000000000.0000000000000000.7b497f257a5f8205.021b587703aae606
+ 28b1fa34a6deaa2f.202ba309356f0684.f47c7da2b845c144.f16c1720c22c991b
+ 9cd9212673fb3d5f
+
+VDIVSD_128(reg)
+ before
+ 4d48924e39cfc662.eba41ed5c4688066.e2b0c1b33d707512.acc6a5cbc3245db3
+ 61076702b3356dd0.a94456d89e10168e.199d84f3ea7b2675.3196e4203c5c9b3d
+ 32609bb07bb87157.3e5b1e2950e32ad2.203fe937d71e545a.5fb8b48c3ff8390d
+ 1da02ac32de40ca0.86b6f3b5f5ec755f.52e2ebeaa1e43c6c.12f793fde604f150
+ 2621fd5e508d7f32
+ after
+ 0000000000000000.0000000000000000.199d84f3ea7b2675.11cda672afb131aa
+ 61076702b3356dd0.a94456d89e10168e.199d84f3ea7b2675.3196e4203c5c9b3d
+ 32609bb07bb87157.3e5b1e2950e32ad2.203fe937d71e545a.5fb8b48c3ff8390d
+ 1da02ac32de40ca0.86b6f3b5f5ec755f.52e2ebeaa1e43c6c.12f793fde604f150
+ 2621fd5e508d7f32
+VDIVSD_128(mem)
+ before
+ 76006c9b969ea1de.7e1210a766467c5a.5d215066a937b660.0dd28678e35a1a58
+ e0615ea0d6431181.b10449c8c169fa2f.9e68b12a89d1a702.ab5bb74d390b29ca
+ 3f104d5a2c898c46.12c1d292dadac5cb.275692ecb1c50570.8ac878d54083a66d
+ 6fd9b8b3b37bcd5a.fd94a6714f2317dc.d3b96f983c1f8cd8.0467c77c934fcdee
+ 76829faecffadaf9
+ after
+ 76006c9b969ea1de.7e1210a766467c5a.5d215066a937b660.0dd28678e35a1a58
+ e0615ea0d6431181.b10449c8c169fa2f.9e68b12a89d1a702.ab5bb74d390b29ca
+ 0000000000000000.0000000000000000.9e68b12a89d1a702.dd77f01a39563f76
+ 6fd9b8b3b37bcd5a.fd94a6714f2317dc.d3b96f983c1f8cd8.0467c77c934fcdee
+ 76829faecffadaf9
+
+VMAXSD_128(reg)
+ before
+ 3d66fcd890100839.4c881899882591e9.cdcac1d1b9d32d0b.7e5bc51a46ecf763
+ b35fdb64701e945a.b1e9eaf6c694941e.e0af201fb6734307.04090f5eec370340
+ 36b936c00eafba0a.7cc7abb889d39225.918fbdc5e291947a.408fc950490c6c99
+ 20bf0b56034fb5f3.88efd6c9eeee462c.3cb59631d8b85d10.10b970dc7a78ee9a
+ 4f537eee9a864470
+ after
+ 0000000000000000.0000000000000000.e0af201fb6734307.408fc950490c6c99
+ b35fdb64701e945a.b1e9eaf6c694941e.e0af201fb6734307.04090f5eec370340
+ 36b936c00eafba0a.7cc7abb889d39225.918fbdc5e291947a.408fc950490c6c99
+ 20bf0b56034fb5f3.88efd6c9eeee462c.3cb59631d8b85d10.10b970dc7a78ee9a
+ 4f537eee9a864470
+VMAXSD_128(mem)
+ before
+ d8287172c6422b47.cebf5594ee8bc3c1.b02de71711f26e5d.3d6fa6ce3475da76
+ 8906c45519b95f4a.9c0311e568ee1d21.d24d5b8d0deac3e4.ef07e90793524658
+ 3cb7f382b0f69ba6.e6d839b5100402bf.c81bac17fee204ee.b0cb5c4a91dedf61
+ cf087be4a6069c87.098acb707f5aac46.706358a101e7eba7.db05f902c9a2df3e
+ cb02be9bd72c829b
+ after
+ d8287172c6422b47.cebf5594ee8bc3c1.b02de71711f26e5d.3d6fa6ce3475da76
+ 8906c45519b95f4a.9c0311e568ee1d21.d24d5b8d0deac3e4.ef07e90793524658
+ 0000000000000000.0000000000000000.d24d5b8d0deac3e4.3d6fa6ce3475da76
+ cf087be4a6069c87.098acb707f5aac46.706358a101e7eba7.db05f902c9a2df3e
+ cb02be9bd72c829b
+
+VMAXSD_128(reg)
+ before
+ de0da68158070623.1cc5d66918f31e18.5f65c282537b5863.a5f0da183204353a
+ 6f74ad21e7c0a583.01ba82fc21ccdd85.45b41a5728f342c1.4290ae66ab459ed4
+ d981d0e521e29c66.58b2fa89dd9a94fc.17c5d05b994fa60d.240d51788bb7e1a1
+ 7a820a3aa1f92679.ff7bbbfc696b00a6.31e2defb421abff3.28343e3beb65bccc
+ 28d1f199ea5ce881
+ after
+ 0000000000000000.0000000000000000.45b41a5728f342c1.4290ae66ab459ed4
+ 6f74ad21e7c0a583.01ba82fc21ccdd85.45b41a5728f342c1.4290ae66ab459ed4
+ d981d0e521e29c66.58b2fa89dd9a94fc.17c5d05b994fa60d.240d51788bb7e1a1
+ 7a820a3aa1f92679.ff7bbbfc696b00a6.31e2defb421abff3.28343e3beb65bccc
+ 28d1f199ea5ce881
+VMAXSD_128(mem)
+ before
+ 02afe680a1a724ee.acc1578d04928167.d0df3f41e14addb2.ef5942a1c0e0ca1e
+ 909c99db2e522a3d.cd8bb349e538e7dd.a8ab04445f43e64a.ad74f7bbaf2e023b
+ af628796ad69b79a.372b1ad9e1779487.64ab85f10263d89b.c77ffab3aa8fa5f5
+ 3bcf2b9d39f98732.47ef89ab93dcc610.deab3e35e4b56fd0.99c845f74d90edf9
+ 7f9ad6f235bc17f3
+ after
+ 02afe680a1a724ee.acc1578d04928167.d0df3f41e14addb2.ef5942a1c0e0ca1e
+ 909c99db2e522a3d.cd8bb349e538e7dd.a8ab04445f43e64a.ad74f7bbaf2e023b
+ 0000000000000000.0000000000000000.a8ab04445f43e64a.ad74f7bbaf2e023b
+ 3bcf2b9d39f98732.47ef89ab93dcc610.deab3e35e4b56fd0.99c845f74d90edf9
+ 7f9ad6f235bc17f3
+
+VMAXSD_128(reg)
+ before
+ d440a810fd9f5e8e.11ad01dcef0d5631.5a22fb2a97f2b725.f377acfa21466716
+ f607b7bd42c5ff76.0bc9853feab2dfc2.ca0f6cc28a45a472.7fda492ed6217b98
+ 403cff659fbb3659.06ee33b246f3df12.f403d8df0862c9a2.5fa293bc1e526883
+ 0e287d74b10c3fe1.deea882120dc114c.354a3cedacd46161.6d99058f16e6ea03
+ 868c1b95d9e8bc43
+ after
+ 0000000000000000.0000000000000000.ca0f6cc28a45a472.7fda492ed6217b98
+ f607b7bd42c5ff76.0bc9853feab2dfc2.ca0f6cc28a45a472.7fda492ed6217b98
+ 403cff659fbb3659.06ee33b246f3df12.f403d8df0862c9a2.5fa293bc1e526883
+ 0e287d74b10c3fe1.deea882120dc114c.354a3cedacd46161.6d99058f16e6ea03
+ 868c1b95d9e8bc43
+VMAXSD_128(mem)
+ before
+ 864752b984649c70.bb1a2c57134556ba.6f87ff79947a339d.e73092581227a95d
+ 499525e7326643b5.a55d087862f1b691.959314a4bdd8ff31.6701d88dd7e8dd3f
+ ab44100b00fb703f.273c0d45399c9b12.2cd84390b7023133.11080af697a238b6
+ 881e8f12092fdd3a.9c05382834d243e8.102309289f0487d0.41932201ece1f76c
+ 53ec1d197532560d
+ after
+ 864752b984649c70.bb1a2c57134556ba.6f87ff79947a339d.e73092581227a95d
+ 499525e7326643b5.a55d087862f1b691.959314a4bdd8ff31.6701d88dd7e8dd3f
+ 0000000000000000.0000000000000000.959314a4bdd8ff31.6701d88dd7e8dd3f
+ 881e8f12092fdd3a.9c05382834d243e8.102309289f0487d0.41932201ece1f76c
+ 53ec1d197532560d
+
+VPSHUFD_0x39_128(reg)
+ before
+ a360f8a9cb209147.bcf11ee6690c48d1.6202838ff120e8c0.1d40e15790ebbb33
+ 8e3bae1f8d37e3c3.23873a753da06a31.d380ece50912c746.2ffa470ba7c38a89
+ 6ec93ce654048930.99ad5ea9a1f60285.4dcb6e961a321c25.221fb72fff96b0fe
+ 9f559c6abf12bf38.fa2e0670b01bcafa.2b2e060ec00e220a.d279adafb572e8bd
+ 1bd5a678e463eff3
+ after
+ a360f8a9cb209147.bcf11ee6690c48d1.6202838ff120e8c0.1d40e15790ebbb33
+ 0000000000000000.0000000000000000.b572e8bd2b2e060e.c00e220ad279adaf
+ 6ec93ce654048930.99ad5ea9a1f60285.4dcb6e961a321c25.221fb72fff96b0fe
+ 9f559c6abf12bf38.fa2e0670b01bcafa.2b2e060ec00e220a.d279adafb572e8bd
+ 1bd5a678e463eff3
+VPSHUFD_0x39_128(mem)
+ before
+ d9001d74a97381cb.7f2dcc1767eec187.21d8aeb4861a7fbc.c8f7aeb9953117a0
+ e7c38e901fb05a72.699bc759eb22cacb.ec75d26340ffddf6.8170640338283494
+ 23ed75b963263513.b9ec899de43c17ad.36d3ef68f9d79fd4.b3e72358437eb891
+ 68494fd990dfcfdb.cb6c0e4df0c8e3dc.dbbc80afcead8284.b8a6e72552bfdd44
+ eefaadd40278e059
+ after
+ d9001d74a97381cb.7f2dcc1767eec187.21d8aeb4861a7fbc.c8f7aeb9953117a0
+ e7c38e901fb05a72.699bc759eb22cacb.ec75d26340ffddf6.8170640338283494
+ 0000000000000000.0000000000000000.21d8aeb4953117a0.c8f7aeb9861a7fbc
+ 68494fd990dfcfdb.cb6c0e4df0c8e3dc.dbbc80afcead8284.b8a6e72552bfdd44
+ eefaadd40278e059
+
+VPSHUFD_0x39_128(reg)
+ before
+ af2e6fd3ee34fd7b.92a297dec2e9e3f6.fb6753d7ab516c02.b6fd0124da8d4230
+ 58902b8cb37f7057.7cc5c8b316502f90.a52952a5b063eccb.a562eeb33a849b04
+ 456adc6dece67498.047f6143a81e6dd3.24fd09259b8aa0e4.83b6c449099d482d
+ d30a7fe136f446eb.0499db7c93615aee.d63174c20953c3f9.2bc7fed064e506d7
+ 7b5f18366666912d
+ after
+ af2e6fd3ee34fd7b.92a297dec2e9e3f6.fb6753d7ab516c02.b6fd0124da8d4230
+ 0000000000000000.0000000000000000.64e506d7d63174c2.0953c3f92bc7fed0
+ 456adc6dece67498.047f6143a81e6dd3.24fd09259b8aa0e4.83b6c449099d482d
+ d30a7fe136f446eb.0499db7c93615aee.d63174c20953c3f9.2bc7fed064e506d7
+ 7b5f18366666912d
+VPSHUFD_0x39_128(mem)
+ before
+ 4d4c8e652c2ea45c.5cba0e542c3521fc.5ae2b449f325b10b.160f8de8964a92b5
+ 7f58dd4bd149fc90.3dc787326b364376.e1256796e5753057.40e45202dcf949c5
+ eb507fd372c255f4.d27de5e78e82e606.742d7050845d91fd.affcbe7f7aee24d5
+ 6ffff2e82aa56bb5.772724df31a64658.f1c84b61ede9902a.c1a3cdc80ab45f90
+ d0247b4a28d835a3
+ after
+ 4d4c8e652c2ea45c.5cba0e542c3521fc.5ae2b449f325b10b.160f8de8964a92b5
+ 7f58dd4bd149fc90.3dc787326b364376.e1256796e5753057.40e45202dcf949c5
+ 0000000000000000.0000000000000000.5ae2b449964a92b5.160f8de8f325b10b
+ 6ffff2e82aa56bb5.772724df31a64658.f1c84b61ede9902a.c1a3cdc80ab45f90
+ d0247b4a28d835a3
+
+VPSHUFD_0x39_128(reg)
+ before
+ 3acdc57171e5e3b9.e533b17815fef9fe.88134186f12ca117.32c074b63b26eb09
+ 59e8a5aa8067a47f.2bb6396e50dabcfc.618b36496aa231ef.14e2683c8b1f5cc7
+ 8bc2195ff2ebb5a0.1b5604b6f74470da.5edc01923794338d.74faa2ddf8e1a090
+ 2aa71dfe62fc52c9.92dd903d2549d0c5.db529dcff48de39d.2cd39e879f76728f
+ 193bd9259bec90f1
+ after
+ 3acdc57171e5e3b9.e533b17815fef9fe.88134186f12ca117.32c074b63b26eb09
+ 0000000000000000.0000000000000000.9f76728fdb529dcf.f48de39d2cd39e87
+ 8bc2195ff2ebb5a0.1b5604b6f74470da.5edc01923794338d.74faa2ddf8e1a090
+ 2aa71dfe62fc52c9.92dd903d2549d0c5.db529dcff48de39d.2cd39e879f76728f
+ 193bd9259bec90f1
+VPSHUFD_0x39_128(mem)
+ before
+ 18fccda3094fb4e2.94e3abf26c26b7a6.6d1858edf6f399e9.3439076a3e197cca
+ 03e4f8ed04aa9b8d.23c1c1a6aef520e2.86d3d8b387518771.c5dd39d1b0c43bc1
+ b7bdd5efa809001e.348f5988c1f6c82a.bad98c7cf36c568a.ea8a316fe71b5c2e
+ 1054e0951279a0c3.2497720343b5ec2a.e5f8f1335752c15f.ff8beab07fa91abc
+ 5f2d600012fbb318
+ after
+ 18fccda3094fb4e2.94e3abf26c26b7a6.6d1858edf6f399e9.3439076a3e197cca
+ 03e4f8ed04aa9b8d.23c1c1a6aef520e2.86d3d8b387518771.c5dd39d1b0c43bc1
+ 0000000000000000.0000000000000000.6d1858ed3e197cca.3439076af6f399e9
+ 1054e0951279a0c3.2497720343b5ec2a.e5f8f1335752c15f.ff8beab07fa91abc
+ 5f2d600012fbb318
+
+VPCMPEQD_128(reg)
+ before
+ 68bc8fcb3f9c61ed.eb7496cb5e0437a5.4d260583d0bcc78d.e4fa82c3ce0e851d
+ 7584747d9f1860e8.22eb717da7b981f3.0c880f75039997ff.91acbb1a75ad5ef0
+ e2d10a83d1fbeeb5.9283ef9809a139d7.be098d4378d8962e.c9da1823673a0703
+ 0aef4d476ed245ff.170a8b06a1ca1c7d.bdf57a5acc0300c3.685016cac1c13e83
+ 4ada30fb9e4ebc9b
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 7584747d9f1860e8.22eb717da7b981f3.0c880f75039997ff.91acbb1a75ad5ef0
+ e2d10a83d1fbeeb5.9283ef9809a139d7.be098d4378d8962e.c9da1823673a0703
+ 0aef4d476ed245ff.170a8b06a1ca1c7d.bdf57a5acc0300c3.685016cac1c13e83
+ 4ada30fb9e4ebc9b
+VPCMPEQD_128(mem)
+ before
+ 4b43e1a21bee4078.4b2939371428a273.8d4ac2b58b3fe613.6698d2279aa9136d
+ 4759a8ab53ad8446.00cccbbd5f8a40bc.d0100e90e20d52c2.153d92147f5309d6
+ 1ae6fe0362954630.8425fd47ea835d87.bc28ed82c23f1eb9.2631b48f178f1faa
+ a0b7619465b43f63.357ecd40529f337f.2d5dda7948e10422.f5c03603fce89197
+ de3613dbcdea9a46
+ after
+ 4b43e1a21bee4078.4b2939371428a273.8d4ac2b58b3fe613.6698d2279aa9136d
+ 4759a8ab53ad8446.00cccbbd5f8a40bc.d0100e90e20d52c2.153d92147f5309d6
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ a0b7619465b43f63.357ecd40529f337f.2d5dda7948e10422.f5c03603fce89197
+ de3613dbcdea9a46
+
+VPCMPEQD_128(reg)
+ before
+ 3ddf478523227766.b5984b4c78162e0a.6d233614316bfe51.ff7d51608f00c029
+ 6e07cf6c9d1b64a1.35553a15b6c5cd52.8a62352f2672fca9.0e52cf23b4a710fb
+ cdf9a5fdd4619ca3.fbbaaadd3bcfd967.e686c4fdcb406732.35a9ceafd2e2aec4
+ b602c7a266815d1a.e592158f24400e74.dfdae1eabc617c99.524fccee06be57b0
+ 400d44cd6b46c6ea
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 6e07cf6c9d1b64a1.35553a15b6c5cd52.8a62352f2672fca9.0e52cf23b4a710fb
+ cdf9a5fdd4619ca3.fbbaaadd3bcfd967.e686c4fdcb406732.35a9ceafd2e2aec4
+ b602c7a266815d1a.e592158f24400e74.dfdae1eabc617c99.524fccee06be57b0
+ 400d44cd6b46c6ea
+VPCMPEQD_128(mem)
+ before
+ dbb2b3391d86b89e.856f30c8ef06e0af.ceaaf9178d2227a6.cfab87629662768a
+ fe09931c398be9f9.968adddb0a7d6411.92ced1619083e128.1345b2d1f5cf93b0
+ 87dd6264db601527.459fc848547124ea.0cca19594c6ff827.08f45fa473320db7
+ 51fb9bfc1e11f753.eefcef7a686e5be6.1a6a4debdaf028ce.08048945af19204d
+ 70c12b2242100a1b
+ after
+ dbb2b3391d86b89e.856f30c8ef06e0af.ceaaf9178d2227a6.cfab87629662768a
+ fe09931c398be9f9.968adddb0a7d6411.92ced1619083e128.1345b2d1f5cf93b0
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 51fb9bfc1e11f753.eefcef7a686e5be6.1a6a4debdaf028ce.08048945af19204d
+ 70c12b2242100a1b
+
+VPCMPEQD_128(reg)
+ before
+ 9d7644a6cba105d0.3730bacf1eab4daa.ecec4ddce20045b2.977aea0359142c4b
+ e970cd3de35a4e16.17453bcbf839d058.9dbadedc5fb420fa.5ec66b8ee2e7c1c7
+ b1fcc35228c7219a.cc099bdbc8c73f88.5cb39fe57b152669.4d194c769473a371
+ 516423533673b907.314755eca9625466.84238a63d0b094ac.3e4009a988c78d73
+ 0f071e11dcec3cf9
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ e970cd3de35a4e16.17453bcbf839d058.9dbadedc5fb420fa.5ec66b8ee2e7c1c7
+ b1fcc35228c7219a.cc099bdbc8c73f88.5cb39fe57b152669.4d194c769473a371
+ 516423533673b907.314755eca9625466.84238a63d0b094ac.3e4009a988c78d73
+ 0f071e11dcec3cf9
+VPCMPEQD_128(mem)
+ before
+ 9a3a089cacf06c30.25f4e8aca8ea530a.24cae5e8b715cc20.73569dc2fd10a66f
+ bda5423513ded944.89fa0ec71bb82b4e.7f60c7bc0fed63e0.8498d36e9cc1975d
+ 521348c82dc23e60.d9c192112a6a7c80.20d37854ccf5d4d2.123429d34950a423
+ 3752964117a958b1.71946ef6718b834c.e1f0729d0b39dd23.7b78995ea148096c
+ 19ae21793f3502e5
+ after
+ 9a3a089cacf06c30.25f4e8aca8ea530a.24cae5e8b715cc20.73569dc2fd10a66f
+ bda5423513ded944.89fa0ec71bb82b4e.7f60c7bc0fed63e0.8498d36e9cc1975d
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 3752964117a958b1.71946ef6718b834c.e1f0729d0b39dd23.7b78995ea148096c
+ 19ae21793f3502e5
+
+VPEXTRD_128_0x3(reg)
+ before
+ 4a23bc92c0a3ca39.462ca98ced9ee362.adc0a0e38da77c5d.9f833381e7c537ff
+ 68236613bf1f9e15.5c6efc95caae9aa0.e99123421a4ba360.375837ee7da6a191
+ d1fa1c6ad835ba25.56e40b49cae43a97.8153f481b3023300.833af8cfe8e7d506
+ dff4d802a96f5914.0e5a52920a4c7f72.d1520d0bf45969ea.60f6f31044959089
+ ab59a59dafba8e47
+ after
+ 4a23bc92c0a3ca39.462ca98ced9ee362.adc0a0e38da77c5d.9f833381e7c537ff
+ 68236613bf1f9e15.5c6efc95caae9aa0.e99123421a4ba360.375837ee7da6a191
+ d1fa1c6ad835ba25.56e40b49cae43a97.8153f481b3023300.833af8cfe8e7d506
+ dff4d802a96f5914.0e5a52920a4c7f72.d1520d0bf45969ea.60f6f31044959089
+ 00000000adc0a0e3
+VPEXTRD_128_0x3(mem)
+ before
+ 3e2d896242658b6c.ef5c9847cb5bb98f.619c4d5ea5f2255e.35d96c4c7ada81c9
+ f63f1c4b1b9f4223.5e7f57a5dc851342.2b757997b8e3e787.09360cb0e014b74b
+ af5ad84456767099.86aa11887877a6d8.49b3512b5e2a8218.a9b3e9a3c3904619
+ 454c3b390ef5d0f9.c427c35c3abfacfd.95205105b4d4b23d.719d0091bedc6be2
+ bc404be66e836250
+ after
+ 3e2d896242658b6c.ef5c9847cb5bb98f.619c4d5ea5f2255e.35d96c4c49b3512b
+ f63f1c4b1b9f4223.5e7f57a5dc851342.2b757997b8e3e787.09360cb0e014b74b
+ af5ad84456767099.86aa11887877a6d8.49b3512b5e2a8218.a9b3e9a3c3904619
+ 454c3b390ef5d0f9.c427c35c3abfacfd.95205105b4d4b23d.719d0091bedc6be2
+ bc404be66e836250
+
+VPEXTRD_128_0x3(reg)
+ before
+ e8e8c80e6e12660f.94e0c0175f292071.7443688dbee9625e.ec89f510d5ec3223
+ 50e072765b13b4cc.78e1e3c8661d1a2a.f349fc88a17f04a7.2ababa3ade7ec0f6
+ 4f764588d0158833.cd1c203a3edd7a52.9b877bb77e0fce84.2b7e1a6eea9715e2
+ 43f43eb269a11eef.6f5df4580476fe15.c947e188f225fba0.cba393991642f012
+ e6f3a0a57d8b0bb2
+ after
+ e8e8c80e6e12660f.94e0c0175f292071.7443688dbee9625e.ec89f510d5ec3223
+ 50e072765b13b4cc.78e1e3c8661d1a2a.f349fc88a17f04a7.2ababa3ade7ec0f6
+ 4f764588d0158833.cd1c203a3edd7a52.9b877bb77e0fce84.2b7e1a6eea9715e2
+ 43f43eb269a11eef.6f5df4580476fe15.c947e188f225fba0.cba393991642f012
+ 000000007443688d
+VPEXTRD_128_0x3(mem)
+ before
+ 583cbe7f3c7e24ef.87a7575fc345b1ad.3a70d90ed4f3609e.d9d62b65994cc8a7
+ fd4867146e28f4f5.76db8efa7a8c7e19.0a204d47c8605d1a.278154bc0d107047
+ b1e4194e2f953af0.6edcdff12903c0de.bb3bccf1ffcab1b5.0f9158f8edfd3129
+ 50db4f1b9ccfb00a.c9f644af6c35b5a9.298bd0f8923b179a.ed553385d2a045fc
+ 1d18e1cf5b84e96a
+ after
+ 583cbe7f3c7e24ef.87a7575fc345b1ad.3a70d90ed4f3609e.d9d62b65bb3bccf1
+ fd4867146e28f4f5.76db8efa7a8c7e19.0a204d47c8605d1a.278154bc0d107047
+ b1e4194e2f953af0.6edcdff12903c0de.bb3bccf1ffcab1b5.0f9158f8edfd3129
+ 50db4f1b9ccfb00a.c9f644af6c35b5a9.298bd0f8923b179a.ed553385d2a045fc
+ 1d18e1cf5b84e96a
+
+VPEXTRD_128_0x3(reg)
+ before
+ fb255f422135581f.b5fb8666d0e41372.e575baa0e0ae9725.30ded746a0c24cf6
+ e3caa84ac240cfc8.be0f381ae8e01f52.1ca43e3121fba3ff.acfe5cc842680cf4
+ 3151b853da308a11.46e2e32500cd8fd7.cbd0cbcccaa715e2.79b7db6a963b13c1
+ 41078bca0492c5a6.2941027233b9202c.4f455ede773e287b.72d7d019b8471c89
+ 7529b7bfc397e477
+ after
+ fb255f422135581f.b5fb8666d0e41372.e575baa0e0ae9725.30ded746a0c24cf6
+ e3caa84ac240cfc8.be0f381ae8e01f52.1ca43e3121fba3ff.acfe5cc842680cf4
+ 3151b853da308a11.46e2e32500cd8fd7.cbd0cbcccaa715e2.79b7db6a963b13c1
+ 41078bca0492c5a6.2941027233b9202c.4f455ede773e287b.72d7d019b8471c89
+ 00000000e575baa0
+VPEXTRD_128_0x3(mem)
+ before
+ 5d780d4ad43726b8.6f381e19ddf1bb32.42f811ed9db08e7e.024ff1d4c54d1976
+ 05914da50633a077.162f6cae00d9a961.6fd38c835bbc95f9.413a82184f5f247e
+ 4b41f3bc75980ce1.943a71f409d6cbe0.8b9ef01e88ebf0c8.69510c18b2008440
+ 0a527c7a3e712721.44a3295695755d5b.7124b8ab41495c18.d4e28b3f89bd7667
+ df37fbf8712136a0
+ after
+ 5d780d4ad43726b8.6f381e19ddf1bb32.42f811ed9db08e7e.024ff1d48b9ef01e
+ 05914da50633a077.162f6cae00d9a961.6fd38c835bbc95f9.413a82184f5f247e
+ 4b41f3bc75980ce1.943a71f409d6cbe0.8b9ef01e88ebf0c8.69510c18b2008440
+ 0a527c7a3e712721.44a3295695755d5b.7124b8ab41495c18.d4e28b3f89bd7667
+ df37fbf8712136a0
+
+VPEXTRD_128_0x0(reg)
+ before
+ e69d59b105b80097.1d9062cd7ccaac64.81b790423f419a7d.ff326017a1e19514
+ 45609fd5e10f0ff7.62c923a14cb059d6.a9c2a323a4c7bff3.1095644cc4bf56e9
+ 59cccbd0a3b1a06d.b3c73ae0ca2ee8a2.17105d6560920869.7f174038c7ef5cc2
+ 7c2dd90fe42aefa4.ee582477105015f5.26edba740e2eb08a.2a8571c6c67e63cc
+ ebaa72e2dc772733
+ after
+ e69d59b105b80097.1d9062cd7ccaac64.81b790423f419a7d.ff326017a1e19514
+ 45609fd5e10f0ff7.62c923a14cb059d6.a9c2a323a4c7bff3.1095644cc4bf56e9
+ 59cccbd0a3b1a06d.b3c73ae0ca2ee8a2.17105d6560920869.7f174038c7ef5cc2
+ 7c2dd90fe42aefa4.ee582477105015f5.26edba740e2eb08a.2a8571c6c67e63cc
+ 00000000a1e19514
+VPEXTRD_128_0x0(mem)
+ before
+ 9f54bf7726e66322.0bcec3fc42073749.ed465b523d239efb.34a5b6bd4a28f403
+ 234dd474bfd8d4c6.62fd870459d3b608.8d5e5d5e6ab23ddf.9c834eaab10a107f
+ 51632ec2c358364b.dd041f94c41ba68c.ab6ca586b60aafce.b9d47da8de6340ab
+ 0660484e4f7344dc.d8308a161f694382.213cafb53a36aff3.e9e53f246ebcbf32
+ 86ff9089fca3cac1
+ after
+ 9f54bf7726e66322.0bcec3fc42073749.ed465b523d239efb.34a5b6bdde6340ab
+ 234dd474bfd8d4c6.62fd870459d3b608.8d5e5d5e6ab23ddf.9c834eaab10a107f
+ 51632ec2c358364b.dd041f94c41ba68c.ab6ca586b60aafce.b9d47da8de6340ab
+ 0660484e4f7344dc.d8308a161f694382.213cafb53a36aff3.e9e53f246ebcbf32
+ 86ff9089fca3cac1
+
+VPEXTRD_128_0x0(reg)
+ before
+ ed716c4224a49d04.1f119e047e34bba5.afcdc1f8074ccb95.cd99f7d91542fb7b
+ 7b86d0bd834973a6.7642acd16da757d4.be27c1a5174d7872.8950fadd603a4d91
+ 8a89b765b5208954.e8beee9f38d8d492.60898789ecfa86c5.322e33ad392b6262
+ 77c81da655b51bba.5253e15cf9d4ed0e.f3400e1021de3339.a4fd1e35bc20f51a
+ bb8a37610426c3e4
+ after
+ ed716c4224a49d04.1f119e047e34bba5.afcdc1f8074ccb95.cd99f7d91542fb7b
+ 7b86d0bd834973a6.7642acd16da757d4.be27c1a5174d7872.8950fadd603a4d91
+ 8a89b765b5208954.e8beee9f38d8d492.60898789ecfa86c5.322e33ad392b6262
+ 77c81da655b51bba.5253e15cf9d4ed0e.f3400e1021de3339.a4fd1e35bc20f51a
+ 000000001542fb7b
+VPEXTRD_128_0x0(mem)
+ before
+ 54a0fa1d2d4888ed.9f8dfeec00926583.8ecb00f2cfa75f72.d29952a65385b97b
+ 490de45654920060.5c2557a35145a25b.79f3c74fd35be6ea.59de50b71e7c5536
+ 779c70f69511e66a.0bdc2237e45a0fef.ef97b25e24fe3da4.e45c02af1c4e4317
+ ba181aeb0bcff737.08fe5d15565be8eb.cc833e0bdb9b22c9.ce5f66faeb88beca
+ 7532770527b503fa
+ after
+ 54a0fa1d2d4888ed.9f8dfeec00926583.8ecb00f2cfa75f72.d29952a61c4e4317
+ 490de45654920060.5c2557a35145a25b.79f3c74fd35be6ea.59de50b71e7c5536
+ 779c70f69511e66a.0bdc2237e45a0fef.ef97b25e24fe3da4.e45c02af1c4e4317
+ ba181aeb0bcff737.08fe5d15565be8eb.cc833e0bdb9b22c9.ce5f66faeb88beca
+ 7532770527b503fa
+
+VPEXTRD_128_0x0(reg)
+ before
+ 3423313a6b614e53.ee4e5e1fd2dbeff2.b0d603a742d668fb.ec83e542163f4e88
+ 667c91075419db83.ef0ab980073e89c8.5db2115b4557cdca.2b6225eff1f5800b
+ 698a92d77d68e534.9918a6f9c50683e4.6cdc819cfa685004.65ee79fe87c9727e
+ 9799301582daa912.c843a176293f9773.39a151d5fe983057.76f15e5cf5c8e20f
+ 3a384ef356fd89e7
+ after
+ 3423313a6b614e53.ee4e5e1fd2dbeff2.b0d603a742d668fb.ec83e542163f4e88
+ 667c91075419db83.ef0ab980073e89c8.5db2115b4557cdca.2b6225eff1f5800b
+ 698a92d77d68e534.9918a6f9c50683e4.6cdc819cfa685004.65ee79fe87c9727e
+ 9799301582daa912.c843a176293f9773.39a151d5fe983057.76f15e5cf5c8e20f
+ 00000000163f4e88
+VPEXTRD_128_0x0(mem)
+ before
+ 8d8fc7b1c6742635.4ef5672f00fb63ca.585926e34ef381a1.204d7c74ed70a76c
+ 4bc24480623a7323.e8ea339093584e08.2524b12c5130ff99.7d2cfee4617ef2f2
+ 509d414e46592ddd.c3c391a4d67da777.0a72bf3d4d01cb88.ac89d491f84d4d93
+ 77eb3b068ce01090.39ce7bd765f4aac4.e50dcb025f73a299.09b2f9e74e69f4fb
+ f0f16952fe5f22d7
+ after
+ 8d8fc7b1c6742635.4ef5672f00fb63ca.585926e34ef381a1.204d7c74f84d4d93
+ 4bc24480623a7323.e8ea339093584e08.2524b12c5130ff99.7d2cfee4617ef2f2
+ 509d414e46592ddd.c3c391a4d67da777.0a72bf3d4d01cb88.ac89d491f84d4d93
+ 77eb3b068ce01090.39ce7bd765f4aac4.e50dcb025f73a299.09b2f9e74e69f4fb
+ f0f16952fe5f22d7
+
+VINSERTF128_0x0(reg)
+ before
+ bd93203fa5ba14d3.9e79ad9453d8d768.a855ef96dd4b939b.91c15167a2913ff9
+ cce41a18de07069b.a01413e4b5503f90.6aa5e94bd90e9da7.ea5ccd5933675fd3
+ 7830544b46d033d9.5986e9e2ce510435.dc0a6363f6c70594.cca9bcc22d02be55
+ 1fc3c84278a4d83c.a49bab7abbe9e283.5bd05b4bcf040710.12739990ac6d18a8
+ 9a87e0aecdb528fb
+ after
+ bd93203fa5ba14d3.9e79ad9453d8d768.a855ef96dd4b939b.91c15167a2913ff9
+ bd93203fa5ba14d3.9e79ad9453d8d768.5bd05b4bcf040710.12739990ac6d18a8
+ 7830544b46d033d9.5986e9e2ce510435.dc0a6363f6c70594.cca9bcc22d02be55
+ 1fc3c84278a4d83c.a49bab7abbe9e283.5bd05b4bcf040710.12739990ac6d18a8
+ 9a87e0aecdb528fb
+VINSERTF128_0x0(mem)
+ before
+ 3fb20d08ace4ab78.1ce8746b100c316e.5f21d698972394a5.4142cc6e0151dec4
+ dcbe9c8a64085d4b.cbec5431ab96791c.64e3e4297f0bd7c8.ebaeb2372738c75f
+ 4f770a20112dfaa1.871c6200e4cdeef1.91ac53178eae6717.b55e0914de47fe8b
+ 72abd2b6d05e3da6.aec29c43583eca9a.c1499f50e117ffbf.fc9fce70c10abff5
+ 1abdfbb76d0b4548
+ after
+ 3fb20d08ace4ab78.1ce8746b100c316e.5f21d698972394a5.4142cc6e0151dec4
+ 4f770a20112dfaa1.871c6200e4cdeef1.5f21d698972394a5.4142cc6e0151dec4
+ 4f770a20112dfaa1.871c6200e4cdeef1.91ac53178eae6717.b55e0914de47fe8b
+ 72abd2b6d05e3da6.aec29c43583eca9a.c1499f50e117ffbf.fc9fce70c10abff5
+ 1abdfbb76d0b4548
+
+VINSERTF128_0x0(reg)
+ before
+ 6c048e557dd8cd31.23247038bca7e385.9b2bfd69a37449c3.cf8642bf93525ceb
+ 4ec083b68efd935b.3cb06092f214a86b.a9a281db5ffba917.992fba4fc06c3ac9
+ 1c3cd4473b05d373.9b191eb18db24784.367524062b5f2442.f91082ee85705582
+ 32c57f72207cc825.1a2c277faa8c7dfb.9ceee356a12df7f2.ccf41687fe6b6844
+ efa9f2064667303b
+ after
+ 6c048e557dd8cd31.23247038bca7e385.9b2bfd69a37449c3.cf8642bf93525ceb
+ 6c048e557dd8cd31.23247038bca7e385.9ceee356a12df7f2.ccf41687fe6b6844
+ 1c3cd4473b05d373.9b191eb18db24784.367524062b5f2442.f91082ee85705582
+ 32c57f72207cc825.1a2c277faa8c7dfb.9ceee356a12df7f2.ccf41687fe6b6844
+ efa9f2064667303b
+VINSERTF128_0x0(mem)
+ before
+ 3cf9935779736993.eca87fa5daeeaf1c.96b5f6ea64ae06fc.395bb8385df15dd1
+ 91b17366b498ce77.a62fd04a04e8c304.ec8007dcd8259eb4.6706a116fb35948b
+ c89d102013e41c13.bca76ecf3bf5428b.f658d74321fc004f.843c995e1987d6cd
+ be89e66fb0620f95.8a5b559f1ba1665b.910ae00a5c40e9f9.ea499d7b50735f43
+ f778a7d83e836d98
+ after
+ 3cf9935779736993.eca87fa5daeeaf1c.96b5f6ea64ae06fc.395bb8385df15dd1
+ c89d102013e41c13.bca76ecf3bf5428b.96b5f6ea64ae06fc.395bb8385df15dd1
+ c89d102013e41c13.bca76ecf3bf5428b.f658d74321fc004f.843c995e1987d6cd
+ be89e66fb0620f95.8a5b559f1ba1665b.910ae00a5c40e9f9.ea499d7b50735f43
+ f778a7d83e836d98
+
+VINSERTF128_0x0(reg)
+ before
+ 0517b5e37f453a79.4f416f41aa1f6327.6c9982253f796c20.9a63a01da4fc15dd
+ 7170c207ae440391.589029801b25d3f5.beabf0cf43088f88.eb2d9268163c4027
+ 98d0cbb0670d038e.b3448f1a1f831c2c.dbdf9b08c4db0c3c.613532d7cd0d2505
+ d483ca4b472b7819.3d271dfad342faf8.217f803d5d7d1feb.d846fd56e57981a1
+ 2c2e6dd27b8f0f27
+ after
+ 0517b5e37f453a79.4f416f41aa1f6327.6c9982253f796c20.9a63a01da4fc15dd
+ 0517b5e37f453a79.4f416f41aa1f6327.217f803d5d7d1feb.d846fd56e57981a1
+ 98d0cbb0670d038e.b3448f1a1f831c2c.dbdf9b08c4db0c3c.613532d7cd0d2505
+ d483ca4b472b7819.3d271dfad342faf8.217f803d5d7d1feb.d846fd56e57981a1
+ 2c2e6dd27b8f0f27
+VINSERTF128_0x0(mem)
+ before
+ 39b80035aa588dc4.82d5bd42ea2a9ce0.d2064f0c52702884.ebd899d8ab7a043f
+ dbaf316d8fe2b5a4.fe129f02eb97ac8f.4eada13cb81864fd.9535e446495ef6e4
+ efe07d64463843f2.a4856cf8e6fde3d2.8de790762347678e.7ae45cf4d3b63387
+ 4f175e08ea67f5db.d17c208e78e97e54.6b8297a6ac08f064.f82ffe4ce70ef4d4
+ 6a64c4bc1ef07876
+ after
+ 39b80035aa588dc4.82d5bd42ea2a9ce0.d2064f0c52702884.ebd899d8ab7a043f
+ efe07d64463843f2.a4856cf8e6fde3d2.d2064f0c52702884.ebd899d8ab7a043f
+ efe07d64463843f2.a4856cf8e6fde3d2.8de790762347678e.7ae45cf4d3b63387
+ 4f175e08ea67f5db.d17c208e78e97e54.6b8297a6ac08f064.f82ffe4ce70ef4d4
+ 6a64c4bc1ef07876
+
+VINSERTF128_0x1(reg)
+ before
+ 2bcdacae16eaf91a.d7205244977a858a.df41b8323ce5b9c1.c44832b87167b9ab
+ 99b7b1906b87b46c.65c6d4046a7db02c.2b212f4fcf7fd0c6.7407de988e71808e
+ 0e6ecfcdb854e517.d4d760347e7d32ec.11688150cc43fe0f.578915331e31fe3a
+ e83e02d199dcc7c7.001d73c0f085c6f8.ed62aaa3d0bc8048.499b55733db3f2da
+ 260819460804169b
+ after
+ 2bcdacae16eaf91a.d7205244977a858a.df41b8323ce5b9c1.c44832b87167b9ab
+ ed62aaa3d0bc8048.499b55733db3f2da.df41b8323ce5b9c1.c44832b87167b9ab
+ 0e6ecfcdb854e517.d4d760347e7d32ec.11688150cc43fe0f.578915331e31fe3a
+ e83e02d199dcc7c7.001d73c0f085c6f8.ed62aaa3d0bc8048.499b55733db3f2da
+ 260819460804169b
+VINSERTF128_0x1(mem)
+ before
+ ca9edd979b2f27a8.81724708abab982a.c5668794dba12979.1b5aa7b37676921c
+ 10281e521140e12f.375799de8a4e91ea.ff7c1a9c5cde179e.f79e72ed5bfd7037
+ d67157628644ff59.643af4c0d050f1b3.8a2ba7c48e474c91.dd7809bb1ade5546
+ f74603b517463e55.656554181c3df232.4141abf98de8837e.2835678a50a47ef5
+ 362189c698dc26f0
+ after
+ ca9edd979b2f27a8.81724708abab982a.c5668794dba12979.1b5aa7b37676921c
+ c5668794dba12979.1b5aa7b37676921c.8a2ba7c48e474c91.dd7809bb1ade5546
+ d67157628644ff59.643af4c0d050f1b3.8a2ba7c48e474c91.dd7809bb1ade5546
+ f74603b517463e55.656554181c3df232.4141abf98de8837e.2835678a50a47ef5
+ 362189c698dc26f0
+
+VINSERTF128_0x1(reg)
+ before
+ 628869dc8e108be1.4f73a137df525a4d.9725b55308a2d113.0289a02676ce7992
+ 08b60537cfcfe777.b9c4aad2fb750f6d.54c514de300aca01.a8ce04366504e9f9
+ 84f65842f7a2775c.13059c7386ba18e2.f9936c23310119a9.0ede5217759691de
+ 31965e6ba117763d.3801f1069d2d32d8.e3d9b990a614f9b6.128306b4c2912b6e
+ 8f8a9df9690074d5
+ after
+ 628869dc8e108be1.4f73a137df525a4d.9725b55308a2d113.0289a02676ce7992
+ e3d9b990a614f9b6.128306b4c2912b6e.9725b55308a2d113.0289a02676ce7992
+ 84f65842f7a2775c.13059c7386ba18e2.f9936c23310119a9.0ede5217759691de
+ 31965e6ba117763d.3801f1069d2d32d8.e3d9b990a614f9b6.128306b4c2912b6e
+ 8f8a9df9690074d5
+VINSERTF128_0x1(mem)
+ before
+ 60be91d286ef273e.6de0141d69b921c5.038527785bdb197a.6ce5f7902ccea7d5
+ 63ed602b346b02d6.932174c4ec15b4a1.525ebab3ddcf88f5.f101238f5ebb5eb2
+ 72e185f08f7fbfc8.fea57cccc6b66b7d.ff5624a53e153c75.ce7a38f9d8685cf8
+ 6b687c0db4381a41.0cb827a191288204.e83ae3399abaf125.5f9c323a3760db54
+ 00b20dbe172f1771
+ after
+ 60be91d286ef273e.6de0141d69b921c5.038527785bdb197a.6ce5f7902ccea7d5
+ 038527785bdb197a.6ce5f7902ccea7d5.ff5624a53e153c75.ce7a38f9d8685cf8
+ 72e185f08f7fbfc8.fea57cccc6b66b7d.ff5624a53e153c75.ce7a38f9d8685cf8
+ 6b687c0db4381a41.0cb827a191288204.e83ae3399abaf125.5f9c323a3760db54
+ 00b20dbe172f1771
+
+VINSERTF128_0x1(reg)
+ before
+ 0d0ac5f213624efc.284cc26fbea1d16c.18a572afecf734e2.e7d5725b0ec96331
+ e2ee5740c884baa1.875ad200cac69e76.7dba576370b0bec5.daf54df7b64f4dc7
+ dbabbe15d021980b.625e27aef3b33e8b.9941d427bcdf5b57.9b64f0f9ad576c11
+ 548df6decac624e7.9624406356756cd6.c687e469690e4844.07f0d84d0fed7c3b
+ fb637fdff91d3872
+ after
+ 0d0ac5f213624efc.284cc26fbea1d16c.18a572afecf734e2.e7d5725b0ec96331
+ c687e469690e4844.07f0d84d0fed7c3b.18a572afecf734e2.e7d5725b0ec96331
+ dbabbe15d021980b.625e27aef3b33e8b.9941d427bcdf5b57.9b64f0f9ad576c11
+ 548df6decac624e7.9624406356756cd6.c687e469690e4844.07f0d84d0fed7c3b
+ fb637fdff91d3872
+VINSERTF128_0x1(mem)
+ before
+ 518a639b87f45de2.a9e0fb0650fe99e0.0077960d0e17e684.62d8839316cbc139
+ e631ff6ed47da7b6.36f0caf8fe5634a3.7a25a79738a666c1.c780ad135ca102e2
+ 9623d042fcc5d21b.57095d22715931dc.e1f8ededef2ca9b8.52ca5f54d91d47ea
+ 3e2e51051cd7993c.6876b2ef4493cb36.11bde6fb4fb86a95.600494c229cacbfe
+ 4b7848c9e734cbc9
+ after
+ 518a639b87f45de2.a9e0fb0650fe99e0.0077960d0e17e684.62d8839316cbc139
+ 0077960d0e17e684.62d8839316cbc139.e1f8ededef2ca9b8.52ca5f54d91d47ea
+ 9623d042fcc5d21b.57095d22715931dc.e1f8ededef2ca9b8.52ca5f54d91d47ea
+ 3e2e51051cd7993c.6876b2ef4493cb36.11bde6fb4fb86a95.600494c229cacbfe
+ 4b7848c9e734cbc9
+
+VEXTRACTF128_0x0(reg)
+ before
+ 707377d5afe882f8.b81cfda24fbfb946.c584c4cb1490405e.e7400ead75536685
+ 2c421e521e712e37.e1ba5204b289ee65.c97f90227cddcaff.3d4ddfef7d0b59b4
+ d92e37acd05b0931.95d4cc196042f3c4.d2b310611905a5c6.f0afd7ae82ebff4e
+ d486c05060334f93.b036e5cc76f58690.3b6c42f286950f5f.dc3471d4a000137e
+ dda6294ff4555270
+ after
+ 707377d5afe882f8.b81cfda24fbfb946.c584c4cb1490405e.e7400ead75536685
+ 2c421e521e712e37.e1ba5204b289ee65.c97f90227cddcaff.3d4ddfef7d0b59b4
+ d92e37acd05b0931.95d4cc196042f3c4.d2b310611905a5c6.f0afd7ae82ebff4e
+ 0000000000000000.0000000000000000.c584c4cb1490405e.e7400ead75536685
+ dda6294ff4555270
+VEXTRACTF128_0x0(mem)
+ before
+ cfd27b0999f67851.7995b5a86a843e09.0eac1b090faf60f4.60f6214260184275
+ 8e84e4f0acf0404d.24a610228bdb103e.8b02e9bc477b401d.9c9caabe421a7bb4
+ f688dfef494e6890.3106cf285ec202de.0303cbd23c65e037.4dacd7d0c927f5ca
+ e3aae8f28a1caa45.fc01ec2880c75096.527c3d35077afe6d.cd70a6e690ccee61
+ 7a35126b3395a025
+ after
+ cfd27b0999f67851.7995b5a86a843e09.0303cbd23c65e037.4dacd7d0c927f5ca
+ 8e84e4f0acf0404d.24a610228bdb103e.8b02e9bc477b401d.9c9caabe421a7bb4
+ f688dfef494e6890.3106cf285ec202de.0303cbd23c65e037.4dacd7d0c927f5ca
+ e3aae8f28a1caa45.fc01ec2880c75096.527c3d35077afe6d.cd70a6e690ccee61
+ 7a35126b3395a025
+
+VEXTRACTF128_0x0(reg)
+ before
+ af4717cb4f0c47c3.31b57be58e66c298.e2e3658d8c763512.5439bcd2c6c553ec
+ c7f1b17280bf21e7.bc7614b46e396eb6.3df836c31f59eefe.e506c39695529edf
+ 1f81ddcc6139683c.60ba304b49a168cb.6a8c5936d4ffb705.e1afce6c8f2e9973
+ 144196458e07596f.f84b4a9638a86d02.c4eacc5248f1cbd3.2400593fd06401d4
+ 89c4e1fd7500922d
+ after
+ af4717cb4f0c47c3.31b57be58e66c298.e2e3658d8c763512.5439bcd2c6c553ec
+ c7f1b17280bf21e7.bc7614b46e396eb6.3df836c31f59eefe.e506c39695529edf
+ 1f81ddcc6139683c.60ba304b49a168cb.6a8c5936d4ffb705.e1afce6c8f2e9973
+ 0000000000000000.0000000000000000.e2e3658d8c763512.5439bcd2c6c553ec
+ 89c4e1fd7500922d
+VEXTRACTF128_0x0(mem)
+ before
+ eec8e091990f07ab.007ed849a4b42f2c.62f6de82595c3888.a95f8a8316bd6715
+ 2ed9d4e7599c1d79.41859f453ecc281e.798668f9c8c98689.74388f35dbeec777
+ 25c138ebd0b390c4.319fe7a3f9dc7ef1.19c965e9a0f91330.81bfd7d5321027a4
+ ae4c89891b611cb7.2d1badd1706f6d52.1d894f3cfefa9baa.2c405fcdb7b0c249
+ d109228b0759d612
+ after
+ eec8e091990f07ab.007ed849a4b42f2c.19c965e9a0f91330.81bfd7d5321027a4
+ 2ed9d4e7599c1d79.41859f453ecc281e.798668f9c8c98689.74388f35dbeec777
+ 25c138ebd0b390c4.319fe7a3f9dc7ef1.19c965e9a0f91330.81bfd7d5321027a4
+ ae4c89891b611cb7.2d1badd1706f6d52.1d894f3cfefa9baa.2c405fcdb7b0c249
+ d109228b0759d612
+
+VEXTRACTF128_0x0(reg)
+ before
+ cb651c7abe989caa.a74841ae55b17c7f.9244ec39401133ed.6394a4e0fdd8d922
+ 789f490577f853be.eb80de449baf6d48.ba65a049044f0a6e.c6b4dfc0b99e8ac5
+ 3304a59ace0535f9.55bfdb380868ab3d.02ccc56c59b42f80.21b67dc84f586abe
+ 58e02da4604c7f08.c3d2b477b9e7f18b.c6c3580edaccddcf.5265f9e4da12353b
+ 338fce0077d9a665
+ after
+ cb651c7abe989caa.a74841ae55b17c7f.9244ec39401133ed.6394a4e0fdd8d922
+ 789f490577f853be.eb80de449baf6d48.ba65a049044f0a6e.c6b4dfc0b99e8ac5
+ 3304a59ace0535f9.55bfdb380868ab3d.02ccc56c59b42f80.21b67dc84f586abe
+ 0000000000000000.0000000000000000.9244ec39401133ed.6394a4e0fdd8d922
+ 338fce0077d9a665
+VEXTRACTF128_0x0(mem)
+ before
+ a2ff7a0842b87a6b.427fdc8fc8576d97.0f85e6ecc939fc5e.6297549b24245209
+ 798079e855bb6d76.4f2daec7a3b53a51.17a4ec82556888e1.3393b57fd247c8d7
+ 96df458dcfef3ab5.d9369fb98def23e2.b5fb412778825141.9305772680c27ce8
+ d3e85ce1c95f9e52.3ee5accf209364f8.c75664c64e9312a9.df3896fccb1fa9e6
+ 73770f6e4fec8c7d
+ after
+ a2ff7a0842b87a6b.427fdc8fc8576d97.b5fb412778825141.9305772680c27ce8
+ 798079e855bb6d76.4f2daec7a3b53a51.17a4ec82556888e1.3393b57fd247c8d7
+ 96df458dcfef3ab5.d9369fb98def23e2.b5fb412778825141.9305772680c27ce8
+ d3e85ce1c95f9e52.3ee5accf209364f8.c75664c64e9312a9.df3896fccb1fa9e6
+ 73770f6e4fec8c7d
+
+VEXTRACTF128_0x1(reg)
+ before
+ ab0fdde6a7b5615b.0e6739d26218557a.d887cf76fb2c393d.2780ce4bf4a68846
+ e34cfcd26f056429.2128584ab3251b58.0568061bb747dd5d.b246fca286c76f43
+ 777a689d4468d096.e9f63537db92ab19.1fd44d29f26f8d05.45746bb81f0282cd
+ c2e51eb2c26ae24c.429f4d84f36bc2e8.84179e0b483085e1.bad69677db647e10
+ ee38f9ccd7f81f37
+ after
+ ab0fdde6a7b5615b.0e6739d26218557a.d887cf76fb2c393d.2780ce4bf4a68846
+ e34cfcd26f056429.2128584ab3251b58.0568061bb747dd5d.b246fca286c76f43
+ 777a689d4468d096.e9f63537db92ab19.1fd44d29f26f8d05.45746bb81f0282cd
+ 0000000000000000.0000000000000000.ab0fdde6a7b5615b.0e6739d26218557a
+ ee38f9ccd7f81f37
+VEXTRACTF128_0x1(mem)
+ before
+ bd6611a42ecb216f.22d8187f8398d6f7.09ed1b1d19bd1cf2.8e7df72f5417009c
+ 042b58e9fde83fe3.f2a1546f267de844.18ad1bee69937563.9b515300b3af3be3
+ 9d554c895f5b36c0.8e8aceee45a653df.4cabc9e3fefa8866.05e1aeea00847261
+ 65ae686f7131c232.52e080687c9d5474.81b3a1e9f4fd1228.29770459d723e1c3
+ 636051b9d517c3b5
+ after
+ bd6611a42ecb216f.22d8187f8398d6f7.9d554c895f5b36c0.8e8aceee45a653df
+ 042b58e9fde83fe3.f2a1546f267de844.18ad1bee69937563.9b515300b3af3be3
+ 9d554c895f5b36c0.8e8aceee45a653df.4cabc9e3fefa8866.05e1aeea00847261
+ 65ae686f7131c232.52e080687c9d5474.81b3a1e9f4fd1228.29770459d723e1c3
+ 636051b9d517c3b5
+
+VEXTRACTF128_0x1(reg)
+ before
+ 10e8927696ec55e2.380329874e749e64.9aef684968f127ae.939020ea68a8ced4
+ 8a5ac2fdb52fd3f7.f22009bd13338883.c10380fea42b0739.5f10c1d376077a97
+ 2e04ddb8ce6b79a0.6fd086fddb7739ba.2568c6f1ccd931c2.bffd00913927d09d
+ 5830e0157e2c8288.8be11b33c34e7036.216936907d86e1f5.90245a0ecd148c11
+ ae5149384fd86c20
+ after
+ 10e8927696ec55e2.380329874e749e64.9aef684968f127ae.939020ea68a8ced4
+ 8a5ac2fdb52fd3f7.f22009bd13338883.c10380fea42b0739.5f10c1d376077a97
+ 2e04ddb8ce6b79a0.6fd086fddb7739ba.2568c6f1ccd931c2.bffd00913927d09d
+ 0000000000000000.0000000000000000.10e8927696ec55e2.380329874e749e64
+ ae5149384fd86c20
+VEXTRACTF128_0x1(mem)
+ before
+ f5504bfada812af5.642cc57f60ff2b5b.221d444be6c3e723.1053ca4553bf527d
+ 41eddb408b1a83bd.ae428a61116fafc6.10527d3260e35cac.5073807ee90fc207
+ 6df375f67db033a4.92bf2a292c094c75.314a43d24eb988fe.3b1353a6dc026b3f
+ 572f9608cd4ef5d5.6ceea1424e573c14.61d21119cc512a44.2f7f3f29c72589d0
+ 8605407346035a66
+ after
+ f5504bfada812af5.642cc57f60ff2b5b.6df375f67db033a4.92bf2a292c094c75
+ 41eddb408b1a83bd.ae428a61116fafc6.10527d3260e35cac.5073807ee90fc207
+ 6df375f67db033a4.92bf2a292c094c75.314a43d24eb988fe.3b1353a6dc026b3f
+ 572f9608cd4ef5d5.6ceea1424e573c14.61d21119cc512a44.2f7f3f29c72589d0
+ 8605407346035a66
+
+VEXTRACTF128_0x1(reg)
+ before
+ 9ef053f0f62818af.da6eb8629600867d.981dec1812e8bc4e.7cb663f1f5b8fcab
+ d18b730c72200055.d27a59f0f5d3a2c7.72960517154507cf.5ec1b548e5f9bb5f
+ 7d239c3357784d04.1b20f49f05d205e0.56a7eaabf2fc5a44.e2c18409b920238b
+ fc04cad241bc3d69.912b0559e3096af4.a09a97414698f159.e6804a208c3aef5c
+ 45cb85797b52dcfd
+ after
+ 9ef053f0f62818af.da6eb8629600867d.981dec1812e8bc4e.7cb663f1f5b8fcab
+ d18b730c72200055.d27a59f0f5d3a2c7.72960517154507cf.5ec1b548e5f9bb5f
+ 7d239c3357784d04.1b20f49f05d205e0.56a7eaabf2fc5a44.e2c18409b920238b
+ 0000000000000000.0000000000000000.9ef053f0f62818af.da6eb8629600867d
+ 45cb85797b52dcfd
+VEXTRACTF128_0x1(mem)
+ before
+ db6eb000a274a69b.ab7af953ca760a30.0f69090caa858e2e.acbc0643aca508b9
+ 833548a11bad0962.e7d126249134f104.73a47ba276512cba.d659341fc0b0da11
+ 1becc7480508c07d.0a554caf30822d92.98aad709647a02c6.7abc1e3f1f44a40d
+ 7e5eabe279918818.7151676243eafb85.5945992c900aca7c.f333bf1165eea258
+ 9f0813002d39109f
+ after
+ db6eb000a274a69b.ab7af953ca760a30.1becc7480508c07d.0a554caf30822d92
+ 833548a11bad0962.e7d126249134f104.73a47ba276512cba.d659341fc0b0da11
+ 1becc7480508c07d.0a554caf30822d92.98aad709647a02c6.7abc1e3f1f44a40d
+ 7e5eabe279918818.7151676243eafb85.5945992c900aca7c.f333bf1165eea258
+ 9f0813002d39109f
+
+VCVTPD2PS_128(reg)
+ before
+ d989177813b1298d.87596f5995551c61.781273a866fa978a.94423df7150f4108
+ fc00c6e4b4e22acf.14a78f9b755f3a82.7ce46ded373e3d4d.236c40560f952297
+ 66b91bb3ab594f11.ff15889234bc9ca7.d713509d4f402879.e4911d359ba62b55
+ 7202154e95a2d3fe.266fd42cef77fffd.e6eb18244c8f95bb.b17c5080d451166d
+ 68f85523d79f9f0c
+ after
+ 0000000000000000.0000000000000000.0000000000000000.7f80000000000000
+ fc00c6e4b4e22acf.14a78f9b755f3a82.7ce46ded373e3d4d.236c40560f952297
+ 66b91bb3ab594f11.ff15889234bc9ca7.d713509d4f402879.e4911d359ba62b55
+ 7202154e95a2d3fe.266fd42cef77fffd.e6eb18244c8f95bb.b17c5080d451166d
+ 68f85523d79f9f0c
+VCVTPD2PS_128(mem)
+ before
+ e3d2a90bbf9e845e.7b26ad220e47f342.6380f154c19c1eb0.05b8c1eecab4c0be
+ 00d6c622a9597f8e.df70e09bb0d6eb8b.94165af6c637b7eb.90c54767643de42f
+ 99d02a56b0dc4dc8.f82dab261adaf783.93fc8cfe1b5584db.e360a7fcb6b53fba
+ 8b8c5092f134a93a.24aa092de5e052d6.3dfd0158dc0142ab.5ad3dc175da80b0a
+ 516be226f5a384cc
+ after
+ e3d2a90bbf9e845e.7b26ad220e47f342.6380f154c19c1eb0.05b8c1eecab4c0be
+ 00d6c622a9597f8e.df70e09bb0d6eb8b.94165af6c637b7eb.90c54767643de42f
+ 99d02a56b0dc4dc8.f82dab261adaf783.93fc8cfe1b5584db.e360a7fcb6b53fba
+ 0000000000000000.0000000000000000.0000000000000000.7f80000000000000
+ 516be226f5a384cc
+
+VCVTPD2PS_128(reg)
+ before
+ 2474b5931931e8ab.b3d5b5c1876c510d.bd31f61eaf733931.6fe637f02448ac88
+ 2f3a52cc65df7154.eb79d3d18f91ff70.210e6f64141fe840.0383a9b30f347f9e
+ ce08b43c76375b73.104228ad24ae708d.aa8f6e6aaf719aae.d6a0d38bbad47718
+ 5c2cd74fe7c8e4b3.fffd2f4163cf5f91.b5fff19e1df48c28.c508326540315023
+ aa89402ebe59c5eb
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 2f3a52cc65df7154.eb79d3d18f91ff70.210e6f64141fe840.0383a9b30f347f9e
+ ce08b43c76375b73.104228ad24ae708d.aa8f6e6aaf719aae.d6a0d38bbad47718
+ 5c2cd74fe7c8e4b3.fffd2f4163cf5f91.b5fff19e1df48c28.c508326540315023
+ aa89402ebe59c5eb
+VCVTPD2PS_128(mem)
+ before
+ 62ed7bd14f57939b.37f0b771551b46c1.92766479670089a7.9fa9f36bf934fa59
+ c9015e3a1038765f.baa1500e5bbebe48.a67944424c4eaafc.c2da713ddfbe20ee
+ bb9165541c072964.418b9f92963c88f5.17d14a862fc57ebb.7bde65816c1d3993
+ 14690d0d90d069d6.28fa9f6aa122df73.c14cf1322c6fc011.2601cda13cdd82f3
+ 208fa40aea8b37bb
+ after
+ 62ed7bd14f57939b.37f0b771551b46c1.92766479670089a7.9fa9f36bf934fa59
+ c9015e3a1038765f.baa1500e5bbebe48.a67944424c4eaafc.c2da713ddfbe20ee
+ bb9165541c072964.418b9f92963c88f5.17d14a862fc57ebb.7bde65816c1d3993
+ 0000000000000000.0000000000000000.0000000000000000.8000000080000000
+ 208fa40aea8b37bb
+
+VCVTPD2PS_128(reg)
+ before
+ c3d3e62912b29397.b055d150879ff2e1.ca394c0019fa0070.80b4b8335d5a2d2a
+ 6c1b8f6851ded332.6b212d0a1e8180b0.8596a2c299532795.30d61873e1918131
+ 77b19c35429c3338.21989d257082ce6f.b35b9d1abdb69091.ad7e8ee0d2217753
+ 40e208fb8277ef56.ae879d8e99ac994b.b2d53a7623b1760e.d37897654c15cdbb
+ 7e90aeee6c793d96
+ after
+ 0000000000000000.0000000000000000.0000000000000000.8000000000000000
+ 6c1b8f6851ded332.6b212d0a1e8180b0.8596a2c299532795.30d61873e1918131
+ 77b19c35429c3338.21989d257082ce6f.b35b9d1abdb69091.ad7e8ee0d2217753
+ 40e208fb8277ef56.ae879d8e99ac994b.b2d53a7623b1760e.d37897654c15cdbb
+ 7e90aeee6c793d96
+VCVTPD2PS_128(mem)
+ before
+ 8a914f674d5a8310.23facf25acfc4238.eebaaa32b60d9d70.dd50744164cf16b8
+ d348f7bc0cc35d54.7c45ed215db5698a.bdfd3ffbe3b0960a.8f1847e71e9dac3c
+ 358221d9c4c0858e.a70e5e5a3030a0f7.f71cd8d73ba23f44.2679afd4eda67346
+ 8c0948aa925eb7ec.00a31f3dc2f9232b.78e3f1b0daee554a.fcbea9746b76a881
+ 6f353033379a879a
+ after
+ 8a914f674d5a8310.23facf25acfc4238.eebaaa32b60d9d70.dd50744164cf16b8
+ d348f7bc0cc35d54.7c45ed215db5698a.bdfd3ffbe3b0960a.8f1847e71e9dac3c
+ 358221d9c4c0858e.a70e5e5a3030a0f7.f71cd8d73ba23f44.2679afd4eda67346
+ 0000000000000000.0000000000000000.0000000000000000.ff800000ff800000
+ 6f353033379a879a
+
+VCMPSS_128_0x0(reg)
+ before
+ d928407deb9d4c3c.b3aaeb1c91a8b198.e34e2b34ae9b2dd3.1c1d0674dda09449
+ 97e4d5be230b3215.88308319ddaa2dbe.ac5c7eac91a2fb9b.be97940e60c5b76d
+ 06b5ec637c7176ce.e6698d8f9371e88b.b7191411069ac92e.3c1e166a7d687be1
+ 80e77fd6915a5415.a81f8668cf089e2b.60d1ead0a910d239.717c087453959cd2
+ 387de719fb59d66c
+ after
+ 0000000000000000.0000000000000000.ac5c7eac91a2fb9b.be97940e00000000
+ 97e4d5be230b3215.88308319ddaa2dbe.ac5c7eac91a2fb9b.be97940e60c5b76d
+ 06b5ec637c7176ce.e6698d8f9371e88b.b7191411069ac92e.3c1e166a7d687be1
+ 80e77fd6915a5415.a81f8668cf089e2b.60d1ead0a910d239.717c087453959cd2
+ 387de719fb59d66c
+VCMPSS_128_0x0(mem)
+ before
+ 6fef2d4394bfe4da.62c58c85ff520796.ac20e992ac7b0ac9.02d0fb54178f5368
+ f19d58df37d48349.089d0edb61e6ccfd.cd3632f846d7e992.fb614308eca48866
+ 9952e3da03a26ee4.cfb9024454a1dff5.e62ede86ba27f7b2.a6d2be5ac3daace0
+ 45db4a1e113763d8.1166622b730f7c2a.d5d367282477f054.5f6d68b538bdfd81
+ 817f3e85e8d9b5f6
+ after
+ 6fef2d4394bfe4da.62c58c85ff520796.ac20e992ac7b0ac9.02d0fb54178f5368
+ f19d58df37d48349.089d0edb61e6ccfd.cd3632f846d7e992.fb614308eca48866
+ 0000000000000000.0000000000000000.cd3632f846d7e992.fb61430800000000
+ 45db4a1e113763d8.1166622b730f7c2a.d5d367282477f054.5f6d68b538bdfd81
+ 817f3e85e8d9b5f6
+
+VCMPSS_128_0x0(reg)
+ before
+ 6a543b366ebb10eb.cf040a997f9f1c50.2bf02cfe5bbdde4a.74f34bca9fd48fa5
+ 74375b3467ee4c0b.15999d3669e55679.79a35b29a73642fe.a1590558474991d0
+ fd769aeb6effa302.f16681e0ea15cc7f.57cbeb16f306e4f5.36d011bf39e3b202
+ 605bf5c82079527e.413731851f3b3c8d.21b3d932dcba00d9.1125ece990acad66
+ 0c2411c369b33f29
+ after
+ 0000000000000000.0000000000000000.79a35b29a73642fe.a159055800000000
+ 74375b3467ee4c0b.15999d3669e55679.79a35b29a73642fe.a1590558474991d0
+ fd769aeb6effa302.f16681e0ea15cc7f.57cbeb16f306e4f5.36d011bf39e3b202
+ 605bf5c82079527e.413731851f3b3c8d.21b3d932dcba00d9.1125ece990acad66
+ 0c2411c369b33f29
+VCMPSS_128_0x0(mem)
+ before
+ 0599fc3adf012477.f834673518e89429.dfd72a10236460d0.33a91fe9feddd156
+ d65029390fa4187b.234beca0f3d9a7af.a813e66e129bf574.e9f7bba8f4fc941a
+ 5c1414ab14a7d662.3bed80734cd7c5bd.79b7e38909edb6a4.9feaa8da5aa184ce
+ 74b33a7e0b171b58.9d661f1cc06e2aff.2c8f9c4e2364608c.b1cee2eacd5bdf21
+ 7bee6646e8b3dfbd
+ after
+ 0599fc3adf012477.f834673518e89429.dfd72a10236460d0.33a91fe9feddd156
+ d65029390fa4187b.234beca0f3d9a7af.a813e66e129bf574.e9f7bba8f4fc941a
+ 0000000000000000.0000000000000000.a813e66e129bf574.e9f7bba800000000
+ 74b33a7e0b171b58.9d661f1cc06e2aff.2c8f9c4e2364608c.b1cee2eacd5bdf21
+ 7bee6646e8b3dfbd
+
+VCMPSS_128_0x0(reg)
+ before
+ 59982f594837c14e.f8f7159d0ffea388.a601c606ea2b1420.9e678daa7d0faf5a
+ a716398f8972c081.c5ad24f43c6b291e.b00c709d6799bdcd.ac0b328733f75f37
+ c1b6805445f01902.b7a1e06faf676b48.18d1194dd24462b1.304608d35f2a2b52
+ 02c200141b3e087c.aa9fc6fb8400232f.3b9dbd82c7b93e79.07e68a7820b3d0d5
+ 0db534648f9f0aec
+ after
+ 0000000000000000.0000000000000000.b00c709d6799bdcd.ac0b328700000000
+ a716398f8972c081.c5ad24f43c6b291e.b00c709d6799bdcd.ac0b328733f75f37
+ c1b6805445f01902.b7a1e06faf676b48.18d1194dd24462b1.304608d35f2a2b52
+ 02c200141b3e087c.aa9fc6fb8400232f.3b9dbd82c7b93e79.07e68a7820b3d0d5
+ 0db534648f9f0aec
+VCMPSS_128_0x0(mem)
+ before
+ 1e808282cbf994c5.c887b63ba4e7c99c.7b725382d6410d02.73bc59a8e3838fd1
+ 1613f1beedcd2b89.6e509d357f78970e.04e802f1c137e7eb.1d7ae72bc22e8f64
+ d13afc0413288b67.506bb16f457cb07d.22cb4f3562ed6b16.95236578ff477bdf
+ 2bc01f4059147089.c923ee53947f4d96.b1e8b639d46f55b1.3802cef936598eed
+ 60651f1c04f0053c
+ after
+ 1e808282cbf994c5.c887b63ba4e7c99c.7b725382d6410d02.73bc59a8e3838fd1
+ 1613f1beedcd2b89.6e509d357f78970e.04e802f1c137e7eb.1d7ae72bc22e8f64
+ 0000000000000000.0000000000000000.04e802f1c137e7eb.1d7ae72b00000000
+ 2bc01f4059147089.c923ee53947f4d96.b1e8b639d46f55b1.3802cef936598eed
+ 60651f1c04f0053c
+
+VCMPSS_128_0x1(reg)
+ before
+ 6a96524b04991c75.0073d65edaa0951b.37c3504f080ead04.8d0bb4e834ca63e5
+ b2e265f4d3df0f46.2c1d9d4bb3d5b74b.f498d4ce3cb40a74.9200c4309e084fe1
+ 949553820c4e195b.8b8bf1f1ffc19242.5eee753bcdfda192.9c9362fc2c38d6cf
+ 6cfb19614c73775f.f9894d3eda70e22f.cf112f045675ae09.878f0a38fd63b4db
+ 2ec138d02a97a432
+ after
+ 0000000000000000.0000000000000000.f498d4ce3cb40a74.9200c430ffffffff
+ b2e265f4d3df0f46.2c1d9d4bb3d5b74b.f498d4ce3cb40a74.9200c4309e084fe1
+ 949553820c4e195b.8b8bf1f1ffc19242.5eee753bcdfda192.9c9362fc2c38d6cf
+ 6cfb19614c73775f.f9894d3eda70e22f.cf112f045675ae09.878f0a38fd63b4db
+ 2ec138d02a97a432
+VCMPSS_128_0x1(mem)
+ before
+ 6ff669b0d2e06300.9660b1fd2ed965ff.52e32d1c61ec623c.a54dff9473a96c85
+ 25f818c40e48ad71.6e0f19c24f0d1ee7.72640d79af43cf95.3aeddf57c12519b4
+ 2c94c1f9fcdd3eaf.50554c1c4a9ae0c2.35da6940e181e567.ec3fcdbadb73ee3f
+ 6095e039b8abd1e9.987e4677bc0ce53d.760fbe5d13b05fde.158dc4275e212ad5
+ 1324c00be6bb0720
+ after
+ 6ff669b0d2e06300.9660b1fd2ed965ff.52e32d1c61ec623c.a54dff9473a96c85
+ 25f818c40e48ad71.6e0f19c24f0d1ee7.72640d79af43cf95.3aeddf57c12519b4
+ 0000000000000000.0000000000000000.72640d79af43cf95.3aeddf57ffffffff
+ 6095e039b8abd1e9.987e4677bc0ce53d.760fbe5d13b05fde.158dc4275e212ad5
+ 1324c00be6bb0720
+
+VCMPSS_128_0x1(reg)
+ before
+ 4050bed30dcbc2cd.9cc9f2725dbc2349.a2d6034040ef6903.13d087bc60defa26
+ f95db8e972df9787.befa718e081eeffc.c9a980e172d0aac1.e7e94049e4177269
+ 9b96acbbae82c2fb.a1f6db7bd4ddf32d.6b43b7c8ef3ae223.cd2665f0bc6583d6
+ 804995b460417ed4.2087ac24dd04e909.e3efa66053ba4ed4.a353739d03d6e897
+ 443be53dd6765ed9
+ after
+ 0000000000000000.0000000000000000.c9a980e172d0aac1.e7e94049ffffffff
+ f95db8e972df9787.befa718e081eeffc.c9a980e172d0aac1.e7e94049e4177269
+ 9b96acbbae82c2fb.a1f6db7bd4ddf32d.6b43b7c8ef3ae223.cd2665f0bc6583d6
+ 804995b460417ed4.2087ac24dd04e909.e3efa66053ba4ed4.a353739d03d6e897
+ 443be53dd6765ed9
+VCMPSS_128_0x1(mem)
+ before
+ 8bac37ba5050a0c7.05c0703f21a708bf.197a5e75409f8ebc.8dfb491439db2981
+ 5670e5028d706c8e.864837ca8f419b68.669a6f5a18ba9d71.c4b19a523d29b0d5
+ 7f546bffabe27c59.5f2de8c04699757a.e5b559bf8262d454.e65e9785fc301f7d
+ e424469fc3b38d56.ecbb7e8de13dd0a2.71969b909aa2ed93.4e4e3b19117db224
+ 57cd827a199ba578
+ after
+ 8bac37ba5050a0c7.05c0703f21a708bf.197a5e75409f8ebc.8dfb491439db2981
+ 5670e5028d706c8e.864837ca8f419b68.669a6f5a18ba9d71.c4b19a523d29b0d5
+ 0000000000000000.0000000000000000.669a6f5a18ba9d71.c4b19a5200000000
+ e424469fc3b38d56.ecbb7e8de13dd0a2.71969b909aa2ed93.4e4e3b19117db224
+ 57cd827a199ba578
+
+VCMPSS_128_0x1(reg)
+ before
+ 5f266815af173322.5facf1cdf3ee5aae.8a3df59efdb9e88b.e508aeba7a86a458
+ c0a7ea54707c98d1.ceb7e875579fa190.93014a5d3598fbe2.1ed80f27411bb7cf
+ d89a02a4f756122e.0b13a7830ad31c25.6451773725664353.f9d23bc4096ce025
+ 014cae72e132dbe8.f38aabe32895889c.597a7a996aaffd89.50c2ad7eee86dc86
+ 0174e1400c74661d
+ after
+ 0000000000000000.0000000000000000.93014a5d3598fbe2.1ed80f2700000000
+ c0a7ea54707c98d1.ceb7e875579fa190.93014a5d3598fbe2.1ed80f27411bb7cf
+ d89a02a4f756122e.0b13a7830ad31c25.6451773725664353.f9d23bc4096ce025
+ 014cae72e132dbe8.f38aabe32895889c.597a7a996aaffd89.50c2ad7eee86dc86
+ 0174e1400c74661d
+VCMPSS_128_0x1(mem)
+ before
+ e6b353f681423c17.9909ea29c99b30a9.63e96f81cef2a01f.cec94eeda0006531
+ dc4d808b66fc189f.fa1db0344c1d4d1e.35fc6f4a17f521db.1e87f0a162e4b6f6
+ bf0ce3edd9afb7e2.82d4fe0105456ef2.468f272820aac7fb.a7035a204ce72d85
+ 6cbdf807f666d40c.8b79cefb919eced2.736d1309051d4eac.c4888ad6fb96068a
+ d1617b2f0a7c7cb0
+ after
+ e6b353f681423c17.9909ea29c99b30a9.63e96f81cef2a01f.cec94eeda0006531
+ dc4d808b66fc189f.fa1db0344c1d4d1e.35fc6f4a17f521db.1e87f0a162e4b6f6
+ 0000000000000000.0000000000000000.35fc6f4a17f521db.1e87f0a100000000
+ 6cbdf807f666d40c.8b79cefb919eced2.736d1309051d4eac.c4888ad6fb96068a
+ d1617b2f0a7c7cb0
+
+VCMPSS_128_0x2(reg)
+ before
+ 2adb29971626cda4.bd2c3bc6d82e2c48.72591e8e8bb4aa69.9664b0d7e05b7119
+ 2b42907aba1f3311.8f2529149b127bc3.94c1ea268f143d64.8c3e7980d06fed6f
+ 2fe2ad4493f3eaa4.be733cde5c1e7da8.4bfb2c2f3a49c56f.31c8eaefee667eda
+ 94077b613c2e3008.26e4f211375eed24.f453e21628df7c35.61ce7f10594bdf85
+ f81cb5cf2a2acd9d
+ after
+ 0000000000000000.0000000000000000.94c1ea268f143d64.8c3e798000000000
+ 2b42907aba1f3311.8f2529149b127bc3.94c1ea268f143d64.8c3e7980d06fed6f
+ 2fe2ad4493f3eaa4.be733cde5c1e7da8.4bfb2c2f3a49c56f.31c8eaefee667eda
+ 94077b613c2e3008.26e4f211375eed24.f453e21628df7c35.61ce7f10594bdf85
+ f81cb5cf2a2acd9d
+VCMPSS_128_0x2(mem)
+ before
+ d27e06188010044d.b5fdf63e525d3feb.a342c69747df8863.eb170745f4639e63
+ cbc0f0d7740840c2.ed0f1a45700b54f6.115a355ea8ad0a90.8c9297293a6069a4
+ bfadeff8241e3c28.9a8be4e432c5aad8.4cf8b95077d22ed8.340f8e2f976217a5
+ 8a127d67ac5eb5aa.17bb4e8635167e3a.30e8d05bcf5cb266.3ddbe9c2a6f6e512
+ 0442a34d04a70f96
+ after
+ d27e06188010044d.b5fdf63e525d3feb.a342c69747df8863.eb170745f4639e63
+ cbc0f0d7740840c2.ed0f1a45700b54f6.115a355ea8ad0a90.8c9297293a6069a4
+ 0000000000000000.0000000000000000.115a355ea8ad0a90.8c92972900000000
+ 8a127d67ac5eb5aa.17bb4e8635167e3a.30e8d05bcf5cb266.3ddbe9c2a6f6e512
+ 0442a34d04a70f96
+
+VCMPSS_128_0x2(reg)
+ before
+ e590b83e4c01d0de.08bb181127d56775.bfec5696158a0ccb.99f6f56acd565067
+ 3c1124001b916595.15743ae0b18f0eb4.f06af7826dae9035.63eda4698ccdc407
+ 6511e4ff0ce20a68.8d0961c267966594.04802eb5d90d4625.6a9a5a4429cccc71
+ bcdbf2a7bc81fa03.4c4609a265f82941.597cf59bf6336946.8aca91e7bf5f22d2
+ 9f47c73f6b938255
+ after
+ 0000000000000000.0000000000000000.f06af7826dae9035.63eda469ffffffff
+ 3c1124001b916595.15743ae0b18f0eb4.f06af7826dae9035.63eda4698ccdc407
+ 6511e4ff0ce20a68.8d0961c267966594.04802eb5d90d4625.6a9a5a4429cccc71
+ bcdbf2a7bc81fa03.4c4609a265f82941.597cf59bf6336946.8aca91e7bf5f22d2
+ 9f47c73f6b938255
+VCMPSS_128_0x2(mem)
+ before
+ 84de77364873aa27.9dbd4c64c6f87211.2ef6ac6bc6c116e6.49a84aa060ad3645
+ 175a1eb9730b5474.6301eda3c6d6ae3f.0ee7c80ba6fbe7af.32522831b206e8cd
+ 338936b507683d67.6cf4d2ce5aa4ea38.cae3d86d22b459ca.6ec48bb888cabd8b
+ b4353d152095212d.13e2f5531bf061a9.3db7587d55f82861.5a4b70a27f86ef2b
+ 5332d25c32c5ba58
+ after
+ 84de77364873aa27.9dbd4c64c6f87211.2ef6ac6bc6c116e6.49a84aa060ad3645
+ 175a1eb9730b5474.6301eda3c6d6ae3f.0ee7c80ba6fbe7af.32522831b206e8cd
+ 0000000000000000.0000000000000000.0ee7c80ba6fbe7af.32522831ffffffff
+ b4353d152095212d.13e2f5531bf061a9.3db7587d55f82861.5a4b70a27f86ef2b
+ 5332d25c32c5ba58
+
+VCMPSS_128_0x2(reg)
+ before
+ b3c7ac513e135cbf.752caec4db9ebbf1.b416549ca745513e.432fc4285cd110a0
+ d754fdec3efd0f0c.543805b05490c8e0.abdeea179a30f3a2.b7169958524eccb4
+ 1b27be9bcf0e10ea.2b26bec4a6760425.5384b32f8f3b8682.773a52fa547819c9
+ db8aecc98cd29a05.d8c156eced5d2bed.0a55ac5022f54489.5d656bfb7d5db20a
+ 47646045ea0855a4
+ after
+ 0000000000000000.0000000000000000.abdeea179a30f3a2.b7169958ffffffff
+ d754fdec3efd0f0c.543805b05490c8e0.abdeea179a30f3a2.b7169958524eccb4
+ 1b27be9bcf0e10ea.2b26bec4a6760425.5384b32f8f3b8682.773a52fa547819c9
+ db8aecc98cd29a05.d8c156eced5d2bed.0a55ac5022f54489.5d656bfb7d5db20a
+ 47646045ea0855a4
+VCMPSS_128_0x2(mem)
+ before
+ 0f03adc6b685bcc3.74ca84e211d6eb0a.36d74814464ff864.2b9dcfe6f0e76a64
+ 930ecf69fde1a492.40338152fca53da5.20331028cc5b28b5.11a81a5d949f34be
+ ad51411adc27c83d.9c10df85e6cbcd82.74a02a159c8a770d.1ac28821aba8dd45
+ 3b987fc56f64e6f2.e4af9be86dd5d64c.0ceb13c5d1eaa098.a137169ed08fa2a2
+ 0152be40a0dfbf84
+ after
+ 0f03adc6b685bcc3.74ca84e211d6eb0a.36d74814464ff864.2b9dcfe6f0e76a64
+ 930ecf69fde1a492.40338152fca53da5.20331028cc5b28b5.11a81a5d949f34be
+ 0000000000000000.0000000000000000.20331028cc5b28b5.11a81a5d00000000
+ 3b987fc56f64e6f2.e4af9be86dd5d64c.0ceb13c5d1eaa098.a137169ed08fa2a2
+ 0152be40a0dfbf84
+
+VCMPSS_128_0x3(reg)
+ before
+ 98607e74b6247094.17ae0556d1a2b8db.745aafe52d4e95af.c5e0452688866081
+ c0ad51a4afebf081.1f6050b91eeffb24.a85e19eac1c24658.7c4b3e22dc6a73f5
+ d785333e26bf7cf5.2d7adbda73576afa.dc07d461c5be25f3.0bf879a7eaa3951f
+ 373421adb82c509d.1ec822a5ece5c289.6ca1ddb8d6cd6d2c.4fb273a0cd3c812c
+ 2547a6f8a242f447
+ after
+ 0000000000000000.0000000000000000.a85e19eac1c24658.7c4b3e2200000000
+ c0ad51a4afebf081.1f6050b91eeffb24.a85e19eac1c24658.7c4b3e22dc6a73f5
+ d785333e26bf7cf5.2d7adbda73576afa.dc07d461c5be25f3.0bf879a7eaa3951f
+ 373421adb82c509d.1ec822a5ece5c289.6ca1ddb8d6cd6d2c.4fb273a0cd3c812c
+ 2547a6f8a242f447
+VCMPSS_128_0x3(mem)
+ before
+ 6781909d84c0aa9d.3d06155c00bfa724.ce16a107a4a5bffc.b4782e5a8f7c5bae
+ f22dac7a90c25e5a.46460db99b03be37.1a30d4eab7a31d80.10d7c5b28d562b25
+ a217767ce154cea9.ac42042f2484d181.dce1383c42ec9740.db0c9d2e6be7193e
+ 540b6b8d9383b4b7.cc44f62a37cf1caf.f1f748e7608cea69.7361b239c6bb60a5
+ 332300403a5f3d05
+ after
+ 6781909d84c0aa9d.3d06155c00bfa724.ce16a107a4a5bffc.b4782e5a8f7c5bae
+ f22dac7a90c25e5a.46460db99b03be37.1a30d4eab7a31d80.10d7c5b28d562b25
+ 0000000000000000.0000000000000000.1a30d4eab7a31d80.10d7c5b200000000
+ 540b6b8d9383b4b7.cc44f62a37cf1caf.f1f748e7608cea69.7361b239c6bb60a5
+ 332300403a5f3d05
+
+VCMPSS_128_0x3(reg)
+ before
+ 779e84ad615eec0b.e2d4069ac35bccaf.0399e017716fda6d.353c80d92e8dd227
+ 9a1e39edd945a863.2940c3908de6d4be.ab8dbd606ef04866.847d5cfdc7fd0aa5
+ faef1b6d3e9faeb8.05191e590b328610.216b8972c8dfa247.ba86593f48e74f10
+ f25c26972bf83ab7.522c93e35c4a9ed0.c18140ba1ec724bb.b323f18bcc585d93
+ 4b1fa2cd6f5bf05b
+ after
+ 0000000000000000.0000000000000000.ab8dbd606ef04866.847d5cfd00000000
+ 9a1e39edd945a863.2940c3908de6d4be.ab8dbd606ef04866.847d5cfdc7fd0aa5
+ faef1b6d3e9faeb8.05191e590b328610.216b8972c8dfa247.ba86593f48e74f10
+ f25c26972bf83ab7.522c93e35c4a9ed0.c18140ba1ec724bb.b323f18bcc585d93
+ 4b1fa2cd6f5bf05b
+VCMPSS_128_0x3(mem)
+ before
+ 5e48e7f24efcc394.ddb257d93ddc870b.ec459f189a3bda2b.e719dea20a34096f
+ c8683de485489369.193ea89d0fd8d361.af30bce6e110f44c.ef81609828b38e0f
+ 654c1e902f4a1c07.014a17513d785864.77b968384ed5a960.3603c00715cfee46
+ 11c008e3680e1a99.f0229f60644652c2.20ab1ffafc97b593.16ecfd5a6c1467c1
+ ec8710ffca0f332b
+ after
+ 5e48e7f24efcc394.ddb257d93ddc870b.ec459f189a3bda2b.e719dea20a34096f
+ c8683de485489369.193ea89d0fd8d361.af30bce6e110f44c.ef81609828b38e0f
+ 0000000000000000.0000000000000000.af30bce6e110f44c.ef81609800000000
+ 11c008e3680e1a99.f0229f60644652c2.20ab1ffafc97b593.16ecfd5a6c1467c1
+ ec8710ffca0f332b
+
+VCMPSS_128_0x3(reg)
+ before
+ 1422f661ca4b8e31.a89076c84da1484c.44143d3620d0ff24.86d35b180861d310
+ e908aced0955b67f.0687e52afa0e634c.576beb3f0ca19938.84fe9a7e8d3fc004
+ c9842d0d22b7e5c0.0773cff78a6127c4.8672a7e7c4465daa.f8f65719a83e389a
+ 0fe3752eb1ff58a1.861eb21a19a74fe1.2e766c9be54a8626.bd880ed37469f6ff
+ af7f3b990dccb85e
+ after
+ 0000000000000000.0000000000000000.576beb3f0ca19938.84fe9a7e00000000
+ e908aced0955b67f.0687e52afa0e634c.576beb3f0ca19938.84fe9a7e8d3fc004
+ c9842d0d22b7e5c0.0773cff78a6127c4.8672a7e7c4465daa.f8f65719a83e389a
+ 0fe3752eb1ff58a1.861eb21a19a74fe1.2e766c9be54a8626.bd880ed37469f6ff
+ af7f3b990dccb85e
+VCMPSS_128_0x3(mem)
+ before
+ a9a95a58907438e5.177180bc53b94bcd.6155097fc4eb98ce.a9c336c50a395257
+ 89d0e8fb196c32bd.3d7a4b24a470f9f1.73e45012a639beb8.55a502d2d0a0fbea
+ 2ac2606dc3c06415.dd49d1d13fb09fb9.989703bfdc9e7dca.8c68cb2fd20abe8a
+ 67493e9caa7d8817.532c0e2ec10579d0.ab3a9f7381259032.ab588d47ad03d6e4
+ 0ec04485fc1880a3
+ after
+ a9a95a58907438e5.177180bc53b94bcd.6155097fc4eb98ce.a9c336c50a395257
+ 89d0e8fb196c32bd.3d7a4b24a470f9f1.73e45012a639beb8.55a502d2d0a0fbea
+ 0000000000000000.0000000000000000.73e45012a639beb8.55a502d200000000
+ 67493e9caa7d8817.532c0e2ec10579d0.ab3a9f7381259032.ab588d47ad03d6e4
+ 0ec04485fc1880a3
+
+VCMPSS_128_0x4(reg)
+ before
+ 12edec575cd4f874.1e32ff73ebae5bef.fa6dfea9c4fcc3e3.8a989f18b2dab419
+ 112c822868c37a03.2a491ddea25f98ca.305a9dade721b89d.0f7f7f9b8acaa4ae
+ 68c60064bd7241fb.665916c9ea9dfdd4.503de8a6c4fe95ab.18b9bbe926001e1a
+ 730a6477f66c8a09.b0306520df734438.b563da00f72196b8.7f13cfeda188dc8c
+ 22593892176f9b2e
+ after
+ 0000000000000000.0000000000000000.305a9dade721b89d.0f7f7f9bffffffff
+ 112c822868c37a03.2a491ddea25f98ca.305a9dade721b89d.0f7f7f9b8acaa4ae
+ 68c60064bd7241fb.665916c9ea9dfdd4.503de8a6c4fe95ab.18b9bbe926001e1a
+ 730a6477f66c8a09.b0306520df734438.b563da00f72196b8.7f13cfeda188dc8c
+ 22593892176f9b2e
+VCMPSS_128_0x4(mem)
+ before
+ db5771c6a6c0162d.8e43a9cdb03e91d8.e29887d09eee2923.bd176f271d15f672
+ 88d8f67467880bb4.15bcccd386729115.da5ef6c342186ac0.c2a7a387d167f282
+ 03aa438878d134f0.64c3c8f31496c86c.724e30e7e800c13d.225d738db0a2c697
+ 2a97d5eef5aa4e0c.d7a2989af7366f88.8734b026abafebc3.3787daa35552ae5a
+ 5f6fd4375d04e57a
+ after
+ db5771c6a6c0162d.8e43a9cdb03e91d8.e29887d09eee2923.bd176f271d15f672
+ 88d8f67467880bb4.15bcccd386729115.da5ef6c342186ac0.c2a7a387d167f282
+ 0000000000000000.0000000000000000.da5ef6c342186ac0.c2a7a387ffffffff
+ 2a97d5eef5aa4e0c.d7a2989af7366f88.8734b026abafebc3.3787daa35552ae5a
+ 5f6fd4375d04e57a
+
+VCMPSS_128_0x4(reg)
+ before
+ f4625db36342a8a1.d76c2693f81c1435.caa63a35caddc516.f6dcf26ea833a380
+ 54ab7185049b337c.e7f5b461a0354397.991baa2f2a1704c1.991172aafa97a7a0
+ d9980d18db98c1b6.37fefb450700975d.a04de2f3b3706a36.4da1adc6bee7b14f
+ e1742cd884c78ffc.a152752c498accb4.3b87e0ef00753021.ee561eae0f307db8
+ 59fd414e097ec907
+ after
+ 0000000000000000.0000000000000000.991baa2f2a1704c1.991172aaffffffff
+ 54ab7185049b337c.e7f5b461a0354397.991baa2f2a1704c1.991172aafa97a7a0
+ d9980d18db98c1b6.37fefb450700975d.a04de2f3b3706a36.4da1adc6bee7b14f
+ e1742cd884c78ffc.a152752c498accb4.3b87e0ef00753021.ee561eae0f307db8
+ 59fd414e097ec907
+VCMPSS_128_0x4(mem)
+ before
+ 68629292c9db4f6a.c68aca319cb4d9f9.02bfa00083dd9dc7.c6179f8eadb1952d
+ f8518d666b55cc0a.e527e38fbfe9db5a.360ff7afd008c7c3.9d471b3c57b1d307
+ e595afb60af7fc16.9a97735e88f4d0cb.190ff6244d1406d4.1b64516599ff275a
+ 0bfc736fc2ce9ab8.4226770a9361f5f7.878c194b150f1525.9eba3b76102acdd3
+ 8195d7d957bb001d
+ after
+ 68629292c9db4f6a.c68aca319cb4d9f9.02bfa00083dd9dc7.c6179f8eadb1952d
+ f8518d666b55cc0a.e527e38fbfe9db5a.360ff7afd008c7c3.9d471b3c57b1d307
+ 0000000000000000.0000000000000000.360ff7afd008c7c3.9d471b3cffffffff
+ 0bfc736fc2ce9ab8.4226770a9361f5f7.878c194b150f1525.9eba3b76102acdd3
+ 8195d7d957bb001d
+
+VCMPSS_128_0x4(reg)
+ before
+ 1f4020fb0a40fde5.4650557bb0e5631d.3720ea007dba868b.5c4fdc104504b1e3
+ d6091249c74400d7.725ed1c8f0481370.d6d0c8aae28ebe32.7427bc5ff800963a
+ 013aaa2e2754459e.6bf264419c0365dd.7b840e765d66da99.acdf34244b0e8055
+ fb20e315c8fb07e7.0dd889d1d3231792.8286b6ce8ad0166c.de42c04b593a2a60
+ e61dddc13e915188
+ after
+ 0000000000000000.0000000000000000.d6d0c8aae28ebe32.7427bc5fffffffff
+ d6091249c74400d7.725ed1c8f0481370.d6d0c8aae28ebe32.7427bc5ff800963a
+ 013aaa2e2754459e.6bf264419c0365dd.7b840e765d66da99.acdf34244b0e8055
+ fb20e315c8fb07e7.0dd889d1d3231792.8286b6ce8ad0166c.de42c04b593a2a60
+ e61dddc13e915188
+VCMPSS_128_0x4(mem)
+ before
+ a23c0570171eb1f9.2207b86c46c5835e.34dcbc66aeb4e3b9.4723be200657ae56
+ ed6bb64500ed06de.d03b289e3c3ff5ae.bcc979eb4cc0857e.26a721d76c87dd04
+ a3766b2d140b0b64.63082c1746f49884.816d3c4cc655bb0f.7b5edb5f59ede021
+ a029a0136f837db7.35b9c2430170a98b.5f9282753b7f3f95.a293e9246814f35a
+ f79446923688525b
+ after
+ a23c0570171eb1f9.2207b86c46c5835e.34dcbc66aeb4e3b9.4723be200657ae56
+ ed6bb64500ed06de.d03b289e3c3ff5ae.bcc979eb4cc0857e.26a721d76c87dd04
+ 0000000000000000.0000000000000000.bcc979eb4cc0857e.26a721d7ffffffff
+ a029a0136f837db7.35b9c2430170a98b.5f9282753b7f3f95.a293e9246814f35a
+ f79446923688525b
+
+VCMPSS_128_0x5(reg)
+ before
+ d6abed155ed638cf.c04fd2e32e611802.a49ce48e093f6470.3205c653c448cd3f
+ 9b25dd197c89e263.dfb67c896cb29772.0afb9064f8ee05de.d69284d07fbe2337
+ a24e0f0b2d2e8cc2.d8281af14681b732.c523c2326d09c782.260438da88edfba9
+ 477280550d507199.89722807d7da346f.2f607462021ae708.00295f5bfadf12c2
+ 3fcb7441f2a224ae
+ after
+ 0000000000000000.0000000000000000.0afb9064f8ee05de.d69284d0ffffffff
+ 9b25dd197c89e263.dfb67c896cb29772.0afb9064f8ee05de.d69284d07fbe2337
+ a24e0f0b2d2e8cc2.d8281af14681b732.c523c2326d09c782.260438da88edfba9
+ 477280550d507199.89722807d7da346f.2f607462021ae708.00295f5bfadf12c2
+ 3fcb7441f2a224ae
+VCMPSS_128_0x5(mem)
+ before
+ beb8f3768b42ec98.e6dd2d65b77bce94.cd6022b73ccaca55.a5fea46253afa11b
+ 5bba58e8e1c927ad.dada11a6c73bdf5e.7fbd85ed905c340f.83484d9cfd543068
+ f19e1f8211469119.81b72983da1ddfa4.7d57cb96f09c2fc9.268c6b7e9b93d19b
+ 5b30c53036c2e607.36be6f6a8cac0c11.a1f8729c779776b1.e814fa73cafac05f
+ 262df7e725153960
+ after
+ beb8f3768b42ec98.e6dd2d65b77bce94.cd6022b73ccaca55.a5fea46253afa11b
+ 5bba58e8e1c927ad.dada11a6c73bdf5e.7fbd85ed905c340f.83484d9cfd543068
+ 0000000000000000.0000000000000000.7fbd85ed905c340f.83484d9c00000000
+ 5b30c53036c2e607.36be6f6a8cac0c11.a1f8729c779776b1.e814fa73cafac05f
+ 262df7e725153960
+
+VCMPSS_128_0x5(reg)
+ before
+ 3c235c46486e774b.773bc5de6d4be1a4.543ce1c67875a052.c96df6ed4258c7f1
+ 864227fcd094b7cc.1f8d9b79d2ec3f1b.397d79033a03d712.d082d1736cebdcb5
+ 60d654755910358f.31f0c3eb80b1bc99.40cd368d6fe2effe.9103811c125d722a
+ 262add1d7e702d3f.8731b92193a71349.c47711d1b29f22c2.e9bc81d34fb9447c
+ b5794d843f0c10d6
+ after
+ 0000000000000000.0000000000000000.397d79033a03d712.d082d173ffffffff
+ 864227fcd094b7cc.1f8d9b79d2ec3f1b.397d79033a03d712.d082d1736cebdcb5
+ 60d654755910358f.31f0c3eb80b1bc99.40cd368d6fe2effe.9103811c125d722a
+ 262add1d7e702d3f.8731b92193a71349.c47711d1b29f22c2.e9bc81d34fb9447c
+ b5794d843f0c10d6
+VCMPSS_128_0x5(mem)
+ before
+ cf05611bff619065.358cc061dc3fda88.fe1cfa0828d90158.23c90739a0c5ad09
+ 152d3a84abc48154.e746f8ab0d097917.737d018a5a5442f2.b70d1532d4e0cb80
+ 61be52ab5e419ed1.98a58169b05b4598.c0204a9545229242.de903629eb7cbad3
+ 9081277c34e5a405.a6f557065fc07cb7.c3d052140752ac75.f29e66898026b4ad
+ 5183a2bd306af5bb
+ after
+ cf05611bff619065.358cc061dc3fda88.fe1cfa0828d90158.23c90739a0c5ad09
+ 152d3a84abc48154.e746f8ab0d097917.737d018a5a5442f2.b70d1532d4e0cb80
+ 0000000000000000.0000000000000000.737d018a5a5442f2.b70d153200000000
+ 9081277c34e5a405.a6f557065fc07cb7.c3d052140752ac75.f29e66898026b4ad
+ 5183a2bd306af5bb
+
+VCMPSS_128_0x5(reg)
+ before
+ 558ae43396d2bba8.7f4535e44abb4f1e.6c8176edb6c5581f.565b93f3b9ed4db6
+ 5b012a564eec4021.08d5f6cdbbd05b48.4697db8c52f4167c.568b8b1e79013133
+ c0326f92f544c1d1.08fce825a42f83af.9081814ecedcf17b.9f2db58163991315
+ de6ab05327647965.5b8885d720e4847e.a68d649fc70626c8.0d0d8d0892c2b18a
+ 7df7909f2287c5be
+ after
+ 0000000000000000.0000000000000000.4697db8c52f4167c.568b8b1effffffff
+ 5b012a564eec4021.08d5f6cdbbd05b48.4697db8c52f4167c.568b8b1e79013133
+ c0326f92f544c1d1.08fce825a42f83af.9081814ecedcf17b.9f2db58163991315
+ de6ab05327647965.5b8885d720e4847e.a68d649fc70626c8.0d0d8d0892c2b18a
+ 7df7909f2287c5be
+VCMPSS_128_0x5(mem)
+ before
+ c9b6383230f40bdd.12f5e7057fdaa689.dd434cce4cfb1ae1.e40581ebd800f10e
+ ce1803aed8154112.b81f1215993282e8.6afab6f843810006.a536d29e9e558efa
+ 68e76cfd35f72189.2d342ced12f64a2f.df7940402282f316.476c5525b4923838
+ 73f0f00d63a6676f.cb8031fa86b43909.168c67920408af40.25f205eab7412d73
+ 9a16de5b42f1a658
+ after
+ c9b6383230f40bdd.12f5e7057fdaa689.dd434cce4cfb1ae1.e40581ebd800f10e
+ ce1803aed8154112.b81f1215993282e8.6afab6f843810006.a536d29e9e558efa
+ 0000000000000000.0000000000000000.6afab6f843810006.a536d29effffffff
+ 73f0f00d63a6676f.cb8031fa86b43909.168c67920408af40.25f205eab7412d73
+ 9a16de5b42f1a658
+
+VCMPSS_128_0x6(reg)
+ before
+ 0422dde2f22be292.cbff09c97f2cd1f0.ef4e1da990f88c23.ecfea6db0621f0ae
+ be63fded627d1bce.4ce0351ca4971938.f5ebed65cc4d7f29.3d9d790543d8718c
+ 23253ae72e728eb7.d25feff4eff2fc72.39a39c99d73f4ec6.e5335dfdd73aef07
+ 91b4903cf39777fa.3947b33c7b4a36ca.17c226b34c5a34a7.bf8dccb0df52264b
+ a9774408772cd284
+ after
+ 0000000000000000.0000000000000000.f5ebed65cc4d7f29.3d9d7905ffffffff
+ be63fded627d1bce.4ce0351ca4971938.f5ebed65cc4d7f29.3d9d790543d8718c
+ 23253ae72e728eb7.d25feff4eff2fc72.39a39c99d73f4ec6.e5335dfdd73aef07
+ 91b4903cf39777fa.3947b33c7b4a36ca.17c226b34c5a34a7.bf8dccb0df52264b
+ a9774408772cd284
+VCMPSS_128_0x6(mem)
+ before
+ 7ebd40f3bad5aedd.625cfb584d771143.5d66fee065aa826d.eb94871ec82b6e77
+ 1a2a3c5bc4587782.f46878a7d79e993d.19864acdc81e9d87.1165bb46e63d38e3
+ 598cb52eb2c1e9a0.a12601952d994b95.4b7415edc1b34343.e580bf97431ccd97
+ 17ad25579f1dbf63.c6e0948eecf363f7.cefcda2d6b742fce.c3328e7d7a556b3e
+ 07c8246527734c85
+ after
+ 7ebd40f3bad5aedd.625cfb584d771143.5d66fee065aa826d.eb94871ec82b6e77
+ 1a2a3c5bc4587782.f46878a7d79e993d.19864acdc81e9d87.1165bb46e63d38e3
+ 0000000000000000.0000000000000000.19864acdc81e9d87.1165bb4600000000
+ 17ad25579f1dbf63.c6e0948eecf363f7.cefcda2d6b742fce.c3328e7d7a556b3e
+ 07c8246527734c85
+
+VCMPSS_128_0x6(reg)
+ before
+ 0d8c7eb9e703ac17.2f5a0ac2a877b6f6.c0e32dffaf381c0e.7ee9167ae36d1f54
+ 31ca96e75690c9a1.7f5fe05be9db8a86.e97bc65213f5b386.370943be44abcd00
+ ced06a590fa6ddcf.e288210e7c56f63f.9ef45df5b3b5640d.d426dfe7aa39f5ff
+ 42e9f57daed1254c.33a14ac880f3b84c.3c99ed522c046a4d.330e65e03223557c
+ 2f8b5194f876a7a4
+ after
+ 0000000000000000.0000000000000000.e97bc65213f5b386.370943beffffffff
+ 31ca96e75690c9a1.7f5fe05be9db8a86.e97bc65213f5b386.370943be44abcd00
+ ced06a590fa6ddcf.e288210e7c56f63f.9ef45df5b3b5640d.d426dfe7aa39f5ff
+ 42e9f57daed1254c.33a14ac880f3b84c.3c99ed522c046a4d.330e65e03223557c
+ 2f8b5194f876a7a4
+VCMPSS_128_0x6(mem)
+ before
+ a36a1ff1173da8a2.e86033bed09edcc5.5075d8730ebe8ada.1db872d7196f03f2
+ 6d774ce2ab8513a4.1c82218811983fe5.14d246fd45c42814.9e9be8ef178169a9
+ 677d5353d158a6d3.399bb9470c4c8a59.5a8210503e105027.1b8f4c06c1c6d81e
+ 6f4ab031a4c41b5e.9df7f9675d45f9cc.0052b35a17afbc3e.f1e09988b4cb8efc
+ 7adacbe18b1bc5f0
+ after
+ a36a1ff1173da8a2.e86033bed09edcc5.5075d8730ebe8ada.1db872d7196f03f2
+ 6d774ce2ab8513a4.1c82218811983fe5.14d246fd45c42814.9e9be8ef178169a9
+ 0000000000000000.0000000000000000.14d246fd45c42814.9e9be8ef00000000
+ 6f4ab031a4c41b5e.9df7f9675d45f9cc.0052b35a17afbc3e.f1e09988b4cb8efc
+ 7adacbe18b1bc5f0
+
+VCMPSS_128_0x6(reg)
+ before
+ 13c9de7de242b9a5.5fa8df6641d52e6e.a2e2dc54a10fc7eb.e00eaa06ecab2986
+ 18f8cec856cda8c8.15645ddfc3969d32.a6a75f7a73373262.d882703fd813522b
+ e5b4982f8347cc05.6b4aa489471322d4.04947c45704773dc.c27984f3f7f0f558
+ d64a371c043d6207.3e26324ee8587a81.17f3312233cec906.7bc15f0d6650cc3a
+ e0247e79413e93fd
+ after
+ 0000000000000000.0000000000000000.a6a75f7a73373262.d882703fffffffff
+ 18f8cec856cda8c8.15645ddfc3969d32.a6a75f7a73373262.d882703fd813522b
+ e5b4982f8347cc05.6b4aa489471322d4.04947c45704773dc.c27984f3f7f0f558
+ d64a371c043d6207.3e26324ee8587a81.17f3312233cec906.7bc15f0d6650cc3a
+ e0247e79413e93fd
+VCMPSS_128_0x6(mem)
+ before
+ cb6f5e24a3c608cc.4704a7fd7539a67b.6bc4831cc3726064.3d11797b59556e8c
+ 196e7af8a8f5e5d3.942fe43c73cad30c.ccef11def36c92aa.d03a50be7d6a9f19
+ a7ed4ee26dd6e740.1916eb479a792667.3e755a809553ca7e.2dbab2563c99985a
+ 4fb757cf0d76ca3c.3107b68984d4db38.9e20d8eec432c40d.b1dd9cae316c95fa
+ b6ee0934f871d1a6
+ after
+ cb6f5e24a3c608cc.4704a7fd7539a67b.6bc4831cc3726064.3d11797b59556e8c
+ 196e7af8a8f5e5d3.942fe43c73cad30c.ccef11def36c92aa.d03a50be7d6a9f19
+ 0000000000000000.0000000000000000.ccef11def36c92aa.d03a50beffffffff
+ 4fb757cf0d76ca3c.3107b68984d4db38.9e20d8eec432c40d.b1dd9cae316c95fa
+ b6ee0934f871d1a6
+
+VCMPSS_128_0x7(reg)
+ before
+ 993af5532e348909.ee9a0faaa5e049f6.3a4c436ed0662d2a.c6bd09149d153e83
+ b70e5c776f3ff8d0.6060f45e50202198.8f328d6218bb5ae9.931869de3b08f20b
+ 6ab43b0d56205ba7.81d781d92b430e4f.8c0691d1f8609c23.e1fd7238ba189dd2
+ 0f798c7f7f63ef39.2dc933065153cb46.8d1249270de02f82.8c37a20e3750fb03
+ 7094744dcebdc7cb
+ after
+ 0000000000000000.0000000000000000.8f328d6218bb5ae9.931869deffffffff
+ b70e5c776f3ff8d0.6060f45e50202198.8f328d6218bb5ae9.931869de3b08f20b
+ 6ab43b0d56205ba7.81d781d92b430e4f.8c0691d1f8609c23.e1fd7238ba189dd2
+ 0f798c7f7f63ef39.2dc933065153cb46.8d1249270de02f82.8c37a20e3750fb03
+ 7094744dcebdc7cb
+VCMPSS_128_0x7(mem)
+ before
+ 69de64df996abe56.02a84d3a8792ed33.410284d1df5f15aa.eda2b3d1f2c851b2
+ 53e2eeb2b7639ccf.a08f7aab0a3b9440.9750f226f070a8a6.0a04ca3943a33c60
+ 0a6c8fb142b51c63.43780d3ca2ea1e0d.0c7ef8f1a1944067.3f828bcd9dfd2d38
+ 6a48c1c8566bfc3d.48b0045bee29c846.7c57121e0dd69819.e76af0f79c635fe5
+ 6006f725db600f14
+ after
+ 69de64df996abe56.02a84d3a8792ed33.410284d1df5f15aa.eda2b3d1f2c851b2
+ 53e2eeb2b7639ccf.a08f7aab0a3b9440.9750f226f070a8a6.0a04ca3943a33c60
+ 0000000000000000.0000000000000000.9750f226f070a8a6.0a04ca39ffffffff
+ 6a48c1c8566bfc3d.48b0045bee29c846.7c57121e0dd69819.e76af0f79c635fe5
+ 6006f725db600f14
+
+VCMPSS_128_0x7(reg)
+ before
+ 04a39bc2f7807971.4f4202e21091f68a.0b8459738887cd96.c3a8bc9a50436de7
+ 318dd83a8b4fd9a7.9525ceed8b34c676.e83d0aef0c8d6baa.bc3d734f88e67bfd
+ 410faaf9335a6b63.18bf9fd4e45f2a2c.3b2a133d17c9dc2d.45e2b22bcecb7e89
+ 92770e6b8c2d6a50.b4daf384361edcd9.60966ec844c65dcc.3963f51840ff31b5
+ 748cb804f98d51ad
+ after
+ 0000000000000000.0000000000000000.e83d0aef0c8d6baa.bc3d734fffffffff
+ 318dd83a8b4fd9a7.9525ceed8b34c676.e83d0aef0c8d6baa.bc3d734f88e67bfd
+ 410faaf9335a6b63.18bf9fd4e45f2a2c.3b2a133d17c9dc2d.45e2b22bcecb7e89
+ 92770e6b8c2d6a50.b4daf384361edcd9.60966ec844c65dcc.3963f51840ff31b5
+ 748cb804f98d51ad
+VCMPSS_128_0x7(mem)
+ before
+ d22878da16819a9e.7e0ffffc3152131b.454345e79e7e98a8.b3cc19fd2f102933
+ 2f05af86b3e8c7b4.63257918bf57a16f.a7c611ea378a1cc6.901a0f4676347d0d
+ 66eddbf4eacd951b.9b03782bd2c751f9.b52ed37a1d4e225f.53ca4c10b2bd9507
+ 55ad7710da3cc0fe.83f6f8a2042f6065.4d4908816dd7679e.5829ccc78138adcc
+ fa838cd87f2f0009
+ after
+ d22878da16819a9e.7e0ffffc3152131b.454345e79e7e98a8.b3cc19fd2f102933
+ 2f05af86b3e8c7b4.63257918bf57a16f.a7c611ea378a1cc6.901a0f4676347d0d
+ 0000000000000000.0000000000000000.a7c611ea378a1cc6.901a0f46ffffffff
+ 55ad7710da3cc0fe.83f6f8a2042f6065.4d4908816dd7679e.5829ccc78138adcc
+ fa838cd87f2f0009
+
+VCMPSS_128_0x7(reg)
+ before
+ 972387ae4731cc6a.d71100c69d420389.7849f6e7f41a075e.4ae12aed4330a7af
+ 8a57b9b475c74a9a.c7e4f0024fea1ce9.d44a6d683c148591.87c4b7a9ba659dc0
+ 2f691e58a67fb946.03f4c5b10d41c54a.f443599078aa14a9.e2bc2aa0ee8306fb
+ e1a6b20576e45319.660bfabdf251bad7.3582b6cb4467f153.369600c0fc959e8c
+ 5e1eb3f400a721a0
+ after
+ 0000000000000000.0000000000000000.d44a6d683c148591.87c4b7a9ffffffff
+ 8a57b9b475c74a9a.c7e4f0024fea1ce9.d44a6d683c148591.87c4b7a9ba659dc0
+ 2f691e58a67fb946.03f4c5b10d41c54a.f443599078aa14a9.e2bc2aa0ee8306fb
+ e1a6b20576e45319.660bfabdf251bad7.3582b6cb4467f153.369600c0fc959e8c
+ 5e1eb3f400a721a0
+VCMPSS_128_0x7(mem)
+ before
+ 381fc12915c64a63.fe5a7227808355c0.cbf60b141a28b9bd.f15181843ed8573b
+ 9e67a54957fdd600.e1d1592a60e7fbe6.108175a0a2d27c28.85fdb529ff87840c
+ 6ec0dc41e35981a4.e557637ab39c8038.0f78b24fa65ac043.4dd24e262502b273
+ 82f7e0fdd4e4067b.68388c83142e2162.a6a7400c41cc403a.a51b48e54cd51e1c
+ e9269fd30f8a03b2
+ after
+ 381fc12915c64a63.fe5a7227808355c0.cbf60b141a28b9bd.f15181843ed8573b
+ 9e67a54957fdd600.e1d1592a60e7fbe6.108175a0a2d27c28.85fdb529ff87840c
+ 0000000000000000.0000000000000000.108175a0a2d27c28.85fdb52900000000
+ 82f7e0fdd4e4067b.68388c83142e2162.a6a7400c41cc403a.a51b48e54cd51e1c
+ e9269fd30f8a03b2
+
+VCMPSS_128_0xA(reg)
+ before
+ 753d505c0ab09ee1.b8d82f6a47ac22b0.c4bfd1b2202a1a0f.afda9ac39034ba3b
+ a5ad56eddad02b56.ea2f447357bd916f.57392c71721ca7ec.07dc3d60ae9fe86f
+ d5c2adf11b78e6bd.f5c89b0321220fe6.7bf39b2ea78e03a5.8b7aa3cfb7188605
+ 61c851d368330ac1.b66eb008c0e7573e.8e361a535a0e6be5.15814afcc8ac5227
+ 82bbadd4fc650602
+ after
+ 0000000000000000.0000000000000000.57392c71721ca7ec.07dc3d6000000000
+ a5ad56eddad02b56.ea2f447357bd916f.57392c71721ca7ec.07dc3d60ae9fe86f
+ d5c2adf11b78e6bd.f5c89b0321220fe6.7bf39b2ea78e03a5.8b7aa3cfb7188605
+ 61c851d368330ac1.b66eb008c0e7573e.8e361a535a0e6be5.15814afcc8ac5227
+ 82bbadd4fc650602
+VCMPSS_128_0xA(mem)
+ before
+ aff4484170525fc1.a50b3f015d8dd40f.07ef006d511826a6.ea51a34e28271b59
+ 76fa9831407c1991.fdd771e697138053.c515061eefc23848.ed8f348aac664eac
+ b498178e86f1ef9d.c577e5eeb1504a38.ccad3e07b6f04851.f13bc7738256418b
+ 4599434661bc9e12.5838978548d16d6b.f9832414c3af14ec.53a35b75478330a1
+ 7011e9fc977a579b
+ after
+ aff4484170525fc1.a50b3f015d8dd40f.07ef006d511826a6.ea51a34e28271b59
+ 76fa9831407c1991.fdd771e697138053.c515061eefc23848.ed8f348aac664eac
+ 0000000000000000.0000000000000000.c515061eefc23848.ed8f348affffffff
+ 4599434661bc9e12.5838978548d16d6b.f9832414c3af14ec.53a35b75478330a1
+ 7011e9fc977a579b
+
+VCMPSS_128_0xA(reg)
+ before
+ a2d26e740dc6f125.05ca9744eaeae21c.14668117f7212697.26633431320a5646
+ 4632e74945f33bea.d1f79073408676e6.544da1105bccb169.3018eb4b1e0dca8a
+ b87d4fe8dc8e7197.83eca8c17c9c179d.7439f1dc0f5e498d.f370c44ca3c52de5
+ 54fea2bb6e22ced7.f8755d1abc38816c.cf766fe8b0642bae.4b353b21de3d3c83
+ 1434ccb7eb81b08f
+ after
+ 0000000000000000.0000000000000000.544da1105bccb169.3018eb4b00000000
+ 4632e74945f33bea.d1f79073408676e6.544da1105bccb169.3018eb4b1e0dca8a
+ b87d4fe8dc8e7197.83eca8c17c9c179d.7439f1dc0f5e498d.f370c44ca3c52de5
+ 54fea2bb6e22ced7.f8755d1abc38816c.cf766fe8b0642bae.4b353b21de3d3c83
+ 1434ccb7eb81b08f
+VCMPSS_128_0xA(mem)
+ before
+ 2a39f4f9e49d4836.7703dd30953c9057.0c5d2a681c677080.c34f179ed9699379
+ 69102ed3e89ebea3.7bd6fab1f066f1c3.9b728b98b7359f05.ab12e36c26fabc99
+ ad85f6301190cf03.bdc4f7ac192e2dc6.817efc96aaaccb26.e209d1bd35a2e4bb
+ d263c8fe7b7d3782.9919cf8cac20820d.9a4efa4f10dab010.c681dcfd9fed458a
+ b1c6009702681bb3
+ after
+ 2a39f4f9e49d4836.7703dd30953c9057.0c5d2a681c677080.c34f179ed9699379
+ 69102ed3e89ebea3.7bd6fab1f066f1c3.9b728b98b7359f05.ab12e36c26fabc99
+ 0000000000000000.0000000000000000.9b728b98b7359f05.ab12e36c00000000
+ d263c8fe7b7d3782.9919cf8cac20820d.9a4efa4f10dab010.c681dcfd9fed458a
+ b1c6009702681bb3
+
+VCMPSS_128_0xA(reg)
+ before
+ 012339f9fa9ea4e2.b47820294273b14b.6b217ebd46c72a43.c1ae00ad05ca0aee
+ 10e6848e211b1ac2.2f8e7b9b847efa8a.8f2701ab82af6115.d46a8a9ea68994ed
+ 3c59dcc3166cba00.1e7254415aa8ce6d.617952c2fc64652f.ae4d140d0f220b39
+ dfc93d02731cbf48.5ff02707e2ffe81e.3d616f6e5273703c.2b251ae55aa12bfd
+ 27bc1914a613af65
+ after
+ 0000000000000000.0000000000000000.8f2701ab82af6115.d46a8a9effffffff
+ 10e6848e211b1ac2.2f8e7b9b847efa8a.8f2701ab82af6115.d46a8a9ea68994ed
+ 3c59dcc3166cba00.1e7254415aa8ce6d.617952c2fc64652f.ae4d140d0f220b39
+ dfc93d02731cbf48.5ff02707e2ffe81e.3d616f6e5273703c.2b251ae55aa12bfd
+ 27bc1914a613af65
+VCMPSS_128_0xA(mem)
+ before
+ 7ddf8c850d83549f.5682a3b8d4b76745.cdd370da388f06c9.7f2c531b1d67bfe9
+ 0b5aef24abfed6d5.fed00a52d6caeca3.44e9aca47762e29b.8226fb36fbcd8ee1
+ acf9bfde9d8ef033.31ff6f3a14e08a10.9ffc5653bc8638c0.a49b6129882f18d1
+ 3b88769dfe4160e6.4c5bcdde2b857f35.bcdaead22207c663.40d783625f1c9a65
+ b2255c4c1c1d5048
+ after
+ 7ddf8c850d83549f.5682a3b8d4b76745.cdd370da388f06c9.7f2c531b1d67bfe9
+ 0b5aef24abfed6d5.fed00a52d6caeca3.44e9aca47762e29b.8226fb36fbcd8ee1
+ 0000000000000000.0000000000000000.44e9aca47762e29b.8226fb36ffffffff
+ 3b88769dfe4160e6.4c5bcdde2b857f35.bcdaead22207c663.40d783625f1c9a65
+ b2255c4c1c1d5048
+
+VCMPSS_128_0xC(reg)
+ before
+ 55d2e8525cc07626.96d2924eeb23e01a.ac2f20a9b64605c1.764de40dc5ef46b1
+ 872b24e2bb9047ad.98a58ede7f3e2cfa.abc8640652ae595e.a822c0efc24c75d6
+ a37a0a67d41a0087.1ccbe637d7a002b3.a67396639a49b7b9.3025fb67352a0efd
+ 040c984d43e9dd60.001117470e551c71.f97ab12b2ba45a7d.e821105e3894cf53
+ aee47bc1ea967203
+ after
+ 0000000000000000.0000000000000000.abc8640652ae595e.a822c0efffffffff
+ 872b24e2bb9047ad.98a58ede7f3e2cfa.abc8640652ae595e.a822c0efc24c75d6
+ a37a0a67d41a0087.1ccbe637d7a002b3.a67396639a49b7b9.3025fb67352a0efd
+ 040c984d43e9dd60.001117470e551c71.f97ab12b2ba45a7d.e821105e3894cf53
+ aee47bc1ea967203
+VCMPSS_128_0xC(mem)
+ before
+ 5c38b87c653cb33a.082cc900a58919e5.1e439bf94068375f.0029b1caa04a7f57
+ d0ea437cc5935023.0a289aed9586f1c2.542df0398ae50eaa.17ce92ad95c762f2
+ e4c699ab27a603eb.654a057eb06da1a2.7c9a91f308d85f7d.9ab4503ea7a83efb
+ 769835f7a68289be.77e0082091ca6532.7358fb13d54ee405.e526e8ea7278511e
+ 5471551e91c3d406
+ after
+ 5c38b87c653cb33a.082cc900a58919e5.1e439bf94068375f.0029b1caa04a7f57
+ d0ea437cc5935023.0a289aed9586f1c2.542df0398ae50eaa.17ce92ad95c762f2
+ 0000000000000000.0000000000000000.542df0398ae50eaa.17ce92adffffffff
+ 769835f7a68289be.77e0082091ca6532.7358fb13d54ee405.e526e8ea7278511e
+ 5471551e91c3d406
+
+VCMPSS_128_0xC(reg)
+ before
+ 43e19344a0160660.602c934a5f319dc7.9a349e40d527781e.1631a8850d52596d
+ 0ec29eca3cfc21d7.7f4d30926dc2fd33.2c93c34917121711.3ff21635cdf17ce2
+ 1160731b00026318.afc986baec3e632e.874974a6f3167eb7.cb67c00f31360790
+ a8060da389b305ce.cd6a13aef9b38be3.08a1abc507c0e8be.975c2200532db7a2
+ 7d9db9f252e24845
+ after
+ 0000000000000000.0000000000000000.2c93c34917121711.3ff21635ffffffff
+ 0ec29eca3cfc21d7.7f4d30926dc2fd33.2c93c34917121711.3ff21635cdf17ce2
+ 1160731b00026318.afc986baec3e632e.874974a6f3167eb7.cb67c00f31360790
+ a8060da389b305ce.cd6a13aef9b38be3.08a1abc507c0e8be.975c2200532db7a2
+ 7d9db9f252e24845
+VCMPSS_128_0xC(mem)
+ before
+ 5af5ffd3486275a4.2f0267ce739b46a7.b3fd525ab02c337e.0ce96611ec9b92d0
+ 0a31728d51b8fbec.029e80085846604c.3e4ebfaa2cb6152d.ed6ba0f64033b899
+ 691e8d0e8af19649.7d2751bdd741906c.4a29d78a8a5cee19.087455e09f1596c6
+ 5486cc410e1801e6.fbe9d859891712b1.b35914e7e42a7a71.ba50823ba4cc6703
+ 5d4b2274ebe468fb
+ after
+ 5af5ffd3486275a4.2f0267ce739b46a7.b3fd525ab02c337e.0ce96611ec9b92d0
+ 0a31728d51b8fbec.029e80085846604c.3e4ebfaa2cb6152d.ed6ba0f64033b899
+ 0000000000000000.0000000000000000.3e4ebfaa2cb6152d.ed6ba0f6ffffffff
+ 5486cc410e1801e6.fbe9d859891712b1.b35914e7e42a7a71.ba50823ba4cc6703
+ 5d4b2274ebe468fb
+
+VCMPSS_128_0xC(reg)
+ before
+ 4eb131f511ead55b.a535ac12f939f9f0.da300f480d5521c7.56acf4ab592c745f
+ e9cdab2bb169e9ce.39f9a86d69613a92.7548f5f7fc86fa5b.0decf3c4036f990f
+ 8aed8c8368ede101.ec9d3c3e779a80f9.277c83d0f436d919.b5e68b1cfefea5af
+ 8d5bd168d203f9a0.9aece47241f38651.4e19b64191f1faac.2a6639a167e65368
+ 48387a3e59326169
+ after
+ 0000000000000000.0000000000000000.7548f5f7fc86fa5b.0decf3c4ffffffff
+ e9cdab2bb169e9ce.39f9a86d69613a92.7548f5f7fc86fa5b.0decf3c4036f990f
+ 8aed8c8368ede101.ec9d3c3e779a80f9.277c83d0f436d919.b5e68b1cfefea5af
+ 8d5bd168d203f9a0.9aece47241f38651.4e19b64191f1faac.2a6639a167e65368
+ 48387a3e59326169
+VCMPSS_128_0xC(mem)
+ before
+ eb28c9dff1ee88dc.4f64754589366d56.1fb31cf3e37509c5.456b8bb56e4498c1
+ ee01a2704a2787ed.2a5474882c1378d0.57bf61ae782ec582.67befd9728bbf004
+ 2f9182dd81e819c9.7b77ca9c542457b9.1dd92e901c2a76b3.125e08555ae03e20
+ 89a2e312b13df99c.9e1873eda0f846be.4fd0ff83ec73d785.a097a85aa041bdc2
+ 6fb5da129769aa95
+ after
+ eb28c9dff1ee88dc.4f64754589366d56.1fb31cf3e37509c5.456b8bb56e4498c1
+ ee01a2704a2787ed.2a5474882c1378d0.57bf61ae782ec582.67befd9728bbf004
+ 0000000000000000.0000000000000000.57bf61ae782ec582.67befd97ffffffff
+ 89a2e312b13df99c.9e1873eda0f846be.4fd0ff83ec73d785.a097a85aa041bdc2
+ 6fb5da129769aa95
+
+VCMPSS_128_0xC(reg)
+ before
+ d90399e9dae54146.d80143fbf733e392.ef856ce7a918818b.c86f50750417a524
+ 3bcee14c0640be80.f87a1d846ed595d5.c908b0f60d1243cb.64819d517f229cbb
+ f262aea5b7065cf0.c4d8ee9a332fc994.8aee3b876871c92b.ffd46303799e7777
+ 580bfd6287c45842.1ae93027614e3cf9.8d83090455c14f56.74321d770f99f383
+ a16847995c1fcc0c
+ after
+ 0000000000000000.0000000000000000.c908b0f60d1243cb.64819d51ffffffff
+ 3bcee14c0640be80.f87a1d846ed595d5.c908b0f60d1243cb.64819d517f229cbb
+ f262aea5b7065cf0.c4d8ee9a332fc994.8aee3b876871c92b.ffd46303799e7777
+ 580bfd6287c45842.1ae93027614e3cf9.8d83090455c14f56.74321d770f99f383
+ a16847995c1fcc0c
+VCMPSS_128_0xC(mem)
+ before
+ 61425d557d3abd3d.ca15c8ed1505ee21.d5776119143daa31.2e1317db718f10f9
+ 908bdc978df88444.a5cc0db4fa55593a.d150fc5b6908ce67.c9ea6076576649c0
+ 09113f4ca965db4a.437bc721d541d638.e93e7dd97cbc65c8.ba53e043a3d33656
+ aa9e025eec8c7e7e.016ff3a23f54a1c8.fb0e617f68642b80.5c9c93adf2611267
+ 0d0f7520e09c1ba1
+ after
+ 61425d557d3abd3d.ca15c8ed1505ee21.d5776119143daa31.2e1317db718f10f9
+ 908bdc978df88444.a5cc0db4fa55593a.d150fc5b6908ce67.c9ea6076576649c0
+ 0000000000000000.0000000000000000.d150fc5b6908ce67.c9ea6076ffffffff
+ aa9e025eec8c7e7e.016ff3a23f54a1c8.fb0e617f68642b80.5c9c93adf2611267
+ 0d0f7520e09c1ba1
+
+VCMPSS_128_0xC(reg)
+ before
+ 28f9830807118bae.4dffa1bb73792b09.3bf48ba2d61af696.e18c2239490ddcba
+ 08a6b8d1064a9e3a.d001994e59389c1a.4d568d8d3620104d.79833ef33cc133a2
+ 0b6210e777d692f2.0d6d6402bad68edb.94e1f4cffaf12c9a.9dc130995c8eed66
+ 8b7887b6f63ea182.e21280c5b35ebc79.6ae1bcd4bf1a8628.2b107417c680c630
+ fd3d875a96a2792c
+ after
+ 0000000000000000.0000000000000000.4d568d8d3620104d.79833ef3ffffffff
+ 08a6b8d1064a9e3a.d001994e59389c1a.4d568d8d3620104d.79833ef33cc133a2
+ 0b6210e777d692f2.0d6d6402bad68edb.94e1f4cffaf12c9a.9dc130995c8eed66
+ 8b7887b6f63ea182.e21280c5b35ebc79.6ae1bcd4bf1a8628.2b107417c680c630
+ fd3d875a96a2792c
+VCMPSS_128_0xC(mem)
+ before
+ f114e44ce600c387.e6361aaa20100895.29bb688260dce41f.2ca1e10920255aa4
+ e16107dbd5a6606d.76e6c43090d702d8.c0339925dc5dc0fa.366f60d8b9a0e3ba
+ aaf06cf17ca10c09.99d581b2e320cdf7.81478d9a43ec0c35.e49534af27175e15
+ 298c8f7cf9fc8288.a94f4d9eb476a39d.49c4c2cdb29686fd.926059f806150662
+ 9c1ccb21f126194c
+ after
+ f114e44ce600c387.e6361aaa20100895.29bb688260dce41f.2ca1e10920255aa4
+ e16107dbd5a6606d.76e6c43090d702d8.c0339925dc5dc0fa.366f60d8b9a0e3ba
+ 0000000000000000.0000000000000000.c0339925dc5dc0fa.366f60d8ffffffff
+ 298c8f7cf9fc8288.a94f4d9eb476a39d.49c4c2cdb29686fd.926059f806150662
+ 9c1ccb21f126194c
+
+VCMPSS_128_0xC(reg)
+ before
+ 5e15879584d6d180.3803ed6768c47f15.04a0245f9f65c076.f574b3ab4566e87e
+ 339688bf5cb26baa.b41f009ee404bfdd.04130360427a6230.5f23dc1e1768efe3
+ 79edca0d14452275.79ad460d8ac8fd0c.07f6e50f3640c375.649fb91444a85759
+ 8b6449ea491c338e.64793ba0751cf7cd.6793c6d7194320f1.e0b3c777e933db0c
+ af2a813521143827
+ after
+ 0000000000000000.0000000000000000.04130360427a6230.5f23dc1effffffff
+ 339688bf5cb26baa.b41f009ee404bfdd.04130360427a6230.5f23dc1e1768efe3
+ 79edca0d14452275.79ad460d8ac8fd0c.07f6e50f3640c375.649fb91444a85759
+ 8b6449ea491c338e.64793ba0751cf7cd.6793c6d7194320f1.e0b3c777e933db0c
+ af2a813521143827
+VCMPSS_128_0xC(mem)
+ before
+ aed1633909582ad6.c54801c396c1daa0.4f4f5943c10d674d.8137a2248710b451
+ b774e96fbc0a6c46.83e5ef0298c35358.17fa1ee38ba609b7.b12f76631b32bd41
+ a7df90c35736bba3.20870e14eaabd962.9848056aeff49a38.54c43cfe7135756c
+ 5aded321f5e9d319.fa795a662907aa69.ae038ac60802d7fc.c445f26226a6187f
+ 5efd93fcd510e425
+ after
+ aed1633909582ad6.c54801c396c1daa0.4f4f5943c10d674d.8137a2248710b451
+ b774e96fbc0a6c46.83e5ef0298c35358.17fa1ee38ba609b7.b12f76631b32bd41
+ 0000000000000000.0000000000000000.17fa1ee38ba609b7.b12f7663ffffffff
+ 5aded321f5e9d319.fa795a662907aa69.ae038ac60802d7fc.c445f26226a6187f
+ 5efd93fcd510e425
+
+VCMPSS_128_0xD(reg)
+ before
+ 7e371c361bff130b.ac3c2d75b22e70d3.6c09cf62f062ff19.35f829e1f2dc792e
+ 8040877e9400e2dd.79c71dabab114dfd.d1816976db491720.09f35fa9ca8f3ffb
+ c064d23fda9e8d46.9d491caffc9f27c4.872e250c87472c28.06c0a709ab26e38e
+ 9aeff8e48c664ff3.f48fa86ec0e2ba54.e85cfe9290e87bdd.082b7dedb2ad2214
+ ebff5d41fa31b8b9
+ after
+ 0000000000000000.0000000000000000.d1816976db491720.09f35fa900000000
+ 8040877e9400e2dd.79c71dabab114dfd.d1816976db491720.09f35fa9ca8f3ffb
+ c064d23fda9e8d46.9d491caffc9f27c4.872e250c87472c28.06c0a709ab26e38e
+ 9aeff8e48c664ff3.f48fa86ec0e2ba54.e85cfe9290e87bdd.082b7dedb2ad2214
+ ebff5d41fa31b8b9
+VCMPSS_128_0xD(mem)
+ before
+ 8b0ac3f1a0bd60a8.6a2df5db43e2658f.5a653bd214e9c2d8.5257f07391b940ec
+ c4162ce9bf5dd70e.8c6ac68f9ea00bc7.aa9753c913bdfa7d.1f6bf81b2645b601
+ 72f01315741ed916.5cf1666d362c7c47.c2f06c3ed96c1f6f.ade310f6ec181ac7
+ 7064f462da0b21ed.360fd1dfa911f6ba.7d3e001d8302edd9.560d36707fbea8eb
+ 783365f67ac49c19
+ after
+ 8b0ac3f1a0bd60a8.6a2df5db43e2658f.5a653bd214e9c2d8.5257f07391b940ec
+ c4162ce9bf5dd70e.8c6ac68f9ea00bc7.aa9753c913bdfa7d.1f6bf81b2645b601
+ 0000000000000000.0000000000000000.aa9753c913bdfa7d.1f6bf81bffffffff
+ 7064f462da0b21ed.360fd1dfa911f6ba.7d3e001d8302edd9.560d36707fbea8eb
+ 783365f67ac49c19
+
+VCMPSS_128_0xD(reg)
+ before
+ 6da299f279b631fc.9c3e4bba0d306dbf.7611035293dbb3cd.b74b8d512c891fe8
+ 92a6cfd1191ea440.d149950b2a9a77b7.7841f8328f16ef2b.4ce48ec8f10f72c7
+ 448b0100f58a3193.ea534c3f4d54fb02.98ebadec3a4fe881.17d57f6eeda0a2a3
+ dd9c2deaaa86139e.c526ee44916ab7cb.325d1ceb2f11d87b.f6eadc2d3d476aa8
+ c4ef22f2fc108801
+ after
+ 0000000000000000.0000000000000000.7841f8328f16ef2b.4ce48ec800000000
+ 92a6cfd1191ea440.d149950b2a9a77b7.7841f8328f16ef2b.4ce48ec8f10f72c7
+ 448b0100f58a3193.ea534c3f4d54fb02.98ebadec3a4fe881.17d57f6eeda0a2a3
+ dd9c2deaaa86139e.c526ee44916ab7cb.325d1ceb2f11d87b.f6eadc2d3d476aa8
+ c4ef22f2fc108801
+VCMPSS_128_0xD(mem)
+ before
+ 5cafcca94707b6da.ba274efad39c8810.3d8ff70513e9653f.a1e2439a0ae9fcc4
+ 9cf8563f3939b061.3776619e0d5aca93.2d5ae16eeddcc289.43c51e6768628f08
+ 5e943c9eefb134c0.b1d66041f34c15d3.73532a6b3e4f89d6.7353a7bde408cef5
+ 8050fab4847bfc23.8293494f21fca67e.e9454ce8204f7852.8cd8dc081b67f535
+ eca0b8b4a90c4074
+ after
+ 5cafcca94707b6da.ba274efad39c8810.3d8ff70513e9653f.a1e2439a0ae9fcc4
+ 9cf8563f3939b061.3776619e0d5aca93.2d5ae16eeddcc289.43c51e6768628f08
+ 0000000000000000.0000000000000000.2d5ae16eeddcc289.43c51e67ffffffff
+ 8050fab4847bfc23.8293494f21fca67e.e9454ce8204f7852.8cd8dc081b67f535
+ eca0b8b4a90c4074
+
+VCMPSS_128_0xD(reg)
+ before
+ eef7372d2983ea5f.dcf80d6c15a4c5b7.07f9173435f9ba3e.6dfec5d1afe74928
+ ed2955df375631a2.5058f0b2bd374aa8.9c54c65cc8cc8abf.d94811120823b885
+ 47810f3770134ee8.b63b1f7298414921.9def5334780355ae.0bf0aa9846108395
+ 564c5f9f6f4580de.ec6f1698c3cc7c4f.6617b826e12955b7.ddc20e4d86b96483
+ 2d8ab81fe32b187b
+ after
+ 0000000000000000.0000000000000000.9c54c65cc8cc8abf.d948111200000000
+ ed2955df375631a2.5058f0b2bd374aa8.9c54c65cc8cc8abf.d94811120823b885
+ 47810f3770134ee8.b63b1f7298414921.9def5334780355ae.0bf0aa9846108395
+ 564c5f9f6f4580de.ec6f1698c3cc7c4f.6617b826e12955b7.ddc20e4d86b96483
+ 2d8ab81fe32b187b
+VCMPSS_128_0xD(mem)
+ before
+ d51424f87a715aab.78d64385d1790130.ccbe52105ae79f5e.5319f39f9ecac785
+ b22bcec66697e83d.076bb653313a0e89.33f54ec6789b7079.c03fff0c4b73e7c4
+ a19d3374c4a97c5d.6157b5772b14e395.fee086a639f6a9cc.09d6d8d885aff022
+ 7c34ceeeafb4d238.e0e63a5c5c94bb02.074b769dba030784.8a297b6ee70b1f49
+ 9f86e33c0e11b0e5
+ after
+ d51424f87a715aab.78d64385d1790130.ccbe52105ae79f5e.5319f39f9ecac785
+ b22bcec66697e83d.076bb653313a0e89.33f54ec6789b7079.c03fff0c4b73e7c4
+ 0000000000000000.0000000000000000.33f54ec6789b7079.c03fff0cffffffff
+ 7c34ceeeafb4d238.e0e63a5c5c94bb02.074b769dba030784.8a297b6ee70b1f49
+ 9f86e33c0e11b0e5
+
+VCMPSS_128_0xE(reg)
+ before
+ a4370cad9550dea4.20bd1b2043c3a8fa.e163436e6045d47a.2b029a9516cf46cd
+ f48af22d1951e72f.690496f69de3b8ce.c11ccb19d2b368a9.46d06f7c6a6421d3
+ edc9912836a20535.33d5bc5cd91fbfe1.da5bcfc94f6bb33c.3482703dd1d155c1
+ ea41e60b86ce7460.5bfb073f1283795e.896d49ea72f8f2df.d2e519c3681f9ec3
+ fac3e6fc4a5cb707
+ after
+ 0000000000000000.0000000000000000.c11ccb19d2b368a9.46d06f7cffffffff
+ f48af22d1951e72f.690496f69de3b8ce.c11ccb19d2b368a9.46d06f7c6a6421d3
+ edc9912836a20535.33d5bc5cd91fbfe1.da5bcfc94f6bb33c.3482703dd1d155c1
+ ea41e60b86ce7460.5bfb073f1283795e.896d49ea72f8f2df.d2e519c3681f9ec3
+ fac3e6fc4a5cb707
+VCMPSS_128_0xE(mem)
+ before
+ 89e954d394935db6.473dec40a762725c.bb44f589641ca172.2a9e37e8d7e6613d
+ 5b22dd3461d14cff.5f0b9f3435e839d6.307a0128ecf5f449.1a3994301bc23c03
+ 4c3cff0bce21400c.90f6fb54cbef067a.966aa806c61a2e0e.b38c5c2cd917bfdc
+ 38013545f68ff409.3549fd0b060014f3.c9e064110c970aee.52e18b4aae712575
+ 53861ef4365dab7a
+ after
+ 89e954d394935db6.473dec40a762725c.bb44f589641ca172.2a9e37e8d7e6613d
+ 5b22dd3461d14cff.5f0b9f3435e839d6.307a0128ecf5f449.1a3994301bc23c03
+ 0000000000000000.0000000000000000.307a0128ecf5f449.1a399430ffffffff
+ 38013545f68ff409.3549fd0b060014f3.c9e064110c970aee.52e18b4aae712575
+ 53861ef4365dab7a
+
+VCMPSS_128_0xE(reg)
+ before
+ 12c510980b668c96.fb3efcccf5282524.a9519fc481a9a0ee.a5a8b334dd794614
+ ebeb5da1cc190676.71c0ce8de8f78f86.4a5adfedd875e617.068e105b53cc9bad
+ 3a43017b120053c5.76502975eb08ee5e.72b0b8f1a8f12219.c85df7728a9ac8e5
+ 5b1bf9927ca9b030.e5bd886f1968fdd6.7f9f273c8da890a0.c6e3e5659ff188e7
+ deea5420addd96e0
+ after
+ 0000000000000000.0000000000000000.4a5adfedd875e617.068e105bffffffff
+ ebeb5da1cc190676.71c0ce8de8f78f86.4a5adfedd875e617.068e105b53cc9bad
+ 3a43017b120053c5.76502975eb08ee5e.72b0b8f1a8f12219.c85df7728a9ac8e5
+ 5b1bf9927ca9b030.e5bd886f1968fdd6.7f9f273c8da890a0.c6e3e5659ff188e7
+ deea5420addd96e0
+VCMPSS_128_0xE(mem)
+ before
+ eb3fc28fd068aefb.aabd3f52a3a05863.9cd268668e22791a.cb72263a22266b5a
+ c9aeaa9f26a08e65.8377d12725708809.765a434867421e57.b476b35703f8f0f1
+ 5403883ac891f049.4293aa7d9ea57ccf.4f239700bfd5a7b9.94f8c9ffcda95a11
+ 6709d94ed44591d5.435ec7c1a9cb7060.03f7df7ab3e6d16b.c842649f1bc5e667
+ ada181a18ad9d09f
+ after
+ eb3fc28fd068aefb.aabd3f52a3a05863.9cd268668e22791a.cb72263a22266b5a
+ c9aeaa9f26a08e65.8377d12725708809.765a434867421e57.b476b35703f8f0f1
+ 0000000000000000.0000000000000000.765a434867421e57.b476b35700000000
+ 6709d94ed44591d5.435ec7c1a9cb7060.03f7df7ab3e6d16b.c842649f1bc5e667
+ ada181a18ad9d09f
+
+VCMPSS_128_0xE(reg)
+ before
+ 9d601a73b5705464.e08e18c566ca2d32.e224225de36f9f69.6da397a25f81589a
+ f5cd2d7f3916ae63.9a5cc18d992c7f8f.7a30b9bfe71c4695.6bf33b64ddb3f772
+ 1233b533b1581947.7040509189754416.69d08752515fa192.d8b248ad4c876c1e
+ 4eddaffabac1d2bd.400641bd53b338f3.0a4e8881bec3ec09.8fae3967c50971cb
+ 6eb18a806646c2a4
+ after
+ 0000000000000000.0000000000000000.7a30b9bfe71c4695.6bf33b6400000000
+ f5cd2d7f3916ae63.9a5cc18d992c7f8f.7a30b9bfe71c4695.6bf33b64ddb3f772
+ 1233b533b1581947.7040509189754416.69d08752515fa192.d8b248ad4c876c1e
+ 4eddaffabac1d2bd.400641bd53b338f3.0a4e8881bec3ec09.8fae3967c50971cb
+ 6eb18a806646c2a4
+VCMPSS_128_0xE(mem)
+ before
+ 4f89b7e24b491dd6.06181540efdd1471.e47a11fd13f21753.b9f8b9bac9d462a9
+ 10003c7b8f1e3c8c.9630e571ed391d0e.3a673b3de33d9c62.d11814680f1e401c
+ 8be296354fd2dcf3.5a711af94f602741.1c9b3b69e2a0844b.b0fa97f72c2ec20e
+ 9efd40fea670b837.ae26b044b2de6fb5.68e08d6d2a278b3b.b0ec3dd3ba8f232c
+ 2f39036958cea022
+ after
+ 4f89b7e24b491dd6.06181540efdd1471.e47a11fd13f21753.b9f8b9bac9d462a9
+ 10003c7b8f1e3c8c.9630e571ed391d0e.3a673b3de33d9c62.d11814680f1e401c
+ 0000000000000000.0000000000000000.3a673b3de33d9c62.d1181468ffffffff
+ 9efd40fea670b837.ae26b044b2de6fb5.68e08d6d2a278b3b.b0ec3dd3ba8f232c
+ 2f39036958cea022
+
+VCMPSS_128_0x11(reg)
+ before
+ 882ce323a076759b.231cb6c1b0058e83.ee9da4beb1403017.f803ae36d7df6c5d
+ 1613db6e2e13de44.f80a746a8a9c1804.7620f0d4e811a713.aad018ae06d3e4df
+ 3738e6b79e3216c9.f795f7e5504112e6.a2fc92f0f4de1054.581349c3d210afea
+ 45e800698e5e5ad5.fd87ba1f1d003a54.ce7d85807031a787.e098bc6058a089ac
+ 1c2aee70b3922d51
+ after
+ 0000000000000000.0000000000000000.7620f0d4e811a713.aad018ae00000000
+ 1613db6e2e13de44.f80a746a8a9c1804.7620f0d4e811a713.aad018ae06d3e4df
+ 3738e6b79e3216c9.f795f7e5504112e6.a2fc92f0f4de1054.581349c3d210afea
+ 45e800698e5e5ad5.fd87ba1f1d003a54.ce7d85807031a787.e098bc6058a089ac
+ 1c2aee70b3922d51
+VCMPSS_128_0x11(mem)
+ before
+ e99759e1ffef5805.9d6e25ef9723e614.e7ad39020de64a7a.56efc6eff999a757
+ 23a97b9e59c5c6f3.9c1852b7570ef534.8fd2f07b3dfeff86.969e4fa82b9f4d71
+ a72dcf93dd1f3247.9c31822c6aaac4de.d2c45b77c85515a2.ead61e19a1d1d581
+ 4fefd1aca60a5a2f.fa04b1ba6b838fc1.8c4ef7e0cbf647fa.aee22eadf7ba7b32
+ 3e0f7bd0cae67a31
+ after
+ e99759e1ffef5805.9d6e25ef9723e614.e7ad39020de64a7a.56efc6eff999a757
+ 23a97b9e59c5c6f3.9c1852b7570ef534.8fd2f07b3dfeff86.969e4fa82b9f4d71
+ 0000000000000000.0000000000000000.8fd2f07b3dfeff86.969e4fa800000000
+ 4fefd1aca60a5a2f.fa04b1ba6b838fc1.8c4ef7e0cbf647fa.aee22eadf7ba7b32
+ 3e0f7bd0cae67a31
+
+VCMPSS_128_0x11(reg)
+ before
+ f5a901eeb5e20f29.f8bbfed6d190f7d4.13dedbcdf7269287.993b3fa461ed52bb
+ 31fcbd74553975c7.7e5cd1fb79c0c865.410bfdd1a81e08dd.d658afaea746f211
+ 4d54aacc4578eab7.bda0c508baa3870c.e1d712331df72e6e.1d71c3eab80ee227
+ a5fdc463222aa8a4.915159eab147f2f5.4f8e155df03e40e7.4b52f844b150df2a
+ 3cc7c8a8ad19a545
+ after
+ 0000000000000000.0000000000000000.410bfdd1a81e08dd.d658afae00000000
+ 31fcbd74553975c7.7e5cd1fb79c0c865.410bfdd1a81e08dd.d658afaea746f211
+ 4d54aacc4578eab7.bda0c508baa3870c.e1d712331df72e6e.1d71c3eab80ee227
+ a5fdc463222aa8a4.915159eab147f2f5.4f8e155df03e40e7.4b52f844b150df2a
+ 3cc7c8a8ad19a545
+VCMPSS_128_0x11(mem)
+ before
+ cc9bb102c974f0a5.944207a687dbec3a.d63c068b79b7c24e.e87b05bcbd7e79f3
+ d79c2e3e206d7b76.787170ff1018f127.682d4ad92f00b640.06ecdbbd2143173f
+ 3994bc49ce1103e3.abd4f9dc5a6cf515.23f09fbfee2d88fa.062b95cbb71a5477
+ ce50d50df06b4419.8bb8a0a8016332b0.e3518329d34af5a6.44852d511c8e6c46
+ 1c46a1bdeb2b9d59
+ after
+ cc9bb102c974f0a5.944207a687dbec3a.d63c068b79b7c24e.e87b05bcbd7e79f3
+ d79c2e3e206d7b76.787170ff1018f127.682d4ad92f00b640.06ecdbbd2143173f
+ 0000000000000000.0000000000000000.682d4ad92f00b640.06ecdbbd00000000
+ ce50d50df06b4419.8bb8a0a8016332b0.e3518329d34af5a6.44852d511c8e6c46
+ 1c46a1bdeb2b9d59
+
+VCMPSS_128_0x11(reg)
+ before
+ eabaed7ac17e215b.729cf778a287fa43.726960cfa089e4a5.841b7103f964b970
+ 0a2c0bf4391234f9.01449d74ff72e08e.be3236bdd36b49a0.e21ce6397d868f86
+ d8eaf997f07414df.561343ef2337b325.c9611cde37959b4c.d91e5db77abc3411
+ b03eb2cf812ffbb8.4fd766d42be22f36.f140109e68911756.45ee51690d136440
+ 0158413c5196da3d
+ after
+ 0000000000000000.0000000000000000.be3236bdd36b49a0.e21ce63900000000
+ 0a2c0bf4391234f9.01449d74ff72e08e.be3236bdd36b49a0.e21ce6397d868f86
+ d8eaf997f07414df.561343ef2337b325.c9611cde37959b4c.d91e5db77abc3411
+ b03eb2cf812ffbb8.4fd766d42be22f36.f140109e68911756.45ee51690d136440
+ 0158413c5196da3d
+VCMPSS_128_0x11(mem)
+ before
+ eb28a61a63515434.ee75320989cf2631.c75a810f33800fea.901c0d6900edf86a
+ de29fdf15e518c52.eedb75afa3e0d1f5.9a69108c551c1070.04420fac9e347c33
+ b629c3ab5ea13ec3.0bbc782f6bef37b1.a3d08f37b0c2eef2.a7fb13d1dcf3dd5d
+ 4ef27336804d28b2.a36436f37e879510.c05b7afc5d7f649c.d696144656b55795
+ ee5e0d75a9062887
+ after
+ eb28a61a63515434.ee75320989cf2631.c75a810f33800fea.901c0d6900edf86a
+ de29fdf15e518c52.eedb75afa3e0d1f5.9a69108c551c1070.04420fac9e347c33
+ 0000000000000000.0000000000000000.9a69108c551c1070.04420facffffffff
+ 4ef27336804d28b2.a36436f37e879510.c05b7afc5d7f649c.d696144656b55795
+ ee5e0d75a9062887
+
+VCMPSS_128_0x12(reg)
+ before
+ 499efdcc70738adf.8451897de062044c.111eab69783527c0.ccd64ec77b5e309b
+ 44a4ddb64887ba48.3212826c99eb8fbd.b138d3fcf484296a.a20c8585236b0c1b
+ 3bbaaa9fcccff46e.3601d8efc7f58430.defcaa188e00d6bd.20cb9d2074b3b447
+ 8a2d61f398d573ff.6be909f2878aa1d2.f6b72d29e3356b63.20dd12868741e64c
+ 800f5ea17a225c56
+ after
+ 0000000000000000.0000000000000000.b138d3fcf484296a.a20c8585ffffffff
+ 44a4ddb64887ba48.3212826c99eb8fbd.b138d3fcf484296a.a20c8585236b0c1b
+ 3bbaaa9fcccff46e.3601d8efc7f58430.defcaa188e00d6bd.20cb9d2074b3b447
+ 8a2d61f398d573ff.6be909f2878aa1d2.f6b72d29e3356b63.20dd12868741e64c
+ 800f5ea17a225c56
+VCMPSS_128_0x12(mem)
+ before
+ 1a2dff5f6960d390.8d49fd1e492774a4.ac989061f4b8a0ce.54b5579b8fb02408
+ cc0370ab6f090626.a1597a8c7b51330c.d7d8e9282b8b3d51.534124da2cfc3c59
+ 705c2d71a929b346.20abd5a9c9ddebe1.c6769134480e3686.51a9905259a6f002
+ e406b29d31cb9419.678908e2d05ad9cf.563e036f654d459a.a838986faf397cae
+ b639379ecd411b0a
+ after
+ 1a2dff5f6960d390.8d49fd1e492774a4.ac989061f4b8a0ce.54b5579b8fb02408
+ cc0370ab6f090626.a1597a8c7b51330c.d7d8e9282b8b3d51.534124da2cfc3c59
+ 0000000000000000.0000000000000000.d7d8e9282b8b3d51.534124da00000000
+ e406b29d31cb9419.678908e2d05ad9cf.563e036f654d459a.a838986faf397cae
+ b639379ecd411b0a
+
+VCMPSS_128_0x12(reg)
+ before
+ d5f968494c4b0bc2.02cb7c1b26fb65ce.d24011a12a513984.64fcbbc7a15427b9
+ 63c42adecbe28681.a77805d7a2c5e48f.bd1ceb54765047a9.ca7c35271530970e
+ bae676c8e392c9f3.b0d9cbbec136cb89.846993654ee23eed.6589ed7adfec53c6
+ 38aa4a7232e80fc6.f7ba4abaa059d7e7.827303424e935cfa.12f160ae1b95150c
+ ab7e09aee436990d
+ after
+ 0000000000000000.0000000000000000.bd1ceb54765047a9.ca7c352700000000
+ 63c42adecbe28681.a77805d7a2c5e48f.bd1ceb54765047a9.ca7c35271530970e
+ bae676c8e392c9f3.b0d9cbbec136cb89.846993654ee23eed.6589ed7adfec53c6
+ 38aa4a7232e80fc6.f7ba4abaa059d7e7.827303424e935cfa.12f160ae1b95150c
+ ab7e09aee436990d
+VCMPSS_128_0x12(mem)
+ before
+ 0dfd646657db9df5.375ea14a546f95a3.59e7fcb85a3bc4d6.1585395613f0da7c
+ 143aedc28f90dbef.144c77bbe4b39739.b22b5fa50ce74d81.98ed300d3884f720
+ 9d0120afa8621028.2cc1c8317e415132.df53ee6cd2692f15.67f5e4d35adced92
+ 821d7a17bf5cf8cc.d9099019bfa4fe3b.ba2c25f9c6cd26be.deea52141483f97e
+ 5818743c0305578e
+ after
+ 0dfd646657db9df5.375ea14a546f95a3.59e7fcb85a3bc4d6.1585395613f0da7c
+ 143aedc28f90dbef.144c77bbe4b39739.b22b5fa50ce74d81.98ed300d3884f720
+ 0000000000000000.0000000000000000.b22b5fa50ce74d81.98ed300d00000000
+ 821d7a17bf5cf8cc.d9099019bfa4fe3b.ba2c25f9c6cd26be.deea52141483f97e
+ 5818743c0305578e
+
+VCMPSS_128_0x12(reg)
+ before
+ 33cb48b8c2ee4271.a05c76e7f08b4e06.7870ccdd4368dbff.208080370720eda7
+ ca4fc9f2eecbf7d1.d388900c56facf02.654277eaa51a242b.ed1c7b14ae6e41fd
+ 79eff3582227b25b.f76e44710db537ed.fcca8dad8145146a.fdcb937bd9c1deeb
+ 9bf8c354fb8fafba.e8da0f0132c941f3.9a560b907475e869.2c5b4359a427809e
+ 569607982aabe242
+ after
+ 0000000000000000.0000000000000000.654277eaa51a242b.ed1c7b1400000000
+ ca4fc9f2eecbf7d1.d388900c56facf02.654277eaa51a242b.ed1c7b14ae6e41fd
+ 79eff3582227b25b.f76e44710db537ed.fcca8dad8145146a.fdcb937bd9c1deeb
+ 9bf8c354fb8fafba.e8da0f0132c941f3.9a560b907475e869.2c5b4359a427809e
+ 569607982aabe242
+VCMPSS_128_0x12(mem)
+ before
+ 574a5c25885ac102.8eb73354148e299b.82986caae041ab40.9930eb011937dcd4
+ 0b41bcedd93fd90b.ac7641c309b05daa.a174d75734292eff.56a52b6b0d162c56
+ 4e48a5da3966e688.5381e90d77828792.2139ccf4498e895c.2d01c639eb9e139c
+ fc2a92dac5dca3a6.dd26259efa8fe2ff.deb5c76d3c7b7684.7a90b8d9505cce51
+ 999efeb6d7db9922
+ after
+ 574a5c25885ac102.8eb73354148e299b.82986caae041ab40.9930eb011937dcd4
+ 0b41bcedd93fd90b.ac7641c309b05daa.a174d75734292eff.56a52b6b0d162c56
+ 0000000000000000.0000000000000000.a174d75734292eff.56a52b6bffffffff
+ fc2a92dac5dca3a6.dd26259efa8fe2ff.deb5c76d3c7b7684.7a90b8d9505cce51
+ 999efeb6d7db9922
+
+VCMPSS_128_0x16(reg)
+ before
+ e676923d1da8b0bb.f0b5ffd898accd91.a8b0f2e22d63ab9f.b3b245ae28fcb3a3
+ bd6572d8bd4d4ec7.08b369bfcfe22074.0e6a4d45ac8b1e1c.7efdc1a32a1df9e4
+ 7ab79af45459b0f3.1ff24b7d868b577c.6da1313314927722.1a62b7395deb0774
+ 78b804fd7d5511ea.113c20fdd8b22fd4.1fa19b180004f15e.63ada35add72977f
+ 34a902f4c8bd6630
+ after
+ 0000000000000000.0000000000000000.0e6a4d45ac8b1e1c.7efdc1a300000000
+ bd6572d8bd4d4ec7.08b369bfcfe22074.0e6a4d45ac8b1e1c.7efdc1a32a1df9e4
+ 7ab79af45459b0f3.1ff24b7d868b577c.6da1313314927722.1a62b7395deb0774
+ 78b804fd7d5511ea.113c20fdd8b22fd4.1fa19b180004f15e.63ada35add72977f
+ 34a902f4c8bd6630
+VCMPSS_128_0x16(mem)
+ before
+ 6b244ef137d830b4.15b4ad60d4cfaf59.b95e672be16364a9.81b685610d6ec97c
+ e3e8053f48cfb036.acf79288f652c4eb.f52499f4beabb126.f02ced78d65b3b27
+ 77c2a3c917afa3e3.99ccaee07f6b8d4e.a05934428a95d478.c64fcecbf857820c
+ 057ea27bbe83c5e6.3781fdd60aa4452b.95cbb202622d87cb.606a24c50eefdbd6
+ 1acaebd2b5ae8232
+ after
+ 6b244ef137d830b4.15b4ad60d4cfaf59.b95e672be16364a9.81b685610d6ec97c
+ e3e8053f48cfb036.acf79288f652c4eb.f52499f4beabb126.f02ced78d65b3b27
+ 0000000000000000.0000000000000000.f52499f4beabb126.f02ced7800000000
+ 057ea27bbe83c5e6.3781fdd60aa4452b.95cbb202622d87cb.606a24c50eefdbd6
+ 1acaebd2b5ae8232
+
+VCMPSS_128_0x16(reg)
+ before
+ 51bb205d8820b3cc.68e880415c57d26d.e4607cd5338c2a31.b24491216180864a
+ 5f89bdd524d2a94f.7bcbb7070b3885a1.fbb6264997ac760a.d1924d89a3998f22
+ a180c0a3244fa168.1cf5c6b9e7319bb1.d7cff69ed2926562.d07f602846855c7f
+ 73ec25342423d7c2.253026440d4ed0c6.d6f7eb407ec935e6.89d848e9634eaa8c
+ da6880b718033476
+ after
+ 0000000000000000.0000000000000000.fbb6264997ac760a.d1924d8900000000
+ 5f89bdd524d2a94f.7bcbb7070b3885a1.fbb6264997ac760a.d1924d89a3998f22
+ a180c0a3244fa168.1cf5c6b9e7319bb1.d7cff69ed2926562.d07f602846855c7f
+ 73ec25342423d7c2.253026440d4ed0c6.d6f7eb407ec935e6.89d848e9634eaa8c
+ da6880b718033476
+VCMPSS_128_0x16(mem)
+ before
+ 9dfd848081adb868.3118e6f4c1db870a.74495492989cdf0f.5379fe9b3ade2042
+ b061d02fb95af08f.3752014f9702ecec.e30ccd90a52685b6.a9a32c1c9f5c6321
+ ed62e1b1dc159816.e1e470b241244313.4f450c2b4ff97ee8.36bf722d4ccf3930
+ 31ca31f007ea6e2a.8b1b32885bcec72c.95c08d4eb32086d0.541acb3cdac4e01b
+ 610033b3e7c6928d
+ after
+ 9dfd848081adb868.3118e6f4c1db870a.74495492989cdf0f.5379fe9b3ade2042
+ b061d02fb95af08f.3752014f9702ecec.e30ccd90a52685b6.a9a32c1c9f5c6321
+ 0000000000000000.0000000000000000.e30ccd90a52685b6.a9a32c1c00000000
+ 31ca31f007ea6e2a.8b1b32885bcec72c.95c08d4eb32086d0.541acb3cdac4e01b
+ 610033b3e7c6928d
+
+VCMPSS_128_0x16(reg)
+ before
+ b7bda7000f618b32.59663ed955e62cf7.9143403c828bb6e2.8f48cde4eca7589b
+ b39d218eed2209b8.3f018359e3148fa8.4fa8973c52e84ae2.1aab46db179ab174
+ b2eb9fc91e9346c8.c0697d5acd81536a.219534f36570c0d8.12b3761e4f064d88
+ 0ef41c1d3d437f11.b869a7ca2d383368.625812cd5aaf536f.542dd899b0f6e703
+ bae5e83857773d10
+ after
+ 0000000000000000.0000000000000000.4fa8973c52e84ae2.1aab46db00000000
+ b39d218eed2209b8.3f018359e3148fa8.4fa8973c52e84ae2.1aab46db179ab174
+ b2eb9fc91e9346c8.c0697d5acd81536a.219534f36570c0d8.12b3761e4f064d88
+ 0ef41c1d3d437f11.b869a7ca2d383368.625812cd5aaf536f.542dd899b0f6e703
+ bae5e83857773d10
+VCMPSS_128_0x16(mem)
+ before
+ 21a723e8609408dc.240595f6e6bbef3d.04cc7c932245eccf.703b2d36cb314054
+ 653e0393e6590792.516804c0b68ad4f9.7e5f7aa3c5b53acb.a68b829a5483c332
+ 6278062605d3f45f.ef6967e7493968f0.03ee1de53592d887.60940b65923018b6
+ f41fa78eda0c8d6f.5b56b9d83a56e7cf.6f45df458beb8330.f9a2c60320c57a8b
+ cf00aee19acd265f
+ after
+ 21a723e8609408dc.240595f6e6bbef3d.04cc7c932245eccf.703b2d36cb314054
+ 653e0393e6590792.516804c0b68ad4f9.7e5f7aa3c5b53acb.a68b829a5483c332
+ 0000000000000000.0000000000000000.7e5f7aa3c5b53acb.a68b829affffffff
+ f41fa78eda0c8d6f.5b56b9d83a56e7cf.6f45df458beb8330.f9a2c60320c57a8b
+ cf00aee19acd265f
+
+VCMPSS_128_0x1E(reg)
+ before
+ 3dfcbf699dd458db.f70063b681138bed.f17af6fd256c8f41.9e303eafe6c9f7f1
+ 9ee0f609c5664cae.47e7b48914f1ad06.0d201ac4a7079af3.6c7ab50f5f3af0f7
+ 50f94e2cad103d82.c0a018f5b2b4ade5.0b9522975bb44591.b5f1c051144a296e
+ ae93c33ef25e6803.3ef70ae5756848b7.482509e4defeccc6.555fdb6221035f81
+ 2891832ca1734e5d
+ after
+ 0000000000000000.0000000000000000.0d201ac4a7079af3.6c7ab50fffffffff
+ 9ee0f609c5664cae.47e7b48914f1ad06.0d201ac4a7079af3.6c7ab50f5f3af0f7
+ 50f94e2cad103d82.c0a018f5b2b4ade5.0b9522975bb44591.b5f1c051144a296e
+ ae93c33ef25e6803.3ef70ae5756848b7.482509e4defeccc6.555fdb6221035f81
+ 2891832ca1734e5d
+VCMPSS_128_0x1E(mem)
+ before
+ 0a53339db0a5b22d.13fa51aa2fda09de.9db7064579173aa8.1e1ccb16cb716a3f
+ d771679f6ba6461e.dd7af4de00125bbf.b9ae8901dbcf3ee3.eac66499bf9a5ca7
+ 6ab69b20ee81c75c.665ea94502919b51.6ea60d05b69b1195.086fd0d95504deab
+ a1f04c0b5442f112.0bf46a4cd0e40541.986c103e26886fe9.d4620c422a3c2bf7
+ a9ed1340d9cc8136
+ after
+ 0a53339db0a5b22d.13fa51aa2fda09de.9db7064579173aa8.1e1ccb16cb716a3f
+ d771679f6ba6461e.dd7af4de00125bbf.b9ae8901dbcf3ee3.eac66499bf9a5ca7
+ 0000000000000000.0000000000000000.b9ae8901dbcf3ee3.eac66499ffffffff
+ a1f04c0b5442f112.0bf46a4cd0e40541.986c103e26886fe9.d4620c422a3c2bf7
+ a9ed1340d9cc8136
+
+VCMPSS_128_0x1E(reg)
+ before
+ e55ae13fff421a15.57e9f44cb9f67f6d.2986355d0796d53a.13cc0d9649a1130c
+ e3f672ac372a323f.686e11cf3aa82e98.1a6106e5433346ea.ba9281fa38f2bb2a
+ ff0dc3f11d0f0761.af4b1e80f264bac0.3cd1d7511e4895fa.6b89e6571188216e
+ 95eacf7c4e7dd326.0a4c984bfe37de11.e922a60b3760fe18.017fba98f06e0104
+ 573e78a8f0b1191a
+ after
+ 0000000000000000.0000000000000000.1a6106e5433346ea.ba9281faffffffff
+ e3f672ac372a323f.686e11cf3aa82e98.1a6106e5433346ea.ba9281fa38f2bb2a
+ ff0dc3f11d0f0761.af4b1e80f264bac0.3cd1d7511e4895fa.6b89e6571188216e
+ 95eacf7c4e7dd326.0a4c984bfe37de11.e922a60b3760fe18.017fba98f06e0104
+ 573e78a8f0b1191a
+VCMPSS_128_0x1E(mem)
+ before
+ 4b939c752d5b23da.01db92b86600d33c.543df91c792c58b6.7e9f6e812807bcf0
+ b84aa2eac47adc70.9e2a08100025424c.68e9bfe08050e2db.57962b1e8dca0d2e
+ 792f07f3d11aff09.ca242ef2b8785d05.241e65812ead38ae.d151d94d02342a7d
+ 6c0d467c6e464ad1.e015fec92b836011.63a667eda0511859.461d757c25d15289
+ 1346f9168f2ebf00
+ after
+ 4b939c752d5b23da.01db92b86600d33c.543df91c792c58b6.7e9f6e812807bcf0
+ b84aa2eac47adc70.9e2a08100025424c.68e9bfe08050e2db.57962b1e8dca0d2e
+ 0000000000000000.0000000000000000.68e9bfe08050e2db.57962b1e00000000
+ 6c0d467c6e464ad1.e015fec92b836011.63a667eda0511859.461d757c25d15289
+ 1346f9168f2ebf00
+
+VCMPSS_128_0x1E(reg)
+ before
+ 94186387ded6ae8b.6bb2db71ba0a77f3.3b497601f4d4871c.004e420ef1483c08
+ 25dfaf3cae565bd9.54e842bfcf72429c.390c9106b0f60dd3.d9e271d23d9d61e8
+ 22e6d79f9a380294.017cf850c98b69f8.34aa4b45fb7630e2.c82e6f24a15c4225
+ e77bd91d3e0ade68.4f3a7712c560a632.8a6ea1286fdf29f4.aafdbbf039919dea
+ 5c1dce2220492c64
+ after
+ 0000000000000000.0000000000000000.390c9106b0f60dd3.d9e271d2ffffffff
+ 25dfaf3cae565bd9.54e842bfcf72429c.390c9106b0f60dd3.d9e271d23d9d61e8
+ 22e6d79f9a380294.017cf850c98b69f8.34aa4b45fb7630e2.c82e6f24a15c4225
+ e77bd91d3e0ade68.4f3a7712c560a632.8a6ea1286fdf29f4.aafdbbf039919dea
+ 5c1dce2220492c64
+VCMPSS_128_0x1E(mem)
+ before
+ b85825a6728fabbe.d0e8b02337582c03.1bee3defdefdb676.96a58e1cabbd37b6
+ 9b7b3d684c70d825.397a581b21ad280e.3f64c5d5316f54f2.b39b0e8e489d94d3
+ e2529155caf66dc5.7e7dcd7397950d38.99678cafd9c13ecf.3e9c1de9e4097df9
+ 67a99d57073027c9.fb3c0b96359c182b.03c50c68f2002e3c.94f4b7981b902ed1
+ 0fefd90988bbe20a
+ after
+ b85825a6728fabbe.d0e8b02337582c03.1bee3defdefdb676.96a58e1cabbd37b6
+ 9b7b3d684c70d825.397a581b21ad280e.3f64c5d5316f54f2.b39b0e8e489d94d3
+ 0000000000000000.0000000000000000.3f64c5d5316f54f2.b39b0e8effffffff
+ 67a99d57073027c9.fb3c0b96359c182b.03c50c68f2002e3c.94f4b7981b902ed1
+ 0fefd90988bbe20a
+
+VMOVDDUP_XMMorMEM64_to_XMM(reg)
+ before
+ 0dd87ea7c818d74d.074cde5c1f27c25e.0c050ff0984f8593.5a48c3ee9937e063
+ e8fda2de76334649.9e06ce4e2fe9f9b0.0d22d4ed5b398f1d.7abd2c2cea721271
+ fda8411a2e966ea8.09a5eb1b528189ea.5ae156f91be77475.3ff0c40f00be7e91
+ a82658c78dcf8917.22f3b0aea5fc2e38.4e8c928073e36e46.86ad0581f825e1f0
+ 29bf6d6fedb6f7b9
+ after
+ 0000000000000000.0000000000000000.7abd2c2cea721271.7abd2c2cea721271
+ e8fda2de76334649.9e06ce4e2fe9f9b0.0d22d4ed5b398f1d.7abd2c2cea721271
+ fda8411a2e966ea8.09a5eb1b528189ea.5ae156f91be77475.3ff0c40f00be7e91
+ a82658c78dcf8917.22f3b0aea5fc2e38.4e8c928073e36e46.86ad0581f825e1f0
+ 29bf6d6fedb6f7b9
+VMOVDDUP_XMMorMEM64_to_XMM(mem)
+ before
+ 05f477c6fb7a7b19.46c3e1522f6ad441.c6bd9af34365a3c7.477082ee00bcb93d
+ f6169f703f7f2a3c.31cada25aff18bd3.d1cf23d649c8a5c3.a0d924af5dfb9306
+ d8f2615bd4d0c04d.c6893eada9f3ea78.1ff4c943d231f058.b4127330272e364c
+ 87543a71d77af879.614a0a57baf92cdd.8cfa0726faad40b1.e1696cdbf9e0dfbc
+ 8228091e709ec901
+ after
+ 05f477c6fb7a7b19.46c3e1522f6ad441.c6bd9af34365a3c7.477082ee00bcb93d
+ f6169f703f7f2a3c.31cada25aff18bd3.d1cf23d649c8a5c3.a0d924af5dfb9306
+ d8f2615bd4d0c04d.c6893eada9f3ea78.1ff4c943d231f058.b4127330272e364c
+ 0000000000000000.0000000000000000.477082ee00bcb93d.477082ee00bcb93d
+ 8228091e709ec901
+
+VMOVDDUP_XMMorMEM64_to_XMM(reg)
+ before
+ f29c486427f331c8.df08a4a0638890eb.5e5b388e7d918eae.f4ab596bde4850fa
+ 8f112418ba6b53bd.bcda1dd3950641d0.1906c6bd8f464b96.33d53bfe9a0cdd60
+ b3d399a8c6936b8b.fa9521f68901ca54.ee98af528ba4a142.25422acc4907a30f
+ bc2ea37fe7f6b5de.75072af55984e5a2.395cf0b80e38ca5d.a6bfa1bf07455e33
+ 92171cc5f1d0c9f6
+ after
+ 0000000000000000.0000000000000000.33d53bfe9a0cdd60.33d53bfe9a0cdd60
+ 8f112418ba6b53bd.bcda1dd3950641d0.1906c6bd8f464b96.33d53bfe9a0cdd60
+ b3d399a8c6936b8b.fa9521f68901ca54.ee98af528ba4a142.25422acc4907a30f
+ bc2ea37fe7f6b5de.75072af55984e5a2.395cf0b80e38ca5d.a6bfa1bf07455e33
+ 92171cc5f1d0c9f6
+VMOVDDUP_XMMorMEM64_to_XMM(mem)
+ before
+ c51817c923b6a187.046d3f09b7206c64.08fab6bc239b50e6.56a0835bb38d0394
+ 1a8c0fb7b802a210.e9de68b2d59dcdc6.913b40380353c44e.a1af66a7172f8793
+ 6f417e7accc187be.c5cb1ae7dbfa13b3.eb96445314b70004.76d49408d5ab9305
+ 9f01e2007cfe0dbc.f681511265c37bd5.f2d73efa73d3be34.315c09eb8a8c6396
+ 2e93c1bad15f33f4
+ after
+ c51817c923b6a187.046d3f09b7206c64.08fab6bc239b50e6.56a0835bb38d0394
+ 1a8c0fb7b802a210.e9de68b2d59dcdc6.913b40380353c44e.a1af66a7172f8793
+ 6f417e7accc187be.c5cb1ae7dbfa13b3.eb96445314b70004.76d49408d5ab9305
+ 0000000000000000.0000000000000000.56a0835bb38d0394.56a0835bb38d0394
+ 2e93c1bad15f33f4
+
+VMOVDDUP_XMMorMEM64_to_XMM(reg)
+ before
+ c9c5b9e346af3ec9.8699b635e3c6f037.d64c09a1108241d9.82c9aa1a3bb4bb0b
+ 5e3eebd08608c1c1.ffd577031e23eb5b.c2783ffe77c5a16a.763a059e8865b3b5
+ 484955ef2df6f889.e8809f574823bc53.1650ee973718d735.acf4ca7177f2615d
+ e533f3abd6061fcd.1b68ac1d7ed21d4c.2f2212d6eb051ee5.ffc4758124688230
+ 4a7683b9aad2d25a
+ after
+ 0000000000000000.0000000000000000.763a059e8865b3b5.763a059e8865b3b5
+ 5e3eebd08608c1c1.ffd577031e23eb5b.c2783ffe77c5a16a.763a059e8865b3b5
+ 484955ef2df6f889.e8809f574823bc53.1650ee973718d735.acf4ca7177f2615d
+ e533f3abd6061fcd.1b68ac1d7ed21d4c.2f2212d6eb051ee5.ffc4758124688230
+ 4a7683b9aad2d25a
+VMOVDDUP_XMMorMEM64_to_XMM(mem)
+ before
+ 6bd66e05253c0d06.9049bf701dc37139.76571942db3aca71.6738a729301ab327
+ 3cafb451b2b3ee61.a4d5b7aa9fba2b77.d41b62b07c6a81ef.1bdfaafba1e3d1a7
+ 9bcfd0896c423296.7f24d6c5f7768936.107e04557c6bfcf1.a76316b8dbeab610
+ 62003f9a70f695d2.7c81182dc283c620.084d791cf74bf8a4.6710e7cc79be9c0f
+ b73119a317e8c04f
+ after
+ 6bd66e05253c0d06.9049bf701dc37139.76571942db3aca71.6738a729301ab327
+ 3cafb451b2b3ee61.a4d5b7aa9fba2b77.d41b62b07c6a81ef.1bdfaafba1e3d1a7
+ 9bcfd0896c423296.7f24d6c5f7768936.107e04557c6bfcf1.a76316b8dbeab610
+ 0000000000000000.0000000000000000.6738a729301ab327.6738a729301ab327
+ b73119a317e8c04f
+
+VMOVD_IREGorMEM32_to_XMM(reg)
+ before
+ f414a8aa52f65d7d.6f0f7b6edadad240.f63a794e9b6e1fe2.96533ff10b153034
+ 7803914bc673b045.9cc802f3c4faa60d.4b99f6941fc2d027.975ed1c0d1d562cc
+ a04ccff40eebf552.c6f74f134d62cd65.d5ec896ce90b159c.e838ac7567984899
+ c8395e0fc6eb6851.ca68debc8e1f0373.f27d304096d529ec.63af4afce8699ec7
+ e68d294171552281
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000071552281
+ 7803914bc673b045.9cc802f3c4faa60d.4b99f6941fc2d027.975ed1c0d1d562cc
+ a04ccff40eebf552.c6f74f134d62cd65.d5ec896ce90b159c.e838ac7567984899
+ c8395e0fc6eb6851.ca68debc8e1f0373.f27d304096d529ec.63af4afce8699ec7
+ e68d294171552281
+VMOVD_IREGorMEM32_to_XMM(mem)
+ before
+ 4b9fc4301e678ef3.4b163a0a8bfe44ed.82e72bd9a53c0364.fc99e77ec1ad49c5
+ 6fb197b60aab9f4b.87316050f8b1c6d3.cb3fb356aec68a64.518ba891071fb1d0
+ 2e8e1fbd512d11b2.d7d5ca4caa8e2aaf.823df11ec4c7549e.4ba171e403b59cbb
+ 6504d63310fa9f57.974d766c3d24ac2c.81ad6120044e1c3e.47263ce552fd4732
+ a26507ff8f83eee1
+ after
+ 4b9fc4301e678ef3.4b163a0a8bfe44ed.82e72bd9a53c0364.fc99e77ec1ad49c5
+ 6fb197b60aab9f4b.87316050f8b1c6d3.cb3fb356aec68a64.518ba891071fb1d0
+ 2e8e1fbd512d11b2.d7d5ca4caa8e2aaf.823df11ec4c7549e.4ba171e403b59cbb
+ 0000000000000000.0000000000000000.0000000000000000.00000000c1ad49c5
+ a26507ff8f83eee1
+
+VMOVD_IREGorMEM32_to_XMM(reg)
+ before
+ b6abce9e56d1cd73.eedd3a03621d0664.23e65f1b4bfc87f7.a55b7f458964a071
+ e0448b2f44751f94.a6e6c61864a30205.d7ed82c673a4f8bb.ca13c77a6f179963
+ 7c7c3c1cf5fb21f2.69ebf66031974e68.0eabd9d74ea73a25.cca1b6abd372c640
+ e79fdcd204ed0f37.13b847c6e605a7b6.266f62bb7b928be0.87d0c7c5d182e133
+ d76d76b28452a768
+ after
+ 0000000000000000.0000000000000000.0000000000000000.000000008452a768
+ e0448b2f44751f94.a6e6c61864a30205.d7ed82c673a4f8bb.ca13c77a6f179963
+ 7c7c3c1cf5fb21f2.69ebf66031974e68.0eabd9d74ea73a25.cca1b6abd372c640
+ e79fdcd204ed0f37.13b847c6e605a7b6.266f62bb7b928be0.87d0c7c5d182e133
+ d76d76b28452a768
+VMOVD_IREGorMEM32_to_XMM(mem)
+ before
+ 98443f6008eed40d.7bf867be0dd9240f.801934369efac91e.7a8418df93ef259a
+ a6219fb97a63244b.95d5d94aad4b9e27.8cd9399c758170ca.6535f8ad344d45fc
+ ddd011abf5bc5251.91802fe47fceb72b.13c6d2e589a657e6.45d0fc93fa3526b5
+ 191d112196051b49.cb4664f720eeabc6.f1aa7bfbf3753ba0.759f22fb8035066e
+ 50ef655363d81fd6
+ after
+ 98443f6008eed40d.7bf867be0dd9240f.801934369efac91e.7a8418df93ef259a
+ a6219fb97a63244b.95d5d94aad4b9e27.8cd9399c758170ca.6535f8ad344d45fc
+ ddd011abf5bc5251.91802fe47fceb72b.13c6d2e589a657e6.45d0fc93fa3526b5
+ 0000000000000000.0000000000000000.0000000000000000.0000000093ef259a
+ 50ef655363d81fd6
+
+VMOVD_IREGorMEM32_to_XMM(reg)
+ before
+ 340cc1063eabad97.36d31b07784a3b5f.9f7374ee2b37b8a5.0252b1cbd1fbd821
+ 7b413280ad39ee5e.10c0ab49b8986dc0.69535b373d361873.228aef423f44ea98
+ 83dcb52d4d0e1cd6.83ae3ed371fb6e98.8531163df17607dd.2d1eb14b585a2c2f
+ a6274579b9b774ac.6b6a4f92c07dfa12.4f5b9f6de483c38f.ffda73d1384b5b12
+ 7389b1c2fc23336e
+ after
+ 0000000000000000.0000000000000000.0000000000000000.00000000fc23336e
+ 7b413280ad39ee5e.10c0ab49b8986dc0.69535b373d361873.228aef423f44ea98
+ 83dcb52d4d0e1cd6.83ae3ed371fb6e98.8531163df17607dd.2d1eb14b585a2c2f
+ a6274579b9b774ac.6b6a4f92c07dfa12.4f5b9f6de483c38f.ffda73d1384b5b12
+ 7389b1c2fc23336e
+VMOVD_IREGorMEM32_to_XMM(mem)
+ before
+ 67f8e809bfec6f6f.4270ded18ebf318b.a4c05a70c02ccc5b.231bf431b1ea8634
+ b6f393929eb4cc40.b1017c9f68b29120.097cdb5b8e14a29f.5dbe10f6f5368d78
+ 3c462e49b487060e.50271b50e11dce17.78694f3d453f3609.5990f0284bf41409
+ d4bd361a1e6fd805.7c2db851988b241b.cc55310401bc44c6.73dd8e344faf5691
+ 06f1e8859ef390bc
+ after
+ 67f8e809bfec6f6f.4270ded18ebf318b.a4c05a70c02ccc5b.231bf431b1ea8634
+ b6f393929eb4cc40.b1017c9f68b29120.097cdb5b8e14a29f.5dbe10f6f5368d78
+ 3c462e49b487060e.50271b50e11dce17.78694f3d453f3609.5990f0284bf41409
+ 0000000000000000.0000000000000000.0000000000000000.00000000b1ea8634
+ 06f1e8859ef390bc
+
+VMOVQ_XMM_MEM64(reg)
+ before
+ 7017f986d44cfe37.5c2425f2f77a0050.8f614e0d2688d1d9.e00afd9adf948a01
+ 0c9dbda58c47dcae.ae4779bb5cb4381c.e60dd9ef2aa10ffd.92552fedfbd5c2e7
+ 36cd314d626f65cd.a8f1ad6268283c94.dd7f55653d611b32.bd0243e8708aa9a4
+ 49f44feaf351d63e.25ef3dd438e2cae5.d001bfdafd543124.3cddb6775abffa63
+ edb10386d6817350
+ after
+ 7017f986d44cfe37.5c2425f2f77a0050.8f614e0d2688d1d9.e00afd9adf948a01
+ 0c9dbda58c47dcae.ae4779bb5cb4381c.e60dd9ef2aa10ffd.92552fedfbd5c2e7
+ 36cd314d626f65cd.a8f1ad6268283c94.dd7f55653d611b32.bd0243e8708aa9a4
+ 49f44feaf351d63e.25ef3dd438e2cae5.d001bfdafd543124.3cddb6775abffa63
+ edb10386d6817350
+VMOVQ_XMM_MEM64(mem)
+ before
+ aa4ca602ffdbce99.a35e15e8da786ab0.000da6fce7ee9c3a.1ce012ba06078c80
+ 51781bd5f2d9c768.9e577eb3b4705fcd.171762c592596fc1.1b684a71f30569f2
+ bc02deecca881ce9.982a87b71cc6ef42.44d9ef1d542efea3.2ae4636b61da0426
+ c9b66c34a4f38749.ec252a61af0457ba.651ec8ef4979070e.a5a25915eb1398c7
+ e8ec29d92d3b6281
+ after
+ aa4ca602ffdbce99.a35e15e8da786ab0.000da6fce7ee9c3a.1b684a71f30569f2
+ 51781bd5f2d9c768.9e577eb3b4705fcd.171762c592596fc1.1b684a71f30569f2
+ bc02deecca881ce9.982a87b71cc6ef42.44d9ef1d542efea3.2ae4636b61da0426
+ c9b66c34a4f38749.ec252a61af0457ba.651ec8ef4979070e.a5a25915eb1398c7
+ e8ec29d92d3b6281
+
+VMOVQ_XMM_MEM64(reg)
+ before
+ 4f0fce24c4df9e01.526040979b27c5b4.f592651b08b9d2e2.54b46a278e47442e
+ 365744634c8988f3.34ccd603cc2f9155.11be3353c46e9e65.ee654fb13fa3712f
+ f910870160c85b03.4cc6ab635217a959.9af590737eb1f5f0.10fef57a779a4c3c
+ f48694699c2554dc.741939a34aebc7eb.ed8379e9d30e132f.944bd76c52378f82
+ 57187174ed86f72c
+ after
+ 4f0fce24c4df9e01.526040979b27c5b4.f592651b08b9d2e2.54b46a278e47442e
+ 365744634c8988f3.34ccd603cc2f9155.11be3353c46e9e65.ee654fb13fa3712f
+ f910870160c85b03.4cc6ab635217a959.9af590737eb1f5f0.10fef57a779a4c3c
+ f48694699c2554dc.741939a34aebc7eb.ed8379e9d30e132f.944bd76c52378f82
+ 57187174ed86f72c
+VMOVQ_XMM_MEM64(mem)
+ before
+ 35313f7f63934067.830565099d2eaf2a.8992feafcfb8a738.67b3e8205e0f36cd
+ 0b61be77d16b255e.01d8f84cfe6ea89a.67fd7573fd89076c.62d3db84bc429877
+ b376694a5219633e.cc4c499e5c717ad8.eb261adbf16ba1b2.3c2d4d81883376d9
+ 0a3abce303aab633.3fad526b52c4628f.efd96ad3c7693237.4f0e3a835e6c0c9e
+ f8c29ff6db7b9572
+ after
+ 35313f7f63934067.830565099d2eaf2a.8992feafcfb8a738.62d3db84bc429877
+ 0b61be77d16b255e.01d8f84cfe6ea89a.67fd7573fd89076c.62d3db84bc429877
+ b376694a5219633e.cc4c499e5c717ad8.eb261adbf16ba1b2.3c2d4d81883376d9
+ 0a3abce303aab633.3fad526b52c4628f.efd96ad3c7693237.4f0e3a835e6c0c9e
+ f8c29ff6db7b9572
+
+VMOVQ_XMM_MEM64(reg)
+ before
+ 939577469bec4e03.ec7a332eff29d968.b64711207df29c6c.50e2df479a8f7626
+ 7cd3bee0394973fa.35024b1763a2890a.8c6680277888631b.ea0cf72486ea28ac
+ 10c8702e51203f06.c19d7f8a4a228244.1f569dede011f447.99242d54a88405f5
+ a9bf899e80fdefd1.6c194b73d1b48043.ca6264df50198b9d.39f6fec51c6cc92c
+ a64ee462fdab2f7e
+ after
+ 939577469bec4e03.ec7a332eff29d968.b64711207df29c6c.50e2df479a8f7626
+ 7cd3bee0394973fa.35024b1763a2890a.8c6680277888631b.ea0cf72486ea28ac
+ 10c8702e51203f06.c19d7f8a4a228244.1f569dede011f447.99242d54a88405f5
+ a9bf899e80fdefd1.6c194b73d1b48043.ca6264df50198b9d.39f6fec51c6cc92c
+ a64ee462fdab2f7e
+VMOVQ_XMM_MEM64(mem)
+ before
+ bcf85d16674ff416.a405069a616abf08.12402bbe13643e33.e8d7cf68642d64c8
+ 57c0e4cf7764d421.5de6e29091f5eb56.8fe09b582c3f793f.d702dcf3b9d8ba75
+ 5371f57848f48bcb.30ae19ebab2aae68.bfc3182b3950ed94.f12d86eeeba6ca4f
+ 8cd90dfdf70dd43f.79a9a7174c9445e9.7eb61d2556a3565d.94a5c9c49523d004
+ 1bb5a1e153dc073d
+ after
+ bcf85d16674ff416.a405069a616abf08.12402bbe13643e33.d702dcf3b9d8ba75
+ 57c0e4cf7764d421.5de6e29091f5eb56.8fe09b582c3f793f.d702dcf3b9d8ba75
+ 5371f57848f48bcb.30ae19ebab2aae68.bfc3182b3950ed94.f12d86eeeba6ca4f
+ 8cd90dfdf70dd43f.79a9a7174c9445e9.7eb61d2556a3565d.94a5c9c49523d004
+ 1bb5a1e153dc073d
+
+VMOVDQA_GtoE_256(reg)
+ before
+ e1ab0bb1c25daca8.dec2a64b9fba6daa.942388800fbfec86.a88426309e446fc7
+ 43d102a07e30fbf1.24f93e4c5c080f37.dd67b9929137dfea.19fbaf3a2d40f5fd
+ 9e74821a22e330c4.3c4a50ed4c027913.b0c235b96d8959c3.ace6342e20a3a42d
+ 4ce0878c4a0186cc.0181591b88b4656a.6981f8613f4097ba.3f1032f892773780
+ ad462484a0ca6b25
+ after
+ e1ab0bb1c25daca8.dec2a64b9fba6daa.942388800fbfec86.a88426309e446fc7
+ 43d102a07e30fbf1.24f93e4c5c080f37.dd67b9929137dfea.19fbaf3a2d40f5fd
+ 4ce0878c4a0186cc.0181591b88b4656a.6981f8613f4097ba.3f1032f892773780
+ 4ce0878c4a0186cc.0181591b88b4656a.6981f8613f4097ba.3f1032f892773780
+ ad462484a0ca6b25
+VMOVDQA_GtoE_256(mem)
+ before
+ d25486be66a8fc46.ab610d6093173ab6.4f69d3c02e2b9067.64eefef7a5e9d47e
+ 8906d492fe1ca50f.1543110498b0882d.01d03cca5a72b637.fc5544e5380e4eb9
+ b0288bec873224ad.e7d28ee2f658abde.f5800f2427969205.8f04c599963e3f17
+ 228526b91af6334c.7d598068489ce074.0646c8b9b1a1e1fe.78467d7e5b02e445
+ 136668ff22e878ef
+ after
+ b0288bec873224ad.e7d28ee2f658abde.f5800f2427969205.8f04c599963e3f17
+ 8906d492fe1ca50f.1543110498b0882d.01d03cca5a72b637.fc5544e5380e4eb9
+ b0288bec873224ad.e7d28ee2f658abde.f5800f2427969205.8f04c599963e3f17
+ 228526b91af6334c.7d598068489ce074.0646c8b9b1a1e1fe.78467d7e5b02e445
+ 136668ff22e878ef
+
+VMOVDQA_GtoE_256(reg)
+ before
+ bbb1828a877b39c0.baea21e3d5758e17.3425e3012b07639c.0feee47715a15f4d
+ ce73c88a27486165.5624f858d4baf33b.6683b4193a267002.ee44dd496fa2c81f
+ a7f8356b9dda2c8a.d0fd270232d11ce4.70bdee1c11834251.7d13311bdaaed7a0
+ a18cc59986bdd8da.06422bcf0cc7c63d.ae1f8d764eac1636.9a295bda72d449fb
+ 1f50d770541dda5d
+ after
+ bbb1828a877b39c0.baea21e3d5758e17.3425e3012b07639c.0feee47715a15f4d
+ ce73c88a27486165.5624f858d4baf33b.6683b4193a267002.ee44dd496fa2c81f
+ a18cc59986bdd8da.06422bcf0cc7c63d.ae1f8d764eac1636.9a295bda72d449fb
+ a18cc59986bdd8da.06422bcf0cc7c63d.ae1f8d764eac1636.9a295bda72d449fb
+ 1f50d770541dda5d
+VMOVDQA_GtoE_256(mem)
+ before
+ ea5522ca9b9745f2.1a7a74817d7d9f02.d2be7faa7da7ac72.7cf78d938a2d285c
+ d504b7d5644d47e5.6c103f8d1fa7bead.123f9f7fa17e8cb1.3690eadf6390b370
+ be29117bca4b9c62.f598212a07c77088.a08f073a95562024.3835a1c77564f51e
+ 7f90afaaea9e0097.0f5f16c5d267f23e.597c34c7753e24f7.de33adb55b322811
+ 84d60a17b18888f6
+ after
+ be29117bca4b9c62.f598212a07c77088.a08f073a95562024.3835a1c77564f51e
+ d504b7d5644d47e5.6c103f8d1fa7bead.123f9f7fa17e8cb1.3690eadf6390b370
+ be29117bca4b9c62.f598212a07c77088.a08f073a95562024.3835a1c77564f51e
+ 7f90afaaea9e0097.0f5f16c5d267f23e.597c34c7753e24f7.de33adb55b322811
+ 84d60a17b18888f6
+
+VMOVDQA_GtoE_256(reg)
+ before
+ 866ab45814f15378.f5050a4ddf512eae.18b11ac91b15807c.1ad0a1125c3f5657
+ 403ba8e31ff9c344.fc53a050c571e3d3.6ada29a17f5c56ee.bd58ca0766677070
+ 0e94e1266f2d1506.7147eb9fba09db33.632640bb99c9b03f.1fe02b93b0c12f6d
+ 4cc35b8c9f188469.2ead6926d725d1fa.5de05a8206e7c91c.1c3340a0555a4f7b
+ 911f861c723c8bc5
+ after
+ 866ab45814f15378.f5050a4ddf512eae.18b11ac91b15807c.1ad0a1125c3f5657
+ 403ba8e31ff9c344.fc53a050c571e3d3.6ada29a17f5c56ee.bd58ca0766677070
+ 4cc35b8c9f188469.2ead6926d725d1fa.5de05a8206e7c91c.1c3340a0555a4f7b
+ 4cc35b8c9f188469.2ead6926d725d1fa.5de05a8206e7c91c.1c3340a0555a4f7b
+ 911f861c723c8bc5
+VMOVDQA_GtoE_256(mem)
+ before
+ 586e78f22276a078.551212814c474d1a.105196d13ad18353.b55673626142de31
+ 4eed920d82114ac0.87ce02711245acc4.f3ffec8cff1aaa6b.c8d287c746672a29
+ 4f68505bad1b44c8.3d4328c98b9edd14.b383e943410c056d.f0a1931d52e1ebb0
+ 37ab2fc7c09f4bbd.d3bd7ff355de1bb5.2ca808e31cb14e86.8a0f91d1213c5b74
+ f2677f4d4d05b61e
+ after
+ 4f68505bad1b44c8.3d4328c98b9edd14.b383e943410c056d.f0a1931d52e1ebb0
+ 4eed920d82114ac0.87ce02711245acc4.f3ffec8cff1aaa6b.c8d287c746672a29
+ 4f68505bad1b44c8.3d4328c98b9edd14.b383e943410c056d.f0a1931d52e1ebb0
+ 37ab2fc7c09f4bbd.d3bd7ff355de1bb5.2ca808e31cb14e86.8a0f91d1213c5b74
+ f2677f4d4d05b61e
+
+VMOVDQA_GtoE_128(reg)
+ before
+ 84f758fe75c73a5d.e282a93dd6aa1bca.a487035c0c92a354.3b3bc556ad1742e2
+ 9d091951330f21db.2cb83caa0c47701c.0eefb0714b45b19d.ba089c8a0f499dac
+ 97eabcb12367a844.f11b64f87d8205df.6c3f829caf84813b.86db0a6a5f541b11
+ cfe73f89e25d0b46.0d759b144568973e.19c4764bd3da4edb.7b8089e1b943773c
+ 75c397dd37226e5a
+ after
+ 84f758fe75c73a5d.e282a93dd6aa1bca.a487035c0c92a354.3b3bc556ad1742e2
+ 9d091951330f21db.2cb83caa0c47701c.0eefb0714b45b19d.ba089c8a0f499dac
+ 0000000000000000.0000000000000000.19c4764bd3da4edb.7b8089e1b943773c
+ cfe73f89e25d0b46.0d759b144568973e.19c4764bd3da4edb.7b8089e1b943773c
+ 75c397dd37226e5a
+VMOVDQA_GtoE_128(mem)
+ before
+ 4f6fb049f8febc97.a14a9d470b7d858a.5c935feb8104e266.73ca87e953d35529
+ e7524e1115e21c1e.695fd2563b5253bf.ba412a674d62a282.d49db1e2ccfcd2d0
+ 1836ef22acda4b1c.8374db220d68b18f.034b7a76c48f92bf.9a89f0a2dae0007d
+ bee80e66d9f305bc.4bd3b3171e4bdaa6.137dcb0202966f49.1fda4195180b1cdb
+ c1db9f27220a6297
+ after
+ 4f6fb049f8febc97.a14a9d470b7d858a.034b7a76c48f92bf.9a89f0a2dae0007d
+ e7524e1115e21c1e.695fd2563b5253bf.ba412a674d62a282.d49db1e2ccfcd2d0
+ 1836ef22acda4b1c.8374db220d68b18f.034b7a76c48f92bf.9a89f0a2dae0007d
+ bee80e66d9f305bc.4bd3b3171e4bdaa6.137dcb0202966f49.1fda4195180b1cdb
+ c1db9f27220a6297
+
+VMOVDQA_GtoE_128(reg)
+ before
+ dad906c495680e5c.b53427cab738052b.1dca55a109880cb2.c5a297f92483f54b
+ c72072d90cb15bd7.d8e6b63b63b50994.55a3c02d6aaa815c.f7875c464663dff2
+ e5fce0d0247286b4.05c938a3f877cb25.4eabed25de3e7553.84f995d58241ea69
+ 8eb94a177836cb9e.17ab27f092890707.662edaf701ce2641.48c2be92f729d2dd
+ 1eae5369bf285279
+ after
+ dad906c495680e5c.b53427cab738052b.1dca55a109880cb2.c5a297f92483f54b
+ c72072d90cb15bd7.d8e6b63b63b50994.55a3c02d6aaa815c.f7875c464663dff2
+ 0000000000000000.0000000000000000.662edaf701ce2641.48c2be92f729d2dd
+ 8eb94a177836cb9e.17ab27f092890707.662edaf701ce2641.48c2be92f729d2dd
+ 1eae5369bf285279
+VMOVDQA_GtoE_128(mem)
+ before
+ e48bd147f649286a.1fa2ae18a5896542.ea56010d4ef77b69.f877810d6ee9ced2
+ 7524b316b8980edc.f505074146f8924c.599741e548cee174.60d4e0d5c218aab3
+ ac4475c42322c0fa.6a2c52fdf80e8b67.423a64669b19f657.fa8ff3ba97e9f590
+ 67b8933b50f2fcf1.db6489b856578f3f.7f0be47b63e4753c.21f5b4288ce7ec14
+ 3352218b3b9fcbec
+ after
+ e48bd147f649286a.1fa2ae18a5896542.423a64669b19f657.fa8ff3ba97e9f590
+ 7524b316b8980edc.f505074146f8924c.599741e548cee174.60d4e0d5c218aab3
+ ac4475c42322c0fa.6a2c52fdf80e8b67.423a64669b19f657.fa8ff3ba97e9f590
+ 67b8933b50f2fcf1.db6489b856578f3f.7f0be47b63e4753c.21f5b4288ce7ec14
+ 3352218b3b9fcbec
+
+VMOVDQA_GtoE_128(reg)
+ before
+ 8bf2354f409ccec4.804c89695d147ced.a4f9aadefd60d881.eed53f10bd3c1c50
+ 8421ece0386a3047.d5ccd4396695fd19.2137b0db88b4a3d9.6966f012c52ca5be
+ 7c2b42aabe952f22.4004ef9686803aa2.ae6a971b94df2cf3.ce88746b95c1ccb3
+ cd5b33196faa0400.9fbf566edae2f1b3.a7dd5c0abc6eaf7a.f70845084c054f5a
+ c2b2e1d60307e8e1
+ after
+ 8bf2354f409ccec4.804c89695d147ced.a4f9aadefd60d881.eed53f10bd3c1c50
+ 8421ece0386a3047.d5ccd4396695fd19.2137b0db88b4a3d9.6966f012c52ca5be
+ 0000000000000000.0000000000000000.a7dd5c0abc6eaf7a.f70845084c054f5a
+ cd5b33196faa0400.9fbf566edae2f1b3.a7dd5c0abc6eaf7a.f70845084c054f5a
+ c2b2e1d60307e8e1
+VMOVDQA_GtoE_128(mem)
+ before
+ 0952c3bfd9d05471.d5febc9ae635ee8e.cccb85ac7dc6dc79.68def9159cec671a
+ a9b467b1e76e4e38.ee61d897c0c02777.a4f2f93d8b38b71f.4db76ca6d1e59180
+ 7fa449974bec9462.76cd837e98d9ec68.04012d0b214440d2.b2b5b02bf6e66958
+ 65ede65d2157e01b.c791baba0b0b790d.c6c49d035af731be.f324c10ea87a2a4e
+ 6c509cbd832e110d
+ after
+ 0952c3bfd9d05471.d5febc9ae635ee8e.04012d0b214440d2.b2b5b02bf6e66958
+ a9b467b1e76e4e38.ee61d897c0c02777.a4f2f93d8b38b71f.4db76ca6d1e59180
+ 7fa449974bec9462.76cd837e98d9ec68.04012d0b214440d2.b2b5b02bf6e66958
+ 65ede65d2157e01b.c791baba0b0b790d.c6c49d035af731be.f324c10ea87a2a4e
+ 6c509cbd832e110d
+
+VMOVDQU_GtoE_128(reg)
+ before
+ 79843ca3228d5a41.385cb9ef84b9ee8e.3ef877b6b4e30911.c707c511535c470e
+ 760e9d2c21234097.d4bd3e3991217ce7.384db8e02fecda21.e496212228803eef
+ bf38bbc41d7c01bb.16dcf12763984454.0fde78a31ab225e9.f73c2e21f36ed18c
+ b04f92d7b125d758.d8854ea5162c03fe.20f5b46b0ec22914.ddc767f9d332bd12
+ 72014898e1d8bead
+ after
+ 79843ca3228d5a41.385cb9ef84b9ee8e.3ef877b6b4e30911.c707c511535c470e
+ 760e9d2c21234097.d4bd3e3991217ce7.384db8e02fecda21.e496212228803eef
+ 0000000000000000.0000000000000000.20f5b46b0ec22914.ddc767f9d332bd12
+ b04f92d7b125d758.d8854ea5162c03fe.20f5b46b0ec22914.ddc767f9d332bd12
+ 72014898e1d8bead
+VMOVDQU_GtoE_128(mem)
+ before
+ 92b74de93c6d8f88.a49f1fd17aa9fe1b.f784d29fc7e87514.c8df66a5a9a7204e
+ 19b5f3d8fdfcedd0.f9745d1f1395b4b0.4fa4f80292d955c0.61e88cbb86ed4745
+ e3c6b451429294b0.0a19482b197433c2.bcb23cb8920a602e.485c211a4221daa2
+ ccb80e40273a4055.32dcdc6327d2b8fe.1a7a1bafe387528c.d986212f79ce1514
+ 70b48864c6803345
+ after
+ 92b74de93c6d8f88.a49f1fd17aa9fe1b.bcb23cb8920a602e.485c211a4221daa2
+ 19b5f3d8fdfcedd0.f9745d1f1395b4b0.4fa4f80292d955c0.61e88cbb86ed4745
+ e3c6b451429294b0.0a19482b197433c2.bcb23cb8920a602e.485c211a4221daa2
+ ccb80e40273a4055.32dcdc6327d2b8fe.1a7a1bafe387528c.d986212f79ce1514
+ 70b48864c6803345
+
+VMOVDQU_GtoE_128(reg)
+ before
+ 6a305327c5c471e1.b0557c91c700aceb.cf071531d93b7e0f.45c80fd2a25de603
+ 21477de313250a96.6b6b7b313ff1959d.3ce7f003cc3cc2a2.1968960dea97d9c2
+ f24502044b303c0d.d9c4850aaa18b798.d4c868449c61c062.72262b4bd841e7f3
+ 3976def50a6f41f5.d62d180a2481ce07.f5f67960e434b4fc.2ccd4a7a8767ccc2
+ 232b6f851416435d
+ after
+ 6a305327c5c471e1.b0557c91c700aceb.cf071531d93b7e0f.45c80fd2a25de603
+ 21477de313250a96.6b6b7b313ff1959d.3ce7f003cc3cc2a2.1968960dea97d9c2
+ 0000000000000000.0000000000000000.f5f67960e434b4fc.2ccd4a7a8767ccc2
+ 3976def50a6f41f5.d62d180a2481ce07.f5f67960e434b4fc.2ccd4a7a8767ccc2
+ 232b6f851416435d
+VMOVDQU_GtoE_128(mem)
+ before
+ 330a17599a5a0aed.52250d24eb7156f8.3e71af1bca399517.f9bd20c34043d91c
+ 3837bde0363ddaa1.99a08cfd8bbfb6c2.ed5ec72bb84bc9f4.3e6857d94d196d6d
+ 0d7edd0703cd72a3.693156ea85e79e01.bfbfda2508c326c9.1e451c0ea743aa9c
+ 90abf3bb1e168c1f.2025675875744a5e.8f5f66f5d9ae67c3.f69e6acee84ccc55
+ 23c03d85afc01043
+ after
+ 330a17599a5a0aed.52250d24eb7156f8.bfbfda2508c326c9.1e451c0ea743aa9c
+ 3837bde0363ddaa1.99a08cfd8bbfb6c2.ed5ec72bb84bc9f4.3e6857d94d196d6d
+ 0d7edd0703cd72a3.693156ea85e79e01.bfbfda2508c326c9.1e451c0ea743aa9c
+ 90abf3bb1e168c1f.2025675875744a5e.8f5f66f5d9ae67c3.f69e6acee84ccc55
+ 23c03d85afc01043
+
+VMOVDQU_GtoE_128(reg)
+ before
+ fff792a0962cb212.9c897ce6a222e542.19c8bcb4f8f2f688.3b0be6874517490d
+ e78f6389391bee70.0ce6f376abff3938.b0664f68aaeedd29.9e8fd6c7680a88d4
+ 38d3aeae35190007.be8cd45656b9432c.414b1ee226f33ced.93b7b2a15f94df44
+ 4c116e7a25b32383.8d489b72bf5bc04b.28c2248c088e4f81.f84ff70145c00c88
+ a82220d4379ac9cc
+ after
+ fff792a0962cb212.9c897ce6a222e542.19c8bcb4f8f2f688.3b0be6874517490d
+ e78f6389391bee70.0ce6f376abff3938.b0664f68aaeedd29.9e8fd6c7680a88d4
+ 0000000000000000.0000000000000000.28c2248c088e4f81.f84ff70145c00c88
+ 4c116e7a25b32383.8d489b72bf5bc04b.28c2248c088e4f81.f84ff70145c00c88
+ a82220d4379ac9cc
+VMOVDQU_GtoE_128(mem)
+ before
+ 7efda904502fd23e.8093a059a6749491.54e6c4b501f16cc1.c0185dd4ed4a5291
+ 58ad0e7fac8ae508.30a63eb753e88edd.f132cc0d388703b9.679ac62571b380c8
+ 10fccb2f69b8bc56.b8964600c89c4f12.3ef72e66812a4060.789259eb2f5616d3
+ 84b75d02a0c31455.75afb3a0a21b11dd.190366aaf7e5e0e1.4e4d1492c3bd505e
+ 4716f286ca776914
+ after
+ 7efda904502fd23e.8093a059a6749491.3ef72e66812a4060.789259eb2f5616d3
+ 58ad0e7fac8ae508.30a63eb753e88edd.f132cc0d388703b9.679ac62571b380c8
+ 10fccb2f69b8bc56.b8964600c89c4f12.3ef72e66812a4060.789259eb2f5616d3
+ 84b75d02a0c31455.75afb3a0a21b11dd.190366aaf7e5e0e1.4e4d1492c3bd505e
+ 4716f286ca776914
+
+VMOVDQA_EtoG_256(reg)
+ before
+ bd3bf033df0d9ea2.8ea93fe36fb9a831.c13d81037df210e9.5c20f0c6b7c49f69
+ 0e0608069f0d2bb3.0ca0edbef2a63615.f98bad95f4ab8ae3.e51b49a6dcd43823
+ 95c53869a5024cf4.d866e37f4495782e.79e631c3a4d4b977.8ec0eb378320683c
+ adc27bca8e793c10.cfc99e1281922aa7.9d9b0bf727f9da50.35db5464c7b5ebe0
+ b438ff18c59e7d3a
+ after
+ bd3bf033df0d9ea2.8ea93fe36fb9a831.c13d81037df210e9.5c20f0c6b7c49f69
+ 95c53869a5024cf4.d866e37f4495782e.79e631c3a4d4b977.8ec0eb378320683c
+ 95c53869a5024cf4.d866e37f4495782e.79e631c3a4d4b977.8ec0eb378320683c
+ adc27bca8e793c10.cfc99e1281922aa7.9d9b0bf727f9da50.35db5464c7b5ebe0
+ b438ff18c59e7d3a
+VMOVDQA_EtoG_256(mem)
+ before
+ e8a3694198e7d977.b34acd93f5fd38b4.ce939863c6a90aad.c1f4369f1ca5291b
+ aee70cca5d9cbcc2.04a92a32771a7c8c.af914f5f2fe7d26c.413eaf251d64e183
+ e0d1669f2fcae248.fa2a8f12af5d4343.4f8f3ff0d6573f0f.79c470f7c6c23f35
+ 5b2df2ac2a7c0635.f31bf79f3951ca86.8b58e204da060dc3.c4d47780b44c7fdd
+ 80b8bf2c828ddd26
+ after
+ e8a3694198e7d977.b34acd93f5fd38b4.ce939863c6a90aad.c1f4369f1ca5291b
+ aee70cca5d9cbcc2.04a92a32771a7c8c.af914f5f2fe7d26c.413eaf251d64e183
+ e0d1669f2fcae248.fa2a8f12af5d4343.4f8f3ff0d6573f0f.79c470f7c6c23f35
+ e8a3694198e7d977.b34acd93f5fd38b4.ce939863c6a90aad.c1f4369f1ca5291b
+ 80b8bf2c828ddd26
+
+VMOVDQA_EtoG_256(reg)
+ before
+ 08be4467cd1294bc.fbc72cdd6bbfe6b4.49c65e45b2824d01.3dbab68555fff7b4
+ b830029d3065e14d.9c6b911e0e9e3bf2.5978c070b67d085f.427f3661634eba0d
+ ec5bf63a4815ff83.1be59c5c2e25c41b.7f7d1a8ce0cd364c.7674de8321ff12fa
+ ff8a1babb0ab2c0a.5200c881e7603b5a.18216605ccfe1476.b5652ad7aa1fbaa8
+ db1e96481aba6f43
+ after
+ 08be4467cd1294bc.fbc72cdd6bbfe6b4.49c65e45b2824d01.3dbab68555fff7b4
+ ec5bf63a4815ff83.1be59c5c2e25c41b.7f7d1a8ce0cd364c.7674de8321ff12fa
+ ec5bf63a4815ff83.1be59c5c2e25c41b.7f7d1a8ce0cd364c.7674de8321ff12fa
+ ff8a1babb0ab2c0a.5200c881e7603b5a.18216605ccfe1476.b5652ad7aa1fbaa8
+ db1e96481aba6f43
+VMOVDQA_EtoG_256(mem)
+ before
+ c46b9fc58fdaedf7.4f0b6d5a05b5a28f.1e89947b565c5ddb.7eb0a248179dde86
+ 4c18c037228df0ef.3728e8b4e2be9ebe.5b4d79349725e6cb.0e75cabf5d35cf2b
+ 4ff0758bf1de3357.122f8926e4535b42.e515f49ac5c59256.24bed8d83952250f
+ a9c03bad18da735c.3e6a4a1ba6ff17c8.98b08298fc4a1ca8.1cd5cafd47811ade
+ 52079a9c244dea46
+ after
+ c46b9fc58fdaedf7.4f0b6d5a05b5a28f.1e89947b565c5ddb.7eb0a248179dde86
+ 4c18c037228df0ef.3728e8b4e2be9ebe.5b4d79349725e6cb.0e75cabf5d35cf2b
+ 4ff0758bf1de3357.122f8926e4535b42.e515f49ac5c59256.24bed8d83952250f
+ c46b9fc58fdaedf7.4f0b6d5a05b5a28f.1e89947b565c5ddb.7eb0a248179dde86
+ 52079a9c244dea46
+
+VMOVDQA_EtoG_256(reg)
+ before
+ 22a046206b43d2f0.36548c8ab28c6c2a.152629ffc44e0cfc.50e99e1a59bf41ec
+ e8eccaf5b9ed0f8b.d278e60cdb00daed.f5af213ddbcd7689.e98cc40cf731bd4e
+ 00362087a9d9dac1.59f8c421b04378d0.38512f438707931c.3e64715af3ab4bfb
+ c6cc4642d893723e.a7a0a2b44d6003ff.3c574d7c63889d60.2d3e20f06839a81f
+ 91e64cba72e890e5
+ after
+ 22a046206b43d2f0.36548c8ab28c6c2a.152629ffc44e0cfc.50e99e1a59bf41ec
+ 00362087a9d9dac1.59f8c421b04378d0.38512f438707931c.3e64715af3ab4bfb
+ 00362087a9d9dac1.59f8c421b04378d0.38512f438707931c.3e64715af3ab4bfb
+ c6cc4642d893723e.a7a0a2b44d6003ff.3c574d7c63889d60.2d3e20f06839a81f
+ 91e64cba72e890e5
+VMOVDQA_EtoG_256(mem)
+ before
+ 462873a42fc3be7a.96f83792e1a611b0.983bfdb0cd6337a7.5b0e79550bdcd102
+ 28d0119bb8d6f00a.cc07efe3609ef4c0.079650034c59cff4.f3c3ae381c906aad
+ 12a9a0892b2ee0c0.c4456aa2f207571d.d27e1798e74d8811.5ec0e8923130a60e
+ e2819e5ca4d64ac9.dafea539336e7571.d4bdce5bb94b1e2b.f95224d0e746bfd1
+ 21c45c5cd960f1a1
+ after
+ 462873a42fc3be7a.96f83792e1a611b0.983bfdb0cd6337a7.5b0e79550bdcd102
+ 28d0119bb8d6f00a.cc07efe3609ef4c0.079650034c59cff4.f3c3ae381c906aad
+ 12a9a0892b2ee0c0.c4456aa2f207571d.d27e1798e74d8811.5ec0e8923130a60e
+ 462873a42fc3be7a.96f83792e1a611b0.983bfdb0cd6337a7.5b0e79550bdcd102
+ 21c45c5cd960f1a1
+
+VMOVDQA_EtoG_128(reg)
+ before
+ 30648ea4a40a7a2b.732286ff3edaec50.6a7e9b16be5e8b68.e81ff139df604c6e
+ 837cb613e3ce941a.a059d45e15478082.cf1048a42f64d5af.ec72fd1c7497d005
+ 765ace14333a7c1b.47f205654628c38a.6702a84e230b8ff2.bb816cf195fc641d
+ 6648d3152fda6eda.42b99300ed8a7096.8d9eb78236dff4dc.3017bca55d9cc4e1
+ 29016922e982ae7e
+ after
+ 30648ea4a40a7a2b.732286ff3edaec50.6a7e9b16be5e8b68.e81ff139df604c6e
+ 0000000000000000.0000000000000000.6702a84e230b8ff2.bb816cf195fc641d
+ 765ace14333a7c1b.47f205654628c38a.6702a84e230b8ff2.bb816cf195fc641d
+ 6648d3152fda6eda.42b99300ed8a7096.8d9eb78236dff4dc.3017bca55d9cc4e1
+ 29016922e982ae7e
+VMOVDQA_EtoG_128(mem)
+ before
+ 800bed5654bbdc1f.ad93c2817438a502.6f7afc1b257744cf.9c3172ab036c411a
+ 1301c62cba510bf1.a88796c49de35e40.a800bba20afefb64.f207d435263fb158
+ bcaf6f903853f620.b36f4b4b4664d540.cb184c81b928517e.ea6cd98c3ce48241
+ 59e1646eeaca5bd7.2a99de800c4945ad.b28f2ca54d03024c.dfab7d1de0e5ee82
+ 2f12bd52afd032c6
+ after
+ 800bed5654bbdc1f.ad93c2817438a502.6f7afc1b257744cf.9c3172ab036c411a
+ 1301c62cba510bf1.a88796c49de35e40.a800bba20afefb64.f207d435263fb158
+ bcaf6f903853f620.b36f4b4b4664d540.cb184c81b928517e.ea6cd98c3ce48241
+ 0000000000000000.0000000000000000.6f7afc1b257744cf.9c3172ab036c411a
+ 2f12bd52afd032c6
+
+VMOVDQA_EtoG_128(reg)
+ before
+ 34eb9398443089ba.c46221b2ebc4f443.694f49d08b1deb33.3b2fd6f8e39ac9f8
+ 4c83fd5c3c923109.daff2348574c7d90.ccde8aa85e6c037f.40c4c66896f963af
+ d126f70932816460.7884e41c4b6eb4e9.af929c7221c3c93d.9f1c78df832d8b9c
+ 21207b0ac3895e6b.78bde21ae337537a.6eb77c9c71ad7818.3202684bc541ffec
+ d6411397784279ca
+ after
+ 34eb9398443089ba.c46221b2ebc4f443.694f49d08b1deb33.3b2fd6f8e39ac9f8
+ 0000000000000000.0000000000000000.af929c7221c3c93d.9f1c78df832d8b9c
+ d126f70932816460.7884e41c4b6eb4e9.af929c7221c3c93d.9f1c78df832d8b9c
+ 21207b0ac3895e6b.78bde21ae337537a.6eb77c9c71ad7818.3202684bc541ffec
+ d6411397784279ca
+VMOVDQA_EtoG_128(mem)
+ before
+ 67a6f3afba3bb563.96bc87cd8a375dd5.b776992f3ab21771.65992491eab74dbd
+ c2fd867fa43871e3.8d4815bd23169b4b.127b83456cecbcf7.f08492bd266b84d8
+ c11248f354456775.630e24462bb25579.63971e4a96f0fd3b.6bc3c18cc4585914
+ 41b1b3f7e66f5446.725cadd43e98c70a.8798e428d3ca9767.31a3ad6a5e07071e
+ a07052c39006cba1
+ after
+ 67a6f3afba3bb563.96bc87cd8a375dd5.b776992f3ab21771.65992491eab74dbd
+ c2fd867fa43871e3.8d4815bd23169b4b.127b83456cecbcf7.f08492bd266b84d8
+ c11248f354456775.630e24462bb25579.63971e4a96f0fd3b.6bc3c18cc4585914
+ 0000000000000000.0000000000000000.b776992f3ab21771.65992491eab74dbd
+ a07052c39006cba1
+
+VMOVDQA_EtoG_128(reg)
+ before
+ 1376ad03f7e0e14a.1ea6457875c2f481.177cadd3f7532caa.5a4854cd408746a7
+ e601b9962e2284c5.34bc79601d480253.afba21b0f26fc107.b874e724f832c529
+ 745d72e9d156f1bd.5fc0cb9dfb0f3be8.946404d5cc79c2ca.7de81a1918d7d117
+ 1bd5d4667d0b64df.7b7fb7192a225b6b.23c552af21fc6aa2.856f6a98bb82269d
+ acd7528dfd4080e8
+ after
+ 1376ad03f7e0e14a.1ea6457875c2f481.177cadd3f7532caa.5a4854cd408746a7
+ 0000000000000000.0000000000000000.946404d5cc79c2ca.7de81a1918d7d117
+ 745d72e9d156f1bd.5fc0cb9dfb0f3be8.946404d5cc79c2ca.7de81a1918d7d117
+ 1bd5d4667d0b64df.7b7fb7192a225b6b.23c552af21fc6aa2.856f6a98bb82269d
+ acd7528dfd4080e8
+VMOVDQA_EtoG_128(mem)
+ before
+ ceea4ee5fb1d9a23.36b7dc7bceca19d6.64c3bac2c78e1d09.b82808ab8b84f639
+ c776db8ad123317c.204d84935f214b4f.f6584f83ee5e3eed.afda2034a99ea23b
+ 734573699a60011c.37e4ca19cd9b37f5.0d0cf248b99e7a44.642798b515d5aa56
+ ae24946f73dfc632.d5c8a97bb3c51975.85aa1ffd475b8d3a.335b6b9c6bb64933
+ 78c2955448cbbc81
+ after
+ ceea4ee5fb1d9a23.36b7dc7bceca19d6.64c3bac2c78e1d09.b82808ab8b84f639
+ c776db8ad123317c.204d84935f214b4f.f6584f83ee5e3eed.afda2034a99ea23b
+ 734573699a60011c.37e4ca19cd9b37f5.0d0cf248b99e7a44.642798b515d5aa56
+ 0000000000000000.0000000000000000.64c3bac2c78e1d09.b82808ab8b84f639
+ 78c2955448cbbc81
+
+VMOVDQU_EtoG_128(reg)
+ before
+ 8fa8134947a23fea.54dfb98676ad3be8.58441e24ad2a2c7b.3afd528eb1a032fa
+ d458dfe704c70e1a.41415e9cc2d51d6a.1aa623805856adb2.08d208e7167927b1
+ a31ff79a1dc564be.5118009c716328e5.7938b6fb4fd6d8c7.cbf5bcf48ff3258a
+ 584a56cf2b287e82.5f2e19729f641785.cf47d2022f35e966.5e32eaa13a19ebb2
+ 9f550edb33f73355
+ after
+ 8fa8134947a23fea.54dfb98676ad3be8.58441e24ad2a2c7b.3afd528eb1a032fa
+ 0000000000000000.0000000000000000.7938b6fb4fd6d8c7.cbf5bcf48ff3258a
+ a31ff79a1dc564be.5118009c716328e5.7938b6fb4fd6d8c7.cbf5bcf48ff3258a
+ 584a56cf2b287e82.5f2e19729f641785.cf47d2022f35e966.5e32eaa13a19ebb2
+ 9f550edb33f73355
+VMOVDQU_EtoG_128(mem)
+ before
+ 6929a58c959aba9e.4f23f9f0cc7c9712.4950270a69e3a776.792073ff94ff1b3a
+ 987c29a27d0d3cb9.e4f6da6b9c4eed19.ea4aa650eaec94e2.d40c966019c1abef
+ 07181808065c74d4.7211f7aa3629ba43.1ee810303f8c99f8.3a5a368f5a06d533
+ 94caeeaa4c941f19.57bf4b1b369a3b3d.c0f6e29783ce74e2.08554ffaf45ad4af
+ 9b48dd0b824ae512
+ after
+ 6929a58c959aba9e.4f23f9f0cc7c9712.4950270a69e3a776.792073ff94ff1b3a
+ 987c29a27d0d3cb9.e4f6da6b9c4eed19.ea4aa650eaec94e2.d40c966019c1abef
+ 07181808065c74d4.7211f7aa3629ba43.1ee810303f8c99f8.3a5a368f5a06d533
+ 0000000000000000.0000000000000000.4950270a69e3a776.792073ff94ff1b3a
+ 9b48dd0b824ae512
+
+VMOVDQU_EtoG_128(reg)
+ before
+ 4d81dc30a0614406.195e25746cc0f9b4.ee4bd229392cabb3.ae3f996fd3bfdfcd
+ 7b4a49d4ec2b2d38.74a03b5281ecbed2.93028940db6b4850.c291b0a54a6996e4
+ 81f01e63ff35db53.805caa30a825299f.a1306accb7e34cc1.dab6a32605da5754
+ bbbe5949770a8b04.185df0fafd76f746.762173396921f3b2.d07befdd1f1edc48
+ 82ac0fb5b540e2ee
+ after
+ 4d81dc30a0614406.195e25746cc0f9b4.ee4bd229392cabb3.ae3f996fd3bfdfcd
+ 0000000000000000.0000000000000000.a1306accb7e34cc1.dab6a32605da5754
+ 81f01e63ff35db53.805caa30a825299f.a1306accb7e34cc1.dab6a32605da5754
+ bbbe5949770a8b04.185df0fafd76f746.762173396921f3b2.d07befdd1f1edc48
+ 82ac0fb5b540e2ee
+VMOVDQU_EtoG_128(mem)
+ before
+ ca147e9ce24c246f.8502f5f2f03679f6.1a70899c9aece4f4.6d219ff38eb07bce
+ 8681bb7dc24e60fa.3b07efcb0546e0d6.6062ef039e91abd5.e17ceb66c11d1ec2
+ 90bd3f44725350b8.3918423e52c5fe50.c7fda01922740914.307d51fe9ff31939
+ c69687dd0e66b0d8.db82e9b974400d0f.2c0d17cc459ebadd.b471cf28c3bea7e0
+ cba4604eca0b0562
+ after
+ ca147e9ce24c246f.8502f5f2f03679f6.1a70899c9aece4f4.6d219ff38eb07bce
+ 8681bb7dc24e60fa.3b07efcb0546e0d6.6062ef039e91abd5.e17ceb66c11d1ec2
+ 90bd3f44725350b8.3918423e52c5fe50.c7fda01922740914.307d51fe9ff31939
+ 0000000000000000.0000000000000000.1a70899c9aece4f4.6d219ff38eb07bce
+ cba4604eca0b0562
+
+VMOVDQU_EtoG_128(reg)
+ before
+ cf6200de4f656f6c.02d61035b1943e84.7d91e2a6074149c0.6960d006201d7a5e
+ 1df7ac43ef5821aa.214a553677e7b4e9.7b912973a656f00e.5bc147b5d2fc04c0
+ 12af5ee8457157c7.ffbed2cd7d6ecf32.31ceb88bed0b3ca6.dffbf9c474481532
+ 08d5143bed3b4c70.79fd04e7de324b8c.fb938d5a79eb6a33.cfdb611f240b69de
+ 082dfbb2fe54bbf1
+ after
+ cf6200de4f656f6c.02d61035b1943e84.7d91e2a6074149c0.6960d006201d7a5e
+ 0000000000000000.0000000000000000.31ceb88bed0b3ca6.dffbf9c474481532
+ 12af5ee8457157c7.ffbed2cd7d6ecf32.31ceb88bed0b3ca6.dffbf9c474481532
+ 08d5143bed3b4c70.79fd04e7de324b8c.fb938d5a79eb6a33.cfdb611f240b69de
+ 082dfbb2fe54bbf1
+VMOVDQU_EtoG_128(mem)
+ before
+ 66bd43691d2cc996.5db7c9a784423d51.69d5656eb741e322.352ea34be582b563
+ c557b6309da14cfa.6b9f7998a6136515.ac10735023a65421.3be9f6ccce5c5adf
+ 02c7cef49bbe0348.8fda217bee390268.1e7ba9783f6e5ab5.68118349cf069556
+ f7d8099f3390a8ad.25b4bcbaf8404ef7.9be284d226a4b009.1af2442c850ba272
+ acd837e28bf8bcdf
+ after
+ 66bd43691d2cc996.5db7c9a784423d51.69d5656eb741e322.352ea34be582b563
+ c557b6309da14cfa.6b9f7998a6136515.ac10735023a65421.3be9f6ccce5c5adf
+ 02c7cef49bbe0348.8fda217bee390268.1e7ba9783f6e5ab5.68118349cf069556
+ 0000000000000000.0000000000000000.69d5656eb741e322.352ea34be582b563
+ acd837e28bf8bcdf
+
+VMOVAPD_GtoE_128(reg)
+ before
+ 7a0f57d87e58204a.8157e21f8022f855.8a7846c261b5856e.ff117e4af554134a
+ dfe2a078f9b70a5f.7c11d65e9e80af6b.1874bb00c523e579.26d415ccc78a3fa3
+ 399e0f3099a2b6c9.c4d05f4aaab7891c.2cf217debe16a8c3.ecf7c444b953f041
+ e2909f6af9a45f35.3560fbcebfd14193.224057caeb1b0bf8.2d45079ee6bbe150
+ c58b5ac66acccffb
+ after
+ 7a0f57d87e58204a.8157e21f8022f855.8a7846c261b5856e.ff117e4af554134a
+ dfe2a078f9b70a5f.7c11d65e9e80af6b.1874bb00c523e579.26d415ccc78a3fa3
+ 0000000000000000.0000000000000000.224057caeb1b0bf8.2d45079ee6bbe150
+ e2909f6af9a45f35.3560fbcebfd14193.224057caeb1b0bf8.2d45079ee6bbe150
+ c58b5ac66acccffb
+VMOVAPD_GtoE_128(mem)
+ before
+ 90953aa96294766f.38024b94b549424f.ab8f25d6fadd94fd.56a8762fe6bd4ac6
+ 6a2f2231ea1f92d7.964012196a1d9bc2.0228594e76e43e85.247770794b88a0d6
+ 2f258e4c1d77de60.5798ed65b4ada53b.16f6142250f4fa59.e8f84113b7094ad7
+ bb43fae517aa1736.d955dae42e859d65.c2c6d03ea31985a2.fe79e56bc5cb8473
+ c24459ed115b8956
+ after
+ 90953aa96294766f.38024b94b549424f.16f6142250f4fa59.e8f84113b7094ad7
+ 6a2f2231ea1f92d7.964012196a1d9bc2.0228594e76e43e85.247770794b88a0d6
+ 2f258e4c1d77de60.5798ed65b4ada53b.16f6142250f4fa59.e8f84113b7094ad7
+ bb43fae517aa1736.d955dae42e859d65.c2c6d03ea31985a2.fe79e56bc5cb8473
+ c24459ed115b8956
+
+VMOVAPD_GtoE_128(reg)
+ before
+ 90a798033944972d.ea54e3e8f5c4f984.76c2d302742fbfed.e4640b8e8c5d9b8f
+ c4ec9e1ad612e8a4.9725c341d2cf3f76.8b2cd62c2339477e.579c40ff26cef74a
+ ba60679f8651b867.a08318dccbd9a63a.75dfdfccd62e70c5.f73aec7b8e7857ff
+ cd4ff0fce58e4521.e0385da5fbeeeafa.8e27e84f2a9b776e.9f0989f0df6575db
+ 2dd7954835a30d0a
+ after
+ 90a798033944972d.ea54e3e8f5c4f984.76c2d302742fbfed.e4640b8e8c5d9b8f
+ c4ec9e1ad612e8a4.9725c341d2cf3f76.8b2cd62c2339477e.579c40ff26cef74a
+ 0000000000000000.0000000000000000.8e27e84f2a9b776e.9f0989f0df6575db
+ cd4ff0fce58e4521.e0385da5fbeeeafa.8e27e84f2a9b776e.9f0989f0df6575db
+ 2dd7954835a30d0a
+VMOVAPD_GtoE_128(mem)
+ before
+ 7c6e8b71ad3eddb7.5b04349f8e54c97e.33100f887f18c6e2.3350ef22ba0b9824
+ 679be75663419f0f.bfcd2ff21d30802b.74d9a8717365f81f.c1a6efb0230a0e94
+ cc2a25e372b8103e.55f4dd632faca8d4.815ea64cf1e13add.9274e46400251769
+ 86e7c204f6afeb6f.78c73a5d60577b24.346a840617964847.0307caaceee7ec50
+ 70ab9ef388ddccf5
+ after
+ 7c6e8b71ad3eddb7.5b04349f8e54c97e.815ea64cf1e13add.9274e46400251769
+ 679be75663419f0f.bfcd2ff21d30802b.74d9a8717365f81f.c1a6efb0230a0e94
+ cc2a25e372b8103e.55f4dd632faca8d4.815ea64cf1e13add.9274e46400251769
+ 86e7c204f6afeb6f.78c73a5d60577b24.346a840617964847.0307caaceee7ec50
+ 70ab9ef388ddccf5
+
+VMOVAPD_GtoE_128(reg)
+ before
+ 35ac5aa56b91f103.709e39a50c33edcf.8690434c4bba36c8.6bcabe8a0193e08a
+ af56fc2e32919827.681a06b2cf4fd289.da9bf39c8c63156c.004ad1c3cae1bcd2
+ 38f580fa7969fd0c.4828a5175c0f56ca.cf3646b9c0dd53bb.d1b6379f8f8e994a
+ 2dd4e076dda35c5f.ee9593c1ce8035bd.c3ac380f82b52d62.b8da6e096ba5321e
+ 9382f1ed7a32457c
+ after
+ 35ac5aa56b91f103.709e39a50c33edcf.8690434c4bba36c8.6bcabe8a0193e08a
+ af56fc2e32919827.681a06b2cf4fd289.da9bf39c8c63156c.004ad1c3cae1bcd2
+ 0000000000000000.0000000000000000.c3ac380f82b52d62.b8da6e096ba5321e
+ 2dd4e076dda35c5f.ee9593c1ce8035bd.c3ac380f82b52d62.b8da6e096ba5321e
+ 9382f1ed7a32457c
+VMOVAPD_GtoE_128(mem)
+ before
+ 3c793d37d9428c8e.ea411a0cfacef0cc.342b4a9a42ad2a8f.1048c60b6f76df0c
+ 918cccd3a4e0c380.cb8629296b73f6fe.f7b64890d3a3f26c.1458eb1722aca566
+ 6c871cadf619a87f.2cf0093acc20a9a2.1404088d9e6c487f.2926a3a138e4ba1b
+ aa36a8b1ebf8f5b7.69cbb6aaba604763.65e0077fbe17eaf5.adffea134ca95bd8
+ fa2ebcdbfb87c449
+ after
+ 3c793d37d9428c8e.ea411a0cfacef0cc.1404088d9e6c487f.2926a3a138e4ba1b
+ 918cccd3a4e0c380.cb8629296b73f6fe.f7b64890d3a3f26c.1458eb1722aca566
+ 6c871cadf619a87f.2cf0093acc20a9a2.1404088d9e6c487f.2926a3a138e4ba1b
+ aa36a8b1ebf8f5b7.69cbb6aaba604763.65e0077fbe17eaf5.adffea134ca95bd8
+ fa2ebcdbfb87c449
+
+VMOVAPD_GtoE_256(reg)
+ before
+ 6e011664e00b3019.2765eccca0896753.dd632ce4d0bf0aee.c715bf5150ad92fa
+ 63c3f31a97c0ddf5.c0e065e830d8b980.e6036856abca2fef.1670aeef6f3cfcb9
+ 36bf4f69bd320489.4f728df3b8f2a969.dff9656be70cf111.2fbd4f4537cfe65e
+ 444226bdeeeee480.b1e9e2d853e2f13b.248f1f8f1e128e01.ecc81e3fc6730a16
+ 2a5d98c93533250d
+ after
+ 6e011664e00b3019.2765eccca0896753.dd632ce4d0bf0aee.c715bf5150ad92fa
+ 63c3f31a97c0ddf5.c0e065e830d8b980.e6036856abca2fef.1670aeef6f3cfcb9
+ 444226bdeeeee480.b1e9e2d853e2f13b.248f1f8f1e128e01.ecc81e3fc6730a16
+ 444226bdeeeee480.b1e9e2d853e2f13b.248f1f8f1e128e01.ecc81e3fc6730a16
+ 2a5d98c93533250d
+VMOVAPD_GtoE_256(mem)
+ before
+ c54838d0a21bf36f.e7987582c57fb786.c20fdf821eb54e22.1112932eef673f6a
+ 99547a3e28372f67.7c0d3624de71ba48.5eb101df34767b49.02cebbb5f39743f9
+ 824eda01e4949621.5fed6710d6512972.619bc2dab23135dd.520f958ec92ed55a
+ 5c03d403f23ee4ca.ec8303b048aa40b0.a799a05fb3f33809.5f201c260ab93038
+ 844f4cea54c3913f
+ after
+ 824eda01e4949621.5fed6710d6512972.619bc2dab23135dd.520f958ec92ed55a
+ 99547a3e28372f67.7c0d3624de71ba48.5eb101df34767b49.02cebbb5f39743f9
+ 824eda01e4949621.5fed6710d6512972.619bc2dab23135dd.520f958ec92ed55a
+ 5c03d403f23ee4ca.ec8303b048aa40b0.a799a05fb3f33809.5f201c260ab93038
+ 844f4cea54c3913f
+
+VMOVAPD_GtoE_256(reg)
+ before
+ 1ce6224543d9331d.033de5326d3fd48e.801d0772d1083aad.0c76165a54c740fa
+ 853299a27286537c.53c8877971a52399.75056dc00df85415.6cffa0b8b0b908dc
+ 197fad6f7e562d08.287238c41b7b8d16.288833089605c995.a301ba63e3d54dda
+ 36195a1702d6fd6e.5e0674ff86cece31.f5f254b50bbbd7d9.8d46e1490a28cb21
+ 069b905441be3edc
+ after
+ 1ce6224543d9331d.033de5326d3fd48e.801d0772d1083aad.0c76165a54c740fa
+ 853299a27286537c.53c8877971a52399.75056dc00df85415.6cffa0b8b0b908dc
+ 36195a1702d6fd6e.5e0674ff86cece31.f5f254b50bbbd7d9.8d46e1490a28cb21
+ 36195a1702d6fd6e.5e0674ff86cece31.f5f254b50bbbd7d9.8d46e1490a28cb21
+ 069b905441be3edc
+VMOVAPD_GtoE_256(mem)
+ before
+ eacc4372a3a16138.364c9c069a91fe5a.d14fb516cfa9a117.388fcc3305a7b88d
+ 15a4768d4cdff161.776370a8e3136e77.5d1a79f51118c4f4.4daa98ee2354a95c
+ 63f1a6935984a982.53acd06978e98672.de333a886928f0f3.9091b352fe4fe5f2
+ b07d4d6fe69a47c8.2871bab5f69e85f7.306677bcf2e4e441.5d8e19cb3422a9fc
+ 10eec6c5615c3126
+ after
+ 63f1a6935984a982.53acd06978e98672.de333a886928f0f3.9091b352fe4fe5f2
+ 15a4768d4cdff161.776370a8e3136e77.5d1a79f51118c4f4.4daa98ee2354a95c
+ 63f1a6935984a982.53acd06978e98672.de333a886928f0f3.9091b352fe4fe5f2
+ b07d4d6fe69a47c8.2871bab5f69e85f7.306677bcf2e4e441.5d8e19cb3422a9fc
+ 10eec6c5615c3126
+
+VMOVAPD_GtoE_256(reg)
+ before
+ 04fdb6ad2086b91c.d715e90d0d2f855e.50ff2af9f9bea5b1.2e7fa97bc8585a0a
+ 9707e6ed0e2e7c88.b685f559ed4f2071.28a21a9f1bd6234c.b6494db308910f79
+ 245850f3c6dfb719.2899ee3f9f04d32c.0da68815fb713b76.a392e04ece9abfbb
+ 073bf22ae426a679.081d4eac425d5cbd.59566fc5321b29d8.d024dd3a357f25fb
+ 1bccc062594dfe66
+ after
+ 04fdb6ad2086b91c.d715e90d0d2f855e.50ff2af9f9bea5b1.2e7fa97bc8585a0a
+ 9707e6ed0e2e7c88.b685f559ed4f2071.28a21a9f1bd6234c.b6494db308910f79
+ 073bf22ae426a679.081d4eac425d5cbd.59566fc5321b29d8.d024dd3a357f25fb
+ 073bf22ae426a679.081d4eac425d5cbd.59566fc5321b29d8.d024dd3a357f25fb
+ 1bccc062594dfe66
+VMOVAPD_GtoE_256(mem)
+ before
+ 5f5606b2570f0628.9cfec8fd058d8555.34dc938aef63754d.6900cb1d5f612821
+ 778e29164bd2f96c.3eebccdac5a38f58.86a438c7c524da0b.99ee98881bce75fb
+ 4140a77a50a0925e.4b4ffc2cbef1012f.dc3fb94dddab4920.466dd37204ee4b12
+ 9737fbca82878e2c.1e76535f8f051786.117a930a55047cbb.cac97747b64ee814
+ 824e7f73cc7986ab
+ after
+ 4140a77a50a0925e.4b4ffc2cbef1012f.dc3fb94dddab4920.466dd37204ee4b12
+ 778e29164bd2f96c.3eebccdac5a38f58.86a438c7c524da0b.99ee98881bce75fb
+ 4140a77a50a0925e.4b4ffc2cbef1012f.dc3fb94dddab4920.466dd37204ee4b12
+ 9737fbca82878e2c.1e76535f8f051786.117a930a55047cbb.cac97747b64ee814
+ 824e7f73cc7986ab
+
+VMOVAPS_GtoE_128(reg)
+ before
+ ca48ea62e3fb6183.5740a2f2fe93a900.12abcddfd26a0c08.002140e9493c3006
+ fe02b1809661b749.5b2816dfdfcf9e06.853c661923ad1d61.86003ed5d45e202e
+ 7acad23a8136c2a9.80b9d57b42472a6b.d1741b771f59863f.80e208bc12760a5e
+ 9aea48fa4106bf4e.a3bf5ab44207095b.549ee66661fa834c.c8951b892091a8c3
+ 3ce3f1281abab688
+ after
+ ca48ea62e3fb6183.5740a2f2fe93a900.12abcddfd26a0c08.002140e9493c3006
+ fe02b1809661b749.5b2816dfdfcf9e06.853c661923ad1d61.86003ed5d45e202e
+ 0000000000000000.0000000000000000.549ee66661fa834c.c8951b892091a8c3
+ 9aea48fa4106bf4e.a3bf5ab44207095b.549ee66661fa834c.c8951b892091a8c3
+ 3ce3f1281abab688
+VMOVAPS_GtoE_128(mem)
+ before
+ b69908861bfef2da.baaf0f2e725eeae4.9e082175fc1cf701.6807c553861d4f34
+ 1383db8d3f6816e5.36652341afc97e19.4f5fa6a98b91af8a.6bfbb3a9294d27a4
+ 306de62aa304dfd4.6a57819e94d4b897.908f663e0c73ee21.b7c6add3e6164748
+ e722a64a62de08d4.b2d323b3be0ad40a.3e65dc1f9acd70f3.a9b3ae3f5b04eacb
+ 9e10b15821a44dda
+ after
+ b69908861bfef2da.baaf0f2e725eeae4.908f663e0c73ee21.b7c6add3e6164748
+ 1383db8d3f6816e5.36652341afc97e19.4f5fa6a98b91af8a.6bfbb3a9294d27a4
+ 306de62aa304dfd4.6a57819e94d4b897.908f663e0c73ee21.b7c6add3e6164748
+ e722a64a62de08d4.b2d323b3be0ad40a.3e65dc1f9acd70f3.a9b3ae3f5b04eacb
+ 9e10b15821a44dda
+
+VMOVAPS_GtoE_128(reg)
+ before
+ f027b48ad682ac20.157095d899034f10.692307ebc8f70e20.35ad843851abf02c
+ fc45b3411628434b.962131bf647f6eb6.ed9528b24f27a182.5133da754e192bf7
+ 1fb6a8e97c244d04.4602f5eddd5c22ef.99738374ee27cadf.6fc35ac3ad24dd81
+ b3c691efa40207f9.01df5d4d22a826e9.c90a129e4282c4e1.6929810c89d7c2f5
+ 1c30ca3dfe3f9580
+ after
+ f027b48ad682ac20.157095d899034f10.692307ebc8f70e20.35ad843851abf02c
+ fc45b3411628434b.962131bf647f6eb6.ed9528b24f27a182.5133da754e192bf7
+ 0000000000000000.0000000000000000.c90a129e4282c4e1.6929810c89d7c2f5
+ b3c691efa40207f9.01df5d4d22a826e9.c90a129e4282c4e1.6929810c89d7c2f5
+ 1c30ca3dfe3f9580
+VMOVAPS_GtoE_128(mem)
+ before
+ 64a5b1432967134e.15c169bd2b4dadd6.a384e6cb4f6e37d0.d9a5d39ae6c5cd34
+ 1d55b208255bf88a.a1f22cc0ac917a47.09bd0b537fbb11d0.2492c1d5777b1f85
+ 230a4a7a0f280061.b3a7d665c45aacf7.0d5648d1cf9a7014.081cd9bc9030f780
+ 5290f48403d9e6fe.a82a64170f357c92.8c1a19315a170fc8.df8e15b9cd7090d0
+ 0735733acbc82822
+ after
+ 64a5b1432967134e.15c169bd2b4dadd6.0d5648d1cf9a7014.081cd9bc9030f780
+ 1d55b208255bf88a.a1f22cc0ac917a47.09bd0b537fbb11d0.2492c1d5777b1f85
+ 230a4a7a0f280061.b3a7d665c45aacf7.0d5648d1cf9a7014.081cd9bc9030f780
+ 5290f48403d9e6fe.a82a64170f357c92.8c1a19315a170fc8.df8e15b9cd7090d0
+ 0735733acbc82822
+
+VMOVAPS_GtoE_128(reg)
+ before
+ db5deeaa26c4f922.86b52c121b7a678e.dac8d14127ad29c5.61d6fa603d3fab19
+ b652827579ee3f7b.9b446e1076183f3d.a6cd1951ab4eed3c.6a566848931d0033
+ f6602b0760d438d9.6d08366a2dbe2936.688538b234a506a3.8266ded778bdca41
+ f5d2e6cc78011eea.d7ce010c5f78e2a6.7c3c2bd0613dada5.85d2d8f7092cc470
+ 4f66d2966174abec
+ after
+ db5deeaa26c4f922.86b52c121b7a678e.dac8d14127ad29c5.61d6fa603d3fab19
+ b652827579ee3f7b.9b446e1076183f3d.a6cd1951ab4eed3c.6a566848931d0033
+ 0000000000000000.0000000000000000.7c3c2bd0613dada5.85d2d8f7092cc470
+ f5d2e6cc78011eea.d7ce010c5f78e2a6.7c3c2bd0613dada5.85d2d8f7092cc470
+ 4f66d2966174abec
+VMOVAPS_GtoE_128(mem)
+ before
+ bced489f9da43ae0.11f6ae305d022e58.b7624ae2255326b8.3e3dec17cba321ee
+ a834b7fed9c62f79.a4167f9faa62a3cf.e8908dd99d5ab099.09d579f310619c2b
+ ee089a9f30e644e2.0b7f5586fbadbbfc.462446dbe3993e75.3b50cdd1cc055b08
+ 6c336d6ebe103648.a37d2c4fed70b08b.ade9f2d6121d8a77.2ffae51b9a1b9a30
+ 411fbb3f172e9450
+ after
+ bced489f9da43ae0.11f6ae305d022e58.462446dbe3993e75.3b50cdd1cc055b08
+ a834b7fed9c62f79.a4167f9faa62a3cf.e8908dd99d5ab099.09d579f310619c2b
+ ee089a9f30e644e2.0b7f5586fbadbbfc.462446dbe3993e75.3b50cdd1cc055b08
+ 6c336d6ebe103648.a37d2c4fed70b08b.ade9f2d6121d8a77.2ffae51b9a1b9a30
+ 411fbb3f172e9450
+
+VMOVAPS_GtoE_256(reg)
+ before
+ cd0b4da7deca8614.fd81ac57a051c0d7.c65c01681b36be27.f8ad0cb447f150cc
+ 2f0996c18b7bac27.7cc0d446f1b4a0ba.d167cf3b228b237d.053a0f639d214e9f
+ c26792f8bbce4136.c7bb6028ce45901d.20ec92369dfc1938.af5d7ace30ba3e1d
+ e46f3eb8094e83ec.b93dcce752114c2e.103546c42914dd05.d1e2c6e11dc7dd71
+ 499571887f54e6c8
+ after
+ cd0b4da7deca8614.fd81ac57a051c0d7.c65c01681b36be27.f8ad0cb447f150cc
+ 2f0996c18b7bac27.7cc0d446f1b4a0ba.d167cf3b228b237d.053a0f639d214e9f
+ e46f3eb8094e83ec.b93dcce752114c2e.103546c42914dd05.d1e2c6e11dc7dd71
+ e46f3eb8094e83ec.b93dcce752114c2e.103546c42914dd05.d1e2c6e11dc7dd71
+ 499571887f54e6c8
+VMOVAPS_GtoE_256(mem)
+ before
+ f142f6af736e164e.f06e946d1288acf6.2d13947199239217.fb8fe851615fab90
+ a7b4d1421520292e.41b092837207f800.010935b0c1871c04.3e467349e16abe84
+ 45b87e2e7f77db95.35813366c457a5b5.0feb2992e34aa722.35a6e31847c0538e
+ a91b795dd07de8af.272c7482a405edc1.3585ee021d77ee9d.3cfa342a2ceea659
+ af9062eb2e7ef292
+ after
+ 45b87e2e7f77db95.35813366c457a5b5.0feb2992e34aa722.35a6e31847c0538e
+ a7b4d1421520292e.41b092837207f800.010935b0c1871c04.3e467349e16abe84
+ 45b87e2e7f77db95.35813366c457a5b5.0feb2992e34aa722.35a6e31847c0538e
+ a91b795dd07de8af.272c7482a405edc1.3585ee021d77ee9d.3cfa342a2ceea659
+ af9062eb2e7ef292
+
+VMOVAPS_GtoE_256(reg)
+ before
+ eab26ac8e9fe74e5.ada73fbc21400ba7.72ff4f43af9c0dd2.4da3ffec8b1bafa0
+ 49ae472bf8fa68fd.2e284b3891cc01a9.7444c21680a84092.3410d93c4840a458
+ 28cef582f7fd0a87.096c19bc392c85e3.8748c865b4b6c4ad.c799f6de70f589f0
+ e35e70378393952e.183e2633386c557f.08575d9ee650d3d0.e00ad4be20431c96
+ 5c2feec973381773
+ after
+ eab26ac8e9fe74e5.ada73fbc21400ba7.72ff4f43af9c0dd2.4da3ffec8b1bafa0
+ 49ae472bf8fa68fd.2e284b3891cc01a9.7444c21680a84092.3410d93c4840a458
+ e35e70378393952e.183e2633386c557f.08575d9ee650d3d0.e00ad4be20431c96
+ e35e70378393952e.183e2633386c557f.08575d9ee650d3d0.e00ad4be20431c96
+ 5c2feec973381773
+VMOVAPS_GtoE_256(mem)
+ before
+ 18d4c0e986df37b5.d6acb5b83748469f.3869ec8ba7982ba9.54bd7d2cb205a9a7
+ eec5c60b75453788.5d03be70b0a95986.46bae9afa4bdc38e.c5c6257ab55e84dd
+ bbcd7d1c5a74d518.d4ae89cb8a410a8e.1cfd988b4be6db5a.b9bd50f68be99e1f
+ 5bba6007547bcb90.97fa12355f9d9464.97fe750bb7202d38.8aeffa0bcf323418
+ 95a91f251ec38275
+ after
+ bbcd7d1c5a74d518.d4ae89cb8a410a8e.1cfd988b4be6db5a.b9bd50f68be99e1f
+ eec5c60b75453788.5d03be70b0a95986.46bae9afa4bdc38e.c5c6257ab55e84dd
+ bbcd7d1c5a74d518.d4ae89cb8a410a8e.1cfd988b4be6db5a.b9bd50f68be99e1f
+ 5bba6007547bcb90.97fa12355f9d9464.97fe750bb7202d38.8aeffa0bcf323418
+ 95a91f251ec38275
+
+VMOVAPS_GtoE_256(reg)
+ before
+ 3735bcb1132ac3e2.aa56ebb87c63d61c.0134531ace4734b3.9389fd1c04767655
+ cadfcc194af3340a.846e9a1af13ab1ea.70a54ae670ce2628.ec6aaaa84ff472dc
+ abf54aca60a8119a.c6ceea1bcc0b1923.3f9cf106e3bba56f.7e6cfa9cb4a7dcfa
+ 36c23531f0d7953e.4a4256a62be3caf6.ca6446e4c39cee33.255c68e54e9a71db
+ bd07716e39d9edaa
+ after
+ 3735bcb1132ac3e2.aa56ebb87c63d61c.0134531ace4734b3.9389fd1c04767655
+ cadfcc194af3340a.846e9a1af13ab1ea.70a54ae670ce2628.ec6aaaa84ff472dc
+ 36c23531f0d7953e.4a4256a62be3caf6.ca6446e4c39cee33.255c68e54e9a71db
+ 36c23531f0d7953e.4a4256a62be3caf6.ca6446e4c39cee33.255c68e54e9a71db
+ bd07716e39d9edaa
+VMOVAPS_GtoE_256(mem)
+ before
+ 22378f2292700b94.c79186b8970cfda1.ed9559a82acd808d.6c4845eeabfc3d20
+ 30b840ef746c88c4.baaf3bcdf1d2856f.8b95720be4d5f614.8396e88e3868cee4
+ c358ffc0fcd92067.6b684edb98b56955.000c1abc7608e9b8.69982d32056bdc29
+ b7e2488145c18fa9.3608bd4e2b41e4ff.27c7cfa8fb7115a5.7c9b0f45ae91a49b
+ 16eb8a33d06762e7
+ after
+ c358ffc0fcd92067.6b684edb98b56955.000c1abc7608e9b8.69982d32056bdc29
+ 30b840ef746c88c4.baaf3bcdf1d2856f.8b95720be4d5f614.8396e88e3868cee4
+ c358ffc0fcd92067.6b684edb98b56955.000c1abc7608e9b8.69982d32056bdc29
+ b7e2488145c18fa9.3608bd4e2b41e4ff.27c7cfa8fb7115a5.7c9b0f45ae91a49b
+ 16eb8a33d06762e7
+
+VMOVAPS_EtoG_128(reg)
+ before
+ 95d39a68077751b9.e821981e6c3290b5.77db849143033319.de920bb98f1c3607
+ 53a13c50ee50aebc.32e269838c38e0b8.8a2d9d127f86924e.00394cdd4f160709
+ ae9f6b57217bb59d.71f1399cc2dd3bdd.cb49063d78563d4a.69870eff576a45d7
+ 001b23e93d86a208.811a8356292f5d51.967dba7ccc006fba.f54acb0ac224ab9e
+ 804c01ecac51f78a
+ after
+ 95d39a68077751b9.e821981e6c3290b5.77db849143033319.de920bb98f1c3607
+ 0000000000000000.0000000000000000.cb49063d78563d4a.69870eff576a45d7
+ ae9f6b57217bb59d.71f1399cc2dd3bdd.cb49063d78563d4a.69870eff576a45d7
+ 001b23e93d86a208.811a8356292f5d51.967dba7ccc006fba.f54acb0ac224ab9e
+ 804c01ecac51f78a
+VMOVAPS_EtoG_128(mem)
+ before
+ e55a2b9032fce3c6.a75f6072ddfdb0a8.3d29c49bde3a013f.4713b53c170f654a
+ 0240c5e26f312c7f.fdb81e5f9e6a1c29.83e97659fc08e4d5.3a58f3eaf4105aa5
+ b2ca4bcf80fd8de1.5f715a1a1c5b2238.2e28177a9fa7c23c.cb9871f0008e8c78
+ d0c43a41806bc417.2ad80f11f15cfd81.19b022ece42356a3.561e2abcd615356f
+ 36381ab812319235
+ after
+ e55a2b9032fce3c6.a75f6072ddfdb0a8.3d29c49bde3a013f.4713b53c170f654a
+ 0240c5e26f312c7f.fdb81e5f9e6a1c29.83e97659fc08e4d5.3a58f3eaf4105aa5
+ b2ca4bcf80fd8de1.5f715a1a1c5b2238.2e28177a9fa7c23c.cb9871f0008e8c78
+ 0000000000000000.0000000000000000.3d29c49bde3a013f.4713b53c170f654a
+ 36381ab812319235
+
+VMOVAPS_EtoG_128(reg)
+ before
+ c9303d52516fde77.3af90d258c878b4e.b83739afbbf7eab0.224e139ae7865d33
+ 6a538ff52e5a56e0.cb374068bf5e9eb1.66dcd46016ba2570.24ce6670c3df931b
+ 75ed0d0d467f361d.5e484ff436fbbb6d.9011dd909d31ea6d.fafc985a9437b485
+ 454ab2063569bada.d1f9b6b70c6a9cad.92234fabede67455.82a42444779c7b9e
+ 9691861a8719a591
+ after
+ c9303d52516fde77.3af90d258c878b4e.b83739afbbf7eab0.224e139ae7865d33
+ 0000000000000000.0000000000000000.9011dd909d31ea6d.fafc985a9437b485
+ 75ed0d0d467f361d.5e484ff436fbbb6d.9011dd909d31ea6d.fafc985a9437b485
+ 454ab2063569bada.d1f9b6b70c6a9cad.92234fabede67455.82a42444779c7b9e
+ 9691861a8719a591
+VMOVAPS_EtoG_128(mem)
+ before
+ 14903ac9e1baee8b.38b67a4c95a41ec2.fe16f29c5db8fe9e.c85e261da16800d1
+ d66ebd3ba08c11b7.a87d614b05bd9d81.c36b7e8f46f09c6c.8f0d5e525640ca90
+ baf5895de19acb42.f3ea64701f3f74c5.fac3d67be31f3442.417ef3b6a7fc0d3c
+ 9af11c1cbff1d858.734a7e257fb6de38.80ec764f4f50804d.3bfbe2b630270781
+ d9d126bc8e4df20d
+ after
+ 14903ac9e1baee8b.38b67a4c95a41ec2.fe16f29c5db8fe9e.c85e261da16800d1
+ d66ebd3ba08c11b7.a87d614b05bd9d81.c36b7e8f46f09c6c.8f0d5e525640ca90
+ baf5895de19acb42.f3ea64701f3f74c5.fac3d67be31f3442.417ef3b6a7fc0d3c
+ 0000000000000000.0000000000000000.fe16f29c5db8fe9e.c85e261da16800d1
+ d9d126bc8e4df20d
+
+VMOVAPS_EtoG_128(reg)
+ before
+ 774cbb365dfb0a89.5330f263579bf424.86e9abd8c1ae1886.32b0dbf4a68f3cb9
+ 70b89d8e37bc8da4.c27d851dc4a7dad3.8613e7f383b45e5c.eadc805705e826b1
+ 2261c932bb1db508.c1a35238231e4791.d1142ee45e54ec66.853ce1648868f861
+ e8933a8d83a8be61.2d6fd69f8f0ef789.c1387d16f018fe4f.e09c7a08491a6ff7
+ d5c7c72d670b469c
+ after
+ 774cbb365dfb0a89.5330f263579bf424.86e9abd8c1ae1886.32b0dbf4a68f3cb9
+ 0000000000000000.0000000000000000.d1142ee45e54ec66.853ce1648868f861
+ 2261c932bb1db508.c1a35238231e4791.d1142ee45e54ec66.853ce1648868f861
+ e8933a8d83a8be61.2d6fd69f8f0ef789.c1387d16f018fe4f.e09c7a08491a6ff7
+ d5c7c72d670b469c
+VMOVAPS_EtoG_128(mem)
+ before
+ 418b45c1fc463b7f.1e99eb0b2bece65c.e2ad8c3e2582a5e7.b3cacff5d58ecfc4
+ 00b26fae24d708ca.20c0db18507267a5.bd29f10200870ed9.041820eda8429c70
+ ee09c1e2fcca6aaa.4a5403208dc87ee8.98af7fd53c28ee88.0e6c6c6a06bea000
+ e85db7489f2c1c4a.f7a1618f7f7967cf.500bb4a4f6710123.2e13afd88a901920
+ c159e6a3d044417b
+ after
+ 418b45c1fc463b7f.1e99eb0b2bece65c.e2ad8c3e2582a5e7.b3cacff5d58ecfc4
+ 00b26fae24d708ca.20c0db18507267a5.bd29f10200870ed9.041820eda8429c70
+ ee09c1e2fcca6aaa.4a5403208dc87ee8.98af7fd53c28ee88.0e6c6c6a06bea000
+ 0000000000000000.0000000000000000.e2ad8c3e2582a5e7.b3cacff5d58ecfc4
+ c159e6a3d044417b
+
+VMOVAPD_EtoG_256(reg)
+ before
+ 21890c38756454be.c877cecc2a09dbd7.85f3efd2c1125d09.c1080b5c496e02d4
+ abf11d01147e9095.6b26805ab86b637c.4f96ac53f01d9d40.c77400e7522caec7
+ bbdb166c4a1e2fab.ad354bde65607066.b0d5917fa7296321.3e190f332db7c12a
+ ad95f1e3b2cf6eac.6a6fab444ef3bdc1.06fd9bc382bfeb57.02c4b52af519f726
+ ef406cbac6600bea
+ after
+ 21890c38756454be.c877cecc2a09dbd7.85f3efd2c1125d09.c1080b5c496e02d4
+ bbdb166c4a1e2fab.ad354bde65607066.b0d5917fa7296321.3e190f332db7c12a
+ bbdb166c4a1e2fab.ad354bde65607066.b0d5917fa7296321.3e190f332db7c12a
+ ad95f1e3b2cf6eac.6a6fab444ef3bdc1.06fd9bc382bfeb57.02c4b52af519f726
+ ef406cbac6600bea
+VMOVAPD_EtoG_256(mem)
+ before
+ e15bb2cebd97baa0.dd69acd4e91d8945.7ea11a798f3107b8.ac5bc78a1e6d708f
+ b4e00352f5cbc074.a7a442aa8b94bb22.c597156743250a77.fd39104017be2f75
+ 449ad9328b07d894.6791afd132c141ef.1a1d19fc86db822c.57e37250083f64b4
+ 6d56b25a9a57bf29.797ef0b57c2f5757.5bffa12275602a01.14a7e9288d7b4af8
+ 92d0723343fe1eef
+ after
+ e15bb2cebd97baa0.dd69acd4e91d8945.7ea11a798f3107b8.ac5bc78a1e6d708f
+ b4e00352f5cbc074.a7a442aa8b94bb22.c597156743250a77.fd39104017be2f75
+ 449ad9328b07d894.6791afd132c141ef.1a1d19fc86db822c.57e37250083f64b4
+ e15bb2cebd97baa0.dd69acd4e91d8945.7ea11a798f3107b8.ac5bc78a1e6d708f
+ 92d0723343fe1eef
+
+VMOVAPD_EtoG_256(reg)
+ before
+ 2ba908dec6551c43.0ae009b73fc83162.39b600c2056a3806.63092ac72cbfbf22
+ 3d7fa793b00b80a0.f9045a339565e969.0384da6468ff22a9.0e062ed6c604fcbd
+ 229e4bbfa0ac85b3.158e21bbb83aa56a.33357d0742794eec.38c42b3b5f3c9ffb
+ 3752f1cf30c56828.3a49db3cc5541f92.2515e2182e65fb7a.bc0d9ce21472620b
+ 78aefdb700b20217
+ after
+ 2ba908dec6551c43.0ae009b73fc83162.39b600c2056a3806.63092ac72cbfbf22
+ 229e4bbfa0ac85b3.158e21bbb83aa56a.33357d0742794eec.38c42b3b5f3c9ffb
+ 229e4bbfa0ac85b3.158e21bbb83aa56a.33357d0742794eec.38c42b3b5f3c9ffb
+ 3752f1cf30c56828.3a49db3cc5541f92.2515e2182e65fb7a.bc0d9ce21472620b
+ 78aefdb700b20217
+VMOVAPD_EtoG_256(mem)
+ before
+ 4773caa640093a4b.d9e7932dfce165aa.430302a1d8be130d.35700601c84e6400
+ 0427809bef82c8d4.62a92f47a18cb7e6.0e8614d50c843f06.be92e630adc0c42a
+ 8d989a832a2966de.2fe3c088ba539b87.769f8cc67db35daa.1ec67d10794757a3
+ bd9094480c0bd094.9ce2435be4c14d3a.561ae75f48562a25.b059c70cc7705b18
+ d098c19233c60a34
+ after
+ 4773caa640093a4b.d9e7932dfce165aa.430302a1d8be130d.35700601c84e6400
+ 0427809bef82c8d4.62a92f47a18cb7e6.0e8614d50c843f06.be92e630adc0c42a
+ 8d989a832a2966de.2fe3c088ba539b87.769f8cc67db35daa.1ec67d10794757a3
+ 4773caa640093a4b.d9e7932dfce165aa.430302a1d8be130d.35700601c84e6400
+ d098c19233c60a34
+
+VMOVAPD_EtoG_256(reg)
+ before
+ d9cd660d5ad6a1a4.6fdcead8b233c423.05f3b22eba6209ab.8cc39f8c897a61a2
+ 2945b1e9d82b5c14.8148181e37aefcb7.c7600b6cd8c30a85.f26632395b29bf4d
+ 1b4ba1924751762f.cda09b05b786357b.3c754981db6f8d75.66ce1b52da710054
+ 0a2d2f7546d52ca1.31b0ee7b50c92a9b.c18068da5ff2ce26.c2c8d7c4235ee0e1
+ e421e07951fb1b20
+ after
+ d9cd660d5ad6a1a4.6fdcead8b233c423.05f3b22eba6209ab.8cc39f8c897a61a2
+ 1b4ba1924751762f.cda09b05b786357b.3c754981db6f8d75.66ce1b52da710054
+ 1b4ba1924751762f.cda09b05b786357b.3c754981db6f8d75.66ce1b52da710054
+ 0a2d2f7546d52ca1.31b0ee7b50c92a9b.c18068da5ff2ce26.c2c8d7c4235ee0e1
+ e421e07951fb1b20
+VMOVAPD_EtoG_256(mem)
+ before
+ a6a3b45f81546c3e.543558fc6e41ba18.87448d6b1b839945.b2cc64e1ffd90945
+ e61bce60ce759067.53b119945e245c3e.ac27f4c136bf3ca2.6ba43a0358af797e
+ 7e54aa6a556b42c6.65eb6daaaf074dbf.7d26a069bc89cfe1.4855e5ad05015b7c
+ 4b1cc46831414088.e43050a90078ca48.d40e0c4fcaed102c.a52b6149a259eaec
+ de72aa45cc456479
+ after
+ a6a3b45f81546c3e.543558fc6e41ba18.87448d6b1b839945.b2cc64e1ffd90945
+ e61bce60ce759067.53b119945e245c3e.ac27f4c136bf3ca2.6ba43a0358af797e
+ 7e54aa6a556b42c6.65eb6daaaf074dbf.7d26a069bc89cfe1.4855e5ad05015b7c
+ a6a3b45f81546c3e.543558fc6e41ba18.87448d6b1b839945.b2cc64e1ffd90945
+ de72aa45cc456479
+
+VMOVAPD_EtoG_128(reg)
+ before
+ 4f76bd0c1e5103d0.293d99457f0444d8.2ecbbffcea030f85.8ea8b4607cf8b9b0
+ 5482950a3508049d.f584a4ef5abf0ae3.9d0ab4110b325721.88c31486edb58798
+ 48e42eabacf6a28b.89bd6151de7e50d5.8e382d53ff93e0c9.9c2aa8af39313511
+ 89e6845b20a71a47.c2b44c58284dd0d9.5ea0252e61b2e328.a7a8edc57d778146
+ 850b5eb6d4932564
+ after
+ 4f76bd0c1e5103d0.293d99457f0444d8.2ecbbffcea030f85.8ea8b4607cf8b9b0
+ 0000000000000000.0000000000000000.8e382d53ff93e0c9.9c2aa8af39313511
+ 48e42eabacf6a28b.89bd6151de7e50d5.8e382d53ff93e0c9.9c2aa8af39313511
+ 89e6845b20a71a47.c2b44c58284dd0d9.5ea0252e61b2e328.a7a8edc57d778146
+ 850b5eb6d4932564
+VMOVAPD_EtoG_128(mem)
+ before
+ 121d776d5b92de97.72d593862ca8a87c.7c35e1ee5439471c.678f990ecd199feb
+ 2babb4d62d7e670a.5ffd58986d8488d7.930c9d007d4d71ca.0651835fe0564ebe
+ aa8192dd67667dea.abaacefd7ec8f603.e304fb7bbf96090e.9732e18e36f52d4c
+ 6c6b8b6e2453dc62.b427f122fcff2dae.49eb7749371fcc14.777eae056a807842
+ 0080e63118856b4c
+ after
+ 121d776d5b92de97.72d593862ca8a87c.7c35e1ee5439471c.678f990ecd199feb
+ 2babb4d62d7e670a.5ffd58986d8488d7.930c9d007d4d71ca.0651835fe0564ebe
+ aa8192dd67667dea.abaacefd7ec8f603.e304fb7bbf96090e.9732e18e36f52d4c
+ 0000000000000000.0000000000000000.7c35e1ee5439471c.678f990ecd199feb
+ 0080e63118856b4c
+
+VMOVAPD_EtoG_128(reg)
+ before
+ 8f86857fdd904115.4d341d758053409f.d5c2bd7182b56981.9f8b8d5800f47609
+ 80da885a542b3749.29aac3de997164cd.69c52e58ad77e82b.c2b1ba923722c219
+ 2fc9ea2d1ae48895.dc97fa9588ba0517.ce7d414218d0e456.8e2879e5f8b46d70
+ f89fa766ca4772a5.42c83c876b39dfaa.5f36f19a5f4c9aae.dfbe463c5db63338
+ 903e9d838535d0a0
+ after
+ 8f86857fdd904115.4d341d758053409f.d5c2bd7182b56981.9f8b8d5800f47609
+ 0000000000000000.0000000000000000.ce7d414218d0e456.8e2879e5f8b46d70
+ 2fc9ea2d1ae48895.dc97fa9588ba0517.ce7d414218d0e456.8e2879e5f8b46d70
+ f89fa766ca4772a5.42c83c876b39dfaa.5f36f19a5f4c9aae.dfbe463c5db63338
+ 903e9d838535d0a0
+VMOVAPD_EtoG_128(mem)
+ before
+ 7f73faa6893cffd2.37a8bb7001df2f25.3609079e5efaaeb1.773c3ace1f7746e0
+ 872ada9188d77dfb.482f22b75a38fcc0.9626d6c87c0a2d59.74db1949f4de2398
+ 842fb8319b130646.8782d9a772de1422.3dea25f0e17419ce.b05e8877790d6f81
+ 524e1070e0fb56e0.50ebdbace45eb4f8.07237102aa442d3b.881385c44a8e6348
+ 59440b9d04ef3e98
+ after
+ 7f73faa6893cffd2.37a8bb7001df2f25.3609079e5efaaeb1.773c3ace1f7746e0
+ 872ada9188d77dfb.482f22b75a38fcc0.9626d6c87c0a2d59.74db1949f4de2398
+ 842fb8319b130646.8782d9a772de1422.3dea25f0e17419ce.b05e8877790d6f81
+ 0000000000000000.0000000000000000.3609079e5efaaeb1.773c3ace1f7746e0
+ 59440b9d04ef3e98
+
+VMOVAPD_EtoG_128(reg)
+ before
+ 7d3e166c42bb3a1e.cc535e3b739b28f5.ffb724334d4318ee.d09b35e9f28727cc
+ 524da39fa17f9486.d0091f7f6f0039b0.f032b1a6481a7caf.731fed93d648c1af
+ 32bdaca0bcc6887b.393ece27f135453e.7ea87c73716d1be8.ce7b15ec7193b80e
+ 7ad92fdd301c52aa.e3bce71e144607ca.0765830465cb3245.bc7b29dee075c715
+ 18eba6563ef9acf1
+ after
+ 7d3e166c42bb3a1e.cc535e3b739b28f5.ffb724334d4318ee.d09b35e9f28727cc
+ 0000000000000000.0000000000000000.7ea87c73716d1be8.ce7b15ec7193b80e
+ 32bdaca0bcc6887b.393ece27f135453e.7ea87c73716d1be8.ce7b15ec7193b80e
+ 7ad92fdd301c52aa.e3bce71e144607ca.0765830465cb3245.bc7b29dee075c715
+ 18eba6563ef9acf1
+VMOVAPD_EtoG_128(mem)
+ before
+ c0960640a82b21ce.86ef27c0980e2dbf.a950e652f4403c81.e6b4c1c7c0bdfd71
+ 8f4ac7893918e2d7.b34991b791275665.69c647aeae2ea08e.77e332271dd1b819
+ 60d1651b0ecbad39.5b34672db6f40848.fdea871e5d1cef1e.153cd39018929ee8
+ 11f85ae442513c20.dbfca78ea4ff8116.4388218e1e17e45d.1e0c9e6e4e8dec8b
+ ed9f912d5b4ddeae
+ after
+ c0960640a82b21ce.86ef27c0980e2dbf.a950e652f4403c81.e6b4c1c7c0bdfd71
+ 8f4ac7893918e2d7.b34991b791275665.69c647aeae2ea08e.77e332271dd1b819
+ 60d1651b0ecbad39.5b34672db6f40848.fdea871e5d1cef1e.153cd39018929ee8
+ 0000000000000000.0000000000000000.a950e652f4403c81.e6b4c1c7c0bdfd71
+ ed9f912d5b4ddeae
+
+VMOVUPD_GtoE_128(reg)
+ before
+ dd41a739d95eaffc.7c8b24cff2b54cb7.8fed4c46f6d6fb78.156b91ea0d2a3c76
+ 4c3ddcfe674c9c21.7f563ec83903982b.d35352c24805b21d.5160531f4462b396
+ 94e12de89ea4e1cb.f42424bb3347dea7.0379b66c3716e4af.d134e317e2c904e9
+ 137795641df2baa4.b9c35294fd8ed858.7bad72b15f98cbda.73b1bec0016dec9a
+ 11a45f04bd5a27d6
+ after
+ dd41a739d95eaffc.7c8b24cff2b54cb7.8fed4c46f6d6fb78.156b91ea0d2a3c76
+ 4c3ddcfe674c9c21.7f563ec83903982b.d35352c24805b21d.5160531f4462b396
+ 0000000000000000.0000000000000000.7bad72b15f98cbda.73b1bec0016dec9a
+ 137795641df2baa4.b9c35294fd8ed858.7bad72b15f98cbda.73b1bec0016dec9a
+ 11a45f04bd5a27d6
+VMOVUPD_GtoE_128(mem)
+ before
+ 88d842d1329b71c8.234c10dc7dc06258.a8fd453fb3e34269.973984fe5b14a44c
+ b51be4127e3c859d.22ac9abe5d9c1694.9e9f77a87053da07.b36ae7bdc718abae
+ 7237bfb3ba492080.6ae32f7556111204.777566bb50e85a5e.2b8c975c402f1baf
+ 9cf9519f04cffe9e.593ccc6c06ac9153.104b8e6570b17f99.5bea914662e531f9
+ 9fd2d0e7c7c72938
+ after
+ 88d842d1329b71c8.234c10dc7dc06258.777566bb50e85a5e.2b8c975c402f1baf
+ b51be4127e3c859d.22ac9abe5d9c1694.9e9f77a87053da07.b36ae7bdc718abae
+ 7237bfb3ba492080.6ae32f7556111204.777566bb50e85a5e.2b8c975c402f1baf
+ 9cf9519f04cffe9e.593ccc6c06ac9153.104b8e6570b17f99.5bea914662e531f9
+ 9fd2d0e7c7c72938
+
+VMOVUPD_GtoE_128(reg)
+ before
+ 538e50aa0e603e19.0f2e15c578d9da23.49056c1109f8d02e.43ec6990ebb704e5
+ d36c0dfed13dae48.a89f870e3174713a.97880bcffa810b40.ed26752ade08a76d
+ 7ab6034cace9b370.411b24674bab7f10.a012a51275d47e36.eac32d1e64af225e
+ a6b92f013cf0893e.b76d66bce38ac0d0.beef3747177c64bc.17910d579ab932e4
+ 4e5a91c39b31922a
+ after
+ 538e50aa0e603e19.0f2e15c578d9da23.49056c1109f8d02e.43ec6990ebb704e5
+ d36c0dfed13dae48.a89f870e3174713a.97880bcffa810b40.ed26752ade08a76d
+ 0000000000000000.0000000000000000.beef3747177c64bc.17910d579ab932e4
+ a6b92f013cf0893e.b76d66bce38ac0d0.beef3747177c64bc.17910d579ab932e4
+ 4e5a91c39b31922a
+VMOVUPD_GtoE_128(mem)
+ before
+ 6cea354d8423ff5d.b2c18c891cde6e5e.e660cbfa151eefa7.4e6bbbd87c05fa7d
+ 4d0f76e1709b35a8.f9191651e8409c7b.aac2ce0bfc72c9c1.acd22f323ffc7c26
+ cd94cf6b7ca6f038.d90fc9c33ea15042.df5decddb4920a49.35708ec2fcec2562
+ c844bcd8c350eb39.adeda24db78ec55e.61fe9f5b5a8a6e6c.4390d5f2506233de
+ 337ffe30d6e8df46
+ after
+ 6cea354d8423ff5d.b2c18c891cde6e5e.df5decddb4920a49.35708ec2fcec2562
+ 4d0f76e1709b35a8.f9191651e8409c7b.aac2ce0bfc72c9c1.acd22f323ffc7c26
+ cd94cf6b7ca6f038.d90fc9c33ea15042.df5decddb4920a49.35708ec2fcec2562
+ c844bcd8c350eb39.adeda24db78ec55e.61fe9f5b5a8a6e6c.4390d5f2506233de
+ 337ffe30d6e8df46
+
+VMOVUPD_GtoE_128(reg)
+ before
+ 618907e72b0c6845.1aecba1261a3e3d6.d0009b59f192397c.0c7165700967b055
+ 29faeb83ea5a0888.9f58430673ad943c.a094b2558839e647.bc81b90ade358d31
+ e71ea76fb05dfcba.3354d5a11579ba96.77f5e2ac1710086d.4dfc1714f4fec02c
+ f741351918a18088.b1acebce62141011.b36f28ca3aa2dd97.9bacfc7a68d00771
+ 825ee22855b71c2d
+ after
+ 618907e72b0c6845.1aecba1261a3e3d6.d0009b59f192397c.0c7165700967b055
+ 29faeb83ea5a0888.9f58430673ad943c.a094b2558839e647.bc81b90ade358d31
+ 0000000000000000.0000000000000000.b36f28ca3aa2dd97.9bacfc7a68d00771
+ f741351918a18088.b1acebce62141011.b36f28ca3aa2dd97.9bacfc7a68d00771
+ 825ee22855b71c2d
+VMOVUPD_GtoE_128(mem)
+ before
+ ddde470bd8bdbc8b.b5ae93edbfb2d09e.f72c0178768953d9.ae4d7e1b8e7b9f74
+ 8af8a60d0cf0a2b8.7db2bc55401d27a7.e09f948d6ee43e19.c6dde20bae288bad
+ 64787c1c0e5c8ce0.ab9aacbe386dc250.48d31ff865328ffe.55694f073734dcf1
+ 472a4322f90b342e.9ab05f95422fdd44.0b921da5787e00b3.b93ec179c52bd0ea
+ 4ca835cef39aa145
+ after
+ ddde470bd8bdbc8b.b5ae93edbfb2d09e.48d31ff865328ffe.55694f073734dcf1
+ 8af8a60d0cf0a2b8.7db2bc55401d27a7.e09f948d6ee43e19.c6dde20bae288bad
+ 64787c1c0e5c8ce0.ab9aacbe386dc250.48d31ff865328ffe.55694f073734dcf1
+ 472a4322f90b342e.9ab05f95422fdd44.0b921da5787e00b3.b93ec179c52bd0ea
+ 4ca835cef39aa145
+
+VMOVSS_XMM_M32(reg)
+ before
+ 6bf3a5735d0c8bad.0ed9790de90b56ce.a840d244faedb330.04a90d80c3d44e65
+ 726a0fd3a00dcccf.975299c7fb68b0ee.3098ff39fd3681c0.11e468756041343f
+ be5b6e59572a9e56.bd611f3e4b2cfcb8.8e03e4dee793839f.0d0eac716ed0706f
+ a910bf731eee3eef.5bd2885df465f758.1ecc7da15392f47a.d3f5535e068ebc1e
+ 4163db294685d47b
+ after
+ 6bf3a5735d0c8bad.0ed9790de90b56ce.a840d244faedb330.04a90d80c3d44e65
+ 726a0fd3a00dcccf.975299c7fb68b0ee.3098ff39fd3681c0.11e468756041343f
+ be5b6e59572a9e56.bd611f3e4b2cfcb8.8e03e4dee793839f.0d0eac716ed0706f
+ a910bf731eee3eef.5bd2885df465f758.1ecc7da15392f47a.d3f5535e068ebc1e
+ 4163db294685d47b
+VMOVSS_XMM_M32(mem)
+ before
+ 3125c0bf4ac376af.90d6fc8c93e5e746.4f714e10121f5cfb.3b40c4edddbe12fc
+ 81077c0b2d545ce9.cff923104f9cd706.730aef43c265e8cd.43abb72e22a417d2
+ 0bd58df80c434353.c2c52f6bf09e48dc.a568e6e31f4357f9.915951d0bdcf3fa7
+ ad5b6e74029ce61a.c5861c0912777773.bf59afda46c565ac.80968e3f4bcbc829
+ 6ead6ae76824ec01
+ after
+ 3125c0bf4ac376af.90d6fc8c93e5e746.4f714e10121f5cfb.3b40c4ed22a417d2
+ 81077c0b2d545ce9.cff923104f9cd706.730aef43c265e8cd.43abb72e22a417d2
+ 0bd58df80c434353.c2c52f6bf09e48dc.a568e6e31f4357f9.915951d0bdcf3fa7
+ ad5b6e74029ce61a.c5861c0912777773.bf59afda46c565ac.80968e3f4bcbc829
+ 6ead6ae76824ec01
+
+VMOVSS_XMM_M32(reg)
+ before
+ b5ece235ae67e8de.41659b6a2b6b0369.3487e75750b49f78.9fa7c71552f8ce12
+ b39df093bc20f769.a5be90c6a4bd546d.6c158abf46e0fd97.1f1fa98160e74d56
+ c20d926f2bd95751.b333ca74899d9551.c77d03af9187cd7b.1d8dd0088b9f9fa4
+ 4088c43399204240.4891c361f5188442.a1094d91cd364bd1.73bcbb98f02a7f2a
+ fe7ae31caa97ab11
+ after
+ b5ece235ae67e8de.41659b6a2b6b0369.3487e75750b49f78.9fa7c71552f8ce12
+ b39df093bc20f769.a5be90c6a4bd546d.6c158abf46e0fd97.1f1fa98160e74d56
+ c20d926f2bd95751.b333ca74899d9551.c77d03af9187cd7b.1d8dd0088b9f9fa4
+ 4088c43399204240.4891c361f5188442.a1094d91cd364bd1.73bcbb98f02a7f2a
+ fe7ae31caa97ab11
+VMOVSS_XMM_M32(mem)
+ before
+ 9b91c680d6efdd88.875a804da280f4e3.41a2f9770438db6c.580665d39578b244
+ 24cedeb08f40d1b9.f5cfc428e186abe5.7832e7a3d30c57fa.47bf45e085da3f81
+ 76fea998f29545d0.e4328a30f3bda1f3.ca0f0ad27d9db319.ca82eb233ae72e34
+ 6deaa3241afbf3fb.b1d1d1d173b113b8.1304ddee1ff9adf5.3d99520a4f2bbb08
+ fc517600613221aa
+ after
+ 9b91c680d6efdd88.875a804da280f4e3.41a2f9770438db6c.580665d385da3f81
+ 24cedeb08f40d1b9.f5cfc428e186abe5.7832e7a3d30c57fa.47bf45e085da3f81
+ 76fea998f29545d0.e4328a30f3bda1f3.ca0f0ad27d9db319.ca82eb233ae72e34
+ 6deaa3241afbf3fb.b1d1d1d173b113b8.1304ddee1ff9adf5.3d99520a4f2bbb08
+ fc517600613221aa
+
+VMOVSS_XMM_M32(reg)
+ before
+ 63f753710b899dc5.e5614640237c9864.b8f69277fdef3ce1.2fdcdbe5d42bffb9
+ cdd5e6caeabb6b06.bb2e10d82a27ef37.56eeca8e2e025a1a.fb6482a2b9406691
+ 98372a759955c618.c91c7cd94b05b6a1.e5057682a276a70e.51684e11e9439daa
+ 1f6b1bdfb5e2eba9.ecf9062da024a7ce.c28691c0f4d8606a.0eb4b91e81406130
+ 0e1441b59c446e4f
+ after
+ 63f753710b899dc5.e5614640237c9864.b8f69277fdef3ce1.2fdcdbe5d42bffb9
+ cdd5e6caeabb6b06.bb2e10d82a27ef37.56eeca8e2e025a1a.fb6482a2b9406691
+ 98372a759955c618.c91c7cd94b05b6a1.e5057682a276a70e.51684e11e9439daa
+ 1f6b1bdfb5e2eba9.ecf9062da024a7ce.c28691c0f4d8606a.0eb4b91e81406130
+ 0e1441b59c446e4f
+VMOVSS_XMM_M32(mem)
+ before
+ 2d5361c257598032.bdbbb575d9ee1662.008f2ac2488f7fe9.49bf17b2c0b3c0d9
+ 473f9531cd8e5205.d075f5a2a20583f2.e1ab65835d53f91f.d6fa04c6a3930408
+ 38a259ef1aeca1f5.b3e3d5d1abb46d02.6b19325bfb7bd29b.c6845566380568a3
+ dc492ae65b81292e.c152537090871141.7aa40d383f13c68a.73aa05001c942855
+ 3ab610ffeacd7fcb
+ after
+ 2d5361c257598032.bdbbb575d9ee1662.008f2ac2488f7fe9.49bf17b2a3930408
+ 473f9531cd8e5205.d075f5a2a20583f2.e1ab65835d53f91f.d6fa04c6a3930408
+ 38a259ef1aeca1f5.b3e3d5d1abb46d02.6b19325bfb7bd29b.c6845566380568a3
+ dc492ae65b81292e.c152537090871141.7aa40d383f13c68a.73aa05001c942855
+ 3ab610ffeacd7fcb
+
+VMOVSD_XMM_M64(reg)
+ before
+ 77f472cf3f3aaab0.0f008304ac59a6db.580e6aeaee08aa59.ea1a720544289117
+ 86b228dcb66ae5b1.ac93e033287ed329.d26217ab61c576f7.9645ddae27c5ee70
+ c33a2c92ece66c7a.91cdbd61ebfe6d44.8d9c541f8449afc6.5cf2cb2003f69abe
+ 8ada7c5d7c3c7ab6.997c977912e52f57.e3061fb2f3219273.17edb745f5c85130
+ a3021d0a1846cff0
+ after
+ 77f472cf3f3aaab0.0f008304ac59a6db.580e6aeaee08aa59.ea1a720544289117
+ 86b228dcb66ae5b1.ac93e033287ed329.d26217ab61c576f7.9645ddae27c5ee70
+ c33a2c92ece66c7a.91cdbd61ebfe6d44.8d9c541f8449afc6.5cf2cb2003f69abe
+ 8ada7c5d7c3c7ab6.997c977912e52f57.e3061fb2f3219273.17edb745f5c85130
+ a3021d0a1846cff0
+VMOVSD_XMM_M64(mem)
+ before
+ dcfd795c887ccf2a.36dc13a903f74c12.a06ae867b93dd78f.31ee73d04bd85ba9
+ 9daa482562770e0b.258deee31ca31d39.82642e17fa141f17.d49e4ce627fa4515
+ c4d40453c24248bf.b239077563cd2bd8.1a36e475f476c41c.2663a75e24148d63
+ 2c482bd1c3e93871.392b5ccd7500b09b.46ac876dc16d81ca.84887fa6ddb16f3e
+ 4b5bcf28ef5d2653
+ after
+ dcfd795c887ccf2a.36dc13a903f74c12.a06ae867b93dd78f.d49e4ce627fa4515
+ 9daa482562770e0b.258deee31ca31d39.82642e17fa141f17.d49e4ce627fa4515
+ c4d40453c24248bf.b239077563cd2bd8.1a36e475f476c41c.2663a75e24148d63
+ 2c482bd1c3e93871.392b5ccd7500b09b.46ac876dc16d81ca.84887fa6ddb16f3e
+ 4b5bcf28ef5d2653
+
+VMOVSD_XMM_M64(reg)
+ before
+ d5269652f5a5ef4e.b0d2398a81799b4e.16b1e856eec9e92d.e19291eb7d07144c
+ 7f37cd8f8c1406da.2e3ea86c19fd2d82.a415a77b69b3113b.c6b380dc445037ce
+ a5d8714b4f36a7a3.8058f662a782aa38.41a496aa824a6570.d3ddcf2a3453a67e
+ a4567ff2db980d56.84ec9d584612cd9d.48aaaf4ed61b2179.e2dafac3661c1f86
+ d1777e91f8b75c12
+ after
+ d5269652f5a5ef4e.b0d2398a81799b4e.16b1e856eec9e92d.e19291eb7d07144c
+ 7f37cd8f8c1406da.2e3ea86c19fd2d82.a415a77b69b3113b.c6b380dc445037ce
+ a5d8714b4f36a7a3.8058f662a782aa38.41a496aa824a6570.d3ddcf2a3453a67e
+ a4567ff2db980d56.84ec9d584612cd9d.48aaaf4ed61b2179.e2dafac3661c1f86
+ d1777e91f8b75c12
+VMOVSD_XMM_M64(mem)
+ before
+ 7a80d68206311a4f.d6fdf2f0cbc5759f.14c51b3b12bb53dc.1473f0d300b08101
+ bbc17d81ab951469.9818c6b1bb4a1b2a.0eb1ecf52889f822.034b54a59d98c1b6
+ 6e05f27a04ef088b.46f5f8a148b13aa2.4c7a8a73a387779a.707ed831495c1c41
+ 711aae592c4cb0e2.3cde822d0e8810b3.aced73a2a0c18d71.b65776e19e8acf51
+ 33232c223aad158f
+ after
+ 7a80d68206311a4f.d6fdf2f0cbc5759f.14c51b3b12bb53dc.034b54a59d98c1b6
+ bbc17d81ab951469.9818c6b1bb4a1b2a.0eb1ecf52889f822.034b54a59d98c1b6
+ 6e05f27a04ef088b.46f5f8a148b13aa2.4c7a8a73a387779a.707ed831495c1c41
+ 711aae592c4cb0e2.3cde822d0e8810b3.aced73a2a0c18d71.b65776e19e8acf51
+ 33232c223aad158f
+
+VMOVSD_XMM_M64(reg)
+ before
+ 412ff561b9522baa.9eca2e0a3fb7c89a.d62062bfa85bd70a.08d6226c3a43f6d3
+ 3ec5cd09b6044d4c.d2e2ef795a3d0ede.700793c5b2b5cb53.3e0013bf8e1a6eeb
+ 8431b185ce4fb722.ea2e6c9398e93cda.66df12aac9222a3a.2839c286b751b0e6
+ 70c19b439cc0a5d7.c07a214216c70fbb.14f4d9d9892e2e6a.a34bacadd2f579f0
+ 8b034c20fa118534
+ after
+ 412ff561b9522baa.9eca2e0a3fb7c89a.d62062bfa85bd70a.08d6226c3a43f6d3
+ 3ec5cd09b6044d4c.d2e2ef795a3d0ede.700793c5b2b5cb53.3e0013bf8e1a6eeb
+ 8431b185ce4fb722.ea2e6c9398e93cda.66df12aac9222a3a.2839c286b751b0e6
+ 70c19b439cc0a5d7.c07a214216c70fbb.14f4d9d9892e2e6a.a34bacadd2f579f0
+ 8b034c20fa118534
+VMOVSD_XMM_M64(mem)
+ before
+ bd2e1ecb4bb18fde.5fbf89aebde25218.31928b73f0e342ad.d592e6c08c66138f
+ 13959e9ae2e1541b.ab797632cc41fb90.19412413404a93dc.070434ca71551756
+ 6a074979dbae9017.b1395e3b656adbec.54546a0d2507bc73.0597bf63d188746b
+ 9e4f99545123fffe.ce4c3e3525e830d8.bf98d84cb8277a9e.2b9784f74b896779
+ d5507df378e72c2d
+ after
+ bd2e1ecb4bb18fde.5fbf89aebde25218.31928b73f0e342ad.070434ca71551756
+ 13959e9ae2e1541b.ab797632cc41fb90.19412413404a93dc.070434ca71551756
+ 6a074979dbae9017.b1395e3b656adbec.54546a0d2507bc73.0597bf63d188746b
+ 9e4f99545123fffe.ce4c3e3525e830d8.bf98d84cb8277a9e.2b9784f74b896779
+ d5507df378e72c2d
+
+VMOVSS_M64_XMM(reg)
+ before
+ 5e0ea8c1f72bfe33.8b380c18604d5cfb.5cfe118da84734ff.34d7ebbe18b5888b
+ 241d00ce61e31a36.0d901daf2537643a.b89bd3ad8914230e.90dd1d4e5ebda363
+ 82c88187549abce3.00214907bcedd3e8.3e6e800264da3bb0.af78ece8a84c8755
+ d35d28566cdd20e5.40b80a0b3f7c6531.4ac514f9d625b692.6d73d379126df08b
+ a6994eebb72c9931
+ after
+ 5e0ea8c1f72bfe33.8b380c18604d5cfb.5cfe118da84734ff.34d7ebbe18b5888b
+ 241d00ce61e31a36.0d901daf2537643a.b89bd3ad8914230e.90dd1d4e5ebda363
+ 82c88187549abce3.00214907bcedd3e8.3e6e800264da3bb0.af78ece8a84c8755
+ d35d28566cdd20e5.40b80a0b3f7c6531.4ac514f9d625b692.6d73d379126df08b
+ a6994eebb72c9931
+VMOVSS_M64_XMM(mem)
+ before
+ 36b7d92bb4953f75.7526efa9443781e9.a921dea6cdefd541.38ea8cfd7a82d160
+ f99af12624b59e80.c270d4eb79341c9a.172740c67f52e043.642ae379ed7cc8c5
+ cb0b11c623987281.1887d388a6612da6.6698ac5674b24163.2ad115dbcaa0d66e
+ 88d9b5f9ce4876a2.d1b6e6ec6748efb6.723e9f42c51ab6ce.e62b1e8eae783806
+ f483fafe34922a3a
+ after
+ 36b7d92bb4953f75.7526efa9443781e9.a921dea6cdefd541.38ea8cfd7a82d160
+ 0000000000000000.0000000000000000.0000000000000000.000000007a82d160
+ cb0b11c623987281.1887d388a6612da6.6698ac5674b24163.2ad115dbcaa0d66e
+ 88d9b5f9ce4876a2.d1b6e6ec6748efb6.723e9f42c51ab6ce.e62b1e8eae783806
+ f483fafe34922a3a
+
+VMOVSS_M64_XMM(reg)
+ before
+ b027a697f97ae7b6.0bcf59a941d3670f.4b4b0a8359789f78.17e693779196f9b0
+ 76611dc598bbac25.32b87ac4964500f5.e0903cb9177a7998.315c06dff133c734
+ a27e5bf5aee1b534.d8629235eca8ff80.eed277fa3edcb9c2.9b6c736703fcdb87
+ 90ca5c91d6783e8e.d9971fe85d0a1edb.cf5db8b36a2a9aa1.33e256fce3fdf3d5
+ d48a2c88ac43c949
+ after
+ b027a697f97ae7b6.0bcf59a941d3670f.4b4b0a8359789f78.17e693779196f9b0
+ 76611dc598bbac25.32b87ac4964500f5.e0903cb9177a7998.315c06dff133c734
+ a27e5bf5aee1b534.d8629235eca8ff80.eed277fa3edcb9c2.9b6c736703fcdb87
+ 90ca5c91d6783e8e.d9971fe85d0a1edb.cf5db8b36a2a9aa1.33e256fce3fdf3d5
+ d48a2c88ac43c949
+VMOVSS_M64_XMM(mem)
+ before
+ 5a2f70f97bd91910.9c911d07ac0d82e0.10249cc905771a33.e07df94e35ee59e2
+ a09e9e3a6bcba155.221f99c1cd2bbfd6.5bd586c501f9aeb4.7e7e38393eb63230
+ 84a3323698261b45.7dbfcc2dd55f2e1b.957557c66c9f9889.03ac70de1e0e6038
+ e00aa8db1ff5440c.0bbeb2b65f340e5c.99d28db9637292df.cc529dab748020a5
+ 36bdbb0bd99aae24
+ after
+ 5a2f70f97bd91910.9c911d07ac0d82e0.10249cc905771a33.e07df94e35ee59e2
+ 0000000000000000.0000000000000000.0000000000000000.0000000035ee59e2
+ 84a3323698261b45.7dbfcc2dd55f2e1b.957557c66c9f9889.03ac70de1e0e6038
+ e00aa8db1ff5440c.0bbeb2b65f340e5c.99d28db9637292df.cc529dab748020a5
+ 36bdbb0bd99aae24
+
+VMOVSS_M64_XMM(reg)
+ before
+ 9b3ac76aebe84661.929f7d141b44d7d5.276947c807369944.45b6a38b018058e1
+ 5813bb3446f42307.752e2ccea92091cc.2d0a88cf6af10c80.73ee152662d4a8bc
+ c99495d5854d82c3.648231f3e5942e1f.78ee703723f2a3bb.01476078a47a3c9b
+ 4a0b51b9457c9f40.3d690870eaac6af7.6660fb6ccfc599a2.c98afe6ce07fd1ab
+ a9866ded34ee2218
+ after
+ 9b3ac76aebe84661.929f7d141b44d7d5.276947c807369944.45b6a38b018058e1
+ 5813bb3446f42307.752e2ccea92091cc.2d0a88cf6af10c80.73ee152662d4a8bc
+ c99495d5854d82c3.648231f3e5942e1f.78ee703723f2a3bb.01476078a47a3c9b
+ 4a0b51b9457c9f40.3d690870eaac6af7.6660fb6ccfc599a2.c98afe6ce07fd1ab
+ a9866ded34ee2218
+VMOVSS_M64_XMM(mem)
+ before
+ 7b0628e9bcd4ed0d.37c3e94c210fb62b.daad2e31d4750183.51ae25da09f42be1
+ 1dd5ac4b933becb7.ec075bfbb5910230.181b1d23c0faaeed.9722ebed6e0d9523
+ 69c07300d531db42.c524a1309e8ec0fa.d47f5330c9482e62.920a4812999b1315
+ 3c94fbf29fc278d9.1e66ba5978932b36.e8a44b460b6a3c0d.a0b038b3272be063
+ 1b61b73eb34839b8
+ after
+ 7b0628e9bcd4ed0d.37c3e94c210fb62b.daad2e31d4750183.51ae25da09f42be1
+ 0000000000000000.0000000000000000.0000000000000000.0000000009f42be1
+ 69c07300d531db42.c524a1309e8ec0fa.d47f5330c9482e62.920a4812999b1315
+ 3c94fbf29fc278d9.1e66ba5978932b36.e8a44b460b6a3c0d.a0b038b3272be063
+ 1b61b73eb34839b8
+
+VMOVSD_M64_XMM(reg)
+ before
+ 6169c11eda7e5ac1.731bbf0e0df97da8.53199fe0de2b818f.31588250a46c961b
+ cc1353be375a7e29.e8213b4139e2a7dd.c0894d336ce3fcb2.8c65723aad5af6b7
+ b9ad688c6767e29d.7874ec754289b1a2.c101c1bdbf45d94b.d39899f04441180e
+ 8581fcf30531c2c8.ffdf4c9842fb5923.b2cff6ea72e05305.e3be725e852cba4c
+ 98a079708b28969c
+ after
+ 6169c11eda7e5ac1.731bbf0e0df97da8.53199fe0de2b818f.31588250a46c961b
+ cc1353be375a7e29.e8213b4139e2a7dd.c0894d336ce3fcb2.8c65723aad5af6b7
+ b9ad688c6767e29d.7874ec754289b1a2.c101c1bdbf45d94b.d39899f04441180e
+ 8581fcf30531c2c8.ffdf4c9842fb5923.b2cff6ea72e05305.e3be725e852cba4c
+ 98a079708b28969c
+VMOVSD_M64_XMM(mem)
+ before
+ ce0d2b127240692b.8adc0b5fad455a57.5a2dd9945544598d.ee3de826223da78d
+ 62d003315780ee24.250a923dfc2ee5f6.632b0e57986e6e0c.d39894dd6aea118e
+ 2eb47cb756f5e3b4.b3578bf78e78a050.f7a567cc268753cb.bc2cf47be772cdb5
+ 0f8715918aa90207.8e0ff4fafeb0c712.f26761df1b9ac5f7.0545066d346216ad
+ 092fc51dee442a23
+ after
+ ce0d2b127240692b.8adc0b5fad455a57.5a2dd9945544598d.ee3de826223da78d
+ 0000000000000000.0000000000000000.0000000000000000.ee3de826223da78d
+ 2eb47cb756f5e3b4.b3578bf78e78a050.f7a567cc268753cb.bc2cf47be772cdb5
+ 0f8715918aa90207.8e0ff4fafeb0c712.f26761df1b9ac5f7.0545066d346216ad
+ 092fc51dee442a23
+
+VMOVSD_M64_XMM(reg)
+ before
+ 26352df9b0a742c3.e11347ac0fab0848.137dc8b3e86196e7.303d777c95b480bb
+ b7a43b6b16149d38.80258ff30204b0a4.9eef048ce917487c.8df2258fade04044
+ 17c8eae1bd19752f.c8896a527ec2b746.8bafa2f39c5f1a7d.e554e704812ac0be
+ a4ed36c641410754.950a53b4a0f1d95b.360aa0539ec44795.142d39c82d9fbd54
+ f64a98c5cc4af333
+ after
+ 26352df9b0a742c3.e11347ac0fab0848.137dc8b3e86196e7.303d777c95b480bb
+ b7a43b6b16149d38.80258ff30204b0a4.9eef048ce917487c.8df2258fade04044
+ 17c8eae1bd19752f.c8896a527ec2b746.8bafa2f39c5f1a7d.e554e704812ac0be
+ a4ed36c641410754.950a53b4a0f1d95b.360aa0539ec44795.142d39c82d9fbd54
+ f64a98c5cc4af333
+VMOVSD_M64_XMM(mem)
+ before
+ 67777fe97a371e86.b85f1b863d198f52.c376c607839bd20f.fb4cf9188ad20d71
+ 43806a1e5473f97a.b16a958d4d2c48d6.2e97403744ce5d8d.36c1a9adfd16a6bc
+ 6530d5527609413a.e95aa1470e06708b.b13a3c2efe953702.43b4ad80921b4f23
+ ab553c70fb05b1f4.be7a39201c34401e.2a2b35d9cefd1c99.7e7300fde66e4352
+ 43489e8e949abff4
+ after
+ 67777fe97a371e86.b85f1b863d198f52.c376c607839bd20f.fb4cf9188ad20d71
+ 0000000000000000.0000000000000000.0000000000000000.fb4cf9188ad20d71
+ 6530d5527609413a.e95aa1470e06708b.b13a3c2efe953702.43b4ad80921b4f23
+ ab553c70fb05b1f4.be7a39201c34401e.2a2b35d9cefd1c99.7e7300fde66e4352
+ 43489e8e949abff4
+
+VMOVSD_M64_XMM(reg)
+ before
+ ee8083a0392bffb6.f0b91c64ff7407d1.8a175b841241f73a.7436aa24cf11c87f
+ db67aba070ad3f43.1029f01a9f61fd00.aa7d03df8cb9cf8c.6b2714fc1edef6e0
+ 664913f8d5adba48.e671347ef6d850ab.7bf82b9e272905c0.eacaf04bd66e63e7
+ ea72b51605b6ad71.505d657c21e6bbfe.57d4d12b7e1cd581.cfeabbff13cfcbc1
+ f554f003f20de999
+ after
+ ee8083a0392bffb6.f0b91c64ff7407d1.8a175b841241f73a.7436aa24cf11c87f
+ db67aba070ad3f43.1029f01a9f61fd00.aa7d03df8cb9cf8c.6b2714fc1edef6e0
+ 664913f8d5adba48.e671347ef6d850ab.7bf82b9e272905c0.eacaf04bd66e63e7
+ ea72b51605b6ad71.505d657c21e6bbfe.57d4d12b7e1cd581.cfeabbff13cfcbc1
+ f554f003f20de999
+VMOVSD_M64_XMM(mem)
+ before
+ 37d40b438f327a9c.c52d8f649c555469.29b9fd003b96fc26.9b5df0f42e1e7b7c
+ 733689aa054c3af5.52c89d503515ebdd.4c507af761f4cd4f.a4de8464d2bc325d
+ 8446e4267067e5d1.ed8dd9456c82ad78.97f0574bae0deaa4.cca489e7078137cf
+ 45d09aa3ed8e365c.f1c941afde28d7e7.e46310ea3fec1152.70fbfce968f9c57e
+ ec2fd7d692b11a17
+ after
+ 37d40b438f327a9c.c52d8f649c555469.29b9fd003b96fc26.9b5df0f42e1e7b7c
+ 0000000000000000.0000000000000000.0000000000000000.9b5df0f42e1e7b7c
+ 8446e4267067e5d1.ed8dd9456c82ad78.97f0574bae0deaa4.cca489e7078137cf
+ 45d09aa3ed8e365c.f1c941afde28d7e7.e46310ea3fec1152.70fbfce968f9c57e
+ ec2fd7d692b11a17
+
+VINSERTPS_0x39_128(reg)
+ before
+ 9c8c181a20347046.949f260b97cdeac1.bcc8d0fa2694a5d5.117622be2f9dfc85
+ dc5ebb21ae0e03b7.4b81044b8b30bd2d.a9d68292e15152ef.f8f507b59a2d6868
+ 08f0ba57d9cc1115.4740b150e4c46acc.133e53e3aaec1be1.77ac3dba9da71027
+ 7c9013293df9d40c.65a9a804bf94aec9.584e3f5a1ef03c56.68663fb95418b2f0
+ a9f18a9eda8a08ed
+ after
+ 0000000000000000.0000000000000000.00000000e15152ef.f8f507b500000000
+ dc5ebb21ae0e03b7.4b81044b8b30bd2d.a9d68292e15152ef.f8f507b59a2d6868
+ 08f0ba57d9cc1115.4740b150e4c46acc.133e53e3aaec1be1.77ac3dba9da71027
+ 7c9013293df9d40c.65a9a804bf94aec9.584e3f5a1ef03c56.68663fb95418b2f0
+ a9f18a9eda8a08ed
+VINSERTPS_0x39_128(mem)
+ before
+ 141798554b0cce4a.9488c10175228949.7f88655537ad4550.d2504361d8e9f1fb
+ 86a5e7cac4a7c234.ac25c04d1dd16c78.73a8642d6919eb8f.df915a667564757c
+ dc67f2ea61699ed7.20b30c77d294b845.1bd7217a70e65bb0.d95d80d390ec0584
+ f029359f3d5d1f5e.4c7ea1ed2ff7aa5b.54df1927692052df.1e00b216c60dddc0
+ 08c6ea9ab25438db
+ after
+ 141798554b0cce4a.9488c10175228949.7f88655537ad4550.d2504361d8e9f1fb
+ 86a5e7cac4a7c234.ac25c04d1dd16c78.73a8642d6919eb8f.df915a667564757c
+ 0000000000000000.0000000000000000.73a8642d00000000.00000000d8e9f1fb
+ f029359f3d5d1f5e.4c7ea1ed2ff7aa5b.54df1927692052df.1e00b216c60dddc0
+ 08c6ea9ab25438db
+
+VINSERTPS_0x39_128(reg)
+ before
+ f4fa26cbf14c5382.9fb72cd7749000f6.8cd17c1ad1857e66.fa8ec7206fd28c49
+ 3fe961151e816a60.c5dc547c230dffca.3cfa986a54ca6f13.eaaea7519f08c41a
+ 43e098e4d580b922.3f65287c65e0d607.b843f1495252bb0e.fe0c35a614cfb77d
+ 5d29c5a4b3d47b74.e71f24c2571542d9.5cf984236aaa9c02.1373ed0bea31219f
+ 05b14c6d3e3dbeab
+ after
+ 0000000000000000.0000000000000000.0000000054ca6f13.eaaea75100000000
+ 3fe961151e816a60.c5dc547c230dffca.3cfa986a54ca6f13.eaaea7519f08c41a
+ 43e098e4d580b922.3f65287c65e0d607.b843f1495252bb0e.fe0c35a614cfb77d
+ 5d29c5a4b3d47b74.e71f24c2571542d9.5cf984236aaa9c02.1373ed0bea31219f
+ 05b14c6d3e3dbeab
+VINSERTPS_0x39_128(mem)
+ before
+ b090cdb62cfc49ce.e910e6c15409ed01.9ad4c43a14b9fe6b.83684b64355d4e9c
+ f0deecd4ce7c7f34.44e3f6a852ac4b76.345185d0b9d7c7ea.8bdc447951f80f88
+ a16525b143c81c08.c8edf1c34c48d07e.9161e270617c5981.cfa06acc5a061971
+ 9ff2f53ba5eddc77.d279d380dc69b9c6.8dd2570628b3705d.aa02bacaeb13a904
+ 7a4c2ee0a1acfaec
+ after
+ b090cdb62cfc49ce.e910e6c15409ed01.9ad4c43a14b9fe6b.83684b64355d4e9c
+ f0deecd4ce7c7f34.44e3f6a852ac4b76.345185d0b9d7c7ea.8bdc447951f80f88
+ 0000000000000000.0000000000000000.345185d000000000.00000000355d4e9c
+ 9ff2f53ba5eddc77.d279d380dc69b9c6.8dd2570628b3705d.aa02bacaeb13a904
+ 7a4c2ee0a1acfaec
+
+VINSERTPS_0x39_128(reg)
+ before
+ 9acbc479175c4ad6.c651d75d10f67aac.bed499499e9c42fa.046e607e2b88c7aa
+ 65cb7701e9afd36d.f24d4703a1efb3d4.e84a3e8c2f6ca7c5.d20279c486081b93
+ 399843e3b431d15e.ffb4c11973e5421b.ac27beb42a6523d4.d35b1fc5543e2845
+ 707e248d146f8255.c950c18ba3e3e5ac.66b7152d2c14f3d2.e342cd6bb236aaeb
+ de86ffa4bafd5cb2
+ after
+ 0000000000000000.0000000000000000.000000002f6ca7c5.d20279c400000000
+ 65cb7701e9afd36d.f24d4703a1efb3d4.e84a3e8c2f6ca7c5.d20279c486081b93
+ 399843e3b431d15e.ffb4c11973e5421b.ac27beb42a6523d4.d35b1fc5543e2845
+ 707e248d146f8255.c950c18ba3e3e5ac.66b7152d2c14f3d2.e342cd6bb236aaeb
+ de86ffa4bafd5cb2
+VINSERTPS_0x39_128(mem)
+ before
+ 9ff2315b8b9efbc6.68c8176ba4f520fd.2ceec4454cf556b4.72464063d004536c
+ 0451df7b3f254252.7bc417e7004de803.045a45338b28525e.2c1f39c2b3c27f4e
+ e87186f2f29fef83.06bc206ec5051513.2d60c0417b8794d7.f08ffeb670d8b223
+ 271ca1abc117bc84.66fd2e6c8ea8e5d8.82ccb15c381eda4a.1ae38aaba3d52998
+ 0665da0eea422058
+ after
+ 9ff2315b8b9efbc6.68c8176ba4f520fd.2ceec4454cf556b4.72464063d004536c
+ 0451df7b3f254252.7bc417e7004de803.045a45338b28525e.2c1f39c2b3c27f4e
+ 0000000000000000.0000000000000000.045a453300000000.00000000d004536c
+ 271ca1abc117bc84.66fd2e6c8ea8e5d8.82ccb15c381eda4a.1ae38aaba3d52998
+ 0665da0eea422058
+
+VPUNPCKLDQ_128(reg)
+ before
+ 0f61e849deadd210.9c1fac92c7996682.f5d33d4ef8c392fe.e16a956edffadde4
+ 9325b2ca1da17c6c.254623942132a8a8.108a4a7e9fe15833.2505e6658c265cd1
+ edfc33fc43ab5a17.9d5c839beaed4023.146d506a1d8e7521.296a222c5aae123d
+ 7931674aeb55a7be.df2f47943fd6e81f.5bca4b7d10572374.cb65c5af659fba52
+ e6c249daca04113f
+ after
+ 0000000000000000.0000000000000000.296a222c2505e665.5aae123d8c265cd1
+ 9325b2ca1da17c6c.254623942132a8a8.108a4a7e9fe15833.2505e6658c265cd1
+ edfc33fc43ab5a17.9d5c839beaed4023.146d506a1d8e7521.296a222c5aae123d
+ 7931674aeb55a7be.df2f47943fd6e81f.5bca4b7d10572374.cb65c5af659fba52
+ e6c249daca04113f
+VPUNPCKLDQ_128(mem)
+ before
+ 554d2c99a5e9d22e.92114b22b12ea10c.c989eb6c3bfa5cc7.42eb372214c79fd9
+ f6d2e8d8115bba4c.96e8d9ef32bf82ae.3637eb0dfb645a48.251d11c7c46b24fc
+ a31cfc832a6585c4.e0020f1d0996864f.0106c3659a209cce.60acd4d7bdcdf088
+ 3af9e1860d14efc3.cbabe818d33eeb9c.08bff05f353bdf84.50e47cbe9a7b3d2a
+ 4f1105e9f801488d
+ after
+ 554d2c99a5e9d22e.92114b22b12ea10c.c989eb6c3bfa5cc7.42eb372214c79fd9
+ f6d2e8d8115bba4c.96e8d9ef32bf82ae.3637eb0dfb645a48.251d11c7c46b24fc
+ 0000000000000000.0000000000000000.42eb3722251d11c7.14c79fd9c46b24fc
+ 3af9e1860d14efc3.cbabe818d33eeb9c.08bff05f353bdf84.50e47cbe9a7b3d2a
+ 4f1105e9f801488d
+
+VPUNPCKLDQ_128(reg)
+ before
+ ba7e6bc272e94c5e.953314ced573b474.b52f614d2b44eb41.2531ede7e7c0de97
+ ed79abb6a4c28649.919712459f8e8f04.f8d97426ae33c3e9.352736e9ccbc5732
+ 444cc0322b1532f9.0bf156d986713d9f.f2f61f10f797ae41.156c4751013a0482
+ 1b44a6a0a3708c1b.dd0c5c74a7297970.fdd25d78a3fdeaf5.9fce9d0ba246a1b2
+ b017b303c9ececef
+ after
+ 0000000000000000.0000000000000000.156c4751352736e9.013a0482ccbc5732
+ ed79abb6a4c28649.919712459f8e8f04.f8d97426ae33c3e9.352736e9ccbc5732
+ 444cc0322b1532f9.0bf156d986713d9f.f2f61f10f797ae41.156c4751013a0482
+ 1b44a6a0a3708c1b.dd0c5c74a7297970.fdd25d78a3fdeaf5.9fce9d0ba246a1b2
+ b017b303c9ececef
+VPUNPCKLDQ_128(mem)
+ before
+ 2514052595399f65.cead596ea65ecf5a.e4b6a0041dc100a4.77b92ac94df0b1b0
+ d8900f5e2038773f.b9d2d607d36b3863.fdb99f7405468f67.baf7826e92fc3f1f
+ a6594d9886f62faa.370117d7c42403e2.02e3d4b07ac2dfe4.24d862d50daed2ed
+ 6b3a3cc1e47e85d1.a6841a4a15146c82.d0febba49844af47.0fa7c5695a91a4c7
+ d8b2a7961731f258
+ after
+ 2514052595399f65.cead596ea65ecf5a.e4b6a0041dc100a4.77b92ac94df0b1b0
+ d8900f5e2038773f.b9d2d607d36b3863.fdb99f7405468f67.baf7826e92fc3f1f
+ 0000000000000000.0000000000000000.77b92ac9baf7826e.4df0b1b092fc3f1f
+ 6b3a3cc1e47e85d1.a6841a4a15146c82.d0febba49844af47.0fa7c5695a91a4c7
+ d8b2a7961731f258
+
+VPUNPCKLDQ_128(reg)
+ before
+ dc4304c8dd1bf74d.04fe57c355dc33e1.61a9dacc63c8aeef.43d7d03c7cd5b9be
+ 75a7d96b4adaf152.4b721a8cf61cf606.c4ba54c949cb06d7.383990644283ba72
+ 002a20ecf9fa1a12.1d620107e24b896b.2b0482ad64a9b0e4.89f2750905596d92
+ d917d7b58708af3a.569a89203675a93d.f1d262e44feee7c2.13ccfd15e1649048
+ b295a376f3afddc0
+ after
+ 0000000000000000.0000000000000000.89f2750938399064.05596d924283ba72
+ 75a7d96b4adaf152.4b721a8cf61cf606.c4ba54c949cb06d7.383990644283ba72
+ 002a20ecf9fa1a12.1d620107e24b896b.2b0482ad64a9b0e4.89f2750905596d92
+ d917d7b58708af3a.569a89203675a93d.f1d262e44feee7c2.13ccfd15e1649048
+ b295a376f3afddc0
+VPUNPCKLDQ_128(mem)
+ before
+ 4217e41657461128.5dbcfa33908feb75.d2e62cc30da412a7.7472efdba727e81e
+ 9f1f3ae32736e7a9.e66383d3af1b0b70.6d1168dc84e680d6.0f2f26fc07dfefa4
+ a57923c8828a1c72.d15a700080394bd7.03e9b958b646aef6.1d5401b50ba337ff
+ 30f01ab1814e6cad.7aebbb25a074e755.70389921bfd15932.fc2e7e7150fefedc
+ 0609989b727c7ee7
+ after
+ 4217e41657461128.5dbcfa33908feb75.d2e62cc30da412a7.7472efdba727e81e
+ 9f1f3ae32736e7a9.e66383d3af1b0b70.6d1168dc84e680d6.0f2f26fc07dfefa4
+ 0000000000000000.0000000000000000.7472efdb0f2f26fc.a727e81e07dfefa4
+ 30f01ab1814e6cad.7aebbb25a074e755.70389921bfd15932.fc2e7e7150fefedc
+ 0609989b727c7ee7
+
+VPACKSSDW_128(reg)
+ before
+ 99314ba10caaf3cb.1c529b8a438f9386.3d6362b0aa581a97.90cb8624bc923db7
+ 0ff293eeba139b35.4569233fe1574c2a.760d610c3b722148.3f6efa4ec99516b0
+ c6976dee1943b0d0.86022cbc7ab554c5.8137b2a5ee4d3815.59ed738a01e79f4a
+ 186ed40ec5c76f49.bde934ed27b26783.ba2b53e760769aaa.b9136dc3809395b1
+ 3dae62e763a5b310
+ after
+ 0000000000000000.0000000000000000.80007fff80008000.7fff7fff7fff8000
+ 0ff293eeba139b35.4569233fe1574c2a.760d610c3b722148.3f6efa4ec99516b0
+ c6976dee1943b0d0.86022cbc7ab554c5.8137b2a5ee4d3815.59ed738a01e79f4a
+ 186ed40ec5c76f49.bde934ed27b26783.ba2b53e760769aaa.b9136dc3809395b1
+ 3dae62e763a5b310
+VPACKSSDW_128(mem)
+ before
+ c088d0e1c52ab794.63c1c4b8592a134b.c5eab6bf065c418f.7d373f3f2c7785b2
+ 1e6e329dc32d5b68.01dd395971f8da83.7ad12f1c33bf9d15.26a57217eedf33da
+ 332c040778ba5cb9.4f0e2f5eaabefe9d.b86a19f2c9e63842.10c2e8dc4337e0cd
+ da8ec20b01de75b3.aa9fa3319f07bc44.5a80f22be5ddce42.99da9efbc70dca38
+ 1c388fde15ec2bc7
+ after
+ c088d0e1c52ab794.63c1c4b8592a134b.c5eab6bf065c418f.7d373f3f2c7785b2
+ 1e6e329dc32d5b68.01dd395971f8da83.7ad12f1c33bf9d15.26a57217eedf33da
+ 0000000000000000.0000000000000000.80007fff7fff7fff.7fff7fff7fff8000
+ da8ec20b01de75b3.aa9fa3319f07bc44.5a80f22be5ddce42.99da9efbc70dca38
+ 1c388fde15ec2bc7
+
+VPACKSSDW_128(reg)
+ before
+ f52ab7f3c9614025.f160e99679a46481.6cde9040ed5f4f25.3ee035b5a2b01a40
+ 80fa12a580f644ff.526df492fd18e34f.f216f2f52f53f4eb.3f565e7b1c6cd969
+ 18f69c60d63a7400.db835feca847ae4b.9892c5be026ee743.38aee969701cc7e9
+ 1b68529066b60cd5.676ca691973c839f.bb9f0606013c64d9.07b4536bbacca0eb
+ 8634176d14891f9b
+ after
+ 0000000000000000.0000000000000000.80007fff7fff8000.80007fff7fff7fff
+ 80fa12a580f644ff.526df492fd18e34f.f216f2f52f53f4eb.3f565e7b1c6cd969
+ 18f69c60d63a7400.db835feca847ae4b.9892c5be026ee743.38aee969701cc7e9
+ 1b68529066b60cd5.676ca691973c839f.bb9f0606013c64d9.07b4536bbacca0eb
+ 8634176d14891f9b
+VPACKSSDW_128(mem)
+ before
+ 93f9b15b9d5e0127.e49c2fa1ccf84829.d1f5456ce5041c77.b589b039c84aa658
+ 08d19d216f5702b9.cee02fffa58b64a9.f7eab968afa93600.e39cbfc3f423ea6d
+ c38658aca681dd7d.377f4e168cfc9b01.b3177d73103a8c66.a1232f1121536cc4
+ 9ee55ce65fe74fa0.79c489521ed62adc.e2470d7824c0dcd4.4b6cfc8dea676708
+ 3dc123a4ecea19e5
+ after
+ 93f9b15b9d5e0127.e49c2fa1ccf84829.d1f5456ce5041c77.b589b039c84aa658
+ 08d19d216f5702b9.cee02fffa58b64a9.f7eab968afa93600.e39cbfc3f423ea6d
+ 0000000000000000.0000000000000000.8000800080008000.8000800080008000
+ 9ee55ce65fe74fa0.79c489521ed62adc.e2470d7824c0dcd4.4b6cfc8dea676708
+ 3dc123a4ecea19e5
+
+VPACKSSDW_128(reg)
+ before
+ d36f9fc3c268bc08.76ba27bdb596144e.f2fdda20f6a54ce7.6148e5630849e077
+ 69c36c54086e8c1d.28d0341bc599e8b2.fc743feab1f63ece.0ae48220d8e0547a
+ 5b0686c55b87c7cf.8ef500eeaafc86f9.f576b41eea543c3c.bbe85f9caf91f60a
+ 0587ea815640a7cb.85f3052180cbab4e.374e33273e4b82dd.4e20f8c1a9698053
+ a058c97ce373af80
+ after
+ 0000000000000000.0000000000000000.7fff7fff7fff8000.800080007fff8000
+ 69c36c54086e8c1d.28d0341bc599e8b2.fc743feab1f63ece.0ae48220d8e0547a
+ 5b0686c55b87c7cf.8ef500eeaafc86f9.f576b41eea543c3c.bbe85f9caf91f60a
+ 0587ea815640a7cb.85f3052180cbab4e.374e33273e4b82dd.4e20f8c1a9698053
+ a058c97ce373af80
+VPACKSSDW_128(mem)
+ before
+ 8d5c4eba78bc3ebe.c39192f4962468bd.ea98c1a0641313de.204aba7048674c5f
+ f2f70465854feb39.f16f7c89b6bf4850.97aeaf5772df79d5.0ab54467a435d56c
+ a9f6666b2538701c.ea6ea4af539d8131.69024c32c53c9a5e.52dacd77ef415ab0
+ 8f26f0b775848a93.0cda04cf084b500b.3c5f121d7a3532a6.5406510cc51516d8
+ 6d85cc93c13f4790
+ after
+ 8d5c4eba78bc3ebe.c39192f4962468bd.ea98c1a0641313de.204aba7048674c5f
+ f2f70465854feb39.f16f7c89b6bf4850.97aeaf5772df79d5.0ab54467a435d56c
+ 0000000000000000.0000000000000000.80007fff7fff7fff.80007fff7fff8000
+ 8f26f0b775848a93.0cda04cf084b500b.3c5f121d7a3532a6.5406510cc51516d8
+ 6d85cc93c13f4790
+
+VPADDW_128(reg)
+ before
+ f7a33b767f4b2783.80511e35903df4cb.b2ff9a567254f18b.ec937f05abd6fdd9
+ 4fac99229cc4f25e.58446dd193726bf0.382960b02c459f5d.55680ed4772cb622
+ d1ebe204b436e6cc.f3ca5777992cab2e.f9a4544ad3a9972c.53ac3b78f8411aad
+ d9ae1386622d3d7a.2db15a13bf7970b0.53bb728e020c15a5.c22982db4a24e5a7
+ 7eac60eb8aded33c
+ after
+ 0000000000000000.0000000000000000.31cdb4faffee3689.a9144a4c6f6dd0cf
+ 4fac99229cc4f25e.58446dd193726bf0.382960b02c459f5d.55680ed4772cb622
+ d1ebe204b436e6cc.f3ca5777992cab2e.f9a4544ad3a9972c.53ac3b78f8411aad
+ d9ae1386622d3d7a.2db15a13bf7970b0.53bb728e020c15a5.c22982db4a24e5a7
+ 7eac60eb8aded33c
+VPADDW_128(mem)
+ before
+ 63014f93d37d9f97.c43f261642363414.e2c3f191206475a2.a1bcb4ea56fa5573
+ 4df3cdbf420d06e5.eceb191ff1dc0745.eece99ded8fa7731.3ef118c86a009243
+ 1850565bf298c352.aefee70d0aabf1ba.2d9ccce404463289.88a79996daaa09c0
+ a0e26453002c9409.66c48c4b2a302f1e.7bfa0890c05462d6.d92a33bf4382f697
+ 8fc5e2af41169474
+ after
+ 63014f93d37d9f97.c43f261642363414.e2c3f191206475a2.a1bcb4ea56fa5573
+ 4df3cdbf420d06e5.eceb191ff1dc0745.eece99ded8fa7731.3ef118c86a009243
+ 0000000000000000.0000000000000000.d1918b6ff95eecd3.e0adcdb2c0fae7b6
+ a0e26453002c9409.66c48c4b2a302f1e.7bfa0890c05462d6.d92a33bf4382f697
+ 8fc5e2af41169474
+
+VPADDW_128(reg)
+ before
+ 04c6a3d26ff12002.c176759387d43337.70880548ecf6fd1e.b4b3c8cf2731c242
+ 9677719469a0d6ee.57d80407a49d5d07.28984c6ded8a9666.b495898c55e80ffc
+ 9f264862ccaef2e4.3ed48d9c7292cda6.ea3e5f27c87637a1.566ac5b36785042e
+ 7c1d24a633a7af8f.51368c3c0ebf4140.11c739e219481c7c.7800fa3079155f05
+ f521a3efa5a3daac
+ after
+ 0000000000000000.0000000000000000.12d6ab94b600ce07.0aff4f3fbd6d142a
+ 9677719469a0d6ee.57d80407a49d5d07.28984c6ded8a9666.b495898c55e80ffc
+ 9f264862ccaef2e4.3ed48d9c7292cda6.ea3e5f27c87637a1.566ac5b36785042e
+ 7c1d24a633a7af8f.51368c3c0ebf4140.11c739e219481c7c.7800fa3079155f05
+ f521a3efa5a3daac
+VPADDW_128(mem)
+ before
+ a99a3cdc0a3b3250.8aa801cd3b184a9b.6eca7dd593317200.fb7fd70b7d8c81a2
+ 6f3741e3c1ea221d.2315dc447f8cffb6.705bdd511df31f13.03b2330c90cda1c0
+ 25c32ff0e9bb683e.a4afb0769c8f0989.32b6279ec91203a4.85ac4b53ed97ba82
+ a50c81f09bbbbee0.6ac179ce2daea5c3.92a7d7a7b398d9e0.ddb81a4a30760593
+ 66249c5ff6f7c19f
+ after
+ a99a3cdc0a3b3250.8aa801cd3b184a9b.6eca7dd593317200.fb7fd70b7d8c81a2
+ 6f3741e3c1ea221d.2315dc447f8cffb6.705bdd511df31f13.03b2330c90cda1c0
+ 0000000000000000.0000000000000000.df255b26b1249113.ff310a170e592362
+ a50c81f09bbbbee0.6ac179ce2daea5c3.92a7d7a7b398d9e0.ddb81a4a30760593
+ 66249c5ff6f7c19f
+
+VPADDW_128(reg)
+ before
+ 7e3acefddba52854.cddcb3cdf6f4e02e.cf9933bacf740f0e.6bfa6a58f6935ef2
+ 8047ab907a0d775c.7801417513748c55.3081dba51d6d8317.987b5a9dae0f4d07
+ c7972e846fbaea63.8145a7d210477c80.e9c66cfbb4263c89.f7f62562f817634b
+ b17555455738bc16.c67562d209786ddc.56b4e2282f2a7711.62364693efb75ce9
+ b7093a1cb0fbf40e
+ after
+ 0000000000000000.0000000000000000.1a4748a0d193bfa0.90717fffa626b052
+ 8047ab907a0d775c.7801417513748c55.3081dba51d6d8317.987b5a9dae0f4d07
+ c7972e846fbaea63.8145a7d210477c80.e9c66cfbb4263c89.f7f62562f817634b
+ b17555455738bc16.c67562d209786ddc.56b4e2282f2a7711.62364693efb75ce9
+ b7093a1cb0fbf40e
+VPADDW_128(mem)
+ before
+ d0397bea57f0e7e6.992f1c3fcd142a21.215ced6019131a95.d39639982a06705a
+ 8b9387e7fea1f09c.da107ddf6ed9702f.6fc8c4685c2441d6.bcba6db842446311
+ c2e3d901c31acc5d.d263768fd513caed.8d8363d6efb89ccc.6d6a7bf213728be2
+ 52f4ed23c2683654.db7502bd9f4f7307.555b4796eedae7a3.42f35eb4381c2578
+ 97a112684dcd6c80
+ after
+ d0397bea57f0e7e6.992f1c3fcd142a21.215ced6019131a95.d39639982a06705a
+ 8b9387e7fea1f09c.da107ddf6ed9702f.6fc8c4685c2441d6.bcba6db842446311
+ 0000000000000000.0000000000000000.9124b1c875375c6b.9050a7506c4ad36b
+ 52f4ed23c2683654.db7502bd9f4f7307.555b4796eedae7a3.42f35eb4381c2578
+ 97a112684dcd6c80
+
+VPSRLW_0x05_128(reg)
+ before
+ c8c0937cef119ea5.18943f381696ebae.53921dd36717a828.a51aea947497e086
+ 319cde5bba74f594.ee8d4c2edcb1a896.9406c43fcafaa5fc.578dcabc9df941a1
+ 2e80ee704883aef8.b1ad8ff02fc42639.fb1cf16c6381a531.487f63fb860fc722
+ 1bbabf2938c9047f.3dbe846a2cdb24c3.e522a2c6ce3ae571.54be2f3b4ae22d32
+ 5815ac6a06803100
+ after
+ 0000000000000000.0000000000000000.072905160671072b.02a5017902570169
+ 319cde5bba74f594.ee8d4c2edcb1a896.9406c43fcafaa5fc.578dcabc9df941a1
+ 2e80ee704883aef8.b1ad8ff02fc42639.fb1cf16c6381a531.487f63fb860fc722
+ 1bbabf2938c9047f.3dbe846a2cdb24c3.e522a2c6ce3ae571.54be2f3b4ae22d32
+ 5815ac6a06803100
+VPSRLW_0x05_128(mem)
+ before
+ 2e4f5573d6f48db6.54944df124d334d2.6f8da788ee035c5f.ac62d2b9a8b1a168
+ b339a641d44bfe80.345b9435a82b7aa0.21e5743791468b3a.ad297db18d7015c3
+ c39f1bc21e903f8c.195b915f61601293.3094686132b36c7f.45c3a01a18057c2e
+ 3a4d30e1d0cf0d03.5ee03fdceafb3757.7864fef3ed53bd5b.ce7c3660e5fc1354
+ a5a03bf091df16e2
+ after
+ 2e4f5573d6f48db6.54944df124d334d2.6f8da788ee035c5f.ac62d2b9a8b1a168
+ b339a641d44bfe80.345b9435a82b7aa0.21e5743791468b3a.ad297db18d7015c3
+ c39f1bc21e903f8c.195b915f61601293.3094686132b36c7f.45c3a01a18057c2e
+ 3a4d30e1d0cf0d03.5ee03fdceafb3757.7864fef3ed53bd5b.ce7c3660e5fc1354
+ a5a03bf091df16e2
+
+VPSRLW_0x05_128(reg)
+ before
+ 267aab34b83cc183.f40f628a05142414.5f369a18df8a2799.d523b2dadd3438fa
+ ad58829af49f4fe4.cdb02ca9da6c40e9.77a89e80de981b05.239b00001e619a87
+ 9684bd8ce493fdb1.a1fe0a2b6ae31cae.0483477f80b25246.3e996553cde79e2f
+ 3d4b577822a40695.4cc379fad2837591.6014928063630609.02e95cbe05d1011d
+ 4b56612de32b7f7e
+ after
+ 0000000000000000.0000000000000000.03000494031b0030.001702e5002e0008
+ ad58829af49f4fe4.cdb02ca9da6c40e9.77a89e80de981b05.239b00001e619a87
+ 9684bd8ce493fdb1.a1fe0a2b6ae31cae.0483477f80b25246.3e996553cde79e2f
+ 3d4b577822a40695.4cc379fad2837591.6014928063630609.02e95cbe05d1011d
+ 4b56612de32b7f7e
+VPSRLW_0x05_128(mem)
+ before
+ f5aef08c8202d47e.fef94cc94a5ea83d.aaccf3042d5a07bb.e9a57af1233774fa
+ dcbb85c7ff61bb48.36da98ebf94e1d54.97e5f63397738e5b.fa82fb3d5bbbd8c4
+ dc4a9dca7554f109.3e3a374acaffa187.efdafd752ddbc59b.eef911d0a7796d14
+ d027b38101e832ec.7564265259fd7282.8e7684b40a9d69a7.2255b916a4007195
+ f3e1ee7bedd91df4
+ after
+ f5aef08c8202d47e.fef94cc94a5ea83d.aaccf3042d5a07bb.e9a57af1233774fa
+ dcbb85c7ff61bb48.36da98ebf94e1d54.97e5f63397738e5b.fa82fb3d5bbbd8c4
+ dc4a9dca7554f109.3e3a374acaffa187.efdafd752ddbc59b.eef911d0a7796d14
+ d027b38101e832ec.7564265259fd7282.8e7684b40a9d69a7.2255b916a4007195
+ f3e1ee7bedd91df4
+
+VPSRLW_0x05_128(reg)
+ before
+ bbeaac6b1f92b0dc.961e43d9be283a1e.36a5606f44d5caf0.4f8708de4bc535ac
+ d8bcef53d6b764fa.09fbc9bcc820c4ca.dd49e10d2412e67e.10d704de0c60e7d6
+ a4a3b49dadd276fa.058ac2183cdd8d1e.c69ca599974102d7.ac33f4a068793950
+ 7cebf5b740712287.6596a9d7366a5143.4deaa97d39ed59a8.ff6754107b1de847
+ e43fa01a6256afe7
+ after
+ 0000000000000000.0000000000000000.026f054b01cf02cd.07fb02a003d80742
+ d8bcef53d6b764fa.09fbc9bcc820c4ca.dd49e10d2412e67e.10d704de0c60e7d6
+ a4a3b49dadd276fa.058ac2183cdd8d1e.c69ca599974102d7.ac33f4a068793950
+ 7cebf5b740712287.6596a9d7366a5143.4deaa97d39ed59a8.ff6754107b1de847
+ e43fa01a6256afe7
+VPSRLW_0x05_128(mem)
+ before
+ 398755ab38324c5b.bde0b00b2c20a34e.07ecfae7d1d3cb68.ce7fe827a5a2289d
+ d90aedad1abd79d0.c1cde0070c6937fa.c65831332a25b8b7.a4a65e0277ecab61
+ 9f96e60e2301f271.e5ff82167cda1838.7da6caa75b6bd45c.2dad07794c581ea0
+ 69f5bcb86f0c756b.85c290a41aff82b4.0aa2422f83b1db84.c4dedffac071bc08
+ c586e3f06ec4c243
+ after
+ 398755ab38324c5b.bde0b00b2c20a34e.07ecfae7d1d3cb68.ce7fe827a5a2289d
+ d90aedad1abd79d0.c1cde0070c6937fa.c65831332a25b8b7.a4a65e0277ecab61
+ 9f96e60e2301f271.e5ff82167cda1838.7da6caa75b6bd45c.2dad07794c581ea0
+ 69f5bcb86f0c756b.85c290a41aff82b4.0aa2422f83b1db84.c4dedffac071bc08
+ c586e3f06ec4c243
+
+VPSLLW_0x05_128(reg)
+ before
+ 8bf10ec7f2dc6cfd.11f4e9991beabce9.fd62081d7f62b319.471814b7bc04885b
+ 746b5cebe945f5e3.755feb9c43a68419.a92be5ed4992e514.12d3bc2b226f980c
+ da3fc9c9ee8c9aa1.6f023dac024c8824.e669238014185450.45a1b677d2ffc7c4
+ 1bbb52cb9e3c97e2.dda85bb775e88638.0e67bf427b823e7a.be4c7e88e7bed0af
+ 57a191487ebb70f8
+ after
+ 0000000000000000.0000000000000000.cce0e8407040cf40.c980d100f7c015e0
+ 746b5cebe945f5e3.755feb9c43a68419.a92be5ed4992e514.12d3bc2b226f980c
+ da3fc9c9ee8c9aa1.6f023dac024c8824.e669238014185450.45a1b677d2ffc7c4
+ 1bbb52cb9e3c97e2.dda85bb775e88638.0e67bf427b823e7a.be4c7e88e7bed0af
+ 57a191487ebb70f8
+VPSLLW_0x05_128(mem)
+ before
+ ed6c6aa5b2ff63cb.9129f25e94e12853.991fc1a8b7873881.7e73b3a01a5bdd3e
+ 5d78858aa0986556.9ad6a5ef6d0788a0.8031ec6be4345a2b.92d7fd048e2f6e47
+ 81935fe2639131c2.900e67e9c43bf474.6fab56ed19fcaa61.a6e098dc738b2d42
+ 3687729b18f7843e.d11d34b73609a87b.40597d1871eae250.16da809364fa55da
+ 3d11b294fd0923bc
+ after
+ ed6c6aa5b2ff63cb.9129f25e94e12853.991fc1a8b7873881.7e73b3a01a5bdd3e
+ 5d78858aa0986556.9ad6a5ef6d0788a0.8031ec6be4345a2b.92d7fd048e2f6e47
+ 81935fe2639131c2.900e67e9c43bf474.6fab56ed19fcaa61.a6e098dc738b2d42
+ 3687729b18f7843e.d11d34b73609a87b.40597d1871eae250.16da809364fa55da
+ 3d11b294fd0923bc
+
+VPSLLW_0x05_128(reg)
+ before
+ 79d0294ddb42d394.59223ca0dad41af4.b74f09c75efbdf63.d007ddd9090abf23
+ 2565e1299934a00d.c42e38ddc537ae10.9fefe184d89fd6d6.fb81f01dfd68fc07
+ 9d1ad694d468c8d4.5478e23ef629fdc0.e64ab85a4181c980.9e9234cf67115727
+ 3d3c04fa276c8594.e5cbb7b089b8c32e.e6ad8ab5352bf40e.930823da66108ab0
+ b7ad3c2c137252ce
+ after
+ 0000000000000000.0000000000000000.d5a056a0a56081c0.61007b40c2005600
+ 2565e1299934a00d.c42e38ddc537ae10.9fefe184d89fd6d6.fb81f01dfd68fc07
+ 9d1ad694d468c8d4.5478e23ef629fdc0.e64ab85a4181c980.9e9234cf67115727
+ 3d3c04fa276c8594.e5cbb7b089b8c32e.e6ad8ab5352bf40e.930823da66108ab0
+ b7ad3c2c137252ce
+VPSLLW_0x05_128(mem)
+ before
+ e64ef8b08d426aac.601768c82fcb13fa.53f5311d99efbc86.fc6254014f2b922c
+ fcb7d452ed8c8f77.64f7fd688712b0b2.7ac0ce7242dba3f5.85b610ab2b0de085
+ d5b34dfe515d7d5a.a427bf47cccb9667.37fa099ca18735a7.dbf4bc1d665b1ac6
+ 4d10dea0d5c0f082.7cf5aad2998502c5.646d5f85d2ff2ec7.5b6a53c49ca37b9a
+ 6162d20d677140ae
+ after
+ e64ef8b08d426aac.601768c82fcb13fa.53f5311d99efbc86.fc6254014f2b922c
+ fcb7d452ed8c8f77.64f7fd688712b0b2.7ac0ce7242dba3f5.85b610ab2b0de085
+ d5b34dfe515d7d5a.a427bf47cccb9667.37fa099ca18735a7.dbf4bc1d665b1ac6
+ 4d10dea0d5c0f082.7cf5aad2998502c5.646d5f85d2ff2ec7.5b6a53c49ca37b9a
+ 6162d20d677140ae
+
+VPSLLW_0x05_128(reg)
+ before
+ 49293363664fa5ae.4098032494c1a31b.47abba738bc92f7a.dee64a1bef504a82
+ 6f0b743133cce645.8a193977ab6c5350.6396ec983d255a30.8131484917854403
+ 2f5490e56a713e20.075dfa8335cebc4e.2a023bac4b24bf93.2819d4fb64aad977
+ e55084eaa8cceaea.9331c4364ef39a40.fa3ba31b52539a50.b16c6a1df2cbc409
+ f7f4879bdef5c3e7
+ after
+ 0000000000000000.0000000000000000.476063604a604a00.2d8043a059608120
+ 6f0b743133cce645.8a193977ab6c5350.6396ec983d255a30.8131484917854403
+ 2f5490e56a713e20.075dfa8335cebc4e.2a023bac4b24bf93.2819d4fb64aad977
+ e55084eaa8cceaea.9331c4364ef39a40.fa3ba31b52539a50.b16c6a1df2cbc409
+ f7f4879bdef5c3e7
+VPSLLW_0x05_128(mem)
+ before
+ d67ea5614334903a.ed4b4aac88682650.0a60127a13e5a853.2d8d2151ee3d2713
+ 2ad6425b3d92e831.a390e097a6d12efe.48b8603da0b2a3b2.2143afbaba6ea187
+ cfc8d976ea1d86f6.636d4118a0943d9f.28032b6a1066468b.30ab4bc252734559
+ a020e79c63e127b5.892c69990f3c90e0.880feded7f0b4f07.b80ff0d553d74e35
+ 13bc9a605826fac6
+ after
+ d67ea5614334903a.ed4b4aac88682650.0a60127a13e5a853.2d8d2151ee3d2713
+ 2ad6425b3d92e831.a390e097a6d12efe.48b8603da0b2a3b2.2143afbaba6ea187
+ cfc8d976ea1d86f6.636d4118a0943d9f.28032b6a1066468b.30ab4bc252734559
+ a020e79c63e127b5.892c69990f3c90e0.880feded7f0b4f07.b80ff0d553d74e35
+ 13bc9a605826fac6
+
+VPUNPCKLQDQ_128(reg)
+ before
+ 9efe46cdfeed83b8.7baae6bbc6e8879b.711a54879156636c.43a624b20aaf7855
+ b621ee8ae0b725b9.3b3154bd2f4062d4.7783ff4fc26df1f0.35954ca5cc5e7e9f
+ b57090019b101e72.bc82ac90b9f5748b.f7b2645b3d0d7718.39a8dfb2e2221c11
+ f83927a0ca85a892.d96a6a1f801278ed.4cf581199ec2318f.2daa5ac5670910d8
+ ec693acb781f1420
+ after
+ 0000000000000000.0000000000000000.39a8dfb2e2221c11.35954ca5cc5e7e9f
+ b621ee8ae0b725b9.3b3154bd2f4062d4.7783ff4fc26df1f0.35954ca5cc5e7e9f
+ b57090019b101e72.bc82ac90b9f5748b.f7b2645b3d0d7718.39a8dfb2e2221c11
+ f83927a0ca85a892.d96a6a1f801278ed.4cf581199ec2318f.2daa5ac5670910d8
+ ec693acb781f1420
+VPUNPCKLQDQ_128(mem)
+ before
+ 51affaae306fe414.dbc6b0d20aa100c3.70b20a56a1a32b26.d49652f482195a01
+ 3a4a165cac053ee1.bb642503f6f061b1.5b29092138b44861.eae2d158859d301c
+ 81040bbf07eddcb3.f25f849f2bff090a.789ae26c5f528ccb.e925fcb142dbed8a
+ 04aa54c55d347bb5.dd03c81244593278.a1d011233588b38f.2fabce6b555ecdf7
+ 17c043f25bb20e10
+ after
+ 51affaae306fe414.dbc6b0d20aa100c3.70b20a56a1a32b26.d49652f482195a01
+ 3a4a165cac053ee1.bb642503f6f061b1.5b29092138b44861.eae2d158859d301c
+ 0000000000000000.0000000000000000.d49652f482195a01.eae2d158859d301c
+ 04aa54c55d347bb5.dd03c81244593278.a1d011233588b38f.2fabce6b555ecdf7
+ 17c043f25bb20e10
+
+VPUNPCKLQDQ_128(reg)
+ before
+ fcb057b2ef64ea81.9d076c59cbe5d613.d89cedc8dd8a19a7.b4991233d46279da
+ 3cc60717aefe9ef5.2ae9d2676d0cabfb.3f75f02d931ff944.8bbf628658ed9ad7
+ 314f4d8e330f6519.851affdb5eb6b497.6edccbae02a30ffb.040f7b09de34d1b3
+ 399727811b207d99.8b6870a1baeead13.c11b7cb5c5a39777.f955dba98144db9a
+ 475cfe515e2873b7
+ after
+ 0000000000000000.0000000000000000.040f7b09de34d1b3.8bbf628658ed9ad7
+ 3cc60717aefe9ef5.2ae9d2676d0cabfb.3f75f02d931ff944.8bbf628658ed9ad7
+ 314f4d8e330f6519.851affdb5eb6b497.6edccbae02a30ffb.040f7b09de34d1b3
+ 399727811b207d99.8b6870a1baeead13.c11b7cb5c5a39777.f955dba98144db9a
+ 475cfe515e2873b7
+VPUNPCKLQDQ_128(mem)
+ before
+ cbf25eec90ec5637.aeea905e01bf2020.199da2a59ec1549c.947ffeb078a9cd64
+ 5fe17968339c4046.ee94859082788a5a.098610d4263a635e.43544e09b843ec70
+ e0f7c9b06445ed0f.53e1018239d5f9f5.38ef36186c659784.2ae5662e21fd3145
+ 2afeccb03ff219be.3a1cffa2c264a79b.82a3915f8f4eab3b.a580448a4d62d88f
+ 0f6fe389dbfe1dfc
+ after
+ cbf25eec90ec5637.aeea905e01bf2020.199da2a59ec1549c.947ffeb078a9cd64
+ 5fe17968339c4046.ee94859082788a5a.098610d4263a635e.43544e09b843ec70
+ 0000000000000000.0000000000000000.947ffeb078a9cd64.43544e09b843ec70
+ 2afeccb03ff219be.3a1cffa2c264a79b.82a3915f8f4eab3b.a580448a4d62d88f
+ 0f6fe389dbfe1dfc
+
+VPUNPCKLQDQ_128(reg)
+ before
+ c6003f97645d3b35.1ac3fe54dfb07f80.00937d5bbab0d1f8.c4709b93a9025dae
+ 257d5420870c6fe9.8a11d989618adc81.ff907719bd46b2b9.d820d2a2d68c670a
+ 88331f90dd96f5c2.57b6db39e08cebed.9460e74966b1888a.9b80b17733f9867b
+ 4a6e9b540588086c.5d7c7f5178c26aef.1b4fcb55517e8d16.e95cb5fddb54752c
+ 9e805822eaa9f14a
+ after
+ 0000000000000000.0000000000000000.9b80b17733f9867b.d820d2a2d68c670a
+ 257d5420870c6fe9.8a11d989618adc81.ff907719bd46b2b9.d820d2a2d68c670a
+ 88331f90dd96f5c2.57b6db39e08cebed.9460e74966b1888a.9b80b17733f9867b
+ 4a6e9b540588086c.5d7c7f5178c26aef.1b4fcb55517e8d16.e95cb5fddb54752c
+ 9e805822eaa9f14a
+VPUNPCKLQDQ_128(mem)
+ before
+ 96b818d27e05b600.c979c4d6986de594.783141be463913b3.f1a81eaa1b37fe0a
+ adcf70f7b073807b.60a2968434d1c8e6.849f9d6b65fda366.70b9dcb55f6a1611
+ bf93dc7e9eff0ae7.6a330ec87541ec0d.5d931043f218d534.f5cc01e0baa312d8
+ a8ced85364b6116f.45792610f6488fb6.dfd9143408986649.dc2f8a99c86c2e0b
+ 812c724b2353a655
+ after
+ 96b818d27e05b600.c979c4d6986de594.783141be463913b3.f1a81eaa1b37fe0a
+ adcf70f7b073807b.60a2968434d1c8e6.849f9d6b65fda366.70b9dcb55f6a1611
+ 0000000000000000.0000000000000000.f1a81eaa1b37fe0a.70b9dcb55f6a1611
+ a8ced85364b6116f.45792610f6488fb6.dfd9143408986649.dc2f8a99c86c2e0b
+ 812c724b2353a655
+
+VPINSRD_128(reg)
+ before
+ 4010b5626ae4b563.444de1631da25140.4cc0dcc75472eb8d.e63c2729c48812d0
+ 75264f4936aa98e0.6fdc7298e5d28685.da542b592a4b3c3d.4e8ac50e41f595f5
+ 7cbc3d6f26318b79.054707e0d94f6b6b.4d8110321460c072.f38d68cf9ceaaae5
+ b11d793dd305c9da.e25a1c261527bd1e.ff9285beaf3db1da.b1128e58f0730ecc
+ 63e6b2955a9d7dd5
+ after
+ 0000000000000000.0000000000000000.da542b592a4b3c3d.4e8ac50e5a9d7dd5
+ 75264f4936aa98e0.6fdc7298e5d28685.da542b592a4b3c3d.4e8ac50e41f595f5
+ 7cbc3d6f26318b79.054707e0d94f6b6b.4d8110321460c072.f38d68cf9ceaaae5
+ b11d793dd305c9da.e25a1c261527bd1e.ff9285beaf3db1da.b1128e58f0730ecc
+ 63e6b2955a9d7dd5
+VPINSRD_128(mem)
+ before
+ e7d25073f573b32d.70940120dbb390ae.e2e02e55b46637c9.4ed58869966c4c1f
+ 18a5e4dcde016b00.156ed084dac61aa2.e0a6b75bd2169799.9494149f667bcced
+ d22aebbe30546279.fcf7e3d66bcba361.ba7835238c4597b9.2e1c25ccbbf56ff1
+ f02cdf03077754c5.817b34802b4c6998.4b222399fdfff456.79b9b85d2f676fd7
+ cfb7c7bc615c094a
+ after
+ e7d25073f573b32d.70940120dbb390ae.e2e02e55b46637c9.4ed58869966c4c1f
+ 18a5e4dcde016b00.156ed084dac61aa2.e0a6b75bd2169799.9494149f667bcced
+ 0000000000000000.0000000000000000.966c4c1fd2169799.9494149f667bcced
+ f02cdf03077754c5.817b34802b4c6998.4b222399fdfff456.79b9b85d2f676fd7
+ cfb7c7bc615c094a
+
+VPINSRD_128(reg)
+ before
+ 8d615057ea6078f7.50783e998077fc0f.ff46c1f0b5d8a6f2.6e70feaa424f699b
+ 0f054e996900f989.cddb836bb75e1784.d4a38590a5f8971d.012e40407641b4b5
+ b2edbeee77c7c8ad.421e2b65c73a6150.5bdf7cce983a77c2.df286748b6e18fd0
+ d0669ac2b242210f.8d10b073cc17969e.ef47a3152a298390.e329eeaf1d3cb617
+ ebfe515fc85de7b7
+ after
+ 0000000000000000.0000000000000000.d4a38590a5f8971d.012e4040c85de7b7
+ 0f054e996900f989.cddb836bb75e1784.d4a38590a5f8971d.012e40407641b4b5
+ b2edbeee77c7c8ad.421e2b65c73a6150.5bdf7cce983a77c2.df286748b6e18fd0
+ d0669ac2b242210f.8d10b073cc17969e.ef47a3152a298390.e329eeaf1d3cb617
+ ebfe515fc85de7b7
+VPINSRD_128(mem)
+ before
+ d1730d46d250dcdc.c6bce081b6fb3f5a.887c9081e3ff719a.ee25f4d1f552f731
+ 73549c4f572252b1.f03b8b971e805f3b.112d467b2701af72.b3c66d6e98400f51
+ ab6d7c6674de0463.aa2f9770875dbd5d.02f14f4eb5260c4f.99750958ad7f069d
+ 578928774591b01d.50e301788c1c946d.399225e4a97c4360.fe80c5fbd09b1ac1
+ 3d319bc49e218468
+ after
+ d1730d46d250dcdc.c6bce081b6fb3f5a.887c9081e3ff719a.ee25f4d1f552f731
+ 73549c4f572252b1.f03b8b971e805f3b.112d467b2701af72.b3c66d6e98400f51
+ 0000000000000000.0000000000000000.f552f7312701af72.b3c66d6e98400f51
+ 578928774591b01d.50e301788c1c946d.399225e4a97c4360.fe80c5fbd09b1ac1
+ 3d319bc49e218468
+
+VPINSRD_128(reg)
+ before
+ b1d6891db29d833f.51761d6ee545100c.3ea4c31cc94c2217.90dd462b1d0e11cf
+ b7b98a74a99951f2.76fed5377009e05b.d0bfdbc6db76a006.e59e2d0d30e832c9
+ ac279a331ea32b2c.a3eecebe03e6de37.627e44e45e284de7.12a05678fb176279
+ ea6bb6c8ad464d99.b21283efbaeac4cc.502dfbe0eded6365.f4b13d579ca65c0c
+ 689b5f952fa2ddad
+ after
+ 0000000000000000.0000000000000000.d0bfdbc6db76a006.e59e2d0d2fa2ddad
+ b7b98a74a99951f2.76fed5377009e05b.d0bfdbc6db76a006.e59e2d0d30e832c9
+ ac279a331ea32b2c.a3eecebe03e6de37.627e44e45e284de7.12a05678fb176279
+ ea6bb6c8ad464d99.b21283efbaeac4cc.502dfbe0eded6365.f4b13d579ca65c0c
+ 689b5f952fa2ddad
+VPINSRD_128(mem)
+ before
+ 482c3720cf16a189.cfd3d89ef40ff3e7.803670b7b0204f45.f61afa282451202d
+ 712e41e3990e63cc.b5aafe218c8958bf.ea26120001953acf.b0903f27a0e1bdeb
+ bf6ef9cba896e0a1.f93b23bd1340b9d0.caade3b8ca534395.dadac549fc28794a
+ 0eb7dbc218bbd435.f8d343de25c151c4.fd9961c9266924c4.d04588fad5b38ef7
+ ed1e84a6c60d399d
+ after
+ 482c3720cf16a189.cfd3d89ef40ff3e7.803670b7b0204f45.f61afa282451202d
+ 712e41e3990e63cc.b5aafe218c8958bf.ea26120001953acf.b0903f27a0e1bdeb
+ 0000000000000000.0000000000000000.2451202d01953acf.b0903f27a0e1bdeb
+ 0eb7dbc218bbd435.f8d343de25c151c4.fd9961c9266924c4.d04588fad5b38ef7
+ ed1e84a6c60d399d
+
+VMOVD_XMM_to_MEM32(reg)
+ before
+ 8fafb6b96cc2b6e9.3ad764b50689fbb3.0cbe5bf05d975d48.5fb4072132e09a88
+ 114419a0625e4087.20980f918e0a1048.9248665f574e1a07.cccb52ab09c6600c
+ ce2ba9c5456e1422.9ac85840cb4cd020.e6bd6098b073c1ae.20aabc53c826337d
+ 24ae6295b07d6e66.8531bbb0d95af766.65684505039191e8.371cc3058a0dcf06
+ edefe2ad6b86f0d4
+ after
+ 8fafb6b96cc2b6e9.3ad764b50689fbb3.0cbe5bf05d975d48.5fb4072132e09a88
+ 114419a0625e4087.20980f918e0a1048.9248665f574e1a07.cccb52ab09c6600c
+ ce2ba9c5456e1422.9ac85840cb4cd020.e6bd6098b073c1ae.20aabc53c826337d
+ 24ae6295b07d6e66.8531bbb0d95af766.65684505039191e8.371cc3058a0dcf06
+ edefe2ad6b86f0d4
+VMOVD_XMM_to_MEM32(mem)
+ before
+ 1eed9538899d5113.6e1b417d3f188a01.bda0b5cbd5414147.69971114ed35c462
+ a6e45890fd5fafee.07bc40e88fcaa39d.1ee1c17fda0c69ee.4f94c12f0ae997c8
+ 619ea8a2e5d7c692.4dde5d423c1ff6e6.84bf5bb705c72c88.73ac4fc4f43b45c5
+ 2be8005b5d11522a.9acd93f6e1a4bf89.cb08ff5f717f4541.312bb93e4ab70c06
+ e55dfb09a5e82636
+ after
+ 1eed9538899d5113.6e1b417d3f188a01.bda0b5cbd5414147.69971114f43b45c5
+ a6e45890fd5fafee.07bc40e88fcaa39d.1ee1c17fda0c69ee.4f94c12f0ae997c8
+ 619ea8a2e5d7c692.4dde5d423c1ff6e6.84bf5bb705c72c88.73ac4fc4f43b45c5
+ 2be8005b5d11522a.9acd93f6e1a4bf89.cb08ff5f717f4541.312bb93e4ab70c06
+ e55dfb09a5e82636
+
+VMOVD_XMM_to_MEM32(reg)
+ before
+ eb8d0f91a45ad002.e08ddca5801a0ee3.4cd4df721ae43932.ce8629633b3f7244
+ 9f09f342e0994516.5c5bb86e6afdb7e9.bd413b22846ba18c.6b0656af7e136dbe
+ 5d1ba288f732c21d.7b1d11a138c60867.4b5ea570bbc63344.7d5501305708f3da
+ 811018cf85b083c4.189e612a0582bf8a.507918c95a802b06.e03ca6d0e129bfc5
+ 708ac17c38828eab
+ after
+ eb8d0f91a45ad002.e08ddca5801a0ee3.4cd4df721ae43932.ce8629633b3f7244
+ 9f09f342e0994516.5c5bb86e6afdb7e9.bd413b22846ba18c.6b0656af7e136dbe
+ 5d1ba288f732c21d.7b1d11a138c60867.4b5ea570bbc63344.7d5501305708f3da
+ 811018cf85b083c4.189e612a0582bf8a.507918c95a802b06.e03ca6d0e129bfc5
+ 708ac17c38828eab
+VMOVD_XMM_to_MEM32(mem)
+ before
+ 080acf217a201cb7.6634518425a0c4b6.11ab26f5ee3c967d.2adc9099fd25c47d
+ 86874baac00e2515.6ad34a11748cc0a0.4110dbee0e004a6d.33d40a4d41423b55
+ c5ceb102285865f3.e839fee40d03b52d.8399fd0182db9686.c8ac814fc161cc3b
+ a0ac7d17ce0b977b.3cb169688c8edc0b.b512061a65d838f3.45b2f10d1a11b2db
+ 073056f2e7dc2ae1
+ after
+ 080acf217a201cb7.6634518425a0c4b6.11ab26f5ee3c967d.2adc9099c161cc3b
+ 86874baac00e2515.6ad34a11748cc0a0.4110dbee0e004a6d.33d40a4d41423b55
+ c5ceb102285865f3.e839fee40d03b52d.8399fd0182db9686.c8ac814fc161cc3b
+ a0ac7d17ce0b977b.3cb169688c8edc0b.b512061a65d838f3.45b2f10d1a11b2db
+ 073056f2e7dc2ae1
+
+VMOVD_XMM_to_MEM32(reg)
+ before
+ 6874ac69c54e70f8.f5eb2bd4cc3278d9.c28987088ebb74e3.b2467426d403e9e0
+ c5c8efe04ff3c0cc.9e57382541d9c33a.d50b5432af15b764.5502c20fea69687b
+ 7a791cc22258550b.79be1ff6470d35ca.d384cd518929e238.7c136cc3c41570ee
+ e3d32e7cd9086c5e.60ea5c33fad98ab4.1740edd1bb82310b.0143ef2d7d13bc65
+ c25fc5383270090d
+ after
+ 6874ac69c54e70f8.f5eb2bd4cc3278d9.c28987088ebb74e3.b2467426d403e9e0
+ c5c8efe04ff3c0cc.9e57382541d9c33a.d50b5432af15b764.5502c20fea69687b
+ 7a791cc22258550b.79be1ff6470d35ca.d384cd518929e238.7c136cc3c41570ee
+ e3d32e7cd9086c5e.60ea5c33fad98ab4.1740edd1bb82310b.0143ef2d7d13bc65
+ c25fc5383270090d
+VMOVD_XMM_to_MEM32(mem)
+ before
+ 99326cd2fe371212.5c212178108f4174.31a96bc9774a7e25.fc8bb01edfacdf8a
+ 648a5fe6fd75949f.42b1f223647a10f7.c6c5c9a2d96acd49.e0b012a591332961
+ fd311b604c354ce1.efcd9ce971541493.fd0bf0ac3d48324b.1dfd10d06ea44b3b
+ 41f51a2c0783f303.c0c21a37d2a98af6.b0475ed1beed6a57.11bca50c118a81c5
+ 163acdc6177206ab
+ after
+ 99326cd2fe371212.5c212178108f4174.31a96bc9774a7e25.fc8bb01e6ea44b3b
+ 648a5fe6fd75949f.42b1f223647a10f7.c6c5c9a2d96acd49.e0b012a591332961
+ fd311b604c354ce1.efcd9ce971541493.fd0bf0ac3d48324b.1dfd10d06ea44b3b
+ 41f51a2c0783f303.c0c21a37d2a98af6.b0475ed1beed6a57.11bca50c118a81c5
+ 163acdc6177206ab
+
+VPANDN_128(reg)
+ before
+ 8ac384691be71798.0da0da36496b4832.11dc6a772306adc9.bd458eff7967309b
+ c7a3c660b975f038.3bffd66b2efa059a.3d67881701f6bbbb.fed0fd2189c14140
+ 2b2590198ea9cc39.a8de8ab5d33be766.a2af6e820706ee76.50b525220b085975
+ 1097ddff360ee844.31087302533ba9c3.9b001a24d2c183a6.8fc184f01a463464
+ 98be9576d28a8e3a
+ after
+ 0000000000000000.0000000000000000.82001220d2010004.010100d012063424
+ c7a3c660b975f038.3bffd66b2efa059a.3d67881701f6bbbb.fed0fd2189c14140
+ 2b2590198ea9cc39.a8de8ab5d33be766.a2af6e820706ee76.50b525220b085975
+ 1097ddff360ee844.31087302533ba9c3.9b001a24d2c183a6.8fc184f01a463464
+ 98be9576d28a8e3a
+VPANDN_128(mem)
+ before
+ 4579d4a150dd2222.d343a97e4c308008.b04b0b3ccb0509dd.84a58769feb3b5f8
+ 73bdbe5bb04dad49.d176f0026d9cd02f.0271d05156a5c1df.b9ebb1bd2568c118
+ fe58cd910de5eada.647caef734dd1366.03473d2c11278ef5.961e958ce66de3b2
+ c2157f3083b29702.e9a1e0ca3d7f8658.8f99ceb917982b4c.768a2d42da4d5770
+ b77b774b9f955801
+ after
+ 4579d4a150dd2222.d343a97e4c308008.b04b0b3ccb0509dd.84a58769feb3b5f8
+ 73bdbe5bb04dad49.d176f0026d9cd02f.0271d05156a5c1df.b9ebb1bd2568c118
+ 0000000000000000.0000000000000000.b00a0b2c89000800.04040640da9334e0
+ c2157f3083b29702.e9a1e0ca3d7f8658.8f99ceb917982b4c.768a2d42da4d5770
+ b77b774b9f955801
+
+VPANDN_128(reg)
+ before
+ b43d6e14d1d0240f.9bbf50222fbf6eed.bc3181e5250f65b2.823300e485035510
+ c81b0e070b8af447.6523ba552d182cc6.39788db58718eb1f.b8e14e997675c86d
+ 51635492ea4f0754.fc0d3ab397ca8cba.bcc101a70026564c.0d6e34c407f9408e
+ aa5f3b2009ac97e3.3c494d2a8cdf4bf4.a259d7262cc6e0e5.5da82e51539b789f
+ 8459b82c76682dcd
+ after
+ 0000000000000000.0000000000000000.8201520228c600e0.45082040018a3092
+ c81b0e070b8af447.6523ba552d182cc6.39788db58718eb1f.b8e14e997675c86d
+ 51635492ea4f0754.fc0d3ab397ca8cba.bcc101a70026564c.0d6e34c407f9408e
+ aa5f3b2009ac97e3.3c494d2a8cdf4bf4.a259d7262cc6e0e5.5da82e51539b789f
+ 8459b82c76682dcd
+VPANDN_128(mem)
+ before
+ 5e4e4f428d6b1b44.2e5cbe1c042de1a0.01a26ea5266625a1.458c0d9da583c595
+ c7536e7db4b0fe30.3ba6dcf4785c2136.27e619108168d6ed.02a69e7a0aea4309
+ 9b3491cb064491bc.2b888e1301c79251.8adfcb57baf31903.35f38628f48594ec
+ b6bd34179f329114.5c50d2e53af9719f.065bfe66ec13ab10.3abfc21302e3f4eb
+ 6d554da7cd8da1b2
+ after
+ 5e4e4f428d6b1b44.2e5cbe1c042de1a0.01a26ea5266625a1.458c0d9da583c595
+ c7536e7db4b0fe30.3ba6dcf4785c2136.27e619108168d6ed.02a69e7a0aea4309
+ 0000000000000000.0000000000000000.000066a526062100.45080185a5018494
+ b6bd34179f329114.5c50d2e53af9719f.065bfe66ec13ab10.3abfc21302e3f4eb
+ 6d554da7cd8da1b2
+
+VPANDN_128(reg)
+ before
+ 2a022251f311d5ec.f4b9d34d9c86b965.2848a2d7bf7ffaca.7724302a33d2483f
+ cc13407b10facd46.30f5eb58184dc7db.edbdfc532de4697e.b806dc8dad3eacbd
+ b1d2a092bfd4c56b.483ef726309275a1.05fbdcc61fb4f968.a7cf7f7c736392b5
+ 348b3f039d2cf808.175e73a3006180e4.cd4e3c9d327ce734.1f4a93e4a34bb754
+ fc4296b05904d7c6
+ after
+ 0000000000000000.0000000000000000.0042008c12188600.0748036002411340
+ cc13407b10facd46.30f5eb58184dc7db.edbdfc532de4697e.b806dc8dad3eacbd
+ b1d2a092bfd4c56b.483ef726309275a1.05fbdcc61fb4f968.a7cf7f7c736392b5
+ 348b3f039d2cf808.175e73a3006180e4.cd4e3c9d327ce734.1f4a93e4a34bb754
+ fc4296b05904d7c6
+VPANDN_128(mem)
+ before
+ 198403cbb09aad37.b18c1a38458da3c8.7921dbb9a2c7a3d0.a2021a4202c76f8d
+ 54dd5623c418f6d1.84202c9f53840259.4955ac5535cf9c90.de6371232921cc20
+ 87170ca3b28a6ec3.089271a3649c5164.65c56163d2852451.debc3daa45173c98
+ 90fe9f3796fcd137.9b2fe6b01361cb98.a73c76d097f6fa3e.fe5a7a45f234f9a2
+ 9a8a255fcb043fea
+ after
+ 198403cbb09aad37.b18c1a38458da3c8.7921dbb9a2c7a3d0.a2021a4202c76f8d
+ 54dd5623c418f6d1.84202c9f53840259.4955ac5535cf9c90.de6371232921cc20
+ 0000000000000000.0000000000000000.302053a882002340.20000a4002c6238d
+ 90fe9f3796fcd137.9b2fe6b01361cb98.a73c76d097f6fa3e.fe5a7a45f234f9a2
+ 9a8a255fcb043fea
+
+VPSLLDQ_0x05_128(reg)
+ before
+ 0f9638646d144b1b.4a608dcb8a7bda5a.98438632fd60ad9f.ed876786a02dd984
+ b7cab1c073ef5ae2.9007514bad124657.5a1a4c95be233325.1172b17308377c4e
+ ef748ce07a22a5ea.3fc167a419cdd15b.3f003745f13998d7.f1c9ce82ec1ea0c9
+ 13dfc32e1d376be0.34584cc0eab93691.a24040ae322b1961.67583c9f67f00021
+ 51ea76b695b95981
+ after
+ 0000000000000000.0000000000000000.2b196167583c9f67.f000210000000000
+ b7cab1c073ef5ae2.9007514bad124657.5a1a4c95be233325.1172b17308377c4e
+ ef748ce07a22a5ea.3fc167a419cdd15b.3f003745f13998d7.f1c9ce82ec1ea0c9
+ 13dfc32e1d376be0.34584cc0eab93691.a24040ae322b1961.67583c9f67f00021
+ 51ea76b695b95981
+VPSLLDQ_0x05_128(mem)
+ before
+ 894df9b393846816.7f565417f8bce670.49997b8d3de13226.de28643c1e87f26e
+ ed4b3f827d5de60c.8f263a08a83d5345.5c5070f52d528146.5102a05c50d85fab
+ 57b1c60f6e50928e.9f9b716bc945ee0c.4749a7e6d717df1c.551bef7864ab9bc4
+ a44b0946826a26c8.0b01f5aef560f270.e74f9c4b563c07d5.48bf4dfef88be364
+ 843ab759a5047337
+ after
+ 894df9b393846816.7f565417f8bce670.49997b8d3de13226.de28643c1e87f26e
+ ed4b3f827d5de60c.8f263a08a83d5345.5c5070f52d528146.5102a05c50d85fab
+ 57b1c60f6e50928e.9f9b716bc945ee0c.4749a7e6d717df1c.551bef7864ab9bc4
+ a44b0946826a26c8.0b01f5aef560f270.e74f9c4b563c07d5.48bf4dfef88be364
+ 843ab759a5047337
+
+VPSLLDQ_0x05_128(reg)
+ before
+ 66d827f409a386eb.b0e58414d6b65fe8.2fa4c23ccb1a9c1e.192fcc10c6cdb69d
+ 4be49b3dc0f35929.584bb3638541f817.67cfd581e50028c2.b7b6b12144d7a89f
+ 8dac0e9f658028a0.76481321ac16af84.0ed029e9df9dd107.9eaec96aec659807
+ 897a7d8695d72ffa.e7aa1f3966413e59.82f1bae0567ed59a.aae490d7d9844303
+ b7238054283f65bc
+ after
+ 0000000000000000.0000000000000000.7ed59aaae490d7d9.8443030000000000
+ 4be49b3dc0f35929.584bb3638541f817.67cfd581e50028c2.b7b6b12144d7a89f
+ 8dac0e9f658028a0.76481321ac16af84.0ed029e9df9dd107.9eaec96aec659807
+ 897a7d8695d72ffa.e7aa1f3966413e59.82f1bae0567ed59a.aae490d7d9844303
+ b7238054283f65bc
+VPSLLDQ_0x05_128(mem)
+ before
+ a23917cdf4a2ba61.9c9be25feb83a9e4.873b5396d0ce62c2.1e7f85d2e52d6e26
+ 45f1d02f59b9fd1c.205b3b940310d309.32c82b2605cad6ed.3ec6842b2939d858
+ 7d1627647491eb19.720583927a0be916.c41d24d422415704.3d12b557bd2b51db
+ 2675985a60364086.eee7b6c6ebff26b6.1905b98c423da133.79ae13c33e91135d
+ 4de89ad947f65b87
+ after
+ a23917cdf4a2ba61.9c9be25feb83a9e4.873b5396d0ce62c2.1e7f85d2e52d6e26
+ 45f1d02f59b9fd1c.205b3b940310d309.32c82b2605cad6ed.3ec6842b2939d858
+ 7d1627647491eb19.720583927a0be916.c41d24d422415704.3d12b557bd2b51db
+ 2675985a60364086.eee7b6c6ebff26b6.1905b98c423da133.79ae13c33e91135d
+ 4de89ad947f65b87
+
+VPSLLDQ_0x05_128(reg)
+ before
+ 140a470774e76408.1cdaa0fc3ab2b88c.f04bd09af378c796.0d4e653a82cc70a7
+ 2c6115b762ef6b8a.3b11ba351d130e5a.d47fce7c2d030862.7cc2a7cbfdf97f8b
+ f0390057ad9aacb9.5fe562f32664ff1a.f6cdabd7362b25c5.422ff829cfd18b0d
+ bbde0452f0756342.6424142171b246f8.b3826317aa7d596c.3b5fd641155f5056
+ 431fbb00ebaf8a95
+ after
+ 0000000000000000.0000000000000000.7d596c3b5fd64115.5f50560000000000
+ 2c6115b762ef6b8a.3b11ba351d130e5a.d47fce7c2d030862.7cc2a7cbfdf97f8b
+ f0390057ad9aacb9.5fe562f32664ff1a.f6cdabd7362b25c5.422ff829cfd18b0d
+ bbde0452f0756342.6424142171b246f8.b3826317aa7d596c.3b5fd641155f5056
+ 431fbb00ebaf8a95
+VPSLLDQ_0x05_128(mem)
+ before
+ 363a26516ccef4f4.eb9c1d14c70accd1.25984cab1808a121.65e9f2a72383e102
+ f07e901fb4c74b9f.dabf4809cfe82211.800f877d3972cac1.695054f63fcbf934
+ 4db67658e0a64ac3.e5927f9da498a2af.50534084f0fd7e04.1a01866d9ae1ddae
+ 28ad55e70c78af8c.6962c03de1a88756.7130f3aa58b47815.d64a8379cf50c81b
+ f87547867ba4f728
+ after
+ 363a26516ccef4f4.eb9c1d14c70accd1.25984cab1808a121.65e9f2a72383e102
+ f07e901fb4c74b9f.dabf4809cfe82211.800f877d3972cac1.695054f63fcbf934
+ 4db67658e0a64ac3.e5927f9da498a2af.50534084f0fd7e04.1a01866d9ae1ddae
+ 28ad55e70c78af8c.6962c03de1a88756.7130f3aa58b47815.d64a8379cf50c81b
+ f87547867ba4f728
+
+VPSRLDQ_0x05_128(reg)
+ before
+ dccfcf013969a680.5f30a8b852483426.c07b075322a40eb3.bf741cdd8ea37520
+ dea41554a52c10d0.cd0bebb7d12296bb.48294e4c04167472.15ea3807add73152
+ 5a3f17ed5d7872c3.4e0a9ad0a213907a.5bb89395228cf23e.515dc116d15b68d7
+ abeed036fada0807.bdf932f0e426df8d.5673d1991992c7c4.4e9a35f4173bd6da
+ e76e108f9b843688
+ after
+ 0000000000000000.0000000000000000.00000000005673d1.991992c7c44e9a35
+ dea41554a52c10d0.cd0bebb7d12296bb.48294e4c04167472.15ea3807add73152
+ 5a3f17ed5d7872c3.4e0a9ad0a213907a.5bb89395228cf23e.515dc116d15b68d7
+ abeed036fada0807.bdf932f0e426df8d.5673d1991992c7c4.4e9a35f4173bd6da
+ e76e108f9b843688
+VPSRLDQ_0x05_128(mem)
+ before
+ faa3ccd27841440d.2ffb3c9d1add0d45.f8a32e01b0673f21.95a804c384b22db0
+ 6205e7a9ca7fbe94.41b3588d580dbf2c.d9d50af025e36c61.75a12881007a61ad
+ fa62db00ae485e49.3d621e7251f65865.3e5c42aa5ca5227a.50ab3a3e28769e67
+ a08426c43fabe15a.7e548cb8a125149f.0102521a73ba1c98.831235669830228c
+ 6a221465ed3627c5
+ after
+ faa3ccd27841440d.2ffb3c9d1add0d45.f8a32e01b0673f21.95a804c384b22db0
+ 6205e7a9ca7fbe94.41b3588d580dbf2c.d9d50af025e36c61.75a12881007a61ad
+ fa62db00ae485e49.3d621e7251f65865.3e5c42aa5ca5227a.50ab3a3e28769e67
+ a08426c43fabe15a.7e548cb8a125149f.0102521a73ba1c98.831235669830228c
+ 6a221465ed3627c5
+
+VPSRLDQ_0x05_128(reg)
+ before
+ 6127d6a7c314eac1.2e3944df9ab103f1.62d59dcbe2263184.0094b72b862c17e6
+ c46c7499b555a62a.814baf3edb687f3a.43314e17b383e9c1.15ddeccbb00ace90
+ ef3feca5608598ac.7687e5ce1cdb1362.7fb39909adca7901.1eab6de50e5dfec4
+ 3eea39395f30fcf5.e7b961797c167995.70a87c0b6f861cf1.f5c8b665bb3363ab
+ 78024437d397b974
+ after
+ 0000000000000000.0000000000000000.000000000070a87c.0b6f861cf1f5c8b6
+ c46c7499b555a62a.814baf3edb687f3a.43314e17b383e9c1.15ddeccbb00ace90
+ ef3feca5608598ac.7687e5ce1cdb1362.7fb39909adca7901.1eab6de50e5dfec4
+ 3eea39395f30fcf5.e7b961797c167995.70a87c0b6f861cf1.f5c8b665bb3363ab
+ 78024437d397b974
+VPSRLDQ_0x05_128(mem)
+ before
+ 812392487395bc49.0dba57bf4ee30eae.b2ad9f2d14266dfe.745df28b9244103c
+ edf81c82b63a2757.b8fb42a5ca290986.b12e1bd50216acca.e51cf7f3b58f8f90
+ 984d5ed2b991b7c9.9bf9f7566e8f2a27.c109525d62f3f224.213187b171f3d596
+ 5fedd42598a727cc.12ff703dd79fad3d.be0bbfb14fc8fb39.82ea9f3064fd20fc
+ 66913adc2a38aa6e
+ after
+ 812392487395bc49.0dba57bf4ee30eae.b2ad9f2d14266dfe.745df28b9244103c
+ edf81c82b63a2757.b8fb42a5ca290986.b12e1bd50216acca.e51cf7f3b58f8f90
+ 984d5ed2b991b7c9.9bf9f7566e8f2a27.c109525d62f3f224.213187b171f3d596
+ 5fedd42598a727cc.12ff703dd79fad3d.be0bbfb14fc8fb39.82ea9f3064fd20fc
+ 66913adc2a38aa6e
+
+VPSRLDQ_0x05_128(reg)
+ before
+ 277454215e30b098.1ca6fb656d87358b.795babc8a0e7ce75.85fedebde6a18335
+ 22dde96b9c726d25.ac424e80573d9b33.2b57a36266f3c87b.f0af2b6d428a4543
+ b319f62681891fc1.eb8e49616fd615f0.86405578c44ed8fa.dce923ad7f90fe90
+ 377475bea901001a.b55668f4d45c61ed.e562bb7457843a9f.257a4069babf6947
+ a72d008e0f214495
+ after
+ 0000000000000000.0000000000000000.0000000000e562bb.7457843a9f257a40
+ 22dde96b9c726d25.ac424e80573d9b33.2b57a36266f3c87b.f0af2b6d428a4543
+ b319f62681891fc1.eb8e49616fd615f0.86405578c44ed8fa.dce923ad7f90fe90
+ 377475bea901001a.b55668f4d45c61ed.e562bb7457843a9f.257a4069babf6947
+ a72d008e0f214495
+VPSRLDQ_0x05_128(mem)
+ before
+ 3ecdde0699c449a6.083a64a0af674dda.e66628259fde3957.a409d3c3ba222916
+ c62757bf74b335a5.83b6bf362f4641ad.5a8a03e0ee655a59.1e8098d18ab2e20a
+ 1b07e5a4bdfbc3bf.043680eec62a1940.ed8e7711ddff8020.b115070b62c3a128
+ 193906a08fa7b01f.e704a4320fa0113f.7b3d00a487b866d8.b8121adcdfdea11b
+ 8ec4cfaf9c912090
+ after
+ 3ecdde0699c449a6.083a64a0af674dda.e66628259fde3957.a409d3c3ba222916
+ c62757bf74b335a5.83b6bf362f4641ad.5a8a03e0ee655a59.1e8098d18ab2e20a
+ 1b07e5a4bdfbc3bf.043680eec62a1940.ed8e7711ddff8020.b115070b62c3a128
+ 193906a08fa7b01f.e704a4320fa0113f.7b3d00a487b866d8.b8121adcdfdea11b
+ 8ec4cfaf9c912090
+
+VPSUBUSB_128(reg)
+ before
+ 917721f235675832.9c8835a107c3b8f2.886d2870a7336555.e0641886099ac9ac
+ 1b770c1047ed85af.80c2ee92405c9764.43bd0713296f502f.f8cf3da17eb365c9
+ 8a108c756eaee5b0.a1b1ae5f577d08a0.74403e8732e10f78.9f4ae9e3020ef55a
+ 388d9e8d4536b2e4.db23eff56732c8d3.7741c7385d14dedd.b1a19a36b2b8378c
+ 0aa0cc88aabce58b
+ after
+ 0000000000000000.0000000000000000.007c0000005b0000.472e006b00002e3d
+ 1b770c1047ed85af.80c2ee92405c9764.43bd0713296f502f.f8cf3da17eb365c9
+ 8a108c756eaee5b0.a1b1ae5f577d08a0.74403e8732e10f78.9f4ae9e3020ef55a
+ 388d9e8d4536b2e4.db23eff56732c8d3.7741c7385d14dedd.b1a19a36b2b8378c
+ 0aa0cc88aabce58b
+VPSUBUSB_128(mem)
+ before
+ 8612f9c40426bb82.833c3dc4681229f4.0ae22f3e8d889328.a80ea0924795f80a
+ 00c49fd6df03779d.c567658674cd858f.09bbe927e48a25cc.63f1c4018bef9baa
+ 568339aa555ed30a.5b5b124004f3045f.b679999d894439eb.04372ff1c6ae0169
+ 6319432c82438cf3.a264405cb511e011.eceabc8a97c38cb0.e72cddcf935e66f5
+ 681ccb058e8c08f8
+ after
+ 8612f9c40426bb82.833c3dc4681229f4.0ae22f3e8d889328.a80ea0924795f80a
+ 00c49fd6df03779d.c567658674cd858f.09bbe927e48a25cc.63f1c4018bef9baa
+ 0000000000000000.0000000000000000.0000ba00570200a4.00e32400445a00a0
+ 6319432c82438cf3.a264405cb511e011.eceabc8a97c38cb0.e72cddcf935e66f5
+ 681ccb058e8c08f8
+
+VPSUBUSB_128(reg)
+ before
+ e353f40154c3211e.0352394883bf5d84.f4ceec4822b25550.87d8cddc2a12da48
+ b31c542e8190ee14.11fc98ea73dd03ea.aee4116ee862a1c9.6211487e5f3ddede
+ 36c5e7f7b07eaa86.6be2dbff6faa3a51.2df4ab3ca2aefe27.5b5fa95b5251559f
+ c798a9ca7d199220.ebcf7e719230bee4.cb48b61ded21a917.4d8f6c611e59fbb6
+ 136c0e7bdf618c50
+ after
+ 0000000000000000.0000000000000000.009c0051004100b2.1500001d41000028
+ b31c542e8190ee14.11fc98ea73dd03ea.aee4116ee862a1c9.6211487e5f3ddede
+ 36c5e7f7b07eaa86.6be2dbff6faa3a51.2df4ab3ca2aefe27.5b5fa95b5251559f
+ c798a9ca7d199220.ebcf7e719230bee4.cb48b61ded21a917.4d8f6c611e59fbb6
+ 136c0e7bdf618c50
+VPSUBUSB_128(mem)
+ before
+ 8bc40a95b276c399.c1e2971285ede28c.6f90fd2ef87d4bd0.e52d2f7d6447de45
+ 8f61dc9cb2a35dbc.82efac3b6487d679.d2f1d420bf9d9c41.d7ef11c8a4add85c
+ fd11007afcf516e6.650ae4b1b472a991.efbe8035009b6e62.fdda586a48ded409
+ af9ef31cab76a943.c5813be1143b9981.a3c37c58d9837c5f.b33a00cfec660ef7
+ 555a05642dd2c1d3
+ after
+ 8bc40a95b276c399.c1e2971285ede28c.6f90fd2ef87d4bd0.e52d2f7d6447de45
+ 8f61dc9cb2a35dbc.82efac3b6487d679.d2f1d420bf9d9c41.d7ef11c8a4add85c
+ 0000000000000000.0000000000000000.6361000000205100.00c2004b40660017
+ af9ef31cab76a943.c5813be1143b9981.a3c37c58d9837c5f.b33a00cfec660ef7
+ 555a05642dd2c1d3
+
+VPSUBUSB_128(reg)
+ before
+ 3f876493a7ad2b49.82d52f6fdc35d3fe.009eae351d6ddff4.cbcc447566618366
+ cd0e18c9f5848504.5382325daa3b5044.70af371a6e94ba97.41a45478c2423fa1
+ 5b391d73b3e10eb1.fc7177d43296dc40.73fed4fda03d6415.e318294d09316c3c
+ 45556ffc7e5200fb.5a6d7bbf8f51321f.63d8814952f31a1c.8bf43ee0583bc664
+ 16040f1eca6a0845
+ after
+ 0000000000000000.0000000000000000.0d0000001c00a07b.000016006a07003d
+ cd0e18c9f5848504.5382325daa3b5044.70af371a6e94ba97.41a45478c2423fa1
+ 5b391d73b3e10eb1.fc7177d43296dc40.73fed4fda03d6415.e318294d09316c3c
+ 45556ffc7e5200fb.5a6d7bbf8f51321f.63d8814952f31a1c.8bf43ee0583bc664
+ 16040f1eca6a0845
+VPSUBUSB_128(mem)
+ before
+ 611418f17ccdef0a.e7ad0bcff263998f.4a44b80ade780f0c.9e8938691d421855
+ 46f0d5468a6d36e0.9d8feb5aaa9f1219.a6c0aca13a182f34.7e5cf7cb9fb7996e
+ a263c30a0e589bf2.c3450d084292aa44.4baed270bf3d4dc3.609fb8da74dddb13
+ 513b5d282799d86d.b51d6d4557c89bbd.15daa6638af126e4.a19c7a02374018f0
+ 9ba036af846d8cb0
+ after
+ 611418f17ccdef0a.e7ad0bcff263998f.4a44b80ade780f0c.9e8938691d421855
+ 46f0d5468a6d36e0.9d8feb5aaa9f1219.a6c0aca13a182f34.7e5cf7cb9fb7996e
+ 0000000000000000.0000000000000000.5c7c009700002028.0000bf6282758119
+ 513b5d282799d86d.b51d6d4557c89bbd.15daa6638af126e4.a19c7a02374018f0
+ 9ba036af846d8cb0
+
+VPSUBSB_128(reg)
+ before
+ abf7e94df8ef74ff.2f421f8cef3da97d.cf61057d84ce222f.e110a566b74276c4
+ 2ded90492f520c8b.18458521824fcc4d.6c5ed31d662f7b47.891b4a65613bf98e
+ 7ece260dc42390fe.e8100cd5fcdbfb0a.ea5fd18f9878e1b0.eac9114da4e96a6f
+ f8e5a70653ed3c04.7c6e2e937bedf3df.a4b2fd40b6349118.e0e476089d578693
+ 4739f58468910925
+ after
+ 0000000000000000.0000000000000000.7f7fd6dd7ffb7f2f.a937d45d7fe473fb
+ 2ded90492f520c8b.18458521824fcc4d.6c5ed31d662f7b47.891b4a65613bf98e
+ 7ece260dc42390fe.e8100cd5fcdbfb0a.ea5fd18f9878e1b0.eac9114da4e96a6f
+ f8e5a70653ed3c04.7c6e2e937bedf3df.a4b2fd40b6349118.e0e476089d578693
+ 4739f58468910925
+VPSUBSB_128(mem)
+ before
+ fb940bac20a3af52.f88010a1793c4b4a.ae2d6948189270f9.f5a2539d5eefc728
+ d8c1326ce19a3345.dae95b49d19dfa7c.5b1738def1d62d84.3b7acd102936bf8f
+ ba8ce8afc882522b.fa6d8669f89b8445.5efa184222c3e7ab.d1876907b593b4f6
+ 7dc0a963f065c730.b4588c6f89c22752.95a08361c6675a9b.121522ed9e95e30c
+ 5c70f42e7fc5887b
+ after
+ fb940bac20a3af52.f88010a1793c4b4a.ae2d6948189270f9.f5a2539d5eefc728
+ d8c1326ce19a3345.dae95b49d19dfa7c.5b1738def1d62d84.3b7acd102936bf8f
+ 0000000000000000.0000000000000000.7feacf96d944bd8b.467f8073cb47f880
+ 7dc0a963f065c730.b4588c6f89c22752.95a08361c6675a9b.121522ed9e95e30c
+ 5c70f42e7fc5887b
+
+VPSUBSB_128(reg)
+ before
+ 09e4db36f4b1def0.fd2aef737651507f.64f669c6219f1d4e.dbd6f725f9ce417f
+ 77bcd4719ae52216.159738cc7552a745.66921ada5bbda3e6.0c68ef7cd8025a84
+ 0045da4b0deb909a.a3d1fe58097289ad.167a9917d4a9f4c5.0421e8517f115fd6
+ 01cce930e7516427.82a5c00450bfb1e4.d0f8e4ea27ed4d99.9fcf5c8f09070ca0
+ b93cc92492ee1f0f
+ after
+ 0000000000000000.0000000000000000.7f9a36f034d0804d.6d7f937fcffb4ee4
+ 77bcd4719ae52216.159738cc7552a745.66921ada5bbda3e6.0c68ef7cd8025a84
+ 0045da4b0deb909a.a3d1fe58097289ad.167a9917d4a9f4c5.0421e8517f115fd6
+ 01cce930e7516427.82a5c00450bfb1e4.d0f8e4ea27ed4d99.9fcf5c8f09070ca0
+ b93cc92492ee1f0f
+VPSUBSB_128(mem)
+ before
+ 2d35aafb37d4524e.d79bfd8dc7a2d96a.8edef7bd6345dc15.f059f6bdf118ea0b
+ d9867b0013c5628a.dcff12cc476b2c0f.a34a206d600ec66e.d2e9ccfdcdb307ca
+ 98fbb82043cb0aee.6d43255b033799c1.9cb3b80263282b18.d2f46017574cdf80
+ 4560de45e2f407a8.e7b531a498925b2d.57e73a67879fc742.4bc6b0752c6eafd9
+ 9baab785e8a6b382
+ after
+ 2d35aafb37d4524e.d79bfd8dc7a2d96a.8edef7bd6345dc15.f059f6bdf118ea0b
+ d9867b0013c5628a.dcff12cc476b2c0f.a34a206d600ec66e.d2e9ccfdcdb307ca
+ 0000000000000000.0000000000000000.156c297ffdc9ea59.e290d640dc9b1dbf
+ 4560de45e2f407a8.e7b531a498925b2d.57e73a67879fc742.4bc6b0752c6eafd9
+ 9baab785e8a6b382
+
+VPSUBSB_128(reg)
+ before
+ 1dee71b2267e2727.be80675c0d4c15e1.a49f3215a109afff.aeb02287e87d5516
+ 2ddcdb6882854673.de29d152dfddf0c8.014f2419ba27d1e2.7fdbed50a3d191c0
+ 26c1ef1399444d13.8025981175b65486.5a0f041c8179fd82.a53315add4a4396d
+ 66e9ab1f064978b3.82413687eae0fc4a.0c2ccd8a8f896e8c.fb86188b96040749
+ 5f9f71d405fcb87f
+ after
+ 0000000000000000.0000000000000000.f523577f2b7f8056.7f55d57f0dcd8a80
+ 2ddcdb6882854673.de29d152dfddf0c8.014f2419ba27d1e2.7fdbed50a3d191c0
+ 26c1ef1399444d13.8025981175b65486.5a0f041c8179fd82.a53315add4a4396d
+ 66e9ab1f064978b3.82413687eae0fc4a.0c2ccd8a8f896e8c.fb86188b96040749
+ 5f9f71d405fcb87f
+VPSUBSB_128(mem)
+ before
+ ab499c753e98083c.47a00af8661f02fe.be49299f5a69a53e.71f27bcf82e561ac
+ bd51165a5ce5b2ac.2731090a555328a1.1208ec44e25c0a8f.e6ac0a57f619128e
+ 6f835a707cee74fa.61eaa2c16d702647.584cfb649ec5e868.c7a8768e86afbddd
+ 9eabe4a2b9c00852.5015d38a4d02389d.6ddfd2eaa9b1fbf6.7030bce1ce369d45
+ 3d91d7ba6b37ef73
+ after
+ ab499c753e98083c.47a00af8661f02fe.be49299f5a69a53e.71f27bcf82e561ac
+ bd51165a5ce5b2ac.2731090a555328a1.1208ec44e25c0a8f.e6ac0a57f619128e
+ 0000000000000000.0000000000000000.54bfc37f88f36580.80ba8f7f7434b1e2
+ 9eabe4a2b9c00852.5015d38a4d02389d.6ddfd2eaa9b1fbf6.7030bce1ce369d45
+ 3d91d7ba6b37ef73
+
+VPSLLD_0x05_128(reg)
+ before
+ 8a17c387f940ee13.279530db30652ae1.52ff97cf8e96994e.2e8feec31f2bff64
+ b30e7cb213dcd8d1.e40cba09fcec97d3.c1f4eafeceb78607.7526c9d91d40b0df
+ 14c2ffa95597e758.b2deff17395e0b54.fa40c982a9f13b74.1f71e119bffbc993
+ 087f47d75cfe5854.6ed57af105c9428f.5a2f2ec6bad1f340.093cb270206807ab
+ 0d52b6c85c932554
+ after
+ 0000000000000000.0000000000000000.45e5d8c05a3e6800.27964e000d00f560
+ b30e7cb213dcd8d1.e40cba09fcec97d3.c1f4eafeceb78607.7526c9d91d40b0df
+ 14c2ffa95597e758.b2deff17395e0b54.fa40c982a9f13b74.1f71e119bffbc993
+ 087f47d75cfe5854.6ed57af105c9428f.5a2f2ec6bad1f340.093cb270206807ab
+ 0d52b6c85c932554
+VPSLLD_0x05_128(mem)
+ before
+ 08816b0f9089e1b9.ed904fa8c39c6672.f2bea7837938f8b0.3b0c17389ee2eb18
+ d6934c2fd755f508.1e42168827fe4e5e.1b6502b9b3b8e8e5.fa247f43f0b05fa8
+ 5355d5164e041d6a.f7e195e323af4cc3.c596077fcf54cf57.f4c462534cc88b9b
+ 5b9382af10a1170d.d4b9ca25543b9c4e.cc1c33c2e8186835.8336bdd54fb5aa9d
+ 04c68b339503f95c
+ after
+ 08816b0f9089e1b9.ed904fa8c39c6672.f2bea7837938f8b0.3b0c17389ee2eb18
+ d6934c2fd755f508.1e42168827fe4e5e.1b6502b9b3b8e8e5.fa247f43f0b05fa8
+ 5355d5164e041d6a.f7e195e323af4cc3.c596077fcf54cf57.f4c462534cc88b9b
+ 5b9382af10a1170d.d4b9ca25543b9c4e.cc1c33c2e8186835.8336bdd54fb5aa9d
+ 04c68b339503f95c
+
+VPSLLD_0x05_128(reg)
+ before
+ d3c2c8dab93fb481.cb19cfe63a389d1d.1016afbb552e79ab.0cc5016c1a1071a9
+ 4d75703757f416bb.7db339a7e7d66cc6.0944430fc3152185.615bed6a8249a4e0
+ cc2a7fb40cae5db4.4e2d3bde33864033.1a8e7f8f397bcd89.a7ab73a93bcfbe05
+ ad2ef2bf73fac319.1a5251773b54d490.9e4260a554edbc62.ba81101462ac7a44
+ 76a93f9713ee95cb
+ after
+ 0000000000000000.0000000000000000.c84c14a09db78c40.50220280558f4880
+ 4d75703757f416bb.7db339a7e7d66cc6.0944430fc3152185.615bed6a8249a4e0
+ cc2a7fb40cae5db4.4e2d3bde33864033.1a8e7f8f397bcd89.a7ab73a93bcfbe05
+ ad2ef2bf73fac319.1a5251773b54d490.9e4260a554edbc62.ba81101462ac7a44
+ 76a93f9713ee95cb
+VPSLLD_0x05_128(mem)
+ before
+ b7ef7c1d68a0cbc4.4ccdc4c329638495.bdeff85f1b4ce50a.f3aae3bfaff628bd
+ 591e439480cfd85b.0553f12cc975ded5.12d0aa80ee7b2fcd.73130348e6224e45
+ 380310e8748677be.340c7565f0bd0b84.f7c1e5c8d0ed6d04.7cc9bcac96fe6aa8
+ 306b600362d16516.35444cdd39c6474f.478e2421deac5ddc.68170a575b15b78f
+ 954beab5d0f372a8
+ after
+ b7ef7c1d68a0cbc4.4ccdc4c329638495.bdeff85f1b4ce50a.f3aae3bfaff628bd
+ 591e439480cfd85b.0553f12cc975ded5.12d0aa80ee7b2fcd.73130348e6224e45
+ 380310e8748677be.340c7565f0bd0b84.f7c1e5c8d0ed6d04.7cc9bcac96fe6aa8
+ 306b600362d16516.35444cdd39c6474f.478e2421deac5ddc.68170a575b15b78f
+ 954beab5d0f372a8
+
+VPSLLD_0x05_128(reg)
+ before
+ 5daf57329125d79f.1d20aed266bd5e92.644673fd411dd0e1.de03e37934c6b981
+ 1e904d3a3b362220.dbef76419b551e5c.1d60e532a34ce0e8.98eb9fbbed473d1e
+ 323bc83969b28ed6.45a3343d1ea560a0.bcdc9ee8fce2b40d.5113d3d32539a7e0
+ f6f9c59cb825586e.390a65b00abae18b.9d079a8ce76888ff.e448faadf9aab1f2
+ 2f54933584a61881
+ after
+ 0000000000000000.0000000000000000.a0f35180ed111fe0.891f55a035563e40
+ 1e904d3a3b362220.dbef76419b551e5c.1d60e532a34ce0e8.98eb9fbbed473d1e
+ 323bc83969b28ed6.45a3343d1ea560a0.bcdc9ee8fce2b40d.5113d3d32539a7e0
+ f6f9c59cb825586e.390a65b00abae18b.9d079a8ce76888ff.e448faadf9aab1f2
+ 2f54933584a61881
+VPSLLD_0x05_128(mem)
+ before
+ 0d031757e33797b9.c7193ecdc31cbc93.92ee84887b9f5d49.1b2cd688006c9768
+ 592304ff316bebc5.ffe6313a2723f5f2.2b1d0cb08e608f05.94994d4ae4791ef4
+ f17fd41a8b4ed0d1.fbab994e7fc54136.e2617c145f0a34ec.6399fb3c2f1c5950
+ b0e205920ceb020b.17b67375688eda0c.92874da009a8082a.e477dccc7cdf8428
+ 7280ec656751da27
+ after
+ 0d031757e33797b9.c7193ecdc31cbc93.92ee84887b9f5d49.1b2cd688006c9768
+ 592304ff316bebc5.ffe6313a2723f5f2.2b1d0cb08e608f05.94994d4ae4791ef4
+ f17fd41a8b4ed0d1.fbab994e7fc54136.e2617c145f0a34ec.6399fb3c2f1c5950
+ b0e205920ceb020b.17b67375688eda0c.92874da009a8082a.e477dccc7cdf8428
+ 7280ec656751da27
+
+VPSRLD_0x05_128(reg)
+ before
+ 6b0028738dfb98fa.71191355d14e3d9d.b051b91b7d0afc20.165afd40a847c7ea
+ 2a438b62896bfa4d.12f0784df5833cb3.20c969ac5bc6e41d.4ca807e059f12c59
+ 0a95119ef82c3bcb.6d33b2689597bc7a.c4697e949d4dcfb0.0e3ce76c38b4f4a2
+ 6942b69376cb9821.60ae3c91cc95781e.f87ff43fdf2bf684.3ae119d05f9cdbf2
+ aa6419f9edb49c74
+ after
+ 0000000000000000.0000000000000000.07c3ffa106f95fb4.01d708ce02fce6df
+ 2a438b62896bfa4d.12f0784df5833cb3.20c969ac5bc6e41d.4ca807e059f12c59
+ 0a95119ef82c3bcb.6d33b2689597bc7a.c4697e949d4dcfb0.0e3ce76c38b4f4a2
+ 6942b69376cb9821.60ae3c91cc95781e.f87ff43fdf2bf684.3ae119d05f9cdbf2
+ aa6419f9edb49c74
+VPSRLD_0x05_128(mem)
+ before
+ 3c9164d1fb08f455.a19577ae9dd34dfa.c52d92b4b6892dca.1856c719beed9846
+ ca347546a8a49fc1.10db4f590cd09503.797b30bd708097ab.8039f48fd61eefa2
+ 3119c8420d9559e3.10603a025c4faee7.59659398168572ec.8c75760bc24a3843
+ 4e0bdab348e6dde8.ff7034132bdbd253.3fb73531c2a57abb.985649fb1efeafd6
+ 002869c987c58f06
+ after
+ 3c9164d1fb08f455.a19577ae9dd34dfa.c52d92b4b6892dca.1856c719beed9846
+ ca347546a8a49fc1.10db4f590cd09503.797b30bd708097ab.8039f48fd61eefa2
+ 3119c8420d9559e3.10603a025c4faee7.59659398168572ec.8c75760bc24a3843
+ 4e0bdab348e6dde8.ff7034132bdbd253.3fb73531c2a57abb.985649fb1efeafd6
+ 002869c987c58f06
+
+VPSRLD_0x05_128(reg)
+ before
+ 2037d3e3992c1580.fbd8258475a4e8fb.375739fa15003ef3.083d947593eb6a41
+ 54ce82b4eebe7df0.154a27a1afda364a.16614622b54a2d72.91c32b4ea363ffac
+ f83b72a825070201.782e5bf6139482fe.f6d956f7a846dc7d.b41577aa0e19f428
+ 67c89f2bd793e260.01503d6fbcde8945.340d65e5898087c0.4efef373f11a07e1
+ 3b4c1a976771f202
+ after
+ 0000000000000000.0000000000000000.01a06b2f044c043e.0277f79b0788d03f
+ 54ce82b4eebe7df0.154a27a1afda364a.16614622b54a2d72.91c32b4ea363ffac
+ f83b72a825070201.782e5bf6139482fe.f6d956f7a846dc7d.b41577aa0e19f428
+ 67c89f2bd793e260.01503d6fbcde8945.340d65e5898087c0.4efef373f11a07e1
+ 3b4c1a976771f202
+VPSRLD_0x05_128(mem)
+ before
+ 57c96a018d2b71b7.ffc205a9a3ef57b8.8a7c4af8c6c5074b.2d476f58f4826ae6
+ 7f425f9d7e53422e.1b75a18e22a69db6.f07dfc7e4e54b83c.3bd471bc86dac09b
+ 8d83735757f51f90.172d6e47f345f205.0f21d1eb70985743.bb00657ddb14c68d
+ 5e58241b331ec50c.4e36683eaf579052.c332442d479ca18c.091649088ebbb865
+ 816418c73b5bd1d2
+ after
+ 57c96a018d2b71b7.ffc205a9a3ef57b8.8a7c4af8c6c5074b.2d476f58f4826ae6
+ 7f425f9d7e53422e.1b75a18e22a69db6.f07dfc7e4e54b83c.3bd471bc86dac09b
+ 8d83735757f51f90.172d6e47f345f205.0f21d1eb70985743.bb00657ddb14c68d
+ 5e58241b331ec50c.4e36683eaf579052.c332442d479ca18c.091649088ebbb865
+ 816418c73b5bd1d2
+
+VPSRLD_0x05_128(reg)
+ before
+ 8034cf287f804e7e.ce8cedd52fd9f0cc.1edb8be1f468b449.e87dd22eef6c5244
+ 60d46895f5b76b15.b9ec4a7166325bfc.e269d39a5e049995.5acef5dc85152697
+ 7e8ee17c3a8b6445.fb45b8dbf436c3ca.f52d3dd788b87ce3.f5f12b2224a2d8b1
+ 36af3548e98874b7.7061b100f6f0e45f.b571c4030f1099df.95b2efece91f25bd
+ 16dcbd26ef99c8e7
+ after
+ 0000000000000000.0000000000000000.05ab8e20007884ce.04ad977f0748f92d
+ 60d46895f5b76b15.b9ec4a7166325bfc.e269d39a5e049995.5acef5dc85152697
+ 7e8ee17c3a8b6445.fb45b8dbf436c3ca.f52d3dd788b87ce3.f5f12b2224a2d8b1
+ 36af3548e98874b7.7061b100f6f0e45f.b571c4030f1099df.95b2efece91f25bd
+ 16dcbd26ef99c8e7
+VPSRLD_0x05_128(mem)
+ before
+ 543c12bc531b7f5c.e48260659f3bd81a.f30db3ca886c79ea.7c8164898e962c34
+ 2b9f689a30b10448.e4555f3ff72fcc18.62153927c5b64095.a8ab1ad7a1d8718f
+ 76cf3daca36814d6.92722d428ef08c5d.9844bf02c9dbf38c.933ae059e561a39b
+ 13990cdec74b6a33.4a27c6daff0b5397.7168c247b1e74efc.9b79b479f5beff05
+ 1ab591a46e7ac078
+ after
+ 543c12bc531b7f5c.e48260659f3bd81a.f30db3ca886c79ea.7c8164898e962c34
+ 2b9f689a30b10448.e4555f3ff72fcc18.62153927c5b64095.a8ab1ad7a1d8718f
+ 76cf3daca36814d6.92722d428ef08c5d.9844bf02c9dbf38c.933ae059e561a39b
+ 13990cdec74b6a33.4a27c6daff0b5397.7168c247b1e74efc.9b79b479f5beff05
+ 1ab591a46e7ac078
+
+VPSRAD_0x05_128(reg)
+ before
+ 6d3a7346ec2123a1.ddc8521db966c38b.67be2674e70b5e6f.c94bbce198e40f11
+ f15457cc0940642c.b02a895394c6db09.4784497ae17de894.7bba2bbe9be0f0f6
+ 004f37a06462bfc4.67892f6e74766eda.45c52c5989ec2fb0.65818acad5e7aed8
+ f777113096137016.e0b3bf5976823729.bdccc97e7ce46d6f.626c56ef630404e3
+ 4d47091a6043af42
+ after
+ 0000000000000000.0000000000000000.fdee664b03e7236b.031362b703182027
+ f15457cc0940642c.b02a895394c6db09.4784497ae17de894.7bba2bbe9be0f0f6
+ 004f37a06462bfc4.67892f6e74766eda.45c52c5989ec2fb0.65818acad5e7aed8
+ f777113096137016.e0b3bf5976823729.bdccc97e7ce46d6f.626c56ef630404e3
+ 4d47091a6043af42
+VPSRAD_0x05_128(mem)
+ before
+ 04dd2137e9b06b22.3317e0e73ee0b2ce.f672b500b6f7f423.0be71e5456f1df7e
+ 62fc19331958f4ae.0e7ca130f554c297.84938d4f4fe05ef3.8a602746b2a0c089
+ 426e6df80d460613.e5f24e7959fbdb1d.68e1c4325d4934c7.9885dec22c7c4e3b
+ 82009a74e0865c7c.14c5e52d06623b0d.7c2ad595fd3f30c8.90a041336112c341
+ cdfd4b05eced5b47
+ after
+ 04dd2137e9b06b22.3317e0e73ee0b2ce.f672b500b6f7f423.0be71e5456f1df7e
+ 62fc19331958f4ae.0e7ca130f554c297.84938d4f4fe05ef3.8a602746b2a0c089
+ 426e6df80d460613.e5f24e7959fbdb1d.68e1c4325d4934c7.9885dec22c7c4e3b
+ 82009a74e0865c7c.14c5e52d06623b0d.7c2ad595fd3f30c8.90a041336112c341
+ cdfd4b05eced5b47
+
+VPSRAD_0x05_128(reg)
+ before
+ adeaf8a46a9954f8.fc7e1b92af25b316.f74161b997141c13.9e393c644acd0f25
+ 8bb2447d76a3e801.8eb46b3e952ec60d.eab2be87a99dbbdb.a8d9758b61008d07
+ c2a02cfaad96540d.126d0964aeae528c.4963f904d78a5310.78d7fdf75de2659d
+ b002aa89aafed3c9.65776ef017af13c0.70a20c9cbd66215e.e8ff4e925b815511
+ d51de64a76e91690
+ after
+ 0000000000000000.0000000000000000.03851064fdeb310a.ff47fa7402dc0aa8
+ 8bb2447d76a3e801.8eb46b3e952ec60d.eab2be87a99dbbdb.a8d9758b61008d07
+ c2a02cfaad96540d.126d0964aeae528c.4963f904d78a5310.78d7fdf75de2659d
+ b002aa89aafed3c9.65776ef017af13c0.70a20c9cbd66215e.e8ff4e925b815511
+ d51de64a76e91690
+VPSRAD_0x05_128(mem)
+ before
+ 1cfd4109cb256745.af22bc940a67a3e0.649c17ceec40c5d5.bbb9f5bcf8be6172
+ 976ad9bd7541025d.1d4d5d89685efeff.e9a981ea486a24f6.86f5afce241d4ff8
+ 23322b519149a403.54ce8ad2616f20d2.d16a2730473beb4f.2da23640dc0f269c
+ 9d1fb4b13a4a0964.b1f33ddd90244704.f9ab858d06bed70e.0c0c877dbc202309
+ 7f7e9df161dd82eb
+ after
+ 1cfd4109cb256745.af22bc940a67a3e0.649c17ceec40c5d5.bbb9f5bcf8be6172
+ 976ad9bd7541025d.1d4d5d89685efeff.e9a981ea486a24f6.86f5afce241d4ff8
+ 23322b519149a403.54ce8ad2616f20d2.d16a2730473beb4f.2da23640dc0f269c
+ 9d1fb4b13a4a0964.b1f33ddd90244704.f9ab858d06bed70e.0c0c877dbc202309
+ 7f7e9df161dd82eb
+
+VPSRAD_0x05_128(reg)
+ before
+ e246740866d17fef.dffeefc98c4fedac.91077415920bad42.3b3718eba000a35c
+ 91ae082e688955c1.c69b5985a4650b06.4e552ae602b08f38.74dc5a38320b0d68
+ e70355cf028f410c.2ec26cd19e97209f.452a5cbc7c9d2891.8064c95ed7eecf5c
+ 42915857d1727e7d.f33ea69a95f1e7a2.d3d204039d60b6f9.3b9ce04bacb2a565
+ 82501ceacc654dae
+ after
+ 0000000000000000.0000000000000000.fe9e9020fceb05b7.01dce702fd65952b
+ 91ae082e688955c1.c69b5985a4650b06.4e552ae602b08f38.74dc5a38320b0d68
+ e70355cf028f410c.2ec26cd19e97209f.452a5cbc7c9d2891.8064c95ed7eecf5c
+ 42915857d1727e7d.f33ea69a95f1e7a2.d3d204039d60b6f9.3b9ce04bacb2a565
+ 82501ceacc654dae
+VPSRAD_0x05_128(mem)
+ before
+ 2f4cf72754128164.fda40c3270bb4ac0.f1dd82caa5801e3c.529920280185731e
+ 1f5cefee5fc6feb2.74876dcd7cf8df80.05697c4feb4f7f99.1fcbab9543969ba9
+ 2e4c7f2b0a8c80c5.0288779290b47a6a.09af1013836ac7e4.96b3a1b7ff216c49
+ 38e723cb7070c2c9.05f127ef487c5629.da7bbb0488ddb14a.139ffefbd2b220a8
+ f2d9bfcc57d4f472
+ after
+ 2f4cf72754128164.fda40c3270bb4ac0.f1dd82caa5801e3c.529920280185731e
+ 1f5cefee5fc6feb2.74876dcd7cf8df80.05697c4feb4f7f99.1fcbab9543969ba9
+ 2e4c7f2b0a8c80c5.0288779290b47a6a.09af1013836ac7e4.96b3a1b7ff216c49
+ 38e723cb7070c2c9.05f127ef487c5629.da7bbb0488ddb14a.139ffefbd2b220a8
+ f2d9bfcc57d4f472
+
+VPUNPCKLWD_128(reg)
+ before
+ 90aedf952b132455.19fa57b8ad7f81e9.d70f774f41dbb16a.5499f70d16b5faf6
+ 476a5ac4e9fbebfa.ad5198dfdec47951.d62e651d175dc5d8.52d5421a4afe5e15
+ 74592cc42e198610.cfb8612d1f4b652f.5d9aecc7658fce20.b2fa18173fc299d3
+ 73c6520195f83141.5dfb2e8d8b2103ad.c79f09b8c7fb0aee.4fd5f3f0120f665b
+ 05335191def182da
+ after
+ 0000000000000000.0000000000000000.b2fa52d51817421a.3fc24afe99d35e15
+ 476a5ac4e9fbebfa.ad5198dfdec47951.d62e651d175dc5d8.52d5421a4afe5e15
+ 74592cc42e198610.cfb8612d1f4b652f.5d9aecc7658fce20.b2fa18173fc299d3
+ 73c6520195f83141.5dfb2e8d8b2103ad.c79f09b8c7fb0aee.4fd5f3f0120f665b
+ 05335191def182da
+VPUNPCKLWD_128(mem)
+ before
+ b0deade6bf72a97b.9fffc6e7bb242739.32e67bea3e510df7.7288b65cda30b3ed
+ 2ca383dcd3a0976b.564e86e33b2aa6a6.2a44c53255e73f3b.b8a3f1203ab706ca
+ 544d4f5d338707d6.f3008d5fb295e831.21e28650ebf057a2.f63ab56e821e3e31
+ 06aa8d57fd31b6e7.d261d8c8bbf22989.f28d3c301d770f5b.899afeb34ef199cd
+ cb0fc95c3bba514a
+ after
+ b0deade6bf72a97b.9fffc6e7bb242739.32e67bea3e510df7.7288b65cda30b3ed
+ 2ca383dcd3a0976b.564e86e33b2aa6a6.2a44c53255e73f3b.b8a3f1203ab706ca
+ 0000000000000000.0000000000000000.7288b8a3b65cf120.da303ab7b3ed06ca
+ 06aa8d57fd31b6e7.d261d8c8bbf22989.f28d3c301d770f5b.899afeb34ef199cd
+ cb0fc95c3bba514a
+
+VPUNPCKLWD_128(reg)
+ before
+ 19e510d3e407a256.1d84bab44dac60ca.4fbd618bf2cca758.7b0f62be07882490
+ d067d186e664ca9b.75a951623e04c0ad.c6602612f4af9c4a.973475e6c330516d
+ 4ae307e0dc5b03c5.e9e3ce4cec4393ba.939522cb5d27450c.21caef95707a531f
+ e4a3af4c637a8a81.57ffae5e7477951d.11aa5121c8c1dd4a.f79c4eb52772e6d2
+ f4750d330725c6b1
+ after
+ 0000000000000000.0000000000000000.21ca9734ef9575e6.707ac330531f516d
+ d067d186e664ca9b.75a951623e04c0ad.c6602612f4af9c4a.973475e6c330516d
+ 4ae307e0dc5b03c5.e9e3ce4cec4393ba.939522cb5d27450c.21caef95707a531f
+ e4a3af4c637a8a81.57ffae5e7477951d.11aa5121c8c1dd4a.f79c4eb52772e6d2
+ f4750d330725c6b1
+VPUNPCKLWD_128(mem)
+ before
+ f322a8fc299eafe9.faf4c338164d9b7b.99c86b84f2ac8203.9ee9b080d108a1af
+ d26f9cfbabe95ca6.e822410f925e715e.8d0c83aa81ed1598.959f39541589cde8
+ 6b28631ba9138a13.0b79243d723b49d7.0d9671bc3d460b07.5118ea092fcf9da1
+ 9c197b4a3e27f45c.bd45682f52705f91.f731b2a643c3207d.30a0be0bbc664c85
+ 8c82b2c657db1841
+ after
+ f322a8fc299eafe9.faf4c338164d9b7b.99c86b84f2ac8203.9ee9b080d108a1af
+ d26f9cfbabe95ca6.e822410f925e715e.8d0c83aa81ed1598.959f39541589cde8
+ 0000000000000000.0000000000000000.9ee9959fb0803954.d1081589a1afcde8
+ 9c197b4a3e27f45c.bd45682f52705f91.f731b2a643c3207d.30a0be0bbc664c85
+ 8c82b2c657db1841
+
+VPUNPCKLWD_128(reg)
+ before
+ c30cc0a69db93a80.3f0e5f73863257af.5bd10a4fcf88ee39.25aac055ae710f26
+ 2f88e618298cf1ef.31d28c829e3f6f35.416b040a850f337b.75cd19b39b5b952d
+ 2e431f8698e07739.4f327c63a25af81d.cb5d54cd0f916a02.c16638ae258e6ebe
+ 1a89675e8542090b.73faad03ad8fae91.55f4f502099bcf7b.e641993069145607
+ c129b82782fc0831
+ after
+ 0000000000000000.0000000000000000.c16675cd38ae19b3.258e9b5b6ebe952d
+ 2f88e618298cf1ef.31d28c829e3f6f35.416b040a850f337b.75cd19b39b5b952d
+ 2e431f8698e07739.4f327c63a25af81d.cb5d54cd0f916a02.c16638ae258e6ebe
+ 1a89675e8542090b.73faad03ad8fae91.55f4f502099bcf7b.e641993069145607
+ c129b82782fc0831
+VPUNPCKLWD_128(mem)
+ before
+ 2cec127e8c4f416b.51a6ba0b8d3ee311.7af69a4cdbeb4cbe.3b7ce41710b89d91
+ 04542221a51bbddf.2de515f94b5e40f6.41f2bf2b49798fcf.d8401b77bf7512f1
+ 252e64fce66b37ba.0c9473935c305e67.a2ba998d124632f1.8a8e988eb35c6747
+ 6c4654fb6d4c6c27.48fdd0475b407610.7a19a25c535df34f.acb056c888fbdb3e
+ 9af45191d8dea882
+ after
+ 2cec127e8c4f416b.51a6ba0b8d3ee311.7af69a4cdbeb4cbe.3b7ce41710b89d91
+ 04542221a51bbddf.2de515f94b5e40f6.41f2bf2b49798fcf.d8401b77bf7512f1
+ 0000000000000000.0000000000000000.3b7cd840e4171b77.10b8bf759d9112f1
+ 6c4654fb6d4c6c27.48fdd0475b407610.7a19a25c535df34f.acb056c888fbdb3e
+ 9af45191d8dea882
+
+VPUNPCKHWD_128(reg)
+ before
+ b0a4855542900bc1.b3686e0a56c91853.3e6d2880e418c79c.a5dd588627ca8c16
+ 4a0def805f9d40a5.d75f2f16bceef769.4a3078ab94468bb7.00d036f6ab99b972
+ c37a8a7ecd9282da.b4f91209bbc7c496.c992bb320756ff0f.65bfb898fad7388e
+ 793952bc28f90e0d.260093d170613c06.15dfec82d7d25f4d.b1765b58318fc397
+ c0c19a226bce17b8
+ after
+ 0000000000000000.0000000000000000.c9924a30bb3278ab.07569446ff0f8bb7
+ 4a0def805f9d40a5.d75f2f16bceef769.4a3078ab94468bb7.00d036f6ab99b972
+ c37a8a7ecd9282da.b4f91209bbc7c496.c992bb320756ff0f.65bfb898fad7388e
+ 793952bc28f90e0d.260093d170613c06.15dfec82d7d25f4d.b1765b58318fc397
+ c0c19a226bce17b8
+VPUNPCKHWD_128(mem)
+ before
+ 6e6bf1e2c59ff01e.c79543a40b6120ea.09412e58f6c71be4.8b630a08a348e720
+ 9742dc845a0e09f5.08d95aa41353f41c.3988608c6a061d5d.87690e2e0544d232
+ 1710d7f547281f68.9a529126db5dc550.92a1a458e829fd9c.653ef66299505d2f
+ caa25f1fa7f8eea4.d74ce698ff0ad032.f05876a88a3c78ce.812ebc0ffcfbc3c5
+ 37855ea1c9ce429d
+ after
+ 6e6bf1e2c59ff01e.c79543a40b6120ea.09412e58f6c71be4.8b630a08a348e720
+ 9742dc845a0e09f5.08d95aa41353f41c.3988608c6a061d5d.87690e2e0544d232
+ 0000000000000000.0000000000000000.094139882e58608c.f6c76a061be41d5d
+ caa25f1fa7f8eea4.d74ce698ff0ad032.f05876a88a3c78ce.812ebc0ffcfbc3c5
+ 37855ea1c9ce429d
+
+VPUNPCKHWD_128(reg)
+ before
+ e38fd8849d571466.8cc4eff0968a31d4.1d1354651ce7516d.2f7852686f4c491f
+ e1982424132176ca.3842035231eba625.c6f3d8f9ce7f83ae.2bceb484b0642eba
+ 8deb40edc8b8a375.ace71733932607c3.30376cc0b05ea3a0.c02719e86c90e1cb
+ 43d5274b57a9d815.c381a77ed94710d9.b52d0e265e11edf0.c94dfc80bcdd1f80
+ 240dd939be56a303
+ after
+ 0000000000000000.0000000000000000.3037c6f36cc0d8f9.b05ece7fa3a083ae
+ e1982424132176ca.3842035231eba625.c6f3d8f9ce7f83ae.2bceb484b0642eba
+ 8deb40edc8b8a375.ace71733932607c3.30376cc0b05ea3a0.c02719e86c90e1cb
+ 43d5274b57a9d815.c381a77ed94710d9.b52d0e265e11edf0.c94dfc80bcdd1f80
+ 240dd939be56a303
+VPUNPCKHWD_128(mem)
+ before
+ ac322cfd8e072a80.5fa2d5aa5c7f5153.59da301f1f5b7f93.b31fb99875239d49
+ 3d8a72ba47fd7024.3d9e467775c74ade.4abf2d027f6d0e1f.845a69809020ee58
+ b2df265a0643311b.3915771c3b0cfe60.71fc1a1318897aa7.852a1b4b4c951dc9
+ e9ffc4cbe6e52890.af5363074cdaaa85.ac5d743e04bc7e57.13dbca66450d6647
+ 88b8713c1514047f
+ after
+ ac322cfd8e072a80.5fa2d5aa5c7f5153.59da301f1f5b7f93.b31fb99875239d49
+ 3d8a72ba47fd7024.3d9e467775c74ade.4abf2d027f6d0e1f.845a69809020ee58
+ 0000000000000000.0000000000000000.59da4abf301f2d02.1f5b7f6d7f930e1f
+ e9ffc4cbe6e52890.af5363074cdaaa85.ac5d743e04bc7e57.13dbca66450d6647
+ 88b8713c1514047f
+
+VPUNPCKHWD_128(reg)
+ before
+ 410f0f385a37341c.bdb4c8f803f013b0.faa406a244bd8afa.d6aeb56f5f11d75c
+ 9a2a9dc8b00132cb.09cbaecd7a6faba7.78535c5bbe42da6b.caba5b93469441e2
+ f0561857b2fe3a38.ab0ff336666fafa0.84ad619d56f4d583.664fe194d4527814
+ 9ddf7d51fdbb870e.7d4e121fe4fad9c8.79fe12d4a960b8ef.8437c3602556381f
+ 023f7ee156ad3c2f
+ after
+ 0000000000000000.0000000000000000.84ad7853619d5c5b.56f4be42d583da6b
+ 9a2a9dc8b00132cb.09cbaecd7a6faba7.78535c5bbe42da6b.caba5b93469441e2
+ f0561857b2fe3a38.ab0ff336666fafa0.84ad619d56f4d583.664fe194d4527814
+ 9ddf7d51fdbb870e.7d4e121fe4fad9c8.79fe12d4a960b8ef.8437c3602556381f
+ 023f7ee156ad3c2f
+VPUNPCKHWD_128(mem)
+ before
+ ba338c058361416f.fe11c7222cc356fa.5d538774101ee64a.b5926a6c5211bf5b
+ 8adf6bb7c780020c.6f37f236dca2e3a8.25e9ce2104e79253.93b565d1ee932572
+ 4c0e96e33f163c31.4c9ffbfaa8e56ac3.b3dd6313df60980e.6eb2ff6f187227e1
+ de8e8a75062eab0b.f193dcd82c1726f7.e1fbc334ba95b6a8.a4d735b36d3b0153
+ 8f6e0107887aef75
+ after
+ ba338c058361416f.fe11c7222cc356fa.5d538774101ee64a.b5926a6c5211bf5b
+ 8adf6bb7c780020c.6f37f236dca2e3a8.25e9ce2104e79253.93b565d1ee932572
+ 0000000000000000.0000000000000000.5d5325e98774ce21.101e04e7e64a9253
+ de8e8a75062eab0b.f193dcd82c1726f7.e1fbc334ba95b6a8.a4d735b36d3b0153
+ 8f6e0107887aef75
+
+VPADDUSB_128(reg)
+ before
+ 8dc461d906b92cf2.1a29c15938d40bc5.ba61933e05c554f1.8d0f6972b492a54d
+ f82551938286f577.ddacb97bf214188c.03531b96cf792f5d.91e5d1b8e6642428
+ 2eddcba3996d86b0.04e3edc74ffb8d8c.28b5714e24c1f5e6.ca4878f16f16ed66
+ 8938cd74e6f81a48.699ad92a6c9427f0.85d58fd1a329e039.1506d80b68b5bd33
+ 4ce96ff1ef4c50ba
+ after
+ 0000000000000000.0000000000000000.88ffaaffffa2ff96.a6ebffc3ffffe15b
+ f82551938286f577.ddacb97bf214188c.03531b96cf792f5d.91e5d1b8e6642428
+ 2eddcba3996d86b0.04e3edc74ffb8d8c.28b5714e24c1f5e6.ca4878f16f16ed66
+ 8938cd74e6f81a48.699ad92a6c9427f0.85d58fd1a329e039.1506d80b68b5bd33
+ 4ce96ff1ef4c50ba
+VPADDUSB_128(mem)
+ before
+ 4cbeb88f20e76227.6681527205b5eeec.e99cfa8e65eca1e5.76fe738ae63c2d02
+ f1512fd11692aea8.22055609942f3e48.60b7cae1540eb996.577b18e7898617ec
+ 176e51a4ed5af166.1711d5a52cf34607.aab5c70e58062930.83997a532993dba4
+ 9ae098f2c24ae690.a2efcbb26b8c41d5.a4636c008ae0addf.58a5953b61f0b5d5
+ 31e86609ce28e12c
+ after
+ 4cbeb88f20e76227.6681527205b5eeec.e99cfa8e65eca1e5.76fe738ae63c2d02
+ f1512fd11692aea8.22055609942f3e48.60b7cae1540eb996.577b18e7898617ec
+ 0000000000000000.0000000000000000.ffffffffb9faffff.cdff8bffffc244ee
+ 9ae098f2c24ae690.a2efcbb26b8c41d5.a4636c008ae0addf.58a5953b61f0b5d5
+ 31e86609ce28e12c
+
+VPADDUSB_128(reg)
+ before
+ 6ab1e82a0bc89a55.577582a8b16f4b50.1fec359cec876c5f.288d35a509a903ce
+ 5e4b170bb55b1dfb.28f78ab3d5d4dad2.eb530ed04c6e0351.13ff9fe8ee6de52a
+ 6b01ef16676da6cb.ea332dfd4a855044.607252b827cf4157.418525b55736101e
+ eb216db9bd8b7170.79f5e5742d8f68cf.db93fec21836641c.8eeb43f9601240d7
+ d6fc759e240c3081
+ after
+ 0000000000000000.0000000000000000.ffe6ffff64a4676d.a1ffe2ffff7fffff
+ 5e4b170bb55b1dfb.28f78ab3d5d4dad2.eb530ed04c6e0351.13ff9fe8ee6de52a
+ 6b01ef16676da6cb.ea332dfd4a855044.607252b827cf4157.418525b55736101e
+ eb216db9bd8b7170.79f5e5742d8f68cf.db93fec21836641c.8eeb43f9601240d7
+ d6fc759e240c3081
+VPADDUSB_128(mem)
+ before
+ f5853791c0319d47.3cf58b5e543fb997.b109300399fddfa2.b8030c58bb2da64c
+ c75206bf4f8c4356.b9ca4773c818bbeb.6e3b8996abdb71e7.530f7ae8ad424395
+ 282f5d12ed29ddd9.bdec9d63b49fb319.8c566c197e36daca.080043dd890179a0
+ f3e8b878b71529fd.a6a6879ab462dccd.e62856782f19d578.332563a3ecf5821c
+ 30c9d7a671aa9ab3
+ after
+ f5853791c0319d47.3cf58b5e543fb997.b109300399fddfa2.b8030c58bb2da64c
+ c75206bf4f8c4356.b9ca4773c818bbeb.6e3b8996abdb71e7.530f7ae8ad424395
+ 0000000000000000.0000000000000000.ff44b999ffffffff.ff1286ffff6fe9e1
+ f3e8b878b71529fd.a6a6879ab462dccd.e62856782f19d578.332563a3ecf5821c
+ 30c9d7a671aa9ab3
+
+VPADDUSB_128(reg)
+ before
+ 5b379952b5acff11.064993dbc95be1ee.ce46028465ed73b2.5a7bc19fd9901f1d
+ 10bda7135388ebe3.3c1d6a293d07c1d7.93160b8d63cab475.c31c2b7a99a874e5
+ aba5fd56e7c99bd5.7132ba4d322687e5.4f649d214987dbc2.fdd70ff68a6c90fa
+ 883c95850efc4b93.8152fe33c2c3ed43.5f7ab5adb3af2344.e477eafdc9e82e8b
+ 53ca367d71290bc2
+ after
+ 0000000000000000.0000000000000000.f290c0ffffffd7b9.ff93ffffffffa2ff
+ 10bda7135388ebe3.3c1d6a293d07c1d7.93160b8d63cab475.c31c2b7a99a874e5
+ aba5fd56e7c99bd5.7132ba4d322687e5.4f649d214987dbc2.fdd70ff68a6c90fa
+ 883c95850efc4b93.8152fe33c2c3ed43.5f7ab5adb3af2344.e477eafdc9e82e8b
+ 53ca367d71290bc2
+VPADDUSB_128(mem)
+ before
+ 289a71609e3ae3cc.03ce6c0d64ab36c8.474ab2c709eab01e.20a54d9b3ecfc9a7
+ 3eb516946d2771d4.77a67f5b84659920.a1e652f524a88ba1.ec30635985720999
+ 70e5a104fafd7207.4212c9da0bb3b048.6af15baa2e083bfa.2069f25125241ec3
+ 9cf78f9c60c7a291.bf5c46f59323b7ec.7d3948d044167c52.189af6f1b97246d4
+ 31116ba4dee7ba76
+ after
+ 289a71609e3ae3cc.03ce6c0d64ab36c8.474ab2c709eab01e.20a54d9b3ecfc9a7
+ 3eb516946d2771d4.77a67f5b84659920.a1e652f524a88ba1.ec30635985720999
+ 0000000000000000.0000000000000000.e8ffffff2dffffbf.ffd5b0f4c3ffd2ff
+ 9cf78f9c60c7a291.bf5c46f59323b7ec.7d3948d044167c52.189af6f1b97246d4
+ 31116ba4dee7ba76
+
+VPMULHUW_128(reg)
+ before
+ c5184ed62f10b956.9cb75a48bb91bd9d.4ad1f31abb40e9b7.b888955581df0ad8
+ 31fc99f348777d1f.4ef080f428687e57.3ebdcbb41d978356.f5abbe23026ea1b5
+ d1094a67c6aa437e.8c707c8cc257a2ed.f96cc92f55b3c075.126e3f28e2d0fc18
+ 018a5d9e4535471e.3401cafca66ae589.d52aecf70020debf.e99d954f3d0fd82b
+ 58043b83303af01b
+ after
+ 0000000000000000.0000000000000000.343dbc8e00037246.e02f6ee50094888b
+ 31fc99f348777d1f.4ef080f428687e57.3ebdcbb41d978356.f5abbe23026ea1b5
+ d1094a67c6aa437e.8c707c8cc257a2ed.f96cc92f55b3c075.126e3f28e2d0fc18
+ 018a5d9e4535471e.3401cafca66ae589.d52aecf70020debf.e99d954f3d0fd82b
+ 58043b83303af01b
+VPMULHUW_128(mem)
+ before
+ 396fadb2d75a0113.1dcdcc0560a2c5ac.2070e731efae0257.30432d79b96a17e1
+ 6aa967c74d7dc740.811c9506b480f8d4.2e894e15ba2eb684.6502891f1d1ea886
+ c57fe6afaeaefecd.89c4b20edc581d41.38187a9622f7bd3c.cfb4fd57c7c8cc5b
+ 27bea55417f962e7.9111228a74b870a0.1ce9ea9f4414d3aa.cca5848b54f2c10b
+ b6211a295f2ac143
+ after
+ 396fadb2d75a0113.1dcdcc0560a2c5ac.2070e731efae0257.30432d79b96a17e1
+ 6aa967c74d7dc740.811c9506b480f8d4.2e894e15ba2eb684.6502891f1d1ea886
+ 0000000000000000.0000000000000000.05e54683ae4f01ab.130a185b15160fb8
+ 27bea55417f962e7.9111228a74b870a0.1ce9ea9f4414d3aa.cca5848b54f2c10b
+ b6211a295f2ac143
+
+VPMULHUW_128(reg)
+ before
+ ea74bc9b85fb08af.6d2f20a3a46baeba.f54fdee5192b2c9c.b4c7171b3b91b3fb
+ c5ea644f61f2d4fa.71a1d3886f0f9f71.11cae38a663d8ee2.dd807ff8247a1a5a
+ a1ce10b08f9a5fd1.10df3af097f2f039.41ce2ee7f87bd21d.73de9c211adcc4f4
+ db6ebb2aac7fe6e0.26b4d2c6361f5f3e.e1a6ba676a7033fb.53aeec8239c26cf5
+ 57bceb079f39cf88
+ after
+ 0000000000000000.0000000000000000.0faea5ad2a811d03.48677639083a0b37
+ c5ea644f61f2d4fa.71a1d3886f0f9f71.11cae38a663d8ee2.dd807ff8247a1a5a
+ a1ce10b08f9a5fd1.10df3af097f2f039.41ce2ee7f87bd21d.73de9c211adcc4f4
+ db6ebb2aac7fe6e0.26b4d2c6361f5f3e.e1a6ba676a7033fb.53aeec8239c26cf5
+ 57bceb079f39cf88
+VPMULHUW_128(mem)
+ before
+ 5cd4139d654ca9da.d0146229542ea5d2.8fee16f568a2a6ab.4d9f837659a9ef25
+ 3ec1e22ea907b616.da0dff192232d753.2857826b4a8881ac.e005868060b1404a
+ d951d3a78677b169.56a59067b217b910.cbbc9213f7dcae6e.f824bdf21c146214
+ 094e62f519a757ff.a027107da16a87b5.55e9c3d98baae71d.f0482636285e932f
+ 24bdbcb9211c0d48
+ after
+ 5cd4139d654ca9da.d0146229542ea5d2.8fee16f568a2a6ab.4d9f837659a9ef25
+ 3ec1e22ea907b616.da0dff192232d753.2857826b4a8881ac.e005868060b1404a
+ 0000000000000000.0000000000000000.16ae0bb21e76546c.43ec451121dd3c0e
+ 094e62f519a757ff.a027107da16a87b5.55e9c3d98baae71d.f0482636285e932f
+ 24bdbcb9211c0d48
+
+VPMULHUW_128(reg)
+ before
+ efce7be8a2d90d0b.aa850b037ea36403.15e17bc88bb67cee.a2aa8fa924fee9e5
+ afc8602d4822ce23.98c24bbcd07794a2.0f1dcdb50b88d566.8eca746fdbe570f1
+ bef866f6ae828d3d.afd19d0e2b30a207.eb2903afbd6acec9.f517ee17ce6b376d
+ 7aa888ae70858605.cb7e7ce4acda4b5f.054f18213eeaa3c5.b35b778e199afb86
+ a4638dbed7807868
+ after
+ 0000000000000000.0000000000000000.0050136302d58884.6409366015fd6ef7
+ afc8602d4822ce23.98c24bbcd07794a2.0f1dcdb50b88d566.8eca746fdbe570f1
+ bef866f6ae828d3d.afd19d0e2b30a207.eb2903afbd6acec9.f517ee17ce6b376d
+ 7aa888ae70858605.cb7e7ce4acda4b5f.054f18213eeaa3c5.b35b778e199afb86
+ a4638dbed7807868
+VPMULHUW_128(mem)
+ before
+ a4fbaa952428693e.3d24c5c12bb8f526.c894672a6e7f4ad6.b9dc087929948f03
+ 8eef4cfd1d9f8c35.65ba169b7ba6164c.82e1d7cc8e2d5d97.631bcf221bf3cf32
+ 400aefe4def09b79.4cb579a8fbdb2425.d52f4ab627f03ecf.5f5a6988af939ffc
+ 951a0d3582275235.5060e85447e45c5b.9d4b3bd456d2aaa9.09e4d31782003b0d
+ bd04083c2fc7de12
+ after
+ a4fbaa952428693e.3d24c5c12bb8f526.c894672a6e7f4ad6.b9dc087929948f03
+ 8eef4cfd1d9f8c35.65ba169b7ba6164c.82e1d7cc8e2d5d97.631bcf221bf3cf32
+ 0000000000000000.0000000000000000.668b56f63d5d1b5b.47f306da048a73bf
+ 951a0d3582275235.5060e85447e45c5b.9d4b3bd456d2aaa9.09e4d31782003b0d
+ bd04083c2fc7de12
+
+VPADDUSW_128(reg)
+ before
+ d70704615273c5b7.69e924dc25516f96.cb08610bfc4cf99a.b501261336e15c52
+ b339c3f388902ba8.9844afc5e479acc7.1bf9e03ab59f388f.fb1c875de32911f6
+ ace6425f6dab4e90.fdf72adcdaabc6f5.9a7f5f4b0f6955e6.4a6adba07ab485c0
+ 205a7c0f9c4f681b.76ce110d24f4784c.a5e6dcaca5378c4a.7eb59cc6179074dd
+ 72cb48bdd5c99978
+ after
+ 0000000000000000.0000000000000000.c1dfffffffffc4d9.fffffffffab986d3
+ b339c3f388902ba8.9844afc5e479acc7.1bf9e03ab59f388f.fb1c875de32911f6
+ ace6425f6dab4e90.fdf72adcdaabc6f5.9a7f5f4b0f6955e6.4a6adba07ab485c0
+ 205a7c0f9c4f681b.76ce110d24f4784c.a5e6dcaca5378c4a.7eb59cc6179074dd
+ 72cb48bdd5c99978
+VPADDUSW_128(mem)
+ before
+ 04765a70d069b2be.6ae06d71b109b6f6.de95e144dd5f7ff7.997a52c714951968
+ 0e834fcb257e78da.e6c511f0496473cd.1017156e22f99722.d086bd0af70e37eb
+ 6ebea2baf014aaf9.ef5664f800ecdd4b.ea2229750ecc7cfb.a75719e0eb2e2380
+ fff2ce294c360247.e3dd63f5712e2e1d.46809947bee6eaac.7a3a63b58b8118d3
+ a57995f57494548f
+ after
+ 04765a70d069b2be.6ae06d71b109b6f6.de95e144dd5f7ff7.997a52c714951968
+ 0e834fcb257e78da.e6c511f0496473cd.1017156e22f99722.d086bd0af70e37eb
+ 0000000000000000.0000000000000000.eeacf6b2ffffffff.ffffffffffff5153
+ fff2ce294c360247.e3dd63f5712e2e1d.46809947bee6eaac.7a3a63b58b8118d3
+ a57995f57494548f
+
+VPADDUSW_128(reg)
+ before
+ 8460ad0c41f21161.9ced510455f03def.1da7095338b4a2ef.02fee1ce4d539c61
+ 743da7668e278cf4.2279a738284e171e.f8ff527ef20d776c.f8687ef8d71e4f47
+ cf5b7d6ff8c000f5.6e634aafe05d4b00.d2333ae23ac2e740.068aebb07953be8a
+ f2052d941b48aa10.5a77b8569a2897c0.058dbeebad612f19.062fa4e24ffea655
+ d625257a742cc3d5
+ after
+ 0000000000000000.0000000000000000.fe8cffffffffa685.fe97fffffffff59c
+ 743da7668e278cf4.2279a738284e171e.f8ff527ef20d776c.f8687ef8d71e4f47
+ cf5b7d6ff8c000f5.6e634aafe05d4b00.d2333ae23ac2e740.068aebb07953be8a
+ f2052d941b48aa10.5a77b8569a2897c0.058dbeebad612f19.062fa4e24ffea655
+ d625257a742cc3d5
+VPADDUSW_128(mem)
+ before
+ 5036eb6404e8d136.3988b23f924bc6f0.c4816c1a71bcb48a.ef5bd906e6758aa1
+ 512f718c1c3f8ca3.003008def9569042.864de2e68223618c.eae7879d828b3584
+ b6dc33dfd83baf48.a3492bdbedf443b1.7da696a5e86c58f0.547ec41e1c2e6d6f
+ 5909ad4753ebf752.7d1f17a40ab21cea.865a0545bfa056e2.876c8cf451ea6b0e
+ e1fcdc8bbc4c6e0c
+ after
+ 5036eb6404e8d136.3988b23f924bc6f0.c4816c1a71bcb48a.ef5bd906e6758aa1
+ 512f718c1c3f8ca3.003008def9569042.864de2e68223618c.eae7879d828b3584
+ 0000000000000000.0000000000000000.fffffffff3dfffff.ffffffffffffc025
+ 5909ad4753ebf752.7d1f17a40ab21cea.865a0545bfa056e2.876c8cf451ea6b0e
+ e1fcdc8bbc4c6e0c
+
+VPADDUSW_128(reg)
+ before
+ bc7caf4ef9dfb016.17815bb2a9581fed.ecfdc9a4eb1b5799.7b33aab125cd178f
+ 753601aba52f6ed7.cc12ba0af790e545.4b313c472cbb3069.39fe01d533fe5723
+ 6977ce0d5cc9e3fd.5586453d589e0385.f6056cf96a1ee207.9c87869d0740d1c9
+ f28b13e1b9384d31.8cab7836e98f35d9.49c6562640d1aa1e.809ab5f6bd9d42ae
+ c2020bca702465fd
+ after
+ 0000000000000000.0000000000000000.94f7926d6d8cda87.ba98b7cbf19b99d1
+ 753601aba52f6ed7.cc12ba0af790e545.4b313c472cbb3069.39fe01d533fe5723
+ 6977ce0d5cc9e3fd.5586453d589e0385.f6056cf96a1ee207.9c87869d0740d1c9
+ f28b13e1b9384d31.8cab7836e98f35d9.49c6562640d1aa1e.809ab5f6bd9d42ae
+ c2020bca702465fd
+VPADDUSW_128(mem)
+ before
+ 3c8d03063cdef8e3.6dbeca915808e621.4e4bcfe1c56e396f.9fc0f43a4b5fc35b
+ cb0519973ed9b58c.365cf18ad6c6ea79.7732c7290947c970.563f44a226556b6a
+ 4b37ca6891205923.a9b08339cffd97e5.e32edafdd027a20b.c98e41c86d3edcf6
+ 98ef906452c09fd5.23087d08de392710.6e0a86463618806a.53fbe71abea653ab
+ 52d03302b2190b37
+ after
+ 3c8d03063cdef8e3.6dbeca915808e621.4e4bcfe1c56e396f.9fc0f43a4b5fc35b
+ cb0519973ed9b58c.365cf18ad6c6ea79.7732c7290947c970.563f44a226556b6a
+ 0000000000000000.0000000000000000.c57dffffceb5ffff.f5ffffff71b4ffff
+ 98ef906452c09fd5.23087d08de392710.6e0a86463618806a.53fbe71abea653ab
+ 52d03302b2190b37
+
+VPMULLW_128(reg)
+ before
+ 215a20eee7244244.8ef9e9799dc444cd.feaed9659f07d7a6.f49146f158291eb9
+ 1be5aa49f953327e.092150928c380438.97ef95bbaff2e354.519097ea52633926
+ 9ebdcd7f83301792.e532419b3e299b42.4a17ac76a98786c6.61d3f31e3fd48dda
+ 042e85fc21492f2c.fdfa3980cca2c416.73721b022a50fda8.0026d8773c88d504
+ 0a55c1e36489cfce
+ after
+ 0000000000000000.0000000000000000.056ee476afa03320.1b600dc6f8988298
+ 1be5aa49f953327e.092150928c380438.97ef95bbaff2e354.519097ea52633926
+ 9ebdcd7f83301792.e532419b3e299b42.4a17ac76a98786c6.61d3f31e3fd48dda
+ 042e85fc21492f2c.fdfa3980cca2c416.73721b022a50fda8.0026d8773c88d504
+ 0a55c1e36489cfce
+VPMULLW_128(mem)
+ before
+ 5a2c2b4dd3e53564.ab83cf2c7029b4f7.2f43b22d55af3ce1.6e4bdccbcddc84a5
+ ce7690a0a6a8c3f3.ed0aa67b0c5de3a0.56da2a8ff25dbfce.97f0ed3d2eb45669
+ 41016ecaf8dc37a7.280d06558f70f7d3.4e8b1c90c1b7090a.4aab49c4eb66b1a1
+ 8f9740b6e68f4bab.b6d9eb2698ee2e3b.f321041ddec9d5c0.e2c9eccc9d7dcff9
+ bd96d2c2e285ec1d
+ after
+ 5a2c2b4dd3e53564.ab83cf2c7029b4f7.2f43b22d55af3ce1.6e4bdccbcddc84a5
+ ce7690a0a6a8c3f3.ed0aa67b0c5de3a0.56da2a8ff25dbfce.97f0ed3d2eb45669
+ 0000000000000000.0000000000000000.c10ee9238e93dc0e.a3508b5f46b0d5ad
+ 8f9740b6e68f4bab.b6d9eb2698ee2e3b.f321041ddec9d5c0.e2c9eccc9d7dcff9
+ bd96d2c2e285ec1d
+
+VPMULLW_128(reg)
+ before
+ 365ef810560b46b7.930582508bcdbc2c.f4ba515bc164c284.206a5f2364a0e01e
+ a96d5824949a1776.2b17b08504a04556.3ffc355ea65def5c.b330a88d7047e64d
+ 720ef06838bf9c04.3298473f6c16a354.f1ea929de465f36c.87415b461dcaa27c
+ ec8fbc4adf05100e.8356c26be03b9253.67d2648316090863.7767f43c8736d1d5
+ 616fef5acb962f84
+ after
+ 0000000000000000.0000000000000000.e0b8071ad7457094.6850e50c1ffa7b11
+ a96d5824949a1776.2b17b08504a04556.3ffc355ea65def5c.b330a88d7047e64d
+ 720ef06838bf9c04.3298473f6c16a354.f1ea929de465f36c.87415b461dcaa27c
+ ec8fbc4adf05100e.8356c26be03b9253.67d2648316090863.7767f43c8736d1d5
+ 616fef5acb962f84
+VPMULLW_128(mem)
+ before
+ 2025c98c04f677b6.753ab63525f8b03f.fc1b9df67b19ce7e.fdfea77cd8d46beb
+ 8f54fdbe4f636797.685cdc95a524b844.77b454ca5abf1302.0fbb58f4c85258b0
+ 8cca07dcc8e8b952.204129d6fb1664c9.d2ed63d598361c0a.fa5572577f100a60
+ f15163d389922914.fb359964c45aef79.e7924702528ca6c3.1818f1119b99bea5
+ c650d18eb879b02b
+ after
+ 2025c98c04f677b6.753ab63525f8b03f.fc1b9df67b19ce7e.fdfea77cd8d46beb
+ 8f54fdbe4f636797.685cdc95a524b844.77b454ca5abf1302.0fbb58f4c85258b0
+ 0000000000000000.0000000000000000.cffc5c1ca1a7f6fc.6a8a423013e8f990
+ f15163d389922914.fb359964c45aef79.e7924702528ca6c3.1818f1119b99bea5
+ c650d18eb879b02b
+
+VPMULLW_128(reg)
+ before
+ 60480e3a713d1b9f.9bb68e8db16c7508.548328ab9b7a9700.946f7b3da3cc6c59
+ 424ea58262703cac.67c502f85982575c.8679d3181d04950c.b3507b72a7022bf7
+ c8ac91d0289f4f00.2f4a3dfea0e08c39.ef619415e5832847.2200c38d7b3b9fca
+ 4eafce925f559044.d111ba8d9f93d0cd.e988691090848a5d.bb4cd07a3b8284fe
+ 5b011d2502e496be
+ after
+ 0000000000000000.0000000000000000.9148098036109d5c.abc074544504fb12
+ 424ea58262703cac.67c502f85982575c.8679d3181d04950c.b3507b72a7022bf7
+ c8ac91d0289f4f00.2f4a3dfea0e08c39.ef619415e5832847.2200c38d7b3b9fca
+ 4eafce925f559044.d111ba8d9f93d0cd.e988691090848a5d.bb4cd07a3b8284fe
+ 5b011d2502e496be
+VPMULLW_128(mem)
+ before
+ dfe9257aec6c9036.30a35832a21e3a27.27e5f69075a6de44.d23a4e73b992f8fb
+ 21d0676616262f94.cad32c1e8d868a53.0e946bf23b2673ca.04c33dacfd39aecd
+ fe845cd39b1e2e02.788d44c1bd1abc74.62e897a10f1e4b8a.dc6e3426f706e77e
+ 52cf82af98614bac.951b9e87cd650c38.00aef5880d9a21b0.b7892d4d4384e1bb
+ ef5e268d7e3fd52f
+ after
+ dfe9257aec6c9036.30a35832a21e3a27.27e5f69075a6de44.d23a4e73b992f8fb
+ 21d0676616262f94.cad32c1e8d868a53.0e946bf23b2673ca.04c33dacfd39aecd
+ 0000000000000000.0000000000000000.96644420b8a4eda8.0a2e1c449b82faff
+ 52cf82af98614bac.951b9e87cd650c38.00aef5880d9a21b0.b7892d4d4384e1bb
+ ef5e268d7e3fd52f
+
+VPSHUFHW_0x39_128(reg)
+ before
+ e13a1b5244c40287.fa7f54e428fa40bf.7fcb35dc5af4b548.c2b2019450a6b26a
+ ea690608309ea26f.d05e4e6068f6c967.91e7062cff51f453.85c038aff44fbae1
+ 6437e51bde59f292.b139ec0e7360a4cf.27bc0be3590b0503.25a315c616a0f544
+ acf0b3f8eb822e9d.79dcaada66448b24.9c96426e03ab2304.7e2913c6d2a61ebd
+ 6c1cb199436cf278
+ after
+ 0000000000000000.0000000000000000.23049c96426e03ab.7e2913c6d2a61ebd
+ ea690608309ea26f.d05e4e6068f6c967.91e7062cff51f453.85c038aff44fbae1
+ 6437e51bde59f292.b139ec0e7360a4cf.27bc0be3590b0503.25a315c616a0f544
+ acf0b3f8eb822e9d.79dcaada66448b24.9c96426e03ab2304.7e2913c6d2a61ebd
+ 6c1cb199436cf278
+VPSHUFHW_0x39_128(mem)
+ before
+ cb49682d85fe2da3.1ee06c09f3a4923c.041305b05caf3b91.4ec0a6379abf8b03
+ 777cb56cb5698b67.16520cbc904b591a.2ea9787c72ac7043.988834acb9d279ac
+ 4c811544eeb8c7f3.f093907b6104c0e3.d36c7f2bc347e566.d538e637fd7129aa
+ 262403a04df79e71.09eff3b4005a0244.cf2697a76b8c5725.631dba460127d6aa
+ 9d83ab446180bd58
+ after
+ cb49682d85fe2da3.1ee06c09f3a4923c.041305b05caf3b91.4ec0a6379abf8b03
+ 0000000000000000.0000000000000000.04133b915caf05b0.4ec0a6379abf8b03
+ 4c811544eeb8c7f3.f093907b6104c0e3.d36c7f2bc347e566.d538e637fd7129aa
+ 262403a04df79e71.09eff3b4005a0244.cf2697a76b8c5725.631dba460127d6aa
+ 9d83ab446180bd58
+
+VPSHUFHW_0x39_128(reg)
+ before
+ deb6b59cba091a5f.e130fb6ced33cb0d.bbb231d209da5de9.fea43add878882ad
+ 8402d4bca84c286b.59737a94eb770cf5.63284641190e0b7e.3cb2e6ba33472129
+ e9b20510c6d8242a.6ab7fb0462cf1b52.5d9d2f6dcb8449ae.651c16288ad3f2c6
+ 6a144302b0364a46.f0c9f9a96f47b553.055ce6c2bbc85225.54ad4615a83aafaf
+ e733f36caa881412
+ after
+ 0000000000000000.0000000000000000.5225055ce6c2bbc8.54ad4615a83aafaf
+ 8402d4bca84c286b.59737a94eb770cf5.63284641190e0b7e.3cb2e6ba33472129
+ e9b20510c6d8242a.6ab7fb0462cf1b52.5d9d2f6dcb8449ae.651c16288ad3f2c6
+ 6a144302b0364a46.f0c9f9a96f47b553.055ce6c2bbc85225.54ad4615a83aafaf
+ e733f36caa881412
+VPSHUFHW_0x39_128(mem)
+ before
+ f9789819abc7df18.64728aff03f4d66b.c675f26d2dec9522.b6b269ac87656390
+ 6649b108c805caf0.3119d6735a9e0346.ca86623db9ca78eb.ceecb398c8e7b89b
+ 0972ba251d4e92c4.2f5523cb52be0e83.d7cac3062eec1adb.a854c1f01cda8df1
+ c0bf2f5cc4acf2c0.b8726e7186e233cd.c90b93b3a85e371e.a0368d211fcb1d3f
+ 12e015986c45a531
+ after
+ f9789819abc7df18.64728aff03f4d66b.c675f26d2dec9522.b6b269ac87656390
+ 0000000000000000.0000000000000000.c67595222decf26d.b6b269ac87656390
+ 0972ba251d4e92c4.2f5523cb52be0e83.d7cac3062eec1adb.a854c1f01cda8df1
+ c0bf2f5cc4acf2c0.b8726e7186e233cd.c90b93b3a85e371e.a0368d211fcb1d3f
+ 12e015986c45a531
+
+VPSHUFHW_0x39_128(reg)
+ before
+ 5a9d54c09fd56172.66fc8d9adc2ea711.29bbb2d39396add1.7b174d2f442c8adf
+ d3b8460455068daf.d6f44ec97edd6de3.de7eeb5c1464b93a.cbb86d681e63d14b
+ db7ee8d22a646493.ee75f0d6c8c70061.34051578a6da93b5.94bb7049510ec58e
+ cd3b3495b97b23cb.8849efaed6f71cb8.859d2d92e48477ee.b1ecd0bef93925d3
+ 00160bb333f1ab47
+ after
+ 0000000000000000.0000000000000000.77ee859d2d92e484.b1ecd0bef93925d3
+ d3b8460455068daf.d6f44ec97edd6de3.de7eeb5c1464b93a.cbb86d681e63d14b
+ db7ee8d22a646493.ee75f0d6c8c70061.34051578a6da93b5.94bb7049510ec58e
+ cd3b3495b97b23cb.8849efaed6f71cb8.859d2d92e48477ee.b1ecd0bef93925d3
+ 00160bb333f1ab47
+VPSHUFHW_0x39_128(mem)
+ before
+ 5b079c141a411415.043b28b99ed80603.823dc53cc3797c14.2e922e186beca090
+ a089ffcecb351c6a.decabfab760748e6.b61df06bac5adda0.8b301476d6a04b48
+ a969b1cb61da7e71.b533f6d5dc922620.02b5eb29aca5fa88.f8c3db16c12cb4c1
+ 53732df9f93bf857.e7c4c7a46d07dc5f.40d03261df6690fa.d1967f65c91b16a8
+ 72f6fdcf8af9afa9
+ after
+ 5b079c141a411415.043b28b99ed80603.823dc53cc3797c14.2e922e186beca090
+ 0000000000000000.0000000000000000.823d7c14c379c53c.2e922e186beca090
+ a969b1cb61da7e71.b533f6d5dc922620.02b5eb29aca5fa88.f8c3db16c12cb4c1
+ 53732df9f93bf857.e7c4c7a46d07dc5f.40d03261df6690fa.d1967f65c91b16a8
+ 72f6fdcf8af9afa9
+
+VPSHUFLW_0x39_128(reg)
+ before
+ 373050c19f52b96f.7b73ef42ae654348.cec73085c4f1a64d.4e3c41ff62aa5b20
+ 7c8e74a5a4b370a7.fb3573949d631e6f.c8892ce27eddbf96.06c395ef517c1726
+ 9d5d65e936a712fc.b08435dae14143f9.2f56b729365664e7.4532a81ec7e98039
+ f6e820f8f1bbd91b.772eb200970b6f11.617acec489e8d1ec.e855f876e0fc5185
+ c9f801e4b9c14735
+ after
+ 0000000000000000.0000000000000000.617acec489e8d1ec.5185e855f876e0fc
+ 7c8e74a5a4b370a7.fb3573949d631e6f.c8892ce27eddbf96.06c395ef517c1726
+ 9d5d65e936a712fc.b08435dae14143f9.2f56b729365664e7.4532a81ec7e98039
+ f6e820f8f1bbd91b.772eb200970b6f11.617acec489e8d1ec.e855f876e0fc5185
+ c9f801e4b9c14735
+VPSHUFLW_0x39_128(mem)
+ before
+ c5e73d556d441d76.e37d9f3e6f7902b0.2afd64f1dace5ee5.b8416b2112204150
+ b8ed2ab319929173.c066e0274f6fc866.a6beca9cc795cc9e.92f68cab6d89f1c0
+ 7fd742ecd8b75d59.e9f1df1f2a2968ea.c73d5dea796d746a.49e72cce37af1de7
+ f47204ebc7bd3d54.b96896929f321ee7.6a469ac80c611375.3a5e47f60c1f0172
+ c1a8da8f8764d80d
+ after
+ c5e73d556d441d76.e37d9f3e6f7902b0.2afd64f1dace5ee5.b8416b2112204150
+ 0000000000000000.0000000000000000.2afd64f1dace5ee5.b841415012206b21
+ 7fd742ecd8b75d59.e9f1df1f2a2968ea.c73d5dea796d746a.49e72cce37af1de7
+ f47204ebc7bd3d54.b96896929f321ee7.6a469ac80c611375.3a5e47f60c1f0172
+ c1a8da8f8764d80d
+
+VPSHUFLW_0x39_128(reg)
+ before
+ 3b11e006440adf63.f488e99c01b2ef8f.8e1803ec4716260a.69a4fe229d7d64eb
+ 02e455c5e09e5221.5be56eeba3a12d37.c34c2099c162bbff.a12504e547ce25f7
+ 736f3539f7ab6cf3.055710c4c897b477.b352eb06a6a01a71.ee9328fb275e10c5
+ eafc7ccf23bd6b84.cea94a138d9f407c.bc74609d945f7f0c.2cbbe652593ce282
+ 3769bbd4f871565a
+ after
+ 0000000000000000.0000000000000000.bc74609d945f7f0c.e2822cbbe652593c
+ 02e455c5e09e5221.5be56eeba3a12d37.c34c2099c162bbff.a12504e547ce25f7
+ 736f3539f7ab6cf3.055710c4c897b477.b352eb06a6a01a71.ee9328fb275e10c5
+ eafc7ccf23bd6b84.cea94a138d9f407c.bc74609d945f7f0c.2cbbe652593ce282
+ 3769bbd4f871565a
+VPSHUFLW_0x39_128(mem)
+ before
+ eb69226f200b2979.c3d927f203618980.92a698c40dc58c72.390079cc2728267e
+ 2487970eee16170a.5a50300d30220294.2d1b77c364165584.854034fefa894a71
+ be8e969d7d9cdc39.0bae968e498c136c.7bd461fdaf9d57df.fe818c9eaa0d2891
+ 954c9b08eaab3333.323e52e0e72cf9b4.589dd45c0a664dae.fe0f7d1ad241fc8b
+ e33603dd0eb0010b
+ after
+ eb69226f200b2979.c3d927f203618980.92a698c40dc58c72.390079cc2728267e
+ 0000000000000000.0000000000000000.92a698c40dc58c72.3900267e272879cc
+ be8e969d7d9cdc39.0bae968e498c136c.7bd461fdaf9d57df.fe818c9eaa0d2891
+ 954c9b08eaab3333.323e52e0e72cf9b4.589dd45c0a664dae.fe0f7d1ad241fc8b
+ e33603dd0eb0010b
+
+VPSHUFLW_0x39_128(reg)
+ before
+ 07411b53fbe674bc.848b233b504ed924.2b4e616fa98ded17.a0424bce907ef51e
+ c87dc0e93470914b.6918a923cc928a37.5228c0a7283c2e41.2e8f423e5df0095b
+ 8037ee0956d99463.1fbfa9aa79820299.031a6af502c4f6df.e04f36988ec84590
+ 8db9a120fdadb8b2.824b9fbe732afc76.9a6e5bc3d3b1829d.9150a1c83f1367ea
+ 1d5c01ba8adc2994
+ after
+ 0000000000000000.0000000000000000.9a6e5bc3d3b1829d.67ea9150a1c83f13
+ c87dc0e93470914b.6918a923cc928a37.5228c0a7283c2e41.2e8f423e5df0095b
+ 8037ee0956d99463.1fbfa9aa79820299.031a6af502c4f6df.e04f36988ec84590
+ 8db9a120fdadb8b2.824b9fbe732afc76.9a6e5bc3d3b1829d.9150a1c83f1367ea
+ 1d5c01ba8adc2994
+VPSHUFLW_0x39_128(mem)
+ before
+ 5f40d25a8e2f48bb.4950d59bc3793ae1.6e8a0849d79735f9.73718f7e368f0e26
+ 35c88e9464197f8a.114787e447c8569e.be465e39c1d4694f.ea6f0393c8ebd527
+ 7abfb2542ba58b2e.41ecb26922264795.504d1f784cee53a3.5bb3b26c2450144c
+ 09f3bb86fcdf28d3.36895295f3204b72.fe69c7f494efb022.218b9877e64b0740
+ 9a41b11fab67eab0
+ after
+ 5f40d25a8e2f48bb.4950d59bc3793ae1.6e8a0849d79735f9.73718f7e368f0e26
+ 0000000000000000.0000000000000000.6e8a0849d79735f9.73710e26368f8f7e
+ 7abfb2542ba58b2e.41ecb26922264795.504d1f784cee53a3.5bb3b26c2450144c
+ 09f3bb86fcdf28d3.36895295f3204b72.fe69c7f494efb022.218b9877e64b0740
+ 9a41b11fab67eab0
+
+VCVTPS2DQ_128(reg)
+ before
+ 2122f9d00f30f847.c02e2417f6d412a4.4a6c63d353419be0.a667d098b6e53cf7
+ 117b6df6ac326eb2.7a3d6af2328f05ce.dadfe291e015768b.2313b850cedcb250
+ c89508fd21fa879d.12ed0702ce1cbc7d.422fca3a36291621.5038f908f7dfd056
+ a1bfc651081381b3.66077935e688f4dc.dea8173af008b84b.0ba412ad4dfa5038
+ 2e217c29ed39ee1f
+ after
+ 0000000000000000.0000000000000000.8000000080000000.0000000091a6d800
+ 117b6df6ac326eb2.7a3d6af2328f05ce.dadfe291e015768b.2313b850cedcb250
+ c89508fd21fa879d.12ed0702ce1cbc7d.422fca3a36291621.5038f908f7dfd056
+ a1bfc651081381b3.66077935e688f4dc.dea8173af008b84b.0ba412ad4dfa5038
+ 2e217c29ed39ee1f
+VCVTPS2DQ_128(mem)
+ before
+ 977cb469f2a9683a.f744a35efd0a96a0.505a3b7695de6818.0a95c5feab3e98b8
+ 2081375a795578b3.286f9c909d6a0312.adb1c9b1f82bd55c.2344d0f00258f212
+ a6fc80e69d49dbb7.8e8dac5483bf03b3.5ad79fd22a79f7d5.83ff357d91e10105
+ 06b90bfb7b924d71.87ebcf144c96d42f.319939c547d78aae.8713ef12f566023f
+ 8accfa19ca713169
+ after
+ 977cb469f2a9683a.f744a35efd0a96a0.505a3b7695de6818.0a95c5feab3e98b8
+ 0000000000000000.0000000000000000.8000000000000000.0000000000000000
+ a6fc80e69d49dbb7.8e8dac5483bf03b3.5ad79fd22a79f7d5.83ff357d91e10105
+ 06b90bfb7b924d71.87ebcf144c96d42f.319939c547d78aae.8713ef12f566023f
+ 8accfa19ca713169
+
+VCVTPS2DQ_128(reg)
+ before
+ ea765200ab90c932.1a8354842e3b890e.6dd3013e937ab033.10c414766c4e4a14
+ 025df432344f0744.bf28d86dd3514cb9.9e913e3df4f7d36b.d122abd1b4ecf233
+ 2ecddb1b0239274b.d27212a285df529f.7473837d0d9a7b82.517f7ac33cbc3f36
+ ca110327b0da64f4.2d2e7e0f60f156ec.4cc3cb6977eee225.6ca9fe361fcbec4a
+ ff6bb1187a23b79a
+ after
+ 0000000000000000.0000000000000000.0000000080000000.8000000000000000
+ 025df432344f0744.bf28d86dd3514cb9.9e913e3df4f7d36b.d122abd1b4ecf233
+ 2ecddb1b0239274b.d27212a285df529f.7473837d0d9a7b82.517f7ac33cbc3f36
+ ca110327b0da64f4.2d2e7e0f60f156ec.4cc3cb6977eee225.6ca9fe361fcbec4a
+ ff6bb1187a23b79a
+VCVTPS2DQ_128(mem)
+ before
+ e490115469d35a53.327668c2dbbefceb.ad2898a0819415cb.83cf126fd07f45ff
+ f8e599d506e491a1.c24806581e7228dc.2e2cdd4104d24b69.73e154fbb4dae0bd
+ 1736c68970641aaf.d5d3da5516812771.8c05c7de04bab4f1.79468d77be8aee0b
+ 1d4f125bc05eafaa.c963df255e783459.a381d4649d550b90.f14aba508a1bac94
+ 3839d6f2b51a5605
+ after
+ e490115469d35a53.327668c2dbbefceb.ad2898a0819415cb.83cf126fd07f45ff
+ 0000000000000000.0000000000000000.0000000000000000.0000000080000000
+ 1736c68970641aaf.d5d3da5516812771.8c05c7de04bab4f1.79468d77be8aee0b
+ 1d4f125bc05eafaa.c963df255e783459.a381d4649d550b90.f14aba508a1bac94
+ 3839d6f2b51a5605
+
+VCVTPS2DQ_128(reg)
+ before
+ a85eddcada12270a.e6fcfb3714df0dbd.f944113593e28a3e.4f6a7fbdecb10d72
+ 9e07cc42968f5c4e.4e08fc0988f2f015.c0c16cef504b66cd.6c8d45d70cd976c2
+ 767e9dc8851e317d.314191be37a313de.7c28ecc1314003b1.d6b6a09d1ada01ad
+ 8c104ec7414ae244.6b7136403eff3343.88c38e15d34b9e97.69b10efa32bf6c5e
+ 014a0adc6e947102
+ after
+ 0000000000000000.0000000000000000.fffffffa80000000.8000000000000000
+ 9e07cc42968f5c4e.4e08fc0988f2f015.c0c16cef504b66cd.6c8d45d70cd976c2
+ 767e9dc8851e317d.314191be37a313de.7c28ecc1314003b1.d6b6a09d1ada01ad
+ 8c104ec7414ae244.6b7136403eff3343.88c38e15d34b9e97.69b10efa32bf6c5e
+ 014a0adc6e947102
+VCVTPS2DQ_128(mem)
+ before
+ 7a4c102eed66ccc5.3c09daab699faa4f.d865687cb8110c71.3fdf4d59d2fb732b
+ b0859ddcc8403bd2.e2b53de096aac64a.54e9a25fc1e55993.ffc825f8c9d9be18
+ 7fbf2bd31e2e7856.da5f74d267f672e0.bbc960d47688d8d6.22c9125e5473ba0a
+ c3c738fd083d407c.80557aed7510eabd.e9d01ec6f2054366.063011f71055a5af
+ 05471d2f9909b8b0
+ after
+ 7a4c102eed66ccc5.3c09daab699faa4f.d865687cb8110c71.3fdf4d59d2fb732b
+ 0000000000000000.0000000000000000.8000000000000000.0000000280000000
+ 7fbf2bd31e2e7856.da5f74d267f672e0.bbc960d47688d8d6.22c9125e5473ba0a
+ c3c738fd083d407c.80557aed7510eabd.e9d01ec6f2054366.063011f71055a5af
+ 05471d2f9909b8b0
+
+VSUBPS_128(reg)
+ before
+ 7c5b32738a1d32bc.58693f47a4784e71.30e14a9d5e82698e.b9cc59235268566e
+ c8b94c2d7f1c4d7d.1970bd9e0eeb5f61.4650e34ebedb2cff.09878bd6b2becf1b
+ 43aa68ca159346a0.e4aa2cec61a32f77.1eee3e6d30a46ebb.b4ce32cb2d126898
+ 4a7d80b7e70d59d0.94e10a1fbaab7adf.14075964516b6d6f.966dc9eedf70de12
+ 8a30cd2be5e5ecb5
+ after
+ 0000000000000000.0000000000000000.4650e34ed16b6d6f.166dc9ee5f70de12
+ c8b94c2d7f1c4d7d.1970bd9e0eeb5f61.4650e34ebedb2cff.09878bd6b2becf1b
+ 43aa68ca159346a0.e4aa2cec61a32f77.1eee3e6d30a46ebb.b4ce32cb2d126898
+ 4a7d80b7e70d59d0.94e10a1fbaab7adf.14075964516b6d6f.966dc9eedf70de12
+ 8a30cd2be5e5ecb5
+VSUBPS_128(mem)
+ before
+ 6ee3b86f5a7c4fac.3a7d925f9216c2ba.04e3d222340ffbc7.83e72ea1bcbb63c7
+ 1c5108a45b41c323.6df5992db13bbc09.127a00e0ebdc7059.c9d9bb8e0d218d6e
+ 724838b803410448.4033928fe107846a.99731047fc1d92c1.412bfc99e1272611
+ 4b92c4956e87ce45.0f8177f0bd075589.749a7f4282de202c.4727eb2dd45c6c5b
+ 361a86b6804999f9
+ after
+ 6ee3b86f5a7c4fac.3a7d925f9216c2ba.04e3d222340ffbc7.83e72ea1bcbb63c7
+ 1c5108a45b41c323.6df5992db13bbc09.127a00e0ebdc7059.c9d9bb8e0d218d6e
+ 0000000000000000.0000000000000000.127a00e0ebdc7059.c9d9bb8e3cbb63c7
+ 4b92c4956e87ce45.0f8177f0bd075589.749a7f4282de202c.4727eb2dd45c6c5b
+ 361a86b6804999f9
+
+VSUBPS_128(reg)
+ before
+ 6c50c7a0847ce997.82fc2929ba1fdc46.372c46bce2c56d11.81bac8bd9a2cd4c6
+ 4314ad577a809ae0.f552e15f0016eb78.127ffa5febcf06af.9aa167a560126bba
+ 19b43147fee2e680.7e606a225e77b607.fdc88f4574b15c0e.9d19d8e4ee9da135
+ 497a50ddad2d0a25.faf13f60f04ffa1e.545202db1af5addb.64ef986763d83163
+ cdef211bd9cfd96f
+ after
+ 0000000000000000.0000000000000000.d45202dbebcf06af.e4ef9867e3d70c8c
+ 4314ad577a809ae0.f552e15f0016eb78.127ffa5febcf06af.9aa167a560126bba
+ 19b43147fee2e680.7e606a225e77b607.fdc88f4574b15c0e.9d19d8e4ee9da135
+ 497a50ddad2d0a25.faf13f60f04ffa1e.545202db1af5addb.64ef986763d83163
+ cdef211bd9cfd96f
+VSUBPS_128(mem)
+ before
+ b2e5f1ea6c8e5285.2eb4078322ed4179.46d3dd04d1a973ea.73684d8b792a33c2
+ f09d83c238225bd3.26ac51a7faafc828.3cd0befa1d91dd96.b6576ec32cd92b6e
+ 64e2548e5b96ae82.8baf2ab3d0fedbdf.bab5602ff113f44f.796b60edcf90d18c
+ e882de3aeef708c1.ba098f154066b64a.9a4e3e8d683c7341.18f01f77ffda60c7
+ ef32a8cc574315cc
+ after
+ b2e5f1ea6c8e5285.2eb4078322ed4179.46d3dd04d1a973ea.73684d8b792a33c2
+ f09d83c238225bd3.26ac51a7faafc828.3cd0befa1d91dd96.b6576ec32cd92b6e
+ 0000000000000000.0000000000000000.c6d3dcf751a973ea.f3684d8bf92a33c2
+ e882de3aeef708c1.ba098f154066b64a.9a4e3e8d683c7341.18f01f77ffda60c7
+ ef32a8cc574315cc
+
+VSUBPS_128(reg)
+ before
+ 597cf65774582c47.59479fb20f4f25ba.10057a38e7749514.b967d4019f171797
+ b41c0586f2a4e1e3.93fe12e2daadc19a.e7f1e98861b3b3ea.f3cc9f78b2b19b7e
+ 5b5cd1c46bb46f4d.7373b3b66a1a978c.9c17d77149af4d77.254819dcbb15bd22
+ aa89567e7e131330.d372ff1adba464bd.8cc4415f3cf59e68.29a8c01bd94f37ae
+ dcb90f20256bc54e
+ after
+ 0000000000000000.0000000000000000.e7f1e98861b3b3ea.f3cc9f78594f37ae
+ b41c0586f2a4e1e3.93fe12e2daadc19a.e7f1e98861b3b3ea.f3cc9f78b2b19b7e
+ 5b5cd1c46bb46f4d.7373b3b66a1a978c.9c17d77149af4d77.254819dcbb15bd22
+ aa89567e7e131330.d372ff1adba464bd.8cc4415f3cf59e68.29a8c01bd94f37ae
+ dcb90f20256bc54e
+VSUBPS_128(mem)
+ before
+ 1a4583d7be76252f.fdef911ec44d0839.90c671fa4a56e358.114421bed510e469
+ bf19962cbd7c117d.afda7d11dbee8c13.863d8543d33dd28a.88e375fab08c5925
+ a700c60b41874664.1e9616c45f83d96c.91a1b7df9164eb7f.4ded38806af63949
+ aec88e6063a5800f.a56e58a1eb972ced.8dbf83bca0d7ea62.bdad66ba9ed9c280
+ 3271fb16e9c12e78
+ after
+ 1a4583d7be76252f.fdef911ec44d0839.90c671fa4a56e358.114421bed510e469
+ bf19962cbd7c117d.afda7d11dbee8c13.863d8543d33dd28a.88e375fab08c5925
+ 0000000000000000.0000000000000000.10c671f4d33dd2c0.914422305510e469
+ aec88e6063a5800f.a56e58a1eb972ced.8dbf83bca0d7ea62.bdad66ba9ed9c280
+ 3271fb16e9c12e78
+
+VADDPS_128(reg)
+ before
+ 0983f4fee73bbada.b03b6a1741e17aaa.9faf3f161cb7c045.566366c51da38d60
+ 9e304ce032d2a254.8926d61df748f162.6aa5c88d8d6ed31e.c859dae523d38ea4
+ 4dc4ff2769122192.15564f5ca0e5a163.609dee74da489f24.bf6d5d0acf73aa5b
+ 728b093f25887440.309450c258c445d9.dfe0ad36a0d26004.176a6b1f3c8f9db1
+ ac1e7e10873422d1
+ after
+ 0000000000000000.0000000000000000.6aa5c889a0d26004.c859dae53c8f9db1
+ 9e304ce032d2a254.8926d61df748f162.6aa5c88d8d6ed31e.c859dae523d38ea4
+ 4dc4ff2769122192.15564f5ca0e5a163.609dee74da489f24.bf6d5d0acf73aa5b
+ 728b093f25887440.309450c258c445d9.dfe0ad36a0d26004.176a6b1f3c8f9db1
+ ac1e7e10873422d1
+VADDPS_128(mem)
+ before
+ 5a5314cacb6ef6e7.69d0669405bfd708.b6af55393cf29bef.41bd023f7b97546a
+ fcd6a8372547d521.8ee11392a2448599.8372daaf687a5dd1.e47fe7fb0623b501
+ 7073b644b0cd7ba9.3d080ba59aa1bc9d.72a85c0ff76847ac.22715ad6dd03c076
+ 91f6bade890ca3ab.d2924a3a8965b6c1.611f554505c917ac.59e0563c9dc2b074
+ e318d79ae1ecc3a8
+ after
+ 5a5314cacb6ef6e7.69d0669405bfd708.b6af55393cf29bef.41bd023f7b97546a
+ fcd6a8372547d521.8ee11392a2448599.8372daaf687a5dd1.e47fe7fb0623b501
+ 0000000000000000.0000000000000000.b6af5539687a5dd1.e47fe7fb7b97546a
+ 91f6bade890ca3ab.d2924a3a8965b6c1.611f554505c917ac.59e0563c9dc2b074
+ e318d79ae1ecc3a8
+
+VADDPS_128(reg)
+ before
+ 1d65da5a460d33be.3b2a30efcb0e0a54.a9cbcdbb0a19afb0.2ba1433dafa887fc
+ 641359ea68b23c61.49dd956592e26cd0.1dff8e95ba4be517.acfba1e3101154c9
+ 126e52b4e1671c3e.99d9642bfb91844a.8c7a8b35348692a2.bff9ec234511393f
+ 84c1c0264fb70d01.06eb192c22290fef.5187bf061456f2fc.42669ee969b3f389
+ 1010352299033ed4
+ after
+ 0000000000000000.0000000000000000.5187bf06ba4be517.42669ee969b3f389
+ 641359ea68b23c61.49dd956592e26cd0.1dff8e95ba4be517.acfba1e3101154c9
+ 126e52b4e1671c3e.99d9642bfb91844a.8c7a8b35348692a2.bff9ec234511393f
+ 84c1c0264fb70d01.06eb192c22290fef.5187bf061456f2fc.42669ee969b3f389
+ 1010352299033ed4
+VADDPS_128(mem)
+ before
+ 04c12cb8f00ed64b.1759a0ab4e2e4c55.6bdf315622b5c9eb.c8742673f74843d2
+ fc46ff998bdf771b.2582ecaf795815e6.a681269417416d69.4c8bbdea78e8bfcf
+ d26c2baf8583dc6f.0b88a29e6dc2a362.919c76d21edab996.3b197ed634c0a3a0
+ 64fc2ae8fa04c274.25b7bde4c5f73372.0afe9cfd528b679d.f06a67a3c75e2bf0
+ c6ca73becc4d926d
+ after
+ 04c12cb8f00ed64b.1759a0ab4e2e4c55.6bdf315622b5c9eb.c8742673f74843d2
+ fc46ff998bdf771b.2582ecaf795815e6.a681269417416d69.4c8bbdea78e8bfcf
+ 0000000000000000.0000000000000000.6bdf315622b5c9ed.4c8b43d778cfb755
+ 64fc2ae8fa04c274.25b7bde4c5f73372.0afe9cfd528b679d.f06a67a3c75e2bf0
+ c6ca73becc4d926d
+
+VADDPS_128(reg)
+ before
+ 1b849f91df1a15c0.8cc57a2f0770e456.cf5b39ed1e8301c5.eb7115ffd06033ab
+ 49e6e5899d50f098.28929670c8d3ff40.65bf132613f34805.12c25bc5b366dbeb
+ ae3a4313a17b5f9e.122efb975838cf5f.433145f940d245de.59bdec3c18a8198a
+ a4cdb49988289d81.27672390d3ab10df.c5fbcdd342ac34fe.9d2e434e1a33aab4
+ bbe1dce9d6124a94
+ after
+ 0000000000000000.0000000000000000.65bf132642ac34fe.9d2e4348b366dbeb
+ 49e6e5899d50f098.28929670c8d3ff40.65bf132613f34805.12c25bc5b366dbeb
+ ae3a4313a17b5f9e.122efb975838cf5f.433145f940d245de.59bdec3c18a8198a
+ a4cdb49988289d81.27672390d3ab10df.c5fbcdd342ac34fe.9d2e434e1a33aab4
+ bbe1dce9d6124a94
+VADDPS_128(mem)
+ before
+ 8da133f86751b457.89eb3489ede2e7eb.44078c4756387eeb.476aa621b50e510e
+ f03cc567eafca529.b7e0bf4d6c357989.43dbb1a9fdecd4af.25cacd4e3383d7bd
+ c17c0d227a20d935.8cf85253a2ad8e06.01ae0ea0e3d2cf59.bb673cc55b9803b5
+ da2e871534c80ba7.627ee8062bd7640f.5a4e201924f72a12.658cf1f4c7d811a2
+ 7f87e74613cf3d31
+ after
+ 8da133f86751b457.89eb3489ede2e7eb.44078c4756387eeb.476aa621b50e510e
+ f03cc567eafca529.b7e0bf4d6c357989.43dbb1a9fdecd4af.25cacd4e3383d7bd
+ 0000000000000000.0000000000000000.4475651cfdecd4af.476aa621b4fbac2d
+ da2e871534c80ba7.627ee8062bd7640f.5a4e201924f72a12.658cf1f4c7d811a2
+ 7f87e74613cf3d31
+
+VMULPS_128(reg)
+ before
+ 64a21a27dc09c20e.181eaf2c3301f8ac.96bf7dd2a23f344f.2b866101dd66a309
+ 722a8603bd13dde4.5718015393d65c70.85080d23a46f3d73.4e214f43292bf468
+ 046b28475378ca60.73e7fa767153f31f.89a39565ccf5b927.a0ec65cb2553d95b
+ 76b1fb5d39c5c42e.48591582e98578e4.ffdc0f05b65de516.fdb31f84ece81010
+ 4142fa5c9bf953b0
+ after
+ 0000000000000000.0000000000000000.ffdc0f051b4f5e23.ff800000d69be048
+ 722a8603bd13dde4.5718015393d65c70.85080d23a46f3d73.4e214f43292bf468
+ 046b28475378ca60.73e7fa767153f31f.89a39565ccf5b927.a0ec65cb2553d95b
+ 76b1fb5d39c5c42e.48591582e98578e4.ffdc0f05b65de516.fdb31f84ece81010
+ 4142fa5c9bf953b0
+VMULPS_128(mem)
+ before
+ 4865713e4d8f5f6a.2347fbb20c8508f9.b338ce611576a8eb.4301796dff31fded
+ eee700171eb8f068.697b24b36744d26e.8e51a10114353f62.b15dcf0a42003d57
+ 0f9623d12b7fc1d6.a39773cae68e5e38.b6700b4d00cbf872.a63b0b491c53e001
+ 873c565990f18fe2.2ce8e26526f0e704.07618731f546914a.7ce82b9528b82397
+ 90b0295903ba41c4
+ after
+ 4865713e4d8f5f6a.2347fbb20c8508f9.b338ce611576a8eb.4301796dff31fded
+ eee700171eb8f068.697b24b36744d26e.8e51a10114353f62.b15dcf0a42003d57
+ 0000000000000000.0000000000000000.021754b800000000.b4e05d13ff800000
+ 873c565990f18fe2.2ce8e26526f0e704.07618731f546914a.7ce82b9528b82397
+ 90b0295903ba41c4
+
+VMULPS_128(reg)
+ before
+ 3edf030349e57835.32a6169c681916b5.62ba6fefc3f6aa7d.5cf0919810b1c414
+ e2c1b5fe94c60295.eca0de84cf03117e.9f5915d4582ae351.93e8a5706c194dfc
+ d8a239b682e81c91.91f62affe2bc3e67.4111d180811acd29.87173fa52689ea2f
+ 7ccd8d97afd701d5.fd7376f8bd4f579c.a22d9d5fdb51a5b4.1447dc21590d55d9
+ 1645f7d122b24b26
+ after
+ 0000000000000000.0000000000000000.02133933f40bf232.800000007f800000
+ e2c1b5fe94c60295.eca0de84cf03117e.9f5915d4582ae351.93e8a5706c194dfc
+ d8a239b682e81c91.91f62affe2bc3e67.4111d180811acd29.87173fa52689ea2f
+ 7ccd8d97afd701d5.fd7376f8bd4f579c.a22d9d5fdb51a5b4.1447dc21590d55d9
+ 1645f7d122b24b26
+VMULPS_128(mem)
+ before
+ 69dd0ca19c838740.2a90ac0eb620ee0c.0be53e5a7bc8184a.20fb77dd025ca79b
+ e8db977ee38cc656.3e359285344e1fe3.9916ff1338343f9d.15c55a6691c60f8d
+ 710a155214dac492.13093b69c4eed005.82d3340e119e86c0.ded84267241b1834
+ df38010b4b783d21.0757a427038b3c1f.a2e859372112aae0.d8802c4a58e8ff3d
+ 5d09127dc8b80053
+ after
+ 69dd0ca19c838740.2a90ac0eb620ee0c.0be53e5a7bc8184a.20fb77dd025ca79b
+ e8db977ee38cc656.3e359285344e1fe3.9916ff1338343f9d.15c55a6691c60f8d
+ 0000000000000000.0000000000000000.80000000748ce2cd.0000001880000000
+ df38010b4b783d21.0757a427038b3c1f.a2e859372112aae0.d8802c4a58e8ff3d
+ 5d09127dc8b80053
+
+VMULPS_128(reg)
+ before
+ cabef26a11175623.0e2fd794a373ec2e.756dc8298cb1a0dd.d421ea7b859d6629
+ 7cedc77fce923e58.d9bc13d938d58fe6.b996a3ddfbec38ea.f64a64c4584a77c6
+ cde08e279cb4f49f.1eab31c527acdf75.2e1d31aeedc940f3.e32e42ffb72599e4
+ 1ae441ce1609b4a4.b7c8ae468c049b06.324f6e08fdd3f3a3.769b0019bd3b88ae
+ 8d5b1afc8797ff51
+ after
+ 0000000000000000.0000000000000000.ac741e7e7f800000.ff800000d6145197
+ 7cedc77fce923e58.d9bc13d938d58fe6.b996a3ddfbec38ea.f64a64c4584a77c6
+ cde08e279cb4f49f.1eab31c527acdf75.2e1d31aeedc940f3.e32e42ffb72599e4
+ 1ae441ce1609b4a4.b7c8ae468c049b06.324f6e08fdd3f3a3.769b0019bd3b88ae
+ 8d5b1afc8797ff51
+VMULPS_128(mem)
+ before
+ 023b0d963046bcf8.bf45dee0d81eb912.82de054882e77dc5.20785757c8978ea7
+ b30753d2d45378d1.184f60c97f7e4096.59bbb2b5256442e0.53e4e707eaa04daa
+ 7a8b6a9c91caf205.814ec3f5a7b585db.1a29317a9284a681.29df1a84fd7a6b5a
+ 3592cddf80b7e4c2.568d04d0eb50c38e.9ff5fe83e45564d4.fdb5ec3aa0b22560
+ 2ab15a956dd3b76b
+ after
+ 023b0d963046bcf8.bf45dee0d81eb912.82de054882e77dc5.20785757c8978ea7
+ b30753d2d45378d1.184f60c97f7e4096.59bbb2b5256442e0.53e4e707eaa04daa
+ 0000000000000000.0000000000000000.9d22c8d880000000.34de0de773bdce46
+ 3592cddf80b7e4c2.568d04d0eb50c38e.9ff5fe83e45564d4.fdb5ec3aa0b22560
+ 2ab15a956dd3b76b
+
+VMAXPS_128(reg)
+ before
+ 0e205e0200695d24.beeaf989bf270b34.f35a1dc7e8da385b.c6eb96bd38e23a06
+ 034ef6ebf500523a.f25d68866a252387.b4ff0c4439e01eed.69d77413a937e143
+ 67871ebeea25d357.aeb898c09bbee8e6.f5c9ccb57aedb1f1.65851470546118b6
+ 9417d0e678641c28.ccc7042471fc157e.12045a84488d2f12.97c0f3c2546b998c
+ d9568bf4c66221f0
+ after
+ 0000000000000000.0000000000000000.12045a84488d2f12.69d77413546b998c
+ 034ef6ebf500523a.f25d68866a252387.b4ff0c4439e01eed.69d77413a937e143
+ 67871ebeea25d357.aeb898c09bbee8e6.f5c9ccb57aedb1f1.65851470546118b6
+ 9417d0e678641c28.ccc7042471fc157e.12045a84488d2f12.97c0f3c2546b998c
+ d9568bf4c66221f0
+VMAXPS_128(mem)
+ before
+ 08115af2c5516c0f.e74a0acf3d476858.2956289f06ee677a.67fbb01f3e4cd2fd
+ 00bedba86d443615.bd6bc6e4d55cf494.a131801b769d9907.50fcccf1f9b7d65e
+ 9e298a02db473a2d.70c80393db2ffc87.11238986de176950.2951a966145979e0
+ bc1ee4ec2b673584.5dabba48eb4abcde.53f9beca59679182.4e4843ea2cbff530
+ 1b2b96e9dc7387f9
+ after
+ 08115af2c5516c0f.e74a0acf3d476858.2956289f06ee677a.67fbb01f3e4cd2fd
+ 00bedba86d443615.bd6bc6e4d55cf494.a131801b769d9907.50fcccf1f9b7d65e
+ 0000000000000000.0000000000000000.2956289f769d9907.67fbb01f3e4cd2fd
+ bc1ee4ec2b673584.5dabba48eb4abcde.53f9beca59679182.4e4843ea2cbff530
+ 1b2b96e9dc7387f9
+
+VMAXPS_128(reg)
+ before
+ eb479fcfc1046be8.3768635378b0e245.e161e86da23b6f45.44809bd5049acdc9
+ 1ce7590976fbdca8.ebd58521de2cff9d.56368a6f9c8e5267.c0829c92fabbdb50
+ 0959c00198e617e7.b42fc5447ae946b8.19759bba74cda1f1.a3cc3eed58d67544
+ 0de8d025c250584e.6e43a0a667f273c1.866c17bbc686978e.c929fcd239f758d0
+ 0e67512db92b4021
+ after
+ 0000000000000000.0000000000000000.56368a6f9c8e5267.c0829c9239f758d0
+ 1ce7590976fbdca8.ebd58521de2cff9d.56368a6f9c8e5267.c0829c92fabbdb50
+ 0959c00198e617e7.b42fc5447ae946b8.19759bba74cda1f1.a3cc3eed58d67544
+ 0de8d025c250584e.6e43a0a667f273c1.866c17bbc686978e.c929fcd239f758d0
+ 0e67512db92b4021
+VMAXPS_128(mem)
+ before
+ 4e50bceaf67ee863.86df86df91c6db8c.f5dd9035c25444e5.f965fbdc2f4572eb
+ 65b1b6f609fa0dc1.cf8bdc9da0d3db4a.25c913dca71a734f.ceae418b4a956bb4
+ 2f57bd3b10ad6b68.4338d0ca8b039537.dad3a4873050bd2c.6291e733b402c194
+ 880c4ba727a2bd83.40325dd2efe345fd.f0c6bf227c03dea8.0f5be8400818ae38
+ 3257401ee364704b
+ after
+ 4e50bceaf67ee863.86df86df91c6db8c.f5dd9035c25444e5.f965fbdc2f4572eb
+ 65b1b6f609fa0dc1.cf8bdc9da0d3db4a.25c913dca71a734f.ceae418b4a956bb4
+ 0000000000000000.0000000000000000.25c913dca71a734f.ceae418b4a956bb4
+ 880c4ba727a2bd83.40325dd2efe345fd.f0c6bf227c03dea8.0f5be8400818ae38
+ 3257401ee364704b
+
+VMAXPS_128(reg)
+ before
+ 27d3ec39e071407a.4c9cdf2469e6c13f.20c5802168fd2649.4370e199a43e91ee
+ 4a19e6fd9ccb5d71.57d5f2a0f28431c7.413c332391e075c6.af9b84d8c70d932b
+ f6772cd6b2ff01db.84810106df88c949.fde5744406156e21.0f1426cbfe7da08a
+ 8937b930bf986965.b16e89424bff47ee.b10a3ef0642a4d05.41a7425e67997438
+ 2020557e1e6dca61
+ after
+ 0000000000000000.0000000000000000.413c3323642a4d05.41a7425e67997438
+ 4a19e6fd9ccb5d71.57d5f2a0f28431c7.413c332391e075c6.af9b84d8c70d932b
+ f6772cd6b2ff01db.84810106df88c949.fde5744406156e21.0f1426cbfe7da08a
+ 8937b930bf986965.b16e89424bff47ee.b10a3ef0642a4d05.41a7425e67997438
+ 2020557e1e6dca61
+VMAXPS_128(mem)
+ before
+ 884ad9153e065f30.5ea68a785e23d1ba.b966054053f465e5.baf88d9446ab4d1f
+ 54f34c11e46fefd2.d11099182b2b7487.7836f1ec1273e058.72fb5e9a4922ab1b
+ 62e5295d2bb43572.3ec0e47ec33c8f78.c9aac932a5897373.365eac70081da3a4
+ 8dedece52fe2ee3d.01046614c2e25e38.8a8d0afe2741db63.636f728020287067
+ 5379af382ccd5010
+ after
+ 884ad9153e065f30.5ea68a785e23d1ba.b966054053f465e5.baf88d9446ab4d1f
+ 54f34c11e46fefd2.d11099182b2b7487.7836f1ec1273e058.72fb5e9a4922ab1b
+ 0000000000000000.0000000000000000.7836f1ec53f465e5.72fb5e9a4922ab1b
+ 8dedece52fe2ee3d.01046614c2e25e38.8a8d0afe2741db63.636f728020287067
+ 5379af382ccd5010
+
+VMINPS_128(reg)
+ before
+ 63c75c03c99a7c4a.b0d711950d04d65e.75261b48c3aa1d74.96ad2f3db5a8d454
+ efa6764d921b33c1.a96f1559e026a802.f8740085621f07d7.c8d4b4d96ac81a71
+ 5362fa8224daaf22.5280731dc5552255.e5380f373cce590e.fed015c063af68e7
+ ec47e30e1a652d19.89d8a7cdd89cfe82.97be46caed424ec4.126bceddbb697ce2
+ e2725c1b8f010f8d
+ after
+ 0000000000000000.0000000000000000.f8740085ed424ec4.c8d4b4d9bb697ce2
+ efa6764d921b33c1.a96f1559e026a802.f8740085621f07d7.c8d4b4d96ac81a71
+ 5362fa8224daaf22.5280731dc5552255.e5380f373cce590e.fed015c063af68e7
+ ec47e30e1a652d19.89d8a7cdd89cfe82.97be46caed424ec4.126bceddbb697ce2
+ e2725c1b8f010f8d
+VMINPS_128(mem)
+ before
+ 48b03a68fa83e014.14a02d5d1048e952.28412d553408f8b6.6c54a0aa0f0724a7
+ 22f3e4af18fba9a5.28bbd5dba30e1f78.0d8882a2f5a3ce1d.be451a4341aa1560
+ 4a05d6dc0676276a.84e2d6f56f430a37.1279209e387c3ae2.ebdcae021cb55e9e
+ 9db48ddbe0ff168f.84622b150f73e73c.15e08537189cf931.4e675a513fb73a0a
+ 4230199e4339e753
+ after
+ 48b03a68fa83e014.14a02d5d1048e952.28412d553408f8b6.6c54a0aa0f0724a7
+ 22f3e4af18fba9a5.28bbd5dba30e1f78.0d8882a2f5a3ce1d.be451a4341aa1560
+ 0000000000000000.0000000000000000.0d8882a2f5a3ce1d.be451a430f0724a7
+ 9db48ddbe0ff168f.84622b150f73e73c.15e08537189cf931.4e675a513fb73a0a
+ 4230199e4339e753
+
+VMINPS_128(reg)
+ before
+ 2484e753c7c99f23.f8ca8498c1a33241.8488d2a91f2bf133.f0892d57b111c738
+ 51aec1de64f39e27.35143700c56d36ac.e09dc71b3cf666c8.803f92ec21e65f21
+ 23fca1aab841220a.315d22fd0969dffb.f4f004d9026180a6.a2d032e181287e18
+ f8b985235f416579.c973c17da8a3e85b.1bcc874e0cf67c79.30068722efe1e04a
+ 07ae0f9b872040e3
+ after
+ 0000000000000000.0000000000000000.e09dc71b0cf67c79.803f92ecefe1e04a
+ 51aec1de64f39e27.35143700c56d36ac.e09dc71b3cf666c8.803f92ec21e65f21
+ 23fca1aab841220a.315d22fd0969dffb.f4f004d9026180a6.a2d032e181287e18
+ f8b985235f416579.c973c17da8a3e85b.1bcc874e0cf67c79.30068722efe1e04a
+ 07ae0f9b872040e3
+VMINPS_128(mem)
+ before
+ 0394463864ee5b0e.2a3068b5f47fa41f.d721916abf280ff7.b37c4be6f64395ee
+ 0084a6e5a259edf8.16ae46cc13851ba9.38320db269030efc.174d4c0d5dd409b1
+ da49ad8f5e6cb2cc.187f1cd459e105c3.c873b140c341a196.a38b872fdc34116d
+ 6eb1d620b43465b7.8defe539621f9f18.63b0f900e8ed86f0.b382f6b810efeccf
+ a27e97159492d583
+ after
+ 0394463864ee5b0e.2a3068b5f47fa41f.d721916abf280ff7.b37c4be6f64395ee
+ 0084a6e5a259edf8.16ae46cc13851ba9.38320db269030efc.174d4c0d5dd409b1
+ 0000000000000000.0000000000000000.d721916abf280ff7.b37c4be6f64395ee
+ 6eb1d620b43465b7.8defe539621f9f18.63b0f900e8ed86f0.b382f6b810efeccf
+ a27e97159492d583
+
+VMINPS_128(reg)
+ before
+ cecb65b004a70734.96869d86bfbcc3e5.cf4a9d68c9c92555.e5b562def5137737
+ 92b45cf7febdbe8f.2f957eab9b108881.3bdb40cb2a6dd225.2a4e66c605c03196
+ 498779541b5d383f.15aaf67d653d6fb8.2df0cad02297e335.0e4683a435fe703a
+ 518eb735f915aff1.24917fe7384e36b5.01d338e14cd19431.6d6b3564a0dcef4f
+ 2387f6f262636b00
+ after
+ 0000000000000000.0000000000000000.01d338e12a6dd225.2a4e66c6a0dcef4f
+ 92b45cf7febdbe8f.2f957eab9b108881.3bdb40cb2a6dd225.2a4e66c605c03196
+ 498779541b5d383f.15aaf67d653d6fb8.2df0cad02297e335.0e4683a435fe703a
+ 518eb735f915aff1.24917fe7384e36b5.01d338e14cd19431.6d6b3564a0dcef4f
+ 2387f6f262636b00
+VMINPS_128(mem)
+ before
+ 0c67443b98a1a07a.0416110534706050.381697d5314f97a5.13d1856c45aa21c4
+ 04d799295ea249e8.c06b863067fb8709.2c04ba336b4c4eb4.bf36addca8abc59b
+ e7a373aacf702477.dfd80f212e415fc8.de2962ed0352190d.614eac9d1262bd61
+ 91964ea90719eb53.bfabaa4726ce2638.294f0def146db2dd.55647e1b1e5a45c3
+ f7c620c2691f996d
+ after
+ 0c67443b98a1a07a.0416110534706050.381697d5314f97a5.13d1856c45aa21c4
+ 04d799295ea249e8.c06b863067fb8709.2c04ba336b4c4eb4.bf36addca8abc59b
+ 0000000000000000.0000000000000000.2c04ba33314f97a5.bf36addca8abc59b
+ 91964ea90719eb53.bfabaa4726ce2638.294f0def146db2dd.55647e1b1e5a45c3
+ f7c620c2691f996d
+
+VSHUFPS_0x39_128(reg)
+ before
+ a3be8dfe8e3ef40a.de7ea41223a95aa7.ba2e510beb2f1506.e9433625bba7d64f
+ b599c13c2a429347.a925f3d03e2a2fa0.2eaf02da17ef6bde.fad1597b130e4090
+ 89a3b8e6d8b8b1cf.d058b6d175aa2469.7578b920499a626b.38c5f2de39aeadcb
+ 7b286f69342b8c4f.2ee36901e435f62f.ecd6704a1bbd375a.7eea7e384891d92e
+ aa0e77775cc580e2
+ after
+ 0000000000000000.0000000000000000.4891d92eecd6704a.17ef6bdefad1597b
+ b599c13c2a429347.a925f3d03e2a2fa0.2eaf02da17ef6bde.fad1597b130e4090
+ 89a3b8e6d8b8b1cf.d058b6d175aa2469.7578b920499a626b.38c5f2de39aeadcb
+ 7b286f69342b8c4f.2ee36901e435f62f.ecd6704a1bbd375a.7eea7e384891d92e
+ aa0e77775cc580e2
+VSHUFPS_0x39_128(mem)
+ before
+ 97fb5b8692565d16.e774e132db275e73.9e92884aa5d5601d.f01425c229e32656
+ 207ea551064f2ef4.28d20aac693864e6.fe319099d7981f60.db80d3f610986b0c
+ 2363d2c4d3bcaca8.9c90e64279ebd955.298bfcda938aef24.0a6476516b694127
+ 7a765ccb15a9965f.9ef87162a7cbfb6b.fa6e48faf7b68c94.d90e0a3fd6e1e554
+ a5c88c2bef8c923f
+ after
+ 97fb5b8692565d16.e774e132db275e73.9e92884aa5d5601d.f01425c229e32656
+ 207ea551064f2ef4.28d20aac693864e6.fe319099d7981f60.db80d3f610986b0c
+ 0000000000000000.0000000000000000.9e92884a29e32656.db80d3f6d7981f60
+ 7a765ccb15a9965f.9ef87162a7cbfb6b.fa6e48faf7b68c94.d90e0a3fd6e1e554
+ a5c88c2bef8c923f
+
+VSHUFPS_0x39_128(reg)
+ before
+ c8dff6834ff78693.0382c152e923a645.8957a877906503d5.4fa4f0e31f28b1dd
+ 9f9f46b394adfbfd.98557c456a359985.bbf986edcf44303e.02fa708326ec1c2b
+ 865378255a3a2d28.17b90a90b5eb2b4c.8f2a073101f4bd53.f13c45c5290f86a9
+ d94986463c2b5ac1.5a7be520e55217c5.603527adc201e5c0.f636ea95439cae84
+ efb3dbdf909f4ee7
+ after
+ 0000000000000000.0000000000000000.439cae84603527ad.cf44303e02fa7083
+ 9f9f46b394adfbfd.98557c456a359985.bbf986edcf44303e.02fa708326ec1c2b
+ 865378255a3a2d28.17b90a90b5eb2b4c.8f2a073101f4bd53.f13c45c5290f86a9
+ d94986463c2b5ac1.5a7be520e55217c5.603527adc201e5c0.f636ea95439cae84
+ efb3dbdf909f4ee7
+VSHUFPS_0x39_128(mem)
+ before
+ b681948f2d2523ff.f4cb6e82d60bbc74.3f678bdf17751b1e.8c68e3ceacf8e530
+ 286a92913639e9f7.33262b46c56790ec.a04977bb6661f080.6d0d36015e65f850
+ 223b50d1c6e85cfc.f2a6b9fca5c912d6.5aed259eef215519.61711cb071d25bcc
+ 7ec04a3bf93d373a.8d97141211bf7ddd.4a1e1176cdc10415.c2e0914983cd4a4f
+ eea6913630e20186
+ after
+ b681948f2d2523ff.f4cb6e82d60bbc74.3f678bdf17751b1e.8c68e3ceacf8e530
+ 286a92913639e9f7.33262b46c56790ec.a04977bb6661f080.6d0d36015e65f850
+ 0000000000000000.0000000000000000.3f678bdfacf8e530.6d0d36016661f080
+ 7ec04a3bf93d373a.8d97141211bf7ddd.4a1e1176cdc10415.c2e0914983cd4a4f
+ eea6913630e20186
+
+VSHUFPS_0x39_128(reg)
+ before
+ 3f0e19e5139bbc1c.19c5fcbcec4437dc.604538f3a5d50eae.4aaab82e1d4dbaa0
+ 126624c1c986b6be.d016e23eba09170f.c7fb220bfe9601f5.375b95b2fad233e5
+ c4f8ae36ed2e2c17.7d7e79af809995fe.1e07cdc6b78e925d.eefe24ee815b2b10
+ af11b3b01b2059d4.fdcb3cfa59ff6bd6.c0b335906d49fc92.495fe1cecdf55d4f
+ 254a483efaab86cb
+ after
+ 0000000000000000.0000000000000000.cdf55d4fc0b33590.fe9601f5375b95b2
+ 126624c1c986b6be.d016e23eba09170f.c7fb220bfe9601f5.375b95b2fad233e5
+ c4f8ae36ed2e2c17.7d7e79af809995fe.1e07cdc6b78e925d.eefe24ee815b2b10
+ af11b3b01b2059d4.fdcb3cfa59ff6bd6.c0b335906d49fc92.495fe1cecdf55d4f
+ 254a483efaab86cb
+VSHUFPS_0x39_128(mem)
+ before
+ 5e8ad62b258961b3.30fd309bf0e77ba1.2cc7a70a624855c3.0b4c57d5bb547c42
+ d0ed067f6a9bac31.a3081f64080fcc29.e63f36cdb67f11f0.5a1e2d013e3a4d17
+ 573d5428e3ee2171.657e7e75fe258819.07ff662e72b0598a.0975b5809188adbd
+ cf473c10af8e7ca1.d0ab483b6eb4ed1c.6bd2b119b1e8eabc.739deabf51c9d6e1
+ f6e1c8281989052f
+ after
+ 5e8ad62b258961b3.30fd309bf0e77ba1.2cc7a70a624855c3.0b4c57d5bb547c42
+ d0ed067f6a9bac31.a3081f64080fcc29.e63f36cdb67f11f0.5a1e2d013e3a4d17
+ 0000000000000000.0000000000000000.2cc7a70abb547c42.5a1e2d01b67f11f0
+ cf473c10af8e7ca1.d0ab483b6eb4ed1c.6bd2b119b1e8eabc.739deabf51c9d6e1
+ f6e1c8281989052f
+
+VPCMPEQB_128(reg)
+ before
+ ed8e4c2986557552.14d73b25e8857bea.41da7a23f54935df.ee86957a903280b3
+ b3f1712d33b764f7.02b9cc52aae1d87b.14580e982e6e9d0e.6ce58d3e2a9ad69b
+ a654339fbc3e0cca.75b96b8312ad507e.a5710205b6b16154.c1bd164f9b2da99f
+ 20038eedbe73a976.49a294a43bf69f1f.507151d8289ebc5e.c9d8aa9a01f5b5ec
+ 6003c70c7501b5ad
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ b3f1712d33b764f7.02b9cc52aae1d87b.14580e982e6e9d0e.6ce58d3e2a9ad69b
+ a654339fbc3e0cca.75b96b8312ad507e.a5710205b6b16154.c1bd164f9b2da99f
+ 20038eedbe73a976.49a294a43bf69f1f.507151d8289ebc5e.c9d8aa9a01f5b5ec
+ 6003c70c7501b5ad
+VPCMPEQB_128(mem)
+ before
+ 6209e890155a670f.7f4c7e82d5e479a8.5a42c3a142c7808c.71a4f77c21c0ebd7
+ abb88a11fc0e853e.1d7a00ca9c1db60b.84637566422cb0ee.6456f15d3ca32a6c
+ 17da277d4729cb65.58d80e32afa89d4c.a3d225df5832eb74.85d23ae716d3b4c9
+ 813d3dbf12b5f7b1.8ab3a624ab136916.925b4ff99fe4ed48.3065ce874addc799
+ c15ba9a7754c9c89
+ after
+ 6209e890155a670f.7f4c7e82d5e479a8.5a42c3a142c7808c.71a4f77c21c0ebd7
+ abb88a11fc0e853e.1d7a00ca9c1db60b.84637566422cb0ee.6456f15d3ca32a6c
+ 0000000000000000.0000000000000000.00000000ff000000.0000000000000000
+ 813d3dbf12b5f7b1.8ab3a624ab136916.925b4ff99fe4ed48.3065ce874addc799
+ c15ba9a7754c9c89
+
+VPCMPEQB_128(reg)
+ before
+ 9400c7b432ad7244.c7ab47c377c0c34d.1057c40d2be95816.2fca6f9e334e7196
+ 05a0251b1d8a8477.c4f1c1759556ec66.4710625accb7a4f8.55ea02bc317d348b
+ 6f87bd46d3720dce.53db27c186812d28.892a7e7529088967.e089833db57cf153
+ 30018da3f0ee49f4.5234f694665043be.33f113ccdf684510.ab716e0fda576619
+ 946f3f1dbc1b4d0a
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 05a0251b1d8a8477.c4f1c1759556ec66.4710625accb7a4f8.55ea02bc317d348b
+ 6f87bd46d3720dce.53db27c186812d28.892a7e7529088967.e089833db57cf153
+ 30018da3f0ee49f4.5234f694665043be.33f113ccdf684510.ab716e0fda576619
+ 946f3f1dbc1b4d0a
+VPCMPEQB_128(mem)
+ before
+ 754f725378d36352.a359919d0f8c7696.9ccaa8d851ccea54.a2b01dca8964129f
+ 2cdd849d2a8c631c.24dcc3a0ccd7ce5f.0c67bb7a6503de18.30b498dac4872dbf
+ 94e4f0e7ed500b95.0ed62118c45c8efc.80d9ab67bb00da34.3a4a816a2b5dd21c
+ 8832321ddd2e15e8.bf93a67192a6f218.d2eaf28a71cf9cd4.1cbbd2e55b733c63
+ 325689b7ef54a840
+ after
+ 754f725378d36352.a359919d0f8c7696.9ccaa8d851ccea54.a2b01dca8964129f
+ 2cdd849d2a8c631c.24dcc3a0ccd7ce5f.0c67bb7a6503de18.30b498dac4872dbf
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 8832321ddd2e15e8.bf93a67192a6f218.d2eaf28a71cf9cd4.1cbbd2e55b733c63
+ 325689b7ef54a840
+
+VPCMPEQB_128(reg)
+ before
+ d866a24d838d525f.e591c62b172f3d42.915f4e17d3413560.e0670ecea37ddd25
+ 6a361711b4a8756b.88ce28feb66141ce.e285157623b99480.841b7a216c155c53
+ 4414e6701e344e10.4bb5d580d7cfdbb9.0d53f8fa1c9b4b23.9cd4b26ee9a4d389
+ c24a0ad75cba19fb.0c12489f9585c82f.6d13f1105d7396f6.025c32a13534fff4
+ 948177a66cd39cbf
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 6a361711b4a8756b.88ce28feb66141ce.e285157623b99480.841b7a216c155c53
+ 4414e6701e344e10.4bb5d580d7cfdbb9.0d53f8fa1c9b4b23.9cd4b26ee9a4d389
+ c24a0ad75cba19fb.0c12489f9585c82f.6d13f1105d7396f6.025c32a13534fff4
+ 948177a66cd39cbf
+VPCMPEQB_128(mem)
+ before
+ 2c0dfb6aab8d6618.40257fb00ac812d8.a5b1fd450d90c35b.6012fe227fcbb0a5
+ a7cd3cd70d6d1828.1af14169c5e97453.f35e71605afb8a6a.409c1a9e2031d6db
+ e18db6daaf7f6f1d.acfa4d6d29a97c16.d3e41edb99d3d787.6afd42efdc304445
+ b718e360adcf2623.528b9d28d09566d0.1f1082a2e52367df.3b8170814e55358e
+ 0d73a2bf132be763
+ after
+ 2c0dfb6aab8d6618.40257fb00ac812d8.a5b1fd450d90c35b.6012fe227fcbb0a5
+ a7cd3cd70d6d1828.1af14169c5e97453.f35e71605afb8a6a.409c1a9e2031d6db
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ b718e360adcf2623.528b9d28d09566d0.1f1082a2e52367df.3b8170814e55358e
+ 0d73a2bf132be763
+
+VMOVHPD_128_StoreForm(reg)
+ before
+ 3e20d317c63e936f.033c4153216afb66.68f22f0659386e2b.b4ae18a15af7f59e
+ 28d500f5031b785f.a2c34ba12a5ca811.4a79fe735d1fcfd4.6e8a5cc4155b3eef
+ 28dc23c3674dd0df.707a7d35e1afe950.536d07db7bd5c676.2970cbf7325cfeff
+ 9a823aee8e60d89a.492d53fb65717c51.e11a44aa4ce68fbe.c22cdf27cc06f1fa
+ 1389163eff63d20b
+ after
+ 3e20d317c63e936f.033c4153216afb66.68f22f0659386e2b.b4ae18a15af7f59e
+ 28d500f5031b785f.a2c34ba12a5ca811.4a79fe735d1fcfd4.6e8a5cc4155b3eef
+ 28dc23c3674dd0df.707a7d35e1afe950.536d07db7bd5c676.2970cbf7325cfeff
+ 9a823aee8e60d89a.492d53fb65717c51.e11a44aa4ce68fbe.c22cdf27cc06f1fa
+ 1389163eff63d20b
+VMOVHPD_128_StoreForm(mem)
+ before
+ f954eb2ae8815e5e.da1240e213e1cc3d.09a849dfcfad1b3d.4fccb34c6fde6558
+ 5059dbd5a36b5120.45da310c925be873.8cb7dccd3d708343.f9ce4f2e7d4a85ef
+ f464602d4a2e667d.352409d6a85b67e9.ae2587b1cbc5708d.3a6e15ba14b52b30
+ c141f81dfcd55ba1.073dc5aef06b864b.4bc0c67794b89d47.70f6ff5ed0ac93c6
+ f5b30b854cbaf85e
+ after
+ f954eb2ae8815e5e.da1240e213e1cc3d.09a849dfcfad1b3d.8cb7dccd3d708343
+ 5059dbd5a36b5120.45da310c925be873.8cb7dccd3d708343.f9ce4f2e7d4a85ef
+ f464602d4a2e667d.352409d6a85b67e9.ae2587b1cbc5708d.3a6e15ba14b52b30
+ c141f81dfcd55ba1.073dc5aef06b864b.4bc0c67794b89d47.70f6ff5ed0ac93c6
+ f5b30b854cbaf85e
+
+VMOVHPD_128_StoreForm(reg)
+ before
+ 27f1349a256b97a3.93bc1e91d26ceab7.177260ff07198044.3f52160cb556c79e
+ 61fc760bf64cac42.46a04e75eb00cfeb.c10cd63588f19381.66a8f15a49aaaabe
+ fe20cd435be872e7.b5bb05b5609cc86a.615a23bc107ef9ad.9c8ed54f6cc001d3
+ 5ba836aef1cb263d.bed7bd3d504c8f60.53a744003a4cef75.bdd03dd53ba58a08
+ a53aa5dad264ff89
+ after
+ 27f1349a256b97a3.93bc1e91d26ceab7.177260ff07198044.3f52160cb556c79e
+ 61fc760bf64cac42.46a04e75eb00cfeb.c10cd63588f19381.66a8f15a49aaaabe
+ fe20cd435be872e7.b5bb05b5609cc86a.615a23bc107ef9ad.9c8ed54f6cc001d3
+ 5ba836aef1cb263d.bed7bd3d504c8f60.53a744003a4cef75.bdd03dd53ba58a08
+ a53aa5dad264ff89
+VMOVHPD_128_StoreForm(mem)
+ before
+ 30978a494b091c83.d5e2acb8538204f1.3cc1f4f9d41de1f8.f33e336da3e7b085
+ 39b4670ec5a19f22.c6182bce1e9848af.0b4525d60a1a795f.9d6dee6fe6dc7988
+ 9e5db7155a374291.8c97af5aee992d22.072fcdbe0e4f14c1.ad7e7072a0b6862b
+ 3a5ef94a26d7c2fd.81ab34c95d11f0f6.0b4a669ffbc96e49.7fbeb6e36c011319
+ 6e79ba2ce64a5bff
+ after
+ 30978a494b091c83.d5e2acb8538204f1.3cc1f4f9d41de1f8.0b4525d60a1a795f
+ 39b4670ec5a19f22.c6182bce1e9848af.0b4525d60a1a795f.9d6dee6fe6dc7988
+ 9e5db7155a374291.8c97af5aee992d22.072fcdbe0e4f14c1.ad7e7072a0b6862b
+ 3a5ef94a26d7c2fd.81ab34c95d11f0f6.0b4a669ffbc96e49.7fbeb6e36c011319
+ 6e79ba2ce64a5bff
+
+VMOVHPD_128_StoreForm(reg)
+ before
+ d8fa7abbab1c9b89.e983a699468eda92.02a0b7880a8dcdd9.f5646e63ee934324
+ 188ff1fa57040f62.86983ceed567477b.6cc133028e99ff75.a04760f802b94e7d
+ 8a821b57858df337.ef693536f06ec5e5.195ca4a288bfc376.e7c0b84953484d81
+ 8920f53dd14382b3.fec10f5bb2b010fb.66bb06d6918e5589.a89bf342fe4bf95b
+ bea48bcf1ece1139
+ after
+ d8fa7abbab1c9b89.e983a699468eda92.02a0b7880a8dcdd9.f5646e63ee934324
+ 188ff1fa57040f62.86983ceed567477b.6cc133028e99ff75.a04760f802b94e7d
+ 8a821b57858df337.ef693536f06ec5e5.195ca4a288bfc376.e7c0b84953484d81
+ 8920f53dd14382b3.fec10f5bb2b010fb.66bb06d6918e5589.a89bf342fe4bf95b
+ bea48bcf1ece1139
+VMOVHPD_128_StoreForm(mem)
+ before
+ 04a6fedcd0de4f44.73b57918d8b3f983.916d464b3838e3ea.af2b5609478ff15a
+ 586fc755308670ab.a38da55435679452.823954f09d12fcdd.50f88fa74650d294
+ 94c9622659d33097.74f4745d85ee8ecd.aff1b738fd4b1401.a56ead1c295c35e4
+ 95814c3c67cf4a37.4436e39f63d124a0.f261ea0e75eeea82.0bd9acd48d3f56f5
+ dc84883c0d867074
+ after
+ 04a6fedcd0de4f44.73b57918d8b3f983.916d464b3838e3ea.823954f09d12fcdd
+ 586fc755308670ab.a38da55435679452.823954f09d12fcdd.50f88fa74650d294
+ 94c9622659d33097.74f4745d85ee8ecd.aff1b738fd4b1401.a56ead1c295c35e4
+ 95814c3c67cf4a37.4436e39f63d124a0.f261ea0e75eeea82.0bd9acd48d3f56f5
+ dc84883c0d867074
+
+VPAND_128(reg)
+ before
+ 75bd3ebe45bcc10d.3863008177897cb5.6d9eec876c9e9276.2954695e2108388b
+ 32cec9c8d26d836b.573bfae3a40a7f3e.4d798d7f3be014fc.2e98b0141ca3bb49
+ 6f0425c45026f23b.d0d5b64d0b6012fd.3e13c1f56d24e5de.dff73c1c82ce2fe8
+ 88ab4e205a724c28.7dfdb0aac796ef1f.9eb884539df542c7.163e876270925093
+ b0390fd302fdd976
+ after
+ 0000000000000000.0000000000000000.0c38845319e000c4.0618800010821001
+ 32cec9c8d26d836b.573bfae3a40a7f3e.4d798d7f3be014fc.2e98b0141ca3bb49
+ 6f0425c45026f23b.d0d5b64d0b6012fd.3e13c1f56d24e5de.dff73c1c82ce2fe8
+ 88ab4e205a724c28.7dfdb0aac796ef1f.9eb884539df542c7.163e876270925093
+ b0390fd302fdd976
+VPAND_128(mem)
+ before
+ 89b44f59521a87bf.d80e41478cdecbdf.3b7e65e8f4b8d3cf.c7b4d20768df6764
+ 7e7bc4e17ff61597.bd7bf8a483f5ab0c.e6254ff2afd37a3a.1753a87c696f8f60
+ 6959e958a39c412d.923c71a5da432a5a.5bbeecb414f3a08c.e8e0011e3d30f768
+ 271c39a9da18c5ab.b39fa8b52e548275.7415b81a3e2200f0.97a9d9597faedb27
+ 81f82c99cb76774a
+ after
+ 89b44f59521a87bf.d80e41478cdecbdf.3b7e65e8f4b8d3cf.c7b4d20768df6764
+ 7e7bc4e17ff61597.bd7bf8a483f5ab0c.e6254ff2afd37a3a.1753a87c696f8f60
+ 0000000000000000.0000000000000000.222445e0a490520a.07108004684f0760
+ 271c39a9da18c5ab.b39fa8b52e548275.7415b81a3e2200f0.97a9d9597faedb27
+ 81f82c99cb76774a
+
+VPAND_128(reg)
+ before
+ 001af74abe13067d.948e32bf41765d3e.7cee97411ab5f00b.0ef62d114a6e5793
+ 715b35d8f411c56b.8c7c5088f3c3c711.48763cb33bf1b0c6.052dc98352e260a0
+ 3007e1b008fdf0c1.ebb20def0c0abd51.758391782c95fd52.3585075d758bd944
+ 9969fa3c9662c22a.8dfbe7e0aa58fc29.5e6094fd8a2c145c.7acb638ccd747cab
+ b0cb59fa76a90500
+ after
+ 0000000000000000.0000000000000000.486014b10a201044.00094180406060a0
+ 715b35d8f411c56b.8c7c5088f3c3c711.48763cb33bf1b0c6.052dc98352e260a0
+ 3007e1b008fdf0c1.ebb20def0c0abd51.758391782c95fd52.3585075d758bd944
+ 9969fa3c9662c22a.8dfbe7e0aa58fc29.5e6094fd8a2c145c.7acb638ccd747cab
+ b0cb59fa76a90500
+VPAND_128(mem)
+ before
+ b35166958d373270.09ce79ea3bcc7953.4e255948e6b840c6.5f5b41acf0423190
+ 5f2905482d28bd26.da835c2492c84ee8.0afadf11de364453.d3be92f3fa639099
+ 901fb2ff738b634f.69d29d5838e18094.9d48f628aedfc5fe.18d6853c451c6c24
+ 22fee9a67a69e017.12083af1c8a44904.e3d9187a71be7ff0.88ef15f56df902dd
+ 81553e890d848e6f
+ after
+ b35166958d373270.09ce79ea3bcc7953.4e255948e6b840c6.5f5b41acf0423190
+ 5f2905482d28bd26.da835c2492c84ee8.0afadf11de364453.d3be92f3fa639099
+ 0000000000000000.0000000000000000.0a205900c6304042.531a00a0f0421090
+ 22fee9a67a69e017.12083af1c8a44904.e3d9187a71be7ff0.88ef15f56df902dd
+ 81553e890d848e6f
+
+VPAND_128(reg)
+ before
+ 5d54fc64c14b4b87.f19426295fd0efa9.31702f5bdf9be7e3.b87ac3f143df2d58
+ 7a374cf226d976d0.d9abe6743dcc4d32.22587602185593de.f8f6727b414f8d60
+ 324c299fd8bb4bf7.b610a4733167b6dd.410b0d52105b8ca1.7f1ba10287195934
+ e3dd8fd8727c06a7.638fdc1356afe6d7.ead4efb7623b0cd7.29b4cd7430494d01
+ d18c70bc58ec27f3
+ after
+ 0000000000000000.0000000000000000.22506602001100d6.28b4407000490d00
+ 7a374cf226d976d0.d9abe6743dcc4d32.22587602185593de.f8f6727b414f8d60
+ 324c299fd8bb4bf7.b610a4733167b6dd.410b0d52105b8ca1.7f1ba10287195934
+ e3dd8fd8727c06a7.638fdc1356afe6d7.ead4efb7623b0cd7.29b4cd7430494d01
+ d18c70bc58ec27f3
+VPAND_128(mem)
+ before
+ 557008c61c0da136.e7377a0790a8e28d.bef40a3ec9b0984c.7900189eab80502d
+ 902c107e97b878f4.9ba6e699cfcc1c55.a20aabe2a5748967.49db847186b6944e
+ 5e8c05d0e6fa675c.5c76d0fbca73f0aa.eb9f39e906097454.b8b1309d8f6a13e7
+ 9a5c61a924de2b98.84f233971e299939.747d3241097b1741.21ce178f63270aa4
+ e07d35b29e7ab530
+ after
+ 557008c61c0da136.e7377a0790a8e28d.bef40a3ec9b0984c.7900189eab80502d
+ 902c107e97b878f4.9ba6e699cfcc1c55.a20aabe2a5748967.49db847186b6944e
+ 0000000000000000.0000000000000000.a2000a2281308844.490000108280100c
+ 9a5c61a924de2b98.84f233971e299939.747d3241097b1741.21ce178f63270aa4
+ e07d35b29e7ab530
+
+VPMOVMSKB_128(reg)
+ before
+ 500b8671dbee4f37.2267a2f36e7080d5.70680bdb667b54ad.1b7112d5cad52c58
+ cfc5063ab60f1667.d07a439cdfbd223e.7c2254323ff45db3.bb475391642370c5
+ b8f5b278cc69446a.8262c08e94d0cc00.056d0b084420f0f7.2fcb7361f3719eb5
+ 66e88597b88915ec.12e996b7a8b53c47.65952bc9128c4824.55c8ec3194cc7454
+ 070c3ced623faccd
+ after
+ 500b8671dbee4f37.2267a2f36e7080d5.70680bdb667b54ad.1b7112d5cad52c58
+ cfc5063ab60f1667.d07a439cdfbd223e.7c2254323ff45db3.bb475391642370c5
+ b8f5b278cc69446a.8262c08e94d0cc00.056d0b084420f0f7.2fcb7361f3719eb5
+ 66e88597b88915ec.12e996b7a8b53c47.65952bc9128c4824.55c8ec3194cc7454
+ 0000000000000591
+VPMOVMSKB_128(mem)
+ before
+ 2361df827ad6024d.37e97b0417fbc79a.5edc400237792b3e.f9e6b0e144c3a2e7
+ 83944fdaf89e3400.8646902984499420.4006395a5e275811.1dac96bc76513aec
+ 04710ae2f6a2fc11.ae49c1739c01b929.963500ad39cc7dee.2d32d9c745c34cde
+ 83c48b8792ef17ac.0d40094ffaae7162.3a330ee6e37357fe.85c5766c4da41369
+ 81b268182981cc3a
+ after
+ 2361df827ad6024d.37e97b0417fbc79a.5edc400237792b3e.f9e6b0e144c3a2e7
+ 83944fdaf89e3400.8646902984499420.4006395a5e275811.1dac96bc76513aec
+ 04710ae2f6a2fc11.ae49c1739c01b929.963500ad39cc7dee.2d32d9c745c34cde
+ 83c48b8792ef17ac.0d40094ffaae7162.3a330ee6e37357fe.85c5766c4da41369
+ 81b268182981cc3a
+
+VPMOVMSKB_128(reg)
+ before
+ 7d43ab3875e5b2fd.da594eb4e88f40ff.fd7563273bddfa77.0acee0f27828a270
+ d5c53b37ce5c035d.e6fccf5413913533.dc35ce69fa198e13.e0d0f3bb15f71a6e
+ e5831580cf72f907.84788b5530feb077.04cc437fd4ee69e2.9906c22ed6ed7a25
+ 09cb338115b4d1a7.8e9afda25ae46ef5.d285c0d764e9c992.123cc937d6157fc0
+ 253d85c3317ce46c
+ after
+ 7d43ab3875e5b2fd.da594eb4e88f40ff.fd7563273bddfa77.0acee0f27828a270
+ d5c53b37ce5c035d.e6fccf5413913533.dc35ce69fa198e13.e0d0f3bb15f71a6e
+ e5831580cf72f907.84788b5530feb077.04cc437fd4ee69e2.9906c22ed6ed7a25
+ 09cb338115b4d1a7.8e9afda25ae46ef5.d285c0d764e9c992.123cc937d6157fc0
+ 000000000000aaf4
+VPMOVMSKB_128(mem)
+ before
+ afd770bd042d6754.9ce793a53cadc6e8.e12ea127ae4e2ada.a3ae40dc4795e8cd
+ 8cd408106a34c2a5.fc243158deea1577.5900f3d04749a151.d191bffa187e033f
+ 9801c8aa809db18b.84cf07069af5faff.d3dc708a41e08f87.b97b399d73315595
+ af2a2d766175f231.9032131c095db12d.298e923fb91fb0a7.b8b8aa31f5391c7b
+ 28940f233a22929c
+ after
+ afd770bd042d6754.9ce793a53cadc6e8.e12ea127ae4e2ada.a3ae40dc4795e8cd
+ 8cd408106a34c2a5.fc243158deea1577.5900f3d04749a151.d191bffa187e033f
+ 9801c8aa809db18b.84cf07069af5faff.d3dc708a41e08f87.b97b399d73315595
+ af2a2d766175f231.9032131c095db12d.298e923fb91fb0a7.b8b8aa31f5391c7b
+ 28940f233a22929c
+
+VPMOVMSKB_128(reg)
+ before
+ 665b63dddc79f4a5.ad1bb1602ac83fc4.7c994f04c9ab76ad.38e1d7dccb12bfde
+ ce58a2cc7ac97d41.6fa0d254f6a0556f.a352ba2b766d842a.dca2ba4e92c67958
+ bcd9c95dae9e6a1d.cf840b3ee10bf05f.63a74dfeab2e1751.f19db8802a479a40
+ 8d28d2fb1485f7e5.aa95d80a0814cbc0.16e605e7057b6dcd.539e4b5db09fddc3
+ de71f1d33fdc000c
+ after
+ 665b63dddc79f4a5.ad1bb1602ac83fc4.7c994f04c9ab76ad.38e1d7dccb12bfde
+ ce58a2cc7ac97d41.6fa0d254f6a0556f.a352ba2b766d842a.dca2ba4e92c67958
+ bcd9c95dae9e6a1d.cf840b3ee10bf05f.63a74dfeab2e1751.f19db8802a479a40
+ 8d28d2fb1485f7e5.aa95d80a0814cbc0.16e605e7057b6dcd.539e4b5db09fddc3
+ 000000000000a2ec
+VPMOVMSKB_128(mem)
+ before
+ 6ee225cdf409bd48.9b92bb1149096044.db9db5a587c8a3bd.1a59df541fdfc04b
+ dfbc6337ea33d0a3.43637f0de8b7e0e7.40691ff979323483.ca4dd6b095e64d76
+ 0dcd28fd3e65f748.e1e71a5a8e19b479.b4c591f4fb5e393d.810ee667041d50fb
+ d3dfee0b0babec63.d1698964d6bd18a7.137d878027597018.9de70be5080e0486
+ 782642963c48a7c2
+ after
+ 6ee225cdf409bd48.9b92bb1149096044.db9db5a587c8a3bd.1a59df541fdfc04b
+ dfbc6337ea33d0a3.43637f0de8b7e0e7.40691ff979323483.ca4dd6b095e64d76
+ 0dcd28fd3e65f748.e1e71a5a8e19b479.b4c591f4fb5e393d.810ee667041d50fb
+ d3dfee0b0babec63.d1698964d6bd18a7.137d878027597018.9de70be5080e0486
+ 782642963c48a7c2
+
+VCVTTSS2SI_64(reg)
+ before
+ 701586e63c54725c.0fbf334d6e126c22.6f37c6975d2f481d.395d7d8b1c2e9340
+ df02d341a5c0a400.9c3972b082a532af.169bcf60befa7f86.0230f000f4e95ee0
+ 2237251412187759.5619271e6370fb36.24e2a02995aafa8f.4ac35acbcb978f24
+ 960179c920e62813.192acf852e8083e4.f458335f80cbf4e3.ece239d8be43e03a
+ c6590813e8f90e4c
+ after
+ 701586e63c54725c.0fbf334d6e126c22.6f37c6975d2f481d.395d7d8b1c2e9340
+ df02d341a5c0a400.9c3972b082a532af.169bcf60befa7f86.0230f000f4e95ee0
+ 2237251412187759.5619271e6370fb36.24e2a02995aafa8f.4ac35acbcb978f24
+ 960179c920e62813.192acf852e8083e4.f458335f80cbf4e3.ece239d8be43e03a
+ 8000000000000000
+VCVTTSS2SI_64(mem)
+ before
+ b3f4446866c6d486.95abc9ce6bb8f3dc.c03ae5cfffe086e5.e249856f18eaab2f
+ 8e7f67c353b5ef15.7c83138d8d1a145d.2913e5eaf19cbf64.4a0193c3fb92591f
+ 35c6ef11ccd21b25.a7d352742596c645.2e824bc120c1eb8e.88cb58c9c5503b5e
+ 8294573cec2a14e1.73e983eeccba463e.ad539340a95ac68f.f7f5d0ec11af8c98
+ f5c9f8987b3b897b
+ after
+ b3f4446866c6d486.95abc9ce6bb8f3dc.c03ae5cfffe086e5.e249856f18eaab2f
+ 8e7f67c353b5ef15.7c83138d8d1a145d.2913e5eaf19cbf64.4a0193c3fb92591f
+ 35c6ef11ccd21b25.a7d352742596c645.2e824bc120c1eb8e.88cb58c9c5503b5e
+ 8294573cec2a14e1.73e983eeccba463e.ad539340a95ac68f.f7f5d0ec11af8c98
+ 0000000000000000
+
+VCVTTSS2SI_64(reg)
+ before
+ dd94cb39a0806eb1.53b61b32d0c89576.3a0fa0672012cff5.81523a53a8740c92
+ 0aa2443b1b0b77e6.83f8b8dd93b95c10.5992a74bbd289f15.854abbe6381978c4
+ da3f620a8967e0c7.ed26a82b520722da.2cbe93063e8af04b.970992e57557c750
+ a7b61e128521e400.6e0c690728c1a600.0fde600440c4fe42.91593b3d7c3ab563
+ 510733d868cdfd28
+ after
+ dd94cb39a0806eb1.53b61b32d0c89576.3a0fa0672012cff5.81523a53a8740c92
+ 0aa2443b1b0b77e6.83f8b8dd93b95c10.5992a74bbd289f15.854abbe6381978c4
+ da3f620a8967e0c7.ed26a82b520722da.2cbe93063e8af04b.970992e57557c750
+ a7b61e128521e400.6e0c690728c1a600.0fde600440c4fe42.91593b3d7c3ab563
+ 0000000000000000
+VCVTTSS2SI_64(mem)
+ before
+ b1dff4a3561c5ccc.cf5575bfacc4c03c.e375765d31f0a2b0.5e400ab15e6107a7
+ 8eadfc8b61338e7b.ad66647e99dcaf28.262f4c198aa2d314.752e8e7a34ed4526
+ c53dc67ba61f4f60.9c36e6b9e9f6ee70.150465274fe2f558.b0f5e7c95ff4f56a
+ 305bcf5f40eb5aa8.f911f7de379db9bf.8ac13f739bbcc4a9.6be1110c7b035320
+ 023e08ad22a59af3
+ after
+ b1dff4a3561c5ccc.cf5575bfacc4c03c.e375765d31f0a2b0.5e400ab15e6107a7
+ 8eadfc8b61338e7b.ad66647e99dcaf28.262f4c198aa2d314.752e8e7a34ed4526
+ c53dc67ba61f4f60.9c36e6b9e9f6ee70.150465274fe2f558.b0f5e7c95ff4f56a
+ 305bcf5f40eb5aa8.f911f7de379db9bf.8ac13f739bbcc4a9.6be1110c7b035320
+ 3841e9c000000000
+
+VCVTTSS2SI_64(reg)
+ before
+ d158c91af3670790.acd291224ca46c7f.21439458205d4cc1.623255ea8a3dfb33
+ 347b4fbe88d3d6a2.166f8ab2e5554110.6e17b7933fc3e324.7a23237639705721
+ 87f296057d7742d7.48fe35fa270a9587.3edb5efa315ab992.ac602605c36293a0
+ 260a9a5b6fdf89d8.1f4b0ee72fcf2311.ebd984fb91ae0bb7.d5b4d881451e6ddb
+ d1edb7d8dab09fff
+ after
+ d158c91af3670790.acd291224ca46c7f.21439458205d4cc1.623255ea8a3dfb33
+ 347b4fbe88d3d6a2.166f8ab2e5554110.6e17b7933fc3e324.7a23237639705721
+ 87f296057d7742d7.48fe35fa270a9587.3edb5efa315ab992.ac602605c36293a0
+ 260a9a5b6fdf89d8.1f4b0ee72fcf2311.ebd984fb91ae0bb7.d5b4d881451e6ddb
+ 0000000000000000
+VCVTTSS2SI_64(mem)
+ before
+ 7cd53ef59f25e538.6c0f572cf996e554.7722926319b1a8da.d25e2602fb4c1440
+ b239eac4af87fdb1.b74dcae4b82892f5.2c4f3c5b00bbdf0e.4fb63e790cbf12d9
+ 50e5353127e5a197.6210eef04722ce67.1a9d87bc00fa86d8.bf2dcacd60933f2d
+ 30a49d2822488e15.c8a4bfba430ed357.1dd9f27036795764.7c0fc56a9155d7e9
+ e3a82bbd3e9018b8
+ after
+ 7cd53ef59f25e538.6c0f572cf996e554.7722926319b1a8da.d25e2602fb4c1440
+ b239eac4af87fdb1.b74dcae4b82892f5.2c4f3c5b00bbdf0e.4fb63e790cbf12d9
+ 50e5353127e5a197.6210eef04722ce67.1a9d87bc00fa86d8.bf2dcacd60933f2d
+ 30a49d2822488e15.c8a4bfba430ed357.1dd9f27036795764.7c0fc56a9155d7e9
+ 8000000000000000
+
+VPACKUSWB_128(reg)
+ before
+ 5043f83001d03c47.2f449d95bdbe8058.475439b0477bde71.11cff665be440ee0
+ 1f2d293176a28042.298fb1641352328c.3a6e583ceff22a60.d24b1085b2686975
+ acb2b92b3a912054.fa535581401161dc.fc3c19ccd801f5d1.3c19bdbe31f02252
+ 531ea48ae829572a.7d5a06d96106c975.eb0b77cb9e337970.2b0578fb55e8f6a1
+ 7bdabd283a5da18e
+ after
+ 0000000000000000.0000000000000000.00ff00ffffffff00.ffff00ff00ff00ff
+ 1f2d293176a28042.298fb1641352328c.3a6e583ceff22a60.d24b1085b2686975
+ acb2b92b3a912054.fa535581401161dc.fc3c19ccd801f5d1.3c19bdbe31f02252
+ 531ea48ae829572a.7d5a06d96106c975.eb0b77cb9e337970.2b0578fb55e8f6a1
+ 7bdabd283a5da18e
+VPACKUSWB_128(mem)
+ before
+ 08660931fd5ade46.70bde6ba1df7626f.90713f56923d2582.61276ea5dc15f2e8
+ ae73d702b9eb6af5.5fdb7b2774867dd0.0e637ce6eec33330.bcdbfbc62e329ee5
+ 49cea2888a1d01c6.7cc3603d8a63e3f9.d3fe397491a3adab.5675189a3116b715
+ b543e9ad8dfb5fe6.23c29068fa19d295.bb0df2eb98e94f1e.8d3fc38d814e7a22
+ bb86f70bb96522b8
+ after
+ 08660931fd5ade46.70bde6ba1df7626f.90713f56923d2582.61276ea5dc15f2e8
+ ae73d702b9eb6af5.5fdb7b2774867dd0.0e637ce6eec33330.bcdbfbc62e329ee5
+ 0000000000000000.0000000000000000.00ff00ffffff0000.ffff00ff0000ff00
+ b543e9ad8dfb5fe6.23c29068fa19d295.bb0df2eb98e94f1e.8d3fc38d814e7a22
+ bb86f70bb96522b8
+
+VPACKUSWB_128(reg)
+ before
+ 3e96b08175e7ed84.cd9e255ede913f81.b025071460348351.a25b24391ea2d7b6
+ 70bbeb5952611532.6faad38898ec5ec2.7f36c1ae594035d8.63b54a4940d9ff9e
+ ae41a201eb5ed66d.76357016d81777d6.ec41bba081ca22d7.dce7e007199a8403
+ 5574d3e3dd6a6ee2.bd0977f3b91e48e8.5394f058735d88fa.e8bd6360c6f22110
+ 62034d3e63ec93f3
+ after
+ 0000000000000000.0000000000000000.ff00ff0000ff00ff.ff00ffffffffff00
+ 70bbeb5952611532.6faad38898ec5ec2.7f36c1ae594035d8.63b54a4940d9ff9e
+ ae41a201eb5ed66d.76357016d81777d6.ec41bba081ca22d7.dce7e007199a8403
+ 5574d3e3dd6a6ee2.bd0977f3b91e48e8.5394f058735d88fa.e8bd6360c6f22110
+ 62034d3e63ec93f3
+VPACKUSWB_128(mem)
+ before
+ 28841c8e0a9596d5.bf9f796dc312173c.22f3640d570e8b25.0f7a5c40cc86a0ec
+ 150d4b3dd9f7e6e5.490f910a3ae10e28.80bfb44fcff2fdb9.7e3efbc626d0a959
+ 046b5635ec203e4c.4f111526dd638e52.b239e1a53dd659cf.fb2dca5520c7ddef
+ d368ba645e1c5c39.2def032d4825d565.962c69fbbbc75d93.e193c35954f77958
+ 8ebce43e5eedb940
+ after
+ 28841c8e0a9596d5.bf9f796dc312173c.22f3640d570e8b25.0f7a5c40cc86a0ec
+ 150d4b3dd9f7e6e5.490f910a3ae10e28.80bfb44fcff2fdb9.7e3efbc626d0a959
+ 0000000000000000.0000000000000000.ffffff00ffff0000.00000000ff00ff00
+ d368ba645e1c5c39.2def032d4825d565.962c69fbbbc75d93.e193c35954f77958
+ 8ebce43e5eedb940
+
+VPACKUSWB_128(reg)
+ before
+ 5df42870db34d854.5cd1f1b54cf6f9d6.3ff5568b18b21d0e.0666c73d68d0c333
+ a9868b5b66591340.7d717914d1bad450.e1710aace996a3f8.e0b177585efe47d9
+ d0c00a6c9ce7a6af.1016cd6d0974a7d2.70ae1cfc565ea2d0.fedaf636b95ba7b1
+ 2ceca00d186acd4e.f28a6aac11312f89.46f786e8fc955742.3eadbfc596f59de8
+ 7af64eef10d8e6aa
+ after
+ 0000000000000000.0000000000000000.ff0000ffff000000.00ff000000ffffff
+ a9868b5b66591340.7d717914d1bad450.e1710aace996a3f8.e0b177585efe47d9
+ d0c00a6c9ce7a6af.1016cd6d0974a7d2.70ae1cfc565ea2d0.fedaf636b95ba7b1
+ 2ceca00d186acd4e.f28a6aac11312f89.46f786e8fc955742.3eadbfc596f59de8
+ 7af64eef10d8e6aa
+VPACKUSWB_128(mem)
+ before
+ 8f811fa2440f3d22.1b5749ac776fc3c9.009bcabd05fc28a0.c09946da76c8fef9
+ 5a1aaec94da6607d.f74d01b35481c5cb.14136b8c00e24e44.3ae057406081d3a2
+ b58c784f47a909e6.1e1ac4904c2c0f00.0bbfc8051eed5ca1.0f18b584574e11e8
+ 7da4f8224f25f58a.ea0a8faefafddc16.c26b5d157c2c0fe2.9d8d5d14f6bbf578
+ 3f8a4a5bda53bbfe
+ after
+ 8f811fa2440f3d22.1b5749ac776fc3c9.009bcabd05fc28a0.c09946da76c8fef9
+ 5a1aaec94da6607d.f74d01b35481c5cb.14136b8c00e24e44.3ae057406081d3a2
+ 0000000000000000.0000000000000000.9b00ffff00ffff00.ffffe2ffffffff00
+ 7da4f8224f25f58a.ea0a8faefafddc16.c26b5d157c2c0fe2.9d8d5d14f6bbf578
+ 3f8a4a5bda53bbfe
+
+VCVTSS2SD_128(reg)
+ before
+ 515d78c59ea29f25.8e2eaa2d8125df95.b8685d79fa7f69b7.13e2a7a635a82234
+ 2f50e3bedf34dc9a.c5f60a5df8b68432.e5822a5de93ef28f.dbf220a6666f53c2
+ 35b087b23896af08.fcc8949cd1e3a08e.cba2f2c663c7b34b.f66546ff2a8c5cba
+ bec9610d4653541c.1070c5d727b8efd4.c715b22003a5e797.4008949f9e0cf945
+ 95a78671ddfae891
+ after
+ 0000000000000000.0000000000000000.e5822a5de93ef28f.bbc19f28a0000000
+ 2f50e3bedf34dc9a.c5f60a5df8b68432.e5822a5de93ef28f.dbf220a6666f53c2
+ 35b087b23896af08.fcc8949cd1e3a08e.cba2f2c663c7b34b.f66546ff2a8c5cba
+ bec9610d4653541c.1070c5d727b8efd4.c715b22003a5e797.4008949f9e0cf945
+ 95a78671ddfae891
+VCVTSS2SD_128(mem)
+ before
+ d20e99610462e3ca.28e76c3ca4f80682.ddb918fb16422c31.362764d76564cb1e
+ d109485b2e50a71c.ce55a4a9ef1002e5.3f7009f2bb8c14d1.7223065826919b8d
+ 6f640f4b78d1f0b2.0b6105c2c22784f1.126114aa31a263df.d857930de2b7938f
+ 88ea6a1efdf179b8.3d558cf1bacac854.3258b60d9590d488.c40d08643462eed1
+ 92935fc7b81fe9ff
+ after
+ d20e99610462e3ca.28e76c3ca4f80682.ddb918fb16422c31.362764d76564cb1e
+ d109485b2e50a71c.ce55a4a9ef1002e5.3f7009f2bb8c14d1.7223065826919b8d
+ 0000000000000000.0000000000000000.3f7009f2bb8c14d1.44ac9963c0000000
+ 88ea6a1efdf179b8.3d558cf1bacac854.3258b60d9590d488.c40d08643462eed1
+ 92935fc7b81fe9ff
+
+VCVTSS2SD_128(reg)
+ before
+ 9e3396a40b79bfc4.f868d5bed9baff5b.bf7e33a4728309b8.7b216a09026325f7
+ 443aa866c8fcaecd.9aaacd18293a3ec7.ec28f84686e184c9.c988ac8995271059
+ e0f392798c35f0c5.4c7ccd19097df127.229fd643936d7434.f858f87969e651da
+ ceac4e49f2afc259.e9aa51ac948dd6a8.bb2fca0735b517a5.e45fcac59baea6a5
+ 69679f59468bc9e7
+ after
+ 0000000000000000.0000000000000000.ec28f84686e184c9.bb75d4d4a0000000
+ 443aa866c8fcaecd.9aaacd18293a3ec7.ec28f84686e184c9.c988ac8995271059
+ e0f392798c35f0c5.4c7ccd19097df127.229fd643936d7434.f858f87969e651da
+ ceac4e49f2afc259.e9aa51ac948dd6a8.bb2fca0735b517a5.e45fcac59baea6a5
+ 69679f59468bc9e7
+VCVTSS2SD_128(mem)
+ before
+ 623df222878777cb.6aafda4297f75f35.4d00d5bce678a776.1524cefe0745a7c7
+ adad3f0a79b06b7e.104a31d016970404.5449d5371c4920bc.8ac9e094a5a76147
+ 258302fe3912622c.1cc74f600b1eed73.da52ce08520dffa7.786bfb35ac6981d1
+ a68ab8ebe2b71800.ea73305c1315562d.bae83b1ba2cffe62.39561b4db7164210
+ 2ad63d49633be1b0
+ after
+ 623df222878777cb.6aafda4297f75f35.4d00d5bce678a776.1524cefe0745a7c7
+ adad3f0a79b06b7e.104a31d016970404.5449d5371c4920bc.8ac9e094a5a76147
+ 0000000000000000.0000000000000000.5449d5371c4920bc.38e8b4f8e0000000
+ a68ab8ebe2b71800.ea73305c1315562d.bae83b1ba2cffe62.39561b4db7164210
+ 2ad63d49633be1b0
+
+VCVTSS2SD_128(reg)
+ before
+ a8375b934b639a5f.0b90dbbc90ad4927.d69ad131ca0a7adf.d2d5985c2b9cda1a
+ 0dc573990c1aa8c6.325fe95c6000b0cc.3b872c4ccb889635.fde561b7067e4efb
+ b6cb80c641ed4894.f6c45eb96eba0a1c.77883f18b21ce6da.16e6131952831730
+ ff967f868767b673.328bb4bed5ea1342.e5e706001c50a67a.fba3296c28b7f1e5
+ 87e71f9da7249848
+ after
+ 0000000000000000.0000000000000000.3b872c4ccb889635.3d16fe3ca0000000
+ 0dc573990c1aa8c6.325fe95c6000b0cc.3b872c4ccb889635.fde561b7067e4efb
+ b6cb80c641ed4894.f6c45eb96eba0a1c.77883f18b21ce6da.16e6131952831730
+ ff967f868767b673.328bb4bed5ea1342.e5e706001c50a67a.fba3296c28b7f1e5
+ 87e71f9da7249848
+VCVTSS2SD_128(mem)
+ before
+ 957f7199e8d9c783.44726a4479142e0f.c4806957b199876b.e1f17b72a5b311c3
+ 03379b4b09df3cc2.e2ab3f6eb481eb16.866ff7701fd521c3.c6f39cd9e8ce645f
+ abdb1a9e2644b032.338df970d3392a31.5623ddf53aa99e75.f23664a1812fdbfa
+ 6b3769805a13e2ff.946494b472c9270f.0e6994d31f21baae.c009cf370d61b141
+ 8bb7d90527f123e0
+ after
+ 957f7199e8d9c783.44726a4479142e0f.c4806957b199876b.e1f17b72a5b311c3
+ 03379b4b09df3cc2.e2ab3f6eb481eb16.866ff7701fd521c3.c6f39cd9e8ce645f
+ 0000000000000000.0000000000000000.866ff7701fd521c3.bcb6623860000000
+ 6b3769805a13e2ff.946494b472c9270f.0e6994d31f21baae.c009cf370d61b141
+ 8bb7d90527f123e0
+
+VCVTSD2SS_128(reg)
+ before
+ b18b7f786c6a6d82.1d1704dcc1588c54.617b0da72fbb1d5a.8c0d99f4ea4a309a
+ 8cd2bbfd7758cbd4.9e46679e78206b5e.f6205eb5a39e4abe.aadc6946b52fbd64
+ 7ad98bfee5487882.cb910fb29b763b49.af9d854b6cfbe8e9.459f7fb39fdd1d38
+ d5eaebe951c5b137.7ec477054567b840.e83f7dd325603384.3a255729c15e0c44
+ 63396d9339c145b2
+ after
+ 0000000000000000.0000000000000000.f6205eb5a39e4abe.aadc6946112ab94e
+ 8cd2bbfd7758cbd4.9e46679e78206b5e.f6205eb5a39e4abe.aadc6946b52fbd64
+ 7ad98bfee5487882.cb910fb29b763b49.af9d854b6cfbe8e9.459f7fb39fdd1d38
+ d5eaebe951c5b137.7ec477054567b840.e83f7dd325603384.3a255729c15e0c44
+ 63396d9339c145b2
+VCVTSD2SS_128(mem)
+ before
+ 9da63edd230f85ae.fa51d528585bb29f.94ab1b8192fe9d6f.fd5243bb6b58693e
+ c53945f29a568865.465c47299597b668.ea1277139f47a703.4a22d16eda6fc4c1
+ b5befec1bba10a03.13553b57a404fa3b.5ac507a8874e9128.2bfa25580d3280b9
+ 4a01e533a1fdc6b3.bf8aaf1e222ebac7.c18f482a6720190a.fb283ae5a02cdbd4
+ 18f60c8130ea0fbb
+ after
+ 9da63edd230f85ae.fa51d528585bb29f.94ab1b8192fe9d6f.fd5243bb6b58693e
+ c53945f29a568865.465c47299597b668.ea1277139f47a703.4a22d16eda6fc4c1
+ 0000000000000000.0000000000000000.ea1277139f47a703.4a22d16eff800000
+ 4a01e533a1fdc6b3.bf8aaf1e222ebac7.c18f482a6720190a.fb283ae5a02cdbd4
+ 18f60c8130ea0fbb
+
+VCVTSD2SS_128(reg)
+ before
+ ddb1979858f7591d.60ce7735687579a2.a4459feaaba232b6.fb3eb5875bc8f9d4
+ a6a5d896b5dff5a4.d3f12eb32d15defb.1fd30527daeb9db5.e49ccaaa7d53edb2
+ ce1ecae7e22e1efc.7f35889a0ce9b3eb.8c80df424b95386f.5976037febccb3d2
+ b36769f87b7111d2.416700d420feb29e.489828a59b2d3f91.3498ddf2c13f055d
+ 52cdd2ef1ab9a082
+ after
+ 0000000000000000.0000000000000000.1fd30527daeb9db5.e49ccaaa00000000
+ a6a5d896b5dff5a4.d3f12eb32d15defb.1fd30527daeb9db5.e49ccaaa7d53edb2
+ ce1ecae7e22e1efc.7f35889a0ce9b3eb.8c80df424b95386f.5976037febccb3d2
+ b36769f87b7111d2.416700d420feb29e.489828a59b2d3f91.3498ddf2c13f055d
+ 52cdd2ef1ab9a082
+VCVTSD2SS_128(mem)
+ before
+ 8fe360621345406b.b0ceb1331e330ad2.f354134f8560973f.ad66dcbd663eedc6
+ c7a40337c7efa044.209d9f06640145a7.72c63bf6581920fb.1838f7f7475480bb
+ d6de355b53c37d3b.61212ddceb66fdfe.9a89f6b4b43707fd.e55876bedafc311c
+ 985b74b8d2ce9379.cea659204fee6f83.466bbf77b6c50972.7013547dbcc13f94
+ 15b58da2882fe4d0
+ after
+ 8fe360621345406b.b0ceb1331e330ad2.f354134f8560973f.ad66dcbd663eedc6
+ c7a40337c7efa044.209d9f06640145a7.72c63bf6581920fb.1838f7f7475480bb
+ 0000000000000000.0000000000000000.72c63bf6581920fb.1838f7f780000000
+ 985b74b8d2ce9379.cea659204fee6f83.466bbf77b6c50972.7013547dbcc13f94
+ 15b58da2882fe4d0
+
+VCVTSD2SS_128(reg)
+ before
+ 308a1d98dbd35d7b.e8e83a3b601c9d2d.c2781e402b26d7e1.5437122a79d0e286
+ 1ddd01cb5038e642.a45005d11ab75981.9be379a71b9970c4.9fb86cb91a634d64
+ 38fc33a784ebbbd1.a76151651bad81a1.b33264c1bcd377da.03bb4710b48a0739
+ dd31b199127617d3.cde698e3800ad1ba.67b3ddfbaa6128cd.5c0c211c6452cc30
+ 867775c745c65876
+ after
+ 0000000000000000.0000000000000000.9be379a71b9970c4.9fb86cb97f800000
+ 1ddd01cb5038e642.a45005d11ab75981.9be379a71b9970c4.9fb86cb91a634d64
+ 38fc33a784ebbbd1.a76151651bad81a1.b33264c1bcd377da.03bb4710b48a0739
+ dd31b199127617d3.cde698e3800ad1ba.67b3ddfbaa6128cd.5c0c211c6452cc30
+ 867775c745c65876
+VCVTSD2SS_128(mem)
+ before
+ 5cc8c0ff73f26636.68c9760b966737f5.f2aa583765d807f8.14b0dfbf7fcebf49
+ bcca7cae0ce3b39e.35107f6aad4a57e2.f17a0c4de525dd86.1476667adaa677fb
+ 814b27c229a4fad7.9f52c623f3aab247.a82230111cfd1091.c5516f9955758d8f
+ 87153c25e841f910.04db49a0031385cf.f26e406f276a5b45.818df5868cc83db0
+ a575f3af1c2bc20b
+ after
+ 5cc8c0ff73f26636.68c9760b966737f5.f2aa583765d807f8.14b0dfbf7fcebf49
+ bcca7cae0ce3b39e.35107f6aad4a57e2.f17a0c4de525dd86.1476667adaa677fb
+ 0000000000000000.0000000000000000.f17a0c4de525dd86.1476667a00000000
+ 87153c25e841f910.04db49a0031385cf.f26e406f276a5b45.818df5868cc83db0
+ a575f3af1c2bc20b
+
+VMOVD_XMM_to_IREG32(reg)
+ before
+ 8d57687fa028594b.a9f537c565c76a72.bff6034f79110c28.aa2ab953217a7bcd
+ 967d4d61b44e3e1d.c5b7948dba410a2c.2cf1f09bf23182fb.ae2116aa27392c56
+ 1a349fc3f626ad2d.b527d06906bc9468.a6160df00aff25f7.d921d35e54b22a0b
+ 76c85b10ff3ee126.571166456342c653.8bb254ba5c052fc6.06f46c5dc4f13019
+ 13675d919502fcab
+ after
+ 8d57687fa028594b.a9f537c565c76a72.bff6034f79110c28.aa2ab953217a7bcd
+ 967d4d61b44e3e1d.c5b7948dba410a2c.2cf1f09bf23182fb.ae2116aa27392c56
+ 1a349fc3f626ad2d.b527d06906bc9468.a6160df00aff25f7.d921d35e54b22a0b
+ 76c85b10ff3ee126.571166456342c653.8bb254ba5c052fc6.06f46c5dc4f13019
+ 00000000217a7bcd
+VMOVD_XMM_to_IREG32(mem)
+ before
+ da4623e8e0f247ee.06857cb46d2117b5.8540d20eede15a18.3611c36584d1dc14
+ 395c394dc3ccd00e.26b7fe1cdc5b8b85.1d8190aec1a50ce4.027e555d1fee6a8e
+ 0a771bac5a9c5136.32a9deb2e7797943.f9a11d12fa999ae2.4d47070ec8e913e0
+ 2a6145f1c06f8793.86a816e32a061c9b.f76af327b5c9be3f.71b6d3e41c4d14b5
+ cc19b74cb6a6a8ba
+ after
+ da4623e8e0f247ee.06857cb46d2117b5.8540d20eede15a18.3611c36584d1dc14
+ 395c394dc3ccd00e.26b7fe1cdc5b8b85.1d8190aec1a50ce4.027e555d1fee6a8e
+ 0a771bac5a9c5136.32a9deb2e7797943.f9a11d12fa999ae2.4d47070ec8e913e0
+ 2a6145f1c06f8793.86a816e32a061c9b.f76af327b5c9be3f.71b6d3e41c4d14b5
+ cc19b74cb6a6a8ba
+
+VMOVD_XMM_to_IREG32(reg)
+ before
+ b8baaeb033810d9b.76e8340811502e51.7e01a41c428eb138.f1a890d70d413527
+ 93e6b47e2e697d03.c8d663dd6a4c029b.76fe83c7cb9e73c7.c4296f101f0ebac5
+ b7e9c62144ea349e.fdf84e5ce66ebe9d.caecb05260c1a0f3.4db80dbd063b0b46
+ 820ede051090701a.f21a7172a2c21f85.d61625289d847269.6620e4cadfd5e2d6
+ ec2e7223c5e7fca0
+ after
+ b8baaeb033810d9b.76e8340811502e51.7e01a41c428eb138.f1a890d70d413527
+ 93e6b47e2e697d03.c8d663dd6a4c029b.76fe83c7cb9e73c7.c4296f101f0ebac5
+ b7e9c62144ea349e.fdf84e5ce66ebe9d.caecb05260c1a0f3.4db80dbd063b0b46
+ 820ede051090701a.f21a7172a2c21f85.d61625289d847269.6620e4cadfd5e2d6
+ 000000000d413527
+VMOVD_XMM_to_IREG32(mem)
+ before
+ bbae32b4d47d14d0.4ea3fa952ee86b20.81074809ba54e07c.f6cae0b51f7226d5
+ b06ca16929a3e794.78f2153f3b7e625f.878d500f4831bfb1.8652dc658117f7e2
+ a534392ee0663115.5d482b6fd3dc9081.e076046f6b64764e.e1fc15a460ff223d
+ 77d278ef14d1ae82.57f1398f91903333.688fe0143cfac180.651287de57b7e391
+ 6de12f7f03ca768b
+ after
+ bbae32b4d47d14d0.4ea3fa952ee86b20.81074809ba54e07c.f6cae0b51f7226d5
+ b06ca16929a3e794.78f2153f3b7e625f.878d500f4831bfb1.8652dc658117f7e2
+ a534392ee0663115.5d482b6fd3dc9081.e076046f6b64764e.e1fc15a460ff223d
+ 77d278ef14d1ae82.57f1398f91903333.688fe0143cfac180.651287de57b7e391
+ 6de12f7f03ca768b
+
+VMOVD_XMM_to_IREG32(reg)
+ before
+ 55b408f3ffc516d7.0211d999e1f11905.c3393a0c11268520.fca460ecdafe5e72
+ 78d90ea7e8330120.22bed81664d12fca.fd6c2a52f028c3f5.768101e25e7c0751
+ 349b3d0559a07012.b3a6f154b97dacff.61d505ceca25285d.b3f23de2e6817948
+ e445927bef98a25b.9193a13efa024bcd.4cc2c7ea39a6f105.8fc392d88e187084
+ e6bf7bb1714da731
+ after
+ 55b408f3ffc516d7.0211d999e1f11905.c3393a0c11268520.fca460ecdafe5e72
+ 78d90ea7e8330120.22bed81664d12fca.fd6c2a52f028c3f5.768101e25e7c0751
+ 349b3d0559a07012.b3a6f154b97dacff.61d505ceca25285d.b3f23de2e6817948
+ e445927bef98a25b.9193a13efa024bcd.4cc2c7ea39a6f105.8fc392d88e187084
+ 00000000dafe5e72
+VMOVD_XMM_to_IREG32(mem)
+ before
+ 94b37557ac2ddb7a.e324077445a8d1a5.985162bf466bca63.187d6d14dc395a99
+ 756bfab85ac2c88b.8f849a5bf75c3a9c.a4aeb2c5b7c4e3eb.2253f2b74d699fc4
+ 64b388be971b2992.42b1479ea23e19ed.91750d3b691a5291.c690523f28c2fb33
+ 3f579a578041bcb9.5af708a8e2dca944.3b71ed0d7978d583.608089180ad1ab91
+ 4c6e93ae8e21eb8b
+ after
+ 94b37557ac2ddb7a.e324077445a8d1a5.985162bf466bca63.187d6d14dc395a99
+ 756bfab85ac2c88b.8f849a5bf75c3a9c.a4aeb2c5b7c4e3eb.2253f2b74d699fc4
+ 64b388be971b2992.42b1479ea23e19ed.91750d3b691a5291.c690523f28c2fb33
+ 3f579a578041bcb9.5af708a8e2dca944.3b71ed0d7978d583.608089180ad1ab91
+ 4c6e93ae8e21eb8b
+
+VPCMPESTRM_0x45_128(reg)
+ before
+ e6a86d6d503ef7cd.e123ad6d31423b2c.31a1dae552c1284c.7e6fd02802ea26ea
+ 8a7812c1eeb50a02.26e23beec52a6219.25fcbac18e7acfb2.353b3176207d01f5
+ 942b7e16011161d7.ea61c2c55803efa9.9055a3a93392dd21.3ea18ce4f13c24ce
+ 5f0dadd927df37f7.086dbdde07db9c0b.cff69207dc958c47.746d5d5f8e3349a1
+ b36a20d1156f2d9b
+ after
+ e6a86d6d503ef7cd.e123ad6d31423b2c.31a1dae552c1284c.7e6fd02802ea26ea
+ 8a7812c1eeb50a02.26e23beec52a6219.25fcbac18e7acfb2.353b3176207d01f5
+ 942b7e16011161d7.ea61c2c55803efa9.9055a3a93392dd21.3ea18ce4f13c24ce
+ 5f0dadd927df37f7.086dbdde07db9c0b.ffff000000000000.00000000ffff0000
+ b36a20d1156f2d9b
+VPCMPESTRM_0x45_128(mem)
+ before
+ d6665228a2fb8ce8.496a9c74fcaaca0f.5ed0a825edbe2569.3f2c8148261019cd
+ bb2b6e4f50e321b3.ad8e46551bfe54ca.c756ff8627b748ef.3a426ed9ac8ec061
+ 3d86f0313b34a929.e7c4a7e6206712d6.1fcd3feed0d2bfca.1d8654250b9bbdaf
+ 374355bc80f9e076.535abb95a8723fdc.4100e347051b4726.45432f97dec44b63
+ 0cc4fb9dc294a728
+ after
+ d6665228a2fb8ce8.496a9c74fcaaca0f.5ed0a825edbe2569.3f2c8148261019cd
+ bb2b6e4f50e321b3.ad8e46551bfe54ca.c756ff8627b748ef.3a426ed9ac8ec061
+ 3d86f0313b34a929.e7c4a7e6206712d6.1fcd3feed0d2bfca.1d8654250b9bbdaf
+ 374355bc80f9e076.535abb95a8723fdc.0000000000000000.0000000000000000
+ 0cc4fb9dc294a728
+
+VPCMPESTRM_0x45_128(reg)
+ before
+ cf56b5a252970caa.872e17db3b3e82c5.4c9a7ecd4faa188b.0bba677fe19f9c2e
+ ea4557122b5ab897.0713b47a86104a42.30d1edfab09cd98d.57c847808169790f
+ b9dddf59e868e598.95bda786807af51b.5a4b038867d3be8e.03f6ff3800859cf5
+ 986949e3254dcf5c.0bf96de943893f7a.2554bce311db033b.e9100c927a00be0b
+ e7e2e9790ce59e7d
+ after
+ cf56b5a252970caa.872e17db3b3e82c5.4c9a7ecd4faa188b.0bba677fe19f9c2e
+ ea4557122b5ab897.0713b47a86104a42.30d1edfab09cd98d.57c847808169790f
+ b9dddf59e868e598.95bda786807af51b.5a4b038867d3be8e.03f6ff3800859cf5
+ 986949e3254dcf5c.0bf96de943893f7a.ffffffffffff0000.0000000000000000
+ e7e2e9790ce59e7d
+VPCMPESTRM_0x45_128(mem)
+ before
+ d73812dbd241f679.e3378f1d7f96b48d.47948090eb47e38b.ef3714774941e340
+ 97dd03a3e71e8328.f691af7192ceced7.23585e6895c29e7b.124208b1ac909b48
+ 019e39bd678b01b9.2dc4a34df9825ae8.7d11825b5c062c76.ecbf93fbd5546600
+ f2472f166f912b56.e41c6a1b503d9469.2f8d68575d1e49a7.d7fbb1c361198114
+ 31425e73eb6c282f
+ after
+ d73812dbd241f679.e3378f1d7f96b48d.47948090eb47e38b.ef3714774941e340
+ 97dd03a3e71e8328.f691af7192ceced7.23585e6895c29e7b.124208b1ac909b48
+ 019e39bd678b01b9.2dc4a34df9825ae8.7d11825b5c062c76.ecbf93fbd5546600
+ f2472f166f912b56.e41c6a1b503d9469.0000000000000000.0000000000000000
+ 31425e73eb6c282f
+
+VPCMPESTRM_0x45_128(reg)
+ before
+ 54e0967910d997fd.47a460981b3ebf2c.77e5fd49348bb709.16978c47b316b03b
+ 9d2156406bea0a2c.da814b30859d7766.426b594241f80072.0ffa6b177afa1e5d
+ 69509934982dbc65.88aa69cbccbb0f31.a1fa7b711111ab50.f48380b3cfd74f3a
+ 12ba5bc1342eea57.2dea38540aa244b8.f0dd5e444361f350.a2fe4707ceb8fefe
+ f5373cff92aae9d4
+ after
+ 54e0967910d997fd.47a460981b3ebf2c.77e5fd49348bb709.16978c47b316b03b
+ 9d2156406bea0a2c.da814b30859d7766.426b594241f80072.0ffa6b177afa1e5d
+ 69509934982dbc65.88aa69cbccbb0f31.a1fa7b711111ab50.f48380b3cfd74f3a
+ 12ba5bc1342eea57.2dea38540aa244b8.ffff0000ffff0000.ffff000000000000
+ f5373cff92aae9d4
+VPCMPESTRM_0x45_128(mem)
+ before
+ c9fadb8738b8cae9.f5ac9853db77cfac.a50f33b65b61d328.8b61fe267075161e
+ fa13a18bdbee5d69.6f704d562896a911.cde3d6dfdc0175ad.ced2588437d74e66
+ 654d09f89759607f.da527436b717b231.7f339dbaa890e972.147c66c83116d7d2
+ e4758fb889048d57.93a00b60258426b9.98cb0433dc19e9a4.bbab265ffdbbef11
+ 1eab93b63454d0cd
+ after
+ c9fadb8738b8cae9.f5ac9853db77cfac.a50f33b65b61d328.8b61fe267075161e
+ fa13a18bdbee5d69.6f704d562896a911.cde3d6dfdc0175ad.ced2588437d74e66
+ 654d09f89759607f.da527436b717b231.7f339dbaa890e972.147c66c83116d7d2
+ e4758fb889048d57.93a00b60258426b9.ffff0000ffffffff.ffff0000ffff0000
+ 1eab93b63454d0cd
+
+VMOVQ_IREGorMEM64_to_XMM(reg)
+ before
+ 98c7a937746cb7b3.5458afb9ccfba01e.f6a50d3e0e6b4354.f477883693a9326e
+ 874d65505990df6e.91c0e6e67d4a5700.5fac773e0c5843af.6f02a4afe94b80fd
+ 4687c26b7e4b86ab.7779af2ab7fe6c29.2b0243cabed66376.e539d48afb0b8e7d
+ 30c2bbf68029e516.e251867397239cc3.b4f36f50be71df54.32e995b4e5f61919
+ 32dc6117c217ddfe
+ after
+ 0000000000000000.0000000000000000.0000000000000000.32dc6117c217ddfe
+ 874d65505990df6e.91c0e6e67d4a5700.5fac773e0c5843af.6f02a4afe94b80fd
+ 4687c26b7e4b86ab.7779af2ab7fe6c29.2b0243cabed66376.e539d48afb0b8e7d
+ 30c2bbf68029e516.e251867397239cc3.b4f36f50be71df54.32e995b4e5f61919
+ 32dc6117c217ddfe
+VMOVQ_IREGorMEM64_to_XMM(mem)
+ before
+ c1dfb6a1ae7a9557.a34a4f5cfab63b5a.ad13e7ac39c3a3fd.57cbf63ba8b5f2f6
+ babe0f3cc62cff51.f96a7709887fc323.b68a4ec1b7ec3c01.70d6d4f7192fd907
+ fb44e8d62638d418.90703169c710b81f.d883389f2faa24fc.5b6006f0ac6ad034
+ 5f3fbe5ae9aad3d7.c2a677e852f357f7.efca2030bd071719.74b48792fdf21229
+ 16205249aa54dc91
+ after
+ c1dfb6a1ae7a9557.a34a4f5cfab63b5a.ad13e7ac39c3a3fd.57cbf63ba8b5f2f6
+ babe0f3cc62cff51.f96a7709887fc323.b68a4ec1b7ec3c01.70d6d4f7192fd907
+ fb44e8d62638d418.90703169c710b81f.d883389f2faa24fc.5b6006f0ac6ad034
+ 0000000000000000.0000000000000000.0000000000000000.57cbf63ba8b5f2f6
+ 16205249aa54dc91
+
+VMOVQ_IREGorMEM64_to_XMM(reg)
+ before
+ 9fee66824c1b6a19.c2790cb42b8fb7ba.ec5947f3c6b6db5a.d72b82617c11d185
+ 6a6bbca781d4f86c.00bf4ed009f23bef.6bd69df4bfe582f2.6c72da1f89d40d6c
+ d3e25225e50ac137.f4dd009a9edf1ba0.99667358d70a866c.896aa554ff5a88f9
+ 36a1226913490325.7c9f9efe076315f9.d358c78cadb32373.0ce15eeefab1fd59
+ d0a181d897e52ab7
+ after
+ 0000000000000000.0000000000000000.0000000000000000.d0a181d897e52ab7
+ 6a6bbca781d4f86c.00bf4ed009f23bef.6bd69df4bfe582f2.6c72da1f89d40d6c
+ d3e25225e50ac137.f4dd009a9edf1ba0.99667358d70a866c.896aa554ff5a88f9
+ 36a1226913490325.7c9f9efe076315f9.d358c78cadb32373.0ce15eeefab1fd59
+ d0a181d897e52ab7
+VMOVQ_IREGorMEM64_to_XMM(mem)
+ before
+ b0778afdf200c940.eff32adea71df7e4.73d1a5e85f89e327.76f794fada6c97b4
+ 8a2ff54b2610971f.592366f03e13dc1d.b43e8f45c35d4256.dc8ed610fdbf1cda
+ 38953fad4f214f82.d27ed00a74b6ec7f.1db4daff4eeceeb1.626b8939af3aef92
+ 9875e3108a3eaf92.b550669ae39364b4.88fd02041d41a265.64d8aae18e694b88
+ 3f22337436d66e67
+ after
+ b0778afdf200c940.eff32adea71df7e4.73d1a5e85f89e327.76f794fada6c97b4
+ 8a2ff54b2610971f.592366f03e13dc1d.b43e8f45c35d4256.dc8ed610fdbf1cda
+ 38953fad4f214f82.d27ed00a74b6ec7f.1db4daff4eeceeb1.626b8939af3aef92
+ 0000000000000000.0000000000000000.0000000000000000.76f794fada6c97b4
+ 3f22337436d66e67
+
+VMOVQ_IREGorMEM64_to_XMM(reg)
+ before
+ 4d94225e420f92dc.849a5d5ef273717d.5de5230b2a358068.d3e6813e4b681c9e
+ eb7c730b4fa0f492.dad12984a4cc516f.288903cae3287b48.d83bd59bf46e1587
+ 752520e8f814cf36.74e7c36ebc560d94.70880241aaf99200.75c77906365e4c4d
+ 47da275fd9f76074.30a6a809541c5f17.932d1cdd1c32013b.8458e96b2a457b1b
+ e3b9a1b6ee2e5f1e
+ after
+ 0000000000000000.0000000000000000.0000000000000000.e3b9a1b6ee2e5f1e
+ eb7c730b4fa0f492.dad12984a4cc516f.288903cae3287b48.d83bd59bf46e1587
+ 752520e8f814cf36.74e7c36ebc560d94.70880241aaf99200.75c77906365e4c4d
+ 47da275fd9f76074.30a6a809541c5f17.932d1cdd1c32013b.8458e96b2a457b1b
+ e3b9a1b6ee2e5f1e
+VMOVQ_IREGorMEM64_to_XMM(mem)
+ before
+ 6cb51ed39d25b481.bde883dd8fd5e3f7.e8da533f8b2b0425.ecc54e0bd46204a6
+ fc19daae54363571.339b30cfb63b946c.795140fe7a8db7e9.d69c93356f12d6ed
+ 70b153342f6ea01a.053f2aa0e9b4ae7e.c0d6ec313f513690.aefee7c988d0b4bb
+ a249054f49d8afa7.8f206dbbc4cc6eda.9734d1c4f6803b45.d1374731bb28dabc
+ 9993addba6a4839e
+ after
+ 6cb51ed39d25b481.bde883dd8fd5e3f7.e8da533f8b2b0425.ecc54e0bd46204a6
+ fc19daae54363571.339b30cfb63b946c.795140fe7a8db7e9.d69c93356f12d6ed
+ 70b153342f6ea01a.053f2aa0e9b4ae7e.c0d6ec313f513690.aefee7c988d0b4bb
+ 0000000000000000.0000000000000000.0000000000000000.ecc54e0bd46204a6
+ 9993addba6a4839e
+
+VMOVUPS_XMM_to_XMMorMEM(reg)
+ before
+ 645d1732e2d2ec0a.6fac6aedbe811e45.2c89f68ee410102c.db386da3ba288335
+ 8ce380a20d3e51af.b3a800f8ab74aa1f.3ac8c084e40bd01f.69ae3bbaa854c98c
+ 6e6fe597c372ee37.4a07415e2bbd1062.1427c709614ae960.1b62b7f5db11ca75
+ 674e407d9ffcfe4f.1196ac0a5b68093a.16f30889f658989a.ce205e406f69421d
+ 5eb4aa88816bedaf
+ after
+ 0000000000000000.0000000000000000.3ac8c084e40bd01f.69ae3bbaa854c98c
+ 8ce380a20d3e51af.b3a800f8ab74aa1f.3ac8c084e40bd01f.69ae3bbaa854c98c
+ 6e6fe597c372ee37.4a07415e2bbd1062.1427c709614ae960.1b62b7f5db11ca75
+ 674e407d9ffcfe4f.1196ac0a5b68093a.16f30889f658989a.ce205e406f69421d
+ 5eb4aa88816bedaf
+VMOVUPS_XMM_to_XMMorMEM(mem)
+ before
+ a7e919b72d208658.d1cc8fc13d68bea2.e221bae7568254d2.9c787d7140c1197a
+ 858c26ba8e96ca44.0934cdcd3a406add.9a74e8e33916ab57.0102242bda12a7ab
+ d46a4e7ec0d8759e.6bd4f60f31123eab.155bb3ea1f31cbf4.a3ddf82461d57fdb
+ 704d0beee0f34293.53f606f1bf6a75b9.2fa296e624de70d6.dd54f5c97099ddb3
+ 0ab41884a3e7fce2
+ after
+ a7e919b72d208658.d1cc8fc13d68bea2.2fa296e624de70d6.dd54f5c97099ddb3
+ 858c26ba8e96ca44.0934cdcd3a406add.9a74e8e33916ab57.0102242bda12a7ab
+ d46a4e7ec0d8759e.6bd4f60f31123eab.155bb3ea1f31cbf4.a3ddf82461d57fdb
+ 704d0beee0f34293.53f606f1bf6a75b9.2fa296e624de70d6.dd54f5c97099ddb3
+ 0ab41884a3e7fce2
+
+VMOVUPS_XMM_to_XMMorMEM(reg)
+ before
+ 884a5cc3974d1a12.3501dbf609f2ef4e.1de8fae180d24cb3.c4140dc466295529
+ b160bdf1e85671ef.ff54398158e136fc.25f4cd490ed9fe44.b07e9570fe1f3718
+ e342377a318f3d26.aa11a17de8cdd3c9.c7677b970808c919.cfaca8d70acbd2d0
+ 783ec6ca0e83bc63.120390d6d6c184e0.5f8c003607ede7dd.fd6ac4e3a639e17c
+ 15846482ed762249
+ after
+ 0000000000000000.0000000000000000.25f4cd490ed9fe44.b07e9570fe1f3718
+ b160bdf1e85671ef.ff54398158e136fc.25f4cd490ed9fe44.b07e9570fe1f3718
+ e342377a318f3d26.aa11a17de8cdd3c9.c7677b970808c919.cfaca8d70acbd2d0
+ 783ec6ca0e83bc63.120390d6d6c184e0.5f8c003607ede7dd.fd6ac4e3a639e17c
+ 15846482ed762249
+VMOVUPS_XMM_to_XMMorMEM(mem)
+ before
+ f5c6049ffb8d4e63.ce9f674d1cbe2851.13f780763dc9036e.49b15992aa13943d
+ 78fb2125ed8a24f5.3fb0146ff7cdbe9d.89b9ef4a3af20c9e.e12080178a060ee5
+ 7af03502de7a5f2c.29becc9c3a3bb9f2.4f15583ee8475d9d.8327733245538f80
+ d772be21eb68ba33.e6158841819457fd.43d7383f63d4b097.8b102d4d778554ba
+ 5528abd5bb299941
+ after
+ f5c6049ffb8d4e63.ce9f674d1cbe2851.43d7383f63d4b097.8b102d4d778554ba
+ 78fb2125ed8a24f5.3fb0146ff7cdbe9d.89b9ef4a3af20c9e.e12080178a060ee5
+ 7af03502de7a5f2c.29becc9c3a3bb9f2.4f15583ee8475d9d.8327733245538f80
+ d772be21eb68ba33.e6158841819457fd.43d7383f63d4b097.8b102d4d778554ba
+ 5528abd5bb299941
+
+VMOVUPS_XMM_to_XMMorMEM(reg)
+ before
+ 3dbbe737aec999bf.6a4b386e2f60f137.d30145c86965d26a.40ca0937c9a6c2b7
+ 9f14dfddebf491e0.11471dd6c76fc263.4dce009f8d3967e4.22bc491433c84f29
+ d6818e350e33bd51.a734ea43cea0e7e5.aec8b4308a9c5118.c47773c1bf46121b
+ 404cf0aab41459be.07dd1ca261ff1de6.533a5de9fb1bcdb2.04c8032a892dc8b7
+ bc7b753aac882d29
+ after
+ 0000000000000000.0000000000000000.4dce009f8d3967e4.22bc491433c84f29
+ 9f14dfddebf491e0.11471dd6c76fc263.4dce009f8d3967e4.22bc491433c84f29
+ d6818e350e33bd51.a734ea43cea0e7e5.aec8b4308a9c5118.c47773c1bf46121b
+ 404cf0aab41459be.07dd1ca261ff1de6.533a5de9fb1bcdb2.04c8032a892dc8b7
+ bc7b753aac882d29
+VMOVUPS_XMM_to_XMMorMEM(mem)
+ before
+ ca5c46e04464fd9e.38c302a87922a0d3.0f0d2ee09b992095.9871f7357d41175d
+ 0837f1056ecbf342.1930be9bf7eacf3a.99919de79979ab1b.dab97f80ab9a6bc5
+ 54d7f29645cbcc40.41e022efcdf722a2.8335e3a576ac7ca7.735ef03622b30498
+ 8809c57fe67044c5.0b1e291095d5d4b5.a7c57e054f3c4c63.c0ac46c37d171f7f
+ 1def7d935852f829
+ after
+ ca5c46e04464fd9e.38c302a87922a0d3.a7c57e054f3c4c63.c0ac46c37d171f7f
+ 0837f1056ecbf342.1930be9bf7eacf3a.99919de79979ab1b.dab97f80ab9a6bc5
+ 54d7f29645cbcc40.41e022efcdf722a2.8335e3a576ac7ca7.735ef03622b30498
+ 8809c57fe67044c5.0b1e291095d5d4b5.a7c57e054f3c4c63.c0ac46c37d171f7f
+ 1def7d935852f829
+
+VMOVNTDQ_128(reg)
+ before
+ e672911250f1ca40.829ae7ad6cc516fd.d238d06aeb102220.e30de9f33f37da7c
+ 77837fad017fd370.1c54d30af4d6ff13.f47811696c35488e.11d9a05a62a9e01d
+ 2c6c42ce06894c67.3403048499afbb33.cb2cea7ab3d082ac.0ff41f29d59d1b73
+ 617ad6e3fb9974ce.a475f905785d068b.b59e56075d6b0b25.b72be249b41f47a9
+ e64a66a71a3b1fec
+ after
+ e672911250f1ca40.829ae7ad6cc516fd.d238d06aeb102220.e30de9f33f37da7c
+ 77837fad017fd370.1c54d30af4d6ff13.f47811696c35488e.11d9a05a62a9e01d
+ 2c6c42ce06894c67.3403048499afbb33.cb2cea7ab3d082ac.0ff41f29d59d1b73
+ 617ad6e3fb9974ce.a475f905785d068b.b59e56075d6b0b25.b72be249b41f47a9
+ e64a66a71a3b1fec
+VMOVNTDQ_128(mem)
+ before
+ 791d262f23fe6168.72f937577d3d8654.49752b7baceb9b44.0c1b517e059420a7
+ 4a709eceec73c748.bb3562952701bda3.00ce18d15266378d.2eeed74a47d6fddb
+ 360f4b6e90a70db9.9879510b96705567.a34d3af385d99690.7565e5d7c1bedd6f
+ 19c5a7fd2ca5f0e7.6513022466168c4d.0fbe0fcd6150737a.3ecb76900cd7fd0f
+ e66b86e3c6ad9967
+ after
+ 791d262f23fe6168.72f937577d3d8654.00ce18d15266378d.2eeed74a47d6fddb
+ 4a709eceec73c748.bb3562952701bda3.00ce18d15266378d.2eeed74a47d6fddb
+ 360f4b6e90a70db9.9879510b96705567.a34d3af385d99690.7565e5d7c1bedd6f
+ 19c5a7fd2ca5f0e7.6513022466168c4d.0fbe0fcd6150737a.3ecb76900cd7fd0f
+ e66b86e3c6ad9967
+
+VMOVNTDQ_128(reg)
+ before
+ c792113c8bcded22.d0603065db792dfd.7d4d704c317f9c01.20ed134b03d78c76
+ 3e8c1405f6c234ec.35aa6194ba2f7d27.3e7498ef9638c22e.b2a6c059877b9bb1
+ a8a589aba318ab73.2570b775e4d49f92.03d474792ecc3a81.a2b594e408475c56
+ 5f296e9a2f5c8e61.7c7eacf476744d6a.28b9025797c83fa6.cae50ad6a2488d92
+ 07039e1d7289e891
+ after
+ c792113c8bcded22.d0603065db792dfd.7d4d704c317f9c01.20ed134b03d78c76
+ 3e8c1405f6c234ec.35aa6194ba2f7d27.3e7498ef9638c22e.b2a6c059877b9bb1
+ a8a589aba318ab73.2570b775e4d49f92.03d474792ecc3a81.a2b594e408475c56
+ 5f296e9a2f5c8e61.7c7eacf476744d6a.28b9025797c83fa6.cae50ad6a2488d92
+ 07039e1d7289e891
+VMOVNTDQ_128(mem)
+ before
+ 35dccca39416297e.c063bf3f35191862.16a0befd8b1944db.086e3df36db70e48
+ 303a115623fc0e86.27a1760452dc8623.cfa1687c40d14010.014122bb4b25e314
+ d4e9e7213b4651d4.f02d9157222f1450.834f265db0a7fc35.6e7cab19ce9ffab5
+ fdb7ccf0f900af95.77540aa33fa0fe94.0e74748df7a83577.aa6cd67b91af8ed8
+ 135d9e4c30e4dc28
+ after
+ 35dccca39416297e.c063bf3f35191862.cfa1687c40d14010.014122bb4b25e314
+ 303a115623fc0e86.27a1760452dc8623.cfa1687c40d14010.014122bb4b25e314
+ d4e9e7213b4651d4.f02d9157222f1450.834f265db0a7fc35.6e7cab19ce9ffab5
+ fdb7ccf0f900af95.77540aa33fa0fe94.0e74748df7a83577.aa6cd67b91af8ed8
+ 135d9e4c30e4dc28
+
+VMOVNTDQ_128(reg)
+ before
+ 039bfff848c72053.876f3caf7837e4f4.1862df5448bb7f9c.4cddcff632dfa702
+ d872f5eb75e69502.4ddcb14ad5f6ab1f.2fa30cd6d60bd413.1956b2867d580d01
+ ec2d7d9152cd78e4.2dcba9ad2b49c13f.18628b95881c39a6.51ab9927f32025a1
+ 9d1a92567b0605a2.02089fc4963de283.2fed5afdf77aea01.cfa700c7b042a80e
+ 71186451d1ca5573
+ after
+ 039bfff848c72053.876f3caf7837e4f4.1862df5448bb7f9c.4cddcff632dfa702
+ d872f5eb75e69502.4ddcb14ad5f6ab1f.2fa30cd6d60bd413.1956b2867d580d01
+ ec2d7d9152cd78e4.2dcba9ad2b49c13f.18628b95881c39a6.51ab9927f32025a1
+ 9d1a92567b0605a2.02089fc4963de283.2fed5afdf77aea01.cfa700c7b042a80e
+ 71186451d1ca5573
+VMOVNTDQ_128(mem)
+ before
+ 12c83fb171c5e7fd.458330a68d1f78eb.a85f0f7b34ddca15.d08e747ac1b222cf
+ 8e840fd3ad3e19d7.41b553ee23a30c69.fb9c75bf1e353421.5792d578824f1ebc
+ c0184fa3a141a72e.eefcf798da1ffec9.d68a4e7a7252ddd4.20457964d5de1a76
+ 86507c0d67db4f2e.a6a419124e1e8ab6.17f7149a4c3f805a.87f35da857e951a7
+ e7e87cb2a3ff00fb
+ after
+ 12c83fb171c5e7fd.458330a68d1f78eb.fb9c75bf1e353421.5792d578824f1ebc
+ 8e840fd3ad3e19d7.41b553ee23a30c69.fb9c75bf1e353421.5792d578824f1ebc
+ c0184fa3a141a72e.eefcf798da1ffec9.d68a4e7a7252ddd4.20457964d5de1a76
+ 86507c0d67db4f2e.a6a419124e1e8ab6.17f7149a4c3f805a.87f35da857e951a7
+ e7e87cb2a3ff00fb
+
+VMOVLHPS_128(reg)
+ before
+ 9e6fd2ec55a9631f.bbf810fd1e17cb02.c6f8b4c6192cebdd.99ad450ac708dbde
+ 07d65bc40a75b5bf.3adb8960df01d8d7.ab46c422dad65ee9.37795cb6ffbaa88d
+ 7e6713a55dee3487.e1c76220c8a632d8.afd845912aa71f87.cf27d68a1160a493
+ 5e6ff7fbeba11a21.8a86172bf5119432.2ffb347fa72b6a63.3c832d7219068a1b
+ 5959df5a31b91852
+ after
+ 0000000000000000.0000000000000000.cf27d68a1160a493.37795cb6ffbaa88d
+ 07d65bc40a75b5bf.3adb8960df01d8d7.ab46c422dad65ee9.37795cb6ffbaa88d
+ 7e6713a55dee3487.e1c76220c8a632d8.afd845912aa71f87.cf27d68a1160a493
+ 5e6ff7fbeba11a21.8a86172bf5119432.2ffb347fa72b6a63.3c832d7219068a1b
+ 5959df5a31b91852
+VMOVLHPS_128(mem)
+ before
+ 0474672e78840863.053a02325019a33c.13e5256c814fbc10.87fb8c58edef7a28
+ 17a142da0873167b.ce1430b627e20d82.56b006ce896a639f.13244988977e8c83
+ 6fadea4bfd9300c5.14487df30c8892a0.31b3383f2871480b.2fc2677b4265dc1f
+ e962dd6b74ef806e.3524e6569c986f41.7eb936aa7a6d257f.3720e29d892ea6a9
+ 878cb75b086725cd
+ after
+ 0474672e78840863.053a02325019a33c.13e5256c814fbc10.87fb8c58edef7a28
+ 17a142da0873167b.ce1430b627e20d82.56b006ce896a639f.13244988977e8c83
+ 6fadea4bfd9300c5.14487df30c8892a0.31b3383f2871480b.2fc2677b4265dc1f
+ e962dd6b74ef806e.3524e6569c986f41.7eb936aa7a6d257f.3720e29d892ea6a9
+ 878cb75b086725cd
+
+VMOVLHPS_128(reg)
+ before
+ 7b50e11f5c9c9636.5f8c9628889453a2.8bf26549729edf12.1b907dfb9c6cb728
+ 6fb95c5721583491.aff9916c568d348c.74fff83a2b2420be.e202871eaa79ba32
+ bf13246df1273d89.b3744a25f9e6e159.4a979b9362b86cf3.b0dcd2ffbfa0e9c8
+ c7a936cf6b95ebcb.48c83e3e8dab1435.6a0648c2b3e5ff5a.62ead98bf7ee0216
+ d2f818ac6f6ebf4a
+ after
+ 0000000000000000.0000000000000000.b0dcd2ffbfa0e9c8.e202871eaa79ba32
+ 6fb95c5721583491.aff9916c568d348c.74fff83a2b2420be.e202871eaa79ba32
+ bf13246df1273d89.b3744a25f9e6e159.4a979b9362b86cf3.b0dcd2ffbfa0e9c8
+ c7a936cf6b95ebcb.48c83e3e8dab1435.6a0648c2b3e5ff5a.62ead98bf7ee0216
+ d2f818ac6f6ebf4a
+VMOVLHPS_128(mem)
+ before
+ ddd10c50422ddc8d.e3c98ce8292f7b03.4ac2e8a330e98a4b.3197fd32bb3817a1
+ 5f432f618d36160e.6fbd2424c78028dc.962ec440fbabfec7.f998b54f163cee74
+ 3518ffcd6b952af7.c7d3faefe2152f03.06d84e010cfe2dd6.20536c855f7dc17f
+ 391df77ff957d174.465508b51579cc23.778c02d27fedd3a4.00151e403388cb6d
+ f62ac7ec2de84aea
+ after
+ ddd10c50422ddc8d.e3c98ce8292f7b03.4ac2e8a330e98a4b.3197fd32bb3817a1
+ 5f432f618d36160e.6fbd2424c78028dc.962ec440fbabfec7.f998b54f163cee74
+ 3518ffcd6b952af7.c7d3faefe2152f03.06d84e010cfe2dd6.20536c855f7dc17f
+ 391df77ff957d174.465508b51579cc23.778c02d27fedd3a4.00151e403388cb6d
+ f62ac7ec2de84aea
+
+VMOVLHPS_128(reg)
+ before
+ 5ede64f5e92978a4.481e94635287cab3.4a904ce2fd383be9.c5165da06f84ac5d
+ 957df0c804d89244.3ee750659331cfdd.2ed0c0e335deb700.cc41da55f8d0732c
+ f55367cf1980d379.f744a971d7619d21.4e6062225af87e16.68daf5df37dbe53d
+ dbabc678c5ae78ed.4f011a733b24f0a9.058e2e0d0711c9d4.75ae2b2847b4bebd
+ cf87f61e4564b9d8
+ after
+ 0000000000000000.0000000000000000.68daf5df37dbe53d.cc41da55f8d0732c
+ 957df0c804d89244.3ee750659331cfdd.2ed0c0e335deb700.cc41da55f8d0732c
+ f55367cf1980d379.f744a971d7619d21.4e6062225af87e16.68daf5df37dbe53d
+ dbabc678c5ae78ed.4f011a733b24f0a9.058e2e0d0711c9d4.75ae2b2847b4bebd
+ cf87f61e4564b9d8
+VMOVLHPS_128(mem)
+ before
+ 5231d4ac4df994ba.a3d2072da4ecbd4d.22e91f57da8683a1.b1a41e0ed8b6d7e9
+ da7a40be797f098e.a914285c50c8de44.4cc93409d0911337.acef30936a72e2fe
+ 432db640e800d480.49bd247068ce167f.a96dd6763a535c94.54bb5f0759d127c2
+ 6915b21eb38ab3bd.df19f7d58588a2a9.15a1808834d719e7.0454a7d64060e2df
+ 1706046cbbaa4e02
+ after
+ 5231d4ac4df994ba.a3d2072da4ecbd4d.22e91f57da8683a1.b1a41e0ed8b6d7e9
+ da7a40be797f098e.a914285c50c8de44.4cc93409d0911337.acef30936a72e2fe
+ 432db640e800d480.49bd247068ce167f.a96dd6763a535c94.54bb5f0759d127c2
+ 6915b21eb38ab3bd.df19f7d58588a2a9.15a1808834d719e7.0454a7d64060e2df
+ 1706046cbbaa4e02
+
+VPABSD_128(reg)
+ before
+ eb1c7335673ba9d6.28ffb144f8286071.c7749ef74585be6f.6c31ae2dd92a085a
+ dae4ef9de0a02c08.5cb72e9ed3e797c7.5d191342444ea57c.89e9dc504557e219
+ 41a87410c1631643.e009a5195fd216ec.fd5554221d71957e.4a9487dd956a6651
+ 7db5fefaa613a134.92c1929fb9f6970c.03745c046d79c81e.8a0029bfe5704f2e
+ 25f740e44f7458db
+ after
+ eb1c7335673ba9d6.28ffb144f8286071.c7749ef74585be6f.6c31ae2dd92a085a
+ 0000000000000000.0000000000000000.02aaabde1d71957e.4a9487dd6a9599af
+ 41a87410c1631643.e009a5195fd216ec.fd5554221d71957e.4a9487dd956a6651
+ 7db5fefaa613a134.92c1929fb9f6970c.03745c046d79c81e.8a0029bfe5704f2e
+ 25f740e44f7458db
+VPABSD_128(mem)
+ before
+ f6464738f2823d85.e85789c82c390a87.4daa721efc5dd752.cbc22852cff27a0b
+ dbb9bba5e8a7bc58.dfda12e4ee638de7.ed92c080441592eb.b08bb279e069e9ef
+ af1b16184dee8f7f.bf8994bc891d6501.4d43f8b3ae2a8302.101bf8e63b694f76
+ 4d3ad67d3d647327.e2b20bbb98f1d081.4b8a96a256a667c4.46bef5047c7fe94d
+ aebfa53f4036f220
+ after
+ f6464738f2823d85.e85789c82c390a87.4daa721efc5dd752.cbc22852cff27a0b
+ 0000000000000000.0000000000000000.4daa721e03a228ae.343dd7ae300d85f5
+ af1b16184dee8f7f.bf8994bc891d6501.4d43f8b3ae2a8302.101bf8e63b694f76
+ 4d3ad67d3d647327.e2b20bbb98f1d081.4b8a96a256a667c4.46bef5047c7fe94d
+ aebfa53f4036f220
+
+VPABSD_128(reg)
+ before
+ a36b0502221aa79a.93e076c1d613247b.a59f734db86e0812.c23316395797fa5d
+ 830e0fbbbfb84468.5bda72ce31095da8.649dc9dd841d4960.8d0af564cd09f8f8
+ a9f4c1d5b39a0536.83f447926c52dcd9.7bf808d9988cd118.8adbae0fd5071cc1
+ 706916bd984f25af.e5fa6ff8a3f95a3b.47fc2cad9146dae6.9371bd268b9d23e6
+ 86999e9509d7c991
+ after
+ a36b0502221aa79a.93e076c1d613247b.a59f734db86e0812.c23316395797fa5d
+ 0000000000000000.0000000000000000.7bf808d967732ee8.752451f12af8e33f
+ a9f4c1d5b39a0536.83f447926c52dcd9.7bf808d9988cd118.8adbae0fd5071cc1
+ 706916bd984f25af.e5fa6ff8a3f95a3b.47fc2cad9146dae6.9371bd268b9d23e6
+ 86999e9509d7c991
+VPABSD_128(mem)
+ before
+ 3d20ce496ec2c9ee.36b80bdd0d60e280.5fb868ecf10a96fa.22f431c30bd7a076
+ 95d0c72cd369e02a.552f9aa2ac5b7554.cbfaad5a73914a41.692e1388a1cc6173
+ 6b76072c57d8ca71.2b18c17911cb1dd8.078bbb2e449b333d.78f4cf68f0b05789
+ 99dd0933131c43ee.12c07bccd83d14b7.ed380c5480330d1a.ab9460d0930fbf65
+ 5e58c22b2676d5b3
+ after
+ 3d20ce496ec2c9ee.36b80bdd0d60e280.5fb868ecf10a96fa.22f431c30bd7a076
+ 0000000000000000.0000000000000000.5fb868ec0ef56906.22f431c30bd7a076
+ 6b76072c57d8ca71.2b18c17911cb1dd8.078bbb2e449b333d.78f4cf68f0b05789
+ 99dd0933131c43ee.12c07bccd83d14b7.ed380c5480330d1a.ab9460d0930fbf65
+ 5e58c22b2676d5b3
+
+VPABSD_128(reg)
+ before
+ ed8cf1e44670d41f.fcd34a2f254006ce.6873c4099f3c979e.5ace1eb844669303
+ b47eea698e8af954.7122440ba951d03c.877d999aff54e239.2b166c46ab3e8324
+ 0e79a8259b4f80fe.d29775b3ba5a5d65.cd2af4ed96123133.3adf72ebd2ca97ab
+ 59c82784084ba4ca.fcfe581375676875.94c5d36d0001bf39.64f4ad91d5138bc2
+ 85209726ce271c95
+ after
+ ed8cf1e44670d41f.fcd34a2f254006ce.6873c4099f3c979e.5ace1eb844669303
+ 0000000000000000.0000000000000000.32d50b1369edcecd.3adf72eb2d356855
+ 0e79a8259b4f80fe.d29775b3ba5a5d65.cd2af4ed96123133.3adf72ebd2ca97ab
+ 59c82784084ba4ca.fcfe581375676875.94c5d36d0001bf39.64f4ad91d5138bc2
+ 85209726ce271c95
+VPABSD_128(mem)
+ before
+ 7a31ae95dc110751.f0b863f2720aa364.cb236917f585af97.399b3186d8adc9f7
+ 1df16dc918de0522.2f9658db7419b777.1cd225ab56beecf8.19f90aa4bba38a18
+ 4b2d50b0a199d533.72ab03abab031cb0.c9d707bcb521dbc3.8e295b33436e3f48
+ e0b1d435904e31b1.14465fceb25510bb.affd8a342eb73a25.f5781fa00f9a2535
+ aa315255b9b47588
+ after
+ 7a31ae95dc110751.f0b863f2720aa364.cb236917f585af97.399b3186d8adc9f7
+ 0000000000000000.0000000000000000.34dc96e90a7a5069.399b318627523609
+ 4b2d50b0a199d533.72ab03abab031cb0.c9d707bcb521dbc3.8e295b33436e3f48
+ e0b1d435904e31b1.14465fceb25510bb.affd8a342eb73a25.f5781fa00f9a2535
+ aa315255b9b47588
+
+VMOVHLPS_128(reg)
+ before
+ 0aa2f0c0dd476ef0.b84974440309d6c7.73b268b1269acd43.aa122d01dc8ec34a
+ 6f15f54b18df4a17.afc0acc916d780a2.ea3a1abea25e90f5.96e0690ddbb1325d
+ 36d75e64050946a9.a1e4f8b1e4c4ea6e.d42c7163c32d947c.4f34bb46482d458b
+ bb35267541509e54.6a7fd4e68adad156.8fd26a0b24941685.b1d9a0973e0db6ff
+ 989d93ecda5d42e6
+ after
+ 0000000000000000.0000000000000000.ea3a1abea25e90f5.d42c7163c32d947c
+ 6f15f54b18df4a17.afc0acc916d780a2.ea3a1abea25e90f5.96e0690ddbb1325d
+ 36d75e64050946a9.a1e4f8b1e4c4ea6e.d42c7163c32d947c.4f34bb46482d458b
+ bb35267541509e54.6a7fd4e68adad156.8fd26a0b24941685.b1d9a0973e0db6ff
+ 989d93ecda5d42e6
+VMOVHLPS_128(mem)
+ before
+ e04b1031372aa56c.5a7849ec67418dc1.e65ebd552327f187.75790021611f52bb
+ 65ae9452727f9abc.6fefc3341466509f.f14d2eebcbb7052c.e46d2f13175884cb
+ 02939a3ba668de03.56e590b9e34d2398.6718a3939f94cb72.36f9f34ce2cde861
+ 95c69dd8f0f22d6c.6ba5ade771824158.238a9838bbccfc84.c96b49385d09b928
+ f70d2c44249934cd
+ after
+ e04b1031372aa56c.5a7849ec67418dc1.e65ebd552327f187.75790021611f52bb
+ 65ae9452727f9abc.6fefc3341466509f.f14d2eebcbb7052c.e46d2f13175884cb
+ 02939a3ba668de03.56e590b9e34d2398.6718a3939f94cb72.36f9f34ce2cde861
+ 95c69dd8f0f22d6c.6ba5ade771824158.238a9838bbccfc84.c96b49385d09b928
+ f70d2c44249934cd
+
+VMOVHLPS_128(reg)
+ before
+ 1e2d98dad40894fc.f9131b166b284224.0a7d152b5990e78d.037189c8396b5790
+ 9815896708e21760.0a4690df3416db57.8fb7c4ef380351e0.e297f32e387b97bf
+ c212fc585db4f7a6.a32a762166c9b230.55a0b6a0a967bb00.9cc95156d20a7740
+ f96feb176e097079.a28d4bc61d4c83dc.ba84e8ab48496097.0cd31f2c2324b33d
+ 1081da9c48d309e2
+ after
+ 0000000000000000.0000000000000000.8fb7c4ef380351e0.55a0b6a0a967bb00
+ 9815896708e21760.0a4690df3416db57.8fb7c4ef380351e0.e297f32e387b97bf
+ c212fc585db4f7a6.a32a762166c9b230.55a0b6a0a967bb00.9cc95156d20a7740
+ f96feb176e097079.a28d4bc61d4c83dc.ba84e8ab48496097.0cd31f2c2324b33d
+ 1081da9c48d309e2
+VMOVHLPS_128(mem)
+ before
+ 839ffc935c25335c.977a5412d86dc086.e2398abc76ab0c86.19ae557ab2347e51
+ 40f803fb7c26eed7.f97d32b4366d2178.3efbafee8df3075b.ce6cf97b83b54edb
+ 255a6ac1c3e0f67e.7bc682682594d0fc.949f37487d2f3186.3508d01956570fe1
+ 0d8fadd24d62067e.7a9f3e9c406e08be.bff19cb6626b4534.a9cfd6c0c7a6fb0e
+ 880d08dc732e4f0f
+ after
+ 839ffc935c25335c.977a5412d86dc086.e2398abc76ab0c86.19ae557ab2347e51
+ 40f803fb7c26eed7.f97d32b4366d2178.3efbafee8df3075b.ce6cf97b83b54edb
+ 255a6ac1c3e0f67e.7bc682682594d0fc.949f37487d2f3186.3508d01956570fe1
+ 0d8fadd24d62067e.7a9f3e9c406e08be.bff19cb6626b4534.a9cfd6c0c7a6fb0e
+ 880d08dc732e4f0f
+
+VMOVHLPS_128(reg)
+ before
+ 2d0e61d9f67c4790.d364491938b5dc03.505564bb24880769.9abd5c2459b40191
+ f31edd23ea1c1e3c.55a5b8819de73138.5a34ef316c6d07aa.03cef27e7d151fc8
+ 38897826ee9811c0.6d1e78f89a03c449.f487db6bb4a9452c.d4f1dab0eb9b5b06
+ 569a2f4e9b7e5cc7.f89a04694b154f64.7a9c25d39ac9fc9c.ebf391a7be517377
+ 229e924d13432146
+ after
+ 0000000000000000.0000000000000000.5a34ef316c6d07aa.f487db6bb4a9452c
+ f31edd23ea1c1e3c.55a5b8819de73138.5a34ef316c6d07aa.03cef27e7d151fc8
+ 38897826ee9811c0.6d1e78f89a03c449.f487db6bb4a9452c.d4f1dab0eb9b5b06
+ 569a2f4e9b7e5cc7.f89a04694b154f64.7a9c25d39ac9fc9c.ebf391a7be517377
+ 229e924d13432146
+VMOVHLPS_128(mem)
+ before
+ 56bf5990057d229f.ab9efd0890593bfe.d3e7d9c0cb2a8fb3.48bdc7d6b75869a6
+ 6421625bb10c31b0.91e1debe66b6e910.d8cf71e9364d4062.ba37bfe1a9e3c8f5
+ 2692299932fb0ca3.66afcedebc20a3aa.e41f4ad1a98b1d9e.2c56085e0bf55536
+ 79dc2b38a5576da4.8454c9d32b23a578.d4a3df6240efe493.fa669ebb7a1a4b14
+ 80b37e6392dee73c
+ after
+ 56bf5990057d229f.ab9efd0890593bfe.d3e7d9c0cb2a8fb3.48bdc7d6b75869a6
+ 6421625bb10c31b0.91e1debe66b6e910.d8cf71e9364d4062.ba37bfe1a9e3c8f5
+ 2692299932fb0ca3.66afcedebc20a3aa.e41f4ad1a98b1d9e.2c56085e0bf55536
+ 79dc2b38a5576da4.8454c9d32b23a578.d4a3df6240efe493.fa669ebb7a1a4b14
+ 80b37e6392dee73c
+
+VMOVQ_XMM_to_IREG64(reg)
+ before
+ 1a89a3c2eece655a.3acce223252a10e0.481ccc09514c2a25.8227ac8915854f6c
+ 243309442a750119.432ecc46ce83b383.0f52d2ebca266f5e.cb762d3347591a56
+ f9feac55e360f625.71ce658dbd6b10b8.3344d7e7313db0cf.8b5edf4af078027c
+ f7368861b419812c.a07827e50ef0e4ac.113cd769221e2923.9fa93dbc2cedc40b
+ e125c37418c5192f
+ after
+ 1a89a3c2eece655a.3acce223252a10e0.481ccc09514c2a25.8227ac8915854f6c
+ 243309442a750119.432ecc46ce83b383.0f52d2ebca266f5e.cb762d3347591a56
+ f9feac55e360f625.71ce658dbd6b10b8.3344d7e7313db0cf.8b5edf4af078027c
+ f7368861b419812c.a07827e50ef0e4ac.113cd769221e2923.9fa93dbc2cedc40b
+ 8227ac8915854f6c
+VMOVQ_XMM_to_IREG64(mem)
+ before
+ 2e9ced5ecf0bc013.79279ad43a2fded8.acf89038dc1deb8a.0687cfdb3a541506
+ 62da38666dcb73e4.db1ddd1a102b48d5.71191b7343ffe07f.6c71b9aa156bb126
+ 59ad1f781012efcd.78644da0d29bfcd0.cba9448360a180b7.a04693424ef0392c
+ efe01d80d1ebf0fb.ae47e6d01e0a3675.967287524f0f875d.fe515810816ee9c7
+ e2df057e4b71fca1
+ after
+ 2e9ced5ecf0bc013.79279ad43a2fded8.acf89038dc1deb8a.0687cfdb3a541506
+ 62da38666dcb73e4.db1ddd1a102b48d5.71191b7343ffe07f.6c71b9aa156bb126
+ 59ad1f781012efcd.78644da0d29bfcd0.cba9448360a180b7.a04693424ef0392c
+ efe01d80d1ebf0fb.ae47e6d01e0a3675.967287524f0f875d.fe515810816ee9c7
+ e2df057e4b71fca1
+
+VMOVQ_XMM_to_IREG64(reg)
+ before
+ a93d94fa4786af66.003eb16ace62319a.d813a4188d05316f.ae4161ce2b56b09e
+ adb503ef12383dc4.6894542323836fd5.511584e3bd172b6b.efe14de21081b9a5
+ 4b944dc94714e464.03ae8495eb5b66d9.7797819c4acc5e15.3520c77a1b9c5c9f
+ df256ff483a4def5.ad58bbae42f6d1d1.a4e697b1cfb00618.5cc94b8267b355b8
+ 40a755e611d3621b
+ after
+ a93d94fa4786af66.003eb16ace62319a.d813a4188d05316f.ae4161ce2b56b09e
+ adb503ef12383dc4.6894542323836fd5.511584e3bd172b6b.efe14de21081b9a5
+ 4b944dc94714e464.03ae8495eb5b66d9.7797819c4acc5e15.3520c77a1b9c5c9f
+ df256ff483a4def5.ad58bbae42f6d1d1.a4e697b1cfb00618.5cc94b8267b355b8
+ ae4161ce2b56b09e
+VMOVQ_XMM_to_IREG64(mem)
+ before
+ bd87629234083df5.c5b663dc61766721.425e7858455e6eea.364dc38de8506121
+ af35ed72ec5ca271.599227ed7e16bd94.9e8c348110a1f650.871aff9c3238a9db
+ f27d727357dd4fbc.f704b693750f1afc.9cad6c14becb282e.f597494a49f21bf3
+ 612b6d7f8e97fe01.fa590c3ae3edbb02.1a8f9dfd6be6bfb1.da119c04c70cf214
+ 93d4f4344b126ceb
+ after
+ bd87629234083df5.c5b663dc61766721.425e7858455e6eea.364dc38de8506121
+ af35ed72ec5ca271.599227ed7e16bd94.9e8c348110a1f650.871aff9c3238a9db
+ f27d727357dd4fbc.f704b693750f1afc.9cad6c14becb282e.f597494a49f21bf3
+ 612b6d7f8e97fe01.fa590c3ae3edbb02.1a8f9dfd6be6bfb1.da119c04c70cf214
+ 93d4f4344b126ceb
+
+VMOVQ_XMM_to_IREG64(reg)
+ before
+ 7d2c4e476f8ec324.da0a5b84af946c6e.c0dd254f633cdc55.f3fc422834007604
+ f265a4aacf0e346a.38e8b66cd6e3552c.a4dcfe3c9189b89f.03c1d78134250954
+ 4fcbf4c8081efa6a.568ffc251e8d746a.02a2916f0a5f8c8c.25aad8f4885f36cc
+ f0a9390cb54852d0.12cca99aa3a08651.367adc526a4b94c9.3782c26d4bbcb799
+ 131710d99a4849e7
+ after
+ 7d2c4e476f8ec324.da0a5b84af946c6e.c0dd254f633cdc55.f3fc422834007604
+ f265a4aacf0e346a.38e8b66cd6e3552c.a4dcfe3c9189b89f.03c1d78134250954
+ 4fcbf4c8081efa6a.568ffc251e8d746a.02a2916f0a5f8c8c.25aad8f4885f36cc
+ f0a9390cb54852d0.12cca99aa3a08651.367adc526a4b94c9.3782c26d4bbcb799
+ f3fc422834007604
+VMOVQ_XMM_to_IREG64(mem)
+ before
+ 97333e22900ea8e1.324c70e4721a7847.476b37b782274710.9bb1db534cd80c02
+ 9ea3c8364a1a8fb4.6f0193bbdd20a87b.d0382468d72e73d1.8f9488dd4c922fe2
+ 03332affe378bc8c.0412a0fd8fe41d19.8bffea99bdc2c5c1.6d6de15c07053a16
+ a4afe16b7735e894.4dcb921626f414cd.528b073650eefa0b.9089e13c18be694a
+ 563384e91c48f729
+ after
+ 97333e22900ea8e1.324c70e4721a7847.476b37b782274710.9bb1db534cd80c02
+ 9ea3c8364a1a8fb4.6f0193bbdd20a87b.d0382468d72e73d1.8f9488dd4c922fe2
+ 03332affe378bc8c.0412a0fd8fe41d19.8bffea99bdc2c5c1.6d6de15c07053a16
+ a4afe16b7735e894.4dcb921626f414cd.528b073650eefa0b.9089e13c18be694a
+ 563384e91c48f729
+
+VMOVQ_XMMorMEM64_to_XMM(reg)
+ before
+ 1ab9c6cfaf302160.5be36865235cd2f9.a67a65723edcc943.03aaf72badbecedc
+ 3765a45b6b01239a.059b3bd903f934e6.6b6a167e72277726.78263465ef3ffc5f
+ 0b8518f7ef473984.7fa2d6b33219cb88.f8e69fa45e615c22.8fcc3cce337c41c1
+ f0632011d48f9ec9.a3c5b6dfccc7530a.a93bfe529f16b1e4.22688a549482592e
+ 0ec59ae22f5c00d1
+ after
+ 1ab9c6cfaf302160.5be36865235cd2f9.a67a65723edcc943.03aaf72badbecedc
+ 0000000000000000.0000000000000000.0000000000000000.03aaf72badbecedc
+ 0b8518f7ef473984.7fa2d6b33219cb88.f8e69fa45e615c22.8fcc3cce337c41c1
+ f0632011d48f9ec9.a3c5b6dfccc7530a.a93bfe529f16b1e4.22688a549482592e
+ 0ec59ae22f5c00d1
+VMOVQ_XMMorMEM64_to_XMM(mem)
+ before
+ 30b1e8631f16f1d7.434cb713b8648f16.4fd15649ee108799.dab52ef2d1d3b518
+ 62f6f1c580bce96c.618cda6b37524817.5d9032deb4ff2561.e7a02cf28f23a26a
+ 816130f3705ba4bb.a46e8484ece60477.aacec68839a0e78d.2c48f2bd7592b684
+ 69bf21d908feddf0.6a40b0ca74ab00e3.12598e3499ff894a.05f87ebe20ad2a15
+ cefecb632bff3dc7
+ after
+ 30b1e8631f16f1d7.434cb713b8648f16.4fd15649ee108799.dab52ef2d1d3b518
+ 0000000000000000.0000000000000000.0000000000000000.dab52ef2d1d3b518
+ 816130f3705ba4bb.a46e8484ece60477.aacec68839a0e78d.2c48f2bd7592b684
+ 69bf21d908feddf0.6a40b0ca74ab00e3.12598e3499ff894a.05f87ebe20ad2a15
+ cefecb632bff3dc7
+
+VMOVQ_XMMorMEM64_to_XMM(reg)
+ before
+ e3a4d51733152947.f7d9406366b25239.0d4c5ca96a2d7807.72fb07cff129c8c3
+ 9f379847d37a2b40.057e0a7ea682bdbf.eadf848d6af9a88e.a482ac445c2a6025
+ 6003115da8ba7f5f.7079f914e37adab1.5e4522e2119acb24.85b8f97ff70c0d9c
+ 81543bc64d626050.14958b1239a76739.c3ca3414fb9c1e77.f16a6a6bdddd8b53
+ c4647cf62ba89577
+ after
+ e3a4d51733152947.f7d9406366b25239.0d4c5ca96a2d7807.72fb07cff129c8c3
+ 0000000000000000.0000000000000000.0000000000000000.72fb07cff129c8c3
+ 6003115da8ba7f5f.7079f914e37adab1.5e4522e2119acb24.85b8f97ff70c0d9c
+ 81543bc64d626050.14958b1239a76739.c3ca3414fb9c1e77.f16a6a6bdddd8b53
+ c4647cf62ba89577
+VMOVQ_XMMorMEM64_to_XMM(mem)
+ before
+ da72a90bfc7ae833.5e7512ef5ffc0bbe.cda03b65c5131e83.76bab590c38cdd30
+ 0f5f6f976c5e40b4.52b492427917bc56.776486f7a2cdbbbd.d360a1c005f543fe
+ 3ff94a8498605826.bb5bb82d383cafc3.eeaee6b6eddefc10.360af4125e638d8b
+ 460ab4bf9c8dedb4.f3b77e1a37f91fb2.0e4ad98dc2549bab.fb02abf06963f783
+ 7e95c1c8c380bd94
+ after
+ da72a90bfc7ae833.5e7512ef5ffc0bbe.cda03b65c5131e83.76bab590c38cdd30
+ 0000000000000000.0000000000000000.0000000000000000.76bab590c38cdd30
+ 3ff94a8498605826.bb5bb82d383cafc3.eeaee6b6eddefc10.360af4125e638d8b
+ 460ab4bf9c8dedb4.f3b77e1a37f91fb2.0e4ad98dc2549bab.fb02abf06963f783
+ 7e95c1c8c380bd94
+
+VMOVQ_XMMorMEM64_to_XMM(reg)
+ before
+ 1b0f320507461a67.005f2b3593f0bb8b.5814e27712d949ce.b303da683b3b55b8
+ 2ebcfa13d2424bab.49c429d09a957dd6.44bedfaf666969c4.b9a76533779de663
+ 13e7165ebfff8c0a.fd052c7ecb88f0c2.1501722ecf34ba40.fc00f7da8f8809d9
+ 26de80526b0a1930.f8edb02a45d6d07b.25299560e8c679ed.58db0a49a1077b46
+ a8041c6cc927f8d6
+ after
+ 1b0f320507461a67.005f2b3593f0bb8b.5814e27712d949ce.b303da683b3b55b8
+ 0000000000000000.0000000000000000.0000000000000000.b303da683b3b55b8
+ 13e7165ebfff8c0a.fd052c7ecb88f0c2.1501722ecf34ba40.fc00f7da8f8809d9
+ 26de80526b0a1930.f8edb02a45d6d07b.25299560e8c679ed.58db0a49a1077b46
+ a8041c6cc927f8d6
+VMOVQ_XMMorMEM64_to_XMM(mem)
+ before
+ ca47a83022f33bb4.c3eb365b71ee2dcb.154a2fbf228bd92c.d28146b14dace278
+ 99702b7fc977020c.465b33e66e370584.32e6272b7eb1c702.7656808e9b71318d
+ f14b1f47d9c0070b.0b7a745dfd71dd0a.2a8e135976575528.6ff43f616da1a1d7
+ ada302726ed906dd.6e94f32dba29f007.d90e6f3525863fcb.17a7809760c96f02
+ cbbb3d9d0f74d7bc
+ after
+ ca47a83022f33bb4.c3eb365b71ee2dcb.154a2fbf228bd92c.d28146b14dace278
+ 0000000000000000.0000000000000000.0000000000000000.d28146b14dace278
+ f14b1f47d9c0070b.0b7a745dfd71dd0a.2a8e135976575528.6ff43f616da1a1d7
+ ada302726ed906dd.6e94f32dba29f007.d90e6f3525863fcb.17a7809760c96f02
+ cbbb3d9d0f74d7bc
+
+VCVTTSS2SI_32(reg)
+ before
+ e87b74de172e14af.ab454feea6cfbdad.cbf5aec342ea7b27.1a32b7aca84c4317
+ c83520c513846387.c6fd82a69aace6a8.7de8a08a3141ba17.cbc668a81ab41b37
+ c8333ec0a00100f1.d9971786687e3efa.e2bbc5ee22b9e883.c795fd1698ca8457
+ 44c2c83a59312799.c2df8b7a2b5180ce.55b81a5ab1de4316.e96df2e33d9b3aa5
+ 0f18c3f92632f84b
+ after
+ e87b74de172e14af.ab454feea6cfbdad.cbf5aec342ea7b27.1a32b7aca84c4317
+ c83520c513846387.c6fd82a69aace6a8.7de8a08a3141ba17.cbc668a81ab41b37
+ c8333ec0a00100f1.d9971786687e3efa.e2bbc5ee22b9e883.c795fd1698ca8457
+ 44c2c83a59312799.c2df8b7a2b5180ce.55b81a5ab1de4316.e96df2e33d9b3aa5
+ 0000000000000000
+VCVTTSS2SI_32(mem)
+ before
+ 1363ec466e9b7c75.982ebc9fdba1132a.5ba1596e00306a50.322c993c7b3c057d
+ d31aeab532e37f50.20c3155bc1dc0151.82a8fd4e0327b6ae.d46340ff1b606a64
+ 290938318d15c008.39cdcfdaa76e2db9.11c2f3074e422012.99a90a102ed5b076
+ f3fb52a89b3ef9c8.3d97e7892ae4d30f.e6b9b883008e66a8.db49f4d950281160
+ f891f8c71be4cacd
+ after
+ 1363ec466e9b7c75.982ebc9fdba1132a.5ba1596e00306a50.322c993c7b3c057d
+ d31aeab532e37f50.20c3155bc1dc0151.82a8fd4e0327b6ae.d46340ff1b606a64
+ 290938318d15c008.39cdcfdaa76e2db9.11c2f3074e422012.99a90a102ed5b076
+ f3fb52a89b3ef9c8.3d97e7892ae4d30f.e6b9b883008e66a8.db49f4d950281160
+ 0000000080000000
+
+VCVTTSS2SI_32(reg)
+ before
+ 4acb14472e95166a.0bbeb4057968e7bd.896f57d2e6c92eff.db5ac6af3216429d
+ 2f4443c322c833e2.4e1cdb3543a24612.799f1d2276aa7b34.cd719b7803e6711d
+ 014881a995085be2.99e2422213f5d1f4.697434e67611f55b.99c9b2c98c0bae53
+ 1e23cb6323e1ca16.c6dc65b9086f468f.b53a9989838cda1f.1930888dec90b76c
+ 2a7097b23c824693
+ after
+ 4acb14472e95166a.0bbeb4057968e7bd.896f57d2e6c92eff.db5ac6af3216429d
+ 2f4443c322c833e2.4e1cdb3543a24612.799f1d2276aa7b34.cd719b7803e6711d
+ 014881a995085be2.99e2422213f5d1f4.697434e67611f55b.99c9b2c98c0bae53
+ 1e23cb6323e1ca16.c6dc65b9086f468f.b53a9989838cda1f.1930888dec90b76c
+ 0000000000000000
+VCVTTSS2SI_32(mem)
+ before
+ a9565d239aec17f5.e0201b5f67e0be29.b2d6c0e73c1b5f0e.b83d467639a7642d
+ 70af55cc22dae8be.a48d6f08fe9071c8.399ccf96cb06d89e.d0c8391b32edd031
+ 5c44fb99ef597319.c7b4c2ca837d209f.38f90fb4d23a6e6b.58286de30dea59d6
+ 49e4cc771d737533.a3e2101192340659.89bafb2b6cc6dda0.acaade3a632a3cc8
+ 2898888cd33ab5b5
+ after
+ a9565d239aec17f5.e0201b5f67e0be29.b2d6c0e73c1b5f0e.b83d467639a7642d
+ 70af55cc22dae8be.a48d6f08fe9071c8.399ccf96cb06d89e.d0c8391b32edd031
+ 5c44fb99ef597319.c7b4c2ca837d209f.38f90fb4d23a6e6b.58286de30dea59d6
+ 49e4cc771d737533.a3e2101192340659.89bafb2b6cc6dda0.acaade3a632a3cc8
+ 0000000000000000
+
+VCVTTSS2SI_32(reg)
+ before
+ 273f6846f6a50047.135a4350c937aa38.95635649c84061a2.09ac0fe9b6b3e169
+ 07eb79d26bf8582a.9671dc110faecd53.fa838fdfc12d6b28.9499c7d9cb0f36f3
+ 23e7b79dcbbefb0b.aff713a70ae69bb0.2c8eb63d18886194.064da0e7c8e5976a
+ d6811e14b4832296.38b664fdd6ead07c.88d0cad169dc7e95.3b9614ffc842c1fa
+ 0f3fa10de83170ce
+ after
+ 273f6846f6a50047.135a4350c937aa38.95635649c84061a2.09ac0fe9b6b3e169
+ 07eb79d26bf8582a.9671dc110faecd53.fa838fdfc12d6b28.9499c7d9cb0f36f3
+ 23e7b79dcbbefb0b.aff713a70ae69bb0.2c8eb63d18886194.064da0e7c8e5976a
+ d6811e14b4832296.38b664fdd6ead07c.88d0cad169dc7e95.3b9614ffc842c1fa
+ 00000000ff70c90d
+VCVTTSS2SI_32(mem)
+ before
+ 5e13c2fd43be5f12.7e03aba2c2d40c76.0e7b4cfe90c727e3.6a94c40551b5ffd5
+ 04dff4bcf5f64bf3.76ba58b2903bf358.0d12459853885e10.2e27a2476ba02000
+ dd6fb1341be4f09d.19f223b2bb4714e8.1046cdb63c392e30.30d55e0154281dc4
+ c58f7753d194093c.c5f7070dde81abd1.f5e5604466e7566f.cceaf6a1a7d931ca
+ 5eb26692014099c1
+ after
+ 5e13c2fd43be5f12.7e03aba2c2d40c76.0e7b4cfe90c727e3.6a94c40551b5ffd5
+ 04dff4bcf5f64bf3.76ba58b2903bf358.0d12459853885e10.2e27a2476ba02000
+ dd6fb1341be4f09d.19f223b2bb4714e8.1046cdb63c392e30.30d55e0154281dc4
+ c58f7753d194093c.c5f7070dde81abd1.f5e5604466e7566f.cceaf6a1a7d931ca
+ 0000000080000000
+
+VPUNPCKLBW_128(reg)
+ before
+ 4279a840fde89153.980bc103321353fb.d415012f9577f3c0.97b9782eee9d91f8
+ d48aba17385e542c.32af0c325a6c8a06.a4970b847db42960.d28f9360ef679af8
+ 703297844d2c20f9.6e46d2cb66ab6a8a.8fcb237831c5895e.82332bc686522d9a
+ 72be3bf1d9e12f66.2a9e91ba71ddafb3.f3fb44774e354f65.8371bf4dce69080b
+ b015c8dfe4b8e577
+ after
+ 0000000000000000.0000000000000000.82d2338f2b93c660.86ef52672d9a9af8
+ d48aba17385e542c.32af0c325a6c8a06.a4970b847db42960.d28f9360ef679af8
+ 703297844d2c20f9.6e46d2cb66ab6a8a.8fcb237831c5895e.82332bc686522d9a
+ 72be3bf1d9e12f66.2a9e91ba71ddafb3.f3fb44774e354f65.8371bf4dce69080b
+ b015c8dfe4b8e577
+VPUNPCKLBW_128(mem)
+ before
+ e7ebc36ae34c8109.3678a2cb7706bd1f.4181c4eb980d14ac.2a746aee7090b622
+ 03be2dd9e73098ee.18acc97fc32908cf.8fbce74af64755a2.918292473163fb41
+ e05b81170d70e551.73a8ab775ad54a22.ef1b76c3a89830c1.8571b7f030395a6d
+ 598e3b127119255f.a5b74421d897c0c5.3f69ee42c90b5f34.608cd453069e0e53
+ 7f21e8de521f559e
+ after
+ e7ebc36ae34c8109.3678a2cb7706bd1f.4181c4eb980d14ac.2a746aee7090b622
+ 03be2dd9e73098ee.18acc97fc32908cf.8fbce74af64755a2.918292473163fb41
+ 0000000000000000.0000000000000000.2a9174826a92ee47.70319063b6fb2241
+ 598e3b127119255f.a5b74421d897c0c5.3f69ee42c90b5f34.608cd453069e0e53
+ 7f21e8de521f559e
+
+VPUNPCKLBW_128(reg)
+ before
+ 3e7aecfcad4769fb.4c23d8b52e361443.092490e8d8f9a564.5a74c9b476ac9f28
+ f9e4dd19b5a28616.93e6d2ec60d36e2a.fb3c8b38f68a36aa.1b068503ca88acc8
+ 0dabb8a106bde99a.0ca3a7a324fdee40.d64b327dcfd3af44.60ec9e1de2aa4141
+ d41b78003b23cf34.9125d2c695bf51b0.f89d8023fe624cde.03f38eecd91e1bbe
+ e2e4d35eccf1f66c
+ after
+ 0000000000000000.0000000000000000.601bec069e851d03.e2caaa8841ac41c8
+ f9e4dd19b5a28616.93e6d2ec60d36e2a.fb3c8b38f68a36aa.1b068503ca88acc8
+ 0dabb8a106bde99a.0ca3a7a324fdee40.d64b327dcfd3af44.60ec9e1de2aa4141
+ d41b78003b23cf34.9125d2c695bf51b0.f89d8023fe624cde.03f38eecd91e1bbe
+ e2e4d35eccf1f66c
+VPUNPCKLBW_128(mem)
+ before
+ d78ee85ed62e8e77.ab8019a2f1617190.003acf42d02653a7.bc7e719620c24823
+ c0bc49d813e29e0a.ee2598f3c3010e59.33ac1b01f03caf51.7d390142d080e1c0
+ 773972b8a018e352.f957f0604d91e03b.084831f1121022d9.991c2d93ab275060
+ d9d2e0ea99dc197b.28631c532c9d24e3.59da8dfc51ab686c.6a71f0f64c43d4b0
+ 4e8546d55061a75b
+ after
+ d78ee85ed62e8e77.ab8019a2f1617190.003acf42d02653a7.bc7e719620c24823
+ c0bc49d813e29e0a.ee2598f3c3010e59.33ac1b01f03caf51.7d390142d080e1c0
+ 0000000000000000.0000000000000000.bc7d7e3971019642.20d0c28048e123c0
+ d9d2e0ea99dc197b.28631c532c9d24e3.59da8dfc51ab686c.6a71f0f64c43d4b0
+ 4e8546d55061a75b
+
+VPUNPCKLBW_128(reg)
+ before
+ 9fa42b9e520c060e.c3540d5a193afbb0.d7931a3afcb016fd.032dab10ca1b3d35
+ bb1a9bbcefd02d75.0f8977f53c3f471d.6234e6805856f134.e30f0718986b5c61
+ fc33939bc23a573b.9a3d9aa51ff6b6f0.25917a90dc1bf235.d34a1effd8a8821b
+ bf3a0ea668d5c20d.403ef058dd6c0752.7cf8d4d8258c55ac.b0ab6bb3a5dc6b90
+ 56ff6a1f1b16d2ec
+ after
+ 0000000000000000.0000000000000000.d3e34a0f1e07ff18.d898a86b825c1b61
+ bb1a9bbcefd02d75.0f8977f53c3f471d.6234e6805856f134.e30f0718986b5c61
+ fc33939bc23a573b.9a3d9aa51ff6b6f0.25917a90dc1bf235.d34a1effd8a8821b
+ bf3a0ea668d5c20d.403ef058dd6c0752.7cf8d4d8258c55ac.b0ab6bb3a5dc6b90
+ 56ff6a1f1b16d2ec
+VPUNPCKLBW_128(mem)
+ before
+ a20f9730585f755a.617d084b7c2da897.de57f7f893acf472.c2b3efc3ce345544
+ 6eaa6ed075c50e07.3c467df69ace4584.4e532a735cc23a7a.5510c7bd74a030aa
+ 979b6cec9053591e.ade269115f46d680.6dff05b455ba9596.90595932b25b2089
+ f9ad0c71c41613cc.109dc909671e9738.172704a799a1c1f4.cfdb9f8e25f1618e
+ 6de1973e68ee3165
+ after
+ a20f9730585f755a.617d084b7c2da897.de57f7f893acf472.c2b3efc3ce345544
+ 6eaa6ed075c50e07.3c467df69ace4584.4e532a735cc23a7a.5510c7bd74a030aa
+ 0000000000000000.0000000000000000.c255b310efc7c3bd.ce7434a0553044aa
+ f9ad0c71c41613cc.109dc909671e9738.172704a799a1c1f4.cfdb9f8e25f1618e
+ 6de1973e68ee3165
+
+VPUNPCKHBW_128(reg)
+ before
+ c8b93cac18dfcab9.70aeca492e19f93d.c2c2984a4de4c458.2897a338458279bd
+ 3bad8a46d04f6937.d8682262ea68c49c.1d9fd241ad23998c.7c1b5f53746a7a20
+ 210b7e762ccb498a.0da891a613103316.7e7e74582467517f.ef7eb3e443647f47
+ d81d13aac9dea75f.eb3a9203c51c00d6.41ad78fd4d3d29dd.5d8e1bd7cd7c465e
+ a21514182ebf8993
+ after
+ 0000000000000000.0000000000000000.7e1d7e9f74d25841.24ad672351997f8c
+ 3bad8a46d04f6937.d8682262ea68c49c.1d9fd241ad23998c.7c1b5f53746a7a20
+ 210b7e762ccb498a.0da891a613103316.7e7e74582467517f.ef7eb3e443647f47
+ d81d13aac9dea75f.eb3a9203c51c00d6.41ad78fd4d3d29dd.5d8e1bd7cd7c465e
+ a21514182ebf8993
+VPUNPCKHBW_128(mem)
+ before
+ 9ae018948338050f.bb30444d4314bf61.4ee9a1641d98e809.c276dc9bc5305c54
+ 21bba535e8f37501.259010cb35facd3d.12833ab53690a7db.5d269b9e27cc288d
+ 137236e978fd9693.748970903b1b0d9f.13d2d9e22d11f877.6e08b172109ec737
+ 4cd0479b4f6124f1.02666208f203ba32.2da3fbd71d27980a.516a1b831b3176fc
+ 6296d43de5127088
+ after
+ 9ae018948338050f.bb30444d4314bf61.4ee9a1641d98e809.c276dc9bc5305c54
+ 21bba535e8f37501.259010cb35facd3d.12833ab53690a7db.5d269b9e27cc288d
+ 0000000000000000.0000000000000000.4e12e983a13a64b5.1d369890e8a709db
+ 4cd0479b4f6124f1.02666208f203ba32.2da3fbd71d27980a.516a1b831b3176fc
+ 6296d43de5127088
+
+VPUNPCKHBW_128(reg)
+ before
+ fddad70c09cbf288.a7a355378a2bdb48.2c74e09ff63f11a3.3bc21b8123dc43bf
+ 7e80235c24ea38a8.02b5dba8456876c4.4f00e8c1e2594d9e.1bfbb5ca5a3eb4c3
+ 41d5b19ad1fb7e94.38d354dc9a23b390.c55476db52e0abce.a81a459fde59a942
+ a1257e30ac89fff7.25c93fbfa8684bd9.ecbd8457e35d67df.beeb48edcc37dc67
+ 3839399f40e6095e
+ after
+ 0000000000000000.0000000000000000.c54f540076e8dbc1.52e2e059ab4dce9e
+ 7e80235c24ea38a8.02b5dba8456876c4.4f00e8c1e2594d9e.1bfbb5ca5a3eb4c3
+ 41d5b19ad1fb7e94.38d354dc9a23b390.c55476db52e0abce.a81a459fde59a942
+ a1257e30ac89fff7.25c93fbfa8684bd9.ecbd8457e35d67df.beeb48edcc37dc67
+ 3839399f40e6095e
+VPUNPCKHBW_128(mem)
+ before
+ f4d193a05572ee55.fcbb878c5220f97d.a463153b8844fdcb.1e8610a3305ebd7f
+ cd7fd5de27e64576.ade5c7185f4ca5d3.936d543d59c28391.b8fd1529d66fe957
+ 9e0f7844d34ecbed.10ed3a426e9a42a5.cdb276b134ee9a58.166c8f57701a2616
+ 454dfabe75b63be7.8020dd751b960a9e.2d00f98438d5fe4b.95217a989bedb166
+ 8f66d358f274c5f4
+ after
+ f4d193a05572ee55.fcbb878c5220f97d.a463153b8844fdcb.1e8610a3305ebd7f
+ cd7fd5de27e64576.ade5c7185f4ca5d3.936d543d59c28391.b8fd1529d66fe957
+ 0000000000000000.0000000000000000.a493636d15543b3d.885944c2fd83cb91
+ 454dfabe75b63be7.8020dd751b960a9e.2d00f98438d5fe4b.95217a989bedb166
+ 8f66d358f274c5f4
+
+VPUNPCKHBW_128(reg)
+ before
+ 61889403123aa06b.9c05d638282b5390.5bcbab1d03ca3a6b.912159a07e826a97
+ 67d3bb0596cb7c78.8102889e08b8cd13.fc379fa6c1c40eb8.d3e210f324029b67
+ fd9244ca1ab396c6.ce128cdd3269659d.beb3b87cf20fc130.d10f9c68465f4de9
+ 7f1329be3b7f2902.61ff5edfc14bd95a.ff8aef0b31389080.657478ebffa73c46
+ 6ddc20686be623ac
+ after
+ 0000000000000000.0000000000000000.befcb337b89f7ca6.f2c10fc4c10e30b8
+ 67d3bb0596cb7c78.8102889e08b8cd13.fc379fa6c1c40eb8.d3e210f324029b67
+ fd9244ca1ab396c6.ce128cdd3269659d.beb3b87cf20fc130.d10f9c68465f4de9
+ 7f1329be3b7f2902.61ff5edfc14bd95a.ff8aef0b31389080.657478ebffa73c46
+ 6ddc20686be623ac
+VPUNPCKHBW_128(mem)
+ before
+ c31510cba727bf47.49a0684e95ba72d8.14967b92d269e375.190741c01bcab753
+ 44e9c500cf76cc43.b786fbe4c3f0adf3.c5a35ee080d0401a.6a77ab054b517256
+ cd25b9f3fedf05cb.2511e1ee61ae1600.4ef183b7e88bab77.4c2728485e5afc34
+ 38956a90506f280c.ef8d13d60c7fe8aa.8c4e670225a6e2b5.1d61b4f3ef6f929a
+ 37714c749b1f7034
+ after
+ c31510cba727bf47.49a0684e95ba72d8.14967b92d269e375.190741c01bcab753
+ 44e9c500cf76cc43.b786fbe4c3f0adf3.c5a35ee080d0401a.6a77ab054b517256
+ 0000000000000000.0000000000000000.14c596a37b5e92e0.d28069d0e340751a
+ 38956a90506f280c.ef8d13d60c7fe8aa.8c4e670225a6e2b5.1d61b4f3ef6f929a
+ 37714c749b1f7034
+
+VMULSS_128(reg)
+ before
+ f8a5ea36fdf3d1ad.620553c4e231ee31.71468e0a5ff0609e.5c8484ac532d9f03
+ ba478ca5b279f2b2.2841f179cf321667.07884ff5f78bba87.986158a3902d9e8b
+ daa52d2d553d0fef.6414bf9d347d5ad9.0d9e510370df3213.1daf5ed2f5b19d79
+ b509ca3a82c9640f.f34b381a2d1e77b4.dfd590a0647503eb.c73b1226a0c656fb
+ 72d0f189ad77863b
+ after
+ 0000000000000000.0000000000000000.07884ff5f78bba87.986158a34670ead5
+ ba478ca5b279f2b2.2841f179cf321667.07884ff5f78bba87.986158a3902d9e8b
+ daa52d2d553d0fef.6414bf9d347d5ad9.0d9e510370df3213.1daf5ed2f5b19d79
+ b509ca3a82c9640f.f34b381a2d1e77b4.dfd590a0647503eb.c73b1226a0c656fb
+ 72d0f189ad77863b
+VMULSS_128(mem)
+ before
+ fa3c75e837d0e965.a5c05d38d6ab2cbe.b1b3daded4212924.d879093872db6abe
+ 3c491c305add3aa6.0716e493ed6fa4a9.7a1621d447932c54.56d6b637339ca336
+ 12c5614b33ab362a.37575ab8629f087c.2a4187e8a2803b71.b438950a4545e9ff
+ 597ac127dd46991c.92cebb11d1ca93e3.9dff8a0600f213a6.4deba11b446179c6
+ 7f3ad6d8cb7c8f37
+ after
+ fa3c75e837d0e965.a5c05d38d6ab2cbe.b1b3daded4212924.d879093872db6abe
+ 3c491c305add3aa6.0716e493ed6fa4a9.7a1621d447932c54.56d6b637339ca336
+ 0000000000000000.0000000000000000.7a1621d447932c54.56d6b637670640ef
+ 597ac127dd46991c.92cebb11d1ca93e3.9dff8a0600f213a6.4deba11b446179c6
+ 7f3ad6d8cb7c8f37
+
+VMULSS_128(reg)
+ before
+ a57331ab772266fd.ed35b6ae75b81ea9.72c9030cd7798389.af1ea51a7ef76f20
+ 1ae0ad02e3e03cc5.aac2bece170f83fc.34922f130f3a121a.3c685411379a0d0b
+ 3cce4648ab414b3b.6cec5472dd568142.34763a9416987c44.20aa14d548e8a792
+ 6589f8e96cd2cf0a.0e81f486e69ad7a6.cec120fa871fffb0.37b15f53ccecfae2
+ 5d46b378dfb2c126
+ after
+ 0000000000000000.0000000000000000.34922f130f3a121a.3c685411410c00a8
+ 1ae0ad02e3e03cc5.aac2bece170f83fc.34922f130f3a121a.3c685411379a0d0b
+ 3cce4648ab414b3b.6cec5472dd568142.34763a9416987c44.20aa14d548e8a792
+ 6589f8e96cd2cf0a.0e81f486e69ad7a6.cec120fa871fffb0.37b15f53ccecfae2
+ 5d46b378dfb2c126
+VMULSS_128(mem)
+ before
+ 6e388b2f9e47b98b.f35cbf51c21e06de.6e4b1bf64be64056.5ebfddb1ff5cd50d
+ 4652636324b69e3c.409598ec48b12a65.671743ae2b46777b.40bb6d2519da3a05
+ c15fb8028e0b2c67.aa7e7d269a187849.d5b1ea9b9fc73844.d003cdc272256c44
+ ba2d04f7f8531e35.8b646c6b55de2b36.94e58ba7c57441db.6ae1f8f4a5caa577
+ 6aa2ea284e54224a
+ after
+ 6e388b2f9e47b98b.f35cbf51c21e06de.6e4b1bf64be64056.5ebfddb1ff5cd50d
+ 4652636324b69e3c.409598ec48b12a65.671743ae2b46777b.40bb6d2519da3a05
+ 0000000000000000.0000000000000000.671743ae2b46777b.40bb6d25d9bc3f7a
+ ba2d04f7f8531e35.8b646c6b55de2b36.94e58ba7c57441db.6ae1f8f4a5caa577
+ 6aa2ea284e54224a
+
+VMULSS_128(reg)
+ before
+ 2b92a0c80b501f69.0f86c52e7d9932d5.41946127148f81d9.807fa3bfb9594c6c
+ 0bfd14417549d77e.9b37769339e92171.265756c774b8b4de.744bacd096831624
+ 652f44002acb8738.390c94124950aa35.97fc49b511e400f0.4e1424c579fd5b2f
+ 95732b70c6626b41.c7d09998c8d9874e.f0ce355f859fa3bc.e9a786897dd4d6b8
+ 20d04e0abe1244ec
+ after
+ 0000000000000000.0000000000000000.265756c774b8b4de.744bacd0d101bb93
+ 0bfd14417549d77e.9b37769339e92171.265756c774b8b4de.744bacd096831624
+ 652f44002acb8738.390c94124950aa35.97fc49b511e400f0.4e1424c579fd5b2f
+ 95732b70c6626b41.c7d09998c8d9874e.f0ce355f859fa3bc.e9a786897dd4d6b8
+ 20d04e0abe1244ec
+VMULSS_128(mem)
+ before
+ d15bf83359c561f7.f717c5fde49bbf46.2051030fd39075e8.8e1816306f76d7ed
+ d61401f069f9e904.e6650f122001bef2.1f594d648582302e.cb28e89468f4d930
+ 0dc7e42d0bb89740.c0aa031d1721a5f2.a2b5f384faba734d.0448a8f60ea5e531
+ 503f1dd75b1128d6.e0329f896486b0f2.8332725a4f45fb71.95c550c4fd16369b
+ daeade6ad0d2091b
+ after
+ d15bf83359c561f7.f717c5fde49bbf46.2051030fd39075e8.8e1816306f76d7ed
+ d61401f069f9e904.e6650f122001bef2.1f594d648582302e.cb28e89468f4d930
+ 0000000000000000.0000000000000000.1f594d648582302e.cb28e8947f800000
+ 503f1dd75b1128d6.e0329f896486b0f2.8332725a4f45fb71.95c550c4fd16369b
+ daeade6ad0d2091b
+
+VSUBSS_128(reg)
+ before
+ 2f054e5224659a5c.7d4a28d8730d58f3.a148dec3a4bc1a9d.a09945d1a02d84c5
+ f1619ae9945c240b.6eb2821d72bae2c2.613abc357250209f.d3b9e7d70881ca75
+ 7a49c09bbc42e5d4.0144a59371238370.7a52364c6bcdfea6.fa5dd757a44a88af
+ 270abbd539a41662.10cc0f248f54f729.4ade47752abff05c.ef508e3d8f967b9d
+ 8f608975e5705f6b
+ after
+ 0000000000000000.0000000000000000.613abc357250209f.d3b9e7d7244a88af
+ f1619ae9945c240b.6eb2821d72bae2c2.613abc357250209f.d3b9e7d70881ca75
+ 7a49c09bbc42e5d4.0144a59371238370.7a52364c6bcdfea6.fa5dd757a44a88af
+ 270abbd539a41662.10cc0f248f54f729.4ade47752abff05c.ef508e3d8f967b9d
+ 8f608975e5705f6b
+VSUBSS_128(mem)
+ before
+ b75745ecc3e4ef46.53f08702a70cf662.78153cbee55afa18.2b28eb1a4cb2316d
+ 41023d8c44ffe95a.5c47208da009bf7f.16eda64c9240476a.7b7d1ea96c33fe86
+ 0a2ced4285cd06d2.9d5b83e4c324af66.c41ecabaaf139b4b.9429dc8c27ce9353
+ efa3d2fba25805db.7277aa72aaebffc3.5f7625f45adeb2e6.d4772231180d2b7f
+ 95b5eb03dc7e03b7
+ after
+ b75745ecc3e4ef46.53f08702a70cf662.78153cbee55afa18.2b28eb1a4cb2316d
+ 41023d8c44ffe95a.5c47208da009bf7f.16eda64c9240476a.7b7d1ea96c33fe86
+ 0000000000000000.0000000000000000.16eda64c9240476a.7b7d1ea96c33fe86
+ efa3d2fba25805db.7277aa72aaebffc3.5f7625f45adeb2e6.d4772231180d2b7f
+ 95b5eb03dc7e03b7
+
+VSUBSS_128(reg)
+ before
+ 342d336e0ead57a6.ca3266a1b5aea0a0.37e993a3f1e9ee41.c4bf32e6afad4767
+ 0d2cf6de4a2463fa.78a42722ddda944e.48fb39e335abb68d.cdc66e7cc98c18fb
+ 7dfe31bf2d71625c.d5c6906933e99d11.01fa999e11bb9452.575653a2c488dfce
+ deefde7e5320917a.bd641e62d6e67714.bd32ad4022a8c43d.3e3d5f44bdad580c
+ 5e450d4fd00540e0
+ after
+ 0000000000000000.0000000000000000.48fb39e335abb68d.cdc66e7cc98bf6c3
+ 0d2cf6de4a2463fa.78a42722ddda944e.48fb39e335abb68d.cdc66e7cc98c18fb
+ 7dfe31bf2d71625c.d5c6906933e99d11.01fa999e11bb9452.575653a2c488dfce
+ deefde7e5320917a.bd641e62d6e67714.bd32ad4022a8c43d.3e3d5f44bdad580c
+ 5e450d4fd00540e0
+VSUBSS_128(mem)
+ before
+ 933cd9ad189e5476.8d4bfb8556bb2c00.0c4a4bf9dfdddd84.daef733503fb81fa
+ b9ec3f4cb1834dfb.e65d8442d5d06e9a.9e44951a6cda8c8c.b37de6ea51420834
+ ac22bc17b8c1ea9b.4573731f6aeb94f3.4f1d77b199ea3f59.a32703c9a7089597
+ 48aacaf94863e582.07d7c58ab197dab7.fba36daa8119b417.083ac440a1da64d1
+ 3d0327badc43b08c
+ after
+ 933cd9ad189e5476.8d4bfb8556bb2c00.0c4a4bf9dfdddd84.daef733503fb81fa
+ b9ec3f4cb1834dfb.e65d8442d5d06e9a.9e44951a6cda8c8c.b37de6ea51420834
+ 0000000000000000.0000000000000000.9e44951a6cda8c8c.b37de6ea51420834
+ 48aacaf94863e582.07d7c58ab197dab7.fba36daa8119b417.083ac440a1da64d1
+ 3d0327badc43b08c
+
+VSUBSS_128(reg)
+ before
+ 9dcc27a3f4cfb674.694fe7e07e75fbdb.86d677ed47607c93.7ea0f3f24171a5f1
+ 86e1c066840ab236.ebdf8fb77504e8d2.1fbc84b6c7d2b533.b4e18673f400cf14
+ 5290ee712881df7e.aa243c6a4a1b6794.2ed5e950ce7ac243.7932a11bb6d1edab
+ 5f24ae2f7dc07af7.82eb6ce518c6354d.0f6ca027f7e3df6e.a95fc0d4a4f1bce3
+ 20335f8cda6bf8e8
+ after
+ 0000000000000000.0000000000000000.1fbc84b6c7d2b533.b4e18673f400cf14
+ 86e1c066840ab236.ebdf8fb77504e8d2.1fbc84b6c7d2b533.b4e18673f400cf14
+ 5290ee712881df7e.aa243c6a4a1b6794.2ed5e950ce7ac243.7932a11bb6d1edab
+ 5f24ae2f7dc07af7.82eb6ce518c6354d.0f6ca027f7e3df6e.a95fc0d4a4f1bce3
+ 20335f8cda6bf8e8
+VSUBSS_128(mem)
+ before
+ ba7cfb2e734b5de5.07e8fb0d1f51bf4e.4f009a15fc120e28.1ecfa7a7df994860
+ 52040ea68b9ea607.a729d175a9c2ea2f.ec2f42e4110aad52.b748f93d212938c6
+ c69816e03f6f9179.9c332cd4b79f3645.3744e04074bad0f7.35249253591eec4c
+ f1048ec8aacad768.40520897e672e03c.0b0bf113402f3142.f6af6e562405a09e
+ 55358ab31e698f66
+ after
+ ba7cfb2e734b5de5.07e8fb0d1f51bf4e.4f009a15fc120e28.1ecfa7a7df994860
+ 52040ea68b9ea607.a729d175a9c2ea2f.ec2f42e4110aad52.b748f93d212938c6
+ 0000000000000000.0000000000000000.ec2f42e4110aad52.b748f93d5f994860
+ f1048ec8aacad768.40520897e672e03c.0b0bf113402f3142.f6af6e562405a09e
+ 55358ab31e698f66
+
+VADDSS_128(reg)
+ before
+ ae02e0d4e2d6f653.ae14f34ae9bc37ff.f0d26228d1c924c2.444fef4b91748c60
+ 5d616e270dd8110f.db94bf5217506b6b.09ff35f515303d80.bddd58d384959f7c
+ bda0301739fc1b47.534f70cd519330d8.e5247d694d316825.5481a796359f24c3
+ 2c09201005cd52a6.f11381a5b28f4271.e18e36ef165ae15b.e3075982bf9dd861
+ 483be8823e9b7681
+ after
+ 0000000000000000.0000000000000000.09ff35f515303d80.bddd58d3359f24c3
+ 5d616e270dd8110f.db94bf5217506b6b.09ff35f515303d80.bddd58d384959f7c
+ bda0301739fc1b47.534f70cd519330d8.e5247d694d316825.5481a796359f24c3
+ 2c09201005cd52a6.f11381a5b28f4271.e18e36ef165ae15b.e3075982bf9dd861
+ 483be8823e9b7681
+VADDSS_128(mem)
+ before
+ 5de9d282cfa6bc4f.05e93c7e0bd8f0d9.93aa6ec857525c63.59895df50b37e4ce
+ 00dc926f8dc964f9.a38c7fcde7a8318c.13e1b4205be83bda.aa61ede6c852ac2c
+ 0be2a53395112aa8.643ee56936c9536a.4f84cd9bda5c9b01.2e62e22eeb39761e
+ 5cc585bb0288cc8b.a34a6abe93c8901f.215f3724f1ba3805.42d8383a0d787e53
+ 420eeb74cc9a0075
+ after
+ 5de9d282cfa6bc4f.05e93c7e0bd8f0d9.93aa6ec857525c63.59895df50b37e4ce
+ 00dc926f8dc964f9.a38c7fcde7a8318c.13e1b4205be83bda.aa61ede6c852ac2c
+ 0000000000000000.0000000000000000.13e1b4205be83bda.aa61ede6c852ac2c
+ 5cc585bb0288cc8b.a34a6abe93c8901f.215f3724f1ba3805.42d8383a0d787e53
+ 420eeb74cc9a0075
+
+VADDSS_128(reg)
+ before
+ 8a52f849c42b3730.cd52b0f4f13d04cc.bbfe0b389b2f2559.673d6da7bc0ecd11
+ 76ee5a2690b76032.3c55a1c87d398f98.0aa4c244e98d4dc2.fbecec1056651752
+ 622f0d75cccbb624.8399d425c38a281a.ea898d4c1a6b4606.ba362e4bdbcad2f3
+ aa610da415f277b5.7fecc5f6de3b8d7f.b9f968bec9574ad2.81e8b144684ab921
+ 2acef0e719ef8a08
+ after
+ 0000000000000000.0000000000000000.0aa4c244e98d4dc2.fbecec10dbcab650
+ 76ee5a2690b76032.3c55a1c87d398f98.0aa4c244e98d4dc2.fbecec1056651752
+ 622f0d75cccbb624.8399d425c38a281a.ea898d4c1a6b4606.ba362e4bdbcad2f3
+ aa610da415f277b5.7fecc5f6de3b8d7f.b9f968bec9574ad2.81e8b144684ab921
+ 2acef0e719ef8a08
+VADDSS_128(mem)
+ before
+ 92b4672108c8fed3.aad0571e06b8dd8f.0d18f127eb5978f2.d1404d0593dd95d2
+ 966693dc54ded4af.bec7e54f3caa255e.07ebd3a405eea5a0.8faa3a8d138765b1
+ 10afee06173fc6c7.4194b5a352538ad0.4a2fe7594909d2b5.508229c1e5e3f41c
+ dd5cf68a6df69148.9181c386e540498e.b2b1a932d2b3b95c.6e15190fa77d7fbe
+ 46b003e3f2df4144
+ after
+ 92b4672108c8fed3.aad0571e06b8dd8f.0d18f127eb5978f2.d1404d0593dd95d2
+ 966693dc54ded4af.bec7e54f3caa255e.07ebd3a405eea5a0.8faa3a8d138765b1
+ 0000000000000000.0000000000000000.07ebd3a405eea5a0.8faa3a8d932c6042
+ dd5cf68a6df69148.9181c386e540498e.b2b1a932d2b3b95c.6e15190fa77d7fbe
+ 46b003e3f2df4144
+
+VADDSS_128(reg)
+ before
+ 359de4a76497785a.d93a26537310f15e.09db096490fc9e47.1b3c951bbcfa17c2
+ 9528b9c898315eab.e013fb4f4498a234.05ee85a9f013c5a5.629e280024e9a812
+ c39f7db22b372fe4.ceb4ef69fc9a5ff7.e00631c1a011f954.61a1ddce258d2779
+ 1b4d2cd2b93729b1.7fe8808db923e5d3.f86e0b193d837801.f513306fdcf15123
+ fabe9dd16521e23b
+ after
+ 0000000000000000.0000000000000000.05ee85a9f013c5a5.629e280025c7917e
+ 9528b9c898315eab.e013fb4f4498a234.05ee85a9f013c5a5.629e280024e9a812
+ c39f7db22b372fe4.ceb4ef69fc9a5ff7.e00631c1a011f954.61a1ddce258d2779
+ 1b4d2cd2b93729b1.7fe8808db923e5d3.f86e0b193d837801.f513306fdcf15123
+ fabe9dd16521e23b
+VADDSS_128(mem)
+ before
+ 4c6fa1dfdb2a95ee.f97dc392ddbd86bd.cf7d29a8943deff2.a8740f1b62f57b58
+ c7f2b7845a162867.b97c3c60335383b4.9a3d66a4abf73b83.4b623735acf14104
+ 47125baefff454d3.b79695a758875c43.bcf5b36e1a5a83b0.3f8581d2b60504b2
+ a89d0948e5cdd85e.4f17c9d3e7e54c16.11728df3fc7484a6.de29e85d1cbc010e
+ 869a68447ba374c3
+ after
+ 4c6fa1dfdb2a95ee.f97dc392ddbd86bd.cf7d29a8943deff2.a8740f1b62f57b58
+ c7f2b7845a162867.b97c3c60335383b4.9a3d66a4abf73b83.4b623735acf14104
+ 0000000000000000.0000000000000000.9a3d66a4abf73b83.4b62373562f57b58
+ a89d0948e5cdd85e.4f17c9d3e7e54c16.11728df3fc7484a6.de29e85d1cbc010e
+ 869a68447ba374c3
+
+VDIVSS_128(reg)
+ before
+ 9124fdf26f45987d.c55d3d3e29af6e33.dd4bd4507df890d9.757e6f1d6d51f990
+ 5d12a4d3932eaaea.7c1f747de6a6d47f.bd7eb38ab54c6437.c4e5d5da8afb9f9b
+ 44b2585383ebe6b4.a8af29ef39bcc36d.4bfb60ed2c6d03dc.da753b146f8032f3
+ a44e15dfdc078887.25d9d8813dfffa2a.e310d9e57de8ab75.93f81db937ec6ec3
+ ca3cf8b4fe490e38
+ after
+ 0000000000000000.0000000000000000.bd7eb38ab54c6437.c4e5d5da80000000
+ 5d12a4d3932eaaea.7c1f747de6a6d47f.bd7eb38ab54c6437.c4e5d5da8afb9f9b
+ 44b2585383ebe6b4.a8af29ef39bcc36d.4bfb60ed2c6d03dc.da753b146f8032f3
+ a44e15dfdc078887.25d9d8813dfffa2a.e310d9e57de8ab75.93f81db937ec6ec3
+ ca3cf8b4fe490e38
+VDIVSS_128(mem)
+ before
+ 5d0b47f1e1a5d07d.d733d7e1390ecb10.cf69fd200e7b33e2.e10719de444896ae
+ 2732865cfb0c6dbf.3aad9ac7378decfb.812b15b6c93a2bc0.a12d1d451e1a0032
+ 047d32e16988a42a.2a085bfb710f27f3.19ea9b318a4a9ef0.7fcedf84a7e827ae
+ cfb7c56d46272fe9.018f15eb8420b7a5.72730b7c6cb747a0.d7355d097a4145ce
+ 04b0923e33ae973d
+ after
+ 5d0b47f1e1a5d07d.d733d7e1390ecb10.cf69fd200e7b33e2.e10719de444896ae
+ 2732865cfb0c6dbf.3aad9ac7378decfb.812b15b6c93a2bc0.a12d1d451e1a0032
+ 0000000000000000.0000000000000000.812b15b6c93a2bc0.a12d1d4519448ae5
+ cfb7c56d46272fe9.018f15eb8420b7a5.72730b7c6cb747a0.d7355d097a4145ce
+ 04b0923e33ae973d
+
+VDIVSS_128(reg)
+ before
+ 64897a916fbd58a8.66aebdeaaff5cb28.1c90c4010b4ddabc.6792e1828b8ce3fa
+ 520d126dcaf9c5ba.a32c9546bffd3415.d85564aba321cae5.d613993104d52e2a
+ 2a88543edfef1a20.64ffc96b934b25da.8f2bf254e728c3cc.9ac2b074f39ee45d
+ 47463e704a2a9386.83f1d64746eb5ba3.9e5e696874ef021c.8e6ba13773f4c0bf
+ 90d9e867a0e27f7b
+ after
+ 0000000000000000.0000000000000000.d85564aba321cae5.d613993180000000
+ 520d126dcaf9c5ba.a32c9546bffd3415.d85564aba321cae5.d613993104d52e2a
+ 2a88543edfef1a20.64ffc96b934b25da.8f2bf254e728c3cc.9ac2b074f39ee45d
+ 47463e704a2a9386.83f1d64746eb5ba3.9e5e696874ef021c.8e6ba13773f4c0bf
+ 90d9e867a0e27f7b
+VDIVSS_128(mem)
+ before
+ 7ada01ee9774ddbe.0793cb6fa8366b97.decf36c5f4ea929d.613ac553e501c482
+ 293868b973b795b4.c4bbf8a7949fe0ff.4f6467d0ba5386f4.340b0281d6ea42a9
+ 7ac09ab551b66488.dc09bf85abf22b6c.b47ee456b432f2d3.731c1c5fe537bb3e
+ 473e12cc4c7e0666.a9ca1e7388bb8b88.e7e72a42fd949367.7abb1057ab7369ed
+ a532d9d7c62b8961
+ after
+ 7ada01ee9774ddbe.0793cb6fa8366b97.decf36c5f4ea929d.613ac553e501c482
+ 293868b973b795b4.c4bbf8a7949fe0ff.4f6467d0ba5386f4.340b0281d6ea42a9
+ 0000000000000000.0000000000000000.4f6467d0ba5386f4.340b0281316711c8
+ 473e12cc4c7e0666.a9ca1e7388bb8b88.e7e72a42fd949367.7abb1057ab7369ed
+ a532d9d7c62b8961
+
+VDIVSS_128(reg)
+ before
+ 50ce7349d1e95747.6e7d4cec811a377c.894a10dfc8843aff.c66db381b18425db
+ d7dbda1b693b0e4a.c94bc5000b96b2f4.d6d5913306db757e.2bdafdfded0f635d
+ 96a40bb82aadeb17.3572f7f407fe34fa.eeb79edddf4b78b1.f3fb83a3cd400b16
+ e977008bafca2a5a.8ec060b4905f79bb.2b3c3148ee617e43.fa9bc15f6c23d634
+ 1d88341ee6c483e3
+ after
+ 0000000000000000.0000000000000000.d6d5913306db757e.2bdafdfd5f3f241d
+ d7dbda1b693b0e4a.c94bc5000b96b2f4.d6d5913306db757e.2bdafdfded0f635d
+ 96a40bb82aadeb17.3572f7f407fe34fa.eeb79edddf4b78b1.f3fb83a3cd400b16
+ e977008bafca2a5a.8ec060b4905f79bb.2b3c3148ee617e43.fa9bc15f6c23d634
+ 1d88341ee6c483e3
+VDIVSS_128(mem)
+ before
+ 368d56cb5830cc4f.2c9eb702941e06be.b1ff7b2cc2c43c63.eaaf48e0cfa8c5e1
+ 2275a551dd726ea3.ba672c887635bdf0.78fcc448ba3a3b1d.885ede111fac8736
+ bd0d9c9e9297250b.f11c598af09c899b.c082b8f494cc2f16.5f93ef477afa00ef
+ e321b79d92aaadb5.2c0a3c729fdea66c.655fd11c6b86d779.cc9b78ee7b1d6db8
+ 2cc27472bea10a3c
+ after
+ 368d56cb5830cc4f.2c9eb702941e06be.b1ff7b2cc2c43c63.eaaf48e0cfa8c5e1
+ 2275a551dd726ea3.ba672c887635bdf0.78fcc448ba3a3b1d.885ede111fac8736
+ 0000000000000000.0000000000000000.78fcc448ba3a3b1d.885ede118f82d917
+ e321b79d92aaadb5.2c0a3c729fdea66c.655fd11c6b86d779.cc9b78ee7b1d6db8
+ 2cc27472bea10a3c
+
+VUNPCKLPS_128(reg)
+ before
+ d953df40e0131328.707d733afab7c1ca.c77ccfad1e88520f.435d8dad5b74ed73
+ 309cb5c27dfec428.40ed4b61e5cb1e79.1dc011a80925c72f.364a679181a32f30
+ 8de7f26630ef58e7.2f3cbbfe6ff17fec.8c21fbcdfe414278.1af0dcb6f81f56db
+ 4c82939695700c11.19383ffdb635a24f.6fea8a8a9669fe98.cb1c6607ddf221a1
+ 259a83704c2a4aad
+ after
+ 0000000000000000.0000000000000000.1af0dcb6364a6791.f81f56db81a32f30
+ 309cb5c27dfec428.40ed4b61e5cb1e79.1dc011a80925c72f.364a679181a32f30
+ 8de7f26630ef58e7.2f3cbbfe6ff17fec.8c21fbcdfe414278.1af0dcb6f81f56db
+ 4c82939695700c11.19383ffdb635a24f.6fea8a8a9669fe98.cb1c6607ddf221a1
+ 259a83704c2a4aad
+VUNPCKLPS_128(mem)
+ before
+ 0435aedc5fd28e2c.c9b793c0490f1b53.daab534bd3a341cf.2168bb496f273839
+ 44bb633935f7a94a.60d3ee4fe758c359.4e6274d2e4481998.00e78978250a2c07
+ c1f61f72e7a45632.6d21a0af0cd63ecf.51291d800530e5d6.66b3f082539b16af
+ 57b35c7494e55211.4cefa54c5315c960.bfccca3f516562b4.b118ecd3956832dd
+ 3b617ad788fcbb3c
+ after
+ 0435aedc5fd28e2c.c9b793c0490f1b53.daab534bd3a341cf.2168bb496f273839
+ 44bb633935f7a94a.60d3ee4fe758c359.4e6274d2e4481998.00e78978250a2c07
+ 0000000000000000.0000000000000000.2168bb4900e78978.6f273839250a2c07
+ 57b35c7494e55211.4cefa54c5315c960.bfccca3f516562b4.b118ecd3956832dd
+ 3b617ad788fcbb3c
+
+VUNPCKLPS_128(reg)
+ before
+ 62dc95fac8e4ee79.e2be982955c75912.5987fa9259a19fb8.7416f7fde4f54c5e
+ 80d339a9efab063f.3de34e7e48552662.f0379aedb907fd84.4cd520a5dbec5f01
+ f293624e9cdd403c.46eefb60899b772c.6d4981ca0fd21f70.22d3c223515456c9
+ 15680d566907d819.d8ab19b933a6069d.2c0aab93f88f4127.d4dd5863633befe1
+ 3dbf5e512cade376
+ after
+ 0000000000000000.0000000000000000.22d3c2234cd520a5.515456c9dbec5f01
+ 80d339a9efab063f.3de34e7e48552662.f0379aedb907fd84.4cd520a5dbec5f01
+ f293624e9cdd403c.46eefb60899b772c.6d4981ca0fd21f70.22d3c223515456c9
+ 15680d566907d819.d8ab19b933a6069d.2c0aab93f88f4127.d4dd5863633befe1
+ 3dbf5e512cade376
+VUNPCKLPS_128(mem)
+ before
+ 394550d9c9b4f1b4.439e342ef2b40a84.cfe5267763818fe1.89c615b510c89e56
+ a33babe7555fd3c6.d980d541d4701229.06699d853438d024.dfc8ba9df20c73a9
+ 596cea68edb746d9.345cebfaaac82bb4.5b03facfc2d88390.8c5e96b63ae4fccb
+ 35a68946acca0618.ae7c73c7104792d0.a97fba402a6c6554.ebd2a56c85de7569
+ 5872e32a6f85192e
+ after
+ 394550d9c9b4f1b4.439e342ef2b40a84.cfe5267763818fe1.89c615b510c89e56
+ a33babe7555fd3c6.d980d541d4701229.06699d853438d024.dfc8ba9df20c73a9
+ 0000000000000000.0000000000000000.89c615b5dfc8ba9d.10c89e56f20c73a9
+ 35a68946acca0618.ae7c73c7104792d0.a97fba402a6c6554.ebd2a56c85de7569
+ 5872e32a6f85192e
+
+VUNPCKLPS_128(reg)
+ before
+ 2e884d5e936625c7.15b3046fafa3ceb0.a42d6713a4798229.cba957c68701319a
+ cb61de738d0cd5e0.d360d8cd114e5bcc.72bbc54affeb396d.9f4d4f4df6a1a58f
+ 8a4892d6fa036424.4d797f4eefd86999.747288d8bf28f145.ff361dbf935b7b5e
+ c68b65f175d70f3f.5dca77dd644cb443.069dac2980bde760.c9323d0978386f34
+ d70b2c17c4463f3c
+ after
+ 0000000000000000.0000000000000000.ff361dbf9f4d4f4d.935b7b5ef6a1a58f
+ cb61de738d0cd5e0.d360d8cd114e5bcc.72bbc54affeb396d.9f4d4f4df6a1a58f
+ 8a4892d6fa036424.4d797f4eefd86999.747288d8bf28f145.ff361dbf935b7b5e
+ c68b65f175d70f3f.5dca77dd644cb443.069dac2980bde760.c9323d0978386f34
+ d70b2c17c4463f3c
+VUNPCKLPS_128(mem)
+ before
+ 068e65d69090a5a3.dd7454319b1512df.e11e3b668cb7f7f5.848a2daadd345668
+ 33876331fb225e95.29515a030749a9ae.b34347d58423efdc.4a8308c5721b7b09
+ 38c1a5131e09253d.086c73d156fd0f58.b1031816689e5824.b4d638e7dcfe92f1
+ f20aa46a1850b8c8.d4129b0923bf818a.b52b29155334edf8.1ecdb97db768d7c9
+ e4b487f29ee58540
+ after
+ 068e65d69090a5a3.dd7454319b1512df.e11e3b668cb7f7f5.848a2daadd345668
+ 33876331fb225e95.29515a030749a9ae.b34347d58423efdc.4a8308c5721b7b09
+ 0000000000000000.0000000000000000.848a2daa4a8308c5.dd345668721b7b09
+ f20aa46a1850b8c8.d4129b0923bf818a.b52b29155334edf8.1ecdb97db768d7c9
+ e4b487f29ee58540
+
+VCVTSI2SS_128(reg)
+ before
+ 62d99fb12d01d900.3e2cde210204d162.eb8ece150b1a3bf0.9c87f6bf61f06c84
+ f487fc2801490fb5.f6f5cd24fa302c36.a72e0963a99b7835.42e3fbfeafde8ef6
+ f6099ac2b548630c.f72fef5f1ce08770.653d475e99cd7506.840bb4c0580a1277
+ c4ac75ebe68b10b1.1da7c0be83209c3e.82068472783c6e0e.3cca9eef7981b236
+ 47ee34792d4f2b5d
+ after
+ 0000000000000000.0000000000000000.a72e0963a99b7835.42e3fbfe4e353cad
+ f487fc2801490fb5.f6f5cd24fa302c36.a72e0963a99b7835.42e3fbfeafde8ef6
+ f6099ac2b548630c.f72fef5f1ce08770.653d475e99cd7506.840bb4c0580a1277
+ c4ac75ebe68b10b1.1da7c0be83209c3e.82068472783c6e0e.3cca9eef7981b236
+ 47ee34792d4f2b5d
+VCVTSI2SS_128(mem)
+ before
+ 8141f249917e3919.babc890f2f9d5350.4528ba2d4bfd28c9.58d6bc0be2759ffa
+ c690544ac01c9895.3385d39b2d0a6793.49805b999182e740.44f9ec9572034376
+ f2a7d76ad73403fe.8d534ef97b5e8a29.06791eec71bc94cd.a2bb0e7dc472972d
+ e151f595f1d3377f.2372f696b626f6bc.58e17f1306b6ec9c.cf68202d754fd7cc
+ 254b1d1321253eff
+ after
+ 8141f249917e3919.babc890f2f9d5350.4528ba2d4bfd28c9.58d6bc0be2759ffa
+ c690544ac01c9895.3385d39b2d0a6793.49805b999182e740.44f9ec9572034376
+ 0000000000000000.0000000000000000.49805b999182e740.44f9ec95cdec5300
+ e151f595f1d3377f.2372f696b626f6bc.58e17f1306b6ec9c.cf68202d754fd7cc
+ 254b1d1321253eff
+
+VCVTSI2SS_128(reg)
+ before
+ 01b2029962800a71.705c2cb52b04ef45.502dc7df79ede8f9.1b82fafb6c7cabdb
+ bfe7c92dd7ed75ce.7892f8b7a0d3e97b.72d2bd3f61409b8b.2b290c8fc01b8cb3
+ bb3770391af7bbc3.d8c1d3876c4ddf4f.e4abd52109aa4d1f.64a230bb1d9e4d53
+ 51eef22bc72b1afc.6bb33b12ac7d8eea.01050af30db73861.a2b8e26ba011a7e5
+ c1399e8a64815995
+ after
+ 0000000000000000.0000000000000000.72d2bd3f61409b8b.2b290c8f4ec902b3
+ bfe7c92dd7ed75ce.7892f8b7a0d3e97b.72d2bd3f61409b8b.2b290c8fc01b8cb3
+ bb3770391af7bbc3.d8c1d3876c4ddf4f.e4abd52109aa4d1f.64a230bb1d9e4d53
+ 51eef22bc72b1afc.6bb33b12ac7d8eea.01050af30db73861.a2b8e26ba011a7e5
+ c1399e8a64815995
+VCVTSI2SS_128(mem)
+ before
+ 9defe00786f91d90.dd584b6e7b13cc25.0d35aa427c6fb17b.272c58200af498fc
+ 11a725cb2185b102.bbc0786ed13e0de9.9a129e05f730052c.b06bbc149cecab9c
+ fb2de8c35232ce17.4774749765351bf4.ee18934639cb4629.fa10303b5e2babef
+ 364da5db340b33fa.ddbe3b56d58630f3.e51103f05f4c309f.5f65b201ec3ed59e
+ 3cb83dd2e3af6458
+ after
+ 9defe00786f91d90.dd584b6e7b13cc25.0d35aa427c6fb17b.272c58200af498fc
+ 11a725cb2185b102.bbc0786ed13e0de9.9a129e05f730052c.b06bbc149cecab9c
+ 0000000000000000.0000000000000000.9a129e05f730052c.b06bbc144d2f4990
+ 364da5db340b33fa.ddbe3b56d58630f3.e51103f05f4c309f.5f65b201ec3ed59e
+ 3cb83dd2e3af6458
+
+VCVTSI2SS_128(reg)
+ before
+ ee53cd1bde0d96c7.9ed3d800e41c9ad7.d9ebc915babc8992.5bcb6cf184c07eba
+ cf835f467ae1a598.0e8bfe1c7d72c0db.97471a41b263627c.2b104934c532eea6
+ 3c93edc152b9cd76.6440911d1b186132.731e2b475908f65e.33ad16a53eae398d
+ 92d175f603214c0e.7bbf0feedb1a3807.c8bcf6914a3682e4.4e6e4f3109411e9e
+ 571e71c245f65703
+ after
+ 0000000000000000.0000000000000000.97471a41b263627c.2b1049344e8becae
+ cf835f467ae1a598.0e8bfe1c7d72c0db.97471a41b263627c.2b104934c532eea6
+ 3c93edc152b9cd76.6440911d1b186132.731e2b475908f65e.33ad16a53eae398d
+ 92d175f603214c0e.7bbf0feedb1a3807.c8bcf6914a3682e4.4e6e4f3109411e9e
+ 571e71c245f65703
+VCVTSI2SS_128(mem)
+ before
+ 2c8bf7450bd9a1e9.2b87f25328a35c0b.2ed4f47bd9850287.f46c798d217a42b9
+ a77f5da779f7b87b.640361435ecd3a1a.5b4bbab030647bde.527cb0a67b5f728a
+ a6c81fd2ab5b57e6.998fbc32402b22e7.ddf0df79fcc35f37.3d369548f4714d02
+ 0430b9b4bc113b56.2678018c6b484f1d.8f8fddc25aaf69be.13e726df273d10ce
+ 2fdb5ed7b04df79a
+ after
+ 2c8bf7450bd9a1e9.2b87f25328a35c0b.2ed4f47bd9850287.f46c798d217a42b9
+ a77f5da779f7b87b.640361435ecd3a1a.5b4bbab030647bde.527cb0a67b5f728a
+ 0000000000000000.0000000000000000.5b4bbab030647bde.527cb0a64e05e90b
+ 0430b9b4bc113b56.2678018c6b484f1d.8f8fddc25aaf69be.13e726df273d10ce
+ 2fdb5ed7b04df79a
+
+VANDPS_128(reg)
+ before
+ ec5e399c2c303d11.9c84a838c92620f6.680a2bbd7ab0fe69.4ff33277653356a1
+ a8bbb39a366f1fdf.4b8f674aeda5c2f2.b990363109ef6b76.f7ea5a843a5ce20a
+ be40c83d6b98d9b2.ee1f72d6449bdc78.76581f54b592d1f1.653ecfd6f434c825
+ 893775f26636a634.5ffe45c8eb122bb1.fbace0931a246d86.73bc0f57b0cac51f
+ fe3095f589279524
+ after
+ 0000000000000000.0000000000000000.3010161001824170.652a4a843014c000
+ a8bbb39a366f1fdf.4b8f674aeda5c2f2.b990363109ef6b76.f7ea5a843a5ce20a
+ be40c83d6b98d9b2.ee1f72d6449bdc78.76581f54b592d1f1.653ecfd6f434c825
+ 893775f26636a634.5ffe45c8eb122bb1.fbace0931a246d86.73bc0f57b0cac51f
+ fe3095f589279524
+VANDPS_128(mem)
+ before
+ e365dd9a9c59f45f.66edb523c4d6c411.7cfa5d0cfe196bcc.a4d97758d3317be0
+ fc296334046b9dfd.b2ae843e20036df6.1fdd358e98b957f3.cd2bdf117c4637ac
+ 2646a4aede694d29.c7c6dfae1749dd8f.2574493ad500ad53.d2ee1429b2eedc95
+ 3e8a1bf44560c010.0380c0df44355287.6b8b15fdd2f92617.0f6e130b11b6a848
+ dff6d7253328d471
+ after
+ e365dd9a9c59f45f.66edb523c4d6c411.7cfa5d0cfe196bcc.a4d97758d3317be0
+ fc296334046b9dfd.b2ae843e20036df6.1fdd358e98b957f3.cd2bdf117c4637ac
+ 0000000000000000.0000000000000000.1cd8150c981943c0.84095710500033a0
+ 3e8a1bf44560c010.0380c0df44355287.6b8b15fdd2f92617.0f6e130b11b6a848
+ dff6d7253328d471
+
+VANDPS_128(reg)
+ before
+ a0d45ce2b7d39fbb.1ebf44f2565cb1de.c02a253c4352068b.cbed15c1aab1816c
+ ad529eae364043d3.a3b29b942c67debe.5b0e0933b12c3646.2268c6747a32787d
+ 62bd99f54ffdfd64.a92e9dc6e38f00dd.317969302a501e65.4cc6a3005d8bc877
+ 1b614a249b95091b.0c01c47598dfd667.9cb73f9d4949f994.25d4285370c52d86
+ 895ed158ceee63d5
+ after
+ 0000000000000000.0000000000000000.1108093020001644.0040820058024875
+ ad529eae364043d3.a3b29b942c67debe.5b0e0933b12c3646.2268c6747a32787d
+ 62bd99f54ffdfd64.a92e9dc6e38f00dd.317969302a501e65.4cc6a3005d8bc877
+ 1b614a249b95091b.0c01c47598dfd667.9cb73f9d4949f994.25d4285370c52d86
+ 895ed158ceee63d5
+VANDPS_128(mem)
+ before
+ 54301bfb94112591.338aaca5b995a2a3.a8f58e8b67641a87.f91489e7aaa3047e
+ 63168028dd3b30e5.0884bbe5428805aa.59d876f66a298a69.a4dc427aeaeb7bd0
+ 90db7ecbc6773ffe.f59a7351d4fa6ed9.fb74f9a0c03adf3a.fa5b66c3a5ac9935
+ b84d90d16ad11008.5519d0530b7719df.6a96917783a3d826.55dcf12c75729b5a
+ 12ace023f9cabdeb
+ after
+ 54301bfb94112591.338aaca5b995a2a3.a8f58e8b67641a87.f91489e7aaa3047e
+ 63168028dd3b30e5.0884bbe5428805aa.59d876f66a298a69.a4dc427aeaeb7bd0
+ 0000000000000000.0000000000000000.08d0068262200a01.a0140062aaa30050
+ b84d90d16ad11008.5519d0530b7719df.6a96917783a3d826.55dcf12c75729b5a
+ 12ace023f9cabdeb
+
+VANDPS_128(reg)
+ before
+ 8d172e13cb3f3b93.b7363324e5565d2e.864ecf59828c4166.820abc66cf712f58
+ 2269d768875e50ff.6863e1b15411e39d.e2836bced6c4231a.1f9bf559c1b0a1fd
+ 2deed78ecab139da.a9a01865d30e5d80.c704a01ea2acfba8.1d17b83c746aea41
+ 0af22bf12fc632d1.55b9532a7d5a8804.8f1f6bb582cf04bc.584882fb05adc54f
+ acfbcd828f85ef54
+ after
+ 0000000000000000.0000000000000000.c200200e82842308.1d13b0184020a041
+ 2269d768875e50ff.6863e1b15411e39d.e2836bced6c4231a.1f9bf559c1b0a1fd
+ 2deed78ecab139da.a9a01865d30e5d80.c704a01ea2acfba8.1d17b83c746aea41
+ 0af22bf12fc632d1.55b9532a7d5a8804.8f1f6bb582cf04bc.584882fb05adc54f
+ acfbcd828f85ef54
+VANDPS_128(mem)
+ before
+ f5fd17bd2ffc247b.15c0cdfd52297790.487a0fee6e002055.981fc6ff13b97b01
+ 0f17db9800201ff1.aaa5bb1ed16543c2.5eaec69cc30ce19e.3c4faf68f0f79c24
+ d51895001efd9ee2.25edf0c04506d314.7322f620988b860b.d9fc215cb614a3d0
+ 25cbc2dfa69d5b79.e1e469504c986231.62a21a660788cdca.c9721848019ccbb2
+ 69fd91966b1c5176
+ after
+ f5fd17bd2ffc247b.15c0cdfd52297790.487a0fee6e002055.981fc6ff13b97b01
+ 0f17db9800201ff1.aaa5bb1ed16543c2.5eaec69cc30ce19e.3c4faf68f0f79c24
+ 0000000000000000.0000000000000000.482a068c42002014.180f866810b11800
+ 25cbc2dfa69d5b79.e1e469504c986231.62a21a660788cdca.c9721848019ccbb2
+ 69fd91966b1c5176
+
+VMINSS_128(reg)
+ before
+ 16e986b4931f71c7.dafbdd23b40e12e3.3cd6203882a82ec6.09faae5a2f0f6f05
+ 2a82f50c12316652.cf7562b7635c814b.910f13e682c1717f.43f62ee82a2d2be8
+ 0213d90c87df6dc3.e206cd87cf9162de.3cdb3dc4e8706807.eb6217fc14edbba0
+ fae92f1f8bb4c2c5.ee779a7f15bc72c7.99859a4051404e0b.df0ae483095bdc59
+ fab9116727844a3e
+ after
+ 0000000000000000.0000000000000000.910f13e682c1717f.43f62ee814edbba0
+ 2a82f50c12316652.cf7562b7635c814b.910f13e682c1717f.43f62ee82a2d2be8
+ 0213d90c87df6dc3.e206cd87cf9162de.3cdb3dc4e8706807.eb6217fc14edbba0
+ fae92f1f8bb4c2c5.ee779a7f15bc72c7.99859a4051404e0b.df0ae483095bdc59
+ fab9116727844a3e
+VMINSS_128(mem)
+ before
+ 173c1a968773c07c.6f51f1b1bd3ca104.ce97468b51e66c33.035a27c559bd6136
+ 145f7bfb4734fb3f.bb951d2eb604452e.60314c979e1d0e4e.d8a6debf9b73db35
+ cbeeb18183d4b7b2.3b01ae021497ebec.7e10288f186c1243.73b5bd9ab3eff8b3
+ 1ab53716565eb001.4be3a0997381cfed.0602565fdcdf343f.2fd3bfc23ebdf65e
+ 6a4be1a3d7670fdf
+ after
+ 173c1a968773c07c.6f51f1b1bd3ca104.ce97468b51e66c33.035a27c559bd6136
+ 145f7bfb4734fb3f.bb951d2eb604452e.60314c979e1d0e4e.d8a6debf9b73db35
+ 0000000000000000.0000000000000000.60314c979e1d0e4e.d8a6debf9b73db35
+ 1ab53716565eb001.4be3a0997381cfed.0602565fdcdf343f.2fd3bfc23ebdf65e
+ 6a4be1a3d7670fdf
+
+VMINSS_128(reg)
+ before
+ 7e6b1daa1b7b80e5.db7f89a5dddfa15a.4786f05f6e4f2ddb.d2d153f40583326e
+ c97d7141a5848419.eb1a231a336247e7.8b3598c1a18c4062.c04a9938b063c6fb
+ a5ced8d6120f592a.2750826174f35ed4.733d9629a9c54530.aa39a619f88cad13
+ 70aa4ed3fda739c2.69ee2166bd9ea14e.5beae505228477ee.6d69f581fa08a2e1
+ e6a8035ed1e66392
+ after
+ 0000000000000000.0000000000000000.8b3598c1a18c4062.c04a9938f88cad13
+ c97d7141a5848419.eb1a231a336247e7.8b3598c1a18c4062.c04a9938b063c6fb
+ a5ced8d6120f592a.2750826174f35ed4.733d9629a9c54530.aa39a619f88cad13
+ 70aa4ed3fda739c2.69ee2166bd9ea14e.5beae505228477ee.6d69f581fa08a2e1
+ e6a8035ed1e66392
+VMINSS_128(mem)
+ before
+ efc04a9b9a2faa51.845dcfa602d8608e.8ec07c162970ce81.9f8882bfa758144b
+ 657f482470f1334b.3f3358babf2f0c39.73920f5bd5749e98.9b6367c5d4ca56f1
+ 24af78e56f37bcac.fb77e47bcd377770.f2305623ddb7d0c0.abc6928246687a8c
+ 091d56cab40eff9f.15766f55ca7cdede.e865ce585b441e24.2bfffe6298bdbbc9
+ 7658a7d167565654
+ after
+ efc04a9b9a2faa51.845dcfa602d8608e.8ec07c162970ce81.9f8882bfa758144b
+ 657f482470f1334b.3f3358babf2f0c39.73920f5bd5749e98.9b6367c5d4ca56f1
+ 0000000000000000.0000000000000000.73920f5bd5749e98.9b6367c5d4ca56f1
+ 091d56cab40eff9f.15766f55ca7cdede.e865ce585b441e24.2bfffe6298bdbbc9
+ 7658a7d167565654
+
+VMINSS_128(reg)
+ before
+ ea1e893b4ebd87d8.ee945fbf5b81b951.ea7df5b4528b7c30.31fff2e86e2745f1
+ e29da10cea818a02.b0e20eb17f9ca6ed.d4d6730400ef8f12.a9c83ebe2f6c0153
+ ba21eab1d62b9a7e.2bd1de8a3c6b81a0.30cee3b17034512f.2c8d2ec6bd200e75
+ cdf56094af49f4f7.3b2f4e38affb0796.5ab043283fe7fe34.971a3eec314f2784
+ c43aeb1ca90309ab
+ after
+ 0000000000000000.0000000000000000.d4d6730400ef8f12.a9c83ebebd200e75
+ e29da10cea818a02.b0e20eb17f9ca6ed.d4d6730400ef8f12.a9c83ebe2f6c0153
+ ba21eab1d62b9a7e.2bd1de8a3c6b81a0.30cee3b17034512f.2c8d2ec6bd200e75
+ cdf56094af49f4f7.3b2f4e38affb0796.5ab043283fe7fe34.971a3eec314f2784
+ c43aeb1ca90309ab
+VMINSS_128(mem)
+ before
+ 90bbb042414a6f17.7967ff231066d41a.bcc6d7a5f358f4fa.aeca8fd30893d4cc
+ d767094a142f17f4.19c1c4c8950f7692.8a63f6bf258c03f9.8866c12068c40da4
+ 750c73203fbfbb6d.0850a9f1dbcf150c.81d2287161a5f1be.45d1d779fb07e668
+ 457468b1dd0518af.a460ac097e32ee33.7ddee8a7c1ae7a76.3f58cb4c5be79bc3
+ d3449b0427f16762
+ after
+ 90bbb042414a6f17.7967ff231066d41a.bcc6d7a5f358f4fa.aeca8fd30893d4cc
+ d767094a142f17f4.19c1c4c8950f7692.8a63f6bf258c03f9.8866c12068c40da4
+ 0000000000000000.0000000000000000.8a63f6bf258c03f9.8866c1200893d4cc
+ 457468b1dd0518af.a460ac097e32ee33.7ddee8a7c1ae7a76.3f58cb4c5be79bc3
+ d3449b0427f16762
+
+VMAXSS_128(reg)
+ before
+ 5de4430df8af87f0.256c66e70a0de9e5.473dc87c19c43db5.5a55b24d64b45a4d
+ 3983bdd36daf371a.f0bfe8b0e3e4eb3c.4f33fab648123d3b.f401034f63c24c6e
+ c36c07c21f7db28c.823b6af78495dae0.168d3c23a8a82b74.27af5699dde40e06
+ 57ed1c46aca436f1.b7aa69a8072c72fc.fa998c2fd5104309.ce2c2617eb275940
+ c741f2b6ab96ec49
+ after
+ 0000000000000000.0000000000000000.4f33fab648123d3b.f401034f63c24c6e
+ 3983bdd36daf371a.f0bfe8b0e3e4eb3c.4f33fab648123d3b.f401034f63c24c6e
+ c36c07c21f7db28c.823b6af78495dae0.168d3c23a8a82b74.27af5699dde40e06
+ 57ed1c46aca436f1.b7aa69a8072c72fc.fa998c2fd5104309.ce2c2617eb275940
+ c741f2b6ab96ec49
+VMAXSS_128(mem)
+ before
+ edbd3360393d814c.5050f8ccb0b0fdf6.6bda60af8bb66ebd.55a1e5466ad8c1a9
+ 1c6b6603b029d577.0ce297bec62d4346.7995cbf82a3e8c4e.84f243d4038ce0fe
+ 2f1608892d65a4f3.e6eff6898ba8468e.bfa8266f00d085dc.e4d8a3463db6ddb5
+ 048b94e0cbfda9ef.3ac2109a9aac407a.18dfed002a791892.cf9f0006b3e4f479
+ a292558202a260f7
+ after
+ edbd3360393d814c.5050f8ccb0b0fdf6.6bda60af8bb66ebd.55a1e5466ad8c1a9
+ 1c6b6603b029d577.0ce297bec62d4346.7995cbf82a3e8c4e.84f243d4038ce0fe
+ 0000000000000000.0000000000000000.7995cbf82a3e8c4e.84f243d46ad8c1a9
+ 048b94e0cbfda9ef.3ac2109a9aac407a.18dfed002a791892.cf9f0006b3e4f479
+ a292558202a260f7
+
+VMAXSS_128(reg)
+ before
+ baffa125c57a5fda.769786f3a6fea195.64a9e15c8fc66eb5.5f059d97c344ff9e
+ 7130dd5b99fa2acf.60035baedb734811.bfee653b07810bec.72e8b020e83df729
+ 2472069019ae0082.a09e8dfd85695a90.a9de98a29e6954ca.2c52a488b471bc62
+ 2f111930e2201b9e.10339accc1ea923e.7dc577ffee0a85fc.6811f5b943eb0972
+ 04ef1da1b3b89b88
+ after
+ 0000000000000000.0000000000000000.bfee653b07810bec.72e8b020b471bc62
+ 7130dd5b99fa2acf.60035baedb734811.bfee653b07810bec.72e8b020e83df729
+ 2472069019ae0082.a09e8dfd85695a90.a9de98a29e6954ca.2c52a488b471bc62
+ 2f111930e2201b9e.10339accc1ea923e.7dc577ffee0a85fc.6811f5b943eb0972
+ 04ef1da1b3b89b88
+VMAXSS_128(mem)
+ before
+ dab99a2b1de22ece.ee5911a78fdeb8d0.8e8dfd07ab04ad46.96effdbd96f1da2d
+ c83ae7439f777e71.bd96ea61bc7413c3.f47a329a5dc367d5.52a8264930a98e0b
+ a84080d55583469c.f813a1ca066d6824.20c4b672f6327b17.0c3cee0d58bfdf3f
+ 5795e1cd5a11437c.fb1e304e0955f29f.ec380479905da637.1ff65276abbe0678
+ e9234cf1c432425f
+ after
+ dab99a2b1de22ece.ee5911a78fdeb8d0.8e8dfd07ab04ad46.96effdbd96f1da2d
+ c83ae7439f777e71.bd96ea61bc7413c3.f47a329a5dc367d5.52a8264930a98e0b
+ 0000000000000000.0000000000000000.f47a329a5dc367d5.52a8264930a98e0b
+ 5795e1cd5a11437c.fb1e304e0955f29f.ec380479905da637.1ff65276abbe0678
+ e9234cf1c432425f
+
+VMAXSS_128(reg)
+ before
+ c40fdae840a8cda3.b2078717ca2d313c.2201955a60b8eedf.35a2989d4750a461
+ 0e06f8c9baabe4ee.9360ec9fc2e3cb09.c909cb59a7239891.d8cdeec8371831c3
+ 2154a0fecec7c3ed.d76d8e515d40cf0f.4c82cfb67b212b60.af8782e87ec00886
+ 5a45d0f51a89a54b.5bfae91ab84ff679.07b79bdf773ee4f9.979ad1e83555e6d9
+ 6dd456b47ae287e6
+ after
+ 0000000000000000.0000000000000000.c909cb59a7239891.d8cdeec87ec00886
+ 0e06f8c9baabe4ee.9360ec9fc2e3cb09.c909cb59a7239891.d8cdeec8371831c3
+ 2154a0fecec7c3ed.d76d8e515d40cf0f.4c82cfb67b212b60.af8782e87ec00886
+ 5a45d0f51a89a54b.5bfae91ab84ff679.07b79bdf773ee4f9.979ad1e83555e6d9
+ 6dd456b47ae287e6
+VMAXSS_128(mem)
+ before
+ 0bff8d386973a6d9.16248319377cc8b5.f9d277e4ef1dff74.56f62d3f3807ff08
+ 4ee8f2601d1401e0.af3fb5d6c32c65d6.8ec3b69d1db5a42c.958980425a07b738
+ 125a0118b2d25125.82e062985a26bb5b.f69720305e23a2cc.20be905477cb4a36
+ 3323374d45b855d4.ec5486cb97f504f0.0d1b3488cf74b580.52df59e12edef2ad
+ 8939d85518cceb4a
+ after
+ 0bff8d386973a6d9.16248319377cc8b5.f9d277e4ef1dff74.56f62d3f3807ff08
+ 4ee8f2601d1401e0.af3fb5d6c32c65d6.8ec3b69d1db5a42c.958980425a07b738
+ 0000000000000000.0000000000000000.8ec3b69d1db5a42c.958980425a07b738
+ 3323374d45b855d4.ec5486cb97f504f0.0d1b3488cf74b580.52df59e12edef2ad
+ 8939d85518cceb4a
+
+VANDNPS_128(reg)
+ before
+ 2018081dd32173b8.8d0d0fe9f2d3c71a.47e71edc16257d40.b01b6b938bb29975
+ 73c7e5a3fb6ac4a4.fde605dad42e6423.f0e52535744362f8.b963423caeec09d7
+ dd946b542b331bba.5d78950a07d5e81a.439997444cdaefc3.05bf366f562bc2d2
+ bcc9979d0006b3a6.8a903c67a8d50f2c.9c5071733b765f4e.70fac2189c7d7f91
+ d6e262249eedfe40
+ after
+ 0000000000000000.0000000000000000.0318924008988d03.049c34435003c200
+ 73c7e5a3fb6ac4a4.fde605dad42e6423.f0e52535744362f8.b963423caeec09d7
+ dd946b542b331bba.5d78950a07d5e81a.439997444cdaefc3.05bf366f562bc2d2
+ bcc9979d0006b3a6.8a903c67a8d50f2c.9c5071733b765f4e.70fac2189c7d7f91
+ d6e262249eedfe40
+VANDNPS_128(mem)
+ before
+ 1341937d7888f90c.6ab363e91571c912.60fa75dcd2399484.5757ad30dda4ef45
+ 03e4cf1045592d21.459ecda406ff99ad.ba81bc55a20d344f.d0f849e5ccefda53
+ 819794ca216c55aa.a8d6d139703d5f21.76f38dbe335eabb8.64804000a7e35e25
+ 6b265d9629ce2ed4.eea76916efb6571b.6f1a6403a237b4ed.6d3b8eec070db566
+ 487430158bf81cc3
+ after
+ 1341937d7888f90c.6ab363e91571c912.60fa75dcd2399484.5757ad30dda4ef45
+ 03e4cf1045592d21.459ecda406ff99ad.ba81bc55a20d344f.d0f849e5ccefda53
+ 0000000000000000.0000000000000000.407a418850308080.0707a41011002504
+ 6b265d9629ce2ed4.eea76916efb6571b.6f1a6403a237b4ed.6d3b8eec070db566
+ 487430158bf81cc3
+
+VANDNPS_128(reg)
+ before
+ 507920e7cc31cee8.9c5da65f798a74cb.745c92a61ef6bc46.81c4be100aa40c17
+ e3945ccf68430880.f007ec132cace3ba.97434956998acb4f.88bb16d188b26f65
+ 5c12df37fbba0638.43f1aa9d5e4136ce.b1a68990fdfdbfe1.60cbe833376c9801
+ 173fa68c202204bb.70e75be92c542b32.20d24fc1e5dbd5a9.e4c2b02034de4517
+ f26beb869a1530d4
+ after
+ 0000000000000000.0000000000000000.20a48080647534a0.6040e822374c9000
+ e3945ccf68430880.f007ec132cace3ba.97434956998acb4f.88bb16d188b26f65
+ 5c12df37fbba0638.43f1aa9d5e4136ce.b1a68990fdfdbfe1.60cbe833376c9801
+ 173fa68c202204bb.70e75be92c542b32.20d24fc1e5dbd5a9.e4c2b02034de4517
+ f26beb869a1530d4
+VANDNPS_128(mem)
+ before
+ 6591134f851c1564.7067ab3b74083db6.55b57ee3b1f17b13.3e139556eeb14953
+ 1801a66912ffb2f2.c3d6ecae92f7eed5.cd278c770a25e59d.68b559b9b40a578a
+ e98820bf5dcbc1ab.6bd76453167c53c3.b309029252fb23fb.fb039658d1723bfb
+ b3f0fb3d818bffbb.c6b70f959d22a82d.e5275d1ea680f259.514b489ee4763052
+ c7d76bf686a1733a
+ after
+ 6591134f851c1564.7067ab3b74083db6.55b57ee3b1f17b13.3e139556eeb14953
+ 1801a66912ffb2f2.c3d6ecae92f7eed5.cd278c770a25e59d.68b559b9b40a578a
+ 0000000000000000.0000000000000000.10907280b1d01a02.160284464ab10851
+ b3f0fb3d818bffbb.c6b70f959d22a82d.e5275d1ea680f259.514b489ee4763052
+ c7d76bf686a1733a
+
+VANDNPS_128(reg)
+ before
+ b9f4fcce557f3f5f.5105b5cf9a4b274d.2fc3eae0c27528be.3e4c180921be0ee5
+ 83eef591ed9dd26e.a195c861c518f78e.0245f0a022011023.9945b03de0c332c9
+ 821154abe9866613.7d6ab3df1dfd29a9.9a8a1c4159539c07.d4de9fa8fe9b1b31
+ 10a91489e6c637fa.c352ef35bf0779cb.55dd6c2f02f60718.c9e363349751854a
+ 562077cfc8f12c40
+ after
+ 0000000000000000.0000000000000000.988a0c4159528c04.449a0f801e180930
+ 83eef591ed9dd26e.a195c861c518f78e.0245f0a022011023.9945b03de0c332c9
+ 821154abe9866613.7d6ab3df1dfd29a9.9a8a1c4159539c07.d4de9fa8fe9b1b31
+ 10a91489e6c637fa.c352ef35bf0779cb.55dd6c2f02f60718.c9e363349751854a
+ 562077cfc8f12c40
+VANDNPS_128(mem)
+ before
+ 55605764ad87cb3e.8a0132957fea83ce.4d17f950c640a51f.8d8cdcd6b9778eff
+ a3717fdf61201f71.4c66a93c507d843b.f9864e1a4fb667d2.a0e166a31b616d6b
+ 1d1d6b2c00c7e405.b22574ebf60c77ee.a16b698175757c10.e82a0800c340e005
+ 9d319838a789d525.1888920c0d219893.2292c67055889f04.c3b1bd5a4ea1227c
+ 8bc3811e570f707a
+ after
+ 55605764ad87cb3e.8a0132957fea83ce.4d17f950c640a51f.8d8cdcd6b9778eff
+ a3717fdf61201f71.4c66a93c507d843b.f9864e1a4fb667d2.a0e166a31b616d6b
+ 0000000000000000.0000000000000000.0411b1408040800d.0d0c9854a0168294
+ 9d319838a789d525.1888920c0d219893.2292c67055889f04.c3b1bd5a4ea1227c
+ 8bc3811e570f707a
+
+VORPS_128(reg)
+ before
+ 9eac51b77a1606ac.007981ed7270b0fd.dadcfc0d2f4a22d6.59c6e1d20afb8edb
+ 56b7279154431fbd.23c1a2387c8b2eba.536caf59fb135262.20d43795b1da03c1
+ 113201188121f85a.e0d57806e1e30e88.e186a85c0b0764e3.548943a46532bae1
+ 2967dab79c3ccd2e.14807d41be860a93.df74e282fbb29406.d1af81eb430e7167
+ 74136d56667be280
+ after
+ 0000000000000000.0000000000000000.f3eeaf5dfb1776e3.74dd77b5f5fabbe1
+ 56b7279154431fbd.23c1a2387c8b2eba.536caf59fb135262.20d43795b1da03c1
+ 113201188121f85a.e0d57806e1e30e88.e186a85c0b0764e3.548943a46532bae1
+ 2967dab79c3ccd2e.14807d41be860a93.df74e282fbb29406.d1af81eb430e7167
+ 74136d56667be280
+VORPS_128(mem)
+ before
+ 178084d2ea84ca58.fba3aedd4221dae6.9b902fd72e7fdf06.a983593768a01d77
+ 97c44049ec35e51b.e3327af30e5b5a2e.51cf09b34edb490d.9b000ae7ed5e3ce1
+ d0aa1fa8889beef4.3e6039669c768ab1.130a88c139a504d6.1035effe27772cf1
+ 9efd9cdcd8c1a20f.6679e7a289ffa61c.bb0d26ed0ce9cb8a.666e06e8b1782b53
+ f8f94a1228ec73b2
+ after
+ 178084d2ea84ca58.fba3aedd4221dae6.9b902fd72e7fdf06.a983593768a01d77
+ 97c44049ec35e51b.e3327af30e5b5a2e.51cf09b34edb490d.9b000ae7ed5e3ce1
+ 0000000000000000.0000000000000000.dbdf2ff76effdf0f.bb835bf7edfe3df7
+ 9efd9cdcd8c1a20f.6679e7a289ffa61c.bb0d26ed0ce9cb8a.666e06e8b1782b53
+ f8f94a1228ec73b2
+
+VORPS_128(reg)
+ before
+ 2220b7e6275f41bb.dd8a34cffbb3bd99.b8c880147081e91a.26a36123e2b35b58
+ 3f314ad24a5ed019.691d616f0b7dfabe.909b0026ee889158.309ab44fd7106f6a
+ ad76fe412e735e79.1e82a1a7242c16aa.4a3c64469fa1d882.b5bc9b5d080cc5ec
+ c63cce9e6f2d2586.d8846f6363cccd88.42f8a7df1d57fa43.91d7923a91b1170c
+ a0b516d08d0d22f3
+ after
+ 0000000000000000.0000000000000000.dabf6466ffa9d9da.b5bebf5fdf1cefee
+ 3f314ad24a5ed019.691d616f0b7dfabe.909b0026ee889158.309ab44fd7106f6a
+ ad76fe412e735e79.1e82a1a7242c16aa.4a3c64469fa1d882.b5bc9b5d080cc5ec
+ c63cce9e6f2d2586.d8846f6363cccd88.42f8a7df1d57fa43.91d7923a91b1170c
+ a0b516d08d0d22f3
+VORPS_128(mem)
+ before
+ bd23a20d182ba1d0.e8cfb957a81561ed.73f1478fe367db84.d41bc55d07363548
+ c6ecb2db4f1851cd.6d7ab8d775b9505a.cb93a617c10bfbcb.5cf1ba2cf6cbc33c
+ 96dec2284edfee16.b38bc98a73a42c78.bc3806e718c4eb89.36c582b889a1e0cc
+ 09c44fdf308c34d8.144ce6dc3e6332f4.21aae5eb059c64e9.bee51a6d5945caa4
+ 509b7db70441bb6f
+ after
+ bd23a20d182ba1d0.e8cfb957a81561ed.73f1478fe367db84.d41bc55d07363548
+ c6ecb2db4f1851cd.6d7ab8d775b9505a.cb93a617c10bfbcb.5cf1ba2cf6cbc33c
+ 0000000000000000.0000000000000000.fbf3e79fe36ffbcf.dcfbff7df7fff77c
+ 09c44fdf308c34d8.144ce6dc3e6332f4.21aae5eb059c64e9.bee51a6d5945caa4
+ 509b7db70441bb6f
+
+VORPS_128(reg)
+ before
+ 4834a7022624f0da.fb69d3ec112cde3f.ee0b0d3a71819d7a.d8b5be10a3a12518
+ 02fc94bb5a77a590.479acc3b0ecaaa76.9b123a0ea88aabb5.bc270e400edfe842
+ da3f414c3dc8153e.cb23b5b8427351aa.78ae67c6800b9652.a9cb4f6963606a92
+ 2c49a9236aa27d90.62d00b4fca319207.e22a92cc948f9afc.7a6cff75be326735
+ 0dd799523a619a56
+ after
+ 0000000000000000.0000000000000000.fbbe7fcea88bbff7.bdef4f696fffead2
+ 02fc94bb5a77a590.479acc3b0ecaaa76.9b123a0ea88aabb5.bc270e400edfe842
+ da3f414c3dc8153e.cb23b5b8427351aa.78ae67c6800b9652.a9cb4f6963606a92
+ 2c49a9236aa27d90.62d00b4fca319207.e22a92cc948f9afc.7a6cff75be326735
+ 0dd799523a619a56
+VORPS_128(mem)
+ before
+ 3dd999ebf3f7c022.5365c8aa7d921931.e76d48ecc11227b8.33d4b68e81a2f560
+ e53c7b2c060295c4.ade19a4f132225ce.38c5ea7c4422cdea.c8f6cf76e2d1e129
+ e3ccbc018f8ed56a.95071b7dc7e1dc12.30a56ce96e6b40c8.fdded9f254a79b04
+ 1157d756a9a63b3d.662448a036587baa.aada4a215cfb3b7f.2fd6d16d72b05f9d
+ b82bb153d879689f
+ after
+ 3dd999ebf3f7c022.5365c8aa7d921931.e76d48ecc11227b8.33d4b68e81a2f560
+ e53c7b2c060295c4.ade19a4f132225ce.38c5ea7c4422cdea.c8f6cf76e2d1e129
+ 0000000000000000.0000000000000000.ffedeafcc532effa.fbf6fffee3f3f569
+ 1157d756a9a63b3d.662448a036587baa.aada4a215cfb3b7f.2fd6d16d72b05f9d
+ b82bb153d879689f
+
+VSQRTSD_128(reg)
+ before
+ f5297710248df3b7.4da748177056846c.7e841c24fc153d41.842e010e29de7b3a
+ 421b1f10ef793c90.718a8b3001aa6c20.38739375b3a36084.986e0c9ef21fbc26
+ fb4fa3c0d7c77ed7.5bca1d8e77afae88.ef3ca9fffa8f1e1f.c465e6bcd2caba6f
+ 7c0f018a7805f638.e534781bef7007ce.012d5b2f6b64b4bd.e2e10d54e5eb3040
+ d0acfd52488fdbc6
+ after
+ 0000000000000000.0000000000000000.38739375b3a36084.fff8000000000000
+ 421b1f10ef793c90.718a8b3001aa6c20.38739375b3a36084.986e0c9ef21fbc26
+ fb4fa3c0d7c77ed7.5bca1d8e77afae88.ef3ca9fffa8f1e1f.c465e6bcd2caba6f
+ 7c0f018a7805f638.e534781bef7007ce.012d5b2f6b64b4bd.e2e10d54e5eb3040
+ d0acfd52488fdbc6
+VSQRTSD_128(mem)
+ before
+ 689430a217c1772d.21a834dc6dbfe05e.ed941ac584fa331f.c890a46fa2ae5d0b
+ 876324306c8ebfa0.46663820528078f6.4db67e775357eea6.a2b2802d3bfa57b5
+ 0ae654e96601714b.479509c4c4d4f9ab.e265211c7796f390.e9dfebd3d4d3dc66
+ cbe93cb71f26465c.8081a3335e47a02a.896e7da20dc0ff08.fb63e1cf06c528cb
+ 32895f8c6f5d798f
+ after
+ 689430a217c1772d.21a834dc6dbfe05e.ed941ac584fa331f.c890a46fa2ae5d0b
+ 876324306c8ebfa0.46663820528078f6.4db67e775357eea6.a2b2802d3bfa57b5
+ 0000000000000000.0000000000000000.4db67e775357eea6.fff8000000000000
+ cbe93cb71f26465c.8081a3335e47a02a.896e7da20dc0ff08.fb63e1cf06c528cb
+ 32895f8c6f5d798f
+
+VSQRTSD_128(reg)
+ before
+ eb9f6076ab25095f.a7375987b309fdfd.4d7603d9bd66a91f.1c9e10f430e3ce3b
+ 83efe0f955ac15e6.7a9e25463fb7505a.09bf24217cbc5035.78bf55fefc0a1b55
+ 54c6db810a7bd9d1.20e81edfde3bfca0.12a9027938d6d018.799ec9ac8e42a481
+ bb704e7a652090cc.76e2bf3eada2bdfb.c3809a4d8c3f6676.fb06e6eb029622ec
+ dac52aa5731254c1
+ after
+ 0000000000000000.0000000000000000.09bf24217cbc5035.5cc631d7bda1823d
+ 83efe0f955ac15e6.7a9e25463fb7505a.09bf24217cbc5035.78bf55fefc0a1b55
+ 54c6db810a7bd9d1.20e81edfde3bfca0.12a9027938d6d018.799ec9ac8e42a481
+ bb704e7a652090cc.76e2bf3eada2bdfb.c3809a4d8c3f6676.fb06e6eb029622ec
+ dac52aa5731254c1
+VSQRTSD_128(mem)
+ before
+ f3a610c7fdc2f42d.1439335002277782.5658854ec7f74f96.7890e60715834ef9
+ 2074143ebdb3bf5c.bc6d88707e1bcaa0.9d16eafd49466d9e.8d25e4146e2ec34d
+ 3efcb2f5cff07179.0d5848447488c4d1.27e86c364e9cd43e.5d8b8fe134cd021f
+ 290a67d74d86c6b1.6445703a81faa2c2.d09986e6f3033fa3.460de3d802eb471b
+ a2f9dd677515ceec
+ after
+ f3a610c7fdc2f42d.1439335002277782.5658854ec7f74f96.7890e60715834ef9
+ 2074143ebdb3bf5c.bc6d88707e1bcaa0.9d16eafd49466d9e.8d25e4146e2ec34d
+ 0000000000000000.0000000000000000.9d16eafd49466d9e.5c4071716076aee0
+ 290a67d74d86c6b1.6445703a81faa2c2.d09986e6f3033fa3.460de3d802eb471b
+ a2f9dd677515ceec
+
+VSQRTSD_128(reg)
+ before
+ cf9978f828d6d23f.bd6aadd25680792f.1d81fabc40fea01f.74f7b4f7538a6cf9
+ 283ab0f9b7ba90c0.d6e702d103ea4720.9458e4384e1ffa93.efcc72568a3a156b
+ 082881d5bf4e441a.4f4fe2c073d1ecb0.2516291947e9ebcb.1de53df0b521f726
+ cdaee7f8dc1d29fa.066cc78bbf40230a.2c07c6cbc5e9b072.da0e90aff04bcd55
+ 0113e78156c25425
+ after
+ 0000000000000000.0000000000000000.9458e4384e1ffa93.2eea12663b98ce14
+ 283ab0f9b7ba90c0.d6e702d103ea4720.9458e4384e1ffa93.efcc72568a3a156b
+ 082881d5bf4e441a.4f4fe2c073d1ecb0.2516291947e9ebcb.1de53df0b521f726
+ cdaee7f8dc1d29fa.066cc78bbf40230a.2c07c6cbc5e9b072.da0e90aff04bcd55
+ 0113e78156c25425
+VSQRTSD_128(mem)
+ before
+ 70c0be51039448c1.d11adfcea9b37c0b.d60c2f1e0643a95b.0577b5ba66aa8535
+ 02e0920a14cd6557.72b663c3c29d79fa.9bf9956561e73ace.0cb1f452c6b9a6c0
+ 9340dd9aa4776610.0acf7244c4655c72.31ff754dee379190.9d027eff80a04ebe
+ ffad1decd0a0091b.f6b105bb4a9a6020.74ec4bc0c93f6ccd.14b74f2e31edbadc
+ cd1a6349742c25c5
+ after
+ 70c0be51039448c1.d11adfcea9b37c0b.d60c2f1e0643a95b.0577b5ba66aa8535
+ 02e0920a14cd6557.72b663c3c29d79fa.9bf9956561e73ace.0cb1f452c6b9a6c0
+ 0000000000000000.0000000000000000.9bf9956561e73ace.22b37a243520ff41
+ ffad1decd0a0091b.f6b105bb4a9a6020.74ec4bc0c93f6ccd.14b74f2e31edbadc
+ cd1a6349742c25c5
+
+VCMPSD_128_0x0(reg)
+ before
+ 2477b7bee5e8cd26.21f1cdecb35407a2.93a81995f1c5c2b0.3f8b93ac0d0c85b0
+ 741c45f721adecab.d7d86a876a9d1fd1.3b00ab3f5474becd.70a7cafbd7a99865
+ 1b540b62c407bfff.fc306ea710890bd5.4b05b62410338f24.e20d6b9b4222631a
+ 746a056a698381cf.6bc45739c22488da.1f0236afc08c7260.708af2776a84a0f9
+ f8e8dc7b6cda0c2e
+ after
+ 0000000000000000.0000000000000000.3b00ab3f5474becd.0000000000000000
+ 741c45f721adecab.d7d86a876a9d1fd1.3b00ab3f5474becd.70a7cafbd7a99865
+ 1b540b62c407bfff.fc306ea710890bd5.4b05b62410338f24.e20d6b9b4222631a
+ 746a056a698381cf.6bc45739c22488da.1f0236afc08c7260.708af2776a84a0f9
+ f8e8dc7b6cda0c2e
+VCMPSD_128_0x0(mem)
+ before
+ 54f3a393633162e6.dbab2d7aacac70c6.025fa02a9b79520b.1444274e010da32f
+ 6279c5ab6c93604d.ab6381002a0fc691.9bcec564b8942495.8418866c6e425e3a
+ fc44bdafa30ec08e.42defc677f37bfdb.14dd43d53481bba4.ccc84e75a4b6de2f
+ 0022088c23ae3ed6.fa689a1c45b09951.475894682c4dd363.48a07bd53ef560ba
+ 54ee09f8d98b2087
+ after
+ 54f3a393633162e6.dbab2d7aacac70c6.025fa02a9b79520b.1444274e010da32f
+ 6279c5ab6c93604d.ab6381002a0fc691.9bcec564b8942495.8418866c6e425e3a
+ 0000000000000000.0000000000000000.9bcec564b8942495.0000000000000000
+ 0022088c23ae3ed6.fa689a1c45b09951.475894682c4dd363.48a07bd53ef560ba
+ 54ee09f8d98b2087
+
+VCMPSD_128_0x0(reg)
+ before
+ 4cfdf44b10055941.48dd202c087e9851.314c57891b078e9f.120b3609bb0328fe
+ 8c1839387fee4994.b242837c6f8a882a.42d8301b9ac7db70.4fc2a4a3fdaf75a3
+ 708cd32cc3d22a2d.181dac6973decb8d.88561f3f617cbb71.dc485b240f5e777b
+ 54a5be94773e38b8.573a17de30871ca8.6113225f09b36b4e.936ad5780d1beab5
+ 51f4908912f3897b
+ after
+ 0000000000000000.0000000000000000.42d8301b9ac7db70.0000000000000000
+ 8c1839387fee4994.b242837c6f8a882a.42d8301b9ac7db70.4fc2a4a3fdaf75a3
+ 708cd32cc3d22a2d.181dac6973decb8d.88561f3f617cbb71.dc485b240f5e777b
+ 54a5be94773e38b8.573a17de30871ca8.6113225f09b36b4e.936ad5780d1beab5
+ 51f4908912f3897b
+VCMPSD_128_0x0(mem)
+ before
+ f3b207443af112fa.94aff6db38bdb1e1.4c6440c6c49039a4.275b34e931f627b2
+ 5370b696a2213e5d.8cf6786ca2dccf52.d169a40f4806dcb0.377a524772d42b4a
+ 4efa1a69658fccd1.98c53eb55025cfba.c313bea4daf4c1f6.eebc77e76ad6b3c1
+ c01badaba0487681.146a4621de27ecc3.ff2f0a719666a6a3.a66c9e34b58afac4
+ bcd8c59aee7c3dfe
+ after
+ f3b207443af112fa.94aff6db38bdb1e1.4c6440c6c49039a4.275b34e931f627b2
+ 5370b696a2213e5d.8cf6786ca2dccf52.d169a40f4806dcb0.377a524772d42b4a
+ 0000000000000000.0000000000000000.d169a40f4806dcb0.0000000000000000
+ c01badaba0487681.146a4621de27ecc3.ff2f0a719666a6a3.a66c9e34b58afac4
+ bcd8c59aee7c3dfe
+
+VCMPSD_128_0x0(reg)
+ before
+ 8d4ae885b136b71c.85a1ed466e57f99a.5c2f8b1ce96b631a.5f890462976845e2
+ 730f01619b46a6ca.7a565528ecc91148.cb610a120c7f706a.c0ed2864f9075be0
+ cb730e9b483844b3.7907613c35a97ab6.bf4cbd70e4ee4f60.fe26f361d94ea4c8
+ f1c10a9d5396cd84.5f808e6e6603ef11.933ca2a00c453ba8.f502e046534adbc7
+ 814b6b008206bd09
+ after
+ 0000000000000000.0000000000000000.cb610a120c7f706a.0000000000000000
+ 730f01619b46a6ca.7a565528ecc91148.cb610a120c7f706a.c0ed2864f9075be0
+ cb730e9b483844b3.7907613c35a97ab6.bf4cbd70e4ee4f60.fe26f361d94ea4c8
+ f1c10a9d5396cd84.5f808e6e6603ef11.933ca2a00c453ba8.f502e046534adbc7
+ 814b6b008206bd09
+VCMPSD_128_0x0(mem)
+ before
+ 7ece107a828e06b9.4247f1d558ee7fe8.088c57aa9ae42d84.a27db40f200f71ed
+ c8574c9f70ef7104.184fbfadf4cc948c.50f938dcee57ef3c.4a5af02abed82ddc
+ 3bb29a5d6734bb15.d0277193c2bb491c.1391adf07d68f365.e620505c7f2cab20
+ b3aa769f8469a019.c61902f25f47da43.2d2232d36324f32a.d11bd21001982666
+ 699771b4e0a7db59
+ after
+ 7ece107a828e06b9.4247f1d558ee7fe8.088c57aa9ae42d84.a27db40f200f71ed
+ c8574c9f70ef7104.184fbfadf4cc948c.50f938dcee57ef3c.4a5af02abed82ddc
+ 0000000000000000.0000000000000000.50f938dcee57ef3c.0000000000000000
+ b3aa769f8469a019.c61902f25f47da43.2d2232d36324f32a.d11bd21001982666
+ 699771b4e0a7db59
+
+VCMPSD_128_0x1(reg)
+ before
+ 08e029b3b7e606a6.0c0d5c51e29bdc3c.56726e3566fc82ae.7a76446fbd95acb8
+ 0c42f67922e0e2f9.22a5c85f9ed52aa9.dc7db1ca74677e08.d65a5eb2a7cad93a
+ cf09d572be21acfd.d14037b5d323488c.b488c81c24130afe.1c99fc863ccc37dd
+ af80c10a2736a05f.f5a824409e92ef13.3addad97138c613c.2a019ad998a982cd
+ db5db496d86d7635
+ after
+ 0000000000000000.0000000000000000.dc7db1ca74677e08.ffffffffffffffff
+ 0c42f67922e0e2f9.22a5c85f9ed52aa9.dc7db1ca74677e08.d65a5eb2a7cad93a
+ cf09d572be21acfd.d14037b5d323488c.b488c81c24130afe.1c99fc863ccc37dd
+ af80c10a2736a05f.f5a824409e92ef13.3addad97138c613c.2a019ad998a982cd
+ db5db496d86d7635
+VCMPSD_128_0x1(mem)
+ before
+ 0b78c7a91722ce41.06f4b6adf7aafacb.69aa0bea1a2dde68.caca5ea8dc5fc16d
+ 961f4efe72d6481f.32b1b0c8cd09f5ec.0b1168a06400cfb7.c099d6b91c17643e
+ 571ec58105959df9.8d03abc543e0ce6e.b6abb84f97187f2d.789712376e41865a
+ 2c41a91eea6a8cfb.7436a412f5bac1ff.464276e2cf80aaf6.4d100c8f6e68656e
+ 9d4fc22bb9183b26
+ after
+ 0b78c7a91722ce41.06f4b6adf7aafacb.69aa0bea1a2dde68.caca5ea8dc5fc16d
+ 961f4efe72d6481f.32b1b0c8cd09f5ec.0b1168a06400cfb7.c099d6b91c17643e
+ 0000000000000000.0000000000000000.0b1168a06400cfb7.0000000000000000
+ 2c41a91eea6a8cfb.7436a412f5bac1ff.464276e2cf80aaf6.4d100c8f6e68656e
+ 9d4fc22bb9183b26
+
+VCMPSD_128_0x1(reg)
+ before
+ c3a22f79ebdd442d.f05474c14061cf52.4496961980230949.96a41e4429440b3e
+ 1b534fe49f44be30.7e22a4572086232a.576e7d487fa8e4f8.849b2c63c1715f2f
+ 00af1fd871d8e3da.b478b4caa9e644ae.0a0b550a8fd48bb9.eaf41c2ab21262f8
+ d00399c1fe26f0d8.6c232008f48ced0b.b9b91bcb4b333d38.a67a6b851833d0c3
+ 92fb946010e164bd
+ after
+ 0000000000000000.0000000000000000.576e7d487fa8e4f8.0000000000000000
+ 1b534fe49f44be30.7e22a4572086232a.576e7d487fa8e4f8.849b2c63c1715f2f
+ 00af1fd871d8e3da.b478b4caa9e644ae.0a0b550a8fd48bb9.eaf41c2ab21262f8
+ d00399c1fe26f0d8.6c232008f48ced0b.b9b91bcb4b333d38.a67a6b851833d0c3
+ 92fb946010e164bd
+VCMPSD_128_0x1(mem)
+ before
+ 8c4213a7b527db11.e698bb0be2b921d5.84ed65fc1f84db6d.c0c4caf74f523420
+ 6e1a64472411f1ec.9dbd8022b71db17e.d6a3fd9146dbcaff.7b785efa38bcad1e
+ 1650032a79ac6179.53bde5721cdfde7f.401066b5849c76ee.4721d340a2fde4dd
+ 5eb06d3ece03e8e5.62e3e468aa8ae183.9c021b53f5d49a65.7e0a253528a2150a
+ 7d81514666367b51
+ after
+ 8c4213a7b527db11.e698bb0be2b921d5.84ed65fc1f84db6d.c0c4caf74f523420
+ 6e1a64472411f1ec.9dbd8022b71db17e.d6a3fd9146dbcaff.7b785efa38bcad1e
+ 0000000000000000.0000000000000000.d6a3fd9146dbcaff.0000000000000000
+ 5eb06d3ece03e8e5.62e3e468aa8ae183.9c021b53f5d49a65.7e0a253528a2150a
+ 7d81514666367b51
+
+VCMPSD_128_0x1(reg)
+ before
+ a0d052ddf946535d.24061d6d4123425c.287c7b6e00aaf937.c8439957b68df391
+ 434424687d5cd9db.421e8fa5ee172b09.ffd5a5f1b7cb6047.9ea15aade3d53d9d
+ c129c3528d074876.95c340d1f0eb5e19.45385e5e6e7a535e.fbe6dc4197b833b6
+ 78cb2c06c5d0dddb.fac3aadc64ab98b8.54f1a320be430e29.bcdf9a00ee419308
+ bb5810d4057c16be
+ after
+ 0000000000000000.0000000000000000.ffd5a5f1b7cb6047.0000000000000000
+ 434424687d5cd9db.421e8fa5ee172b09.ffd5a5f1b7cb6047.9ea15aade3d53d9d
+ c129c3528d074876.95c340d1f0eb5e19.45385e5e6e7a535e.fbe6dc4197b833b6
+ 78cb2c06c5d0dddb.fac3aadc64ab98b8.54f1a320be430e29.bcdf9a00ee419308
+ bb5810d4057c16be
+VCMPSD_128_0x1(mem)
+ before
+ d51cbaabf7767b05.c37559f2c245d4b6.4be84bb465649511.8a4e6ea345b0cc53
+ e6f9156fe1397c08.fe7548811ff168b2.65ff9e4410211050.4199bd539f4fcb89
+ cab99c0eded4d6f4.8515f51f7961d77b.24d41f7980efc7a3.d6208b9c67ac4476
+ 5e29cb730b5045f5.b4a25a386b1f5abf.64334b3dd1d97333.a62dd4ea395176c7
+ 0b0d95a9b2cc9b28
+ after
+ d51cbaabf7767b05.c37559f2c245d4b6.4be84bb465649511.8a4e6ea345b0cc53
+ e6f9156fe1397c08.fe7548811ff168b2.65ff9e4410211050.4199bd539f4fcb89
+ 0000000000000000.0000000000000000.65ff9e4410211050.0000000000000000
+ 5e29cb730b5045f5.b4a25a386b1f5abf.64334b3dd1d97333.a62dd4ea395176c7
+ 0b0d95a9b2cc9b28
+
+VCMPSD_128_0x2(reg)
+ before
+ 620cc9456ea9f044.7c151e8a83bb8536.e668753992ba3028.02e79c7d20ebd32f
+ 07766c2a0872b1c8.0149123f632051e4.79b3408c89bb9462.d8be90268932a1c1
+ 56967ac51cb51a5f.c991227ec68c662a.c8ceb99eedb0c11a.c382a22227b99a15
+ acbaef8047fe66b6.b0b9ca33c90a7f35.2e07dcdc5924f4fc.9f004f5f168c7a59
+ 480411c773b7fdb6
+ after
+ 0000000000000000.0000000000000000.79b3408c89bb9462.ffffffffffffffff
+ 07766c2a0872b1c8.0149123f632051e4.79b3408c89bb9462.d8be90268932a1c1
+ 56967ac51cb51a5f.c991227ec68c662a.c8ceb99eedb0c11a.c382a22227b99a15
+ acbaef8047fe66b6.b0b9ca33c90a7f35.2e07dcdc5924f4fc.9f004f5f168c7a59
+ 480411c773b7fdb6
+VCMPSD_128_0x2(mem)
+ before
+ 9a5a66485947de5b.632cc8c924d8d279.928c864a87a65a31.09a8a3b06aa468b3
+ 71cec9cde548da72.d839ff0b50cf9953.4bd7d2af1d6db149.b4fe0c88bbbb5aec
+ a92bb64232c4ad27.672d93b2666ff9f1.b7662b4fa66a41aa.8a5512cfe8f50653
+ 1d3eaa935dc912a7.6c547d2a03452cfe.b2050b143ea9c57f.e9f9b1f18edea893
+ 2b36e55a49037b59
+ after
+ 9a5a66485947de5b.632cc8c924d8d279.928c864a87a65a31.09a8a3b06aa468b3
+ 71cec9cde548da72.d839ff0b50cf9953.4bd7d2af1d6db149.b4fe0c88bbbb5aec
+ 0000000000000000.0000000000000000.4bd7d2af1d6db149.ffffffffffffffff
+ 1d3eaa935dc912a7.6c547d2a03452cfe.b2050b143ea9c57f.e9f9b1f18edea893
+ 2b36e55a49037b59
+
+VCMPSD_128_0x2(reg)
+ before
+ ae57ab76b4f0bd50.abd41fac8163c61e.43f9badfc2dc6f27.1880f1ec0237faf5
+ ccaafeb16b2fa725.2eb7937abb9c85b8.486a473d40c0fd18.c4a356c20d1f9c38
+ e379da770b4e7883.82b481e726820a9f.d7f11fb0187e137c.9439b7827c6d6773
+ 4d113b352fd96a17.839666e0de211302.4bdb3ea4e7a1ed00.630f91176b2e16d3
+ 0df25f6ff56d6783
+ after
+ 0000000000000000.0000000000000000.486a473d40c0fd18.ffffffffffffffff
+ ccaafeb16b2fa725.2eb7937abb9c85b8.486a473d40c0fd18.c4a356c20d1f9c38
+ e379da770b4e7883.82b481e726820a9f.d7f11fb0187e137c.9439b7827c6d6773
+ 4d113b352fd96a17.839666e0de211302.4bdb3ea4e7a1ed00.630f91176b2e16d3
+ 0df25f6ff56d6783
+VCMPSD_128_0x2(mem)
+ before
+ 6dac9d76363613b0.67be1d55745aba8d.0c2bbc5200835a0b.0274a08648b6c74f
+ 6109c7164b96d985.8ecc7d45755fa490.fb3d0128a8b69be7.570842c0d748dc16
+ c4d75a3c4f987330.1c86566fcf7464cd.2b9ab04df1c694c1.a6e31fc031e36901
+ 71e1d1d45f489eda.6e3aa4411d2335ef.770c45aff7bdffc6.4b5033f0f213aabb
+ a19d7abeb565dbf0
+ after
+ 6dac9d76363613b0.67be1d55745aba8d.0c2bbc5200835a0b.0274a08648b6c74f
+ 6109c7164b96d985.8ecc7d45755fa490.fb3d0128a8b69be7.570842c0d748dc16
+ 0000000000000000.0000000000000000.fb3d0128a8b69be7.0000000000000000
+ 71e1d1d45f489eda.6e3aa4411d2335ef.770c45aff7bdffc6.4b5033f0f213aabb
+ a19d7abeb565dbf0
+
+VCMPSD_128_0x2(reg)
+ before
+ 0614f0951664374e.46f2a8cb96b316b2.e0326326fcfa54a3.bd603c39d7a99922
+ d50292e1b29dfb7f.1dd75b0b10e496e2.cebb908a0785fc95.d86112d7ad961d00
+ 69b35b0e249b632f.d45c6682eae7db96.952126d9db4e6b70.a3dd4275948f488c
+ 2072478809eaaa0b.454d461b40c9a1fb.8fb0217f13e3dbe1.fc9f48ffa8a0d6f4
+ bd72a06206d58362
+ after
+ 0000000000000000.0000000000000000.cebb908a0785fc95.ffffffffffffffff
+ d50292e1b29dfb7f.1dd75b0b10e496e2.cebb908a0785fc95.d86112d7ad961d00
+ 69b35b0e249b632f.d45c6682eae7db96.952126d9db4e6b70.a3dd4275948f488c
+ 2072478809eaaa0b.454d461b40c9a1fb.8fb0217f13e3dbe1.fc9f48ffa8a0d6f4
+ bd72a06206d58362
+VCMPSD_128_0x2(mem)
+ before
+ c323c788c93b0b02.558d52bcfd170dbf.4e7676c22d95a43d.19b47de84bd08894
+ eb7e375f0edd2901.634e79149aacc8f6.c9a37263ce589f87.8f78368020a0b034
+ 0f4f6ed1f0c89a8b.a803b7fd7f38175d.949fb6ea3e1c4f06.4d4949b42edf8d6d
+ 0d62e8cc8c0619cb.7ef608e4454435a0.8937bf4399f070e5.af74b1ee10195cec
+ 11436a9c62db595d
+ after
+ c323c788c93b0b02.558d52bcfd170dbf.4e7676c22d95a43d.19b47de84bd08894
+ eb7e375f0edd2901.634e79149aacc8f6.c9a37263ce589f87.8f78368020a0b034
+ 0000000000000000.0000000000000000.c9a37263ce589f87.ffffffffffffffff
+ 0d62e8cc8c0619cb.7ef608e4454435a0.8937bf4399f070e5.af74b1ee10195cec
+ 11436a9c62db595d
+
+VCMPSD_128_0x3(reg)
+ before
+ cf037028c1b0bf6b.bf821f3bfda564ee.437468338a5e5f6a.8537085afcddbd51
+ 45ffc000c924cbc3.027d910a60b1351f.51c9d358ea12d167.656b0d1b82f1f476
+ cf85558f14c4b911.b21db824d035488b.054046be00eac645.039f4a734837ce7f
+ c8df2a41411bc500.ac2f1278693d5b5e.bc27bcd169747bae.3c9f3b4c6abc0a99
+ ec365d94028b62f0
+ after
+ 0000000000000000.0000000000000000.51c9d358ea12d167.0000000000000000
+ 45ffc000c924cbc3.027d910a60b1351f.51c9d358ea12d167.656b0d1b82f1f476
+ cf85558f14c4b911.b21db824d035488b.054046be00eac645.039f4a734837ce7f
+ c8df2a41411bc500.ac2f1278693d5b5e.bc27bcd169747bae.3c9f3b4c6abc0a99
+ ec365d94028b62f0
+VCMPSD_128_0x3(mem)
+ before
+ f0322b362fb093af.8e5b3e82e9b62a3d.ca7f1bef48d628c3.d0c831fdc03c2c4e
+ 225d211d0a375902.7c438abeab202573.e9d94d76890a6ce7.9e70a1aea1cc15d2
+ 5f84bb37b22d7016.eee40c6120e5f14f.e50826f947e8e3f5.836b0850a9b271e6
+ 8373766f409d9317.3f89bfd8e791cc7d.9ada21659e79481a.d905634f747a7d35
+ fd8aad189dae756c
+ after
+ f0322b362fb093af.8e5b3e82e9b62a3d.ca7f1bef48d628c3.d0c831fdc03c2c4e
+ 225d211d0a375902.7c438abeab202573.e9d94d76890a6ce7.9e70a1aea1cc15d2
+ 0000000000000000.0000000000000000.e9d94d76890a6ce7.0000000000000000
+ 8373766f409d9317.3f89bfd8e791cc7d.9ada21659e79481a.d905634f747a7d35
+ fd8aad189dae756c
+
+VCMPSD_128_0x3(reg)
+ before
+ 4b45e215c0dc9436.6af6ccb1d2947f31.cd809f8d99b1f0a8.e419baa4abcb5882
+ 1f84ffb47a901840.f0d83be9841def8f.f314a8eed4d19a7d.9f926da48ae9cf58
+ d591fe5f66543a36.f1e63f047144a15d.0c90d665347b05a7.a711b74f55e068c9
+ c9b9dd8421b639c3.49ed52ecb6164fc8.76412660543d6fd3.d86212932bbbe000
+ 0e51fc5b2686f32a
+ after
+ 0000000000000000.0000000000000000.f314a8eed4d19a7d.0000000000000000
+ 1f84ffb47a901840.f0d83be9841def8f.f314a8eed4d19a7d.9f926da48ae9cf58
+ d591fe5f66543a36.f1e63f047144a15d.0c90d665347b05a7.a711b74f55e068c9
+ c9b9dd8421b639c3.49ed52ecb6164fc8.76412660543d6fd3.d86212932bbbe000
+ 0e51fc5b2686f32a
+VCMPSD_128_0x3(mem)
+ before
+ 25a9f193624e5d73.5848978e46424f94.d4b7f28e6e9eb6fc.8c73934ad1a212ac
+ f9376b27fc1ed906.dc8a28e97283ba54.6e1199d7b5e89125.a972198f46372adf
+ 66c8e8030f022510.b2ca8d014005b3b0.f3c7c5b2a8019d6d.2b8ab49b4f87f518
+ 4826e314b707fabc.3556c1424d547954.3ea4f20a63f49603.6c0661da891ead02
+ c9341bb88f898f4a
+ after
+ 25a9f193624e5d73.5848978e46424f94.d4b7f28e6e9eb6fc.8c73934ad1a212ac
+ f9376b27fc1ed906.dc8a28e97283ba54.6e1199d7b5e89125.a972198f46372adf
+ 0000000000000000.0000000000000000.6e1199d7b5e89125.0000000000000000
+ 4826e314b707fabc.3556c1424d547954.3ea4f20a63f49603.6c0661da891ead02
+ c9341bb88f898f4a
+
+VCMPSD_128_0x3(reg)
+ before
+ 9f5edea1fe53d69c.7a1ed84411381737.c378bf1834fd46eb.2d769acd00cd3811
+ 48d1a6017208c0a3.da7b438139a136ad.b77d86f0928b5722.9b073be69e993ec4
+ 22d970458535870b.430ba1b54a4f1449.6db10f34028be8a4.6424504157636647
+ 87c136d7d6656782.91986cce614d6d38.416057522087341e.639955ca473769c7
+ 7632c66d8b220670
+ after
+ 0000000000000000.0000000000000000.b77d86f0928b5722.0000000000000000
+ 48d1a6017208c0a3.da7b438139a136ad.b77d86f0928b5722.9b073be69e993ec4
+ 22d970458535870b.430ba1b54a4f1449.6db10f34028be8a4.6424504157636647
+ 87c136d7d6656782.91986cce614d6d38.416057522087341e.639955ca473769c7
+ 7632c66d8b220670
+VCMPSD_128_0x3(mem)
+ before
+ 78bb20173e2ff76d.d4d7f625fe249eb1.9ff022b699a7fca5.8fd65bb4890e783c
+ 44ffdeb27d6af9eb.6566ab9a9cff6647.4bdd3e5b0e6a7ebd.b25e16c8d9a9f0a9
+ b8cc7c2b63e0c815.97b952a24981fcee.6f2c3da8dda1afab.084685f9abe6d811
+ aeec766f0d9c1f18.c41de5a9a4369c53.e9a8998922584b9c.ecd8a2b29b506b22
+ ba616b614674e686
+ after
+ 78bb20173e2ff76d.d4d7f625fe249eb1.9ff022b699a7fca5.8fd65bb4890e783c
+ 44ffdeb27d6af9eb.6566ab9a9cff6647.4bdd3e5b0e6a7ebd.b25e16c8d9a9f0a9
+ 0000000000000000.0000000000000000.4bdd3e5b0e6a7ebd.0000000000000000
+ aeec766f0d9c1f18.c41de5a9a4369c53.e9a8998922584b9c.ecd8a2b29b506b22
+ ba616b614674e686
+
+VCMPSD_128_0x4(reg)
+ before
+ cd2dda7147dd84e9.042c486996aabb1f.49de621b46ab8121.941fd0eaf79c0dbc
+ 8388ee4f3b1783f8.94586f041a175857.8248c464cd6be805.4b5c5db87b78b236
+ 36bda065bdae1d5f.3c3b662eb6eeb2ec.cba607f0d5020daa.ec2abdddc8f9f637
+ 441aed206a2f8fc9.d6a3a9d2863c8409.8046282bf9fd2bbd.51566a46fa2a94eb
+ 57ace2e02e17497d
+ after
+ 0000000000000000.0000000000000000.8248c464cd6be805.ffffffffffffffff
+ 8388ee4f3b1783f8.94586f041a175857.8248c464cd6be805.4b5c5db87b78b236
+ 36bda065bdae1d5f.3c3b662eb6eeb2ec.cba607f0d5020daa.ec2abdddc8f9f637
+ 441aed206a2f8fc9.d6a3a9d2863c8409.8046282bf9fd2bbd.51566a46fa2a94eb
+ 57ace2e02e17497d
+VCMPSD_128_0x4(mem)
+ before
+ dbf8a0957fccd11a.07e9d2eddd2614e3.405bb4dca50c8bdb.fd722182d5e77fea
+ b70620530a56e8ed.dd774a36b31dea59.542e04382f6a838e.9e77f05f064c45dc
+ c8a1de05eac04923.2010516987a24bd6.efe914d34162274d.bfa2903028b9b940
+ eb9757973b17b1e7.2e00e4f0f6407306.ee586097f7013444.bc3cfd5fd6b916c1
+ f194345aacd9990c
+ after
+ dbf8a0957fccd11a.07e9d2eddd2614e3.405bb4dca50c8bdb.fd722182d5e77fea
+ b70620530a56e8ed.dd774a36b31dea59.542e04382f6a838e.9e77f05f064c45dc
+ 0000000000000000.0000000000000000.542e04382f6a838e.ffffffffffffffff
+ eb9757973b17b1e7.2e00e4f0f6407306.ee586097f7013444.bc3cfd5fd6b916c1
+ f194345aacd9990c
+
+VCMPSD_128_0x4(reg)
+ before
+ baf5308c47a47ecc.fab206f51a66dc66.6193fd399b84a097.2b4764716b5266a1
+ 73aaed6142a601af.d2bf670ba3b985cc.17149aaf13f90c33.83819c4ebc62798d
+ 770067453a6b5d5e.4f8af6c5f11c6a44.aad0b6bef92bf486.d2d48518043c2837
+ 24439aa4ca80cf88.4edf2f0f219c44fb.77144ed2e9a7943d.f50a9abd5fec30c9
+ c6f05728ea7e4d6f
+ after
+ 0000000000000000.0000000000000000.17149aaf13f90c33.ffffffffffffffff
+ 73aaed6142a601af.d2bf670ba3b985cc.17149aaf13f90c33.83819c4ebc62798d
+ 770067453a6b5d5e.4f8af6c5f11c6a44.aad0b6bef92bf486.d2d48518043c2837
+ 24439aa4ca80cf88.4edf2f0f219c44fb.77144ed2e9a7943d.f50a9abd5fec30c9
+ c6f05728ea7e4d6f
+VCMPSD_128_0x4(mem)
+ before
+ 22523845c0ff3b57.d5bf83ea8f7093d7.a9898fd54e44d21c.da2a5c5780f82704
+ e5fcba00fd7bb5aa.e6c01d8424c8e4f7.3d5691049421ced4.305edeba5aaaea86
+ ebba5745bffc7897.b29264dc2613ff95.e610b186103ef54f.d3fecf65124a1970
+ 10588d001f903f48.9780545f30dd205d.80846b49dda703b8.20552bc64463ef6d
+ 73aeee478d82a92a
+ after
+ 22523845c0ff3b57.d5bf83ea8f7093d7.a9898fd54e44d21c.da2a5c5780f82704
+ e5fcba00fd7bb5aa.e6c01d8424c8e4f7.3d5691049421ced4.305edeba5aaaea86
+ 0000000000000000.0000000000000000.3d5691049421ced4.ffffffffffffffff
+ 10588d001f903f48.9780545f30dd205d.80846b49dda703b8.20552bc64463ef6d
+ 73aeee478d82a92a
+
+VCMPSD_128_0x4(reg)
+ before
+ 2856155688318353.30a1d71d3b42c8e9.f0d8e97adeb383fa.e77e3c381869b43c
+ 9b999b5ed2feb993.2762b2892f1fcda8.18e42098ce1f6319.f7ca9f3edc8fc306
+ 28c37cca06758697.d167982e16320bae.6df1f42599b0fd66.8c3410494625ed43
+ 2b20b408c121270a.0a7c07fa0c873d2a.494b618cddef8d8c.82870b447138ee1f
+ b5900c1b7ad281c5
+ after
+ 0000000000000000.0000000000000000.18e42098ce1f6319.ffffffffffffffff
+ 9b999b5ed2feb993.2762b2892f1fcda8.18e42098ce1f6319.f7ca9f3edc8fc306
+ 28c37cca06758697.d167982e16320bae.6df1f42599b0fd66.8c3410494625ed43
+ 2b20b408c121270a.0a7c07fa0c873d2a.494b618cddef8d8c.82870b447138ee1f
+ b5900c1b7ad281c5
+VCMPSD_128_0x4(mem)
+ before
+ 001c90bb7c026362.00fc3f839e8ed899.ae6d7ad72e2b2046.0a3d643b356a4e37
+ 41f5120e94d15021.03a21aa73a48d5f0.98066eb39829702e.0a15f79d3eac7d15
+ 53e80e01dd4d032f.906040e130dc59ba.a6125d79658de90f.a71d181f944256d0
+ 12c0008174823ab7.0380ad9b1dd5a1a4.b35ec515b1644615.3ba3c22bd2b71514
+ 24f1f12e9497f58e
+ after
+ 001c90bb7c026362.00fc3f839e8ed899.ae6d7ad72e2b2046.0a3d643b356a4e37
+ 41f5120e94d15021.03a21aa73a48d5f0.98066eb39829702e.0a15f79d3eac7d15
+ 0000000000000000.0000000000000000.98066eb39829702e.ffffffffffffffff
+ 12c0008174823ab7.0380ad9b1dd5a1a4.b35ec515b1644615.3ba3c22bd2b71514
+ 24f1f12e9497f58e
+
+VCMPSD_128_0x5(reg)
+ before
+ bc53a295776f33ea.594b6578747bafe7.b84f5e429cc0e859.9bb7217399b9446b
+ 6017cfca16ca0bd3.0653b8d4f9441ee8.0b194d4349276c86.39e7ed7f38989f3e
+ 6c88763b0e34b8f6.f4a6758020e945e9.58297808c19967d7.6bbaa525ab0e13ba
+ 3df19253fa3a77fe.fe0e18670577de14.facddaffa09f16f7.0cfec6510d265b0a
+ f77ecaf07bec345b
+ after
+ 0000000000000000.0000000000000000.0b194d4349276c86.0000000000000000
+ 6017cfca16ca0bd3.0653b8d4f9441ee8.0b194d4349276c86.39e7ed7f38989f3e
+ 6c88763b0e34b8f6.f4a6758020e945e9.58297808c19967d7.6bbaa525ab0e13ba
+ 3df19253fa3a77fe.fe0e18670577de14.facddaffa09f16f7.0cfec6510d265b0a
+ f77ecaf07bec345b
+VCMPSD_128_0x5(mem)
+ before
+ 0a052fec106d5ad8.2da0207d77678498.02581d77c3f9a695.4f4f6f9381c7b492
+ 20607133e9b488ae.99df1a2720471b70.db4f019b767b5899.b2fc3430009c7f56
+ 145b0aaf21ce7b08.ddfb7ebc92677731.64c13fbf3b0ab14c.7e202342baabb0ed
+ c4c2784ed4c5ef14.554047a86852d588.7b7953d02db16dd9.11073a354a7f8603
+ c6fd74754da43c45
+ after
+ 0a052fec106d5ad8.2da0207d77678498.02581d77c3f9a695.4f4f6f9381c7b492
+ 20607133e9b488ae.99df1a2720471b70.db4f019b767b5899.b2fc3430009c7f56
+ 0000000000000000.0000000000000000.db4f019b767b5899.0000000000000000
+ c4c2784ed4c5ef14.554047a86852d588.7b7953d02db16dd9.11073a354a7f8603
+ c6fd74754da43c45
+
+VCMPSD_128_0x5(reg)
+ before
+ f84ece6e5ea60d5f.0a6136fb1fa8a0fb.5df971583e957120.fa42b9b8697c486d
+ 0545428d1a1236fc.c304c0a21e8049eb.5174f936b1ba86a6.bfe9ee640b78fe33
+ 472fce3c1c74f2c9.cc76922fec5ba710.8efbd9af5d4f52c6.a43a6cc12db04a59
+ 1c586de801567e72.ff84298ea5447696.6ddb0f30dde00f2b.8601b1b9ee31e908
+ 420a383a6706966e
+ after
+ 0000000000000000.0000000000000000.5174f936b1ba86a6.0000000000000000
+ 0545428d1a1236fc.c304c0a21e8049eb.5174f936b1ba86a6.bfe9ee640b78fe33
+ 472fce3c1c74f2c9.cc76922fec5ba710.8efbd9af5d4f52c6.a43a6cc12db04a59
+ 1c586de801567e72.ff84298ea5447696.6ddb0f30dde00f2b.8601b1b9ee31e908
+ 420a383a6706966e
+VCMPSD_128_0x5(mem)
+ before
+ b2207e2fb63b0fb7.de0c1bfe644616a2.39faffab664771a8.4d609623cdf8f982
+ b311fd84f7dc0e0f.eb97d4e9e2cff605.57a492724b715572.89d66bf6ca234e76
+ 22a7332545f64fa1.9d459515167e5a49.334e5ed06fcdde22.7d8988146fed48b4
+ d9af9bfebd949099.516159ee9dde7d18.aac4ddafee68c8e2.85c4ebe959e323e8
+ fdd58fe124901dbd
+ after
+ b2207e2fb63b0fb7.de0c1bfe644616a2.39faffab664771a8.4d609623cdf8f982
+ b311fd84f7dc0e0f.eb97d4e9e2cff605.57a492724b715572.89d66bf6ca234e76
+ 0000000000000000.0000000000000000.57a492724b715572.0000000000000000
+ d9af9bfebd949099.516159ee9dde7d18.aac4ddafee68c8e2.85c4ebe959e323e8
+ fdd58fe124901dbd
+
+VCMPSD_128_0x5(reg)
+ before
+ 410670686a8170e0.b5f5b1fb7ac38b25.64391ce0127b9c1e.98d18dfde54dcede
+ ada48aeaca4159fc.9245f208988efd6e.3017da5711e2f208.da43e9a56f88ad43
+ 9cfbdad3dd5c14be.4c6ad8113401a2a3.124890bf379ebd82.4ae46d92a926213d
+ 6c575b8f425edcd2.bf32e1036a2935ee.66183884203b3737.c58195b2ae31e6f7
+ 27e6ddf09bb8b79e
+ after
+ 0000000000000000.0000000000000000.3017da5711e2f208.0000000000000000
+ ada48aeaca4159fc.9245f208988efd6e.3017da5711e2f208.da43e9a56f88ad43
+ 9cfbdad3dd5c14be.4c6ad8113401a2a3.124890bf379ebd82.4ae46d92a926213d
+ 6c575b8f425edcd2.bf32e1036a2935ee.66183884203b3737.c58195b2ae31e6f7
+ 27e6ddf09bb8b79e
+VCMPSD_128_0x5(mem)
+ before
+ 4cdfc2388bc4515d.7804098b92d4eee3.c76789c85510737c.89d2d01267469cd4
+ 1037bf779a636f61.1b4de0316b49869d.40d64a4e11c51878.d5c454d6a84a2a04
+ 4fbc5097e6a0cfd6.b37fddef694ae0ae.064ba180bb51df0e.a738be3a80d31b74
+ e538f28588882be7.9be7fa30276237c0.f5920b496ec2856c.5b7c0cac8a6eacd0
+ 4dda389763a619c3
+ after
+ 4cdfc2388bc4515d.7804098b92d4eee3.c76789c85510737c.89d2d01267469cd4
+ 1037bf779a636f61.1b4de0316b49869d.40d64a4e11c51878.d5c454d6a84a2a04
+ 0000000000000000.0000000000000000.40d64a4e11c51878.0000000000000000
+ e538f28588882be7.9be7fa30276237c0.f5920b496ec2856c.5b7c0cac8a6eacd0
+ 4dda389763a619c3
+
+VCMPSD_128_0x6(reg)
+ before
+ d99f4067a6089dfa.ae781f2e9e2640c1.2ecf355f411dc87f.e97703974724c6bc
+ 5b162088f01e7520.8648557c4486c98f.ca8389ea5408cf98.bec5055561815e2a
+ 2f8dd266dc77dde2.49740f5d95b5837e.c951f33cfcae87b7.50498e6fd9e708e4
+ b14e546d079c10ec.d3c7c9bbadbe2ab9.89846dc1d49b2d87.7bd018d2ca618113
+ 1b24216851fc85e6
+ after
+ 0000000000000000.0000000000000000.ca8389ea5408cf98.0000000000000000
+ 5b162088f01e7520.8648557c4486c98f.ca8389ea5408cf98.bec5055561815e2a
+ 2f8dd266dc77dde2.49740f5d95b5837e.c951f33cfcae87b7.50498e6fd9e708e4
+ b14e546d079c10ec.d3c7c9bbadbe2ab9.89846dc1d49b2d87.7bd018d2ca618113
+ 1b24216851fc85e6
+VCMPSD_128_0x6(mem)
+ before
+ 0c12241e89c3d087.3da7a1090c1b4ce9.ff0f0084a9ad7a6e.6467f5e5785bfdb5
+ 29659ee18ec21d22.2fe2b5a6887fca86.ab162fa3a48f2ec6.b7478615857b33ed
+ 50eb099b7e0629e4.e34c8cb11654c96e.b2a9d104bb6f03f0.df701cbb96870ada
+ 5c6ee33a729ab0f9.b53123945227844e.f09465930959b516.362eb4454809bf28
+ 19cd481d378f8e85
+ after
+ 0c12241e89c3d087.3da7a1090c1b4ce9.ff0f0084a9ad7a6e.6467f5e5785bfdb5
+ 29659ee18ec21d22.2fe2b5a6887fca86.ab162fa3a48f2ec6.b7478615857b33ed
+ 0000000000000000.0000000000000000.ab162fa3a48f2ec6.0000000000000000
+ 5c6ee33a729ab0f9.b53123945227844e.f09465930959b516.362eb4454809bf28
+ 19cd481d378f8e85
+
+VCMPSD_128_0x6(reg)
+ before
+ e599d6b1fda5b29a.28bca7a9888b6d8c.00dc75bdd98336d1.40a3643cab5a0064
+ f4dd596b39d56916.929fd1d3dce31dca.229b7e9647f51ba5.80a24cecbc7d9f07
+ a3e6ceb984adeca3.75e4dea688b07cdf.76b83a8d37087173.8a5c978d59cf4f2b
+ 4e002f067cb97aed.ac56480dabfe46f6.5881a50d454872ea.3c9fc30d9d5accfb
+ 71354c56a52cd1a4
+ after
+ 0000000000000000.0000000000000000.229b7e9647f51ba5.ffffffffffffffff
+ f4dd596b39d56916.929fd1d3dce31dca.229b7e9647f51ba5.80a24cecbc7d9f07
+ a3e6ceb984adeca3.75e4dea688b07cdf.76b83a8d37087173.8a5c978d59cf4f2b
+ 4e002f067cb97aed.ac56480dabfe46f6.5881a50d454872ea.3c9fc30d9d5accfb
+ 71354c56a52cd1a4
+VCMPSD_128_0x6(mem)
+ before
+ 04ebac568c511b52.52777abebd844da2.15c38df55fd8363c.2340bc820e425bb4
+ d38d61f86fd46630.0997aa4de29aa26b.8af62848c04a09dc.35427a582d80687d
+ b8e7e62769c16e6a.d0acbb208887b5f7.e9ba95f3eb607b03.e8d2dbfb3f91d4f2
+ 90c4b7d19624ee2e.0301aaa14ad8c2f0.0cdc51e2fb2747dc.9a3edbd8dffedcbf
+ a6d07759aa55bc8f
+ after
+ 04ebac568c511b52.52777abebd844da2.15c38df55fd8363c.2340bc820e425bb4
+ d38d61f86fd46630.0997aa4de29aa26b.8af62848c04a09dc.35427a582d80687d
+ 0000000000000000.0000000000000000.8af62848c04a09dc.ffffffffffffffff
+ 90c4b7d19624ee2e.0301aaa14ad8c2f0.0cdc51e2fb2747dc.9a3edbd8dffedcbf
+ a6d07759aa55bc8f
+
+VCMPSD_128_0x6(reg)
+ before
+ 67d6a9eb3b21b00f.38f250e1130aa3a6.fee4713dc4180402.d128d7020daa2a94
+ 3b9a6ffb2feff3eb.8a3b2e44fc7e49fe.1d9f0e6193d3b8db.126aa33d3cf5e057
+ 7c69c5f3214ac2ce.646ccbe46c8d9b63.bc7f7c7753961924.ac6e3181a5152550
+ 878ea541aebe5964.a051a5ae7f415601.37d0b8ed9eec658c.7cfffdb96315b4ac
+ 5ceb84d193024a96
+ after
+ 0000000000000000.0000000000000000.1d9f0e6193d3b8db.ffffffffffffffff
+ 3b9a6ffb2feff3eb.8a3b2e44fc7e49fe.1d9f0e6193d3b8db.126aa33d3cf5e057
+ 7c69c5f3214ac2ce.646ccbe46c8d9b63.bc7f7c7753961924.ac6e3181a5152550
+ 878ea541aebe5964.a051a5ae7f415601.37d0b8ed9eec658c.7cfffdb96315b4ac
+ 5ceb84d193024a96
+VCMPSD_128_0x6(mem)
+ before
+ 29fc40b550e7a33c.b9570d5071d8f35b.1bb6388e52a93603.eadebc2e1362d6bd
+ bfffaf51b6d07ac7.6c0ff78c0723ce5c.b166fe7100cef796.30f486a64c82a963
+ fbc04d91e2ca8c65.fd0162610b2b2316.3f2f7542a6be54e5.676011c0e5db192c
+ b70b9461f0df9542.c97a473b197d3133.9fdb17ec5f840a1d.ea6c59eb7bf663c1
+ 15655a90a961c3d1
+ after
+ 29fc40b550e7a33c.b9570d5071d8f35b.1bb6388e52a93603.eadebc2e1362d6bd
+ bfffaf51b6d07ac7.6c0ff78c0723ce5c.b166fe7100cef796.30f486a64c82a963
+ 0000000000000000.0000000000000000.b166fe7100cef796.ffffffffffffffff
+ b70b9461f0df9542.c97a473b197d3133.9fdb17ec5f840a1d.ea6c59eb7bf663c1
+ 15655a90a961c3d1
+
+VCMPSD_128_0x7(reg)
+ before
+ 4497111c0ca77506.d0ab02adfb1e518a.2ac6a386cea43260.ae37625d482dd56a
+ d24e79fb3f55b50c.226e12621f907b68.7d3173aec62c6348.480fd2807cc471f7
+ 1dd58e9adff6be90.891e406a7943d008.1e07b2209ba20098.492fe141185599f1
+ 807a4c638716cc3e.e18808b325420c97.6a935c46ec9145fb.8d630d8c37ec0a83
+ f077d14df6967fda
+ after
+ 0000000000000000.0000000000000000.7d3173aec62c6348.ffffffffffffffff
+ d24e79fb3f55b50c.226e12621f907b68.7d3173aec62c6348.480fd2807cc471f7
+ 1dd58e9adff6be90.891e406a7943d008.1e07b2209ba20098.492fe141185599f1
+ 807a4c638716cc3e.e18808b325420c97.6a935c46ec9145fb.8d630d8c37ec0a83
+ f077d14df6967fda
+VCMPSD_128_0x7(mem)
+ before
+ 4e36a970705fb622.5687b0c4d3411dc1.0678e7283d9aeb41.bb236e8e53856d1e
+ 836d12e2c1516986.fd49b4276004ebc6.d4ba58b5e0562832.6e01e2626c0bb5ad
+ 6be8868d067a5533.cf0c56facaea73f9.271ad74528828095.df7ab630d4ae5853
+ e273835f5be63554.2a1c91a8ac80f105.db63e0c6312baf96.6adae56326fb94bd
+ 6b6d6b67ff7ca396
+ after
+ 4e36a970705fb622.5687b0c4d3411dc1.0678e7283d9aeb41.bb236e8e53856d1e
+ 836d12e2c1516986.fd49b4276004ebc6.d4ba58b5e0562832.6e01e2626c0bb5ad
+ 0000000000000000.0000000000000000.d4ba58b5e0562832.ffffffffffffffff
+ e273835f5be63554.2a1c91a8ac80f105.db63e0c6312baf96.6adae56326fb94bd
+ 6b6d6b67ff7ca396
+
+VCMPSD_128_0x7(reg)
+ before
+ 3e7e45a8fabfc28b.c4da8442db9fc616.68c5629da251a096.cc62ef24185c7062
+ 3f5b6d92b4502c48.ede90524a2b3c4a5.e752c34549e9be5a.d6e48149f8218025
+ ca4ee191c8ba1e78.386b83f0cd2deb2c.0111b20c3dd584fb.d4b31122ed879b0a
+ 3ba49c12d289d4c8.832e7892771af6d8.144c2a5f19a03125.a49c1b9b15997c3e
+ 216a1ba18963e1ed
+ after
+ 0000000000000000.0000000000000000.e752c34549e9be5a.ffffffffffffffff
+ 3f5b6d92b4502c48.ede90524a2b3c4a5.e752c34549e9be5a.d6e48149f8218025
+ ca4ee191c8ba1e78.386b83f0cd2deb2c.0111b20c3dd584fb.d4b31122ed879b0a
+ 3ba49c12d289d4c8.832e7892771af6d8.144c2a5f19a03125.a49c1b9b15997c3e
+ 216a1ba18963e1ed
+VCMPSD_128_0x7(mem)
+ before
+ 27eb8e1e67f28442.eea99b7f70498ae3.a9fc62f6bd85a2d4.7a5027a879d6ff85
+ 91e9ee00cb51216a.3ea9d8463b877b76.86a2bc08bb7bab4d.9069a654fa042bc7
+ 3d32b932d08c7690.89f051d1d1cee42c.f5ec03b48b06cd6e.b3e3a2d037b5f196
+ 06906ba092b03de1.2ac9018eceab01b3.d4a5b1e64c34c364.3d091687cd758d9f
+ 8b2901e457d13a8d
+ after
+ 27eb8e1e67f28442.eea99b7f70498ae3.a9fc62f6bd85a2d4.7a5027a879d6ff85
+ 91e9ee00cb51216a.3ea9d8463b877b76.86a2bc08bb7bab4d.9069a654fa042bc7
+ 0000000000000000.0000000000000000.86a2bc08bb7bab4d.ffffffffffffffff
+ 06906ba092b03de1.2ac9018eceab01b3.d4a5b1e64c34c364.3d091687cd758d9f
+ 8b2901e457d13a8d
+
+VCMPSD_128_0x7(reg)
+ before
+ f98d5c557254350d.c7d07e352ec83388.7d82e4e8cca90eb4.fd9b448b17114a5b
+ e4822445b98ab9cb.5ebd70dfc0e013b3.dd65f74a6a5446de.4e98378d0aa71e7e
+ a6545620c8000472.a525bb8a62059a8b.a8bf34224238e6db.a26906da4105fafa
+ 9c4fed523d4150af.7ad3dd203342843f.39dc99dbf0e22a57.d4da2e5cd7349bfb
+ c2b72a01e942bdac
+ after
+ 0000000000000000.0000000000000000.dd65f74a6a5446de.ffffffffffffffff
+ e4822445b98ab9cb.5ebd70dfc0e013b3.dd65f74a6a5446de.4e98378d0aa71e7e
+ a6545620c8000472.a525bb8a62059a8b.a8bf34224238e6db.a26906da4105fafa
+ 9c4fed523d4150af.7ad3dd203342843f.39dc99dbf0e22a57.d4da2e5cd7349bfb
+ c2b72a01e942bdac
+VCMPSD_128_0x7(mem)
+ before
+ 46cc75b4923a1c3a.22bfe547b1d9d92d.b792528e4da48df8.eb0821e211de4dff
+ 3ee58e61ee2873d0.94ef3b6cc255dd99.3a2f94c0cc3671e5.1c8ec9a140b68c7f
+ 84cdeef41a197f9b.4e2dea2b0c40969f.dd7621a3cd04eb30.26bc8b851af82382
+ f55112593218fcc6.acc3edf12a2741ea.7d3374226b1ab806.67dc65fb3a2f4eb5
+ 393b526d3de848c4
+ after
+ 46cc75b4923a1c3a.22bfe547b1d9d92d.b792528e4da48df8.eb0821e211de4dff
+ 3ee58e61ee2873d0.94ef3b6cc255dd99.3a2f94c0cc3671e5.1c8ec9a140b68c7f
+ 0000000000000000.0000000000000000.3a2f94c0cc3671e5.ffffffffffffffff
+ f55112593218fcc6.acc3edf12a2741ea.7d3374226b1ab806.67dc65fb3a2f4eb5
+ 393b526d3de848c4
+
+VCMPSD_128_0xA(reg)
+ before
+ fa254e49beae4e5a.6e3d777c5132a57e.0afe422bb8941a27.f7320928c3859392
+ 04e656f95a0d9c23.c95d984a937237ef.c42ae54453165c01.253e5ca3f0503a01
+ b5c964ebac926dcd.e37df1ad15e46e44.3692d0a796364425.e425ea7e0e88677e
+ 671c768a50c8fe01.9869ff93f29406aa.bc8401c21e820e3f.11b12ea53a37d636
+ 86afa404906c4555
+ after
+ 0000000000000000.0000000000000000.c42ae54453165c01.0000000000000000
+ 04e656f95a0d9c23.c95d984a937237ef.c42ae54453165c01.253e5ca3f0503a01
+ b5c964ebac926dcd.e37df1ad15e46e44.3692d0a796364425.e425ea7e0e88677e
+ 671c768a50c8fe01.9869ff93f29406aa.bc8401c21e820e3f.11b12ea53a37d636
+ 86afa404906c4555
+VCMPSD_128_0xA(mem)
+ before
+ 20ebc8872b306e06.77298742e43b8b6e.c5ec3ce6478fba4c.b24a73008685f5fa
+ bb31171a28910e76.423d937f017850be.44d426942fe04757.733222cd6bcc3703
+ 334c0baaa29ae1d0.22a497ad450a889e.f2eb3888c79469f7.5d860b9568e10e05
+ 640a2221b558a241.74aa8e394b7d70b9.abfeefae2ab6dc57.cb9328c51a53b6ad
+ 19a577c71cab6da7
+ after
+ 20ebc8872b306e06.77298742e43b8b6e.c5ec3ce6478fba4c.b24a73008685f5fa
+ bb31171a28910e76.423d937f017850be.44d426942fe04757.733222cd6bcc3703
+ 0000000000000000.0000000000000000.44d426942fe04757.0000000000000000
+ 640a2221b558a241.74aa8e394b7d70b9.abfeefae2ab6dc57.cb9328c51a53b6ad
+ 19a577c71cab6da7
+
+VCMPSD_128_0xA(reg)
+ before
+ a207f3080b776d9e.2b35d76d7ed60ef5.949b748db05e44bc.4bd9c5f175525ba4
+ c40798f58242f33e.629aa7781820e117.dec3451710383f52.ae483840c375a309
+ daef63f91e993a35.e6050c30a043d6d4.af6dfd4106979f28.b016c384312a6fb3
+ 3f0c4e7f7a07802d.93428480314aaa57.61e699792e089dea.2d11e2aada7d7dce
+ 0103119eda7a8785
+ after
+ 0000000000000000.0000000000000000.dec3451710383f52.0000000000000000
+ c40798f58242f33e.629aa7781820e117.dec3451710383f52.ae483840c375a309
+ daef63f91e993a35.e6050c30a043d6d4.af6dfd4106979f28.b016c384312a6fb3
+ 3f0c4e7f7a07802d.93428480314aaa57.61e699792e089dea.2d11e2aada7d7dce
+ 0103119eda7a8785
+VCMPSD_128_0xA(mem)
+ before
+ 08b9cd4d4e2e4a05.51aa57f53218ffd2.441d8a54e84119cd.517a142a25167843
+ 1eff91a152a58179.6a157ac6e358f3d1.d7619a98e034df62.db756abf864d6ae0
+ 1fa1d98801e9e90e.e899b15e29549ad6.27dc31383630b741.5b2397a6ee3ab16c
+ e76a21ed77083ef0.2581fa299f982e8c.1058c92005415e97.2dd0974af8688694
+ adc7671741642804
+ after
+ 08b9cd4d4e2e4a05.51aa57f53218ffd2.441d8a54e84119cd.517a142a25167843
+ 1eff91a152a58179.6a157ac6e358f3d1.d7619a98e034df62.db756abf864d6ae0
+ 0000000000000000.0000000000000000.d7619a98e034df62.ffffffffffffffff
+ e76a21ed77083ef0.2581fa299f982e8c.1058c92005415e97.2dd0974af8688694
+ adc7671741642804
+
+VCMPSD_128_0xA(reg)
+ before
+ 3755027a64b9d167.5128e6bbd10e3c4a.7f1b4f93e1aeeca0.6ea2e03c6a71908f
+ 26c764ddfdf3be6a.3ba5a2e02b059e49.50b1ae088c240fbd.1d86f17880ce0956
+ d86689ada99e2bb8.80aed3479ffb2118.f59013f53b86d591.f8cf78c164648418
+ a8816e57044753fe.fc0ff4dc4cfc81e4.cb0478c48b5e78c5.dd4bf201313dbe00
+ a7c4da260367733a
+ after
+ 0000000000000000.0000000000000000.50b1ae088c240fbd.0000000000000000
+ 26c764ddfdf3be6a.3ba5a2e02b059e49.50b1ae088c240fbd.1d86f17880ce0956
+ d86689ada99e2bb8.80aed3479ffb2118.f59013f53b86d591.f8cf78c164648418
+ a8816e57044753fe.fc0ff4dc4cfc81e4.cb0478c48b5e78c5.dd4bf201313dbe00
+ a7c4da260367733a
+VCMPSD_128_0xA(mem)
+ before
+ 3108ac1bf7ee5ef4.f2630e45a97973e7.8a94828c4b127ad9.2c59dbe3173a3407
+ 59e1e4cc29dd3c58.125865e534c1c721.0809f741bb4bc722.75da37bc7ca64703
+ fa1cfe25b440c992.63ab6fa242aa8a55.5139d1e8b5b325eb.03d588bd552ceb65
+ ef857712b423c1cf.43a928e86fc0fa32.40f28b6e58555062.3094ca513f5a5dd8
+ 5964fae4d5bcd908
+ after
+ 3108ac1bf7ee5ef4.f2630e45a97973e7.8a94828c4b127ad9.2c59dbe3173a3407
+ 59e1e4cc29dd3c58.125865e534c1c721.0809f741bb4bc722.75da37bc7ca64703
+ 0000000000000000.0000000000000000.0809f741bb4bc722.0000000000000000
+ ef857712b423c1cf.43a928e86fc0fa32.40f28b6e58555062.3094ca513f5a5dd8
+ 5964fae4d5bcd908
+
+VCMPSD_128_0xC(reg)
+ before
+ da9112e2b4dc9aa3.16e7ca7f4693df3b.0d9e8d23568f5162.b3fea1bdbd3d03b1
+ 0f6710b77748dd52.49107358859be001.1cd699bf93a4cb91.842a90c30277fb04
+ 5432f0cfbb8cdec4.66caee898e47804e.ce9d4828c38aa66c.9142d26b4310f488
+ 053dac961b33d8a3.47e2b8ff7da47a4e.7e3e96ca81ce1c9f.b412e5a19b13aa69
+ cb654451278cd8d2
+ after
+ 0000000000000000.0000000000000000.1cd699bf93a4cb91.ffffffffffffffff
+ 0f6710b77748dd52.49107358859be001.1cd699bf93a4cb91.842a90c30277fb04
+ 5432f0cfbb8cdec4.66caee898e47804e.ce9d4828c38aa66c.9142d26b4310f488
+ 053dac961b33d8a3.47e2b8ff7da47a4e.7e3e96ca81ce1c9f.b412e5a19b13aa69
+ cb654451278cd8d2
+VCMPSD_128_0xC(mem)
+ before
+ b0096c6702883bf0.7ed5427933c9089b.ca244ba46cbd8b2c.870780126afb6ad5
+ 40c8d7cf48128fee.1b47ace2a0daaa5a.c95c25667a9f6f14.4742016a199dcbbb
+ 586f037516378ff9.38dde93ffdf3fa89.2156c12fc055e234.183c153f2b417dfd
+ d2ca6b458702f83d.31e3f2fbe79f33d7.afdd9ced5ceb9fb5.5841b8fe3b72ba46
+ 619de612e6bcbe42
+ after
+ b0096c6702883bf0.7ed5427933c9089b.ca244ba46cbd8b2c.870780126afb6ad5
+ 40c8d7cf48128fee.1b47ace2a0daaa5a.c95c25667a9f6f14.4742016a199dcbbb
+ 0000000000000000.0000000000000000.c95c25667a9f6f14.ffffffffffffffff
+ d2ca6b458702f83d.31e3f2fbe79f33d7.afdd9ced5ceb9fb5.5841b8fe3b72ba46
+ 619de612e6bcbe42
+
+VCMPSD_128_0xC(reg)
+ before
+ 909c9ce7c7acc79f.8ba58b2cb87f86e5.62a7c481fa6a92ee.4dbf308b6a6d63c6
+ 4289d5e97acd0f06.5fcbe014c4baf51e.27745c3fd1e1537a.d8c6fbf505e8ea91
+ d1b18d849cabd326.2b0ae4ebc8c00014.dc95b5a0088fb228.2cbf78174a67ef43
+ 9a61c024c9d34ea9.c92c159be09c64f2.dd57cb103c01eaa4.267623dd54f72f07
+ a0b779333fa3660a
+ after
+ 0000000000000000.0000000000000000.27745c3fd1e1537a.ffffffffffffffff
+ 4289d5e97acd0f06.5fcbe014c4baf51e.27745c3fd1e1537a.d8c6fbf505e8ea91
+ d1b18d849cabd326.2b0ae4ebc8c00014.dc95b5a0088fb228.2cbf78174a67ef43
+ 9a61c024c9d34ea9.c92c159be09c64f2.dd57cb103c01eaa4.267623dd54f72f07
+ a0b779333fa3660a
+VCMPSD_128_0xC(mem)
+ before
+ 774df50628775077.fae36b359cd0be3c.16feee12265bdde4.85079bfb08c2389a
+ 870612402b7fa87b.4b848823b12e5d8a.ee4dec3bb9082717.32ef1fce095ed8b4
+ acac4fcf63c82b42.ea8f155aa57a6840.2de28902b2affdb7.3f5b55f3da6105a1
+ c20c259dec5e95f7.33520d47143f1a09.af8c43532f5d1cf0.089938d71758fc0b
+ e8f3c4e75ecff99f
+ after
+ 774df50628775077.fae36b359cd0be3c.16feee12265bdde4.85079bfb08c2389a
+ 870612402b7fa87b.4b848823b12e5d8a.ee4dec3bb9082717.32ef1fce095ed8b4
+ 0000000000000000.0000000000000000.ee4dec3bb9082717.ffffffffffffffff
+ c20c259dec5e95f7.33520d47143f1a09.af8c43532f5d1cf0.089938d71758fc0b
+ e8f3c4e75ecff99f
+
+VCMPSD_128_0xC(reg)
+ before
+ 3db7f68d48503808.a5f21298e34ba2c7.82176d549909b092.5016951a4c1d3fed
+ 612fc9377369f4f3.312a90ab639d0ddd.332b2fefd0656687.ec4bfb4424fb24da
+ b2a839507ba56a0c.42801dc2895f9366.a3db518356de7893.5ff8f1bbd40485e4
+ 8b6e4244fb91d6fe.b4bf35c9709ef08e.2c70ce7cc6002163.85e9f46c77431f37
+ 3aea7f4429c4adff
+ after
+ 0000000000000000.0000000000000000.332b2fefd0656687.ffffffffffffffff
+ 612fc9377369f4f3.312a90ab639d0ddd.332b2fefd0656687.ec4bfb4424fb24da
+ b2a839507ba56a0c.42801dc2895f9366.a3db518356de7893.5ff8f1bbd40485e4
+ 8b6e4244fb91d6fe.b4bf35c9709ef08e.2c70ce7cc6002163.85e9f46c77431f37
+ 3aea7f4429c4adff
+VCMPSD_128_0xC(mem)
+ before
+ 5ac70e2e0793ec67.47cce07f8fb87375.63b552ac3565df80.2b39a246bd589ea2
+ c14c1d152cbd989b.4410106dd4a67e1f.2b2cf257f3c01d68.fc81ca4dd6712bfd
+ 4a4428e7b54e6dc8.dc84cc7a66e833a5.e7f18fb6c7bc6674.fa9341fdaed80420
+ d37dac8fbe50261a.6c761212df09ceb6.75d0a8b5cc6475ce.83bd03c2e01864b6
+ f2490c0808bd886c
+ after
+ 5ac70e2e0793ec67.47cce07f8fb87375.63b552ac3565df80.2b39a246bd589ea2
+ c14c1d152cbd989b.4410106dd4a67e1f.2b2cf257f3c01d68.fc81ca4dd6712bfd
+ 0000000000000000.0000000000000000.2b2cf257f3c01d68.ffffffffffffffff
+ d37dac8fbe50261a.6c761212df09ceb6.75d0a8b5cc6475ce.83bd03c2e01864b6
+ f2490c0808bd886c
+
+VCMPSD_128_0xD(reg)
+ before
+ a384583cc353abed.37c124f962d180bc.5130dea2de958afc.b094b6411ec408a2
+ f2bae4c8ad670be6.52dd0c11bddd37db.e5ff2a94fd19a424.740b3644dbe9d91d
+ 3b36aa1a6184e202.ff9de1c3ec7f07a3.852ef456d82058d9.9cffa5ac1cdea46b
+ da46a89c7b376def.1ccc1dfc0ac3ab3f.8e0b37520c36e1c8.063e7e64ffb027b7
+ 8d923d58a0691c2e
+ after
+ 0000000000000000.0000000000000000.e5ff2a94fd19a424.ffffffffffffffff
+ f2bae4c8ad670be6.52dd0c11bddd37db.e5ff2a94fd19a424.740b3644dbe9d91d
+ 3b36aa1a6184e202.ff9de1c3ec7f07a3.852ef456d82058d9.9cffa5ac1cdea46b
+ da46a89c7b376def.1ccc1dfc0ac3ab3f.8e0b37520c36e1c8.063e7e64ffb027b7
+ 8d923d58a0691c2e
+VCMPSD_128_0xD(mem)
+ before
+ 0cc85f741a1740fc.2a34dabc980ae756.84383ea634b5e0dc.5ae0eff634e87c9c
+ 61ac5ea489c64e4c.894d3ae5548c8de6.12abbfae856262a5.46fb18adedc16502
+ 6609b8d40a80034b.52ddc6834a469b48.a4f21c0119d5ecc7.aea6afe3d24dd8a6
+ f9ade8f0b8541b24.e030790216c64d2b.14d9d28a0e1a3b6d.ee2eae047f191033
+ 63df137c91b04a56
+ after
+ 0cc85f741a1740fc.2a34dabc980ae756.84383ea634b5e0dc.5ae0eff634e87c9c
+ 61ac5ea489c64e4c.894d3ae5548c8de6.12abbfae856262a5.46fb18adedc16502
+ 0000000000000000.0000000000000000.12abbfae856262a5.0000000000000000
+ f9ade8f0b8541b24.e030790216c64d2b.14d9d28a0e1a3b6d.ee2eae047f191033
+ 63df137c91b04a56
+
+VCMPSD_128_0xD(reg)
+ before
+ 6704dab7a49ec2ba.f4626ae4b04b5204.91924fce5597df39.402c5b347d3e0bc4
+ 57ebfd215370b30c.35f5bb9d0d736416.bf4f4454a2468c1f.02b735ed844c18f8
+ 8fde7a273ab15bf8.96325605ecd70c87.c8b255fe9a5e9188.3846dba03f511d34
+ 6b2a4c33f6edf429.f5e5b70a68830783.06087c39d86b2921.bca4ca39c957d7a5
+ 6b9e7ca43e6d0277
+ after
+ 0000000000000000.0000000000000000.bf4f4454a2468c1f.0000000000000000
+ 57ebfd215370b30c.35f5bb9d0d736416.bf4f4454a2468c1f.02b735ed844c18f8
+ 8fde7a273ab15bf8.96325605ecd70c87.c8b255fe9a5e9188.3846dba03f511d34
+ 6b2a4c33f6edf429.f5e5b70a68830783.06087c39d86b2921.bca4ca39c957d7a5
+ 6b9e7ca43e6d0277
+VCMPSD_128_0xD(mem)
+ before
+ 22016fcebb9c59d5.471b6fb323b1ba4c.2cda5a969e841035.d79db772f9fa9195
+ bb971ea15bf299eb.7ffddf115c88eb0c.18dcbb97a9e5e5ca.95bd011398960592
+ 132c050a3b7a7ee7.6f1c99bb3dffc116.96b957f8a6b3406e.9eb4578a52cbc1c1
+ 068ea1f67741c4f2.72c4971c63a17816.803ba9a5b0f9dd4c.4cceb342c22601d0
+ fd5613a78432006b
+ after
+ 22016fcebb9c59d5.471b6fb323b1ba4c.2cda5a969e841035.d79db772f9fa9195
+ bb971ea15bf299eb.7ffddf115c88eb0c.18dcbb97a9e5e5ca.95bd011398960592
+ 0000000000000000.0000000000000000.18dcbb97a9e5e5ca.ffffffffffffffff
+ 068ea1f67741c4f2.72c4971c63a17816.803ba9a5b0f9dd4c.4cceb342c22601d0
+ fd5613a78432006b
+
+VCMPSD_128_0xD(reg)
+ before
+ 0b9a7225357bfb3e.71876c4f2951263b.e640d7a069fa4eb7.b32f2d8ae3c37a90
+ d3e4cd28718e2df4.2ee5e40370b961ec.26dd54b3ec967da6.0b615f935c1dd168
+ b1811e1cd3f6d439.1a7284fd65823131.8ee70bc18702428e.649dbbac37149ffd
+ 02bd636df73f2abb.11fbc82927ba5238.7aaaf636d7c9d91c.9aaebec28fb49f7e
+ 8a62e3bf80078f15
+ after
+ 0000000000000000.0000000000000000.26dd54b3ec967da6.0000000000000000
+ d3e4cd28718e2df4.2ee5e40370b961ec.26dd54b3ec967da6.0b615f935c1dd168
+ b1811e1cd3f6d439.1a7284fd65823131.8ee70bc18702428e.649dbbac37149ffd
+ 02bd636df73f2abb.11fbc82927ba5238.7aaaf636d7c9d91c.9aaebec28fb49f7e
+ 8a62e3bf80078f15
+VCMPSD_128_0xD(mem)
+ before
+ 0e83a691271b29ee.20e497887af66b24.ef4c2d73cf6c7f2a.4572137f77787dfb
+ 03de8322a0fb2a37.6841b6d7f8a6d520.90312ec77ca57536.4d8b5d06049a6bd9
+ 453ff76005b44d19.3621bcc80bdba25c.d07547114770ef86.ed40d13919bbdf5f
+ b0727d3675514fc3.e6d1a6c552220f84.8be6f43d4ed9ab46.80de69825368153c
+ 64b2234f4d2b4819
+ after
+ 0e83a691271b29ee.20e497887af66b24.ef4c2d73cf6c7f2a.4572137f77787dfb
+ 03de8322a0fb2a37.6841b6d7f8a6d520.90312ec77ca57536.4d8b5d06049a6bd9
+ 0000000000000000.0000000000000000.90312ec77ca57536.ffffffffffffffff
+ b0727d3675514fc3.e6d1a6c552220f84.8be6f43d4ed9ab46.80de69825368153c
+ 64b2234f4d2b4819
+
+VCMPSD_128_0xE(reg)
+ before
+ f306fa0ba393b5a5.204391900adeec5f.d49b6f3c67065843.9d4eb137aded63a4
+ 8b27ea22f229988a.707daf5ae068e019.5ccc1398e613b846.e27afbec7fb7d4c9
+ 8660ef00d67b2c75.7eee538014fae61e.dab08e456cd66c38.36364d46e043b9e4
+ 42ff0611ea14ae11.2560faeec1a0bb9a.aa92ddaf94dab0c6.754e2333ed9ecf1f
+ 7b8df99ec2d3d2a6
+ after
+ 0000000000000000.0000000000000000.5ccc1398e613b846.0000000000000000
+ 8b27ea22f229988a.707daf5ae068e019.5ccc1398e613b846.e27afbec7fb7d4c9
+ 8660ef00d67b2c75.7eee538014fae61e.dab08e456cd66c38.36364d46e043b9e4
+ 42ff0611ea14ae11.2560faeec1a0bb9a.aa92ddaf94dab0c6.754e2333ed9ecf1f
+ 7b8df99ec2d3d2a6
+VCMPSD_128_0xE(mem)
+ before
+ 24c14b737aee7ea6.194e2ac1ca815a0b.41a01f9003671bb9.28c0fa42faacbf9c
+ 4bb4969e31fc8e4b.699a577c134d6c0e.ae7a3e53f85ac2a5.b084e36a3cd6d765
+ ce33550b0408bfc1.8c2f89ae60041fc7.48b9d321b9856b8d.9e2b9394f3e731cd
+ 880a04a60e1ecd32.df59bcc44e33b0e2.ea2b5be864f5d39b.4e01072abd680c82
+ 1c52399a36e7a32e
+ after
+ 24c14b737aee7ea6.194e2ac1ca815a0b.41a01f9003671bb9.28c0fa42faacbf9c
+ 4bb4969e31fc8e4b.699a577c134d6c0e.ae7a3e53f85ac2a5.b084e36a3cd6d765
+ 0000000000000000.0000000000000000.ae7a3e53f85ac2a5.0000000000000000
+ 880a04a60e1ecd32.df59bcc44e33b0e2.ea2b5be864f5d39b.4e01072abd680c82
+ 1c52399a36e7a32e
+
+VCMPSD_128_0xE(reg)
+ before
+ 646a274ef9ef317d.54051f5b6c4b74cd.bf64ed2878655b0a.729a509215b5b6fc
+ 8194ccb4a20df21c.10f02316399a6fbc.869c17487b265bec.bbd4300de7d1cfdb
+ d11d2437cecb24b7.97968bc392177b2c.914c368ff203ed34.a0a37744f656db65
+ af522c4219b801fa.c4c5d34f92cf5448.3cc146697a874d8d.ffd49f235f4f96c6
+ b23326963ec8bc29
+ after
+ 0000000000000000.0000000000000000.869c17487b265bec.0000000000000000
+ 8194ccb4a20df21c.10f02316399a6fbc.869c17487b265bec.bbd4300de7d1cfdb
+ d11d2437cecb24b7.97968bc392177b2c.914c368ff203ed34.a0a37744f656db65
+ af522c4219b801fa.c4c5d34f92cf5448.3cc146697a874d8d.ffd49f235f4f96c6
+ b23326963ec8bc29
+VCMPSD_128_0xE(mem)
+ before
+ 978b8789adce08ba.767dde431e5dc68f.754777a556cdb53d.e4484442ae3eb7a3
+ 88aa3ee8cb6c37a7.84eb38a57948af25.84e9f4b0f91d5b36.e32b2b862bb56624
+ 635ac79fb2af051a.34e735d5c704f766.cf77c45e97cc0261.96b6f7a18c7797b9
+ 02689e9b7ea12d3f.e1bfd23da31edbff.30bd659a4de566e7.5937a4ff6d118611
+ 88f92e0c6b0d6fd6
+ after
+ 978b8789adce08ba.767dde431e5dc68f.754777a556cdb53d.e4484442ae3eb7a3
+ 88aa3ee8cb6c37a7.84eb38a57948af25.84e9f4b0f91d5b36.e32b2b862bb56624
+ 0000000000000000.0000000000000000.84e9f4b0f91d5b36.ffffffffffffffff
+ 02689e9b7ea12d3f.e1bfd23da31edbff.30bd659a4de566e7.5937a4ff6d118611
+ 88f92e0c6b0d6fd6
+
+VCMPSD_128_0xE(reg)
+ before
+ 7f47923522f98db4.43a040c64c516c43.e9bd094aaa21979b.85865250377542f7
+ 9a6ecbe42d611d59.00ce280e37c87e52.a62fd869779967e7.a8a0076c708753ba
+ 35bad58728d05a6e.16bed25d5c141f97.765f3a04a713868e.76d501da1427555f
+ ac77ac88b0d282a2.623bbba1d6400a3f.b39a2b89d51a313e.ccf2bb8640610310
+ 84c3b15c10421afa
+ after
+ 0000000000000000.0000000000000000.a62fd869779967e7.0000000000000000
+ 9a6ecbe42d611d59.00ce280e37c87e52.a62fd869779967e7.a8a0076c708753ba
+ 35bad58728d05a6e.16bed25d5c141f97.765f3a04a713868e.76d501da1427555f
+ ac77ac88b0d282a2.623bbba1d6400a3f.b39a2b89d51a313e.ccf2bb8640610310
+ 84c3b15c10421afa
+VCMPSD_128_0xE(mem)
+ before
+ 7b145f499fd55648.5bf14d5561f3cf9f.be135dc5c159fc75.bb2ca7629e3aa4a0
+ 8eb1413709277327.9e73b259d5c07e11.071036b53b69b166.e860abfd9dff1a62
+ 9765d4146b432cc2.d14bd900abc4caa5.1affc15d5d7fe43e.978432c56ef6d030
+ 73fd93cbe0353e46.4fc3bdb67d8cf007.d1ac7aa945a45228.25e23826aeab02b6
+ ecc7b98cf9a8ec9f
+ after
+ 7b145f499fd55648.5bf14d5561f3cf9f.be135dc5c159fc75.bb2ca7629e3aa4a0
+ 8eb1413709277327.9e73b259d5c07e11.071036b53b69b166.e860abfd9dff1a62
+ 0000000000000000.0000000000000000.071036b53b69b166.0000000000000000
+ 73fd93cbe0353e46.4fc3bdb67d8cf007.d1ac7aa945a45228.25e23826aeab02b6
+ ecc7b98cf9a8ec9f
+
+VCMPSD_128_0x11(reg)
+ before
+ 497fb263ea7bc997.fe46fa47850965df.76285be7e7a32ce2.09e3de860fe6b751
+ 98561e181db0d64c.140a857675cc5db8.a1c6aeff8595bae3.9e6f67ded650cfe4
+ 3698f8152fd24f68.9115b143cd89e1fe.2ce9b16bf5eed6b6.6c1e939eb6ef550e
+ 7d903fc8bc6d7097.5135f89aa84daedc.72dc6295d03bbb06.4fbaddb3ccce06fb
+ 2310c20733f99ed6
+ after
+ 0000000000000000.0000000000000000.a1c6aeff8595bae3.ffffffffffffffff
+ 98561e181db0d64c.140a857675cc5db8.a1c6aeff8595bae3.9e6f67ded650cfe4
+ 3698f8152fd24f68.9115b143cd89e1fe.2ce9b16bf5eed6b6.6c1e939eb6ef550e
+ 7d903fc8bc6d7097.5135f89aa84daedc.72dc6295d03bbb06.4fbaddb3ccce06fb
+ 2310c20733f99ed6
+VCMPSD_128_0x11(mem)
+ before
+ c4ecbc88087dd9cc.ca8cec9b5e0d7486.3035d86722237f7f.d1edbdeab407a580
+ 0e1a492166647208.79d6fdfcb43f98e1.0ae0cd9758171213.a466bcd73ddfd2cf
+ dd66e4be6abd26b7.e6bb6c56588e1753.bb035114663621c3.46945dc7064e7ca0
+ 0d9b094b3091b005.6d873714e6862f89.1f6ae2cc678b69bc.15c39b26ace0e09e
+ 6b3f725fca223a77
+ after
+ c4ecbc88087dd9cc.ca8cec9b5e0d7486.3035d86722237f7f.d1edbdeab407a580
+ 0e1a492166647208.79d6fdfcb43f98e1.0ae0cd9758171213.a466bcd73ddfd2cf
+ 0000000000000000.0000000000000000.0ae0cd9758171213.0000000000000000
+ 0d9b094b3091b005.6d873714e6862f89.1f6ae2cc678b69bc.15c39b26ace0e09e
+ 6b3f725fca223a77
+
+VCMPSD_128_0x11(reg)
+ before
+ a654dee0fc9fc5d4.7a8735b4d2eece1d.6a865aa4fbb41a2e.12e1faa97722a529
+ 204edc14dfe3bf64.00f4e2e56ee03a2c.3903cf7132a315ef.70341799b3089237
+ 377867680e7a61d0.7baf8eca2071b15d.364c94e727e05b78.152fb5863748ec11
+ 451f7b4626f1eac7.c684b45003afeedd.bdaba47378f52974.dd9d4e5e1eee6fe5
+ a34c600c8407d6dc
+ after
+ 0000000000000000.0000000000000000.3903cf7132a315ef.0000000000000000
+ 204edc14dfe3bf64.00f4e2e56ee03a2c.3903cf7132a315ef.70341799b3089237
+ 377867680e7a61d0.7baf8eca2071b15d.364c94e727e05b78.152fb5863748ec11
+ 451f7b4626f1eac7.c684b45003afeedd.bdaba47378f52974.dd9d4e5e1eee6fe5
+ a34c600c8407d6dc
+VCMPSD_128_0x11(mem)
+ before
+ 4506667c869ede25.a78f141bc3d494f3.bf3ed16134a6afd8.2a6dfb7fbe70bb8f
+ 9e98dc9a3fbf43ea.ba142e547fad9c01.41ab5febce60ae79.d9de957897dd4d77
+ 89ce3e52cc77c157.d8fac65bf90a3e9c.2795dcd8edeba7ed.264a6fcb9fc71ad6
+ e473099148d11399.5e8cd79eca77b671.4fcac316ae53585f.6cfd84e271ba5f58
+ 0942d02ba94258aa
+ after
+ 4506667c869ede25.a78f141bc3d494f3.bf3ed16134a6afd8.2a6dfb7fbe70bb8f
+ 9e98dc9a3fbf43ea.ba142e547fad9c01.41ab5febce60ae79.d9de957897dd4d77
+ 0000000000000000.0000000000000000.41ab5febce60ae79.ffffffffffffffff
+ e473099148d11399.5e8cd79eca77b671.4fcac316ae53585f.6cfd84e271ba5f58
+ 0942d02ba94258aa
+
+VCMPSD_128_0x11(reg)
+ before
+ 58674f11e4ec4178.8a55b841d0d9f6dc.a8185d88917e3f2b.941490902da37bfc
+ b5b6fd00be43556d.563ec7507f9c264b.13e85484e7ad1677.d140bf3285e7cdef
+ 7b7cd764d2d4d136.26fbb2a872255e13.f949b9006b907601.e41acde8d22b0965
+ 0805d8a9bc2af17f.d458f537c4815b60.b7878767b6b29d74.a76d359e317cec8a
+ f8077340bee53289
+ after
+ 0000000000000000.0000000000000000.13e85484e7ad1677.0000000000000000
+ b5b6fd00be43556d.563ec7507f9c264b.13e85484e7ad1677.d140bf3285e7cdef
+ 7b7cd764d2d4d136.26fbb2a872255e13.f949b9006b907601.e41acde8d22b0965
+ 0805d8a9bc2af17f.d458f537c4815b60.b7878767b6b29d74.a76d359e317cec8a
+ f8077340bee53289
+VCMPSD_128_0x11(mem)
+ before
+ b1b203ba9372978f.b69dfc3b19d1f0f3.3e210de891bad95d.a9eeba25669fc57d
+ b03b62f9cf30d7c8.e38f3f8684560b3f.3e2275a6f7de9436.2bca4ea717e32ac7
+ cf6e0ae78b2aad5f.ea299ef79a447e0e.b227a95f0ff94719.99663f57640b0aff
+ ec177972e66dd680.26b514f8f627850d.74fb25fef716af30.4f108aa2e9a29fd1
+ a9122af5433426e8
+ after
+ b1b203ba9372978f.b69dfc3b19d1f0f3.3e210de891bad95d.a9eeba25669fc57d
+ b03b62f9cf30d7c8.e38f3f8684560b3f.3e2275a6f7de9436.2bca4ea717e32ac7
+ 0000000000000000.0000000000000000.3e2275a6f7de9436.0000000000000000
+ ec177972e66dd680.26b514f8f627850d.74fb25fef716af30.4f108aa2e9a29fd1
+ a9122af5433426e8
+
+VCMPSD_128_0x12(reg)
+ before
+ 03b91bba0e4edbf1.e1022b85f9040d59.f5809cf6358c5be7.616b666fcb4188a7
+ b951595fe57bf997.8bfa9a0be2fb1014.b1d6355ef2fd3d49.5644e79fa5868dab
+ 2726e14f6448bd87.c7cd43f2bd5e99dd.b703d89bca0967df.2d502478a4f27b68
+ a983adf6283f636d.6f45a325a53a64e1.6452831958391454.c35b99e7e2900e09
+ f533c2d97b6d02bb
+ after
+ 0000000000000000.0000000000000000.b1d6355ef2fd3d49.0000000000000000
+ b951595fe57bf997.8bfa9a0be2fb1014.b1d6355ef2fd3d49.5644e79fa5868dab
+ 2726e14f6448bd87.c7cd43f2bd5e99dd.b703d89bca0967df.2d502478a4f27b68
+ a983adf6283f636d.6f45a325a53a64e1.6452831958391454.c35b99e7e2900e09
+ f533c2d97b6d02bb
+VCMPSD_128_0x12(mem)
+ before
+ 9da31c398c9412a9.9bb6bbc0ccef26f4.602f3590b79a2f4c.12113144381b8155
+ 987622f23011fb00.59090719ede144c9.7657761f0e8bb449.1e8ade88073bea8e
+ c27950f284f079ec.3ec98b6d26a3f797.8d89e0bfc618b005.e50a865161238baa
+ f7782224a33e4898.a842452814c07b0b.8290f15afc4ddeab.c1dd250be1619f55
+ 0f4fb8222381633d
+ after
+ 9da31c398c9412a9.9bb6bbc0ccef26f4.602f3590b79a2f4c.12113144381b8155
+ 987622f23011fb00.59090719ede144c9.7657761f0e8bb449.1e8ade88073bea8e
+ 0000000000000000.0000000000000000.7657761f0e8bb449.0000000000000000
+ f7782224a33e4898.a842452814c07b0b.8290f15afc4ddeab.c1dd250be1619f55
+ 0f4fb8222381633d
+
+VCMPSD_128_0x12(reg)
+ before
+ 2bac3a02c40d130b.133f1574aa072331.f2c02fb652c50ed0.2f3a24ddcc36fc68
+ 7240a7185f93ea6e.f29aa3ceb455c7e2.788e48847d3dea93.7151f53551e0c468
+ 3e56fcce919f2610.70544a1edd36efd8.95fa89fc30b44c00.24a2e04ca757f3d6
+ ec3b3392f6bc009e.693b855043b5593f.a74eef8c07b66fc3.24f96210eba544df
+ 4d22f56c38d874ae
+ after
+ 0000000000000000.0000000000000000.788e48847d3dea93.0000000000000000
+ 7240a7185f93ea6e.f29aa3ceb455c7e2.788e48847d3dea93.7151f53551e0c468
+ 3e56fcce919f2610.70544a1edd36efd8.95fa89fc30b44c00.24a2e04ca757f3d6
+ ec3b3392f6bc009e.693b855043b5593f.a74eef8c07b66fc3.24f96210eba544df
+ 4d22f56c38d874ae
+VCMPSD_128_0x12(mem)
+ before
+ 7be9174cabfb3f70.d83b4acf2876b7c3.b919d151ffdfbf42.08d7779fa0d09186
+ 8a19449c5f1b6151.5ea23cf1c659852c.3cbba80b2fbfde0e.16e11ca0948decf8
+ 5580f6487143957c.dabc056469f2a784.ceed886cef6171ce.2bb8dafd817abcc3
+ bae8ab3cfc7f981e.a8d5a294b0cc5978.4b7bec5e5ad235af.a5a8ad2103223f94
+ defc9278b411af16
+ after
+ 7be9174cabfb3f70.d83b4acf2876b7c3.b919d151ffdfbf42.08d7779fa0d09186
+ 8a19449c5f1b6151.5ea23cf1c659852c.3cbba80b2fbfde0e.16e11ca0948decf8
+ 0000000000000000.0000000000000000.3cbba80b2fbfde0e.0000000000000000
+ bae8ab3cfc7f981e.a8d5a294b0cc5978.4b7bec5e5ad235af.a5a8ad2103223f94
+ defc9278b411af16
+
+VCMPSD_128_0x12(reg)
+ before
+ 3402846e33d449f6.941ede641ddc2662.24380ded3473d7b3.8f3051cf8c1de6dd
+ 01047f701af648df.bfee0badef65fb75.aa3244db93745ce3.76da31aaa24e4083
+ a34f7fe80503ea7e.1723ae018f26d282.961043ca695a25b1.db430adbb772fece
+ 742f80449188697f.778b434e182c68b7.441c042751b26ecc.9c38574ee894dde9
+ 948594ef50c09901
+ after
+ 0000000000000000.0000000000000000.aa3244db93745ce3.0000000000000000
+ 01047f701af648df.bfee0badef65fb75.aa3244db93745ce3.76da31aaa24e4083
+ a34f7fe80503ea7e.1723ae018f26d282.961043ca695a25b1.db430adbb772fece
+ 742f80449188697f.778b434e182c68b7.441c042751b26ecc.9c38574ee894dde9
+ 948594ef50c09901
+VCMPSD_128_0x12(mem)
+ before
+ 9ff63daa0c03ee41.d1f07fee5910018d.bdf0477ea682793d.0fa2845ce80772de
+ 9857cf6b376897d6.17dd7754fa27f055.c420357f5634c043.55f0c0d7c9e56e93
+ 5d73c51feefb51ec.a04464e00f5a7083.67e5893c444ffaf3.7151b30290d89e98
+ c8189bb04cc9d8af.c96f43003534bec2.840cc0a18bdee379.bf10594bda6d3d99
+ 9a7aaf1d432f8941
+ after
+ 9ff63daa0c03ee41.d1f07fee5910018d.bdf0477ea682793d.0fa2845ce80772de
+ 9857cf6b376897d6.17dd7754fa27f055.c420357f5634c043.55f0c0d7c9e56e93
+ 0000000000000000.0000000000000000.c420357f5634c043.0000000000000000
+ c8189bb04cc9d8af.c96f43003534bec2.840cc0a18bdee379.bf10594bda6d3d99
+ 9a7aaf1d432f8941
+
+VCMPSD_128_0x16(reg)
+ before
+ 60dbb0e465abbc3d.b710cd0c6edde749.eeab0e1f074115be.f561549a47ee3702
+ 6c7f570cdf6c1239.0428d71d6f443be9.6b44c3a9220eb324.98afc3139589b1ba
+ 19b2a3014bfec9e0.8d2c36d16c0890b9.9c865d0a2126d2a0.48c488f890be0ecc
+ c5bf8d3045ee1bdf.2ce865138038a2e6.debdd8afa015afde.e06a203655960a65
+ 3d6e05b7ff1f60b0
+ after
+ 0000000000000000.0000000000000000.6b44c3a9220eb324.0000000000000000
+ 6c7f570cdf6c1239.0428d71d6f443be9.6b44c3a9220eb324.98afc3139589b1ba
+ 19b2a3014bfec9e0.8d2c36d16c0890b9.9c865d0a2126d2a0.48c488f890be0ecc
+ c5bf8d3045ee1bdf.2ce865138038a2e6.debdd8afa015afde.e06a203655960a65
+ 3d6e05b7ff1f60b0
+VCMPSD_128_0x16(mem)
+ before
+ 3c9cb568ab64cddb.caf412036ac745e1.bf27e0cfc7dd2c9b.8b3430023c688589
+ b7c0ab3674710d0f.869b2fe755158293.20b723f15e05eb05.0038627091aa914d
+ 8ca6630c7753dc7a.5301df49a36410a0.2d62ab6561bb9b4f.991669663a680fd7
+ 951959d5cf15f548.8f721e93ef4129b5.c0f5f317eb0bf7a6.b218414ed32c3bd3
+ a78be696f98550ed
+ after
+ 3c9cb568ab64cddb.caf412036ac745e1.bf27e0cfc7dd2c9b.8b3430023c688589
+ b7c0ab3674710d0f.869b2fe755158293.20b723f15e05eb05.0038627091aa914d
+ 0000000000000000.0000000000000000.20b723f15e05eb05.ffffffffffffffff
+ 951959d5cf15f548.8f721e93ef4129b5.c0f5f317eb0bf7a6.b218414ed32c3bd3
+ a78be696f98550ed
+
+VCMPSD_128_0x16(reg)
+ before
+ d3ba55a947fc8bd0.afe70a7f99c415a5.943ae933d538097e.b63c77f41802bc36
+ 94f389f35a1f2828.b6daf1f5f06bf8bc.c0a53a94f3d3eea6.eb03b3e605aba62a
+ 45807edfce7963a2.87bf8a23f01659b9.6dfe0f22e2a012da.3c1623dbcd1371af
+ 42af30dc3d9777ea.fc6251f5b6d1f5ca.f8936349402bb2c6.834044bd8d45d8f0
+ 9d4e917a604d981a
+ after
+ 0000000000000000.0000000000000000.c0a53a94f3d3eea6.0000000000000000
+ 94f389f35a1f2828.b6daf1f5f06bf8bc.c0a53a94f3d3eea6.eb03b3e605aba62a
+ 45807edfce7963a2.87bf8a23f01659b9.6dfe0f22e2a012da.3c1623dbcd1371af
+ 42af30dc3d9777ea.fc6251f5b6d1f5ca.f8936349402bb2c6.834044bd8d45d8f0
+ 9d4e917a604d981a
+VCMPSD_128_0x16(mem)
+ before
+ 660d86fd63386d59.e7ca9b534603a1ab.f28fc2585ea98818.beae3375a9fe0915
+ ba479f31b11113d8.8f1ebcb1824c1d92.45115a3603aaced2.199c7912b8a75573
+ 75c8580467e445c4.98f68e6290fb264b.d1b6947cc1de8222.66a9338c09b2d08e
+ 735e2e61a0bdc049.5da00dd3099ef981.7248ec17b5536134.01205c5039a9b70f
+ 464ff0c8e31a45a5
+ after
+ 660d86fd63386d59.e7ca9b534603a1ab.f28fc2585ea98818.beae3375a9fe0915
+ ba479f31b11113d8.8f1ebcb1824c1d92.45115a3603aaced2.199c7912b8a75573
+ 0000000000000000.0000000000000000.45115a3603aaced2.ffffffffffffffff
+ 735e2e61a0bdc049.5da00dd3099ef981.7248ec17b5536134.01205c5039a9b70f
+ 464ff0c8e31a45a5
+
+VCMPSD_128_0x16(reg)
+ before
+ 9280eb62a491b7fa.90d49c3579a93f91.3966356e8bc0d2e1.0494def2fb142736
+ 3f014a88189849ba.a8f51e6a0db480cb.8a9602a1b2eeec16.6366e7f8ae2e9051
+ aa1c08a8d9be3793.978e31ed78e83d21.ab7a71d619b385cd.6b8a8217eaac57b4
+ 2f1e212d868cbc2e.396c4fabd75333c0.f75f7d7b5c9bd7b1.f8cc2b3acc9a3989
+ e6f75e4d6f05f1fc
+ after
+ 0000000000000000.0000000000000000.8a9602a1b2eeec16.0000000000000000
+ 3f014a88189849ba.a8f51e6a0db480cb.8a9602a1b2eeec16.6366e7f8ae2e9051
+ aa1c08a8d9be3793.978e31ed78e83d21.ab7a71d619b385cd.6b8a8217eaac57b4
+ 2f1e212d868cbc2e.396c4fabd75333c0.f75f7d7b5c9bd7b1.f8cc2b3acc9a3989
+ e6f75e4d6f05f1fc
+VCMPSD_128_0x16(mem)
+ before
+ 11d9973cf0f83d3b.2a529183b890153a.6a58f68e46001dd3.cc9122fb18321e6f
+ 553c53f36a7fd76f.f70654160e557e61.0621a184e0fcb887.845c5dc2e90598b3
+ 8eed0d5ef9a77cc7.f28467522167334f.e992cc78c152c008.7d0b283c6aa07f28
+ 97b8416abb7be76d.771ac5a38f536fb2.ef76f455060ef181.11eb81d5378d107b
+ 9e4963faed5a8658
+ after
+ 11d9973cf0f83d3b.2a529183b890153a.6a58f68e46001dd3.cc9122fb18321e6f
+ 553c53f36a7fd76f.f70654160e557e61.0621a184e0fcb887.845c5dc2e90598b3
+ 0000000000000000.0000000000000000.0621a184e0fcb887.ffffffffffffffff
+ 97b8416abb7be76d.771ac5a38f536fb2.ef76f455060ef181.11eb81d5378d107b
+ 9e4963faed5a8658
+
+VCMPSD_128_0x1E(reg)
+ before
+ 7e6fca1527931f6a.4e696b01c907d68d.e2126a76f4a46f33.f39b9409ca3d061f
+ 0eaab39382c2155d.8ecb081141580354.8eb95235ebe76e81.d3cb287f2aeabc0d
+ ab4518e19a75a5df.33ac93843f792aee.d95b7a4e11a7aa46.6ad32ca34221cf78
+ af8ef76a09380a9a.18d68848de760986.1e43dd2b01705d2e.947f1c622ceffb8c
+ 2c9a75a6075ffb74
+ after
+ 0000000000000000.0000000000000000.8eb95235ebe76e81.0000000000000000
+ 0eaab39382c2155d.8ecb081141580354.8eb95235ebe76e81.d3cb287f2aeabc0d
+ ab4518e19a75a5df.33ac93843f792aee.d95b7a4e11a7aa46.6ad32ca34221cf78
+ af8ef76a09380a9a.18d68848de760986.1e43dd2b01705d2e.947f1c622ceffb8c
+ 2c9a75a6075ffb74
+VCMPSD_128_0x1E(mem)
+ before
+ 10f2b15cec7e8c5c.77cf4b996e95813a.1b1663483a5c5a49.b9bf773a57cec4e6
+ 1a514e71fa566a72.5f5611dc621a466c.1638a0707036da63.051944e6b04e1a1a
+ 2884c8cf4af550e0.c46d439e835395dc.e708bcac9c1044ff.609e409aa77b9c75
+ 14589964fa67fbd2.0061df4b6dcaa935.695132e8d9f7554a.259b68c4d9e286a4
+ af59b7cfe20e1453
+ after
+ 10f2b15cec7e8c5c.77cf4b996e95813a.1b1663483a5c5a49.b9bf773a57cec4e6
+ 1a514e71fa566a72.5f5611dc621a466c.1638a0707036da63.051944e6b04e1a1a
+ 0000000000000000.0000000000000000.1638a0707036da63.ffffffffffffffff
+ 14589964fa67fbd2.0061df4b6dcaa935.695132e8d9f7554a.259b68c4d9e286a4
+ af59b7cfe20e1453
+
+VCMPSD_128_0x1E(reg)
+ before
+ 5c2729285d8b822d.bc963f1b26b72775.707ee04fbb0dbf24.77e17e1043f6c96f
+ 8750ba39e6e60bdf.fa0d35e0e9f190f5.700f42160aa81354.ef821c11f71a5c9b
+ 8b1f676f1aa9ec14.ac88f79e5f21f17d.5c62020df526e072.ab0188d5106dcaf9
+ c6e12b3794636079.acd20144a554073a.90c11a9e1813642a.882a3f49abfeceb6
+ 63c9bc5ae3d625fe
+ after
+ 0000000000000000.0000000000000000.700f42160aa81354.0000000000000000
+ 8750ba39e6e60bdf.fa0d35e0e9f190f5.700f42160aa81354.ef821c11f71a5c9b
+ 8b1f676f1aa9ec14.ac88f79e5f21f17d.5c62020df526e072.ab0188d5106dcaf9
+ c6e12b3794636079.acd20144a554073a.90c11a9e1813642a.882a3f49abfeceb6
+ 63c9bc5ae3d625fe
+VCMPSD_128_0x1E(mem)
+ before
+ 16aa7bf3d5038afc.92e302fbf19da4b9.d8b9d0bbd7958e57.6879883710fbd927
+ 7e98f9009c90bbdd.4d6fe829cce5f481.0a07def010f14102.40d64742796b7b16
+ 7861b06c548972cc.51d1d92bc1c78c7d.1f89a9cf6c72dd64.7424532dedee88a2
+ decf1e251bfb6bf7.fb57d26f6dcda858.f30aad4508271eab.60afa9630b103a78
+ 60c3444f6d5ecd44
+ after
+ 16aa7bf3d5038afc.92e302fbf19da4b9.d8b9d0bbd7958e57.6879883710fbd927
+ 7e98f9009c90bbdd.4d6fe829cce5f481.0a07def010f14102.40d64742796b7b16
+ 0000000000000000.0000000000000000.0a07def010f14102.0000000000000000
+ decf1e251bfb6bf7.fb57d26f6dcda858.f30aad4508271eab.60afa9630b103a78
+ 60c3444f6d5ecd44
+
+VCMPSD_128_0x1E(reg)
+ before
+ cfab205faf637fb1.8dafbe160af26487.a84bce606c8583bf.6358643cff19c003
+ 0bb439fe6eac8a6b.61cd0c2c3f7817aa.b2fbc96a597a5a5e.493e4ca26e567e98
+ 6f2a8b9845c42b20.37f58551d69b418c.76b1bff9d13968e0.8287df6170e91595
+ 5759139ad1379e7a.e9f2a372ea669d59.51baad796f4debf1.ea009c6722df4126
+ 5d75fc9f9f43be79
+ after
+ 0000000000000000.0000000000000000.b2fbc96a597a5a5e.ffffffffffffffff
+ 0bb439fe6eac8a6b.61cd0c2c3f7817aa.b2fbc96a597a5a5e.493e4ca26e567e98
+ 6f2a8b9845c42b20.37f58551d69b418c.76b1bff9d13968e0.8287df6170e91595
+ 5759139ad1379e7a.e9f2a372ea669d59.51baad796f4debf1.ea009c6722df4126
+ 5d75fc9f9f43be79
+VCMPSD_128_0x1E(mem)
+ before
+ b7b27cf5042147b7.1e8dcc6ead911e25.5492e47c97e6e93c.9d628d57cf431d3f
+ d48399556c85990f.2212b281765fe8ce.549fc359fa26df61.b7f55dfd8ea53a73
+ 90b3ceabf47c6fab.be33c140c72d3821.c5e6bdf72e323cf5.fbbe18d94701803c
+ c71097e3b71287b7.4d3ef5163c854ac9.83334c405016bb24.c50bbb5597e32944
+ 712640df1ad57237
+ after
+ b7b27cf5042147b7.1e8dcc6ead911e25.5492e47c97e6e93c.9d628d57cf431d3f
+ d48399556c85990f.2212b281765fe8ce.549fc359fa26df61.b7f55dfd8ea53a73
+ 0000000000000000.0000000000000000.549fc359fa26df61.0000000000000000
+ c71097e3b71287b7.4d3ef5163c854ac9.83334c405016bb24.c50bbb5597e32944
+ 712640df1ad57237
+
+VPSHUFB_128(reg)
+ before
+ 5c5ca5e26a6597c3.556471ead1519b60.2d7d4b6e72f55973.6a52ee227cdf191a
+ e0f9e5c9261fd391.167cd6aa604768d2.b93dbeb60508a2cb.560f1e88cc991202
+ 5a49fd02e78e6350.e62444117d00a939.4cca4a59904b617c.2335585e5f4e6208
+ 2697e7f84c3e83aa.a128360946861bc0.446fecc3af49d133.ad9219904e0cc459
+ cff0db0ab7dff521
+ after
+ 0000000000000000.0000000000000000.b60008a2000512b6.cc1ecb3db93d99cb
+ e0f9e5c9261fd391.167cd6aa604768d2.b93dbeb60508a2cb.560f1e88cc991202
+ 5a49fd02e78e6350.e62444117d00a939.4cca4a59904b617c.2335585e5f4e6208
+ 2697e7f84c3e83aa.a128360946861bc0.446fecc3af49d133.ad9219904e0cc459
+ cff0db0ab7dff521
+VPSHUFB_128(mem)
+ before
+ 671c1cb9b6d1b18b.a031a117eebb6e4b.23532880d6e77a93.fb7a9e60ff8e2f9b
+ 50e2578766f0b4c4.236126cc6b9261e1.487397614a2f82df.ce355e9c1ca7b761
+ 660e0961e448b9f8.0d7472815f4e9815.ec52fe98be68eed0.1aed27e3a11fa530
+ 846bac344be37d52.b9b681a3657c4f96.eabdd8114ca07b91.39eff5a22a8234b5
+ 8984c543545da19c
+ after
+ 671c1cb9b6d1b18b.a031a117eebb6e4b.23532880d6e77a93.fb7a9e60ff8e2f9b
+ 50e2578766f0b4c4.236126cc6b9261e1.487397614a2f82df.ce355e9c1ca7b761
+ 0000000000000000.0000000000000000.1c1cdf0000002f00.002f006100004800
+ 846bac344be37d52.b9b681a3657c4f96.eabdd8114ca07b91.39eff5a22a8234b5
+ 8984c543545da19c
+
+VPSHUFB_128(reg)
+ before
+ 64fb9134ba3b2890.88c7beebb7cfbcff.8373509f1aa6c10e.2080a4b813e3e54f
+ 279f57dff9a8043e.4decba714518312a.c7f7d9df195b2c29.6967db792d3be836
+ 2ebb12b2ac317251.aea71cb411c89900.e18d1ad1fe24c994.a03efa40b6b63f71
+ d69dbf187061ae77.89c4619f36eeb0ac.2c830fe0668fd7fb.a3d07efacb60a72d
+ 4cebe2918743dc95
+ after
+ 0000000000000000.0000000000000000.00005b0000790000.00f700360000c7e8
+ 279f57dff9a8043e.4decba714518312a.c7f7d9df195b2c29.6967db792d3be836
+ 2ebb12b2ac317251.aea71cb411c89900.e18d1ad1fe24c994.a03efa40b6b63f71
+ d69dbf187061ae77.89c4619f36eeb0ac.2c830fe0668fd7fb.a3d07efacb60a72d
+ 4cebe2918743dc95
+VPSHUFB_128(mem)
+ before
+ 7959a3f3066e99d6.798f587de0c4f459.b90f031ed093325c.0623b278ec279009
+ 05e73b0b65ea9b1b.74dedb4d98e77fa5.1953801dfcc5da39.caba01052d79316b
+ cb6128c4c0c59e91.23d543f436558c07.875e5388d68f6572.d394f7f3c510f6cd
+ a893e50c320a5e64.e2c28cde539a572b.ddfaf84c78fd8f30.7ffc90ae4e781ada
+ 2840c8a2673dda3f
+ after
+ 7959a3f3066e99d6.798f587de0c4f459.b90f031ed093325c.0623b278ec279009
+ 05e73b0b65ea9b1b.74dedb4d98e77fa5.1953801dfcc5da39.caba01052d79316b
+ 0000000000000000.0000000000000000.00192d530000791d.ba2d003900ca00da
+ a893e50c320a5e64.e2c28cde539a572b.ddfaf84c78fd8f30.7ffc90ae4e781ada
+ 2840c8a2673dda3f
+
+VPSHUFB_128(reg)
+ before
+ 2caa9c3caaec72a7.7948eeced8c596bf.0df0b3778d431cbc.f9f4ec53011c13a2
+ e58806e6b3111ebf.184ebff6cd0303cf.00aab22c80db1666.b518aa8b8af7aef2
+ b124040d1e361932.636fd5702dcf61c0.173d8767c7ee82d6.ee32adde329b1c4d
+ eacb921e89e9a0ad.3478aa2815366bbd.aef52d96fe099bb8.810e743a121219de
+ 4877788a486b60d2
+ after
+ 0000000000000000.0000000000000000.b5b200b500000000.00f70000f7002cb2
+ e58806e6b3111ebf.184ebff6cd0303cf.00aab22c80db1666.b518aa8b8af7aef2
+ b124040d1e361932.636fd5702dcf61c0.173d8767c7ee82d6.ee32adde329b1c4d
+ eacb921e89e9a0ad.3478aa2815366bbd.aef52d96fe099bb8.810e743a121219de
+ 4877788a486b60d2
+VPSHUFB_128(mem)
+ before
+ 203b37b9f0afae54.eec9aa848db5efdc.6835bc0ba043def2.211ea124c2b79fb8
+ e6242bb525ecbf91.17694aabc827416a.dc728603eb02768d.cc04dd7cae85c880
+ 74ffd269042d4eb5.c3f96cffd6cad304.6afb85fe127fefb7.0bf2df0c5ffe53bf
+ a798a8c2a87f18eb.4cc30eec522ae156.ef9b33e62fc7049f.3a36a23f70ae7b1f
+ b51a22817e217d4d
+ after
+ 203b37b9f0afae54.eec9aa848db5efdc.6835bc0ba043def2.211ea124c2b79fb8
+ e6242bb525ecbf91.17694aabc827416a.dc728603eb02768d.cc04dd7cae85c880
+ 0000000000000000.0000000000000000.8ddd00eb00ae0000.c872007c00000000
+ a798a8c2a87f18eb.4cc30eec522ae156.ef9b33e62fc7049f.3a36a23f70ae7b1f
+ b51a22817e217d4d
+
+VCVTTSD2SI_32(reg)
+ before
+ d7eb5b3e24e495f4.5bbb27aa2dedd960.0f142cded9d4a70b.471f0ea961e5726f
+ fef54ae3ff82ffc1.6c33cd0eb0834d3f.6838c041065360cf.4e549132c1e6f554
+ 8584eadaaa88f660.b6ce15db4d4d2fb5.b47bc88175334950.e004396d6ed54979
+ c7e43790c281b87c.15567bfb1f583cee.4d293f0ac3019e37.d9fc804681be290b
+ 1607e4a918ae5235
+ after
+ d7eb5b3e24e495f4.5bbb27aa2dedd960.0f142cded9d4a70b.471f0ea961e5726f
+ fef54ae3ff82ffc1.6c33cd0eb0834d3f.6838c041065360cf.4e549132c1e6f554
+ 8584eadaaa88f660.b6ce15db4d4d2fb5.b47bc88175334950.e004396d6ed54979
+ c7e43790c281b87c.15567bfb1f583cee.4d293f0ac3019e37.d9fc804681be290b
+ 0000000080000000
+VCVTTSD2SI_32(mem)
+ before
+ 71f3e0824fb07f24.22602d72e2f97ec2.65987b5c42b03015.908d21498b489b33
+ c78af0bd41d06e04.f145c9eaa77d87dd.826092e8d35fc757.d9f56aa86a957bee
+ f39990460b1ad900.8fe00566ac970d7a.487a3a8ded73bcdf.84ab1795fb727b14
+ d3ed3d0ac89b7d44.5a7bdf518dd64d44.93b2f136adf7ccda.edfc237bdb6dd653
+ 70348ac6a612ca54
+ after
+ 71f3e0824fb07f24.22602d72e2f97ec2.65987b5c42b03015.908d21498b489b33
+ c78af0bd41d06e04.f145c9eaa77d87dd.826092e8d35fc757.d9f56aa86a957bee
+ f39990460b1ad900.8fe00566ac970d7a.487a3a8ded73bcdf.84ab1795fb727b14
+ d3ed3d0ac89b7d44.5a7bdf518dd64d44.93b2f136adf7ccda.edfc237bdb6dd653
+ 0000000000000000
+
+VCVTTSD2SI_32(reg)
+ before
+ 699f48e2f6ec91c6.425072f3945f15fe.ac625217e7c383e8.3fd333cf2ef8b274
+ 34885a3b69876753.1c8eabef8c705e58.e3e35b2456ecea12.28ab7a448d812cd8
+ 2d3dba3d9b6f8aa7.3d7564e9ccdc147e.5949f4e475dcc06d.2a044481e59ef433
+ b008665427313470.81cf1acd6eaff39d.6cdf1bc3e0203ea6.21ab0c73535cc7b0
+ e96c4e04f2c6607c
+ after
+ 699f48e2f6ec91c6.425072f3945f15fe.ac625217e7c383e8.3fd333cf2ef8b274
+ 34885a3b69876753.1c8eabef8c705e58.e3e35b2456ecea12.28ab7a448d812cd8
+ 2d3dba3d9b6f8aa7.3d7564e9ccdc147e.5949f4e475dcc06d.2a044481e59ef433
+ b008665427313470.81cf1acd6eaff39d.6cdf1bc3e0203ea6.21ab0c73535cc7b0
+ 0000000000000000
+VCVTTSD2SI_32(mem)
+ before
+ 5d138621dfe87dc3.193659ecaa58a257.c46a478691f3b6e1.76f2cb2d3443a369
+ 5b6b31b735cfd7b0.c4139072bf71100b.e11069024fb61a76.d5ce008f0cd12961
+ be42c9b110862d6f.0deb05500206b936.b68efb2dc404db86.e3bfb75305570d3a
+ 6162ccfa8d193a2e.500ab6f411a6da84.1eb07af10de7b540.fd11ebe7ba608ba2
+ 7f1097b5c878df43
+ after
+ 5d138621dfe87dc3.193659ecaa58a257.c46a478691f3b6e1.76f2cb2d3443a369
+ 5b6b31b735cfd7b0.c4139072bf71100b.e11069024fb61a76.d5ce008f0cd12961
+ be42c9b110862d6f.0deb05500206b936.b68efb2dc404db86.e3bfb75305570d3a
+ 6162ccfa8d193a2e.500ab6f411a6da84.1eb07af10de7b540.fd11ebe7ba608ba2
+ 0000000080000000
+
+VCVTTSD2SI_32(reg)
+ before
+ c607ba2bca2c44c9.2298b580c895b917.e8bb9ec885daafa2.f441603b456d63ce
+ 2c434db45d07f7e1.dcb0012edc056756.334cb93afc30743c.160f2bf789a2a25d
+ 0e104dbc1c953337.6a762bf0e576ff18.8c0704b5113364fd.5fe45612f4912e18
+ c8bab7afa4633676.aab5aeb200f23e89.4e3979a56170bc92.aa8e5d76a346c22c
+ d5d7bd11b1cd1bc5
+ after
+ c607ba2bca2c44c9.2298b580c895b917.e8bb9ec885daafa2.f441603b456d63ce
+ 2c434db45d07f7e1.dcb0012edc056756.334cb93afc30743c.160f2bf789a2a25d
+ 0e104dbc1c953337.6a762bf0e576ff18.8c0704b5113364fd.5fe45612f4912e18
+ c8bab7afa4633676.aab5aeb200f23e89.4e3979a56170bc92.aa8e5d76a346c22c
+ 0000000000000000
+VCVTTSD2SI_32(mem)
+ before
+ ba8bf1ce3a33f50e.b68d86f990fc3a4b.763b08604887e0d4.d72e16768872b8a7
+ 377874995b830c33.34d5b6067ded7b61.acd2b5e7da41a126.8232d69420c593e7
+ 2669c55e30c91b62.9fdd444206c03765.26472f31d12b3dab.aa90b66cc8f58aff
+ 64295d09d412dfc4.51f32a1ac703a803.c266f42c4a516f8e.ad96b068198fd99a
+ e58ec2f5b21ebc65
+ after
+ ba8bf1ce3a33f50e.b68d86f990fc3a4b.763b08604887e0d4.d72e16768872b8a7
+ 377874995b830c33.34d5b6067ded7b61.acd2b5e7da41a126.8232d69420c593e7
+ 2669c55e30c91b62.9fdd444206c03765.26472f31d12b3dab.aa90b66cc8f58aff
+ 64295d09d412dfc4.51f32a1ac703a803.c266f42c4a516f8e.ad96b068198fd99a
+ 0000000080000000
+
+VCVTTSD2SI_64(reg)
+ before
+ b0c5e7802c2f6e0b.ce86b98663691488.a76166f85d420be6.5afb7fc260bff4fb
+ 68871b73264d2c39.3e4a56c1fadb75d8.fd74f34a63089cbb.cbd24ce130828720
+ 6b205b3c3904329b.9142afa6b573bfe1.ae78ce7a76e1962d.f2b6d774d5a5e526
+ 13dca14603e1bbdc.a4394022ae3daece.18b9f1f6325936e9.a9759d676c35cb3c
+ cdd919a6103df28c
+ after
+ b0c5e7802c2f6e0b.ce86b98663691488.a76166f85d420be6.5afb7fc260bff4fb
+ 68871b73264d2c39.3e4a56c1fadb75d8.fd74f34a63089cbb.cbd24ce130828720
+ 6b205b3c3904329b.9142afa6b573bfe1.ae78ce7a76e1962d.f2b6d774d5a5e526
+ 13dca14603e1bbdc.a4394022ae3daece.18b9f1f6325936e9.a9759d676c35cb3c
+ 8000000000000000
+VCVTTSD2SI_64(mem)
+ before
+ 3aafc71dddc91943.bd06ebfd206f04a9.51fd861f0445fecc.96825a2932fdb89a
+ ccc323b8f1e5fa8c.c6eb34cd2b3a49ae.7559fb8bd1986a06.8421047f125857ee
+ 60e1a963659e5294.88d87822c0cfc696.ec181d513142afa9.3ee0eb646ff7518e
+ d0d4d60a57ffdc86.6017b4687cb9b60d.9207675c414d89e1.200c0b44e465e029
+ 85f1618b0e2e4069
+ after
+ 3aafc71dddc91943.bd06ebfd206f04a9.51fd861f0445fecc.96825a2932fdb89a
+ ccc323b8f1e5fa8c.c6eb34cd2b3a49ae.7559fb8bd1986a06.8421047f125857ee
+ 60e1a963659e5294.88d87822c0cfc696.ec181d513142afa9.3ee0eb646ff7518e
+ d0d4d60a57ffdc86.6017b4687cb9b60d.9207675c414d89e1.200c0b44e465e029
+ 0000000000000000
+
+VCVTTSD2SI_64(reg)
+ before
+ cbdbe8a688deaffa.f96a259ae215568f.aaf4e30bfb8456c0.43f2569a1cc7b4d9
+ 4d159cffee026789.b76d12fd23eb7adb.c3bd0178d8bde25b.dca564f6debbebbe
+ 66ed7904de25a5c2.e6aa1a21368d0595.05bd0a19afef958a.37ec0f5ca536ebbb
+ 74ad7c1ff1d4a450.62edb7f13608b2ea.cd3ffa5c1da6acf8.3192d2b88a436ffd
+ a66529f7abee35b0
+ after
+ cbdbe8a688deaffa.f96a259ae215568f.aaf4e30bfb8456c0.43f2569a1cc7b4d9
+ 4d159cffee026789.b76d12fd23eb7adb.c3bd0178d8bde25b.dca564f6debbebbe
+ 66ed7904de25a5c2.e6aa1a21368d0595.05bd0a19afef958a.37ec0f5ca536ebbb
+ 74ad7c1ff1d4a450.62edb7f13608b2ea.cd3ffa5c1da6acf8.3192d2b88a436ffd
+ 8000000000000000
+VCVTTSD2SI_64(mem)
+ before
+ 722f90032444f7ff.d2a29fbec59aa1e0.070267583f673e05.7790ceabbd6f6351
+ 70bd84c910507217.db18e04cf603d81e.b1b5a5446eb66513.5ffc80742cd5f643
+ 7edb80368b1e6123.ed5b3b351f9c85b5.3cd1eda0de02e340.e1cf0f220565a077
+ 77550035b2ba8150.62b7aae5dcf0e452.8424bc58ac5673b7.59557421e5a99e9c
+ 23daacdd67302c5c
+ after
+ 722f90032444f7ff.d2a29fbec59aa1e0.070267583f673e05.7790ceabbd6f6351
+ 70bd84c910507217.db18e04cf603d81e.b1b5a5446eb66513.5ffc80742cd5f643
+ 7edb80368b1e6123.ed5b3b351f9c85b5.3cd1eda0de02e340.e1cf0f220565a077
+ 77550035b2ba8150.62b7aae5dcf0e452.8424bc58ac5673b7.59557421e5a99e9c
+ 8000000000000000
+
+VCVTTSD2SI_64(reg)
+ before
+ 9ba9b4c228838663.37f680b1a1318eca.98772ac8ca8b30a0.65788c58f3bed2a4
+ 1d10873cc330e75e.9a8c7d98738f44bc.e9e9b84a85f9a64c.ba9adb8dd047bc35
+ 055921b8d5c28cf9.7ce171d544de5e52.b2574fd7a7c78101.615624e15efced94
+ afd17ea0f9c5b1e0.b8c2da54312d99ba.500eecdbcf81ff6c.3578e342b9e920ed
+ 12cb959afe1b126d
+ after
+ 9ba9b4c228838663.37f680b1a1318eca.98772ac8ca8b30a0.65788c58f3bed2a4
+ 1d10873cc330e75e.9a8c7d98738f44bc.e9e9b84a85f9a64c.ba9adb8dd047bc35
+ 055921b8d5c28cf9.7ce171d544de5e52.b2574fd7a7c78101.615624e15efced94
+ afd17ea0f9c5b1e0.b8c2da54312d99ba.500eecdbcf81ff6c.3578e342b9e920ed
+ 0000000000000000
+VCVTTSD2SI_64(mem)
+ before
+ d31db5d7499d7f40.77c49b62cbc691be.2cfb33015585b11e.1d5a89c397b15a39
+ 5638bfe3b57b2291.b87d7368e850693f.b358f9c8cdf462aa.778724f99be5ce13
+ 76e92fac5ec2b88d.d04a0220ecf07510.28a5a696b485678b.b8e0b8eb78a999a7
+ 0efc811d617dfd60.1a7544f57231f0dd.69adb85527447ded.3db34104c987f5a0
+ 624abbb02b0d1fab
+ after
+ d31db5d7499d7f40.77c49b62cbc691be.2cfb33015585b11e.1d5a89c397b15a39
+ 5638bfe3b57b2291.b87d7368e850693f.b358f9c8cdf462aa.778724f99be5ce13
+ 76e92fac5ec2b88d.d04a0220ecf07510.28a5a696b485678b.b8e0b8eb78a999a7
+ 0efc811d617dfd60.1a7544f57231f0dd.69adb85527447ded.3db34104c987f5a0
+ 0000000000000000
+
+VCVTSI2SS_64(reg)
+ before
+ 83f2235b39c75274.fc3d3222dab8ad35.f24b3552169f1851.513eaaf2413e60fb
+ fdf773718f40cca6.1a77bda7e4808339.b318d2a575c72719.bb22f85a1f7ecbe2
+ 2aa5a95eca04c7ee.46789e999be03c97.bb2816592b3359e1.85261f78dc107bce
+ 6748c08e869f80f7.5a0a51e21ce5947c.64c7fddbd272ec54.8916993794012cea
+ a5bee485645c9a63
+ after
+ 0000000000000000.0000000000000000.b318d2a575c72719.bb22f85adeb48237
+ fdf773718f40cca6.1a77bda7e4808339.b318d2a575c72719.bb22f85a1f7ecbe2
+ 2aa5a95eca04c7ee.46789e999be03c97.bb2816592b3359e1.85261f78dc107bce
+ 6748c08e869f80f7.5a0a51e21ce5947c.64c7fddbd272ec54.8916993794012cea
+ a5bee485645c9a63
+VCVTSI2SS_64(mem)
+ before
+ b3e97b4d682e8064.102bb56d5e9e326e.34fa536f82994613.0c418395090d1a1f
+ 9065db7bbb819b1a.819c8368ee8c1aff.ae141e2dea0a0f89.0ee1a5f4699220ed
+ 19fc7efb7964a7b0.16e525e9d3f57455.a52430066f44ab0a.c5f45e65918c396b
+ 287be2babfe05f53.2b539a5ea9667c1d.f6f604e82e52d6c1.8fc6aa521a88a344
+ c6a38529a3119825
+ after
+ b3e97b4d682e8064.102bb56d5e9e326e.34fa536f82994613.0c418395090d1a1f
+ 9065db7bbb819b1a.819c8368ee8c1aff.ae141e2dea0a0f89.0ee1a5f4699220ed
+ 0000000000000000.0000000000000000.ae141e2dea0a0f89.0ee1a5f45d441839
+ 287be2babfe05f53.2b539a5ea9667c1d.f6f604e82e52d6c1.8fc6aa521a88a344
+ c6a38529a3119825
+
+VCVTSI2SS_64(reg)
+ before
+ c7d7eb55c5b354ba.9aae82a2a903802f.1c32db310b6a6d02.7b5517be42404bdb
+ efaed9411efb15ae.4c61daa052d8c66f.45cde5d0958e84b1.110fe374c71ac784
+ 98734a5b4a7415ae.186067a1d66ced40.0272b5a6e45cfdd6.95eee6f6dbed06e7
+ 20743a0ee4aa9166.db76a38f52c9b0cd.ae6b461f9363141c.e1bf9b3097c4c330
+ d24e7e0e19acbb8c
+ after
+ 0000000000000000.0000000000000000.45cde5d0958e84b1.110fe374de36c608
+ efaed9411efb15ae.4c61daa052d8c66f.45cde5d0958e84b1.110fe374c71ac784
+ 98734a5b4a7415ae.186067a1d66ced40.0272b5a6e45cfdd6.95eee6f6dbed06e7
+ 20743a0ee4aa9166.db76a38f52c9b0cd.ae6b461f9363141c.e1bf9b3097c4c330
+ d24e7e0e19acbb8c
+VCVTSI2SS_64(mem)
+ before
+ 44670c7c7db0aa27.e1fba5c6882ac481.71700c58e1fecc43.a70694a73f2c0430
+ 13d5c066dedc4c2d.385587efd37fecab.b61b1de7a014fdce.488d9caa83450abd
+ 1b6615b9583d5cc9.81ceddf661354391.87415228aa19ff99.ed4d5894fc396270
+ 38e48a5f08de9727.18b1a245cdd906df.beaf28071c188dd1.f191c6d2459547f5
+ b2a7e1cefbe4f6f7
+ after
+ 44670c7c7db0aa27.e1fba5c6882ac481.71700c58e1fecc43.a70694a73f2c0430
+ 13d5c066dedc4c2d.385587efd37fecab.b61b1de7a014fdce.488d9caa83450abd
+ 0000000000000000.0000000000000000.b61b1de7a014fdce.488d9caadeb1f2d7
+ 38e48a5f08de9727.18b1a245cdd906df.beaf28071c188dd1.f191c6d2459547f5
+ b2a7e1cefbe4f6f7
+
+VCVTSI2SS_64(reg)
+ before
+ 8bdaa5f5b9b2ab23.471c984609cbb975.5a4cd24ab3f67041.38301a70111e64a1
+ d7750fb41c8ba124.22dabc5978107edc.a1e96a6fb018be62.d192a44fa5363f36
+ f4c51a76bffc16a7.a5ea738371baa18b.4ad664225fcc2cee.659f4290f56cdcbc
+ 3c16c1a73e904457.ae1838b20ed5dfac.b15dbece5d9df693.d02570201dcdf55e
+ eeeeabe938644749
+ after
+ 0000000000000000.0000000000000000.a1e96a6fb018be62.d192a44fdd888aa1
+ d7750fb41c8ba124.22dabc5978107edc.a1e96a6fb018be62.d192a44fa5363f36
+ f4c51a76bffc16a7.a5ea738371baa18b.4ad664225fcc2cee.659f4290f56cdcbc
+ 3c16c1a73e904457.ae1838b20ed5dfac.b15dbece5d9df693.d02570201dcdf55e
+ eeeeabe938644749
+VCVTSI2SS_64(mem)
+ before
+ 9ac76ed9633d8da8.0db403b236d467e1.182f87d16e6bf36b.32cb73de451857fa
+ b27b35dab96584a8.c1ebd9054353bdf1.bffdddccaa8a9bf5.296b7fc0b4c78cd2
+ 11d87cda56e7e875.b606410c00998032.7f4cb590e13e9176.f28bdfdf4538d1c5
+ 93a8bfc457cf753a.465335310933ed51.34e98a072c91921a.e9768ea795f7617f
+ 6a7787853f8f7aad
+ after
+ 9ac76ed9633d8da8.0db403b236d467e1.182f87d16e6bf36b.32cb73de451857fa
+ b27b35dab96584a8.c1ebd9054353bdf1.bffdddccaa8a9bf5.296b7fc0b4c78cd2
+ 0000000000000000.0000000000000000.bffdddccaa8a9bf5.296b7fc05e4b2dcf
+ 93a8bfc457cf753a.465335310933ed51.34e98a072c91921a.e9768ea795f7617f
+ 6a7787853f8f7aad
+
+VCVTSI2SD_64(reg)
+ before
+ d1dbc9e3e08c56fb.14b97b84d72ae624.cf1cb3e1fbac3ffa.baa0da1ea991590b
+ 7aee4d2e137a3115.6fd52b06f303f85e.abaeb7887190b4d8.ec3d21c2744aa478
+ c0fc11d374e649a6.82c94b36c6666715.37553b93086c8697.a88bd9dda8c62c8b
+ 01500f3ca05bd85a.286158006d60ef74.d05d3d6c5bcbf2e5.c958805d6213b071
+ 2a6e912dbd3deb55
+ after
+ 0000000000000000.0000000000000000.abaeb7887190b4d8.43c5374896de9ef6
+ 7aee4d2e137a3115.6fd52b06f303f85e.abaeb7887190b4d8.ec3d21c2744aa478
+ c0fc11d374e649a6.82c94b36c6666715.37553b93086c8697.a88bd9dda8c62c8b
+ 01500f3ca05bd85a.286158006d60ef74.d05d3d6c5bcbf2e5.c958805d6213b071
+ 2a6e912dbd3deb55
+VCVTSI2SD_64(mem)
+ before
+ a99a8838d54e9864.983845d733661bde.3c68cc5003fc4ba9.d011b8810739336b
+ 21a8e26cc75574ca.e1feaf0fc8924dde.9cac2513a54638dd.94bfa83da74386d8
+ 6d6419b4ae5b3ab2.37f04750fb6bab05.23f7de336e4b723f.79b1090bd87427d6
+ 6b99abfca76ea748.f8580b06697d7100.ac17739e7b16b4f8.d934d85935585212
+ 11940f925b7c4237
+ after
+ a99a8838d54e9864.983845d733661bde.3c68cc5003fc4ba9.d011b8810739336b
+ 21a8e26cc75574ca.e1feaf0fc8924dde.9cac2513a54638dd.94bfa83da74386d8
+ 0000000000000000.0000000000000000.9cac2513a54638dd.c3c7f723bf7c6366
+ 6b99abfca76ea748.f8580b06697d7100.ac17739e7b16b4f8.d934d85935585212
+ 11940f925b7c4237
+
+VCVTSI2SD_64(reg)
+ before
+ 7d1dac23e56b34f2.f5151331ce9977ba.7f83f69dad55db7b.15d6613ee7b3bb37
+ 791aab766fb164ee.e9a2cd3d3de86632.27bc0481647f2521.38012201cf2f4326
+ 61d906f896db0dd8.210d560d136830dc.4e51311e2a858a9f.f36334d24e9508f2
+ 91a4bb15f6746d5c.7b22298e692490e5.4e8c79e199f546a0.20ca129d80f2c5c6
+ 9c00394e825137cf
+ after
+ 0000000000000000.0000000000000000.27bc0481647f2521.c3d8fff1ac5f6bb2
+ 791aab766fb164ee.e9a2cd3d3de86632.27bc0481647f2521.38012201cf2f4326
+ 61d906f896db0dd8.210d560d136830dc.4e51311e2a858a9f.f36334d24e9508f2
+ 91a4bb15f6746d5c.7b22298e692490e5.4e8c79e199f546a0.20ca129d80f2c5c6
+ 9c00394e825137cf
+VCVTSI2SD_64(mem)
+ before
+ 44d323d170be1a38.65c9c53a2a09bd25.d1adc2aa5e294379.85bbd934505a97d1
+ f20d4e126545292e.399220d1ce243ce0.007a9d4f0b8104c3.4d284c85e841b7dd
+ 837b35fe7df321dd.694bc8487f542538.e55436688f3b90f0.0420ce3eff35e371
+ d4e9547fd5d3be70.5142b90ad922b3da.5a090ae10360a42b.04ee5ccd31c25739
+ abe0f09d19754fe0
+ after
+ 44d323d170be1a38.65c9c53a2a09bd25.d1adc2aa5e294379.85bbd934505a97d1
+ f20d4e126545292e.399220d1ce243ce0.007a9d4f0b8104c3.4d284c85e841b7dd
+ 0000000000000000.0000000000000000.007a9d4f0b8104c3.c3de9109b2ebe95a
+ d4e9547fd5d3be70.5142b90ad922b3da.5a090ae10360a42b.04ee5ccd31c25739
+ abe0f09d19754fe0
+
+VCVTSI2SD_64(reg)
+ before
+ 5341881a54d90613.bf22278288f2bc14.4dc2f083761c2271.3c6393a685fef9a1
+ 595c1fb07d7ab97d.21f42bf4b35bd6f5.b916681ff5cdb0ab.672f50a331204e7e
+ 1a7eb2cb30e5a3cc.d629dbc0711ac93e.f08b1d4af0c29731.b839bac422d35ded
+ f0f33bd70aa501a9.ba8eb3d2df3b511b.506e0c70038514b2.094d4ef57422e31b
+ 3736892244199b33
+ after
+ 0000000000000000.0000000000000000.b916681ff5cdb0ab.43cb9b4491220cce
+ 595c1fb07d7ab97d.21f42bf4b35bd6f5.b916681ff5cdb0ab.672f50a331204e7e
+ 1a7eb2cb30e5a3cc.d629dbc0711ac93e.f08b1d4af0c29731.b839bac422d35ded
+ f0f33bd70aa501a9.ba8eb3d2df3b511b.506e0c70038514b2.094d4ef57422e31b
+ 3736892244199b33
+VCVTSI2SD_64(mem)
+ before
+ 1ec2e638aec44362.3807b840a74610c2.aaef2f1518cb2ab9.34082ffdcaa563d8
+ 9abbe121cd3095d4.4e062472a25509c3.8018cc7739d50f44.f8a8845de3abbf4f
+ 87eef6cbbd684eb4.8e3b7bda975d2b58.19d505e35d66bde8.f79906fde72565c4
+ c127a2219b79292f.55f4b9e223eab02c.51f15646a189efd0.8f26b147749e91e3
+ 1b9d82a926a37f57
+ after
+ 1ec2e638aec44362.3807b840a74610c2.aaef2f1518cb2ab9.34082ffdcaa563d8
+ 9abbe121cd3095d4.4e062472a25509c3.8018cc7739d50f44.f8a8845de3abbf4f
+ 0000000000000000.0000000000000000.8018cc7739d50f44.43ca0417fee552b2
+ c127a2219b79292f.55f4b9e223eab02c.51f15646a189efd0.8f26b147749e91e3
+ 1b9d82a926a37f57
+
+VCVTSI2SD_32(reg)
+ before
+ f648748e98bf6acd.2432600e826ee370.fd7bdbf8e189d5eb.043a3b8a204a6328
+ 7e748361677e8ff1.8cdbac808f5338a4.e31ddc876ec5d642.0e7a309cf6b6d31d
+ 0d6dab902e6c2a6e.d5ed0262dd35e4f7.6326b8fb652aeedd.4b7eb26940d8fcdb
+ 017ee886891676f0.db36dea0891fa294.d9e26bc063455a68.96123bdb1abc998d
+ cd024ae09f6f6760
+ after
+ 0000000000000000.0000000000000000.e31ddc876ec5d642.c1d8242628000000
+ 7e748361677e8ff1.8cdbac808f5338a4.e31ddc876ec5d642.0e7a309cf6b6d31d
+ 0d6dab902e6c2a6e.d5ed0262dd35e4f7.6326b8fb652aeedd.4b7eb26940d8fcdb
+ 017ee886891676f0.db36dea0891fa294.d9e26bc063455a68.96123bdb1abc998d
+ cd024ae09f6f6760
+VCVTSI2SD_32(mem)
+ before
+ cb195863ebfc2280.b4f537af1508b025.7a80bd27ae1d2fa8.a19cf14203a1568e
+ 6c25e24f1b6f8618.841c92786dcc14b7.8d981ae1693c475e.17a247ede2cb1dfb
+ 8cf065924ad54e55.cb41f84b2ef0de52.f24a71bbd587a6e3.973e682d9b4eec5c
+ 06475c1795393762.e6ae6295f40049a3.84623ea20f0a0763.7dbd506ecbb6ff5d
+ 246bfc1d0d8f92aa
+ after
+ cb195863ebfc2280.b4f537af1508b025.7a80bd27ae1d2fa8.a19cf14203a1568e
+ 6c25e24f1b6f8618.841c92786dcc14b7.8d981ae1693c475e.17a247ede2cb1dfb
+ 0000000000000000.0000000000000000.8d981ae1693c475e.418d0ab470000000
+ 06475c1795393762.e6ae6295f40049a3.84623ea20f0a0763.7dbd506ecbb6ff5d
+ 246bfc1d0d8f92aa
+
+VCVTSI2SD_32(reg)
+ before
+ ea9466a4fd66e0ed.b8f643ca18a7fd6c.32b0cdc359869256.1fabfe8032d22709
+ 2a848c7138c627d5.7dc99698ed2c5c9f.0992363ffc10f516.9ef32b435aeac202
+ 408669ee5a3ca00c.308cd26b33d30f26.c8a29877762aad90.df0443d6a45e9379
+ 87e8f989fe538a3f.af0a723003a8d32d.cc2aefd5665ef76f.bdabc2242c3b579b
+ 13b4221b0d8cca93
+ after
+ 0000000000000000.0000000000000000.0992363ffc10f516.41ab199526000000
+ 2a848c7138c627d5.7dc99698ed2c5c9f.0992363ffc10f516.9ef32b435aeac202
+ 408669ee5a3ca00c.308cd26b33d30f26.c8a29877762aad90.df0443d6a45e9379
+ 87e8f989fe538a3f.af0a723003a8d32d.cc2aefd5665ef76f.bdabc2242c3b579b
+ 13b4221b0d8cca93
+VCVTSI2SD_32(mem)
+ before
+ bfebe1a6635ea88e.5df439adc0971f19.d511f2d47bb864e2.6f7837c7653a0f60
+ 9b1b79b24bbbacb8.1df723c63d949c47.7d6bce41b70e7d6f.0ed66db8124a310f
+ 85126929e0b1933c.223db54010d73d75.85e58265d2b7db00.05918c1406189827
+ 579a2af83f4c1947.ca12ea87d6eb3d4e.c74b8b2be9bd3ac2.b0f59047df328155
+ 6b4d75be39242844
+ after
+ bfebe1a6635ea88e.5df439adc0971f19.d511f2d47bb864e2.6f7837c7653a0f60
+ 9b1b79b24bbbacb8.1df723c63d949c47.7d6bce41b70e7d6f.0ed66db8124a310f
+ 0000000000000000.0000000000000000.7d6bce41b70e7d6f.41d94e83d8000000
+ 579a2af83f4c1947.ca12ea87d6eb3d4e.c74b8b2be9bd3ac2.b0f59047df328155
+ 6b4d75be39242844
+
+VCVTSI2SD_32(reg)
+ before
+ 92e737e3af79c9a1.ef80390b8397f905.70c1bf082b5dd97e.2169647e172e56e1
+ 810dd323ddbd9f18.2790134fc99ef0a1.6f982e2da9b84db3.6d0a894c7816ea88
+ 940c44eb607ce754.dd9633af2c6dba47.25e13563ef88d597.88fc76802980b3e4
+ 273086a5d443dc02.eb5e1516c9111325.ece9cf17965aacd6.4f09a80746786d21
+ 9cfe9acbea0ad36a
+ after
+ 0000000000000000.0000000000000000.6f982e2da9b84db3.c1b5f52c96000000
+ 810dd323ddbd9f18.2790134fc99ef0a1.6f982e2da9b84db3.6d0a894c7816ea88
+ 940c44eb607ce754.dd9633af2c6dba47.25e13563ef88d597.88fc76802980b3e4
+ 273086a5d443dc02.eb5e1516c9111325.ece9cf17965aacd6.4f09a80746786d21
+ 9cfe9acbea0ad36a
+VCVTSI2SD_32(mem)
+ before
+ 4ca7c8b93143a2eb.96c595bfd49dbccd.2eb43572bb95b665.22fcf8b33cb90f1d
+ 3cd0aebe382e96d1.3d176ea4fc16c162.826310ae1f066033.2166aca57d313a18
+ 4645c8c41ad86b48.78720bc0e93b286d.c43821b6106fcdbc.4672e858f44f6872
+ 47d193b9f44cdc7c.a3216a7e36972c99.ceffe476abdcb82c.ee6ea7383e9ed6d8
+ 73a4e5b1f6aac0f5
+ after
+ 4ca7c8b93143a2eb.96c595bfd49dbccd.2eb43572bb95b665.22fcf8b33cb90f1d
+ 3cd0aebe382e96d1.3d176ea4fc16c162.826310ae1f066033.2166aca57d313a18
+ 0000000000000000.0000000000000000.826310ae1f066033.41ce5c878e800000
+ 47d193b9f44cdc7c.a3216a7e36972c99.ceffe476abdcb82c.ee6ea7383e9ed6d8
+ 73a4e5b1f6aac0f5
+
+VPOR_128(reg)
+ before
+ 32619e2fb8006277.1b428a87e196a698.1a71864d80b70a93.7d84d5da0b59deae
+ 88f1cf1e212bf707.9f62291cfec385c8.39ae5c966226fe06.ad9371ce4cf3fb6f
+ cfa072eacdb7bc53.adfeec6366dd353a.5b24e6c67970449f.3af8323f8bb5cb9a
+ 64ba85005731ed07.22e2504836f37117.de1f22496021170a.017e9617e3ac095c
+ dcf2184371e372e1
+ after
+ 0000000000000000.0000000000000000.7baefed67b76fe9f.bffb73ffcff7fbff
+ 88f1cf1e212bf707.9f62291cfec385c8.39ae5c966226fe06.ad9371ce4cf3fb6f
+ cfa072eacdb7bc53.adfeec6366dd353a.5b24e6c67970449f.3af8323f8bb5cb9a
+ 64ba85005731ed07.22e2504836f37117.de1f22496021170a.017e9617e3ac095c
+ dcf2184371e372e1
+VPOR_128(mem)
+ before
+ a82035b05166c254.a38b04ca5b24c6cf.dad9cfb7890ef68e.1deb0b8cb4c6b5f2
+ 41d467499e42b5e2.e85ee9b6761c8256.b1b1e79c7c3c7fc9.73d39ef910eb5703
+ 83da2cfa748206b6.8f80322e43a65e48.833414e32a88caf4.3e24d5fe101a3ceb
+ 4afeffaef03272fd.f53dd9a05f4d9552.2c30d079afff913d.d92bae0552e19e54
+ 9f32247c6fcbbaea
+ after
+ a82035b05166c254.a38b04ca5b24c6cf.dad9cfb7890ef68e.1deb0b8cb4c6b5f2
+ 41d467499e42b5e2.e85ee9b6761c8256.b1b1e79c7c3c7fc9.73d39ef910eb5703
+ 0000000000000000.0000000000000000.fbf9efbffd3effcf.7ffb9ffdb4eff7f3
+ 4afeffaef03272fd.f53dd9a05f4d9552.2c30d079afff913d.d92bae0552e19e54
+ 9f32247c6fcbbaea
+
+VPOR_128(reg)
+ before
+ ee8533ce0565cc5a.710b5c532d5fb4e3.74e1dc77659d6520.886f994828ac91cd
+ 2072d767b03a0f50.d6cfc0d548148a93.69b8371ff223085e.73bee93eb19b85d3
+ 93440db30ad6c177.5414a51e5c5dae3a.300ee404a16abab7.c8e83e4565d92a79
+ a146d01eb2c61b7c.c7a7891b8647dd03.252ee1920fffb9d7.65bb144b60713ceb
+ 2501e53bbf6f7756
+ after
+ 0000000000000000.0000000000000000.79bef71ff36bbaff.fbfeff7ff5dbaffb
+ 2072d767b03a0f50.d6cfc0d548148a93.69b8371ff223085e.73bee93eb19b85d3
+ 93440db30ad6c177.5414a51e5c5dae3a.300ee404a16abab7.c8e83e4565d92a79
+ a146d01eb2c61b7c.c7a7891b8647dd03.252ee1920fffb9d7.65bb144b60713ceb
+ 2501e53bbf6f7756
+VPOR_128(mem)
+ before
+ e4882f019ee096e6.a7c51c1542955c0b.0b54e7b8e1ddd21b.a3652935d76c3f6b
+ 7e1a6d8917cf56c6.020ded0256cfbecf.fce73ce2892b4aad.0800b85a9640891f
+ ce841bbf49487323.0c6a3f528b017e74.752b02839b3e01e7.af498a6be704d39e
+ b292b58f4d58a929.22280f727cb6d8a8.54eeb7893321b3f2.f48c9cd666465895
+ 3317e905b09155b0
+ after
+ e4882f019ee096e6.a7c51c1542955c0b.0b54e7b8e1ddd21b.a3652935d76c3f6b
+ 7e1a6d8917cf56c6.020ded0256cfbecf.fce73ce2892b4aad.0800b85a9640891f
+ 0000000000000000.0000000000000000.fff7fffae9ffdabf.ab65b97fd76cbf7f
+ b292b58f4d58a929.22280f727cb6d8a8.54eeb7893321b3f2.f48c9cd666465895
+ 3317e905b09155b0
+
+VPOR_128(reg)
+ before
+ c8356d666172069a.050fb8e5420ab303.a19358cdc67a0714.74fad6df6ce01cfd
+ 0e3124641473a700.a2c99fae416a4ede.e3f616ce04da4967.b01cdb716288f731
+ 63580a6a6523738d.678ae6d4698536e5.459e45e3d361d84b.e620422a322401bd
+ 22f61ce6f10ba7ee.2e200945d3662645.23d8e277ce9bf06c.f0d288f9f8c0f5cb
+ acfd28c7cf699088
+ after
+ 0000000000000000.0000000000000000.e7fe57efd7fbd96f.f63cdb7b72acf7bd
+ 0e3124641473a700.a2c99fae416a4ede.e3f616ce04da4967.b01cdb716288f731
+ 63580a6a6523738d.678ae6d4698536e5.459e45e3d361d84b.e620422a322401bd
+ 22f61ce6f10ba7ee.2e200945d3662645.23d8e277ce9bf06c.f0d288f9f8c0f5cb
+ acfd28c7cf699088
+VPOR_128(mem)
+ before
+ f46f9e81d32a8e1f.a657554353b97fcf.d55584eb9d1adb29.d9eee8f69215cf78
+ a6f266132110abbd.4dc7b1ee28b836db.36f6d4b4e3ab11be.c42c53ccba5aaf18
+ 9c53fd6ad425a38d.71912c510b9509be.2fce748bc0288430.3ee01f65e2f6ccfb
+ b45edd70097731bd.7003c3d999db3426.9aabe05c519aefaa.a455482ea77664cb
+ 52d6cb91a565b134
+ after
+ f46f9e81d32a8e1f.a657554353b97fcf.d55584eb9d1adb29.d9eee8f69215cf78
+ a6f266132110abbd.4dc7b1ee28b836db.36f6d4b4e3ab11be.c42c53ccba5aaf18
+ 0000000000000000.0000000000000000.f7f7d4ffffbbdbbf.ddeefbfeba5fef78
+ b45edd70097731bd.7003c3d999db3426.9aabe05c519aefaa.a455482ea77664cb
+ 52d6cb91a565b134
+
+VPXOR_128(reg)
+ before
+ a4b0a3fc774ff0e4.c8df8413db121276.a56770f36d16f3bd.55579413b00f0f59
+ f62fccd9b9c15d84.b5a26d3d670101e6.6b0a310924d3812f.3aa00d9cfc92a069
+ a49f4296084633c3.587315dcc850bb39.1f380289599d1b29.2650c6e34f305d05
+ 0a4c029eff6baf4b.8b1df6db1b0bfc9b.1e3ddddea900fd57.f6343bd5c5f30359
+ 8418e85c7bea4e93
+ after
+ 0000000000000000.0000000000000000.743233807d4e9a06.1cf0cb7fb3a2fd6c
+ f62fccd9b9c15d84.b5a26d3d670101e6.6b0a310924d3812f.3aa00d9cfc92a069
+ a49f4296084633c3.587315dcc850bb39.1f380289599d1b29.2650c6e34f305d05
+ 0a4c029eff6baf4b.8b1df6db1b0bfc9b.1e3ddddea900fd57.f6343bd5c5f30359
+ 8418e85c7bea4e93
+VPXOR_128(mem)
+ before
+ adc749668c1efadd.8381065c3bbb0dc8.2b6d8e267b3f8037.c265c073af896264
+ 4d0fdbdd159dc263.6d8c4c3e58c288e7.152f58a904f70339.69fba5b608c387fd
+ 40ba19af32726352.23b7d0aff00c5e54.232fd050d34040cf.6d4c8b124f3aa8cd
+ 63957fc7fdaa99d6.014f8c1ca226c9bb.323973070425f422.2ba56bf3207b0181
+ ff5042c51811cdc5
+ after
+ adc749668c1efadd.8381065c3bbb0dc8.2b6d8e267b3f8037.c265c073af896264
+ 4d0fdbdd159dc263.6d8c4c3e58c288e7.152f58a904f70339.69fba5b608c387fd
+ 0000000000000000.0000000000000000.3e42d68f7fc8830e.ab9e65c5a74ae599
+ 63957fc7fdaa99d6.014f8c1ca226c9bb.323973070425f422.2ba56bf3207b0181
+ ff5042c51811cdc5
+
+VPXOR_128(reg)
+ before
+ 469a0df5d3884944.906c89119450201a.63a07eef079b05c7.1e19bcbbb2b2da61
+ 5acec7edec6db1ab.a40bb4791370b34b.a4f6a095bef85024.c39a2756f9f4b0b6
+ 983a6c1bff4b40a6.7b3e7aeb95160f94.229cf07a60c8e47f.fd8930c6f6f6304d
+ 5c28f9e9a9ae33e0.f1d05953374fef22.38e06a0b8b97fe84.a8b253f5c4c41754
+ a0e10dd1806a20f4
+ after
+ 0000000000000000.0000000000000000.866a50efde30b45b.3e1317900f0280fb
+ 5acec7edec6db1ab.a40bb4791370b34b.a4f6a095bef85024.c39a2756f9f4b0b6
+ 983a6c1bff4b40a6.7b3e7aeb95160f94.229cf07a60c8e47f.fd8930c6f6f6304d
+ 5c28f9e9a9ae33e0.f1d05953374fef22.38e06a0b8b97fe84.a8b253f5c4c41754
+ a0e10dd1806a20f4
+VPXOR_128(mem)
+ before
+ c1e2d84546f5085c.02e568c58523c605.e28fcc9d14271121.410c08b3dbf1d9de
+ e781323d30718bb6.e6beb71a303535c2.2a4550b549a82fbc.9b6dc8ddeb63b23a
+ ee8997a55de8652e.64fce1534570bbc3.a5bf5f88f1e00620.a04fa5f75779c544
+ b2c88169e66851f2.d8eee2de616195b4.2fc9770028da5178.aefe9b6cbcbd4ea7
+ 1fc6a6a8b6bd890f
+ after
+ c1e2d84546f5085c.02e568c58523c605.e28fcc9d14271121.410c08b3dbf1d9de
+ e781323d30718bb6.e6beb71a303535c2.2a4550b549a82fbc.9b6dc8ddeb63b23a
+ 0000000000000000.0000000000000000.c8ca9c285d8f3e9d.da61c06e30926be4
+ b2c88169e66851f2.d8eee2de616195b4.2fc9770028da5178.aefe9b6cbcbd4ea7
+ 1fc6a6a8b6bd890f
+
+VPXOR_128(reg)
+ before
+ 51f2c317e004b12a.0f086e75eafd0c2b.9edfb7261f93ff40.a32f130b0ba3cdf1
+ 9ed0ed25d61f03a2.e116d8b582b15208.121a5a971c933513.dfbdb094b54636b6
+ 64aa203e3599ba23.03be3e15cc92dfb3.90edc99ef3eb72da.be3ec88643cf48f5
+ fdcd58cf98fe135a.53cc1982e4ac6e58.74a2ffa5412af341.1c7fd9cfd14bbed7
+ d54c5e5a7ac5558b
+ after
+ 0000000000000000.0000000000000000.82f79309ef7847c9.61837812f6897e43
+ 9ed0ed25d61f03a2.e116d8b582b15208.121a5a971c933513.dfbdb094b54636b6
+ 64aa203e3599ba23.03be3e15cc92dfb3.90edc99ef3eb72da.be3ec88643cf48f5
+ fdcd58cf98fe135a.53cc1982e4ac6e58.74a2ffa5412af341.1c7fd9cfd14bbed7
+ d54c5e5a7ac5558b
+VPXOR_128(mem)
+ before
+ c471d3145a49c93b.c68591429cdb4bf3.ac0be6e6e509bc24.1a86f919a1d9f4f3
+ c7bab4e78ee4d613.1c1ec805ddbb9b99.e949222fecb78543.dee5b167af86b09d
+ b9f37ec031a13740.59e3f882f52a42f9.e850484814c284e0.1c0a25f908bc64eb
+ 75e8ab8b608da9ee.da221d2783b57abe.84edd41d79347628.2f43503d48084c88
+ 75da2e9e0af4a321
+ after
+ c471d3145a49c93b.c68591429cdb4bf3.ac0be6e6e509bc24.1a86f919a1d9f4f3
+ c7bab4e78ee4d613.1c1ec805ddbb9b99.e949222fecb78543.dee5b167af86b09d
+ 0000000000000000.0000000000000000.4542c4c909be3967.c463487e0e5f446e
+ 75e8ab8b608da9ee.da221d2783b57abe.84edd41d79347628.2f43503d48084c88
+ 75da2e9e0af4a321
+
+VPSUBB_128(reg)
+ before
+ 491cbc88ea0fa761.d964ba3536b2e848.fb25335f20e78095.98ec439a381b1747
+ 0655f46785e292f5.bf3424a8cf1eaf7b.193937966a4c8f2a.02190fab6c832368
+ 0ad1d4a776fba089.052466d249ddbbb3.8eaa2438fd71e528.9c3fb63c327755b8
+ b0dc57b45ae50fc8.8500fd9ebdfac81b.b7c4f6b174e1bc3c.442cb339a6036a62
+ d4aa838ee2331e93
+ after
+ 0000000000000000.0000000000000000.8b8f135e6ddbaa02.66da596f3a0cceb0
+ 0655f46785e292f5.bf3424a8cf1eaf7b.193937966a4c8f2a.02190fab6c832368
+ 0ad1d4a776fba089.052466d249ddbbb3.8eaa2438fd71e528.9c3fb63c327755b8
+ b0dc57b45ae50fc8.8500fd9ebdfac81b.b7c4f6b174e1bc3c.442cb339a6036a62
+ d4aa838ee2331e93
+VPSUBB_128(mem)
+ before
+ 2a86a02805142c76.53c27afacc2d195e.1d9464f8498192df.f0d3a96d6c295111
+ 208c88f128b15138.51ce37e6695efbf9.a7ab17cc097ed42d.952239d880d3df54
+ 9488b6d76a174905.044d8ce2cc04f043.0113920618fe4b2e.02ffa35f4c6da3b1
+ 6046a6c4e450d008.ca8c745c92ac36e8.05965292920cb311.93b4e26c6d83d9d3
+ a48ef26d7fa0bd67
+ after
+ 2a86a02805142c76.53c27afacc2d195e.1d9464f8498192df.f0d3a96d6c295111
+ 208c88f128b15138.51ce37e6695efbf9.a7ab17cc097ed42d.952239d880d3df54
+ 0000000000000000.0000000000000000.8a17b3d4c0fd424e.a54f906b14aa8e43
+ 6046a6c4e450d008.ca8c745c92ac36e8.05965292920cb311.93b4e26c6d83d9d3
+ a48ef26d7fa0bd67
+
+VPSUBB_128(reg)
+ before
+ 91d9cfcd1c508a18.6192d4a6b56ba16e.fdd4ebbe56e10795.9001d15c94b5c700
+ b6e076f7e31f7d93.7437bd68f6717962.fb74ee76b52f9ff6.7f208d5039034428
+ 6ff1e2596e9ad284.7302dcf6c5701411.1eb777ef4a223cb6.acbf025b9e05e6b4
+ 18560e5e594cc596.3bbfad3c3e732da7.c3e88495b2471882.f4aaaa67dfc469d1
+ 33ac0362164e88aa
+ after
+ 0000000000000000.0000000000000000.ddbd77876b0d6340.d3618bf59bfe5e74
+ b6e076f7e31f7d93.7437bd68f6717962.fb74ee76b52f9ff6.7f208d5039034428
+ 6ff1e2596e9ad284.7302dcf6c5701411.1eb777ef4a223cb6.acbf025b9e05e6b4
+ 18560e5e594cc596.3bbfad3c3e732da7.c3e88495b2471882.f4aaaa67dfc469d1
+ 33ac0362164e88aa
+VPSUBB_128(mem)
+ before
+ 4593883662ae006c.0c5df97241c29176.a83aac267c87814f.475510d4882a7005
+ 0729b5d1dcf18d43.a9509c01c18773cf.963f55a09bb6cc36.0448171868557fec
+ 533b061ea322ea5a.4a7cf5787627a74e.e29a2597b80fca88.570e96cdef5683e3
+ 0695f709d04dd5de.4b2dff41fb2e689f.661697f5ef9b3670.9df3885fb9b9b695
+ 3043e93a600955af
+ after
+ 4593883662ae006c.0c5df97241c29176.a83aac267c87814f.475510d4882a7005
+ 0729b5d1dcf18d43.a9509c01c18773cf.963f55a09bb6cc36.0448171868557fec
+ 0000000000000000.0000000000000000.ee05a97a1f2f4be7.bdf30744e02b0fe7
+ 0695f709d04dd5de.4b2dff41fb2e689f.661697f5ef9b3670.9df3885fb9b9b695
+ 3043e93a600955af
+
+VPSUBB_128(reg)
+ before
+ 6d49b5cb83d29bdd.fc02057e817f08fa.07aeb6c9ed29f36d.ff8027a85b68cd1a
+ b052e87cbca0c5ca.1150ab69d2c23fdb.dc4d167de7a38464.89a4519a18814bb3
+ 55ab7fbba7000f22.214965b7de2538ad.25541bc785295632.e04e92b943f36c67
+ b89e75f3e17db592.08bbb052c2b1ad9b.3d10c2156446a781.e04a65f0f7c9eb62
+ 6564462b510f85cf
+ after
+ 0000000000000000.0000000000000000.b7f9fbb6627a2e32.a956bfe1d58edf4c
+ b052e87cbca0c5ca.1150ab69d2c23fdb.dc4d167de7a38464.89a4519a18814bb3
+ 55ab7fbba7000f22.214965b7de2538ad.25541bc785295632.e04e92b943f36c67
+ b89e75f3e17db592.08bbb052c2b1ad9b.3d10c2156446a781.e04a65f0f7c9eb62
+ 6564462b510f85cf
+VPSUBB_128(mem)
+ before
+ 4b67b1566cd2f5da.3578c69005a3f2c6.a270062799745ad2.82cd06d22086b1fd
+ 6d21225d651df9b0.28856efeb0ff036a.cb35e5237f7afd7d.4ed7e36a5476b053
+ a95c162c57fc4b7d.ed1069a97d1c2429.5ed5c83191cd50c9.ff7a55499ca1e22f
+ dae508af5f7ca86c.e067b4fd098690af.391e2b3ceb7b10e2.ef0159db9593813c
+ 7cbaea8cdbd8ca27
+ after
+ 4b67b1566cd2f5da.3578c69005a3f2c6.a270062799745ad2.82cd06d22086b1fd
+ 6d21225d651df9b0.28856efeb0ff036a.cb35e5237f7afd7d.4ed7e36a5476b053
+ 0000000000000000.0000000000000000.29c5dffce606a3ab.cc0add9834f0ff56
+ dae508af5f7ca86c.e067b4fd098690af.391e2b3ceb7b10e2.ef0159db9593813c
+ 7cbaea8cdbd8ca27
+
+VPSUBD_128(reg)
+ before
+ 00ef04c809fdf89b.dc8874d398a8cbaa.5dd44a66efca85a9.37db8b32a890f9f3
+ d8eda3fcbb8e4946.8b11d6821f8c7163.c0a42750cb733dc3.34d763fee416c628
+ 6100c4928e15f7d1.c24babaa0f3556c2.652347283b0ef4a8.0cdf2e8cbc1b34af
+ f57461f81d203fea.5f046e3584ae36f4.a89da758d826e805.9abf6bc84babffb2
+ bc43939eaed0e35d
+ after
+ 0000000000000000.0000000000000000.5b80e0289064491b.27f8357227fb9179
+ d8eda3fcbb8e4946.8b11d6821f8c7163.c0a42750cb733dc3.34d763fee416c628
+ 6100c4928e15f7d1.c24babaa0f3556c2.652347283b0ef4a8.0cdf2e8cbc1b34af
+ f57461f81d203fea.5f046e3584ae36f4.a89da758d826e805.9abf6bc84babffb2
+ bc43939eaed0e35d
+VPSUBD_128(mem)
+ before
+ 4d3724fb00989bdd.f1947898053b5c3d.3d069a119b03cd24.e45e424e40475386
+ 286698c95e0fe45e.b2ae04e0e1f08b76.371eae297041d67f.77b114740ffd72d6
+ 2b9d6df5e3407a0b.920c023b4ecd0840.2b1823691e730e30.bce31938e0d580a2
+ 30a91f6cac371811.eefb6c15e75e0f47.f3c077bdc1a63065.0f414d054f5aba95
+ cb15ad47f9195c5c
+ after
+ 4d3724fb00989bdd.f1947898053b5c3d.3d069a119b03cd24.e45e424e40475386
+ 286698c95e0fe45e.b2ae04e0e1f08b76.371eae297041d67f.77b114740ffd72d6
+ 0000000000000000.0000000000000000.fa181418d53e095b.9352d226cfb61f50
+ 30a91f6cac371811.eefb6c15e75e0f47.f3c077bdc1a63065.0f414d054f5aba95
+ cb15ad47f9195c5c
+
+VPSUBD_128(reg)
+ before
+ 4eac346a799da2a3.15542819d4007b9c.22c740da482edb39.6de1251176e4f947
+ f351deda6c72c715.b46b06e777a85fd7.8abc79f60fc9a9bf.7449a951583b2505
+ 1552a7046d25095e.ebb934c4b23a80ef.822613d5d5bbb588.e3c27f6984b770c8
+ 12f98c521941a12c.940c2e9ba1c2990f.66500be338913a3e.97192346156396bf
+ 6d1a12d2284b5214
+ after
+ 0000000000000000.0000000000000000.089666213a0df437.908729e8d383b43d
+ f351deda6c72c715.b46b06e777a85fd7.8abc79f60fc9a9bf.7449a951583b2505
+ 1552a7046d25095e.ebb934c4b23a80ef.822613d5d5bbb588.e3c27f6984b770c8
+ 12f98c521941a12c.940c2e9ba1c2990f.66500be338913a3e.97192346156396bf
+ 6d1a12d2284b5214
+VPSUBD_128(mem)
+ before
+ 3f91c7fbd87b61f4.449488310b52ce29.8d2e70585f4d6764.92875b8dd4d6768d
+ eb4abeab42007e8a.096d970ee0e4ca01.b0ed77e708e6a619.6218013d4416a223
+ 4b1174d081e56603.bbd1b5533384d261.da13bd35b99a115b.324df86124defda9
+ 3cb16355b237d58a.b70cde6ea1be22f5.e86dc02c8e746556.5e733c6311b9c1ce
+ 42d5cab1a6342c3c
+ after
+ 3f91c7fbd87b61f4.449488310b52ce29.8d2e70585f4d6764.92875b8dd4d6768d
+ eb4abeab42007e8a.096d970ee0e4ca01.b0ed77e708e6a619.6218013d4416a223
+ 0000000000000000.0000000000000000.23bf078fa9993eb5.cf90a5b06f402b96
+ 3cb16355b237d58a.b70cde6ea1be22f5.e86dc02c8e746556.5e733c6311b9c1ce
+ 42d5cab1a6342c3c
+
+VPSUBD_128(reg)
+ before
+ 3ac19db680d9779f.9af70926f001874c.5a690fcac51cf568.b4c7fcb9a1805e35
+ a281b1de3a37e1a4.42afe12f584f3875.fe3643d33b2c8967.1becebc911cab825
+ d663029571d7a4f7.0ea5675c052da330.01bd76f5a17a189d.f9aa0b46f85f2e51
+ 31b18c47c047fd44.dba5189913a885aa.bd4ba49c9090deb7.2bcbd61e724a7de6
+ 8b1cca3c9c986110
+ after
+ 0000000000000000.0000000000000000.fc78ccde99b270ca.2242e083196b89d4
+ a281b1de3a37e1a4.42afe12f584f3875.fe3643d33b2c8967.1becebc911cab825
+ d663029571d7a4f7.0ea5675c052da330.01bd76f5a17a189d.f9aa0b46f85f2e51
+ 31b18c47c047fd44.dba5189913a885aa.bd4ba49c9090deb7.2bcbd61e724a7de6
+ 8b1cca3c9c986110
+VPSUBD_128(mem)
+ before
+ f669638c915495fa.11b84c60c4122835.857b6ed39fcb990e.8f2cca34a6fc1861
+ 487e1bfa6e8ad7d1.d1c33d4d18c56079.e8f2e7f4c5a39d89.d3ace2297e4a0346
+ 5d2770724e47e1c0.cd205b7859ebe2ba.e0d7feea9f3b4b47.e617eae8b504d813
+ 112fdde04d966ff4.6019a24f2210eaa5.49f6309f4c9f6073.22b8dddbe7b8d674
+ e4ddb870aff23714
+ after
+ f669638c915495fa.11b84c60c4122835.857b6ed39fcb990e.8f2cca34a6fc1861
+ 487e1bfa6e8ad7d1.d1c33d4d18c56079.e8f2e7f4c5a39d89.d3ace2297e4a0346
+ 0000000000000000.0000000000000000.6377792125d8047b.448017f5d74deae5
+ 112fdde04d966ff4.6019a24f2210eaa5.49f6309f4c9f6073.22b8dddbe7b8d674
+ e4ddb870aff23714
+
+VPADDD_128(reg)
+ before
+ 88d07511a93d389f.4064de3088833f99.e8fc0e3c10c0b4e5.ff1bf701e6dc973a
+ 6ade122c722514c2.c690f04f1b1a0bda.bf139cadbe887b27.de12d1fb89fdadc7
+ e6538a2ca5360929.7f808d2721688fe4.43ab470dc8f37c17.c2a73979520e5e47
+ 587bd97ddffd5180.470033a6b67989e2.cf100bc8cb8ef360.87a5ab675c1c66e6
+ 09daa4b1c43280cf
+ after
+ 0000000000000000.0000000000000000.02bee3ba877bf73e.a0ba0b74dc0c0c0e
+ 6ade122c722514c2.c690f04f1b1a0bda.bf139cadbe887b27.de12d1fb89fdadc7
+ e6538a2ca5360929.7f808d2721688fe4.43ab470dc8f37c17.c2a73979520e5e47
+ 587bd97ddffd5180.470033a6b67989e2.cf100bc8cb8ef360.87a5ab675c1c66e6
+ 09daa4b1c43280cf
+VPADDD_128(mem)
+ before
+ 24109e43a55c692f.1ca1fc8bbb052971.fadc5db6f757b301.be8de54a63e41bae
+ b41417091ca6dd31.8e13eec2d6daccab.73e087450010ca6d.6d70cfff2b8131af
+ 94b28af0441e9802.0a1bab8ecb0977d8.90d72e3eecb08a51.3903c753bff2710c
+ a2b674e239cd55ce.ec062f5c361d66a5.2c8ecc8dd741aeda.7c94c8b2bcc21774
+ 946dce88bd7d5e91
+ after
+ 24109e43a55c692f.1ca1fc8bbb052971.fadc5db6f757b301.be8de54a63e41bae
+ b41417091ca6dd31.8e13eec2d6daccab.73e087450010ca6d.6d70cfff2b8131af
+ 0000000000000000.0000000000000000.6ebce4fbf7687d6e.2bfeb5498f654d5d
+ a2b674e239cd55ce.ec062f5c361d66a5.2c8ecc8dd741aeda.7c94c8b2bcc21774
+ 946dce88bd7d5e91
+
+VPADDD_128(reg)
+ before
+ dbdbd6425fb08310.b9eb4fcd18c1d1c0.90207696b4a3d5bd.23d2df1eded1f333
+ ae29da4a3de6c29c.b51f999bfd05c804.51b57daae126ffcd.506de3dd1c6c1589
+ 6aa5d80ef4ab56e2.711ccd3a03a5f5c8.8d113e0258322281.912b52b6ae1cd007
+ 6999cbf91f8c7c8d.cbaf679546ae1536.9f7fb70cb5537784.c1daa995aff0dfdb
+ bb4565673cf1ff2e
+ after
+ 0000000000000000.0000000000000000.dec6bbac3959224e.e1993693ca88e590
+ ae29da4a3de6c29c.b51f999bfd05c804.51b57daae126ffcd.506de3dd1c6c1589
+ 6aa5d80ef4ab56e2.711ccd3a03a5f5c8.8d113e0258322281.912b52b6ae1cd007
+ 6999cbf91f8c7c8d.cbaf679546ae1536.9f7fb70cb5537784.c1daa995aff0dfdb
+ bb4565673cf1ff2e
+VPADDD_128(mem)
+ before
+ 5d370116702dec2f.0853b0775b14704a.9da4e398e32be47a.e34de43395163d83
+ 817df99068af6108.a31d81f443cf6ec5.c5c7be2ff6281ec1.b4c5bfe29406ae29
+ 05e3cabf3f831be5.96443cdc744ab1a9.1ee373469ab27e37.703446874db00723
+ c335ef9111b6d6f3.3e14dc9b891076a3.83c67ec9ebd4c107.72e6748d5c9f841d
+ 152745615e5f60c2
+ after
+ 5d370116702dec2f.0853b0775b14704a.9da4e398e32be47a.e34de43395163d83
+ 817df99068af6108.a31d81f443cf6ec5.c5c7be2ff6281ec1.b4c5bfe29406ae29
+ 0000000000000000.0000000000000000.636ca1c7d954033b.9813a415291cebac
+ c335ef9111b6d6f3.3e14dc9b891076a3.83c67ec9ebd4c107.72e6748d5c9f841d
+ 152745615e5f60c2
+
+VPADDD_128(reg)
+ before
+ b742b56dee7dd8be.993fe3f1fc534e5e.f5d85d9d1fadf95e.d23a5ba4069aa35e
+ b285c11ea98428bf.61cd25cb19673e51.18debc4ed1ae7687.e50c87c40611df68
+ 643a63e12a008c6e.f9aa2e0b86fc63f9.0370f31b3b9e28ca.99087c1308443250
+ 27ae99200e7d3f7a.3ba37b9d5e207981.12db006efa0a4cd2.cbfab87f27405842
+ 55aeb7f380100d6c
+ after
+ 0000000000000000.0000000000000000.1c4faf690d4c9f51.7e1503d70e5611b8
+ b285c11ea98428bf.61cd25cb19673e51.18debc4ed1ae7687.e50c87c40611df68
+ 643a63e12a008c6e.f9aa2e0b86fc63f9.0370f31b3b9e28ca.99087c1308443250
+ 27ae99200e7d3f7a.3ba37b9d5e207981.12db006efa0a4cd2.cbfab87f27405842
+ 55aeb7f380100d6c
+VPADDD_128(mem)
+ before
+ 14f0f35a2ec00cf7.592d5e49f0887e8d.0484896dbedf3b16.a16bdeb5a97c1d4c
+ e58beaa24e5c1212.5403afc76dad8554.3119d367c24466e4.0c6c8a5ae583d9e3
+ a24c16b6fbf1dbe7.767b860520768f7a.9c2ed578855bb616.ae2afecb4aa8ba44
+ 28fff582518a22a3.19e3e171a571d9ac.228f0c8a2330e7d9.e5f138737379fd1b
+ 0c0c33befc81dd13
+ after
+ 14f0f35a2ec00cf7.592d5e49f0887e8d.0484896dbedf3b16.a16bdeb5a97c1d4c
+ e58beaa24e5c1212.5403afc76dad8554.3119d367c24466e4.0c6c8a5ae583d9e3
+ 0000000000000000.0000000000000000.359e5cd48123a1fa.add8690f8efff72f
+ 28fff582518a22a3.19e3e171a571d9ac.228f0c8a2330e7d9.e5f138737379fd1b
+ 0c0c33befc81dd13
+
+VPMOVZXBW_128(reg)
+ before
+ 7fc8eb18824c97d9.537003f26d34a471.9a85bb76992a9f95.9f07f28bb9d0b459
+ 9a715ceda0676718.006bbaf36bfa1d7e.56ae1180982b1de2.f06405666247dac1
+ b95383a9f35e897d.09bc986f66e849f5.a7abddfb3d028e3f.ef70c0063b9f153d
+ 37ba5bb916bb38b3.4b2e18537a0be303.eac51d54243b2f57.79f8a0595fe620fa
+ 6ac81f4aeb27b924
+ after
+ 7fc8eb18824c97d9.537003f26d34a471.9a85bb76992a9f95.9f07f28bb9d0b459
+ 0000000000000000.0000000000000000.00ef007000c00006.003b009f0015003d
+ b95383a9f35e897d.09bc986f66e849f5.a7abddfb3d028e3f.ef70c0063b9f153d
+ 37ba5bb916bb38b3.4b2e18537a0be303.eac51d54243b2f57.79f8a0595fe620fa
+ 6ac81f4aeb27b924
+VPMOVZXBW_128(mem)
+ before
+ 9eabbbc5fa6f9ae7.72f2e087a50cb268.a28eb68cc46da8d4.7b4bccf5ea603cd7
+ f16fefb7a8c97f6e.c5460e803edc3045.eaa8ee045f1d5493.b688e64c2bfff06a
+ 3fde370a134126e5.8b04e2117ab8f1f9.ff483da96824a36d.f8c767c382a489bd
+ 64c60fab54e44979.227656a5f72b2f2d.bd3a1d66fb90508d.9b554cc88bd9417c
+ fc7e90c6e32d5452
+ after
+ 9eabbbc5fa6f9ae7.72f2e087a50cb268.a28eb68cc46da8d4.7b4bccf5ea603cd7
+ 0000000000000000.0000000000000000.007b004b00cc00f5.00ea0060003c00d7
+ 3fde370a134126e5.8b04e2117ab8f1f9.ff483da96824a36d.f8c767c382a489bd
+ 64c60fab54e44979.227656a5f72b2f2d.bd3a1d66fb90508d.9b554cc88bd9417c
+ fc7e90c6e32d5452
+
+VPMOVZXBW_128(reg)
+ before
+ 778e2f28252900ec.3cf1f48789bda456.e4e968a851c12790.004a0c27326d1820
+ 68d1255cee5b7ff5.a32c6188ced8f5a8.2fa91385230615cc.a44486d82cc5b652
+ 2b936fcdd94e0d1a.7542d29c3e42f699.5d0154aa0987348e.85f3056502a6e84e
+ 1c1f07e7838ee807.8d01c3adf5066458.cc3f2583a0d0c181.7e2407bad31b6840
+ 6da307c3b831f356
+ after
+ 778e2f28252900ec.3cf1f48789bda456.e4e968a851c12790.004a0c27326d1820
+ 0000000000000000.0000000000000000.008500f300050065.000200a600e8004e
+ 2b936fcdd94e0d1a.7542d29c3e42f699.5d0154aa0987348e.85f3056502a6e84e
+ 1c1f07e7838ee807.8d01c3adf5066458.cc3f2583a0d0c181.7e2407bad31b6840
+ 6da307c3b831f356
+VPMOVZXBW_128(mem)
+ before
+ 2d3c816dcff344ba.97c2eb1787a84a67.c934b1a91030fb0f.d6ad847a846bf852
+ 9abbf1a2346d1898.f8c916c7812770e7.04a6167baacd76eb.d9986cfc4fe615ac
+ 8febd45002ac2b1d.9a7e85640e989632.1a24700fe0e89217.2f4cd975a0cd533c
+ ea9aa46156bb3975.db2d325bca86f7f5.e67a3a51cd8d0bc0.3515c85211aaefae
+ 483f33fd3e0b25ad
+ after
+ 2d3c816dcff344ba.97c2eb1787a84a67.c934b1a91030fb0f.d6ad847a846bf852
+ 0000000000000000.0000000000000000.00d600ad0084007a.0084006b00f80052
+ 8febd45002ac2b1d.9a7e85640e989632.1a24700fe0e89217.2f4cd975a0cd533c
+ ea9aa46156bb3975.db2d325bca86f7f5.e67a3a51cd8d0bc0.3515c85211aaefae
+ 483f33fd3e0b25ad
+
+VPMOVZXBW_128(reg)
+ before
+ c21618e4c47c30e6.8692dfc34ba7fecb.16241b16507dd0dc.4674f12d8ec99d12
+ 00e572723e874e05.3ea00061fd7a354c.a7ae3b033c095d92.15de0f903ea70338
+ 5efa3e1249bab9b5.f090842789429a24.ea168e8d2bb7dac4.2e831264fa33fa5f
+ 399f763280a1ada2.772ee5010a0beb7e.3aa91120b912821d.6f307597dd7a3eb2
+ b2b2b41304878a5e
+ after
+ c21618e4c47c30e6.8692dfc34ba7fecb.16241b16507dd0dc.4674f12d8ec99d12
+ 0000000000000000.0000000000000000.002e008300120064.00fa003300fa005f
+ 5efa3e1249bab9b5.f090842789429a24.ea168e8d2bb7dac4.2e831264fa33fa5f
+ 399f763280a1ada2.772ee5010a0beb7e.3aa91120b912821d.6f307597dd7a3eb2
+ b2b2b41304878a5e
+VPMOVZXBW_128(mem)
+ before
+ d5d34cc68a669b8e.eb21183d7fc6677a.ae46a1db9de0e287.f5b3be2881a7924a
+ b260b79b8c242d6f.d1cb1fa0e3b724e6.73a333a15ecd3c6a.768093111f0146f6
+ 2724737d25ccfc2d.47eb87c548001d95.a012183f67deb554.185c8b4730acd9cf
+ 0eedfb5a716bc3f3.a9cc4d19492c9131.135fcaa2d7200870.3993a3364f35887e
+ 3370d54b19268fb2
+ after
+ d5d34cc68a669b8e.eb21183d7fc6677a.ae46a1db9de0e287.f5b3be2881a7924a
+ 0000000000000000.0000000000000000.00f500b300be0028.008100a70092004a
+ 2724737d25ccfc2d.47eb87c548001d95.a012183f67deb554.185c8b4730acd9cf
+ 0eedfb5a716bc3f3.a9cc4d19492c9131.135fcaa2d7200870.3993a3364f35887e
+ 3370d54b19268fb2
+
+VPMOVZXWD_128(reg)
+ before
+ 64401ff0290e2a14.4585cc1d8d0b3fee.53b96b0882c7ba66.a657c7b4c89ef3eb
+ 264f7c931c769453.a6ba60b395bb2c4a.a1ffdfff905dd5e1.36c38a63566430f1
+ d7e9e89e8dec0a19.0e563506a4844532.efeaa4680f7b1e4e.a0728f9a9d7f7bad
+ d15a5f7f19fcc813.5a26c603d67447d2.99c6b7b19aacd059.be2f5244bbfa914c
+ 6dc5504fc9e22efa
+ after
+ 64401ff0290e2a14.4585cc1d8d0b3fee.53b96b0882c7ba66.a657c7b4c89ef3eb
+ 0000000000000000.0000000000000000.0000a07200008f9a.00009d7f00007bad
+ d7e9e89e8dec0a19.0e563506a4844532.efeaa4680f7b1e4e.a0728f9a9d7f7bad
+ d15a5f7f19fcc813.5a26c603d67447d2.99c6b7b19aacd059.be2f5244bbfa914c
+ 6dc5504fc9e22efa
+VPMOVZXWD_128(mem)
+ before
+ 8a0104a6e5420ee2.71eedea15b3009ec.64f68f964896ee58.fbdf1245cd7c28ad
+ efafea352b26ed30.14f06070ef160a51.09910dac15f7f6ed.7180b390457862f6
+ 799b7ee8b69b8611.14aee158723907ed.25c5ba305aa11ac0.56f795fe9d2bb9e1
+ 04913caca2ab96b1.ce725dc580263c6d.955c140d32a317fb.088eb4fb72226b1a
+ e2920cf35fe8b24c
+ after
+ 8a0104a6e5420ee2.71eedea15b3009ec.64f68f964896ee58.fbdf1245cd7c28ad
+ 0000000000000000.0000000000000000.0000fbdf00001245.0000cd7c000028ad
+ 799b7ee8b69b8611.14aee158723907ed.25c5ba305aa11ac0.56f795fe9d2bb9e1
+ 04913caca2ab96b1.ce725dc580263c6d.955c140d32a317fb.088eb4fb72226b1a
+ e2920cf35fe8b24c
+
+VPMOVZXWD_128(reg)
+ before
+ 404f9a520109ca24.6c5da16b0c65d83c.9f89d123b468e47d.33239631ba06a9ca
+ 7e115984f311f14e.8dca281210d20add.e13f38deaa8c3cc8.dce6bd870dd88b5b
+ f72445f6d28d6175.43a54d8ec900e6c0.f1df8d62ff1c80fb.6c7103fb48247bd7
+ 09d35a1239095746.6abb8cca53fa2913.2bb7cf1c4fa6ebc1.bf90e67986f7336d
+ b10fe1ede45c6f47
+ after
+ 404f9a520109ca24.6c5da16b0c65d83c.9f89d123b468e47d.33239631ba06a9ca
+ 0000000000000000.0000000000000000.00006c71000003fb.0000482400007bd7
+ f72445f6d28d6175.43a54d8ec900e6c0.f1df8d62ff1c80fb.6c7103fb48247bd7
+ 09d35a1239095746.6abb8cca53fa2913.2bb7cf1c4fa6ebc1.bf90e67986f7336d
+ b10fe1ede45c6f47
+VPMOVZXWD_128(mem)
+ before
+ 1eb970437d5fed91.0e6b9546c50f0e6c.ded662b1cbcd8eff.eb11f77635b6bac7
+ e25b0f686d0d6779.6438f0fd112dc394.7bc24a314c84d2b3.8e3b03de4dd629b9
+ d9c13b46d1719928.668669a2b9eeb269.1d4dc035f32bb159.6e7fedbf34947442
+ dfb76fcbc59741cd.6fa1fba35adf1799.a04240a9dbcfe71d.e82ab385857cd60f
+ 5887519cdd198ccb
+ after
+ 1eb970437d5fed91.0e6b9546c50f0e6c.ded662b1cbcd8eff.eb11f77635b6bac7
+ 0000000000000000.0000000000000000.0000eb110000f776.000035b60000bac7
+ d9c13b46d1719928.668669a2b9eeb269.1d4dc035f32bb159.6e7fedbf34947442
+ dfb76fcbc59741cd.6fa1fba35adf1799.a04240a9dbcfe71d.e82ab385857cd60f
+ 5887519cdd198ccb
+
+VPMOVZXWD_128(reg)
+ before
+ 1ae4c170d7f7d223.d00927e1648c1992.ddd5a36b908b2ecd.e06c4679217b2f2c
+ 8a8b016d0fa2e4c3.8783df76ca5bdea3.0a6e5b66f67e32b4.b9984f91e03b46b2
+ 03ca0cff23a7fd56.e2f0137514104c2d.54b72101284560f7.0792d6dd351ce8da
+ e3ebde92ac915a89.bc1d40ca5db81e5c.15fdf0a6c36bf345.a626574a3b29d1d1
+ 71204ec20f6ebcc3
+ after
+ 1ae4c170d7f7d223.d00927e1648c1992.ddd5a36b908b2ecd.e06c4679217b2f2c
+ 0000000000000000.0000000000000000.000007920000d6dd.0000351c0000e8da
+ 03ca0cff23a7fd56.e2f0137514104c2d.54b72101284560f7.0792d6dd351ce8da
+ e3ebde92ac915a89.bc1d40ca5db81e5c.15fdf0a6c36bf345.a626574a3b29d1d1
+ 71204ec20f6ebcc3
+VPMOVZXWD_128(mem)
+ before
+ 464b3833ccf866db.853b739348ed3707.f1d7e161c25e115b.aa8cc4c2627c2848
+ 007590878ed28b46.4506c86c9345cf7d.5ce872265f0ee157.70b09ac2a2053bad
+ 7a68d2ac7208e62f.7f97d88b28285f97.db1c70054ed54a7c.c1b56d101e91681f
+ 92f17a8d94a734c3.8f3c9f5aa31f2300.494155eaaebe07f5.fae7381a73aceb4b
+ 7791fa4a3ce3ffdc
+ after
+ 464b3833ccf866db.853b739348ed3707.f1d7e161c25e115b.aa8cc4c2627c2848
+ 0000000000000000.0000000000000000.0000aa8c0000c4c2.0000627c00002848
+ 7a68d2ac7208e62f.7f97d88b28285f97.db1c70054ed54a7c.c1b56d101e91681f
+ 92f17a8d94a734c3.8f3c9f5aa31f2300.494155eaaebe07f5.fae7381a73aceb4b
+ 7791fa4a3ce3ffdc
+
+VPBLENDVB_128(reg)
+ before
+ 9500ac0e16c1e17f.23dc04160fba312e.d03f1947a1b85665.81229fc298d5d5ef
+ ae804bd19cd2cce0.08f5ed33ff4d999b.a0ed42bdbe7e3671.618ac9772a277095
+ 1f5dd4ff6ba3feaa.1f08b0d0816d2736.5a93172895fefdd1.c4464ff780bf9314
+ 44e342041ebfb18a.42e0c9d9b025982d.597a93f4c2c3e730.8522ae2cb5a9fb97
+ 82ea6004e6f2644c
+ after
+ 0000000000000000.0000000000000000.a0ed172895fefd71.c48a4f7780bf9314
+ ae804bd19cd2cce0.08f5ed33ff4d999b.a0ed42bdbe7e3671.618ac9772a277095
+ 1f5dd4ff6ba3feaa.1f08b0d0816d2736.5a93172895fefdd1.c4464ff780bf9314
+ 44e342041ebfb18a.42e0c9d9b025982d.597a93f4c2c3e730.8522ae2cb5a9fb97
+ 82ea6004e6f2644c
+VPBLENDVB_128(mem)
+ before
+ 956ae36a2ea58a5c.795e914d51b2222b.4f4ab43ba982a8aa.fbf1b28de259323c
+ 9b6eb24aa9cf28f5.1a19be44a1098c3a.2013ede0878f12d9.9a437060904c189e
+ 71c14a90747bfb43.8362c356aa4f2c63.9305f1b5675893e7.94bbcad76929d605
+ f1302528abb5bf72.10839ef007103e51.82ec3ba764e9e700.44a6bb5f087ca71a
+ 05513f650acfc98c
+ after
+ 956ae36a2ea58a5c.795e914d51b2222b.4f4ab43ba982a8aa.fbf1b28de259323c
+ 9b6eb24aa9cf28f5.1a19be44a1098c3a.2013ede0878f12d9.9a437060904c189e
+ 0000000000000000.0000000000000000.4f4aed3b8782a8d9.9af1b260904c329e
+ f1302528abb5bf72.10839ef007103e51.82ec3ba764e9e700.44a6bb5f087ca71a
+ 05513f650acfc98c
+
+VPBLENDVB_128(reg)
+ before
+ 340652530ab07605.f987c1fe69892fad.1dc94a7c54d9feb1.ca9647a19b4fca4f
+ 2e11f097a5aaea32.639299ffca040820.0680c4682e35a72e.48ce928e2795f701
+ 4dc0169c764a63be.0c1d2915eb3106f9.27f4061f31b17675.d65f965c25c82b41
+ ef5ebfce191b1b56.d0f4ee2ee71de562.dc700e0df7d8a732.5116d1f6b0f2223c
+ 95bfbe48e522971e
+ after
+ 0000000000000000.0000000000000000.2780c46831b1762e.48ce965c25c8f701
+ 2e11f097a5aaea32.639299ffca040820.0680c4682e35a72e.48ce928e2795f701
+ 4dc0169c764a63be.0c1d2915eb3106f9.27f4061f31b17675.d65f965c25c82b41
+ ef5ebfce191b1b56.d0f4ee2ee71de562.dc700e0df7d8a732.5116d1f6b0f2223c
+ 95bfbe48e522971e
+VPBLENDVB_128(mem)
+ before
+ 7e26d93edf614712.6e36e7992ba94fa5.8ce26234dbd36087.8142d79e1f367610
+ e9179fc5babdee45.27958a6948813a58.1ab50315e25f3495.72b45d3e43571ebc
+ b05e8ac7934148e2.76c7a4aa0b2e1a1b.57374cbc19cd1db8.0a139d59ffc8dce1
+ b0c6183186fa1016.b81832c8103c2999.1f35b9149b2ad61b.a7ab915bef14eb2c
+ a4c837b0b1c88948
+ after
+ 7e26d93edf614712.6e36e7992ba94fa5.8ce26234dbd36087.8142d79e1f367610
+ e9179fc5babdee45.27958a6948813a58.1ab50315e25f3495.72b45d3e43571ebc
+ 0000000000000000.0000000000000000.1ab56215db5f6095.8142d73e1f5776bc
+ b0c6183186fa1016.b81832c8103c2999.1f35b9149b2ad61b.a7ab915bef14eb2c
+ a4c837b0b1c88948
+
+VPBLENDVB_128(reg)
+ before
+ 5db58ac5de6ff0e2.c51cc4f0adf3030d.47d42f30f438a37f.4e7bc70b85821deb
+ 2dc0860414955da6.cb2d0bef2738ddf2.8046974c53adc678.c0d4f18df2dfac53
+ 723328dbefc60b40.9ec367190ed65af2.bfbc678ac728cc31.510eb384ff4f3f80
+ 865b6ab40a8f385a.1aaa565c7ed83538.60809954ef33f256.ddf389ddc7dd949e
+ 4051ef84669665d8
+ after
+ 0000000000000000.0000000000000000.80bc674cc7adcc78.510eb384ff4f3f80
+ 2dc0860414955da6.cb2d0bef2738ddf2.8046974c53adc678.c0d4f18df2dfac53
+ 723328dbefc60b40.9ec367190ed65af2.bfbc678ac728cc31.510eb384ff4f3f80
+ 865b6ab40a8f385a.1aaa565c7ed83538.60809954ef33f256.ddf389ddc7dd949e
+ 4051ef84669665d8
+VPBLENDVB_128(mem)
+ before
+ 56f26266f9856e5b.c7844afd027c1ea3.1bb053a3944a2bf1.bfdf2b18655c7492
+ fba35d6d9cb66d52.8ffac4217217f9c5.7da0dada6b38f749.38251841c52f8d92
+ 0b305c876a361cea.3c09d28cf6ee076d.1c4568ed20af576b.279e5c3bac377a01
+ 6264db9f7f10384e.28fc72aa2b8c8246.d46c77c8cebb0584.e895f472b500778c
+ d758db527c16bfdf
+ after
+ 56f26266f9856e5b.c7844afd027c1ea3.1bb053a3944a2bf1.bfdf2b18655c7492
+ fba35d6d9cb66d52.8ffac4217217f9c5.7da0dada6b38f749.38251841c52f8d92
+ 0000000000000000.0000000000000000.1ba0daa3944af7f1.bfdf2b41652f8d92
+ 6264db9f7f10384e.28fc72aa2b8c8246.d46c77c8cebb0584.e895f472b500778c
+ d758db527c16bfdf
+
+VPMINSD_128(reg)
+ before
+ 50310c479f0690a5.db0d56a0f8507dac.b1219ee7ac7ea7fd.80e185589266bebf
+ af6d86beb75b248b.54f54a78f103a62d.31c254b0164fb13d.fe700d8787be3d49
+ 5058422162a1b73c.a8e9321284347000.062c906f058bdeb3.29e58c42c9cf3f4e
+ 8f3e3dde3c658765.b3b58a5ad0ef974f.8aab4c9113bf680b.dd0b7c7675a380f9
+ f5b05b0ea749bc77
+ after
+ 0000000000000000.0000000000000000.062c906f058bdeb3.fe700d8787be3d49
+ af6d86beb75b248b.54f54a78f103a62d.31c254b0164fb13d.fe700d8787be3d49
+ 5058422162a1b73c.a8e9321284347000.062c906f058bdeb3.29e58c42c9cf3f4e
+ 8f3e3dde3c658765.b3b58a5ad0ef974f.8aab4c9113bf680b.dd0b7c7675a380f9
+ f5b05b0ea749bc77
+VPMINSD_128(mem)
+ before
+ 4f9ea4f57acaaff3.c86b745fe032ceb2.5025ce3def41d746.1a8b8683df768bf0
+ c6a2d3190a34149a.562ae212ea95c9ce.5d057ba5fd35eb12.131739b0023c850f
+ 358865657492a797.97c98362f719b366.b4200c7f16d790df.cf9d61831b9e9014
+ 7a1cd4c5d4f02617.e69254baa34ac925.3344fdb8583482d8.ab67fa6ac327e9aa
+ 03c201d09963cc7d
+ after
+ 4f9ea4f57acaaff3.c86b745fe032ceb2.5025ce3def41d746.1a8b8683df768bf0
+ c6a2d3190a34149a.562ae212ea95c9ce.5d057ba5fd35eb12.131739b0023c850f
+ 0000000000000000.0000000000000000.5025ce3def41d746.131739b0df768bf0
+ 7a1cd4c5d4f02617.e69254baa34ac925.3344fdb8583482d8.ab67fa6ac327e9aa
+ 03c201d09963cc7d
+
+VPMINSD_128(reg)
+ before
+ 33fa702136df743a.6f2a9e25455b4b46.9ed2508889b547b8.b53bca3adc577c2a
+ 975b45c938261e8d.f27d3e71e3ded34f.1dd5723845e469ca.15d2f0f3c04d3b01
+ 8c317c343bc50622.dde23096cb857a5f.bee6b93474666a08.31d5e9ce20207b88
+ 6cc70fcfda4667a4.0e26f17e185dfba2.dc531ee9b1c4881e.e30f33b717def8eb
+ 084e499ac2936d58
+ after
+ 0000000000000000.0000000000000000.bee6b93445e469ca.15d2f0f3c04d3b01
+ 975b45c938261e8d.f27d3e71e3ded34f.1dd5723845e469ca.15d2f0f3c04d3b01
+ 8c317c343bc50622.dde23096cb857a5f.bee6b93474666a08.31d5e9ce20207b88
+ 6cc70fcfda4667a4.0e26f17e185dfba2.dc531ee9b1c4881e.e30f33b717def8eb
+ 084e499ac2936d58
+VPMINSD_128(mem)
+ before
+ 7d5da7633c4a97f9.946bfc04b1377ebf.5f13fc17e7711443.d5669ec3998cfcb7
+ 1c07cafea10f32fa.60673d415d248720.ad75cc4b53ce7f6e.036d362fc7490580
+ c3192d570eeef988.2c08d1f07a98be73.d51ae008797ff851.c4b2e197d888dd25
+ 4c5f4c5a9ef4a9cf.539ab17fa31f5e64.b1cdb13974903c16.72829b6967d4c151
+ 6b29611011b9edb1
+ after
+ 7d5da7633c4a97f9.946bfc04b1377ebf.5f13fc17e7711443.d5669ec3998cfcb7
+ 1c07cafea10f32fa.60673d415d248720.ad75cc4b53ce7f6e.036d362fc7490580
+ 0000000000000000.0000000000000000.ad75cc4be7711443.d5669ec3998cfcb7
+ 4c5f4c5a9ef4a9cf.539ab17fa31f5e64.b1cdb13974903c16.72829b6967d4c151
+ 6b29611011b9edb1
+
+VPMINSD_128(reg)
+ before
+ 09f22df771c49cf0.94a5a3f46e2cfefa.3368da597445a59e.1e59bdc9610d07e9
+ a92bfd8c23800cbb.77b6ae0f9aa3b436.27c049e98a97cccd.f98b7ea65b0315f7
+ a81ecc3ac47977bd.d260ea993c6486ae.8becf99d80a0129e.1c2f72bb7e7d226c
+ 6018976df03c19a3.7f6dd27c737b318f.bb3ae6e0f3edb1bd.641115f5e788e973
+ adfde13eb22f2739
+ after
+ 0000000000000000.0000000000000000.8becf99d80a0129e.f98b7ea65b0315f7
+ a92bfd8c23800cbb.77b6ae0f9aa3b436.27c049e98a97cccd.f98b7ea65b0315f7
+ a81ecc3ac47977bd.d260ea993c6486ae.8becf99d80a0129e.1c2f72bb7e7d226c
+ 6018976df03c19a3.7f6dd27c737b318f.bb3ae6e0f3edb1bd.641115f5e788e973
+ adfde13eb22f2739
+VPMINSD_128(mem)
+ before
+ d3bf5483fa7e97e9.2e65589242542f19.5baae2a658f57105.13f40d1f7e09e6d5
+ b222e9b1db82f7b0.6f510d13564df5ca.42e396020adc013b.ee6768c4be80ed93
+ 26f31cb2724501ba.7d28b15dc9b4a763.10e46b7ca23f9f5e.aadef53c4ede01a3
+ 0cff6974dbd67232.b53540dd3714818f.a179dc003e270599.a2a7aff3cbb05fb0
+ 310d9256d0814367
+ after
+ d3bf5483fa7e97e9.2e65589242542f19.5baae2a658f57105.13f40d1f7e09e6d5
+ b222e9b1db82f7b0.6f510d13564df5ca.42e396020adc013b.ee6768c4be80ed93
+ 0000000000000000.0000000000000000.42e396020adc013b.ee6768c4be80ed93
+ 0cff6974dbd67232.b53540dd3714818f.a179dc003e270599.a2a7aff3cbb05fb0
+ 310d9256d0814367
+
+VPMAXSD_128(reg)
+ before
+ b55b9bd0f9dee973.3e104de1303e0545.73c6b6fd3af9befb.d16e647afaa2ef19
+ 89dec5cce4528c81.98f243e7908b771e.1325102b71f09b53.7c8e82d7f1bb1b0a
+ 08e20cb82a69693c.f873c77114c984ea.f19f49d275845342.7ea6af01407f4397
+ 90b36cff69b0bc51.395e556bdb02e8d5.69805d5de5422475.b38269e502f923ed
+ f7ee2a7053357937
+ after
+ 0000000000000000.0000000000000000.1325102b75845342.7ea6af01407f4397
+ 89dec5cce4528c81.98f243e7908b771e.1325102b71f09b53.7c8e82d7f1bb1b0a
+ 08e20cb82a69693c.f873c77114c984ea.f19f49d275845342.7ea6af01407f4397
+ 90b36cff69b0bc51.395e556bdb02e8d5.69805d5de5422475.b38269e502f923ed
+ f7ee2a7053357937
+VPMAXSD_128(mem)
+ before
+ 26b6708c5040ffa2.7b9de10d3db2c06c.377e69c1fe445e0a.d714483a5ab44897
+ 1ca6b7271525725a.27eb684e40fbb238.cea0805f9c9aa3b6.97a706d47369fc55
+ b489792cbcf08e8a.eeebfb2e1117ce62.da901532ce117304.05849497c9ea7b5b
+ cc2c348764ae0e5f.2ee798194a935096.371aa424b2b48a21.7df8edf0fac50254
+ 5b4f0d49a285cded
+ after
+ 26b6708c5040ffa2.7b9de10d3db2c06c.377e69c1fe445e0a.d714483a5ab44897
+ 1ca6b7271525725a.27eb684e40fbb238.cea0805f9c9aa3b6.97a706d47369fc55
+ 0000000000000000.0000000000000000.377e69c1fe445e0a.d714483a7369fc55
+ cc2c348764ae0e5f.2ee798194a935096.371aa424b2b48a21.7df8edf0fac50254
+ 5b4f0d49a285cded
+
+VPMAXSD_128(reg)
+ before
+ fbd5f10f5cb618d1.3f5c6324276aaf04.412c3b7c87fb737f.c00aa922648fa338
+ b9d693afc5e51ead.e9e382ef21302da6.8406dec165d974c9.532ba119ffaf7b77
+ f09ef193789d1c2d.a58d0dd46f0d4470.54c07f567fbb8f22.cb4b06f4a01fce07
+ fe780629116b4efc.512881bf2c0caf8f.0ba819a5722dff34.0334569e62ec5717
+ d9b30d056120d3d0
+ after
+ 0000000000000000.0000000000000000.54c07f567fbb8f22.532ba119ffaf7b77
+ b9d693afc5e51ead.e9e382ef21302da6.8406dec165d974c9.532ba119ffaf7b77
+ f09ef193789d1c2d.a58d0dd46f0d4470.54c07f567fbb8f22.cb4b06f4a01fce07
+ fe780629116b4efc.512881bf2c0caf8f.0ba819a5722dff34.0334569e62ec5717
+ d9b30d056120d3d0
+VPMAXSD_128(mem)
+ before
+ 2894a514bac9fe61.3eb2cedc2ddaf0c7.c87f599d753a2b2f.0609a81cd9b901ab
+ cba39cb788f394f4.0c96461868763d39.e55d115865a1747b.a12e282651edd134
+ a0ac6cdae8a950b6.c37168495ccc72ff.868f25de184f45a0.3864962f7555ab7b
+ 817a9369f6f7efd2.c18f32dba866cbc4.85e1111aac505bca.28f7eca3e27cca2b
+ cb3328ee33ee6bf1
+ after
+ 2894a514bac9fe61.3eb2cedc2ddaf0c7.c87f599d753a2b2f.0609a81cd9b901ab
+ cba39cb788f394f4.0c96461868763d39.e55d115865a1747b.a12e282651edd134
+ 0000000000000000.0000000000000000.e55d1158753a2b2f.0609a81c51edd134
+ 817a9369f6f7efd2.c18f32dba866cbc4.85e1111aac505bca.28f7eca3e27cca2b
+ cb3328ee33ee6bf1
+
+VPMAXSD_128(reg)
+ before
+ 7e63467c0437ca78.4cda8d51cde92d75.613c9f3ae6d38335.c01f52f73aaf7224
+ 9dd540baf2e4236d.db99d47c898cc5ca.fec3abd2b29cd7fe.11156363e07846db
+ 84d314129980b17c.0c81e6d847eb74fe.f6725310a94f03ca.568fc049bab7921a
+ 8faabdf19497b150.b95e3e4f2212f63d.a393925e66774346.6958e595e379130e
+ 273d4f3377c985e2
+ after
+ 0000000000000000.0000000000000000.fec3abd2b29cd7fe.568fc049e07846db
+ 9dd540baf2e4236d.db99d47c898cc5ca.fec3abd2b29cd7fe.11156363e07846db
+ 84d314129980b17c.0c81e6d847eb74fe.f6725310a94f03ca.568fc049bab7921a
+ 8faabdf19497b150.b95e3e4f2212f63d.a393925e66774346.6958e595e379130e
+ 273d4f3377c985e2
+VPMAXSD_128(mem)
+ before
+ 6d0a790f93b4a3c3.1aa737c47fb65e96.bffe58cf360e07b2.6373642a86a1d21e
+ 158bdf1653442add.81137ef6f768f6f9.fb2cb043a1ea628a.905ec5dea458edfd
+ fc8cfd32d188d65b.203d8ef2973ab326.47b3c3967cb3c4f1.87a0b1e85c28d090
+ fed94f512c89636a.53706426fcb6d2c9.80600cb6e574e912.a58525b34c9eb682
+ 44581cab0d45dc80
+ after
+ 6d0a790f93b4a3c3.1aa737c47fb65e96.bffe58cf360e07b2.6373642a86a1d21e
+ 158bdf1653442add.81137ef6f768f6f9.fb2cb043a1ea628a.905ec5dea458edfd
+ 0000000000000000.0000000000000000.fb2cb043360e07b2.6373642aa458edfd
+ fed94f512c89636a.53706426fcb6d2c9.80600cb6e574e912.a58525b34c9eb682
+ 44581cab0d45dc80
+
+VANDPD_128(reg)
+ before
+ c266923c3da97e35.f83d525d7e558c35.75f7fbfdc26b8e8d.82ff078ef8398c19
+ 79fc83d27857d84e.c4868144e3f70ee9.e41f4fe383e2241e.2a5c300bd00e6a34
+ c664ecd959da2577.3f7e58f1787ca5b2.fb345d44dea9d02a.5243041789003f8c
+ 05eac7bd7cbea25b.45f2535058ef0cbb.16821f8d6c4bce5b.d780fd9f401bc750
+ 95de99901169bdaa
+ after
+ 0000000000000000.0000000000000000.e0144d4082a0000a.0240000380002a04
+ 79fc83d27857d84e.c4868144e3f70ee9.e41f4fe383e2241e.2a5c300bd00e6a34
+ c664ecd959da2577.3f7e58f1787ca5b2.fb345d44dea9d02a.5243041789003f8c
+ 05eac7bd7cbea25b.45f2535058ef0cbb.16821f8d6c4bce5b.d780fd9f401bc750
+ 95de99901169bdaa
+VANDPD_128(mem)
+ before
+ 682a53d417f8dec6.93dc12ea7e908ba7.b2aeef4d9f5c0131.90559328cc55595d
+ 2c31a8596ed3e6d2.ca85c8cdfadb1b06.627ea6d46bcf3e3f.c7f9b4829752aedd
+ bdbd1209330791f7.0730e6d18d2b9025.312df6d1d5557f12.16b97f086bce0987
+ f79a0fd2819f9a64.a62a6661d30d24b0.fb895a30fbfa82d6.d8e3ee24e455a606
+ 6bc1ff449d74c007
+ after
+ 682a53d417f8dec6.93dc12ea7e908ba7.b2aeef4d9f5c0131.90559328cc55595d
+ 2c31a8596ed3e6d2.ca85c8cdfadb1b06.627ea6d46bcf3e3f.c7f9b4829752aedd
+ 0000000000000000.0000000000000000.222ea6440b4c0031.805190008450085d
+ f79a0fd2819f9a64.a62a6661d30d24b0.fb895a30fbfa82d6.d8e3ee24e455a606
+ 6bc1ff449d74c007
+
+VANDPD_128(reg)
+ before
+ 2aa0add332b69436.b6961a9f75a7be43.03bf46eb660c1352.9c5c4fddf9c801b6
+ 70ccf43d40a85e3e.d67caf5c2a2cb8c0.7a3b81dae5b59bb8.f0734fc5eacdb8df
+ 9b90d0ee63d559cc.33174bf5bd394609.67ea149ae992f68d.d39ad8d2ea14657c
+ 053a3e5236c9c28b.a934685649da2247.2618f9971131607e.219d65f216aac2ba
+ b64773108a9a8cc5
+ after
+ 0000000000000000.0000000000000000.622a009ae1909288.d01248c0ea04205c
+ 70ccf43d40a85e3e.d67caf5c2a2cb8c0.7a3b81dae5b59bb8.f0734fc5eacdb8df
+ 9b90d0ee63d559cc.33174bf5bd394609.67ea149ae992f68d.d39ad8d2ea14657c
+ 053a3e5236c9c28b.a934685649da2247.2618f9971131607e.219d65f216aac2ba
+ b64773108a9a8cc5
+VANDPD_128(mem)
+ before
+ 6d667c1861f07fc8.0b1439d55511d528.139f846ceb1c09a9.13102e3df61e1737
+ 24c4fef6b7b956f0.0a6cbde35d38ce4e.4f241a21be0ab659.8a20aef836e45563
+ b62e7496a900ce68.5c8cc6e9eacae8aa.388fa662dfb0e683.e79275346d0f57af
+ ff705ae452d2a35d.5fc15051965460e8.aaaba51c691b5554.86b37f5e362b59c6
+ c2cfc9e02ec59655
+ after
+ 6d667c1861f07fc8.0b1439d55511d528.139f846ceb1c09a9.13102e3df61e1737
+ 24c4fef6b7b956f0.0a6cbde35d38ce4e.4f241a21be0ab659.8a20aef836e45563
+ 0000000000000000.0000000000000000.03040020aa080009.02002e3836041523
+ ff705ae452d2a35d.5fc15051965460e8.aaaba51c691b5554.86b37f5e362b59c6
+ c2cfc9e02ec59655
+
+VANDPD_128(reg)
+ before
+ f9314d28f0684b08.da562ccccf3991fb.6d565889006172b3.8046923a7856bff8
+ 862709a118a1b48a.25ac673a3b43536d.e399d9fbc17d59b8.982ae9a7296ddf9a
+ c5fbf9b643fb0d88.bb3d861ab3fca6df.1dd4cf15783553a2.cd242651986d7367
+ 11fa17d50d0291ad.77d70559526e467f.78553642be14991f.fa00c523e061348b
+ fd8a43091d55e131
+ after
+ 0000000000000000.0000000000000000.0190c911403551a0.88202001086d5302
+ 862709a118a1b48a.25ac673a3b43536d.e399d9fbc17d59b8.982ae9a7296ddf9a
+ c5fbf9b643fb0d88.bb3d861ab3fca6df.1dd4cf15783553a2.cd242651986d7367
+ 11fa17d50d0291ad.77d70559526e467f.78553642be14991f.fa00c523e061348b
+ fd8a43091d55e131
+VANDPD_128(mem)
+ before
+ b08e1bef6c563485.c870616910427da6.374460e135a7ee77.4e660bee31a66ad8
+ f1d7c9c2e86feab5.45a9d2deeb480d1e.d55113a077b35bf3.fc5449856d78007b
+ 9a32c96caeadbfeb.e3f166a038a07cc2.2fca9b81349d4920.de6bec730d1599b4
+ 896c98dad91a6e53.0094191c93d4073e.1f7b73708971742a.50f6f024ae096e2f
+ ae435104ebe1be97
+ after
+ b08e1bef6c563485.c870616910427da6.374460e135a7ee77.4e660bee31a66ad8
+ f1d7c9c2e86feab5.45a9d2deeb480d1e.d55113a077b35bf3.fc5449856d78007b
+ 0000000000000000.0000000000000000.154000a035a34a73.4c44098421200058
+ 896c98dad91a6e53.0094191c93d4073e.1f7b73708971742a.50f6f024ae096e2f
+ ae435104ebe1be97
+
+VMULPD_256(reg)
+ before
+ 549c0c806028c398.984fb0f986c5b51a.f6dde8bc9972ea3d.832f1759923b973c
+ 9e4e1c02aa6bbadf.a5a78fb3d0b74d6c.2319cdede505606c.35b403286a086f83
+ e8a57df86534df18.8a42b0f6d4fef574.e194c61c141aa777.12d4b4c92de3b82a
+ 8eed2bcc2c126dee.24eb90adada5675f.8e9acfb3c13cf909.f75ca528f8d92d5e
+ be185231e7f58b4b
+ after
+ 470438e8e28f380f.0000000000000000.c4c0c0758382c8f8.0899e611ac44d325
+ 9e4e1c02aa6bbadf.a5a78fb3d0b74d6c.2319cdede505606c.35b403286a086f83
+ e8a57df86534df18.8a42b0f6d4fef574.e194c61c141aa777.12d4b4c92de3b82a
+ 8eed2bcc2c126dee.24eb90adada5675f.8e9acfb3c13cf909.f75ca528f8d92d5e
+ be185231e7f58b4b
+VMULPD_256(mem)
+ before
+ 44d437d115438e1c.ec7223ec9b8ea10e.4f6da9c478b96058.8477e22088f793cf
+ 655bd0f29ecff2fe.5e7f5fc34f36b724.e895792750449c8c.2177fdce06d8b074
+ fe7b9a829fa6721d.4062ddbde395eadb.c92f7bc25255d727.bfe51a29d76a8da5
+ e9fe106c33d3cba4.ee659846f43778e0.cf072b8199f5cc54.bb0f379d9639660d
+ 723f5096e0d27759
+ after
+ 44d437d115438e1c.ec7223ec9b8ea10e.4f6da9c478b96058.8477e22088f793cf
+ 655bd0f29ecff2fe.5e7f5fc34f36b724.e895792750449c8c.2177fdce06d8b074
+ 6a41931c836f62c2.fff0000000000000.f813e7b74f719c5d.8000000000000000
+ e9fe106c33d3cba4.ee659846f43778e0.cf072b8199f5cc54.bb0f379d9639660d
+ 723f5096e0d27759
+
+VMULPD_256(reg)
+ before
+ 3ec25f8050c0fb35.03b1ae9b7763b9bf.c3d58dca1da99bde.d6e9065041323840
+ 7ce462c7828f2f4c.2860f0fd8661f79b.1dfeb6b5fb778f82.baa1871b6717d617
+ 88f054d813cc4f4b.34d7537d7dd94364.572c1174292b9278.58fa29cf27b16404
+ be34311d9e0296dd.03e2510777d85746.ccab99714453de6b.8ac16b569b0b9c33
+ 2dc3c69ee2313bd1
+ after
+ c5e4cee168bb9ef3.1d48b2d374536274.353af09fca8dcfeb.d3aca959ad2d15ba
+ 7ce462c7828f2f4c.2860f0fd8661f79b.1dfeb6b5fb778f82.baa1871b6717d617
+ 88f054d813cc4f4b.34d7537d7dd94364.572c1174292b9278.58fa29cf27b16404
+ be34311d9e0296dd.03e2510777d85746.ccab99714453de6b.8ac16b569b0b9c33
+ 2dc3c69ee2313bd1
+VMULPD_256(mem)
+ before
+ 1dcab7921630fc0a.7bfaf504c0bd41af.714d68879068ef6c.dac64b1ae77ab008
+ 36a2bb1d53139c0a.19909df7158a8c6d.5ae313eae598c902.dcca21d9ae2d43fa
+ 54194d2db6e6d7fb.f540246437f4b3c2.9a71cf1a92719f35.2d04191c36f7d4ee
+ 52fae9ad5ab5690c.6b5786b6c587f15b.0dc31604b2012d31.2bbe2e4e1b649f8f
+ 30445cdbf800e08a
+ after
+ 1dcab7921630fc0a.7bfaf504c0bd41af.714d68879068ef6c.dac64b1ae77ab008
+ 36a2bb1d53139c0a.19909df7158a8c6d.5ae313eae598c902.dcca21d9ae2d43fa
+ 147f46f6cbcc44a5.559bff294a24e64b.7ff0000000000000.77a2349af678c288
+ 52fae9ad5ab5690c.6b5786b6c587f15b.0dc31604b2012d31.2bbe2e4e1b649f8f
+ 30445cdbf800e08a
+
+VMULPD_256(reg)
+ before
+ 9ae49f2f6958d38b.0e100c895c8d0d67.d720bf5958d083e3.8fa5669562543122
+ c3e9f4b60bf8b33d.632831add77a8039.95e9ccb98f5aa507.fce33ab8bc746533
+ 099e56dc7a6abd4d.2d0ed306e8867ead.01fda74203b29373.30490e58df6f8690
+ c650c10d513c2c67.488e717eaabfc3f0.77a74e60526388d2.07a25f63e5515066
+ 5cbca8c4ea247ee1
+ after
+ 8d989bdf2a2870ed.50474e1fc5661c82.8000000000000000.ed3e1cfed79b4855
+ c3e9f4b60bf8b33d.632831add77a8039.95e9ccb98f5aa507.fce33ab8bc746533
+ 099e56dc7a6abd4d.2d0ed306e8867ead.01fda74203b29373.30490e58df6f8690
+ c650c10d513c2c67.488e717eaabfc3f0.77a74e60526388d2.07a25f63e5515066
+ 5cbca8c4ea247ee1
+VMULPD_256(mem)
+ before
+ 0d6165670bf6cd2c.584b31b52cfa3d36.9074840339310a2e.5334bc8018f9c1d1
+ f55e123863d3f974.19dba241a82e2c66.e08b897fb2e61092.f0f0ee0cf000791b
+ ef7f2b230fc5bee5.664c111b606635a5.16a1fde031ec9149.ac27de727705ee5d
+ d98f2d152adad7aa.9bea79b1f12e949d.0d805b11d14f487e.e2248a1c48935a43
+ ee35ed78ff37fa78
+ after
+ 0d6165670bf6cd2c.584b31b52cfa3d36.9074840339310a2e.5334bc8018f9c1d1
+ f55e123863d3f974.19dba241a82e2c66.e08b897fb2e61092.f0f0ee0cf000791b
+ c2d058f84ce76325.32377bd44f0b0e33.3111a789c4acd6ea.fff0000000000000
+ d98f2d152adad7aa.9bea79b1f12e949d.0d805b11d14f487e.e2248a1c48935a43
+ ee35ed78ff37fa78
+
+VMOVUPD_EtoG_128(reg)
+ before
+ 2ca403f1397c09a9.8e5c92f8d11e01f0.1500d66ef61084fa.a0f51ffdae1af25e
+ f7bfc9f291eec581.e9b0d8ba1f9cf8e2.2edb24be0c9a4269.adccc692e5594b14
+ add039e9a41968ad.c8587b45316077ad.43c8600dce580996.0ed1cabb92180fce
+ a92451420e8a2ed8.0520f58722763b7c.b01085c7d8d4172c.a1d0a964d064f9b5
+ 4094de7abb48c6f7
+ after
+ 2ca403f1397c09a9.8e5c92f8d11e01f0.1500d66ef61084fa.a0f51ffdae1af25e
+ f7bfc9f291eec581.e9b0d8ba1f9cf8e2.2edb24be0c9a4269.adccc692e5594b14
+ add039e9a41968ad.c8587b45316077ad.43c8600dce580996.0ed1cabb92180fce
+ 0000000000000000.0000000000000000.43c8600dce580996.0ed1cabb92180fce
+ 4094de7abb48c6f7
+VMOVUPD_EtoG_128(mem)
+ before
+ c9eae5e770d032c0.46060c676acc55af.7ed4c46a0feb007c.d1028f58c89ca6d8
+ 169f3b980a09f83c.e2c467c5546c17de.0d4063dc13ca82d9.02e97a2c373cf345
+ 057d5b7aa6fed596.d7a85cc869f5b110.90304ec84a1f7cbe.9f1042afc33f3920
+ 7050c1775fbc85fb.8300e9dd44f35ef2.e16f011ad1f7ab58.05c5e44e0831b515
+ 8e525b73a19ea3cf
+ after
+ c9eae5e770d032c0.46060c676acc55af.7ed4c46a0feb007c.d1028f58c89ca6d8
+ 169f3b980a09f83c.e2c467c5546c17de.0d4063dc13ca82d9.02e97a2c373cf345
+ 0000000000000000.0000000000000000.7ed4c46a0feb007c.d1028f58c89ca6d8
+ 7050c1775fbc85fb.8300e9dd44f35ef2.e16f011ad1f7ab58.05c5e44e0831b515
+ 8e525b73a19ea3cf
+
+VMOVUPD_EtoG_128(reg)
+ before
+ 9604a38c2a133ffb.34e6e97d524ec496.4016096e82f35c30.ddcaf9bec45dcbd3
+ 7b27b803401bc444.2e0a4f779ac04d94.6c37b8e9be80e575.610db0a13d5e975a
+ 980797467e426f57.38877051541edd20.61aef3b99426356d.4704a4ad5b05cc19
+ 49ef3ac081157cdf.2f2ac7f79b753067.7cc9b449a1728ac6.6c7b51cf385e263e
+ ad3e31f4f07561f2
+ after
+ 9604a38c2a133ffb.34e6e97d524ec496.4016096e82f35c30.ddcaf9bec45dcbd3
+ 7b27b803401bc444.2e0a4f779ac04d94.6c37b8e9be80e575.610db0a13d5e975a
+ 980797467e426f57.38877051541edd20.61aef3b99426356d.4704a4ad5b05cc19
+ 0000000000000000.0000000000000000.61aef3b99426356d.4704a4ad5b05cc19
+ ad3e31f4f07561f2
+VMOVUPD_EtoG_128(mem)
+ before
+ e418c206a0573864.ea2d9fdde41f278a.f0bfd0558bd00195.1ad3f90781ef1e2a
+ eed77ef3630f68be.d70bc20944edab01.55120757413c0dd5.9517bd5ecf292e45
+ a745e4a656aaad2c.6cd69db03c0a45f3.3befe8e9d9c41054.4ae2fcba28adf5c4
+ eb2f6d0b9433c2dc.04da2e3e6902300a.7e22f0f76e74c63d.9680b3882706b153
+ d33ddd3268c09c9d
+ after
+ e418c206a0573864.ea2d9fdde41f278a.f0bfd0558bd00195.1ad3f90781ef1e2a
+ eed77ef3630f68be.d70bc20944edab01.55120757413c0dd5.9517bd5ecf292e45
+ 0000000000000000.0000000000000000.f0bfd0558bd00195.1ad3f90781ef1e2a
+ eb2f6d0b9433c2dc.04da2e3e6902300a.7e22f0f76e74c63d.9680b3882706b153
+ d33ddd3268c09c9d
+
+VMOVUPD_EtoG_128(reg)
+ before
+ 5e6576258868f24f.9661960e3ab665f7.fd636f206661aaf2.fa769a6e1c58eabd
+ 93437ace2289f114.84a7dc9b634050ac.b2bc5ec0d0b4ed58.8bb86238007d3900
+ ce25e597d3afd399.91ccba9e2cdc3f25.7e33f78c428736e8.0db5c44336ef6f31
+ 6c55b4ee3667d58a.999eac03b096f08e.bf1234ee5964c04d.5c373d7ad8b8487d
+ 540a48c805e67f0f
+ after
+ 5e6576258868f24f.9661960e3ab665f7.fd636f206661aaf2.fa769a6e1c58eabd
+ 93437ace2289f114.84a7dc9b634050ac.b2bc5ec0d0b4ed58.8bb86238007d3900
+ ce25e597d3afd399.91ccba9e2cdc3f25.7e33f78c428736e8.0db5c44336ef6f31
+ 0000000000000000.0000000000000000.7e33f78c428736e8.0db5c44336ef6f31
+ 540a48c805e67f0f
+VMOVUPD_EtoG_128(mem)
+ before
+ d1fc611bd784d114.c720e23ee83c3392.78e72fb70b7b1d15.d0a61354b0d9c934
+ afd8045e6a9ff9b8.3cd26bf285ba285e.0a74bda45a9582e3.0c3b8f29e3718b49
+ ca69ad7dda42b526.27b74b78a76ef199.2b11d4b8b9f3dd27.d11da4d88fb94237
+ fe7cd9654579bf8b.e41a7e3bece3caf0.b78aefdd439ee80b.79984ecf503c2cab
+ 62f78a7ac1868350
+ after
+ d1fc611bd784d114.c720e23ee83c3392.78e72fb70b7b1d15.d0a61354b0d9c934
+ afd8045e6a9ff9b8.3cd26bf285ba285e.0a74bda45a9582e3.0c3b8f29e3718b49
+ 0000000000000000.0000000000000000.78e72fb70b7b1d15.d0a61354b0d9c934
+ fe7cd9654579bf8b.e41a7e3bece3caf0.b78aefdd439ee80b.79984ecf503c2cab
+ 62f78a7ac1868350
+
+VADDPD_256(reg)
+ before
+ e68853437e2484d3.27dd0300c451d412.cf4901a7f0a6ee0f.8aaa8a0114a460bb
+ 6295a59724a16adf.2058a73b75d5afe8.448ecf294e419ba1.803f220f49110164
+ 336b7ce24e897321.c7b9410374110d39.9e36e42ba3430b53.741332f3fdef8632
+ b356d4919969d945.f7cb4e42dc12aa30.3b8d3c1a8a357ad0.44f335994d4cac51
+ cbabaaed54342feb
+ after
+ 6295a59724a16adf.c7b9410374110d39.448ecf294e419ba1.741332f3fdef8632
+ 6295a59724a16adf.2058a73b75d5afe8.448ecf294e419ba1.803f220f49110164
+ 336b7ce24e897321.c7b9410374110d39.9e36e42ba3430b53.741332f3fdef8632
+ b356d4919969d945.f7cb4e42dc12aa30.3b8d3c1a8a357ad0.44f335994d4cac51
+ cbabaaed54342feb
+VADDPD_256(mem)
+ before
+ e4070adb2fb2cb2f.3fa2aa0ea0ccd8f6.8b5c48e6cae342f9.76dfd463a0a526c5
+ 6dd3d34ff9d23b47.349af9c7003eaee1.6136adda599090c2.ab78a770801e49de
+ 41da7f36cfa03c60.ec8cbd27544c95b1.5426f909a52652b5.36a3b1afc62d20c6
+ 3bea8c7acc298aa5.c4c2f39a3981ca13.3ff8a661cbb041fe.72aeee8b0f5ce629
+ bde35a70f63ad8b5
+ after
+ e4070adb2fb2cb2f.3fa2aa0ea0ccd8f6.8b5c48e6cae342f9.76dfd463a0a526c5
+ 6dd3d34ff9d23b47.349af9c7003eaee1.6136adda599090c2.ab78a770801e49de
+ 6dd3d34ff9d23b47.3fa2aa0ea0ccd8f6.6136adda599090c2.76dfd463a0a526c5
+ 3bea8c7acc298aa5.c4c2f39a3981ca13.3ff8a661cbb041fe.72aeee8b0f5ce629
+ bde35a70f63ad8b5
+
+VADDPD_256(reg)
+ before
+ 728ff2ca18503214.39cd76090d78e043.1889958b4a6989b3.007832cde73b1cca
+ ecfeb105112c30f2.1550b7cdad99fb65.452da16824910d3c.7172173913d19d45
+ 897c938d7b590dfc.ad3fcdb4c9999739.a5fa129d6284935b.70b1d4926e81819a
+ a45494cef56407de.db6633a97c8370e8.953ce494a1ce57bb.d702e2c2125484f6
+ 8432beb61b586185
+ after
+ ecfeb105112c30f2.ad3fcdb4c9999739.452da16824910d3c.717218565cf8855d
+ ecfeb105112c30f2.1550b7cdad99fb65.452da16824910d3c.7172173913d19d45
+ 897c938d7b590dfc.ad3fcdb4c9999739.a5fa129d6284935b.70b1d4926e81819a
+ a45494cef56407de.db6633a97c8370e8.953ce494a1ce57bb.d702e2c2125484f6
+ 8432beb61b586185
+VADDPD_256(mem)
+ before
+ 510be55ba698d672.98d4b13519d85743.7d906598e26441a1.713e13ba7cfc9409
+ 1c5ad29bce209ce9.c346e52c83413cd8.6d8bdf6d1846c78d.954e9c7b8f9987f1
+ bfea0164b0fd7218.7ff72c21cf2cf049.88211e143a37bedb.5db67a4477316c1e
+ 1789eea1673a1228.2933827e9b24b041.ab1f9c796343e1b5.25c3a97fcf517f3d
+ 49c1259a3484fbf9
+ after
+ 510be55ba698d672.98d4b13519d85743.7d906598e26441a1.713e13ba7cfc9409
+ 1c5ad29bce209ce9.c346e52c83413cd8.6d8bdf6d1846c78d.954e9c7b8f9987f1
+ 510be55ba698d672.c346e52c83413cd8.7d906598e26441a1.713e13ba7cfc9409
+ 1789eea1673a1228.2933827e9b24b041.ab1f9c796343e1b5.25c3a97fcf517f3d
+ 49c1259a3484fbf9
+
+VADDPD_256(reg)
+ before
+ 25fbeb0042571dff.0101163e0fe43948.1e46e3b180b5b86c.b051d789af75ed48
+ 14bff61d945521fb.571ff427c506a3a2.b87b4c251c6c4378.74834a2e3bd99ebf
+ 7457425dc60a4398.f6af0448a5ac0c63.5520b8460bd48f0f.d4807255227cb047
+ a011cb2c7502be83.ba7dc28dcae22fb6.4f7f2380e879d5dd.aa16caeb8168de0b
+ d30fcddb73ace538
+ after
+ 7457425dc60a4398.f6af0448a5ac0c63.5520b8460bd48f0f.74834a2e3bd99ebf
+ 14bff61d945521fb.571ff427c506a3a2.b87b4c251c6c4378.74834a2e3bd99ebf
+ 7457425dc60a4398.f6af0448a5ac0c63.5520b8460bd48f0f.d4807255227cb047
+ a011cb2c7502be83.ba7dc28dcae22fb6.4f7f2380e879d5dd.aa16caeb8168de0b
+ d30fcddb73ace538
+VADDPD_256(mem)
+ before
+ 2b38f911155181fa.f4378df63ccacf67.7f55abe251b5c9c8.03e5893f4fe8548f
+ 8e5eca7882656d7c.cc168527b8edb2f1.22033933553195c4.ce9ee7efddac46d1
+ d84abafed7f367eb.83faae2b84f8a2cd.7d52ea6df26051d7.0af637fc2e51e84e
+ e5cb478e2f082972.772e046f3c76dca6.6d10397a4550b72d.143977d2dd6476b3
+ 48b3a2de86702cab
+ after
+ 2b38f911155181fa.f4378df63ccacf67.7f55abe251b5c9c8.03e5893f4fe8548f
+ 8e5eca7882656d7c.cc168527b8edb2f1.22033933553195c4.ce9ee7efddac46d1
+ 2b38f911155181fa.f4378df63ccacf67.7f55abe251b5c9c8.ce9ee7efddac46d1
+ e5cb478e2f082972.772e046f3c76dca6.6d10397a4550b72d.143977d2dd6476b3
+ 48b3a2de86702cab
+
+VSUBPD_256(reg)
+ before
+ 02afb58bc60145e3.91acec15a7af6f3e.0300835d7ef39c29.ce07a348690c84f1
+ 9e7aaa4438a4fe07.b8b8257d5af4f77b.82ba2763e3fb1e01.7c04a2c27ba17350
+ 78607f7779e492c2.36bc6eb364e47b54.52a9edec091b9ddb.53d2b4d4961a4175
+ ecad2f8f244d3fc1.e78444a4e28ab7f6.cd19d0638cdf5662.2f3f5469d783aa8d
+ ec16fe6f59e96ac3
+ after
+ f8607f7779e492c2.b8b8257d5b11662e.d2a9edec091b9ddb.7c04a2c27ba17350
+ 9e7aaa4438a4fe07.b8b8257d5af4f77b.82ba2763e3fb1e01.7c04a2c27ba17350
+ 78607f7779e492c2.36bc6eb364e47b54.52a9edec091b9ddb.53d2b4d4961a4175
+ ecad2f8f244d3fc1.e78444a4e28ab7f6.cd19d0638cdf5662.2f3f5469d783aa8d
+ ec16fe6f59e96ac3
+VSUBPD_256(mem)
+ before
+ 65222fd139573c45.56adb6f8d66c3faf.a7dc223af0f2698c.5156cc3607d18543
+ 7830617c92d9dd3c.12ac111e2acccf39.52908463a9294b43.38acded0167f652a
+ 000c125a817c09d7.7cf53b6dbdfa2a0b.c46ce60a293a1a47.e066009d567433c2
+ d982bd58214b7c40.f0d52f512a808dd0.d93bc51a8d3192c3.a3d2300a633d2bb8
+ df3a6981d76589b8
+ after
+ 65222fd139573c45.56adb6f8d66c3faf.a7dc223af0f2698c.5156cc3607d18543
+ 7830617c92d9dd3c.12ac111e2acccf39.52908463a9294b43.38acded0167f652a
+ 7830617c92d9dd3c.d6adb6f8d66c3faf.52908463a9294b43.d156cc3607d18543
+ d982bd58214b7c40.f0d52f512a808dd0.d93bc51a8d3192c3.a3d2300a633d2bb8
+ df3a6981d76589b8
+
+VSUBPD_256(reg)
+ before
+ eeeba76f5178886d.df5edf638f52f1a3.ca99ec360eed3435.6ccb9b81f11b6ee3
+ 2d31e7416b036583.ed6bf265e69e252d.668b6b8904ca5be5.5be6e62a6f036bd5
+ f9582361c1915ca8.e177744c423ad40a.20f7aab4a8a53d8d.8159210126f545c3
+ acab593df0aea885.964ce003c032b965.542ba325970917d9.b9f0c9f32ffeb8d9
+ e17658eaa9297f44
+ after
+ 79582361c1915ca8.ed6bf265e69e252d.668b6b8904ca5be5.5be6e62a6f036bd5
+ 2d31e7416b036583.ed6bf265e69e252d.668b6b8904ca5be5.5be6e62a6f036bd5
+ f9582361c1915ca8.e177744c423ad40a.20f7aab4a8a53d8d.8159210126f545c3
+ acab593df0aea885.964ce003c032b965.542ba325970917d9.b9f0c9f32ffeb8d9
+ e17658eaa9297f44
+VSUBPD_256(mem)
+ before
+ d4b94cd3ad825730.a378844093e786c9.e7b7b2767c93916b.5d7254476d822574
+ 6d83209b5a16fcc8.3a09a1d547c7321e.b284669091681848.9917b985c59da30a
+ 8aa1502cc9f02939.ceabaa6aa7dae831.d17f793f1bbd0927.6367cc4d3be6cc49
+ 05df5974181c9baf.b9aa9d6a4fade3ad.2274666f379f2235.17ae8b0a6ce7dddb
+ 1038f128f42e126c
+ after
+ d4b94cd3ad825730.a378844093e786c9.e7b7b2767c93916b.5d7254476d822574
+ 6d83209b5a16fcc8.3a09a1d547c7321e.b284669091681848.9917b985c59da30a
+ 6d83209b5a16fcc8.3a09a1d547c7321e.67b7b2767c93916b.dd7254476d822574
+ 05df5974181c9baf.b9aa9d6a4fade3ad.2274666f379f2235.17ae8b0a6ce7dddb
+ 1038f128f42e126c
+
+VSUBPD_256(reg)
+ before
+ ac51fa136d46a6a9.bc09b65e63a70e55.58527541dccb603f.802ea90a00191d9d
+ 4544a23876bcd63e.89ebe2d6c59c3e57.07ef2e5ceac19b92.c67abefd9338b68c
+ 395fe501a81bded6.4a515cc75a08e6e3.22ccc5251419cf53.d12522340c06ab2d
+ e2ecc0dba2effa1e.d9069d1f3ff5c323.05363409f6613a2e.7ef94f9c8592b6ad
+ a7c3c3201de59438
+ after
+ 4544a23876bcd63e.ca515cc75a08e6e3.a2ccc5251419cf53.512522340c06ab2d
+ 4544a23876bcd63e.89ebe2d6c59c3e57.07ef2e5ceac19b92.c67abefd9338b68c
+ 395fe501a81bded6.4a515cc75a08e6e3.22ccc5251419cf53.d12522340c06ab2d
+ e2ecc0dba2effa1e.d9069d1f3ff5c323.05363409f6613a2e.7ef94f9c8592b6ad
+ a7c3c3201de59438
+VSUBPD_256(mem)
+ before
+ 2a4ef9abed0d01f9.9e382e33fdc565c2.14d722ca90729143.0c7a79752d2516ce
+ e1686e2b1315b81d.c78f2b7358285c6d.d59168b268880b70.93e28fd355f09fe0
+ a9db9c8bab0a76d0.bb3db4094ca41bcb.f9feeac4e345eed6.f6ba7291094e130f
+ 5e7401b7d0f6f73d.d48ec36077c5dd8a.5cea24ed1eb4f6a0.91501f1ae5cbac08
+ c0ef91da86f4a776
+ after
+ 2a4ef9abed0d01f9.9e382e33fdc565c2.14d722ca90729143.0c7a79752d2516ce
+ e1686e2b1315b81d.c78f2b7358285c6d.d59168b268880b70.93e28fd355f09fe0
+ e1686e2b1315b81d.c78f2b7358285c6d.d59168b268880b70.93e28fd355f09fe0
+ 5e7401b7d0f6f73d.d48ec36077c5dd8a.5cea24ed1eb4f6a0.91501f1ae5cbac08
+ c0ef91da86f4a776
+
+VDIVPD_256(reg)
+ before
+ dfe2c43d87543f07.ddff189b9fe8f690.6fcd56e47518df54.db23931734e2dffb
+ 4976b4af8578b164.00485e2333e930f6.e9476801e1295dd5.5073b13042da6412
+ 5cf85d9c1beb393c.a41b4d3ba807619b.9c49f623578293ba.98a8fc2264a84212
+ 73b2bc70e6391339.a54463d01b4d45ab.e51dfab674b1bcaf.8f8cefdbb4583527
+ 11ec074650f7f87c
+ after
+ 2c6dd1efe3c69095.9c1c8fa648425ab9.7ff0000000000000.f7b9389f0424598a
+ 4976b4af8578b164.00485e2333e930f6.e9476801e1295dd5.5073b13042da6412
+ 5cf85d9c1beb393c.a41b4d3ba807619b.9c49f623578293ba.98a8fc2264a84212
+ 73b2bc70e6391339.a54463d01b4d45ab.e51dfab674b1bcaf.8f8cefdbb4583527
+ 11ec074650f7f87c
+VDIVPD_256(mem)
+ before
+ fa94be4f5490493e.eaf0cc9781ee7a07.df8e1bcca8c89751.21107226d442155f
+ 265092e2db30e298.1c00897e8997ab53.2ec7f11c6a8314b9.aa6d59e012c0da77
+ 71ebfeeb02e27fb7.672cef8f99bfe2c9.6eb961ad7d8a7810.dd82ab4ecab746a2
+ b7337e56e4b2dec7.26c2fa384ef35b14.7b31e86afeea7f82.169964de99b3978d
+ b1ff81fa1a4107e4
+ after
+ fa94be4f5490493e.eaf0cc9781ee7a07.df8e1bcca8c89751.21107226d442155f
+ 265092e2db30e298.1c00897e8997ab53.2ec7f11c6a8314b9.aa6d59e012c0da77
+ 8000000000000000.8000000000000000.8f297223982344d3.c94c8e25f7cf9f09
+ b7337e56e4b2dec7.26c2fa384ef35b14.7b31e86afeea7f82.169964de99b3978d
+ b1ff81fa1a4107e4
+
+VDIVPD_256(reg)
+ before
+ 0a01fd10eaecd252.d4f28e109eadb9f3.b40ca7e343be51e1.31fb003f08ade43b
+ 7de8d48ba4403684.a4f5ab034bdecc68.6f57f1fe14ac01dc.6ce22718b8e26466
+ 660302d7e5ca6d25.0308501d0751d551.b1efd4f45e4aa7b0.08b4d9e02992ba2f
+ 219d84604815b3e2.cdf7f948ef138edb.d81f4d31bd237e09.e13b908678cba4c3
+ d344caf3c099dc4e
+ after
+ 57d4e5c0cab57a74.e1dc84d1d5daaf91.fd58125f84fc65ab.7ff0000000000000
+ 7de8d48ba4403684.a4f5ab034bdecc68.6f57f1fe14ac01dc.6ce22718b8e26466
+ 660302d7e5ca6d25.0308501d0751d551.b1efd4f45e4aa7b0.08b4d9e02992ba2f
+ 219d84604815b3e2.cdf7f948ef138edb.d81f4d31bd237e09.e13b908678cba4c3
+ d344caf3c099dc4e
+VDIVPD_256(mem)
+ before
+ ba9b02141e061ffb.0a0154926aad4667.de8d22721e2fb432.3e355621ccc3c395
+ 710cb4d5ad2028f7.7d7d70d9e61f605f.12984886b1b10381.417bed3027b6b2fe
+ d6635c2389f3b46e.d65bd3a259f63e77.44e2e570c4a636f5.3b3f0dcb6b8987f0
+ c46c76e8d0897f8b.71e87a575ebf1c5a.5238771c72190ab9.89cbb25c33c87d18
+ 886cd9501cfdd122
+ after
+ ba9b02141e061ffb.0a0154926aad4667.de8d22721e2fb432.3e355621ccc3c395
+ 710cb4d5ad2028f7.7d7d70d9e61f605f.12984886b1b10381.417bed3027b6b2fe
+ f661018e47fd8f5e.7ff0000000000000.8000000000000000.4334f11b66f5a968
+ c46c76e8d0897f8b.71e87a575ebf1c5a.5238771c72190ab9.89cbb25c33c87d18
+ 886cd9501cfdd122
+
+VDIVPD_256(reg)
+ before
+ 926d7c14c1b6bfb9.17f27f129bf0457b.aa705f66910535b5.17667976d7163bfa
+ 041c9913bf7f828a.aac2f28c0834c169.dc3e80398f54c634.6f38686a10aa85e3
+ 3bc32bb8b1e25840.5ba84b423360b182.65a0d83ef4380b82.357abee438e0a3a2
+ 91b02f71346d7a88.047007203680cef2.a0e063e05b3e404b.47f7f9d16cc45260
+ 7f7d941bc7634e4c
+ after
+ 0847de31c100d110.8f08f5227cf3900c.b68cf8aa92cc61ca.79ad33f2e30ea17d
+ 041c9913bf7f828a.aac2f28c0834c169.dc3e80398f54c634.6f38686a10aa85e3
+ 3bc32bb8b1e25840.5ba84b423360b182.65a0d83ef4380b82.357abee438e0a3a2
+ 91b02f71346d7a88.047007203680cef2.a0e063e05b3e404b.47f7f9d16cc45260
+ 7f7d941bc7634e4c
+VDIVPD_256(mem)
+ before
+ bbd60bb065c8528f.632d9fa9e3ac270e.83e6a01230a0d7e4.e94b1e8a60f1a03d
+ d5cfdb7a63001b58.0d8779cc5b2a997d.b3d694043bcd8684.9b2d03aaa0de6802
+ ab347e67dd1565d1.eb0ab84637730d82.6f0b5ee273129800.14d210acb690d346
+ 17d17262ee15ec27.590158831313bfc8.95537b98f57bc982.af8640fa3f931fb6
+ c7959001d77486fe
+ after
+ bbd60bb065c8528f.632d9fa9e3ac270e.83e6a01230a0d7e4.e94b1e8a60f1a03d
+ d5cfdb7a63001b58.0d8779cc5b2a997d.b3d694043bcd8684.9b2d03aaa0de6802
+ 59e71ef8dd2fabb8.0000000000000000.6fdfeef362d0e1d0.0000000000000000
+ 17d17262ee15ec27.590158831313bfc8.95537b98f57bc982.af8640fa3f931fb6
+ c7959001d77486fe
+
+VPCMPEQQ_128(reg)
+ before
+ ba4afa2d18be45c9.f7713257b30c6b85.b3ba56f08c97ebfc.ff786513dc15d436
+ e2f27ceba1fd97c4.25e23b3247059f18.557facf73e8accca.8a479a3d45eb7749
+ 9dda11a50bbdba9b.7fee07dfc60c440b.9b9d5806c4789fdd.138c95044b0a6be7
+ 454bb5c9f48be8f9.df62144a4d2d158b.e1605587baeea0e2.7412d2520b7c6f3b
+ 8aa7cd15a0503d72
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ e2f27ceba1fd97c4.25e23b3247059f18.557facf73e8accca.8a479a3d45eb7749
+ 9dda11a50bbdba9b.7fee07dfc60c440b.9b9d5806c4789fdd.138c95044b0a6be7
+ 454bb5c9f48be8f9.df62144a4d2d158b.e1605587baeea0e2.7412d2520b7c6f3b
+ 8aa7cd15a0503d72
+VPCMPEQQ_128(mem)
+ before
+ 32150338278f92b7.389464c2f8f35d8a.220add60f775cfc4.8314a0e8bd770a84
+ 4629efa7bb472a37.d0001bfbb27f57fc.24b2de0be1ef2ee1.dd05339469a01a70
+ a3b00d4e7883c11e.6adad5e2bfbd10f8.c225943927a8ee0f.4b7f0cf658f30c52
+ 2573d9197b501297.63708ee2ba39c52d.d63179d4e3abca79.29cd267c29ff1bd5
+ d33c7d91764d85a6
+ after
+ 32150338278f92b7.389464c2f8f35d8a.220add60f775cfc4.8314a0e8bd770a84
+ 4629efa7bb472a37.d0001bfbb27f57fc.24b2de0be1ef2ee1.dd05339469a01a70
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 2573d9197b501297.63708ee2ba39c52d.d63179d4e3abca79.29cd267c29ff1bd5
+ d33c7d91764d85a6
+
+VPCMPEQQ_128(reg)
+ before
+ a4180da2db6b8470.a941cff4e0b9dacf.150c42673f7db245.3da00bca34047f4c
+ faadd319f4e454e0.09e56cccc2cad4f1.ddfbeedeeb1712ed.d340c50633bfc9b4
+ 3047ca635f4533a2.222a2b8b3d8fbe2a.17898cb15a9322d0.74db2374ffe963dc
+ a232eeedb5195b61.d0de881f6e1552a6.20021a4d277b1e9b.fc3da200b18e0bf1
+ 4734bd9667b87b1f
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ faadd319f4e454e0.09e56cccc2cad4f1.ddfbeedeeb1712ed.d340c50633bfc9b4
+ 3047ca635f4533a2.222a2b8b3d8fbe2a.17898cb15a9322d0.74db2374ffe963dc
+ a232eeedb5195b61.d0de881f6e1552a6.20021a4d277b1e9b.fc3da200b18e0bf1
+ 4734bd9667b87b1f
+VPCMPEQQ_128(mem)
+ before
+ 318bf0223d756f91.abb93b2194ec09c9.efcbff7271684d90.52b1941fee5d41f9
+ 960db7904ed0a573.a92aae6d984a7888.5bbe0d7260926a15.0ae3f4914cc5c897
+ 52878eccb7d6d7f2.f6cf413b5cc0e548.f0832d0a5aa16660.a4e53811dc3eef21
+ 41c5f2c39392c13a.f0f5f2f97dd98cb5.8ae5db2679a0fd9e.7c015a0a3b54f242
+ ee8458e704930ca7
+ after
+ 318bf0223d756f91.abb93b2194ec09c9.efcbff7271684d90.52b1941fee5d41f9
+ 960db7904ed0a573.a92aae6d984a7888.5bbe0d7260926a15.0ae3f4914cc5c897
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 41c5f2c39392c13a.f0f5f2f97dd98cb5.8ae5db2679a0fd9e.7c015a0a3b54f242
+ ee8458e704930ca7
+
+VPCMPEQQ_128(reg)
+ before
+ 56ba2e16d4887afb.3f935e5ffe102176.f2e8bc129622a97c.05b293b2d99cebfb
+ 10eed60246be78eb.28bd4e8e155db1d3.57f39cf243267849.3db4d19a97a0eba2
+ 786e4e17f7c14223.d80f3e3bf4842e7d.7d648c05217134c7.0db812caceb8bac0
+ ea8491c2821e134e.2b54aa52b691549f.be858ab7cb901aa3.538ad12e9af11480
+ eaf68ab21956b50f
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 10eed60246be78eb.28bd4e8e155db1d3.57f39cf243267849.3db4d19a97a0eba2
+ 786e4e17f7c14223.d80f3e3bf4842e7d.7d648c05217134c7.0db812caceb8bac0
+ ea8491c2821e134e.2b54aa52b691549f.be858ab7cb901aa3.538ad12e9af11480
+ eaf68ab21956b50f
+VPCMPEQQ_128(mem)
+ before
+ aec8b94364f35899.c27d9b6d84602819.fc5a0fbe7791de66.77a39174de0e6589
+ 7accdbcb99d5ba49.5ca568859814bc2f.29ebe86d548f89fd.050a9da9f6775224
+ 2ccd6b38d407974c.1348f5775ac50d3d.8dd4b14b68971191.c206abc0ad581d20
+ 9f98e5753095aacd.45b23dae67ff55ee.04e1e742d0b6324e.0be3b627a23c022b
+ 3dedb9486eaf3dee
+ after
+ aec8b94364f35899.c27d9b6d84602819.fc5a0fbe7791de66.77a39174de0e6589
+ 7accdbcb99d5ba49.5ca568859814bc2f.29ebe86d548f89fd.050a9da9f6775224
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 9f98e5753095aacd.45b23dae67ff55ee.04e1e742d0b6324e.0be3b627a23c022b
+ 3dedb9486eaf3dee
+
+VSUBPD_128(reg)
+ before
+ b26fb391b03e0918.aef9c56ec98cb0f9.4d2e3c955b4ed1f0.69dd043fa7f7a75f
+ c7b69d6d0174a353.37bc870fbcf765fb.8709ee9ad13fbcec.9a96862e0a662df0
+ d80f744800dd464b.15ada84425e38400.4e904f28655d5491.71d6e8fc1410802f
+ 41c4358e460630ae.2398a3f91e5acb34.000d5cabb435d389.cc6aa693e2005b46
+ 861e3de18f437b61
+ after
+ 0000000000000000.0000000000000000.ce904f28655d5491.f1d6e8fc1410802f
+ c7b69d6d0174a353.37bc870fbcf765fb.8709ee9ad13fbcec.9a96862e0a662df0
+ d80f744800dd464b.15ada84425e38400.4e904f28655d5491.71d6e8fc1410802f
+ 41c4358e460630ae.2398a3f91e5acb34.000d5cabb435d389.cc6aa693e2005b46
+ 861e3de18f437b61
+VSUBPD_128(mem)
+ before
+ 7abe27d137e39cad.5f21dbab717a9b25.3f48f41ac66af4c2.f8cd108f59527580
+ 8516e24ff7ef7a56.8c74620b1dc5c35f.438b1793371fbbd7.911b6740f1407823
+ 84f2e947eb70d087.2508c71be574e606.0d2b88518d84de9f.29455d2a188c161e
+ 511db9a52e745b6d.8628044565123ec6.77f5c43ee5a51745.1a95efba68c18c1c
+ c259175a806b15ca
+ after
+ 7abe27d137e39cad.5f21dbab717a9b25.3f48f41ac66af4c2.f8cd108f59527580
+ 8516e24ff7ef7a56.8c74620b1dc5c35f.438b1793371fbbd7.911b6740f1407823
+ 0000000000000000.0000000000000000.438b1793371fbbd7.78cd108f59527580
+ 511db9a52e745b6d.8628044565123ec6.77f5c43ee5a51745.1a95efba68c18c1c
+ c259175a806b15ca
+
+VSUBPD_128(reg)
+ before
+ 7bdbd378f916eed4.ca64cc55dc06d733.0b2117f63a2c084d.5eb546485a8e23f5
+ a3681f7e714f53e5.c994a0431232ff07.103ffb9b004c8044.9f368a59094cbedd
+ 944cf5da84a280a9.2b77b05bec059012.f1cead9f5201e15a.14460d5f0deaa327
+ acd253f7cd99b1ce.cdd9788a848a4682.0a1a276dccd46839.9aaf494582758fff
+ 0e3ebcf785f83e92
+ after
+ 0000000000000000.0000000000000000.71cead9f5201e15a.9f368a59094cbedd
+ a3681f7e714f53e5.c994a0431232ff07.103ffb9b004c8044.9f368a59094cbedd
+ 944cf5da84a280a9.2b77b05bec059012.f1cead9f5201e15a.14460d5f0deaa327
+ acd253f7cd99b1ce.cdd9788a848a4682.0a1a276dccd46839.9aaf494582758fff
+ 0e3ebcf785f83e92
+VSUBPD_128(mem)
+ before
+ 4ac0e161327f6b0c.45483441e9c221fd.898874baf9cedd83.b66e67730b53518d
+ 2bfe346fa416d398.bcf8942473a90de5.3c4f21d965dc1041.5318681caa09d803
+ 8dc7320df8ca3263.6e2f6f0c07d8b030.c2f9fad2e4c09ce7.3c6226d446823847
+ 4ce6552849a64498.b539c16542dd488b.f7537b9093873da1.cd999d077a4bae05
+ 6209ca22e3f075e8
+ after
+ 4ac0e161327f6b0c.45483441e9c221fd.898874baf9cedd83.b66e67730b53518d
+ 2bfe346fa416d398.bcf8942473a90de5.3c4f21d965dc1041.5318681caa09d803
+ 0000000000000000.0000000000000000.3c4f21d965dc1041.5318681caa09d803
+ 4ce6552849a64498.b539c16542dd488b.f7537b9093873da1.cd999d077a4bae05
+ 6209ca22e3f075e8
+
+VSUBPD_128(reg)
+ before
+ 56fea88f1cfbcb9c.44261baab3b7c464.ee62879bc0440fa1.b72920018d3bae9d
+ 07c333bbc2faeace.5155ff8153086ff3.75f6bc1a1c97411f.de476610efebad04
+ d0a6671370780f2a.4f3d7e9744a50170.a7405c4ff2641cb0.4979c8a9d4a0f405
+ 0cf14101c202755b.1aab12daa39b3608.de8e64a5df37da01.d28ac2b858683fca
+ 5648d02a984e4c7f
+ after
+ 0000000000000000.0000000000000000.75f6bc1a1c97411f.de476610efebad04
+ 07c333bbc2faeace.5155ff8153086ff3.75f6bc1a1c97411f.de476610efebad04
+ d0a6671370780f2a.4f3d7e9744a50170.a7405c4ff2641cb0.4979c8a9d4a0f405
+ 0cf14101c202755b.1aab12daa39b3608.de8e64a5df37da01.d28ac2b858683fca
+ 5648d02a984e4c7f
+VSUBPD_128(mem)
+ before
+ b07d6ee9b05fd551.19f1bbf356235a0e.8e6b39358bf5c9e6.772ace877e9ab8be
+ bef619e2bba6966c.51f2d354c567f8ef.87486e9419bf7737.ce6198636c1cf292
+ 5b7f4c02d52f4dfc.12408490ad5a8ba9.e1102de36806fb27.3f7fbda44446c32a
+ 63e483341b07b42c.b627cb13aa8951e8.788df30e95d513e1.26d039b6a3a66831
+ df9f090524c71d54
+ after
+ b07d6ee9b05fd551.19f1bbf356235a0e.8e6b39358bf5c9e6.772ace877e9ab8be
+ bef619e2bba6966c.51f2d354c567f8ef.87486e9419bf7737.ce6198636c1cf292
+ 0000000000000000.0000000000000000.0e6b39358bf5c9e6.f72ace877e9ab8be
+ 63e483341b07b42c.b627cb13aa8951e8.788df30e95d513e1.26d039b6a3a66831
+ df9f090524c71d54
+
+VADDPD_128(reg)
+ before
+ c63a27fd64351d3f.b2f03a63a9398828.9bf3a2495680845a.288c3a01bb387992
+ 37eb910afe7da69d.2471ed7d9ad1851d.1bef079e50c961a9.cdd980a8f73cea65
+ 8eff42988f2af21b.9531196d0adc6637.9468f57e32f22381.434040f064ec2187
+ 26c23714b2c93d64.e0fd391f1665e8a1.60aa68569887088f.658df7c31f54db23
+ 118c1f0f4381d466
+ after
+ 0000000000000000.0000000000000000.1bef079e50c961a9.cdd980a8f73cea65
+ 37eb910afe7da69d.2471ed7d9ad1851d.1bef079e50c961a9.cdd980a8f73cea65
+ 8eff42988f2af21b.9531196d0adc6637.9468f57e32f22381.434040f064ec2187
+ 26c23714b2c93d64.e0fd391f1665e8a1.60aa68569887088f.658df7c31f54db23
+ 118c1f0f4381d466
+VADDPD_128(mem)
+ before
+ 220836beec7ec87c.5d806ae803e5c525.e3a1c97fd978c788.dc015d901f124a7f
+ 73ceb7be37577291.8e85d9821f0ac409.79e945797022bf18.65b9cf9a622125fc
+ e2aa1efa401990cf.151c7f4da2c476be.7da12afaf66e8b7c.551ebadefe40d7b3
+ 4a68e75e22cfdb65.4e9358b427a019ed.cd94f3ec8869e8e1.097b1aca8ef99a4f
+ dd1debc9afdaab7d
+ after
+ 220836beec7ec87c.5d806ae803e5c525.e3a1c97fd978c788.dc015d901f124a7f
+ 73ceb7be37577291.8e85d9821f0ac409.79e945797022bf18.65b9cf9a622125fc
+ 0000000000000000.0000000000000000.79e945797022bf18.65b9cf9a622125fc
+ 4a68e75e22cfdb65.4e9358b427a019ed.cd94f3ec8869e8e1.097b1aca8ef99a4f
+ dd1debc9afdaab7d
+
+VADDPD_128(reg)
+ before
+ 2e502a47fc6f46e9.86d48fd6f985127d.943461254a29e745.43901c3c411d9272
+ 5660d1b01242a63e.74ba914ee248ef44.454c950ba8ec1d70.bd5f21d73e98445c
+ b299de708ce10829.eee569b2f8232fe5.bc27efd2dc74f71a.16ce7ea89ae6bbca
+ 9e474cf306d8a855.d22393ee58238e8d.54116de6834db0f0.29a9b09a7112b3e9
+ d3bc329be028e8e5
+ after
+ 0000000000000000.0000000000000000.454c950ba8ec1d70.bd5f21d73e98445c
+ 5660d1b01242a63e.74ba914ee248ef44.454c950ba8ec1d70.bd5f21d73e98445c
+ b299de708ce10829.eee569b2f8232fe5.bc27efd2dc74f71a.16ce7ea89ae6bbca
+ 9e474cf306d8a855.d22393ee58238e8d.54116de6834db0f0.29a9b09a7112b3e9
+ d3bc329be028e8e5
+VADDPD_128(mem)
+ before
+ f1d28096033415e9.76b518a51db2c16f.fa3e8cef1e52c767.6b550bb43803869e
+ 5db91677f543f722.96313df36dfb9023.4303ce9f64bf98a0.5b41c3a69823b2cf
+ f53b712ad2604abc.5a05b647913f511c.8a3ed7ec4973ba64.821f93293e397330
+ 93250c9cb798c9e2.1e7e810f250b4007.a9ba23c0e67cecde.3a3c76aac7cf036d
+ e1e46894ce739f31
+ after
+ f1d28096033415e9.76b518a51db2c16f.fa3e8cef1e52c767.6b550bb43803869e
+ 5db91677f543f722.96313df36dfb9023.4303ce9f64bf98a0.5b41c3a69823b2cf
+ 0000000000000000.0000000000000000.fa3e8cef1e52c767.6b550bb43803869e
+ 93250c9cb798c9e2.1e7e810f250b4007.a9ba23c0e67cecde.3a3c76aac7cf036d
+ e1e46894ce739f31
+
+VADDPD_128(reg)
+ before
+ d1636652f0b18328.144363b7c0f531c0.3ee89ab5c6ea988f.7e452c0959e5e83b
+ 68046a52c813ea00.5561f26808863e84.168ffba70f689661.e3a970b2beba6ba7
+ 001572fff3271262.304b359cab54ac57.02bea2509d127629.b5b369a73008314d
+ f6e079c50c7834fd.82cca93dc66d3668.5ec38a1c0c737492.d03095d4ccdaf659
+ 10e97025ad3d75f9
+ after
+ 0000000000000000.0000000000000000.168ffba70f689661.e3a970b2beba6ba7
+ 68046a52c813ea00.5561f26808863e84.168ffba70f689661.e3a970b2beba6ba7
+ 001572fff3271262.304b359cab54ac57.02bea2509d127629.b5b369a73008314d
+ f6e079c50c7834fd.82cca93dc66d3668.5ec38a1c0c737492.d03095d4ccdaf659
+ 10e97025ad3d75f9
+VADDPD_128(mem)
+ before
+ 52ad7486ef3c6b56.a6b27b10af938f7b.27b1c93974dc99e1.85e8af77f618cb49
+ 70471fe4afe3939f.6dd8754c79035d89.fbc7117bd2ae91ef.d57a0ecdfa8cb8f9
+ 4782ec29093fabfe.a59b62e50654dbd2.dad8fdeffbeed9bd.a9c5a18ab15b774f
+ b32c5743185b6d9f.ab4a3e48f1134503.a1b00a810ca82f78.5d15661bba1143f7
+ 4cb558eaae3b599c
+ after
+ 52ad7486ef3c6b56.a6b27b10af938f7b.27b1c93974dc99e1.85e8af77f618cb49
+ 70471fe4afe3939f.6dd8754c79035d89.fbc7117bd2ae91ef.d57a0ecdfa8cb8f9
+ 0000000000000000.0000000000000000.fbc7117bd2ae91ef.d57a0ecdfa8cb8f9
+ b32c5743185b6d9f.ab4a3e48f1134503.a1b00a810ca82f78.5d15661bba1143f7
+ 4cb558eaae3b599c
+
+VUNPCKLPD_128(reg)
+ before
+ d4f373652b65f5ea.900fdc1cf84395b0.db3005dfd6cbd7c7.2a1db21d20e84d4b
+ 5019b4f6cd19538f.baf8f8a2c603e15a.9198b3185209cccb.52ea73af53bbef63
+ 1b74160b2fe5ae35.0db325c09da80bcc.2acf455e005761bb.f5e2c923c32dd3ec
+ 9350940fed544388.650be1629a3ed030.0021b61c7d43d142.efd22e668948b311
+ 1b872062c31a4bfe
+ after
+ 0000000000000000.0000000000000000.f5e2c923c32dd3ec.52ea73af53bbef63
+ 5019b4f6cd19538f.baf8f8a2c603e15a.9198b3185209cccb.52ea73af53bbef63
+ 1b74160b2fe5ae35.0db325c09da80bcc.2acf455e005761bb.f5e2c923c32dd3ec
+ 9350940fed544388.650be1629a3ed030.0021b61c7d43d142.efd22e668948b311
+ 1b872062c31a4bfe
+VUNPCKLPD_128(mem)
+ before
+ 57ca19058daf59e1.12f92d6ea4f34e35.9ecea874d8cfecb2.70da02c064595a0d
+ 7e6a9739021197e4.f6bbda94f04d0ae8.94c6f4e274691a7f.d64625b5522436c7
+ 6c3216ec3e4ec233.99e199ed6ceeb44c.22c04398891817c3.8eb11b67e230a21d
+ fded10095e7196fb.59b964e5b463880e.2688108234e69faa.f466e142b109d9bb
+ 64b272b25a3c184c
+ after
+ 57ca19058daf59e1.12f92d6ea4f34e35.9ecea874d8cfecb2.70da02c064595a0d
+ 7e6a9739021197e4.f6bbda94f04d0ae8.94c6f4e274691a7f.d64625b5522436c7
+ 0000000000000000.0000000000000000.70da02c064595a0d.d64625b5522436c7
+ fded10095e7196fb.59b964e5b463880e.2688108234e69faa.f466e142b109d9bb
+ 64b272b25a3c184c
+
+VUNPCKLPD_128(reg)
+ before
+ 39e2ca247a549b7d.0d69037c7d87ce68.908d39e86537c2d9.7bead78d90e16e5f
+ d140e502acde9ef9.77706a31b89b27a6.9baa14631bf69d5b.fdb214a3b9153f0e
+ 8718c0ba8c645c6d.19cfc1142aba5ddf.d75cefc0702d563d.88ac44b2cd8ccfe4
+ b7b856b6b7751284.ce528411f0ee2c42.9eefc86c0367292d.f7a3e1a4e554da0d
+ 286469671f791bb4
+ after
+ 0000000000000000.0000000000000000.88ac44b2cd8ccfe4.fdb214a3b9153f0e
+ d140e502acde9ef9.77706a31b89b27a6.9baa14631bf69d5b.fdb214a3b9153f0e
+ 8718c0ba8c645c6d.19cfc1142aba5ddf.d75cefc0702d563d.88ac44b2cd8ccfe4
+ b7b856b6b7751284.ce528411f0ee2c42.9eefc86c0367292d.f7a3e1a4e554da0d
+ 286469671f791bb4
+VUNPCKLPD_128(mem)
+ before
+ f6bb57e697054f06.bd6ba364c99afcec.71c4301425454ff9.4dae9ad46d3051d7
+ 3c74280d6807322f.f47ca32f5d61564e.e0f3400ae6cb8331.41e761634d150be7
+ d85b56c8ae887f5a.ba3852830f555b59.f6a930dd4e8a8415.d4e419853ca19308
+ a43c5f038696f4b3.6aebadcb7c0348b7.8eb37c7b7a910dd2.63f2bfa6d86025e6
+ 4a5d4d32bddffc2f
+ after
+ f6bb57e697054f06.bd6ba364c99afcec.71c4301425454ff9.4dae9ad46d3051d7
+ 3c74280d6807322f.f47ca32f5d61564e.e0f3400ae6cb8331.41e761634d150be7
+ 0000000000000000.0000000000000000.4dae9ad46d3051d7.41e761634d150be7
+ a43c5f038696f4b3.6aebadcb7c0348b7.8eb37c7b7a910dd2.63f2bfa6d86025e6
+ 4a5d4d32bddffc2f
+
+VUNPCKLPD_128(reg)
+ before
+ e571c19586a9558c.7ee2beaa0b3c4b68.5fe1af763ff65914.86dea0ce85e9db94
+ 907a173bd04a6cac.401bf0a95a8640a3.f76654edf5bac91d.b8f319c48ca0aa86
+ a7c34990364f7c39.c8b16fed8e819190.8dc6989d39dbd57e.02c16248aac136d4
+ 869955015443c3df.f071b960c438f85c.7c4c78f2a8e6b9e2.3e13f746fb583aac
+ 49b454aa9c727337
+ after
+ 0000000000000000.0000000000000000.02c16248aac136d4.b8f319c48ca0aa86
+ 907a173bd04a6cac.401bf0a95a8640a3.f76654edf5bac91d.b8f319c48ca0aa86
+ a7c34990364f7c39.c8b16fed8e819190.8dc6989d39dbd57e.02c16248aac136d4
+ 869955015443c3df.f071b960c438f85c.7c4c78f2a8e6b9e2.3e13f746fb583aac
+ 49b454aa9c727337
+VUNPCKLPD_128(mem)
+ before
+ 0072f660a91a9da4.894936f8c7b27b4c.952749f017b83233.2245ef59dd67b1f6
+ 3d1758543d5d731d.0c1de8e32b29e029.949e9b88a40bfb40.d9fdf93c75e8f866
+ dd70f6727446b2cf.6b62672c1b333025.c7a42b1386400eb0.ffc092090bf7cbdd
+ bd484ca76be116e5.0263af41335da5ea.0b03767fda6028ae.eedab62b3c1f6607
+ 0397620da3ed0492
+ after
+ 0072f660a91a9da4.894936f8c7b27b4c.952749f017b83233.2245ef59dd67b1f6
+ 3d1758543d5d731d.0c1de8e32b29e029.949e9b88a40bfb40.d9fdf93c75e8f866
+ 0000000000000000.0000000000000000.2245ef59dd67b1f6.d9fdf93c75e8f866
+ bd484ca76be116e5.0263af41335da5ea.0b03767fda6028ae.eedab62b3c1f6607
+ 0397620da3ed0492
+
+VUNPCKHPD_128(reg)
+ before
+ 9b42911dddece227.b76dd6dd3d3a5b8c.2d6ebd8d10327c24.3d89f7b7bb790567
+ 10293fc685a83c75.a8aa1102075e3cef.48cd8c7c4d3ef080.37002aa745966007
+ bf96687437ae4e26.6cca7801e458763b.afce187a870d3eaa.d6358b3b95c4f6b9
+ 05d60994908953e7.df9a87c5f135c59c.bdbb5ef3592ca24d.f6f39660c70e83aa
+ 7308c800f680c306
+ after
+ 0000000000000000.0000000000000000.afce187a870d3eaa.48cd8c7c4d3ef080
+ 10293fc685a83c75.a8aa1102075e3cef.48cd8c7c4d3ef080.37002aa745966007
+ bf96687437ae4e26.6cca7801e458763b.afce187a870d3eaa.d6358b3b95c4f6b9
+ 05d60994908953e7.df9a87c5f135c59c.bdbb5ef3592ca24d.f6f39660c70e83aa
+ 7308c800f680c306
+VUNPCKHPD_128(mem)
+ before
+ 293e9c083e2671f8.3c351c902cc58863.dde6ba3c4900e43d.d0e1585360265816
+ f4638e65bc0d4aac.c1fe9fd5a5ef2947.437a8e5109c5914b.438b040737889bb1
+ b1411b018c410a4f.f07f8dd09a92713e.eb227df04c9186f1.72075d797bdda8c9
+ 3aa5bdcac8cc6c0d.2502e3eba53b9ef5.b2a905062f6f7f5c.b8a05f17c7b1bb0b
+ 73a1074bb7901022
+ after
+ 293e9c083e2671f8.3c351c902cc58863.dde6ba3c4900e43d.d0e1585360265816
+ f4638e65bc0d4aac.c1fe9fd5a5ef2947.437a8e5109c5914b.438b040737889bb1
+ 0000000000000000.0000000000000000.dde6ba3c4900e43d.437a8e5109c5914b
+ 3aa5bdcac8cc6c0d.2502e3eba53b9ef5.b2a905062f6f7f5c.b8a05f17c7b1bb0b
+ 73a1074bb7901022
+
+VUNPCKHPD_128(reg)
+ before
+ fd575083e807e2bb.6b5bf2ab8fbc2e11.bcd59b946274e918.74dda17dcd6b3ab8
+ b40e362af6a26e82.222e3590fb1c0a88.1142b3366ecb9152.0d88ce4242917130
+ f212b5ac7cebf022.3aec026528f9bc9e.8096263c64ccd050.59770642abeee0f1
+ 15afc9741670a347.8f5fd516335e027e.651cf114e102e4bd.3376c767248e4526
+ 79518c9fc87b5afc
+ after
+ 0000000000000000.0000000000000000.8096263c64ccd050.1142b3366ecb9152
+ b40e362af6a26e82.222e3590fb1c0a88.1142b3366ecb9152.0d88ce4242917130
+ f212b5ac7cebf022.3aec026528f9bc9e.8096263c64ccd050.59770642abeee0f1
+ 15afc9741670a347.8f5fd516335e027e.651cf114e102e4bd.3376c767248e4526
+ 79518c9fc87b5afc
+VUNPCKHPD_128(mem)
+ before
+ 06d3d2d4b3c3dc9f.77306ff161bcc49f.fd542b8f37579655.1c220e2980f90646
+ b6ca13f40272873a.76e2a18cf95c8fd3.60977fbc50f1354e.01f27be8de3d7597
+ 6500cdead09216f9.6c125db279db4092.94f44d8a9c379a96.70da33bb965b6b5b
+ ee427ba23a31460a.b70a9fcf7dc51286.743711e334358259.c524320f44de253f
+ 5c1d74508652dfee
+ after
+ 06d3d2d4b3c3dc9f.77306ff161bcc49f.fd542b8f37579655.1c220e2980f90646
+ b6ca13f40272873a.76e2a18cf95c8fd3.60977fbc50f1354e.01f27be8de3d7597
+ 0000000000000000.0000000000000000.fd542b8f37579655.60977fbc50f1354e
+ ee427ba23a31460a.b70a9fcf7dc51286.743711e334358259.c524320f44de253f
+ 5c1d74508652dfee
+
+VUNPCKHPD_128(reg)
+ before
+ 9111f6ebf544d415.2f5c99085c5bd397.b1176150a2a7425c.de2c48b536f8a9c2
+ c04bb24b2f3f415f.031aa308501a79cc.b784a19f830c0cbf.ad9e6deabe8bcbfe
+ 4419a6dbd0d06279.4548168f357cf3d6.269f5a2abd80ab5c.bc5afc70e7faa338
+ 7bc5ce097382730f.d3b16c87248dfee1.58b2885ceb905dde.e92c7132cd52ef9d
+ 0fe0481c8d9e6858
+ after
+ 0000000000000000.0000000000000000.269f5a2abd80ab5c.b784a19f830c0cbf
+ c04bb24b2f3f415f.031aa308501a79cc.b784a19f830c0cbf.ad9e6deabe8bcbfe
+ 4419a6dbd0d06279.4548168f357cf3d6.269f5a2abd80ab5c.bc5afc70e7faa338
+ 7bc5ce097382730f.d3b16c87248dfee1.58b2885ceb905dde.e92c7132cd52ef9d
+ 0fe0481c8d9e6858
+VUNPCKHPD_128(mem)
+ before
+ 0942fe1a43ebcd96.c09c2440b4e1afcd.882324de3b585618.aa0b27a1aac75bf2
+ b51e0e180943d883.6feba6ec307a535d.3f68b77e96e9b6a8.78f4346495b1e444
+ ed3ff402feb4464a.e3fb4f7982d79a6e.d64da255504cdbbd.1ebaaa1348db327f
+ 8f732cc53c4ad318.7a1b1b534787c2aa.279e624e868e8182.f8a9851a61d08250
+ 630cc1e3791d1062
+ after
+ 0942fe1a43ebcd96.c09c2440b4e1afcd.882324de3b585618.aa0b27a1aac75bf2
+ b51e0e180943d883.6feba6ec307a535d.3f68b77e96e9b6a8.78f4346495b1e444
+ 0000000000000000.0000000000000000.882324de3b585618.3f68b77e96e9b6a8
+ 8f732cc53c4ad318.7a1b1b534787c2aa.279e624e868e8182.f8a9851a61d08250
+ 630cc1e3791d1062
+
+VUNPCKHPS_128(reg)
+ before
+ b9315adb2e4c1862.7584334bdf103a19.8e9606e61a1305be.1027725453ba6424
+ 57624d6e1cebd5fc.7d3f838104123978.7db70d9f9809a055.6bb34e55d3dc3fce
+ 99ec9509de8684db.81709a54c65c8962.a1cb2ae85cf4ce1c.1510723c2301cfad
+ db1b2e1610a860ac.5ee2f3af42fbe902.581f5b2f0361cdbe.eb085bf65f34d0ec
+ c768836da282fdb8
+ after
+ 0000000000000000.0000000000000000.a1cb2ae87db70d9f.5cf4ce1c9809a055
+ 57624d6e1cebd5fc.7d3f838104123978.7db70d9f9809a055.6bb34e55d3dc3fce
+ 99ec9509de8684db.81709a54c65c8962.a1cb2ae85cf4ce1c.1510723c2301cfad
+ db1b2e1610a860ac.5ee2f3af42fbe902.581f5b2f0361cdbe.eb085bf65f34d0ec
+ c768836da282fdb8
+VUNPCKHPS_128(mem)
+ before
+ 86fc688e08f6133d.793b14034fdda71a.f1630b7d93fa1385.fcfd9bde28dbd7e9
+ 05908645ae9ccea6.ce98443b36b193d2.14bd5cacd566c416.ebb1e76368ee2846
+ 1ef0577faf80ea20.387eb82a62b16180.a4be6427254ab8e2.7f893a295e27fe83
+ aee7592728af22d6.12386e3c6e684ccf.7d309eda9fb2ab15.15d08f9ca711934c
+ 0ad1e428de38244d
+ after
+ 86fc688e08f6133d.793b14034fdda71a.f1630b7d93fa1385.fcfd9bde28dbd7e9
+ 05908645ae9ccea6.ce98443b36b193d2.14bd5cacd566c416.ebb1e76368ee2846
+ 0000000000000000.0000000000000000.f1630b7d14bd5cac.93fa1385d566c416
+ aee7592728af22d6.12386e3c6e684ccf.7d309eda9fb2ab15.15d08f9ca711934c
+ 0ad1e428de38244d
+
+VUNPCKHPS_128(reg)
+ before
+ b8d935399f29ed31.91420728343433f5.b81361ddf763926c.7ce086b15eaa58da
+ 7c347c3b876f29a4.a3cedd70f01cd9a9.865b8e79982d6c02.7b9999997f3f7c5e
+ b32eb79a31961554.c15557ea7772cf1d.d75cef7cee52193e.5729527c1d7cd2cc
+ b713e1c33a2bedeb.c5a4f182e642d37e.09628252945ed4cb.ec5a2c47546e1851
+ 16faa6e741200819
+ after
+ 0000000000000000.0000000000000000.d75cef7c865b8e79.ee52193e982d6c02
+ 7c347c3b876f29a4.a3cedd70f01cd9a9.865b8e79982d6c02.7b9999997f3f7c5e
+ b32eb79a31961554.c15557ea7772cf1d.d75cef7cee52193e.5729527c1d7cd2cc
+ b713e1c33a2bedeb.c5a4f182e642d37e.09628252945ed4cb.ec5a2c47546e1851
+ 16faa6e741200819
+VUNPCKHPS_128(mem)
+ before
+ b1d33947ff9e5e4f.e52ef6203eb9ec15.8c86282458999ff7.77b9426827ded857
+ 99b26252abf5d820.99cdf21fd8cc4f7f.f2c977bcea82efb5.7dac2c28425d628b
+ aa639ef6603030b7.2f3ad22aa4f152d5.d3375a36b70981e4.76893a008268ad16
+ c0b1681e3b5b2341.03c291af3fb331c2.0b9d4e7fdb3b0faf.c09a6a5b828af6a1
+ b52cb7a4de4f79db
+ after
+ b1d33947ff9e5e4f.e52ef6203eb9ec15.8c86282458999ff7.77b9426827ded857
+ 99b26252abf5d820.99cdf21fd8cc4f7f.f2c977bcea82efb5.7dac2c28425d628b
+ 0000000000000000.0000000000000000.8c862824f2c977bc.58999ff7ea82efb5
+ c0b1681e3b5b2341.03c291af3fb331c2.0b9d4e7fdb3b0faf.c09a6a5b828af6a1
+ b52cb7a4de4f79db
+
+VUNPCKHPS_128(reg)
+ before
+ b38b1d493344726e.b76a3cb658836dea.71b12b19449f27f3.76c8cd8173235543
+ 140298b51df41c07.6b5897aad1b3c9dd.d5539cd4503f7113.ef82552a9bcd11cb
+ 36df255437ebb551.b848f4e6c4f7f447.8bf3e14cfe224bcf.549761646e45fd74
+ 736cbf931db576f9.7906ce564d5caa53.efdff4edebd1f1d3.80d56d1d0898d66a
+ 4f06f64086d258d8
+ after
+ 0000000000000000.0000000000000000.8bf3e14cd5539cd4.fe224bcf503f7113
+ 140298b51df41c07.6b5897aad1b3c9dd.d5539cd4503f7113.ef82552a9bcd11cb
+ 36df255437ebb551.b848f4e6c4f7f447.8bf3e14cfe224bcf.549761646e45fd74
+ 736cbf931db576f9.7906ce564d5caa53.efdff4edebd1f1d3.80d56d1d0898d66a
+ 4f06f64086d258d8
+VUNPCKHPS_128(mem)
+ before
+ 9df877b904fd3eeb.29f662dc6cdf9eaa.8c5ea3e787eda72e.5d61d323b2da9eca
+ 45756c749c2745ce.b2ca0a9cbff56711.cc1cef838fb6a603.31c6795aefc88f60
+ 254a515d6d5c29ae.6b31b340b3810eda.150c2c1880c46400.c75ae3ff3f27ff43
+ 1843a26091a7a6b6.b17a5a32e311cfb0.42f9d89076229d4e.7b690b7c3e842c1d
+ a83fef3f876a509a
+ after
+ 9df877b904fd3eeb.29f662dc6cdf9eaa.8c5ea3e787eda72e.5d61d323b2da9eca
+ 45756c749c2745ce.b2ca0a9cbff56711.cc1cef838fb6a603.31c6795aefc88f60
+ 0000000000000000.0000000000000000.8c5ea3e7cc1cef83.87eda72e8fb6a603
+ 1843a26091a7a6b6.b17a5a32e311cfb0.42f9d89076229d4e.7b690b7c3e842c1d
+ a83fef3f876a509a
+
+VMOVUPS_EtoG_128(reg)
+ before
+ ac278ab3b766a867.f92bdc6924147714.def0fae0ec31e640.31b06ed98edc0c1c
+ e26fd84368036f30.a6d0796542af59f1.4fde8fb5696b8e36.bdfd6adee4ff6e94
+ a661d65d39cde3a1.fafcf73e0985087c.6092151cf74d043d.c1ac498b93967fe2
+ 534a7e6cc4503d64.d07dd2e292a13fde.6e56898331638301.1b8985ccb7adfa33
+ a5609c8d6d519db3
+ after
+ ac278ab3b766a867.f92bdc6924147714.def0fae0ec31e640.31b06ed98edc0c1c
+ 0000000000000000.0000000000000000.6092151cf74d043d.c1ac498b93967fe2
+ a661d65d39cde3a1.fafcf73e0985087c.6092151cf74d043d.c1ac498b93967fe2
+ 534a7e6cc4503d64.d07dd2e292a13fde.6e56898331638301.1b8985ccb7adfa33
+ a5609c8d6d519db3
+VMOVUPS_EtoG_128(mem)
+ before
+ 3dfc09bad18d228d.4776cedca519bc28.061d843bfb0fbb46.d377e655b438492f
+ bd2b4840fd6e45ee.dd30c11979b49b97.76a88b3760dc38de.ec4028fe1b589073
+ 03b7d60910fec402.70c65490dbab155e.feec62c1dc1372d3.15ff4beb034f9479
+ e96d2e02234b59f4.5e8281ab688c6728.78b485c58cc12450.aaff4b8607aa93ec
+ 078b253cc3f4c778
+ after
+ 3dfc09bad18d228d.4776cedca519bc28.061d843bfb0fbb46.d377e655b438492f
+ bd2b4840fd6e45ee.dd30c11979b49b97.76a88b3760dc38de.ec4028fe1b589073
+ 03b7d60910fec402.70c65490dbab155e.feec62c1dc1372d3.15ff4beb034f9479
+ 0000000000000000.0000000000000000.061d843bfb0fbb46.d377e655b438492f
+ 078b253cc3f4c778
+
+VMOVUPS_EtoG_128(reg)
+ before
+ 88f0d47ad4b96dca.4d19cc185561c1f0.01b246d7bbe2cca2.c1cb702f8bf00b82
+ 897a54aad586c18e.09862c36bf4bb824.b7a09e81713a8177.b6ffa0ebf5afe394
+ 6675a13a63e6fe70.fa82ca477f15f9b9.da998514251fc255.311a8fe5e70767b3
+ 7b2db8951a66611b.fcd72339b1cb41de.c8e9f8fb741dcbe5.0fe9bb0a7c06540b
+ 2d37a044d1b766c7
+ after
+ 88f0d47ad4b96dca.4d19cc185561c1f0.01b246d7bbe2cca2.c1cb702f8bf00b82
+ 0000000000000000.0000000000000000.da998514251fc255.311a8fe5e70767b3
+ 6675a13a63e6fe70.fa82ca477f15f9b9.da998514251fc255.311a8fe5e70767b3
+ 7b2db8951a66611b.fcd72339b1cb41de.c8e9f8fb741dcbe5.0fe9bb0a7c06540b
+ 2d37a044d1b766c7
+VMOVUPS_EtoG_128(mem)
+ before
+ 65d2b88102275914.24ed93279590263b.ec53b1f7707a4cbd.dbdbf1a4f9c1d8d5
+ 948581ab2960e81e.bc03305c70f3897d.a4c0f26dd92dd582.70bd6e7a509624d1
+ 961b75b06571d010.a1b98ba04818c58d.01eb628807f1995b.e4d96ae91628ec85
+ 4761137bcf63cd16.2e5c9e5fb88d1716.df9f7b3216d15472.917ce15de7046b9c
+ d4f2d0425eb5dfc2
+ after
+ 65d2b88102275914.24ed93279590263b.ec53b1f7707a4cbd.dbdbf1a4f9c1d8d5
+ 948581ab2960e81e.bc03305c70f3897d.a4c0f26dd92dd582.70bd6e7a509624d1
+ 961b75b06571d010.a1b98ba04818c58d.01eb628807f1995b.e4d96ae91628ec85
+ 0000000000000000.0000000000000000.ec53b1f7707a4cbd.dbdbf1a4f9c1d8d5
+ d4f2d0425eb5dfc2
+
+VMOVUPS_EtoG_128(reg)
+ before
+ 0987320417c782a5.8423d4f886449a5d.bf3867055dddbac5.1aaabb5823d9c2f3
+ 8d870310afc790ee.272d3512a31ff511.af99e0fed295ec46.8fd69de64a169e0b
+ ba3d3fd0c240474c.0d4bb3b84401975e.5ccb07b7b33fe744.18f19dc9a693a5e6
+ edf7e2b2ebbee169.1248c9d385f53f6f.2119d89a9e6ae86c.92c537ec535c93af
+ d91fe83a6e7d2393
+ after
+ 0987320417c782a5.8423d4f886449a5d.bf3867055dddbac5.1aaabb5823d9c2f3
+ 0000000000000000.0000000000000000.5ccb07b7b33fe744.18f19dc9a693a5e6
+ ba3d3fd0c240474c.0d4bb3b84401975e.5ccb07b7b33fe744.18f19dc9a693a5e6
+ edf7e2b2ebbee169.1248c9d385f53f6f.2119d89a9e6ae86c.92c537ec535c93af
+ d91fe83a6e7d2393
+VMOVUPS_EtoG_128(mem)
+ before
+ c9cb2ba1120313bd.82ffe921c6ce9bf2.12f2f3508107a770.59d04d152c9f2a69
+ 3e947c0c5cfa1d5a.d5a24e88f0fbb192.e913ae1b55448d8e.623d6493fb6cebe8
+ 13485767676cfd95.422c0f5504d25ef6.737874211cb7aaf5.97aa187fa75c6594
+ 26b1389e5067719c.25e928f39fdddfc9.8cedc34cf26cbdd0.53636547cbfcd41b
+ f4b6475603d77626
+ after
+ c9cb2ba1120313bd.82ffe921c6ce9bf2.12f2f3508107a770.59d04d152c9f2a69
+ 3e947c0c5cfa1d5a.d5a24e88f0fbb192.e913ae1b55448d8e.623d6493fb6cebe8
+ 13485767676cfd95.422c0f5504d25ef6.737874211cb7aaf5.97aa187fa75c6594
+ 0000000000000000.0000000000000000.12f2f3508107a770.59d04d152c9f2a69
+ f4b6475603d77626
+
+VADDPS_256(reg)
+ before
+ d4eebb18ec798564.529c9c9d32f73398.da2593ce5caa70b8.0f3e168af470804c
+ 5056bcf9226f3e7e.73d5fe512a2600b8.bd2b4e52d8c54c6e.da36e9c63eceb095
+ c53b46663f44dc23.6528daa453029326.2a4854ebaeb9b199.c8a3b9ebea9209d6
+ 8de955c9e2849dfd.0461ac83ca97a90e.7dc8a1067a12d8e2.b54f00e717c9463c
+ 7c073ca5df7e24f2
+ after
+ 5056bcf63f44dc23.73d5fe5153029326.bd2b4e52d8c54c6e.da36e9c6ea9209d6
+ 5056bcf9226f3e7e.73d5fe512a2600b8.bd2b4e52d8c54c6e.da36e9c63eceb095
+ c53b46663f44dc23.6528daa453029326.2a4854ebaeb9b199.c8a3b9ebea9209d6
+ 8de955c9e2849dfd.0461ac83ca97a90e.7dc8a1067a12d8e2.b54f00e717c9463c
+ 7c073ca5df7e24f2
+VADDPS_256(mem)
+ before
+ fb97e9115ebd5f25.06ace58fa5bcbbb9.2b4cf1dbaaeffe9d.12f7310dd95c00f8
+ 0dcb8118b193b301.8ad0f32524777202.b8b423970f184eff.4521016e67246485
+ 8e6f81a4f30bdbb1.76a17af6fc410085.8666c0a2161e545f.71920c93bff53f35
+ 594e66a241319461.266a766dc8a79fed.702e44eadb0bceea.f4954eea7d5ccdb5
+ 2978c3de3ee44cb1
+ after
+ fb97e9115ebd5f25.06ace58fa5bcbbb9.2b4cf1dbaaeffe9d.12f7310dd95c00f8
+ 0dcb8118b193b301.8ad0f32524777202.b8b423970f184eff.4521016e67246485
+ fb97e9115ebd5f25.8ad0463fa59dcd79.b8b42397aaeffe9d.4521016e67246485
+ 594e66a241319461.266a766dc8a79fed.702e44eadb0bceea.f4954eea7d5ccdb5
+ 2978c3de3ee44cb1
+
+VADDPS_256(reg)
+ before
+ 6b8567db9e19f6d4.4c36abffb6129a3f.f778e3f825348ce7.54d8295a79ed75cc
+ 1809374c388708cb.41f1cca56eb9a875.4317be02ae74031f.0c30edde0cd00830
+ 8b502ea0a8bbbe42.164c468287327b2f.679302f7fff43f40.76020a62b1bf4143
+ 1fa648408b4153e4.a51394811a8acf9a.bf38ab43b53f7df7.6c19fed283c6dd30
+ cc43451b9ff19824
+ after
+ 1809374c388708cb.41f1cca56eb9a875.679302f7fff43f40.76020a62b1bf4143
+ 1809374c388708cb.41f1cca56eb9a875.4317be02ae74031f.0c30edde0cd00830
+ 8b502ea0a8bbbe42.164c468287327b2f.679302f7fff43f40.76020a62b1bf4143
+ 1fa648408b4153e4.a51394811a8acf9a.bf38ab43b53f7df7.6c19fed283c6dd30
+ cc43451b9ff19824
+VADDPS_256(mem)
+ before
+ 704a5927204d2d4a.325681997ca3045e.cc12318e45cc60e2.a752b5526ce1f9ef
+ 36fbb8e423e55acf.1eaed617186f0d5b.65149c952405e932.7b2c1c91bf67eed5
+ f822dd3cc3c6d8df.41f84227fa30aa88.4ee74e82d24027b7.9714dd6a4a5c9955
+ 938a441d1dfa66a5.f581c133bf731690.6155c4416b89d69d.5754f34baa4d361a
+ 17395a9e7bc401d1
+ after
+ 704a5927204d2d4a.325681997ca3045e.cc12318e45cc60e2.a752b5526ce1f9ef
+ 36fbb8e423e55acf.1eaed617186f0d5b.65149c952405e932.7b2c1c91bf67eed5
+ 704a592723e6f52a.325681997ca3045e.65149c9545cc60e2.7b2c1c916ce1f9ef
+ 938a441d1dfa66a5.f581c133bf731690.6155c4416b89d69d.5754f34baa4d361a
+ 17395a9e7bc401d1
+
+VADDPS_256(reg)
+ before
+ 330f0ed158503525.e40169724c90be4e.98954fa902c38e20.7b2b7bbe0cecb10f
+ 07220c4fdd7a0fc3.c551c9266d919d06.8480e8f460ac4ee4.7935eee5d1767539
+ efbd4f83a7d0cb57.1348df279b0bbff8.178e897f74bb9187.353f99a3d432de48
+ 472ed2db51dda58c.abb02760f209e050.ab0a2db8da7b95b6.8c15f9e2342da868
+ 5a8288900b728ec5
+ after
+ efbd4f83dd7a0fc3.c551c9266d919d06.178e897f74bb9187.7935eee5d436b81d
+ 07220c4fdd7a0fc3.c551c9266d919d06.8480e8f460ac4ee4.7935eee5d1767539
+ efbd4f83a7d0cb57.1348df279b0bbff8.178e897f74bb9187.353f99a3d432de48
+ 472ed2db51dda58c.abb02760f209e050.ab0a2db8da7b95b6.8c15f9e2342da868
+ 5a8288900b728ec5
+VADDPS_256(mem)
+ before
+ 7b53c497750d4d8a.6bbf94c2782dd80f.67561dbe8f98bb3b.9d41d00a2f78931d
+ cc5528e58f0aa1e3.b6bd8ea5b74da18b.24053e2b8ec30de5.4a806ee10f3fca67
+ 27523165747645fe.8674beeeabc83cad.be8b04940a96917a.0c1103aa155b7440
+ 69175903405cf704.36301e0aef2be420.11b2ede61f1d0525.40408ccfdd58ce56
+ 425b04bd04c31452
+ after
+ 7b53c497750d4d8a.6bbf94c2782dd80f.67561dbe8f98bb3b.9d41d00a2f78931d
+ cc5528e58f0aa1e3.b6bd8ea5b74da18b.24053e2b8ec30de5.4a806ee10f3fca67
+ 7b53c497750d4d8a.6bbf94c2782dd80f.67561dbe8fc97eb4.4a806ee12f78931d
+ 69175903405cf704.36301e0aef2be420.11b2ede61f1d0525.40408ccfdd58ce56
+ 425b04bd04c31452
+
+VSUBPS_256(reg)
+ before
+ 6fad67e1262782e3.6e6f1eab11c97024.213cad662001d691.f948740bea652312
+ 2181b2a5de1053b3.1228fb4900c86f88.a5e6646cd9d64eac.521716f18779a76e
+ b524df77c80bc46f.310c6cca2b65ae5c.1d78408ab737881c.f8ec4d8211664f65
+ 87e2ecc281a310c2.a7e9ed18aeadebce.e43f3e2a55afbf8e.c79397aca437d523
+ 9bd76f5a5df8f6d3
+ after
+ 3524df77de1053b3.b10c6ccaab65ae5c.a5e664e8d9d64eac.78ec4d8291664f75
+ 2181b2a5de1053b3.1228fb4900c86f88.a5e6646cd9d64eac.521716f18779a76e
+ b524df77c80bc46f.310c6cca2b65ae5c.1d78408ab737881c.f8ec4d8211664f65
+ 87e2ecc281a310c2.a7e9ed18aeadebce.e43f3e2a55afbf8e.c79397aca437d523
+ 9bd76f5a5df8f6d3
+VSUBPS_256(mem)
+ before
+ 5086517857b66ea1.f307d4f1a4647559.5089fb20a4abdf07.588759ba4fca30ae
+ c26abaf2af7cf8ba.55df9372cedb2ddf.08b911cf296b4936.d39c8da542141727
+ cd5024b48056514a.09b626b09a937501.aa44ab105afae385.b3cad657ca1aafa6
+ 4d040dabe651357c.6bd78818a519886a.14f845ce53636a20.525c313c826835d6
+ 0ea099c00688e564
+ after
+ 5086517857b66ea1.f307d4f1a4647559.5089fb20a4abdf07.588759ba4fca30ae
+ c26abaf2af7cf8ba.55df9372cedb2ddf.08b911cf296b4936.d39c8da542141727
+ d0865178d7b66ea1.7307d4f1cedb2ddf.d089fb20296b9f26.d88780ddcfca30ae
+ 4d040dabe651357c.6bd78818a519886a.14f845ce53636a20.525c313c826835d6
+ 0ea099c00688e564
+
+VSUBPS_256(reg)
+ before
+ 41e00a4ff308fbfb.1d52f0c1ff78607d.d790b4148af8a3c8.219f5cf72fb29a34
+ 49698056e474b248.1b064ae3e4d78d79.a92ba911e5bc02c4.ad076a760af42eed
+ 8087f83f765647f7.22ec95feb37b799b.3cf5607b53f1e10d.94faed370134e376
+ 43866c78443cf6b3.0dcf4ffd886fdf10.ee3ad6bf70247b4d.b14560262f7e75fc
+ e2b4402fb1dfa0ab
+ after
+ 49698056f65647f7.a2ec94f1e4d78d79.bcf5607be5bc02c4.ad076a760af42ed6
+ 49698056e474b248.1b064ae3e4d78d79.a92ba911e5bc02c4.ad076a760af42eed
+ 8087f83f765647f7.22ec95feb37b799b.3cf5607b53f1e10d.94faed370134e376
+ 43866c78443cf6b3.0dcf4ffd886fdf10.ee3ad6bf70247b4d.b14560262f7e75fc
+ e2b4402fb1dfa0ab
+VSUBPS_256(mem)
+ before
+ 0212073fa2621fae.eeb1da6bebb2fa29.ba7cf3cb7ebf7d03.1a450848d7e00d30
+ ec2d33401f13af32.de563d8606429005.04bffd56b1780da1.1c64f18124b2d363
+ 7ecf3f1f43ff0c62.6dbf9234327af4f2.c664e9893ea54c16.50e18dd8f4250992
+ 92c6a7c92b31f16b.f839d3e10ae6629c.de3734504153f58d.1109d9b8e3c5ea68
+ bd28d08d8c1eb392
+ after
+ 0212073fa2621fae.eeb1da6bebb2fa29.ba7cf3cb7ebf7d03.1a450848d7e00d30
+ ec2d33401f13af32.de563d8606429005.04bffd56b1780da1.1c64f18124b2d363
+ ec2d334022646e6b.6eb1da6b6bb2fa29.3a7cf3cbfebf7d03.1c58a0fc57e00d30
+ 92c6a7c92b31f16b.f839d3e10ae6629c.de3734504153f58d.1109d9b8e3c5ea68
+ bd28d08d8c1eb392
+
+VSUBPS_256(reg)
+ before
+ af8a6dc38bbda0bc.06dce829f2b61b78.db10fef92b1015b0.26045997d58cc632
+ 427bafc67d2dec91.b4de7c2ab49846b6.72900ee830864ada.7c96d44a165e7933
+ d4478f02fdfbd4be.7a97e1ba8ee52e51.1905ff1ab5d43dc6.babb215621d5cab9
+ bf390ae4a8b294ee.32d592c49ca98e74.2dbacdfc5785291f.be3dbda511fc77f3
+ 62e9222503df3a0b
+ after
+ 54478f027e296583.fa97e1bab49846b6.72900ee835d45f59.7c96d44aa1d5cab7
+ 427bafc67d2dec91.b4de7c2ab49846b6.72900ee830864ada.7c96d44a165e7933
+ d4478f02fdfbd4be.7a97e1ba8ee52e51.1905ff1ab5d43dc6.babb215621d5cab9
+ bf390ae4a8b294ee.32d592c49ca98e74.2dbacdfc5785291f.be3dbda511fc77f3
+ 62e9222503df3a0b
+VSUBPS_256(mem)
+ before
+ 848bcec0128ad02e.619e1dd619de68ce.ba620c34f9ef234c.08fd75f8b2254c91
+ feee3c645b0af487.14c2c346ed0c8b09.ec0cc9f6c1c3a905.0718f27b6140e0c9
+ ade0e9fcf96a6443.36f1f89ebfc73a4c.a59d47f71131dbca.865840f200632173
+ 6e2b4f7408b7da8d.2177b94c2c9bb143.c2e20121054676c7.e0095bc82c194d3b
+ 7376406881ee9ecc
+ after
+ 848bcec0128ad02e.619e1dd619de68ce.ba620c34f9ef234c.08fd75f8b2254c91
+ feee3c645b0af487.14c2c346ed0c8b09.ec0cc9f6c1c3a905.0718f27b6140e0c9
+ feee3c645b0af487.e19e1dd6ed0c8b09.ec0cc9f679ef234c.88ea57a96140e0c9
+ 6e2b4f7408b7da8d.2177b94c2c9bb143.c2e20121054676c7.e0095bc82c194d3b
+ 7376406881ee9ecc
+
+VMULPS_256(reg)
+ before
+ 9aedea40996f50d2.1b9decb7a6fc1392.33a000bbcf152b99.1da77361b80d362a
+ b1b855bb1327a1fa.91003bb4ec45ca7e.c6b7cb5744c0e5fb.93b71aa44693d71d
+ 14257d4589a3cbf0.ac21b854f89ebc7c.370a158c28281b15.00e070d4cce314cc
+ 1f7e5e4a976e0b5f.48cbe084e614a5b9.e2e3dbc617da0992.40ecf3df6509aa64
+ 30a81eb02e115511
+ after
+ 866e52ea80000000.0002880f7f800000.be46462a2d7d56aa.80000000d40323c1
+ b1b855bb1327a1fa.91003bb4ec45ca7e.c6b7cb5744c0e5fb.93b71aa44693d71d
+ 14257d4589a3cbf0.ac21b854f89ebc7c.370a158c28281b15.00e070d4cce314cc
+ 1f7e5e4a976e0b5f.48cbe084e614a5b9.e2e3dbc617da0992.40ecf3df6509aa64
+ 30a81eb02e115511
+VMULPS_256(mem)
+ before
+ aae06e334208d0fe.2d10f537d9149df4.42cc2e30d1b24160.248f1771ac61ea1e
+ 8b605d54befad958.9c263d76ed21bc5b.74ee1e45d5854b9e.575ac7f98349fb67
+ aff469ffbdf1294a.c70e32746c22a53f.bbff2cad0f98809f.d88fe6cb391f7816
+ f2670d205bfb7f01.0913d09ef4a3944d.f3c9d4569af79c8e.037c70516a6e9cda
+ 346b61f9b0c2a55d
+ after
+ aae06e334208d0fe.2d10f537d9149df4.42cc2e30d1b24160.248f1771ac61ea1e
+ 8b605d54befad958.9c263d76ed21bc5b.74ee1e45d5854b9e.575ac7f98349fb67
+ 0000000cc1861040.89bc439e7f800000.783deb1567b9a13c.3c74937900000000
+ f2670d205bfb7f01.0913d09ef4a3944d.f3c9d4569af79c8e.037c70516a6e9cda
+ 346b61f9b0c2a55d
+
+VMULPS_256(reg)
+ before
+ c8aab62daaa8cc4b.3087c5a3b52395a9.c080135e212ec530.f819932b93af5a98
+ 19836a5bf2ab5052.451e0d74e776296d.47a2f8228e517395.a6bbe31716cb78e8
+ 844379ee24576b1b.0df962800cfff47a.f9c57a55d897db27.d97a42083d57b0ab
+ 6535df52dd395b55.64e43fb140cab5fb.343595639a8d3993.6d242ce92760be0d
+ 3d831ba6edf16039
+ after
+ 80000000d7902822.1399f7e6b4f61e58.ff80000027787cf5.40b7ac3b14ab6ef6
+ 19836a5bf2ab5052.451e0d74e776296d.47a2f8228e517395.a6bbe31716cb78e8
+ 844379ee24576b1b.0df962800cfff47a.f9c57a55d897db27.d97a42083d57b0ab
+ 6535df52dd395b55.64e43fb140cab5fb.343595639a8d3993.6d242ce92760be0d
+ 3d831ba6edf16039
+VMULPS_256(mem)
+ before
+ 27648d2bad16505c.18a798f3b8dc59aa.25ab20f5a0e4261d.523e46b870bec885
+ 0693fc6583dc4ba1.f9e4a13d51cda4c6.2e1981374858040b.b12b87c0f7b6c5a8
+ b6dce73e8a4e0c35.6437f59c46967657.5afcde6353320bf3.ab4a56e7ca026ca9
+ 130bc7a4df785044.b4ed907c30c60c06.851eb465dd7ff6fe.9de5ae99862df934
+ e4498b43c7c3a7f4
+ after
+ 27648d2bad16505c.18a798f3b8dc59aa.25ab20f5a0e4261d.523e46b870bec885
+ 0693fc6583dc4ba1.f9e4a13d51cda4c6.2e1981374858040b.b12b87c0f7b6c5a8
+ 0000000000000000.d315adc8cb3101a1.144d3a26a9c083c3.c3fefc46ff800000
+ 130bc7a4df785044.b4ed907c30c60c06.851eb465dd7ff6fe.9de5ae99862df934
+ e4498b43c7c3a7f4
+
+VMULPS_256(reg)
+ before
+ dac2ea4f2751b395.f8ec19819d67d3f9.47526f4aade6a282.8b4c7e29034a825b
+ dd9cc52b456259c5.434a5ac3e0265180.78b28c7059847375.4752b89be09f6b34
+ 47221a41ba82d42e.cff20554c5c18507.a358e55ccf2bbc8b.97fcdfa7918b6db5
+ 75a2e4ff253e627c.77b0962268452db8.24927579ab68b971.56166d393119430b
+ 5f6be03ddd55aa62
+ after
+ e54689b2c0675a62.d3bf4e03667b73bd.dc974676e931b558.9fd025d132ada70d
+ dd9cc52b456259c5.434a5ac3e0265180.78b28c7059847375.4752b89be09f6b34
+ 47221a41ba82d42e.cff20554c5c18507.a358e55ccf2bbc8b.97fcdfa7918b6db5
+ 75a2e4ff253e627c.77b0962268452db8.24927579ab68b971.56166d393119430b
+ 5f6be03ddd55aa62
+VMULPS_256(mem)
+ before
+ 90c9b3a0b04c5ee5.c36620d01f213c5c.19508a18e4bd02bf.56aa38328ac5a5d3
+ c3fa624dc7091ac1.8dbbc82047b7a17a.8f9e5b225535c349.97ee2bf508d1be5c
+ d6cb6a2f3d999b22.30edda5b368dcb81.b766872cd8ba2a82.42a8482dc0153eb9
+ a30845342f069d33.064851ed8a2ef71e.6c7389238957f495.b2258d464e1f6196
+ 45b0f5ac4f7a659e
+ after
+ 90c9b3a0b04c5ee5.c36620d01f213c5c.19508a18e4bd02bf.56aa38328ac5a5d3
+ c3fa624dc7091ac1.8dbbc82047b7a17a.8f9e5b225535c349.97ee2bf508d1be5c
+ 154546de37dae849.11a8cdde27674fb3.80000000fa863320.af1e5d7980000000
+ a30845342f069d33.064851ed8a2ef71e.6c7389238957f495.b2258d464e1f6196
+ 45b0f5ac4f7a659e
+
+VDIVPS_256(reg)
+ before
+ 56977ccc5eb3847e.087d7147b85fdc20.6c172942df2661fc.8993ddf18218ddaf
+ 40241f101855fbe1.dff56954f4ad1317.bea85fc6d00245c8.eb900083e20aa0fc
+ 61a5d9e518ec0574.063eaa4700feff41.5845ede6f94dde2e.6f376dc6c238fba7
+ 1364a6b8fb05e0e2.5722ae0cf85d5ccd.963cd10cf79369d9.ef54a0a441afa7dc
+ 49b2150b787a63c9
+ after
+ 1dfd54773ee818e1.ff800000ff800000.a5d9c60a1621fefc.bbc8f9795f3fd997
+ 40241f101855fbe1.dff56954f4ad1317.bea85fc6d00245c8.eb900083e20aa0fc
+ 61a5d9e518ec0574.063eaa4700feff41.5845ede6f94dde2e.6f376dc6c238fba7
+ 1364a6b8fb05e0e2.5722ae0cf85d5ccd.963cd10cf79369d9.ef54a0a441afa7dc
+ 49b2150b787a63c9
+VDIVPS_256(mem)
+ before
+ 571f48e685a5e998.b4ae82f45c2bc6d8.af6ef38ff6d6e5e5.d4d706a666612176
+ f665b621843cf675.9ece6904d8eaf302.ebeef4bc197657b6.6e62891ee14244b0
+ 0252daa8904c468d.2e1258560acfa50b.e56e2d807b486e6b.c02b54e204c30c34
+ 58b03067c6e0950c.c1c54a558e6516a0.7aba1bc53859e631.267d655d6c6fb6ae
+ fba3b7fbb4d27dc9
+ after
+ 571f48e685a5e998.b4ae82f45c2bc6d8.af6ef38ff6d6e5e5.d4d706a666612176
+ f665b621843cf675.9ece6904d8eaf302.ebeef4bc197657b6.6e62891ee14244b0
+ deb898263e11c877.2997659cbc2f12be.7c0000a180000000.d906d9f7ba5ce7e5
+ 58b03067c6e0950c.c1c54a558e6516a0.7aba1bc53859e631.267d655d6c6fb6ae
+ fba3b7fbb4d27dc9
+
+VDIVPS_256(reg)
+ before
+ 9dea462879789e31.d24c344a41059e1d.b1323b6d0138836d.869d38796db47a33
+ 679f0e5056ee5594.4df1623d1dc61eed.5ba6270affd5281d.e6e502873565e79e
+ b50b0cdfe8bfde9c.a56d372c772fd0a7.1c6d0b9823c7405c.745cf4daad79e99e
+ e27d3b42ca7875f5.b68a2e046b4d7278.4ed3e183099a08d8.0dcf8a60f0fb3b5e
+ 8d0a41041bf79b0b
+ after
+ f2126a71ad9eff5f.e8023fc800000000.7eb3703effd5281d.b204aa54c76b813d
+ 679f0e5056ee5594.4df1623d1dc61eed.5ba6270affd5281d.e6e502873565e79e
+ b50b0cdfe8bfde9c.a56d372c772fd0a7.1c6d0b9823c7405c.745cf4daad79e99e
+ e27d3b42ca7875f5.b68a2e046b4d7278.4ed3e183099a08d8.0dcf8a60f0fb3b5e
+ 8d0a41041bf79b0b
+VDIVPS_256(mem)
+ before
+ d0d894b24979c2d0.4c4097e399a4554c.5c16c3af142bbe8c.4e24a7384edbbc3a
+ b207ff56978e6fda.4e9f1c30f0cfba4d.73db721b8ed5700e.78ab59218e159731
+ 0f61fedd20425c55.43e8c7936b85e2a3.d7a6b833f657462b.28b6f1ac63d4d667
+ c3b40d31009f476c.8965927aa85307fb.644310e267befa0e.ba8f6c446ca5b588
+ 8a83c75442137042
+ after
+ d0d894b24979c2d0.4c4097e399a4554c.5c16c3af142bbe8c.4e24a7384edbbc3a
+ b207ff56978e6fda.4e9f1c30f0cfba4d.73db721b8ed5700e.78ab59218e159731
+ 20a0bff68d91feb7.41d37e477f800000.573a4f99ba1f12e7.6a053461800ae476
+ c3b40d31009f476c.8965927aa85307fb.644310e267befa0e.ba8f6c446ca5b588
+ 8a83c75442137042
+
+VDIVPS_256(reg)
+ before
+ f5defd4a84aa423e.aacaa94054b3e94c.7a637b5040c56601.f67df616fe1649e4
+ 55ec0b91cbf7682b.a0704df438890120.742e7d81d1653b60.6922e6bad669efd9
+ 06f8eb95b6851eb3.8171753bc72e4915.d2119579f7c1c1c5.99fc5cba0cc5a718
+ 66509bc2dee1a082.289b9dff1dad7e57.ef5abda44c6436db.62d8d503bb362ece
+ a083cc7f00c64026
+ after
+ 7f80000054ede433.5e7ec6f0b0c93d51.e1996a3e19176f81.ff800000ff800000
+ 55ec0b91cbf7682b.a0704df438890120.742e7d81d1653b60.6922e6bad669efd9
+ 06f8eb95b6851eb3.8171753bc72e4915.d2119579f7c1c1c5.99fc5cba0cc5a718
+ 66509bc2dee1a082.289b9dff1dad7e57.ef5abda44c6436db.62d8d503bb362ece
+ a083cc7f00c64026
+VDIVPS_256(mem)
+ before
+ 2ec6bd1bf683994d.d03e1684e2952946.73b8412e57125c11.2853f36e6fdbd34f
+ ea7024c4ba79f46e.a00f58485b2ff6a8.3d96deb3906a9e6f.da4a3243fab1d7cc
+ af4c7e6467b20eb6.320f5d78e73b4257.62ffef7ae5c0019f.5f89769089727cff
+ 592546e9193ca251.e28a228222444bfd.bdc0f06f712041cb.155dbcbfb9abff94
+ 5611fe3e25e79c36
+ after
+ 2ec6bd1bf683994d.d03e1684e2952946.73b8412e57125c11.2853f36e6fdbd34f
+ ea7024c4ba79f46e.a00f58485b2ff6a8.3d96deb3906a9e6f.da4a3243fab1d7cc
+ fb1aaad603731e8a.0f410c89b816fff9.09519dad800000cd.f17437daca4f1bdf
+ 592546e9193ca251.e28a228222444bfd.bdc0f06f712041cb.155dbcbfb9abff94
+ 5611fe3e25e79c36
+
+VPCMPGTQ_128(reg)
+ before
+ 7ff33a776ab28f92.c3c8f73eed236e6b.0ccca1d0a7d64b46.2ca55d7e51971a1f
+ ec4d6bd823991353.cb02104eff712c2e.0b20d8d0127d7fdf.8a79b394a03047c8
+ fa6d8ecced276526.4b9c0a076a3499c9.3dd4c3ed00c62274.b20a6d9b7bf885f2
+ 039d9dbf63e8c0b7.216563544a787066.fd325c930d3d71b0.82220781fdf990c8
+ d48ffd3043412377
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ ec4d6bd823991353.cb02104eff712c2e.0b20d8d0127d7fdf.8a79b394a03047c8
+ fa6d8ecced276526.4b9c0a076a3499c9.3dd4c3ed00c62274.b20a6d9b7bf885f2
+ 039d9dbf63e8c0b7.216563544a787066.fd325c930d3d71b0.82220781fdf990c8
+ d48ffd3043412377
+VPCMPGTQ_128(mem)
+ before
+ 861bcc9668dcfb2b.642a961d226962b1.28289621bc486f32.a787a12dd36ca840
+ 7293ee9e89d5d40f.79607452c53585c1.3bb01f5bdbb05058.961f8d2af1e103d0
+ 76c2e133c1386a50.9e8a33cae8d96593.38cb7aecc4bccf05.28461cf30127be0b
+ 6c7620432c117819.2ff6d0f128df40d2.f94323c19279aa64.b7474af59fcb149e
+ a170149c68584234
+ after
+ 861bcc9668dcfb2b.642a961d226962b1.28289621bc486f32.a787a12dd36ca840
+ 7293ee9e89d5d40f.79607452c53585c1.3bb01f5bdbb05058.961f8d2af1e103d0
+ 0000000000000000.0000000000000000.ffffffffffffffff.0000000000000000
+ 6c7620432c117819.2ff6d0f128df40d2.f94323c19279aa64.b7474af59fcb149e
+ a170149c68584234
+
+VPCMPGTQ_128(reg)
+ before
+ 400b7455f75a837a.327928b9e76dbb97.88ee453421d5502a.5be597c762f29ba2
+ f265688ae95e141b.a29973810e57eff5.05bf90fd6e47d248.3b7d51e84f345feb
+ 11caeca9d9ef31c4.99a07f88bcdccf60.02b5acbaabc002d8.73d6cd127649b16a
+ fb86fa1d63991621.f45bc7b80d061804.db1c96d575cc1b85.e0be8830f23f4f4c
+ 5ffffc2ee022f3bd
+ after
+ 0000000000000000.0000000000000000.ffffffffffffffff.0000000000000000
+ f265688ae95e141b.a29973810e57eff5.05bf90fd6e47d248.3b7d51e84f345feb
+ 11caeca9d9ef31c4.99a07f88bcdccf60.02b5acbaabc002d8.73d6cd127649b16a
+ fb86fa1d63991621.f45bc7b80d061804.db1c96d575cc1b85.e0be8830f23f4f4c
+ 5ffffc2ee022f3bd
+VPCMPGTQ_128(mem)
+ before
+ ca67a7f85bfd5ae8.0ae4905125e8ffdd.8d96c7fe1ee4860c.ec4048bc67f75afc
+ fec0047a7fdc3ff9.9b32a8b3b86927a5.411cfb470a7fd5a5.916dc0da1ecefbe9
+ d7d78fa069cc5f1e.0bba41aebaa8cb25.ecbbe07eeee5c0fa.26eef99b36dc39f7
+ 3277c55635d77680.b4c954aec72f2608.6b3df18ee5210438.0610ef6b49ae52d3
+ 8f1f9eb6f6cf8028
+ after
+ ca67a7f85bfd5ae8.0ae4905125e8ffdd.8d96c7fe1ee4860c.ec4048bc67f75afc
+ fec0047a7fdc3ff9.9b32a8b3b86927a5.411cfb470a7fd5a5.916dc0da1ecefbe9
+ 0000000000000000.0000000000000000.ffffffffffffffff.0000000000000000
+ 3277c55635d77680.b4c954aec72f2608.6b3df18ee5210438.0610ef6b49ae52d3
+ 8f1f9eb6f6cf8028
+
+VPCMPGTQ_128(reg)
+ before
+ 1c6703e8d6cbffa3.e96e2088fe0c404e.f3abde207a8c76fa.986faa650c405d8b
+ 0934196e882e0df0.d9861e23e07478b2.25acdc6e6f4bf5a9.501d87ee7e4d861e
+ b1d2dcb2a585e4ba.de8d3a11f81ddbd8.a418490543f6dfbe.6f13051558543d1e
+ 728c4822cb5bc1ae.d44df140621225ee.cd3b2152911c72e8.d11d9fc6b5613bb6
+ 5206d0edb2813f13
+ after
+ 0000000000000000.0000000000000000.ffffffffffffffff.0000000000000000
+ 0934196e882e0df0.d9861e23e07478b2.25acdc6e6f4bf5a9.501d87ee7e4d861e
+ b1d2dcb2a585e4ba.de8d3a11f81ddbd8.a418490543f6dfbe.6f13051558543d1e
+ 728c4822cb5bc1ae.d44df140621225ee.cd3b2152911c72e8.d11d9fc6b5613bb6
+ 5206d0edb2813f13
+VPCMPGTQ_128(mem)
+ before
+ ce9c17766ac00361.a7af5a28963ddf77.9793bd9b3960111d.fc6061bff646e8d1
+ 21a9ed4ef92845cb.ab880c32a1b67cc2.032b1c0d99125d94.8dd403ba0e027e25
+ 27fad05f7cc7be7e.dc615cab8952d23a.f4e089849f34c37d.dce305ae73db7092
+ bc5b3a970fa92da5.948645ffe89e1d8c.468080eb66d3ff04.45d96206c45df9c1
+ 240216309a155661
+ after
+ ce9c17766ac00361.a7af5a28963ddf77.9793bd9b3960111d.fc6061bff646e8d1
+ 21a9ed4ef92845cb.ab880c32a1b67cc2.032b1c0d99125d94.8dd403ba0e027e25
+ 0000000000000000.0000000000000000.ffffffffffffffff.0000000000000000
+ bc5b3a970fa92da5.948645ffe89e1d8c.468080eb66d3ff04.45d96206c45df9c1
+ 240216309a155661
+
+VPEXTRQ_128_0x0(reg)
+ before
+ d5aa1e97948ec31c.bc98a9e0cdd84c6d.3145c49a5d259b64.d5d57e2e0bfacf56
+ b41c74a84b547b9e.027d9928d262d802.0de9d3e88273866d.7cacfd3aa9b5ed9f
+ 1da516cd5df4bc95.6cd5845a3b538d8f.86bd7055f3141b54.19d27bf95d11160b
+ 6c92ff7366f9bfaa.d56de86224b52641.f60e964d4d9595c5.87107358421905c5
+ a235624474d977f9
+ after
+ d5aa1e97948ec31c.bc98a9e0cdd84c6d.3145c49a5d259b64.d5d57e2e0bfacf56
+ b41c74a84b547b9e.027d9928d262d802.0de9d3e88273866d.7cacfd3aa9b5ed9f
+ 1da516cd5df4bc95.6cd5845a3b538d8f.86bd7055f3141b54.19d27bf95d11160b
+ 6c92ff7366f9bfaa.d56de86224b52641.f60e964d4d9595c5.87107358421905c5
+ d5d57e2e0bfacf56
+VPEXTRQ_128_0x0(mem)
+ before
+ 450cc2a7105e28d4.fd2d2c0601f0c38c.1911402ca7966043.ba28413c2c82326b
+ 4e60116f32b3d482.2cc297f3cb6403e5.138d08a4e302f7c2.2f576e8f2a652cf2
+ 98feca87f5e4362e.559f3ea55fe1ba61.a1adbcb6f103a7e9.afe718b0e6ccbf08
+ feb369da75fe0c05.d30f1c8759f324ad.9e3dd94ef0a72be6.97243a0df9432956
+ 4459d3110254a48b
+ after
+ 450cc2a7105e28d4.fd2d2c0601f0c38c.1911402ca7966043.afe718b0e6ccbf08
+ 4e60116f32b3d482.2cc297f3cb6403e5.138d08a4e302f7c2.2f576e8f2a652cf2
+ 98feca87f5e4362e.559f3ea55fe1ba61.a1adbcb6f103a7e9.afe718b0e6ccbf08
+ feb369da75fe0c05.d30f1c8759f324ad.9e3dd94ef0a72be6.97243a0df9432956
+ 4459d3110254a48b
+
+VPEXTRQ_128_0x0(reg)
+ before
+ 10d3dc289a8d6d51.5e486a56cf0c0f33.045d2d0756277f75.e509da59f9fa40e2
+ 58df52bd5f7ac055.938c4ae61f1afee3.43d66e90f2080564.54dc3bc12b06a20c
+ 78c7323eeda6d842.784a847780359341.ebc6d98ec723f327.c58378749fda0c8e
+ ccd77717df9df2c5.eb4d94f30e688b7b.5a796c6d7403856a.16ca0d5c737f3b94
+ 217d7767c303eb4b
+ after
+ 10d3dc289a8d6d51.5e486a56cf0c0f33.045d2d0756277f75.e509da59f9fa40e2
+ 58df52bd5f7ac055.938c4ae61f1afee3.43d66e90f2080564.54dc3bc12b06a20c
+ 78c7323eeda6d842.784a847780359341.ebc6d98ec723f327.c58378749fda0c8e
+ ccd77717df9df2c5.eb4d94f30e688b7b.5a796c6d7403856a.16ca0d5c737f3b94
+ e509da59f9fa40e2
+VPEXTRQ_128_0x0(mem)
+ before
+ c4683180aa71d8df.b05d1db2d2eb4a89.c663f647e6c0a2bb.eb3b22999334f6d8
+ d956b79344d5bd7b.80a4217c611d1b3b.e756275f2348932d.f957f87ec043831e
+ 3e15858cae3c574c.98f77de128bea287.28f3a128e20c1cfe.e21be88998bb68e7
+ cd6f185704b1627d.54a32f4ec45a1b18.6606e28c3e18f65a.00d1f024b628e1e0
+ b1c60bbdb71629b4
+ after
+ c4683180aa71d8df.b05d1db2d2eb4a89.c663f647e6c0a2bb.e21be88998bb68e7
+ d956b79344d5bd7b.80a4217c611d1b3b.e756275f2348932d.f957f87ec043831e
+ 3e15858cae3c574c.98f77de128bea287.28f3a128e20c1cfe.e21be88998bb68e7
+ cd6f185704b1627d.54a32f4ec45a1b18.6606e28c3e18f65a.00d1f024b628e1e0
+ b1c60bbdb71629b4
+
+VPEXTRQ_128_0x0(reg)
+ before
+ 4f4635be36127d10.6331ebe06141993b.10f4322dd17ec29b.7e5b66795479e06c
+ 389d6b95cfa819a0.dd277a14e1f7b9b2.283683eceab5d2bb.4abda7da3f3a9461
+ c617a7ad2062380f.151d41dda1df7e0d.f8b51cf6ab8c8825.a7f9229b1b68cf64
+ 56ffe772c2ce180a.e8dfbc29bc05a479.dcbcfbb7b18d2084.72dc54a8060d4da2
+ 8530b8ed1938ca47
+ after
+ 4f4635be36127d10.6331ebe06141993b.10f4322dd17ec29b.7e5b66795479e06c
+ 389d6b95cfa819a0.dd277a14e1f7b9b2.283683eceab5d2bb.4abda7da3f3a9461
+ c617a7ad2062380f.151d41dda1df7e0d.f8b51cf6ab8c8825.a7f9229b1b68cf64
+ 56ffe772c2ce180a.e8dfbc29bc05a479.dcbcfbb7b18d2084.72dc54a8060d4da2
+ 7e5b66795479e06c
+VPEXTRQ_128_0x0(mem)
+ before
+ bdc2cb5672f2017e.45a226505378f23d.323868e24f76e622.30991b9b9747d686
+ f65d07cf2d49af74.ed4d60b36fea0553.d0f6c0f6753d0133.5096780efa43e5d4
+ 0ccfea4465488f54.ab4a9207b1b28bf8.9ce340504b67b1d8.98000f7c750f8a1d
+ dbe3efa236fc5f4c.dbe6b7b8b55cc1d9.73cc64dbecffb13e.6323da51a536010b
+ 0f4bd7f92545854a
+ after
+ bdc2cb5672f2017e.45a226505378f23d.323868e24f76e622.98000f7c750f8a1d
+ f65d07cf2d49af74.ed4d60b36fea0553.d0f6c0f6753d0133.5096780efa43e5d4
+ 0ccfea4465488f54.ab4a9207b1b28bf8.9ce340504b67b1d8.98000f7c750f8a1d
+ dbe3efa236fc5f4c.dbe6b7b8b55cc1d9.73cc64dbecffb13e.6323da51a536010b
+ 0f4bd7f92545854a
+
+VPEXTRQ_128_0x1(reg)
+ before
+ f7c301e192c65387.3f6492d3bd70d985.da6ccb331872e3a2.317da9857511bf91
+ 76d954738748a76e.141f4fc515b0b92d.022acae275822dff.b2c1893901aa94fd
+ ead7cd1da054bdaa.36e0a3635bc9bd70.b06ab0336918da9b.d26682e4add5efad
+ ae0a664a7a78d0e8.81730899abc69f79.40797a9090bf2722.6d360f70949e8acd
+ 5fffadcad311238a
+ after
+ f7c301e192c65387.3f6492d3bd70d985.da6ccb331872e3a2.317da9857511bf91
+ 76d954738748a76e.141f4fc515b0b92d.022acae275822dff.b2c1893901aa94fd
+ ead7cd1da054bdaa.36e0a3635bc9bd70.b06ab0336918da9b.d26682e4add5efad
+ ae0a664a7a78d0e8.81730899abc69f79.40797a9090bf2722.6d360f70949e8acd
+ da6ccb331872e3a2
+VPEXTRQ_128_0x1(mem)
+ before
+ 848bd6df853b7310.1dbe1d65b13f1dd4.d1a3fc521fb31c75.0ea4236784034f42
+ b8a70899c628398b.953feedce036df19.023efb7cd69df090.7634a723e47090a4
+ d71ebee6b3e22f25.70d9d31aa3e85464.f00e7f03e98ed6f5.d4780230499324f7
+ bcbe75b16777120d.0cd8c98b97e1b660.77e106d177958bd1.84bb30fa52f748e5
+ e2482eed9828371a
+ after
+ 848bd6df853b7310.1dbe1d65b13f1dd4.d1a3fc521fb31c75.f00e7f03e98ed6f5
+ b8a70899c628398b.953feedce036df19.023efb7cd69df090.7634a723e47090a4
+ d71ebee6b3e22f25.70d9d31aa3e85464.f00e7f03e98ed6f5.d4780230499324f7
+ bcbe75b16777120d.0cd8c98b97e1b660.77e106d177958bd1.84bb30fa52f748e5
+ e2482eed9828371a
+
+VPEXTRQ_128_0x1(reg)
+ before
+ 4a6df775b9b32e43.4552a7e5fff39e6d.c387cd9c58ae42ba.73810bd399bbcb4f
+ 187487fe5123690c.4da5d27097608e72.f233dab781da341d.c0ba0af56d0e529c
+ a8aadaf5fb052421.b084713d4acc9f47.f628ed49aef1c736.395a7f240f9adbe4
+ 565bedc454e49a2d.49bb003834438d19.29b200bf7c8038b1.bc2ce64a9a6a2352
+ 24fbbc552b8ae513
+ after
+ 4a6df775b9b32e43.4552a7e5fff39e6d.c387cd9c58ae42ba.73810bd399bbcb4f
+ 187487fe5123690c.4da5d27097608e72.f233dab781da341d.c0ba0af56d0e529c
+ a8aadaf5fb052421.b084713d4acc9f47.f628ed49aef1c736.395a7f240f9adbe4
+ 565bedc454e49a2d.49bb003834438d19.29b200bf7c8038b1.bc2ce64a9a6a2352
+ c387cd9c58ae42ba
+VPEXTRQ_128_0x1(mem)
+ before
+ 4c947c30dd06df52.7dd2bbd9f74c08dc.f616fb4e72cf1414.e81d11838612c339
+ 12c4a2c7ccebcb3c.7b5d409f80c9aadb.9261df691f7eef63.90b41b036933a37b
+ 5155ab05154466fc.ab4678818ce8bcd6.f8672776585cdb33.7bc51aaac0701522
+ e41311d8d31d6bbf.68da5fedb6347978.06f54f62387494af.069a0ae3285455db
+ 8d80e81c3c6b9f52
+ after
+ 4c947c30dd06df52.7dd2bbd9f74c08dc.f616fb4e72cf1414.f8672776585cdb33
+ 12c4a2c7ccebcb3c.7b5d409f80c9aadb.9261df691f7eef63.90b41b036933a37b
+ 5155ab05154466fc.ab4678818ce8bcd6.f8672776585cdb33.7bc51aaac0701522
+ e41311d8d31d6bbf.68da5fedb6347978.06f54f62387494af.069a0ae3285455db
+ 8d80e81c3c6b9f52
+
+VPEXTRQ_128_0x1(reg)
+ before
+ 6cc3aec098422e32.a9cc522c238398b1.1065f24e9b3a1e6e.97d8d317dbd2d504
+ 00af5a3bda643f28.7a4ae9eb2181a7fd.fe332c10d785e764.86da2f835e825b5d
+ a390e8fa9b5d0edf.355b5302e72354d0.8d90099f05a10f05.b1c8e091dd91e2e7
+ b2b1526779bad604.b4c90a5d94765d56.1bc88568c11bd3fe.f26d612d730a26ce
+ 26972e423df9e23d
+ after
+ 6cc3aec098422e32.a9cc522c238398b1.1065f24e9b3a1e6e.97d8d317dbd2d504
+ 00af5a3bda643f28.7a4ae9eb2181a7fd.fe332c10d785e764.86da2f835e825b5d
+ a390e8fa9b5d0edf.355b5302e72354d0.8d90099f05a10f05.b1c8e091dd91e2e7
+ b2b1526779bad604.b4c90a5d94765d56.1bc88568c11bd3fe.f26d612d730a26ce
+ 1065f24e9b3a1e6e
+VPEXTRQ_128_0x1(mem)
+ before
+ 2a10c3bf566bd361.896096ef1006d543.d4618ce941857cba.03269dd5a87d6ffa
+ d8a69d8dda6bb566.84e7aefffbce4547.72ef54910d5d6e29.a0f74c5355561fa6
+ 0d233799e6064377.ff939901d69c62bd.683fde401109eece.50888e4f652f1ead
+ a6540dcf95473ac0.56b050633eff6a50.941ca6e46c95bad6.6d225f347396a9bc
+ 5414bb6d1b17fc7f
+ after
+ 2a10c3bf566bd361.896096ef1006d543.d4618ce941857cba.683fde401109eece
+ d8a69d8dda6bb566.84e7aefffbce4547.72ef54910d5d6e29.a0f74c5355561fa6
+ 0d233799e6064377.ff939901d69c62bd.683fde401109eece.50888e4f652f1ead
+ a6540dcf95473ac0.56b050633eff6a50.941ca6e46c95bad6.6d225f347396a9bc
+ 5414bb6d1b17fc7f
+
+VPSRLQ_0x05_128(reg)
+ before
+ 62a99f68fa3c52a1.7d059b1c043a566f.e58ad090ce8097ad.d0532968370d8c6c
+ f12c0690ac93e8cf.6f015d6a4feb53ad.076c16f423ad2580.f9b1e2b8907e21bd
+ 5eebec51cca8fab5.5916d0a79067eca9.1aa31dfbd8115274.eb004dc093f334f5
+ 06304d17f705c4fe.150e6fbde6bade8d.797ce1118a385836.820de66c5b79823f
+ 9ba329a8041bc7c8
+ after
+ 0000000000000000.0000000000000000.03cbe7088c51c2c1.04106f3362dbcc11
+ f12c0690ac93e8cf.6f015d6a4feb53ad.076c16f423ad2580.f9b1e2b8907e21bd
+ 5eebec51cca8fab5.5916d0a79067eca9.1aa31dfbd8115274.eb004dc093f334f5
+ 06304d17f705c4fe.150e6fbde6bade8d.797ce1118a385836.820de66c5b79823f
+ 9ba329a8041bc7c8
+VPSRLQ_0x05_128(mem)
+ before
+ 10909361abe5bfbb.4348264ec8388156.80b6b69a6aeee585.80415fa2d5af7471
+ be9f9f816ce42545.727f7162dbcd6e6a.76da21293b11bcbf.8b3f911a5301e2d2
+ 819bc9f66222b692.ef212cc0cd4ec7e6.d3462d56722e2164.f5c275e5a2bbdd05
+ 35518daaa9ae2ecd.177952d23949c776.73c6540d2d52cda3.1c1506705e68a2b5
+ 5b86402522946d8e
+ after
+ 10909361abe5bfbb.4348264ec8388156.80b6b69a6aeee585.80415fa2d5af7471
+ be9f9f816ce42545.727f7162dbcd6e6a.76da21293b11bcbf.8b3f911a5301e2d2
+ 819bc9f66222b692.ef212cc0cd4ec7e6.d3462d56722e2164.f5c275e5a2bbdd05
+ 35518daaa9ae2ecd.177952d23949c776.73c6540d2d52cda3.1c1506705e68a2b5
+ 5b86402522946d8e
+
+VPSRLQ_0x05_128(reg)
+ before
+ 0d5f20728bcc7a3e.b68d688b5e914823.44d5e006bc4aacc5.3225143a88887fa6
+ 90eda1c2349b046f.e01bd5849cd9c2bf.d37fd0c7f1dbaf7f.ec31e8c99edcf199
+ 3e7cbf80b98d48cd.8fc65081809256ce.20c42080758b0f52.7db44da78c5be1aa
+ 7558761ab72e8205.9f5c556e25c6c07c.87f0cb9fe4e306e7.c17bbdbe6d100802
+ 9452b6fc5d0725d0
+ after
+ 0000000000000000.0000000000000000.043f865cff271837.060bddedf3688040
+ 90eda1c2349b046f.e01bd5849cd9c2bf.d37fd0c7f1dbaf7f.ec31e8c99edcf199
+ 3e7cbf80b98d48cd.8fc65081809256ce.20c42080758b0f52.7db44da78c5be1aa
+ 7558761ab72e8205.9f5c556e25c6c07c.87f0cb9fe4e306e7.c17bbdbe6d100802
+ 9452b6fc5d0725d0
+VPSRLQ_0x05_128(mem)
+ before
+ d205b34b794df23e.8fcdc2fbca0bedc3.eca76037a883bef4.644fcd8fd871d1ed
+ 57603099ddec2c78.ea26a08f8db0c6b2.5175eec824d40a63.132c23bcefc0ac0e
+ fe2eaad1a3f38fab.e0b10a429ca7497f.ac907a0db6c661f4.f0d5c892c55cd3f6
+ a53c9cdfea6bd603.cfb8fe81947eb2d6.d8c480f279647ed4.5794b87df5d28152
+ a4b6efea1cadf3ce
+ after
+ d205b34b794df23e.8fcdc2fbca0bedc3.eca76037a883bef4.644fcd8fd871d1ed
+ 57603099ddec2c78.ea26a08f8db0c6b2.5175eec824d40a63.132c23bcefc0ac0e
+ fe2eaad1a3f38fab.e0b10a429ca7497f.ac907a0db6c661f4.f0d5c892c55cd3f6
+ a53c9cdfea6bd603.cfb8fe81947eb2d6.d8c480f279647ed4.5794b87df5d28152
+ a4b6efea1cadf3ce
+
+VPSRLQ_0x05_128(reg)
+ before
+ 33876943d57a6516.275782afcc63beab.118878b610c13c62.b1df7c648aba1e2e
+ 5f5323f6bdc312d4.6049d82d65e403d0.036d724eadfa24cf.13aceb4d04d5fd30
+ 8666176d6f1737b7.2bde1a45d2fc619e.02b3eab606b7a6cb.d9f6489b03c0d703
+ 030b431687ff1069.66e4c5e32eb69340.68a5db59b884fdff.e18a0f39a48867d6
+ 0635bc1303376ad3
+ after
+ 0000000000000000.0000000000000000.03452edacdc427ef.070c5079cd24433e
+ 5f5323f6bdc312d4.6049d82d65e403d0.036d724eadfa24cf.13aceb4d04d5fd30
+ 8666176d6f1737b7.2bde1a45d2fc619e.02b3eab606b7a6cb.d9f6489b03c0d703
+ 030b431687ff1069.66e4c5e32eb69340.68a5db59b884fdff.e18a0f39a48867d6
+ 0635bc1303376ad3
+VPSRLQ_0x05_128(mem)
+ before
+ 23c1cb153bdb9c26.328fa35ca209d897.eb2653f4961e56e3.929141a25eeb661a
+ 16fab92b6880b9fc.6e3f31ab5bc0cdec.986f4262254166b2.dcc118ff957a1dc6
+ b9ae0141a7317c81.1565eb6e4fb12915.488c0e1bf82a7eda.a3825ddbf8bd5eb0
+ eaa71f4313faa2e0.824ecc141a6728be.d649310a2ae55b86.41200aa2243e6483
+ 13e71dc0b48b6cec
+ after
+ 23c1cb153bdb9c26.328fa35ca209d897.eb2653f4961e56e3.929141a25eeb661a
+ 16fab92b6880b9fc.6e3f31ab5bc0cdec.986f4262254166b2.dcc118ff957a1dc6
+ b9ae0141a7317c81.1565eb6e4fb12915.488c0e1bf82a7eda.a3825ddbf8bd5eb0
+ eaa71f4313faa2e0.824ecc141a6728be.d649310a2ae55b86.41200aa2243e6483
+ 13e71dc0b48b6cec
+
+VPMULUDQ_128(reg)
+ before
+ 752392a14530b296.83b38f1dc9e7e746.1045d006566e0892.2072291ad77fb9e4
+ c31f63b272b8722e.629ccdbce40506df.1d98f3b1a252033d.00d371391c03541d
+ 59288e5dd7afe760.612f560a815fbcd6.0391328198a0566d.53378552157ee75f
+ 938b0e1011a14ed7.5d38a5f5bb01c557.207e87e3d4e43ccc.f66ce151ddfa2fd6
+ c33c02229086e8ae
+ after
+ 0000000000000000.0000000000000000.60c65bfae821def9.025a28db2d6861c3
+ c31f63b272b8722e.629ccdbce40506df.1d98f3b1a252033d.00d371391c03541d
+ 59288e5dd7afe760.612f560a815fbcd6.0391328198a0566d.53378552157ee75f
+ 938b0e1011a14ed7.5d38a5f5bb01c557.207e87e3d4e43ccc.f66ce151ddfa2fd6
+ c33c02229086e8ae
+VPMULUDQ_128(mem)
+ before
+ 987462b14b2bcd12.cd92df35bb1be23f.33833667aff8dd8f.cea9f041f2a8f306
+ 4fe07feb2af79b2e.638afd3a72a8e146.bddb864e784fbfaa.6b5f6809907ab5c8
+ c54cd5ba47f50e30.b1be648ad2d48596.d80d0f95331328d4.51ececa647e6bebe
+ d684de0cc132e242.137c1190762c0bdb.61e64f28fb4fd438.de9b7683b5764c93
+ 6cba040e76b899f4
+ after
+ 987462b14b2bcd12.cd92df35bb1be23f.33833667aff8dd8f.cea9f041f2a8f306
+ 4fe07feb2af79b2e.638afd3a72a8e146.bddb864e784fbfaa.6b5f6809907ab5c8
+ 0000000000000000.0000000000000000.52b37966efb1d1f6.88f3598638ad1ab0
+ d684de0cc132e242.137c1190762c0bdb.61e64f28fb4fd438.de9b7683b5764c93
+ 6cba040e76b899f4
+
+VPMULUDQ_128(reg)
+ before
+ 589391b22537e28c.5f5318cbb2b8d290.e50effbafa3baec3.3230c1f3ed0f7f02
+ ff731adb5e806209.3a87fee536969b47.82c22a73fb8eabf7.28b8e1e22460e460
+ bba699f6be1e5714.44ea0c456ad5f993.48e28f2814b03e26.1f492ce1bc4cc07c
+ e9780c6de19dfb5b.5949bed76983a79f.92bb2843e22da3fa.f3b11cddd2e2ce82
+ 80bb2fc0812bcc9f
+ after
+ 0000000000000000.0000000000000000.145454976aa358aa.1ac20fd496b69e80
+ ff731adb5e806209.3a87fee536969b47.82c22a73fb8eabf7.28b8e1e22460e460
+ bba699f6be1e5714.44ea0c456ad5f993.48e28f2814b03e26.1f492ce1bc4cc07c
+ e9780c6de19dfb5b.5949bed76983a79f.92bb2843e22da3fa.f3b11cddd2e2ce82
+ 80bb2fc0812bcc9f
+VPMULUDQ_128(mem)
+ before
+ a232e078e63574ff.e5356ead628a8b8a.557090874fab6398.bc98f3310091151f
+ 36e3acef1d0b82cd.0b28bb23dd70424d.142aff413a5ae6a9.21c7eb5f0a69d242
+ 169a0d1341bab436.b89fef39efdc5d4f.724586f1439befff.1f920d379e41130f
+ 1e2381cf6e4dc465.46e4075d3358183c.4b8ba183887a38c6.1147532755a31731
+ 5230bb99cd1d1855
+ after
+ a232e078e63574ff.e5356ead628a8b8a.557090874fab6398.bc98f3310091151f
+ 36e3acef1d0b82cd.0b28bb23dd70424d.142aff413a5ae6a9.21c7eb5f0a69d242
+ 0000000000000000.0000000000000000.12291e9a070f4f58.0005e6cc0871dffe
+ 1e2381cf6e4dc465.46e4075d3358183c.4b8ba183887a38c6.1147532755a31731
+ 5230bb99cd1d1855
+
+VPMULUDQ_128(reg)
+ before
+ 409a40fba23a5327.2c49830fc1d06f87.1244fefa4672afc1.7bcacde325047f29
+ 35d1deb86f870452.1bda8fbf555071c7.780bd07bc3b65d8a.decc84fe35447d55
+ 8f21913cd08f6682.c7a022cb47d88553.d485794e47af5f43.505e44bed446f175
+ a8d556f362deb765.0c69b61fb2746854.82fdf6de6de9f197.ad4b88111f1795b6
+ d161cce232c22643
+ after
+ 0000000000000000.0000000000000000.36cda66f1cc6b11e.2c2b7ac27b884cd9
+ 35d1deb86f870452.1bda8fbf555071c7.780bd07bc3b65d8a.decc84fe35447d55
+ 8f21913cd08f6682.c7a022cb47d88553.d485794e47af5f43.505e44bed446f175
+ a8d556f362deb765.0c69b61fb2746854.82fdf6de6de9f197.ad4b88111f1795b6
+ d161cce232c22643
+VPMULUDQ_128(mem)
+ before
+ 976b8d1d2853604a.de3a2849c10130a5.c6ffc9a7b331d6f9.dec14198d2f04f32
+ dd3446ad1dd7fef4.8b9d03ab878310ee.d12ed64f651a8b6c.441b58e61151b4c1
+ 7e8972802e59bd70.0c48e38353f091ed.08c45a04e43b42d9.0f583635c7975df0
+ 5636908276e559e8.be88c43ebfd5f04e.498ccfb14da1b86d.9dc4d8f18f4f856b
+ 49ab388705036adc
+ after
+ 976b8d1d2853604a.de3a2849c10130a5.c6ffc9a7b331d6f9.dec14198d2f04f32
+ dd3446ad1dd7fef4.8b9d03ab878310ee.d12ed64f651a8b6c.441b58e61151b4c1
+ 0000000000000000.0000000000000000.46c53e77bb09e40c.0e45483b5facdcb2
+ 5636908276e559e8.be88c43ebfd5f04e.498ccfb14da1b86d.9dc4d8f18f4f856b
+ 49ab388705036adc
+
+VPSLLQ_0x05_128(reg)
+ before
+ 6f595462c64246f2.4007199d12888e88.fba8a34967bd69bc.6f51b341bc57a854
+ 6b1927ed6e955657.1ac88bbe1d4d177d.20f67b0ee83438e4.55e181a24c69d0b9
+ 9839ad96988ad5b8.bf4460d1b440b1f3.8abc48fbddc79871.d906b5bf19e4eac9
+ 5403e3c8e0ac00c0.0a4816c3f26e1815.9348067be301c610.d68dcc8440d3b3b0
+ 274140dddd42e699
+ after
+ 0000000000000000.0000000000000000.6900cf7c6038c200.d1b990881a767600
+ 6b1927ed6e955657.1ac88bbe1d4d177d.20f67b0ee83438e4.55e181a24c69d0b9
+ 9839ad96988ad5b8.bf4460d1b440b1f3.8abc48fbddc79871.d906b5bf19e4eac9
+ 5403e3c8e0ac00c0.0a4816c3f26e1815.9348067be301c610.d68dcc8440d3b3b0
+ 274140dddd42e699
+VPSLLQ_0x05_128(mem)
+ before
+ aaf08fb60b3e41b1.fac4c3efe388131c.d9a1297ef4e20710.98e4b2fa956efd6d
+ 396434fbe6d27e23.e5c84b773da94a78.061913f0d5a83b10.f5dd47e48f9b7b33
+ b26bab988b0b591c.735b76cc889be17f.6f7d5204b1cd7040.067fc1a56e137a0f
+ efcf717a15f490c7.ffc8415a63ea13dd.ee9861a6a55c62cc.27151ca9ce6236ac
+ b4ed545d4a15edb7
+ after
+ aaf08fb60b3e41b1.fac4c3efe388131c.d9a1297ef4e20710.98e4b2fa956efd6d
+ 396434fbe6d27e23.e5c84b773da94a78.061913f0d5a83b10.f5dd47e48f9b7b33
+ b26bab988b0b591c.735b76cc889be17f.6f7d5204b1cd7040.067fc1a56e137a0f
+ efcf717a15f490c7.ffc8415a63ea13dd.ee9861a6a55c62cc.27151ca9ce6236ac
+ b4ed545d4a15edb7
+
+VPSLLQ_0x05_128(reg)
+ before
+ 0951662b7fb7d9dc.ce5d018ba199dd51.e45da68e67231d40.6138bcc2cd62cce2
+ 828e4d8007d437c6.29e1d6b94a06fde6.8064a3d233d23a52.a227df4444ea6bac
+ 7bf005c981f94322.dd276fee2d48abb1.2d2a33946081a7bf.8e3347182600fb56
+ 50c38a7187b1389b.c7fa4518656aa5df.49fb523e8dbea034.02266e2a90b0370d
+ d8cdd2669e07dcfd
+ after
+ 0000000000000000.0000000000000000.3f6a47d1b7d40680.44cdc5521606e1a0
+ 828e4d8007d437c6.29e1d6b94a06fde6.8064a3d233d23a52.a227df4444ea6bac
+ 7bf005c981f94322.dd276fee2d48abb1.2d2a33946081a7bf.8e3347182600fb56
+ 50c38a7187b1389b.c7fa4518656aa5df.49fb523e8dbea034.02266e2a90b0370d
+ d8cdd2669e07dcfd
+VPSLLQ_0x05_128(mem)
+ before
+ edf4eeb96b10a651.5d53d9e3b58953de.c128d6220f79a59c.2e23fc3e5314615d
+ 1d663f0d13d85136.feecec8da80cd097.a87b9cf8467f6813.39ed2eff501026e5
+ 45f14050b36a98d7.8fd9c1dafbc6ea71.58c01586268ba970.c7a7e3ed203d2a79
+ 3f5f6c6d66d23861.6c6753364b43df19.aec3bdb8cca625e0.329b17745e27aac4
+ d716c600a65be173
+ after
+ edf4eeb96b10a651.5d53d9e3b58953de.c128d6220f79a59c.2e23fc3e5314615d
+ 1d663f0d13d85136.feecec8da80cd097.a87b9cf8467f6813.39ed2eff501026e5
+ 45f14050b36a98d7.8fd9c1dafbc6ea71.58c01586268ba970.c7a7e3ed203d2a79
+ 3f5f6c6d66d23861.6c6753364b43df19.aec3bdb8cca625e0.329b17745e27aac4
+ d716c600a65be173
+
+VPSLLQ_0x05_128(reg)
+ before
+ 1365edfd95640d32.e87d414f491ced00.f0e29f0d3310e93a.84500e7a54de988f
+ 40d186d7c7ce68ac.1c173be4775572df.79969fcc50b84481.b73286b9d93ebea9
+ bba98ffbd7262e8e.b7f9d4170d88852b.62cf51dd3dc82e9a.2337a05f77d35259
+ e03804d361f79d84.95ef8ad426c2df0f.07d9b0ad97cbe130.a429d85a4ba811cb
+ 16d5aa9470c9b72c
+ after
+ 0000000000000000.0000000000000000.fb3615b2f97c2600.853b0b4975023960
+ 40d186d7c7ce68ac.1c173be4775572df.79969fcc50b84481.b73286b9d93ebea9
+ bba98ffbd7262e8e.b7f9d4170d88852b.62cf51dd3dc82e9a.2337a05f77d35259
+ e03804d361f79d84.95ef8ad426c2df0f.07d9b0ad97cbe130.a429d85a4ba811cb
+ 16d5aa9470c9b72c
+VPSLLQ_0x05_128(mem)
+ before
+ 550793fb0343ffa8.0bc9dfcd02ceef39.92c5d807de0e3fb8.c3ffb9a9f94d9aef
+ 3d8b0e7a2021a76b.98a91e5355356159.8a463a9d53785f52.f48f663b00da9485
+ aa2d97fde16f69a0.e324bbd3f7ba2f91.593f2c809e0dfd08.f4d3b5d147ff0d9c
+ 78b8aa7065390173.4986b4b883e9948d.db7c2b9dddd8d207.2118a1d66a483fe0
+ d6aa26b6063f66fe
+ after
+ 550793fb0343ffa8.0bc9dfcd02ceef39.92c5d807de0e3fb8.c3ffb9a9f94d9aef
+ 3d8b0e7a2021a76b.98a91e5355356159.8a463a9d53785f52.f48f663b00da9485
+ aa2d97fde16f69a0.e324bbd3f7ba2f91.593f2c809e0dfd08.f4d3b5d147ff0d9c
+ 78b8aa7065390173.4986b4b883e9948d.db7c2b9dddd8d207.2118a1d66a483fe0
+ d6aa26b6063f66fe
+
+VPMAXUD_128(reg)
+ before
+ 6ed440ddb772c0a2.83f9c3bfc58c2d11.241b056e964ccdf9.ecc9b2e12ce59d7a
+ 46e4ecb7186c8777.a7bd5fd62074a7a6.d12fa861cb721680.68f23d37a641188e
+ bb2425b0c5baf82a.bfcef9a18ffb2c5d.ab0d9bfdbfe4aace.2bc3488a67f7006f
+ 27e1e7345be74e67.a9f90d0d302f7763.1002d9ae0d30c690.100750c88c131148
+ f58bcfdc30a20646
+ after
+ 0000000000000000.0000000000000000.d12fa861cb721680.68f23d37a641188e
+ 46e4ecb7186c8777.a7bd5fd62074a7a6.d12fa861cb721680.68f23d37a641188e
+ bb2425b0c5baf82a.bfcef9a18ffb2c5d.ab0d9bfdbfe4aace.2bc3488a67f7006f
+ 27e1e7345be74e67.a9f90d0d302f7763.1002d9ae0d30c690.100750c88c131148
+ f58bcfdc30a20646
+VPMAXUD_128(mem)
+ before
+ b51c43b270af9c94.e8682eb0757fc7d9.400917041f1c45e4.5b5b5ee052e1a672
+ 2c84273667468f5f.5802f68eb00f9d2c.60cc947477cc520b.e86226002983861f
+ 358ff85432749bd2.d4fe3c3ca7220c0d.e40cfe47554d5a05.13632e782ea3a144
+ ae0b30f9ec447b1a.b9a7fb24f7445228.aa97d36bd4ab18fd.38ac71b6fecc358d
+ b288eb25358b7ba5
+ after
+ b51c43b270af9c94.e8682eb0757fc7d9.400917041f1c45e4.5b5b5ee052e1a672
+ 2c84273667468f5f.5802f68eb00f9d2c.60cc947477cc520b.e86226002983861f
+ 0000000000000000.0000000000000000.60cc947477cc520b.e862260052e1a672
+ ae0b30f9ec447b1a.b9a7fb24f7445228.aa97d36bd4ab18fd.38ac71b6fecc358d
+ b288eb25358b7ba5
+
+VPMAXUD_128(reg)
+ before
+ df4298306e6bb239.72c34d0fb2c2ec63.61482fb43b02a929.8d378ecb10f14920
+ 1a27744545f814f4.5c82ca839ffbaad8.292fd45710e74ebb.68b9ac53262ba999
+ bf837ccf57bfde83.4a152342d0fa70a6.6da6e779117f7c8a.19e8a8ef3165f496
+ 29a2ab3a3f4a4c92.1648d53760ccfbf9.89fa6386db577144.7a92fd8b4eace540
+ 69822913990b39c6
+ after
+ 0000000000000000.0000000000000000.6da6e779117f7c8a.68b9ac533165f496
+ 1a27744545f814f4.5c82ca839ffbaad8.292fd45710e74ebb.68b9ac53262ba999
+ bf837ccf57bfde83.4a152342d0fa70a6.6da6e779117f7c8a.19e8a8ef3165f496
+ 29a2ab3a3f4a4c92.1648d53760ccfbf9.89fa6386db577144.7a92fd8b4eace540
+ 69822913990b39c6
+VPMAXUD_128(mem)
+ before
+ c083a8732c8eac51.b6d0fdf29a2899cc.9ee75b4d6c7b07fc.da7644ea09fa6792
+ 5d62f4982642f910.c0596e6404e202dd.bcbe30720f1550dc.ba68861137f59b23
+ 1aeb8b6ca032dd2d.a588fbfa1706c373.4e99d39165a691c4.861b256702d248a1
+ d5eae8ddb96b14d5.bfaa9e21721f1838.2e43bd968b3987e1.9ada1e59061fabb8
+ 52f26c51de680016
+ after
+ c083a8732c8eac51.b6d0fdf29a2899cc.9ee75b4d6c7b07fc.da7644ea09fa6792
+ 5d62f4982642f910.c0596e6404e202dd.bcbe30720f1550dc.ba68861137f59b23
+ 0000000000000000.0000000000000000.bcbe30726c7b07fc.da7644ea37f59b23
+ d5eae8ddb96b14d5.bfaa9e21721f1838.2e43bd968b3987e1.9ada1e59061fabb8
+ 52f26c51de680016
+
+VPMAXUD_128(reg)
+ before
+ 0aaf0bbd26388364.682b87d58af85a33.6c0b5546aeba3cd8.39896b6d9ddaee5e
+ 1e5df7087b1b6f51.b079e44232e56a74.06f71cd469626c00.4c375a03b6958168
+ e9482d9d799d0187.89a27c0fca3e01c3.ebbaed363fa3e45c.41190542f277fd2b
+ c9bba7eaba4b75b2.d070ca287010db4d.75a0c6dacb0adf97.f5fbe8176e8b1ed2
+ 44a9806f45dea08a
+ after
+ 0000000000000000.0000000000000000.ebbaed3669626c00.4c375a03f277fd2b
+ 1e5df7087b1b6f51.b079e44232e56a74.06f71cd469626c00.4c375a03b6958168
+ e9482d9d799d0187.89a27c0fca3e01c3.ebbaed363fa3e45c.41190542f277fd2b
+ c9bba7eaba4b75b2.d070ca287010db4d.75a0c6dacb0adf97.f5fbe8176e8b1ed2
+ 44a9806f45dea08a
+VPMAXUD_128(mem)
+ before
+ 0bee4734947b3e7e.1904635addb0077f.5fb04a794066b43e.02f4a22baa229a5e
+ 2498bb54766eb5db.356d5d597c59f29a.132e78ee554d47c1.ec047d957777515c
+ 6c7157ba08c4c1cd.79438f5333d073af.c8b6d074cbd05103.901a5384ce96403e
+ bf46985265871d7f.41d2f7b49fa4c669.5a13cff5bffb8d2f.4a8320644c0aa2b0
+ 778be1a18d5fb45d
+ after
+ 0bee4734947b3e7e.1904635addb0077f.5fb04a794066b43e.02f4a22baa229a5e
+ 2498bb54766eb5db.356d5d597c59f29a.132e78ee554d47c1.ec047d957777515c
+ 0000000000000000.0000000000000000.5fb04a79554d47c1.ec047d95aa229a5e
+ bf46985265871d7f.41d2f7b49fa4c669.5a13cff5bffb8d2f.4a8320644c0aa2b0
+ 778be1a18d5fb45d
+
+VPMINUD_128(reg)
+ before
+ 717d91a82c22b2f2.f9e3f808aac6871e.e8668fe95b5e2674.a613f05e4ddab972
+ 95a72ce3c5ded81b.f613f5c8f28ab8d5.cc4b555c038cd07d.8680af9c907a8ff8
+ 3f53afc0f51f6183.92a40a7e5ae16fd1.48cc457b34b90030.d7278999a4e7cbec
+ cbcf14aa57728ad6.a960b316fdd6663e.b73659b08a72f138.75d4f843a62b2b7b
+ 3c537a85b15469d0
+ after
+ 0000000000000000.0000000000000000.48cc457b038cd07d.8680af9c907a8ff8
+ 95a72ce3c5ded81b.f613f5c8f28ab8d5.cc4b555c038cd07d.8680af9c907a8ff8
+ 3f53afc0f51f6183.92a40a7e5ae16fd1.48cc457b34b90030.d7278999a4e7cbec
+ cbcf14aa57728ad6.a960b316fdd6663e.b73659b08a72f138.75d4f843a62b2b7b
+ 3c537a85b15469d0
+VPMINUD_128(mem)
+ before
+ 08708a4be26d4218.9565590c88628ec1.17156c7df7765b47.77d68f69a042e142
+ b4f6a4815483727f.f9627954237cabf0.b88db29d65cc0719.e2f6e21113b50afa
+ 1eb2451324a1b430.531170edc54a1b0f.6895006463e429df.56e24e147e58a80b
+ 2171e7ed6dd3c558.ffc03b43095b1bc9.03f9d2bc0ccb7bc6.2de8cfde7db6f921
+ c55362dbad5b37ea
+ after
+ 08708a4be26d4218.9565590c88628ec1.17156c7df7765b47.77d68f69a042e142
+ b4f6a4815483727f.f9627954237cabf0.b88db29d65cc0719.e2f6e21113b50afa
+ 0000000000000000.0000000000000000.17156c7d65cc0719.77d68f6913b50afa
+ 2171e7ed6dd3c558.ffc03b43095b1bc9.03f9d2bc0ccb7bc6.2de8cfde7db6f921
+ c55362dbad5b37ea
+
+VPMINUD_128(reg)
+ before
+ 786e0277a9d39f10.99fd08fb4c266122.59b9d4c28c38e6ca.6584a4937c8cbafa
+ a486ab1e0eab6c3f.6223232adca544bb.bd4a39d6e96fb9bf.6904f3d4d033a2a6
+ a3e7593d786fdc24.58aeb4643a5c294f.87bd66ecbd8bd054.ed43396b23cdeef7
+ d2dd083e81a9296b.566c38978158cd09.135f556ea3186734.cc0ef44492655b18
+ e2319f4b3907a536
+ after
+ 0000000000000000.0000000000000000.87bd66ecbd8bd054.6904f3d423cdeef7
+ a486ab1e0eab6c3f.6223232adca544bb.bd4a39d6e96fb9bf.6904f3d4d033a2a6
+ a3e7593d786fdc24.58aeb4643a5c294f.87bd66ecbd8bd054.ed43396b23cdeef7
+ d2dd083e81a9296b.566c38978158cd09.135f556ea3186734.cc0ef44492655b18
+ e2319f4b3907a536
+VPMINUD_128(mem)
+ before
+ 0a78b76c32c0887d.8eb4b58fc8e790bf.3a272aadcda4eb15.bd7c03ca37a3b90c
+ 22afb6939c9bbf18.31b85b9ae7b54ccd.dfad06943b4d41a1.e15f6d6a16b70388
+ 05a11aad90a40733.1834f6cd7a9d9a40.20c84837e75d89d7.da568ebcdce18153
+ 8e1c5ea42ce81bfc.9f7582931d2db6c5.db456c82ece280e3.06ab622b24ac6f1a
+ c0ace6238aa40888
+ after
+ 0a78b76c32c0887d.8eb4b58fc8e790bf.3a272aadcda4eb15.bd7c03ca37a3b90c
+ 22afb6939c9bbf18.31b85b9ae7b54ccd.dfad06943b4d41a1.e15f6d6a16b70388
+ 0000000000000000.0000000000000000.3a272aad3b4d41a1.bd7c03ca16b70388
+ 8e1c5ea42ce81bfc.9f7582931d2db6c5.db456c82ece280e3.06ab622b24ac6f1a
+ c0ace6238aa40888
+
+VPMINUD_128(reg)
+ before
+ 63a3150fab55894a.9beafe668c72b99d.23c7fc586ef1dc08.eaefef6166e8e1f2
+ 4ddcea5e224c2e0c.06d877ddcb4f9b42.fe765f88067347b4.2b944cc072796a30
+ d9a564798c153279.adb243f7068a7e18.8dcea78f83423476.78ffff8b2ba4d5c8
+ 62497ccd853ad23d.6a43e09f582f1d4b.2c1bd0d981e7dff9.affb84aeae72dee7
+ aa55581616f143b9
+ after
+ 0000000000000000.0000000000000000.8dcea78f067347b4.2b944cc02ba4d5c8
+ 4ddcea5e224c2e0c.06d877ddcb4f9b42.fe765f88067347b4.2b944cc072796a30
+ d9a564798c153279.adb243f7068a7e18.8dcea78f83423476.78ffff8b2ba4d5c8
+ 62497ccd853ad23d.6a43e09f582f1d4b.2c1bd0d981e7dff9.affb84aeae72dee7
+ aa55581616f143b9
+VPMINUD_128(mem)
+ before
+ 47d9f5ad802cbe69.46132fc6a7494a06.1b59c9c1dd4a3606.37a8d6d29bf083ea
+ 6053d961072f0c23.df507ad191cdd67e.9abf7b49b2e88376.0ac3b6e76de85ef5
+ d28f7f1dc807e815.8b4d5858dc53b151.c4407023f314c1c6.01b66b82945baac5
+ 7a5864ccdebf1068.a454c5c92666182c.76a9263bbbdbab23.78cef111acd6a307
+ cb5744fe50e48766
+ after
+ 47d9f5ad802cbe69.46132fc6a7494a06.1b59c9c1dd4a3606.37a8d6d29bf083ea
+ 6053d961072f0c23.df507ad191cdd67e.9abf7b49b2e88376.0ac3b6e76de85ef5
+ 0000000000000000.0000000000000000.1b59c9c1b2e88376.0ac3b6e76de85ef5
+ 7a5864ccdebf1068.a454c5c92666182c.76a9263bbbdbab23.78cef111acd6a307
+ cb5744fe50e48766
+
+VPMULLD_128(reg)
+ before
+ 569d61b71c12908f.327c025c66643e4b.88b1be8f0b9247bb.8ac6187e2647feb9
+ 75eb43a7adeafa2e.d7c5d7b87b012fe8.91b23d15266479a9.dd63c2d6516776b3
+ 838fe63a9efb03ee.46005ecc3aa29e6c.1ca240c91467eba3.4c4ba1305744cf3e
+ ded346dc8ccee57c.59f91384be534802.86ccc2167027d954.b14c2f7955ecc486
+ e930ea9c666a12b6
+ after
+ 0000000000000000.0000000000000000.e781357dd4a6999b.dcef1e20bc957c5a
+ 75eb43a7adeafa2e.d7c5d7b87b012fe8.91b23d15266479a9.dd63c2d6516776b3
+ 838fe63a9efb03ee.46005ecc3aa29e6c.1ca240c91467eba3.4c4ba1305744cf3e
+ ded346dc8ccee57c.59f91384be534802.86ccc2167027d954.b14c2f7955ecc486
+ e930ea9c666a12b6
+VPMULLD_128(mem)
+ before
+ d0c44d85a7cb75fa.e1045ff912f1dd83.ed7c73cd2321e9d7.297dc068d6317f69
+ 42d4d41f331aa87f.e86e2efdcdef27b0.de54f99186183d16.6201342ce310188e
+ 1b2cfc5827636871.4f5dae555855feae.084f20bd0342ffec.8da41ccc3350e16e
+ 3798401b9eb271fc.711cdb6b50ad9f2b.4737673eb4adec85.07b273b5617e16b6
+ 2a7635540925f212
+ after
+ d0c44d85a7cb75fa.e1045ff912f1dd83.ed7c73cd2321e9d7.297dc068d6317f69
+ 42d4d41f331aa87f.e86e2efdcdef27b0.de54f99186183d16.6201342ce310188e
+ 0000000000000000.0000000000000000.5563fc1d8fca537a.3d1a31e084f6843e
+ 3798401b9eb271fc.711cdb6b50ad9f2b.4737673eb4adec85.07b273b5617e16b6
+ 2a7635540925f212
+
+VPMULLD_128(reg)
+ before
+ 533e5e13c8d1b22d.72e41c55b5147f4b.acf9b1ad508646d0.77d947feb864c00c
+ de54eb60390f92b3.a8db0cf087954d8a.5a3e2c85f4692f4c.74013deb297436ae
+ 2705d7a6f96ace51.b54a8cd9303f98e6.d9384961dae49549.1a7bc6f023e80c96
+ 8a9d1e50a36fa1b3.75fd19fdcd201c8b.843303ac9b82b573.45135df9c3ccfcf1
+ d1947ef2242dc2eb
+ after
+ 0000000000000000.0000000000000000.6658cb65c235b8ac.54f6ce50145831f4
+ de54eb60390f92b3.a8db0cf087954d8a.5a3e2c85f4692f4c.74013deb297436ae
+ 2705d7a6f96ace51.b54a8cd9303f98e6.d9384961dae49549.1a7bc6f023e80c96
+ 8a9d1e50a36fa1b3.75fd19fdcd201c8b.843303ac9b82b573.45135df9c3ccfcf1
+ d1947ef2242dc2eb
+VPMULLD_128(mem)
+ before
+ 9acba6c763161caf.6368bcccd4a84885.c4c02e467a4395a5.b67b56d2d5d0cb77
+ 7c8550649b93c469.0eb1ad8527a3ff72.7e5f47a252b5be5f.cd5c3e3f24591201
+ 538cf7b5e9b17647.e7c6eee839ec0226.7fa6e0fb718154e5.2321b85f22a9c7bc
+ faad1aa7687bf073.4af17a5fa50e8c4e.a360753ff4b31364.1618bf9e6e4d2655
+ 008b4f68a2d06b77
+ after
+ 9acba6c763161caf.6368bcccd4a84885.c4c02e467a4395a5.b67b56d2d5d0cb77
+ 7c8550649b93c469.0eb1ad8527a3ff72.7e5f47a252b5be5f.cd5c3e3f24591201
+ 0000000000000000.0000000000000000.6e6cb24c2fcdfe3b.24d939aefc7e2977
+ faad1aa7687bf073.4af17a5fa50e8c4e.a360753ff4b31364.1618bf9e6e4d2655
+ 008b4f68a2d06b77
+
+VPMULLD_128(reg)
+ before
+ 3ec764295abed1d0.4fb3322434fdec19.937f4d570895da96.c55a8359f758b608
+ 2d18fb4e33a49509.2d6cbc1a6a442766.1ebc633cfd0d28a9.c3618535947bfafc
+ 27ca0e41c80df3d0.6fa23573265b5d86.47f4b97b2003b134.783ff7bfea289b6d
+ 89289b70b68526d1.f323181d834e49a4.69734a7f0e02b2e3.bfc056e4126c5587
+ 76b21c8e2b52e375
+ after
+ 0000000000000000.0000000000000000.216a09d419c41b54.7d53858bd920714c
+ 2d18fb4e33a49509.2d6cbc1a6a442766.1ebc633cfd0d28a9.c3618535947bfafc
+ 27ca0e41c80df3d0.6fa23573265b5d86.47f4b97b2003b134.783ff7bfea289b6d
+ 89289b70b68526d1.f323181d834e49a4.69734a7f0e02b2e3.bfc056e4126c5587
+ 76b21c8e2b52e375
+VPMULLD_128(mem)
+ before
+ 78e0c7aa4ee70264.af809d4698996bb8.94b9e1039d2aa8ed.e28412b363976761
+ a015d2259a356d7f.f61c112f0bd4fe30.2d310d1191fa368d.0d750d85ba4d0b5b
+ cc1eb9e9284ae2f3.b849f196aac21be5.9c5616337bcaafaf.46903760afb0dc7c
+ d6c7f9e416321beb.52533be912f0fd85.bbf67a5576a7ce80.e8228db0df4c1471
+ 51770ae1e5aeefe6
+ after
+ 78e0c7aa4ee70264.af809d4698996bb8.94b9e1039d2aa8ed.e28412b363976761
+ a015d2259a356d7f.f61c112f0bd4fe30.2d310d1191fa368d.0d750d85ba4d0b5b
+ 0000000000000000.0000000000000000.e9581833c4930889.065fcdff7a6fea7b
+ d6c7f9e416321beb.52533be912f0fd85.bbf67a5576a7ce80.e8228db0df4c1471
+ 51770ae1e5aeefe6
+
+VPMAXUW_128(reg)
+ before
+ dbdaaa5f5e61ab86.9cdc0c0180f8d594.2086ea94dee9e1b9.68dcb4639e9c502b
+ e4996996e5f282fd.f829702b81a8cb1a.7e2efa01aa390330.7dd3404a10b6f1dd
+ c7fe44f317ecb1f9.c87aa050364ebba8.c896689d136d9f94.d8a89bf4e7ff6cc1
+ df5736e08fdb7324.e69a195bbaf75f6b.5a0c2ed4b510f091.5327404e40867e04
+ cc1cab453654e3d2
+ after
+ 0000000000000000.0000000000000000.c896fa01aa399f94.d8a89bf4e7fff1dd
+ e4996996e5f282fd.f829702b81a8cb1a.7e2efa01aa390330.7dd3404a10b6f1dd
+ c7fe44f317ecb1f9.c87aa050364ebba8.c896689d136d9f94.d8a89bf4e7ff6cc1
+ df5736e08fdb7324.e69a195bbaf75f6b.5a0c2ed4b510f091.5327404e40867e04
+ cc1cab453654e3d2
+VPMAXUW_128(mem)
+ before
+ 1d5358c4e6775756.8aee3bcbea4c062a.2f56553929ae748f.90da4a132baf33d5
+ 2397c3b66bfa95bd.22104f1ec3caa4b8.807ad2d4a080b53f.c64db7c511d4a309
+ bbb66909e2ea5a33.04096e47b7e1897a.b3d20b193a77dfa7.58b17155040e7edc
+ bf7ac4a8665162e3.8d2495b1611ef31b.a52a7cf514a2aef5.a25175319fe6fef8
+ 007bbec47fea6009
+ after
+ 1d5358c4e6775756.8aee3bcbea4c062a.2f56553929ae748f.90da4a132baf33d5
+ 2397c3b66bfa95bd.22104f1ec3caa4b8.807ad2d4a080b53f.c64db7c511d4a309
+ 0000000000000000.0000000000000000.807ad2d4a080b53f.c64db7c52bafa309
+ bf7ac4a8665162e3.8d2495b1611ef31b.a52a7cf514a2aef5.a25175319fe6fef8
+ 007bbec47fea6009
+
+VPMAXUW_128(reg)
+ before
+ ce79487a40a5dfbc.0cb0537f133e68f9.17afbfc85e0c1c48.334ea1524a0ade52
+ 68990fbf7ca3b8bd.7e248f7a06ba2aa3.fff4e8f8493741ac.3709f71ef6bd2aed
+ 29250fffd27127b7.f1a2f5865bd3620a.a2400cadbe2c9df4.8e29f94337c64ff0
+ 6f6a45a6db9a6857.42f5028d2d94cc5d.5adf28535a766ecc.147823af26320987
+ a5c3f14de20c13e0
+ after
+ 0000000000000000.0000000000000000.fff4e8f8be2c9df4.8e29f943f6bd4ff0
+ 68990fbf7ca3b8bd.7e248f7a06ba2aa3.fff4e8f8493741ac.3709f71ef6bd2aed
+ 29250fffd27127b7.f1a2f5865bd3620a.a2400cadbe2c9df4.8e29f94337c64ff0
+ 6f6a45a6db9a6857.42f5028d2d94cc5d.5adf28535a766ecc.147823af26320987
+ a5c3f14de20c13e0
+VPMAXUW_128(mem)
+ before
+ 1dd6e00984602a24.95b3ac2036abb649.4beb317c980a26c6.841d3656b9a1eedf
+ 587d6bcf2a3b0a82.f74e40da7c2f4f38.e94efe40b9402a71.7c463423763a5ada
+ 32830e8bf0a76f24.f086fd3e4bb26cd1.f8ebe5c4ab42948c.9fa51d242dcced68
+ 87b64529f1b31436.dea6dfba3fc14cbf.548e63f38b1d2240.4788eec77be3e437
+ d139a176fb0c7bf0
+ after
+ 1dd6e00984602a24.95b3ac2036abb649.4beb317c980a26c6.841d3656b9a1eedf
+ 587d6bcf2a3b0a82.f74e40da7c2f4f38.e94efe40b9402a71.7c463423763a5ada
+ 0000000000000000.0000000000000000.e94efe40b9402a71.841d3656b9a1eedf
+ 87b64529f1b31436.dea6dfba3fc14cbf.548e63f38b1d2240.4788eec77be3e437
+ d139a176fb0c7bf0
+
+VPMAXUW_128(reg)
+ before
+ 9905349f4ad2ee41.33e08c964a68b6e6.1bfbe3b9f3e729af.d903f3bb75db8ebc
+ fb38a2ad03c178d6.12ce60bc16d4115d.05d104a604b0404d.63161107838b952a
+ 531ee80cc366565a.004c3c897103e1ca.f6743eef0da8cd44.ce9239c3d436f3b6
+ fd030028254cc47a.d9269ce778ffe157.4c308effaa5c0b40.f544e7db81ea638d
+ b6f9983ba9b3a2db
+ after
+ 0000000000000000.0000000000000000.f6743eef0da8cd44.ce9239c3d436f3b6
+ fb38a2ad03c178d6.12ce60bc16d4115d.05d104a604b0404d.63161107838b952a
+ 531ee80cc366565a.004c3c897103e1ca.f6743eef0da8cd44.ce9239c3d436f3b6
+ fd030028254cc47a.d9269ce778ffe157.4c308effaa5c0b40.f544e7db81ea638d
+ b6f9983ba9b3a2db
+VPMAXUW_128(mem)
+ before
+ ec7bc7cf659b6ccc.5532e86dc600fde2.7927fcc446d6ce30.6150ee42785838ef
+ 7397f084d3b07d8a.b7f89b47410d3f3d.bc1dd80bf8946482.93225c2512268dfa
+ 27188f440ffe9044.7fa1152233ffc438.7dd2ada8aa435e79.3cf0d31215544910
+ e3cc21fd348f6224.0979526b3762c87e.9a13f68777f17941.ba074f761d6ea6db
+ 67b3cdbec4fee108
+ after
+ ec7bc7cf659b6ccc.5532e86dc600fde2.7927fcc446d6ce30.6150ee42785838ef
+ 7397f084d3b07d8a.b7f89b47410d3f3d.bc1dd80bf8946482.93225c2512268dfa
+ 0000000000000000.0000000000000000.bc1dfcc4f894ce30.9322ee4278588dfa
+ e3cc21fd348f6224.0979526b3762c87e.9a13f68777f17941.ba074f761d6ea6db
+ 67b3cdbec4fee108
+
+VPEXTRW_128_EregOnly_toG_0x0(reg)
+ before
+ a0404754a9923642.857d20995f71ae57.b0cc4f8ce9c389bc.eeac2f947baa7104
+ c2f9bba665b5e136.e8f90a06abb03208.d2e606f3e6ad419e.5469d4bbd37802f1
+ 272c241f97f41d8f.e70a5b2f3457a864.ca12750bcaad2dcf.aa1662e89a69e732
+ 2c237f2ad8da27fa.607d8d001772cd97.f49e983f304e88fc.cb7e5408ed89ddf4
+ 926f2605e7e39f62
+ after
+ a0404754a9923642.857d20995f71ae57.b0cc4f8ce9c389bc.eeac2f947baa7104
+ c2f9bba665b5e136.e8f90a06abb03208.d2e606f3e6ad419e.5469d4bbd37802f1
+ 272c241f97f41d8f.e70a5b2f3457a864.ca12750bcaad2dcf.aa1662e89a69e732
+ 2c237f2ad8da27fa.607d8d001772cd97.f49e983f304e88fc.cb7e5408ed89ddf4
+ 0000000000007104
+VPEXTRW_128_EregOnly_toG_0x0(mem)
+ before
+ ddb354cda483eba9.2d2bc635c6f43a23.2d1d1e656f0d5ccc.abd469fdb41c8fd0
+ 86175a4a42757bf4.8690f7abfdcc94b5.2cb8884a5935132f.4d01e6b0f3a37ef8
+ 6b67b56adac60c71.939e0df818f06f5d.38194a9bf1f5acee.35710ac48870911f
+ 666fe0188a815949.b1a00489b4ec07c6.2c0bdd455159e333.be70d1a5100e04f3
+ 464937c0260a121d
+ after
+ ddb354cda483eba9.2d2bc635c6f43a23.2d1d1e656f0d5ccc.abd469fdb41c8fd0
+ 86175a4a42757bf4.8690f7abfdcc94b5.2cb8884a5935132f.4d01e6b0f3a37ef8
+ 6b67b56adac60c71.939e0df818f06f5d.38194a9bf1f5acee.35710ac48870911f
+ 666fe0188a815949.b1a00489b4ec07c6.2c0bdd455159e333.be70d1a5100e04f3
+ 464937c0260a121d
+
+VPEXTRW_128_EregOnly_toG_0x0(reg)
+ before
+ 274a397f67eff74c.55fa57406eb220ab.3ae4d9c86c4b9a9d.e55bbe32986e762a
+ bfbdd14f6e49f129.12d696cea1661bc0.8bb48622dc99628e.40d56a4fe03f1f00
+ 68effd9dd8a53a63.7acd1aae3fa807b7.005d0904a1629c44.17455c8945d99be1
+ 802cb9d4408e0fa4.6aac5ecc65859fba.f52c5dd85733846c.487710cbe347a5f8
+ ad360201d895fb72
+ after
+ 274a397f67eff74c.55fa57406eb220ab.3ae4d9c86c4b9a9d.e55bbe32986e762a
+ bfbdd14f6e49f129.12d696cea1661bc0.8bb48622dc99628e.40d56a4fe03f1f00
+ 68effd9dd8a53a63.7acd1aae3fa807b7.005d0904a1629c44.17455c8945d99be1
+ 802cb9d4408e0fa4.6aac5ecc65859fba.f52c5dd85733846c.487710cbe347a5f8
+ 000000000000762a
+VPEXTRW_128_EregOnly_toG_0x0(mem)
+ before
+ 2350af163dcf577a.61c0ff5f4390ac99.bc3fde152e08a0f6.c56a7f0c999755b1
+ 868f92f83002763d.69f7cdac7c384ded.4d521673b73dc696.ce66690b031a4cc0
+ b3c02792cd3913e7.f21c1d2688112d4d.fab082d41c30cdc7.6b6b19413249a545
+ 84afead12f81eba3.597ced3902a78964.9d279f2277ee70b4.f8c48a1ac1af9beb
+ d1beb8024dd96c5f
+ after
+ 2350af163dcf577a.61c0ff5f4390ac99.bc3fde152e08a0f6.c56a7f0c999755b1
+ 868f92f83002763d.69f7cdac7c384ded.4d521673b73dc696.ce66690b031a4cc0
+ b3c02792cd3913e7.f21c1d2688112d4d.fab082d41c30cdc7.6b6b19413249a545
+ 84afead12f81eba3.597ced3902a78964.9d279f2277ee70b4.f8c48a1ac1af9beb
+ d1beb8024dd96c5f
+
+VPEXTRW_128_EregOnly_toG_0x0(reg)
+ before
+ 52a59f657152524c.d628589f72e5ba9e.fb64395186879cdf.1381e84be7826c8a
+ d6c53cafcaa6895f.85f6ebe9b3713c03.321efbdab13ca46a.388bd93a85f97d75
+ bb6a8a4cf3614f43.6de7219c0e312cff.5bf631411f52dbb0.e811eedb705e5ea0
+ 5ce085a98910dea6.6ac575a29e3247be.d23ad6f06b567d5e.ffdfa41ac1bdcc38
+ 59c175e397238368
+ after
+ 52a59f657152524c.d628589f72e5ba9e.fb64395186879cdf.1381e84be7826c8a
+ d6c53cafcaa6895f.85f6ebe9b3713c03.321efbdab13ca46a.388bd93a85f97d75
+ bb6a8a4cf3614f43.6de7219c0e312cff.5bf631411f52dbb0.e811eedb705e5ea0
+ 5ce085a98910dea6.6ac575a29e3247be.d23ad6f06b567d5e.ffdfa41ac1bdcc38
+ 0000000000006c8a
+VPEXTRW_128_EregOnly_toG_0x0(mem)
+ before
+ d283df220b9b3f5d.14722930273e7331.585d64e97f80496b.f335e65431d3c81f
+ 46f05ec33b31bb43.416e734f69784993.137b685bce25ed33.1b325dda0e55f6a0
+ 91d56cb243f1b445.3e1e5d71ec499d75.77ebffe6a62ff141.a47e38ed9d69448d
+ 8ffe87dc3ee8e690.66cfe5014c3dab86.6079a47524a90fc2.eb6572f87b9aee91
+ 4c33076943742f59
+ after
+ d283df220b9b3f5d.14722930273e7331.585d64e97f80496b.f335e65431d3c81f
+ 46f05ec33b31bb43.416e734f69784993.137b685bce25ed33.1b325dda0e55f6a0
+ 91d56cb243f1b445.3e1e5d71ec499d75.77ebffe6a62ff141.a47e38ed9d69448d
+ 8ffe87dc3ee8e690.66cfe5014c3dab86.6079a47524a90fc2.eb6572f87b9aee91
+ 4c33076943742f59
+
+VPEXTRW_128_EregOnly_toG_0x7(reg)
+ before
+ 2334f3ab92844490.1c37292b48220d4f.17cd066d24e1af70.aaf0d3f463a003e2
+ ccb4332a035569e3.144cd08d7ea9e4af.ab63bd2010c0e5e0.311d094f801f8bcc
+ a3fec1523374d9fe.5309f8edfc8b28dc.80df0486ad668881.d1cdc072963261ad
+ 04609b8fbd6bd18c.b5391b36ddd49501.f08bd90b9760d500.66ca764ac2e641b0
+ cbe1a6c11f46e902
+ after
+ 2334f3ab92844490.1c37292b48220d4f.17cd066d24e1af70.aaf0d3f463a003e2
+ ccb4332a035569e3.144cd08d7ea9e4af.ab63bd2010c0e5e0.311d094f801f8bcc
+ a3fec1523374d9fe.5309f8edfc8b28dc.80df0486ad668881.d1cdc072963261ad
+ 04609b8fbd6bd18c.b5391b36ddd49501.f08bd90b9760d500.66ca764ac2e641b0
+ 00000000000017cd
+VPEXTRW_128_EregOnly_toG_0x7(mem)
+ before
+ deddcdc4ca5e13cf.4a24bc4e3dc98d3a.15aab7563d8ee64a.59b5371c69390708
+ 7a8c6540de3b7c42.d39721f9511749b3.5126473839c7d8e5.15a71a23bf7d5c46
+ 7bb8ec2077e8e088.fa05c4fe92e340a4.447a47c8ec8b27fc.81ae7f8d36b90e66
+ bc2fdd4fb271facc.1bb9a3c79eb8b0b9.ca7233f373e48fbb.fa1561c769785913
+ da2abb3cf5467bfa
+ after
+ deddcdc4ca5e13cf.4a24bc4e3dc98d3a.15aab7563d8ee64a.59b5371c69390708
+ 7a8c6540de3b7c42.d39721f9511749b3.5126473839c7d8e5.15a71a23bf7d5c46
+ 7bb8ec2077e8e088.fa05c4fe92e340a4.447a47c8ec8b27fc.81ae7f8d36b90e66
+ bc2fdd4fb271facc.1bb9a3c79eb8b0b9.ca7233f373e48fbb.fa1561c769785913
+ da2abb3cf5467bfa
+
+VPEXTRW_128_EregOnly_toG_0x7(reg)
+ before
+ 7e378c5775b0aec7.1bbbb4bbabe3873b.9201b9c21123d29d.bed988a3e9e1cb4f
+ 428acd8686412f25.7229ed4f7d494300.ba27025a86aee5fd.fe7dc1c56b8b98e4
+ 826d7b34c38539c0.9f4405f744b0ea48.f1787bfb99e82384.64285a4614f0b1a5
+ 9b2d93cdc8090a45.7dda779f1d22373f.92401e11e75ac9df.cea7cf10011bd4bf
+ 16c69c114d18bb5e
+ after
+ 7e378c5775b0aec7.1bbbb4bbabe3873b.9201b9c21123d29d.bed988a3e9e1cb4f
+ 428acd8686412f25.7229ed4f7d494300.ba27025a86aee5fd.fe7dc1c56b8b98e4
+ 826d7b34c38539c0.9f4405f744b0ea48.f1787bfb99e82384.64285a4614f0b1a5
+ 9b2d93cdc8090a45.7dda779f1d22373f.92401e11e75ac9df.cea7cf10011bd4bf
+ 0000000000009201
+VPEXTRW_128_EregOnly_toG_0x7(mem)
+ before
+ 1a513e3414f423ad.e71610bd3358dc60.e7b6bf3323aee710.f8cbe9080b9213b9
+ b414306573bac7d8.c373ee709dfeecbd.bba359a0735db6e8.8165d74ca21b3cc0
+ c2dbee908677650d.8b922a53a4887507.d36ec2d0283d5ff3.885ae5494782819d
+ 1e71f4a16835b776.9bbdbed0e481b4ea.0ce374b15f599f5c.68f50d6b97521eff
+ 7f834d1f2d174f8f
+ after
+ 1a513e3414f423ad.e71610bd3358dc60.e7b6bf3323aee710.f8cbe9080b9213b9
+ b414306573bac7d8.c373ee709dfeecbd.bba359a0735db6e8.8165d74ca21b3cc0
+ c2dbee908677650d.8b922a53a4887507.d36ec2d0283d5ff3.885ae5494782819d
+ 1e71f4a16835b776.9bbdbed0e481b4ea.0ce374b15f599f5c.68f50d6b97521eff
+ 7f834d1f2d174f8f
+
+VPEXTRW_128_EregOnly_toG_0x7(reg)
+ before
+ 2750a0cfa65e4ffc.a6a3bf8435027a3f.4f41a855f875e513.43ceed2d33bd3250
+ bea802e99db25bf0.343dca250aea6995.036ae34c7cf1442e.52fba832c176d4fa
+ 9ed770d8af9faf18.a50b917003f841a4.13846c230d800ce7.163522ab248f4087
+ 2429e40777b2861f.d5d990523b38be97.dbdb3d4546af7ae9.6c4ad58379153322
+ 2e043fa8db1369f8
+ after
+ 2750a0cfa65e4ffc.a6a3bf8435027a3f.4f41a855f875e513.43ceed2d33bd3250
+ bea802e99db25bf0.343dca250aea6995.036ae34c7cf1442e.52fba832c176d4fa
+ 9ed770d8af9faf18.a50b917003f841a4.13846c230d800ce7.163522ab248f4087
+ 2429e40777b2861f.d5d990523b38be97.dbdb3d4546af7ae9.6c4ad58379153322
+ 0000000000004f41
+VPEXTRW_128_EregOnly_toG_0x7(mem)
+ before
+ 3930db0567959d35.ade95ce492761db2.a17343b5ceb69c9b.b7ba541dc409cae0
+ 699a258738a78d04.9365d3da9b77b07c.e3a42787d97f96db.026fac19221a3879
+ 9b0e9a186a56f392.33e745552e427b2a.783ab7b2779f6984.1a4441a4fd6eff60
+ a957b5a51aae8b0a.eabcafc2e862b968.3cff6f24c520d1c2.5a860f2bf1925c40
+ 1e81131898118bc6
+ after
+ 3930db0567959d35.ade95ce492761db2.a17343b5ceb69c9b.b7ba541dc409cae0
+ 699a258738a78d04.9365d3da9b77b07c.e3a42787d97f96db.026fac19221a3879
+ 9b0e9a186a56f392.33e745552e427b2a.783ab7b2779f6984.1a4441a4fd6eff60
+ a957b5a51aae8b0a.eabcafc2e862b968.3cff6f24c520d1c2.5a860f2bf1925c40
+ 1e81131898118bc6
+
+VPMINUW_128(reg)
+ before
+ c18148d89078c79e.7043f21b64b91399.12300c8b6563a7e1.0bc0cbc8de1089c0
+ a1d2aad875524d73.cc9ccd646285456b.088e581d3fd28142.c149488adf7a4eab
+ 19bf3582e22b59f2.992fc26e331dddab.28248fe5153a8336.3a666056e36bdcae
+ 8495e644748f26c6.b3c84e23f18e9986.ce3cad4d8127e86a.52e2911806eeeff6
+ e58b56bd650f42af
+ after
+ 0000000000000000.0000000000000000.088e581d153a8142.3a66488adf7a4eab
+ a1d2aad875524d73.cc9ccd646285456b.088e581d3fd28142.c149488adf7a4eab
+ 19bf3582e22b59f2.992fc26e331dddab.28248fe5153a8336.3a666056e36bdcae
+ 8495e644748f26c6.b3c84e23f18e9986.ce3cad4d8127e86a.52e2911806eeeff6
+ e58b56bd650f42af
+VPMINUW_128(mem)
+ before
+ cf2b2c2f1cdb9204.40a1b788c60bf29c.f633eb71b8e33327.5624afc31f26ed8a
+ ec8f8d5b465d9b22.a82da6bc742bf71f.3e3c1743a52868bb.1d268fb28cc2cd41
+ 1883f72effa11934.1785ae4b1b7971fd.67ae4e85d36af46e.7d8f4c856387c63c
+ 2fd3e59364b4c767.ebf7cca157839edf.4d560a235fb4926b.d3aadfaa41021226
+ 7bc5458cc1beedac
+ after
+ cf2b2c2f1cdb9204.40a1b788c60bf29c.f633eb71b8e33327.5624afc31f26ed8a
+ ec8f8d5b465d9b22.a82da6bc742bf71f.3e3c1743a52868bb.1d268fb28cc2cd41
+ 0000000000000000.0000000000000000.3e3c1743a5283327.1d268fb21f26cd41
+ 2fd3e59364b4c767.ebf7cca157839edf.4d560a235fb4926b.d3aadfaa41021226
+ 7bc5458cc1beedac
+
+VPMINUW_128(reg)
+ before
+ d02b7b988048957a.0d4ad47591a162e7.7ecefa2ac3d4b873.cb01c9096412ffdf
+ 30277c38192a443b.8eb63ec2a174a6df.2d553652fbf9fc65.bf790624ff91f7f5
+ f60644d928f2379c.8de1a165b03a4e7c.55d97b869c7da561.048b3d5e4b3c35da
+ 7e14cfe74a2caa48.e898784adbfe17e9.50a6c53041ecf112.7602eaa4641f77b9
+ f0ac89e3674777c0
+ after
+ 0000000000000000.0000000000000000.2d5536529c7da561.048b06244b3c35da
+ 30277c38192a443b.8eb63ec2a174a6df.2d553652fbf9fc65.bf790624ff91f7f5
+ f60644d928f2379c.8de1a165b03a4e7c.55d97b869c7da561.048b3d5e4b3c35da
+ 7e14cfe74a2caa48.e898784adbfe17e9.50a6c53041ecf112.7602eaa4641f77b9
+ f0ac89e3674777c0
+VPMINUW_128(mem)
+ before
+ 5053970670bff118.249d1acf1b63d8ec.7aa73f5d3dccbd53.7c0811bd87d31a25
+ 71c58ff89a93a3f0.44ec20fc3623fe34.1fda728af3b1fce5.334b5a9a09bd5d45
+ 2ecceda701d04772.3a4fddd938f858cb.b2fd8ebe18b88fcd.d2bb9c326436f51f
+ 65352efec2819aca.61104dd4bb6f225e.11db0ee3c9ed3334.b5a3d3f033cb1f5e
+ 3950fb42130717af
+ after
+ 5053970670bff118.249d1acf1b63d8ec.7aa73f5d3dccbd53.7c0811bd87d31a25
+ 71c58ff89a93a3f0.44ec20fc3623fe34.1fda728af3b1fce5.334b5a9a09bd5d45
+ 0000000000000000.0000000000000000.1fda3f5d3dccbd53.334b11bd09bd1a25
+ 65352efec2819aca.61104dd4bb6f225e.11db0ee3c9ed3334.b5a3d3f033cb1f5e
+ 3950fb42130717af
+
+VPMINUW_128(reg)
+ before
+ b80f11939f7619be.f1cccce9f9b25725.177d6c585e149798.16426ee6215da349
+ 8f290f4f74a56036.ad5c4554c1703caf.b7e037d1bb71f426.9ffc2ab43d139d35
+ 1aedf3e22d1f29c4.77b3142b36c60393.9c86a9ab6e1475b3.86d6be38381bdb27
+ b5a6b8b86771b013.299bb65b75c168fe.24babe52148855ed.a99ca75d2e821a49
+ e21a60113d5315c8
+ after
+ 0000000000000000.0000000000000000.9c8637d16e1475b3.86d62ab4381b9d35
+ 8f290f4f74a56036.ad5c4554c1703caf.b7e037d1bb71f426.9ffc2ab43d139d35
+ 1aedf3e22d1f29c4.77b3142b36c60393.9c86a9ab6e1475b3.86d6be38381bdb27
+ b5a6b8b86771b013.299bb65b75c168fe.24babe52148855ed.a99ca75d2e821a49
+ e21a60113d5315c8
+VPMINUW_128(mem)
+ before
+ 0f1b653f7e9b8acf.bc9f5b3ebd2530d0.a1e1a5ce996b291b.a9ca7232485ad17d
+ 0a6d32d30f64338b.8b26d7decbc9e7a7.b9515f72bfd30018.8900c2b8a7152512
+ b1da44b90cbdcd27.7e8527052ee90e43.4eb75f310202aa1e.1eaaa94ecc458d55
+ de2f15de8faf13d0.f10949208110e451.3ddf21f97f06e25b.c6122362547744f5
+ db852c5eda35879c
+ after
+ 0f1b653f7e9b8acf.bc9f5b3ebd2530d0.a1e1a5ce996b291b.a9ca7232485ad17d
+ 0a6d32d30f64338b.8b26d7decbc9e7a7.b9515f72bfd30018.8900c2b8a7152512
+ 0000000000000000.0000000000000000.a1e15f72996b0018.89007232485a2512
+ de2f15de8faf13d0.f10949208110e451.3ddf21f97f06e25b.c6122362547744f5
+ db852c5eda35879c
+
+VPHMINPOSUW_128(reg)
+ before
+ bb4ec0b0fb0e92f7.6e38232cb748c2b2.40fe399a61caa37c.609421b551ea66fb
+ c0bbdcc3528ba0b1.3ec1ea909e9396f8.c7b0f1de6aa38971.94a4dc5195baf02a
+ 48177b037b3aee77.2895e4f7609d4bcf.e26a6f5a3728cfdc.b5d9cdb966833c13
+ adad99dc13a7b8f4.09828f4b1a709c62.ed7aae7964e4b468.a00070d9e05108e2
+ 2fe5419d202e0ec5
+ after
+ bb4ec0b0fb0e92f7.6e38232cb748c2b2.40fe399a61caa37c.609421b551ea66fb
+ 0000000000000000.0000000000000000.0000000000000000.0000000000053728
+ 48177b037b3aee77.2895e4f7609d4bcf.e26a6f5a3728cfdc.b5d9cdb966833c13
+ adad99dc13a7b8f4.09828f4b1a709c62.ed7aae7964e4b468.a00070d9e05108e2
+ 2fe5419d202e0ec5
+VPHMINPOSUW_128(mem)
+ before
+ 3f54bcf142280be5.4cca32bab65c3ad5.bd52667ae71b46de.442aaaa78e6472c2
+ ac185ec1614abb71.81ba4209ffe7afc6.20d2e56fe4a7056f.42c7605050324695
+ 52ffa2fa99a1d993.a9c9c6358ad45472.0ecf88162c229440.459dcae147dd6c8e
+ 0dd3048607382278.1e43b9abf4ad6586.6312cb5bdc97b07e.a8f8e6c40eee1f58
+ c623af6641f39ca0
+ after
+ 3f54bcf142280be5.4cca32bab65c3ad5.bd52667ae71b46de.442aaaa78e6472c2
+ ac185ec1614abb71.81ba4209ffe7afc6.20d2e56fe4a7056f.42c7605050324695
+ 0000000000000000.0000000000000000.0000000000000000.000000000003442a
+ 0dd3048607382278.1e43b9abf4ad6586.6312cb5bdc97b07e.a8f8e6c40eee1f58
+ c623af6641f39ca0
+
+VPHMINPOSUW_128(reg)
+ before
+ fd6c21347e771f12.b9610053c71b524b.3d7317d5d9011dad.fb6a2b2a0f131555
+ a81d39995e07e459.3275134cf3562438.62a7dd21d459b994.b3a2236fe2a17ff0
+ 2283f2007f2e2622.54dbb85caaf6566d.e92905f9814375e7.65852f16704da97b
+ c9ea47d77d782219.fb5f6b710507a214.2e468dcb7d4a8d51.ede0cc0cd5245023
+ 297f743b2e313014
+ after
+ fd6c21347e771f12.b9610053c71b524b.3d7317d5d9011dad.fb6a2b2a0f131555
+ 0000000000000000.0000000000000000.0000000000000000.00000000000605f9
+ 2283f2007f2e2622.54dbb85caaf6566d.e92905f9814375e7.65852f16704da97b
+ c9ea47d77d782219.fb5f6b710507a214.2e468dcb7d4a8d51.ede0cc0cd5245023
+ 297f743b2e313014
+VPHMINPOSUW_128(mem)
+ before
+ f42ea59097800579.f79e3789f37214e9.03cca8762393c459.8d4a700263fa3c7f
+ 2ab9daf82b1e8a7f.0aebbb827da7373f.48f0eb571da87a6a.6281aa0ad0e0bf1c
+ a7ec8f5e06167c52.5c1cd12eb8a3c8c6.a695b10012527e70.0936384f5f8752d5
+ 479241ae4574971d.4b7f73f940f2032b.f988755e1b9b8c9a.deb7153dad7b3156
+ 3d4e3c405549974a
+ after
+ f42ea59097800579.f79e3789f37214e9.03cca8762393c459.8d4a700263fa3c7f
+ 2ab9daf82b1e8a7f.0aebbb827da7373f.48f0eb571da87a6a.6281aa0ad0e0bf1c
+ 0000000000000000.0000000000000000.0000000000000000.00000000000703cc
+ 479241ae4574971d.4b7f73f940f2032b.f988755e1b9b8c9a.deb7153dad7b3156
+ 3d4e3c405549974a
+
+VPHMINPOSUW_128(reg)
+ before
+ 8248acc4f37cc15e.e6796bd40345960d.315e9f4faf212419.1d95b35b56916212
+ 09f15e3624a1eb3d.5f6b89bc5d94364d.6c06519da4bc663d.ed87e7e5df40ba04
+ 2e954f0084435094.903517526e6d330a.56c3834db94d0643.472c8ee6d1b2519d
+ 4d807c90aeee2d0f.54a3918253dd4970.4ce133cd8a6240d6.064e234c49f5e309
+ 05bb220162152b73
+ after
+ 8248acc4f37cc15e.e6796bd40345960d.315e9f4faf212419.1d95b35b56916212
+ 0000000000000000.0000000000000000.0000000000000000.0000000000040643
+ 2e954f0084435094.903517526e6d330a.56c3834db94d0643.472c8ee6d1b2519d
+ 4d807c90aeee2d0f.54a3918253dd4970.4ce133cd8a6240d6.064e234c49f5e309
+ 05bb220162152b73
+VPHMINPOSUW_128(mem)
+ before
+ 223d07f3381ce608.c1fde0513e2ebe59.8680743827ef33aa.aaab5c87b4874fa3
+ 38a14e0de819d0f4.e85a78aed1903e1f.049a3a6107afaee4.cd6ffae9d2467056
+ 22b3743b8d15a562.1de13e15039feb0c.a8bb61e70e2a754c.0f77095e812ddf9a
+ be3ef469441e207f.bbdf30f16fe8ffcd.50b065b8596b460c.cd1086525cc8d81b
+ 63866b31ffa19686
+ after
+ 223d07f3381ce608.c1fde0513e2ebe59.8680743827ef33aa.aaab5c87b4874fa3
+ 38a14e0de819d0f4.e85a78aed1903e1f.049a3a6107afaee4.cd6ffae9d2467056
+ 0000000000000000.0000000000000000.0000000000000000.00000000000527ef
+ be3ef469441e207f.bbdf30f16fe8ffcd.50b065b8596b460c.cd1086525cc8d81b
+ 63866b31ffa19686
+
+VPMAXSW_128(reg)
+ before
+ 2d25b66707475687.e6104a84293ffe76.20a048aeb1f6b60d.d745c0be037edb50
+ 87396360104354ca.78f3f2765784fb74.a77085b866554e79.1846f0e72970f145
+ cd0d6c88b523ccfa.4eb4682ceafad2a4.ab9ae07c299201bd.f07f701ee64c4317
+ 5cefcf4c9372f9c3.451f2993ffac4033.8a6c566497380c84.3cbcbc4f561f8ff1
+ d6c8506696f48f00
+ after
+ 0000000000000000.0000000000000000.ab9ae07c66554e79.1846701e29704317
+ 87396360104354ca.78f3f2765784fb74.a77085b866554e79.1846f0e72970f145
+ cd0d6c88b523ccfa.4eb4682ceafad2a4.ab9ae07c299201bd.f07f701ee64c4317
+ 5cefcf4c9372f9c3.451f2993ffac4033.8a6c566497380c84.3cbcbc4f561f8ff1
+ d6c8506696f48f00
+VPMAXSW_128(mem)
+ before
+ 9c70a94fc2d7006f.8e29871644bc18d2.3a00b095b1a7014d.9e30e4dd4bd3aa7b
+ 688141f6f5d49d6c.bf089054678e64d3.072379201cf5d11d.45338554e2ef194e
+ 17c496474bf82320.4dd8e67196731b72.8a53011f5ea56bd0.d9c13534f71993a8
+ 8608242fe14e4eb9.93e485d86df8775a.9d5ec27e90c08c91.b826f1e827dd5436
+ 3cadb3de0dc59aa3
+ after
+ 9c70a94fc2d7006f.8e29871644bc18d2.3a00b095b1a7014d.9e30e4dd4bd3aa7b
+ 688141f6f5d49d6c.bf089054678e64d3.072379201cf5d11d.45338554e2ef194e
+ 0000000000000000.0000000000000000.3a0079201cf5014d.4533e4dd4bd3194e
+ 8608242fe14e4eb9.93e485d86df8775a.9d5ec27e90c08c91.b826f1e827dd5436
+ 3cadb3de0dc59aa3
+
+VPMAXSW_128(reg)
+ before
+ c2a47981455f9f9c.8f186598d2e3da63.ed7a6af789a7b537.1d0e3a29d054f08e
+ a7553e3d6c37a0cc.0fbfd7703bc2824a.b7e49039850f10b6.e630e40c3a6c52f0
+ 450dff7e1ed7d8e0.e2cbf4a237f70399.4d70f30afeb9c583.d4903c13e91570e5
+ f918b6b0f6cd8584.e4063b19e38e197c.0b6890d68f331049.c4fabf2af95a0499
+ 9039e73d8747ca38
+ after
+ 0000000000000000.0000000000000000.4d70f30afeb910b6.e6303c133a6c70e5
+ a7553e3d6c37a0cc.0fbfd7703bc2824a.b7e49039850f10b6.e630e40c3a6c52f0
+ 450dff7e1ed7d8e0.e2cbf4a237f70399.4d70f30afeb9c583.d4903c13e91570e5
+ f918b6b0f6cd8584.e4063b19e38e197c.0b6890d68f331049.c4fabf2af95a0499
+ 9039e73d8747ca38
+VPMAXSW_128(mem)
+ before
+ 151b3239afe880ed.1fc2614090a5e163.f13d25c35a947f21.4c196109d5082db5
+ 2f6a1b088c4ae0e4.1457fb9889e9292a.e63c2f8bb915f2b1.6ecf64106bc55773
+ baf31f983a79a64a.322380257d279884.9dcfd65d1b1b2e5b.ccd59455eef4cc2e
+ 9282b8d4d67f904b.d671ec5407eb6b1e.f3c195269db4ef49.c179ed46f924c593
+ ab056c4d29de814d
+ after
+ 151b3239afe880ed.1fc2614090a5e163.f13d25c35a947f21.4c196109d5082db5
+ 2f6a1b088c4ae0e4.1457fb9889e9292a.e63c2f8bb915f2b1.6ecf64106bc55773
+ 0000000000000000.0000000000000000.f13d2f8b5a947f21.6ecf64106bc55773
+ 9282b8d4d67f904b.d671ec5407eb6b1e.f3c195269db4ef49.c179ed46f924c593
+ ab056c4d29de814d
+
+VPMAXSW_128(reg)
+ before
+ e5c60cd819b03a09.93e364a77b6a5813.5c8e3c90c3c0dea4.c4e0e8d05aebf0a7
+ ca08c95265252d72.99e29eff4645bbcd.20c66b444e322dc1.ecf64c486ecdeea2
+ b8179f27aaca9635.804ae2c7521d75a5.7e6575de43cd9322.46d03b7bf665a566
+ 093f8ac3842ab0fe.24e9adebbcfd41c8.d2b756c93f1e4d72.b03a33530ebfd11f
+ 0500afbed1e82df8
+ after
+ 0000000000000000.0000000000000000.7e6575de4e322dc1.46d04c486ecdeea2
+ ca08c95265252d72.99e29eff4645bbcd.20c66b444e322dc1.ecf64c486ecdeea2
+ b8179f27aaca9635.804ae2c7521d75a5.7e6575de43cd9322.46d03b7bf665a566
+ 093f8ac3842ab0fe.24e9adebbcfd41c8.d2b756c93f1e4d72.b03a33530ebfd11f
+ 0500afbed1e82df8
+VPMAXSW_128(mem)
+ before
+ 21ed2ba65beb761d.1bcb87928ed1b878.608979589ff1dc62.78080a71ddb0975e
+ e0cf24f9c9d468bb.48099000644cea50.12f7c4f81806029e.cca38e42ba0fac92
+ 1e7014a236b0befe.ed43a379a3268232.15ff09b842476ea9.2ad5dda871c8cab9
+ b69d798dbf8a3511.67c6bc6ae6ebbbc9.456cc5853ac0deaf.eeebf3109e662b80
+ 742fcde4de760b92
+ after
+ 21ed2ba65beb761d.1bcb87928ed1b878.608979589ff1dc62.78080a71ddb0975e
+ e0cf24f9c9d468bb.48099000644cea50.12f7c4f81806029e.cca38e42ba0fac92
+ 0000000000000000.0000000000000000.608979581806029e.78080a71ddb0ac92
+ b69d798dbf8a3511.67c6bc6ae6ebbbc9.456cc5853ac0deaf.eeebf3109e662b80
+ 742fcde4de760b92
+
+VPMINSW_128(reg)
+ before
+ 18ed6592cd83a89c.8622cfa6806e8921.10ded53dca28d2c1.7e0c72491b7e0cdb
+ 3573b98406193c4a.69cb90d99369755a.45d7ec60ea6803c8.9ba98ef2018cb45a
+ 290cc42825c40447.3a6439131786b7e7.63fcfc3de3378988.7a11946b09f69457
+ 4f0382e9c7113b40.d7b8473e25d109f5.c49b01425022a2ad.f60e009f4fc966ff
+ ea6d4e7cee10e77d
+ after
+ 0000000000000000.0000000000000000.45d7ec60e3378988.9ba98ef2018c9457
+ 3573b98406193c4a.69cb90d99369755a.45d7ec60ea6803c8.9ba98ef2018cb45a
+ 290cc42825c40447.3a6439131786b7e7.63fcfc3de3378988.7a11946b09f69457
+ 4f0382e9c7113b40.d7b8473e25d109f5.c49b01425022a2ad.f60e009f4fc966ff
+ ea6d4e7cee10e77d
+VPMINSW_128(mem)
+ before
+ 34fafbed02d8d2ff.03a5f033888b1ee0.1b953548dc5727af.c5fef7daceb488e4
+ ae8082dea82be5ae.a03e087203bfe9d4.e1c57f1b5523cf42.c272db71f87977d9
+ 36cd5f3cfb17dab9.841ac812d438d8c7.0715a2a5ae42bbd9.1843a8736bfead37
+ a6ab0ef118a86d49.09852b7f98822666.675119d103bea8a1.21bd5a4cc2ce64ab
+ 3a2ced689975d8e0
+ after
+ 34fafbed02d8d2ff.03a5f033888b1ee0.1b953548dc5727af.c5fef7daceb488e4
+ ae8082dea82be5ae.a03e087203bfe9d4.e1c57f1b5523cf42.c272db71f87977d9
+ 0000000000000000.0000000000000000.e1c53548dc57cf42.c272db71ceb488e4
+ a6ab0ef118a86d49.09852b7f98822666.675119d103bea8a1.21bd5a4cc2ce64ab
+ 3a2ced689975d8e0
+
+VPMINSW_128(reg)
+ before
+ bfdb5d338d804783.dce70cea1ae95c8d.8dca2e25ea2a115d.df455f8a6fa651c6
+ 0c17a71a3a7aeb40.b24dd3141ee661af.6b37cb7067bad257.49bcf3be0e037473
+ 7d2dc6873bf001c2.05a9e1593fab39dc.fe1600cdaac1a801.82844e58fde3cbd5
+ 6e67b6e82c6cc5b6.b2c7b2a79a459f3f.a4b4c8a650c8cd07.6767ed4458511218
+ d2324d6f3a590767
+ after
+ 0000000000000000.0000000000000000.fe16cb70aac1a801.8284f3befde3cbd5
+ 0c17a71a3a7aeb40.b24dd3141ee661af.6b37cb7067bad257.49bcf3be0e037473
+ 7d2dc6873bf001c2.05a9e1593fab39dc.fe1600cdaac1a801.82844e58fde3cbd5
+ 6e67b6e82c6cc5b6.b2c7b2a79a459f3f.a4b4c8a650c8cd07.6767ed4458511218
+ d2324d6f3a590767
+VPMINSW_128(mem)
+ before
+ a0b1e9c3bf0864ee.3b1273a7aa7d72c7.9372c0e94abf5105.b75d1f69f45d7e14
+ aeb03d2d0469e6db.4079fa3251ac45a2.8578890b6c260959.945d0181330cf7d5
+ d6fac69a24894957.d8ea45f4bb877af3.65a387f91b858368.98006b59a85f74f5
+ f55dfef53c734891.61af525987994c65.0dc0389f74e87d5e.1d91585fefe43021
+ 805dc4fea5276804
+ after
+ a0b1e9c3bf0864ee.3b1273a7aa7d72c7.9372c0e94abf5105.b75d1f69f45d7e14
+ aeb03d2d0469e6db.4079fa3251ac45a2.8578890b6c260959.945d0181330cf7d5
+ 0000000000000000.0000000000000000.8578890b4abf0959.945d0181f45df7d5
+ f55dfef53c734891.61af525987994c65.0dc0389f74e87d5e.1d91585fefe43021
+ 805dc4fea5276804
+
+VPMINSW_128(reg)
+ before
+ 1eb1aba266b2574b.e7a363296733a0b3.36151ccd4f6ef9a4.5a9b18e9925bb166
+ 51d70ab8cd133aa2.889a7024c2d60dea.b369a0bcaf93bb5e.2800a1c391ebdcad
+ 761cdbaa76d64eb4.b40ca2d168664a61.34f5d8924493ce3d.53ba51198ea3ba5e
+ e9cb1ce5fe85cc2e.48c5731c76f21445.1405c2bca9fb70ed.b797a3d8a59006a6
+ 306113eaf0bd7db1
+ after
+ 0000000000000000.0000000000000000.b369a0bcaf93bb5e.2800a1c38ea3ba5e
+ 51d70ab8cd133aa2.889a7024c2d60dea.b369a0bcaf93bb5e.2800a1c391ebdcad
+ 761cdbaa76d64eb4.b40ca2d168664a61.34f5d8924493ce3d.53ba51198ea3ba5e
+ e9cb1ce5fe85cc2e.48c5731c76f21445.1405c2bca9fb70ed.b797a3d8a59006a6
+ 306113eaf0bd7db1
+VPMINSW_128(mem)
+ before
+ 9ae51d3d8e36dbaa.0732c9d601aef3bb.1e9361f1078327c1.b1e759a47a56db1b
+ d1ef3ebc9908dbbe.2a9bdce719ddfd08.1341e73c38273f02.66e59ab854304c73
+ b14bf0532d3e3b18.af535386e59c27c1.039a81e924e91734.8e4d7f62d316fea0
+ 16c5b1ed67e4b5e5.f2a7281eff7aac91.ca6babe5e7d66c82.8769061092932e4f
+ ab862a2d2e33182c
+ after
+ 9ae51d3d8e36dbaa.0732c9d601aef3bb.1e9361f1078327c1.b1e759a47a56db1b
+ d1ef3ebc9908dbbe.2a9bdce719ddfd08.1341e73c38273f02.66e59ab854304c73
+ 0000000000000000.0000000000000000.1341e73c078327c1.b1e79ab85430db1b
+ 16c5b1ed67e4b5e5.f2a7281eff7aac91.ca6babe5e7d66c82.8769061092932e4f
+ ab862a2d2e33182c
+
+VPMAXUB_128(reg)
+ before
+ 58f0e7254282f8e2.dc28fd7862070551.4fe0591a0300ca25.4380e21a9ff9fa18
+ e8f239646a0d0a1e.df424edf3bb2e987.224de2e88ebcbb28.4ca5a176655e7d24
+ b9da1d564360898b.fbdd220f0df11bb4.c739bdf33b39bc47.c0a664e35712b0d0
+ 25f28e676805b2d6.0cc6f4f2f5d15703.9aefe8a8a603082e.7b4fa74f90205048
+ 596be7a52d9419b9
+ after
+ 0000000000000000.0000000000000000.c74de2f38ebcbc47.c0a6a1e3655eb0d0
+ e8f239646a0d0a1e.df424edf3bb2e987.224de2e88ebcbb28.4ca5a176655e7d24
+ b9da1d564360898b.fbdd220f0df11bb4.c739bdf33b39bc47.c0a664e35712b0d0
+ 25f28e676805b2d6.0cc6f4f2f5d15703.9aefe8a8a603082e.7b4fa74f90205048
+ 596be7a52d9419b9
+VPMAXUB_128(mem)
+ before
+ 36c89ed14a7bc64f.8a888803768ac0aa.eec940750e5d5ba1.f7bd5e716da7dc88
+ ed304abf01e01436.42e60796097af0b4.7cb1828574a1e1ba.3aed1bbb29b07402
+ 5c70665b71cfbf99.aa59078dbb627fa0.944c370c44aaa679.bfcc1bf278ab0c47
+ 5e546f91b45582a4.1f2c85522bcda619.1164d9f89a83660a.e1a65b83f622df04
+ fec6d6d93ea42be5
+ after
+ 36c89ed14a7bc64f.8a888803768ac0aa.eec940750e5d5ba1.f7bd5e716da7dc88
+ ed304abf01e01436.42e60796097af0b4.7cb1828574a1e1ba.3aed1bbb29b07402
+ 0000000000000000.0000000000000000.eec9828574a1e1ba.f7ed5ebb6db0dc88
+ 5e546f91b45582a4.1f2c85522bcda619.1164d9f89a83660a.e1a65b83f622df04
+ fec6d6d93ea42be5
+
+VPMAXUB_128(reg)
+ before
+ 717a885fecba2995.cea7df4de67d1b84.fbad7c53f347a4cc.cec7e6349138dc9b
+ 960c6d839df218c1.8a37347c24544465.9b26e8fbaf5db364.a93fd9ab45d6c556
+ c8c981b0edd73214.6dcee90889e4b972.5ce5c5b6fb9a108e.7d992f4bd368dd67
+ 65fdc15277f6b43b.52397adf313b38d8.983410ef758bf6f6.25a162ff57fae0fb
+ 7f22f0b4ec99893e
+ after
+ 0000000000000000.0000000000000000.9be5e8fbfb9ab38e.a999d9abd3d6dd67
+ 960c6d839df218c1.8a37347c24544465.9b26e8fbaf5db364.a93fd9ab45d6c556
+ c8c981b0edd73214.6dcee90889e4b972.5ce5c5b6fb9a108e.7d992f4bd368dd67
+ 65fdc15277f6b43b.52397adf313b38d8.983410ef758bf6f6.25a162ff57fae0fb
+ 7f22f0b4ec99893e
+VPMAXUB_128(mem)
+ before
+ 65ea5454ae50955b.c8f428d5d7dadae1.174464eb39657bc3.ac60c414b6baa347
+ b5c30bccba2cc07f.4cfab2a5aa0fdfb3.96bb211abd6d3f5e.f4b5dd915cb5512e
+ 497a8f082b37c5d6.4f5b5b2e8b21005d.ad6a2f57d85f3fd5.cc7e57d003083d57
+ ffdb5ef51e7f618b.2b6220dd179d798a.361d098ea7473956.90092e3e463da26d
+ 9ca05f47c1e3bd1c
+ after
+ 65ea5454ae50955b.c8f428d5d7dadae1.174464eb39657bc3.ac60c414b6baa347
+ b5c30bccba2cc07f.4cfab2a5aa0fdfb3.96bb211abd6d3f5e.f4b5dd915cb5512e
+ 0000000000000000.0000000000000000.96bb64ebbd6d7bc3.f4b5dd91b6baa347
+ ffdb5ef51e7f618b.2b6220dd179d798a.361d098ea7473956.90092e3e463da26d
+ 9ca05f47c1e3bd1c
+
+VPMAXUB_128(reg)
+ before
+ 4c90e5581183ca11.b1b2f37eae1050ca.3e5cfb1ce90f86e7.0e9f2cab4532e70a
+ fc25bcdcd2ab05f8.3ccbca8ef8f54ec1.e296ea599e016220.12bd129ace2b0520
+ 08abe03e9fe6a97c.7df15f13173a1699.7559e9fed1014ae0.1c4439475f3f51c2
+ cc6e4eec14c0f34a.4ef22ff828eb6581.51f4f2791f9a7ad4.09fe1c9f1378851d
+ b6b7378c07e55e5c
+ after
+ 0000000000000000.0000000000000000.e296eafed10162e0.1cbd399ace3f51c2
+ fc25bcdcd2ab05f8.3ccbca8ef8f54ec1.e296ea599e016220.12bd129ace2b0520
+ 08abe03e9fe6a97c.7df15f13173a1699.7559e9fed1014ae0.1c4439475f3f51c2
+ cc6e4eec14c0f34a.4ef22ff828eb6581.51f4f2791f9a7ad4.09fe1c9f1378851d
+ b6b7378c07e55e5c
+VPMAXUB_128(mem)
+ before
+ fd3d07fc578f98ac.a4ba0051cec61f0e.8c98b5294615f7a3.d4b2033523592da7
+ bb5b06d91d84ee38.ecdaf4d968836973.13b06d928dc3872c.58de169e79c9a006
+ ccdcb21178cf1d2d.ff1b26f07f840c26.c006d31f1a02d347.3ac62a20be760f9c
+ 0c8d868f817de1b7.3bc99002ae5445d2.6d6663bc09dd9521.d7b438278eedb616
+ 89f53d1f84b9d020
+ after
+ fd3d07fc578f98ac.a4ba0051cec61f0e.8c98b5294615f7a3.d4b2033523592da7
+ bb5b06d91d84ee38.ecdaf4d968836973.13b06d928dc3872c.58de169e79c9a006
+ 0000000000000000.0000000000000000.8cb0b5928dc3f7a3.d4de169e79c9a0a7
+ 0c8d868f817de1b7.3bc99002ae5445d2.6d6663bc09dd9521.d7b438278eedb616
+ 89f53d1f84b9d020
+
+VPEXTRB_GtoE_128_0x0(reg)
+ before
+ add536743c669a65.583aff3e5799f501.fb30307b927f5024.f79b9a56756089e5
+ 9fa01e9353815092.8aaf970c132f1638.9b9c00c7c69168c8.3a73f3d77a986cc0
+ bba1f1e665952d52.7fb8cce5d34b0087.7659fe53e717ca69.12b8ea2c3590fbde
+ 5e26acdb0c2f6f52.132019b3b3fa6f1b.eab22689909cb2b4.5b37fb42c254ef6a
+ f1bca3043bf00791
+ after
+ add536743c669a65.583aff3e5799f501.fb30307b927f5024.f79b9a56756089e5
+ 9fa01e9353815092.8aaf970c132f1638.9b9c00c7c69168c8.3a73f3d77a986cc0
+ bba1f1e665952d52.7fb8cce5d34b0087.7659fe53e717ca69.12b8ea2c3590fbde
+ 5e26acdb0c2f6f52.132019b3b3fa6f1b.eab22689909cb2b4.5b37fb42c254ef6a
+ 00000000000000c0
+VPEXTRB_GtoE_128_0x0(mem)
+ before
+ b0135d5ebf71fd7e.e27949dce7d9503e.22b5fa63ce481e20.52f572d75dad5b54
+ 7408a53b68e38e5e.a4e7c65790210cc1.8841ebe1413fcac1.096ce0a8ecd503f6
+ 1966f7895250765d.00bc1eb7a393e188.2191691a27ed2f2b.6d646b68d6a0e445
+ 7bfbcf3499c670a6.52444d68bdba093e.c871eff89c5d0989.d8290f82b99b3aee
+ a806c8643151439d
+ after
+ b0135d5ebf71fd7e.e27949dce7d9503e.22b5fa63ce481e20.52f572d75dad5bf6
+ 7408a53b68e38e5e.a4e7c65790210cc1.8841ebe1413fcac1.096ce0a8ecd503f6
+ 1966f7895250765d.00bc1eb7a393e188.2191691a27ed2f2b.6d646b68d6a0e445
+ 7bfbcf3499c670a6.52444d68bdba093e.c871eff89c5d0989.d8290f82b99b3aee
+ a806c8643151439d
+
+VPEXTRB_GtoE_128_0x0(reg)
+ before
+ 37499379d84e39fd.7691aa265b513965.f6ca50d67922c090.5badf969bd9c1308
+ e33c6b2e4d1f59bb.e5f5034cb1fb8dc8.489c216d7357442a.b5100358a6b50ad4
+ 062c4ced2a4fde83.a6f35692b9d227f9.a404be9949e6cfb7.b26889b071b4aa18
+ fd6532230b6a0600.94561fe58fe2c524.664f22c6945a9ee4.2e7f085f3da6ae00
+ 0422fb502496d3ba
+ after
+ 37499379d84e39fd.7691aa265b513965.f6ca50d67922c090.5badf969bd9c1308
+ e33c6b2e4d1f59bb.e5f5034cb1fb8dc8.489c216d7357442a.b5100358a6b50ad4
+ 062c4ced2a4fde83.a6f35692b9d227f9.a404be9949e6cfb7.b26889b071b4aa18
+ fd6532230b6a0600.94561fe58fe2c524.664f22c6945a9ee4.2e7f085f3da6ae00
+ 00000000000000d4
+VPEXTRB_GtoE_128_0x0(mem)
+ before
+ 121dde6f4291d570.2533193d8dfd0bde.8becdb2f4e352176.e9c94a61f240ed5c
+ 333c2ea9b4a16f4e.d8e2fea54b9329cb.667f055e13d9f71b.8bbe30d4ff22f7cc
+ 424b65e895d45f81.73bedcc9e2b89e70.03dd195df9da053e.a77ad28d568ff9e0
+ 1d15011902365f35.5312af14edf9a47c.3dd093181c42050c.99482bf793102f43
+ bc75377d5333d5a1
+ after
+ 121dde6f4291d570.2533193d8dfd0bde.8becdb2f4e352176.e9c94a61f240edcc
+ 333c2ea9b4a16f4e.d8e2fea54b9329cb.667f055e13d9f71b.8bbe30d4ff22f7cc
+ 424b65e895d45f81.73bedcc9e2b89e70.03dd195df9da053e.a77ad28d568ff9e0
+ 1d15011902365f35.5312af14edf9a47c.3dd093181c42050c.99482bf793102f43
+ bc75377d5333d5a1
+
+VPEXTRB_GtoE_128_0x0(reg)
+ before
+ 6e4ef38d328326a8.9f687d2916d12b95.d22b73f109e17899.ef25ef7a991fb4b1
+ 0a1d5992cb8d5f02.a30e5502eeb381ce.4d5625ced1fc5674.f7a8aa728c7dcd58
+ eb2f67f8badcbc5b.07d40692a5e81b0c.20ddc016e2d779b8.2f243fe90f670e2e
+ 6fcf182b9cfc7860.a5860ac4577bb67a.a70c4035d7fd1e12.75672acc41e9315e
+ a33be7073c0ff215
+ after
+ 6e4ef38d328326a8.9f687d2916d12b95.d22b73f109e17899.ef25ef7a991fb4b1
+ 0a1d5992cb8d5f02.a30e5502eeb381ce.4d5625ced1fc5674.f7a8aa728c7dcd58
+ eb2f67f8badcbc5b.07d40692a5e81b0c.20ddc016e2d779b8.2f243fe90f670e2e
+ 6fcf182b9cfc7860.a5860ac4577bb67a.a70c4035d7fd1e12.75672acc41e9315e
+ 0000000000000058
+VPEXTRB_GtoE_128_0x0(mem)
+ before
+ 976df2871ce60f7e.f14b69980c79d0bd.5bf0df8421780d45.3e31a1984cfa812d
+ 2bc9c836fe7942c6.cced54a9a7e0001d.03dd00be1febde98.4197dfa9de5bddb6
+ 3d1be402fdd54819.5e03d7cb08bd442d.7a1bea5e6ce1e3a0.0c89f7d529ab7059
+ a72fc2d53604dca2.01d7ed6bcc9ad799.9d7417502465d888.fb54e489c87673c1
+ 6a44a22f5749259b
+ after
+ 976df2871ce60f7e.f14b69980c79d0bd.5bf0df8421780d45.3e31a1984cfa81b6
+ 2bc9c836fe7942c6.cced54a9a7e0001d.03dd00be1febde98.4197dfa9de5bddb6
+ 3d1be402fdd54819.5e03d7cb08bd442d.7a1bea5e6ce1e3a0.0c89f7d529ab7059
+ a72fc2d53604dca2.01d7ed6bcc9ad799.9d7417502465d888.fb54e489c87673c1
+ 6a44a22f5749259b
+
+VPEXTRB_GtoE_128_0x1(reg)
+ before
+ b5a52d3573afc092.46d0df9dc415bc8e.13b692f48e05f60c.46b5058064847b7d
+ 38c38206b7358253.f6ccb545c311a209.eeecc3d1ea89dd32.52aa2fda484986ab
+ 4fe99c0ec066a489.94edc2b950064a3e.efc47a707eb3c7b9.9e1f114beac0b63d
+ 566576b92ace65e2.fa0081e587ff7259.738cb53ce30ef14b.04e028bd69f5c760
+ 61b8ee1edff5743f
+ after
+ b5a52d3573afc092.46d0df9dc415bc8e.13b692f48e05f60c.46b5058064847b7d
+ 38c38206b7358253.f6ccb545c311a209.eeecc3d1ea89dd32.52aa2fda484986ab
+ 4fe99c0ec066a489.94edc2b950064a3e.efc47a707eb3c7b9.9e1f114beac0b63d
+ 566576b92ace65e2.fa0081e587ff7259.738cb53ce30ef14b.04e028bd69f5c760
+ 0000000000000086
+VPEXTRB_GtoE_128_0x1(mem)
+ before
+ 9174e15868cb7a07.a9810f738ff9ff07.05d16eb58309d488.d48e6fa1b7269794
+ 70e17c59218495e4.a48a60a88e74afa7.912c0615612f2df4.6f17a40b9688f541
+ dbc93b0c252b8001.a2cc67c4c0cab16c.7adcc3f23b7d39cc.a17351e61bbf46fe
+ acf89b5d90ccf88b.01931e33c4884002.9daf233630ffb33a.c4ee719fe257c776
+ 35d400a088ddb456
+ after
+ 9174e15868cb7a07.a9810f738ff9ff07.05d16eb58309d488.d48e6fa1b72697f5
+ 70e17c59218495e4.a48a60a88e74afa7.912c0615612f2df4.6f17a40b9688f541
+ dbc93b0c252b8001.a2cc67c4c0cab16c.7adcc3f23b7d39cc.a17351e61bbf46fe
+ acf89b5d90ccf88b.01931e33c4884002.9daf233630ffb33a.c4ee719fe257c776
+ 35d400a088ddb456
+
+VPEXTRB_GtoE_128_0x1(reg)
+ before
+ 5070fa56a8dc4849.c03c17388074b9ad.1c2b846233399916.d46fa2cf5ac2586a
+ 71105b2edfe0c0fc.f3602b890e2d7f94.4edf92bbab69f854.fce9baa7d5d1e48a
+ f4fe2093c976581b.212f533d5806056c.f5fc45acc8a49967.f1e9e8acbe3912c3
+ 368744f000294c51.26760b3e7a080860.6cce9aa02577b7fc.8f3ba9c93005a044
+ b2ab78ea48414737
+ after
+ 5070fa56a8dc4849.c03c17388074b9ad.1c2b846233399916.d46fa2cf5ac2586a
+ 71105b2edfe0c0fc.f3602b890e2d7f94.4edf92bbab69f854.fce9baa7d5d1e48a
+ f4fe2093c976581b.212f533d5806056c.f5fc45acc8a49967.f1e9e8acbe3912c3
+ 368744f000294c51.26760b3e7a080860.6cce9aa02577b7fc.8f3ba9c93005a044
+ 00000000000000e4
+VPEXTRB_GtoE_128_0x1(mem)
+ before
+ 3504d1fb21fac6c8.91f7c3b32386d74b.de02d0798f41449d.0ea18c025f6e8fbf
+ f61431e8d83bd824.629a9947cb1736b4.249c1ddbb3bd754e.39c1174011135d5b
+ d0a5129d88103877.05bbc218976ba539.d6136e4e038656a0.477a37c5d7f45c7d
+ 9f84f2064e86a2ed.d6a83b92200b6086.cf323fc09baaa4bf.9618e9fd4e9cc9d0
+ 80e628541198e001
+ after
+ 3504d1fb21fac6c8.91f7c3b32386d74b.de02d0798f41449d.0ea18c025f6e8f5d
+ f61431e8d83bd824.629a9947cb1736b4.249c1ddbb3bd754e.39c1174011135d5b
+ d0a5129d88103877.05bbc218976ba539.d6136e4e038656a0.477a37c5d7f45c7d
+ 9f84f2064e86a2ed.d6a83b92200b6086.cf323fc09baaa4bf.9618e9fd4e9cc9d0
+ 80e628541198e001
+
+VPEXTRB_GtoE_128_0x1(reg)
+ before
+ 6231f037bd73ddbb.3f7d4c0f45a8d4b0.30abff210485a246.ebc40c1c96351bd6
+ 99453d10eeb9fbab.8b5b9da58a8288ef.71110a32df64a826.0697524e10317612
+ 7f6e0c4d3ef7777d.61ec5fb238217bd4.f426582f4c34aed1.fb758c4226ac729e
+ 71f857584cb88ddc.9cfa10246b90698c.1536e686e882eff4.a82b36e4f3b2cba7
+ e885cc20944d3c58
+ after
+ 6231f037bd73ddbb.3f7d4c0f45a8d4b0.30abff210485a246.ebc40c1c96351bd6
+ 99453d10eeb9fbab.8b5b9da58a8288ef.71110a32df64a826.0697524e10317612
+ 7f6e0c4d3ef7777d.61ec5fb238217bd4.f426582f4c34aed1.fb758c4226ac729e
+ 71f857584cb88ddc.9cfa10246b90698c.1536e686e882eff4.a82b36e4f3b2cba7
+ 0000000000000076
+VPEXTRB_GtoE_128_0x1(mem)
+ before
+ 974ecbe2248b83df.cc2f1c9fb1887875.18532be640db0d42.308dafa14ed9a83b
+ 9054ae17c0785a65.ea5e568c0cf475f3.b0c12ce4d30f2423.a176afee1ac61551
+ b161f1a9831f7d19.28d2028df687c003.4211900a3f376a5b.c33fe2d8e9d471e2
+ d44210868a8caa24.e2d71a0d0dcd9551.a80fd144a0609b15.f43244cb578ffa9c
+ 8f9cd233fe84ea29
+ after
+ 974ecbe2248b83df.cc2f1c9fb1887875.18532be640db0d42.308dafa14ed9a815
+ 9054ae17c0785a65.ea5e568c0cf475f3.b0c12ce4d30f2423.a176afee1ac61551
+ b161f1a9831f7d19.28d2028df687c003.4211900a3f376a5b.c33fe2d8e9d471e2
+ d44210868a8caa24.e2d71a0d0dcd9551.a80fd144a0609b15.f43244cb578ffa9c
+ 8f9cd233fe84ea29
+
+VPEXTRB_GtoE_128_0x2(reg)
+ before
+ efc9877c7d3d7d35.d7c48899f0cb9bb5.74b99c78ed532f88.c0866d7e1394727d
+ 72055f126e49f16d.94b0d3cdd1e90df6.3bc4833a31a4cb55.6444dfa4b3e1acc1
+ 729b56616d31807d.e9d56f104af1bb14.9144cbbf764da563.7213a3a29d53050b
+ 4dd969d517836710.b0fed74d77ef633a.d384707457d8f95f.c4c03665edf53887
+ 381713d7bdd30262
+ after
+ efc9877c7d3d7d35.d7c48899f0cb9bb5.74b99c78ed532f88.c0866d7e1394727d
+ 72055f126e49f16d.94b0d3cdd1e90df6.3bc4833a31a4cb55.6444dfa4b3e1acc1
+ 729b56616d31807d.e9d56f104af1bb14.9144cbbf764da563.7213a3a29d53050b
+ 4dd969d517836710.b0fed74d77ef633a.d384707457d8f95f.c4c03665edf53887
+ 00000000000000e1
+VPEXTRB_GtoE_128_0x2(mem)
+ before
+ a8e4b6e62cf91fc8.5d0993db07cae1d3.c7f6887073f0bf95.5dd26fc370d302f5
+ f1f39b7c53744be4.0078d0ddda932c72.088afc655aff8b50.8b78c31a5ecafdd0
+ f00f3e87504f41e3.90721c492b698298.5087b11849298598.b9c368e3bd48259d
+ 7f061cf23f97bef0.6b43738a96d81ff1.7cb722765c796799.43ff5a8c28d9b807
+ 857896803b09f0bb
+ after
+ a8e4b6e62cf91fc8.5d0993db07cae1d3.c7f6887073f0bf95.5dd26fc370d302ca
+ f1f39b7c53744be4.0078d0ddda932c72.088afc655aff8b50.8b78c31a5ecafdd0
+ f00f3e87504f41e3.90721c492b698298.5087b11849298598.b9c368e3bd48259d
+ 7f061cf23f97bef0.6b43738a96d81ff1.7cb722765c796799.43ff5a8c28d9b807
+ 857896803b09f0bb
+
+VPEXTRB_GtoE_128_0x2(reg)
+ before
+ da79172a93650a65.7ba2afa93b577e38.eb36d20bb96d412b.66e6cb69aefbee7e
+ a050d9f8cb7841b0.c0b07598619b3ce7.6e99343a2db322f0.ebe228df5bbbd674
+ 3247d85580cfd249.2bfceaabcc6fb628.4eb695829036ffec.e776b6c280c6daa7
+ ecab10ae4df4f9db.965288ce98e0a628.e8daf14f7e8313cc.366df0003827b742
+ b5945284a0eb2971
+ after
+ da79172a93650a65.7ba2afa93b577e38.eb36d20bb96d412b.66e6cb69aefbee7e
+ a050d9f8cb7841b0.c0b07598619b3ce7.6e99343a2db322f0.ebe228df5bbbd674
+ 3247d85580cfd249.2bfceaabcc6fb628.4eb695829036ffec.e776b6c280c6daa7
+ ecab10ae4df4f9db.965288ce98e0a628.e8daf14f7e8313cc.366df0003827b742
+ 00000000000000bb
+VPEXTRB_GtoE_128_0x2(mem)
+ before
+ 3eb7583ad31deb61.2ac87e6dcf76f213.de7dcdeee2f9c812.9852450e92259c3c
+ aea27f0eeec9ba3e.47ea1dffa1def89d.df4b34f5c6c7d913.bb678b2968a8d4e7
+ e12142ec0cfc5234.a15ce9d160ba4924.758639d15f559657.ab68c10d9d99f77a
+ b3ff1cc049c16f6e.936cde4da7951e54.7cfb586cc9afb809.c5a0e227cc8343a0
+ 655aebe192f2f206
+ after
+ 3eb7583ad31deb61.2ac87e6dcf76f213.de7dcdeee2f9c812.9852450e92259ca8
+ aea27f0eeec9ba3e.47ea1dffa1def89d.df4b34f5c6c7d913.bb678b2968a8d4e7
+ e12142ec0cfc5234.a15ce9d160ba4924.758639d15f559657.ab68c10d9d99f77a
+ b3ff1cc049c16f6e.936cde4da7951e54.7cfb586cc9afb809.c5a0e227cc8343a0
+ 655aebe192f2f206
+
+VPEXTRB_GtoE_128_0x2(reg)
+ before
+ e7e3d6a98b734158.000a8c76c224cc18.7864f8e112fcb6db.d0760eb421e2fe56
+ a787a1ea51916c41.a40c0bfa9332265f.ae9134f73e7a4b63.4dc3d69482f92269
+ 0192470f83d9ae6e.7bd21739d7f5396f.8f3f8dfdc79b1a98.cfae2cf80900e16f
+ 5150c486bad5448a.61282a1dab7cc173.79baff5e48ec5f27.32028cccd104f794
+ 528d72fcf7101f03
+ after
+ e7e3d6a98b734158.000a8c76c224cc18.7864f8e112fcb6db.d0760eb421e2fe56
+ a787a1ea51916c41.a40c0bfa9332265f.ae9134f73e7a4b63.4dc3d69482f92269
+ 0192470f83d9ae6e.7bd21739d7f5396f.8f3f8dfdc79b1a98.cfae2cf80900e16f
+ 5150c486bad5448a.61282a1dab7cc173.79baff5e48ec5f27.32028cccd104f794
+ 00000000000000f9
+VPEXTRB_GtoE_128_0x2(mem)
+ before
+ 0b195b74963016e9.f30d15ba95136a42.31dac2942ad07998.c64e87865df855bc
+ 3973c220cb719871.43143518ad1f5b42.c9b35b8970ff1e0a.d4461fe1a34b3902
+ b76723edb1de60c8.9db2200aa0845535.04816fe89a156cf4.fdf0c5dbb67147a6
+ 63c1fac564832c1a.5d34d2fd0ace92c8.be0e7c9cc31c1e83.9f9674e131f7bb54
+ 1485285db069d0b7
+ after
+ 0b195b74963016e9.f30d15ba95136a42.31dac2942ad07998.c64e87865df8554b
+ 3973c220cb719871.43143518ad1f5b42.c9b35b8970ff1e0a.d4461fe1a34b3902
+ b76723edb1de60c8.9db2200aa0845535.04816fe89a156cf4.fdf0c5dbb67147a6
+ 63c1fac564832c1a.5d34d2fd0ace92c8.be0e7c9cc31c1e83.9f9674e131f7bb54
+ 1485285db069d0b7
+
+VPEXTRB_GtoE_128_0x3(reg)
+ before
+ b909debcd051c37b.184cc496016db692.dfe4475d86894ea6.d327fd930822f1e2
+ eb6e906b2c3dd04e.b1d6fb4aa4a7ba5d.7f0e7c97b142c77c.1e986eb98433a13e
+ 04ff3cd561b932d9.0c291dcf683df6a6.99006b16268437f6.7d2d4bf8545ae9c3
+ 610add650a4f27cb.0412a6106a3c249a.8805124581dcdbbf.cbb2113d93a3879c
+ e3f23b745e1a35f5
+ after
+ b909debcd051c37b.184cc496016db692.dfe4475d86894ea6.d327fd930822f1e2
+ eb6e906b2c3dd04e.b1d6fb4aa4a7ba5d.7f0e7c97b142c77c.1e986eb98433a13e
+ 04ff3cd561b932d9.0c291dcf683df6a6.99006b16268437f6.7d2d4bf8545ae9c3
+ 610add650a4f27cb.0412a6106a3c249a.8805124581dcdbbf.cbb2113d93a3879c
+ 0000000000000084
+VPEXTRB_GtoE_128_0x3(mem)
+ before
+ a3bb458ad0ccaffc.5ed97089c48de9ce.745d10f9c4af0164.aa686d925fd5ee83
+ e5d7ab6906c4b3db.58b9efac2affb48e.3ad6d97695a24831.5a7676685bfbadf0
+ 8713e9ff1b0efbbe.a9f6583ad82fc5b9.30487b73f722b72d.f37b2b3312da54b0
+ 633b7c372cb744d2.aedca69f6cac59f9.348174dc063a0883.d3c3875f20ff1f6f
+ 559a865820f649da
+ after
+ a3bb458ad0ccaffc.5ed97089c48de9ce.745d10f9c4af0164.aa686d925fd5ee5b
+ e5d7ab6906c4b3db.58b9efac2affb48e.3ad6d97695a24831.5a7676685bfbadf0
+ 8713e9ff1b0efbbe.a9f6583ad82fc5b9.30487b73f722b72d.f37b2b3312da54b0
+ 633b7c372cb744d2.aedca69f6cac59f9.348174dc063a0883.d3c3875f20ff1f6f
+ 559a865820f649da
+
+VPEXTRB_GtoE_128_0x3(reg)
+ before
+ d44c248aae49109d.571bdffd54ca4943.c3b7d5477fffa9fa.204b409ddff6f760
+ ae245e626786ad63.3d7e8e3daf54c83c.44d2e29fafb6f469.d27359a39d6342f0
+ 3d6f2e4ae6385fd9.f33205e35a5f7bea.8d7ac711985c74f2.24c53dd85d8ca35e
+ df7992b0c8ec60ab.5301c1db71fa1e79.fafc820ad57d6640.f40d672a3a7ed7d6
+ 1c17538351449986
+ after
+ d44c248aae49109d.571bdffd54ca4943.c3b7d5477fffa9fa.204b409ddff6f760
+ ae245e626786ad63.3d7e8e3daf54c83c.44d2e29fafb6f469.d27359a39d6342f0
+ 3d6f2e4ae6385fd9.f33205e35a5f7bea.8d7ac711985c74f2.24c53dd85d8ca35e
+ df7992b0c8ec60ab.5301c1db71fa1e79.fafc820ad57d6640.f40d672a3a7ed7d6
+ 000000000000009d
+VPEXTRB_GtoE_128_0x3(mem)
+ before
+ 79ae7dd1bdeaa798.ee8e85fea82ded84.3ab83d110f2e6f14.e7a20ef702a606ff
+ e8a062ff9b7cbb38.c8fa04a222874210.8523f571500928e7.b0b96743bc628fdd
+ 43b77df906079193.c7090907d3879afd.0e0e65e85196061f.b18c8a599e3e3e84
+ 67c04aab1a96e7d5.4806929957b833f5.b24509602de2c5e8.466972a745c44fa0
+ cb9a1b984c83fddf
+ after
+ 79ae7dd1bdeaa798.ee8e85fea82ded84.3ab83d110f2e6f14.e7a20ef702a606bc
+ e8a062ff9b7cbb38.c8fa04a222874210.8523f571500928e7.b0b96743bc628fdd
+ 43b77df906079193.c7090907d3879afd.0e0e65e85196061f.b18c8a599e3e3e84
+ 67c04aab1a96e7d5.4806929957b833f5.b24509602de2c5e8.466972a745c44fa0
+ cb9a1b984c83fddf
+
+VPEXTRB_GtoE_128_0x3(reg)
+ before
+ 9b6d8198500486ea.30874501f4367729.a83f9ac449a647a4.4d935ec701f7206e
+ 142ca013edd52470.7ad8ebe7b0f2febc.41fe1ef446de12b7.bbc5df08e8e4d4dc
+ 91247576bd81131b.227eb64a69d638b9.70901895e9ebd1da.d9a8080effb29d5e
+ 6ea0fb2b5e959197.024724143befe04d.91418613ce59c0b8.810655c7616f3622
+ 90ac431e2b265c51
+ after
+ 9b6d8198500486ea.30874501f4367729.a83f9ac449a647a4.4d935ec701f7206e
+ 142ca013edd52470.7ad8ebe7b0f2febc.41fe1ef446de12b7.bbc5df08e8e4d4dc
+ 91247576bd81131b.227eb64a69d638b9.70901895e9ebd1da.d9a8080effb29d5e
+ 6ea0fb2b5e959197.024724143befe04d.91418613ce59c0b8.810655c7616f3622
+ 00000000000000e8
+VPEXTRB_GtoE_128_0x3(mem)
+ before
+ e2654cff78e4cb1a.06ee2e9f6c9bd891.f7fdb0334348b3a4.015c63db92b51bfe
+ 53ffee5665b43fa7.b7590a3f822225b5.dd6dd7919ded6de9.1a2fab57d08a1e57
+ bf44a4100da27324.dc2c8c763db3b3ae.9063131c63eac949.39045af525640470
+ 0201eb178cbb24bf.d0b4aeaf38dcbf29.ecabe2bfb44c85ef.ba296d1f2dd00af5
+ f9e8df4382596b91
+ after
+ e2654cff78e4cb1a.06ee2e9f6c9bd891.f7fdb0334348b3a4.015c63db92b51bd0
+ 53ffee5665b43fa7.b7590a3f822225b5.dd6dd7919ded6de9.1a2fab57d08a1e57
+ bf44a4100da27324.dc2c8c763db3b3ae.9063131c63eac949.39045af525640470
+ 0201eb178cbb24bf.d0b4aeaf38dcbf29.ecabe2bfb44c85ef.ba296d1f2dd00af5
+ f9e8df4382596b91
+
+VPEXTRB_GtoE_128_0x4(reg)
+ before
+ 528eacccc38c65f1.f8033d58ff0a0ea1.f13d6e580f2885d2.cd11bf66aa1f5a08
+ 2166d02689f332c0.7d1318c0829bedf9.9913c7dc5f244154.0f6026fd616d07c0
+ c2be48bd731c0fab.6c00f73a307b7cf1.2682b6a7c45b2f5b.8d669470f6444742
+ 91e00efd1a93375e.a39557b125b578b5.f2d53525d9598a95.25ed83ab84b0d5bb
+ b2c2719a27bb6d56
+ after
+ 528eacccc38c65f1.f8033d58ff0a0ea1.f13d6e580f2885d2.cd11bf66aa1f5a08
+ 2166d02689f332c0.7d1318c0829bedf9.9913c7dc5f244154.0f6026fd616d07c0
+ c2be48bd731c0fab.6c00f73a307b7cf1.2682b6a7c45b2f5b.8d669470f6444742
+ 91e00efd1a93375e.a39557b125b578b5.f2d53525d9598a95.25ed83ab84b0d5bb
+ 00000000000000fd
+VPEXTRB_GtoE_128_0x4(mem)
+ before
+ 10b1d92afd73cd40.ea1a20521ce3e784.fd9db2137e559d72.5b5942c23aab8fac
+ 1b8637451fe4afa4.29b6792815985bca.56e6864b5668a654.bb5bd8ea84dc794c
+ ae0c08d9ab18d0b0.aa0116eca03ecfdb.8a3a4e45caf95086.6f25f30a52788522
+ a711c7d0bd1dec8d.c947f1085a627e64.746686edf6145735.d404908c410cefda
+ 4443a9deec23f31f
+ after
+ 10b1d92afd73cd40.ea1a20521ce3e784.fd9db2137e559d72.5b5942c23aab8fea
+ 1b8637451fe4afa4.29b6792815985bca.56e6864b5668a654.bb5bd8ea84dc794c
+ ae0c08d9ab18d0b0.aa0116eca03ecfdb.8a3a4e45caf95086.6f25f30a52788522
+ a711c7d0bd1dec8d.c947f1085a627e64.746686edf6145735.d404908c410cefda
+ 4443a9deec23f31f
+
+VPEXTRB_GtoE_128_0x4(reg)
+ before
+ 1c303c6af049cd9e.e15ff01870ffbe6a.e1d308eade8fa510.f236aa2ff4c6768d
+ b916449ee80bb802.37c3ff9ce0c80371.50f356fdc852808d.df7537f8e31a6bb9
+ 7540bee571f4f1f8.870970482a8677ce.71f1d7acb5364b84.16f1a832dc1cf0e6
+ adfba4ab2690b32c.abfdc0086a45d6ae.a01b886540c741a4.757479cbfdd9c13f
+ d6cc26ad625c9cf1
+ after
+ 1c303c6af049cd9e.e15ff01870ffbe6a.e1d308eade8fa510.f236aa2ff4c6768d
+ b916449ee80bb802.37c3ff9ce0c80371.50f356fdc852808d.df7537f8e31a6bb9
+ 7540bee571f4f1f8.870970482a8677ce.71f1d7acb5364b84.16f1a832dc1cf0e6
+ adfba4ab2690b32c.abfdc0086a45d6ae.a01b886540c741a4.757479cbfdd9c13f
+ 00000000000000f8
+VPEXTRB_GtoE_128_0x4(mem)
+ before
+ 17c32bc626b13b27.bd93f45ca46c3c49.816a6ac8ba10db3d.38bb639306919f97
+ 1225050066e55b0e.0154a9648613c6fc.e31eea7439f343a6.971d66a2a321a109
+ a5c02f493d03b7d2.d589bf2f69118ef0.afe3bcf801faca16.178f8cfeb10282a7
+ aa5f258cc7180d9e.95803329e8f3cfd2.bf865d412e322bb8.165cd214cfc17f1d
+ efcf324e97e9d416
+ after
+ 17c32bc626b13b27.bd93f45ca46c3c49.816a6ac8ba10db3d.38bb639306919fa2
+ 1225050066e55b0e.0154a9648613c6fc.e31eea7439f343a6.971d66a2a321a109
+ a5c02f493d03b7d2.d589bf2f69118ef0.afe3bcf801faca16.178f8cfeb10282a7
+ aa5f258cc7180d9e.95803329e8f3cfd2.bf865d412e322bb8.165cd214cfc17f1d
+ efcf324e97e9d416
+
+VPEXTRB_GtoE_128_0x4(reg)
+ before
+ fd36aa19a506bd3f.ffcd63b5212f179f.9d83ffbf9f44c64e.f1d34739dda623ba
+ 9edb35e295a57544.7ed866b067549101.49df215b2b91af0f.1f96f8ce29636e45
+ 2c0bcf14055139d0.044aa96ab49339ef.f5e0946b2764c6c2.279bebeb2f73c887
+ 0411741a8e96458f.6ef0a8cd24f9c995.fdd2555a304c4612.e3ad9d7b0ae5ecac
+ 309a886cd6c297e0
+ after
+ fd36aa19a506bd3f.ffcd63b5212f179f.9d83ffbf9f44c64e.f1d34739dda623ba
+ 9edb35e295a57544.7ed866b067549101.49df215b2b91af0f.1f96f8ce29636e45
+ 2c0bcf14055139d0.044aa96ab49339ef.f5e0946b2764c6c2.279bebeb2f73c887
+ 0411741a8e96458f.6ef0a8cd24f9c995.fdd2555a304c4612.e3ad9d7b0ae5ecac
+ 00000000000000ce
+VPEXTRB_GtoE_128_0x4(mem)
+ before
+ ea2c2aa9b018854e.833b2162ce01d42f.9695dfc6d491fe21.bd015e93e2d26cac
+ ee30fe1eb4f27122.03d4d157611d2359.5907ca42df6894bd.91b9ad84d884743c
+ 167280b7fd5d198a.e1278065e2766ebc.9311e62b62894695.d5453d98aeed9a6d
+ 3fbe2d61a86336af.7a812af8ee99f102.207eae6f7800d1d6.e5f20a3b019919ec
+ 1c0c10d96c152e64
+ after
+ ea2c2aa9b018854e.833b2162ce01d42f.9695dfc6d491fe21.bd015e93e2d26c84
+ ee30fe1eb4f27122.03d4d157611d2359.5907ca42df6894bd.91b9ad84d884743c
+ 167280b7fd5d198a.e1278065e2766ebc.9311e62b62894695.d5453d98aeed9a6d
+ 3fbe2d61a86336af.7a812af8ee99f102.207eae6f7800d1d6.e5f20a3b019919ec
+ 1c0c10d96c152e64
+
+VPEXTRB_GtoE_128_0x9(reg)
+ before
+ d8df4cdf8cec1482.45df8006d01387c0.282ecc7c1f11e7d8.dd1b9ef93ed9f1ac
+ 74b7b9b7fcab09f2.04a3f4939176c6e7.487a615e146a8de9.a4b432b5cf216142
+ 4ce053ce59dd475f.58d408f5089ab150.36b1e40867311fe2.5215e78f48e3dec5
+ bba516913e0e0b75.1d3f3516508a0129.4f1e54e7b4f1d86e.c30a3773c42c2460
+ d35ea04d6007ef40
+ after
+ d8df4cdf8cec1482.45df8006d01387c0.282ecc7c1f11e7d8.dd1b9ef93ed9f1ac
+ 74b7b9b7fcab09f2.04a3f4939176c6e7.487a615e146a8de9.a4b432b5cf216142
+ 4ce053ce59dd475f.58d408f5089ab150.36b1e40867311fe2.5215e78f48e3dec5
+ bba516913e0e0b75.1d3f3516508a0129.4f1e54e7b4f1d86e.c30a3773c42c2460
+ 000000000000008d
+VPEXTRB_GtoE_128_0x9(mem)
+ before
+ 5edf9d093780fa91.1f54ff6a47cb90e2.2fb0f9e48653759b.ed0faa689836f63a
+ 4057ab9465a4027e.d23708c7119f1450.6af3ce4ac500c7d5.6dcee4f6ae8db3f2
+ 559344d8077ec334.329b2f133816d16b.aad432342a9db401.2ba8fcfc93814b41
+ 795fe6c3391af9de.99cc6fba57bc03e0.cb1ea08ed037f84b.83e9f0e8e29efcd4
+ d1ddbc2538710056
+ after
+ 5edf9d093780fa91.1f54ff6a47cb90e2.2fb0f9e48653759b.ed0faa689836f6c7
+ 4057ab9465a4027e.d23708c7119f1450.6af3ce4ac500c7d5.6dcee4f6ae8db3f2
+ 559344d8077ec334.329b2f133816d16b.aad432342a9db401.2ba8fcfc93814b41
+ 795fe6c3391af9de.99cc6fba57bc03e0.cb1ea08ed037f84b.83e9f0e8e29efcd4
+ d1ddbc2538710056
+
+VPEXTRB_GtoE_128_0x9(reg)
+ before
+ 71cf5a1f30859374.88870c3f16855fa9.6515c5280a1ee85b.a99f9544d4d94ee1
+ bf0dc8426767f3da.5dd6323abacab2c0.f0c42bc9eec8ba87.20218c42518f73ec
+ 17e101fa78a25a33.d61ad59f42f5ae51.98239f099f44b611.0c7100746466239b
+ d59801b400c2052c.ce1d705aca130e85.b77f1c54b72017a5.485b70c728691918
+ b2ab5525baa4138f
+ after
+ 71cf5a1f30859374.88870c3f16855fa9.6515c5280a1ee85b.a99f9544d4d94ee1
+ bf0dc8426767f3da.5dd6323abacab2c0.f0c42bc9eec8ba87.20218c42518f73ec
+ 17e101fa78a25a33.d61ad59f42f5ae51.98239f099f44b611.0c7100746466239b
+ d59801b400c2052c.ce1d705aca130e85.b77f1c54b72017a5.485b70c728691918
+ 00000000000000ba
+VPEXTRB_GtoE_128_0x9(mem)
+ before
+ 252c2c7c3524cb2d.557ec4da9a533070.21ac7f576c2f8f8b.ab259e17d5e71bee
+ 7dac72b6b5f4fd1e.f2df47dae2e216ac.aa937e824755ed8d.ce5e22bc9326fc98
+ 95f5a2c15720678d.0a07851e75faf48b.479ee9c77492e3b7.7d79a3b18d68f650
+ 4bd4388837b5c3a7.f8417a14ef2806bb.d3993d1212f12f36.15c11c60603947c2
+ f0818c37a726299a
+ after
+ 252c2c7c3524cb2d.557ec4da9a533070.21ac7f576c2f8f8b.ab259e17d5e71bed
+ 7dac72b6b5f4fd1e.f2df47dae2e216ac.aa937e824755ed8d.ce5e22bc9326fc98
+ 95f5a2c15720678d.0a07851e75faf48b.479ee9c77492e3b7.7d79a3b18d68f650
+ 4bd4388837b5c3a7.f8417a14ef2806bb.d3993d1212f12f36.15c11c60603947c2
+ f0818c37a726299a
+
+VPEXTRB_GtoE_128_0x9(reg)
+ before
+ 6b07eca1ffbad983.7915b1f770bece98.18db2227ebf788e5.294ff4503a7e8b36
+ e29d390a03829329.fd8487fa1e48438b.c51f79c305f3b5b8.278e8c6b0b46b3e2
+ b19070de4f08923a.b2ec387d5e5de0ad.5d5a7c54daa8cade.a72081519e546567
+ 342c8c8980da135f.731b3f6c4b0b5f29.3bd8264606a30303.87d24dec11b55bf1
+ a1706e2a807352ab
+ after
+ 6b07eca1ffbad983.7915b1f770bece98.18db2227ebf788e5.294ff4503a7e8b36
+ e29d390a03829329.fd8487fa1e48438b.c51f79c305f3b5b8.278e8c6b0b46b3e2
+ b19070de4f08923a.b2ec387d5e5de0ad.5d5a7c54daa8cade.a72081519e546567
+ 342c8c8980da135f.731b3f6c4b0b5f29.3bd8264606a30303.87d24dec11b55bf1
+ 00000000000000b5
+VPEXTRB_GtoE_128_0x9(mem)
+ before
+ d3c65ff6069c05c1.c8bc897732845247.1edb18b3025e7c2c.bae47305236f9bd4
+ f79f9c3cc03c3261.c78e641400908a9c.8df9403f9f61f5e1.38cc5ffdd099cffd
+ ebc9a1e8c85e93b4.8eec17cd878df80a.9d4132fa3c208475.0fdbe79aa6acdb29
+ 890eebe63d0ee4e9.7923a00c6104d83f.2b7f6ad2f8a7e614.9d5c06494434fa05
+ 3c9cb77443be6a3d
+ after
+ d3c65ff6069c05c1.c8bc897732845247.1edb18b3025e7c2c.bae47305236f9bf5
+ f79f9c3cc03c3261.c78e641400908a9c.8df9403f9f61f5e1.38cc5ffdd099cffd
+ ebc9a1e8c85e93b4.8eec17cd878df80a.9d4132fa3c208475.0fdbe79aa6acdb29
+ 890eebe63d0ee4e9.7923a00c6104d83f.2b7f6ad2f8a7e614.9d5c06494434fa05
+ 3c9cb77443be6a3d
+
+VPEXTRB_GtoE_128_0xE(reg)
+ before
+ 4ae7f98942d5657c.ae3bf4223958e32a.e47ffa3f2d8366e4.117f64b2ec03d6e9
+ 2189c5f3da05286e.371c3a89d8494aa4.2b4c22d08595dda8.2c0c9c85363f1221
+ 1fcd191da9dbeec1.fe7d390537ecd682.a9d6122d05c67b35.59f48f39f26854e7
+ 9e01f0754be2f41e.e02a6b83714e43f1.bc68c8c14aa37937.7201b8b93b895868
+ 540093f12eaedcd0
+ after
+ 4ae7f98942d5657c.ae3bf4223958e32a.e47ffa3f2d8366e4.117f64b2ec03d6e9
+ 2189c5f3da05286e.371c3a89d8494aa4.2b4c22d08595dda8.2c0c9c85363f1221
+ 1fcd191da9dbeec1.fe7d390537ecd682.a9d6122d05c67b35.59f48f39f26854e7
+ 9e01f0754be2f41e.e02a6b83714e43f1.bc68c8c14aa37937.7201b8b93b895868
+ 000000000000004c
+VPEXTRB_GtoE_128_0xE(mem)
+ before
+ dbbd9ccde6e39a4a.fb6f46665ba67634.b9ee4ef0a37a4c1c.bf503ff8efb7165b
+ e4044f3a7f354f03.9364175c75b4b0ad.66965d37e97cae30.0ed8733e918f8c4d
+ 49a0292216afb727.c02c5fc43697dd36.c1ef14445d602559.054d61ffcbb618b9
+ e75fa572c75e8de1.df131b083adb3a7a.a7c3ef021e336cc2.fffb03a73ab8f649
+ 5a2e57a3792161ac
+ after
+ dbbd9ccde6e39a4a.fb6f46665ba67634.b9ee4ef0a37a4c1c.bf503ff8efb71696
+ e4044f3a7f354f03.9364175c75b4b0ad.66965d37e97cae30.0ed8733e918f8c4d
+ 49a0292216afb727.c02c5fc43697dd36.c1ef14445d602559.054d61ffcbb618b9
+ e75fa572c75e8de1.df131b083adb3a7a.a7c3ef021e336cc2.fffb03a73ab8f649
+ 5a2e57a3792161ac
+
+VPEXTRB_GtoE_128_0xE(reg)
+ before
+ 7132585d257e968c.9a0b3f17ad4d8e5d.4c6546951c0d0326.f4df6a5f45014098
+ a0520243d95ad196.3e7173fce48876c8.636ddcd878b873e5.840e0246f0d45d06
+ 42db52bf32424e75.af5dbe0c891c004e.8179da3beb68c764.331e32a43bba7f39
+ b51a423fcbc148d6.c99b9b35b714ea1b.00d33a2c10aa3b4f.ddd9766341be615d
+ 5e0d4b701fedc09d
+ after
+ 7132585d257e968c.9a0b3f17ad4d8e5d.4c6546951c0d0326.f4df6a5f45014098
+ a0520243d95ad196.3e7173fce48876c8.636ddcd878b873e5.840e0246f0d45d06
+ 42db52bf32424e75.af5dbe0c891c004e.8179da3beb68c764.331e32a43bba7f39
+ b51a423fcbc148d6.c99b9b35b714ea1b.00d33a2c10aa3b4f.ddd9766341be615d
+ 000000000000006d
+VPEXTRB_GtoE_128_0xE(mem)
+ before
+ 92842bb8f0525826.5359d02e4063fc65.68f786628b7ced5a.3dc8fa1684090b51
+ 550b9425d0f9e523.7ae4f8f82eb5a6cd.683cfb7f2061c837.94a41564e2117217
+ 836d01a5dcef22c1.8409b409314281ba.a538767893ce35df.61b38784c74fad4c
+ f778ee232f3fcc2c.cf1301cde496cada.fab57439ffcff27e.00414de1ce4ef89d
+ cd9961e8949b8fb6
+ after
+ 92842bb8f0525826.5359d02e4063fc65.68f786628b7ced5a.3dc8fa1684090b3c
+ 550b9425d0f9e523.7ae4f8f82eb5a6cd.683cfb7f2061c837.94a41564e2117217
+ 836d01a5dcef22c1.8409b409314281ba.a538767893ce35df.61b38784c74fad4c
+ f778ee232f3fcc2c.cf1301cde496cada.fab57439ffcff27e.00414de1ce4ef89d
+ cd9961e8949b8fb6
+
+VPEXTRB_GtoE_128_0xE(reg)
+ before
+ 2408c103b4c0ad42.8ff6d88ae6f59f8f.b54ddcb0e33ebdd7.458070ae8170b83f
+ 61da699fcb4c8fee.26b53ac81d1e5617.9404401ecbc5965d.6165e6c434be464f
+ df5b532874c87065.987f8fc8efc5aeef.c6842a8337b79019.2a30526534c556da
+ fcd77c0b4bc28e54.c021567678f66344.a819944cc4a1e8b7.7bac317f9f90a50b
+ 32a7fdfc8e2bef0f
+ after
+ 2408c103b4c0ad42.8ff6d88ae6f59f8f.b54ddcb0e33ebdd7.458070ae8170b83f
+ 61da699fcb4c8fee.26b53ac81d1e5617.9404401ecbc5965d.6165e6c434be464f
+ df5b532874c87065.987f8fc8efc5aeef.c6842a8337b79019.2a30526534c556da
+ fcd77c0b4bc28e54.c021567678f66344.a819944cc4a1e8b7.7bac317f9f90a50b
+ 0000000000000004
+VPEXTRB_GtoE_128_0xE(mem)
+ before
+ 2aeb34ca1fa2ef11.139ae1b3edc52366.7c6708bfd5be3041.970f7ce30d0edae2
+ 3e4552d46e02623e.80ef7d8bf65e6c49.a71c238d2128d313.edb2ddb6af8aa147
+ 4c81d106955604c1.9e244c010117a4a6.1c0e21cd794006e6.074db33045a27a91
+ 2f6b2f4cb3aa91c8.cb834b80aa7f092c.b907806cf81385e5.412dfabd6ce1a16d
+ f89eafc8bfd35287
+ after
+ 2aeb34ca1fa2ef11.139ae1b3edc52366.7c6708bfd5be3041.970f7ce30d0eda1c
+ 3e4552d46e02623e.80ef7d8bf65e6c49.a71c238d2128d313.edb2ddb6af8aa147
+ 4c81d106955604c1.9e244c010117a4a6.1c0e21cd794006e6.074db33045a27a91
+ 2f6b2f4cb3aa91c8.cb834b80aa7f092c.b907806cf81385e5.412dfabd6ce1a16d
+ f89eafc8bfd35287
+
+VPEXTRB_GtoE_128_0xF(reg)
+ before
+ 86ecccc0db05c88a.c2cee692e20bc47c.625975748e1fd585.58d5bc54baac0e3d
+ 48634f0e5b024023.e37875c43e845a0c.bef2c5494985445d.d7424f73dd185b1a
+ 9a4f341fdb56f6fd.6c3355cfe4210fa1.3d9a3a6b753c9461.101bb7b47a6129a7
+ d8fb755ff88e26c5.3bcc039defef9e6a.3a9ccd46b1d1ff3d.e12b6f02af963311
+ 2440f34b98c03783
+ after
+ 86ecccc0db05c88a.c2cee692e20bc47c.625975748e1fd585.58d5bc54baac0e3d
+ 48634f0e5b024023.e37875c43e845a0c.bef2c5494985445d.d7424f73dd185b1a
+ 9a4f341fdb56f6fd.6c3355cfe4210fa1.3d9a3a6b753c9461.101bb7b47a6129a7
+ d8fb755ff88e26c5.3bcc039defef9e6a.3a9ccd46b1d1ff3d.e12b6f02af963311
+ 00000000000000be
+VPEXTRB_GtoE_128_0xF(mem)
+ before
+ b724bf7a50edef2a.5eb5103a4e350b27.2a0ffc1b7cf9c491.10467b4796cfc29c
+ 74a5507cf3281731.88c7ff1d78d7e2ce.16c8bb36a64c3d43.1de241d8c3c2182b
+ 388d203b9e7d6dc5.b27e41731201e667.dcc3bcd98af3c5ab.bbbd1a67d1373f96
+ e0a9ada46cf9ab12.3826cfa7b93e559d.56cb7cef43fa17f6.4823025e5eb97188
+ 1e60f62b06d4eaad
+ after
+ b724bf7a50edef2a.5eb5103a4e350b27.2a0ffc1b7cf9c491.10467b4796cfc216
+ 74a5507cf3281731.88c7ff1d78d7e2ce.16c8bb36a64c3d43.1de241d8c3c2182b
+ 388d203b9e7d6dc5.b27e41731201e667.dcc3bcd98af3c5ab.bbbd1a67d1373f96
+ e0a9ada46cf9ab12.3826cfa7b93e559d.56cb7cef43fa17f6.4823025e5eb97188
+ 1e60f62b06d4eaad
+
+VPEXTRB_GtoE_128_0xF(reg)
+ before
+ 9ac0f0396415e8b3.46c472a47aa78e43.760ba627091b691d.61ae7566ee6df04f
+ 198eeef41506a543.47acec25e494d285.c878c35e9c235f93.d9362529a6590ce3
+ f517ebc8b4365e0c.bf2c9615c4cb3203.89bb21b811e272aa.9b30072487c926de
+ 8ba8e421dd2e4eb8.8b0feb5e39586bea.171ebca102e4df0f.81689743aecafc6b
+ 68aa5273376747b7
+ after
+ 9ac0f0396415e8b3.46c472a47aa78e43.760ba627091b691d.61ae7566ee6df04f
+ 198eeef41506a543.47acec25e494d285.c878c35e9c235f93.d9362529a6590ce3
+ f517ebc8b4365e0c.bf2c9615c4cb3203.89bb21b811e272aa.9b30072487c926de
+ 8ba8e421dd2e4eb8.8b0feb5e39586bea.171ebca102e4df0f.81689743aecafc6b
+ 00000000000000c8
+VPEXTRB_GtoE_128_0xF(mem)
+ before
+ 2cc1b29e3dacc6ed.388bd36b2d7db3f4.852269ee5c483966.cdee91850bb6e26d
+ a97b35b1dca6333a.560cb61240acc76b.8a318cb04ca557a2.07779ad0c9e3b771
+ bba25699315f4cca.42798883b149c6ca.7608ce90227e82cb.2005d5eed7f899c6
+ 3e03924158e6cac8.581d45281cdfeebc.2573ad7afddc760c.76e33d4cd180c51a
+ 645fce5454077716
+ after
+ 2cc1b29e3dacc6ed.388bd36b2d7db3f4.852269ee5c483966.cdee91850bb6e28a
+ a97b35b1dca6333a.560cb61240acc76b.8a318cb04ca557a2.07779ad0c9e3b771
+ bba25699315f4cca.42798883b149c6ca.7608ce90227e82cb.2005d5eed7f899c6
+ 3e03924158e6cac8.581d45281cdfeebc.2573ad7afddc760c.76e33d4cd180c51a
+ 645fce5454077716
+
+VPEXTRB_GtoE_128_0xF(reg)
+ before
+ 45c38574fc19eb69.0e6a63946b446c61.f443e96f1efa79ee.733da45af6cdef92
+ 775c5d1764435cbd.07a347808987ecc0.723871c25227a40c.3c342f1c2b5da889
+ 557652a9291107be.057ab9f0ccbb0712.2f48d88f55f1abc1.5c22caadb8965e1c
+ 3a5d6095e60d2819.e4ba35d050ea7983.85bf1a41c2e4c9ba.afd4f2f7b886cd78
+ 111622e84738b1c8
+ after
+ 45c38574fc19eb69.0e6a63946b446c61.f443e96f1efa79ee.733da45af6cdef92
+ 775c5d1764435cbd.07a347808987ecc0.723871c25227a40c.3c342f1c2b5da889
+ 557652a9291107be.057ab9f0ccbb0712.2f48d88f55f1abc1.5c22caadb8965e1c
+ 3a5d6095e60d2819.e4ba35d050ea7983.85bf1a41c2e4c9ba.afd4f2f7b886cd78
+ 0000000000000072
+VPEXTRB_GtoE_128_0xF(mem)
+ before
+ 5eb4d66a82b9c539.845d834937c5fa7a.8031380c3222fd3e.d1e93344368d3ba2
+ 71798a6b8514c6f7.8dc1b830b9c4ba8c.b5a93c908d6e5070.6f121f044c773d26
+ 2833bbd66b55702d.b2d7f9b70797a4fc.5fefbf497ddb2e44.bb85dbeda12f0af2
+ 5eace39750897e08.50e94448bec9f475.5acf3c21207452e7.1090626bd03fe0b1
+ cc7db0ea7635f910
+ after
+ 5eb4d66a82b9c539.845d834937c5fa7a.8031380c3222fd3e.d1e93344368d3bb5
+ 71798a6b8514c6f7.8dc1b830b9c4ba8c.b5a93c908d6e5070.6f121f044c773d26
+ 2833bbd66b55702d.b2d7f9b70797a4fc.5fefbf497ddb2e44.bb85dbeda12f0af2
+ 5eace39750897e08.50e94448bec9f475.5acf3c21207452e7.1090626bd03fe0b1
+ cc7db0ea7635f910
+
+VPMINUB_128(reg)
+ before
+ 4a99c1d72e9d91ba.efb1809a51bbadb3.c14495507ae6e5a5.811530058f457a85
+ e630929c9402e65c.b60e0dcb89f7b95b.6334e63cd57bb435.b28c15e2e85b6049
+ fc8d1ea745f032a1.918f0716154a5d2c.900535766e139dd3.c80269a347c1c05f
+ e8fe6163ddf3b237.5b00e86710bf5751.a5027d6cdf3adb2b.9e41a733c78458f5
+ 12164b8084aee235
+ after
+ 0000000000000000.0000000000000000.6305353c6e139d35.b20215a3475b6049
+ e630929c9402e65c.b60e0dcb89f7b95b.6334e63cd57bb435.b28c15e2e85b6049
+ fc8d1ea745f032a1.918f0716154a5d2c.900535766e139dd3.c80269a347c1c05f
+ e8fe6163ddf3b237.5b00e86710bf5751.a5027d6cdf3adb2b.9e41a733c78458f5
+ 12164b8084aee235
+VPMINUB_128(mem)
+ before
+ ff4dd1759b4d1b4b.05cd573bf798a1c7.ef2c2eab976361f6.fe79ba89c47dace9
+ 40b2b6fe286dbe64.b147fd9d2f6b3c00.2be154ccc5403749.f8b4e838b96749b8
+ b3107507451989ac.47b84df422f6bf8c.eae9d6b8b7649774.ed0004e75c84f144
+ 32358a7c115d364e.226c45ac6bc76617.0711315988db3ba3.3aa908014661de3b
+ 3bfbf2f215894d46
+ after
+ ff4dd1759b4d1b4b.05cd573bf798a1c7.ef2c2eab976361f6.fe79ba89c47dace9
+ 40b2b6fe286dbe64.b147fd9d2f6b3c00.2be154ccc5403749.f8b4e838b96749b8
+ 0000000000000000.0000000000000000.2b2c2eab97403749.f879ba38b96749b8
+ 32358a7c115d364e.226c45ac6bc76617.0711315988db3ba3.3aa908014661de3b
+ 3bfbf2f215894d46
+
+VPMINUB_128(reg)
+ before
+ 4c42be2765897a14.9beb714aa6458177.a0afe031a7696c4e.6025e09d54b0e003
+ c9c9660ad1eba14f.c8ffa75b20de2853.1bcd1af072690fdd.cff15e6f38ef41c0
+ 0edee808f53dfda3.963da69d9c33e50d.f111f0536652886f.31402abb50a41c05
+ 77cb3f8e6e0bcbbe.e271ecfa355075d1.7dc85dc722b016b1.63e0bd6db7dc2bff
+ 3f9b947189a22ad9
+ after
+ 0000000000000000.0000000000000000.1b111a5366520f6f.31402a6f38a41c05
+ c9c9660ad1eba14f.c8ffa75b20de2853.1bcd1af072690fdd.cff15e6f38ef41c0
+ 0edee808f53dfda3.963da69d9c33e50d.f111f0536652886f.31402abb50a41c05
+ 77cb3f8e6e0bcbbe.e271ecfa355075d1.7dc85dc722b016b1.63e0bd6db7dc2bff
+ 3f9b947189a22ad9
+VPMINUB_128(mem)
+ before
+ a23e2cb3e303d7c0.60dd6706d8e04749.8667f460084293cd.1a3e5db93f10f34e
+ 69950020e109ece0.25605cdece48acf3.60ea3bba3014fd2a.25bfec945bfc5cf4
+ 6e6c8ca29ec32664.229f1a81eccf3766.4ac83bf3c9d36d17.fb9706c312038d4c
+ 8e8f4d27363a4179.b3e89e5bcf02244e.21cb72f9f08a9fbe.f612a8b4ffaec105
+ 747bcdd2bf8b36c8
+ after
+ a23e2cb3e303d7c0.60dd6706d8e04749.8667f460084293cd.1a3e5db93f10f34e
+ 69950020e109ece0.25605cdece48acf3.60ea3bba3014fd2a.25bfec945bfc5cf4
+ 0000000000000000.0000000000000000.60673b600814932a.1a3e5d943f105c4e
+ 8e8f4d27363a4179.b3e89e5bcf02244e.21cb72f9f08a9fbe.f612a8b4ffaec105
+ 747bcdd2bf8b36c8
+
+VPMINUB_128(reg)
+ before
+ cf207189ed262544.a5c9bd99c67cf84b.3485e3d8126cae58.c1c05bb7c145514c
+ 644b90452509cd23.90e85ae669940805.01c4e564529a1330.0673731a57113dec
+ 8f49277204c26812.29b69ff93c8f2dd3.75efa16b2a168d81.cdb0340ccff820cb
+ ad66307d26dd33bc.4d0009be5a7822e2.ee531159376f58f8.f0421c7a4409b614
+ 4cf7a651d24dbaf4
+ after
+ 0000000000000000.0000000000000000.01c4a1642a161330.0673340c571120cb
+ 644b90452509cd23.90e85ae669940805.01c4e564529a1330.0673731a57113dec
+ 8f49277204c26812.29b69ff93c8f2dd3.75efa16b2a168d81.cdb0340ccff820cb
+ ad66307d26dd33bc.4d0009be5a7822e2.ee531159376f58f8.f0421c7a4409b614
+ 4cf7a651d24dbaf4
+VPMINUB_128(mem)
+ before
+ bd994e7b96d2e997.18eda9d026e46ace.d8921221e05ba45e.c73c339a142eb241
+ 1ff590e6aba3ff28.2d2c8dd8a06649f3.a637380ee9446f73.5bf5029b5ee1d507
+ 4ed7e97c2ecdb7d4.486dd90231ec0bd8.93bdf67191403f4c.08cc7bc6b013fef7
+ 260bd32b3a5bcfc6.c5fe87b97404ed29.7beec836f55bcf15.290b9889a75168bc
+ 19ff574fde265003
+ after
+ bd994e7b96d2e997.18eda9d026e46ace.d8921221e05ba45e.c73c339a142eb241
+ 1ff590e6aba3ff28.2d2c8dd8a06649f3.a637380ee9446f73.5bf5029b5ee1d507
+ 0000000000000000.0000000000000000.a637120ee0446f5e.5b3c029a142eb207
+ 260bd32b3a5bcfc6.c5fe87b97404ed29.7beec836f55bcf15.290b9889a75168bc
+ 19ff574fde265003
+
+VPMAXSB_128(reg)
+ before
+ 36f4b383f11ef278.835dccdeec59002b.0029956806392a91.3a982a49319fdcfb
+ da36a8937dc68ac6.4198508160d4092f.553bfe7d821700bd.ac859997601a222a
+ 631132ea1ea95499.3c8ad900b0d7a4fd.207fbf63852ba958.ad82900a9ed85dce
+ 2bd04ef46e538b9f.4ffde547fa6e8fc1.bd43d286aa00620f.195a8b9008e34811
+ ccdb0614ba49a022
+ after
+ 0000000000000000.0000000000000000.557ffe7d852b0058.ad85990a601a5d2a
+ da36a8937dc68ac6.4198508160d4092f.553bfe7d821700bd.ac859997601a222a
+ 631132ea1ea95499.3c8ad900b0d7a4fd.207fbf63852ba958.ad82900a9ed85dce
+ 2bd04ef46e538b9f.4ffde547fa6e8fc1.bd43d286aa00620f.195a8b9008e34811
+ ccdb0614ba49a022
+VPMAXSB_128(mem)
+ before
+ a1cf7e82cf15212b.90c1f71d0c506c81.58beef435aa683a9.88d235528e22668e
+ 76046dc563548659.ec2e29d2922d32ee.329973deeb8a3fdf.dd77e333cc1ef280
+ 264451cb93118cd7.9d64e07d9c761a90.b95aed05ca267d8f.187fd896017f4291
+ 8d5ca5807a59efd2.fdaf188cc7b56014.c9ccd9a51287fae6.953610e5c8d2926f
+ b0e8888ebda21dc4
+ after
+ a1cf7e82cf15212b.90c1f71d0c506c81.58beef435aa683a9.88d235528e22668e
+ 76046dc563548659.ec2e29d2922d32ee.329973deeb8a3fdf.dd77e333cc1ef280
+ 0000000000000000.0000000000000000.58be73435aa63fdf.dd773552cc22668e
+ 8d5ca5807a59efd2.fdaf188cc7b56014.c9ccd9a51287fae6.953610e5c8d2926f
+ b0e8888ebda21dc4
+
+VPMAXSB_128(reg)
+ before
+ c5e13afb7d7b203c.8618e6ce35366a76.695bce69ae784025.3dbdb4a9dfb87210
+ 2f6c249aa4e9d784.ef438ea2dfb6bbee.3db3fd82ee4bf670.f3f7f9fc4ec5a038
+ 4cd642d6cd797e48.a2ab1be895e59c67.d605a14122b8bda0.c647248c7bbb418b
+ 776c8e1b94b65034.7d1a088d72cdc90c.8e9bb614e74dd262.9179b24481a51135
+ 32591d107c8fcc61
+ after
+ 0000000000000000.0000000000000000.3d05fd41224bf670.f34724fc7bc54138
+ 2f6c249aa4e9d784.ef438ea2dfb6bbee.3db3fd82ee4bf670.f3f7f9fc4ec5a038
+ 4cd642d6cd797e48.a2ab1be895e59c67.d605a14122b8bda0.c647248c7bbb418b
+ 776c8e1b94b65034.7d1a088d72cdc90c.8e9bb614e74dd262.9179b24481a51135
+ 32591d107c8fcc61
+VPMAXSB_128(mem)
+ before
+ 83b2e3dc89862d3c.0b7806d5962d8af2.5b5ed17b937d000a.c2c23966d8967062
+ 62527f94c395f1f1.6647a5706e696831.1741f3a013fefb8c.cec625a3921dd54b
+ a9036e2547c9d4ad.e3246758b9f6259b.8f90e8e70e5e77bf.0ef37637b0713bca
+ 36922a79312d919b.dd5d48f91261fedd.9d162e3ca2a82fcf.de94288ece1bdf8a
+ 9bf7371589a9fc38
+ after
+ 83b2e3dc89862d3c.0b7806d5962d8af2.5b5ed17b937d000a.c2c23966d8967062
+ 62527f94c395f1f1.6647a5706e696831.1741f3a013fefb8c.cec625a3921dd54b
+ 0000000000000000.0000000000000000.5b5ef37b137d000a.cec63966d81d7062
+ 36922a79312d919b.dd5d48f91261fedd.9d162e3ca2a82fcf.de94288ece1bdf8a
+ 9bf7371589a9fc38
+
+VPMAXSB_128(reg)
+ before
+ 9f66a0367da6cf80.e3cb317e9bcde5e8.b23c45bf16352fa2.1ea1408be8e8e1e7
+ 472f5e5f459e940d.8d7afe1ea4b58cc0.bc0f581760fef497.effb9bc0fe2b4734
+ ef9c6dfa7d1e878c.116b0d4765f2424e.59207f6b8d488867.eaf2b9c7ff7c1de2
+ f2f9c975c2b1e3a8.496adae4fc8fc2bf.e3bcb62938a028c0.ed50188c08e8211c
+ d2e233fb357a0d0e
+ after
+ 0000000000000000.0000000000000000.59207f6b6048f467.effbb9c7ff7c4734
+ 472f5e5f459e940d.8d7afe1ea4b58cc0.bc0f581760fef497.effb9bc0fe2b4734
+ ef9c6dfa7d1e878c.116b0d4765f2424e.59207f6b8d488867.eaf2b9c7ff7c1de2
+ f2f9c975c2b1e3a8.496adae4fc8fc2bf.e3bcb62938a028c0.ed50188c08e8211c
+ d2e233fb357a0d0e
+VPMAXSB_128(mem)
+ before
+ 76748601a13e9ee6.ae946f3bafe4e50e.1242e2e18599c93f.b82ef7bcfe92104b
+ b5d18e88684090cd.7eb859b7e141c96a.49c0a0291b1a13f9.32c4408f7aa87bb6
+ 6cc7c57ea78d9ef2.beb08557f457cb67.c8b090abdb215b19.aec98b104970a6ad
+ 7520a9ce7930857f.cac9ee8682af26b2.6cde2e50e0b75fcc.8988d6aa0676cddc
+ 1d4e1dc94d442cee
+ after
+ 76748601a13e9ee6.ae946f3bafe4e50e.1242e2e18599c93f.b82ef7bcfe92104b
+ b5d18e88684090cd.7eb859b7e141c96a.49c0a0291b1a13f9.32c4408f7aa87bb6
+ 0000000000000000.0000000000000000.4942e2291b1a133f.322e40bc7aa87b4b
+ 7520a9ce7930857f.cac9ee8682af26b2.6cde2e50e0b75fcc.8988d6aa0676cddc
+ 1d4e1dc94d442cee
+
+VPMINSB_128(reg)
+ before
+ c7675adabb68fe8f.ada9b563fb3601a0.fe5091b12ad717f6.1116f60546ead83e
+ e31f8b47ec6e806d.f02e652b48aacd83.b58e6842855ad9e0.932465b62ac5859b
+ cec2ab7d7be0ee32.1a7b36117d98a651.4dd271a632c5aa1b.ced3f650a855200e
+ e29bb6e9044c838a.075ca301b50d4839.2167a74acaa2c455.9ef025bddba566c3
+ df476eebdfc113e8
+ after
+ 0000000000000000.0000000000000000.b58e68a685c5aae0.93d3f6b6a8c5859b
+ e31f8b47ec6e806d.f02e652b48aacd83.b58e6842855ad9e0.932465b62ac5859b
+ cec2ab7d7be0ee32.1a7b36117d98a651.4dd271a632c5aa1b.ced3f650a855200e
+ e29bb6e9044c838a.075ca301b50d4839.2167a74acaa2c455.9ef025bddba566c3
+ df476eebdfc113e8
+VPMINSB_128(mem)
+ before
+ 6da44ec4d1b6e3a6.7cf8a8f5243e7d22.939c28e70c146f65.8c980798eb806437
+ 24d34036cc8f912c.f8237e0f764116a6.9a0941b0a0b9d601.ecb38bfe31e8c570
+ e0a0c02ced58daa4.b26933a297e18ac1.f86d6a468a083a3b.9c0231e6376825a9
+ 7dd64a924f1d7a3a.0616c31922aa1720.89952096e80e573c.f7d2f4be9a8bbe91
+ 5b6fd0f1f5deccd2
+ after
+ 6da44ec4d1b6e3a6.7cf8a8f5243e7d22.939c28e70c146f65.8c980798eb806437
+ 24d34036cc8f912c.f8237e0f764116a6.9a0941b0a0b9d601.ecb38bfe31e8c570
+ 0000000000000000.0000000000000000.939c28b0a0b9d601.8c988b98eb80c537
+ 7dd64a924f1d7a3a.0616c31922aa1720.89952096e80e573c.f7d2f4be9a8bbe91
+ 5b6fd0f1f5deccd2
+
+VPMINSB_128(reg)
+ before
+ 2224c1ebe4ec8d19.d7435a540feb2c1b.50762ae2b429f76e.294dde8dd6d7e933
+ aa3fc41804413b11.cab16d5e48cead73.ecd46568e8e96658.b46120166f6dab4a
+ 4d0ad4e4f06a1367.32edfe9d17d0b96d.367e6e185b76a28a.069d621ccfde5aad
+ 69d3edbc45f250c6.ebc389fb97ff0b36.8abe435ca85de5af.facc208d1336b289
+ 6ebbd754567f6e0a
+ after
+ 0000000000000000.0000000000000000.ecd46518e8e9a28a.b49d2016cfdeabad
+ aa3fc41804413b11.cab16d5e48cead73.ecd46568e8e96658.b46120166f6dab4a
+ 4d0ad4e4f06a1367.32edfe9d17d0b96d.367e6e185b76a28a.069d621ccfde5aad
+ 69d3edbc45f250c6.ebc389fb97ff0b36.8abe435ca85de5af.facc208d1336b289
+ 6ebbd754567f6e0a
+VPMINSB_128(mem)
+ before
+ 3d36025db5c74b5b.58e40b0a9f6530db.d0ff8a66e56761fa.44e1dfa16c296c73
+ 43091d944b1a05a9.778a2a3b9850ed52.bf6c7ec81c1275e4.c0333f5342677384
+ 5b00a5e535825720.231047bccf3ec3d6.93d8e00f580f0321.5a005ddfc6a2358c
+ 63e7143d8e0dffeb.b6c45df8ddbbf014.270d2c25b667c9dc.6d9437b09566ef37
+ 573ac8314b3fdd32
+ after
+ 3d36025db5c74b5b.58e40b0a9f6530db.d0ff8a66e56761fa.44e1dfa16c296c73
+ 43091d944b1a05a9.778a2a3b9850ed52.bf6c7ec81c1275e4.c0333f5342677384
+ 0000000000000000.0000000000000000.bfff8ac8e51261e4.c0e1dfa142296c84
+ 63e7143d8e0dffeb.b6c45df8ddbbf014.270d2c25b667c9dc.6d9437b09566ef37
+ 573ac8314b3fdd32
+
+VPMINSB_128(reg)
+ before
+ 73400cd083ba3b29.358ae88673c7b737.8df0685a6154aeb8.59d8def852288142
+ 1df000f8d96244c8.afb49cadffbb3b2f.04e26450f4943a6d.04057273475de87f
+ b0979e15eac435b9.ac32ac9f4ff54900.77e44e453407d0df.03606582b112b9be
+ 8a81e493516b49ab.07d095477e819bd5.434321a5bd3aabbb.34b43211ad54b22b
+ 71cf550d562e8df4
+ after
+ 0000000000000000.0000000000000000.04e24e45f494d0df.03056582b112b9be
+ 1df000f8d96244c8.afb49cadffbb3b2f.04e26450f4943a6d.04057273475de87f
+ b0979e15eac435b9.ac32ac9f4ff54900.77e44e453407d0df.03606582b112b9be
+ 8a81e493516b49ab.07d095477e819bd5.434321a5bd3aabbb.34b43211ad54b22b
+ 71cf550d562e8df4
+VPMINSB_128(mem)
+ before
+ 987b4a60c9ac0643.05facddeabe3be48.9e5ad190a96ceedc.c24bd9dc2ab808ad
+ 83858df721dbdb44.7f4d566293b9ce3d.4b9cde68ebc1fd3e.51477256180d2361
+ 10b99bbf7bc6c624.53c8798ca677b635.ec6137ba608c8629.4c85e88022c63782
+ 19e3efa2f27a840f.dcb534c67facb1dd.5b77597225da43c9.0f4f38c4e46e81bc
+ f6f25d8ffb923dbc
+ after
+ 987b4a60c9ac0643.05facddeabe3be48.9e5ad190a96ceedc.c24bd9dc2ab808ad
+ 83858df721dbdb44.7f4d566293b9ce3d.4b9cde68ebc1fd3e.51477256180d2361
+ 0000000000000000.0000000000000000.9e9cd190a9c1eedc.c247d9dc18b808ad
+ 19e3efa2f27a840f.dcb534c67facb1dd.5b77597225da43c9.0f4f38c4e46e81bc
+ f6f25d8ffb923dbc
+
+VPERM2F128_0x00(reg)
+ before
+ 5dba534e03bca72e.7bcf058ea302d030.7861827ebbe1fde0.75a8be7c56b6f04a
+ a0f3166c977bfabe.13495a6ea96a68b4.81185f1ef5a4d4eb.17c1e4c50e2d4bd7
+ 1be9a35453587317.bb1c682e21be06c6.5426c814ca8172aa.1b8e4637694a0e9d
+ 2ae8f474d4e14ee5.5015adba260b6693.4ed6b7cbd50215c8.5edb60bf8419f6c7
+ bc74ae4a7aa6bf82
+ after
+ 81185f1ef5a4d4eb.17c1e4c50e2d4bd7.81185f1ef5a4d4eb.17c1e4c50e2d4bd7
+ a0f3166c977bfabe.13495a6ea96a68b4.81185f1ef5a4d4eb.17c1e4c50e2d4bd7
+ 1be9a35453587317.bb1c682e21be06c6.5426c814ca8172aa.1b8e4637694a0e9d
+ 2ae8f474d4e14ee5.5015adba260b6693.4ed6b7cbd50215c8.5edb60bf8419f6c7
+ bc74ae4a7aa6bf82
+VPERM2F128_0x00(mem)
+ before
+ 1224adc268fe24f9.283b0737b5a1c7d5.ae00a4fed45c4647.c9762aafb3b5f7f2
+ 3ab9d815692ce259.732fd80993241993.b2a9c9e648be600d.23501c2cff2655d4
+ 11fdab2e9a3db5ce.6610615609f781ca.36dc995e9e3c7112.b6b189ae55df6b19
+ 73bda2f9163c5883.5d2aa08bb4a53b27.17658e52f1e23581.dfe56ea1526e746d
+ fa38c671925fad7e
+ after
+ 1224adc268fe24f9.283b0737b5a1c7d5.ae00a4fed45c4647.c9762aafb3b5f7f2
+ 3ab9d815692ce259.732fd80993241993.b2a9c9e648be600d.23501c2cff2655d4
+ b2a9c9e648be600d.23501c2cff2655d4.b2a9c9e648be600d.23501c2cff2655d4
+ 73bda2f9163c5883.5d2aa08bb4a53b27.17658e52f1e23581.dfe56ea1526e746d
+ fa38c671925fad7e
+
+VPERM2F128_0x00(reg)
+ before
+ 63f68d8bb03c52f5.3cc53a62fa3588a5.b3c98f122fbb8256.310f26af5dbd6787
+ 776bbf5948939e81.48e0ee556135015f.c6392c5817c49302.60a7dc5fffd7c450
+ 90e25849f7f0cecc.73dc3abe68477fde.f1c573ca074caad8.80f92d50f33f0807
+ 0ba855c558dd1e83.99839a892a77bd4e.8fba5ed39be00383.6dd1936d54feeed9
+ 03fb8ca13e2233f1
+ after
+ c6392c5817c49302.60a7dc5fffd7c450.c6392c5817c49302.60a7dc5fffd7c450
+ 776bbf5948939e81.48e0ee556135015f.c6392c5817c49302.60a7dc5fffd7c450
+ 90e25849f7f0cecc.73dc3abe68477fde.f1c573ca074caad8.80f92d50f33f0807
+ 0ba855c558dd1e83.99839a892a77bd4e.8fba5ed39be00383.6dd1936d54feeed9
+ 03fb8ca13e2233f1
+VPERM2F128_0x00(mem)
+ before
+ 1e4393daceb7937c.4409b13b08e8ca51.96a38aa3c3d278da.fe65ebde700bd9b0
+ 9a7424031fc7caa6.97516816a29d0de3.460687f650636caf.981015592259690a
+ 535cbc084e60939a.60cc76c2c38724e4.85790c70ed3655f8.bb08d8af4c56ef3f
+ 25c5d5d6768dac85.fbc6d7ab06324b01.2fc795fbb557eee2.c298304c8a8fa6f8
+ 080e1a9c7990cbe3
+ after
+ 1e4393daceb7937c.4409b13b08e8ca51.96a38aa3c3d278da.fe65ebde700bd9b0
+ 9a7424031fc7caa6.97516816a29d0de3.460687f650636caf.981015592259690a
+ 460687f650636caf.981015592259690a.460687f650636caf.981015592259690a
+ 25c5d5d6768dac85.fbc6d7ab06324b01.2fc795fbb557eee2.c298304c8a8fa6f8
+ 080e1a9c7990cbe3
+
+VPERM2F128_0x00(reg)
+ before
+ eab4910bb5e39aac.eb7ced57b35bce92.c48a883d082abee5.20be9e85c4d3f498
+ c5d79105d9164fff.834d7f7823d5b8ee.176584e464fcb83e.3329a3f937b62348
+ f3c316f781b42587.c8040826df0724c5.50a4c70cb63376b5.46d32143290a361b
+ d2c41c4b4a4a59f1.966c024b05fecf42.cb914d229c5c33f9.3489934fb7ddea40
+ d9177509fd3bfbe1
+ after
+ 176584e464fcb83e.3329a3f937b62348.176584e464fcb83e.3329a3f937b62348
+ c5d79105d9164fff.834d7f7823d5b8ee.176584e464fcb83e.3329a3f937b62348
+ f3c316f781b42587.c8040826df0724c5.50a4c70cb63376b5.46d32143290a361b
+ d2c41c4b4a4a59f1.966c024b05fecf42.cb914d229c5c33f9.3489934fb7ddea40
+ d9177509fd3bfbe1
+VPERM2F128_0x00(mem)
+ before
+ 1049435d152f242a.bc26a06fcf6327e8.c853ebd5b1c57592.e3781390af012db4
+ b7eb7a371ec52348.0e359dcdad8bca19.3c833eaffe69d1e0.f6a714c48db19e92
+ a9c895843109b267.243c0fd37f4f7f2f.cdc977c408f4a059.5f694c29d2f5c340
+ c1ad102e6c088db2.5b88f2ece23a82d7.56f11302ec749e28.7a09b72a195bd76a
+ a2d45135fe6e18bb
+ after
+ 1049435d152f242a.bc26a06fcf6327e8.c853ebd5b1c57592.e3781390af012db4
+ b7eb7a371ec52348.0e359dcdad8bca19.3c833eaffe69d1e0.f6a714c48db19e92
+ 3c833eaffe69d1e0.f6a714c48db19e92.3c833eaffe69d1e0.f6a714c48db19e92
+ c1ad102e6c088db2.5b88f2ece23a82d7.56f11302ec749e28.7a09b72a195bd76a
+ a2d45135fe6e18bb
+
+VPERM2F128_0xFF(reg)
+ before
+ 351617b51ebbc0e0.dd676723ebcd7256.0d66438471d90fbd.b5c78c54c6f5877a
+ 8e1b041614cd0b85.d7c0164dc9641b7f.9720fd07c8b6618c.c41660a6b181167b
+ 082f14c47d303755.8d859a9a23da4558.55021ce1855fb5f1.61ac0ae5c9270856
+ 019d432cf4707efd.d9816ef5143aab0d.a35a9c7e41604797.665306fb2bf01938
+ b1d8d1d5f2ea044d
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 8e1b041614cd0b85.d7c0164dc9641b7f.9720fd07c8b6618c.c41660a6b181167b
+ 082f14c47d303755.8d859a9a23da4558.55021ce1855fb5f1.61ac0ae5c9270856
+ 019d432cf4707efd.d9816ef5143aab0d.a35a9c7e41604797.665306fb2bf01938
+ b1d8d1d5f2ea044d
+VPERM2F128_0xFF(mem)
+ before
+ 1c07e6603b2086c0.d3b38eb8161a1d28.99820e4ab8910bcc.dd73794a9a43522b
+ 85acc086219e5bbd.dcbbf0d57eba4f83.a752f6852ce91fbf.5f98b0b22c971459
+ c693de35c1713f72.760265f0c9da51b9.e0bfa3928c51a312.85163c2092e5c7cc
+ bc88b95836a4ed09.ffd4e97492085f77.2193905df3d255f2.ab39190268bba731
+ 2d4d43c34ba4f233
+ after
+ 1c07e6603b2086c0.d3b38eb8161a1d28.99820e4ab8910bcc.dd73794a9a43522b
+ 85acc086219e5bbd.dcbbf0d57eba4f83.a752f6852ce91fbf.5f98b0b22c971459
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ bc88b95836a4ed09.ffd4e97492085f77.2193905df3d255f2.ab39190268bba731
+ 2d4d43c34ba4f233
+
+VPERM2F128_0xFF(reg)
+ before
+ 679eb7ced62ce27f.4356cfdb9c4422ae.d17d78cc76cfb569.449b39d27d7aef8b
+ b5777091a6e0b4c1.38ca9aaa115c9a8e.4a490f6610bc8f3a.26a31ade47542e08
+ 73266a77564ba3a4.75b098b1aef810d5.c483a9adfd5a2897.a376af6b6c6dce96
+ fcf5a1ec83faecd5.d7d445dc912442ae.9c79420dd835bd2c.98e2756709cf8a60
+ dfb1e7bd39891f93
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ b5777091a6e0b4c1.38ca9aaa115c9a8e.4a490f6610bc8f3a.26a31ade47542e08
+ 73266a77564ba3a4.75b098b1aef810d5.c483a9adfd5a2897.a376af6b6c6dce96
+ fcf5a1ec83faecd5.d7d445dc912442ae.9c79420dd835bd2c.98e2756709cf8a60
+ dfb1e7bd39891f93
+VPERM2F128_0xFF(mem)
+ before
+ 55b0815819a4495b.ae31115cc978cbff.3a021b17d6ede946.2f75d6f23dda89a4
+ d6abbf26c42ec3e3.e426b734c2517ccf.7a06984e985fc4c8.d7c462c8c9d4caab
+ 3e6e1e1257324a58.fa208ede0c113af0.73ab376ef3848d61.f1b2e0fc18afbaef
+ 69c51808edbd9ae5.4b6a92c74345420f.02be7461046a013d.d98a4ef8c4f89519
+ eb9aa7296c3a99d8
+ after
+ 55b0815819a4495b.ae31115cc978cbff.3a021b17d6ede946.2f75d6f23dda89a4
+ d6abbf26c42ec3e3.e426b734c2517ccf.7a06984e985fc4c8.d7c462c8c9d4caab
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 69c51808edbd9ae5.4b6a92c74345420f.02be7461046a013d.d98a4ef8c4f89519
+ eb9aa7296c3a99d8
+
+VPERM2F128_0xFF(reg)
+ before
+ 842ce8fcaa0200d6.337b2bf5a3da6fb7.3552bf5c0278d0d8.010bcb15e61cdc87
+ fe8d0bdc1ada07bf.785ed3c3949584fa.13221107e63720f6.4d5eb975b6a7da6c
+ b60a0e345950ea41.14388a5fdcfb96d9.402785368a0d6d16.c283b86c9016b617
+ 08edec7202f0e405.e3d6ceb698176181.1aad16548a86f4e4.3c4646e88e752db5
+ 9672dfd4cfd1fb72
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ fe8d0bdc1ada07bf.785ed3c3949584fa.13221107e63720f6.4d5eb975b6a7da6c
+ b60a0e345950ea41.14388a5fdcfb96d9.402785368a0d6d16.c283b86c9016b617
+ 08edec7202f0e405.e3d6ceb698176181.1aad16548a86f4e4.3c4646e88e752db5
+ 9672dfd4cfd1fb72
+VPERM2F128_0xFF(mem)
+ before
+ aed5fd1c6c35db79.5082a101b24532ba.c10419b2e4f5a11d.fb00c0cd832ff10b
+ 5f391ead83ad8af7.ea172a4d04db100a.8a8ee941dba211da.416c7f0d11939f38
+ 856bbd713046c417.32f682c2953eb9a1.1a40ba4d99296ee4.463d5080cf3e3b16
+ fc3756558e0b4406.846da4cc00fb6b2d.4ce506c43b967466.68be2e9259bd0152
+ 013c15af4c9b2d97
+ after
+ aed5fd1c6c35db79.5082a101b24532ba.c10419b2e4f5a11d.fb00c0cd832ff10b
+ 5f391ead83ad8af7.ea172a4d04db100a.8a8ee941dba211da.416c7f0d11939f38
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ fc3756558e0b4406.846da4cc00fb6b2d.4ce506c43b967466.68be2e9259bd0152
+ 013c15af4c9b2d97
+
+VPERM2F128_0x30(reg)
+ before
+ 6e0301444364fa92.9f696546ba08c8ef.3cc68fd8e19d6057.fe4a4b91ddf6de8d
+ 0c5fefbbdba5a5ef.4ccc672ecf4a0a00.b54e3c50d5b1d4ce.0b3c04a099546984
+ 359cd982afe96a59.de2ed6fbe9dcc662.4d51a9a278c1053c.4f85addd8ebcd178
+ 4605bd035cbc847d.3159309825caba44.5f1ad038655c2d4d.a5f1c234d63bd194
+ eb4ec0928ddc2705
+ after
+ 359cd982afe96a59.de2ed6fbe9dcc662.b54e3c50d5b1d4ce.0b3c04a099546984
+ 0c5fefbbdba5a5ef.4ccc672ecf4a0a00.b54e3c50d5b1d4ce.0b3c04a099546984
+ 359cd982afe96a59.de2ed6fbe9dcc662.4d51a9a278c1053c.4f85addd8ebcd178
+ 4605bd035cbc847d.3159309825caba44.5f1ad038655c2d4d.a5f1c234d63bd194
+ eb4ec0928ddc2705
+VPERM2F128_0x30(mem)
+ before
+ fc6722e1cfab8df7.9ce896ac7dab3107.201af0f09f21a0cf.47f7af80390b89ae
+ b307640fbab5bf95.918f61e8af41aaa2.893d93f172ec3532.613242e58e5c540b
+ eefb020667057b0c.824718238d0a2efa.468e9386ba373497.081883d303dacb0f
+ 870f78b4f4a77b88.cb5cb9c9b493f7bc.35d86e9b940f5b2b.9af570b632122a67
+ 721504fab78fadbf
+ after
+ fc6722e1cfab8df7.9ce896ac7dab3107.201af0f09f21a0cf.47f7af80390b89ae
+ b307640fbab5bf95.918f61e8af41aaa2.893d93f172ec3532.613242e58e5c540b
+ fc6722e1cfab8df7.9ce896ac7dab3107.893d93f172ec3532.613242e58e5c540b
+ 870f78b4f4a77b88.cb5cb9c9b493f7bc.35d86e9b940f5b2b.9af570b632122a67
+ 721504fab78fadbf
+
+VPERM2F128_0x30(reg)
+ before
+ ebc43b0b2fdd8fc2.5c0f43047da87c34.c81a3f46bf674294.30e99f1d1c7f6419
+ 634e115535880e1d.47c7dee11d13393d.d5cda6064b124b2e.158ba3f66c940b8e
+ 34fe8244661d637b.2602c539f1f570ce.4ec0eb75f3214e35.be8bf413a3580eb5
+ bc218b455d28cd89.d38e74f71459db14.8f410800531f8655.09b51061dada27bc
+ d0d572ca302313cc
+ after
+ 34fe8244661d637b.2602c539f1f570ce.d5cda6064b124b2e.158ba3f66c940b8e
+ 634e115535880e1d.47c7dee11d13393d.d5cda6064b124b2e.158ba3f66c940b8e
+ 34fe8244661d637b.2602c539f1f570ce.4ec0eb75f3214e35.be8bf413a3580eb5
+ bc218b455d28cd89.d38e74f71459db14.8f410800531f8655.09b51061dada27bc
+ d0d572ca302313cc
+VPERM2F128_0x30(mem)
+ before
+ f0b7963cbe418d13.550427c2b73386f2.2b356808a24b363a.f49afb110898303b
+ 4627f8a2a23f53bd.5df052290fcccb63.0bc41c56b8d73f6d.d918bf16ad198893
+ acf015e8f82a1ff6.2e3409e5027ed888.4d070cce710ab0d9.9a075079df2dc909
+ ffdf68fadb0cade9.251b46612bd6e80c.cecab45ceaef46a9.93b3aba83a613048
+ 2067cb0e5940f9fc
+ after
+ f0b7963cbe418d13.550427c2b73386f2.2b356808a24b363a.f49afb110898303b
+ 4627f8a2a23f53bd.5df052290fcccb63.0bc41c56b8d73f6d.d918bf16ad198893
+ f0b7963cbe418d13.550427c2b73386f2.0bc41c56b8d73f6d.d918bf16ad198893
+ ffdf68fadb0cade9.251b46612bd6e80c.cecab45ceaef46a9.93b3aba83a613048
+ 2067cb0e5940f9fc
+
+VPERM2F128_0x30(reg)
+ before
+ 9d71ac17d8565fd2.1bc06dc468f4bbc2.9ff0070b265f399c.6bd990ed3f93bd0a
+ 661b4a2f542fa076.dd5fa032baeb03af.f601474e91a504e4.feff1d6c8a01d027
+ d7b2a1c26858f693.1f887d30edff42d9.879803960535888f.640ad6c4ea453c2d
+ 4b82ae3cb15c9dd6.be0781aa1e3b346f.af023550209aff49.79c437e3786bbd48
+ 19fabcb453800ea3
+ after
+ d7b2a1c26858f693.1f887d30edff42d9.f601474e91a504e4.feff1d6c8a01d027
+ 661b4a2f542fa076.dd5fa032baeb03af.f601474e91a504e4.feff1d6c8a01d027
+ d7b2a1c26858f693.1f887d30edff42d9.879803960535888f.640ad6c4ea453c2d
+ 4b82ae3cb15c9dd6.be0781aa1e3b346f.af023550209aff49.79c437e3786bbd48
+ 19fabcb453800ea3
+VPERM2F128_0x30(mem)
+ before
+ 2078e223948fec6b.20d76c0acac8d3eb.96a7278d69ac949b.c88bdbe67d60a6c0
+ 6a09231c59a513cb.b1fcd7965027d27d.8335ebc3e95d1f89.2f7ff0c5b914b99d
+ d37bfd8bbecd3ff0.593feb4ede05d739.617d4a3aba5a9167.4029705a7041748f
+ 3798eb5cde132b06.76eaa49c10ee1dca.0c4bbeddf9b0a55e.57d7570f3d731240
+ d1d3a252bc37d05c
+ after
+ 2078e223948fec6b.20d76c0acac8d3eb.96a7278d69ac949b.c88bdbe67d60a6c0
+ 6a09231c59a513cb.b1fcd7965027d27d.8335ebc3e95d1f89.2f7ff0c5b914b99d
+ 2078e223948fec6b.20d76c0acac8d3eb.8335ebc3e95d1f89.2f7ff0c5b914b99d
+ 3798eb5cde132b06.76eaa49c10ee1dca.0c4bbeddf9b0a55e.57d7570f3d731240
+ d1d3a252bc37d05c
+
+VPERM2F128_0x21(reg)
+ before
+ 086a4c8e8a18e991.722e6a7cd6849438.634affee836fe1dd.606bc598c16a189d
+ 59e8512f42a39b88.6007f4d5c12b36b3.7babf7afd3145f1d.39a9da562f94a64e
+ 2099ada0816220f0.ddf00755bb14cda2.1c59884b9b67d337.73d079055e3a0b9d
+ b9c85c4fe2e4b573.c5b41ee6e14c1432.a0a0af2e77f678d7.eaae1e906b6902b8
+ 7a0d46e4712d49c8
+ after
+ 1c59884b9b67d337.73d079055e3a0b9d.59e8512f42a39b88.6007f4d5c12b36b3
+ 59e8512f42a39b88.6007f4d5c12b36b3.7babf7afd3145f1d.39a9da562f94a64e
+ 2099ada0816220f0.ddf00755bb14cda2.1c59884b9b67d337.73d079055e3a0b9d
+ b9c85c4fe2e4b573.c5b41ee6e14c1432.a0a0af2e77f678d7.eaae1e906b6902b8
+ 7a0d46e4712d49c8
+VPERM2F128_0x21(mem)
+ before
+ ffba6ceb8d9099fc.80c35ba802b295bd.f421b6764fdec88f.65cb66c4044c8ca8
+ 54810c92daa0b17e.d0d4a5157c5afd7c.460249f01fd6a5e4.c528ab79def64957
+ 572ea2c675694b7a.07483603ec672959.962255407041665e.1d0179b99f7feb90
+ e38cab7179f5241d.806b0bdfef655503.c24e55525c2ac828.caa3ccf0e673affe
+ 265aa18b4d5fd14d
+ after
+ ffba6ceb8d9099fc.80c35ba802b295bd.f421b6764fdec88f.65cb66c4044c8ca8
+ 54810c92daa0b17e.d0d4a5157c5afd7c.460249f01fd6a5e4.c528ab79def64957
+ f421b6764fdec88f.65cb66c4044c8ca8.54810c92daa0b17e.d0d4a5157c5afd7c
+ e38cab7179f5241d.806b0bdfef655503.c24e55525c2ac828.caa3ccf0e673affe
+ 265aa18b4d5fd14d
+
+VPERM2F128_0x21(reg)
+ before
+ 8e72f2f470ce8d2b.d369a2810252f893.97891e1321e1bc24.a552c512ff9d876f
+ 5f36bd99ec4c1f42.058f03e12d8c8207.a8ee6d0d1d669b68.1afa216c76a75e5f
+ f3f4fde55c66c23e.54cb4a7d16ae7fa6.0fe5f3377f812e7c.ff12e64cdc530b23
+ a7f6af445da7b3cc.9be9f340d8c4ab9c.27bbacffe4bdb10c.2f658f9f4ead48e7
+ 85c0984fe7c2d1d9
+ after
+ 0fe5f3377f812e7c.ff12e64cdc530b23.5f36bd99ec4c1f42.058f03e12d8c8207
+ 5f36bd99ec4c1f42.058f03e12d8c8207.a8ee6d0d1d669b68.1afa216c76a75e5f
+ f3f4fde55c66c23e.54cb4a7d16ae7fa6.0fe5f3377f812e7c.ff12e64cdc530b23
+ a7f6af445da7b3cc.9be9f340d8c4ab9c.27bbacffe4bdb10c.2f658f9f4ead48e7
+ 85c0984fe7c2d1d9
+VPERM2F128_0x21(mem)
+ before
+ dff07d4ac39d6423.d789cd228a9b2d98.b8b57b188fdac214.4ebd95d0e8a65fc3
+ 17bfba7a004bbbf1.dff955eb7fcf6e4d.85fa5df158fd7f3b.df35a81626c9754e
+ 0bfacccdb7d69370.1c92420bd9ceb098.e08615b54e389f3c.3570e33d3ab02f59
+ 956c2e2e064ca7cc.e8a090ee34252f24.a3231f518e97de44.aeb941b1c1eac88f
+ a45ebfde56007d9d
+ after
+ dff07d4ac39d6423.d789cd228a9b2d98.b8b57b188fdac214.4ebd95d0e8a65fc3
+ 17bfba7a004bbbf1.dff955eb7fcf6e4d.85fa5df158fd7f3b.df35a81626c9754e
+ b8b57b188fdac214.4ebd95d0e8a65fc3.17bfba7a004bbbf1.dff955eb7fcf6e4d
+ 956c2e2e064ca7cc.e8a090ee34252f24.a3231f518e97de44.aeb941b1c1eac88f
+ a45ebfde56007d9d
+
+VPERM2F128_0x21(reg)
+ before
+ 75a9573196808a2e.93e35c8909b9b530.a06e3c002b5e299e.ac9ef8b13327f77e
+ 7ce807141cf52bef.df29d2cadb2877c9.a04940ae5b07d8b2.d5c31ac25af3a717
+ 1465caf585ec9b8b.560c0ddd98a5a9c2.447e9a625eac790b.fc5e036f1e08aa3b
+ 9a6d9c3e6cf017af.d55687ae5d3c0948.e857458ad3d84856.fb3b2ea39c71bc15
+ af26184cef3a98d2
+ after
+ 447e9a625eac790b.fc5e036f1e08aa3b.7ce807141cf52bef.df29d2cadb2877c9
+ 7ce807141cf52bef.df29d2cadb2877c9.a04940ae5b07d8b2.d5c31ac25af3a717
+ 1465caf585ec9b8b.560c0ddd98a5a9c2.447e9a625eac790b.fc5e036f1e08aa3b
+ 9a6d9c3e6cf017af.d55687ae5d3c0948.e857458ad3d84856.fb3b2ea39c71bc15
+ af26184cef3a98d2
+VPERM2F128_0x21(mem)
+ before
+ f5ea3b55346ffb9d.6b4c795d6e8ddb07.36d4be2a46fa5187.e8213e905417803e
+ a75415aa861da1a3.e14d5ebd2650223e.56522e3b6dea3eaa.a0277fe27df55e70
+ a2302137014f4510.5abe46ca30c42901.129b51cff1198cde.6bb706ebebff1e98
+ c24adbe8c212a50f.30e92df029752cfc.447da5d0ec92f64f.a71bce1739c0fc61
+ afa1d3d204c53377
+ after
+ f5ea3b55346ffb9d.6b4c795d6e8ddb07.36d4be2a46fa5187.e8213e905417803e
+ a75415aa861da1a3.e14d5ebd2650223e.56522e3b6dea3eaa.a0277fe27df55e70
+ 36d4be2a46fa5187.e8213e905417803e.a75415aa861da1a3.e14d5ebd2650223e
+ c24adbe8c212a50f.30e92df029752cfc.447da5d0ec92f64f.a71bce1739c0fc61
+ afa1d3d204c53377
+
+VPERM2F128_0x12(reg)
+ before
+ df931188e7980088.e36ec0a9e5717acd.c01b0f9badf067da.c9c2a52c7a613928
+ 933e85a57fc89e3e.e2684b6785788376.66a0e93757c01547.7d37cdceb8921195
+ 26ed2a9667de4b45.9903f70cbe337a35.7fc4b530c37173f1.3ca899a2c13239c3
+ f6eefcc53c68414a.e50c4386adaf1c36.65d371f38e90bd81.e2e18593b14d6ede
+ 4bae0e90a6ed6c12
+ after
+ 933e85a57fc89e3e.e2684b6785788376.7fc4b530c37173f1.3ca899a2c13239c3
+ 933e85a57fc89e3e.e2684b6785788376.66a0e93757c01547.7d37cdceb8921195
+ 26ed2a9667de4b45.9903f70cbe337a35.7fc4b530c37173f1.3ca899a2c13239c3
+ f6eefcc53c68414a.e50c4386adaf1c36.65d371f38e90bd81.e2e18593b14d6ede
+ 4bae0e90a6ed6c12
+VPERM2F128_0x12(mem)
+ before
+ 53dbaf82b920ef8a.5e8bf79f99f1bdf9.a250a8bf6ef825a6.751819ea54a82ea6
+ d633e45608f1b272.b91218911b06fafd.ac98a3a51c1851b1.0be1a783b045040a
+ b0832af8af6d72f7.65cd59065d323603.dfb3b123d31d5b83.837819283ef47959
+ bd97fb55c99feb45.bc09b86afb01abb7.176c4d25b0120047.392a69479b40c941
+ 8943954b62b6316b
+ after
+ 53dbaf82b920ef8a.5e8bf79f99f1bdf9.a250a8bf6ef825a6.751819ea54a82ea6
+ d633e45608f1b272.b91218911b06fafd.ac98a3a51c1851b1.0be1a783b045040a
+ d633e45608f1b272.b91218911b06fafd.a250a8bf6ef825a6.751819ea54a82ea6
+ bd97fb55c99feb45.bc09b86afb01abb7.176c4d25b0120047.392a69479b40c941
+ 8943954b62b6316b
+
+VPERM2F128_0x12(reg)
+ before
+ cf0f99a030e0ee86.d93bd5577293d988.1c123028920095c4.308ff397ce04fc29
+ 67d96fb2a04c393c.e03b33ecc756f7eb.df34beaebeba32d7.05e720654afe0a56
+ adef15ed4f865139.ae6391ffe4f3029a.63ba5c671abbbc9b.74414f7b3f0ce7fa
+ fd9b86bdd819702b.1f7e6c7be476b6c2.02f108c0428f70bd.5869fbc5c93b4f40
+ 8d2ba22f0696fd55
+ after
+ 67d96fb2a04c393c.e03b33ecc756f7eb.63ba5c671abbbc9b.74414f7b3f0ce7fa
+ 67d96fb2a04c393c.e03b33ecc756f7eb.df34beaebeba32d7.05e720654afe0a56
+ adef15ed4f865139.ae6391ffe4f3029a.63ba5c671abbbc9b.74414f7b3f0ce7fa
+ fd9b86bdd819702b.1f7e6c7be476b6c2.02f108c0428f70bd.5869fbc5c93b4f40
+ 8d2ba22f0696fd55
+VPERM2F128_0x12(mem)
+ before
+ ef53c0a60f29af65.b32abe8ed791d3bb.0e593f4ee3ecce8f.1a26bd23d3c389e8
+ 59accf1402011f9b.2be8b9cde97ab698.59c18663fe60072c.05a377fd68e345c9
+ a9044d67fb290924.c12174e4aa61546c.db80bda650de1dc6.20b533bb9e79de0c
+ ba25b58a15ad2b2b.d121ea41b5d1eae3.6f626004f673cb89.c8a7ebc71013905c
+ 57c79d8f5b3d9966
+ after
+ ef53c0a60f29af65.b32abe8ed791d3bb.0e593f4ee3ecce8f.1a26bd23d3c389e8
+ 59accf1402011f9b.2be8b9cde97ab698.59c18663fe60072c.05a377fd68e345c9
+ 59accf1402011f9b.2be8b9cde97ab698.0e593f4ee3ecce8f.1a26bd23d3c389e8
+ ba25b58a15ad2b2b.d121ea41b5d1eae3.6f626004f673cb89.c8a7ebc71013905c
+ 57c79d8f5b3d9966
+
+VPERM2F128_0x12(reg)
+ before
+ 2a5f457e1a8133d5.67dc83696c9a3fdd.b633174fa657b4aa.f335ec670b2acfa0
+ 9dbdddffea6d9b56.8ef534f01dfb0265.cea5f7791a7eee6d.42c4dbbcac0fe338
+ 0d2b6280668d0d95.093c420b44dd2ff1.74c1862dadd2d3d7.37daabf0f42fc37c
+ d4f6d16c2b6bc43d.b67d2ba6fc4a83aa.03d4c1d6fadfa095.b044d8ed00952d99
+ 87cedca1eb4edbba
+ after
+ 9dbdddffea6d9b56.8ef534f01dfb0265.74c1862dadd2d3d7.37daabf0f42fc37c
+ 9dbdddffea6d9b56.8ef534f01dfb0265.cea5f7791a7eee6d.42c4dbbcac0fe338
+ 0d2b6280668d0d95.093c420b44dd2ff1.74c1862dadd2d3d7.37daabf0f42fc37c
+ d4f6d16c2b6bc43d.b67d2ba6fc4a83aa.03d4c1d6fadfa095.b044d8ed00952d99
+ 87cedca1eb4edbba
+VPERM2F128_0x12(mem)
+ before
+ 9a4435f7d1648a0c.4f6a252fd496fdfb.6f836aad6151babf.d92aa3e09d329053
+ c3725edbcfe6f5bb.dad25a36fd97f47b.121b7b0c90fb9059.510f28b73357e1bc
+ e024d33901dddaf2.d17c6deb43fce468.7912dbb0a456c1a7.c6ce4cc857d8cd7d
+ cb2510fd8257f3de.90b258bb42500a6e.82320583ba6d08d3.96b50c7da6439141
+ 1b0e6243bb2368b5
+ after
+ 9a4435f7d1648a0c.4f6a252fd496fdfb.6f836aad6151babf.d92aa3e09d329053
+ c3725edbcfe6f5bb.dad25a36fd97f47b.121b7b0c90fb9059.510f28b73357e1bc
+ c3725edbcfe6f5bb.dad25a36fd97f47b.6f836aad6151babf.d92aa3e09d329053
+ cb2510fd8257f3de.90b258bb42500a6e.82320583ba6d08d3.96b50c7da6439141
+ 1b0e6243bb2368b5
+
+VPERM2F128_0x03(reg)
+ before
+ b3264c8733059084.614292136e5ffcab.73c11913951fa23a.07477573ed4c220a
+ b849c6b4a974435b.7f47d367e201b384.d6f5ab5dd8f6e878.e61fa76a5a00ca77
+ 88c3ca35bafcbde6.ff0051e5fa4ad295.159a0b07a86017d3.f98517561c94be47
+ 7ddf5678012a3cd0.be39887ad145160c.8cfc337ca1ea6cf8.1d4442224f15b8a5
+ 2e29a2ba118e74be
+ after
+ d6f5ab5dd8f6e878.e61fa76a5a00ca77.88c3ca35bafcbde6.ff0051e5fa4ad295
+ b849c6b4a974435b.7f47d367e201b384.d6f5ab5dd8f6e878.e61fa76a5a00ca77
+ 88c3ca35bafcbde6.ff0051e5fa4ad295.159a0b07a86017d3.f98517561c94be47
+ 7ddf5678012a3cd0.be39887ad145160c.8cfc337ca1ea6cf8.1d4442224f15b8a5
+ 2e29a2ba118e74be
+VPERM2F128_0x03(mem)
+ before
+ 0900b50a7b0bb0be.f4eb64e81a89fac6.99bef21083ff3b12.976721285d1e2393
+ 8895f7feab9826d0.4a31f3f1a2a53474.6a5a0d952d83fcd6.9226d0777b8b784f
+ 88b4e282bd429321.d9fffcff350b2685.0edb53f3eadd1682.d8863cd595baa6d9
+ e529f483cc15b3dc.fe9f7c7e6e460ba5.610b4318d71a4542.c7d361ae4739eadc
+ ba593c6e2e938005
+ after
+ 0900b50a7b0bb0be.f4eb64e81a89fac6.99bef21083ff3b12.976721285d1e2393
+ 8895f7feab9826d0.4a31f3f1a2a53474.6a5a0d952d83fcd6.9226d0777b8b784f
+ 6a5a0d952d83fcd6.9226d0777b8b784f.0900b50a7b0bb0be.f4eb64e81a89fac6
+ e529f483cc15b3dc.fe9f7c7e6e460ba5.610b4318d71a4542.c7d361ae4739eadc
+ ba593c6e2e938005
+
+VPERM2F128_0x03(reg)
+ before
+ 0d64c881e555a300.7bbfa8ebf41b412e.165d70dbe9e22082.3fb756ef0f454444
+ 1b40015408099078.26437aa85262fa43.7b87d380436ca1c5.84ab0964af6ad0b2
+ 4238e351343e831a.c282e6a401f59a46.8a68a1da186fc91d.0cb2d963d295a5b8
+ dd9a6be6057db891.2b4669cd1ee1dc64.9f4bd7560277d534.b39a41d894d37f83
+ 552dbdb01230193e
+ after
+ 7b87d380436ca1c5.84ab0964af6ad0b2.4238e351343e831a.c282e6a401f59a46
+ 1b40015408099078.26437aa85262fa43.7b87d380436ca1c5.84ab0964af6ad0b2
+ 4238e351343e831a.c282e6a401f59a46.8a68a1da186fc91d.0cb2d963d295a5b8
+ dd9a6be6057db891.2b4669cd1ee1dc64.9f4bd7560277d534.b39a41d894d37f83
+ 552dbdb01230193e
+VPERM2F128_0x03(mem)
+ before
+ ce39cad568b63017.47b0937e16546a8a.3d5b7e0ec5317dc8.167d6f5fa01101b6
+ fa88e234b1738037.dec75984044ed6b0.d48fa15310f1399f.4b4a67608cc88951
+ b5e783ba0a72c5cd.fc2bb8666af838b0.ccad4e881e2ecc15.9afebac76229a8ae
+ db2228518dc0ba03.ff27ad8fe4ddcb36.0180019908f3f155.5fe564ffbfbe9b7c
+ f64b62743e159e65
+ after
+ ce39cad568b63017.47b0937e16546a8a.3d5b7e0ec5317dc8.167d6f5fa01101b6
+ fa88e234b1738037.dec75984044ed6b0.d48fa15310f1399f.4b4a67608cc88951
+ d48fa15310f1399f.4b4a67608cc88951.ce39cad568b63017.47b0937e16546a8a
+ db2228518dc0ba03.ff27ad8fe4ddcb36.0180019908f3f155.5fe564ffbfbe9b7c
+ f64b62743e159e65
+
+VPERM2F128_0x03(reg)
+ before
+ bb7bae927bbaed15.48044de759681c05.4109326b0f89cced.4fd53772ed4c668c
+ 0ac246c51438c339.d85b6f678876a700.201b456686897782.92786bffe646e4e5
+ 3f6d257aa21b5d7d.66f108bd36f71620.f6aae1ede66808a1.a535192c11ec2a8d
+ b6c6481bc3eff68d.d09396d580f62691.2003026acbb2baf5.66d8bde68a4af2b0
+ b02cd4176c6df979
+ after
+ 201b456686897782.92786bffe646e4e5.3f6d257aa21b5d7d.66f108bd36f71620
+ 0ac246c51438c339.d85b6f678876a700.201b456686897782.92786bffe646e4e5
+ 3f6d257aa21b5d7d.66f108bd36f71620.f6aae1ede66808a1.a535192c11ec2a8d
+ b6c6481bc3eff68d.d09396d580f62691.2003026acbb2baf5.66d8bde68a4af2b0
+ b02cd4176c6df979
+VPERM2F128_0x03(mem)
+ before
+ 5fffd8add460fb14.cb19a9161341cc14.f10d959b817f937d.fb6fa54bd0f4ca2a
+ 4e1b4793dd2fb3af.d9b446d52d9c19be.a52b7ffb569f1813.e13dc5fa91b974ee
+ 5b4d9db5a3e7de74.3ee21ac6ad8d1a38.c7b9d1e21a61737d.2fb85ee5ab8df3ea
+ 606154ff4393388f.55ee2154309f0a2e.3582083aead25ee8.422b6c76b9fd84cd
+ 74e4eb1b57946341
+ after
+ 5fffd8add460fb14.cb19a9161341cc14.f10d959b817f937d.fb6fa54bd0f4ca2a
+ 4e1b4793dd2fb3af.d9b446d52d9c19be.a52b7ffb569f1813.e13dc5fa91b974ee
+ a52b7ffb569f1813.e13dc5fa91b974ee.5fffd8add460fb14.cb19a9161341cc14
+ 606154ff4393388f.55ee2154309f0a2e.3582083aead25ee8.422b6c76b9fd84cd
+ 74e4eb1b57946341
+
+VPERM2F128_0x85(reg)
+ before
+ 222dd83f23deccf3.3b23ea5dd83f7d2d.7a2558eb525e274b.c9549ff0e1fc957f
+ a8532d4eb668fa8e.c75fd9bb7ff8687a.08d3b9f7ae56ab3c.61f912f11cedd66f
+ 62a1e8b4aebd2abf.dfe09f0554c9b6a1.5d4442e4e014d2ad.d73ede28b6b1dbe3
+ ac6504dda7699831.6173b82771bf23cf.d4c4ee1e8523da49.09ef7e80cc536109
+ d1d76de779df230a
+ after
+ 0000000000000000.0000000000000000.a8532d4eb668fa8e.c75fd9bb7ff8687a
+ a8532d4eb668fa8e.c75fd9bb7ff8687a.08d3b9f7ae56ab3c.61f912f11cedd66f
+ 62a1e8b4aebd2abf.dfe09f0554c9b6a1.5d4442e4e014d2ad.d73ede28b6b1dbe3
+ ac6504dda7699831.6173b82771bf23cf.d4c4ee1e8523da49.09ef7e80cc536109
+ d1d76de779df230a
+VPERM2F128_0x85(mem)
+ before
+ 0dc42a48d961df15.e2ea7e363cf97f91.27e59e0ef5e46a30.c89fba113810fdbd
+ 97802e8f09e64f53.607b512909f81d8b.0e00cfa4f94748ef.9720a029966678b4
+ 4dd9f6a825792ff3.82657824abf3acca.f390c6d79cf17938.9b949ed33ab186db
+ 0999ff8048273d1f.a4f4f191be7468fb.b063ff91f7f0b939.3247af79c17e64dd
+ b685cf89c6584e67
+ after
+ 0dc42a48d961df15.e2ea7e363cf97f91.27e59e0ef5e46a30.c89fba113810fdbd
+ 97802e8f09e64f53.607b512909f81d8b.0e00cfa4f94748ef.9720a029966678b4
+ 0000000000000000.0000000000000000.97802e8f09e64f53.607b512909f81d8b
+ 0999ff8048273d1f.a4f4f191be7468fb.b063ff91f7f0b939.3247af79c17e64dd
+ b685cf89c6584e67
+
+VPERM2F128_0x85(reg)
+ before
+ 849afb6ee6cb8025.a88dc4018efa3304.2274b8dedd098fc9.2244f6c0294fc31b
+ f9d22d93bc6436c2.0681c1181401cecd.5831c776a43e5be1.26fe284f4b1b540d
+ 6f786366e4aeabeb.004073b2f545caa7.a2761cc5b09e09ee.965e102a7b5e2839
+ 44da9852fb351c4c.709854b94ed4e2bd.5c91b2369cb5d49e.4f302a3dd527facc
+ 2d40f274747f88f1
+ after
+ 0000000000000000.0000000000000000.f9d22d93bc6436c2.0681c1181401cecd
+ f9d22d93bc6436c2.0681c1181401cecd.5831c776a43e5be1.26fe284f4b1b540d
+ 6f786366e4aeabeb.004073b2f545caa7.a2761cc5b09e09ee.965e102a7b5e2839
+ 44da9852fb351c4c.709854b94ed4e2bd.5c91b2369cb5d49e.4f302a3dd527facc
+ 2d40f274747f88f1
+VPERM2F128_0x85(mem)
+ before
+ 0c5ae5bb74748bd5.d242c8c39d86c490.3353e21b3ab9d33c.e2cc8537050ff99a
+ c94a7dfff211c2a3.76fdf026652ce163.253e98c3d6015950.8f7492348639b491
+ 3edb382a0a63e788.8c570be5efb3ad72.2225f39d3db72f24.c1d5d397bcbe412d
+ 48da912ad775b7b0.719b156dd8a86469.06d46d958ce712e5.d33b46cd422bdb1a
+ 21f2e643b50bbf05
+ after
+ 0c5ae5bb74748bd5.d242c8c39d86c490.3353e21b3ab9d33c.e2cc8537050ff99a
+ c94a7dfff211c2a3.76fdf026652ce163.253e98c3d6015950.8f7492348639b491
+ 0000000000000000.0000000000000000.c94a7dfff211c2a3.76fdf026652ce163
+ 48da912ad775b7b0.719b156dd8a86469.06d46d958ce712e5.d33b46cd422bdb1a
+ 21f2e643b50bbf05
+
+VPERM2F128_0x85(reg)
+ before
+ 0645af63b0ea299a.c31405e97553ee46.7f170a2bbc9644f4.ad178497de9dbebe
+ e0819e9bd0555584.8b530e55010a4877.1315e689350987be.f3bab38f50e6efdc
+ 09f3ae55b0d77e70.7c632a5996a4806e.89e3a6f5e28e6a73.b4887669fdce606b
+ dfe5daffecfce10a.7212d4e151305358.3dcb45da5db029c1.cc4e4911015fce96
+ 17d8a97479a7f58a
+ after
+ 0000000000000000.0000000000000000.e0819e9bd0555584.8b530e55010a4877
+ e0819e9bd0555584.8b530e55010a4877.1315e689350987be.f3bab38f50e6efdc
+ 09f3ae55b0d77e70.7c632a5996a4806e.89e3a6f5e28e6a73.b4887669fdce606b
+ dfe5daffecfce10a.7212d4e151305358.3dcb45da5db029c1.cc4e4911015fce96
+ 17d8a97479a7f58a
+VPERM2F128_0x85(mem)
+ before
+ 71f2117c81b29172.bda321042150bafd.492b88d94db77d60.8b1abfa442fbff51
+ b668fd17348a5d7b.fe7b7cd0eb6044f6.dd79c32da747b9b4.cf1b10be2efc29d2
+ c206e930ae3d16d1.00b8e9cfe5b8bca0.09c9ffc97aecc47d.651c3496bc3ee3ee
+ 719752b30cd7789f.1da5626dabe25ea8.abe7ba99e3b05aea.a9672898884e6851
+ f74ae72e30b7f6a8
+ after
+ 71f2117c81b29172.bda321042150bafd.492b88d94db77d60.8b1abfa442fbff51
+ b668fd17348a5d7b.fe7b7cd0eb6044f6.dd79c32da747b9b4.cf1b10be2efc29d2
+ 0000000000000000.0000000000000000.b668fd17348a5d7b.fe7b7cd0eb6044f6
+ 719752b30cd7789f.1da5626dabe25ea8.abe7ba99e3b05aea.a9672898884e6851
+ f74ae72e30b7f6a8
+
+VPERM2F128_0x5A(reg)
+ before
+ ab0f6dc54d05c79f.9ee8b28c69623e11.b28fe517da6c66b9.9e9f6f8afda13625
+ 2103b6ca7dc417e2.27c687a7e2ec2555.1cc26e370de10f80.bebd9b86e5cb165a
+ b472bfa75c81241c.e7fb4cf09281e995.b58af73ae1ce96a9.e60cb87bb638b4b6
+ c2a783ca85c728f9.ba537e53962b45fd.da337e8df1be37df.f45a44538cf6cc65
+ c371bafc84111c92
+ after
+ 2103b6ca7dc417e2.27c687a7e2ec2555.0000000000000000.0000000000000000
+ 2103b6ca7dc417e2.27c687a7e2ec2555.1cc26e370de10f80.bebd9b86e5cb165a
+ b472bfa75c81241c.e7fb4cf09281e995.b58af73ae1ce96a9.e60cb87bb638b4b6
+ c2a783ca85c728f9.ba537e53962b45fd.da337e8df1be37df.f45a44538cf6cc65
+ c371bafc84111c92
+VPERM2F128_0x5A(mem)
+ before
+ 2e1e9661ba945e6a.a6f0fe9d94235f26.7b9c97bc0af8f7ba.e809fe9bda3d2dcf
+ 132d546e498b4f19.bc972c8e261f074f.08a1151708f4b9f8.395773cf37d8b624
+ 4d6a710f4d02aaca.5fea0908d74a5a1f.3b2d7351ae2947e2.2a6ad997a51a0b8b
+ b7a16830e3062caa.ed339277422d9543.f20d2d5518a65fa5.178e2d5ebf906bb0
+ 5c0f699022c4103e
+ after
+ 2e1e9661ba945e6a.a6f0fe9d94235f26.7b9c97bc0af8f7ba.e809fe9bda3d2dcf
+ 132d546e498b4f19.bc972c8e261f074f.08a1151708f4b9f8.395773cf37d8b624
+ 132d546e498b4f19.bc972c8e261f074f.0000000000000000.0000000000000000
+ b7a16830e3062caa.ed339277422d9543.f20d2d5518a65fa5.178e2d5ebf906bb0
+ 5c0f699022c4103e
+
+VPERM2F128_0x5A(reg)
+ before
+ 56398b99694437e2.2f9db5bd26a291e4.c1bec2470356f467.070dc00e6174bb6d
+ 5f588fe5309c1c47.8f2bd4a233e295a5.36d995e4b750b236.58f9a66aa6a11865
+ d4b76fe11456fb1a.b51842cc25d3f418.aacf07baf9a80c5d.bf9d5d54023831b9
+ 11a429f7b1010f07.7b2e79251980696a.77eb153666e93e87.1ac560b89145c497
+ 433c2c8270d58b29
+ after
+ 5f588fe5309c1c47.8f2bd4a233e295a5.0000000000000000.0000000000000000
+ 5f588fe5309c1c47.8f2bd4a233e295a5.36d995e4b750b236.58f9a66aa6a11865
+ d4b76fe11456fb1a.b51842cc25d3f418.aacf07baf9a80c5d.bf9d5d54023831b9
+ 11a429f7b1010f07.7b2e79251980696a.77eb153666e93e87.1ac560b89145c497
+ 433c2c8270d58b29
+VPERM2F128_0x5A(mem)
+ before
+ 18cf3b9ebbf3429b.7269b894a22695b9.be39f79b2af6b1c7.fb7bbac2999f8461
+ 734a0bf88daca71a.535318258353c8dd.5b073718753f875a.90c9f2cc2f571996
+ 3179177c020b74d2.10ae4515f113e61e.2c63b68a156aa950.9422b9bec39c3ad3
+ 2e28db17371c66ee.04c63bcf87f22929.0e18eedc2780d1d5.61d10b06f2fa23c4
+ 5524e50f57fe0f14
+ after
+ 18cf3b9ebbf3429b.7269b894a22695b9.be39f79b2af6b1c7.fb7bbac2999f8461
+ 734a0bf88daca71a.535318258353c8dd.5b073718753f875a.90c9f2cc2f571996
+ 734a0bf88daca71a.535318258353c8dd.0000000000000000.0000000000000000
+ 2e28db17371c66ee.04c63bcf87f22929.0e18eedc2780d1d5.61d10b06f2fa23c4
+ 5524e50f57fe0f14
+
+VPERM2F128_0x5A(reg)
+ before
+ ca6642458e333c70.4723d4b347eb389b.8de6f7c1e27dceaa.ddf35dfac68fbb14
+ 1de21e143425e384.56357c3e4f85a804.065c74569e3f104c.76c07ed00ea22539
+ abe575e8e56143fb.382c51a36af57056.cb72aefa55c52dbc.b34bcd4a1dc6c971
+ cebb442d3c729681.c9d2cecdb5484dbd.3875a219a69a5ea5.7160c7540c0664e8
+ 8ccbe7dbf96eb2ca
+ after
+ 1de21e143425e384.56357c3e4f85a804.0000000000000000.0000000000000000
+ 1de21e143425e384.56357c3e4f85a804.065c74569e3f104c.76c07ed00ea22539
+ abe575e8e56143fb.382c51a36af57056.cb72aefa55c52dbc.b34bcd4a1dc6c971
+ cebb442d3c729681.c9d2cecdb5484dbd.3875a219a69a5ea5.7160c7540c0664e8
+ 8ccbe7dbf96eb2ca
+VPERM2F128_0x5A(mem)
+ before
+ e057a9c9ff0a6e42.e3b0854fd5e419c3.e5f470aa4b89fa64.a9b14a202a4ae2b4
+ 49d1890c3be7557c.461036bb4d44086d.685eb12549c43478.7972a4798061f495
+ a306038ec91123a5.532652db3f1d9f2b.2edc0f2aca06b724.0603ab91416ccff3
+ cac0943dc49293e9.6740d61d48fb19a8.133905a5eb5a3f95.abb25bd50bf6b07a
+ c3c9b1b07a8cd2d8
+ after
+ e057a9c9ff0a6e42.e3b0854fd5e419c3.e5f470aa4b89fa64.a9b14a202a4ae2b4
+ 49d1890c3be7557c.461036bb4d44086d.685eb12549c43478.7972a4798061f495
+ 49d1890c3be7557c.461036bb4d44086d.0000000000000000.0000000000000000
+ cac0943dc49293e9.6740d61d48fb19a8.133905a5eb5a3f95.abb25bd50bf6b07a
+ c3c9b1b07a8cd2d8
+
+VPERMILPD_256_0x0(reg)
+ before
+ ac95a88d29b972b7.9acbb60448786274.dca8bceb046bb390.f3420f83c7cc87f7
+ c0623cdab509ccc3.eff5e7cf72ce4c71.0fab02b30df8a890.aac4a9ae7a684c75
+ 5d7c6902b9091ca9.a509a38a5da10d0c.5c95a3e0022e3654.14895014213b4a3c
+ dd2f2b71d1449d15.98d2642126fc6072.1fb29bde7c9a9788.0d5e7f9fd8513d77
+ 710fb23dbab4e053
+ after
+ ac95a88d29b972b7.9acbb60448786274.dca8bceb046bb390.f3420f83c7cc87f7
+ a509a38a5da10d0c.a509a38a5da10d0c.14895014213b4a3c.14895014213b4a3c
+ 5d7c6902b9091ca9.a509a38a5da10d0c.5c95a3e0022e3654.14895014213b4a3c
+ dd2f2b71d1449d15.98d2642126fc6072.1fb29bde7c9a9788.0d5e7f9fd8513d77
+ 710fb23dbab4e053
+VPERMILPD_256_0x0(mem)
+ before
+ 1c6765d8e372f0fc.9ec67f939a468db2.a41da880e8eb03cf.b44de7191ac708d7
+ ea34155e7097289d.fa8f5fd4af9c252d.a5b6e993c07baf4e.77b482fd7542c4ed
+ b7403cba7d2d4663.4fd4c9a0add1a432.7769a647c9b7231c.c43168f62b950877
+ 5e5858d824420479.f7e2b9643071446c.f50258861fab1965.f7119570d84f1021
+ 6ba005d817f91897
+ after
+ 1c6765d8e372f0fc.9ec67f939a468db2.a41da880e8eb03cf.b44de7191ac708d7
+ 9ec67f939a468db2.9ec67f939a468db2.b44de7191ac708d7.a41da880e8eb03cf
+ b7403cba7d2d4663.4fd4c9a0add1a432.7769a647c9b7231c.c43168f62b950877
+ 5e5858d824420479.f7e2b9643071446c.f50258861fab1965.f7119570d84f1021
+ 6ba005d817f91897
+
+VPERMILPD_256_0x0(reg)
+ before
+ 7e2ab59885215b83.bd48e4a484e21f0c.4f05298ad2094287.fd4c7c3edf644e54
+ 8bfb9f1ebd521694.afdc5d0ab6175247.b48917803224da31.6a158f5925ed7e16
+ ee5ec1d55b198574.0fe03df7d9f05b58.80b97eb0e94e4813.17270cc50c5264d6
+ 03a11728fc00e4d0.bb1f02550676f468.10e35a889614c7dc.e24f6f6db0a0bdc1
+ a659353d2ee24503
+ after
+ 7e2ab59885215b83.bd48e4a484e21f0c.4f05298ad2094287.fd4c7c3edf644e54
+ 0fe03df7d9f05b58.0fe03df7d9f05b58.17270cc50c5264d6.17270cc50c5264d6
+ ee5ec1d55b198574.0fe03df7d9f05b58.80b97eb0e94e4813.17270cc50c5264d6
+ 03a11728fc00e4d0.bb1f02550676f468.10e35a889614c7dc.e24f6f6db0a0bdc1
+ a659353d2ee24503
+VPERMILPD_256_0x0(mem)
+ before
+ 3e11d821a225b8c7.250e9b853c966e53.8d6727125cb7d9a6.c051a773d2019436
+ 8843d6052773d139.b2f24b57b56460aa.63822818f4bec83b.ed5062dd3ba1eacd
+ 5ebaaad5d9da4d87.0599220a06f8f681.183d8255ec977b56.f12c86326d81074f
+ 9e43d17dd566e8db.794e1c0ac9dd6b83.8764afb4604faf21.29310ede032c2566
+ f1abf94d9a2e80be
+ after
+ 3e11d821a225b8c7.250e9b853c966e53.8d6727125cb7d9a6.c051a773d2019436
+ 250e9b853c966e53.250e9b853c966e53.c051a773d2019436.8d6727125cb7d9a6
+ 5ebaaad5d9da4d87.0599220a06f8f681.183d8255ec977b56.f12c86326d81074f
+ 9e43d17dd566e8db.794e1c0ac9dd6b83.8764afb4604faf21.29310ede032c2566
+ f1abf94d9a2e80be
+
+VPERMILPD_256_0x0(reg)
+ before
+ a5e540ebcd145604.22abc5ea36225d61.6c5f35c49aa0fc5c.8dc32d206bf11fc9
+ a12de1253869e1e4.c7bc0406191a6946.38176aa216cce5ba.0725778729898979
+ 41cdd76578b95e09.6a4209bf995ac8b6.3bc1b511d8ed6247.cf580ad4b724a75e
+ e1121e192991091f.e50b5000d3ef36dc.cfaa147e7d90aeaf.c32660f331cd35a3
+ bd5cf7d1b291f175
+ after
+ a5e540ebcd145604.22abc5ea36225d61.6c5f35c49aa0fc5c.8dc32d206bf11fc9
+ 6a4209bf995ac8b6.6a4209bf995ac8b6.cf580ad4b724a75e.cf580ad4b724a75e
+ 41cdd76578b95e09.6a4209bf995ac8b6.3bc1b511d8ed6247.cf580ad4b724a75e
+ e1121e192991091f.e50b5000d3ef36dc.cfaa147e7d90aeaf.c32660f331cd35a3
+ bd5cf7d1b291f175
+VPERMILPD_256_0x0(mem)
+ before
+ 9ac64a58567b9500.dd48b2ace67c1dd4.16e255b4e2e46ee5.521e8254a040069f
+ 3730d5753a97de6f.91ba90894b07d7d2.d79295c9e3462dfc.1e69fcfedd89a6c3
+ 6e65151579f187ef.59b6b21ef5bd73c5.05e88b2af1202f4e.90d67dead2f7c9c6
+ 1c33842330964eab.908616d67f2a2d5b.7cb0b3c3287e2f07.05b300831817ac55
+ d74a83354d758b1b
+ after
+ 9ac64a58567b9500.dd48b2ace67c1dd4.16e255b4e2e46ee5.521e8254a040069f
+ dd48b2ace67c1dd4.dd48b2ace67c1dd4.521e8254a040069f.16e255b4e2e46ee5
+ 6e65151579f187ef.59b6b21ef5bd73c5.05e88b2af1202f4e.90d67dead2f7c9c6
+ 1c33842330964eab.908616d67f2a2d5b.7cb0b3c3287e2f07.05b300831817ac55
+ d74a83354d758b1b
+
+VPERMILPD_256_0xF(reg)
+ before
+ 63e8026c0d9ba2c6.1d64a08a7b92edd1.9478b71d86da403d.18b68980a56cea52
+ 06d97794f3172cff.4dc5e43874ef218a.c0d6925fa55ae91a.b6c6894e84f71c5c
+ 1a69e01a9b756674.8822cc1839bba504.70eda1097935639c.30ac3017e02a8150
+ fce43868a2408cd1.aa47d516e601366b.0008e2859df8ec6f.6333f9c8d512d45b
+ 2b28604e80bad2a9
+ after
+ 63e8026c0d9ba2c6.1d64a08a7b92edd1.9478b71d86da403d.18b68980a56cea52
+ 1a69e01a9b756674.1a69e01a9b756674.70eda1097935639c.70eda1097935639c
+ 1a69e01a9b756674.8822cc1839bba504.70eda1097935639c.30ac3017e02a8150
+ fce43868a2408cd1.aa47d516e601366b.0008e2859df8ec6f.6333f9c8d512d45b
+ 2b28604e80bad2a9
+VPERMILPD_256_0xF(mem)
+ before
+ 6458e193fc2e3765.08957beba304d9c2.90007a1e96ce90eb.cb755040ae2ebe40
+ ea8df985667bbfbc.9acaa5103b4d8bf2.1419371c662d6faf.2f7fe8a7476316bb
+ 9993230fdaac25d9.0fcdb34206a8db0d.135d88fc712a8ee3.8671a42404232f8b
+ 4d38db1d72cd26e9.c1eba0ec9ea008c0.6899e9abd4d2aab4.2e98822582fb475d
+ 82407d155d7798dd
+ after
+ 6458e193fc2e3765.08957beba304d9c2.90007a1e96ce90eb.cb755040ae2ebe40
+ 6458e193fc2e3765.6458e193fc2e3765.90007a1e96ce90eb.cb755040ae2ebe40
+ 9993230fdaac25d9.0fcdb34206a8db0d.135d88fc712a8ee3.8671a42404232f8b
+ 4d38db1d72cd26e9.c1eba0ec9ea008c0.6899e9abd4d2aab4.2e98822582fb475d
+ 82407d155d7798dd
+
+VPERMILPD_256_0xF(reg)
+ before
+ ddb5916030215eb6.e2479d9b4deb7e18.0d70687ca2c14cb7.f199d713aa307f4e
+ 9d43ba729787d794.348be5758411e891.4fa8075dab98e59e.8929cd220f50c9dc
+ 1c35f5b72f343d25.1ed13097364b2181.e3df7afb58b00c20.0c1547c2203f438b
+ b8d93d9b94b5cd13.7ee5f9ed7ca6e513.2560bbc2429600e9.5629c1e1f807aa87
+ 4330b76ab4b7b9fb
+ after
+ ddb5916030215eb6.e2479d9b4deb7e18.0d70687ca2c14cb7.f199d713aa307f4e
+ 1c35f5b72f343d25.1c35f5b72f343d25.e3df7afb58b00c20.e3df7afb58b00c20
+ 1c35f5b72f343d25.1ed13097364b2181.e3df7afb58b00c20.0c1547c2203f438b
+ b8d93d9b94b5cd13.7ee5f9ed7ca6e513.2560bbc2429600e9.5629c1e1f807aa87
+ 4330b76ab4b7b9fb
+VPERMILPD_256_0xF(mem)
+ before
+ aff7a64970592e14.cb798e8a6195c20a.2f93bc64742def74.7078c81e07d4fba6
+ 754b096a47f9c3fd.b262e4f132605ab7.0da7f5e63aecfdd0.22739c7c43f83a03
+ 73f65cb955a335e3.cae03b3aa4a3cfc6.f4ec2161e9f0c952.969d3446918ef9ab
+ 84c41b22b7643ff2.6d3f90d352e95de2.bf30bbbf9e440f27.28428aea8e21734b
+ 34ae9cd2d53de58f
+ after
+ aff7a64970592e14.cb798e8a6195c20a.2f93bc64742def74.7078c81e07d4fba6
+ aff7a64970592e14.aff7a64970592e14.2f93bc64742def74.7078c81e07d4fba6
+ 73f65cb955a335e3.cae03b3aa4a3cfc6.f4ec2161e9f0c952.969d3446918ef9ab
+ 84c41b22b7643ff2.6d3f90d352e95de2.bf30bbbf9e440f27.28428aea8e21734b
+ 34ae9cd2d53de58f
+
+VPERMILPD_256_0xF(reg)
+ before
+ 162c656c026e8b22.8383c39188479f55.f8cade26d9be42b8.4c3d3eee74f48d7a
+ 290ae123b241a0b1.4efecff3e5580f38.c7cf21a1d4afb8f3.76e029d9870dfd78
+ cb920d63804162e7.c000bb32e9a44bc9.379855afe047fc40.18e5f56cf49a1c4c
+ 5711e39809fb0b71.b456033cb0361132.a27277bc98124a4b.10182093d6a7a523
+ 3845253a4a415529
+ after
+ 162c656c026e8b22.8383c39188479f55.f8cade26d9be42b8.4c3d3eee74f48d7a
+ cb920d63804162e7.cb920d63804162e7.379855afe047fc40.379855afe047fc40
+ cb920d63804162e7.c000bb32e9a44bc9.379855afe047fc40.18e5f56cf49a1c4c
+ 5711e39809fb0b71.b456033cb0361132.a27277bc98124a4b.10182093d6a7a523
+ 3845253a4a415529
+VPERMILPD_256_0xF(mem)
+ before
+ 6e37804d6c73e889.28d3612ee9fad7fb.08cc24fb581a1b9f.65a98234989dddbf
+ 8cbbadb9564a1a70.9c248291bbca0430.962e985dfa5d263d.dc8972837e73f249
+ 709e286827d0a70a.0e4f432d1bf8ccbc.3c48dd4db40aed38.635d4315e321c594
+ f4aa6e47f8134a82.d9a29e6ea60f6c4d.d4e66eb7a22e2ebb.5673f1566531914d
+ 111579b3a0319320
+ after
+ 6e37804d6c73e889.28d3612ee9fad7fb.08cc24fb581a1b9f.65a98234989dddbf
+ 6e37804d6c73e889.6e37804d6c73e889.08cc24fb581a1b9f.65a98234989dddbf
+ 709e286827d0a70a.0e4f432d1bf8ccbc.3c48dd4db40aed38.635d4315e321c594
+ f4aa6e47f8134a82.d9a29e6ea60f6c4d.d4e66eb7a22e2ebb.5673f1566531914d
+ 111579b3a0319320
+
+VPERMILPD_256_0xA(reg)
+ before
+ f091d6962fad07b8.f5abfa43e81fc004.5b6791c1f79b1f8d.3bd3c887dfd3a3f3
+ 4f31046dae3029c2.506f484710ffc4be.eeeb1790ab292328.4edc65a98708080b
+ 8a41ffa2ba4634e9.dfc1d53e8fbf14da.ef7a2c495d43b2cb.e7cdc309b7d61b31
+ fd0fc4a3ee7b65da.7f6c1b167e6b6a84.bb60cc57a9780822.e3725d948a4b968e
+ 1f97af341d723650
+ after
+ f091d6962fad07b8.f5abfa43e81fc004.5b6791c1f79b1f8d.3bd3c887dfd3a3f3
+ 8a41ffa2ba4634e9.dfc1d53e8fbf14da.ef7a2c495d43b2cb.e7cdc309b7d61b31
+ 8a41ffa2ba4634e9.dfc1d53e8fbf14da.ef7a2c495d43b2cb.e7cdc309b7d61b31
+ fd0fc4a3ee7b65da.7f6c1b167e6b6a84.bb60cc57a9780822.e3725d948a4b968e
+ 1f97af341d723650
+VPERMILPD_256_0xA(mem)
+ before
+ 750835d68c58b6a3.04e64ddbe75cf841.0d3d98bafb1082e9.ace9f4252c5163d8
+ c2906c67f107d4b3.fb1198b6417429c9.6300c71622b91a35.20609f21825cfd9a
+ e2fdcfd26b8e4aab.3edda1a09650331f.5e8124160e73ec93.7112c9b646251313
+ b119da0313f6d5b7.28976205857a53ee.da8c2ca7db49b530.fc4c6e501536e1f0
+ 1e588b5c8a1da2dd
+ after
+ 750835d68c58b6a3.04e64ddbe75cf841.0d3d98bafb1082e9.ace9f4252c5163d8
+ 750835d68c58b6a3.04e64ddbe75cf841.0d3d98bafb1082e9.0d3d98bafb1082e9
+ e2fdcfd26b8e4aab.3edda1a09650331f.5e8124160e73ec93.7112c9b646251313
+ b119da0313f6d5b7.28976205857a53ee.da8c2ca7db49b530.fc4c6e501536e1f0
+ 1e588b5c8a1da2dd
+
+VPERMILPD_256_0xA(reg)
+ before
+ 31821b4441669385.0bb109e5084d3005.1788d951a781c5e3.b3ed59b3a6473137
+ 92181975d79bf095.cd91d966639e18be.66ff00f19aeec4aa.c56f29278b7a1bd5
+ 9d65845ce74af4b9.d185c57142f64911.7147d54ffa4f8dee.ecdf17f0a5ed3036
+ aeb455630effdc9c.f45848f3c1607f28.93ab54d9622f5c5b.040aa0f910ac2c85
+ e9ba3e2de9c3caef
+ after
+ 31821b4441669385.0bb109e5084d3005.1788d951a781c5e3.b3ed59b3a6473137
+ 9d65845ce74af4b9.d185c57142f64911.7147d54ffa4f8dee.ecdf17f0a5ed3036
+ 9d65845ce74af4b9.d185c57142f64911.7147d54ffa4f8dee.ecdf17f0a5ed3036
+ aeb455630effdc9c.f45848f3c1607f28.93ab54d9622f5c5b.040aa0f910ac2c85
+ e9ba3e2de9c3caef
+VPERMILPD_256_0xA(mem)
+ before
+ 77bb6f7a4b3fc79f.21528af8e845e4ea.12d8e1d6fbe8752f.2a7977f96f1b6d9f
+ 8adbaecb532cdfc2.528b1d860fa84850.07cf09070d9be853.90fb3c1dbc9efb64
+ fee5770c1c94ce84.9dab0c7922b4437a.ae0a3e73128494c0.237e9eb0e5444356
+ afa44729c3854f10.5efe533cbaf61214.e555fa0426af35a2.3d4e991e879a8122
+ 3cb629d33e2af074
+ after
+ 77bb6f7a4b3fc79f.21528af8e845e4ea.12d8e1d6fbe8752f.2a7977f96f1b6d9f
+ 77bb6f7a4b3fc79f.21528af8e845e4ea.12d8e1d6fbe8752f.12d8e1d6fbe8752f
+ fee5770c1c94ce84.9dab0c7922b4437a.ae0a3e73128494c0.237e9eb0e5444356
+ afa44729c3854f10.5efe533cbaf61214.e555fa0426af35a2.3d4e991e879a8122
+ 3cb629d33e2af074
+
+VPERMILPD_256_0xA(reg)
+ before
+ 7a044b3ba583cdf7.79e5980e630b1f93.f1d0ec3d76f9f1c9.877cbba866298624
+ 5582fac2582e5458.3874e8a71930fa38.b26cd5e8ef491c45.704afd4aeefd4472
+ 277e32d4f4b9c143.c81db2e100029c2c.fd2009a7c373ce35.7c8d3ad5d9372ab9
+ 4e42efdd14b04f63.04ac73a6358dc09a.2e3684e78e024445.870ff03743e4f625
+ 6c9d9a5b490f62e1
+ after
+ 7a044b3ba583cdf7.79e5980e630b1f93.f1d0ec3d76f9f1c9.877cbba866298624
+ 277e32d4f4b9c143.c81db2e100029c2c.fd2009a7c373ce35.7c8d3ad5d9372ab9
+ 277e32d4f4b9c143.c81db2e100029c2c.fd2009a7c373ce35.7c8d3ad5d9372ab9
+ 4e42efdd14b04f63.04ac73a6358dc09a.2e3684e78e024445.870ff03743e4f625
+ 6c9d9a5b490f62e1
+VPERMILPD_256_0xA(mem)
+ before
+ 0903b42d06c42b1a.241b2d4a559d3b64.caeca5e4d3db23b0.a1fb4215eb83b920
+ 390dba9a97100cfc.0654e985530ec1f3.f5abc685f6fa8197.b2bb409b77816b73
+ d787298c17fec3b2.513b1efca88f1cbc.60b35177bbf6957e.bdc179e7cd8894ea
+ c13c7cf0a39a0a69.5f1ac81af2aa896b.e9d1c2a53ed91c8e.1d5be96389247130
+ 30d38c7d48e23df2
+ after
+ 0903b42d06c42b1a.241b2d4a559d3b64.caeca5e4d3db23b0.a1fb4215eb83b920
+ 0903b42d06c42b1a.241b2d4a559d3b64.caeca5e4d3db23b0.caeca5e4d3db23b0
+ d787298c17fec3b2.513b1efca88f1cbc.60b35177bbf6957e.bdc179e7cd8894ea
+ c13c7cf0a39a0a69.5f1ac81af2aa896b.e9d1c2a53ed91c8e.1d5be96389247130
+ 30d38c7d48e23df2
+
+VPERMILPD_256_0x5(reg)
+ before
+ 51765ea0a54d35db.d2fa2fb356f19d4c.8d3fe34bcded44ab.6bd195fb9ab2d2f6
+ dc905c383df29598.e58bbebf4d0e3a88.37f46cfbd4e48928.c17f4765eb8a73e0
+ 2c6d81b1ac5c99d5.d8bca502a3fd9b48.b9865e96a4199390.c9a753cf4e6fba79
+ 9f59c9778c177d3d.8559616774cb7db9.6f41b588d81b9f8c.5d143525de6c64ec
+ 5b936954b88d2d66
+ after
+ 51765ea0a54d35db.d2fa2fb356f19d4c.8d3fe34bcded44ab.6bd195fb9ab2d2f6
+ d8bca502a3fd9b48.2c6d81b1ac5c99d5.c9a753cf4e6fba79.b9865e96a4199390
+ 2c6d81b1ac5c99d5.d8bca502a3fd9b48.b9865e96a4199390.c9a753cf4e6fba79
+ 9f59c9778c177d3d.8559616774cb7db9.6f41b588d81b9f8c.5d143525de6c64ec
+ 5b936954b88d2d66
+VPERMILPD_256_0x5(mem)
+ before
+ 9df16c46f7dfd012.8fa030f67cb07c7c.ca2e6ddadd839b07.b6706d3d0d73e9cb
+ 01f8b8e8b86d0a1d.5a8db39b16b2d340.81064546fa32b35d.e8618221deafacf7
+ 6174cb27164497b3.5a6d4dd0f6a9bd33.87af659ae6e37fe8.625ef1a1e75a26bc
+ 9a3321ee2e6e33ff.ed8cfa03b8217701.b9f34abfbda2bbd4.80b4b527c50091c8
+ 9eafca21142e29c4
+ after
+ 9df16c46f7dfd012.8fa030f67cb07c7c.ca2e6ddadd839b07.b6706d3d0d73e9cb
+ 8fa030f67cb07c7c.9df16c46f7dfd012.b6706d3d0d73e9cb.b6706d3d0d73e9cb
+ 6174cb27164497b3.5a6d4dd0f6a9bd33.87af659ae6e37fe8.625ef1a1e75a26bc
+ 9a3321ee2e6e33ff.ed8cfa03b8217701.b9f34abfbda2bbd4.80b4b527c50091c8
+ 9eafca21142e29c4
+
+VPERMILPD_256_0x5(reg)
+ before
+ 179b2cf96e6f2c5f.890034281bfa992e.6d36b69efaa73d57.f19f6fa29c7b254c
+ 49c4d81d7250d443.08a681c3faf1866c.38b77d0f55c74be1.0c7f502f9f7b777c
+ 8f76c9f8ba5b5d1c.f4f285aae661b6e4.a85b4cc1670bdd4a.e75f6953e0ad6e92
+ 45fcfaf6e21f0597.29b0bbc9fc55e4c2.1a6d1e20cc012e3f.5c0a36f87e1ec5b7
+ 484e340c93d93a1a
+ after
+ 179b2cf96e6f2c5f.890034281bfa992e.6d36b69efaa73d57.f19f6fa29c7b254c
+ f4f285aae661b6e4.8f76c9f8ba5b5d1c.e75f6953e0ad6e92.a85b4cc1670bdd4a
+ 8f76c9f8ba5b5d1c.f4f285aae661b6e4.a85b4cc1670bdd4a.e75f6953e0ad6e92
+ 45fcfaf6e21f0597.29b0bbc9fc55e4c2.1a6d1e20cc012e3f.5c0a36f87e1ec5b7
+ 484e340c93d93a1a
+VPERMILPD_256_0x5(mem)
+ before
+ 87f5de793bea87e5.c7a36a8387250660.84aca00d57dacd34.eb3bef981f357b6b
+ f5ccb02d935d6945.71b7120b44fb9d23.dfb2ae6013fb2d63.750fbb95fd31ff7b
+ 6fa02613b63f9b65.9e84f0fab62c068a.178e63af4dc4c07e.15367e830183f81b
+ cf3abd17c19cda72.ac56febd78457c44.080b3ae7204141af.28fc35cec7b7a0f6
+ 08acdbe3ec5733b9
+ after
+ 87f5de793bea87e5.c7a36a8387250660.84aca00d57dacd34.eb3bef981f357b6b
+ c7a36a8387250660.87f5de793bea87e5.eb3bef981f357b6b.eb3bef981f357b6b
+ 6fa02613b63f9b65.9e84f0fab62c068a.178e63af4dc4c07e.15367e830183f81b
+ cf3abd17c19cda72.ac56febd78457c44.080b3ae7204141af.28fc35cec7b7a0f6
+ 08acdbe3ec5733b9
+
+VPERMILPD_256_0x5(reg)
+ before
+ 12946c2c0bf1ef10.f269ef25cf7ee297.f6793bbe27d03cfb.8ef7aff2a97f6d22
+ a2fee517c1110ea6.b4f83a29fcf36f01.d738a06a5e5c825c.851c3ebe048a0005
+ 1438400ea942cd27.f1b21a0f65063cdc.ade02a2eb9728a12.c94764354c6cb681
+ c48c7b7f60106840.856409c426c40653.d3bed675d5a08fca.36439b459d334ac5
+ a8de61d914ea79fb
+ after
+ 12946c2c0bf1ef10.f269ef25cf7ee297.f6793bbe27d03cfb.8ef7aff2a97f6d22
+ f1b21a0f65063cdc.1438400ea942cd27.c94764354c6cb681.ade02a2eb9728a12
+ 1438400ea942cd27.f1b21a0f65063cdc.ade02a2eb9728a12.c94764354c6cb681
+ c48c7b7f60106840.856409c426c40653.d3bed675d5a08fca.36439b459d334ac5
+ a8de61d914ea79fb
+VPERMILPD_256_0x5(mem)
+ before
+ fbe332ddcc9eff4f.0e4791d582071a9d.4cda84325a388992.a41c9fab4e71ce30
+ 0b1d883de25a97ef.4eb47e7ca9b420ea.21e008471d6e81c7.7e46813bbf7283ef
+ b459e1e5712afe04.e0213fe073a2b6d2.e24210ed8c73a91c.bb8a7893c42ee9b3
+ d163b8c2961bf0bd.20d9cf6d7c5d1701.6acc1912c352bebd.b933811efa313d2a
+ d28c9749fd08bbfe
+ after
+ fbe332ddcc9eff4f.0e4791d582071a9d.4cda84325a388992.a41c9fab4e71ce30
+ 0e4791d582071a9d.fbe332ddcc9eff4f.a41c9fab4e71ce30.a41c9fab4e71ce30
+ b459e1e5712afe04.e0213fe073a2b6d2.e24210ed8c73a91c.bb8a7893c42ee9b3
+ d163b8c2961bf0bd.20d9cf6d7c5d1701.6acc1912c352bebd.b933811efa313d2a
+ d28c9749fd08bbfe
+
+VPERMILPD_128_0x0(reg)
+ before
+ 64e2b67e673e9fdb.400789be6c382844.6a27298f5f728124.95499da1dd177bd8
+ c981da2ad75f246e.dc11d0c60f8d64c5.1a584cb2b96c2de7.3f871a86f6cf9e96
+ 5eb500bae7f88763.814c0ac79c275e6d.8cb8314325d85af5.43500bad2b85e126
+ 80ca229833940465.0a86b1ac2f11d268.1c93d5ac3f4143fb.7f71ec02974501b2
+ ceb63971571cb966
+ after
+ 64e2b67e673e9fdb.400789be6c382844.6a27298f5f728124.95499da1dd177bd8
+ 0000000000000000.0000000000000000.43500bad2b85e126.43500bad2b85e126
+ 5eb500bae7f88763.814c0ac79c275e6d.8cb8314325d85af5.43500bad2b85e126
+ 80ca229833940465.0a86b1ac2f11d268.1c93d5ac3f4143fb.7f71ec02974501b2
+ ceb63971571cb966
+VPERMILPD_128_0x0(mem)
+ before
+ 0bea6fe68615c76f.890c3e3258bfd621.55894360e3577ee1.2535355ba43323a5
+ 14db094e413ce5f9.d6c64ff3f1063a42.3d223bd1d4061c05.05e94cbbf03a369e
+ c4538393a39ecf2f.c34552469bf46c75.9d1d16ea1f296900.17fc1637bee3ba93
+ f61f59a3c946433e.acd64199f115a866.53464e97e0cd20fd.b7bb903daab9e92f
+ 4070b5385149001f
+ after
+ 0bea6fe68615c76f.890c3e3258bfd621.55894360e3577ee1.2535355ba43323a5
+ 0000000000000000.0000000000000000.2535355ba43323a5.55894360e3577ee1
+ c4538393a39ecf2f.c34552469bf46c75.9d1d16ea1f296900.17fc1637bee3ba93
+ f61f59a3c946433e.acd64199f115a866.53464e97e0cd20fd.b7bb903daab9e92f
+ 4070b5385149001f
+
+VPERMILPD_128_0x0(reg)
+ before
+ 106880944f1e3b0f.880b0769ce41fb52.eec31a578ff629c0.396961c432fcfe28
+ 82eef0bd3ec4d5aa.54e30ad0ce99b496.e358d8ec12222c30.2d51ca5d31c4bfaf
+ f150fe20bdc80b9c.3873ddc6e75c2936.e8e377c51625ed61.09cb064ffa311fbc
+ bbd8a72765b41993.0e87fc3632961860.59aff34c368ca800.aba48f84a84eda7b
+ eda6e3ea5827ab19
+ after
+ 106880944f1e3b0f.880b0769ce41fb52.eec31a578ff629c0.396961c432fcfe28
+ 0000000000000000.0000000000000000.09cb064ffa311fbc.09cb064ffa311fbc
+ f150fe20bdc80b9c.3873ddc6e75c2936.e8e377c51625ed61.09cb064ffa311fbc
+ bbd8a72765b41993.0e87fc3632961860.59aff34c368ca800.aba48f84a84eda7b
+ eda6e3ea5827ab19
+VPERMILPD_128_0x0(mem)
+ before
+ ad9e7d6b25c84fc2.3ad4e83fd5173b39.b3eae30ccd523b3d.920749ee0fe298b9
+ c557d9f52c3e81a1.cc8ebcd5a67aac3a.04690f34d39c4efc.ef3874183cb4fa37
+ 129f73738894ffe3.cb531f54776ba943.dbd1fb9a61800fc7.cc8e7034598c0927
+ 7040c8d056d783b3.956e0e27e1766e00.15eb232b930b38cb.855539b003f80334
+ 76d9ccf7d584220b
+ after
+ ad9e7d6b25c84fc2.3ad4e83fd5173b39.b3eae30ccd523b3d.920749ee0fe298b9
+ 0000000000000000.0000000000000000.920749ee0fe298b9.b3eae30ccd523b3d
+ 129f73738894ffe3.cb531f54776ba943.dbd1fb9a61800fc7.cc8e7034598c0927
+ 7040c8d056d783b3.956e0e27e1766e00.15eb232b930b38cb.855539b003f80334
+ 76d9ccf7d584220b
+
+VPERMILPD_128_0x0(reg)
+ before
+ fb6524756cbba358.bc0753fab112c93e.842d83bc8225361c.8f8603d184488633
+ 6f473d966329c1c6.d0c090dcb5518fb0.f5db7c7ef6063f44.236d177a5044b42c
+ 30c913c6575ab902.8937fb637fa08f34.45c3f4d9d8a5c223.ae6bdc10140a80e1
+ 9938a271e3dbc7b7.c33810792b0c86f7.ce32e839c48cfe66.0c4ecd81eba6a47f
+ 19e066b8f225dd32
+ after
+ fb6524756cbba358.bc0753fab112c93e.842d83bc8225361c.8f8603d184488633
+ 0000000000000000.0000000000000000.ae6bdc10140a80e1.ae6bdc10140a80e1
+ 30c913c6575ab902.8937fb637fa08f34.45c3f4d9d8a5c223.ae6bdc10140a80e1
+ 9938a271e3dbc7b7.c33810792b0c86f7.ce32e839c48cfe66.0c4ecd81eba6a47f
+ 19e066b8f225dd32
+VPERMILPD_128_0x0(mem)
+ before
+ b2ee23a14491e625.06e0e703a4372792.5a8f4c0bd4a03025.ed74520a57492db9
+ b1448128fef97c85.d20ddde835fb153e.2a072a06966948e9.fed530b92d688cc7
+ f3aefa393b665b7d.5b0a808d33b2cc69.106e26548e728b6f.5ea17db0e173573d
+ 54f70cc017e63f3a.fc25cc5c39e888bc.e68ebce3d7c7b5e4.6723355c0ff8cac7
+ 76a9542a54832010
+ after
+ b2ee23a14491e625.06e0e703a4372792.5a8f4c0bd4a03025.ed74520a57492db9
+ 0000000000000000.0000000000000000.ed74520a57492db9.5a8f4c0bd4a03025
+ f3aefa393b665b7d.5b0a808d33b2cc69.106e26548e728b6f.5ea17db0e173573d
+ 54f70cc017e63f3a.fc25cc5c39e888bc.e68ebce3d7c7b5e4.6723355c0ff8cac7
+ 76a9542a54832010
+
+VPERMILPD_128_0x3(reg)
+ before
+ e77dd7854b9e96c4.b0ed32a9b084e3e8.10a8bdc3e42a87e6.8934699d8e758174
+ 16ecb9d891d76790.e35ae9e01f4d04b2.f5e0502dcf030391.d52ba870cf87ac4b
+ 5f42f691c1bad120.c90bab52824c5ec5.0619800596ff3969.a641f547b409f293
+ 1ecb8a1b78d20e20.3dccf6e9f58dad4c.9e9f49b9d6aa651b.d741cc0e5c080f7b
+ 46f6a9b1e08fbe2d
+ after
+ e77dd7854b9e96c4.b0ed32a9b084e3e8.10a8bdc3e42a87e6.8934699d8e758174
+ 0000000000000000.0000000000000000.0619800596ff3969.0619800596ff3969
+ 5f42f691c1bad120.c90bab52824c5ec5.0619800596ff3969.a641f547b409f293
+ 1ecb8a1b78d20e20.3dccf6e9f58dad4c.9e9f49b9d6aa651b.d741cc0e5c080f7b
+ 46f6a9b1e08fbe2d
+VPERMILPD_128_0x3(mem)
+ before
+ ce2d091c5faabcd6.afd271e251ab5b3b.1d694593931dac74.1bbea8b42b91c253
+ 4bb2673cf266c5a1.6ea5a852e9d1f31d.44ad143b78071869.d7c1976230408ebc
+ 99513ffbb7ce95bb.b78e2ad7dbd11373.8e66e0cdc157ac56.2ff6142f81410203
+ 93d60d46caeee750.e6daf3dec436f7e9.d75e2434891a2667.80a71a88bb225dd3
+ 2421a5d7796ed9d9
+ after
+ ce2d091c5faabcd6.afd271e251ab5b3b.1d694593931dac74.1bbea8b42b91c253
+ 0000000000000000.0000000000000000.1d694593931dac74.1bbea8b42b91c253
+ 99513ffbb7ce95bb.b78e2ad7dbd11373.8e66e0cdc157ac56.2ff6142f81410203
+ 93d60d46caeee750.e6daf3dec436f7e9.d75e2434891a2667.80a71a88bb225dd3
+ 2421a5d7796ed9d9
+
+VPERMILPD_128_0x3(reg)
+ before
+ 79b0b28a58b2b3c1.170c4e0a46d3788b.57d500d13f8ddb2a.fa625c5eed5b40ca
+ d9a03b0bf3792736.00c17d3248880499.65cb4b1ee860fae3.d53e04370826b7a9
+ a13c3ec8e74f71e5.2abf16a9eb1946a5.6e08d22f5c3e91c0.43be98a9f7884630
+ 2dd2b62bcfc1cc7a.70d3955d4b93fbdc.cdd7907237b0dc6c.1fae95a1d58cab8c
+ 47d9750bbf3ea0e9
+ after
+ 79b0b28a58b2b3c1.170c4e0a46d3788b.57d500d13f8ddb2a.fa625c5eed5b40ca
+ 0000000000000000.0000000000000000.6e08d22f5c3e91c0.6e08d22f5c3e91c0
+ a13c3ec8e74f71e5.2abf16a9eb1946a5.6e08d22f5c3e91c0.43be98a9f7884630
+ 2dd2b62bcfc1cc7a.70d3955d4b93fbdc.cdd7907237b0dc6c.1fae95a1d58cab8c
+ 47d9750bbf3ea0e9
+VPERMILPD_128_0x3(mem)
+ before
+ 960db6d4d0abe172.daaca0a2485a75a0.b0c976398501df69.de86815214441794
+ e714d4e625de2c54.0217f698eda7a703.c46d3629b46fae79.fc5fa23b8f857de3
+ 18bb492fd9e43bbb.025fb6795b32a051.8a8b5019f5ea2338.85afed9945004b06
+ 03ce939a09c8cbd2.36d0dbb12d899a33.dcee40f5647dfbd1.d4c260d8d240bda9
+ 44e4f664d0d10e77
+ after
+ 960db6d4d0abe172.daaca0a2485a75a0.b0c976398501df69.de86815214441794
+ 0000000000000000.0000000000000000.b0c976398501df69.de86815214441794
+ 18bb492fd9e43bbb.025fb6795b32a051.8a8b5019f5ea2338.85afed9945004b06
+ 03ce939a09c8cbd2.36d0dbb12d899a33.dcee40f5647dfbd1.d4c260d8d240bda9
+ 44e4f664d0d10e77
+
+VPERMILPD_128_0x3(reg)
+ before
+ 3360aba9de3f7b1c.86192d13d09697c6.fab661adff38d158.986382aa1b35f271
+ fb847c1395174046.7b6793864a5a5dc2.aa5c45d76ec9836a.98b79222391cc344
+ fa9a640f94e5999f.c08641df9421d7f3.a210819c16cbea15.bab4ed4bd8402b75
+ 8aef5f077433c1d3.2f40b40acaf6c184.3e1c136992c74307.d8270e0f14ade631
+ cfdb715c096eb0a3
+ after
+ 3360aba9de3f7b1c.86192d13d09697c6.fab661adff38d158.986382aa1b35f271
+ 0000000000000000.0000000000000000.a210819c16cbea15.a210819c16cbea15
+ fa9a640f94e5999f.c08641df9421d7f3.a210819c16cbea15.bab4ed4bd8402b75
+ 8aef5f077433c1d3.2f40b40acaf6c184.3e1c136992c74307.d8270e0f14ade631
+ cfdb715c096eb0a3
+VPERMILPD_128_0x3(mem)
+ before
+ 7c9e931dd58f44f8.09cf6969d48ff58f.a56266f307e6d9a2.dacdf6a87e4bcae9
+ b93aee3e911c5f5b.d1867ea04d84717f.feb8d58667fbd979.d26f26c777e2ba6a
+ 637c00aa5b22bdf9.405f9b177d9f704e.170e7db007447e34.824da03119185034
+ 563144504fac19fe.b0a8bb3c006b2fa9.ca2fd85b02ca8300.46b55f52fe7ac8f3
+ 7af15f95c5935d54
+ after
+ 7c9e931dd58f44f8.09cf6969d48ff58f.a56266f307e6d9a2.dacdf6a87e4bcae9
+ 0000000000000000.0000000000000000.a56266f307e6d9a2.dacdf6a87e4bcae9
+ 637c00aa5b22bdf9.405f9b177d9f704e.170e7db007447e34.824da03119185034
+ 563144504fac19fe.b0a8bb3c006b2fa9.ca2fd85b02ca8300.46b55f52fe7ac8f3
+ 7af15f95c5935d54
+
+VUNPCKLPD_256(reg)
+ before
+ 7a4f9c6908f04d03.6f22361988c73095.7eabda7a7174ea3b.f4e96475759ba608
+ a1191237631cd2ab.881e53f2227ebeeb.07b5f43d6c47ddb1.71069ce97bc2a179
+ 4d9cbe6c73a328f9.7ef015c73add7f2b.a51206f28e6f43b7.1e54fca2314c317f
+ d9249b74d3118d99.2d63fa85ecf12e82.b50e0a03737859f8.d59d008eb2441145
+ 73ad24981bb6fef8
+ after
+ 7ef015c73add7f2b.881e53f2227ebeeb.1e54fca2314c317f.71069ce97bc2a179
+ a1191237631cd2ab.881e53f2227ebeeb.07b5f43d6c47ddb1.71069ce97bc2a179
+ 4d9cbe6c73a328f9.7ef015c73add7f2b.a51206f28e6f43b7.1e54fca2314c317f
+ d9249b74d3118d99.2d63fa85ecf12e82.b50e0a03737859f8.d59d008eb2441145
+ 73ad24981bb6fef8
+VUNPCKLPD_256(mem)
+ before
+ d452e5ac87aeb4c3.a0fca5bc1ff33b36.71457d1653c5881c.93f5feddb6ef5b21
+ d457beb61339efd3.0072d8aef5d46f7d.26601b688b654924.9c13ddedf35f84dd
+ 4f872ba3da636a54.54d031b8ee416419.28814e66b1dd2dc7.2ab3a49dc75512d9
+ 21afa95df836e271.f763aa44a8c558b7.537494fbe03aef30.9a224d5bcd5b3ec1
+ 48acd692a2ff4740
+ after
+ d452e5ac87aeb4c3.a0fca5bc1ff33b36.71457d1653c5881c.93f5feddb6ef5b21
+ d457beb61339efd3.0072d8aef5d46f7d.26601b688b654924.9c13ddedf35f84dd
+ a0fca5bc1ff33b36.0072d8aef5d46f7d.93f5feddb6ef5b21.9c13ddedf35f84dd
+ 21afa95df836e271.f763aa44a8c558b7.537494fbe03aef30.9a224d5bcd5b3ec1
+ 48acd692a2ff4740
+
+VUNPCKLPD_256(reg)
+ before
+ 909d3aaee1cd6703.269bb2d18ac01357.477741c0bfec8502.8304681535884c8c
+ ce41761a2750dbb5.3a17c4ecac0cb931.9e58f197ce4327a8.94ff469fcbd1ff07
+ 5ee484440f14df03.38ef5a9979278f2c.5a52b73571557c52.622fab85bf23c6cc
+ 9cd1629836a5af99.feeff0c30d1c5274.d5b08d0645aebeaf.c96111b32c8a5b08
+ a461f6162f107be6
+ after
+ 38ef5a9979278f2c.3a17c4ecac0cb931.622fab85bf23c6cc.94ff469fcbd1ff07
+ ce41761a2750dbb5.3a17c4ecac0cb931.9e58f197ce4327a8.94ff469fcbd1ff07
+ 5ee484440f14df03.38ef5a9979278f2c.5a52b73571557c52.622fab85bf23c6cc
+ 9cd1629836a5af99.feeff0c30d1c5274.d5b08d0645aebeaf.c96111b32c8a5b08
+ a461f6162f107be6
+VUNPCKLPD_256(mem)
+ before
+ d1fbd598e3c3e193.e4550b8037908622.67e2035885f7bd34.6dc07176e5db2a68
+ 2bfb2b2765af4b3b.92bd7b69af60a14b.4f960e43fcc58e99.7ccc5ef2ee67fb2c
+ 8e2d72add0de7309.0153aec039a23cbf.92d58c708f917fce.602150e4fcde6fa5
+ d55c2818405e1529.8f63a1ef71e0922b.0b6cfccb5a674d00.730b44b9aacdc080
+ 12d634de94bf2a68
+ after
+ d1fbd598e3c3e193.e4550b8037908622.67e2035885f7bd34.6dc07176e5db2a68
+ 2bfb2b2765af4b3b.92bd7b69af60a14b.4f960e43fcc58e99.7ccc5ef2ee67fb2c
+ e4550b8037908622.92bd7b69af60a14b.6dc07176e5db2a68.7ccc5ef2ee67fb2c
+ d55c2818405e1529.8f63a1ef71e0922b.0b6cfccb5a674d00.730b44b9aacdc080
+ 12d634de94bf2a68
+
+VUNPCKLPD_256(reg)
+ before
+ 99cd1ebe5740eb0a.de55c852d23befc9.973b4e64f4a9e03b.9827d7407754b35a
+ 653efdc48edd3d11.84e4ce49a27fbb13.7526b3895e86629a.14d19bbc05636f0a
+ d073ce5ed5215d2a.a2d5b7e8cb383633.856fcccc4a0553f5.5a38c2291da13b39
+ 37b98bf7ca988601.16f4fd1b69721b56.2263939854b1f1f7.4826ca74dd18d316
+ b8682f8a61d6f5ca
+ after
+ a2d5b7e8cb383633.84e4ce49a27fbb13.5a38c2291da13b39.14d19bbc05636f0a
+ 653efdc48edd3d11.84e4ce49a27fbb13.7526b3895e86629a.14d19bbc05636f0a
+ d073ce5ed5215d2a.a2d5b7e8cb383633.856fcccc4a0553f5.5a38c2291da13b39
+ 37b98bf7ca988601.16f4fd1b69721b56.2263939854b1f1f7.4826ca74dd18d316
+ b8682f8a61d6f5ca
+VUNPCKLPD_256(mem)
+ before
+ 88ca6b56c4e75b84.f65c32fb06cff641.ba0d1ece993827a8.aa4e06591917764d
+ 9218fcc32356c26e.69a8bed62751e797.6ceb95ee76961654.787c207b34c21ea2
+ b41e5dbf992fe5b5.ece92bf4c9aa96ae.065cde651d98a487.e739dd6a423e27a4
+ c8a80a35427e8284.db6a76c287673e33.662a7620a94b8d6d.55d03992df17cbfc
+ 1c8f3160a5da4759
+ after
+ 88ca6b56c4e75b84.f65c32fb06cff641.ba0d1ece993827a8.aa4e06591917764d
+ 9218fcc32356c26e.69a8bed62751e797.6ceb95ee76961654.787c207b34c21ea2
+ f65c32fb06cff641.69a8bed62751e797.aa4e06591917764d.787c207b34c21ea2
+ c8a80a35427e8284.db6a76c287673e33.662a7620a94b8d6d.55d03992df17cbfc
+ 1c8f3160a5da4759
+
+VUNPCKHPD_256(reg)
+ before
+ 9ac0bf3e3313d664.ac817f113b505308.937899aafd131cd2.6622d80c37ba8c31
+ 29b0e19a224cb6cc.3a76393fa0b0146c.6e60921ac83a6c36.e4107f13e2f25eff
+ 27ab93de1013213b.4f54b2ac8cab83dd.c86c5c7c84696a0c.babfea23c7fdbe05
+ eefdcf7899f3535e.c8e568421b4b5a87.ffe9f43ecc2b51ff.c5fd922701ea6a6c
+ e294f50badc21c63
+ after
+ 27ab93de1013213b.29b0e19a224cb6cc.c86c5c7c84696a0c.6e60921ac83a6c36
+ 29b0e19a224cb6cc.3a76393fa0b0146c.6e60921ac83a6c36.e4107f13e2f25eff
+ 27ab93de1013213b.4f54b2ac8cab83dd.c86c5c7c84696a0c.babfea23c7fdbe05
+ eefdcf7899f3535e.c8e568421b4b5a87.ffe9f43ecc2b51ff.c5fd922701ea6a6c
+ e294f50badc21c63
+VUNPCKHPD_256(mem)
+ before
+ eb518dbbe6939014.dcf293d358798ae0.7ff5d6ee6a9f5695.6e2254cb3c0d5ebc
+ bd01d823c96884ab.4bd5d95bea30006e.5152799d94b03234.71657a8e719acdef
+ 346d522f714eb256.98f4a07ceaa4f2b3.1ac7cc39b68cac90.64fc61f5065eda43
+ 2c6475cbfa4fd73f.1f99e1a2f4629b5c.b61f4ab0eb3e7ed4.a334056b98e5c065
+ 8a5a625cc2bcbc00
+ after
+ eb518dbbe6939014.dcf293d358798ae0.7ff5d6ee6a9f5695.6e2254cb3c0d5ebc
+ bd01d823c96884ab.4bd5d95bea30006e.5152799d94b03234.71657a8e719acdef
+ eb518dbbe6939014.bd01d823c96884ab.7ff5d6ee6a9f5695.5152799d94b03234
+ 2c6475cbfa4fd73f.1f99e1a2f4629b5c.b61f4ab0eb3e7ed4.a334056b98e5c065
+ 8a5a625cc2bcbc00
+
+VUNPCKHPD_256(reg)
+ before
+ 74b87535216e0ac1.82b1bfe3817aae92.3d119939a5f53915.022771ed50d3652c
+ bf9a39605088e553.101fab6422d8f57c.4ca8c5ad99e90689.d8abbddc00561cc5
+ c64eaa4aec958a64.b37cb538f7776629.a9a9606b6bcb3f65.1577a86918d360cb
+ e41ec4609021359d.4792594d1f62bec4.b06266ddb7261f54.9557b080b357ed6a
+ 3416500deeec7fcd
+ after
+ c64eaa4aec958a64.bf9a39605088e553.a9a9606b6bcb3f65.4ca8c5ad99e90689
+ bf9a39605088e553.101fab6422d8f57c.4ca8c5ad99e90689.d8abbddc00561cc5
+ c64eaa4aec958a64.b37cb538f7776629.a9a9606b6bcb3f65.1577a86918d360cb
+ e41ec4609021359d.4792594d1f62bec4.b06266ddb7261f54.9557b080b357ed6a
+ 3416500deeec7fcd
+VUNPCKHPD_256(mem)
+ before
+ ce8204fce4a1d120.7758840dd9b822ad.a82e148eb4a6b87a.bd1dd3711a86e303
+ 3f65483ab17fa090.da46e4bc62e78c3d.b21c61e6d24e1176.2d27a4912f78c71e
+ 638c99b17294a849.6835e2dbc73ab0fc.4127bc43966685e5.5acdd4ab93870750
+ 16c3724f43eca576.7f7179d5a53bc994.311da1901bfbd0f2.a1595f2ae140de46
+ 5e17417ab62d89ab
+ after
+ ce8204fce4a1d120.7758840dd9b822ad.a82e148eb4a6b87a.bd1dd3711a86e303
+ 3f65483ab17fa090.da46e4bc62e78c3d.b21c61e6d24e1176.2d27a4912f78c71e
+ ce8204fce4a1d120.3f65483ab17fa090.a82e148eb4a6b87a.b21c61e6d24e1176
+ 16c3724f43eca576.7f7179d5a53bc994.311da1901bfbd0f2.a1595f2ae140de46
+ 5e17417ab62d89ab
+
+VUNPCKHPD_256(reg)
+ before
+ ed557707addd442c.33d64ffe3f915244.7945a616987815b2.5dc88cb97e18adcb
+ aa5dfb3d63d94b75.9890acac82916cdf.b4ff630a3b7cce01.a3f5faabdac9d999
+ f17dcb8873afd931.20bf064429f8ae72.8ae9ae1d2ad4312e.de7066504c1b108b
+ 1dffe2547aea2b0d.a72dd7b250d0d62a.585182bb020b7ae4.ea054c95ef190ecb
+ a3802867dfcf8e85
+ after
+ f17dcb8873afd931.aa5dfb3d63d94b75.8ae9ae1d2ad4312e.b4ff630a3b7cce01
+ aa5dfb3d63d94b75.9890acac82916cdf.b4ff630a3b7cce01.a3f5faabdac9d999
+ f17dcb8873afd931.20bf064429f8ae72.8ae9ae1d2ad4312e.de7066504c1b108b
+ 1dffe2547aea2b0d.a72dd7b250d0d62a.585182bb020b7ae4.ea054c95ef190ecb
+ a3802867dfcf8e85
+VUNPCKHPD_256(mem)
+ before
+ e4ad77b0394a4de6.8c303d0e13167cb4.09a79de211279e32.7b81db515eade4d0
+ 8b57b35e1995071a.995cd620dac00ad3.21f9d3c08b09c3b7.4dc6b649db47ac9e
+ 734b5a5c9abc774c.a0ceabf86c730f16.cdeff638d88000e5.2b6b0e1114640ef9
+ 7755e895d8cc5aa9.fdd4b70165bcc828.e8558036149a13e7.72bede13a690458e
+ 7c0925bd2c588e09
+ after
+ e4ad77b0394a4de6.8c303d0e13167cb4.09a79de211279e32.7b81db515eade4d0
+ 8b57b35e1995071a.995cd620dac00ad3.21f9d3c08b09c3b7.4dc6b649db47ac9e
+ e4ad77b0394a4de6.8b57b35e1995071a.09a79de211279e32.21f9d3c08b09c3b7
+ 7755e895d8cc5aa9.fdd4b70165bcc828.e8558036149a13e7.72bede13a690458e
+ 7c0925bd2c588e09
+
+VSHUFPS_0x39_256(reg)
+ before
+ a69adc7a43472515.7541d7f7f0d06c5d.0bb8f6a6602670b6.4df6efa75b63b6e9
+ 4cbb00b686e9465e.47dba56dfed56993.28c76555f93d446b.daa0be75cbe6a519
+ cbb98edd92cb2c91.cbefcce31de50c78.af4dfe79cd8e80f4.691d698e7d2f9ea1
+ 7de0815b0278145a.db48ca46690e1237.fb96bf7e77a360fc.d83a6ddc8f4a5bad
+ 01c3454d1d44996a
+ after
+ 690e12377de0815b.86e9465e47dba56d.8f4a5badfb96bf7e.f93d446bdaa0be75
+ 4cbb00b686e9465e.47dba56dfed56993.28c76555f93d446b.daa0be75cbe6a519
+ cbb98edd92cb2c91.cbefcce31de50c78.af4dfe79cd8e80f4.691d698e7d2f9ea1
+ 7de0815b0278145a.db48ca46690e1237.fb96bf7e77a360fc.d83a6ddc8f4a5bad
+ 01c3454d1d44996a
+VSHUFPS_0x39_256(mem)
+ before
+ c2846ccc42281304.bf7bd59c727d3a65.55b41b80ff5c37fd.6aeea3d0940b2031
+ f54861451b0287a6.edd8870c7f64d95d.13fd397efada36f5.57a1a7dcc04ffb3c
+ 78dd9da4c3dfaf7d.63419118c5bb2fee.f3f0a22d7794cc4c.1dfac50c95fd2ecc
+ 250d9dd556ca47b5.7d03f12adf0e76c5.cf59d1779196b52e.1a46fbcdb1a0f48a
+ a8d2448cb0c58a25
+ after
+ c2846ccc42281304.bf7bd59c727d3a65.55b41b80ff5c37fd.6aeea3d0940b2031
+ f54861451b0287a6.edd8870c7f64d95d.13fd397efada36f5.57a1a7dcc04ffb3c
+ c2846ccc727d3a65.edd8870c1b0287a6.55b41b80940b2031.57a1a7dcfada36f5
+ 250d9dd556ca47b5.7d03f12adf0e76c5.cf59d1779196b52e.1a46fbcdb1a0f48a
+ a8d2448cb0c58a25
+
+VSHUFPS_0x39_256(reg)
+ before
+ 25e89cb42df72c47.d9a5dec4f1d00d79.976aa2b069e8ea8e.8503424a65edadc6
+ ebd400b0c5c2169d.7171db5eaffcbbf5.0dc2a11500d5c9f5.efbc71910ea46f41
+ 57e46aee13b384d2.c73d108dad5a0e56.3b57e8c440614da5.ea4edb38a9c8b8cb
+ c662d8d9b455b193.b8d5fa3e07f6c1c8.7c75752bc319b24a.5286fb2b5164448f
+ 04314d562284ceb9
+ after
+ 07f6c1c8c662d8d9.c5c2169d7171db5e.5164448f7c75752b.00d5c9f5efbc7191
+ ebd400b0c5c2169d.7171db5eaffcbbf5.0dc2a11500d5c9f5.efbc71910ea46f41
+ 57e46aee13b384d2.c73d108dad5a0e56.3b57e8c440614da5.ea4edb38a9c8b8cb
+ c662d8d9b455b193.b8d5fa3e07f6c1c8.7c75752bc319b24a.5286fb2b5164448f
+ 04314d562284ceb9
+VSHUFPS_0x39_256(mem)
+ before
+ da184da539341376.929c45dd4334da8b.2004135ed7dd9277.2e6743b528883691
+ b10a7804b281cff2.18dcad665cdd3a67.db97d9d83c1a3b8e.ac7a4ece083b1326
+ 65d2485fa876be59.b56f0de09cdb0fd3.c65bc7974fba7939.52fa93e202bc86b4
+ d23b3ba337209bd6.c3a160b89fba937a.bb1a5a892fc807a6.7c330c5eaf9acbe8
+ 8571b7acae5e1d6e
+ after
+ da184da539341376.929c45dd4334da8b.2004135ed7dd9277.2e6743b528883691
+ b10a7804b281cff2.18dcad665cdd3a67.db97d9d83c1a3b8e.ac7a4ece083b1326
+ da184da54334da8b.18dcad66b281cff2.2004135e28883691.ac7a4ece3c1a3b8e
+ d23b3ba337209bd6.c3a160b89fba937a.bb1a5a892fc807a6.7c330c5eaf9acbe8
+ 8571b7acae5e1d6e
+
+VSHUFPS_0x39_256(reg)
+ before
+ cb008f399896b9f1.d413ccba7c8a2395.9fbea25800070209.97a00c99f550a2fe
+ a92b90720bcddb1e.4724789293c012c3.a511cf2d5b4d9a2b.36bb5bb3bf5f0670
+ 7a40b7c1a390bfa0.073bb91696cf248c.31e8e3a44d18958d.7436c2c4a900ef26
+ 9c89fe94fb6aa024.f0240d31a4c2141c.9f8ddb2871f530db.2ddcbdb6ce3f184c
+ 3d7ac8764b283e10
+ after
+ a4c2141c9c89fe94.0bcddb1e47247892.ce3f184c9f8ddb28.5b4d9a2b36bb5bb3
+ a92b90720bcddb1e.4724789293c012c3.a511cf2d5b4d9a2b.36bb5bb3bf5f0670
+ 7a40b7c1a390bfa0.073bb91696cf248c.31e8e3a44d18958d.7436c2c4a900ef26
+ 9c89fe94fb6aa024.f0240d31a4c2141c.9f8ddb2871f530db.2ddcbdb6ce3f184c
+ 3d7ac8764b283e10
+VSHUFPS_0x39_256(mem)
+ before
+ 80dd60f13bc81d9b.69536356b0e7bb55.deaaefd1d6a59f9e.4b4db224646fa7c0
+ d2ce0011ba2b711c.3feae2735d944ce1.ad9bdbe14b85803e.91746406c11335e9
+ 0f1c24c4e55bf5bd.789975579efb8e71.39c14e4d1c6d7529.cd4eed39256b1701
+ 129248f4d86666aa.72ae196e10abbeb3.5ee9c2026869388b.5b2649292b0589b5
+ 974a7542706dc6b1
+ after
+ 80dd60f13bc81d9b.69536356b0e7bb55.deaaefd1d6a59f9e.4b4db224646fa7c0
+ d2ce0011ba2b711c.3feae2735d944ce1.ad9bdbe14b85803e.91746406c11335e9
+ 80dd60f1b0e7bb55.3feae273ba2b711c.deaaefd1646fa7c0.917464064b85803e
+ 129248f4d86666aa.72ae196e10abbeb3.5ee9c2026869388b.5b2649292b0589b5
+ 974a7542706dc6b1
+
+VUNPCKLPS_256(reg)
+ before
+ dd046cf08f2e0ba0.b9fbe98fad587f10.8773cb244e2d1853.f8dfb5ea4886868f
+ 89a12aa025d4942f.df258180833bfe1b.153586e5f50fd8fd.e26fa2f2dacf1a62
+ f76dabbccdeb9d09.60da8eb3741d9df6.7640471ea1dd395c.fa6505073a50b230
+ 83b4ecb2230061db.17e78b149c0a19ce.07e00839ec21781d.1b8d5b1383160824
+ 21b21f04d22cd86b
+ after
+ 60da8eb3df258180.741d9df6833bfe1b.fa650507e26fa2f2.3a50b230dacf1a62
+ 89a12aa025d4942f.df258180833bfe1b.153586e5f50fd8fd.e26fa2f2dacf1a62
+ f76dabbccdeb9d09.60da8eb3741d9df6.7640471ea1dd395c.fa6505073a50b230
+ 83b4ecb2230061db.17e78b149c0a19ce.07e00839ec21781d.1b8d5b1383160824
+ 21b21f04d22cd86b
+VUNPCKLPS_256(mem)
+ before
+ e7a1cdc5429ee030.89c2e8ecc49e1e51.e218f590180c2dcf.2561c7a47569d1eb
+ 4b26e141ef79daa0.64e29bd84c520d16.9c38461103329724.2a0f7fc9d5417f73
+ 270dd766f6c883e7.726101e156a76dd7.2015fc847a8511fa.73352c16ab33bf60
+ 59222c1f72979630.0e8c16737e29783f.4c7992d69813577c.5d20caf690cdcd5f
+ 421d56d5229be51c
+ after
+ e7a1cdc5429ee030.89c2e8ecc49e1e51.e218f590180c2dcf.2561c7a47569d1eb
+ 4b26e141ef79daa0.64e29bd84c520d16.9c38461103329724.2a0f7fc9d5417f73
+ 89c2e8ec64e29bd8.c49e1e514c520d16.2561c7a42a0f7fc9.7569d1ebd5417f73
+ 59222c1f72979630.0e8c16737e29783f.4c7992d69813577c.5d20caf690cdcd5f
+ 421d56d5229be51c
+
+VUNPCKLPS_256(reg)
+ before
+ 7f76ca1ffd274242.bc315b5980f3d0a7.94add7fa61646bfb.fa3184f179e727d7
+ 70772440bc00217e.2b05e0fe3ce7ed7a.5f113fe29ae582b6.080a4fc33b0d3b36
+ 716e60a4fcafbe7b.846c37fbc17fa9d2.cd034a97c638f81d.50cd6d37f79250c6
+ dea678b758c255e6.a130dd3c2bc8c0de.38d1f48580e70adc.b0495c38cb8121b3
+ 024997b4d3e76c28
+ after
+ 846c37fb2b05e0fe.c17fa9d23ce7ed7a.50cd6d37080a4fc3.f79250c63b0d3b36
+ 70772440bc00217e.2b05e0fe3ce7ed7a.5f113fe29ae582b6.080a4fc33b0d3b36
+ 716e60a4fcafbe7b.846c37fbc17fa9d2.cd034a97c638f81d.50cd6d37f79250c6
+ dea678b758c255e6.a130dd3c2bc8c0de.38d1f48580e70adc.b0495c38cb8121b3
+ 024997b4d3e76c28
+VUNPCKLPS_256(mem)
+ before
+ 24989b962aceeb52.136a6ae66cc4216b.5f1e4cae97cdedc8.fec53a186580f49e
+ f003e2cbec445a5d.6c07309bd5415fb5.9b02023b209bedbd.792d17bd108ef210
+ 4357ea3d36557774.45c9c9442fc64a71.2fa77ad1e23d7be8.075387de1e9e3fde
+ fa5e2ed9240cfcc3.fafc2e4b15de204a.f8db315bfbbf5576.028486e92a3b18b3
+ c80c1049d1f1b93c
+ after
+ 24989b962aceeb52.136a6ae66cc4216b.5f1e4cae97cdedc8.fec53a186580f49e
+ f003e2cbec445a5d.6c07309bd5415fb5.9b02023b209bedbd.792d17bd108ef210
+ 136a6ae66c07309b.6cc4216bd5415fb5.fec53a18792d17bd.6580f49e108ef210
+ fa5e2ed9240cfcc3.fafc2e4b15de204a.f8db315bfbbf5576.028486e92a3b18b3
+ c80c1049d1f1b93c
+
+VUNPCKLPS_256(reg)
+ before
+ b3362269ae4d5d24.efe42a8cd075a678.e7ec5c1e23161bed.d368a1c5842d3592
+ 2050b7b75eda4118.ffb75b40599c30bd.68e45028f6f87806.9a1b48fb9b94d769
+ 6ca4cb9e7c24a1c3.06a23be3d98e58be.d93205d529137240.2ac1a1e95cfff927
+ f17f5a8aa4b8b9d2.e170485f6c57d8a8.9520779159f04648.5f23287be27b55f7
+ 15105a9d4913a806
+ after
+ 06a23be3ffb75b40.d98e58be599c30bd.2ac1a1e99a1b48fb.5cfff9279b94d769
+ 2050b7b75eda4118.ffb75b40599c30bd.68e45028f6f87806.9a1b48fb9b94d769
+ 6ca4cb9e7c24a1c3.06a23be3d98e58be.d93205d529137240.2ac1a1e95cfff927
+ f17f5a8aa4b8b9d2.e170485f6c57d8a8.9520779159f04648.5f23287be27b55f7
+ 15105a9d4913a806
+VUNPCKLPS_256(mem)
+ before
+ 2953b23caed3ad7f.0c2d61e87321c4f1.6aeefda22f016da7.fafba3c8211d30c9
+ 75b7ab422dc8228f.1afada2285ebffcb.7ee8d6973d9ad2e6.630f83e61e256c70
+ d60ac49ce1fcc162.7532c3a575a3a60d.f92a502ab22dc492.2ca81558eb9535e8
+ 28167637e67e4723.7a2017dedfd4f562.b780e647acc7ffd6.b012548825f7c9de
+ 4d983ce467da61fe
+ after
+ 2953b23caed3ad7f.0c2d61e87321c4f1.6aeefda22f016da7.fafba3c8211d30c9
+ 75b7ab422dc8228f.1afada2285ebffcb.7ee8d6973d9ad2e6.630f83e61e256c70
+ 0c2d61e81afada22.7321c4f185ebffcb.fafba3c8630f83e6.211d30c91e256c70
+ 28167637e67e4723.7a2017dedfd4f562.b780e647acc7ffd6.b012548825f7c9de
+ 4d983ce467da61fe
+
+VUNPCKHPS_256(reg)
+ before
+ 5e87cad64dc73cf3.47a83efe59576fff.8512d337600a2777.94b514da44733fdf
+ 3e2bf9cc744c946a.0f8c99dd5595f621.f252f11e93d279f8.6c9756cf983d3fd9
+ 4bd0c53178f4a60f.5c8d02bff74498b6.1d2d6ffe15b72690.1bf02813c432bcef
+ dfc22a71f44cae8d.0a79f5925a6e11ea.62ef484381456cec.7d8d0790e35d724e
+ 6e3a6e3411ca1d21
+ after
+ 4bd0c5313e2bf9cc.78f4a60f744c946a.1d2d6ffef252f11e.15b7269093d279f8
+ 3e2bf9cc744c946a.0f8c99dd5595f621.f252f11e93d279f8.6c9756cf983d3fd9
+ 4bd0c53178f4a60f.5c8d02bff74498b6.1d2d6ffe15b72690.1bf02813c432bcef
+ dfc22a71f44cae8d.0a79f5925a6e11ea.62ef484381456cec.7d8d0790e35d724e
+ 6e3a6e3411ca1d21
+VUNPCKHPS_256(mem)
+ before
+ cac3d9e96b867895.584d24f884dfe791.f51aef429b211ce8.1de47858740985b7
+ 6cf3c49d0d9c40d5.10bdb032c5398fc6.f83d6bb9d56876dd.aa57fcab898eae9e
+ 3298ab3b1218300f.655dc88b53e7dfd9.f1aee4e42550dbf4.6596cfa85d61224d
+ f77c0baf9607066c.b17a6a6fc9741675.bb39d9afa6e4075a.aaebedb98b0d1e6f
+ d5a3524bb01edeb1
+ after
+ cac3d9e96b867895.584d24f884dfe791.f51aef429b211ce8.1de47858740985b7
+ 6cf3c49d0d9c40d5.10bdb032c5398fc6.f83d6bb9d56876dd.aa57fcab898eae9e
+ cac3d9e96cf3c49d.6b8678950d9c40d5.f51aef42f83d6bb9.9b211ce8d56876dd
+ f77c0baf9607066c.b17a6a6fc9741675.bb39d9afa6e4075a.aaebedb98b0d1e6f
+ d5a3524bb01edeb1
+
+VUNPCKHPS_256(reg)
+ before
+ 420afacb67209ebe.976c5fe5b6747c1b.5160924ac36c6e47.32aac3077531b53b
+ 4d6ce2a34ca09943.ed3423c98d6b4f46.a25b3a89de5c24fb.31cd1fd6ad41a2c2
+ 51150441fc290cec.d7a0d44738f93a19.feb76096b5cf743c.966d6a0a6a228a1c
+ ac505e0f13483364.307cec4bd229fbc1.c2c0ffdfe5519ab7.3c571f8ec9e02874
+ fe57ba4ee68539f7
+ after
+ 511504414d6ce2a3.fc290cec4ca09943.feb76096a25b3a89.b5cf743cde5c24fb
+ 4d6ce2a34ca09943.ed3423c98d6b4f46.a25b3a89de5c24fb.31cd1fd6ad41a2c2
+ 51150441fc290cec.d7a0d44738f93a19.feb76096b5cf743c.966d6a0a6a228a1c
+ ac505e0f13483364.307cec4bd229fbc1.c2c0ffdfe5519ab7.3c571f8ec9e02874
+ fe57ba4ee68539f7
+VUNPCKHPS_256(mem)
+ before
+ ba39b835dc1f79d0.b96bec7b2c884a58.d393e9c278074c6a.4bc113cf096fd118
+ 4bc99331c7baa42c.d4b0a8f0e3758c73.9eb3469645a0e93f.f30798d2beb4560a
+ 8cd3c92ec4617537.586c90dad59b3662.6ba67fb556ff906d.17de8b549fac6439
+ 5b22d516ee20a91c.a3eb9fa59d8784d0.18391109c630fb20.1392e6c149e43952
+ 436fa78557e70f01
+ after
+ ba39b835dc1f79d0.b96bec7b2c884a58.d393e9c278074c6a.4bc113cf096fd118
+ 4bc99331c7baa42c.d4b0a8f0e3758c73.9eb3469645a0e93f.f30798d2beb4560a
+ ba39b8354bc99331.dc1f79d0c7baa42c.d393e9c29eb34696.78074c6a45a0e93f
+ 5b22d516ee20a91c.a3eb9fa59d8784d0.18391109c630fb20.1392e6c149e43952
+ 436fa78557e70f01
+
+VUNPCKHPS_256(reg)
+ before
+ 03c1ca0c654122f2.928433d66203fc08.1079d1bdd8c4b16a.7f387680b140e783
+ afd349c2107fb0d0.0ec3605b3b172927.fa61228e21dffadc.7e6f2c05343a0fc2
+ a3f32214f42cf347.acacd78f9667eda4.bff18e8515639bd1.efa9ae846b2b310b
+ 3b6b506cacd52804.460b14608e0004ab.b973120c4fdcd0f6.b0b479e9711d0788
+ 9b5a0720621f4d65
+ after
+ a3f32214afd349c2.f42cf347107fb0d0.bff18e85fa61228e.15639bd121dffadc
+ afd349c2107fb0d0.0ec3605b3b172927.fa61228e21dffadc.7e6f2c05343a0fc2
+ a3f32214f42cf347.acacd78f9667eda4.bff18e8515639bd1.efa9ae846b2b310b
+ 3b6b506cacd52804.460b14608e0004ab.b973120c4fdcd0f6.b0b479e9711d0788
+ 9b5a0720621f4d65
+VUNPCKHPS_256(mem)
+ before
+ 8d68d6155b3ac1cf.d388cf38d4048bb3.baab93b840ec2a6a.4634a9916cd7d4f7
+ 63aa61b5787c1df2.c7969be209475700.e25ad085c7391a0b.c0804f7e07dfe47f
+ f7ec24ead4f01ef9.73e1b0d8e62ac996.9be248b240f391ba.85a30141bd803c3b
+ 26fa9ba28ba37f11.33b40b8508381d21.c111762bc6254ba4.efe9b945294717d6
+ 5b9d75f6e8bfb2fd
+ after
+ 8d68d6155b3ac1cf.d388cf38d4048bb3.baab93b840ec2a6a.4634a9916cd7d4f7
+ 63aa61b5787c1df2.c7969be209475700.e25ad085c7391a0b.c0804f7e07dfe47f
+ 8d68d61563aa61b5.5b3ac1cf787c1df2.baab93b8e25ad085.40ec2a6ac7391a0b
+ 26fa9ba28ba37f11.33b40b8508381d21.c111762bc6254ba4.efe9b945294717d6
+ 5b9d75f6e8bfb2fd
+
+VXORPD_256(reg)
+ before
+ 260c30c09574495b.cc9f43c7baa0fe65.635da7550bfd8e4e.31b1d6dc76db03f5
+ aa83e70fccf3189d.c6a897477cf35522.5f2680b489055ac9.c58fe4b16b2276d8
+ 444c944f2ac75a6f.eee2130deea84174.835c930e21ddbb3d.5a761c96c104607a
+ 50b335ec4b7c4c7c.211733052bcc7d86.2a4bdacf6c10ed57.cc34fb7895907d06
+ f793fc4103cf88a9
+ after
+ eecf7340e63442f2.284a844a925b1456.dc7a13baa8d8e1f4.9ff9f827aa2616a2
+ aa83e70fccf3189d.c6a897477cf35522.5f2680b489055ac9.c58fe4b16b2276d8
+ 444c944f2ac75a6f.eee2130deea84174.835c930e21ddbb3d.5a761c96c104607a
+ 50b335ec4b7c4c7c.211733052bcc7d86.2a4bdacf6c10ed57.cc34fb7895907d06
+ f793fc4103cf88a9
+VXORPD_256(mem)
+ before
+ b7619bdf25cf3e8f.2b06c553c99f2a71.3b14741b506ac685.b23f5364082b2ec3
+ e868543c1a9b5be3.2f9040ee43bb2ff9.18a4513b788fd89c.7683f93791b9b82c
+ 6675a446fc409bd2.b99ca22b535c98c1.94954651bf466ff8.d165c9b5a246c83f
+ 0d5406e8e7c9b987.2577e874950fa175.8bb1cf49429b46c5.212fbd4bd85f99a7
+ c12ed364ce8f6911
+ after
+ b7619bdf25cf3e8f.2b06c553c99f2a71.3b14741b506ac685.b23f5364082b2ec3
+ e868543c1a9b5be3.2f9040ee43bb2ff9.18a4513b788fd89c.7683f93791b9b82c
+ 5f09cfe33f54656c.049685bd8a240588.23b0252028e51e19.c4bcaa53999296ef
+ 0d5406e8e7c9b987.2577e874950fa175.8bb1cf49429b46c5.212fbd4bd85f99a7
+ c12ed364ce8f6911
+
+VXORPD_256(reg)
+ before
+ 0cae066c20627228.b9d0f60ef842722f.cf6d0d37a65f86c0.d9c5680f1d9b1a2e
+ 60fb52ce6b64f099.46b7f0a44ab881f6.13ca0ddf21d8824f.5a9e8e906b51a760
+ 1761b3f84b222110.90d37096fa36a407.4ddae4d8a307d2cd.ea05bcb649c9a986
+ 8f2b26565b283f38.73f1f3d023c8958f.d9e98f8ec777b2e7.65c96e6fd110dbcd
+ a6b520a62231fa61
+ after
+ 779ae1362046d189.d6648032b08e25f1.5e10e90782df5082.b09b322622980ee6
+ 60fb52ce6b64f099.46b7f0a44ab881f6.13ca0ddf21d8824f.5a9e8e906b51a760
+ 1761b3f84b222110.90d37096fa36a407.4ddae4d8a307d2cd.ea05bcb649c9a986
+ 8f2b26565b283f38.73f1f3d023c8958f.d9e98f8ec777b2e7.65c96e6fd110dbcd
+ a6b520a62231fa61
+VXORPD_256(mem)
+ before
+ 8b944e465638c16d.22a7a652370087be.cbddf43ee27b11b9.1342086d2ab55e49
+ ef34753d8932ee1e.2d1f2f597c38344e.7463efcc525ad3b2.57324de1674b119e
+ ae5f1076d82a3b9f.0de0bdd7c55b8493.494f60678f7199a5.010659561ac80893
+ a3e29bdd5e2c651d.1c364c39aff6b139.286dc4f9b6cd1cbf.6d082939e1b57fd3
+ f684b7f455a0b10b
+ after
+ 8b944e465638c16d.22a7a652370087be.cbddf43ee27b11b9.1342086d2ab55e49
+ ef34753d8932ee1e.2d1f2f597c38344e.7463efcc525ad3b2.57324de1674b119e
+ 64a03b7bdf0a2f73.0fb8890b4b38b3f0.bfbe1bf2b021c20b.4470458c4dfe4fd7
+ a3e29bdd5e2c651d.1c364c39aff6b139.286dc4f9b6cd1cbf.6d082939e1b57fd3
+ f684b7f455a0b10b
+
+VXORPD_256(reg)
+ before
+ fac801f51414dbe7.ac89925f384527c3.b76dd9e9d694f7ee.ec889570e3791b2c
+ d41f02a7ba9e3912.a41f72e681803fbe.3bd05f55d4c1945c.706d51b731815118
+ e0d4b675e2c80639.6672b65f56e9673a.02addae8470ac22f.92e874babcf279ad
+ 79341acd28218007.d04cdab7d28d5b62.694e460dcbfabe14.2dc57865a1d7501a
+ 1cd0dba4fc3c9189
+ after
+ 34cbb4d258563f2b.c26dc4b9d7695884.397d85bd93cb5673.e285250d8d7328b5
+ d41f02a7ba9e3912.a41f72e681803fbe.3bd05f55d4c1945c.706d51b731815118
+ e0d4b675e2c80639.6672b65f56e9673a.02addae8470ac22f.92e874babcf279ad
+ 79341acd28218007.d04cdab7d28d5b62.694e460dcbfabe14.2dc57865a1d7501a
+ 1cd0dba4fc3c9189
+VXORPD_256(mem)
+ before
+ 3dd51763e82ef927.fd8b281a2932e129.bd7a5ad81277d963.cc00a032fb1ec3b7
+ 6a9fab8e81b8441f.c725dec88089654a.08c9b2b031b39b69.870fe3c274000fc3
+ 81fc1011e4e72e9e.324e3743cab14a17.8f025f2a4c4e5e9f.f7c70b29d12edce5
+ 5cb6c3d92cc673cf.9c5230f8a237ca3c.2cf4dc327e53dd32.767414d4af3467c8
+ 6161fa2da99ceb19
+ after
+ 3dd51763e82ef927.fd8b281a2932e129.bd7a5ad81277d963.cc00a032fb1ec3b7
+ 6a9fab8e81b8441f.c725dec88089654a.08c9b2b031b39b69.870fe3c274000fc3
+ 574abced6996bd38.3aaef6d2a9bb8463.b5b3e86823c4420a.4b0f43f08f1ecc74
+ 5cb6c3d92cc673cf.9c5230f8a237ca3c.2cf4dc327e53dd32.767414d4af3467c8
+ 6161fa2da99ceb19
+
+VBROADCASTSD_256(reg)
+ before
+ 14dcbaa15bf5a584.d89a41d07661cedf.5f7cc351a5a62264.bc6aa5b4e3cfd64d
+ eb2f4f9d62c8d1b4.d27405e4ddc4fcfa.d919eebb6e8a8d3c.1c2f369c98cd031d
+ 42a7b58b5aa3ab56.240f8bff7efcb84b.6475aca39a704970.26110cd6b95920cd
+ 7590e8d9dd116e15.ab394f0f7414bfff.5edcf974c4e390ab.b7daa24e607feb8a
+ ac5774f0ac4c1e80
+ after
+ 14dcbaa15bf5a584.d89a41d07661cedf.5f7cc351a5a62264.bc6aa5b4e3cfd64d
+ eb2f4f9d62c8d1b4.d27405e4ddc4fcfa.d919eebb6e8a8d3c.1c2f369c98cd031d
+ 42a7b58b5aa3ab56.240f8bff7efcb84b.6475aca39a704970.26110cd6b95920cd
+ 7590e8d9dd116e15.ab394f0f7414bfff.5edcf974c4e390ab.b7daa24e607feb8a
+ ac5774f0ac4c1e80
+VBROADCASTSD_256(mem)
+ before
+ df53fea9b7cb76da.e035e5f28a9e579e.44bcceffdc19ce42.219ad199896f9e9a
+ 2d9cbc639d09aec5.dee4a642fbd7a29d.c96683bbd1159e3f.0bfb318084a1b1e8
+ 72fd2b0c7b11846c.cde72935cc478bbd.1701ea2f6f17ee22.764a149451040342
+ 8b41c68e6cefb2fc.088c69379a7b4daa.0a5a7f47d3287819.bfd576418e24d153
+ 43e653f3d48e56c8
+ after
+ df53fea9b7cb76da.e035e5f28a9e579e.44bcceffdc19ce42.219ad199896f9e9a
+ 219ad199896f9e9a.219ad199896f9e9a.219ad199896f9e9a.219ad199896f9e9a
+ 72fd2b0c7b11846c.cde72935cc478bbd.1701ea2f6f17ee22.764a149451040342
+ 8b41c68e6cefb2fc.088c69379a7b4daa.0a5a7f47d3287819.bfd576418e24d153
+ 43e653f3d48e56c8
+
+VBROADCASTSD_256(reg)
+ before
+ 5ccaa816c1cdd04d.523509d78daff5a1.eb1d63b400fe2512.7f3cbfef1956f94d
+ 67cd6f17f06d798d.a4a570d2f95e0886.d2e711189b5c4f9f.507524145cac2ced
+ c03aa660fefb8e35.5d5d786bcd08a8d8.183571cf062106fd.5acf2ca0b837cf23
+ c45f495e87024af0.59299b8e24b791c2.1b557e46deda87d9.791852814a029c1b
+ 891a13a12e195003
+ after
+ 5ccaa816c1cdd04d.523509d78daff5a1.eb1d63b400fe2512.7f3cbfef1956f94d
+ 67cd6f17f06d798d.a4a570d2f95e0886.d2e711189b5c4f9f.507524145cac2ced
+ c03aa660fefb8e35.5d5d786bcd08a8d8.183571cf062106fd.5acf2ca0b837cf23
+ c45f495e87024af0.59299b8e24b791c2.1b557e46deda87d9.791852814a029c1b
+ 891a13a12e195003
+VBROADCASTSD_256(mem)
+ before
+ 66a2e9ee7e89a604.cd86527e260eea6b.74d457271b797f71.369235e7be120edf
+ ec7c5253595d5b4d.38fdbf2b77acaa52.8a2c2823cd592d11.c43790204256d6ba
+ f773c9bcd8a12b08.610e8ad01767c650.77fb886c566458cd.23918d5c07311d17
+ 6355ca151a62d261.a406b1dba1cb7912.170ef5efd3a5bcd2.adec2706a92f1da2
+ c0945a8cc3dd1206
+ after
+ 66a2e9ee7e89a604.cd86527e260eea6b.74d457271b797f71.369235e7be120edf
+ 369235e7be120edf.369235e7be120edf.369235e7be120edf.369235e7be120edf
+ f773c9bcd8a12b08.610e8ad01767c650.77fb886c566458cd.23918d5c07311d17
+ 6355ca151a62d261.a406b1dba1cb7912.170ef5efd3a5bcd2.adec2706a92f1da2
+ c0945a8cc3dd1206
+
+VBROADCASTSD_256(reg)
+ before
+ b6d52259f1c63af0.0cecd24a38aa0b85.5d3030b7b2650043.4631e9996028154b
+ edfa7cd9d076cf0b.cd055b47518893a0.e8da01d0e5c09790.e030e25518fa1e65
+ bf516379fc7a0e04.846ce3f87e0526de.a14e2292d76979a5.c0d65c0e1726944c
+ 8a24d3a3105d3286.0cede54add2f806a.e4da8e6a23eae42d.c4f1d1b27ab8322b
+ c74bbf2c5cbdb62f
+ after
+ b6d52259f1c63af0.0cecd24a38aa0b85.5d3030b7b2650043.4631e9996028154b
+ edfa7cd9d076cf0b.cd055b47518893a0.e8da01d0e5c09790.e030e25518fa1e65
+ bf516379fc7a0e04.846ce3f87e0526de.a14e2292d76979a5.c0d65c0e1726944c
+ 8a24d3a3105d3286.0cede54add2f806a.e4da8e6a23eae42d.c4f1d1b27ab8322b
+ c74bbf2c5cbdb62f
+VBROADCASTSD_256(mem)
+ before
+ a5b1a168da40da83.a8c0c8c4a8ab793e.4154de278a125c70.0dc841c265d212d5
+ 3aeff3520f4d5b54.76713e4961f11dd8.ff6d487da0b9771d.776537073aaa3f48
+ 61d131d618f1f4ce.5182329cd6ba5bff.2103a1363c308d9d.80fd6da63e00a933
+ f823d8e11037631c.93419f2ba4926e60.85e364407983591b.83dbde090c5f8a42
+ dc4d869e40541f20
+ after
+ a5b1a168da40da83.a8c0c8c4a8ab793e.4154de278a125c70.0dc841c265d212d5
+ 0dc841c265d212d5.0dc841c265d212d5.0dc841c265d212d5.0dc841c265d212d5
+ 61d131d618f1f4ce.5182329cd6ba5bff.2103a1363c308d9d.80fd6da63e00a933
+ f823d8e11037631c.93419f2ba4926e60.85e364407983591b.83dbde090c5f8a42
+ dc4d869e40541f20
+
+VCMPPD_128_0x4(reg)
+ before
+ e79d61d07769a37a.d9b0635d142b626a.99f98160660693a6.06d90d8673bf98c4
+ ff196b0b4d2d53fb.e2464e373fdaade6.bff5d4a9b9a1067e.7fb118f447ef06c4
+ 820ba1bb5d296b50.eeaf155cae4f02ba.6282957138ef0394.ce370276111f5f46
+ cbbffe4c43eb2724.d8b834b77c971b12.dcecbf247f7dc593.cd3746f8eb5c5e76
+ 5a7c6066f4b1c082
+ after
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ ff196b0b4d2d53fb.e2464e373fdaade6.bff5d4a9b9a1067e.7fb118f447ef06c4
+ 820ba1bb5d296b50.eeaf155cae4f02ba.6282957138ef0394.ce370276111f5f46
+ cbbffe4c43eb2724.d8b834b77c971b12.dcecbf247f7dc593.cd3746f8eb5c5e76
+ 5a7c6066f4b1c082
+VCMPPD_128_0x4(mem)
+ before
+ 4fd4ccac462a4194.35837e2a9cfec324.7e2d2833c6bcb51b.8a7f4e2e2bd68928
+ 8a0907b7fdd49cd8.1ea21dc103ef7afc.bada6cbea7cd8b01.c8863efcd8868bff
+ e5e88b7136ba8e7b.e067d87d15498957.698a7c433bd35bef.f24f8bf8211a06c3
+ 3d3dd6c80ce9d3a9.d920a9cb6d982be2.680bd4ae9fdcdf12.6424328fa31d3820
+ 7a522e2ef91b5bc3
+ after
+ 4fd4ccac462a4194.35837e2a9cfec324.7e2d2833c6bcb51b.8a7f4e2e2bd68928
+ 8a0907b7fdd49cd8.1ea21dc103ef7afc.bada6cbea7cd8b01.c8863efcd8868bff
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 3d3dd6c80ce9d3a9.d920a9cb6d982be2.680bd4ae9fdcdf12.6424328fa31d3820
+ 7a522e2ef91b5bc3
+
+VCMPPD_128_0x4(reg)
+ before
+ 90267b3fbfa1ab58.6fd363a69c6c278d.63178e15a8699d49.9127f1ebeff3d395
+ 02e91530923a668a.5578aff9014f4554.dc9983c961471b37.c2ab4ee74624f5a5
+ 2ceaf96c0d73c606.ccf634ac579eea29.9ef1825235bee158.d563678cc07cff6e
+ 6a74215fcdd70778.b11b70abbb66d239.076d891bbf5a2b5a.a71bb8c77a06ae1b
+ 149fbd858fcfbdd9
+ after
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 02e91530923a668a.5578aff9014f4554.dc9983c961471b37.c2ab4ee74624f5a5
+ 2ceaf96c0d73c606.ccf634ac579eea29.9ef1825235bee158.d563678cc07cff6e
+ 6a74215fcdd70778.b11b70abbb66d239.076d891bbf5a2b5a.a71bb8c77a06ae1b
+ 149fbd858fcfbdd9
+VCMPPD_128_0x4(mem)
+ before
+ f9baf3b01ce2ead4.18d28b746df2678b.deb1dee249b2b8b0.715893929ba834e7
+ 3039d5363c4bef37.9151331a8a5020ec.3085fb3d1c8f59b9.39fd9c22663439ab
+ 96e9df020c17892e.333d13babf7e6f46.836241a851087181.bba9a037bc887553
+ 07948d00a75073e6.59e229c1a9079046.b3162e100229bc34.54a89b3e3832268b
+ 5e468aa176be86fe
+ after
+ f9baf3b01ce2ead4.18d28b746df2678b.deb1dee249b2b8b0.715893929ba834e7
+ 3039d5363c4bef37.9151331a8a5020ec.3085fb3d1c8f59b9.39fd9c22663439ab
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 07948d00a75073e6.59e229c1a9079046.b3162e100229bc34.54a89b3e3832268b
+ 5e468aa176be86fe
+
+VCMPPD_128_0x4(reg)
+ before
+ 36cf68cd13b7d159.5f075c1c2a056a8b.5f8c6f9be378be98.9c6b3d5f4efff5fd
+ 388e312faba94547.7a0dc642b03f2a49.a087e3b50a5c36e7.1a2fea834f94d908
+ c0d1e231d9201c75.3474495e560c6f4b.7a1e8179b93f34e0.092cb16621f72482
+ 2be2754139a9938f.6906605c3777f4bd.489f43558dadf42e.452f0ff6e1319297
+ aa047e1eaa50de72
+ after
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 388e312faba94547.7a0dc642b03f2a49.a087e3b50a5c36e7.1a2fea834f94d908
+ c0d1e231d9201c75.3474495e560c6f4b.7a1e8179b93f34e0.092cb16621f72482
+ 2be2754139a9938f.6906605c3777f4bd.489f43558dadf42e.452f0ff6e1319297
+ aa047e1eaa50de72
+VCMPPD_128_0x4(mem)
+ before
+ 14767cca9960c540.d30ee8ca68cfe640.f59188296f8d76cc.655427b32133b17e
+ 5f5385e6c96b022d.15a13638011e5035.b4df3baf1b59b1a4.2f8a2801115da87b
+ 6765135e577f5364.4de75bf6a1230e19.82bdf7db57e76171.008d42aafab515d2
+ 0879a41e5ea77212.d72b5473e3695c99.3bf6379a3e44415d.36a8711a78c9332f
+ 2b29b2bd26243f3d
+ after
+ 14767cca9960c540.d30ee8ca68cfe640.f59188296f8d76cc.655427b32133b17e
+ 5f5385e6c96b022d.15a13638011e5035.b4df3baf1b59b1a4.2f8a2801115da87b
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 0879a41e5ea77212.d72b5473e3695c99.3bf6379a3e44415d.36a8711a78c9332f
+ 2b29b2bd26243f3d
+
+VCVTDQ2PD_128(reg)
+ before
+ 3d5a00ffa05375a9.1e5bb312fbf01c62.0fbb1b18647d7561.bb5878d7ec7b0e97
+ c689574d83e1111f.85d7bc2749650c81.51e1ae52bfe9961c.ddad347e7e988349
+ 2300b3116a5a4e4a.18b93b476512009b.f8ea088d903bfb77.7fc3e97b10a85ea0
+ b10b10b8f24b69d6.b5cdac606a04b1db.6222263674ffe01d.7c6412babcb659c7
+ b05d2b27a1ce31eb
+ after
+ 3d5a00ffa05375a9.1e5bb312fbf01c62.0fbb1b18647d7561.bb5878d7ec7b0e97
+ 0000000000000000.0000000000000000.41dff0fa5ec00000.41b0a85ea0000000
+ 2300b3116a5a4e4a.18b93b476512009b.f8ea088d903bfb77.7fc3e97b10a85ea0
+ b10b10b8f24b69d6.b5cdac606a04b1db.6222263674ffe01d.7c6412babcb659c7
+ b05d2b27a1ce31eb
+VCVTDQ2PD_128(mem)
+ before
+ f67ab0aed8fda138.caf86bafb63f9e71.37de8c5c7446de6e.ead502b707c080bb
+ 2c861e3b804e67d9.cb12bf6153c228c4.79b95629a0e5427f.ec4f9a7ee40a19fd
+ 2c4ff0bbb2ce3dfb.11a408396461447e.592a86b20aeb983b.c4dbe9f5a769e48e
+ d49fa2188d87dfc9.f6fc42a586a72e49.b2fd99e3cd669dcd.cdc7eb8aed6a201a
+ 655d9da85298074f
+ after
+ f67ab0aed8fda138.caf86bafb63f9e71.37de8c5c7446de6e.ead502b707c080bb
+ 0000000000000000.0000000000000000.c1b52afd49000000.419f0202ec000000
+ 2c4ff0bbb2ce3dfb.11a408396461447e.592a86b20aeb983b.c4dbe9f5a769e48e
+ d49fa2188d87dfc9.f6fc42a586a72e49.b2fd99e3cd669dcd.cdc7eb8aed6a201a
+ 655d9da85298074f
+
+VCVTDQ2PD_128(reg)
+ before
+ e7eafabb7180d6d7.ff44b0402a870b70.d7646a10542022d2.5ffe09a805620c62
+ aebafd2fe6adc95e.8808961da7da7b1b.10297be66b595bc4.3ef954edcfeaa226
+ 1818a4704eab1b91.4db8d19d208becf7.fd97719366dd16cc.29b9f59e460a1b44
+ 8052ebea4407091c.281fdcabb0a61930.faf94883e1398f95.fe0c69a787ce33e9
+ 97bc2af5ae43a641
+ after
+ e7eafabb7180d6d7.ff44b0402a870b70.d7646a10542022d2.5ffe09a805620c62
+ 0000000000000000.0000000000000000.41c4dcfacf000000.41d18286d1000000
+ 1818a4704eab1b91.4db8d19d208becf7.fd97719366dd16cc.29b9f59e460a1b44
+ 8052ebea4407091c.281fdcabb0a61930.faf94883e1398f95.fe0c69a787ce33e9
+ 97bc2af5ae43a641
+VCVTDQ2PD_128(mem)
+ before
+ d296b672d5742f77.41b3cc0a654ccfaa.f60b33337337c0f1.639dfc2379f702cc
+ 8966880c1a6d8bb8.b986453a4c06a9e8.94465221864b9b67.94cd8addcaa5aa1d
+ 99f71cae993b752f.421851e896c2d282.dc9eb66105ed66be.e9d6ed1f6fcfc433
+ df17ee436de9aa09.3ab5ec7ede0a8723.acddd9df0b2adf21.be04215304008bbb
+ 6fa322e726c43d60
+ after
+ d296b672d5742f77.41b3cc0a654ccfaa.f60b33337337c0f1.639dfc2379f702cc
+ 0000000000000000.0000000000000000.41d8e77f08c00000.41de7dc0b3000000
+ 99f71cae993b752f.421851e896c2d282.dc9eb66105ed66be.e9d6ed1f6fcfc433
+ df17ee436de9aa09.3ab5ec7ede0a8723.acddd9df0b2adf21.be04215304008bbb
+ 6fa322e726c43d60
+
+VCVTDQ2PD_128(reg)
+ before
+ 58ffed4671a714cf.35907bb9b384e771.fba9136ac16d0477.ded03987b40cc0bc
+ d5637ddb7f364db3.78303efb8617e594.e23fc017da74842c.4f4252461da2c6bd
+ 421dce14effc23ba.84c1b3f503ae639e.4cc5f1f1c5ad44ec.db019e0661f5ac4d
+ fb77dc5c5b86d38d.3610569345561bba.9385a1641fa48063.5fd89bb59d13309b
+ b592c43eed070cd1
+ after
+ 58ffed4671a714cf.35907bb9b384e771.fba9136ac16d0477.ded03987b40cc0bc
+ 0000000000000000.0000000000000000.c1c27f30fd000000.41d87d6b13400000
+ 421dce14effc23ba.84c1b3f503ae639e.4cc5f1f1c5ad44ec.db019e0661f5ac4d
+ fb77dc5c5b86d38d.3610569345561bba.9385a1641fa48063.5fd89bb59d13309b
+ b592c43eed070cd1
+VCVTDQ2PD_128(mem)
+ before
+ bafc958c6bdefd1b.5bbea3205f5e99db.68e8a3c26819ca15.14ccccdc84e3743e
+ 4ae28a8d35a3bea7.c03e20ca9813b14e.f717176c89062bda.2ce66fc58ff85b29
+ 41101f2c67620c9e.85434ec7a12e5692.bf672d7ec426fc36.351f858bdc6f72cf
+ 7b52d1551c27a32f.06192983163dc654.9ca661e53487f755.8cc30a9b08d2f5dd
+ 8d1dfa5fafaf20fe
+ after
+ bafc958c6bdefd1b.5bbea3205f5e99db.68e8a3c26819ca15.14ccccdc84e3743e
+ 0000000000000000.0000000000000000.41b4ccccdc000000.c1dec722f0800000
+ 41101f2c67620c9e.85434ec7a12e5692.bf672d7ec426fc36.351f858bdc6f72cf
+ 7b52d1551c27a32f.06192983163dc654.9ca661e53487f755.8cc30a9b08d2f5dd
+ 8d1dfa5fafaf20fe
+
+VDIVPD_128(reg)
+ before
+ 947b51456b922edf.d4731bf471ff3f84.9e0bad6b95cb3a40.6a9e2f8bf534d962
+ fd270cb7db065c2c.284179f681f69bc9.ab66d6eab765f101.051c145e243a5d8a
+ 246e26239997e590.538668456916742c.8777a16b1a962544.49ec8b49dca440f8
+ 659c9bf441d107b8.310f62cf446d86d6.9088095c5aea13b5.12d910383a7e3ed9
+ 3cb11f1759d51359
+ after
+ 0000000000000000.0000000000000000.63deedc6cbbfb654.0000000000000000
+ fd270cb7db065c2c.284179f681f69bc9.ab66d6eab765f101.051c145e243a5d8a
+ 246e26239997e590.538668456916742c.8777a16b1a962544.49ec8b49dca440f8
+ 659c9bf441d107b8.310f62cf446d86d6.9088095c5aea13b5.12d910383a7e3ed9
+ 3cb11f1759d51359
+VDIVPD_128(mem)
+ before
+ a33e34d256b47aa3.1dfd67967041fc4f.9ea8e57e2e068df6.21e50a2812eef7ff
+ 234dcc554c2730e4.a5dd8675c1720002.761d6c4044ee44b6.95dca03bde2c0ccf
+ 97aa628c583bf147.5c87f5fdd0f0517d.953973ffa1306842.49b8c8015b3390d0
+ dd21726495fb79f9.9d48af9a3b48296b.d6ca77a962d8b4c7.9ac47de6248cbcaf
+ e24dbb56d6c5cf17
+ after
+ a33e34d256b47aa3.1dfd67967041fc4f.9ea8e57e2e068df6.21e50a2812eef7ff
+ 234dcc554c2730e4.a5dd8675c1720002.761d6c4044ee44b6.95dca03bde2c0ccf
+ 0000000000000000.0000000000000000.fff0000000000000.b3e5c4e344af7b24
+ dd21726495fb79f9.9d48af9a3b48296b.d6ca77a962d8b4c7.9ac47de6248cbcaf
+ e24dbb56d6c5cf17
+
+VDIVPD_128(reg)
+ before
+ 7f9f7ebe0d6a03b5.d07e78c71f738325.c46cb0b89b05c579.179af329a3f3e671
+ cb06c38864059535.4c8df1a313b0ccf9.2d3ff4c48eb46152.3376636b7f8cb86b
+ 23ce84227724c142.2c1958e28dbd109e.340d7828b0e038a3.062a435b12b0e7e2
+ e443bff6e353c289.4eef2972a8a60a43.352237529c158718.6b820fe579692e02
+ 404a44f6cfc54bf6
+ after
+ 0000000000000000.0000000000000000.392159a36411c6b7.6d3b4762f2ff8097
+ cb06c38864059535.4c8df1a313b0ccf9.2d3ff4c48eb46152.3376636b7f8cb86b
+ 23ce84227724c142.2c1958e28dbd109e.340d7828b0e038a3.062a435b12b0e7e2
+ e443bff6e353c289.4eef2972a8a60a43.352237529c158718.6b820fe579692e02
+ 404a44f6cfc54bf6
+VDIVPD_128(mem)
+ before
+ 604d5c7831d0f8eb.68b06f72431cd6b5.8ddbe03e81787712.8bc92dadeedf8a5c
+ a659d559ba94f10c.0c629101330d3773.c4a9f932323e1337.945056a443cb7d1b
+ f0382b83861ff486.2ca51f0f51b2216f.d125f13ada049adf.ab01aea537649b03
+ 18b7d8e4b27dbb84.24c517083695d254.8e1b434293d7c736.2c29321b653721be
+ 7214dd7269cf4bf8
+ after
+ 604d5c7831d0f8eb.68b06f72431cd6b5.8ddbe03e81787712.8bc92dadeedf8a5c
+ a659d559ba94f10c.0c629101330d3773.c4a9f932323e1337.945056a443cb7d1b
+ 0000000000000000.0000000000000000.76bdd0e58be7dbd1.4874c3d709c496fb
+ 18b7d8e4b27dbb84.24c517083695d254.8e1b434293d7c736.2c29321b653721be
+ 7214dd7269cf4bf8
+
+VDIVPD_128(reg)
+ before
+ db0eab16e0b8545e.fca25a675ab90334.500e7458804584cf.d9566b3679c25767
+ c1629874657f799c.76c52cf799df87bf.0dcc326bcb4b738b.8ca4e502a9d2069f
+ 825ea1f695aff65d.64ebca828cfb0553.b54a4eadb235dd35.85cf2d933e118f0a
+ 784cc1090bd4074e.a0e2b0f34e1a371c.a5d6c28bd18efc79.9ea4c0d3558eafd3
+ b4ef19b009522226
+ after
+ 0000000000000000.0000000000000000.98712635c0ac663f.46c57207e054505a
+ c1629874657f799c.76c52cf799df87bf.0dcc326bcb4b738b.8ca4e502a9d2069f
+ 825ea1f695aff65d.64ebca828cfb0553.b54a4eadb235dd35.85cf2d933e118f0a
+ 784cc1090bd4074e.a0e2b0f34e1a371c.a5d6c28bd18efc79.9ea4c0d3558eafd3
+ b4ef19b009522226
+VDIVPD_128(mem)
+ before
+ a47bb415776ba431.0179f41a647ae71b.07745b36fb47d946.39ba8c6fc5e20d02
+ 48160eedbae4f01d.773136943b2ed36f.766e4538b08fa9fc.cd43a7c72abe4c7d
+ 7d8aa126efcac319.38c083e22d7c07f6.c79cece388fd616b.bdbd0ffe9badf495
+ 20a5ebab3127d94f.9e72d872d5eebe5e.d7cacc24a09dbebe.6474c17fb43c42f7
+ 20b3b8b812f5724f
+ after
+ a47bb415776ba431.0179f41a647ae71b.07745b36fb47d946.39ba8c6fc5e20d02
+ 48160eedbae4f01d.773136943b2ed36f.766e4538b08fa9fc.cd43a7c72abe4c7d
+ 0000000000000000.0000000000000000.7ff0000000000000.d377b0fda33f2d39
+ 20a5ebab3127d94f.9e72d872d5eebe5e.d7cacc24a09dbebe.6474c17fb43c42f7
+ 20b3b8b812f5724f
+
+VANDPD_256(reg)
+ before
+ 4cc8f0145067bf48.0b3167689c0aedeb.069230afcf123551.82c45fe8147b7b22
+ 44fd65ff0b1b678f.1bfb91494d7cbc1b.cd6d8705b874a87b.a555231afea456c2
+ 649f13e5de9fa4cf.2ccee63b608b0209.4d50d9e02c9e5389.1a4b92a57d2309cb
+ 07faf733667eb2b5.1a78e028f0427be1.e38523acc61e7127.be702b77aa055169
+ 6d91677ba455e9c7
+ after
+ 449d01e50a1b248f.08ca800940080009.4d40810028140009.004102007c2000c2
+ 44fd65ff0b1b678f.1bfb91494d7cbc1b.cd6d8705b874a87b.a555231afea456c2
+ 649f13e5de9fa4cf.2ccee63b608b0209.4d50d9e02c9e5389.1a4b92a57d2309cb
+ 07faf733667eb2b5.1a78e028f0427be1.e38523acc61e7127.be702b77aa055169
+ 6d91677ba455e9c7
+VANDPD_256(mem)
+ before
+ 037ac39d841f8e12.8b5a0c533e45cfed.c1c3fdfd19aee2d0.ec595fd622803f00
+ 5cf6bcc96870fc75.4b0a4eb2037e3522.fe7db8a7f8daf402.c2178bc8dd4ef9c1
+ 54d3cdeb6c53ef1d.a358b9bd50b82100.ab708e10a9d26da2.c20da2ef9316da15
+ c7db72efabd42236.ee8e49dec27cce35.a569f92646a309dd.4885a1b8de641fa9
+ b0cc828e5dc20429
+ after
+ 037ac39d841f8e12.8b5a0c533e45cfed.c1c3fdfd19aee2d0.ec595fd622803f00
+ 5cf6bcc96870fc75.4b0a4eb2037e3522.fe7db8a7f8daf402.c2178bc8dd4ef9c1
+ 0072808900108c10.0b0a0c1202440520.c041b8a5188ae000.c0110bc000003900
+ c7db72efabd42236.ee8e49dec27cce35.a569f92646a309dd.4885a1b8de641fa9
+ b0cc828e5dc20429
+
+VANDPD_256(reg)
+ before
+ 562e43dcaabfc540.91dc28c242ff52eb.8af9fb83f458796b.c83477d4ee5883de
+ 96f7df1061e49d9b.8ea0694e4ce13b69.d1e5ca1782d75e4e.ef9c8306bbfd98d2
+ cc7353951fbfc9e5.9af4b381e58699db.219eb2060986b98b.f86f99a8c99e03e4
+ 54ee99d77fdb85cb.91a381452af8276e.d470b0bc25f0c6ce.be7736a635488242
+ 1d81d4ec1a07cf15
+ after
+ 8473531001a48981.8aa0210044801949.018482060086180a.e80c8100899c00c0
+ 96f7df1061e49d9b.8ea0694e4ce13b69.d1e5ca1782d75e4e.ef9c8306bbfd98d2
+ cc7353951fbfc9e5.9af4b381e58699db.219eb2060986b98b.f86f99a8c99e03e4
+ 54ee99d77fdb85cb.91a381452af8276e.d470b0bc25f0c6ce.be7736a635488242
+ 1d81d4ec1a07cf15
+VANDPD_256(mem)
+ before
+ f159f16694e5a78c.8ab3af421dc40df9.4f7b4f883745a24d.48a6bea571a1c0c2
+ 16cb0801c1f0c5d1.ca10904397079c1a.af469a352779c5a6.d78eda2d8926e414
+ 67a396a7ba34e610.704f3844862f6fdb.8fd2dc38169e4ea2.df72ffc00a0a6d70
+ c2ad15469dbbc676.d8bda3b288c9c2e7.cae9937d21c2f770.ba9f29cb8fd99981
+ c56155b8b520a2f3
+ after
+ f159f16694e5a78c.8ab3af421dc40df9.4f7b4f883745a24d.48a6bea571a1c0c2
+ 16cb0801c1f0c5d1.ca10904397079c1a.af469a352779c5a6.d78eda2d8926e414
+ 1049000080e08580.8a10804215040c18.0f420a0027418004.40869a250120c000
+ c2ad15469dbbc676.d8bda3b288c9c2e7.cae9937d21c2f770.ba9f29cb8fd99981
+ c56155b8b520a2f3
+
+VANDPD_256(reg)
+ before
+ 5d047df5176ac474.02b403c88693212f.5ea6cefa3960d0eb.3c583bf063f17d3a
+ dcd39fec52433dad.0385db1b90c8b366.5e55b3863480d693.c0eb4e7df9359b2c
+ 9f1cb60b0138474d.a0ed192ad7653748.331850c415b5108a.346d4910fe9c0f73
+ 0229bfbdc1d41ffe.b7b539e178766a01.3b39a11f798cb97c.73aca9968f32933b
+ 5872e9f9c702e3af
+ after
+ 9c1096080000050d.0085190a90403340.1210108414801082.00694810f8140b20
+ dcd39fec52433dad.0385db1b90c8b366.5e55b3863480d693.c0eb4e7df9359b2c
+ 9f1cb60b0138474d.a0ed192ad7653748.331850c415b5108a.346d4910fe9c0f73
+ 0229bfbdc1d41ffe.b7b539e178766a01.3b39a11f798cb97c.73aca9968f32933b
+ 5872e9f9c702e3af
+VANDPD_256(mem)
+ before
+ c18d8527c318bdfc.6247b46e2da3006c.22acb82c8f0707bc.d105a003fc900f17
+ 88c7fa0a9e80db4e.19c2938ae2322845.bf9d11f73625cba6.50c84bdc394e4c05
+ 8bedc3907447fad0.84e6577d7b0cd133.6853c02e8cdb72ea.16ce9d16cc51acf2
+ a4ca5ba46278d5ae.fffffcb394bd38e2.fb9c41beab35b8b5.7e63921d52256d8b
+ e3d3265d6657c97c
+ after
+ c18d8527c318bdfc.6247b46e2da3006c.22acb82c8f0707bc.d105a003fc900f17
+ 88c7fa0a9e80db4e.19c2938ae2322845.bf9d11f73625cba6.50c84bdc394e4c05
+ 808580028200994c.0042900a20220044.228c1024060503a4.5000000038000c05
+ a4ca5ba46278d5ae.fffffcb394bd38e2.fb9c41beab35b8b5.7e63921d52256d8b
+ e3d3265d6657c97c
+
+VPMOVSXBW_128(reg)
+ before
+ a3695642a571fd70.b12c4132841f2a16.e6587f98cad298ff.52421191af405932
+ 18721c39aa024414.8cddee26f549b332.953fda99b9d62e36.4b12aa94b507108e
+ a03a76ac1293dc14.12abdf6cd1012c2e.68fe0b20fc563632.c0d88ab4d8979af5
+ 950d5f0978b2ff1b.206091f035545337.bbe20d9b2fdcec9f.8e5f2ddc35fbb292
+ 92750df7e73f1592
+ after
+ a3695642a571fd70.b12c4132841f2a16.e6587f98cad298ff.52421191af405932
+ 0000000000000000.0000000000000000.ffc0ffd8ff8affb4.ffd8ff97ff9afff5
+ a03a76ac1293dc14.12abdf6cd1012c2e.68fe0b20fc563632.c0d88ab4d8979af5
+ 950d5f0978b2ff1b.206091f035545337.bbe20d9b2fdcec9f.8e5f2ddc35fbb292
+ 92750df7e73f1592
+VPMOVSXBW_128(mem)
+ before
+ a6e4a8f30a6f7f21.5537d4bb79ebe9d5.90c97f9f3d4de279.ea37dd74eff68b2b
+ a77a78bbbb98ac6a.3a04d02db0c8d8f0.3fb2256303f8961f.51487519d8305080
+ 7101fb3b16c55899.a1bf4ecdb9d70616.09e6002aa6612a56.4c63d3f58415774a
+ e146ad5f36033edb.e7b64c0631a3b0f3.cb338ade40955c49.36d2f27492313c37
+ 6de3ce029b10daf0
+ after
+ a6e4a8f30a6f7f21.5537d4bb79ebe9d5.90c97f9f3d4de279.ea37dd74eff68b2b
+ 0000000000000000.0000000000000000.ffea0037ffdd0074.ffeffff6ff8b002b
+ 7101fb3b16c55899.a1bf4ecdb9d70616.09e6002aa6612a56.4c63d3f58415774a
+ e146ad5f36033edb.e7b64c0631a3b0f3.cb338ade40955c49.36d2f27492313c37
+ 6de3ce029b10daf0
+
+VPMOVSXBW_128(reg)
+ before
+ 4ce0630b3e3f8e24.d1140814385d1b5c.6633c644b4b91134.5f63416ded9fe625
+ 2f16aefb1449947d.1e398a4437dfaa48.7b83b6f4dda46785.a243a0c2ca8c8516
+ 71d1aa3fbcbb27a7.a47faedc4f95a9ca.82f21a8048f1ec91.709f24c8f267f447
+ 705c5341cf20844f.3fb4f0c99d8cd20e.d8cbed55922add05.a543476d813cf0e5
+ 1dfb879d9518351b
+ after
+ 4ce0630b3e3f8e24.d1140814385d1b5c.6633c644b4b91134.5f63416ded9fe625
+ 0000000000000000.0000000000000000.0070ff9f0024ffc8.fff20067fff40047
+ 71d1aa3fbcbb27a7.a47faedc4f95a9ca.82f21a8048f1ec91.709f24c8f267f447
+ 705c5341cf20844f.3fb4f0c99d8cd20e.d8cbed55922add05.a543476d813cf0e5
+ 1dfb879d9518351b
+VPMOVSXBW_128(mem)
+ before
+ b4925f4247067f16.8705a56feb04e721.cba2ccf63cd0e241.d75c2be056dd758c
+ 46d64b49b5128902.11169d33acf48bc8.2416bf4e496b948f.dcefd08b3196f1d3
+ af91c79efb49100a.6cdc35fbad7baef1.26dc43bfdf6ba524.43d2d9c4bfdf8d86
+ cb90502e34b5d05b.f3a36b328b258a48.adbfd6341bdbd12b.684f41f69a468550
+ a7b3048d615714de
+ after
+ b4925f4247067f16.8705a56feb04e721.cba2ccf63cd0e241.d75c2be056dd758c
+ 0000000000000000.0000000000000000.ffd7005c002bffe0.0056ffdd0075ff8c
+ af91c79efb49100a.6cdc35fbad7baef1.26dc43bfdf6ba524.43d2d9c4bfdf8d86
+ cb90502e34b5d05b.f3a36b328b258a48.adbfd6341bdbd12b.684f41f69a468550
+ a7b3048d615714de
+
+VPMOVSXBW_128(reg)
+ before
+ 5c491ef4ad9d77db.769f61e37c658520.01b73a44e17e5b78.958df49918c8d4d0
+ e35f8c9a1da4eaf4.8c8a76abf062ea86.f4649f9d4b135f2d.ba1017daf33d6940
+ 984048e84af8a8d5.e91d0b71acbabcb9.26f594a96670d015.f815bde3c7464da7
+ d737504bd226ef29.69239d20cb79b6e4.f5b817d4cd1febda.2a6961a0b1f03c30
+ 2ed57ffecc46f208
+ after
+ 5c491ef4ad9d77db.769f61e37c658520.01b73a44e17e5b78.958df49918c8d4d0
+ 0000000000000000.0000000000000000.fff80015ffbdffe3.ffc70046004dffa7
+ 984048e84af8a8d5.e91d0b71acbabcb9.26f594a96670d015.f815bde3c7464da7
+ d737504bd226ef29.69239d20cb79b6e4.f5b817d4cd1febda.2a6961a0b1f03c30
+ 2ed57ffecc46f208
+VPMOVSXBW_128(mem)
+ before
+ df2893e735542a5b.fc919f2f51b9f99d.e769a6a669a99634.bbf7238a1daeeb28
+ 192d1a490727a154.639a3201623e02dc.41bba4eea35816d4.d5ffb437f2a80eac
+ b7af8e0e5eca1320.689e032ba23f4893.52e512e49492f3f1.a01cc748e69a8e12
+ 977b6d24574a3bea.66e9101bac4b056d.f5b36d755962e8b6.769a5627980fa805
+ b4c45f42a1939732
+ after
+ df2893e735542a5b.fc919f2f51b9f99d.e769a6a669a99634.bbf7238a1daeeb28
+ 0000000000000000.0000000000000000.ffbbfff70023ff8a.001dffaeffeb0028
+ b7af8e0e5eca1320.689e032ba23f4893.52e512e49492f3f1.a01cc748e69a8e12
+ 977b6d24574a3bea.66e9101bac4b056d.f5b36d755962e8b6.769a5627980fa805
+ b4c45f42a1939732
+
+VPSUBUSW_128(reg)
+ before
+ b6e8dd04a0b39844.945e32760eb1d6df.bbc6543b1ceb7618.08f12f8b0dd4b350
+ d950cdd92efae7e8.89215af09e0da02b.c282cbf98fadd63d.666bd613cdf40eeb
+ 7749292de9f5c0ca.54935f7e236a55f9.d66a72c0a11c628b.eaecddfab4cfb5b2
+ ed1fef6c6d2e5e95.cf7fbf0cbad2b075.55c843fcecc556ac.7241c02adf7066d2
+ d836fc9169e3db77
+ after
+ 0000000000000000.0000000000000000.6cba87fd00007f91.000015e900000000
+ d950cdd92efae7e8.89215af09e0da02b.c282cbf98fadd63d.666bd613cdf40eeb
+ 7749292de9f5c0ca.54935f7e236a55f9.d66a72c0a11c628b.eaecddfab4cfb5b2
+ ed1fef6c6d2e5e95.cf7fbf0cbad2b075.55c843fcecc556ac.7241c02adf7066d2
+ d836fc9169e3db77
+VPSUBUSW_128(mem)
+ before
+ fa970b1a6e35d1cc.971e1a025533fef6.d8b0f5867e546ecd.9ae93c190f33ee4c
+ b2306bb10b7103fe.d192a65b3e90dc98.49f47ed98cf94b2a.00185883a4f26518
+ decc97425ca42f38.f7c690e3c3cf3328.0015d4ef00cf02bb.e5a394a6478ef9bc
+ 58390cb97cd80fa7.6507d207807f4152.d7e075b6f4e150aa.a4d4eaef9594e3e3
+ 98f958c82990623a
+ after
+ fa970b1a6e35d1cc.971e1a025533fef6.d8b0f5867e546ecd.9ae93c190f33ee4c
+ b2306bb10b7103fe.d192a65b3e90dc98.49f47ed98cf94b2a.00185883a4f26518
+ 0000000000000000.0000000000000000.000000000ea50000.00001c6a95bf0000
+ 58390cb97cd80fa7.6507d207807f4152.d7e075b6f4e150aa.a4d4eaef9594e3e3
+ 98f958c82990623a
+
+VPSUBUSW_128(reg)
+ before
+ 1e5cd99fa00cb06d.fd414402871c5f76.77a26a3112293fc1.ac21dc18873bf124
+ 934a69de95960a27.aab1bd099a79ddd2.89e153cf155b6c22.59a38503d2eaa154
+ 510e05f3a4b9ac14.3955f2bad1fd43e7.f7108a4b24a00220.bb34ec62f3f91b67
+ b6f6a7496b02d2e2.87f95f0247b34ee0.1d7d0913db843f68.af9e8e2006751c88
+ 0fafe62b266960e4
+ after
+ 0000000000000000.0000000000000000.6c644abc00002cba.00000000cc7584cc
+ 934a69de95960a27.aab1bd099a79ddd2.89e153cf155b6c22.59a38503d2eaa154
+ 510e05f3a4b9ac14.3955f2bad1fd43e7.f7108a4b24a00220.bb34ec62f3f91b67
+ b6f6a7496b02d2e2.87f95f0247b34ee0.1d7d0913db843f68.af9e8e2006751c88
+ 0fafe62b266960e4
+VPSUBUSW_128(mem)
+ before
+ b831706e70e1a2a7.1c4d4d4c83fcb73a.716981cb18a8b9ea.5773ce92d7945ca6
+ 86f1a8d6ffe99ffc.e05ef2688a3398cb.d170d20361e64230.013dd434b35b9885
+ 55ba0a4def8e1310.5f7692091c34b03f.84dcd0943d7ca3df.772817650c662db2
+ 015a13c05ddcba0e.f3e12a9bd48a3c43.6677f66cc9739923.148193917d4058d8
+ 36924524a37555a4
+ after
+ b831706e70e1a2a7.1c4d4d4c83fcb73a.716981cb18a8b9ea.5773ce92d7945ca6
+ 86f1a8d6ffe99ffc.e05ef2688a3398cb.d170d20361e64230.013dd434b35b9885
+ 0000000000000000.0000000000000000.60075038493e0000.000005a200003bdf
+ 015a13c05ddcba0e.f3e12a9bd48a3c43.6677f66cc9739923.148193917d4058d8
+ 36924524a37555a4
+
+VPSUBUSW_128(reg)
+ before
+ 38a7288b19915fc2.679b3e1c65dd4f23.f9ebb58a4ec17982.530ec17620d9df27
+ 750e38307c21b3dd.614b074b229f8f7b.cde02f432766a0a9.276dab9e5fb93218
+ 4b11718067b08da1.cc34ea3bb02d3641.cc0b9430fa04f063.be5f32d0a1204e21
+ 15fed0e876cb29bc.842364d62c9400a2.50bae0bf6428a35d.f4b2d1f80219ef6f
+ a5300403a0b0d02e
+ after
+ 0000000000000000.0000000000000000.7d26000000000000.000000005da00000
+ 750e38307c21b3dd.614b074b229f8f7b.cde02f432766a0a9.276dab9e5fb93218
+ 4b11718067b08da1.cc34ea3bb02d3641.cc0b9430fa04f063.be5f32d0a1204e21
+ 15fed0e876cb29bc.842364d62c9400a2.50bae0bf6428a35d.f4b2d1f80219ef6f
+ a5300403a0b0d02e
+VPSUBUSW_128(mem)
+ before
+ ada747db94f2ae89.2e1f4fd346fdc2d8.65e4f00ab1dfa8c9.b637105a015cf643
+ e8e1176dfcea45ad.f4c1ecad73d295a1.4b420ac25c1aebe3.5acf1e6f6b2e24c0
+ 32abefa6f4a451c5.c130a2e198d7dec4.120b2eea4852841c.98ce0869412a6b81
+ 67d04b70972d8dfe.f3b76edd5197d8ed.9509d86e9292319f.cc80cab41cdb0531
+ 52305ebc9bcd2f7d
+ after
+ ada747db94f2ae89.2e1f4fd346fdc2d8.65e4f00ab1dfa8c9.b637105a015cf643
+ e8e1176dfcea45ad.f4c1ecad73d295a1.4b420ac25c1aebe3.5acf1e6f6b2e24c0
+ 0000000000000000.0000000000000000.000000000000431a.00000e1569d20000
+ 67d04b70972d8dfe.f3b76edd5197d8ed.9509d86e9292319f.cc80cab41cdb0531
+ 52305ebc9bcd2f7d
+
+VPSUBSW_128(reg)
+ before
+ 862cc2ed578c2411.631ea7b90190b684.e4a44a0d3b9ec0c7.b209853a55e6ac99
+ c4bef1b3eea52198.0260806c4fd98782.f24134dbf279d2ff.44d8b03bae5bb235
+ 6833e77afca362bf.1f6150759c15be25.77dc27b411b34a41.273fd55bb8fcfea0
+ cdd7a0af1c132331.98ee95c0054f1598.d1bf1f0434d86338.370d70878fd54d06
+ 4f0dfeac51f35b92
+ after
+ 0000000000000000.0000000000000000.208215d7bda18000.0dcb80001e868000
+ c4bef1b3eea52198.0260806c4fd98782.f24134dbf279d2ff.44d8b03bae5bb235
+ 6833e77afca362bf.1f6150759c15be25.77dc27b411b34a41.273fd55bb8fcfea0
+ cdd7a0af1c132331.98ee95c0054f1598.d1bf1f0434d86338.370d70878fd54d06
+ 4f0dfeac51f35b92
+VPSUBSW_128(mem)
+ before
+ 4d0afab51761e470.51f619bceb7f9f9b.48d3ca39a5934908.5a371938f8755a90
+ 0cd1e08dff2ba4ce.4fdc4d0f047614a8.0adc6ccc99ee15a1.6f8f10baf8146bf6
+ 672f2c22255e56d6.23d438130381bb06.bcd5f565fc6b378e.6c1500f8d144d116
+ 3cee5a5fa305b7b4.292cd633852ed35e.3989e3f1eb1668fb.ae13e55d1e8fc99c
+ 8fd7bb547c818f33
+ after
+ 4d0afab51761e470.51f619bceb7f9f9b.48d3ca39a5934908.5a371938f8755a90
+ 0cd1e08dff2ba4ce.4fdc4d0f047614a8.0adc6ccc99ee15a1.6f8f10baf8146bf6
+ 0000000000000000.0000000000000000.c2097ffff45bcc99.1558f782ff9f1166
+ 3cee5a5fa305b7b4.292cd633852ed35e.3989e3f1eb1668fb.ae13e55d1e8fc99c
+ 8fd7bb547c818f33
+
+VPSUBSW_128(reg)
+ before
+ 6cab7e4b86a65f87.65dae730982c8295.bc2e23dd2608965f.5cc5b15a81fc6716
+ a1dc2badd98b7446.c0c14e811ee074a5.3a271c7c809c41b3.0356db8edb28ef09
+ 8ab6bde710bb0b19.276d0b3e512c490f.fe63bc7c32751006.0806de7814a6bb00
+ 83843063c7c260af.78ac9a544e1dbd00.632eff49d61f3e05.49a2340349838828
+ a0f55b1d95ca11ad
+ after
+ 0000000000000000.0000000000000000.d6f91d33aa7d03ae.b9b4a78b91a566e1
+ a1dc2badd98b7446.c0c14e811ee074a5.3a271c7c809c41b3.0356db8edb28ef09
+ 8ab6bde710bb0b19.276d0b3e512c490f.fe63bc7c32751006.0806de7814a6bb00
+ 83843063c7c260af.78ac9a544e1dbd00.632eff49d61f3e05.49a2340349838828
+ a0f55b1d95ca11ad
+VPSUBSW_128(mem)
+ before
+ ebcdceb1148813ba.e994818e9b2dafb2.8d4878ad30bd8ca4.c7d3e1500826085c
+ 04f40aabe3c84b7c.1630abd4288733ce.440e1f37141b7126.84a05ffb6517aab6
+ c83889f71e96721e.67a5a9a2095c29b1.77ca0ddc154029b2.f8df74b7887d60c0
+ 1463c981e0fe47cd.383f7962da39cc04.0448bd8a503a6f76.7ddd1cf10ee56526
+ 71e6531492daf693
+ after
+ ebcdceb1148813ba.e994818e9b2dafb2.8d4878ad30bd8ca4.c7d3e1500826085c
+ 04f40aabe3c84b7c.1630abd4288733ce.440e1f37141b7126.84a05ffb6517aab6
+ 0000000000000000.0000000000000000.7fffa68ae35e7fff.bccd7eab5cf1a25a
+ 1463c981e0fe47cd.383f7962da39cc04.0448bd8a503a6f76.7ddd1cf10ee56526
+ 71e6531492daf693
+
+VPSUBSW_128(reg)
+ before
+ 2e46158bb0e84fb3.c2424536450d84b5.e44a178238a95a76.c553ac2ce014009b
+ 12485fc4059cab34.afa179006acee601.c9127d6dbe390db1.97b854ade2db9850
+ 773a2c2a2d8147bf.b84be2cd6a4e28de.42e3a98f09742261.564433fb7199f3bf
+ ba667829c3235f03.b70efa8762980878.ab089654b5e6d433.dfc1c401a95dcd15
+ 0cfc83aca730e17d
+ after
+ 0000000000000000.0000000000000000.1e0a7fff0853397e.b7f77fff397ecb3b
+ 12485fc4059cab34.afa179006acee601.c9127d6dbe390db1.97b854ade2db9850
+ 773a2c2a2d8147bf.b84be2cd6a4e28de.42e3a98f09742261.564433fb7199f3bf
+ ba667829c3235f03.b70efa8762980878.ab089654b5e6d433.dfc1c401a95dcd15
+ 0cfc83aca730e17d
+VPSUBSW_128(mem)
+ before
+ bac0ede68720ec24.38193f2d640f2faa.89b43f1c6db840fa.60ce40285c1b60d3
+ c5db7c9c6438a935.4b9f7da2abd0f261.0a0a2c77a8ba8d90.bd81a4779da002ed
+ 0918aebb5a85d6dd.50442ff534f2e5d3.16dc3d842eabaa67.1d6dbcad1100f62b
+ 6242ff2d86122d48.a35450909c0244ad.89f6ef2f1c9654ab.dede863656c8773c
+ 5b20fd7f0883c3ca
+ after
+ bac0ede68720ec24.38193f2d640f2faa.89b43f1c6db840fa.60ce40285c1b60d3
+ c5db7c9c6438a935.4b9f7da2abd0f261.0a0a2c77a8ba8d90.bd81a4779da002ed
+ 0000000000000000.0000000000000000.7fffed5b80008000.800080008000a21a
+ 6242ff2d86122d48.a35450909c0244ad.89f6ef2f1c9654ab.dede863656c8773c
+ 5b20fd7f0883c3ca
+
+VPCMPEQW_128(reg)
+ before
+ ef7e1df2c2bd1382.ac26e9e004eb6ba1.a01bdce07e8b4a9a.3f24bd648d884788
+ f846e3fd2102a60f.c390e9beee1d4b15.a3e4d05277193547.1431230f9e8c3f29
+ d1c24a0bc0dfb61e.834c7cb563b28acf.09fc265123393f60.e4eb9d1c6aaef7ba
+ d53f4d873be0805b.c8251db07db9e4fc.2cafdc481c76a490.8b1ca7770dfb2c68
+ e591be0da47e9a5f
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ f846e3fd2102a60f.c390e9beee1d4b15.a3e4d05277193547.1431230f9e8c3f29
+ d1c24a0bc0dfb61e.834c7cb563b28acf.09fc265123393f60.e4eb9d1c6aaef7ba
+ d53f4d873be0805b.c8251db07db9e4fc.2cafdc481c76a490.8b1ca7770dfb2c68
+ e591be0da47e9a5f
+VPCMPEQW_128(mem)
+ before
+ ce165dc84b43fdcb.6209ebdf2f8f4071.6ee9489b583b15c8.6949eda5015da284
+ 227700961d5710d7.d26b1d7e387a310c.51627a621146d85e.1c1655d36b7873e7
+ bd80236236c590af.83b3e1d0f12c90da.4d5e2df1c3e6eaeb.a162113ef9565366
+ 7bfc4218b3993880.cf2b3142f6329985.3ea7df358a25079a.54781c52448080ad
+ 91a5717cea843467
+ after
+ ce165dc84b43fdcb.6209ebdf2f8f4071.6ee9489b583b15c8.6949eda5015da284
+ 227700961d5710d7.d26b1d7e387a310c.51627a621146d85e.1c1655d36b7873e7
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 7bfc4218b3993880.cf2b3142f6329985.3ea7df358a25079a.54781c52448080ad
+ 91a5717cea843467
+
+VPCMPEQW_128(reg)
+ before
+ b3360f2687edac41.37b8daa3afe0c676.14200b3ee41788b9.ff090b188411eb98
+ 1875efbdb64724e6.cf8166f147a5f4bc.acde6b3156679823.6e522e87cab65110
+ 1bae0eae141fd703.1e2162ee97f47f7f.f4b14b88e9af066f.664dc26f7a1ef62f
+ 182f69633c000243.00644a84b9da22eb.49e5a9ad397a0e48.c3c545bbb0579621
+ 60873256876dec12
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 1875efbdb64724e6.cf8166f147a5f4bc.acde6b3156679823.6e522e87cab65110
+ 1bae0eae141fd703.1e2162ee97f47f7f.f4b14b88e9af066f.664dc26f7a1ef62f
+ 182f69633c000243.00644a84b9da22eb.49e5a9ad397a0e48.c3c545bbb0579621
+ 60873256876dec12
+VPCMPEQW_128(mem)
+ before
+ 1b60052e1b6bb52c.6b43fb4aca77e154.50189ba0cc629b2b.05c6800ee054eb5b
+ ce1a3b2e895dad9e.6f35c0ce5b0fb0df.ec08d02ee998a36c.859fcc157ccadb53
+ 57814e42ed4f9092.8252b55b8a54aa93.aeff651b2e89f9d9.25bd8930a96718dd
+ 9163bc56614e1935.ffe6d55df4d30c1a.74cad651b740589f.416db4ca02b7dea5
+ 36f9474f24476a56
+ after
+ 1b60052e1b6bb52c.6b43fb4aca77e154.50189ba0cc629b2b.05c6800ee054eb5b
+ ce1a3b2e895dad9e.6f35c0ce5b0fb0df.ec08d02ee998a36c.859fcc157ccadb53
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 9163bc56614e1935.ffe6d55df4d30c1a.74cad651b740589f.416db4ca02b7dea5
+ 36f9474f24476a56
+
+VPCMPEQW_128(reg)
+ before
+ 5ead402baaa2f99d.578a0056046505b2.413d1b4035161220.1835a0be9fca7be9
+ 16d79bcb3155c425.86c4962ff0a01036.a6a38670e8acf752.780c3d4d03311fe4
+ bac2529954ea0a9b.fbdbfbcb410cf5ec.89630f59a91ef85c.6e1b2beafe83ffbc
+ a6b96302afef05ab.909caa1814b47101.45cbb36715fa51e9.d82de581acccd89c
+ 9010e8fe2a1767b1
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 16d79bcb3155c425.86c4962ff0a01036.a6a38670e8acf752.780c3d4d03311fe4
+ bac2529954ea0a9b.fbdbfbcb410cf5ec.89630f59a91ef85c.6e1b2beafe83ffbc
+ a6b96302afef05ab.909caa1814b47101.45cbb36715fa51e9.d82de581acccd89c
+ 9010e8fe2a1767b1
+VPCMPEQW_128(mem)
+ before
+ 748eae4d94706527.3609c973dff0f200.23d31f0084a540a1.38256f07c7cb3ea6
+ 5e74b55a05e39129.c6fe805680780d47.8e4cd671aeea1ef7.bcbe3ea35b1efa3f
+ 2b8e7811997da5e3.b2e484192c13912b.aed24b56ad8fc630.2fe21ca96f7ec25f
+ b7a8735f6d495e83.5607d127824dbb59.6032fb9b9da0f578.ebdd06849c77d2b2
+ 4dfbf69f809665e6
+ after
+ 748eae4d94706527.3609c973dff0f200.23d31f0084a540a1.38256f07c7cb3ea6
+ 5e74b55a05e39129.c6fe805680780d47.8e4cd671aeea1ef7.bcbe3ea35b1efa3f
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ b7a8735f6d495e83.5607d127824dbb59.6032fb9b9da0f578.ebdd06849c77d2b2
+ 4dfbf69f809665e6
+
+VPADDB_128(reg)
+ before
+ b287ea68b766b8a4.df8e222e9c547732.0eb264ec1cb3c77d.7e39602c9b2a67fa
+ 74cfdd4adc73079b.7d0b026c43a9ae1f.353338d496d0f042.e5b1f8f5c338d7e2
+ f01dccb18c4a8e75.6eed8e047d54bd74.29d4494b8d317455.71673fe230d7025e
+ 83beb10a627688df.8efe42e16761615d.45e294bd9c608d61.fe26afdfff12a497
+ 69bcc6d84bf579bc
+ after
+ 0000000000000000.0000000000000000.5e07811f23016497.561837d7f30fd940
+ 74cfdd4adc73079b.7d0b026c43a9ae1f.353338d496d0f042.e5b1f8f5c338d7e2
+ f01dccb18c4a8e75.6eed8e047d54bd74.29d4494b8d317455.71673fe230d7025e
+ 83beb10a627688df.8efe42e16761615d.45e294bd9c608d61.fe26afdfff12a497
+ 69bcc6d84bf579bc
+VPADDB_128(mem)
+ before
+ 8cf4ffba308c3cf7.87fe8abffa833284.b90b9af11cdd5508.e5a9139660ec7713
+ 4499d66fcbe4aa74.5928523df1fec811.cbe0131fb9d4569f.6475c442745e7016
+ 6d78c7e537097f61.558a05f1e2728531.a04828575950204e.2091a22e7544b218
+ e35d4f07910577e7.d76e9f456a6ba691.14115485195f6f42.744ba9c4fe297ac2
+ bbedd672ab9a03c3
+ after
+ 8cf4ffba308c3cf7.87fe8abffa833284.b90b9af11cdd5508.e5a9139660ec7713
+ 4499d66fcbe4aa74.5928523df1fec811.cbe0131fb9d4569f.6475c442745e7016
+ 0000000000000000.0000000000000000.84ebad10d5b1aba7.491ed7d8d44ae729
+ e35d4f07910577e7.d76e9f456a6ba691.14115485195f6f42.744ba9c4fe297ac2
+ bbedd672ab9a03c3
+
+VPADDB_128(reg)
+ before
+ 53c424a219228ac5.8214e9c0f4e64d35.3b221da7247667dd.03051696140cfea6
+ 971c8fc2e44d4b74.266811fe7db7be75.ddf07a82ad1e04c0.49f2e77466648aa8
+ e241133da7a8827d.ab2743ac488585d3.1a25b242a1f0b8e7.c2a2450c2c72cf71
+ 927fac7ffebd6b8c.ec1bfbb66f5b607c.4c0cc1529a76c0fd.4ae2aa4b82428930
+ bd7d951c83e1730f
+ after
+ 0000000000000000.0000000000000000.f7152cc44e0ebca7.0b942c8092d65919
+ 971c8fc2e44d4b74.266811fe7db7be75.ddf07a82ad1e04c0.49f2e77466648aa8
+ e241133da7a8827d.ab2743ac488585d3.1a25b242a1f0b8e7.c2a2450c2c72cf71
+ 927fac7ffebd6b8c.ec1bfbb66f5b607c.4c0cc1529a76c0fd.4ae2aa4b82428930
+ bd7d951c83e1730f
+VPADDB_128(mem)
+ before
+ f7417f6a4b5a4a3a.012257f4861b414c.c712b6081045099c.d0f3a321363e58af
+ d4f9e523f7b9c9de.8c750e08db4b416a.17d6ef8f47503d5f.0124551811d4bca9
+ 2f704432a30bae27.90c5cf2898dba691.b83322352f87b7f0.3dedd2a4c6c32796
+ e6731783695bb341.675e96be5957ad6e.86f7cbe8e5f6347b.df981631f297d623
+ 43721e2c30dc05fb
+ after
+ f7417f6a4b5a4a3a.012257f4861b414c.c712b6081045099c.d0f3a321363e58af
+ d4f9e523f7b9c9de.8c750e08db4b416a.17d6ef8f47503d5f.0124551811d4bca9
+ 0000000000000000.0000000000000000.dee8a597579546fb.d117f83947121458
+ e6731783695bb341.675e96be5957ad6e.86f7cbe8e5f6347b.df981631f297d623
+ 43721e2c30dc05fb
+
+VPADDB_128(reg)
+ before
+ c5c7e4ff1c1fefcb.d4ceda0268b59556.6f8c5d37bb4993ad.5ced679284aa702d
+ c1e2661854ebd13e.d54d099bb9260f95.029b2200593f91f9.18e0702128ae2732
+ 92119fe171cde702.c4bc213b7bb9de28.7dd6e084d0c5e6ff.959d647fee0e15b5
+ 969e8bc811506cc0.7fe69dccc77abe3c.3c8b932ebb65cc6b.aef1bf9af2d7f5e3
+ 41a6fb5d4f1483e8
+ after
+ 0000000000000000.0000000000000000.7f710284290477f8.ad7dd4a016bc3ce7
+ c1e2661854ebd13e.d54d099bb9260f95.029b2200593f91f9.18e0702128ae2732
+ 92119fe171cde702.c4bc213b7bb9de28.7dd6e084d0c5e6ff.959d647fee0e15b5
+ 969e8bc811506cc0.7fe69dccc77abe3c.3c8b932ebb65cc6b.aef1bf9af2d7f5e3
+ 41a6fb5d4f1483e8
+VPADDB_128(mem)
+ before
+ 298896b421d27def.28d62738cf009e27.e098f93bbc766bfc.9c04376cb7ad80e8
+ 41650a8b851b9d24.a4056d9d4869b7e0.c59fb17573b8a195.f78ec9a95f293d22
+ 6707d5cf96fea0b5.65775b631818f39a.08c541650a4d1b33.aa7544514f6341c7
+ 753c736a718442cc.c978ecf6d99990ff.87d726f69d3f9601.1105a3d024e9c680
+ 888ae5927a4709fc
+ after
+ 298896b421d27def.28d62738cf009e27.e098f93bbc766bfc.9c04376cb7ad80e8
+ 41650a8b851b9d24.a4056d9d4869b7e0.c59fb17573b8a195.f78ec9a95f293d22
+ 0000000000000000.0000000000000000.a537aab02f2e0c91.9392001516d6bd0a
+ 753c736a718442cc.c978ecf6d99990ff.87d726f69d3f9601.1105a3d024e9c680
+ 888ae5927a4709fc
+
+VMOVAPS_EtoG_256(reg)
+ before
+ 6b4f0304ec0845e5.48ce5e4932bb3e95.2a541dc22a76c8bc.1ca0db16479dcd2b
+ 16a2fb9017b8b7e7.bd8a1459f3ae523d.e656e834a43dd87c.a5eedcb025707ddf
+ e5cdc8a496e39bb0.ae3c1084d36938f0.57cb4bb6e679fbec.fc8ba5b052c66246
+ 341d66aa05162de9.f9b0ceb8ebf9acd9.db0041b689b76fb7.ff45b302eaaa388f
+ 88e681930a28bbe4
+ after
+ 6b4f0304ec0845e5.48ce5e4932bb3e95.2a541dc22a76c8bc.1ca0db16479dcd2b
+ e5cdc8a496e39bb0.ae3c1084d36938f0.57cb4bb6e679fbec.fc8ba5b052c66246
+ e5cdc8a496e39bb0.ae3c1084d36938f0.57cb4bb6e679fbec.fc8ba5b052c66246
+ 341d66aa05162de9.f9b0ceb8ebf9acd9.db0041b689b76fb7.ff45b302eaaa388f
+ 88e681930a28bbe4
+VMOVAPS_EtoG_256(mem)
+ before
+ 743b8b4dcd4da672.5fded11001dca841.78b1cae059696b25.cc3fc69e2c826e8b
+ 9f104d1d5024b664.c25c064125c24962.080c81e839c631ff.88d4d6dc68663411
+ e63043f0afbaa6e7.b9e2ffa80e524cf8.858e6ebca61bba94.690d6edbdbf0fff7
+ 2369eab0041a3426.a0bebab3571aedb0.cc010d48bd74c210.cd34890721ab09e9
+ 0e9723ccd5238f93
+ after
+ 743b8b4dcd4da672.5fded11001dca841.78b1cae059696b25.cc3fc69e2c826e8b
+ 9f104d1d5024b664.c25c064125c24962.080c81e839c631ff.88d4d6dc68663411
+ e63043f0afbaa6e7.b9e2ffa80e524cf8.858e6ebca61bba94.690d6edbdbf0fff7
+ 743b8b4dcd4da672.5fded11001dca841.78b1cae059696b25.cc3fc69e2c826e8b
+ 0e9723ccd5238f93
+
+VMOVAPS_EtoG_256(reg)
+ before
+ 8980389693e5cca0.3385bd4b6e501a4e.d23a32cd9da66736.b732da7899dd049e
+ 9a3cc5d1f87cfebc.f25138ac0669148b.ada364637b81f735.23ec523856633d6b
+ 9e17c4e9a0745f95.3c99d7bfeb6fe008.8c454adf8e37d95a.ecfdef74111228a2
+ ef5d334b265a2cd5.ed291770367138f2.cb6ce2ae71554851.ee302f19e6f48370
+ 05508d11f0170801
+ after
+ 8980389693e5cca0.3385bd4b6e501a4e.d23a32cd9da66736.b732da7899dd049e
+ 9e17c4e9a0745f95.3c99d7bfeb6fe008.8c454adf8e37d95a.ecfdef74111228a2
+ 9e17c4e9a0745f95.3c99d7bfeb6fe008.8c454adf8e37d95a.ecfdef74111228a2
+ ef5d334b265a2cd5.ed291770367138f2.cb6ce2ae71554851.ee302f19e6f48370
+ 05508d11f0170801
+VMOVAPS_EtoG_256(mem)
+ before
+ 0d2a864a4b867480.ea590e6126b9a028.e1cd72ab0578d974.c563273cc16581c5
+ e28a94af144e821a.eb594f993d1df83b.f451665c74927fbb.d87816f619f6c063
+ 603c352b667aeffa.4ea7f35d061370ba.02806f6f9ecbe5f3.5ff5a947169140d6
+ 630be4ac5e16774d.6f90f71b1e264450.e72707d1a02dc847.b527de9a53c43fcb
+ 385ab05d6c1af7ed
+ after
+ 0d2a864a4b867480.ea590e6126b9a028.e1cd72ab0578d974.c563273cc16581c5
+ e28a94af144e821a.eb594f993d1df83b.f451665c74927fbb.d87816f619f6c063
+ 603c352b667aeffa.4ea7f35d061370ba.02806f6f9ecbe5f3.5ff5a947169140d6
+ 0d2a864a4b867480.ea590e6126b9a028.e1cd72ab0578d974.c563273cc16581c5
+ 385ab05d6c1af7ed
+
+VMOVAPS_EtoG_256(reg)
+ before
+ 42da1bfbfe20a4ea.c7c51d1d172fd63f.aa60563e20e2afaa.7f12ac6c95c6e4e4
+ 31f31be0a561846b.68345d6aaed0c7fb.5b630d32a9d4ee73.a60dd82e99a1f4f5
+ 5ff0ad78fc69d11f.22261e803e0507ae.dee4166354873d58.38e40901c9cbb6a7
+ 2a1fcc2f9fc5c8af.d165de49e4db5283.8f316f3dbe88d705.1163bbd3414fe426
+ 0d55688f1b393a9d
+ after
+ 42da1bfbfe20a4ea.c7c51d1d172fd63f.aa60563e20e2afaa.7f12ac6c95c6e4e4
+ 5ff0ad78fc69d11f.22261e803e0507ae.dee4166354873d58.38e40901c9cbb6a7
+ 5ff0ad78fc69d11f.22261e803e0507ae.dee4166354873d58.38e40901c9cbb6a7
+ 2a1fcc2f9fc5c8af.d165de49e4db5283.8f316f3dbe88d705.1163bbd3414fe426
+ 0d55688f1b393a9d
+VMOVAPS_EtoG_256(mem)
+ before
+ 07878e2176967638.ecca74712b00a4ca.50be18b2bb5d64a7.ca94132c8262fa25
+ ddc6a8756c715225.023ea1ab3ba6a31a.7dfc48a8e097f846.eb5afe9c3da1e064
+ 6adc327719d68b8e.c9c74f476c44ff4c.33edeb156e96cb8b.4ecf2cfa8ad1c570
+ 8a95a8139ad2dc9f.9bb17bb35965f40b.4e5b7ce7816599a3.4f3f9ab0057fe7f3
+ 4af6432c4b368099
+ after
+ 07878e2176967638.ecca74712b00a4ca.50be18b2bb5d64a7.ca94132c8262fa25
+ ddc6a8756c715225.023ea1ab3ba6a31a.7dfc48a8e097f846.eb5afe9c3da1e064
+ 6adc327719d68b8e.c9c74f476c44ff4c.33edeb156e96cb8b.4ecf2cfa8ad1c570
+ 07878e2176967638.ecca74712b00a4ca.50be18b2bb5d64a7.ca94132c8262fa25
+ 4af6432c4b368099
+
+VCVTDQ2PD_256(reg)
+ before
+ 9a3f23d9f883cd0f.18bf87350a700285.d54720599f95c004.a914770936101db9
+ 9d683622a7f10901.f2254aca86bdb96c.d4d73aa7d9619de2.22e25866a9a414fa
+ aebb7875f40c711b.f2926dbc29c3bd7f.f2abc508a454c852.94929becf52c3a91
+ 2885e63d7c604107.f6d36cf90f90caeb.8c10bee89bfa7d00.daefbd8636b44bab
+ d2c7392089490274
+ after
+ 9a3f23d9f883cd0f.18bf87350a700285.d54720599f95c004.a914770936101db9
+ c1aaa875f0000000.c1d6eacdeb800000.c1dadb5905000000.c1a5a78ade000000
+ aebb7875f40c711b.f2926dbc29c3bd7f.f2abc508a454c852.94929becf52c3a91
+ 2885e63d7c604107.f6d36cf90f90caeb.8c10bee89bfa7d00.daefbd8636b44bab
+ d2c7392089490274
+VCVTDQ2PD_256(mem)
+ before
+ 56e48ba709f61c17.69127be6db7ab574.d9b4c36b56309bdc.fe5220b35be0f797
+ 44142f05d3c855c1.ccad33dcabe5080c.7601ef0017aeed7d.a4bde7d57f9173c4
+ 7621a22702c9689e.aca40a8c8b2e787c.aa866ba370167bfa.da9d0fbaa3992d32
+ c9d85efab30812d9.6741fd6014e03e6f.520fb3407d740281.fc3d94cf6485608e
+ 66ea737e5ee04a84
+ after
+ 56e48ba709f61c17.69127be6db7ab574.d9b4c36b56309bdc.fe5220b35be0f797
+ c1c3259e4a800000.41d58c26f7000000.c17addf4d0000000.41d6f83de5c00000
+ 7621a22702c9689e.aca40a8c8b2e787c.aa866ba370167bfa.da9d0fbaa3992d32
+ c9d85efab30812d9.6741fd6014e03e6f.520fb3407d740281.fc3d94cf6485608e
+ 66ea737e5ee04a84
+
+VCVTDQ2PD_256(reg)
+ before
+ 74f1a7342c3724bf.1a05e168018e0f9f.57d206c5e5879992.486743c359d53e3c
+ 829c2c5e6a142dec.4374a65f09691b1b.daa1232897b0c390.6a5b98182044eb57
+ ec38fe67b5059fb6.21f02acae6a4f17a.4afb50f4c9e6f917.92b72d2befcec5ff
+ 0e101abaa996b8ca.9147e795b54b4ee7.052c879414b577d0.9d477ee9e17d8760
+ 68d7073c1360eea5
+ after
+ 74f1a7342c3724bf.1a05e168018e0f9f.57d206c5e5879992.486743c359d53e3c
+ 41d2bed43d000000.c1cb0c8374800000.c1db5234b5400000.c1b0313a01000000
+ ec38fe67b5059fb6.21f02acae6a4f17a.4afb50f4c9e6f917.92b72d2befcec5ff
+ 0e101abaa996b8ca.9147e795b54b4ee7.052c879414b577d0.9d477ee9e17d8760
+ 68d7073c1360eea5
+VCVTDQ2PD_256(mem)
+ before
+ cd334411a180b5fb.44727ac5e152b1d4.6d435bac916bee8f.657fc67616aa7869
+ a926b255a5eb9a8d.eaa81cf3f9c5c97f.92b101fb96108c9e.c74207056b503a8e
+ d87eccf33eac5788.5c00fcb08e7b3a78.dc5d556ee144e53f.88bf49adae33f7eb
+ 36050ed786d0a818.f6c414683b01416a.2813d4f18e15b59f.024385da7be0eb2b
+ 921ab8f86fe253fa
+ after
+ cd334411a180b5fb.44727ac5e152b1d4.6d435bac916bee8f.657fc67616aa7869
+ 41db50d6eb000000.c1dba5045c400000.41d95ff19d800000.41b6aa7869000000
+ d87eccf33eac5788.5c00fcb08e7b3a78.dc5d556ee144e53f.88bf49adae33f7eb
+ 36050ed786d0a818.f6c414683b01416a.2813d4f18e15b59f.024385da7be0eb2b
+ 921ab8f86fe253fa
+
+VCVTDQ2PD_256(reg)
+ before
+ 9490df7426c56b06.9f88f4ec99624b68.134162889de21a02.509ef970b88eb8e9
+ 65f1f5b83b166ff9.efd3fb20936efaa5.11c2e07a4fab00eb.31cc40d87bbca94a
+ 5f88f6314a609b7f.03b19d5e920072fa.4b958cabede730d3.a7672513f4aa45ee
+ dfa3df4cf02f2a45.b5f05893af256f94.1c0562881522e663.8e3c240f3f644800
+ c217bab777f66ead
+ after
+ 9490df7426c56b06.9f88f4ec99624b68.134162889de21a02.509ef970b88eb8e9
+ 41d2e5632ac00000.c1b218cf2d000000.c1d62636bb400000.c1a6ab7424000000
+ 5f88f6314a609b7f.03b19d5e920072fa.4b958cabede730d3.a7672513f4aa45ee
+ dfa3df4cf02f2a45.b5f05893af256f94.1c0562881522e663.8e3c240f3f644800
+ c217bab777f66ead
+VCVTDQ2PD_256(mem)
+ before
+ 1fc461f7b86d7220.418caa74c81059f7.e25aa7a908e9ac9f.e25d5c7b60e95e4a
+ 810f97ba1fd51186.e19055146f8e6340.65bd078db956e646.f8ea78f26cc6d331
+ c4c3d8eec738060b.1bfbdb9a803586cd.1ce3f22cdd7ad9b6.b9f8b158d54882c7
+ c4ad9e7ecda40fda.4b1938719892fc49.e299e6709061401a.83d3031936f8a7b6
+ b0c76aa12b647dab
+ after
+ 1fc461f7b86d7220.418caa74c81059f7.e25aa7a908e9ac9f.e25d5c7b60e95e4a
+ c1bda55857000000.41a1d3593e000000.c1bda2a385000000.41d83a5792800000
+ c4c3d8eec738060b.1bfbdb9a803586cd.1ce3f22cdd7ad9b6.b9f8b158d54882c7
+ c4ad9e7ecda40fda.4b1938719892fc49.e299e6709061401a.83d3031936f8a7b6
+ b0c76aa12b647dab
+
+VMOVHPD_128_LoadForm(reg)
+ before
+ 9e1fe35c51184151.5c9a67574c25e620.cd35690552300261.93ab5e47ef15d99f
+ a72869b6449e2f55.6a54ad6360c54808.fd9d68c24b9cd3c0.0be4d79c16a45e71
+ 282ff81b9e848362.c9a8ef8f2792f0bf.379b33151e60ac14.2612cb5a201a8bbb
+ 7e7e8cf8fe557825.5561a6c8ba989b70.d77cc568680bc906.c0ffb86f29811eaa
+ b47819c64ee7d169
+ after
+ 9e1fe35c51184151.5c9a67574c25e620.cd35690552300261.93ab5e47ef15d99f
+ a72869b6449e2f55.6a54ad6360c54808.fd9d68c24b9cd3c0.0be4d79c16a45e71
+ 282ff81b9e848362.c9a8ef8f2792f0bf.379b33151e60ac14.2612cb5a201a8bbb
+ 7e7e8cf8fe557825.5561a6c8ba989b70.d77cc568680bc906.c0ffb86f29811eaa
+ b47819c64ee7d169
+VMOVHPD_128_LoadForm(mem)
+ before
+ e0496a4baa586125.036221b7fe9e4b4a.ea4d4ff837e10549.398c1b28c4266645
+ 1f3e27eb5ade8909.1426b4c63aea387c.6336670dba7bea73.b9172fc2ce3fbe7b
+ 4c23cd9079870643.0e18408f4fc57a68.9eea69f25e72061d.b269ffa023e10e54
+ 45c3d627245f94fc.4b82c180d8bc4eba.7533d1923fd01471.82cd86305f99927d
+ 8491c0dd1df186a2
+ after
+ e0496a4baa586125.036221b7fe9e4b4a.ea4d4ff837e10549.398c1b28c4266645
+ 1f3e27eb5ade8909.1426b4c63aea387c.6336670dba7bea73.b9172fc2ce3fbe7b
+ 0000000000000000.0000000000000000.398c1b28c4266645.b9172fc2ce3fbe7b
+ 45c3d627245f94fc.4b82c180d8bc4eba.7533d1923fd01471.82cd86305f99927d
+ 8491c0dd1df186a2
+
+VMOVHPD_128_LoadForm(reg)
+ before
+ 14ffaa13f978256e.e5ecc09d7670ef63.28b23304715af01d.c6de1cdb7aa4d09b
+ 8d643e3e90b7ac8e.076807dc8cc9d3a1.01f29387b82c9c3d.6cb6c4b82bf7f8c8
+ 4d0c7aca7d3c57ae.890425d28173fbe5.338fdc7546bc8dc7.428947166dd74624
+ ae4359235d926179.458c986a717c2459.18d50a3ab9980067.262220df5c4f77da
+ f24ccb00156b4717
+ after
+ 14ffaa13f978256e.e5ecc09d7670ef63.28b23304715af01d.c6de1cdb7aa4d09b
+ 8d643e3e90b7ac8e.076807dc8cc9d3a1.01f29387b82c9c3d.6cb6c4b82bf7f8c8
+ 4d0c7aca7d3c57ae.890425d28173fbe5.338fdc7546bc8dc7.428947166dd74624
+ ae4359235d926179.458c986a717c2459.18d50a3ab9980067.262220df5c4f77da
+ f24ccb00156b4717
+VMOVHPD_128_LoadForm(mem)
+ before
+ 84d4c565b3387107.0e54d8b5cc46079c.19cbdb8f79ef092a.0d0f1942ad4c31c9
+ b68689fb53c1b3d5.c88df1ec64e385c2.df8f6a2fb5d86783.6e8b05f9bd625c98
+ 652e93ad1013c7ad.3738a235c4f51798.74a2c1354044fa91.9793cbcc8569bc80
+ 6e985f66073869bc.b9a2e6fa8509f8c9.b5d25d8e363e7e7f.e4746625a2ea8e2e
+ b17ad272b0730d4e
+ after
+ 84d4c565b3387107.0e54d8b5cc46079c.19cbdb8f79ef092a.0d0f1942ad4c31c9
+ b68689fb53c1b3d5.c88df1ec64e385c2.df8f6a2fb5d86783.6e8b05f9bd625c98
+ 0000000000000000.0000000000000000.0d0f1942ad4c31c9.6e8b05f9bd625c98
+ 6e985f66073869bc.b9a2e6fa8509f8c9.b5d25d8e363e7e7f.e4746625a2ea8e2e
+ b17ad272b0730d4e
+
+VMOVHPD_128_LoadForm(reg)
+ before
+ 5af10b1d4a8f778c.ab8f6914533f562e.a817b9a945aa6502.7ce9b824b4d3af7a
+ 3b250e940cca0693.f9e12ea210314a2f.61e318ada0649aef.a6b450e4d60e48ae
+ af62d64293b1f70f.355829fc5c1c01ea.4152fd7131c4d23b.10ffa1bbb7fb0646
+ 14f35e937acf85ad.39c1d60e500b378b.a2af666395554a93.9495259373a6a46f
+ 0f445a5a271ce054
+ after
+ 5af10b1d4a8f778c.ab8f6914533f562e.a817b9a945aa6502.7ce9b824b4d3af7a
+ 3b250e940cca0693.f9e12ea210314a2f.61e318ada0649aef.a6b450e4d60e48ae
+ af62d64293b1f70f.355829fc5c1c01ea.4152fd7131c4d23b.10ffa1bbb7fb0646
+ 14f35e937acf85ad.39c1d60e500b378b.a2af666395554a93.9495259373a6a46f
+ 0f445a5a271ce054
+VMOVHPD_128_LoadForm(mem)
+ before
+ 5dd6bbfaee687423.c525a5f35eb1ed19.e2e8b1c40a0ba740.e1474eee67a33ea3
+ 5a18c461e5971c05.1e44a4cedae26bfe.0c99360aa6270e32.5b67b17e433bea16
+ e2d6f17a27b49628.7b9c59908bee3b09.939fe2cd3f6b2790.6a598c80c6a88998
+ d2dcbe31d1cb9cb8.3779bea60c6198e6.53c830f7f1e3b084.6b69da5e8c7658d7
+ bae597853032937c
+ after
+ 5dd6bbfaee687423.c525a5f35eb1ed19.e2e8b1c40a0ba740.e1474eee67a33ea3
+ 5a18c461e5971c05.1e44a4cedae26bfe.0c99360aa6270e32.5b67b17e433bea16
+ 0000000000000000.0000000000000000.e1474eee67a33ea3.5b67b17e433bea16
+ d2dcbe31d1cb9cb8.3779bea60c6198e6.53c830f7f1e3b084.6b69da5e8c7658d7
+ bae597853032937c
+
+VCVTPD2PS_256(reg)
+ before
+ b418bf624e677536.04f6a872fee9ebe1.b027d27afac8c040.28de9c75d99c633b
+ b34d4e5f83a13caf.55f02a29ca193fce.41f18e7af0aeecc4.eeaea23412a2fde0
+ 14d141ea6a6d2294.a195c042526753ab.4525ef108ba05b1d.8104bf1fb9ff399f
+ 33f0936ea0566390.c4b2e7aab2dfe4a5.1a0df2aa662947f8.bdac6e22eac1d4a6
+ 7e722b28bff38a1f
+ after
+ 0000000000000000.0000000000000000.800000007f800000.4f8c73d8ff800000
+ b34d4e5f83a13caf.55f02a29ca193fce.41f18e7af0aeecc4.eeaea23412a2fde0
+ 14d141ea6a6d2294.a195c042526753ab.4525ef108ba05b1d.8104bf1fb9ff399f
+ 33f0936ea0566390.c4b2e7aab2dfe4a5.1a0df2aa662947f8.bdac6e22eac1d4a6
+ 7e722b28bff38a1f
+VCVTPD2PS_256(mem)
+ before
+ a021721f57a21736.6cf64057c0e83d50.9913194b058eaee8.1af692b31dd5ed00
+ ff86bff3cbd93619.1b2f441067b0ea7f.fe84d41367806c9f.a32ccb974d3189e3
+ 776e8f8e39a4a4f1.9ce79b083039a6ca.ced193ecf5bfdcf7.0ffa99c292c8564a
+ e4a35dddbd101ded.4b6942a8b810afdc.e5c6d2c4cb59b81c.bcaef9a0872691e3
+ 0492e69dc8d8765a
+ after
+ a021721f57a21736.6cf64057c0e83d50.9913194b058eaee8.1af692b31dd5ed00
+ ff86bff3cbd93619.1b2f441067b0ea7f.fe84d41367806c9f.a32ccb974d3189e3
+ 776e8f8e39a4a4f1.9ce79b083039a6ca.ced193ecf5bfdcf7.0ffa99c292c8564a
+ 0000000000000000.0000000000000000.800000007f800000.8000000000000000
+ 0492e69dc8d8765a
+
+VCVTPD2PS_256(reg)
+ before
+ 45f35c25f269415b.22f2a5cc72285d37.8403345d9abf3f63.1f2e0e86045abc39
+ d91e57a4a0652d91.0c26e34875f81ffb.a3ff6d9373d59308.58d6c21ebccca67b
+ 1d5cd4876f5877a9.800d943be18d2066.04aae9b7dedbe77a.6b8b697810bd300d
+ 6efccd38facf5b4e.59713393d2f21ca4.024fa533775f7663.361782801b39171c
+ 94468622fa4a16d4
+ after
+ 0000000000000000.0000000000000000.ff80000000000000.800000007f800000
+ d91e57a4a0652d91.0c26e34875f81ffb.a3ff6d9373d59308.58d6c21ebccca67b
+ 1d5cd4876f5877a9.800d943be18d2066.04aae9b7dedbe77a.6b8b697810bd300d
+ 6efccd38facf5b4e.59713393d2f21ca4.024fa533775f7663.361782801b39171c
+ 94468622fa4a16d4
+VCVTPD2PS_256(mem)
+ before
+ 60e6f34ac8feea60.26494025de56142d.72203b3b6533cee0.fb3c9c75dbec7d6f
+ 78c243e5a2614fec.a28e28b9b678e0f1.a9e42b1fb65df347.4abccae7a60f384b
+ b7a5f4dda37e01a6.3e1982601fc1f947.d98a7c2be07b4705.4b1a2bf77352e3a3
+ f85c8220e861bcb8.57344886b4bd9bdb.ddddac4bff9a8645.59a3bb10de44b922
+ d2a3779e846ef775
+ after
+ 60e6f34ac8feea60.26494025de56142d.72203b3b6533cee0.fb3c9c75dbec7d6f
+ 78c243e5a2614fec.a28e28b9b678e0f1.a9e42b1fb65df347.4abccae7a60f384b
+ b7a5f4dda37e01a6.3e1982601fc1f947.d98a7c2be07b4705.4b1a2bf77352e3a3
+ 0000000000000000.0000000000000000.7f80000000000000.7f800000ff800000
+ d2a3779e846ef775
+
+VCVTPD2PS_256(reg)
+ before
+ 11665a0d005ed948.19b367988c163b4e.472c789712f90358.93ab366b30c46b34
+ 713860c9ef9f9a46.f4762133acaa3b95.6b4c0dffd4006e6b.d5bf96778f07b3fd
+ 5065853eedbe771c.67712bdc632877b9.1fe2032a965e15bf.81e4485b366f1acd
+ 0838c6d99446ac75.4c70017fcd9cace5.bf395684f5a03701.71e7c80444075bcf
+ 8394935cd2db3330
+ after
+ 0000000000000000.0000000000000000.7f800000ff800000.7f800000ff800000
+ 713860c9ef9f9a46.f4762133acaa3b95.6b4c0dffd4006e6b.d5bf96778f07b3fd
+ 5065853eedbe771c.67712bdc632877b9.1fe2032a965e15bf.81e4485b366f1acd
+ 0838c6d99446ac75.4c70017fcd9cace5.bf395684f5a03701.71e7c80444075bcf
+ 8394935cd2db3330
+VCVTPD2PS_256(mem)
+ before
+ 91b72451fff75e1c.f7fe1e0483c374fe.803e1f0807139646.a79c037a8d510edd
+ 781cf7cde46898be.7703892d53c20d62.e0a802632d98f107.33580576f9fdd7fe
+ 158e89be9f399c43.e69303bea2ceb14e.467a247c59387956.bfb958e6d531ce11
+ 42db540f4c7727d6.9efa88250c739d6e.8f800340aafee95c.a70bf834be782ec1
+ 479ae2ce505f34bb
+ after
+ 91b72451fff75e1c.f7fe1e0483c374fe.803e1f0807139646.a79c037a8d510edd
+ 781cf7cde46898be.7703892d53c20d62.e0a802632d98f107.33580576f9fdd7fe
+ 158e89be9f399c43.e69303bea2ceb14e.467a247c59387956.bfb958e6d531ce11
+ 0000000000000000.0000000000000000.80000000ff800000.8000000080000000
+ 479ae2ce505f34bb
+
+VPUNPCKHDQ_128(reg)
+ before
+ fbb1111f25711cab.dccdd6ac062df5a5.fd8415cd2c3d0c6d.98861a993af6fe47
+ 1f9e8193dc3a213c.bf318a81ea67c1d9.5d7ca5229fb93bf8.3b58e675252c7343
+ 0eab2e960e46811b.c8d3ec7a133148a0.1b303490007366bb.55c1e2be88ad067c
+ 262514945a2276f3.d17f79839d984626.94eabe83ebf5c961.c28f89627e84711d
+ 5e8c594c24be7052
+ after
+ 0000000000000000.0000000000000000.1b3034905d7ca522.007366bb9fb93bf8
+ 1f9e8193dc3a213c.bf318a81ea67c1d9.5d7ca5229fb93bf8.3b58e675252c7343
+ 0eab2e960e46811b.c8d3ec7a133148a0.1b303490007366bb.55c1e2be88ad067c
+ 262514945a2276f3.d17f79839d984626.94eabe83ebf5c961.c28f89627e84711d
+ 5e8c594c24be7052
+VPUNPCKHDQ_128(mem)
+ before
+ 0685ce689566c149.c25830f959593c71.b700ab89a5a77797.22f74067fdcd9f96
+ 944662a2ee881e2b.3e907d32aa781140.56240076476b961e.22a3b4a8d2872508
+ e59b93e64a314427.f519f7a9e60a2f0d.8ab5f3389eef60e7.f03918b305ae9760
+ d54fdc20c66cef67.453e9accab9bd384.2f8001b9c63f911f.e80767f232ce304d
+ 67579ed3f6732d79
+ after
+ 0685ce689566c149.c25830f959593c71.b700ab89a5a77797.22f74067fdcd9f96
+ 944662a2ee881e2b.3e907d32aa781140.56240076476b961e.22a3b4a8d2872508
+ 0000000000000000.0000000000000000.b700ab8956240076.a5a77797476b961e
+ d54fdc20c66cef67.453e9accab9bd384.2f8001b9c63f911f.e80767f232ce304d
+ 67579ed3f6732d79
+
+VPUNPCKHDQ_128(reg)
+ before
+ c777b7c0ec2aca90.402fb93c7d45da17.894c620595b73850.2151a4e7dc68e5f2
+ 65b1b027b17e4340.0208a7268bc9c265.1c904cc23feb9b1e.3cf45aadfb75178c
+ 9d528473e0fbd332.f7a420cb0d03637a.5c54536e46c3389a.5c359ef74072e418
+ cba52f10162eb715.fad0a2151fff7885.a3e4737445c94b6f.5ddfecb1c66c07c2
+ 1bbfc1c7aa6e3eb7
+ after
+ 0000000000000000.0000000000000000.5c54536e1c904cc2.46c3389a3feb9b1e
+ 65b1b027b17e4340.0208a7268bc9c265.1c904cc23feb9b1e.3cf45aadfb75178c
+ 9d528473e0fbd332.f7a420cb0d03637a.5c54536e46c3389a.5c359ef74072e418
+ cba52f10162eb715.fad0a2151fff7885.a3e4737445c94b6f.5ddfecb1c66c07c2
+ 1bbfc1c7aa6e3eb7
+VPUNPCKHDQ_128(mem)
+ before
+ 72a2972507844323.4bf8ae6aeea22b93.e958a8f2dcc9bfb0.4f8ea942d88b104a
+ 3d52ecb7fabbd331.7995fced05e36b58.9f07ae4d606ef227.ba9def449c94c2d6
+ 5a9c3b699e1ea90e.b1ca1505f67eb212.f8ab3112c8facd17.425c43e42c719ec0
+ a44b012810b982e6.4ee1f51f5efe3d6a.d00eab2c2f770eac.4118a08f25addfb3
+ 141d02b123d4c25c
+ after
+ 72a2972507844323.4bf8ae6aeea22b93.e958a8f2dcc9bfb0.4f8ea942d88b104a
+ 3d52ecb7fabbd331.7995fced05e36b58.9f07ae4d606ef227.ba9def449c94c2d6
+ 0000000000000000.0000000000000000.e958a8f29f07ae4d.dcc9bfb0606ef227
+ a44b012810b982e6.4ee1f51f5efe3d6a.d00eab2c2f770eac.4118a08f25addfb3
+ 141d02b123d4c25c
+
+VPUNPCKHDQ_128(reg)
+ before
+ 18b766b7c0738367.f72db8de6b991ae4.ae2798a5d8f0470f.02fd9a89b2f36f11
+ a732c60b9b155e7f.2e0cde79cbc92d35.2ce8fb0400df0eab.6c4479156c7aad73
+ 1eda201b4d468f51.27b6eee44d557604.246f18a97357ccea.e9afc5ba7a1783fe
+ dafa6f5275935189.bdf5640b0d4ab37e.f20aedffcde4be79.540af865f7d6aedd
+ 8b20900200c3ea3d
+ after
+ 0000000000000000.0000000000000000.246f18a92ce8fb04.7357ccea00df0eab
+ a732c60b9b155e7f.2e0cde79cbc92d35.2ce8fb0400df0eab.6c4479156c7aad73
+ 1eda201b4d468f51.27b6eee44d557604.246f18a97357ccea.e9afc5ba7a1783fe
+ dafa6f5275935189.bdf5640b0d4ab37e.f20aedffcde4be79.540af865f7d6aedd
+ 8b20900200c3ea3d
+VPUNPCKHDQ_128(mem)
+ before
+ 69bf087eb0ebf349.35dfb01bac87e1d2.cb96bcda26b39dce.f1037671a9131f04
+ c9b1dcc32459852e.8cd5dde490ae7ad8.2f64733db49cf322.7fa8ad6da36f2d36
+ 89c389bf77195b17.3b28f418bd955a48.c32d0420d4126fa3.f743905e588522bc
+ 83c18a5dc6383231.9e24f024cec7bbce.65bceb6fa120ce80.b4201ab063e03a42
+ 148d47cf610cb373
+ after
+ 69bf087eb0ebf349.35dfb01bac87e1d2.cb96bcda26b39dce.f1037671a9131f04
+ c9b1dcc32459852e.8cd5dde490ae7ad8.2f64733db49cf322.7fa8ad6da36f2d36
+ 0000000000000000.0000000000000000.cb96bcda2f64733d.26b39dceb49cf322
+ 83c18a5dc6383231.9e24f024cec7bbce.65bceb6fa120ce80.b4201ab063e03a42
+ 148d47cf610cb373
+
+VBROADCASTSS_128(reg)
+ before
+ 72d51328ed96c7fc.95775a892cc1c5a8.1115cd7260d0da16.efdca41638d3cce2
+ 29437b25a409b388.99b0782fc5c1d1a7.f046886f0e3df2cb.3f5aac02b43524f8
+ 9725793421f1b2c4.6c3a5d3bae42125b.97051b8774994099.2f027d1d325494ec
+ 16c50bbf01da025b.ebdf8699035344f0.629c84272f71002d.9ca09555cd3cd5eb
+ 63007094a2f8a620
+ after
+ 72d51328ed96c7fc.95775a892cc1c5a8.1115cd7260d0da16.efdca41638d3cce2
+ 29437b25a409b388.99b0782fc5c1d1a7.f046886f0e3df2cb.3f5aac02b43524f8
+ 9725793421f1b2c4.6c3a5d3bae42125b.97051b8774994099.2f027d1d325494ec
+ 16c50bbf01da025b.ebdf8699035344f0.629c84272f71002d.9ca09555cd3cd5eb
+ 63007094a2f8a620
+VBROADCASTSS_128(mem)
+ before
+ 5eed88c8cc94c1b8.04702c34df51ddfa.f06c7035dffd2391.ad58beb9db506e33
+ 6a355adc681ce3de.bb71d9fd58e27f4d.58ad96fb5e4e6a6a.d485c5ab13c2c557
+ 64a263bc919dc8bf.98160c88071726ff.006e74d89d51d6a9.336f966873534244
+ 26011e5463222c87.f8aac340897e0cbd.c27a87b6b7132277.26612c5c989021a6
+ 09a983f31d049e2a
+ after
+ 5eed88c8cc94c1b8.04702c34df51ddfa.f06c7035dffd2391.ad58beb9db506e33
+ 0000000000000000.0000000000000000.db506e33db506e33.db506e33db506e33
+ 64a263bc919dc8bf.98160c88071726ff.006e74d89d51d6a9.336f966873534244
+ 26011e5463222c87.f8aac340897e0cbd.c27a87b6b7132277.26612c5c989021a6
+ 09a983f31d049e2a
+
+VBROADCASTSS_128(reg)
+ before
+ 389197999f3cf47c.8d1e0890fbb8ca61.3578f99179a36e33.7b9f4983c99e0c03
+ 0e6664bab9c26047.75c59b5c756a5f7a.accdabe77310870c.07a73829ee014e77
+ e974e7c208251d38.bac155a5ec44a6fd.baf5d3ae145395f4.425fcf964345a400
+ 24071b1d27ee69fb.38e0b1557c535d17.b93c6f53f8f8d299.09938bb5e378ccc9
+ 360fe672eba580ff
+ after
+ 389197999f3cf47c.8d1e0890fbb8ca61.3578f99179a36e33.7b9f4983c99e0c03
+ 0e6664bab9c26047.75c59b5c756a5f7a.accdabe77310870c.07a73829ee014e77
+ e974e7c208251d38.bac155a5ec44a6fd.baf5d3ae145395f4.425fcf964345a400
+ 24071b1d27ee69fb.38e0b1557c535d17.b93c6f53f8f8d299.09938bb5e378ccc9
+ 360fe672eba580ff
+VBROADCASTSS_128(mem)
+ before
+ a69f5eb976d97dcd.1b6afc38b3ab7e3b.ccec2b5a42a23ef4.06ee7a40ba897aa4
+ 350f6e76a11f7f60.29eb867d47e799a5.50b23f9e5a3d06bf.fd56f0e2f694cbc4
+ bf2a9296878341e4.acd4b65a7f2ff5e4.a1fe6a0fdf3070a5.fac2cda649a5ffa3
+ 20bd460344128084.fe72863af80ed0a5.9b9c2698ed8839d1.597c0ef74e4753ed
+ 77d1ae40a2060350
+ after
+ a69f5eb976d97dcd.1b6afc38b3ab7e3b.ccec2b5a42a23ef4.06ee7a40ba897aa4
+ 0000000000000000.0000000000000000.ba897aa4ba897aa4.ba897aa4ba897aa4
+ bf2a9296878341e4.acd4b65a7f2ff5e4.a1fe6a0fdf3070a5.fac2cda649a5ffa3
+ 20bd460344128084.fe72863af80ed0a5.9b9c2698ed8839d1.597c0ef74e4753ed
+ 77d1ae40a2060350
+
+VBROADCASTSS_128(reg)
+ before
+ ae0da9efe06e4a75.349407aaf5d7f86c.7d11f4884e106493.1958f125a1511d70
+ 5b7cfb6fa50c650b.d67b5078b6de64ca.84fdfbb21cc2ed5b.f9fd47a21695d8ae
+ da69a12c8c6b90bc.e43e9d58a23482c8.6e829823feaea9a9.1658a2fb696225b6
+ 8622959232170634.39a96a35d5e40c92.99ebc5479163d228.4c36801cb5c4c1b5
+ 77615cf116c568d6
+ after
+ ae0da9efe06e4a75.349407aaf5d7f86c.7d11f4884e106493.1958f125a1511d70
+ 5b7cfb6fa50c650b.d67b5078b6de64ca.84fdfbb21cc2ed5b.f9fd47a21695d8ae
+ da69a12c8c6b90bc.e43e9d58a23482c8.6e829823feaea9a9.1658a2fb696225b6
+ 8622959232170634.39a96a35d5e40c92.99ebc5479163d228.4c36801cb5c4c1b5
+ 77615cf116c568d6
+VBROADCASTSS_128(mem)
+ before
+ 73a6b267aa73d646.bdf1d50e329d0521.b18734fd6cfabe56.5f86808b716aa585
+ 1bd0fe688adac631.da235c0a2988c72c.28a5759b8283563d.1d9dc45939515d6c
+ 4dadbce2d404f5c2.390427f3b2658804.79d0abfb348a8e76.307d8d1e85a43888
+ e40769bfa4ff1f25.36e0303669bf8653.82d251099e1b232b.f272d847f2ed7085
+ c0c89f3e1bba4111
+ after
+ 73a6b267aa73d646.bdf1d50e329d0521.b18734fd6cfabe56.5f86808b716aa585
+ 0000000000000000.0000000000000000.716aa585716aa585.716aa585716aa585
+ 4dadbce2d404f5c2.390427f3b2658804.79d0abfb348a8e76.307d8d1e85a43888
+ e40769bfa4ff1f25.36e0303669bf8653.82d251099e1b232b.f272d847f2ed7085
+ c0c89f3e1bba4111
+
+VPMOVSXDQ_128(reg)
+ before
+ f7cae0719d97e9d6.bcac80ed15d7ff88.2d03753deb22fbc5.1e77e4b1da43d088
+ f1c6964b130ea280.b0667d5743965215.7ab8f176d41a2407.288ddee0070d52ba
+ 0b06be371aada9bc.9e02dde94b4ad4f8.784da04cbf343cc5.7edfbd803e8565ed
+ a1d752a34d003a36.604b1a8f49ff415e.850c7f2b48fb80aa.fb38fc7e9eb8c54c
+ 7a6517c740b12e04
+ after
+ f7cae0719d97e9d6.bcac80ed15d7ff88.2d03753deb22fbc5.1e77e4b1da43d088
+ 0000000000000000.0000000000000000.000000007edfbd80.000000003e8565ed
+ 0b06be371aada9bc.9e02dde94b4ad4f8.784da04cbf343cc5.7edfbd803e8565ed
+ a1d752a34d003a36.604b1a8f49ff415e.850c7f2b48fb80aa.fb38fc7e9eb8c54c
+ 7a6517c740b12e04
+VPMOVSXDQ_128(mem)
+ before
+ d9328b46427c5b41.0f8550fa49919099.d40fb23558c05473.fc42887f0cfc2c63
+ f26bd2e6c026092e.b25cb3a8a9eee892.d41920c79499ca62.383bb9b4a6c27c9c
+ a3dc6a95d5baf3f7.e4a8771a09a37ecc.3e34e1311a965f58.97430d36b3d9ab00
+ c651ce3e9d45d6ca.02b499ba063b8df4.ec2d6f6005c4ce81.73a58171cecef73c
+ 2aaf0fd1942c99fb
+ after
+ d9328b46427c5b41.0f8550fa49919099.d40fb23558c05473.fc42887f0cfc2c63
+ 0000000000000000.0000000000000000.fffffffffc42887f.000000000cfc2c63
+ a3dc6a95d5baf3f7.e4a8771a09a37ecc.3e34e1311a965f58.97430d36b3d9ab00
+ c651ce3e9d45d6ca.02b499ba063b8df4.ec2d6f6005c4ce81.73a58171cecef73c
+ 2aaf0fd1942c99fb
+
+VPMOVSXDQ_128(reg)
+ before
+ 16abb5c3a07fd0ea.38957bcd35d26ed0.68ce13f53c4252b6.bcd0483e722ed408
+ 95e66eb18f53d6b4.d675eb2eb96d7738.7240e338464409bd.88e9e7b97ce12d19
+ 01ac3609fc35e806.7abd9c4e4422ad2c.7c5704edc0ceeeb6.2d44c8bb40e795e2
+ b849093684b1428c.01390917f2fecbd9.e25f7382476b3c4c.88ac6732d94fc78c
+ 73ef410963228046
+ after
+ 16abb5c3a07fd0ea.38957bcd35d26ed0.68ce13f53c4252b6.bcd0483e722ed408
+ 0000000000000000.0000000000000000.000000002d44c8bb.0000000040e795e2
+ 01ac3609fc35e806.7abd9c4e4422ad2c.7c5704edc0ceeeb6.2d44c8bb40e795e2
+ b849093684b1428c.01390917f2fecbd9.e25f7382476b3c4c.88ac6732d94fc78c
+ 73ef410963228046
+VPMOVSXDQ_128(mem)
+ before
+ cbd7d12cfc6e7c3a.1408e4a4c2511ff1.48b5ae76e00c8e6a.ffa32a6276a8312c
+ 6c319387bd3e7695.7337c2be53a3bde2.29fd08582959b10c.317127f9ea0f0602
+ 33c90306c49f2b82.2f209ff2d233550b.81dc91a7eaf0f2ea.d31365b33f2efa79
+ fa6b9d952d9c572e.a51077abdb8b2617.2c20c7513edd0b31.41d7e0fc0f91473d
+ d7079440f9c32afc
+ after
+ cbd7d12cfc6e7c3a.1408e4a4c2511ff1.48b5ae76e00c8e6a.ffa32a6276a8312c
+ 0000000000000000.0000000000000000.ffffffffffa32a62.0000000076a8312c
+ 33c90306c49f2b82.2f209ff2d233550b.81dc91a7eaf0f2ea.d31365b33f2efa79
+ fa6b9d952d9c572e.a51077abdb8b2617.2c20c7513edd0b31.41d7e0fc0f91473d
+ d7079440f9c32afc
+
+VPMOVSXDQ_128(reg)
+ before
+ f1f07eeb9650df60.9ee2de211341b6c4.315347560b396ab2.07932541422cb80d
+ eadd996984c5a115.fbfc4194929a0371.30350a5dfec95e8a.ec02276311eab7a9
+ 201ce1275facadc8.ed8342dcc7b4fb61.fc02bb2d4ec53e48.b8394aa3c822c232
+ eef8528fc2943f25.50445de3cd9a5abf.f20659339abb469b.470409ed82e196d3
+ 752ee02d5c32efb9
+ after
+ f1f07eeb9650df60.9ee2de211341b6c4.315347560b396ab2.07932541422cb80d
+ 0000000000000000.0000000000000000.ffffffffb8394aa3.ffffffffc822c232
+ 201ce1275facadc8.ed8342dcc7b4fb61.fc02bb2d4ec53e48.b8394aa3c822c232
+ eef8528fc2943f25.50445de3cd9a5abf.f20659339abb469b.470409ed82e196d3
+ 752ee02d5c32efb9
+VPMOVSXDQ_128(mem)
+ before
+ 1e854b4f71218810.afbce90f4a0693d7.000b0f97c159dcb8.6e8cddd97c37b12d
+ 1ed3c640debb1e03.c1b5a0119290e48b.d9a4d3e3bffc3c77.cce1458d90c3bcaa
+ 51e5ceeabe0b6dbf.7e2f750336bd6fed.b7db25b3e18f3729.68518bba73eea2c0
+ 9387de3b2d1d306f.44766350d31a70a8.767b81f3461f88fa.9e28adccc041a118
+ cab2a72f144af361
+ after
+ 1e854b4f71218810.afbce90f4a0693d7.000b0f97c159dcb8.6e8cddd97c37b12d
+ 0000000000000000.0000000000000000.000000006e8cddd9.000000007c37b12d
+ 51e5ceeabe0b6dbf.7e2f750336bd6fed.b7db25b3e18f3729.68518bba73eea2c0
+ 9387de3b2d1d306f.44766350d31a70a8.767b81f3461f88fa.9e28adccc041a118
+ cab2a72f144af361
+
+VPMOVSXWD_128(reg)
+ before
+ 483b734f0a94d545.bf85721d48fe2540.6dd6676405322269.f251638f07b7ed15
+ 740e0f983fab8270.b3aa067e2ab9065e.579a7bab6791c2db.072a4873436320a6
+ aa7876764e1c3790.4ac41649f05a8ff4.5c109d9195c48cab.90d0ab8b1330dedb
+ 46c5a455d372304e.609d1f6ab6ee7e2e.da82c8832c56bc84.6b1008c49529e2de
+ 73b5db08e55ae9db
+ after
+ 483b734f0a94d545.bf85721d48fe2540.6dd6676405322269.f251638f07b7ed15
+ 0000000000000000.0000000000000000.ffff90d0ffffab8b.00001330ffffdedb
+ aa7876764e1c3790.4ac41649f05a8ff4.5c109d9195c48cab.90d0ab8b1330dedb
+ 46c5a455d372304e.609d1f6ab6ee7e2e.da82c8832c56bc84.6b1008c49529e2de
+ 73b5db08e55ae9db
+VPMOVSXWD_128(mem)
+ before
+ 848da1451ed0afff.a44195a26c3aa959.d1029ccd96808d3a.2b3df8ebc7d38d13
+ 7962d5655d96f076.203846c7b2ffdd5b.78bf095eaf1c7942.ac8d2a3603c83c04
+ 3002f356bdb8676b.16f6b232434d0900.33a0e3091bcffd72.babe59d17cc00502
+ 843777035a43d20b.e1c7d54dbbb069f5.dd71a4baf6a4d6f7.af1b8027cc4723ba
+ e8f29ea391ead3d7
+ after
+ 848da1451ed0afff.a44195a26c3aa959.d1029ccd96808d3a.2b3df8ebc7d38d13
+ 0000000000000000.0000000000000000.00002b3dfffff8eb.ffffc7d3ffff8d13
+ 3002f356bdb8676b.16f6b232434d0900.33a0e3091bcffd72.babe59d17cc00502
+ 843777035a43d20b.e1c7d54dbbb069f5.dd71a4baf6a4d6f7.af1b8027cc4723ba
+ e8f29ea391ead3d7
+
+VPMOVSXWD_128(reg)
+ before
+ c18dacb367345106.50cedd585142ea82.dff6ab86b5b539e6.51fdca5e5da7c0fd
+ 9739a7c2e9b1d9f3.7292a241bdc26efb.6bd03048cde7b47e.6d12d0df6be577af
+ c4428c3cb4eea649.c45141aabbcd18a3.e0a161ffa0d3176a.0b7a322b3c69b73a
+ a5f4568d6376f5b5.24d6367f6771a5a5.9cb53917c9049e56.09026d2ced403bca
+ 4176fbd09a74c08a
+ after
+ c18dacb367345106.50cedd585142ea82.dff6ab86b5b539e6.51fdca5e5da7c0fd
+ 0000000000000000.0000000000000000.00000b7a0000322b.00003c69ffffb73a
+ c4428c3cb4eea649.c45141aabbcd18a3.e0a161ffa0d3176a.0b7a322b3c69b73a
+ a5f4568d6376f5b5.24d6367f6771a5a5.9cb53917c9049e56.09026d2ced403bca
+ 4176fbd09a74c08a
+VPMOVSXWD_128(mem)
+ before
+ 91a25a025e1301a7.969a012193d502e3.6cecfdacdbbad12e.fa58b4fce50684ed
+ d35105ae5629bb4c.f3828a65df98097e.7a60121e36b35769.55d5ce1a8f6506dc
+ e55179c09dc1aaa6.18f6ebc3e34a4532.28fef2bf9168f583.0b7a84de64ae60ce
+ a16c30244fe78ae0.614422a93c78f3ac.5492187d0be564a8.7691d0b2ff6dce70
+ f467b004fd2c8b6d
+ after
+ 91a25a025e1301a7.969a012193d502e3.6cecfdacdbbad12e.fa58b4fce50684ed
+ 0000000000000000.0000000000000000.fffffa58ffffb4fc.ffffe506ffff84ed
+ e55179c09dc1aaa6.18f6ebc3e34a4532.28fef2bf9168f583.0b7a84de64ae60ce
+ a16c30244fe78ae0.614422a93c78f3ac.5492187d0be564a8.7691d0b2ff6dce70
+ f467b004fd2c8b6d
+
+VPMOVSXWD_128(reg)
+ before
+ df48203ef979d472.e46fa8c689a71727.2ab62a8186ac4e98.d8e80043bd376303
+ 95801ace90e0e52b.8b265c92660e0ca7.cf9800b95b7494a1.91cb27fcc669acc1
+ 705b9c1f5debf943.705dc8750327268b.ac389ebc5a5cff74.5c0907963f88fc0e
+ cd24a19dfc284d67.70df69597cff2000.1de102f51defccbd.136c1efc469f0f15
+ 93c1e71af7baa102
+ after
+ df48203ef979d472.e46fa8c689a71727.2ab62a8186ac4e98.d8e80043bd376303
+ 0000000000000000.0000000000000000.00005c0900000796.00003f88fffffc0e
+ 705b9c1f5debf943.705dc8750327268b.ac389ebc5a5cff74.5c0907963f88fc0e
+ cd24a19dfc284d67.70df69597cff2000.1de102f51defccbd.136c1efc469f0f15
+ 93c1e71af7baa102
+VPMOVSXWD_128(mem)
+ before
+ b8d4dedc6de56d03.092825b40b221d43.677ab92ceba1b831.7ede27d240b93627
+ 5e71802fc42d3041.7eb424d02366a582.31f836d96f19a84b.2a7c09be60467a5f
+ 616347fd199da5eb.89129a5de27f20d0.ab265b4b2173ac7a.7f08a4261823d410
+ 9e78b13388428a2b.868f84c7e3facbda.afd0a47020bc82e9.d8cbf57405db80e7
+ 9114f715c2fbb990
+ after
+ b8d4dedc6de56d03.092825b40b221d43.677ab92ceba1b831.7ede27d240b93627
+ 0000000000000000.0000000000000000.00007ede000027d2.000040b900003627
+ 616347fd199da5eb.89129a5de27f20d0.ab265b4b2173ac7a.7f08a4261823d410
+ 9e78b13388428a2b.868f84c7e3facbda.afd0a47020bc82e9.d8cbf57405db80e7
+ 9114f715c2fbb990
+
+VDIVPS_128(reg)
+ before
+ 052ea676ec0ebcb6.ef7a39be2c27992d.d276dd7bc361e24c.1ac28e338500e4c5
+ 9264fe011ea0c506.31365c8821588f1f.c715a1e31e42a0d2.c8c894806e498f39
+ 9204fc24f43e102b.4078947f84e2272a.c2b6cd6d8f294317.95ae3244f7a53f72
+ 63589a490b72d8d2.f80c5f8e70d01e7d.1fa65b83b2a005c7.5d3fe4693b1faf9c
+ fc4826dc57c49ce2
+ after
+ 0000000000000000.0000000000000000.e6e64333ab1bae3c.ab05cb8f72a1908e
+ 9264fe011ea0c506.31365c8821588f1f.c715a1e31e42a0d2.c8c894806e498f39
+ 9204fc24f43e102b.4078947f84e2272a.c2b6cd6d8f294317.95ae3244f7a53f72
+ 63589a490b72d8d2.f80c5f8e70d01e7d.1fa65b83b2a005c7.5d3fe4693b1faf9c
+ fc4826dc57c49ce2
+VDIVPS_128(mem)
+ before
+ 4e95758a669fc271.60add6deffcb5aa6.35be38a1022e3042.3a32499324352290
+ 2ff24c5d84bcdc74.e44fac4e6bd2d254.d3599ba4550919a5.6fa392088074d81b
+ 7a2b2743ce28a818.4d891605eb157b88.adab0583866c94d3.1a48324e63e86117
+ 0d0c822660eee089.f5a9116f1c2092ed.a17ef02ab0635ef8.976c26d1681df92e
+ 425a68fd2c9fde0c
+ after
+ 4e95758a669fc271.60add6deffcb5aa6.35be38a1022e3042.3a32499324352290
+ 2ff24c5d84bcdc74.e44fac4e6bd2d254.d3599ba4550919a5.6fa392088074d81b
+ 0000000000000000.0000000000000000.dd126db77f800000.74eade3f9ba52317
+ 0d0c822660eee089.f5a9116f1c2092ed.a17ef02ab0635ef8.976c26d1681df92e
+ 425a68fd2c9fde0c
+
+VDIVPS_128(reg)
+ before
+ 7760f63e4afb4a5e.c360d9f4541a40f2.3af99af89a7d5330.8a9fda85f0fb3340
+ 92c8cc015ebc7ad0.78f5a998c9b98680.76c7ac0c00bafafd.44da3e81613fcfd5
+ efdfe4b0056faa0e.08956dfed9d66c5e.065d4418ea62c2ff.abfa9908203bede6
+ eaf13bb8db9e15c3.4e0da112a07dafb9.47085c86f502e8e2.9acd650848fc4a9d
+ ef1d206bf58da227
+ after
+ 0000000000000000.0000000000000000.6f3b6db680000000.e98801f857c2a1a1
+ 92c8cc015ebc7ad0.78f5a998c9b98680.76c7ac0c00bafafd.44da3e81613fcfd5
+ efdfe4b0056faa0e.08956dfed9d66c5e.065d4418ea62c2ff.abfa9908203bede6
+ eaf13bb8db9e15c3.4e0da112a07dafb9.47085c86f502e8e2.9acd650848fc4a9d
+ ef1d206bf58da227
+VDIVPS_128(mem)
+ before
+ 85b8451f44fab0af.de49ce867bd8f89b.2829c1c03bbb0abc.9313f2c4bc25a854
+ 3768500f51503162.2935988582a68f43.71b44af5c59b3a95.47cc013cdc573dfe
+ e3fabe27379ae16c.26ff95208a961667.047cb79b5b29fb6d.bf7d855cf025e58f
+ 633a095312e47cf8.31f4c2c53233c8b2.bf4b84a018720973.58747a8f951ad9b1
+ 6cfbdd4166c35811
+ after
+ 85b8451f44fab0af.de49ce867bd8f89b.2829c1c03bbb0abc.9313f2c4bc25a854
+ 3768500f51503162.2935988582a68f43.71b44af5c59b3a95.47cc013cdc573dfe
+ 0000000000000000.0000000000000000.7f800000c9547549.f4307f8e5fa6501f
+ 633a095312e47cf8.31f4c2c53233c8b2.bf4b84a018720973.58747a8f951ad9b1
+ 6cfbdd4166c35811
+
+VDIVPS_128(reg)
+ before
+ 585fa8deffaa9c5a.95f3af7fff3bbd32.a5601adf140ae2d1.7cee2dee198120d0
+ 78ecd9d2fd5de239.53f32b9719aa6148.e08f98dacca69f70.19312e737963fbb3
+ 28ed6c89fc686659.7b04f9877d3d2464.3ccd3b22f7933d3a.70e0041a54225746
+ c4b05b7097556467.e7f3963c4601c1b2.1766fc24305df6dc.5fc72acec7cdefb6
+ c0b21c7dee6d802e
+ after
+ 0000000000000000.0000000000000000.ff800000dbc02c2a.000000e4f10db407
+ 78ecd9d2fd5de239.53f32b9719aa6148.e08f98dacca69f70.19312e737963fbb3
+ 28ed6c89fc686659.7b04f9877d3d2464.3ccd3b22f7933d3a.70e0041a54225746
+ c4b05b7097556467.e7f3963c4601c1b2.1766fc24305df6dc.5fc72acec7cdefb6
+ c0b21c7dee6d802e
+VDIVPS_128(mem)
+ before
+ 716c5612e410c6db.a87fa4f16bb3170f.758c7da09101f55f.cca5d84a14910701
+ 4cc2557ac5c17de8.30a74179130bbcfc.ff9b29a1794a7c97.b6d7cc023ebbab56
+ 2e81949fae8c6182.b87431752beb8fdb.63ec192a1be71285.3348d3b64b652086
+ f4728f6ebb7e2dd5.9c326d5050decb57.7b4ac62692e47256.9d44e9d4d61da03e
+ 51170bc67c6e672a
+ after
+ 716c5612e410c6db.a87fa4f16bb3170f.758c7da09101f55f.cca5d84a14910701
+ 4cc2557ac5c17de8.30a74179130bbcfc.ff9b29a1794a7c97.b6d7cc023ebbab56
+ 0000000000000000.0000000000000000.ffdb29a1ff800000.29a68da269a5a2ab
+ f4728f6ebb7e2dd5.9c326d5050decb57.7b4ac62692e47256.9d44e9d4d61da03e
+ 51170bc67c6e672a
+
+VANDPS_256(reg)
+ before
+ ac0d33fad8e5b3f5.7864c2d306a29e0c.382df2751d70ad1d.2483ae83fb4d5935
+ 08715fdb860dbe4c.9722a9bbae056f54.e8b1bd522f2e71d8.3a614b2c712f834f
+ c2918ad52372c5db.2d77c111cdb25ed9.0809c95221a35236.9ab11b0d1095abd0
+ 37b7b1544ba1044d.163185c07fb525c6.f48212e1905c8ee0.1e3f9a12f68c8ee3
+ a3d742283c1fe8b5
+ after
+ 00110ad102008448.052281118c004e50.0801895221225010.1a210b0c10058340
+ 08715fdb860dbe4c.9722a9bbae056f54.e8b1bd522f2e71d8.3a614b2c712f834f
+ c2918ad52372c5db.2d77c111cdb25ed9.0809c95221a35236.9ab11b0d1095abd0
+ 37b7b1544ba1044d.163185c07fb525c6.f48212e1905c8ee0.1e3f9a12f68c8ee3
+ a3d742283c1fe8b5
+VANDPS_256(mem)
+ before
+ 05449139005a7571.c130cec49925b64e.2f1a71b6e11b8047.0768956b17e45f85
+ 205402325d4af044.bd48df92a98a188b.52ff01de0eef2d89.9f074c5d53c701cf
+ d0d1110070fa165a.874adf28185d66b0.5cacb224223de6b8.17ab3521df91b26a
+ f1883a8e5576a3de.7c84caf38229db69.29edfe743b116800.cba04b2458cfac03
+ 16318ad3590c2c46
+ after
+ 05449139005a7571.c130cec49925b64e.2f1a71b6e11b8047.0768956b17e45f85
+ 205402325d4af044.bd48df92a98a188b.52ff01de0eef2d89.9f074c5d53c701cf
+ 00440030004a7040.8100ce808900100a.021a0196000b0001.0700044913c40185
+ f1883a8e5576a3de.7c84caf38229db69.29edfe743b116800.cba04b2458cfac03
+ 16318ad3590c2c46
+
+VANDPS_256(reg)
+ before
+ 56abef987fd56dde.5f45fac727ca53fd.f6409c60827bb461.958d63ba72786f8c
+ e55b75e165b5ac78.f6d4cc990203e1e2.52cc52dab4dd2d44.7c5a5de2e57eb688
+ 218b1719a73825c0.92012bef032d0aba.ec72e7ccb5dd82c0.ba1e66d9b02dfa21
+ 6487d4ace2eb1461.0f9796b5455289b1.207f57a42007ee7e.2ba6fc89ee93f783
+ abbe99e0bbbb68d9
+ after
+ 210b150125302440.92000889020100a2.404042c8b4dd0040.381a44c0a02cb200
+ e55b75e165b5ac78.f6d4cc990203e1e2.52cc52dab4dd2d44.7c5a5de2e57eb688
+ 218b1719a73825c0.92012bef032d0aba.ec72e7ccb5dd82c0.ba1e66d9b02dfa21
+ 6487d4ace2eb1461.0f9796b5455289b1.207f57a42007ee7e.2ba6fc89ee93f783
+ abbe99e0bbbb68d9
+VANDPS_256(mem)
+ before
+ 1532bbc834b20b50.0c9da506b259b507.496486d7e5801cf2.4a3e9ecd92e6ae2d
+ 47cdde2f75839a14.73188893b20e4360.1c327941fec37daa.c6fdb8b3a606fe77
+ 1c5d7c00993ad150.f74377bf7e97fb16.64ceeadfad256904.f007a2c2f9f31a08
+ 70ac1327bce46e31.f26b70f6b37f18d5.fc04559e0db49b2d.24a75767263a3d8d
+ be2ad30cc966a4b2
+ after
+ 1532bbc834b20b50.0c9da506b259b507.496486d7e5801cf2.4a3e9ecd92e6ae2d
+ 47cdde2f75839a14.73188893b20e4360.1c327941fec37daa.c6fdb8b3a606fe77
+ 05009a0834820a10.00188002b2080100.08200041e4801ca2.423c98818206ae25
+ 70ac1327bce46e31.f26b70f6b37f18d5.fc04559e0db49b2d.24a75767263a3d8d
+ be2ad30cc966a4b2
+
+VANDPS_256(reg)
+ before
+ 1adc121e7f038a23.1f871e90fb8c2be2.c2dc6fa5ec52d74a.c29f36683a7cd051
+ 9309110ae49e2d8b.04ba1927713ec590.c1e26e36c69c7421.916d0a2b5187c49b
+ 87fdcb3a93c2c796.fd1180d83b07f767.4cc96b17dcea2b05.45384bd16ee33338
+ 51033c1c28fc95f1.e558d08f74f27e92.c0dd61b2cbc838a3.b9ce7748ac9cd853
+ cbf9097b27bc7119
+ after
+ 8309010a80820582.041000003106c500.40c06a16c4882001.01280a0140830018
+ 9309110ae49e2d8b.04ba1927713ec590.c1e26e36c69c7421.916d0a2b5187c49b
+ 87fdcb3a93c2c796.fd1180d83b07f767.4cc96b17dcea2b05.45384bd16ee33338
+ 51033c1c28fc95f1.e558d08f74f27e92.c0dd61b2cbc838a3.b9ce7748ac9cd853
+ cbf9097b27bc7119
+VANDPS_256(mem)
+ before
+ 55867e56fc51b7b5.4d68601b40d7d248.975a8439390c163d.77694c752ec1d6a6
+ 354151c547676954.d67933a377dfbc46.f1e518c0a55f7b96.ceba28cba26142bb
+ 46f5fdb423094122.4a80b22068a18d98.cdc30812d5f969c7.211df220c234b78e
+ 6370000fac43fc4a.04cad8feafa781ea.09c1d019e4e69bfc.ccdca4e02bc773ca
+ 2b433c7778a5b01c
+ after
+ 55867e56fc51b7b5.4d68601b40d7d248.975a8439390c163d.77694c752ec1d6a6
+ 354151c547676954.d67933a377dfbc46.f1e518c0a55f7b96.ceba28cba26142bb
+ 1500504444412114.4468200340d79040.91400000210c1214.46280841224142a2
+ 6370000fac43fc4a.04cad8feafa781ea.09c1d019e4e69bfc.ccdca4e02bc773ca
+ 2b433c7778a5b01c
+
+VXORPS_256(reg)
+ before
+ 9ba0b651455aab2f.697cd6c3ff2156f9.5fa2a1a9e980d6e7.7fabedc3ee31ce62
+ 763e0cda2f739fb0.35e6f9ba37b00a5b.b956098db1b5c63b.0d4ddafb10e6bd25
+ 19683c7fd27bc94b.a17ae7e171fbd69b.6c300d16a4d48e94.8d7213ad66112570
+ e06b41aac9fe65ab.8b041b25c80f73e5.d67ea8b15d68699c.dde814c50bbfc270
+ d7795a2f1bfb5051
+ after
+ 6f5630a5fd0856fb.949c1e5b464bdcc0.d566049b156148af.803fc95676f79855
+ 763e0cda2f739fb0.35e6f9ba37b00a5b.b956098db1b5c63b.0d4ddafb10e6bd25
+ 19683c7fd27bc94b.a17ae7e171fbd69b.6c300d16a4d48e94.8d7213ad66112570
+ e06b41aac9fe65ab.8b041b25c80f73e5.d67ea8b15d68699c.dde814c50bbfc270
+ d7795a2f1bfb5051
+VXORPS_256(mem)
+ before
+ 58f260d7b3d28b3e.279317c9b089af7d.cd50117159f6a067.518ad6c879fe94ff
+ 3d1fa2aaef4e2e63.4a2cba4624a7e26c.442945b03fbf174b.3ba193c993214c6a
+ 60cc9c92ea7ef6ed.a482268fc1e53b25.cd5d34d0967395bd.ee0fdb1f485dca89
+ 9ec4ca7dc06b9e08.93e0580f22cef654.42b659bc7c20d6ea.c81fab36333f4d07
+ 231ffe79f0520f91
+ after
+ 58f260d7b3d28b3e.279317c9b089af7d.cd50117159f6a067.518ad6c879fe94ff
+ 3d1fa2aaef4e2e63.4a2cba4624a7e26c.442945b03fbf174b.3ba193c993214c6a
+ 65edc27d5c9ca55d.6dbfad8f942e4d11.897954c16649b72c.6a2b4501eadfd895
+ 9ec4ca7dc06b9e08.93e0580f22cef654.42b659bc7c20d6ea.c81fab36333f4d07
+ 231ffe79f0520f91
+
+VXORPS_256(reg)
+ before
+ 5c59d0561c224dd2.d3d5a9558e23e4e0.72944b32e3ee4fa4.800130600ad196fe
+ d01a1d38533c4278.dcc9b4086fb182a0.9de8fb64a1d181c2.630a35a85e939024
+ d9aee28c302b2c2c.936e678180223474.70296511f704c959.c79de48194708189
+ d46119bc4f7b459c.d58e3eacdc81b88a.46a383a582126216.8985bad5c7772458
+ 8390329113b137be
+ after
+ 09b4ffb463176e54.4fa7d389ef93b6d4.edc19e7556d5489b.a497d129cae311ad
+ d01a1d38533c4278.dcc9b4086fb182a0.9de8fb64a1d181c2.630a35a85e939024
+ d9aee28c302b2c2c.936e678180223474.70296511f704c959.c79de48194708189
+ d46119bc4f7b459c.d58e3eacdc81b88a.46a383a582126216.8985bad5c7772458
+ 8390329113b137be
+VXORPS_256(mem)
+ before
+ 9288c8a2952c74e7.1d7fc0354db9c974.7ef5b674a0dac80b.7da2538ddd888aa5
+ 923af9f368f398fe.1053d264c670f660.6a7149c8e73a2126.7071d033a4f17bb1
+ 5f723f6fa9135e30.0a2b4cb3552c060b.75cd7591cdab7f05.7a5ef60575d972e6
+ d5fc1804749783a8.65512890967a3621.7bd4b5bc6f3c9dd4.f9b3c26de9ccaaf2
+ 48bd2fd99e57617f
+ after
+ 9288c8a2952c74e7.1d7fc0354db9c974.7ef5b674a0dac80b.7da2538ddd888aa5
+ 923af9f368f398fe.1053d264c670f660.6a7149c8e73a2126.7071d033a4f17bb1
+ 00b23151fddfec19.0d2c12518bc93f14.1484ffbc47e0e92d.0dd383be7979f114
+ d5fc1804749783a8.65512890967a3621.7bd4b5bc6f3c9dd4.f9b3c26de9ccaaf2
+ 48bd2fd99e57617f
+
+VXORPS_256(reg)
+ before
+ c2c839b43006d139.d0a4ff9de38bc393.7e12646626e5c24f.58538635e9f638c1
+ c520dc6a3a6336cd.2c35702615fcda1d.b1bafba1a0fae541.e81662e956e70cf5
+ ab11146758fccee7.c47de88b23f58371.5a95eaada143dca3.07e9c7c2d31bd49f
+ d2e6de17275cd332.7646e1b82c827bbc.d5ee2bf6c44fe320.919830ae7b9c4ee9
+ 61ef1a986a7834ff
+ after
+ 6e31c80d629ff82a.e84898ad3609596c.eb2f110c01b939e2.efffa52b85fcd86a
+ c520dc6a3a6336cd.2c35702615fcda1d.b1bafba1a0fae541.e81662e956e70cf5
+ ab11146758fccee7.c47de88b23f58371.5a95eaada143dca3.07e9c7c2d31bd49f
+ d2e6de17275cd332.7646e1b82c827bbc.d5ee2bf6c44fe320.919830ae7b9c4ee9
+ 61ef1a986a7834ff
+VXORPS_256(mem)
+ before
+ 55b9ff6bbdbb420e.94ed35e64310825b.1d5dd99a49b07e29.7e13bce8a5a73564
+ 48c45d158f6f3642.4f70154046a3160e.958e4b1b988a48e5.b14e98efe2d9101c
+ 16daaf81fda2cac6.5dbc7a91cfa1cdf6.baa4b328351c941b.c9ecbb771470aef4
+ 9ac8719b2260bbc7.1b1d60467897e1bf.676d8eae3b731ff9.243921edd9f84b98
+ 1d81c7bbcdfe25b2
+ after
+ 55b9ff6bbdbb420e.94ed35e64310825b.1d5dd99a49b07e29.7e13bce8a5a73564
+ 48c45d158f6f3642.4f70154046a3160e.958e4b1b988a48e5.b14e98efe2d9101c
+ 1d7da27e32d4744c.db9d20a605b39455.88d39281d13a36cc.cf5d2407477e2578
+ 9ac8719b2260bbc7.1b1d60467897e1bf.676d8eae3b731ff9.243921edd9f84b98
+ 1d81c7bbcdfe25b2
+
+VORPS_256(reg)
+ before
+ 1010a74f8b0d76f1.b25a1f501bb3c471.e6dfc4c9dd108e17.7ab35798c79aa5a8
+ 5931bf13afb27bff.395b368a03a9a2ef.184da1889b9812a7.ce448ad1f49de157
+ 53320b75d6786f89.0a993136f74e116e.0eb5f3ee4dbca71e.3eeaa347de899030
+ 5c5d85e09ceb8f3a.03de8c4112accd19.2461b6678f078a26.a8721ee5a2696e5f
+ e7a878975b493611
+ after
+ 5b33bf77fffa7fff.3bdb37bef7efb3ef.1efdf3eedfbcb7bf.feeeabd7fe9df177
+ 5931bf13afb27bff.395b368a03a9a2ef.184da1889b9812a7.ce448ad1f49de157
+ 53320b75d6786f89.0a993136f74e116e.0eb5f3ee4dbca71e.3eeaa347de899030
+ 5c5d85e09ceb8f3a.03de8c4112accd19.2461b6678f078a26.a8721ee5a2696e5f
+ e7a878975b493611
+VORPS_256(mem)
+ before
+ d6572c492636a672.cfff2bc09c9717bf.fef7c39571d2921d.b69ee75fff05f76b
+ 534db6e71f3b78ad.0764f881720943c4.d9b052202fc91ba5.21b881423643299b
+ 3854925e606568ef.62d8e88fbbcd4ef4.6ed5b6cd699f25de.bffb807cd24c5d60
+ 62393d9808bf3463.3ba6f756126d76fb.9b326a883a5f6bf4.edb3e0796faccf66
+ 072b9da5a8f0ba5a
+ after
+ d6572c492636a672.cfff2bc09c9717bf.fef7c39571d2921d.b69ee75fff05f76b
+ 534db6e71f3b78ad.0764f881720943c4.d9b052202fc91ba5.21b881423643299b
+ d75fbeef3f3ffeff.cffffbc1fe9f57ff.fff7d3b57fdb9bbd.b7bee75fff47fffb
+ 62393d9808bf3463.3ba6f756126d76fb.9b326a883a5f6bf4.edb3e0796faccf66
+ 072b9da5a8f0ba5a
+
+VORPS_256(reg)
+ before
+ 69b1b46d19a35be7.aec8318330559637.ed1c22431477f487.3a93ea3dbe15aa12
+ 6f8f203b5f52eebb.f6cdec09f7334b94.d68463c05c760742.29c3b2d812ce9e65
+ 7512dd7d1688af7f.1814e91876660fa8.502bb83b87f7e9d8.428f3f4552950319
+ d786e79dd9d1d9e2.ee68a59bccf99d9f.b95d1d1e3085d7f6.62c40c7099779559
+ 662c9445037f0f51
+ after
+ 7f9ffd7f5fdaefff.fedded19f7774fbc.d6affbfbdff7efda.6bcfbfdd52df9f7d
+ 6f8f203b5f52eebb.f6cdec09f7334b94.d68463c05c760742.29c3b2d812ce9e65
+ 7512dd7d1688af7f.1814e91876660fa8.502bb83b87f7e9d8.428f3f4552950319
+ d786e79dd9d1d9e2.ee68a59bccf99d9f.b95d1d1e3085d7f6.62c40c7099779559
+ 662c9445037f0f51
+VORPS_256(mem)
+ before
+ 289356b1adb92e2f.f1363b0944b9a98e.55979a7d12f9b2a5.6b668cd7f4ac0d48
+ 85c7cb9eb231ad1d.1f70d32cf4cd5b2f.296b46ac66710ae5.c39103d16ef9c679
+ 599271fa2ff44a47.bc7ead7284982b73.47b12413e46d608b.1e2c7c783af74036
+ 81c2c3af3f0dbfda.26aec44791a75403.8935b09fa7f971c5.d681f538f532b42a
+ 48dd6a7d3b376102
+ after
+ 289356b1adb92e2f.f1363b0944b9a98e.55979a7d12f9b2a5.6b668cd7f4ac0d48
+ 85c7cb9eb231ad1d.1f70d32cf4cd5b2f.296b46ac66710ae5.c39103d16ef9c679
+ add7dfbfbfb9af3f.ff76fb2df4fdfbaf.7dffdefd76f9bae5.ebf78fd7fefdcf79
+ 81c2c3af3f0dbfda.26aec44791a75403.8935b09fa7f971c5.d681f538f532b42a
+ 48dd6a7d3b376102
+
+VORPS_256(reg)
+ before
+ d18cd5b3a791816a.d7213dabff89c802.b84a1517b684138e.ccc3673acb22f9bc
+ cbda3446d5cc510d.387c5bd98a7323ea.ce9f9a4e90bea4be.ec26c4d16df3b49f
+ 931382a362750d98.809f9925fdd78abf.c3f95159bade423f.c52c4251a9795d98
+ 8583bb34ea17f1b7.8b56747b73c2baac.f5a335a2d1722abe.339f60a49abfb1d3
+ 124c97b85cd16c7e
+ after
+ dbdbb6e7f7fd5d9d.b8ffdbfdfff7abff.cfffdb5fbafee6bf.ed2ec6d1edfbfd9f
+ cbda3446d5cc510d.387c5bd98a7323ea.ce9f9a4e90bea4be.ec26c4d16df3b49f
+ 931382a362750d98.809f9925fdd78abf.c3f95159bade423f.c52c4251a9795d98
+ 8583bb34ea17f1b7.8b56747b73c2baac.f5a335a2d1722abe.339f60a49abfb1d3
+ 124c97b85cd16c7e
+VORPS_256(mem)
+ before
+ 3eff64770cbc4ac2.fd75db67073e3815.356c67c7093f6fde.bfeb4397700598e7
+ 938444cfc58b06ce.5736dfa658771f5e.5aafeef6da5a6481.7c1b75a23424c865
+ eda7b2aba44a5dcc.f012c25f774de13f.d6e986f2021f56c0.8a80c931b85af5e5
+ 28332af7c4060ae8.225580fd004dbc64.85e7a9a89e9b01c8.44663aaf98335c13
+ 0519c487713c399a
+ after
+ 3eff64770cbc4ac2.fd75db67073e3815.356c67c7093f6fde.bfeb4397700598e7
+ 938444cfc58b06ce.5736dfa658771f5e.5aafeef6da5a6481.7c1b75a23424c865
+ bfff64ffcdbf4ece.ff77dfe75f7f3f5f.7fefeff7db7f6fdf.fffb77b77425d8e7
+ 28332af7c4060ae8.225580fd004dbc64.85e7a9a89e9b01c8.44663aaf98335c13
+ 0519c487713c399a
+
+VANDNPD_256(reg)
+ before
+ 2be56327dfffc726.20f6299f42cacb50.4a4b15ec9001ea79.4375d505cada20c4
+ 101514fb7d0b4365.b1ba2a8f39a25a2d.c4407e98c2f7a829.ec5f85f3a1e671e1
+ 11f7d26de7e9e901.b74ca8b4c69a74ae.ec7fb56d32bb3120.5b7035603fcdae4a
+ 8bd599eaba27f5a6.0d7821f804bfd4fd.1d55b8d77ed8c20b.6e766237c19b932d
+ 003b8764425adeb3
+ after
+ 01e2c20482e0a800.06448030c6182482.283f816530081100.132030001e098e0a
+ 101514fb7d0b4365.b1ba2a8f39a25a2d.c4407e98c2f7a829.ec5f85f3a1e671e1
+ 11f7d26de7e9e901.b74ca8b4c69a74ae.ec7fb56d32bb3120.5b7035603fcdae4a
+ 8bd599eaba27f5a6.0d7821f804bfd4fd.1d55b8d77ed8c20b.6e766237c19b932d
+ 003b8764425adeb3
+VANDNPD_256(mem)
+ before
+ ed8c20d3df18490b.d8fc65de9151a201.91091148101d3746.b50f82433fda9796
+ 1035a970b4e1915f.56b832b609f12dbe.1ecdf29105bf59b6.0ff7101b134dec6c
+ 47029e27dbbf71db.5f55fddcbd95d288.908e42beffb1f679.87595ccc96befc3a
+ 6dbf7ce573c1a6ac.501ec1be4ac9cc0c.c21a7cba1bffc9ba.798364c363b804ac
+ 41c0236b16c8406d
+ after
+ ed8c20d3df18490b.d8fc65de9151a201.91091148101d3746.b50f82433fda9796
+ 1035a970b4e1915f.56b832b609f12dbe.1ecdf29105bf59b6.0ff7101b134dec6c
+ ed8800834b184800.8844454890008201.8100014810002640.b00882402c921392
+ 6dbf7ce573c1a6ac.501ec1be4ac9cc0c.c21a7cba1bffc9ba.798364c363b804ac
+ 41c0236b16c8406d
+
+VANDNPD_256(reg)
+ before
+ 3a5b952f4c79ec2a.5d37bd9495f0ecfe.85617ac74b1758f5.923b1c7375b690a6
+ c2a1b77da157438e.f538df215f5afffc.5b6824635d0db2f0.dbbe9fd428e10469
+ 34de83c0b0ee8246.0f8c5e79ed0a9bd3.2c80bcfd1b3716a9.786f7fc9508ce42e
+ eb5ef76415cbe5fe.8900b4875a0c7baf.55f53d03221fbfcb.47193a3e0ac4ea22
+ 228a4b1f7194d370
+ after
+ 345e008010a88040.0a840058a0000003.2480989c02320409.20416009500ce006
+ c2a1b77da157438e.f538df215f5afffc.5b6824635d0db2f0.dbbe9fd428e10469
+ 34de83c0b0ee8246.0f8c5e79ed0a9bd3.2c80bcfd1b3716a9.786f7fc9508ce42e
+ eb5ef76415cbe5fe.8900b4875a0c7baf.55f53d03221fbfcb.47193a3e0ac4ea22
+ 228a4b1f7194d370
+VANDNPD_256(mem)
+ before
+ e78c2e59a2085b45.456d0ed66d7aa761.3d605f36c36d5cbb.3213a3e10d53ea03
+ 70ec60d6b82d3dcc.9c56c5805385051b.0978da744338f923.1f26ea01785fd3fc
+ 9a765c84d00e3732.4e6716cf647a3bda.c713a12cf6790f15.78790ed000ceb563
+ 42f69e4d05b802a3.b5eaff303be48548.55ff304af93d5abb.99590cba412ccee4
+ de13df2cd605582a
+ after
+ e78c2e59a2085b45.456d0ed66d7aa761.3d605f36c36d5cbb.3213a3e10d53ea03
+ 70ec60d6b82d3dcc.9c56c5805385051b.0978da744338f923.1f26ea01785fd3fc
+ 87000e0902004201.41290a562c7aa260.3400050280450498.201101e005002803
+ 42f69e4d05b802a3.b5eaff303be48548.55ff304af93d5abb.99590cba412ccee4
+ de13df2cd605582a
+
+VANDNPD_256(reg)
+ before
+ a3f183905be68fe2.4238a21f74365d4a.2f2c7b0d75501e11.8d0604ba688f9641
+ 4440f4546d5ab1b7.7707e4e538940254.167986d4ad4943e2.4cf597695e7c7fd4
+ 1d4b2fe3a8eef856.be31e18b6edeaeec.c81d1def805b3067.6f986741f70fd0a0
+ 8a602ea9a62ca16b.f18013fc31211d40.9f643acc8913204b.d0bbf02f505446d0
+ 4c2aac2084579c91
+ after
+ 190b0ba380a44840.8830010a464aaca8.c804192b00123005.23086000a1038020
+ 4440f4546d5ab1b7.7707e4e538940254.167986d4ad4943e2.4cf597695e7c7fd4
+ 1d4b2fe3a8eef856.be31e18b6edeaeec.c81d1def805b3067.6f986741f70fd0a0
+ 8a602ea9a62ca16b.f18013fc31211d40.9f643acc8913204b.d0bbf02f505446d0
+ 4c2aac2084579c91
+VANDNPD_256(mem)
+ before
+ bfb019feb025900e.e7c9ef1206a2e7a1.edc1f9279e680b79.f999dbd664fc503b
+ 061ab1b7efcadc74.90d46e8a61dc07a5.8ec00cf5d0c033c5.300afb79aea2fce2
+ fb35f3365e503cef.e0cba57d56653d22.b149c953e3345250.a1019621039260ed
+ 7bcb586718c56eaa.35fb92577ec9c5c5.3027ad2df4d02346.a8cba93afe57b708
+ a2b42f313b7d3ede
+ after
+ bfb019feb025900e.e7c9ef1206a2e7a1.edc1f9279e680b79.f999dbd664fc503b
+ 061ab1b7efcadc74.90d46e8a61dc07a5.8ec00cf5d0c033c5.300afb79aea2fce2
+ b9a008481025000a.670981100622e000.6101f1020e280838.c9910086405c0019
+ 7bcb586718c56eaa.35fb92577ec9c5c5.3027ad2df4d02346.a8cba93afe57b708
+ a2b42f313b7d3ede
+
+VANDNPS_256(reg)
+ before
+ e90724705791311c.62a85d363a342cd2.eaaf2f847895da3a.e82833701ea164d2
+ da128464ee1ecb6e.8c9a7f8fdfaa3392.5a357a71dd53b92c.b516d7067eb1cf20
+ d11f4b7a9ab04a7f.d56c395e24323f17.e3d76f884b929e47.73be15dd300f215d
+ 2a7c761dfad4e8fb.19e9078f24d80b8d.e0e308375edbc539.feec6adf4fc415b5
+ 326c51faf7de6854
+ after
+ 010d4b1a10a00011.5164005020100c05.a1c2058802800643.42a800d9000e205d
+ da128464ee1ecb6e.8c9a7f8fdfaa3392.5a357a71dd53b92c.b516d7067eb1cf20
+ d11f4b7a9ab04a7f.d56c395e24323f17.e3d76f884b929e47.73be15dd300f215d
+ 2a7c761dfad4e8fb.19e9078f24d80b8d.e0e308375edbc539.feec6adf4fc415b5
+ 326c51faf7de6854
+VANDNPS_256(mem)
+ before
+ eb0a46194569d665.4173ffb8a715e18f.34de660efba9541f.aca343e9b1bc69ac
+ 0591c528546f1b14.7251e5b940ff72e7.0217d0c8c6b0d6fa.a5641b09e1c0c74c
+ 5ccf4a1341fef28e.1961218b5e1fd8af.5f60c3a7a1f94c49.25728c0589741bc6
+ cb8e52c6272118ff.92f1b09aa0004c92.2785ba99a7917439.8a1992484563a0c6
+ 2ea42a3eb21993f7
+ after
+ eb0a46194569d665.4173ffb8a715e18f.34de660efba9541f.aca343e9b1bc69ac
+ 0591c528546f1b14.7251e5b940ff72e7.0217d0c8c6b0d6fa.a5641b09e1c0c74c
+ ea0a02110100c461.01221a00a7008108.34c8260639090005.088340e0103c28a0
+ cb8e52c6272118ff.92f1b09aa0004c92.2785ba99a7917439.8a1992484563a0c6
+ 2ea42a3eb21993f7
+
+VANDNPS_256(reg)
+ before
+ 6f604f546b233006.309b582e23e54992.394b8f529f2f0d3c.35523189f48308f6
+ a79afdf40d0cb39e.66c2d83550554174.6abdb920f937555a.6792a563a5dbc4ab
+ 349c308b3460576d.49ce4ec9ca7dbbd1.81912a6e4aa46198.98139013d6a66685
+ 70b3e4867aac591c.b58d37d4ae6a74d4.da14dea92d026da1.a49f7085a1efa8af
+ 6603c1a525c24756
+ after
+ 1004000b30604461.090c06c88a28ba81.8100024e02802080.9801101052242204
+ a79afdf40d0cb39e.66c2d83550554174.6abdb920f937555a.6792a563a5dbc4ab
+ 349c308b3460576d.49ce4ec9ca7dbbd1.81912a6e4aa46198.98139013d6a66685
+ 70b3e4867aac591c.b58d37d4ae6a74d4.da14dea92d026da1.a49f7085a1efa8af
+ 6603c1a525c24756
+VANDNPS_256(mem)
+ before
+ bc0bfd5f7b2cfea5.b82a164f7e7bf559.85c90d44182728aa.d192d23e3fdeb422
+ 8182a19fc2388ac9.684fc154d95966d0.97504e0323c1927e.c25601971bc373c7
+ 90362a5113f2a7ee.dd6ce1002ad3ea2d.c5ec76ffeb426f7d.08ae67225d3ee63b
+ c7f113628d67113f.71cf72be0a74ba1b.ed6aff238db87bd2.01e4004aa2da492b
+ 0845c87b8623d742
+ after
+ bc0bfd5f7b2cfea5.b82a164f7e7bf559.85c90d44182728aa.d192d23e3fdeb422
+ 8182a19fc2388ac9.684fc154d95966d0.97504e0323c1927e.c25601971bc373c7
+ 3c095c4039047424.9020160b26229109.0089014418262880.1180d228241c8420
+ c7f113628d67113f.71cf72be0a74ba1b.ed6aff238db87bd2.01e4004aa2da492b
+ 0845c87b8623d742
+
+VANDNPS_256(reg)
+ before
+ 781ebc21a3a5cd2d.0180d9bd49a284e9.81c271fc17c81546.ea96675b252f71ab
+ afb8d7a898ed6698.19b0f64d65afbb18.6992d925ed5c355c.973b2893ceb20f31
+ 0862157cff86e02e.ed4ae800fd9b73f7.858ba6a527bb5706.d227c1b8a44d0f93
+ de67720974fd759b.571d2ac12c7167b3.31f8d4e96271b7f3.7524abb4c40c2dfa
+ 5eff637449fc2795
+ after
+ 0042005467028026.e44a0800981040e7.8409268002a34202.4004c128204d0082
+ afb8d7a898ed6698.19b0f64d65afbb18.6992d925ed5c355c.973b2893ceb20f31
+ 0862157cff86e02e.ed4ae800fd9b73f7.858ba6a527bb5706.d227c1b8a44d0f93
+ de67720974fd759b.571d2ac12c7167b3.31f8d4e96271b7f3.7524abb4c40c2dfa
+ 5eff637449fc2795
+VANDNPS_256(mem)
+ before
+ 678466e55028b78e.8f12ebbb94dd628d.34f4387c0f3e5477.ca275f5b390b91cd
+ 6d7f2ff1f49c9a12.75b07bfffab2e2ae.619a8e1dc10cf670.aa62446848142040
+ 4dbc3a8652658c4c.ee8e1e3f430933aa.b8dca8905eea09c9.2ef67e7d2c19a1fa
+ e106038f858e4869.54f6d0e90a6d8f2e.178703c103e149af.b12f090481a450a4
+ 9159e16be24368ed
+ after
+ 678466e55028b78e.8f12ebbb94dd628d.34f4387c0f3e5477.ca275f5b390b91cd
+ 6d7f2ff1f49c9a12.75b07bfffab2e2ae.619a8e1dc10cf670.aa62446848142040
+ 028040040020258c.8a028000044d0001.146430600e320007.40051b13310b918d
+ e106038f858e4869.54f6d0e90a6d8f2e.178703c103e149af.b12f090481a450a4
+ 9159e16be24368ed
+
+VORPD_256(reg)
+ before
+ 29c0031deb82267f.062b07f8aa248b94.05348d68eb6a32e6.58651a9ccbff714e
+ d5b06a8639ecc606.99f5c1addc3211fa.5b965228848d5a7d.5842690ed34f3ed1
+ f1741212670d832f.7431ad9a37c495c7.b3661a946e6141a0.f3ec6d0136de6b65
+ d959f72d12719ba6.74ab47abd8e7d426.6af2e11a477224fa.062ea06311b6b635
+ 6bd3801f80e6d96e
+ after
+ f5f47a967fedc72f.fdf5edbffff695ff.fbf65abceeed5bfd.fbee6d0ff7df7ff5
+ d5b06a8639ecc606.99f5c1addc3211fa.5b965228848d5a7d.5842690ed34f3ed1
+ f1741212670d832f.7431ad9a37c495c7.b3661a946e6141a0.f3ec6d0136de6b65
+ d959f72d12719ba6.74ab47abd8e7d426.6af2e11a477224fa.062ea06311b6b635
+ 6bd3801f80e6d96e
+VORPD_256(mem)
+ before
+ ffa888209d77903c.e9ab1543d5a54717.752f0cccdba58a44.da84a326ab4d3f38
+ 9e793554877799ca.7cb669c04d34c62c.538876e95b0d734c.60695c22357dcd06
+ 241201a657f1ae45.f0c6ee1015ab5394.ea8403ef74284a6b.58ed097b818e0b0f
+ 6d3f6a022bf28cd8.a027a0a0ca9529f9.16ed2ec84304cccd.1f5ca59d2c0d3500
+ 0f012cf5d1858685
+ after
+ ffa888209d77903c.e9ab1543d5a54717.752f0cccdba58a44.da84a326ab4d3f38
+ 9e793554877799ca.7cb669c04d34c62c.538876e95b0d734c.60695c22357dcd06
+ fff9bd749f7799fe.fdbf7dc3ddb5c73f.77af7eeddbadfb4c.faedff26bf7dff3e
+ 6d3f6a022bf28cd8.a027a0a0ca9529f9.16ed2ec84304cccd.1f5ca59d2c0d3500
+ 0f012cf5d1858685
+
+VORPD_256(reg)
+ before
+ 852a9bed0d823b49.55cbeb541f85efb0.e7247bda077e8508.b3907462e3acb59d
+ dd21ecf37c9190f8.b88400894eb692f9.230b7b2c68f3a26c.9d394fa8712dc008
+ 73331d72b83dc13f.7234258bd59232de.af269d008a7ebdd2.b0b43d850992ab39
+ a3ac29d6601209ca.5fa8d747cf248b8c.e6c2dcc409ae12e6.c8cdb9e7c5e7305d
+ c14f3fb9c4390ba0
+ after
+ ff33fdf3fcbdd1ff.fab4258bdfb6b2ff.af2fff2ceaffbffe.bdbd7fad79bfeb39
+ dd21ecf37c9190f8.b88400894eb692f9.230b7b2c68f3a26c.9d394fa8712dc008
+ 73331d72b83dc13f.7234258bd59232de.af269d008a7ebdd2.b0b43d850992ab39
+ a3ac29d6601209ca.5fa8d747cf248b8c.e6c2dcc409ae12e6.c8cdb9e7c5e7305d
+ c14f3fb9c4390ba0
+VORPD_256(mem)
+ before
+ 77084ce71f93fa2d.c9d80c8b0d9da545.5bac91aa5878582e.262b34e3800cdd53
+ c6c25a5ef501b731.4102c3fd5e69d15b.420ccf9f8d9b57f1.c9aca1c98b2659c5
+ 8a4ae7085f90ffd7.67784998ec03c9b8.f0930d1189984201.2d9320e2c788c4ea
+ 9f6c6ed27b4b8d4c.978499c855f5c809.400fc8ee697bd589.ac2aac9ad0bc576b
+ a3be415e415051f7
+ after
+ 77084ce71f93fa2d.c9d80c8b0d9da545.5bac91aa5878582e.262b34e3800cdd53
+ c6c25a5ef501b731.4102c3fd5e69d15b.420ccf9f8d9b57f1.c9aca1c98b2659c5
+ f7ca5effff93ff3d.c9dacfff5ffdf55f.5bacdfbfddfb5fff.efafb5eb8b2eddd7
+ 9f6c6ed27b4b8d4c.978499c855f5c809.400fc8ee697bd589.ac2aac9ad0bc576b
+ a3be415e415051f7
+
+VORPD_256(reg)
+ before
+ 6f9cdb98b6cfec38.e0f36ca9653e1ebc.2d73b2f935ce0bfa.104a7a214951ceb6
+ 6a0d77b5ccc665db.2bad5b7738766e52.85918d982717cd36.3b11a1964425e7b3
+ f1600f221ec0f88b.5b64b92a11fe393a.fb2a280fc85e4c6a.9d30b8397603ddad
+ 61e0a14a4949e1f5.4be601ad0be23aa2.ea8a7dccb32ec242.11733cf6fcf86bd0
+ 75a6a7baf10f4e47
+ after
+ fb6d7fb7dec6fddb.7bedfb7f39fe7f7a.ffbbad9fef5fcd7e.bf31b9bf7627ffbf
+ 6a0d77b5ccc665db.2bad5b7738766e52.85918d982717cd36.3b11a1964425e7b3
+ f1600f221ec0f88b.5b64b92a11fe393a.fb2a280fc85e4c6a.9d30b8397603ddad
+ 61e0a14a4949e1f5.4be601ad0be23aa2.ea8a7dccb32ec242.11733cf6fcf86bd0
+ 75a6a7baf10f4e47
+VORPD_256(mem)
+ before
+ a394776f7254423e.14d82898e8ee5bc4.d9fdafeb422f2fb4.b0fc8a3984146c69
+ 790b27039ad403e3.6796a17a983aa3a5.e0763fd2d3f0d19c.a8ce4bc4d89a858c
+ d2d53360859a4d60.b664065bf4baf444.3b1d2e4dd931df87.2e4abad84b4f4b56
+ 89bf187451b2dbe1.5e8f55a799f88c4c.c8bdf74871ff13a1.9dbdd5e177bcf874
+ 5373964bfb6fc892
+ after
+ a394776f7254423e.14d82898e8ee5bc4.d9fdafeb422f2fb4.b0fc8a3984146c69
+ 790b27039ad403e3.6796a17a983aa3a5.e0763fd2d3f0d19c.a8ce4bc4d89a858c
+ fb9f776ffad443ff.77dea9faf8fefbe5.f9ffbffbd3ffffbc.b8fecbfddc9eeded
+ 89bf187451b2dbe1.5e8f55a799f88c4c.c8bdf74871ff13a1.9dbdd5e177bcf874
+ 5373964bfb6fc892
+
+VPERMILPS_256_0x0F(reg)
+ before
+ aab7fc8271f3f95b.7c95502a17296a93.b96289ca2282a56a.612416b0b7652a15
+ 00d700f275d5c57b.8523596df50ab5a2.242b9e302be47b49.e41c076fc570e010
+ b01d9f08a4a069a0.8134ae2b07627939.fb35914651a84c96.2b724772ba2bf0be
+ 15d7d62e99e02074.4d96cc4f683c7285.9acb5c76305d52fd.14f250a6b0a2184a
+ 7968a0f5c3e111e0
+ after
+ aab7fc8271f3f95b.7c95502a17296a93.b96289ca2282a56a.612416b0b7652a15
+ 0762793907627939.b01d9f08b01d9f08.ba2bf0beba2bf0be.fb359146fb359146
+ b01d9f08a4a069a0.8134ae2b07627939.fb35914651a84c96.2b724772ba2bf0be
+ 15d7d62e99e02074.4d96cc4f683c7285.9acb5c76305d52fd.14f250a6b0a2184a
+ 7968a0f5c3e111e0
+VPERMILPS_256_0x0F(mem)
+ before
+ 37a0b24d0ff59aae.8d4fa0d2f12227a3.c3132dc534a45cb1.5d3afd2e638cca29
+ 2b650399b2e96ddd.72d2f95e47f1bada.c1784f7a88a6f3ea.a0ce6fd886c3f0c7
+ 2f850dc5c5ca479c.21acde4037d915c5.2191ad587f4ff25c.bfd3aee2368dff82
+ 20ca4ebd66a2e415.f72849e35e67740f.c02ac34c36aa1632.1695b7b70e763407
+ 005f85c2ab0bcb02
+ after
+ 37a0b24d0ff59aae.8d4fa0d2f12227a3.c3132dc534a45cb1.5d3afd2e638cca29
+ f12227a38d4fa0d2.37a0b24d0ff59aae.638cca295d3afd2e.c3132dc534a45cb1
+ 2f850dc5c5ca479c.21acde4037d915c5.2191ad587f4ff25c.bfd3aee2368dff82
+ 20ca4ebd66a2e415.f72849e35e67740f.c02ac34c36aa1632.1695b7b70e763407
+ 005f85c2ab0bcb02
+
+VPERMILPS_256_0x0F(reg)
+ before
+ db7f1471a9d7001e.da01416db1800075.4e9438b358261265.7a0f0e43c9c41a99
+ 023f602fa2670e08.3af662c1c16d56e7.833aa61cc0a22c72.2c0b082752a8bcbd
+ d1ec65693546326b.1a752ea5b277a398.f367908a3368fde3.b0eb2fe6f062b6c9
+ a4d22089fb00a7f4.57492005a1a9a2b3.f867f0694c03c364.e37cfe6bbcfec4e9
+ a188f2a2d589a44a
+ after
+ db7f1471a9d7001e.da01416db1800075.4e9438b358261265.7a0f0e43c9c41a99
+ b277a398b277a398.d1ec6569d1ec6569.f062b6c9f062b6c9.f367908af367908a
+ d1ec65693546326b.1a752ea5b277a398.f367908a3368fde3.b0eb2fe6f062b6c9
+ a4d22089fb00a7f4.57492005a1a9a2b3.f867f0694c03c364.e37cfe6bbcfec4e9
+ a188f2a2d589a44a
+VPERMILPS_256_0x0F(mem)
+ before
+ c6dc8577540f1018.d63d8cfc9221ab4e.cd40b4ceaa101165.ef86c425a7ffb8a0
+ 2e4335d6589ac57f.c579a52f96367827.582466eae8b7aada.3410072be1e91844
+ b58b7dabfa387faa.ccd1678ca2ca4b28.d4c2b24777aa293d.2450b5e5954c21fb
+ 377ed9e258f4f9c5.4692ce81536a5f00.1de615d074f64cbb.1994cac160b40d73
+ 70264329deae1955
+ after
+ c6dc8577540f1018.d63d8cfc9221ab4e.cd40b4ceaa101165.ef86c425a7ffb8a0
+ 9221ab4ed63d8cfc.c6dc8577540f1018.a7ffb8a0ef86c425.cd40b4ceaa101165
+ b58b7dabfa387faa.ccd1678ca2ca4b28.d4c2b24777aa293d.2450b5e5954c21fb
+ 377ed9e258f4f9c5.4692ce81536a5f00.1de615d074f64cbb.1994cac160b40d73
+ 70264329deae1955
+
+VPERMILPS_256_0x0F(reg)
+ before
+ 85531b8ba9c5814f.90e9c5688edbf0fd.9108d77844a1f259.0f5c0970faa6cd7f
+ b4674e526085800d.9c99be27b7f8207e.07807ddf11fb3edf.86f00c1526c669b6
+ 59aed8ea9c7b533b.37573f0def574474.0643bc2157057f3f.5e6d9aaa1362dc8c
+ d073b5bffc323683.3df2c40453051a0a.e8a091aab24af325.73a12d1bde87e12c
+ a1564355a24135c2
+ after
+ 85531b8ba9c5814f.90e9c5688edbf0fd.9108d77844a1f259.0f5c0970faa6cd7f
+ ef574474ef574474.59aed8ea59aed8ea.1362dc8c1362dc8c.0643bc210643bc21
+ 59aed8ea9c7b533b.37573f0def574474.0643bc2157057f3f.5e6d9aaa1362dc8c
+ d073b5bffc323683.3df2c40453051a0a.e8a091aab24af325.73a12d1bde87e12c
+ a1564355a24135c2
+VPERMILPS_256_0x0F(mem)
+ before
+ c35957427c9a947c.7504e23d19376494.8a35c9faff0d5c6c.0be2f6e6bd56d43c
+ b776e5cf87a0ba84.a4ab5ad091141b18.f9ebcbda0e7bc6c7.c954e94114b65f31
+ 587969e9e05f6206.b9b519e5005895bc.68e244909c5c1647.8043652754f5cfaf
+ 822d5f7aa2e1492f.106e1ce6018c0e2b.b2e4b208c6bb0617.8afb6605189f6263
+ 44c8e945fd4052f9
+ after
+ c35957427c9a947c.7504e23d19376494.8a35c9faff0d5c6c.0be2f6e6bd56d43c
+ 193764947504e23d.c35957427c9a947c.bd56d43c0be2f6e6.8a35c9faff0d5c6c
+ 587969e9e05f6206.b9b519e5005895bc.68e244909c5c1647.8043652754f5cfaf
+ 822d5f7aa2e1492f.106e1ce6018c0e2b.b2e4b208c6bb0617.8afb6605189f6263
+ 44c8e945fd4052f9
+
+VPERMILPS_256_0xFA(reg)
+ before
+ 0bf6e8559f65db1c.10604470e9352b2b.04225d40313ec412.b3be902ea7a45364
+ 39d1619f989a3b79.e0dc93b6d264c325.f31dda602bf9f11d.463c5bee5c24b85a
+ 2ba44f91866aacbc.cd6ec837797cce4a.38aa8eb18b49d1f7.49298d340046f224
+ 3ebcaf9605616b90.b2e260e1f98808c6.2f17759eeebba24d.9753a4edb016bdef
+ 0b841b0387a1d5e6
+ after
+ 0bf6e8559f65db1c.10604470e9352b2b.04225d40313ec412.b3be902ea7a45364
+ 2ba44f912ba44f91.866aacbc866aacbc.38aa8eb138aa8eb1.8b49d1f78b49d1f7
+ 2ba44f91866aacbc.cd6ec837797cce4a.38aa8eb18b49d1f7.49298d340046f224
+ 3ebcaf9605616b90.b2e260e1f98808c6.2f17759eeebba24d.9753a4edb016bdef
+ 0b841b0387a1d5e6
+VPERMILPS_256_0xFA(mem)
+ before
+ 83896e64a2f2f636.cc657b1ab00bb4a1.6d04d59f6e942cc4.33ae8c95efdb9eca
+ d92f1afa1c16db0a.32ebb18924f5c29d.d89fa55df5adf871.a2bccd012b33021b
+ eb3f99b31117418f.cc9a4c4ffcaad22d.d1814b08a9de26f8.d78d364e3e510aeb
+ 9388697a9e03e3f1.f6be48d8d5b62000.3274448aa7337286.2d6dc2e9c3c0f1e8
+ 02a76e3c560df4bb
+ after
+ 83896e64a2f2f636.cc657b1ab00bb4a1.6d04d59f6e942cc4.33ae8c95efdb9eca
+ 83896e64a2f2f636.cc657b1acc657b1a.6d04d59f6e942cc4.33ae8c9533ae8c95
+ eb3f99b31117418f.cc9a4c4ffcaad22d.d1814b08a9de26f8.d78d364e3e510aeb
+ 9388697a9e03e3f1.f6be48d8d5b62000.3274448aa7337286.2d6dc2e9c3c0f1e8
+ 02a76e3c560df4bb
+
+VPERMILPS_256_0xFA(reg)
+ before
+ b08934b494c34f13.afd5053bdfe67e5b.0ca2a2914aa6e7c0.d9450ad00ab99a46
+ 955d12be186e3e99.19f1eae2efcbcefa.6a9454e4f7056419.a0c01bc7ef7b5865
+ 0b7003c47f9bfcfc.aeaa925beabe8ffa.6cde5c3e795fd3b9.64b1f2597186690f
+ 700e033464d5c6e6.4bca7b92edcb7d86.6ecdb50c6c417049.02e40b74ade5896f
+ 5424e203bea473b2
+ after
+ b08934b494c34f13.afd5053bdfe67e5b.0ca2a2914aa6e7c0.d9450ad00ab99a46
+ 0b7003c40b7003c4.7f9bfcfc7f9bfcfc.6cde5c3e6cde5c3e.795fd3b9795fd3b9
+ 0b7003c47f9bfcfc.aeaa925beabe8ffa.6cde5c3e795fd3b9.64b1f2597186690f
+ 700e033464d5c6e6.4bca7b92edcb7d86.6ecdb50c6c417049.02e40b74ade5896f
+ 5424e203bea473b2
+VPERMILPS_256_0xFA(mem)
+ before
+ 373ff4f2c1cfe404.1e830e7863a8d804.ca1e207414ff53ca.ccad5cb96a367678
+ 88ffbc2dd1739890.731b21fe19a06d01.0871fdeb7a65cef4.e2ca4bb012cb22f0
+ 2131b6a00b9b4a82.c9213731224ac38a.e1918fe43b0aa92d.0c6f805ffe8bb05d
+ dfa15e378a54b707.7de24c7d1932134a.3249504c74f9a2a4.a6eaf631ca025c6c
+ 0b85a99213bc61c9
+ after
+ 373ff4f2c1cfe404.1e830e7863a8d804.ca1e207414ff53ca.ccad5cb96a367678
+ 373ff4f2c1cfe404.1e830e781e830e78.ca1e207414ff53ca.ccad5cb9ccad5cb9
+ 2131b6a00b9b4a82.c9213731224ac38a.e1918fe43b0aa92d.0c6f805ffe8bb05d
+ dfa15e378a54b707.7de24c7d1932134a.3249504c74f9a2a4.a6eaf631ca025c6c
+ 0b85a99213bc61c9
+
+VPERMILPS_256_0xFA(reg)
+ before
+ 998d95ee7446fc1f.9e1b30de6aa99b4b.ecab5c4e9be29cee.d564be0e403e7383
+ ab4eb7b28a2b691b.3a6aa981c8a6b27a.70c6641043e89822.a7af5416bce6d8f6
+ 9d140a48f0f8e369.8f5c440dc058b7bf.667f5e30add04491.84f68e4f03fb8f2b
+ ca2a8a1d4338a7b4.7abb7d6c6cc96746.2a2448187624dce8.4805e9a7328c524b
+ cfa8e00964a2de85
+ after
+ 998d95ee7446fc1f.9e1b30de6aa99b4b.ecab5c4e9be29cee.d564be0e403e7383
+ 9d140a489d140a48.f0f8e369f0f8e369.667f5e30667f5e30.add04491add04491
+ 9d140a48f0f8e369.8f5c440dc058b7bf.667f5e30add04491.84f68e4f03fb8f2b
+ ca2a8a1d4338a7b4.7abb7d6c6cc96746.2a2448187624dce8.4805e9a7328c524b
+ cfa8e00964a2de85
+VPERMILPS_256_0xFA(mem)
+ before
+ f5aaef62b54bef03.90de339e1e77f1a9.d554d08ceb087e3d.18001e3539739cd2
+ 96d9929c429240f1.4a7a02351d41fdf3.7df3ba58571eb7cd.8d5edaf49346bffc
+ 8eff45a427848e7d.534bf150dd23063f.4e64b6bccc19d025.e38b7ac01f2b8212
+ b9e985677f2c95d0.099dfe5afaa94938.237340a36704836f.77d3f8047aad20bf
+ a582522e4058d7b0
+ after
+ f5aaef62b54bef03.90de339e1e77f1a9.d554d08ceb087e3d.18001e3539739cd2
+ f5aaef62b54bef03.90de339e90de339e.d554d08ceb087e3d.18001e3518001e35
+ 8eff45a427848e7d.534bf150dd23063f.4e64b6bccc19d025.e38b7ac01f2b8212
+ b9e985677f2c95d0.099dfe5afaa94938.237340a36704836f.77d3f8047aad20bf
+ a582522e4058d7b0
+
+VPERMILPS_256_0xA3(reg)
+ before
+ c9e484a90bb9e190.f363cdcf66961019.c6bc24bf0f5d028c.daebd4fb43ec8cd7
+ 3f4588e1795b7b0c.183999caf9cfbd82.e8f460ebb8cd6ce4.4e9aeeb07ddca98a
+ 63f05c4226cae0d0.0436654354e25637.c990ac4a9284c4ef.5b4a0bac30e094b4
+ 9133fb39ad934d87.9228ad2592db9765.c7de0648390f4656.ddc8a6dc79050a81
+ b0e03b2c7356c61b
+ after
+ c9e484a90bb9e190.f363cdcf66961019.c6bc24bf0f5d028c.daebd4fb43ec8cd7
+ 26cae0d026cae0d0.54e2563763f05c42.9284c4ef9284c4ef.30e094b4c990ac4a
+ 63f05c4226cae0d0.0436654354e25637.c990ac4a9284c4ef.5b4a0bac30e094b4
+ 9133fb39ad934d87.9228ad2592db9765.c7de0648390f4656.ddc8a6dc79050a81
+ b0e03b2c7356c61b
+VPERMILPS_256_0xA3(mem)
+ before
+ af5e46893adf85b1.25586130ab41fede.a0d9ee5ecfc73e38.3c28695148f92ec8
+ b80d44ddebad036d.7aac8a94bb612f80.0916a3d928b105db.85bbd1d25bceb7ef
+ a6bbb016a2cbfc7c.ee7a73d27a7e1b1a.a9ab4882b8a5a97b.ffe33b350f1b1e78
+ 5532061f7a462b09.dc1017548324ff58.5b6459469cb0e544.04eca1e8ff6b9f0e
+ f1210155c84a755e
+ after
+ af5e46893adf85b1.25586130ab41fede.a0d9ee5ecfc73e38.3c28695148f92ec8
+ 3adf85b1af5e4689.25586130ab41fede.cfc73e38a0d9ee5e.3c28695148f92ec8
+ a6bbb016a2cbfc7c.ee7a73d27a7e1b1a.a9ab4882b8a5a97b.ffe33b350f1b1e78
+ 5532061f7a462b09.dc1017548324ff58.5b6459469cb0e544.04eca1e8ff6b9f0e
+ f1210155c84a755e
+
+VPERMILPS_256_0xA3(reg)
+ before
+ 23d056ea0545dd13.a03fc2e48f284e41.a0b9728872df17e5.fd0d530fefdd7661
+ f4439d1253e713da.65ae6050fe7f1e50.95c080d9e43c9f6e.6a71b1cace3818ff
+ c1c7d0394dbc535f.7e4b5d51e3575a61.19723db374c6d29e.7d5eef6454ce8749
+ e6a8edcb8f51d84d.c9e134d359babca0.871ba682bf0aed22.149e89c79eaa7e6c
+ 09fefce1c7d9bb93
+ after
+ 23d056ea0545dd13.a03fc2e48f284e41.a0b9728872df17e5.fd0d530fefdd7661
+ 4dbc535f4dbc535f.e3575a61c1c7d039.74c6d29e74c6d29e.54ce874919723db3
+ c1c7d0394dbc535f.7e4b5d51e3575a61.19723db374c6d29e.7d5eef6454ce8749
+ e6a8edcb8f51d84d.c9e134d359babca0.871ba682bf0aed22.149e89c79eaa7e6c
+ 09fefce1c7d9bb93
+VPERMILPS_256_0xA3(mem)
+ before
+ 3a4ac29deb66f7ec.bf32ef34b631df51.203e61c07cb7013b.3a07b6b261932ca5
+ 814e59e7285df1a0.a8b1d2e05ee8a416.612c60056957e55c.908269aff4edcad5
+ bcd53caa97ca63dd.fd70933b22036249.6678ad8e3ba8232f.e4d8bbe517a5045b
+ c5ade8d456ba0acf.1abd2cb29f0d5796.0deec5480fb579e1.9154a9c0644616e6
+ f5432dad775c3c1f
+ after
+ 3a4ac29deb66f7ec.bf32ef34b631df51.203e61c07cb7013b.3a07b6b261932ca5
+ eb66f7ec3a4ac29d.bf32ef34b631df51.7cb7013b203e61c0.3a07b6b261932ca5
+ bcd53caa97ca63dd.fd70933b22036249.6678ad8e3ba8232f.e4d8bbe517a5045b
+ c5ade8d456ba0acf.1abd2cb29f0d5796.0deec5480fb579e1.9154a9c0644616e6
+ f5432dad775c3c1f
+
+VPERMILPS_256_0xA3(reg)
+ before
+ 6af14516ec73b1b5.79a0d7518138a2a2.5be29baf7093bda8.305a231e008aa09e
+ 4eaaed696118b252.b57b870b3251e781.1c2cdba03120d02c.ac8843fb2b345791
+ fbba1f116fd77ba3.530a73ef880f9499.b9e7e9ef7f40cecd.5e43a2cdabbe58e7
+ ce6dd97ab43a4753.301917ea9d816615.8e5ebf0af57ff138.2059ba7f9d3560cb
+ cf9409fd1ca42b6a
+ after
+ 6af14516ec73b1b5.79a0d7518138a2a2.5be29baf7093bda8.305a231e008aa09e
+ 6fd77ba36fd77ba3.880f9499fbba1f11.7f40cecd7f40cecd.abbe58e7b9e7e9ef
+ fbba1f116fd77ba3.530a73ef880f9499.b9e7e9ef7f40cecd.5e43a2cdabbe58e7
+ ce6dd97ab43a4753.301917ea9d816615.8e5ebf0af57ff138.2059ba7f9d3560cb
+ cf9409fd1ca42b6a
+VPERMILPS_256_0xA3(mem)
+ before
+ 47c10a33441775f0.240e150fcccf530f.2874efe68db01822.f7df5b5c306a7519
+ 65ac390d329af988.57ebd23e5222db82.18e678d175aa68eb.50b4b851cb8c981b
+ 03211377023a745f.c44e0973e2bd1b59.da3c2d95707a109d.f52bd255637294eb
+ feeb125ecf03a1a0.c884b718192e4e40.4b438a209b2dcc64.428ea5d493a6a634
+ 922a2e3af8b70aa3
+ after
+ 47c10a33441775f0.240e150fcccf530f.2874efe68db01822.f7df5b5c306a7519
+ 441775f047c10a33.240e150fcccf530f.8db018222874efe6.f7df5b5c306a7519
+ 03211377023a745f.c44e0973e2bd1b59.da3c2d95707a109d.f52bd255637294eb
+ feeb125ecf03a1a0.c884b718192e4e40.4b438a209b2dcc64.428ea5d493a6a634
+ 922a2e3af8b70aa3
+
+VPERMILPS_256_0x5A(reg)
+ before
+ 434a68f42d2efbe3.32d8b4acb5ff3e78.bdd9d99a9301b1e2.47c50b5d11ce5a6b
+ b03c4f6ccf99b6a2.7bb2744fd13c0513.00986a65ebc080ec.aa8f2d38ef6974df
+ 344bdf1079837789.b546cf313ec5b29c.ed0f66e6bdf9f609.506c6b9d500ad7eb
+ 2dc2154ac8797a47.bc603f4019a70340.e088ca87a63851e6.152a407850be3fbc
+ d5932bb50d91677e
+ after
+ 434a68f42d2efbe3.32d8b4acb5ff3e78.bdd9d99a9301b1e2.47c50b5d11ce5a6b
+ b546cf31b546cf31.7983778979837789.506c6b9d506c6b9d.bdf9f609bdf9f609
+ 344bdf1079837789.b546cf313ec5b29c.ed0f66e6bdf9f609.506c6b9d500ad7eb
+ 2dc2154ac8797a47.bc603f4019a70340.e088ca87a63851e6.152a407850be3fbc
+ d5932bb50d91677e
+VPERMILPS_256_0x5A(mem)
+ before
+ 6c74a541a08d0c5c.f6eeeb885706fa85.6ccc42677eedb22a.355190b64108ca2f
+ b69a2c0627c0ea83.ea1b5f35c2b634f2.a156539287a37c87.49b4b6de2bf5a08f
+ 8fcf3af2be35bc1e.67956cbda6166438.37c9eead53d61d83.76fe376bff8b0db3
+ d3df4eef80f9405a.c7a80f8c9fb0c504.0af390a4fb915049.197a0fc95a574f46
+ 8e763b64d7e49ff5
+ after
+ 6c74a541a08d0c5c.f6eeeb885706fa85.6ccc42677eedb22a.355190b64108ca2f
+ f6eeeb885706fa85.f6eeeb88f6eeeb88.355190b64108ca2f.355190b6355190b6
+ 8fcf3af2be35bc1e.67956cbda6166438.37c9eead53d61d83.76fe376bff8b0db3
+ d3df4eef80f9405a.c7a80f8c9fb0c504.0af390a4fb915049.197a0fc95a574f46
+ 8e763b64d7e49ff5
+
+VPERMILPS_256_0x5A(reg)
+ before
+ 313cb5a813be3c6c.5e98e1eb89173062.689f420e48139401.f69eb3639ee0d206
+ 5d1a7b01a9726056.0bc470d1f69b4864.a4c803af3dc80ddc.d697d5d655d05fe5
+ 705a88db368b4860.b831788de2924689.d86d4ddb1b5d6c40.88aa71e93e6cb313
+ c549d9a355963035.40a9740b6a07e400.61db1cff7d5eecda.e7a3048975c089bc
+ cf4d08a015d99e0b
+ after
+ 313cb5a813be3c6c.5e98e1eb89173062.689f420e48139401.f69eb3639ee0d206
+ b831788db831788d.368b4860368b4860.88aa71e988aa71e9.1b5d6c401b5d6c40
+ 705a88db368b4860.b831788de2924689.d86d4ddb1b5d6c40.88aa71e93e6cb313
+ c549d9a355963035.40a9740b6a07e400.61db1cff7d5eecda.e7a3048975c089bc
+ cf4d08a015d99e0b
+VPERMILPS_256_0x5A(mem)
+ before
+ 1b76fb1c3bc2ae2d.b83368c3a21e5382.7ff9e037a906dff3.995e6d850055ca56
+ a9e858e80287744d.a56333a9baafeef3.50ed38fdbc9cf28e.dd413bdb3fd0425f
+ 54709bf08635ad98.e82735bf39d53d33.9150f949bed4dafe.8ad2816bd75b8fa2
+ f7da4020e4d71539.dcc96a73ba1d7cef.1df09e08ccbb536f.fa5c3ea36380efcb
+ 8a2a6bee80cd9b85
+ after
+ 1b76fb1c3bc2ae2d.b83368c3a21e5382.7ff9e037a906dff3.995e6d850055ca56
+ b83368c3a21e5382.b83368c3b83368c3.995e6d850055ca56.995e6d85995e6d85
+ 54709bf08635ad98.e82735bf39d53d33.9150f949bed4dafe.8ad2816bd75b8fa2
+ f7da4020e4d71539.dcc96a73ba1d7cef.1df09e08ccbb536f.fa5c3ea36380efcb
+ 8a2a6bee80cd9b85
+
+VPERMILPS_256_0x5A(reg)
+ before
+ 968905b8c9ced27c.70f2c4643779675d.df97cf30d912e6d2.cf97a324015b190c
+ 7ac5096ddb0dce5d.9983a2a89c286130.4cdb5e623341b889.8513848b7ac2e702
+ 932a72795118ccd4.505b56d82fefbddd.7ee1157564352dbf.192ebd2852fc7b7d
+ 3b033c48c77b088d.6f445ce00bdb3791.d3f7efd5067a8322.69b5cbe6a6148ea8
+ 4f7329b39116dfaf
+ after
+ 968905b8c9ced27c.70f2c4643779675d.df97cf30d912e6d2.cf97a324015b190c
+ 505b56d8505b56d8.5118ccd45118ccd4.192ebd28192ebd28.64352dbf64352dbf
+ 932a72795118ccd4.505b56d82fefbddd.7ee1157564352dbf.192ebd2852fc7b7d
+ 3b033c48c77b088d.6f445ce00bdb3791.d3f7efd5067a8322.69b5cbe6a6148ea8
+ 4f7329b39116dfaf
+VPERMILPS_256_0x5A(mem)
+ before
+ a936537a2f0e28c0.cf9e6446dac1be33.d40b31ad4cf68d78.a568e9eeb89df45b
+ 51c8c5279d092605.ab45e5e026762972.597c4f290f4f79bd.527ffd2d1328bd19
+ 24f7fca6f71295aa.2b45ba80462686f7.dc6334426fefb88c.358a29fcb6aa1905
+ ff8d73e3583631dc.abebe194d65e106e.378c5ce288e40613.a9d368c93aac46ce
+ 0ba7b6fe3ebc7e1e
+ after
+ a936537a2f0e28c0.cf9e6446dac1be33.d40b31ad4cf68d78.a568e9eeb89df45b
+ cf9e6446dac1be33.cf9e6446cf9e6446.a568e9eeb89df45b.a568e9eea568e9ee
+ 24f7fca6f71295aa.2b45ba80462686f7.dc6334426fefb88c.358a29fcb6aa1905
+ ff8d73e3583631dc.abebe194d65e106e.378c5ce288e40613.a9d368c93aac46ce
+ 0ba7b6fe3ebc7e1e
+
+VPMULHW_128(reg)
+ before
+ b85110095b66fda2.bc57a6cbdc80b5c7.8780568673a90583.47c241f778391e7c
+ 0a1f70552f340105.38201148a0fcde96.1b5313c4b9949fe1.e9d3616c58fbbdf3
+ 5f5cd44e56b4c4f4.50b63048bfb66776.c2af16b943a91b34.f789362d46349fa5
+ 115337606b72831a.dee480b556bb0e92.dadf5ad1ad76b429.4eb13e265ef37fbe
+ ca17f543bb411a69
+ after
+ 0000000000000000.0000000000000000.fc09070316b41c79.f92e17a62100df0a
+ 0a1f70552f340105.38201148a0fcde96.1b5313c4b9949fe1.e9d3616c58fbbdf3
+ 5f5cd44e56b4c4f4.50b63048bfb66776.c2af16b943a91b34.f789362d46349fa5
+ 115337606b72831a.dee480b556bb0e92.dadf5ad1ad76b429.4eb13e265ef37fbe
+ ca17f543bb411a69
+VPMULHW_128(mem)
+ before
+ 4787d570792c2cd3.7d5195f70af87a24.bf757c7d80168d17.be30db789487a86c
+ a1cc5c9ab5bf7127.ffa2eb7fd0d4e4be.cf36a08b5ad4a031.caee961a936730a8
+ b5b405ab8b07a492.f49234645992fe93.eaf368cbff00050b.5a65852347a28b8a
+ 5d094c91160f8240.b66d6c1340bc0450.ec7851298ca676d2.c9e1a6004bc5f4be
+ 75aef41b3b5aa6ef
+ after
+ 4787d570792c2cd3.7d5195f70af87a24.bf757c7d80168d17.be30db789487a86c
+ a1cc5c9ab5bf7127.ffa2eb7fd0d4e4be.cf36a08b5ad4a031.caee961a936730a8
+ 0000000000000000.0000000000000000.0c4cd194d29d2b01.0da40f1c2d97ef5a
+ 5d094c91160f8240.b66d6c1340bc0450.ec7851298ca676d2.c9e1a6004bc5f4be
+ 75aef41b3b5aa6ef
+
+VPMULHW_128(reg)
+ before
+ b9176be2b5f0ddca.7698ad3672e3c75c.a27e8ff621e031a0.b191d5911cd3b0b1
+ f06a08bf5210d7fa.dc2da588bc902e13.1413997b998ac230.150972efcc916fd5
+ 78f1c620b048ce2c.6b94ae720f217590.6876870c4344f3ac.f4aea42fb7ef6e6a
+ abf9a0706b23ff0b.ff9946e088a25600.faf45417bc9d00bf.2a4ae53df9f66a9b
+ 93aab306afb41f95
+ after
+ 0000000000000000.0000000000000000.ff9ade531af8ffd1.0379f3fc01362e91
+ f06a08bf5210d7fa.dc2da588bc902e13.1413997b998ac230.150972efcc916fd5
+ 78f1c620b048ce2c.6b94ae720f217590.6876870c4344f3ac.f4aea42fb7ef6e6a
+ abf9a0706b23ff0b.ff9946e088a25600.faf45417bc9d00bf.2a4ae53df9f66a9b
+ 93aab306afb41f95
+VPMULHW_128(mem)
+ before
+ 0b9a8874f5354883.e7ce951b1e2ea644.7307e9be421f8d8f.26d9fc079f1e2416
+ 6ee6e275e683a392.86bb9e8c65f4fe83.a5ac11f85aa5d868.48717b4889559c5c
+ 98593df49eaceaee.e60eb932dd014573.70523c7aeb40f1b8.bc07cd4615cda43e
+ 65c113dd3abcd9c2.6111e07622e2b4c1.b0c6e53012fa95aa.dee9ef6de0127868
+ 0a61dc2985b15385
+ after
+ 0b9a8874f5354883.e7ce951b1e2ea644.7307e9be421f8d8f.26d9fc079f1e2416
+ 6ee6e275e683a392.86bb9e8c65f4fe83.a5ac11f85aa5d868.48717b4889559c5c
+ 0000000000000000.0000000000000000.d769fe70176911b3.0afefe162ce8f1f4
+ 65c113dd3abcd9c2.6111e07622e2b4c1.b0c6e53012fa95aa.dee9ef6de0127868
+ 0a61dc2985b15385
+
+VPMULHW_128(reg)
+ before
+ 9cbc90e7a1357242.b0e8e21bd5bd2e3b.551211c5ce228a19.41d48806eae17f6b
+ f0460711cf2b104a.579b259c8cbda384.1c5b488b804d0126.ff48a1e990016c26
+ 624b3e14ab1e6b4a.35a6584c7bc8f5ca.13397f35d2f05695.c5edadc31f641809
+ 4e17305dd29abdee.25d5f715bce8df38.97f7b42d6096c511.71912682b3183f3d
+ defe8a1169299cf1
+ after
+ 0000000000000000.0000000000000000.f47aea83cfd2ffbc.ffaef1d821a51ab7
+ f0460711cf2b104a.579b259c8cbda384.1c5b488b804d0126.ff48a1e990016c26
+ 624b3e14ab1e6b4a.35a6584c7bc8f5ca.13397f35d2f05695.c5edadc31f641809
+ 4e17305dd29abdee.25d5f715bce8df38.97f7b42d6096c511.71912682b3183f3d
+ defe8a1169299cf1
+VPMULHW_128(mem)
+ before
+ e701545c5da2ed4f.0ff5d957e02b43e1.05f47fe46e2b1efb.02e3e2e1c7cb8a47
+ 6a66014faa8feb83.0333356d705e38d0.b0ce6ba5aa9d6e3f.b14705bca21ce0e2
+ 41f90bd66cfc55ba.851b400d1ebeda66.013137458e498b2f.0071192a8d14048f
+ 4a85f0ddc0f6e520.f0faf7a287d86250.d6e75fae363b30f8.4cab1b96263f31fa
+ ef42056e062aa5ce
+ after
+ e701545c5da2ed4f.0ff5d957e02b43e1.05f47fe46e2b1efb.02e3e2e1c7cb8a47
+ 6a66014faa8feb83.0333356d705e38d0.b0ce6ba5aa9d6e3f.b14705bca21ce0e2
+ 0000000000000000.0000000000000000.fe2835c6db410d57.ff1cff59149d0e4f
+ 4a85f0ddc0f6e520.f0faf7a287d86250.d6e75fae363b30f8.4cab1b96263f31fa
+ ef42056e062aa5ce
+
+VPUNPCKHQDQ_128(reg)
+ before
+ 4682d51ecb609ab8.5fd82b50c18858e0.a21c559846370f39.09bd5fcebd7f1bc6
+ adb68710116d4c63.5ebc391b8cbe6a27.f6cd565cf8671cce.787fb490402205c4
+ 802c15b173def97c.21fe942b3ca5d620.4758f65839f4c4bb.fdf9d9e0da2fad1f
+ 1b2e7d6d8d3edbaf.866aba6aee485af9.f30b32f9a36b44ab.76f64aaaa7b2cd02
+ bd4483dac4b8229a
+ after
+ 0000000000000000.0000000000000000.4758f65839f4c4bb.f6cd565cf8671cce
+ adb68710116d4c63.5ebc391b8cbe6a27.f6cd565cf8671cce.787fb490402205c4
+ 802c15b173def97c.21fe942b3ca5d620.4758f65839f4c4bb.fdf9d9e0da2fad1f
+ 1b2e7d6d8d3edbaf.866aba6aee485af9.f30b32f9a36b44ab.76f64aaaa7b2cd02
+ bd4483dac4b8229a
+VPUNPCKHQDQ_128(mem)
+ before
+ afad015c4d4c6812.da09bab1fc1a2fa7.67cc26c6bdb4afdb.543005acd558d74b
+ 29fe3f1c5d7b5b97.1909c8e75cfc3111.a1f05429c6f494f4.c8146bdb6845ba47
+ 0503b9061050b655.347aa37d48721c98.11a1c0812414c370.a90360f4fac0294a
+ 2088eb0783d73677.87a847de5c082de9.91ade7b9f420f97b.5549e06127556001
+ 2631e8908a8e9b17
+ after
+ afad015c4d4c6812.da09bab1fc1a2fa7.67cc26c6bdb4afdb.543005acd558d74b
+ 29fe3f1c5d7b5b97.1909c8e75cfc3111.a1f05429c6f494f4.c8146bdb6845ba47
+ 0000000000000000.0000000000000000.67cc26c6bdb4afdb.a1f05429c6f494f4
+ 2088eb0783d73677.87a847de5c082de9.91ade7b9f420f97b.5549e06127556001
+ 2631e8908a8e9b17
+
+VPUNPCKHQDQ_128(reg)
+ before
+ 790973ecc0f91539.57595109d11c962a.6edeb1763549a0b0.fede44bd5125f240
+ ab1b7de164210b12.844168fa172c9499.456adcb16ec1b198.35015379582e6aeb
+ 16b402db1293b84f.840eabc57012eaf1.6796c4fba4fc9b4d.10e290d924481caa
+ 1720ff4667da5a9c.338a9655f9db545e.32af66c072879b7d.6c4d77c9d17ec5a6
+ 250d85367cdc200e
+ after
+ 0000000000000000.0000000000000000.6796c4fba4fc9b4d.456adcb16ec1b198
+ ab1b7de164210b12.844168fa172c9499.456adcb16ec1b198.35015379582e6aeb
+ 16b402db1293b84f.840eabc57012eaf1.6796c4fba4fc9b4d.10e290d924481caa
+ 1720ff4667da5a9c.338a9655f9db545e.32af66c072879b7d.6c4d77c9d17ec5a6
+ 250d85367cdc200e
+VPUNPCKHQDQ_128(mem)
+ before
+ 17f0350a416eeb0c.0aab6e8fff822ba4.6d82a598cd92900b.0101bc6c75edecd2
+ 1ec003333a41e0cc.4ca14d2075186714.0ec2557909435825.30d8c46b48bbccf8
+ 164a6b9b8661bb7c.374e976665274c97.f21520e4c8fb69d7.1a80792a887c759c
+ db5aea303fd83a45.28fd49ce6c3c14da.f54984c527c57f4e.1d44d713d0bc246a
+ 9471db94bd08140d
+ after
+ 17f0350a416eeb0c.0aab6e8fff822ba4.6d82a598cd92900b.0101bc6c75edecd2
+ 1ec003333a41e0cc.4ca14d2075186714.0ec2557909435825.30d8c46b48bbccf8
+ 0000000000000000.0000000000000000.6d82a598cd92900b.0ec2557909435825
+ db5aea303fd83a45.28fd49ce6c3c14da.f54984c527c57f4e.1d44d713d0bc246a
+ 9471db94bd08140d
+
+VPUNPCKHQDQ_128(reg)
+ before
+ da548018eaea8332.49bcfbdd81b41756.7bfb5dc325e1fc89.f328fc0941ad55b6
+ 4d37c20af3f1ab85.3c3c1a8e69000fd9.8c94d1b02da4404f.c880059a32c0a83a
+ 47669dd875a6c8b1.90a5c32f12c9defa.b714a0031f111bd9.501b196518083407
+ 262f0ded0c971863.21c572ac991a3fe7.58c7c62798b3cad2.67c6b6570c94b448
+ e94c575b2c6de62a
+ after
+ 0000000000000000.0000000000000000.b714a0031f111bd9.8c94d1b02da4404f
+ 4d37c20af3f1ab85.3c3c1a8e69000fd9.8c94d1b02da4404f.c880059a32c0a83a
+ 47669dd875a6c8b1.90a5c32f12c9defa.b714a0031f111bd9.501b196518083407
+ 262f0ded0c971863.21c572ac991a3fe7.58c7c62798b3cad2.67c6b6570c94b448
+ e94c575b2c6de62a
+VPUNPCKHQDQ_128(mem)
+ before
+ b27b795c93a184d9.44dd0fb55350d546.cb66a4f119ffefc9.cbf94088331689e7
+ 9e1d96485e3c4a80.ffbb9d9de65b3c07.6a55d4eaaf85aacf.6cf509928dc693c4
+ 88002c0aa948f64c.b116b50f62468851.d95e7e8476b72c23.97081db241502614
+ 4eeeb68e8ed34268.b73a5378629cf7d1.f64d1ea98aa130f1.a87e7852ec3f7b84
+ fba316df2920d1bf
+ after
+ b27b795c93a184d9.44dd0fb55350d546.cb66a4f119ffefc9.cbf94088331689e7
+ 9e1d96485e3c4a80.ffbb9d9de65b3c07.6a55d4eaaf85aacf.6cf509928dc693c4
+ 0000000000000000.0000000000000000.cb66a4f119ffefc9.6a55d4eaaf85aacf
+ 4eeeb68e8ed34268.b73a5378629cf7d1.f64d1ea98aa130f1.a87e7852ec3f7b84
+ fba316df2920d1bf
+
+VPSRAW_0x05_128(reg)
+ before
+ ecc3f4c6947d6372.cbb4b0c02ce9eb01.6e73714583eac333.9ced314708507366
+ d62a0c71cae56c49.da1e968c9d94ac43.300d0de060bb2822.a70c32480ccfb0ae
+ 17245c4e67e128ef.59f7e5dffde34259.5a5422b7969b644b.f2749d9ab12aa5f4
+ 0afce0c806ffd511.230d17a368df696f.4993ac35c017b15a.5bf2ee28136e0c65
+ bc52a1de4fa6a22d
+ after
+ 0000000000000000.0000000000000000.024cfd61fe00fd8a.02dfff71009b0063
+ d62a0c71cae56c49.da1e968c9d94ac43.300d0de060bb2822.a70c32480ccfb0ae
+ 17245c4e67e128ef.59f7e5dffde34259.5a5422b7969b644b.f2749d9ab12aa5f4
+ 0afce0c806ffd511.230d17a368df696f.4993ac35c017b15a.5bf2ee28136e0c65
+ bc52a1de4fa6a22d
+VPSRAW_0x05_128(mem)
+ before
+ f36033a881df2277.0bff924b43caad5a.132aaac5fc96ddb3.5717a7c57bba4cfa
+ dbe71f72c4234a70.75797043bbcfed77.071c1a32d213594f.e12d10d5621071d7
+ 4fb5e1283481d443.a6b6751c0999d113.d9ade1d508629b6f.431ee1d012a65b9e
+ 2c94f5b6ee027c1d.f8029d42cab494db.67aa7d99ba905c40.d9391822260747fb
+ ffc9b1383ac0719a
+ after
+ f36033a881df2277.0bff924b43caad5a.132aaac5fc96ddb3.5717a7c57bba4cfa
+ dbe71f72c4234a70.75797043bbcfed77.071c1a32d213594f.e12d10d5621071d7
+ 4fb5e1283481d443.a6b6751c0999d113.d9ade1d508629b6f.431ee1d012a65b9e
+ 2c94f5b6ee027c1d.f8029d42cab494db.67aa7d99ba905c40.d9391822260747fb
+ ffc9b1383ac0719a
+
+VPSRAW_0x05_128(reg)
+ before
+ 1119a67ceb5b1426.4f51d7090db40029.c9a8e4219aac737b.8bde696c03a85bee
+ 6b77f55bd5676d4b.92b8040baea21a94.74f64725130eaa9e.2317213900b752a4
+ 692d9942936db8b6.d395f7aaecd8878a.5436c0bbd46675f1.091f21ecccc7fe8f
+ 67888e9bc1fb3113.ecb42cd0e4630236.c7b54d4d763e0f20.1bc4e67183e61bda
+ 33d0eab5422065b3
+ after
+ 0000000000000000.0000000000000000.fe3d026a03b10079.00deff33fc1f00de
+ 6b77f55bd5676d4b.92b8040baea21a94.74f64725130eaa9e.2317213900b752a4
+ 692d9942936db8b6.d395f7aaecd8878a.5436c0bbd46675f1.091f21ecccc7fe8f
+ 67888e9bc1fb3113.ecb42cd0e4630236.c7b54d4d763e0f20.1bc4e67183e61bda
+ 33d0eab5422065b3
+VPSRAW_0x05_128(mem)
+ before
+ 2e10aba224809743.c1d4d0d4fc9c130e.bae1206bb14e49c5.27bfe9499724b5d6
+ e850a52546126eb8.d35d5c58e0dc9b51.1ae74d6670a61662.d1a0911ad3a3a3c0
+ 3e5b522bc4e2a53e.f96e2c930748058b.e69331ad3c76263a.22a43f2cc5481489
+ 0aff309eb8fdfa01.8f553ef1106b8d66.fbb1472c31ca3479.7416f1ea0a9e46de
+ 2543a2c23d31726a
+ after
+ 2e10aba224809743.c1d4d0d4fc9c130e.bae1206bb14e49c5.27bfe9499724b5d6
+ e850a52546126eb8.d35d5c58e0dc9b51.1ae74d6670a61662.d1a0911ad3a3a3c0
+ 3e5b522bc4e2a53e.f96e2c930748058b.e69331ad3c76263a.22a43f2cc5481489
+ 0aff309eb8fdfa01.8f553ef1106b8d66.fbb1472c31ca3479.7416f1ea0a9e46de
+ 2543a2c23d31726a
+
+VPSRAW_0x05_128(reg)
+ before
+ 8f784f20fa8ed7da.2906ba6c416f272c.f15c8dde94d26e8f.350d0bcf6caefd4a
+ 0ffff26ede40afda.773d6c807842e8eb.7ad016c63208e5b1.7073fa82092f3dda
+ 0125891985d33715.d070c2c67c84fb6c.88fdd31583992e79.89af8e322359b055
+ c1350f8d8ad4ab38.106b382a66401ad8.762fc23726118493.5a8c45c9d63611e6
+ c0d79a353fd41db9
+ after
+ 0000000000000000.0000000000000000.03b1fe110130fc24.02d4022efeb1008f
+ 0ffff26ede40afda.773d6c807842e8eb.7ad016c63208e5b1.7073fa82092f3dda
+ 0125891985d33715.d070c2c67c84fb6c.88fdd31583992e79.89af8e322359b055
+ c1350f8d8ad4ab38.106b382a66401ad8.762fc23726118493.5a8c45c9d63611e6
+ c0d79a353fd41db9
+VPSRAW_0x05_128(mem)
+ before
+ 975c0a607a3e90fb.ac7d803789ce47ee.13fa4b985483025e.a0b1de99b4fd24aa
+ bbe70f38a18125d8.1c47d8811f4e46e4.b5e876fc62586f28.61d124a5cbe84a6b
+ 084427a8d3a89a7c.6ee014d9e7dee5c6.d2033542abcb1c62.17d98ec9075f3281
+ 5a3fcd9c29bfa912.fe952faa7e0c5f3f.461505574ce9c639.1c161a7003ed1799
+ ced4c3055c1e365e
+ after
+ 975c0a607a3e90fb.ac7d803789ce47ee.13fa4b985483025e.a0b1de99b4fd24aa
+ bbe70f38a18125d8.1c47d8811f4e46e4.b5e876fc62586f28.61d124a5cbe84a6b
+ 084427a8d3a89a7c.6ee014d9e7dee5c6.d2033542abcb1c62.17d98ec9075f3281
+ 5a3fcd9c29bfa912.fe952faa7e0c5f3f.461505574ce9c639.1c161a7003ed1799
+ ced4c3055c1e365e
+
+VPCMPGTD_128(reg)
+ before
+ 885f85f6ad7fcb7d.8da37d00c2d30ec6.28af25607f64f2fc.edeb602560bd29d9
+ a5035cae929b11a2.7c3eb4c0b7ef87c5.487df2678771d8a8.a351c49a0353006e
+ 820b4599a8fe4578.05daecc8271fce3b.ba4a932b31bf4ef0.4413aca052b80923
+ 7cc53b238a35a3ac.0344a3042b70a053.da6102181ada8f80.acfd942569f7fe24
+ b7daf914621c9b9e
+ after
+ 0000000000000000.0000000000000000.ffffffff00000000.0000000000000000
+ a5035cae929b11a2.7c3eb4c0b7ef87c5.487df2678771d8a8.a351c49a0353006e
+ 820b4599a8fe4578.05daecc8271fce3b.ba4a932b31bf4ef0.4413aca052b80923
+ 7cc53b238a35a3ac.0344a3042b70a053.da6102181ada8f80.acfd942569f7fe24
+ b7daf914621c9b9e
+VPCMPGTD_128(mem)
+ before
+ 407756595c349ebd.ed7b3ab9d5cb67ea.52485461e1edb83a.04103d9add4fd803
+ 25a026e0714ac1ac.337a3ec5254cccdd.ceb27cc965a2d31c.94a13f1d17a96526
+ 4121e895bd6ac198.a80e43b414440f31.524d952ad29cad24.e661050e63747294
+ 70c615645da159ad.a98346f341406c94.bce71d6e45e6027f.559c89d75d3d3afa
+ 3f9dc9e6a28ffa04
+ after
+ 407756595c349ebd.ed7b3ab9d5cb67ea.52485461e1edb83a.04103d9add4fd803
+ 25a026e0714ac1ac.337a3ec5254cccdd.ceb27cc965a2d31c.94a13f1d17a96526
+ 0000000000000000.0000000000000000.00000000ffffffff.00000000ffffffff
+ 70c615645da159ad.a98346f341406c94.bce71d6e45e6027f.559c89d75d3d3afa
+ 3f9dc9e6a28ffa04
+
+VPCMPGTD_128(reg)
+ before
+ ffb2c0a5cef7ee5d.8d5b2b396cfa4616.932442ed45cc1eb0.e74a8f83d98c8d58
+ f1256a827c0052b2.76aca40107814400.c03f330dbf726231.ae436754aa9b0cdc
+ 7043c4e8483661ae.0584fea649430f96.8d1e15c148c174c4.ef9e22cdd51e3836
+ da58c843cf2658fe.18b0b5164f4b6205.560ee5747e429015.85273ada7521d094
+ 4ba92d67a7b18e1f
+ after
+ 0000000000000000.0000000000000000.ffffffff00000000.0000000000000000
+ f1256a827c0052b2.76aca40107814400.c03f330dbf726231.ae436754aa9b0cdc
+ 7043c4e8483661ae.0584fea649430f96.8d1e15c148c174c4.ef9e22cdd51e3836
+ da58c843cf2658fe.18b0b5164f4b6205.560ee5747e429015.85273ada7521d094
+ 4ba92d67a7b18e1f
+VPCMPGTD_128(mem)
+ before
+ 1ff2766087d92f06.8ab074ffac5a734d.89fc433b34a5fb78.775b9e92fd83f1cf
+ dbcc91b130a66f72.db97c3887c61ed48.36342603145e931c.4c513c87600fd49f
+ 5c04fb47be220992.2b59b24adac4039b.f924d9590c81e91d.323cbbbf44727530
+ 7f662f0c4e5cbb90.d4413bb26311f1f1.b097d829381bb7a6.836717a744390f2f
+ 9c204da9fcefe048
+ after
+ 1ff2766087d92f06.8ab074ffac5a734d.89fc433b34a5fb78.775b9e92fd83f1cf
+ dbcc91b130a66f72.db97c3887c61ed48.36342603145e931c.4c513c87600fd49f
+ 0000000000000000.0000000000000000.ffffffff00000000.00000000ffffffff
+ 7f662f0c4e5cbb90.d4413bb26311f1f1.b097d829381bb7a6.836717a744390f2f
+ 9c204da9fcefe048
+
+VPCMPGTD_128(reg)
+ before
+ d9b1583309202226.1ebea9eefb5d3e99.349c5c2ab2d3f3f7.355b9f5fb336bae4
+ 966734af07591176.17d8e5d8e23351d8.a5b6102064974459.663aabe799e1ae03
+ 2f8edd8b9125ebe3.44805fb51ee9ae7a.85db53fe14e821c2.1d0176ad07254f2e
+ ff7150324311ea1a.82819473cb8b12aa.2e5721325f52c6df.377c7e9e19105891
+ 90773ea4e9ad865a
+ after
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffff00000000
+ 966734af07591176.17d8e5d8e23351d8.a5b6102064974459.663aabe799e1ae03
+ 2f8edd8b9125ebe3.44805fb51ee9ae7a.85db53fe14e821c2.1d0176ad07254f2e
+ ff7150324311ea1a.82819473cb8b12aa.2e5721325f52c6df.377c7e9e19105891
+ 90773ea4e9ad865a
+VPCMPGTD_128(mem)
+ before
+ 05be33ac960994b2.645e870fbaa84ac7.ada8fefd06263995.fe767727e0626e5b
+ 701cd8a33a2f40c8.b99f809091764995.a2c11b3febc6df67.4f83504934a356e3
+ ae5fa874f12b44c6.5a82372065072130.3b9867259575bf4b.7ecca804f6a1ba22
+ 9b51210ad8095cd9.a351a62cd1e80f46.55f95c9c2141966e.e89b7bc4c2e9d6c5
+ e73dc6f53506e578
+ after
+ 05be33ac960994b2.645e870fbaa84ac7.ada8fefd06263995.fe767727e0626e5b
+ 701cd8a33a2f40c8.b99f809091764995.a2c11b3febc6df67.4f83504934a356e3
+ 0000000000000000.0000000000000000.0000000000000000.ffffffffffffffff
+ 9b51210ad8095cd9.a351a62cd1e80f46.55f95c9c2141966e.e89b7bc4c2e9d6c5
+ e73dc6f53506e578
+
+VPMOVZXBD_128(reg)
+ before
+ d8fe8403eb8424e6.13bfbf530ad6462c.ef59cb1e72a44f81.ccb0788ea9351ffb
+ 172ab05b7ff0cfbc.f275fc3aa39dbcec.9ce6a063e3c81c8d.7c8836e84c5e181f
+ 000c49678dd521a5.143e56abc16b7b44.05432368c1dfb317.414e129724c73b06
+ f0f14895b2bf584e.55e848937d4b3f61.86be5097a77550cb.f7ce88854d7c44db
+ 7ad415a0e48af1cb
+ after
+ d8fe8403eb8424e6.13bfbf530ad6462c.ef59cb1e72a44f81.ccb0788ea9351ffb
+ 0000000000000000.0000000000000000.00000024000000c7.0000003b00000006
+ 000c49678dd521a5.143e56abc16b7b44.05432368c1dfb317.414e129724c73b06
+ f0f14895b2bf584e.55e848937d4b3f61.86be5097a77550cb.f7ce88854d7c44db
+ 7ad415a0e48af1cb
+VPMOVZXBD_128(mem)
+ before
+ a62c34d304fbfc01.4126ab4f893bad63.913d4edcf549c36e.7aa1215e31162f54
+ 57a2610acade22aa.50f56c03afd45f8f.a40be5734572c499.3f399427fc4f8b5f
+ 69011831513c1ff2.79ab891cbf17a87f.6a1c874588d1fe0b.2fd2a460a4aca198
+ b817d534b623ae04.1893fe06568ec6de.bf3db23cda722cf3.a8b84d74c4b7adaa
+ 04378bcff8feea42
+ after
+ a62c34d304fbfc01.4126ab4f893bad63.913d4edcf549c36e.7aa1215e31162f54
+ 0000000000000000.0000000000000000.0000003100000016.0000002f00000054
+ 69011831513c1ff2.79ab891cbf17a87f.6a1c874588d1fe0b.2fd2a460a4aca198
+ b817d534b623ae04.1893fe06568ec6de.bf3db23cda722cf3.a8b84d74c4b7adaa
+ 04378bcff8feea42
+
+VPMOVZXBD_128(reg)
+ before
+ a19a5bdddd0c950b.20ae15ff149f8c0d.89fbc52d0fc8f259.7f39e14658620c7b
+ d92fb80a0f6eeab2.7d93537e88ba7538.282edcfd874e6b9c.86de904d1eac58cf
+ 0a409ec329af25e2.aa920b9e2d8225b2.51773ee259ae6b52.b0f73c3f475ccc1c
+ 8e1a0972c75b8148.8577b949200357a7.6023e74922732f28.d84f5f07ef7f268e
+ dcb3779133202051
+ after
+ a19a5bdddd0c950b.20ae15ff149f8c0d.89fbc52d0fc8f259.7f39e14658620c7b
+ 0000000000000000.0000000000000000.000000470000005c.000000cc0000001c
+ 0a409ec329af25e2.aa920b9e2d8225b2.51773ee259ae6b52.b0f73c3f475ccc1c
+ 8e1a0972c75b8148.8577b949200357a7.6023e74922732f28.d84f5f07ef7f268e
+ dcb3779133202051
+VPMOVZXBD_128(mem)
+ before
+ 97efffc92e4b778f.c209f58486ff3b90.e90dda6d7c47c842.b07ed39c7d29f3c9
+ e5cf749bfd0de677.03595f6601268f65.b222e8f45d5c33af.9fd4ff48065df2e2
+ a11f50f4bb712a33.ab554282d55cb874.bb8061cce04e561c.887166ba5a9a691f
+ a9aa11be8583fff0.174b9a469d2ef368.e2f4c1e02128ebb3.c7a0045d156d942b
+ b7aed59cd261aeb2
+ after
+ 97efffc92e4b778f.c209f58486ff3b90.e90dda6d7c47c842.b07ed39c7d29f3c9
+ 0000000000000000.0000000000000000.0000007d00000029.000000f3000000c9
+ a11f50f4bb712a33.ab554282d55cb874.bb8061cce04e561c.887166ba5a9a691f
+ a9aa11be8583fff0.174b9a469d2ef368.e2f4c1e02128ebb3.c7a0045d156d942b
+ b7aed59cd261aeb2
+
+VPMOVZXBD_128(reg)
+ before
+ b6e8d5e52d02f562.d73d32e7765021d9.a385631df6277cee.024a821c3bf6afa0
+ 1f9801a3c3dca3e5.09a52f59abe34b1b.ac509a737bd38fb2.f64e226c4ac45d10
+ 4d0b54422f7cf4e7.19ac85023f483be2.8cf83ab4c9bf675f.9ccb1bbc6b9fb32f
+ 9e8cca2f0e6e2615.e51fafcd4e8caa59.a0c93f4c7b7641a2.ce8febf8b9926b28
+ 6a640e0d51a94128
+ after
+ b6e8d5e52d02f562.d73d32e7765021d9.a385631df6277cee.024a821c3bf6afa0
+ 0000000000000000.0000000000000000.0000006b0000009f.000000b30000002f
+ 4d0b54422f7cf4e7.19ac85023f483be2.8cf83ab4c9bf675f.9ccb1bbc6b9fb32f
+ 9e8cca2f0e6e2615.e51fafcd4e8caa59.a0c93f4c7b7641a2.ce8febf8b9926b28
+ 6a640e0d51a94128
+VPMOVZXBD_128(mem)
+ before
+ 4a17fee54ff1f35b.6d695fd4fb3c731b.47c928a5f5ba57ac.440fa5a72d845927
+ 4b74396dcd753bec.15ec109e937418a4.1d786f7850dffc09.d41568327c76eb99
+ 4a473a92e942d607.f463d8fa71a1505d.41f6fd317a065699.ac28855704d732a4
+ 215c7d3fbf627fda.6418b252325059f2.91114fbd8f3b218b.2895f78360346bf5
+ a4a6ba232c18d138
+ after
+ 4a17fee54ff1f35b.6d695fd4fb3c731b.47c928a5f5ba57ac.440fa5a72d845927
+ 0000000000000000.0000000000000000.0000002d00000084.0000005900000027
+ 4a473a92e942d607.f463d8fa71a1505d.41f6fd317a065699.ac28855704d732a4
+ 215c7d3fbf627fda.6418b252325059f2.91114fbd8f3b218b.2895f78360346bf5
+ a4a6ba232c18d138
+
+VPMOVSXBD_128(reg)
+ before
+ 7ca8caa2050fa218.ad7f7e5f6ae4f48e.c3589d14710c6d0e.e793e206ac8a1909
+ 0ce6246b86a51842.cb7bbae007d1ef52.6b6f92aacb61c85d.204931f9ed00f940
+ b0aec2ec4c677062.551dacadb1372d50.b9a88f82dbdca88d.19ffb8826da87e5b
+ c34aa290f3e0e523.2831d0b2852169b5.0a518f073e084748.ac80f48e488f6387
+ b69a5f089bc066ef
+ after
+ 7ca8caa2050fa218.ad7f7e5f6ae4f48e.c3589d14710c6d0e.e793e206ac8a1909
+ 0000000000000000.0000000000000000.0000006dffffffa8.0000007e0000005b
+ b0aec2ec4c677062.551dacadb1372d50.b9a88f82dbdca88d.19ffb8826da87e5b
+ c34aa290f3e0e523.2831d0b2852169b5.0a518f073e084748.ac80f48e488f6387
+ b69a5f089bc066ef
+VPMOVSXBD_128(mem)
+ before
+ 131777db814741c0.a307c0c3159db432.2083a2db9e9c60ac.b8b48ea58f71e23a
+ 9fc4b7f51730b026.ab3216f15128193a.1adf9f1518b3ce62.201e88c86aa4b410
+ 366d9c417888714c.3715a287401050e8.f011414a10726f02.9fdb79dc6c2cfb76
+ b4dea0abc15b3e5f.a3fc5eef80de95e8.7fe40667a2e5feb9.8f375e4e3195f117
+ 4d7e3288536cd3a0
+ after
+ 131777db814741c0.a307c0c3159db432.2083a2db9e9c60ac.b8b48ea58f71e23a
+ 0000000000000000.0000000000000000.ffffff8f00000071.ffffffe20000003a
+ 366d9c417888714c.3715a287401050e8.f011414a10726f02.9fdb79dc6c2cfb76
+ b4dea0abc15b3e5f.a3fc5eef80de95e8.7fe40667a2e5feb9.8f375e4e3195f117
+ 4d7e3288536cd3a0
+
+VPMOVSXBD_128(reg)
+ before
+ 35fbf1f7713cdcbc.f6e3411f0db3d48a.4a354996ad2023e5.a3256959e91938b3
+ a3fc980825914918.d647fa89789eeffa.8a0a5ce96261368c.38a0e70b011ad91b
+ f4cb21260bf85660.31d847d51f274adb.bdc994523c2e0c88.1a21fa6807f29c1e
+ 82b58abcc0fc3f3f.e260a4f01e5ba258.41bcee3fd612df86.2574205e16af3fe7
+ 3565d4d84b5c7ca3
+ after
+ 35fbf1f7713cdcbc.f6e3411f0db3d48a.4a354996ad2023e5.a3256959e91938b3
+ 0000000000000000.0000000000000000.00000007fffffff2.ffffff9c0000001e
+ f4cb21260bf85660.31d847d51f274adb.bdc994523c2e0c88.1a21fa6807f29c1e
+ 82b58abcc0fc3f3f.e260a4f01e5ba258.41bcee3fd612df86.2574205e16af3fe7
+ 3565d4d84b5c7ca3
+VPMOVSXBD_128(mem)
+ before
+ 26bf92c2c1060f7e.aa06ce38df2a3f62.c7ac8ec49045b39e.7130651bcc99ec31
+ d450d70895b8b6a3.c80ae905050c9374.bb88803f92f138d8.a871f552bb506f36
+ 1ae21d96e27e2b3e.380cd88fcd307722.9ac0f64b3e6cef33.44ca9a503fc1a341
+ d642e258c5652b7d.565a9542d4222718.40206cd6b3c192db.9f895181f37bc6fd
+ 17f8155173071117
+ after
+ 26bf92c2c1060f7e.aa06ce38df2a3f62.c7ac8ec49045b39e.7130651bcc99ec31
+ 0000000000000000.0000000000000000.ffffffccffffff99.ffffffec00000031
+ 1ae21d96e27e2b3e.380cd88fcd307722.9ac0f64b3e6cef33.44ca9a503fc1a341
+ d642e258c5652b7d.565a9542d4222718.40206cd6b3c192db.9f895181f37bc6fd
+ 17f8155173071117
+
+VPMOVSXBD_128(reg)
+ before
+ 0665e22c5cf3c33b.e33ca13b5978718a.7d3e1e8bb56dde01.89735fcb0bfcddfb
+ c91ab47f49cb1614.1d9cd629bac3ba91.0b056fd40c9dd98a.51864916622a8ebf
+ bd6488b4d719474e.602dfe100553c2bf.5bfb828a773e535e.7325a8a3d5565f55
+ 3c8e5839a26b9297.87bd94da56334540.c96c541a8fdd8a2a.cd1cf75e7f8c0de7
+ 3a37b3337dd953a1
+ after
+ 0665e22c5cf3c33b.e33ca13b5978718a.7d3e1e8bb56dde01.89735fcb0bfcddfb
+ 0000000000000000.0000000000000000.ffffffd500000056.0000005f00000055
+ bd6488b4d719474e.602dfe100553c2bf.5bfb828a773e535e.7325a8a3d5565f55
+ 3c8e5839a26b9297.87bd94da56334540.c96c541a8fdd8a2a.cd1cf75e7f8c0de7
+ 3a37b3337dd953a1
+VPMOVSXBD_128(mem)
+ before
+ 9542560eea48eeb0.a3e62278444d3398.70161475c86ffe3f.b1a4e2eef205b89a
+ bc095edce3e59a40.4eb6e1df5c496500.f505facc7714aae9.6fee27743c431a59
+ 8957468783bd137c.9a4c92d983ed6579.f456c2cb802d056a.5e981f170822eb13
+ daf98afde7db1491.e1f22fd257c56eb0.48d5e95effc7cbed.dcecc743f22e6876
+ 44371a6497f3cd2c
+ after
+ 9542560eea48eeb0.a3e62278444d3398.70161475c86ffe3f.b1a4e2eef205b89a
+ 0000000000000000.0000000000000000.fffffff200000005.ffffffb8ffffff9a
+ 8957468783bd137c.9a4c92d983ed6579.f456c2cb802d056a.5e981f170822eb13
+ daf98afde7db1491.e1f22fd257c56eb0.48d5e95effc7cbed.dcecc743f22e6876
+ 44371a6497f3cd2c
+
+VPINSRB_128_1of3(reg)
+ before
+ f1c513e692fe56e1.8abba7282a4c5bab.80f5b636745bbe50.cc4dea710fecb79f
+ 41e2b13580da3f42.746917f6691aa1f5.d3a12271753d8f06.5e8c41f0ccaa86ab
+ 8ed9edbdfc14c3fb.75cf5852bf54a59b.36416feff7f71d7d.d85c6ac8530df43e
+ 36f8c4eaa3371fb7.6ab8e528480321cb.0523991c9514a662.188ae2e3bf20bc83
+ f8e2232e2def9ba7
+ after
+ 0000000000000000.0000000000000000.d3a12271753d8f06.5e8c41f0ccaa86a7
+ 41e2b13580da3f42.746917f6691aa1f5.d3a12271753d8f06.5e8c41f0ccaa86ab
+ 8ed9edbdfc14c3fb.75cf5852bf54a59b.36416feff7f71d7d.d85c6ac8530df43e
+ 36f8c4eaa3371fb7.6ab8e528480321cb.0523991c9514a662.188ae2e3bf20bc83
+ f8e2232e2def9ba7
+VPINSRB_128_1of3(mem)
+ before
+ 5530ab96b8864dd6.9489332910cf8e23.2df23b642135d2af.9c919d65eb206461
+ 0c40f5067df28e3b.03d935e4e0694deb.9c47d4f266f57473.57d8763496a79425
+ f7de7e6a973e1903.e034c689ae9098ba.91842ebe324fc344.924420f73236725b
+ f3d5c0ad2377ab5a.88e6e38317d0ab3c.e975c4b5a1507a4e.a9219718595839ae
+ f8bbd805aa9a26cb
+ after
+ 5530ab96b8864dd6.9489332910cf8e23.2df23b642135d2af.9c919d65eb206461
+ 0c40f5067df28e3b.03d935e4e0694deb.9c47d4f266f57473.57d8763496a79425
+ 0000000000000000.0000000000000000.9c47d4f266f57473.57d8763461a79425
+ f3d5c0ad2377ab5a.88e6e38317d0ab3c.e975c4b5a1507a4e.a9219718595839ae
+ f8bbd805aa9a26cb
+
+VPINSRB_128_1of3(reg)
+ before
+ db5ede29bf86755d.ddf239bd3ca8006b.553a863eb6b6c21f.81e612c1d00356bc
+ ae55a5f034aa6112.8f016485feddd462.a57ead2528cd180d.33a395d0da7512bb
+ cded29c6a6922893.e6cebdf28622e26c.d2fc53a608a1eab2.dc77c7ccdcb16c76
+ 93726617b0c9048f.be25c1eef084e7b5.3901752df2bf73bb.583026a3f1c31e1a
+ 83982d4036b8e4d3
+ after
+ 0000000000000000.0000000000000000.a57ead2528cd180d.33a395d0da7512d3
+ ae55a5f034aa6112.8f016485feddd462.a57ead2528cd180d.33a395d0da7512bb
+ cded29c6a6922893.e6cebdf28622e26c.d2fc53a608a1eab2.dc77c7ccdcb16c76
+ 93726617b0c9048f.be25c1eef084e7b5.3901752df2bf73bb.583026a3f1c31e1a
+ 83982d4036b8e4d3
+VPINSRB_128_1of3(mem)
+ before
+ 397c598fc69a7ccc.5e30594fefdb31b0.f3d2eb66570e9e69.36d90d2483b2f1d4
+ 57a8247cbe78a032.8973fddbfe55eda2.61a0b647d7cdc5b3.26d019f857069ea8
+ b7e70cf3395b0d30.6f874e257ac17212.e45ca17b8dcc16bf.633294150848b6e4
+ 36078ce054517ff3.6eb7489bfeaefdac.58d225f095174dbb.4a4b7ae835037733
+ 3766c7db78c31b42
+ after
+ 397c598fc69a7ccc.5e30594fefdb31b0.f3d2eb66570e9e69.36d90d2483b2f1d4
+ 57a8247cbe78a032.8973fddbfe55eda2.61a0b647d7cdc5b3.26d019f857069ea8
+ 0000000000000000.0000000000000000.61a0b647d7cdc5b3.26d019f8d4069ea8
+ 36078ce054517ff3.6eb7489bfeaefdac.58d225f095174dbb.4a4b7ae835037733
+ 3766c7db78c31b42
+
+VPINSRB_128_1of3(reg)
+ before
+ 86d0785c6d15dfbd.b0d2202f2a65b1a7.e151e7a726a5c91b.99cebf9009bb28d0
+ 93d588d6b184ff4f.011644ccd7a46077.239f28b78f34140c.831cec4908c3612d
+ bac1f3b5df9cb6a5.049d75a478194890.92ee0636d5e6182b.f2882706ac3bb5fc
+ 57e0b56594ea416a.97342ea129d0241d.888a7d9093481123.c2ddecb31130e069
+ cfe9b83c54ad9da1
+ after
+ 0000000000000000.0000000000000000.239f28b78f34140c.831cec4908c361a1
+ 93d588d6b184ff4f.011644ccd7a46077.239f28b78f34140c.831cec4908c3612d
+ bac1f3b5df9cb6a5.049d75a478194890.92ee0636d5e6182b.f2882706ac3bb5fc
+ 57e0b56594ea416a.97342ea129d0241d.888a7d9093481123.c2ddecb31130e069
+ cfe9b83c54ad9da1
+VPINSRB_128_1of3(mem)
+ before
+ f576068d90bea9d0.c67eca526bf9dc4b.95a6ebb105d6b24b.63be8a3165e53da0
+ 10515193e170c021.63e62fe80156c2f4.dac128bf2836ac46.7dd82785e849d650
+ fc46183864ce9ec1.8a65df93f18c3110.425061b6affcce39.342252f8b80119dd
+ 9421d46935e4fedc.9748d6bfd727624c.a91e1384b535d651.e2e906f6709841f3
+ e5793fecac9a8c3f
+ after
+ f576068d90bea9d0.c67eca526bf9dc4b.95a6ebb105d6b24b.63be8a3165e53da0
+ 10515193e170c021.63e62fe80156c2f4.dac128bf2836ac46.7dd82785e849d650
+ 0000000000000000.0000000000000000.dac128bf2836ac46.7dd82785a049d650
+ 9421d46935e4fedc.9748d6bfd727624c.a91e1384b535d651.e2e906f6709841f3
+ e5793fecac9a8c3f
+
+VPINSRB_128_2of3(reg)
+ before
+ 971efa440994346d.b6ad02136fbf9d9d.e6d910d950b39453.eaf8b91457ec7eb9
+ 5524316c22117528.3db81f212f6a3631.d3648a4bf8bd01d2.e3aacf52b02d839e
+ 7cd7e2ce949d8d1d.040ca67e90f187c3.ba373f836ad0e775.6f00d22bdd05a02b
+ 668208d8fac5b6f7.e9761318ae614a80.f69d2beb43797fe7.69c63c89fa7f928e
+ afc78b5921a815f0
+ after
+ 0000000000000000.0000000000000000.d3648a4bf8bd01d2.e3f0cf52b02d839e
+ 5524316c22117528.3db81f212f6a3631.d3648a4bf8bd01d2.e3aacf52b02d839e
+ 7cd7e2ce949d8d1d.040ca67e90f187c3.ba373f836ad0e775.6f00d22bdd05a02b
+ 668208d8fac5b6f7.e9761318ae614a80.f69d2beb43797fe7.69c63c89fa7f928e
+ afc78b5921a815f0
+VPINSRB_128_2of3(mem)
+ before
+ 1cd03a88708ae580.7072a0f5f1142d63.c7c2e3daa6c53c94.e5e14af11d4308d4
+ 8baec5000333bd67.f6f4a49114162d0d.79bc90b09429182a.e250990097babcea
+ da2ba9aff5af5bd4.54521218ff58f4a0.dd2f9886929a9c6e.483612844b6ad8d3
+ e3146080630978f1.e6d8e5f64f65bcc9.cde97648bf23828e.75dfb3e9d5e0983b
+ c497779bd2a737cf
+ after
+ 1cd03a88708ae580.7072a0f5f1142d63.c7c2e3daa6c53c94.e5e14af11d4308d4
+ 8baec5000333bd67.f6f4a49114162d0d.79bc90b09429182a.e250990097babcea
+ 0000000000000000.0000000000000000.79bc90b09429d42a.e250990097babcea
+ e3146080630978f1.e6d8e5f64f65bcc9.cde97648bf23828e.75dfb3e9d5e0983b
+ c497779bd2a737cf
+
+VPINSRB_128_2of3(reg)
+ before
+ 90a95a06dd4cf23b.8434685f684dd3eb.08d41997a0c9c233.27b4a6e335d186b4
+ 37635997935a052a.97593c38208726ed.1791ab678d11418b.c55da54110ae660c
+ 130f6fb88f5dac49.f94d59f7a8c42e24.6d5a95d3b3c8767d.85b0ee506dc8dcc3
+ 82fa98d76ee22244.87de39881c0fa7bb.677cd545ad7b9db4.4179fdfa672ba505
+ d6844e2d1be27cfd
+ after
+ 0000000000000000.0000000000000000.1791ab678d11418b.c5fda54110ae660c
+ 37635997935a052a.97593c38208726ed.1791ab678d11418b.c55da54110ae660c
+ 130f6fb88f5dac49.f94d59f7a8c42e24.6d5a95d3b3c8767d.85b0ee506dc8dcc3
+ 82fa98d76ee22244.87de39881c0fa7bb.677cd545ad7b9db4.4179fdfa672ba505
+ d6844e2d1be27cfd
+VPINSRB_128_2of3(mem)
+ before
+ 219d5dd4a4f91fd8.de70d05ecb74a4c6.1bd65ad797754ddf.6143662b17b4f2dd
+ fc8fa7da1e7c48c1.85bd13bb439f6e7b.920237d03500dbbc.b6fb44ef8e01b0a3
+ 4427a72da678b4e5.d12d5e5971f0bb11.c92e4c6013bf0e7d.c4f06cffadee14b3
+ d531d9b858f81e70.1f0baca4f1f2c832.9a2516714cbba14f.e66dd9c611065ab9
+ 78c087b055d5be60
+ after
+ 219d5dd4a4f91fd8.de70d05ecb74a4c6.1bd65ad797754ddf.6143662b17b4f2dd
+ fc8fa7da1e7c48c1.85bd13bb439f6e7b.920237d03500dbbc.b6fb44ef8e01b0a3
+ 0000000000000000.0000000000000000.920237d03500ddbc.b6fb44ef8e01b0a3
+ d531d9b858f81e70.1f0baca4f1f2c832.9a2516714cbba14f.e66dd9c611065ab9
+ 78c087b055d5be60
+
+VPINSRB_128_2of3(reg)
+ before
+ d633722916e77b55.8c79b9684f09438d.cca5f9086031d18a.e2b50ff1fd02525d
+ 5c13969defc9ce43.43cbc327a8b6df69.324541f15a3a12c6.7da8b5ca419fdbd5
+ 65acf0787d06f3d7.d7f374e27e0bae2f.ae3881cb7a98c692.47cb83ea359ff8e0
+ 4f4a7b275b2b25bd.24bc4786ed156b0c.9dcab3025cd72a99.1ceaf53cf40d67ac
+ d9d188ac9bf5e265
+ after
+ 0000000000000000.0000000000000000.324541f15a3a12c6.7d65b5ca419fdbd5
+ 5c13969defc9ce43.43cbc327a8b6df69.324541f15a3a12c6.7da8b5ca419fdbd5
+ 65acf0787d06f3d7.d7f374e27e0bae2f.ae3881cb7a98c692.47cb83ea359ff8e0
+ 4f4a7b275b2b25bd.24bc4786ed156b0c.9dcab3025cd72a99.1ceaf53cf40d67ac
+ d9d188ac9bf5e265
+VPINSRB_128_2of3(mem)
+ before
+ 584cb72645632637.7538331426c3a1a0.06f3b8fd12dfd32c.5946d5039d847a88
+ 7627fe960f64ef4d.32c414ad795aa32c.596443350875a2ba.3ffae238d92af20a
+ 0f2dd9e91404f8d3.e4381b5cf17d670f.f9db6518ece393e3.ab30d70fab55cdcc
+ ff2bc409704dfef6.e6e1428f29b628f3.c2249994d93664d2.f936aef2af92487a
+ 8556654f826c9ebf
+ after
+ 584cb72645632637.7538331426c3a1a0.06f3b8fd12dfd32c.5946d5039d847a88
+ 7627fe960f64ef4d.32c414ad795aa32c.596443350875a2ba.3ffae238d92af20a
+ 0000000000000000.0000000000000000.59644335087588ba.3ffae238d92af20a
+ ff2bc409704dfef6.e6e1428f29b628f3.c2249994d93664d2.f936aef2af92487a
+ 8556654f826c9ebf
+
+VPINSRB_128_3of3(reg)
+ before
+ abddf791bf6f0d48.21ed3ce3404dbde2.930b87b1bd942384.900b5b94ec7acfb4
+ c71661240328cfc0.533fbc64a010f0c2.4902e52e4aa0936f.3f5b270440b990b5
+ 354f9d74e92221d4.70edc077aba055c3.621259726c68b660.abe279d0f2016500
+ 51d2a9ed0eea3e30.54c3c4077d0ba611.3c87dde9be78c602.b06acee41d5e08c2
+ 29c0a12ddeda3626
+ after
+ 0000000000000000.0000000000000000.4902e5264aa0936f.3f5b270440b990b5
+ c71661240328cfc0.533fbc64a010f0c2.4902e52e4aa0936f.3f5b270440b990b5
+ 354f9d74e92221d4.70edc077aba055c3.621259726c68b660.abe279d0f2016500
+ 51d2a9ed0eea3e30.54c3c4077d0ba611.3c87dde9be78c602.b06acee41d5e08c2
+ 29c0a12ddeda3626
+VPINSRB_128_3of3(mem)
+ before
+ f4b06e955083aa59.77ed80fb0d0a637f.db8c4402335c9fd7.31ac6fffdc5a0002
+ ec06b10990652187.03ea1e0b8211cc6e.e115bd53e9a0fe42.9fce0a20639ca00c
+ ed8de776b98a57db.51167f870a88b5a8.412baae6b9e27d7d.e039aab8eec9e1cb
+ d2138ac7e7000882.bdbda0dc41fd59da.d99887a7c22fd9b5.51394c341a6e00eb
+ 4f1aeafe8216391a
+ after
+ f4b06e955083aa59.77ed80fb0d0a637f.db8c4402335c9fd7.31ac6fffdc5a0002
+ ec06b10990652187.03ea1e0b8211cc6e.e115bd53e9a0fe42.9fce0a20639ca00c
+ 0000000000000000.0000000000000000.0215bd53e9a0fe42.9fce0a20639ca00c
+ d2138ac7e7000882.bdbda0dc41fd59da.d99887a7c22fd9b5.51394c341a6e00eb
+ 4f1aeafe8216391a
+
+VPINSRB_128_3of3(reg)
+ before
+ 34288284c34dc701.796218e737d3efa7.a22a7b77c2fbf5b0.8428d0821d91cd16
+ 5dae0f3178a0e74f.bd470dc4c50dc977.5eab0ec3290fc5d5.1da90264e91616cb
+ 26f98e713e9ad5ae.798ee349acbd521d.4c8a552b13c305f5.82e698373fca7000
+ eb55f9afb0c7cdca.8b03186208ec46c6.c8144a1d1ca6f0be.8eaa0ee83eb797e3
+ 1cc2e064ffec469e
+ after
+ 0000000000000000.0000000000000000.5eab0e9e290fc5d5.1da90264e91616cb
+ 5dae0f3178a0e74f.bd470dc4c50dc977.5eab0ec3290fc5d5.1da90264e91616cb
+ 26f98e713e9ad5ae.798ee349acbd521d.4c8a552b13c305f5.82e698373fca7000
+ eb55f9afb0c7cdca.8b03186208ec46c6.c8144a1d1ca6f0be.8eaa0ee83eb797e3
+ 1cc2e064ffec469e
+VPINSRB_128_3of3(mem)
+ before
+ 0afa8a96a0723b5d.090e4e596bb40a51.cd7226fbf6a8609e.2d96eb04df41c3da
+ 321e89693d572f4d.da7088db0aecc9ec.1da68c0091fc5dd0.d959334cf822baf5
+ 72fa58cbf1a6e19a.bbc7a39f29fc464a.556cc35ef6f4f989.27ac1e6204d410bc
+ a45a73a7d86b0b6f.085e9c12666ebc15.539048ff419deff5.72daa8b09ee402db
+ 182ecea363ddccfd
+ after
+ 0afa8a96a0723b5d.090e4e596bb40a51.cd7226fbf6a8609e.2d96eb04df41c3da
+ 321e89693d572f4d.da7088db0aecc9ec.1da68c0091fc5dd0.d959334cf822baf5
+ 0000000000000000.0000000000000000.daa68c0091fc5dd0.d959334cf822baf5
+ a45a73a7d86b0b6f.085e9c12666ebc15.539048ff419deff5.72daa8b09ee402db
+ 182ecea363ddccfd
+
+VPINSRB_128_3of3(reg)
+ before
+ 73f58aa8ee4baacf.a50956e90fb36af9.1d836da05ad169f9.f1df98d18c02fc3f
+ e17cda29dcbbd7fd.52d47e7db289ba64.568014b6a3ae87a4.0c222ebef630dc93
+ bc0dba94c8b89032.85876650dcfab7db.0fa28cbedc9352bf.812886b498314b1f
+ 61f424534fce111a.1bee8a4ca9111c8a.a435d226a20b08f9.2abc1c9e9014040d
+ e4a96d68fae2c489
+ after
+ 0000000000000000.0000000000000000.56801489a3ae87a4.0c222ebef630dc93
+ e17cda29dcbbd7fd.52d47e7db289ba64.568014b6a3ae87a4.0c222ebef630dc93
+ bc0dba94c8b89032.85876650dcfab7db.0fa28cbedc9352bf.812886b498314b1f
+ 61f424534fce111a.1bee8a4ca9111c8a.a435d226a20b08f9.2abc1c9e9014040d
+ e4a96d68fae2c489
+VPINSRB_128_3of3(mem)
+ before
+ 8cbcf4fdf1a947c0.2d7f16d40c8a9563.f1d5665e36daa69e.7185e05991a2e3fc
+ fcc12d4c927449de.7af88a829b7759b6.e10876739e611043.d2ddb4c344e51f74
+ 1184943ef850850e.a6ad7ec9992199c2.c8523775feb318a5.228b49d0575ffa0f
+ a7d1a6c03f48b87d.0be8ee15a2159131.8281245272db78ef.bfd99bec679dae76
+ 0414a6830f2a7858
+ after
+ 8cbcf4fdf1a947c0.2d7f16d40c8a9563.f1d5665e36daa69e.7185e05991a2e3fc
+ fcc12d4c927449de.7af88a829b7759b6.e10876739e611043.d2ddb4c344e51f74
+ 0000000000000000.0000000000000000.fc0876739e611043.d2ddb4c344e51f74
+ a7d1a6c03f48b87d.0be8ee15a2159131.8281245272db78ef.bfd99bec679dae76
+ 0414a6830f2a7858
+
+VCOMISD_128(reg)
+ before
+ 4d886701ec92945f.9a74ddbe84689d56.06f6d4d251de7cb0.eb5fb9f514e6ec4d
+ f581d9d299613d37.c638b725e3bcf2c6.f3232e6d420897ea.e0b9724a02df32ed
+ 5a4af863b224b08d.08eaafdf775171f9.2fbbf75012201e8c.3b5bcc3d58d204f8
+ d731c01ed566290d.3a5742da5c33d61a.14092be85db14c41.d91041ba31cc1f9d
+ 96a64fadaad83f06
+ after
+ 4d886701ec92945f.9a74ddbe84689d56.06f6d4d251de7cb0.eb5fb9f514e6ec4d
+ f581d9d299613d37.c638b725e3bcf2c6.f3232e6d420897ea.e0b9724a02df32ed
+ 5a4af863b224b08d.08eaafdf775171f9.2fbbf75012201e8c.3b5bcc3d58d204f8
+ d731c01ed566290d.3a5742da5c33d61a.14092be85db14c41.d91041ba31cc1f9d
+ 0000000000000001
+VCOMISD_128(mem)
+ before
+ 4ee77202de021f5f.c7802e719bb4e462.3949ea01af6cdf56.ff5bc6a2be475fb6
+ dda124a6ea567cd6.88843cc7a2991c39.e18c253f8b0a46d8.4cfbc5e9d16f9097
+ 1f9ee383e9e11294.7589e88b86a10e3e.0dee6e820d18c8cd.5736232833b41e8f
+ efab2986f7af9cc8.e9db2d2be259f61c.9b3a41b550a32161.7c58dccd7fa2434b
+ 17adec4352c63c76
+ after
+ 4ee77202de021f5f.c7802e719bb4e462.3949ea01af6cdf56.ff5bc6a2be475fb6
+ dda124a6ea567cd6.88843cc7a2991c39.e18c253f8b0a46d8.4cfbc5e9d16f9097
+ 1f9ee383e9e11294.7589e88b86a10e3e.0dee6e820d18c8cd.5736232833b41e8f
+ efab2986f7af9cc8.e9db2d2be259f61c.9b3a41b550a32161.7c58dccd7fa2434b
+ 0000000000000000
+
+VCOMISD_128(reg)
+ before
+ 848050f647ab45bd.2b93749c31cad89c.42c60812524c0f7f.663b1bc471b60cbf
+ 1f1f0252fbde9acc.ae2440b0b240803c.da9573ac73069615.4abe769b8b5d4614
+ 44d400c409e9764e.542907ae971d50d5.0e966c66e114c788.238fd027bba58b8b
+ 4fec45b60d5a16f0.f96d4782fc6b0693.3b13eeaa3601de84.cd7aa4521c999751
+ 234b6f0aca452591
+ after
+ 848050f647ab45bd.2b93749c31cad89c.42c60812524c0f7f.663b1bc471b60cbf
+ 1f1f0252fbde9acc.ae2440b0b240803c.da9573ac73069615.4abe769b8b5d4614
+ 44d400c409e9764e.542907ae971d50d5.0e966c66e114c788.238fd027bba58b8b
+ 4fec45b60d5a16f0.f96d4782fc6b0693.3b13eeaa3601de84.cd7aa4521c999751
+ 0000000000000000
+VCOMISD_128(mem)
+ before
+ 03cdab39e3b6f279.9cb3ce95a4bdb65d.78bd7b18fc385ca1.bb59f5e5115916b6
+ 48ced6cd80f7b932.867595ce6a9d9142.afe51f5cb3900f2c.ecb47e840ca8acca
+ ce186bb0bf1438eb.6b7e98cbfa86e44a.79b1af3a3e7dda60.287084f1c37bdc6b
+ 7078e6d0bc1a29cd.a619d2faf004eb23.b1eda89eb80d7a68.ccd8029ad35ee146
+ 343af7ead7dbf806
+ after
+ 03cdab39e3b6f279.9cb3ce95a4bdb65d.78bd7b18fc385ca1.bb59f5e5115916b6
+ 48ced6cd80f7b932.867595ce6a9d9142.afe51f5cb3900f2c.ecb47e840ca8acca
+ ce186bb0bf1438eb.6b7e98cbfa86e44a.79b1af3a3e7dda60.287084f1c37bdc6b
+ 7078e6d0bc1a29cd.a619d2faf004eb23.b1eda89eb80d7a68.ccd8029ad35ee146
+ 0000000000000001
+
+VCOMISD_128(reg)
+ before
+ bde05c4c6b815d58.0cbac31891144907.93943fc6e9a4e176.356485753e4cab71
+ c1172e2e2dd94ce8.7caa7f745d0f53c3.8d39dc9b81f204f2.e0e4c2a9eb4529a6
+ 9d2b6afbb6710061.9e1495d03a15052e.f255a3e553788e41.8d37db28db04af34
+ ad680b1fa4d4b670.4cc3811944341973.1d349210fbc4bb0f.1a2a4cdc2c95fb46
+ 618992b3f705c609
+ after
+ bde05c4c6b815d58.0cbac31891144907.93943fc6e9a4e176.356485753e4cab71
+ c1172e2e2dd94ce8.7caa7f745d0f53c3.8d39dc9b81f204f2.e0e4c2a9eb4529a6
+ 9d2b6afbb6710061.9e1495d03a15052e.f255a3e553788e41.8d37db28db04af34
+ ad680b1fa4d4b670.4cc3811944341973.1d349210fbc4bb0f.1a2a4cdc2c95fb46
+ 0000000000000001
+VCOMISD_128(mem)
+ before
+ 401f28985a5fcfa9.4d1a0d07938eaac0.6484bf3998784bbf.6921a4881661c909
+ 91ba8a7771afd051.d98c6d1d1e2c18fe.c024cc1d51ec593d.346ad6b93fdcf2db
+ 3124343c5702862e.ad0b25cee1393bd6.3e6d22b28c9cfd1a.d859220f13c07330
+ fd2ba3d32863ad6c.25e43387794150f3.b82b3fe26494f482.b33c86f72d9987b5
+ 1f5dfddb2af46c16
+ after
+ 401f28985a5fcfa9.4d1a0d07938eaac0.6484bf3998784bbf.6921a4881661c909
+ 91ba8a7771afd051.d98c6d1d1e2c18fe.c024cc1d51ec593d.346ad6b93fdcf2db
+ 3124343c5702862e.ad0b25cee1393bd6.3e6d22b28c9cfd1a.d859220f13c07330
+ fd2ba3d32863ad6c.25e43387794150f3.b82b3fe26494f482.b33c86f72d9987b5
+ 0000000000000001
+
+VCOMISS_128(reg)
+ before
+ 7a098329a55c5cfe.cf99522801df0136.9d6192b282d19202.0b2c9e9bf6e1f9a0
+ 1e8c154c3b5d9319.843bbd27fd813db8.71cf3fbd97743fae.143bbcc85d8ecaa1
+ 6931adb087834f15.f9dd60bd39551e20.fd79341354b791a4.ad231355b6a821b1
+ b54649c0255bca9b.084ab7d4d1675f97.9dad6f205625c590.b3b1212e1c3abbfb
+ 02b1613fab5053ab
+ after
+ 7a098329a55c5cfe.cf99522801df0136.9d6192b282d19202.0b2c9e9bf6e1f9a0
+ 1e8c154c3b5d9319.843bbd27fd813db8.71cf3fbd97743fae.143bbcc85d8ecaa1
+ 6931adb087834f15.f9dd60bd39551e20.fd79341354b791a4.ad231355b6a821b1
+ b54649c0255bca9b.084ab7d4d1675f97.9dad6f205625c590.b3b1212e1c3abbfb
+ 0000000000000000
+VCOMISS_128(mem)
+ before
+ 77ef507480f6a6ef.5f15e4eab271415a.8e503f5adfc4be4c.adb5eb50384a161d
+ ec3768b9b73970f0.c4eb7a9aca4feffc.67b9733a8277f569.88dfa40f97b2c1f8
+ 3e5527fa6b246ddd.3e14083a0883122e.6f52cf5fd38dc01b.8c7596c90eea02cc
+ 49140824b8c458e0.2adc89370899e49b.83e7cfb7f111dd8d.14c4beea3a7d1546
+ 7c1717deb6f83512
+ after
+ 77ef507480f6a6ef.5f15e4eab271415a.8e503f5adfc4be4c.adb5eb50384a161d
+ ec3768b9b73970f0.c4eb7a9aca4feffc.67b9733a8277f569.88dfa40f97b2c1f8
+ 3e5527fa6b246ddd.3e14083a0883122e.6f52cf5fd38dc01b.8c7596c90eea02cc
+ 49140824b8c458e0.2adc89370899e49b.83e7cfb7f111dd8d.14c4beea3a7d1546
+ 0000000000000001
+
+VCOMISS_128(reg)
+ before
+ 1fbc9d121fe6a0db.e9418721bb24ee25.e48ff9fd671ba2f0.7d44f02df50f06ec
+ 5bfe4cf010d38f4d.faa920df9050ebda.c87854f9c19887d8.3a35acadfd94f863
+ 8b2821e6264b4116.5816504951550a28.33e59695b099d000.9686812325ab6f1f
+ 0a87165ffcdbf0e0.df54914a1d3e093e.7f20bc3fd3acb914.6d02ea7c8860264c
+ 9b7664a243c0da15
+ after
+ 1fbc9d121fe6a0db.e9418721bb24ee25.e48ff9fd671ba2f0.7d44f02df50f06ec
+ 5bfe4cf010d38f4d.faa920df9050ebda.c87854f9c19887d8.3a35acadfd94f863
+ 8b2821e6264b4116.5816504951550a28.33e59695b099d000.9686812325ab6f1f
+ 0a87165ffcdbf0e0.df54914a1d3e093e.7f20bc3fd3acb914.6d02ea7c8860264c
+ 0000000000000001
+VCOMISS_128(mem)
+ before
+ fcae698371d547a6.366729c62e0fd957.6b3161d00e17a246.0976c162c45c7ebf
+ 6b7677092eae282d.6914568959713828.d8783cc640ed916c.2d33a16a1f355aae
+ c69a092297543bd4.01da9713198f48ff.02f49c18d0cb94de.47a358c381c48a8c
+ e8e69cb8c8d53ac7.5804e9d009f44787.c572ffb3d9bd65c5.b311e2d985944a06
+ cdcb3c18c731d6c8
+ after
+ fcae698371d547a6.366729c62e0fd957.6b3161d00e17a246.0976c162c45c7ebf
+ 6b7677092eae282d.6914568959713828.d8783cc640ed916c.2d33a16a1f355aae
+ c69a092297543bd4.01da9713198f48ff.02f49c18d0cb94de.47a358c381c48a8c
+ e8e69cb8c8d53ac7.5804e9d009f44787.c572ffb3d9bd65c5.b311e2d985944a06
+ 0000000000000000
+
+VCOMISS_128(reg)
+ before
+ f11b61ece528697d.ad25aab9dc3de134.ccdf492cc52d6e6d.fcbee08177d0c050
+ 7b4e4dc1780440d2.f124b110ef96ee44.b7b8b294eac5fc5c.85a4bb6fc80f63a9
+ c6b0fc041e529672.8fb02ca91eee1b26.76d9217213482b02.3bf00c6ae58608fc
+ 308d6b1f739da90a.6593977084512404.668f9033dd433808.fa6d4f5cec426c76
+ 9de90133f94e4b43
+ after
+ f11b61ece528697d.ad25aab9dc3de134.ccdf492cc52d6e6d.fcbee08177d0c050
+ 7b4e4dc1780440d2.f124b110ef96ee44.b7b8b294eac5fc5c.85a4bb6fc80f63a9
+ c6b0fc041e529672.8fb02ca91eee1b26.76d9217213482b02.3bf00c6ae58608fc
+ 308d6b1f739da90a.6593977084512404.668f9033dd433808.fa6d4f5cec426c76
+ 0000000000000000
+VCOMISS_128(mem)
+ before
+ 022e9dda27b6608e.143195801271b345.4e996e513ecac70a.e125fd44e3415f1c
+ 04099f3c92876884.cee77691975af1d1.26902e396765be65.44e96310c2cedcea
+ 7e46844757cc1f51.bafd0ac09fe59e57.c84352121c2ec641.ec26be021577ea1e
+ 4eb1c6e692914120.33bd4d78c69df786.127d56ca78329bc9.33270a8879c7c663
+ 7639440d894aab65
+ after
+ 022e9dda27b6608e.143195801271b345.4e996e513ecac70a.e125fd44e3415f1c
+ 04099f3c92876884.cee77691975af1d1.26902e396765be65.44e96310c2cedcea
+ 7e46844757cc1f51.bafd0ac09fe59e57.c84352121c2ec641.ec26be021577ea1e
+ 4eb1c6e692914120.33bd4d78c69df786.127d56ca78329bc9.33270a8879c7c663
+ 0000000000000000
+
+VMOVUPS_YMM_to_YMMorMEM(reg)
+ before
+ 11a866fde28dd7d2.4e16e3055de3891d.97743c25a70f3808.de0bb64b987cf82a
+ 60c06ec41f1b8453.5c405691d7cdb476.416ed233dec69d89.0ab9ee8397189b90
+ bfcc58cedc80ee97.52fc9c741a5c7e55.8cf70b0e084e62b6.70537b5d91133d26
+ 8a1a1e88b6495348.0e172f9b429aa2e6.d65ae322c034c23b.eea5d8c4a3789d18
+ 5e7b81a6e9547594
+ after
+ 60c06ec41f1b8453.5c405691d7cdb476.416ed233dec69d89.0ab9ee8397189b90
+ 60c06ec41f1b8453.5c405691d7cdb476.416ed233dec69d89.0ab9ee8397189b90
+ bfcc58cedc80ee97.52fc9c741a5c7e55.8cf70b0e084e62b6.70537b5d91133d26
+ 8a1a1e88b6495348.0e172f9b429aa2e6.d65ae322c034c23b.eea5d8c4a3789d18
+ 5e7b81a6e9547594
+VMOVUPS_YMM_to_YMMorMEM(mem)
+ before
+ 9ea0f2ee7eb182c3.1df4be5c4901ed12.6a5b8df36c95dd56.79e557dca303fac3
+ 88e1a8887e9e80d4.d4a732b83035f9a3.44943166b359ebd1.d3e262a64c4745fb
+ f90a1e6106242af1.0b7f79060770b3a4.769097e234f18882.3e9e00ee588ce08f
+ cee7cf6332513e47.1ec88cb46b3e56c4.dd1a3b520a696f96.18652d1e625f072a
+ bb83e5a4074cf678
+ after
+ cee7cf6332513e47.1ec88cb46b3e56c4.dd1a3b520a696f96.18652d1e625f072a
+ 88e1a8887e9e80d4.d4a732b83035f9a3.44943166b359ebd1.d3e262a64c4745fb
+ f90a1e6106242af1.0b7f79060770b3a4.769097e234f18882.3e9e00ee588ce08f
+ cee7cf6332513e47.1ec88cb46b3e56c4.dd1a3b520a696f96.18652d1e625f072a
+ bb83e5a4074cf678
+
+VMOVUPS_YMM_to_YMMorMEM(reg)
+ before
+ 844425ebe2dde927.e1443a7b1c307601.69ce682df82b1fad.56fd9aa251cd5d38
+ d0f3e85f8fa01be0.0fedd896e3ce8e4c.48dd0adc48c44a0b.bb062fbe262a0e95
+ f9dd2a6cab21c952.34ad279fa1354353.17406d2ffa94128b.e9017692a58b3dd9
+ 5c4fe77ed2ea2e27.2c52a28172745243.32448d91a728b5d9.bcbaeb0ae9fda82f
+ 10fd0a120f8b09c4
+ after
+ d0f3e85f8fa01be0.0fedd896e3ce8e4c.48dd0adc48c44a0b.bb062fbe262a0e95
+ d0f3e85f8fa01be0.0fedd896e3ce8e4c.48dd0adc48c44a0b.bb062fbe262a0e95
+ f9dd2a6cab21c952.34ad279fa1354353.17406d2ffa94128b.e9017692a58b3dd9
+ 5c4fe77ed2ea2e27.2c52a28172745243.32448d91a728b5d9.bcbaeb0ae9fda82f
+ 10fd0a120f8b09c4
+VMOVUPS_YMM_to_YMMorMEM(mem)
+ before
+ c196509632411cc4.56931c019f89880c.d4a6c52a73947448.f535676fee0a6da1
+ ac5038836e2c9f5a.41f5c361ae8a11ac.06760c85bfa3688d.bb5ff53368c9768d
+ abf83ec3e0574cb2.7ac3da0b9c7705b4.9f8ef37e73ace83f.e20e354ab4ee0e4c
+ 9b5bde44a3cedff9.5d485c6905dea2cf.7bbaf701aabcb189.c58e22216b076f88
+ bf2ab8222b9fd6ee
+ after
+ 9b5bde44a3cedff9.5d485c6905dea2cf.7bbaf701aabcb189.c58e22216b076f88
+ ac5038836e2c9f5a.41f5c361ae8a11ac.06760c85bfa3688d.bb5ff53368c9768d
+ abf83ec3e0574cb2.7ac3da0b9c7705b4.9f8ef37e73ace83f.e20e354ab4ee0e4c
+ 9b5bde44a3cedff9.5d485c6905dea2cf.7bbaf701aabcb189.c58e22216b076f88
+ bf2ab8222b9fd6ee
+
+VMOVUPS_YMM_to_YMMorMEM(reg)
+ before
+ 2e30f4bb90437e29.584395f1d49d165b.46cf46e9834b22aa.76c593fa80de7f98
+ 6dead156357ea5e6.be7cdeb58ed1ab04.92a592f5b549c2f1.6c7c4355121e0d98
+ d7a54a61b7dc84d1.a9d4357eee765b1e.9b163efb3564be4f.39ac84ff7c8918b4
+ caad5e47b1e95a95.f41616371096e2d8.be6e45669f285171.b91fd0e2d92a5c19
+ c8a2a5ec450d94f2
+ after
+ 6dead156357ea5e6.be7cdeb58ed1ab04.92a592f5b549c2f1.6c7c4355121e0d98
+ 6dead156357ea5e6.be7cdeb58ed1ab04.92a592f5b549c2f1.6c7c4355121e0d98
+ d7a54a61b7dc84d1.a9d4357eee765b1e.9b163efb3564be4f.39ac84ff7c8918b4
+ caad5e47b1e95a95.f41616371096e2d8.be6e45669f285171.b91fd0e2d92a5c19
+ c8a2a5ec450d94f2
+VMOVUPS_YMM_to_YMMorMEM(mem)
+ before
+ 41017e07dd3f7e6c.a04d0674bf3262de.7d0dfdcc0e3ffb5c.57f9a3a29022b802
+ 0207d721bdcbd3b3.b7d340547e43d75a.1f86672a067d63d7.c203551ba3dd2faf
+ e6822d2500bd52f2.6989065389a6f6b2.b64dcf3b145ad674.5bd7563d74e5f124
+ c93cfbffc222b655.13bc56de7de9fa95.1e2eb1ec53e41060.7dc3a174a1c73b0c
+ 8611352dc30e4914
+ after
+ c93cfbffc222b655.13bc56de7de9fa95.1e2eb1ec53e41060.7dc3a174a1c73b0c
+ 0207d721bdcbd3b3.b7d340547e43d75a.1f86672a067d63d7.c203551ba3dd2faf
+ e6822d2500bd52f2.6989065389a6f6b2.b64dcf3b145ad674.5bd7563d74e5f124
+ c93cfbffc222b655.13bc56de7de9fa95.1e2eb1ec53e41060.7dc3a174a1c73b0c
+ 8611352dc30e4914
+
+VDPPD_128_1of4(reg)
+ before
+ d10e0bd2784757e7.8702bd9b2005ba0a.12b92c5ff69821ad.33f5892ae027ccc7
+ ba0521d05cfda032.fba0efe535721a3b.c0c982438e3da5a7.d06dd4dfd62dc7d4
+ 9d4471940abc62a0.03e20dc91e769414.7a3b56f7e466c22e.d3640df95104bcb4
+ d616f9891e10d6df.7a949433f61ce2c2.9d5aa3e5919fb6ef.17a4b0636eb86992
+ 77fa39084953889b
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ ba0521d05cfda032.fba0efe535721a3b.c0c982438e3da5a7.d06dd4dfd62dc7d4
+ 9d4471940abc62a0.03e20dc91e769414.7a3b56f7e466c22e.d3640df95104bcb4
+ d616f9891e10d6df.7a949433f61ce2c2.9d5aa3e5919fb6ef.17a4b0636eb86992
+ 77fa39084953889b
+VDPPD_128_1of4(mem)
+ before
+ d13224d6fde3d6fa.c0c6b51b35863b98.3b81fe10da70c171.8371657b3472bb95
+ ff18eeb8a6740edd.b9a19fb5eba9cb7a.2477c94ae57fed4c.89ce9824666d0ecd
+ df78129b6111ee6d.1cf3b5c5da06c32f.0f4071cf34542180.0bbb394cc51cea43
+ 4b1d0c6949c630d8.4408f2b6a1285f63.daa97089e2fb1b39.6685425fed098da2
+ f477b1c979c23197
+ after
+ d13224d6fde3d6fa.c0c6b51b35863b98.3b81fe10da70c171.8371657b3472bb95
+ ff18eeb8a6740edd.b9a19fb5eba9cb7a.2477c94ae57fed4c.89ce9824666d0ecd
+ df78129b6111ee6d.1cf3b5c5da06c32f.0f4071cf34542180.0bbb394cc51cea43
+ 4b1d0c6949c630d8.4408f2b6a1285f63.daa97089e2fb1b39.6685425fed098da2
+ f477b1c979c23197
+
+VDPPD_128_1of4(reg)
+ before
+ 12df82f606d313cd.21d4580f7b9f904a.8f2c52f5da9bdac3.5f7e44660b8194a2
+ 1c08af532fc76ef1.3b6a727913a9ccef.57abd1ec21ec71fb.7c8a6851cdf14be8
+ 6e3d364a902a7faf.77a9d7942bef9ef2.fad06b0813a560b6.0b9b58364158fa36
+ 64cb1248c68882b2.af5d024ae27ec380.d3e81db64b55e3a1.ea7c900185c15eb9
+ f3f88d9eb438339c
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 1c08af532fc76ef1.3b6a727913a9ccef.57abd1ec21ec71fb.7c8a6851cdf14be8
+ 6e3d364a902a7faf.77a9d7942bef9ef2.fad06b0813a560b6.0b9b58364158fa36
+ 64cb1248c68882b2.af5d024ae27ec380.d3e81db64b55e3a1.ea7c900185c15eb9
+ f3f88d9eb438339c
+VDPPD_128_1of4(mem)
+ before
+ 03dcc9f9ebc9340c.5afe3fba6d6eb3a7.c0546f895160f6c4.3d3fe26066853568
+ f7f4c2ff46811f35.ac22b90b20674d39.87599b3c96a4f5eb.9521b674ffc393b6
+ a90cf49ae06bae42.b6837ca67bff8d15.de37004fcd537a20.38da965cb29b3937
+ f6efd9b8d5949d60.d36c85f91bc3afe7.a2bb1cae117b4290.80b67c861d976299
+ cb00665dd9454b85
+ after
+ 03dcc9f9ebc9340c.5afe3fba6d6eb3a7.c0546f895160f6c4.3d3fe26066853568
+ f7f4c2ff46811f35.ac22b90b20674d39.87599b3c96a4f5eb.9521b674ffc393b6
+ a90cf49ae06bae42.b6837ca67bff8d15.de37004fcd537a20.38da965cb29b3937
+ f6efd9b8d5949d60.d36c85f91bc3afe7.a2bb1cae117b4290.80b67c861d976299
+ cb00665dd9454b85
+
+VDPPD_128_1of4(reg)
+ before
+ 73064f4d843130aa.ba6bef434207a9ba.612bcf6f9b3eef5a.b0b16a457f270867
+ d51234c2bae54db2.d14ab02942d08f7d.bb0a567498fd881b.e2e56600326489d0
+ 4e710f2816efdd4a.18599b55f2fb08d5.3d561774ad8bb7d5.15238dcb463c81f8
+ 386fdeec34db1d1d.696429b26d95d3ed.435b0cdc7774b835.25375993d8beac0a
+ eeec484204f3c533
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ d51234c2bae54db2.d14ab02942d08f7d.bb0a567498fd881b.e2e56600326489d0
+ 4e710f2816efdd4a.18599b55f2fb08d5.3d561774ad8bb7d5.15238dcb463c81f8
+ 386fdeec34db1d1d.696429b26d95d3ed.435b0cdc7774b835.25375993d8beac0a
+ eeec484204f3c533
+VDPPD_128_1of4(mem)
+ before
+ 4c0fd5c5e5e9899f.f0579c78b13349d8.a137d72ed0a9aaf2.286533169145c6e6
+ 1b6d7d0997abb479.d277453a28859d26.9c9e22b536444a0f.4ac0878f98881e96
+ 37d0baf9374601ee.3a19d59c365d54b4.36658531bb716f71.04b704b427ccfcee
+ 7c040a81e0c52e29.848b490c7745ab2e.4b577c8f7d3cd444.b197a7efda9a9b9d
+ afad6bae4e80394d
+ after
+ 4c0fd5c5e5e9899f.f0579c78b13349d8.a137d72ed0a9aaf2.286533169145c6e6
+ 1b6d7d0997abb479.d277453a28859d26.9c9e22b536444a0f.4ac0878f98881e96
+ 37d0baf9374601ee.3a19d59c365d54b4.36658531bb716f71.04b704b427ccfcee
+ 7c040a81e0c52e29.848b490c7745ab2e.4b577c8f7d3cd444.b197a7efda9a9b9d
+ afad6bae4e80394d
+
+VDPPD_128_2of4(reg)
+ before
+ 58434c5c1f0910aa.c6d7e88caf34f557.0c179cf485ccdd3f.b74184bb95b236b3
+ 0aa54665e8c25c61.f114d008bfa012a4.2e0acac2ff7b2894.56ef17a221de51eb
+ 1f21553545365b1e.d9863fe12d14433b.46afcfe17ee0c6d8.042db32e3dcce017
+ f5027638d3f1478c.5afaaf01149c4249.b054a8bda186f3b8.9cc7d34d0489a164
+ fc89f3ea92204dfe
+ after
+ 0000000000000000.0000000000000000.1b2cdb840fa41bfd.0000000000000000
+ 0aa54665e8c25c61.f114d008bfa012a4.2e0acac2ff7b2894.56ef17a221de51eb
+ 1f21553545365b1e.d9863fe12d14433b.46afcfe17ee0c6d8.042db32e3dcce017
+ f5027638d3f1478c.5afaaf01149c4249.b054a8bda186f3b8.9cc7d34d0489a164
+ fc89f3ea92204dfe
+VDPPD_128_2of4(mem)
+ before
+ ff3e90f0049da310.e693a3da2e805d58.503c9e559145cbf9.c8434fc201f9ede0
+ 81b3244d750d5ec7.5021db87f16ed82d.961887c9bf1a9c78.eacac25d3cc6eefb
+ 5eb52dec027b394e.8df817acb847f6b8.0a5ae74aba276ff2.7233fcf8ee7833b5
+ 710e27b9c6f3f0d2.fa6454b32098f1a5.87cd38c2a0790192.bccbfa00b29cf8bc
+ 24deb6e225bc78ba
+ after
+ ff3e90f0049da310.e693a3da2e805d58.503c9e559145cbf9.c8434fc201f9ede0
+ 81b3244d750d5ec7.5021db87f16ed82d.961887c9bf1a9c78.eacac25d3cc6eefb
+ 5eb52dec027b394e.8df817acb847f6b8.0a5ae74aba276ff2.7233fcf8ee7833b5
+ 710e27b9c6f3f0d2.fa6454b32098f1a5.87cd38c2a0790192.bccbfa00b29cf8bc
+ 24deb6e225bc78ba
+
+VDPPD_128_2of4(reg)
+ before
+ 06b72e08e267f05b.988a8ca1de82417e.f4b18f0ac4ec069f.e93ff81f8a1b0e84
+ bda45de085269c4c.aef7d98e6533e680.d52bc31b41cf7053.0b7aa24c961951f6
+ a7ef3fd5ab87b839.8e208b6d78129c01.fa1dec5432ce6c6d.cb4bb235e0808712
+ 1fe6d153f0157fce.16d01d2b322c1f30.bfd4062034743698.037ea4c5835b6c04
+ 91dff5eb9bb7bcf9
+ after
+ 0000000000000000.0000000000000000.96d70d4440523452.0000000000000000
+ bda45de085269c4c.aef7d98e6533e680.d52bc31b41cf7053.0b7aa24c961951f6
+ a7ef3fd5ab87b839.8e208b6d78129c01.fa1dec5432ce6c6d.cb4bb235e0808712
+ 1fe6d153f0157fce.16d01d2b322c1f30.bfd4062034743698.037ea4c5835b6c04
+ 91dff5eb9bb7bcf9
+VDPPD_128_2of4(mem)
+ before
+ 4f3a2090459e321d.80d30dc6ee5d2eb5.20d40cb2b08c2a36.819c0eebe24d0a80
+ 1b5aa1a19c1e8b9b.2803f19a44ea019d.8af8d2f00d3f7b42.9ac1ff21d9e623d3
+ cf0cf40abd4383a0.72c1783b8c483330.2e08edd0664fcb7e.678fd52eb4cabe3a
+ 491d96b8c318d558.b95b9f156203011b.ead0d83ed6cad917.44528c7e0f851764
+ 8d55207d87a469fb
+ after
+ 4f3a2090459e321d.80d30dc6ee5d2eb5.20d40cb2b08c2a36.819c0eebe24d0a80
+ 1b5aa1a19c1e8b9b.2803f19a44ea019d.8af8d2f00d3f7b42.9ac1ff21d9e623d3
+ cf0cf40abd4383a0.72c1783b8c483330.2e08edd0664fcb7e.678fd52eb4cabe3a
+ 491d96b8c318d558.b95b9f156203011b.ead0d83ed6cad917.44528c7e0f851764
+ 8d55207d87a469fb
+
+VDPPD_128_2of4(reg)
+ before
+ 9ee68e98b8b2f2ab.63570295cba93eee.5b1b609463a8a709.981c0f2579bc5f38
+ d34fd1393d3ceb22.fb86b38ff0027a8e.b24fb9252ac361a7.16b70e746c301a0e
+ 88dde5ceb2cc9309.eb7828904f304566.1c41a53254de6aa0.3e6e5114cb32c6c4
+ 19dcc6c2b4f0250f.10f8da86033e5a9f.f33e20297c87ffa2.ed0d55f2b1ce1e87
+ 006095fa3a11e083
+ after
+ 0000000000000000.0000000000000000.1535d7f8b78ffe28.0000000000000000
+ d34fd1393d3ceb22.fb86b38ff0027a8e.b24fb9252ac361a7.16b70e746c301a0e
+ 88dde5ceb2cc9309.eb7828904f304566.1c41a53254de6aa0.3e6e5114cb32c6c4
+ 19dcc6c2b4f0250f.10f8da86033e5a9f.f33e20297c87ffa2.ed0d55f2b1ce1e87
+ 006095fa3a11e083
+VDPPD_128_2of4(mem)
+ before
+ 51338d198306c6e3.e2987180de34dcde.47d1475c29397668.959126753e495c56
+ bd52ba39a7ba8cd4.3f5ce076cd23f422.6ad0e9fedc2c55eb.5c88b48238b1bc6a
+ 20889648c338ef82.8c76110f1d49ab88.56c13e583823b255.a56ec5bb034a5c8a
+ 57a39f30f28cac18.2430ffb768323bbc.e770c2565a2a4bd1.cd8e558e3da07862
+ 2e35606782404c9d
+ after
+ 51338d198306c6e3.e2987180de34dcde.47d1475c29397668.959126753e495c56
+ bd52ba39a7ba8cd4.3f5ce076cd23f422.6ad0e9fedc2c55eb.5c88b48238b1bc6a
+ 20889648c338ef82.8c76110f1d49ab88.56c13e583823b255.a56ec5bb034a5c8a
+ 57a39f30f28cac18.2430ffb768323bbc.e770c2565a2a4bd1.cd8e558e3da07862
+ 2e35606782404c9d
+
+VDPPD_128_3of4(reg)
+ before
+ 25afe3b06db513e7.3c6d50df51c27cc2.65d7a7da4d6be169.f9a9efe45e4eda8c
+ 0f48d8d69a8b0aee.acb32640fbe71ead.aab703e4657fd93c.693843ef5f9a1bb1
+ 464c3d45a64f6d5c.83419b3f0d074c05.4f1c11424efb5ee1.11e83961791bcc6d
+ 27060e6a2c8c77dd.9de32dc8a22cc3f6.af51cc5ea46aad03.ce864d28c9dca7ec
+ 7cdffb2e6be96859
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 0f48d8d69a8b0aee.acb32640fbe71ead.aab703e4657fd93c.693843ef5f9a1bb1
+ 464c3d45a64f6d5c.83419b3f0d074c05.4f1c11424efb5ee1.11e83961791bcc6d
+ 27060e6a2c8c77dd.9de32dc8a22cc3f6.af51cc5ea46aad03.ce864d28c9dca7ec
+ 7cdffb2e6be96859
+VDPPD_128_3of4(mem)
+ before
+ f7bdc0617a4fcde1.0ec445afc9cf651e.d66457c7d7643fab.28a431a60258024f
+ 1bec16ac121990af.57d0e08219a273cb.0a929528c7ba7b50.155f3a8405529970
+ c43a7bfb50536ef0.5e77d94eb693dd8f.153763d88e3b3412.d1cfe56648e2ad13
+ ce726b3a4f0a23cf.7f052e7f3f2ede17.d3203ec149f2261d.ba402db767977be3
+ 2afe0ee3fffa3f8e
+ after
+ f7bdc0617a4fcde1.0ec445afc9cf651e.d66457c7d7643fab.28a431a60258024f
+ 1bec16ac121990af.57d0e08219a273cb.0a929528c7ba7b50.155f3a8405529970
+ c43a7bfb50536ef0.5e77d94eb693dd8f.153763d88e3b3412.d1cfe56648e2ad13
+ ce726b3a4f0a23cf.7f052e7f3f2ede17.d3203ec149f2261d.ba402db767977be3
+ 2afe0ee3fffa3f8e
+
+VDPPD_128_3of4(reg)
+ before
+ 7f558456ac9934bd.145f60552c496a7a.16c6db814dfeb30e.2019a1d114eb0c9c
+ 13908c7c0900971f.74ced838021c001a.7f05dac07f8f9821.d8ee08f20a33a4bc
+ 44fd21c1b2b9a45d.c98b4ecfed90a1de.161029a86e6dc9fc.d66aef1247d5a7a9
+ 6ce63f9144529726.ef623e060bb009f0.3731c3a5b825814a.f85bd31ce8ddd48e
+ 198b2efc0858e698
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 13908c7c0900971f.74ced838021c001a.7f05dac07f8f9821.d8ee08f20a33a4bc
+ 44fd21c1b2b9a45d.c98b4ecfed90a1de.161029a86e6dc9fc.d66aef1247d5a7a9
+ 6ce63f9144529726.ef623e060bb009f0.3731c3a5b825814a.f85bd31ce8ddd48e
+ 198b2efc0858e698
+VDPPD_128_3of4(mem)
+ before
+ 15c77e9ec45198f2.e898e2595a56ab24.c21f24ca7588f37c.3eb5a423f942fdb7
+ c7db3eee38d4a6c9.155f068391521d04.1d8d7d0549251caf.87e8c88fcc5179f1
+ 0d93ebd87eeece49.4d87a87d85d12971.de7ac3a5a3923fb5.6e162c53cedc30a2
+ c2bbff48b5aaca9d.ed5bc3b1d05f0a18.e0b074959edb1ab9.4e8bcbdd9a725f76
+ 8592a197cc9c421a
+ after
+ 15c77e9ec45198f2.e898e2595a56ab24.c21f24ca7588f37c.3eb5a423f942fdb7
+ c7db3eee38d4a6c9.155f068391521d04.1d8d7d0549251caf.87e8c88fcc5179f1
+ 0d93ebd87eeece49.4d87a87d85d12971.de7ac3a5a3923fb5.6e162c53cedc30a2
+ c2bbff48b5aaca9d.ed5bc3b1d05f0a18.e0b074959edb1ab9.4e8bcbdd9a725f76
+ 8592a197cc9c421a
+
+VDPPD_128_3of4(reg)
+ before
+ 6e79aaef01e8143a.c11ef82bf61457f2.5229538d1189fda4.fefc0bc1560d67e8
+ 658ae250d4e11382.e88a516b5f393173.d63b547ce1da3ec2.162a0515e833e36e
+ c5124626e214799c.11c986f60c24134d.d6dec3eadede091e.0306dc7d70594976
+ ec5dd1ddc70c8237.1aa814b718e2bbab.ae5e9b43a4229963.a05c0ee5088c572d
+ cbf71639cfd7c7be
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 658ae250d4e11382.e88a516b5f393173.d63b547ce1da3ec2.162a0515e833e36e
+ c5124626e214799c.11c986f60c24134d.d6dec3eadede091e.0306dc7d70594976
+ ec5dd1ddc70c8237.1aa814b718e2bbab.ae5e9b43a4229963.a05c0ee5088c572d
+ cbf71639cfd7c7be
+VDPPD_128_3of4(mem)
+ before
+ 5ea47165df465556.35b77fe11e556cfd.ddf37599a07de2ba.ba07d8f3ce312b3e
+ 3630995654e6bf20.fb6b4c9e837b719b.3876278abf0447a6.56257666f998fb5a
+ 30650cf64bc2bf49.9cc73581930bcebc.05fca5759180a49a.de037108c0e14564
+ 260f4533dfe712fd.721534f4e991be0d.22536c4633ffb6c3.aeefc646bf9a4408
+ 2233708a934f35f1
+ after
+ 5ea47165df465556.35b77fe11e556cfd.ddf37599a07de2ba.ba07d8f3ce312b3e
+ 3630995654e6bf20.fb6b4c9e837b719b.3876278abf0447a6.56257666f998fb5a
+ 30650cf64bc2bf49.9cc73581930bcebc.05fca5759180a49a.de037108c0e14564
+ 260f4533dfe712fd.721534f4e991be0d.22536c4633ffb6c3.aeefc646bf9a4408
+ 2233708a934f35f1
+
+VDPPD_128_4of4(reg)
+ before
+ 961c6b42d88b53cc.f6fcc0f72d607367.dba2476522977f39.6945f6e9c18c394d
+ 66f6b3d828dadc44.7af7f9305039a0b4.31ba6a3ed9ab4bee.b79fc14a5633e863
+ ee0c45ba22c80a06.8fcb6dc9647e5310.d1a997edaa585ed5.e92d48560e018131
+ 8aac1b5360e21abe.114597ae873c49a6.18baccdd322bf69c.d9bb07f70601bee5
+ 64147b1b59405ba8
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 66f6b3d828dadc44.7af7f9305039a0b4.31ba6a3ed9ab4bee.b79fc14a5633e863
+ ee0c45ba22c80a06.8fcb6dc9647e5310.d1a997edaa585ed5.e92d48560e018131
+ 8aac1b5360e21abe.114597ae873c49a6.18baccdd322bf69c.d9bb07f70601bee5
+ 64147b1b59405ba8
+VDPPD_128_4of4(mem)
+ before
+ 66061eac24c915a9.9620330f7eb34717.dd31f3cbd27e3da2.603b047a0daf4def
+ bc5b6e9882a8a912.6eb6895a19c8cebe.cd5bfd0c6351ec31.07763b30d670a07a
+ 40e0e6ca90ead00f.6db817a0ccaceb5e.be8f315d56c0127f.67b86d6b2afb2ae8
+ cf61032e699a49ce.f173db4d34ebdaa4.8c990cabc6d76bb8.dd4d9697a4db29e5
+ c581b320e09cd71f
+ after
+ 66061eac24c915a9.9620330f7eb34717.dd31f3cbd27e3da2.603b047a0daf4def
+ bc5b6e9882a8a912.6eb6895a19c8cebe.cd5bfd0c6351ec31.07763b30d670a07a
+ 40e0e6ca90ead00f.6db817a0ccaceb5e.be8f315d56c0127f.67b86d6b2afb2ae8
+ cf61032e699a49ce.f173db4d34ebdaa4.8c990cabc6d76bb8.dd4d9697a4db29e5
+ c581b320e09cd71f
+
+VDPPD_128_4of4(reg)
+ before
+ 7ca0bf737bcb713f.45aa3fb02ac4ce78.5533cfceec11d63b.134409e0cfa3b207
+ 5cf6b6fa10f332f4.7e87183cee741c3c.f543f18d91ab1dd1.2f5da4ea8e2ea498
+ c2ce95233ca157e8.56c409bed2b7ef44.2cf13df8be44e80f.bcb15ab31e87fd98
+ 0a7556589b5f1cc8.a92c8e22f19902bc.5887ad790f6976a4.960aa5299cb77833
+ 9934033724ccd395
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 5cf6b6fa10f332f4.7e87183cee741c3c.f543f18d91ab1dd1.2f5da4ea8e2ea498
+ c2ce95233ca157e8.56c409bed2b7ef44.2cf13df8be44e80f.bcb15ab31e87fd98
+ 0a7556589b5f1cc8.a92c8e22f19902bc.5887ad790f6976a4.960aa5299cb77833
+ 9934033724ccd395
+VDPPD_128_4of4(mem)
+ before
+ a1fdefc9d0d2c8e9.9037f707c7bbbd3f.538c2354672412d2.d3523f7e21a50139
+ 8a30e5cbbfd3135b.b060739b5f4175fa.30b045415166dbaf.fb9eee729084c67d
+ 309861290add7218.c63cc680fc7b81a4.1c646fd3cb6a1882.2bb7b6c1f793011a
+ 6f02e0cfcffb9f4c.2e17ed223cf81dea.f3741df8f03d8775.bee993d7f25dedbd
+ 127f82201e6ec811
+ after
+ a1fdefc9d0d2c8e9.9037f707c7bbbd3f.538c2354672412d2.d3523f7e21a50139
+ 8a30e5cbbfd3135b.b060739b5f4175fa.30b045415166dbaf.fb9eee729084c67d
+ 309861290add7218.c63cc680fc7b81a4.1c646fd3cb6a1882.2bb7b6c1f793011a
+ 6f02e0cfcffb9f4c.2e17ed223cf81dea.f3741df8f03d8775.bee993d7f25dedbd
+ 127f82201e6ec811
+
+VDPPD_128_4of4(reg)
+ before
+ 81c77e081753cbc3.233adda92a3a5622.443ce2edbb418477.90accb9bdceae1b4
+ 680b83fb7896357e.270cd4a436a555c7.64f8a34d14e4f4f9.d1d7f6a8ac7de56c
+ 24988d65ddc640ef.594441aa10495667.ea972bafe46ca719.91c3180a7c034ec9
+ 0fba98b3e36c29c2.94ada1a9d330162d.3265777dc665d986.ac3aafaf6687d7f6
+ fd09368389153c20
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 680b83fb7896357e.270cd4a436a555c7.64f8a34d14e4f4f9.d1d7f6a8ac7de56c
+ 24988d65ddc640ef.594441aa10495667.ea972bafe46ca719.91c3180a7c034ec9
+ 0fba98b3e36c29c2.94ada1a9d330162d.3265777dc665d986.ac3aafaf6687d7f6
+ fd09368389153c20
+VDPPD_128_4of4(mem)
+ before
+ 62fc2a70ffba3b73.86bda14f25162ca2.b4156f8b9b685146.97ae8124575cc8ea
+ b6de0563e4818e1a.e6eca3a74050843c.9446273e85fdc2dd.77be471132dcaef1
+ d47d45485477f242.89959a26cfa46f3c.120d45adadf9261f.2de1c4aff372c848
+ 9aa3650c6da62316.cc0282386fa1274d.093645c42e6a3938.1562f46a37a9519b
+ 8a8ed4ad990d8695
+ after
+ 62fc2a70ffba3b73.86bda14f25162ca2.b4156f8b9b685146.97ae8124575cc8ea
+ b6de0563e4818e1a.e6eca3a74050843c.9446273e85fdc2dd.77be471132dcaef1
+ d47d45485477f242.89959a26cfa46f3c.120d45adadf9261f.2de1c4aff372c848
+ 9aa3650c6da62316.cc0282386fa1274d.093645c42e6a3938.1562f46a37a9519b
+ 8a8ed4ad990d8695
+
+VPINSRW_128_1of4(reg)
+ before
+ eab15ee6b62ba3e3.e21de199481cdcc3.0b805848bbd0e81b.548da46f245cb753
+ 901790802a8de431.8ab736dd03e5db74.a25b17c44fbff053.d1dedd9aacda5b9c
+ d70c65e88fc2842a.6c3ddec3ba0cd956.eedfbb18c8f979a1.5af46c31e2f0e241
+ 1ddbda888453c17b.667b5737889d9595.495740aec20abfb1.cd9ccd20e0aa086c
+ 04a37d54c5158849
+ after
+ 0000000000000000.0000000000000000.a25b17c44fbff053.d1dedd9aacda8849
+ 901790802a8de431.8ab736dd03e5db74.a25b17c44fbff053.d1dedd9aacda5b9c
+ d70c65e88fc2842a.6c3ddec3ba0cd956.eedfbb18c8f979a1.5af46c31e2f0e241
+ 1ddbda888453c17b.667b5737889d9595.495740aec20abfb1.cd9ccd20e0aa086c
+ 04a37d54c5158849
+VPINSRW_128_1of4(mem)
+ before
+ dcd3f6b7aa3c1f05.bcd2e9cda3ced4cf.523d1c258aa4c95c.1011a2f3d87f002e
+ 32f9b637ae2b89cc.123b902488befcd3.0e4eaa79db2e32d8.9f57de53a7e376c4
+ e0e038beeaef82c9.7963caf7cfb07332.747b7b1f97468c35.5277ef3bcac25e20
+ c356f93a7c93c529.4f9693b4162f7699.61910d03dbf9929e.85bbd116dda9f4ee
+ 946f804f7d2373da
+ after
+ dcd3f6b7aa3c1f05.bcd2e9cda3ced4cf.523d1c258aa4c95c.1011a2f3d87f002e
+ 32f9b637ae2b89cc.123b902488befcd3.0e4eaa79db2e32d8.9f57de53a7e376c4
+ 0000000000000000.0000000000000000.0e4eaa79db2e32d8.002ede53a7e376c4
+ c356f93a7c93c529.4f9693b4162f7699.61910d03dbf9929e.85bbd116dda9f4ee
+ 946f804f7d2373da
+
+VPINSRW_128_1of4(reg)
+ before
+ dbe1f95445bd188f.b825739680240f17.ee20e8c5f6c741b4.b259db11c251023f
+ b55c3790d2021fb9.991a24be11ad1cc0.b44dc3980d05102e.41a26136695d9646
+ 802b366fbf7ec305.4301879e4c3aa750.fb682298f7741eb4.eb371c5cec260add
+ 979bf25da9bd421f.92a618224cd86ef2.20be00314fa0a8f2.8ce3867165ba1b30
+ 01741d60f324866c
+ after
+ 0000000000000000.0000000000000000.b44dc3980d05102e.41a26136695d866c
+ b55c3790d2021fb9.991a24be11ad1cc0.b44dc3980d05102e.41a26136695d9646
+ 802b366fbf7ec305.4301879e4c3aa750.fb682298f7741eb4.eb371c5cec260add
+ 979bf25da9bd421f.92a618224cd86ef2.20be00314fa0a8f2.8ce3867165ba1b30
+ 01741d60f324866c
+VPINSRW_128_1of4(mem)
+ before
+ 24b45c14af7104bd.56f967c62b4cd6b2.63d554362d912bd3.809c59cfb216e993
+ d270bf7bb8ac544e.198e9216e2b6bb6b.905ab6c70c749a1e.754c2adeba611e43
+ e774c38027e1304c.3ba96eb969882ff6.f600b9bf058a7900.5c1b6ecb060d84b0
+ 3f8ce30f1a1c55e2.1a95f71c5d4d6cfe.7195dc0c33e182a5.9154210030a75483
+ 71453febd4bacd6b
+ after
+ 24b45c14af7104bd.56f967c62b4cd6b2.63d554362d912bd3.809c59cfb216e993
+ d270bf7bb8ac544e.198e9216e2b6bb6b.905ab6c70c749a1e.754c2adeba611e43
+ 0000000000000000.0000000000000000.905ab6c70c749a1e.e9932adeba611e43
+ 3f8ce30f1a1c55e2.1a95f71c5d4d6cfe.7195dc0c33e182a5.9154210030a75483
+ 71453febd4bacd6b
+
+VPINSRW_128_1of4(reg)
+ before
+ 5638c4f68fd22912.b6839b14ad6a7f3d.119d29a95991af30.dde39898b2847138
+ 9d7aad8ffc7ca524.2827677cfbd76989.7b0f00cefae03337.16b76a519f8004e6
+ a258f520b8437d4f.7142c331216dd0f1.b63579f6dbc735c0.f8dccf2215e0f5da
+ c11b98175eb4ec3c.6da12c203a3a70a2.1c5c8f8c98d2f176.5f2042f731b00141
+ 274e3fbc0efde447
+ after
+ 0000000000000000.0000000000000000.7b0f00cefae03337.16b76a519f80e447
+ 9d7aad8ffc7ca524.2827677cfbd76989.7b0f00cefae03337.16b76a519f8004e6
+ a258f520b8437d4f.7142c331216dd0f1.b63579f6dbc735c0.f8dccf2215e0f5da
+ c11b98175eb4ec3c.6da12c203a3a70a2.1c5c8f8c98d2f176.5f2042f731b00141
+ 274e3fbc0efde447
+VPINSRW_128_1of4(mem)
+ before
+ 2c31435dc9d25917.561292df8b592f9a.f8101d36624a04c7.0bd03efece8ba306
+ 4996c9c67d3b1dde.bd88dfe4dac08213.ee5b125eb6a74a8d.dddc82b71980871c
+ 5c494ce34745ecc7.52c87c92e8752053.2a4d8783525ffb1f.f0ce5823143cd863
+ 40164aa142fb81ff.7120645650034608.8ab4f893507ed6ab.9ef0bbaf5b4cd388
+ 4590a7c58b3bb337
+ after
+ 2c31435dc9d25917.561292df8b592f9a.f8101d36624a04c7.0bd03efece8ba306
+ 4996c9c67d3b1dde.bd88dfe4dac08213.ee5b125eb6a74a8d.dddc82b71980871c
+ 0000000000000000.0000000000000000.ee5b125eb6a74a8d.a30682b71980871c
+ 40164aa142fb81ff.7120645650034608.8ab4f893507ed6ab.9ef0bbaf5b4cd388
+ 4590a7c58b3bb337
+
+VPINSRW_128_2of4(reg)
+ before
+ 3ff818d23f95b61b.d1c93fea8b699ab2.76da939aaff630db.e95ae279cf0e965a
+ e9750b4314e716e1.ea2da5ac3d9cf10b.bc4305cba0da1a7b.230cc021e91df65b
+ a0527a82a5bc0f34.6910fad1749f4237.a1a7b756bf3c3f92.13960e77bab7b2d8
+ bedd63fd8fa0dfc1.293cb9474d7e4b61.8051a4a5a9a7ddcc.97c449675fe688fd
+ 8a62ebdef3b832f7
+ after
+ 0000000000000000.0000000000000000.bc4305cba0da1a7b.230c32f7e91df65b
+ e9750b4314e716e1.ea2da5ac3d9cf10b.bc4305cba0da1a7b.230cc021e91df65b
+ a0527a82a5bc0f34.6910fad1749f4237.a1a7b756bf3c3f92.13960e77bab7b2d8
+ bedd63fd8fa0dfc1.293cb9474d7e4b61.8051a4a5a9a7ddcc.97c449675fe688fd
+ 8a62ebdef3b832f7
+VPINSRW_128_2of4(mem)
+ before
+ c73b72c693396df2.a060c11f6d20c033.057e5ef9e446c6b6.b58fc826faa82dd6
+ 2c1d590c5a73f519.a2299153dcc7ef37.dba266d354027061.9cab1f444dca6e5c
+ 94d21c9d64758599.2182cd077721a779.86744bc1b9be048f.90f2a56b3e99da09
+ da273864cf48db9e.77b873a6dbbb26a4.e1c08baf3087406c.efb057076aa1ae8a
+ 143130846d6f268b
+ after
+ c73b72c693396df2.a060c11f6d20c033.057e5ef9e446c6b6.b58fc826faa82dd6
+ 2c1d590c5a73f519.a2299153dcc7ef37.dba266d354027061.9cab1f444dca6e5c
+ 0000000000000000.0000000000000000.dba266d354027061.2dd61f444dca6e5c
+ da273864cf48db9e.77b873a6dbbb26a4.e1c08baf3087406c.efb057076aa1ae8a
+ 143130846d6f268b
+
+VPINSRW_128_2of4(reg)
+ before
+ 5ac12c4ee18f7db7.dce8274cb4fab053.01177e9ca320a665.ca51a189d468de23
+ 1fac47d1658bf0bb.74e167433196c3e4.1beaea566bdc6467.1bf4093bc26e9ae1
+ bd3d7e7992f1bb42.7fdd73346228ce7f.217fb43ed17c9b57.b27640b215a432d2
+ 92c1ccb3074c1af9.daaac80b62bd8e4e.6f20d6c16e8b88e1.69a1c1d8ea166021
+ 1d42089b5cd0e1fa
+ after
+ 0000000000000000.0000000000000000.1beaea566bdc6467.1bf4e1fac26e9ae1
+ 1fac47d1658bf0bb.74e167433196c3e4.1beaea566bdc6467.1bf4093bc26e9ae1
+ bd3d7e7992f1bb42.7fdd73346228ce7f.217fb43ed17c9b57.b27640b215a432d2
+ 92c1ccb3074c1af9.daaac80b62bd8e4e.6f20d6c16e8b88e1.69a1c1d8ea166021
+ 1d42089b5cd0e1fa
+VPINSRW_128_2of4(mem)
+ before
+ ab2491e688df708b.f8842de95d29488b.5f12e0b44d60bf7d.611a4e4ce09667b0
+ ed15d8a4894ecbfe.4dd29d89331382a5.ebe2391c401e1c39.53b91749c2287471
+ c0df5ac37c2aac7f.ebf718fe229604f3.5be64e2d570263ae.a1492d26b1cdeacf
+ 014f912e7c7dcf3b.2f3f9bb4c83f0920.89ea9bd4ac184e07.a7168d4e49110677
+ c16c322d25810415
+ after
+ ab2491e688df708b.f8842de95d29488b.5f12e0b44d60bf7d.611a4e4ce09667b0
+ ed15d8a4894ecbfe.4dd29d89331382a5.ebe2391c401e1c39.53b91749c2287471
+ 0000000000000000.0000000000000000.ebe2391c401e1c39.67b01749c2287471
+ 014f912e7c7dcf3b.2f3f9bb4c83f0920.89ea9bd4ac184e07.a7168d4e49110677
+ c16c322d25810415
+
+VPINSRW_128_2of4(reg)
+ before
+ 4b96182fe1a82054.8a31fbd1a556f25e.76f52116c199ced9.52b99cfe5e6c9971
+ a0e13bc01a1395e0.3851149814becf13.1a67a692a8308fca.9221ce95870b0117
+ 1e99974c6b4ca067.e77b5670e5c32387.78df26941991889e.26ecac8743004326
+ 200a293f71e27d93.737b3f433370aae5.edaa9e86b147f401.e8e8b2bfaf5818ca
+ b5df5c29e61e3f2e
+ after
+ 0000000000000000.0000000000000000.1a67a692a8308fca.92213f2e870b0117
+ a0e13bc01a1395e0.3851149814becf13.1a67a692a8308fca.9221ce95870b0117
+ 1e99974c6b4ca067.e77b5670e5c32387.78df26941991889e.26ecac8743004326
+ 200a293f71e27d93.737b3f433370aae5.edaa9e86b147f401.e8e8b2bfaf5818ca
+ b5df5c29e61e3f2e
+VPINSRW_128_2of4(mem)
+ before
+ 699d27b1045e727f.0280ec05c75e6710.b81c4afe1ad21f5a.d31408d50cde10a1
+ e0f08e4327256ee8.1f47dc0b094e9b8b.922cf38eb7f43f12.876962edc5e31827
+ f6a30ccb687eef96.d5aaf5bbd53d55b0.dd75b6dd26e2c638.65f4a73b78e14842
+ 87812035e575b0b5.7ff63383c4b8d02a.75c410d982a96ff9.c902d429c264db9c
+ 10e0e3253ef90ee1
+ after
+ 699d27b1045e727f.0280ec05c75e6710.b81c4afe1ad21f5a.d31408d50cde10a1
+ e0f08e4327256ee8.1f47dc0b094e9b8b.922cf38eb7f43f12.876962edc5e31827
+ 0000000000000000.0000000000000000.922cf38eb7f43f12.10a162edc5e31827
+ 87812035e575b0b5.7ff63383c4b8d02a.75c410d982a96ff9.c902d429c264db9c
+ 10e0e3253ef90ee1
+
+VPINSRW_128_3of4(reg)
+ before
+ 94d8d29a892b1cbf.6f57436eba166e70.787893ce744a4aa6.36e47c6de754f880
+ b2379cf43e8743df.8af1f360026ee5f4.1e7a1007817ffdd0.fca3768572ef1bfa
+ c6483e9ffa97bdf0.b41baaf9d989d06c.cb49a69c86e32553.a3cc7a0d3e869493
+ 2c59b20758e9c69c.c9a1e7235c71ed05.dd3052f81f0300dc.072a04f168262176
+ 048a911d0bdb7cd0
+ after
+ 0000000000000000.0000000000000000.1e7a1007817f7cd0.fca3768572ef1bfa
+ b2379cf43e8743df.8af1f360026ee5f4.1e7a1007817ffdd0.fca3768572ef1bfa
+ c6483e9ffa97bdf0.b41baaf9d989d06c.cb49a69c86e32553.a3cc7a0d3e869493
+ 2c59b20758e9c69c.c9a1e7235c71ed05.dd3052f81f0300dc.072a04f168262176
+ 048a911d0bdb7cd0
+VPINSRW_128_3of4(mem)
+ before
+ 76b89c7d43af61cc.40b5f698f5099c8f.a54f23cca734f5eb.ae7d0e87e96bc816
+ 3980a1fe2eb08e97.5ea705be6c827977.23f0dbdfd5dea749.9c7ad8b580a5baae
+ 28ae1c8ae5eabd5c.e17cdbe55ae09afd.21528c480279be4c.0174abef7e3f114f
+ 210d8a0f8667ab49.2780747a5aaf3bd0.7a3fb1f34b13f51f.3ab7839f82c50ba6
+ a48f5d3226c1e25f
+ after
+ 76b89c7d43af61cc.40b5f698f5099c8f.a54f23cca734f5eb.ae7d0e87e96bc816
+ 3980a1fe2eb08e97.5ea705be6c827977.23f0dbdfd5dea749.9c7ad8b580a5baae
+ 0000000000000000.0000000000000000.23f0dbdfc816a749.9c7ad8b580a5baae
+ 210d8a0f8667ab49.2780747a5aaf3bd0.7a3fb1f34b13f51f.3ab7839f82c50ba6
+ a48f5d3226c1e25f
+
+VPINSRW_128_3of4(reg)
+ before
+ 9948331506c1d325.ff6b65772d361487.8bffcde7087c979a.0a84c6cccbb808ef
+ 762e03b3bf5119a5.9d922bb0f560b345.6945e09a01d2eb07.aced47bf9f72b5e7
+ 978cc877ecfbf18b.d94f58a5faf345ac.1d9dabfde13e73c4.3e45b1b8e24fb634
+ 59af7fcf294d9782.8e6e664259fa86eb.02542a7e434b6b7d.9a5a7fa4b15bc802
+ 9ef62d6d27a1a77c
+ after
+ 0000000000000000.0000000000000000.6945e09a01d2a77c.aced47bf9f72b5e7
+ 762e03b3bf5119a5.9d922bb0f560b345.6945e09a01d2eb07.aced47bf9f72b5e7
+ 978cc877ecfbf18b.d94f58a5faf345ac.1d9dabfde13e73c4.3e45b1b8e24fb634
+ 59af7fcf294d9782.8e6e664259fa86eb.02542a7e434b6b7d.9a5a7fa4b15bc802
+ 9ef62d6d27a1a77c
+VPINSRW_128_3of4(mem)
+ before
+ 25e63701612d0ecf.16e4222614d34736.97bbd3732e81322c.76b75788c3850edd
+ 0af6194a7a0bbb27.2b75afe846173c54.d20219249495049c.d4103087fe789991
+ 2bf250368e4867af.f4ae21815da7b388.190eb641a741b966.77acb0e78fb14845
+ 62a657b0baefd194.cddd745df50fe87e.4aad26b684910db7.bdd6d31413bb56a4
+ 01dc957a2623005b
+ after
+ 25e63701612d0ecf.16e4222614d34736.97bbd3732e81322c.76b75788c3850edd
+ 0af6194a7a0bbb27.2b75afe846173c54.d20219249495049c.d4103087fe789991
+ 0000000000000000.0000000000000000.d20219240edd049c.d4103087fe789991
+ 62a657b0baefd194.cddd745df50fe87e.4aad26b684910db7.bdd6d31413bb56a4
+ 01dc957a2623005b
+
+VPINSRW_128_3of4(reg)
+ before
+ 9e08f38662748215.8cdeaaa41a0cb301.124da5e9a9da16e1.3fa9e3704692bbba
+ f2a8e7a2663a187f.8665c5fec9acca23.1f49ae8f15947b5d.d6cf6b590a4f809c
+ 57066f3ccb02fd44.2a0825aae3dad225.501e8dbdd6c9509f.e9eb395febd51889
+ 2a6f86be2f576e11.5694459485a38634.01183ddd8806d453.55c8c96d062f3fac
+ f734976e7669b032
+ after
+ 0000000000000000.0000000000000000.1f49ae8f1594b032.d6cf6b590a4f809c
+ f2a8e7a2663a187f.8665c5fec9acca23.1f49ae8f15947b5d.d6cf6b590a4f809c
+ 57066f3ccb02fd44.2a0825aae3dad225.501e8dbdd6c9509f.e9eb395febd51889
+ 2a6f86be2f576e11.5694459485a38634.01183ddd8806d453.55c8c96d062f3fac
+ f734976e7669b032
+VPINSRW_128_3of4(mem)
+ before
+ a9f92050578f2847.c82f29962ec5a792.e4d3a1a9cb12a47c.8e83bb5dc6d64125
+ 48e4dffec7ae6316.8b91532f63d9e372.b191b5d3d033e628.53ab01a82cc5d5bf
+ b0c25064dfd11ccb.d1e3fff56b1e5f5e.999cfdffb0120865.acdb0d295760c9d0
+ be5cef6ebd051194.f46f2b54e1205702.79bef61a88bcc75e.f561da4ee2325c02
+ 8a8764826ac8c802
+ after
+ a9f92050578f2847.c82f29962ec5a792.e4d3a1a9cb12a47c.8e83bb5dc6d64125
+ 48e4dffec7ae6316.8b91532f63d9e372.b191b5d3d033e628.53ab01a82cc5d5bf
+ 0000000000000000.0000000000000000.b191b5d34125e628.53ab01a82cc5d5bf
+ be5cef6ebd051194.f46f2b54e1205702.79bef61a88bcc75e.f561da4ee2325c02
+ 8a8764826ac8c802
+
+VPINSRW_128_4of4(reg)
+ before
+ c69aa7328aad4a7b.4c8139097d55fc9a.5182d3b8616c0709.2bc51b0f733ddf40
+ 07e6a0c8df6d1e1a.37fca81f3acd990c.4568f18d888daa1f.8c7be8ca8e9f0c37
+ a8b74ab104957f8b.5b98ba9d107aa614.2a6d833ff20f7df2.78add936f4f00a6e
+ 0558a15a96afaa79.9423ea701c66ddde.5ddd843b3a7fbc2b.cb276b41c23b9412
+ 61b518d6138d674e
+ after
+ 0000000000000000.0000000000000000.4568674e888daa1f.8c7be8ca8e9f0c37
+ 07e6a0c8df6d1e1a.37fca81f3acd990c.4568f18d888daa1f.8c7be8ca8e9f0c37
+ a8b74ab104957f8b.5b98ba9d107aa614.2a6d833ff20f7df2.78add936f4f00a6e
+ 0558a15a96afaa79.9423ea701c66ddde.5ddd843b3a7fbc2b.cb276b41c23b9412
+ 61b518d6138d674e
+VPINSRW_128_4of4(mem)
+ before
+ 16225ee203f13f4f.7917a12d304adb91.be67b58279a0fa98.3a03f0ebfc68a279
+ c63cb94faf73d741.623e47986fef4e7e.b53195c14431bb6b.1d2dc3bdd5566c86
+ 4dcda30a3320ec4f.1a1a8d05ee2c3eed.554d08189927da86.62a5fa1b60d656fe
+ 87a29a00aa033aa6.fff771e2498ce889.7a868973928e1413.65b890733a739c8f
+ 82b28130feb979e2
+ after
+ 16225ee203f13f4f.7917a12d304adb91.be67b58279a0fa98.3a03f0ebfc68a279
+ c63cb94faf73d741.623e47986fef4e7e.b53195c14431bb6b.1d2dc3bdd5566c86
+ 0000000000000000.0000000000000000.a27995c14431bb6b.1d2dc3bdd5566c86
+ 87a29a00aa033aa6.fff771e2498ce889.7a868973928e1413.65b890733a739c8f
+ 82b28130feb979e2
+
+VPINSRW_128_4of4(reg)
+ before
+ 15dfc9be49352aa6.5087181b31287c71.6b21ee9a1d9c88ff.00aa94be4e70253e
+ 7a8a6589b672eb85.84489b49e29b6fdd.bce4019906e759fb.c383a6e5e6dbc834
+ 0d014ffde2fdf82b.ffb09f75dc69cf16.4c8ca44b9ff99828.9fde39d478daba21
+ 2a8e858668618c46.9c8d9e8a399e5847.7964d51c845f8133.6f87cb77207ab731
+ 114ad7bbf9c67a8f
+ after
+ 0000000000000000.0000000000000000.bce47a8f06e759fb.c383a6e5e6dbc834
+ 7a8a6589b672eb85.84489b49e29b6fdd.bce4019906e759fb.c383a6e5e6dbc834
+ 0d014ffde2fdf82b.ffb09f75dc69cf16.4c8ca44b9ff99828.9fde39d478daba21
+ 2a8e858668618c46.9c8d9e8a399e5847.7964d51c845f8133.6f87cb77207ab731
+ 114ad7bbf9c67a8f
+VPINSRW_128_4of4(mem)
+ before
+ 60f3da8a20cac167.2d7e0291e52ae47f.39a916761544c69d.9db98f7952a450c8
+ 384e4ed2b09346e6.721dc388f4e43c85.b1d182248d6ad443.16d7cecca4544092
+ 7426b17dc52cc538.55b7c2d8311ccf02.e0d15e80bc193e66.3e0a8f8217fc8e3d
+ f2487e797da2fc88.3298fdee395ddaa2.a1752677bf5fc232.729ecc0846277677
+ 0fde83c9ce6133ea
+ after
+ 60f3da8a20cac167.2d7e0291e52ae47f.39a916761544c69d.9db98f7952a450c8
+ 384e4ed2b09346e6.721dc388f4e43c85.b1d182248d6ad443.16d7cecca4544092
+ 0000000000000000.0000000000000000.50c882248d6ad443.16d7cecca4544092
+ f2487e797da2fc88.3298fdee395ddaa2.a1752677bf5fc232.729ecc0846277677
+ 0fde83c9ce6133ea
+
+VPINSRW_128_4of4(reg)
+ before
+ 6f18af304a370242.8d8031b1f1ffa503.640b6f35a8349912.d28957f3b1471ad2
+ ef964dab57341f2c.209a46113f517dd5.495e1419192c47fe.4ed86ce1afdd0372
+ eba557a590e4c654.89623a8582a43f29.3cdbe90528d12211.f030e12ed42e3940
+ bf91cb8a92d43265.a2a488f9d703a92b.99cfe86772af64f8.965b32c43d457766
+ 1a26db91052e7b10
+ after
+ 0000000000000000.0000000000000000.495e7b10192c47fe.4ed86ce1afdd0372
+ ef964dab57341f2c.209a46113f517dd5.495e1419192c47fe.4ed86ce1afdd0372
+ eba557a590e4c654.89623a8582a43f29.3cdbe90528d12211.f030e12ed42e3940
+ bf91cb8a92d43265.a2a488f9d703a92b.99cfe86772af64f8.965b32c43d457766
+ 1a26db91052e7b10
+VPINSRW_128_4of4(mem)
+ before
+ 5a5d598049f6fe6b.c7a6a4c6f88fa00c.492bac595a7a7509.bb860faa9253495f
+ 30cc277c24a8bfa3.6030dec55ea14cf4.58c5229225155fed.004c593b25480ff1
+ 7a3ec173b25178e3.e47a76f4619772ca.ad3c678e57e12503.c26cc384c71bf05b
+ 1281a35010fbe658.b0d266bd9dfc4d3a.225df53a09e98178.5f3447f212572948
+ 31eee3f2a588f565
+ after
+ 5a5d598049f6fe6b.c7a6a4c6f88fa00c.492bac595a7a7509.bb860faa9253495f
+ 30cc277c24a8bfa3.6030dec55ea14cf4.58c5229225155fed.004c593b25480ff1
+ 0000000000000000.0000000000000000.495f229225155fed.004c593b25480ff1
+ 1281a35010fbe658.b0d266bd9dfc4d3a.225df53a09e98178.5f3447f212572948
+ 31eee3f2a588f565
+
+VBROADCASTSS_256(reg)
+ before
+ 96e792ee193b925d.d55f4a005ab5c52d.2082ac8dad5d1aef.94f44a835a393078
+ e86b50540cfb3add.a0a5316daa88d08f.90d743d12d441496.e0cce15463deed2e
+ 85c61a8e1a542991.4d1fd4841f82c5aa.5c1d28f4ba3f79da.e0b3379843e376c7
+ c743ea0aded39d24.b999af32d3ae5ea9.dfa05561f0da8368.7173c63d1355856e
+ 70d90c2ef13fd650
+ after
+ 96e792ee193b925d.d55f4a005ab5c52d.2082ac8dad5d1aef.94f44a835a393078
+ e86b50540cfb3add.a0a5316daa88d08f.90d743d12d441496.e0cce15463deed2e
+ 85c61a8e1a542991.4d1fd4841f82c5aa.5c1d28f4ba3f79da.e0b3379843e376c7
+ c743ea0aded39d24.b999af32d3ae5ea9.dfa05561f0da8368.7173c63d1355856e
+ 70d90c2ef13fd650
+VBROADCASTSS_256(mem)
+ before
+ b7b28457f9ad2799.0b30be33f503d043.c0df3e61e21957b9.77abc88669a06fec
+ 23c7aaa446ac3274.aed79175fa70ff9a.3fbcfeff69cd6d06.7f8b7ccec41d7811
+ 90e7fb02f446b40e.0a855f3c89a765d4.10fd6af683d95cbb.538d6da59adddb83
+ daddf25b208a6993.7c8625f43f33409d.106ffe344d46e004.4ffb97778a6dd4f0
+ ce22f7b12d589f02
+ after
+ b7b28457f9ad2799.0b30be33f503d043.c0df3e61e21957b9.77abc88669a06fec
+ 69a06fec69a06fec.69a06fec69a06fec.69a06fec69a06fec.69a06fec69a06fec
+ 90e7fb02f446b40e.0a855f3c89a765d4.10fd6af683d95cbb.538d6da59adddb83
+ daddf25b208a6993.7c8625f43f33409d.106ffe344d46e004.4ffb97778a6dd4f0
+ ce22f7b12d589f02
+
+VBROADCASTSS_256(reg)
+ before
+ 2e4e88bd222b7765.dd740b9ce6810c2e.6126de0ab8a0caa3.1bdc36a4e222b50e
+ caca460802719ac6.767ac2b261395a0b.13b185e88f7b408f.0d108f325f789605
+ fde42dff6bb641d1.7fb99388adbd0f57.ef7319fc604fdd10.c2d983cadf554015
+ 25e63a0df987ab31.d5fefb09e71ae63e.51b793b0c8a8ded0.160290587fc46f69
+ e55631c85ad1de2d
+ after
+ 2e4e88bd222b7765.dd740b9ce6810c2e.6126de0ab8a0caa3.1bdc36a4e222b50e
+ caca460802719ac6.767ac2b261395a0b.13b185e88f7b408f.0d108f325f789605
+ fde42dff6bb641d1.7fb99388adbd0f57.ef7319fc604fdd10.c2d983cadf554015
+ 25e63a0df987ab31.d5fefb09e71ae63e.51b793b0c8a8ded0.160290587fc46f69
+ e55631c85ad1de2d
+VBROADCASTSS_256(mem)
+ before
+ 0ba2e3078c894a8e.9d1d679d476e1293.541574232a5b9deb.95caf17262137f7b
+ 64b220ff32f76fb8.c0d5b21df2fab3a3.d7c97cc1938ced8b.17f82daccb1bfcbf
+ cc52669e682708d7.ec5a16f895b4ca0c.3ce88fcf3dba954a.338d45cc9e4c9045
+ 1f4e30ce4926d216.7bf8909acc2a927b.5e3c273945f05053.45d5353d783378bc
+ a91cf76bf45bf0ce
+ after
+ 0ba2e3078c894a8e.9d1d679d476e1293.541574232a5b9deb.95caf17262137f7b
+ 62137f7b62137f7b.62137f7b62137f7b.62137f7b62137f7b.62137f7b62137f7b
+ cc52669e682708d7.ec5a16f895b4ca0c.3ce88fcf3dba954a.338d45cc9e4c9045
+ 1f4e30ce4926d216.7bf8909acc2a927b.5e3c273945f05053.45d5353d783378bc
+ a91cf76bf45bf0ce
+
+VBROADCASTSS_256(reg)
+ before
+ bbad89c2af513327.3972fb7df1ff89a1.cbfa1a6f34e7489b.1992c2ebc63ad9d3
+ d7d5e6af449f7f74.f58941967dbee9a5.36aeb2e368782819.49b6dad1dda5ecf5
+ 59e10a9c50d40e61.316180050870ae4e.1a5e536205686ea0.ca74eed8a53c47e6
+ 9d1bf1f66e791c9a.c8c433b6af2093c7.d157f959a74355dd.779877ea3b0ba4d2
+ 2eeef2f5ba1fc0e4
+ after
+ bbad89c2af513327.3972fb7df1ff89a1.cbfa1a6f34e7489b.1992c2ebc63ad9d3
+ d7d5e6af449f7f74.f58941967dbee9a5.36aeb2e368782819.49b6dad1dda5ecf5
+ 59e10a9c50d40e61.316180050870ae4e.1a5e536205686ea0.ca74eed8a53c47e6
+ 9d1bf1f66e791c9a.c8c433b6af2093c7.d157f959a74355dd.779877ea3b0ba4d2
+ 2eeef2f5ba1fc0e4
+VBROADCASTSS_256(mem)
+ before
+ ca41dce43e835749.ffcf982a3a1ce7ca.967fd6958dda543d.b8e5a132e8961a7c
+ 275eb0a2e443242c.da4bfaa25148a99d.765ee58ebfabafdc.2c54465b67ecf928
+ 2011ea1dc86ce4ba.8cda13cc4f8a9fc0.462cdd8d609e5ecf.87efe33ebdd12d8e
+ 932607400509531e.70c7df13cf6c04df.e1b7387f8dbf1e43.2604774989d2f459
+ 65ddfbe7647a8836
+ after
+ ca41dce43e835749.ffcf982a3a1ce7ca.967fd6958dda543d.b8e5a132e8961a7c
+ e8961a7ce8961a7c.e8961a7ce8961a7c.e8961a7ce8961a7c.e8961a7ce8961a7c
+ 2011ea1dc86ce4ba.8cda13cc4f8a9fc0.462cdd8d609e5ecf.87efe33ebdd12d8e
+ 932607400509531e.70c7df13cf6c04df.e1b7387f8dbf1e43.2604774989d2f459
+ 65ddfbe7647a8836
+
+VPALIGNR_128_1of3(reg)
+ before
+ a0c76c84ec5525d1.5a6981f7b7262d85.e25f5ae36d7d15a5.22c9744e611bab63
+ 340ec78cbdf008d5.53a6d62efbd02d1b.3dee81a8c6460ebf.e72f0de8f9bdc05c
+ 7bfe076b72d66eef.58a881d1ec12100b.dfc04fce75552bd9.0ab67d3770b11a59
+ d2e3288da89490cb.473dfecda7f99282.2321c0c11735a79e.69274229e3047587
+ de51d7a96dc18d12
+ after
+ 0000000000000000.0000000000000000.dfc04fce75552bd9.0ab67d3770b11a59
+ 340ec78cbdf008d5.53a6d62efbd02d1b.3dee81a8c6460ebf.e72f0de8f9bdc05c
+ 7bfe076b72d66eef.58a881d1ec12100b.dfc04fce75552bd9.0ab67d3770b11a59
+ d2e3288da89490cb.473dfecda7f99282.2321c0c11735a79e.69274229e3047587
+ de51d7a96dc18d12
+VPALIGNR_128_1of3(mem)
+ before
+ 47ffb8a32af51d25.9508275efab4ad14.fa2fca0c478f6eac.645cd0ed4773c0bb
+ 7efc610337abe2ed.20baff4b04c4ff76.4f4b607ce9e361b4.00bf7cbea29aafdb
+ 60154fb5b0ef9896.cf46abbe6350c39e.205d3c07a8fe27c7.5194bfa1c336b3ab
+ ca17fca5b0cdfa4b.fef62925b3e33538.4a30da9ba1ee7c10.b528950047d406d6
+ 86c7fa49c9ffe509
+ after
+ 47ffb8a32af51d25.9508275efab4ad14.fa2fca0c478f6eac.645cd0ed4773c0bb
+ 7efc610337abe2ed.20baff4b04c4ff76.4f4b607ce9e361b4.00bf7cbea29aafdb
+ 0000000000000000.0000000000000000.9aafdbfa2fca0c47.8f6eac645cd0ed47
+ ca17fca5b0cdfa4b.fef62925b3e33538.4a30da9ba1ee7c10.b528950047d406d6
+ 86c7fa49c9ffe509
+
+VPALIGNR_128_1of3(reg)
+ before
+ 22bdeae7e6438cf0.96cce6c05352c638.091775eb8f0990ef.aa92b623efbe1bbc
+ e3566246392d3636.a10089f0b689b58b.4cf4897b934e1170.1a4d4d8aaf7bc1f6
+ 26dd5dd15f482188.c7815f23f47f866d.23db63435c3ff467.772e1abefc2f2aeb
+ 48a0d7f6f3208792.e51ae6432a3ff30d.e916feae8567747f.9d0299aaf2e911c7
+ 6992463bafb234b5
+ after
+ 0000000000000000.0000000000000000.23db63435c3ff467.772e1abefc2f2aeb
+ e3566246392d3636.a10089f0b689b58b.4cf4897b934e1170.1a4d4d8aaf7bc1f6
+ 26dd5dd15f482188.c7815f23f47f866d.23db63435c3ff467.772e1abefc2f2aeb
+ 48a0d7f6f3208792.e51ae6432a3ff30d.e916feae8567747f.9d0299aaf2e911c7
+ 6992463bafb234b5
+VPALIGNR_128_1of3(mem)
+ before
+ b5ad9d5b4c984de2.a3e9cc219141a4ff.d596993e73d5b995.fcf35628ab53cf65
+ 5e1e1bf7e7a61879.940538bcd639b57b.74c2f4ffec4d9431.b7bc681d698e3fc4
+ 40b03bfc9be952a7.774018345e91f6b3.9e6a7372b0b4400f.76be2ef95ca40049
+ 37317954856cb898.a9e567f5c4d7a353.2f5a9283dc157858.9444a6291f2150a0
+ 6f9ccb174f926974
+ after
+ b5ad9d5b4c984de2.a3e9cc219141a4ff.d596993e73d5b995.fcf35628ab53cf65
+ 5e1e1bf7e7a61879.940538bcd639b57b.74c2f4ffec4d9431.b7bc681d698e3fc4
+ 0000000000000000.0000000000000000.8e3fc4d596993e73.d5b995fcf35628ab
+ 37317954856cb898.a9e567f5c4d7a353.2f5a9283dc157858.9444a6291f2150a0
+ 6f9ccb174f926974
+
+VPALIGNR_128_1of3(reg)
+ before
+ 6210993187828872.1f6b51edc13b0377.8442216ca496f807.035ece1e8b7df93b
+ c8ee0de1637ee845.d42b40b16a63f271.65a143039b5a307a.f641a22fdaf77ee2
+ ff8022958011c69a.323dc18e9cef3fb1.a850c72844b08858.e4d18aa2e48fc579
+ 6213d3b87ac75e1c.156c506f74eba764.a999ab463c233b4f.a9d80363c552882e
+ 2123875f9a4b842a
+ after
+ 0000000000000000.0000000000000000.a850c72844b08858.e4d18aa2e48fc579
+ c8ee0de1637ee845.d42b40b16a63f271.65a143039b5a307a.f641a22fdaf77ee2
+ ff8022958011c69a.323dc18e9cef3fb1.a850c72844b08858.e4d18aa2e48fc579
+ 6213d3b87ac75e1c.156c506f74eba764.a999ab463c233b4f.a9d80363c552882e
+ 2123875f9a4b842a
+VPALIGNR_128_1of3(mem)
+ before
+ 287e94807f86749c.4cf31fb6ec2dec78.598669400d63e6b6.c4c9eac91e3f8708
+ 9ab5a5b48f1015ae.1b6cfffb72ceac5a.da5588ed8464b7d2.552b801d8791a632
+ 539336e6e6f4238c.29c971f3a936d96d.74a62a62f4fad7e5.b80d6aae12a4d577
+ 2ee6c402a13e5a63.d3576f0a2df2b05e.0245ca8c7a2f021a.49b9a3e85c054f83
+ 647d2637003e5103
+ after
+ 287e94807f86749c.4cf31fb6ec2dec78.598669400d63e6b6.c4c9eac91e3f8708
+ 9ab5a5b48f1015ae.1b6cfffb72ceac5a.da5588ed8464b7d2.552b801d8791a632
+ 0000000000000000.0000000000000000.91a632598669400d.63e6b6c4c9eac91e
+ 2ee6c402a13e5a63.d3576f0a2df2b05e.0245ca8c7a2f021a.49b9a3e85c054f83
+ 647d2637003e5103
+
+VPALIGNR_128_2of3(reg)
+ before
+ 65a3f2079bdd17a3.0978caf3dcfb755f.7663f7ac998c6cd9.62fee4553111f39e
+ a87800c5c86edd0f.bf16c3a7b13632ab.6c37054689934a89.6f9df4aa35ac689d
+ 88484ddb237cdef2.2c8c2e0a3ffb4a74.132093429a90861a.05ee7778a30a1b42
+ 635ed6b7499358f8.2ba684069f577ce6.c5699f0e67115c3a.ffbce8aa9739c8b9
+ 3bd4c22b2c452d30
+ after
+ 0000000000000000.0000000000000000.f4aa35ac689d1320.93429a90861a05ee
+ a87800c5c86edd0f.bf16c3a7b13632ab.6c37054689934a89.6f9df4aa35ac689d
+ 88484ddb237cdef2.2c8c2e0a3ffb4a74.132093429a90861a.05ee7778a30a1b42
+ 635ed6b7499358f8.2ba684069f577ce6.c5699f0e67115c3a.ffbce8aa9739c8b9
+ 3bd4c22b2c452d30
+VPALIGNR_128_2of3(mem)
+ before
+ 940284e97e3904d1.940896c3d63f84ce.9a304388f055822c.df6024148da20892
+ e512a7cfaa210ac8.7790896d650da120.54f5e57c4b011973.bd4f1ec2a7cdc5d1
+ 0cd0a9c9cc09fa42.6743ac209289e999.34c3e8cfcf68fde6.bc8489835220d0a1
+ e30805c3fffe926b.c26efa48fa3d99e6.1864c86b9595e9b2.364962c3292764af
+ 88eba3eec96dbfa6
+ after
+ 940284e97e3904d1.940896c3d63f84ce.9a304388f055822c.df6024148da20892
+ e512a7cfaa210ac8.7790896d650da120.54f5e57c4b011973.bd4f1ec2a7cdc5d1
+ 0000000000000000.0000000000000000.73bd4f1ec2a7cdc5.d19a304388f05582
+ e30805c3fffe926b.c26efa48fa3d99e6.1864c86b9595e9b2.364962c3292764af
+ 88eba3eec96dbfa6
+
+VPALIGNR_128_2of3(reg)
+ before
+ 0eb64a70cd7e1b33.488537a95f0b8c6e.e35a6e5138b7edb3.daa5ff3ebb959a02
+ 24f553b5d1e6b501.1515bb68093ca478.255607a7e98220ab.58520b335d72cc04
+ 26f6b8297232c8bd.28820dea189e98b5.e6adbeb6a82b6f7b.6c376736963a3be1
+ 700377394ced9113.5b99aa1da93c2250.80aa90eb123d16ce.f41f8f3382f9a2c7
+ cad8ff163ebabee2
+ after
+ 0000000000000000.0000000000000000.0b335d72cc04e6ad.beb6a82b6f7b6c37
+ 24f553b5d1e6b501.1515bb68093ca478.255607a7e98220ab.58520b335d72cc04
+ 26f6b8297232c8bd.28820dea189e98b5.e6adbeb6a82b6f7b.6c376736963a3be1
+ 700377394ced9113.5b99aa1da93c2250.80aa90eb123d16ce.f41f8f3382f9a2c7
+ cad8ff163ebabee2
+VPALIGNR_128_2of3(mem)
+ before
+ cb2c34cbe6894b5e.5e698a4ffaa34cae.8c260debd723ff75.519a7ab0c2445151
+ d4e8a83e95720466.4c74f0d918e1353b.95f4b242bf5eea52.b3ca777355cd5baf
+ bfd8d95b6782a727.9670a24143328765.53d1160d7cf9a110.0484839e66627195
+ 69c8420f79c4edcc.98a99df516237fd9.a387b3372a00dede.9e149b9f9292cfaf
+ dfc8b9e174e6b0a8
+ after
+ cb2c34cbe6894b5e.5e698a4ffaa34cae.8c260debd723ff75.519a7ab0c2445151
+ d4e8a83e95720466.4c74f0d918e1353b.95f4b242bf5eea52.b3ca777355cd5baf
+ 0000000000000000.0000000000000000.52b3ca777355cd5b.af8c260debd723ff
+ 69c8420f79c4edcc.98a99df516237fd9.a387b3372a00dede.9e149b9f9292cfaf
+ dfc8b9e174e6b0a8
+
+VPALIGNR_128_2of3(reg)
+ before
+ 21eadbd0a9ec512d.af846044e6459582.ae6bde602e3e5942.5fe407aee7805de6
+ c1c8fcd8cc30eeea.6bd7aee8cb105974.340160ee2712514e.64b28d5dcc84dc54
+ 1cac1965793cc38a.7a8ea7e54431f6cf.86b81f0b9b28a2a6.8ebec131f7191556
+ 8ce32ce34d9e0bb9.b876c9296bb428bf.ffdc1823290e89f9.b9d32014844ac516
+ c1bf24f38e23a8c0
+ after
+ 0000000000000000.0000000000000000.8d5dcc84dc5486b8.1f0b9b28a2a68ebe
+ c1c8fcd8cc30eeea.6bd7aee8cb105974.340160ee2712514e.64b28d5dcc84dc54
+ 1cac1965793cc38a.7a8ea7e54431f6cf.86b81f0b9b28a2a6.8ebec131f7191556
+ 8ce32ce34d9e0bb9.b876c9296bb428bf.ffdc1823290e89f9.b9d32014844ac516
+ c1bf24f38e23a8c0
+VPALIGNR_128_2of3(mem)
+ before
+ 834c4bbb31b07981.6eb933bee4e20324.0159909f5ea6ab6f.fdb945a26a4f42f1
+ d94810568afef585.1e7a2963d992e777.3104763339133a0c.db9ba4f5fc78083a
+ a07df0b2b419d8f7.f9710a3cc83df25e.2442f9d1170592c1.f4ce30867b141881
+ b4b865b9cc0bdd04.59ecd2b74e6c6284.b6e19465158a6ebb.a69de5c382afae72
+ 4c56c016aed505b8
+ after
+ 834c4bbb31b07981.6eb933bee4e20324.0159909f5ea6ab6f.fdb945a26a4f42f1
+ d94810568afef585.1e7a2963d992e777.3104763339133a0c.db9ba4f5fc78083a
+ 0000000000000000.0000000000000000.0cdb9ba4f5fc7808.3a0159909f5ea6ab
+ b4b865b9cc0bdd04.59ecd2b74e6c6284.b6e19465158a6ebb.a69de5c382afae72
+ 4c56c016aed505b8
+
+VPALIGNR_128_3of3(reg)
+ before
+ 4143bced9a135b00.f1c5ed59eee2c2d7.9b357e3e06ad7195.c3abc3dc4ead8c26
+ e3b1d5b3e2f4eaf6.336f037d34a9409d.1b99093f8d8b5b3f.276d0320df7ba62d
+ 8cec07d42305ee45.55842311bd6d1681.35646f257e925e2b.bef4ce1ee3ff79fd
+ 9a3f4ebcf9d1a599.35ceca01a239ffb1.45e2ac5c764fb408.6409a2c37645c0c1
+ f57bfafab55a38a6
+ after
+ 0000000000000000.0000000000000000.8d8b5b3f276d0320.df7ba62d35646f25
+ e3b1d5b3e2f4eaf6.336f037d34a9409d.1b99093f8d8b5b3f.276d0320df7ba62d
+ 8cec07d42305ee45.55842311bd6d1681.35646f257e925e2b.bef4ce1ee3ff79fd
+ 9a3f4ebcf9d1a599.35ceca01a239ffb1.45e2ac5c764fb408.6409a2c37645c0c1
+ f57bfafab55a38a6
+VPALIGNR_128_3of3(mem)
+ before
+ 4d1552aebb499dd7.67f8a7d7ffe449a0.ae1a72390219b656.a75ebc50104d9980
+ 48a227cda51eab82.51610c91d1cb1704.9c3499a6f61af79f.b7269c6de9184b3f
+ c1f0f3428fe61dd0.b2c77b560c114a71.dbe8ba329c4780b6.d184471f9c3d04f2
+ 96c934f994acb1f0.e877f0924b422094.470252ca10ac0bc7.51c5b9d3c5470145
+ 9235eff302c37ee4
+ after
+ 4d1552aebb499dd7.67f8a7d7ffe449a0.ae1a72390219b656.a75ebc50104d9980
+ 48a227cda51eab82.51610c91d1cb1704.9c3499a6f61af79f.b7269c6de9184b3f
+ 0000000000000000.0000000000000000.3499a6f61af79fb7.269c6de9184b3fae
+ 96c934f994acb1f0.e877f0924b422094.470252ca10ac0bc7.51c5b9d3c5470145
+ 9235eff302c37ee4
+
+VPALIGNR_128_3of3(reg)
+ before
+ f220e3ecec3cb679.a2fa65ded07c200c.4dba65b22bebd319.bb4edb5b6d5655ff
+ ccd2932b213ee6b3.c04f03dd60632950.3edfd82048979fab.1597d3d0d0501a8a
+ 7c96fa1b3d554a3c.ce9388e35f6c86e9.1731444a3cd2c2f7.30aab51454a71593
+ 5eba1428db0e1ec1.a79472daeaa3f403.35fba59ba62976a8.e753fd1515650347
+ 185e27be3098a0d2
+ after
+ 0000000000000000.0000000000000000.48979fab1597d3d0.d0501a8a1731444a
+ ccd2932b213ee6b3.c04f03dd60632950.3edfd82048979fab.1597d3d0d0501a8a
+ 7c96fa1b3d554a3c.ce9388e35f6c86e9.1731444a3cd2c2f7.30aab51454a71593
+ 5eba1428db0e1ec1.a79472daeaa3f403.35fba59ba62976a8.e753fd1515650347
+ 185e27be3098a0d2
+VPALIGNR_128_3of3(mem)
+ before
+ 9d97b0fbc04ca85f.cd88debd97f49ded.261c3caf1c152fc9.f28bf77f1f27f86b
+ 54ca13b8e28bd61b.274d52480e94046d.29f8624f11cdf268.ab2b3761455884ec
+ 17c2cce2b264e731.c7556e34db798fed.8af561a5e6d8fa0c.bc285fafb44955d6
+ c44d57634ae097ce.08eb2dee9b2f7918.27dcb49cb74003e0.81cd6dd50785a8d6
+ 56685d3ddb98b997
+ after
+ 9d97b0fbc04ca85f.cd88debd97f49ded.261c3caf1c152fc9.f28bf77f1f27f86b
+ 54ca13b8e28bd61b.274d52480e94046d.29f8624f11cdf268.ab2b3761455884ec
+ 0000000000000000.0000000000000000.f8624f11cdf268ab.2b3761455884ec26
+ c44d57634ae097ce.08eb2dee9b2f7918.27dcb49cb74003e0.81cd6dd50785a8d6
+ 56685d3ddb98b997
+
+VPALIGNR_128_3of3(reg)
+ before
+ 98442954cb0fc3c6.35353128c90da11d.485d8be0e943ff9a.da7cd6229f14c910
+ a1accf867375040f.4847d41e48f6c24b.e1f5857762405d21.81a04622bb5d07ca
+ ceed4a407057b51d.d74fbe2fe6a7b684.31011620a1b2cf57.f6137d8826297a38
+ 7a5396ed5e3f159d.bf186b49bc2d39f3.92cb3a45432590e8.16a3f840fc83de86
+ be1a34375a77eee1
+ after
+ 0000000000000000.0000000000000000.62405d2181a04622.bb5d07ca31011620
+ a1accf867375040f.4847d41e48f6c24b.e1f5857762405d21.81a04622bb5d07ca
+ ceed4a407057b51d.d74fbe2fe6a7b684.31011620a1b2cf57.f6137d8826297a38
+ 7a5396ed5e3f159d.bf186b49bc2d39f3.92cb3a45432590e8.16a3f840fc83de86
+ be1a34375a77eee1
+VPALIGNR_128_3of3(mem)
+ before
+ c845ac575b126875.032aaff8d7bc5e3a.dd705557e99306c5.62a0ed54e326dd81
+ 11efdc8d1c60056d.c4be92cf7a57cea1.0b21f94586e6da26.fbcc2bb71e41f2ce
+ 76e641c6b96b84f6.195a39dde19e9e7e.26f9d4ffb1317141.bb9af1dc8f000a7a
+ d1f555ec4c419f3b.5e4ca28ea81c0d7c.0bc2617186808642.fc583a2ed3f16232
+ 1b50021985a036a1
+ after
+ c845ac575b126875.032aaff8d7bc5e3a.dd705557e99306c5.62a0ed54e326dd81
+ 11efdc8d1c60056d.c4be92cf7a57cea1.0b21f94586e6da26.fbcc2bb71e41f2ce
+ 0000000000000000.0000000000000000.21f94586e6da26fb.cc2bb71e41f2cedd
+ d1f555ec4c419f3b.5e4ca28ea81c0d7c.0bc2617186808642.fc583a2ed3f16232
+ 1b50021985a036a1
+
+VMOVSD_REG_XMM(reg)
+ before
+ 74cf45094197c275.ffe796edf4ed1369.efdec84e6c5e5548.94491d8720dfd756
+ 6421006aa4644157.dc897fb4ca7c9cac.285da889c8eeb38d.9e59822d9b5b1ea9
+ 45922da94a93f0f5.44a78d2dedf9f62f.64153cab595b63f8.05c00e4f14001767
+ 746eca30cdae0bfb.130d3a447670dc1f.01528220ba2ea035.a5483cdaa7d87fbb
+ 5abf88b86ff113d1
+ after
+ 74cf45094197c275.ffe796edf4ed1369.efdec84e6c5e5548.94491d8720dfd756
+ 0000000000000000.0000000000000000.efdec84e6c5e5548.a5483cdaa7d87fbb
+ 45922da94a93f0f5.44a78d2dedf9f62f.64153cab595b63f8.05c00e4f14001767
+ 746eca30cdae0bfb.130d3a447670dc1f.01528220ba2ea035.a5483cdaa7d87fbb
+ 5abf88b86ff113d1
+VMOVSD_REG_XMM(mem)
+ before
+ 00ef6ed788568cd6.4d00d36dcc43cd15.258704e583ed0ba7.5a60755588f5a7ef
+ 73a56b220f14a9f6.2c9642cae1de73ee.56e066fc307d3ef4.ca8a12b45e3bb4d2
+ 8fadf9841f36245d.6e7a14b5a80a3932.82e6dc75982c3332.af1d53abd88d038c
+ 30d296ebd5c8ba36.6df94698be535b8e.8563e23dd804a48c.646636a59376cfc7
+ 44afb60e2b82552f
+ after
+ 00ef6ed788568cd6.4d00d36dcc43cd15.258704e583ed0ba7.5a60755588f5a7ef
+ 73a56b220f14a9f6.2c9642cae1de73ee.56e066fc307d3ef4.ca8a12b45e3bb4d2
+ 8fadf9841f36245d.6e7a14b5a80a3932.82e6dc75982c3332.af1d53abd88d038c
+ 30d296ebd5c8ba36.6df94698be535b8e.8563e23dd804a48c.646636a59376cfc7
+ 44afb60e2b82552f
+
+VMOVSD_REG_XMM(reg)
+ before
+ ad44cf513b3dd171.32e2be424cd727ad.865fd3e1be4514ae.3b24f53e0b134e2f
+ f9737ddc5f347e39.71a7eb75a16e26ef.15f8b8fb456da13e.80f590664d64ec46
+ 8687bd1a34f39932.c9ee9b70ef997428.760fef52ee563ee9.30a22f9fbb043bfe
+ aecb8a7856045e09.168349205365cd83.05f27652568c275b.27f64ed771fef783
+ 41bf6af98a5edc00
+ after
+ ad44cf513b3dd171.32e2be424cd727ad.865fd3e1be4514ae.3b24f53e0b134e2f
+ 0000000000000000.0000000000000000.865fd3e1be4514ae.27f64ed771fef783
+ 8687bd1a34f39932.c9ee9b70ef997428.760fef52ee563ee9.30a22f9fbb043bfe
+ aecb8a7856045e09.168349205365cd83.05f27652568c275b.27f64ed771fef783
+ 41bf6af98a5edc00
+VMOVSD_REG_XMM(mem)
+ before
+ 59c7fdf12231a5a2.ce8ce06060f5096a.3332716fe8ddec2d.1eeb4868189c9741
+ 4ddb85ab56821094.4316bb3fee52d500.fec78f4bcb0d8f52.1c4761fed011cb47
+ f8c77d13415dd603.67b517829da5ff77.520e209e1702701d.5d52bd811b78ff19
+ 3557621500cfb61a.97b5f193087cc37d.0bd29e56e8c74bbb.3c58595e955c6e61
+ 15a52fffd94955ce
+ after
+ 59c7fdf12231a5a2.ce8ce06060f5096a.3332716fe8ddec2d.1eeb4868189c9741
+ 4ddb85ab56821094.4316bb3fee52d500.fec78f4bcb0d8f52.1c4761fed011cb47
+ f8c77d13415dd603.67b517829da5ff77.520e209e1702701d.5d52bd811b78ff19
+ 3557621500cfb61a.97b5f193087cc37d.0bd29e56e8c74bbb.3c58595e955c6e61
+ 15a52fffd94955ce
+
+VMOVSD_REG_XMM(reg)
+ before
+ 44843dd284cbf00a.e257ae9daee36a06.306244e0cc635cbb.04e0875e5b68de57
+ 24437f42306f7ac2.da92df9868a6aff3.8c070cd484e407e0.1b0456a18cf2e31e
+ 132cefbb7cc031a1.f8d670f04922410c.08f145dacd8d0096.2a0a880d9670173c
+ 6c8c8ba9024b4f54.1aeddd936e65db7e.006cec6042ea8389.0fbe978d95ee35dc
+ a4ec010da679fb2a
+ after
+ 44843dd284cbf00a.e257ae9daee36a06.306244e0cc635cbb.04e0875e5b68de57
+ 0000000000000000.0000000000000000.306244e0cc635cbb.0fbe978d95ee35dc
+ 132cefbb7cc031a1.f8d670f04922410c.08f145dacd8d0096.2a0a880d9670173c
+ 6c8c8ba9024b4f54.1aeddd936e65db7e.006cec6042ea8389.0fbe978d95ee35dc
+ a4ec010da679fb2a
+VMOVSD_REG_XMM(mem)
+ before
+ c75f417ae41c2354.8aaf4e785e9b1087.1aa4a36bf27b3a75.d1c4fcd17f85cb67
+ 52e5d4be6ce46983.cbe134942d3cb2e5.d6c73c66f16f1a1c.d545719922ec15d9
+ 234834c659db8be6.8a6d39690abb6f1a.2822266f884d37a0.693b4725c4ab9d8e
+ 1455df7fc81043a7.22a15a6392a284d4.ee80dc72d3214c2c.e9f17adf034d9f30
+ b1b507347b5e566b
+ after
+ c75f417ae41c2354.8aaf4e785e9b1087.1aa4a36bf27b3a75.d1c4fcd17f85cb67
+ 52e5d4be6ce46983.cbe134942d3cb2e5.d6c73c66f16f1a1c.d545719922ec15d9
+ 234834c659db8be6.8a6d39690abb6f1a.2822266f884d37a0.693b4725c4ab9d8e
+ 1455df7fc81043a7.22a15a6392a284d4.ee80dc72d3214c2c.e9f17adf034d9f30
+ b1b507347b5e566b
+
+VMOVSS_REG_XMM(reg)
+ before
+ 1dd1e991c76affed.03d850d3d48c4ef3.f1c791ef60802cbd.02afdb5bedf816ed
+ 89921c6083fed55f.ca9c03b09a5d67f5.512cdc7711dea581.41799d16f2dd510e
+ 51449c0f4ca51670.466f7401358e4cda.a01c3769404a29cd.88aba08fffddb8bc
+ d1336609bdebfcca.541b20b2c22cb7cd.38e39c308a50f44d.b1115fb230020923
+ 9977566c9f5bfd6e
+ after
+ 1dd1e991c76affed.03d850d3d48c4ef3.f1c791ef60802cbd.02afdb5bedf816ed
+ 0000000000000000.0000000000000000.f1c791ef60802cbd.02afdb5b30020923
+ 51449c0f4ca51670.466f7401358e4cda.a01c3769404a29cd.88aba08fffddb8bc
+ d1336609bdebfcca.541b20b2c22cb7cd.38e39c308a50f44d.b1115fb230020923
+ 9977566c9f5bfd6e
+VMOVSS_REG_XMM(mem)
+ before
+ 1da902a76bf153ca.65aa74ba735dc419.ce6e82af5c4164fb.76cd09388a7a44ac
+ 1772dd51aed2c562.68f7c48e0986a90b.913216e420dc1190.b72578ecdc565397
+ 649f655584091063.386452f11cf3e849.7934583d290678b7.5538e8ba1e705eb9
+ e0fd159e0aa3f0f9.303e184f472fbd82.623fc4a693cd569d.ad53520ee952a0bf
+ 1cc0b352db8a5755
+ after
+ 1da902a76bf153ca.65aa74ba735dc419.ce6e82af5c4164fb.76cd09388a7a44ac
+ 1772dd51aed2c562.68f7c48e0986a90b.913216e420dc1190.b72578ecdc565397
+ 649f655584091063.386452f11cf3e849.7934583d290678b7.5538e8ba1e705eb9
+ e0fd159e0aa3f0f9.303e184f472fbd82.623fc4a693cd569d.ad53520ee952a0bf
+ 1cc0b352db8a5755
+
+VMOVSS_REG_XMM(reg)
+ before
+ fccb08f38fa4bd26.67566a1a5bab214f.acd1141427c66460.2921d70b7b3c676d
+ aac24c5da22a0edf.d577deb4932d5e92.076940ac5744188f.a8a40c59fc606654
+ 82f07bfdb0aa882c.062bef58d03664ee.9f519a84743617bc.bc96df7a3344107e
+ e0a0923d54b065b8.d64018f32bd0ee8d.cfd71e0619289a93.41c1cc5c3cf42116
+ 13f250ea327d5449
+ after
+ fccb08f38fa4bd26.67566a1a5bab214f.acd1141427c66460.2921d70b7b3c676d
+ 0000000000000000.0000000000000000.acd1141427c66460.2921d70b3cf42116
+ 82f07bfdb0aa882c.062bef58d03664ee.9f519a84743617bc.bc96df7a3344107e
+ e0a0923d54b065b8.d64018f32bd0ee8d.cfd71e0619289a93.41c1cc5c3cf42116
+ 13f250ea327d5449
+VMOVSS_REG_XMM(mem)
+ before
+ 0ef5e60f31e96742.201f8b8b2ac6e22f.2180d56fc20aba9e.f245c6a0e3a4e0bf
+ 0e950ab95647132e.9eb96452cf7a3b3e.c3b8a2b9b1ed824b.66e890bd6d3823ed
+ efa038d3bca01739.b6ba18fede58ab91.98b5fcbe138703c1.850c77c8536fa0c9
+ 8ce0ec4980022d8e.c46ea3fbf4eb6fd4.7c415e6804e4f82b.adfd772f32d693fe
+ 38078c5da6f83738
+ after
+ 0ef5e60f31e96742.201f8b8b2ac6e22f.2180d56fc20aba9e.f245c6a0e3a4e0bf
+ 0e950ab95647132e.9eb96452cf7a3b3e.c3b8a2b9b1ed824b.66e890bd6d3823ed
+ efa038d3bca01739.b6ba18fede58ab91.98b5fcbe138703c1.850c77c8536fa0c9
+ 8ce0ec4980022d8e.c46ea3fbf4eb6fd4.7c415e6804e4f82b.adfd772f32d693fe
+ 38078c5da6f83738
+
+VMOVSS_REG_XMM(reg)
+ before
+ 8475b3be4a61c925.c322a308bd79135a.242102b5acbfc3b2.4b2844a5a10e1eb6
+ eb95e7beba9e856f.6f32d8fa900f82c8.321e2f98a360e2d7.e1382a5f0613318e
+ cbb124ca933aa7c2.6cdc070c14d23905.4ab32810745b0af0.1a3b8c844effedde
+ 7e16664c70c16acb.96ecac2b65cef23d.c82ae889bb3b75a9.d1ffe7ff95dc0dd3
+ e44eb6bcf8b84f98
+ after
+ 8475b3be4a61c925.c322a308bd79135a.242102b5acbfc3b2.4b2844a5a10e1eb6
+ 0000000000000000.0000000000000000.242102b5acbfc3b2.4b2844a595dc0dd3
+ cbb124ca933aa7c2.6cdc070c14d23905.4ab32810745b0af0.1a3b8c844effedde
+ 7e16664c70c16acb.96ecac2b65cef23d.c82ae889bb3b75a9.d1ffe7ff95dc0dd3
+ e44eb6bcf8b84f98
+VMOVSS_REG_XMM(mem)
+ before
+ 2ef575a7929f6c5a.6110a9b2eec00b36.c82e4441a00d6a9b.08d06c70158d5fad
+ 8bc0a1ac809b2345.d1ebea66a8c2c6ae.e06d4a3ce19d5d4b.66f1ae2f1edb06a9
+ d67ab4b8ddba2e84.28f224d63b53d6e0.b9763a07438a867b.3ed8ac3471b4a449
+ edf12cb5c6084a43.c373536c42007977.2e15908de2dfa255.ebd361e9aaa17638
+ cb2cc9bc6630b723
+ after
+ 2ef575a7929f6c5a.6110a9b2eec00b36.c82e4441a00d6a9b.08d06c70158d5fad
+ 8bc0a1ac809b2345.d1ebea66a8c2c6ae.e06d4a3ce19d5d4b.66f1ae2f1edb06a9
+ d67ab4b8ddba2e84.28f224d63b53d6e0.b9763a07438a867b.3ed8ac3471b4a449
+ edf12cb5c6084a43.c373536c42007977.2e15908de2dfa255.ebd361e9aaa17638
+ cb2cc9bc6630b723
+
+VMOVLPD_128_M64_XMM_XMM(reg)
+ before
+ 3930e11841eca4b5.aaef8491569033b0.ffb873965a54e920.1d16c8bcdba86d05
+ 912ba369d662799b.eb423836aa5ea4f5.360e81bf1edb6287.61455f7f4af1a3b8
+ 2e690d1bc11d7281.8ab4c592dd7e5a3e.c5c178532b222157.d56ed0c24ac7ff9a
+ 6e361a9a9fa9ca12.6512a5900bfd11b8.081d54be1cb4633d.575c9772f7353ed6
+ c1dd30796e471c99
+ after
+ 3930e11841eca4b5.aaef8491569033b0.ffb873965a54e920.1d16c8bcdba86d05
+ 912ba369d662799b.eb423836aa5ea4f5.360e81bf1edb6287.61455f7f4af1a3b8
+ 2e690d1bc11d7281.8ab4c592dd7e5a3e.c5c178532b222157.d56ed0c24ac7ff9a
+ 6e361a9a9fa9ca12.6512a5900bfd11b8.081d54be1cb4633d.575c9772f7353ed6
+ c1dd30796e471c99
+VMOVLPD_128_M64_XMM_XMM(mem)
+ before
+ f0bb17c4ca0a540f.abdec7520b92bffa.5627561b51e6858f.5b6e116c8d1d61e4
+ c1c3c9402889a363.43ac0eb0a2658ae7.3bc15321cb4571ee.1affabca1cea5af9
+ 0ec1c1d7a3d1c5c1.90eded1effae6a83.eeaa198d94279202.a11e1f4262a68828
+ b5807b7758ed7657.f0ed5f0abff7997a.4db0224cc897a4f6.4c156842fdde281c
+ 77318234881c7682
+ after
+ f0bb17c4ca0a540f.abdec7520b92bffa.5627561b51e6858f.5b6e116c8d1d61e4
+ c1c3c9402889a363.43ac0eb0a2658ae7.3bc15321cb4571ee.1affabca1cea5af9
+ 0000000000000000.0000000000000000.3bc15321cb4571ee.5b6e116c8d1d61e4
+ b5807b7758ed7657.f0ed5f0abff7997a.4db0224cc897a4f6.4c156842fdde281c
+ 77318234881c7682
+
+VMOVLPD_128_M64_XMM_XMM(reg)
+ before
+ 7ebe6986a0eead05.90ce740b62e9714f.bdf860de7dce5479.329dec4884a262f8
+ bd071aa3e1e00a52.7c75267fded173d5.555aed08d6bed72c.7a3ef26ee4538a31
+ 905a8ff6e67dc915.55430fbfe7b23816.125f00f365545d3e.015eb0aa03b6d5cf
+ 5301c6ed4b5125f9.f802aab799977b3e.5152970bc61b245c.a4cba3e9fdd702fe
+ 3d504516efc3cbea
+ after
+ 7ebe6986a0eead05.90ce740b62e9714f.bdf860de7dce5479.329dec4884a262f8
+ bd071aa3e1e00a52.7c75267fded173d5.555aed08d6bed72c.7a3ef26ee4538a31
+ 905a8ff6e67dc915.55430fbfe7b23816.125f00f365545d3e.015eb0aa03b6d5cf
+ 5301c6ed4b5125f9.f802aab799977b3e.5152970bc61b245c.a4cba3e9fdd702fe
+ 3d504516efc3cbea
+VMOVLPD_128_M64_XMM_XMM(mem)
+ before
+ a9b8141cf485edbe.614abbf3ade85cab.3f7f7353118dfa78.6f81adbc969f6631
+ c4d08be9292a24a6.187f6875a7cfa8d6.0785e77f6b9f6ef1.c6363e72716d5f6a
+ 6a642668a9bd2cd0.d3edcbddd6914527.2ce28027c2d996d4.b3be4799f2104cb3
+ 77406285914ac065.eedfde98d5bb714a.8a60bc3832472c4e.9365c39db51469b7
+ c076aeeb5706f223
+ after
+ a9b8141cf485edbe.614abbf3ade85cab.3f7f7353118dfa78.6f81adbc969f6631
+ c4d08be9292a24a6.187f6875a7cfa8d6.0785e77f6b9f6ef1.c6363e72716d5f6a
+ 0000000000000000.0000000000000000.0785e77f6b9f6ef1.6f81adbc969f6631
+ 77406285914ac065.eedfde98d5bb714a.8a60bc3832472c4e.9365c39db51469b7
+ c076aeeb5706f223
+
+VMOVLPD_128_M64_XMM_XMM(reg)
+ before
+ 973f04ed747123a3.c730ba2cfcde9d94.c4a3a01340d866ea.fdcd169cd8f6ee8b
+ 740ac111a7e237e2.36ffaa4906847e87.b3840ab8b57461b3.61f30b41cff295b6
+ b325e2c18ce36b8c.a07baec8cd48216a.16cd19f5cd1c9d53.929f15123445e0fc
+ b0da626bc002fa4e.e16e42966a36406a.48cbca34265a5774.6c9db2fb23fd8988
+ cbb85de7b6254d87
+ after
+ 973f04ed747123a3.c730ba2cfcde9d94.c4a3a01340d866ea.fdcd169cd8f6ee8b
+ 740ac111a7e237e2.36ffaa4906847e87.b3840ab8b57461b3.61f30b41cff295b6
+ b325e2c18ce36b8c.a07baec8cd48216a.16cd19f5cd1c9d53.929f15123445e0fc
+ b0da626bc002fa4e.e16e42966a36406a.48cbca34265a5774.6c9db2fb23fd8988
+ cbb85de7b6254d87
+VMOVLPD_128_M64_XMM_XMM(mem)
+ before
+ 8bbe92c40ccae825.c7763d7adecb22d4.d5a5e39dfb5b98b3.a7ca18e35cbdcbc2
+ 8879ce7d3ef7158d.54446f5a83c91dca.58ec0ccb9cc3e471.8d16ff6d0ace35ea
+ 9eb68bff6bb891ec.b392f4774a8828db.460f390a6878e1cf.58fb7b3ecc1bd198
+ a9414734ac1a186d.40aac93dd0947eb3.7bd9e6487b884bf9.62c489c23f2fda77
+ 09bf2465ff978d34
+ after
+ 8bbe92c40ccae825.c7763d7adecb22d4.d5a5e39dfb5b98b3.a7ca18e35cbdcbc2
+ 8879ce7d3ef7158d.54446f5a83c91dca.58ec0ccb9cc3e471.8d16ff6d0ace35ea
+ 0000000000000000.0000000000000000.58ec0ccb9cc3e471.a7ca18e35cbdcbc2
+ a9414734ac1a186d.40aac93dd0947eb3.7bd9e6487b884bf9.62c489c23f2fda77
+ 09bf2465ff978d34
+
+VMOVLPD_128_XMM_M64(reg)
+ before
+ a7364894a6de257a.84e67d091f28653d.57dae918b07a5cff.d3188f70f2ffde1c
+ 9976f1b9d390dff7.0d71aa6be0ee3687.546c507586c5fe6b.2996b16ee8e75564
+ 3ccb1c41203af754.1fae48440a794578.93adfabeef02a0a2.5b20c72e7a4e6efc
+ ea81c3992967a93f.9668d582bad44e3c.70e9e46087bb7d51.44824d9cc340e211
+ c088bfa4e0c770cf
+ after
+ a7364894a6de257a.84e67d091f28653d.57dae918b07a5cff.d3188f70f2ffde1c
+ 9976f1b9d390dff7.0d71aa6be0ee3687.546c507586c5fe6b.2996b16ee8e75564
+ 3ccb1c41203af754.1fae48440a794578.93adfabeef02a0a2.5b20c72e7a4e6efc
+ ea81c3992967a93f.9668d582bad44e3c.70e9e46087bb7d51.44824d9cc340e211
+ c088bfa4e0c770cf
+VMOVLPD_128_XMM_M64(mem)
+ before
+ aafe9a32ecf2d261.00e3e42c8ba33164.4d6ccc100b0b0fff.466b09c8e97fd224
+ e0af593304cac5f4.db3f7a65e17bca6f.2286a9da192b42eb.73816561b1d7dbc6
+ 3c697891435d05b3.d5df82b2c77ab10b.f082e9cb013fa42f.5275f4977c51d4e4
+ 9cf6733ac6b64dcb.4b10f67edb2c21e4.922c06d1de54f0f5.3f95b2d5e678f829
+ 952b9c898ad98442
+ after
+ aafe9a32ecf2d261.00e3e42c8ba33164.4d6ccc100b0b0fff.5275f4977c51d4e4
+ e0af593304cac5f4.db3f7a65e17bca6f.2286a9da192b42eb.73816561b1d7dbc6
+ 3c697891435d05b3.d5df82b2c77ab10b.f082e9cb013fa42f.5275f4977c51d4e4
+ 9cf6733ac6b64dcb.4b10f67edb2c21e4.922c06d1de54f0f5.3f95b2d5e678f829
+ 952b9c898ad98442
+
+VMOVLPD_128_XMM_M64(reg)
+ before
+ b284ad1e04ffb4db.da23c718a8e15a67.991ed435b61e58a8.e6507ed8cd74e46a
+ f1ebe101f176c39f.d4bcee1906ebe8b4.1b551743f6db9000.c6b9cccaeaae3ab9
+ adae349ceccaee3a.648d6628fbdfb3de.2d00bb1437f0069b.10356c944f0bae0f
+ 4417a35c9288715a.6861aa31a3ca7610.2b6dbc1514e7f523.9e8edb221b99fe97
+ 4d9194616763e47e
+ after
+ b284ad1e04ffb4db.da23c718a8e15a67.991ed435b61e58a8.e6507ed8cd74e46a
+ f1ebe101f176c39f.d4bcee1906ebe8b4.1b551743f6db9000.c6b9cccaeaae3ab9
+ adae349ceccaee3a.648d6628fbdfb3de.2d00bb1437f0069b.10356c944f0bae0f
+ 4417a35c9288715a.6861aa31a3ca7610.2b6dbc1514e7f523.9e8edb221b99fe97
+ 4d9194616763e47e
+VMOVLPD_128_XMM_M64(mem)
+ before
+ fa0a123c52751df0.107429ae7e3c88a9.ba0636201bb6ee77.71e617b0294e9a44
+ 7fc4d49ef5dc6418.6f0fc2fc4d706ed3.384687e17fb1d73f.5bb9c75213b131ac
+ b98d53756fa37723.bb356ab49ab26085.bcee1860eac7ec93.4530c8686e9bf604
+ 852f0dacd9d7103d.52311d40028d9a6b.23ca658a7803eb9f.8b97165dd59824fb
+ 893cae9ce434f83b
+ after
+ fa0a123c52751df0.107429ae7e3c88a9.ba0636201bb6ee77.4530c8686e9bf604
+ 7fc4d49ef5dc6418.6f0fc2fc4d706ed3.384687e17fb1d73f.5bb9c75213b131ac
+ b98d53756fa37723.bb356ab49ab26085.bcee1860eac7ec93.4530c8686e9bf604
+ 852f0dacd9d7103d.52311d40028d9a6b.23ca658a7803eb9f.8b97165dd59824fb
+ 893cae9ce434f83b
+
+VMOVLPD_128_XMM_M64(reg)
+ before
+ 9b6a8b9338fcae70.bd787c2f5183eb91.8e51d80e208e5730.49a6ea4946718d91
+ 1d6ca9ad6c7b8247.3e321eeaf3b3c64b.cce096899040d481.0b4e238b6f1d9192
+ 6b8f04561d3eaf6c.e42a6fc9da735b99.6929531def2f4d09.438d8d3a1014b1d1
+ e11f98fae6d0728b.8c2be9b822d067a4.bf790b36d9e8fe75.ce31a3444462aa78
+ 8804e194281138b4
+ after
+ 9b6a8b9338fcae70.bd787c2f5183eb91.8e51d80e208e5730.49a6ea4946718d91
+ 1d6ca9ad6c7b8247.3e321eeaf3b3c64b.cce096899040d481.0b4e238b6f1d9192
+ 6b8f04561d3eaf6c.e42a6fc9da735b99.6929531def2f4d09.438d8d3a1014b1d1
+ e11f98fae6d0728b.8c2be9b822d067a4.bf790b36d9e8fe75.ce31a3444462aa78
+ 8804e194281138b4
+VMOVLPD_128_XMM_M64(mem)
+ before
+ 4dd3c315d72f17b0.da68620664bd064e.10030aa4e8d5a69b.2b1cbb40e9f62271
+ f96ac6b56ec70299.b4b65de43291a964.4d7c4d77488fd3a8.095e5da8bbe5f6a8
+ 6894646008e6b69a.ca558501edd99577.1f642e1e5d09abf7.b68befd8ec42b6c7
+ 771f1b00c297eee0.7790d6ca30200734.62852986434feab6.8cee6c3e18989d7a
+ e8d5d144d973e96c
+ after
+ 4dd3c315d72f17b0.da68620664bd064e.10030aa4e8d5a69b.b68befd8ec42b6c7
+ f96ac6b56ec70299.b4b65de43291a964.4d7c4d77488fd3a8.095e5da8bbe5f6a8
+ 6894646008e6b69a.ca558501edd99577.1f642e1e5d09abf7.b68befd8ec42b6c7
+ 771f1b00c297eee0.7790d6ca30200734.62852986434feab6.8cee6c3e18989d7a
+ e8d5d144d973e96c
+
+VSHUFPD_128_1of2(reg)
+ before
+ 268a1858ce60d449.ffd56782b7e66896.19b54caa98f33a46.f2acbb9a176e4b0e
+ a25a3fe491ea9abe.df84c2d203e0deea.0b0ee40cc0dd6c5a.aba55f46f4718c2e
+ b8914156be9e7977.f2f6aaddc3900d05.a8e8995e446ad71c.693b9176f7646640
+ c47b1a19f206ab20.14f8998d1302b016.4e8f670bc127b737.083ccd153b549870
+ 64728f12dd4cdceb
+ after
+ 0000000000000000.0000000000000000.083ccd153b549870.aba55f46f4718c2e
+ a25a3fe491ea9abe.df84c2d203e0deea.0b0ee40cc0dd6c5a.aba55f46f4718c2e
+ b8914156be9e7977.f2f6aaddc3900d05.a8e8995e446ad71c.693b9176f7646640
+ c47b1a19f206ab20.14f8998d1302b016.4e8f670bc127b737.083ccd153b549870
+ 64728f12dd4cdceb
+VSHUFPD_128_1of2(mem)
+ before
+ 58aa5456f858f0dd.2263c799c8b16c64.21550dd00e438447.574e4b7fd39f4a57
+ c2b097cea9858d72.2e974342dc28faef.f5db8291d05e45c4.21733f26155eca2a
+ 7d50d4660bde72d5.44618a81ccf98f6e.6c5472bb765fafba.0648416c23f17459
+ 6556870b3b6f5932.c00e98c031af688d.628e5b3c1b537d55.631b4cbd9ae28393
+ 95365c8615c03582
+ after
+ 58aa5456f858f0dd.2263c799c8b16c64.21550dd00e438447.574e4b7fd39f4a57
+ c2b097cea9858d72.2e974342dc28faef.f5db8291d05e45c4.21733f26155eca2a
+ 0000000000000000.0000000000000000.574e4b7fd39f4a57.f5db8291d05e45c4
+ 6556870b3b6f5932.c00e98c031af688d.628e5b3c1b537d55.631b4cbd9ae28393
+ 95365c8615c03582
+
+VSHUFPD_128_1of2(reg)
+ before
+ f6e66e313114c4d3.558e2da75445ffb6.feea696ca9d6c1f7.b253b8ffdc456dc1
+ e3767c2c896c6c31.2bc34028726b208d.5a41faf2d0fbd559.3a7005f0d5413828
+ b93484e1ba546b49.c2c23e79b2ed77e2.2f5f45bc41a9e15f.d5b1befc20549db9
+ d26a81be5f56fbc6.f557a38630d8c1e2.db8f4838986d21b4.5ee1600ddc89569e
+ b3ce661022ec2004
+ after
+ 0000000000000000.0000000000000000.5ee1600ddc89569e.3a7005f0d5413828
+ e3767c2c896c6c31.2bc34028726b208d.5a41faf2d0fbd559.3a7005f0d5413828
+ b93484e1ba546b49.c2c23e79b2ed77e2.2f5f45bc41a9e15f.d5b1befc20549db9
+ d26a81be5f56fbc6.f557a38630d8c1e2.db8f4838986d21b4.5ee1600ddc89569e
+ b3ce661022ec2004
+VSHUFPD_128_1of2(mem)
+ before
+ ae424cf2108ab716.8b66702e15005955.a24ee93b0737bab9.b91fffd172d2d105
+ 2d0b8e9dc26ed601.40724b9d77dec1a2.a4738e8453161e92.245964f36b642cfd
+ 0bf3a8ff53a43af1.4ddb1077227b6e58.d6920c4d3182a899.7a8a750a1eb06f49
+ 23c71703e0399f11.0fedba28b1639d24.1676e182bc8615fc.16fe2d822740d695
+ 530188c723a39c8c
+ after
+ ae424cf2108ab716.8b66702e15005955.a24ee93b0737bab9.b91fffd172d2d105
+ 2d0b8e9dc26ed601.40724b9d77dec1a2.a4738e8453161e92.245964f36b642cfd
+ 0000000000000000.0000000000000000.b91fffd172d2d105.a4738e8453161e92
+ 23c71703e0399f11.0fedba28b1639d24.1676e182bc8615fc.16fe2d822740d695
+ 530188c723a39c8c
+
+VSHUFPD_128_1of2(reg)
+ before
+ 8fde8245ad62feda.525256958438c18d.e0f3451cc0228ab1.3eed890f112f21e5
+ 25e31768620b382d.7562e1a15bae5b93.1d3baebfec4570ac.2cc17ee14b878780
+ 705a449ddd29852f.66c1341382a52a4c.220fef7ed1578cc1.babf3ee2879d04fa
+ cd90044ebb49238c.033dccd7152ceae7.4bbc06c30ae41a9b.c5b34400e07a547f
+ 2a680c25732c333a
+ after
+ 0000000000000000.0000000000000000.c5b34400e07a547f.2cc17ee14b878780
+ 25e31768620b382d.7562e1a15bae5b93.1d3baebfec4570ac.2cc17ee14b878780
+ 705a449ddd29852f.66c1341382a52a4c.220fef7ed1578cc1.babf3ee2879d04fa
+ cd90044ebb49238c.033dccd7152ceae7.4bbc06c30ae41a9b.c5b34400e07a547f
+ 2a680c25732c333a
+VSHUFPD_128_1of2(mem)
+ before
+ c3ac123f5bbe5c58.99d153e997f64cf1.26a024d92f4c568e.f48eeefc337956e7
+ 6d49d339b53c8c04.2e692ed90ebc3c0a.acb7b805ec132c6e.79d1a394e9a17b50
+ 050dcaff9cb37f6b.eaa38f8abb283182.724e0448698c25b2.36d122f6c8e9c783
+ 65c2737d2d2ff0b9.27cd74673ac56506.5230848cc1c40087.86d966906adb732c
+ c7376bcd6e06bef6
+ after
+ c3ac123f5bbe5c58.99d153e997f64cf1.26a024d92f4c568e.f48eeefc337956e7
+ 6d49d339b53c8c04.2e692ed90ebc3c0a.acb7b805ec132c6e.79d1a394e9a17b50
+ 0000000000000000.0000000000000000.f48eeefc337956e7.acb7b805ec132c6e
+ 65c2737d2d2ff0b9.27cd74673ac56506.5230848cc1c40087.86d966906adb732c
+ c7376bcd6e06bef6
+
+VSHUFPD_128_2of2(reg)
+ before
+ 54352d196df3e28e.6a354a9f83ba9d19.4231d8de281f1541.292bb5bf11c57718
+ 8920a8e006301c9f.f031cc51ba623fb8.981cb85b21c37de0.d30912cb749e4792
+ c244d98fd248a8d6.d3847380ef3295c2.83da0e48c03cd88f.2c97179e07582c21
+ 5aedbb9070c8c1de.eff8bd163e375962.60b7d812a11663f9.10a14023e501e2f0
+ 5bf30a462ba4242c
+ after
+ 0000000000000000.0000000000000000.60b7d812a11663f9.d30912cb749e4792
+ 8920a8e006301c9f.f031cc51ba623fb8.981cb85b21c37de0.d30912cb749e4792
+ c244d98fd248a8d6.d3847380ef3295c2.83da0e48c03cd88f.2c97179e07582c21
+ 5aedbb9070c8c1de.eff8bd163e375962.60b7d812a11663f9.10a14023e501e2f0
+ 5bf30a462ba4242c
+VSHUFPD_128_2of2(mem)
+ before
+ ea59eff3f44eaf00.af674a50793ba465.205b2501c17c49c4.8bff112561de5acb
+ 979e6d165d0a3e99.1cfd823c8b2d8d14.4277282b970d1e15.61feb5ee9c1ff8b0
+ 3f90ff9c81e48f23.fcfc5fbe422ab89a.31194082daf69781.3cffc0d7ec657a55
+ bef9226f7ce95cc9.adb1de4439bf60a1.c90debf1a6446e33.794f2f4ef03d1c66
+ 743afdbe42321a8e
+ after
+ ea59eff3f44eaf00.af674a50793ba465.205b2501c17c49c4.8bff112561de5acb
+ 979e6d165d0a3e99.1cfd823c8b2d8d14.4277282b970d1e15.61feb5ee9c1ff8b0
+ 0000000000000000.0000000000000000.205b2501c17c49c4.4277282b970d1e15
+ bef9226f7ce95cc9.adb1de4439bf60a1.c90debf1a6446e33.794f2f4ef03d1c66
+ 743afdbe42321a8e
+
+VSHUFPD_128_2of2(reg)
+ before
+ 890c26937ed1af7a.efa6507c6b2462b8.8966fa390d77c2d5.e61ea46418036058
+ 1411a63941a418d5.b06307b06aa15c1b.ee67af0959df1ae3.641ae7c74b3d291c
+ 71957a1c2639914c.dcfcc2f5946d071f.3602fa20b982a377.1fcb31065c0084aa
+ fce39ca8c91c568b.4f3dfe3905931ff0.bf82d5eacaec9a3c.f3fefc0d66582e2f
+ bc80c6c8864fe3d6
+ after
+ 0000000000000000.0000000000000000.bf82d5eacaec9a3c.641ae7c74b3d291c
+ 1411a63941a418d5.b06307b06aa15c1b.ee67af0959df1ae3.641ae7c74b3d291c
+ 71957a1c2639914c.dcfcc2f5946d071f.3602fa20b982a377.1fcb31065c0084aa
+ fce39ca8c91c568b.4f3dfe3905931ff0.bf82d5eacaec9a3c.f3fefc0d66582e2f
+ bc80c6c8864fe3d6
+VSHUFPD_128_2of2(mem)
+ before
+ 561a0a23d7f35ecc.11480a49c8d8a23d.e5f13567da1f60b9.e3323ed327aa3bdf
+ 9c9b440b75505d3d.0c10bf6bbcf9b20f.7ae5e56b2f1e85a6.005f30476d47c20b
+ 6ccef16a7d709a54.4887b87b430bc1ac.e9e589311e9b4ce5.7055a7b3384f6a6d
+ a17e8c2e0b61d13e.23f9efe3f99b0dc1.10bd9da5c6a26ea0.9060a081224f70b1
+ bdcc151fcad21082
+ after
+ 561a0a23d7f35ecc.11480a49c8d8a23d.e5f13567da1f60b9.e3323ed327aa3bdf
+ 9c9b440b75505d3d.0c10bf6bbcf9b20f.7ae5e56b2f1e85a6.005f30476d47c20b
+ 0000000000000000.0000000000000000.e5f13567da1f60b9.7ae5e56b2f1e85a6
+ a17e8c2e0b61d13e.23f9efe3f99b0dc1.10bd9da5c6a26ea0.9060a081224f70b1
+ bdcc151fcad21082
+
+VSHUFPD_128_2of2(reg)
+ before
+ 51e504f7c964858d.167891423a2fc026.f8b262117934d0fa.ca399db34140aa03
+ a9f66877be920c7e.a9897c9226e42139.23fe0c6f5f634702.f2250647ab80ba3b
+ 214c3e0a42e7e100.357ac90aec8fb1a2.0028e96b48b3ad86.664d534e206e5b74
+ 1634801cf4ef40bf.951af596a8392b8e.ea7df670d0b04031.017c00b2be1749d9
+ 9e7f89619e863f97
+ after
+ 0000000000000000.0000000000000000.ea7df670d0b04031.f2250647ab80ba3b
+ a9f66877be920c7e.a9897c9226e42139.23fe0c6f5f634702.f2250647ab80ba3b
+ 214c3e0a42e7e100.357ac90aec8fb1a2.0028e96b48b3ad86.664d534e206e5b74
+ 1634801cf4ef40bf.951af596a8392b8e.ea7df670d0b04031.017c00b2be1749d9
+ 9e7f89619e863f97
+VSHUFPD_128_2of2(mem)
+ before
+ 1b226a46dec7fada.e2f82c196d376469.a7347b2275f04d29.3f492dea92e63ab0
+ 5231204c9ae736cd.e2e43d6d4b4a8aa7.4593d79a6fbfd19e.5ad88c452ae2d7ae
+ 21782661edf1af9c.7246af842ab4ee28.4d0585eab3b2731a.96760eed353055d9
+ 62c2f870f4f22075.ee697fcaa502cc96.995402ff5cd6f1c9.516eb04e4e5aeeda
+ e50e6cd512eedf60
+ after
+ 1b226a46dec7fada.e2f82c196d376469.a7347b2275f04d29.3f492dea92e63ab0
+ 5231204c9ae736cd.e2e43d6d4b4a8aa7.4593d79a6fbfd19e.5ad88c452ae2d7ae
+ 0000000000000000.0000000000000000.a7347b2275f04d29.4593d79a6fbfd19e
+ 62c2f870f4f22075.ee697fcaa502cc96.995402ff5cd6f1c9.516eb04e4e5aeeda
+ e50e6cd512eedf60
+
+VSHUFPD_256_1of2(reg)
+ before
+ b0a040ec1c776314.f2dd1265caf54682.b298a7ac58bf5f9d.074dc8c3873605d6
+ 0c7127010982b8a5.ae93f12c8b06ddef.1a202594e078e4eb.71bc55244fdf6c6e
+ 57cd1d7e749a18bd.70b110b15431a0e9.824df4f0d9b79629.b46c240cd1dbe1bc
+ eb001ed1f94bbf09.1503ebe140834d9c.466b112ade0bb306.ad2bb269283922ed
+ 36c379267102e92c
+ after
+ 1503ebe140834d9c.ae93f12c8b06ddef.ad2bb269283922ed.71bc55244fdf6c6e
+ 0c7127010982b8a5.ae93f12c8b06ddef.1a202594e078e4eb.71bc55244fdf6c6e
+ 57cd1d7e749a18bd.70b110b15431a0e9.824df4f0d9b79629.b46c240cd1dbe1bc
+ eb001ed1f94bbf09.1503ebe140834d9c.466b112ade0bb306.ad2bb269283922ed
+ 36c379267102e92c
+VSHUFPD_256_1of2(mem)
+ before
+ 2c02f72fc744f2a6.265627653622eb34.7a55fea66c079d33.c2c676b08bfd752c
+ 6bb2a770460afb87.621a33a6c4aad6eb.7973c5eef4ca4fdb.52a921ed7d1b1947
+ d0a005d50b61befa.fc993e00416fbdd9.ef28bda3f2d71dbf.52620d4d4ff0da04
+ 35978e4a3254f82c.512044df49fedbab.b84261b3853ac40c.1d3b363c9e09f50f
+ 1181982605f0a613
+ after
+ 2c02f72fc744f2a6.265627653622eb34.7a55fea66c079d33.c2c676b08bfd752c
+ 6bb2a770460afb87.621a33a6c4aad6eb.7973c5eef4ca4fdb.52a921ed7d1b1947
+ 2c02f72fc744f2a6.6bb2a770460afb87.7a55fea66c079d33.7973c5eef4ca4fdb
+ 35978e4a3254f82c.512044df49fedbab.b84261b3853ac40c.1d3b363c9e09f50f
+ 1181982605f0a613
+
+VSHUFPD_256_1of2(reg)
+ before
+ 89803077213429bd.7765bdbcd6ef6548.bbf942af77e26e0d.b08b2d09c6ff00ee
+ e184f99c8d5eb9b9.72d40d15133ec07b.977132dc67a7b0aa.b3d09d91d4338d90
+ 74d8efffe6fc93b2.02b2fd43064ec6f1.41d312d3b6dadd2f.9edd2d37c8e2261f
+ a0ca0e0ec799f355.03c90630ca2b33d5.156ddefeff063347.4b7d5ae7c01688c6
+ 977e9f8dd8dd6eb2
+ after
+ 03c90630ca2b33d5.72d40d15133ec07b.4b7d5ae7c01688c6.b3d09d91d4338d90
+ e184f99c8d5eb9b9.72d40d15133ec07b.977132dc67a7b0aa.b3d09d91d4338d90
+ 74d8efffe6fc93b2.02b2fd43064ec6f1.41d312d3b6dadd2f.9edd2d37c8e2261f
+ a0ca0e0ec799f355.03c90630ca2b33d5.156ddefeff063347.4b7d5ae7c01688c6
+ 977e9f8dd8dd6eb2
+VSHUFPD_256_1of2(mem)
+ before
+ 5eaa78152b42960f.c0a45333ccc2154d.51e6a5ca7cdfc254.6f8990cbdfb7ec9f
+ 7ccf626bd652ba08.2fb3b8dc92023447.c8d557fc38783099.ac7426a4f27a45e3
+ ccb7d77cf41897ca.4b433b74b5e58dee.446197b2180139d1.267b9af7d2da7abe
+ 2c2f5532a1a0e880.6ea0d767d0f75cf0.a158e1d83b879928.3ae7ea2f1e64c6dd
+ 440712b86fa266eb
+ after
+ 5eaa78152b42960f.c0a45333ccc2154d.51e6a5ca7cdfc254.6f8990cbdfb7ec9f
+ 7ccf626bd652ba08.2fb3b8dc92023447.c8d557fc38783099.ac7426a4f27a45e3
+ 5eaa78152b42960f.7ccf626bd652ba08.51e6a5ca7cdfc254.c8d557fc38783099
+ 2c2f5532a1a0e880.6ea0d767d0f75cf0.a158e1d83b879928.3ae7ea2f1e64c6dd
+ 440712b86fa266eb
+
+VSHUFPD_256_1of2(reg)
+ before
+ a0260cfe64229695.7702577bfaf76a57.f61689217fc5dcf6.bb84b25aba150bc9
+ aa8fd66d96709187.89fe59421b28d97b.3df04b0e5fdb4aaf.6eb28524b4b74de1
+ be906b71a317956c.3eedd8731e3ff117.a17c1b9a0cc3e2c4.95afd522427a189b
+ 3773c77727a3dcf1.729d4ffa22496d58.7c04f431210be0e4.0e44214182692b24
+ b440e26b909040a7
+ after
+ 729d4ffa22496d58.89fe59421b28d97b.0e44214182692b24.6eb28524b4b74de1
+ aa8fd66d96709187.89fe59421b28d97b.3df04b0e5fdb4aaf.6eb28524b4b74de1
+ be906b71a317956c.3eedd8731e3ff117.a17c1b9a0cc3e2c4.95afd522427a189b
+ 3773c77727a3dcf1.729d4ffa22496d58.7c04f431210be0e4.0e44214182692b24
+ b440e26b909040a7
+VSHUFPD_256_1of2(mem)
+ before
+ 636e958e87fc1452.7385e6e9bda0a2c1.00d83ac341510b69.2bd5d23f3a3f7fb9
+ f699b79484b8634e.cd12c534029b2589.c66b15ba97638477.0b3bb231f4e9fcf0
+ 4b8ec36ba2d0e8ca.a1655fc5911f9ff5.9f225ccb418c97ad.76828f71ea979334
+ 3d1a35fefd5160f0.4bccb00706b94db0.66c88ce25ad7fe39.c9f5646db9d57f32
+ 61e23090fc2dfe95
+ after
+ 636e958e87fc1452.7385e6e9bda0a2c1.00d83ac341510b69.2bd5d23f3a3f7fb9
+ f699b79484b8634e.cd12c534029b2589.c66b15ba97638477.0b3bb231f4e9fcf0
+ 636e958e87fc1452.f699b79484b8634e.00d83ac341510b69.c66b15ba97638477
+ 3d1a35fefd5160f0.4bccb00706b94db0.66c88ce25ad7fe39.c9f5646db9d57f32
+ 61e23090fc2dfe95
+
+VSHUFPD_256_2of2(reg)
+ before
+ 9893ec46502d490a.a7068a39b24687ec.2691b466fef46a67.f92b1febff507644
+ cb5595fb50619f3d.67213c08dcbc19eb.9001674d155c33c5.331593d34b04bbfd
+ 5674281b99533ad9.5736c95798bdd119.e468c62ae57de477.ef5464845afe888d
+ 953ca012c691578b.5510ac1202576ca1.7d12cc680de4b928.0bb20cec4a4b9a23
+ 61fc09f634f5ade9
+ after
+ 953ca012c691578b.67213c08dcbc19eb.7d12cc680de4b928.331593d34b04bbfd
+ cb5595fb50619f3d.67213c08dcbc19eb.9001674d155c33c5.331593d34b04bbfd
+ 5674281b99533ad9.5736c95798bdd119.e468c62ae57de477.ef5464845afe888d
+ 953ca012c691578b.5510ac1202576ca1.7d12cc680de4b928.0bb20cec4a4b9a23
+ 61fc09f634f5ade9
+VSHUFPD_256_2of2(mem)
+ before
+ cffdd68e360a7d0c.e4f9f94c73a732fe.3b7d61253496a6b0.b94b7574271ced86
+ 2f83efa06c96c5b7.9ff630353d2007df.e747657d4d853a72.f35fbdb8cfb2be3a
+ 5e58d018f1a44217.22813f39c08811da.333b33046730e512.8699a1a1a23165f3
+ 394af6e2e140b057.c9e424c5976b8d9a.fc2547a89ea363bc.d0461b9c3b25215a
+ 2bb22913371b2c1e
+ after
+ cffdd68e360a7d0c.e4f9f94c73a732fe.3b7d61253496a6b0.b94b7574271ced86
+ 2f83efa06c96c5b7.9ff630353d2007df.e747657d4d853a72.f35fbdb8cfb2be3a
+ e4f9f94c73a732fe.2f83efa06c96c5b7.b94b7574271ced86.e747657d4d853a72
+ 394af6e2e140b057.c9e424c5976b8d9a.fc2547a89ea363bc.d0461b9c3b25215a
+ 2bb22913371b2c1e
+
+VSHUFPD_256_2of2(reg)
+ before
+ f529c774319ec3e9.9a23dbea5976caa4.f06cda445e56b7cc.1fd01d530eeb709e
+ 88f7ef29c53a2268.5eb0fd1c74534e2a.f3655e21b2d4ca1b.760a31f3d513c7e1
+ 41689fa0917c8446.62bdd8654fe2f514.2e1aaaca2e710334.de9d00730c2825b4
+ 7dc7d2442eef2730.8015e6af06307e8f.fdd9bcaa6fba9ec3.345705bfd1354641
+ 5202bcc34046e5b4
+ after
+ 7dc7d2442eef2730.5eb0fd1c74534e2a.fdd9bcaa6fba9ec3.760a31f3d513c7e1
+ 88f7ef29c53a2268.5eb0fd1c74534e2a.f3655e21b2d4ca1b.760a31f3d513c7e1
+ 41689fa0917c8446.62bdd8654fe2f514.2e1aaaca2e710334.de9d00730c2825b4
+ 7dc7d2442eef2730.8015e6af06307e8f.fdd9bcaa6fba9ec3.345705bfd1354641
+ 5202bcc34046e5b4
+VSHUFPD_256_2of2(mem)
+ before
+ 156ba16b7467c03b.966284813a1f44d1.9586a5e8b448a3c7.bcec8f2d113ad673
+ 595d30a389a59000.e983b1c351991ad6.7dda8ffb753621e7.c7a11fbfae7ee9f1
+ faa6e6589c0b142f.d37755760ee8e3eb.14de23d36607b41b.794268cce51111e8
+ d4103e74c9a606f5.ae8a6d070d98dcbb.375eda5ea2c51890.301c67c04f7f8a05
+ 477b17088a5492f3
+ after
+ 156ba16b7467c03b.966284813a1f44d1.9586a5e8b448a3c7.bcec8f2d113ad673
+ 595d30a389a59000.e983b1c351991ad6.7dda8ffb753621e7.c7a11fbfae7ee9f1
+ 966284813a1f44d1.595d30a389a59000.bcec8f2d113ad673.7dda8ffb753621e7
+ d4103e74c9a606f5.ae8a6d070d98dcbb.375eda5ea2c51890.301c67c04f7f8a05
+ 477b17088a5492f3
+
+VSHUFPD_256_2of2(reg)
+ before
+ 1aaa740e321d635f.c469b4e52b81237e.d708f4e0eb3641f3.c0263187457f0872
+ 04f77a3fe2663af5.a47bc495dea827f5.aa3ce66f434d4e3e.8c02a53a6d3e41ed
+ 63ac260837b95261.5113eb72ff28ce87.8373401eb2693e49.77bdb16333107e2c
+ 911672d4cca4e84d.a7fda467a90cd35f.befafc5bd4174ec0.5d25d1efb5007d5b
+ 1a0482c80f1bf8a7
+ after
+ 911672d4cca4e84d.a47bc495dea827f5.befafc5bd4174ec0.8c02a53a6d3e41ed
+ 04f77a3fe2663af5.a47bc495dea827f5.aa3ce66f434d4e3e.8c02a53a6d3e41ed
+ 63ac260837b95261.5113eb72ff28ce87.8373401eb2693e49.77bdb16333107e2c
+ 911672d4cca4e84d.a7fda467a90cd35f.befafc5bd4174ec0.5d25d1efb5007d5b
+ 1a0482c80f1bf8a7
+VSHUFPD_256_2of2(mem)
+ before
+ 8a273edb5c6cac3c.ec815c0f3db23868.81046b60f960f3aa.b71b189043e2b94e
+ 885a8315b8ff5445.cf39e02427707e5c.bdf6bc490a31ea93.cb238f2b9e56bda0
+ f269cc6140e1adef.958af8812669f6d6.369d130ef98a7348.545e5d977e009461
+ a32095aa101d7366.9bbfa191d529db81.c8c7ed9be1774bf2.af177f40826b7b3e
+ 379cef924324ade3
+ after
+ 8a273edb5c6cac3c.ec815c0f3db23868.81046b60f960f3aa.b71b189043e2b94e
+ 885a8315b8ff5445.cf39e02427707e5c.bdf6bc490a31ea93.cb238f2b9e56bda0
+ ec815c0f3db23868.885a8315b8ff5445.b71b189043e2b94e.bdf6bc490a31ea93
+ a32095aa101d7366.9bbfa191d529db81.c8c7ed9be1774bf2.af177f40826b7b3e
+ 379cef924324ade3
+
+VPERMILPS_128_0x00(reg)
+ before
+ 4a37abfa5fb667fb.774a5bde43bf62d5.3e26d8c1d03d6a0a.4f3ec5dcdf052ec0
+ 4335aee272ade533.4ab499e8f5d43569.d809987bb430de1c.a7ce17be0e3fd7dc
+ 7ee2f5b717956336.f72acab44367aa4d.c7b5de2c1c8e7464.ab455f2b8b310472
+ 578a7ae6ebfb1cb1.5c786d2e48847aae.6576a441a5e4688e.396e1a1171e86faf
+ 2c14c25adc6fd4bf
+ after
+ 4a37abfa5fb667fb.774a5bde43bf62d5.3e26d8c1d03d6a0a.4f3ec5dcdf052ec0
+ 0000000000000000.0000000000000000.8b3104728b310472.8b3104728b310472
+ 7ee2f5b717956336.f72acab44367aa4d.c7b5de2c1c8e7464.ab455f2b8b310472
+ 578a7ae6ebfb1cb1.5c786d2e48847aae.6576a441a5e4688e.396e1a1171e86faf
+ 2c14c25adc6fd4bf
+VPERMILPS_128_0x00(mem)
+ before
+ 5f04d5f4e9d2f1cd.2a793bd9896a4d50.546afb42213864b8.0f98e824ebbdf645
+ b00bcfcab41e8006.52fa33fe8d6f32be.baccf1dde98e2296.2266a54388a55a36
+ faf32ac8585e3e96.2d5a5ec0949507a8.6c6acce9bd937174.f82ed7091b29cf0d
+ 188864daf19ee6a8.16e6b98b396807b9.450f0754b8510d80.ee3a7ae13dd49275
+ 60d78b398c32de1a
+ after
+ 5f04d5f4e9d2f1cd.2a793bd9896a4d50.546afb42213864b8.0f98e824ebbdf645
+ 0000000000000000.0000000000000000.ebbdf645ebbdf645.ebbdf6450f98e824
+ faf32ac8585e3e96.2d5a5ec0949507a8.6c6acce9bd937174.f82ed7091b29cf0d
+ 188864daf19ee6a8.16e6b98b396807b9.450f0754b8510d80.ee3a7ae13dd49275
+ 60d78b398c32de1a
+
+VPERMILPS_128_0x00(reg)
+ before
+ aa51047ca4d0f1a9.e898f7ec9ceb3669.69e83fcb19746f9e.20881f08f7d6b1e4
+ 29f4e316203905ce.44ed62ea7450e804.81adebecd0467b02.dba18ef3952e1acc
+ 370c23749df95635.0a551ec096dab8a6.bc80bb5af9696693.5026d2ffae640465
+ 31e4c100b69d2289.149aa85b1d93647a.74afab81306a6dfa.5de3661a5f842bdb
+ dca3c62fc49a4a59
+ after
+ aa51047ca4d0f1a9.e898f7ec9ceb3669.69e83fcb19746f9e.20881f08f7d6b1e4
+ 0000000000000000.0000000000000000.ae640465ae640465.ae640465ae640465
+ 370c23749df95635.0a551ec096dab8a6.bc80bb5af9696693.5026d2ffae640465
+ 31e4c100b69d2289.149aa85b1d93647a.74afab81306a6dfa.5de3661a5f842bdb
+ dca3c62fc49a4a59
+VPERMILPS_128_0x00(mem)
+ before
+ aa346e2af8b31e0c.73c9b82707b0a376.40897da52689a6ad.0784b5ce12d4cce6
+ a460daf717da6320.590803562dbf16a9.68ee188cccc83b6b.cf4dd7ab3a33bf00
+ a4f487833e1cd4c0.3feba1f7c454b7ce.6995f5fb2c5bdedf.2a540c85451481f7
+ 87bcf0b889832f18.81bf8b7866fdc191.204990dd614e4d36.72e650c9ce024f75
+ 054fa0e271896527
+ after
+ aa346e2af8b31e0c.73c9b82707b0a376.40897da52689a6ad.0784b5ce12d4cce6
+ 0000000000000000.0000000000000000.12d4cce612d4cce6.12d4cce60784b5ce
+ a4f487833e1cd4c0.3feba1f7c454b7ce.6995f5fb2c5bdedf.2a540c85451481f7
+ 87bcf0b889832f18.81bf8b7866fdc191.204990dd614e4d36.72e650c9ce024f75
+ 054fa0e271896527
+
+VPERMILPS_128_0x00(reg)
+ before
+ 3ddaf63ccb36feb8.2a849183131e2d55.7acfbe44b246719d.67d7662088ad429c
+ 78d55043789457d5.6718e7d1f8f68da3.886937c742ba039e.1b0cf2afbc85793c
+ 108aa962132fac29.1b436c8c5519092e.06d7f16db2e5b341.18b2b0761ae1b042
+ 6246fd0839943961.22d39ea245925e21.5066e8a29f53bc32.3b961c61bdcea1db
+ 5e83b35dc1570933
+ after
+ 3ddaf63ccb36feb8.2a849183131e2d55.7acfbe44b246719d.67d7662088ad429c
+ 0000000000000000.0000000000000000.1ae1b0421ae1b042.1ae1b0421ae1b042
+ 108aa962132fac29.1b436c8c5519092e.06d7f16db2e5b341.18b2b0761ae1b042
+ 6246fd0839943961.22d39ea245925e21.5066e8a29f53bc32.3b961c61bdcea1db
+ 5e83b35dc1570933
+VPERMILPS_128_0x00(mem)
+ before
+ 5e47ef544388a476.ca55499e854e3929.5892f8fee56e48a8.c26319d2a4915b1c
+ 17ad4e335f6e2dcf.a503889193e9e92c.9a4df78c50b883f1.b7187e695e2acbac
+ 65804be72f14616a.4d9cb64d00f28517.c2d01538a37cca25.8dd115d368ab4a8e
+ 248d635ad286fc74.1f6bcf3f67f44895.ade6d0eef9c6da73.9fdcd97d5f9f126d
+ 4983c6d1de9260f6
+ after
+ 5e47ef544388a476.ca55499e854e3929.5892f8fee56e48a8.c26319d2a4915b1c
+ 0000000000000000.0000000000000000.a4915b1ca4915b1c.a4915b1cc26319d2
+ 65804be72f14616a.4d9cb64d00f28517.c2d01538a37cca25.8dd115d368ab4a8e
+ 248d635ad286fc74.1f6bcf3f67f44895.ade6d0eef9c6da73.9fdcd97d5f9f126d
+ 4983c6d1de9260f6
+
+VPERMILPS_128_0xFE(reg)
+ before
+ e614d93d81116fd4.30a0107a62d0b919.77becfd1657b7053.375da39a6ea36e05
+ d4d90d2ce5a67db4.6585d032fbff5585.b1dfb371961437fd.3cff0a281f1f4407
+ 6d1f5d09a6e0c441.9f071e6eba1f8ce3.291b768a944ad93e.989a8185284416a7
+ 0f32c8425f488028.baf4761aba3a1a5f.3bbe1488fea994c3.27f8859ba420a10e
+ c4e69158afbea06b
+ after
+ e614d93d81116fd4.30a0107a62d0b919.77becfd1657b7053.375da39a6ea36e05
+ 0000000000000000.0000000000000000.291b768a291b768a.291b768a944ad93e
+ 6d1f5d09a6e0c441.9f071e6eba1f8ce3.291b768a944ad93e.989a8185284416a7
+ 0f32c8425f488028.baf4761aba3a1a5f.3bbe1488fea994c3.27f8859ba420a10e
+ c4e69158afbea06b
+VPERMILPS_128_0xFE(mem)
+ before
+ 4d2f21a6662bd0e8.145d4742ac6cef15.92165522185eba26.431489d76dbea237
+ 9da1b173e572edb1.daeed8752ad74bb3.033b3572ef972a64.9d68d1e380143f47
+ 9007beaa479fb3f3.bb2f75477516d1af.e82d94f65cef2344.a508e918d038a99f
+ 022cc237a8bfddda.156e1c2528b4bcb5.1fb8ed9b7a7464f3.b73ecce2fbb41aea
+ 2f5776ad9d17cfd5
+ after
+ 4d2f21a6662bd0e8.145d4742ac6cef15.92165522185eba26.431489d76dbea237
+ 0000000000000000.0000000000000000.9216552292165522.9216552292165522
+ 9007beaa479fb3f3.bb2f75477516d1af.e82d94f65cef2344.a508e918d038a99f
+ 022cc237a8bfddda.156e1c2528b4bcb5.1fb8ed9b7a7464f3.b73ecce2fbb41aea
+ 2f5776ad9d17cfd5
+
+VPERMILPS_128_0xFE(reg)
+ before
+ 699fe3e651ea040b.cedd3b0625dd2991.42f5c979df3d4a70.83aabd4b6532a79d
+ c16210f7b4bbf439.d2e6a403d9065045.9f1176b1373eb58d.f0ce7ef43a33a96d
+ 93ecf84e6115dc0b.e9137a1ae1441122.890d2137cb4239b7.41efae8015852690
+ 3a889755f485f82c.ee30373758a52653.5a37c57938d5149b.54dac8dd1134d931
+ 045c48f64a4a7f7d
+ after
+ 699fe3e651ea040b.cedd3b0625dd2991.42f5c979df3d4a70.83aabd4b6532a79d
+ 0000000000000000.0000000000000000.890d2137890d2137.890d2137cb4239b7
+ 93ecf84e6115dc0b.e9137a1ae1441122.890d2137cb4239b7.41efae8015852690
+ 3a889755f485f82c.ee30373758a52653.5a37c57938d5149b.54dac8dd1134d931
+ 045c48f64a4a7f7d
+VPERMILPS_128_0xFE(mem)
+ before
+ 2c3faab7ddd5d49f.1484e97a0a958449.bf0859475b354c05.6fd95ee1198480e4
+ aa4f6b0ce6e194c5.7c2aea283ed4bb0d.37685b3405fe3f63.2441e8dd0bdaba3f
+ 585a06e180797a18.cdc797cb2dcbda25.311db9ec730eba9a.d6b960d8a963fe58
+ 142af722c7a943c7.65a7ebcf73081c3c.8bf1f059c0717ad5.df8ec03e8fac87da
+ 9c0c067b5b409272
+ after
+ 2c3faab7ddd5d49f.1484e97a0a958449.bf0859475b354c05.6fd95ee1198480e4
+ 0000000000000000.0000000000000000.bf085947bf085947.bf085947bf085947
+ 585a06e180797a18.cdc797cb2dcbda25.311db9ec730eba9a.d6b960d8a963fe58
+ 142af722c7a943c7.65a7ebcf73081c3c.8bf1f059c0717ad5.df8ec03e8fac87da
+ 9c0c067b5b409272
+
+VPERMILPS_128_0xFE(reg)
+ before
+ 697e2efba6ac5bcb.b88dbabbd87dabfb.9f16e2a0aa16bfff.1fb17b6909323b41
+ a232322b0e7a1d92.224dcc99ce026de3.d65f78aa7182fd1a.cb28d507695db90a
+ a37210752f381573.2c37a7a6c64346a9.68d0aa5a62d71338.69247c1ffcfeaf5b
+ c88bc347a4727f19.b417c9d0db4df27a.afb3731a19a13c06.d76fec9ddf22da61
+ efd79f6d2ed4f648
+ after
+ 697e2efba6ac5bcb.b88dbabbd87dabfb.9f16e2a0aa16bfff.1fb17b6909323b41
+ 0000000000000000.0000000000000000.68d0aa5a68d0aa5a.68d0aa5a62d71338
+ a37210752f381573.2c37a7a6c64346a9.68d0aa5a62d71338.69247c1ffcfeaf5b
+ c88bc347a4727f19.b417c9d0db4df27a.afb3731a19a13c06.d76fec9ddf22da61
+ efd79f6d2ed4f648
+VPERMILPS_128_0xFE(mem)
+ before
+ 8e26137b0321be3b.6dc9470b09b39731.94b9ad022a2a2d81.0955cf58326db630
+ 9129c3b47d14f066.ee78982ffb879866.a9e8d027cee9b2eb.d002ba7e4bc6bb61
+ d2ac2b02b6b945f7.a7e4b21e157abf65.d071ac2de4933ee3.620630fafd388746
+ 2e7ac852ca1c7c18.f4599244f41948da.e321bfff87368d96.19ac2e37e650588a
+ 5242afa1a29868da
+ after
+ 8e26137b0321be3b.6dc9470b09b39731.94b9ad022a2a2d81.0955cf58326db630
+ 0000000000000000.0000000000000000.94b9ad0294b9ad02.94b9ad0294b9ad02
+ d2ac2b02b6b945f7.a7e4b21e157abf65.d071ac2de4933ee3.620630fafd388746
+ 2e7ac852ca1c7c18.f4599244f41948da.e321bfff87368d96.19ac2e37e650588a
+ 5242afa1a29868da
+
+VPERMILPS_128_0x30(reg)
+ before
+ 6a12afa4cc9ff4e1.81611491d64a4ff5.3022330c33ef6f70.bfc28489d3dd5a30
+ bb692aac01ee384c.a72b8daaf54e7bbb.b98c91e46f896fd3.402178b7e59563dc
+ a2931d25dc136fc7.7da5ae894435bc96.eae3a938437285b1.42091576d96961c7
+ 7bdc827bf99ad6fd.dd9bf419de0aceb1.1f7375724c36edb4.a148d9b0ca65131c
+ 3aa93f52d4953308
+ after
+ 6a12afa4cc9ff4e1.81611491d64a4ff5.3022330c33ef6f70.bfc28489d3dd5a30
+ 0000000000000000.0000000000000000.d96961c7eae3a938.d96961c7d96961c7
+ a2931d25dc136fc7.7da5ae894435bc96.eae3a938437285b1.42091576d96961c7
+ 7bdc827bf99ad6fd.dd9bf419de0aceb1.1f7375724c36edb4.a148d9b0ca65131c
+ 3aa93f52d4953308
+VPERMILPS_128_0x30(mem)
+ before
+ e7f7c34914067eb7.a390571bf50ea99b.a4d9d948e0d96c39.b488f3ff2561e288
+ 85ffe180a6c3b054.74fb976f6bfb234c.ae2bdb0165af5359.046e1e4c6b80a1da
+ f08d16e2a4d9850c.4b683fe5f8ed81bd.d75c75318a963e3e.6d70f2c3b91e6656
+ 046ddc5d2d53b80a.842449e73771ff9a.fb3a23c26a9deb14.49dc6cd2acc86da7
+ f6fc87e3df09f17a
+ after
+ e7f7c34914067eb7.a390571bf50ea99b.a4d9d948e0d96c39.b488f3ff2561e288
+ 0000000000000000.0000000000000000.2561e2882561e288.2561e288a4d9d948
+ f08d16e2a4d9850c.4b683fe5f8ed81bd.d75c75318a963e3e.6d70f2c3b91e6656
+ 046ddc5d2d53b80a.842449e73771ff9a.fb3a23c26a9deb14.49dc6cd2acc86da7
+ f6fc87e3df09f17a
+
+VPERMILPS_128_0x30(reg)
+ before
+ cf1d3f64ee6d2f7b.9d6ab1dc5a3d067b.7b7bb3e3c512d98e.f68f61a121cd1406
+ 2f8b90c076816355.9652114b4aa42b8b.8cb978443e5c4a46.a428acbbcc347641
+ 7491766313d0c8b5.cdef76961693e265.132a95763cdc8f6d.e1d17ffa87deccf0
+ f87deeb960e69b46.1d0f5ea9dd16e836.6c1a04e55d1de4b0.8856564c6dd5d340
+ 7783ad9c9a27475c
+ after
+ cf1d3f64ee6d2f7b.9d6ab1dc5a3d067b.7b7bb3e3c512d98e.f68f61a121cd1406
+ 0000000000000000.0000000000000000.87deccf0132a9576.87deccf087deccf0
+ 7491766313d0c8b5.cdef76961693e265.132a95763cdc8f6d.e1d17ffa87deccf0
+ f87deeb960e69b46.1d0f5ea9dd16e836.6c1a04e55d1de4b0.8856564c6dd5d340
+ 7783ad9c9a27475c
+VPERMILPS_128_0x30(mem)
+ before
+ 892301d52be0e472.1999f22ef95018b5.627c4470b83af929.f3d4c3fd3dac85bb
+ 9a03cce53b0a65ab.3132812f7b987bad.7802a4d8c50ad06b.04a5cd2a7713ad39
+ 86f08cb7e7b38836.9d949426814dffdb.3b6ffacb20922b28.fbda1ed9a8e099d7
+ 28b4bc374ae7063d.ba0b2880a8f8e1eb.868ec237e4dfc48b.34bdb2746b9f8440
+ 0b9a86695cdbac21
+ after
+ 892301d52be0e472.1999f22ef95018b5.627c4470b83af929.f3d4c3fd3dac85bb
+ 0000000000000000.0000000000000000.3dac85bb3dac85bb.3dac85bb627c4470
+ 86f08cb7e7b38836.9d949426814dffdb.3b6ffacb20922b28.fbda1ed9a8e099d7
+ 28b4bc374ae7063d.ba0b2880a8f8e1eb.868ec237e4dfc48b.34bdb2746b9f8440
+ 0b9a86695cdbac21
+
+VPERMILPS_128_0x30(reg)
+ before
+ dbbf942218204b26.5e1bd95281b09eec.e2e33aaa8b275d88.372a79062efc57c0
+ 0277da0d3bfa9efa.03f35df2a71c0a70.7268c50fc766ae5f.29109a2619f5a2f5
+ db0d549560f6e04a.f207c604d93707f5.c6e5c51af73f111b.370da182c1d75f54
+ c2cefc25239f4fc1.09228f75320c51a6.3ba73639b840c26a.3feb0b0643ad4b09
+ 1b76529eba842141
+ after
+ dbbf942218204b26.5e1bd95281b09eec.e2e33aaa8b275d88.372a79062efc57c0
+ 0000000000000000.0000000000000000.c1d75f54c6e5c51a.c1d75f54c1d75f54
+ db0d549560f6e04a.f207c604d93707f5.c6e5c51af73f111b.370da182c1d75f54
+ c2cefc25239f4fc1.09228f75320c51a6.3ba73639b840c26a.3feb0b0643ad4b09
+ 1b76529eba842141
+VPERMILPS_128_0x30(mem)
+ before
+ a97cf43643669f28.1206d02b2182250c.2211342fcfa7a3b0.2bfb15d7a5f5fdf5
+ c3c76cbafa617fe9.2901cb12f62a9ed6.1ba03220cb14ba3f.f32b5d605be9fd6a
+ 47253717fa817db1.610be9473c23f8cc.ce9b03334360527e.ef830a4075a8ff75
+ 0f60cf375fd157ac.186f263492fa6d9a.19ce255452962799.7b5118e390be3fc2
+ f3e083b647b8f8fc
+ after
+ a97cf43643669f28.1206d02b2182250c.2211342fcfa7a3b0.2bfb15d7a5f5fdf5
+ 0000000000000000.0000000000000000.a5f5fdf5a5f5fdf5.a5f5fdf52211342f
+ 47253717fa817db1.610be9473c23f8cc.ce9b03334360527e.ef830a4075a8ff75
+ 0f60cf375fd157ac.186f263492fa6d9a.19ce255452962799.7b5118e390be3fc2
+ f3e083b647b8f8fc
+
+VPERMILPS_128_0x21(reg)
+ before
+ b37b4823362168cf.f945b207465dc705.a97b7f46913a3aeb.d605136e14c2f4be
+ 176f6297fa85c9e8.dfa05b74ca318ae8.6f79eeead86f9a6c.e30b4a6fa6f17616
+ 7b08cd7f2e7157f3.9e3d4669075a5b83.c8b6718a0026cac9.1aad4443242e69d0
+ 3b9285466f70509c.13e7efd11be3f8ff.0e7e0394a8e906ad.58b77fd4a9868816
+ 7af5760f51049115
+ after
+ b37b4823362168cf.f945b207465dc705.a97b7f46913a3aeb.d605136e14c2f4be
+ 0000000000000000.0000000000000000.242e69d00026cac9.242e69d01aad4443
+ 7b08cd7f2e7157f3.9e3d4669075a5b83.c8b6718a0026cac9.1aad4443242e69d0
+ 3b9285466f70509c.13e7efd11be3f8ff.0e7e0394a8e906ad.58b77fd4a9868816
+ 7af5760f51049115
+VPERMILPS_128_0x21(mem)
+ before
+ 5a33a5e139b43df8.b3598757590fee8d.186cd39a1fd91b8b.9e1da17269478ac5
+ d53d89347ca24bec.3fa8cd2087d86e75.8a966daf31478051.d5df4692e1c992bc
+ c7de9cf637db751c.3bcd550c955a0bfe.463239fc6d39e57e.0d0fed5facfd593f
+ 0ce45c11856a78b5.03121a87201e02d5.260cb36deebb043d.a3fb9445656f1cf9
+ f4ed37b0a8a91697
+ after
+ 5a33a5e139b43df8.b3598757590fee8d.186cd39a1fd91b8b.9e1da17269478ac5
+ 0000000000000000.0000000000000000.69478ac59e1da172.69478ac51fd91b8b
+ c7de9cf637db751c.3bcd550c955a0bfe.463239fc6d39e57e.0d0fed5facfd593f
+ 0ce45c11856a78b5.03121a87201e02d5.260cb36deebb043d.a3fb9445656f1cf9
+ f4ed37b0a8a91697
+
+VPERMILPS_128_0x21(reg)
+ before
+ 5a32d00c123985c5.81194473835c10e3.f2c419fdc3b28fa5.07f057efd0da9abb
+ 32165dc63faba32e.004ad0074cbcf9d1.662f4cdb1ba1ee1b.c5a9a26c30a16323
+ d8e4d948ca89ac7f.66437db9fd96eeac.ba9fb18bc3785ae3.3c050fd12a1d1aa2
+ a9ea40004f61de63.8fcfc675b1f7ac9f.4960437a57c210a8.48ce1a0bd9597c64
+ c5d13f0559614594
+ after
+ 5a32d00c123985c5.81194473835c10e3.f2c419fdc3b28fa5.07f057efd0da9abb
+ 0000000000000000.0000000000000000.2a1d1aa2c3785ae3.2a1d1aa23c050fd1
+ d8e4d948ca89ac7f.66437db9fd96eeac.ba9fb18bc3785ae3.3c050fd12a1d1aa2
+ a9ea40004f61de63.8fcfc675b1f7ac9f.4960437a57c210a8.48ce1a0bd9597c64
+ c5d13f0559614594
+VPERMILPS_128_0x21(mem)
+ before
+ 8fdafbaac742305f.ff728e586bbf7387.57bc272785eaeed7.71bdff15750b4c17
+ 82b5c9e83e07faf0.37cac0beb92ea897.9ad41cbb947b7280.8d03dfc7b6df4adb
+ 7a2d25aadbbc5f74.ad3cd19dd63ab93e.34e5211efab7f2c5.f87ee1fbb8cb45a1
+ 53108bdcb96e1b17.bd15bd605d6fe129.01b9b33ad4a82bd3.107a001f175a7a14
+ 2f43389e6e1925e1
+ after
+ 8fdafbaac742305f.ff728e586bbf7387.57bc272785eaeed7.71bdff15750b4c17
+ 0000000000000000.0000000000000000.750b4c1771bdff15.750b4c1785eaeed7
+ 7a2d25aadbbc5f74.ad3cd19dd63ab93e.34e5211efab7f2c5.f87ee1fbb8cb45a1
+ 53108bdcb96e1b17.bd15bd605d6fe129.01b9b33ad4a82bd3.107a001f175a7a14
+ 2f43389e6e1925e1
+
+VPERMILPS_128_0x21(reg)
+ before
+ b32585e4599381b4.e928776af528e904.c3a08075eb5a5d03.dd1d4dfd3e5dd8d5
+ f66ce45d7554cb38.18436640aaf68767.1b2b17471b866979.a3dc6b5153dfb6f8
+ 566350755ee93f1a.bc2bd34bf5e5ae6e.21007c428a7f4037.31c489242f3c8168
+ 2d57c598aedd1906.b0ad3a75f1001d43.316dadd3d3d220e8.62a02361ef80f550
+ 123bb6f4aeb5cddc
+ after
+ b32585e4599381b4.e928776af528e904.c3a08075eb5a5d03.dd1d4dfd3e5dd8d5
+ 0000000000000000.0000000000000000.2f3c81688a7f4037.2f3c816831c48924
+ 566350755ee93f1a.bc2bd34bf5e5ae6e.21007c428a7f4037.31c489242f3c8168
+ 2d57c598aedd1906.b0ad3a75f1001d43.316dadd3d3d220e8.62a02361ef80f550
+ 123bb6f4aeb5cddc
+VPERMILPS_128_0x21(mem)
+ before
+ 1d62bdc989e9c73a.d9943f3304bc94a7.d29417abbb538e12.a7bca564930a4339
+ 5ee1b4cc9c289c94.b466bab0fa13eda9.fdaee7da6eebbe08.df3a616265b4e5d5
+ b38418e9017d0b16.1b19337d2c6d60ba.0dc525ed26d36951.3433db3ae55b4469
+ f717630cd7f4ceed.6bf9a50437562884.dda74dcf00174a19.04f21156b08b9aa1
+ aac5fe2462d02328
+ after
+ 1d62bdc989e9c73a.d9943f3304bc94a7.d29417abbb538e12.a7bca564930a4339
+ 0000000000000000.0000000000000000.930a4339a7bca564.930a4339bb538e12
+ b38418e9017d0b16.1b19337d2c6d60ba.0dc525ed26d36951.3433db3ae55b4469
+ f717630cd7f4ceed.6bf9a50437562884.dda74dcf00174a19.04f21156b08b9aa1
+ aac5fe2462d02328
+
+VPERMILPS_128_0xD7(reg)
+ before
+ 82f69e0f96b71dab.056513223799a245.fe510cb3b65b83b3.4b1edb6e18c41e8a
+ e7d2ee83e8cbc2d5.bb3ba31540794349.316e64f54607aaf4.31f74bb589e5a1d3
+ 37a6e8ecf5994f53.f3668fd30b9f6c26.609caa3682e6dcf3.6dfd1a906f868f1e
+ cdbb8ab659ac00d0.8bb05447b617da08.e727d9e20685535b.d9fec3ebe7b4a398
+ 53c5c2b20c7a9a6c
+ after
+ 82f69e0f96b71dab.056513223799a245.fe510cb3b65b83b3.4b1edb6e18c41e8a
+ 0000000000000000.0000000000000000.609caa366dfd1a90.6dfd1a90609caa36
+ 37a6e8ecf5994f53.f3668fd30b9f6c26.609caa3682e6dcf3.6dfd1a906f868f1e
+ cdbb8ab659ac00d0.8bb05447b617da08.e727d9e20685535b.d9fec3ebe7b4a398
+ 53c5c2b20c7a9a6c
+VPERMILPS_128_0xD7(mem)
+ before
+ b51d93d2fbe430c7.0460cf4dae9010f9.5de66c5c5dee491a.225bed656f6f4cd9
+ ddd3b235d0ff20d4.3ae0b41d93d2bd7a.47d355001b2f7589.6e84e22b59300318
+ a5b39cc9a5d627c0.c9863393a1fd40fe.23458a1e0ce71980.25edb4a05f55b4c5
+ eb89cc78987601b7.0f9f4a19779dd832.cf0688a24d20f22c.a4e460311d699a8c
+ 47b3e14830f9f218
+ after
+ b51d93d2fbe430c7.0460cf4dae9010f9.5de66c5c5dee491a.225bed656f6f4cd9
+ 0000000000000000.0000000000000000.225bed655dee491a.5de66c5c6f6f4cd9
+ a5b39cc9a5d627c0.c9863393a1fd40fe.23458a1e0ce71980.25edb4a05f55b4c5
+ eb89cc78987601b7.0f9f4a19779dd832.cf0688a24d20f22c.a4e460311d699a8c
+ 47b3e14830f9f218
+
+VPERMILPS_128_0xD7(reg)
+ before
+ 6aa73353348ff816.8921be30c5ea6ae4.6678f41cae3ebfc2.25e4c978fae8bcb8
+ 680c52bdc4bae731.5c46efdc473e1d74.2c5b2d09e56d3259.02a9cb8c2e4b3251
+ 9f2e3bf17c03fc16.41c6d9673b7ed793.bb94f24bb5b66da4.432209cb05541223
+ 6a58e85df9f87371.126bfabfbcb7546c.71713d4ebca3ab4e.c21bff1f9c0f1559
+ 5c5f29760e89fa20
+ after
+ 6aa73353348ff816.8921be30c5ea6ae4.6678f41cae3ebfc2.25e4c978fae8bcb8
+ 0000000000000000.0000000000000000.bb94f24b432209cb.432209cbbb94f24b
+ 9f2e3bf17c03fc16.41c6d9673b7ed793.bb94f24bb5b66da4.432209cb05541223
+ 6a58e85df9f87371.126bfabfbcb7546c.71713d4ebca3ab4e.c21bff1f9c0f1559
+ 5c5f29760e89fa20
+VPERMILPS_128_0xD7(mem)
+ before
+ edbc04ba78cc7ba3.25d8576cd62487ed.ac02cdcfe7f44f2b.a83c0c7e96c22a04
+ 51fc0bd9f5e7550f.2cf8848ab0147636.eb57ce84d74286fe.bd435a47de9f2371
+ 65ecbabea2e34490.db056923225279fa.ab367ac8a8acb20e.0dd0231530c4d542
+ 03588d559ace0451.8d4b04a4c96dcfe3.c96a4b88773e928a.f230645429bf7a23
+ c9af1870651c4fbf
+ after
+ edbc04ba78cc7ba3.25d8576cd62487ed.ac02cdcfe7f44f2b.a83c0c7e96c22a04
+ 0000000000000000.0000000000000000.a83c0c7ee7f44f2b.ac02cdcf96c22a04
+ 65ecbabea2e34490.db056923225279fa.ab367ac8a8acb20e.0dd0231530c4d542
+ 03588d559ace0451.8d4b04a4c96dcfe3.c96a4b88773e928a.f230645429bf7a23
+ c9af1870651c4fbf
+
+VPERMILPS_128_0xD7(reg)
+ before
+ ee993bd57f6590c3.080c018afab3507f.a0164f7740eeb39d.1fc1bfb16005e09c
+ bd39c9f0132879da.50d49149dd9fe545.6fb14809246360d5.8a05512d7e0c5970
+ 93ddbe2bbef145b1.b77cb97e609d7ed0.556aebc710571337.e6037eeaed5fb934
+ cacf17f41b4b31f4.19cff5159eb9d94c.b08b321ba157076e.0f87c0d2ca0abc11
+ e15d95d3301a1d36
+ after
+ ee993bd57f6590c3.080c018afab3507f.a0164f7740eeb39d.1fc1bfb16005e09c
+ 0000000000000000.0000000000000000.556aebc7e6037eea.e6037eea556aebc7
+ 93ddbe2bbef145b1.b77cb97e609d7ed0.556aebc710571337.e6037eeaed5fb934
+ cacf17f41b4b31f4.19cff5159eb9d94c.b08b321ba157076e.0f87c0d2ca0abc11
+ e15d95d3301a1d36
+VPERMILPS_128_0xD7(mem)
+ before
+ 385178d83c9b99cd.bf5cceb6c7c2784e.529ac1fab400b0e4.db611b7372ee7927
+ f02ee5cd0997ec02.ced0e2dd5de2586c.3ea99a1abd7dc0c5.3138a13a1fa8a50e
+ e4c1599eb41cd102.53774cd57a380bf9.b9c8fa5fd53cc41a.105cc0dc4511c7ce
+ f2d74e37583605f9.aa9c090ab94fcea2.9fc360b7194a7910.d21974c580b61a14
+ d5baba616b23dc8b
+ after
+ 385178d83c9b99cd.bf5cceb6c7c2784e.529ac1fab400b0e4.db611b7372ee7927
+ 0000000000000000.0000000000000000.db611b73b400b0e4.529ac1fa72ee7927
+ e4c1599eb41cd102.53774cd57a380bf9.b9c8fa5fd53cc41a.105cc0dc4511c7ce
+ f2d74e37583605f9.aa9c090ab94fcea2.9fc360b7194a7910.d21974c580b61a14
+ d5baba616b23dc8b
+
+VPERMILPS_128_0xB5(reg)
+ before
+ 738d8d1ca2e246e0.f53a428512ef4413.2f8d16e8b7b3dc13.cb66450da4b29bd3
+ 0adce962c28197be.c9b7b072fd55497a.3e946edb0ff172f7.1b7c264d9380e68e
+ f4f4caa0668c09d2.4a1915eb3574d25d.32fe0d4f5e94ccfb.6ad2806202c1156e
+ 8e212c402b8dd9c8.532eebddd75699e6.6917efb13f2926ca.9435ce3a0c80e69e
+ 746f8cc1cdc9124b
+ after
+ 738d8d1ca2e246e0.f53a428512ef4413.2f8d16e8b7b3dc13.cb66450da4b29bd3
+ 0000000000000000.0000000000000000.5e94ccfb32fe0d4f.6ad280626ad28062
+ f4f4caa0668c09d2.4a1915eb3574d25d.32fe0d4f5e94ccfb.6ad2806202c1156e
+ 8e212c402b8dd9c8.532eebddd75699e6.6917efb13f2926ca.9435ce3a0c80e69e
+ 746f8cc1cdc9124b
+VPERMILPS_128_0xB5(mem)
+ before
+ e84c36e162a958a0.35af0cb0ac12434b.c2c0b033ff095a42.3e2b116b4e3bbb11
+ cb9a4987e62b72cb.43e9655a86a78308.729ddfd8c899d39c.0d866eeb2856c87c
+ f824409f765b1df5.151d33ac54d6d4aa.3e8ff4ba4e10be21.3273029b690689b6
+ 4db597162d46154d.07957211b32d73de.04636bc4ae7cd8fd.0840c9e9acd83a6b
+ ed37bf408d571649
+ after
+ e84c36e162a958a0.35af0cb0ac12434b.c2c0b033ff095a42.3e2b116b4e3bbb11
+ 0000000000000000.0000000000000000.3e2b116b4e3bbb11.ff095a42ff095a42
+ f824409f765b1df5.151d33ac54d6d4aa.3e8ff4ba4e10be21.3273029b690689b6
+ 4db597162d46154d.07957211b32d73de.04636bc4ae7cd8fd.0840c9e9acd83a6b
+ ed37bf408d571649
+
+VPERMILPS_128_0xB5(reg)
+ before
+ 3ca5e10ca9105afa.a41acad627f715fd.759e1ff53e389b50.9fe4c1e204e9dc5b
+ 50d62ab99b8e422a.db1f55cd817ada31.bc8435c492818aab.eae071006b628767
+ 871596b3005d0986.cc90b5e657dc2016.3693b0ea4a967a9c.c322f70afff3954f
+ 3cb02167740aecba.5539650dc428a3d8.40178cd30203a7cf.0475cfeddda8c23d
+ 8aa67693208eca5d
+ after
+ 3ca5e10ca9105afa.a41acad627f715fd.759e1ff53e389b50.9fe4c1e204e9dc5b
+ 0000000000000000.0000000000000000.4a967a9c3693b0ea.c322f70ac322f70a
+ 871596b3005d0986.cc90b5e657dc2016.3693b0ea4a967a9c.c322f70afff3954f
+ 3cb02167740aecba.5539650dc428a3d8.40178cd30203a7cf.0475cfeddda8c23d
+ 8aa67693208eca5d
+VPERMILPS_128_0xB5(mem)
+ before
+ 328166eae5b068dc.caf1c83f911f2771.50e6e12ee56b1ea2.365bc5eb57534fef
+ d6d21ddc471b59e6.8f2686a8f62bf658.9b62a535d5af4ea1.74ac589fe512aca8
+ 5465175763d958a6.e599570f3cb7941b.107a2e0eb003ef00.5657405947ccfba7
+ 8605ce4654f82349.2a9737de01513e65.8cfaf7a59370bcec.38a67987190e7898
+ 76e6ff93f8635e26
+ after
+ 328166eae5b068dc.caf1c83f911f2771.50e6e12ee56b1ea2.365bc5eb57534fef
+ 0000000000000000.0000000000000000.365bc5eb57534fef.e56b1ea2e56b1ea2
+ 5465175763d958a6.e599570f3cb7941b.107a2e0eb003ef00.5657405947ccfba7
+ 8605ce4654f82349.2a9737de01513e65.8cfaf7a59370bcec.38a67987190e7898
+ 76e6ff93f8635e26
+
+VPERMILPS_128_0xB5(reg)
+ before
+ 6c62cfeb8057eafe.4980c095378474fa.b86c2283e18530e2.ecae7ce699047391
+ 7668e4fa4b7758cc.79a0672f278807e6.ec63156977dda540.0a6239bedfcacd1a
+ ef42392cf84ee43b.f332410340109a39.23ca0bfc60e7da29.c3e2aa1781cf89b4
+ 353ecded2069c9f8.9102cafa9f29e71e.b7eb00a8372f0b49.f3f94cdf991e618b
+ 77759a0146c312ca
+ after
+ 6c62cfeb8057eafe.4980c095378474fa.b86c2283e18530e2.ecae7ce699047391
+ 0000000000000000.0000000000000000.60e7da2923ca0bfc.c3e2aa17c3e2aa17
+ ef42392cf84ee43b.f332410340109a39.23ca0bfc60e7da29.c3e2aa1781cf89b4
+ 353ecded2069c9f8.9102cafa9f29e71e.b7eb00a8372f0b49.f3f94cdf991e618b
+ 77759a0146c312ca
+VPERMILPS_128_0xB5(mem)
+ before
+ 29201068a1ca589d.a3a699a9625344ae.30dc7c0160ddabc2.0513f0d9983f744d
+ e6c72a02c940ef31.95c79bcc5798900a.ac8bd5049e3ba250.6a8ed7fb20a550e1
+ 8a3665bad73092b2.66eccec39ec4ebb8.e1dd50f0754c87f5.40a8b27a6beddcb0
+ f1393b7ce9a7fe4c.74632ef8d0648f63.ab9c69af021e17dd.e4ad7cc314a15467
+ b2e83140b74ff3b1
+ after
+ 29201068a1ca589d.a3a699a9625344ae.30dc7c0160ddabc2.0513f0d9983f744d
+ 0000000000000000.0000000000000000.0513f0d9983f744d.60ddabc260ddabc2
+ 8a3665bad73092b2.66eccec39ec4ebb8.e1dd50f0754c87f5.40a8b27a6beddcb0
+ f1393b7ce9a7fe4c.74632ef8d0648f63.ab9c69af021e17dd.e4ad7cc314a15467
+ b2e83140b74ff3b1
+
+VPERMILPS_128_0x85(reg)
+ before
+ 06a7ce5ff183f73b.f79b2a341bb0ee2a.1a77b7d98b04b9b8.e6959c2f61bc0e33
+ 3c344d8a5dc799b1.7829aecf88572078.b37365d06b2ea462.6e94665aac332724
+ b0dcac2f98a918be.50b041374da94e63.9da4354b0b708e0e.1f65411e028e1fdb
+ bfebe6b93db5ae0f.5bfa615985b13517.335622b50855b167.d5d4ab667dd9b285
+ 6cac201e39219c4e
+ after
+ 06a7ce5ff183f73b.f79b2a341bb0ee2a.1a77b7d98b04b9b8.e6959c2f61bc0e33
+ 0000000000000000.0000000000000000.0b708e0e028e1fdb.1f65411e1f65411e
+ b0dcac2f98a918be.50b041374da94e63.9da4354b0b708e0e.1f65411e028e1fdb
+ bfebe6b93db5ae0f.5bfa615985b13517.335622b50855b167.d5d4ab667dd9b285
+ 6cac201e39219c4e
+VPERMILPS_128_0x85(mem)
+ before
+ c0ba1a3253719861.c3adf794e976994f.75d488224c7b90c0.d0d5287afd6a491a
+ adcb178ee6d564eb.196ddc2c3778122b.7a0a347dbf141c88.d26d4306863a94d3
+ 0fa9921f0e5ab917.1c7990edc447584f.4567e155fa87959e.936970c54051cc3d
+ c12107cfe80b5612.2a1b0e432b70a566.b4b9099817e0b72c.7017aa23c63c2e05
+ c6c1ed8cb586f5d7
+ after
+ c0ba1a3253719861.c3adf794e976994f.75d488224c7b90c0.d0d5287afd6a491a
+ 0000000000000000.0000000000000000.75d48822d0d5287a.75d48822fd6a491a
+ 0fa9921f0e5ab917.1c7990edc447584f.4567e155fa87959e.936970c54051cc3d
+ c12107cfe80b5612.2a1b0e432b70a566.b4b9099817e0b72c.7017aa23c63c2e05
+ c6c1ed8cb586f5d7
+
+VPERMILPS_128_0x85(reg)
+ before
+ efb4356ca9bb5f5e.a1fef28c90f4f508.9ea0559b097e361d.a2ca2a31352c3d5f
+ 493c7f303c68a646.8a0ed04021225324.d4545e5ff9fe471f.eb67bf0c6e76e562
+ 2ea4c5420d18063d.581b1bd9b8a02c93.288326fd977a1319.6a5c4415deca6862
+ fb3a0510b557bdec.e6f35141707a3b80.f679aadf8081d7b7.fd753538a235858b
+ 7f7e0f62d5c2f608
+ after
+ efb4356ca9bb5f5e.a1fef28c90f4f508.9ea0559b097e361d.a2ca2a31352c3d5f
+ 0000000000000000.0000000000000000.977a1319deca6862.6a5c44156a5c4415
+ 2ea4c5420d18063d.581b1bd9b8a02c93.288326fd977a1319.6a5c4415deca6862
+ fb3a0510b557bdec.e6f35141707a3b80.f679aadf8081d7b7.fd753538a235858b
+ 7f7e0f62d5c2f608
+VPERMILPS_128_0x85(mem)
+ before
+ cb424d7d947d7806.0c493a05d3b20502.1260ed6665bd3d18.9981e573509ccfa4
+ bf8f6b76fa73c7b0.be1c618d00b41b29.b62f6c33b474ee86.6fe9d424a259378c
+ 352fe53a24af9e33.6b007414dbe93b0e.b02b489479ab0af7.d3fb715d12434a1d
+ 0bef37b42d3dbaba.70417106fddea05c.db22ff75ce6f4c97.2104ba8c3de74501
+ b450a91cbed063e4
+ after
+ cb424d7d947d7806.0c493a05d3b20502.1260ed6665bd3d18.9981e573509ccfa4
+ 0000000000000000.0000000000000000.1260ed669981e573.1260ed66509ccfa4
+ 352fe53a24af9e33.6b007414dbe93b0e.b02b489479ab0af7.d3fb715d12434a1d
+ 0bef37b42d3dbaba.70417106fddea05c.db22ff75ce6f4c97.2104ba8c3de74501
+ b450a91cbed063e4
+
+VPERMILPS_128_0x85(reg)
+ before
+ ea2b3d7a328ae273.1b9bdecf312ad772.292b53cf041e87c0.12df0cc3d2cb7191
+ 1de06f1034a1fc5a.43fe55794d81b187.f20916db8c352ce5.332dec689fcc3512
+ abbd3c4b61a2ee44.5de6189d9d4f0324.2729b79630b0ca78.18d91951517d5346
+ ee0ca1985419f3de.471ea3273c9f8a76.24d5306d8c1a9e25.9eaf116b05ea8858
+ a27b4fa0d61f9075
+ after
+ ea2b3d7a328ae273.1b9bdecf312ad772.292b53cf041e87c0.12df0cc3d2cb7191
+ 0000000000000000.0000000000000000.30b0ca78517d5346.18d9195118d91951
+ abbd3c4b61a2ee44.5de6189d9d4f0324.2729b79630b0ca78.18d91951517d5346
+ ee0ca1985419f3de.471ea3273c9f8a76.24d5306d8c1a9e25.9eaf116b05ea8858
+ a27b4fa0d61f9075
+VPERMILPS_128_0x85(mem)
+ before
+ fe094fdee12927c8.441a9961aa9049d4.db717303467d02a9.455a7fca3dffe497
+ 8f248d104113087e.07332014fe952ad1.f6ac031ed8f526e8.e6059f1bdfecd87b
+ 329a862212eaf0c2.95a3331bedb3d281.759bcf620e14b35f.631f8cca0d6cb57c
+ c135b50071b99bc1.48b6cce412777f92.320a53bc02e5653c.18f74345630cb847
+ 61d8bff77e571d87
+ after
+ fe094fdee12927c8.441a9961aa9049d4.db717303467d02a9.455a7fca3dffe497
+ 0000000000000000.0000000000000000.db717303455a7fca.db7173033dffe497
+ 329a862212eaf0c2.95a3331bedb3d281.759bcf620e14b35f.631f8cca0d6cb57c
+ c135b50071b99bc1.48b6cce412777f92.320a53bc02e5653c.18f74345630cb847
+ 61d8bff77e571d87
+
+VPERMILPS_128_0x29(reg)
+ before
+ 9a0dfc4cf9d920ea.19c296967a8cc4a7.7eb7e9da0a6c6bae.0ac40b19d375f8a8
+ 1ee3f6b0711efc19.160da5d0486f299f.91f38569701ed381.d99774639bcf27d2
+ 4ba6a98f81b3eec3.95e25e9af86f83d6.deb79dfde01af3b8.7c4d098876ffafe4
+ 7ca21255c6233292.700c3ee0a5979177.c14d2b02f7eb06ff.cdb3467381114c0a
+ a995a710d712ba72
+ after
+ 9a0dfc4cf9d920ea.19c296967a8cc4a7.7eb7e9da0a6c6bae.0ac40b19d375f8a8
+ 0000000000000000.0000000000000000.76ffafe4e01af3b8.e01af3b87c4d0988
+ 4ba6a98f81b3eec3.95e25e9af86f83d6.deb79dfde01af3b8.7c4d098876ffafe4
+ 7ca21255c6233292.700c3ee0a5979177.c14d2b02f7eb06ff.cdb3467381114c0a
+ a995a710d712ba72
+VPERMILPS_128_0x29(mem)
+ before
+ ecbfa94b940eb445.0d232c6fdbfb0332.8459c08f6bf40daf.97012de5511d4901
+ 72fdc610d60ff7b2.5975f3475dc69e50.ad9360916791b4aa.ba219e10893df86b
+ 171b7c4bb6233ee3.bee3634ae7103f98.c7879ad4b47a4293.87f87af13bd64ee8
+ b7e446e852554704.97bb78e5156622b5.ae01eb436fbc7397.5ad1bdf204758825
+ 8ff964817fa4e2ce
+ after
+ ecbfa94b940eb445.0d232c6fdbfb0332.8459c08f6bf40daf.97012de5511d4901
+ 0000000000000000.0000000000000000.6bf40daf97012de5.511d49016bf40daf
+ 171b7c4bb6233ee3.bee3634ae7103f98.c7879ad4b47a4293.87f87af13bd64ee8
+ b7e446e852554704.97bb78e5156622b5.ae01eb436fbc7397.5ad1bdf204758825
+ 8ff964817fa4e2ce
+
+VPERMILPS_128_0x29(reg)
+ before
+ 82bc6a0949f1988e.2e25a1d4c6b2cc43.3f472f8385528254.3ecdcec9b36202e1
+ 8f66cbf5fde8e512.58aa07f92d458ac9.14d48390d0639c21.53b7bf549d78ac9e
+ 124383b338140605.113ff645a31a3cc5.70ae70779422acc7.c98a3acf480b2dfa
+ 679f8eae95013714.35b0e9a2453e9f61.b120f3a66c1dedf2.7c13bb26d1254020
+ 471fbf4653d5a23d
+ after
+ 82bc6a0949f1988e.2e25a1d4c6b2cc43.3f472f8385528254.3ecdcec9b36202e1
+ 0000000000000000.0000000000000000.480b2dfa9422acc7.9422acc7c98a3acf
+ 124383b338140605.113ff645a31a3cc5.70ae70779422acc7.c98a3acf480b2dfa
+ 679f8eae95013714.35b0e9a2453e9f61.b120f3a66c1dedf2.7c13bb26d1254020
+ 471fbf4653d5a23d
+VPERMILPS_128_0x29(mem)
+ before
+ 0878c119eb240f7c.eac5e952b13bb4eb.9fc95dfe2fbc6fc9.31780688f5df9c50
+ 9aeb3d8cb420420a.f7038f0c274fb835.2d55cc447ca0682a.4e00a78acbf5f58b
+ d943af8ccbd5f912.eaa37c4694c8809f.ba21b46048f745b0.6206d11689ea344f
+ a04e94034b4eeec2.1ff2ad6d933347d4.22fa903eb0ccc386.cbd48099cb4a9449
+ e3b6b1802ea25225
+ after
+ 0878c119eb240f7c.eac5e952b13bb4eb.9fc95dfe2fbc6fc9.31780688f5df9c50
+ 0000000000000000.0000000000000000.2fbc6fc931780688.f5df9c502fbc6fc9
+ d943af8ccbd5f912.eaa37c4694c8809f.ba21b46048f745b0.6206d11689ea344f
+ a04e94034b4eeec2.1ff2ad6d933347d4.22fa903eb0ccc386.cbd48099cb4a9449
+ e3b6b1802ea25225
+
+VPERMILPS_128_0x29(reg)
+ before
+ 07fa5e354d7daa8e.cdd667df5097dd43.f23c1ceec01a4b81.40aadccacf2b9ed9
+ 93eb8526c567d731.3ba9a40bf7bc84c4.bfccc733b80cc652.f2fd14f0c22192d5
+ e4d421be31ed16b9.c591c7725cca9d6f.e1f0a9aa1792f5f2.13c1b59ca4b95aa5
+ 54032f682e9aa3d3.495b4c029acce570.b6f2bebe783a130d.7ec139bb92ffb376
+ 11c81e37a7005973
+ after
+ 07fa5e354d7daa8e.cdd667df5097dd43.f23c1ceec01a4b81.40aadccacf2b9ed9
+ 0000000000000000.0000000000000000.a4b95aa51792f5f2.1792f5f213c1b59c
+ e4d421be31ed16b9.c591c7725cca9d6f.e1f0a9aa1792f5f2.13c1b59ca4b95aa5
+ 54032f682e9aa3d3.495b4c029acce570.b6f2bebe783a130d.7ec139bb92ffb376
+ 11c81e37a7005973
+VPERMILPS_128_0x29(mem)
+ before
+ a7a3e0fe00c707c9.40c2a99257faba2b.a2d2b0a6cdce17f4.991f03db778f5e51
+ 1b1ef9fab8617aa3.045e8da7499a966c.abc46e4a12ddf027.e5c3726db11e0f68
+ 4b05e719ebd86e2f.fc23d6139f057443.42fc02db84042c34.f82a09e0c17265fe
+ 11242546b63b9f96.845c8043f5c8905b.4145e843404f8748.2da0c3a044179bc0
+ df719d19d599ec5a
+ after
+ a7a3e0fe00c707c9.40c2a99257faba2b.a2d2b0a6cdce17f4.991f03db778f5e51
+ 0000000000000000.0000000000000000.cdce17f4991f03db.778f5e51cdce17f4
+ 4b05e719ebd86e2f.fc23d6139f057443.42fc02db84042c34.f82a09e0c17265fe
+ 11242546b63b9f96.845c8043f5c8905b.4145e843404f8748.2da0c3a044179bc0
+ df719d19d599ec5a
+
+VBLENDPS_128_1of3(reg)
+ before
+ 6ce891b811859577.4a472f6d3593c806.f85788a1e86d2561.866c9d6f62cbbd8e
+ 2e529de79367d1c4.d339817a83eea6ab.b55ee89a14827101.eb3d9b4c04838934
+ 83fbbc13f8c9dded.86c79859bc57f5b1.14be9e9b1493aee6.4d8460c44584a863
+ c52feaa9db39f59d.40bdeef6fdda7043.74c3a50e842b18bd.890d67c53ed9d549
+ 79a32d3a0d8ece12
+ after
+ 0000000000000000.0000000000000000.b55ee89a14827101.eb3d9b4c04838934
+ 2e529de79367d1c4.d339817a83eea6ab.b55ee89a14827101.eb3d9b4c04838934
+ 83fbbc13f8c9dded.86c79859bc57f5b1.14be9e9b1493aee6.4d8460c44584a863
+ c52feaa9db39f59d.40bdeef6fdda7043.74c3a50e842b18bd.890d67c53ed9d549
+ 79a32d3a0d8ece12
+VBLENDPS_128_1of3(mem)
+ before
+ fa142c0fceaf4dea.523a2314d9425580.dee7013d6284d48d.30b9fa6101d6ed31
+ e92ae2309c490efc.846864c08d713944.3a114d1b0660ddbd.a4ec97ff262067ef
+ 20b2ca899467cf74.b804a8199451dc93.31074c7a057b47fd.2ca77a549096c2a3
+ 7c786006d1164a80.4b5ceb8b896e7b19.9f947c487ce0cd79.24389eccdbc33cf8
+ e8e9ffd3a1340f9b
+ after
+ fa142c0fceaf4dea.523a2314d9425580.dee7013d6284d48d.30b9fa6101d6ed31
+ e92ae2309c490efc.846864c08d713944.3a114d1b0660ddbd.a4ec97ff262067ef
+ 0000000000000000.0000000000000000.3a114d1b0660ddbd.30b9fa6101d6ed31
+ 7c786006d1164a80.4b5ceb8b896e7b19.9f947c487ce0cd79.24389eccdbc33cf8
+ e8e9ffd3a1340f9b
+
+VBLENDPS_128_1of3(reg)
+ before
+ d40799d581747837.d94821936f613c49.97ba298208555183.61865870869b2c5e
+ 43de693e140fb379.13ed871c8b5461fe.f96b5f6aae919c7d.51a75cdd40b920d8
+ 93ba6a7af991fb0d.0635108e41fc74c9.cdbb87af17ae96b2.4cc4047dc5446512
+ 1fe798f6c9878d9e.8eea38d3ac6332d7.70f59fbdde397bcf.2ea9cc3b324bb639
+ d3223103a2d7d078
+ after
+ 0000000000000000.0000000000000000.f96b5f6aae919c7d.51a75cdd40b920d8
+ 43de693e140fb379.13ed871c8b5461fe.f96b5f6aae919c7d.51a75cdd40b920d8
+ 93ba6a7af991fb0d.0635108e41fc74c9.cdbb87af17ae96b2.4cc4047dc5446512
+ 1fe798f6c9878d9e.8eea38d3ac6332d7.70f59fbdde397bcf.2ea9cc3b324bb639
+ d3223103a2d7d078
+VBLENDPS_128_1of3(mem)
+ before
+ 17faaec231f66efc.42b0ef1c227ca5d8.87d979d9e8985753.3c67a3019fbd897f
+ d6ffbf62fdb34ef1.5a626c5aa0fd7f69.cdce508b12a49e69.8e5b8de5f7c6fa6f
+ ecfbe1d01f1b2a82.c24a091bde9556fb.3c953ad44595c447.c21f5bd781e10b4b
+ 35bb8ef9b539bfdc.d5b2c4ca78d0673a.b0fab2a29e778517.34fd0742da99f8be
+ 40428f929d7bfc75
+ after
+ 17faaec231f66efc.42b0ef1c227ca5d8.87d979d9e8985753.3c67a3019fbd897f
+ d6ffbf62fdb34ef1.5a626c5aa0fd7f69.cdce508b12a49e69.8e5b8de5f7c6fa6f
+ 0000000000000000.0000000000000000.cdce508b12a49e69.3c67a3019fbd897f
+ 35bb8ef9b539bfdc.d5b2c4ca78d0673a.b0fab2a29e778517.34fd0742da99f8be
+ 40428f929d7bfc75
+
+VBLENDPS_128_1of3(reg)
+ before
+ 4239ef336711541b.8d0b44c7db19c82a.f1e698d50b3beed3.05c834e038549d05
+ 96302191d3ea3c5d.d0b77e28acc80299.703482a733612672.17cc3d7a303ac73f
+ 987123187e8fefe7.da8ab80644512954.b0e77cac8bce4cc2.c2d3475da134c0ee
+ a44af034038eab64.86526f4fc0c0f989.0b4a8450af0e9c70.e2a7d073a84f4441
+ 531553a960960f62
+ after
+ 0000000000000000.0000000000000000.703482a733612672.17cc3d7a303ac73f
+ 96302191d3ea3c5d.d0b77e28acc80299.703482a733612672.17cc3d7a303ac73f
+ 987123187e8fefe7.da8ab80644512954.b0e77cac8bce4cc2.c2d3475da134c0ee
+ a44af034038eab64.86526f4fc0c0f989.0b4a8450af0e9c70.e2a7d073a84f4441
+ 531553a960960f62
+VBLENDPS_128_1of3(mem)
+ before
+ f0e84dece515dc7d.16058451ff72a981.b2d91eee3b222d61.deaa95003cae5228
+ 97ee382655d968bf.4aefdbdc0dc728e9.39ec40cfd282820b.8653ab26cd3aa995
+ 23f19245c9ed6f54.9c54f23fc91a6349.f75754dea0ecb4b1.5d91c330ff3cde63
+ 6fbfd6345f5eac67.677fc4e8d0f6954c.c7e6d307c26d7f7f.c0b0d7886e422d40
+ 0cfce59cb4d8d1d5
+ after
+ f0e84dece515dc7d.16058451ff72a981.b2d91eee3b222d61.deaa95003cae5228
+ 97ee382655d968bf.4aefdbdc0dc728e9.39ec40cfd282820b.8653ab26cd3aa995
+ 0000000000000000.0000000000000000.39ec40cfd282820b.deaa95003cae5228
+ 6fbfd6345f5eac67.677fc4e8d0f6954c.c7e6d307c26d7f7f.c0b0d7886e422d40
+ 0cfce59cb4d8d1d5
+
+VBLENDPS_128_2of3(reg)
+ before
+ 9bc0e8d6708808d1.592280de3336dc25.09be4d41bee8faa0.87653b3753109ea2
+ ca49dda43be00bde.bce70d315f83bbba.dd5b89b82e7bd0ee.119f065870e2ce46
+ f5e3be71b36c19a8.73d9f71802510551.3fa474b8bc3b51e5.4362b25834edcb96
+ 79da89a974b76cdd.5cc6bc8036ab7517.8ae30bad05b5ba2f.f878bb21bc3f50bf
+ 0bae9ba123e41aed
+ after
+ 0000000000000000.0000000000000000.dd5b89b8bc3b51e5.4362b25870e2ce46
+ ca49dda43be00bde.bce70d315f83bbba.dd5b89b82e7bd0ee.119f065870e2ce46
+ f5e3be71b36c19a8.73d9f71802510551.3fa474b8bc3b51e5.4362b25834edcb96
+ 79da89a974b76cdd.5cc6bc8036ab7517.8ae30bad05b5ba2f.f878bb21bc3f50bf
+ 0bae9ba123e41aed
+VBLENDPS_128_2of3(mem)
+ before
+ 5ad0d0c386e7e54b.b07a39b8194d4126.5179d753179dc837.1c654903a4734778
+ bfaad57200546d05.f70fca0b3fbad432.30bdc47ec233bade.4f752a263604336d
+ 1707269cad376d49.aae4390c818b61ab.d35f00ed527a0637.8161aa8356f1bbba
+ 3fb53f2caa9da241.254780287b4b233d.182b068de47d696f.0d73c684a1c81b0a
+ 4ef97896b2148f0a
+ after
+ 5ad0d0c386e7e54b.b07a39b8194d4126.5179d753179dc837.1c654903a4734778
+ bfaad57200546d05.f70fca0b3fbad432.30bdc47ec233bade.4f752a263604336d
+ 0000000000000000.0000000000000000.5179d753c233bade.4f752a26a4734778
+ 3fb53f2caa9da241.254780287b4b233d.182b068de47d696f.0d73c684a1c81b0a
+ 4ef97896b2148f0a
+
+VBLENDPS_128_2of3(reg)
+ before
+ a23dbe2626625266.117e9d0f1391c819.c4829dccca865796.d9ed524893489fb2
+ 638c949e983da1c9.6b2fba2f03209afe.e3e28b620ac9385f.f371600c7ce8642b
+ ee31f46ca531b8df.279414799654d51c.deb34758d59f0447.4382acc4ba687307
+ a07adcfbe8cbd256.227927d9e93c359e.1141cb19ca95f5f8.a3eeb35c6ad58971
+ f07fefc0a73a6297
+ after
+ 0000000000000000.0000000000000000.e3e28b62d59f0447.4382acc47ce8642b
+ 638c949e983da1c9.6b2fba2f03209afe.e3e28b620ac9385f.f371600c7ce8642b
+ ee31f46ca531b8df.279414799654d51c.deb34758d59f0447.4382acc4ba687307
+ a07adcfbe8cbd256.227927d9e93c359e.1141cb19ca95f5f8.a3eeb35c6ad58971
+ f07fefc0a73a6297
+VBLENDPS_128_2of3(mem)
+ before
+ 0602dedc8da3b9a2.d3b246b7fe962dd7.38a96d3c17e176b1.d7d715118335481e
+ c243fc9c391d4bc0.e424310c821e0211.46f2648d3d515380.8ec320ab9c0e3867
+ fe0ec3ecc7b2d41d.301d966610f090ae.261e86b776978938.914fe856b2a9027c
+ 972eb1b8527110e5.11e972314597115b.b5fa51a8dfc0d405.3cc8697b6094e20c
+ eb7aa087435a14c1
+ after
+ 0602dedc8da3b9a2.d3b246b7fe962dd7.38a96d3c17e176b1.d7d715118335481e
+ c243fc9c391d4bc0.e424310c821e0211.46f2648d3d515380.8ec320ab9c0e3867
+ 0000000000000000.0000000000000000.38a96d3c3d515380.8ec320ab8335481e
+ 972eb1b8527110e5.11e972314597115b.b5fa51a8dfc0d405.3cc8697b6094e20c
+ eb7aa087435a14c1
+
+VBLENDPS_128_2of3(reg)
+ before
+ f9b188e6f688d447.697141edf663ba43.e4d4c2d9bd9fc2c3.cf52414b93d7f012
+ c4b81d0516a95d4b.50a1ef75d0968f63.052a81cb1295df93.50f2d08cafe8988c
+ a7dd5b4e3e49eb79.288b373efc154b72.d136ab71e304a476.14a67c574eff899e
+ fd6a3f2f0af4bc7c.cdfb963394edaa9c.a2463d39ca784c19.f73ac0988d297e75
+ d579183b8772353d
+ after
+ 0000000000000000.0000000000000000.052a81cbe304a476.14a67c57afe8988c
+ c4b81d0516a95d4b.50a1ef75d0968f63.052a81cb1295df93.50f2d08cafe8988c
+ a7dd5b4e3e49eb79.288b373efc154b72.d136ab71e304a476.14a67c574eff899e
+ fd6a3f2f0af4bc7c.cdfb963394edaa9c.a2463d39ca784c19.f73ac0988d297e75
+ d579183b8772353d
+VBLENDPS_128_2of3(mem)
+ before
+ 8a30012d58e46821.24acc31217370a01.1bbd8740b729670d.d5a4318d637e1428
+ f22bf5581d8dd44e.76efe565019d12b4.ee9d86507fd53ff0.c69d85db4ba1374e
+ e93672aaf27934ef.517fa09363b31040.22660f5108feee71.d17d348e1d6ef338
+ 4b1df30df2b24531.0fa8f108d9043f51.93e59e2f6faf2fbd.52903a12766f8291
+ a52194d3f1322106
+ after
+ 8a30012d58e46821.24acc31217370a01.1bbd8740b729670d.d5a4318d637e1428
+ f22bf5581d8dd44e.76efe565019d12b4.ee9d86507fd53ff0.c69d85db4ba1374e
+ 0000000000000000.0000000000000000.1bbd87407fd53ff0.c69d85db637e1428
+ 4b1df30df2b24531.0fa8f108d9043f51.93e59e2f6faf2fbd.52903a12766f8291
+ a52194d3f1322106
+
+VBLENDPS_128_3of3(reg)
+ before
+ 267e3c3d2b430b43.f4acf46f3946c340.0eb5d230001cdd95.1de7b0d4cff4bf00
+ 31f130bcbf2d7df3.bfaef2bbe4406a47.a8f44177748823b6.9b36c02d44da5a65
+ 22c76bbd497cb3c3.8af167dd0eadf573.3baf394ad0d35060.eb9f4a26ec6cbb19
+ 554ceaaa67bce95e.303fd1c1d49821ef.2133b613b0899e40.e8edcaace0b6a048
+ 6eeebda93ec5c31d
+ after
+ 0000000000000000.0000000000000000.3baf394ad0d35060.9b36c02d44da5a65
+ 31f130bcbf2d7df3.bfaef2bbe4406a47.a8f44177748823b6.9b36c02d44da5a65
+ 22c76bbd497cb3c3.8af167dd0eadf573.3baf394ad0d35060.eb9f4a26ec6cbb19
+ 554ceaaa67bce95e.303fd1c1d49821ef.2133b613b0899e40.e8edcaace0b6a048
+ 6eeebda93ec5c31d
+VBLENDPS_128_3of3(mem)
+ before
+ 586c9d0b22a4e0c5.25cca7f1b27a5a71.8d65ab53520eaae8.b7ccb53fb1374a02
+ 8435e8bda75fb56b.f093a0fcc84143a7.7c2f727fa2194c89.5ac6313b6e689051
+ cd131aabe903fc3c.11ecd039459ee0ae.db68a031e3c7c2ff.646c257284a8acda
+ 0ed3adc0059b7263.e4253313c31c6d2f.84deb3562e24c976.320c904f8e84d948
+ 20f06b4029875448
+ after
+ 586c9d0b22a4e0c5.25cca7f1b27a5a71.8d65ab53520eaae8.b7ccb53fb1374a02
+ 8435e8bda75fb56b.f093a0fcc84143a7.7c2f727fa2194c89.5ac6313b6e689051
+ 0000000000000000.0000000000000000.8d65ab53520eaae8.b7ccb53fb1374a02
+ 0ed3adc0059b7263.e4253313c31c6d2f.84deb3562e24c976.320c904f8e84d948
+ 20f06b4029875448
+
+VBLENDPS_128_3of3(reg)
+ before
+ 8b65b3b0f03d5886.25401fea1733d20e.c488c6f5e14725d9.555b26d8a13a1d19
+ cdb7650b7f3323ad.ec28ea1539d8d966.0f62834d39ab4556.29ac75a558187915
+ 43327cbd74f4ef6a.41568c2b8a95439a.20ff688667d50952.db9d1da76ec79a96
+ 4922f432680cf868.fe9581192477ccd3.52ab700d0851ac7a.49fa99cc00553cc7
+ 4d8f64ff29cd1bd5
+ after
+ 0000000000000000.0000000000000000.20ff688667d50952.29ac75a558187915
+ cdb7650b7f3323ad.ec28ea1539d8d966.0f62834d39ab4556.29ac75a558187915
+ 43327cbd74f4ef6a.41568c2b8a95439a.20ff688667d50952.db9d1da76ec79a96
+ 4922f432680cf868.fe9581192477ccd3.52ab700d0851ac7a.49fa99cc00553cc7
+ 4d8f64ff29cd1bd5
+VBLENDPS_128_3of3(mem)
+ before
+ c528fd2c053bf2eb.3bd2cad7f9087c54.01b243cb23893040.03b1984cb7a96b7a
+ 8b90dd3fb1ac7e36.7590f916c373b5da.2479502ea4d72a0b.8d5fdab0116b82fd
+ 7c948124492b7be1.53a67c5c61dae0a5.44b6232dc26d7761.4eff34a6b1222db0
+ 750066c7e8c5a419.316151166fc73962.3e3538b39a58d26d.a0dea198345ba73f
+ e1481df435a12d55
+ after
+ c528fd2c053bf2eb.3bd2cad7f9087c54.01b243cb23893040.03b1984cb7a96b7a
+ 8b90dd3fb1ac7e36.7590f916c373b5da.2479502ea4d72a0b.8d5fdab0116b82fd
+ 0000000000000000.0000000000000000.01b243cb23893040.03b1984cb7a96b7a
+ 750066c7e8c5a419.316151166fc73962.3e3538b39a58d26d.a0dea198345ba73f
+ e1481df435a12d55
+
+VBLENDPS_128_3of3(reg)
+ before
+ 6b89a5245180fb9e.50a00715aa85b60a.6b0d74af8ac9fbbc.ecc10bae47a3f95c
+ 9cec339623854cc8.ea40e0f8ac776ddf.5df5df924d696360.2b281909e55ba659
+ cebfc5b5473b5d7c.1fac6e5e09a785c5.6367902d5535adfa.d834ddb0918a9591
+ 5e4c56ed5b2e6a69.ccaf2b31de22b9e7.d9ad82eb3db81435.cdb2d38f673f8430
+ e76e779282832d61
+ after
+ 0000000000000000.0000000000000000.6367902d5535adfa.2b281909e55ba659
+ 9cec339623854cc8.ea40e0f8ac776ddf.5df5df924d696360.2b281909e55ba659
+ cebfc5b5473b5d7c.1fac6e5e09a785c5.6367902d5535adfa.d834ddb0918a9591
+ 5e4c56ed5b2e6a69.ccaf2b31de22b9e7.d9ad82eb3db81435.cdb2d38f673f8430
+ e76e779282832d61
+VBLENDPS_128_3of3(mem)
+ before
+ 023446a5ff644d51.a9e0e2aaf8ebaf39.cb17955f46f3c672.1a15b138a27fd6be
+ facfbab5f9eda02b.09c76658bcfd6799.f9ae27d35e276892.84e91a801f142d40
+ ab0d51ac8c2be11c.db4ddd6442f0cf34.32415e7941c95b72.7276b73051065568
+ f2b88678d529cd50.7bbe4338275123b7.529cb43c0ce55a3f.400886b2d3de8ce2
+ 49ea8273422a0c59
+ after
+ 023446a5ff644d51.a9e0e2aaf8ebaf39.cb17955f46f3c672.1a15b138a27fd6be
+ facfbab5f9eda02b.09c76658bcfd6799.f9ae27d35e276892.84e91a801f142d40
+ 0000000000000000.0000000000000000.cb17955f46f3c672.1a15b138a27fd6be
+ f2b88678d529cd50.7bbe4338275123b7.529cb43c0ce55a3f.400886b2d3de8ce2
+ 49ea8273422a0c59
+
+VBLENDPD_128_1of2(reg)
+ before
+ eb6aa7e039751279.a99dd603eff320f2.4566944207ab9ecd.358ba70bda882224
+ 81d2f264554cd9f0.ad88bb3bf796952f.9690ccec7d8a7e23.b7d9b2cfc8bd6e4e
+ 666f5d6a313a9f68.da45b30b081de932.c889e8a4257bfc65.b4545175f190fce9
+ f88de66069cb9e8d.0ba0395f3f94d828.389de3d59c09573e.08c600e9710d8620
+ 8ffc3c186541c920
+ after
+ 0000000000000000.0000000000000000.9690ccec7d8a7e23.b7d9b2cfc8bd6e4e
+ 81d2f264554cd9f0.ad88bb3bf796952f.9690ccec7d8a7e23.b7d9b2cfc8bd6e4e
+ 666f5d6a313a9f68.da45b30b081de932.c889e8a4257bfc65.b4545175f190fce9
+ f88de66069cb9e8d.0ba0395f3f94d828.389de3d59c09573e.08c600e9710d8620
+ 8ffc3c186541c920
+VBLENDPD_128_1of2(mem)
+ before
+ 25c280ece9388014.917889b19a8b120c.1e64c923b7071e3d.4218b9ea7dc0c95b
+ a6e4485318fc6829.8f7c40c960073991.ee5fe0438d83769c.42466651652d9067
+ ee2d10380e9b3d8b.4ce4091456cb4dc7.575bf8abdc149d72.9473e675efdbe50f
+ d86b5586e821bb65.26fedefe18618b5b.35258f47c1c44fea.94ea36c2b85707ff
+ 9ef851a55b2c30e2
+ after
+ 25c280ece9388014.917889b19a8b120c.1e64c923b7071e3d.4218b9ea7dc0c95b
+ a6e4485318fc6829.8f7c40c960073991.ee5fe0438d83769c.42466651652d9067
+ 0000000000000000.0000000000000000.ee5fe0438d83769c.4218b9ea7dc0c95b
+ d86b5586e821bb65.26fedefe18618b5b.35258f47c1c44fea.94ea36c2b85707ff
+ 9ef851a55b2c30e2
+
+VBLENDPD_128_1of2(reg)
+ before
+ 0dea338874e69d65.4268912bc2989de4.7714bdf343572ef8.6489200357a14831
+ 3f09d8d8a0118a33.07f14212b60ea033.9c73a2607239744c.bf5227ccbbb74373
+ 8fa43d027b3a32f9.03d2e327e38f807f.f26787af42919700.244e218c0810fddb
+ 59065d70a0ecd262.11d7f1576225f9f4.d33c6a4e4eedd3c2.6e4789315aba3295
+ 780bdba6cec19dcf
+ after
+ 0000000000000000.0000000000000000.9c73a2607239744c.bf5227ccbbb74373
+ 3f09d8d8a0118a33.07f14212b60ea033.9c73a2607239744c.bf5227ccbbb74373
+ 8fa43d027b3a32f9.03d2e327e38f807f.f26787af42919700.244e218c0810fddb
+ 59065d70a0ecd262.11d7f1576225f9f4.d33c6a4e4eedd3c2.6e4789315aba3295
+ 780bdba6cec19dcf
+VBLENDPD_128_1of2(mem)
+ before
+ 206493d78030fbb3.f97b3490abb4a61c.0fcce68c52dec6bd.9c3d46a733d9663e
+ 411f2db08b13086d.ca4ebecd391de9d0.d87c40b3ccc6a406.aab817288cdf8a20
+ b608261d0b76802a.2accf793e6b3d92d.47b57ab9efe84ffd.57f7d93cf68d7c13
+ 5deaf90a1d661e16.7441dc4e4d02b0dd.3a411088d45082cc.0047894f0c6f78c3
+ 01f421cd6b0fb9de
+ after
+ 206493d78030fbb3.f97b3490abb4a61c.0fcce68c52dec6bd.9c3d46a733d9663e
+ 411f2db08b13086d.ca4ebecd391de9d0.d87c40b3ccc6a406.aab817288cdf8a20
+ 0000000000000000.0000000000000000.d87c40b3ccc6a406.9c3d46a733d9663e
+ 5deaf90a1d661e16.7441dc4e4d02b0dd.3a411088d45082cc.0047894f0c6f78c3
+ 01f421cd6b0fb9de
+
+VBLENDPD_128_1of2(reg)
+ before
+ b64a9f22aefb7c0d.10932263dcee9f5c.03f9686a0a97aa8c.8bed7f0e990afa9f
+ 7b95ffba72bffdff.adcd1d14651abf29.35409753bafd05e7.188541365a2373a3
+ ac203b0152e6775e.0e65670ad4f739a9.65616575f8c1fb9a.bbd5d4ec32a6a904
+ a5385164eafc27d6.11277a2f4390ca07.eeaacf3d616ec950.52a8b31c3e9f57ed
+ b7cc5bb2991b3a8b
+ after
+ 0000000000000000.0000000000000000.35409753bafd05e7.188541365a2373a3
+ 7b95ffba72bffdff.adcd1d14651abf29.35409753bafd05e7.188541365a2373a3
+ ac203b0152e6775e.0e65670ad4f739a9.65616575f8c1fb9a.bbd5d4ec32a6a904
+ a5385164eafc27d6.11277a2f4390ca07.eeaacf3d616ec950.52a8b31c3e9f57ed
+ b7cc5bb2991b3a8b
+VBLENDPD_128_1of2(mem)
+ before
+ c70b469a5f250e09.c22a3b4dd78d4915.90dfd471d1f22e6f.2e65d0159090aab6
+ 5f32f2c0adca8e94.5f40f82ab42619c4.6859f0ba9728210f.7fdf646a22b4dc78
+ 590dda109e157758.d8c681661e52d292.76604bf8b33e5e10.3f6487a9b2659941
+ 92687a774f128580.890ad36cb19db129.94c25f164140a2a1.c840353ddd2f1dbd
+ 77bf6b923e9fa69a
+ after
+ c70b469a5f250e09.c22a3b4dd78d4915.90dfd471d1f22e6f.2e65d0159090aab6
+ 5f32f2c0adca8e94.5f40f82ab42619c4.6859f0ba9728210f.7fdf646a22b4dc78
+ 0000000000000000.0000000000000000.6859f0ba9728210f.2e65d0159090aab6
+ 92687a774f128580.890ad36cb19db129.94c25f164140a2a1.c840353ddd2f1dbd
+ 77bf6b923e9fa69a
+
+VBLENDPD_128_2of2(reg)
+ before
+ a92c241471406e81.e60e4fdfdbcd7439.ce57ebaa0894f235.9f49aa005c3ba9ec
+ b8d45c2f139eb221.32cdd3365f53ffaf.03f8c48bbfc2d163.73c2a7a2213a2e1e
+ 01040f4fc046ad24.506f8466f7afe30d.843a5a7b73b4895f.edf9d2e8ab4aee62
+ e1063ae013c39d37.1dc1dd5dbdeedc7f.ac6aaae6bff557d5.e7baa8be1676a5e5
+ 3ed0a4117fca0fd2
+ after
+ 0000000000000000.0000000000000000.843a5a7b73b4895f.73c2a7a2213a2e1e
+ b8d45c2f139eb221.32cdd3365f53ffaf.03f8c48bbfc2d163.73c2a7a2213a2e1e
+ 01040f4fc046ad24.506f8466f7afe30d.843a5a7b73b4895f.edf9d2e8ab4aee62
+ e1063ae013c39d37.1dc1dd5dbdeedc7f.ac6aaae6bff557d5.e7baa8be1676a5e5
+ 3ed0a4117fca0fd2
+VBLENDPD_128_2of2(mem)
+ before
+ ce0941cb0252e756.b227d74ea8a1bc05.75905b06d01ba632.d9d2ae394011776f
+ 732ffedaba1bea9d.d1b2e4051c6d473b.34a5784d4942fc52.66be64de919424dc
+ 090f5428c331d4d2.9af55c720bb27984.36cfb21e46709b0b.af7cc7424e0b9bc6
+ 6c75c1a33a9e6122.693a3cff10fc8f8d.57d98465e3b03e88.0f56d3d2150218da
+ e49a85f87f03d7c3
+ after
+ ce0941cb0252e756.b227d74ea8a1bc05.75905b06d01ba632.d9d2ae394011776f
+ 732ffedaba1bea9d.d1b2e4051c6d473b.34a5784d4942fc52.66be64de919424dc
+ 0000000000000000.0000000000000000.75905b06d01ba632.d9d2ae394011776f
+ 6c75c1a33a9e6122.693a3cff10fc8f8d.57d98465e3b03e88.0f56d3d2150218da
+ e49a85f87f03d7c3
+
+VBLENDPD_128_2of2(reg)
+ before
+ 8892d8222a9c132e.782dbf363a704cb8.9ace7e1ac7d8c502.738e6a0f3b0ea3f5
+ 598bc8bbb25809c7.0903cccde0b252c1.8afe202ecdd1578e.66bbe0066b97847f
+ b2d1512fb2c4f539.fbc2645447712f69.93131da7bd7380de.0c2c63378e569e52
+ eeaf6feac66b1230.2a3801b78cb89edb.125c71f1344b7d9d.41ad6e8fc057ac9a
+ e10a7df91ea66b82
+ after
+ 0000000000000000.0000000000000000.93131da7bd7380de.66bbe0066b97847f
+ 598bc8bbb25809c7.0903cccde0b252c1.8afe202ecdd1578e.66bbe0066b97847f
+ b2d1512fb2c4f539.fbc2645447712f69.93131da7bd7380de.0c2c63378e569e52
+ eeaf6feac66b1230.2a3801b78cb89edb.125c71f1344b7d9d.41ad6e8fc057ac9a
+ e10a7df91ea66b82
+VBLENDPD_128_2of2(mem)
+ before
+ c80f0c60c3509736.6b731f588bd99d5a.722f21e2ca935c43.63241978cde48a78
+ d18797b2cc61ece3.83675be59d9bd260.ae743ec11e0f25cf.e1b610a825cbe31b
+ da409bda55e325b5.93d921fd963cedf1.bcd3d740a337b4a9.ea6052edd78bc331
+ be0493c479e4ffd7.f8136d0d154829b7.7717654c7517c7fd.d96cdbb37fb06767
+ 0a27a767bac60a68
+ after
+ c80f0c60c3509736.6b731f588bd99d5a.722f21e2ca935c43.63241978cde48a78
+ d18797b2cc61ece3.83675be59d9bd260.ae743ec11e0f25cf.e1b610a825cbe31b
+ 0000000000000000.0000000000000000.722f21e2ca935c43.63241978cde48a78
+ be0493c479e4ffd7.f8136d0d154829b7.7717654c7517c7fd.d96cdbb37fb06767
+ 0a27a767bac60a68
+
+VBLENDPD_128_2of2(reg)
+ before
+ d9ddb373245aeae1.59a0fb5c54703676.0c62397fb44cc35f.bb0e65cfb2bc18f8
+ a2d9f94558f7417d.86e0508e039286be.2c1183c10fd3f794.638254b7733163c6
+ c1697747f22a4cea.238f0c47a156aada.b56e463dc3690003.4d41adefd6836692
+ 91d729e78f7d46d1.0b7bad714bc85ff7.01c37e616b9b1b57.5415ec63f7bcdb89
+ 53cb8efff1ea7fd7
+ after
+ 0000000000000000.0000000000000000.b56e463dc3690003.638254b7733163c6
+ a2d9f94558f7417d.86e0508e039286be.2c1183c10fd3f794.638254b7733163c6
+ c1697747f22a4cea.238f0c47a156aada.b56e463dc3690003.4d41adefd6836692
+ 91d729e78f7d46d1.0b7bad714bc85ff7.01c37e616b9b1b57.5415ec63f7bcdb89
+ 53cb8efff1ea7fd7
+VBLENDPD_128_2of2(mem)
+ before
+ 282f0dafe0190da7.70700990cb7f6ce1.196eaef91cf56140.6d5e2798a4f4843d
+ ad0ce75fe1534226.b98015ae41b9fac3.2b358bcc30e86be2.55893e4e09007761
+ c03097fb0fa7da7f.c75348ad8db92c26.1b9cc1d5a5ad3a08.1591bdef364c2f6e
+ 3b65996f871e91df.f8359ef94c0a3eb4.c76fcaff94518adf.0ac2a2e7c863e911
+ 8e67e9a25bd1e1f5
+ after
+ 282f0dafe0190da7.70700990cb7f6ce1.196eaef91cf56140.6d5e2798a4f4843d
+ ad0ce75fe1534226.b98015ae41b9fac3.2b358bcc30e86be2.55893e4e09007761
+ 0000000000000000.0000000000000000.196eaef91cf56140.6d5e2798a4f4843d
+ 3b65996f871e91df.f8359ef94c0a3eb4.c76fcaff94518adf.0ac2a2e7c863e911
+ 8e67e9a25bd1e1f5
+
+VBLENDPD_256_1of3(reg)
+ before
+ fece8c8c8a2352c7.fc786aa864c62371.a67213ff19396b1a.097a24381bdf1793
+ b6418912f1e47a33.dd358590c3aa4b62.2f55a42991d1f003.bf894a6b56649c4f
+ 120ddb9e2da093e4.bc686615bfd6c6de.ed2b4be44f5e081c.c367b98460ead640
+ 6e7e7e9edae4d987.73dd892175574f10.3e40069df06df010.f2e1eb6f55808192
+ 29c45e19522f5870
+ after
+ b6418912f1e47a33.dd358590c3aa4b62.2f55a42991d1f003.bf894a6b56649c4f
+ b6418912f1e47a33.dd358590c3aa4b62.2f55a42991d1f003.bf894a6b56649c4f
+ 120ddb9e2da093e4.bc686615bfd6c6de.ed2b4be44f5e081c.c367b98460ead640
+ 6e7e7e9edae4d987.73dd892175574f10.3e40069df06df010.f2e1eb6f55808192
+ 29c45e19522f5870
+VBLENDPD_256_1of3(mem)
+ before
+ 42da8d6c72051806.26e06e7c933b8ac7.df5f6aa20038a425.7ce0d0be0f89e48d
+ 1aeff455d20d7d82.967fa8a6f432e051.ddbc86837d867f49.0557a6b5493e203c
+ 8dd110c18e54430d.19a726879a5417d1.47be58b0074c9ca7.33f182ed3919e0cb
+ 784a5b9ac0e425d6.0da3e68b202d6df2.fa325c15ba96b96b.64f962d27ba55fe6
+ f2bd41d0ac6eda39
+ after
+ 42da8d6c72051806.26e06e7c933b8ac7.df5f6aa20038a425.7ce0d0be0f89e48d
+ 1aeff455d20d7d82.967fa8a6f432e051.ddbc86837d867f49.0557a6b5493e203c
+ 1aeff455d20d7d82.967fa8a6f432e051.df5f6aa20038a425.7ce0d0be0f89e48d
+ 784a5b9ac0e425d6.0da3e68b202d6df2.fa325c15ba96b96b.64f962d27ba55fe6
+ f2bd41d0ac6eda39
+
+VBLENDPD_256_1of3(reg)
+ before
+ 3a871c5368018c6f.b52853ce87cce007.cdc0e31e23491c61.d2e40e9eb37090c3
+ 98a4edc74ae9b334.21357348fc1530cc.b54a1aac3e3561c9.aba0ea370ee7ded8
+ 6960b298eeb28936.983e37f43ecdd153.218d85a10e7c78d7.61316dcde6075ed9
+ 07076633f1e94a1f.f60f1cbe66ff7ec5.6cd5226a2eab9c36.d165124a57dacef0
+ d506559c7e6ee849
+ after
+ 98a4edc74ae9b334.21357348fc1530cc.b54a1aac3e3561c9.aba0ea370ee7ded8
+ 98a4edc74ae9b334.21357348fc1530cc.b54a1aac3e3561c9.aba0ea370ee7ded8
+ 6960b298eeb28936.983e37f43ecdd153.218d85a10e7c78d7.61316dcde6075ed9
+ 07076633f1e94a1f.f60f1cbe66ff7ec5.6cd5226a2eab9c36.d165124a57dacef0
+ d506559c7e6ee849
+VBLENDPD_256_1of3(mem)
+ before
+ 4ae1b2ad77ce6912.cfe40502ef19349b.17749d9293b8f451.f46eec713b4d0a94
+ 0cc2a66b5c070c74.1d448b7382ce8157.d738365cde03ee21.14a3e024d0eefe9a
+ f775acc14c248e9e.4d74f5f049956eff.1229630865ec2a61.27c1f8ed8a1bb4f7
+ e7c6409b6131abba.bbbe3ee7def9373e.a411a0824480623f.8b15323a045e6754
+ 9ae98976da465460
+ after
+ 4ae1b2ad77ce6912.cfe40502ef19349b.17749d9293b8f451.f46eec713b4d0a94
+ 0cc2a66b5c070c74.1d448b7382ce8157.d738365cde03ee21.14a3e024d0eefe9a
+ 0cc2a66b5c070c74.1d448b7382ce8157.17749d9293b8f451.f46eec713b4d0a94
+ e7c6409b6131abba.bbbe3ee7def9373e.a411a0824480623f.8b15323a045e6754
+ 9ae98976da465460
+
+VBLENDPD_256_1of3(reg)
+ before
+ b28af90da95cb7c5.b780dee5b73b1ff4.c36f62c3dd8617c1.69bd6ab796ca53e4
+ 2d437e6b0d2ecb30.4571028b6b4da579.c1d35df0e3c94b33.3df93c9177d6b87f
+ 696215fca147cd4c.6c6329799873fa75.11352cda8b4d0f41.fc9192fe04b14e3a
+ c031b92c0134f9c6.0823ce9b5abada14.0fe3c9ed719f9e97.8250e8e95966d141
+ ab04ba3e9101fdc1
+ after
+ 2d437e6b0d2ecb30.4571028b6b4da579.c1d35df0e3c94b33.3df93c9177d6b87f
+ 2d437e6b0d2ecb30.4571028b6b4da579.c1d35df0e3c94b33.3df93c9177d6b87f
+ 696215fca147cd4c.6c6329799873fa75.11352cda8b4d0f41.fc9192fe04b14e3a
+ c031b92c0134f9c6.0823ce9b5abada14.0fe3c9ed719f9e97.8250e8e95966d141
+ ab04ba3e9101fdc1
+VBLENDPD_256_1of3(mem)
+ before
+ 527785e9c88f8de6.90fd6667ca808b49.f57d6ddecf2d0180.17273295334936e0
+ 5576c4d61b1b3edc.3312181997b7be82.0f3c822c10d82ae8.854e623f6ada10c8
+ 8fcdf3f1a5b1cccd.06bccbaf0566cf1d.312e8a733bc81276.b5a45655b4db6bfd
+ db488e26835ef3e8.66477c93af18fac5.391dff9d6c087557.03750845adda8229
+ cb0d7679f06290f8
+ after
+ 527785e9c88f8de6.90fd6667ca808b49.f57d6ddecf2d0180.17273295334936e0
+ 5576c4d61b1b3edc.3312181997b7be82.0f3c822c10d82ae8.854e623f6ada10c8
+ 5576c4d61b1b3edc.3312181997b7be82.f57d6ddecf2d0180.17273295334936e0
+ db488e26835ef3e8.66477c93af18fac5.391dff9d6c087557.03750845adda8229
+ cb0d7679f06290f8
+
+VBLENDPD_256_2of3(reg)
+ before
+ 68b79b5f1900d117.17b31261d02d6e57.adff263332597a27.02d75f98bea40eb6
+ 38c07362c53e8332.1ed9fa8ea92afa47.382fc5fa29b68cef.6726264f4da99ac0
+ 9675fbed90abe0f5.cb88c29a296253e3.6324555431ba6cc8.46d7ceae3622d5a1
+ dd202d6e15d0250a.fc8ae6706de03458.8b2bd3ade5f1565e.79b6d5a1951b7b84
+ de8eb61484a14795
+ after
+ 38c07362c53e8332.cb88c29a296253e3.6324555431ba6cc8.6726264f4da99ac0
+ 38c07362c53e8332.1ed9fa8ea92afa47.382fc5fa29b68cef.6726264f4da99ac0
+ 9675fbed90abe0f5.cb88c29a296253e3.6324555431ba6cc8.46d7ceae3622d5a1
+ dd202d6e15d0250a.fc8ae6706de03458.8b2bd3ade5f1565e.79b6d5a1951b7b84
+ de8eb61484a14795
+VBLENDPD_256_2of3(mem)
+ before
+ 4f2dedf322bff602.6b0e0750f03b8e20.8bace3fb90b05ad1.0a8e3a71e2e8855f
+ aa5df62a898244f5.9b8a8400be7756e1.56ba3329aedf817c.3d99860cc32a3674
+ c9eb4da6d5f4ec9a.c8e2a1e81a11bafa.378054e5e4786582.809ab3ea2444a54c
+ 8aa36f512324ab1e.50605875a194f616.0cc9c11b4e88c112.2fdcbd77a2c00e91
+ a6aaa120d92cacef
+ after
+ 4f2dedf322bff602.6b0e0750f03b8e20.8bace3fb90b05ad1.0a8e3a71e2e8855f
+ aa5df62a898244f5.9b8a8400be7756e1.56ba3329aedf817c.3d99860cc32a3674
+ 4f2dedf322bff602.9b8a8400be7756e1.56ba3329aedf817c.0a8e3a71e2e8855f
+ 8aa36f512324ab1e.50605875a194f616.0cc9c11b4e88c112.2fdcbd77a2c00e91
+ a6aaa120d92cacef
+
+VBLENDPD_256_2of3(reg)
+ before
+ 41515a4f6414bc14.c751d7198e1b3dad.8d52a714ee8c46e2.af63f6b7071a5255
+ 5c1de472df0379a9.5dc101e833e75e72.dd02892f9e86e509.fd1870a52b3ad47a
+ 535a3bf3e785215d.29be6aac2d93c99a.9abdfa344c0d1039.d3b5aad1d7f402ab
+ 82545c401826eeda.05168c50982c3b50.22cff68d95ad031b.0b06202727559915
+ 82d74e94366855e3
+ after
+ 5c1de472df0379a9.29be6aac2d93c99a.9abdfa344c0d1039.fd1870a52b3ad47a
+ 5c1de472df0379a9.5dc101e833e75e72.dd02892f9e86e509.fd1870a52b3ad47a
+ 535a3bf3e785215d.29be6aac2d93c99a.9abdfa344c0d1039.d3b5aad1d7f402ab
+ 82545c401826eeda.05168c50982c3b50.22cff68d95ad031b.0b06202727559915
+ 82d74e94366855e3
+VBLENDPD_256_2of3(mem)
+ before
+ 15f4b002203af242.455641c40c731dcc.ce93e5c092bc70c1.cf837aa814f2f95d
+ 9e28c35f02d62b5d.f8aee8eb62f7e9e0.6102f0e834522319.fe2781f065692fab
+ fa400296f748bd61.f6a64c21b43f8fc2.982f29b49cf71183.0c0507d1259ee1b1
+ 0509e9921c9c647a.9d8b6ad29ed64b1d.50e60d11e6b9f62c.536a08b7f01b4b1a
+ 30a2810e616ea892
+ after
+ 15f4b002203af242.455641c40c731dcc.ce93e5c092bc70c1.cf837aa814f2f95d
+ 9e28c35f02d62b5d.f8aee8eb62f7e9e0.6102f0e834522319.fe2781f065692fab
+ 15f4b002203af242.f8aee8eb62f7e9e0.6102f0e834522319.cf837aa814f2f95d
+ 0509e9921c9c647a.9d8b6ad29ed64b1d.50e60d11e6b9f62c.536a08b7f01b4b1a
+ 30a2810e616ea892
+
+VBLENDPD_256_2of3(reg)
+ before
+ fff96d43142335c7.9b4df4418cdfdcd3.48a93d6abc48599e.65f216e92da38e3f
+ 1dbbc7c0a6c52e63.98d8a08e641ce099.534cc056ac21f5f1.b321c2298dc294e9
+ e4338ef3b3e0cf12.d8786765bf602df7.19bff10007ee5ac1.163d8cbe2321c556
+ b1afbb46d5005381.37f8c7b2b9b67e1a.f850ccd56b3ac4bb.6a13f1920accddb1
+ 8b6f6b935fd09827
+ after
+ 1dbbc7c0a6c52e63.d8786765bf602df7.19bff10007ee5ac1.b321c2298dc294e9
+ 1dbbc7c0a6c52e63.98d8a08e641ce099.534cc056ac21f5f1.b321c2298dc294e9
+ e4338ef3b3e0cf12.d8786765bf602df7.19bff10007ee5ac1.163d8cbe2321c556
+ b1afbb46d5005381.37f8c7b2b9b67e1a.f850ccd56b3ac4bb.6a13f1920accddb1
+ 8b6f6b935fd09827
+VBLENDPD_256_2of3(mem)
+ before
+ 551d78ac3d37b1e3.e0794c27abb2f75c.91233c626f2a912e.4b494b427492718a
+ a4e993c9c110e512.cdde3b01cf81f64e.c2c6405ffdc9205e.6df76cb2bd819bdb
+ 549e38d60764efe0.d42a863fddf98e04.a6ad51977e9ee8d7.bca62a91e3937f59
+ 410ae4bf29418d78.51a9294f72a7f929.19a4e9f40eb5a4c4.92a2814a815559b2
+ 4d376d4b3352648f
+ after
+ 551d78ac3d37b1e3.e0794c27abb2f75c.91233c626f2a912e.4b494b427492718a
+ a4e993c9c110e512.cdde3b01cf81f64e.c2c6405ffdc9205e.6df76cb2bd819bdb
+ 551d78ac3d37b1e3.cdde3b01cf81f64e.c2c6405ffdc9205e.4b494b427492718a
+ 410ae4bf29418d78.51a9294f72a7f929.19a4e9f40eb5a4c4.92a2814a815559b2
+ 4d376d4b3352648f
+
+VBLENDPD_256_3of3(reg)
+ before
+ 47b1ebff9616de9f.47f7117045b37907.a0a61e9c2916746a.f7778664ca1b1152
+ de5bf6d3452d008b.42323dd577c470b8.1d6f63929ed33a73.1cf2a4d1cedbebac
+ 6c828a31dd240902.0d87e3dbda822db8.244ef39e6f6888ef.64e0bd293501ee00
+ 4e72a386fa8733ae.86c1806c8bf96e33.1190ca2a35639a8a.aa0f4f571b9ad577
+ cc49d5479db15d40
+ after
+ 6c828a31dd240902.0d87e3dbda822db8.1d6f63929ed33a73.1cf2a4d1cedbebac
+ de5bf6d3452d008b.42323dd577c470b8.1d6f63929ed33a73.1cf2a4d1cedbebac
+ 6c828a31dd240902.0d87e3dbda822db8.244ef39e6f6888ef.64e0bd293501ee00
+ 4e72a386fa8733ae.86c1806c8bf96e33.1190ca2a35639a8a.aa0f4f571b9ad577
+ cc49d5479db15d40
+VBLENDPD_256_3of3(mem)
+ before
+ a55bcbe5d6524285.e1773d3f36e0bb3c.88ae8e76a533ed54.4081e4a38e50acf2
+ 1011ad1de38a4072.7fdd55c630bddd57.ee188be3443e6648.0d6d3e7616baf9d1
+ eb36f8dcdf641234.85efe68981aad5ac.96cdf2a18526973a.d3a0d30d682dbed3
+ 1198270ce7ec75f7.4ffbecf3c831dee6.5b973f9b84f63a57.f0659fd6203537a5
+ bf0a9e3cdb5fa0f3
+ after
+ a55bcbe5d6524285.e1773d3f36e0bb3c.88ae8e76a533ed54.4081e4a38e50acf2
+ 1011ad1de38a4072.7fdd55c630bddd57.ee188be3443e6648.0d6d3e7616baf9d1
+ a55bcbe5d6524285.e1773d3f36e0bb3c.88ae8e76a533ed54.4081e4a38e50acf2
+ 1198270ce7ec75f7.4ffbecf3c831dee6.5b973f9b84f63a57.f0659fd6203537a5
+ bf0a9e3cdb5fa0f3
+
+VBLENDPD_256_3of3(reg)
+ before
+ 9cd9ccab35363468.5d01b69b162f25e6.3a4b636f9ee035b2.1843eebd5cba0cca
+ e21f268fc94730b1.ad3e21738938dd2e.a02c486ba24315bc.ab9d7cf3297ec8c0
+ ef28a754331dd07a.db1be4825b145afb.deea96526de5bcaf.ee706429084f2b65
+ 1d404b6610444f6e.c5647cb3a8cd5878.50d149909d526438.bf8a224b1538f1e4
+ f8b532456a45d66a
+ after
+ ef28a754331dd07a.db1be4825b145afb.a02c486ba24315bc.ab9d7cf3297ec8c0
+ e21f268fc94730b1.ad3e21738938dd2e.a02c486ba24315bc.ab9d7cf3297ec8c0
+ ef28a754331dd07a.db1be4825b145afb.deea96526de5bcaf.ee706429084f2b65
+ 1d404b6610444f6e.c5647cb3a8cd5878.50d149909d526438.bf8a224b1538f1e4
+ f8b532456a45d66a
+VBLENDPD_256_3of3(mem)
+ before
+ 77be110426839623.cab20e31fb49ea3a.45e564f18e7193d1.522d5d92ce164902
+ 1671397262fdec3a.51cced2291b7dd89.396a182a260cc634.4049cec29bbea9ba
+ b39a287d3dc095db.0dd8e3a36d1a6408.7bbe14498ea9aecb.7673998da0d5be0c
+ 28055a10d0d74c34.5c23eb212cffba62.e8aed53ae25407c2.50f5b9607ae7c5a3
+ 2a1c2aa5c581fa2c
+ after
+ 77be110426839623.cab20e31fb49ea3a.45e564f18e7193d1.522d5d92ce164902
+ 1671397262fdec3a.51cced2291b7dd89.396a182a260cc634.4049cec29bbea9ba
+ 77be110426839623.cab20e31fb49ea3a.45e564f18e7193d1.522d5d92ce164902
+ 28055a10d0d74c34.5c23eb212cffba62.e8aed53ae25407c2.50f5b9607ae7c5a3
+ 2a1c2aa5c581fa2c
+
+VBLENDPD_256_3of3(reg)
+ before
+ 6034e8ca1c2e9852.527d4916394ecf6f.98f9040969f01c44.5d07d6ea3c198c46
+ 4e89f03a1b7bdcc2.0ed0727d9431d8b8.1ea627c6c17cc65a.b4939343bb05fa83
+ 50663c615ff20228.36c85230fc8d233c.4b7552c4cf2cf34f.ca1e883279230da4
+ c219caab8322452f.a732641b8e6d6e27.79b4806f2f8ee0d0.7c7631a4928081d6
+ a4660b8423271144
+ after
+ 50663c615ff20228.36c85230fc8d233c.1ea627c6c17cc65a.b4939343bb05fa83
+ 4e89f03a1b7bdcc2.0ed0727d9431d8b8.1ea627c6c17cc65a.b4939343bb05fa83
+ 50663c615ff20228.36c85230fc8d233c.4b7552c4cf2cf34f.ca1e883279230da4
+ c219caab8322452f.a732641b8e6d6e27.79b4806f2f8ee0d0.7c7631a4928081d6
+ a4660b8423271144
+VBLENDPD_256_3of3(mem)
+ before
+ 1fb991bd47247a1b.00ec96842494e384.3dda252a65de73a4.05adad337e2ec989
+ c93c3f3d1b837887.652c9a58ddd616d2.d48c0f4a9debefe0.4cadd57c5896ea25
+ 7ebb91efba51c7b3.4f25d4934b731ac6.4913a06553a09d06.a800f4b658547e50
+ 1a0204bf419a22cc.19233ea109f82d0b.763d5368a3093b43.76f2074d1af4c2b8
+ 12cf09ad3b00f206
+ after
+ 1fb991bd47247a1b.00ec96842494e384.3dda252a65de73a4.05adad337e2ec989
+ c93c3f3d1b837887.652c9a58ddd616d2.d48c0f4a9debefe0.4cadd57c5896ea25
+ 1fb991bd47247a1b.00ec96842494e384.3dda252a65de73a4.05adad337e2ec989
+ 1a0204bf419a22cc.19233ea109f82d0b.763d5368a3093b43.76f2074d1af4c2b8
+ 12cf09ad3b00f206
+
+VPBLENDW_128_0x00(reg)
+ before
+ d9e3f643560649e9.79dd1299cb6846fd.1f71d7efb4f0894e.38d4a440a83383c3
+ 2579cb790892050b.7717396974c9ee73.bc5d98e7e7e76b3b.6ba50fd77e2a32b1
+ 53de82bded2f5f19.f07ef41b5ac8d85a.4e317ef73e690e7e.eb7c111b42f8033a
+ bf5e197a9f6996be.c0dcc09c9672bedd.2f3a868a5703b0c1.942524f70fabb389
+ 426cc657024efecb
+ after
+ 0000000000000000.0000000000000000.bc5d98e7e7e76b3b.6ba50fd77e2a32b1
+ 2579cb790892050b.7717396974c9ee73.bc5d98e7e7e76b3b.6ba50fd77e2a32b1
+ 53de82bded2f5f19.f07ef41b5ac8d85a.4e317ef73e690e7e.eb7c111b42f8033a
+ bf5e197a9f6996be.c0dcc09c9672bedd.2f3a868a5703b0c1.942524f70fabb389
+ 426cc657024efecb
+VPBLENDW_128_0x00(mem)
+ before
+ d11c732736eea02c.c5458b1cbdcce4a7.c3fe17d646d25d29.bdc4ab0bcb408bb3
+ 1c03a553c89654d7.c1dfd40fe0e5867f.d5b077b786f47069.521be9e838addbfe
+ 01ebdac7d352d7f9.0f78f1bfa73fb8f3.d2be5b2971e5b4ca.4c8b3c8c3ad5de4f
+ 5ba18d6f742fe5bd.0b5bdc98ab66b6ae.96f3401a23b0e578.055fa1636b44ce51
+ dbe513d96a87e8b1
+ after
+ d11c732736eea02c.c5458b1cbdcce4a7.c3fe17d646d25d29.bdc4ab0bcb408bb3
+ 1c03a553c89654d7.c1dfd40fe0e5867f.d5b077b786f47069.521be9e838addbfe
+ 0000000000000000.0000000000000000.d5b077b786f47069.521be9e838ad8bb3
+ 5ba18d6f742fe5bd.0b5bdc98ab66b6ae.96f3401a23b0e578.055fa1636b44ce51
+ dbe513d96a87e8b1
+
+VPBLENDW_128_0x00(reg)
+ before
+ 28678e5bd129671a.06f13a38c6383a50.11d593068ae7bb5e.fd1da075b961bf9e
+ 4a320e533cb68939.dea65d0ce67991dd.7d331275e04d04ac.e206f9264e05fd69
+ 9b928f2f48bb88ba.be8e72d9efffa792.abbf53524825cd47.237bc619ffa75c04
+ 78d30e5990c3a048.8473f689fdd53898.f6c553075ffa51d9.9b48833ae753989c
+ 2639ac7523166d5c
+ after
+ 0000000000000000.0000000000000000.7d331275e04d04ac.e206f9264e05fd69
+ 4a320e533cb68939.dea65d0ce67991dd.7d331275e04d04ac.e206f9264e05fd69
+ 9b928f2f48bb88ba.be8e72d9efffa792.abbf53524825cd47.237bc619ffa75c04
+ 78d30e5990c3a048.8473f689fdd53898.f6c553075ffa51d9.9b48833ae753989c
+ 2639ac7523166d5c
+VPBLENDW_128_0x00(mem)
+ before
+ 9f1abeb6cefb9671.3e40863fb15a0f90.0b23640a2d07ff1e.bc930f02c058cd0e
+ e4b634ea050ed007.4727f34b460d0f3e.2e6838479ba2b94e.587482ad07cb7d93
+ cfdb8afbe35cd74a.f0d252ebec67ddfd.cb0fef2c62b12254.26b3a876d1e09c14
+ 3e533cd785f06664.958e9d8a3ef4b479.bce403a59e41f65d.819d7ec8ba22683c
+ c77eff0f5c1e1bb8
+ after
+ 9f1abeb6cefb9671.3e40863fb15a0f90.0b23640a2d07ff1e.bc930f02c058cd0e
+ e4b634ea050ed007.4727f34b460d0f3e.2e6838479ba2b94e.587482ad07cb7d93
+ 0000000000000000.0000000000000000.2e6838479ba2b94e.587482ad07cbcd0e
+ 3e533cd785f06664.958e9d8a3ef4b479.bce403a59e41f65d.819d7ec8ba22683c
+ c77eff0f5c1e1bb8
+
+VPBLENDW_128_0x00(reg)
+ before
+ 53a226b7565ff134.0bebc66806d73a84.92a7d294d941d25f.dfb2f29e6c5cf095
+ 8055f22c4271285b.146fa59c831b0fd4.4369ec7558d9715b.0f473703e711cd27
+ ace25cdbbce1fada.33ab545e17cba181.0520e79a5748ce19.276d4fc12c694940
+ 3197612e613aa45c.466a4f9adef0abb6.3217bf6d731b2444.04f1b4c256721f0b
+ 839fe4f382370cb6
+ after
+ 0000000000000000.0000000000000000.4369ec7558d9715b.0f473703e711cd27
+ 8055f22c4271285b.146fa59c831b0fd4.4369ec7558d9715b.0f473703e711cd27
+ ace25cdbbce1fada.33ab545e17cba181.0520e79a5748ce19.276d4fc12c694940
+ 3197612e613aa45c.466a4f9adef0abb6.3217bf6d731b2444.04f1b4c256721f0b
+ 839fe4f382370cb6
+VPBLENDW_128_0x00(mem)
+ before
+ 7e435a41cbc4cc6a.6dbefe92cc08618e.277a123cf598eaa0.279b715b48ddb088
+ d3a992974e261b55.baa42e749ad76f1b.b4a51a3078ce1a6a.40f9f8d1711bae92
+ 5c9c08e02668b4a3.7695ed3e663408b0.c7b8e262829ef641.d97b50398a5f5a0e
+ f6ea390a70975480.fbdd385eccab68f9.3d7fe6bf2f153b51.4e6e75013038efa8
+ fa1d6494fe2faa0b
+ after
+ 7e435a41cbc4cc6a.6dbefe92cc08618e.277a123cf598eaa0.279b715b48ddb088
+ d3a992974e261b55.baa42e749ad76f1b.b4a51a3078ce1a6a.40f9f8d1711bae92
+ 0000000000000000.0000000000000000.b4a51a3078ce1a6a.40f9f8d1711bb088
+ f6ea390a70975480.fbdd385eccab68f9.3d7fe6bf2f153b51.4e6e75013038efa8
+ fa1d6494fe2faa0b
+
+VPBLENDW_128_0xFE(reg)
+ before
+ 3bd6185e91d2c7e3.7d5da00047beb717.a7c8093f6ac6cda1.f2c6a2319c3ea5c5
+ 6ce38dca85ac82dd.cec2b9aec7e99894.d4a15e4dd9137155.c35992a6e426f0ca
+ e992bf47744a16a5.c3e500000d24b425.dfb632f4b71e91c1.8a03330824d8d78b
+ 0e2daa3efd36c0e6.3992f1e3357cc7f3.255182a0a0716890.2491004577601735
+ 6dd07548facb6cf4
+ after
+ 0000000000000000.0000000000000000.dfb632f4b71e91c1.8a03330824d8f0ca
+ 6ce38dca85ac82dd.cec2b9aec7e99894.d4a15e4dd9137155.c35992a6e426f0ca
+ e992bf47744a16a5.c3e500000d24b425.dfb632f4b71e91c1.8a03330824d8d78b
+ 0e2daa3efd36c0e6.3992f1e3357cc7f3.255182a0a0716890.2491004577601735
+ 6dd07548facb6cf4
+VPBLENDW_128_0xFE(mem)
+ before
+ 418a0efcc82492f3.36014b1cb9ffbc4d.0c9409415afd8d2d.00bf48bd2f9a346e
+ 7c8b474ffe77445f.bf599d4d472e4586.18b9c30798b1c1fd.cd4c82b700252f09
+ faa19d2cb7d03f64.04839c3e4051983c.39cb9b220ca6208f.e8432bfbb09c960a
+ 97978b80103c3e2c.60c9445942f3f11c.4b970d7dd2e76611.adf23ff3da8da420
+ 79a3ba0d1b8496f5
+ after
+ 418a0efcc82492f3.36014b1cb9ffbc4d.0c9409415afd8d2d.00bf48bd2f9a346e
+ 7c8b474ffe77445f.bf599d4d472e4586.18b9c30798b1c1fd.cd4c82b700252f09
+ 0000000000000000.0000000000000000.0c9409415afd8d2d.00bf48bd2f9a346e
+ 97978b80103c3e2c.60c9445942f3f11c.4b970d7dd2e76611.adf23ff3da8da420
+ 79a3ba0d1b8496f5
+
+VPBLENDW_128_0xFE(reg)
+ before
+ a6a499b30f0ba835.2f388d3524c7ffe6.3179910ce9a18bd1.2ae9960305814fac
+ 913fd75350b1168e.9e5120380f7b3cbc.d2dd80c1d0e6a408.b28db1a2c17f968f
+ 96c170587dff1ba9.c0afbe76ee66b2db.9e420ce6934e766c.bf4fda4523edf8e4
+ 1175602e2f83f435.711be5d9dd931c6e.f3f431e6cf653daa.2dfa8dd846d830d7
+ d85c4647474bfc96
+ after
+ 0000000000000000.0000000000000000.9e420ce6934e766c.bf4fda4523ed968f
+ 913fd75350b1168e.9e5120380f7b3cbc.d2dd80c1d0e6a408.b28db1a2c17f968f
+ 96c170587dff1ba9.c0afbe76ee66b2db.9e420ce6934e766c.bf4fda4523edf8e4
+ 1175602e2f83f435.711be5d9dd931c6e.f3f431e6cf653daa.2dfa8dd846d830d7
+ d85c4647474bfc96
+VPBLENDW_128_0xFE(mem)
+ before
+ 9c3f827e4152164a.5ea9a34105c8dddc.8d64104ff70f37a2.2b3fec2d20b8376e
+ 5570bc6950fa3b22.d9a736fd985a124a.f055bbc358e5bfa3.a46e372721d39e63
+ debb70f5924e2648.debd14ce86c6ce2d.76b963201d21709c.b8ce10406e40af36
+ 15ec1a0c205a95e8.c93539216b974e2e.fa5e835461d005ba.c5ac72e5a48da593
+ 255259805e46be25
+ after
+ 9c3f827e4152164a.5ea9a34105c8dddc.8d64104ff70f37a2.2b3fec2d20b8376e
+ 5570bc6950fa3b22.d9a736fd985a124a.f055bbc358e5bfa3.a46e372721d39e63
+ 0000000000000000.0000000000000000.8d64104ff70f37a2.2b3fec2d20b8376e
+ 15ec1a0c205a95e8.c93539216b974e2e.fa5e835461d005ba.c5ac72e5a48da593
+ 255259805e46be25
+
+VPBLENDW_128_0xFE(reg)
+ before
+ 350dc27e39f53498.d5ce379c182b422f.f55ca160e25acdfc.5a0e974a41fd3b28
+ 5228a74cd128449a.fa2f428f96cce949.c07e49f9889a8941.71961beed9b4ce13
+ d6f10655c06b29d5.5fd9b7d3b5494861.85e62c56f8e3bca9.1bc28b2d43027aa7
+ 1eb2da04a54820f5.e299125391af19a4.a0e246e5cec1a3e1.335d64f19ef2fa0f
+ 9735202703910b77
+ after
+ 0000000000000000.0000000000000000.85e62c56f8e3bca9.1bc28b2d4302ce13
+ 5228a74cd128449a.fa2f428f96cce949.c07e49f9889a8941.71961beed9b4ce13
+ d6f10655c06b29d5.5fd9b7d3b5494861.85e62c56f8e3bca9.1bc28b2d43027aa7
+ 1eb2da04a54820f5.e299125391af19a4.a0e246e5cec1a3e1.335d64f19ef2fa0f
+ 9735202703910b77
+VPBLENDW_128_0xFE(mem)
+ before
+ 21143dbc91e9690d.86b920c7194d65a7.5d3bcffb4709193e.6cbc9311a7c17995
+ afc7379a6108cffb.6b50d209ba063497.ae8b6bb7f363035a.47c10f451e6e7b70
+ 1b1b88af91fafa6d.27c4ee3624fdc870.b0546173b0ca9425.8c3eb7efd055e51f
+ 43d9aee63dcaa690.17616fbaf2c05edf.3e642d1b9a4988ca.967c867a5901f34e
+ c3ca785354fee1a8
+ after
+ 21143dbc91e9690d.86b920c7194d65a7.5d3bcffb4709193e.6cbc9311a7c17995
+ afc7379a6108cffb.6b50d209ba063497.ae8b6bb7f363035a.47c10f451e6e7b70
+ 0000000000000000.0000000000000000.5d3bcffb4709193e.6cbc9311a7c17995
+ 43d9aee63dcaa690.17616fbaf2c05edf.3e642d1b9a4988ca.967c867a5901f34e
+ c3ca785354fee1a8
+
+VPBLENDW_128_0x30(reg)
+ before
+ 6e7389e45dd9eada.01d0242b80848f90.97725101c1db328f.36854b9cceed9b76
+ f2c2b69a111c4b8f.33cb666976347098.034591782cd97f2d.728437e067c08954
+ ad04fae20b563f74.b395f08f3ce706d5.b7242989cf468365.cf2d6ed482d10d91
+ f9865126e8100334.5ffc3f86eea80d72.0f5c17a247ae78e2.2a4c6b653a29e459
+ 5dadaa7eacd6c9d7
+ after
+ 0000000000000000.0000000000000000.03459178cf468365.728437e067c08954
+ f2c2b69a111c4b8f.33cb666976347098.034591782cd97f2d.728437e067c08954
+ ad04fae20b563f74.b395f08f3ce706d5.b7242989cf468365.cf2d6ed482d10d91
+ f9865126e8100334.5ffc3f86eea80d72.0f5c17a247ae78e2.2a4c6b653a29e459
+ 5dadaa7eacd6c9d7
+VPBLENDW_128_0x30(mem)
+ before
+ 451ba80bf3e37a38.3492b7d443d8d37c.11cacd3ba784409d.6739562d309e9a51
+ bf64dff72b5cb1a7.b8742856b83aebf8.a6cc189a83855c7f.1b07e29824a1275d
+ a552cd30724e2a52.e27aa11ae4c08753.facd9c909fba1d46.8712b84ec24359b3
+ d4b2eda1e1c5a362.0fee1d8b63f8e23a.ea9bd307162c3f1e.07a6d3baa4116cff
+ f60e2f4a66969eec
+ after
+ 451ba80bf3e37a38.3492b7d443d8d37c.11cacd3ba784409d.6739562d309e9a51
+ bf64dff72b5cb1a7.b8742856b83aebf8.a6cc189a83855c7f.1b07e29824a1275d
+ 0000000000000000.0000000000000000.a6cc189a83855c7f.1b07e298309e9a51
+ d4b2eda1e1c5a362.0fee1d8b63f8e23a.ea9bd307162c3f1e.07a6d3baa4116cff
+ f60e2f4a66969eec
+
+VPBLENDW_128_0x30(reg)
+ before
+ b297c869a55f2926.2850bb3796cbd605.991e9815d06d3959.50013bed05e97d33
+ 968d9a83fcf74a5b.7ef8b4dcad6e8067.dd540e24c8acc75b.09ca4e2c87fc94b0
+ fe3ca20508ea3d35.b075527d41b95cb4.38dd7c24e640caec.f1c38bb2b97240c1
+ 45f0db5964c43d60.9b9513076eb92817.0405dc82c6b67cba.e4b86b6ab6563d94
+ be756b409bb44652
+ after
+ 0000000000000000.0000000000000000.dd540e24e640caec.09ca4e2c87fc94b0
+ 968d9a83fcf74a5b.7ef8b4dcad6e8067.dd540e24c8acc75b.09ca4e2c87fc94b0
+ fe3ca20508ea3d35.b075527d41b95cb4.38dd7c24e640caec.f1c38bb2b97240c1
+ 45f0db5964c43d60.9b9513076eb92817.0405dc82c6b67cba.e4b86b6ab6563d94
+ be756b409bb44652
+VPBLENDW_128_0x30(mem)
+ before
+ 5bc608208398182a.c9f541ecad128789.1b22726451799ebc.9e182ca80598196e
+ 9776bdf68b0f6e46.e596d02b7e60575c.0ce9ec8205057bd0.626167043e74dfb7
+ 4e5306aece2506d2.f42184817338e984.4ab6fb4ba7697a7f.ac2e8a000ed6083f
+ 5c27603568e49afb.54e05a59292878ae.b1551dad53b258f5.d8c98f0a1148d1b2
+ 437f748de15876be
+ after
+ 5bc608208398182a.c9f541ecad128789.1b22726451799ebc.9e182ca80598196e
+ 9776bdf68b0f6e46.e596d02b7e60575c.0ce9ec8205057bd0.626167043e74dfb7
+ 0000000000000000.0000000000000000.0ce9ec8205057bd0.626167040598196e
+ 5c27603568e49afb.54e05a59292878ae.b1551dad53b258f5.d8c98f0a1148d1b2
+ 437f748de15876be
+
+VPBLENDW_128_0x30(reg)
+ before
+ 479c34f41d92320c.9dbf4575775ae7ed.60204d213cbb4186.1d92cd9323ecd15d
+ 416cccad5e81424b.ede7335c1493a8d4.732d5944477e80b7.6a3887e93621a1e3
+ 8d3a362343b1e225.286ba5d45d999adb.eb527b2ee6fc70ee.7415c89ba55f83b4
+ 875470c265ae4d46.2a1617cb6d7a792e.22ddad4bb6c14ed6.16f30a958eb234fc
+ 2e9fcbc40d2470e6
+ after
+ 0000000000000000.0000000000000000.732d5944e6fc70ee.6a3887e93621a1e3
+ 416cccad5e81424b.ede7335c1493a8d4.732d5944477e80b7.6a3887e93621a1e3
+ 8d3a362343b1e225.286ba5d45d999adb.eb527b2ee6fc70ee.7415c89ba55f83b4
+ 875470c265ae4d46.2a1617cb6d7a792e.22ddad4bb6c14ed6.16f30a958eb234fc
+ 2e9fcbc40d2470e6
+VPBLENDW_128_0x30(mem)
+ before
+ 97e586123dc3f39f.8a0475f76205c05c.cfb6062c614201fa.7518ed07535a561c
+ 2d91b86c3b9b7853.f497412cd6417710.f315ede355fbed6b.415036ce5852c46b
+ cb6edbbf22b6bc2d.2059d0ce5cefae11.710047dc63b3faac.e0d2840d6135d370
+ 4f4a6df60e227b5a.6a961f4a9199a009.27439303aa76e4ea.b0e7d42e0b90c0d7
+ 0bde209ff1eec74b
+ after
+ 97e586123dc3f39f.8a0475f76205c05c.cfb6062c614201fa.7518ed07535a561c
+ 2d91b86c3b9b7853.f497412cd6417710.f315ede355fbed6b.415036ce5852c46b
+ 0000000000000000.0000000000000000.f315ede355fbed6b.415036ce535a561c
+ 4f4a6df60e227b5a.6a961f4a9199a009.27439303aa76e4ea.b0e7d42e0b90c0d7
+ 0bde209ff1eec74b
+
+VPBLENDW_128_0x21(reg)
+ before
+ 4e0266cab0db2379.94efe9fc1ceb7005.2e9a280a10ce8ba4.f0aa4a44444e6751
+ d59ea11de3e4110c.752acbbf681b585b.c8b0e97c7517a88f.a701e98b4d493e0c
+ fd00ce032794cdb2.d0c7902a0dc1ef87.93265e0b5d023676.2a13edc5e2732648
+ 2072e7e817779314.8092b22927e6f1b7.ed468123631a6f04.53aed1dc1ed6db30
+ 009c12be1d8118f1
+ after
+ 0000000000000000.0000000000000000.c8b0e97c5d02a88f.a701e98b4d492648
+ d59ea11de3e4110c.752acbbf681b585b.c8b0e97c7517a88f.a701e98b4d493e0c
+ fd00ce032794cdb2.d0c7902a0dc1ef87.93265e0b5d023676.2a13edc5e2732648
+ 2072e7e817779314.8092b22927e6f1b7.ed468123631a6f04.53aed1dc1ed6db30
+ 009c12be1d8118f1
+VPBLENDW_128_0x21(mem)
+ before
+ 0caa2a56fc7d9ab6.9b41ea384f1a9ee0.6056afa8d3981914.315d503024ec90e6
+ 52a4978fd7d81dac.cab8d25f6d082bc2.4ee102932de224cd.bab7c69e3c03d5c8
+ af56d457c99d5dff.09259bc90acd7666.24fd27d74fd0ce0b.e69fdfd945eb7955
+ 008b5d99efd815da.b4d342e2c4f6bb77.c0779b5e586fd2fd.0f63974dde30b93a
+ 934deb67a15fd122
+ after
+ 0caa2a56fc7d9ab6.9b41ea384f1a9ee0.6056afa8d3981914.315d503024ec90e6
+ 52a4978fd7d81dac.cab8d25f6d082bc2.4ee102932de224cd.bab7c69e3c03d5c8
+ 0000000000000000.0000000000000000.4ee102932de21914.bab7c69e24ecd5c8
+ 008b5d99efd815da.b4d342e2c4f6bb77.c0779b5e586fd2fd.0f63974dde30b93a
+ 934deb67a15fd122
+
+VPBLENDW_128_0x21(reg)
+ before
+ ccabd5912a04fdba.1f11ae416496026a.270dc117370e35a1.fc1bd91661caedcd
+ 18c7533815a978ad.eab2443b44e2e0db.be2016d2fea12191.b5b55ce989eedba8
+ d1ee61c900dc7fa8.3b3b9973acc96a58.d5583c81b53cbaf3.c811a3c5e9e558b9
+ 556cf9af84284e57.ef782bd6b7565d0d.c801308ff96a3e73.0ffa27959fbe1f2d
+ 673e6644c782ed2f
+ after
+ 0000000000000000.0000000000000000.be2016d2b53c2191.b5b55ce989ee58b9
+ 18c7533815a978ad.eab2443b44e2e0db.be2016d2fea12191.b5b55ce989eedba8
+ d1ee61c900dc7fa8.3b3b9973acc96a58.d5583c81b53cbaf3.c811a3c5e9e558b9
+ 556cf9af84284e57.ef782bd6b7565d0d.c801308ff96a3e73.0ffa27959fbe1f2d
+ 673e6644c782ed2f
+VPBLENDW_128_0x21(mem)
+ before
+ ada7dac07c3f7eec.fe8c19563f1a2065.e335754e82957528.f367ec6765b8e7bb
+ bb0201f4db008d90.2a9cbb2acd3d327f.f13ef4c929926ed2.b2d56e7796b1f27a
+ 6e1b57cdffd2d746.33e6dd97c91dc051.f65e2231c65a033a.6199b12a27e19a5a
+ a2be563504c0183b.76b77b09d0470686.ce627d7478f8f18a.5cfdb1ecb5d41c08
+ fe4e6a29db17b42f
+ after
+ ada7dac07c3f7eec.fe8c19563f1a2065.e335754e82957528.f367ec6765b8e7bb
+ bb0201f4db008d90.2a9cbb2acd3d327f.f13ef4c929926ed2.b2d56e7796b1f27a
+ 0000000000000000.0000000000000000.f13ef4c929927528.b2d56e7765b8f27a
+ a2be563504c0183b.76b77b09d0470686.ce627d7478f8f18a.5cfdb1ecb5d41c08
+ fe4e6a29db17b42f
+
+VPBLENDW_128_0x21(reg)
+ before
+ a5d8d94e36359e7c.33b67c1907d60c9a.4f5b8fec7d463fca.5517807d5879f4ef
+ ace7f9c561bb159b.fdd1446624206e90.1b1e17ac6ca6a8cb.6747a83885e8c894
+ 6ec7c6fbf9345737.dcd92a0676abfb49.344c0eb53af47d32.e0bf6f91185128a6
+ 49c33c5d992c9dfd.ac9baae719836ff0.f730707482bbfaae.9d4a53742fc1d150
+ 78b6cfcde6437ebf
+ after
+ 0000000000000000.0000000000000000.1b1e17ac3af4a8cb.6747a83885e828a6
+ ace7f9c561bb159b.fdd1446624206e90.1b1e17ac6ca6a8cb.6747a83885e8c894
+ 6ec7c6fbf9345737.dcd92a0676abfb49.344c0eb53af47d32.e0bf6f91185128a6
+ 49c33c5d992c9dfd.ac9baae719836ff0.f730707482bbfaae.9d4a53742fc1d150
+ 78b6cfcde6437ebf
+VPBLENDW_128_0x21(mem)
+ before
+ 4ecd5f8858e3ed1f.98285855de302698.49e341f32ab286b2.c0183953e1885ae9
+ fa5c7f91a2add89b.b643145163ca2cb5.8f7d6918c446fbba.eb4e66c0f2e5da8f
+ 5a30acd5dfaefc5f.015e6ebcc489ecff.5a35a041044a8b35.d41ff2265260b54e
+ 4913613e2bf21499.d3c561029ef6a223.86d6625a05cbf14f.d7d7d9f19d8529cf
+ 50c2178d6ddf70c1
+ after
+ 4ecd5f8858e3ed1f.98285855de302698.49e341f32ab286b2.c0183953e1885ae9
+ fa5c7f91a2add89b.b643145163ca2cb5.8f7d6918c446fbba.eb4e66c0f2e5da8f
+ 0000000000000000.0000000000000000.8f7d6918c44686b2.eb4e66c0e188da8f
+ 4913613e2bf21499.d3c561029ef6a223.86d6625a05cbf14f.d7d7d9f19d8529cf
+ 50c2178d6ddf70c1
+
+VPBLENDW_128_0xD7(reg)
+ before
+ 9b2ba96660fac6ce.a3d11abaa383dd73.8ac6ea8f8d9f89cd.ef2e294fe4d4eb33
+ 146089e8126269a2.44385334636f1319.80ac03cf2c0fdfa8.7107730cbc71330e
+ 17abb57f1ea493eb.0812899885c272b8.13c2aa2e17d3dd61.e82ebb7eaaaf860b
+ 00592897214b8152.cb2d36d12886b57c.9d55da18eb76c2a4.306f7d8fc9999f57
+ 2496352c363b3c1e
+ after
+ 0000000000000000.0000000000000000.13c2aa2e2c0fdd61.7107bb7eaaaf860b
+ 146089e8126269a2.44385334636f1319.80ac03cf2c0fdfa8.7107730cbc71330e
+ 17abb57f1ea493eb.0812899885c272b8.13c2aa2e17d3dd61.e82ebb7eaaaf860b
+ 00592897214b8152.cb2d36d12886b57c.9d55da18eb76c2a4.306f7d8fc9999f57
+ 2496352c363b3c1e
+VPBLENDW_128_0xD7(mem)
+ before
+ a26e60420ca2168b.2bb6df9db6e46f86.6853d8cd66c99991.7cb18ffa4384c81c
+ 85c578bc67d9ecca.f40ed4fb79f99831.bd51ea785b97da21.0a22c63ebc8a2c75
+ a865fb8564ec7909.b7ad051f081939ff.a5f3e9bc24fa345b.a4f47a52f1132a5d
+ e91b648b1fe87872.cfde6d73fccd8e9d.fb044f86dc006269.a673a6a07fabfe7e
+ 6dea499601dfe384
+ after
+ a26e60420ca2168b.2bb6df9db6e46f86.6853d8cd66c99991.7cb18ffa4384c81c
+ 85c578bc67d9ecca.f40ed4fb79f99831.bd51ea785b97da21.0a22c63ebc8a2c75
+ 0000000000000000.0000000000000000.bd51d8cd66c9da21.7cb18ffabc8a2c75
+ e91b648b1fe87872.cfde6d73fccd8e9d.fb044f86dc006269.a673a6a07fabfe7e
+ 6dea499601dfe384
+
+VPBLENDW_128_0xD7(reg)
+ before
+ 53a65c9f143a161c.23b330b9b3d8a631.9aef0865f3a3d3b7.9d529ac2a0b52178
+ b5f3dc275348d2f2.31f9dafb3cc9be73.732ad360882643f8.66a7455d8b242db3
+ ef1dc69a5b9655b1.f1b8dd3dd7c57d64.b5dcc8d058e31b0d.31d1cc41ba594147
+ 5d701564c7afd906.3dbeb76b9fda9f2f.be51e521ff6597a2.dc9aac5c48601a60
+ 41ce609951467429
+ after
+ 0000000000000000.0000000000000000.b5dcc8d088261b0d.66a7cc41ba594147
+ b5f3dc275348d2f2.31f9dafb3cc9be73.732ad360882643f8.66a7455d8b242db3
+ ef1dc69a5b9655b1.f1b8dd3dd7c57d64.b5dcc8d058e31b0d.31d1cc41ba594147
+ 5d701564c7afd906.3dbeb76b9fda9f2f.be51e521ff6597a2.dc9aac5c48601a60
+ 41ce609951467429
+VPBLENDW_128_0xD7(mem)
+ before
+ 3e3b63e4f2160bce.5b38c5f134209a9c.f3d5e472b114e001.e9d525bf1738f262
+ adac342947dc9a7d.46c0d3ad3d73d620.edcade3c287efc06.91b385173fe869fa
+ 6bec4c546ba5de5f.785639057e36c73e.096923b72124ae69.1439ff9310023815
+ 55c928517a7c93a3.4e44f56394f5aaa1.217e2ecdb712b356.ccb191a029119b60
+ 176836ab23a2cd86
+ after
+ 3e3b63e4f2160bce.5b38c5f134209a9c.f3d5e472b114e001.e9d525bf1738f262
+ adac342947dc9a7d.46c0d3ad3d73d620.edcade3c287efc06.91b385173fe869fa
+ 0000000000000000.0000000000000000.edcae472b114fc06.e9d525bf3fe869fa
+ 55c928517a7c93a3.4e44f56394f5aaa1.217e2ecdb712b356.ccb191a029119b60
+ 176836ab23a2cd86
+
+VPBLENDW_128_0xD7(reg)
+ before
+ 4faaea1e9d400b34.450d450c916e7473.24d702351a3bbbf6.12d57b6c0755c6fb
+ d2c3aa6730779116.18851e71cc863efc.555b5de5ad9435e8.b939867f2cf8a481
+ faff70f17ad49ad7.abfc2f6d45d0ad69.3f1c00e1e98c5524.f078ccf243080a17
+ 24a93a2817e26324.d840f5ea1b587de7.3d65e99469b05755.945cc8b16790b1e7
+ 81b2f6a8b49c581e
+ after
+ 0000000000000000.0000000000000000.3f1c00e1ad945524.b939ccf243080a17
+ d2c3aa6730779116.18851e71cc863efc.555b5de5ad9435e8.b939867f2cf8a481
+ faff70f17ad49ad7.abfc2f6d45d0ad69.3f1c00e1e98c5524.f078ccf243080a17
+ 24a93a2817e26324.d840f5ea1b587de7.3d65e99469b05755.945cc8b16790b1e7
+ 81b2f6a8b49c581e
+VPBLENDW_128_0xD7(mem)
+ before
+ 9346d2c34838b9e7.ad0e0378a22d28a9.7c1cead6682b69a1.ab84136ac98b7629
+ a7e4d8ee3c71916f.ef7bc74db7422511.735b8c1c48552ec4.e5c37acfa6aaf049
+ 97578515ae529be1.473a8313f3ac9508.99ca56a7d8e0887c.476f1a2f9b98ff64
+ 406d5425b9e8956a.11973236f2f7b53b.ca35c56533da33f4.2cd4f0f645e1df24
+ f23ef7913f11ce35
+ after
+ 9346d2c34838b9e7.ad0e0378a22d28a9.7c1cead6682b69a1.ab84136ac98b7629
+ a7e4d8ee3c71916f.ef7bc74db7422511.735b8c1c48552ec4.e5c37acfa6aaf049
+ 0000000000000000.0000000000000000.735bead6682b2ec4.ab84136aa6aaf049
+ 406d5425b9e8956a.11973236f2f7b53b.ca35c56533da33f4.2cd4f0f645e1df24
+ f23ef7913f11ce35
+
+VPBLENDW_128_0xB5(reg)
+ before
+ f4f82b6a25b50644.7ef0c1087a3e3936.aae0d0234fb0c156.e3685341754eea59
+ 8d5088ef9558c4fd.2dad49ac0d604470.6c605944a662f405.be2f7e27bc496ad6
+ 1b900b8a2887430b.297066fc8d5b7145.b462c90794998bf3.3855c10321d66e98
+ f905aea97ccdc01b.4e0596e3163a7de0.de331dd6b4e2c2cc.2da898c2c201b4cb
+ 79f27f4ebbd7f69a
+ after
+ 0000000000000000.0000000000000000.b462594494998bf3.be2fc103bc496e98
+ 8d5088ef9558c4fd.2dad49ac0d604470.6c605944a662f405.be2f7e27bc496ad6
+ 1b900b8a2887430b.297066fc8d5b7145.b462c90794998bf3.3855c10321d66e98
+ f905aea97ccdc01b.4e0596e3163a7de0.de331dd6b4e2c2cc.2da898c2c201b4cb
+ 79f27f4ebbd7f69a
+VPBLENDW_128_0xB5(mem)
+ before
+ f700f3942763f132.82fb6fb72db677d9.7838544fc509246e.461f4f1fa3c8d53e
+ 859e6f8122b160be.14be4a20d6cfa4f0.83d41c2bb5d5221b.48725e4dfcd8fff2
+ fe986f00c9cd006b.099a395013a3830d.4ba76b6303a93212.407843cc5c9c7d97
+ 3eb96ffc38c48d65.bfda39b381be4fdb.ac7bbbe3ca91117f.8a7dfb085ea38bd7
+ 82cc836d9f76655e
+ after
+ f700f3942763f132.82fb6fb72db677d9.7838544fc509246e.461f4f1fa3c8d53e
+ 859e6f8122b160be.14be4a20d6cfa4f0.83d41c2bb5d5221b.48725e4dfcd8fff2
+ 0000000000000000.0000000000000000.83d4544fb5d5221b.461f5e4da3c8fff2
+ 3eb96ffc38c48d65.bfda39b381be4fdb.ac7bbbe3ca91117f.8a7dfb085ea38bd7
+ 82cc836d9f76655e
+
+VPBLENDW_128_0xB5(reg)
+ before
+ 84b3d667baa346d9.21cfec638aa2c3d7.90cc47b5bcac4507.811d8a98279a7b90
+ ec7cf0634cb56bf4.83a46020db715ded.d9ba5ec25efaa03c.a859536c35cf2c6f
+ 1674cdcbf038105b.3f05491f484018d5.f7f17b4606349e27.fcfb924d103cdf48
+ 5ee76a0d42b970b9.33be224cec18b0b9.44bd98ae4ee47974.59cec425d5ee5148
+ 9aa064e2a0f03e9b
+ after
+ 0000000000000000.0000000000000000.f7f15ec206349e27.a859924d35cfdf48
+ ec7cf0634cb56bf4.83a46020db715ded.d9ba5ec25efaa03c.a859536c35cf2c6f
+ 1674cdcbf038105b.3f05491f484018d5.f7f17b4606349e27.fcfb924d103cdf48
+ 5ee76a0d42b970b9.33be224cec18b0b9.44bd98ae4ee47974.59cec425d5ee5148
+ 9aa064e2a0f03e9b
+VPBLENDW_128_0xB5(mem)
+ before
+ 9d3bee6e8c4e616c.1f20c293dfc3c8ba.3a9b6893e407e1c5.1e6ab364d2986dce
+ 3d6cdeb7b51577e8.b76dd1cb63e3540b.2f6895e14b186626.df43c7d62fdcb8e2
+ 55ffb0a838503c3b.8118932069a44f58.f0f027203e57fc08.e496d06f003a945b
+ c3c0e12d310b6c90.d96e04fd8d92f74c.5801993dd8d15f96.89adca9be2403ee6
+ 2ad5b2c6707af12f
+ after
+ 9d3bee6e8c4e616c.1f20c293dfc3c8ba.3a9b6893e407e1c5.1e6ab364d2986dce
+ 3d6cdeb7b51577e8.b76dd1cb63e3540b.2f6895e14b186626.df43c7d62fdcb8e2
+ 0000000000000000.0000000000000000.2f6868934b186626.1e6ac7d6d298b8e2
+ c3c0e12d310b6c90.d96e04fd8d92f74c.5801993dd8d15f96.89adca9be2403ee6
+ 2ad5b2c6707af12f
+
+VPBLENDW_128_0xB5(reg)
+ before
+ 245a825c4673ebe1.617aec32bb53c214.1abb21d06c3a8694.4265672536914afd
+ d18838c901b766a9.0dfb4da4f233fbf2.a24be504a22638dc.8ce90ec373a37a69
+ 8eabcf793dd29f32.a10d806df3b8d357.cb6a4c06c9e54bcf.10590802ab14ab05
+ b70e44d89551d129.fb7d027ad9ec056e.f36452408000f91a.ac81d3d0fbef99fe
+ 3a2cea187f41ff7f
+ after
+ 0000000000000000.0000000000000000.cb6ae504c9e54bcf.8ce9080273a3ab05
+ d18838c901b766a9.0dfb4da4f233fbf2.a24be504a22638dc.8ce90ec373a37a69
+ 8eabcf793dd29f32.a10d806df3b8d357.cb6a4c06c9e54bcf.10590802ab14ab05
+ b70e44d89551d129.fb7d027ad9ec056e.f36452408000f91a.ac81d3d0fbef99fe
+ 3a2cea187f41ff7f
+VPBLENDW_128_0xB5(mem)
+ before
+ 9728cac652149ab5.a8ff9253a5bf393a.f5174db8c1dd4e64.7584f41f60057f68
+ a03fedc6907726cb.bdc8b4540aa81310.6ca7df11c6976a65.ac172d10087f1866
+ 2f3ed10556735eee.52b6a94960999b58.3df933730525159c.f669f97d11fb02bf
+ 21f1f16dc016ff4a.c3156a9c421d0cbd.42d8c6c999930a36.adc654d41a047720
+ 2e7a3a80bc26b335
+ after
+ 9728cac652149ab5.a8ff9253a5bf393a.f5174db8c1dd4e64.7584f41f60057f68
+ a03fedc6907726cb.bdc8b4540aa81310.6ca7df11c6976a65.ac172d10087f1866
+ 0000000000000000.0000000000000000.6ca74db8c6976a65.75842d1060051866
+ 21f1f16dc016ff4a.c3156a9c421d0cbd.42d8c6c999930a36.adc654d41a047720
+ 2e7a3a80bc26b335
+
+VPBLENDW_128_0x85(reg)
+ before
+ d6d1a8ec95eef4a9.5324c9ebe96bc50a.6c30f4bb4cc1a3ec.581212ff9eed065f
+ ff16998641e77429.9fa3d66ced7f6c5b.a95544111b0f9c91.5c7195013240c542
+ 079709b95b9d7061.e23992dae95caf68.d5ce550a4a963357.28c2cabb6e97020b
+ 489ef4f17f9d23fc.f8b37b23f8114b5e.4ee9231276dfa3eb.99d12d1970ff7ae7
+ 8b6a3b075483e902
+ after
+ 0000000000000000.0000000000000000.d5ce44111b0f9c91.5c71cabb3240020b
+ ff16998641e77429.9fa3d66ced7f6c5b.a95544111b0f9c91.5c7195013240c542
+ 079709b95b9d7061.e23992dae95caf68.d5ce550a4a963357.28c2cabb6e97020b
+ 489ef4f17f9d23fc.f8b37b23f8114b5e.4ee9231276dfa3eb.99d12d1970ff7ae7
+ 8b6a3b075483e902
+VPBLENDW_128_0x85(mem)
+ before
+ da586f71352f0b88.1f78569a4a72cba6.bdde0c3237a7fc69.6ff0ab953a7829f8
+ 626944442f109ba4.e8712c2158a8a20c.0e84c1f3c12c7eb4.9430e7ff33ec012b
+ ff67396a5f315682.ffd471f044cce5da.c5721752b3ab8c6c.18f4d5bdfcc86630
+ 8e1fc7d1e09ef850.c1ef2175aa69cfbc.bf73893b2831e3bc.598a7039329795b2
+ b23db4e070e5ca5e
+ after
+ da586f71352f0b88.1f78569a4a72cba6.bdde0c3237a7fc69.6ff0ab953a7829f8
+ 626944442f109ba4.e8712c2158a8a20c.0e84c1f3c12c7eb4.9430e7ff33ec012b
+ 0000000000000000.0000000000000000.bdde0c32c12cfc69.6ff0ab9533ec012b
+ 8e1fc7d1e09ef850.c1ef2175aa69cfbc.bf73893b2831e3bc.598a7039329795b2
+ b23db4e070e5ca5e
+
+VPBLENDW_128_0x85(reg)
+ before
+ 7e589e1f533e40df.e95d6b64cf633d37.880c391a270b9d5d.d855939a3cc93ed1
+ 1b282961762f35e2.eceda20e488de066.b179b34d563f8b69.ece2b15b0c7f5bd7
+ e3f950127543e312.759be7bd65289e07.98808d79d490d58e.d7e85f6bb460f4f9
+ 3417129ded07861c.5f32b65c453e3246.996ec2093c8bb675.75311ab44f77c664
+ a18a5d24fad08c43
+ after
+ 0000000000000000.0000000000000000.9880b34d563f8b69.ece25f6b0c7ff4f9
+ 1b282961762f35e2.eceda20e488de066.b179b34d563f8b69.ece2b15b0c7f5bd7
+ e3f950127543e312.759be7bd65289e07.98808d79d490d58e.d7e85f6bb460f4f9
+ 3417129ded07861c.5f32b65c453e3246.996ec2093c8bb675.75311ab44f77c664
+ a18a5d24fad08c43
+VPBLENDW_128_0x85(mem)
+ before
+ 39bea4a5d07803c3.68ce68707a065cac.86808cd701dd5a50.108e4e6b2bba6bcd
+ 189b6b25ed7ae710.dd6950f7b7cc9f6d.c64fe41bb811d051.592e2e0a3cab3040
+ 1aeb2e8f6ee2f455.ed36c49c40e68c0c.fb6c391283e45175.d0995d520cea407a
+ 1b7c6acf6ebde5bf.f67fc2ccb2df5e35.01a309a9806498e6.d11ad6b03602d928
+ b8fe988e577f35f6
+ after
+ 39bea4a5d07803c3.68ce68707a065cac.86808cd701dd5a50.108e4e6b2bba6bcd
+ 189b6b25ed7ae710.dd6950f7b7cc9f6d.c64fe41bb811d051.592e2e0a3cab3040
+ 0000000000000000.0000000000000000.86808cd7b8115a50.108e4e6b3cab3040
+ 1b7c6acf6ebde5bf.f67fc2ccb2df5e35.01a309a9806498e6.d11ad6b03602d928
+ b8fe988e577f35f6
+
+VPBLENDW_128_0x85(reg)
+ before
+ e1919c590aed9090.f6189ad10a167779.529146f3a8435393.b3c0d0cdcb9d63d3
+ a71fe07eebd928a1.898c3a815df966b0.5eb84a7ebf9fa5d2.ef8e08687f996b66
+ 68f35e6797ce37d5.afa4c7cb84736e8f.7740ccd7927e91a0.90db2f68b9666fcc
+ 7f5b1482aa59fad9.432bbb9b9a8f4a44.f774c76cbe6c52a6.7171c0b894102a30
+ 701d37432ca157bf
+ after
+ 0000000000000000.0000000000000000.77404a7ebf9fa5d2.ef8e2f687f996fcc
+ a71fe07eebd928a1.898c3a815df966b0.5eb84a7ebf9fa5d2.ef8e08687f996b66
+ 68f35e6797ce37d5.afa4c7cb84736e8f.7740ccd7927e91a0.90db2f68b9666fcc
+ 7f5b1482aa59fad9.432bbb9b9a8f4a44.f774c76cbe6c52a6.7171c0b894102a30
+ 701d37432ca157bf
+VPBLENDW_128_0x85(mem)
+ before
+ 68ab11f79e28b3a5.48a1fe3abf05ac59.23ef94debc59b7f8.3ba237a8def62593
+ 34e7c8bf05aef90d.1e1316fb725e8a00.2abacd7e05de71da.a01418f68fa74611
+ b29cda877e41e623.5ffb5a3160f0d07b.335ae26992293313.801767c46c0bf1cd
+ bc98c23c25ec3615.66a6c5482448ba76.1c9950897e46bad2.38f71e7d12af6172
+ 24003b8e1c1ed3ad
+ after
+ 68ab11f79e28b3a5.48a1fe3abf05ac59.23ef94debc59b7f8.3ba237a8def62593
+ 34e7c8bf05aef90d.1e1316fb725e8a00.2abacd7e05de71da.a01418f68fa74611
+ 0000000000000000.0000000000000000.23ef94de05deb7f8.3ba237a88fa74611
+ bc98c23c25ec3615.66a6c5482448ba76.1c9950897e46bad2.38f71e7d12af6172
+ 24003b8e1c1ed3ad
+
+VPBLENDW_128_0x29(reg)
+ before
+ a07dba6126e48329.30a5fcc814bba50d.8e5f53ac5bf2849c.bf4491cce642c241
+ 08bc9563cd8eac93.e89005186abbef37.357400c9a178699a.fa26231de528078d
+ b807ca00ada78c97.c225581940f7cfc0.b52fc80c9068a51b.a70d8168970544e1
+ 0cac54a561bc5ce0.983071b5b57c02d4.6cdea8dfc74d76cc.a3c3289919e4366a
+ cb16929c87d19953
+ after
+ 0000000000000000.0000000000000000.357400c99068699a.a70d231de52844e1
+ 08bc9563cd8eac93.e89005186abbef37.357400c9a178699a.fa26231de528078d
+ b807ca00ada78c97.c225581940f7cfc0.b52fc80c9068a51b.a70d8168970544e1
+ 0cac54a561bc5ce0.983071b5b57c02d4.6cdea8dfc74d76cc.a3c3289919e4366a
+ cb16929c87d19953
+VPBLENDW_128_0x29(mem)
+ before
+ f9d03d5dfcd828c9.60f52fbc85575b1b.477dccdae254439e.b4cb9bb0dfb41658
+ 0abea4c99406a0f8.102e57b3b607c4f3.acd7e573e68e4f4b.eb439de97628c26c
+ dbac43ca6c66bd0b.78a5c8f59055d215.a10c396cda33e306.6b91abf82835b6b4
+ 4665964d9f053b2f.f4a57feeadcfc12c.03e642b1dc51b8fc.9203bf4890682edb
+ bae4d7454b4c658e
+ after
+ f9d03d5dfcd828c9.60f52fbc85575b1b.477dccdae254439e.b4cb9bb0dfb41658
+ 0abea4c99406a0f8.102e57b3b607c4f3.acd7e573e68e4f4b.eb439de97628c26c
+ 0000000000000000.0000000000000000.477de573e68e439e.eb439de9dfb4c26c
+ 4665964d9f053b2f.f4a57feeadcfc12c.03e642b1dc51b8fc.9203bf4890682edb
+ bae4d7454b4c658e
+
+VPBLENDW_128_0x29(reg)
+ before
+ 407fee5bf46d9878.28b71a3f4aeed590.e079770aac00cfe6.ae327f2e08f38d59
+ 812101f627580247.5d6c4a8b882d4859.976eacb5277536ec.7fbc69cf79261c48
+ d7160a828198e0a4.c151a21d76ce50b6.77d11b5bbab833ed.50507d804bf522f6
+ 9faa076b9eb96f3d.31329ee02fdea9d4.dbebbe6801580293.feb9382d9b6c5a8e
+ 65c515c38597823d
+ after
+ 0000000000000000.0000000000000000.976eacb5bab836ec.505069cf792622f6
+ 812101f627580247.5d6c4a8b882d4859.976eacb5277536ec.7fbc69cf79261c48
+ d7160a828198e0a4.c151a21d76ce50b6.77d11b5bbab833ed.50507d804bf522f6
+ 9faa076b9eb96f3d.31329ee02fdea9d4.dbebbe6801580293.feb9382d9b6c5a8e
+ 65c515c38597823d
+VPBLENDW_128_0x29(mem)
+ before
+ 613e902c2483542f.3529f31d1948e8be.87dbbbc2d0680edf.1f0b93489adede8a
+ cef12556943b8d8f.f5deca058ed08ad3.a01874ae74793c03.9e7c95681ed8047f
+ 88aa512cf2cce88a.3c17888d9add8f27.58b44591381cee6b.b689c0322bd1b01e
+ 6b358f995941224b.641e2a23d8fc3466.8b7daa55375de243.c28011145d561e12
+ 1dab83794ff28908
+ after
+ 613e902c2483542f.3529f31d1948e8be.87dbbbc2d0680edf.1f0b93489adede8a
+ cef12556943b8d8f.f5deca058ed08ad3.a01874ae74793c03.9e7c95681ed8047f
+ 0000000000000000.0000000000000000.87db74ae74790edf.9e7c95689ade047f
+ 6b358f995941224b.641e2a23d8fc3466.8b7daa55375de243.c28011145d561e12
+ 1dab83794ff28908
+
+VPBLENDW_128_0x29(reg)
+ before
+ 255712cc9e312eac.535e5b8be6a6f7ff.ca40ab32e5b8b53d.153d1fe78d49d2b8
+ 34d0ba7be59f49a9.1cf031edb40823d2.cac907265c9d4d58.d2c1213457eb7bf6
+ a86177f1c0c915ab.a2b98dabe07261ef.c0053a6bda383963.9dd52a26b14f9828
+ db58469acc3bcf60.c183ecb285f06e83.083f406dfa14b509.5445b9abb682e67b
+ d2dc47ae828f211b
+ after
+ 0000000000000000.0000000000000000.cac90726da384d58.9dd5213457eb9828
+ 34d0ba7be59f49a9.1cf031edb40823d2.cac907265c9d4d58.d2c1213457eb7bf6
+ a86177f1c0c915ab.a2b98dabe07261ef.c0053a6bda383963.9dd52a26b14f9828
+ db58469acc3bcf60.c183ecb285f06e83.083f406dfa14b509.5445b9abb682e67b
+ d2dc47ae828f211b
+VPBLENDW_128_0x29(mem)
+ before
+ f368511a32820533.2bff21e3a47fb372.541bc9ecc08f06b9.fec5169859befcf6
+ 93b354dde1684df0.f2a40736e523fd8d.394da046ac5ae5be.fee1b75892c14bd7
+ 8d8acbe2ac4cb67d.8d91f1002bb3e85e.4be5edad665dc6be.64e01f1942a9de58
+ bfb93215af3afc07.5913dcae10b9b191.66ae2d0b09a566e4.8b0e4b480402f125
+ d1b7354f7459bfe8
+ after
+ f368511a32820533.2bff21e3a47fb372.541bc9ecc08f06b9.fec5169859befcf6
+ 93b354dde1684df0.f2a40736e523fd8d.394da046ac5ae5be.fee1b75892c14bd7
+ 0000000000000000.0000000000000000.541ba046ac5a06b9.fee1b75859be4bd7
+ bfb93215af3afc07.5913dcae10b9b191.66ae2d0b09a566e4.8b0e4b480402f125
+ d1b7354f7459bfe8
+
+VMOVUPS_EtoG_256(reg)
+ before
+ 9127db9c2f398650.040c0563043fdbba.b075c5aa33c394d1.6576da4eb13d815d
+ 27a93899d12f7f07.374fc1b6ca660ec1.ef05a7622d5dcccb.260772617b31d254
+ ee8b48b4f5c6e9ba.364de1fb1abb5248.730d7e409d11962a.842e712f838e16f6
+ 44170858378afe14.dcd4e11f124b637d.96db46b21c6d2e9b.5ab751a6e45f096e
+ 866e90b1bab167e9
+ after
+ 9127db9c2f398650.040c0563043fdbba.b075c5aa33c394d1.6576da4eb13d815d
+ 27a93899d12f7f07.374fc1b6ca660ec1.ef05a7622d5dcccb.260772617b31d254
+ ee8b48b4f5c6e9ba.364de1fb1abb5248.730d7e409d11962a.842e712f838e16f6
+ ee8b48b4f5c6e9ba.364de1fb1abb5248.730d7e409d11962a.842e712f838e16f6
+ 866e90b1bab167e9
+VMOVUPS_EtoG_256(mem)
+ before
+ e21ea83d228eeb93.849a72f13407fbc2.04ae3d0cce21fc8a.b5b9fc2349fdd0ca
+ 4c95183437045297.096084eb87ca1c70.8ca871b0694ada9b.2cf49bffbd4bb762
+ 9e9d5983161f5822.31b539b2cd5e9cc9.4e8efaf600d0b9dd.57d81fb216e52010
+ b603e816daeab860.57e48eb3a250b879.282c53c9aec1557c.92b084a9f057477f
+ 39cac64ee62c685c
+ after
+ e21ea83d228eeb93.849a72f13407fbc2.04ae3d0cce21fc8a.b5b9fc2349fdd0ca
+ 4c95183437045297.096084eb87ca1c70.8ca871b0694ada9b.2cf49bffbd4bb762
+ e21ea83d228eeb93.849a72f13407fbc2.04ae3d0cce21fc8a.b5b9fc2349fdd0ca
+ b603e816daeab860.57e48eb3a250b879.282c53c9aec1557c.92b084a9f057477f
+ 39cac64ee62c685c
+
+VMOVUPS_EtoG_256(reg)
+ before
+ a870e20e94f0be53.6e9342daa0712f7c.d63b7d58a02bac2e.f44df8178f2969a3
+ 3befd356972f860f.a419e2ba83c079a2.0c04040e667bb492.8fbf65cbc013b27f
+ 4e9395908b76fb3d.326144a1a0e45200.538c1e428dcd0b51.d64c17d25d8bec3c
+ 3da8242a0b505b88.f537e47d12e875c0.091fc75eb3acee18.a3c18916819dd205
+ d3ea378448562106
+ after
+ a870e20e94f0be53.6e9342daa0712f7c.d63b7d58a02bac2e.f44df8178f2969a3
+ 3befd356972f860f.a419e2ba83c079a2.0c04040e667bb492.8fbf65cbc013b27f
+ 4e9395908b76fb3d.326144a1a0e45200.538c1e428dcd0b51.d64c17d25d8bec3c
+ 4e9395908b76fb3d.326144a1a0e45200.538c1e428dcd0b51.d64c17d25d8bec3c
+ d3ea378448562106
+VMOVUPS_EtoG_256(mem)
+ before
+ 43939d09cfc1956c.647a7d8fb349e09d.c9663f39f6d99f0e.8809fbd074a49993
+ cd88378f31ebea63.1f559a2b20eec728.8bbbd0c167c28c17.2d95b7036b42476d
+ 4e9482048bdfdb17.ca847969edca4bd4.1502130182aff707.5511f66335113553
+ a285f952f8a925b3.c15415b8b76aa94e.440784e562ac9d09.5ac7b45c6d9d9ff0
+ 9904ed5aaf73c1f2
+ after
+ 43939d09cfc1956c.647a7d8fb349e09d.c9663f39f6d99f0e.8809fbd074a49993
+ cd88378f31ebea63.1f559a2b20eec728.8bbbd0c167c28c17.2d95b7036b42476d
+ 43939d09cfc1956c.647a7d8fb349e09d.c9663f39f6d99f0e.8809fbd074a49993
+ a285f952f8a925b3.c15415b8b76aa94e.440784e562ac9d09.5ac7b45c6d9d9ff0
+ 9904ed5aaf73c1f2
+
+VMOVUPS_EtoG_256(reg)
+ before
+ 6f149ec9981ed602.a625186795568463.60116b8119591d41.f496a05923c63a4a
+ 3643c115c42a1bce.34415b2e7df0b455.02077531b023e35a.017be14ae2088af5
+ 4bdd54abce24cc02.29a53f93cd8670b2.0582313417543645.4881c5a2ba7f4837
+ 0a2e53f55297254a.611c3e82a02175a9.c4ce9af7eb7954ad.a375c74ec836313c
+ ef23643b2839012f
+ after
+ 6f149ec9981ed602.a625186795568463.60116b8119591d41.f496a05923c63a4a
+ 3643c115c42a1bce.34415b2e7df0b455.02077531b023e35a.017be14ae2088af5
+ 4bdd54abce24cc02.29a53f93cd8670b2.0582313417543645.4881c5a2ba7f4837
+ 4bdd54abce24cc02.29a53f93cd8670b2.0582313417543645.4881c5a2ba7f4837
+ ef23643b2839012f
+VMOVUPS_EtoG_256(mem)
+ before
+ 08571654f595743d.cf81b861ed0f6151.b874d6e713cf7e64.9a36ade4c71e763e
+ cadd5b854b554591.f62381593a19bdc3.0a7783ae419b490f.e507646947cddba6
+ 1181aeb947853158.dc60a84bd640744d.33f3bfc4469290d8.008ebdf00914bd8f
+ b80e8bde0432f3be.db842ba25c10c49b.0fb208133fbf10e8.4615b3e7a67e59a5
+ 15e842b9bc98eb95
+ after
+ 08571654f595743d.cf81b861ed0f6151.b874d6e713cf7e64.9a36ade4c71e763e
+ cadd5b854b554591.f62381593a19bdc3.0a7783ae419b490f.e507646947cddba6
+ 08571654f595743d.cf81b861ed0f6151.b874d6e713cf7e64.9a36ade4c71e763e
+ b80e8bde0432f3be.db842ba25c10c49b.0fb208133fbf10e8.4615b3e7a67e59a5
+ 15e842b9bc98eb95
+
+VSQRTSS_128(reg)
+ before
+ c75566d2e7edae0b.9d526fe09f6749ee.50db06ca6916e759.7a81d889482e846e
+ baa71c9ec109e0b2.9b17d4a93330ed15.97b1332f98dd1932.4f2bad107ceca994
+ 48295f89e979ba37.8e2a3826dd9a9c5e.0c51b03d86f298d2.6c7e0396f7043b86
+ ce282b00f9c87b46.52571643b8b011f6.0a087860cedf9ee6.ac445406d682f671
+ eb4b1e4c35739581
+ after
+ 0000000000000000.0000000000000000.97b1332f98dd1932.4f2bad10ffc00000
+ baa71c9ec109e0b2.9b17d4a93330ed15.97b1332f98dd1932.4f2bad107ceca994
+ 48295f89e979ba37.8e2a3826dd9a9c5e.0c51b03d86f298d2.6c7e0396f7043b86
+ ce282b00f9c87b46.52571643b8b011f6.0a087860cedf9ee6.ac445406d682f671
+ eb4b1e4c35739581
+VSQRTSS_128(mem)
+ before
+ 055ddc542ee2d5e1.a9f07c6d8d825d8a.c36aebede07e0908.ef2387050d33681a
+ d5470a0ae0db72be.33cd4e3d42349daf.bc2e310e721140c2.16ecd996de773219
+ 39d5245a646b2844.c90b9eddb3697763.1b7166948a74724d.dbaf6b81dd393790
+ 0cd2a730d99db29e.c8f667b87dad264f.bbfd056a43b35bd8.9aba3830a704b42b
+ af583c11d865e595
+ after
+ 055ddc542ee2d5e1.a9f07c6d8d825d8a.c36aebede07e0908.ef2387050d33681a
+ d5470a0ae0db72be.33cd4e3d42349daf.bc2e310e721140c2.16ecd996de773219
+ 0000000000000000.0000000000000000.bc2e310e721140c2.16ecd99626564ef5
+ 0cd2a730d99db29e.c8f667b87dad264f.bbfd056a43b35bd8.9aba3830a704b42b
+ af583c11d865e595
+
+VSQRTSS_128(reg)
+ before
+ 75d4738f0be6067b.290c0e79587dcdf9.8ad9a5393b8de822.779f8a7cb9dbb68c
+ 4a7bd915dc165288.6e4dd51f00183580.6c0154ce8a94f786.2d2371b509f74098
+ 89996b11e87e0669.b5637810ea79a560.cabb71e2054e8f27.b75537044f13b426
+ 8d7a24eecaac5eca.dc18733634addac4.0051f7e14948eeb3.f3005752a63ccf63
+ bbf24d8c2a7d4d7a
+ after
+ 0000000000000000.0000000000000000.6c0154ce8a94f786.2d2371b547427416
+ 4a7bd915dc165288.6e4dd51f00183580.6c0154ce8a94f786.2d2371b509f74098
+ 89996b11e87e0669.b5637810ea79a560.cabb71e2054e8f27.b75537044f13b426
+ 8d7a24eecaac5eca.dc18733634addac4.0051f7e14948eeb3.f3005752a63ccf63
+ bbf24d8c2a7d4d7a
+VSQRTSS_128(mem)
+ before
+ edf5959ef8e3ea98.b46a00191f2b9556.bd39437ffabe90d9.6b0fe237f10d4ed3
+ 63d6ac752b7862e8.58b4fbfc8288e8b9.369163d657bb83cb.65432e509929eb36
+ fb610cfbe04a7098.d7a61204904e93a1.21ee4f2768ad6ec5.4b38d799de290386
+ 8f62331e3265d1d1.8c8a3f9ee409d2b8.5c1a835e47a20ef4.7939da7c5c98d06f
+ 4b933267ae028f9f
+ after
+ edf5959ef8e3ea98.b46a00191f2b9556.bd39437ffabe90d9.6b0fe237f10d4ed3
+ 63d6ac752b7862e8.58b4fbfc8288e8b9.369163d657bb83cb.65432e509929eb36
+ 0000000000000000.0000000000000000.369163d657bb83cb.65432e50ffc00000
+ 8f62331e3265d1d1.8c8a3f9ee409d2b8.5c1a835e47a20ef4.7939da7c5c98d06f
+ 4b933267ae028f9f
+
+VSQRTSS_128(reg)
+ before
+ 1d92dbc470f47cbf.fca59cc83ed440c1.d2ad80341b46e0aa.c1e37c6713a51f84
+ 4b82d1013ff9d27e.1ff6c4e71fa37a94.065bd134d090fa24.2d13b52ee6c35ca0
+ 31af1189b69ece86.d2202566f2de3b76.85e02c09a0735cd2.7d77aaa0dc068274
+ 2a6495c7726eac83.f2f03d31d2923f92.a9888f1e267c415f.8bdbd7a7127d4d2e
+ 340ab831a33179f8
+ after
+ 0000000000000000.0000000000000000.065bd134d090fa24.2d13b52effc00000
+ 4b82d1013ff9d27e.1ff6c4e71fa37a94.065bd134d090fa24.2d13b52ee6c35ca0
+ 31af1189b69ece86.d2202566f2de3b76.85e02c09a0735cd2.7d77aaa0dc068274
+ 2a6495c7726eac83.f2f03d31d2923f92.a9888f1e267c415f.8bdbd7a7127d4d2e
+ 340ab831a33179f8
+VSQRTSS_128(mem)
+ before
+ 54d2ca28ac30c1fe.94ef5b290ff5a722.5c328734dbca4214.d09ef4e1ff36e678
+ c7fd887a4985e26d.ca9a5f1a27bffd0f.eab27f5b2a93ff2a.546f5abdc62d87c8
+ 6a586e12943d9871.28b29b075959e8f6.793ca292dbf833fd.9248ba1e17ee60fc
+ 17aff8dcab639f35.0a830d5a3e4ea482.e59c6bc6090599bc.e67311708f04acc0
+ ad3d5c20cafba8bf
+ after
+ 54d2ca28ac30c1fe.94ef5b290ff5a722.5c328734dbca4214.d09ef4e1ff36e678
+ c7fd887a4985e26d.ca9a5f1a27bffd0f.eab27f5b2a93ff2a.546f5abdc62d87c8
+ 0000000000000000.0000000000000000.eab27f5b2a93ff2a.546f5abdffc00000
+ 17aff8dcab639f35.0a830d5a3e4ea482.e59c6bc6090599bc.e67311708f04acc0
+ ad3d5c20cafba8bf
+
+VSQRTPS_128(reg)
+ before
+ 41f19698636090a6.abcea3c4aa03b2e6.cb59af80752b6f5f.0a9d56e1d0c7ef91
+ ffddbb46f6be9f21.0281e9b6ac298eaf.c97f7fe5977b833a.c40cdfd14d49efa8
+ 434bc89420a112db.f893489ecee2eebd.5f4379f642ca1dbf.efb582809b97562f
+ 6988b7f07c962580.69d23b682b3a903c.e8ef971e12a47899.6764bcdcd7bddf4f
+ 08e507d01dc84737
+ after
+ 41f19698636090a6.abcea3c4aa03b2e6.cb59af80752b6f5f.0a9d56e1d0c7ef91
+ 0000000000000000.0000000000000000.4f5fb35b4120d821.ffc00000ffc00000
+ 434bc89420a112db.f893489ecee2eebd.5f4379f642ca1dbf.efb582809b97562f
+ 6988b7f07c962580.69d23b682b3a903c.e8ef971e12a47899.6764bcdcd7bddf4f
+ 08e507d01dc84737
+VSQRTPS_128(mem)
+ before
+ ae04e14887c44a11.cde186c5a72814bd.31083f00e03b2e57.c2d0d7c8a296d175
+ 358cc63034bba409.cb9f307e3ce31a3e.2c02ce5308f3853b.473234628e2c64ff
+ 794b30743dbb104d.bf11b189d85474af.368c664bbf6d5013.d561aa5773f06de2
+ 560b9d00c1d04b06.0582065116065ebb.2a7282d622b64c0c.c6a93513ed7028ca
+ 7855d2029737d065
+ after
+ ae04e14887c44a11.cde186c5a72814bd.31083f00e03b2e57.c2d0d7c8a296d175
+ 0000000000000000.0000000000000000.383ac25bffc00000.ffc00000ffc00000
+ 794b30743dbb104d.bf11b189d85474af.368c664bbf6d5013.d561aa5773f06de2
+ 560b9d00c1d04b06.0582065116065ebb.2a7282d622b64c0c.c6a93513ed7028ca
+ 7855d2029737d065
+
+VSQRTPS_128(reg)
+ before
+ 45b37c900dd2a25d.a89987c0d9041163.f93d29429386140e.e6809fdf4cd93551
+ 8b0d2f29ecccd95e.4ac16da0a3651e8e.f79018c9ea5ed155.458137515ae2c710
+ a4b0e73acfb1b215.1a4fc88d3bff2db3.5bc5ce50b81dd23c.2342c81a68debd72
+ ede8a02d530e6a2e.f30e1571bcdcfbff.81294844984c536e.5c8fcd2591d8d4a6
+ cb34c25ff1dcc8d6
+ after
+ 45b37c900dd2a25d.a89987c0d9041163.f93d29429386140e.e6809fdf4cd93551
+ 0000000000000000.0000000000000000.4d9f1eb5ffc00000.315f4d7f5428d9e7
+ a4b0e73acfb1b215.1a4fc88d3bff2db3.5bc5ce50b81dd23c.2342c81a68debd72
+ ede8a02d530e6a2e.f30e1571bcdcfbff.81294844984c536e.5c8fcd2591d8d4a6
+ cb34c25ff1dcc8d6
+VSQRTPS_128(mem)
+ before
+ 4efd23b2a5f7552e.c3015770146e3a54.b0ccd13a430a449e.c508801226798f98
+ c0b66d0bc83436db.8046076dac5d6134.2f5377d3eb95c3bb.83ad7424ff2fc366
+ fc2b1a5677a02809.8105ac92ba681979.4b708328d0873583.16661fe8bffb2b83
+ e027a980cd45e7e3.2288424ad71a9fd0.dfef72250fee5622.dc7d7dc90167029c
+ 303f8b336102865c
+ after
+ 4efd23b2a5f7552e.c3015770146e3a54.b0ccd13a430a449e.c508801226798f98
+ 0000000000000000.0000000000000000.ffc00000413c23d0.ffc0000032fcc28c
+ fc2b1a5677a02809.8105ac92ba681979.4b708328d0873583.16661fe8bffb2b83
+ e027a980cd45e7e3.2288424ad71a9fd0.dfef72250fee5622.dc7d7dc90167029c
+ 303f8b336102865c
+
+VSQRTPS_128(reg)
+ before
+ 6df843927c55f170.46779373e6312e96.c01cc601a1ff2ee5.c99cbeb6c3d6e2c3
+ f1f4a352edee7f84.0ce7551de070ba4e.b50d3323b4a40463.e342e5c7094a9493
+ 177fa6df51586e43.0c436c69d40d4736.5ea7851cab945bf7.0baf6244fd5629bd
+ 3ae549a54320f859.24575343e014917a.1736b858235c704c.1badb219b9065d6e
+ f1094f335c67ebd1
+ after
+ 6df843927c55f170.46779373e6312e96.c01cc601a1ff2ee5.c99cbeb6c3d6e2c3
+ 0000000000000000.0000000000000000.4f126ecaffc00000.2595d492ffc00000
+ 177fa6df51586e43.0c436c69d40d4736.5ea7851cab945bf7.0baf6244fd5629bd
+ 3ae549a54320f859.24575343e014917a.1736b858235c704c.1badb219b9065d6e
+ f1094f335c67ebd1
+VSQRTPS_128(mem)
+ before
+ 678fb77cff849013.b871861160d15a74.2eee869720915348.3c05c843b7867e0f
+ 5b0b65e2c16a0860.eb705b8d43f7cf3e.08d68151af914ac9.2962b24a03a0c2ec
+ a749d54fbb230fe3.312fc387891f9563.8cd9c15da91f322c.3a9771d7a436788e
+ 281583b10cbe60c9.e4f7ba69cdd4e690.97c4c0a72b48c69b.cbf1015836d3dca2
+ 38bc5e38530329d3
+ after
+ 678fb77cff849013.b871861160d15a74.2eee869720915348.3c05c843b7867e0f
+ 0000000000000000.0000000000000000.372ebb6930086349.3db91018ffc00000
+ a749d54fbb230fe3.312fc387891f9563.8cd9c15da91f322c.3a9771d7a436788e
+ 281583b10cbe60c9.e4f7ba69cdd4e690.97c4c0a72b48c69b.cbf1015836d3dca2
+ 38bc5e38530329d3
+
+VSQRTPS_256(reg)
+ before
+ dd4385e29a529cce.bb3aecf3cd44b83d.62173da1aca2fe71.0663fc1b5016c343
+ 16d471c4a54d713f.3a858b011cc3d36c.05da469ac1151bb1.b382f1a63598e54f
+ 3fb91d49107fe4d1.82c2dcc715466c82.2a8bd3c0a9ba77fd.7bed1932f6d7e8ec
+ b34088dd78753031.6fbd5b31d3da40aa.2e78df7fff1d4f00.3a6ff2adade18745
+ ccd6f70179c17f87
+ after
+ dd4385e29a529cce.bb3aecf3cd44b83d.62173da1aca2fe71.0663fc1b5016c343
+ 3f99ee3f27fff268.ffc000002a61617d.3505c86fffc00000.5dae3560ffc00000
+ 3fb91d49107fe4d1.82c2dcc715466c82.2a8bd3c0a9ba77fd.7bed1932f6d7e8ec
+ b34088dd78753031.6fbd5b31d3da40aa.2e78df7fff1d4f00.3a6ff2adade18745
+ ccd6f70179c17f87
+VSQRTPS_256(mem)
+ before
+ 0eeca41c73848cde.d0b3abec78ba920a.dd42842b72890b11.6beb66435fc8de67
+ da7e75e9ba356975.f15f84e3adda4609.a91dd4a20f6289e3.3e316578664962de
+ 0d58e65467e0d479.72900e2cb26187da.ad19c680c66e754b.0496d78ab02c1510
+ 8345744998928715.ae91453424dc9228.c603d6b3b2bb8c75.1766b8e5d7fc34aa
+ d4ec04f67a45fa58
+ after
+ 0eeca41c73848cde.d0b3abec78ba920a.dd42842b72890b11.6beb66435fc8de67
+ 272e0a5659824159.ffc000005c1a88ec.ffc00000590471c8.55ad954d4fa058dd
+ 0d58e65467e0d479.72900e2cb26187da.ad19c680c66e754b.0496d78ab02c1510
+ 8345744998928715.ae91453424dc9228.c603d6b3b2bb8c75.1766b8e5d7fc34aa
+ d4ec04f67a45fa58
+
+VSQRTPS_256(reg)
+ before
+ 9775b7273393a4c5.18139ab469553e76.03b025689ed6a39f.d0a78025ef548a8e
+ bc4ecee69e736e9d.a88cd482f538b7c8.cc37aa32bcdcf5ed.a7d141c49a462bc2
+ 9fc1449e5870948d.0f7e9f9d5944ac36.6473d1001b79c6bc.274d947bce9c2a3d
+ 9c1b15bbfc165141.29b375f2b087d9ed.29b0953d573950b8.2ce7f536a862442a
+ 926ae0e143a534b5
+ after
+ 9775b7273393a4c5.18139ab469553e76.03b025689ed6a39f.d0a78025ef548a8e
+ ffc000004bf82ba0.277f4f924c606252.51f9d57d2d7cde77.336568b3ffc00000
+ 9fc1449e5870948d.0f7e9f9d5944ac36.6473d1001b79c6bc.274d947bce9c2a3d
+ 9c1b15bbfc165141.29b375f2b087d9ed.29b0953d573950b8.2ce7f536a862442a
+ 926ae0e143a534b5
+VSQRTPS_256(mem)
+ before
+ 34a4d168bc70b80b.0fa83da927f2e265.d2f8d46e160dfc18.753af2550ba9cf8e
+ f05f45b72ecf8a58.54b3b8d4748f83a4.e51837fca8e0cfe4.a65de4b4d35481ea
+ a168b7bab6cf67c7.c78a83a880796faa.40e11a87820e0f7d.166468c64cc6a077
+ 238ba35e6f7b0a85.c4779991e63de424.be1efafdbfa3780e.239d79f7128b69e2
+ 275213b3c03017d6
+ after
+ 34a4d168bc70b80b.0fa83da927f2e265.d2f8d46e160dfc18.753af2550ba9cf8e
+ 3a113f3effc00000.2792bf5c33b05240.ffc000002abea6da.5a5ac3f625936e3b
+ a168b7bab6cf67c7.c78a83a880796faa.40e11a87820e0f7d.166468c64cc6a077
+ 238ba35e6f7b0a85.c4779991e63de424.be1efafdbfa3780e.239d79f7128b69e2
+ 275213b3c03017d6
+
+VSQRTPS_256(reg)
+ before
+ 7fd03267f241e801.5294858d76df30be.a7c7f6fb42661cbe.3b9a52497ba9c5c3
+ 8863d37d4548160c.094eda35e608959d.ccc6965332815323.93229d57d32eb3ca
+ 9c57f06354d3dea5.26871d40db01f54f.8fc076034f19c700.a1825a13e23efe4d
+ 18f78783bc6e7b78.8409c99c72d60cff.4b01917937bab201.43860269c5e36278
+ 54fa1346972b9a78
+ after
+ 7fd03267f241e801.5294858d76df30be.a7c7f6fb42661cbe.3b9a52497ba9c5c3
+ ffc000004a24adf1.33038250ffc00000.ffc0000047466944.ffc00000ffc00000
+ 9c57f06354d3dea5.26871d40db01f54f.8fc076034f19c700.a1825a13e23efe4d
+ 18f78783bc6e7b78.8409c99c72d60cff.4b01917937bab201.43860269c5e36278
+ 54fa1346972b9a78
+VSQRTPS_256(mem)
+ before
+ afa9079475226379.5991934b18a32a31.fea15d34c79495da.5ed4e31f86f051d1
+ 32605c407ad379a6.b96f11260500277b.721b52f4f5464d0b.23866863d748df1d
+ b7ec8e37c34a972c.95defb801e11ae02.ba4326c818f9efc0.f6641cb0c64d9990
+ 1c1717646b937a37.492a4fc5ff61fa74.b4e4549c4db73822.32b8fc72f08cbbd7
+ 35cf0315f090819e
+ after
+ afa9079475226379.5991934b18a32a31.fea15d34c79495da.5ed4e31f86f051d1
+ ffc000005a4be40e.4c88814f2c10844b.ffc00000ffc00000.4f25130cffc00000
+ b7ec8e37c34a972c.95defb801e11ae02.ba4326c818f9efc0.f6641cb0c64d9990
+ 1c1717646b937a37.492a4fc5ff61fa74.b4e4549c4db73822.32b8fc72f08cbbd7
+ 35cf0315f090819e
+
+VSQRTPD_128(reg)
+ before
+ 5af42d0563e52690.3bae75b28ebbdef2.319f0861467c487a.3bcc585caf8ee460
+ fc7576afe418e859.f27c230f49cd7f8a.a98922c08ceed4c3.2ac5aef45b8aafa3
+ 799cdb7d10b400a7.1b4f9d66b8d5182a.0d339a4e6f44d9f9.5e9cd2516cb6551a
+ 2bb757dc8245ad24.94f15fa3f6e066ff.b9ea6a788b0995c8.b41d415dff1e91ef
+ 061476062fce204f
+ after
+ 5af42d0563e52690.3bae75b28ebbdef2.319f0861467c487a.3bcc585caf8ee460
+ 0000000000000000.0000000000000000.2691b5c2a69be3bb.4f45796aaf5c6f3c
+ 799cdb7d10b400a7.1b4f9d66b8d5182a.0d339a4e6f44d9f9.5e9cd2516cb6551a
+ 2bb757dc8245ad24.94f15fa3f6e066ff.b9ea6a788b0995c8.b41d415dff1e91ef
+ 061476062fce204f
+VSQRTPD_128(mem)
+ before
+ 324ded3619d3bd65.7010e639d757297c.3730e6b21ff92534.09fb90a87bc941de
+ 129423dbd838255e.a2f484feaa77b15c.e1d6ac80502d10f6.59b0074cdb111ce4
+ 83b492e0890a1465.1eaf2d9998318170.6fb02ff7a587e471.0556cbce486c6089
+ 617ab831475446a7.418cde753c0fd463.bb8aeb0438135dd0.6938d99c5d674b77
+ e1a42c21b78c165a
+ after
+ 324ded3619d3bd65.7010e639d757297c.3730e6b21ff92534.09fb90a87bc941de
+ 0000000000000000.0000000000000000.3b9071c496db6a35.24f500402ec6043f
+ 83b492e0890a1465.1eaf2d9998318170.6fb02ff7a587e471.0556cbce486c6089
+ 617ab831475446a7.418cde753c0fd463.bb8aeb0438135dd0.6938d99c5d674b77
+ e1a42c21b78c165a
+
+VSQRTPD_128(reg)
+ before
+ c9e4c0c9f16a00df.89b210ba2f227750.65d992fe329fe8e2.a22f5a9428dd3740
+ 7d469100a88a43b2.d52816675c80628b.e8e045a0186df798.006dfa918ff22dec
+ 58149b32777a1c7f.22a84724ea7bc485.24eef3c787033d32.b20e45e9895dfc01
+ b89bdbcbfbc5c7f0.4cfe1ddef61e5869.764f99df1deff75c.92dfb987332b60ab
+ 7dacd257a8671415
+ after
+ c9e4c0c9f16a00df.89b210ba2f227750.65d992fe329fe8e2.a22f5a9428dd3740
+ 0000000000000000.0000000000000000.326f78c60acaa920.fff8000000000000
+ 58149b32777a1c7f.22a84724ea7bc485.24eef3c787033d32.b20e45e9895dfc01
+ b89bdbcbfbc5c7f0.4cfe1ddef61e5869.764f99df1deff75c.92dfb987332b60ab
+ 7dacd257a8671415
+VSQRTPD_128(mem)
+ before
+ 4f410a45051dd66c.f8264c38cff87fb4.2ff5167f9c76dc64.3a4f315475bd62c1
+ e46adf3d655a60db.7403eae3909e8175.a75aadf5f68e0aa2.cd3ab9932cf7b70e
+ 18f2cc2be4296e8f.877cb13ad94309e0.90f95f2a23729f4e.895b2c06de2b35ef
+ c7a74dfb9f96beb4.8fdf9da7477353a0.c69ea60c3d2f5695.cb00871b26e5160f
+ ef73c43ca0b0971a
+ after
+ 4f410a45051dd66c.f8264c38cff87fb4.2ff5167f9c76dc64.3a4f315475bd62c1
+ 0000000000000000.0000000000000000.37f25e5dcc8623c1.3d1f98013eeb276b
+ 18f2cc2be4296e8f.877cb13ad94309e0.90f95f2a23729f4e.895b2c06de2b35ef
+ c7a74dfb9f96beb4.8fdf9da7477353a0.c69ea60c3d2f5695.cb00871b26e5160f
+ ef73c43ca0b0971a
+
+VSQRTPD_128(reg)
+ before
+ 5101e1d7e918f3bd.cd53df9ab2ad0a75.e676ab9875bb9a62.2515008660d0eca2
+ 4df6d9579ca968a4.06c3fcf2387b0eff.ea8ed678ffa61bd2.892ae884a9611da2
+ 3f9ea82856f0307b.4ec322f14d0c887d.f6731ab382c1129b.cea8daf233efa5c1
+ 83444bb6b27888ec.811fcc810e6a321c.657074b59a97ba69.d05d53bc1b853f2a
+ 6b13cdce7c2fa80a
+ after
+ 5101e1d7e918f3bd.cd53df9ab2ad0a75.e676ab9875bb9a62.2515008660d0eca2
+ 0000000000000000.0000000000000000.fff8000000000000.fff8000000000000
+ 3f9ea82856f0307b.4ec322f14d0c887d.f6731ab382c1129b.cea8daf233efa5c1
+ 83444bb6b27888ec.811fcc810e6a321c.657074b59a97ba69.d05d53bc1b853f2a
+ 6b13cdce7c2fa80a
+VSQRTPD_128(mem)
+ before
+ 7b97c61473f99c8c.7536bd6d4dcdaba6.7aa3769097a3c908.94d3deeae2b450ea
+ dbb5b97b1bf1d7dd.71befab9c27cd653.171a9d0903c3096c.e0e656bef6a510c7
+ 693923ed90201429.d329fe07ad1045a0.3351bbd86ed4ad75.a3f7d79d73f536af
+ 00ee7e58ef94109b.f7c3c5c1ab163438.aa154ee9f5e4724e.3b505df3f430fd4c
+ 023ee52d16e3a24b
+ after
+ 7b97c61473f99c8c.7536bd6d4dcdaba6.7aa3769097a3c908.94d3deeae2b450ea
+ 0000000000000000.0000000000000000.5d48f4d4ecabd914.fff8000000000000
+ 693923ed90201429.d329fe07ad1045a0.3351bbd86ed4ad75.a3f7d79d73f536af
+ 00ee7e58ef94109b.f7c3c5c1ab163438.aa154ee9f5e4724e.3b505df3f430fd4c
+ 023ee52d16e3a24b
+
+VSQRTPD_256(reg)
+ before
+ 550c69b574996157.7ca248a65458875f.38d84c555819dec8.5730d228b3ff1424
+ 9108e7f9abde751d.b81ffcc5da7834a3.f4b48d2d4fa581fc.186ec181c52f4f22
+ 107c5a64563f1b48.923216a09d01d491.86a286b72c46567f.c89d98e04683de76
+ 2fb6bf6212478f85.e4a71223bafe2355.4af0335e8c899cfe.4288d43253047e49
+ 64faf06107c0ebca
+ after
+ 550c69b574996157.7ca248a65458875f.38d84c555819dec8.5730d228b3ff1424
+ 28354c8e7cd26e05.fff8000000000000.fff8000000000000.fff8000000000000
+ 107c5a64563f1b48.923216a09d01d491.86a286b72c46567f.c89d98e04683de76
+ 2fb6bf6212478f85.e4a71223bafe2355.4af0335e8c899cfe.4288d43253047e49
+ 64faf06107c0ebca
+VSQRTPD_256(mem)
+ before
+ 08c0685b7fc2e023.4a00105f7a820d80.8c4a6d3a4d7bdd1c.9be88e8d0bf98d24
+ 0ca6b90ad6161a80.bda74bc72b7dd0e4.65e6a2d17185bd12.d7d795b24423669e
+ 4a785e5c28c9550e.e5f76b06c0c3155e.4a492dd442278062.59094338d3926318
+ a002d23c93e64df9.1c3b6c88d6e01899.193d8a2fdd6de239.7cca948c55d2bf3d
+ 9e6584186570b7b9
+ after
+ 08c0685b7fc2e023.4a00105f7a820d80.8c4a6d3a4d7bdd1c.9be88e8d0bf98d24
+ 2456e9f24bc0cfe3.44f6ac2f4471c937.fff8000000000000.fff8000000000000
+ 4a785e5c28c9550e.e5f76b06c0c3155e.4a492dd442278062.59094338d3926318
+ a002d23c93e64df9.1c3b6c88d6e01899.193d8a2fdd6de239.7cca948c55d2bf3d
+ 9e6584186570b7b9
+
+VSQRTPD_256(reg)
+ before
+ 19281049a0f7873a.e8109496307abd6c.bfc14bb908611542.ac8f36cf5d649ec3
+ 4b5d328ca1f36b69.006d1d561d8f6294.2ad30206f2d14705.e00bab9edf17712b
+ 8e51e84b05f09ef5.c2e6ea687533f89c.b9be8fd931bdeb8d.927d678a7e93179d
+ 40502df4677b5d88.0b4778b855723ab1.c8ceeda060af3c87.9cb1e67e57e34c47
+ db73a2658513cb52
+ after
+ 19281049a0f7873a.e8109496307abd6c.bfc14bb908611542.ac8f36cf5d649ec3
+ fff8000000000000.fff8000000000000.fff8000000000000.fff8000000000000
+ 8e51e84b05f09ef5.c2e6ea687533f89c.b9be8fd931bdeb8d.927d678a7e93179d
+ 40502df4677b5d88.0b4778b855723ab1.c8ceeda060af3c87.9cb1e67e57e34c47
+ db73a2658513cb52
+VSQRTPD_256(mem)
+ before
+ 2c8e192d252f51ed.bba6fef26420e4cf.b85c4232d957e5ff.b34f19c51c36789e
+ 69cfc5c152449a42.5d9e55b097696e75.a3f1c4c31ceeb5b1.d58d0db601dbd97f
+ 6f02240d285d617e.8086309c9ce43827.a9d27b553a4366f4.8cd4c7deaa2c9cd6
+ 1af3b2fdc48763cc.81a88a21101d7e90.a6cae1d65063b3f4.336f42a9b3b4fc4e
+ 26ab7a83b9ff3694
+ after
+ 2c8e192d252f51ed.bba6fef26420e4cf.b85c4232d957e5ff.b34f19c51c36789e
+ 363f08dc3a66712e.fff8000000000000.fff8000000000000.fff8000000000000
+ 6f02240d285d617e.8086309c9ce43827.a9d27b553a4366f4.8cd4c7deaa2c9cd6
+ 1af3b2fdc48763cc.81a88a21101d7e90.a6cae1d65063b3f4.336f42a9b3b4fc4e
+ 26ab7a83b9ff3694
+
+VSQRTPD_256(reg)
+ before
+ c1d46bd8579a8653.476ee97e42cd5c59.bd5160ab8f9e7c5d.77a77431795a59dc
+ 603612142a112838.d03f477abd3b0850.8eceaca6b4f56d3a.f633af51d23214d8
+ 5e1d6aa4cdee57ee.923147de51de22de.51686c7f1bae8ed2.003b0f2476f99f15
+ 19d56ff2dcbf5123.691165971bc0672f.626e9ba061531bd2.718b0e9582bab8bf
+ 25ee2a9011821902
+ after
+ c1d46bd8579a8653.476ee97e42cd5c59.bd5160ab8f9e7c5d.77a77431795a59dc
+ 4f05b1dfc131d1ff.fff8000000000000.48abf4d8b28e4f85.2014ceaf6a98a278
+ 5e1d6aa4cdee57ee.923147de51de22de.51686c7f1bae8ed2.003b0f2476f99f15
+ 19d56ff2dcbf5123.691165971bc0672f.626e9ba061531bd2.718b0e9582bab8bf
+ 25ee2a9011821902
+VSQRTPD_256(mem)
+ before
+ f832de023f5c7e09.eca91d6bf50f4f80.31ab1d8f36f0936e.1d2b357722724fe5
+ c621a6d52a54a500.32e7717cb16b90b4.c6cbecb4bf7762c8.dfea366ef99768b8
+ 6b89fef6eb774814.49d96590ae5e4e68.043d4cf1d2638f68.02f89bf3824ca0f7
+ c3346352a0d02371.8bccf7138874c64b.c7cdbb3289c0d77b.e3a15f715a20334d
+ de317e531c9c5f67
+ after
+ f832de023f5c7e09.eca91d6bf50f4f80.31ab1d8f36f0936e.1d2b357722724fe5
+ fff8000000000000.fff8000000000000.38cd74e7caf84d27.2e8d81e1190dbe2e
+ 6b89fef6eb774814.49d96590ae5e4e68.043d4cf1d2638f68.02f89bf3824ca0f7
+ c3346352a0d02371.8bccf7138874c64b.c7cdbb3289c0d77b.e3a15f715a20334d
+ de317e531c9c5f67
+
+VRSQRTSS_128(reg)
+ before
+ 4ff4f407654e5ef0.aaef50d3656bf443.560c2270da393407.eb47b5630398f52d
+ 9236bef8d0c16c95.fc854167555575b4.04e4e315403ad349.4c76b47059f9a7a9
+ 0342d692fa81c702.94c4b2f88c9963f3.f3a2346e5703e0bc.c5273645aaeea71b
+ fe653a427e1ba9e2.5077207427437a2a.7d9013e5bb1e970d.3426b6ce0f84b2b1
+ 743fb0f8a6c68395
+ after
+ 0000000000000000.0000000000000000.04e4e315403ad349.4c76b470ffc00000
+ 9236bef8d0c16c95.fc854167555575b4.04e4e315403ad349.4c76b47059f9a7a9
+ 0342d692fa81c702.94c4b2f88c9963f3.f3a2346e5703e0bc.c5273645aaeea71b
+ fe653a427e1ba9e2.5077207427437a2a.7d9013e5bb1e970d.3426b6ce0f84b2b1
+ 743fb0f8a6c68395
+VRSQRTSS_128(mem)
+ before
+ 613ea0ad8bc0d7f3.dfece572f81a4fe2.0b6905c641607586.00fb7be7061934e7
+ d6ee03dbd97f6af8.0121d48f050bf5ad.a167dfdaf7fb1132.d62f68e0d780f2f7
+ b11d536cad0ef8d0.c25001064179d6f0.ed3d299c64200a5b.5c78d73dc8dd0ee9
+ cd950e4e227a3da6.7dc76a4147f02f57.cdb760f8a5dc1c2d.ef22c26875bec468
+ e97927cf7baf4f21
+ after
+ 613ea0ad8bc0d7f3.dfece572f81a4fe2.0b6905c641607586.00fb7be7061934e7
+ d6ee03dbd97f6af8.0121d48f050bf5ad.a167dfdaf7fb1132.d62f68e0d780f2f7
+ 0000000000000000.0000000000000000.a167dfdaf7fb1132.d62f68e05c257800
+ cd950e4e227a3da6.7dc76a4147f02f57.cdb760f8a5dc1c2d.ef22c26875bec468
+ e97927cf7baf4f21
+
+VRSQRTSS_128(reg)
+ before
+ a7c801dd753aedc0.0523af6c54cdf4a7.8ed10aaeb3fc3c8d.1ca1fedbd53a02d3
+ 855d4dfd00edd8f0.3793b3b26015d9ff.51b9ddb8222a393f.b5c6812f1146797a
+ e082059db7544c5d.3eb1940c615eaad9.21cce0cb30056118.76f364e2740d3d4d
+ 1284272836f986b5.f549d06674b32162.5c560d53781af1c5.39f523de1b9a0979
+ dc963b1121f99a29
+ after
+ 0000000000000000.0000000000000000.51b9ddb8222a393f.b5c6812f252c5800
+ 855d4dfd00edd8f0.3793b3b26015d9ff.51b9ddb8222a393f.b5c6812f1146797a
+ e082059db7544c5d.3eb1940c615eaad9.21cce0cb30056118.76f364e2740d3d4d
+ 1284272836f986b5.f549d06674b32162.5c560d53781af1c5.39f523de1b9a0979
+ dc963b1121f99a29
+VRSQRTSS_128(mem)
+ before
+ 39a32666a337ac8a.78aeae0b1a6ac3a1.3a26e2acb520fbc5.5da362bc96f425f1
+ 2ee762c8bc5ffbc8.6e4e96b0ff333cd0.e71547ca3eb1f42f.7fffda72271f384a
+ 95306a25887e420e.50afdc8480df30ec.dae279ad2e73c7cb.20b672e1c6286779
+ 4c48bb68249e3e89.7a1c7af339fad9a1.ed5af63f9f7132c6.9a1324761099ee2d
+ 4b63ee9ba001090f
+ after
+ 39a32666a337ac8a.78aeae0b1a6ac3a1.3a26e2acb520fbc5.5da362bc96f425f1
+ 2ee762c8bc5ffbc8.6e4e96b0ff333cd0.e71547ca3eb1f42f.7fffda72271f384a
+ 0000000000000000.0000000000000000.e71547ca3eb1f42f.7fffda72ffc00000
+ 4c48bb68249e3e89.7a1c7af339fad9a1.ed5af63f9f7132c6.9a1324761099ee2d
+ 4b63ee9ba001090f
+
+VRSQRTSS_128(reg)
+ before
+ 8df2cbbe13e9f3ce.2dfdcf7eacceab65.48e26e6ac710749c.fd46396eadb7ef4c
+ be0cb74904dfe914.151924513b1744cd.164db353c6ae3d89.e775be257452ba88
+ 38fdaeaa106f278e.e16935ceed87c6ed.40a9461cd15f6f14.85b2014f124d50a7
+ 5811ad4cd223e8e7.6bb97ee1df29edf3.2242213084af47e8.b4c87fdaa0b56dd5
+ 5184b3b13c95cd3d
+ after
+ 0000000000000000.0000000000000000.164db353c6ae3d89.e775be25560ef000
+ be0cb74904dfe914.151924513b1744cd.164db353c6ae3d89.e775be257452ba88
+ 38fdaeaa106f278e.e16935ceed87c6ed.40a9461cd15f6f14.85b2014f124d50a7
+ 5811ad4cd223e8e7.6bb97ee1df29edf3.2242213084af47e8.b4c87fdaa0b56dd5
+ 5184b3b13c95cd3d
+VRSQRTSS_128(mem)
+ before
+ 36b219c002f92c0b.7b93af9be68969cc.90d47c772c0a7508.186342fb7c2b01b1
+ 401e2df30dee456c.fbd1b003e92ce6e8.2c88a97bf134195b.7d5aa4e9545ed81c
+ 4b946b37797ed58c.3515acf077999be8.1c9f83d849b69616.af714366a9d50ad5
+ 33e0507663b89797.86aca0ce2b5bc378.3ae6857c5199a865.09f51bde161bd187
+ e73229bd38bc69df
+ after
+ 36b219c002f92c0b.7b93af9be68969cc.90d47c772c0a7508.186342fb7c2b01b1
+ 401e2df30dee456c.fbd1b003e92ce6e8.2c88a97bf134195b.7d5aa4e9545ed81c
+ 0000000000000000.0000000000000000.2c88a97bf134195b.7d5aa4e9211c9800
+ 33e0507663b89797.86aca0ce2b5bc378.3ae6857c5199a865.09f51bde161bd187
+ e73229bd38bc69df
+
+VRSQRTPS_128(reg)
+ before
+ a574686faa441089.d4cd579de7a549b8.48e28709a1ff9b43.63292c5224eb0a76
+ 9e07d46109400030.0a28fc992053a51b.d8025c0d760f5ff6.7334f246dfb77a72
+ 303669fdf03c7681.b1bebb552acd68ee.925a1e4746194a3c.46d355449d0ab288
+ b54e24b1fcc2ad27.a55911bc22204d5a.d234c621aca999c2.b8d2d0387bef6ee2
+ a5fcdf0e94726cac
+ after
+ a574686faa441089.d4cd579de7a549b8.48e28709a1ff9b43.63292c5224eb0a76
+ 0000000000000000.0000000000000000.ffc000003c256800.3bc74000ffc00000
+ 303669fdf03c7681.b1bebb552acd68ee.925a1e4746194a3c.46d355449d0ab288
+ b54e24b1fcc2ad27.a55911bc22204d5a.d234c621aca999c2.b8d2d0387bef6ee2
+ a5fcdf0e94726cac
+VRSQRTPS_128(mem)
+ before
+ e91efeb304a06614.8b9bffe8c860e2cf.c2c579bc2357118e.f5de520944498834
+ 6004aa11e8841843.0d69f80df0a15124.e4d06f404a7e70b4.55a2bc6aab87533d
+ e67a5e165c2a4068.96040a8e111236d4.e7456f34b2a226f8.4fcd02b07cef358a
+ 574c96ac7b9f98ad.84b832d6c73ecd88.a7eff58478ceee87.3faa2047540c6bc6
+ 8187109bce6a319e
+ after
+ e91efeb304a06614.8b9bffe8c860e2cf.c2c579bc2357118e.f5de520944498834
+ 0000000000000000.0000000000000000.ffc000004d8ba800.ffc000003d104000
+ e67a5e165c2a4068.96040a8e111236d4.e7456f34b2a226f8.4fcd02b07cef358a
+ 574c96ac7b9f98ad.84b832d6c73ecd88.a7eff58478ceee87.3faa2047540c6bc6
+ 8187109bce6a319e
+
+VRSQRTPS_128(reg)
+ before
+ 71aed0188695c3be.8e46cec161eedd3e.31d16a51adb151ef.009b7e1cb70e858d
+ 6a6d5b2a1a1a5cd1.693382402b23cb48.fb9ab06c5ff8ffb2.ce1585e88c6fa735
+ ca0ead3d23843984.c3e02f15f44b1df7.3c60ff917a9e1280.ed2986d512fc10ac
+ ecdec2be3f609682.781a502cd9719076.516f532d992fc703.38a3fdcd66c17b1e
+ 8d4e67bea3cba5b6
+ after
+ 71aed0188695c3be.8e46cec161eedd3e.31d16a51adb151ef.009b7e1cb70e858d
+ 0000000000000000.0000000000000000.4108900021e66000.ffc0000055b67000
+ ca0ead3d23843984.c3e02f15f44b1df7.3c60ff917a9e1280.ed2986d512fc10ac
+ ecdec2be3f609682.781a502cd9719076.516f532d992fc703.38a3fdcd66c17b1e
+ 8d4e67bea3cba5b6
+VRSQRTPS_128(mem)
+ before
+ c7f83f92e5254aa1.2c2997170a38ae78.63ab6171f6a1e0f2.9713a9ad59385ae8
+ c16b013749db250a.e63a27b61f9bbe12.625fdfd065e8c997.6898fc7b554407da
+ 59742998ebfaf31e.765f6e051a1202fb.5004443545510690.214a47052adf0a86
+ 6adf33a1e68d7009.37e26872982bb5e0.08650e8dafe8540a.1e7489b573969e97
+ bc63bbf9cdf400ba
+ after
+ c7f83f92e5254aa1.2c2997170a38ae78.63ab6171f6a1e0f2.9713a9ad59385ae8
+ 0000000000000000.0000000000000000.2d5d3800ffc00000.ffc000003296d800
+ 59742998ebfaf31e.765f6e051a1202fb.5004443545510690.214a47052adf0a86
+ 6adf33a1e68d7009.37e26872982bb5e0.08650e8dafe8540a.1e7489b573969e97
+ bc63bbf9cdf400ba
+
+VRSQRTPS_128(reg)
+ before
+ 5563da3cd3856b9b.cf789c3e56a058f6.871011683571156c.684db8c2c1ba6f30
+ 46c0e3ea22d61de5.660bdf5b58406611.c13666538c715c4c.4b89bec297d2122f
+ ebc6d16f55725045.096378e407785788.409d629f39b6c62b.8ce59d774c3cfa32
+ a0c1a03808e54166.964de3c68055e785.629401b8d9cc91b7.092dcfcffd05e367
+ 9c2dd2b5c53889f7
+ after
+ 5563da3cd3856b9b.cf789c3e56a058f6.871011683571156c.684db8c2c1ba6f30
+ 0000000000000000.0000000000000000.3ee6d80042563800.ffc0000039150000
+ ebc6d16f55725045.096378e407785788.409d629f39b6c62b.8ce59d774c3cfa32
+ a0c1a03808e54166.964de3c68055e785.629401b8d9cc91b7.092dcfcffd05e367
+ 9c2dd2b5c53889f7
+VRSQRTPS_128(mem)
+ before
+ 22b12115c0e2a710.c1fc4dafd8bc2bf5.e7969cebdee2d134.81663f0b073ff799
+ 788439db0b0efade.aac5d24161824b9e.da0820403e2bd2c2.fb5e1902609c3580
+ 787394f3c2c83e8d.b7662d5b3ec3dd0c.496feab2bb3ca65b.2bc98a0a7f6f8615
+ 004ab049001c2e48.442c59670b0c1dec.1199762c7222092a.6cf48e9001422807
+ 1b2921fe81a35500
+ after
+ 22b12115c0e2a710.c1fc4dafd8bc2bf5.e7969cebdee2d134.81663f0b073ff799
+ 0000000000000000.0000000000000000.ffc00000ffc00000.ffc000005b93d000
+ 787394f3c2c83e8d.b7662d5b3ec3dd0c.496feab2bb3ca65b.2bc98a0a7f6f8615
+ 004ab049001c2e48.442c59670b0c1dec.1199762c7222092a.6cf48e9001422807
+ 1b2921fe81a35500
+
+VRSQRTPS_256(reg)
+ before
+ 95b43fc29c1d49ad.ead508cae117873b.ad6353d365e846e9.0f5141997ee8b65c
+ 34e3e547ed3d42b9.13e0186082c40594.4e57150ae8e495b0.1d62c5e7fc9b6a1c
+ 56010ef9108e7ad1.57375df9fe30647d.83539d782e8b46ed.189980010745e197
+ 5559b644a29c2ea0.93a5517f72665f22.a8a5e689d669954b.dcc2edd3bcf5d6f9
+ 45a9884936b4066d
+ after
+ 95b43fc29c1d49ad.ead508cae117873b.ad6353d365e846e9.0f5141997ee8b65c
+ 3434480056f2b000.33974000ffc00000.ffc0000047f56000.52e9b8005b919000
+ 56010ef9108e7ad1.57375df9fe30647d.83539d782e8b46ed.189980010745e197
+ 5559b644a29c2ea0.93a5517f72665f22.a8a5e689d669954b.dcc2edd3bcf5d6f9
+ 45a9884936b4066d
+VRSQRTPS_256(mem)
+ before
+ 301ace5091902d20.8e38d9943ff499d3.a1f872e0f972b3b0.1997eca97a0abd77
+ 77e139d2ea94073d.5dea73558221f916.5efa3b07b0601c53.3176ac44b6fbfb1c
+ f7c947bc5dcd4ff1.1fbb81f307af8814.a67828dfb23d5536.4e8e20c626c78ae7
+ 8c9f73fb0446c268.2ef7fedb6b2b827a.553eb6561c151c86.cb2b469b68fba883
+ 0498193015228f9d
+ after
+ 301ace5091902d20.8e38d9943ff499d3.a1f872e0f972b3b0.1997eca97a0abd77
+ 47249800ffc00000.ffc000003f393800.ffc00000ffc00000.526af800222de800
+ f7c947bc5dcd4ff1.1fbb81f307af8814.a67828dfb23d5536.4e8e20c626c78ae7
+ 8c9f73fb0446c268.2ef7fedb6b2b827a.553eb6561c151c86.cb2b469b68fba883
+ 0498193015228f9d
+
+VRSQRTPS_256(reg)
+ before
+ 542395efcbc87ce1.12303a7afe0b1ccd.e7e9e6774a2025f3.4717605809f22b6e
+ 1916b7462679aafb.654616246529194d.a6df36353e1bab2c.58d1a2cf96e23e1b
+ adbe799fc1c25795.61ad85e755ab7413.c723e87fe6a651d1.6436f8a8def013b9
+ 6e67d968392fbd5e.e23302aeeb9dea4c.a602fac3dc4f538d.4714decffd296473
+ dd35d1311098ed76
+ after
+ 542395efcbc87ce1.12303a7afe0b1ccd.e7e9e6774a2025f3.4717605809f22b6e
+ ffc00000ffc00000.2e5bd800345d3800.ffc00000ffc00000.2d176800ffc00000
+ adbe799fc1c25795.61ad85e755ab7413.c723e87fe6a651d1.6436f8a8def013b9
+ 6e67d968392fbd5e.e23302aeeb9dea4c.a602fac3dc4f538d.4714decffd296473
+ dd35d1311098ed76
+VRSQRTPS_256(mem)
+ before
+ 02664cb833496ced.b65dd30c294a1800.c4a30965420b3624.9fc8676cbca2ec0d
+ 9273cb5281499b05.e3ec61f72da1a628.e3c817f8770216c6.0ec12be6232a59fc
+ 6927caea16a337e9.4f5f8195e2bfa181.1b6fa653a58e445f.4f38439dac73d607
+ 6250c56b0f63fcc7.58042d52e33146b8.47643463e9b97d1a.be7baafdf3099eda
+ b7d45b729679ef20
+ after
+ 02664cb833496ced.b65dd30c294a1800.c4a30965420b3624.9fc8676cbca2ec0d
+ 5e06f00045905000.ffc000004a901000.ffc000003e2d9800.ffc00000ffc00000
+ 6927caea16a337e9.4f5f8195e2bfa181.1b6fa653a58e445f.4f38439dac73d607
+ 6250c56b0f63fcc7.58042d52e33146b8.47643463e9b97d1a.be7baafdf3099eda
+ b7d45b729679ef20
+
+VRSQRTPS_256(reg)
+ before
+ 969055692e4e0386.5bb839c38896a5c8.5825639bcd82d078.45733c125e917c24
+ b7fb914c591416b7.2f2ca1dd9b47ef1b.ad0f1fda3c3e7d6e.f0683b4d2022fea9
+ 76610c89b3586660.ba7879a5678296ea.b10e5b7ccaf28746.240eab014c76bfd4
+ 2f0ec38ad7a52d2d.d7683d0806545661.c16e15ee16292aab.bc330a19fe9c7bd2
+ 96a1d380519deece
+ after
+ 969055692e4e0386.5bb839c38896a5c8.5825639bcd82d078.45733c125e917c24
+ 24088000ffc00000.ffc000002b7d7800.ffc00000ffc00000.4d2b700039026800
+ 76610c89b3586660.ba7879a5678296ea.b10e5b7ccaf28746.240eab014c76bfd4
+ 2f0ec38ad7a52d2d.d7683d0806545661.c16e15ee16292aab.bc330a19fe9c7bd2
+ 96a1d380519deece
+VRSQRTPS_256(mem)
+ before
+ 8d2582246187d3f5.3d4db1bd6188a8c9.64c86af094c8eaad.3a7a489bb96fa44a
+ 7c8b94f04b65e672.fe6cd28dee8c12e1.3b637b4a2dea0ffa.7680f0ee52512fcf
+ 419f83d02b43e572.cdb523651a3da820.3a07ec03efc78173.d2ca09557a5a08e5
+ b62dcdb01c2e8a21.05759fb38028a633.3c7e3905f36afb45.aaa5903bd0166b38
+ 5a5d7f0ced129375
+ after
+ 8d2582246187d3f5.3d4db1bd6188a8c9.64c86af094c8eaad.3a7a489bb96fa44a
+ ffc000002e788800.408ed0002e77b800.2ccc9000ffc00000.42017000ffc00000
+ 419f83d02b43e572.cdb523651a3da820.3a07ec03efc78173.d2ca09557a5a08e5
+ b62dcdb01c2e8a21.05759fb38028a633.3c7e3905f36afb45.aaa5903bd0166b38
+ 5a5d7f0ced129375
+
+VMOVDQU_GtoE_256(reg)
+ before
+ 3e3ed4346fd9bd48.b900ed7c3a3192aa.04f841e3bcd748c5.1c95df3e57e03a9c
+ b3948b1ff2f8255d.24e55f21a258b93a.2589085f6bd9c983.b81858993733faa3
+ 13aa9e3a11f9065f.d5a9a0896fb0bafd.c376ed9428b76719.ead22202ae71f786
+ bbce0bef686a9dfa.a6162ba2be44531e.3c09edee90ff5b32.8f91b865d9a6ec73
+ 842096aed3dd9694
+ after
+ 3e3ed4346fd9bd48.b900ed7c3a3192aa.04f841e3bcd748c5.1c95df3e57e03a9c
+ b3948b1ff2f8255d.24e55f21a258b93a.2589085f6bd9c983.b81858993733faa3
+ bbce0bef686a9dfa.a6162ba2be44531e.3c09edee90ff5b32.8f91b865d9a6ec73
+ bbce0bef686a9dfa.a6162ba2be44531e.3c09edee90ff5b32.8f91b865d9a6ec73
+ 842096aed3dd9694
+VMOVDQU_GtoE_256(mem)
+ before
+ a34a39c9b822b115.074accac94d726db.74f87b56aa213ec9.ea9005da3e3ce47b
+ cadc1ca2a581f823.536be0db31cbddae.1c1d0f935052372c.2b5530c2cffb3ca0
+ d3a2bb25b50728ea.fa7d40eadad2fd1f.78506044cbe3fb71.59a56a14dec7a04c
+ 9b68923f05bffd95.5acbe9442b78c4d9.655cec5438e046c4.d2ccb03b082c4c2c
+ f015fca2e8b77beb
+ after
+ d3a2bb25b50728ea.fa7d40eadad2fd1f.78506044cbe3fb71.59a56a14dec7a04c
+ cadc1ca2a581f823.536be0db31cbddae.1c1d0f935052372c.2b5530c2cffb3ca0
+ d3a2bb25b50728ea.fa7d40eadad2fd1f.78506044cbe3fb71.59a56a14dec7a04c
+ 9b68923f05bffd95.5acbe9442b78c4d9.655cec5438e046c4.d2ccb03b082c4c2c
+ f015fca2e8b77beb
+
+VMOVDQU_GtoE_256(reg)
+ before
+ 10ce4cb71af36b36.fef91ddab1b63351.cea3d854c14a6b88.c00e2db1b256d452
+ 8f419be53b6c56b8.d923d9e4d3f78549.b24f088837d331d9.6332a14655506147
+ c7bbe698e7af781e.06b041478a8eb0aa.621d754b2aa05078.2b94c4003edba8ce
+ 1588273db9470e14.626dd1f1ef8870a0.3a571c0a353c0510.f40010c989026614
+ 9a42038e51d15644
+ after
+ 10ce4cb71af36b36.fef91ddab1b63351.cea3d854c14a6b88.c00e2db1b256d452
+ 8f419be53b6c56b8.d923d9e4d3f78549.b24f088837d331d9.6332a14655506147
+ 1588273db9470e14.626dd1f1ef8870a0.3a571c0a353c0510.f40010c989026614
+ 1588273db9470e14.626dd1f1ef8870a0.3a571c0a353c0510.f40010c989026614
+ 9a42038e51d15644
+VMOVDQU_GtoE_256(mem)
+ before
+ f925183cb255368b.d6f45c3e4dc05445.c92605cd21ef8056.954af72ff5338c4e
+ ed76cbbdc998c015.644b800840a7865e.17a75ac739d29ef9.d1410427051120de
+ 530298ffb2a9b10d.1cd88f082e87e00a.28bc4bcb553a84b4.498a3e5e0263fe6b
+ 0593fcec8791c4a0.5ae985a8b1ec9df6.d83153c59135eeb4.5870a14187b462a2
+ 5c3e2a3b3091882e
+ after
+ 530298ffb2a9b10d.1cd88f082e87e00a.28bc4bcb553a84b4.498a3e5e0263fe6b
+ ed76cbbdc998c015.644b800840a7865e.17a75ac739d29ef9.d1410427051120de
+ 530298ffb2a9b10d.1cd88f082e87e00a.28bc4bcb553a84b4.498a3e5e0263fe6b
+ 0593fcec8791c4a0.5ae985a8b1ec9df6.d83153c59135eeb4.5870a14187b462a2
+ 5c3e2a3b3091882e
+
+VMOVDQU_GtoE_256(reg)
+ before
+ b041d4b79b85abbc.dff57272675eb6f9.7ac85f566863face.03d1f1a208ce9a25
+ afc59b23611c08f7.bff6767c6b1c4345.d8c2187dec77323d.85699e4cd7124232
+ b7167bea20e3db8c.806184f6b2d527b0.d023ac88dcb583f0.3ac5d8b0190ca208
+ 2280707874655f27.fe0118cc55971d65.be3717e5d1a72792.feb119bbeac878d2
+ adf9df5767537ebd
+ after
+ b041d4b79b85abbc.dff57272675eb6f9.7ac85f566863face.03d1f1a208ce9a25
+ afc59b23611c08f7.bff6767c6b1c4345.d8c2187dec77323d.85699e4cd7124232
+ 2280707874655f27.fe0118cc55971d65.be3717e5d1a72792.feb119bbeac878d2
+ 2280707874655f27.fe0118cc55971d65.be3717e5d1a72792.feb119bbeac878d2
+ adf9df5767537ebd
+VMOVDQU_GtoE_256(mem)
+ before
+ 2369a672acb871f5.4e4e7739f72ed173.15a3afea736de291.fe4a55ff6adc5bd0
+ 3bcce8f7d3030da5.95ce8a9948ca6d1d.a113c43d2564325f.eca7634240dd5a56
+ d3ef23d2fb410dfa.554aa70401c66fd1.7e1dd3af8987c9fc.e49b3c1bf13861cf
+ c69fd2ef3e7d2e1f.e80fcae7beae123a.878d582dbbe26293.4272dcf41978ace8
+ 6278403a5329774c
+ after
+ d3ef23d2fb410dfa.554aa70401c66fd1.7e1dd3af8987c9fc.e49b3c1bf13861cf
+ 3bcce8f7d3030da5.95ce8a9948ca6d1d.a113c43d2564325f.eca7634240dd5a56
+ d3ef23d2fb410dfa.554aa70401c66fd1.7e1dd3af8987c9fc.e49b3c1bf13861cf
+ c69fd2ef3e7d2e1f.e80fcae7beae123a.878d582dbbe26293.4272dcf41978ace8
+ 6278403a5329774c
+
+VCVTPS2PD_256(reg)
+ before
+ a0f9625a3cd8fda8.f0a6713ab8c32c41.ab69edac1c0c9304.9a2ed0a4d682ba52
+ 574140be6f107ba8.2cd07c9f8620c38b.fba30ec1b66e2edd.92ceb5fff7728d62
+ e59bd5d4885e2df7.58eb700ac39fae2a.320b289029601e6f.4a37852939bf96f2
+ a5551d07244d4f42.4fc2c8688c4daa4a.adec3787106ca066.a036bc10b873922b
+ 6f97d49f919c3d3c
+ after
+ a0f9625a3cd8fda8.f0a6713ab8c32c41.ab69edac1c0c9304.9a2ed0a4d682ba52
+ 574140be6f107ba8.2cd07c9f8620c38b.fba30ec1b66e2edd.92ceb5fff7728d62
+ bdbd86f0e0000000.3a0d940cc0000000.bc06d78200000000.bf0e724560000000
+ a5551d07244d4f42.4fc2c8688c4daa4a.adec3787106ca066.a036bc10b873922b
+ 6f97d49f919c3d3c
+VCVTPS2PD_256(mem)
+ before
+ 92264bc2df46534f.f3b915c3df691c34.ec2000a3fc347316.c89137110820f06f
+ e7af9b65bf7c8f91.2a14b774533fd17a.0dd294a92f62c4bb.df47259aac084a36
+ 48fd42744d4aae2d.a8b201861f59aabf.8ca4006543e35a65.4f5afb8e99afe966
+ 93ddbcdca4bc6c50.c8dfee65dd46e2b0.4762c1c251c2f13f.7216b7596aa10aac
+ a5c65567bb6ae9b3
+ after
+ 92264bc2df46534f.f3b915c3df691c34.ec2000a3fc347316.c89137110820f06f
+ e7af9b65bf7c8f91.2a14b774533fd17a.0dd294a92f62c4bb.df47259aac084a36
+ c584001460000000.c7868e62c0000000.c11226e220000000.39041e0de0000000
+ 93ddbcdca4bc6c50.c8dfee65dd46e2b0.4762c1c251c2f13f.7216b7596aa10aac
+ a5c65567bb6ae9b3
+
+VCVTPS2PD_256(reg)
+ before
+ 44b8cf252997c228.a21c8387e0df8425.e5e67a7d298fb6f9.18d852ae770b4576
+ ab3623fd50b3d0b7.538415631ebeb3d9.5d15a23ba0c26245.ddd22f14d1ca1135
+ 368d4c5ccb4a500b.80e1ed5a7965b598.8ab66109dd6a2241.701bd4e07a0c12a9
+ 410a46af36e97dd1.0601875a0de1468d.ca16b3557d143199.ae80befe8edc04fd
+ 74cd685a2a47a25e
+ after
+ 44b8cf252997c228.a21c8387e0df8425.e5e67a7d298fb6f9.18d852ae770b4576
+ ab3623fd50b3d0b7.538415631ebeb3d9.5d15a23ba0c26245.ddd22f14d1ca1135
+ c142d66aa0000000.47a2863320000000.bdd017dfc0000000.b9db809fa0000000
+ 410a46af36e97dd1.0601875a0de1468d.ca16b3557d143199.ae80befe8edc04fd
+ 74cd685a2a47a25e
+VCVTPS2PD_256(mem)
+ before
+ 9cce4ee16a57a9f8.28f60d612e1b95b4.c2af5f4ef83d21e5.778194891b4bccf8
+ 034fec7d681bd5f6.47a09ddd4e6dd261.8eb6f221538603cc.ee430013539b2f0b
+ 851cbe1c439ce285.fa53f39133697184.47e3bbc13cc7a86d.8ca8f45ec391957d
+ ff0041a815e88bd0.9c5a0ae8799eadc8.c9023619cf0ccbf4.abfb6bd604b83bfb
+ a98961e7b49c5d30
+ after
+ 9cce4ee16a57a9f8.28f60d612e1b95b4.c2af5f4ef83d21e5.778194891b4bccf8
+ 034fec7d681bd5f6.47a09ddd4e6dd261.8eb6f221538603cc.ee430013539b2f0b
+ c055ebe9c0000000.c707a43ca0000000.46f0329120000000.3b69799f00000000
+ ff0041a815e88bd0.9c5a0ae8799eadc8.c9023619cf0ccbf4.abfb6bd604b83bfb
+ a98961e7b49c5d30
+
+VCVTPS2PD_256(reg)
+ before
+ e09fd2fd6fca37c9.4bc9f00ffa0a8d04.8b02de4eba95c3d9.f1dfdf162761298f
+ ad87bb84d0cd0472.4641473c0f0fa44d.22976c2f95dcef65.994633a260d37e67
+ 6c8d16e8733101d6.cc35c21b6f028bd6.bd65aef8a3fe6d16.9e03acaa976e86ab
+ 7affe195f5836aa2.b971de9836ef00cc.b7b8a21383887898.dce1c81be83cfc85
+ 2fad02df6e4b9d21
+ after
+ e09fd2fd6fca37c9.4bc9f00ffa0a8d04.8b02de4eba95c3d9.f1dfdf162761298f
+ ad87bb84d0cd0472.4641473c0f0fa44d.22976c2f95dcef65.994633a260d37e67
+ bef7144260000000.b8710f1300000000.c39c390360000000.c5079f90a0000000
+ 7affe195f5836aa2.b971de9836ef00cc.b7b8a21383887898.dce1c81be83cfc85
+ 2fad02df6e4b9d21
+VCVTPS2PD_256(mem)
+ before
+ 7334d7e445a625ad.312817f8f14e7a81.e9c1159f82e2bd5a.6edc43edce054d98
+ 8440c1148a5a5052.ee53b57c041e6f20.38f0e51c6ce87ead.3d1c8ef3220128c2
+ 3e9d3e5d5872d93f.0dcdb58cca80832b.82ccc9fb120d01f1.7fc67d8f1b0845c1
+ 7d19c9aaccfa7d9e.eae21596ddfff24d.a31f3e28905b0051.92240e2f54a7df42
+ d1833c3e696933f1
+ after
+ 7334d7e445a625ad.312817f8f14e7a81.e9c1159f82e2bd5a.6edc43edce054d98
+ 8440c1148a5a5052.ee53b57c041e6f20.38f0e51c6ce87ead.3d1c8ef3220128c2
+ c53822b3e0000000.b85c57ab40000000.45db887da0000000.c1c0a9b300000000
+ 7d19c9aaccfa7d9e.eae21596ddfff24d.a31f3e28905b0051.92240e2f54a7df42
+ d1833c3e696933f1
+
+VCVTTPS2DQ_128(reg)
+ before
+ 972f0328f7db7d79.1d7fdee701fff79b.e1ded005dc28fa33.77b6be9001e037fa
+ 42735f599a88f887.fa9afa00148c0564.4e0de3456085d588.da5dc71d81a76417
+ 2c9d4d3dedfce1c6.f03797e120ad6122.8dbb48c208a4bff9.a8e0d4bd2dbd41d5
+ b2f7c8408cc474e3.da223377426fc804.fa33fde86d11f632.bd0a625b212d8b60
+ f4a9ebe37803fee3
+ after
+ 972f0328f7db7d79.1d7fdee701fff79b.e1ded005dc28fa33.77b6be9001e037fa
+ 42735f599a88f887.fa9afa00148c0564.4e0de3456085d588.da5dc71d81a76417
+ 0000000000000000.0000000000000000.8000000080000000.0000000000000000
+ b2f7c8408cc474e3.da223377426fc804.fa33fde86d11f632.bd0a625b212d8b60
+ f4a9ebe37803fee3
+VCVTTPS2DQ_128(mem)
+ before
+ 2b87ed414e4c558b.31cfccce146bed89.962749ac95ddf534.f1c3fd232d57b4de
+ 3d71e361c0134d83.036f5554217d8765.ff12556d3603a5de.ceb544dfe40236aa
+ 0633492fe965a2f8.86245f3c4d877f23.f1aed4a740ee942f.ed56ce892d9eb841
+ 61999b97e64c1016.1439e7f43714116e.47c94145cfa97e53.a9f2988ba5b87550
+ 60d49c53e7dbaa83
+ after
+ 2b87ed414e4c558b.31cfccce146bed89.962749ac95ddf534.f1c3fd232d57b4de
+ 3d71e361c0134d83.036f5554217d8765.ff12556d3603a5de.ceb544dfe40236aa
+ 0000000000000000.0000000000000000.0000000000000000.8000000000000000
+ 61999b97e64c1016.1439e7f43714116e.47c94145cfa97e53.a9f2988ba5b87550
+ 60d49c53e7dbaa83
+
+VCVTTPS2DQ_128(reg)
+ before
+ 6d4ad84c8f949385.2c6f5685d2d65208.0afce8e678b078f3.df2d183200401e75
+ 2c9e48e13a6e6c03.4280f5e5ca0f25fa.c4b75e80afe8f25d.94a7d55cefc032c2
+ f81de68084f570a8.7e9af4a4e901451a.9fb8452d7547b85a.4103f4aeb7347366
+ 2f13b09407b5dc21.be87cfac4cba6d92.f5499a5968590993.c40df21474a8a08c
+ f7914a7a43297360
+ after
+ 6d4ad84c8f949385.2c6f5685d2d65208.0afce8e678b078f3.df2d183200401e75
+ 2c9e48e13a6e6c03.4280f5e5ca0f25fa.c4b75e80afe8f25d.94a7d55cefc032c2
+ 0000000000000000.0000000000000000.8000000080000000.fffffdc980000000
+ 2f13b09407b5dc21.be87cfac4cba6d92.f5499a5968590993.c40df21474a8a08c
+ f7914a7a43297360
+VCVTTPS2DQ_128(mem)
+ before
+ b85a78cd3fc2a910.2ccca189623bec19.dc1402eb0e465a8e.23b7587024ab1fb6
+ e135f8f78580fec6.4a94b5cb2f13db3d.b60d0a4c4bb0c83b.854e7bde44c8386f
+ 50ef47e5306d2dae.e7b7e8c70ac7e639.263e62bb200473c5.7759ff0f653c8d6a
+ df52df845d98f4f5.5d8037e790e549b8.0a728624a94e1657.5526e06f22945d52
+ 7bff1b6b175be2d3
+ after
+ b85a78cd3fc2a910.2ccca189623bec19.dc1402eb0e465a8e.23b7587024ab1fb6
+ e135f8f78580fec6.4a94b5cb2f13db3d.b60d0a4c4bb0c83b.854e7bde44c8386f
+ 0000000000000000.0000000000000000.8000000000000000.0000000000000000
+ df52df845d98f4f5.5d8037e790e549b8.0a728624a94e1657.5526e06f22945d52
+ 7bff1b6b175be2d3
+
+VCVTTPS2DQ_128(reg)
+ before
+ 4531ab6de11e599a.6c2a3ebe270a0cc7.0a3c9c985cf83f67.3c77f273019b6e1e
+ 0f088ce31c67fe53.d145df81abd1344f.483715470b8d06f2.9917239444f63745
+ 35d0ba3763c50ca9.eb6e3fb804f826ba.75bd9e5e382fd804.fe1f94738f6c2cf9
+ 13d532d752c1c049.9670d84f4f8c9f33.eb1a314b7f6af24a.455bc1fcfe080a66
+ 4b97261cacd68db7
+ after
+ 4531ab6de11e599a.6c2a3ebe270a0cc7.0a3c9c985cf83f67.3c77f273019b6e1e
+ 0f088ce31c67fe53.d145df81abd1344f.483715470b8d06f2.9917239444f63745
+ 0000000000000000.0000000000000000.8000000080000000.00000dbc80000000
+ 13d532d752c1c049.9670d84f4f8c9f33.eb1a314b7f6af24a.455bc1fcfe080a66
+ 4b97261cacd68db7
+VCVTTPS2DQ_128(mem)
+ before
+ ec9e3fbdb5e27119.0562ee2e86e956df.af182832a7975be7.089acc797dcb8f6f
+ 053e89cd363971b8.67c5eca89ac80916.1032aa4d29281602.26886954ceddec20
+ 70417f374ae64abf.954827b12bea179b.968ada8cf0488baf.a23206480d2c4508
+ 0a749de60ef6b85a.ea389cb5d4dcba19.1dec35db1805771b.d9e29fc1d745d6d4
+ 25e52e2bc7b3da30
+ after
+ ec9e3fbdb5e27119.0562ee2e86e956df.af182832a7975be7.089acc797dcb8f6f
+ 053e89cd363971b8.67c5eca89ac80916.1032aa4d29281602.26886954ceddec20
+ 0000000000000000.0000000000000000.0000000000000000.0000000080000000
+ 0a749de60ef6b85a.ea389cb5d4dcba19.1dec35db1805771b.d9e29fc1d745d6d4
+ 25e52e2bc7b3da30
+
+VCVTTPS2DQ_256(reg)
+ before
+ e387b1f279028ec7.afa35fc89d7476b6.c4e14520322a2e3d.81243626be6a9572
+ 6f1323838abf2e46.3b9a42c8146c42ff.7e8f205fe05eb1b3.9ffd585afe84a3df
+ 25d780489575f558.8a25c0d28eebd661.738e28dc7b067d26.51441a61f25e5b8e
+ 621dc4af37b020aa.781057d227fbee07.01295a059eadcf43.74c6f529b9047aac
+ e44d669d6d83bb65
+ after
+ e387b1f279028ec7.afa35fc89d7476b6.c4e14520322a2e3d.81243626be6a9572
+ 6f1323838abf2e46.3b9a42c8146c42ff.7e8f205fe05eb1b3.9ffd585afe84a3df
+ 8000000000000000.8000000000000000.0000000000000000.8000000000000000
+ 621dc4af37b020aa.781057d227fbee07.01295a059eadcf43.74c6f529b9047aac
+ e44d669d6d83bb65
+VCVTTPS2DQ_256(mem)
+ before
+ 7da5eaa82ae6dbe5.8033ec220cfdebe8.e12682b5fcab481d.83adb044e5e0e2b5
+ 1b9cfc380d399656.dc63f30faee792bd.a134be6529049ed0.54672807ed2af329
+ 99fd18383188a8e7.d2fad5e1bcfa50d6.940685cfc914ac4c.d2a1bdb952173e4a
+ d593bb94b3e0ccc2.be438e04cfc362de.966855e0f9e730bd.57a76bc6af33ffc5
+ 41c72e9aa00b7246
+ after
+ 7da5eaa82ae6dbe5.8033ec220cfdebe8.e12682b5fcab481d.83adb044e5e0e2b5
+ 1b9cfc380d399656.dc63f30faee792bd.a134be6529049ed0.54672807ed2af329
+ 8000000000000000.0000000000000000.8000000080000000.0000000080000000
+ d593bb94b3e0ccc2.be438e04cfc362de.966855e0f9e730bd.57a76bc6af33ffc5
+ 41c72e9aa00b7246
+
+VCVTTPS2DQ_256(reg)
+ before
+ ea4c03a1c22bd278.aa2b6038ae4dbf14.fc8c1be486cd0482.8326a983d387e44e
+ b081e547b11d5c08.f49182113fd93d08.e82076ed7aa5726e.370cfda37602852b
+ edb3d0f8086f4ba2.8f91a009819202cb.de4a9d8b49d6e74d.8ee5ce2efc64cf81
+ ff2ec02063addcf1.57f7330e9084c989.3a578b2b8feca0cc.637f970f81b77d7c
+ 94a4d43222094c47
+ after
+ ea4c03a1c22bd278.aa2b6038ae4dbf14.fc8c1be486cd0482.8326a983d387e44e
+ b081e547b11d5c08.f49182113fd93d08.e82076ed7aa5726e.370cfda37602852b
+ 8000000080000000.8000000000000000.0000000000000000.8000000000000000
+ ff2ec02063addcf1.57f7330e9084c989.3a578b2b8feca0cc.637f970f81b77d7c
+ 94a4d43222094c47
+VCVTTPS2DQ_256(mem)
+ before
+ fc210183fa66f80f.403eb12c5f614ba1.278eb80a89b94f6d.57933d37e773d896
+ 76c29aee26d83d00.0d2fa0869719d460.dd24aceb883f50a4.934aad1deef8cd58
+ e0521c60c16dd645.c24d889ca861b3d8.54838a9ca8228759.49c7d9473f06b9be
+ 159f01c3e831800b.bce365d92dc323b5.6778ce08056db1b9.d558bc23762ad973
+ 9347521c30ef6824
+ after
+ fc210183fa66f80f.403eb12c5f614ba1.278eb80a89b94f6d.57933d37e773d896
+ 76c29aee26d83d00.0d2fa0869719d460.dd24aceb883f50a4.934aad1deef8cd58
+ 8000000080000000.0000000280000000.0000000000000000.8000000080000000
+ 159f01c3e831800b.bce365d92dc323b5.6778ce08056db1b9.d558bc23762ad973
+ 9347521c30ef6824
+
+VCVTTPS2DQ_256(reg)
+ before
+ dee2989d08e1a47c.f073c705b62ff77d.553e33a9c3cd61a4.f4cff51dbc2c8aef
+ 147388149b8cc728.4f9bea104873f6c8.eaabef78050ba851.d55479c6e96bce29
+ 904720ed857d0dd3.0ce3e4d2b9093a17.d77394b28f073667.e8d3d8efa7373890
+ ada95b92613fb42a.0517333526fe7f97.78e51ec3ff4f4593.07178d85129b8552
+ 10ed147247a3719b
+ after
+ dee2989d08e1a47c.f073c705b62ff77d.553e33a9c3cd61a4.f4cff51dbc2c8aef
+ 147388149b8cc728.4f9bea104873f6c8.eaabef78050ba851.d55479c6e96bce29
+ 0000000080000000.0000000000000000.8000000080000000.0000000000000000
+ ada95b92613fb42a.0517333526fe7f97.78e51ec3ff4f4593.07178d85129b8552
+ 10ed147247a3719b
+VCVTTPS2DQ_256(mem)
+ before
+ dd22eaa3615cb797.c9e73670cb5ff6d9.14035227aa5d8174.294c8917ee6f1280
+ 4c808a057dd11471.3e4babf36068108b.1773bd936132fbd9.46f3d11afaf2d8db
+ 37d37082b60f4456.6a23b888bbe63ded.e832f065688aaaf3.2c28f339bf64d450
+ 7be9180829210371.a7b958997966bbab.640d6889db704aee.3535eaded851428a
+ bd67b277e1465e36
+ after
+ dd22eaa3615cb797.c9e73670cb5ff6d9.14035227aa5d8174.294c8917ee6f1280
+ 4c808a057dd11471.3e4babf36068108b.1773bd936132fbd9.46f3d11afaf2d8db
+ 8000000080000000.ffe31932ff200927.0000000000000000.0000000080000000
+ 7be9180829210371.a7b958997966bbab.640d6889db704aee.3535eaded851428a
+ bd67b277e1465e36
+
+VCVTDQ2PS_128(reg)
+ before
+ 220a476e77ce63ff.f58dfe82f1130cef.535a87943573c470.68d09fecd4f196f5
+ bf6aa63135758e92.7f8a9fdc2bf11cfb.c85142e48b9994e8.ce47137872184b34
+ f0d2c92bb8c81b9a.f6ad7602f2c8efc2.63ec83f4186569c1.733e401acff125d9
+ 1190aec89b5246c5.37c2ffe062a34070.8176483278627da5.3481a0bf0788e00d
+ ebdbb15137ea37ff
+ after
+ 220a476e77ce63ff.f58dfe82f1130cef.535a87943573c470.68d09fecd4f196f5
+ bf6aa63135758e92.7f8a9fdc2bf11cfb.c85142e48b9994e8.ce47137872184b34
+ 0000000000000000.0000000000000000.cefd13704ef0c4fb.4e5206834cf11c02
+ 1190aec89b5246c5.37c2ffe062a34070.8176483278627da5.3481a0bf0788e00d
+ ebdbb15137ea37ff
+VCVTDQ2PS_128(mem)
+ before
+ 751aedbe7a22e7d9.7eee51747ba04abc.1c95b662988fcc30.7c3a8c09461c0d40
+ ae08d3f1ed3dacc7.9339ac9bf33d642e.82f21774b0974f2f.b1854be51f20543f
+ 7272dcd6ab4641f7.abbdbda9a0b5cfc5.45a59f02c5c78598.7da382339ef9904e
+ 9d248559d1496492.24c67e0b1d94c92d.4179c9f9f32b2998.3ae02c5d5f33fb18
+ 458845d0ff5bd14a
+ after
+ 751aedbe7a22e7d9.7eee51747ba04abc.1c95b662988fcc30.7c3a8c09461c0d40
+ ae08d3f1ed3dacc7.9339ac9bf33d642e.82f21774b0974f2f.b1854be51f20543f
+ 0000000000000000.0000000000000000.4de4adb3cecee068.4ef875184e8c381a
+ 9d248559d1496492.24c67e0b1d94c92d.4179c9f9f32b2998.3ae02c5d5f33fb18
+ 458845d0ff5bd14a
+
+VCVTDQ2PS_128(reg)
+ before
+ fae6c9f919fc508f.0bea4b667a53cfc7.599fed2b07678c13.523b114357d0f85b
+ b548b4424aa2b294.988fa9e9c36f3ec0.a5960677f9ba5523.54b8f3ce0dc2ae0c
+ d3f803192dda3405.20e11bcec7a96fa9.66f5c35990175f08.23baec852f0b07d8
+ ae43b1e95f2f128d.7faa1e02a20e1cb0.f709223f670ce86f.9b0d7753dcb9beea
+ 987f10262ed7906f
+ after
+ fae6c9f919fc508f.0bea4b667a53cfc7.599fed2b07678c13.523b114357d0f85b
+ b548b4424aa2b294.988fa9e9c36f3ec0.a5960677f9ba5523.54b8f3ce0dc2ae0c
+ 0000000000000000.0000000000000000.cd0f6ddc4ece19d1.cec9e511ce0d1904
+ ae43b1e95f2f128d.7faa1e02a20e1cb0.f709223f670ce86f.9b0d7753dcb9beea
+ 987f10262ed7906f
+VCVTDQ2PS_128(mem)
+ before
+ f6db33e941723893.a375ba1d7c2d87d9.91b72c6f71a801fe.b31e1e941a242a04
+ 91ec5c8831957481.0eda1a231e61d094.32d4c3035086dcc2.f880b3c346ec6172
+ 457f08f01c4cfe66.4bbdcd66e356296b.3ecd5ea85ab16726.207bdd3a87efcb66
+ ee60b20b1ba4936d.b66cd0526799cd0a.916d794cab375f56.895a996578b9a28b
+ 8d6be2aeb5d7238e
+ after
+ f6db33e941723893.a375ba1d7c2d87d9.91b72c6f71a801fe.b31e1e941a242a04
+ 91ec5c8831957481.0eda1a231e61d094.32d4c3035086dcc2.f880b3c346ec6172
+ 0000000000000000.0000000000000000.cedc91a74ee35004.ce99c3c34dd12150
+ ee60b20b1ba4936d.b66cd0526799cd0a.916d794cab375f56.895a996578b9a28b
+ 8d6be2aeb5d7238e
+
+VCVTDQ2PS_128(reg)
+ before
+ 89f8b482dbd4891a.675bd6c64ca8eec3.ab311e5445b4fa1c.078291da6024807f
+ da4e0b4d853c12dc.8e3cf00ecb64cc94.8559b3d61a36ea4e.7bd6213e948285cd
+ dab9e37c509cf880.3ece7dcdb3e5e90b.a2308b4581a8d94b.cb36a464645f2b6c
+ e6853979d77f77b1.52dff7f121360154.5d02a30e179805c0.d26e9938ebc72e86
+ 6b4a79a646c54a4a
+ after
+ 89f8b482dbd4891a.675bd6c64ca8eec3.ab311e5445b4fa1c.078291da6024807f
+ da4e0b4d853c12dc.8e3cf00ecb64cc94.8559b3d61a36ea4e.7bd6213e948285cd
+ 0000000000000000.0000000000000000.4eba05464dbcc02e.ce36459bcda1c68c
+ e6853979d77f77b1.52dff7f121360154.5d02a30e179805c0.d26e9938ebc72e86
+ 6b4a79a646c54a4a
+VCVTDQ2PS_128(mem)
+ before
+ 7496c29a90653ae2.5bfd08b2b771cd1c.a839dc653063cf9d.121bf69b7791a859
+ c81dee01e6b3bb7b.936f4c928bff346c.1ba9a814fc791110.1dc6805a3d20ffc1
+ 42ad7bc563bc8940.eb250285f0b4e94e.86fbd5eca28380d9.d9513db606cf45a4
+ c010e5d4248b5f5e.bf6c24f6811c286e.c7fbe1d83e8edb25.a406291b6d2db7b0
+ d93241f50fc3918f
+ after
+ 7496c29a90653ae2.5bfd08b2b771cd1c.a839dc653063cf9d.121bf69b7791a859
+ c81dee01e6b3bb7b.936f4c928bff346c.1ba9a814fc791110.1dc6805a3d20ffc1
+ 0000000000000000.0000000000000000.ceaf8c474e418f3e.4d90dfb54eef2351
+ c010e5d4248b5f5e.bf6c24f6811c286e.c7fbe1d83e8edb25.a406291b6d2db7b0
+ d93241f50fc3918f
+
+VCVTDQ2PS_256(reg)
+ before
+ d32180b0881f0fed.1c13a618442cfa00.6c90b053dbc42c77.b87546c4eaa4dc20
+ f01fe2b872cc6c77.34823c7fe0ac1654.4cdda10899373216.3734839dc5d440f5
+ 8b7763796c57e6d9.e22922f413166f83.bc9ff37f580176f6.1e05114de927c3d1
+ ff770060104bb6be.04d3d463f977c0bc.1821a225b3af33c4.4bb56dc172ab20e0
+ 980e14e67d6b154d
+ after
+ d32180b0881f0fed.1c13a618442cfa00.6c90b053dbc42c77.b87546c4eaa4dc20
+ f01fe2b872cc6c77.34823c7fe0ac1654.4cdda10899373216.3734839dc5d440f5
+ cb08ffa04d825db6.4c9a7a8cccd107e8.4dc10d11ce98a198.4e976adc4ee55642
+ ff770060104bb6be.04d3d463f977c0bc.1821a225b3af33c4.4bb56dc172ab20e0
+ 980e14e67d6b154d
+VCVTDQ2PS_256(mem)
+ before
+ e3dd81a625735b44.aa69b4d7fa341bd3.744eceb8afd9c628.bcb1ab6646cca62c
+ 06ed30ef87d0b1f3.e69a7b4cc69f4fc4.0f648ddf514a3df6.049909afaee40bd9
+ de0c9dacbe8dd183.1056512912178f3c.b2e28bc4fad6e050.4c26b86a86849e78
+ 480445c9e6b77823.85e932dc772817e7.37944654c6886c63.f0a4b4056b379ab4
+ 4c5efaebf98a3c3a
+ after
+ e3dd81a625735b44.aa69b4d7fa341bd3.744eceb8afd9c628.bcb1ab6646cca62c
+ 06ed30ef87d0b1f3.e69a7b4cc69f4fc4.0f648ddf514a3df6.049909afaee40bd9
+ cde113f34e15cd6d.ceab2c96ccb97c86.4ee89d9dcea04c74.ce869ca94e8d994c
+ 480445c9e6b77823.85e932dc772817e7.37944654c6886c63.f0a4b4056b379ab4
+ 4c5efaebf98a3c3a
+
+VCVTDQ2PS_256(reg)
+ before
+ bba28588cb08c0b6.1ea2a3321c5962fd.9f9e1bd0935f2273.7b463979d26c9d5a
+ 9bba51487d3d62d3.3db233d37c7f4b3e.bcc307710247ee8a.5bc3e120398f2f62
+ 47f45a97acb55d3e.810071982135ee11.36a2f22b5f6cb4d8.b1d9b93618fbdda6
+ 1b9a9ce1f3fdeea2.c658da6d288808a3.6a88d86a465bb30a.5a523ca68abf6453
+ 32fbe85cace48095
+ after
+ bba28588cb08c0b6.1ea2a3321c5962fd.9f9e1bd0935f2273.7b463979d26c9d5a
+ 9bba51487d3d62d3.3db233d37c7f4b3e.bcc307710247ee8a.5bc3e120398f2f62
+ 4ddcd4e7cd402116.ce669c964e222023.4ed511b14e8cb766.4eb4a479ceea8137
+ 1b9a9ce1f3fdeea2.c658da6d288808a3.6a88d86a465bb30a.5a523ca68abf6453
+ 32fbe85cace48095
+VCVTDQ2PS_256(mem)
+ before
+ 15a139439978ec97.73f91492efa051ac.e986e83eac84541f.b5c1b69a549f25cc
+ df0da9496e866686.aa5dbd163b2bc108.c45519f8c93390b2.7199862725c447c9
+ 6c0eb659461ba88d.1e1193da73297b61.3493e8859ca37688.fb5c467d545755ae
+ 986fdb603e426ed9.2a6392483526bb64.150ad2d340dfc3cc.af56f1097de38b26
+ e9d284363df424de
+ after
+ 15a139439978ec97.73f91492efa051ac.e986e83eac84541f.b5c1b69a549f25cc
+ df0da9496e866686.aa5dbd163b2bc108.c45519f8c93390b2.7199862725c447c9
+ 4dad09cacecd0e27.4ee7f229cd82fd73.cdb3c8becea6f758.ce947c934ea93e4c
+ 986fdb603e426ed9.2a6392483526bb64.150ad2d340dfc3cc.af56f1097de38b26
+ e9d284363df424de
+
+VCVTDQ2PS_256(reg)
+ before
+ 051df96f2f175d82.3ffb944871077696.299db6ce1aaebdbc.438751cdd2f432ab
+ 5f834e22f0d771bd.3d7f5dfefb777aef.790cfcd7c04ebc16.9ad5e35f6ded8050
+ 53507eba1bc09e3c.6ec7b36ff99d3611.74fc5fcec392f51d.f6c203742ed669e8
+ 3dd085a34d5f1eaa.ae9f118587856827.78b9db21be04a47e.33192dfa30bca99e
+ 2ca5dedc90aafba0
+ after
+ 051df96f2f175d82.3ffb944871077696.299db6ce1aaebdbc.438751cdd2f432ab
+ 5f834e22f0d771bd.3d7f5dfefb777aef.790cfcd7c04ebc16.9ad5e35f6ded8050
+ 4e7742174e9abe3d.cea2c1ddcef0f530.4ef173b6ce83f6b7.4e4c64b84e42f2a6
+ 3dd085a34d5f1eaa.ae9f118587856827.78b9db21be04a47e.33192dfa30bca99e
+ 2ca5dedc90aafba0
+VCVTDQ2PS_256(mem)
+ before
+ bf33900769ac1c17.794f6049213f2eb4.d9d3f32ec03cca5e.df8f6d3b4d3204e5
+ c78fc165d8cfc832.63180a1834ed0906.cb2fd555c0cd19e2.07c90f880da752fd
+ 2085ece3f81ebb1b.57787e7c21f3ec4b.607e34e5a44411de.4ab5bf759af0ca73
+ a6e18e6ee6a5b0fe.b1bcbbe185e01330.738e8acc88ae6d7e.069d786c8e98a8f3
+ 95ce36da882b2728
+ after
+ bf33900769ac1c17.794f6049213f2eb4.d9d3f32ec03cca5e.df8f6d3b4d3204e5
+ c78fc165d8cfc832.63180a1834ed0906.cb2fd555c0cd19e2.07c90f880da752fd
+ ce8198e04ed35838.4ef29ec14e04fcbb.ce18b033ce7f0cd7.ce01c24b4e9a640a
+ a6e18e6ee6a5b0fe.b1bcbbe185e01330.738e8acc88ae6d7e.069d786c8e98a8f3
+ 95ce36da882b2728
+
+VCVTTPD2DQ_128(reg)
+ before
+ 5494f62c223684be.346e21f0bd716408.cd2ebab4fb3dba60.e22955f58616eaf0
+ a03bb2ccf844fb63.a8fa2357998d9365.071a795f1f981c88.881c104cbd88445e
+ d30e6828a7e1c7c0.dd4f0f8e9705f840.bbcef2508e7c7654.403338be461137f4
+ 4a5b13abca9a2584.ae3a6181d3e650c6.449523f2e475046f.e839473540bc7edf
+ 5bfcbb9ec495d64b
+ after
+ 5494f62c223684be.346e21f0bd716408.cd2ebab4fb3dba60.e22955f58616eaf0
+ a03bb2ccf844fb63.a8fa2357998d9365.071a795f1f981c88.881c104cbd88445e
+ 0000000000000000.0000000000000000.0000000000000000.8000000080000000
+ 4a5b13abca9a2584.ae3a6181d3e650c6.449523f2e475046f.e839473540bc7edf
+ 5bfcbb9ec495d64b
+VCVTTPD2DQ_128(mem)
+ before
+ 74460fe6f1a9fb63.616cb0c0fefa5159.f987951b683b5723.00ba08b0bc100285
+ 11e4bff7e003a854.758e39d5de8d87ec.9802284a7210c882.4a8a9bf8b2d9ab44
+ 0ca248bfafaf9a4a.e00dac5506e002e8.697795fa0e726110.7e51da35635a3c56
+ 434c25297aba8d70.ff3504ac137efffa.47b15815576cdcf8.f75bc0d36b21f167
+ 13f4493e64b90524
+ after
+ 74460fe6f1a9fb63.616cb0c0fefa5159.f987951b683b5723.00ba08b0bc100285
+ 11e4bff7e003a854.758e39d5de8d87ec.9802284a7210c882.4a8a9bf8b2d9ab44
+ 0000000000000000.0000000000000000.0000000000000000.8000000000000000
+ 434c25297aba8d70.ff3504ac137efffa.47b15815576cdcf8.f75bc0d36b21f167
+ 13f4493e64b90524
+
+VCVTTPD2DQ_128(reg)
+ before
+ 2c6771e3edafb539.90aed1215c2f3df2.2e523d47a1f4bacd.0d7ded886a0bf567
+ a002342c9f8e3d51.d194cb92711b65fe.c9af54904bcc6e0e.98a8d13f63596a88
+ c90f8f8619e2d919.e0c98c6ad688c2be.2c9943f4ad945969.c5fc7e275c65f588
+ 05db7d5ef438c43d.9b1a9195a785105e.b35d08e064d8b589.6e46722b74385393
+ 71512836c4e040d4
+ after
+ 2c6771e3edafb539.90aed1215c2f3df2.2e523d47a1f4bacd.0d7ded886a0bf567
+ a002342c9f8e3d51.d194cb92711b65fe.c9af54904bcc6e0e.98a8d13f63596a88
+ 0000000000000000.0000000000000000.0000000000000000.0000000080000000
+ 05db7d5ef438c43d.9b1a9195a785105e.b35d08e064d8b589.6e46722b74385393
+ 71512836c4e040d4
+VCVTTPD2DQ_128(mem)
+ before
+ a8eb1d366a687778.aeb2fa1ecf1b3b68.dc5457fdff1b0a0b.ba459ebe0c23be1b
+ f0decb1682ddb5ab.22e0033443177a46.8041598ffa586df1.9d9d01fc4001b2ca
+ 25f7b0c22749b698.bbb1920beeb8bc85.63ad1338b547f53b.b8b32e059cfecb43
+ 2402472676bb356b.d670a50f6c8b3ecf.626602e24bf55e16.67d22045bda74631
+ 0645d3283e875e42
+ after
+ a8eb1d366a687778.aeb2fa1ecf1b3b68.dc5457fdff1b0a0b.ba459ebe0c23be1b
+ f0decb1682ddb5ab.22e0033443177a46.8041598ffa586df1.9d9d01fc4001b2ca
+ 0000000000000000.0000000000000000.0000000000000000.8000000000000000
+ 2402472676bb356b.d670a50f6c8b3ecf.626602e24bf55e16.67d22045bda74631
+ 0645d3283e875e42
+
+VCVTTPD2DQ_128(reg)
+ before
+ f059431abc2b501f.c7cb0d2e8a3cef51.d06a37ac581c3cd0.5736a07bd96d63ad
+ 835b6c87d21e5877.eb1e7cc67fdaa076.03ec454e4ef5f235.1feb6bed7bbbc12d
+ 1a954bdb1decb2f4.6cc712db72a00406.cc40c961eba49baa.964fde264beb34c2
+ 1153db8238219942.26914a577f9bd62c.88b3c151cbb574da.982f7611670a7797
+ 0157ad9aeb2348d9
+ after
+ f059431abc2b501f.c7cb0d2e8a3cef51.d06a37ac581c3cd0.5736a07bd96d63ad
+ 835b6c87d21e5877.eb1e7cc67fdaa076.03ec454e4ef5f235.1feb6bed7bbbc12d
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 1153db8238219942.26914a577f9bd62c.88b3c151cbb574da.982f7611670a7797
+ 0157ad9aeb2348d9
+VCVTTPD2DQ_128(mem)
+ before
+ ad9301adf24361b3.c3e318e9c04a4a0e.f54aa027c1d6d314.9190288b89b3b972
+ 78aeed3699757e52.8e8ffe7a50f20104.b5bc9038545db7eb.4425fa79c12aa51d
+ 3e76ed21fbc55de2.cda589a385a6facf.42b49775553d3edd.fdbc338910a67688
+ dbb57d5b3540b88e.db6fb6cefaf1701c.78fe2fcadf802316.18a2d02511b4665f
+ f124ccbb61dfb14d
+ after
+ ad9301adf24361b3.c3e318e9c04a4a0e.f54aa027c1d6d314.9190288b89b3b972
+ 78aeed3699757e52.8e8ffe7a50f20104.b5bc9038545db7eb.4425fa79c12aa51d
+ 0000000000000000.0000000000000000.0000000000000000.8000000000000000
+ dbb57d5b3540b88e.db6fb6cefaf1701c.78fe2fcadf802316.18a2d02511b4665f
+ f124ccbb61dfb14d
+
+VCVTTPD2DQ_256(reg)
+ before
+ e48b23b69bb395ff.2b381ace62f14b83.163a80694b5fa097.3365d6230f3523c1
+ 4d26d1825cbd4c20.0acb3f689ee4d4ec.d852e3df157dc6eb.4fb7086b0065f90a
+ 8840d38b3f88125d.543a681306260df6.7f02dc9cf4d61dc4.a8be3f91cf1e631e
+ f124233de1a02562.e55011bdb5c2b3cd.6598650c83f6e2d0.1a47f97e976c1b29
+ 811eb11f7559de56
+ after
+ e48b23b69bb395ff.2b381ace62f14b83.163a80694b5fa097.3365d6230f3523c1
+ 4d26d1825cbd4c20.0acb3f689ee4d4ec.d852e3df157dc6eb.4fb7086b0065f90a
+ 0000000000000000.0000000000000000.8000000080000000.8000000000000000
+ f124233de1a02562.e55011bdb5c2b3cd.6598650c83f6e2d0.1a47f97e976c1b29
+ 811eb11f7559de56
+VCVTTPD2DQ_256(mem)
+ before
+ b80fe36084f367d2.e420bf04dd92bfda.99dbb751c8c4829c.e85e7c9b5e6951b9
+ 9de60b2ee04673c9.bd7ea24dd0e91d72.4ba5d4bb5b393590.62a21cb622bca62b
+ 0b6fa573a75cbe66.d88bc98255327bd5.d97be6e7892c89d4.30ae41c76a7b1cd3
+ de752e1df24304d6.91932e1108f814b0.1e2968c16ea93a95.afcfe83bd330f05d
+ 39500b7ff8695e74
+ after
+ b80fe36084f367d2.e420bf04dd92bfda.99dbb751c8c4829c.e85e7c9b5e6951b9
+ 9de60b2ee04673c9.bd7ea24dd0e91d72.4ba5d4bb5b393590.62a21cb622bca62b
+ 0000000000000000.0000000000000000.0000000080000000.0000000080000000
+ de752e1df24304d6.91932e1108f814b0.1e2968c16ea93a95.afcfe83bd330f05d
+ 39500b7ff8695e74
+
+VCVTTPD2DQ_256(reg)
+ before
+ 2b7fa8fe76b2a1c5.f1c52117df070044.43e1cf6486c725af.f67bd73527bd04fe
+ e2a6ba23e895f7fb.222bfa4d8ab370dd.4cc3a7e96b2bea7d.3c3dad2fcf73a23d
+ b8133e5ceba099c3.4b7336ab0d530dcd.0783b20b52b19fc6.ce3a689c83d7d17b
+ 0a102e141a5fc6c9.4a694f1d87f3963f.d06eed35d7e47f38.864083665ef64de7
+ 42197a7b7cdbd1aa
+ after
+ 2b7fa8fe76b2a1c5.f1c52117df070044.43e1cf6486c725af.f67bd73527bd04fe
+ e2a6ba23e895f7fb.222bfa4d8ab370dd.4cc3a7e96b2bea7d.3c3dad2fcf73a23d
+ 0000000000000000.0000000000000000.0000000080000000.8000000000000000
+ 0a102e141a5fc6c9.4a694f1d87f3963f.d06eed35d7e47f38.864083665ef64de7
+ 42197a7b7cdbd1aa
+VCVTTPD2DQ_256(mem)
+ before
+ dc92cac5fa931af3.34ea88b7125db8b8.fad9c38f12a0c55f.02d052d59751c77d
+ 3277ed32f428e4ec.92ed47b16e26ac3d.368e0dedca65575b.fbf5df572d83b241
+ 1e9461ad85a8ebc2.8064676eca46de03.dc56aa23cc4e085d.16298f2536067e31
+ 7eb4a122ca1feaa0.5a9de55bc34a8ab7.c6fb141e33689391.aeb85fac4e6765f9
+ 21ed49580f31a444
+ after
+ dc92cac5fa931af3.34ea88b7125db8b8.fad9c38f12a0c55f.02d052d59751c77d
+ 3277ed32f428e4ec.92ed47b16e26ac3d.368e0dedca65575b.fbf5df572d83b241
+ 0000000000000000.0000000000000000.8000000000000000.8000000000000000
+ 7eb4a122ca1feaa0.5a9de55bc34a8ab7.c6fb141e33689391.aeb85fac4e6765f9
+ 21ed49580f31a444
+
+VCVTTPD2DQ_256(reg)
+ before
+ c9154b9618f076bf.2ca52a7dde989eb3.7ce2bbe2f5bdeb05.d14ac9c81cbeb624
+ 047d60d002301916.063176aadd1fc326.4280e771fb2b3e98.da0f440fa25d2a42
+ 2c6e84746b7ec7f4.e6250395e4c01426.08c364727121bf1d.bb1501dde24fae16
+ 9f37b3edef66bc05.a94d4c2b0e884edf.2af72f53f42aa93f.512a7c20f7a3fccd
+ 791832c3fe62d192
+ after
+ c9154b9618f076bf.2ca52a7dde989eb3.7ce2bbe2f5bdeb05.d14ac9c81cbeb624
+ 047d60d002301916.063176aadd1fc326.4280e771fb2b3e98.da0f440fa25d2a42
+ 0000000000000000.0000000000000000.0000000000000000.0000000080000000
+ 9f37b3edef66bc05.a94d4c2b0e884edf.2af72f53f42aa93f.512a7c20f7a3fccd
+ 791832c3fe62d192
+VCVTTPD2DQ_256(mem)
+ before
+ 0dac9eb2129ae992.b723eaa6297236f7.2b75cd5678822d7c.0468427f20d339ab
+ eab33cd94f5600f9.d17d240db6306f73.496803043ebb6d2a.f2629b618fa6ab0d
+ ecf68824d2a3d1f2.4a935d8d312ca428.ddf4681f7a3ec914.50303567e0323a10
+ f044fe7fb78c19aa.7caf919236f011c0.c4e37a954b17fe67.7a1f0cfcad002461
+ cb7b1c8d929ea3ab
+ after
+ 0dac9eb2129ae992.b723eaa6297236f7.2b75cd5678822d7c.0468427f20d339ab
+ eab33cd94f5600f9.d17d240db6306f73.496803043ebb6d2a.f2629b618fa6ab0d
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ f044fe7fb78c19aa.7caf919236f011c0.c4e37a954b17fe67.7a1f0cfcad002461
+ cb7b1c8d929ea3ab
+
+VCVTPD2DQ_128(reg)
+ before
+ a19062842b97f39b.d0681bd7191d934c.c41ebd89620af1e8.da03b451ca52c84f
+ 57aad94e167852dd.692d5a161462fd05.7e2cdbdc5106814b.fb1e923f16fce2f7
+ 49157d58ecccfa1c.9761372ac5681101.0725e9f89e6efd96.0300914b48210a8c
+ d21c4a0c4b1f2804.36ce2efd483b8c6b.b954e34ae5d0a074.ce772c617ecbfa3a
+ 384edf6dd4086e2c
+ after
+ a19062842b97f39b.d0681bd7191d934c.c41ebd89620af1e8.da03b451ca52c84f
+ 57aad94e167852dd.692d5a161462fd05.7e2cdbdc5106814b.fb1e923f16fce2f7
+ 0000000000000000.0000000000000000.0000000000000000.0000000080000000
+ d21c4a0c4b1f2804.36ce2efd483b8c6b.b954e34ae5d0a074.ce772c617ecbfa3a
+ 384edf6dd4086e2c
+VCVTPD2DQ_128(mem)
+ before
+ 1d50265b65e3248e.500d3dd8cffd1743.2241bc7db7e52970.f106c33cc3b8a792
+ 594a7d174e69d68d.1d32502613f30483.37865c953174a53b.0b88873cd3b14e9c
+ c808618eaaa54055.97d88164b48c2b70.51688a31d0f3bcf9.632429b5b247d13d
+ 46564daa95a32011.194bcbfd4d55c8b7.4cb5c23db06f2ad6.5527a712fb066b22
+ 3dddfdc14b7b59f6
+ after
+ 1d50265b65e3248e.500d3dd8cffd1743.2241bc7db7e52970.f106c33cc3b8a792
+ 594a7d174e69d68d.1d32502613f30483.37865c953174a53b.0b88873cd3b14e9c
+ 0000000000000000.0000000000000000.0000000000000000.0000000080000000
+ 46564daa95a32011.194bcbfd4d55c8b7.4cb5c23db06f2ad6.5527a712fb066b22
+ 3dddfdc14b7b59f6
+
+VCVTPD2DQ_128(reg)
+ before
+ 7791252d3d31d766.af00bd592c7030ee.fed62b5d7ad91704.043780a5eef3aafd
+ 5f911dc26eb4211e.dfd22d868b172d18.a4c79bf0d8a45302.54bb4155a58bf99b
+ 5127e0ed799172c9.b297191dcda4d3ba.656819220243b95e.1a0d8039f144d3db
+ a9a06a18fb530714.031dfe090e24dd01.9e06a05f954184c4.31f9b93df029f4ea
+ 754b684ebb4617f4
+ after
+ 7791252d3d31d766.af00bd592c7030ee.fed62b5d7ad91704.043780a5eef3aafd
+ 5f911dc26eb4211e.dfd22d868b172d18.a4c79bf0d8a45302.54bb4155a58bf99b
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ a9a06a18fb530714.031dfe090e24dd01.9e06a05f954184c4.31f9b93df029f4ea
+ 754b684ebb4617f4
+VCVTPD2DQ_128(mem)
+ before
+ c1cf0a5670a8f924.c348b7b08f871baa.b02e57386ba20818.aced2c142d2af1df
+ f3501a432b5a56a7.fa6bc422d1b8ec38.9497a096ff2a102c.e969baab648b3c5b
+ e69b14000768e9a8.ac558cd95e72b469.8b24560de7c9b169.b2c64592d9efa1e6
+ 757c747920df6f54.34510b40d241b0eb.70a0f38a3e8aa6fa.6450c83325e25c29
+ 595242fce7f1a8d3
+ after
+ c1cf0a5670a8f924.c348b7b08f871baa.b02e57386ba20818.aced2c142d2af1df
+ f3501a432b5a56a7.fa6bc422d1b8ec38.9497a096ff2a102c.e969baab648b3c5b
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 757c747920df6f54.34510b40d241b0eb.70a0f38a3e8aa6fa.6450c83325e25c29
+ 595242fce7f1a8d3
+
+VCVTPD2DQ_128(reg)
+ before
+ ee19ac58b8a7c28e.7ebfb69a93caa4d6.eeac3dc5c8b21b67.21d9f5f92179ac0b
+ 7ff203b33790e506.dc30574f7c36435b.35b31ed3dc50338c.7899d747aba37fca
+ 68274479fd394fe9.6a9bd284f52d0a0f.67b0abd6aba83204.53ad155ef913da61
+ 06046a16a82d3ae0.06cba3251dbdb31d.dff0df3ad045547b.8de12c2c26d67afc
+ 0101969c4ef61bc8
+ after
+ ee19ac58b8a7c28e.7ebfb69a93caa4d6.eeac3dc5c8b21b67.21d9f5f92179ac0b
+ 7ff203b33790e506.dc30574f7c36435b.35b31ed3dc50338c.7899d747aba37fca
+ 0000000000000000.0000000000000000.0000000000000000.8000000000000000
+ 06046a16a82d3ae0.06cba3251dbdb31d.dff0df3ad045547b.8de12c2c26d67afc
+ 0101969c4ef61bc8
+VCVTPD2DQ_128(mem)
+ before
+ 8cd9d19a8e8279f1.b3d771f6d4f8e29a.8a8e461e0ef2fab2.f8beb66be8b3d79e
+ 0b35581202834fa2.cceb56861c2785c1.d4ae375ce4d79dfa.10682cd58f7ff519
+ 58e0a8f0c5075a08.ad8b13301c455d01.bef8f3c9bc785620.81383ee55f34eb97
+ 51a73b20f319564e.b204a66171dfa708.2538f553b1e1e250.a97ce605f75ef4c5
+ e27e22a3f0894d4f
+ after
+ 8cd9d19a8e8279f1.b3d771f6d4f8e29a.8a8e461e0ef2fab2.f8beb66be8b3d79e
+ 0b35581202834fa2.cceb56861c2785c1.d4ae375ce4d79dfa.10682cd58f7ff519
+ 0000000000000000.0000000000000000.0000000000000000.0000000080000000
+ 51a73b20f319564e.b204a66171dfa708.2538f553b1e1e250.a97ce605f75ef4c5
+ e27e22a3f0894d4f
+
+VCVTPD2DQ_256(reg)
+ before
+ 8a8bee29e84232e0.d0578f8ea9c5fea2.37a20a86b77f9f7f.e639b9e4e01ffdb8
+ fbef44057b15df24.b2ba1f2603180f2d.98b13c0a89b48015.dbc9bc6a643d6282
+ 93f522a2448c90c9.d49c67d51b1d451d.317d365883078774.e1b278d05948ceda
+ aceb836ce0358078.10cbe38510e15c9e.5d51f6de4206f048.d5c16b02dc4bfded
+ 91c310ec0952aae7
+ after
+ 8a8bee29e84232e0.d0578f8ea9c5fea2.37a20a86b77f9f7f.e639b9e4e01ffdb8
+ fbef44057b15df24.b2ba1f2603180f2d.98b13c0a89b48015.dbc9bc6a643d6282
+ 0000000000000000.0000000000000000.0000000000000000.8000000080000000
+ aceb836ce0358078.10cbe38510e15c9e.5d51f6de4206f048.d5c16b02dc4bfded
+ 91c310ec0952aae7
+VCVTPD2DQ_256(mem)
+ before
+ f281e37afb6992f3.a31b63cfea9cece0.43121024fc6f0fdc.7a7b7707613cf73e
+ d4ca6198cf9d713e.d5d2be37fe4b0fab.493c699dfbd31b02.e345b53f7d35d702
+ 13690433a0f903f3.9c5c9010b9d02786.fe166adb2a1a3c3c.f4fcacf2317ecd40
+ 8b294a358a8a033f.5505d6c6b7b76e1c.3e6c8fcca44e2db8.09ec598d1aa314a3
+ 7d61b77ad32eead7
+ after
+ f281e37afb6992f3.a31b63cfea9cece0.43121024fc6f0fdc.7a7b7707613cf73e
+ d4ca6198cf9d713e.d5d2be37fe4b0fab.493c699dfbd31b02.e345b53f7d35d702
+ 0000000000000000.0000000000000000.8000000000000000.8000000080000000
+ 8b294a358a8a033f.5505d6c6b7b76e1c.3e6c8fcca44e2db8.09ec598d1aa314a3
+ 7d61b77ad32eead7
+
+VCVTPD2DQ_256(reg)
+ before
+ aea6c226f9ad8989.18d8ae8caa5b2e4e.5c198bc5938a201a.e50a555b867eac9f
+ f70976fe27ab2e65.9640ad221b78404b.0ee3ab7ae9d77b2b.d0bc3774ebb37320
+ b3d4d06cf9b51416.e12ec1e5faeef563.c5b13350562ab9fc.d94db103effb3e65
+ 4054cade0d567949.d56e68c062c808c1.decd1db2750d1739.dd8b3ff5af61cb9a
+ b7405d3447f2d4ec
+ after
+ aea6c226f9ad8989.18d8ae8caa5b2e4e.5c198bc5938a201a.e50a555b867eac9f
+ f70976fe27ab2e65.9640ad221b78404b.0ee3ab7ae9d77b2b.d0bc3774ebb37320
+ 0000000000000000.0000000000000000.0000005380000000.8000000080000000
+ 4054cade0d567949.d56e68c062c808c1.decd1db2750d1739.dd8b3ff5af61cb9a
+ b7405d3447f2d4ec
+VCVTPD2DQ_256(mem)
+ before
+ 453988add2b91587.f8d562bffc1a97aa.4ecb1d9f70123692.b584670ee30fd18d
+ 62423b4d6cc24c97.39a3937b648daae4.28135c6e3fd93a02.a6220ccf3bb922a5
+ ea27f2ff321a3347.5d0a5a7ee13cf0a3.3f10a219ec28d23c.0df308611a99472c
+ b9b329ae40cc87c3.c256b1340db3a395.6f8f698c920bb86d.464258301b3a7ccf
+ ad5df6a8db28fc3a
+ after
+ 453988add2b91587.f8d562bffc1a97aa.4ecb1d9f70123692.b584670ee30fd18d
+ 62423b4d6cc24c97.39a3937b648daae4.28135c6e3fd93a02.a6220ccf3bb922a5
+ 0000000000000000.0000000000000000.8000000080000000.8000000000000000
+ b9b329ae40cc87c3.c256b1340db3a395.6f8f698c920bb86d.464258301b3a7ccf
+ ad5df6a8db28fc3a
+
+VCVTPD2DQ_256(reg)
+ before
+ 9e8ee035f5f00518.abb45c48b1e40438.c2d29609877c0064.945c2fb34e8fa9c0
+ 75221143061dd116.9cf408b8a16f65d2.bbcb0469e92542bc.8a436f7b3bbf6062
+ 8d65863fa93c9cdf.6740a8ea2d7867bc.078df7c1cf3aa74a.2c10a6ce76a79a7e
+ 44a339937ad8a420.ea64b8ca700bc623.03646c7bd64569ba.588f4e9a1a541341
+ e98be5c943d187d7
+ after
+ 9e8ee035f5f00518.abb45c48b1e40438.c2d29609877c0064.945c2fb34e8fa9c0
+ 75221143061dd116.9cf408b8a16f65d2.bbcb0469e92542bc.8a436f7b3bbf6062
+ 0000000000000000.0000000000000000.8000000080000000.0000000080000000
+ 44a339937ad8a420.ea64b8ca700bc623.03646c7bd64569ba.588f4e9a1a541341
+ e98be5c943d187d7
+VCVTPD2DQ_256(mem)
+ before
+ bad1e6490e2ab16c.f52828ad167d2384.002cb44487353e33.0c9c5e0599d4c4b7
+ a92dcd05976c4f2a.fc3f4ef819b755b9.846419458d018a17.7c81c9c9b573f6ee
+ 916b16e9f9a21a40.b536a7df1e137868.54d762b79f7c67fc.b05ea935c5ac390a
+ 4d573ee150d8d1d8.7b5730d0c11cc640.4a530b87d8b0910d.0480fab4660dcab8
+ d533b9b23322e5a4
+ after
+ bad1e6490e2ab16c.f52828ad167d2384.002cb44487353e33.0c9c5e0599d4c4b7
+ a92dcd05976c4f2a.fc3f4ef819b755b9.846419458d018a17.7c81c9c9b573f6ee
+ 0000000000000000.0000000000000000.0000000080000000.0000000000000000
+ 4d573ee150d8d1d8.7b5730d0c11cc640.4a530b87d8b0910d.0480fab4660dcab8
+ d533b9b23322e5a4
+
+VMOVSLDUP_128(reg)
+ before
+ 7dc3e09bc975c579.bbbdc0d9b91b2e1f.acefe4369f5f7ceb.44a290a255abc377
+ 597c6ddbc394a7e4.b56818bd4f76ee40.a34abe7d5367d615.1d916df33179ba65
+ c5aa5bdebd0bc790.1926c2792ff6cd68.bbb4bc117ac00f6b.b0ec1f6588253204
+ 1d98a7105465602a.c1c13bfa75a586c2.5278da5faff66599.da7f21e677bbe780
+ 7815ef611a479404
+ after
+ 7dc3e09bc975c579.bbbdc0d9b91b2e1f.acefe4369f5f7ceb.44a290a255abc377
+ 597c6ddbc394a7e4.b56818bd4f76ee40.a34abe7d5367d615.1d916df33179ba65
+ 0000000000000000.0000000000000000.aff66599aff66599.77bbe78077bbe780
+ 1d98a7105465602a.c1c13bfa75a586c2.5278da5faff66599.da7f21e677bbe780
+ 7815ef611a479404
+VMOVSLDUP_128(mem)
+ before
+ 647c05c28cd6f6bd.bd944cde242eaf5e.8a06fd2a3b92d77b.c2e412d18f96114a
+ 7c7ee0f5e973c9d7.01e845b2c8f2f0d7.51c186f7a0c679bf.694262d4b52c522b
+ 9ae8fbe74e2bc87d.45e190fadc3e5f42.f0bd524bbd4f2bb9.a1dfc5d5be4262e8
+ 9b86d282d708b0db.e5cb2920fd9d374a.45c8db14b038a796.c807373f45667e2c
+ 3806b57de724e2a3
+ after
+ 647c05c28cd6f6bd.bd944cde242eaf5e.8a06fd2a3b92d77b.c2e412d18f96114a
+ 7c7ee0f5e973c9d7.01e845b2c8f2f0d7.51c186f7a0c679bf.694262d4b52c522b
+ 0000000000000000.0000000000000000.3b92d77b3b92d77b.8f96114a8f96114a
+ 9b86d282d708b0db.e5cb2920fd9d374a.45c8db14b038a796.c807373f45667e2c
+ 3806b57de724e2a3
+
+VMOVSLDUP_128(reg)
+ before
+ 4f2739fd3f06c9fb.5c24e1b39f193d1f.3df20a92c69bb59c.2aac9f3d958daa82
+ 67b8c12aea9a71dd.b78ea467c2672b72.a9a131bbd4c515e4.7c3618b2875bf0a8
+ dd034870836b13f8.898f98885d003503.85269907c3a693cd.1733c45fa3ad3534
+ 0d55ca3ba606eef6.aef438048bef18fc.2ccb3ee22dcb6a04.d76c1f3004903454
+ 99b0a311c60faa31
+ after
+ 4f2739fd3f06c9fb.5c24e1b39f193d1f.3df20a92c69bb59c.2aac9f3d958daa82
+ 67b8c12aea9a71dd.b78ea467c2672b72.a9a131bbd4c515e4.7c3618b2875bf0a8
+ 0000000000000000.0000000000000000.2dcb6a042dcb6a04.0490345404903454
+ 0d55ca3ba606eef6.aef438048bef18fc.2ccb3ee22dcb6a04.d76c1f3004903454
+ 99b0a311c60faa31
+VMOVSLDUP_128(mem)
+ before
+ 37caceef063652fa.54fb44f7f0f63c84.028a00c66941908a.fcdd1db8b1bfd734
+ 8e851bb4e012ead9.0c3eb110fdc73a4d.611b6cba120158d8.50a830f5e80e160a
+ 7aaf064e6fae2cfa.926d0df3680624fe.a873f9cca33b2e13.8478750671446232
+ d7120ba7cf16d48b.42d3540acd3e3642.b16021e837fbcc66.f398e755e5eef857
+ fb568250e2981425
+ after
+ 37caceef063652fa.54fb44f7f0f63c84.028a00c66941908a.fcdd1db8b1bfd734
+ 8e851bb4e012ead9.0c3eb110fdc73a4d.611b6cba120158d8.50a830f5e80e160a
+ 0000000000000000.0000000000000000.6941908a6941908a.b1bfd734b1bfd734
+ d7120ba7cf16d48b.42d3540acd3e3642.b16021e837fbcc66.f398e755e5eef857
+ fb568250e2981425
+
+VMOVSLDUP_128(reg)
+ before
+ f7fc436104ccf24a.817ba7ad1d56a0b5.78bb82c3c9fcabc6.59ad62faea4eeefe
+ 42d725f6e618cd70.54b6544b747b4aa7.91729489f7cac036.7c2538eeda405207
+ 3a33237a2407e243.2c8e906df1918f8b.e74485c7f436b03d.f6951db120dbb2ac
+ 395c3c595b266d70.e5d1d7ffafa22b8d.d77d51eb5bccb988.a2ca8f2dda2dca19
+ 5e8d08502442587c
+ after
+ f7fc436104ccf24a.817ba7ad1d56a0b5.78bb82c3c9fcabc6.59ad62faea4eeefe
+ 42d725f6e618cd70.54b6544b747b4aa7.91729489f7cac036.7c2538eeda405207
+ 0000000000000000.0000000000000000.5bccb9885bccb988.da2dca19da2dca19
+ 395c3c595b266d70.e5d1d7ffafa22b8d.d77d51eb5bccb988.a2ca8f2dda2dca19
+ 5e8d08502442587c
+VMOVSLDUP_128(mem)
+ before
+ 05ad0604192416ff.9d9e69ff2700a9a3.5b49a3edcbbcd9da.bd69f460c91715c2
+ 73f50537d5e1c1ce.c044a8d82321d387.69c3722360eb569e.f5546a92d9a30198
+ 84307fd475841516.009cf350eb1627c9.ed0bbf8d8b395e05.db89b0ed28fcb8b6
+ 142cf2c7141acd03.b7f048d31c6ae114.c2ed061867b4ad3a.cb55c1dd51af77c7
+ 200599cff1477a78
+ after
+ 05ad0604192416ff.9d9e69ff2700a9a3.5b49a3edcbbcd9da.bd69f460c91715c2
+ 73f50537d5e1c1ce.c044a8d82321d387.69c3722360eb569e.f5546a92d9a30198
+ 0000000000000000.0000000000000000.cbbcd9dacbbcd9da.c91715c2c91715c2
+ 142cf2c7141acd03.b7f048d31c6ae114.c2ed061867b4ad3a.cb55c1dd51af77c7
+ 200599cff1477a78
+
+VMOVSLDUP_256(reg)
+ before
+ 38e3342da351fd74.feb3d9fccfaea6c1.428da3ce52a93c16.c435c3ae1068fe69
+ 6e3b8f6503573b68.2092b05fc14d5c7a.febffeab27607578.cfaf733da45f0ebf
+ 1e5ba5e1aee871ff.5595f3dc0701ab5d.45d257d73a1ac8e8.be2690af3ca79968
+ a48e720f408ddbe7.78871f5fbcd84e94.7411a9bf24637012.6f6798f2f64c5a8f
+ bd3e06f1ee580e61
+ after
+ 38e3342da351fd74.feb3d9fccfaea6c1.428da3ce52a93c16.c435c3ae1068fe69
+ 6e3b8f6503573b68.2092b05fc14d5c7a.febffeab27607578.cfaf733da45f0ebf
+ 408ddbe7408ddbe7.bcd84e94bcd84e94.2463701224637012.f64c5a8ff64c5a8f
+ a48e720f408ddbe7.78871f5fbcd84e94.7411a9bf24637012.6f6798f2f64c5a8f
+ bd3e06f1ee580e61
+VMOVSLDUP_256(mem)
+ before
+ 837757983fda710a.5b1ff25a54d4b5c9.6736afd5fdde024c.e8caf0ce84c8aaa2
+ 9fde05d305db3eb5.a15b212e86483a54.fd6c1f28e51d83b0.fb472870f3d4b243
+ eb3f8e8e5d69338e.d18efcf67376a732.15f6eb4691a48ced.0ad54e110f13c4a1
+ 45656db5628f0ac3.46047e21b6e9380f.8da18f191c7cda2f.71c05c1d74121b6a
+ 8c545000bd5cf447
+ after
+ 837757983fda710a.5b1ff25a54d4b5c9.6736afd5fdde024c.e8caf0ce84c8aaa2
+ 9fde05d305db3eb5.a15b212e86483a54.fd6c1f28e51d83b0.fb472870f3d4b243
+ 3fda710a3fda710a.54d4b5c954d4b5c9.fdde024cfdde024c.84c8aaa284c8aaa2
+ 45656db5628f0ac3.46047e21b6e9380f.8da18f191c7cda2f.71c05c1d74121b6a
+ 8c545000bd5cf447
+
+VMOVSLDUP_256(reg)
+ before
+ b7dd2626877d8be7.871e1f3431597f7e.5e09a318ec2d2898.3f36888fa3b329a1
+ 4ea6d8fb6d021bf4.8f341ef8e5d450eb.74e96748b0ceb479.098451934154356f
+ adfc64ec0b76e21a.3774e8eb9b0b3737.e3efc71d9f59185d.c5566611126bb9c7
+ 302cc563fe651a07.5caaf8fb6e0bf18e.0968be04545a90f1.507743f5330572d2
+ 87b5652bc02d1cbf
+ after
+ b7dd2626877d8be7.871e1f3431597f7e.5e09a318ec2d2898.3f36888fa3b329a1
+ 4ea6d8fb6d021bf4.8f341ef8e5d450eb.74e96748b0ceb479.098451934154356f
+ fe651a07fe651a07.6e0bf18e6e0bf18e.545a90f1545a90f1.330572d2330572d2
+ 302cc563fe651a07.5caaf8fb6e0bf18e.0968be04545a90f1.507743f5330572d2
+ 87b5652bc02d1cbf
+VMOVSLDUP_256(mem)
+ before
+ 44da479fd4f072b8.3380f7cee25cff64.dba1ca137bde3a1b.40a048676c5b57e1
+ 64b3653d8b5931ea.1245f69752e6cfe0.8e27da1edd93cd0b.e6e361b482eaaad8
+ c40b3bf202741580.29c6be2cea90c425.5206a50ab1336789.557d05563392c582
+ 3eb045a8544ddaa7.d4514cf847e51bdf.040ca6c212ccc4c2.eaba31b81ae0e38d
+ 02e5e048d45f41a2
+ after
+ 44da479fd4f072b8.3380f7cee25cff64.dba1ca137bde3a1b.40a048676c5b57e1
+ 64b3653d8b5931ea.1245f69752e6cfe0.8e27da1edd93cd0b.e6e361b482eaaad8
+ d4f072b8d4f072b8.e25cff64e25cff64.7bde3a1b7bde3a1b.6c5b57e16c5b57e1
+ 3eb045a8544ddaa7.d4514cf847e51bdf.040ca6c212ccc4c2.eaba31b81ae0e38d
+ 02e5e048d45f41a2
+
+VMOVSLDUP_256(reg)
+ before
+ f74c0e71fc9b1b70.af6d004d9ef13b8a.6f309b6704710fbb.7e0359321c699fe2
+ 2639b79f2e21ada1.f30de7ccfb6bf556.56b1a7e5bec0dd65.9db83a46ec17b514
+ ecf9d83f077c32e2.e65d761088c8c437.e41e6dde105fc188.3df6c5eb9ee1c285
+ a3d86bbb2338e7de.6429290760136358.77c4e7be97d9f7d1.3a8b770b4dd38261
+ 7041cb9315f9b0d3
+ after
+ f74c0e71fc9b1b70.af6d004d9ef13b8a.6f309b6704710fbb.7e0359321c699fe2
+ 2639b79f2e21ada1.f30de7ccfb6bf556.56b1a7e5bec0dd65.9db83a46ec17b514
+ 2338e7de2338e7de.6013635860136358.97d9f7d197d9f7d1.4dd382614dd38261
+ a3d86bbb2338e7de.6429290760136358.77c4e7be97d9f7d1.3a8b770b4dd38261
+ 7041cb9315f9b0d3
+VMOVSLDUP_256(mem)
+ before
+ bbe63d7013600907.a8216e801ce20842.4a3d7d9ca05890e6.6aee13f2eebbbaec
+ f8444a8c6314492a.5722dcfb9105d0b9.7265ecbb63a4050c.19eaece4b2904784
+ 01286cd51f1f2b68.0c25b2961c2e7df0.b96cf451c6027ef7.df036e027ee4da46
+ b25e2136668f6dec.2378eabf59e74893.fb201048e47eb9d3.1a8496b6ee43afdd
+ 24ba5f6e9f3a01f6
+ after
+ bbe63d7013600907.a8216e801ce20842.4a3d7d9ca05890e6.6aee13f2eebbbaec
+ f8444a8c6314492a.5722dcfb9105d0b9.7265ecbb63a4050c.19eaece4b2904784
+ 1360090713600907.1ce208421ce20842.a05890e6a05890e6.eebbbaeceebbbaec
+ b25e2136668f6dec.2378eabf59e74893.fb201048e47eb9d3.1a8496b6ee43afdd
+ 24ba5f6e9f3a01f6
+
+VMOVSHDUP_128(reg)
+ before
+ 5bf1c5952d550d3d.e9b1e49b526fc9e3.f86582e1e5be704d.144bbd8dd92470cb
+ 1975c497331e0f5d.81ef31f0ffccfb79.e73975675b3f2fcb.e0ba750dc2015f0c
+ bc9258df4d234202.56e284218ab1c1d9.4c3fc0bf58f5c3b8.3a39b6b2bb2144c1
+ 9e937edc18efe3da.44575a1a0e2ad530.83c55d54776c65c1.0094fb6adf8ed917
+ 0d96c11f4a56db3a
+ after
+ 5bf1c5952d550d3d.e9b1e49b526fc9e3.f86582e1e5be704d.144bbd8dd92470cb
+ 1975c497331e0f5d.81ef31f0ffccfb79.e73975675b3f2fcb.e0ba750dc2015f0c
+ 0000000000000000.0000000000000000.83c55d5483c55d54.0094fb6a0094fb6a
+ 9e937edc18efe3da.44575a1a0e2ad530.83c55d54776c65c1.0094fb6adf8ed917
+ 0d96c11f4a56db3a
+VMOVSHDUP_128(mem)
+ before
+ 3d0d82bf19850655.1dc530f7300f2e8e.271a2ec7a744f4a9.e8154a9355305492
+ 6cc3bc3567251594.93756c9d300e5fcd.dbf77c15730ad971.d77d82e68dcecad6
+ 7585ea6d5144c525.5eed2e3ab478b141.3bbac0ee8b8841b4.ac4701babbd1043a
+ 361f8853f3eed232.d87a703b59da6197.252f77400dcbe89d.c3c0c37b7dc53e69
+ 7834c5966c37b310
+ after
+ 3d0d82bf19850655.1dc530f7300f2e8e.271a2ec7a744f4a9.e8154a9355305492
+ 6cc3bc3567251594.93756c9d300e5fcd.dbf77c15730ad971.d77d82e68dcecad6
+ 0000000000000000.0000000000000000.271a2ec7271a2ec7.e8154a93e8154a93
+ 361f8853f3eed232.d87a703b59da6197.252f77400dcbe89d.c3c0c37b7dc53e69
+ 7834c5966c37b310
+
+VMOVSHDUP_128(reg)
+ before
+ 27ee017626b2a0da.8a5d12d3672df8e7.5e67300ababfab7a.74211cf515de8a59
+ 2b3c758647c34174.4c0b05dacc0ff271.4d02691574b3ca97.035d2bfbbecde213
+ e2681d346af5d28a.5af4db523ba07dfc.ff9517c72243fc99.b0af203d24a5aef8
+ a7bff3eb2bd48ec8.8fe61329d2eb55b3.d16e368c61fa7a2d.56e377a76471a733
+ d0c5ad259a3e8cf1
+ after
+ 27ee017626b2a0da.8a5d12d3672df8e7.5e67300ababfab7a.74211cf515de8a59
+ 2b3c758647c34174.4c0b05dacc0ff271.4d02691574b3ca97.035d2bfbbecde213
+ 0000000000000000.0000000000000000.d16e368cd16e368c.56e377a756e377a7
+ a7bff3eb2bd48ec8.8fe61329d2eb55b3.d16e368c61fa7a2d.56e377a76471a733
+ d0c5ad259a3e8cf1
+VMOVSHDUP_128(mem)
+ before
+ fc213da3e016175e.d68ef51727edb2d8.c6ab2649adfc35c3.1fd7c3cfcc6483ff
+ b4c2a30d550705a5.ca1e1e24f9ca7969.dd1091a0e7dfda58.451db9feff0e51ba
+ d6765b50131d12f3.e1be6a7e3efa2125.aee1d1199da1009d.9f8c14859883210b
+ 3c07e2563663f974.75b9d5919106e4b9.17ea619fea4d63bf.8a6fd0ce30502f9d
+ 6014e94665ffb71d
+ after
+ fc213da3e016175e.d68ef51727edb2d8.c6ab2649adfc35c3.1fd7c3cfcc6483ff
+ b4c2a30d550705a5.ca1e1e24f9ca7969.dd1091a0e7dfda58.451db9feff0e51ba
+ 0000000000000000.0000000000000000.c6ab2649c6ab2649.1fd7c3cf1fd7c3cf
+ 3c07e2563663f974.75b9d5919106e4b9.17ea619fea4d63bf.8a6fd0ce30502f9d
+ 6014e94665ffb71d
+
+VMOVSHDUP_128(reg)
+ before
+ 7ec55c59d31ef437.c442b20cdbe57853.e45a5cca8f7cffd0.f2f6bd20eaefbee9
+ 40cf247415392396.48f3495f1daf48bd.88eef993d3e7ad17.1cd36187ba94ce48
+ 027e3d01c7db7fe7.a5e5223a19ce28dd.bfc2aa5afad42c39.724bcac176474f07
+ 201ea36e869046d5.b8e6ba88ea4dd2e0.e3206a899fceb6e4.ce2b72b83915fc53
+ 0d3fd7591f099258
+ after
+ 7ec55c59d31ef437.c442b20cdbe57853.e45a5cca8f7cffd0.f2f6bd20eaefbee9
+ 40cf247415392396.48f3495f1daf48bd.88eef993d3e7ad17.1cd36187ba94ce48
+ 0000000000000000.0000000000000000.e3206a89e3206a89.ce2b72b8ce2b72b8
+ 201ea36e869046d5.b8e6ba88ea4dd2e0.e3206a899fceb6e4.ce2b72b83915fc53
+ 0d3fd7591f099258
+VMOVSHDUP_128(mem)
+ before
+ 0c537590452fcd41.f5fb5326ede4b20d.5bc08b37ac3903f1.5254368e5f6187c1
+ a533c64ac693693b.df6147959964003b.6b4113327c9d773d.66ac09d4d51add7e
+ b5aa4872bf422171.399b7d27259b6b0a.c433cd657685eaf0.7c73dec79e84f2c7
+ 188576f34b47b210.5ff6f0482e163127.436335bcb5fd1735.f1f4b3d3552b0348
+ 1f7c8464969c4cac
+ after
+ 0c537590452fcd41.f5fb5326ede4b20d.5bc08b37ac3903f1.5254368e5f6187c1
+ a533c64ac693693b.df6147959964003b.6b4113327c9d773d.66ac09d4d51add7e
+ 0000000000000000.0000000000000000.5bc08b375bc08b37.5254368e5254368e
+ 188576f34b47b210.5ff6f0482e163127.436335bcb5fd1735.f1f4b3d3552b0348
+ 1f7c8464969c4cac
+
+VMOVSHDUP_256(reg)
+ before
+ 63574be6fe62089f.aa91ccbb87afd844.adbe9d644f608b3d.c29cc8245612bb39
+ 1ad106c5280974cf.4898c6b58e854e38.7e3f7ee72505b8f9.1eac018774cf9127
+ 9e36b06eb11ecce6.cc67e0cd7dd5d219.30c5913d4b91f306.335d5bd22b41572c
+ 4cd1454b352c4b90.13c997ef6fac1e12.1e9cd1d35e917712.dd7d55f29873c774
+ f8d668d2d6719d2a
+ after
+ 63574be6fe62089f.aa91ccbb87afd844.adbe9d644f608b3d.c29cc8245612bb39
+ 1ad106c5280974cf.4898c6b58e854e38.7e3f7ee72505b8f9.1eac018774cf9127
+ 4cd1454b4cd1454b.13c997ef13c997ef.1e9cd1d31e9cd1d3.dd7d55f2dd7d55f2
+ 4cd1454b352c4b90.13c997ef6fac1e12.1e9cd1d35e917712.dd7d55f29873c774
+ f8d668d2d6719d2a
+VMOVSHDUP_256(mem)
+ before
+ 6035115d0248977b.80f0c1ca4fbf2e7a.f98c66078115ee50.a40f3b13f99081c6
+ f166cd8137036f92.96dd21559b64b150.5a7ac901ce1c00ff.1d6cc96bb91b4cd1
+ 8734172992aee29c.eae5605ab6a610bd.12603dca72ce0e4a.e7fd794639bd15dc
+ fe6d6b412f56acc5.d8547a443b12866e.fd0b3c4c8a36d45e.5c0f460f15021896
+ daee2c34ea7791a9
+ after
+ 6035115d0248977b.80f0c1ca4fbf2e7a.f98c66078115ee50.a40f3b13f99081c6
+ f166cd8137036f92.96dd21559b64b150.5a7ac901ce1c00ff.1d6cc96bb91b4cd1
+ 6035115d6035115d.80f0c1ca80f0c1ca.f98c6607f98c6607.a40f3b13a40f3b13
+ fe6d6b412f56acc5.d8547a443b12866e.fd0b3c4c8a36d45e.5c0f460f15021896
+ daee2c34ea7791a9
+
+VMOVSHDUP_256(reg)
+ before
+ bbe5272054a7bbc2.32db46b528068838.bc766b7fc732500e.f645447532601066
+ 5d42343fee1ed48c.ff4b23719bca3322.f2963077f595aa4a.dbdad02f85587c8f
+ 1a4f4efe546815b4.40897d61a4af69ae.d602c39862c4d0ce.87985c689f2bd505
+ 505971c72312bde5.d361d2725ec0e609.c404224ea94dfd45.d649650b9de5d7f3
+ a4bb66049b903d86
+ after
+ bbe5272054a7bbc2.32db46b528068838.bc766b7fc732500e.f645447532601066
+ 5d42343fee1ed48c.ff4b23719bca3322.f2963077f595aa4a.dbdad02f85587c8f
+ 505971c7505971c7.d361d272d361d272.c404224ec404224e.d649650bd649650b
+ 505971c72312bde5.d361d2725ec0e609.c404224ea94dfd45.d649650b9de5d7f3
+ a4bb66049b903d86
+VMOVSHDUP_256(mem)
+ before
+ ccb8db3fb33ac4e9.59ad9907f6a806cc.939f9e8ee609655e.18e9480566bb6e5b
+ 2c0d40a804ef2849.9294c22b6ab42d15.5c0f5ba35797a3db.2efd322a369a5ebe
+ 9f86112ba8ba25d1.585de99d1ac46e6b.097c879bcd755ca9.628cda27b5770b18
+ 00eecbb4bba776af.055309cba364057b.78b39d6465af4bf7.0fe23e6a7eddaf15
+ 934a595e2e598762
+ after
+ ccb8db3fb33ac4e9.59ad9907f6a806cc.939f9e8ee609655e.18e9480566bb6e5b
+ 2c0d40a804ef2849.9294c22b6ab42d15.5c0f5ba35797a3db.2efd322a369a5ebe
+ ccb8db3fccb8db3f.59ad990759ad9907.939f9e8e939f9e8e.18e9480518e94805
+ 00eecbb4bba776af.055309cba364057b.78b39d6465af4bf7.0fe23e6a7eddaf15
+ 934a595e2e598762
+
+VMOVSHDUP_256(reg)
+ before
+ 4912276e5f76ceab.2d13e83059c2d80c.f6c11e20a01e2df1.848019e93b522def
+ 8d84a508b0c0c29c.01bfe689a0180717.87f52407ae802378.08af78166a69bebd
+ baedcd97bbc39cdf.57c041ada9b4bef9.153918ee681622bc.e20c34d70e00b98e
+ 2e999d871c0c9b23.0de0738692a2bae1.fadaf5406b6b686a.ec63cb184424dc8e
+ 047fb8c528e0e1e8
+ after
+ 4912276e5f76ceab.2d13e83059c2d80c.f6c11e20a01e2df1.848019e93b522def
+ 8d84a508b0c0c29c.01bfe689a0180717.87f52407ae802378.08af78166a69bebd
+ 2e999d872e999d87.0de073860de07386.fadaf540fadaf540.ec63cb18ec63cb18
+ 2e999d871c0c9b23.0de0738692a2bae1.fadaf5406b6b686a.ec63cb184424dc8e
+ 047fb8c528e0e1e8
+VMOVSHDUP_256(mem)
+ before
+ 042e77cbd44184c9.44d310447027fa12.fdebfa0277efb7f9.9323b769520b2f2e
+ ca3a85146751835d.57e9233b529ef459.05af510c73a6716e.3c625ad6ba82b3b4
+ 30705d8dfa1e98cf.c525d0d65fffc6a3.fff7f490a3d4a36b.51e2daf13e5d32a7
+ 149c7b23acb4804b.e8d5158232d5ab9d.c88e5f7a22830a1d.2eee34277a27e6b3
+ 2fd363e50b6c0c85
+ after
+ 042e77cbd44184c9.44d310447027fa12.fdebfa0277efb7f9.9323b769520b2f2e
+ ca3a85146751835d.57e9233b529ef459.05af510c73a6716e.3c625ad6ba82b3b4
+ 042e77cb042e77cb.44d3104444d31044.fdebfa02fdebfa02.9323b7699323b769
+ 149c7b23acb4804b.e8d5158232d5ab9d.c88e5f7a22830a1d.2eee34277a27e6b3
+ 2fd363e50b6c0c85
+
+VPERMILPS_VAR_128(reg)
+ before
+ b0dd63958cb9e0c9.50895bc1961ef7ff.1e43edac68ade0f2.3d420fb60cc262af
+ 0d5830a59a999d2b.c1057952d668b814.c1bc54bf9c12a150.38dd7e307e9a664e
+ a290c780d1998056.43da52c4889e80b9.2f8c47266b902a60.962c2ad59319d326
+ cbd02292cc43c5f6.b3d66002c7cd0b18.c2fec04f70b4b7d0.34fa8f8f684a6562
+ ec15274c193ad82f
+ after
+ 0000000000000000.0000000000000000.9c12a1507e9a664e.38dd7e309c12a150
+ 0d5830a59a999d2b.c1057952d668b814.c1bc54bf9c12a150.38dd7e307e9a664e
+ a290c780d1998056.43da52c4889e80b9.2f8c47266b902a60.962c2ad59319d326
+ cbd02292cc43c5f6.b3d66002c7cd0b18.c2fec04f70b4b7d0.34fa8f8f684a6562
+ ec15274c193ad82f
+VPERMILPS_VAR_128(mem)
+ before
+ 9b4870f6c0f3e7b9.e3663f472726a8b8.ebc321f8b000145d.d760bda54709834c
+ 1d5ee47b7c844f2b.489c1a0b7fcb6448.c86e11935e4458b6.cbfc39948d1bcb80
+ 4e2402c666f6ccb1.55bfad4a6fc03651.26a2aabdeda4934d.f81f3088de77ca17
+ 0b6643c39d571978.661bf67094905980.e12d6a637a2c814e.bb159fedd5a8bebd
+ 702a812f0e3ae120
+ after
+ 9b4870f6c0f3e7b9.e3663f472726a8b8.ebc321f8b000145d.d760bda54709834c
+ 1d5ee47b7c844f2b.489c1a0b7fcb6448.c86e11935e4458b6.cbfc39948d1bcb80
+ 0000000000000000.0000000000000000.8d1bcb80cbfc3994.cbfc39948d1bcb80
+ 0b6643c39d571978.661bf67094905980.e12d6a637a2c814e.bb159fedd5a8bebd
+ 702a812f0e3ae120
+
+VPERMILPS_VAR_128(reg)
+ before
+ 74aad2bb26ba6fe9.2ef0245d3ab2f4ac.d6fcefe989c80b81.d6d9cc7121e9dde6
+ 21e08efbb9b3a6c7.948e22835b141679.03ae9622eaf286ff.df744cd4fde66441
+ d41ab15d62b1c064.190bb81e1c883e0a.487ce785559d07a7.d9c866772a2fd28a
+ e9a2384cbd41fa6d.9935621b981a268b.00b3dc806352c924.a0a29745c5d0e2ee
+ 10ce5a2ce9d65298
+ after
+ 0000000000000000.0000000000000000.df744cd403ae9622.03ae9622eaf286ff
+ 21e08efbb9b3a6c7.948e22835b141679.03ae9622eaf286ff.df744cd4fde66441
+ d41ab15d62b1c064.190bb81e1c883e0a.487ce785559d07a7.d9c866772a2fd28a
+ e9a2384cbd41fa6d.9935621b981a268b.00b3dc806352c924.a0a29745c5d0e2ee
+ 10ce5a2ce9d65298
+VPERMILPS_VAR_128(mem)
+ before
+ 05172b17b34ddcb5.bcc51d3367ee908d.f0d69d66ecd78c29.89a0737eb29f0a23
+ 5a4b86f23e3f3c70.a9cf5e80fb45bd71.fabbe3ec33ca2910.3e8da7eade0f044f
+ ed34e7a9a7ba30f7.0c0cf79e16d0bec4.93b0b29789ffbc6b.7ac67432822ff356
+ 999fcb2809ca7273.41c8e2f9531dcf33.968185550b83ff67.9b99d6c13a8a15e1
+ fb51ca03a3aca49f
+ after
+ 05172b17b34ddcb5.bcc51d3367ee908d.f0d69d66ecd78c29.89a0737eb29f0a23
+ 5a4b86f23e3f3c70.a9cf5e80fb45bd71.fabbe3ec33ca2910.3e8da7eade0f044f
+ 0000000000000000.0000000000000000.33ca29103e8da7ea.33ca2910fabbe3ec
+ 999fcb2809ca7273.41c8e2f9531dcf33.968185550b83ff67.9b99d6c13a8a15e1
+ fb51ca03a3aca49f
+
+VPERMILPS_VAR_128(reg)
+ before
+ f7394b645922dd39.3a58ad5c8179bf13.a44e1dfd4fb82b69.e1f9d811d561af30
+ ec9e5551f677fb5e.ac2b092f2ad5d201.91eba316a52c1014.4fe628b601a588f1
+ 34cce43419373cb8.cbe45b8e21ea6869.64eb70b1f105b7dd.bc12ef32ae5c45d7
+ 2d0ff47a5cefdaf4.724f206681c23d78.799a8038d0cf5f73.034aab70f691a30d
+ 025ad85cf5505ec0
+ after
+ 0000000000000000.0000000000000000.4fe628b64fe628b6.a52c101491eba316
+ ec9e5551f677fb5e.ac2b092f2ad5d201.91eba316a52c1014.4fe628b601a588f1
+ 34cce43419373cb8.cbe45b8e21ea6869.64eb70b1f105b7dd.bc12ef32ae5c45d7
+ 2d0ff47a5cefdaf4.724f206681c23d78.799a8038d0cf5f73.034aab70f691a30d
+ 025ad85cf5505ec0
+VPERMILPS_VAR_128(mem)
+ before
+ 940ef0e3c8a6321c.31b382905b2a11bd.7f37d2a2666b0d5a.2c44d019de174380
+ 953270ef8a9eda4c.9d0489e1b3741fc0.cd69ef2dedf1933a.d8355bbeb6689eb0
+ e091d56d5844137c.cd4d05d8ff5a3ea8.37b1f3f5325e8d45.dbb81d95f44facb0
+ 53f99a4a4da599da.1edbf2e3dc67ab22.9bdb58e550c0b4a7.901b12093557ab2c
+ 52a83686150cd5cf
+ after
+ 940ef0e3c8a6321c.31b382905b2a11bd.7f37d2a2666b0d5a.2c44d019de174380
+ 953270ef8a9eda4c.9d0489e1b3741fc0.cd69ef2dedf1933a.d8355bbeb6689eb0
+ 0000000000000000.0000000000000000.edf1933aedf1933a.d8355bbeb6689eb0
+ 53f99a4a4da599da.1edbf2e3dc67ab22.9bdb58e550c0b4a7.901b12093557ab2c
+ 52a83686150cd5cf
+
+VPERMILPD_VAR_128(reg)
+ before
+ 7fac86772ffa6746.c8343b7085cc2790.eafa4d6de527a2da.d3b39ce96323c78b
+ 7273fd4b1fae9d3d.1d0f35cd1ec57aca.8ef611e2b6275e7b.bd0539ed8892801e
+ 8649976b82b4b25f.2c56034c319d4eb5.661b3aaeecf21cb2.339cadddda199c8b
+ 19795044f396e359.d3d520d9dc5f5f7d.ceb5c43d2314182a.134674a676c4d7ff
+ 37cd083277a0eca5
+ after
+ 0000000000000000.0000000000000000.8ef611e2b6275e7b.8ef611e2b6275e7b
+ 7273fd4b1fae9d3d.1d0f35cd1ec57aca.8ef611e2b6275e7b.bd0539ed8892801e
+ 8649976b82b4b25f.2c56034c319d4eb5.661b3aaeecf21cb2.339cadddda199c8b
+ 19795044f396e359.d3d520d9dc5f5f7d.ceb5c43d2314182a.134674a676c4d7ff
+ 37cd083277a0eca5
+VPERMILPD_VAR_128(mem)
+ before
+ 7dfee76ffab899aa.855125420fe26cd6.ec570b603b18684d.220fabfcf61a8d90
+ bfa58c471a19973a.281b11d271238983.55aa3dcd69d32652.be77ec55018fb890
+ da8d73a8f4cda580.5c24105eb6e6750b.e898330c829c55b8.fe3782b6e100d5d5
+ ab84187da3e37da9.7fb81e5479b66d1b.82ee6a09a37fb0aa.3e9c698932f7200c
+ daf29d3c8f03d4e0
+ after
+ 7dfee76ffab899aa.855125420fe26cd6.ec570b603b18684d.220fabfcf61a8d90
+ bfa58c471a19973a.281b11d271238983.55aa3dcd69d32652.be77ec55018fb890
+ 0000000000000000.0000000000000000.be77ec55018fb890.be77ec55018fb890
+ ab84187da3e37da9.7fb81e5479b66d1b.82ee6a09a37fb0aa.3e9c698932f7200c
+ daf29d3c8f03d4e0
+
+VPERMILPD_VAR_128(reg)
+ before
+ 2e851b3a94ad2efe.0c54f8b14464dce1.eb23371f571fad5f.00785db0e889f454
+ 96a0deeede836a12.dacb8e32f25e7e53.feb1582aebae7082.3c0288ee6bc5dde3
+ 6e91e1c60810c4c7.f2b356ebc9dc1f2b.12ad7ce3d1eef431.135868ad4b402783
+ 12a2232dafe077ca.2ed9ccc9e6eb7a96.84649fb5a66b7218.614577dba2058d60
+ 029633628c20cca5
+ after
+ 0000000000000000.0000000000000000.3c0288ee6bc5dde3.feb1582aebae7082
+ 96a0deeede836a12.dacb8e32f25e7e53.feb1582aebae7082.3c0288ee6bc5dde3
+ 6e91e1c60810c4c7.f2b356ebc9dc1f2b.12ad7ce3d1eef431.135868ad4b402783
+ 12a2232dafe077ca.2ed9ccc9e6eb7a96.84649fb5a66b7218.614577dba2058d60
+ 029633628c20cca5
+VPERMILPD_VAR_128(mem)
+ before
+ d3181730269da07e.dd209d906e80c0c6.6b086db665964cc0.b123bd0c06b229e2
+ ae95a0308b89c419.2d574d59e27bdb68.850eb39f61e950d5.f334d2558c4e533b
+ 70da484ed7eff69f.5d932df5a65e035b.58b51c71f6f04400.a7e3dbfad4cb2dd1
+ f5b28d7628dcef3f.c81f3cd157b4754c.c0cb231641b8e26d.297ed3687bb6f34d
+ d650b60c1d9ae15e
+ after
+ d3181730269da07e.dd209d906e80c0c6.6b086db665964cc0.b123bd0c06b229e2
+ ae95a0308b89c419.2d574d59e27bdb68.850eb39f61e950d5.f334d2558c4e533b
+ 0000000000000000.0000000000000000.f334d2558c4e533b.850eb39f61e950d5
+ f5b28d7628dcef3f.c81f3cd157b4754c.c0cb231641b8e26d.297ed3687bb6f34d
+ d650b60c1d9ae15e
+
+VPERMILPD_VAR_128(reg)
+ before
+ 08a48150550332ae.19ebea94975b6e23.cc49735790096de7.991a457c5e4ce649
+ 1cc72ea2bf7e23ea.b84fdb9542782d77.c45bcff5eeea27d7.bf6ffc8d68b90ec0
+ 6e05bb6df896efbd.aeacdc634540ea69.0ba24d150ce2dec9.0e96c6377b0a14fe
+ 5aaa231c9bd7d4d4.d7cc6aebbbbe5e22.ff6ae825867dcf69.625a1e65b44bb52e
+ 978980032e89ad7c
+ after
+ 0000000000000000.0000000000000000.bf6ffc8d68b90ec0.c45bcff5eeea27d7
+ 1cc72ea2bf7e23ea.b84fdb9542782d77.c45bcff5eeea27d7.bf6ffc8d68b90ec0
+ 6e05bb6df896efbd.aeacdc634540ea69.0ba24d150ce2dec9.0e96c6377b0a14fe
+ 5aaa231c9bd7d4d4.d7cc6aebbbbe5e22.ff6ae825867dcf69.625a1e65b44bb52e
+ 978980032e89ad7c
+VPERMILPD_VAR_128(mem)
+ before
+ 89ed69fd06cfb715.3c02621d45ce0cda.0f7c001ac0fe48d1.faff9c90f9473662
+ 1453533f57299025.705975db9106d47c.31871adb710d62a0.5aad65c201cd4e61
+ 1487bcb63da4f4d7.52fa57c31c0c6765.1bbb3419eaf669bb.79bf4027399b5411
+ 64551f4cd64b9f58.3e33033f816b0243.a8e2cbc246c5194f.b583282b3d3b841f
+ 6843193aaa3b1a36
+ after
+ 89ed69fd06cfb715.3c02621d45ce0cda.0f7c001ac0fe48d1.faff9c90f9473662
+ 1453533f57299025.705975db9106d47c.31871adb710d62a0.5aad65c201cd4e61
+ 0000000000000000.0000000000000000.5aad65c201cd4e61.31871adb710d62a0
+ 64551f4cd64b9f58.3e33033f816b0243.a8e2cbc246c5194f.b583282b3d3b841f
+ 6843193aaa3b1a36
+
+VPERMILPS_VAR_256(reg)
+ before
+ f04c0fc11b275103.e289f9ee3b2a4cd4.904e78bc5cafe1bf.b4ca59c1a1872d88
+ a7ea072a2d896632.69efc4898a4eb876.a398afa64a644088.1b3d5c0218476291
+ ea69fbe37bef956e.d452fe08dfc29e6b.d55da56ae7175a48.b8084f71c6117497
+ 1514e956a2e51964.017f22565592bcde.81e85773ce536cab.69f7affac8f21fc6
+ 09d5f68a39f51e49
+ after
+ a7ea072a2d896632.8a4eb876a7ea072a.4a64408818476291.1b3d5c02a398afa6
+ a7ea072a2d896632.69efc4898a4eb876.a398afa64a644088.1b3d5c0218476291
+ ea69fbe37bef956e.d452fe08dfc29e6b.d55da56ae7175a48.b8084f71c6117497
+ 1514e956a2e51964.017f22565592bcde.81e85773ce536cab.69f7affac8f21fc6
+ 09d5f68a39f51e49
+VPERMILPS_VAR_256(mem)
+ before
+ 7370a20b36262e4d.8539ccf13df52fc0.cb42ac6108cbccfc.0387c02c9ba5b25e
+ 85922e6ada920bfd.9422a11fe9ad132d.0d67181415788bf1.b784dc03eb98680d
+ 1909169442447086.9f1c624c41990157.a5bae35b98a6b4e8.f82ca8635ab8c963
+ 0d9fd77489491a13.02730de4e24334eb.6d078822ac5f050d.24cb1fb88391120d
+ 96ad3c6e02b07fb7
+ after
+ 7370a20b36262e4d.8539ccf13df52fc0.cb42ac6108cbccfc.0387c02c9ba5b25e
+ 85922e6ada920bfd.9422a11fe9ad132d.0d67181415788bf1.b784dc03eb98680d
+ 85922e6a9422a11f.9422a11fe9ad132d.b784dc03eb98680d.eb98680d15788bf1
+ 0d9fd77489491a13.02730de4e24334eb.6d078822ac5f050d.24cb1fb88391120d
+ 96ad3c6e02b07fb7
+
+VPERMILPS_VAR_256(reg)
+ before
+ a91efef174a04b0c.3b21ebf5cbabc5d1.19739d536739e995.431983556db1388e
+ bb6a5ead74eeb3b9.815ad00525782dec.40680e056c075c01.01be50e1f8a80994
+ 26dc590f9f25f369.b918018fb3bc0d8f.d49d5c678e38c8da.85c06cb0684f364e
+ 48c1ec8190d147c9.c125fb7f908222e7.2f6084e369586bcc.a9ec51b0dab279e6
+ 4b0e7dcb69dd8f89
+ after
+ bb6a5ead815ad005.bb6a5eadbb6a5ead.40680e056c075c01.f8a809946c075c01
+ bb6a5ead74eeb3b9.815ad00525782dec.40680e056c075c01.01be50e1f8a80994
+ 26dc590f9f25f369.b918018fb3bc0d8f.d49d5c678e38c8da.85c06cb0684f364e
+ 48c1ec8190d147c9.c125fb7f908222e7.2f6084e369586bcc.a9ec51b0dab279e6
+ 4b0e7dcb69dd8f89
+VPERMILPS_VAR_256(mem)
+ before
+ 45f16bef32dd3362.7b651271e47fea84.734f38c1d8d62820.aefb81e698f37f84
+ 7463980750bd239e.1d14c74936ba1947.ac603642a8c4da65.adbb4fddb79640ae
+ b52e7effdf8a1968.881a0877230e10be.492570ec1c59f5e2.87ecea3363ccecf6
+ e2209bc2fd4fd2ed.1ac3cf6646080a94.246a62ac4fa035c5.9ad94f533821bd07
+ 41d079abd022ef8d
+ after
+ 45f16bef32dd3362.7b651271e47fea84.734f38c1d8d62820.aefb81e698f37f84
+ 7463980750bd239e.1d14c74936ba1947.ac603642a8c4da65.adbb4fddb79640ae
+ 7463980750bd239e.1d14c74936ba1947.adbb4fddb79640ae.a8c4da65b79640ae
+ e2209bc2fd4fd2ed.1ac3cf6646080a94.246a62ac4fa035c5.9ad94f533821bd07
+ 41d079abd022ef8d
+
+VPERMILPS_VAR_256(reg)
+ before
+ d81b64a6ca5ac035.d8036a3fc3180959.2d5a1a823b334476.1afa896f5da65638
+ bb080cb0c0566aab.73a4675f4ff17bd7.1e2de4379f1bfa10.07a35f1f63761367
+ 46e16d354ea12a9a.8fce0f0fbde7e494.49862af10e4d680d.c72f62aa7c1c297f
+ d4f384a210c73caf.094fdd3b280500bb.0bb2e61c2354c919.376b0dfbc5a454ac
+ 3123ddfe591b4f19
+ after
+ 73a4675fc0566aab.bb080cb04ff17bd7.07a35f1f07a35f1f.9f1bfa101e2de437
+ bb080cb0c0566aab.73a4675f4ff17bd7.1e2de4379f1bfa10.07a35f1f63761367
+ 46e16d354ea12a9a.8fce0f0fbde7e494.49862af10e4d680d.c72f62aa7c1c297f
+ d4f384a210c73caf.094fdd3b280500bb.0bb2e61c2354c919.376b0dfbc5a454ac
+ 3123ddfe591b4f19
+VPERMILPS_VAR_256(mem)
+ before
+ 92234c9f558dd8f3.c3894c61a454db96.bbf14dd0ac588a79.befd16247abc5ae2
+ 3637d8cad404a865.6ef1c1dfa3d544fa.8282dbb866eb3ffa.bfb2b576b0125711
+ f92afc6bf28e7e9c.3076df89abd6b388.3acc03e171cadb69.6a1fbf7c61e1fb55
+ b7ca346ecc3614c4.6763a2c958e164eb.bf9c4236ea0219f3.1b8e30a427b58458
+ 2f4d0558a11b2bc6
+ after
+ 92234c9f558dd8f3.c3894c61a454db96.bbf14dd0ac588a79.befd16247abc5ae2
+ 3637d8cad404a865.6ef1c1dfa3d544fa.8282dbb866eb3ffa.bfb2b576b0125711
+ 3637d8ca3637d8ca.6ef1c1dfd404a865.b0125711bfb2b576.b012571166eb3ffa
+ b7ca346ecc3614c4.6763a2c958e164eb.bf9c4236ea0219f3.1b8e30a427b58458
+ 2f4d0558a11b2bc6
+
+VPERMILPD_VAR_256(reg)
+ before
+ 00a63906699e2f4d.4ce1fcbf7e092808.6e05070d458492d0.edbe12a2ed9eb7c3
+ ebe6c8191bcaca96.943cd14b23127395.a0a809c00f4a7ae2.a0fdf11394aa6f06
+ 4c58aefd542c3a50.6ba72efcd75db496.5b98a44e51c058ce.b4275b74fe33fde8
+ 7f4ae71eaf4fb825.acee8fc0b7f7a538.f921d523a7716740.0406cab144441f94
+ 6e67bcb684e98f37
+ after
+ 943cd14b23127395.ebe6c8191bcaca96.a0a809c00f4a7ae2.a0fdf11394aa6f06
+ ebe6c8191bcaca96.943cd14b23127395.a0a809c00f4a7ae2.a0fdf11394aa6f06
+ 4c58aefd542c3a50.6ba72efcd75db496.5b98a44e51c058ce.b4275b74fe33fde8
+ 7f4ae71eaf4fb825.acee8fc0b7f7a538.f921d523a7716740.0406cab144441f94
+ 6e67bcb684e98f37
+VPERMILPD_VAR_256(mem)
+ before
+ cd16ab70da2f0afc.e00770e8c8c083c1.35dc7082dfeb03a6.d88e96abaee9e4e3
+ fddf16c961214b10.cbda44c73d09d5d2.e13f4d2e6a458a0e.522de55201b50b64
+ da8e76af36cb0f9f.9b105f27a7b9eb01.8ce1a3b07412f599.c448bd843d60186f
+ 3fef480c743a12d4.aef5be75a45901fd.128fedf41a5d0176.8b2c1aaefe7646af
+ 0125f93ade84d2d0
+ after
+ cd16ab70da2f0afc.e00770e8c8c083c1.35dc7082dfeb03a6.d88e96abaee9e4e3
+ fddf16c961214b10.cbda44c73d09d5d2.e13f4d2e6a458a0e.522de55201b50b64
+ cbda44c73d09d5d2.cbda44c73d09d5d2.e13f4d2e6a458a0e.e13f4d2e6a458a0e
+ 3fef480c743a12d4.aef5be75a45901fd.128fedf41a5d0176.8b2c1aaefe7646af
+ 0125f93ade84d2d0
+
+VPERMILPD_VAR_256(reg)
+ before
+ 847f54967c15f880.0acd09ce377910db.5fd55b1bd0775270.4e15a7e677326acf
+ 6e85292c71b5f369.16f534df9c94c4e2.0afb3487c69e1b06.1e3f4e72a89eecd0
+ 1c85736a5cf10137.3e33452dbf98ec13.0bb54424225b986c.5dd95c84c8ac42a6
+ eac92fbbd6545b97.6053b9a3bb90419a.bd4d875d8138044e.e6ae4f08f468297d
+ 978ca2eb47df5d80
+ after
+ 6e85292c71b5f369.6e85292c71b5f369.1e3f4e72a89eecd0.0afb3487c69e1b06
+ 6e85292c71b5f369.16f534df9c94c4e2.0afb3487c69e1b06.1e3f4e72a89eecd0
+ 1c85736a5cf10137.3e33452dbf98ec13.0bb54424225b986c.5dd95c84c8ac42a6
+ eac92fbbd6545b97.6053b9a3bb90419a.bd4d875d8138044e.e6ae4f08f468297d
+ 978ca2eb47df5d80
+VPERMILPD_VAR_256(mem)
+ before
+ 4a3dd118de1c99dc.349e578b7e6a4035.56210a2dac8882a4.7e11faa07fc49d57
+ dd8e597ad42c9abd.5750e946edc0eabc.fe69b6b7af8d695d.a94b9758b7889d34
+ 2a4bb4ff46191c4e.ad2be058c1e196d9.33f6382ee0aab3f0.99485cf1c5124091
+ 0f4060924ff2dbbb.937a382d96598037.d0960c7c59eb1c8a.ac5344d746edc419
+ 3dba4b77d5a66379
+ after
+ 4a3dd118de1c99dc.349e578b7e6a4035.56210a2dac8882a4.7e11faa07fc49d57
+ dd8e597ad42c9abd.5750e946edc0eabc.fe69b6b7af8d695d.a94b9758b7889d34
+ 5750e946edc0eabc.5750e946edc0eabc.a94b9758b7889d34.fe69b6b7af8d695d
+ 0f4060924ff2dbbb.937a382d96598037.d0960c7c59eb1c8a.ac5344d746edc419
+ 3dba4b77d5a66379
+
+VPERMILPD_VAR_256(reg)
+ before
+ a7c76e3b0fc85a5c.6638d81f0bc09232.658bee3107b5e483.b213af8e395d5f57
+ 48c8a8908fdfe46f.0d0199929791fedc.7fa8fcd1b080fd69.b63a9c51990b3a82
+ 7a07f5e3f2783f5d.de651dd70f70dbe8.3d1f60772e460894.b6d74faf98026637
+ 9bd1519fd31ea5d3.b631e2da8d69e480.fb3a15911d9440b1.90b544964f4da2a4
+ 1ea2f7f1dcf8a8f3
+ after
+ 0d0199929791fedc.0d0199929791fedc.b63a9c51990b3a82.7fa8fcd1b080fd69
+ 48c8a8908fdfe46f.0d0199929791fedc.7fa8fcd1b080fd69.b63a9c51990b3a82
+ 7a07f5e3f2783f5d.de651dd70f70dbe8.3d1f60772e460894.b6d74faf98026637
+ 9bd1519fd31ea5d3.b631e2da8d69e480.fb3a15911d9440b1.90b544964f4da2a4
+ 1ea2f7f1dcf8a8f3
+VPERMILPD_VAR_256(mem)
+ before
+ 3d68e5ac5b0f3550.0571b82fcf5d527d.723163873089d6d1.1545188918f5e36b
+ c9d589b3e79f05e8.1535270181c28406.ec311ccb12db6d06.e78e63cdbbf62b6f
+ 9fb35ff29db3d4e7.2868998085d8751b.01fd8a904f6c654c.cd60f4c8a3225569
+ 99cfe35598585d78.98550a18782b6268.8d6027c4044779ce.2206c6e66b059c04
+ 44cdd593b02b3dec
+ after
+ 3d68e5ac5b0f3550.0571b82fcf5d527d.723163873089d6d1.1545188918f5e36b
+ c9d589b3e79f05e8.1535270181c28406.ec311ccb12db6d06.e78e63cdbbf62b6f
+ 1535270181c28406.1535270181c28406.e78e63cdbbf62b6f.ec311ccb12db6d06
+ 99cfe35598585d78.98550a18782b6268.8d6027c4044779ce.2206c6e66b059c04
+ 44cdd593b02b3dec
+
+VPSLLW_128(reg)
+ before
+ 8e021d3b0d2174cf.94f491c8f4995dc8.c2497635f6488798.6d2871524c7866b9
+ 5cee9b4a1f727d57.6cf0e637ce828f02.0390da439aba1f57.7b1fe325440ce839
+ 09e04a2d81ab9430.fd8d5d8f4220b153.b57630ae000d6753.9412f92b070eba79
+ f323264ed057f407.239972ba6b7e7de7.354776e3c5ce9b35.94cd304fb28a9aa6
+ 571b037d608c41eb
+ after
+ 8e021d3b0d2174cf.94f491c8f4995dc8.c2497635f6488798.6d2871524c7866b9
+ 5cee9b4a1f727d57.6cf0e637ce828f02.0390da439aba1f57.7b1fe325440ce839
+ 0000000000000000.0000000000000000.0000000000000000.000000000000000b
+ 0000000000000000.0000000000000000.80001800d000b800.f80028006000c800
+ 000000000000000b
+VPSLLW_128(mem)
+ before
+ b9caeea12e216e75.75022b1ba702d988.badea1a665a8afe9.df4ea84c8588f6ac
+ 96a46da83755db70.eacb56fea238815e.9e29673e4daa0586.0fd9c057dac7b562
+ ca77fc7c97324607.b0c8a1655f862636.ab463f6d3e9139e9.2132bb6f63181403
+ 310d180b6bc66867.21460abb777805bc.bd00a5215569083f.71a696ffb9064f3d
+ 5c814c757b1da1b9
+ after
+ b9caeea12e216e75.75022b1ba702d988.badea1a665a8afe9.df4ea84c8588f6ac
+ 96a46da83755db70.eacb56fea238815e.9e29673e4daa0586.0fd9c057dac7b562
+ ca77fc7c97324607.b0c8a1655f862636.ab463f6d3e9139e9.2132bb6f63181403
+ 0000000000000000.0000000000000000.52007c0054000c00.b200ae008e00c400
+ 5c814c757b1da1b9
+
+VPSLLW_128(reg)
+ before
+ 3c0fda3c42ea4726.a7333c3fcf1c00bb.9b918c6c88985a9b.b0251545ad3c2eb4
+ 6d9b3ac0adf87d2e.08b4e406de41c830.79f424e42e746080.607f0bc563186673
+ 4d736a6d55d47f7d.2f5e8c4ab4407df2.16bdcc8f03975516.a9db048e92096da9
+ 37e165afd90888c1.fafbb0f96e25db2c.cf3682d9a68e720a.67067b8a5719ff81
+ 75c9eca6cd56d828
+ after
+ 3c0fda3c42ea4726.a7333c3fcf1c00bb.9b918c6c88985a9b.b0251545ad3c2eb4
+ 6d9b3ac0adf87d2e.08b4e406de41c830.79f424e42e746080.607f0bc563186673
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000008
+ 0000000000000000.0000000000000000.f400e40074008000.7f00c50018007300
+ 0000000000000008
+VPSLLW_128(mem)
+ before
+ b1f3d3cf11ccb3c9.873227f3d222d5a3.4459cdfe27fd9d0a.01ad412eb1e4f607
+ f64fadef3e854d91.99b2aca3deaea1d2.e9425e45fcd380ba.066c05fbc0251bba
+ 20a8f5f4708f61ac.c9adf12d99372af8.c483dfba08b34066.3cc0cbaa70de1ecf
+ 0acb26c9c4f6ad46.736ff0fb9e49aac1.b3e8cc4968aa993a.fdf48da95c9a3bf1
+ a656496221e5aecd
+ after
+ b1f3d3cf11ccb3c9.873227f3d222d5a3.4459cdfe27fd9d0a.01ad412eb1e4f607
+ f64fadef3e854d91.99b2aca3deaea1d2.e9425e45fcd380ba.066c05fbc0251bba
+ 20a8f5f4708f61ac.c9adf12d99372af8.c483dfba08b34066.3cc0cbaa70de1ecf
+ 0000000000000000.0000000000000000.4000a00060004000.80006000a0004000
+ a656496221e5aecd
+
+VPSLLW_128(reg)
+ before
+ 9330fa435a4cb20e.9285bf5956c4eb89.f243a77b89705eda.913ca2df37c34663
+ 21d09db7a45a8461.929f39924107d8a4.a4771218f73981ef.394ddc66920b040d
+ aa802c2a9a9b5f72.e8e8125fa1cb2fc1.e4552b3e843050ab.89e5f6cc948c8f63
+ 8b8da508d99c81ec.6f2bc5ac931bae0d.0e2af058cadf07bb.5bd26cfb5a54a292
+ 8ddebbe1ff6ffac6
+ after
+ 9330fa435a4cb20e.9285bf5956c4eb89.f243a77b89705eda.913ca2df37c34663
+ 21d09db7a45a8461.929f39924107d8a4.a4771218f73981ef.394ddc66920b040d
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000006
+ 0000000000000000.0000000000000000.1dc08600ce407bc0.5340198082c00340
+ 0000000000000006
+VPSLLW_128(mem)
+ before
+ f9d65d69a0e8532a.204303bdfce8247c.0233ce6632030fb3.7d425cd568d4e2cb
+ 7d85d07e58cb69eb.c5ed42b59f0c84ce.7fcea9779b8f0ee0.8fe96b1ef89a1d86
+ f3b98f0e4324f734.d6d95f5c5f92df8d.c0c6d2cce9cc69bf.9e6a19a016bef399
+ 393c17047e00ba32.af51541fd8086f65.a2e8c65239c5da7d.081363c75fcba1af
+ 272e43006e4d6275
+ after
+ f9d65d69a0e8532a.204303bdfce8247c.0233ce6632030fb3.7d425cd568d4e2cb
+ 7d85d07e58cb69eb.c5ed42b59f0c84ce.7fcea9779b8f0ee0.8fe96b1ef89a1d86
+ f3b98f0e4324f734.d6d95f5c5f92df8d.c0c6d2cce9cc69bf.9e6a19a016bef399
+ 0000000000000000.0000000000000000.f9c02ee071e0dc00.fd2063c01340b0c0
+ 272e43006e4d6275
+
+VPSRLW_128(reg)
+ before
+ 5908b7b5e0d17396.29dce24c256a6e10.aca21f68a5fa7103.020000f3a6871e46
+ f8edbb5450e210bf.a0636ed3536fcefb.2918bba562f32113.bad9fc9d4d1cf045
+ 622949485a0c759c.7b9e36832419971f.82ff2540ac7fba40.a741373b49920ea7
+ f1075ffc9cdbded8.9459b649b57785a7.13a357a71e2a7937.a6022bb9b7f53298
+ 91ea5603b2501943
+ after
+ 5908b7b5e0d17396.29dce24c256a6e10.aca21f68a5fa7103.020000f3a6871e46
+ f8edbb5450e210bf.a0636ed3536fcefb.2918bba562f32113.bad9fc9d4d1cf045
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000003
+ 0000000000000000.0000000000000000.052317740c5e0422.175b1f9309a31e08
+ 0000000000000003
+VPSRLW_128(mem)
+ before
+ 45c3330556af7ed4.02d5f7deafdc8620.c85f6a12219254c0.38504f4555819aa4
+ 9e5a3eabc01f1e79.f2dd1059319baa20.f37ecfc98578bf95.4d510886ed0f5832
+ 797af4e10caab55b.1b6ca3d9bea28583.f2806059fc348353.adf37ed68061f18e
+ b0f1cf93555fffa9.daceadcbf17f55f5.9f3299b0a3d35c26.b682ada1ad029f63
+ c34a92530d7e9e5e
+ after
+ 45c3330556af7ed4.02d5f7deafdc8620.c85f6a12219254c0.38504f4555819aa4
+ 9e5a3eabc01f1e79.f2dd1059319baa20.f37ecfc98578bf95.4d510886ed0f5832
+ 797af4e10caab55b.1b6ca3d9bea28583.f2806059fc348353.adf37ed68061f18e
+ 0000000000000000.0000000000000000.0003000300020002.0001000000030001
+ c34a92530d7e9e5e
+
+VPSRLW_128(reg)
+ before
+ 309728593f612c2b.20894daeb747b78d.8c4f2b9966be5424.d760f6b995600539
+ 58b56b1ddc388375.a510e91c4f709a33.8b3b18b0bae9beb9.76d6f460efe73cb9
+ 99ef570d828ee0e9.1b5020cb39e564c9.34de707d888fd163.58600e91cc74bad1
+ 4e92e993cdf07e32.5e166ca690b3d078.e383306a6d39c7cc.59c9bf3849143eae
+ 55df864181d3827c
+ after
+ 309728593f612c2b.20894daeb747b78d.8c4f2b9966be5424.d760f6b995600539
+ 58b56b1ddc388375.a510e91c4f709a33.8b3b18b0bae9beb9.76d6f460efe73cb9
+ 0000000000000000.0000000000000000.0000000000000000.000000000000000c
+ 0000000000000000.0000000000000000.00080001000b000b.0007000f000e0003
+ 000000000000000c
+VPSRLW_128(mem)
+ before
+ 286cdc9990bb4466.d2eb1b1d58e99bfd.4a2e4b9870e59c6f.f47752e50575dda0
+ ae3d3f2a93da3d99.8344eb16c00571f5.bb63388ff68782d8.c306d459eace4f8d
+ c31e29e2a63c2c40.bbe954ea9fd13cc7.8d83af763da63edf.ac7cb131bbd0583c
+ 43db18abe4ebcb88.d828530594d83a1f.9c582d39624d8eb1.0b25e5db1108355c
+ 3c4d6dc28b012297
+ after
+ 286cdc9990bb4466.d2eb1b1d58e99bfd.4a2e4b9870e59c6f.f47752e50575dda0
+ ae3d3f2a93da3d99.8344eb16c00571f5.bb63388ff68782d8.c306d459eace4f8d
+ c31e29e2a63c2c40.bbe954ea9fd13cc7.8d83af763da63edf.ac7cb131bbd0583c
+ 0000000000000000.0000000000000000.0176007101ed0105.018601a801d5009f
+ 3c4d6dc28b012297
+
+VPSRLW_128(reg)
+ before
+ 9b3f4353c2475a99.0940887369f5d79d.344ce2d339a6a5a8.c3af2cc580882c7a
+ 844865f854671b10.f318f32552660caa.2da0ffc02ac7ba0f.e0552a04b464d566
+ 53b5ce1eddec9ea5.dc30d7adbb4825dc.1d71a53804c8b400.ce13a2e319ec44a0
+ 64d07b31f8632207.a054aff7bea9df5e.610bd0a76335d126.69b8114fcb2c3654
+ 8c0ff132e73167af
+ after
+ 9b3f4353c2475a99.0940887369f5d79d.344ce2d339a6a5a8.c3af2cc580882c7a
+ 844865f854671b10.f318f32552660caa.2da0ffc02ac7ba0f.e0552a04b464d566
+ 0000000000000000.0000000000000000.0000000000000000.000000000000000f
+ 0000000000000000.0000000000000000.0000000100000001.0001000000010001
+ 000000000000000f
+VPSRLW_128(mem)
+ before
+ 15e3c07a890693dd.13e5669e4257e2e0.1a50f7ef7a95f65d.56ba7d7ae1984b2d
+ df01f912ccb77509.bc428dd0565419dc.28f02b8108162604.56caa71b1d7f5ec3
+ c53618e5cc51cb60.ba32eb32d0e603a8.a500c899873a2a81.be8749f8b0764891
+ a54b99e1a6df4e0e.6b007c324d9adef0.6c4c4924100dbffd.eb3c627c39074346
+ 3736eb1351c08c8c
+ after
+ 15e3c07a890693dd.13e5669e4257e2e0.1a50f7ef7a95f65d.56ba7d7ae1984b2d
+ df01f912ccb77509.bc428dd0565419dc.28f02b8108162604.56caa71b1d7f5ec3
+ c53618e5cc51cb60.ba32eb32d0e603a8.a500c899873a2a81.be8749f8b0764891
+ 0000000000000000.0000000000000000.0002000200000002.0005000a00010005
+ 3736eb1351c08c8c
+
+VPSRAW_128(reg)
+ before
+ ffc2e128962d5f10.5a0ff9f1766dbd3e.2af93d3b69fbe45f.5b9f2a0cc299a1a7
+ 9f2a4129a4d9f77d.bf4db3025708d21c.526928b9be9652a2.4cc6e73fb6ed8ba9
+ 73ba068216509180.b2d043fe65bb4ad6.419c3b18ebf66465.1d8dfca70a123a2f
+ d7c02c9d891e69c4.0d6625d2bd93e196.52de71c48aa75553.a8c0e632da166a66
+ cb2b20cb4104d77a
+ after
+ ffc2e128962d5f10.5a0ff9f1766dbd3e.2af93d3b69fbe45f.5b9f2a0cc299a1a7
+ 9f2a4129a4d9f77d.bf4db3025708d21c.526928b9be9652a2.4cc6e73fb6ed8ba9
+ 0000000000000000.0000000000000000.0000000000000000.000000000000001a
+ 0000000000000000.0000000000000000.00000000ffff0000.0000ffffffffffff
+ 000000000000001a
+VPSRAW_128(mem)
+ before
+ 6099265e5be83c96.2787b0e798d0baf6.aed9d66a7a9b5288.e07ac72937366219
+ 45d874d745cf56e7.bf5a8cccdff1c1c2.6ff6d0b3b9df5bd9.49be37b48f2ec762
+ 54b287221bc4e198.fb86beb9fb0dbad3.2d899197956bb5b5.e7f4bfcf2d1bc0db
+ 6af4da2bf8d498d6.3757411888b1e1d6.c55e95042b4c1f47.18695ae8ae89882f
+ 36690469ad055c0b
+ after
+ 6099265e5be83c96.2787b0e798d0baf6.aed9d66a7a9b5288.e07ac72937366219
+ 45d874d745cf56e7.bf5a8cccdff1c1c2.6ff6d0b3b9df5bd9.49be37b48f2ec762
+ 54b287221bc4e198.fb86beb9fb0dbad3.2d899197956bb5b5.e7f4bfcf2d1bc0db
+ 0000000000000000.0000000000000000.000dfffafff7000b.00090006fff1fff8
+ 36690469ad055c0b
+
+VPSRAW_128(reg)
+ before
+ 9f40bac0c61b781b.646ae9dff80a38cd.cf19125721687176.114056e5968d53bc
+ ad3a76589755170a.1ce0302838727da8.1f182be162bfa760.eefc5126f23b0e3f
+ bda2369db9417785.6f222bf4d3182394.839f8a22e840bf3f.395f03b35d600cfd
+ 2cc5f5fbca6bd138.39fb572de609e5bd.57fc2a864e7af5c1.cc33e778f00b0922
+ 84457a61c945c0d9
+ after
+ 9f40bac0c61b781b.646ae9dff80a38cd.cf19125721687176.114056e5968d53bc
+ ad3a76589755170a.1ce0302838727da8.1f182be162bfa760.eefc5126f23b0e3f
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000019
+ 0000000000000000.0000000000000000.000000000000ffff.ffff0000ffff0000
+ 0000000000000019
+VPSRAW_128(mem)
+ before
+ 3d60365a041cee4f.54f0afde665d64ce.57392fc18c50804e.f779077931f6848f
+ d352994fbc9b4eaf.926d61b228a56af3.a3a62f9be2fab073.bf631e672c42a958
+ 22e61e2d0dcf9e27.428906e3accf2054.fa0fd3a603123059.0a0669bcdce9a0c6
+ 06e741de14c398e0.c18f9ade8f65c29d.384098d00ca4be2c.36aee6e4dc78a485
+ 9ea6904cc979f242
+ after
+ 3d60365a041cee4f.54f0afde665d64ce.57392fc18c50804e.f779077931f6848f
+ d352994fbc9b4eaf.926d61b228a56af3.a3a62f9be2fab073.bf631e672c42a958
+ 22e61e2d0dcf9e27.428906e3accf2054.fa0fd3a603123059.0a0669bcdce9a0c6
+ 0000000000000000.0000000000000000.e8e90be6f8beec1c.efd807990b10ea56
+ 9ea6904cc979f242
+
+VPSRAW_128(reg)
+ before
+ 9d3c635e3e7bc6a9.5b227e50ec83f808.69cd190d6cf58c7a.3904f80418bd1318
+ 91ba5c88d7075c65.fd63526eb21c7ccb.978d7fdee00bb996.d929712f4468ee48
+ d56d753531abef23.c87637248299de54.a71cc9bb8732869d.f4797e3babb109e8
+ c4a1acd0e8f2bc8f.9826ab5d7606dbd0.f5c7f212fbf62e3d.66c29c156aa42225
+ 0bce45aa9c4ef22b
+ after
+ 9d3c635e3e7bc6a9.5b227e50ec83f808.69cd190d6cf58c7a.3904f80418bd1318
+ 91ba5c88d7075c65.fd63526eb21c7ccb.978d7fdee00bb996.d929712f4468ee48
+ 0000000000000000.0000000000000000.0000000000000000.000000000000000b
+ 0000000000000000.0000000000000000.fff2000ffffcfff7.fffb000e0008fffd
+ 000000000000000b
+VPSRAW_128(mem)
+ before
+ bf6af7e45dbb3826.bca2fdc79769fe54.49412a07ad702f6b.ddd7f64edbe3ef1f
+ 5e612db1caf5ae40.17bc6285da9bf31f.b7912e0e40e19550.bb9bd1dbc08603f2
+ c38164fcfe0a11a8.333bd8764e14d59b.bee4355c4e68caac.eb5e7f25496aa760
+ cc9516b016061d88.6a6a5c078f61e175.3a04badef00e8aaa.c96bfd980f1b1615
+ b11046a0b0268dbe
+ after
+ bf6af7e45dbb3826.bca2fdc79769fe54.49412a07ad702f6b.ddd7f64edbe3ef1f
+ 5e612db1caf5ae40.17bc6285da9bf31f.b7912e0e40e19550.bb9bd1dbc08603f2
+ c38164fcfe0a11a8.333bd8764e14d59b.bee4355c4e68caac.eb5e7f25496aa760
+ 0000000000000000.0000000000000000.fffe00000001fffe.fffeffffffff0000
+ b11046a0b0268dbe
+
+VPSLLD_128(reg)
+ before
+ ff9756a9c8164807.5468c1bb2ef38d0d.1996e9a2380d5358.07bd398044e19177
+ 0f4d2920f278839c.37c7e00861df1e62.9d0b7cb4e5a466f1.00dd2e2f66ed9a3f
+ 3d7ebc6fcbd77928.507eef83cbd68cb4.50150faa33b357ec.032f15d5713d622d
+ e4750a04eebf6757.7d596a1989e2932f.8f00a0eebdc562f4.eb7e6b6082dda46e
+ 9397abbbb4d91e2d
+ after
+ ff9756a9c8164807.5468c1bb2ef38d0d.1996e9a2380d5358.07bd398044e19177
+ 0f4d2920f278839c.37c7e00861df1e62.9d0b7cb4e5a466f1.00dd2e2f66ed9a3f
+ 0000000000000000.0000000000000000.0000000000000000.000000000000000d
+ 0000000000000000.0000000000000000.6f9680008cde2000.a5c5e000b347e000
+ 000000000000000d
+VPSLLD_128(mem)
+ before
+ d94751d2233e8a97.62800f4af7bc89d6.9924ceb4b611eefe.b7172aee2066c2b6
+ 9858da90ec17a5d7.12e9c7ac835b1b51.7faa96416f6f5a4e.22a8a915f723b4dd
+ ab96c0e32a702a1a.4ffd2e982d275873.0db83eadcf07934a.2dfd19cedf877416
+ f0cf81b7fa56d78c.7708417992ad7de9.1e1b42e2f2e5541f.34637787731e3e0d
+ 9326bdab4f754d6d
+ after
+ d94751d2233e8a97.62800f4af7bc89d6.9924ceb4b611eefe.b7172aee2066c2b6
+ 9858da90ec17a5d7.12e9c7ac835b1b51.7faa96416f6f5a4e.22a8a915f723b4dd
+ ab96c0e32a702a1a.4ffd2e982d275873.0db83eadcf07934a.2dfd19cedf877416
+ 0000000000000000.0000000000000000.52c82000eb49c000.1522a000769ba000
+ 9326bdab4f754d6d
+
+VPSLLD_128(reg)
+ before
+ a792e9a61117dee3.41cd98f678d46658.e556fbbb4e78c65f.8d9d1ecef5155af8
+ caf3f7e552902d1a.7c5e828dbef693ab.f43358cafc146e80.380b4f5cf4a46102
+ 5994e1d2b06d75bf.7b4cb968ebc91cb1.02eb5413380eb2f9.f93050780a9d2569
+ b0c3a5dac739f47e.1b64bb741858bb95.6ac9ec009ff0ce75.adda9d0d540c6158
+ 31d3b20aedfed2fc
+ after
+ a792e9a61117dee3.41cd98f678d46658.e556fbbb4e78c65f.8d9d1ecef5155af8
+ caf3f7e552902d1a.7c5e828dbef693ab.f43358cafc146e80.380b4f5cf4a46102
+ 0000000000000000.0000000000000000.0000000000000000.000000000000001c
+ 0000000000000000.0000000000000000.a000000000000000.c000000020000000
+ 000000000000001c
+VPSLLD_128(mem)
+ before
+ 5fe90c58f17e3481.2bca3d6a3281e402.3972039c64b02d84.871a1bfecc49fea1
+ 14e626e47d994212.26f6a8ec8dcf81f8.af420dcbe8dc2da9.b72bdd7a5ca27d28
+ 2d977c9aac5ab9db.fd93dfce75b2090b.5b9f55efc3e87931.54452edfea8988b7
+ 84c88a679bcd550a.0ceddf7b85b3b6e8.175658f30ee0cb47.bbb70a98128a5bfa
+ 49cc6e13712f319c
+ after
+ 5fe90c58f17e3481.2bca3d6a3281e402.3972039c64b02d84.871a1bfecc49fea1
+ 14e626e47d994212.26f6a8ec8dcf81f8.af420dcbe8dc2da9.b72bdd7a5ca27d28
+ 2d977c9aac5ab9db.fd93dfce75b2090b.5b9f55efc3e87931.54452edfea8988b7
+ 0000000000000000.0000000000000000.b000000090000000.a000000080000000
+ 49cc6e13712f319c
+
+VPSLLD_128(reg)
+ before
+ 58cf55bba306474a.f644cc3566fed2c8.ae4fa55f5a60c43b.c03491c3e7d1e018
+ 450ebbfc439bd9b0.60d9bff227faeb44.41062ce68f4471af.32037c4b6ac673d0
+ 6dd39c42ee782379.9c51de88fdcd5da8.205f707cc1ebf7f1.49909577b2cc419a
+ 2a6bf5f93f2b6051.8779a5e50181e420.a7a46e8d8ce293ac.e2a65833dbee06a3
+ d713426c02387e16
+ after
+ 58cf55bba306474a.f644cc3566fed2c8.ae4fa55f5a60c43b.c03491c3e7d1e018
+ 450ebbfc439bd9b0.60d9bff227faeb44.41062ce68f4471af.32037c4b6ac673d0
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000016
+ 0000000000000000.0000000000000000.398000006bc00000.12c00000f4000000
+ 0000000000000016
+VPSLLD_128(mem)
+ before
+ 05a2ce0c43b76420.d922c08dd240cde5.fd1d90f452243bda.322220858ab4818d
+ 481e7801b97575ed.d644fb6b4441a6e1.da091ca109c120ff.1c2584d059eefc40
+ 7c54bc3580816da8.7e1ca1fd30bc26f1.fa09c3d844654cbe.c3f895db951b4170
+ 7d101796b5e4077e.2bf8afb1333d8bc0.39e803851f1b7e41.82e94f10d9c78cc9
+ b442afddc27f19f9
+ after
+ 05a2ce0c43b76420.d922c08dd240cde5.fd1d90f452243bda.322220858ab4818d
+ 481e7801b97575ed.d644fb6b4441a6e1.da091ca109c120ff.1c2584d059eefc40
+ 7c54bc3580816da8.7e1ca1fd30bc26f1.fa09c3d844654cbe.c3f895db951b4170
+ 0000000000000000.0000000000000000.42000000fe000000.a000000080000000
+ b442afddc27f19f9
+
+VPSRLD_128(reg)
+ before
+ b750b0adebce23aa.271e040f73ac019a.3a221ff2e84e0efa.73745794b5ef70b4
+ e55f4eebf040e788.5649ff8cd7e51529.07e7ef2bec7eee4d.84773cf223eee045
+ 9cbb85056e61a140.e65f84f9fc99ff57.ee931acadb566562.48be2c898423871d
+ 36b0516601be8c7e.b32a0f42ffd67d4f.4b729c3a4f64b0e8.9b15a547f49a246b
+ 5948221690607159
+ after
+ b750b0adebce23aa.271e040f73ac019a.3a221ff2e84e0efa.73745794b5ef70b4
+ e55f4eebf040e788.5649ff8cd7e51529.07e7ef2bec7eee4d.84773cf223eee045
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000019
+ 0000000000000000.0000000000000000.0000000300000076.0000004200000011
+ 0000000000000019
+VPSRLD_128(mem)
+ before
+ 5e231fe4747f2b13.1189af7a44e3e5ed.98781d53fba7493e.7acf72e7e6330b89
+ 8571199cba060ec6.879499add35ae83a.731329180d19204f.d7f8973d3c4fb2f1
+ acff8b2a81fed59e.f61b0d6c4bb1d111.1fc7af7d5037bdaf.be3707a8ec45e0cd
+ ae9af17ae3763dc6.b86b07214774db1d.78622b6fe10ddd89.8bd9be9593a0d2c9
+ 9a2ab86eccedc491
+ after
+ 5e231fe4747f2b13.1189af7a44e3e5ed.98781d53fba7493e.7acf72e7e6330b89
+ 8571199cba060ec6.879499add35ae83a.731329180d19204f.d7f8973d3c4fb2f1
+ acff8b2a81fed59e.f61b0d6c4bb1d111.1fc7af7d5037bdaf.be3707a8ec45e0cd
+ 0000000000000000.0000000000000000.000039890000068c.00006bfc00001e27
+ 9a2ab86eccedc491
+
+VPSRLD_128(reg)
+ before
+ 4676f2a134b6f1cf.670cc778fc77026b.2ad08139642d430a.5aaf1ad8dba83c0b
+ ed096698668a9632.b2218910e90fe0b9.a99679213d6a4586.a079f7a65a13965e
+ ea2e12c1fef2ef64.6da7b42ec54992db.8f08ea446fb71c3a.288d3ec47b5ba6b1
+ 9932f287997c3712.7269c2bfad31d5fe.3974d00d959e05d5.cdb86b1e5a8a292e
+ 6ac4faa012aedb01
+ after
+ 4676f2a134b6f1cf.670cc778fc77026b.2ad08139642d430a.5aaf1ad8dba83c0b
+ ed096698668a9632.b2218910e90fe0b9.a99679213d6a4586.a079f7a65a13965e
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000001
+ 0000000000000000.0000000000000000.54cb3c901eb522c3.503cfbd32d09cb2f
+ 0000000000000001
+VPSRLD_128(mem)
+ before
+ dd7d6836bfd37857.55620056d2b3ace7.9f3231adbcd4654d.032427ea4cad3c01
+ 00b130cc7e04bb5c.7c083a9946248890.cfcf7de60f3dfdf5.4a65ec462f70fd6b
+ b12ace4e6a4d613b.69719bbf915a07b9.dd0c2055c1785a21.6883198ddb7183be
+ cab6bea8a0ba2621.77e81f314de1670d.a7b598e5ee9238ff.bacaac2beb3e0ba7
+ 9c86a18cfc63d1d1
+ after
+ dd7d6836bfd37857.55620056d2b3ace7.9f3231adbcd4654d.032427ea4cad3c01
+ 00b130cc7e04bb5c.7c083a9946248890.cfcf7de60f3dfdf5.4a65ec462f70fd6b
+ b12ace4e6a4d613b.69719bbf915a07b9.dd0c2055c1785a21.6883198ddb7183be
+ 0000000000000000.0000000000000000.000067e70000079e.00002532000017b8
+ 9c86a18cfc63d1d1
+
+VPSRLD_128(reg)
+ before
+ 6a02f21da96b11e9.291f7cc73b58c53a.04bbc25c1945e238.07966084b39653b8
+ 808b9d488ee2069b.a83285955832fbb1.6a3481ac8f13b5e8.da7af41d2c91667a
+ 3a6e9d7b4854ed92.24bb5400125484b2.07a1568e4bd71bc7.fd2fd09c748d2e71
+ f4f5ee20724e017a.7a8665f286cb1c6a.354c3f6ce91b5281.4a7f71eda79967c9
+ 9f3751fce2beccad
+ after
+ 6a02f21da96b11e9.291f7cc73b58c53a.04bbc25c1945e238.07966084b39653b8
+ 808b9d488ee2069b.a83285955832fbb1.6a3481ac8f13b5e8.da7af41d2c91667a
+ 0000000000000000.0000000000000000.0000000000000000.000000000000000d
+ 0000000000000000.0000000000000000.000351a40004789d.0006d3d70001648b
+ 000000000000000d
+VPSRLD_128(mem)
+ before
+ d623eeb6410a1a49.0a6d8ca5a95b8001.845e3559cfa27e05.528237b4076d94c3
+ cc0fc405de880dcb.d82173758907a4d1.1f103e200ae667af.b88f3bd13e591d39
+ 5dc74dd7d845615d.ba5fa0fbaddfaa96.2869fe3352a29393.c5be452e2c692b8e
+ 66160716494bd12b.0c710ea5b16ecdfe.7933f07ec4e2bedd.d35d53396d2bf86f
+ 3fb6605d9c2ac187
+ after
+ d623eeb6410a1a49.0a6d8ca5a95b8001.845e3559cfa27e05.528237b4076d94c3
+ cc0fc405de880dcb.d82173758907a4d1.1f103e200ae667af.b88f3bd13e591d39
+ 5dc74dd7d845615d.ba5fa0fbaddfaa96.2869fe3352a29393.c5be452e2c692b8e
+ 0000000000000000.0000000000000000.003e207c0015cccf.01711e77007cb23a
+ 3fb6605d9c2ac187
+
+VPSRAD_128(reg)
+ before
+ 6616690655f3c184.c1ca6db04da91a62.29a5b9de32414ab2.ef3b90ed7bb3a3bb
+ a2c968a13511360f.4badfb900168f82e.6f459e13cbe35d61.664c5b6c931fff57
+ 501b5b98d8105ad6.e08c2da2809626ba.399eb7ae19e042b5.ba34cbe829358ddd
+ cc583d58d97d6a85.5c337fd2e63e6233.e3fb021cb7c4345a.c7be5e4b58fe0b7a
+ 69b58f833d88335a
+ after
+ 6616690655f3c184.c1ca6db04da91a62.29a5b9de32414ab2.ef3b90ed7bb3a3bb
+ a2c968a13511360f.4badfb900168f82e.6f459e13cbe35d61.664c5b6c931fff57
+ 0000000000000000.0000000000000000.0000000000000000.000000000000001a
+ 0000000000000000.0000000000000000.0000001bfffffff2.00000019ffffffe4
+ 000000000000001a
+VPSRAD_128(mem)
+ before
+ 7de6db7af4dec1a8.72cb0a4ed4e3a1c8.9b6d6e0c516d65c4.c8aa7aca411c71fd
+ dd1dbc1e980d7391.9fc2bee466cf3c4a.7908753cda2eee9a.46f51c225574324a
+ 6526b05a45200340.ad8756882acb77b7.d2ce104e9f8db7e1.b82ae2928c56b6ec
+ f3cc321a18232ee2.f967cda5bd658ebc.828dbc2ebc977ec4.7993ca8484503790
+ e77dcf66d9edf2e2
+ after
+ 7de6db7af4dec1a8.72cb0a4ed4e3a1c8.9b6d6e0c516d65c4.c8aa7aca411c71fd
+ dd1dbc1e980d7391.9fc2bee466cf3c4a.7908753cda2eee9a.46f51c225574324a
+ 6526b05a45200340.ad8756882acb77b7.d2ce104e9f8db7e1.b82ae2928c56b6ec
+ 0000000000000000.0000000000000000.1e421d4ff68bbba6.11bd4708155d0c92
+ e77dcf66d9edf2e2
+
+VPSRAD_128(reg)
+ before
+ 5c34eda326ba238d.62ddbe4a2c23b0a2.dfae1fa6ba29bc05.650ff3c94c57fc70
+ 360420a70742053d.8e23d1d69e2b44ae.bba848f9bea23e3e.572133096bd9f010
+ cf3865de1911d6a0.536ce5aa8947a72f.e9a04509645c5012.348ef7dc362a14d1
+ 851db7b4f8b4cf60.8d8278b20a849554.c5e4104349e32e2d.d824bb2dc95525de
+ 1eaefce83f66df65
+ after
+ 5c34eda326ba238d.62ddbe4a2c23b0a2.dfae1fa6ba29bc05.650ff3c94c57fc70
+ 360420a70742053d.8e23d1d69e2b44ae.bba848f9bea23e3e.572133096bd9f010
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000005
+ 0000000000000000.0000000000000000.fddd4247fdf511f1.02b90998035ecf80
+ 0000000000000005
+VPSRAD_128(mem)
+ before
+ e4f735f8b46afd8f.b20012963eb62f29.183105da3cedca47.abbea71108c4133c
+ 05cce14b456c3c8b.b32b72ee8aa330a8.cf47090f3b8e0134.f67b05e03e8a3ceb
+ 5df97fcd0d785883.e5ebd32976080f89.908ffe3c2474f748.0467271c86c2e4e6
+ c74a8868299b0da3.a28b32b49e700877.36d4624c13aa67af.30ce07327cf649d7
+ d6fca38dbdb5a56d
+ after
+ e4f735f8b46afd8f.b20012963eb62f29.183105da3cedca47.abbea71108c4133c
+ 05cce14b456c3c8b.b32b72ee8aa330a8.cf47090f3b8e0134.f67b05e03e8a3ceb
+ 5df97fcd0d785883.e5ebd32976080f89.908ffe3c2474f748.0467271c86c2e4e6
+ 0000000000000000.0000000000000000.fffe7a380001dc70.ffffb3d80001f451
+ d6fca38dbdb5a56d
+
+VPSRAD_128(reg)
+ before
+ 523cf698e5883552.218b7a09b4e01618.47598af99f67571f.9ce4b02d233c0f94
+ ffdcfcc18ffd3433.4687cf9ccb53300e.319fd766147a372c.a08964ca7037a924
+ 3b26b273579fdfbb.110b050e890117b0.baab15669a34e54b.1d90fb0f17a6f28b
+ 6167121adafb7297.60e498490bf5862b.3fc74165cc219c28.eec4efe83495a5f4
+ f1f3be41e211808c
+ after
+ 523cf698e5883552.218b7a09b4e01618.47598af99f67571f.9ce4b02d233c0f94
+ ffdcfcc18ffd3433.4687cf9ccb53300e.319fd766147a372c.a08964ca7037a924
+ 0000000000000000.0000000000000000.0000000000000000.000000000000000c
+ 0000000000000000.0000000000000000.000319fd000147a3.fffa08960007037a
+ 000000000000000c
+VPSRAD_128(mem)
+ before
+ 00e7e3063d253d7e.cceb1a22b49c2973.0ddc023b6c3b3aab.1c4056cf46ce9a6e
+ f96eda2362de98f7.dafec5f77f0e40fa.f6c0c1cfc8e0ef5b.ad625010a5c619ca
+ b65220856c474f22.e6eb1005daddf2d8.f55b50f13cef6167.4e782b94859555e7
+ 15603016786c1c2c.4b00f5b95e967cbb.e87b2b8de4754bfd.5bd0e3c881c88c72
+ 30b4751636eaf817
+ after
+ 00e7e3063d253d7e.cceb1a22b49c2973.0ddc023b6c3b3aab.1c4056cf46ce9a6e
+ f96eda2362de98f7.dafec5f77f0e40fa.f6c0c1cfc8e0ef5b.ad625010a5c619ca
+ b65220856c474f22.e6eb1005daddf2d8.f55b50f13cef6167.4e782b94859555e7
+ 0000000000000000.0000000000000000.ffffffedffffff91.ffffff5affffff4b
+ 30b4751636eaf817
+
+VPSLLQ_128(reg)
+ before
+ 2971dceb3e87d681.f06485c4a159bc41.6787727daac5194d.a9eace8fdb7d6a47
+ a25314b4382c625d.242a9e79041bea8c.94cd82bf57f4063a.1576b6e33d137a71
+ f7a619dcbe64d756.8e7df423bcbd643a.301e21e904b17f2f.09e95d75274336a8
+ 84b6e8ce6cbc7219.082b05ade64ce477.95c64b694a87c0d8.5f104131b51a5b18
+ f4b7dd0402a3a5ec
+ after
+ 2971dceb3e87d681.f06485c4a159bc41.6787727daac5194d.a9eace8fdb7d6a47
+ a25314b4382c625d.242a9e79041bea8c.94cd82bf57f4063a.1576b6e33d137a71
+ 0000000000000000.0000000000000000.0000000000000000.000000000000002c
+ 0000000000000000.0000000000000000.4063a00000000000.37a7100000000000
+ 000000000000002c
+VPSLLQ_128(mem)
+ before
+ a4a9aed82aebd051.a5cf7bf8dfbf6f52.6ffe4b039dd2276e.2010fdaac70305e0
+ 4cb42f9b4afd9772.b63cd0c5b2f909ac.9fc34411fd5ee84b.2e4a321817b089f4
+ c6a2db387de5b77c.134ae2a182f67ed4.75466cc323f9e43b.19bee61fd51a89bf
+ ef40309ae0afec9b.1745aef8ea430875.cb533d052bb1d76a.3eb9152b9dce40ee
+ fa88bca80c57ec2d
+ after
+ a4a9aed82aebd051.a5cf7bf8dfbf6f52.6ffe4b039dd2276e.2010fdaac70305e0
+ 4cb42f9b4afd9772.b63cd0c5b2f909ac.9fc34411fd5ee84b.2e4a321817b089f4
+ c6a2db387de5b77c.134ae2a182f67ed4.75466cc323f9e43b.19bee61fd51a89bf
+ 0000000000000000.0000000000000000.dd09600000000000.113e800000000000
+ fa88bca80c57ec2d
+
+VPSLLQ_128(reg)
+ before
+ a774d502be41c727.a35aaaaf8e68f1fa.20792e37876be33c.7eb535c430917d04
+ a2cc5ea64e190d89.bebcc362a41b84c6.893260c8f4fb4dd5.6a3acfea4ea69134
+ 47db53fe586afcff.1c32f99f3dd55e2a.aebc3f18ce7e80eb.6bac8765a2fbd026
+ f2ecae7879c1ce34.9988c75275a13e53.ea62c894b080b92a.5dd8d91f479cf607
+ 1c8a42065a96be03
+ after
+ a774d502be41c727.a35aaaaf8e68f1fa.20792e37876be33c.7eb535c430917d04
+ a2cc5ea64e190d89.bebcc362a41b84c6.893260c8f4fb4dd5.6a3acfea4ea69134
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000003
+ 0000000000000000.0000000000000000.49930647a7da6ea8.51d67f52753489a0
+ 0000000000000003
+VPSLLQ_128(mem)
+ before
+ 848e3d05f7f4e646.ff4c6d7e4ca8c0d4.1189a9686a8bde6d.9b72f5a6378d3340
+ 71b0460838c228fb.ca478a7e6ead0e8c.60021bcb35a0fca3.1b36c4bcfe322cd7
+ bfbbd9fb3c0c404e.b02903e37a5cf308.62bf9a68f4eb5122.c8fb3041a1fbde9b
+ 4a7c72ca1cdfec6c.0b3ed4190d3facf4.f38ca12cc3789c15.fd0d35a1bd728539
+ 15b7cf48ee255f5d
+ after
+ 848e3d05f7f4e646.ff4c6d7e4ca8c0d4.1189a9686a8bde6d.9b72f5a6378d3340
+ 71b0460838c228fb.ca478a7e6ead0e8c.60021bcb35a0fca3.1b36c4bcfe322cd7
+ bfbbd9fb3c0c404e.b02903e37a5cf308.62bf9a68f4eb5122.c8fb3041a1fbde9b
+ 0000000000000000.0000000000000000.66b41f9460000000.9fc6459ae0000000
+ 15b7cf48ee255f5d
+
+VPSLLQ_128(reg)
+ before
+ 6d47fba2cf9fa6b2.eec08e61f747e681.38d2f78cc2e575fb.ef35ac02bd5497a9
+ 6207b41bfc6d97e5.8651a8ace64eebb8.92306aa836d789c9.328637d5fe8aff0a
+ 4e44f61f121a6da2.f0fc3c980702b63e.77a528d904a3250b.974abf93a3269063
+ 8f4bbd1bac326694.078cc60f766f043f.427e2d8bc9d4856d.fc4ebe27c73505e1
+ 3c5fb27d87c21baf
+ after
+ 6d47fba2cf9fa6b2.eec08e61f747e681.38d2f78cc2e575fb.ef35ac02bd5497a9
+ 6207b41bfc6d97e5.8651a8ace64eebb8.92306aa836d789c9.328637d5fe8aff0a
+ 0000000000000000.0000000000000000.0000000000000000.000000000000002f
+ 0000000000000000.0000000000000000.c4e4800000000000.7f85000000000000
+ 000000000000002f
+VPSLLQ_128(mem)
+ before
+ 33471681fed98efa.7f6505796742bc67.a7cfc3ff4e9f91e6.4f05752b20f6e59a
+ bcd2671f49871aed.7be1cba7ded5abc8.ab8fad52aca01960.fa86fd23a596803f
+ b5ce1f4483d77ab5.e00a0a0fae777163.f19a02f6ab7e57d8.9f4fc0e1f53f9408
+ f906bcdac9d56b7e.082bbe1f72b548e4.54ba3dd66744087b.99abbad0ac7e5aa0
+ 46e5e75b65de11b4
+ after
+ 33471681fed98efa.7f6505796742bc67.a7cfc3ff4e9f91e6.4f05752b20f6e59a
+ bcd2671f49871aed.7be1cba7ded5abc8.ab8fad52aca01960.fa86fd23a596803f
+ b5ce1f4483d77ab5.e00a0a0fae777163.f19a02f6ab7e57d8.9f4fc0e1f53f9408
+ 0000000000000000.0000000000000000.9600000000000000.03f0000000000000
+ 46e5e75b65de11b4
+
+VPSRLQ_128(reg)
+ before
+ 014a43f0bcebf3ef.6345b9ce368ea973.5092e342c71a6df6.afbcdbdefdfee874
+ 2626cbfa4e323dfe.d158920de70defc1.148976e448321b45.e06b57fa88b8b3f1
+ 10c57ae5b63d2b8d.1d0bc482f75ffa94.b05d7271928a907f.c1952c16257f241b
+ 1d734c1d919bf847.252aca18838e8617.8159d35540ad064d.3005d81ef05ef821
+ 0786d7fe0361eb2c
+ after
+ 014a43f0bcebf3ef.6345b9ce368ea973.5092e342c71a6df6.afbcdbdefdfee874
+ 2626cbfa4e323dfe.d158920de70defc1.148976e448321b45.e06b57fa88b8b3f1
+ 0000000000000000.0000000000000000.0000000000000000.000000000000002c
+ 0000000000000000.0000000000000000.0000000000014897.00000000000e06b5
+ 000000000000002c
+VPSRLQ_128(mem)
+ before
+ 24e5a3a37d95b86b.a77c3d0f7bd5e1d8.c3811fbda6a84f77.e1cb95fcee28ba5e
+ 61eebaf777051c08.0c2b4a250e7922ee.d5dc425c7cb910df.2dfeb4d23985e75c
+ 9c6d97e810bed330.a6cd6dcce912f733.3506ace122cc867c.c13d2d44bd52caf3
+ af2eb66061cb990e.d3aea471a52d9b53.c0ccda38b4ed6d79.f9d5fbbc151b9fd1
+ 31121aa8dd6ba29f
+ after
+ 24e5a3a37d95b86b.a77c3d0f7bd5e1d8.c3811fbda6a84f77.e1cb95fcee28ba5e
+ 61eebaf777051c08.0c2b4a250e7922ee.d5dc425c7cb910df.2dfeb4d23985e75c
+ 9c6d97e810bed330.a6cd6dcce912f733.3506ace122cc867c.c13d2d44bd52caf3
+ 0000000000000000.0000000000000000.00000001abb884b8.000000005bfd69a4
+ 31121aa8dd6ba29f
+
+VPSRLQ_128(reg)
+ before
+ c5408673b2ce0e0c.77fc934d893829cf.ed1aeb7fe0554bfb.53fa494e4d288003
+ 10ab3c8830d020c2.d0a5ab9aa111409e.525d3c61361643d7.c85c740d098a7c46
+ 709e3655f1fe146d.97f37933c7639aa8.5cc3958542fdbe92.fcbed762051e1d6d
+ 4067724594e326ba.a6b379041739f319.6997f156a195f9d9.cbecef3a5cf11fa5
+ 12b1367f2b0e3d19
+ after
+ c5408673b2ce0e0c.77fc934d893829cf.ed1aeb7fe0554bfb.53fa494e4d288003
+ 10ab3c8830d020c2.d0a5ab9aa111409e.525d3c61361643d7.c85c740d098a7c46
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000019
+ 0000000000000000.0000000000000000.000000292e9e309b.000000642e3a0684
+ 0000000000000019
+VPSRLQ_128(mem)
+ before
+ abdb2a1f8d8134f6.dc50ecc4b30c9155.dab127f9aca0061c.d3274c40ee6a3057
+ 733446059f57c068.a0a69e3eea0392ea.0fb9ffffa2a390de.f7bda2afc5099fb9
+ 4689071d7c9a9c9a.e8b5861fd6576524.21967e00164e4c8a.31a6ef0fc3fd81ab
+ 00a6e753415986b9.0fc99ed4129145af.ed161fe924adf84d.de2e30cc84d213d8
+ 58a06053a31591ed
+ after
+ abdb2a1f8d8134f6.dc50ecc4b30c9155.dab127f9aca0061c.d3274c40ee6a3057
+ 733446059f57c068.a0a69e3eea0392ea.0fb9ffffa2a390de.f7bda2afc5099fb9
+ 4689071d7c9a9c9a.e8b5861fd6576524.21967e00164e4c8a.31a6ef0fc3fd81ab
+ 0000000000000000.0000000000000000.0000000000007dcf.000000000007bded
+ 58a06053a31591ed
+
+VPSRLQ_128(reg)
+ before
+ fc4a7b0ebc513796.7d566493099d37f0.732ee4c73a3f6f38.4d035ea7e7cd4e53
+ 26767e6b6c12407e.9967f9c9f1746e6c.6f2f5466ebec1f6b.1e2ab8247bba0ac7
+ 327263d54ee5e951.30a322e114e9e559.5e19e81bc12590f3.3c57a74efd7eead6
+ 7c8828b7ff556dbc.1ed85bc88e095ae2.9e399e545775007d.8356a9108827a8ab
+ cff3395639c00173
+ after
+ fc4a7b0ebc513796.7d566493099d37f0.732ee4c73a3f6f38.4d035ea7e7cd4e53
+ 26767e6b6c12407e.9967f9c9f1746e6c.6f2f5466ebec1f6b.1e2ab8247bba0ac7
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000033
+ 0000000000000000.0000000000000000.0000000000000de5.00000000000003c5
+ 0000000000000033
+VPSRLQ_128(mem)
+ before
+ fbf9d30c2b56b15a.6005c87f1aef0a6b.3fd021687cdf8634.89d9717c4a68a9b5
+ e535f41e7bf4738b.3a343f983c3dfa0a.6f58efaffa77287a.7d455dff358bc746
+ 6874167844a60433.66638a6e00ce7a44.8a3c418723defae1.d4cb5e49b46998dc
+ 6080b706a379207d.40dca36d032bc5c5.6c4793de131fb995.ecb671c6648e5625
+ 1f5191e2e0863ecb
+ after
+ fbf9d30c2b56b15a.6005c87f1aef0a6b.3fd021687cdf8634.89d9717c4a68a9b5
+ e535f41e7bf4738b.3a343f983c3dfa0a.6f58efaffa77287a.7d455dff358bc746
+ 6874167844a60433.66638a6e00ce7a44.8a3c418723defae1.d4cb5e49b46998dc
+ 0000000000000000.0000000000000000.000deb1df5ff4ee5.000fa8abbfe6b178
+ 1f5191e2e0863ecb
+
+VROUNDPS_128_0x0(reg)
+ before
+ cbe9ba09c5de8b7a.a92652b5b3788396.24ed8801e0e2183a.f047629fe74621c1
+ 4acae8a8af227bdf.1f31636f91afe8aa.6ee03597347eaf4f.f40628b6ba60ed92
+ f940172938dc48a6.9d6f6722582b0ce4.7a02a4999a8bc6af.5351630fa978da33
+ 359744faff9a2f7a.01aad9b824f7aa70.a49fd275ae969807.e9f48e96d09aa4d1
+ 91bb263749d30798
+ after
+ cbe9ba09c5de8b7a.a92652b5b3788396.24ed8801e0e2183a.f047629fe74621c1
+ 4acae8a8af227bdf.1f31636f91afe8aa.6ee03597347eaf4f.f40628b6ba60ed92
+ f940172938dc48a6.9d6f6722582b0ce4.7a02a4999a8bc6af.5351630fa978da33
+ 0000000000000000.0000000000000000.6ee0359700000000.f40628b680000000
+ 91bb263749d30798
+VROUNDPS_128_0x0(mem)
+ before
+ 2972a5de332ebeb3.581b6a859ee86b08.26b0351f1220807c.4802bc950d2a6203
+ 8ce48978a7b7864e.bf178538b15039fb.e74bf7423eb04832.c1795d6753d4604e
+ 95df4defc37b1a97.c6d8917ed460d500.22489b0dc3b5bfbe.6d4eb1561b1fce95
+ 222d6d31a38538b8.caaa8bc3a5a47bc3.b1729e6cbd3ba04d.a7cfb5ce0197e783
+ ca46643aa2c8e8c5
+ after
+ 2972a5de332ebeb3.581b6a859ee86b08.26b0351f1220807c.4802bc950d2a6203
+ 8ce48978a7b7864e.bf178538b15039fb.e74bf7423eb04832.c1795d6753d4604e
+ 95df4defc37b1a97.c6d8917ed460d500.22489b0dc3b5bfbe.6d4eb1561b1fce95
+ 0000000000000000.0000000000000000.0000000000000000.4802bc8000000000
+ ca46643aa2c8e8c5
+
+VROUNDPS_128_0x0(reg)
+ before
+ 34ffb909993f0d07.0d9b662862e29add.25d96e73bda666ef.72977b4b494ca90b
+ 4048b3a4838891f4.34f5b2c21d9dfd33.34b136fabaf5d331.3f82ae9682f79423
+ 496c4b78fc2db138.7106cfeaefc21ce6.537edfc4381afe34.f6feb33985451dc2
+ adb67ef19ebca981.a29c388cf45db521.de8b653dd2a322a5.71d807216d440214
+ 8edc243857fffd44
+ after
+ 34ffb909993f0d07.0d9b662862e29add.25d96e73bda666ef.72977b4b494ca90b
+ 4048b3a4838891f4.34f5b2c21d9dfd33.34b136fabaf5d331.3f82ae9682f79423
+ 496c4b78fc2db138.7106cfeaefc21ce6.537edfc4381afe34.f6feb33985451dc2
+ 0000000000000000.0000000000000000.0000000080000000.3f80000080000000
+ 8edc243857fffd44
+VROUNDPS_128_0x0(mem)
+ before
+ 27d6886c5e82cb7e.c673497c08c0b579.a1826a94497b8211.3126c5d2241b7d30
+ 1992aea89fda27f0.f2f0a783d3c610cc.4b83dfee0a2740e1.a899faedcb0e4980
+ 41db13d73512cfc3.8b7794749d59f727.7d6c1586526eaabe.9f3100fc6309c242
+ 797f31e73d377d26.ef540dba0205a636.110987493d5a7dd4.723ad36987972621
+ 7d0070a2d345afca
+ after
+ 27d6886c5e82cb7e.c673497c08c0b579.a1826a94497b8211.3126c5d2241b7d30
+ 1992aea89fda27f0.f2f0a783d3c610cc.4b83dfee0a2740e1.a899faedcb0e4980
+ 41db13d73512cfc3.8b7794749d59f727.7d6c1586526eaabe.9f3100fc6309c242
+ 0000000000000000.0000000000000000.80000000497b8210.0000000000000000
+ 7d0070a2d345afca
+
+VROUNDPS_128_0x0(reg)
+ before
+ 1cced212e49d99e9.9e4886c3d254ee43.78d50cc09d5758a4.e426b121e8fa754e
+ aaf2f525552e2229.8d038d571175dd47.83458ff40bda4a1e.d38e10fb6e574e59
+ 85b6d547c3818437.207cc28f15a6075d.6def91c1e71ab84f.b80f1ec4ec7fc321
+ 08676ee4c924fcbe.347fa258faf428b2.90200f93cda4dee4.707359677d7d91d1
+ d7873cd03e5e7495
+ after
+ 1cced212e49d99e9.9e4886c3d254ee43.78d50cc09d5758a4.e426b121e8fa754e
+ aaf2f525552e2229.8d038d571175dd47.83458ff40bda4a1e.d38e10fb6e574e59
+ 85b6d547c3818437.207cc28f15a6075d.6def91c1e71ab84f.b80f1ec4ec7fc321
+ 0000000000000000.0000000000000000.8000000000000000.d38e10fb6e574e59
+ d7873cd03e5e7495
+VROUNDPS_128_0x0(mem)
+ before
+ c91743ea4a2d279a.8f51bd6804a2c66b.a5d7a89cdd6bfc71.492403d75a03f789
+ 22efeba3bef6670c.76c0bd400f881de9.4f524f48da153ec7.f4476bf72ac340e9
+ bedbafe6b5c5f017.18ff6ad687603ee6.0eba16490b00abe0.eed54260d871f5b1
+ 79a70ba04ca77ee6.d35cc09807b9650b.bedc76898f37ffe7.9119847f0098518d
+ 3a612dbe3fc49128
+ after
+ c91743ea4a2d279a.8f51bd6804a2c66b.a5d7a89cdd6bfc71.492403d75a03f789
+ 22efeba3bef6670c.76c0bd400f881de9.4f524f48da153ec7.f4476bf72ac340e9
+ bedbafe6b5c5f017.18ff6ad687603ee6.0eba16490b00abe0.eed54260d871f5b1
+ 0000000000000000.0000000000000000.80000000dd6bfc71.492403d05a03f789
+ 3a612dbe3fc49128
+
+VROUNDPS_128_0x1(reg)
+ before
+ 45f73a8b3082f12e.2f1e7bbb9ea8cca5.0121bbf02b1cce07.3b84ecf680c7f509
+ 0e28a651705dad4c.bc0d7b24c7d29781.009b584c9117b484.617ef57bfabb4b71
+ f1406d7b9ae2002e.fc4088c8e4339ba6.2b169217d235542e.0c960c041a1fbb4c
+ 4a8b8b774b9b2780.cb831d9111d69440.ddde65bd8c03eab2.1897ad7dfb0001c6
+ 614e55d2ba69db0a
+ after
+ 45f73a8b3082f12e.2f1e7bbb9ea8cca5.0121bbf02b1cce07.3b84ecf680c7f509
+ 0e28a651705dad4c.bc0d7b24c7d29781.009b584c9117b484.617ef57bfabb4b71
+ f1406d7b9ae2002e.fc4088c8e4339ba6.2b169217d235542e.0c960c041a1fbb4c
+ 0000000000000000.0000000000000000.00000000bf800000.617ef57bfabb4b71
+ 614e55d2ba69db0a
+VROUNDPS_128_0x1(mem)
+ before
+ c3887fef72660344.7554fcb01e165eed.05a2b66d69c83d7a.743fcdaa5b0cb1bc
+ 1a0fa6c0400435a2.cee9bd93b0dfe121.8669cf4608145380.4a84c74ad9dce6f7
+ 41b049323f4e2f4e.b194c98a9c81ebc9.2aa3e40a0bc6927f.bdfb4e09a500c510
+ 1636e12f8b50ab74.7aa21c027f88b991.cc1d72a48eebb5a3.27ee5e5359038ab2
+ e5aaf3949171708b
+ after
+ c3887fef72660344.7554fcb01e165eed.05a2b66d69c83d7a.743fcdaa5b0cb1bc
+ 1a0fa6c0400435a2.cee9bd93b0dfe121.8669cf4608145380.4a84c74ad9dce6f7
+ 41b049323f4e2f4e.b194c98a9c81ebc9.2aa3e40a0bc6927f.bdfb4e09a500c510
+ 0000000000000000.0000000000000000.0000000069c83d7a.743fcdaa5b0cb1bc
+ e5aaf3949171708b
+
+VROUNDPS_128_0x1(reg)
+ before
+ 547b0a39ead7b444.746feba541176641.855fb267f4808724.4aa4f400ab8e7917
+ cead9dacffc0928b.3625e47e7dae1ce1.2e17882697f6902f.7f02e60a81bb9a08
+ b08baa5b6db8450c.3a2647a85a21887f.d01699aa0575115e.4603c5af297fd4a2
+ 56632cb1cf4c0a73.5b3c900ef47d6748.c9a7e15eda8a465c.7d750bd9c2e5e210
+ ff23367565fa817f
+ after
+ 547b0a39ead7b444.746feba541176641.855fb267f4808724.4aa4f400ab8e7917
+ cead9dacffc0928b.3625e47e7dae1ce1.2e17882697f6902f.7f02e60a81bb9a08
+ b08baa5b6db8450c.3a2647a85a21887f.d01699aa0575115e.4603c5af297fd4a2
+ 0000000000000000.0000000000000000.00000000bf800000.7f02e60abf800000
+ ff23367565fa817f
+VROUNDPS_128_0x1(mem)
+ before
+ a7d8c17031c86c1a.1d7f201ac2071d6b.74343c9c68cd7568.74185cb0b1c06ad6
+ 536128b43f5d610e.5f2c8001e175baa0.63d9c53ed21d6e0a.2db3060b26a3bb77
+ dd8ae82fadc51a86.79b64ad4c9231cc0.02f9a9e04d7a0d5b.4fc5dcdbd6bf73ec
+ 231f7bcc970b54af.c76979ff159c8074.2f5f636ef5ef0f86.389ad98c5ca1cee1
+ 427df98a55d40a01
+ after
+ a7d8c17031c86c1a.1d7f201ac2071d6b.74343c9c68cd7568.74185cb0b1c06ad6
+ 536128b43f5d610e.5f2c8001e175baa0.63d9c53ed21d6e0a.2db3060b26a3bb77
+ dd8ae82fadc51a86.79b64ad4c9231cc0.02f9a9e04d7a0d5b.4fc5dcdbd6bf73ec
+ 0000000000000000.0000000000000000.74343c9c68cd7568.74185cb0bf800000
+ 427df98a55d40a01
+
+VROUNDPS_128_0x1(reg)
+ before
+ cbbc38415ce561f8.ffec5f76183bcab5.a59109ec616c226b.c4d66fd5e78930b8
+ 2ea1931e0e5f1074.4fbd0f1b4d613ac3.6f79f7084a203e4f.9f2b4aff3e522b1c
+ c67a058b06ce521f.ed5d08a6518a5e06.816f3dbf6c430fcc.9a2a6fd91759bddf
+ f1918af6e1bf65a5.b699c40440c1f3aa.37bdd97e6262d290.939f5a508da7a22d
+ 6456874fbd4a9631
+ after
+ cbbc38415ce561f8.ffec5f76183bcab5.a59109ec616c226b.c4d66fd5e78930b8
+ 2ea1931e0e5f1074.4fbd0f1b4d613ac3.6f79f7084a203e4f.9f2b4aff3e522b1c
+ c67a058b06ce521f.ed5d08a6518a5e06.816f3dbf6c430fcc.9a2a6fd91759bddf
+ 0000000000000000.0000000000000000.6f79f7084a203e4c.bf80000000000000
+ 6456874fbd4a9631
+VROUNDPS_128_0x1(mem)
+ before
+ ea1a72c1c24d5418.09331ec93abd83b3.873dc11f3713b4da.edb0c6b0c807c244
+ 02b99894b9bd990e.6bacbd72ae54e8f5.3a157ae4518a5ec2.ff9400c03bc11d97
+ 86fd73b3bda4213e.7447645cd811d216.aced6b40ab35ad90.c9b4841c56191d33
+ 53b3820aea11a7d4.7e520ef3557f7bc3.ba91101d611d5d6d.a75e4d2fb69dffc4
+ f5dc5765f7d8fef7
+ after
+ ea1a72c1c24d5418.09331ec93abd83b3.873dc11f3713b4da.edb0c6b0c807c244
+ 02b99894b9bd990e.6bacbd72ae54e8f5.3a157ae4518a5ec2.ff9400c03bc11d97
+ 86fd73b3bda4213e.7447645cd811d216.aced6b40ab35ad90.c9b4841c56191d33
+ 0000000000000000.0000000000000000.bf80000000000000.edb0c6b0c807c280
+ f5dc5765f7d8fef7
+
+VROUNDPS_128_0x2(reg)
+ before
+ 0f7c9e2ab3565778.45a73e855d0de9fe.e617b7a3c02a20a7.3ecce6698d502988
+ 50881eea89a446f2.38a5241132a6a1e5.09e35bd8b59ffc6f.156c680e4ed9ce0b
+ 164dd411124d0712.0978b19884e78bb8.4102f7fed1694dc7.1b3b12fabdc50822
+ bc16bb0bedded584.92ee60076fdd65a1.ebc08581b0144d5a.2c066018f91f92fb
+ 2499cf541bf329bf
+ after
+ 0f7c9e2ab3565778.45a73e855d0de9fe.e617b7a3c02a20a7.3ecce6698d502988
+ 50881eea89a446f2.38a5241132a6a1e5.09e35bd8b59ffc6f.156c680e4ed9ce0b
+ 164dd411124d0712.0978b19884e78bb8.4102f7fed1694dc7.1b3b12fabdc50822
+ 0000000000000000.0000000000000000.3f80000080000000.3f8000004ed9ce0b
+ 2499cf541bf329bf
+VROUNDPS_128_0x2(mem)
+ before
+ dfc0da9a414e899d.9e31cf45b3e2eef3.b0d1ad4b1093e9cc.636903ceed2d39d5
+ 3946fdd6873a6ebf.17e90c2902e58b0c.3fee144f8215d367.06486c4f243f4ce3
+ 0ef9b4f408c69351.85896e257674eb7a.1b1112fee270e19b.2eabbd72f2d6c332
+ 3aa37be1e1fbb581.425ef2a4aa1a48ea.200622464caecd97.38dcf0a1f27fda6b
+ 8028034ac1c5cd3c
+ after
+ dfc0da9a414e899d.9e31cf45b3e2eef3.b0d1ad4b1093e9cc.636903ceed2d39d5
+ 3946fdd6873a6ebf.17e90c2902e58b0c.3fee144f8215d367.06486c4f243f4ce3
+ 0ef9b4f408c69351.85896e257674eb7a.1b1112fee270e19b.2eabbd72f2d6c332
+ 0000000000000000.0000000000000000.800000003f800000.636903ceed2d39d5
+ 8028034ac1c5cd3c
+
+VROUNDPS_128_0x2(reg)
+ before
+ 62dbf1d8fa34d751.9911cf872de79078.acb493113b63df08.2a99c012dade5485
+ 3a41b7b73a593555.070f2bd40896e065.1dd74ddac4dbec7f.1595684eab093291
+ 64a64f531cbf23f5.60690bb28f126072.f3131d6ae10faafb.bcc796e6d83d22e8
+ 3c55b7183df3dcdd.80eaeb0fdd69cdcb.88b3fd2d2f8b572a.fdfcc7c68086e1b6
+ b3fe76dabcee2b27
+ after
+ 62dbf1d8fa34d751.9911cf872de79078.acb493113b63df08.2a99c012dade5485
+ 3a41b7b73a593555.070f2bd40896e065.1dd74ddac4dbec7f.1595684eab093291
+ 64a64f531cbf23f5.60690bb28f126072.f3131d6ae10faafb.bcc796e6d83d22e8
+ 0000000000000000.0000000000000000.3f800000c4dbe000.3f80000080000000
+ b3fe76dabcee2b27
+VROUNDPS_128_0x2(mem)
+ before
+ ba9a1f0faa83bc65.1e9bea7238809eb8.436047d60fa7e39d.3a05eb9049d92cb5
+ ee9b3e4f66514f9f.66c4e4cdaaf2a333.84959cf341d65d14.6353e2fdcc87684b
+ 2acf50880b62a1ff.701ca1962ed527f9.215665528e04f85c.61eadee154214596
+ 4c00cfa4b6c46db2.97ef1e3760b668b7.f56f1edf123d709f.8e16dca97b310043
+ 4723d6bfe045d5fd
+ after
+ ba9a1f0faa83bc65.1e9bea7238809eb8.436047d60fa7e39d.3a05eb9049d92cb5
+ ee9b3e4f66514f9f.66c4e4cdaaf2a333.84959cf341d65d14.6353e2fdcc87684b
+ 2acf50880b62a1ff.701ca1962ed527f9.215665528e04f85c.61eadee154214596
+ 0000000000000000.0000000000000000.436100003f800000.3f80000049d92cb8
+ 4723d6bfe045d5fd
+
+VROUNDPS_128_0x2(reg)
+ before
+ e95cca911ce80071.2ffc3991828371e3.3989551edd20a019.dbac4386ea8b810c
+ ce0fb38acea7bc4a.ae8d0a3a8baa67bf.b13544b641a00cca.b1d9513331fce6cd
+ 53868e158f0d4635.a780bc8bee450c72.5b41e76a27c1e777.52c1c3d3049c5c0f
+ d40e55a0fda7d9de.f4a0cd70c6601b27.92f738a82b0f6ecb.993215507e769efd
+ 64f6c398bb966ac4
+ after
+ e95cca911ce80071.2ffc3991828371e3.3989551edd20a019.dbac4386ea8b810c
+ ce0fb38acea7bc4a.ae8d0a3a8baa67bf.b13544b641a00cca.b1d9513331fce6cd
+ 53868e158f0d4635.a780bc8bee450c72.5b41e76a27c1e777.52c1c3d3049c5c0f
+ 0000000000000000.0000000000000000.8000000041a80000.800000003f800000
+ 64f6c398bb966ac4
+VROUNDPS_128_0x2(mem)
+ before
+ 8dda4995d9087a8f.adf30696b4ffb3f0.73bbb7d53008520a.b4a435dbea16dd73
+ f2aa2435f1d98b8c.3a819c634fa30e18.ff9cf9a648486b49.1c94d96fff63701a
+ 6d32cf63211458e4.d80313746b1f2601.730e0cd0282c220e.251320d00781636e
+ dc3dc60b85c59fc6.e1c76833a3fe3958.acde6d3defc13585.2d6c066b9dfdf118
+ 8eed88aa5e6256c7
+ after
+ 8dda4995d9087a8f.adf30696b4ffb3f0.73bbb7d53008520a.b4a435dbea16dd73
+ f2aa2435f1d98b8c.3a819c634fa30e18.ff9cf9a648486b49.1c94d96fff63701a
+ 6d32cf63211458e4.d80313746b1f2601.730e0cd0282c220e.251320d00781636e
+ 0000000000000000.0000000000000000.73bbb7d53f800000.80000000ea16dd73
+ 8eed88aa5e6256c7
+
+VROUNDPS_128_0x3(reg)
+ before
+ a6e0a0fae53cd024.1999851938f91a5b.b217950d93cc81c9.87d899dab7125edb
+ cf924cc8cf1899de.0110897956bb86d2.a740986fd8153bff.dec80b949c2c5a3c
+ 674f887fb781ee9f.716f4d17fc189e55.1c8f6cc30e66a3a7.8f7a3f56ba1ae4d3
+ c8634e8a3a030b14.43824de0451b1f11.6c4d0e77d04af46c.74b9b10c2fe8bacd
+ 6a53dea114a29655
+ after
+ a6e0a0fae53cd024.1999851938f91a5b.b217950d93cc81c9.87d899dab7125edb
+ cf924cc8cf1899de.0110897956bb86d2.a740986fd8153bff.dec80b949c2c5a3c
+ 674f887fb781ee9f.716f4d17fc189e55.1c8f6cc30e66a3a7.8f7a3f56ba1ae4d3
+ 0000000000000000.0000000000000000.80000000d8153bff.dec80b9480000000
+ 6a53dea114a29655
+VROUNDPS_128_0x3(mem)
+ before
+ 4d12410387553598.501a9c57f32b2ce8.541505be4ed0c531.f5c978f6ba4d6bfb
+ fac3561da40c52c2.59bf6c517f848cc8.81f3f19f33434ce2.124ea8ac69fc4400
+ 4b3299dc86d4aafe.409fbce4799a685f.a4ea8e6d0e816f4f.1f27990578e2ba26
+ 1d2b872a49b8f979.6207887c7dfafb5a.9ac45716fe95eba5.78a1476d848c0b1a
+ 7908ae5028857187
+ after
+ 4d12410387553598.501a9c57f32b2ce8.541505be4ed0c531.f5c978f6ba4d6bfb
+ fac3561da40c52c2.59bf6c517f848cc8.81f3f19f33434ce2.124ea8ac69fc4400
+ 4b3299dc86d4aafe.409fbce4799a685f.a4ea8e6d0e816f4f.1f27990578e2ba26
+ 0000000000000000.0000000000000000.541505be4ed0c531.f5c978f680000000
+ 7908ae5028857187
+
+VROUNDPS_128_0x3(reg)
+ before
+ 7da8cb1a0159281a.4c799af40ac4fb5e.1941ca85282f8365.3f4ec8851c8c7c10
+ e2cd9937aa946e7e.b4ea5027e5046bda.c299806c16c53a2b.6f545da68771ddbb
+ 03c31414c0c37d61.314824adf5850619.b95da59be2495c59.06a293655850cbd3
+ 3bd5381bde71926c.9f60937456538846.5ad8357f2846279a.e004e4aeae360283
+ d946ce6da22e3ef8
+ after
+ 7da8cb1a0159281a.4c799af40ac4fb5e.1941ca85282f8365.3f4ec8851c8c7c10
+ e2cd9937aa946e7e.b4ea5027e5046bda.c299806c16c53a2b.6f545da68771ddbb
+ 03c31414c0c37d61.314824adf5850619.b95da59be2495c59.06a293655850cbd3
+ 0000000000000000.0000000000000000.c298000000000000.6f545da680000000
+ d946ce6da22e3ef8
+VROUNDPS_128_0x3(mem)
+ before
+ cd33cd8e52443a5e.e85102baa02be84e.dafe17662578ac8e.02552c858548d59b
+ 98985bfdda84b3e0.65816c5ca37cbcb0.beee2e717d02301c.0b21871894dca308
+ 1641f6a755fb65ab.0db2746c83f04a41.27fc53807bfcce1d.d28841a3f28dcd8c
+ 23fa1876dfb50cea.3e301558db14ceab.f1f3027f3a7342bd.b3d656943ae78ed4
+ 0a57c2560977238b
+ after
+ cd33cd8e52443a5e.e85102baa02be84e.dafe17662578ac8e.02552c858548d59b
+ 98985bfdda84b3e0.65816c5ca37cbcb0.beee2e717d02301c.0b21871894dca308
+ 1641f6a755fb65ab.0db2746c83f04a41.27fc53807bfcce1d.d28841a3f28dcd8c
+ 0000000000000000.0000000000000000.dafe176600000000.0000000080000000
+ 0a57c2560977238b
+
+VROUNDPS_128_0x3(reg)
+ before
+ 33578255fac8c85e.9b8f3f5895bc63ca.52464c8b4773849b.f8a0b85ad7724a27
+ 8a2190fdaa67b8f9.5acce738931e2777.a74213716499a7bc.18d0effd6d05a088
+ 6b03eabab4de3007.3c7c8a01f4e7141c.976e6876ce1374bb.2d4d25551939000b
+ 31478bf9b4bc6c35.1c6da6a1d421e5e5.80184607206c2643.12e4d54cf61928dd
+ a5607ccf21b1d22a
+ after
+ 33578255fac8c85e.9b8f3f5895bc63ca.52464c8b4773849b.f8a0b85ad7724a27
+ 8a2190fdaa67b8f9.5acce738931e2777.a74213716499a7bc.18d0effd6d05a088
+ 6b03eabab4de3007.3c7c8a01f4e7141c.976e6876ce1374bb.2d4d25551939000b
+ 0000000000000000.0000000000000000.800000006499a7bc.000000006d05a088
+ a5607ccf21b1d22a
+VROUNDPS_128_0x3(mem)
+ before
+ c18f94cbb50ebb1d.3a3a7024488aa82e.d869b60350da5700.bc8aa98ef630fb01
+ 423b9b2bce3b9fe3.e12893a909d61f9f.4b3d3613831e2697.a8118e78edec2da1
+ 03320cda894439a7.825cf2f2952b0f34.51b5a2be8af70ed6.a1f8f032a02bf8ce
+ e23e63c602364696.7924886d8816b198.c59c77ee8074caea.018dca27ac799a35
+ 251a1bc2ac634d82
+ after
+ c18f94cbb50ebb1d.3a3a7024488aa82e.d869b60350da5700.bc8aa98ef630fb01
+ 423b9b2bce3b9fe3.e12893a909d61f9f.4b3d3613831e2697.a8118e78edec2da1
+ 03320cda894439a7.825cf2f2952b0f34.51b5a2be8af70ed6.a1f8f032a02bf8ce
+ 0000000000000000.0000000000000000.d869b60350da5700.80000000f630fb01
+ 251a1bc2ac634d82
+
+VROUNDPS_128_0x4(reg)
+ before
+ 69eddc713d744e60.b92c1cda541c82db.21ca51857d214478.85c03090829e17ff
+ 29500a9ffa38d87b.66c7b4029b03a9a3.d89b4aa610db027f.6beb4991ab83b040
+ c290a2b87f3c2980.c4dda62af4f5761a.f9e36d3cdecd285a.55ea3edb182e53da
+ 8ef99f286a0b7b1b.ae396e3e7a01a66b.dfeeb8b38285f2b4.1d898b5ce4abbaf9
+ a194adff2b07a2c8
+ after
+ 69eddc713d744e60.b92c1cda541c82db.21ca51857d214478.85c03090829e17ff
+ 29500a9ffa38d87b.66c7b4029b03a9a3.d89b4aa610db027f.6beb4991ab83b040
+ c290a2b87f3c2980.c4dda62af4f5761a.f9e36d3cdecd285a.55ea3edb182e53da
+ 0000000000000000.0000000000000000.d89b4aa600000000.6beb499180000000
+ a194adff2b07a2c8
+VROUNDPS_128_0x4(mem)
+ before
+ bbd71fb00a4dc673.ead6fd5b54310bf8.02a6882b4a30f5c3.e8082677998e9b3b
+ 491e5d5b9d8ae428.3275b9bedb3b14c2.9af171db7f901e4e.6f7db4f4be756098
+ 2534e3ecffc8b611.c220cdbb9bb4d325.53e6a33c362cde37.cf985c968ec57d7a
+ 2de62e4f4c15f95a.f62437c02f2884ce.0a519c388a10f1ab.66a61ccaa40a2e8a
+ 8ef3effa9dd1ae77
+ after
+ bbd71fb00a4dc673.ead6fd5b54310bf8.02a6882b4a30f5c3.e8082677998e9b3b
+ 491e5d5b9d8ae428.3275b9bedb3b14c2.9af171db7f901e4e.6f7db4f4be756098
+ 2534e3ecffc8b611.c220cdbb9bb4d325.53e6a33c362cde37.cf985c968ec57d7a
+ 0000000000000000.0000000000000000.000000004a30f5c4.e808267780000000
+ 8ef3effa9dd1ae77
+
+VROUNDPS_128_0x4(reg)
+ before
+ a5cbd19414a53aeb.3b00b970a17d6830.2acdf23733246369.99fed7bd984913d5
+ 057abf03a6120e93.2c4e003b1a0bc0bf.ba67fb8e4433aba2.ddb8d1b67be2ffe2
+ 0b4cb3b2eea5651a.dc9c7f9dd2cbbd32.023e4c30fde29924.b34d040e50e872fd
+ 148cab0f89e97c2d.28b6b280e5c91bb6.5e9de388fbbc699b.f587eeb332662853
+ 80330a903e68dc10
+ after
+ a5cbd19414a53aeb.3b00b970a17d6830.2acdf23733246369.99fed7bd984913d5
+ 057abf03a6120e93.2c4e003b1a0bc0bf.ba67fb8e4433aba2.ddb8d1b67be2ffe2
+ 0b4cb3b2eea5651a.dc9c7f9dd2cbbd32.023e4c30fde29924.b34d040e50e872fd
+ 0000000000000000.0000000000000000.800000004433c000.ddb8d1b67be2ffe2
+ 80330a903e68dc10
+VROUNDPS_128_0x4(mem)
+ before
+ 301dd4928ffa4c5f.7a88a285126a8f77.ea6716d270129576.29d2bb04d94d57b4
+ e211c9a34129326d.9a8a948025b5daa5.ff7d267d8eb2e89f.c127d00f34219e1b
+ 70da64b071014a65.d1df7e6d5f559863.43c25e6f5cb3d05d.81e91e16a8c57b7b
+ b74621a63b8c5274.79d35bb65cd6065c.92033a93f52308db.c564a283cfc42a81
+ e8e457c347abe6d9
+ after
+ 301dd4928ffa4c5f.7a88a285126a8f77.ea6716d270129576.29d2bb04d94d57b4
+ e211c9a34129326d.9a8a948025b5daa5.ff7d267d8eb2e89f.c127d00f34219e1b
+ 70da64b071014a65.d1df7e6d5f559863.43c25e6f5cb3d05d.81e91e16a8c57b7b
+ 0000000000000000.0000000000000000.ea6716d270129576.00000000d94d57b4
+ e8e457c347abe6d9
+
+VROUNDPS_128_0x4(reg)
+ before
+ 48b53943ac05ec2e.931f7c6fb9d804c6.efb127c8b6c5603d.c80c37d5760d4d46
+ 4022446d995e782d.e032f1f90af01c86.8fc7de100cade2b1.c1a9cf21fa7e5bc9
+ 2b7875afab42c581.7a4bfd2e48e158e1.b55f7cf8f81ac765.59a580639d81ee91
+ 6704c6737d3e11d7.3d361afc8fb67202.bdc7feee16994c05.6ccec5887c22c1ca
+ d6ee1b7ab36e919f
+ after
+ 48b53943ac05ec2e.931f7c6fb9d804c6.efb127c8b6c5603d.c80c37d5760d4d46
+ 4022446d995e782d.e032f1f90af01c86.8fc7de100cade2b1.c1a9cf21fa7e5bc9
+ 2b7875afab42c581.7a4bfd2e48e158e1.b55f7cf8f81ac765.59a580639d81ee91
+ 0000000000000000.0000000000000000.8000000000000000.c1a80000fa7e5bc9
+ d6ee1b7ab36e919f
+VROUNDPS_128_0x4(mem)
+ before
+ 73d2fc265d701a3d.4f103527abde96da.05bfc64efc7b2716.04495e5d03b5ac3c
+ 1f46e679963418cf.3ee8bd36d2ac9038.aeb17d10aa3d3349.e4329bb05afa25b7
+ b616545e7bc74682.92da5b0c8e363d9a.14d9b92eb60751c6.bacdae55b8f5f121
+ 140dc3c028346182.a53109157a07d7ae.1204f8943be53eba.e26894b7b8314c27
+ b74e4a43f73b7475
+ after
+ 73d2fc265d701a3d.4f103527abde96da.05bfc64efc7b2716.04495e5d03b5ac3c
+ 1f46e679963418cf.3ee8bd36d2ac9038.aeb17d10aa3d3349.e4329bb05afa25b7
+ b616545e7bc74682.92da5b0c8e363d9a.14d9b92eb60751c6.bacdae55b8f5f121
+ 0000000000000000.0000000000000000.00000000fc7b2716.0000000000000000
+ b74e4a43f73b7475
+
+VROUNDPS_256_0x0(reg)
+ before
+ 97cacb63109da3b6.15f9ad8db88725fa.d438c5bd32ac9b20.86fcb52f56e4b650
+ dd2913849fe51697.94a490b047cd4d17.7c3c8a7153b0c49c.4b8e6ce9220f74b5
+ e5b71e12419f09c3.6fdbe715f2119604.f789549b789f90cd.3d8599afbb723614
+ 0bc0e97a9256b7e7.816a2ea8d45fbcee.a36b20a83e063960.37afb86e3e1ab69b
+ 17d64611c712b073
+ after
+ 97cacb63109da3b6.15f9ad8db88725fa.d438c5bd32ac9b20.86fcb52f56e4b650
+ dd2913849fe51697.94a490b047cd4d17.7c3c8a7153b0c49c.4b8e6ce9220f74b5
+ e5b71e12419f09c3.6fdbe715f2119604.f789549b789f90cd.3d8599afbb723614
+ dd29138480000000.8000000047cd4d00.7c3c8a7153b0c49c.4b8e6ce900000000
+ 17d64611c712b073
+VROUNDPS_256_0x0(mem)
+ before
+ b8c8be837166e2cb.ab8f6f272d965daf.a61de1550ac47b00.da2ee9054070fc00
+ f54f9cb2582306cd.2172ac84afeb37c6.b9c07d09af4b8e68.f91eab1d1b69145a
+ ac385d899954d9a5.c8b39cffb2e281d9.981e7daee000b24f.5c86625b6a7ebe19
+ b84f7bf450051680.fea03b03d5077693.1d055d31b8f0a2e4.60b30a2dca3a36ea
+ 5ff2a0fed629b879
+ after
+ b8c8be837166e2cb.ab8f6f272d965daf.a61de1550ac47b00.da2ee9054070fc00
+ f54f9cb2582306cd.2172ac84afeb37c6.b9c07d09af4b8e68.f91eab1d1b69145a
+ ac385d899954d9a5.c8b39cffb2e281d9.981e7daee000b24f.5c86625b6a7ebe19
+ 800000007166e2cb.8000000000000000.8000000000000000.da2ee90540800000
+ 5ff2a0fed629b879
+
+VROUNDPS_256_0x0(reg)
+ before
+ b68c1e3a2bd87f71.f45f74df98437b8a.1e8386fcb2e453a1.263f997f54261c50
+ c1d0824d64d2c87f.3e36c3368d19c2ee.83a97856e50754ae.8d99ad83cfaedac2
+ dc09c7a31ea4cf4e.709ee5e64c94a7d9.8b5d0d7d0bfbb468.30df162845959964
+ 6382eaa9f4d8cf8b.686454d9f0bee876.90ed41ddbf4db078.e9dd4f5cd4e61463
+ 965ed40a95ae09ea
+ after
+ b68c1e3a2bd87f71.f45f74df98437b8a.1e8386fcb2e453a1.263f997f54261c50
+ c1d0824d64d2c87f.3e36c3368d19c2ee.83a97856e50754ae.8d99ad83cfaedac2
+ dc09c7a31ea4cf4e.709ee5e64c94a7d9.8b5d0d7d0bfbb468.30df162845959964
+ c1d0000064d2c87f.0000000080000000.80000000e50754ae.80000000cfaedac2
+ 965ed40a95ae09ea
+VROUNDPS_256_0x0(mem)
+ before
+ 1130211ea6f73226.b289e6c982fc06e2.00548efd96a63ff3.f0a311e39e88848d
+ 381db38423d04c42.2568b670659cadfe.153a0e3c59556979.05cd78f943386c50
+ e5f204292642126b.186c580b3843038c.84e2508456d92136.2db5728d4beaa370
+ f57b92f7ce5b41cd.e7e1c805987d4237.2717d0c0a83d2556.c2a8fb0951286697
+ 22f10fdbf281f172
+ after
+ 1130211ea6f73226.b289e6c982fc06e2.00548efd96a63ff3.f0a311e39e88848d
+ 381db38423d04c42.2568b670659cadfe.153a0e3c59556979.05cd78f943386c50
+ e5f204292642126b.186c580b3843038c.84e2508456d92136.2db5728d4beaa370
+ 0000000080000000.8000000080000000.0000000080000000.f0a311e380000000
+ 22f10fdbf281f172
+
+VROUNDPS_256_0x0(reg)
+ before
+ a7deab6ec97e7fac.4584d9db35269593.ee1300c921d6a8ac.dba70bdc6c8d2f05
+ afbaca2e72ad4df2.afd853c277b0caea.894dfec56edb6e97.7c5c7cc4bdd6fb6e
+ 94d068878a9a97ef.10457e96b1039bfd.14ddbd641b17d3a3.e7039f64b72447bd
+ b36d81e5adcf9950.4495d545fe2ec5f9.eb0d3912c517117d.f668f0a87781cd20
+ 8657eb7c19fb4ac0
+ after
+ a7deab6ec97e7fac.4584d9db35269593.ee1300c921d6a8ac.dba70bdc6c8d2f05
+ afbaca2e72ad4df2.afd853c277b0caea.894dfec56edb6e97.7c5c7cc4bdd6fb6e
+ 94d068878a9a97ef.10457e96b1039bfd.14ddbd641b17d3a3.e7039f64b72447bd
+ 8000000072ad4df2.8000000077b0caea.800000006edb6e97.7c5c7cc480000000
+ 8657eb7c19fb4ac0
+VROUNDPS_256_0x0(mem)
+ before
+ 739b0dccb89d7acc.68dd11b476da8ec1.2795d4ba7b3a040a.692a6f3b076565d0
+ 9902d1857074186e.106c15608147b3ed.9512f7e14335135b.ec80594c7e900b49
+ d456b3915e8be1d3.056688566ba04481.6ad5baa6732aaf19.cf5bf5afc5213e93
+ 00642fde9eee9126.a4166600d0747c28.82ad9af526269470.6d063ed178a63b5b
+ 24cf301f35aa3e4d
+ after
+ 739b0dccb89d7acc.68dd11b476da8ec1.2795d4ba7b3a040a.692a6f3b076565d0
+ 9902d1857074186e.106c15608147b3ed.9512f7e14335135b.ec80594c7e900b49
+ d456b3915e8be1d3.056688566ba04481.6ad5baa6732aaf19.cf5bf5afc5213e93
+ 739b0dcc80000000.68dd11b476da8ec1.000000007b3a040a.692a6f3b00000000
+ 24cf301f35aa3e4d
+
+VROUNDPS_256_0x1(reg)
+ before
+ 4f00c80495ba8314.f9f8c2574aa9e393.49caaccc4b4c988f.ba6512ba79347e8b
+ 49e601eb3661455d.9bdee7e781c99548.50cc542478b6d462.ecc89ee187602896
+ 70cdd642b42bc1d4.c2e21a7c5c5a616f.15695c76f43d6c4c.f4a3bb576cb74fbe
+ 1e014674aaa53324.4acfd701fa660334.f4edbf2d5a6d9bfa.b0c2e3064544af2f
+ fbf194db2e130414
+ after
+ 4f00c80495ba8314.f9f8c2574aa9e393.49caaccc4b4c988f.ba6512ba79347e8b
+ 49e601eb3661455d.9bdee7e781c99548.50cc542478b6d462.ecc89ee187602896
+ 70cdd642b42bc1d4.c2e21a7c5c5a616f.15695c76f43d6c4c.f4a3bb576cb74fbe
+ 49e601e800000000.bf800000bf800000.50cc542478b6d462.ecc89ee1bf800000
+ fbf194db2e130414
+VROUNDPS_256_0x1(mem)
+ before
+ b1fc49c34231099a.b1ce4aedb45ad6fa.0f739a6274fb39c5.49a479b547d39e17
+ aeaf7ea99da97bed.837fe0196fd6e701.ed98e08be925bd4b.70d9877a56fab150
+ ced5b0795c871638.f262026477a5a2e6.c00b246972ee4bf5.c5dae4e8246e1051
+ ed3c5a1f9ad895a8.58c1ae3a66544354.6498e2e62d64a1ed.a4f18b6b4cbcf6c5
+ 696b7b6f6a6fa059
+ after
+ b1fc49c34231099a.b1ce4aedb45ad6fa.0f739a6274fb39c5.49a479b547d39e17
+ aeaf7ea99da97bed.837fe0196fd6e701.ed98e08be925bd4b.70d9877a56fab150
+ ced5b0795c871638.f262026477a5a2e6.c00b246972ee4bf5.c5dae4e8246e1051
+ bf80000042300000.bf800000bf800000.0000000074fb39c5.49a479b047d39e00
+ 696b7b6f6a6fa059
+
+VROUNDPS_256_0x1(reg)
+ before
+ 7094ad611b144ab8.e6aef88774a7b568.13e9e008db6f05f8.b40a96f03693795f
+ 15b81eabfb362f8f.97f8069d050032a5.7d2692387080257e.8e2fbd71a8859078
+ b423cbbba5618c8a.dbe6004d6af0c88b.f3c4c238c115df91.cdd1d257a048a264
+ a820affcb5219d54.8d436383be823245.d10e6b726bba6ede.4cbe518c39e86a4e
+ e9c0b6fe8f6fa563
+ after
+ 7094ad611b144ab8.e6aef88774a7b568.13e9e008db6f05f8.b40a96f03693795f
+ 15b81eabfb362f8f.97f8069d050032a5.7d2692387080257e.8e2fbd71a8859078
+ b423cbbba5618c8a.dbe6004d6af0c88b.f3c4c238c115df91.cdd1d257a048a264
+ 00000000fb362f8f.bf80000000000000.7d2692387080257e.bf800000bf800000
+ e9c0b6fe8f6fa563
+VROUNDPS_256_0x1(mem)
+ before
+ 7fa47d98bfec0fcf.4ffdc7d9c8039d9a.8bdda92c1ec22dff.7452895409f90f11
+ e9362346e46864bd.04040dc07a92ca07.af7e5032a5bd74e7.36da18493860fed5
+ 054123f41bf15f5a.22827f1c665b5e48.d7f3d483707ec527.74f315bd937b77d6
+ ad93f98f8092bdd1.07c3175928e99508.de08af099a11daeb.8ae97a1cb6d4b5c1
+ d40845d23efaf542
+ after
+ 7fa47d98bfec0fcf.4ffdc7d9c8039d9a.8bdda92c1ec22dff.7452895409f90f11
+ e9362346e46864bd.04040dc07a92ca07.af7e5032a5bd74e7.36da18493860fed5
+ 054123f41bf15f5a.22827f1c665b5e48.d7f3d483707ec527.74f315bd937b77d6
+ 7fe47d98c0000000.4ffdc7d9c8039dc0.bf80000000000000.7452895400000000
+ d40845d23efaf542
+
+VROUNDPS_256_0x1(reg)
+ before
+ ae9c724bc7767305.bff621012e573a4f.0e13d4e35dc8adf4.9f895fb240837060
+ 74f0fbf3ecd66bb5.15371737414d91ff.92bdaf27a085e0b8.f7425f697ddf42b2
+ 8352de374aa518fe.8c22581ed67f7f0e.f10fa58f8eab6bff.c3ff2b1a6d320e0c
+ 350c16817b6fb78d.01835fa008fac0a8.8553b388c2c68976.dd8b3fb12d878e9b
+ 23b3181ad9ea7f8a
+ after
+ ae9c724bc7767305.bff621012e573a4f.0e13d4e35dc8adf4.9f895fb240837060
+ 74f0fbf3ecd66bb5.15371737414d91ff.92bdaf27a085e0b8.f7425f697ddf42b2
+ 8352de374aa518fe.8c22581ed67f7f0e.f10fa58f8eab6bff.c3ff2b1a6d320e0c
+ 74f0fbf3ecd66bb5.0000000041400000.bf800000bf800000.f7425f697ddf42b2
+ 23b3181ad9ea7f8a
+VROUNDPS_256_0x1(mem)
+ before
+ 6f4430418c679c07.e66b9f3f1ec1830e.4e26a8abf3c810f8.acd6d47fd96278c9
+ 9e070512620ba23b.f4bb75dccd26ba2d.51d6b02ab5f82a2b.c0e404df6e0c72a3
+ 8dcb137a78e14d54.ba4794c3242b9695.e461f1096793cb6c.1fc940131e50b3b1
+ 165bd463e9f6597e.945df962c05a54f2.e491e93427a7afe9.23d0828984b8799e
+ 2947c8ac3cd2fe17
+ after
+ 6f4430418c679c07.e66b9f3f1ec1830e.4e26a8abf3c810f8.acd6d47fd96278c9
+ 9e070512620ba23b.f4bb75dccd26ba2d.51d6b02ab5f82a2b.c0e404df6e0c72a3
+ 8dcb137a78e14d54.ba4794c3242b9695.e461f1096793cb6c.1fc940131e50b3b1
+ 6f443041bf800000.e66b9f3f00000000.4e26a8abf3c810f8.bf800000d96278c9
+ 2947c8ac3cd2fe17
+
+VROUNDPS_256_0x2(reg)
+ before
+ 8e780de8e32a7fc7.1682c6bbd25581e5.de479f243c422ff1.2d331397113f91cb
+ acb04ea9154a375b.690e636d4e0a82b4.f4538275356c643e.9b13eb1e40682f40
+ e03b855b6dc0647f.ebc92a647a211817.32cb9fc146662f84.0bfdeeb5d02d4374
+ 8665b06b871840de.7880948e71a7fe3c.f3fcf0740cbbcc70.57bc9648de9a8993
+ 5c1e61c486bbbfc8
+ after
+ 8e780de8e32a7fc7.1682c6bbd25581e5.de479f243c422ff1.2d331397113f91cb
+ acb04ea9154a375b.690e636d4e0a82b4.f4538275356c643e.9b13eb1e40682f40
+ e03b855b6dc0647f.ebc92a647a211817.32cb9fc146662f84.0bfdeeb5d02d4374
+ 800000003f800000.690e636d4e0a82b4.f45382753f800000.8000000040800000
+ 5c1e61c486bbbfc8
+VROUNDPS_256_0x2(mem)
+ before
+ f6edca13e39d9f3f.fb7aca4300dc0825.edff1ed650a8f14c.953273fb22f876ae
+ 01f64e23114ce525.99c6cf50749af7ff.24124528322ead76.73b823c025a76be9
+ 590567df2dd24fa6.bd94bbff7ede4a19.fa8484713447eee4.e8dcfc31b057e4ce
+ dae69332523d97ee.c3318bbbba333d1f.4b23579b71fe6fc2.52e8fbb860912008
+ 0c291bc3d0e35944
+ after
+ f6edca13e39d9f3f.fb7aca4300dc0825.edff1ed650a8f14c.953273fb22f876ae
+ 01f64e23114ce525.99c6cf50749af7ff.24124528322ead76.73b823c025a76be9
+ 590567df2dd24fa6.bd94bbff7ede4a19.fa8484713447eee4.e8dcfc31b057e4ce
+ f6edca13e39d9f3f.fb7aca433f800000.edff1ed650a8f14c.800000003f800000
+ 0c291bc3d0e35944
+
+VROUNDPS_256_0x2(reg)
+ before
+ 71eb58bd9cd8cc2d.60654d0a9d987a28.07e93aefc5250cbc.f3b93b930560ed3d
+ df7aae1261fdb570.c74d115229f0b480.e508c4093a40f29d.cd13aa460d782481
+ b022192ebbdd4fb9.eb6c5cf613500023.b9da2574b6112c6d.b7fd229ea552d0ba
+ 422e967d4504d7b3.a78ca8e376c41b3d.dfab599cd423f6d9.8c431e89e8fbac13
+ 28b01af1f27e75b8
+ after
+ 71eb58bd9cd8cc2d.60654d0a9d987a28.07e93aefc5250cbc.f3b93b930560ed3d
+ df7aae1261fdb570.c74d115229f0b480.e508c4093a40f29d.cd13aa460d782481
+ b022192ebbdd4fb9.eb6c5cf613500023.b9da2574b6112c6d.b7fd229ea552d0ba
+ df7aae1261fdb570.c74d11003f800000.e508c4093f800000.cd13aa463f800000
+ 28b01af1f27e75b8
+VROUNDPS_256_0x2(mem)
+ before
+ 671293c4e0e7e7d6.efec1f6b9bff890b.d97a73036f59c1f9.b3c65ded31028b8d
+ 253303edcd43bd99.14a6b2645a59a16d.5c023843191aad84.91782cd3683b2934
+ 3de0e858d69db42c.0ea94bd51d9e5a84.0cef749091139d0a.d50ec2bb15590a7b
+ 8de5bef1170188bc.3741e428815bf1fc.c50fa1d4f2514bb6.dbd21c0fd5e96a0d
+ ff10343d44768797
+ after
+ 671293c4e0e7e7d6.efec1f6b9bff890b.d97a73036f59c1f9.b3c65ded31028b8d
+ 253303edcd43bd99.14a6b2645a59a16d.5c023843191aad84.91782cd3683b2934
+ 3de0e858d69db42c.0ea94bd51d9e5a84.0cef749091139d0a.d50ec2bb15590a7b
+ 671293c4e0e7e7d6.efec1f6b80000000.d97a73036f59c1f9.800000003f800000
+ ff10343d44768797
+
+VROUNDPS_256_0x2(reg)
+ before
+ 9c1608affd8c9bc5.f00effa4aa7cf475.ecba7bcb211ba283.622c3dfd58df73b5
+ 102f93d39cb7e342.4127285eae19b682.8a5f0b289a6aa8c3.c114c3f6e0c9d332
+ b6a6d114be849abb.5efbb6093ce48810.6b7e90ad87d54168.bd91afaaa61c255a
+ eac8bfdeff7efddb.2258249373ea264a.ec6106c585e7a71f.31707d07c5e32658
+ fb7daaf8592b915a
+ after
+ 9c1608affd8c9bc5.f00effa4aa7cf475.ecba7bcb211ba283.622c3dfd58df73b5
+ 102f93d39cb7e342.4127285eae19b682.8a5f0b289a6aa8c3.c114c3f6e0c9d332
+ b6a6d114be849abb.5efbb6093ce48810.6b7e90ad87d54168.bd91afaaa61c255a
+ 3f80000080000000.4130000080000000.8000000080000000.c1100000e0c9d332
+ fb7daaf8592b915a
+VROUNDPS_256_0x2(mem)
+ before
+ f583b1697ffe2489.07e1579dfa32484f.6808eee66c364e5d.69556adc2f2c1694
+ fd500e47526a9914.6b3d97bd4b2bb7c2.0ed891f045d5ba74.3fa6b75e2231cc72
+ edae3d7cef7bac24.70287aaa8ff585e1.ee94889c1ad127bc.c8a0e9b7f9810366
+ a36abbf5713c1be8.74edfdd0611df058.e6084ed506395061.618ffc5350a8f71b
+ 66beec9ec433e63e
+ after
+ f583b1697ffe2489.07e1579dfa32484f.6808eee66c364e5d.69556adc2f2c1694
+ fd500e47526a9914.6b3d97bd4b2bb7c2.0ed891f045d5ba74.3fa6b75e2231cc72
+ edae3d7cef7bac24.70287aaa8ff585e1.ee94889c1ad127bc.c8a0e9b7f9810366
+ f583b1697ffe2489.3f800000fa32484f.6808eee66c364e5d.69556adc3f800000
+ 66beec9ec433e63e
+
+VROUNDPS_256_0x3(reg)
+ before
+ 337ab605f1ad0a7b.f950029ff5b9a08a.d2da1a9b5e2d31d2.d0ff62892516f38e
+ 241055f272a3a07d.cc2c906496fef837.e539cf7821b487fc.89473da39476ca70
+ 95cac5d3e39fe4f1.f9cae1327118de1a.0b5717d1473b2c82.eeaa5c0f6f649133
+ e2f50212e1301182.5af56ff4a1121060.9e80ee146b505d0f.d9f53cbad1ec0602
+ 27f4588ed61be309
+ after
+ 337ab605f1ad0a7b.f950029ff5b9a08a.d2da1a9b5e2d31d2.d0ff62892516f38e
+ 241055f272a3a07d.cc2c906496fef837.e539cf7821b487fc.89473da39476ca70
+ 95cac5d3e39fe4f1.f9cae1327118de1a.0b5717d1473b2c82.eeaa5c0f6f649133
+ 0000000072a3a07d.cc2c906480000000.e539cf7800000000.8000000080000000
+ 27f4588ed61be309
+VROUNDPS_256_0x3(mem)
+ before
+ b5732c789bfce576.67dc091d08df64dd.cc7bb89643f94834.fb0050ac2a7f5650
+ 5d3d35653b9cc872.7fcdd45ff23a19ae.2c26360472d842c3.7f233a041f5253f0
+ fc20ed40d306472c.881261443ecc6ba0.54c3672a4bbbbc39.8434a78ae6578f9c
+ 6ee6d2f47e461fce.ddf8ab388621985f.211ec7f4e9ae70c1.678093a91c1a47ff
+ 8554facd5d25b6c6
+ after
+ b5732c789bfce576.67dc091d08df64dd.cc7bb89643f94834.fb0050ac2a7f5650
+ 5d3d35653b9cc872.7fcdd45ff23a19ae.2c26360472d842c3.7f233a041f5253f0
+ fc20ed40d306472c.881261443ecc6ba0.54c3672a4bbbbc39.8434a78ae6578f9c
+ 8000000080000000.67dc091d00000000.cc7bb89643f90000.fb0050ac00000000
+ 8554facd5d25b6c6
+
+VROUNDPS_256_0x3(reg)
+ before
+ 38fad9634406199d.8f5d5f6f59690c85.daccafa766c6da99.6f03d04e68be1b88
+ ddbf2ad56d49ad2f.3b4f119c7f79c97c.dbd867fd7b466df8.1a3d0024e5f679b9
+ d0eeeb907578ab29.4f8862670d8513e0.3b68d1a7602e8f28.fe9ad2637c634581
+ 6ed51801f8215236.a5d6d0bc1e96a6dc.58cae80fb1097ad6.f7e4c2f547103c0c
+ e1e84cc865091a85
+ after
+ 38fad9634406199d.8f5d5f6f59690c85.daccafa766c6da99.6f03d04e68be1b88
+ ddbf2ad56d49ad2f.3b4f119c7f79c97c.dbd867fd7b466df8.1a3d0024e5f679b9
+ d0eeeb907578ab29.4f8862670d8513e0.3b68d1a7602e8f28.fe9ad2637c634581
+ ddbf2ad56d49ad2f.000000007f79c97c.dbd867fd7b466df8.00000000e5f679b9
+ e1e84cc865091a85
+VROUNDPS_256_0x3(mem)
+ before
+ 9872edc7f05b9a19.11beab9290d0dc03.1a04d687cfba3e9d.8d48a9a30b636bae
+ f84e1fde04117af3.16f6a2b1dc0f863c.8addf0b43bfc964f.35300ecd0ac99d5b
+ dd4860f8be377440.d9caf7c9766d8b8c.d12e9a307e696b1d.aecc15fb49c64d8a
+ 232b2c0339da442c.b683a845fa7329a0.cac351e5b60c7933.5269b99865e6b7e7
+ 7f53f610f9b5171d
+ after
+ 9872edc7f05b9a19.11beab9290d0dc03.1a04d687cfba3e9d.8d48a9a30b636bae
+ f84e1fde04117af3.16f6a2b1dc0f863c.8addf0b43bfc964f.35300ecd0ac99d5b
+ dd4860f8be377440.d9caf7c9766d8b8c.d12e9a307e696b1d.aecc15fb49c64d8a
+ 80000000f05b9a19.0000000080000000.00000000cfba3e9d.8000000000000000
+ 7f53f610f9b5171d
+
+VROUNDPS_256_0x3(reg)
+ before
+ 8fd5c8cfa1c0a9d9.a6c5fdea9205a8e2.0970b19305af9a23.536890c1fcf17cbf
+ e03d2c41fa93a8c6.42e0519ae4c45a8f.2edc0c1e32ac1bc2.47e9d3ae6e252feb
+ ccd51dd29fb85191.d349a3fd4c24165e.8112b7531df6e729.8212969a27b34fe3
+ b1eb97ee2dbddfe5.35cc6f00e5309a7c.5e60ad9c641a3b03.e0ae567044a798d4
+ 3d8b8d1ce10ec5ea
+ after
+ 8fd5c8cfa1c0a9d9.a6c5fdea9205a8e2.0970b19305af9a23.536890c1fcf17cbf
+ e03d2c41fa93a8c6.42e0519ae4c45a8f.2edc0c1e32ac1bc2.47e9d3ae6e252feb
+ ccd51dd29fb85191.d349a3fd4c24165e.8112b7531df6e729.8212969a27b34fe3
+ e03d2c41fa93a8c6.42e00000e4c45a8f.0000000000000000.47e9d3806e252feb
+ 3d8b8d1ce10ec5ea
+VROUNDPS_256_0x3(mem)
+ before
+ 7473b98a18f39351.e9c99601402d8f6f.43343190cbf4a015.2110ea66a0a353fd
+ 633355a60862be34.d1bc167872959edb.db4f66971b7de554.266f6a1d6f1e6bc2
+ e597de5ccb6801bf.c60f14bd628045d4.d8e78803f1d62565.c8c92a2e6d15beff
+ d56ace987d101a1f.22108b3eaa7ac307.15ca15bf680b1b76.6569250435178a60
+ 589d570a63ad0890
+ after
+ 7473b98a18f39351.e9c99601402d8f6f.43343190cbf4a015.2110ea66a0a353fd
+ 633355a60862be34.d1bc167872959edb.db4f66971b7de554.266f6a1d6f1e6bc2
+ e597de5ccb6801bf.c60f14bd628045d4.d8e78803f1d62565.c8c92a2e6d15beff
+ 7473b98a00000000.e9c9960140000000.43340000cbf4a015.0000000080000000
+ 589d570a63ad0890
+
+VROUNDPS_256_0x4(reg)
+ before
+ fdafbcae9465773c.117aa3473b67c380.42097766e610521f.70c288b69c2984b1
+ afec505b64ca110f.7491d8532077b80d.8348d4a1b2cd2fc9.c49c5ed6aa3b1c42
+ cca0107d6e6913b6.d97ce9aa484eb7f3.3f179f5aac3e95b1.ec24110aae4d9f56
+ af17f7804ecdb9dc.1e075336d0f87a5e.d3c3d3ff6dedc282.c6251f3fc36cc819
+ 2c6d035f05a354b6
+ after
+ fdafbcae9465773c.117aa3473b67c380.42097766e610521f.70c288b69c2984b1
+ afec505b64ca110f.7491d8532077b80d.8348d4a1b2cd2fc9.c49c5ed6aa3b1c42
+ cca0107d6e6913b6.d97ce9aa484eb7f3.3f179f5aac3e95b1.ec24110aae4d9f56
+ 8000000064ca110f.7491d85300000000.8000000080000000.c49c600080000000
+ 2c6d035f05a354b6
+VROUNDPS_256_0x4(mem)
+ before
+ fcc63a5791ffff5a.b39d01d0a1823e2e.1dfe90e5d480be79.9b986cfc9368f0e9
+ 10fd3e13828a8431.367e2ad90214df58.b42d1ea26ff23e70.f3e166bbba3b5c92
+ 46de8d80f552a066.92056f080e10d805.bd607859be5ab871.37ecbda97df04128
+ 7835a28905630f25.257fcac7600265e2.15621bf6dcc5e6a5.c3036e327816dc57
+ f37374c3483669cc
+ after
+ fcc63a5791ffff5a.b39d01d0a1823e2e.1dfe90e5d480be79.9b986cfc9368f0e9
+ 10fd3e13828a8431.367e2ad90214df58.b42d1ea26ff23e70.f3e166bbba3b5c92
+ 46de8d80f552a066.92056f080e10d805.bd607859be5ab871.37ecbda97df04128
+ fcc63a5780000000.8000000080000000.00000000d480be79.8000000080000000
+ f37374c3483669cc
+
+VROUNDPS_256_0x4(reg)
+ before
+ 2388cbc789de2433.83cef919cfc88d9c.493939849574c19b.99008165e53e843b
+ af8e6fa9d6994837.44740e1e6e8dd5f4.5c7cb8a948f429db.23072892f6d2505d
+ f3d15dd7cbf31285.95f55e83ffbea45c.b89741a4160dd94f.90418b6a2a8b0438
+ 4b9d8fbc0579bec9.531b64349d68b6fe.bbd5d2e09a4c0ca2.bd7a26d79e785df7
+ 848076c76ea217c7
+ after
+ 2388cbc789de2433.83cef919cfc88d9c.493939849574c19b.99008165e53e843b
+ af8e6fa9d6994837.44740e1e6e8dd5f4.5c7cb8a948f429db.23072892f6d2505d
+ f3d15dd7cbf31285.95f55e83ffbea45c.b89741a4160dd94f.90418b6a2a8b0438
+ 80000000d6994837.447400006e8dd5f4.5c7cb8a948f429e0.00000000f6d2505d
+ 848076c76ea217c7
+VROUNDPS_256_0x4(mem)
+ before
+ c21ef524b417edd3.133d03c41fb688ae.5ab39c1d6496c607.bf8165c9703cff81
+ 531f21dc8fe29c48.a6feb55bb637abe1.8789822a715592a2.21e9f9cb3569ee97
+ 135075da1810e052.622c9fed6587640d.b4699247e0b0d4fc.3e57875285601591
+ df7d6e096eac741c.a213bfe6c932efdf.be1e4961ccb34840.70180ccafbacaf1b
+ 1478859f33d9f9e0
+ after
+ c21ef524b417edd3.133d03c41fb688ae.5ab39c1d6496c607.bf8165c9703cff81
+ 531f21dc8fe29c48.a6feb55bb637abe1.8789822a715592a2.21e9f9cb3569ee97
+ 135075da1810e052.622c9fed6587640d.b4699247e0b0d4fc.3e57875285601591
+ c220000080000000.0000000000000000.5ab39c1d6496c607.bf800000703cff81
+ 1478859f33d9f9e0
+
+VROUNDPS_256_0x4(reg)
+ before
+ 86c3ed3eca742f8d.91728657aac215d3.c2ff0fb27dc48703.81762262516bab9b
+ 224440115c088ccd.06fb3bb0ea5e7fa2.1d3c8dbe1eca6924.d93b99378ce3ba39
+ 45497b8683224e4d.1ae308fe4a8d6eb6.1115357447cfd1ef.a23a2acd99272e45
+ 491c9807de4cafb9.a9f8692ee55b9d3b.f9d801429460fa0f.b83f520f9243c6ec
+ f7168ce996443c59
+ after
+ 86c3ed3eca742f8d.91728657aac215d3.c2ff0fb27dc48703.81762262516bab9b
+ 224440115c088ccd.06fb3bb0ea5e7fa2.1d3c8dbe1eca6924.d93b99378ce3ba39
+ 45497b8683224e4d.1ae308fe4a8d6eb6.1115357447cfd1ef.a23a2acd99272e45
+ 000000005c088ccd.00000000ea5e7fa2.0000000000000000.d93b993780000000
+ f7168ce996443c59
+VROUNDPS_256_0x4(mem)
+ before
+ 3b8b5446bf364db9.8b0a95020714ebbc.8f04da2cd8d2c95c.30cfef93a3082231
+ 606926142923b538.675f6de29a064003.a8d4d8e53e00ae46.1447fad30d538300
+ 427e7e3ff0192f01.39671c1334ade839.cf34de4333f00824.ff8c1e6d70ce5929
+ bd94d9b132247840.5d6d9f0170951f0b.e2f06834d4af9223.4fe957cf6804e258
+ 5eaca2648f815838
+ after
+ 3b8b5446bf364db9.8b0a95020714ebbc.8f04da2cd8d2c95c.30cfef93a3082231
+ 606926142923b538.675f6de29a064003.a8d4d8e53e00ae46.1447fad30d538300
+ 427e7e3ff0192f01.39671c1334ade839.cf34de4333f00824.ff8c1e6d70ce5929
+ 00000000bf800000.8000000000000000.80000000d8d2c95c.0000000080000000
+ 5eaca2648f815838
+
+VROUNDPD_128_0x0(reg)
+ before
+ 8a1ffa9984d2f876.ac78b257084e4c23.2fbff018ea4a2325.bcd3f2a33d48096f
+ 2d8f5bd8e182fdbe.edf6851d90a566d4.0ba70dc440592e32.39abf87b88c72933
+ a448c18e421da5bb.5bd9cef0e635847f.4d72f1710b4d7ddf.3542f7aad439ad9b
+ 4c96282844302a19.d2ef0aba25086051.506c998ce9b34cd7.8b656a1b3ba952d5
+ 19e0cdbad924d40b
+ after
+ 8a1ffa9984d2f876.ac78b257084e4c23.2fbff018ea4a2325.bcd3f2a33d48096f
+ 2d8f5bd8e182fdbe.edf6851d90a566d4.0ba70dc440592e32.39abf87b88c72933
+ a448c18e421da5bb.5bd9cef0e635847f.4d72f1710b4d7ddf.3542f7aad439ad9b
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 19e0cdbad924d40b
+VROUNDPD_128_0x0(mem)
+ before
+ ba7f9d74cbb4ee69.7fc58d108246c886.2d02b4696a2cb676.72e1ff7f7615d6c7
+ 490e54332c675e1c.9a21ebb499ebbdab.4ae048e8d0ad4419.0e1d21b84d02585b
+ a45870e41949de50.faf53e7f24ac4337.045342237395c467.806bfaa20a030e3e
+ a62b6c74ad642a30.f98e82dcc01497d4.36281e0570f2f38c.231886a84aa6341c
+ 5571c238a97605a3
+ after
+ ba7f9d74cbb4ee69.7fc58d108246c886.2d02b4696a2cb676.72e1ff7f7615d6c7
+ 490e54332c675e1c.9a21ebb499ebbdab.4ae048e8d0ad4419.0e1d21b84d02585b
+ a45870e41949de50.faf53e7f24ac4337.045342237395c467.806bfaa20a030e3e
+ 0000000000000000.0000000000000000.0000000000000000.72e1ff7f7615d6c7
+ 5571c238a97605a3
+
+VROUNDPD_128_0x0(reg)
+ before
+ 71c0a8bdc200be7d.2a51c4cd05c600e9.f439b43908aff52f.be2b597de3d08cb3
+ d25236a331cf9b56.0e97f5dd3c7b1aa7.4740cf01990a98f3.76276e74e63a4d09
+ d6726756936fd7db.2cc9798f6e8e3595.4eefcfa00eb0bdcd.3cead9d7983cf0b9
+ d86e3843836cafb8.62b3cecfb80b0ce0.6594b083032da068.ea3e169213e231f0
+ 5ef0a1927339ced9
+ after
+ 71c0a8bdc200be7d.2a51c4cd05c600e9.f439b43908aff52f.be2b597de3d08cb3
+ d25236a331cf9b56.0e97f5dd3c7b1aa7.4740cf01990a98f3.76276e74e63a4d09
+ d6726756936fd7db.2cc9798f6e8e3595.4eefcfa00eb0bdcd.3cead9d7983cf0b9
+ 0000000000000000.0000000000000000.4740cf01990a98f3.76276e74e63a4d09
+ 5ef0a1927339ced9
+VROUNDPD_128_0x0(mem)
+ before
+ 72ccf7c1d54c81a1.3390a3d49e535f98.8a206f8936fe5db3.e87a6e14150e7c71
+ 049e930d54280774.4526a6767fb02328.81ded9a90374e23b.33ec06c0e0de8f94
+ ee32f1600dd71b7d.687a3c96c30d3614.24b7861b3b7857a3.a23773f4ff29127c
+ 0d538ea81b687be9.fad9619f05f8d507.4d78f4cbfb177a18.91a7b11a0e7c44d6
+ 5c88bca0aa625f4d
+ after
+ 72ccf7c1d54c81a1.3390a3d49e535f98.8a206f8936fe5db3.e87a6e14150e7c71
+ 049e930d54280774.4526a6767fb02328.81ded9a90374e23b.33ec06c0e0de8f94
+ ee32f1600dd71b7d.687a3c96c30d3614.24b7861b3b7857a3.a23773f4ff29127c
+ 0000000000000000.0000000000000000.8000000000000000.e87a6e14150e7c71
+ 5c88bca0aa625f4d
+
+VROUNDPD_128_0x0(reg)
+ before
+ 5f2691f16e68a18e.3dcfe4d09ae4e1e4.558f12fce1fc3cad.d9ed9ea55f5c05c6
+ f6cc2b79f7194344.5b7071c4a7590999.d6e7491bf5a6a6b4.a5e200968153b5d8
+ 7dc885a4e101841d.4103b0705ed2b134.da2f0467da8150c6.8b2397888008467b
+ 50649edec6ac9ec2.cc541dc0da5c93e3.bbb13e4c2e19768f.687bdd69768873da
+ 18b750237fdef922
+ after
+ 5f2691f16e68a18e.3dcfe4d09ae4e1e4.558f12fce1fc3cad.d9ed9ea55f5c05c6
+ f6cc2b79f7194344.5b7071c4a7590999.d6e7491bf5a6a6b4.a5e200968153b5d8
+ 7dc885a4e101841d.4103b0705ed2b134.da2f0467da8150c6.8b2397888008467b
+ 0000000000000000.0000000000000000.d6e7491bf5a6a6b4.8000000000000000
+ 18b750237fdef922
+VROUNDPD_128_0x0(mem)
+ before
+ 77a46ba4b817947f.cbed6f9345a7cee2.d82f35a038026ccf.d6baf3368dfb54bc
+ 620caad73c3eff1c.49aff62ff77d5027.415f72fd92d0f827.8896209192b225f9
+ b3bb8aa8275ff726.28f62d1e7bbb5f3d.e4b252c107d2f215.2b91c0cad9ca26f1
+ 477f8603978738c8.c30e13cd6aec38d1.9bf251dab11517c5.1cf7cf4bffd09351
+ b71349819f4fa7c4
+ after
+ 77a46ba4b817947f.cbed6f9345a7cee2.d82f35a038026ccf.d6baf3368dfb54bc
+ 620caad73c3eff1c.49aff62ff77d5027.415f72fd92d0f827.8896209192b225f9
+ b3bb8aa8275ff726.28f62d1e7bbb5f3d.e4b252c107d2f215.2b91c0cad9ca26f1
+ 0000000000000000.0000000000000000.d82f35a038026ccf.d6baf3368dfb54bc
+ b71349819f4fa7c4
+
+VROUNDPD_128_0x1(reg)
+ before
+ 58332ad956d39ff7.fa231ad4a5c07e2f.7542a1a6629c178f.43ece932aca42365
+ 5ba16fbec0e9b796.a872c2086f198487.9cdfd417ff573822.b86c97b7158cd11e
+ 1daa139b771c2b4c.2d39fa89119b07fb.9331a98bdcaad637.d63ed85407d8df1f
+ f89a12de1af936c6.65453f44a654c3b8.b5841b6d96212e7a.792e27f59f940692
+ 7c070086f8cd05a3
+ after
+ 58332ad956d39ff7.fa231ad4a5c07e2f.7542a1a6629c178f.43ece932aca42365
+ 5ba16fbec0e9b796.a872c2086f198487.9cdfd417ff573822.b86c97b7158cd11e
+ 1daa139b771c2b4c.2d39fa89119b07fb.9331a98bdcaad637.d63ed85407d8df1f
+ 0000000000000000.0000000000000000.bff0000000000000.bff0000000000000
+ 7c070086f8cd05a3
+VROUNDPD_128_0x1(mem)
+ before
+ bd97e0f32f8e977f.49bd68f2420a15af.2b5f0c264a5074e9.6024262bc8467c96
+ 17a841285fe37752.6c5e11438ede04b4.5d56dd191a99d5bb.ee5dc6300ea7fb38
+ 6607a111a5d96148.bdcb0a3d97fe3f81.d6f52e0b323da35a.bd7bf8e805cfe80b
+ 86807b9a1c7b138b.974e4e4cfbf801c1.72077be7ad489af1.27c9b7bf484b7fbc
+ 8994ff2274a6fcf6
+ after
+ bd97e0f32f8e977f.49bd68f2420a15af.2b5f0c264a5074e9.6024262bc8467c96
+ 17a841285fe37752.6c5e11438ede04b4.5d56dd191a99d5bb.ee5dc6300ea7fb38
+ 6607a111a5d96148.bdcb0a3d97fe3f81.d6f52e0b323da35a.bd7bf8e805cfe80b
+ 0000000000000000.0000000000000000.0000000000000000.6024262bc8467c96
+ 8994ff2274a6fcf6
+
+VROUNDPD_128_0x1(reg)
+ before
+ 4028cc7b256c9a66.52de4cb0e1d5474a.5834d9dd56578721.0d5a4199a7c475ad
+ a6d11b38f52a96b8.a8ef8e3d0ff4baaf.5bc9a75a43a70d4c.82b8fb0d3dbff1b9
+ 18dbe6c3836b2c97.637dbf2fc2e328e7.fc59b5315f75ceef.afee252f8a45ca42
+ f3922b8a68bb97b0.5f565a7117ae4c1d.9730fecc454c07b6.6fc83bebab60bb73
+ 9e11ba2dbb1e827a
+ after
+ 4028cc7b256c9a66.52de4cb0e1d5474a.5834d9dd56578721.0d5a4199a7c475ad
+ a6d11b38f52a96b8.a8ef8e3d0ff4baaf.5bc9a75a43a70d4c.82b8fb0d3dbff1b9
+ 18dbe6c3836b2c97.637dbf2fc2e328e7.fc59b5315f75ceef.afee252f8a45ca42
+ 0000000000000000.0000000000000000.5bc9a75a43a70d4c.bff0000000000000
+ 9e11ba2dbb1e827a
+VROUNDPD_128_0x1(mem)
+ before
+ 17971de2d78bd980.9141e5f743a714ae.7744dbef2a62e37e.88997e9991b9f44c
+ b824e0f41ab27cb4.4f351178adbadf3e.8914bf95160aa936.2ae23103e047d05d
+ 5b857f51a19f293f.89baa9784480340c.6f92804ff7b35a70.db551376ce82d997
+ de8777e4875e9a50.9b1cab63a4864ec3.07899c09ea67b158.f63f215ef5f749a4
+ d6ec5627f4305c30
+ after
+ 17971de2d78bd980.9141e5f743a714ae.7744dbef2a62e37e.88997e9991b9f44c
+ b824e0f41ab27cb4.4f351178adbadf3e.8914bf95160aa936.2ae23103e047d05d
+ 5b857f51a19f293f.89baa9784480340c.6f92804ff7b35a70.db551376ce82d997
+ 0000000000000000.0000000000000000.7744dbef2a62e37e.bff0000000000000
+ d6ec5627f4305c30
+
+VROUNDPD_128_0x1(reg)
+ before
+ d9a8ae3d65bc50e8.1bf34298e8fc8c11.e2a712a568576a10.2bc78eaf0a346b1c
+ 59be250ce4245f78.f0985e5be184baaf.b8a7daaa2d80c49e.b916d22d742644e6
+ b47cb8000ef6c68b.374146188e02e255.7a67ffdf8e8b981a.8b43e5704448f7e2
+ 442c62867ebdc0ce.ceb977bb0a83be30.84357eae27062130.7f1a426294a6413d
+ 6f6765f1834cde23
+ after
+ d9a8ae3d65bc50e8.1bf34298e8fc8c11.e2a712a568576a10.2bc78eaf0a346b1c
+ 59be250ce4245f78.f0985e5be184baaf.b8a7daaa2d80c49e.b916d22d742644e6
+ b47cb8000ef6c68b.374146188e02e255.7a67ffdf8e8b981a.8b43e5704448f7e2
+ 0000000000000000.0000000000000000.bff0000000000000.bff0000000000000
+ 6f6765f1834cde23
+VROUNDPD_128_0x1(mem)
+ before
+ 38f6ca072a478abf.671b1f08d1068bed.8fcd6b3071120a6b.325b5285957d9c8b
+ b792ed92a7a2003e.7795ebf4a25c6193.574aa063e0bc8433.e02677ce747b44d8
+ c6094b7d166afdcb.d2e6c2b58d4b7e6c.03fa9141738ce6b4.eae2e9f75f8c57c2
+ 42255eb492aa3d93.d259a1b630602026.6da9bab4458eed19.acdba56bf23c0ff6
+ 815ca695ca18a920
+ after
+ 38f6ca072a478abf.671b1f08d1068bed.8fcd6b3071120a6b.325b5285957d9c8b
+ b792ed92a7a2003e.7795ebf4a25c6193.574aa063e0bc8433.e02677ce747b44d8
+ c6094b7d166afdcb.d2e6c2b58d4b7e6c.03fa9141738ce6b4.eae2e9f75f8c57c2
+ 0000000000000000.0000000000000000.bff0000000000000.0000000000000000
+ 815ca695ca18a920
+
+VROUNDPD_128_0x2(reg)
+ before
+ c7b3e8e382ab60eb.07b3a423386e7bc2.d53c83652426816b.722597aa72ce558f
+ d92a67c0b7827104.f27f99b623c27583.35d9642d0729dee7.ee39a50d1759d942
+ 130e1f9904271816.dd55b7596fb3e503.4f7d407a75f67247.bdb05fcb4f3a365d
+ d1ab0dd8062991ce.a5007cf9394c876d.7f7514b909187b37.bc5741cf377e280c
+ c5fac705ea306a7c
+ after
+ c7b3e8e382ab60eb.07b3a423386e7bc2.d53c83652426816b.722597aa72ce558f
+ d92a67c0b7827104.f27f99b623c27583.35d9642d0729dee7.ee39a50d1759d942
+ 130e1f9904271816.dd55b7596fb3e503.4f7d407a75f67247.bdb05fcb4f3a365d
+ 0000000000000000.0000000000000000.3ff0000000000000.ee39a50d1759d942
+ c5fac705ea306a7c
+VROUNDPD_128_0x2(mem)
+ before
+ b5656e59855cb9d9.6e4d2cea581117d8.264e63809d9a18ee.220ada545f1b3362
+ 6864b1b7230fd14f.483f783c976de8df.3c09e8dcb6a855b2.928b90b8148cd675
+ bac20b0be0546e09.bacfed385ec83d8f.c3fe87f7a082f7e4.2c433152c3f6a21b
+ 874dfb41d9374b33.1f47874c49af5596.97f9bdbf7835bdb1.4c7dba8c09e5d101
+ 4e8625d482e6a0d3
+ after
+ b5656e59855cb9d9.6e4d2cea581117d8.264e63809d9a18ee.220ada545f1b3362
+ 6864b1b7230fd14f.483f783c976de8df.3c09e8dcb6a855b2.928b90b8148cd675
+ bac20b0be0546e09.bacfed385ec83d8f.c3fe87f7a082f7e4.2c433152c3f6a21b
+ 0000000000000000.0000000000000000.3ff0000000000000.3ff0000000000000
+ 4e8625d482e6a0d3
+
+VROUNDPD_128_0x2(reg)
+ before
+ 8eaa7095c8844b3c.abcffa452ac525fa.d5f443e2f5ad6a9e.94c6051f59cc6144
+ 6835963a7a4c0de9.02158604ee08b88a.36221c68fe4eb953.9631db036053a0ca
+ 3873933131c82385.68eb1968420fc00e.a01d0e49ff1f7e62.7905bb57a8d7366f
+ 5ab064e58c86c9bd.b81d315f41e3f8b3.6d3116f194abf477.191021074e63de5e
+ 521c8aff6d0355c4
+ after
+ 8eaa7095c8844b3c.abcffa452ac525fa.d5f443e2f5ad6a9e.94c6051f59cc6144
+ 6835963a7a4c0de9.02158604ee08b88a.36221c68fe4eb953.9631db036053a0ca
+ 3873933131c82385.68eb1968420fc00e.a01d0e49ff1f7e62.7905bb57a8d7366f
+ 0000000000000000.0000000000000000.3ff0000000000000.8000000000000000
+ 521c8aff6d0355c4
+VROUNDPD_128_0x2(mem)
+ before
+ 00f6712b22c457cc.2a3704c324123a3d.d0764ad407921da5.fba92ecc5a7e583d
+ fe6a527888b19fa3.04556f3597f7b4b0.8bc4deb3b128eb0f.a4d35446ed24e661
+ 2a44a9d0bbd6eb75.4457a1a881c171c3.c5d16be75aaf1d1e.c6f983cce82ada8f
+ 5f4ff321d840f56d.468796887dfcad21.5a6a6c5e1f3570fd.bb68b7c8e71c6f72
+ e06ceda78784e2b6
+ after
+ 00f6712b22c457cc.2a3704c324123a3d.d0764ad407921da5.fba92ecc5a7e583d
+ fe6a527888b19fa3.04556f3597f7b4b0.8bc4deb3b128eb0f.a4d35446ed24e661
+ 2a44a9d0bbd6eb75.4457a1a881c171c3.c5d16be75aaf1d1e.c6f983cce82ada8f
+ 0000000000000000.0000000000000000.d0764ad407921da5.fba92ecc5a7e583d
+ e06ceda78784e2b6
+
+VROUNDPD_128_0x2(reg)
+ before
+ 92511fd663f06f09.7859aa55fbfa79b8.66314b422835a677.255b5d041bc6a0d9
+ 2b624bc018ec5114.532c4c5a3f103581.00a3ba411df79671.0470bac36b6d68de
+ 08ed6cd04102c686.cb95551bc18fe3f5.6f28e1f0f8cfbaba.d27500882a368637
+ 853c7f747bc00809.bb603f849b82403f.110bbcbd56484dfe.6a35aa3f752db410
+ aa7e34d5675fae97
+ after
+ 92511fd663f06f09.7859aa55fbfa79b8.66314b422835a677.255b5d041bc6a0d9
+ 2b624bc018ec5114.532c4c5a3f103581.00a3ba411df79671.0470bac36b6d68de
+ 08ed6cd04102c686.cb95551bc18fe3f5.6f28e1f0f8cfbaba.d27500882a368637
+ 0000000000000000.0000000000000000.3ff0000000000000.3ff0000000000000
+ aa7e34d5675fae97
+VROUNDPD_128_0x2(mem)
+ before
+ 6c1a1a341dd732f6.ff9c7e1761b25349.01598881ecf5078c.41994513d2ee8ceb
+ 8ed6d84ab2a1fa59.d05967258f62e4f4.774baafecef5f608.5a1e7a5e094db32b
+ ea7eeb0243cac3ed.55bf350aa35ff8b4.fb0423e75d8dc7de.bae6560a97f2fe6a
+ 5edece48eb5d48de.ea1ae4323632c835.674e6f28b6c9363b.bc3dd5831769a855
+ bb6ff335253cef98
+ after
+ 6c1a1a341dd732f6.ff9c7e1761b25349.01598881ecf5078c.41994513d2ee8ceb
+ 8ed6d84ab2a1fa59.d05967258f62e4f4.774baafecef5f608.5a1e7a5e094db32b
+ ea7eeb0243cac3ed.55bf350aa35ff8b4.fb0423e75d8dc7de.bae6560a97f2fe6a
+ 0000000000000000.0000000000000000.3ff0000000000000.41994513d4000000
+ bb6ff335253cef98
+
+VROUNDPD_128_0x3(reg)
+ before
+ 15c7ad8d5ef90cde.c4c1fd08c6674757.ebb5710ae6699324.99f608aef4b6014b
+ 2492fdf55d2b3ed4.faf5f42ef1f27a85.b4ddd6fc4f8f932d.6bc86c63345fe239
+ 461ce1dbbf5fbf26.da4430a6880d9d94.a1df11750c3005fb.bb90163591d19631
+ d5b154a91f20cc7f.417b2c5ca6c16eaf.0e051de2b9d9253a.631a820e2817d861
+ 40312cdc143d66f3
+ after
+ 15c7ad8d5ef90cde.c4c1fd08c6674757.ebb5710ae6699324.99f608aef4b6014b
+ 2492fdf55d2b3ed4.faf5f42ef1f27a85.b4ddd6fc4f8f932d.6bc86c63345fe239
+ 461ce1dbbf5fbf26.da4430a6880d9d94.a1df11750c3005fb.bb90163591d19631
+ 0000000000000000.0000000000000000.8000000000000000.6bc86c63345fe239
+ 40312cdc143d66f3
+VROUNDPD_128_0x3(mem)
+ before
+ 2fa3918a724ffa13.2f9d53cd19faa18b.0c66643c671ca702.579cf6aef3152e98
+ 0a3a2c045d5a50ee.ae2cd8b24a7a79f8.15d15433e82905ba.d8ef994455715dbf
+ aec37936f16926b0.afa9e1c44e2b9270.3988782b44f54403.ed4c01127c77ee5b
+ f70af40c4b893684.8f62696fc099269f.54564d12988a1f09.f2fd2a8303b61c1a
+ 4250100387b725a5
+ after
+ 2fa3918a724ffa13.2f9d53cd19faa18b.0c66643c671ca702.579cf6aef3152e98
+ 0a3a2c045d5a50ee.ae2cd8b24a7a79f8.15d15433e82905ba.d8ef994455715dbf
+ aec37936f16926b0.afa9e1c44e2b9270.3988782b44f54403.ed4c01127c77ee5b
+ 0000000000000000.0000000000000000.0000000000000000.579cf6aef3152e98
+ 4250100387b725a5
+
+VROUNDPD_128_0x3(reg)
+ before
+ 3b8faffea40843ab.c1db1a7287c53d97.a8a16d1f3d517132.42084ed3fff753f7
+ 380704e1f434b2d6.e9016555c029f714.57b3e74060deb0d5.e06bf75996459cf9
+ 95030a1615c8b0d2.494a539f12c21f28.f8e4d53ec5cc1f33.0849c4927882b53d
+ add1bd0aa34e774c.be805f3e9a9b72ff.e87f328609a8faf9.976f3269c2b95bec
+ 69a8bbca8ff74a35
+ after
+ 3b8faffea40843ab.c1db1a7287c53d97.a8a16d1f3d517132.42084ed3fff753f7
+ 380704e1f434b2d6.e9016555c029f714.57b3e74060deb0d5.e06bf75996459cf9
+ 95030a1615c8b0d2.494a539f12c21f28.f8e4d53ec5cc1f33.0849c4927882b53d
+ 0000000000000000.0000000000000000.57b3e74060deb0d5.e06bf75996459cf9
+ 69a8bbca8ff74a35
+VROUNDPD_128_0x3(mem)
+ before
+ 5ac2dda1fc473e42.debc192a395544f0.2470061c74c0acc4.81d2fa82c7fd7dd2
+ 468713db24b5f23f.830f1be174665269.57e6c227ba3d88a4.202729a09c57e36b
+ 09c4da62234e235a.f717bd9aef0fde64.33ae114a8b1fc4ca.21ccbc4a24436970
+ 7f46ac23161d8dbc.9820fdc346db248d.94946e7101721963.e00baeeef94c4a8c
+ b931fbf7baffc46c
+ after
+ 5ac2dda1fc473e42.debc192a395544f0.2470061c74c0acc4.81d2fa82c7fd7dd2
+ 468713db24b5f23f.830f1be174665269.57e6c227ba3d88a4.202729a09c57e36b
+ 09c4da62234e235a.f717bd9aef0fde64.33ae114a8b1fc4ca.21ccbc4a24436970
+ 0000000000000000.0000000000000000.0000000000000000.8000000000000000
+ b931fbf7baffc46c
+
+VROUNDPD_128_0x3(reg)
+ before
+ 08899fd100e611bb.84d6070b192eec94.c076d6c71657608f.566355883840469b
+ 296197e86a8f6e26.f3436605478efb0c.cd654512fb0ece16.54e9437b4d97069d
+ 7803dda891861659.aa5846fcbc487750.19384410908ca9d0.6cf0b2365b831496
+ 51bd6f7d135646ff.84e021de95681c8d.023cd12d715e2e67.794520a57e0e2cb1
+ 57b408b5d4460c1b
+ after
+ 08899fd100e611bb.84d6070b192eec94.c076d6c71657608f.566355883840469b
+ 296197e86a8f6e26.f3436605478efb0c.cd654512fb0ece16.54e9437b4d97069d
+ 7803dda891861659.aa5846fcbc487750.19384410908ca9d0.6cf0b2365b831496
+ 0000000000000000.0000000000000000.cd654512fb0ece16.54e9437b4d97069d
+ 57b408b5d4460c1b
+VROUNDPD_128_0x3(mem)
+ before
+ e209e65076376eff.10d948d38c8b3ac5.5da97596edfba5ef.e2bee7d53b0f9887
+ f50f376482eb0f8b.11a4651797b12e56.117dbd10e10ccfa1.16088275892b24dd
+ 6e9476db1470abe8.b06ac0b3d1555d5f.7b2975388da756d0.fb679f77f83f0e15
+ 28621fa347d2fd45.48765715d502048b.797919fa0bd9f5a8.eb26384923d692da
+ 43934b55a77cecd9
+ after
+ e209e65076376eff.10d948d38c8b3ac5.5da97596edfba5ef.e2bee7d53b0f9887
+ f50f376482eb0f8b.11a4651797b12e56.117dbd10e10ccfa1.16088275892b24dd
+ 6e9476db1470abe8.b06ac0b3d1555d5f.7b2975388da756d0.fb679f77f83f0e15
+ 0000000000000000.0000000000000000.5da97596edfba5ef.e2bee7d53b0f9887
+ 43934b55a77cecd9
+
+VROUNDPD_128_0x4(reg)
+ before
+ 60f9d3091fbe57bd.fe46aea7371bc2cc.371625a83f455f88.e63826437aad6a54
+ 9ca3cdd028271033.ce0c9fd30159b6a9.d89426d7aca9aaff.9d3417fdf32f6f01
+ 54de33165d4352e7.72806f13c1989509.873e5710b7ba209f.7c376816946cc0da
+ e4f603475b9f5b84.c86d995391e31a18.9f5eb2befd04fe12.5d0f9578796f1b0c
+ 1e861a11bd443ac2
+ after
+ 60f9d3091fbe57bd.fe46aea7371bc2cc.371625a83f455f88.e63826437aad6a54
+ 9ca3cdd028271033.ce0c9fd30159b6a9.d89426d7aca9aaff.9d3417fdf32f6f01
+ 54de33165d4352e7.72806f13c1989509.873e5710b7ba209f.7c376816946cc0da
+ 0000000000000000.0000000000000000.d89426d7aca9aaff.8000000000000000
+ 1e861a11bd443ac2
+VROUNDPD_128_0x4(mem)
+ before
+ 996874cb7df8da29.a83738cfbdc665b7.aaa1997f90460201.7e40354d1a148004
+ ac831e94d496b66d.fcecce1a2044ad2b.f6e6eb83d8cd09f1.7e32db29a875e122
+ 31a29457de2b8cb9.3c63c2941fa66e8d.86090c4c8585ea13.fd7fa1bf46b45e18
+ 06905200b8c2163a.c4e60eaa5677e589.38d676c4b4796295.567281798e5c3391
+ e45979c41cf99c3a
+ after
+ 996874cb7df8da29.a83738cfbdc665b7.aaa1997f90460201.7e40354d1a148004
+ ac831e94d496b66d.fcecce1a2044ad2b.f6e6eb83d8cd09f1.7e32db29a875e122
+ 31a29457de2b8cb9.3c63c2941fa66e8d.86090c4c8585ea13.fd7fa1bf46b45e18
+ 0000000000000000.0000000000000000.8000000000000000.7e40354d1a148004
+ e45979c41cf99c3a
+
+VROUNDPD_128_0x4(reg)
+ before
+ 057e840d8c18d4bf.051bd57b7e67101c.f0c2b0c662444eca.e619a7d980b62da0
+ 132e9ebf7c4418cb.0b0d98b54b26388a.1c43a356de97e5fd.6e9e1a7606460762
+ 6bb4c3458509a40a.f53317983b0c48b0.a4b5e4c567ffe5cd.aa304c866138ab07
+ 6a5ef00d45f4b32a.9d58ce116b24fdbc.e4646d7e99058be7.779db7f7ad95d6bb
+ b1afd9b4076b44a9
+ after
+ 057e840d8c18d4bf.051bd57b7e67101c.f0c2b0c662444eca.e619a7d980b62da0
+ 132e9ebf7c4418cb.0b0d98b54b26388a.1c43a356de97e5fd.6e9e1a7606460762
+ 6bb4c3458509a40a.f53317983b0c48b0.a4b5e4c567ffe5cd.aa304c866138ab07
+ 0000000000000000.0000000000000000.0000000000000000.6e9e1a7606460762
+ b1afd9b4076b44a9
+VROUNDPD_128_0x4(mem)
+ before
+ 35332da98bc5b0fd.6a772082589082d4.e04a390df67b13d8.389c3cef0f3713f7
+ ddf52fc254b0d8e5.c84a4f1059694db7.9ad4d576f91c4530.fca84c836520b9a8
+ 86c15cec7f36758a.e1247923e50c507d.a7c11d3a8f1350f1.8cd599a6384cb8a7
+ 0c622f112766461b.0f519b279604c6d3.e4de8d44d56cf047.436f1fc423484d9f
+ 7fc2db4ac39fb33d
+ after
+ 35332da98bc5b0fd.6a772082589082d4.e04a390df67b13d8.389c3cef0f3713f7
+ ddf52fc254b0d8e5.c84a4f1059694db7.9ad4d576f91c4530.fca84c836520b9a8
+ 86c15cec7f36758a.e1247923e50c507d.a7c11d3a8f1350f1.8cd599a6384cb8a7
+ 0000000000000000.0000000000000000.e04a390df67b13d8.0000000000000000
+ 7fc2db4ac39fb33d
+
+VROUNDPD_128_0x4(reg)
+ before
+ 9b1ac8a2b3de282d.4ba6231e684905c2.af1db0890bddec64.2bf7a180e634e05d
+ f3c3e2399090e61a.1f57b7005fed70ab.1dd4b3b3de24fedd.59d8d6dadf76dd60
+ e208257cf5412ab0.644264a1275d4004.b6c1a312ab6437e9.4a4da63edb3fa37b
+ c6378ed57e7e2f9d.f633a8efdda634f6.d43279130f29d535.da218f98f79aeedb
+ e5220cd44e9379ac
+ after
+ 9b1ac8a2b3de282d.4ba6231e684905c2.af1db0890bddec64.2bf7a180e634e05d
+ f3c3e2399090e61a.1f57b7005fed70ab.1dd4b3b3de24fedd.59d8d6dadf76dd60
+ e208257cf5412ab0.644264a1275d4004.b6c1a312ab6437e9.4a4da63edb3fa37b
+ 0000000000000000.0000000000000000.0000000000000000.59d8d6dadf76dd60
+ e5220cd44e9379ac
+VROUNDPD_128_0x4(mem)
+ before
+ 471a9adffc370119.f99a17b2c8d2338b.b1f6fdd59cd306b0.d4713321a500126d
+ dcd6b3a31e91424f.d97ebe7e6fc97026.7157e13f81f0735c.12cbcba70a742a3c
+ 8022d50ed0adf879.c02f7ea50eef221b.1221cf19a70a3726.ea8c3f13d9115b4f
+ 0fca7b0a2d98dec4.0cf8549341d18716.7022444f2b2c0d3c.b8008bd0af64df51
+ d872a94a27f8f2ef
+ after
+ 471a9adffc370119.f99a17b2c8d2338b.b1f6fdd59cd306b0.d4713321a500126d
+ dcd6b3a31e91424f.d97ebe7e6fc97026.7157e13f81f0735c.12cbcba70a742a3c
+ 8022d50ed0adf879.c02f7ea50eef221b.1221cf19a70a3726.ea8c3f13d9115b4f
+ 0000000000000000.0000000000000000.8000000000000000.d4713321a500126d
+ d872a94a27f8f2ef
+
+VROUNDPD_256_0x0(reg)
+ before
+ a63097edde5ad2d5.64992185515db15b.17273ab4a5fbd9c2.6724bbcd2862b2c7
+ 7e8450256f15b9ae.5d5d446a59082d6c.3f062e74d6f755cc.d3f4af7fbbb9e2f6
+ bcbbd05f77b5e427.d5e05fa561a60d20.dee22b3f6e5336e0.8f5e9f52ff3c58f3
+ bc21130591c68feb.a8efee2283420ea6.52082d820c9abaa9.792e043011f7d2ea
+ 6c2f5b070cf70a08
+ after
+ a63097edde5ad2d5.64992185515db15b.17273ab4a5fbd9c2.6724bbcd2862b2c7
+ 7e8450256f15b9ae.5d5d446a59082d6c.3f062e74d6f755cc.d3f4af7fbbb9e2f6
+ bcbbd05f77b5e427.d5e05fa561a60d20.dee22b3f6e5336e0.8f5e9f52ff3c58f3
+ 7e8450256f15b9ae.5d5d446a59082d6c.0000000000000000.d3f4af7fbbb9e2f6
+ 6c2f5b070cf70a08
+VROUNDPD_256_0x0(mem)
+ before
+ 442f21c10c47bc79.d902168559d5f5a7.b1566dcddee8ec28.f5c131a74a591bd3
+ dcf8d14c2ef3a668.71aad4496c6d5306.cee158928ba562d2.245c321cc41b950b
+ 1257e7938e088202.df6449bf661be5b6.da5c2c5da9842ed1.3c242b4b176c66fd
+ c018e08247910d73.7f7e7152e26ae760.b092631b51910a51.97641ba2ded9c855
+ 926afb8cb6edf8be
+ after
+ 442f21c10c47bc79.d902168559d5f5a7.b1566dcddee8ec28.f5c131a74a591bd3
+ dcf8d14c2ef3a668.71aad4496c6d5306.cee158928ba562d2.245c321cc41b950b
+ 1257e7938e088202.df6449bf661be5b6.da5c2c5da9842ed1.3c242b4b176c66fd
+ 442f21c10c47bc79.d902168559d5f5a7.8000000000000000.f5c131a74a591bd3
+ 926afb8cb6edf8be
+
+VROUNDPD_256_0x0(reg)
+ before
+ 8980c8753a3532e4.c4073605759b02e6.ac42486e7ce694b3.2e517bb6a2d9b27d
+ d8f37fc9063bb175.f9ef670835301f88.c4fdcb7fd11b2959.2e63f01cb567e482
+ db0f1bf4b78db21a.3a9eee77a25e1e84.22fbf5f17d96e2fe.8e953c37a8485a8c
+ ef1f9862e9b77182.65de473ed931bb07.2187c2301ae2fa4f.28b3ddf59786d1c6
+ da894e419d2f045c
+ after
+ 8980c8753a3532e4.c4073605759b02e6.ac42486e7ce694b3.2e517bb6a2d9b27d
+ d8f37fc9063bb175.f9ef670835301f88.c4fdcb7fd11b2959.2e63f01cb567e482
+ db0f1bf4b78db21a.3a9eee77a25e1e84.22fbf5f17d96e2fe.8e953c37a8485a8c
+ d8f37fc9063bb175.f9ef670835301f88.c4fdcb7fd11b2959.0000000000000000
+ da894e419d2f045c
+VROUNDPD_256_0x0(mem)
+ before
+ 7ee20b07d74fb17c.6e71f37f37432957.547cef4af6b4b43c.1fef2ea8478caef8
+ f28c90335ff1924f.b54f26b83ec01745.e444618513f3c350.767e36c59d1f3aa4
+ 10515ab154216304.20062f7798b777fa.f20219dd4ffaa56f.847fd5f4bb27d900
+ b5fee36dd0ebe2c5.0be2092ae4b6851f.5882933dc3d615c4.a33f069f3a31c9b8
+ 310ac834b9c84477
+ after
+ 7ee20b07d74fb17c.6e71f37f37432957.547cef4af6b4b43c.1fef2ea8478caef8
+ f28c90335ff1924f.b54f26b83ec01745.e444618513f3c350.767e36c59d1f3aa4
+ 10515ab154216304.20062f7798b777fa.f20219dd4ffaa56f.847fd5f4bb27d900
+ 7ee20b07d74fb17c.6e71f37f37432957.547cef4af6b4b43c.0000000000000000
+ 310ac834b9c84477
+
+VROUNDPD_256_0x0(reg)
+ before
+ 882c141ed17887e9.be5fa954ef5cc9bf.d22fb13bbc487c63.f38f4b908d92d17c
+ 06f0e8c820cecdbc.05402850ce7fd51d.d0392118bcf99a70.a0f7bec4c93b93c2
+ 05a43fa042555399.676dda4e8861c20c.634b572c815618f2.398467c492dc17c3
+ e2921511d299552f.c0b13d3b3a0d4bb7.e6b34ee3a6ea3596.9b03c27c05811bab
+ a2404bd83d3659a5
+ after
+ 882c141ed17887e9.be5fa954ef5cc9bf.d22fb13bbc487c63.f38f4b908d92d17c
+ 06f0e8c820cecdbc.05402850ce7fd51d.d0392118bcf99a70.a0f7bec4c93b93c2
+ 05a43fa042555399.676dda4e8861c20c.634b572c815618f2.398467c492dc17c3
+ 0000000000000000.0000000000000000.d0392118bcf99a70.8000000000000000
+ a2404bd83d3659a5
+VROUNDPD_256_0x0(mem)
+ before
+ 2b077ec556088ede.fa0766876c270f28.edd9cc02008f2d4b.b5bb02a9c8422b08
+ 1023d82d6d027682.a74f2e6fad8abc31.c8b2038ff4f324f4.2cb070ea82e937f4
+ 2e62d4fd9e31ccbc.46b66a33314e99f5.2e065ecd3546ebdd.a6de9212716b9504
+ 618eee2204a04db8.338815409300e221.fba259aadc943f33.8191668e305480e7
+ 1815e7c85c313547
+ after
+ 2b077ec556088ede.fa0766876c270f28.edd9cc02008f2d4b.b5bb02a9c8422b08
+ 1023d82d6d027682.a74f2e6fad8abc31.c8b2038ff4f324f4.2cb070ea82e937f4
+ 2e62d4fd9e31ccbc.46b66a33314e99f5.2e065ecd3546ebdd.a6de9212716b9504
+ 0000000000000000.fa0766876c270f28.edd9cc02008f2d4b.8000000000000000
+ 1815e7c85c313547
+
+VROUNDPD_256_0x1(reg)
+ before
+ c7b5112e908df0d1.8574a287bb5bb5a3.ca102b036f2bd260.0b51711107e7dc21
+ e9bee12a69f5ed30.76e06d17e06fbfa9.689ca9e6625ba65f.3ae121efd24d7ed4
+ dc7d512a82f46711.109ecac08ee729f6.67768957071d9aca.641ce52e58d1e078
+ fa3c5f9977169b20.2f7a356de2cfacb5.24ebc9c1fbfcea4c.65d03abbb680bf38
+ 19c79a830765d741
+ after
+ c7b5112e908df0d1.8574a287bb5bb5a3.ca102b036f2bd260.0b51711107e7dc21
+ e9bee12a69f5ed30.76e06d17e06fbfa9.689ca9e6625ba65f.3ae121efd24d7ed4
+ dc7d512a82f46711.109ecac08ee729f6.67768957071d9aca.641ce52e58d1e078
+ e9bee12a69f5ed30.76e06d17e06fbfa9.689ca9e6625ba65f.0000000000000000
+ 19c79a830765d741
+VROUNDPD_256_0x1(mem)
+ before
+ 5cce8370678ce4be.a14707e3e5e8c508.af3f2a0af7340712.fb47648fd984d192
+ 0ab07070f302a1dc.2bec437468f52075.6cbb2583ea21f43a.48d6562f3e428c47
+ fe3bdd6ec6d2cbc7.f67610b89bc9e915.41b8a3c4d6a23159.67e49c0cc5c15718
+ 16394755fd081eaa.5c306b1b1af15c92.0c031fb9d8c3779a.b4bc30930b8e6eb1
+ 8bab102eab330cbd
+ after
+ 5cce8370678ce4be.a14707e3e5e8c508.af3f2a0af7340712.fb47648fd984d192
+ 0ab07070f302a1dc.2bec437468f52075.6cbb2583ea21f43a.48d6562f3e428c47
+ fe3bdd6ec6d2cbc7.f67610b89bc9e915.41b8a3c4d6a23159.67e49c0cc5c15718
+ 5cce8370678ce4be.bff0000000000000.bff0000000000000.fb47648fd984d192
+ 8bab102eab330cbd
+
+VROUNDPD_256_0x1(reg)
+ before
+ 48fd384a423f6ee9.2d782913b4b155b2.bb674f0982f8b598.a868154f0b91852a
+ 46fea2536b3bcfe0.1fc2fe9306d82d0a.6d67b9ee6e6a2fd4.f1b301708b181535
+ e3fa4bb6c2b56d4f.c7e445c10f8962df.cf7ca3377bd407f2.c2af600a7663e4e6
+ 7a3d30dee43882e1.03aa778aecd1af5c.3ef20b4e44c1799d.f92aac07e57eae6a
+ 71ee6355f6752eec
+ after
+ 48fd384a423f6ee9.2d782913b4b155b2.bb674f0982f8b598.a868154f0b91852a
+ 46fea2536b3bcfe0.1fc2fe9306d82d0a.6d67b9ee6e6a2fd4.f1b301708b181535
+ e3fa4bb6c2b56d4f.c7e445c10f8962df.cf7ca3377bd407f2.c2af600a7663e4e6
+ 46fea2536b3bcfe0.0000000000000000.6d67b9ee6e6a2fd4.f1b301708b181535
+ 71ee6355f6752eec
+VROUNDPD_256_0x1(mem)
+ before
+ 05c801dfc5552199.67124c366d514b44.aedf12d8b8bbd2ae.1415eca166bdc082
+ 938400916c29439c.05c79b2cf88a0321.a351909890538501.ae30429b7c55194c
+ f6eede570afd5023.b2a61a2b2172e827.c0ca6fb78fa68480.689009a82314c0a8
+ 09d1151db9de0357.c9fcc49f85923400.df182b1fd1bf8d58.9f813e33f686f142
+ ad4fdbab9238e7c5
+ after
+ 05c801dfc5552199.67124c366d514b44.aedf12d8b8bbd2ae.1415eca166bdc082
+ 938400916c29439c.05c79b2cf88a0321.a351909890538501.ae30429b7c55194c
+ f6eede570afd5023.b2a61a2b2172e827.c0ca6fb78fa68480.689009a82314c0a8
+ 0000000000000000.67124c366d514b44.bff0000000000000.0000000000000000
+ ad4fdbab9238e7c5
+
+VROUNDPD_256_0x1(reg)
+ before
+ ef46de7992b5dfde.aafb24cf95d71967.a51594f4c0782358.de053ebe74ab5ab5
+ c1b2430a92891538.b336845abbf44e7c.a43d89966caff3dc.975e267f9174a8c2
+ 7fde04ca2f41c580.024fb2a846425dc5.21bf9cf128c4de38.e8ee5e4d462932ac
+ 85181f2505682a62.71122ba653cc036c.77e9ca728d422117.ab836216afd3b69e
+ bee7aec5e780eec5
+ after
+ ef46de7992b5dfde.aafb24cf95d71967.a51594f4c0782358.de053ebe74ab5ab5
+ c1b2430a92891538.b336845abbf44e7c.a43d89966caff3dc.975e267f9174a8c2
+ 7fde04ca2f41c580.024fb2a846425dc5.21bf9cf128c4de38.e8ee5e4d462932ac
+ c1b2430a93000000.bff0000000000000.bff0000000000000.bff0000000000000
+ bee7aec5e780eec5
+VROUNDPD_256_0x1(mem)
+ before
+ fbe8bf470a3b964c.2faa8e88af8a8189.dd4b6a41fd9ffc9e.040510833ab5f726
+ 3f500f8635106c60.d9e1505ec93405a2.23c6eb6461c60486.22606992c8aa9e11
+ 67ec1c6f830c2a2d.df095e12f0f1f458.1d4e2bfa9a4dd651.2f46d109d5ac5083
+ 4d8761ef113a8dde.9d6eb512c04e8858.a8b1a4f1c5402f2a.85034556fd474928
+ 81e3bfe4db08c7ae
+ after
+ fbe8bf470a3b964c.2faa8e88af8a8189.dd4b6a41fd9ffc9e.040510833ab5f726
+ 3f500f8635106c60.d9e1505ec93405a2.23c6eb6461c60486.22606992c8aa9e11
+ 67ec1c6f830c2a2d.df095e12f0f1f458.1d4e2bfa9a4dd651.2f46d109d5ac5083
+ fbe8bf470a3b964c.0000000000000000.dd4b6a41fd9ffc9e.0000000000000000
+ 81e3bfe4db08c7ae
+
+VROUNDPD_256_0x2(reg)
+ before
+ 80313d1f0c7904be.ceef5bf0fba751a0.6f5b52c9d3d6fe4e.a0b9d434fdaccb3e
+ dc3aba732b293d07.c6ef85605b5e319e.b01e30a3c81591e5.e23336af5e9c65b9
+ f24b334cd4a1ad33.12525a29506bea05.be014b0c39977eca.48eb464e051dbbc6
+ 1faea216a47092ef.8ce55839f3db3801.f451a070c2e901a8.afad81fe0e3a8692
+ f34461a994ff8548
+ after
+ 80313d1f0c7904be.ceef5bf0fba751a0.6f5b52c9d3d6fe4e.a0b9d434fdaccb3e
+ dc3aba732b293d07.c6ef85605b5e319e.b01e30a3c81591e5.e23336af5e9c65b9
+ f24b334cd4a1ad33.12525a29506bea05.be014b0c39977eca.48eb464e051dbbc6
+ dc3aba732b293d07.c6ef85605b5e319e.8000000000000000.e23336af5e9c65b9
+ f34461a994ff8548
+VROUNDPD_256_0x2(mem)
+ before
+ f07e643cb3797215.bdaf053d371f26e6.1174fb7b63b8d6bd.ae5a293b0096562c
+ 822505a488b20b25.299c572e283ca5c5.7dcbbddbb9118166.4768e4d98e2bb801
+ 8506c1cc2fb909a3.bfc0945313524d37.acb61c4514eff527.1dc6ccb7083364d5
+ d5ed129fc2972bbc.db66b81a95ed58e9.7a0093a58d60ee2d.8bc2dd3f0b3a9651
+ eca614df33cc8a24
+ after
+ f07e643cb3797215.bdaf053d371f26e6.1174fb7b63b8d6bd.ae5a293b0096562c
+ 822505a488b20b25.299c572e283ca5c5.7dcbbddbb9118166.4768e4d98e2bb801
+ 8506c1cc2fb909a3.bfc0945313524d37.acb61c4514eff527.1dc6ccb7083364d5
+ f07e643cb3797215.8000000000000000.3ff0000000000000.8000000000000000
+ eca614df33cc8a24
+
+VROUNDPD_256_0x2(reg)
+ before
+ 9ebf6c021b767bf8.4ea6760b605a2b9b.d9dbc0ed499a0387.c3779ee7427027a4
+ fc59e11460c4a679.ccfd68fb230ec66d.166ba73acce48abc.63e5b9f84f295db7
+ 61c06f809d404754.2bbd645b27bdb85e.ec62696cb9572835.361761c2cf994c93
+ 2b4012b46e789935.47b4e7178975bc99.b80c02efad801a9d.18d91133decbb063
+ e5f7453599cc4454
+ after
+ 9ebf6c021b767bf8.4ea6760b605a2b9b.d9dbc0ed499a0387.c3779ee7427027a4
+ fc59e11460c4a679.ccfd68fb230ec66d.166ba73acce48abc.63e5b9f84f295db7
+ 61c06f809d404754.2bbd645b27bdb85e.ec62696cb9572835.361761c2cf994c93
+ fc59e11460c4a679.ccfd68fb230ec66d.3ff0000000000000.63e5b9f84f295db7
+ e5f7453599cc4454
+VROUNDPD_256_0x2(mem)
+ before
+ 783c79b61ca7c592.b424c71b70f7d9c7.fcac6b1b64418f4b.d6b56e2f43ea9ca1
+ af762aa18268ef48.59ba88223e4a43b7.26726e54d42eed9f.a2a8aa981822e9ed
+ 656fd2e2e71c7da3.774c533375fc13b0.a1d26bacf74791c2.7733b196c7b23f2c
+ 76f4ef6568ce2cce.682724bbb1998460.4898df10e69839e0.b3a07f95ed28d80b
+ b13c10022510f035
+ after
+ 783c79b61ca7c592.b424c71b70f7d9c7.fcac6b1b64418f4b.d6b56e2f43ea9ca1
+ af762aa18268ef48.59ba88223e4a43b7.26726e54d42eed9f.a2a8aa981822e9ed
+ 656fd2e2e71c7da3.774c533375fc13b0.a1d26bacf74791c2.7733b196c7b23f2c
+ 783c79b61ca7c592.8000000000000000.fcac6b1b64418f4b.d6b56e2f43ea9ca1
+ b13c10022510f035
+
+VROUNDPD_256_0x2(reg)
+ before
+ cd5361470bf5c557.bdd1fc16208ab8f6.8a97f5278caed370.f98f446dbf2e9f24
+ 63306dd23c63911c.18d276e12c5ddc47.37e8c4e1a5c63c8e.8f8518ae9e147fba
+ cf21300e54e69132.62c3d7b2a75256ec.cc658c57966dfa66.e544d6be9e5797d0
+ 6c70a666ee0b0042.766f9d76ae76e011.a55c49f4fb304ba4.d999fa8bdb01a190
+ 4650000072205a26
+ after
+ cd5361470bf5c557.bdd1fc16208ab8f6.8a97f5278caed370.f98f446dbf2e9f24
+ 63306dd23c63911c.18d276e12c5ddc47.37e8c4e1a5c63c8e.8f8518ae9e147fba
+ cf21300e54e69132.62c3d7b2a75256ec.cc658c57966dfa66.e544d6be9e5797d0
+ 63306dd23c63911c.3ff0000000000000.3ff0000000000000.8000000000000000
+ 4650000072205a26
+VROUNDPD_256_0x2(mem)
+ before
+ 073565097fc07dbf.986acc48a65e1bfb.32a443175cd336e4.1f17f723709a68f3
+ fa13a4921cecc887.ae5b9c1f19691e07.712c4583ce77168f.94e39352933790ff
+ f9b8398768b0f5a9.098f1457e2ba4512.0ed420a41f6e3a3e.610c17ecfd94fd76
+ e2eea0d57d18c052.07522f5c9edccbc9.e7684f686bc35f1e.e2de815d4c3cec01
+ 73a5cd121cbc994f
+ after
+ 073565097fc07dbf.986acc48a65e1bfb.32a443175cd336e4.1f17f723709a68f3
+ fa13a4921cecc887.ae5b9c1f19691e07.712c4583ce77168f.94e39352933790ff
+ f9b8398768b0f5a9.098f1457e2ba4512.0ed420a41f6e3a3e.610c17ecfd94fd76
+ 3ff0000000000000.8000000000000000.3ff0000000000000.3ff0000000000000
+ 73a5cd121cbc994f
+
+VROUNDPD_256_0x3(reg)
+ before
+ 70acf575089e400a.8f8256667731e7ae.02f0e99be95ceed8.d6b44dbacf82405b
+ 3541f7f3ac701cde.dd40d528730624e8.58b43f7e5dc5e7ea.b883998667b79b20
+ 1eaecef9a5be6a79.a9f49b058ca3342c.64eb2c7299a3f5ac.6aa3acb84e6f2a9a
+ 874076f18f136684.cd6a23ebdf15d2a8.81e1ace4368352c9.c6de033ca0b5a9f4
+ a9011bfe7a96d65b
+ after
+ 70acf575089e400a.8f8256667731e7ae.02f0e99be95ceed8.d6b44dbacf82405b
+ 3541f7f3ac701cde.dd40d528730624e8.58b43f7e5dc5e7ea.b883998667b79b20
+ 1eaecef9a5be6a79.a9f49b058ca3342c.64eb2c7299a3f5ac.6aa3acb84e6f2a9a
+ 0000000000000000.dd40d528730624e8.58b43f7e5dc5e7ea.8000000000000000
+ a9011bfe7a96d65b
+VROUNDPD_256_0x3(mem)
+ before
+ f0d86febf81c6bfb.cc43eb4905fb4bae.276deac58767bc85.0ce2bb3fd2ef3bef
+ 752f7bed355625ff.4902296ca30256a1.91cb6a7ea0a6acf2.623a55ee0976ecc7
+ 15d2bcf24d4dc094.5acb2dc606b5c309.e84e210447dd5e19.dd35775f76a1a000
+ ac8cace45d0ff7e6.5be8f2c3c99fcd93.08c38a4298189027.db1e1cfdb6fe9543
+ b64340346419043f
+ after
+ f0d86febf81c6bfb.cc43eb4905fb4bae.276deac58767bc85.0ce2bb3fd2ef3bef
+ 752f7bed355625ff.4902296ca30256a1.91cb6a7ea0a6acf2.623a55ee0976ecc7
+ 15d2bcf24d4dc094.5acb2dc606b5c309.e84e210447dd5e19.dd35775f76a1a000
+ f0d86febf81c6bfb.cc43eb4905fb4bae.0000000000000000.0000000000000000
+ b64340346419043f
+
+VROUNDPD_256_0x3(reg)
+ before
+ cbeedf701c7c2c9e.172bc9b180a78720.a8a774cf894db2eb.cdf62225ae64fc47
+ 766cf61d7bb5470d.30798e44d3222c6e.9c52b056e149acbc.14b36397a6cb5fa6
+ 14097fa81d509237.d4437889718ba1fd.9536a0c46e22f7b3.b7c5cb859b5c756f
+ ff10787b9dd749c9.df55016c77eea3f9.ee9f4285cb61d17c.93fad5dca920f9cf
+ 841cfd86ed25a8f2
+ after
+ cbeedf701c7c2c9e.172bc9b180a78720.a8a774cf894db2eb.cdf62225ae64fc47
+ 766cf61d7bb5470d.30798e44d3222c6e.9c52b056e149acbc.14b36397a6cb5fa6
+ 14097fa81d509237.d4437889718ba1fd.9536a0c46e22f7b3.b7c5cb859b5c756f
+ 766cf61d7bb5470d.0000000000000000.8000000000000000.0000000000000000
+ 841cfd86ed25a8f2
+VROUNDPD_256_0x3(mem)
+ before
+ 66f8bf7182763e03.94cfdc0397d9a86e.2d7aa7d90057ee8e.02d89106959474c2
+ 155a98878520762f.2f90a8ada8dfead3.9a80e5bc28d33ee7.2f2f8ab167461d32
+ 6d0e02b6112e0ea1.2ca1d6e46b774ca4.023137010c6e4e30.d0ee27f4de040777
+ 4ae07be943acbf86.e74c64137d2c098c.415b1994c832db96.4062663a95596f3e
+ ddd742ee28d19133
+ after
+ 66f8bf7182763e03.94cfdc0397d9a86e.2d7aa7d90057ee8e.02d89106959474c2
+ 155a98878520762f.2f90a8ada8dfead3.9a80e5bc28d33ee7.2f2f8ab167461d32
+ 6d0e02b6112e0ea1.2ca1d6e46b774ca4.023137010c6e4e30.d0ee27f4de040777
+ 66f8bf7182763e03.8000000000000000.0000000000000000.0000000000000000
+ ddd742ee28d19133
+
+VROUNDPD_256_0x3(reg)
+ before
+ 0199b77e34f9a901.889b7f0c37a7480a.bcde4da8798a5f38.33c80862772da145
+ 0af4c155555cf354.030d880b072a6358.07a28e0efc1e8853.b4457f55356b5c69
+ 52335ddf2586aada.960014d2d141ce9c.24e621b1a173c18a.a09dfa5b1ff6c72c
+ 37a4868843030b3c.1f419e4eb1f94204.6ff504fd05154589.d39ef55f51dc9fbd
+ 2812ed4de628a046
+ after
+ 0199b77e34f9a901.889b7f0c37a7480a.bcde4da8798a5f38.33c80862772da145
+ 0af4c155555cf354.030d880b072a6358.07a28e0efc1e8853.b4457f55356b5c69
+ 52335ddf2586aada.960014d2d141ce9c.24e621b1a173c18a.a09dfa5b1ff6c72c
+ 0000000000000000.0000000000000000.0000000000000000.8000000000000000
+ 2812ed4de628a046
+VROUNDPD_256_0x3(mem)
+ before
+ 7dc75c10fae785f4.139138bd49605129.799ca269c25d7eba.441a325ec39151fb
+ ad87c096aa240bf2.44476fe8d329b94b.80dd9c1021793cea.ffa2a7417872218c
+ 941f94cb11ecee6d.241227777ee87f4f.10cf0830e95a39c1.fcd95f10bf45f1ea
+ 0d5b55994c49e991.103e5dd4e52bdfe0.044063b4360b316b.970b57393495fcbf
+ 2c84892674ee7fb7
+ after
+ 7dc75c10fae785f4.139138bd49605129.799ca269c25d7eba.441a325ec39151fb
+ ad87c096aa240bf2.44476fe8d329b94b.80dd9c1021793cea.ffa2a7417872218c
+ 941f94cb11ecee6d.241227777ee87f4f.10cf0830e95a39c1.fcd95f10bf45f1ea
+ 7dc75c10fae785f4.0000000000000000.799ca269c25d7eba.441a325ec39151fb
+ 2c84892674ee7fb7
+
+VROUNDPD_256_0x4(reg)
+ before
+ 168ff3451bdcb67f.f6067ded7649ba89.64160c6da57e15ab.3afa28872598df13
+ b3799101c4ecddc3.29ee8ab3acf81b82.7de830ac596b5c5b.8dcad397d20e00e6
+ 5e8f5dc60ba92f2f.84ddf7d80960c8a7.b5fec5ff9e80f19d.d87ce1cf58785010
+ 721b55008da0e96d.e2a14046aa907f25.69a5c8d10f490f1d.f9dccc1bd3e28bbc
+ cab5126760596c17
+ after
+ 168ff3451bdcb67f.f6067ded7649ba89.64160c6da57e15ab.3afa28872598df13
+ b3799101c4ecddc3.29ee8ab3acf81b82.7de830ac596b5c5b.8dcad397d20e00e6
+ 5e8f5dc60ba92f2f.84ddf7d80960c8a7.b5fec5ff9e80f19d.d87ce1cf58785010
+ 8000000000000000.0000000000000000.7de830ac596b5c5b.8000000000000000
+ cab5126760596c17
+VROUNDPD_256_0x4(mem)
+ before
+ 29d52e9f1ae8b04c.4d6a741be55c472c.1e04e2ebaa91fa27.f529348e4950f486
+ f0069db01e9c1388.4ac7b683b0698416.16d357b22571f6da.b5d605a2e724da85
+ fd15d984888050f6.c48017a48954ddd8.a4d91d87393b2e6a.05f73779854efec5
+ 2ace600972a024c3.19df94ea0da88e1d.a5e4af56fffb6002.42dac680c05c9bf3
+ c6c9af2134d9eebb
+ after
+ 29d52e9f1ae8b04c.4d6a741be55c472c.1e04e2ebaa91fa27.f529348e4950f486
+ f0069db01e9c1388.4ac7b683b0698416.16d357b22571f6da.b5d605a2e724da85
+ fd15d984888050f6.c48017a48954ddd8.a4d91d87393b2e6a.05f73779854efec5
+ 0000000000000000.4d6a741be55c472c.0000000000000000.f529348e4950f486
+ c6c9af2134d9eebb
+
+VROUNDPD_256_0x4(reg)
+ before
+ ee12edca7c5133c8.54fdad29fb084b1b.a33227c2d7f1d392.f6be8a0b95be46cf
+ 16ff7ce53451a6c7.586e3cd23cc58129.c0c3ce9684bbe7e2.71352892168f9cfd
+ 99dc58e0f9648263.10ed89ef53e2811a.cadf85d4af9307bb.f41307d79f7b20b7
+ d5f77e2666170449.5945116c5c6c081a.1fd146e7f5056fc6.5925a2c64c8d8c29
+ 7d37754c38d19d81
+ after
+ ee12edca7c5133c8.54fdad29fb084b1b.a33227c2d7f1d392.f6be8a0b95be46cf
+ 16ff7ce53451a6c7.586e3cd23cc58129.c0c3ce9684bbe7e2.71352892168f9cfd
+ 99dc58e0f9648263.10ed89ef53e2811a.cadf85d4af9307bb.f41307d79f7b20b7
+ 0000000000000000.586e3cd23cc58129.c0c3ce8000000000.71352892168f9cfd
+ 7d37754c38d19d81
+VROUNDPD_256_0x4(mem)
+ before
+ 3c14fd537f530fe8.259be82218f46825.10434f34726dd254.19e70f3af19b5ab1
+ 738ab4c93e209d8d.e5139442ab8aeaa2.0fb3bf36b2f49af4.156cda3b40e30528
+ fc6318999043049a.71ac7df1b962c56d.3361dd5b370a1e27.70aba5557d69acd7
+ b46ca4ae92c9003b.25b3a09ce10a3631.581925901dbd1719.84f16cf444b78b69
+ ae8a2985325bdd8a
+ after
+ 3c14fd537f530fe8.259be82218f46825.10434f34726dd254.19e70f3af19b5ab1
+ 738ab4c93e209d8d.e5139442ab8aeaa2.0fb3bf36b2f49af4.156cda3b40e30528
+ fc6318999043049a.71ac7df1b962c56d.3361dd5b370a1e27.70aba5557d69acd7
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ ae8a2985325bdd8a
+
+VROUNDPD_256_0x4(reg)
+ before
+ 4ac2da72e3e1dfe8.7771d4f65fbd4c9e.5c71f7adbc0d789b.5aa714c1811844f6
+ b5e57a28f2d3cd2d.213e255c142ba5ec.74358091e9f8c956.15d625db7f285fe9
+ 493e0514fbbfe205.8e9f12cccc20c754.c84a36b501556310.6573d4c832f8251e
+ 631b77a09b315c1d.9a5f1732a3a76e00.b3fb1683a2b38372.264a9d76b69452c3
+ 3427fdcf2809a201
+ after
+ 4ac2da72e3e1dfe8.7771d4f65fbd4c9e.5c71f7adbc0d789b.5aa714c1811844f6
+ b5e57a28f2d3cd2d.213e255c142ba5ec.74358091e9f8c956.15d625db7f285fe9
+ 493e0514fbbfe205.8e9f12cccc20c754.c84a36b501556310.6573d4c832f8251e
+ 8000000000000000.0000000000000000.74358091e9f8c956.0000000000000000
+ 3427fdcf2809a201
+VROUNDPD_256_0x4(mem)
+ before
+ 6bd66fc1a362d007.5fc6cd3a6db47521.214cb07bb7cc551c.93961a69689b642b
+ a7236f3744ab99ff.998c024d0ed469bc.ff305991219b39d6.c36540d1ee9b44e4
+ c4d9791d26f0b915.6db91244191d769b.10d88f61ff21d657.9eb58329d13e5d4c
+ 9ec6095f663eeb76.3799f98d2b1cd669.3010cdd86d6ae8ce.82d2dfdcac11eb0d
+ c90750561b9f2cd4
+ after
+ 6bd66fc1a362d007.5fc6cd3a6db47521.214cb07bb7cc551c.93961a69689b642b
+ a7236f3744ab99ff.998c024d0ed469bc.ff305991219b39d6.c36540d1ee9b44e4
+ c4d9791d26f0b915.6db91244191d769b.10d88f61ff21d657.9eb58329d13e5d4c
+ 6bd66fc1a362d007.5fc6cd3a6db47521.0000000000000000.8000000000000000
+ c90750561b9f2cd4
+
+VROUNDSS_0x0(reg)
+ before
+ d1a2d303bb745a4c.11b49ce91fa1ec4e.5377b493df5cc5d3.3ba48fe186802a65
+ f4ed634f271db222.f970ada86e2378c8.1da13dc3d2698185.0d60516766715948
+ 9036fca7fc256f01.32c6b8866ed24a11.f16192879fd0442a.810f8f582a4931a4
+ ffc79a75d618cf96.978239713cba2055.2b04ae4ce31c4b6e.757ec69fed126da5
+ c4797128ccdaca76
+ after
+ d1a2d303bb745a4c.11b49ce91fa1ec4e.5377b493df5cc5d3.3ba48fe186802a65
+ f4ed634f271db222.f970ada86e2378c8.1da13dc3d2698185.0d60516766715948
+ 9036fca7fc256f01.32c6b8866ed24a11.f16192879fd0442a.810f8f582a4931a4
+ 0000000000000000.0000000000000000.f16192879fd0442a.810f8f5866715948
+ c4797128ccdaca76
+VROUNDSS_0x0(mem)
+ before
+ 4acc0cdfe2ad0444.9eed39264f830c8d.066fad53f3e5b4bf.27d68e7e39dad2ff
+ e24314b04c95d63b.caf3d62706f16291.5a5b8f1aaf62c27c.41232c8a3d951487
+ 6aaa038825a0fe86.dd276ce394ee0f4f.6e105bb08d3a08b7.d43786db8cd94eb2
+ bccd57518ada3652.34d3f7c598074d73.205b8d03a97b409d.3e5d97dcc232bc2d
+ dae35bfb7a2d9aa4
+ after
+ 4acc0cdfe2ad0444.9eed39264f830c8d.066fad53f3e5b4bf.27d68e7e39dad2ff
+ e24314b04c95d63b.caf3d62706f16291.5a5b8f1aaf62c27c.41232c8a3d951487
+ 6aaa038825a0fe86.dd276ce394ee0f4f.6e105bb08d3a08b7.d43786db8cd94eb2
+ 0000000000000000.0000000000000000.f16192879fd0442a.810f8f5800000000
+ dae35bfb7a2d9aa4
+
+VROUNDSS_0x0(reg)
+ before
+ 0413cfa3505523c3.b6778bf8964e3aca.2b45733babc759a8.4b08a1fe1e30275a
+ 173aed40e1379434.33751b6a6608c81b.1ec7ddb06bba6f9a.cae3148d08657819
+ 71a4b33ec85e28a6.0e93849215149a70.6aa63090746dcaf6.7bb7619c8427f106
+ 6c9d1c09a2561dc3.259d405bc07f6df7.692e6847616ba768.38520418ad814c4f
+ df7e79eba07f451e
+ after
+ 0413cfa3505523c3.b6778bf8964e3aca.2b45733babc759a8.4b08a1fe1e30275a
+ 173aed40e1379434.33751b6a6608c81b.1ec7ddb06bba6f9a.cae3148d08657819
+ 71a4b33ec85e28a6.0e93849215149a70.6aa63090746dcaf6.7bb7619c8427f106
+ 0000000000000000.0000000000000000.6aa63090746dcaf6.7bb7619c00000000
+ df7e79eba07f451e
+VROUNDSS_0x0(mem)
+ before
+ 4a083c02782e9a9f.6670250d0aacad38.525fcdb38254fcd9.78aa8141cf40429c
+ 57bcca4a529905ff.ba6bc8b79dea15b0.73a4a685779f0544.f36877eb5979d63d
+ e0669ead49cd436a.c3d80371f69f90d8.623a48bdbc6d4264.36b247af9ba1a0f7
+ c2d234197ad50f0b.df04d1a9b2545c5b.fceb2d476dc96f65.9dd5ecfa3245dc77
+ 841d6239baefc669
+ after
+ 4a083c02782e9a9f.6670250d0aacad38.525fcdb38254fcd9.78aa8141cf40429c
+ 57bcca4a529905ff.ba6bc8b79dea15b0.73a4a685779f0544.f36877eb5979d63d
+ e0669ead49cd436a.c3d80371f69f90d8.623a48bdbc6d4264.36b247af9ba1a0f7
+ 0000000000000000.0000000000000000.6aa63090746dcaf6.7bb7619ccf40429c
+ 841d6239baefc669
+
+VROUNDSS_0x0(reg)
+ before
+ 47d6a5d7ce2e9979.dacc097900bd270f.683b2ec96c97b3e6.1e84d310a5c04a72
+ 424cb23f0a8b9252.021f97b9f89145a1.bbc9173fc1f4d125.a2d1b502805d8db8
+ d1cb83df0b94eda0.17985cc57d5e25ee.35f986764cf5f4c3.659e4f0a1bacf562
+ 4f9e16226cd4e610.f503d389ab2f8522.301979daaa28566d.43b71d1591b93e9d
+ 19e79c0dff912394
+ after
+ 47d6a5d7ce2e9979.dacc097900bd270f.683b2ec96c97b3e6.1e84d310a5c04a72
+ 424cb23f0a8b9252.021f97b9f89145a1.bbc9173fc1f4d125.a2d1b502805d8db8
+ d1cb83df0b94eda0.17985cc57d5e25ee.35f986764cf5f4c3.659e4f0a1bacf562
+ 0000000000000000.0000000000000000.35f986764cf5f4c3.659e4f0a80000000
+ 19e79c0dff912394
+VROUNDSS_0x0(mem)
+ before
+ c1fc47e0803f6174.1a126774cad7b84e.792c78f19f111f68.0a73ebd7761934cf
+ 18c09a7931d0b469.8d737041c02aa005.7ddfc8e9750fb0ed.1d54d8d94c52ca94
+ fa0011c42d4fd79e.040d2ff6eb58dae2.dee83d5d4835f4dc.c6083d4cc9615368
+ 438829ad91c88740.da2c9efde6eea191.7812553a3490a662.61db159c89d20cf9
+ 4a195c36272f31f0
+ after
+ c1fc47e0803f6174.1a126774cad7b84e.792c78f19f111f68.0a73ebd7761934cf
+ 18c09a7931d0b469.8d737041c02aa005.7ddfc8e9750fb0ed.1d54d8d94c52ca94
+ fa0011c42d4fd79e.040d2ff6eb58dae2.dee83d5d4835f4dc.c6083d4cc9615368
+ 0000000000000000.0000000000000000.35f986764cf5f4c3.659e4f0a761934cf
+ 4a195c36272f31f0
+
+VROUNDSS_0x1(reg)
+ before
+ de0e0e843f06fdfc.cf235d207848807a.6d1cbbc34e7732bd.272a8b6a562a83ab
+ 770527f46ee3adc7.7a9f2909ffda7e79.182882b5be7fc913.c7fc5cdbca1247e2
+ 724ba4f04f507dfe.20c60954418a3c69.369ded3ed293a23e.34544278ab51ad34
+ 2b2c80e67fdba94c.9d6679ee5a657775.25c8fac9273ef8eb.4afebb2c15f572cc
+ e5c642e5250a52d7
+ after
+ de0e0e843f06fdfc.cf235d207848807a.6d1cbbc34e7732bd.272a8b6a562a83ab
+ 770527f46ee3adc7.7a9f2909ffda7e79.182882b5be7fc913.c7fc5cdbca1247e2
+ 724ba4f04f507dfe.20c60954418a3c69.369ded3ed293a23e.34544278ab51ad34
+ 0000000000000000.0000000000000000.369ded3ed293a23e.34544278ca1247e4
+ e5c642e5250a52d7
+VROUNDSS_0x1(mem)
+ before
+ e177538ef69a0981.fef4b74199106c5e.cd49f6c16776ebca.3ff3a4c4590c08c5
+ 1adf6b13a5b352f5.47ef456d3a7a03df.8c3cfbbb84c95493.e26be79a03890e7a
+ 6cc804614d60eb60.626926d6fda5aa7c.b60a04c6cc6a6dfd.697bbfb7c14245b3
+ b2ff9c620aae8ded.abad57e87f1d9de0.27818dd05b66f333.2f71298730c3ea1e
+ 91972076ec963967
+ after
+ e177538ef69a0981.fef4b74199106c5e.cd49f6c16776ebca.3ff3a4c4590c08c5
+ 1adf6b13a5b352f5.47ef456d3a7a03df.8c3cfbbb84c95493.e26be79a03890e7a
+ 6cc804614d60eb60.626926d6fda5aa7c.b60a04c6cc6a6dfd.697bbfb7c14245b3
+ 0000000000000000.0000000000000000.369ded3ed293a23e.34544278590c08c5
+ 91972076ec963967
+
+VROUNDSS_0x1(reg)
+ before
+ ec3aa0f090496e3a.ca50ae03faa8f7c9.7e08d30f5b6f17b9.ba6c12c44ec9a263
+ 9aa6a562b867c442.8f87b731365ae320.37c796b72d2655b0.4d96108ec09d35b6
+ f9272b36017d782c.dd6f31d6dcd10e1d.32349c4d93cf9274.bbcc021acef0695b
+ 63092fda0616c6a3.8fd69ae0081834ed.ca9be23b26f40caf.e0da645494cefa7c
+ 978cb2282c42a345
+ after
+ ec3aa0f090496e3a.ca50ae03faa8f7c9.7e08d30f5b6f17b9.ba6c12c44ec9a263
+ 9aa6a562b867c442.8f87b731365ae320.37c796b72d2655b0.4d96108ec09d35b6
+ f9272b36017d782c.dd6f31d6dcd10e1d.32349c4d93cf9274.bbcc021acef0695b
+ 0000000000000000.0000000000000000.32349c4d93cf9274.bbcc021ac0a00000
+ 978cb2282c42a345
+VROUNDSS_0x1(mem)
+ before
+ beae6982b55822e3.3598acb864bee954.83866d3ad53c10bb.5d4a63ef8424fd0d
+ 300b044f481c3182.cb1f9e3eb6021eea.944c26cf5f475fb4.468c1bd449e8a23b
+ c870ff79039b8c4d.82eb01d7996da112.9df4428dc347dd03.e1ac065510ce36e5
+ 64aad6ee02e0f171.b449d2efa88cae78.7c4a3b5f1d4846d5.89f720e07561f7b6
+ 9cb966e0152e1f5b
+ after
+ beae6982b55822e3.3598acb864bee954.83866d3ad53c10bb.5d4a63ef8424fd0d
+ 300b044f481c3182.cb1f9e3eb6021eea.944c26cf5f475fb4.468c1bd449e8a23b
+ c870ff79039b8c4d.82eb01d7996da112.9df4428dc347dd03.e1ac065510ce36e5
+ 0000000000000000.0000000000000000.32349c4d93cf9274.bbcc021abf800000
+ 9cb966e0152e1f5b
+
+VROUNDSS_0x1(reg)
+ before
+ 753ed3c18bc0ea80.de83059860f71a1a.be830cf27fe980c7.0b198f3188545556
+ 6fd263ef74a396d0.14c809653aedc473.fce5ab4cbc1254ac.282fb9f0207ac7b1
+ e8c012d76b635df8.e0445d40abcdaaa8.cabdab69f89366d2.ad56358602c35813
+ 3a56dde30d8d7ca3.20c57d15cfa48ae7.845608b5d1f6f1e6.785b80e0493dc3a8
+ 630a15eb12f3c59b
+ after
+ 753ed3c18bc0ea80.de83059860f71a1a.be830cf27fe980c7.0b198f3188545556
+ 6fd263ef74a396d0.14c809653aedc473.fce5ab4cbc1254ac.282fb9f0207ac7b1
+ e8c012d76b635df8.e0445d40abcdaaa8.cabdab69f89366d2.ad56358602c35813
+ 0000000000000000.0000000000000000.cabdab69f89366d2.ad56358600000000
+ 630a15eb12f3c59b
+VROUNDSS_0x1(mem)
+ before
+ 4c2f6f9178f11a18.c3debf80f5ad2e7e.ae15e5d0c37c1e5a.86fbbf9de3ca3394
+ 0d960dc098447e4d.dda5b41bc04db034.6702125da364222d.2cf9cb8bc9986687
+ 830b68638df7ac64.e6f7b81f09fb3e72.28567fa88a65548d.d29c28ed1feec66c
+ 8a59fe6673176189.3820c7f76d4214e4.cbdea89d948d6ea6.d430d22e825791ee
+ 8e01c6b98d5f01ba
+ after
+ 4c2f6f9178f11a18.c3debf80f5ad2e7e.ae15e5d0c37c1e5a.86fbbf9de3ca3394
+ 0d960dc098447e4d.dda5b41bc04db034.6702125da364222d.2cf9cb8bc9986687
+ 830b68638df7ac64.e6f7b81f09fb3e72.28567fa88a65548d.d29c28ed1feec66c
+ 0000000000000000.0000000000000000.cabdab69f89366d2.ad563586e3ca3394
+ 8e01c6b98d5f01ba
+
+VROUNDSS_0x2(reg)
+ before
+ 5c5afffcdd93537c.ff4d49b568af59e9.316cde1187af6e35.2d660929dee72da3
+ 9a8979620d7ec2df.bcb3c73c85cb4fb0.2b26f8d8f4cd8712.2ab91e3683804db1
+ a3d83057baad8b90.9e57f4e7e8770109.839c11b84f289c27.9fa564b2a06289fb
+ d594204780abea3a.81054aa2adc02821.9618251d344de81f.66f45688509c9eae
+ 5c7370a3b03748f6
+ after
+ 5c5afffcdd93537c.ff4d49b568af59e9.316cde1187af6e35.2d660929dee72da3
+ 9a8979620d7ec2df.bcb3c73c85cb4fb0.2b26f8d8f4cd8712.2ab91e3683804db1
+ a3d83057baad8b90.9e57f4e7e8770109.839c11b84f289c27.9fa564b2a06289fb
+ 0000000000000000.0000000000000000.839c11b84f289c27.9fa564b280000000
+ 5c7370a3b03748f6
+VROUNDSS_0x2(mem)
+ before
+ 5dee2ef1db4142fe.8b09469ff9041b8a.41894759efb28323.bee7317340c7a9a6
+ 45310d5deec549f3.21839dc9c344592b.baae66f9ca57cc3c.58552f270f22196a
+ f00887d304d01900.f24d21327af8e1ca.c941236c5bbdc098.c0ad1da33beb7414
+ 3a3e1a403a6d6e52.5cb5ce47b9abef13.480efaa0bdef1b62.523df65463adf853
+ 6b4fb7a721f5dfd1
+ after
+ 5dee2ef1db4142fe.8b09469ff9041b8a.41894759efb28323.bee7317340c7a9a6
+ 45310d5deec549f3.21839dc9c344592b.baae66f9ca57cc3c.58552f270f22196a
+ f00887d304d01900.f24d21327af8e1ca.c941236c5bbdc098.c0ad1da33beb7414
+ 0000000000000000.0000000000000000.839c11b84f289c27.9fa564b240e00000
+ 6b4fb7a721f5dfd1
+
+VROUNDSS_0x2(reg)
+ before
+ 65305a07114d663a.ffa1428eaba80315.ba05a0721deabfb1.14e168800dfa99c7
+ 9d2ddddfd043c93c.1bfb79aa738e9574.678a942141408c51.0986e7f767e9f5f2
+ 6f903b9df9634380.6a193d81af2ae09c.c190a5bfc139939f.03c9f5f3e5c8ec10
+ 37a570ac293811b5.c8c708fd7b88a0b8.2263cfb83a621046.dd750e5fa6a43a4d
+ 7558ac27c3889ad4
+ after
+ 65305a07114d663a.ffa1428eaba80315.ba05a0721deabfb1.14e168800dfa99c7
+ 9d2ddddfd043c93c.1bfb79aa738e9574.678a942141408c51.0986e7f767e9f5f2
+ 6f903b9df9634380.6a193d81af2ae09c.c190a5bfc139939f.03c9f5f3e5c8ec10
+ 0000000000000000.0000000000000000.c190a5bfc139939f.03c9f5f367e9f5f2
+ 7558ac27c3889ad4
+VROUNDSS_0x2(mem)
+ before
+ a63c4d385a80c9d2.51ba7978fb4e6f85.11d1580cf2b590f5.e84f0e7848463ef3
+ 4cee6c7c87998372.1919516d0c31989c.2103a99830bc6d7f.6da05f6b86715a51
+ 433a85e065de83e1.eb10f3f7f76ecaa8.d328758f52a9f381.0fa1bdfd9070a00d
+ 66ec1451115b874a.23e95e8358903f52.050d3adc7489dd28.289f249a03ce4cd2
+ 15e690af7a17994d
+ after
+ a63c4d385a80c9d2.51ba7978fb4e6f85.11d1580cf2b590f5.e84f0e7848463ef3
+ 4cee6c7c87998372.1919516d0c31989c.2103a99830bc6d7f.6da05f6b86715a51
+ 433a85e065de83e1.eb10f3f7f76ecaa8.d328758f52a9f381.0fa1bdfd9070a00d
+ 0000000000000000.0000000000000000.c190a5bfc139939f.03c9f5f348463f00
+ 15e690af7a17994d
+
+VROUNDSS_0x2(reg)
+ before
+ 33c2fea692d8c42a.93cf96b9a61d49db.1cf18b7bcc243349.927f736bb067e89f
+ dc7f68ede69c0914.a5b18506402f85bd.3474784defb4e437.56489c28254fd013
+ 6d68ccee13efa3b8.785c5f23fc9df91f.c6bd1f635ccf8cc8.2c3431ffed4e50af
+ 43cb2517b45ed0c2.e79d9ffbf6745f2a.2e1a7e2bb0fe68a9.f211afdd246f26a0
+ 83aa91ace6be0c12
+ after
+ 33c2fea692d8c42a.93cf96b9a61d49db.1cf18b7bcc243349.927f736bb067e89f
+ dc7f68ede69c0914.a5b18506402f85bd.3474784defb4e437.56489c28254fd013
+ 6d68ccee13efa3b8.785c5f23fc9df91f.c6bd1f635ccf8cc8.2c3431ffed4e50af
+ 0000000000000000.0000000000000000.c6bd1f635ccf8cc8.2c3431ff3f800000
+ 83aa91ace6be0c12
+VROUNDSS_0x2(mem)
+ before
+ baca535a5148be30.b8f270d36674c9dd.d040c27c49bf740d.c8d5911085cfb386
+ 753e71d17e18fa27.292aa78ec4bdcdb5.0d114291118af3f2.ef3b527e7acdaa0a
+ 8ed267ff8b3a7a23.f2bfc8b46bc616f7.7cdb9d266be29a06.0198bfe1298589e2
+ e352b2cf94bbfb4f.6ffdceb1f61ae14f.f76c4e2873d22374.5938d3a52e828cba
+ 52678a362650ee3d
+ after
+ baca535a5148be30.b8f270d36674c9dd.d040c27c49bf740d.c8d5911085cfb386
+ 753e71d17e18fa27.292aa78ec4bdcdb5.0d114291118af3f2.ef3b527e7acdaa0a
+ 8ed267ff8b3a7a23.f2bfc8b46bc616f7.7cdb9d266be29a06.0198bfe1298589e2
+ 0000000000000000.0000000000000000.c6bd1f635ccf8cc8.2c3431ff80000000
+ 52678a362650ee3d
+
+VROUNDSS_0x3(reg)
+ before
+ 4a71e000ac7bed18.4e8acd2cb4a638d8.fc30b5f102456a69.5c8ed28143674a69
+ 9ba1d16f5d90c2f6.ad4534040808efe9.f5a37ae02ad4edf0.850ea31efaabcd10
+ a3445af0d41bac84.da516342abecdaaf.b6a417eb0a52a590.50b83fecb1ad6697
+ bca776edaea6e56d.b278d7d3b95eb555.9b7d8a7c3f4bcff6.975821d58776d227
+ 37bac5c79514ccee
+ after
+ 4a71e000ac7bed18.4e8acd2cb4a638d8.fc30b5f102456a69.5c8ed28143674a69
+ 9ba1d16f5d90c2f6.ad4534040808efe9.f5a37ae02ad4edf0.850ea31efaabcd10
+ a3445af0d41bac84.da516342abecdaaf.b6a417eb0a52a590.50b83fecb1ad6697
+ 0000000000000000.0000000000000000.b6a417eb0a52a590.50b83fecfaabcd10
+ 37bac5c79514ccee
+VROUNDSS_0x3(mem)
+ before
+ 0daaa7adf9921218.441321d486bfaa5e.12870ba14f6a3e08.007bce01644ca7ce
+ f3f34473cffd5ed1.95d75810f9f13703.d44a7b99881d2ff4.41eadfe416e068c4
+ c6621705325f6c44.0c3e150ca2c9c707.d58da3a781824544.ba16ba93f1944f83
+ 62c39c4f3fc7fa9d.069356361dd29817.f21cffb856a63c25.c74a5a7990f398b7
+ c4d4bb028f897e0d
+ after
+ 0daaa7adf9921218.441321d486bfaa5e.12870ba14f6a3e08.007bce01644ca7ce
+ f3f34473cffd5ed1.95d75810f9f13703.d44a7b99881d2ff4.41eadfe416e068c4
+ c6621705325f6c44.0c3e150ca2c9c707.d58da3a781824544.ba16ba93f1944f83
+ 0000000000000000.0000000000000000.b6a417eb0a52a590.50b83fec644ca7ce
+ c4d4bb028f897e0d
+
+VROUNDSS_0x3(reg)
+ before
+ 0dfed99a8be23f31.a4e24f3d113ec20a.dd2416f90898e3df.05c20cb72194cfc2
+ fe15b0ad1f8b15ce.668bacbbc4d281b4.ee3b52c1fca8e70a.eb4d458f0158bb48
+ f2653da7e80f3c91.858a30b5758ef3ca.962504fb978dde44.8087262e0ffebce3
+ 473a7bf581fbf226.ddaa5618407fd376.2f2e2a1174d3053b.a03d2b7f6a938dbe
+ 273bd16e2b22eb06
+ after
+ 0dfed99a8be23f31.a4e24f3d113ec20a.dd2416f90898e3df.05c20cb72194cfc2
+ fe15b0ad1f8b15ce.668bacbbc4d281b4.ee3b52c1fca8e70a.eb4d458f0158bb48
+ f2653da7e80f3c91.858a30b5758ef3ca.962504fb978dde44.8087262e0ffebce3
+ 0000000000000000.0000000000000000.962504fb978dde44.8087262e00000000
+ 273bd16e2b22eb06
+VROUNDSS_0x3(mem)
+ before
+ f14c92e770b892e6.58df660187da7138.4ab89ace40b0dee4.16a2bf7030079898
+ da3eecd655603e8b.80a2fa399538f674.a88079c5912dd042.a7ccbf8567b4d30a
+ bedb5a27f526aa21.1dcd330747a1bc85.d3ce6de8500364b9.3efa26bab466f13b
+ 79f159c76d1793d3.8aad0ed93aa20018.a76ef423983d5778.3876f17db3aa2fd7
+ ef8d1b39010bc88c
+ after
+ f14c92e770b892e6.58df660187da7138.4ab89ace40b0dee4.16a2bf7030079898
+ da3eecd655603e8b.80a2fa399538f674.a88079c5912dd042.a7ccbf8567b4d30a
+ bedb5a27f526aa21.1dcd330747a1bc85.d3ce6de8500364b9.3efa26bab466f13b
+ 0000000000000000.0000000000000000.962504fb978dde44.8087262e00000000
+ ef8d1b39010bc88c
+
+VROUNDSS_0x3(reg)
+ before
+ c08ba05a3916fa03.e74a63a0d83eb5ce.228e861a0ac7fed8.002c896186e765a9
+ 07bc7c4bf855ffeb.e4b3f6a052a7cc3d.43bc9736529af272.bad3a890350d4a78
+ 206bab7ad95714ee.4cf78db1f85f934d.47833e99aea91792.b131cd9bc2bcc113
+ 67e62a5379a574b8.fbe4a5c1e671c72a.8c2e75afbb7fabe3.c110756f480088a3
+ c63d1bf6e4e35857
+ after
+ c08ba05a3916fa03.e74a63a0d83eb5ce.228e861a0ac7fed8.002c896186e765a9
+ 07bc7c4bf855ffeb.e4b3f6a052a7cc3d.43bc9736529af272.bad3a890350d4a78
+ 206bab7ad95714ee.4cf78db1f85f934d.47833e99aea91792.b131cd9bc2bcc113
+ 0000000000000000.0000000000000000.47833e99aea91792.b131cd9b00000000
+ c63d1bf6e4e35857
+VROUNDSS_0x3(mem)
+ before
+ 9b843b1db173f059.3777f44073cd5cf7.cd45b8bb36e924ff.6c0b3ae415a9e812
+ 1eb151d1ccbc0ad5.ee6b05ae635a0854.9de5448b07d465f9.446488a456b20acb
+ 2a8fdafc50c863f8.e70e5a0ae6d8b47e.4991c41d733d4743.71865b5b1d264eb9
+ 9aec518c59a5b7ee.7eacedbe98d49b1f.ac15b45d9630860a.4dbdb0760492f088
+ 3555815fa7812ce6
+ after
+ 9b843b1db173f059.3777f44073cd5cf7.cd45b8bb36e924ff.6c0b3ae415a9e812
+ 1eb151d1ccbc0ad5.ee6b05ae635a0854.9de5448b07d465f9.446488a456b20acb
+ 2a8fdafc50c863f8.e70e5a0ae6d8b47e.4991c41d733d4743.71865b5b1d264eb9
+ 0000000000000000.0000000000000000.47833e99aea91792.b131cd9b00000000
+ 3555815fa7812ce6
+
+VROUNDSS_0x4(reg)
+ before
+ 8699cc84a37f3e7d.4c92326c045fc1e2.0f91bc3814d9fae3.a13d90378dbadd7a
+ 9ad78c50931961f9.1b4ef9886d013e01.f608c2e2f6740d77.06d5d59773e60abe
+ ce59be2f14dad207.e2ec22cbaf97ea77.8e5efb2adb301087.b6a8fe6a65c0c702
+ 7e6c5c8dc14ecc53.7f382a23e62d816f.35e0647b5f993ebe.8c83879a7e55d074
+ 6633ec15dab0e33e
+ after
+ 8699cc84a37f3e7d.4c92326c045fc1e2.0f91bc3814d9fae3.a13d90378dbadd7a
+ 9ad78c50931961f9.1b4ef9886d013e01.f608c2e2f6740d77.06d5d59773e60abe
+ ce59be2f14dad207.e2ec22cbaf97ea77.8e5efb2adb301087.b6a8fe6a65c0c702
+ 0000000000000000.0000000000000000.8e5efb2adb301087.b6a8fe6a73e60abe
+ 6633ec15dab0e33e
+VROUNDSS_0x4(mem)
+ before
+ 1e82a9c597deba8c.065c64d636028d88.ccfd8c7c2fd0be16.46d8f7411d3cd4c9
+ 923d3b98cee9128b.c375d17610814f53.a709c4c0a58b5e97.1c93b2e8b1a30e54
+ 9c2f1d799ddfa667.0f039fd9eb584e5f.ea264edc656a1d1f.155c90dcb85d270a
+ 1a26cb5420cc344b.4751cb6b6211c859.7321a7bc8a7ab6d9.8b818e89cdf35c98
+ dc4ca65c8df3e9a9
+ after
+ 1e82a9c597deba8c.065c64d636028d88.ccfd8c7c2fd0be16.46d8f7411d3cd4c9
+ 923d3b98cee9128b.c375d17610814f53.a709c4c0a58b5e97.1c93b2e8b1a30e54
+ 9c2f1d799ddfa667.0f039fd9eb584e5f.ea264edc656a1d1f.155c90dcb85d270a
+ 0000000000000000.0000000000000000.8e5efb2adb301087.b6a8fe6a00000000
+ dc4ca65c8df3e9a9
+
+VROUNDSS_0x4(reg)
+ before
+ 630bd6bf93e80aea.e6ecc11572bb7664.c7ac4f99123af7ed.1cc6494d31c6e6f2
+ 7b0819207c5ffa06.dd4f7ca8afb828dd.eb6129cd955f18c6.c3e1b27a755b6996
+ 81906be9e3e3f6aa.dc1976f9f4cf08e3.0fba54758a0b6791.423e5d2e7344fbf0
+ d2efc88865003a82.bd172df55d0dd0a2.8f04cdfb8bca1ff9.76a9c757468d572d
+ 3ced6ae00b423a78
+ after
+ 630bd6bf93e80aea.e6ecc11572bb7664.c7ac4f99123af7ed.1cc6494d31c6e6f2
+ 7b0819207c5ffa06.dd4f7ca8afb828dd.eb6129cd955f18c6.c3e1b27a755b6996
+ 81906be9e3e3f6aa.dc1976f9f4cf08e3.0fba54758a0b6791.423e5d2e7344fbf0
+ 0000000000000000.0000000000000000.0fba54758a0b6791.423e5d2e755b6996
+ 3ced6ae00b423a78
+VROUNDSS_0x4(mem)
+ before
+ 6ed7c4b5dd7060fe.c8702d689d430139.5d151d86047d3d45.c78a8ecd34287dab
+ e93350c2d82284eb.c16195f52737887c.99dec09a082c0bf9.129a955622b2bd53
+ 89cd8af31965646a.170cfc9ba0680bf7.4b40941b8325f5ea.ce7edd02f0f31b9c
+ 2a71ef34bc44b9a8.27be5ec6a463c655.500514f79174b843.5684623d3b78d232
+ 06f620739ecb1fc3
+ after
+ 6ed7c4b5dd7060fe.c8702d689d430139.5d151d86047d3d45.c78a8ecd34287dab
+ e93350c2d82284eb.c16195f52737887c.99dec09a082c0bf9.129a955622b2bd53
+ 89cd8af31965646a.170cfc9ba0680bf7.4b40941b8325f5ea.ce7edd02f0f31b9c
+ 0000000000000000.0000000000000000.0fba54758a0b6791.423e5d2e00000000
+ 06f620739ecb1fc3
+
+VROUNDSS_0x4(reg)
+ before
+ 3a211410b67b3df9.a9ebfa72dccb42d1.4dc3b8e2ceb3f442.84fabc194f251030
+ 4d5039811e116a80.e00626979506b910.e667045bbae4d26c.c3eb086dd845b8de
+ 9dd18b30731be005.ac8ff2910402db91.4cf6409e05839c7c.e9a474de48e06d79
+ 85ee068a5024dc34.e953d74a45cb6481.dcbb68154b1b8d21.d2f17d5bbd00eb2d
+ 5a9e9ecd50b3ee25
+ after
+ 3a211410b67b3df9.a9ebfa72dccb42d1.4dc3b8e2ceb3f442.84fabc194f251030
+ 4d5039811e116a80.e00626979506b910.e667045bbae4d26c.c3eb086dd845b8de
+ 9dd18b30731be005.ac8ff2910402db91.4cf6409e05839c7c.e9a474de48e06d79
+ 0000000000000000.0000000000000000.4cf6409e05839c7c.e9a474ded845b8de
+ 5a9e9ecd50b3ee25
+VROUNDSS_0x4(mem)
+ before
+ 5d7653211f04318d.60f5a7fc52b999b8.731b52b0736b100c.f204762e2738e305
+ b746194346007192.8c3068f11465553e.26b6e0aeaaf09a5e.ea1b68533567d8d4
+ 44da6a20e0b26a60.63ec47d532b44a72.deeffc300765bfa2.204d38f21233a83c
+ e0fec4a20926d823.43753f134933b4ff.77922222a5d73b04.f0e6e476592990e6
+ b632684ba7d3cd81
+ after
+ 5d7653211f04318d.60f5a7fc52b999b8.731b52b0736b100c.f204762e2738e305
+ b746194346007192.8c3068f11465553e.26b6e0aeaaf09a5e.ea1b68533567d8d4
+ 44da6a20e0b26a60.63ec47d532b44a72.deeffc300765bfa2.204d38f21233a83c
+ 0000000000000000.0000000000000000.4cf6409e05839c7c.e9a474de00000000
+ b632684ba7d3cd81
+
+VROUNDSS_0x5(reg)
+ before
+ ce7cbedd97bf98b7.677ea2b7de697606.86174d19f56dd192.cc6acf70a151c9b1
+ 9412e498c6793034.b526804a7b860135.8a1d6b52d1eedbd6.bb447e0616df26d5
+ 643ed5e8cf8ccfa6.a6c1db46fb8935dd.a9d4972b79420f78.1fecaad0208e0e9b
+ 9a4d8d394e84b2b6.151c2e997a7fcd2a.4189cc0e8af6a823.d42ed1badd693c30
+ b6d66fb1667c6ec0
+ after
+ ce7cbedd97bf98b7.677ea2b7de697606.86174d19f56dd192.cc6acf70a151c9b1
+ 9412e498c6793034.b526804a7b860135.8a1d6b52d1eedbd6.bb447e0616df26d5
+ 643ed5e8cf8ccfa6.a6c1db46fb8935dd.a9d4972b79420f78.1fecaad0208e0e9b
+ 0000000000000000.0000000000000000.a9d4972b79420f78.1fecaad000000000
+ b6d66fb1667c6ec0
+VROUNDSS_0x5(mem)
+ before
+ a0affe9fd9d45e76.928b08f8e0ed1513.e004f52e15738647.ac8606689f96e484
+ 7087fc72527cc87f.a844438f21543367.e243acf1e7711c61.471842a655acfd47
+ 0128e415ec806a06.38c4396cac44495e.f6a5cfcf0d864aa4.6f8a7a3247c62f17
+ 2e5f3274c3edfe38.9d56e6fa1d4a93a5.faf8dbb2a2bdce3b.7e2aac7a1270b8a1
+ d142d4e95134d290
+ after
+ a0affe9fd9d45e76.928b08f8e0ed1513.e004f52e15738647.ac8606689f96e484
+ 7087fc72527cc87f.a844438f21543367.e243acf1e7711c61.471842a655acfd47
+ 0128e415ec806a06.38c4396cac44495e.f6a5cfcf0d864aa4.6f8a7a3247c62f17
+ 0000000000000000.0000000000000000.a9d4972b79420f78.1fecaad080000000
+ d142d4e95134d290
+
+VROUNDSS_0x5(reg)
+ before
+ c420eceaa1a0ba91.d5f8637bf4ce4140.354846a411f14de8.c9074a87c3226253
+ b40ef1eb9d40ac50.d0bff1169b30ee4c.5be455d824c5b2d2.3e9d9a3b8bc2c217
+ fb59e057e29ee378.fd805a31d31dc285.6a771001f152ff10.378747b817a8acb4
+ f64db49a0b499cb6.360619b8b8a4791a.c04d728b14256f4e.8e91cbec82e1da55
+ 2187a4c2e8770927
+ after
+ c420eceaa1a0ba91.d5f8637bf4ce4140.354846a411f14de8.c9074a87c3226253
+ b40ef1eb9d40ac50.d0bff1169b30ee4c.5be455d824c5b2d2.3e9d9a3b8bc2c217
+ fb59e057e29ee378.fd805a31d31dc285.6a771001f152ff10.378747b817a8acb4
+ 0000000000000000.0000000000000000.6a771001f152ff10.378747b880000000
+ 2187a4c2e8770927
+VROUNDSS_0x5(mem)
+ before
+ ca354d266679f456.01356921b4ca13b6.591eaa9767cecf34.b8b277e22aca4037
+ 6767420418f0590d.785ffc567aaf8323.40958abbfba98002.adf11b73cecbac78
+ d2e8ff4819eaf279.b71567a6f98329a9.c935340e914047ae.fd585ba89db6f0bc
+ e88501de85727bc6.1aa4a87eccd241f5.ceca247e449fe165.023131ee321647b0
+ 1ac99bb22a78efff
+ after
+ ca354d266679f456.01356921b4ca13b6.591eaa9767cecf34.b8b277e22aca4037
+ 6767420418f0590d.785ffc567aaf8323.40958abbfba98002.adf11b73cecbac78
+ d2e8ff4819eaf279.b71567a6f98329a9.c935340e914047ae.fd585ba89db6f0bc
+ 0000000000000000.0000000000000000.6a771001f152ff10.378747b800000000
+ 1ac99bb22a78efff
+
+VROUNDSS_0x5(reg)
+ before
+ 9f6c955f20672256.860ac2b27994b21f.fd58ba488f2907b3.2d22d6f531d30952
+ ef661960b16f1c61.8643c0b0115d51b0.bc7d9a72df13b68e.c008c66173e77da2
+ 64022523781d1bcb.c5fc77c568d815a7.b35f4267581d8b33.644771ad26e8f780
+ 5b8eb31311fc5941.200161db9a12ba2d.3e4ab09394d1c24e.f5ac51c568e13319
+ 5003e49552deef99
+ after
+ 9f6c955f20672256.860ac2b27994b21f.fd58ba488f2907b3.2d22d6f531d30952
+ ef661960b16f1c61.8643c0b0115d51b0.bc7d9a72df13b68e.c008c66173e77da2
+ 64022523781d1bcb.c5fc77c568d815a7.b35f4267581d8b33.644771ad26e8f780
+ 0000000000000000.0000000000000000.b35f4267581d8b33.644771ad73e77da2
+ 5003e49552deef99
+VROUNDSS_0x5(mem)
+ before
+ 4f18a60902ebe52b.3154c29c1998136f.711dfce0c416fb71.b989df6232be978a
+ cfb7110d9415d2fc.40a24b2a2c7e8500.951ec2be01f0959d.7f69cb40cc6d4594
+ acaca38e23687237.e5c24b29e539eaa0.68ce32636ead44dd.ee367099fe6c0917
+ c2c2d776cbee8009.7d00bf06e0557ffd.c6fac5ba2658c35f.613ccbd965461fc0
+ 34c7d76c9c88c23b
+ after
+ 4f18a60902ebe52b.3154c29c1998136f.711dfce0c416fb71.b989df6232be978a
+ cfb7110d9415d2fc.40a24b2a2c7e8500.951ec2be01f0959d.7f69cb40cc6d4594
+ acaca38e23687237.e5c24b29e539eaa0.68ce32636ead44dd.ee367099fe6c0917
+ 0000000000000000.0000000000000000.b35f4267581d8b33.644771ad00000000
+ 34c7d76c9c88c23b
+
+VROUNDSD_0x0(reg)
+ before
+ c22390bf3fbc2f33.edc629b3a9b5b99e.62aaa22bba5f80c0.8b6ef8af46fdcf4d
+ 699bf23ceb71a255.0985152fd8c8d921.f10bf0050fe22898.93f5482ee9a824d3
+ 847dfa513c30574c.f2c918d875349bbf.866ea601796ab42f.ba5d30232b667e1e
+ 6e13a269cd8789c5.845ead999c04bca3.7d20be8a97846031.dc702c7b29439859
+ d5fcb920ff492fb2
+ after
+ c22390bf3fbc2f33.edc629b3a9b5b99e.62aaa22bba5f80c0.8b6ef8af46fdcf4d
+ 699bf23ceb71a255.0985152fd8c8d921.f10bf0050fe22898.93f5482ee9a824d3
+ 847dfa513c30574c.f2c918d875349bbf.866ea601796ab42f.ba5d30232b667e1e
+ 0000000000000000.0000000000000000.866ea601796ab42f.8000000000000000
+ d5fcb920ff492fb2
+VROUNDSD_0x0(mem)
+ before
+ 81cb51ffc886ff52.85aae8ef3b01756b.9b12505e6744f8fa.326d360b03bb684c
+ bcaa7205a105c468.238ec751212b57eb.13b07d13f5010bf0.01a109f2599c0729
+ 6265971ca4d3391e.a60a3cfa1b906af1.c803b0a45f46b0b0.460833aa36b17a77
+ 4fc73c32f0fb1ba0.686c4156c6bceb28.96d866fdc41fa567.5deeb19f3588fde0
+ a29e7d3df2adcc10
+ after
+ 81cb51ffc886ff52.85aae8ef3b01756b.9b12505e6744f8fa.326d360b03bb684c
+ bcaa7205a105c468.238ec751212b57eb.13b07d13f5010bf0.01a109f2599c0729
+ 6265971ca4d3391e.a60a3cfa1b906af1.c803b0a45f46b0b0.460833aa36b17a77
+ 0000000000000000.0000000000000000.866ea601796ab42f.0000000000000000
+ a29e7d3df2adcc10
+
+VROUNDSD_0x0(reg)
+ before
+ 716595f00bab22b4.5f9ede329f89261b.c7fed4d1bd3c163d.59fb1a0a3d99a340
+ 2690f425190e3c78.6db4f708cd8a15bb.1d0df0d89d9b27dc.ec3848b7e8bf6968
+ 1d699746ba625508.57d605a09709a5ac.c7e691d5026559b0.2d5b6cf1e19db10b
+ b23c78c18a34ab0f.f8d084e618129218.22d2b4368727e965.f72f03a243403854
+ 268287b82bb3ba6f
+ after
+ 716595f00bab22b4.5f9ede329f89261b.c7fed4d1bd3c163d.59fb1a0a3d99a340
+ 2690f425190e3c78.6db4f708cd8a15bb.1d0df0d89d9b27dc.ec3848b7e8bf6968
+ 1d699746ba625508.57d605a09709a5ac.c7e691d5026559b0.2d5b6cf1e19db10b
+ 0000000000000000.0000000000000000.c7e691d5026559b0.ec3848b7e8bf6968
+ 268287b82bb3ba6f
+VROUNDSD_0x0(mem)
+ before
+ 951e761eb402f28a.40579500240f7839.2c6eeec66db2972e.88205465c86c13a9
+ 22d04cc0fa3a9dcf.2505e9712480f933.ce7cc02db1f47218.561b6dd062c01225
+ a764838a1a66776a.bc91707f271269a9.bcc5770501e5dd03.e90efbe1f0b02388
+ 02a699682f923c88.61482796c9510646.d0178e3b788f941a.9b47fa060ec7827c
+ c91067aa5a916bae
+ after
+ 951e761eb402f28a.40579500240f7839.2c6eeec66db2972e.88205465c86c13a9
+ 22d04cc0fa3a9dcf.2505e9712480f933.ce7cc02db1f47218.561b6dd062c01225
+ a764838a1a66776a.bc91707f271269a9.bcc5770501e5dd03.e90efbe1f0b02388
+ 0000000000000000.0000000000000000.c7e691d5026559b0.8000000000000000
+ c91067aa5a916bae
+
+VROUNDSD_0x0(reg)
+ before
+ cfb63c396d9b19c9.0e62084656cba755.6f760822a5c90ab7.e83c81bc3300558a
+ 0984771fe570c97a.a6634e10ab1c75fc.4467118f5707b1a8.de01cd734d44da7e
+ d3c813c85e9cb76c.a876e7b2489262aa.3b673d497c9639c4.9032ed4be366e024
+ 89cd0da173ac1e4c.ee684d194c37298b.afc289bcaf03dcb8.d89a5c32107222a5
+ 94079913f0745e30
+ after
+ cfb63c396d9b19c9.0e62084656cba755.6f760822a5c90ab7.e83c81bc3300558a
+ 0984771fe570c97a.a6634e10ab1c75fc.4467118f5707b1a8.de01cd734d44da7e
+ d3c813c85e9cb76c.a876e7b2489262aa.3b673d497c9639c4.9032ed4be366e024
+ 0000000000000000.0000000000000000.3b673d497c9639c4.de01cd734d44da7e
+ 94079913f0745e30
+VROUNDSD_0x0(mem)
+ before
+ 9e431ddaa0794eee.87de6014c02b3cc6.5503fe2fd01a87ca.fec3ef548dd9d72f
+ d41c65733c8cae0e.2948078fe2a64b85.ba1375e2f3443893.82b76d7eb1a465d6
+ 105ceecbdfba3cba.cb57007c75a78736.f7662e1ccec3f814.99eafea4b8f1c358
+ 2fd033cca50db21f.c957474914bc2e84.e9c7a5cb80a28276.9da89e343d4b2d62
+ eb3d4a99dd3edfa0
+ after
+ 9e431ddaa0794eee.87de6014c02b3cc6.5503fe2fd01a87ca.fec3ef548dd9d72f
+ d41c65733c8cae0e.2948078fe2a64b85.ba1375e2f3443893.82b76d7eb1a465d6
+ 105ceecbdfba3cba.cb57007c75a78736.f7662e1ccec3f814.99eafea4b8f1c358
+ 0000000000000000.0000000000000000.3b673d497c9639c4.fec3ef548dd9d72f
+ eb3d4a99dd3edfa0
+
+VROUNDSD_0x1(reg)
+ before
+ e0f5fc3e335715bd.0d44b063ab94cd68.7f94d6615b717a1c.6d0157da22ee93e8
+ d61bb291db210a66.8783e27d0c5849c2.4959ab30e751a8a9.5de1bf35d2b1e794
+ 2bfd67fd7228fb47.775b4304e567e158.83f4c12153e8f3d9.963359c8acfa39a7
+ 39e517ee94f9230b.ba9651e651cc5257.89af14a23cc29855.f4c3a17fcbd2474c
+ 535d14464b47cab0
+ after
+ e0f5fc3e335715bd.0d44b063ab94cd68.7f94d6615b717a1c.6d0157da22ee93e8
+ d61bb291db210a66.8783e27d0c5849c2.4959ab30e751a8a9.5de1bf35d2b1e794
+ 2bfd67fd7228fb47.775b4304e567e158.83f4c12153e8f3d9.963359c8acfa39a7
+ 0000000000000000.0000000000000000.83f4c12153e8f3d9.5de1bf35d2b1e794
+ 535d14464b47cab0
+VROUNDSD_0x1(mem)
+ before
+ 90cd2c0a496481fe.5d20bfd1dc1fc05e.2c01870e6d9458eb.b6d7a11f3d6cd3cc
+ 85de67b5e1362663.f3fa5a10e6260ced.a968626854caae3f.68b86202f371e0e8
+ 0f5d40352ec8760b.58bee4184f9b4364.0d975ce0237a1180.fa9e55b8f95efa55
+ 0a1734744c262d21.e6ba5956b309a36f.345af362f5b03dd9.c8d575aeecbe5ec0
+ 2da8be4e671d48d5
+ after
+ 90cd2c0a496481fe.5d20bfd1dc1fc05e.2c01870e6d9458eb.b6d7a11f3d6cd3cc
+ 85de67b5e1362663.f3fa5a10e6260ced.a968626854caae3f.68b86202f371e0e8
+ 0f5d40352ec8760b.58bee4184f9b4364.0d975ce0237a1180.fa9e55b8f95efa55
+ 0000000000000000.0000000000000000.83f4c12153e8f3d9.bff0000000000000
+ 2da8be4e671d48d5
+
+VROUNDSD_0x1(reg)
+ before
+ 87642d060708f43f.52d6bd60585d07d2.fa38b534acfc66b9.fa7da2dae779ee77
+ 3056bd40670a9dab.c36659e46d77bf49.f086f520d901c9ee.3bcbe53414e1df86
+ 86c8696a23af80c5.399583eca88312b3.24ee1485d4a308bc.d311385c98f2cd31
+ e40630efd883d938.902eb764248abc3b.f2bd0ecf396e5ecc.9e1b183f90ba74a5
+ 78b500c71845900d
+ after
+ 87642d060708f43f.52d6bd60585d07d2.fa38b534acfc66b9.fa7da2dae779ee77
+ 3056bd40670a9dab.c36659e46d77bf49.f086f520d901c9ee.3bcbe53414e1df86
+ 86c8696a23af80c5.399583eca88312b3.24ee1485d4a308bc.d311385c98f2cd31
+ 0000000000000000.0000000000000000.24ee1485d4a308bc.0000000000000000
+ 78b500c71845900d
+VROUNDSD_0x1(mem)
+ before
+ 3dab6ce24b9ddc96.a55e0b3b2213e3b1.a4fc7238fe9a780f.b63edf69a5ef08cd
+ c9c9d87b45d0156c.271bf8ba9cebdbdb.50cc2e5451bf0358.ccbf83c1b3b14269
+ f8dac17e23eaf7ba.c488f1d8e295fd63.726a69a43a031945.908af743ff41474c
+ a5aba1d700f53dac.d9f2f402919f85f4.e5a29e15d4747500.5eed3659272a5523
+ 92323c70c4f8a69a
+ after
+ 3dab6ce24b9ddc96.a55e0b3b2213e3b1.a4fc7238fe9a780f.b63edf69a5ef08cd
+ c9c9d87b45d0156c.271bf8ba9cebdbdb.50cc2e5451bf0358.ccbf83c1b3b14269
+ f8dac17e23eaf7ba.c488f1d8e295fd63.726a69a43a031945.908af743ff41474c
+ 0000000000000000.0000000000000000.24ee1485d4a308bc.bff0000000000000
+ 92323c70c4f8a69a
+
+VROUNDSD_0x1(reg)
+ before
+ 88a605f57437765d.ae09f672f9ffa470.c3a5fda24494ae3b.85404a913c1ed5b5
+ 9b958e52d3740317.eebe3b3b2914e830.dced06259801b5e4.2d0fe7068d0bf391
+ 294ad2f57c3a8774.4196ed1ead3ec418.81160df82871d69a.bbddf35ee3498bc0
+ 8d13cd480b163e21.825f8607a18bf655.0f6c0d8691704c0a.0a74e9875be45b6d
+ f5a1456c11e71dc5
+ after
+ 88a605f57437765d.ae09f672f9ffa470.c3a5fda24494ae3b.85404a913c1ed5b5
+ 9b958e52d3740317.eebe3b3b2914e830.dced06259801b5e4.2d0fe7068d0bf391
+ 294ad2f57c3a8774.4196ed1ead3ec418.81160df82871d69a.bbddf35ee3498bc0
+ 0000000000000000.0000000000000000.81160df82871d69a.0000000000000000
+ f5a1456c11e71dc5
+VROUNDSD_0x1(mem)
+ before
+ 5a3083f9205e8ef4.233a7bb91d9266ca.8fe484e21f073813.e03a023a6e8b55df
+ 14ed201aa4556925.460dd8b34e3d391a.42f0629c45bc467d.51cde8825c4d2ac6
+ fea497bbbad96b85.54d6e1a239a0f4be.79509c202fb9dec0.be71bcc9f6430a6b
+ f62064c87df5503f.a8e191f27a49d362.0ed0af59f807ba08.8372787bd9f72f79
+ fd1c1a04a0f7d69d
+ after
+ 5a3083f9205e8ef4.233a7bb91d9266ca.8fe484e21f073813.e03a023a6e8b55df
+ 14ed201aa4556925.460dd8b34e3d391a.42f0629c45bc467d.51cde8825c4d2ac6
+ fea497bbbad96b85.54d6e1a239a0f4be.79509c202fb9dec0.be71bcc9f6430a6b
+ 0000000000000000.0000000000000000.81160df82871d69a.e03a023a6e8b55df
+ fd1c1a04a0f7d69d
+
+VROUNDSD_0x2(reg)
+ before
+ 86bb9ed0e7cf3b82.d62e032d0ab5d480.9d7ce40faec311b1.df3c1535bdb49780
+ 7b9afe4c4b099ad5.7c9bf1d77c26b373.91f2d665709beb58.c6604c9f99cb3054
+ 380738e268342e42.c231a8b0f053a845.de8e64615d5c9d02.a108cf83a85843b2
+ 194c47ffd9d93474.85bca6a681497022.e29e896d1092635c.4aff1bcd07688ac4
+ 9f12aa69d206c1b6
+ after
+ 86bb9ed0e7cf3b82.d62e032d0ab5d480.9d7ce40faec311b1.df3c1535bdb49780
+ 7b9afe4c4b099ad5.7c9bf1d77c26b373.91f2d665709beb58.c6604c9f99cb3054
+ 380738e268342e42.c231a8b0f053a845.de8e64615d5c9d02.a108cf83a85843b2
+ 0000000000000000.0000000000000000.de8e64615d5c9d02.c6604c9f99cb3054
+ 9f12aa69d206c1b6
+VROUNDSD_0x2(mem)
+ before
+ 7a0dfa43243fa6b5.7ab627103a86e718.a20a66a34c12c635.f76c41f726ca7811
+ b8bc8647191ef3ed.b791d48028c685d9.f3e665956cbd68ab.7b4588693a8f19ce
+ 35ebca62ceaf6589.2b294aba3e254864.551b1d67fe5310b0.c8745a31e96d823f
+ ce66437e5efeb7b6.34c9862c19306d65.a4760c051de27a6f.3c47b4bacef1ee0f
+ 3109917085a69beb
+ after
+ 7a0dfa43243fa6b5.7ab627103a86e718.a20a66a34c12c635.f76c41f726ca7811
+ b8bc8647191ef3ed.b791d48028c685d9.f3e665956cbd68ab.7b4588693a8f19ce
+ 35ebca62ceaf6589.2b294aba3e254864.551b1d67fe5310b0.c8745a31e96d823f
+ 0000000000000000.0000000000000000.de8e64615d5c9d02.f76c41f726ca7811
+ 3109917085a69beb
+
+VROUNDSD_0x2(reg)
+ before
+ 0405edbfab18c27f.5df86b89e618a79f.2dbf834155722f87.bdc3ad5be5756414
+ 1288c413dcd4a276.bf6fc06e8108ef71.72553d658c78cc77.7ace7c55741988cc
+ b5de13d8b365757c.d095bd184cdb4c58.5fd8b1045dcd7de0.b863f6dfe3d9a3c3
+ 4a53d47acc57783e.6c37df75629c797f.5094d98b61fd816f.534e96e650c17125
+ 275ad854d6ddad1d
+ after
+ 0405edbfab18c27f.5df86b89e618a79f.2dbf834155722f87.bdc3ad5be5756414
+ 1288c413dcd4a276.bf6fc06e8108ef71.72553d658c78cc77.7ace7c55741988cc
+ b5de13d8b365757c.d095bd184cdb4c58.5fd8b1045dcd7de0.b863f6dfe3d9a3c3
+ 0000000000000000.0000000000000000.5fd8b1045dcd7de0.7ace7c55741988cc
+ 275ad854d6ddad1d
+VROUNDSD_0x2(mem)
+ before
+ 10543817923a14d7.2d330566c437e768.6f21a070e0573313.a0d5b364379413d0
+ ea093219a0e46280.bac9a1063690fea6.b51f7ef5e119363f.ade63afc781f6eae
+ 914343481be55244.4e63a5c8bfeef8a3.1afcf4f082ed3e30.d2156ac0c229cfb5
+ e1cee58f1f4ba14f.434b0b16fbde120b.7a857e4ededf0612.6aac401bb13f7193
+ d3f8b778e0ec91f2
+ after
+ 10543817923a14d7.2d330566c437e768.6f21a070e0573313.a0d5b364379413d0
+ ea093219a0e46280.bac9a1063690fea6.b51f7ef5e119363f.ade63afc781f6eae
+ 914343481be55244.4e63a5c8bfeef8a3.1afcf4f082ed3e30.d2156ac0c229cfb5
+ 0000000000000000.0000000000000000.5fd8b1045dcd7de0.8000000000000000
+ d3f8b778e0ec91f2
+
+VROUNDSD_0x2(reg)
+ before
+ 6745cb45ecbc6b7e.b67896dac9210bcc.f6ced15e84eb878b.b18798f911fb4b10
+ 84df78ed703c3be4.ec0cd21534744ce7.c338f20bf9a195cf.9bccbfdf384ec957
+ 8412badc08f73cd0.5f55132c7d4f1fcd.06d56a89f38d7683.14216eea6fe43c12
+ c5298e7e5179aced.eb20d70bbfbe42aa.1bf03644113a6752.f8522108d1c75f6e
+ 232a54237a05ef97
+ after
+ 6745cb45ecbc6b7e.b67896dac9210bcc.f6ced15e84eb878b.b18798f911fb4b10
+ 84df78ed703c3be4.ec0cd21534744ce7.c338f20bf9a195cf.9bccbfdf384ec957
+ 8412badc08f73cd0.5f55132c7d4f1fcd.06d56a89f38d7683.14216eea6fe43c12
+ 0000000000000000.0000000000000000.06d56a89f38d7683.8000000000000000
+ 232a54237a05ef97
+VROUNDSD_0x2(mem)
+ before
+ 7177842987aaa7b8.a172ee3fe64fc4e8.6c39989e17ce6ea9.5ed751a8ec35a3e8
+ be032b0514c045fe.7637d88b6404c36d.be6cd5d2a08a62f7.2bd4b721220867f2
+ e59bc7a33b558394.9ec548cf6724e327.bc85079176fed8c0.de34641b4f42ef1c
+ c40bd3ef1b751ea7.76683875893c61c2.444fabc9b6378d2f.d24354030e6c7712
+ 654d8443fc143a7e
+ after
+ 7177842987aaa7b8.a172ee3fe64fc4e8.6c39989e17ce6ea9.5ed751a8ec35a3e8
+ be032b0514c045fe.7637d88b6404c36d.be6cd5d2a08a62f7.2bd4b721220867f2
+ e59bc7a33b558394.9ec548cf6724e327.bc85079176fed8c0.de34641b4f42ef1c
+ 0000000000000000.0000000000000000.06d56a89f38d7683.5ed751a8ec35a3e8
+ 654d8443fc143a7e
+
+VROUNDSD_0x3(reg)
+ before
+ f29eee49b4c5750f.361fccd5cd2ad162.5b6ca6eb69d779ec.31983e647c403d71
+ d5819080d20c646f.16a32c4270835af3.a71c8d9ba081674e.5e2a3b50e325a3b1
+ 6a446653f373434b.426271201d897383.b7c6e9f3cdc76697.a9d21e7807f37c1c
+ 0c316a30b3894d4e.942a165df34ad841.e7b4b65e8934b371.ed5c64c805b584de
+ 0594872cf9787722
+ after
+ f29eee49b4c5750f.361fccd5cd2ad162.5b6ca6eb69d779ec.31983e647c403d71
+ d5819080d20c646f.16a32c4270835af3.a71c8d9ba081674e.5e2a3b50e325a3b1
+ 6a446653f373434b.426271201d897383.b7c6e9f3cdc76697.a9d21e7807f37c1c
+ 0000000000000000.0000000000000000.b7c6e9f3cdc76697.5e2a3b50e325a3b1
+ 0594872cf9787722
+VROUNDSD_0x3(mem)
+ before
+ cf460590fe461014.19959a82acd7bf25.eac597e30bd14756.9433f14872548988
+ 253d59e0302d0ce2.ecbcf1b57debd57c.1f0071a0832a7af1.188f951d24b4268a
+ e5460008ac3927b6.e0f16b35c050cafe.0ea71e7f77622e3c.d0149d493adfc421
+ e92e74f58d751cbc.5382046f1193db57.94861c6b02841e64.180e083851619ff9
+ 4cc8cf5604c7f5bf
+ after
+ cf460590fe461014.19959a82acd7bf25.eac597e30bd14756.9433f14872548988
+ 253d59e0302d0ce2.ecbcf1b57debd57c.1f0071a0832a7af1.188f951d24b4268a
+ e5460008ac3927b6.e0f16b35c050cafe.0ea71e7f77622e3c.d0149d493adfc421
+ 0000000000000000.0000000000000000.b7c6e9f3cdc76697.8000000000000000
+ 4cc8cf5604c7f5bf
+
+VROUNDSD_0x3(reg)
+ before
+ c890f010ef9c001f.0ebf3391f0eda821.9fbab9cd0d3f4435.8e68e652409c0894
+ e8b066d0af6cfdc4.31c5b8caf0ad8711.22e484bc4fe04142.d61bf91f4eb7a6f9
+ 08752d04e0c4285a.2c0e7f8baac275b7.364d63a974030d2a.4a69cfbe48e0b4be
+ 842b41171d2fbc8f.dd6504bf39372d40.394151ff1733e59a.c41fe61c4924f010
+ 2109b9236d8e141b
+ after
+ c890f010ef9c001f.0ebf3391f0eda821.9fbab9cd0d3f4435.8e68e652409c0894
+ e8b066d0af6cfdc4.31c5b8caf0ad8711.22e484bc4fe04142.d61bf91f4eb7a6f9
+ 08752d04e0c4285a.2c0e7f8baac275b7.364d63a974030d2a.4a69cfbe48e0b4be
+ 0000000000000000.0000000000000000.364d63a974030d2a.d61bf91f4eb7a6f9
+ 2109b9236d8e141b
+VROUNDSD_0x3(mem)
+ before
+ 3ef3c4c0d12add0a.b81d9f74023af60d.1e95c454ba196cd7.850c4b29d4fc053e
+ f5a884e09004060a.009941892c701280.cc6b3a354873eea9.77f94c9549eaa8c1
+ 23f6736ec7294d46.b7e925c1365d4c96.c3b3e24eff516ee2.6c564fae0f8a0bd0
+ a4a70f5592a56cec.3b5b4688bd8ddff8.df39388bfcbfa9ad.be6d52e0c4686a16
+ ca8b5197040e0141
+ after
+ 3ef3c4c0d12add0a.b81d9f74023af60d.1e95c454ba196cd7.850c4b29d4fc053e
+ f5a884e09004060a.009941892c701280.cc6b3a354873eea9.77f94c9549eaa8c1
+ 23f6736ec7294d46.b7e925c1365d4c96.c3b3e24eff516ee2.6c564fae0f8a0bd0
+ 0000000000000000.0000000000000000.364d63a974030d2a.8000000000000000
+ ca8b5197040e0141
+
+VROUNDSD_0x3(reg)
+ before
+ edfc463f6a0a0bfa.5488d3830b822025.e739a14a5c8d0855.fdc9b8d95bca5b37
+ 810c2f4592e8c5ef.0f653be350ce241f.17d03074b0e80257.f72fdf22377d40ab
+ e307071319336bcc.b10ac4617d943506.276bf170542b0baa.aa362853ace51336
+ 6f38ca169a77383d.1743e9e9ade10f06.7258dfabe5e15dfb.f2ab0f59d70d9104
+ ab5b101ed3017640
+ after
+ edfc463f6a0a0bfa.5488d3830b822025.e739a14a5c8d0855.fdc9b8d95bca5b37
+ 810c2f4592e8c5ef.0f653be350ce241f.17d03074b0e80257.f72fdf22377d40ab
+ e307071319336bcc.b10ac4617d943506.276bf170542b0baa.aa362853ace51336
+ 0000000000000000.0000000000000000.276bf170542b0baa.f72fdf22377d40ab
+ ab5b101ed3017640
+VROUNDSD_0x3(mem)
+ before
+ b110a890bdce7e17.81ed74bbb2406aed.1bdc2667fdc06e4a.56e2f792fe9635f6
+ e096529ab17f64b4.7670026dfd1b3a88.9aa0f7c7883d0dfe.2d54338f3bd6ce46
+ 14bb8a28c920e544.a80e6f971593e7bb.6f5cd8f66b65a94f.55fb9110392e6698
+ 294acc2624bebdf3.7413b7a79934ab32.78dc46dec143fe69.29230c80942a3798
+ 0418a04be7547df1
+ after
+ b110a890bdce7e17.81ed74bbb2406aed.1bdc2667fdc06e4a.56e2f792fe9635f6
+ e096529ab17f64b4.7670026dfd1b3a88.9aa0f7c7883d0dfe.2d54338f3bd6ce46
+ 14bb8a28c920e544.a80e6f971593e7bb.6f5cd8f66b65a94f.55fb9110392e6698
+ 0000000000000000.0000000000000000.276bf170542b0baa.56e2f792fe9635f6
+ 0418a04be7547df1
+
+VROUNDSD_0x4(reg)
+ before
+ 442649ddce3a764f.fb0e9480db64a7ec.36cbd608228bc499.90ecbc6da6e3c877
+ 439804a2e6675c60.65d45f220d1e605c.4a82c9264f236b9b.9358b68d3752c2a6
+ 5fbccc06cb686cce.4568a8f8d3f9a46e.0c838a6db989dfe4.5decb02c8f9aa922
+ f2dc9d7518c8e145.7696ebef4b002e4f.d71b1749fe475a21.ca732635cbca3816
+ b6ba959407ec2daf
+ after
+ 442649ddce3a764f.fb0e9480db64a7ec.36cbd608228bc499.90ecbc6da6e3c877
+ 439804a2e6675c60.65d45f220d1e605c.4a82c9264f236b9b.9358b68d3752c2a6
+ 5fbccc06cb686cce.4568a8f8d3f9a46e.0c838a6db989dfe4.5decb02c8f9aa922
+ 0000000000000000.0000000000000000.0c838a6db989dfe4.8000000000000000
+ b6ba959407ec2daf
+VROUNDSD_0x4(mem)
+ before
+ fc8e78355e0c4218.5945735c6913f972.d42aa4f1913fbc2b.09966b27baeb19fe
+ 7ab94b04ec36347e.f1434a255bd6ee01.3bef50ecc0c3082d.fd40837188015826
+ 0b078aedce77be0d.14221f3e899cfc9d.86b36acaf597ce82.0f65599505145246
+ 8a46b2dc1fda9ef0.1f2ded1190f161f3.93406d794bc7cc55.9b51ebfdccb0440a
+ fd4f341779616a1d
+ after
+ fc8e78355e0c4218.5945735c6913f972.d42aa4f1913fbc2b.09966b27baeb19fe
+ 7ab94b04ec36347e.f1434a255bd6ee01.3bef50ecc0c3082d.fd40837188015826
+ 0b078aedce77be0d.14221f3e899cfc9d.86b36acaf597ce82.0f65599505145246
+ 0000000000000000.0000000000000000.0c838a6db989dfe4.0000000000000000
+ fd4f341779616a1d
+
+VROUNDSD_0x4(reg)
+ before
+ 90ad304ea9b4ff2c.d5413ebefc6b8e53.6eb2b00c0b6257ae.3d63d8e4de60bcd3
+ b2b5dc0ef73441e2.c7c3aa7d80374a64.5efb649a977a1b7b.5fe824f7cb6d5b27
+ beb432c3006e6aec.3b997207c749904d.49550627cfc5e906.d79bcf9e2dfa647e
+ 0ff630d960edb6f6.0f8f1346efad1a3a.8c0c911f4fd0fcfa.7f4854c521149404
+ 35ba2f58c3c6a7e4
+ after
+ 90ad304ea9b4ff2c.d5413ebefc6b8e53.6eb2b00c0b6257ae.3d63d8e4de60bcd3
+ b2b5dc0ef73441e2.c7c3aa7d80374a64.5efb649a977a1b7b.5fe824f7cb6d5b27
+ beb432c3006e6aec.3b997207c749904d.49550627cfc5e906.d79bcf9e2dfa647e
+ 0000000000000000.0000000000000000.49550627cfc5e906.5fe824f7cb6d5b27
+ 35ba2f58c3c6a7e4
+VROUNDSD_0x4(mem)
+ before
+ d3bedc442d1d594b.03c7d1bcb23d63ab.1d7107281170a558.836c01eeb5269104
+ 3721d7737e236665.f57212d892ebabb7.430bcc984b9decd3.8ac052009a54e4cf
+ 3bad9dd2cfe6895d.4045ed999d82cbc8.5b29dd82b941add6.fd5680c19ce43008
+ bc2ea94e3f727f5f.428a606c6e8efe88.4296b7d27666a28e.3878889e5764b25b
+ 977465016660a673
+ after
+ d3bedc442d1d594b.03c7d1bcb23d63ab.1d7107281170a558.836c01eeb5269104
+ 3721d7737e236665.f57212d892ebabb7.430bcc984b9decd3.8ac052009a54e4cf
+ 3bad9dd2cfe6895d.4045ed999d82cbc8.5b29dd82b941add6.fd5680c19ce43008
+ 0000000000000000.0000000000000000.49550627cfc5e906.8000000000000000
+ 977465016660a673
+
+VROUNDSD_0x4(reg)
+ before
+ 76941358656348fd.977277d2e7d20399.558e66bba29c82a3.d51fd4749e1b8726
+ 31248e0df1f9d3a4.a6448449e612d335.d69dfbf4d43691c6.ee90b2544e691acc
+ 2472d38ea5ae8415.c66f4aa1553ea95f.22031b82a0eb679d.6ab5cc5fa15e15a9
+ abc9dc461e0f97fc.d4c047c552634144.930cc3d0a34442d3.265a9e7fb40535eb
+ fc4ba4a1a36b35be
+ after
+ 76941358656348fd.977277d2e7d20399.558e66bba29c82a3.d51fd4749e1b8726
+ 31248e0df1f9d3a4.a6448449e612d335.d69dfbf4d43691c6.ee90b2544e691acc
+ 2472d38ea5ae8415.c66f4aa1553ea95f.22031b82a0eb679d.6ab5cc5fa15e15a9
+ 0000000000000000.0000000000000000.22031b82a0eb679d.ee90b2544e691acc
+ fc4ba4a1a36b35be
+VROUNDSD_0x4(mem)
+ before
+ c9535bb2889ad34e.2274a7a1f8a74804.aa03f6a1f98c5910.8703ee4c79cf5c15
+ 69403e9d82a1c9c6.e5c0300bcd03d2da.2504d32165c6abee.58359861bd18f20e
+ b8dcc94eaa89d452.4ffa71f03cad7229.218f5b32b21cf40b.63efbd7b0ca9406b
+ 92f478b01f60af20.be6b68bcde34649e.7a7008befd9af092.057b5a07011081d8
+ 98256a6f38d9f200
+ after
+ c9535bb2889ad34e.2274a7a1f8a74804.aa03f6a1f98c5910.8703ee4c79cf5c15
+ 69403e9d82a1c9c6.e5c0300bcd03d2da.2504d32165c6abee.58359861bd18f20e
+ b8dcc94eaa89d452.4ffa71f03cad7229.218f5b32b21cf40b.63efbd7b0ca9406b
+ 0000000000000000.0000000000000000.22031b82a0eb679d.8000000000000000
+ 98256a6f38d9f200
+
+VROUNDSD_0x5(reg)
+ before
+ 793be8204e8ecf90.d454c8b1fa311759.8d620fdc5121e3e5.0c7258b2624d5ab0
+ 0408d387debd5334.58c8343c5909c82c.182a64ba31022ca9.b362c6fbfc40ef91
+ 95d7240e85f2bb97.fb1b373e58f37ec3.ba0e63c419627b96.4b0dcf84e77f6b60
+ 88f5d923dfb84365.991b50a112fbf44a.d15c0664a6ce0c5a.b03ded384016894a
+ bebe9e052212067a
+ after
+ 793be8204e8ecf90.d454c8b1fa311759.8d620fdc5121e3e5.0c7258b2624d5ab0
+ 0408d387debd5334.58c8343c5909c82c.182a64ba31022ca9.b362c6fbfc40ef91
+ 95d7240e85f2bb97.fb1b373e58f37ec3.ba0e63c419627b96.4b0dcf84e77f6b60
+ 0000000000000000.0000000000000000.ba0e63c419627b96.8000000000000000
+ bebe9e052212067a
+VROUNDSD_0x5(mem)
+ before
+ 515e5dd6aa7f9e1d.39aeec31869b274b.0e92f852a42ee7ee.b75e4b0873d11a9f
+ 45e8a697f3670d5f.044e5ba41927a2f5.354dad3e299713db.ca612d1b1cf7e211
+ 7627f6341ad80e6b.452122e731e9f10f.ec18e94fbd42343d.64b1a8093ecda05d
+ c0e8c7993ade5e6e.58733b686d6c5044.0ebf2a737d3c053f.e399b83e75dd8f2f
+ a1675a265cb6ec32
+ after
+ 515e5dd6aa7f9e1d.39aeec31869b274b.0e92f852a42ee7ee.b75e4b0873d11a9f
+ 45e8a697f3670d5f.044e5ba41927a2f5.354dad3e299713db.ca612d1b1cf7e211
+ 7627f6341ad80e6b.452122e731e9f10f.ec18e94fbd42343d.64b1a8093ecda05d
+ 0000000000000000.0000000000000000.ba0e63c419627b96.8000000000000000
+ a1675a265cb6ec32
+
+VROUNDSD_0x5(reg)
+ before
+ fc65892d8fe1f313.fff797b27083b993.998fa493663cfb40.770dec958590430d
+ 4ee141bfabece07e.0f20e16cd7d5db07.64c358d2bae62db0.03d0a9a0f04aa9d4
+ f5257e484b63ee1e.cb2f22b18ce07ff5.1559539205f52340.8ed2df82da77f5c0
+ 4b7e3c350cd05a9f.11efd46faaae628b.089e9140e2f6189b.f3e009266022e1fc
+ 10c6a3789d572ab5
+ after
+ fc65892d8fe1f313.fff797b27083b993.998fa493663cfb40.770dec958590430d
+ 4ee141bfabece07e.0f20e16cd7d5db07.64c358d2bae62db0.03d0a9a0f04aa9d4
+ f5257e484b63ee1e.cb2f22b18ce07ff5.1559539205f52340.8ed2df82da77f5c0
+ 0000000000000000.0000000000000000.1559539205f52340.0000000000000000
+ 10c6a3789d572ab5
+VROUNDSD_0x5(mem)
+ before
+ c0502965ae238b17.ad3778f08ac160ae.bc2e75904d4d40f2.99de0f46ee744a6e
+ de4a18d7ae91c24d.789e2de75fc23bf7.a7b6800292c9d459.2464c812c4fbf365
+ 487febbbbaad8984.06fd5785295d2826.b05471b0952cdbe9.047eb80e0017502b
+ d9bd1efeed849ce7.b4a2f236842063e6.b2d4c486718511d1.9776dba83f559c6d
+ 38992d4b1c4014d6
+ after
+ c0502965ae238b17.ad3778f08ac160ae.bc2e75904d4d40f2.99de0f46ee744a6e
+ de4a18d7ae91c24d.789e2de75fc23bf7.a7b6800292c9d459.2464c812c4fbf365
+ 487febbbbaad8984.06fd5785295d2826.b05471b0952cdbe9.047eb80e0017502b
+ 0000000000000000.0000000000000000.1559539205f52340.8000000000000000
+ 38992d4b1c4014d6
+
+VROUNDSD_0x5(reg)
+ before
+ 4333ab633465f413.6cce2d8a6421b9a3.ded7fb660b9728e3.8802f67042dd323b
+ 1390505c234f78d0.df7f944d3a909ae3.e0e96d815b4cb2cb.10aa825a2542f954
+ 06fc18a2838adcb8.0c9cd0328bdefcd4.162444f30fce3e47.2497e43035bf2347
+ 76c3ffa1f3a35b77.d1f15c2574169aa2.ddd37c28c4a60806.a29698df8f606c41
+ 64741b514e328f6d
+ after
+ 4333ab633465f413.6cce2d8a6421b9a3.ded7fb660b9728e3.8802f67042dd323b
+ 1390505c234f78d0.df7f944d3a909ae3.e0e96d815b4cb2cb.10aa825a2542f954
+ 06fc18a2838adcb8.0c9cd0328bdefcd4.162444f30fce3e47.2497e43035bf2347
+ 0000000000000000.0000000000000000.162444f30fce3e47.0000000000000000
+ 64741b514e328f6d
+VROUNDSD_0x5(mem)
+ before
+ 48fbe7738f4049f8.c13002c60d2532bb.0849b41111453278.8f44118c15624bb2
+ 28f77a326d97560e.41901c7b6d9c9c2e.8e7254e57d767e83.89c1008c9e8d45f7
+ e1365079054172da.542f492eaf94d67c.4036b98ad4b53aef.27974492fcb33083
+ 5083e333724d5889.54598549719a1c52.f8625eed330e24e7.c512d90ccb6148ff
+ be7ebb64a522cb1a
+ after
+ 48fbe7738f4049f8.c13002c60d2532bb.0849b41111453278.8f44118c15624bb2
+ 28f77a326d97560e.41901c7b6d9c9c2e.8e7254e57d767e83.89c1008c9e8d45f7
+ e1365079054172da.542f492eaf94d67c.4036b98ad4b53aef.27974492fcb33083
+ 0000000000000000.0000000000000000.162444f30fce3e47.8000000000000000
+ be7ebb64a522cb1a
+
+VPTEST_128_1(reg)
+ before
+ 7027e7082983f37e.4fa9b04ed1c4c547.9f5acc3a4c3aaa5c.93c2bffab68ef697
+ 36595863f10efcd7.bb7534b53db4753f.8f7e1b6cdefebc45.ee22589e77406d2d
+ 6c5f09e1995224d2.70b3ea54d328239d.81106d4bc3748dba.e34da5c3953144d2
+ 6e86f9eebed8a51b.4b2f4f18ae2d8c8f.d25ebe4396285a66.4f1123572a6c39b5
+ 0e384d4452fd0600
+ after
+ 7027e7082983f37e.4fa9b04ed1c4c547.9f5acc3a4c3aaa5c.93c2bffab68ef697
+ 36595863f10efcd7.bb7534b53db4753f.8f7e1b6cdefebc45.ee22589e77406d2d
+ 6c5f09e1995224d2.70b3ea54d328239d.81106d4bc3748dba.e34da5c3953144d2
+ 6e86f9eebed8a51b.4b2f4f18ae2d8c8f.d25ebe4396285a66.4f1123572a6c39b5
+ 0000000000000000
+VPTEST_128_1(mem)
+ before
+ fc8f9f782af068e0.981a21f6fb2ebc5e.26b5ddebeace6c3e.dcb20ac0f4a45ef6
+ f6e395decd521a80.45677f65eddfa545.de1112baa4177fd9.fc594d2e7876d716
+ d6fdac62582fd90d.d3b90da82f789b7f.4f0e6972f714808a.8f9f84f9be2aff71
+ 79ac5ef0e69161b2.9d5cca295e83dbb6.557a5efd00d22c7d.efcfaa8e634a12b4
+ 7937bb5702644e8b
+ after
+ fc8f9f782af068e0.981a21f6fb2ebc5e.26b5ddebeace6c3e.dcb20ac0f4a45ef6
+ f6e395decd521a80.45677f65eddfa545.de1112baa4177fd9.fc594d2e7876d716
+ d6fdac62582fd90d.d3b90da82f789b7f.4f0e6972f714808a.8f9f84f9be2aff71
+ 79ac5ef0e69161b2.9d5cca295e83dbb6.557a5efd00d22c7d.efcfaa8e634a12b4
+ 0000000000000000
+
+VPTEST_128_1(reg)
+ before
+ 8921b4c23804eda1.bbbb297493866e9c.fe9baf55158fa197.cc1f6d49db5d3fe0
+ 7bdb8f39a0b52ca2.78f589da7c19bbf7.54c3b999f02529cd.90ca1340a3bf75dc
+ abaf4a2ad703473b.8c27f80fbd5705ee.fa21e5608cd3ae05.7d46cad0740689a0
+ 75eae000797a7918.d31df3fd714b08ad.4bff2e1685246deb.6f6110e46b3d3856
+ 42e66168a3713e2a
+ after
+ 8921b4c23804eda1.bbbb297493866e9c.fe9baf55158fa197.cc1f6d49db5d3fe0
+ 7bdb8f39a0b52ca2.78f589da7c19bbf7.54c3b999f02529cd.90ca1340a3bf75dc
+ abaf4a2ad703473b.8c27f80fbd5705ee.fa21e5608cd3ae05.7d46cad0740689a0
+ 75eae000797a7918.d31df3fd714b08ad.4bff2e1685246deb.6f6110e46b3d3856
+ 0000000000000000
+VPTEST_128_1(mem)
+ before
+ d2a0374839ad564a.35d74d2720a7ffe5.28a3f792b4018062.a5a9902676a5a22a
+ fb5c107048fd3ddf.47c48e0b6a15154d.69857fb8a3862837.626d07fefbe1886e
+ 98e667cded6eaf18.07fc9e18f350f6fc.718f085d5ae5bd58.e0969009b1645c65
+ 870ab849430b671f.d1ca78ba56e5e09f.1c8c0c6cf42afaf3.796f26b434bb5ab9
+ 8b45c5691e71be16
+ after
+ d2a0374839ad564a.35d74d2720a7ffe5.28a3f792b4018062.a5a9902676a5a22a
+ fb5c107048fd3ddf.47c48e0b6a15154d.69857fb8a3862837.626d07fefbe1886e
+ 98e667cded6eaf18.07fc9e18f350f6fc.718f085d5ae5bd58.e0969009b1645c65
+ 870ab849430b671f.d1ca78ba56e5e09f.1c8c0c6cf42afaf3.796f26b434bb5ab9
+ 0000000000000000
+
+VPTEST_128_1(reg)
+ before
+ 706469950e12c329.a3947fd166e02320.017b1b5d305f0ce2.464a09d18d629d31
+ 85180fa59e2ba69e.c84f395273fa9d48.f35b806e1c4bb970.ca937a7842986041
+ 27adb1036a47a320.d10960b7866491c3.03b6a457b63422f6.8634db4d2ed8004d
+ b06f4d1d0ff2f55c.9c8c72ebba2abdbc.8cd884869ba68220.55f9a83c6e2f3881
+ 12ad5e311da8c60a
+ after
+ 706469950e12c329.a3947fd166e02320.017b1b5d305f0ce2.464a09d18d629d31
+ 85180fa59e2ba69e.c84f395273fa9d48.f35b806e1c4bb970.ca937a7842986041
+ 27adb1036a47a320.d10960b7866491c3.03b6a457b63422f6.8634db4d2ed8004d
+ b06f4d1d0ff2f55c.9c8c72ebba2abdbc.8cd884869ba68220.55f9a83c6e2f3881
+ 0000000000000000
+VPTEST_128_1(mem)
+ before
+ 9b1e7819584f6414.7da9de5e28b9d9fd.04a5eadc2b59db60.ec0c1b66672d1599
+ cb1672de3a31ceca.eaa8613152278bb0.e4204575f6fca8db.7e9f6562b556190e
+ 7d62c86ee059c259.53b9d00428c84721.1ac9fda23720df58.9ede5fe821acc82a
+ 8fcef6b465d4faed.15262942462948fb.806c904f09cf3d03.a713046348bc5f9a
+ f78b4f3fc6111a0a
+ after
+ 9b1e7819584f6414.7da9de5e28b9d9fd.04a5eadc2b59db60.ec0c1b66672d1599
+ cb1672de3a31ceca.eaa8613152278bb0.e4204575f6fca8db.7e9f6562b556190e
+ 7d62c86ee059c259.53b9d00428c84721.1ac9fda23720df58.9ede5fe821acc82a
+ 8fcef6b465d4faed.15262942462948fb.806c904f09cf3d03.a713046348bc5f9a
+ 0000000000000000
+
+VPTEST_128_2(reg)
+ before
+ e9913fe835373425.db26799be5ac33b1.8a3b675749d5cbeb.f4d4796888177e0a
+ d873cdcb34bbea97.3f36cc117eef28d1.0f4686b0cd580c9c.50ce35dad1045e97
+ 227bf6525c27780e.95ca6b0149a9977b.009282b76d3f47bb.72273e8fffa199d6
+ 21f7b7ea4c0a1a34.baadd25764e53ad8.b96a58d9c615b7f4.34a912752ffaeaf4
+ 74212c767c1b0e1d
+ after
+ e9913fe835373425.db26799be5ac33b1.8a3b675749d5cbeb.f4d4796888177e0a
+ 0000000000000000.0000000000000000.009282b76d3f47bb.72273e8fffa199d6
+ 227bf6525c27780e.95ca6b0149a9977b.009282b76d3f47bb.72273e8fffa199d6
+ 21f7b7ea4c0a1a34.baadd25764e53ad8.b96a58d9c615b7f4.34a912752ffaeaf4
+ 0000000000000001
+VPTEST_128_2(mem)
+ before
+ 0c5a08800311c07c.33310b009ded0bb5.8bac7effeaafcd17.961b0383736799f2
+ d922227edfe7be3e.b276eeffee5e883e.e294eae5f8130e62.f3f17f1f10bf2862
+ b743f75b2daac28e.fc115d52d8e9cd7b.9c2e92f6aa1eb7e6.2c38c81b3aaba2ef
+ 838a020508658899.6b505267f9181517.9649f21c1bdb85ce.9d3cdbe28cb74146
+ a248b3e0a36e4213
+ after
+ 0c5a08800311c07c.33310b009ded0bb5.8bac7effeaafcd17.961b0383736799f2
+ 0000000000000000.0000000000000000.74538100155032e8.69e4fc7c8c98660d
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 838a020508658899.6b505267f9181517.9649f21c1bdb85ce.9d3cdbe28cb74146
+ 0000000000000040
+
+VPTEST_128_2(reg)
+ before
+ 96aa4c811a5ce001.17c3bf678c24ce8b.5c7ecba9ed799ebf.aab0864567573347
+ d7aca2318e0d58bd.50baaa6ed6f34e8f.2ce6c3844f98a11e.b52ecb5bab9d7f7c
+ c09bb15c9a0ee6f2.0a3b3f0402dfc5d2.35d53764bbff5de1.93913c4c02b9239a
+ adc3766edbeac64d.2112fb162bf3ef80.d49721b5ce3c0cb4.20a3550389b8dccd
+ 3931926c5ba46540
+ after
+ 96aa4c811a5ce001.17c3bf678c24ce8b.5c7ecba9ed799ebf.aab0864567573347
+ 0000000000000000.0000000000000000.35d53764bbff5de1.93913c4c02b9239a
+ c09bb15c9a0ee6f2.0a3b3f0402dfc5d2.35d53764bbff5de1.93913c4c02b9239a
+ adc3766edbeac64d.2112fb162bf3ef80.d49721b5ce3c0cb4.20a3550389b8dccd
+ 0000000000000001
+VPTEST_128_2(mem)
+ before
+ b8077073958c7b20.f970ecd3ec2e3479.710a59916d3c87c4.65787fe424dbeb42
+ 7af169045279da98.02ed0ff86a656b24.d7f1d55fe5c54aca.45c44c5b58663638
+ 5bbafb0bae793ed5.2388db47f01ba7f7.2d91eb6eae9af4bf.cec68487066b2942
+ 3730a174c7976203.b78b4c2e1bdd26a1.50b718a8e5c840cf.5dcc23d5cb76ff0b
+ 4e2026b04211f53f
+ after
+ b8077073958c7b20.f970ecd3ec2e3479.710a59916d3c87c4.65787fe424dbeb42
+ 0000000000000000.0000000000000000.8ef5a66e92c3783b.9a87801bdb2414bd
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 3730a174c7976203.b78b4c2e1bdd26a1.50b718a8e5c840cf.5dcc23d5cb76ff0b
+ 0000000000000040
+
+VPTEST_128_2(reg)
+ before
+ fd0f888308ca468b.ea1dd82bb6e0034d.1c435f18863622cc.1c2ed7fba65aeb26
+ c6e545bcb82d309b.504e1a1d995fdde0.adfc0f70cdb2d824.6dc4a4520b5cb1ee
+ 05ee59c6efc5ed1b.448fe5348c20ace7.c50258a48ddd8456.1e44fb9933db4e56
+ 1675c00d481ebab6.a4acb45eaa302b8f.c2a1371f6244610e.0d7958bc37e27d88
+ 153038a7367dfbb1
+ after
+ fd0f888308ca468b.ea1dd82bb6e0034d.1c435f18863622cc.1c2ed7fba65aeb26
+ 0000000000000000.0000000000000000.c50258a48ddd8456.1e44fb9933db4e56
+ 05ee59c6efc5ed1b.448fe5348c20ace7.c50258a48ddd8456.1e44fb9933db4e56
+ 1675c00d481ebab6.a4acb45eaa302b8f.c2a1371f6244610e.0d7958bc37e27d88
+ 0000000000000001
+VPTEST_128_2(mem)
+ before
+ 1235164749b984fc.55c877fd60c4d218.4b7003860f9a1704.fe24a64de773adf7
+ e0546e868ea1d496.1e317902d24472ee.15a94f98d86a2b71.d6d9a39ab8f4a1be
+ 5a59bc512141a6ab.cdfdc2893b29d6e4.de21137f20ad2502.a70a297372557c0e
+ 5e0f7d951da6b766.be784ffc36003aa5.81a5cb29046ebfe5.cb043442b0217894
+ a013c1750fe5d2fc
+ after
+ 1235164749b984fc.55c877fd60c4d218.4b7003860f9a1704.fe24a64de773adf7
+ 0000000000000000.0000000000000000.b48ffc79f065e8fb.01db59b2188c5208
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 5e0f7d951da6b766.be784ffc36003aa5.81a5cb29046ebfe5.cb043442b0217894
+ 0000000000000040
+
+VPTEST_256_1(reg)
+ before
+ 8083ca762a2cc6f1.c7442c3d9fdbc3f4.4cee1ac95f53d9de.dc01f3829fb9b644
+ c89f4db39e829020.71c24534c2ec8580.d5ab215a53b1f03b.ca0107740e9bc54b
+ d4b5459606746b35.37564468a2e6ba37.b4fa5f1daea3bb67.267184ec6c1faa27
+ 010faf8dff8d94db.f7cca5c45cd41e44.4529d07d0bb7760f.ce1ce4d6d6511f04
+ 9dd0a51f673ee00d
+ after
+ 8083ca762a2cc6f1.c7442c3d9fdbc3f4.4cee1ac95f53d9de.dc01f3829fb9b644
+ c89f4db39e829020.71c24534c2ec8580.d5ab215a53b1f03b.ca0107740e9bc54b
+ d4b5459606746b35.37564468a2e6ba37.b4fa5f1daea3bb67.267184ec6c1faa27
+ 010faf8dff8d94db.f7cca5c45cd41e44.4529d07d0bb7760f.ce1ce4d6d6511f04
+ 0000000000000000
+VPTEST_256_1(mem)
+ before
+ 6e5743b13cf1ab6f.a9fa8503245a46be.8bf0e5340bc26dd4.e38271e606785cde
+ 1f7e387a70773a56.29c2c5641265bf8c.d18e7fa4ccbd6213.ec523cc43c73aa81
+ 8a11026520db4aed.ddb36a1c643c39ee.a371ef00bbd0ba2c.bbe52f8349339ca4
+ 8ddc1c5e67299661.21197098b66bf093.df66b135f208314c.ab87458fc7446df2
+ 1a837a5455325a17
+ after
+ 6e5743b13cf1ab6f.a9fa8503245a46be.8bf0e5340bc26dd4.e38271e606785cde
+ 1f7e387a70773a56.29c2c5641265bf8c.d18e7fa4ccbd6213.ec523cc43c73aa81
+ 8a11026520db4aed.ddb36a1c643c39ee.a371ef00bbd0ba2c.bbe52f8349339ca4
+ 8ddc1c5e67299661.21197098b66bf093.df66b135f208314c.ab87458fc7446df2
+ 0000000000000000
+
+VPTEST_256_1(reg)
+ before
+ 6227cb3e8c8a9fc1.02aa0251616ddcdd.513fd442a57c2225.5f3a412d906f829f
+ e1bd33ba0bd8789a.c749302a2bb4d68e.c9739087cdfe0950.01b71cd6af136a50
+ f192ae326ba6204e.b68323d5e109409f.e5ffa2d4c97ae2c2.9faabd1a6b00a58c
+ f0f238144b82d48a.ac25553e9e79d83d.01300593357ee924.16dea0e7e041ef7e
+ 432142282ce20353
+ after
+ 6227cb3e8c8a9fc1.02aa0251616ddcdd.513fd442a57c2225.5f3a412d906f829f
+ e1bd33ba0bd8789a.c749302a2bb4d68e.c9739087cdfe0950.01b71cd6af136a50
+ f192ae326ba6204e.b68323d5e109409f.e5ffa2d4c97ae2c2.9faabd1a6b00a58c
+ f0f238144b82d48a.ac25553e9e79d83d.01300593357ee924.16dea0e7e041ef7e
+ 0000000000000000
+VPTEST_256_1(mem)
+ before
+ 003d1dc968ef9e36.3829cdcb44f7d0fa.85fb44517e0e5894.7952b532ae955925
+ 2affafb5b2757c54.27826ac2f4924f49.1ed16cfb9ed77dcf.a9b0af1cd04b6f6f
+ 9d3473db267f58d9.174b0a67f7de8e24.5172472619dd021b.ed98eebd352d67ae
+ 36a5e524df1aeff0.65cea925e867c936.fbac53c00c2ea5a3.a1546e807cc67c8f
+ 21322bd43fa3ecbe
+ after
+ 003d1dc968ef9e36.3829cdcb44f7d0fa.85fb44517e0e5894.7952b532ae955925
+ 2affafb5b2757c54.27826ac2f4924f49.1ed16cfb9ed77dcf.a9b0af1cd04b6f6f
+ 9d3473db267f58d9.174b0a67f7de8e24.5172472619dd021b.ed98eebd352d67ae
+ 36a5e524df1aeff0.65cea925e867c936.fbac53c00c2ea5a3.a1546e807cc67c8f
+ 0000000000000000
+
+VPTEST_256_1(reg)
+ before
+ c87c21221a4ff1e6.cf21827df951fdc6.6e58436863ba3c2c.f8490bb492d52094
+ f47f4dd7aa56c7b4.4573c4d291303e86.8c35d59d056222b2.2517ebedc8df301a
+ 0087aa5f8a44acd4.74662910c3c46d5d.1cb1592e6aebb873.5ce06f59c9579060
+ 47df342756a6daf1.38c82c21aa184777.7a18cd882de23a1c.7a7013e3b249fd93
+ 5b9554779ec133de
+ after
+ c87c21221a4ff1e6.cf21827df951fdc6.6e58436863ba3c2c.f8490bb492d52094
+ f47f4dd7aa56c7b4.4573c4d291303e86.8c35d59d056222b2.2517ebedc8df301a
+ 0087aa5f8a44acd4.74662910c3c46d5d.1cb1592e6aebb873.5ce06f59c9579060
+ 47df342756a6daf1.38c82c21aa184777.7a18cd882de23a1c.7a7013e3b249fd93
+ 0000000000000000
+VPTEST_256_1(mem)
+ before
+ db1aad01aaccee6e.27d5e799ac078eb8.6d634af3623888ff.03b62c18ead2e358
+ d6ca9a6ef176e96f.fbb3c02325f403d4.ef04fd710830ec22.11d673483e48f1d4
+ 287298a88fc9e10c.1ec6b92f5ff877f2.9a77c386b70d2e0b.01c59c86c4ce9d3c
+ adde219ca1d39272.ee5ad02bf69f24bd.4a8717208cdb0be7.2fcfa53d19f2263b
+ f74089d9d840c67e
+ after
+ db1aad01aaccee6e.27d5e799ac078eb8.6d634af3623888ff.03b62c18ead2e358
+ d6ca9a6ef176e96f.fbb3c02325f403d4.ef04fd710830ec22.11d673483e48f1d4
+ 287298a88fc9e10c.1ec6b92f5ff877f2.9a77c386b70d2e0b.01c59c86c4ce9d3c
+ adde219ca1d39272.ee5ad02bf69f24bd.4a8717208cdb0be7.2fcfa53d19f2263b
+ 0000000000000000
+
+VPTEST_256_2(reg)
+ before
+ b56445c59e43bab0.41dab337439fb8cc.c5bb0082857646e3.db02752aa2a43ee2
+ c587d36f06873e7e.bf32c964903a0e47.013546a0a8081b0d.29b25a9016768527
+ 83f43143ad988e94.05b2df0ea4af510f.fc139cf1fce1ddea.1064403e035d9ae3
+ 4bf85aab2e03e59d.ee2572239c0a3c4f.14a300e11c8ec923.6be4a52186633a41
+ 18fe0423ba96206e
+ after
+ b56445c59e43bab0.41dab337439fb8cc.c5bb0082857646e3.db02752aa2a43ee2
+ 83f43143ad988e94.05b2df0ea4af510f.fc139cf1fce1ddea.1064403e035d9ae3
+ 83f43143ad988e94.05b2df0ea4af510f.fc139cf1fce1ddea.1064403e035d9ae3
+ 4bf85aab2e03e59d.ee2572239c0a3c4f.14a300e11c8ec923.6be4a52186633a41
+ 0000000000000001
+VPTEST_256_2(mem)
+ before
+ f27eda32bc020a96.79e04a1426538046.5659fd8e93588d34.a32f6ddda59a1a67
+ d530a138a7b1b2e4.68f6fdeb30159b3a.1918fb3ba6a4fee9.0704df4f33910e60
+ 9cdfd72397b1d484.7686709ae8d37126.122feb16f1fa4c9b.9a6e53a46100dfbb
+ 2558f7dda90e2ea4.fede9d8feb1c3fb6.1f6a460b8e673275.b9b9c349cb72c923
+ c0302da90e730a45
+ after
+ f27eda32bc020a96.79e04a1426538046.5659fd8e93588d34.a32f6ddda59a1a67
+ 0d8125cd43fdf569.861fb5ebd9ac7fb9.a9a602716ca772cb.5cd092225a65e598
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 2558f7dda90e2ea4.fede9d8feb1c3fb6.1f6a460b8e673275.b9b9c349cb72c923
+ 0000000000000040
+
+VPTEST_256_2(reg)
+ before
+ 0c218c2fc590dccc.4b677d54f9d27a6e.5c498234d5794195.1b948a079cf66ea5
+ f7d6dd498c547c65.e9d8e673a20b750e.ec121bf74178b270.e17b31f434b4ba54
+ de9c1a62014b25bc.dd77ac26c0c5dab1.09866243cba4d0f2.4fe9b9bf74abd2b1
+ 1dbf41e6bd02157c.01104d59700b6683.11f15584108ad5c8.3fab9e5578e974e5
+ 8f8d5aa15b7a5a1f
+ after
+ 0c218c2fc590dccc.4b677d54f9d27a6e.5c498234d5794195.1b948a079cf66ea5
+ de9c1a62014b25bc.dd77ac26c0c5dab1.09866243cba4d0f2.4fe9b9bf74abd2b1
+ de9c1a62014b25bc.dd77ac26c0c5dab1.09866243cba4d0f2.4fe9b9bf74abd2b1
+ 1dbf41e6bd02157c.01104d59700b6683.11f15584108ad5c8.3fab9e5578e974e5
+ 0000000000000001
+VPTEST_256_2(mem)
+ before
+ 195b6b8e3a694189.108b4d415e048652.336e44f9cde9d5af.5f9fef26abb5fd9d
+ bbe14c0a30c2e450.134c3adf80ddb5e9.4d5f0df0f46be362.4edc2c9539b1861f
+ 4feb79005991019f.824d052dbe1addee.2dad252b009e4cc8.3cf3083d560aaaf7
+ b3446e5cd2e352a3.badba895b4463b0d.ad2507970e8dcb0c.8332808b9c4da6d4
+ 81e38ee9aa06b55f
+ after
+ 195b6b8e3a694189.108b4d415e048652.336e44f9cde9d5af.5f9fef26abb5fd9d
+ e6a49471c596be76.ef74b2bea1fb79ad.cc91bb0632162a50.a06010d9544a0262
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ b3446e5cd2e352a3.badba895b4463b0d.ad2507970e8dcb0c.8332808b9c4da6d4
+ 0000000000000040
+
+VPTEST_256_2(reg)
+ before
+ 905330c519bf1547.c1b9a80ab7c39387.15432185ffed0bf1.ab932e1e39451d5a
+ 0ece628987060036.5617a1f7233e8278.efcf6b673b9c8947.01c219ae9ed0fde0
+ 55a01ea39066b2d9.4f28d70d325ed9a2.a6cc83a903def0ba.8c804132583d29c7
+ c315627ecf6c69db.86b8c53901325530.958563b6f3407df7.2997249684955b3e
+ b2d43cc63de64f6f
+ after
+ 905330c519bf1547.c1b9a80ab7c39387.15432185ffed0bf1.ab932e1e39451d5a
+ 55a01ea39066b2d9.4f28d70d325ed9a2.a6cc83a903def0ba.8c804132583d29c7
+ 55a01ea39066b2d9.4f28d70d325ed9a2.a6cc83a903def0ba.8c804132583d29c7
+ c315627ecf6c69db.86b8c53901325530.958563b6f3407df7.2997249684955b3e
+ 0000000000000001
+VPTEST_256_2(mem)
+ before
+ 040407aea03bc386.b2782886e1a35fe9.d895e868abc3b14f.184809f9a84d6caa
+ fbf0013ac8a171b1.7f176f276197d1ae.218abb844d1fab2b.8b5f70e0bd91f97e
+ 7367a456d122161a.863c30cdebd5fad7.3d62b97b0251fdef.4a1794d6cf985f20
+ 49346eeed8cd6ded.243468e41ce81810.09ea6038e76664c7.b1bd714779efdb3b
+ 1b9b04a05821a97c
+ after
+ 040407aea03bc386.b2782886e1a35fe9.d895e868abc3b14f.184809f9a84d6caa
+ fbfbf8515fc43c79.4d87d7791e5ca016.276a1797543c4eb0.e7b7f60657b29355
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 49346eeed8cd6ded.243468e41ce81810.09ea6038e76664c7.b1bd714779efdb3b
+ 0000000000000040
+
+VTESTPS_128_1(reg)
+ before
+ e6fd484b07bb048e.5722daeff9ab3457.b34b14d8905c6504.5fee2ca717699be0
+ 6d3139b52348291f.7aff64434eca2584.90cc2f16e2be1e60.1c3a97b4af665f66
+ 0b81d34b475454d8.8e9588d8f635fd9f.1705b508ae997ecf.1c9a1f4bca6a6c85
+ 1e3b1378106bc168.6fb1c3990bf977d5.a440a21c9179c2fe.3bd93f58857f7e68
+ 55c573c7fbb4503b
+ after
+ e6fd484b07bb048e.5722daeff9ab3457.b34b14d8905c6504.5fee2ca717699be0
+ 6d3139b52348291f.7aff64434eca2584.90cc2f16e2be1e60.1c3a97b4af665f66
+ 0b81d34b475454d8.8e9588d8f635fd9f.1705b508ae997ecf.1c9a1f4bca6a6c85
+ 1e3b1378106bc168.6fb1c3990bf977d5.a440a21c9179c2fe.3bd93f58857f7e68
+ 0000000000000001
+VTESTPS_128_1(mem)
+ before
+ 4628378548129f2b.01a9f3a7191aab78.f91f9071a9215051.94caf3bc26eb2699
+ eacf087c89a72764.0f187146feed4fb7.08aa6b4eedb94440.41f0a3560a7ae64b
+ 1d86619ada7fa411.a6d488c05c6ee8cf.7820d01bf2ce0fcd.08fcae55d8b33dc1
+ ba19bec956a4d15f.20283581cf2bb46d.244b3bc4d56b6c26.453a10252d2068a6
+ 54f8c632a450a3a7
+ after
+ 4628378548129f2b.01a9f3a7191aab78.f91f9071a9215051.94caf3bc26eb2699
+ eacf087c89a72764.0f187146feed4fb7.08aa6b4eedb94440.41f0a3560a7ae64b
+ 1d86619ada7fa411.a6d488c05c6ee8cf.7820d01bf2ce0fcd.08fcae55d8b33dc1
+ ba19bec956a4d15f.20283581cf2bb46d.244b3bc4d56b6c26.453a10252d2068a6
+ 0000000000000000
+
+VTESTPS_128_1(reg)
+ before
+ 9180cae8dacc2a70.9f539bf719246b7a.db6272f5f2afed3c.eaf82936b19c1874
+ 58201ab36a2238ac.a702750f400b2d8d.31cc3d886187d0e9.a5f3155ba36ecfe6
+ 0422b1fff1dd0a08.aef0c6fde763d5c5.7fb491a6b93e991f.31087b20c6ec4da6
+ f3d38c390a89db2f.90ea0cad283a1d4d.22646abc9560838b.6a03d77236224de0
+ 2bb0a63b101d8cc1
+ after
+ 9180cae8dacc2a70.9f539bf719246b7a.db6272f5f2afed3c.eaf82936b19c1874
+ 58201ab36a2238ac.a702750f400b2d8d.31cc3d886187d0e9.a5f3155ba36ecfe6
+ 0422b1fff1dd0a08.aef0c6fde763d5c5.7fb491a6b93e991f.31087b20c6ec4da6
+ f3d38c390a89db2f.90ea0cad283a1d4d.22646abc9560838b.6a03d77236224de0
+ 0000000000000000
+VTESTPS_128_1(mem)
+ before
+ 52da626970e8c675.807fa5cb51b3e9ce.28bcc20b229cc252.7429c534927acbd9
+ ba4e89e7718fb627.0771fa2363e66e91.54326503ef937f00.d24e9d7c4b17adb4
+ 3ed897a02f1f1904.e4f786acdcafa723.ef186f81ab2d1282.9921edfe5dc364c9
+ bc440682c7a3ab38.725b45d15799cf31.d4395e7272763504.23ecb428630b2dc4
+ cdfdeb65fa7a4450
+ after
+ 52da626970e8c675.807fa5cb51b3e9ce.28bcc20b229cc252.7429c534927acbd9
+ ba4e89e7718fb627.0771fa2363e66e91.54326503ef937f00.d24e9d7c4b17adb4
+ 3ed897a02f1f1904.e4f786acdcafa723.ef186f81ab2d1282.9921edfe5dc364c9
+ bc440682c7a3ab38.725b45d15799cf31.d4395e7272763504.23ecb428630b2dc4
+ 0000000000000040
+
+VTESTPS_128_1(reg)
+ before
+ f39e8f21bd9ce519.0e5e5478552828ee.0fea340070302366.e163adc06279a4b4
+ f21c9dc849fe4bcc.12f2fb6ef4b84b53.16f04da4c401df6f.f060d85994421dbc
+ 24c310c6392bb315.a2cb7951c061d192.e2b98e29ee963ff7.dffd5c2726dd5a48
+ e6dee48729b059a0.9cb74a0bd62f76d8.d191f2fb8b7e7fac.8806b41834571885
+ c9475b17d9bb129f
+ after
+ f39e8f21bd9ce519.0e5e5478552828ee.0fea340070302366.e163adc06279a4b4
+ f21c9dc849fe4bcc.12f2fb6ef4b84b53.16f04da4c401df6f.f060d85994421dbc
+ 24c310c6392bb315.a2cb7951c061d192.e2b98e29ee963ff7.dffd5c2726dd5a48
+ e6dee48729b059a0.9cb74a0bd62f76d8.d191f2fb8b7e7fac.8806b41834571885
+ 0000000000000000
+VTESTPS_128_1(mem)
+ before
+ 7c8bd010321506c1.94bb1677b6177818.da80e889512df550.3ec476873742da37
+ 7fa08cef5a72ae18.8aa4a0037cee4e29.3af3d1b84e670b27.849d14378c708d47
+ ac500ca06dddc6d0.24e6809516c11580.96dc8082e8e97489.0169ca782893d385
+ e068cd0f88630c14.becdb19b201b09c9.cc0671d53cc0eca1.0f7593b7a738e9a0
+ 0c0b6b5fa4ea0b42
+ after
+ 7c8bd010321506c1.94bb1677b6177818.da80e889512df550.3ec476873742da37
+ 7fa08cef5a72ae18.8aa4a0037cee4e29.3af3d1b84e670b27.849d14378c708d47
+ ac500ca06dddc6d0.24e6809516c11580.96dc8082e8e97489.0169ca782893d385
+ e068cd0f88630c14.becdb19b201b09c9.cc0671d53cc0eca1.0f7593b7a738e9a0
+ 0000000000000040
+
+VTESTPS_128_2(reg)
+ before
+ 52774fdbbc357518.f8b44a29c60f3a10.b4a53080378868b0.b63f209c65f72e9c
+ 3e0739998aa663cd.ce00ffd844ed0df1.62baf7aff7946ce0.31510ac3809bf7a6
+ 2d052704abc8100e.3f1869091e0940e3.23580496facc5105.1909aa36a8b703ea
+ 79bf1488ba27b986.27c702a96e709112.55ca52a0dfbb55cc.4b347ce1f9570d94
+ a19bfcb09087d2d1
+ after
+ 52774fdbbc357518.f8b44a29c60f3a10.b4a53080378868b0.b63f209c65f72e9c
+ 0000000000000000.0000000000000000.23580496facc5105.1909aa36a8b703ea
+ 2d052704abc8100e.3f1869091e0940e3.23580496facc5105.1909aa36a8b703ea
+ 79bf1488ba27b986.27c702a96e709112.55ca52a0dfbb55cc.4b347ce1f9570d94
+ 0000000000000001
+VTESTPS_128_2(mem)
+ before
+ f80da78f89540ecd.7f7ffc91535099e2.62da48a3532dbaa9.535ddd393feeb2e1
+ 2c55f76affc97db4.9c92dc8b13ceeece.cd1eb6e2e64d78d4.795da2cdb9efa5ef
+ 193e6a2e0ef3dab1.2a44afe3962df2f5.425dc95446db86c1.23169bc9e64d6aa3
+ 9b967bc5d3dde2f0.86e1710377fae104.9e63fbe48ce3a199.acd4c69765913ca9
+ 72e31ea4cf4958ac
+ after
+ f80da78f89540ecd.7f7ffc91535099e2.62da48a3532dbaa9.535ddd393feeb2e1
+ 0000000000000000.0000000000000000.9d25b75cacd24556.aca222c6c0114d1e
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 9b967bc5d3dde2f0.86e1710377fae104.9e63fbe48ce3a199.acd4c69765913ca9
+ 0000000000000041
+
+VTESTPS_128_2(reg)
+ before
+ d08e9f5dc200fa59.8e27a71d6a93519e.0cb41e5852c0f9a6.bdfeca7ed672858b
+ 2123462cda435e5b.cebe6821ed22e3e7.180bb24fc40b7488.7bf9b10f4093eec1
+ c3ec0d7fb29dbf5f.37273cbc7b9553f7.06302a5368688f56.b41f2c81e5529767
+ 1036f2c1e79a5a10.a52d9edc2df85ef9.327081cfdb6286bb.443db7c1e2bb3dab
+ 0720cfbc52db9cb6
+ after
+ d08e9f5dc200fa59.8e27a71d6a93519e.0cb41e5852c0f9a6.bdfeca7ed672858b
+ 0000000000000000.0000000000000000.06302a5368688f56.b41f2c81e5529767
+ c3ec0d7fb29dbf5f.37273cbc7b9553f7.06302a5368688f56.b41f2c81e5529767
+ 1036f2c1e79a5a10.a52d9edc2df85ef9.327081cfdb6286bb.443db7c1e2bb3dab
+ 0000000000000001
+VTESTPS_128_2(mem)
+ before
+ d991ef5c51be70b7.664df15e14c76b1c.f49e0a6c2258bf19.f817b331b8869464
+ 965f938ffc6e74d8.1f7c04c2d5ae2d2c.0044fd5873c03484.b471bce49c5ef6fc
+ 1955373f6ff96545.99112859c7deddee.a5ecf18d3f3c7766.c2c998542278e830
+ 403e585ac46bfe2b.2e565a8f85e0b70e.bf6264f59fd945ea.7e6d44ede760a5ac
+ 44a7bb1b86a16a1b
+ after
+ d991ef5c51be70b7.664df15e14c76b1c.f49e0a6c2258bf19.f817b331b8869464
+ 0000000000000000.0000000000000000.0b61f593dda740e6.07e84cce47796b9b
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 403e585ac46bfe2b.2e565a8f85e0b70e.bf6264f59fd945ea.7e6d44ede760a5ac
+ 0000000000000040
+
+VTESTPS_128_2(reg)
+ before
+ 70c4f94b9cc7732a.e6e870cb1acefdb6.3c9895d0ac42f738.2972d17db1a2593d
+ 5e10fae7c45efc84.e71dfd7e8b301c11.1d23d689d890d817.c1e8b41291a3718b
+ 6ad7bb5d9af340d6.1eaa7a5f339d1869.2e431724a3549758.62908a9e5ae947ff
+ f0653717bb117dcc.695b645b2f1facea.cc44560fac1c70a6.e835ce0f297f97c6
+ 2ea4fc5019711f0b
+ after
+ 70c4f94b9cc7732a.e6e870cb1acefdb6.3c9895d0ac42f738.2972d17db1a2593d
+ 0000000000000000.0000000000000000.2e431724a3549758.62908a9e5ae947ff
+ 6ad7bb5d9af340d6.1eaa7a5f339d1869.2e431724a3549758.62908a9e5ae947ff
+ f0653717bb117dcc.695b645b2f1facea.cc44560fac1c70a6.e835ce0f297f97c6
+ 0000000000000001
+VTESTPS_128_2(mem)
+ before
+ 12a9904c46cc99fb.4b056a83c345ec11.a3fb355c9ac596bf.51728eb48c749eae
+ 6e1006f1cd9bc2c2.d904500c4d1acc52.a7586b4f91989015.1a18bb81e2e65e1b
+ 20a5db2ac9ea558b.f5afe51ef51c573a.533c81212fa65617.8483d9e14700ec9a
+ 03348ae457c60f82.fb50262558d7ca76.8174f3bc90faa6f2.e900e540594e84d7
+ a6d9d90ab45a617d
+ after
+ 12a9904c46cc99fb.4b056a83c345ec11.a3fb355c9ac596bf.51728eb48c749eae
+ 0000000000000000.0000000000000000.5c04caa3653a6940.ae8d714b738b6151
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 03348ae457c60f82.fb50262558d7ca76.8174f3bc90faa6f2.e900e540594e84d7
+ 0000000000000040
+
+VTESTPS_128_3(reg)
+ before
+ 175ab3abf3b3c039.f2888f09933aacd5.46340e8d11d861b1.0fcd3e0ed2a03ad1
+ 98d16f8fb3e2ddb6.cb6f66869852e8ad.34a699c2bdab5798.d710dc020ea5cfe1
+ 858907228f75f4a1.68b38c47821b7f39.1ff4c330f7dae9d7.b70c4b836214204e
+ 3acd79d123f740a6.a6217b396ea02ca3.656889435cf35319.898c067feafaeb43
+ 2b5b8ae1c161eaed
+ after
+ 175ab3abf3b3c039.f2888f09933aacd5.46340e8d11d861b1.0fcd3e0ed2a03ad1
+ 98d16f8fb3e2ddb6.cb6f66869852e8ad.34a699c2bdab5798.d710dc020ea5cfe1
+ 858907228f75f4a1.68b38c47821b7f39.1ff4c330f7dae9d7.b70c4b836214204e
+ 3acd79d123f740a6.a6217b396ea02ca3.656889435cf35319.898c067feafaeb43
+ 0000000000000000
+VTESTPS_128_3(mem)
+ before
+ 774651960357d978.13eabf060cf4fe70.6285b14677eeac18.6050e6688781d10b
+ 4a1ad988cde8760f.6c2cd82fe6f969ac.76aaa95cb910bac3.6ef6d60915119e59
+ 81a19da43b1f7bde.a1dfbdb64c91bf05.bf5ee066521214d1.e9a75594a12ef7ae
+ f6a719d76708a513.0e4f6b09da493a28.1a6bd0505b00746d.2faf5f74c86418b7
+ 9a59f11425403c1f
+ after
+ 774651960357d978.13eabf060cf4fe70.6285b14677eeac18.6050e6688781d10b
+ 4a1ad988cde8760f.6c2cd82fe6f969ac.76aaa95cb910bac3.6ef6d60915119e59
+ 81a19da43b1f7bde.a1dfbdb64c91bf05.bf5ee066521214d1.e9a75594a12ef7ae
+ f6a719d76708a513.0e4f6b09da493a28.1a6bd0505b00746d.2faf5f74c86418b7
+ 0000000000000001
+
+VTESTPS_128_3(reg)
+ before
+ 87f306e2554da093.86faca0b70afafd8.0fc7df932dab17c1.619ef706f2e796c4
+ 53c79a49f31780be.0d652a2e70215759.009514c0e046917b.71c4d07433d23802
+ 5822a9b59b2b184d.68b3b72a836a57c3.3c0306fc90a3e503.26a6d78639ce1452
+ f3503093ea14a3ec.71b1ecedc6946c42.215eb2b3d8504f04.5c13892820e6e7e1
+ f0d6614705266cda
+ after
+ 87f306e2554da093.86faca0b70afafd8.0fc7df932dab17c1.619ef706f2e796c4
+ 53c79a49f31780be.0d652a2e70215759.009514c0e046917b.71c4d07433d23802
+ 5822a9b59b2b184d.68b3b72a836a57c3.3c0306fc90a3e503.26a6d78639ce1452
+ f3503093ea14a3ec.71b1ecedc6946c42.215eb2b3d8504f04.5c13892820e6e7e1
+ 0000000000000001
+VTESTPS_128_3(mem)
+ before
+ bcbadacd049b616a.819d294d7c5e5e46.052b456254ad5101.0af2125155d80b2b
+ 9d8d73a7384f80bd.5c559250ec968508.00ed3f7549c0c32d.530b2443a2c85423
+ 6f19a5c2bd5186fe.e1c36609d64754dd.3ec35512c3da7ef1.57f5e3f35caa6899
+ 0e2bed09b0aa2e5a.6c35a2e2d7fd0672.9b780325db063e7a.74fb4bcf1e0d8039
+ 056a5941847adbae
+ after
+ bcbadacd049b616a.819d294d7c5e5e46.052b456254ad5101.0af2125155d80b2b
+ 9d8d73a7384f80bd.5c559250ec968508.00ed3f7549c0c32d.530b2443a2c85423
+ 6f19a5c2bd5186fe.e1c36609d64754dd.3ec35512c3da7ef1.57f5e3f35caa6899
+ 0e2bed09b0aa2e5a.6c35a2e2d7fd0672.9b780325db063e7a.74fb4bcf1e0d8039
+ 0000000000000041
+
+VTESTPS_128_3(reg)
+ before
+ 658e08b72b7fb3a5.568fc8682c6835fc.59f540498a45d873.f3dac59aaf50bef4
+ f2b3549cafa745ca.2310b1ca4e975711.04503ea98caa058b.22b3175e5bc5bb8a
+ 0625395cab7fcdc8.517c241d314150c5.c992976e78b8cb67.04d0765bfa70f169
+ ff30b363bb92864c.bc9d9e4df274db43.04074703ebfc64b2.75fd5d7fa85d1cbc
+ 510648b48299f7b0
+ after
+ 658e08b72b7fb3a5.568fc8682c6835fc.59f540498a45d873.f3dac59aaf50bef4
+ f2b3549cafa745ca.2310b1ca4e975711.04503ea98caa058b.22b3175e5bc5bb8a
+ 0625395cab7fcdc8.517c241d314150c5.c992976e78b8cb67.04d0765bfa70f169
+ ff30b363bb92864c.bc9d9e4df274db43.04074703ebfc64b2.75fd5d7fa85d1cbc
+ 0000000000000001
+VTESTPS_128_3(mem)
+ before
+ 73b6b3e8a42f3f70.3720bf1d7c6cae01.3f409a44ac3bb5b8.11fa4bd680010d19
+ b9db1a06292baf2a.0c4057f68a9a7e94.b83193ef7ca39a4f.4cb99e53d4540148
+ fe3ffafa2d9a0507.d8dd795a80a735b0.023c083a7db74635.118e3ce482807dea
+ 1eafceb0cd87fb36.f84321b5fa1f0d02.f92d7212cc847496.bcc621f62711bdac
+ a9ad49f65e93fd39
+ after
+ 73b6b3e8a42f3f70.3720bf1d7c6cae01.3f409a44ac3bb5b8.11fa4bd680010d19
+ b9db1a06292baf2a.0c4057f68a9a7e94.b83193ef7ca39a4f.4cb99e53d4540148
+ fe3ffafa2d9a0507.d8dd795a80a735b0.023c083a7db74635.118e3ce482807dea
+ 1eafceb0cd87fb36.f84321b5fa1f0d02.f92d7212cc847496.bcc621f62711bdac
+ 0000000000000000
+
+VTESTPS_128_3(reg)
+ before
+ 348fb14ec393783e.f4f7121424fe4ee1.c9be4974958f4336.78d04e618414e19d
+ b8b8536cf39c6b67.5ee343124f0cb934.a59aef01ec8213f7.5df01915c1754977
+ 93732dba8a3b125f.373fdb9669bcfa5c.e9230eca9c84b9f2.835a4e19a0b3674f
+ 200e3ba623fba9d3.5ad6588d8f1acb85.f2a4a23a402270d3.c5da69593dd8f852
+ 013ce7c0b3f2b8ab
+ after
+ 348fb14ec393783e.f4f7121424fe4ee1.c9be4974958f4336.78d04e618414e19d
+ b8b8536cf39c6b67.5ee343124f0cb934.a59aef01ec8213f7.5df01915c1754977
+ 93732dba8a3b125f.373fdb9669bcfa5c.e9230eca9c84b9f2.835a4e19a0b3674f
+ 200e3ba623fba9d3.5ad6588d8f1acb85.f2a4a23a402270d3.c5da69593dd8f852
+ 0000000000000000
+VTESTPS_128_3(mem)
+ before
+ 124c423c1e0d6387.bbd3779b5a686b6e.a57635e1dc33e8da.1a6aa7bd75e77545
+ d3d6f8b99b34b412.bf0fdf05cc0e95dd.f2e9ee806d120f88.bec11abfd65f03f4
+ 22a5842145736877.8a0e6e50147a63cb.1ffc00545dc3fabb.3af5f5ac0017588d
+ d987626139d63be3.771c20e8cf3710e5.067be54bc853669e.ea5236f08e9aaebc
+ 2a24d9f71c74412d
+ after
+ 124c423c1e0d6387.bbd3779b5a686b6e.a57635e1dc33e8da.1a6aa7bd75e77545
+ d3d6f8b99b34b412.bf0fdf05cc0e95dd.f2e9ee806d120f88.bec11abfd65f03f4
+ 22a5842145736877.8a0e6e50147a63cb.1ffc00545dc3fabb.3af5f5ac0017588d
+ d987626139d63be3.771c20e8cf3710e5.067be54bc853669e.ea5236f08e9aaebc
+ 0000000000000000
+
+VTESTPS_128_3(reg)
+ before
+ 56b6d82d47324f8b.d5460f66926ae882.e184f13998d2d9d7.85321b50cbcd0e5d
+ ca5631ffab5f1282.f3af061a6d3a2c7f.2694ddb00cd6fa4c.76ec1d4f823eb026
+ e24edfd7e388c7bf.0d8ec36be553c306.a096e1b7c6cfaff1.b777683408b00623
+ faebde238b37aaee.01aec24317bf6945.add7f8bc634a3372.229d76eb7932cc80
+ 942bc560f2cdc06a
+ after
+ 56b6d82d47324f8b.d5460f66926ae882.e184f13998d2d9d7.85321b50cbcd0e5d
+ ca5631ffab5f1282.f3af061a6d3a2c7f.2694ddb00cd6fa4c.76ec1d4f823eb026
+ e24edfd7e388c7bf.0d8ec36be553c306.a096e1b7c6cfaff1.b777683408b00623
+ faebde238b37aaee.01aec24317bf6945.add7f8bc634a3372.229d76eb7932cc80
+ 0000000000000040
+VTESTPS_128_3(mem)
+ before
+ eaedd0808f8f9c0d.6e792a4d40faf6bb.a9dd7f901e8cd966.a7a31e297ed2c37a
+ feaf13356b831d94.9a44bfc39d5de8d1.e2e5773d17c6d095.ec46506cb4f39bb6
+ ad3d0a6da2b6fe2c.da979af03febbcdc.889425361d780aff.d60c88f0a03af6d1
+ d36232125133fd00.8ac0b640c230ad89.78b405674dae42d0.c240c421df321178
+ 0d2fff6b0c672856
+ after
+ eaedd0808f8f9c0d.6e792a4d40faf6bb.a9dd7f901e8cd966.a7a31e297ed2c37a
+ feaf13356b831d94.9a44bfc39d5de8d1.e2e5773d17c6d095.ec46506cb4f39bb6
+ ad3d0a6da2b6fe2c.da979af03febbcdc.889425361d780aff.d60c88f0a03af6d1
+ d36232125133fd00.8ac0b640c230ad89.78b405674dae42d0.c240c421df321178
+ 0000000000000000
+
+VTESTPS_128_3(reg)
+ before
+ 1126363ac3667718.4deb06129306d43d.06090f1fc0b8f984.8c1293bcc2753533
+ 2b6f63faa1ba396a.f5a50258853b400f.aabfa2f9d810da78.a1794b2198d79f55
+ b756841742efabf7.a85aa2d042dffca1.d12e693aa3c38c12.93b7aa83ece33c61
+ 122994fe4092096c.42d76366e7fdc520.d9a2624fbf5e4dfe.3e962bccdaa2c784
+ 7ee44aea7c22fdea
+ after
+ 1126363ac3667718.4deb06129306d43d.06090f1fc0b8f984.8c1293bcc2753533
+ 2b6f63faa1ba396a.f5a50258853b400f.aabfa2f9d810da78.a1794b2198d79f55
+ b756841742efabf7.a85aa2d042dffca1.d12e693aa3c38c12.93b7aa83ece33c61
+ 122994fe4092096c.42d76366e7fdc520.d9a2624fbf5e4dfe.3e962bccdaa2c784
+ 0000000000000000
+VTESTPS_128_3(mem)
+ before
+ 2f6b83c7f16e9abe.96338f193a2e8e74.9fe7c0068fa257b7.1d6688a2c86c57e7
+ 2df8535153935a2d.a0bf71d6ca4f77bc.9b58359c56d96e93.f8c8d8a05979e77a
+ 54573573be9cf862.8c1a379f8c8200f0.12f43e1459aec5e0.c8124cb60f123862
+ 8053a5194f95318a.b690dce21d5265bb.e088575ab42e19c9.e891e24f85c2884c
+ b39195d7571511e3
+ after
+ 2f6b83c7f16e9abe.96338f193a2e8e74.9fe7c0068fa257b7.1d6688a2c86c57e7
+ 2df8535153935a2d.a0bf71d6ca4f77bc.9b58359c56d96e93.f8c8d8a05979e77a
+ 54573573be9cf862.8c1a379f8c8200f0.12f43e1459aec5e0.c8124cb60f123862
+ 8053a5194f95318a.b690dce21d5265bb.e088575ab42e19c9.e891e24f85c2884c
+ 0000000000000001
+
+VTESTPS_128_3(reg)
+ before
+ 875e61b922970fd4.8dba1f2f218bc0d1.7a6d5c0a184be1ca.e1e1fd5b8264267b
+ be44426382d5c0cb.57561fa151896362.34fdb3831afab1c8.f1c8ab01e05ca821
+ b68e3541125b5e73.baf4225bfa9bd46a.408cdeb9beea1162.ec0cdd3ae8235ae8
+ c98a35bd6eb32679.9260a34939ced014.fa65d718a1a83d44.ad780ff1b9c4f9fc
+ 12d7bd116d4b4088
+ after
+ 875e61b922970fd4.8dba1f2f218bc0d1.7a6d5c0a184be1ca.e1e1fd5b8264267b
+ be44426382d5c0cb.57561fa151896362.34fdb3831afab1c8.f1c8ab01e05ca821
+ b68e3541125b5e73.baf4225bfa9bd46a.408cdeb9beea1162.ec0cdd3ae8235ae8
+ c98a35bd6eb32679.9260a34939ced014.fa65d718a1a83d44.ad780ff1b9c4f9fc
+ 0000000000000001
+VTESTPS_128_3(mem)
+ before
+ f6f7648820c5edb9.54823e44336b5389.bb661e57292d128d.bed59c0c5ebe7019
+ 35a27f41ef3dbaba.b4c34c42fc0e234e.10d20f72e6c45800.e829280191bbe78e
+ aaa58a28f5bf64b8.43995b246629d074.6f70f3848da05b9a.d4ab7864d828de4e
+ 33cc012a4f58a6de.5e5068540d4796a9.b30b447b3accda87.dda7869fcc939006
+ 616b50200b873a62
+ after
+ f6f7648820c5edb9.54823e44336b5389.bb661e57292d128d.bed59c0c5ebe7019
+ 35a27f41ef3dbaba.b4c34c42fc0e234e.10d20f72e6c45800.e829280191bbe78e
+ aaa58a28f5bf64b8.43995b246629d074.6f70f3848da05b9a.d4ab7864d828de4e
+ 33cc012a4f58a6de.5e5068540d4796a9.b30b447b3accda87.dda7869fcc939006
+ 0000000000000001
+
+VTESTPS_128_3(reg)
+ before
+ bb42d1523191180d.abe2613118133e59.62336e408bf4b397.b7708042085490f3
+ 477705a0d93b65b4.edb5252a6dfce655.a99069537ebd61ea.596b23c513453808
+ 6057e9789f145f02.d70fc90269205afd.90b155f8822ddd4f.74c8a7f078aa8ff5
+ 642e774520a540a4.44bdc9a3298a587e.73e32f9d32d16272.e3538aaf538f50e4
+ 84d846eebf013802
+ after
+ bb42d1523191180d.abe2613118133e59.62336e408bf4b397.b7708042085490f3
+ 477705a0d93b65b4.edb5252a6dfce655.a99069537ebd61ea.596b23c513453808
+ 6057e9789f145f02.d70fc90269205afd.90b155f8822ddd4f.74c8a7f078aa8ff5
+ 642e774520a540a4.44bdc9a3298a587e.73e32f9d32d16272.e3538aaf538f50e4
+ 0000000000000040
+VTESTPS_128_3(mem)
+ before
+ 31225a99d80b037a.ae48ad73f77c4445.0f8ca1fbc8469a04.ae72f2ad2b332efe
+ c8ff3f9cbbba6d79.99f1866ec124a992.1645cef56361ddba.9eaa9a9408e17ba0
+ 233972e48319322a.8375ffa3192aa937.33b7cb7d15e6dccd.9dd723bf66678603
+ 1f9d705b4d340dba.c61f127c9c1981df.43ad147ffae25568.08448998e04f8ad4
+ 3b3fc98c1228c4bf
+ after
+ 31225a99d80b037a.ae48ad73f77c4445.0f8ca1fbc8469a04.ae72f2ad2b332efe
+ c8ff3f9cbbba6d79.99f1866ec124a992.1645cef56361ddba.9eaa9a9408e17ba0
+ 233972e48319322a.8375ffa3192aa937.33b7cb7d15e6dccd.9dd723bf66678603
+ 1f9d705b4d340dba.c61f127c9c1981df.43ad147ffae25568.08448998e04f8ad4
+ 0000000000000000
+
+VTESTPS_128_3(reg)
+ before
+ 9212de08997b706f.99f7b4ef3417bb55.c03cbd66e57d6c37.23f225e72f6002b8
+ 690ac47611d6ca91.6b12ba8a55cff726.cb18fbce91e3a8eb.ad547ba1d06c9fe8
+ 1c73774414c40dd0.72bcfe1acb677e5a.45ffc81f3bd66fa6.be9d9199f712ea25
+ 0798f4dd41d176d9.8bbffd8ab3ec0d1d.883d20c480e2fd15.339ae3bbc35f9d9b
+ e616edf44e5e7575
+ after
+ 9212de08997b706f.99f7b4ef3417bb55.c03cbd66e57d6c37.23f225e72f6002b8
+ 690ac47611d6ca91.6b12ba8a55cff726.cb18fbce91e3a8eb.ad547ba1d06c9fe8
+ 1c73774414c40dd0.72bcfe1acb677e5a.45ffc81f3bd66fa6.be9d9199f712ea25
+ 0798f4dd41d176d9.8bbffd8ab3ec0d1d.883d20c480e2fd15.339ae3bbc35f9d9b
+ 0000000000000000
+VTESTPS_128_3(mem)
+ before
+ b4df2b2eb41c2de0.85c735ad328a4158.90e932c628685d9a.f21e002bfb9490e3
+ 79c01a5712a48307.f44a3820837aaaf8.5e0419ba46ea2dfd.dded63bf487762bd
+ 1284355983023117.af6ff8a2d12eec65.d1dd2e522a7b3774.a6f845ec0517b04e
+ 59f8f8222442f43c.1280729fb731444d.c63fee7af0293828.aa89a21ecb01b543
+ 43ed77c138c0af48
+ after
+ b4df2b2eb41c2de0.85c735ad328a4158.90e932c628685d9a.f21e002bfb9490e3
+ 79c01a5712a48307.f44a3820837aaaf8.5e0419ba46ea2dfd.dded63bf487762bd
+ 1284355983023117.af6ff8a2d12eec65.d1dd2e522a7b3774.a6f845ec0517b04e
+ 59f8f8222442f43c.1280729fb731444d.c63fee7af0293828.aa89a21ecb01b543
+ 0000000000000001
+
+VTESTPS_128_3(reg)
+ before
+ ce70be42e7e0d808.2be8df9d107187a1.79caa083d20fee5a.17f8d31fb3ffeb48
+ a75d750b75ee6d30.642067b6649ba773.3f9880babd542538.a1d25b2b8f0a0efe
+ 2b0298897e75a96b.e06c0a593bca10dd.c2380db1158d2694.409b018ca1555b76
+ b4a921299d01c966.7b974672b20c7e0c.5df544d275452d1a.d01d422c05ec8fde
+ 2d2598f9d5dc655f
+ after
+ ce70be42e7e0d808.2be8df9d107187a1.79caa083d20fee5a.17f8d31fb3ffeb48
+ a75d750b75ee6d30.642067b6649ba773.3f9880babd542538.a1d25b2b8f0a0efe
+ 2b0298897e75a96b.e06c0a593bca10dd.c2380db1158d2694.409b018ca1555b76
+ b4a921299d01c966.7b974672b20c7e0c.5df544d275452d1a.d01d422c05ec8fde
+ 0000000000000000
+VTESTPS_128_3(mem)
+ before
+ 337f81de30309a28.9fa00e566e1f09cd.116f97eee46cac2c.6b1a1f8b79097575
+ bef678c72ff4ea63.4831597b8e5aa54b.7ebe77b7edf75768.4af49c47be643c52
+ aa58f9a0f135113c.0ba90006983ed88d.9e5164baeab83bed.54cfb671e0e2bc5d
+ d36f81558ffdcae0.4453ff622958df3e.4df4d8e4f7bb14e6.e7f769777a103141
+ 5db8b1c42879d9ab
+ after
+ 337f81de30309a28.9fa00e566e1f09cd.116f97eee46cac2c.6b1a1f8b79097575
+ bef678c72ff4ea63.4831597b8e5aa54b.7ebe77b7edf75768.4af49c47be643c52
+ aa58f9a0f135113c.0ba90006983ed88d.9e5164baeab83bed.54cfb671e0e2bc5d
+ d36f81558ffdcae0.4453ff622958df3e.4df4d8e4f7bb14e6.e7f769777a103141
+ 0000000000000001
+
+VTESTPS_256_1(reg)
+ before
+ 145d8bc487a9ee46.14088ad2285bd27b.4f7d50fbdc33f60b.677351202f0d9d80
+ 6634f2e4332dadbf.4bef9203d558e539.8871f13d4e5c58a0.c7994b59aeb993e7
+ b187e28ec79051c1.53f014d5b402bf45.4b7ddd951a5d43a8.4b34407d91cbb146
+ 4fa3572fdf5e18f9.08d78d32e1651bcb.f4eb106ddcc5f1d0.ce0eae77f350b5ca
+ 2cf41033f153599e
+ after
+ 145d8bc487a9ee46.14088ad2285bd27b.4f7d50fbdc33f60b.677351202f0d9d80
+ 6634f2e4332dadbf.4bef9203d558e539.8871f13d4e5c58a0.c7994b59aeb993e7
+ b187e28ec79051c1.53f014d5b402bf45.4b7ddd951a5d43a8.4b34407d91cbb146
+ 4fa3572fdf5e18f9.08d78d32e1651bcb.f4eb106ddcc5f1d0.ce0eae77f350b5ca
+ 0000000000000000
+VTESTPS_256_1(mem)
+ before
+ 41b2e29da6e05aef.9dd44d3418243c13.46707708778cb6f8.de088632311d9ec3
+ e814a0a12f0473e9.f865c1070d6dfaba.e886504193834cf8.67203c51b5f3882e
+ ffe6c72ca7ca62b7.baa4ae165bc58d9b.cce693cb505698f6.ea7e2d3403d2e9bd
+ 60f3d2282b3ee185.40dc10cb9db93261.cd5cbc91ca12571f.c3705549b747fe1b
+ 4e40b0fb6edc02f5
+ after
+ 41b2e29da6e05aef.9dd44d3418243c13.46707708778cb6f8.de088632311d9ec3
+ e814a0a12f0473e9.f865c1070d6dfaba.e886504193834cf8.67203c51b5f3882e
+ ffe6c72ca7ca62b7.baa4ae165bc58d9b.cce693cb505698f6.ea7e2d3403d2e9bd
+ 60f3d2282b3ee185.40dc10cb9db93261.cd5cbc91ca12571f.c3705549b747fe1b
+ 0000000000000000
+
+VTESTPS_256_1(reg)
+ before
+ e63c3ab6c42032f6.e9093d82d66dac81.e658e39470d425b9.c6b4477f1ec2459f
+ e9aef0e6549ccacb.75f28427c56281d5.096524dc6fa2a24f.95bab18168721ea1
+ b2e2cdf7bade061f.df7b2302132a1aad.034fce0f36b0e4ce.143a7583c22f9d51
+ 9c26cd559371229f.057097feddcf3436.3162dd99628928e3.21ff0f714b047fdd
+ 96d7fb371dfd806f
+ after
+ e63c3ab6c42032f6.e9093d82d66dac81.e658e39470d425b9.c6b4477f1ec2459f
+ e9aef0e6549ccacb.75f28427c56281d5.096524dc6fa2a24f.95bab18168721ea1
+ b2e2cdf7bade061f.df7b2302132a1aad.034fce0f36b0e4ce.143a7583c22f9d51
+ 9c26cd559371229f.057097feddcf3436.3162dd99628928e3.21ff0f714b047fdd
+ 0000000000000000
+VTESTPS_256_1(mem)
+ before
+ 518cb6c254275b33.05c5ec6c7ae259f7.c19d5b093e608a9c.efe94de78fb9aa3a
+ 2cebbafc0d8dcd56.470a27a80cbce8d2.f0cdeb0e52e6da0a.99321a6358cda57e
+ 04c085d3633c9204.c0437876e48b0add.6fcec3f9366fdead.8b87417a5a50575b
+ b6d69231733f6668.cabadd409fdcfcc4.186a60b6060652b0.2135bd9930cefa7e
+ b7898a2a76d4ca93
+ after
+ 518cb6c254275b33.05c5ec6c7ae259f7.c19d5b093e608a9c.efe94de78fb9aa3a
+ 2cebbafc0d8dcd56.470a27a80cbce8d2.f0cdeb0e52e6da0a.99321a6358cda57e
+ 04c085d3633c9204.c0437876e48b0add.6fcec3f9366fdead.8b87417a5a50575b
+ b6d69231733f6668.cabadd409fdcfcc4.186a60b6060652b0.2135bd9930cefa7e
+ 0000000000000000
+
+VTESTPS_256_1(reg)
+ before
+ a9cca49bc9ed0545.1cfb5e0458a204af.c3bc5274d83afa32.c96e3d32ddb7f440
+ 534d0857c4a6e541.13f963372e712904.0594d17d2c3140d3.5ca6d657d78f7e89
+ 1157b0ca048aa633.789e1fb612b99194.ee9058c6364d0a55.aedea7121199adb6
+ 3f359a5f242586c6.25b40d6d2085f78b.d8fbe2bd921b9362.9be22c50a6e23cf4
+ 007de2fbb375e96f
+ after
+ a9cca49bc9ed0545.1cfb5e0458a204af.c3bc5274d83afa32.c96e3d32ddb7f440
+ 534d0857c4a6e541.13f963372e712904.0594d17d2c3140d3.5ca6d657d78f7e89
+ 1157b0ca048aa633.789e1fb612b99194.ee9058c6364d0a55.aedea7121199adb6
+ 3f359a5f242586c6.25b40d6d2085f78b.d8fbe2bd921b9362.9be22c50a6e23cf4
+ 0000000000000040
+VTESTPS_256_1(mem)
+ before
+ b77c4401535e6e52.3834c285c103bfa7.f708aa4873e21814.20206bcddd2718a6
+ 9dacce4da3aa88c9.5aa022a576b18e81.ca65703328dbb05c.224cef62b3fbd4ce
+ 8ed7fccbbe63f201.00c5b82ce0ba2f01.7a99dd1b597c7b8f.3bcb6ae9af250586
+ 66ca4b67c1986926.86ef7e869aabddd3.e36e6cea25d234d8.c5e9d9cc6d31e579
+ 1df237788aaab054
+ after
+ b77c4401535e6e52.3834c285c103bfa7.f708aa4873e21814.20206bcddd2718a6
+ 9dacce4da3aa88c9.5aa022a576b18e81.ca65703328dbb05c.224cef62b3fbd4ce
+ 8ed7fccbbe63f201.00c5b82ce0ba2f01.7a99dd1b597c7b8f.3bcb6ae9af250586
+ 66ca4b67c1986926.86ef7e869aabddd3.e36e6cea25d234d8.c5e9d9cc6d31e579
+ 0000000000000000
+
+VTESTPS_256_2(reg)
+ before
+ 9f31805aa21ca4c2.0150350dc752a964.476a7220410fd5a2.e1b2998ea6e79863
+ a7f4b1dc5013fb70.3b3738a9ed9f6ee6.a18190647072531b.502fe0f1f8ca635d
+ 9285c46c301cf20a.f049cf274e8a73d8.ef82d2c0c46093e9.0cb2be01388451f2
+ ba31b775dfc2c53b.fc54777406207567.8cb7369ed866d0b9.f107ada981231d4d
+ dbf92bd5f0b3849b
+ after
+ 9f31805aa21ca4c2.0150350dc752a964.476a7220410fd5a2.e1b2998ea6e79863
+ 9285c46c301cf20a.f049cf274e8a73d8.ef82d2c0c46093e9.0cb2be01388451f2
+ 9285c46c301cf20a.f049cf274e8a73d8.ef82d2c0c46093e9.0cb2be01388451f2
+ ba31b775dfc2c53b.fc54777406207567.8cb7369ed866d0b9.f107ada981231d4d
+ 0000000000000001
+VTESTPS_256_2(mem)
+ before
+ a656b471a03e4108.7c448563f891afb0.3b22aa7a326c30bf.d66db76c48104736
+ 2ee8c269aed212bf.340a2aa11816ed14.8980e626ee7a600c.27f05195b1e8340d
+ 4f7cd3a9357ab1ed.3ecea39edadcbb14.c239a6655557c078.dd8b0085af7cd2ea
+ e5de621d5243dbbd.f6deeac3db70545c.c21b6722830e0d32.528cc1a8dd575e78
+ e43d8f6ad7061464
+ after
+ a656b471a03e4108.7c448563f891afb0.3b22aa7a326c30bf.d66db76c48104736
+ 59a94b8e5fc1bef7.83bb7a9c076e504f.c4dd5585cd93cf40.29924893b7efb8c9
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ e5de621d5243dbbd.f6deeac3db70545c.c21b6722830e0d32.528cc1a8dd575e78
+ 0000000000000040
+
+VTESTPS_256_2(reg)
+ before
+ edec66383a14305a.ccdaebb220384b5c.b884fd7db65cf597.64f0a34995ab0264
+ cae3427ca10ded05.df3cea52bc65bff6.df0dd738072eda72.8686d8c6a73b5d3b
+ d86e1fa3a97e8811.fcd0dbeb41d7f0b6.c9c575616b723f98.03a78185d3c9d8e2
+ 71dbfa1aedf23d2c.fe613b67cb999dc9.d1f8d1627eb35fb6.b7201a7238613086
+ 7dbd1f79ef102053
+ after
+ edec66383a14305a.ccdaebb220384b5c.b884fd7db65cf597.64f0a34995ab0264
+ d86e1fa3a97e8811.fcd0dbeb41d7f0b6.c9c575616b723f98.03a78185d3c9d8e2
+ d86e1fa3a97e8811.fcd0dbeb41d7f0b6.c9c575616b723f98.03a78185d3c9d8e2
+ 71dbfa1aedf23d2c.fe613b67cb999dc9.d1f8d1627eb35fb6.b7201a7238613086
+ 0000000000000001
+VTESTPS_256_2(mem)
+ before
+ 33490d8617e16674.f275ce4c0af547ff.c0bc85b477b8815a.53f2e9a9db7d7878
+ b3925f86c9e1bc16.b88797a49b14e339.20ad35bd613e5796.abfeb8a01e5cc389
+ db629163241ade64.1d5f51903dda4d84.f900c86ea439dca8.346a3ab5e4dd7f95
+ 86871f0b419a8a8b.7e47f97b8bd3c18d.2681b8b35cb5cbbd.4c806c53c98be64a
+ 4e8d49e668f33552
+ after
+ 33490d8617e16674.f275ce4c0af547ff.c0bc85b477b8815a.53f2e9a9db7d7878
+ ccb6f279e81e998b.0d8a31b3f50ab800.3f437a4b88477ea5.ac0d165624828787
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 86871f0b419a8a8b.7e47f97b8bd3c18d.2681b8b35cb5cbbd.4c806c53c98be64a
+ 0000000000000040
+
+VTESTPS_256_2(reg)
+ before
+ 95ddccda5da0a859.8fcb85683e6d7ab6.378c8ad1228c7aff.85fc8378a6bde101
+ 7fbbf39b451e7a0c.d4fb4068379e6b12.a47a00fe9d90b587.f03ca4a99d5dda9f
+ 6775ba95bbfae817.2fe2cbf6473918cb.215c576e986caed0.450f98325ea172c4
+ a8561b355cbf2e25.7d4ea2fe8a4a3f0c.0a808b8eb0aaa187.5e3fd9000596659c
+ 1999e5fdac476e52
+ after
+ 95ddccda5da0a859.8fcb85683e6d7ab6.378c8ad1228c7aff.85fc8378a6bde101
+ 6775ba95bbfae817.2fe2cbf6473918cb.215c576e986caed0.450f98325ea172c4
+ 6775ba95bbfae817.2fe2cbf6473918cb.215c576e986caed0.450f98325ea172c4
+ a8561b355cbf2e25.7d4ea2fe8a4a3f0c.0a808b8eb0aaa187.5e3fd9000596659c
+ 0000000000000001
+VTESTPS_256_2(mem)
+ before
+ 50e9371771c04a13.a0a914e5c3f988e3.9b09416c1dde9a02.bb3099c881d8c958
+ e0fa4b39700eb40a.a9bba0138d3531fd.63e1252c1c00e5d9.90b97c8aa68263ee
+ a69a9d4ec43c6964.21d8bb2955fd661e.b3a0c82aa2bddebc.e567303ebb33aaf6
+ 7c93aa448a57264c.624c6295b8e063f2.6513a852cb1f3fd7.1686b1525d77dc1b
+ 7f62fc3128da330a
+ after
+ 50e9371771c04a13.a0a914e5c3f988e3.9b09416c1dde9a02.bb3099c881d8c958
+ af16c8e88e3fb5ec.5f56eb1a3c06771c.64f6be93e22165fd.44cf66377e2736a7
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 7c93aa448a57264c.624c6295b8e063f2.6513a852cb1f3fd7.1686b1525d77dc1b
+ 0000000000000040
+
+VTESTPS_256_3(reg)
+ before
+ 7c460c46b6e9ec6e.3fb3ed06dd6aa4ef.c9628fc251676327.56054191b435c558
+ 6980ddffa62f42f5.cbc4e280da81a279.b368401cbc20a367.62440dd178082b68
+ a25a6bc792397248.fd93059e9ca9da15.7aa8700f96975f5e.669b8a0034a62f36
+ 8221b20b1691b816.afebd24d3fec09f0.7b6f1b077b56d3b9.3cd53309041a8bec
+ c1bf84d70271fcb6
+ after
+ 7c460c46b6e9ec6e.3fb3ed06dd6aa4ef.c9628fc251676327.56054191b435c558
+ 6980ddffa62f42f5.cbc4e280da81a279.b368401cbc20a367.62440dd178082b68
+ a25a6bc792397248.fd93059e9ca9da15.7aa8700f96975f5e.669b8a0034a62f36
+ 8221b20b1691b816.afebd24d3fec09f0.7b6f1b077b56d3b9.3cd53309041a8bec
+ 0000000000000000
+VTESTPS_256_3(mem)
+ before
+ d125f9584cb63dc2.6721af35cfc65009.be9ac677e059ea35.13093e7006eb3a24
+ 48d30e77fef50b39.aca65db2586175cd.066a5c099bf93b11.9cc2d4b6d3e2d14a
+ 02954020333a224a.adfcb8ee4df0650f.632910f08bdab6b0.73e6d9467fc5d4d8
+ db360a3f08923e1f.c56ebc564cfe597b.b1a15e16cc07183d.f4c0498aa6227f79
+ 7b9e20f0e2850dda
+ after
+ d125f9584cb63dc2.6721af35cfc65009.be9ac677e059ea35.13093e7006eb3a24
+ 48d30e77fef50b39.aca65db2586175cd.066a5c099bf93b11.9cc2d4b6d3e2d14a
+ 02954020333a224a.adfcb8ee4df0650f.632910f08bdab6b0.73e6d9467fc5d4d8
+ db360a3f08923e1f.c56ebc564cfe597b.b1a15e16cc07183d.f4c0498aa6227f79
+ 0000000000000000
+
+VTESTPS_256_3(reg)
+ before
+ 64ca5be2d279bba7.af84e8c198091ae4.52496555ee1890bc.cc9fc3697b8d1ce5
+ 0b91f5ce108ac48b.5a49579000a973c7.aedab056d1c9447f.90efbad4b3777fd3
+ cc3fea1f38446633.b852d19a5b8005f1.376b98c7919db270.d95cbf4391d1fd34
+ 04203641e734db4a.a56bd4c9c5998c91.48481913c921163a.83b44ea230a85234
+ 6ac1e3ddad0739fe
+ after
+ 64ca5be2d279bba7.af84e8c198091ae4.52496555ee1890bc.cc9fc3697b8d1ce5
+ 0b91f5ce108ac48b.5a49579000a973c7.aedab056d1c9447f.90efbad4b3777fd3
+ cc3fea1f38446633.b852d19a5b8005f1.376b98c7919db270.d95cbf4391d1fd34
+ 04203641e734db4a.a56bd4c9c5998c91.48481913c921163a.83b44ea230a85234
+ 0000000000000000
+VTESTPS_256_3(mem)
+ before
+ 6a50fbe023fa6fbf.0c80d5a0b8e55f7d.fd60db0b5b01c3d1.3cbf2fa615dfab8a
+ 5e2d1197af8eb0a2.43aac4a847e33078.9cfc624a38c367dd.701bd7ec1266af0b
+ 2424a1ef6cceb8d4.04ebfec532bb88e6.5d0de67479eb33e2.41a70c515b3f5b6a
+ 970127d276c64280.ab8f7f6312f8a474.1e5de2743a86e50c.09b0ca418df8ee52
+ 26820d29441da270
+ after
+ 6a50fbe023fa6fbf.0c80d5a0b8e55f7d.fd60db0b5b01c3d1.3cbf2fa615dfab8a
+ 5e2d1197af8eb0a2.43aac4a847e33078.9cfc624a38c367dd.701bd7ec1266af0b
+ 2424a1ef6cceb8d4.04ebfec532bb88e6.5d0de67479eb33e2.41a70c515b3f5b6a
+ 970127d276c64280.ab8f7f6312f8a474.1e5de2743a86e50c.09b0ca418df8ee52
+ 0000000000000040
+
+VTESTPS_256_3(reg)
+ before
+ f269d2731b38b470.9390202eea830bd4.94e243ef8527c0cd.bab9d236969f3786
+ cab1138daed760fd.f39c07ede410cff9.1b3047d327d3179e.0ded32a6a943e67d
+ 0ba6cee19a86e1c4.95f258fd7f79491e.9cc5867d9388e693.f2c57eb0907cad1d
+ 0f93fedd7acf7570.545e8f49d8cb366d.72ecfc5865d26957.470d334166584a91
+ e790cb4348e37706
+ after
+ f269d2731b38b470.9390202eea830bd4.94e243ef8527c0cd.bab9d236969f3786
+ cab1138daed760fd.f39c07ede410cff9.1b3047d327d3179e.0ded32a6a943e67d
+ 0ba6cee19a86e1c4.95f258fd7f79491e.9cc5867d9388e693.f2c57eb0907cad1d
+ 0f93fedd7acf7570.545e8f49d8cb366d.72ecfc5865d26957.470d334166584a91
+ 0000000000000000
+VTESTPS_256_3(mem)
+ before
+ ad1cc4a45127f0a7.33c5a0ecea4056ae.0bac28bd09115212.fbf3a5cf3a3edc96
+ 777b9a4e9d3273a1.d388ae7a8865c02a.98a8a0453157593a.92247d50ae577afe
+ 1f7ac72f4910ba1f.4b2826f3edc8f18f.d51e72cd6aaa0611.93cc81465caa8039
+ 83e5c93271cc824f.f7f103c3b7f8238a.a0d91a41d01516c2.5937ac1de0c22af3
+ 42b1fa41d72bb3d9
+ after
+ ad1cc4a45127f0a7.33c5a0ecea4056ae.0bac28bd09115212.fbf3a5cf3a3edc96
+ 777b9a4e9d3273a1.d388ae7a8865c02a.98a8a0453157593a.92247d50ae577afe
+ 1f7ac72f4910ba1f.4b2826f3edc8f18f.d51e72cd6aaa0611.93cc81465caa8039
+ 83e5c93271cc824f.f7f103c3b7f8238a.a0d91a41d01516c2.5937ac1de0c22af3
+ 0000000000000000
+
+VTESTPS_256_3(reg)
+ before
+ a885671fdc725897.7d881b423072865a.342f4156827e92c6.d3a7148d80a5457a
+ e901f0218c2255d8.eb2e394da30e846e.5c2ddd18e9e87cf0.4c52dc9e95644e65
+ 5f6f90b482c7e649.a7a59f3ee5ad36b7.cc39d17688c11bb4.e5a7ef5e2c61eeae
+ 681c43455bed4696.8eb7ca01125a5861.e09d1bdafc95acbd.7b72c8bb60a5e181
+ eb7ee3a04e3ee30c
+ after
+ a885671fdc725897.7d881b423072865a.342f4156827e92c6.d3a7148d80a5457a
+ e901f0218c2255d8.eb2e394da30e846e.5c2ddd18e9e87cf0.4c52dc9e95644e65
+ 5f6f90b482c7e649.a7a59f3ee5ad36b7.cc39d17688c11bb4.e5a7ef5e2c61eeae
+ 681c43455bed4696.8eb7ca01125a5861.e09d1bdafc95acbd.7b72c8bb60a5e181
+ 0000000000000000
+VTESTPS_256_3(mem)
+ before
+ 0f99bdf81137af78.5e54053fb221b26a.7d3134834722a897.f4a6b6b2e1f16bb8
+ c48dd0b1c69d02f4.9f63d20d24ef6671.4edf5bae9f10e086.64a09e69d2609350
+ e7289ab6887a98aa.8595a71d4ce19d59.de8dbb6f3730bd59.8bd7d06a6b6f6132
+ 523496f373dd2cc6.6d357fdac68594cc.0907ceb32b8efa3d.c796472349a8110a
+ 732bffff079ade83
+ after
+ 0f99bdf81137af78.5e54053fb221b26a.7d3134834722a897.f4a6b6b2e1f16bb8
+ c48dd0b1c69d02f4.9f63d20d24ef6671.4edf5bae9f10e086.64a09e69d2609350
+ e7289ab6887a98aa.8595a71d4ce19d59.de8dbb6f3730bd59.8bd7d06a6b6f6132
+ 523496f373dd2cc6.6d357fdac68594cc.0907ceb32b8efa3d.c796472349a8110a
+ 0000000000000000
+
+VTESTPS_256_3(reg)
+ before
+ ebe0f46a42ce064a.e27e4054a4cf7b76.b49056b02f678776.ac1812659537555d
+ 8b0222d095d2c30a.73d115c6375e41e4.b4f3280b2311b204.a18e0170943688e6
+ aedd869e9d315170.e1fb8f3347953a3c.caa8f2573d115022.c5331ac241985004
+ b2bd1b3ef578ee28.08c62c88f08121ab.53fcae0119f39e7b.f4d4d646bb6868e2
+ 0a3db2e81bb28dad
+ after
+ ebe0f46a42ce064a.e27e4054a4cf7b76.b49056b02f678776.ac1812659537555d
+ 8b0222d095d2c30a.73d115c6375e41e4.b4f3280b2311b204.a18e0170943688e6
+ aedd869e9d315170.e1fb8f3347953a3c.caa8f2573d115022.c5331ac241985004
+ b2bd1b3ef578ee28.08c62c88f08121ab.53fcae0119f39e7b.f4d4d646bb6868e2
+ 0000000000000000
+VTESTPS_256_3(mem)
+ before
+ e3392b947f837b90.f2eddd1d3a31d4dd.c50067b24f2db35d.a93a5a735441d8bc
+ 5b96bc3603e6eeb8.cabbc8a807eb403b.f273bd9b80a5ac7d.29b0f11a8a893990
+ 4e1ee1bac2e7a151.9571d849f92f6df0.6ceca8319df6c838.2fa870635557fea4
+ 989f170dd9925186.b15c0a6eab8b98a6.0f37a65fc52bc2b9.176fd1b9543563a4
+ 3d51128721b2a43b
+ after
+ e3392b947f837b90.f2eddd1d3a31d4dd.c50067b24f2db35d.a93a5a735441d8bc
+ 5b96bc3603e6eeb8.cabbc8a807eb403b.f273bd9b80a5ac7d.29b0f11a8a893990
+ 4e1ee1bac2e7a151.9571d849f92f6df0.6ceca8319df6c838.2fa870635557fea4
+ 989f170dd9925186.b15c0a6eab8b98a6.0f37a65fc52bc2b9.176fd1b9543563a4
+ 0000000000000000
+
+VTESTPS_256_3(reg)
+ before
+ fd9a2e3b5857fc16.15e3d81963f4ba84.78c85982b98afd09.b61f32111250572d
+ b396224096b2a8e0.a1b7a2cc7c199876.4801c1f1c0b9d8c6.3f72c833a07142bf
+ bb91e802764ee446.18e6f010410ba689.7b533f275ca36589.85fae5b18c9b419d
+ 71d67eed94b7ecf4.563e3ed3ced8a1e8.6f09cd9028d4dffd.64840377f1da0ef0
+ b8dca071eb3866e7
+ after
+ fd9a2e3b5857fc16.15e3d81963f4ba84.78c85982b98afd09.b61f32111250572d
+ b396224096b2a8e0.a1b7a2cc7c199876.4801c1f1c0b9d8c6.3f72c833a07142bf
+ bb91e802764ee446.18e6f010410ba689.7b533f275ca36589.85fae5b18c9b419d
+ 71d67eed94b7ecf4.563e3ed3ced8a1e8.6f09cd9028d4dffd.64840377f1da0ef0
+ 0000000000000000
+VTESTPS_256_3(mem)
+ before
+ 5dce378c98c304ac.31b3df6e8e7afb95.368909003e8c44c1.7e716998c0d983cf
+ 2e2645b21187a56b.577207effd224ed6.9695cb83ad314d3d.06d50eabc13d8cab
+ 09b044d1748e0551.3f60f2dd7f3c2162.512c024838d5768b.6182b836c68c383c
+ c937b2d3dde6e08a.45c99da5b053afe6.431b2a3bfa847cd5.ecc464a36c53c12e
+ 04e70c604e1d632f
+ after
+ 5dce378c98c304ac.31b3df6e8e7afb95.368909003e8c44c1.7e716998c0d983cf
+ 2e2645b21187a56b.577207effd224ed6.9695cb83ad314d3d.06d50eabc13d8cab
+ 09b044d1748e0551.3f60f2dd7f3c2162.512c024838d5768b.6182b836c68c383c
+ c937b2d3dde6e08a.45c99da5b053afe6.431b2a3bfa847cd5.ecc464a36c53c12e
+ 0000000000000000
+
+VTESTPS_256_3(reg)
+ before
+ 0336aed709765ce8.4a880aa6679bf241.c5f802b12bf3350e.472ebd4810481a47
+ 46ff457638ebe608.6770c8352eb8f6a3.1a3b1f6f8ca8ef85.3b30385b952f0e0e
+ 298ccea878073e39.feb8686c4f49a9dc.a2dcf04a70ff18f7.faef1861a6451256
+ 092a43d964569f27.e92f6737e65ac617.b8286fae7383ee12.5f35d8445e95e24a
+ 48d0f4f2da2b3c17
+ after
+ 0336aed709765ce8.4a880aa6679bf241.c5f802b12bf3350e.472ebd4810481a47
+ 46ff457638ebe608.6770c8352eb8f6a3.1a3b1f6f8ca8ef85.3b30385b952f0e0e
+ 298ccea878073e39.feb8686c4f49a9dc.a2dcf04a70ff18f7.faef1861a6451256
+ 092a43d964569f27.e92f6737e65ac617.b8286fae7383ee12.5f35d8445e95e24a
+ 0000000000000040
+VTESTPS_256_3(mem)
+ before
+ 8f8ae9553513dae9.4025a27599654780.06a040820df80a81.b76b9a0730c1ab80
+ 1230325b8b5a79eb.2bc9e6e8b2bf70ee.2fd66f39e32e3145.fdf16cc143448bed
+ ab8d4aeff90bd449.26620b9e4bf0571d.429f70498208f790.e506e1484998cc06
+ 386fb0fd9b32a931.8d3b0e03018537ba.19c5c09c0693188d.caf6f508dd4aa877
+ 0a0ca56d9ce45ceb
+ after
+ 8f8ae9553513dae9.4025a27599654780.06a040820df80a81.b76b9a0730c1ab80
+ 1230325b8b5a79eb.2bc9e6e8b2bf70ee.2fd66f39e32e3145.fdf16cc143448bed
+ ab8d4aeff90bd449.26620b9e4bf0571d.429f70498208f790.e506e1484998cc06
+ 386fb0fd9b32a931.8d3b0e03018537ba.19c5c09c0693188d.caf6f508dd4aa877
+ 0000000000000000
+
+VTESTPS_256_3(reg)
+ before
+ ff95ebe421f5230f.93a0dd718cdcb2cd.bca2e98470094d71.9215d91f8cda4f69
+ 07ddc5d709063b8f.99ee4e37e814ab49.0fe19a8b3309d5ed.875b39bf2fea5950
+ 7c302eb4efa5de16.2723803bcce752d2.e2451c86e60f0bda.d5625c670ccef16d
+ bcda23e6705e4850.170cee6a54606194.911a6cdf26a92ae6.59f8bc023e92d4ed
+ ede7d77ee142befc
+ after
+ ff95ebe421f5230f.93a0dd718cdcb2cd.bca2e98470094d71.9215d91f8cda4f69
+ 07ddc5d709063b8f.99ee4e37e814ab49.0fe19a8b3309d5ed.875b39bf2fea5950
+ 7c302eb4efa5de16.2723803bcce752d2.e2451c86e60f0bda.d5625c670ccef16d
+ bcda23e6705e4850.170cee6a54606194.911a6cdf26a92ae6.59f8bc023e92d4ed
+ 0000000000000040
+VTESTPS_256_3(mem)
+ before
+ 6efd27c612eb6bc5.21279fd827bbb7eb.467514ae9a8b95ba.78ab84048f636fbb
+ b8042ac6ed989774.08629df8b04a6591.90296ff5bd74a971.f3466260bbc81605
+ a8c95c6a8d56fd36.ced91bb1a8968fee.d2f67929d7285be4.5d35015f49645b72
+ 1817379f0f305a37.cdd6156fab2c70af.e6a6b03804b26540.14c65d6dd2c379ab
+ 734372f6f572ad5f
+ after
+ 6efd27c612eb6bc5.21279fd827bbb7eb.467514ae9a8b95ba.78ab84048f636fbb
+ b8042ac6ed989774.08629df8b04a6591.90296ff5bd74a971.f3466260bbc81605
+ a8c95c6a8d56fd36.ced91bb1a8968fee.d2f67929d7285be4.5d35015f49645b72
+ 1817379f0f305a37.cdd6156fab2c70af.e6a6b03804b26540.14c65d6dd2c379ab
+ 0000000000000000
+
+VTESTPS_256_3(reg)
+ before
+ d6f93d664bfc3338.e5bc394f8e3269a3.62a6859f54974680.a9068f0d611f84b1
+ 9834b92a73ee46e2.eb82dd672668e8a5.e99569ab3f644b0c.f7e29393097a7362
+ 173fe2ac06d3230a.06379fd4f4df9169.bfeebc00091dbc00.ac0636b818cfef80
+ ae68b45aa237065c.12a5fb8113a3211c.3eff7a0b4d50d407.a43ef668ac2bb436
+ bb554e8dde997eb1
+ after
+ d6f93d664bfc3338.e5bc394f8e3269a3.62a6859f54974680.a9068f0d611f84b1
+ 9834b92a73ee46e2.eb82dd672668e8a5.e99569ab3f644b0c.f7e29393097a7362
+ 173fe2ac06d3230a.06379fd4f4df9169.bfeebc00091dbc00.ac0636b818cfef80
+ ae68b45aa237065c.12a5fb8113a3211c.3eff7a0b4d50d407.a43ef668ac2bb436
+ 0000000000000000
+VTESTPS_256_3(mem)
+ before
+ cd19ba14cc25081d.b8f92c9ee3a72a83.eb996e59a0be53ea.c3129f36a889d0ce
+ b654b6e992dc0fa5.933f44e664aecd2c.6ddf724ab63ee4ff.aa7528efb652ec01
+ 52d3bff94bc84f76.9a86fa9dc2d82903.7442853f722e9086.4f7210a11139644b
+ 7d62502e13f884bb.281a492f98b17ab3.dc902324ef9b13ab.0e5653b858ca7359
+ 436ced9f249056d6
+ after
+ cd19ba14cc25081d.b8f92c9ee3a72a83.eb996e59a0be53ea.c3129f36a889d0ce
+ b654b6e992dc0fa5.933f44e664aecd2c.6ddf724ab63ee4ff.aa7528efb652ec01
+ 52d3bff94bc84f76.9a86fa9dc2d82903.7442853f722e9086.4f7210a11139644b
+ 7d62502e13f884bb.281a492f98b17ab3.dc902324ef9b13ab.0e5653b858ca7359
+ 0000000000000000
+
+VTESTPS_256_3(reg)
+ before
+ 4a02dbc51417496f.13cde576077569a1.9b472e0882c6fee8.8193c6e54a90289b
+ 7f631793c1eb87d0.f0e0fabc434dbb54.4d58a3941da3ef50.3f18ec6e9e198c82
+ 3eda9f76c9994ea4.f0660cebe28c35ff.9c9ba63f04d28a95.f1ec10ab0843fb8b
+ e3b46edac8acd898.ee2c95f1003c95cf.e25a3275d4e10a63.75d8ae89a31931e3
+ a6ab42f28ca7e9b6
+ after
+ 4a02dbc51417496f.13cde576077569a1.9b472e0882c6fee8.8193c6e54a90289b
+ 7f631793c1eb87d0.f0e0fabc434dbb54.4d58a3941da3ef50.3f18ec6e9e198c82
+ 3eda9f76c9994ea4.f0660cebe28c35ff.9c9ba63f04d28a95.f1ec10ab0843fb8b
+ e3b46edac8acd898.ee2c95f1003c95cf.e25a3275d4e10a63.75d8ae89a31931e3
+ 0000000000000001
+VTESTPS_256_3(mem)
+ before
+ 603049d4defae02f.ca3d812c59b16157.c8fe13b9ba6b95ef.7ce243a2295bad67
+ 7e323d19b51dd27b.4fc1d2d61932278e.59a8012f2b25f28c.c77fd6339dcdad4d
+ de7e9caf2e1d7ac5.cd8c5f46a3be64e8.7cf6dc40707567d1.1d7de592cfc247c0
+ 5be1e1816504953a.a2e923e693de5513.0fb41ed6a467b2eb.db276e2d58c6b66d
+ 5dcb6c6fd76637ff
+ after
+ 603049d4defae02f.ca3d812c59b16157.c8fe13b9ba6b95ef.7ce243a2295bad67
+ 7e323d19b51dd27b.4fc1d2d61932278e.59a8012f2b25f28c.c77fd6339dcdad4d
+ de7e9caf2e1d7ac5.cd8c5f46a3be64e8.7cf6dc40707567d1.1d7de592cfc247c0
+ 5be1e1816504953a.a2e923e693de5513.0fb41ed6a467b2eb.db276e2d58c6b66d
+ 0000000000000000
+
+VTESTPD_128_1(reg)
+ before
+ 00b3dcc4e52d0623.d024897b75e0df06.29251a24862035b8.edae45dee4078d06
+ 1e2cb89820a85f85.1b160e897abd1454.bd8d416b180f4186.f1afcc454b62b44d
+ 1482fe5724617dd0.1682ee9791a5ef50.bc6b9227e338b527.f9842ff5f683e5ed
+ 3e01a96d8ce69db1.9f33a491d5a72d28.810c0bc48626cd47.dff9ebdc0076da12
+ 81da7ae5854850e7
+ after
+ 00b3dcc4e52d0623.d024897b75e0df06.29251a24862035b8.edae45dee4078d06
+ 1e2cb89820a85f85.1b160e897abd1454.bd8d416b180f4186.f1afcc454b62b44d
+ 1482fe5724617dd0.1682ee9791a5ef50.bc6b9227e338b527.f9842ff5f683e5ed
+ 3e01a96d8ce69db1.9f33a491d5a72d28.810c0bc48626cd47.dff9ebdc0076da12
+ 0000000000000001
+VTESTPD_128_1(mem)
+ before
+ b9f35afca2040299.f8f5b546f5c3fbd3.90f7ad6463cc8a05.67bba7ae9b65c493
+ 650f060d73b7ae53.9ea91f4efa82d2e3.c79883fa5722c116.ccc66351be81d8b7
+ 5ffcfb04136b0e42.8c6ae1f237b2608d.1ee3a441cbb48f85.0b77391a8c07425e
+ 8484b3cd9e2fde91.1e85f99c49dcde7c.73a48b23de8eb07f.7f1c2773a0834135
+ 85ff28ca977f0fe8
+ after
+ b9f35afca2040299.f8f5b546f5c3fbd3.90f7ad6463cc8a05.67bba7ae9b65c493
+ 650f060d73b7ae53.9ea91f4efa82d2e3.c79883fa5722c116.ccc66351be81d8b7
+ 5ffcfb04136b0e42.8c6ae1f237b2608d.1ee3a441cbb48f85.0b77391a8c07425e
+ 8484b3cd9e2fde91.1e85f99c49dcde7c.73a48b23de8eb07f.7f1c2773a0834135
+ 0000000000000001
+
+VTESTPD_128_1(reg)
+ before
+ 7a6d38890c89e922.b174ac54310cdc6d.b04462bacc8e8b5d.a0a6b48ea9bde02f
+ b8b1541e9b2c0b8f.c0986185e810c202.9ef319b65b53a1db.82b79b6d4a4cdac2
+ 9d1976f4e2f5b1dd.8ebc4e4dde464d7b.44e018fe92b75ea3.f6a1bdabdd485b63
+ 83f09c777a6f16b5.f8acf0962fbb3805.fe565dfd0e47fb61.d63295367dbc1f3f
+ ff349ff947b4e182
+ after
+ 7a6d38890c89e922.b174ac54310cdc6d.b04462bacc8e8b5d.a0a6b48ea9bde02f
+ b8b1541e9b2c0b8f.c0986185e810c202.9ef319b65b53a1db.82b79b6d4a4cdac2
+ 9d1976f4e2f5b1dd.8ebc4e4dde464d7b.44e018fe92b75ea3.f6a1bdabdd485b63
+ 83f09c777a6f16b5.f8acf0962fbb3805.fe565dfd0e47fb61.d63295367dbc1f3f
+ 0000000000000001
+VTESTPD_128_1(mem)
+ before
+ 4d7457e1563c5e57.c781c113012677c6.d833c14ef87941cb.28a0e31f6a8eb7c0
+ 9cbd39d8c66152eb.c619e13413a70fba.0b1f3f5f548f22fa.1e0ba6d04319cc6d
+ c8ddc2cbb42f7969.da04f9464b7d1b3e.6d3ae5b7600698be.3be4a27c34737713
+ ae9e6da73cb08efe.608e04b54534d8fd.da51304137ec5e42.dd75d48fda28f45f
+ 5f0a3776d0c47efd
+ after
+ 4d7457e1563c5e57.c781c113012677c6.d833c14ef87941cb.28a0e31f6a8eb7c0
+ 9cbd39d8c66152eb.c619e13413a70fba.0b1f3f5f548f22fa.1e0ba6d04319cc6d
+ c8ddc2cbb42f7969.da04f9464b7d1b3e.6d3ae5b7600698be.3be4a27c34737713
+ ae9e6da73cb08efe.608e04b54534d8fd.da51304137ec5e42.dd75d48fda28f45f
+ 0000000000000040
+
+VTESTPD_128_1(reg)
+ before
+ 1cf1c79bb3d45298.28ceb65679f24ed6.b403feee9e597fa4.2e309ae9f64c31b3
+ 7274806b1ee3acdc.133719c68700751c.33aee35bf1774fde.45a2a19bb833cd3c
+ bce15f53ad7ec877.4ba613e183e7bffd.37ddaf6adb1b8258.fb75c04399acee0a
+ 55825ebefd30e113.ace71f9588b2e7a4.1dda5f85f8cf55be.2c7373ceb7c34f49
+ b46a36262b85ad24
+ after
+ 1cf1c79bb3d45298.28ceb65679f24ed6.b403feee9e597fa4.2e309ae9f64c31b3
+ 7274806b1ee3acdc.133719c68700751c.33aee35bf1774fde.45a2a19bb833cd3c
+ bce15f53ad7ec877.4ba613e183e7bffd.37ddaf6adb1b8258.fb75c04399acee0a
+ 55825ebefd30e113.ace71f9588b2e7a4.1dda5f85f8cf55be.2c7373ceb7c34f49
+ 0000000000000040
+VTESTPD_128_1(mem)
+ before
+ 6f24863813fdc4c8.9ba47b18aa85345c.12c5b9cdb36daa3e.41f2ed1ae22103bb
+ 396edef18b375060.e893b1cc4f0afdff.590e5d751f25c3f7.ff715794389dcafc
+ ee13ba3bae400c19.9a9afd48884a77a8.5c8c8779e9e5f0fa.b3a3995f93cee42c
+ 6ae196049823b51f.0b0759f8f2d1df02.f90cb4c52cb9eb74.b9d3ade792408ef8
+ 6d4f9198ce7f030c
+ after
+ 6f24863813fdc4c8.9ba47b18aa85345c.12c5b9cdb36daa3e.41f2ed1ae22103bb
+ 396edef18b375060.e893b1cc4f0afdff.590e5d751f25c3f7.ff715794389dcafc
+ ee13ba3bae400c19.9a9afd48884a77a8.5c8c8779e9e5f0fa.b3a3995f93cee42c
+ 6ae196049823b51f.0b0759f8f2d1df02.f90cb4c52cb9eb74.b9d3ade792408ef8
+ 0000000000000041
+
+VTESTPD_128_2(reg)
+ before
+ 2b6140dee5188013.89a3ef3766ec069d.9924c346292c71ba.0b5b5f4605ae7190
+ 4f56b625739641ba.26243fc033a8bdc0.9e3f369fc8e6697c.6e4204e68fcf3d7b
+ 347aefda138682ac.1f31048b1c6294b3.78a2ae6f6b8b02f3.fe901f92e6280c61
+ 3819e86762727e96.4f96b9843c2648a3.819a2823afa879cb.96102d3728c69a6d
+ 148da9c06eb4a3cb
+ after
+ 2b6140dee5188013.89a3ef3766ec069d.9924c346292c71ba.0b5b5f4605ae7190
+ 0000000000000000.0000000000000000.78a2ae6f6b8b02f3.fe901f92e6280c61
+ 347aefda138682ac.1f31048b1c6294b3.78a2ae6f6b8b02f3.fe901f92e6280c61
+ 3819e86762727e96.4f96b9843c2648a3.819a2823afa879cb.96102d3728c69a6d
+ 0000000000000001
+VTESTPD_128_2(mem)
+ before
+ 53d40f18d6fee3a9.b67f9c3afbe97323.911fdb97b00194bc.16729f252fc70ab1
+ 2eb2db2d7cb11531.0af707be7a749a01.c398e4b093fe3629.93780fe38877f051
+ 83f189ea7ad8f68f.90cf255e7ca132d9.c0cc52bc0229e716.55f674c855426857
+ 2c5d963bef7f41f0.a351f2889dfb755a.6388a0a5188f66b1.b63aca3f33b4ae6e
+ 138e0db6bd59fe42
+ after
+ 53d40f18d6fee3a9.b67f9c3afbe97323.911fdb97b00194bc.16729f252fc70ab1
+ 0000000000000000.0000000000000000.6ee024684ffe6b43.e98d60dad038f54e
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 2c5d963bef7f41f0.a351f2889dfb755a.6388a0a5188f66b1.b63aca3f33b4ae6e
+ 0000000000000040
+
+VTESTPD_128_2(reg)
+ before
+ c83f3a9890be9381.07c47d0cf5b3b380.a1ca6ba7770fa02e.8a994a59f23b6e24
+ 31994c52476eaad4.eef0ba49a87f086a.e5868b27a968ef01.0fc9cdc3ab39ba9b
+ aae73f4e7ef57fea.bfafc9df25f0fcdb.cad14e74cd929d80.d0e5a3ce60960743
+ 907710f9d2e04e6d.54cb27b887104bff.aef6b0fb7f19e757.a7b84a682c5d1048
+ 72103d7c2b9b92d5
+ after
+ c83f3a9890be9381.07c47d0cf5b3b380.a1ca6ba7770fa02e.8a994a59f23b6e24
+ 0000000000000000.0000000000000000.cad14e74cd929d80.d0e5a3ce60960743
+ aae73f4e7ef57fea.bfafc9df25f0fcdb.cad14e74cd929d80.d0e5a3ce60960743
+ 907710f9d2e04e6d.54cb27b887104bff.aef6b0fb7f19e757.a7b84a682c5d1048
+ 0000000000000001
+VTESTPD_128_2(mem)
+ before
+ 0bb7f9f67a5b4a17.3d93babfdfba5209.8b114ec2ebeeb001.eb43ae265c8a0931
+ 4f7bf8c235a9f139.0e88380d400fc86c.3e4dbce76c93e80d.df024362ff703fbb
+ 1b26b8cc77914668.5fa2884d916ceb3f.4b4bec15270dae51.e4806b1c0558c4a1
+ 4985b4015c2003d0.8b2da6ed6f5cf931.8cd65b373767bff6.580922bf09cdd58e
+ 95e964b6a75bae2e
+ after
+ 0bb7f9f67a5b4a17.3d93babfdfba5209.8b114ec2ebeeb001.eb43ae265c8a0931
+ 0000000000000000.0000000000000000.74eeb13d14114ffe.14bc51d9a375f6ce
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 4985b4015c2003d0.8b2da6ed6f5cf931.8cd65b373767bff6.580922bf09cdd58e
+ 0000000000000040
+
+VTESTPD_128_2(reg)
+ before
+ f96b2e6f7c8f8a2f.b664684b0161e59c.f0758c58756c2cec.debb8338b9aed72b
+ dedd7b5524f4a63a.3f8e51988161a7f9.e9c638fa4027c11c.1dc7e206c8ecb21a
+ a18947d43a163efe.bed1e9d2f92b0713.d26ba53f6c19f36e.26c4f38c80300cf0
+ 9fbc8e585b828e25.10f7aee784cbbf15.07b1cf9393ceff8e.d37f32b7fe83a0d8
+ 01c31c715ef32bff
+ after
+ f96b2e6f7c8f8a2f.b664684b0161e59c.f0758c58756c2cec.debb8338b9aed72b
+ 0000000000000000.0000000000000000.d26ba53f6c19f36e.26c4f38c80300cf0
+ a18947d43a163efe.bed1e9d2f92b0713.d26ba53f6c19f36e.26c4f38c80300cf0
+ 9fbc8e585b828e25.10f7aee784cbbf15.07b1cf9393ceff8e.d37f32b7fe83a0d8
+ 0000000000000001
+VTESTPD_128_2(mem)
+ before
+ 8c5e2ba7bb8b6890.32c24c4d22c3d15c.11cd1bc23f4d8c2b.e4e4b36254d32128
+ 501bdd46315815b8.b7e77e202b65444e.9d1fac4f45be2982.c4504b1848b395e6
+ 29c5ae38dd65eca3.8a771f3b13f523a8.90b9de7ab3295346.054195210dfb9677
+ f329186bdbbeaa7c.07be2b0b75fea915.c6672c2fa49bc6a3.02038cea3f366285
+ 16e12cdd79f032bd
+ after
+ 8c5e2ba7bb8b6890.32c24c4d22c3d15c.11cd1bc23f4d8c2b.e4e4b36254d32128
+ 0000000000000000.0000000000000000.ee32e43dc0b273d4.1b1b4c9dab2cded7
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ f329186bdbbeaa7c.07be2b0b75fea915.c6672c2fa49bc6a3.02038cea3f366285
+ 0000000000000040
+
+VTESTPD_128_3(reg)
+ before
+ 9f29726858b545ca.8a1398c945700a70.8a079ffdee0c1442.1bf4125a351f3ec4
+ f82559f67712d559.ca4fab403a85c9aa.709f757c1aac9edb.6b2e0ce781c176d5
+ 7c22dcf272931f16.8fa8ccbbd40ca357.13d2abf39369838b.92df96c2a48e2b03
+ 896cfacae6c25fac.b5ec77262f0e54a3.d0ec3cd0f8d001ff.6cd42dd8bb91197a
+ d5d94c13e2d6fc66
+ after
+ 9f29726858b545ca.8a1398c945700a70.8a079ffdee0c1442.1bf4125a351f3ec4
+ f82559f67712d559.ca4fab403a85c9aa.709f757c1aac9edb.6b2e0ce781c176d5
+ 7c22dcf272931f16.8fa8ccbbd40ca357.13d2abf39369838b.92df96c2a48e2b03
+ 896cfacae6c25fac.b5ec77262f0e54a3.d0ec3cd0f8d001ff.6cd42dd8bb91197a
+ 0000000000000041
+VTESTPD_128_3(mem)
+ before
+ a9ba6f61346a8ff2.794eace96f2dd0c7.18e5296d689997b9.0339247ee26b52e2
+ c44312adcd588f4a.aa16f0bba85faf15.94615c7c9ab929c6.08056069f0c9b2e1
+ 023fb1e3caacb79b.760ec0ad2de53840.052a8e40e178c6f5.3b9bebfdbb735fa8
+ 3e7bc9ee4673c511.3b831a299b4aa7f4.460c3aa35be42a73.f848c0a7e1f793e2
+ 9a59ded1fee08b3c
+ after
+ a9ba6f61346a8ff2.794eace96f2dd0c7.18e5296d689997b9.0339247ee26b52e2
+ c44312adcd588f4a.aa16f0bba85faf15.94615c7c9ab929c6.08056069f0c9b2e1
+ 023fb1e3caacb79b.760ec0ad2de53840.052a8e40e178c6f5.3b9bebfdbb735fa8
+ 3e7bc9ee4673c511.3b831a299b4aa7f4.460c3aa35be42a73.f848c0a7e1f793e2
+ 0000000000000041
+
+VTESTPD_128_3(reg)
+ before
+ 7f183ee8adba8361.56c4d5bc5eb873d7.53c1fa9c8d1a37de.35d5dd922109106b
+ 02d1dd598b12b6fe.25e451392e877e1a.1b145a73a0e225aa.ad50f1fa51f1350a
+ 7fd2b88e337361be.87a7b94fd0eda106.f0c83818702dad03.8a48f4c607aa557c
+ 5266caf5416ac04f.57db8aeb63f59ac6.2c298ff997870a96.a78a61e15e402bed
+ e2e3b43972be7487
+ after
+ 7f183ee8adba8361.56c4d5bc5eb873d7.53c1fa9c8d1a37de.35d5dd922109106b
+ 02d1dd598b12b6fe.25e451392e877e1a.1b145a73a0e225aa.ad50f1fa51f1350a
+ 7fd2b88e337361be.87a7b94fd0eda106.f0c83818702dad03.8a48f4c607aa557c
+ 5266caf5416ac04f.57db8aeb63f59ac6.2c298ff997870a96.a78a61e15e402bed
+ 0000000000000001
+VTESTPD_128_3(mem)
+ before
+ 151d6ab96030ec79.d6d80ff952820f5a.734b3ff900ab2287.2c825b80b37d7a0e
+ 1e04fd4d44a24fed.697584060147898e.b5c25466c51cf874.4c20981b609a3718
+ d866ebe138215810.66892488eb466b95.fb0d451cce53d7ba.e8504335396a7d60
+ 1e0daf615bb8c40d.2860eaebac09f11b.1ff88f09365d7a84.5d5c563adb7a8991
+ 0590cf96e1559858
+ after
+ 151d6ab96030ec79.d6d80ff952820f5a.734b3ff900ab2287.2c825b80b37d7a0e
+ 1e04fd4d44a24fed.697584060147898e.b5c25466c51cf874.4c20981b609a3718
+ d866ebe138215810.66892488eb466b95.fb0d451cce53d7ba.e8504335396a7d60
+ 1e0daf615bb8c40d.2860eaebac09f11b.1ff88f09365d7a84.5d5c563adb7a8991
+ 0000000000000041
+
+VTESTPD_128_3(reg)
+ before
+ 3d3aaab6e888e360.cdc7c5bac7734f11.0d46d59bdf1f56cd.ff4fac181a449eff
+ 61a5e1048b9da956.c25eaad6985fb447.7086de042011d757.75de1a359516fe57
+ cd1c72ed662224e6.d79fd9a3eb87b0dc.ac6e02920c6db064.5f70544cc3df57b7
+ ddec58de16a391bb.ea56ce0bdbf8fffc.1f483eb23ebe1da1.97d3d749c1aa664c
+ fbd11d18ab83e442
+ after
+ 3d3aaab6e888e360.cdc7c5bac7734f11.0d46d59bdf1f56cd.ff4fac181a449eff
+ 61a5e1048b9da956.c25eaad6985fb447.7086de042011d757.75de1a359516fe57
+ cd1c72ed662224e6.d79fd9a3eb87b0dc.ac6e02920c6db064.5f70544cc3df57b7
+ ddec58de16a391bb.ea56ce0bdbf8fffc.1f483eb23ebe1da1.97d3d749c1aa664c
+ 0000000000000041
+VTESTPD_128_3(mem)
+ before
+ 6537a4a59c7690c4.ed618f4137ab2c82.d54f05fc85bd5dd2.23618dce529159ba
+ b2d1e7dcb09024fe.59c7138463c630e6.7555fa6104e2858b.1605eb54e671a15a
+ be6b62aa04dc5d1e.7d6ae0123980da94.a7352a2674733453.528055af93ea312d
+ 66d191f9b367f64d.b595f35753666638.45bc0f37f27d2655.341ec54af78944e1
+ 192a3993aed9171f
+ after
+ 6537a4a59c7690c4.ed618f4137ab2c82.d54f05fc85bd5dd2.23618dce529159ba
+ b2d1e7dcb09024fe.59c7138463c630e6.7555fa6104e2858b.1605eb54e671a15a
+ be6b62aa04dc5d1e.7d6ae0123980da94.a7352a2674733453.528055af93ea312d
+ 66d191f9b367f64d.b595f35753666638.45bc0f37f27d2655.341ec54af78944e1
+ 0000000000000040
+
+VTESTPD_128_3(reg)
+ before
+ 5bf2acf55366e696.84cef1b7da3cadba.5c9647bf4d030f7d.2cb427809a0b16bd
+ 57c01bdc83bdedf0.f530fdcf94673c8f.d0b7d8b6c4e41310.38eaeeed872ac1b9
+ 6ae180b5d96967da.95c1312cfef460f8.6c45a3a85393ac9c.4529de6ad6e5e372
+ eea1d9eaf1f691ff.404e09bc33f0d423.8c8ca201979f16ce.303f75e3a2483817
+ d3f72e45075f7bd2
+ after
+ 5bf2acf55366e696.84cef1b7da3cadba.5c9647bf4d030f7d.2cb427809a0b16bd
+ 57c01bdc83bdedf0.f530fdcf94673c8f.d0b7d8b6c4e41310.38eaeeed872ac1b9
+ 6ae180b5d96967da.95c1312cfef460f8.6c45a3a85393ac9c.4529de6ad6e5e372
+ eea1d9eaf1f691ff.404e09bc33f0d423.8c8ca201979f16ce.303f75e3a2483817
+ 0000000000000001
+VTESTPD_128_3(mem)
+ before
+ 0b1c857a223769cf.404b21e868f1a70c.d2a3026a5067553a.8bd8d32d2b918f51
+ b47bf6700edcbe3c.bc2d541cd9e5e4ac.278b972270639f69.c7743199acf751d3
+ aae0fe12e8583642.be916ef0e15e858c.1bd443d0b0f26edd.9baeb8afb55c99fd
+ c917184bcbb98c10.a2c56cd21be9c658.8a4885612b1f7dc1.62d065dde24da27e
+ 7a27338dd055a900
+ after
+ 0b1c857a223769cf.404b21e868f1a70c.d2a3026a5067553a.8bd8d32d2b918f51
+ b47bf6700edcbe3c.bc2d541cd9e5e4ac.278b972270639f69.c7743199acf751d3
+ aae0fe12e8583642.be916ef0e15e858c.1bd443d0b0f26edd.9baeb8afb55c99fd
+ c917184bcbb98c10.a2c56cd21be9c658.8a4885612b1f7dc1.62d065dde24da27e
+ 0000000000000000
+
+VTESTPD_128_3(reg)
+ before
+ 3eff1e2d1b00ea2f.edebc009d40a7dd0.c413492d2411e3bb.50b5d6bffdf78943
+ 09a422285edba1b8.f22a72371f58c4ae.81c8016d98631762.49e5b4d743854e8c
+ 39623bea35700a47.b39eaac1c6ae1fd7.332f90fd11699ff8.51a5999619d588cb
+ 288566df3d4e6087.0e15e593e7184877.3796f24c2db1b72a.44c004e79af4f22a
+ fe046eb5e2ed49d5
+ after
+ 3eff1e2d1b00ea2f.edebc009d40a7dd0.c413492d2411e3bb.50b5d6bffdf78943
+ 09a422285edba1b8.f22a72371f58c4ae.81c8016d98631762.49e5b4d743854e8c
+ 39623bea35700a47.b39eaac1c6ae1fd7.332f90fd11699ff8.51a5999619d588cb
+ 288566df3d4e6087.0e15e593e7184877.3796f24c2db1b72a.44c004e79af4f22a
+ 0000000000000040
+VTESTPD_128_3(mem)
+ before
+ 5b3c54ee0ecc48f9.33589d7312fee025.de599e9a9ea3fcba.e84724c388c79ba4
+ 3633337d3a9eadc2.b728de134f0ec5cc.ff3651c0065af6cb.a49021cfbd368611
+ 6db6864e806e325c.0e412529900a4c29.4d7a7af33c49f3d6.c6bbe5dc698ab51e
+ db91c94dff4894f1.96ef6c22727cb2e8.a3f0961d5b7daf08.aa156d57274f6476
+ aceab3aa9312cec6
+ after
+ 5b3c54ee0ecc48f9.33589d7312fee025.de599e9a9ea3fcba.e84724c388c79ba4
+ 3633337d3a9eadc2.b728de134f0ec5cc.ff3651c0065af6cb.a49021cfbd368611
+ 6db6864e806e325c.0e412529900a4c29.4d7a7af33c49f3d6.c6bbe5dc698ab51e
+ db91c94dff4894f1.96ef6c22727cb2e8.a3f0961d5b7daf08.aa156d57274f6476
+ 0000000000000001
+
+VTESTPD_128_3(reg)
+ before
+ 2885b5434b5e30b9.5c907866d0398eb0.a97eb16b90f230b4.df631f2c7f01e68d
+ 79346e8ce8c0c6fd.cb7f1086124cddc3.a439ef6f87f8053a.dca0930ac5e15490
+ fd41daf308c3cb3b.06290c97de8d3d57.e36e2299f2186b26.75746ea5492ab43e
+ 0ff9f6e346f37d22.e75be88653096a97.c36746576ee09f23.88a92ae826e7c2c3
+ f00b45bf78253c4a
+ after
+ 2885b5434b5e30b9.5c907866d0398eb0.a97eb16b90f230b4.df631f2c7f01e68d
+ 79346e8ce8c0c6fd.cb7f1086124cddc3.a439ef6f87f8053a.dca0930ac5e15490
+ fd41daf308c3cb3b.06290c97de8d3d57.e36e2299f2186b26.75746ea5492ab43e
+ 0ff9f6e346f37d22.e75be88653096a97.c36746576ee09f23.88a92ae826e7c2c3
+ 0000000000000001
+VTESTPD_128_3(mem)
+ before
+ 886839165ceedcff.0ba8bcc83fdc165b.4ce220408acb20b0.9e71581496dcdcdd
+ 2e8a84daed515f10.4c9a2a0e8f0bd295.0f8830b0a1e01ace.d1d8533c06966002
+ bc3fa2f5485781a7.301b3b21d00cef7a.0e1a95c1b452151c.b8e8323b5b9c653b
+ 0f510d54890efdf0.1177ec6da169a7b7.2363ca61de30ccc6.afedf47d317a2837
+ 1232926f23bbe4a0
+ after
+ 886839165ceedcff.0ba8bcc83fdc165b.4ce220408acb20b0.9e71581496dcdcdd
+ 2e8a84daed515f10.4c9a2a0e8f0bd295.0f8830b0a1e01ace.d1d8533c06966002
+ bc3fa2f5485781a7.301b3b21d00cef7a.0e1a95c1b452151c.b8e8323b5b9c653b
+ 0f510d54890efdf0.1177ec6da169a7b7.2363ca61de30ccc6.afedf47d317a2837
+ 0000000000000001
+
+VTESTPD_128_3(reg)
+ before
+ 3d050a7bceebd622.048d43e4ca819118.4df9375f9bb037f7.2c314b7b3c83fcfa
+ 8cb0570fcd963a6b.75bfbf8f2abcf74b.3eee1a615d6cdae7.034e94fbe95961e1
+ 5b807595bc494c24.40b3fd43c2ccebb4.42a390e1802ace32.868822cd01bdb7aa
+ 06c1607b388f47fc.3f3479ebb0bc2a80.b3629549a3754d86.8fa970dea1bbba7f
+ fb7efa18e460258d
+ after
+ 3d050a7bceebd622.048d43e4ca819118.4df9375f9bb037f7.2c314b7b3c83fcfa
+ 8cb0570fcd963a6b.75bfbf8f2abcf74b.3eee1a615d6cdae7.034e94fbe95961e1
+ 5b807595bc494c24.40b3fd43c2ccebb4.42a390e1802ace32.868822cd01bdb7aa
+ 06c1607b388f47fc.3f3479ebb0bc2a80.b3629549a3754d86.8fa970dea1bbba7f
+ 0000000000000041
+VTESTPD_128_3(mem)
+ before
+ a6d33c68e7b7b5ff.e9bf152cdcf5689d.4f0fb073109970da.ef7725075fd9938c
+ 6d73b2bbc6cd2502.60c58e134505ebb3.4c111dc7fd6e79ef.50303d8652e3def2
+ 2a2cd9fb9bad33c1.c721c99e0e4d0ceb.13043cd3944701eb.34d7d832181e6864
+ bac82c1685639969.791dc138d45906f1.7eb58983f030c3f9.f5baf2774c166e8e
+ f02387c18a582b1b
+ after
+ a6d33c68e7b7b5ff.e9bf152cdcf5689d.4f0fb073109970da.ef7725075fd9938c
+ 6d73b2bbc6cd2502.60c58e134505ebb3.4c111dc7fd6e79ef.50303d8652e3def2
+ 2a2cd9fb9bad33c1.c721c99e0e4d0ceb.13043cd3944701eb.34d7d832181e6864
+ bac82c1685639969.791dc138d45906f1.7eb58983f030c3f9.f5baf2774c166e8e
+ 0000000000000001
+
+VTESTPD_128_3(reg)
+ before
+ 815f947c6f6fddb7.f91427f79dfc1326.d406734e32b41670.6aef81c32d367c46
+ 05ba131497e7be10.c3dc468a02825f23.3328d94ac5ea7815.b3809e7f6865e7fd
+ d68002f69d4d0bd0.f4ec06bbcd04378d.f2cff1992888678c.35335ea4bdc7c24b
+ 51fc5d8c1d2cffa3.6810e1761c8b588f.6c46b6a7f8182080.ccd33c1c476ac75c
+ 542db5d52259b35b
+ after
+ 815f947c6f6fddb7.f91427f79dfc1326.d406734e32b41670.6aef81c32d367c46
+ 05ba131497e7be10.c3dc468a02825f23.3328d94ac5ea7815.b3809e7f6865e7fd
+ d68002f69d4d0bd0.f4ec06bbcd04378d.f2cff1992888678c.35335ea4bdc7c24b
+ 51fc5d8c1d2cffa3.6810e1761c8b588f.6c46b6a7f8182080.ccd33c1c476ac75c
+ 0000000000000001
+VTESTPD_128_3(mem)
+ before
+ a90d43ba6ba14175.d27c1e44b410d736.fb1455a70b257e56.ffdb25e1d029df9e
+ a73f64b63d4d2ed5.b54a4288fd86cf35.89c3de3ab5de640e.06d838b24d44df91
+ 2a8e93b7b56936a8.56b3c6c69519234b.eeeaf61c37c0c7e2.dc8aed850af75e06
+ 0ec84ca8ee02151a.1103a56917550e25.06551b37acd963ff.df3d3fc8a3cd96a8
+ 693d2ae6b553c325
+ after
+ a90d43ba6ba14175.d27c1e44b410d736.fb1455a70b257e56.ffdb25e1d029df9e
+ a73f64b63d4d2ed5.b54a4288fd86cf35.89c3de3ab5de640e.06d838b24d44df91
+ 2a8e93b7b56936a8.56b3c6c69519234b.eeeaf61c37c0c7e2.dc8aed850af75e06
+ 0ec84ca8ee02151a.1103a56917550e25.06551b37acd963ff.df3d3fc8a3cd96a8
+ 0000000000000000
+
+VTESTPD_128_3(reg)
+ before
+ d8d6aa4bdc142326.2fb70c7505238656.4286dcdd20c7cd6e.add0c7793034f390
+ 8653bc63b39cf05a.69294d0b15d84689.4587658e4bfa9cd3.bf2778cce0de35c2
+ d1025b9ad678676a.98e88d543b2e11de.76543ee8357bb600.1826aa1ed8e2e3c1
+ 132d835ce233c305.97c1473d9230a382.3137625779d559a0.9498d75a324cb9b8
+ 0e4a7d6c0d2975d3
+ after
+ d8d6aa4bdc142326.2fb70c7505238656.4286dcdd20c7cd6e.add0c7793034f390
+ 8653bc63b39cf05a.69294d0b15d84689.4587658e4bfa9cd3.bf2778cce0de35c2
+ d1025b9ad678676a.98e88d543b2e11de.76543ee8357bb600.1826aa1ed8e2e3c1
+ 132d835ce233c305.97c1473d9230a382.3137625779d559a0.9498d75a324cb9b8
+ 0000000000000001
+VTESTPD_128_3(mem)
+ before
+ 640917408384d140.a9213016725942d5.447ff7b337eab7a1.d27dcd47b494bf5f
+ 719f21c2b0698a29.f02a5e3223771e87.7af01aa045690a66.b5727b25814424eb
+ 11d817deb1e55bba.42940a1e901893c6.15de2bf2d8b858fe.3662695b7c72c6ee
+ 1f827680a1030120.fcaa2f4456c8df3f.f017a6940de35c94.b199925742a9df14
+ 8162f2846f76ac0a
+ after
+ 640917408384d140.a9213016725942d5.447ff7b337eab7a1.d27dcd47b494bf5f
+ 719f21c2b0698a29.f02a5e3223771e87.7af01aa045690a66.b5727b25814424eb
+ 11d817deb1e55bba.42940a1e901893c6.15de2bf2d8b858fe.3662695b7c72c6ee
+ 1f827680a1030120.fcaa2f4456c8df3f.f017a6940de35c94.b199925742a9df14
+ 0000000000000001
+
+VTESTPD_128_3(reg)
+ before
+ 040b854d9e64687c.7968b9959dd03887.7bbac91210143c9d.e965077100f7d355
+ 95de47206bff5016.f9555c07c056bc1a.190ed4f35b87e78d.db95ca77ccff796c
+ 8f28356873d3a082.7d16dbc426a34906.33f34d53d2ad1cbb.a1726c918d070a06
+ 50354a91526d946f.e077b2b6edc39a77.25b52f9e121316d2.19ca68ab601c414f
+ 1d673ab26049db72
+ after
+ 040b854d9e64687c.7968b9959dd03887.7bbac91210143c9d.e965077100f7d355
+ 95de47206bff5016.f9555c07c056bc1a.190ed4f35b87e78d.db95ca77ccff796c
+ 8f28356873d3a082.7d16dbc426a34906.33f34d53d2ad1cbb.a1726c918d070a06
+ 50354a91526d946f.e077b2b6edc39a77.25b52f9e121316d2.19ca68ab601c414f
+ 0000000000000040
+VTESTPD_128_3(mem)
+ before
+ 8b175e90aa9b949c.33508207a2586787.fd445ecb2ec16c98.4ba07640b644127f
+ 3da45132591c27f9.93c7d93702215777.b1495aee07a97a95.01001ea55acc4c6d
+ 10db8d858adb51b4.cee44c8b0b539dea.d952220b9487819c.a320233a9b38ff49
+ e188907358e1cefa.3ef5d5705c7a788d.4f2a320ef0683dd7.8d4d8269151369bf
+ 1bd4369f63eac37a
+ after
+ 8b175e90aa9b949c.33508207a2586787.fd445ecb2ec16c98.4ba07640b644127f
+ 3da45132591c27f9.93c7d93702215777.b1495aee07a97a95.01001ea55acc4c6d
+ 10db8d858adb51b4.cee44c8b0b539dea.d952220b9487819c.a320233a9b38ff49
+ e188907358e1cefa.3ef5d5705c7a788d.4f2a320ef0683dd7.8d4d8269151369bf
+ 0000000000000040
+
+VTESTPD_256_1(reg)
+ before
+ a9ff3b4921474c27.8a77d5eae03c5af6.414472538e23220b.f19e07e337576a72
+ 931b8dd2ecb83e71.e873d9d53df7b0d5.311e1f9f40d9d812.997a1c768661c49a
+ 357329a560c9d705.d84a16208c1e8dc2.6ccfd6bf0b28d64b.248aedb4f890067b
+ eb5509301805508f.34c60ab7e8beadea.4ca295218d9d5764.6f9af687aaf3ed40
+ 5476b3dcb8933416
+ after
+ a9ff3b4921474c27.8a77d5eae03c5af6.414472538e23220b.f19e07e337576a72
+ 931b8dd2ecb83e71.e873d9d53df7b0d5.311e1f9f40d9d812.997a1c768661c49a
+ 357329a560c9d705.d84a16208c1e8dc2.6ccfd6bf0b28d64b.248aedb4f890067b
+ eb5509301805508f.34c60ab7e8beadea.4ca295218d9d5764.6f9af687aaf3ed40
+ 0000000000000001
+VTESTPD_256_1(mem)
+ before
+ b0e9a1a03c7e9928.110b2bdeb0f8e8ba.d9b430866de3cb79.2ee5563062c39909
+ 5fc13bbe55bfd6a3.03e38b1bc52ed933.a3e004793897a49a.6fe218582526d6e6
+ 3dc8fd221d63a7b3.1d272353f23460a5.6f16037c65e8f47a.69e6d40572534aa6
+ 26cb63b7b075ca83.ba24f1f3d495b9bd.1721a87b0fe17744.793d87a3e6d532f5
+ fb332e9f1d38ca81
+ after
+ b0e9a1a03c7e9928.110b2bdeb0f8e8ba.d9b430866de3cb79.2ee5563062c39909
+ 5fc13bbe55bfd6a3.03e38b1bc52ed933.a3e004793897a49a.6fe218582526d6e6
+ 3dc8fd221d63a7b3.1d272353f23460a5.6f16037c65e8f47a.69e6d40572534aa6
+ 26cb63b7b075ca83.ba24f1f3d495b9bd.1721a87b0fe17744.793d87a3e6d532f5
+ 0000000000000000
+
+VTESTPD_256_1(reg)
+ before
+ 4c14c463b2094ef4.f696ea6b2a01f940.3825ef6506de1f26.78cf6f63528fe825
+ c62b455c41d3fafa.8af40c29a913f115.f2781b16249acf8e.6eead41e4bfd0449
+ c6c6aef767220940.bcb347de46b86e2f.43687173cc55059e.d53f539a163787db
+ a82ff99fbf83b872.699d16741ffc2bba.8940ebe6979cfd05.899a69c2ce492d08
+ 66c790828f40b1fb
+ after
+ 4c14c463b2094ef4.f696ea6b2a01f940.3825ef6506de1f26.78cf6f63528fe825
+ c62b455c41d3fafa.8af40c29a913f115.f2781b16249acf8e.6eead41e4bfd0449
+ c6c6aef767220940.bcb347de46b86e2f.43687173cc55059e.d53f539a163787db
+ a82ff99fbf83b872.699d16741ffc2bba.8940ebe6979cfd05.899a69c2ce492d08
+ 0000000000000000
+VTESTPD_256_1(mem)
+ before
+ 489246c57628d0e1.c8b324bfe681423b.6c80f6d850e9e5e1.1f4d87dd23f9f26c
+ 0bc607799e0b45e6.829e2ac577a8e548.a32661f7f48d58d1.60db40c30cfb2182
+ 8b304d8924f7ce35.323c071c0f85db44.e95cd5bb27f43fb5.aa361204ed2bc6f1
+ a39d96e223f825fb.34d8b83049a361dc.1aeecd12062858ba.57aaf90c62171c66
+ c582f247084b608c
+ after
+ 489246c57628d0e1.c8b324bfe681423b.6c80f6d850e9e5e1.1f4d87dd23f9f26c
+ 0bc607799e0b45e6.829e2ac577a8e548.a32661f7f48d58d1.60db40c30cfb2182
+ 8b304d8924f7ce35.323c071c0f85db44.e95cd5bb27f43fb5.aa361204ed2bc6f1
+ a39d96e223f825fb.34d8b83049a361dc.1aeecd12062858ba.57aaf90c62171c66
+ 0000000000000001
+
+VTESTPD_256_1(reg)
+ before
+ 4e0bf8217b51ce10.31d75c6eb7180763.e4c0376dc28fb2bb.12a7c6e7ad375d0c
+ 4f92070655b7a29d.10ab1e1afe652f9a.9e3e824015d30b8f.ad553a25372d0ad6
+ 25611b63350817e0.1ce455d311eb5acb.be9f9413dffea801.c7c2a7bac0141d45
+ 2ac530a2b5d16a85.31507e830eb44424.a02f6a53bb99c5c0.3bbb889165fa5084
+ e70c599641eb60c0
+ after
+ 4e0bf8217b51ce10.31d75c6eb7180763.e4c0376dc28fb2bb.12a7c6e7ad375d0c
+ 4f92070655b7a29d.10ab1e1afe652f9a.9e3e824015d30b8f.ad553a25372d0ad6
+ 25611b63350817e0.1ce455d311eb5acb.be9f9413dffea801.c7c2a7bac0141d45
+ 2ac530a2b5d16a85.31507e830eb44424.a02f6a53bb99c5c0.3bbb889165fa5084
+ 0000000000000001
+VTESTPD_256_1(mem)
+ before
+ a68196b671f10824.bb094331719dd737.2ab9161811cea9ce.a03afe6d45329d76
+ 53e6bcdb101a05de.357b4f7a06f899a3.e5ed987d354545f8.190c4ecb1a546dcf
+ cc0645f23b721317.f26550eb0f6fed75.3cb6809d9623d3cc.69f055dbd68c7178
+ ecafafe80d03eefe.4f1542ef288d0f58.0de14b6651770f76.eb340f081464e51d
+ fb2279be706b0469
+ after
+ a68196b671f10824.bb094331719dd737.2ab9161811cea9ce.a03afe6d45329d76
+ 53e6bcdb101a05de.357b4f7a06f899a3.e5ed987d354545f8.190c4ecb1a546dcf
+ cc0645f23b721317.f26550eb0f6fed75.3cb6809d9623d3cc.69f055dbd68c7178
+ ecafafe80d03eefe.4f1542ef288d0f58.0de14b6651770f76.eb340f081464e51d
+ 0000000000000040
+
+VTESTPD_256_2(reg)
+ before
+ f4078d69872a0b09.8eab76a7a3dc52bc.a8d522f2efdf3bf8.333973c3824ab723
+ 342f4975f42f36a9.90c7141d1806fa80.5af2eb60fdefac02.898c76a144aa85ff
+ 15e6a84e5405c0f4.cccf0735888fa374.bfb899a5f04b9f22.eda5cfeab3a23635
+ f577a7604339e697.208ecada108208c5.3472282d647f5004.394ffa8bec3e86f2
+ 4b5774700a8b3062
+ after
+ f4078d69872a0b09.8eab76a7a3dc52bc.a8d522f2efdf3bf8.333973c3824ab723
+ 15e6a84e5405c0f4.cccf0735888fa374.bfb899a5f04b9f22.eda5cfeab3a23635
+ 15e6a84e5405c0f4.cccf0735888fa374.bfb899a5f04b9f22.eda5cfeab3a23635
+ f577a7604339e697.208ecada108208c5.3472282d647f5004.394ffa8bec3e86f2
+ 0000000000000001
+VTESTPD_256_2(mem)
+ before
+ fd89b8862a94f2b0.2f3040175b56e43d.66d2d9faccebe69e.156e9464f415fb53
+ 2cb142b867668608.1e5b71e03be8f693.7b65b080d7d7f92c.bef6dab73c9cdbbb
+ b59b8ef1de0ba897.204535257c7c5744.3c15cc594d51fd9a.8b57f590d99d2de9
+ 7212181faa921589.8f3a8854bc9d44fd.83aca76f4b66ae15.d8dde15d67a62c89
+ 01d49a8881421647
+ after
+ fd89b8862a94f2b0.2f3040175b56e43d.66d2d9faccebe69e.156e9464f415fb53
+ 02764779d56b0d4f.d0cfbfe8a4a91bc2.992d260533141961.ea916b9b0bea04ac
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 7212181faa921589.8f3a8854bc9d44fd.83aca76f4b66ae15.d8dde15d67a62c89
+ 0000000000000040
+
+VTESTPD_256_2(reg)
+ before
+ 62881d7fc3fd25ce.40e45d2de704890a.c88667d897d7f96a.2df7bfafed21c7c9
+ 564565adca6496ca.fcdbd807b36fc045.2875cc1ca8b7b136.17c290064e8e05e1
+ 3b566d7e3102a4e8.80c4059927de7666.0952b58e8cc8a90e.1bd8945e8ab9238a
+ 6c08345e95648cd4.a96b60cf615e669b.c86a1d99de961d9e.160749a5beafdfef
+ e4192ac5057bf33e
+ after
+ 62881d7fc3fd25ce.40e45d2de704890a.c88667d897d7f96a.2df7bfafed21c7c9
+ 3b566d7e3102a4e8.80c4059927de7666.0952b58e8cc8a90e.1bd8945e8ab9238a
+ 3b566d7e3102a4e8.80c4059927de7666.0952b58e8cc8a90e.1bd8945e8ab9238a
+ 6c08345e95648cd4.a96b60cf615e669b.c86a1d99de961d9e.160749a5beafdfef
+ 0000000000000001
+VTESTPD_256_2(mem)
+ before
+ 61dbb3ac7c2a1ba0.45a7b3b991158a39.539c65957dfa4d0d.c20a00a93aae4991
+ 691960453ec71543.227fe8fbc2a1dac4.5a2291d896bee6eb.517c5b2b3d9b6893
+ d99fad7c685e9b53.5edccd91c394b721.9acb5f82c8b6ef5f.d20c298983e9b752
+ 8b39173d15fc6afc.570a61e5317b5ffb.ef614b8030ef2296.a1086630a7257277
+ 1bbb0e8d45dad4b1
+ after
+ 61dbb3ac7c2a1ba0.45a7b3b991158a39.539c65957dfa4d0d.c20a00a93aae4991
+ 9e244c5383d5e45f.ba584c466eea75c6.ac639a6a8205b2f2.3df5ff56c551b66e
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 8b39173d15fc6afc.570a61e5317b5ffb.ef614b8030ef2296.a1086630a7257277
+ 0000000000000040
+
+VTESTPD_256_2(reg)
+ before
+ 9a701d0afa941baa.5cb3197461ac3e69.68549d65a7e10bff.35b1d1bfe9753cbb
+ 7b74901561e0810f.28d82f0d697ad2c6.ec087e7bc253fad8.48876e2a1052f8fa
+ 1a1362191749428b.cb75d6f54972e340.417001951d5c6633.04af9dadc1941381
+ d3998f82b75b9ccb.205688161ca12d03.c1d9211e54888cbb.45f5da331646497a
+ e724a1aa2e755611
+ after
+ 9a701d0afa941baa.5cb3197461ac3e69.68549d65a7e10bff.35b1d1bfe9753cbb
+ 1a1362191749428b.cb75d6f54972e340.417001951d5c6633.04af9dadc1941381
+ 1a1362191749428b.cb75d6f54972e340.417001951d5c6633.04af9dadc1941381
+ d3998f82b75b9ccb.205688161ca12d03.c1d9211e54888cbb.45f5da331646497a
+ 0000000000000001
+VTESTPD_256_2(mem)
+ before
+ c6096efe222cf574.025213bbdea3c97a.0547c35efe136b3a.ca8fda820464a81e
+ be71be191077e3cc.038aea3327ac0545.551402b70cd25b12.b6dd282dc97bf505
+ ab260ce81463dc48.328c11532f038ed7.ec89c10f62ecb7b7.e311088b3e59b01e
+ 69f5d45749fb9c12.eba6838891329ede.a6717d511b6d3b54.ab757508ff8b1515
+ 6c566b10a99c6096
+ after
+ c6096efe222cf574.025213bbdea3c97a.0547c35efe136b3a.ca8fda820464a81e
+ 39f69101ddd30a8b.fdadec44215c3685.fab83ca101ec94c5.3570257dfb9b57e1
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 69f5d45749fb9c12.eba6838891329ede.a6717d511b6d3b54.ab757508ff8b1515
+ 0000000000000040
+
+VTESTPD_256_3(reg)
+ before
+ 8001e60fd718cc4c.d3a99253cc4bde56.8a223c3eeac87203.5f99b169535fa516
+ 44bfe372268b96e4.c710c3c6b8605f41.6b4d38e2d54e46f5.f2ced84327d0af28
+ 15df5ca33182fa09.20f4e29e2945dbff.e97274deee52555e.3dda71cbb2cc16b7
+ 4dac4f1095893368.b9236ac63c060dbb.62dfeba0d25fdcea.1b89f5ed115d95ef
+ 67a9e2955f91e9fb
+ after
+ 8001e60fd718cc4c.d3a99253cc4bde56.8a223c3eeac87203.5f99b169535fa516
+ 44bfe372268b96e4.c710c3c6b8605f41.6b4d38e2d54e46f5.f2ced84327d0af28
+ 15df5ca33182fa09.20f4e29e2945dbff.e97274deee52555e.3dda71cbb2cc16b7
+ 4dac4f1095893368.b9236ac63c060dbb.62dfeba0d25fdcea.1b89f5ed115d95ef
+ 0000000000000000
+VTESTPD_256_3(mem)
+ before
+ ff05b2b0b974ce07.4971b724ed2b7fac.7067da2a0db0b2a2.31df99921d021746
+ be68e3283a110041.657c914bd6f41882.208dabb6b74e86e0.b2bd7a226ac5421e
+ 7f9ff1ebff743bd3.fe17d7f1eb703a96.a4605b5656ed45a0.40c68abb5537981d
+ 207656e323a93ae9.6e8f8782c92c2293.daae65f60797aa0f.3946c6c97be156f0
+ f88929b87751b843
+ after
+ ff05b2b0b974ce07.4971b724ed2b7fac.7067da2a0db0b2a2.31df99921d021746
+ be68e3283a110041.657c914bd6f41882.208dabb6b74e86e0.b2bd7a226ac5421e
+ 7f9ff1ebff743bd3.fe17d7f1eb703a96.a4605b5656ed45a0.40c68abb5537981d
+ 207656e323a93ae9.6e8f8782c92c2293.daae65f60797aa0f.3946c6c97be156f0
+ 0000000000000040
+
+VTESTPD_256_3(reg)
+ before
+ d8dbaff4e612f9c1.7bb990fec3bdbab0.122f9c6a0bb30d26.9c424582e65a7258
+ 378854e964b15617.6e341a27fabb7654.464512154d9134fa.c8e777e60d4259a8
+ 6fdb15048bb90bf0.d3b3704ae4af2b00.661ce5ef2c53d6bc.386a770f9b5a1a2a
+ de21edaffab653f9.87010e539ea695e1.ceff126544842d18.ca97c2e7a9ae720b
+ 583ad35c564a1d77
+ after
+ d8dbaff4e612f9c1.7bb990fec3bdbab0.122f9c6a0bb30d26.9c424582e65a7258
+ 378854e964b15617.6e341a27fabb7654.464512154d9134fa.c8e777e60d4259a8
+ 6fdb15048bb90bf0.d3b3704ae4af2b00.661ce5ef2c53d6bc.386a770f9b5a1a2a
+ de21edaffab653f9.87010e539ea695e1.ceff126544842d18.ca97c2e7a9ae720b
+ 0000000000000001
+VTESTPD_256_3(mem)
+ before
+ bf1f2658bb3bd799.dea6d8584a356cdd.67eb712e44ab7022.da3b94e130b076b9
+ dc1138c9f68c5b9e.cdb6d26919c19049.4d3d13c7f0cb78f1.e61c67d18c64ed4c
+ 89de839a234a66b1.059dd75003e6fce9.16c3720bc1116877.4eee879ff52bcd7c
+ a35085b75d80b400.e4a7e478a330eb68.9f4909e4d189fde2.6efdf1b9079253f6
+ a294a08a5c24bb66
+ after
+ bf1f2658bb3bd799.dea6d8584a356cdd.67eb712e44ab7022.da3b94e130b076b9
+ dc1138c9f68c5b9e.cdb6d26919c19049.4d3d13c7f0cb78f1.e61c67d18c64ed4c
+ 89de839a234a66b1.059dd75003e6fce9.16c3720bc1116877.4eee879ff52bcd7c
+ a35085b75d80b400.e4a7e478a330eb68.9f4909e4d189fde2.6efdf1b9079253f6
+ 0000000000000000
+
+VTESTPD_256_3(reg)
+ before
+ 4601907e936d4077.0634b90cc13a00b4.c41ff44d962c9a73.c29b55403c3ff25e
+ b58ebd0145f920d6.8f569b856a8407fb.0253033b776645b6.5c84d1091f400517
+ 4d88237f1155952e.1882a80e746b8501.fb8d0daee26828dc.49d2f82d9597f038
+ 693bbf64900cdb2c.7e835a94fcfa36f2.091a0f1274c07e91.654f4897bb516fed
+ 8dc83d33ac794064
+ after
+ 4601907e936d4077.0634b90cc13a00b4.c41ff44d962c9a73.c29b55403c3ff25e
+ b58ebd0145f920d6.8f569b856a8407fb.0253033b776645b6.5c84d1091f400517
+ 4d88237f1155952e.1882a80e746b8501.fb8d0daee26828dc.49d2f82d9597f038
+ 693bbf64900cdb2c.7e835a94fcfa36f2.091a0f1274c07e91.654f4897bb516fed
+ 0000000000000040
+VTESTPD_256_3(mem)
+ before
+ 9b0951ed851b1dc6.65f38c1d61ab307b.9d272f011e3ed5f9.894603d3c9fa8483
+ 6cde02b16144c342.9cfc86141dbdcec8.5138a243f5421f42.d75ce75e7ca1765b
+ dc12cb6b5dffee02.6ca1a9b762cef2bf.768330449d12d0fa.4faab61d29418fc8
+ c772280794585932.302ff170cc6ad70b.e8d453f233bba44d.4e7a6d7e6d660c74
+ 2e1a06ebe39d290b
+ after
+ 9b0951ed851b1dc6.65f38c1d61ab307b.9d272f011e3ed5f9.894603d3c9fa8483
+ 6cde02b16144c342.9cfc86141dbdcec8.5138a243f5421f42.d75ce75e7ca1765b
+ dc12cb6b5dffee02.6ca1a9b762cef2bf.768330449d12d0fa.4faab61d29418fc8
+ c772280794585932.302ff170cc6ad70b.e8d453f233bba44d.4e7a6d7e6d660c74
+ 0000000000000000
+
+VTESTPD_256_3(reg)
+ before
+ 4cd47fd22871223b.09cb9671225cc100.43f35badf61eba59.83f78938d2485667
+ 04f5d39ed76e32ad.7ee78f962416e295.0337e2d97d76d755.23b84d0297c5a373
+ b2c8febb8d219610.01939160b6927720.ca47825ffcfc6aaa.a4e21b3c9d3f469d
+ b29bfd95e5158a0e.709b17bdf3dc3ecb.f67138ad0f3eaf05.e24270d201c1fd12
+ b9a5c6b0de5782fe
+ after
+ 4cd47fd22871223b.09cb9671225cc100.43f35badf61eba59.83f78938d2485667
+ 04f5d39ed76e32ad.7ee78f962416e295.0337e2d97d76d755.23b84d0297c5a373
+ b2c8febb8d219610.01939160b6927720.ca47825ffcfc6aaa.a4e21b3c9d3f469d
+ b29bfd95e5158a0e.709b17bdf3dc3ecb.f67138ad0f3eaf05.e24270d201c1fd12
+ 0000000000000041
+VTESTPD_256_3(mem)
+ before
+ 04d59bc2510e928c.60b8cb987cd64a53.a6ca9d98f701f1c2.e100fe2f53c7e111
+ a19f6af475f1e8e9.186d6430edf1118d.7feea0dddf0d4c32.e93fd24f63243d7b
+ 6bceb033670c4141.3504c4cad5f11c65.d7d19a77c60a0d47.687baf7adce0feee
+ 3e30e769426c59bf.15cae7d0cf63a68a.89400954c906ee2c.bb00911c5a876117
+ 3f1a75a277a6a2a2
+ after
+ 04d59bc2510e928c.60b8cb987cd64a53.a6ca9d98f701f1c2.e100fe2f53c7e111
+ a19f6af475f1e8e9.186d6430edf1118d.7feea0dddf0d4c32.e93fd24f63243d7b
+ 6bceb033670c4141.3504c4cad5f11c65.d7d19a77c60a0d47.687baf7adce0feee
+ 3e30e769426c59bf.15cae7d0cf63a68a.89400954c906ee2c.bb00911c5a876117
+ 0000000000000001
+
+VTESTPD_256_3(reg)
+ before
+ 4e155576d2c8fd3a.f58f8d84221cec90.130bcaaf77d2eda6.73076860030dac0e
+ 453d2f060479ae8c.6eb91d6f2428b5df.8b1267d46aca2b65.70f23485912a0219
+ 81ddfebdac46f044.84781316649d72d9.d92dbcaa44d79d74.5bcde7b08e69ad78
+ 5c42bf0663ba000d.1299eb65fd86dca9.58a6c59ca0867e7f.1263ffcd17d66958
+ 7082f7c9477ef2e4
+ after
+ 4e155576d2c8fd3a.f58f8d84221cec90.130bcaaf77d2eda6.73076860030dac0e
+ 453d2f060479ae8c.6eb91d6f2428b5df.8b1267d46aca2b65.70f23485912a0219
+ 81ddfebdac46f044.84781316649d72d9.d92dbcaa44d79d74.5bcde7b08e69ad78
+ 5c42bf0663ba000d.1299eb65fd86dca9.58a6c59ca0867e7f.1263ffcd17d66958
+ 0000000000000040
+VTESTPD_256_3(mem)
+ before
+ 50f44b8e3b6c0449.33b86c4fc7611993.f6e722480befb27d.66cb7c181a620c31
+ 9086780a0eac5ab2.628b030374c87983.0a3033ababe5ae7e.5ee6df894ff88137
+ 0a04f928dd4bb14c.45077f8f057a5a89.2c3f9a7af8738ddb.9b43e95bdad3193d
+ 9c3a49d4c354c443.3878dc5d1703f951.36dfd3a10fa60bbd.7b3096fa587f12ee
+ 59f8e2d36489a6f7
+ after
+ 50f44b8e3b6c0449.33b86c4fc7611993.f6e722480befb27d.66cb7c181a620c31
+ 9086780a0eac5ab2.628b030374c87983.0a3033ababe5ae7e.5ee6df894ff88137
+ 0a04f928dd4bb14c.45077f8f057a5a89.2c3f9a7af8738ddb.9b43e95bdad3193d
+ 9c3a49d4c354c443.3878dc5d1703f951.36dfd3a10fa60bbd.7b3096fa587f12ee
+ 0000000000000040
+
+VTESTPD_256_3(reg)
+ before
+ 90e6ca509b7c1203.20f3e7fadcd450c2.972917da45f09186.06dd5b0d0b88e353
+ 7e4848df98e491bf.73fd4c8645d511f6.be682a722bcc5fd4.7605aca80927d3c7
+ 7d685aeaf84d61d6.7222f5641a66c30b.097f139266249fe8.63234460248f9446
+ eb93fbdf5644bcf5.f72f5f807690222c.d4bbcda492838d6e.aa039f1f79cbe5fb
+ 257037d323e78013
+ after
+ 90e6ca509b7c1203.20f3e7fadcd450c2.972917da45f09186.06dd5b0d0b88e353
+ 7e4848df98e491bf.73fd4c8645d511f6.be682a722bcc5fd4.7605aca80927d3c7
+ 7d685aeaf84d61d6.7222f5641a66c30b.097f139266249fe8.63234460248f9446
+ eb93fbdf5644bcf5.f72f5f807690222c.d4bbcda492838d6e.aa039f1f79cbe5fb
+ 0000000000000001
+VTESTPD_256_3(mem)
+ before
+ b13889673fef22b9.221428284f55dec8.dff005c67561e985.7b6854164a756412
+ 2b2512c7e8f0871a.7f39db337e0a05fa.0731632334e4d544.5ad2a5532a86617f
+ 6d044ddf3af56b62.5f4d126b80f16b38.49bdf681ce26a192.cd44bbc7cf43c061
+ 54a1b79b520b89bc.1c9bc83cf0964d2e.826238ce60310b9e.300c92ded437bd65
+ df742604d6ef9337
+ after
+ b13889673fef22b9.221428284f55dec8.dff005c67561e985.7b6854164a756412
+ 2b2512c7e8f0871a.7f39db337e0a05fa.0731632334e4d544.5ad2a5532a86617f
+ 6d044ddf3af56b62.5f4d126b80f16b38.49bdf681ce26a192.cd44bbc7cf43c061
+ 54a1b79b520b89bc.1c9bc83cf0964d2e.826238ce60310b9e.300c92ded437bd65
+ 0000000000000000
+
+VTESTPD_256_3(reg)
+ before
+ 35c973a570f57f82.bcc8cae74c3d9e55.1370fa126a83e687.8eeaa7f40514cd92
+ 9057762d3fd8bcf3.814404b043976558.a118a2598b4674ef.4922bee1dad8a39b
+ 4b6a2a08de218836.7fe3e0e053269cf2.20dfbe7eef6b3114.90d6fa80fa8b4be4
+ c24d8ba3ea5e1df6.936fda6599f5fd4f.ed1149eb317c599f.3dd2d5bd82387f9a
+ 2de2cd848decfce8
+ after
+ 35c973a570f57f82.bcc8cae74c3d9e55.1370fa126a83e687.8eeaa7f40514cd92
+ 9057762d3fd8bcf3.814404b043976558.a118a2598b4674ef.4922bee1dad8a39b
+ 4b6a2a08de218836.7fe3e0e053269cf2.20dfbe7eef6b3114.90d6fa80fa8b4be4
+ c24d8ba3ea5e1df6.936fda6599f5fd4f.ed1149eb317c599f.3dd2d5bd82387f9a
+ 0000000000000001
+VTESTPD_256_3(mem)
+ before
+ 3cd25dc138b27efb.504e9568fe1ab8e0.97b56e293110459a.64f93f0ded072a3f
+ 466d01619e96c0ff.53b745c5b6e2949f.6881191a36832f00.e1e59c51c098de9e
+ 2780354edba57f1f.25d59525af41efe0.e29f5523c45b78ac.c01f5d2245bab268
+ bbd776750cea7787.24f483f385c3034e.e0dba030f8a4dccb.5ef47deb19f9e24b
+ 15b0f81ad7e1a9f0
+ after
+ 3cd25dc138b27efb.504e9568fe1ab8e0.97b56e293110459a.64f93f0ded072a3f
+ 466d01619e96c0ff.53b745c5b6e2949f.6881191a36832f00.e1e59c51c098de9e
+ 2780354edba57f1f.25d59525af41efe0.e29f5523c45b78ac.c01f5d2245bab268
+ bbd776750cea7787.24f483f385c3034e.e0dba030f8a4dccb.5ef47deb19f9e24b
+ 0000000000000001
+
+VTESTPD_256_3(reg)
+ before
+ 429fca1a1cff4406.dd3e3fc34d716365.ab600a9dd3f50c96.4000762ded681789
+ 410cf05783deef37.6b810c23b94701e3.1565278e35614864.dddb5106c0b5e411
+ 6d45643da90ae52f.406c59806c770b2d.c04ed4324896f163.9339afa78c970090
+ 249424392910649c.38caa3c8830d3d71.06690ff6a81d4440.3ee40bfc6d182731
+ baa9e1f281461521
+ after
+ 429fca1a1cff4406.dd3e3fc34d716365.ab600a9dd3f50c96.4000762ded681789
+ 410cf05783deef37.6b810c23b94701e3.1565278e35614864.dddb5106c0b5e411
+ 6d45643da90ae52f.406c59806c770b2d.c04ed4324896f163.9339afa78c970090
+ 249424392910649c.38caa3c8830d3d71.06690ff6a81d4440.3ee40bfc6d182731
+ 0000000000000040
+VTESTPD_256_3(mem)
+ before
+ e253ad73e12d858c.c1462bb5a07ba627.2f6864e6191655d8.4400d344f0847ca7
+ 94b0eb6dabd7349d.a0a7761ea9d8e77f.00131ac64b9d0d91.d7601c89bc57d743
+ ab8a18cafb52de80.1d03ffe1e0b2654e.8995405435ae22c6.19d5e732a9208fc0
+ 03afaf78ecaa3e63.94a6c468e2955a40.a5ba537cf1564fa3.67ab2ea9526de0cc
+ 1e2def5c54ca0811
+ after
+ e253ad73e12d858c.c1462bb5a07ba627.2f6864e6191655d8.4400d344f0847ca7
+ 94b0eb6dabd7349d.a0a7761ea9d8e77f.00131ac64b9d0d91.d7601c89bc57d743
+ ab8a18cafb52de80.1d03ffe1e0b2654e.8995405435ae22c6.19d5e732a9208fc0
+ 03afaf78ecaa3e63.94a6c468e2955a40.a5ba537cf1564fa3.67ab2ea9526de0cc
+ 0000000000000000
+
+VTESTPD_256_3(reg)
+ before
+ 98a925b64ac1413b.77e92c629ae91170.61dbc0214b0d0302.2f50cd2b9ea05155
+ 3269cd22d1e0c8f7.e5050c74221d13d3.dff0ef77b6a79b40.05222c4b5598e408
+ 48bae10e84b3d9f1.27cec99aa05200b9.6c2f4ed6bfee5fa5.02fbebc9354bc4e7
+ 36e85fe500c4afd4.1b12e1c02f93934e.63e5d7aa036f8bde.01a8869257c4ad1f
+ e0f57a91d90f5adc
+ after
+ 98a925b64ac1413b.77e92c629ae91170.61dbc0214b0d0302.2f50cd2b9ea05155
+ 3269cd22d1e0c8f7.e5050c74221d13d3.dff0ef77b6a79b40.05222c4b5598e408
+ 48bae10e84b3d9f1.27cec99aa05200b9.6c2f4ed6bfee5fa5.02fbebc9354bc4e7
+ 36e85fe500c4afd4.1b12e1c02f93934e.63e5d7aa036f8bde.01a8869257c4ad1f
+ 0000000000000040
+VTESTPD_256_3(mem)
+ before
+ 79ae41b1d7398849.593f4213e0a1874d.9b9ccfd2ebec89bd.1f5e885f1db55b97
+ aa9f59e06c4df292.0b0b8605c0d69d07.853710bcf1699e33.fee65c61aa4c0a7b
+ 4d943d09b45855e5.a99728253dee2caf.b3b01e6b5c178ddc.5ac8501c45c1d637
+ 3f586a18cc656d6b.8f3122e0f37571f1.03d377c9490113e3.91525efc8b9ff876
+ fdce846e1772afe5
+ after
+ 79ae41b1d7398849.593f4213e0a1874d.9b9ccfd2ebec89bd.1f5e885f1db55b97
+ aa9f59e06c4df292.0b0b8605c0d69d07.853710bcf1699e33.fee65c61aa4c0a7b
+ 4d943d09b45855e5.a99728253dee2caf.b3b01e6b5c178ddc.5ac8501c45c1d637
+ 3f586a18cc656d6b.8f3122e0f37571f1.03d377c9490113e3.91525efc8b9ff876
+ 0000000000000040
+
+VTESTPD_256_3(reg)
+ before
+ fc89bddc86c6352f.5db85af9d080f653.192372a37df7a878.4f6c96c4d334ec74
+ e8cf05b47328c701.81808b99dbb5acc7.a3ba13d877010df1.7447f74617bad4bd
+ 1fec58617b24a107.887c78e209114af4.894202ed7e1edb07.4f2f163d30a286e7
+ fb2bb34f3944feec.4f789dc1779f8d05.2606394d2ddb5067.baf270943af5bf21
+ 925a803753c13b95
+ after
+ fc89bddc86c6352f.5db85af9d080f653.192372a37df7a878.4f6c96c4d334ec74
+ e8cf05b47328c701.81808b99dbb5acc7.a3ba13d877010df1.7447f74617bad4bd
+ 1fec58617b24a107.887c78e209114af4.894202ed7e1edb07.4f2f163d30a286e7
+ fb2bb34f3944feec.4f789dc1779f8d05.2606394d2ddb5067.baf270943af5bf21
+ 0000000000000000
+VTESTPD_256_3(mem)
+ before
+ b334c2129411b570.dada11e94a161c5d.b0407723406c3027.d854b66421c2a5bd
+ fa4cb2111bf2eadd.16436e9d49263406.889f80f28183f185.fa76749ef66119b4
+ 416ecc20046f9609.0cb3c6d6d2fe8592.b363361c55f08a4c.e8ba6f674644e6f8
+ 65658d2c6a94751f.18761601822c49ad.0e56148cd9bfb7a8.fe6aa32bb0f64937
+ 98d30d56cd037e1b
+ after
+ b334c2129411b570.dada11e94a161c5d.b0407723406c3027.d854b66421c2a5bd
+ fa4cb2111bf2eadd.16436e9d49263406.889f80f28183f185.fa76749ef66119b4
+ 416ecc20046f9609.0cb3c6d6d2fe8592.b363361c55f08a4c.e8ba6f674644e6f8
+ 65658d2c6a94751f.18761601822c49ad.0e56148cd9bfb7a8.fe6aa32bb0f64937
+ 0000000000000000
+
+VBLENDVPS_128(reg)
+ before
+ 1140a8543bf8c050.42ff701f696d424c.97d85988f53cbd05.7345962e28fd36c4
+ c7ff7092965f4c83.b406f1e71e07babc.e3258ad8c5b81d43.bffc39ee5fb5c1cd
+ 155b617a79c75e60.97478c6ea46d999a.59a9a85e912ea516.ce4778b899f415ee
+ 569f787a81b93292.c78ebea218ac9b13.55afac84f32a9028.7cf1cf78f3c5ee54
+ a5c8ba1a8834072b
+ after
+ 0000000000000000.0000000000000000.e3258ad8912ea516.bffc39ee99f415ee
+ c7ff7092965f4c83.b406f1e71e07babc.e3258ad8c5b81d43.bffc39ee5fb5c1cd
+ 155b617a79c75e60.97478c6ea46d999a.59a9a85e912ea516.ce4778b899f415ee
+ 569f787a81b93292.c78ebea218ac9b13.55afac84f32a9028.7cf1cf78f3c5ee54
+ a5c8ba1a8834072b
+VBLENDVPS_128(mem)
+ before
+ 2596b58b754e1d9e.e818affc49c303c6.20a7026e96cf7b52.338494b887361b25
+ d8283db5d51eecda.2512046e6d700ea8.7e5ed4be38e2f684.4f745a65eae181bb
+ 9a4acd86c4b02f0a.6bd9723b8a4d8fe3.bd7eb07e1df2c7d5.05cbfcf7b7b40093
+ 46c8e1e85f11a45b.14b9f6cf3ce5c124.b9d4129a5e0aac70.b1d576da8b3dd25c
+ afdec27a010734c0
+ after
+ 2596b58b754e1d9e.e818affc49c303c6.20a7026e96cf7b52.338494b887361b25
+ d8283db5d51eecda.2512046e6d700ea8.7e5ed4be38e2f684.4f745a65eae181bb
+ 0000000000000000.0000000000000000.20a7026e38e2f684.338494b887361b25
+ 46c8e1e85f11a45b.14b9f6cf3ce5c124.b9d4129a5e0aac70.b1d576da8b3dd25c
+ afdec27a010734c0
+
+VBLENDVPS_128(reg)
+ before
+ 5b31de43b69e616b.ba6df5c9c14c05f9.7efd8a961ec4e116.4e2d77fe1a365f81
+ 111bc5a1458f960b.d1078514076d0e0f.03f32cfccc772b66.57535a966a839d36
+ 2de873004a650f49.67600eb54d817dc9.01e5d76ee389dbbf.b213374f6cfc21b9
+ 0be4e4cd63ad08d4.58450b98ad930c55.d2208756fe862cce.3a388a133cada836
+ cb90d0d0f5a3eeda
+ after
+ 0000000000000000.0000000000000000.01e5d76ee389dbbf.57535a966a839d36
+ 111bc5a1458f960b.d1078514076d0e0f.03f32cfccc772b66.57535a966a839d36
+ 2de873004a650f49.67600eb54d817dc9.01e5d76ee389dbbf.b213374f6cfc21b9
+ 0be4e4cd63ad08d4.58450b98ad930c55.d2208756fe862cce.3a388a133cada836
+ cb90d0d0f5a3eeda
+VBLENDVPS_128(mem)
+ before
+ 40e58470b4e9afd1.075b157229f2bc56.7f82f8a946af78dd.d3f03921bafb5b3f
+ 770522e1948ba646.7d99015d3ac0687b.bae352d432e27c8d.61a1e83cb373a4bd
+ 4bba260eb1969166.c8eaa4f832a348f0.e43493058d37d592.d67e8f12837a42f5
+ 97d10ce32815295d.4699fab1ac289861.d840392974ba3f18.8fd52d0ec89d7292
+ e8f0bb9e1e677041
+ after
+ 40e58470b4e9afd1.075b157229f2bc56.7f82f8a946af78dd.d3f03921bafb5b3f
+ 770522e1948ba646.7d99015d3ac0687b.bae352d432e27c8d.61a1e83cb373a4bd
+ 0000000000000000.0000000000000000.7f82f8a932e27c8d.d3f03921bafb5b3f
+ 97d10ce32815295d.4699fab1ac289861.d840392974ba3f18.8fd52d0ec89d7292
+ e8f0bb9e1e677041
+
+VBLENDVPS_128(reg)
+ before
+ 3e1c362d206478ae.3915514c14152d56.52f3fff344da9379.74d5bf2a0278764a
+ eba59b276b21c584.0b54703592a0577e.4744b02a974676e5.92bda1f6537c3655
+ 4cd7e5f89a299470.eb59e58abec46400.83d808c240f77d51.10c55c7784d33a65
+ bdfd100c4a08211e.b3ef2c37b28d1009.61fb0327dc79e368.c8b96a9bb1873fa5
+ 9865494df5a60042
+ after
+ 0000000000000000.0000000000000000.4744b02a40f77d51.10c55c7784d33a65
+ eba59b276b21c584.0b54703592a0577e.4744b02a974676e5.92bda1f6537c3655
+ 4cd7e5f89a299470.eb59e58abec46400.83d808c240f77d51.10c55c7784d33a65
+ bdfd100c4a08211e.b3ef2c37b28d1009.61fb0327dc79e368.c8b96a9bb1873fa5
+ 9865494df5a60042
+VBLENDVPS_128(mem)
+ before
+ 5a9474796d3c3a67.9a6519d0164ba839.41e3c1298d0616c4.3cf89dc50658e5d7
+ ec14680b3454a941.3f59faae9a7d646d.6f01214a683b345e.721dd3095b21bf49
+ 28af9fef66fa09fb.0827b114732b9267.1b15c78862382303.5db49f5d7660ad6b
+ eb329711203a16c2.5119396c3ddf6dd3.1feb2fce940aa2de.5b0aff2ff49feae8
+ c66befe9706cb36d
+ after
+ 5a9474796d3c3a67.9a6519d0164ba839.41e3c1298d0616c4.3cf89dc50658e5d7
+ ec14680b3454a941.3f59faae9a7d646d.6f01214a683b345e.721dd3095b21bf49
+ 0000000000000000.0000000000000000.6f01214a8d0616c4.721dd3090658e5d7
+ eb329711203a16c2.5119396c3ddf6dd3.1feb2fce940aa2de.5b0aff2ff49feae8
+ c66befe9706cb36d
+
+VBLENDVPS_256(reg)
+ before
+ fc2369f9875344a6.1269cb5d7d218bc2.767b8f249227335c.584ed6071dbc6b1c
+ 577e6bcad4ded83e.7720b7c09aba2526.d39bada7118f1eaf.a30c3621165b3be9
+ 34c7f0c8f39bace2.f722d82493129f1b.c4c4916054a26b78.daefcd079df2ce70
+ f04bf45f8215fc3e.6e3da8778234b7cc.a54136bdf7ec5562.dac416a5ce8de0dd
+ 7f578de7c4382c5e
+ after
+ 34c7f0c8f39bace2.7720b7c093129f1b.c4c4916054a26b78.daefcd079df2ce70
+ 577e6bcad4ded83e.7720b7c09aba2526.d39bada7118f1eaf.a30c3621165b3be9
+ 34c7f0c8f39bace2.f722d82493129f1b.c4c4916054a26b78.daefcd079df2ce70
+ f04bf45f8215fc3e.6e3da8778234b7cc.a54136bdf7ec5562.dac416a5ce8de0dd
+ 7f578de7c4382c5e
+VBLENDVPS_256(mem)
+ before
+ a574afba9b006f1c.e55773fb1ad904fd.b83ba5a4862c2766.d15f982997f9191a
+ 28e6f60870f06446.703569085972ffcb.b2e94a96b806ab15.a66bb311cf56f34b
+ e57be0be5f15c906.ed32d3f2da6d2a55.3613133b37cf0104.7fae84df3c8e1fa2
+ b6fde8c9837a5888.b999ac263a54c147.21857d7e1c93e360.b8770600792ed8cb
+ ac1135e123c15b71
+ after
+ a574afba9b006f1c.e55773fb1ad904fd.b83ba5a4862c2766.d15f982997f9191a
+ 28e6f60870f06446.703569085972ffcb.b2e94a96b806ab15.a66bb311cf56f34b
+ a574afba9b006f1c.e55773fb5972ffcb.b2e94a96b806ab15.d15f9829cf56f34b
+ b6fde8c9837a5888.b999ac263a54c147.21857d7e1c93e360.b8770600792ed8cb
+ ac1135e123c15b71
+
+VBLENDVPS_256(reg)
+ before
+ b9c70decd5d3e441.78398b13f82bcefa.2eb8f00e15b5ff4d.4f0b034b855c0e54
+ 39e78b8f2bf1afe6.07fb438adb35e685.a9d99c18061c2212.9c71218f8e383e0d
+ 8abba934c2a5f70d.3f0f8e1947a35d58.8649aaaea9136442.e482533452322eb7
+ 07906549367ef961.fc41e7ac5981ef9d.2155183e9b28018b.030b1527ee579b7d
+ d5d8e4557db2418c
+ after
+ 39e78b8f2bf1afe6.3f0f8e19db35e685.a9d99c18a9136442.9c71218f52322eb7
+ 39e78b8f2bf1afe6.07fb438adb35e685.a9d99c18061c2212.9c71218f8e383e0d
+ 8abba934c2a5f70d.3f0f8e1947a35d58.8649aaaea9136442.e482533452322eb7
+ 07906549367ef961.fc41e7ac5981ef9d.2155183e9b28018b.030b1527ee579b7d
+ d5d8e4557db2418c
+VBLENDVPS_256(mem)
+ before
+ 36b53ba81b4fdb0f.0bb2bb392205f18f.1a5cca2f2cdc5880.d646e13377e73796
+ 016e960ee53b2733.f46ca57022c81a43.742eb48eddbf532e.016b01f9dadb4012
+ 14cf7171f781df24.1c0c205ad353b128.e8811fb587369dd3.fe0f75fc5f9058a9
+ 4aa348bf6b2dbf0d.e1dc2963d130f2eb.51228990474ef29b.297d37a8a392bd07
+ de034569416ea9d9
+ after
+ 36b53ba81b4fdb0f.0bb2bb392205f18f.1a5cca2f2cdc5880.d646e13377e73796
+ 016e960ee53b2733.f46ca57022c81a43.742eb48eddbf532e.016b01f9dadb4012
+ 016e960ee53b2733.0bb2bb392205f18f.742eb48eddbf532e.016b01f977e73796
+ 4aa348bf6b2dbf0d.e1dc2963d130f2eb.51228990474ef29b.297d37a8a392bd07
+ de034569416ea9d9
+
+VBLENDVPS_256(reg)
+ before
+ 79eb9bacd5af59cb.7fb898e3604c851b.9d2abbf7b7ed1938.8bdd6d0c38120eb0
+ 568233dbfce20989.8fd8dcc9f0e9eb79.ad40d383211561ba.727d4813778eac41
+ d1140a635291f4be.55d0905d3710ae54.6e6b6b71ac35071d.e1d094931fcf8978
+ 45ec1db1724b5716.af6c308b52ce89d7.3af6812ff3d8470f.b6a0cf764ce06182
+ ccbb74aa1bcdef8a
+ after
+ 568233dbfce20989.55d0905df0e9eb79.ad40d383ac35071d.e1d09493778eac41
+ 568233dbfce20989.8fd8dcc9f0e9eb79.ad40d383211561ba.727d4813778eac41
+ d1140a635291f4be.55d0905d3710ae54.6e6b6b71ac35071d.e1d094931fcf8978
+ 45ec1db1724b5716.af6c308b52ce89d7.3af6812ff3d8470f.b6a0cf764ce06182
+ ccbb74aa1bcdef8a
+VBLENDVPS_256(mem)
+ before
+ feebff1aa8a3f0bd.10586730f9996e3e.787739405c2e3930.6e2f1027938a5c39
+ 2afdedb20e6d2047.8da2e44b810975e2.8bbf2666723c7a88.666014c727d8844a
+ 2abdb85e69373b53.18179170a926a7ad.c60e73ebaf05080e.7fd7897a4c4df8ec
+ dcf6de0ad60efc0d.0c03690a0b7d414c.03319cb930949feb.13de6cac9d76f7cc
+ 7fc2b7c9b6ddbb95
+ after
+ feebff1aa8a3f0bd.10586730f9996e3e.787739405c2e3930.6e2f1027938a5c39
+ 2afdedb20e6d2047.8da2e44b810975e2.8bbf2666723c7a88.666014c727d8844a
+ feebff1aa8a3f0bd.8da2e44b810975e2.8bbf2666723c7a88.666014c7938a5c39
+ dcf6de0ad60efc0d.0c03690a0b7d414c.03319cb930949feb.13de6cac9d76f7cc
+ 7fc2b7c9b6ddbb95
+
+VBLENDVPD_128(reg)
+ before
+ 1fcf683d341081f4.1a76daa270fd20a3.c7b2678543997e6b.20f41dbe10f6fa4e
+ 4f507b74b39b8594.c20728125410633f.a3708a4dee069cb5.f72373e56b35d661
+ 6b93eadbce080322.ae7645479d54800d.fe89cbcfa750d5d7.668a19195e60ee51
+ cfe2b3dc22e6364a.bc8fac2b68d4343a.334827750b04667c.47f58b480580ff49
+ 782f455d7ba3c576
+ after
+ 0000000000000000.0000000000000000.a3708a4dee069cb5.f72373e56b35d661
+ 4f507b74b39b8594.c20728125410633f.a3708a4dee069cb5.f72373e56b35d661
+ 6b93eadbce080322.ae7645479d54800d.fe89cbcfa750d5d7.668a19195e60ee51
+ cfe2b3dc22e6364a.bc8fac2b68d4343a.334827750b04667c.47f58b480580ff49
+ 782f455d7ba3c576
+VBLENDVPD_128(mem)
+ before
+ d305c445dcd4fc03.d78ad0e44abe5bb7.c61ed8acd09d3bf2.9dfa9badb5ae8a51
+ 354483ea451f601d.dfd74060e21eae16.aaef48b5f2ba5160.9aeb22e142d87f01
+ 7bb5fe39d291acf0.4315fcbb87916a12.42cd7531e93731b1.8467b87f4d107f39
+ 7f27b11e9d359da7.5f900160d4a3cc58.6b86dd0ed2209810.b8ba5af173e1c6a5
+ 933002a54fd892f0
+ after
+ d305c445dcd4fc03.d78ad0e44abe5bb7.c61ed8acd09d3bf2.9dfa9badb5ae8a51
+ 354483ea451f601d.dfd74060e21eae16.aaef48b5f2ba5160.9aeb22e142d87f01
+ 0000000000000000.0000000000000000.aaef48b5f2ba5160.9dfa9badb5ae8a51
+ 7f27b11e9d359da7.5f900160d4a3cc58.6b86dd0ed2209810.b8ba5af173e1c6a5
+ 933002a54fd892f0
+
+VBLENDVPD_128(reg)
+ before
+ 6f14ae067d801dc7.1e651886c518ee6f.8f944cbd66e11093.01e4fa37c88242aa
+ a9b459809a65a4d6.343ab05c64455d74.2f6cd83dd8d67171.e1b44a98e768eaab
+ 9e5a007f421463c8.9d74f48b96c8a4e1.9b65a14cc70f2d9b.e5c2491d4ddf4d3e
+ a8539d6f10189549.36dd600178ae7fe2.2ecba456ce177ec0.eada71b313f22790
+ ccc7404457ad34cc
+ after
+ 0000000000000000.0000000000000000.2f6cd83dd8d67171.e5c2491d4ddf4d3e
+ a9b459809a65a4d6.343ab05c64455d74.2f6cd83dd8d67171.e1b44a98e768eaab
+ 9e5a007f421463c8.9d74f48b96c8a4e1.9b65a14cc70f2d9b.e5c2491d4ddf4d3e
+ a8539d6f10189549.36dd600178ae7fe2.2ecba456ce177ec0.eada71b313f22790
+ ccc7404457ad34cc
+VBLENDVPD_128(mem)
+ before
+ 675731bd341d2f1f.24eb2ebda0fd7706.d94270a92502aca4.46eadbc88a7aa08a
+ 9754c00bc74dd5b5.6e6daed38f5045ab.636fa16fb9d0e553.3e0e440c96c4d1a5
+ 388b69192c49e2b9.e327191e799c3ae4.b0306d3f5224e71b.7283da8f8f824bbe
+ 26c8a9d27e1d1258.dd636b0bf96e935c.9c505205090b6e27.3d9499be103f4b81
+ fd8e7e03b6880c99
+ after
+ 675731bd341d2f1f.24eb2ebda0fd7706.d94270a92502aca4.46eadbc88a7aa08a
+ 9754c00bc74dd5b5.6e6daed38f5045ab.636fa16fb9d0e553.3e0e440c96c4d1a5
+ 0000000000000000.0000000000000000.d94270a92502aca4.3e0e440c96c4d1a5
+ 26c8a9d27e1d1258.dd636b0bf96e935c.9c505205090b6e27.3d9499be103f4b81
+ fd8e7e03b6880c99
+
+VBLENDVPD_128(reg)
+ before
+ 0cbe84cc1ce8cbb3.3dd7fb24d9d620bd.b96fa105ab508cbf.039dccadfc9135a3
+ c86ea684deebc47b.5984dafa5a80c915.d395b6772cd061bb.c1e1552447c0f9bc
+ 8beae397991e339c.569ac5401c25c88c.8722a6cf177a4df9.b2e96b5405a6769e
+ b3803471e90c54c2.10e735e23cd3db4d.31616d7809d98d28.b281882b524e6774
+ 9c752a934bc58a6b
+ after
+ 0000000000000000.0000000000000000.d395b6772cd061bb.b2e96b5405a6769e
+ c86ea684deebc47b.5984dafa5a80c915.d395b6772cd061bb.c1e1552447c0f9bc
+ 8beae397991e339c.569ac5401c25c88c.8722a6cf177a4df9.b2e96b5405a6769e
+ b3803471e90c54c2.10e735e23cd3db4d.31616d7809d98d28.b281882b524e6774
+ 9c752a934bc58a6b
+VBLENDVPD_128(mem)
+ before
+ 4e90cd7a0c1699af.9a7b977e6941629b.6335a8ccd596bc85.2da007de9d795df2
+ a3a0ebcbb04d506b.9e26062ab54a9ad1.2b5199ea0478285f.d72a716d70e6f903
+ 776f027253776dcc.19ce7fe16ab23710.43078429e487da08.8b4aa6921dad9c08
+ a6ca8d5b129faafd.69bffe1023057605.8922e57391cf8fac.a54da2b7405983ad
+ 817f61497676e99e
+ after
+ 4e90cd7a0c1699af.9a7b977e6941629b.6335a8ccd596bc85.2da007de9d795df2
+ a3a0ebcbb04d506b.9e26062ab54a9ad1.2b5199ea0478285f.d72a716d70e6f903
+ 0000000000000000.0000000000000000.6335a8ccd596bc85.2da007de9d795df2
+ a6ca8d5b129faafd.69bffe1023057605.8922e57391cf8fac.a54da2b7405983ad
+ 817f61497676e99e
+
+VBLENDVPD_256(reg)
+ before
+ 7a2ce0b55b910c86.0b7d087208d1c42b.e8457d217dcf935c.d87039b6285a0376
+ eea01a658a352611.8454efa3521a7682.f3acfa82139dcac0.0cbbfadcc536f293
+ 38260bc79fef74ec.ec1bbfda0b857d2d.e740709d82fb57de.00d1a6d3836f172e
+ b40baf46374a31c3.1e9df304501f9558.1e4cdbe065747561.927cb8867e0f3074
+ 9c89ade1d324f690
+ after
+ 38260bc79fef74ec.8454efa3521a7682.f3acfa82139dcac0.00d1a6d3836f172e
+ eea01a658a352611.8454efa3521a7682.f3acfa82139dcac0.0cbbfadcc536f293
+ 38260bc79fef74ec.ec1bbfda0b857d2d.e740709d82fb57de.00d1a6d3836f172e
+ b40baf46374a31c3.1e9df304501f9558.1e4cdbe065747561.927cb8867e0f3074
+ 9c89ade1d324f690
+VBLENDVPD_256(mem)
+ before
+ fcc400d09eba28af.bd9c024eeed29b41.f8a8070b3cf27a31.f51d37b6599461f6
+ 8df82c3ffadc80fd.b123014b5f14ec13.540677ddec0ce8e2.c800818bf9e75649
+ 2af3af1a0396bba5.ebeda7a9269a60e5.1084bf647b799a97.f33fb3cbe2fa9205
+ b07f054ed6f495d4.c645f0d4e0f33562.06ee5c8e05444d7d.d226cbe2af584fd7
+ c203c53cfc8dca6a
+ after
+ fcc400d09eba28af.bd9c024eeed29b41.f8a8070b3cf27a31.f51d37b6599461f6
+ 8df82c3ffadc80fd.b123014b5f14ec13.540677ddec0ce8e2.c800818bf9e75649
+ fcc400d09eba28af.bd9c024eeed29b41.540677ddec0ce8e2.f51d37b6599461f6
+ b07f054ed6f495d4.c645f0d4e0f33562.06ee5c8e05444d7d.d226cbe2af584fd7
+ c203c53cfc8dca6a
+
+VBLENDVPD_256(reg)
+ before
+ 1d219b4566263e6b.fc69a8c58e03c9b6.a079d83828a8a536.1410c946a779bcc0
+ 40cb4b6a89aee886.e87d166c48ce1576.d3d35c419b47ed0f.14b582787d24a48b
+ 874ed01500b10466.5287ca301f623240.bda1775cd45b4897.e4ab0310a252c10b
+ 4ef626b467bcceb8.145340fc30c9df42.b82d25f37071f37a.5ebcc9fa320ecf6c
+ 5fb54f224a658ad9
+ after
+ 40cb4b6a89aee886.e87d166c48ce1576.bda1775cd45b4897.14b582787d24a48b
+ 40cb4b6a89aee886.e87d166c48ce1576.d3d35c419b47ed0f.14b582787d24a48b
+ 874ed01500b10466.5287ca301f623240.bda1775cd45b4897.e4ab0310a252c10b
+ 4ef626b467bcceb8.145340fc30c9df42.b82d25f37071f37a.5ebcc9fa320ecf6c
+ 5fb54f224a658ad9
+VBLENDVPD_256(mem)
+ before
+ c46211750661ad7e.f10f49b15b5a8127.0bacf4bb9612d6a6.22c462740a142b65
+ 678f8bdd8111f588.cbe5357a78185a60.1460635b6d46d498.55b22a4a3fd02904
+ 25073948d77e1d23.3ac3e77a5981950f.093908c7d3739545.af427ae1aa322c02
+ da9898a025b6e37b.99f75a1d9a216edf.c7045febe1a4d5d9.8ac24da4e7c56e0c
+ 437c9f0193152ccd
+ after
+ c46211750661ad7e.f10f49b15b5a8127.0bacf4bb9612d6a6.22c462740a142b65
+ 678f8bdd8111f588.cbe5357a78185a60.1460635b6d46d498.55b22a4a3fd02904
+ c46211750661ad7e.f10f49b15b5a8127.0bacf4bb9612d6a6.22c462740a142b65
+ da9898a025b6e37b.99f75a1d9a216edf.c7045febe1a4d5d9.8ac24da4e7c56e0c
+ 437c9f0193152ccd
+
+VBLENDVPD_256(reg)
+ before
+ 37bd6c634aafa1f3.630c23d386c401bb.44cb8acfd884207d.2a8de4b3b5e64f7f
+ c0d1b137a71e0b27.9a3156cc17b5330f.978c74fcae37e894.0ea0130c6b43c064
+ 3b0468e746eea417.5cd1ad77f39437a5.ed861210b9c501d1.500869e01ecae3b3
+ 04a28fe0c4aca86f.85b8a5bf376dc7a6.a405627894bba9e0.ca93611cea847699
+ 590b77adec7f3342
+ after
+ c0d1b137a71e0b27.5cd1ad77f39437a5.ed861210b9c501d1.500869e01ecae3b3
+ c0d1b137a71e0b27.9a3156cc17b5330f.978c74fcae37e894.0ea0130c6b43c064
+ 3b0468e746eea417.5cd1ad77f39437a5.ed861210b9c501d1.500869e01ecae3b3
+ 04a28fe0c4aca86f.85b8a5bf376dc7a6.a405627894bba9e0.ca93611cea847699
+ 590b77adec7f3342
+VBLENDVPD_256(mem)
+ before
+ d93d287e3fc6d7d9.77f6218fbde355db.f1b4b893fe4da041.17545f9edba41a6c
+ 26f5ee7a00661d8b.f14e1b5ecc1fe506.7c9064dc643e7ea0.a1c105f02c0c9121
+ 1cff478f4b6ac283.ccf477bb8ded959c.02172487864f1cef.a09651d8207f49ad
+ 9727aea83ade82ee.653533119dd8a14a.5f1675808089375c.6f203ec4558a80ba
+ 69abc81f67b970f4
+ after
+ d93d287e3fc6d7d9.77f6218fbde355db.f1b4b893fe4da041.17545f9edba41a6c
+ 26f5ee7a00661d8b.f14e1b5ecc1fe506.7c9064dc643e7ea0.a1c105f02c0c9121
+ d93d287e3fc6d7d9.f14e1b5ecc1fe506.7c9064dc643e7ea0.a1c105f02c0c9121
+ 9727aea83ade82ee.653533119dd8a14a.5f1675808089375c.6f203ec4558a80ba
+ 69abc81f67b970f4
+
+VPMULDQ_128(reg)
+ before
+ ec83eb55f1965508.73389fb1eccf19f8.185d4acc976d44bc.6f59d1b46dfa8b10
+ 52f4a3d28faf6da2.8b0097967a4842cc.41b8b9581836bb9e.0eacb60d6aaed33a
+ f949ed02de8ff26d.bd4910430355ba97.3c917a21bbc2429b.18db9f7992afcd04
+ 3bd0c4517ac32116.e4e088a5a0033d84.65368b931c9a145f.68b209e3010b339a
+ dcfc6e36d4cec129
+ after
+ 0000000000000000.0000000000000000.f98b9f355d3e54aa.d272242f2286bee8
+ 52f4a3d28faf6da2.8b0097967a4842cc.41b8b9581836bb9e.0eacb60d6aaed33a
+ f949ed02de8ff26d.bd4910430355ba97.3c917a21bbc2429b.18db9f7992afcd04
+ 3bd0c4517ac32116.e4e088a5a0033d84.65368b931c9a145f.68b209e3010b339a
+ dcfc6e36d4cec129
+VPMULDQ_128(mem)
+ before
+ 4f874c60260235dd.76d3242bfdd63549.dc917aa66f5d87c0.18f1e71ad94c6f97
+ 9d1d1e4c14b549e1.049f09fc06546cb1.812762338c6f5376.b00f8a228b638def
+ a18b60e6b9f3ba62.42806f312fca00fa.ae70bd3912465ed4.8bdc7018d06baa13
+ 399d8e1b32c6438c.8dc2533414c32dd2.413606a31eed6403.04a4966644f104ad
+ 77b3f67a8280d56c
+ after
+ 4f874c60260235dd.76d3242bfdd63549.dc917aa66f5d87c0.18f1e71ad94c6f97
+ 9d1d1e4c14b549e1.049f09fc06546cb1.812762338c6f5376.b00f8a228b638def
+ 0000000000000000.0000000000000000.cdba0c59845fd280.11a1041a1c3758f9
+ 399d8e1b32c6438c.8dc2533414c32dd2.413606a31eed6403.04a4966644f104ad
+ 77b3f67a8280d56c
+
+VPMULDQ_128(reg)
+ before
+ 40548ebe26a55afa.401e25d59a3ca18a.3fb0b07352cb31e2.1547b95ccb702032
+ bad55aa0cdebce04.91dca0010e619089.b5988259846f46d9.056d525235dc4f8b
+ 4380548b13de6e35.0aa17b8ca93fccb4.4bc4c552463aa961.ef754d70793cad3a
+ 36a27aeb930a763a.853a326088e51138.5d8176ca36b89626.ae2b27a2b29cf56c
+ 1d5a5bd4fd09e54d
+ after
+ 0000000000000000.0000000000000000.de1a1cd407191939.1981e5ad6d3ef47e
+ bad55aa0cdebce04.91dca0010e619089.b5988259846f46d9.056d525235dc4f8b
+ 4380548b13de6e35.0aa17b8ca93fccb4.4bc4c552463aa961.ef754d70793cad3a
+ 36a27aeb930a763a.853a326088e51138.5d8176ca36b89626.ae2b27a2b29cf56c
+ 1d5a5bd4fd09e54d
+VPMULDQ_128(mem)
+ before
+ 1ad065f2768e3708.ee87c72ce9fc22bf.e073416bc65c1a40.481b902ded7648d6
+ 7f57c1e93738a7ca.c97b37bab240ad6f.f518259880b2a4f9.66de0fe709fffc1b
+ 29bceca35f12f3be.22c9c601896055f6.a2f559d3d1f26a8f.1416ef6426dfeea1
+ f5cb600e0728d512.54bf716e0bea5302.c1d65908d528292d.ae0e2c10dfa35915
+ 9014c358d0d67a22
+ after
+ 1ad065f2768e3708.ee87c72ce9fc22bf.e073416bc65c1a40.481b902ded7648d6
+ 7f57c1e93738a7ca.c97b37bab240ad6f.f518259880b2a4f9.66de0fe709fffc1b
+ 0000000000000000.0000000000000000.1ca9b9c530e68840.ff469f208e565692
+ f5cb600e0728d512.54bf716e0bea5302.c1d65908d528292d.ae0e2c10dfa35915
+ 9014c358d0d67a22
+
+VPMULDQ_128(reg)
+ before
+ 1672afa696058d76.bd509b144e860aef.bda7326bd369e63d.3086a123a9619d00
+ 9c75ec68cdbbceba.5f1718a34d394e83.b7ce07667e6a4853.c9d2ae1069a88234
+ 7e6976081084789d.b5eb54a6234c5cfa.a080ecc9a778b6f1.6987fbbb300a94f4
+ 18994af4fbecc8c9.9c9ac908e9ccf180.d209db02eb1f6cc3.ed6f03101a928e6c
+ 2f5645fc444c2dca
+ after
+ 0000000000000000.0000000000000000.d448a9039d611823.13d3f678f5ea2990
+ 9c75ec68cdbbceba.5f1718a34d394e83.b7ce07667e6a4853.c9d2ae1069a88234
+ 7e6976081084789d.b5eb54a6234c5cfa.a080ecc9a778b6f1.6987fbbb300a94f4
+ 18994af4fbecc8c9.9c9ac908e9ccf180.d209db02eb1f6cc3.ed6f03101a928e6c
+ 2f5645fc444c2dca
+VPMULDQ_128(mem)
+ before
+ 0c0a3a69c9442c38.c65362972b80faea.f0eef5b7bdc4c940.aab4d27ce5eca574
+ 60556045c68749e2.e3e1bc5d3bcb4aae.8eb4539ebb409f66.85cfcba3316a9fb1
+ 0805327a56203ef5.cd9153b2c85af3be.50b85faafe4c3020.bda4c4e36c259325
+ dee42cf6961cc79d.dfad24026db732c9.13c696c5a2f53897.af80b9a832aac07d
+ b8afa45e1e846065
+ after
+ 0c0a3a69c9442c38.c65362972b80faea.f0eef5b7bdc4c940.aab4d27ce5eca574
+ 60556045c68749e2.e3e1bc5d3bcb4aae.8eb4539ebb409f66.85cfcba3316a9fb1
+ 0000000000000000.0000000000000000.11c93db6e566ef80.faf76f63a9697134
+ dee42cf6961cc79d.dfad24026db732c9.13c696c5a2f53897.af80b9a832aac07d
+ b8afa45e1e846065
+
+VCMPPD_256_0x4(reg)
+ before
+ 327d8371cc3fb088.bfbfcaa4a186a205.758229b9c7714379.b3a973dcc44673fa
+ 7a36514ed968ec93.87628870946a895a.ea5c60447111617a.0c2f71dc804c9c73
+ ec260a5fe18a5032.1299e3468ad539c7.9c86c40d0825c979.fa220faff112702e
+ e498aa127e311710.3c2f5612a0d26e79.e64e52822738b722.594fc64333a4ab59
+ 05821382630f091d
+ after
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 7a36514ed968ec93.87628870946a895a.ea5c60447111617a.0c2f71dc804c9c73
+ ec260a5fe18a5032.1299e3468ad539c7.9c86c40d0825c979.fa220faff112702e
+ e498aa127e311710.3c2f5612a0d26e79.e64e52822738b722.594fc64333a4ab59
+ 05821382630f091d
+VCMPPD_256_0x4(mem)
+ before
+ da87735a9c5e45a9.bed92ed14fea7ed9.e1f25dc1f16de39c.23fe040d6bd76720
+ b42a61b6fb9d1c27.d735910aee40c03a.ddac753d99b2555b.b1e3d81c6f8d1420
+ 6f3659829bd949c3.89f8cf28f7c01bdf.0c2a1873b5ae80e3.eb49c91acfe6fbce
+ e779d8aa991d8aab.316ee49707f4c974.4a38c450616d1f5f.2c7cd372286f58d5
+ d2c8f29216b266e1
+ after
+ da87735a9c5e45a9.bed92ed14fea7ed9.e1f25dc1f16de39c.23fe040d6bd76720
+ b42a61b6fb9d1c27.d735910aee40c03a.ddac753d99b2555b.b1e3d81c6f8d1420
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ e779d8aa991d8aab.316ee49707f4c974.4a38c450616d1f5f.2c7cd372286f58d5
+ d2c8f29216b266e1
+
+VCMPPD_256_0x4(reg)
+ before
+ 377823e6343e62a0.f8bd591a10759908.2be3cdc3b96a07a4.73a2f4beb8f9f0fc
+ b8da61d81e9c88bc.7ecf57bf1ded3309.d3a28418a9ae101b.623324abd660ade5
+ b238a8d5715a14e1.547b5083db9213d8.84f80702754b2186.f5b9d102d8ae1248
+ 7fdff449c80441bc.588cc0536770f6a1.9c3251eeb6cd7691.07fe76afd9eddd4e
+ 74cf8f9ef62bc826
+ after
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ b8da61d81e9c88bc.7ecf57bf1ded3309.d3a28418a9ae101b.623324abd660ade5
+ b238a8d5715a14e1.547b5083db9213d8.84f80702754b2186.f5b9d102d8ae1248
+ 7fdff449c80441bc.588cc0536770f6a1.9c3251eeb6cd7691.07fe76afd9eddd4e
+ 74cf8f9ef62bc826
+VCMPPD_256_0x4(mem)
+ before
+ 17f898bb4b7490fa.7d1b41a1c0244cf9.65d0211cdc929891.769a5f460ac04be7
+ ce450df2f2d2f0f6.06388c47f4487143.5711f1c95604b5d4.6e7c2b770db1db35
+ 74826b300a54a547.7781d0a901fceb47.091dab45f2d20895.e026b3ee5a2b6327
+ e47a2c5fac036b19.2c44093282caf7b0.59becb7ecc094f01.28e3f2168dbb1f68
+ a1fee45a43ec4ba5
+ after
+ 17f898bb4b7490fa.7d1b41a1c0244cf9.65d0211cdc929891.769a5f460ac04be7
+ ce450df2f2d2f0f6.06388c47f4487143.5711f1c95604b5d4.6e7c2b770db1db35
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ e47a2c5fac036b19.2c44093282caf7b0.59becb7ecc094f01.28e3f2168dbb1f68
+ a1fee45a43ec4ba5
+
+VCMPPD_256_0x4(reg)
+ before
+ a9c48628184a2289.fcfbce6cf6edfe97.82cb334e1440d12b.22c1ce5fffb44344
+ 9b81d2eba761e1c1.96cfcd44041d1aee.d3634b6852eab564.3ff22ed4a7dfa389
+ d281c60f8cbec4f9.90c3a3d2f19f7a4a.7c584ceed952de06.8e1c69c9e19729fd
+ ac105d0164ed06dc.c4a3ce01da80dbd6.d9f6324c440689be.e90dfa2ac8e792cb
+ 2e8f5de479db9a20
+ after
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 9b81d2eba761e1c1.96cfcd44041d1aee.d3634b6852eab564.3ff22ed4a7dfa389
+ d281c60f8cbec4f9.90c3a3d2f19f7a4a.7c584ceed952de06.8e1c69c9e19729fd
+ ac105d0164ed06dc.c4a3ce01da80dbd6.d9f6324c440689be.e90dfa2ac8e792cb
+ 2e8f5de479db9a20
+VCMPPD_256_0x4(mem)
+ before
+ 376f0fe10f80fc27.8379942bca78e416.103bc9bfdacbf8be.4689f9ec2f92f237
+ e1798b0fa7e1760d.b50a65fa5bed9a55.4e5610f70d8c8e30.1f5c9d3b3781541e
+ 09794d585c0bc1fe.9c0dcedbb2d76443.5cc21f9590d05956.c0bc1ba5f85fed1f
+ 893bd1aa4b099c25.96cfca386cc37d8c.144973857fa2155c.85f66e970db8f7e5
+ ca54927b1219ae1d
+ after
+ 376f0fe10f80fc27.8379942bca78e416.103bc9bfdacbf8be.4689f9ec2f92f237
+ e1798b0fa7e1760d.b50a65fa5bed9a55.4e5610f70d8c8e30.1f5c9d3b3781541e
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 893bd1aa4b099c25.96cfca386cc37d8c.144973857fa2155c.85f66e970db8f7e5
+ ca54927b1219ae1d
+
+VCMPPS_128_0x4(reg)
+ before
+ eb2383bfa40d5072.3e8a93f08fe7c1af.fd9c557f243c22dd.53b886b4f50f7e6f
+ 44ae3ece5f211791.0534101645b1edc7.2fc06c1a77ce8fe2.f6dbd60c0e224fbb
+ 3143bd14dddf4026.b803c2078874dc9b.868709770006ff46.d77edf7ae7e7456b
+ 0e2cfefdbdd506dc.34c428b2753b4a54.603c2a015b6fafb6.d36d1beb9b6a1bac
+ c673084947b88fa9
+ after
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 44ae3ece5f211791.0534101645b1edc7.2fc06c1a77ce8fe2.f6dbd60c0e224fbb
+ 3143bd14dddf4026.b803c2078874dc9b.868709770006ff46.d77edf7ae7e7456b
+ 0e2cfefdbdd506dc.34c428b2753b4a54.603c2a015b6fafb6.d36d1beb9b6a1bac
+ c673084947b88fa9
+VCMPPS_128_0x4(mem)
+ before
+ 8d5d208206dd5b8f.37b7fdf5988fa660.5543bb002713f220.172dca242595dbdd
+ 02f8e281f5e33b8a.072eb4680d985c5d.f84cf8deba07912b.08a4e54cfa05bf68
+ 020ec7322fd8edc5.dcde21c2b57c6480.f7aa5c384b23e2a1.8fee78e5754a9603
+ 696b4c81d1c72b6d.11123e6f2fc8f975.2f2b62fbf574a3ad.09577e5c32f09d59
+ d02af31bce841017
+ after
+ 8d5d208206dd5b8f.37b7fdf5988fa660.5543bb002713f220.172dca242595dbdd
+ 02f8e281f5e33b8a.072eb4680d985c5d.f84cf8deba07912b.08a4e54cfa05bf68
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 696b4c81d1c72b6d.11123e6f2fc8f975.2f2b62fbf574a3ad.09577e5c32f09d59
+ d02af31bce841017
+
+VCMPPS_128_0x4(reg)
+ before
+ 41b5d38fe5912ae9.13ddee5af6bdb2ad.011809dc140658e7.7c998611d5048e7b
+ b8421a2511a3297a.dc2f28a9bbc53eb2.0a3a7e7302c5bd82.bac1446807e26038
+ 911fc548f1474776.a02c765a3beb8aa8.87c697a2958e64f4.c56f19eaa617d410
+ 2896ce631e08c08a.3ba15559923c53ba.d30652d468ef88e7.796f8085ceb1a72f
+ b28df5249cbc95c0
+ after
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ b8421a2511a3297a.dc2f28a9bbc53eb2.0a3a7e7302c5bd82.bac1446807e26038
+ 911fc548f1474776.a02c765a3beb8aa8.87c697a2958e64f4.c56f19eaa617d410
+ 2896ce631e08c08a.3ba15559923c53ba.d30652d468ef88e7.796f8085ceb1a72f
+ b28df5249cbc95c0
+VCMPPS_128_0x4(mem)
+ before
+ 4c94f4b32b425aef.d9f434e43772d162.895a3f93ddc35515.4c47aa7418736607
+ 2352f91e9851b1e9.0084f036d512b7aa.6623b2f2388c4be4.4cd59bf040a73a01
+ 12918151fef457da.f994ffc59773ab0d.aec82964bea4f354.31fc21b37c163f81
+ f71e07397a3808ed.206e5efd1622ec37.3c1520d48b160791.55073929694cb232
+ 1643debfa2d6cfc1
+ after
+ 4c94f4b32b425aef.d9f434e43772d162.895a3f93ddc35515.4c47aa7418736607
+ 2352f91e9851b1e9.0084f036d512b7aa.6623b2f2388c4be4.4cd59bf040a73a01
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ f71e07397a3808ed.206e5efd1622ec37.3c1520d48b160791.55073929694cb232
+ 1643debfa2d6cfc1
+
+VCMPPS_128_0x4(reg)
+ before
+ cefd0cdfc43fd2d9.adc507c02728804f.d160084bf0aab4d5.eed5142ebcee43c6
+ db7fbff66b13f628.1051fdd421d07a2c.68b4f919c1974093.9fd67f5e6d396520
+ 9716f37131df7857.fc90665f853db3af.41b72dd42475cc1c.2be2df50b80227ca
+ 5f0da5bab52e9414.4c4cbc4f6f7ae705.b8b5a1e9b6d1931d.6dc6b0f0bc5546f1
+ 434e6c2a923f7dc0
+ after
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ db7fbff66b13f628.1051fdd421d07a2c.68b4f919c1974093.9fd67f5e6d396520
+ 9716f37131df7857.fc90665f853db3af.41b72dd42475cc1c.2be2df50b80227ca
+ 5f0da5bab52e9414.4c4cbc4f6f7ae705.b8b5a1e9b6d1931d.6dc6b0f0bc5546f1
+ 434e6c2a923f7dc0
+VCMPPS_128_0x4(mem)
+ before
+ 884590ea59cb8964.8fb2d03f908c850b.de537d8efa94d159.29f950c21236d242
+ 1779991c2a052609.844f706b618689e8.8c6f250a42952ed8.efd136cdd431c536
+ ceb402ad24fa10da.983281a9c1a7d956.346d2eae648bbaad.68874f75994da8a6
+ 88c3488860b50304.28a500674e7bb401.b11916667c823006.ef689726fd16b63d
+ dfc10b4c9a182ca8
+ after
+ 884590ea59cb8964.8fb2d03f908c850b.de537d8efa94d159.29f950c21236d242
+ 1779991c2a052609.844f706b618689e8.8c6f250a42952ed8.efd136cdd431c536
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffffffff
+ 88c3488860b50304.28a500674e7bb401.b11916667c823006.ef689726fd16b63d
+ dfc10b4c9a182ca8
+
+VCMPPS_256_0x4(reg)
+ before
+ 96dba6530fe04593.2073e598fc42bab3.90f5e810a48f5497.de3e571ea5854e0c
+ 6f0564a7f6f93fa9.748d57cb14aef212.2c6e35105e6ef6c1.99aa70c3fba0ceee
+ c58a41b4ebf05496.5ee0190cc304664e.585be3d419a4d62e.bc27da3f9bdf6cd5
+ f6b53ae68b50c108.bb37a7472651d392.710aeec670be3088.2582127fa04fe6f0
+ ae87957027fbf669
+ after
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 6f0564a7f6f93fa9.748d57cb14aef212.2c6e35105e6ef6c1.99aa70c3fba0ceee
+ c58a41b4ebf05496.5ee0190cc304664e.585be3d419a4d62e.bc27da3f9bdf6cd5
+ f6b53ae68b50c108.bb37a7472651d392.710aeec670be3088.2582127fa04fe6f0
+ ae87957027fbf669
+VCMPPS_256_0x4(mem)
+ before
+ 3402defc4bef596d.5cd34aaa71a5c1a9.685d7d68589ff50b.d1c55353ff473f7b
+ 94bf69112938cb27.55316d6a3a7c9225.3f1f175b75fd88e4.d5d90de863cc40b5
+ a889b29adce107c4.3b199f9481606e29.1e4af20c9a74484a.d89218ef38d76fdf
+ 4d2e368381f7ca6f.6cd7dc93e2dd9161.dfa88967e212f069.383c70d619f607a8
+ 50231208a2b545ba
+ after
+ 3402defc4bef596d.5cd34aaa71a5c1a9.685d7d68589ff50b.d1c55353ff473f7b
+ 94bf69112938cb27.55316d6a3a7c9225.3f1f175b75fd88e4.d5d90de863cc40b5
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 4d2e368381f7ca6f.6cd7dc93e2dd9161.dfa88967e212f069.383c70d619f607a8
+ 50231208a2b545ba
+
+VCMPPS_256_0x4(reg)
+ before
+ 7c93f9f1709f65c1.607870b83385d055.42b921d3fb803978.5f0558596ae23d6c
+ 18d721fd1e40a26a.bb34dc250e97d4a2.1a0969bf65d4a01b.7a2fdccc4df1ea80
+ 803c869849243a61.3b2ef6b62f3a9381.5115b0c5be6503f5.0df18faea849b5d0
+ 100e242e8cd86652.bc323b57b278c91f.4127f251a2c09eb3.f216efea97f95889
+ 066b776b340a8fd7
+ after
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 18d721fd1e40a26a.bb34dc250e97d4a2.1a0969bf65d4a01b.7a2fdccc4df1ea80
+ 803c869849243a61.3b2ef6b62f3a9381.5115b0c5be6503f5.0df18faea849b5d0
+ 100e242e8cd86652.bc323b57b278c91f.4127f251a2c09eb3.f216efea97f95889
+ 066b776b340a8fd7
+VCMPPS_256_0x4(mem)
+ before
+ 25bca41f9e8a18e5.2399f82b84e765e7.1a0b25f4b26032a7.478c2bcdac70ac01
+ 2bd5f0f1ee84ade0.1729fdfbccde72cf.3187327a4bfb8946.bf9058a678016a8a
+ f482d9cd42050bf3.470a2f0b0148c8b4.dd70ddd39a578b28.067f7448a30014fb
+ 5c8eda9fb618ee4b.0e878ac5beb1a443.fa93a3edba7ff478.76a47b20c8f8e500
+ 6c4d6a9884751a44
+ after
+ 25bca41f9e8a18e5.2399f82b84e765e7.1a0b25f4b26032a7.478c2bcdac70ac01
+ 2bd5f0f1ee84ade0.1729fdfbccde72cf.3187327a4bfb8946.bf9058a678016a8a
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 5c8eda9fb618ee4b.0e878ac5beb1a443.fa93a3edba7ff478.76a47b20c8f8e500
+ 6c4d6a9884751a44
+
+VCMPPS_256_0x4(reg)
+ before
+ 44c43b1e7304ef73.3fc76f5465c91114.caee0a979fa64127.64bcfeb3c8807f63
+ 5a56ec1d2f30a03a.79f714d66c253179.d689aceb41b1dc0d.f7b76c10e065ea14
+ 0a4f780157856845.e6eb4612e6370aa7.8da56b2f4061b1a1.8f5068f21c3aefb8
+ b0fbdb3684908440.626f80f5ef0b57c9.4d8e43ce373ffc8e.08526e449b0c4a7b
+ 3e8bfbf276e6b988
+ after
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ 5a56ec1d2f30a03a.79f714d66c253179.d689aceb41b1dc0d.f7b76c10e065ea14
+ 0a4f780157856845.e6eb4612e6370aa7.8da56b2f4061b1a1.8f5068f21c3aefb8
+ b0fbdb3684908440.626f80f5ef0b57c9.4d8e43ce373ffc8e.08526e449b0c4a7b
+ 3e8bfbf276e6b988
+VCMPPS_256_0x4(mem)
+ before
+ 0dc589e9ccd4f60c.a8a5122855dc30d6.c94f3e6aa4aed60c.708f3034c2d9f880
+ 51cd9613b6e3be32.4e9b184363f6a8b3.f756fc5c202b419c.54f62fcd7ebbe325
+ e66f9d5d521ecc27.fe27e8f34c682784.c75237b9808e54a4.530d3b05076ff626
+ a7761bb4bc91dd17.149681a4acc1eaf5.170d696ce0e4cd51.ca215049f8837032
+ 167f6a03ed828bf3
+ after
+ 0dc589e9ccd4f60c.a8a5122855dc30d6.c94f3e6aa4aed60c.708f3034c2d9f880
+ 51cd9613b6e3be32.4e9b184363f6a8b3.f756fc5c202b419c.54f62fcd7ebbe325
+ ffffffffffffffff.ffffffffffffffff.ffffffffffffffff.ffffffffffffffff
+ a7761bb4bc91dd17.149681a4acc1eaf5.170d696ce0e4cd51.ca215049f8837032
+ 167f6a03ed828bf3
+
+VPCMPGTB_128(reg)
+ before
+ 917086a083f98416.72b08a020f49ad2d.ec34dcc31e8a2cb1.c25410615b3866ce
+ 98439e8d55739746.22e768356851f895.e24df7ba3f512b65.a4f3a7840d96dc48
+ 8843b035007c0030.92e93038e2b5797d.512dccf7aaa121bd.98b6abc1130beaeb
+ bbbbb7031fa1fa7f.a0805ef69982ee0f.971f59e4fb074b64.7c69960588a24de2
+ 2ad7e63a8967c159
+ after
+ 0000000000000000.0000000000000000.00ffff00ffffffff.ffff0000000000ff
+ 98439e8d55739746.22e768356851f895.e24df7ba3f512b65.a4f3a7840d96dc48
+ 8843b035007c0030.92e93038e2b5797d.512dccf7aaa121bd.98b6abc1130beaeb
+ bbbbb7031fa1fa7f.a0805ef69982ee0f.971f59e4fb074b64.7c69960588a24de2
+ 2ad7e63a8967c159
+VPCMPGTB_128(mem)
+ before
+ 80ce164e3167027e.8ef9b0654f6dc2e0.27796e5daac31077.0f719aefcf0de407
+ 5918a22b9cadcc7b.5d4795c62b6d93ff.02a0dd5830849ee2.156d8983c2422a51
+ 908207bfe845da7c.85f26492502bab87.0fc026d348d2527c.0460240c6e2f57ef
+ 03d8bff52e3ce9ae.6045183559354425.28a7c5bb0eb8e970.3a9665f67262a78d
+ 115a4bad686658d6
+ after
+ 80ce164e3167027e.8ef9b0654f6dc2e0.27796e5daac31077.0f719aefcf0de407
+ 5918a22b9cadcc7b.5d4795c62b6d93ff.02a0dd5830849ee2.156d8983c2422a51
+ 0000000000000000.0000000000000000.00000000ff000000.ff00000000ffffff
+ 03d8bff52e3ce9ae.6045183559354425.28a7c5bb0eb8e970.3a9665f67262a78d
+ 115a4bad686658d6
+
+VPCMPGTB_128(reg)
+ before
+ e7facf9decc8a476.8ce648b88c9db43d.4b8ead1be2179a84.2b1f36fa9c431feb
+ 17c0ee339b13c81b.08771df61e75f854.a21820b1885beb51.f2f5f67d117eaf19
+ fcfaa5d910d3ff6f.5459bb9affcf7120.c12e6b61e7907138.5bf57f3187755725
+ f4f2effde895861e.4a569c904bb7dbcc.041d8c999a3f69e4.40eb4f001a34d03b
+ 7ea3e1d8e6c8d989
+ after
+ 0000000000000000.0000000000000000.0000000000ff00ff.000000ffffff0000
+ 17c0ee339b13c81b.08771df61e75f854.a21820b1885beb51.f2f5f67d117eaf19
+ fcfaa5d910d3ff6f.5459bb9affcf7120.c12e6b61e7907138.5bf57f3187755725
+ f4f2effde895861e.4a569c904bb7dbcc.041d8c999a3f69e4.40eb4f001a34d03b
+ 7ea3e1d8e6c8d989
+VPCMPGTB_128(mem)
+ before
+ f2e8b2a4093c2c38.59f5c809bee499d5.c83b3ec51f39f285.c7317ec33df60f02
+ 76883c509c9d8677.884f2d6b2e4c7440.a8d41c2396627177.66b63d4d6d409e3d
+ e74dfdc8bdf5a370.de4b188ed55a530a.c7edb297cd3d15cd.3df8c6a2c5a95342
+ 210470f888533f50.b53787de4f9971e0.01527d0ee0d799b4.a742142de2be6abd
+ 02e2235c600a1f59
+ after
+ f2e8b2a4093c2c38.59f5c809bee499d5.c83b3ec51f39f285.c7317ec33df60f02
+ 76883c509c9d8677.884f2d6b2e4c7440.a8d41c2396627177.66b63d4d6d409e3d
+ 0000000000000000.0000000000000000.000000ff00ffffff.ff0000ffffff00ff
+ 210470f888533f50.b53787de4f9971e0.01527d0ee0d799b4.a742142de2be6abd
+ 02e2235c600a1f59
+
+VPCMPGTB_128(reg)
+ before
+ a922ef9ad91aadc3.017911cc18c01542.6a5d75c737950b6d.33cef772e93bbb58
+ f84f7454ec7951a6.61785d30894ae273.5a0adfb52adb5c5e.372e9eb1077535e4
+ 4bb5aff432b346af.1ecccf10f8fc610e.df8abf14c3f6a25f.ea3fedb65391c384
+ fda09be74954ca89.1443e35981e35040.562913509e72171b.28cb616dec9c2365
+ cd9f74c2eba20fb3
+ after
+ 0000000000000000.0000000000000000.ffffff00ff00ff00.ff00000000ffffff
+ f84f7454ec7951a6.61785d30894ae273.5a0adfb52adb5c5e.372e9eb1077535e4
+ 4bb5aff432b346af.1ecccf10f8fc610e.df8abf14c3f6a25f.ea3fedb65391c384
+ fda09be74954ca89.1443e35981e35040.562913509e72171b.28cb616dec9c2365
+ cd9f74c2eba20fb3
+VPCMPGTB_128(mem)
+ before
+ b586a4a16fad449a.6c5c349acde917e2.1fa715f53f0a6935.1b33d6d658dcf73f
+ bc4e6cf691cb7e45.f334767759fd6a63.1bc5e1d24e7d6818.8bf304108cbf8076
+ bec148ad6f0778e0.ed755dec8a1dfebb.e469c4dbcb490b16.00b7996cd7a7ec6e
+ 97acb4b3256eef98.b86be663fbd41194.565f38fbd1790c5a.d7c99254d52178d0
+ 6c76ea3620b8604a
+ after
+ b586a4a16fad449a.6c5c349acde917e2.1fa715f53f0a6935.1b33d6d658dcf73f
+ bc4e6cf691cb7e45.f334767759fd6a63.1bc5e1d24e7d6818.8bf304108cbf8076
+ 0000000000000000.0000000000000000.00ff0000ffff0000.0000ffff000000ff
+ 97acb4b3256eef98.b86be663fbd41194.565f38fbd1790c5a.d7c99254d52178d0
+ 6c76ea3620b8604a
+
+VPCMPGTW_128(reg)
+ before
+ 1b0a9d7d57f8df88.23dc2df2ce0b9f99.ae630c4a48aedd9a.4d73bb207d192811
+ 40d1a795136e3236.3e1a2e5886ea430f.2da6cb0c0e389e7a.a570c935ea351b67
+ 371604eaf3a595fe.c43533cf6a189925.8f832015e9fd92e0.3a24dc2635daa087
+ 5c27b1e8902a438f.91f8b84596a05b07.324505d17489f377.e85972e07914749d
+ 8adc064dd3ed53d7
+ after
+ 0000000000000000.0000000000000000.ffff0000ffffffff.000000000000ffff
+ 40d1a795136e3236.3e1a2e5886ea430f.2da6cb0c0e389e7a.a570c935ea351b67
+ 371604eaf3a595fe.c43533cf6a189925.8f832015e9fd92e0.3a24dc2635daa087
+ 5c27b1e8902a438f.91f8b84596a05b07.324505d17489f377.e85972e07914749d
+ 8adc064dd3ed53d7
+VPCMPGTW_128(mem)
+ before
+ fe79145a5e73f95f.0b4ea9fb88877a93.802e3aa5258e45e2.703778ac4b69feec
+ 1ffc18f437b22161.a0d8e890774b74b7.6fa533db33ef15e2.a7a674120b28eeea
+ c9308e0579b4880a.77116b11f8ff6da6.392721d3ddce8532.31def5704f52011e
+ d7e3f37b4088ea86.eb452ceba831a30d.ba817f793e3752ff.6b2bf830b4737134
+ b2d977c0d6187ad7
+ after
+ fe79145a5e73f95f.0b4ea9fb88877a93.802e3aa5258e45e2.703778ac4b69feec
+ 1ffc18f437b22161.a0d8e890774b74b7.6fa533db33ef15e2.a7a674120b28eeea
+ 0000000000000000.0000000000000000.ffff0000ffff0000.0000000000000000
+ d7e3f37b4088ea86.eb452ceba831a30d.ba817f793e3752ff.6b2bf830b4737134
+ b2d977c0d6187ad7
+
+VPCMPGTW_128(reg)
+ before
+ 6034708a4fcd5ab4.27dfc241a9370200.5ac0298b226c5098.cd7fcab973373775
+ d287defcbd1d4b77.94f17742d0cf8da5.1fcd5d5c023cb0f2.50ec7c7f97d9f1bf
+ 651fbe81bc948acb.f9e58f6cd05b47a1.96bac4c9e52e01c8.1e9613b8c7293c0a
+ 73480a85e7be535c.348784aac5e7eb1f.1ad15b4066ce7dc5.12470a4e1e34d481
+ 0accdd2fb9057551
+ after
+ 0000000000000000.0000000000000000.ffffffffffff0000.ffffffff00000000
+ d287defcbd1d4b77.94f17742d0cf8da5.1fcd5d5c023cb0f2.50ec7c7f97d9f1bf
+ 651fbe81bc948acb.f9e58f6cd05b47a1.96bac4c9e52e01c8.1e9613b8c7293c0a
+ 73480a85e7be535c.348784aac5e7eb1f.1ad15b4066ce7dc5.12470a4e1e34d481
+ 0accdd2fb9057551
+VPCMPGTW_128(mem)
+ before
+ e0f20945b3a9daa5.594ec074db28e1d8.1fa2d4e8cc80374c.095f1c2c22a66196
+ 7282087e282ac0aa.737ddbba335d71e8.9804fa130031e553.beb005f9b544e9e6
+ 9a4b58c53596e28c.1d2157c38ce93f3b.797773157e06b161.94101114ba335063
+ 36187406f6f9fd76.b38531fc8159867b.a0c8b9db610c59a1.e9ca3de7cd00d3b6
+ 172c83df8b36ae8e
+ after
+ e0f20945b3a9daa5.594ec074db28e1d8.1fa2d4e8cc80374c.095f1c2c22a66196
+ 7282087e282ac0aa.737ddbba335d71e8.9804fa130031e553.beb005f9b544e9e6
+ 0000000000000000.0000000000000000.0000ffffffff0000.0000000000000000
+ 36187406f6f9fd76.b38531fc8159867b.a0c8b9db610c59a1.e9ca3de7cd00d3b6
+ 172c83df8b36ae8e
+
+VPCMPGTW_128(reg)
+ before
+ 7c80e1698f611d94.20b4d92d865ecd95.91f763cfae388354.e7c34a52c64e9740
+ 721352ef760e5b77.35ed012601d10e15.13c1eba9b0127274.2b34a164c8d9286a
+ 5731d2dfdbc8a5e1.528d6add845e7c21.9530c4f723748f84.49e73aff84b8c84a
+ 85265da35a1b377f.51618f3f2b12d2e5.7390eb24a1e91533.1ba7910e15f7320d
+ 7e42237d98a223df
+ after
+ 0000000000000000.0000000000000000.ffffffff0000ffff.00000000ffffffff
+ 721352ef760e5b77.35ed012601d10e15.13c1eba9b0127274.2b34a164c8d9286a
+ 5731d2dfdbc8a5e1.528d6add845e7c21.9530c4f723748f84.49e73aff84b8c84a
+ 85265da35a1b377f.51618f3f2b12d2e5.7390eb24a1e91533.1ba7910e15f7320d
+ 7e42237d98a223df
+VPCMPGTW_128(mem)
+ before
+ 4f826b3828c657eb.5a3ef0a990934cfc.0f34ec3611f8cd8f.092d5a9bc9fe412b
+ 6834e52be26e895d.30c4865c19bd2205.68d4feaf521d2848.b3520fca353e4f18
+ a6240d42e1a77662.64051b289025f245.390c3f970b8ca13f.cd4d051c81357ba7
+ e51e5f69417cda26.534eab799255fb69.5ca72dd95751f29e.b26838fd4a6f0084
+ c0f0a4d92b791b5a
+ after
+ 4f826b3828c657eb.5a3ef0a990934cfc.0f34ec3611f8cd8f.092d5a9bc9fe412b
+ 6834e52be26e895d.30c4865c19bd2205.68d4feaf521d2848.b3520fca353e4f18
+ 0000000000000000.0000000000000000.ffffffffffffffff.00000000ffffffff
+ e51e5f69417cda26.534eab799255fb69.5ca72dd95751f29e.b26838fd4a6f0084
+ c0f0a4d92b791b5a
+
+VPMADDWD_128(reg)
+ before
+ 5231461dc1de08d6.01ed588c1ff971d5.57e933bbbadb771d.ae7243615379d791
+ c4771933a72b02a4.d65f7398972bf69a.cd22ad5ba443a30c.0b39fd1a1a0e0e46
+ 710d19887aeb466f.413e2c77c31c26a1.114717c3ed17bbe3.4fc8d8f2c91f51e6
+ b7414289d5aa10e4.1c57ff17c2dbbd18.7fa36d6030e6fb4d.56eb4fd47bb55da0
+ fc6ddead4cdeee9e
+ after
+ 0000000000000000.0000000000000000.f4e55fbf1f8220a9.03f08e1cfefb1e96
+ c4771933a72b02a4.d65f7398972bf69a.cd22ad5ba443a30c.0b39fd1a1a0e0e46
+ 710d19887aeb466f.413e2c77c31c26a1.114717c3ed17bbe3.4fc8d8f2c91f51e6
+ b7414289d5aa10e4.1c57ff17c2dbbd18.7fa36d6030e6fb4d.56eb4fd47bb55da0
+ fc6ddead4cdeee9e
+VPMADDWD_128(mem)
+ before
+ 1d1c016759a5bf0c.f15d91a054f49cae.44766963ae717628.7481a99f0a399ef7
+ 95c234efbe178d18.7aae003b9456257a.9567e547a3ec0f00.4a2ec9eb169ee18d
+ 402cf432963f14eb.b0808dc5315ce8f3.eaf6efaebe5742ca.5ef6c7aff1a0ffba
+ fa26bc1afd290fb4.ed1f33aac69021c7.21ee03861abfcbb2.0c25a15937cb362b
+ b007535482acc08b
+ after
+ 1d1c016759a5bf0c.f15d91a054f49cae.44766963ae717628.7481a99f0a399ef7
+ 95c234efbe178d18.7aae003b9456257a.9567e547a3ec0f00.4a2ec9eb169ee18d
+ 0000000000000000.0000000000000000.d87e02ef24421b2c.3401c5230c71da39
+ fa26bc1afd290fb4.ed1f33aac69021c7.21ee03861abfcbb2.0c25a15937cb362b
+ b007535482acc08b
+
+VPMADDWD_128(reg)
+ before
+ a6e8d70c70ceda87.9f7c089510e23c9d.8fd7ef56ef800b9f.151d9dbbd42f68e5
+ 4a132bed9dbdbfcb.0bf9548eeb7555d2.f0f3bb3549b7e32a.a24d3a3707b3d38f
+ f8d64a64a406ac02.196b1cf0a9ee1680.6ec195b370c2e511.a44b55e7d058c9dc
+ 0c7b30db2234ddd9.a79cdda9665a3dd3.638b783cff2c4d03.f7e36ab74a2905f6
+ 76e1f5949132440c
+ after
+ 0000000000000000.0000000000000000.160dd04223809478.3519ab3007f72b6c
+ 4a132bed9dbdbfcb.0bf9548eeb7555d2.f0f3bb3549b7e32a.a24d3a3707b3d38f
+ f8d64a64a406ac02.196b1cf0a9ee1680.6ec195b370c2e511.a44b55e7d058c9dc
+ 0c7b30db2234ddd9.a79cdda9665a3dd3.638b783cff2c4d03.f7e36ab74a2905f6
+ 76e1f5949132440c
+VPMADDWD_128(mem)
+ before
+ ff107368c2804248.e14fd9bfb2d48efb.905912a43fc484f6.2c9e603d928156aa
+ 6d3e5f21f91ebbd7.d59d427df171fa15.b06e37cd4f38a816.26464a20c64e3db3
+ 9c3535aa51196ae4.43b3667f7a975ed3.e2a7c811b3c3645f.abcf3053361e3ec9
+ 67c271efe67b0d9c.87dc4133e9d2f6e0.04d0425a867075fc.188410407f7d9499
+ cab3e5553cf87cce
+ after
+ ff107368c2804248.e14fd9bfb2d48efb.905912a43fc484f6.2c9e603d928156aa
+ 6d3e5f21f91ebbd7.d59d427df171fa15.b06e37cd4f38a816.26464a20c64e3db3
+ 0000000000000000.0000000000000000.26c45f923dfc4c04.228950d42d90842c
+ 67c271efe67b0d9c.87dc4133e9d2f6e0.04d0425a867075fc.188410407f7d9499
+ cab3e5553cf87cce
+
+VPMADDWD_128(reg)
+ before
+ 1ba6acfd0a1a3215.acb18fdbd5525d2b.fc63cf04dbaffee9.f1b42095e54b971a
+ 68aa5fa4846ff21a.45ce0c5c3aaa19bc.00950c5eebb9b199.8421deafeb6186e4
+ 0d0bfcb64684f788.10e4635e308dfb7b.eebef5adb67d4c9d.9be1f892b5bdfd87
+ 66157e9fede47e0c.e7c110cbd30ac096.212a855dd8860ba0.10c1eb2c5e6cba2e
+ c18d316802797607
+ after
+ 0000000000000000.0000000000000000.ff76461cee5bf62a.3169a3cf0726d1d9
+ 68aa5fa4846ff21a.45ce0c5c3aaa19bc.00950c5eebb9b199.8421deafeb6186e4
+ 0d0bfcb64684f788.10e4635e308dfb7b.eebef5adb67d4c9d.9be1f892b5bdfd87
+ 66157e9fede47e0c.e7c110cbd30ac096.212a855dd8860ba0.10c1eb2c5e6cba2e
+ c18d316802797607
+VPMADDWD_128(mem)
+ before
+ 88114832bff0f03b.cf14e1cb151bc351.a82f8f90402a2437.f725b8daeb602950
+ 4318ab75aedde2f8.a45322a659b60104.2dfb5c9992fbe28a.cbfb8a908e98e356
+ cc70d71fed4d096a.41203b9d564076d1.54f1f4d3e688b8bc.f8f7f8eb5bb97561
+ 00e3461c984b21bd.02c52a1aa7465c63.f7ddd22957dd5ff9.dc66fc58ee4f1b1a
+ d1949441e3e61030
+ after
+ 88114832bff0f03b.cf14e1cb151bc351.a82f8f90402a2437.f725b8daeb602950
+ 4318ab75aedde2f8.a45322a659b60104.2dfb5c9992fbe28a.cbfb8a908e98e356
+ 0000000000000000.0000000000000000.c78eb625e081f0d4.227026e70482d1e0
+ 00e3461c984b21bd.02c52a1aa7465c63.f7ddd22957dd5ff9.dc66fc58ee4f1b1a
+ d1949441e3e61030
+
+VADDSUBPS_128(reg)
+ before
+ 35cdbc14d80b914d.bc3e7656c9e4e61c.438fea8be853ef67.f38b72860207966c
+ 625d6e3c664ada1e.da4de2ba9f2213b4.60ca785ab6f36d88.25c651d802111742
+ b590a8252b2d264e.37dc0635341465b0.b5c1cef5acb21073.675ce90a74089fa6
+ 8bb1643ac342b28a.afb75eb1a4c3973d.9ec2eac7671d14d4.9617b80873f7eac5
+ 8ec439be1beab4cb
+ after
+ 0000000000000000.0000000000000000.60ca785ab6f36d7d.675ce90af4089fa6
+ 625d6e3c664ada1e.da4de2ba9f2213b4.60ca785ab6f36d88.25c651d802111742
+ b590a8252b2d264e.37dc0635341465b0.b5c1cef5acb21073.675ce90a74089fa6
+ 8bb1643ac342b28a.afb75eb1a4c3973d.9ec2eac7671d14d4.9617b80873f7eac5
+ 8ec439be1beab4cb
+VADDSUBPS_128(mem)
+ before
+ 2c2fe81889edb8e3.3e0ea1e9c915ba7d.1fa9671c0c3d6786.7717c73c82bfb756
+ 4a244202d90db33a.2bf1589ed9307ad4.617f9c60878d8fb8.9c0e61c09a2533a6
+ c56ec169265660fb.afa786c390212d3b.5206796b32c0cbff.69f1b4bf4ad9c56f
+ 79dbe3378cd27d53.247c28c58a74105d.ce087a2828e1d986.390dbda52f6aa95e
+ 6aad77dfe4611a1e
+ after
+ 2c2fe81889edb8e3.3e0ea1e9c915ba7d.1fa9671c0c3d6786.7717c73c82bfb756
+ 4a244202d90db33a.2bf1589ed9307ad4.617f9c60878d8fb8.9c0e61c09a2533a6
+ 0000000000000000.0000000000000000.617f9c608c3dae4e.7717c73c9a2533a6
+ 79dbe3378cd27d53.247c28c58a74105d.ce087a2828e1d986.390dbda52f6aa95e
+ 6aad77dfe4611a1e
+
+VADDSUBPS_128(reg)
+ before
+ 571fded7064c555d.4235235a288fc46e.e7bb391062b35fe7.b1521c8386fc737a
+ 5baeeefb30b696c4.fc49febc1598f177.54b2b511b46c5584.d7afda68671d5606
+ d4a5a4b5ff2c1902.83e3ee4b70fac29b.c7ab99321d2b30e1.1ced2fc3e7513e57
+ 1d51fa730e3919c0.b3cf71f255c0f105.9cf4dfe1387b29aa.5cd69a8024a4e699
+ 7337948c37200bf7
+ after
+ 0000000000000000.0000000000000000.54b2b511b46c5584.d7afda6867b74a2e
+ 5baeeefb30b696c4.fc49febc1598f177.54b2b511b46c5584.d7afda68671d5606
+ d4a5a4b5ff2c1902.83e3ee4b70fac29b.c7ab99321d2b30e1.1ced2fc3e7513e57
+ 1d51fa730e3919c0.b3cf71f255c0f105.9cf4dfe1387b29aa.5cd69a8024a4e699
+ 7337948c37200bf7
+VADDSUBPS_128(mem)
+ before
+ 3ddd9bd13ed3699e.91feeea0f969d3ad.68d9029ddef63be2.30d78589a2e87f8a
+ 9692293d55c8bbb9.8ef87ba85d498373.7ecc1d382aa95c5e.dda18696f6fe6c2e
+ 5a22bdba970cbf75.6e8b9ef7d66364bf.d1763faf52e40fa4.009dde74d14a2e41
+ 655bd03620aa2ffd.8f0251f9ff46b33c.3da1e2ee75b311e1.f5198a8fce57fe70
+ 185f84538ab11b67
+ after
+ 3ddd9bd13ed3699e.91feeea0f969d3ad.68d9029ddef63be2.30d78589a2e87f8a
+ 9692293d55c8bbb9.8ef87ba85d498373.7ecc1d382aa95c5e.dda18696f6fe6c2e
+ 0000000000000000.0000000000000000.7ecc1d385ef63be2.dda18696f6fe6c2e
+ 655bd03620aa2ffd.8f0251f9ff46b33c.3da1e2ee75b311e1.f5198a8fce57fe70
+ 185f84538ab11b67
+
+VADDSUBPS_128(reg)
+ before
+ c4bdca2ca0e5bfd1.9207df9c0daec77f.4bab921a747bac97.9d1a84e1ac231e40
+ 577d5786ad7e275b.bff467d879254524.ffd05cc6d2908b7b.cfada074153ff2ee
+ 2cec28ce4c098fb0.c7ece3d6811a631b.08beab6ab4118b95.ae26b394cc134817
+ 9f56376e1911327d.86bccf824099de8e.c0c17c70b788e991.1650372becacdde6
+ e2f9aa2792156d88
+ after
+ 0000000000000000.0000000000000000.ffd05cc6d2908b7b.cfada0744c134817
+ 577d5786ad7e275b.bff467d879254524.ffd05cc6d2908b7b.cfada074153ff2ee
+ 2cec28ce4c098fb0.c7ece3d6811a631b.08beab6ab4118b95.ae26b394cc134817
+ 9f56376e1911327d.86bccf824099de8e.c0c17c70b788e991.1650372becacdde6
+ e2f9aa2792156d88
+VADDSUBPS_128(mem)
+ before
+ f0eb8773d95ab328.0c0682d4b1224d6e.d730a7c8d3af71a9.8424ca467683e11a
+ 1bf34afbdd886cf3.cf4a046ab0c81c2e.9813e8945567d999.b13590568e8eaedd
+ 3edd6fabbbaa5414.436cb99eb190db6a.a4330dd3e3ced28a.a13fcd0e9a338e86
+ 3775736f8ecc26b8.c6ba9edb5005c5cd.d65a926f98ee18a7.b18d7ad93700bac0
+ 3d6c942300817137
+ after
+ f0eb8773d95ab328.0c0682d4b1224d6e.d730a7c8d3af71a9.8424ca467683e11a
+ 1bf34afbdd886cf3.cf4a046ab0c81c2e.9813e8945567d999.b13590568e8eaedd
+ 0000000000000000.0000000000000000.d730a7c8557dc7ce.b1359056f683e11a
+ 3775736f8ecc26b8.c6ba9edb5005c5cd.d65a926f98ee18a7.b18d7ad93700bac0
+ 3d6c942300817137
+
+VADDSUBPS_256(reg)
+ before
+ a12818589240ed98.e086d13373fba00b.b37ead8d2ab41704.0c56f35691d5661d
+ 3a0d01e488cb6b8f.17de05e386427c38.6504e420db280cba.20f1ac73e98f7a18
+ 62664b337eae27c8.b6478b6be2ae766c.3a9a3e00fdede29d.f0f83ab1bd270dc3
+ 7681f3b111745dee.9b8ee0b8a3494cd3.8c8bb8992f90d356.563618fe28a9de4a
+ 3079c2454621a7db
+ after
+ 62664b33feae27c8.b6478b6b62ae766c.6504e4207dede29d.f0f83ab1e98f7a18
+ 3a0d01e488cb6b8f.17de05e386427c38.6504e420db280cba.20f1ac73e98f7a18
+ 62664b337eae27c8.b6478b6be2ae766c.3a9a3e00fdede29d.f0f83ab1bd270dc3
+ 7681f3b111745dee.9b8ee0b8a3494cd3.8c8bb8992f90d356.563618fe28a9de4a
+ 3079c2454621a7db
+VADDSUBPS_256(mem)
+ before
+ 588bb472349c25a0.d2a8f4cbdda948ad.a07f7eb4e622b898.b9224c580a9b1c94
+ ab3a6b710e2514c5.d22849eb7dd925b2.a3e6e34dc64277e7.1cadf8a72d9df800
+ 0650622eefc93077.d24ef07f8d912fa9.7e8f8b6d5fb745ee.1076b7f4311fa549
+ 439a1596f39334e2.2e63e5f1aa5ca43e.0e45f002cf8cddd7.f2ca85a9b5af5d19
+ 1ff45f3452d95c1d
+ after
+ 588bb472349c25a0.d2a8f4cbdda948ad.a07f7eb4e622b898.b9224c580a9b1c94
+ ab3a6b710e2514c5.d22849eb7dd925b2.a3e6e34dc64277e7.1cadf8a72d9df800
+ 588bb472b49c25a0.d2fd19c07dd925b2.a3e8e24a6622b898.b9224c582d9df800
+ 439a1596f39334e2.2e63e5f1aa5ca43e.0e45f002cf8cddd7.f2ca85a9b5af5d19
+ 1ff45f3452d95c1d
+
+VADDSUBPS_256(reg)
+ before
+ f1423f00a627e000.3fe30093378fdd31.42b622af70c7be1c.30d690f72fcefcce
+ c6ff23794d27236f.d7f99f13d6c9e691.6992a5247a5cbaef.be0ce5389d875e00
+ f876060be2656215.e5a76f00ed4e0d2d.014269bc64a9d364.95b46db135c6be99
+ e4f4e422016bd99f.46b8eb4897290c32.65136ae3cb3a4727.919aa44e1294d9c4
+ 8e8a04fb50ff6bae
+ after
+ f876060b62656215.e5a76f006d4e0d2d.6992a5247a5cbaef.be0ce538b5c6be99
+ c6ff23794d27236f.d7f99f13d6c9e691.6992a5247a5cbaef.be0ce5389d875e00
+ f876060be2656215.e5a76f00ed4e0d2d.014269bc64a9d364.95b46db135c6be99
+ e4f4e422016bd99f.46b8eb4897290c32.65136ae3cb3a4727.919aa44e1294d9c4
+ 8e8a04fb50ff6bae
+VADDSUBPS_256(mem)
+ before
+ 684f0ba50c123082.e6c5ba2a47c7c3b9.d6f98fd6f1679fcc.f151a5054a9a4fe3
+ fcb7343662dae36d.5b35838f50055d0e.7136d79616138426.0148148e7e552a45
+ 248cfb9c6d62419b.9d903bbeb7afe34b.f33b40742339756d.f044b5eb02f813f9
+ bd9bdcc149b60637.0921de211853901b.38d4445c33e62fcc.1c918386720d45aa
+ e07a7acd6c23fc05
+ after
+ 684f0ba50c123082.e6c5ba2a47c7c3b9.d6f98fd6f1679fcc.f151a5054a9a4fe3
+ fcb7343662dae36d.5b35838f50055d0e.7136d79616138426.0148148e7e552a45
+ fcb7343662dae36d.e6c5ba2950055caa.7136d79671679fcc.f151a5057e552a45
+ bd9bdcc149b60637.0921de211853901b.38d4445c33e62fcc.1c918386720d45aa
+ e07a7acd6c23fc05
+
+VADDSUBPS_256(reg)
+ before
+ 974d972a89c376b5.a3b0549313e3ed6e.fb366826107da12b.1ccc613a63246e70
+ 9f54d50b677bed67.b297ddfde6f4b46b.cf19d6373ab75227.7bf113face02ed85
+ 52dc2fdba2d69ec6.c61cf5ebdff5155b.e11723c23390dfba.310dd48890896936
+ 0e31a406d561c57f.ba0a184919f2cc6a.8d7c4b3296918391.1aed22d1c6c79eb0
+ 125d77bf8cc8471e
+ after
+ 52dc2fdb677bed67.c61cf5ebe6f4b097.e11723c23ab74fe4.7bf113face02ed85
+ 9f54d50b677bed67.b297ddfde6f4b46b.cf19d6373ab75227.7bf113face02ed85
+ 52dc2fdba2d69ec6.c61cf5ebdff5155b.e11723c23390dfba.310dd48890896936
+ 0e31a406d561c57f.ba0a184919f2cc6a.8d7c4b3296918391.1aed22d1c6c79eb0
+ 125d77bf8cc8471e
+VADDSUBPS_256(mem)
+ before
+ f5295140fd9622ad.2d9e2df79ca79d3e.6c2fc003b1f897c3.2f944af300487b57
+ 9f1c2c3f353fe989.0d71c81d943464ae.b7556b05c2133093.23aa1c710c4003b9
+ ec0482a851cf58dd.08f46fe15995537c.7749943b694d5405.c50cbe1857055763
+ b7abd1666c502dd6.7c7520b08555a954.88d7b791c1b4be46.71042b547c24b200
+ 83df5f921828513d
+ after
+ f5295140fd9622ad.2d9e2df79ca79d3e.6c2fc003b1f897c3.2f944af300487b57
+ 9f1c2c3f353fe989.0d71c81d943464ae.b7556b05c2133093.23aa1c710c4003b9
+ f52951407d9622ad.2d9e2df71ca79ce4.6c2fc003c2133093.2f944af40c4003b8
+ b7abd1666c502dd6.7c7520b08555a954.88d7b791c1b4be46.71042b547c24b200
+ 83df5f921828513d
+
+VADDSUBPD_128(reg)
+ before
+ 57e9563cc69e6fc5.dede9467a3d0229f.c33ed7f6b700a0e1.c6cb50f4e7542b81
+ 496e0dbf22114a45.3c694797125bf465.3a9c8e20892375d0.0cf0dc4ef63757e4
+ b5ba7f88c90d1c69.ac1866e0d3fb5e53.3eda4398974964cc.3814d58d0a6bfe98
+ f618a802571e22dc.0cb76e2f05be1d96.2946f1cc7efea982.2501b99c40fcdbcc
+ ae840367b4f5acaa
+ after
+ 0000000000000000.0000000000000000.3eda4398974964cc.b814d58d0a6bfe98
+ 496e0dbf22114a45.3c694797125bf465.3a9c8e20892375d0.0cf0dc4ef63757e4
+ b5ba7f88c90d1c69.ac1866e0d3fb5e53.3eda4398974964cc.3814d58d0a6bfe98
+ f618a802571e22dc.0cb76e2f05be1d96.2946f1cc7efea982.2501b99c40fcdbcc
+ ae840367b4f5acaa
+VADDSUBPD_128(mem)
+ before
+ b16930da81622a5e.6ad6849867d1974b.3711da70c1b0ed5a.582a9427d9cf7f9d
+ 087cbae1c34f1415.6c3e0fb895b1b961.08f4269025dc8aca.27d42815444723ca
+ 91881f6897c924fb.579d46cd7e4bc1cb.5d2ace794d4eaf13.f38eaa015df2d0b5
+ 265bda5b18db173b.893f2443bd2aee34.10804e1954121a61.16a51459bd5dc409
+ ed65648902133973
+ after
+ b16930da81622a5e.6ad6849867d1974b.3711da70c1b0ed5a.582a9427d9cf7f9d
+ 087cbae1c34f1415.6c3e0fb895b1b961.08f4269025dc8aca.27d42815444723ca
+ 0000000000000000.0000000000000000.3711da70c1b0ed5a.d82a9427d9cf7f9d
+ 265bda5b18db173b.893f2443bd2aee34.10804e1954121a61.16a51459bd5dc409
+ ed65648902133973
+
+VADDSUBPD_128(reg)
+ before
+ d41996fbc8a06b9e.a5bf68a66391a902.5d70a587efda7b49.ffc2235b573584df
+ 270fa41caa919837.e881433693f8957b.2e7bc503b0e7a3b6.04bcc82b71c2acba
+ 42918c584471faea.cd6de9f5c51b99d4.5aae81249adea326.fd39b975bec54c1d
+ 81ec491c33cdce62.2e4fd5d114076e36.3b53d4574c4bb646.c40772255b4b2135
+ 36f07027645fe72d
+ after
+ 0000000000000000.0000000000000000.5aae81249adea326.7d39b975bec54c1d
+ 270fa41caa919837.e881433693f8957b.2e7bc503b0e7a3b6.04bcc82b71c2acba
+ 42918c584471faea.cd6de9f5c51b99d4.5aae81249adea326.fd39b975bec54c1d
+ 81ec491c33cdce62.2e4fd5d114076e36.3b53d4574c4bb646.c40772255b4b2135
+ 36f07027645fe72d
+VADDSUBPD_128(mem)
+ before
+ 30c12e67f40e5a32.406cd7d2132f504c.e8f383b49dc7d3cf.2fb7ba065fb819c2
+ 8c4628d127633570.db5d32e87f25bb53.d8246f8c7b6782cb.90262f9f71b30845
+ 274bda521a6a3512.ae0b56c9133b4c24.d8b01644cbf33856.bcec2f8c1ec8bf7c
+ de9cc0d4e82f1545.15c140e16cfc3f6b.c561f3c8a878b19b.0d54b73b01817a12
+ e0acc217b76c74b4
+ after
+ 30c12e67f40e5a32.406cd7d2132f504c.e8f383b49dc7d3cf.2fb7ba065fb819c2
+ 8c4628d127633570.db5d32e87f25bb53.d8246f8c7b6782cb.90262f9f71b30845
+ 0000000000000000.0000000000000000.e8f383b49dc7d3cf.afb7ba065fb819c2
+ de9cc0d4e82f1545.15c140e16cfc3f6b.c561f3c8a878b19b.0d54b73b01817a12
+ e0acc217b76c74b4
+
+VADDSUBPD_128(reg)
+ before
+ 923e4c8cdb14ea0d.8b045745aebf9334.6ccdeb9c25f4d0d3.7c0482042f01a9c6
+ 7d575106090617ca.0b511a908725690c.0e795366dbaf3a08.d7653fe47b9bdb05
+ fe43cef1decd3997.3a4d85a0906e53f9.591275ab29babab8.b350a654a8510481
+ 714ebdbaf6f58a1f.f4c51463e4a50f26.a8e44bd7aca08b8d.ec903441d32fdf69
+ 5ef3649518412ae7
+ after
+ 0000000000000000.0000000000000000.591275ab29babab8.d7653fe47b9bdb05
+ 7d575106090617ca.0b511a908725690c.0e795366dbaf3a08.d7653fe47b9bdb05
+ fe43cef1decd3997.3a4d85a0906e53f9.591275ab29babab8.b350a654a8510481
+ 714ebdbaf6f58a1f.f4c51463e4a50f26.a8e44bd7aca08b8d.ec903441d32fdf69
+ 5ef3649518412ae7
+VADDSUBPD_128(mem)
+ before
+ e543b23e91949f27.33c41ccbec0b460f.158544c4a0d657c0.573bd356ffeeeb33
+ 5d4d9a265d34fa57.9ef1e6915c9aab12.79588fafdf0ee8f2.c1630895bf2f1457
+ a2dd993b962bf9a0.0f201879e32ff3d5.fc0c7310be587ee9.44a7e6fe87ef43a5
+ 90bf2a6858875631.e29eacee1c545b04.7a6b6bd458c0d4d1.3b546afff4bbb3c8
+ 01b78f03a11da26d
+ after
+ e543b23e91949f27.33c41ccbec0b460f.158544c4a0d657c0.573bd356ffeeeb33
+ 5d4d9a265d34fa57.9ef1e6915c9aab12.79588fafdf0ee8f2.c1630895bf2f1457
+ 0000000000000000.0000000000000000.79588fafdf0ee8f2.d73bd356ffeeeb33
+ 90bf2a6858875631.e29eacee1c545b04.7a6b6bd458c0d4d1.3b546afff4bbb3c8
+ 01b78f03a11da26d
+
+VADDSUBPD_256(reg)
+ before
+ f41a51752aa44a40.03bfc999c053ce34.73b7a05ba4971f4a.cf43f4e5c953a7d5
+ 6ec9acc32cd9e7ec.d7a8f2bae99c1dd5.1eb7ef2e16847a54.d75e88302f1bb322
+ cd129c58434ab71e.e84821b7f06dfe42.3fea95d20fa6a9cd.6e89a5a2a327b3e3
+ 6b401ea00a83f481.1269d37cf0d22ea4.329c8fb32a89e862.708fc62643806545
+ b93e68a72a348374
+ after
+ 6ec9acc32cd9e7ec.684821b7f06dfe42.3fea95d20fa6a9cd.ee89a5a2a327b3e3
+ 6ec9acc32cd9e7ec.d7a8f2bae99c1dd5.1eb7ef2e16847a54.d75e88302f1bb322
+ cd129c58434ab71e.e84821b7f06dfe42.3fea95d20fa6a9cd.6e89a5a2a327b3e3
+ 6b401ea00a83f481.1269d37cf0d22ea4.329c8fb32a89e862.708fc62643806545
+ b93e68a72a348374
+VADDSUBPD_256(mem)
+ before
+ 25600513754fc99b.a69e2c081d0edbc2.31d883f506d8692a.5318d83d04b972bf
+ 8fc31b5540dbf5e7.d879c4fa1979a78c.2061ad0f4d8a6bfe.feab6cdd38c3858f
+ d5312559a5e6c183.5e1de2e3994f968c.bdd0cdb4e1f4ef4c.8fa147fd63325a7f
+ d2779f0bc37cea9c.95d680303a1de26e.e3f060d2df23b241.6246650a2093303a
+ d3e6c3710b70426d
+ after
+ 25600513754fc99b.a69e2c081d0edbc2.31d883f506d8692a.5318d83d04b972bf
+ 8fc31b5540dbf5e7.d879c4fa1979a78c.2061ad0f4d8a6bfe.feab6cdd38c3858f
+ 25600513754fc99b.d879c4fa1979a78c.31d883f506d8692a.feab6cdd38c3858f
+ d2779f0bc37cea9c.95d680303a1de26e.e3f060d2df23b241.6246650a2093303a
+ d3e6c3710b70426d
+
+VADDSUBPD_256(reg)
+ before
+ 3dcd5b9cc158cbc4.61610557b4a72b5e.d7f09c4b976ec7dd.6e8fe15363226f09
+ fe472bf9ded407ea.60bad42a947641f4.81b731a24dce8386.3977cc2588fde4cf
+ 719f2ff3fd72348c.aa50866e7ff2e88a.f0763ba0f7ca5015.22759d336ac1cbc0
+ f22261f6babd8c55.1aed99109329dc4e.7e7ab6b032ed6b35.0355d0692679e108
+ bae3e2b3d832e1d2
+ after
+ fe472bf9ded407ea.60bad42a947641f4.f0763ba0f7ca5015.3977cc2588fde4cf
+ fe472bf9ded407ea.60bad42a947641f4.81b731a24dce8386.3977cc2588fde4cf
+ 719f2ff3fd72348c.aa50866e7ff2e88a.f0763ba0f7ca5015.22759d336ac1cbc0
+ f22261f6babd8c55.1aed99109329dc4e.7e7ab6b032ed6b35.0355d0692679e108
+ bae3e2b3d832e1d2
+VADDSUBPD_256(mem)
+ before
+ 22ea4efd9bf6894b.dc1cbf6eb2424cf2.8e5f89fde926d86a.88109f4099c31092
+ 163890338bd4939e.8dd944c7808cb00e.e070d0209ff59a0a.6a81f0bbc9d97ad9
+ 73972441c5d5bbf8.5fa5ec6dc127f356.eeedec64d1a3db5b.801ca78d5dbae6b6
+ 16d486146407bf84.b0cbb3cc119f5276.92a158b79a3b5a89.262cc023f1f390d5
+ b8fc35e7220eb3e1
+ after
+ 22ea4efd9bf6894b.dc1cbf6eb2424cf2.8e5f89fde926d86a.88109f4099c31092
+ 163890338bd4939e.8dd944c7808cb00e.e070d0209ff59a0a.6a81f0bbc9d97ad9
+ 22ea4efd9bf6894b.5c1cbf6eb2424cf2.e070d0209ff59a0a.6a81f0bbc9d97ad9
+ 16d486146407bf84.b0cbb3cc119f5276.92a158b79a3b5a89.262cc023f1f390d5
+ b8fc35e7220eb3e1
+
+VADDSUBPD_256(reg)
+ before
+ 92da04468c9a8c86.d9bb33968575596f.db9996500a810919.aa5a900417cad1bf
+ 101028adca205771.9a18a6b5432b46e5.3b598f664b5954ec.10e21037635afd2a
+ 8eeb9d86782e504e.33b75b5bbb364111.2e589c786db16e9b.a207553c9af99af5
+ 68b75f3f334fb2c9.8164cf7608a10820.0ee2b8f40e1794d1.3a93d900d9b3644e
+ b5531a6d3b93165e
+ after
+ 101028aa566f886b.b3b75b5bbb364111.3b598f664b5954ec.2207553c9af99af5
+ 101028adca205771.9a18a6b5432b46e5.3b598f664b5954ec.10e21037635afd2a
+ 8eeb9d86782e504e.33b75b5bbb364111.2e589c786db16e9b.a207553c9af99af5
+ 68b75f3f334fb2c9.8164cf7608a10820.0ee2b8f40e1794d1.3a93d900d9b3644e
+ b5531a6d3b93165e
+VADDSUBPD_256(mem)
+ before
+ ef139470dda56d53.fac06b43970fba8c.61ea7cf14779553d.3843e045ca16023b
+ c59ec1f6dbf52459.a051bbfe3efba446.ad16e0b893c9e595.09c70ed73c3bf384
+ 11c21fe94f90f99c.b6b84ddcc79eaca1.42b476b7089d7354.dbb940150111a559
+ b04929375882a647.983f1c49cb850d4a.fc90badac301bca5.0c66716db4245165
+ f61b9e4bf1013655
+ after
+ ef139470dda56d53.fac06b43970fba8c.61ea7cf14779553d.3843e045ca16023b
+ c59ec1f6dbf52459.a051bbfe3efba446.ad16e0b893c9e595.09c70ed73c3bf384
+ ef139470dda56d53.7ac06b43970fba8c.61ea7cf14779553d.b843e045ca16023b
+ b04929375882a647.983f1c49cb850d4a.fc90badac301bca5.0c66716db4245165
+ f61b9e4bf1013655
+
+VCVTSS2SI_64(reg)
+ before
+ f622c11955338ed5.7e005bcb0fd5e786.a13325b1e93b04ec.b776290de0027cb5
+ 68c8d8447c469690.57b3319193977a87.2fe06280ba4ccd34.50323d3d7aac6fb0
+ a858de3801c78a33.172e2775fdd31973.9d92d122dd44a3ce.a18f7454ad0950c1
+ 1320cf628041a669.9a3dba636b968179.47946d04ebb0c365.875a49409627dc14
+ de5f39eb5111cfd6
+ after
+ f622c11955338ed5.7e005bcb0fd5e786.a13325b1e93b04ec.b776290de0027cb5
+ 68c8d8447c469690.57b3319193977a87.2fe06280ba4ccd34.50323d3d7aac6fb0
+ a858de3801c78a33.172e2775fdd31973.9d92d122dd44a3ce.a18f7454ad0950c1
+ 1320cf628041a669.9a3dba636b968179.47946d04ebb0c365.875a49409627dc14
+ 8000000000000000
+VCVTSS2SI_64(mem)
+ before
+ 826abe43f8d4e433.036aa72c964125df.bcab6547f9eb6ec3.88343390821b69a6
+ 4f475633aa7bd957.d5836304de514441.5946a40dc2de9b7d.bebc1d343e12d13c
+ 21c27ca78012686d.e5b8fe55f5ff3e3a.4dd8f4a2e37cc5d4.4379295bba2036d4
+ d4a6ac8b99a64da1.8f52748b76d75177.742ecff077d0a8f4.75b7527093d1d519
+ afc294e164b2eab8
+ after
+ 826abe43f8d4e433.036aa72c964125df.bcab6547f9eb6ec3.88343390821b69a6
+ 4f475633aa7bd957.d5836304de514441.5946a40dc2de9b7d.bebc1d343e12d13c
+ 21c27ca78012686d.e5b8fe55f5ff3e3a.4dd8f4a2e37cc5d4.4379295bba2036d4
+ d4a6ac8b99a64da1.8f52748b76d75177.742ecff077d0a8f4.75b7527093d1d519
+ 0000000000000000
+
+VCVTSS2SI_64(reg)
+ before
+ 4ce6eb19c94eb05d.43c163cb0e424620.2fa0c112fe64b7a3.aa14b3e59ae6ff09
+ a96e54845f3164b3.4cdd1b53fef20d16.21ede2562832ad6b.cb561b6b69cb883e
+ 23a8ca8ec1e84267.cac7520f82c35fae.c184d1c391cd6e7b.b3c08370008afdbf
+ 14de49a48cfe8625.994b83ecb8c0f715.6bb38cc5d4c2377e.3e1d68df792f1ab9
+ 473a45a4f3c79d58
+ after
+ 4ce6eb19c94eb05d.43c163cb0e424620.2fa0c112fe64b7a3.aa14b3e59ae6ff09
+ a96e54845f3164b3.4cdd1b53fef20d16.21ede2562832ad6b.cb561b6b69cb883e
+ 23a8ca8ec1e84267.cac7520f82c35fae.c184d1c391cd6e7b.b3c08370008afdbf
+ 14de49a48cfe8625.994b83ecb8c0f715.6bb38cc5d4c2377e.3e1d68df792f1ab9
+ 8000000000000000
+VCVTSS2SI_64(mem)
+ before
+ ace395ab885d40c7.da5dcd305cff6b98.95352bd4bcf59277.7bc40ec88e9c4421
+ 48e4d7e054fdc033.cf71529fcb772e6c.9950c4b5a96fecff.4d0454395ae7d10f
+ f709842f74b4d8c8.5066d55e78f30b4f.836acc799c39c1da.3cbf5882d43019f5
+ 941e1a84038d45b1.ba8751d8fcff3deb.2e4dbe0eb05fcc33.a64018119902597f
+ e6d58f5045eacd58
+ after
+ ace395ab885d40c7.da5dcd305cff6b98.95352bd4bcf59277.7bc40ec88e9c4421
+ 48e4d7e054fdc033.cf71529fcb772e6c.9950c4b5a96fecff.4d0454395ae7d10f
+ f709842f74b4d8c8.5066d55e78f30b4f.836acc799c39c1da.3cbf5882d43019f5
+ 941e1a84038d45b1.ba8751d8fcff3deb.2e4dbe0eb05fcc33.a64018119902597f
+ 0000000000000000
+
+VCVTSS2SI_64(reg)
+ before
+ 58c8b9ad7373b12d.fdef13cc1e94c31b.6722c278f62501ec.75c6165f01eecb37
+ 57669393bf2940a9.0c47edf1e0d60e31.b48124acfff493ff.36a15158acf17711
+ 41fb176ec699b779.9ff324e1665ee120.fdf174dfb5f52fd0.4caae9e5cc748fef
+ 71d343aa234d5248.90bf3286cb38fa13.9ebead7db4b6100a.92ac5cf27e84cdfa
+ e675256bde2cee61
+ after
+ 58c8b9ad7373b12d.fdef13cc1e94c31b.6722c278f62501ec.75c6165f01eecb37
+ 57669393bf2940a9.0c47edf1e0d60e31.b48124acfff493ff.36a15158acf17711
+ 41fb176ec699b779.9ff324e1665ee120.fdf174dfb5f52fd0.4caae9e5cc748fef
+ 71d343aa234d5248.90bf3286cb38fa13.9ebead7db4b6100a.92ac5cf27e84cdfa
+ 0000000000000000
+VCVTSS2SI_64(mem)
+ before
+ 22cfc03c0779ae4d.423a12b373d44cc3.bd7795ce2b711237.f334cbf297c2735a
+ 2387aa521575c8ed.127c81f551b7e296.00e7c8a4a314e8b8.599fcaaafba5946b
+ c6695e97252ffa6b.3be48add5a84506c.37da47f44f2e36c1.2a4aa6127becaeea
+ e54158f952b0fdf4.1bbf2bd529c6d2f2.3c1e8eaa4ac9b97f.c3835c94b322ff83
+ 8094e79e40d3c1e1
+ after
+ 22cfc03c0779ae4d.423a12b373d44cc3.bd7795ce2b711237.f334cbf297c2735a
+ 2387aa521575c8ed.127c81f551b7e296.00e7c8a4a314e8b8.599fcaaafba5946b
+ c6695e97252ffa6b.3be48add5a84506c.37da47f44f2e36c1.2a4aa6127becaeea
+ e54158f952b0fdf4.1bbf2bd529c6d2f2.3c1e8eaa4ac9b97f.c3835c94b322ff83
+ 0000000000000000
+
+VCVTSS2SI_32(reg)
+ before
+ bdca439abe8c30b1.5edb1463b90690b3.0c595f4b5b0aa3d4.ed7d1ab2b0f42d1e
+ d6716cf6c8d88a9e.0b030ec0753c6dd5.6cfe22a98bdb00bd.24c465f89eb84ec9
+ 26d45f1dfa440955.c984c3fea25e5185.95fa705d56c5255a.bebfed693023d7ac
+ 0b41167af15be982.742bad085d79f8f0.e59946d257554d56.973a2def804085f5
+ 8c01a277ad1c13cd
+ after
+ bdca439abe8c30b1.5edb1463b90690b3.0c595f4b5b0aa3d4.ed7d1ab2b0f42d1e
+ d6716cf6c8d88a9e.0b030ec0753c6dd5.6cfe22a98bdb00bd.24c465f89eb84ec9
+ 26d45f1dfa440955.c984c3fea25e5185.95fa705d56c5255a.bebfed693023d7ac
+ 0b41167af15be982.742bad085d79f8f0.e59946d257554d56.973a2def804085f5
+ 0000000000000000
+VCVTSS2SI_32(mem)
+ before
+ 77dfc7eed1c23f63.e0028f7b48a968d0.e9c44acac2991e42.b6269f742b16b55e
+ 35a2173f083ec3e1.0165c68b9cbac0eb.021b1630ecc87ea6.65ef77af6d94991d
+ a21410556f9c5b74.cab4b517881b2e81.9cfc8b27f814d549.4f3ecaefb95c3540
+ 9a022e1e21e9c547.963c5a89a957ee3c.933327990088de56.ce6095a0acf9c473
+ 3fa1d32ee2f78361
+ after
+ 77dfc7eed1c23f63.e0028f7b48a968d0.e9c44acac2991e42.b6269f742b16b55e
+ 35a2173f083ec3e1.0165c68b9cbac0eb.021b1630ecc87ea6.65ef77af6d94991d
+ a21410556f9c5b74.cab4b517881b2e81.9cfc8b27f814d549.4f3ecaefb95c3540
+ 9a022e1e21e9c547.963c5a89a957ee3c.933327990088de56.ce6095a0acf9c473
+ 0000000000000000
+
+VCVTSS2SI_32(reg)
+ before
+ fe4d7f06f6e3aeb7.f938eb853a30bb87.c349af4e9afb3bc8.c38b6573233157fa
+ 67af989284488020.9b81c576d87efa5f.ac26b2d3f89252d2.08d1c1a27b1afa61
+ d714174029b23749.5cab37de14de3efc.ad215f825ea86f06.3ed1b710244f83b6
+ a8c9fa7a80ae0cde.1880bda70c5c4289.2184b0c968c9ce0f.4157c4ab3bddb026
+ ed2f635edbce3bdc
+ after
+ fe4d7f06f6e3aeb7.f938eb853a30bb87.c349af4e9afb3bc8.c38b6573233157fa
+ 67af989284488020.9b81c576d87efa5f.ac26b2d3f89252d2.08d1c1a27b1afa61
+ d714174029b23749.5cab37de14de3efc.ad215f825ea86f06.3ed1b710244f83b6
+ a8c9fa7a80ae0cde.1880bda70c5c4289.2184b0c968c9ce0f.4157c4ab3bddb026
+ 0000000080000000
+VCVTSS2SI_32(mem)
+ before
+ 1e2510152131e105.37183bae26c73e8a.abced4bedc05c334.669ca312b382aa9a
+ b00447bc280f5ecd.e04ed847b68a07fa.f15ff6109fe47d26.d6b533cbdb5f4053
+ 7f9a843f0d766d5f.ffb6cdb1cd81a5d9.c600a18771052b8e.cf1b5c5f7beacce5
+ 67b1448aeb72cbe8.f09e1458063b51d4.067c50116f758b96.ab1a1a3a2fb189fd
+ c8fd6ac8943fb446
+ after
+ 1e2510152131e105.37183bae26c73e8a.abced4bedc05c334.669ca312b382aa9a
+ b00447bc280f5ecd.e04ed847b68a07fa.f15ff6109fe47d26.d6b533cbdb5f4053
+ 7f9a843f0d766d5f.ffb6cdb1cd81a5d9.c600a18771052b8e.cf1b5c5f7beacce5
+ 67b1448aeb72cbe8.f09e1458063b51d4.067c50116f758b96.ab1a1a3a2fb189fd
+ 0000000000000000
+
+VCVTSS2SI_32(reg)
+ before
+ 801247754621896d.44160289df0d3493.0f51aba8fe414a97.8da17f98b53f576a
+ 31a3adaee0e2441d.f1953a290455648d.b81a8d0d5021cacd.373aab0a5e6f4b37
+ 35fd98ddfe0e2003.4cfa685477561602.4746b6f499660e23.df124e5286122529
+ e96c046f3d325acb.301009f8531a071d.172122c7749c5244.63f6e65c4a339f6c
+ 9eb2ee14c5de762a
+ after
+ 801247754621896d.44160289df0d3493.0f51aba8fe414a97.8da17f98b53f576a
+ 31a3adaee0e2441d.f1953a290455648d.b81a8d0d5021cacd.373aab0a5e6f4b37
+ 35fd98ddfe0e2003.4cfa685477561602.4746b6f499660e23.df124e5286122529
+ e96c046f3d325acb.301009f8531a071d.172122c7749c5244.63f6e65c4a339f6c
+ 0000000080000000
+VCVTSS2SI_32(mem)
+ before
+ 6c12e36614206592.aa3ceed138d92e20.79a597ffb4aff20a.86f7cef37d50d1dd
+ a8e23f3f520429ce.d2b8516d8c8fd7af.02839057b72195f7.ef14b5e5510dc89a
+ 30ed80899c967e0b.be2e29b1d4e19223.a97770eb787baa0e.aec3d3088c607326
+ de0021320de32074.cae87208ad5a9b29.494db1a712c9ee7b.1e5124c7c9d40d2d
+ 9d0ba490a4f5d45d
+ after
+ 6c12e36614206592.aa3ceed138d92e20.79a597ffb4aff20a.86f7cef37d50d1dd
+ a8e23f3f520429ce.d2b8516d8c8fd7af.02839057b72195f7.ef14b5e5510dc89a
+ 30ed80899c967e0b.be2e29b1d4e19223.a97770eb787baa0e.aec3d3088c607326
+ de0021320de32074.cae87208ad5a9b29.494db1a712c9ee7b.1e5124c7c9d40d2d
+ 0000000080000000
+
+VCVTSD2SI_32(reg)
+ before
+ 863b50ceba4f0260.90e89e24c2f6ca36.533329deb2862e6d.bdd1d177a1171c6b
+ 342e23eda66fd3e2.206f744dd6db3a7d.b35b499f80f2869a.e3ce4a474272f20a
+ 052f195a05e18590.6c621e98659f2974.47acceb7b229e05d.95129a0310e52a83
+ 548c2e7f722f5216.4e8c17f08c4d5647.6b72b492e4b77862.b1673d98287c8003
+ 119aadf0a644b2b6
+ after
+ 863b50ceba4f0260.90e89e24c2f6ca36.533329deb2862e6d.bdd1d177a1171c6b
+ 342e23eda66fd3e2.206f744dd6db3a7d.b35b499f80f2869a.e3ce4a474272f20a
+ 052f195a05e18590.6c621e98659f2974.47acceb7b229e05d.95129a0310e52a83
+ 548c2e7f722f5216.4e8c17f08c4d5647.6b72b492e4b77862.b1673d98287c8003
+ 0000000080000000
+VCVTSD2SI_32(mem)
+ before
+ 927768f8a4487ac7.7c8f5fc98ae7771f.a4bbde4367f27b24.7bf8f79db3298a54
+ 11cae99d40959562.db86a7a5e8942f58.48b9ec7c11995534.d38b9442bb0a51df
+ 685facca9635beb5.cbbb017d29c3b86d.1854be88a64ea0a6.cf7886ee97e70ab0
+ 74022d6ac137b3e9.aa7b6cbfe8ff4c09.ee56d151431d18a4.cb09c90ee34bf073
+ 238b590d3cc241d3
+ after
+ 927768f8a4487ac7.7c8f5fc98ae7771f.a4bbde4367f27b24.7bf8f79db3298a54
+ 11cae99d40959562.db86a7a5e8942f58.48b9ec7c11995534.d38b9442bb0a51df
+ 685facca9635beb5.cbbb017d29c3b86d.1854be88a64ea0a6.cf7886ee97e70ab0
+ 74022d6ac137b3e9.aa7b6cbfe8ff4c09.ee56d151431d18a4.cb09c90ee34bf073
+ 0000000080000000
+
+VCVTSD2SI_32(reg)
+ before
+ 334933563dd8377d.127ee96bdea42e2d.d212e1d5c2d427d8.a78ca0c40413785b
+ 57915157831a0f1d.1ca05bb8088aecab.a0cb5e2d52cf8788.20c2a7cd043b7df6
+ eaadb17baa13045e.6f34ff3d5cf4a890.71f4de32357ba6c3.33c363595fa2e2a2
+ 4aea4f2e4c5053ed.e70651e6f5ef1f07.9fd75d500664c135.bd5d4e533253658a
+ 9a5ae6a6985ac0db
+ after
+ 334933563dd8377d.127ee96bdea42e2d.d212e1d5c2d427d8.a78ca0c40413785b
+ 57915157831a0f1d.1ca05bb8088aecab.a0cb5e2d52cf8788.20c2a7cd043b7df6
+ eaadb17baa13045e.6f34ff3d5cf4a890.71f4de32357ba6c3.33c363595fa2e2a2
+ 4aea4f2e4c5053ed.e70651e6f5ef1f07.9fd75d500664c135.bd5d4e533253658a
+ 0000000000000000
+VCVTSD2SI_32(mem)
+ before
+ a687a640aec3afc1.d29525dc085b3875.61e2cea0ef860d3d.87c1d7f36117138b
+ bdb00b0c8f9bf067.def831f277c3efa3.b794f05567c52e5d.86fe4887e31fda71
+ bba18ff658ee3dfa.ca5f6dda3711b423.c6e735f279b83d94.f6daad7928085092
+ 7d26b0ea24c653a5.f118d801e4d3c2a0.6aa81864406cf70e.34a10133ca5fb29b
+ 9c9e402268af3b37
+ after
+ a687a640aec3afc1.d29525dc085b3875.61e2cea0ef860d3d.87c1d7f36117138b
+ bdb00b0c8f9bf067.def831f277c3efa3.b794f05567c52e5d.86fe4887e31fda71
+ bba18ff658ee3dfa.ca5f6dda3711b423.c6e735f279b83d94.f6daad7928085092
+ 7d26b0ea24c653a5.f118d801e4d3c2a0.6aa81864406cf70e.34a10133ca5fb29b
+ 0000000000000000
+
+VCVTSD2SI_32(reg)
+ before
+ 8a1f67b39c842813.dd0ae9d40f31ee95.b16d6bd4199455c7.7fa31696d8ed18f6
+ 5b6e7051026bb5db.b81bb6a0363ac9f6.64ac23bd73e1ab43.e1a4a9735e455b79
+ 69d8596737ef1e3a.e923933bb5eea1f3.681ffd2a8d45fec1.6c774fe9ed827ec2
+ 11a91d63d69d9edd.4eeffd8fa75832b9.1813f486034c8bec.fce883e3a2af3bfe
+ 6dc2c14d98d94e59
+ after
+ 8a1f67b39c842813.dd0ae9d40f31ee95.b16d6bd4199455c7.7fa31696d8ed18f6
+ 5b6e7051026bb5db.b81bb6a0363ac9f6.64ac23bd73e1ab43.e1a4a9735e455b79
+ 69d8596737ef1e3a.e923933bb5eea1f3.681ffd2a8d45fec1.6c774fe9ed827ec2
+ 11a91d63d69d9edd.4eeffd8fa75832b9.1813f486034c8bec.fce883e3a2af3bfe
+ 0000000080000000
+VCVTSD2SI_32(mem)
+ before
+ 9bd38613ec0b75fe.af2db8b07cff726f.c24b6f8a29843773.cfd4043d72838e71
+ 61e54c21b9516a19.9faf27bac4a3d69d.21036516557f6e4e.ebad29bb767442fc
+ 9dc591631cb8ead8.3d7d64ed4b150613.47e35b214a549176.c6ec606caaaee538
+ 2a3fd0c6304bb065.e4e16db6ace03d7c.10b6ce96220f5c16.bedba4bcaabab0d2
+ 2dc8f1171326e276
+ after
+ 9bd38613ec0b75fe.af2db8b07cff726f.c24b6f8a29843773.cfd4043d72838e71
+ 61e54c21b9516a19.9faf27bac4a3d69d.21036516557f6e4e.ebad29bb767442fc
+ 9dc591631cb8ead8.3d7d64ed4b150613.47e35b214a549176.c6ec606caaaee538
+ 2a3fd0c6304bb065.e4e16db6ace03d7c.10b6ce96220f5c16.bedba4bcaabab0d2
+ 0000000080000000
+
+VCVTSD2SI_64(reg)
+ before
+ 70fd43ea807eb5cf.e41f8534111679ec.f2283e7f8390b885.58493861f9bd8d5a
+ e4c7979f8e4c6689.a7302d9bdc26019a.c29ed1b56eb1b2d9.fa68176eec69de70
+ e371e7a4d91e3152.4e4043e5ad86049b.b08f23c506d06925.d4dfe6a9161f0c82
+ ca493163fb8052d3.b71943009f423d1a.18473119e9781715.c17a22fe94ecd2bc
+ 9c05455981dbed4b
+ after
+ 70fd43ea807eb5cf.e41f8534111679ec.f2283e7f8390b885.58493861f9bd8d5a
+ e4c7979f8e4c6689.a7302d9bdc26019a.c29ed1b56eb1b2d9.fa68176eec69de70
+ e371e7a4d91e3152.4e4043e5ad86049b.b08f23c506d06925.d4dfe6a9161f0c82
+ ca493163fb8052d3.b71943009f423d1a.18473119e9781715.c17a22fe94ecd2bc
+ 8000000000000000
+VCVTSD2SI_64(mem)
+ before
+ 434ccda7faf8195b.f599704a93fc04bb.bc88a9d7ce676944.5611f61fb336f954
+ 901a35d21a501217.c1afa1c43a2084b4.3b59f15657004445.c53b6e42ff954a8e
+ 613cf9c8feee93ac.88d5be3d8e780d6b.0f589869561a8a48.c30f96ee69214771
+ 917e9673c1df5a46.a758c5212b8edd8b.135019fce6bff67a.abda698f8e662ca7
+ d8e8e29109f135dc
+ after
+ 434ccda7faf8195b.f599704a93fc04bb.bc88a9d7ce676944.5611f61fb336f954
+ 901a35d21a501217.c1afa1c43a2084b4.3b59f15657004445.c53b6e42ff954a8e
+ 613cf9c8feee93ac.88d5be3d8e780d6b.0f589869561a8a48.c30f96ee69214771
+ 917e9673c1df5a46.a758c5212b8edd8b.135019fce6bff67a.abda698f8e662ca7
+ 8000000000000000
+
+VCVTSD2SI_64(reg)
+ before
+ a8850060774d9ebd.fbac86c1802d2010.7a84b1dcacf02ec1.250ff0fb23fd4506
+ 75fcbc687307a2f6.7c92479d56e7a436.5da47edaae2a3cb8.1f5f99532ae03319
+ 9d9b13159aaa7e32.f1fb54f35f16a0e6.ac062887ccc7451d.df0d91ee16737bde
+ 7bac02d487c26d1e.34b52aafb8c8d14a.c3f4ac50a253839c.3fe552b904c2da82
+ 1cb35aa10fd90c31
+ after
+ a8850060774d9ebd.fbac86c1802d2010.7a84b1dcacf02ec1.250ff0fb23fd4506
+ 75fcbc687307a2f6.7c92479d56e7a436.5da47edaae2a3cb8.1f5f99532ae03319
+ 9d9b13159aaa7e32.f1fb54f35f16a0e6.ac062887ccc7451d.df0d91ee16737bde
+ 7bac02d487c26d1e.34b52aafb8c8d14a.c3f4ac50a253839c.3fe552b904c2da82
+ 0000000000000000
+VCVTSD2SI_64(mem)
+ before
+ 5343249154c5cd16.6a7c840fd7dcac66.238a43bd7d08f38e.febb059fcd5a33e0
+ be612d75ee91d85e.c7579534258377b5.98471d09c9e2c2df.b9a72fe2e9699196
+ 3ad8ef38fa4aea35.ef8932ae0e430ab7.70b83380b863f969.50042683900bd869
+ a475e8c893fbbfc6.3c5d55e92da9a11a.88a9010c67965557.1f1ee7f061cd4506
+ 82416d94f6391418
+ after
+ 5343249154c5cd16.6a7c840fd7dcac66.238a43bd7d08f38e.febb059fcd5a33e0
+ be612d75ee91d85e.c7579534258377b5.98471d09c9e2c2df.b9a72fe2e9699196
+ 3ad8ef38fa4aea35.ef8932ae0e430ab7.70b83380b863f969.50042683900bd869
+ a475e8c893fbbfc6.3c5d55e92da9a11a.88a9010c67965557.1f1ee7f061cd4506
+ 8000000000000000
+
+VCVTSD2SI_64(reg)
+ before
+ d5b8b4dbebdd804d.d6049310d5b0133d.0c21fc501f407788.bae6049bf18891d6
+ 74d0b831dd45c74e.ad516cfddd75a1c7.b91f22517f94c9ad.e33ab61773446b11
+ bad5750267fc23ca.0528f079c7572690.a0a4c458e932d236.df73956e08d69d35
+ 0513e8ba268ed06b.ba559a71ae615dc4.1dfcdccffaa5d0cf.8a5b1c8bcd4be36e
+ c0bfc85addadfbe7
+ after
+ d5b8b4dbebdd804d.d6049310d5b0133d.0c21fc501f407788.bae6049bf18891d6
+ 74d0b831dd45c74e.ad516cfddd75a1c7.b91f22517f94c9ad.e33ab61773446b11
+ bad5750267fc23ca.0528f079c7572690.a0a4c458e932d236.df73956e08d69d35
+ 0513e8ba268ed06b.ba559a71ae615dc4.1dfcdccffaa5d0cf.8a5b1c8bcd4be36e
+ 8000000000000000
+VCVTSD2SI_64(mem)
+ before
+ 5e6b13c7550b9fcd.b0d60cc6b5880cdd.a8a3e5d2aea0048e.8d7368234e79fd23
+ 3e2a7bbe506e8c4b.166add90b17411cd.abdf5086e41fd51a.4a5563c07f3b95df
+ 3dca7b2bebe47e8e.951a5786b5e11ce7.9fd5547b6cea8c96.b1eec9132c76d6ae
+ 37158ffa417830c2.883476125d5868d6.60516e9b600ee72b.1e899686efb6fa3d
+ ed73c78764883e38
+ after
+ 5e6b13c7550b9fcd.b0d60cc6b5880cdd.a8a3e5d2aea0048e.8d7368234e79fd23
+ 3e2a7bbe506e8c4b.166add90b17411cd.abdf5086e41fd51a.4a5563c07f3b95df
+ 3dca7b2bebe47e8e.951a5786b5e11ce7.9fd5547b6cea8c96.b1eec9132c76d6ae
+ 37158ffa417830c2.883476125d5868d6.60516e9b600ee72b.1e899686efb6fa3d
+ 0000000000000000
+
+VDPPS_128_1of4(reg)
+ before
+ 7af857812877de4a.08d933176e375f12.4a0237a246673347.ca1f1bd4df96a008
+ 216442e0d60f1520.8be0e46f8f2cc7ab.39d195a10c99b7e6.b90bd611038e7457
+ 3e0384100bdd2065.9ef71decc06323b8.afed8c7b4a7b305e.09e01b3ee8031f44
+ 2d21197d626c3bc6.1ce95a7c1ce93166.0aa1199c9c98dc5b.966c6747ab005cfc
+ 3c7935186791e8ab
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 216442e0d60f1520.8be0e46f8f2cc7ab.39d195a10c99b7e6.b90bd611038e7457
+ 3e0384100bdd2065.9ef71decc06323b8.afed8c7b4a7b305e.09e01b3ee8031f44
+ 2d21197d626c3bc6.1ce95a7c1ce93166.0aa1199c9c98dc5b.966c6747ab005cfc
+ 3c7935186791e8ab
+VDPPS_128_1of4(mem)
+ before
+ d7d4009e38c37f7c.4a09fe937849a1ef.e184170abfc9abe1.a43b36709f7cf58b
+ 434947c33ba1dd9c.f1082ebee8ff908b.c993d081c60f4d54.db05e163efb4b898
+ 5ba483748c37bd37.7e6ba56a4e1a4147.b0e102cf4cc8d5ec.094c15e127cb602e
+ fdb0319e4692dc78.4d7c5f044726f3ce.713b28df6efffdd4.8c5cce57e34d2bfa
+ be81092fc0c753a8
+ after
+ d7d4009e38c37f7c.4a09fe937849a1ef.e184170abfc9abe1.a43b36709f7cf58b
+ 434947c33ba1dd9c.f1082ebee8ff908b.c993d081c60f4d54.db05e163efb4b898
+ 5ba483748c37bd37.7e6ba56a4e1a4147.b0e102cf4cc8d5ec.094c15e127cb602e
+ fdb0319e4692dc78.4d7c5f044726f3ce.713b28df6efffdd4.8c5cce57e34d2bfa
+ be81092fc0c753a8
+
+VDPPS_128_1of4(reg)
+ before
+ fc07c0d759c414e3.043bce2c86bdf58c.ba8759f66fb0e0cd.ea6dbe9d47c08239
+ a33af1b94bd0ac58.4b0fd50967c4c69e.21da8eae614346f0.f64341f6f4181f46
+ 0d659743317855b2.b0f9c22305b409db.ddc0fa96ba6c5ee2.70892bd491129129
+ 97d5afe0a8474c9e.0ec512657d987b6f.4c84991c14b6674f.360afa2438bb940b
+ 239329d3071de41b
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ a33af1b94bd0ac58.4b0fd50967c4c69e.21da8eae614346f0.f64341f6f4181f46
+ 0d659743317855b2.b0f9c22305b409db.ddc0fa96ba6c5ee2.70892bd491129129
+ 97d5afe0a8474c9e.0ec512657d987b6f.4c84991c14b6674f.360afa2438bb940b
+ 239329d3071de41b
+VDPPS_128_1of4(mem)
+ before
+ 12f134cb1a463c82.9dd733fc4bc9ccc8.403f3fbbeb7cd785.c97368ab0ead9be5
+ e1ee98fa8c425a6f.7bb52103b68b13db.2432c711696ddb49.afd961af42dd374e
+ 6a57cf4b7a1cf70c.8dbb746186185b84.946c2553167641e9.5c0282944cd37736
+ 8bf757aaffe0d286.2f37288257fce16e.6eb7d56e0ca4c58f.2b3ac6c6c91a964a
+ 77cc29b1543fd136
+ after
+ 12f134cb1a463c82.9dd733fc4bc9ccc8.403f3fbbeb7cd785.c97368ab0ead9be5
+ e1ee98fa8c425a6f.7bb52103b68b13db.2432c711696ddb49.afd961af42dd374e
+ 6a57cf4b7a1cf70c.8dbb746186185b84.946c2553167641e9.5c0282944cd37736
+ 8bf757aaffe0d286.2f37288257fce16e.6eb7d56e0ca4c58f.2b3ac6c6c91a964a
+ 77cc29b1543fd136
+
+VDPPS_128_1of4(reg)
+ before
+ 9e06a8c28acd64a5.1e9cab03379aa508.be743ad2c4c4e046.8ce0544c67012567
+ fa323e6306508b44.001048423f572dbf.94bda4be6afb95b8.ccb31ddb449b1b9e
+ e99de702655581bf.0e21a853332226d6.0e5f64b0e42e3c6f.08fcac05be7e6460
+ c5939f09426783c1.229949222e084c7a.88a67516cee71118.1d877db8f2b5bbd8
+ e8200cdffb4cde33
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ fa323e6306508b44.001048423f572dbf.94bda4be6afb95b8.ccb31ddb449b1b9e
+ e99de702655581bf.0e21a853332226d6.0e5f64b0e42e3c6f.08fcac05be7e6460
+ c5939f09426783c1.229949222e084c7a.88a67516cee71118.1d877db8f2b5bbd8
+ e8200cdffb4cde33
+VDPPS_128_1of4(mem)
+ before
+ 4392d665f54f879c.ec6062e63a12cdf6.1945a69b4c135ad7.5dded35ac5b44f5e
+ 0baa5638fdcb7340.b8502d04e8e39a0c.d0f13babaa520d18.eb537bea642133ee
+ 1c3408432fcb5d4b.86aefbcfe86527ad.2168853c63ce206a.8d50683148b9f974
+ 53fc6873a65c02e8.b3c8c8b3d724b085.e978fe3c949551f8.9f23969b0c08dd9b
+ 7d1601944d9a1a10
+ after
+ 4392d665f54f879c.ec6062e63a12cdf6.1945a69b4c135ad7.5dded35ac5b44f5e
+ 0baa5638fdcb7340.b8502d04e8e39a0c.d0f13babaa520d18.eb537bea642133ee
+ 1c3408432fcb5d4b.86aefbcfe86527ad.2168853c63ce206a.8d50683148b9f974
+ 53fc6873a65c02e8.b3c8c8b3d724b085.e978fe3c949551f8.9f23969b0c08dd9b
+ 7d1601944d9a1a10
+
+VDPPS_128_2of4(reg)
+ before
+ 8376a588a6fced7e.8acef2b27f891e44.99e8901c51ad7141.04eb249558b25af0
+ 0c8f7fe3b4b99292.9e7623edd55e6d8a.955b5076f18ba58d.4e8e7235cc32f77b
+ 76ad8a12125e44f8.6bbf7611c4e8aae7.046d022d534a8914.a32d64070b20e6c7
+ 1c1bc27f5d76405b.cd76670869329287.4069a4ae14775983.e09477f73288e100
+ df8f26f15c76a552
+ after
+ 0000000000000000.0000000000000000.ff80000000000000.ff80000000000000
+ 0c8f7fe3b4b99292.9e7623edd55e6d8a.955b5076f18ba58d.4e8e7235cc32f77b
+ 76ad8a12125e44f8.6bbf7611c4e8aae7.046d022d534a8914.a32d64070b20e6c7
+ 1c1bc27f5d76405b.cd76670869329287.4069a4ae14775983.e09477f73288e100
+ df8f26f15c76a552
+VDPPS_128_2of4(mem)
+ before
+ 7deaede1a6f7eee8.59272398308dc267.a06772c0df48e195.a69d3163d09d5185
+ 967048b42b1777ee.8b1baac7283006ca.c05e14234336523e.9253a6ba2248acc7
+ 06eeb35407e0fd91.0d44517ae0e9472e.0927c81fb009a3ad.60d9fd1da605a7f5
+ a830abae57603cfd.3aee161cf447c23f.578e0a9f43cd8e0f.6c7934faf95f7dba
+ 128046bcb6e26cc3
+ after
+ 7deaede1a6f7eee8.59272398308dc267.a06772c0df48e195.a69d3163d09d5185
+ 967048b42b1777ee.8b1baac7283006ca.c05e14234336523e.9253a6ba2248acc7
+ 06eeb35407e0fd91.0d44517ae0e9472e.0927c81fb009a3ad.60d9fd1da605a7f5
+ a830abae57603cfd.3aee161cf447c23f.578e0a9f43cd8e0f.6c7934faf95f7dba
+ 128046bcb6e26cc3
+
+VDPPS_128_2of4(reg)
+ before
+ ae3930cf7a1baebb.5a02abaf37a3ef5d.7065f41901d3b2aa.865e568f178ccf90
+ 9cf2ec9fe095804f.f7302f42c2b3d4de.09f5e8dda31b551b.726528db4954245b
+ 38f5789885dd1d2b.5b86b352149ea5ac.63eaecd475abe53d.f76dfd6ff431479d
+ de90cf26047dc2fa.62cfb3cd4a6f1ef2.d88ffe6a130d9fbd.f0435038352df581
+ 3bb39d202756e934
+ after
+ 0000000000000000.0000000000000000.fe12e87b00000000.fe12e87b00000000
+ 9cf2ec9fe095804f.f7302f42c2b3d4de.09f5e8dda31b551b.726528db4954245b
+ 38f5789885dd1d2b.5b86b352149ea5ac.63eaecd475abe53d.f76dfd6ff431479d
+ de90cf26047dc2fa.62cfb3cd4a6f1ef2.d88ffe6a130d9fbd.f0435038352df581
+ 3bb39d202756e934
+VDPPS_128_2of4(mem)
+ before
+ b3896014e7b8e0e2.ea0dedb6f904ab69.e8d8ac9e8033fddd.c631190b1acfbf47
+ 34901601905d96b6.b8b9ceb201fb1423.c86e19b1d0f5fc98.871c3923257c8086
+ 999639d23e53c7dd.a4e06f87b8f038d5.e05b76f259c2d850.789c5b1fd1a11f26
+ c06547720ea62e82.09cdcaa2b96e542b.0b6b3f4d34a44c31.f6fd7969b9c9d8d5
+ 5b8b916f7a80e63c
+ after
+ b3896014e7b8e0e2.ea0dedb6f904ab69.e8d8ac9e8033fddd.c631190b1acfbf47
+ 34901601905d96b6.b8b9ceb201fb1423.c86e19b1d0f5fc98.871c3923257c8086
+ 999639d23e53c7dd.a4e06f87b8f038d5.e05b76f259c2d850.789c5b1fd1a11f26
+ c06547720ea62e82.09cdcaa2b96e542b.0b6b3f4d34a44c31.f6fd7969b9c9d8d5
+ 5b8b916f7a80e63c
+
+VDPPS_128_2of4(reg)
+ before
+ 04919e9caf53860a.84cabccf1c6088d2.45cedd6ea002a4d0.246cf1af80a91566
+ 4d5c9d5cf5cdf4e9.c09112d4839091f8.b32da4560a366470.0929070256ddef1b
+ 9238881ae77a6c85.5286c76d5f3f0521.af3719c89399cfb9.956dfd33d54a967e
+ 30715d4422e7298c.14755586cd7b9f79.94393a2fd6b42255.a3054f2f16ffc5b9
+ 11bd79e137053af8
+ after
+ 0000000000000000.0000000000000000.ecafa12300000000.ecafa12300000000
+ 4d5c9d5cf5cdf4e9.c09112d4839091f8.b32da4560a366470.0929070256ddef1b
+ 9238881ae77a6c85.5286c76d5f3f0521.af3719c89399cfb9.956dfd33d54a967e
+ 30715d4422e7298c.14755586cd7b9f79.94393a2fd6b42255.a3054f2f16ffc5b9
+ 11bd79e137053af8
+VDPPS_128_2of4(mem)
+ before
+ b961f834546aae68.81531746419f68a7.e4293b0be84f1c2b.c07c02f76f1599f0
+ 79bd47168839e035.e22ab28ae02f6585.9c6ff2e9cdc73864.8e4f6d8dfb476f37
+ 2b9de272ef7e8a8a.af412b7d9d215bd0.1a13f70a98f0ae50.59fd775b15d7e1d6
+ accc4534a6466994.44e67c8b11048834.38e2c75c63d53b1a.7fd11dce5a502b78
+ 5a185953653e89ca
+ after
+ b961f834546aae68.81531746419f68a7.e4293b0be84f1c2b.c07c02f76f1599f0
+ 79bd47168839e035.e22ab28ae02f6585.9c6ff2e9cdc73864.8e4f6d8dfb476f37
+ 2b9de272ef7e8a8a.af412b7d9d215bd0.1a13f70a98f0ae50.59fd775b15d7e1d6
+ accc4534a6466994.44e67c8b11048834.38e2c75c63d53b1a.7fd11dce5a502b78
+ 5a185953653e89ca
+
+VDPPS_128_3of4(reg)
+ before
+ 481f2954d32e3678.d917ed48c99c397f.fd63a321da61265f.d3a5ddc94d839bee
+ a330893f3fab6f2d.8c4a559b738db676.36059ba993c671fa.c82bb53f6f048afa
+ c897737e46417095.a231f917c0249ba5.4b186191d9bea7b4.f13fcba9e767c368
+ 14a2e57f837d745e.f89855a9cd6da539.98e8ef4448d50237.2bac9cf3d1b50364
+ 533fa30848fc061b
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ a330893f3fab6f2d.8c4a559b738db676.36059ba993c671fa.c82bb53f6f048afa
+ c897737e46417095.a231f917c0249ba5.4b186191d9bea7b4.f13fcba9e767c368
+ 14a2e57f837d745e.f89855a9cd6da539.98e8ef4448d50237.2bac9cf3d1b50364
+ 533fa30848fc061b
+VDPPS_128_3of4(mem)
+ before
+ 43c45cd7694788b9.e19bd9ad92eab831.684be53eb5748f5e.79c0432e7b98be2f
+ d80743494fa34469.8dd04d74101478bd.cf1526c095461740.49ee58bb0e92194a
+ eed4d54b161bf758.728b3d409988f0ac.09c4931d89eef70a.66bc2a579e504d31
+ 61f78cc9dbbb5cb1.ed19a37dc8d15bab.f222a840ab79ebe8.2b77b56ec65d9793
+ f46bf66c2345331a
+ after
+ 43c45cd7694788b9.e19bd9ad92eab831.684be53eb5748f5e.79c0432e7b98be2f
+ d80743494fa34469.8dd04d74101478bd.cf1526c095461740.49ee58bb0e92194a
+ eed4d54b161bf758.728b3d409988f0ac.09c4931d89eef70a.66bc2a579e504d31
+ 61f78cc9dbbb5cb1.ed19a37dc8d15bab.f222a840ab79ebe8.2b77b56ec65d9793
+ f46bf66c2345331a
+
+VDPPS_128_3of4(reg)
+ before
+ 1ce4e8bd50945c72.0d3be6b0ba8f31a1.5ac67d98397bf665.67fce11519f2b108
+ 012d87cee9d74f48.cf6d5eeacea43054.16dec6fb8913fd87.421ebb88ef650393
+ fe94cf098c994848.815a7165330615f5.7bac7a135424abbc.6053b08548df9eb8
+ 6e63bddcd267831d.00cc990c06bf9eb1.e67e954d353a3eb1.9d693ef8416b3ea1
+ d52ae1cdf5159e7a
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 012d87cee9d74f48.cf6d5eeacea43054.16dec6fb8913fd87.421ebb88ef650393
+ fe94cf098c994848.815a7165330615f5.7bac7a135424abbc.6053b08548df9eb8
+ 6e63bddcd267831d.00cc990c06bf9eb1.e67e954d353a3eb1.9d693ef8416b3ea1
+ d52ae1cdf5159e7a
+VDPPS_128_3of4(mem)
+ before
+ e46413f181e97b71.afe74bb259cc3b74.288f54ca62dd85b3.b39e1414c8e2ef12
+ a6e1524e00f491af.1c6c77f6bd54adf9.d4711d8d646b8728.3e59f2d3aaa7fd8a
+ f66e18d18e429b63.103e3c16998c1557.e23d70402776603c.e3fb2bf87615a2c6
+ b2d6e36748dd57b7.e9a9977d89ffae3a.2dbecacfc809cb1a.fed0bbeec9b91b71
+ eb239f213e1ea438
+ after
+ e46413f181e97b71.afe74bb259cc3b74.288f54ca62dd85b3.b39e1414c8e2ef12
+ a6e1524e00f491af.1c6c77f6bd54adf9.d4711d8d646b8728.3e59f2d3aaa7fd8a
+ f66e18d18e429b63.103e3c16998c1557.e23d70402776603c.e3fb2bf87615a2c6
+ b2d6e36748dd57b7.e9a9977d89ffae3a.2dbecacfc809cb1a.fed0bbeec9b91b71
+ eb239f213e1ea438
+
+VDPPS_128_3of4(reg)
+ before
+ 0642d1fd72d179c7.b5e72ffb49d37fd7.01f882972a39b550.91c1a526623085ef
+ ab774fef005cd5c9.db6c7679ae30cff0.b579fbd118c76643.ea127f3212f84ae6
+ 360f1461844df5eb.003036cd93fe052e.6276fd95ed34fdbf.147dd3ddf36cd62c
+ 03561dc09b3015d8.ff00eae3134bdbbc.623c8450480cb571.eace1e152198e4ec
+ 4ad0dac4ba893154
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ ab774fef005cd5c9.db6c7679ae30cff0.b579fbd118c76643.ea127f3212f84ae6
+ 360f1461844df5eb.003036cd93fe052e.6276fd95ed34fdbf.147dd3ddf36cd62c
+ 03561dc09b3015d8.ff00eae3134bdbbc.623c8450480cb571.eace1e152198e4ec
+ 4ad0dac4ba893154
+VDPPS_128_3of4(mem)
+ before
+ 0f5185d8d74a788d.6d986479e190703d.b6a80ea74a230ec7.13178d6fc3dbcb05
+ 151b9a3b96e777c6.d221e7f6f1f943c5.00f41e055590597b.cf53135cfa2e7b26
+ 37fb95db136de828.8d3ca1a567f7ca1e.b8b097e94fa07903.f33b11858a910081
+ 53bdf2a368e788e2.fa378ef1e01740f1.bca7f440555f2a8c.db1d86550e8e97c1
+ e4436b3722b47c93
+ after
+ 0f5185d8d74a788d.6d986479e190703d.b6a80ea74a230ec7.13178d6fc3dbcb05
+ 151b9a3b96e777c6.d221e7f6f1f943c5.00f41e055590597b.cf53135cfa2e7b26
+ 37fb95db136de828.8d3ca1a567f7ca1e.b8b097e94fa07903.f33b11858a910081
+ 53bdf2a368e788e2.fa378ef1e01740f1.bca7f440555f2a8c.db1d86550e8e97c1
+ e4436b3722b47c93
+
+VDPPS_128_4of4(reg)
+ before
+ 68fabd99648ceba3.432d2e7fb462121e.745cab46f8e5e3ed.e7a7b1f482d82841
+ c48e79e66da41f9c.e517c45b11e84409.59f8f2104aebedbc.147a4af3f2172e4f
+ 544b9a8adb87552b.134630249b87d8ce.045761bb72b79a0a.21ed3b27c328fae1
+ 747d1cf24ac1c9fb.ab87eec46f4b8a9a.d0c4f3b30dd42884.e8cc017e0e184524
+ 47e217e3f1f2ce44
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ c48e79e66da41f9c.e517c45b11e84409.59f8f2104aebedbc.147a4af3f2172e4f
+ 544b9a8adb87552b.134630249b87d8ce.045761bb72b79a0a.21ed3b27c328fae1
+ 747d1cf24ac1c9fb.ab87eec46f4b8a9a.d0c4f3b30dd42884.e8cc017e0e184524
+ 47e217e3f1f2ce44
+VDPPS_128_4of4(mem)
+ before
+ 18fdf94288c24f6c.806ffc8855dfb7b9.87a77b28a83f1898.1b8da564b6cfd1d6
+ 38e72387ee9585c9.d46e34b9986c5a11.8570513d636f3cf5.3ffc713a0a33d2ab
+ 846e129e3f762c87.ccc7c2f2b0f4efae.7faeeeedbbe7b3dd.9a5f55a2a48c66b0
+ d65c4173987200d1.c4c4a19d3904b13d.522fcd26cdb4387b.86004c062167cb91
+ 612c52d41c4f3bf9
+ after
+ 18fdf94288c24f6c.806ffc8855dfb7b9.87a77b28a83f1898.1b8da564b6cfd1d6
+ 38e72387ee9585c9.d46e34b9986c5a11.8570513d636f3cf5.3ffc713a0a33d2ab
+ 846e129e3f762c87.ccc7c2f2b0f4efae.7faeeeedbbe7b3dd.9a5f55a2a48c66b0
+ d65c4173987200d1.c4c4a19d3904b13d.522fcd26cdb4387b.86004c062167cb91
+ 612c52d41c4f3bf9
+
+VDPPS_128_4of4(reg)
+ before
+ 852f647732d0f294.0b7e2cf21494bcd3.18b2ce28ce27de69.dbbe6bd3b4e189fc
+ 50547c5bfe762e10.00a04f08d0e81dbb.24dc43fe0beab0df.f42642e08d7b608c
+ 1ce998eb1cce2916.8f8d269fe87adeb2.4490fe8b8dd8644b.7a34d039738d7a56
+ 4638b39529642055.95132ea57657bde7.d418fa3bef7d3558.49b490ca82239286
+ 3e72ff7fd749654a
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 50547c5bfe762e10.00a04f08d0e81dbb.24dc43fe0beab0df.f42642e08d7b608c
+ 1ce998eb1cce2916.8f8d269fe87adeb2.4490fe8b8dd8644b.7a34d039738d7a56
+ 4638b39529642055.95132ea57657bde7.d418fa3bef7d3558.49b490ca82239286
+ 3e72ff7fd749654a
+VDPPS_128_4of4(mem)
+ before
+ 333a97448e0cafcb.2b8ec9c5c1c24e77.eefce205998a7484.2fc2337ace6560b3
+ 05d8d605c2772c38.2537d7e57f76f129.7615beaa6a20bfb6.b3d8a5b4c51d2107
+ 901737af8f9797bb.917fd862ff0c4316.0a2a3e8208245ca8.bba74d557130b401
+ b0c4362c1277ad80.cbb2c8a8de0e81eb.8407df788ca20587.a37a26c96d2b544d
+ c69f2c7d56993f96
+ after
+ 333a97448e0cafcb.2b8ec9c5c1c24e77.eefce205998a7484.2fc2337ace6560b3
+ 05d8d605c2772c38.2537d7e57f76f129.7615beaa6a20bfb6.b3d8a5b4c51d2107
+ 901737af8f9797bb.917fd862ff0c4316.0a2a3e8208245ca8.bba74d557130b401
+ b0c4362c1277ad80.cbb2c8a8de0e81eb.8407df788ca20587.a37a26c96d2b544d
+ c69f2c7d56993f96
+
+VDPPS_128_4of4(reg)
+ before
+ 82615bdbc706ae88.41ac4f6a67232ab5.2f1ba324b80be653.c1781b7814a7777e
+ 320bb0515dfee0d1.1f99ff54a8a8c983.1a086540278caffb.9d49706ebc3e6eba
+ 31ea254ab30e0f1b.2657c0d5f4114819.e6c30b6aca1f188f.f44559479f73a567
+ dd4ab83165c27812.32b410db656a61a1.f099900d3b4f5dba.a23953edda53d9b0
+ 83f1d84e88e8c6c1
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 320bb0515dfee0d1.1f99ff54a8a8c983.1a086540278caffb.9d49706ebc3e6eba
+ 31ea254ab30e0f1b.2657c0d5f4114819.e6c30b6aca1f188f.f44559479f73a567
+ dd4ab83165c27812.32b410db656a61a1.f099900d3b4f5dba.a23953edda53d9b0
+ 83f1d84e88e8c6c1
+VDPPS_128_4of4(mem)
+ before
+ 72396654c54127c8.9077657410a45763.1f7b6b5117c0d047.94d6f09516a8b929
+ 4ddd78edae67baef.a8bd267e5042e7ba.c9774b23271e5339.2ec6276ef8b76987
+ efa98b035f683962.7f67f8bbc02766c2.0c752e3eb090a4a0.1ab431047c07a981
+ 34681984f350604f.73c2d897fce00d28.c3418f8cce237fab.b4ee0bc33e24b5c3
+ 58beb017dc9bc8f8
+ after
+ 72396654c54127c8.9077657410a45763.1f7b6b5117c0d047.94d6f09516a8b929
+ 4ddd78edae67baef.a8bd267e5042e7ba.c9774b23271e5339.2ec6276ef8b76987
+ efa98b035f683962.7f67f8bbc02766c2.0c752e3eb090a4a0.1ab431047c07a981
+ 34681984f350604f.73c2d897fce00d28.c3418f8cce237fab.b4ee0bc33e24b5c3
+ 58beb017dc9bc8f8
+
+VDPPS_256_1of4(reg)
+ before
+ 62711c6ceff71fcd.f8e7a05b8629eddf.de1bc17fa1f81b97.cca7eafa9fe2a284
+ 2d534b2f15c5f5ed.16f39b7435019a41.1dbcb0dd4afbcabd.0273bb753cd9c757
+ 17b03acaea908805.6c5686bb1be4239f.8df29f1e94765743.41707ee7c315ab51
+ 7bd4e4ab09e412c0.d5dcdd1c55dd4625.88088caf1af4fed7.646cb03e50a10a9e
+ 4931cc65fe899f69
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 2d534b2f15c5f5ed.16f39b7435019a41.1dbcb0dd4afbcabd.0273bb753cd9c757
+ 17b03acaea908805.6c5686bb1be4239f.8df29f1e94765743.41707ee7c315ab51
+ 7bd4e4ab09e412c0.d5dcdd1c55dd4625.88088caf1af4fed7.646cb03e50a10a9e
+ 4931cc65fe899f69
+VDPPS_256_1of4(mem)
+ before
+ cb8c4e47e9da27df.b50a453c0e4dd0cc.2d531d84fef8bd00.6b4c72fb7901fb25
+ c549b3d22e9f5e2c.21a059eb9658fdd2.4f86c1dd3341455c.93094d6d4c2a89d9
+ 153475f1e9e4007b.1ae01c233d90d681.194045150fc59a64.5a8a197330fae59e
+ 9519129034b6c8f8.fe178b509e829783.654e2516af8f7745.1d1cd378c0fd4a20
+ 380b75e899c0f60d
+ after
+ cb8c4e47e9da27df.b50a453c0e4dd0cc.2d531d84fef8bd00.6b4c72fb7901fb25
+ c549b3d22e9f5e2c.21a059eb9658fdd2.4f86c1dd3341455c.93094d6d4c2a89d9
+ 153475f1e9e4007b.1ae01c233d90d681.194045150fc59a64.5a8a197330fae59e
+ 9519129034b6c8f8.fe178b509e829783.654e2516af8f7745.1d1cd378c0fd4a20
+ 380b75e899c0f60d
+
+VDPPS_256_1of4(reg)
+ before
+ 07a3fd2f56ce230e.23c3059c2e2073d1.2891a1de55b97c84.117cddce2eab9a2b
+ e62f67b993b30dd2.99ffcbfff12fbd30.f39a5a39ffc1c131.f796ea28a826bc41
+ 31fdadf3edfcf203.d59adea699ed6141.bd7db2cd3727a136.f568c70f3a0b9cb3
+ 4457cd4700340c4d.b15ebc7e43681c31.e088a6079a76593e.e5bef0710067f4af
+ a563e1391544815e
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ e62f67b993b30dd2.99ffcbfff12fbd30.f39a5a39ffc1c131.f796ea28a826bc41
+ 31fdadf3edfcf203.d59adea699ed6141.bd7db2cd3727a136.f568c70f3a0b9cb3
+ 4457cd4700340c4d.b15ebc7e43681c31.e088a6079a76593e.e5bef0710067f4af
+ a563e1391544815e
+VDPPS_256_1of4(mem)
+ before
+ 0f24175395b1ffef.7b8ac12367e8985e.0b17e0710aacaa2c.ba053151c33a24f6
+ 00cd0dac9db7298c.32e288f1bea3d2df.bd93c66d0bc4c75d.a5414f194fff3f0a
+ 552a3e2e4964bd62.c5ab1b1fa2f1f57f.a49dea5d61bc2ef1.ff88fcc9d952e625
+ e80729c6b3c3759c.90317718af5e3ee8.9d00c92d28a09c13.222634cffebf55f3
+ 6b67f49659d0c822
+ after
+ 0f24175395b1ffef.7b8ac12367e8985e.0b17e0710aacaa2c.ba053151c33a24f6
+ 00cd0dac9db7298c.32e288f1bea3d2df.bd93c66d0bc4c75d.a5414f194fff3f0a
+ 552a3e2e4964bd62.c5ab1b1fa2f1f57f.a49dea5d61bc2ef1.ff88fcc9d952e625
+ e80729c6b3c3759c.90317718af5e3ee8.9d00c92d28a09c13.222634cffebf55f3
+ 6b67f49659d0c822
+
+VDPPS_256_1of4(reg)
+ before
+ 3796378a86137a5b.96304761fae10d67.efc099477f77e9c6.8289dec97d7dcdf0
+ e000f9172214a84d.3b7016ea38c842ee.3ea37c1ab1c731c6.3004a51d7c5e7cb4
+ c3f236a9c95d8da2.b395114c8987d15e.d9271cfcdedb5494.833d9a154050678a
+ 3db6ebac167c6707.db69b4750a2773e3.1c98765aa53d8cdc.5700399de65e489f
+ 8819ffa18994db1f
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ e000f9172214a84d.3b7016ea38c842ee.3ea37c1ab1c731c6.3004a51d7c5e7cb4
+ c3f236a9c95d8da2.b395114c8987d15e.d9271cfcdedb5494.833d9a154050678a
+ 3db6ebac167c6707.db69b4750a2773e3.1c98765aa53d8cdc.5700399de65e489f
+ 8819ffa18994db1f
+VDPPS_256_1of4(mem)
+ before
+ f353670e45ffde35.a898128ca5fd7027.8db97b50d6b6e7a8.6242849e9f7c1548
+ 727bedce37aa0b0d.61e6a9b6136ae4af.a651e2c90a3fe7da.097144356b212d87
+ e25e0dcf7aa11ed4.c4ebab94fc51014a.02fd66ccc1cf30a4.6c71b18ca2ba0e43
+ 1fc644fc2bf0d5b6.2df21594fa3e01a5.7d88824517717e33.e68dc70de2d2f529
+ d5138326c7f61de4
+ after
+ f353670e45ffde35.a898128ca5fd7027.8db97b50d6b6e7a8.6242849e9f7c1548
+ 727bedce37aa0b0d.61e6a9b6136ae4af.a651e2c90a3fe7da.097144356b212d87
+ e25e0dcf7aa11ed4.c4ebab94fc51014a.02fd66ccc1cf30a4.6c71b18ca2ba0e43
+ 1fc644fc2bf0d5b6.2df21594fa3e01a5.7d88824517717e33.e68dc70de2d2f529
+ d5138326c7f61de4
+
+VDPPS_256_2of4(reg)
+ before
+ 944de041ecb1c421.057f0d4065a4eadf.f948e120acbc216c.f3bfb22029318cb3
+ 7e88d9ccee8f238c.7057e48945c91a79.82390da6ac579d4a.406f734a131c174f
+ f1106d32681c79d0.3b1945c2e76921b3.25119491969bb0ec.40623fadf03ddb34
+ 473095dff6e50199.4490acd76592bab7.3e1c724d071597fd.cf659437dca0938d
+ c844edd2f452fd87
+ after
+ ff80000000000000.ff80000000000000.c3e785ba00000000.c3e785ba00000000
+ 7e88d9ccee8f238c.7057e48945c91a79.82390da6ac579d4a.406f734a131c174f
+ f1106d32681c79d0.3b1945c2e76921b3.25119491969bb0ec.40623fadf03ddb34
+ 473095dff6e50199.4490acd76592bab7.3e1c724d071597fd.cf659437dca0938d
+ c844edd2f452fd87
+VDPPS_256_2of4(mem)
+ before
+ 09cac66c545ed24e.de364f3f3576f695.668996b5dd50a2b2.29a6a4469a508e2a
+ 6dc59cf017d0d10d.106c95bec059956d.7dd07e466bad95cf.42fa25e8ebd8d01f
+ d0ffea4a59b5b5f0.3a1f65c9341c19d0.6531e0772ab74f3b.e466f09f983a9a87
+ 0e452c6637183925.b99cbbca2d4bc068.fa783835377a8b22.6d3404d83a01280f
+ 38b15afd6fbab662
+ after
+ 09cac66c545ed24e.de364f3f3576f695.668996b5dd50a2b2.29a6a4469a508e2a
+ 6dc59cf017d0d10d.106c95bec059956d.7dd07e466bad95cf.42fa25e8ebd8d01f
+ d0ffea4a59b5b5f0.3a1f65c9341c19d0.6531e0772ab74f3b.e466f09f983a9a87
+ 0e452c6637183925.b99cbbca2d4bc068.fa783835377a8b22.6d3404d83a01280f
+ 38b15afd6fbab662
+
+VDPPS_256_2of4(reg)
+ before
+ a128f07bd3f07f2d.0263de30cc0519d6.e72c912e4570c4e2.1770036aad0006af
+ 04e7c0bf012fc11b.8a257c943589132f.211ee5621b1961e9.9ae7bc04a8577b0f
+ bd39c8349503b5da.8157837e8dafe15d.c4bdb2d048d2d52a.5ea7dfee458ba86d
+ 276904462cf99a13.c2c46ddbf183408c.2a54f4e66b255a50.3e7de813a0a647f6
+ 18355361d4b615d5
+ after
+ 83bc599200000000.83bc599200000000.ae6b1b1b00000000.ae6b1b1b00000000
+ 04e7c0bf012fc11b.8a257c943589132f.211ee5621b1961e9.9ae7bc04a8577b0f
+ bd39c8349503b5da.8157837e8dafe15d.c4bdb2d048d2d52a.5ea7dfee458ba86d
+ 276904462cf99a13.c2c46ddbf183408c.2a54f4e66b255a50.3e7de813a0a647f6
+ 18355361d4b615d5
+VDPPS_256_2of4(mem)
+ before
+ c69b9dc3fdc7cd38.a0c46e60629caa75.2b3ab8957c12ece7.b031a70f1da02d08
+ 267b412638e42d48.839604f0d17922aa.9683e09a4b67a09b.b29ec8b7fccf89fe
+ 12a0bb74a019ef33.2b2bc161181b3e5e.e16c5fd4798e1ad4.8de8514aa43cacdd
+ 68d7879a5272cf25.f6cfa120d10e393e.e6c1b331229413bd.9b5a4034b075d052
+ 394291e1bd063208
+ after
+ c69b9dc3fdc7cd38.a0c46e60629caa75.2b3ab8957c12ece7.b031a70f1da02d08
+ 267b412638e42d48.839604f0d17922aa.9683e09a4b67a09b.b29ec8b7fccf89fe
+ 12a0bb74a019ef33.2b2bc161181b3e5e.e16c5fd4798e1ad4.8de8514aa43cacdd
+ 68d7879a5272cf25.f6cfa120d10e393e.e6c1b331229413bd.9b5a4034b075d052
+ 394291e1bd063208
+
+VDPPS_256_2of4(reg)
+ before
+ c3eb3ebe667a0dac.02ed21846afc8b4a.3ecea09798df50f6.834d579c64844a83
+ 95a04535475d9eea.beac061f02c2ddcd.6173ba330a18bf31.92dec701586b7951
+ 0baea1b3fd3b216d.76e0b15539d182db.ba0bec61c248c29c.f13f7f4c1c545d54
+ 81614ea524a1d2e2.07579e142833359f.a4e2318b5df894e3.7a3bfc69cb4bb2b7
+ 0a9fb844825c33a7
+ after
+ ff80000000000000.ff80000000000000.3543564f00000000.3543564f00000000
+ 95a04535475d9eea.beac061f02c2ddcd.6173ba330a18bf31.92dec701586b7951
+ 0baea1b3fd3b216d.76e0b15539d182db.ba0bec61c248c29c.f13f7f4c1c545d54
+ 81614ea524a1d2e2.07579e142833359f.a4e2318b5df894e3.7a3bfc69cb4bb2b7
+ 0a9fb844825c33a7
+VDPPS_256_2of4(mem)
+ before
+ 7e3731ca5d949e50.53054876571aecf4.4edc4a47edf7b446.7c44851f76b672b1
+ b0cfe3e577feaddd.dde68b913232ac50.253a2fdaa426b9fb.9f7de587a90e98b2
+ 7d324883eca71c7b.7a4f146452764ea2.693ecbb968ce01eb.67d94b31948a4194
+ c12ede8ed99aa855.888ede5a52710e95.f7b499d056fa4742.32a3b588d0b8aa00
+ 5a291ef8fb240fa5
+ after
+ 7e3731ca5d949e50.53054876571aecf4.4edc4a47edf7b446.7c44851f76b672b1
+ b0cfe3e577feaddd.dde68b913232ac50.253a2fdaa426b9fb.9f7de587a90e98b2
+ 7d324883eca71c7b.7a4f146452764ea2.693ecbb968ce01eb.67d94b31948a4194
+ c12ede8ed99aa855.888ede5a52710e95.f7b499d056fa4742.32a3b588d0b8aa00
+ 5a291ef8fb240fa5
+
+VDPPS_256_3of4(reg)
+ before
+ 3cb583edb158ac2d.588d1ff459e30e98.62ede5dfcfb027d6.a968150b89b7482b
+ 3594ded38de2bc45.1f1c8aa0898e0770.64b9265f64bed610.5c26bc561d0fc0d3
+ 9f122d172b4e7c98.f0a7987d84a85208.ea3e9b47ae2757f0.ecba089e2f116b65
+ d77a6b23282628d3.a8fac679673ca98d.4fc842014878e521.35ef77cddbc6040e
+ 139284d03c3c48fa
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 3594ded38de2bc45.1f1c8aa0898e0770.64b9265f64bed610.5c26bc561d0fc0d3
+ 9f122d172b4e7c98.f0a7987d84a85208.ea3e9b47ae2757f0.ecba089e2f116b65
+ d77a6b23282628d3.a8fac679673ca98d.4fc842014878e521.35ef77cddbc6040e
+ 139284d03c3c48fa
+VDPPS_256_3of4(mem)
+ before
+ 6270ac946e7ef354.391a94651ff8fca1.23e191804d57c92a.f1a316facf3bbd51
+ fe5369048e99c049.213ca447ad5033af.3d28747c52046e0c.2b1a139fdeff1b29
+ c307390cb7986d04.eb2e98376eb80aa9.d29aeb5a944f535f.587a365a114d3a58
+ 8d5a97970687b4b2.f33a6b9ffcbfbc3a.be0473062c45354e.d6107a9905b35888
+ ff26dbc756bcaf65
+ after
+ 6270ac946e7ef354.391a94651ff8fca1.23e191804d57c92a.f1a316facf3bbd51
+ fe5369048e99c049.213ca447ad5033af.3d28747c52046e0c.2b1a139fdeff1b29
+ c307390cb7986d04.eb2e98376eb80aa9.d29aeb5a944f535f.587a365a114d3a58
+ 8d5a97970687b4b2.f33a6b9ffcbfbc3a.be0473062c45354e.d6107a9905b35888
+ ff26dbc756bcaf65
+
+VDPPS_256_3of4(reg)
+ before
+ 310855509ff57b9c.3817ff939673517f.95ad19edf6ee870f.dd32866d38f1d006
+ c604e4a07ce9fad9.a009eeec84670296.2dd29e8cf5d3a5d3.0bf0a279d45fdfb2
+ 1c6585238a2466c7.a1fdde8ceb6f8124.17f7f7e898f95233.230a42181b9c207f
+ 8d7632456533fc13.17bf4d60e8988a54.af661e6d78ecccdb.034ce23529b34c99
+ 8681ffbb1bb0222b
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ c604e4a07ce9fad9.a009eeec84670296.2dd29e8cf5d3a5d3.0bf0a279d45fdfb2
+ 1c6585238a2466c7.a1fdde8ceb6f8124.17f7f7e898f95233.230a42181b9c207f
+ 8d7632456533fc13.17bf4d60e8988a54.af661e6d78ecccdb.034ce23529b34c99
+ 8681ffbb1bb0222b
+VDPPS_256_3of4(mem)
+ before
+ 887613980ca05d62.7784ea72a8a1f768.dd1bb65496eddb53.516d118833394d76
+ e5f89cb7198eb869.34dba617effa9573.d1dd9655117a2e4d.5956cba3656b12b0
+ 78d116045d86ef6d.21c7639ed7cb10e0.ced0674d774c406d.236e492ba90f5737
+ 1fcdfb6cf595c099.9b941e75fb9fa55a.b0c2a72ae16ecddf.0b01858d9caf57b5
+ 6d5a7d33d9da4fd6
+ after
+ 887613980ca05d62.7784ea72a8a1f768.dd1bb65496eddb53.516d118833394d76
+ e5f89cb7198eb869.34dba617effa9573.d1dd9655117a2e4d.5956cba3656b12b0
+ 78d116045d86ef6d.21c7639ed7cb10e0.ced0674d774c406d.236e492ba90f5737
+ 1fcdfb6cf595c099.9b941e75fb9fa55a.b0c2a72ae16ecddf.0b01858d9caf57b5
+ 6d5a7d33d9da4fd6
+
+VDPPS_256_3of4(reg)
+ before
+ a4c72c8bfc197b47.b5bac8d9fcc6e51b.fc8ed206f8028f8e.527dd1d76dec90d1
+ 0e928e00a2fa17b4.1563fa388f251b1c.a1007bbf69810b28.92ce614037d3466d
+ 0609a0fe67085ec9.1d930c76c9bf1ecb.e637150beba755d3.4a81d3505a2eabdf
+ e7765cf1e5d08d30.a7177b7dc79fa951.287f9d561900a93b.5862a4f6f20a7b54
+ 963d4f1b1c7171f8
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 0e928e00a2fa17b4.1563fa388f251b1c.a1007bbf69810b28.92ce614037d3466d
+ 0609a0fe67085ec9.1d930c76c9bf1ecb.e637150beba755d3.4a81d3505a2eabdf
+ e7765cf1e5d08d30.a7177b7dc79fa951.287f9d561900a93b.5862a4f6f20a7b54
+ 963d4f1b1c7171f8
+VDPPS_256_3of4(mem)
+ before
+ e2dd50acf3714af6.0f26c045bbdde098.91bbc13ba4d27add.c1240e0c9019420e
+ 160f23959416c27b.d964c76683bb92ab.b54b5c9b7d624a99.0e726499eb7d5df5
+ 10a045c31a6b94b3.a07e6ec0d9f6e016.f193c7896d5dd8b2.6bb59b69c6b8369f
+ aa5a3120a27c7dc9.c2beafbf5a1b0684.1f5f7ef090cfde53.3438afe8be5708b6
+ c5499d836fe511e6
+ after
+ e2dd50acf3714af6.0f26c045bbdde098.91bbc13ba4d27add.c1240e0c9019420e
+ 160f23959416c27b.d964c76683bb92ab.b54b5c9b7d624a99.0e726499eb7d5df5
+ 10a045c31a6b94b3.a07e6ec0d9f6e016.f193c7896d5dd8b2.6bb59b69c6b8369f
+ aa5a3120a27c7dc9.c2beafbf5a1b0684.1f5f7ef090cfde53.3438afe8be5708b6
+ c5499d836fe511e6
+
+VDPPS_256_4of4(reg)
+ before
+ 7a3260a474ef8add.c209629a475539e9.997288d0a1b640a2.1d7afdbf03c319a9
+ af40f4b969ffb244.327b571b26038441.83e4f45d4b51c91b.c5b1c0dfe24545df
+ c0bf552deba3c4ca.d77b89915a9119fa.da61efd4f37ade9d.f4d0443d48611d22
+ 09fb806b9567fb19.8ed476e7000cb543.fc3475a035bcbbd1.87a304c551245f9e
+ 58f67c641a99c57e
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ af40f4b969ffb244.327b571b26038441.83e4f45d4b51c91b.c5b1c0dfe24545df
+ c0bf552deba3c4ca.d77b89915a9119fa.da61efd4f37ade9d.f4d0443d48611d22
+ 09fb806b9567fb19.8ed476e7000cb543.fc3475a035bcbbd1.87a304c551245f9e
+ 58f67c641a99c57e
+VDPPS_256_4of4(mem)
+ before
+ 44952904becd0bef.e63f6fe104d693dd.31539809337f1446.43ab832dafa49b65
+ 274b85935acbee1d.b3d920fad47ccac3.9dc46de30ff6f130.0c1114e6fabdbb05
+ dee60efb099f2b33.cb138e229fe5da77.aef37161b17d0a2c.b4b12439b493575d
+ 43303f2ae8557b5d.8c3ab6c5049e00a4.40ac1e6f35211967.95d8af9279b3ab18
+ 0cd2b25be4a8f2e2
+ after
+ 44952904becd0bef.e63f6fe104d693dd.31539809337f1446.43ab832dafa49b65
+ 274b85935acbee1d.b3d920fad47ccac3.9dc46de30ff6f130.0c1114e6fabdbb05
+ dee60efb099f2b33.cb138e229fe5da77.aef37161b17d0a2c.b4b12439b493575d
+ 43303f2ae8557b5d.8c3ab6c5049e00a4.40ac1e6f35211967.95d8af9279b3ab18
+ 0cd2b25be4a8f2e2
+
+VDPPS_256_4of4(reg)
+ before
+ 76eb270191fe6969.33f6950b12fa9dc8.519a924f9c3278f7.30bbf2fab6edda0c
+ 2d6f0cf01d424c57.8a048a8aa49a4ba0.767f202d052e7d1c.58eb68ec50ee0b48
+ 8ea95d9523ffd658.24269c93b93f4211.56345bc9db1d4cbe.9509fc33202f6647
+ f5e7145a40c24419.dd2746126ef73e46.4f074091b98b218a.c3e22ab942bca734
+ be406f6cd1a28c3c
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ 2d6f0cf01d424c57.8a048a8aa49a4ba0.767f202d052e7d1c.58eb68ec50ee0b48
+ 8ea95d9523ffd658.24269c93b93f4211.56345bc9db1d4cbe.9509fc33202f6647
+ f5e7145a40c24419.dd2746126ef73e46.4f074091b98b218a.c3e22ab942bca734
+ be406f6cd1a28c3c
+VDPPS_256_4of4(mem)
+ before
+ 62ef4537e9eccf8a.be732fad1015d246.91d504f3decdfa6b.bc42c9ef3c05382b
+ 8bbd2a06a7a62d4b.459aa8f92d86bc8a.1cfa522325ce33ad.f832f451ff15cc4e
+ 15759ac526dd62aa.e6a87daa36a13d92.5a63ad8c6005a538.6123bc229e4a1a9e
+ dbe20f60839c29d5.fde9aa2cc4f19209.27dc901cab7e0b37.51611dceb62d5ec9
+ 263813c1e34cd378
+ after
+ 62ef4537e9eccf8a.be732fad1015d246.91d504f3decdfa6b.bc42c9ef3c05382b
+ 8bbd2a06a7a62d4b.459aa8f92d86bc8a.1cfa522325ce33ad.f832f451ff15cc4e
+ 15759ac526dd62aa.e6a87daa36a13d92.5a63ad8c6005a538.6123bc229e4a1a9e
+ dbe20f60839c29d5.fde9aa2cc4f19209.27dc901cab7e0b37.51611dceb62d5ec9
+ 263813c1e34cd378
+
+VDPPS_256_4of4(reg)
+ before
+ 3af39b67c033b65a.bbd107c3d9ef3ff5.e6a829eb7602f79c.5f3177bd214623d7
+ ebe0b02ce96c4318.900efdda44e36039.fd33f853e560a8f7.dd2dde5dde68a644
+ 93494e7cfb85b661.36656d91e28348cb.9ed412d0af98e0c5.7f9e42e7fff053a9
+ 8f7b71c491094adf.89a2d3d5ccdbb2d7.25d873ce7035dcb2.204e1d479febe533
+ 9c0aed69db64170d
+ after
+ 0000000000000000.0000000000000000.0000000000000000.0000000000000000
+ ebe0b02ce96c4318.900efdda44e36039.fd33f853e560a8f7.dd2dde5dde68a644
+ 93494e7cfb85b661.36656d91e28348cb.9ed412d0af98e0c5.7f9e42e7fff053a9
+ 8f7b71c491094adf.89a2d3d5ccdbb2d7.25d873ce7035dcb2.204e1d479febe533
+ 9c0aed69db64170d
+VDPPS_256_4of4(mem)
+ before
+ ce9e2d39cf67a564.3cc2156e48853c3f.6490ac9020f85b8a.ee8b17bac3c4d86c
+ 94d65aa395014d64.f46a37e8bc84c82c.a5fd72b0fae5fe10.5539fbfe45cf0f9d
+ c97eee934c3dc938.14bed29c87922953.27b3a32075ae5994.b52e1a0891e5bef1
+ 486167f60d27d60d.f90ce2f8483c9c5f.c57fbaccad602643.6cb57042438f2115
+ d51cf91af85b73b5
+ after
+ ce9e2d39cf67a564.3cc2156e48853c3f.6490ac9020f85b8a.ee8b17bac3c4d86c
+ 94d65aa395014d64.f46a37e8bc84c82c.a5fd72b0fae5fe10.5539fbfe45cf0f9d
+ c97eee934c3dc938.14bed29c87922953.27b3a32075ae5994.b52e1a0891e5bef1
+ 486167f60d27d60d.f90ce2f8483c9c5f.c57fbaccad602643.6cb57042438f2115
+ d51cf91af85b73b5
+
+VHADDPS_128(reg)
+ before
+ 4cadb1fb4bd4f27d.ef4d40b6f6cc300e.fd9e6367980d5dfd.5d2d34a0bf062249
+ 2cb59551d987d817.980cf5c123379268.7dc152551591a8d9.ca898b88c7ac08d1
+ d380a0883eff6132.216b0302af75ba46.d5c1aa2e5b55b89e.e75f3d70df5f9608
+ 9c5ace0c15c8cb78.6436e464b79061d5.61ea675e05e4caf9.927ac544262a8619
+ a5a7a0f0b6199431
+ after
+ 0000000000000000.0000000000000000.5b55a069e75f3e50.7dc15255ca8c3bab
+ 2cb59551d987d817.980cf5c123379268.7dc152551591a8d9.ca898b88c7ac08d1
+ d380a0883eff6132.216b0302af75ba46.d5c1aa2e5b55b89e.e75f3d70df5f9608
+ 9c5ace0c15c8cb78.6436e464b79061d5.61ea675e05e4caf9.927ac544262a8619
+ a5a7a0f0b6199431
+VHADDPS_128(mem)
+ before
+ fdb34861ab397e7b.e28e1b49fa6e5096.3f3916d556974641.7d888551b0cb1a95
+ 77683b812295fe24.036a84ac8a7e2d37.8c3f1440a89323b5.85e60073f794e41f
+ ed92f43e363ad158.5938039f60849d08.29165b91ca92b55e.d552d53176cd6343
+ 3dffef820433b242.42459690190adeb4.f08865b4d89fb868.c916fff5ca02d4ac
+ bd7f7a2d8fbe7207
+ after
+ fdb34861ab397e7b.e28e1b49fa6e5096.3f3916d556974641.7d888551b0cb1a95
+ 77683b812295fe24.036a84ac8a7e2d37.8c3f1440a89323b5.85e60073f794e41f
+ 0000000000000000.0000000000000000.569746417d888551.a89323b5f794e41f
+ 3dffef820433b242.42459690190adeb4.f08865b4d89fb868.c916fff5ca02d4ac
+ bd7f7a2d8fbe7207
+
+VHADDPS_128(reg)
+ before
+ 0dd942435f8d7bff.417aa83ba78c5f0f.18dd39e9509e2ae9.be62b095edc6e7fe
+ 156f54a5d9fb2941.d6ce9c543b5192eb.384ce618a1cbbd50.7070b7212514004c
+ 318faabe9795b979.d8c846b9de8f0801.ffdd9b88a91ed597.e07ef6429d94bd80
+ bd8342fa35e66652.24342256a9517c7d.c7de53a50422ac6a.eb57eae67053dac3
+ 6dc90df7bb5c1444
+ after
+ 0000000000000000.0000000000000000.ffdd9b88e07ef642.384ce6187070b721
+ 156f54a5d9fb2941.d6ce9c543b5192eb.384ce618a1cbbd50.7070b7212514004c
+ 318faabe9795b979.d8c846b9de8f0801.ffdd9b88a91ed597.e07ef6429d94bd80
+ bd8342fa35e66652.24342256a9517c7d.c7de53a50422ac6a.eb57eae67053dac3
+ 6dc90df7bb5c1444
+VHADDPS_128(mem)
+ before
+ 439edd6399bb282d.159918c5507b6d79.94deac17baa4ab8c.ee990adb4d637f75
+ 47a3d515277dcfaa.941b268b83df0a99.059260e82d93515a.ce5bbc96216e8963
+ 56a472f980adc8e9.98566ab86b9e795f.531cbbb61d2a2a13.c47065421bce08e0
+ 4c6d2efbc157cd13.7c96deb9a344f576.5a47386ba676f1e2.2c24024bd70f369a
+ 63c38e1ef2be503a
+ after
+ 439edd6399bb282d.159918c5507b6d79.94deac17baa4ab8c.ee990adb4d637f75
+ 47a3d515277dcfaa.941b268b83df0a99.059260e82d93515a.ce5bbc96216e8963
+ 0000000000000000.0000000000000000.baa4ab8cee990adb.2d93515ace5bbc96
+ 4c6d2efbc157cd13.7c96deb9a344f576.5a47386ba676f1e2.2c24024bd70f369a
+ 63c38e1ef2be503a
+
+VHADDPS_128(reg)
+ before
+ c39905250766916f.05ca870705879b57.9c2680f8c85ebc8c.f6e053f5e58163f3
+ a9f164ceb39436e3.5d87f809694aeedf.53544ce37577074a.03b4893ef55a3c73
+ 7118a58392d27b43.306ffded08ac81d7.ff6a3ce4461c155f.5d8d5434f30a378e
+ 775ac6b23eae9c3a.5a4f129ffeb7116d.fab54e69d8d82074.e03732c2fb9f1270
+ 68809ed427258744
+ after
+ 0000000000000000.0000000000000000.ff6a3ce4f30a378e.7577074af55a3c73
+ a9f164ceb39436e3.5d87f809694aeedf.53544ce37577074a.03b4893ef55a3c73
+ 7118a58392d27b43.306ffded08ac81d7.ff6a3ce4461c155f.5d8d5434f30a378e
+ 775ac6b23eae9c3a.5a4f129ffeb7116d.fab54e69d8d82074.e03732c2fb9f1270
+ 68809ed427258744
+VHADDPS_128(mem)
+ before
+ d133145696a65236.1703c2c656b4d475.b7f3b40c68795aca.a2817dddc7376538
+ f71b103461303173.ad5f952b736e609f.23275e1e62fd171d.521ac5acaec62055
+ b6050f5aa6cede27.95ba3c4d336b7c65.7ab78cc307500690.65cc224229108c78
+ eabd8cb4818d157d.2b5fb19832346372.976fbae6737de04f.39e2910bd5a1e74c
+ 28aa0d734e066a7e
+ after
+ d133145696a65236.1703c2c656b4d475.b7f3b40c68795aca.a2817dddc7376538
+ f71b103461303173.ad5f952b736e609f.23275e1e62fd171d.521ac5acaec62055
+ 0000000000000000.0000000000000000.68795acac7376538.62fd171d521ac5ac
+ eabd8cb4818d157d.2b5fb19832346372.976fbae6737de04f.39e2910bd5a1e74c
+ 28aa0d734e066a7e
+
+VHADDPS_256(reg)
+ before
+ 8f6e92e62fc954b9.6e0f032f0d7894a2.cb9bf2780b575374.581a6573c3906487
+ cb7b1cd01479dfaa.20c7f0b5679c15c2.d1bafa5a5b5f8614.9886075513964d64
+ 361da79e9a9f48fd.dbb0d034aa035508.9908c6a8bdd83801.337d1e7a7d9a5611
+ 2da030ba5cc9cb5d.7b981e96f2bb10a1.7ed150cfce4fa7e5.04cc25ce20a83bbb
+ e93f993b16cdba8e
+ after
+ 361da79edbb0d034.cb7b1cd0679c15c2.bdd838017d9a5611.5b5f85fd9885e1c2
+ cb7b1cd01479dfaa.20c7f0b5679c15c2.d1bafa5a5b5f8614.9886075513964d64
+ 361da79e9a9f48fd.dbb0d034aa035508.9908c6a8bdd83801.337d1e7a7d9a5611
+ 2da030ba5cc9cb5d.7b981e96f2bb10a1.7ed150cfce4fa7e5.04cc25ce20a83bbb
+ e93f993b16cdba8e
+VHADDPS_256(mem)
+ before
+ bda1f4ae7b148db5.0d4fb292f783a377.db4956c95cd001b8.de61963c294f0d6c
+ 5bc0b4136b8a715d.3078299106570ef7.d990f4b8044ce57a.1404935a6a65a743
+ a1665457043922b1.f365912326d44688.5039744f053d7813.7c0543952e1cb016
+ 696050645f2f5bde.b263e7b3f28387d6.1b10537a7baf76ae.71b1a35810006590
+ 5154ad11ad9e025e
+ after
+ bda1f4ae7b148db5.0d4fb292f783a377.db4956c95cd001b8.de61963c294f0d6c
+ 5bc0b4136b8a715d.3078299106570ef7.d990f4b8044ce57a.1404935a6a65a743
+ 7b148db5f783a377.6b8a715d30782991.5cb6d6dfde61963c.d990f4b86a65a743
+ 696050645f2f5bde.b263e7b3f28387d6.1b10537a7baf76ae.71b1a35810006590
+ 5154ad11ad9e025e
+
+VHADDPS_256(reg)
+ before
+ 773a5f2ba180c32c.917a25289a78da0f.c9be26af06f20f8e.18e10c2583ad9a77
+ 3eafb4138635e3a5.f3804d8ed11f5871.95c24a83ffac185c.21771b3c3943a19c
+ 04fea933fb46a076.6d3e46821f309430.70ba4f99793ddeec.149ffcabb77d4747
+ 237538f89a41334a.d9808bf0a1b74877.b7f4315e0f329fe9.cb262c5f1c6847a4
+ 23d62542810f5ee0
+ after
+ fb46a0766d3e4682.3eafb413f3804d8e.793ddf49b77d4747.ffec185c3943a19c
+ 3eafb4138635e3a5.f3804d8ed11f5871.95c24a83ffac185c.21771b3c3943a19c
+ 04fea933fb46a076.6d3e46821f309430.70ba4f99793ddeec.149ffcabb77d4747
+ 237538f89a41334a.d9808bf0a1b74877.b7f4315e0f329fe9.cb262c5f1c6847a4
+ 23d62542810f5ee0
+VHADDPS_256(mem)
+ before
+ f97c6542057e4827.f95e5fcfffb1dbce.151199c472c13173.c6baed3e5e1695ff
+ 27e36749c1c2c1a4.e0061922c623d2ad.fbbeeaeaae590b50.f95a7ea60175fddb
+ 8ad9a845d3e68484.36b9625f8d225594.6854fc4e728c9139.ac1ee00194dc1329
+ ff28a22157f74ef2.55c337f0ed3aa02f.399c4adcd964815a.3b520fbab4d61295
+ 0244083ffcf037ca
+ after
+ f97c6542057e4827.f95e5fcfffb1dbce.151199c472c13173.c6baed3e5e1695ff
+ 27e36749c1c2c1a4.e0061922c623d2ad.fbbeeaeaae590b50.f95a7ea60175fddb
+ f97c6542fff1dbce.c1c2c1a4e0061922.72c131735e1695ff.fbbeeaeaf95a7ea6
+ ff28a22157f74ef2.55c337f0ed3aa02f.399c4adcd964815a.3b520fbab4d61295
+ 0244083ffcf037ca
+
+VHADDPS_256(reg)
+ before
+ 5c3fc6fb09b5be74.609dd3c96800db1b.9b70924384f8ef29.4865508100f095e1
+ a78e455a76b1e240.8a04b629230de62b.620b71c3eee77d2f.727a8b27033989f8
+ 3e7e81c8e070e1da.5929c72da32b2d4d.07e1cfdcc69387ed.93a675bcfc4d1acb
+ 7d5c76b1e27ff5ed.aad883c104646aae.e73fa8faa989480e.88b78c2b0a370587
+ 2b774b5f46040358
+ after
+ e070e1da5929c72d.76b1e240230de62b.c69387edfc4d1acb.eee77d2f727a8b27
+ a78e455a76b1e240.8a04b629230de62b.620b71c3eee77d2f.727a8b27033989f8
+ 3e7e81c8e070e1da.5929c72da32b2d4d.07e1cfdcc69387ed.93a675bcfc4d1acb
+ 7d5c76b1e27ff5ed.aad883c104646aae.e73fa8faa989480e.88b78c2b0a370587
+ 2b774b5f46040358
+VHADDPS_256(mem)
+ before
+ 59b32e46cfbfd369.c071218119695a26.57dd65d263c75979.5c6ff9893154fd3e
+ ee37b2cbbe742fe7.620c7da420bb4e31.3d03e84adc5db8db.c3bebdf6fd80e32b
+ c6cf52da312fd4fd.c178868794000bb9.38188b178a344100.7877f0aba79a337e
+ bd468a5f44fd7ed8.3800389410c4ce6b.24e6c7238957b013.d8e88e16cb2d2ce6
+ 3d5b93a106c5080d
+ after
+ 59b32e46cfbfd369.c071218119695a26.57dd65d263c75979.5c6ff9893154fd3e
+ ee37b2cbbe742fe7.620c7da420bb4e31.3d03e84adc5db8db.c3bebdf6fd80e32b
+ 59b32e3ac0712181.ee37b2cb620c7da4.63c7597a5c6ff989.dc5db8dbfd80e32b
+ bd468a5f44fd7ed8.3800389410c4ce6b.24e6c7238957b013.d8e88e16cb2d2ce6
+ 3d5b93a106c5080d
+
+VHADDPD_128(reg)
+ before
+ 041dfcbaf3ef049f.af6ad64712eae8a4.22f28f393193d2f2.dd3a195cf6d3c341
+ 897bc4cb2f365c4a.7805b27cb800cf8c.dd9888e192fa54fb.3fdffeadecb334b5
+ 28bee74255274bb7.f4e49beb514defbd.c33f1ef7cf859031.26a3f1028803c09c
+ 3d35618a024c0e95.ffd30c81f9dd0362.32334de985bec241.6e516e47e5d02322
+ f3b4f26820251872
+ after
+ 0000000000000000.0000000000000000.c33f1ef7cf859031.dd9888e192fa54fb
+ 897bc4cb2f365c4a.7805b27cb800cf8c.dd9888e192fa54fb.3fdffeadecb334b5
+ 28bee74255274bb7.f4e49beb514defbd.c33f1ef7cf859031.26a3f1028803c09c
+ 3d35618a024c0e95.ffd30c81f9dd0362.32334de985bec241.6e516e47e5d02322
+ f3b4f26820251872
+VHADDPD_128(mem)
+ before
+ 9099f851540e5cb9.242b2e0fd133e18e.759e8129cdbac9a8.84bf1122503326d7
+ 23ccfbee9e98ab22.39eb4b3d5f68ff4e.311076cee9f2faba.1731670ecb6ff79e
+ 8719792c19cec0da.d8c3b3814776a583.11f7675e679155c6.45d34a1a92ff7243
+ 984ceef5e2bc590d.5dfd624526e90fd6.f01dd1c466a195f5.6cf3b6b0426ed272
+ e6dba73d764855d6
+ after
+ 9099f851540e5cb9.242b2e0fd133e18e.759e8129cdbac9a8.84bf1122503326d7
+ 23ccfbee9e98ab22.39eb4b3d5f68ff4e.311076cee9f2faba.1731670ecb6ff79e
+ 0000000000000000.0000000000000000.759e8129cdbac9a8.311076cee9f2faba
+ 984ceef5e2bc590d.5dfd624526e90fd6.f01dd1c466a195f5.6cf3b6b0426ed272
+ e6dba73d764855d6
+
+VHADDPD_128(reg)
+ before
+ 10d81a2ecb1a351c.3130d437146f30e6.23e654f6974d79f6.aa4f2fec00307576
+ 473509eddc6faeef.3093a9dccbf20192.88ca8601362f1e8d.1a59fdc2514ab173
+ e54072e846d3fefc.703fe8d224518a3c.e7f4f3d0a01a3c47.1e07b83276f90718
+ 4743508aa4d35fee.cc010d043b998511.9cb297d1719b0cd1.9125da298a4b3192
+ 4e7ee191aa4cec0d
+ after
+ 0000000000000000.0000000000000000.e7f4f3d0a01a3c47.1a59fdc2514ab173
+ 473509eddc6faeef.3093a9dccbf20192.88ca8601362f1e8d.1a59fdc2514ab173
+ e54072e846d3fefc.703fe8d224518a3c.e7f4f3d0a01a3c47.1e07b83276f90718
+ 4743508aa4d35fee.cc010d043b998511.9cb297d1719b0cd1.9125da298a4b3192
+ 4e7ee191aa4cec0d
+VHADDPD_128(mem)
+ before
+ 33e04857f106f4b4.c98ca03e93fa0e72.22a5955e2bd5af3c.034e6e6f443dcdd7
+ 1b158b687b8804b4.c8655c72aed44634.4df7facc1011c3ea.77157416b58cb904
+ e1ea27af66dbda39.9e1b829192ee45df.28c3ba3a075a7f47.5653a63261140d05
+ 632b9617cb0d2f6e.a8fa0d07dad34520.91d450942bbb9d7e.fb54ff2fe4620586
+ c1647b79d802dc32
+ after
+ 33e04857f106f4b4.c98ca03e93fa0e72.22a5955e2bd5af3c.034e6e6f443dcdd7
+ 1b158b687b8804b4.c8655c72aed44634.4df7facc1011c3ea.77157416b58cb904
+ 0000000000000000.0000000000000000.22a5955e2bd5af3c.77157416b58cb904
+ 632b9617cb0d2f6e.a8fa0d07dad34520.91d450942bbb9d7e.fb54ff2fe4620586
+ c1647b79d802dc32
+
+VHADDPD_128(reg)
+ before
+ 06cf167cdc7ecfb6.7ba4568ec829c27f.424df941220f83a2.62f738c69941d9bc
+ 24e0cda489641abd.0620e2ff793b4d9a.c86243a9082f3a12.79f9efbd6cf7f12d
+ 79e49b5e7e3ff9f4.e16db756f9508de9.9683e5ac25bea71c.b0a4f063c1e99ffc
+ 5f277c14549ca706.e6554f7f64733e98.08fdddb71749066b.e4c5b7a6b323a055
+ f227c0715fb2af66
+ after
+ 0000000000000000.0000000000000000.b0a4f063c1e99ffc.79f9efbd6cf7f12d
+ 24e0cda489641abd.0620e2ff793b4d9a.c86243a9082f3a12.79f9efbd6cf7f12d
+ 79e49b5e7e3ff9f4.e16db756f9508de9.9683e5ac25bea71c.b0a4f063c1e99ffc
+ 5f277c14549ca706.e6554f7f64733e98.08fdddb71749066b.e4c5b7a6b323a055
+ f227c0715fb2af66
+VHADDPD_128(mem)
+ before
+ b49887afe0a18a59.34f56c34aa0661a0.f2a52867d7b11bd4.7a1c2634795b93ac
+ 07e2894e53fdeb5a.529a67291909636e.e229bdf86e15e2c9.482cbc91e880898a
+ c8d24039d3d08e96.16626a5f3f32e81b.90ad8a1f43ab4da2.ce799c39004425b2
+ d1342a5c7c293139.dd987041b80c2d54.d9fc0bc9757f188c.684fc1985c34a3d0
+ 72f9271a98db3f8f
+ after
+ b49887afe0a18a59.34f56c34aa0661a0.f2a52867d7b11bd4.7a1c2634795b93ac
+ 07e2894e53fdeb5a.529a67291909636e.e229bdf86e15e2c9.482cbc91e880898a
+ 0000000000000000.0000000000000000.7a1c2634795b93ac.e229bdf86e15e2c9
+ d1342a5c7c293139.dd987041b80c2d54.d9fc0bc9757f188c.684fc1985c34a3d0
+ 72f9271a98db3f8f
+
+VHADDPD_256(reg)
+ before
+ 47c4ca2b51c6349b.ffd4c3a36b118e6e.018a753d1f236ec5.99e4bde01e9e00b2
+ 45fca637227fbfa2.2e7e85fbbc966262.df8275bf1004e719.ad2f1b525a13c241
+ c7edb8aaa8951c4e.3afeee4e8ac36940.d4cd6d31283ad3fc.efaba10a46eb1765
+ 29e3fbf07e91864b.ff1f7989f1a55e35.3ab7570003516f1c.3c22cbf4fd31be49
+ 706016fc9bf1711a
+ after
+ c7edb8aaa8951c4e.45fca637227fbfa2.efaba10a46eb1765.df8275bf1004e719
+ 45fca637227fbfa2.2e7e85fbbc966262.df8275bf1004e719.ad2f1b525a13c241
+ c7edb8aaa8951c4e.3afeee4e8ac36940.d4cd6d31283ad3fc.efaba10a46eb1765
+ 29e3fbf07e91864b.ff1f7989f1a55e35.3ab7570003516f1c.3c22cbf4fd31be49
+ 706016fc9bf1711a
+VHADDPD_256(mem)
+ before
+ 6733fd0e3e38ed03.c62a6b7640013a46.59afa2990e47fe6d.6e8c31983cd6f722
+ fd66fb16ff11ee31.fc0d04a68c7074eb.2478e568fdb50513.cc97f6666f54a7bd
+ 0ec48f00fc882fd0.26d9c2eefb6b6fe5.3c47bfe4d9fc2e54.b025a3d43957ba97
+ 761a32b951a96d0b.9fdba2b92b7d69e1.7de7abf8be27375b.77833250356c6d5c
+ 7bfba145001efbba
+ after
+ 6733fd0e3e38ed03.c62a6b7640013a46.59afa2990e47fe6d.6e8c31983cd6f722
+ fd66fb16ff11ee31.fc0d04a68c7074eb.2478e568fdb50513.cc97f6666f54a7bd
+ 6733fd0e3e38ed03.fd66fb1773248863.6e8c31983cd6f722.cc97f6666f54a7bd
+ 761a32b951a96d0b.9fdba2b92b7d69e1.7de7abf8be27375b.77833250356c6d5c
+ 7bfba145001efbba
+
+VHADDPD_256(reg)
+ before
+ 19daeb1f35faa25a.1134622b1981640f.c55d9f72b8329c8b.c3262590c942da55
+ ad6b0d4a718a9ceb.bbde9944701ccf07.f2acb5873d16448e.eacfa9981559d36e
+ 93fc01324f5c2517.50e456ee73846c20.8413e16356b69f97.ceadb3fcbf79e0d1
+ 27d8c5436cfc7b8a.ac1212173ec7f486.d5e01d72a09ee751.4b8dc0a8e2aebbab
+ 3d3b4b889a022027
+ after
+ 50e456ee73846c20.bbde9944701ccf07.ceadb3fcbf79e0d1.f2acb5873d16448e
+ ad6b0d4a718a9ceb.bbde9944701ccf07.f2acb5873d16448e.eacfa9981559d36e
+ 93fc01324f5c2517.50e456ee73846c20.8413e16356b69f97.ceadb3fcbf79e0d1
+ 27d8c5436cfc7b8a.ac1212173ec7f486.d5e01d72a09ee751.4b8dc0a8e2aebbab
+ 3d3b4b889a022027
+VHADDPD_256(mem)
+ before
+ 8083d0890583cd72.c54a54e963f5d8f2.aa334aaaecf12664.435d6720b7585969
+ ef31cb953c3d7cb7.c89faa90d1d379f8.28157b93990cbde7.28d7bada3572308a
+ 6810b99a5d3aea24.8e23c3a551229a4b.018220be6226743a.e19a120ab978aa61
+ c6ee14828489d3e2.72229c927f6f7695.1147b517624b078a.cbf26c1dddf4019a
+ 402bc2803d7472e0
+ after
+ 8083d0890583cd72.c54a54e963f5d8f2.aa334aaaecf12664.435d6720b7585969
+ ef31cb953c3d7cb7.c89faa90d1d379f8.28157b93990cbde7.28d7bada3572308a
+ c54a54e963f5d8f2.ef31cb953c3d7cb7.435d6720b7585969.28d7bc31eeabc156
+ c6ee14828489d3e2.72229c927f6f7695.1147b517624b078a.cbf26c1dddf4019a
+ 402bc2803d7472e0
+
+VHADDPD_256(reg)
+ before
+ 9d91129e768438e0.e4955a3bcc33f220.d0e82fc5f8454a82.3330b68ab6853402
+ 3e6f57e223ae9046.a0d207b051460407.04c07aa8583152bf.4508a00379e2b5cf
+ 80128ebae080b6bd.d57195cd30cdc5c6.69f779a93abecaf8.219dee6fc86e471d
+ bdc7b1914b86e6f1.5e3e827e85d4f187.5dda26333a78edd8.a5b91cb8be34a617
+ ac29a6cc78408dea
+ after
+ d57195cd30cdc5c6.3e6f57e223ae9046.69f779a93abecaf8.4508a00379e2b5cf
+ 3e6f57e223ae9046.a0d207b051460407.04c07aa8583152bf.4508a00379e2b5cf
+ 80128ebae080b6bd.d57195cd30cdc5c6.69f779a93abecaf8.219dee6fc86e471d
+ bdc7b1914b86e6f1.5e3e827e85d4f187.5dda26333a78edd8.a5b91cb8be34a617
+ ac29a6cc78408dea
+VHADDPD_256(mem)
+ before
+ 11b90895119ebac2.52d8bed3fd4a5b8f.190548af6b684377.3bb37fb2f5ebf80c
+ b235bf01a55be6ca.9b91b0ec945a5243.e091654cfe9478c1.5ecf7f9206a42740
+ 696946fb5182d02f.f4408348ac4207b9.91b055415b644c92.2479223f0a2eb51f
+ 1321196f311f321c.b9303454e08db59c.062c927b9de57a15.e8ff64259d16df56
+ 05ab42b159e7e190
+ after
+ 11b90895119ebac2.52d8bed3fd4a5b8f.190548af6b684377.3bb37fb2f5ebf80c
+ b235bf01a55be6ca.9b91b0ec945a5243.e091654cfe9478c1.5ecf7f9206a42740
+ 52d8bed3fd4a5b8f.b235bf01a55be6ca.3bb37fb2f5ebf80c.e091654cfd987c31
+ 1321196f311f321c.b9303454e08db59c.062c927b9de57a15.e8ff64259d16df56
+ 05ab42b159e7e190
+
+VHSUBPS_128(reg)
+ before
+ d9cbb64ddd2df77a.8d28b449603fc9be.46acbd7accc79a98.1dd29ae4e122bf77
+ bea9be67c2755cbf.b14b9475faed5140.f7011c280d7cef5a.b06ee86a4228d7e4
+ 11925569a64a4d0c.5d5734df1c3685cf.287b4cc83f39f38e.9ccbf8f8dd027e87
+ 2fd278c12538060d.6b161074e2252397.35664ac8fd89e0e0.beb74679cdbc6f8d
+ f0fc4fdb2e626722
+ after
+ 0000000000000000.0000000000000000.3f39f38edd027e87.77011c284228d7e4
+ bea9be67c2755cbf.b14b9475faed5140.f7011c280d7cef5a.b06ee86a4228d7e4
+ 11925569a64a4d0c.5d5734df1c3685cf.287b4cc83f39f38e.9ccbf8f8dd027e87
+ 2fd278c12538060d.6b161074e2252397.35664ac8fd89e0e0.beb74679cdbc6f8d
+ f0fc4fdb2e626722
+VHSUBPS_128(mem)
+ before
+ 0f678e091e012271.72b422dadaccc26d.b854a41e67c6e5c3.7a0e1093e3f8f4fa
+ f7c57fefb6a45ba6.38864e206291bed9.20df6ccac7258780.53be9c948e13688b
+ 85df9e791458d0ef.db92faff581336fd.8081e5651f4fc6f9.1cc4e93999657b3d
+ 9384689454283b75.b82522e358df6684.b2088ada8a505e5b.316af3eda17b67bd
+ edfdb61d41e069b6
+ after
+ 0f678e091e012271.72b422dadaccc26d.b854a41e67c6e5c3.7a0e1093e3f8f4fa
+ f7c57fefb6a45ba6.38864e206291bed9.20df6ccac7258780.53be9c948e13688b
+ 0000000000000000.0000000000000000.67c6e5c3fa0e1093.c7258780d3be9c94
+ 9384689454283b75.b82522e358df6684.b2088ada8a505e5b.316af3eda17b67bd
+ edfdb61d41e069b6
+
+VHSUBPS_128(reg)
+ before
+ aec92f331620bdd5.fe7f572a91205867.2c8bc038ff80891a.933ed71525320bd2
+ cf1a599cbbc89ec6.a29be928e74de5ef.9110d26ae982dc6d.fff048010b038989
+ ac3b30c5cd624934.5ba6997b73b99c39.440053e6b1729b26.d2ea5a8c59ce93ad
+ a07ab018e77dfacc.056ae40d50733973.a1a63f16f3db01f4.e8f887a12aa0e669
+ 1de54d2d9a843eea
+ after
+ 0000000000000000.0000000000000000.c40053e659ce9756.e982dc6dfff04801
+ cf1a599cbbc89ec6.a29be928e74de5ef.9110d26ae982dc6d.fff048010b038989
+ ac3b30c5cd624934.5ba6997b73b99c39.440053e6b1729b26.d2ea5a8c59ce93ad
+ a07ab018e77dfacc.056ae40d50733973.a1a63f16f3db01f4.e8f887a12aa0e669
+ 1de54d2d9a843eea
+VHSUBPS_128(mem)
+ before
+ 4d7f281ac686565c.0921d603a6a2ed39.7cb444cc9b847ac6.045092684c494b81
+ 54909255cab3ebea.417d9cf0a55f5d28.9c5037a370fa1961.c94849465749b579
+ 0ee509cbc116b9c1.a6da004d803f8744.4109387ee9e1d36e.4cdb5f1eb1667b8a
+ 574a0766c8bb7b0c.9284fd85d4cfa73a.47adc34925436419.e955d05bf52cd85d
+ fc029869c02809a1
+ after
+ 4d7f281ac686565c.0921d603a6a2ed39.7cb444cc9b847ac6.045092684c494b81
+ 54909255cab3ebea.417d9cf0a55f5d28.9c5037a370fa1961.c94849465749b579
+ 0000000000000000.0000000000000000.fcb444cc4c494b81.70fa19615749b579
+ 574a0766c8bb7b0c.9284fd85d4cfa73a.47adc34925436419.e955d05bf52cd85d
+ fc029869c02809a1
+
+VHSUBPS_128(reg)
+ before
+ e12db4b4ade54a00.0b8b0a14f9aeeef8.63c790043d9af8b6.8a0655f03d2e878f
+ f4241ea859f0d726.06738ec073fcceb1.73efb336562cb763.e6e1685f4fadf9fc
+ 9131d4b15fd4ebc1.23d00d5550b1d762.20476487bb1220ee.360a7a8277cd768c
+ 14a1d13c5c1dc37a.406c05c1acd7c538.c41c9e6409d76f03.584d0646d099b96a
+ 27768995771d80c2
+ after
+ 0000000000000000.0000000000000000.bb1220ee77cd768c.f3efb33666e1685f
+ f4241ea859f0d726.06738ec073fcceb1.73efb336562cb763.e6e1685f4fadf9fc
+ 9131d4b15fd4ebc1.23d00d5550b1d762.20476487bb1220ee.360a7a8277cd768c
+ 14a1d13c5c1dc37a.406c05c1acd7c538.c41c9e6409d76f03.584d0646d099b96a
+ 27768995771d80c2
+VHSUBPS_128(mem)
+ before
+ 7f517d5d876685c1.d9c012b3eb579b00.3814f1efa47d535e.bdba5d37db07df4d
+ 3ba960881c7f8493.3cda9183a80faefd.e7944dcb53ac3d01.656d9e6dce2fad78
+ 394bad0454753b63.993b4c1930d0391d.28b89542d672414d.19815b737dda1532
+ 5403e0bc4852645e.4b2e3ee01f27780d.d94c463e48da196d.364192b485945225
+ 16fb3e9b81eaa1fd
+ after
+ 7f517d5d876685c1.d9c012b3eb579b00.3814f1efa47d535e.bdba5d37db07df4d
+ 3ba960881c7f8493.3cda9183a80faefd.e7944dcb53ac3d01.656d9e6dce2fad78
+ 0000000000000000.0000000000000000.b814f1efdb07df4d.67944dcbe56d9e6d
+ 5403e0bc4852645e.4b2e3ee01f27780d.d94c463e48da196d.364192b485945225
+ 16fb3e9b81eaa1fd
+
+VHSUBPS_256(reg)
+ before
+ 16f95c960e673e67.679d759c1624bcb0.b0016344109fa679.d51bdbacc6f0828d
+ 9288e610c797650f.50e5e990d9f7fe84.23feb8b09fc4010c.f7f3d0796bc138db
+ e6f4da75490751a0.e9a7b784aed6e806.007237926922c373.1d9ea18f5458f681
+ 6e8933312f423fc7.10ae5b64b1cd3464.a2a9de550946285a.21e9cadc9cc17aab
+ e1a0c84b60097d86
+ after
+ 66f4da7569a7b784.c797650fd9f7febd.6922c3735458f681.a3ff7cb177f3d07a
+ 9288e610c797650f.50e5e990d9f7fe84.23feb8b09fc4010c.f7f3d0796bc138db
+ e6f4da75490751a0.e9a7b784aed6e806.007237926922c373.1d9ea18f5458f681
+ 6e8933312f423fc7.10ae5b64b1cd3464.a2a9de550946285a.21e9cadc9cc17aab
+ e1a0c84b60097d86
+VHSUBPS_256(mem)
+ before
+ 378f16c7bb3bbe3e.8793edb015d46b2f.9fc8511dfce89ec8.67efa8661cbb6e6c
+ 0181303ec964f7fe.8b5d055f984a1185.74bf1699ae34e45e.a98f922f3e0ecf56
+ 1944929ba78ee5f3.d73575a8542f6c75.696024c5e0bcc053.c6d7961d09ca88c3
+ 5ca2b9cb71c84448.c7653bf8e410b9aa.5b77f98eb18cefd3.1811b29d1c7bd460
+ fd8ae11910aef1d8
+ after
+ 378f16c7bb3bbe3e.8793edb015d46b2f.9fc8511dfce89ec8.67efa8661cbb6e6c
+ 0181303ec964f7fe.8b5d055f984a1185.74bf1699ae34e45e.a98f922f3e0ecf56
+ bb3cdc6c15d46b2f.c964f7fe984a1185.fce89ec8e7efa866.f4bf16993e0ecf56
+ 5ca2b9cb71c84448.c7653bf8e410b9aa.5b77f98eb18cefd3.1811b29d1c7bd460
+ fd8ae11910aef1d8
+
+VHSUBPS_256(reg)
+ before
+ cf8e1fff83ee19d8.a76820b8411bcf2a.b73a52bce47733d1.27cf10df3ab12c09
+ ec6969b911c7880c.d462434f369544c5.0300b75ff1f21895.a736e6a39a363522
+ ae66b9b555c67c1f.c05c9e7d6a415d44.0603644ca70da2a3.b876f5c8ea28c449
+ 72d30d5eec762fbe.4722ad2cf92cd6d4.1e8e57f1a0530ea7.375cbb39489295ab
+ feb5b3e2d0806674
+ after
+ 55c67c1f6a415d44.6c6969b95462434f.a70da2a3ea28c449.f1f218952736e6a3
+ ec6969b911c7880c.d462434f369544c5.0300b75ff1f21895.a736e6a39a363522
+ ae66b9b555c67c1f.c05c9e7d6a415d44.0603644ca70da2a3.b876f5c8ea28c449
+ 72d30d5eec762fbe.4722ad2cf92cd6d4.1e8e57f1a0530ea7.375cbb39489295ab
+ feb5b3e2d0806674
+VHSUBPS_256(mem)
+ before
+ ea4a59af9dfff1cf.95fa60207163de95.467fed4a00606ca1.a6ee8bb97b50974c
+ d7ea2a8dcb19f3e9.7128ae67801ac44f.9740d9c19aecdbd6.fa70fc10d1907a3e
+ a160a16677dd28ee.63a9f49fb6261f98.1732ed7fe4d9df9f.765ea66241a0f32b
+ 24773a27bd544b09.c8c92d35af13291e.a21fa56ff9353429.7505861c640b3ebd
+ 55b197a8d95e96a0
+ after
+ ea4a59af9dfff1cf.95fa60207163de95.467fed4a00606ca1.a6ee8bb97b50974c
+ d7ea2a8dcb19f3e9.7128ae67801ac44f.9740d9c19aecdbd6.fa70fc10d1907a3e
+ 6a4a59af7163de95.57ea2a8df128ae67.c67fed4a7b50974c.9aeb5a227a70fc10
+ 24773a27bd544b09.c8c92d35af13291e.a21fa56ff9353429.7505861c640b3ebd
+ 55b197a8d95e96a0
+
+VHSUBPS_256(reg)
+ before
+ 71add57339243981.3dfd71bdb88c1966.fad45493066e1f8a.14d37e7df60b95a0
+ 24473cea22e9600c.c6bcc21384904e32.5616682757c23c8b.491cf295f668bf30
+ ccc9c978303a4aec.9c81aa143e6da599.38da625b3f9bbdcb.1dc57fa316576e04
+ c4807688fea131ce.9b18a3ae012edcc6.fc6d409d5986def6.6c99a09371e45d48
+ 1265d252231c4929
+ after
+ 4cc9c9783e6da599.a42a10e846bcc213.3f9bba619dc57df4.57af6f86f668bf30
+ 24473cea22e9600c.c6bcc21384904e32.5616682757c23c8b.491cf295f668bf30
+ ccc9c978303a4aec.9c81aa143e6da599.38da625b3f9bbdcb.1dc57fa316576e04
+ c4807688fea131ce.9b18a3ae012edcc6.fc6d409d5986def6.6c99a09371e45d48
+ 1265d252231c4929
+VHSUBPS_256(mem)
+ before
+ ebf58fca490aeed3.67b8418829ad525e.9e4c2bcceadface6.fe1bfc57420edbba
+ d31555e9ffba0772.13bd25e34ce7e947.83ebbe5a148dd425.9a3094f795bfefc0
+ a6919f9960395131.22db1f0503dd3136.25bfd6449c430fae.2cf804e8ef2657b7
+ 4035eac88892883c.f25d295aeb1a67d6.6095f1769d0d18ae.10bf4696ebce4f49
+ a2d0586d26441222
+ after
+ ebf58fca490aeed3.67b8418829ad525e.9e4c2bcceadface6.fe1bfc57420edbba
+ d31555e9ffba0772.13bd25e34ce7e947.83ebbe5a148dd425.9a3094f795bfefc0
+ 6bf58fcae7b84188.fffa07724ce7e947.eadface67e1bfc57.148dd4251a3034ff
+ 4035eac88892883c.f25d295aeb1a67d6.6095f1769d0d18ae.10bf4696ebce4f49
+ a2d0586d26441222
+
+VHSUBPD_128(reg)
+ before
+ 3e7835da3b12deef.7cccb06194d168c0.dd91414e9f2bc7d4.103989dc34f8ab50
+ 4004d947c7c7ed5c.38246f509f03ade9.41c1624dbc9b8ddb.11771d637c0f86c1
+ 04be402165ec7b15.4f07a281c63312e2.783a88c4def6f498.3e1b26f5925e632d
+ e6f267d5b10fc6c5.9d42c5e0246d53d8.df48b01d9fc939b7.75f1218091f2ffbf
+ 91c48bef95d616a4
+ after
+ 0000000000000000.0000000000000000.f83a88c4def6f498.c1c1624dbc9b8ddb
+ 4004d947c7c7ed5c.38246f509f03ade9.41c1624dbc9b8ddb.11771d637c0f86c1
+ 04be402165ec7b15.4f07a281c63312e2.783a88c4def6f498.3e1b26f5925e632d
+ e6f267d5b10fc6c5.9d42c5e0246d53d8.df48b01d9fc939b7.75f1218091f2ffbf
+ 91c48bef95d616a4
+VHSUBPD_128(mem)
+ before
+ 6e61df2dbb166307.41ee49cd48bb0818.fda15459d6be2ef7.d337d5c69e9f98e3
+ e79499281fbfa315.73fde277c67d7ebb.4defccd8f7315d6a.ae52f22974044cc9
+ da2936cbdcdc92f9.d76a2e3ec6df635a.68faa74aa4d29d5e.cde706b4c0859314
+ 21ec30020e79ece0.c982298ee470f4a0.298c6399f8aeaafe.8c400ad21bada771
+ 47aafbef2308c48c
+ after
+ 6e61df2dbb166307.41ee49cd48bb0818.fda15459d6be2ef7.d337d5c69e9f98e3
+ e79499281fbfa315.73fde277c67d7ebb.4defccd8f7315d6a.ae52f22974044cc9
+ 0000000000000000.0000000000000000.7da15459d6be2ef7.cdefccd8f7315d6a
+ 21ec30020e79ece0.c982298ee470f4a0.298c6399f8aeaafe.8c400ad21bada771
+ 47aafbef2308c48c
+
+VHSUBPD_128(reg)
+ before
+ 5b71d67774232710.9aa905b9d2a36cf6.a491d0d3bdb96d3a.6e727cb310d03f77
+ 22e196d6a9890daa.1f2b30dc4365cf66.c6e31e79ec480ad4.11796c82074419f4
+ f94637785fc7af06.8e402d587eccd15d.8ac40fec0ea80619.f06ab1f4fa17f4a2
+ 3cebb6c931674ccf.c1b279179ee22d07.4b7f9f98be669fb6.e514c6f404548cad
+ ce42276e41089c40
+ after
+ 0000000000000000.0000000000000000.f06ab1f4fa17f4a2.46e31e79ec480ad4
+ 22e196d6a9890daa.1f2b30dc4365cf66.c6e31e79ec480ad4.11796c82074419f4
+ f94637785fc7af06.8e402d587eccd15d.8ac40fec0ea80619.f06ab1f4fa17f4a2
+ 3cebb6c931674ccf.c1b279179ee22d07.4b7f9f98be669fb6.e514c6f404548cad
+ ce42276e41089c40
+VHSUBPD_128(mem)
+ before
+ 85bf504ece3ee188.471d0e36bbf71eb1.964e8f07c0b6a08f.6762cbe9990d0e56
+ e758be80c70217b1.76293a299a036259.e7e0eb12ff51e622.38b78e4c3a2992a6
+ d1daebf04760f9e6.255938106a165473.9133092678c1bbeb.1ccbe42b3e476551
+ 1d0f558b6a654553.b0fa0456c6bc2faa.7115652e4611da17.6deac9f440f2c404
+ 89603912ddb6eb6b
+ after
+ 85bf504ece3ee188.471d0e36bbf71eb1.964e8f07c0b6a08f.6762cbe9990d0e56
+ e758be80c70217b1.76293a299a036259.e7e0eb12ff51e622.38b78e4c3a2992a6
+ 0000000000000000.0000000000000000.6762cbe9990d0e56.67e0eb12ff51e622
+ 1d0f558b6a654553.b0fa0456c6bc2faa.7115652e4611da17.6deac9f440f2c404
+ 89603912ddb6eb6b
+
+VHSUBPD_128(reg)
+ before
+ ca7931f1b0201531.a8c3783b4d1cb426.735798664a8130ab.61507c15864e00d1
+ 8d80acfc56bb8003.4ec4ceee0b920588.cabef2ae93f29322.3eb1c9c95382e946
+ 2fc3a6a16a13668d.ecddd58ec1d2f2a8.10790d993c9a93ba.e405c835c9bc50a2
+ 0a8c1b4c88b4037a.5cd908098ae838b0.a3d6e593e2066e20.3015f5460605f310
+ fcb0cce6236b8cbd
+ after
+ 0000000000000000.0000000000000000.e405c835c9bc50a2.4abef2ae93f29322
+ 8d80acfc56bb8003.4ec4ceee0b920588.cabef2ae93f29322.3eb1c9c95382e946
+ 2fc3a6a16a13668d.ecddd58ec1d2f2a8.10790d993c9a93ba.e405c835c9bc50a2
+ 0a8c1b4c88b4037a.5cd908098ae838b0.a3d6e593e2066e20.3015f5460605f310
+ fcb0cce6236b8cbd
+VHSUBPD_128(mem)
+ before
+ 25a1ca023ef9d7d4.7b2807674d2c9476.7b85e34a83e093cc.de1f770820c15eff
+ 87b36a8772bc9182.dee3675f5504552e.25ade23dc7c7bf2a.1da1bd6493579f04
+ feb4285fdcbf77f3.900836a03bca824e.361d81ce73a877f3.bba7b514d6546fdb
+ 666e8078980e4252.ebe570979b095782.8aa13de9a2907856.167f5a828645082f
+ 8973a81c3eb5a7ad
+ after
+ 25a1ca023ef9d7d4.7b2807674d2c9476.7b85e34a83e093cc.de1f770820c15eff
+ 87b36a8772bc9182.dee3675f5504552e.25ade23dc7c7bf2a.1da1bd6493579f04
+ 0000000000000000.0000000000000000.fb85e34a83e093cc.a5ade23dc7c7bf2a
+ 666e8078980e4252.ebe570979b095782.8aa13de9a2907856.167f5a828645082f
+ 8973a81c3eb5a7ad
+
+VHSUBPD_256(reg)
+ before
+ 6fd19c4c9a318700.9baeefbcc1b6b1cc.4cc412ae124d0f75.fd04917a718a7d7d
+ 26e331803744e5d5.7940f01973c27e8c.0ff316533b23e7d3.6b14f96dfba24494
+ 09f66223b17afdd7.dcefff7acb3e66bf.90bc7af1b3161a4a.b09bf2ae5ce587c9
+ 73562ea1a3600bb3.a08998cbe4362591.2b6c39f415b2e683.a866f62ab15e0345
+ 2f4183cb16197337
+ after
+ dcefff7acb3e66bf.7940f01973c27e8c.b09bf2ae5ce587c9.6b14f96dfba24494
+ 26e331803744e5d5.7940f01973c27e8c.0ff316533b23e7d3.6b14f96dfba24494
+ 09f66223b17afdd7.dcefff7acb3e66bf.90bc7af1b3161a4a.b09bf2ae5ce587c9
+ 73562ea1a3600bb3.a08998cbe4362591.2b6c39f415b2e683.a866f62ab15e0345
+ 2f4183cb16197337
+VHSUBPD_256(mem)
+ before
+ 21f8147fa62394c9.c24f8e66a9814b15.a1d837f8dbb7762d.3c4e4fc8fe84852d
+ 5a5625317d872227.502c80de6069f8a8.bba959edcbcd16c0.1fb0b9d9091734f2
+ b52933cdb851d97e.7a3afe7564a54f19.c9c87997d182c175.30dc7293d3f82e7e
+ 103bb93e738e74fa.9dc6069750bf8b14.a90113e008e43279.cb207562f7b1b07e
+ 4cc6c1b212d0f69e
+ after
+ 21f8147fa62394c9.c24f8e66a9814b15.a1d837f8dbb7762d.3c4e4fc8fe84852d
+ 5a5625317d872227.502c80de6069f8a8.bba959edcbcd16c0.1fb0b9d9091734f2
+ c24f8e66a9814b15.da5625317d872227.3c4e4fc8fe84852d.3ba959edcbcd16c0
+ 103bb93e738e74fa.9dc6069750bf8b14.a90113e008e43279.cb207562f7b1b07e
+ 4cc6c1b212d0f69e
+
+VHSUBPD_256(reg)
+ before
+ 0f1b4ff0bfe13c8a.46593272c849b1c6.131a94b1c046e944.3620a3b58cff27f8
+ 6f6b1c869a6fbded.334f1d55d68e490f.3a83a22d51c3a555.4cf1a6037add5a1d
+ ca0125e24006b773.b2e9f3d1b66afb01.6c4c2e799ec4fbf5.c63f97b5ee8c8714
+ 7b2b656e4d3263c9.a1f332d387e881c7.06c333ff44d527cd.82d7f1b603186c0b
+ 5b8533f4d58cc32c
+ after
+ 4a0125e24006b773.ef6b1c869a6fbded.ec4c2e799ec4fbf5.4cf1a6037add5a1d
+ 6f6b1c869a6fbded.334f1d55d68e490f.3a83a22d51c3a555.4cf1a6037add5a1d
+ ca0125e24006b773.b2e9f3d1b66afb01.6c4c2e799ec4fbf5.c63f97b5ee8c8714
+ 7b2b656e4d3263c9.a1f332d387e881c7.06c333ff44d527cd.82d7f1b603186c0b
+ 5b8533f4d58cc32c
+VHSUBPD_256(mem)
+ before
+ 2c15d65a81f449a3.de33d8985c80009b.db3854476214988e.6432ad2dde80648c
+ d35358d4235cb99d.4e667bcb097cc894.3b86d71a66fbfc81.e3e7986e0953efdc
+ 2a0b344ed6d1d146.29114973f1b0f861.9fa73736aca868cd.dd2cf12e60da036a
+ 0f08e6b4b65e4bc9.ca7d3dfcafaaccae.e168ee895228999d.af4eb2d980a0dee1
+ b599d9db0431baee
+ after
+ 2c15d65a81f449a3.de33d8985c80009b.db3854476214988e.6432ad2dde80648c
+ d35358d4235cb99d.4e667bcb097cc894.3b86d71a66fbfc81.e3e7986e0953efdc
+ de33d8985c80009b.535358d4235cb99d.6432ad2dde80648c.e3e7986e0953efdc
+ 0f08e6b4b65e4bc9.ca7d3dfcafaaccae.e168ee895228999d.af4eb2d980a0dee1
+ b599d9db0431baee
+
+VHSUBPD_256(reg)
+ before
+ 4b5862a08819d43c.5c18eaf3e00fe353.8cf956d2e0f57f26.df957afe74854b1f
+ cdd94794a9e56778.ef05bcf56ff15710.cdd08d611f1e4e76.73fa56812dcd3a7c
+ 976686240320b04e.a29cd9a8800f612b.e74ddf1609b07549.7b62fefe990c21e2
+ 054c19ba3156eb69.53a9bcf62e76bed0.38bd495b3937304c.d19bee61d54dbd7d
+ 526fa396fd9cca79
+ after
+ a29cd9a8800f612b.ef05bcf56ff15710.7b62fefe990c21e2.73fa56812dcd3a7c
+ cdd94794a9e56778.ef05bcf56ff15710.cdd08d611f1e4e76.73fa56812dcd3a7c
+ 976686240320b04e.a29cd9a8800f612b.e74ddf1609b07549.7b62fefe990c21e2
+ 054c19ba3156eb69.53a9bcf62e76bed0.38bd495b3937304c.d19bee61d54dbd7d
+ 526fa396fd9cca79
+VHSUBPD_256(mem)
+ before
+ dbab97892c050301.73d7ffc4cf145476.dcf7e1cd9631292d.1a6dc69e4c40ba2a
+ 461b48267e952642.3d5331ac7ae52620.1a54c518d34c606b.eba75249dd555090
+ 708b315a1057ec67.bf0cace0cd569e14.ea8ae2c201d31db9.05b7eaca89052e2a
+ 36c7cf0ffd58149d.554e6dcb65f1f8fd.2667b6b93ed31c41.c6eb888cebd98fa3
+ 888d2afba05fb0a8
+ after
+ dbab97892c050301.73d7ffc4cf145476.dcf7e1cd9631292d.1a6dc69e4c40ba2a
+ 461b48267e952642.3d5331ac7ae52620.1a54c518d34c606b.eba75249dd555090
+ 73d7ffc4cf145476.c61b48267e952642.5cf7e1cd9631292d.eba75249dd555090
+ 36c7cf0ffd58149d.554e6dcb65f1f8fd.2667b6b93ed31c41.c6eb888cebd98fa3
+ 888d2afba05fb0a8
+
+VEXTRACTPS_0x0(reg)
+ before
+ a8ebcb834323cde5.729a9d3362a3580f.5b646fd9de457089.abb5bce8a3571b2f
+ 834f689070af2205.01d116b05b4475ea.2d9bae76d2db4161.5541703c4e6cd4b1
+ 7306fb8ec491eab4.bf39b8740247275a.263f270ee041a834.00d64f9f5b1d04f1
+ d55c82e9db55629f.889cff6a75b92a8a.a49cd40da102e1ac.8842d3fee576671b
+ ca4f7a460883b85c
+ after
+ a8ebcb834323cde5.729a9d3362a3580f.5b646fd9de457089.abb5bce8a3571b2f
+ 834f689070af2205.01d116b05b4475ea.2d9bae76d2db4161.5541703c4e6cd4b1
+ 7306fb8ec491eab4.bf39b8740247275a.263f270ee041a834.00d64f9f5b1d04f1
+ d55c82e9db55629f.889cff6a75b92a8a.a49cd40da102e1ac.8842d3fee576671b
+ 000000004e6cd4b1
+VEXTRACTPS_0x0(mem)
+ before
+ a0cbbf61e151b4e0.059df80e5085c672.38c7657ed0a639a7.02feb3e0b3ab2775
+ e7801f3d8bec17d2.60145967bfb051d9.ab85689c2e1811dc.9bb1bff1b2c7b73c
+ 7b3b14c4235e9c5f.400fa162c55f417f.bda483b0ac1d6d56.cd00f4ae39e2cdad
+ 38c81ce4c5b501b2.02d8cd69fd20d010.4aee32a765c00b41.f3394f81e588a473
+ 68a6cbd851467a3b
+ after
+ a0cbbf61e151b4e0.059df80e5085c672.38c7657ed0a639a7.02feb3e0b2c7b73c
+ e7801f3d8bec17d2.60145967bfb051d9.ab85689c2e1811dc.9bb1bff1b2c7b73c
+ 7b3b14c4235e9c5f.400fa162c55f417f.bda483b0ac1d6d56.cd00f4ae39e2cdad
+ 38c81ce4c5b501b2.02d8cd69fd20d010.4aee32a765c00b41.f3394f81e588a473
+ 68a6cbd851467a3b
+
+VEXTRACTPS_0x0(reg)
+ before
+ 8a94641e19a789b1.faf2b2888bfcfff8.02bcd8ea047e3a3a.2e30f26b760ea5c8
+ b34f16bfda380d80.9c87529c9440555c.9c07be507505bda6.45373de9fa12f818
+ 4122dd2730844454.fc51790cf98cbe0c.2c057b07ed429303.6bcc910e0dd8bf5c
+ 8e5bb6c2b61768db.f51da1c4d9ecf531.0e010b7b07c0f8fb.7cbe69c5cc6db7c1
+ 54d841f952dc9c72
+ after
+ 8a94641e19a789b1.faf2b2888bfcfff8.02bcd8ea047e3a3a.2e30f26b760ea5c8
+ b34f16bfda380d80.9c87529c9440555c.9c07be507505bda6.45373de9fa12f818
+ 4122dd2730844454.fc51790cf98cbe0c.2c057b07ed429303.6bcc910e0dd8bf5c
+ 8e5bb6c2b61768db.f51da1c4d9ecf531.0e010b7b07c0f8fb.7cbe69c5cc6db7c1
+ 00000000fa12f818
+VEXTRACTPS_0x0(mem)
+ before
+ cfe59698bc312a9d.f8449bfc087eb6bf.63b748b14d6db6fa.9e496b18600b2a3a
+ c8b3e28d26791c6b.d92a8a41c34469ac.22ebe9bd731abf91.3827964a93b0636d
+ 1d0ca3c4abbf300b.8f5a7ffd82f5bf4f.0e8501d567ffca22.38e8887e3c3ae040
+ a9bd5429670f1fa7.741d749de21ef254.02510ae6442994da.f9d83e1ef936dd5f
+ d943b297632f9574
+ after
+ cfe59698bc312a9d.f8449bfc087eb6bf.63b748b14d6db6fa.9e496b1893b0636d
+ c8b3e28d26791c6b.d92a8a41c34469ac.22ebe9bd731abf91.3827964a93b0636d
+ 1d0ca3c4abbf300b.8f5a7ffd82f5bf4f.0e8501d567ffca22.38e8887e3c3ae040
+ a9bd5429670f1fa7.741d749de21ef254.02510ae6442994da.f9d83e1ef936dd5f
+ d943b297632f9574
+
+VEXTRACTPS_0x0(reg)
+ before
+ 3375e25618b1452e.479272a87776a86b.e5c2678b7f4a3e66.dc1a82db27a3d9e5
+ 63b9c9c6b4482937.d556772ef6ff8584.3e945335f305e132.77ade49f2b7a546e
+ c55d6353d2817d3c.2ed7e1a501b6731e.dcde3406dddc1563.aed6ac206cb8c2a2
+ b4abad680ee77ce8.2ddf2bfab3a82e64.19ee066ad65a17a6.5f615649076bdfad
+ 641a5f06179f67ba
+ after
+ 3375e25618b1452e.479272a87776a86b.e5c2678b7f4a3e66.dc1a82db27a3d9e5
+ 63b9c9c6b4482937.d556772ef6ff8584.3e945335f305e132.77ade49f2b7a546e
+ c55d6353d2817d3c.2ed7e1a501b6731e.dcde3406dddc1563.aed6ac206cb8c2a2
+ b4abad680ee77ce8.2ddf2bfab3a82e64.19ee066ad65a17a6.5f615649076bdfad
+ 000000002b7a546e
+VEXTRACTPS_0x0(mem)
+ before
+ 9bcd4243b95e15f6.8ef0a173050763e8.b03bd11a28e07183.520ec6cc7c0b23a7
+ de457bed09b7a68c.ae783ddf526c6ee8.91b850f07d6bf9a7.e38b6e9a6b7c7411
+ 0b5086ee21b3d6a9.6f8e7c1992a2d893.ae1f2367ce5382fb.28b0fc403e384791
+ fcb8e03320606078.2f805a8b6036de95.e13fc56d36a7c8ab.7dcb6c2892cbd8d2
+ 3f27b8bf02c26281
+ after
+ 9bcd4243b95e15f6.8ef0a173050763e8.b03bd11a28e07183.520ec6cc6b7c7411
+ de457bed09b7a68c.ae783ddf526c6ee8.91b850f07d6bf9a7.e38b6e9a6b7c7411
+ 0b5086ee21b3d6a9.6f8e7c1992a2d893.ae1f2367ce5382fb.28b0fc403e384791
+ fcb8e03320606078.2f805a8b6036de95.e13fc56d36a7c8ab.7dcb6c2892cbd8d2
+ 3f27b8bf02c26281
+
+VEXTRACTPS_0x1(reg)
+ before
+ c80fde712aa8234a.8f4a03a91fc90126.4898d4a259b3bc9c.08e3b5edd27086e5
+ 75d0d9aba70a54d8.9ed26d3a3dfa75df.1824e5cb18a5ae52.fdd66cd3bdbc79d3
+ a1b6a5d8157234d8.061b9ad4930078ce.f96e89703a98ef63.9de6670b13965da1
+ aa0d3e630e6ffdf5.a4f3046240e6c520.49c3bcff5a19bc7c.c5dd2382f10aed7c
+ 4f881b227225e790
+ after
+ c80fde712aa8234a.8f4a03a91fc90126.4898d4a259b3bc9c.08e3b5edd27086e5
+ 75d0d9aba70a54d8.9ed26d3a3dfa75df.1824e5cb18a5ae52.fdd66cd3bdbc79d3
+ a1b6a5d8157234d8.061b9ad4930078ce.f96e89703a98ef63.9de6670b13965da1
+ aa0d3e630e6ffdf5.a4f3046240e6c520.49c3bcff5a19bc7c.c5dd2382f10aed7c
+ 00000000fdd66cd3
+VEXTRACTPS_0x1(mem)
+ before
+ 18b2cbd8b3f30408.eb21a1ba318aeddc.522428d05db91901.626f7ae215b45149
+ fd29b091d07e0311.c03dc84818513d39.ed7c830a0884309c.a2bdc08706f3e975
+ d8b84437e3d49ed6.85afb1795f4f2cb7.52c590fc5d53c51d.63fb8959ca64c1ad
+ 862a05b80b009284.96c157b9a311f403.5bcccc92773296b1.0273d1c4fc93159c
+ db729434380a21f0
+ after
+ 18b2cbd8b3f30408.eb21a1ba318aeddc.522428d05db91901.626f7ae2a2bdc087
+ fd29b091d07e0311.c03dc84818513d39.ed7c830a0884309c.a2bdc08706f3e975
+ d8b84437e3d49ed6.85afb1795f4f2cb7.52c590fc5d53c51d.63fb8959ca64c1ad
+ 862a05b80b009284.96c157b9a311f403.5bcccc92773296b1.0273d1c4fc93159c
+ db729434380a21f0
+
+VEXTRACTPS_0x1(reg)
+ before
+ 4b44cf151b572052.e34c6eff610f9b47.4fc0b7747f21d2c8.e55cb1b8722e5d84
+ ac357cd441064f70.cbeafcf8040c754a.0bf8cb16900e02b3.cc43bd5a6b53d6c2
+ 5b9199db44a1eaf6.1ad0298f0d03dbba.28b5910b7161bf70.ec4b6b657eabbe96
+ b4a32298c3b62c90.acca73b09a008ac2.014304c0bfa846aa.214237c3c644d22c
+ 47f29d625f29cbb1
+ after
+ 4b44cf151b572052.e34c6eff610f9b47.4fc0b7747f21d2c8.e55cb1b8722e5d84
+ ac357cd441064f70.cbeafcf8040c754a.0bf8cb16900e02b3.cc43bd5a6b53d6c2
+ 5b9199db44a1eaf6.1ad0298f0d03dbba.28b5910b7161bf70.ec4b6b657eabbe96
+ b4a32298c3b62c90.acca73b09a008ac2.014304c0bfa846aa.214237c3c644d22c
+ 00000000cc43bd5a
+VEXTRACTPS_0x1(mem)
+ before
+ 3a281a2d66676851.13b9117558d152e9.5da35547c7103d8f.f1ed219f156ed30d
+ d6b0280ff6096338.d51d63e09f7d98ad.09294b40af3fb24d.5600e2160f40a247
+ f75545f62c1b7991.541c154335463a89.8c26d1886f97a327.8bc945904aa9ee02
+ 79e5edcd23aa6688.ed02220cb5b87329.c26764092226cd4a.eb9245796235f4ea
+ d4a7de3cf270f0ac
+ after
+ 3a281a2d66676851.13b9117558d152e9.5da35547c7103d8f.f1ed219f5600e216
+ d6b0280ff6096338.d51d63e09f7d98ad.09294b40af3fb24d.5600e2160f40a247
+ f75545f62c1b7991.541c154335463a89.8c26d1886f97a327.8bc945904aa9ee02
+ 79e5edcd23aa6688.ed02220cb5b87329.c26764092226cd4a.eb9245796235f4ea
+ d4a7de3cf270f0ac
+
+VEXTRACTPS_0x1(reg)
+ before
+ a0560c4796e71df4.382a9a80f8c1e54a.fc1b87a6bc608039.87b87fb1e4f7ebe1
+ adeacc05eb26b86d.10f1cafbc66cb303.ddb23e7de5c99d64.b7e59e6ad217ba19
+ 55ae19e38db7fdc4.dd06f82baab88cde.ec1545fdcd7f0656.2eb93d220891f61e
+ f5efef4b172828a5.7a35a0fabfb02b08.858e97930f0ff6bc.c802d9c4a1715b1b
+ 608aec3cb9c4a43d
+ after
+ a0560c4796e71df4.382a9a80f8c1e54a.fc1b87a6bc608039.87b87fb1e4f7ebe1
+ adeacc05eb26b86d.10f1cafbc66cb303.ddb23e7de5c99d64.b7e59e6ad217ba19
+ 55ae19e38db7fdc4.dd06f82baab88cde.ec1545fdcd7f0656.2eb93d220891f61e
+ f5efef4b172828a5.7a35a0fabfb02b08.858e97930f0ff6bc.c802d9c4a1715b1b
+ 00000000b7e59e6a
+VEXTRACTPS_0x1(mem)
+ before
+ d41ef4766d958faf.eaf94aaa250574bb.c54a3e5622604ead.036a30a94704aa42
+ ff8a6c5ed8f0d59e.8e18266d54d81eb2.99114f29eed5aff8.c4f50cac12eb5e94
+ bc9ad1e017e23535.3e9880fe3f2f6238.d2554d613f1a0a16.237b28090c4f4d5c
+ e91a9de8457669a1.57c553cb83967bf6.4be3b6e9323b1d32.7c487e2ad0bcb449
+ 2ba70c7dfbbecf05
+ after
+ d41ef4766d958faf.eaf94aaa250574bb.c54a3e5622604ead.036a30a9c4f50cac
+ ff8a6c5ed8f0d59e.8e18266d54d81eb2.99114f29eed5aff8.c4f50cac12eb5e94
+ bc9ad1e017e23535.3e9880fe3f2f6238.d2554d613f1a0a16.237b28090c4f4d5c
+ e91a9de8457669a1.57c553cb83967bf6.4be3b6e9323b1d32.7c487e2ad0bcb449
+ 2ba70c7dfbbecf05
+
+VEXTRACTPS_0x2(reg)
+ before
+ 8be6ce6d27e2d93d.61d54e637fb92e0e.33ea9b3fbb97a69b.e28705ace345a279
+ fa4fbe66f3b3109c.ff995f3be0b540a7.2f5454c584c01fd1.710db7986d435617
+ d32fdad4f9beaecf.a1304c5e85785a99.a74f7bcb799d2244.d6414698ec41f437
+ 71d21d23d58eef82.216792b6890e3910.f8270bbc36b8eaa2.ebef30987d4c3a05
+ 8ee2f0853b6fe2af
+ after
+ 8be6ce6d27e2d93d.61d54e637fb92e0e.33ea9b3fbb97a69b.e28705ace345a279
+ fa4fbe66f3b3109c.ff995f3be0b540a7.2f5454c584c01fd1.710db7986d435617
+ d32fdad4f9beaecf.a1304c5e85785a99.a74f7bcb799d2244.d6414698ec41f437
+ 71d21d23d58eef82.216792b6890e3910.f8270bbc36b8eaa2.ebef30987d4c3a05
+ 0000000084c01fd1
+VEXTRACTPS_0x2(mem)
+ before
+ 99e8034943b7a85e.328483bf24af1160.5d0aab3108829937.7c280004599fb494
+ eacbe3d1b02e4a41.7190081481ae4e15.2fe515ba1fe0363b.909e56107bdebcc9
+ 5b580e0a9fe38282.8944a98e8915e34f.75c34b3dea34cb47.90d4094a3a003eeb
+ ca5bffde2bdf0d4e.d8ea609ad7730bb8.0972caa6848b1588.d818161f329175a6
+ c4b478fcfe1d9ea8
+ after
+ 99e8034943b7a85e.328483bf24af1160.5d0aab3108829937.7c2800041fe0363b
+ eacbe3d1b02e4a41.7190081481ae4e15.2fe515ba1fe0363b.909e56107bdebcc9
+ 5b580e0a9fe38282.8944a98e8915e34f.75c34b3dea34cb47.90d4094a3a003eeb
+ ca5bffde2bdf0d4e.d8ea609ad7730bb8.0972caa6848b1588.d818161f329175a6
+ c4b478fcfe1d9ea8
+
+VEXTRACTPS_0x2(reg)
+ before
+ b0f52b4b3a31f49a.119f323b7130a6d0.b8cf2ba2085104fc.c8bc0ce109f0d029
+ f8272b7a8358b52b.0df2230c8ce10b35.873f0614b73d08c8.8f6e8fda9670b757
+ f89675f4741e1b05.9b1e4f3d99fff6a8.9f86eb5b81c353c8.3854ce7d4715883e
+ 0c8d0325aa1063d4.95f131bab3942356.5df0d8e3016d23a7.a03a45b736eefc09
+ a4ec71728204d2e5
+ after
+ b0f52b4b3a31f49a.119f323b7130a6d0.b8cf2ba2085104fc.c8bc0ce109f0d029
+ f8272b7a8358b52b.0df2230c8ce10b35.873f0614b73d08c8.8f6e8fda9670b757
+ f89675f4741e1b05.9b1e4f3d99fff6a8.9f86eb5b81c353c8.3854ce7d4715883e
+ 0c8d0325aa1063d4.95f131bab3942356.5df0d8e3016d23a7.a03a45b736eefc09
+ 00000000b73d08c8
+VEXTRACTPS_0x2(mem)
+ before
+ 1e35cc9c4565c4fd.8f5ad379c0b9c846.d835456ff7af506b.1ec8c717d3c9b212
+ ebe2d4209b1c8f7e.df47e15c53a68704.40b7074880593712.3c5bb76595633db4
+ e7c004e9a136ef94.57a1273afe62dcbd.a942f3316aa09578.14f6a139e0c5ff3a
+ ee99d9e572bea06a.53b4a37f5e79031b.f0a48616d28f26c8.03e382fd527d3650
+ 636e571e86171ca1
+ after
+ 1e35cc9c4565c4fd.8f5ad379c0b9c846.d835456ff7af506b.1ec8c71780593712
+ ebe2d4209b1c8f7e.df47e15c53a68704.40b7074880593712.3c5bb76595633db4
+ e7c004e9a136ef94.57a1273afe62dcbd.a942f3316aa09578.14f6a139e0c5ff3a
+ ee99d9e572bea06a.53b4a37f5e79031b.f0a48616d28f26c8.03e382fd527d3650
+ 636e571e86171ca1
+
+VEXTRACTPS_0x2(reg)
+ before
+ 91e51b08191dedda.dc3acdff2ac05d2d.2ecc4f970e7737ca.efa73be4d333a52f
+ e993ca28a71de7a7.8d6e5e23e749e309.463429efabe9b677.83198e858a97cfd9
+ c7c361e8cba344b3.dd03073ec263ed28.f63a2df1d05bb9ce.88c4fbe713c760f1
+ 87c2dab6213941aa.a8c3443ad91d39b9.9928550b1a577f7a.da75fff589d013a4
+ 55f8159a08bca61d
+ after
+ 91e51b08191dedda.dc3acdff2ac05d2d.2ecc4f970e7737ca.efa73be4d333a52f
+ e993ca28a71de7a7.8d6e5e23e749e309.463429efabe9b677.83198e858a97cfd9
+ c7c361e8cba344b3.dd03073ec263ed28.f63a2df1d05bb9ce.88c4fbe713c760f1
+ 87c2dab6213941aa.a8c3443ad91d39b9.9928550b1a577f7a.da75fff589d013a4
+ 00000000abe9b677
+VEXTRACTPS_0x2(mem)
+ before
+ d518b9c4ad9ad289.85dc33fd466d1a39.ca7b9104488081e6.8d4b9fa8246b4228
+ 36a3675e93735614.1d5d6729d5cb0a0c.1ff86b892a9a82dc.2cef06338a223f84
+ 53639b54d755ece9.ab9172a66bde4ecf.83044db39b77f7c6.d460861ae909b239
+ 0a25d293944c5235.8bc451e0a332222d.d26bb370b8219dd1.dfea1bc8ddabd6f3
+ abd8c2a90194e860
+ after
+ d518b9c4ad9ad289.85dc33fd466d1a39.ca7b9104488081e6.8d4b9fa82a9a82dc
+ 36a3675e93735614.1d5d6729d5cb0a0c.1ff86b892a9a82dc.2cef06338a223f84
+ 53639b54d755ece9.ab9172a66bde4ecf.83044db39b77f7c6.d460861ae909b239
+ 0a25d293944c5235.8bc451e0a332222d.d26bb370b8219dd1.dfea1bc8ddabd6f3
+ abd8c2a90194e860
+
+VEXTRACTPS_0x3(reg)
+ before
+ 92787629f151242a.36b58705e7624123.1941fe431a53c1d2.e8fb19aa9da63029
+ f21433b54a6dc6fd.b3df3697eba578e0.b156773b6bce696b.a17efb4f65126cf9
+ 25f9f5b7a7740986.5d6f5b36bc21b198.af4db734322e54a4.d8c2d64a2c6f0c6e
+ 8873b89da5f32a71.0f3173cc77e0a976.6f73bb9b0c00be28.6b9125870fcbceb3
+ 35b864f229326bf5
+ after
+ 92787629f151242a.36b58705e7624123.1941fe431a53c1d2.e8fb19aa9da63029
+ f21433b54a6dc6fd.b3df3697eba578e0.b156773b6bce696b.a17efb4f65126cf9
+ 25f9f5b7a7740986.5d6f5b36bc21b198.af4db734322e54a4.d8c2d64a2c6f0c6e
+ 8873b89da5f32a71.0f3173cc77e0a976.6f73bb9b0c00be28.6b9125870fcbceb3
+ 00000000b156773b
+VEXTRACTPS_0x3(mem)
+ before
+ 1203107797aea260.78ce79d1df756569.a7f0f94738f01ca6.4d147dda95cee5a4
+ dd3da303744d2d1f.4f5533c1f286f51b.007969921a5dc556.a57bfb5f682703c4
+ 74349b80dd1bc95e.6a56e2d779b31832.f5983f98393261b0.d2f6309421945533
+ b1b273dced23324b.261b82811187085b.6419f747b27bace0.32cf18e75da3169e
+ 2053b0c3b8df83b0
+ after
+ 1203107797aea260.78ce79d1df756569.a7f0f94738f01ca6.4d147dda00796992
+ dd3da303744d2d1f.4f5533c1f286f51b.007969921a5dc556.a57bfb5f682703c4
+ 74349b80dd1bc95e.6a56e2d779b31832.f5983f98393261b0.d2f6309421945533
+ b1b273dced23324b.261b82811187085b.6419f747b27bace0.32cf18e75da3169e
+ 2053b0c3b8df83b0
+
+VEXTRACTPS_0x3(reg)
+ before
+ f8cef294cdd5d816.7285a701c1712310.ddf1102a558e0142.28c80e8aa1446213
+ 158cdcc63810517c.9177b4dd741159d9.ec24873ee2554092.1c71ff4d219a3e75
+ d5d969c5961c298d.ec55145b221090d3.af00e329536702f8.1edf467d4e88fd31
+ 920196fd82859ef5.5dea4566e879842a.82d120574450801f.08e05f04451a5b74
+ b73ec6cf215d136a
+ after
+ f8cef294cdd5d816.7285a701c1712310.ddf1102a558e0142.28c80e8aa1446213
+ 158cdcc63810517c.9177b4dd741159d9.ec24873ee2554092.1c71ff4d219a3e75
+ d5d969c5961c298d.ec55145b221090d3.af00e329536702f8.1edf467d4e88fd31
+ 920196fd82859ef5.5dea4566e879842a.82d120574450801f.08e05f04451a5b74
+ 00000000ec24873e
+VEXTRACTPS_0x3(mem)
+ before
+ 08c6f8cbff5ce23e.aa4f5ddb99d8e962.c204c2ece258f009.c1e23a35539df9b4
+ d54470e2fa24841c.7710bcc976a1497e.f56d08d82bba919d.c8812e2d19d9a763
+ fc83aa022fc0b532.5790ae35b66af8f5.d4f39117dfaa2311.f3f8f7ad3491c7d7
+ 57512316b93c30aa.a41b2f89f4c13374.3960db931b356193.9e94911f3f4f95bd
+ 25a1f8f1d7a14cc0
+ after
+ 08c6f8cbff5ce23e.aa4f5ddb99d8e962.c204c2ece258f009.c1e23a35f56d08d8
+ d54470e2fa24841c.7710bcc976a1497e.f56d08d82bba919d.c8812e2d19d9a763
+ fc83aa022fc0b532.5790ae35b66af8f5.d4f39117dfaa2311.f3f8f7ad3491c7d7
+ 57512316b93c30aa.a41b2f89f4c13374.3960db931b356193.9e94911f3f4f95bd
+ 25a1f8f1d7a14cc0
+
+VEXTRACTPS_0x3(reg)
+ before
+ e46a298e9813298d.c378550ab5a4b2b0.bcfd3c33cd3136a7.01816139fb66094c
+ 373d1e611d3068d0.1cc6beca3e05f771.f982cf9edc473c39.08219ff59a49d46a
+ 7a64d5d802844434.3f05d942706aba19.b8f5e636bd8e83d7.2b0e12b414ea8119
+ 082d4a5ee49bfb66.0602225e68e0b9d3.56a47c670d92452c.441334618656ca85
+ 30fb83e70b986cd9
+ after
+ e46a298e9813298d.c378550ab5a4b2b0.bcfd3c33cd3136a7.01816139fb66094c
+ 373d1e611d3068d0.1cc6beca3e05f771.f982cf9edc473c39.08219ff59a49d46a
+ 7a64d5d802844434.3f05d942706aba19.b8f5e636bd8e83d7.2b0e12b414ea8119
+ 082d4a5ee49bfb66.0602225e68e0b9d3.56a47c670d92452c.441334618656ca85
+ 00000000f982cf9e
+VEXTRACTPS_0x3(mem)
+ before
+ cb937a34c0bd2341.3fe277605e02c711.4e88160a4272adcc.2dd98d9d68e0bee5
+ f1a79533c0d0abeb.7ad05a480d44e4e2.f3652f32192c552f.9ae1164469032bae
+ 7e0351d028ddbf00.1542ed838cee9085.d163ebc3091a6b29.fa0812c8ac87c832
+ 4e7329f713f11caf.6b862f7e778b05a5.c450c5a72f49ade6.a7997d96cef9d11e
+ fee253186be4821e
+ after
+ cb937a34c0bd2341.3fe277605e02c711.4e88160a4272adcc.2dd98d9df3652f32
+ f1a79533c0d0abeb.7ad05a480d44e4e2.f3652f32192c552f.9ae1164469032bae
+ 7e0351d028ddbf00.1542ed838cee9085.d163ebc3091a6b29.fa0812c8ac87c832
+ 4e7329f713f11caf.6b862f7e778b05a5.c450c5a72f49ade6.a7997d96cef9d11e
+ fee253186be4821e
+
+VLDDQU_128(reg)
+ before
+ 5b2d90bc1ed516dd.3dc299949d177d22.dae719a36ca780ee.a8f63acca6c5d491
+ 1ac831ec8356ca07.27be1d93e45ba085.bdb0a86004cf3c0e.5922c41d8b989f57
+ 97fd311637f5d949.e83131e101c93f05.6f2ed91fdd8d76af.b3a0e186fad0c863
+ 2e198ca5d53e814f.5ce85268126e17ce.4eada74e93706a7d.923b0cf20d780ce2
+ d2c1c14fe39d2700
+ after
+ 5b2d90bc1ed516dd.3dc299949d177d22.dae719a36ca780ee.a8f63acca6c5d491
+ 1ac831ec8356ca07.27be1d93e45ba085.bdb0a86004cf3c0e.5922c41d8b989f57
+ 97fd311637f5d949.e83131e101c93f05.6f2ed91fdd8d76af.b3a0e186fad0c863
+ 2e198ca5d53e814f.5ce85268126e17ce.4eada74e93706a7d.923b0cf20d780ce2
+ d2c1c14fe39d2700
+VLDDQU_128(mem)
+ before
+ 4ffc7d88954ad4e8.3b673e05fabcfcc5.5faffb163356e30c.b4790e58c1015425
+ e5b9ba8a428bd0c7.1a3543a241fb8756.cd52a8d57f8b60ea.ffde0aa903ce7053
+ 70c4f63f036dd7c8.27cd98e847875dae.829cd593121b4a94.892798adf662f9b2
+ cbe9ac94f6fba418.be7d3843a7edbb7a.5a5bfe3b09125d37.b0a2b3d0364a2cef
+ ce99577f5d1144b5
+ after
+ 4ffc7d88954ad4e8.3b673e05fabcfcc5.5faffb163356e30c.b4790e58c1015425
+ 0000000000000000.0000000000000000.c55faffb163356e3.0cb4790e58c10154
+ 70c4f63f036dd7c8.27cd98e847875dae.829cd593121b4a94.892798adf662f9b2
+ cbe9ac94f6fba418.be7d3843a7edbb7a.5a5bfe3b09125d37.b0a2b3d0364a2cef
+ ce99577f5d1144b5
+
+VLDDQU_128(reg)
+ before
+ 405980240a437eb2.d4f459763741f5e2.3b8f1f20fdb8dd66.3059a0b97f7a54ff
+ 632e2b2cd76d168f.66b177cfe14c8453.fa5049e9e675ff1d.e26336f99161ed17
+ 91645204601a48fa.5deb848d11270d97.570cb30bfeae5c4c.4b453ce75ad3e1ac
+ 2746f31742d6509f.946ffb9be2de4eda.ad0e58f3e0f2319f.47cb2e6ff7daefea
+ b1c1897d8385d1fc
+ after
+ 405980240a437eb2.d4f459763741f5e2.3b8f1f20fdb8dd66.3059a0b97f7a54ff
+ 632e2b2cd76d168f.66b177cfe14c8453.fa5049e9e675ff1d.e26336f99161ed17
+ 91645204601a48fa.5deb848d11270d97.570cb30bfeae5c4c.4b453ce75ad3e1ac
+ 2746f31742d6509f.946ffb9be2de4eda.ad0e58f3e0f2319f.47cb2e6ff7daefea
+ b1c1897d8385d1fc
+VLDDQU_128(mem)
+ before
+ 67f2c8fe1bdd440f.822209d0182e692a.e90958e5707e0146.5aa4340c28cabac1
+ 432c67dcdaf0044e.fc42919d7eadd046.37851856d812e30a.b91843c273c4335f
+ 2339e205ddc9cce6.f2f385e912dfc09f.59afb5dc35a7af50.26b881805d6bd724
+ e1e6b6633f745902.c081e3206d5177e3.2d53ad63a4472345.fcceebb4814ce3bd
+ 99a77cc97bf293d6
+ after
+ 67f2c8fe1bdd440f.822209d0182e692a.e90958e5707e0146.5aa4340c28cabac1
+ 0000000000000000.0000000000000000.2ae90958e5707e01.465aa4340c28caba
+ 2339e205ddc9cce6.f2f385e912dfc09f.59afb5dc35a7af50.26b881805d6bd724
+ e1e6b6633f745902.c081e3206d5177e3.2d53ad63a4472345.fcceebb4814ce3bd
+ 99a77cc97bf293d6
+
+VLDDQU_128(reg)
+ before
+ 588e302ce8e9221a.5bff5de41dfe67cf.c238a6ae2d8e2fbb.8d3c7bd54101f914
+ 94d1034763bdcd35.6b5055739272b279.5463caffee2325d6.57389b1f26deedea
+ abbaf28789fbd0d5.efa419fcbaddf52b.d2504b804b9a94de.65118a2d72ecbdf2
+ f797f859f52f67a4.c1c9256bb249ed12.9849269be081b97f.9494c3ec3e362359
+ c18dc147a9c8dc4b
+ after
+ 588e302ce8e9221a.5bff5de41dfe67cf.c238a6ae2d8e2fbb.8d3c7bd54101f914
+ 94d1034763bdcd35.6b5055739272b279.5463caffee2325d6.57389b1f26deedea
+ abbaf28789fbd0d5.efa419fcbaddf52b.d2504b804b9a94de.65118a2d72ecbdf2
+ f797f859f52f67a4.c1c9256bb249ed12.9849269be081b97f.9494c3ec3e362359
+ c18dc147a9c8dc4b
+VLDDQU_128(mem)
+ before
+ c6c70329ccafa3f3.d6b2112744e3cd4e.bf89f6ac96c4565a.029c56bd4a64d067
+ 80100280c6f6367e.a258395f11a53f80.c3b107ab815aeb2e.6c93d75325ce153f
+ cc323c37b0aa4f18.b9d46c6bf900f9e6.aa0dd4558f166aba.327aa5c80c4bc3b6
+ 84fb2b3aa8d6aaec.7574a7b99781362b.5069d994dd048c2c.b09fbd879b671776
+ 424d1afe6faf4d2b
+ after
+ c6c70329ccafa3f3.d6b2112744e3cd4e.bf89f6ac96c4565a.029c56bd4a64d067
+ 0000000000000000.0000000000000000.4ebf89f6ac96c456.5a029c56bd4a64d0
+ cc323c37b0aa4f18.b9d46c6bf900f9e6.aa0dd4558f166aba.327aa5c80c4bc3b6
+ 84fb2b3aa8d6aaec.7574a7b99781362b.5069d994dd048c2c.b09fbd879b671776
+ 424d1afe6faf4d2b
+
+VLDDQU_256(reg)
+ before
+ 44cfb89823aea182.85354d75ca860526.3383e5b487b333fc.92919256863010ad
+ 127293c154f14e27.abad1ed431c61af4.504c22c866222c04.4a507c85a7a7b06c
+ 0882a7e59d0391c6.d32e1843f9a3a67f.261c5a61d05b5df0.5574120f5b752993
+ 814bf1719b70a509.d786b9af3f2865f6.123f8aeb60e9016c.8fc7d0dfbfa4374f
+ d41632e0ee4296cb
+ after
+ 44cfb89823aea182.85354d75ca860526.3383e5b487b333fc.92919256863010ad
+ 127293c154f14e27.abad1ed431c61af4.504c22c866222c04.4a507c85a7a7b06c
+ 0882a7e59d0391c6.d32e1843f9a3a67f.261c5a61d05b5df0.5574120f5b752993
+ 814bf1719b70a509.d786b9af3f2865f6.123f8aeb60e9016c.8fc7d0dfbfa4374f
+ d41632e0ee4296cb
+VLDDQU_256(mem)
+ before
+ 002db500055a0134.db196ccfe9c4c89f.947f7c021f621283.7001acd3b2585523
+ efd7d32b1ff935b5.7138146c248c3432.e6e7dd29b45c6a52.9daebe83633595c2
+ 7ee20a4b592aed7b.9ef3e5b5e753266f.a98858111a222991.f391bb690f0bfcf5
+ 8618d64dcef9e7b1.c098db15cfa6d901.b92f6aa56ec10a69.cff8a0ef5066c867
+ 8d2d6783c5d333c4
+ after
+ 002db500055a0134.db196ccfe9c4c89f.947f7c021f621283.7001acd3b2585523
+ c2002db500055a01.34db196ccfe9c4c8.9f947f7c021f6212.837001acd3b25855
+ 7ee20a4b592aed7b.9ef3e5b5e753266f.a98858111a222991.f391bb690f0bfcf5
+ 8618d64dcef9e7b1.c098db15cfa6d901.b92f6aa56ec10a69.cff8a0ef5066c867
+ 8d2d6783c5d333c4
+
+VLDDQU_256(reg)
+ before
+ 897d0e8f08dd79b9.e647b11d9a73dd85.3271f3f777108b95.f2a88ed1cb44cb09
+ 1f349081b511d8f2.793919a8daa38c20.4fcb28c97b1d76d7.30be40814eb7259b
+ ab9ee9c469f98a1b.1bbb88d8aa95afb1.75f276f6785ad672.4f3ffca01227d74b
+ 890616c4bf24cbdf.a8987c9b25560362.fe31daea0a52e912.2bf53e1d349f9b46
+ 9fad83e1cf2b2fb8
+ after
+ 897d0e8f08dd79b9.e647b11d9a73dd85.3271f3f777108b95.f2a88ed1cb44cb09
+ 1f349081b511d8f2.793919a8daa38c20.4fcb28c97b1d76d7.30be40814eb7259b
+ ab9ee9c469f98a1b.1bbb88d8aa95afb1.75f276f6785ad672.4f3ffca01227d74b
+ 890616c4bf24cbdf.a8987c9b25560362.fe31daea0a52e912.2bf53e1d349f9b46
+ 9fad83e1cf2b2fb8
+VLDDQU_256(mem)
+ before
+ 893346d900d84ccd.15ba12ed531bd9ea.fc9e71dc67f1445f.48d64e11cc91e965
+ c45303f1e2b1b1b0.ab04d9acc36ceee9.f397e1868d722ed5.ad2bd0d75aa41314
+ 2cd9361692c2188d.a731676ba8a24788.69514a87b2e67cf0.8a7e5ba85115a2ce
+ 9c915c322b183e91.658db897a0492072.399627caf358ecdc.3c19ebf14c73d43d
+ 1d497d1ce847e30e
+ after
+ 893346d900d84ccd.15ba12ed531bd9ea.fc9e71dc67f1445f.48d64e11cc91e965
+ 14893346d900d84c.cd15ba12ed531bd9.eafc9e71dc67f144.5f48d64e11cc91e9
+ 2cd9361692c2188d.a731676ba8a24788.69514a87b2e67cf0.8a7e5ba85115a2ce
+ 9c915c322b183e91.658db897a0492072.399627caf358ecdc.3c19ebf14c73d43d
+ 1d497d1ce847e30e
+
+VLDDQU_256(reg)
+ before
+ 8a590b97c01f0bec.f246ef33c9bedfe8.4164c99d47eeb454.4133f43b6cd437c3
+ e09793cc71878a84.09c56d0489c0b6bd.960294e7381c40da.5cf42dc737671cd4
+ 794d102996099a81.bcda5291872b803d.c2b217e30f6000af.65a44f58731c5539
+ b2c97f19cc337890.e95118c6de0af994.20c24efc69453080.3a11d5db39ff9f1f
+ b5053b3da71db6b1
+ after
+ 8a590b97c01f0bec.f246ef33c9bedfe8.4164c99d47eeb454.4133f43b6cd437c3
+ e09793cc71878a84.09c56d0489c0b6bd.960294e7381c40da.5cf42dc737671cd4
+ 794d102996099a81.bcda5291872b803d.c2b217e30f6000af.65a44f58731c5539
+ b2c97f19cc337890.e95118c6de0af994.20c24efc69453080.3a11d5db39ff9f1f
+ b5053b3da71db6b1
+VLDDQU_256(mem)
+ before
+ b44efd68d981551c.e755da08ae91605d.6bf63d8faa69dded.0b7c339ee2570bf8
+ 12b6974aea37398c.743e1f62d9ae8d93.1d953bd80855e774.e12dc4351523cec4
+ aa0a86cef74c1e2c.b6d04993e8163cdf.ddf9908d13d9d457.fd21fc2d9e33b590
+ 591545e01bcbc028.075654077755a9ec.85f0b89ae80260c0.baa4d7f21a16fb07
+ 760151f02455ddd5
+ after
+ b44efd68d981551c.e755da08ae91605d.6bf63d8faa69dded.0b7c339ee2570bf8
+ c4b44efd68d98155.1ce755da08ae9160.5d6bf63d8faa69dd.ed0b7c339ee2570b
+ aa0a86cef74c1e2c.b6d04993e8163cdf.ddf9908d13d9d457.fd21fc2d9e33b590
+ 591545e01bcbc028.075654077755a9ec.85f0b89ae80260c0.baa4d7f21a16fb07
+ 760151f02455ddd5
+
+VMAXPS_256(reg)
+ before
+ 8c866693597e97a8.fca5506c72c1daae.c41e3d2a23f80f67.f3442deca2da46db
+ 577d1348541c642a.6d84235e193829e7.4972fe69888aabfc.01c26d6d5e7043d5
+ 34335379b2bc8207.8a803ba22c3f6902.f29f952e4197b956.8c36f30b37cd13da
+ 80f422940ee92bec.2d631324c6df5529.1bf1fde7eaac7522.716b3bb04aff7215
+ 8a2fc14ab2111bb3
+ after
+ 577d1348541c642a.6d84235e193829e7.4972fe69888aabfc.716b3bb05e7043d5
+ 577d1348541c642a.6d84235e193829e7.4972fe69888aabfc.01c26d6d5e7043d5
+ 34335379b2bc8207.8a803ba22c3f6902.f29f952e4197b956.8c36f30b37cd13da
+ 80f422940ee92bec.2d631324c6df5529.1bf1fde7eaac7522.716b3bb04aff7215
+ 8a2fc14ab2111bb3
+VMAXPS_256(mem)
+ before
+ b44c02c48c0fcbdf.950c7d04052f9b85.33fa27d00326ab89.20b432ff20541a0b
+ cc90790af3063ec6.d1c65e35321b107d.7911f393001f244d.5d3431e17f1ce6be
+ acc5a20804022f94.8e70c3923138c481.d973f357d8d77fa2.2dbcf5fba18e12e7
+ 31b8f9aada0d5c74.2954a7899f12f43c.30eea40aa85876b3.ee9a7ab82539dd31
+ fb18bc84a4a68149
+ after
+ b44c02c48c0fcbdf.950c7d04052f9b85.33fa27d00326ab89.20b432ff20541a0b
+ cc90790af3063ec6.d1c65e35321b107d.7911f393001f244d.5d3431e17f1ce6be
+ b44c02c48c0fcbdf.950c7d04321b107d.7911f3930326ab89.5d3431e17f1ce6be
+ 31b8f9aada0d5c74.2954a7899f12f43c.30eea40aa85876b3.ee9a7ab82539dd31
+ fb18bc84a4a68149
+
+VMAXPS_256(reg)
+ before
+ b083b7cbbd633bda.3734fbdc91357e93.ffbf07861836dc5b.5a4c81968bb1c6ad
+ 692768fa09fb4791.9a07228b4685541d.6afdddf3372fb78a.335a06e99eeb2bbc
+ 8150ca7b27fbe019.36fbeca1150a983d.c75a273d9889c274.97e4afeefc14610b
+ 564ad9bbb0ee4320.e7ded40c18cf081f.7222e0d0d8d139c6.62b6f991c23723c7
+ 719c5ebe0b612e1b
+ after
+ 692768fa09fb4791.9a07228b4685541d.7222e0d0372fb78a.62b6f9919eeb2bbc
+ 692768fa09fb4791.9a07228b4685541d.6afdddf3372fb78a.335a06e99eeb2bbc
+ 8150ca7b27fbe019.36fbeca1150a983d.c75a273d9889c274.97e4afeefc14610b
+ 564ad9bbb0ee4320.e7ded40c18cf081f.7222e0d0d8d139c6.62b6f991c23723c7
+ 719c5ebe0b612e1b
+VMAXPS_256(mem)
+ before
+ 9e615c61f49d3d34.436091274260ac4f.897a57b66ee05df0.c8a104199392572b
+ c6d36e6798f70e3e.a3dfee2979dd5755.f89cef8d314956dc.23228f8263585950
+ c5bc11ba137c5b64.d414ed2ff0f27fdc.10101a7c7d17ad0e.e0f27e79e7b07be1
+ 76e9bf478237e1d3.304989a4442a6190.ada1536f6f561fb3.5b5dcc69b925f989
+ f0af75be75440ef5
+ after
+ 9e615c61f49d3d34.436091274260ac4f.897a57b66ee05df0.c8a104199392572b
+ c6d36e6798f70e3e.a3dfee2979dd5755.f89cef8d314956dc.23228f8263585950
+ 9e615c6198f70e3e.4360912779dd5755.897a57b66ee05df0.23228f8263585950
+ 76e9bf478237e1d3.304989a4442a6190.ada1536f6f561fb3.5b5dcc69b925f989
+ f0af75be75440ef5
+
+VMAXPS_256(reg)
+ before
+ fb3475e4b897f7d0.b726f6fb01345bb6.15cabef41012391e.ab1d1652221068f7
+ d838c9471dacf0c7.633f31c0ab80863a.dde5898bf0354232.e64ee011b3534305
+ e3066b53400f3586.5600ed849c261e8b.e6e5e4d5811fb977.3a012b983d2b6d0a
+ 78eb5974bf4b01b8.6c34a432f132dfd4.8a15cd3e5e5dda9a.830375d3dda2a231
+ 9d1d39aeaec69da7
+ after
+ 78eb59741dacf0c7.6c34a432ab80863a.8a15cd3e5e5dda9a.830375d3b3534305
+ d838c9471dacf0c7.633f31c0ab80863a.dde5898bf0354232.e64ee011b3534305
+ e3066b53400f3586.5600ed849c261e8b.e6e5e4d5811fb977.3a012b983d2b6d0a
+ 78eb5974bf4b01b8.6c34a432f132dfd4.8a15cd3e5e5dda9a.830375d3dda2a231
+ 9d1d39aeaec69da7
+VMAXPS_256(mem)
+ before
+ 631ef316cca31c98.f3338e1633ec910a.81a8d4b6c6b18441.27c23f32247ae146
+ b3d120f55443d92f.af2a07a63a7e2027.7028f8fc35aecb00.1738361e6f020928
+ 68013b3962b49099.0a1cbe8e708eecbc.17808cf05d356d3b.b7c3af6cd9828fec
+ 5d7bc0cd1102ff01.5f55b13c70a72f75.517c0c7e5853291e.64afa48a0185af3d
+ 784813e28097a4c8
+ after
+ 631ef316cca31c98.f3338e1633ec910a.81a8d4b6c6b18441.27c23f32247ae146
+ b3d120f55443d92f.af2a07a63a7e2027.7028f8fc35aecb00.1738361e6f020928
+ 631ef3165443d92f.af2a07a63a7e2027.7028f8fc35aecb00.27c23f326f020928
+ 5d7bc0cd1102ff01.5f55b13c70a72f75.517c0c7e5853291e.64afa48a0185af3d
+ 784813e28097a4c8
+
+VMAXPD_128(reg)
+ before
+ 50d9f7e2f545ab39.700c2b9d7d37e094.0a21db1ad65626fd.f9e8f5924213b9d6
+ 48af4df5f91a003b.7c7df895c362f07d.67cb38963f260c01.ed90c2193781da8f
+ bd170f872ba2df7a.5c9da4a1ff8ceae9.d1a0c51b47a31f2c.083feffd55aa4874
+ 095b3b04246a83a4.ee37aaad4cc38c04.a6ec7c158959992b.25c2f82cb599beb2
+ 22e55991755af975
+ after
+ 0000000000000000.0000000000000000.67cb38963f260c01.25c2f82cb599beb2
+ 48af4df5f91a003b.7c7df895c362f07d.67cb38963f260c01.ed90c2193781da8f
+ bd170f872ba2df7a.5c9da4a1ff8ceae9.d1a0c51b47a31f2c.083feffd55aa4874
+ 095b3b04246a83a4.ee37aaad4cc38c04.a6ec7c158959992b.25c2f82cb599beb2
+ 22e55991755af975
+VMAXPD_128(mem)
+ before
+ d9748f17b1fab5e8.89c7ccd882fd2962.0c1686a5c61290f9.41fb5bf0a1d5b6a9
+ 283b15ac8484ae37.99a9be6fe1e70d63.9408b4758a85b2f5.fd195d182ca3b454
+ e905673b0b059f90.954c0e35dcb56b51.60d7b10ab329b024.38917ff9c54dcdd5
+ f9a001b06188451d.d9fbb6970ff27ed8.4e50f74e5e0944b1.4cb1bb0009613edb
+ 97c30f97936a420f
+ after
+ d9748f17b1fab5e8.89c7ccd882fd2962.0c1686a5c61290f9.41fb5bf0a1d5b6a9
+ 283b15ac8484ae37.99a9be6fe1e70d63.9408b4758a85b2f5.fd195d182ca3b454
+ 0000000000000000.0000000000000000.0c1686a5c61290f9.41fb5bf0a1d5b6a9
+ f9a001b06188451d.d9fbb6970ff27ed8.4e50f74e5e0944b1.4cb1bb0009613edb
+ 97c30f97936a420f
+
+VMAXPD_128(reg)
+ before
+ 7314762c00f51720.35d660f7a2195c0a.c103b4ff172b83a6.383f042fa6322bc9
+ 3ef0ec29eb8df7b8.7774fffcebc49f84.a9b003db90eab564.fb6f5397a8ae2097
+ 52a36dfcf0be1e84.9c465aac5796ccb7.ed4ea09515be52c1.74ae61747f8ce148
+ 0d79f610ad15ca2f.8118edf1039a9cce.e929859b42309467.7dc6a8b148d52807
+ f385a63a1e97b101
+ after
+ 0000000000000000.0000000000000000.a9b003db90eab564.7dc6a8b148d52807
+ 3ef0ec29eb8df7b8.7774fffcebc49f84.a9b003db90eab564.fb6f5397a8ae2097
+ 52a36dfcf0be1e84.9c465aac5796ccb7.ed4ea09515be52c1.74ae61747f8ce148
+ 0d79f610ad15ca2f.8118edf1039a9cce.e929859b42309467.7dc6a8b148d52807
+ f385a63a1e97b101
+VMAXPD_128(mem)
+ before
+ b2b5d6fb1ddd3a62.c9bd82d1bb1d3566.00b634b90bddcef6.f98cb058b4ceb802
+ 9723b4e062b47d55.e3bc0dabb8629cd4.f6ebacee896a1c5a.79c51c380623f93f
+ 7c9abdd509273707.b8c3930a40713a26.3f85d07e9c4d4327.c41ec5a7d5bc94ca
+ 3ee86cc72d4224a3.a21c115aeed54d08.b74e1c545d92ff89.38e4a711bc23c54e
+ 3063bfe258e7c878
+ after
+ b2b5d6fb1ddd3a62.c9bd82d1bb1d3566.00b634b90bddcef6.f98cb058b4ceb802
+ 9723b4e062b47d55.e3bc0dabb8629cd4.f6ebacee896a1c5a.79c51c380623f93f
+ 0000000000000000.0000000000000000.00b634b90bddcef6.79c51c380623f93f
+ 3ee86cc72d4224a3.a21c115aeed54d08.b74e1c545d92ff89.38e4a711bc23c54e
+ 3063bfe258e7c878
+
+VMAXPD_128(reg)
+ before
+ 08e708874491d8f4.b9d73ca0ea11ff56.fe1481075e1a0f25.3a130c5ceb460cab
+ 1bbb7e6a1daf326d.c935ac4e5da1854c.28f6e17e2dcdbc2a.a5a01c825f7525ba
+ c72d1df97ecc1290.4acc35bba1fe72b0.7c102d29f67992c2.d2c0c9b2d72907e1
+ 6787e29e0375b408.186954d5d33281af.56ac5f7656aacb9a.9e418ed86f706d4d
+ e5ede7e04255152a
+ after
+ 0000000000000000.0000000000000000.56ac5f7656aacb9a.9e418ed86f706d4d
+ 1bbb7e6a1daf326d.c935ac4e5da1854c.28f6e17e2dcdbc2a.a5a01c825f7525ba
+ c72d1df97ecc1290.4acc35bba1fe72b0.7c102d29f67992c2.d2c0c9b2d72907e1
+ 6787e29e0375b408.186954d5d33281af.56ac5f7656aacb9a.9e418ed86f706d4d
+ e5ede7e04255152a
+VMAXPD_128(mem)
+ before
+ 839251b66de5b9a3.5616c7c749355382.0fd886870f4b6f74.131775cfe9eda45e
+ 53fa46470b2b16e5.f226cadfec982ca9.0be446bd6f54f82c.0d9e69a249cd59b9
+ 33f2447d3833e71b.9503e652872a7b2b.e85b1063125ad803.a18a395a15d72558
+ fe45c646110ae972.9df9188cb6787bb1.820761651168ca24.2b2ae163e69545e6
+ 07c95b295b95f510
+ after
+ 839251b66de5b9a3.5616c7c749355382.0fd886870f4b6f74.131775cfe9eda45e
+ 53fa46470b2b16e5.f226cadfec982ca9.0be446bd6f54f82c.0d9e69a249cd59b9
+ 0000000000000000.0000000000000000.0fd886870f4b6f74.131775cfe9eda45e
+ fe45c646110ae972.9df9188cb6787bb1.820761651168ca24.2b2ae163e69545e6
+ 07c95b295b95f510
+
+VMAXPD_256(reg)
+ before
+ 91b2a5180d637082.90c1488db2bbd816.64535af9160e69ea.b5b5b4af8b8a8cbc
+ 2533ba9c9a8af4e7.c530473e35527032.485faa054376817f.5c32842d99cdd7f6
+ 1e9696229e96bbec.79603e45b9dc6cf3.a367031cd83eff1f.554750cc593c6aff
+ da283514b413013c.871ba98e58648a84.d2b861aa71f21e74.7bc39176e7e3ff02
+ aa71c4195ecf532d
+ after
+ 2533ba9c9a8af4e7.871ba98e58648a84.485faa054376817f.7bc39176e7e3ff02
+ 2533ba9c9a8af4e7.c530473e35527032.485faa054376817f.5c32842d99cdd7f6
+ 1e9696229e96bbec.79603e45b9dc6cf3.a367031cd83eff1f.554750cc593c6aff
+ da283514b413013c.871ba98e58648a84.d2b861aa71f21e74.7bc39176e7e3ff02
+ aa71c4195ecf532d
+VMAXPD_256(mem)
+ before
+ bd1c669fdb0b22a9.b43594df798e0484.cd2e04052ef68312.329ec11cab1c1b2b
+ 9291f2f679a327a5.0808aef08892fe70.2665cb96589f16c8.1d651edc214a32ef
+ 049de40954a41f4b.32ef7fb27dac2cab.6d8b7b2df16afdd4.f058735870089e6d
+ ee09b9c48919c6c7.8d340391f567c9e2.806e8eb61663f55f.08c5bffb33e09d50
+ bff6fb3107606845
+ after
+ bd1c669fdb0b22a9.b43594df798e0484.cd2e04052ef68312.329ec11cab1c1b2b
+ 9291f2f679a327a5.0808aef08892fe70.2665cb96589f16c8.1d651edc214a32ef
+ 9291f2f679a327a5.0808aef08892fe70.2665cb96589f16c8.329ec11cab1c1b2b
+ ee09b9c48919c6c7.8d340391f567c9e2.806e8eb61663f55f.08c5bffb33e09d50
+ bff6fb3107606845
+
+VMAXPD_256(reg)
+ before
+ 7238246687143ef8.2ea4eb13330fd846.772436f88c4f12c0.3ad8821ee297ba98
+ 7dd7370650865914.9e39f8e26f9010f4.4b0b1555dcf043f2.7697d34f711107a8
+ 3c1f2f7dfd44f646.1c935b1d59aa2bfc.64359b1384d79823.1275fb37e1de99be
+ 0b5c08372ada5139.828090b00b69e58b.20eec49f1e8f4c01.e83f78c14b082c04
+ d6c0c5d9cd9d7ca7
+ after
+ 7dd7370650865914.828090b00b69e58b.4b0b1555dcf043f2.7697d34f711107a8
+ 7dd7370650865914.9e39f8e26f9010f4.4b0b1555dcf043f2.7697d34f711107a8
+ 3c1f2f7dfd44f646.1c935b1d59aa2bfc.64359b1384d79823.1275fb37e1de99be
+ 0b5c08372ada5139.828090b00b69e58b.20eec49f1e8f4c01.e83f78c14b082c04
+ d6c0c5d9cd9d7ca7
+VMAXPD_256(mem)
+ before
+ b6c65e6b83a944d2.46d9bfa074d3a69a.aeca1488a4d8f9cd.da828c6346a59d35
+ 651bbf63883741b2.49e44e2477bb3015.7a3e628f3e0324ed.ed3cf0cc99a4c46e
+ c08d65adf8532f72.70c7b330ce1e2c55.c3a8f6b3f5f62217.b769ea47b2180055
+ a1e6ca35f009c93f.17cfe92f1589d607.66d34cdee5beaf79.9255783e2e8e8b99
+ dc4c961fa891a2e4
+ after
+ b6c65e6b83a944d2.46d9bfa074d3a69a.aeca1488a4d8f9cd.da828c6346a59d35
+ 651bbf63883741b2.49e44e2477bb3015.7a3e628f3e0324ed.ed3cf0cc99a4c46e
+ 651bbf63883741b2.49e44e2477bb3015.7a3e628f3e0324ed.da828c6346a59d35
+ a1e6ca35f009c93f.17cfe92f1589d607.66d34cdee5beaf79.9255783e2e8e8b99
+ dc4c961fa891a2e4
+
+VMAXPD_256(reg)
+ before
+ ef9a3e54bcad81e3.e5f36ce78b66cd45.9a48ed8ce98769d6.3d8de0fe2c66863c
+ 288b6e4b086f6341.6980c7b0e675f4af.557db9b5e5a4226f.25a02ffee3fb648f
+ e46a216f256286ab.0758557a1d43fdaa.a4bc4b15a66d3d7e.fbdab4ca2888059c
+ 7d85532cb11223cc.9c4994334bdba262.e34f9e18c86df5ae.9905eb4e1719248f
+ dcee5076cbba7f96
+ after
+ 7d85532cb11223cc.6980c7b0e675f4af.557db9b5e5a4226f.25a02ffee3fb648f
+ 288b6e4b086f6341.6980c7b0e675f4af.557db9b5e5a4226f.25a02ffee3fb648f
+ e46a216f256286ab.0758557a1d43fdaa.a4bc4b15a66d3d7e.fbdab4ca2888059c
+ 7d85532cb11223cc.9c4994334bdba262.e34f9e18c86df5ae.9905eb4e1719248f
+ dcee5076cbba7f96
+VMAXPD_256(mem)
+ before
+ a0605f2e6078cfdb.502600ee480c7951.041dfec68c49a002.6e84ae2ae53188ac
+ c1299563f35ed38a.ba9a242185dbc2e6.1ba1121efd9ab3b6.a0a577b79c443023
+ 1b136dffa07945d0.152dbc32040b3b36.bea14929b9d897ab.d7fff62b863229c0
+ 8bec63f082d4e2d9.be2bc38b622920ee.c7e920d2dc12070d.6ede26f34187b12e
+ c18d037969d0021a
+ after
+ a0605f2e6078cfdb.502600ee480c7951.041dfec68c49a002.6e84ae2ae53188ac
+ c1299563f35ed38a.ba9a242185dbc2e6.1ba1121efd9ab3b6.a0a577b79c443023
+ a0605f2e6078cfdb.502600ee480c7951.1ba1121efd9ab3b6.6e84ae2ae53188ac
+ 8bec63f082d4e2d9.be2bc38b622920ee.c7e920d2dc12070d.6ede26f34187b12e
+ c18d037969d0021a
+
+VMINPS_256(reg)
+ before
+ 2b5a892a99995930.eb7ef320b57b66d0.11df359a3ac0adb9.134514058451c008
+ 0a8fb5736e6cf11c.18969a7d567b8de2.6a960fc9295c1d44.7e80a0aecaa37dc7
+ b87981bf83d70788.ee00d3f280df123a.259d4b86cb8aad3b.e46840bacc13fc76
+ 9364eb7a7465d723.48871a6b50b3b205.9e3ee73bbad59849.21c77113a6aef742
+ 116aada6737f2b57
+ after
+ 9364eb7a6e6cf11c.18969a7d50b3b205.9e3ee73bbad59849.21c77113caa37dc7
+ 0a8fb5736e6cf11c.18969a7d567b8de2.6a960fc9295c1d44.7e80a0aecaa37dc7
+ b87981bf83d70788.ee00d3f280df123a.259d4b86cb8aad3b.e46840bacc13fc76
+ 9364eb7a7465d723.48871a6b50b3b205.9e3ee73bbad59849.21c77113a6aef742
+ 116aada6737f2b57
+VMINPS_256(mem)
+ before
+ 8f1d72604f9253e0.f69cef0fdea39d97.04f9ebd4e104296e.32c6de5695c91c1b
+ 79ac3b2c57f42c0a.3c6d87ec5d1c9591.fd20c21950dd32a3.3b812c42f5f3735c
+ aae384f5a7b07201.c222b07c8c5cfabc.0fca1c26b84a8acd.16bace6b79dedab9
+ fe8dcaa95ad2e1f0.e509672c07f009c5.16c174e73658ed1b.1ebfbe3dba178cde
+ b1dafa255629c676
+ after
+ 8f1d72604f9253e0.f69cef0fdea39d97.04f9ebd4e104296e.32c6de5695c91c1b
+ 79ac3b2c57f42c0a.3c6d87ec5d1c9591.fd20c21950dd32a3.3b812c42f5f3735c
+ 8f1d72604f9253e0.f69cef0fdea39d97.fd20c219e104296e.32c6de56f5f3735c
+ fe8dcaa95ad2e1f0.e509672c07f009c5.16c174e73658ed1b.1ebfbe3dba178cde
+ b1dafa255629c676
+
+VMINPS_256(reg)
+ before
+ 2a587d8de9a0c42e.517788338c673404.ff6ca7666b63fd57.eed14649e51216b7
+ e58544e20e08c2b1.7e6d397f5a7a2968.6e986d975341131f.72c80e36e284c3cd
+ 3ead499162eefbac.633b5c79df177949.8cd9b32c5c1787c9.8071499c48bbae8a
+ 911c8a0480ddaccb.dbad6a0d384be3d3.b67b778f22709500.f397716533c2931a
+ a607047fc0a530a8
+ after
+ e58544e280ddaccb.dbad6a0d384be3d3.b67b778f22709500.f3977165e284c3cd
+ e58544e20e08c2b1.7e6d397f5a7a2968.6e986d975341131f.72c80e36e284c3cd
+ 3ead499162eefbac.633b5c79df177949.8cd9b32c5c1787c9.8071499c48bbae8a
+ 911c8a0480ddaccb.dbad6a0d384be3d3.b67b778f22709500.f397716533c2931a
+ a607047fc0a530a8
+VMINPS_256(mem)
+ before
+ 778e7ed50b713f61.391d02a9046211b9.c18fe02880212131.49c9b42e3fd87971
+ 41f659532f317d71.94fdadeb8b086623.f3ad3bb4d4a6f08f.9f11667452dc6ec8
+ df0b13e548f1a503.fd098836b05be6b4.4cd2f69f4fe40c1b.159d89ccf407b1b0
+ 2f9b267773be7544.d08b8ef610e7ce19.a7cb8ed30ee930ff.07ba1aa4c3e57dd5
+ d1b413675b0310e4
+ after
+ 778e7ed50b713f61.391d02a9046211b9.c18fe02880212131.49c9b42e3fd87971
+ 41f659532f317d71.94fdadeb8b086623.f3ad3bb4d4a6f08f.9f11667452dc6ec8
+ 41f659530b713f61.94fdadeb8b086623.f3ad3bb4d4a6f08f.9f1166743fd87971
+ 2f9b267773be7544.d08b8ef610e7ce19.a7cb8ed30ee930ff.07ba1aa4c3e57dd5
+ d1b413675b0310e4
+
+VMINPS_256(reg)
+ before
+ d0d7728157eca489.0b7011f5cba3a75f.68d0ba9747395afd.e2647d3e2cc11967
+ 5e6f325f542c7570.51584d4b6dadf781.23230a85f0dcc50e.d76941cac5778380
+ d8c7506bed50c144.db1d576674e623d5.5bd27a2ca75d4cf5.64a65565f6172a76
+ 9a2cc712bee3c2b1.878cac30fd5ce588.6e2704f909472b61.63e635fadbadc974
+ b1f75d758f461da7
+ after
+ 9a2cc712bee3c2b1.878cac30fd5ce588.23230a85f0dcc50e.d76941cadbadc974
+ 5e6f325f542c7570.51584d4b6dadf781.23230a85f0dcc50e.d76941cac5778380
+ d8c7506bed50c144.db1d576674e623d5.5bd27a2ca75d4cf5.64a65565f6172a76
+ 9a2cc712bee3c2b1.878cac30fd5ce588.6e2704f909472b61.63e635fadbadc974
+ b1f75d758f461da7
+VMINPS_256(mem)
+ before
+ 2ba349c22eede23b.00eb92c16472b564.2f71c797231bfac6.b670a656b1269efb
+ abb776ced5afd35b.664eb0e27b87d609.b0982486032e1dba.91f75bb03c87e072
+ 0eff5f83a096ae33.28a21ae39db0604c.e7cc3fe8b8a10c91.59091f7445f52e70
+ 314780ceaab12cf0.a132cd2f697990d8.aeda95ab5f808177.6cf2ef0d68fcc4a2
+ 24fdc5e74229ddb3
+ after
+ 2ba349c22eede23b.00eb92c16472b564.2f71c797231bfac6.b670a656b1269efb
+ abb776ced5afd35b.664eb0e27b87d609.b0982486032e1dba.91f75bb03c87e072
+ abb776ced5afd35b.00eb92c16472b564.b0982486032e1dba.b670a656b1269efb
+ 314780ceaab12cf0.a132cd2f697990d8.aeda95ab5f808177.6cf2ef0d68fcc4a2
+ 24fdc5e74229ddb3
+
+VMINPD_128(reg)
+ before
+ df789f6e6f07b650.ee5b569c0f090cbe.2f4cc632796da259.e28fa1ba13d83897
+ f7ad780d8a228b24.22065bd7ecac08c9.2d3a00586918d27c.5fb5df01f1b4ef1d
+ c9e94c33300798dc.a9160d6d5ca5dd3c.f749770dd6065bed.0219cb6c14216036
+ b1781849fc411824.5f55e7497c014743.e9c628bd5bc47a57.a586e2e8982a480e
+ 25ca9e5f9adb63d1
+ after
+ 0000000000000000.0000000000000000.e9c628bd5bc47a57.a586e2e8982a480e
+ f7ad780d8a228b24.22065bd7ecac08c9.2d3a00586918d27c.5fb5df01f1b4ef1d
+ c9e94c33300798dc.a9160d6d5ca5dd3c.f749770dd6065bed.0219cb6c14216036
+ b1781849fc411824.5f55e7497c014743.e9c628bd5bc47a57.a586e2e8982a480e
+ 25ca9e5f9adb63d1
+VMINPD_128(mem)
+ before
+ 5eb07dbe36416caa.0ca6d7bc8a5c48a7.2190665767cb020c.5efb0dd495dd6a67
+ 2c03faf2866720c5.34bf85f877e56412.c99304833a0fc9c0.b43424be1fde69c9
+ 6b9092e5a9593b4f.860e1e6a5e67a710.34293fb910d9598e.46bf68e89652b128
+ f723bf85b9237874.5ee19e7cdc6e4f4e.3e2092e505366da0.70e6d5bc95c57f31
+ 8df768a8b8c40e8f
+ after
+ 5eb07dbe36416caa.0ca6d7bc8a5c48a7.2190665767cb020c.5efb0dd495dd6a67
+ 2c03faf2866720c5.34bf85f877e56412.c99304833a0fc9c0.b43424be1fde69c9
+ 0000000000000000.0000000000000000.c99304833a0fc9c0.b43424be1fde69c9
+ f723bf85b9237874.5ee19e7cdc6e4f4e.3e2092e505366da0.70e6d5bc95c57f31
+ 8df768a8b8c40e8f
+
+VMINPD_128(reg)
+ before
+ fb3c1c179cd99cef.ac88ffbdd2d29460.1882029c8d879678.c34279f33632c322
+ 1402ec74dd9363fc.668acd7911724b3e.103e45350b3db839.9f5d70d0bfd71542
+ 3695d72d167b9f63.01f7a5a5910d593a.a26163b3f51cf33e.ae3bf466bb332029
+ bb40d6ade31f8ed0.5999042d6fb17981.2a375882e4b18132.cba980a346519f06
+ d47290717d3e4f03
+ after
+ 0000000000000000.0000000000000000.103e45350b3db839.cba980a346519f06
+ 1402ec74dd9363fc.668acd7911724b3e.103e45350b3db839.9f5d70d0bfd71542
+ 3695d72d167b9f63.01f7a5a5910d593a.a26163b3f51cf33e.ae3bf466bb332029
+ bb40d6ade31f8ed0.5999042d6fb17981.2a375882e4b18132.cba980a346519f06
+ d47290717d3e4f03
+VMINPD_128(mem)
+ before
+ a464a0be7c05ec4c.0151e760e10a6aee.4a3e64fdc66a693f.040b200e77879ec2
+ 174a2d755eb2320e.621204b2acc9706a.afb04301b342e29f.8c2bb8c3472b889a
+ 09efb1823f52dc75.3cd12b10dfe7dbf0.66bb1c265147a3ce.1ee11b0df2277965
+ 5520aad13cf0a8ac.e9d858e416f0e92b.4a2d6c56bc8566f8.167a4558140aaed0
+ d0423211485d6386
+ after
+ a464a0be7c05ec4c.0151e760e10a6aee.4a3e64fdc66a693f.040b200e77879ec2
+ 174a2d755eb2320e.621204b2acc9706a.afb04301b342e29f.8c2bb8c3472b889a
+ 0000000000000000.0000000000000000.afb04301b342e29f.8c2bb8c3472b889a
+ 5520aad13cf0a8ac.e9d858e416f0e92b.4a2d6c56bc8566f8.167a4558140aaed0
+ d0423211485d6386
+
+VMINPD_128(reg)
+ before
+ a885dfa22baed334.d9a9934e70994fe0.c674859cee71d4c8.37d1ad7f1106e848
+ fa8f477958883b86.7056e9e5f857903d.30f0b0a202f5d872.08725d8b6cd8e5eb
+ 21ab66006b78d727.f5f32682ef3825ee.819ad464ef0833d6.9bddf768e807180c
+ 7b2738a50108e3c4.464bc8127248cb20.16bced4c50371f9f.cbdff701a19d3ed8
+ 7342d942b4a8137a
+ after
+ 0000000000000000.0000000000000000.16bced4c50371f9f.cbdff701a19d3ed8
+ fa8f477958883b86.7056e9e5f857903d.30f0b0a202f5d872.08725d8b6cd8e5eb
+ 21ab66006b78d727.f5f32682ef3825ee.819ad464ef0833d6.9bddf768e807180c
+ 7b2738a50108e3c4.464bc8127248cb20.16bced4c50371f9f.cbdff701a19d3ed8
+ 7342d942b4a8137a
+VMINPD_128(mem)
+ before
+ 71d21a173d345320.634db9d3b5c79a08.3e2b4a7f9c913efe.4ba4f7c8c20dd97a
+ 9f5d356c574cb9f3.346ae6f6243e39a0.b86028b78a2139b5.7d9cef43e0169d13
+ dbada62d1efc0222.4ccaba7aeafbfb37.92b4dfa457047970.06f1cf2946dfa615
+ ff90e946af50ead6.06b931cba1891e7a.a6f4ea342045ba5c.43ef95e692f3312d
+ 90e13de65ddf7a06
+ after
+ 71d21a173d345320.634db9d3b5c79a08.3e2b4a7f9c913efe.4ba4f7c8c20dd97a
+ 9f5d356c574cb9f3.346ae6f6243e39a0.b86028b78a2139b5.7d9cef43e0169d13
+ 0000000000000000.0000000000000000.b86028b78a2139b5.4ba4f7c8c20dd97a
+ ff90e946af50ead6.06b931cba1891e7a.a6f4ea342045ba5c.43ef95e692f3312d
+ 90e13de65ddf7a06
+
+VMINPD_256(reg)
+ before
+ 4915c196452dbc4d.e9d07ba425552c3e.bd824755e875dc15.d2ebc45200f0b8a5
+ cad51f60e66b34ae.733ad6319d168584.cf73f985594a72b3.f067ebea13112e76
+ 6f6e52b2db251ed4.7b9a78db32a0b1d5.96d642c590941b01.de32dbe876b5d9fc
+ 942c56f6c0e6b66c.dbbcdc8d01fd6c5c.70f81e8329e015ab.761a0e3845e77563
+ 95e902c69ab4bdd6
+ after
+ cad51f60e66b34ae.dbbcdc8d01fd6c5c.cf73f985594a72b3.f067ebea13112e76
+ cad51f60e66b34ae.733ad6319d168584.cf73f985594a72b3.f067ebea13112e76
+ 6f6e52b2db251ed4.7b9a78db32a0b1d5.96d642c590941b01.de32dbe876b5d9fc
+ 942c56f6c0e6b66c.dbbcdc8d01fd6c5c.70f81e8329e015ab.761a0e3845e77563
+ 95e902c69ab4bdd6
+VMINPD_256(mem)
+ before
+ 186c327f94276f81.955b279a323a3721.706b7f32253c7146.b7258929c2b99a5c
+ d96f1a4d4d4c4492.ce47c109ccaddea0.1774dbb8bb667dbe.c9a97f25f4abe6c1
+ b5bd371de12ffb33.9b3c21af2bcce795.aaa46e0ade894cf1.00cffde25d433785
+ 882403dc6ddd4e90.578542f7ea228eab.06c5b314aab0990b.b9e5fecc990bc755
+ 51357e4f4392d3dc
+ after
+ 186c327f94276f81.955b279a323a3721.706b7f32253c7146.b7258929c2b99a5c
+ d96f1a4d4d4c4492.ce47c109ccaddea0.1774dbb8bb667dbe.c9a97f25f4abe6c1
+ d96f1a4d4d4c4492.ce47c109ccaddea0.1774dbb8bb667dbe.c9a97f25f4abe6c1
+ 882403dc6ddd4e90.578542f7ea228eab.06c5b314aab0990b.b9e5fecc990bc755
+ 51357e4f4392d3dc
+
+VMINPD_256(reg)
+ before
+ 220c79d7f86197c7.2e6efc750c61fad6.606f204fa63c0e8e.07a427c23ce82237
+ 89b6ecd053064ec2.84689dd4dbc8bb31.1146b823faa5a4ec.890c4401b03ca0a2
+ e27fd1a6f00d3578.64de63e4f51d4dcc.c65604dd83e98c6f.68cb88bb21b8d277
+ 8ab326c66c018896.ab9cc893776c6bd4.dbeb02eadc9401c3.81ac6eddab6872e3
+ ae7a72546b593d12
+ after
+ 8ab326c66c018896.ab9cc893776c6bd4.dbeb02eadc9401c3.890c4401b03ca0a2
+ 89b6ecd053064ec2.84689dd4dbc8bb31.1146b823faa5a4ec.890c4401b03ca0a2
+ e27fd1a6f00d3578.64de63e4f51d4dcc.c65604dd83e98c6f.68cb88bb21b8d277
+ 8ab326c66c018896.ab9cc893776c6bd4.dbeb02eadc9401c3.81ac6eddab6872e3
+ ae7a72546b593d12
+VMINPD_256(mem)
+ before
+ cc02100b7d96ef2f.db9ee69a626e82c7.356e4acc7cc2d274.ab51adb7a2334095
+ b710c5edfb2c4467.328b0e906fe060b8.de1f647c21293dd9.94d301ae70518591
+ 4b700be80426f7e5.ebc798122ee45e15.827d928d81b06a2f.f0bffb3de37b0c62
+ 64ed60e7b190c5d6.629e828e3c05b889.fd5250ecb86013a1.1d5f96ce963c10b5
+ 7600cecf2520ce36
+ after
+ cc02100b7d96ef2f.db9ee69a626e82c7.356e4acc7cc2d274.ab51adb7a2334095
+ b710c5edfb2c4467.328b0e906fe060b8.de1f647c21293dd9.94d301ae70518591
+ cc02100b7d96ef2f.db9ee69a626e82c7.de1f647c21293dd9.ab51adb7a2334095
+ 64ed60e7b190c5d6.629e828e3c05b889.fd5250ecb86013a1.1d5f96ce963c10b5
+ 7600cecf2520ce36
+
+VMINPD_256(reg)
+ before
+ 56ee9fab2db48290.dd5540d621776a66.f35cc76f35cfa9c1.2b6b1b86e347f55c
+ 1b7405ce4a836770.947225a16de6a1c0.fa4d6421b3cf6e68.e8946e451e71cb8b
+ 1fe0fda41719ba81.64128d34b4e92711.d3bd53105490432b.0f99c51784e8525b
+ c07c81993003b770.29fff37b0f8db884.daf792a8b49f64b6.7e469ce731ba46f7
+ 106670a042f3638d
+ after
+ c07c81993003b770.947225a16de6a1c0.fa4d6421b3cf6e68.e8946e451e71cb8b
+ 1b7405ce4a836770.947225a16de6a1c0.fa4d6421b3cf6e68.e8946e451e71cb8b
+ 1fe0fda41719ba81.64128d34b4e92711.d3bd53105490432b.0f99c51784e8525b
+ c07c81993003b770.29fff37b0f8db884.daf792a8b49f64b6.7e469ce731ba46f7
+ 106670a042f3638d
+VMINPD_256(mem)
+ before
+ a1c6bb30d29d6446.5895901a32cb9ae8.bf05d3639cdd0f46.6b481c556e860cb4
+ 0d33fb82fec60751.44772391b8009e96.02f2a9d677e5ea83.e2fded841fd378d2
+ 2f77ab82e17a05d8.e16e376b5f2b0026.cd91f1c2bbb20366.9b60019f6212e3bb
+ e55e481d98c31d07.89c6c915c2dafc43.fead2811854f161b.f2bd5514d3ce8b1c
+ 4262e34d0f93aaa1
+ after
+ a1c6bb30d29d6446.5895901a32cb9ae8.bf05d3639cdd0f46.6b481c556e860cb4
+ 0d33fb82fec60751.44772391b8009e96.02f2a9d677e5ea83.e2fded841fd378d2
+ a1c6bb30d29d6446.44772391b8009e96.bf05d3639cdd0f46.e2fded841fd378d2
+ e55e481d98c31d07.89c6c915c2dafc43.fead2811854f161b.f2bd5514d3ce8b1c
+ 4262e34d0f93aaa1
+
+VMOVHPS_128_StoreForm(reg)
+ before
+ e99aa9b8b2ed7df5.0ab64c3d3eaf090b.99cbd4fa7e99cd9a.7013c9b1f0c8e1d0
+ 42b0a3c057693fc5.794a35cff04a8610.6dc854852ef2b0d6.fe90508d182a1eaf
+ a9f1cbd09a922ebc.10e57ec0c99f5041.620a45246f73e1a5.86ee3a911a808ae4
+ 79a91f5618f58487.a954a3fae6ba22cb.d2dea442dca89cb0.e2f901a911d7e09c
+ f07f23c11a39de03
+ after
+ e99aa9b8b2ed7df5.0ab64c3d3eaf090b.99cbd4fa7e99cd9a.7013c9b1f0c8e1d0
+ 42b0a3c057693fc5.794a35cff04a8610.6dc854852ef2b0d6.fe90508d182a1eaf
+ a9f1cbd09a922ebc.10e57ec0c99f5041.620a45246f73e1a5.86ee3a911a808ae4
+ 79a91f5618f58487.a954a3fae6ba22cb.d2dea442dca89cb0.e2f901a911d7e09c
+ f07f23c11a39de03
+VMOVHPS_128_StoreForm(mem)
+ before
+ 8a4a1bc551b43e44.10249abd6d1d7dd1.2263216b62a7b9da.1a8e6c4b121c1ca5
+ 8e2866a2d154bc8c.c8ae387233965747.55de72fe5a73d199.966699abac5b9e30
+ d6e37e42b6241607.ff92f5df09ed4c95.2091149fe9292634.a2b427ce47f15efd
+ 4048e1921d3006e0.101ece7188ad9966.5d4882392bd573d9.9ac312217e6b97b7
+ dade570eed54870a
+ after
+ 8a4a1bc551b43e44.10249abd6d1d7dd1.2263216b62a7b9da.55de72fe5a73d199
+ 8e2866a2d154bc8c.c8ae387233965747.55de72fe5a73d199.966699abac5b9e30
+ d6e37e42b6241607.ff92f5df09ed4c95.2091149fe9292634.a2b427ce47f15efd
+ 4048e1921d3006e0.101ece7188ad9966.5d4882392bd573d9.9ac312217e6b97b7
+ dade570eed54870a
+
+VMOVHPS_128_StoreForm(reg)
+ before
+ be52f102313868a3.a6230a7f21844943.569cbd954f627967.eace39ba3d8475b1
+ a26bdc6ae5a4762e.e54075f4de2d9a5e.2f59c0b5f7992944.a1f0b30e3b41e8eb
+ e27514b1a623ef57.da6a9edc7236b75a.f5a1d23f1fdce5a8.5f7a6e1f401987b1
+ dabc964210420dc8.5f6f0225f6ac5a66.05c0f09d60bae940.0138e5da68171030
+ 61f6942cd0473c93
+ after
+ be52f102313868a3.a6230a7f21844943.569cbd954f627967.eace39ba3d8475b1
+ a26bdc6ae5a4762e.e54075f4de2d9a5e.2f59c0b5f7992944.a1f0b30e3b41e8eb
+ e27514b1a623ef57.da6a9edc7236b75a.f5a1d23f1fdce5a8.5f7a6e1f401987b1
+ dabc964210420dc8.5f6f0225f6ac5a66.05c0f09d60bae940.0138e5da68171030
+ 61f6942cd0473c93
+VMOVHPS_128_StoreForm(mem)
+ before
+ 5c80f8ff93b5ca07.e68b5c8bbe8b0d30.51191cba889a3fac.bc02153d58bc71b7
+ cea18b41ce6e74b7.623064f74c8d2a39.8d356887440c2459.74b23c8aa370b8ba
+ 9327cbdc9c7df7d0.aaf5a9f257d1a190.ed8f6278450ec398.8a1e63f0dc62fbf4
+ 88dc33be1aef0f7e.192728e87ae5aee0.4ef3867aa7add996.5b9086db9f1c7512
+ 41559fb7892c64c0
+ after
+ 5c80f8ff93b5ca07.e68b5c8bbe8b0d30.51191cba889a3fac.8d356887440c2459
+ cea18b41ce6e74b7.623064f74c8d2a39.8d356887440c2459.74b23c8aa370b8ba
+ 9327cbdc9c7df7d0.aaf5a9f257d1a190.ed8f6278450ec398.8a1e63f0dc62fbf4
+ 88dc33be1aef0f7e.192728e87ae5aee0.4ef3867aa7add996.5b9086db9f1c7512
+ 41559fb7892c64c0
+
+VMOVHPS_128_StoreForm(reg)
+ before
+ 99b9acf1361e02a9.878d3fd263cf78ec.0d12db4652548dd6.8c2c517787f4227e
+ bf07a8f3417c8b7a.6d066c049429ed47.e102c0767aab791e.83083e5c01f0597d
+ 108d8f2b46d43dde.16123540c80a2bba.f043d2e58e75af63.0f51c91630ac3bbf
+ e6955d03e2b25282.5e7f16721c7ded72.98200e002c3e6b52.0cd46e903034846f
+ 565daab51e95efba
+ after
+ 99b9acf1361e02a9.878d3fd263cf78ec.0d12db4652548dd6.8c2c517787f4227e
+ bf07a8f3417c8b7a.6d066c049429ed47.e102c0767aab791e.83083e5c01f0597d
+ 108d8f2b46d43dde.16123540c80a2bba.f043d2e58e75af63.0f51c91630ac3bbf
+ e6955d03e2b25282.5e7f16721c7ded72.98200e002c3e6b52.0cd46e903034846f
+ 565daab51e95efba
+VMOVHPS_128_StoreForm(mem)
+ before
+ c9b8f87315da39cb.9e6d0fe9b0a10712.21178b86ab8ef19b.34e66e32ed92e996
+ 41b0d4b5320f1ecf.945fa0484d2d9839.3ba81069914af160.1fe1f0e66ffe64dc
+ 9a13ba6790415af2.24b80c8b54e240a4.88fc2205ebbbaaee.b75d8f8a4e0d19cf
+ b0ab26754c7ba85f.aac34f20624d3cfe.e4e03c48d5f0d770.56a64789254c441c
+ 5a08144f9046206f
+ after
+ c9b8f87315da39cb.9e6d0fe9b0a10712.21178b86ab8ef19b.3ba81069914af160
+ 41b0d4b5320f1ecf.945fa0484d2d9839.3ba81069914af160.1fe1f0e66ffe64dc
+ 9a13ba6790415af2.24b80c8b54e240a4.88fc2205ebbbaaee.b75d8f8a4e0d19cf
+ b0ab26754c7ba85f.aac34f20624d3cfe.e4e03c48d5f0d770.56a64789254c441c
+ 5a08144f9046206f
+
+VMOVNTDQ_256(reg)
+ before
+ 1dcff3482c87ea73.5f4695cb81c9c642.82ce667212f9c8f4.2a1fda1c6af23513
+ fd46dfe0959cded5.83ae82564c386dc9.08234bed01721f32.3887786fc6cf8003
+ 54bad48365103841.f7b06900c8d35c1e.9810fcfeca457f63.e9e3922c0693746b
+ 8077ce9e3b6f3362.9917c6b612a64d6d.8edf740f0afd2234.19fea53f4548cc77
+ a4a52c94a0fc4655
+ after
+ 1dcff3482c87ea73.5f4695cb81c9c642.82ce667212f9c8f4.2a1fda1c6af23513
+ fd46dfe0959cded5.83ae82564c386dc9.08234bed01721f32.3887786fc6cf8003
+ 54bad48365103841.f7b06900c8d35c1e.9810fcfeca457f63.e9e3922c0693746b
+ 8077ce9e3b6f3362.9917c6b612a64d6d.8edf740f0afd2234.19fea53f4548cc77
+ a4a52c94a0fc4655
+VMOVNTDQ_256(mem)
+ before
+ 65a4a31733bb9b2f.dbc9c99bb1460ce4.44b1166545befde3.46ddb08d5c274450
+ 3ac787b418908a31.c2fcc2e86320ff75.d448d4f87d2628ac.1b56aae55c4e2364
+ feda52576e87cd88.925cb4efee8947bf.24aa7c5ad7ea89f4.6b956081a7fef91c
+ 8ca882ed4eac2160.a5349b1eed0e226e.12a18a796f17dde5.91e8cdcfd9c30223
+ e999ed3a8d2a7c26
+ after
+ 3ac787b418908a31.c2fcc2e86320ff75.d448d4f87d2628ac.1b56aae55c4e2364
+ 3ac787b418908a31.c2fcc2e86320ff75.d448d4f87d2628ac.1b56aae55c4e2364
+ feda52576e87cd88.925cb4efee8947bf.24aa7c5ad7ea89f4.6b956081a7fef91c
+ 8ca882ed4eac2160.a5349b1eed0e226e.12a18a796f17dde5.91e8cdcfd9c30223
+ e999ed3a8d2a7c26
+
+VMOVNTDQ_256(reg)
+ before
+ cef5bd2e5fbea1d0.c2fe9260d70c42e4.58d173e0fd3ac92f.78fa7a4060b8e0ae
+ 9e493717ec0caece.7aa9fe9e22b2eb41.077f39a1b9997bae.3480c99bc6d94e79
+ b4de5961d09fdfcb.927343924daad9a3.0e8ae8cdbdb87296.2001f276be87e273
+ 6b031e78a5036f74.e429db277401c835.c93e7cd0a622eb94.1a4871bd63cd59c7
+ fc20c25dd2b76fa2
+ after
+ cef5bd2e5fbea1d0.c2fe9260d70c42e4.58d173e0fd3ac92f.78fa7a4060b8e0ae
+ 9e493717ec0caece.7aa9fe9e22b2eb41.077f39a1b9997bae.3480c99bc6d94e79
+ b4de5961d09fdfcb.927343924daad9a3.0e8ae8cdbdb87296.2001f276be87e273
+ 6b031e78a5036f74.e429db277401c835.c93e7cd0a622eb94.1a4871bd63cd59c7
+ fc20c25dd2b76fa2
+VMOVNTDQ_256(mem)
+ before
+ a45661402752df2f.210383c80ac59c75.4e96444bb2c27424.95e7f11610632253
+ ecb6cb547ca9669b.302982be98709f79.aa88f9e923fa989b.ccd0430b96085380
+ b20c7b83efc9c012.f6c219c4ee90b72d.d6c977ede4b3f1c7.cb476f1cd49cb9c7
+ d024edbb9cbda9bf.cd1b4347a5b11e3d.ac27384311fb3bd3.ee9670b367ac91d3
+ 910a423eebc21751
+ after
+ ecb6cb547ca9669b.302982be98709f79.aa88f9e923fa989b.ccd0430b96085380
+ ecb6cb547ca9669b.302982be98709f79.aa88f9e923fa989b.ccd0430b96085380
+ b20c7b83efc9c012.f6c219c4ee90b72d.d6c977ede4b3f1c7.cb476f1cd49cb9c7
+ d024edbb9cbda9bf.cd1b4347a5b11e3d.ac27384311fb3bd3.ee9670b367ac91d3
+ 910a423eebc21751
+
+VMOVNTDQ_256(reg)
+ before
+ 0fefe128fb6d86ec.23c99ee79e91dccf.137efcb45c601154.096cbad7c5de31ec
+ c6914adc33361b51.88c908f21251166e.22374176ac29cc1f.ca6578961c67913e
+ 113b77c830ab122c.d9eea9ca130a13c7.58940cf933968a49.c9deee6a33a214f4
+ 4c3b66578d57a628.f305fc5abec78e06.0fdf5ba98d35897f.e3a29841259c793b
+ f47ff3050f5f7a3e
+ after
+ 0fefe128fb6d86ec.23c99ee79e91dccf.137efcb45c601154.096cbad7c5de31ec
+ c6914adc33361b51.88c908f21251166e.22374176ac29cc1f.ca6578961c67913e
+ 113b77c830ab122c.d9eea9ca130a13c7.58940cf933968a49.c9deee6a33a214f4
+ 4c3b66578d57a628.f305fc5abec78e06.0fdf5ba98d35897f.e3a29841259c793b
+ f47ff3050f5f7a3e
+VMOVNTDQ_256(mem)
+ before
+ d83f7aa40cfad42a.d3db13f5e7c715f1.b2da7d8f2e954559.a46629f25592026c
+ 6cafa9093976432b.0268780ed9859835.f239a9537f7ff1e9.74737240273734bd
+ 8a9bfc20b1e1836c.342e930f00206e9e.90edfa93ce9151e5.d95333ffa0b2591e
+ 0fcff0d591464f1a.c7795e62f721d2d8.66c4ee3c37d81f77.3052679b5c8fae3a
+ d5bc0a80f6586fbe
+ after
+ 6cafa9093976432b.0268780ed9859835.f239a9537f7ff1e9.74737240273734bd
+ 6cafa9093976432b.0268780ed9859835.f239a9537f7ff1e9.74737240273734bd
+ 8a9bfc20b1e1836c.342e930f00206e9e.90edfa93ce9151e5.d95333ffa0b2591e
+ 0fcff0d591464f1a.c7795e62f721d2d8.66c4ee3c37d81f77.3052679b5c8fae3a
+ d5bc0a80f6586fbe
+
+VMOVHPS_128_LoadForm(reg)
+ before
+ 24dc181b0a9bd855.d7170014f4b26460.1694d7745b16ff90.51880038d55f18cb
+ 7a008dd635e424ac.be3fa8c9f7307d6b.7ccdfab2c78a3272.2d06ad75c432f80f
+ 3172661f12be906f.a01264e0b5cc5867.576ec186d80aa629.d60a6fdd215d7b6c
+ a67f9d613eb55749.595db0454b93af7f.02c42a5e29219862.2860c45e07ed5c11
+ ffd427e393ee5828
+ after
+ 24dc181b0a9bd855.d7170014f4b26460.1694d7745b16ff90.51880038d55f18cb
+ 7a008dd635e424ac.be3fa8c9f7307d6b.7ccdfab2c78a3272.2d06ad75c432f80f
+ 3172661f12be906f.a01264e0b5cc5867.576ec186d80aa629.d60a6fdd215d7b6c
+ a67f9d613eb55749.595db0454b93af7f.02c42a5e29219862.2860c45e07ed5c11
+ ffd427e393ee5828
+VMOVHPS_128_LoadForm(mem)
+ before
+ 37311458e06a2bdd.357331085455b7e7.c5ec09e5d4903fe0.d81b30a5565b44c9
+ ab4408a90b6f905d.3a9a1b80f12beaf4.c08be9aa6ccfc3b5.37bfcfc7fc44e609
+ 39da7dc22f0944d4.113f5835b0c22d1d.2606cf82305df82b.79fc0330b769b9cf
+ bcbdf1906942036e.16b0e5932ea6bb0e.d22934583b459a6e.fc1dc94c2256fbc6
+ 1a701c87d995e59b
+ after
+ 37311458e06a2bdd.357331085455b7e7.c5ec09e5d4903fe0.d81b30a5565b44c9
+ ab4408a90b6f905d.3a9a1b80f12beaf4.c08be9aa6ccfc3b5.37bfcfc7fc44e609
+ 0000000000000000.0000000000000000.d81b30a5565b44c9.37bfcfc7fc44e609
+ bcbdf1906942036e.16b0e5932ea6bb0e.d22934583b459a6e.fc1dc94c2256fbc6
+ 1a701c87d995e59b
+
+VMOVHPS_128_LoadForm(reg)
+ before
+ 313ff84d79b4b6f9.10badffdd4288855.a537bd060664d172.a2bf9518aa9365a9
+ 9bd7590b9d3fa88d.119cc4f68cc791b8.1921dcfad587abf6.71956fad99541409
+ b5843b2be2c0f803.9a311a68ae29d8c1.d0ba3edc369c8545.1b783d05239365b9
+ dc929b1be3c5e206.89435f3e565c199d.254ee016c52e9a0c.7b327b0c645c11e6
+ 6f8fa5ac79bcd7bb
+ after
+ 313ff84d79b4b6f9.10badffdd4288855.a537bd060664d172.a2bf9518aa9365a9
+ 9bd7590b9d3fa88d.119cc4f68cc791b8.1921dcfad587abf6.71956fad99541409
+ b5843b2be2c0f803.9a311a68ae29d8c1.d0ba3edc369c8545.1b783d05239365b9
+ dc929b1be3c5e206.89435f3e565c199d.254ee016c52e9a0c.7b327b0c645c11e6
+ 6f8fa5ac79bcd7bb
+VMOVHPS_128_LoadForm(mem)
+ before
+ d25d38d27dbe7166.6a4c74453ddaa243.b9a00e639f6c1277.7429bd161fc927f7
+ 7f67af6a8d6e9c10.bc00c2178b897365.0512a3c5a5637d7c.1996d146e0f968b1
+ 54788661c4d914e8.2ef881fc6a609219.4b669a4f854f17d8.6fe31814a34b99e6
+ 2b5d39a13e0a9418.1c81ae6075eb3a0b.666770ed5b3c9bb6.d45a8eeb044af544
+ a3483037a083b975
+ after
+ d25d38d27dbe7166.6a4c74453ddaa243.b9a00e639f6c1277.7429bd161fc927f7
+ 7f67af6a8d6e9c10.bc00c2178b897365.0512a3c5a5637d7c.1996d146e0f968b1
+ 0000000000000000.0000000000000000.7429bd161fc927f7.1996d146e0f968b1
+ 2b5d39a13e0a9418.1c81ae6075eb3a0b.666770ed5b3c9bb6.d45a8eeb044af544
+ a3483037a083b975
+
+VMOVHPS_128_LoadForm(reg)
+ before
+ 37f9f96412812125.e2e24418180dd9cc.e3e744af49b4a9e6.31e3a08b4235c642
+ eeb8e5def7d06801.53d324b16eef9f31.dd763f5581491957.8aa5a615564654aa
+ 23d3f012ebfdcbb5.5cfc54585bbba273.677a9bbeb936c60a.4b78fe78b47b0118
+ 3194176a889286ec.d72950f9fc7e9dbd.dd3e54568e06eeaa.5129259e77e189b8
+ 79849575bc83a7b7
+ after
+ 37f9f96412812125.e2e24418180dd9cc.e3e744af49b4a9e6.31e3a08b4235c642
+ eeb8e5def7d06801.53d324b16eef9f31.dd763f5581491957.8aa5a615564654aa
+ 23d3f012ebfdcbb5.5cfc54585bbba273.677a9bbeb936c60a.4b78fe78b47b0118
+ 3194176a889286ec.d72950f9fc7e9dbd.dd3e54568e06eeaa.5129259e77e189b8
+ 79849575bc83a7b7
+VMOVHPS_128_LoadForm(mem)
+ before
+ 9d55cce79e6e1841.764955536d1ed553.a22594806c424d3c.9b0f678a9c45cbe3
+ 9b6846e23aac9781.4c3ca63a332af396.97bd9dd9c7166e1b.fd3acfc47e7f9a62
+ 4d887d51ab4be2a4.11ba068978441d60.93bde6f02a03bb87.5f098872d04197d3
+ 9083ef200e57b3d5.1f0f71aed8f88f5d.73f1ebb1b017f2ac.1dc98efe2f16fde1
+ 93c5ded6378a0939
+ after
+ 9d55cce79e6e1841.764955536d1ed553.a22594806c424d3c.9b0f678a9c45cbe3
+ 9b6846e23aac9781.4c3ca63a332af396.97bd9dd9c7166e1b.fd3acfc47e7f9a62
+ 0000000000000000.0000000000000000.9b0f678a9c45cbe3.fd3acfc47e7f9a62
+ 9083ef200e57b3d5.1f0f71aed8f88f5d.73f1ebb1b017f2ac.1dc98efe2f16fde1
+ 93c5ded6378a0939
+
+VMOVNTDQA_128(reg)
+ before
+ 1d4b7365822af787.4023163a7edbc641.d386e414eed0843b.11252809765dccb5
+ 16a54817af810376.3a35708e17e3d914.8a6d5a27575a39a4.4a2519e298e208cf
+ dc215c58571c68b3.58857905f67ca679.9e0ecf53ae22ea44.fabc3b2a30b16026
+ ca09a894198663e9.77dfab8c37b0ea9d.6cb63f048fb2d3c8.feb809cc5dd691e5
+ 30e3ffb3385d5738
+ after
+ 1d4b7365822af787.4023163a7edbc641.d386e414eed0843b.11252809765dccb5
+ 16a54817af810376.3a35708e17e3d914.8a6d5a27575a39a4.4a2519e298e208cf
+ dc215c58571c68b3.58857905f67ca679.9e0ecf53ae22ea44.fabc3b2a30b16026
+ ca09a894198663e9.77dfab8c37b0ea9d.6cb63f048fb2d3c8.feb809cc5dd691e5
+ 30e3ffb3385d5738
+VMOVNTDQA_128(mem)
+ before
+ 6d0a99cde0536e4c.3caa2a378e4b2fc5.730e840ff58e61ab.51b1a6a697982fdc
+ 91f954056ec3914d.8d4fddae55f70af3.28e07f7b4c1fc6d0.a74b01a562603b2b
+ 787caa4700ba7d67.1b46bd6307172e1e.721f18ba5971d638.cbd04b6e8b943362
+ fe5e197fb243edc5.41dac6c44237d8f3.2d98cbba388f4d0e.198b806baec2522c
+ edca9d0a6876d636
+ after
+ 6d0a99cde0536e4c.3caa2a378e4b2fc5.730e840ff58e61ab.51b1a6a697982fdc
+ 91f954056ec3914d.8d4fddae55f70af3.28e07f7b4c1fc6d0.a74b01a562603b2b
+ 787caa4700ba7d67.1b46bd6307172e1e.721f18ba5971d638.cbd04b6e8b943362
+ 0000000000000000.0000000000000000.730e840ff58e61ab.51b1a6a697982fdc
+ edca9d0a6876d636
+
+VMOVNTDQA_128(reg)
+ before
+ a3d79cb5543af82c.ff6c1d9a9f6a9f93.5a56f43ba2e1431d.351715650386e67f
+ 97ff7bda0f9cf7b9.57733082e43c4dfe.c4074436c2a3ad49.666870a9d9615eb6
+ 268e35e434280d8a.e23dd0249cc4b432.da39b1203f085022.9c575a71d42c71e0
+ aad0c63f6069784a.7c97776de30e8f5b.f7383765b49d6855.b3af4fa910f4db29
+ 873dc93daac457bc
+ after
+ a3d79cb5543af82c.ff6c1d9a9f6a9f93.5a56f43ba2e1431d.351715650386e67f
+ 97ff7bda0f9cf7b9.57733082e43c4dfe.c4074436c2a3ad49.666870a9d9615eb6
+ 268e35e434280d8a.e23dd0249cc4b432.da39b1203f085022.9c575a71d42c71e0
+ aad0c63f6069784a.7c97776de30e8f5b.f7383765b49d6855.b3af4fa910f4db29
+ 873dc93daac457bc
+VMOVNTDQA_128(mem)
+ before
+ f4ce4619bda8a3c6.80102b572eeb71a6.014da348d6279ba3.7950d271bded338e
+ d62c412a65ad7872.039c5f983b3a374a.4c2ad0a0911a9439.bacc7fb0f784eb78
+ 0824365abfde95ed.91be5d6e22e304e1.3bfc78632ef33647.17fa398efdefcdc0
+ 6881a197e747b463.85c3244680711518.a98d197cccbf3cfa.ed24fc776cb91412
+ 9697c4d7e06efe19
+ after
+ f4ce4619bda8a3c6.80102b572eeb71a6.014da348d6279ba3.7950d271bded338e
+ d62c412a65ad7872.039c5f983b3a374a.4c2ad0a0911a9439.bacc7fb0f784eb78
+ 0824365abfde95ed.91be5d6e22e304e1.3bfc78632ef33647.17fa398efdefcdc0
+ 0000000000000000.0000000000000000.014da348d6279ba3.7950d271bded338e
+ 9697c4d7e06efe19
+
+VMOVNTDQA_128(reg)
+ before
+ 709f8e1bf39bc581.d111ffcbf8f592ff.3bf7ad8af071a69a.72aa2ed78589647d
+ d58754ad44cba5f8.1f9ecae40ff3ebee.0fa6f5a80e6df214.711f3360755d67fd
+ 229d14fb6c8adc27.2df680cc474d7a5b.5d1cf90a77f43632.84b8a403b94804a6
+ b32cc9700a65a4bd.d9e39c71bc10fc73.80a4b41ec78fae9f.8641fead6c55f5a3
+ 5285bc48ab90f721
+ after
+ 709f8e1bf39bc581.d111ffcbf8f592ff.3bf7ad8af071a69a.72aa2ed78589647d
+ d58754ad44cba5f8.1f9ecae40ff3ebee.0fa6f5a80e6df214.711f3360755d67fd
+ 229d14fb6c8adc27.2df680cc474d7a5b.5d1cf90a77f43632.84b8a403b94804a6
+ b32cc9700a65a4bd.d9e39c71bc10fc73.80a4b41ec78fae9f.8641fead6c55f5a3
+ 5285bc48ab90f721
+VMOVNTDQA_128(mem)
+ before
+ c6525ac19106c64b.e57f7078b7e73a64.fd329bbe8b472d61.d68c234f99cc9607
+ bc7254053bc21d4e.12e3037f129cdac9.77aef79fd0fec952.ba1e400889362918
+ 12b226ffc4d0b955.97a480f1b411bf97.22252e00a5428b72.88a709b7345aa47c
+ a2de4d9a483d568d.d00ee23a3bd1267b.d962bbce291e30ec.9b7378c735c342df
+ 51ce8ca529fd41ee
+ after
+ c6525ac19106c64b.e57f7078b7e73a64.fd329bbe8b472d61.d68c234f99cc9607
+ bc7254053bc21d4e.12e3037f129cdac9.77aef79fd0fec952.ba1e400889362918
+ 12b226ffc4d0b955.97a480f1b411bf97.22252e00a5428b72.88a709b7345aa47c
+ 0000000000000000.0000000000000000.fd329bbe8b472d61.d68c234f99cc9607
+ 51ce8ca529fd41ee
+
+VMASKMOVDQU_128(reg)
+ before
+ 04033ebbab94db55.4ac144c4e414b022.196c25c643684b20.7a301bf3769f74ed
+ 12608b7658154dbf.e4298768b462823f.ce0c460167636933.df5cc85ca8d012a1
+ d52f7043cb0cd2d9.4ee19272d3328911.4b383f58434dbd60.e5b240f6dcbdc733
+ abbde88ca103a84f.62b4e2ce5d9081c4.ec3d0e3574b28352.69fefeab2d724fd0
+ 450c7e69b8fc66a3
+ after
+ 04033ebbab94db55.4ac144c4e414b022.196c25c643684b20.7a301bf3769f74ed
+ 12608b7658154dbf.e4298768b462823f.ce0c460167636933.df5cc85ca8d012a1
+ d52f7043cb0cd2d9.4ee19272d3328911.4b383f58434dbd60.e5b240f6dcbdc733
+ abbde88ca103a84f.62b4e2ce5d9081c4.ec3d0e3574b28352.69fefeab2d724fd0
+ 450c7e69b8fc66a3
+VMASKMOVDQU_128(mem)
+ before
+ 56a73c1b9866c7d9.ee56efbf758809cc.fd6ff2696f882583.0d68ae06961ff7b6
+ 799db5ade9bd2f9d.fc468246e42631fc.fcde3e2d2527327a.0a021b35441f5437
+ 88b8640bc80c5a1c.2fd99b8f896a5e8d.39cd4207997864d7.3f5a52301a3fd782
+ 60c5c521515f0382.e55a380501dfca29.91077ae4ea8877c3.08bb4e62b50abc42
+ c1700b37b00c3f25
+ after
+ 56a73c1b9866c7d9.ee56efbf758809cc.9107f2696f882583.0d68ae06961ff7b6
+ 799db5ade9bd2f9d.fc468246e42631fc.fcde3e2d2527327a.0a021b35441f5437
+ 88b8640bc80c5a1c.2fd99b8f896a5e8d.39cd4207997864d7.3f5a52301a3fd782
+ 60c5c521515f0382.e55a380501dfca29.91077ae4ea8877c3.08bb4e62b50abc42
+ c1700b37b00c3f25
+
+VMASKMOVDQU_128(reg)
+ before
+ c5c6851ba8d19bd4.dd9054db9fc2e8fa.78165414e711b27c.e05a63ae3262266d
+ 7209b87a38e60dfe.dce58d25cf42c2b1.455aec28d78d5233.039078538d122eff
+ 2385a1c0fdd6d14d.378fedebfcea50d2.a870faad6edee5fa.d47635be18a44ba5
+ 34863b5a922e226d.cb5cef1a42c74c8a.fea47c104890a87c.30d816dbee25398d
+ f38298962ba1b3e0
+ after
+ c5c6851ba8d19bd4.dd9054db9fc2e8fa.78165414e711b27c.e05a63ae3262266d
+ 7209b87a38e60dfe.dce58d25cf42c2b1.455aec28d78d5233.039078538d122eff
+ 2385a1c0fdd6d14d.378fedebfcea50d2.a870faad6edee5fa.d47635be18a44ba5
+ 34863b5a922e226d.cb5cef1a42c74c8a.fea47c104890a87c.30d816dbee25398d
+ f38298962ba1b3e0
+VMASKMOVDQU_128(mem)
+ before
+ f94035dbed2276cd.005882b294793d0b.74160f9cbee47305.a1446dbb0030d766
+ 1ede6b964db63d7e.e54672359e435ed3.0e8ac95f8b4d816e.ee9bc91c3249ad63
+ 3e27b5b36968c61f.3e9e07504c19c170.75849a4ec60f32f2.41f48c9d7b686720
+ 35e8901f5d45cbde.66aa3e6e3c85a18f.85d0fd548a3541bc.f69cb3ac76174149
+ 69df39b4c0e47789
+ after
+ f94035dbed2276cd.005882b294793d0b.74d0fd9c8ae44105.f69cb3bb00304166
+ 1ede6b964db63d7e.e54672359e435ed3.0e8ac95f8b4d816e.ee9bc91c3249ad63
+ 3e27b5b36968c61f.3e9e07504c19c170.75849a4ec60f32f2.41f48c9d7b686720
+ 35e8901f5d45cbde.66aa3e6e3c85a18f.85d0fd548a3541bc.f69cb3ac76174149
+ 69df39b4c0e47789
+
+VMASKMOVDQU_128(reg)
+ before
+ f6091a20f45b448d.dfed76c4445809e4.bbb712fb07163bdc.1a3a6e5ff4cb6bf9
+ f966525eaf07e500.1802e5903aad3b60.97117f624b55cb02.108d695a1fde6cd5
+ ce42ddd98c74968f.bcf3586d5c511e7c.58038211a3d08cad.43966a312878ff7b
+ d1e8b8fd282e93e6.a68c4c49c64f6e64.58db1573ac12bb8b.8e22eed12aa8e118
+ cffb70244277ced7
+ after
+ f6091a20f45b448d.dfed76c4445809e4.bbb712fb07163bdc.1a3a6e5ff4cb6bf9
+ f966525eaf07e500.1802e5903aad3b60.97117f624b55cb02.108d695a1fde6cd5
+ ce42ddd98c74968f.bcf3586d5c511e7c.58038211a3d08cad.43966a312878ff7b
+ d1e8b8fd282e93e6.a68c4c49c64f6e64.58db1573ac12bb8b.8e22eed12aa8e118
+ cffb70244277ced7
+VMASKMOVDQU_128(mem)
+ before
+ e1ee6c178bf381e5.5ea6de371ec217b0.b4983b0f93b3e745.f5e336f502a89446
+ a0c65e972228b86d.d1c64bf10bbb5f9a.c1e4a3abdf8a444b.8969e001401d538a
+ e751c38e22212d9d.8695fc988aa6a64f.a93dff09c7df42a1.72b70f0402fd3304
+ 945916eaa7ea9c9e.d95feb99370d2a7c.476dcb1566be9d74.0a19c06be5d57160
+ aeddeda084304949
+ after
+ e1ee6c178bf381e5.5ea6de371ec217b0.476dcb1566bee745.0ae3c0f502a89460
+ a0c65e972228b86d.d1c64bf10bbb5f9a.c1e4a3abdf8a444b.8969e001401d538a
+ e751c38e22212d9d.8695fc988aa6a64f.a93dff09c7df42a1.72b70f0402fd3304
+ 945916eaa7ea9c9e.d95feb99370d2a7c.476dcb1566be9d74.0a19c06be5d57160
+ aeddeda084304949
+
+VMOVMSKPD_128(reg)
+ before
+ ba4e94117c9af66c.82acd396ce8fc39f.266f165eaf7f25cd.794083bbd93411f0
+ 8bb7b02968a0b574.8c14767db31d5cca.c81378558e85d4ed.1a84a4e73b4c5940
+ 7b663e53e5cdc20e.905e7b8d719f244b.1d950de96fad7288.0504a886a9123291
+ e7a538fd8ead59e6.69555fb12421d64f.8042d286ee823d4c.188b0d823e93580e
+ 2ee64fc917da86e4
+ after
+ ba4e94117c9af66c.82acd396ce8fc39f.266f165eaf7f25cd.794083bbd93411f0
+ 8bb7b02968a0b574.8c14767db31d5cca.c81378558e85d4ed.1a84a4e73b4c5940
+ 7b663e53e5cdc20e.905e7b8d719f244b.1d950de96fad7288.0504a886a9123291
+ e7a538fd8ead59e6.69555fb12421d64f.8042d286ee823d4c.188b0d823e93580e
+ 0000000000000002
+VMOVMSKPD_128(mem)
+ before
+ 22e1e8454ff4793e.2bc19c9200cdb5a7.f2c79dd5e9b02f02.4c66c198a8916ee3
+ d24856e402ebed4a.a306657ed6b813fe.097fb1e6db57eb8f.df4dd88b386544f9
+ 18e714914dce9e31.abbf8f2eacfbaf96.884817ce1722c623.944312cb3b8afa3b
+ d18a9e384ca64721.9f3a170c1f20c41c.4def4c7ab91e7ce9.c6946cc44c8ccb55
+ d38be0e308f8f4f2
+ after
+ 22e1e8454ff4793e.2bc19c9200cdb5a7.f2c79dd5e9b02f02.4c66c198a8916ee3
+ d24856e402ebed4a.a306657ed6b813fe.097fb1e6db57eb8f.df4dd88b386544f9
+ 18e714914dce9e31.abbf8f2eacfbaf96.884817ce1722c623.944312cb3b8afa3b
+ d18a9e384ca64721.9f3a170c1f20c41c.4def4c7ab91e7ce9.c6946cc44c8ccb55
+ d38be0e308f8f4f2
+
+VMOVMSKPD_128(reg)
+ before
+ 15756c920a5ab0bf.dafc70c51a81a546.dcc1f785cbb5903c.3240cad7db56c80f
+ ea9e0b3eef3c3c68.0d0a0724d36a74cc.bba12d064b464da1.14070fcf9cd767be
+ ac52b954522cd498.4780dd41946d6fde.9b26b4f93b5e37f8.d010965015ac1424
+ b9dd723fd0b5b4fb.652a7008799753a8.d79c89cc38898cec.4026dc4564e18d6d
+ 41175b9aa5828cc5
+ after
+ 15756c920a5ab0bf.dafc70c51a81a546.dcc1f785cbb5903c.3240cad7db56c80f
+ ea9e0b3eef3c3c68.0d0a0724d36a74cc.bba12d064b464da1.14070fcf9cd767be
+ ac52b954522cd498.4780dd41946d6fde.9b26b4f93b5e37f8.d010965015ac1424
+ b9dd723fd0b5b4fb.652a7008799753a8.d79c89cc38898cec.4026dc4564e18d6d
+ 0000000000000002
+VMOVMSKPD_128(mem)
+ before
+ b0ad913bf39ccd57.6b8b336b0464183f.41d43c669df3dc58.cb4fa6eadd53862a
+ 67b5f9146b3a0e4f.1fa7f7448bc43b0e.b84abb451c8ec618.d38a09bfc749615e
+ 43fb0f11286909db.327fba3600615a14.a6576b931373cc14.4b9badb792f65b33
+ 204b501e46347b24.fe5d78adffc8b0fe.e8c9c73b9daeab79.8fcc8e3ed8e7ae56
+ fb6aa8c038a79772
+ after
+ b0ad913bf39ccd57.6b8b336b0464183f.41d43c669df3dc58.cb4fa6eadd53862a
+ 67b5f9146b3a0e4f.1fa7f7448bc43b0e.b84abb451c8ec618.d38a09bfc749615e
+ 43fb0f11286909db.327fba3600615a14.a6576b931373cc14.4b9badb792f65b33
+ 204b501e46347b24.fe5d78adffc8b0fe.e8c9c73b9daeab79.8fcc8e3ed8e7ae56
+ fb6aa8c038a79772
+
+VMOVMSKPD_128(reg)
+ before
+ eac1f8a94bc25234.da703627e2a72059.e08e2e1525847b78.586a4b28d74c1f73
+ ba1d7965b0c41a48.4d383f1918cfb3a4.345ed6da0e21f52d.d3077348dc57e42d
+ c6ca2761003a2c59.556de7de03b6f132.57186e68552c5aca.356cbb86c9deb5d4
+ 6913fe07d9afc413.cedca864bf6b962e.a30af22c9630e8fa.5a65a0ceb9ea4f93
+ 1ebd9d0dc8896d97
+ after
+ eac1f8a94bc25234.da703627e2a72059.e08e2e1525847b78.586a4b28d74c1f73
+ ba1d7965b0c41a48.4d383f1918cfb3a4.345ed6da0e21f52d.d3077348dc57e42d
+ c6ca2761003a2c59.556de7de03b6f132.57186e68552c5aca.356cbb86c9deb5d4
+ 6913fe07d9afc413.cedca864bf6b962e.a30af22c9630e8fa.5a65a0ceb9ea4f93
+ 0000000000000002
+VMOVMSKPD_128(mem)
+ before
+ 5d422e2d14c6cd0c.0145fbc5d7b01e24.9451ff9669f75dc4.757e5c906eb9d96a
+ f3bed01bb6ae291d.e9ad180695c87536.8398695f1c680322.29c2aa0278546ac6
+ bcfefdc4cc4c3ef7.7c955335af8306f5.777d61adf5ca4472.1b20d6ed518cd7b9
+ 94ce331272acc7c5.1849a7c0c26e0d0e.4ccb636b0f27dce0.a7e5debd94ee5bf0
+ 295cbedede043316
+ after
+ 5d422e2d14c6cd0c.0145fbc5d7b01e24.9451ff9669f75dc4.757e5c906eb9d96a
+ f3bed01bb6ae291d.e9ad180695c87536.8398695f1c680322.29c2aa0278546ac6
+ bcfefdc4cc4c3ef7.7c955335af8306f5.777d61adf5ca4472.1b20d6ed518cd7b9
+ 94ce331272acc7c5.1849a7c0c26e0d0e.4ccb636b0f27dce0.a7e5debd94ee5bf0
+ 295cbedede043316
+
+VMOVMSKPD_256(reg)
+ before
+ fdd370bcca5d9bd8.57faedf3c3db81b4.171711126a14c52d.de4fec85878d869a
+ 7f94f2c3f582cee2.e14da751dbe428ef.d74a8b9742016bfd.09d676e87807ffc9
+ 0bed3f5ffa010adf.0d95de1ad7d378a4.b22d13bbe6c13b2b.a92a7f7effa2039c
+ fd2853fc7665887c.b99c0d39d2b52cfc.050da4ebf3e17163.9a18823437694e3d
+ b76bfcf73c689bd8
+ after
+ fdd370bcca5d9bd8.57faedf3c3db81b4.171711126a14c52d.de4fec85878d869a
+ 7f94f2c3f582cee2.e14da751dbe428ef.d74a8b9742016bfd.09d676e87807ffc9
+ 0bed3f5ffa010adf.0d95de1ad7d378a4.b22d13bbe6c13b2b.a92a7f7effa2039c
+ fd2853fc7665887c.b99c0d39d2b52cfc.050da4ebf3e17163.9a18823437694e3d
+ 000000000000000d
+VMOVMSKPD_256(mem)
+ before
+ def167b12caca79a.b1922a07043a8764.c02faf9ae9950126.2d363a9104ed4850
+ ea74415020402eaf.8377c1ea400d4244.fe1a4329377fb34c.84f4d21bb66ffd9e
+ b6c205bf3631eb42.ce221313c769f4c7.4e2942d2d980fe9a.679366f3a5f5ccfb
+ 20a52fe98a899b80.f0e11cec35dbd99b.8e282a82eaa39d3d.335ff4876b0bf010
+ 42a37741a73ba78c
+ after
+ def167b12caca79a.b1922a07043a8764.c02faf9ae9950126.2d363a9104ed4850
+ ea74415020402eaf.8377c1ea400d4244.fe1a4329377fb34c.84f4d21bb66ffd9e
+ b6c205bf3631eb42.ce221313c769f4c7.4e2942d2d980fe9a.679366f3a5f5ccfb
+ 20a52fe98a899b80.f0e11cec35dbd99b.8e282a82eaa39d3d.335ff4876b0bf010
+ 42a37741a73ba78c
+
+VMOVMSKPD_256(reg)
+ before
+ f1acec8ff2132a19.03ea3cbc3656fa95.44fed8e325ee2f69.98e2752387f54d61
+ 9cc64ddcea1fb863.3a5ca62359a4c4ac.26c74363332e30e0.4a25a1a3cb80ca31
+ a03d98942bea8b18.a3c9eb0b0d7eb4f2.f1865ad8fc2819aa.7fbb2aecd352cfda
+ 575dc8235000e0e1.18fc865e6ef08792.038818ae1b662673.12718aecba771988
+ e1133f8e9dfa6466
+ after
+ f1acec8ff2132a19.03ea3cbc3656fa95.44fed8e325ee2f69.98e2752387f54d61
+ 9cc64ddcea1fb863.3a5ca62359a4c4ac.26c74363332e30e0.4a25a1a3cb80ca31
+ a03d98942bea8b18.a3c9eb0b0d7eb4f2.f1865ad8fc2819aa.7fbb2aecd352cfda
+ 575dc8235000e0e1.18fc865e6ef08792.038818ae1b662673.12718aecba771988
+ 0000000000000000
+VMOVMSKPD_256(mem)
+ before
+ c66dc4bd97e76ca0.1e72d9f6f6edf36d.77c0f3099906f9b9.b61879512d7792e8
+ 9e4a9567c44aec64.51c7c877b83e0066.9ae2aff8a9cdc592.6884792ecde49ab5
+ 46782e774130a1dc.4caa8f13327e4278.5f2e3518bb50a84a.741615af983b7a85
+ 98c10cda2aa44734.6b652c370139f651.a0700153ea9b5e0d.351c474129076e05
+ 09e00d511dd5b1e1
+ after
+ c66dc4bd97e76ca0.1e72d9f6f6edf36d.77c0f3099906f9b9.b61879512d7792e8
+ 9e4a9567c44aec64.51c7c877b83e0066.9ae2aff8a9cdc592.6884792ecde49ab5
+ 46782e774130a1dc.4caa8f13327e4278.5f2e3518bb50a84a.741615af983b7a85
+ 98c10cda2aa44734.6b652c370139f651.a0700153ea9b5e0d.351c474129076e05
+ 09e00d511dd5b1e1
+
+VMOVMSKPD_256(reg)
+ before
+ 4aaf63490f3080c4.72f2a97a9ab39999.0a459a4dc1fc579a.3a748f9753bba306
+ 55d443979ca4175a.aed78344ad675437.8596d6c30c52a302.0a055bcf11bb3262
+ 879daba65fbeb151.293c162480cf3439.38a4da0481c81433.eaf1e2e741a8c84c
+ 3a5595e2f5098c52.bfecdc072ef4f5cc.7ebaa47cbae8e7d9.b7029ecbfe8d21f2
+ 4d050d676476f87d
+ after
+ 4aaf63490f3080c4.72f2a97a9ab39999.0a459a4dc1fc579a.3a748f9753bba306
+ 55d443979ca4175a.aed78344ad675437.8596d6c30c52a302.0a055bcf11bb3262
+ 879daba65fbeb151.293c162480cf3439.38a4da0481c81433.eaf1e2e741a8c84c
+ 3a5595e2f5098c52.bfecdc072ef4f5cc.7ebaa47cbae8e7d9.b7029ecbfe8d21f2
+ 0000000000000005
+VMOVMSKPD_256(mem)
+ before
+ 89c6aba790700a1b.cb4700b7f911e10c.4db553d8d4e4521b.b5262f96534157a2
+ 4511f2779e8513f8.97c0e5910763ef29.ad61f5828daa0853.383277c1e95ca137
+ 5eb160c3a9c4cf40.f80c41dcbc8af056.bcbd40f37653d3a0.632b786617c70147
+ b0747078cd36f91e.4b771104b412213e.5695b016aaea6f2d.925d2ff27a0db37c
+ 201497d1adbbf382
+ after
+ 89c6aba790700a1b.cb4700b7f911e10c.4db553d8d4e4521b.b5262f96534157a2
+ 4511f2779e8513f8.97c0e5910763ef29.ad61f5828daa0853.383277c1e95ca137
+ 5eb160c3a9c4cf40.f80c41dcbc8af056.bcbd40f37653d3a0.632b786617c70147
+ b0747078cd36f91e.4b771104b412213e.5695b016aaea6f2d.925d2ff27a0db37c
+ 201497d1adbbf382
+
+VMOVMSKPS_128(reg)
+ before
+ 6b9bac704d5cfc06.17249e8027e94ebe.ec4d50768988be8e.57b5bfd7467b9727
+ ce406a39f57c0ab4.6f8e66c9d3e88a4d.38d9fa9cda7703f1.9be9eb22651208b9
+ a44dce9a41a75b37.947e453eeb4069f7.89690ce4416b2b14.fefdafe324bc7d10
+ 4b0fd2fdce6a293c.62c0b6cb8efca6e8.3c4780b85af173a3.5cbc87069e85b458
+ 91f3f078ef7767bc
+ after
+ 6b9bac704d5cfc06.17249e8027e94ebe.ec4d50768988be8e.57b5bfd7467b9727
+ ce406a39f57c0ab4.6f8e66c9d3e88a4d.38d9fa9cda7703f1.9be9eb22651208b9
+ a44dce9a41a75b37.947e453eeb4069f7.89690ce4416b2b14.fefdafe324bc7d10
+ 4b0fd2fdce6a293c.62c0b6cb8efca6e8.3c4780b85af173a3.5cbc87069e85b458
+ 0000000000000001
+VMOVMSKPS_128(mem)
+ before
+ 796e642334a05369.1dd274d03850b16f.b520355bd628fe4b.adc05486c2941649
+ f0f961f5890c338a.78e2af7e1ae62f7b.69693edcdfd12d4c.382083b914e152b3
+ d26062d809c5c44c.b68b807310b7de0c.5a684d3ac602ee18.39b309bded62618c
+ fb6fe3bad0d9c2db.3518e11bb74ffcd0.64eadf5fa6c7fedb.0cc4e3fee8a58081
+ 0da10be8a236ea3e
+ after
+ 796e642334a05369.1dd274d03850b16f.b520355bd628fe4b.adc05486c2941649
+ f0f961f5890c338a.78e2af7e1ae62f7b.69693edcdfd12d4c.382083b914e152b3
+ d26062d809c5c44c.b68b807310b7de0c.5a684d3ac602ee18.39b309bded62618c
+ fb6fe3bad0d9c2db.3518e11bb74ffcd0.64eadf5fa6c7fedb.0cc4e3fee8a58081
+ 0da10be8a236ea3e
+
+VMOVMSKPS_128(reg)
+ before
+ 98947fe7b6a0dc6e.46f16186fb53e962.4fd7d0e2ab3bc271.62b96f389b2d19c0
+ 09ea3a68c06f92be.91b45628a540f40e.6212483587066f9b.32a279b1c33ffaf4
+ bcef39d55e2f48d9.b782408cebaba00a.c816457ee73c3dfb.af7079b737095fa3
+ 0cef769c296d396c.94289a9ee9a1a983.de2fc42a686a693d.b5f1ec34159802f8
+ 1fef4c1679f79f20
+ after
+ 98947fe7b6a0dc6e.46f16186fb53e962.4fd7d0e2ab3bc271.62b96f389b2d19c0
+ 09ea3a68c06f92be.91b45628a540f40e.6212483587066f9b.32a279b1c33ffaf4
+ bcef39d55e2f48d9.b782408cebaba00a.c816457ee73c3dfb.af7079b737095fa3
+ 0cef769c296d396c.94289a9ee9a1a983.de2fc42a686a693d.b5f1ec34159802f8
+ 000000000000000a
+VMOVMSKPS_128(mem)
+ before
+ cb3817487e32f446.5736ef27bfb4a222.0372e14ab92ccba4.01a9c0a6a51b2f0c
+ 9496c9b64056bb97.f80f9fe4bc91bfa9.e22b8f7c7a5ac19a.8bcf345d3bdbcb15
+ 55d6dc4bdc6eb13e.4bc8823eba8fccaa.0b21222145374891.d9ef1fbac5377803
+ ecc3cef56e869169.abab95a0583a04d4.5c1e152338cd1cb4.47537a2be0ba7383
+ 3248421b27f0f741
+ after
+ cb3817487e32f446.5736ef27bfb4a222.0372e14ab92ccba4.01a9c0a6a51b2f0c
+ 9496c9b64056bb97.f80f9fe4bc91bfa9.e22b8f7c7a5ac19a.8bcf345d3bdbcb15
+ 55d6dc4bdc6eb13e.4bc8823eba8fccaa.0b21222145374891.d9ef1fbac5377803
+ ecc3cef56e869169.abab95a0583a04d4.5c1e152338cd1cb4.47537a2be0ba7383
+ 3248421b27f0f741
+
+VMOVMSKPS_128(reg)
+ before
+ f41a74f6366642e8.332b19a010ab1841.7605d278301ea4d1.b0efe4706f2bf830
+ ea150b28aba78e25.08d93b36e1e802f5.07223731dec8e84d.e2600cf2055a9931
+ 7085031d1f3f17a3.4598b0a4fb4a0bae.b94ebf38ffc40bf5.d03d08971768bbe2
+ e2b5594230bb1b0f.c835f2d67adcef9b.ead467f72e9c4a75.5452534ac0601a70
+ 4c6b6cf71c4e7106
+ after
+ f41a74f6366642e8.332b19a010ab1841.7605d278301ea4d1.b0efe4706f2bf830
+ ea150b28aba78e25.08d93b36e1e802f5.07223731dec8e84d.e2600cf2055a9931
+ 7085031d1f3f17a3.4598b0a4fb4a0bae.b94ebf38ffc40bf5.d03d08971768bbe2
+ e2b5594230bb1b0f.c835f2d67adcef9b.ead467f72e9c4a75.5452534ac0601a70
+ 0000000000000009
+VMOVMSKPS_128(mem)
+ before
+ 9253cc8a483f7dd1.9cf308017aa6d415.6b7c7fb97baa69e6.f40229db08dee178
+ 03d7f0ef603efafc.fa890bc7988d7f60.0b39d23819c036bc.3522035128150cab
+ 7cc355127f58a3b4.58c4600126fa589d.8538673e712b1148.0781f0c32bce06ba
+ d7e376e0c1983525.12f0031ac17c9a77.b344bab99ef6b8b7.c86bec9fac940c50
+ d22cf44f48f35a19
+ after
+ 9253cc8a483f7dd1.9cf308017aa6d415.6b7c7fb97baa69e6.f40229db08dee178
+ 03d7f0ef603efafc.fa890bc7988d7f60.0b39d23819c036bc.3522035128150cab
+ 7cc355127f58a3b4.58c4600126fa589d.8538673e712b1148.0781f0c32bce06ba
+ d7e376e0c1983525.12f0031ac17c9a77.b344bab99ef6b8b7.c86bec9fac940c50
+ d22cf44f48f35a19
+
+VMOVMSKPS_256(reg)
+ before
+ 830f02419a782bc3.f103cf43430a6c7a.8458ee7d049c829b.722b4894bc2ee534
+ 356214e03eaebcf7.a6efdd2920ba04e0.0a4a1f988ce84cb5.9fb78cbbe8dd54ec
+ 456f2598d2214964.d3721a7c75b5b882.001091d6f4eb3370.14b5021a3e12c30b
+ 108331d5ef5e0eb4.525a042a5d06458d.c1f840a3d9327579.aef1269dd9d6ecbc
+ 49377530d6378c2c
+ after
+ 830f02419a782bc3.f103cf43430a6c7a.8458ee7d049c829b.722b4894bc2ee534
+ 356214e03eaebcf7.a6efdd2920ba04e0.0a4a1f988ce84cb5.9fb78cbbe8dd54ec
+ 456f2598d2214964.d3721a7c75b5b882.001091d6f4eb3370.14b5021a3e12c30b
+ 108331d5ef5e0eb4.525a042a5d06458d.c1f840a3d9327579.aef1269dd9d6ecbc
+ 000000000000004f
+VMOVMSKPS_256(mem)
+ before
+ c15269c050405f86.f0ea350333f04694.0071161ef5ba672d.ab4c296bd6474c7b
+ f210803763fe20f7.42f02c8f39632eaf.b984cd4458dcda8d.1959469b88b9f423
+ b93b35832c7c8cab.62e112e39e4402b2.595fa387a37859da.676b959d8a11ab1d
+ f0a0058ec6c65fcd.ac09e36dfe1efd48.bcce16d6f19ba13f.f0cd11de79ddab14
+ 12cdb6cbf0a831b4
+ after
+ c15269c050405f86.f0ea350333f04694.0071161ef5ba672d.ab4c296bd6474c7b
+ f210803763fe20f7.42f02c8f39632eaf.b984cd4458dcda8d.1959469b88b9f423
+ b93b35832c7c8cab.62e112e39e4402b2.595fa387a37859da.676b959d8a11ab1d
+ f0a0058ec6c65fcd.ac09e36dfe1efd48.bcce16d6f19ba13f.f0cd11de79ddab14
+ 12cdb6cbf0a831b4
+
+VMOVMSKPS_256(reg)
+ before
+ 28b581cf8cff78ab.740b6a464ee9548a.7db39b97f47d5d1e.be9ca11a5f506de9
+ 8dd26c55e86dbea3.2148e296dff0280d.2f2c37cf1cee5be0.3b97c04008a37b04
+ 9f7075cba07e3d48.d223e86a96e79783.1fc0b28013fc3639.0f89ef3408a085bb
+ b8db989c51be3147.6567f8ae8eda5d18.a9bb0815743328d6.163fabe37c54483b
+ 2c856f3780cb7faf
+ after
+ 28b581cf8cff78ab.740b6a464ee9548a.7db39b97f47d5d1e.be9ca11a5f506de9
+ 8dd26c55e86dbea3.2148e296dff0280d.2f2c37cf1cee5be0.3b97c04008a37b04
+ 9f7075cba07e3d48.d223e86a96e79783.1fc0b28013fc3639.0f89ef3408a085bb
+ b8db989c51be3147.6567f8ae8eda5d18.a9bb0815743328d6.163fabe37c54483b
+ 0000000000000098
+VMOVMSKPS_256(mem)
+ before
+ 2d27b71e2f0fe744.365fcf3497bad84c.b5e28f4ee4d635f7.296935fcdc206f62
+ f5f0ff83a52e3c26.734718ff0dfe6c02.9e5e2736b3e7dc4d.fb1635a0e64e448a
+ 5faec451ff343a80.cde16d694f142a16.fca83e5218170e45.7b0d056d2f4ae6fa
+ 492b8076592b9c7f.9e77ccdefa8a4d33.ab8c4f8e2e74870c.059ba0d0529f8f5d
+ f40d0233ebd97c60
+ after
+ 2d27b71e2f0fe744.365fcf3497bad84c.b5e28f4ee4d635f7.296935fcdc206f62
+ f5f0ff83a52e3c26.734718ff0dfe6c02.9e5e2736b3e7dc4d.fb1635a0e64e448a
+ 5faec451ff343a80.cde16d694f142a16.fca83e5218170e45.7b0d056d2f4ae6fa
+ 492b8076592b9c7f.9e77ccdefa8a4d33.ab8c4f8e2e74870c.059ba0d0529f8f5d
+ f40d0233ebd97c60
+
+VMOVMSKPS_256(reg)
+ before
+ a6ac27039784e9ae.8e34b1ddcd211f4e.435631cba9ec1307.86d5d6d7120a02ce
+ 76c70cadf22d11f4.0a95d2727a227f1a.19ca969af9c4b63b.6b515017dfe33cb6
+ c0a9ac9b975f31dd.981a60227938780f.7a1ff9b985a0727d.35ca383cb10df1f0
+ e09e033b22a78517.168fd5d7e971c558.c3a05592ea0c8579.bf0e0a31a594dcaa
+ e7e742e2d783ba0e
+ after
+ a6ac27039784e9ae.8e34b1ddcd211f4e.435631cba9ec1307.86d5d6d7120a02ce
+ 76c70cadf22d11f4.0a95d2727a227f1a.19ca969af9c4b63b.6b515017dfe33cb6
+ c0a9ac9b975f31dd.981a60227938780f.7a1ff9b985a0727d.35ca383cb10df1f0
+ e09e033b22a78517.168fd5d7e971c558.c3a05592ea0c8579.bf0e0a31a594dcaa
+ 000000000000009f
+VMOVMSKPS_256(mem)
+ before
+ 88225c3b62e64748.31f10df83090484b.5fbfaf7ee3d92321.519ba693c39229db
+ 7d8bd52862c93f85.11efc63e5da6b828.4e786904867b4e98.7e5ae827adc09b4e
+ a4ed2895f4395df1.dbe42b7944750f58.c1847f53eb6301e7.a72a18ba4322177e
+ d716d16e33415eb7.ea1c3715818a8987.92b06e59309df93a.285730b82242d819
+ 5d2d2e8de5ae1bc8
+ after
+ 88225c3b62e64748.31f10df83090484b.5fbfaf7ee3d92321.519ba693c39229db
+ 7d8bd52862c93f85.11efc63e5da6b828.4e786904867b4e98.7e5ae827adc09b4e
+ a4ed2895f4395df1.dbe42b7944750f58.c1847f53eb6301e7.a72a18ba4322177e
+ d716d16e33415eb7.ea1c3715818a8987.92b06e59309df93a.285730b82242d819
+ 5d2d2e8de5ae1bc8
+
+VMOVNTPD_128(reg)
+ before
+ a2f80ea529f21c3a.f4d04c9f3cedfe04.9ce3e67eb1706462.9fc8b0017136f2be
+ 5303ca6c89991619.d5e816152b4af804.4c8434206fb4da95.c298c337c939a89f
+ cc9b604fa12f4611.582aa9ba1a6309e2.554d1e6858e128cb.d9eb22e755b2d608
+ 690dcab80e40e8d0.5762837c2845edca.15889fc0078389b1.be8f4afd30ae3926
+ 4e4eb56576388d24
+ after
+ a2f80ea529f21c3a.f4d04c9f3cedfe04.9ce3e67eb1706462.9fc8b0017136f2be
+ 5303ca6c89991619.d5e816152b4af804.4c8434206fb4da95.c298c337c939a89f
+ cc9b604fa12f4611.582aa9ba1a6309e2.554d1e6858e128cb.d9eb22e755b2d608
+ 690dcab80e40e8d0.5762837c2845edca.15889fc0078389b1.be8f4afd30ae3926
+ 4e4eb56576388d24
+VMOVNTPD_128(mem)
+ before
+ 66f5e10b445d8d2f.86a307156b5938ff.af5c1f456efb60ea.e682b39519273bf3
+ e05049dbb528f673.7fa910d15505714d.3de3fa030a911d6b.268756542958783c
+ 992b69c2e6a5841b.b06de25768d0d064.dbc58ea11813e17c.2fe38468d4a27c38
+ 6d51beaaf2e0f354.753a7a153f4791f0.66cc590bb38e6847.5ee23a3db5928595
+ 10cf733f68b3cdfc
+ after
+ 66f5e10b445d8d2f.86a307156b5938ff.66cc590bb38e6847.5ee23a3db5928595
+ e05049dbb528f673.7fa910d15505714d.3de3fa030a911d6b.268756542958783c
+ 992b69c2e6a5841b.b06de25768d0d064.dbc58ea11813e17c.2fe38468d4a27c38
+ 6d51beaaf2e0f354.753a7a153f4791f0.66cc590bb38e6847.5ee23a3db5928595
+ 10cf733f68b3cdfc
+
+VMOVNTPD_128(reg)
+ before
+ 9ff72bda8a91911c.3990c281f6e6fe4a.2a5bd37676f5f09e.bac5d62df80d6df9
+ 68a75e7ab7b90c9f.d7b2f3310ec26228.2b1de9e6aa67281a.b47c81f3029dadbd
+ c829098b8ab67c32.2484cca85481db1a.d3cdb9d176287610.2ebdd749ed49e4c0
+ 19ca26799f141b80.fcd3cad1e72e254d.80b53da477c4162a.0553531cd61dce2d
+ 150c7056d9252631
+ after
+ 9ff72bda8a91911c.3990c281f6e6fe4a.2a5bd37676f5f09e.bac5d62df80d6df9
+ 68a75e7ab7b90c9f.d7b2f3310ec26228.2b1de9e6aa67281a.b47c81f3029dadbd
+ c829098b8ab67c32.2484cca85481db1a.d3cdb9d176287610.2ebdd749ed49e4c0
+ 19ca26799f141b80.fcd3cad1e72e254d.80b53da477c4162a.0553531cd61dce2d
+ 150c7056d9252631
+VMOVNTPD_128(mem)
+ before
+ 3ab2ade5116ea9f8.b8d5b3b093602636.3b686798e0d5fbed.8d2173c948c74317
+ 501283b39a0413ad.0198ab9d0225d8ff.bd1221e95d831a26.565f56ad85be3a81
+ 33f870ae91f1207d.505d0baa87ef6e88.5e9c73b07a433d23.36b9e2bdcc353715
+ bf30eec111438b93.0171cd45be4b247d.fad1d9da52212210.8b7d1463b6b6767e
+ aff5e70de1cf3269
+ after
+ 3ab2ade5116ea9f8.b8d5b3b093602636.fad1d9da52212210.8b7d1463b6b6767e
+ 501283b39a0413ad.0198ab9d0225d8ff.bd1221e95d831a26.565f56ad85be3a81
+ 33f870ae91f1207d.505d0baa87ef6e88.5e9c73b07a433d23.36b9e2bdcc353715
+ bf30eec111438b93.0171cd45be4b247d.fad1d9da52212210.8b7d1463b6b6767e
+ aff5e70de1cf3269
+
+VMOVNTPD_128(reg)
+ before
+ 006e5726e90ba882.d0867bd83705111c.7121efd944c43689.6d7ecf51022a831a
+ d934601a69f71474.42c593df1e446e44.fab66cd2b4e6df59.936fd202a5691d6d
+ 9592fe55fd1eb1eb.f1bbb0c2e30b5d36.f97f409cab3e5c98.48705dda57eaab35
+ 92d62e43420cbc95.b932506da1669b1e.cac768a3c457e9f3.684decc435b9ea9d
+ cfd2fbab5ae396d1
+ after
+ 006e5726e90ba882.d0867bd83705111c.7121efd944c43689.6d7ecf51022a831a
+ d934601a69f71474.42c593df1e446e44.fab66cd2b4e6df59.936fd202a5691d6d
+ 9592fe55fd1eb1eb.f1bbb0c2e30b5d36.f97f409cab3e5c98.48705dda57eaab35
+ 92d62e43420cbc95.b932506da1669b1e.cac768a3c457e9f3.684decc435b9ea9d
+ cfd2fbab5ae396d1
+VMOVNTPD_128(mem)
+ before
+ 58ca067de3746bfe.2a4aea50d44e711b.75f7edcc7562e42a.c8d9df539cbec216
+ e1038a25ec762450.ba3c30e84d6f0c2c.03d606cb7a0af384.5103a118cefe22ac
+ 4547028f90f77ef2.9ff6fc784cfbc872.3e9a1457cc6a8658.c08faa5ef6a34662
+ 6063eaa7eb033511.33c5486a6b7fe29a.0211945a898f57d3.71caf692b13969e3
+ c000821e9b4dc9dc
+ after
+ 58ca067de3746bfe.2a4aea50d44e711b.0211945a898f57d3.71caf692b13969e3
+ e1038a25ec762450.ba3c30e84d6f0c2c.03d606cb7a0af384.5103a118cefe22ac
+ 4547028f90f77ef2.9ff6fc784cfbc872.3e9a1457cc6a8658.c08faa5ef6a34662
+ 6063eaa7eb033511.33c5486a6b7fe29a.0211945a898f57d3.71caf692b13969e3
+ c000821e9b4dc9dc
+
+VMOVNTPD_256(reg)
+ before
+ 097c48704f6aa0f8.0d23bf591aa505d9.d3f4122c4686964f.2a0503c2ca842221
+ a88c46f2691d2be5.2a52fb9238e9a975.dcd155287a9c1f3e.9444dc7aad56a56d
+ f87a781286f0a54c.92be1c3c62dbde12.a8a60dcca24eba12.1b989b6e4e0f9ae4
+ 5793d83b42724bdc.20319d44b38860db.94c136835b27a378.9acebd8ac8bdbeb2
+ efb2bcba376ccc02
+ after
+ 097c48704f6aa0f8.0d23bf591aa505d9.d3f4122c4686964f.2a0503c2ca842221
+ a88c46f2691d2be5.2a52fb9238e9a975.dcd155287a9c1f3e.9444dc7aad56a56d
+ f87a781286f0a54c.92be1c3c62dbde12.a8a60dcca24eba12.1b989b6e4e0f9ae4
+ 5793d83b42724bdc.20319d44b38860db.94c136835b27a378.9acebd8ac8bdbeb2
+ efb2bcba376ccc02
+VMOVNTPD_256(mem)
+ before
+ f40f16eab8268101.202364d9382c593e.b278fa9747fbeafd.fc6ccdb940b3161c
+ 87b3460666fa99da.ae76175804ac0b21.225fb0203c4039a3.3cf4ccdaed7f4ea9
+ 8268c8fa5ef1d0ba.5fd8ed24437d9d2f.4eb239caab6409fa.b1a53152ff1688cc
+ c3fb19b3bb19e2cc.8d95e2aa902c4a15.103d1383b272162e.b5caf88d12040030
+ a5b11bf7c1d6f182
+ after
+ c3fb19b3bb19e2cc.8d95e2aa902c4a15.103d1383b272162e.b5caf88d12040030
+ 87b3460666fa99da.ae76175804ac0b21.225fb0203c4039a3.3cf4ccdaed7f4ea9
+ 8268c8fa5ef1d0ba.5fd8ed24437d9d2f.4eb239caab6409fa.b1a53152ff1688cc
+ c3fb19b3bb19e2cc.8d95e2aa902c4a15.103d1383b272162e.b5caf88d12040030
+ a5b11bf7c1d6f182
+
+VMOVNTPD_256(reg)
+ before
+ dda498fda817996e.2438b41b9a7d8a3d.96f8f35488444f7e.46ccb9366d771b6a
+ b9f06a096453329f.83eb152016298539.d44e1a8fc651e717.ca2aa8cff77dd5db
+ 95e18d899117f8c2.bae0b8ac4c2a8eeb.a5e355c8e7e04f8b.79245a3a6c9300ad
+ cdc3fde7caee2982.a6e219ad578b6380.63039f69867cc388.30874d64e9c2570b
+ c91dfc3789189721
+ after
+ dda498fda817996e.2438b41b9a7d8a3d.96f8f35488444f7e.46ccb9366d771b6a
+ b9f06a096453329f.83eb152016298539.d44e1a8fc651e717.ca2aa8cff77dd5db
+ 95e18d899117f8c2.bae0b8ac4c2a8eeb.a5e355c8e7e04f8b.79245a3a6c9300ad
+ cdc3fde7caee2982.a6e219ad578b6380.63039f69867cc388.30874d64e9c2570b
+ c91dfc3789189721
+VMOVNTPD_256(mem)
+ before
+ 21b2e3a069a07c1d.bde2b791ab65ff8c.24bfb50e5459be24.6cfaf5e040b17fb7
+ 14147f8ca567c228.c08ab5f2d107b68c.0e4107bb5e9f5b02.1a145198b00cbfc6
+ 7f0d4ae557772471.3406f576d7608c2d.41358ba09169f846.cb9cb1fd7218be61
+ 3c6bc2999edf5f22.74a372895afcbb1c.9967bda90ac34f1e.d9e0107b2361b934
+ a12a6b7e5f74ebea
+ after
+ 3c6bc2999edf5f22.74a372895afcbb1c.9967bda90ac34f1e.d9e0107b2361b934
+ 14147f8ca567c228.c08ab5f2d107b68c.0e4107bb5e9f5b02.1a145198b00cbfc6
+ 7f0d4ae557772471.3406f576d7608c2d.41358ba09169f846.cb9cb1fd7218be61
+ 3c6bc2999edf5f22.74a372895afcbb1c.9967bda90ac34f1e.d9e0107b2361b934
+ a12a6b7e5f74ebea
+
+VMOVNTPD_256(reg)
+ before
+ 7fc7bc72c1dc922f.28f8629393a82f67.dcad2997f5688004.f2a319c2e5ba1db3
+ d00301c3e525e8b1.1f81a6bf55e0506e.c870140c452f1792.28b41cd83d5a1d34
+ ee2a35de68dc291a.fdd20b09fd927d60.93383155e5debb71.186841d52ead0dcb
+ 3687542de68c9316.9eb70c5daacb736c.9b517bdc7200a94f.9c8904a7d5c1a7a4
+ 91e4e1384ea1a8ed
+ after
+ 7fc7bc72c1dc922f.28f8629393a82f67.dcad2997f5688004.f2a319c2e5ba1db3
+ d00301c3e525e8b1.1f81a6bf55e0506e.c870140c452f1792.28b41cd83d5a1d34
+ ee2a35de68dc291a.fdd20b09fd927d60.93383155e5debb71.186841d52ead0dcb
+ 3687542de68c9316.9eb70c5daacb736c.9b517bdc7200a94f.9c8904a7d5c1a7a4
+ 91e4e1384ea1a8ed
+VMOVNTPD_256(mem)
+ before
+ d3455576b35acbcf.04675a1ef9c16052.defb25a77596edbc.3b06ef0f87211dd5
+ 3e78db4c23f7cd79.b417441b4008cd7a.996cd2d37cffa97c.cea48758c1ce53b2
+ ae49efa6b8846a15.a2e10d9255ec1639.abd48fcddb1361da.b2784125bb91868f
+ fe830d708e0e5ecf.2a12b1eed4f9763c.f000d982adddd2ff.41cc18e111f9f31b
+ d9ed08f8608fd600
+ after
+ fe830d708e0e5ecf.2a12b1eed4f9763c.f000d982adddd2ff.41cc18e111f9f31b
+ 3e78db4c23f7cd79.b417441b4008cd7a.996cd2d37cffa97c.cea48758c1ce53b2
+ ae49efa6b8846a15.a2e10d9255ec1639.abd48fcddb1361da.b2784125bb91868f
+ fe830d708e0e5ecf.2a12b1eed4f9763c.f000d982adddd2ff.41cc18e111f9f31b
+ d9ed08f8608fd600
+
+VMOVNTPS_128(reg)
+ before
+ d4260dd644e16aeb.0cf4b196c2a064d4.a8f62c9b5abc2a2e.44bc2bdc0e69b71a
+ 90c524e7587aec87.b36658046f463950.78d87b0582c06ebc.83d401c91bc4cd55
+ 6714489738e79881.cfa67da6b10d996f.f6069898e8927d92.8913d734f0f9d0dc
+ b760755281b3aa84.3c809c69a600405b.7eca81c02abc955b.32472909a8147cdc
+ 593a74345f228c81
+ after
+ d4260dd644e16aeb.0cf4b196c2a064d4.a8f62c9b5abc2a2e.44bc2bdc0e69b71a
+ 90c524e7587aec87.b36658046f463950.78d87b0582c06ebc.83d401c91bc4cd55
+ 6714489738e79881.cfa67da6b10d996f.f6069898e8927d92.8913d734f0f9d0dc
+ b760755281b3aa84.3c809c69a600405b.7eca81c02abc955b.32472909a8147cdc
+ 593a74345f228c81
+VMOVNTPS_128(mem)
+ before
+ dcb933a1322ebdf7.daf5a784ce6a5d3d.d6bf3137672be943.6c7131eae1cdefc3
+ 9690e23c3c44cb68.2d1fda9abc99ee58.7831b9fe129b5151.1c47a580ab4eca78
+ 628bfdf19a717203.0d2a0bfee6cb9980.00a0aea8c35b34b2.ea98d7f024cd6124
+ 1e7601ac67c06df2.d462351ee98c9962.49da8e2395774d91.32b0c5a4e7d5ef73
+ 4fda6a0a90f3b012
+ after
+ dcb933a1322ebdf7.daf5a784ce6a5d3d.49da8e2395774d91.32b0c5a4e7d5ef73
+ 9690e23c3c44cb68.2d1fda9abc99ee58.7831b9fe129b5151.1c47a580ab4eca78
+ 628bfdf19a717203.0d2a0bfee6cb9980.00a0aea8c35b34b2.ea98d7f024cd6124
+ 1e7601ac67c06df2.d462351ee98c9962.49da8e2395774d91.32b0c5a4e7d5ef73
+ 4fda6a0a90f3b012
+
+VMOVNTPS_128(reg)
+ before
+ 9f63c28dbcb1e2ad.a51c6959c03d7962.df12546560692baa.2ea9d55aa4fc591b
+ 7d98ca98079ebff0.d24bb1e5c0f5527e.8a87643fe8ed8b03.8ddafd390df5147c
+ 44c37c990c438485.83cd553b84f3b373.320e62181ca4f519.403984acec6e3adf
+ 5231d6fb672e6d1b.926fd2462743596c.31f1495c991ba49a.2591e59f5b748670
+ 16b09cfe7912b55d
+ after
+ 9f63c28dbcb1e2ad.a51c6959c03d7962.df12546560692baa.2ea9d55aa4fc591b
+ 7d98ca98079ebff0.d24bb1e5c0f5527e.8a87643fe8ed8b03.8ddafd390df5147c
+ 44c37c990c438485.83cd553b84f3b373.320e62181ca4f519.403984acec6e3adf
+ 5231d6fb672e6d1b.926fd2462743596c.31f1495c991ba49a.2591e59f5b748670
+ 16b09cfe7912b55d
+VMOVNTPS_128(mem)
+ before
+ f16025b5605583d0.022dd32bb5eab55c.ddfda2f4c5f20097.e47c1577faddd52f
+ 906efcb12c47abf5.af057093910499f5.3e4343307b0b641d.a7fdc2d5db77c487
+ d1a69edcfaf7eaf9.b703a7a098075591.930c30e6659b402d.d6bf4ce2d973ad4c
+ 8ed48624e56efc08.747576bf657f25dd.b626e5029ead51f0.cd0db00b905fcb2a
+ e834e9ba9bc75bcf
+ after
+ f16025b5605583d0.022dd32bb5eab55c.b626e5029ead51f0.cd0db00b905fcb2a
+ 906efcb12c47abf5.af057093910499f5.3e4343307b0b641d.a7fdc2d5db77c487
+ d1a69edcfaf7eaf9.b703a7a098075591.930c30e6659b402d.d6bf4ce2d973ad4c
+ 8ed48624e56efc08.747576bf657f25dd.b626e5029ead51f0.cd0db00b905fcb2a
+ e834e9ba9bc75bcf
+
+VMOVNTPS_128(reg)
+ before
+ 8380f35d963698e4.a4c430730aba9d4d.44a5d85a95f94484.845bdf70424d5395
+ fa3dca5e1e38c018.f04119b784e688f5.81e0c9dfc300ef34.da78991c6e870146
+ a9b76b2bcf590d15.4c19bbdb6fff7a2b.897245b88c206296.92498ff23e681830
+ ec39d02f4326bc87.951694cbe90f2f1c.b6a649538be5d858.899a3ddfcdfb547e
+ 9c371fcd374d715d
+ after
+ 8380f35d963698e4.a4c430730aba9d4d.44a5d85a95f94484.845bdf70424d5395
+ fa3dca5e1e38c018.f04119b784e688f5.81e0c9dfc300ef34.da78991c6e870146
+ a9b76b2bcf590d15.4c19bbdb6fff7a2b.897245b88c206296.92498ff23e681830
+ ec39d02f4326bc87.951694cbe90f2f1c.b6a649538be5d858.899a3ddfcdfb547e
+ 9c371fcd374d715d
+VMOVNTPS_128(mem)
+ before
+ a5ebb2aa99692af8.1f11f7d6192a081b.a8051f730b2562f4.65cad01b5cdc8e26
+ 818371610e5b3c7c.9d89db8cebf22e7d.5fb2d8bff34ad0de.f328d67c9c91c0ac
+ 0cccd8ddb32f6315.c4ee79bd55096a58.97e93c9cbd8c3507.ba0d57e2e78eaa95
+ 2290630ca3f25bee.ef8cccd5f3fbf859.2c75c5f484f64d9a.17c550b9d861878d
+ 669cbc6e0b969442
+ after
+ a5ebb2aa99692af8.1f11f7d6192a081b.2c75c5f484f64d9a.17c550b9d861878d
+ 818371610e5b3c7c.9d89db8cebf22e7d.5fb2d8bff34ad0de.f328d67c9c91c0ac
+ 0cccd8ddb32f6315.c4ee79bd55096a58.97e93c9cbd8c3507.ba0d57e2e78eaa95
+ 2290630ca3f25bee.ef8cccd5f3fbf859.2c75c5f484f64d9a.17c550b9d861878d
+ 669cbc6e0b969442
+
+VMOVNTPS_256(reg)
+ before
+ 04de966b1db80d5e.9f9b8fd9fbafdf34.7aafcf416354142c.fa24f1b46495d3c4
+ 4bd6dd1eaa532e8d.5fbbd630d673ac12.c0a2806b3ea1f97c.ddc03bc97a7484b1
+ 98d28af14cf3327c.3ebbb6fd50497db5.1fb3dbc0226de3f6.b116201de19f1c8c
+ 471c9b52a22556d7.1866ab2d863d1049.f22cdaadab451045.52f21a9eb6235782
+ 9c20a737140af0be
+ after
+ 04de966b1db80d5e.9f9b8fd9fbafdf34.7aafcf416354142c.fa24f1b46495d3c4
+ 4bd6dd1eaa532e8d.5fbbd630d673ac12.c0a2806b3ea1f97c.ddc03bc97a7484b1
+ 98d28af14cf3327c.3ebbb6fd50497db5.1fb3dbc0226de3f6.b116201de19f1c8c
+ 471c9b52a22556d7.1866ab2d863d1049.f22cdaadab451045.52f21a9eb6235782
+ 9c20a737140af0be
+VMOVNTPS_256(mem)
+ before
+ 6b6c42d41863a46d.b4010aac4674d549.c9892faa945c1ff9.945a7b9d74b4ba16
+ 9ba16761de372ebb.3bcdd56ad46ced7f.2df0c06295b167f2.6389b9fc1a461e14
+ 088d93ca80944cd3.38ccf8fae99ad824.2067d83fa548a35f.b9059035388878ed
+ 8efa40fb1c86b8e2.07496dc72089d3e5.7ebaf52fe12e906d.f41afcb66a05034a
+ 6e14faea4d49fdda
+ after
+ 8efa40fb1c86b8e2.07496dc72089d3e5.7ebaf52fe12e906d.f41afcb66a05034a
+ 9ba16761de372ebb.3bcdd56ad46ced7f.2df0c06295b167f2.6389b9fc1a461e14
+ 088d93ca80944cd3.38ccf8fae99ad824.2067d83fa548a35f.b9059035388878ed
+ 8efa40fb1c86b8e2.07496dc72089d3e5.7ebaf52fe12e906d.f41afcb66a05034a
+ 6e14faea4d49fdda
+
+VMOVNTPS_256(reg)
+ before
+ 853e853e7ce09f46.09b5ece0ce172f13.0492323d15c6196e.23b5931c656eea47
+ 93e5991c9457283d.548a1266b1556c93.8bf142c966dbe76a.eb232cf44c146d1b
+ f55532f1313ad269.4d442f77e24c2d8e.f8b399d5ac567985.b1d23ea2b22dd412
+ 08da4c2aed13da77.cfb1bd017c062c2f.a72433ce85c30b6d.538c4412b4c4dc5b
+ ac1eba306de54120
+ after
+ 853e853e7ce09f46.09b5ece0ce172f13.0492323d15c6196e.23b5931c656eea47
+ 93e5991c9457283d.548a1266b1556c93.8bf142c966dbe76a.eb232cf44c146d1b
+ f55532f1313ad269.4d442f77e24c2d8e.f8b399d5ac567985.b1d23ea2b22dd412
+ 08da4c2aed13da77.cfb1bd017c062c2f.a72433ce85c30b6d.538c4412b4c4dc5b
+ ac1eba306de54120
+VMOVNTPS_256(mem)
+ before
+ 97541ce8fa9dbf8d.26c0e43167707c12.b59b3aee9b9125a3.f4900d218dadd8cc
+ f2f9e72776f711cf.ac52f57438ddf4e7.ddd0212c5cf9d615.3a4322385fa01d4e
+ 98db96d7fefff412.f6de7b5effe47da1.221aeea6db49f9b2.d7886e81972816a0
+ 64c4a5e6adc22481.61ae725a551354ed.5f461d48338d4ba5.26aded67d2d2ff6e
+ 83fc9b56ac291363
+ after
+ 64c4a5e6adc22481.61ae725a551354ed.5f461d48338d4ba5.26aded67d2d2ff6e
+ f2f9e72776f711cf.ac52f57438ddf4e7.ddd0212c5cf9d615.3a4322385fa01d4e
+ 98db96d7fefff412.f6de7b5effe47da1.221aeea6db49f9b2.d7886e81972816a0
+ 64c4a5e6adc22481.61ae725a551354ed.5f461d48338d4ba5.26aded67d2d2ff6e
+ 83fc9b56ac291363
+
+VMOVNTPS_256(reg)
+ before
+ 49c275bac0ba8f2c.3481903ea04b5c49.470fd7d6d9f6b477.72202bfe80d1871b
+ d64b76ffaa10af75.e2ded3cdf2a75996.054da53d2418dbea.357393b4df226a40
+ 84e39a9107b7aee9.4ca7eb7ebfe0d793.f7b4d8fbd40503f3.860dd1566c8bb03f
+ b1d5dddc723cc935.4ca8533c2504926c.79906c7d8549683d.3fb861d041181545
+ 3e41c00f7dd6557e
+ after
+ 49c275bac0ba8f2c.3481903ea04b5c49.470fd7d6d9f6b477.72202bfe80d1871b
+ d64b76ffaa10af75.e2ded3cdf2a75996.054da53d2418dbea.357393b4df226a40
+ 84e39a9107b7aee9.4ca7eb7ebfe0d793.f7b4d8fbd40503f3.860dd1566c8bb03f
+ b1d5dddc723cc935.4ca8533c2504926c.79906c7d8549683d.3fb861d041181545
+ 3e41c00f7dd6557e
+VMOVNTPS_256(mem)
+ before
+ 5d7468fd39d02b15.b86f3c4d882a3c04.c0ad87f53d1f454f.e72c5d2dd2714875
+ 7a1dd78894135436.f4fbb24ee40d4303.82810394253cad66.9dd6a8785708dd47
+ 6f08899ba7aa8b0f.c3c63a4c237219dd.6ff14405f96786dd.f7d848cbb19a645e
+ 1900f82190a18eca.7f1cd3b4e0e3fb3f.64cac535d3ac8be1.517f39907cb41967
+ 0717773553e1370d
+ after
+ 1900f82190a18eca.7f1cd3b4e0e3fb3f.64cac535d3ac8be1.517f39907cb41967
+ 7a1dd78894135436.f4fbb24ee40d4303.82810394253cad66.9dd6a8785708dd47
+ 6f08899ba7aa8b0f.c3c63a4c237219dd.6ff14405f96786dd.f7d848cbb19a645e
+ 1900f82190a18eca.7f1cd3b4e0e3fb3f.64cac535d3ac8be1.517f39907cb41967
+ 0717773553e1370d
+
+VPACKSSWB_128(reg)
+ before
+ 75ecff25d2aefbfd.55d3a1086b041793.854976f1b8ef25d5.3bd6020ed218799e
+ f749cbcc96a5a1e3.fd4b013b53e0e297.3298216f461fd24a.d1e1777d10b60c3f
+ e97cd9963a55646a.ee3593a66540ad02.e057cf9a26013f4b.03b9a06fa99300f1
+ a7cf25ef5b47823f.045dd435bc3132ff.ecd07cdef521a884.ab29facfbaba10df
+ a6fc00885e37f936
+ after
+ 0000000000000000.0000000000000000.80807f7f7f80807f.7f7f7f80807f7f7f
+ f749cbcc96a5a1e3.fd4b013b53e0e297.3298216f461fd24a.d1e1777d10b60c3f
+ e97cd9963a55646a.ee3593a66540ad02.e057cf9a26013f4b.03b9a06fa99300f1
+ a7cf25ef5b47823f.045dd435bc3132ff.ecd07cdef521a884.ab29facfbaba10df
+ a6fc00885e37f936
+VPACKSSWB_128(mem)
+ before
+ d0ff2e88b2167722.8c8fa9439409350d.1b8f3ed574be2ebb.b35024a74f0949a0
+ 05fe00bad16446ce.f60863fe8226b981.10964f70aaf35c61.8f23c361cf475d4b
+ 21c5f30ad82d2167.40864d8cc02b4c46.bd4082f37adc7a1e.dd95567811672133
+ 00208164e27bc518.c654665aeba32809.ff57534bff86421e.f9f2d858b2f3d101
+ 4086456e4d79a864
+ after
+ d0ff2e88b2167722.8c8fa9439409350d.1b8f3ed574be2ebb.b35024a74f0949a0
+ 05fe00bad16446ce.f60863fe8226b981.10964f70aaf35c61.8f23c361cf475d4b
+ 0000000000000000.0000000000000000.7f7f7f7f807f7f7f.7f7f807f8080807f
+ 00208164e27bc518.c654665aeba32809.ff57534bff86421e.f9f2d858b2f3d101
+ 4086456e4d79a864
+
+VPACKSSWB_128(reg)
+ before
+ 0c9c9a247f85e406.7eda28b40b5ced0e.e3c0a7d29e1a8a76.b2a83e6255fd718c
+ ba81d1e8e4a2be94.77c163e671db5775.f5140d62751cad39.b2ffc026994bc295
+ a681e825165c75b9.c79fafe72d05bd78.569d95750e36cffc.db285382e67ef264
+ 2ce8da47b43f4322.4a4186a15de5dc44.64a73a7602f32a6e.09ef756259a1bd26
+ 181fa2b20dc1df07
+ after
+ 0000000000000000.0000000000000000.7f807f80807f8080.807f7f8080808080
+ ba81d1e8e4a2be94.77c163e671db5775.f5140d62751cad39.b2ffc026994bc295
+ a681e825165c75b9.c79fafe72d05bd78.569d95750e36cffc.db285382e67ef264
+ 2ce8da47b43f4322.4a4186a15de5dc44.64a73a7602f32a6e.09ef756259a1bd26
+ 181fa2b20dc1df07
+VPACKSSWB_128(mem)
+ before
+ e386545e1fe91332.a802a3ba57d8657a.dc7366021d876f04.797ef8d3efe0fa39
+ 48ee0952aa2516d4.761b40ea9eb2176e.5901caf488f833e5.f36ecbf771887d0a
+ 22243c7acb82a418.f27eab43225995a9.9db62f65ba43e413.2cc2b04e2277ed8c
+ 4df469c39d0b792b.7878e231815a1ad9.84600f40d0743eb9.82c8a244a13a876c
+ 4fca9d46885c8655
+ after
+ e386545e1fe91332.a802a3ba57d8657a.dc7366021d876f04.797ef8d3efe0fa39
+ 48ee0952aa2516d4.761b40ea9eb2176e.5901caf488f833e5.f36ecbf771887d0a
+ 0000000000000000.0000000000000000.807f7f7f7f808080.7f80807f80807f7f
+ 4df469c39d0b792b.7878e231815a1ad9.84600f40d0743eb9.82c8a244a13a876c
+ 4fca9d46885c8655
+
+VPACKSSWB_128(reg)
+ before
+ f1159dbe736928f4.a5290c173dcc5038.6456e1205740e3a7.e9c9e871e598fc04
+ c2f59e1affeea7f5.0591a164c6d2e66d.1262a27d3f982cc2.aabe35e416badb1f
+ 1fb69dc4c7763f03.4bf6a5945428f7f3.dde822b2d6ed30d4.a20b72857ee69737
+ 65a3952a688d2ecb.5226939504da3ef9.23365e2db7cb2c89.ad7c1b403a29ec77
+ a6ddad01658e950c
+ after
+ 0000000000000000.0000000000000000.807f807f807f7f80.7f807f7f807f7f80
+ c2f59e1affeea7f5.0591a164c6d2e66d.1262a27d3f982cc2.aabe35e416badb1f
+ 1fb69dc4c7763f03.4bf6a5945428f7f3.dde822b2d6ed30d4.a20b72857ee69737
+ 65a3952a688d2ecb.5226939504da3ef9.23365e2db7cb2c89.ad7c1b403a29ec77
+ a6ddad01658e950c
+VPACKSSWB_128(mem)
+ before
+ 6bf9a3b51c214f22.ee0a82b67dc0aef9.f5ebe752f2f578a9.3f9751587ebe5c8e
+ d69e79467aefd6e5.173561d6a39afc38.12121eb73984612f.8d56f7a1c853fb8f
+ c596aba29c03e57f.3c712cf575a75334.8367b2b0f594b5b8.68c04d7331154737
+ 12aeb5b39d6a391f.b90ae17f9074f19a.26b52129432f2f70.2e214e3a53917a33
+ 3ac5f562cd52d02f
+ after
+ 6bf9a3b51c214f22.ee0a82b67dc0aef9.f5ebe752f2f578a9.3f9751587ebe5c8e
+ d69e79467aefd6e5.173561d6a39afc38.12121eb73984612f.8d56f7a1c853fb8f
+ 0000000000000000.0000000000000000.8080807f7f7f7f7f.7f7f7f7f80808080
+ 12aeb5b39d6a391f.b90ae17f9074f19a.26b52129432f2f70.2e214e3a53917a33
+ 3ac5f562cd52d02f
+
+VPAVGB_128(reg)
+ before
+ e7f8415739e487d6.9bb214679a2e8eef.ea4c7be08f8c1016.d6cae60e3e648c82
+ 93052b8633d4d9d5.3a6e43a9ae5ea01c.2c83f6850e7bed54.6e707e4c033c881b
+ 983ab05958ad03d7.cdadbe65f5032ad1.d9fa4ed8aacec3ff.cb7463cdadc5de66
+ 54e1cd3d43fb4089.2e3d01878c2be93b.4efe8046ff10cfc3.caa2137e590a4b91
+ 45c6094c22178bc5
+ after
+ 0000000000000000.0000000000000000.83bfa2af5ca5d8aa.9d72718d5881b341
+ 93052b8633d4d9d5.3a6e43a9ae5ea01c.2c83f6850e7bed54.6e707e4c033c881b
+ 983ab05958ad03d7.cdadbe65f5032ad1.d9fa4ed8aacec3ff.cb7463cdadc5de66
+ 54e1cd3d43fb4089.2e3d01878c2be93b.4efe8046ff10cfc3.caa2137e590a4b91
+ 45c6094c22178bc5
+VPAVGB_128(mem)
+ before
+ 1aacc12225f95a30.21477d9f914ace96.3be889fb8fe19985.e7dc873ca8ce4d4d
+ 231fb7eb7dbb73fe.5db8bce9dd27e7ab.ce7bd1ad1931f5dc.00de5f2441927949
+ 3ded6895476a935b.62808789c31ec774.c4c2558a4628ba6c.f551046c67eb8e63
+ 44e04f0b9e117672.8eebd8eae1b9ac9c.f989917c33d1a460.2180737fb562c946
+ e2b9a7c9c885669e
+ after
+ 1aacc12225f95a30.21477d9f914ace96.3be889fb8fe19985.e7dc873ca8ce4d4d
+ 231fb7eb7dbb73fe.5db8bce9dd27e7ab.ce7bd1ad1931f5dc.00de5f2441927949
+ 0000000000000000.0000000000000000.85b2add45489c7b1.74dd733075b0634b
+ 44e04f0b9e117672.8eebd8eae1b9ac9c.f989917c33d1a460.2180737fb562c946
+ e2b9a7c9c885669e
+
+VPAVGB_128(reg)
+ before
+ 93469cb53cdfa118.15c5e8399ebcd76f.3b44ad78d086d0d0.4a9c0171fb396fe5
+ 90754eb2abfdb560.8a68af0b64777380.c6d9019f2e1170bc.91c62253bb6bd626
+ 3590b929b469df21.8095206e0c4f06ce.8cf4d1cb97e4c70b.abd46f108e739650
+ dde4da87f0b25b08.d317b84cb1504c88.e7e21768a68d1369.74936493915e6b8f
+ c8cd7dc7df37110e
+ after
+ 0000000000000000.0000000000000000.a9e769b5637b9c64.9ecd4932a56fb63b
+ 90754eb2abfdb560.8a68af0b64777380.c6d9019f2e1170bc.91c62253bb6bd626
+ 3590b929b469df21.8095206e0c4f06ce.8cf4d1cb97e4c70b.abd46f108e739650
+ dde4da87f0b25b08.d317b84cb1504c88.e7e21768a68d1369.74936493915e6b8f
+ c8cd7dc7df37110e
+VPAVGB_128(mem)
+ before
+ 834e369a950a43fa.e6bcac38fe6164c1.5fbcf2926f8400d8.34efd1e2f7988e84
+ 81e40cf7cee3be7f.ab662ba9770437f7.004e4a2d63f9dfea.cf66faa6278f7505
+ 9e5a7acba7cf3dc7.872c5344f9261057.929a3c08a9baa5ec.14958e1ed100039b
+ b67bfc003bda7e01.d85c207720542a8c.f16c450e5cd40e07.60c689b8927775f0
+ 0d47e8de067e07b0
+ after
+ 834e369a950a43fa.e6bcac38fe6164c1.5fbcf2926f8400d8.34efd1e2f7988e84
+ 81e40cf7cee3be7f.ab662ba9770437f7.004e4a2d63f9dfea.cf66faa6278f7505
+ 0000000000000000.0000000000000000.30859e6069bf70e1.82abe6c48f948245
+ b67bfc003bda7e01.d85c207720542a8c.f16c450e5cd40e07.60c689b8927775f0
+ 0d47e8de067e07b0
+
+VPAVGB_128(reg)
+ before
+ 7862a6fec7a4f589.a5140f83a60e3b57.f9408fac8719c343.f990e02d9852d56a
+ fd64bf8374727a24.47f22d41057931f6.45259b51ca011527.86d289507a40b73f
+ f8982fd9a676d330.78ded42474261b09.1a5740d186985ce5.74fdbc631dab6fb2
+ c54cf26cfc3b3c57.14a77f1a0e22b6bd.d2227b98576bd629.9fdff5529e9ebbf1
+ e342b10918255525
+ after
+ 0000000000000000.0000000000000000.303e6e91a84d3986.7de8a35a4c769379
+ fd64bf8374727a24.47f22d41057931f6.45259b51ca011527.86d289507a40b73f
+ f8982fd9a676d330.78ded42474261b09.1a5740d186985ce5.74fdbc631dab6fb2
+ c54cf26cfc3b3c57.14a77f1a0e22b6bd.d2227b98576bd629.9fdff5529e9ebbf1
+ e342b10918255525
+VPAVGB_128(mem)
+ before
+ 1cf36b74a74dfa7d.c0ca05a80f4df145.f718aa0eef78be3e.cbd14612d806bd9e
+ 25be9f8069216523.456063f97d392da8.fdfcd2eb3434efb7.5fb19faba5f34ef1
+ dc6fc91777ad5443.b05808cce28a2d29.0121729ff8630455.ec0f81d05bc0c4ce
+ 1cd16627effe810a.5cfff08bd9cd2c77.e15106155810ba43.cc35e8eb95f95de0
+ 5c70d169f02853d3
+ after
+ 1cf36b74a74dfa7d.c0ca05a80f4df145.f718aa0eef78be3e.cbd14612d806bd9e
+ 25be9f8069216523.456063f97d392da8.fdfcd2eb3434efb7.5fb19faba5f34ef1
+ 0000000000000000.0000000000000000.fa8abe7d9256d77b.95c1735fbf7d86c8
+ 1cd16627effe810a.5cfff08bd9cd2c77.e15106155810ba43.cc35e8eb95f95de0
+ 5c70d169f02853d3
+
+VPAVGW_128(reg)
+ before
+ f90b36b708dbe355.c1b2f19aed1fa8a4.a7a118a4ff8d683c.78590a397047cdae
+ fd541540779e4810.a6dce65e8c1c873c.ec897b81ef561b24.a205faf85a15f9c2
+ c595696fdcfbbfb0.a91cc15ee802d8ff.8705159045b482dc.3a20533c3585f9aa
+ ad1c2fb2d08084e2.a43efe861edc5819.d35fe23c9e34d810.1e788ff21aa48a92
+ 28d72c07287c68a8
+ after
+ 0000000000000000.0000000000000000.b9c748899a854f00.6e13a71a47cdf9b6
+ fd541540779e4810.a6dce65e8c1c873c.ec897b81ef561b24.a205faf85a15f9c2
+ c595696fdcfbbfb0.a91cc15ee802d8ff.8705159045b482dc.3a20533c3585f9aa
+ ad1c2fb2d08084e2.a43efe861edc5819.d35fe23c9e34d810.1e788ff21aa48a92
+ 28d72c07287c68a8
+VPAVGW_128(mem)
+ before
+ 360aa665781b4e16.12336174f1b9d352.750e1ac24ab6c2b5.2ee4def095615a6b
+ 22de77fa288df908.4e27fd21db30e7ab.f75790fe879dd300.f3e1061ac7c8449a
+ ca1c1db154dd25ab.be44fe252973fd9a.05e7dc26f19c4725.7d9f5525d0f4d249
+ 0893137617178e2b.bed560ec780e51ca.7d887a27a5c0da51.2a6dc77e4b714023
+ 5596588fd4ccc9d5
+ after
+ 360aa665781b4e16.12336174f1b9d352.750e1ac24ab6c2b5.2ee4def095615a6b
+ 22de77fa288df908.4e27fd21db30e7ab.f75790fe879dd300.f3e1061ac7c8449a
+ 0000000000000000.0000000000000000.b63355e0692acadb.91637285ae954f83
+ 0893137617178e2b.bed560ec780e51ca.7d887a27a5c0da51.2a6dc77e4b714023
+ 5596588fd4ccc9d5
+
+VPAVGW_128(reg)
+ before
+ 596505c5088faa0a.ba0ed5348d47efb3.aa2820e3638c1ee8.3907e6ebbe1348af
+ 9427c98d82491e6f.ba58dfdad37a0570.de8738748679a2a0.16309d5f59a44c6c
+ 6029a051df8362af.e63fae5105bb8c8d.b63fa60d7e61179d.f1cf1a70917ca3b4
+ 1bb5867fbacbb277.188dbc863e173f38.8e9c6518e7d1b98c.a4b0d90983a908b2
+ 0c9e57164a363993
+ after
+ 0000000000000000.0000000000000000.ca636f41826d5d1f.84005be875907810
+ 9427c98d82491e6f.ba58dfdad37a0570.de8738748679a2a0.16309d5f59a44c6c
+ 6029a051df8362af.e63fae5105bb8c8d.b63fa60d7e61179d.f1cf1a70917ca3b4
+ 1bb5867fbacbb277.188dbc863e173f38.8e9c6518e7d1b98c.a4b0d90983a908b2
+ 0c9e57164a363993
+VPAVGW_128(mem)
+ before
+ 06670e82022ff082.1f177781afad4a73.2d0f87659a98db9a.c2ea71035b54c618
+ 6cd57c3bc9a1e9ad.c99d70c55bb3664e.01908bdb364d1ce1.ae75c739797678ee
+ 1bb51c2cb898e23d.76916cb65a6b41b5.71de42d22d3fbe39.ae896225dbc40bba
+ efd36a42ed1e9560.804167c047601854.57c42a389c7c7cce.1d713e351dc9bd27
+ 597a57d4dc12c8e1
+ after
+ 06670e82022ff082.1f177781afad4a73.2d0f87659a98db9a.c2ea71035b54c618
+ 6cd57c3bc9a1e9ad.c99d70c55bb3664e.01908bdb364d1ce1.ae75c739797678ee
+ 0000000000000000.0000000000000000.175089a068737c3e.b8b09c1e6a659f83
+ efd36a42ed1e9560.804167c047601854.57c42a389c7c7cce.1d713e351dc9bd27
+ 597a57d4dc12c8e1
+
+VPAVGW_128(reg)
+ before
+ bdf0a96eb32a6996.c5fbe3678441bf42.44f75d4fbf1f26d6.900dbdf79e0f13cb
+ a51f31703f9ddcf0.77f80188980c1b0f.1f004bcf5d33a9e7.f8867afd50053f5c
+ 6c53ea441bf75c9b.e2984292458c67f2.6ba82badbd29db35.6bfbda35cd69bcaf
+ 70d8d057e4c52644.e2a5216fa8cc5d17.853bfb537c8bf869.c5385a8b324745ed
+ e20977eb9aab9745
+ after
+ 0000000000000000.0000000000000000.45543bbe8d2ec28e.b241aa998eb77e06
+ a51f31703f9ddcf0.77f80188980c1b0f.1f004bcf5d33a9e7.f8867afd50053f5c
+ 6c53ea441bf75c9b.e2984292458c67f2.6ba82badbd29db35.6bfbda35cd69bcaf
+ 70d8d057e4c52644.e2a5216fa8cc5d17.853bfb537c8bf869.c5385a8b324745ed
+ e20977eb9aab9745
+VPAVGW_128(mem)
+ before
+ 9e39ac4122a26de1.0cf9df1635937697.53ec1b0ddcd8baab.c904b62f35e73e32
+ d5967579e53885ed.9b0413ecaaeb883f.1139aa56febc39da.935159ab85c9e73a
+ 63ea4f80ff779996.7b436944e05b97e9.f8584c382a8597d0.3f6cde3508bb302d
+ 2402b4408e6d6608.0703dc8c736ee041.e4157c9e7a3f90b8.2aa24338584b55b9
+ ae3f831f14059187
+ after
+ 9e39ac4122a26de1.0cf9df1635937697.53ec1b0ddcd8baab.c904b62f35e73e32
+ d5967579e53885ed.9b0413ecaaeb883f.1139aa56febc39da.935159ab85c9e73a
+ 0000000000000000.0000000000000000.329362b2edca7a43.ae2b87ed5dd892b6
+ 2402b4408e6d6608.0703dc8c736ee041.e4157c9e7a3f90b8.2aa24338584b55b9
+ ae3f831f14059187
+
+VPADDSB_128(reg)
+ before
+ 288f9b58d5742146.f4aa22a7ab26a76f.9a90682ffeb19ff2.b13bb6740df4e0be
+ f4dd854e3a2441a0.afae149f74ac19f6.92350a991daf0fa9.3b9877a6fcb2420f
+ 6e773f6ddca12c41.31d90616040d78c9.4940bc366df46d11.5df63920658573d7
+ f1a7c42259781fd7.56f975f778558015.1cfb7c728a0df5d7.f5227acf64772f41
+ dee8b59d1496327a
+ after
+ 0000000000000000.0000000000000000.db75c6cf7fa37cba.7f8e7fc661807fe6
+ f4dd854e3a2441a0.afae149f74ac19f6.92350a991daf0fa9.3b9877a6fcb2420f
+ 6e773f6ddca12c41.31d90616040d78c9.4940bc366df46d11.5df63920658573d7
+ f1a7c42259781fd7.56f975f778558015.1cfb7c728a0df5d7.f5227acf64772f41
+ dee8b59d1496327a
+VPADDSB_128(mem)
+ before
+ f414677792ee37ae.dbba10d74d34560b.fad8dc2eec8eec06.68b345b90f85e3a6
+ 12710a4af989fb08.87fc1ff953620d8c.f843b6a77ac679c7.87b5137898e8722b
+ 16cd1c0165753ab5.51b9eef5088c7f04.2e06824e4109e385.d74ae319c2c3df12
+ dbf21887f3beafe0.953d77350741ea1f.77edb90f5b61e66c.b2c1af0a28a16606
+ 756575b5670e42b4
+ after
+ f414677792ee37ae.dbba10d74d34560b.fad8dc2eec8eec06.68b345b90f85e3a6
+ 12710a4af989fb08.87fc1ff953620d8c.f843b6a77ac679c7.87b5137898e8722b
+ 0000000000000000.0000000000000000.f21b92d5668065cd.ef805831a78055d1
+ dbf21887f3beafe0.953d77350741ea1f.77edb90f5b61e66c.b2c1af0a28a16606
+ 756575b5670e42b4
+
+VPADDSB_128(reg)
+ before
+ 7c8130881a97b0c7.3cad7acabf6e17b6.afd3b827ec0a878a.aec4d8d6e4dc3da7
+ 2463ddeedec7eced.17cabfb5e4942e62.fac9ad36547595f1.b1565c90f986a563
+ c75576534e2a32cf.471561347e39b012.d46950ceda0d4eff.5a71c027b569dacb
+ c2a4f923064dbd1b.a759de33aa6b58ef.98009f5b1b5fef61.87df81893494970c
+ 136d19a193109951
+ after
+ 0000000000000000.0000000000000000.ce32fd042e7fe3f0.0b7f1cb7aeef802e
+ 2463ddeedec7eced.17cabfb5e4942e62.fac9ad36547595f1.b1565c90f986a563
+ c75576534e2a32cf.471561347e39b012.d46950ceda0d4eff.5a71c027b569dacb
+ c2a4f923064dbd1b.a759de33aa6b58ef.98009f5b1b5fef61.87df81893494970c
+ 136d19a193109951
+VPADDSB_128(mem)
+ before
+ d9e7065aeeeb9cc7.719b61caa4bbca7d.1564b19e8435e328.a1da9549b3f6b4c3
+ b619c3a260305c9a.3088aab4c10095a1.6b00566226a30de6.4d422e043c5ed8d0
+ 87cecc6406eb94f5.5bb6d14dfba95a32.87fa4a69afc29158.f68666f855239835
+ 26d49d8cfb290105.4e70d002ee4154dc.431e08a1389d2ca8.faf03a9298d2309d
+ b3cea43ca1f7dcb5
+ after
+ d9e7065aeeeb9cc7.719b61caa4bbca7d.1564b19e8435e328.a1da9549b3f6b4c3
+ b619c3a260305c9a.3088aab4c10095a1.6b00566226a30de6.4d422e043c5ed8d0
+ 0000000000000000.0000000000000000.7f640700aad8f00e.ee1cc34def548c93
+ 26d49d8cfb290105.4e70d002ee4154dc.431e08a1389d2ca8.faf03a9298d2309d
+ b3cea43ca1f7dcb5
+
+VPADDSB_128(reg)
+ before
+ 7f6aa2630c1cd728.71f5b3065bf55ff6.6503a53d3554c04c.7c380bf4e0419a03
+ b811307477cf5ea3.42fe88be435c69f3.fcbb4b6c6c6fd92e.0f14d250c0b89794
+ bc0f48da7b9badd2.76bb9aa1ce69dc28.6fe4bffa301ddd2e.d67dd6a0f611de88
+ e5afe801b60dff60.eaf86499192874c3.1acafb521ceb06f6.ae4195cf9e552c0a
+ 742a89cbd3923d47
+ after
+ 0000000000000000.0000000000000000.6b9f0a667f7fb65c.e57fa8f0b6c98080
+ b811307477cf5ea3.42fe88be435c69f3.fcbb4b6c6c6fd92e.0f14d250c0b89794
+ bc0f48da7b9badd2.76bb9aa1ce69dc28.6fe4bffa301ddd2e.d67dd6a0f611de88
+ e5afe801b60dff60.eaf86499192874c3.1acafb521ceb06f6.ae4195cf9e552c0a
+ 742a89cbd3923d47
+VPADDSB_128(mem)
+ before
+ 0205307fb2d3cc6b.913f0a55c4b091fa.7881639440a5eded.59b8fde2cd649135
+ 359e06d8562596a1.1a09ac4240109f4c.fd21117c5ded02d5.88fcc015de14b995
+ e9c185c0db935716.dd5aca34c7ba6501.55a5ec3f8f0b70a5.03e04057ec87bbc3
+ fa392b245e29cbf5.367e5e97f4391ec5.5cda6fc8ef0cf38a.25b17914924ad36a
+ 4cbb68b96de83d37
+ after
+ 0205307fb2d3cc6b.913f0a55c4b091fa.7881639440a5eded.59b8fde2cd649135
+ 359e06d8562596a1.1a09ac4240109f4c.fd21117c5ded02d5.88fcc015de14b995
+ 0000000000000000.0000000000000000.75a274107f92efc2.e1b4bdf7ab7880ca
+ fa392b245e29cbf5.367e5e97f4391ec5.5cda6fc8ef0cf38a.25b17914924ad36a
+ 4cbb68b96de83d37
+
+VPADDSW_128(reg)
+ before
+ d34a08b018ee34d6.44d473f1fbf3ad6b.82c166d763190746.ee8a17039cfb47af
+ 15aa556630e7f6f2.a35cd911cdfebaa4.1b6fdd60b1e75c2d.e7825edcafe42741
+ 70264b48505fbc38.f39ed972f056aecb.5ed3bf9f792e5929.248dc23f46d4506b
+ 3f0be7c015e3c553.1066f0fe8105450d.a73b08fe587b39e4.7f79be187dd67d5a
+ d510ce536ff66c3a
+ after
+ 0000000000000000.0000000000000000.7a429cff2b157fff.0c0f211bf6b877ac
+ 15aa556630e7f6f2.a35cd911cdfebaa4.1b6fdd60b1e75c2d.e7825edcafe42741
+ 70264b48505fbc38.f39ed972f056aecb.5ed3bf9f792e5929.248dc23f46d4506b
+ 3f0be7c015e3c553.1066f0fe8105450d.a73b08fe587b39e4.7f79be187dd67d5a
+ d510ce536ff66c3a
+VPADDSW_128(mem)
+ before
+ 011f6edc3940d736.dda6233c1afd4bf0.d68098a39b193a95.52f1b5ebe958390a
+ e1731ba0f6c17b7a.a841fd27fb3c8bba.21b84f4c5b9d4a90.bb42c1d1c9539449
+ 50d65089c2851334.fa2870ed5529c15e.cdd991e5dc9e302a.3e7a281c94f8884a
+ 2a148985ba965c8e.31a979fac4522888.b6b1d85a3b27aa8e.37e5e638e4d24fbc
+ 02cef891576d2549
+ after
+ 011f6edc3940d736.dda6233c1afd4bf0.d68098a39b193a95.52f1b5ebe958390a
+ e1731ba0f6c17b7a.a841fd27fb3c8bba.21b84f4c5b9d4a90.bb42c1d1c9539449
+ 0000000000000000.0000000000000000.f838e7eff6b67fff.0e338000b2abcd53
+ 2a148985ba965c8e.31a979fac4522888.b6b1d85a3b27aa8e.37e5e638e4d24fbc
+ 02cef891576d2549
+
+VPADDSW_128(reg)
+ before
+ fb8358938955489d.4bfb427ffa0212b4.a70f12bae342fee3.b80aa297934472e9
+ 7e4e04aa1517f266.8f55f8639cd5f1d3.baa539994e867c1c.afb16a8901024566
+ e77cf742983e604d.d2f0251cbf19b417.c4b8e903a2a9e1df.7772ac1aa06cde32
+ 92592ec8ad57ce01.ef9647987ddc18ac.23941e657a3767d7.eb19e4378d8efb79
+ e9718fcde3755566
+ after
+ 0000000000000000.0000000000000000.8000229cf12f5dfb.272316a3a16e2398
+ 7e4e04aa1517f266.8f55f8639cd5f1d3.baa539994e867c1c.afb16a8901024566
+ e77cf742983e604d.d2f0251cbf19b417.c4b8e903a2a9e1df.7772ac1aa06cde32
+ 92592ec8ad57ce01.ef9647987ddc18ac.23941e657a3767d7.eb19e4378d8efb79
+ e9718fcde3755566
+VPADDSW_128(mem)
+ before
+ 4c4827c7be2cab25.db31a3a6f0ec772c.c414d9c3f22ad9bc.3185d52973bd4bb0
+ ef682a103bbfb8e4.1e50544aff8c987a.2c3658873b0db376.4bd709bd28c6c918
+ b09e1396763b37cd.b6013c1e73c06d98.02c73ed173936104.cdd6b58b36de1db9
+ 6ab65f448aabe50c.01925790ea163232.2495098db7c8a093.14cdd8013892823f
+ 7a096b8acb6d3557
+ after
+ 4c4827c7be2cab25.db31a3a6f0ec772c.c414d9c3f22ad9bc.3185d52973bd4bb0
+ ef682a103bbfb8e4.1e50544aff8c987a.2c3658873b0db376.4bd709bd28c6c918
+ 0000000000000000.0000000000000000.f04a324a2d378d32.7d5cdee67fff14c8
+ 6ab65f448aabe50c.01925790ea163232.2495098db7c8a093.14cdd8013892823f
+ 7a096b8acb6d3557
+
+VPADDSW_128(reg)
+ before
+ 5cd66b928afb71ad.f87c8906931c7dce.5a4da20bff1922f3.6d6a34a822b72c4e
+ 1680d58512c974ec.38bb0cc8ae98bc3f.1c7f17fb4f567a88.b8143b0cd16cc062
+ 0453a4cffe6278c1.04416676f62d5e8a.a574b4cc7658769d.e35d9ba7dff319fb
+ 829bd4dceb53b9d7.3ad813fd88e71fdc.507874ea0eab51dd.c811cf646859f344
+ 45fe522f89a90a69
+ after
+ 0000000000000000.0000000000000000.c1f3ccc77fff7fff.9b71d6b3b15fda5d
+ 1680d58512c974ec.38bb0cc8ae98bc3f.1c7f17fb4f567a88.b8143b0cd16cc062
+ 0453a4cffe6278c1.04416676f62d5e8a.a574b4cc7658769d.e35d9ba7dff319fb
+ 829bd4dceb53b9d7.3ad813fd88e71fdc.507874ea0eab51dd.c811cf646859f344
+ 45fe522f89a90a69
+VPADDSW_128(mem)
+ before
+ 34efa3f45eef1998.eda36218742675db.b44d8d477fd1bb61.78d654c2b6db48f5
+ 72af3b9f0238ddfa.9fb948f03569e679.506c5242f8f7ed44.7bdc4ebe07759790
+ dc0c971c918f12be.f52784cecba8495c.e801ddd80e6572b1.b3d4604ba0047a5b
+ 4cd034572801730e.4b3a1120d16eda31.59d8aaf7de2805d6.7e0b85d61a152c01
+ 36cdb9c91433ea2f
+ after
+ 34efa3f45eef1998.eda36218742675db.b44d8d477fd1bb61.78d654c2b6db48f5
+ 72af3b9f0238ddfa.9fb948f03569e679.506c5242f8f7ed44.7bdc4ebe07759790
+ 0000000000000000.0000000000000000.04b9df8978c8a8a5.7fff7fffbe50e085
+ 4cd034572801730e.4b3a1120d16eda31.59d8aaf7de2805d6.7e0b85d61a152c01
+ 36cdb9c91433ea2f
+
+VPHADDW_128(reg)
+ before
+ 3966f99227eaf091.9fc88d3ce399bd17.fc3eec50e447d4a3.80bc358a834b63dc
+ e1223f9cf1c779d2.b2bf1eb8dc63ac04.667f0fcca0bf745f.377bfb7d1adb49f2
+ 8b4c89530e55c29f.5f8364b5326bfc02.e44878ffa063f610.5bdf77bcbee37042
+ 9431d223192007a4.83dfd921ffbe683c.d2e7225580be9564.c8b525338b6f97f9
+ 5ac981ce9f8b7842
+ after
+ 0000000000000000.0000000000000000.5d479673d39b2f25.764b151e32f864cd
+ e1223f9cf1c779d2.b2bf1eb8dc63ac04.667f0fcca0bf745f.377bfb7d1adb49f2
+ 8b4c89530e55c29f.5f8364b5326bfc02.e44878ffa063f610.5bdf77bcbee37042
+ 9431d223192007a4.83dfd921ffbe683c.d2e7225580be9564.c8b525338b6f97f9
+ 5ac981ce9f8b7842
+VPHADDW_128(mem)
+ before
+ eee707791344d04a.561e1678aeb5848c.fa9efbe75f68addf.8ca6093add5d8f04
+ 5eda342005a55a3c.2e5d52be6a9f7403.a08d45f26f738717.6ed2291a52cb1e9f
+ 877083b090bbd445.783a8161e96a14b6.517834304aedb20f.d3b77f617c947edf
+ 45737013d191f891.91039fcec6a3a051.ea2b428c0ce1e9f4.19a1067cf644ed70
+ 9bdbbad55c68a5ff
+ after
+ eee707791344d04a.561e1678aeb5848c.fa9efbe75f68addf.8ca6093add5d8f04
+ 5eda342005a55a3c.2e5d52be6a9f7403.a08d45f26f738717.6ed2291a52cb1e9f
+ 0000000000000000.0000000000000000.f6850d4795e06c61.e67ff68a97ec716a
+ 45737013d191f891.91039fcec6a3a051.ea2b428c0ce1e9f4.19a1067cf644ed70
+ 9bdbbad55c68a5ff
+
+VPHADDW_128(reg)
+ before
+ b4b397da4c8be338.74b07837e433834b.d303a86f9dd55380.4572edf2d35ce9f1
+ c2739af55f3ae2c6.f0f31507e4ae30a0.9b8598b20b8c6aee.3f18b04eb8696d33
+ 2068bd943300df56.9508c56eed0dbcbb.45d66c01ab552147.b4eb078dd91433e6
+ 29defe2264691694.3fbb035a1c5ce3c9.2d421eca1abbb439.80b56e99526af535
+ 7e43625f3e76704d
+ after
+ 0000000000000000.0000000000000000.b1d7cc9cbc780cfa.3437767aef66259c
+ c2739af55f3ae2c6.f0f31507e4ae30a0.9b8598b20b8c6aee.3f18b04eb8696d33
+ 2068bd943300df56.9508c56eed0dbcbb.45d66c01ab552147.b4eb078dd91433e6
+ 29defe2264691694.3fbb035a1c5ce3c9.2d421eca1abbb439.80b56e99526af535
+ 7e43625f3e76704d
+VPHADDW_128(mem)
+ before
+ 8c615eccb9445f59.3b21590b8d02c32b.cad74bb68ca861f6.af15ad78f34b5e6d
+ 85dbdecbe0e07f86.b07dc8bb4a5622c8.122a1a6e5afcf16d.279b1277d38f5c92
+ 457c5e47cf578c00.e63d489e38f16e16.f37eea6ea164505a.f1204a335516ea52
+ a8125b2ea1b542f2.37afd620f35fe4c2.48a039a37eed3aeb.69ef521816694459
+ eb562592b116a554
+ after
+ 8c615eccb9445f59.3b21590b8d02c32b.cad74bb68ca861f6.af15ad78f34b5e6d
+ 85dbdecbe0e07f86.b07dc8bb4a5622c8.122a1a6e5afcf16d.279b1277d38f5c92
+ 0000000000000000.0000000000000000.168dee9e5c8d51b8.2c984c693a123021
+ a8125b2ea1b542f2.37afd620f35fe4c2.48a039a37eed3aeb.69ef521816694459
+ eb562592b116a554
+
+VPHADDW_128(reg)
+ before
+ d39fbf0ec3a84aef.8a674f6b72045c88.001d6dad152dbf77.ef5c82f70ca26b4a
+ 7d171cf6e7ab6fd6.c648b8ea5f5397f0.9ed40ab13de73de2.c37e4158678f9ea3
+ 450a39b8b9ac4fb4.3a81119783abaf54.6b20a799051798af.a0d1f3b0acc19023
+ 86c311bed6362735.c1ded75efb1a60e0.c54d42cf094b0c89.612313edf743fdf6
+ e43e1df96321a047
+ after
+ 0000000000000000.0000000000000000.12b99dc694813ce4.a9857bc904d60632
+ 7d171cf6e7ab6fd6.c648b8ea5f5397f0.9ed40ab13de73de2.c37e4158678f9ea3
+ 450a39b8b9ac4fb4.3a81119783abaf54.6b20a799051798af.a0d1f3b0acc19023
+ 86c311bed6362735.c1ded75efb1a60e0.c54d42cf094b0c89.612313edf743fdf6
+ e43e1df96321a047
+VPHADDW_128(mem)
+ before
+ 04ef8dc20c683643.9e90a076dad63306.362b842ce2ab65c1.06a6d6c1e60fd71d
+ 9c02df330f237b16.e8bbe24b6017aed3.773396eb556a7b23.8b795fda37ed3316
+ 8a439038885e2beb.c091d3a80485d647.5fc488886f645e31.b010d98699735d21
+ a87d1bbd922601ef.815e70fb63ade50f.c9a8d6f04da4c918.d1b84131a72d90ea
+ 4bbd9147fda60a1c
+ after
+ 04ef8dc20c683643.9e90a076dad63306.362b842ce2ab65c1.06a6d6c1e60fd71d
+ 9c02df330f237b16.e8bbe24b6017aed3.773396eb556a7b23.8b795fda37ed3316
+ 0000000000000000.0000000000000000.ba57486cdd67bd2c.0e1ed08deb536b03
+ a87d1bbd922601ef.815e70fb63ade50f.c9a8d6f04da4c918.d1b84131a72d90ea
+ 4bbd9147fda60a1c
+
+VPHADDD_128(reg)
+ before
+ 786bc734386a0564.d47efcaf4986ba4d.896eb4af191917d7.93acfd0e0a367904
+ b50ede64f405be6d.e810aff8ca8b1232.320d9b31c058aa4a.979c77cdc2272a20
+ 5ef1d343cc0470e4.c200b185303fc4c9.da8721ebf7f3d815.b344c21b92829899
+ cf62a13e5cf25875.3c1a7c4398b08d3f.dc27434a5778dee3.c16f59e396547e9a
+ 9eebb911e9a79950
+ after
+ 0000000000000000.0000000000000000.d27afa0045c75ab4.f266457b59c3a1ed
+ b50ede64f405be6d.e810aff8ca8b1232.320d9b31c058aa4a.979c77cdc2272a20
+ 5ef1d343cc0470e4.c200b185303fc4c9.da8721ebf7f3d815.b344c21b92829899
+ cf62a13e5cf25875.3c1a7c4398b08d3f.dc27434a5778dee3.c16f59e396547e9a
+ 9eebb911e9a79950
+VPHADDD_128(mem)
+ before
+ 27825c91a78aa5e6.64ab43bf415bb2cb.332a8e1c1dea29c0.933afcbb7f72f761
+ 3601c050ed065d89.7919b83417ccba93.84fc62fedcf85477.5d0c48a8086e613a
+ a8346038d7297e65.6af8f90779d0ab78.095b75d4f0e6c991.94e9237f91f7561b
+ 5ae7b83680fec4a5.939303a603f4c227.9f15418a75c0453a.951d89abb39912b0
+ bdf477970ce1d3a4
+ after
+ 27825c91a78aa5e6.64ab43bf415bb2cb.332a8e1c1dea29c0.933afcbb7f72f761
+ 3601c050ed065d89.7919b83417ccba93.84fc62fedcf85477.5d0c48a8086e613a
+ 0000000000000000.0000000000000000.5114b7dc12adf41c.61f4b775657aa9e2
+ 5ae7b83680fec4a5.939303a603f4c227.9f15418a75c0453a.951d89abb39912b0
+ bdf477970ce1d3a4
+
+VPHADDD_128(reg)
+ before
+ 66b9e8b1385ad3a4.26e645370492eb76.5038d37c52c23b4c.23f4440c8993849d
+ eebad864d2904f5c.e9fc812580efae03.fc3164f501c95292.6fc5f946456a41e6
+ af41431c76108277.7ff6eaee0f24ca79.f5ccb27dad9242a6.6054dc24c7523942
+ 069b2545c165aaa1.c4a1fb7dce3afb04.9653ba80f1ab4833.d26d6a922b5628dd
+ a1db1e7c8c82cae3
+ after
+ 0000000000000000.0000000000000000.a35ef52327a71566.fdfab787b5303b2c
+ eebad864d2904f5c.e9fc812580efae03.fc3164f501c95292.6fc5f946456a41e6
+ af41431c76108277.7ff6eaee0f24ca79.f5ccb27dad9242a6.6054dc24c7523942
+ 069b2545c165aaa1.c4a1fb7dce3afb04.9653ba80f1ab4833.d26d6a922b5628dd
+ a1db1e7c8c82cae3
+VPHADDD_128(mem)
+ before
+ a96c73cf06e3da7f.4f147b4c4f1b0187.95c730bed83ffdcf.3b13766a6a9fa0e6
+ c6eae875b68415dd.e6f7409bbbbfc4d5.cc35069d4a3e8b07.3f57e4a8b3fb856b
+ d522f65cb771372b.289270a0a1dc2e37.46b6f8063f4462d7.006dffa4694a346d
+ b0e01a6f26b6fc92.6f2f08c59efe7c58.df1882e5d35c3d6c.d9a0c3cb2718e999
+ 253b2d8a8af1df9a
+ after
+ a96c73cf06e3da7f.4f147b4c4f1b0187.95c730bed83ffdcf.3b13766a6a9fa0e6
+ c6eae875b68415dd.e6f7409bbbbfc4d5.cc35069d4a3e8b07.3f57e4a8b3fb856b
+ 0000000000000000.0000000000000000.6e072e8da5b31750.167391a4f3536a13
+ b0e01a6f26b6fc92.6f2f08c59efe7c58.df1882e5d35c3d6c.d9a0c3cb2718e999
+ 253b2d8a8af1df9a
+
+VPHADDD_128(reg)
+ before
+ 428b384c2d62541d.33f0d1991f601f41.181c02784db2eae4.732520262392daf2
+ 8adcdf7dacf682cd.3c1e96c8bc7b5d62.7fa35c244b83b489.deab4eb64bf3f394
+ 5b7a2188a43aa557.a635e5e71c117121.0011113433fe15f0.fc74897f668a457f
+ 0fb1f7dbb1b9fb67.4d033be2583019ab.f7b11d16a2ad4ac8.a84d4c6f91638bde
+ c0011370e78b82de
+ after
+ 0000000000000000.0000000000000000.340f272462fecefe.cb2710ad2a9f424a
+ 8adcdf7dacf682cd.3c1e96c8bc7b5d62.7fa35c244b83b489.deab4eb64bf3f394
+ 5b7a2188a43aa557.a635e5e71c117121.0011113433fe15f0.fc74897f668a457f
+ 0fb1f7dbb1b9fb67.4d033be2583019ab.f7b11d16a2ad4ac8.a84d4c6f91638bde
+ c0011370e78b82de
+VPHADDD_128(mem)
+ before
+ 1f5e5a70840de6ab.04cc5fe26effbea8.0d5213a68fe40f2c.c0d17d35331e8fbb
+ a12e9d5a85f57370.9419530777992bc7.c2efe81dda3710d0.b7bc2cfd83dd1f75
+ 223f591a0550e45a.1de2d1b769127d70.48a638345737d7c1.38bd25db2d7538a3
+ 7d5b099c2129f694.f974d55edff6f24e.7a437fd822f0222e.9f216739ce7214f1
+ 4834eb840160ef0b
+ after
+ 1f5e5a70840de6ab.04cc5fe26effbea8.0d5213a68fe40f2c.c0d17d35331e8fbb
+ a12e9d5a85f57370.9419530777992bc7.c2efe81dda3710d0.b7bc2cfd83dd1f75
+ 0000000000000000.0000000000000000.9d3622d2f3f00cf0.9d26f8ed3b994c72
+ 7d5b099c2129f694.f974d55edff6f24e.7a437fd822f0222e.9f216739ce7214f1
+ 4834eb840160ef0b
+
+VPHADDSW_128(reg)
+ before
+ 8e42af2962cc079c.904f29ccf48c654b.851b596976d2c40d.369137f3566caa41
+ cf96ad928e419650.36e736969b86edaa.1e235b42c931305b.575ede7310b92e27
+ 667ee32d214cd9d4.4aeeaae6312249df.1ed7d657759f71e1.b874ef436be3690b
+ af444d65b6780bd4.aa3203a9d36c3613.e285c61315a9c44e.37a0e64e83f4161a
+ afae408275fbf280
+ after
+ 0000000000000000.0000000000000000.f52e7fffa7b77fff.7965f98c35d13ee0
+ cf96ad928e419650.36e736969b86edaa.1e235b42c931305b.575ede7310b92e27
+ 667ee32d214cd9d4.4aeeaae6312249df.1ed7d657759f71e1.b874ef436be3690b
+ af444d65b6780bd4.aa3203a9d36c3613.e285c61315a9c44e.37a0e64e83f4161a
+ afae408275fbf280
+VPHADDSW_128(mem)
+ before
+ fb6a77ca5c01b868.0536e5a6e95169fb.317dbcc99c717075.c77727e146da654c
+ f99f0912551425fe.c69ea95c57632ff6.ba9d5134a93cb22e.27faf62fa3be9088
+ 831b71477c3ff570.4dc994f39b3b9971.235c3fd415d9b96d.5f5a2d68c9e280ad
+ 77a82b53eb8ee4e8.f502a2d75265e317.46870097fd55415c.cbe3caf953d17268
+ c7e0c94cdd17a264
+ after
+ fb6a77ca5c01b868.0536e5a6e95169fb.317dbcc99c717075.c77727e146da654c
+ f99f0912551425fe.c69ea95c57632ff6.ba9d5134a93cb22e.27faf62fa3be9088
+ 0000000000000000.0000000000000000.ee460ce6ef587fff.0bd180001e298000
+ 77a82b53eb8ee4e8.f502a2d75265e317.46870097fd55415c.cbe3caf953d17268
+ c7e0c94cdd17a264
+
+VPHADDSW_128(reg)
+ before
+ af9f24ce04414b4e.af13b423c10eae92.1c97cf74186b4895.01e912687cbb0628
+ df6ad9eb64daabd2.092887a417ca0e9b.1cd2173787db0496.2e50f033ae18c3fc
+ b38fe310986ffb9b.5fb320c00ccfc12f.5301778a3e4055c7.aa8617e4b0773505
+ 87583ea73c8a7a56.8e80fb65b9278279.1b6eeadbd62775d3.525901679ee4186e
+ 00932ca8936b2764
+ after
+ 0000000000000000.0000000000000000.7fff7fffc26ae57c.34098c711e838000
+ df6ad9eb64daabd2.092887a417ca0e9b.1cd2173787db0496.2e50f033ae18c3fc
+ b38fe310986ffb9b.5fb320c00ccfc12f.5301778a3e4055c7.aa8617e4b0773505
+ 87583ea73c8a7a56.8e80fb65b9278279.1b6eeadbd62775d3.525901679ee4186e
+ 00932ca8936b2764
+VPHADDSW_128(mem)
+ before
+ 91011394ab191f13.b711e61eedba63ae.735a947e3de10ea6.d2666c94ed1ba167
+ e26f321503f9bca6.9f08d7e04788f150.e80f68f7b10622e1.d234fa231fa8152f
+ cda80518b618ba4a.9b880e59e48260e7.ca69f1bc33a47757.79268ef3075b0dd6
+ 2f7a098ae181d42b.07dc86f56333ee21.f535aeb9dfc6cc34.2187267042bfc409
+ 27a2bd066b607773
+ after
+ 91011394ab191f13.b711e61eedba63ae.735a947e3de10ea6.d2666c94ed1ba167
+ e26f321503f9bca6.9f08d7e04788f150.e80f68f7b10622e1.d234fa231fa8152f
+ 0000000000000000.0000000000000000.07d84c873efa8e82.5106d3e7cc5734d7
+ 2f7a098ae181d42b.07dc86f56333ee21.f535aeb9dfc6cc34.2187267042bfc409
+ 27a2bd066b607773
+
+VPHADDSW_128(reg)
+ before
+ e8c450211ecb61c2.e4afb9569f40c774.3e513b205e28d5a7.463f18dad079dba3
+ be39d92df88bbf9f.c81491680d614f51.9e342a4671eb5228.9753ac0b22c861d1
+ 064d5696952cceb8.b8750dab46f128ef.82ce4dd3380ba14e.c53ce738f2bf19e9
+ 1c4cc2c8903bc7b9.8e9eaa0d67fb0d7a.466ea2335111fdc5.acc8444e5c6ac118
+ 28c13f377bd6138a
+ after
+ 0000000000000000.0000000000000000.d0a1d959ac740ca8.c87a7fff80007fff
+ be39d92df88bbf9f.c81491680d614f51.9e342a4671eb5228.9753ac0b22c861d1
+ 064d5696952cceb8.b8750dab46f128ef.82ce4dd3380ba14e.c53ce738f2bf19e9
+ 1c4cc2c8903bc7b9.8e9eaa0d67fb0d7a.466ea2335111fdc5.acc8444e5c6ac118
+ 28c13f377bd6138a
+VPHADDSW_128(mem)
+ before
+ 15f454e16b0ecc6a.5c8119308543e94e.275be3798b8cbb1e.455f24d3558ba33a
+ 4f2d0037491fa7e5.233a573811d06e22.5f7734dccfafed06.ddeccf1de204cf59
+ b238be2430146126.cbc1794ecf6f93e1.12c019204e70615e.6963a07f9409bdcd
+ 1ae10a963df9b65a.b1637add5cab9438.1c000e3224dcd153.440e92640625a843
+ cc3aa137d5e4cd67
+ after
+ 15f454e16b0ecc6a.5c8119308543e94e.275be3798b8cbb1e.455f24d3558ba33a
+ 4f2d0037491fa7e5.233a573811d06e22.5f7734dccfafed06.ddeccf1de204cf59
+ 0000000000000000.0000000000000000.0ad480006a32f8c5.7fffbcb5ad09b15d
+ 1ae10a963df9b65a.b1637add5cab9438.1c000e3224dcd153.440e92640625a843
+ cc3aa137d5e4cd67
+
+VPMADDUBSW_128(reg)
+ before
+ 5b33c9669cd268e4.63f360788bdb62ad.316c56515310acd3.590490ff6efefa11
+ 4f44065cf77cb466.693c3cb637c5204a.a7280916512b185e.a498197148e297c3
+ 02bb5585836eee9b.08861b3d5cc3ad5e.6fe28f98f1871484.db882876cd956596
+ d2e2b04edb32522d.1b9e78f717e2c514.e5e8e543d0b1dbf1.d99f36f9192220b6
+ 7aabc0e54995844e
+ after
+ 0000000000000000.0000000000000000.43b9f317e6eed458.a10c37fe9332ead5
+ 4f44065cf77cb466.693c3cb637c5204a.a7280916512b185e.a498197148e297c3
+ 02bb5585836eee9b.08861b3d5cc3ad5e.6fe28f98f1871484.db882876cd956596
+ d2e2b04edb32522d.1b9e78f717e2c514.e5e8e543d0b1dbf1.d99f36f9192220b6
+ 7aabc0e54995844e
+VPMADDUBSW_128(mem)
+ before
+ 9a76432878fb4c8b.190716219c561cc8.8050cfd1832d2499.658406838934aa52
+ 14cd3aadc35f3598.3474806b62668719.12689cb8bdb08519.4b03eec4b99cbd53
+ c67c216046cdfba2.8076eb99c7ecd0cc.adb15c96e078a5bf.f2b19a73fb7550a0
+ 8b4f742e1b525ad5.575854156a76338c.2cf98959089040b8.b8da04faeb4c9ee3
+ f8ca2ac726ace5cb
+ after
+ 9a76432878fb4c8b.190716219c561cc8.8050cfd1832d2499.658406838934aa52
+ 14cd3aadc35f3598.3474806b62668719.12689cb8bdb08519.4b03eec4b99cbd53
+ 0000000000000000.0000000000000000.1780c05cc2a708a5.1c23a5e0c9b1db18
+ 8b4f742e1b525ad5.575854156a76338c.2cf98959089040b8.b8da04faeb4c9ee3
+ f8ca2ac726ace5cb
+
+VPMADDUBSW_128(reg)
+ before
+ 0ecc074448225e02.3e12b00161f90d5c.1668b64de490eb06.6d0aa1ec5204112f
+ 552e97dfec394835.bd9050c631ced163.1af00dabd4c435e5.4bb1203adae1d551
+ 2b3ad703ae7ddd0f.e397d06aa9de6218.bd3e559dd3a04dd6.a1ba8031bb324849
+ eb3dc11c2b7a5a3d.8bf1acd7e5347ba5.5c9c8b8e80b06f85.4df13fbc11042644
+ 2921d7c8f9612a6e
+ after
+ 0000000000000000.0000000000000000.3352c230913cea5f.b3c5fb1af1305301
+ 552e97dfec394835.bd9050c631ced163.1af00dabd4c435e5.4bb1203adae1d551
+ 2b3ad703ae7ddd0f.e397d06aa9de6218.bd3e559dd3a04dd6.a1ba8031bb324849
+ eb3dc11c2b7a5a3d.8bf1acd7e5347ba5.5c9c8b8e80b06f85.4df13fbc11042644
+ 2921d7c8f9612a6e
+VPMADDUBSW_128(mem)
+ before
+ 1318c73f8e5711f2.f0835396febdfb6b.936b60fb00ddd936.5357aaea747ed69d
+ e5a0880eedf297fd.985888ddc4d1fb44.d5d169c117e338f8.febbae1d4d98bfcb
+ 7d869721313d77bb.3e075d5e19439774.2fef421445545417.b9139394a78a66ba
+ b596716577446e57.3ddecc83979e0ba9.7b9067e2a63ce8be.e0ad55b91ddf0717
+ cfd3f1f94b23dd8e
+ after
+ 1318c73f8e5711f2.f0835396febdfb6b.936b60fb00ddd936.5357aaea747ed69d
+ e5a0880eedf297fd.985888ddc4d1fb44.d5d169c117e338f8.febbae1d4d98bfcb
+ 0000000000000000.0000000000000000.fcaa239be0f72bc8.7fffc30e6db49229
+ b596716577446e57.3ddecc83979e0ba9.7b9067e2a63ce8be.e0ad55b91ddf0717
+ cfd3f1f94b23dd8e
+
+VPMADDUBSW_128(reg)
+ before
+ e2d262c1cee225ca.6b9c91c5da1338fd.f327d3b9dd6e938d.9682541657a6b11a
+ 75f6a47b42a91a78.7964732c77b791db.ba2f6d6d84406acc.5d8f869d749e6b57
+ e48bb3954203fa43.bcba9388693b341b.f04296092a9fcd13.aa8478611830d1a0
+ 8bdd8c7a6a7cffd8.10696ec4cdacdee9.efac4afb6b17f80e.5a2da64f5f69a021
+ 4a568c5466549407
+ after
+ 0000000000000000.0000000000000000.007ed6b3fd68fa06.9b7e7a4d2880cbbb
+ 75f6a47b42a91a78.7964732c77b791db.ba2f6d6d84406acc.5d8f869d749e6b57
+ e48bb3954203fa43.bcba9388693b341b.f04296092a9fcd13.aa8478611830d1a0
+ 8bdd8c7a6a7cffd8.10696ec4cdacdee9.efac4afb6b17f80e.5a2da64f5f69a021
+ 4a568c5466549407
+VPMADDUBSW_128(mem)
+ before
+ 54cba65a48fe697e.c638299657a166e3.523e7fccbe154b72.14b886aee2352668
+ 5557714f2272dab2.f1e78854a4fd6a0f.5c05428c598236e2.bcb4458e2c8494ce
+ 29c8681d0fbca4ce.6837a423ee1d4809.0b8a33f0b9ff5c64.41ea8307e4907eeb
+ ade807b22ce983fe.87747a6cd08c3c7c.3b99cfe4fa997925.00a73c85a6e6206d
+ 56376d740f11b5fd
+ after
+ 54cba65a48fe697e.c638299657a166e3.523e7fccbe154b72.14b886aee2352668
+ 5557714f2272dab2.f1e78854a4fd6a0f.5c05428c598236e2.bcb4458e2c8494ce
+ 0000000000000000.0000000000000000.1eae044ef3b87476.dc10b1a2162c69a8
+ ade807b22ce983fe.87747a6cd08c3c7c.3b99cfe4fa997925.00a73c85a6e6206d
+ 56376d740f11b5fd
+
+VPHSUBW_128(reg)
+ before
+ 9de61040bb9d7a49.bb84caf994033370.a9ea049ce7d68215.c8fe9055395b4950
+ 320023564517abfd.30682ede64196f4d.2ce5401fce875580.8f84f42d91528712
+ 71d1a220490a84c5.e85fad4db734f4c4.6bb12962222cf368.6af876591f89f097
+ b6a4870c6402404c.bf37c532aa627dff.c199bccf7e519579.362693c6ff0c400a
+ cfdac55f4ce83398
+ after
+ 0000000000000000.0000000000000000.bdb1d13c0b61d10e.133a86f964a9f5c0
+ 320023564517abfd.30682ede64196f4d.2ce5401fce875580.8f84f42d91528712
+ 71d1a220490a84c5.e85fad4db734f4c4.6bb12962222cf368.6af876591f89f097
+ b6a4870c6402404c.bf37c532aa627dff.c199bccf7e519579.362693c6ff0c400a
+ cfdac55f4ce83398
+VPHSUBW_128(mem)
+ before
+ 11e08a102228846c.5dc6d084318c1c3e.91baf27958aec82a.8ceaf3d47e807a61
+ d8045dc49ed8f0b3.c38377f64d335348.3ab6ae0fdd258f73.27f1ccdbc047dcca
+ ff11ba69db053299.42277acd53832316.96f577de56d28f03.edf84252dd31f860
+ 64d51eebf6ba0849.37fed575e009c654.8144c7d4dfc18309.3c4b51a473cb0ad0
+ 6e38f53d1ea04dc6
+ after
+ 11e08a102228846c.5dc6d084318c1c3e.91baf27958aec82a.8ceaf3d47e807a61
+ d8045dc49ed8f0b3.c38377f64d335348.3ab6ae0fdd258f73.27f1ccdbc047dcca
+ 0000000000000000.0000000000000000.60bf6f7c66eafbe1.7359b24ea4ea1c83
+ 64d51eebf6ba0849.37fed575e009c654.8144c7d4dfc18309.3c4b51a473cb0ad0
+ 6e38f53d1ea04dc6
+
+VPHSUBW_128(reg)
+ before
+ e10a2b89783cffed.e21a03340a032cf0.fe54825a8f5078ad.d66e1cdb93ff28af
+ ef0ceef4202c59f2.55ade73134ed5bb9.f3747fe8fde577cd.7341f2e18e973a21
+ f58b3aebb0fb9a81.995a45ce8f8350d1.71abc78bc552fd61.3387c3d1ed95758c
+ 50d30bd8c435fc45.8aed9af837d1c863.d64656b084264715.f20e0d97cc06941c
+ 8ca04b1f45f554fc
+ after
+ 0000000000000000.0000000000000000.55e0380f904a87f7.8c7479e87fa0ab8a
+ ef0ceef4202c59f2.55ade73134ed5bb9.f3747fe8fde577cd.7341f2e18e973a21
+ f58b3aebb0fb9a81.995a45ce8f8350d1.71abc78bc552fd61.3387c3d1ed95758c
+ 50d30bd8c435fc45.8aed9af837d1c863.d64656b084264715.f20e0d97cc06941c
+ 8ca04b1f45f554fc
+VPHSUBW_128(mem)
+ before
+ dc0af955776e7159.5a305d28f967bcea.0331609949e47f9d.7d8f28c1d5ea9194
+ c01893257b7ea75f.70ee2d48ea1c161e.e2f4159fe1c731a8.c2d23a2c542c168b
+ 1395967b7030b139.ef5976a334e0458a.020034f51a869ab3.015d875b9e7713a6
+ b04f7d446f904c14.31bc34a4724087dd.3e223987102e75e7.967b0bbc4f58c490
+ dc77c2ba025965f6
+ after
+ dc0af955776e7159.5a305d28f967bcea.0331609949e47f9d.7d8f28c1d5ea9194
+ c01893257b7ea75f.70ee2d48ea1c161e.e2f4159fe1c731a8.c2d23a2c542c168b
+ 0000000000000000.0000000000000000.5d6835b9ab32bbaa.32ab4fe1775ac25f
+ b04f7d446f904c14.31bc34a4724087dd.3e223987102e75e7.967b0bbc4f58c490
+ dc77c2ba025965f6
+
+VPHSUBW_128(reg)
+ before
+ 319ea8c053093183.7510c46a97ab341b.936463b941c716c1.7426a040e0ca7f73
+ f03cba3cdff165e4.3ca6e7db018c247b.719e004d3c012ee2.7ed8e60fa6667381
+ 749df399419f3dc5.e3db6281cb40d95f.27b406cc007b0dee.3a0386dd7d0f0e3e
+ 1b0d4f44169ef4d1.447cb24a11d10ff4.12f271a228c0ed8e.8275fc9781d00cd5
+ 34f8c429cfb62973
+ after
+ 0000000000000000.0000000000000000.df180d734cda912f.8eaff2e16737cd1b
+ f03cba3cdff165e4.3ca6e7db018c247b.719e004d3c012ee2.7ed8e60fa6667381
+ 749df399419f3dc5.e3db6281cb40d95f.27b406cc007b0dee.3a0386dd7d0f0e3e
+ 1b0d4f44169ef4d1.447cb24a11d10ff4.12f271a228c0ed8e.8275fc9781d00cd5
+ 34f8c429cfb62973
+VPHSUBW_128(mem)
+ before
+ 2a595b8082cb2143.3fd7caa7f97bc7b4.3d545221ee4e8266.8ca63d3b505c0a71
+ 42643b86b71daf73.3e49612f87c1f21c.a831bef27fc0ede0.f21b660415dca241
+ 56e5e22989b8902c.73ad0e495bfcb1b3.63dd72a9de350d8f.a09ce96713cbefaa
+ 43a8cb5315a77f9c.3950cf5f12b93f25.4826eb322ab89e9f.f276c1d2e5b52e5a
+ 44f5eaaf27279bfa
+ after
+ 2a595b8082cb2143.3fd7caa7f97bc7b4.3d545221ee4e8266.8ca63d3b505c0a71
+ 42643b86b71daf73.3e49612f87c1f21c.a831bef27fc0ede0.f21b660415dca241
+ 0000000000000000.0000000000000000.14cd9418b095ba15.16c16e2073e98c65
+ 43a8cb5315a77f9c.3950cf5f12b93f25.4826eb322ab89e9f.f276c1d2e5b52e5a
+ 44f5eaaf27279bfa
+
+VPHSUBD_128(reg)
+ before
+ f265606c76ac7139.e67973f276f639ef.ed7ea0df4783d91f.34d6a4797d565b3b
+ 581220746dd1edc1.192354f1c9b17a51.ec837b3497e6bb4d.04ba196bf319018f
+ d1472432a9214b3e.b973ec3c29e5feed.90ab5ec99d6f205a.929ec6f2a9104cc9
+ bb526a14c628c65d.a335b6bfb29d81ef.3741430cf6a945f3.bb4d27fcba44f813
+ 5b95b97343c3c099
+ after
+ 0000000000000000.0000000000000000.0cc3c191167185d7.ab634019ee5ee824
+ 581220746dd1edc1.192354f1c9b17a51.ec837b3497e6bb4d.04ba196bf319018f
+ d1472432a9214b3e.b973ec3c29e5feed.90ab5ec99d6f205a.929ec6f2a9104cc9
+ bb526a14c628c65d.a335b6bfb29d81ef.3741430cf6a945f3.bb4d27fcba44f813
+ 5b95b97343c3c099
+VPHSUBD_128(mem)
+ before
+ 4e40f74560986188.717dee855e729cca.b1352e6681e6be85.3b9229683d2066c3
+ 711b5d5d2bd0970c.4f15aaf2108c0731.c03fd11db2cb72d8.f9eb09490e61bf77
+ 9ef267a7c2761e50.b1669cc57501433d.ac1f1ad160585817.cd96e01b06f78bbb
+ b291920f4196b181.f2bcbe6b2c5e8e9a.51a0856ca79a2e6c.14e0ab4bc16e073a
+ 28146543da536fa1
+ after
+ 4e40f74560986188.717dee855e729cca.b1352e6681e6be85.3b9229683d2066c3
+ 711b5d5d2bd0970c.4f15aaf2108c0731.c03fd11db2cb72d8.f9eb09490e61bf77
+ 0000000000000000.0000000000000000.d0b1901f018e3d5b.f28ba1bb1476b62e
+ b291920f4196b181.f2bcbe6b2c5e8e9a.51a0856ca79a2e6c.14e0ab4bc16e073a
+ 28146543da536fa1
+
+VPHSUBD_128(reg)
+ before
+ 66800a71ed31fe9c.89c45881c33c0dca.70620e50ce2e22f5.8b8f8edca49cae03
+ 2a6e973f9794f1d6.ff5637e96575ed58.86a688e1f9fd3cfa.36b8b10b726a950a
+ d02b061b730984fb.f015aa33424d0f57.8fd2268949571754.2ee76be72e109eaa
+ b40455701e1bf3b8.38cb2e4b77ce2df2.e933e6b359c9f0b0.4fe8365bf49b8612
+ 75879053de17096c
+ after
+ 0000000000000000.0000000000000000.b984f0cbff2932c3.7356b4193bb1e3ff
+ 2a6e973f9794f1d6.ff5637e96575ed58.86a688e1f9fd3cfa.36b8b10b726a950a
+ d02b061b730984fb.f015aa33424d0f57.8fd2268949571754.2ee76be72e109eaa
+ b40455701e1bf3b8.38cb2e4b77ce2df2.e933e6b359c9f0b0.4fe8365bf49b8612
+ 75879053de17096c
+VPHSUBD_128(mem)
+ before
+ 7c8ff5bb0b8ee3e4.32427fa9335679b9.b3453d1e1f060456.ee15c3cdc5df03ba
+ 40cedf7f940ecfa8.a63480344f4753aa.3d4f559656004fae.fcc4b9422a238c1d
+ 9d0ecc8b98a38ae1.6c25557c0d79bd36.b1b5f1a139c9cb27.6d8cc47e2423c785
+ 6f1c36cb3057d0be.e060f8ed0a79f309.ed438e2ae36c34ec.9fb8e1ed4e6aefa0
+ ec960bfb44854118
+ after
+ 7c8ff5bb0b8ee3e4.32427fa9335679b9.b3453d1e1f060456.ee15c3cdc5df03ba
+ 40cedf7f940ecfa8.a63480344f4753aa.3d4f559656004fae.fcc4b9422a238c1d
+ 0000000000000000.0000000000000000.6bc0c738d7c93fed.18b0fa182d5ed2db
+ 6f1c36cb3057d0be.e060f8ed0a79f309.ed438e2ae36c34ec.9fb8e1ed4e6aefa0
+ ec960bfb44854118
+
+VPHSUBD_128(reg)
+ before
+ b2703e14a3fff899.91c49c2b7a385d69.5e3367f4e1d130d0.ccc4a61c71f5462b
+ 4b9376a5066451d0.e1d277989252ec0e.42e89dfb2f10b137.2a05b765ff71bc0d
+ 144baf180a418969.3a1144fc93af3ada.e8cc976f8fbfb2e9.e3d23cf0a8eb53c1
+ 6ae4e6db4b21d90f.774f80459a5d03f9.ac2b4fbd9d6c6e93.d2f7b1aa886fc771
+ d540927dbc0ad449
+ after
+ 0000000000000000.0000000000000000.a6f31b7ac51916d1.ec28133cd56c04a8
+ 4b9376a5066451d0.e1d277989252ec0e.42e89dfb2f10b137.2a05b765ff71bc0d
+ 144baf180a418969.3a1144fc93af3ada.e8cc976f8fbfb2e9.e3d23cf0a8eb53c1
+ 6ae4e6db4b21d90f.774f80459a5d03f9.ac2b4fbd9d6c6e93.d2f7b1aa886fc771
+ d540927dbc0ad449
+VPHSUBD_128(mem)
+ before
+ c7795c565fc73576.a7a916586390806f.7656a65ec2680296.ea50c34ff6a222e1
+ 836e89218eb3a724.28e83bfdf11bb834.12f3323327daf4de.fd89ee9336ee0a7e
+ e7ea98cb64d8e67e.49eb51358e4dbe0b.26f2a1b0e6c195fd.4320ccf4f8da6117
+ cdba023efd44adb1.67ff556cd8b2cda0.901f6dc11a29a11e.17625aded8f56557
+ d49b92bd73c850eb
+ after
+ c7795c565fc73576.a7a916586390806f.7656a65ec2680296.ea50c34ff6a222e1
+ 836e89218eb3a724.28e83bfdf11bb834.12f3323327daf4de.fd89ee9336ee0a7e
+ 0000000000000000.0000000000000000.4c115c380c515f92.14e7c2ab39641beb
+ cdba023efd44adb1.67ff556cd8b2cda0.901f6dc11a29a11e.17625aded8f56557
+ d49b92bd73c850eb
+
+VPHSUBSW_128(reg)
+ before
+ d81772fd64e15e7f.13aa44687703b9e9.dc70420e6bd7239e.2a451452e01dd36e
+ 7e22f50a48cbcdbe.9386db34eb20c651.058a1487e247fab2.d232114f54a9e818
+ 21081850ba13d754.2b1a428e77a79015.3e99c743da8f8f87.62b0e1a490d99c49
+ 1f14d53c5744b9ef.b531f56237a4d263.e3e857aeee391dca.b88cfe3eb3baaa2c
+ ae92e607d657cfee
+ after
+ 0000000000000000.0000000000000000.88aab4f880000b70.0efd186b3f1d936f
+ 7e22f50a48cbcdbe.9386db34eb20c651.058a1487e247fab2.d232114f54a9e818
+ 21081850ba13d754.2b1a428e77a79015.3e99c743da8f8f87.62b0e1a490d99c49
+ 1f14d53c5744b9ef.b531f56237a4d263.e3e857aeee391dca.b88cfe3eb3baaa2c
+ ae92e607d657cfee
+VPHSUBSW_128(mem)
+ before
+ 228e14ed18bdc7bb.d2932a38baeaae39.0f99709c46244964.50c5c135bad3e127
+ ee4c04da92f64ebe.98d212b28092f4de.131c3028c032b147.e17a0042dbe91749
+ ef9832bc63111f24.cb1a891444c7c58b.9e87aff2c2dbc536.f2541043ed06fbdd
+ 023d1b7ea417f718.c9ba8ccca3155dec.8da66be66729425e.df9feda38ab6c88e
+ 04a694cd5185bb09
+ after
+ 228e14ed18bdc7bb.d2932a38baeaae39.0f99709c46244964.50c5c135bad3e127
+ ee4c04da92f64ebe.98d212b28092f4de.131c3028c032b147.e17a0042dbe91749
+ 0000000000000000.0000000000000000.6103034080002654.1d0cf1151ec83b60
+ 023d1b7ea417f718.c9ba8ccca3155dec.8da66be66729425e.df9feda38ab6c88e
+ 04a694cd5185bb09
+
+VPHSUBSW_128(reg)
+ before
+ bdb7002fdc0010fa.01083a0c731692c7.ecfd15453808faac.ba45e0f1cc2be4ea
+ 661c2c34c7b2030c.c9c50b52ec19ab5d.912e22eba02dd678.023088fd0dea6707
+ 5a231748af28cfec.36400a3c2a2dff05.159bae2a76102efb.4132e1f8447486e0
+ f716bad72fedb145.2445b3b6495c4aec.d28eb56e563b3de2.531966cc90d4fea2
+ 15af93670a178b79
+ after
+ 0000000000000000.0000000000000000.988fb8eba0c68000.7fff364b86cd591d
+ 661c2c34c7b2030c.c9c50b52ec19ab5d.912e22eba02dd678.023088fd0dea6707
+ 5a231748af28cfec.36400a3c2a2dff05.159bae2a76102efb.4132e1f8447486e0
+ f716bad72fedb145.2445b3b6495c4aec.d28eb56e563b3de2.531966cc90d4fea2
+ 15af93670a178b79
+VPHSUBSW_128(mem)
+ before
+ 61c1e4b4d148e890.9842134ee48de5c4.70a083ad66b5483e.25543423dd3c41d9
+ 141bd59ffe73d314.99f31d176994a615.f41cf50b9d41b426.6b3926b5a79f748b
+ 0a88e314afa50630.5574d49f5b8f31e3.8d8685be090e4bd0.fe8987904eef13a5
+ 1fd689ff00e83d11.2a1334535509c2da.17aaafb0c627c969.3b8f532171b859d3
+ 7e9886d2aa8683c0
+ after
+ 61c1e4b4d148e890.9842134ee48de5c4.70a083ad66b5483e.25543423dd3c41d9
+ 141bd59ffe73d314.99f31d176994a615.f41cf50b9d41b426.6b3926b5a79f748b
+ 0000000000000000.0000000000000000.8000e1890ecf649d.00ef16e5bb7c7fff
+ 1fd689ff00e83d11.2a1334535509c2da.17aaafb0c627c969.3b8f532171b859d3
+ 7e9886d2aa8683c0
+
+VPHSUBSW_128(reg)
+ before
+ 23f11d1195e6cd18.2fcf434d0c4b36e3.731a399df38f94a8.6e54f0cff199ea1d
+ 86e41349cf637388.16418ee8f0d7abd1.8bd6e0ebd2ace5f7.6e50c306a56f6918
+ 03be64e6f389b0bc.b0f6e4bdc79a5808.d09324a88eecef73.f36aa441ffb50385
+ f6cb0c549ee5c160.d9bbc3b9ada0fbb3.9c9d0140c2dceec9.d96d0f6c1a787390
+ fb27807313c37766
+ after
+ 0000000000000000.0000000000000000.54156087b0d703d0.5515134b80007fff
+ 86e41349cf637388.16418ee8f0d7abd1.8bd6e0ebd2ace5f7.6e50c306a56f6918
+ 03be64e6f389b0bc.b0f6e4bdc79a5808.d09324a88eecef73.f36aa441ffb50385
+ f6cb0c549ee5c160.d9bbc3b9ada0fbb3.9c9d0140c2dceec9.d96d0f6c1a787390
+ fb27807313c37766
+VPHSUBSW_128(mem)
+ before
+ 3762744205a2c933.bb5607ff6b02e21f.6c5ba6c7bff34eff.4d40731f0a0720a5
+ 68eb66c50d222622.aead5253f76c4ea5.47a409d219a10e18.3dc777b103f9bfb2
+ 6a8ed2e9464e4960.2b1ae8bcddb0439f.456169c8d6b6f729.ca800862493e089d
+ 19173498cd32ef19.8eeac5a6b959fbb9.425d4194123cc45e.4eb5229e77633611
+ 26b3c1d229f487bc
+ after
+ 3762744205a2c933.bb5607ff6b02e21f.6c5ba6c7bff34eff.4d40731f0a0720a5
+ 68eb66c50d222622.aead5253f76c4ea5.47a409d219a10e18.3dc777b103f9bfb2
+ 0000000000000000.0000000000000000.80007fff25df169e.c22ef47739eabbb9
+ 19173498cd32ef19.8eeac5a6b959fbb9.425d4194123cc45e.4eb5229e77633611
+ 26b3c1d229f487bc
+
+VPABSB_128(reg)
+ before
+ afc6e268fc7b3547.505109c0bddbd478.3369e57e29f4b29e.1a650c22ea4132e5
+ 433a7fce8b867d60.ed0acc4b3254b4aa.76e345aec60ca6fb.a845495e79d1fde8
+ 3f5a966e73a19ab3.cb0cf82749a94bda.b2a4e0a42e2d117c.cac97134dcf6e193
+ 007422b64f56c9ec.c5240c3f1ee75435.45f7b2cafde330cc.5bbd02912ebe9913
+ 36ec765f8c35e294
+ after
+ 0000000000000000.0000000000000000.4e5c205c2e2d117c.36377134240a1f6d
+ 433a7fce8b867d60.ed0acc4b3254b4aa.76e345aec60ca6fb.a845495e79d1fde8
+ 3f5a966e73a19ab3.cb0cf82749a94bda.b2a4e0a42e2d117c.cac97134dcf6e193
+ 007422b64f56c9ec.c5240c3f1ee75435.45f7b2cafde330cc.5bbd02912ebe9913
+ 36ec765f8c35e294
+VPABSB_128(mem)
+ before
+ 39234b8b11667841.e0d22011bc3346b6.b91e817fcc198ce6.8a29b78ecebb3e98
+ 3e2ffd02da5d1647.3cc18aeb55c44dbd.81c6d5d36f4cae1b.dd87eb5b3d40788b
+ 23da06af022679d2.708d5eb0b69419af.fbe78327248a77fd.995b4b9de7ff1a52
+ c2f1e47da5ce5d0d.d88297cc7d2fe735.024f076706e1a3bb.1cf2d2c067836099
+ c1977c305a58850b
+ after
+ 39234b8b11667841.e0d22011bc3346b6.b91e817fcc198ce6.8a29b78ecebb3e98
+ 3e2ffd02da5d1647.3cc18aeb55c44dbd.81c6d5d36f4cae1b.dd87eb5b3d40788b
+ 0000000000000000.0000000000000000.471e7f7f3419741a.7629497232453e68
+ c2f1e47da5ce5d0d.d88297cc7d2fe735.024f076706e1a3bb.1cf2d2c067836099
+ c1977c305a58850b
+
+VPABSB_128(reg)
+ before
+ e398455a5b0bc754.f93f125ae0607e25.d0ec31ab4321f3fe.71c8dd7f325dee7e
+ e03f2aa807275f22.a2920c31cfe89745.b41629b9a6f778b4.251f815cc3091475
+ 12da2687f9388c1f.9bb44eee8d73659a.e04d7963423cb403.fb2070e8d6f1d0ca
+ d7b33564ceca88f7.be73557d360ca44f.b0de1f13b27ce099.cd9725118621dfaa
+ 79501cc1f0a6fc40
+ after
+ 0000000000000000.0000000000000000.204d7963423c4c03.052070182a0f3036
+ e03f2aa807275f22.a2920c31cfe89745.b41629b9a6f778b4.251f815cc3091475
+ 12da2687f9388c1f.9bb44eee8d73659a.e04d7963423cb403.fb2070e8d6f1d0ca
+ d7b33564ceca88f7.be73557d360ca44f.b0de1f13b27ce099.cd9725118621dfaa
+ 79501cc1f0a6fc40
+VPABSB_128(mem)
+ before
+ d917d2e62f8be4b9.891753a9216a9057.e8999bcbe7c00f91.8013163792443b1f
+ cab7c16b60dd5340.85527cc48fa4e0eb.f6f39ec2bc9a638c.ac395a397f1fff44
+ 28fd673c9ea70502.28afad20b302b35e.c24dda4fcfa65c6b.909be887149a6ab2
+ d0b53f4506f5b62b.cc7ce1292912475d.2972c95f3ff0b65b.8887bb8cee3fb515
+ f047cfb4a89d1f1a
+ after
+ d917d2e62f8be4b9.891753a9216a9057.e8999bcbe7c00f91.8013163792443b1f
+ cab7c16b60dd5340.85527cc48fa4e0eb.f6f39ec2bc9a638c.ac395a397f1fff44
+ 0000000000000000.0000000000000000.1867653519400f6f.801316376e443b1f
+ d0b53f4506f5b62b.cc7ce1292912475d.2972c95f3ff0b65b.8887bb8cee3fb515
+ f047cfb4a89d1f1a
+
+VPABSB_128(reg)
+ before
+ 2429206bdf3de26d.9cabc572b3d321e6.cf03144b8f60d693.0730e9dc26852c87
+ 7f77aa1d2ead3bba.69ab76afc14e0360.8b9142f27e769cad.3951b4b4a0707b1c
+ 5f7e6a36327866ab.1381cce94d7117c4.5d72688a94e2d657.99a2a8d2cabe5f46
+ 1f895b23862b9eef.76f8450a73491b3f.a1f2807f6c30c13c.04ef4122bf7a9330
+ 5604f9909cb0d507
+ after
+ 0000000000000000.0000000000000000.5d7268766c1e2a57.675e582e36425f46
+ 7f77aa1d2ead3bba.69ab76afc14e0360.8b9142f27e769cad.3951b4b4a0707b1c
+ 5f7e6a36327866ab.1381cce94d7117c4.5d72688a94e2d657.99a2a8d2cabe5f46
+ 1f895b23862b9eef.76f8450a73491b3f.a1f2807f6c30c13c.04ef4122bf7a9330
+ 5604f9909cb0d507
+VPABSB_128(mem)
+ before
+ 6bad4e087c6ddff6.1be6794ec7512030.6edd5c004de1c9fd.b45d883ea3ea9609
+ 1fb5bb767bbc6d2a.aedfc0259076281b.d7fc8eb5fa45de29.f0fe7b31d59e946a
+ 4eeabcc6b6a93dcf.36c22c127e26f25b.8d215517948215f0.b22356c69dd8f50a
+ d416cee549400910.0dd9ba832ceeb99d.6c182f1137a32b7d.561613679723f695
+ 3824b082600bd2b8
+ after
+ 6bad4e087c6ddff6.1be6794ec7512030.6edd5c004de1c9fd.b45d883ea3ea9609
+ 1fb5bb767bbc6d2a.aedfc0259076281b.d7fc8eb5fa45de29.f0fe7b31d59e946a
+ 0000000000000000.0000000000000000.6e235c004d1f3703.4c5d783e5d166a09
+ d416cee549400910.0dd9ba832ceeb99d.6c182f1137a32b7d.561613679723f695
+ 3824b082600bd2b8
+
+VPABSW_128(reg)
+ before
+ b4992882931cc71f.8d066bbd4f8e8d1a.917165e33659ba8d.50ad978f00b4dcfd
+ 26c177d3cde30f76.5586113ce49f8718.1dd6299e39f431d6.15ab097d0ac2e49c
+ eae79ae1a9ebe767.08623b4c257db137.0c530320d14a5924.97e002c772d8fe85
+ 5c598c18c4c08aa1.816665db2e36c8a3.bb36edd599e76f25.b216fc595302e7e5
+ 421a751fca4c5be7
+ after
+ 0000000000000000.0000000000000000.0c5303202eb65924.682002c772d8017b
+ 26c177d3cde30f76.5586113ce49f8718.1dd6299e39f431d6.15ab097d0ac2e49c
+ eae79ae1a9ebe767.08623b4c257db137.0c530320d14a5924.97e002c772d8fe85
+ 5c598c18c4c08aa1.816665db2e36c8a3.bb36edd599e76f25.b216fc595302e7e5
+ 421a751fca4c5be7
+VPABSW_128(mem)
+ before
+ 22b8e806f2c416b8.d86149e4b9ef35ce.9e5d0cd41ad68887.87c9e5292d58af82
+ 30bcd2f8e773d384.ba4ccdb22403249b.3a14aa230567ac10.ca5ae6882a2855ea
+ 47f1ade3c6674f76.5e6614eca28993b3.3158bdb40cf7f169.e233ec5e2be39c07
+ 4325f7b1abab46ba.1ffb1b00cf0cbdc3.5ef3c1734a9213bf.29a1f418cd16c186
+ fceff820ab4c0012
+ after
+ 22b8e806f2c416b8.d86149e4b9ef35ce.9e5d0cd41ad68887.87c9e5292d58af82
+ 30bcd2f8e773d384.ba4ccdb22403249b.3a14aa230567ac10.ca5ae6882a2855ea
+ 0000000000000000.0000000000000000.61a30cd41ad67779.78371ad72d58507e
+ 4325f7b1abab46ba.1ffb1b00cf0cbdc3.5ef3c1734a9213bf.29a1f418cd16c186
+ fceff820ab4c0012
+
+VPABSW_128(reg)
+ before
+ b86bf6e462119458.ff222b50b14b737e.5b57dc584618e077.9fb1304cdc42ce3d
+ b75fe9cf8df2ba03.59b5c5abf45493ec.6dc55562a339357a.cf60872bdd16dd11
+ 5619ce4dc97aaec0.2baa41ae91d16230.b193828983fcfb79.c9cb43fd6a17fd64
+ f1e39fcab135ac3b.53cd1c45a4ce9c77.820b5d3882ec6c1f.6bbddfac9e53ea65
+ 8f03d72696d55f3e
+ after
+ 0000000000000000.0000000000000000.4e6d7d777c040487.363543fd6a17029c
+ b75fe9cf8df2ba03.59b5c5abf45493ec.6dc55562a339357a.cf60872bdd16dd11
+ 5619ce4dc97aaec0.2baa41ae91d16230.b193828983fcfb79.c9cb43fd6a17fd64
+ f1e39fcab135ac3b.53cd1c45a4ce9c77.820b5d3882ec6c1f.6bbddfac9e53ea65
+ 8f03d72696d55f3e
+VPABSW_128(mem)
+ before
+ 1369a8556da9191b.e40a5ab2e2b0ef1f.ace9d15c4858fced.3e7ae4dd3b96c519
+ d1bbcd273fdcd429.8cdafa71f776b419.11ccdcdf997a3fbd.402c12e34a854213
+ a7c5c1872a794c94.439e7b738d1337d4.6040b9bab4402114.e36de3b74c451eb8
+ 6f530361478d3c87.66a4da243f14b4fd.7312e5dab4b75d1e.858853c3dc6396b4
+ 80cb5f74976ae6b5
+ after
+ 1369a8556da9191b.e40a5ab2e2b0ef1f.ace9d15c4858fced.3e7ae4dd3b96c519
+ d1bbcd273fdcd429.8cdafa71f776b419.11ccdcdf997a3fbd.402c12e34a854213
+ 0000000000000000.0000000000000000.53172ea448580313.3e7a1b233b963ae7
+ 6f530361478d3c87.66a4da243f14b4fd.7312e5dab4b75d1e.858853c3dc6396b4
+ 80cb5f74976ae6b5
+
+VPABSW_128(reg)
+ before
+ 3280013718e64a64.07300ca1b422612f.513611f1a9046640.270eda29b6eab006
+ f5f43776fc63fd70.492959338c4677b7.60a11e4468708a48.59001695d5e6d6f8
+ 2773fc9fde6e3c83.120a6703ec05394c.ef31fc8b17e25bc2.e3b415092eb68b22
+ 22494d1d5b93434a.3f9fb1fdf06a641a.5a32a83053e91759.a2f65170dc668aad
+ 739148b8fc0290c8
+ after
+ 0000000000000000.0000000000000000.10cf037517e25bc2.1c4c15092eb674de
+ f5f43776fc63fd70.492959338c4677b7.60a11e4468708a48.59001695d5e6d6f8
+ 2773fc9fde6e3c83.120a6703ec05394c.ef31fc8b17e25bc2.e3b415092eb68b22
+ 22494d1d5b93434a.3f9fb1fdf06a641a.5a32a83053e91759.a2f65170dc668aad
+ 739148b8fc0290c8
+VPABSW_128(mem)
+ before
+ 305274cca997599d.44c1245b0e5c4d70.aab4b30eb381b44c.fcf01ca1b80ef8ba
+ b6055398ff30a059.e7297fc7935797a2.3015ea205156e50f.33b75649e1df3b91
+ e17661081bda2227.68cb59cc87105d8b.ad8dd021e7f6b28f.5ad251946ae71b89
+ 8e71180919a09b34.24f4afd68611dbd8.feeae3fc906dd8f7.cd8e09eef0b2d54f
+ e8377ac30ecda58e
+ after
+ 305274cca997599d.44c1245b0e5c4d70.aab4b30eb381b44c.fcf01ca1b80ef8ba
+ b6055398ff30a059.e7297fc7935797a2.3015ea205156e50f.33b75649e1df3b91
+ 0000000000000000.0000000000000000.554c4cf24c7f4bb4.03101ca147f20746
+ 8e71180919a09b34.24f4afd68611dbd8.feeae3fc906dd8f7.cd8e09eef0b2d54f
+ e8377ac30ecda58e
+
+VPMOVSXBQ_128(reg)
+ before
+ 0719a17f61c4c7f3.97c2f685148ec7ab.75f17b512be84c35.fdf69e9c69c51373
+ 8580798f84217629.d934766928b161b9.b80bbbaa1221ed4d.877e7eef8d0c1e30
+ c0b8fe5d1372f0de.309414a27213268a.49916a4bd846facd.784efde0194db75a
+ 130c2c56ac426ebb.78ae4c1a0dc3d249.84ce84a219e5ae60.ac31995b2895981d
+ fff5cd4dd6ef7da4
+ after
+ 0719a17f61c4c7f3.97c2f685148ec7ab.75f17b512be84c35.fdf69e9c69c51373
+ 0000000000000000.0000000000000000.ffffffffffffffb7.000000000000005a
+ c0b8fe5d1372f0de.309414a27213268a.49916a4bd846facd.784efde0194db75a
+ 130c2c56ac426ebb.78ae4c1a0dc3d249.84ce84a219e5ae60.ac31995b2895981d
+ fff5cd4dd6ef7da4
+VPMOVSXBQ_128(mem)
+ before
+ 4d6415a04167241b.d9ca00e7e81e2f6f.8d4e9bbf16ca2123.c60d0519708a47b3
+ 724ced41820a47af.703c747b65916da3.4b407b7ca936ce43.699bea1e79bfff72
+ 4a77d21db7e3a28c.32af867ebf276506.8e506a3de01396d6.cac42e1cd1131248
+ b1b23f1efcfef3de.7d6f315b916c5342.324ae4eeda6b3408.45d4cd7e130fbee2
+ 3617c3b2dc413deb
+ after
+ 4d6415a04167241b.d9ca00e7e81e2f6f.8d4e9bbf16ca2123.c60d0519708a47b3
+ 0000000000000000.0000000000000000.0000000000000047.ffffffffffffffb3
+ 4a77d21db7e3a28c.32af867ebf276506.8e506a3de01396d6.cac42e1cd1131248
+ b1b23f1efcfef3de.7d6f315b916c5342.324ae4eeda6b3408.45d4cd7e130fbee2
+ 3617c3b2dc413deb
+
+VPMOVSXBQ_128(reg)
+ before
+ f9d90d23c734cb10.83c8b0326c68f4cf.abc7728077ed7204.13f9637bb04c6604
+ ea65a53d7174a6fd.9b87a143232c628e.1a0543590e36fff7.0c2a65d081c1e6f6
+ 6508896d758e085d.d7ba8f3f3e56f945.2473a250f2d136c8.fba965d966d7710c
+ c60fb41d6f0d2edd.122cf411d8f37421.275e8ad2bd4c5322.bb42df837d99c270
+ 28c14fb8e213964e
+ after
+ f9d90d23c734cb10.83c8b0326c68f4cf.abc7728077ed7204.13f9637bb04c6604
+ 0000000000000000.0000000000000000.0000000000000071.000000000000000c
+ 6508896d758e085d.d7ba8f3f3e56f945.2473a250f2d136c8.fba965d966d7710c
+ c60fb41d6f0d2edd.122cf411d8f37421.275e8ad2bd4c5322.bb42df837d99c270
+ 28c14fb8e213964e
+VPMOVSXBQ_128(mem)
+ before
+ 1df13266b052a9d3.68c423bafc7e5428.28aa4ea50e0e904d.7d12f74b0e3391b2
+ 78a002770461b72b.a973d0b1b86cb5eb.f40018e7fbb309f6.83dbe6287f102d24
+ 14983dd9f94d7c81.e46ab96c3e638ed2.54facfc3bcef9b48.960551d3ac716323
+ cca65e77ab20b302.75f4d9592aef1b88.2364ed266ccd016e.10dc36ba32e26e5c
+ 4eab9048aced8c7b
+ after
+ 1df13266b052a9d3.68c423bafc7e5428.28aa4ea50e0e904d.7d12f74b0e3391b2
+ 0000000000000000.0000000000000000.ffffffffffffff91.ffffffffffffffb2
+ 14983dd9f94d7c81.e46ab96c3e638ed2.54facfc3bcef9b48.960551d3ac716323
+ cca65e77ab20b302.75f4d9592aef1b88.2364ed266ccd016e.10dc36ba32e26e5c
+ 4eab9048aced8c7b
+
+VPMOVSXBQ_128(reg)
+ before
+ acc05ce8b720f72b.7e96e23d37e818da.b85c2ce3199d98ba.3c09f0fa2859f895
+ 87659408ee07eb18.05344317b8b16934.08efaf76a7f84013.7db6532d0ba03ce8
+ 39e73613ed2ca5f0.3c4cfff14b86603d.c3f95c7e6f8d5040.c03892a932ad8894
+ 1f913d76511d625c.01a991b70c73ba20.44c631670de704ec.e3592a5cb88c99c4
+ c0e69531ba4a2ba5
+ after
+ acc05ce8b720f72b.7e96e23d37e818da.b85c2ce3199d98ba.3c09f0fa2859f895
+ 0000000000000000.0000000000000000.ffffffffffffff88.ffffffffffffff94
+ 39e73613ed2ca5f0.3c4cfff14b86603d.c3f95c7e6f8d5040.c03892a932ad8894
+ 1f913d76511d625c.01a991b70c73ba20.44c631670de704ec.e3592a5cb88c99c4
+ c0e69531ba4a2ba5
+VPMOVSXBQ_128(mem)
+ before
+ 35aa511353f2fa63.95b1a59bb6665b0b.2e1876551584330a.e6a2299d1e9297c5
+ 1c73d9f09f91c129.f7926befb792cfa7.a16528b885c68626.07d9418c3d1b4674
+ 530baab3bb313d24.a17f89def02df8dc.345d25ca764471a1.01b673a1070c4da8
+ b4403e49c3e12a80.efc5fdd5fec31357.c4c9e879040aaea7.3286bd4617f4e80a
+ f4951ae90a5c5249
+ after
+ 35aa511353f2fa63.95b1a59bb6665b0b.2e1876551584330a.e6a2299d1e9297c5
+ 0000000000000000.0000000000000000.ffffffffffffff97.ffffffffffffffc5
+ 530baab3bb313d24.a17f89def02df8dc.345d25ca764471a1.01b673a1070c4da8
+ b4403e49c3e12a80.efc5fdd5fec31357.c4c9e879040aaea7.3286bd4617f4e80a
+ f4951ae90a5c5249
+
+VPMOVSXWQ_128(reg)
+ before
+ a52f86f47bd2c80f.1cdc139cd2aa4368.3db0c23e7de15cc4.2e78edb04b25f963
+ 9fa0fdd507e28609.68aca499049a4508.e78cd58708120ecf.4c35b05a69a00f02
+ 3f347cf74916c7e2.727c6d2c76bcec8e.49a5301b3be26623.fbcbae657788acb0
+ e236fec6ddfcc847.1717eb42431df423.bf46d166b3dea06c.180762bc93e88c98
+ 7db5484bd9cc6be6
+ after
+ a52f86f47bd2c80f.1cdc139cd2aa4368.3db0c23e7de15cc4.2e78edb04b25f963
+ 0000000000000000.0000000000000000.0000000000007788.ffffffffffffacb0
+ 3f347cf74916c7e2.727c6d2c76bcec8e.49a5301b3be26623.fbcbae657788acb0
+ e236fec6ddfcc847.1717eb42431df423.bf46d166b3dea06c.180762bc93e88c98
+ 7db5484bd9cc6be6
+VPMOVSXWQ_128(mem)
+ before
+ 07a1dcfe644104c7.e2f47fae601fc5e3.334b98c688c718f6.a4bdb3d40b91f757
+ 92979ac250511467.9cb8fb1b6e0cfa63.a3e2f2a360c91531.5654d2d1e088a990
+ fa63ff81ba0b56f2.6dcf6f79a24ea273.41a974c7e82ca700.30582ac9cd4ef0c2
+ 1bd08628be788893.af85d6349872fabe.ea6c9b1d3bfe8991.8e15b8286f6f089a
+ ccd7775a61772fc4
+ after
+ 07a1dcfe644104c7.e2f47fae601fc5e3.334b98c688c718f6.a4bdb3d40b91f757
+ 0000000000000000.0000000000000000.0000000000000b91.fffffffffffff757
+ fa63ff81ba0b56f2.6dcf6f79a24ea273.41a974c7e82ca700.30582ac9cd4ef0c2
+ 1bd08628be788893.af85d6349872fabe.ea6c9b1d3bfe8991.8e15b8286f6f089a
+ ccd7775a61772fc4
+
+VPMOVSXWQ_128(reg)
+ before
+ 45ea63cc40f39feb.d1ababa477a66476.bf252bb8ed023ef1.7af7e191764a790d
+ 579978e8a76f95bc.f8c1eae001a0a7c9.f9fd6d723d8ca9b7.cd16c40fb41d31a3
+ 5c31b31c33754ce2.6cdcc0c779730cb5.b95795cc239c78bd.bf95bf8312826d7d
+ b2fe0ed37f93010a.09c8a847fa2a5069.5c81a1343bbce7af.2c3f4ed9ab85ebc7
+ f0e1edfe9b3365af
+ after
+ 45ea63cc40f39feb.d1ababa477a66476.bf252bb8ed023ef1.7af7e191764a790d
+ 0000000000000000.0000000000000000.0000000000001282.0000000000006d7d
+ 5c31b31c33754ce2.6cdcc0c779730cb5.b95795cc239c78bd.bf95bf8312826d7d
+ b2fe0ed37f93010a.09c8a847fa2a5069.5c81a1343bbce7af.2c3f4ed9ab85ebc7
+ f0e1edfe9b3365af
+VPMOVSXWQ_128(mem)
+ before
+ e74719dcff97975e.b44c87782754f0df.ab531e4ba1d12f0f.3cc58b15227a3238
+ ed3d4d61f3bd3f03.bd671979c845550f.2e489ebf897565d3.b67051db73629405
+ de8f057792b217c8.2b9bc141fef16c43.6e72a48fcf21ade2.26cdeff2cbff4ac1
+ 9509bd0cf881dcd9.5834793c64e4702a.479eada78ee1c468.e82a5fc6c5dd9019
+ 58d19fc3fd88a2b9
+ after
+ e74719dcff97975e.b44c87782754f0df.ab531e4ba1d12f0f.3cc58b15227a3238
+ 0000000000000000.0000000000000000.000000000000227a.0000000000003238
+ de8f057792b217c8.2b9bc141fef16c43.6e72a48fcf21ade2.26cdeff2cbff4ac1
+ 9509bd0cf881dcd9.5834793c64e4702a.479eada78ee1c468.e82a5fc6c5dd9019
+ 58d19fc3fd88a2b9
+
+VPMOVSXWQ_128(reg)
+ before
+ d110aa55118dbb4c.f076f10b42364a63.a27d3fd796ab9e6d.959834f3e3c26690
+ b1317ce89a77187f.caa31e608bde1c92.63c30e7c31d131bb.342cb560e9cf4f87
+ 538111e936d3f5fd.ff5dbff7f0840f91.f852e298d0e266be.ff26acd8bd143a79
+ 134c66c2812b8d73.6a6e50bc8d34df8d.be76b898106b7923.d45196497a9ee491
+ 8e7bee9d3c7809fc
+ after
+ d110aa55118dbb4c.f076f10b42364a63.a27d3fd796ab9e6d.959834f3e3c26690
+ 0000000000000000.0000000000000000.ffffffffffffbd14.0000000000003a79
+ 538111e936d3f5fd.ff5dbff7f0840f91.f852e298d0e266be.ff26acd8bd143a79
+ 134c66c2812b8d73.6a6e50bc8d34df8d.be76b898106b7923.d45196497a9ee491
+ 8e7bee9d3c7809fc
+VPMOVSXWQ_128(mem)
+ before
+ 086e30c220ae64e5.4ddd76e1160e1d8d.e9a24e9b7cfb48b2.0f7b8be68cf7a695
+ 20f7d8a3424db279.5d823db09105e1f6.57c73380dce4052b.48ad56f0e11229c1
+ b1e2622cbd60afe4.9e85b79d8f9e145b.8fa87d58c6fbd325.c5571820aa493d52
+ 96fb4b49adf31751.6e33e013ac64f467.6f10a70d584d6ecb.e3c6cae484271ff5
+ fc4669a70a380a56
+ after
+ 086e30c220ae64e5.4ddd76e1160e1d8d.e9a24e9b7cfb48b2.0f7b8be68cf7a695
+ 0000000000000000.0000000000000000.ffffffffffff8cf7.ffffffffffffa695
+ b1e2622cbd60afe4.9e85b79d8f9e145b.8fa87d58c6fbd325.c5571820aa493d52
+ 96fb4b49adf31751.6e33e013ac64f467.6f10a70d584d6ecb.e3c6cae484271ff5
+ fc4669a70a380a56
+
+VPACKUSDW_128(reg)
+ before
+ 6d23f2d5d9093c20.ad0e0ee62f13a5ec.28d9b57e83e4bbc7.d2cc2d8daee5914a
+ 92a960da8c25ef00.d0e627ef5ecb16e3.27c0314ab0a9a526.93a88cc2e3cff9cd
+ c724af23bf1860a1.dd50125157282660.c93750e3d03ff032.90703e9a14186282
+ 68dfdc1a0f6fcab0.ae194bf63535908f.68890eb67e32d694.a3f0c1005ccb8892
+ a9f490e0d7f5262b
+ after
+ 0000000000000000.0000000000000000.000000000000ffff.ffff000000000000
+ 92a960da8c25ef00.d0e627ef5ecb16e3.27c0314ab0a9a526.93a88cc2e3cff9cd
+ c724af23bf1860a1.dd50125157282660.c93750e3d03ff032.90703e9a14186282
+ 68dfdc1a0f6fcab0.ae194bf63535908f.68890eb67e32d694.a3f0c1005ccb8892
+ a9f490e0d7f5262b
+VPACKUSDW_128(mem)
+ before
+ 7f472826a2a1f979.d128e12c18b56ad9.210b4fcb15fe119d.6201682d570f94fb
+ ffb603bed9dbbda8.5e49bcc675767cc7.10f299bd128f65b6.12ec59b5f6626510
+ 070d9f9497af2de3.6b8f6852c23f3c27.589ca5b749f54805.d397ddbbf8b58782
+ 71187795f82a0656.5446e23e9c9be5a4.d6d4f0a4d53b75b7.024cf0a9f89634fb
+ fc578eed9390a828
+ after
+ 7f472826a2a1f979.d128e12c18b56ad9.210b4fcb15fe119d.6201682d570f94fb
+ ffb603bed9dbbda8.5e49bcc675767cc7.10f299bd128f65b6.12ec59b5f6626510
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffffffffffff0000
+ 71187795f82a0656.5446e23e9c9be5a4.d6d4f0a4d53b75b7.024cf0a9f89634fb
+ fc578eed9390a828
+
+VPACKUSDW_128(reg)
+ before
+ 1b06b4f2643021b4.1aa307ab1957042f.75ba24f59f17b4eb.6465f472d36ea9f7
+ bda45d240701d94c.de7accc41543e398.2a362ce3653ee5a8.df1c2f0c5e98a0f2
+ 3c7c85ef198f0d9b.9a6840ca09f95ebd.cf08f5748d9cb486.23c51c5e93c815d4
+ f5db28bf3667f84e.283be1ab108532cb.c07a7b14b1bd5c32.0c2c37548d07c5c8
+ 771dfddb68636cfb
+ after
+ 0000000000000000.0000000000000000.00000000ffff0000.ffffffff0000ffff
+ bda45d240701d94c.de7accc41543e398.2a362ce3653ee5a8.df1c2f0c5e98a0f2
+ 3c7c85ef198f0d9b.9a6840ca09f95ebd.cf08f5748d9cb486.23c51c5e93c815d4
+ f5db28bf3667f84e.283be1ab108532cb.c07a7b14b1bd5c32.0c2c37548d07c5c8
+ 771dfddb68636cfb
+VPACKUSDW_128(mem)
+ before
+ 3e64e8dd41e7c698.440d4200f914d811.65bd2a5247f31bee.58d9bb2f6d2e1a57
+ 3ecc764734a08ecc.865ed01efe22e78f.2dbb97aac950d451.f571af315d7a29a2
+ 532222065b9981c3.151acd86e21e6175.5c01a5a1b3a81b21.f28e55861f2ec7be
+ 59336905d5de5ba8.4e8c35a24193846e.ce5acf232005aa89.ab7ba89b4cd52e58
+ 7b86a4da82fb9b1c
+ after
+ 3e64e8dd41e7c698.440d4200f914d811.65bd2a5247f31bee.58d9bb2f6d2e1a57
+ 3ecc764734a08ecc.865ed01efe22e78f.2dbb97aac950d451.f571af315d7a29a2
+ 0000000000000000.0000000000000000.ffffffffffffffff.ffff00000000ffff
+ 59336905d5de5ba8.4e8c35a24193846e.ce5acf232005aa89.ab7ba89b4cd52e58
+ 7b86a4da82fb9b1c
+
+VPACKUSDW_128(reg)
+ before
+ c0f946b15d2c49b6.2cc9c52fbc7cd8a8.8d0205e0b50e8a27.5f94911a2d753db6
+ d421888a78f576d0.a8b0b4722c7eb3ee.2ec637aadd19b04c.eb796773f50392d4
+ 154a68d370e25c19.a9b6b1b942f0a9a7.8d25c96e53423288.4ed7cd1a94bc630e
+ ddc0e2f7e07d373b.0ba638f019de75ff.066bb697b3154b88.647840fc27ab6c91
+ 09293b03cadc6b88
+ after
+ 0000000000000000.0000000000000000.0000ffffffff0000.ffff000000000000
+ d421888a78f576d0.a8b0b4722c7eb3ee.2ec637aadd19b04c.eb796773f50392d4
+ 154a68d370e25c19.a9b6b1b942f0a9a7.8d25c96e53423288.4ed7cd1a94bc630e
+ ddc0e2f7e07d373b.0ba638f019de75ff.066bb697b3154b88.647840fc27ab6c91
+ 09293b03cadc6b88
+VPACKUSDW_128(mem)
+ before
+ 19b63a1d985c1a20.8acff062645445e3.aa4bc603ce55d521.f5e4fa919a1d38f7
+ 70eab935ad363684.76c2908099f2c0bc.6272d5de7c61833a.b6db92c8a3e63582
+ e993343626767be2.ffe7bcbd1ae4e573.0ee7e36e400c3c75.a59e79a86afc7dd5
+ 627b280e1f29a463.7f88728684b5efb3.8c766b9d3564bbff.1e77aa9d8dec4e9b
+ 7db32414a541e281
+ after
+ 19b63a1d985c1a20.8acff062645445e3.aa4bc603ce55d521.f5e4fa919a1d38f7
+ 70eab935ad363684.76c2908099f2c0bc.6272d5de7c61833a.b6db92c8a3e63582
+ 0000000000000000.0000000000000000.0000000000000000.ffffffff00000000
+ 627b280e1f29a463.7f88728684b5efb3.8c766b9d3564bbff.1e77aa9d8dec4e9b
+ 7db32414a541e281
+
+VPMOVZXBQ_128(reg)
+ before
+ 1e9ee07750877532.b66f10a8b25a6e36.54f2ae4573f11c29.b7ebea587775bd04
+ 5d84db342a4b455b.c13b68f0fe159585.d8716a678125a681.6b11da8c2349feaf
+ 96b112b5ce188ca8.5eabacd31d67d57c.6851a4594ddcc966.83b6b92455ef3a2d
+ 24708068d87b87c4.6b8b593b2b5be948.61dd578670a2c385.dda4020b28702da9
+ 54a8312fb8da9250
+ after
+ 1e9ee07750877532.b66f10a8b25a6e36.54f2ae4573f11c29.b7ebea587775bd04
+ 0000000000000000.0000000000000000.000000000000003a.000000000000002d
+ 96b112b5ce188ca8.5eabacd31d67d57c.6851a4594ddcc966.83b6b92455ef3a2d
+ 24708068d87b87c4.6b8b593b2b5be948.61dd578670a2c385.dda4020b28702da9
+ 54a8312fb8da9250
+VPMOVZXBQ_128(mem)
+ before
+ c38ec37b2238254d.650f21b8e5ff715c.c2a6ea1544fd8e15.1d637f598904ce8a
+ 082232db8296a4cd.b4d8f2109130871b.41cadb4e865a800e.f92d1840318d2720
+ fd30fc3bf301c9fc.6c18eede779b05ae.c3c1a8d00a7d7a60.51881fa607c90af3
+ 80839c8791845105.eb1b108e33ca27c0.2358ce89ee733937.81c08ef7a445b2b0
+ e521639fa68c5c03
+ after
+ c38ec37b2238254d.650f21b8e5ff715c.c2a6ea1544fd8e15.1d637f598904ce8a
+ 0000000000000000.0000000000000000.00000000000000ce.000000000000008a
+ fd30fc3bf301c9fc.6c18eede779b05ae.c3c1a8d00a7d7a60.51881fa607c90af3
+ 80839c8791845105.eb1b108e33ca27c0.2358ce89ee733937.81c08ef7a445b2b0
+ e521639fa68c5c03
+
+VPMOVZXBQ_128(reg)
+ before
+ daf79a0aa92b4498.6be88eac792bf815.8c2c578a624c28fe.3f5bc7644e4679be
+ ba8d2da548aca51a.9c2c4f94c6037958.aa99bc3f9faa4614.f195114d4504f621
+ e2311ada1f9dbc35.ed195a2d951792f9.a3ac3c198772baad.16d42730f0b96b8e
+ ae2d5b17cb8ac596.3b7b2a610174fd24.d1b3d485b52fc376.8be385f96a70952f
+ 2a8da894cf353030
+ after
+ daf79a0aa92b4498.6be88eac792bf815.8c2c578a624c28fe.3f5bc7644e4679be
+ 0000000000000000.0000000000000000.000000000000006b.000000000000008e
+ e2311ada1f9dbc35.ed195a2d951792f9.a3ac3c198772baad.16d42730f0b96b8e
+ ae2d5b17cb8ac596.3b7b2a610174fd24.d1b3d485b52fc376.8be385f96a70952f
+ 2a8da894cf353030
+VPMOVZXBQ_128(mem)
+ before
+ d19f0bed3c14f7be.7aceefc6e8fefce9.63203e1e27257607.92f87fedc66e9b1b
+ 5ae52af0cc1aa705.a160cf5511859cda.3fd30f4f2236bacc.40c839bf55ba7f47
+ a22b818a9c52fc30.812ef82fe2abe314.ac5f1bdf0fb3859f.396fff66ff9faba7
+ 853c8ca5c8c9b26c.758667bff8fd0a43.8791dcbc09a993ad.d738cb4d5faa5ae6
+ 77719be21166cab1
+ after
+ d19f0bed3c14f7be.7aceefc6e8fefce9.63203e1e27257607.92f87fedc66e9b1b
+ 0000000000000000.0000000000000000.000000000000009b.000000000000001b
+ a22b818a9c52fc30.812ef82fe2abe314.ac5f1bdf0fb3859f.396fff66ff9faba7
+ 853c8ca5c8c9b26c.758667bff8fd0a43.8791dcbc09a993ad.d738cb4d5faa5ae6
+ 77719be21166cab1
+
+VPMOVZXBQ_128(reg)
+ before
+ 76646a90b25f35b3.e0e6c82f6a8a84e4.d9b21773ee065014.aa35d0d12c23a022
+ 2e5e35c3de22d799.8df3b012a1a12fc5.090004b66153ef33.f217730b952e6729
+ fcabf6e8303aed0f.6930c03c861b6f3b.61ba2bf5ec6f244b.3b033f5460d5a5ef
+ 3d97ab694433b3c0.506974983802ff71.3c2d869a2ce62b09.61c5b299a824159f
+ 402847c789287566
+ after
+ 76646a90b25f35b3.e0e6c82f6a8a84e4.d9b21773ee065014.aa35d0d12c23a022
+ 0000000000000000.0000000000000000.00000000000000a5.00000000000000ef
+ fcabf6e8303aed0f.6930c03c861b6f3b.61ba2bf5ec6f244b.3b033f5460d5a5ef
+ 3d97ab694433b3c0.506974983802ff71.3c2d869a2ce62b09.61c5b299a824159f
+ 402847c789287566
+VPMOVZXBQ_128(mem)
+ before
+ b4f97ac820eb7f70.4b6e4fb3b79a6559.1e6a4912d0659d94.f8a41312bc443f19
+ 9a05c78a897cf0e8.837bde3325fa3f85.afffba966c4d03cf.f06dcdc939169d26
+ cc16abf7dee483fb.410c545328df7cf1.dff4421028c8ed4f.7fd3b02c3ee781dd
+ 26f8a1fd3e31f5d4.e16bae815fd65949.8a14606d1fe11940.0321b9a6674427e9
+ d7a4e3a252b8caf7
+ after
+ b4f97ac820eb7f70.4b6e4fb3b79a6559.1e6a4912d0659d94.f8a41312bc443f19
+ 0000000000000000.0000000000000000.000000000000003f.0000000000000019
+ cc16abf7dee483fb.410c545328df7cf1.dff4421028c8ed4f.7fd3b02c3ee781dd
+ 26f8a1fd3e31f5d4.e16bae815fd65949.8a14606d1fe11940.0321b9a6674427e9
+ d7a4e3a252b8caf7
+
+VPMOVZXWQ_128(reg)
+ before
+ 56a82a8e98cfa7b2.86792587c26f02a0.bfe5e728636a1138.8c2c8d976ea541cd
+ de798ad5d716fac7.c764b38189a8668b.37c6fbb3d328e26b.c108477b301f2123
+ c963ffe3ab18fee2.c584c7d7aceadcc0.a55ae690489a068d.05740806815b776d
+ 75b18624ae61f0ae.5ca6de754a40216c.65eda42a614fba4b.343c4e227e66fdd8
+ 2a2c95bd434b7090
+ after
+ 56a82a8e98cfa7b2.86792587c26f02a0.bfe5e728636a1138.8c2c8d976ea541cd
+ 0000000000000000.0000000000000000.000000000000815b.000000000000776d
+ c963ffe3ab18fee2.c584c7d7aceadcc0.a55ae690489a068d.05740806815b776d
+ 75b18624ae61f0ae.5ca6de754a40216c.65eda42a614fba4b.343c4e227e66fdd8
+ 2a2c95bd434b7090
+VPMOVZXWQ_128(mem)
+ before
+ c20f57c2ea168cc0.3cb119047f7d0cd8.689673487cb7f1ba.d3ca32edb7d03951
+ dab2121d92d40c95.7cadb6efb8f98e0c.c520023a605a08d7.4b3e8b46e8abc04a
+ 4de241ba5590ad3a.8ff25952f561b1f5.4e100738123521ee.2995ab9f906b8be3
+ f76960854f562bdc.d2ccfc97d33fb23f.e131ff2fad55f92d.c91b8f654a9cd6c7
+ 871c3105b3cbdca3
+ after
+ c20f57c2ea168cc0.3cb119047f7d0cd8.689673487cb7f1ba.d3ca32edb7d03951
+ 0000000000000000.0000000000000000.000000000000b7d0.0000000000003951
+ 4de241ba5590ad3a.8ff25952f561b1f5.4e100738123521ee.2995ab9f906b8be3
+ f76960854f562bdc.d2ccfc97d33fb23f.e131ff2fad55f92d.c91b8f654a9cd6c7
+ 871c3105b3cbdca3
+
+VPMOVZXWQ_128(reg)
+ before
+ bee48fe96683da23.b313eb6a9d3342a6.a2869d2ced21cd98.5951640a4ec54cbd
+ ccbea47fff510cf2.5fae5f555a32adc5.596e377be0933daa.913ab4b41092d5cd
+ 0cf86c321bc0aebd.d6053733a3602965.54cfc6f2471f3f21.67b96b1b0fc65186
+ dadce46e565cfb2f.f3e3efee93c772b1.eff446fcbf530faa.b69a032a686f7c17
+ 59a9facd369912aa
+ after
+ bee48fe96683da23.b313eb6a9d3342a6.a2869d2ced21cd98.5951640a4ec54cbd
+ 0000000000000000.0000000000000000.0000000000000fc6.0000000000005186
+ 0cf86c321bc0aebd.d6053733a3602965.54cfc6f2471f3f21.67b96b1b0fc65186
+ dadce46e565cfb2f.f3e3efee93c772b1.eff446fcbf530faa.b69a032a686f7c17
+ 59a9facd369912aa
+VPMOVZXWQ_128(mem)
+ before
+ 2eb2caf0964fce6c.91b7069f4ab230f5.94150374467543d6.862ab405e3bbe9f1
+ 0f80f17fa49d6d88.8fd5d031964c89ba.9367efb0da765900.76bd0a7950e208a1
+ dae0eb677b8fab2b.2f823d90d4b9412b.cea5308d68d5705a.19f946c4a154a967
+ 699f329237324380.cc094928a08295f4.1f9b41f90e9e4411.cc296452729d08ee
+ eb9b5e90604a61e3
+ after
+ 2eb2caf0964fce6c.91b7069f4ab230f5.94150374467543d6.862ab405e3bbe9f1
+ 0000000000000000.0000000000000000.000000000000e3bb.000000000000e9f1
+ dae0eb677b8fab2b.2f823d90d4b9412b.cea5308d68d5705a.19f946c4a154a967
+ 699f329237324380.cc094928a08295f4.1f9b41f90e9e4411.cc296452729d08ee
+ eb9b5e90604a61e3
+
+VPMOVZXWQ_128(reg)
+ before
+ d29932e807e6eff2.9a8744eef591f2b4.c4b8f1669735c1c0.64159edfe8dd9050
+ dd70dbc702fdefc6.47649c65d0b874f3.71d930b4545d013c.77dec32b119f1144
+ 686d559aed1c9c0c.4d04b6e5e4b48568.31b9028074879014.35c32dc9a5ef8318
+ cfd99ccc65ce346f.89320e594f90e040.5ea46334923eabf3.7b9057a5c1daa1f9
+ 2311bdac816a2813
+ after
+ d29932e807e6eff2.9a8744eef591f2b4.c4b8f1669735c1c0.64159edfe8dd9050
+ 0000000000000000.0000000000000000.000000000000a5ef.0000000000008318
+ 686d559aed1c9c0c.4d04b6e5e4b48568.31b9028074879014.35c32dc9a5ef8318
+ cfd99ccc65ce346f.89320e594f90e040.5ea46334923eabf3.7b9057a5c1daa1f9
+ 2311bdac816a2813
+VPMOVZXWQ_128(mem)
+ before
+ 0a12dbc8ffaed491.6e03acc805a0f19c.d5b921ac2a5942a7.55e64f3e4a0e8e86
+ 0c5f2de75aaf61a0.a13682fc6a1c103f.0e666acc931a67c8.73cbc3093a847478
+ 06c330f3ac7b8a6b.c3bd19d330d1cc03.100565a4a6df0acf.129eba01fb2b9a76
+ d20c5fda111d0c1f.32e56db9f1486294.b8628e217eb4e8ea.90ac30922b8f3c2b
+ 47422128663d9644
+ after
+ 0a12dbc8ffaed491.6e03acc805a0f19c.d5b921ac2a5942a7.55e64f3e4a0e8e86
+ 0000000000000000.0000000000000000.0000000000004a0e.0000000000008e86
+ 06c330f3ac7b8a6b.c3bd19d330d1cc03.100565a4a6df0acf.129eba01fb2b9a76
+ d20c5fda111d0c1f.32e56db9f1486294.b8628e217eb4e8ea.90ac30922b8f3c2b
+ 47422128663d9644
+
+VPMOVZXDQ_128(reg)
+ before
+ 94aa8a2f47c0e36d.4d043687a6a2a3e8.49fa7b1a4c0f0ea0.e049622d37a6bd42
+ d33065136aa46051.537831e686150af1.64483d63dab10cd1.65865bb5eec14506
+ 6122b0406c76499d.c034cde3cd82ff67.de1bb1fe3abb97d3.23e4f7a6bf0f3b60
+ 98cb6623e8c1d9fc.7004846a99f53c75.15bfd25805b8ec53.f630b1eac59e5c7c
+ ba37066f1c796488
+ after
+ 94aa8a2f47c0e36d.4d043687a6a2a3e8.49fa7b1a4c0f0ea0.e049622d37a6bd42
+ 0000000000000000.0000000000000000.0000000023e4f7a6.00000000bf0f3b60
+ 6122b0406c76499d.c034cde3cd82ff67.de1bb1fe3abb97d3.23e4f7a6bf0f3b60
+ 98cb6623e8c1d9fc.7004846a99f53c75.15bfd25805b8ec53.f630b1eac59e5c7c
+ ba37066f1c796488
+VPMOVZXDQ_128(mem)
+ before
+ 4bc3701fe1ad0fad.d57684277b114e1b.3fb3d467037b7d48.647f9dded93447fd
+ 85a06de82f45181a.747004b7c1f3e2a6.090f38c62920800c.26a90cfa52bbe47c
+ 449c78b5234d3cf9.d105e44154f2d148.aae22d7327eeffec.b9871d1a0bdafe7d
+ 64820d72d8d23676.48811f30d39b59ae.fef92d5b18f3b615.7866cba9a01cd2ac
+ be921213ae0e9cb4
+ after
+ 4bc3701fe1ad0fad.d57684277b114e1b.3fb3d467037b7d48.647f9dded93447fd
+ 0000000000000000.0000000000000000.00000000647f9dde.00000000d93447fd
+ 449c78b5234d3cf9.d105e44154f2d148.aae22d7327eeffec.b9871d1a0bdafe7d
+ 64820d72d8d23676.48811f30d39b59ae.fef92d5b18f3b615.7866cba9a01cd2ac
+ be921213ae0e9cb4
+
+VPMOVZXDQ_128(reg)
+ before
+ e956eec4d13b9742.c11da90b6bdfc4bf.3530b2f0d778b483.e120b668183a63b2
+ 53005c28a42f0001.373ac66cf780a0fd.f45e97edff171e74.2f23438844d0c0f0
+ 59da57abc377139e.a1a5e28299c2875f.e156cc93e404d52d.c4cd51a6b8c08afb
+ 5832dbb9cb9e0cc4.dd2a78376cb0340f.58664c4e24ca1359.7bec5aae8f167dfe
+ 324adc8ce5df5426
+ after
+ e956eec4d13b9742.c11da90b6bdfc4bf.3530b2f0d778b483.e120b668183a63b2
+ 0000000000000000.0000000000000000.00000000c4cd51a6.00000000b8c08afb
+ 59da57abc377139e.a1a5e28299c2875f.e156cc93e404d52d.c4cd51a6b8c08afb
+ 5832dbb9cb9e0cc4.dd2a78376cb0340f.58664c4e24ca1359.7bec5aae8f167dfe
+ 324adc8ce5df5426
+VPMOVZXDQ_128(mem)
+ before
+ c4b4522cd726cc9e.aa52e4bf58302620.c69504788d566439.b5d8138a5bf515a5
+ 0df6387a80f8a193.ad876e2704ba9e5e.38b1033217c1d30a.54f91db4241117bc
+ e8dc0a62fd5f8f31.bb1c765f6ec7b029.0e4cf05026fc3dae.901567361cab544b
+ 333245d0696951a3.315ff7d12fe3972e.263047bdd7135d50.c777eb7ede4e09fe
+ 546da7f706877280
+ after
+ c4b4522cd726cc9e.aa52e4bf58302620.c69504788d566439.b5d8138a5bf515a5
+ 0000000000000000.0000000000000000.00000000b5d8138a.000000005bf515a5
+ e8dc0a62fd5f8f31.bb1c765f6ec7b029.0e4cf05026fc3dae.901567361cab544b
+ 333245d0696951a3.315ff7d12fe3972e.263047bdd7135d50.c777eb7ede4e09fe
+ 546da7f706877280
+
+VPMOVZXDQ_128(reg)
+ before
+ 9341970c31e1cb7e.c9c364b0e122a415.6b9aedebe69b9118.5b2a84674613f11d
+ df40b52bfbe84fa3.855de3ef809444b5.c61b54182c7ad795.880623398e07b241
+ 96b6ffbffe283b9c.45ca3e7763cdecad.9c2c29c49f0ca84e.8b90a11fcbfb5fe7
+ 13ef7034d92ecb14.e3d7f136a5d95929.4a1a675bdbde3ef1.3e9479051afcb23b
+ 7fdd27d89615686b
+ after
+ 9341970c31e1cb7e.c9c364b0e122a415.6b9aedebe69b9118.5b2a84674613f11d
+ 0000000000000000.0000000000000000.000000008b90a11f.00000000cbfb5fe7
+ 96b6ffbffe283b9c.45ca3e7763cdecad.9c2c29c49f0ca84e.8b90a11fcbfb5fe7
+ 13ef7034d92ecb14.e3d7f136a5d95929.4a1a675bdbde3ef1.3e9479051afcb23b
+ 7fdd27d89615686b
+VPMOVZXDQ_128(mem)
+ before
+ 283827825c533da1.b13704f626863ab8.3d50791762c34756.2c310a497b7bd72a
+ 1772f6f087c0ec09.cedab77281bac534.2d015106b7977260.9ebc0efa1c6faca5
+ 26550e0f346b33d0.c42386128758a833.91b5f5efc0619572.fc096fda5947fc0d
+ 33adedc97e5dcb22.f15f6b43d3eb1e62.433ae1be982e6db9.a2622a56ce8e010e
+ ec143ad818d1f855
+ after
+ 283827825c533da1.b13704f626863ab8.3d50791762c34756.2c310a497b7bd72a
+ 0000000000000000.0000000000000000.000000002c310a49.000000007b7bd72a
+ 26550e0f346b33d0.c42386128758a833.91b5f5efc0619572.fc096fda5947fc0d
+ 33adedc97e5dcb22.f15f6b43d3eb1e62.433ae1be982e6db9.a2622a56ce8e010e
+ ec143ad818d1f855
+
+VMPSADBW_128_0x0(reg)
+ before
+ 366b9bced39a1d8e.18480e0c82a4732a.afda64720200656d.205a925f5b09b660
+ dcb349a29a78ab64.b2f1eec35b4be515.5ce06d09af22b7ff.05e283be26ff2b94
+ 3a3841c209f4df84.dd7307da265fde0e.52bd807676dd51c5.cc9e30c7151b8981
+ ac457d99bd9cf59a.769bd73dfeea1a42.efbd9b24f4be6e6a.525a156743698c52
+ 73e1ae88ccf5f034
+ after
+ 0000000000000000.0000000000000000.019b026b015b011a.01c501f201800166
+ dcb349a29a78ab64.b2f1eec35b4be515.5ce06d09af22b7ff.05e283be26ff2b94
+ 3a3841c209f4df84.dd7307da265fde0e.52bd807676dd51c5.cc9e30c7151b8981
+ ac457d99bd9cf59a.769bd73dfeea1a42.efbd9b24f4be6e6a.525a156743698c52
+ 73e1ae88ccf5f034
+VMPSADBW_128_0x0(mem)
+ before
+ 0c017818cdcc7053.8e28fb9351fb2851.5735d9d800fb55dd.8d2bb87fc5504b9b
+ f784ee0261f9c9da.3c2bb61c629db656.5d0d8997479b4a0a.8955d5f3841f2403
+ 11378c31a589b7f5.119baba08b0fd954.64ef6466efd8b6f6.4085eeecceb8354f
+ 36e6ce93b487f5d1.6bc4d48b69ddcdf8.48a7e53115bd54cd.0c08fdd63ea6b92b
+ 4a2a001d7075ed42
+ after
+ 0c017818cdcc7053.8e28fb9351fb2851.5735d9d800fb55dd.8d2bb87fc5504b9b
+ f784ee0261f9c9da.3c2bb61c629db656.5d0d8997479b4a0a.8955d5f3841f2403
+ 0000000000000000.0000000000000000.0083014501380123.01b4016801050131
+ 36e6ce93b487f5d1.6bc4d48b69ddcdf8.48a7e53115bd54cd.0c08fdd63ea6b92b
+ 4a2a001d7075ed42
+
+VMPSADBW_128_0x0(reg)
+ before
+ 5636f22e01b20d41.425d3113abff419a.a5f22f4a9791d0ee.e60087e5d557e2ba
+ 8c7acf738ce854d3.11682f9da5fe557c.1a71b747b2b91ce1.18c7c96c49b11ae9
+ 4940935aaea3ffa5.7fd3461dbe8eeda2.288c69f055e0ee7e.bbc924b490d7b987
+ e7d63b4d03704a63.6869f18013bec738.2a903faf1c938170.abd015a8c4d67ac0
+ c4a8193301b91ac0
+ after
+ 0000000000000000.0000000000000000.017b015f016000b3.00d0013e0127016e
+ 8c7acf738ce854d3.11682f9da5fe557c.1a71b747b2b91ce1.18c7c96c49b11ae9
+ 4940935aaea3ffa5.7fd3461dbe8eeda2.288c69f055e0ee7e.bbc924b490d7b987
+ e7d63b4d03704a63.6869f18013bec738.2a903faf1c938170.abd015a8c4d67ac0
+ c4a8193301b91ac0
+VMPSADBW_128_0x0(mem)
+ before
+ e21fab43648c55b1.c386c2ba25da71b8.a8f7adb0c0979d6b.7bca37f2a45d1264
+ e00047c3085be7c2.399d240cb36daf51.1b49f49ae0272b67.79844c2489cadd05
+ 9c166a9f0a338b1d.a5665daf46b641d9.9d2b442b907a2f58.7e0a7ab166661e00
+ f12e8fc38520feef.632f6a0f7d4063fd.0a69184eea9a6369.e8aabd05d7be1101
+ 11af128c795ef1b3
+ after
+ e21fab43648c55b1.c386c2ba25da71b8.a8f7adb0c0979d6b.7bca37f2a45d1264
+ e00047c3085be7c2.399d240cb36daf51.1b49f49ae0272b67.79844c2489cadd05
+ 0000000000000000.0000000000000000.0119010a00e300cc.0068016e01dd01b2
+ f12e8fc38520feef.632f6a0f7d4063fd.0a69184eea9a6369.e8aabd05d7be1101
+ 11af128c795ef1b3
+
+VMPSADBW_128_0x0(reg)
+ before
+ 576474b2e8d0fbc3.bb14311c962cfc63.cf434598f1985169.3ecfecee0d9584c6
+ 1416dfe3bfa26add.d694cf94586541a6.45edecb6404946c8.15283df913774e9c
+ a6114f8b9a607bac.1e7ae219e7d788e4.217a5ad606df7fc7.6a42865a184a7c17
+ 67a1c01716946adc.6e91e795608c8e48.be368c62dee63711.1be743fd391ccb62
+ 03e4f0ce91f9f7aa
+ after
+ 0000000000000000.0000000000000000.00830124015f0146.009e019d015400e5
+ 1416dfe3bfa26add.d694cf94586541a6.45edecb6404946c8.15283df913774e9c
+ a6114f8b9a607bac.1e7ae219e7d788e4.217a5ad606df7fc7.6a42865a184a7c17
+ 67a1c01716946adc.6e91e795608c8e48.be368c62dee63711.1be743fd391ccb62
+ 03e4f0ce91f9f7aa
+VMPSADBW_128_0x0(mem)
+ before
+ fd0509b93debbc1b.b4122ff1cecc731b.a4a75bf6df920fff.7a6d7cc865ebac53
+ e7150bab5800d5e0.e9b097875f94d213.9b86b9277ff5c634.b06a287236791839
+ 9ce2708eff44ff26.63c6f4446476c270.2efb7d135cc07014.bc7b8bceed1db86e
+ f736b6504dc2f618.7ca142947a0080df.3bd224a893ffc9ca.faeaa1472762c79f
+ c50567487fd48377
+ after
+ fd0509b93debbc1b.b4122ff1cecc731b.a4a75bf6df920fff.7a6d7cc865ebac53
+ e7150bab5800d5e0.e9b097875f94d213.9b86b9277ff5c634.b06a287236791839
+ 0000000000000000.0000000000000000.018a013300d9016f.011f01520130014f
+ f736b6504dc2f618.7ca142947a0080df.3bd224a893ffc9ca.faeaa1472762c79f
+ c50567487fd48377
+
+VMPSADBW_128_0x1(reg)
+ before
+ 7b16d73f92ff26a3.d6de59db5f8675e3.918e7ee33cbe470c.9cd728d140be8d84
+ 776aef98fc70ecce.13a6d31d509c39b2.fed6a39d463a55a2.2fd6077a7e0a776b
+ 144caabd58b213a5.8c5aa2003d11feb2.1fc8ad2e3602e44e.ce9a3c9069ee44ad
+ b00a051b4252d5d4.1bc6417241f0800f.50af9802a5a231bb.57f043fd1e76b076
+ a4a599aeb8af76f2
+ after
+ 0000000000000000.0000000000000000.01a000d401ba0126.00eb01af00bb0140
+ 776aef98fc70ecce.13a6d31d509c39b2.fed6a39d463a55a2.2fd6077a7e0a776b
+ 144caabd58b213a5.8c5aa2003d11feb2.1fc8ad2e3602e44e.ce9a3c9069ee44ad
+ b00a051b4252d5d4.1bc6417241f0800f.50af9802a5a231bb.57f043fd1e76b076
+ a4a599aeb8af76f2
+VMPSADBW_128_0x1(mem)
+ before
+ 9383b99054a4534c.a5eefa1e57db6f06.9eb62c5e78457af4.edd6608531a57796
+ fe561f8d0d6203b1.5146873332d91ce8.eff5dfb0ff1da98e.538b02247697f38b
+ c2ec479300f4424c.0e5ca7c470d91a26.eb50d754f283c909.dc1879490f04e145
+ bc10ad8d4866cb4a.3a7d563fac66a36b.6f938e376b849590.e4cac16298797d71
+ c9edd6d9ae8102ba
+ after
+ 9383b99054a4534c.a5eefa1e57db6f06.9eb62c5e78457af4.edd6608531a57796
+ fe561f8d0d6203b1.5146873332d91ce8.eff5dfb0ff1da98e.538b02247697f38b
+ 0000000000000000.0000000000000000.015d009f019001a4.018101c501ce014f
+ bc10ad8d4866cb4a.3a7d563fac66a36b.6f938e376b849590.e4cac16298797d71
+ c9edd6d9ae8102ba
+
+VMPSADBW_128_0x1(reg)
+ before
+ e6cdb51ceca8adcd.c68dce6702c45bd6.2ff4910f820cf363.558a8243892bca4f
+ 97b55896ef7bba55.bd30250d491bae1d.4a0f529f8f5848bc.7a012f6566842474
+ 38f3bdb352856500.7ec52e6b39767f4b.e819975d6fd5dc20.bbc40f8a1e9b5f28
+ 25d1e0dfb253e977.e318656defe28b8b.635d5bb4bd0fec3b.f29ea09cce7d369a
+ fc5d5c89913566f4
+ after
+ 0000000000000000.0000000000000000.019c016f00b40149.01c90148018f00c0
+ 97b55896ef7bba55.bd30250d491bae1d.4a0f529f8f5848bc.7a012f6566842474
+ 38f3bdb352856500.7ec52e6b39767f4b.e819975d6fd5dc20.bbc40f8a1e9b5f28
+ 25d1e0dfb253e977.e318656defe28b8b.635d5bb4bd0fec3b.f29ea09cce7d369a
+ fc5d5c89913566f4
+VMPSADBW_128_0x1(mem)
+ before
+ b5cbc23c84d0ab62.ba9cbb86aa708369.c9f546ff876a8e0a.18289a101693b3ba
+ f9b54ba1c259c012.52a04c14d7686e80.0c284e0d1c1a44f3.64c651de15ec6f49
+ a4e774a468dc632d.4b298df6d4c7e868.887cf884cafe6873.a1837b8856a65a93
+ 922dba3191664ee2.00827c963e1a2bce.19bec04eae23b7b6.2cab147b764eb045
+ 61891824106faf0a
+ after
+ b5cbc23c84d0ab62.ba9cbb86aa708369.c9f546ff876a8e0a.18289a101693b3ba
+ f9b54ba1c259c012.52a04c14d7686e80.0c284e0d1c1a44f3.64c651de15ec6f49
+ 0000000000000000.0000000000000000.00cb01e301840201.01200250018a012b
+ 922dba3191664ee2.00827c963e1a2bce.19bec04eae23b7b6.2cab147b764eb045
+ 61891824106faf0a
+
+VMPSADBW_128_0x1(reg)
+ before
+ 9c6b83edc195918f.9f5298345a023d5b.ccf91562b0ed745e.9bbb2259e495ede7
+ 3a9b5244244d9380.a7248a99debceec4.0dd852c4c7cafec3.ea3d9b90865ec633
+ 95668094d622f188.866d0d4d39a11b4b.1e6c312a1e3f07aa.e210a6deb38cfdc5
+ 0a18094873a0e654.18fa9b3a88bb8019.5a01adff51d7c9bf.5f02bf31852a4fca
+ 3dde62741845776e
+ after
+ 0000000000000000.0000000000000000.012f01b401a5008e.019e016701280175
+ 3a9b5244244d9380.a7248a99debceec4.0dd852c4c7cafec3.ea3d9b90865ec633
+ 95668094d622f188.866d0d4d39a11b4b.1e6c312a1e3f07aa.e210a6deb38cfdc5
+ 0a18094873a0e654.18fa9b3a88bb8019.5a01adff51d7c9bf.5f02bf31852a4fca
+ 3dde62741845776e
+VMPSADBW_128_0x1(mem)
+ before
+ 586f0b9388e833dc.f5fde9ce9554af8f.3997b24ee719db5d.1fe3c2aefd1f80ad
+ 8c82377bf31f3d41.b2601c91dac988e6.c510cd7371c4e641.c75e6ca5bea26a21
+ b5e3611672f752c8.9d8f9ffdde8cac05.9830689742ca5ef1.b0bda8502fecc1c6
+ ae5e0551237b2d9e.12d46d7f3c275997.8ec500a57737ff9a.344e7119ec8ac249
+ b05bc36d9207a855
+ after
+ 586f0b9388e833dc.f5fde9ce9554af8f.3997b24ee719db5d.1fe3c2aefd1f80ad
+ 8c82377bf31f3d41.b2601c91dac988e6.c510cd7371c4e641.c75e6ca5bea26a21
+ 0000000000000000.0000000000000000.014201be00e4018c.00e3009b010f01c5
+ ae5e0551237b2d9e.12d46d7f3c275997.8ec500a57737ff9a.344e7119ec8ac249
+ b05bc36d9207a855
+
+VMPSADBW_128_0x2(reg)
+ before
+ 81319ab8bcefb197.55bf9f1922b78bef.6c7c82819129c949.829910892b158468
+ 011cf26707cf17bb.85d1ac588ab828e6.09d3da70781b38c6.5279132f7b72aa87
+ 8d68c8e40e32166c.1962a6fc7889c0af.442572b98e8be4bb.d9318883825a2d21
+ 8260179d6ea4ec57.ef3c0bf007360e78.79be45c66e0407d4.f28de8715dd8c965
+ 7b59b1e527f8397d
+ after
+ 0000000000000000.0000000000000000.014d0165018401ab.0182018900f2009a
+ 011cf26707cf17bb.85d1ac588ab828e6.09d3da70781b38c6.5279132f7b72aa87
+ 8d68c8e40e32166c.1962a6fc7889c0af.442572b98e8be4bb.d9318883825a2d21
+ 8260179d6ea4ec57.ef3c0bf007360e78.79be45c66e0407d4.f28de8715dd8c965
+ 7b59b1e527f8397d
+VMPSADBW_128_0x2(mem)
+ before
+ 4f605dccfdc63a96.3a52dbfdc2b2d327.e22c571f53ccd06b.04e94f05b413debc
+ 49706a10fa4f88db.12881170a7e70889.cdfe04777956bfb4.40f48ce1fd42a41f
+ 4753549f3b9ede79.664fb361b8cfc729.8e7e90e395e19a80.8b29f8c6e42096ab
+ 23d69563dbbff99b.93f3bf3e92f74bb2.ff78754fc1771bfb.40d590200636f00a
+ ba444f5bff12eee8
+ after
+ 4f605dccfdc63a96.3a52dbfdc2b2d327.e22c571f53ccd06b.04e94f05b413debc
+ 49706a10fa4f88db.12881170a7e70889.cdfe04777956bfb4.40f48ce1fd42a41f
+ 0000000000000000.0000000000000000.0057019d013200f5.018400a4018601ac
+ 23d69563dbbff99b.93f3bf3e92f74bb2.ff78754fc1771bfb.40d590200636f00a
+ ba444f5bff12eee8
+
+VMPSADBW_128_0x2(reg)
+ before
+ 57c231e3693fcbf2.bbc5ab4af7bf956f.f3c03073d0ead1d1.feb732a81c27ff50
+ 729a3224e34ac5d4.e9ec113faaa96e1e.e302026a0f349531.650840d8c0fa02ac
+ 661a4f8b07be1539.8b16432e108a3fd7.bf043190ea62d27f.12381cccc9fedf3b
+ 918c83827127face.7b11bd03466cc5c3.e314ba51fdffc567.df114371543e5428
+ aa6030b17cc61a9f
+ after
+ 0000000000000000.0000000000000000.01a4016a01c501ca.014b01ad011501bf
+ 729a3224e34ac5d4.e9ec113faaa96e1e.e302026a0f349531.650840d8c0fa02ac
+ 661a4f8b07be1539.8b16432e108a3fd7.bf043190ea62d27f.12381cccc9fedf3b
+ 918c83827127face.7b11bd03466cc5c3.e314ba51fdffc567.df114371543e5428
+ aa6030b17cc61a9f
+VMPSADBW_128_0x2(mem)
+ before
+ 4df05f7a5ea3f0ce.4d3dca77bd12ae3f.96a7fcaa685dbc11.ab7c981ae597aa94
+ a58f4cb715e090de.f77920d4890a6e37.b9a57a0f9169dfeb.7389c7553db7bdb3
+ 8f077454bd8ab7fe.ec8c81076e9b7662.bed7b51fdd9beb7e.97874370a2ea396f
+ e525523d73ac2158.86c1ea7b0a52016e.820928c469ff9cf5.73c109d6b0bd5b75
+ 628514f302bb5f71
+ after
+ 4df05f7a5ea3f0ce.4d3dca77bd12ae3f.96a7fcaa685dbc11.ab7c981ae597aa94
+ a58f4cb715e090de.f77920d4890a6e37.b9a57a0f9169dfeb.7389c7553db7bdb3
+ 0000000000000000.0000000000000000.011401c601820086.011e018c00e40128
+ e525523d73ac2158.86c1ea7b0a52016e.820928c469ff9cf5.73c109d6b0bd5b75
+ 628514f302bb5f71
+
+VMPSADBW_128_0x2(reg)
+ before
+ c21d60333470810e.84b5625e53528a19.2366569cf9ba4d05.e20650eb50a2ae7d
+ eed7e902e368fcf9.488320a37888ad6c.1dc5c1d6d65f93d3.b89ca881af8edc41
+ 42fdabccaa300ddd.0d5b09f8ff5b477e.d12b27953dce1285.e195ab71a1d2e36e
+ 1adca3fd2653f067.b009974903d7137a.9ce48545cb9204c7.39bed7a743777f30
+ 9ce4a80eb08b6bb2
+ after
+ 0000000000000000.0000000000000000.0151011801590147.011e015e013601c0
+ eed7e902e368fcf9.488320a37888ad6c.1dc5c1d6d65f93d3.b89ca881af8edc41
+ 42fdabccaa300ddd.0d5b09f8ff5b477e.d12b27953dce1285.e195ab71a1d2e36e
+ 1adca3fd2653f067.b009974903d7137a.9ce48545cb9204c7.39bed7a743777f30
+ 9ce4a80eb08b6bb2
+VMPSADBW_128_0x2(mem)
+ before
+ e6d0989405196521.d1c0cc01f25ee043.0b584883a006cf8d.d83cd5521c37a644
+ f35125245d2e27a8.c5f42245aadc1a1c.fb169790f3f635e3.e27f1528cb4a34a9
+ 9f32caabd5d56d74.51c6a133ec59da9f.5c0d015e17b202a7.16f940347456eaa1
+ c63e0313881af5b1.d080453951615c77.0a0a00d82947f106.d0f553e1b4e703d9
+ 6cc0489a268abcfd
+ after
+ e6d0989405196521.d1c0cc01f25ee043.0b584883a006cf8d.d83cd5521c37a644
+ f35125245d2e27a8.c5f42245aadc1a1c.fb169790f3f635e3.e27f1528cb4a34a9
+ 0000000000000000.0000000000000000.00ee016901e701da.011500f4021b0126
+ c63e0313881af5b1.d080453951615c77.0a0a00d82947f106.d0f553e1b4e703d9
+ 6cc0489a268abcfd
+
+VMPSADBW_128_0x3(reg)
+ before
+ 46a61dcd67ca50b8.44424c49920a798a.a06f0bc27781db51.e1d812ea44c0bf2b
+ baf3cde51233fdb7.f50a223a10b0b52c.1bdfee39fa4594d8.bd45b27f85292843
+ 24f3544ec452fda5.b56200d01e1867c2.9f1cea0c7537c3b9.7a1c5c85078fe879
+ e0f2af7418b28d2f.601662f9d74f4979.8672fca684e5a3a0.f3288de7e7fdbafb
+ 0636bf92407f5bf2
+ after
+ 0000000000000000.0000000000000000.0195012d022500f2.01d400f801660120
+ baf3cde51233fdb7.f50a223a10b0b52c.1bdfee39fa4594d8.bd45b27f85292843
+ 24f3544ec452fda5.b56200d01e1867c2.9f1cea0c7537c3b9.7a1c5c85078fe879
+ e0f2af7418b28d2f.601662f9d74f4979.8672fca684e5a3a0.f3288de7e7fdbafb
+ 0636bf92407f5bf2
+VMPSADBW_128_0x3(mem)
+ before
+ 8e1270702f22878d.4a3bd9c3abe0e801.d2f2c4a05760187d.2e2c1e73c4da7138
+ 67881b6ecff1faf6.be1bcda718664bc6.e7c1a3b0bb5790f9.f1984ee0d1a3692e
+ 6d643d793df86f59.98df8a8cfcd3f22b.7a5179171f416c19.2d00875745cbc72e
+ 7b71507b9444a3e3.34d109dff2b019db.696cc4c09d29690b.3cb1c545bfdec6e3
+ 7bf70517d969a3f9
+ after
+ 8e1270702f22878d.4a3bd9c3abe0e801.d2f2c4a05760187d.2e2c1e73c4da7138
+ 67881b6ecff1faf6.be1bcda718664bc6.e7c1a3b0bb5790f9.f1984ee0d1a3692e
+ 0000000000000000.0000000000000000.0163007e00a6012f.012b00a60087011d
+ 7b71507b9444a3e3.34d109dff2b019db.696cc4c09d29690b.3cb1c545bfdec6e3
+ 7bf70517d969a3f9
+
+VMPSADBW_128_0x3(reg)
+ before
+ 471e41372ff79a1e.6f7dd262f0e052c0.ee3d480a968bfb83.8fdfff97541b43f9
+ fa7177135e14e6fb.24523e196ed8371b.2271417b85efd5cf.c776a7895d24b60f
+ f13ea216014dc43f.75bd108c2a390f21.2bb8f29d5b68e36a.effc3680d74f7d7a
+ 88cfbfabb52d7094.408ac4a63f0e96fe.675d57dbb3836100.e23f2a69dba85566
+ 7b09fe31883cfafe
+ after
+ 0000000000000000.0000000000000000.012e01130139013d.010501b901a00190
+ fa7177135e14e6fb.24523e196ed8371b.2271417b85efd5cf.c776a7895d24b60f
+ f13ea216014dc43f.75bd108c2a390f21.2bb8f29d5b68e36a.effc3680d74f7d7a
+ 88cfbfabb52d7094.408ac4a63f0e96fe.675d57dbb3836100.e23f2a69dba85566
+ 7b09fe31883cfafe
+VMPSADBW_128_0x3(mem)
+ before
+ 98272ec2f716276f.1c71c840154026a7.5f85d755c96387dd.31ad6aa329cc8a3f
+ 1365370a464299e5.0770bb40bd132123.b07ac485e545a0eb.e5f429605acd9bd1
+ ca8f94f491cd0c8b.a61893174a319eb5.0e340720aebf9b53.de7e8f7ee214d062
+ 9771c06cf3c23c8d.55b54c325827d908.54801c1341de3442.7a9798695b2c649f
+ 138a408e64a29434
+ after
+ 98272ec2f716276f.1c71c840154026a7.5f85d755c96387dd.31ad6aa329cc8a3f
+ 1365370a464299e5.0770bb40bd132123.b07ac485e545a0eb.e5f429605acd9bd1
+ 0000000000000000.0000000000000000.00d90154013501ae.016d0150007c0105
+ 9771c06cf3c23c8d.55b54c325827d908.54801c1341de3442.7a9798695b2c649f
+ 138a408e64a29434
+
+VMPSADBW_128_0x3(reg)
+ before
+ 07a5835796019ccc.58d73a5d882ee419.7092e3fb827f0dc9.5f2b804abaac29e3
+ b0325e3190d5b814.e78c7bb56d1bc159.53fc52df64c778a4.0cffadb233383463
+ 6c7ecc89ebab23b8.225d0060be988f79.5a40974b9b8b5444.35c92136cb8b12ee
+ 95d5c9c9460e1a63.e317464896ae09a6.e1a8ada9c356dd56.b85457c19bb37faf
+ 6f6ecc41c1bb36d3
+ after
+ 0000000000000000.0000000000000000.00f101c10148018a.0145013c00db00aa
+ b0325e3190d5b814.e78c7bb56d1bc159.53fc52df64c778a4.0cffadb233383463
+ 6c7ecc89ebab23b8.225d0060be988f79.5a40974b9b8b5444.35c92136cb8b12ee
+ 95d5c9c9460e1a63.e317464896ae09a6.e1a8ada9c356dd56.b85457c19bb37faf
+ 6f6ecc41c1bb36d3
+VMPSADBW_128_0x3(mem)
+ before
+ 37e1faa159b0f486.8983525f3a8ad9c1.0784c85a116bec0c.4480906777b45185
+ ec7a5fcd7e9c75f3.a2d461b665ab9b80.6a7002834cdaf4d6.df163df05331ea7e
+ 6b0576b14d8e7446.3d13f43a63fe9d4a.e9a971ad6208dd31.0eb5afb0f45ae5ec
+ 8e4ebc39e18faeac.b78d0657cf0f1bcb.5ef98fc670006248.2da8e213f5ba7d7d
+ 973cd285f3deefda
+ after
+ 37e1faa159b0f486.8983525f3a8ad9c1.0784c85a116bec0c.4480906777b45185
+ ec7a5fcd7e9c75f3.a2d461b665ab9b80.6a7002834cdaf4d6.df163df05331ea7e
+ 0000000000000000.0000000000000000.01d6019a01f90267.00850140024100e5
+ 8e4ebc39e18faeac.b78d0657cf0f1bcb.5ef98fc670006248.2da8e213f5ba7d7d
+ 973cd285f3deefda
+
+VMPSADBW_128_0x4(reg)
+ before
+ aabe7b72895177b2.3221ab5156addf51.6a8f9479456851b0.a62edab892ce4048
+ c178da46549f51af.334ac1e6c9f3c361.b363980c62977aa5.9d12cd71e27e335d
+ 38b6ea6def54b87d.6d9479e2566e1507.ef56107cc228d355.1f72e5dc7e1df6b2
+ 6ac6a754f7fde9c9.bccd4f321829926f.78b3f73600a6986d.081a9ce582b64774
+ 34d670780956e0ce
+ after
+ 0000000000000000.0000000000000000.01d000da014e011f.00dc018501a60094
+ c178da46549f51af.334ac1e6c9f3c361.b363980c62977aa5.9d12cd71e27e335d
+ 38b6ea6def54b87d.6d9479e2566e1507.ef56107cc228d355.1f72e5dc7e1df6b2
+ 6ac6a754f7fde9c9.bccd4f321829926f.78b3f73600a6986d.081a9ce582b64774
+ 34d670780956e0ce
+VMPSADBW_128_0x4(mem)
+ before
+ 7f71dc8130087ded.b5f20d650725203f.fcbfbfc32b30f6c6.abc849a4b89d0498
+ c5b95cec12d8dcfd.7488180ebc59998a.09374680ac90fd38.e4df023487995583
+ e2786ca6ccd3b729.02d2c5b9b1248f57.bf015e55b65362f1.7f451f500827c5da
+ b27b89997904ca9e.bd1d0fd482123f52.fae8852e6688e21c.d8479b66d8d29048
+ 4b2e72e19226f47a
+ after
+ 7f71dc8130087ded.b5f20d650725203f.fcbfbfc32b30f6c6.abc849a4b89d0498
+ c5b95cec12d8dcfd.7488180ebc59998a.09374680ac90fd38.e4df023487995583
+ 0000000000000000.0000000000000000.0168013f01380172.010801d1023800d4
+ b27b89997904ca9e.bd1d0fd482123f52.fae8852e6688e21c.d8479b66d8d29048
+ 4b2e72e19226f47a
+
+VMPSADBW_128_0x4(reg)
+ before
+ 3449a02dd3b02b1b.118e2eb33577d387.ffb5f2caccb0e526.96ba37f6d73838e5
+ efe322b636fb71d8.db7dd7de1d398c11.26e56b072b89bc7f.6f41ee9c26712279
+ d847f2e85893045d.ec1300084c55b268.8cfb74f73a29010b.614a28096e3f5a04
+ 4bc30e2fd4051e55.201e261cdfd701b7.8f410b06951cf074.48a1602accac9db1
+ ff1212eb5bc6a6ad
+ after
+ 0000000000000000.0000000000000000.011d00ef0162016a.012800e00144012f
+ efe322b636fb71d8.db7dd7de1d398c11.26e56b072b89bc7f.6f41ee9c26712279
+ d847f2e85893045d.ec1300084c55b268.8cfb74f73a29010b.614a28096e3f5a04
+ 4bc30e2fd4051e55.201e261cdfd701b7.8f410b06951cf074.48a1602accac9db1
+ ff1212eb5bc6a6ad
+VMPSADBW_128_0x4(mem)
+ before
+ 6469ba3937993224.a4a171f847dcfc6d.5268c306f2cc342b.89052ba1d9efc566
+ 5272d4fe7e2ffd41.3f2e18ad4ca5da50.60be55b2a03f08ef.d791d032a12ebb8e
+ a5f8dd284996c331.78b6fdbc7febf3ab.25ec570c053c3930.d632f7268a630f98
+ 38c850a2b6da3f1f.aa841e8f7d3a842a.7dbe46003ed08319.e0339aea2f1cfd2f
+ 52e2b7e92de5c000
+ after
+ 6469ba3937993224.a4a171f847dcfc6d.5268c306f2cc342b.89052ba1d9efc566
+ 5272d4fe7e2ffd41.3f2e18ad4ca5da50.60be55b2a03f08ef.d791d032a12ebb8e
+ 0000000000000000.0000000000000000.0102010d015a022f.021c010e00cc009f
+ 38c850a2b6da3f1f.aa841e8f7d3a842a.7dbe46003ed08319.e0339aea2f1cfd2f
+ 52e2b7e92de5c000
+
+VMPSADBW_128_0x4(reg)
+ before
+ 8989498e1f4896b6.e9aea958e1062f38.33e67694e21ec978.43009c7a6606a1d8
+ df764d47a2d3b8fe.92766536e4264ca8.6e2601364924fe41.557dd7679aea5096
+ b1f3bd7f51126584.11ecfe28de46559a.b791bce04ed75e33.8d0372b1f5894c82
+ 5b4d97a2c990d7f3.41dcf21ae973043a.6973a1008ec426f8.c95ce94693ee50c5
+ e355b9109126198e
+ after
+ 0000000000000000.0000000000000000.01a601a801a30204.017e005f016e0152
+ df764d47a2d3b8fe.92766536e4264ca8.6e2601364924fe41.557dd7679aea5096
+ b1f3bd7f51126584.11ecfe28de46559a.b791bce04ed75e33.8d0372b1f5894c82
+ 5b4d97a2c990d7f3.41dcf21ae973043a.6973a1008ec426f8.c95ce94693ee50c5
+ e355b9109126198e
+VMPSADBW_128_0x4(mem)
+ before
+ b9ba5cfd0b3b6307.39d0d61ca5d94bf8.fd11bcf821b816b6.e218ae02a476913c
+ 255750f81c3bea5d.a7c776598179fd3e.2359d9aea3214738.7dccde502d79ddac
+ 05f710ede13269bb.018074c6fafd2972.8d7ec3298abb52ec.95db2e57c55a44f4
+ 336819c8752b9d4e.a345cacdacf00a40.184df853f391f5ff.8890988306a403bf
+ b0381a418fe355ba
+ after
+ b9ba5cfd0b3b6307.39d0d61ca5d94bf8.fd11bcf821b816b6.e218ae02a476913c
+ 255750f81c3bea5d.a7c776598179fd3e.2359d9aea3214738.7dccde502d79ddac
+ 0000000000000000.0000000000000000.0132009a00b200a4.014c013f015000de
+ 336819c8752b9d4e.a345cacdacf00a40.184df853f391f5ff.8890988306a403bf
+ b0381a418fe355ba
+
+VMPSADBW_128_0x5(reg)
+ before
+ 6b20affbf9a37891.8d74e575f4324241.e96376dc32dedd53.a192f31af9b0e99d
+ 1391531fe271a6ef.ede8f2e07b5313c1.2f26735d2854de58.02183068b922edf1
+ 06da0218e6d91b80.3090bbf6259bcdfa.d1dabebe2bdd48fa.18ad2b2b4ef6bb28
+ 9e46b951a06515f2.3238bca10f152c17.2bcb516ad70658e6.c01b614ed535106d
+ d42f4dbd69eda8ed
+ after
+ 0000000000000000.0000000000000000.007d00d701a60149.00c30157010300ed
+ 1391531fe271a6ef.ede8f2e07b5313c1.2f26735d2854de58.02183068b922edf1
+ 06da0218e6d91b80.3090bbf6259bcdfa.d1dabebe2bdd48fa.18ad2b2b4ef6bb28
+ 9e46b951a06515f2.3238bca10f152c17.2bcb516ad70658e6.c01b614ed535106d
+ d42f4dbd69eda8ed
+VMPSADBW_128_0x5(mem)
+ before
+ 31b66b6426293fd4.38207338ada3ceee.d0ab72cf55ceec45.99452accc6594ac8
+ b379372f29f6904d.31b62c38a81f8323.e4b7576a11d1c8af.779344529765594b
+ 37472d0a8e5f5885.e352e0bd2d63703b.4b26e960622a7d82.21029b67e4b3c31c
+ 97ebcae2707052a7.ab418c34d9fdd0e3.e1c6a39c61e5c7ea.f2de2b7849d1c2e6
+ 4873f1ef624a9256
+ after
+ 31b66b6426293fd4.38207338ada3ceee.d0ab72cf55ceec45.99452accc6594ac8
+ b379372f29f6904d.31b62c38a81f8323.e4b7576a11d1c8af.779344529765594b
+ 0000000000000000.0000000000000000.012b0085010e01cf.0195011f01390104
+ 97ebcae2707052a7.ab418c34d9fdd0e3.e1c6a39c61e5c7ea.f2de2b7849d1c2e6
+ 4873f1ef624a9256
+
+VMPSADBW_128_0x5(reg)
+ before
+ 7e0de839cdab7118.b03089a1eb353ce0.e5cf2a074879e0c6.8261010a2d0f6112
+ f0f80cc3237f99d7.5ee4e6351cbbd05c.ee48b8a31561dc91.0ac38096dfb40927
+ f97f59f70252473f.7dd15d881f0ecb46.20f73275dc43ffef.55ba9b2c95de7955
+ f7f0cc4306b0b6fe.e9c46b880e38e8cb.d82992e73aab868d.3f11ceb86b9b6dc7
+ a49395267cf6a3a9
+ after
+ 0000000000000000.0000000000000000.002e013501dd013f.005a01d8016800d9
+ f0f80cc3237f99d7.5ee4e6351cbbd05c.ee48b8a31561dc91.0ac38096dfb40927
+ f97f59f70252473f.7dd15d881f0ecb46.20f73275dc43ffef.55ba9b2c95de7955
+ f7f0cc4306b0b6fe.e9c46b880e38e8cb.d82992e73aab868d.3f11ceb86b9b6dc7
+ a49395267cf6a3a9
+VMPSADBW_128_0x5(mem)
+ before
+ 600d6c62e5fcd528.44955f11ca2623be.7e898b200847e416.722bd667ca24ad17
+ 4f4bd059c1b8bf70.3ebb10cfeb3fca2b.18eb393c27467b54.4a47f860293ab038
+ 4d193cf52c361fac.40aedae80488e7f2.93b8f1c8874269b1.bccaf63df279ca9d
+ 36432c244383af09.a5b9bac8b18cb6bf.cbba2fb045466958.2400cc6cc26e38f1
+ de34745834a436e1
+ after
+ 600d6c62e5fcd528.44955f11ca2623be.7e898b200847e416.722bd667ca24ad17
+ 4f4bd059c1b8bf70.3ebb10cfeb3fca2b.18eb393c27467b54.4a47f860293ab038
+ 0000000000000000.0000000000000000.0161011a00de00d4.011b00de015d006d
+ 36432c244383af09.a5b9bac8b18cb6bf.cbba2fb045466958.2400cc6cc26e38f1
+ de34745834a436e1
+
+VMPSADBW_128_0x5(reg)
+ before
+ 46b4ec6de5a70019.e6951cd122aa2cb3.cb2aaadb8fd7723d.9bbe70e07c5e3876
+ b8ca2f187004d144.39da88e8e4b752d5.0c4ba88d39f65819.e1902f4448979236
+ 90c339c37246e60f.0ae0ed54a5b7dc9c.c569af4a4c74a3ff.78fce8c8c7fc33c5
+ 2aeb06db86fa7a25.3771c60382b58733.53d0bb7f64dd909a.3cce17591299d64f
+ 08d239e1477b38ff
+ after
+ 0000000000000000.0000000000000000.016b017c01560184.020a0142016b0212
+ b8ca2f187004d144.39da88e8e4b752d5.0c4ba88d39f65819.e1902f4448979236
+ 90c339c37246e60f.0ae0ed54a5b7dc9c.c569af4a4c74a3ff.78fce8c8c7fc33c5
+ 2aeb06db86fa7a25.3771c60382b58733.53d0bb7f64dd909a.3cce17591299d64f
+ 08d239e1477b38ff
+VMPSADBW_128_0x5(mem)
+ before
+ bad3c94e82ad1502.e18e93cd48abcb33.9b5a8fe196bd0fc7.10ccc9961bbe5b96
+ 2d9e438bde3b2883.13f8db0455e513e4.1267c5d8fedc3084.59a9d4fd10a240a1
+ 3cff238477322eaf.1b74daeb49348fe6.7763e2d5d51da595.8bb3d71edc157b64
+ c5c2e5256a9de3b1.554f8cf0bf257ae2.a81c64c4388c2b26.0035d1671ea4478e
+ 157cbb436fdae1c9
+ after
+ bad3c94e82ad1502.e18e93cd48abcb33.9b5a8fe196bd0fc7.10ccc9961bbe5b96
+ 2d9e438bde3b2883.13f8db0455e513e4.1267c5d8fedc3084.59a9d4fd10a240a1
+ 0000000000000000.0000000000000000.00d5013c017301a9.01ea00eb014500de
+ c5c2e5256a9de3b1.554f8cf0bf257ae2.a81c64c4388c2b26.0035d1671ea4478e
+ 157cbb436fdae1c9
+
+VMPSADBW_128_0x6(reg)
+ before
+ 26d5921e6e4384c1.a3b3065ad38902b6.1cd6ed7e53431287.7f5cc69242367e65
+ 8f8a5364b46c6e24.b19e010fcc0049ea.ce53fa01a21b917f.daf084291026597c
+ ade7f981dfe0d99b.cd4e523074107278.c613aee547383376.94a41b77bd697997
+ da3a80e18b2b01d5.d19175a9e5c5398d.5f610596df263619.8844056765099ae3
+ 939cc0e52515788c
+ after
+ 0000000000000000.0000000000000000.012c01b400e300df.013501b201a501e9
+ 8f8a5364b46c6e24.b19e010fcc0049ea.ce53fa01a21b917f.daf084291026597c
+ ade7f981dfe0d99b.cd4e523074107278.c613aee547383376.94a41b77bd697997
+ da3a80e18b2b01d5.d19175a9e5c5398d.5f610596df263619.8844056765099ae3
+ 939cc0e52515788c
+VMPSADBW_128_0x6(mem)
+ before
+ 9278c7dd1996cebd.73cee5f153da247c.9b31e6673b2a5c55.f78bfb800672d414
+ 5fa3973b5c9a59a3.d4ee221bd3787c3c.05fb2254934b95fb.e8db8d1056a74a12
+ d8eaaaeb0a2cd569.59e735cca89246c3.ecbba45e0834a1ab.909fb5b06e51d3c0
+ d71a7ed94058fd3d.5e0519716eb2beba.2d3ce86fb7f23c93.492171cee7fcacca
+ 71aebdd45f3511db
+ after
+ 9278c7dd1996cebd.73cee5f153da247c.9b31e6673b2a5c55.f78bfb800672d414
+ 5fa3973b5c9a59a3.d4ee221bd3787c3c.05fb2254934b95fb.e8db8d1056a74a12
+ 0000000000000000.0000000000000000.010e008400d30158.01ad023d023501d4
+ d71a7ed94058fd3d.5e0519716eb2beba.2d3ce86fb7f23c93.492171cee7fcacca
+ 71aebdd45f3511db
+
+VMPSADBW_128_0x6(reg)
+ before
+ 6292933072883e9f.39fd8ef11a2b8e48.3f94cb75c0671fd0.a24c6b75bb9021dd
+ 7a18f14dbb7f6fc4.db5f5620b2b044b8.58e045433a3aa6af.28b5a75b301b0db5
+ 138ed297d7a8dff3.970e525027f4dbb9.0434854979b98f03.9c441a0d339ebc48
+ 8a3e327a618fcbdb.4ad5ff6f93020e77.a1de86f2186f1679.d8c63f77e025e9c2
+ b904928552bc514e
+ after
+ 0000000000000000.0000000000000000.015e013601ad0181.00970150019100c5
+ 7a18f14dbb7f6fc4.db5f5620b2b044b8.58e045433a3aa6af.28b5a75b301b0db5
+ 138ed297d7a8dff3.970e525027f4dbb9.0434854979b98f03.9c441a0d339ebc48
+ 8a3e327a618fcbdb.4ad5ff6f93020e77.a1de86f2186f1679.d8c63f77e025e9c2
+ b904928552bc514e
+VMPSADBW_128_0x6(mem)
+ before
+ 1bcd9023a670b019.3c750d62f5be6e26.d07fd86812e69a1d.8a2844aab4e876bd
+ daecb33ef74cc24e.837f5fbb30c30681.05d95926c1ad3bd7.1b5fbbdde8b1ec7b
+ d22c79c0615d421a.bca825f1ae2acd97.c5affe97bb61acd3.b0cfe8f85156b35e
+ df5b5d9701aeeda9.433c5a700a7dff15.eccd44a61d11ab3a.a4c4c6658a610912
+ 5589519130602844
+ after
+ 1bcd9023a670b019.3c750d62f5be6e26.d07fd86812e69a1d.8a2844aab4e876bd
+ daecb33ef74cc24e.837f5fbb30c30681.05d95926c1ad3bd7.1b5fbbdde8b1ec7b
+ 0000000000000000.0000000000000000.026c01be006a0201.018500f902690171
+ df5b5d9701aeeda9.433c5a700a7dff15.eccd44a61d11ab3a.a4c4c6658a610912
+ 5589519130602844
+
+VMPSADBW_128_0x6(reg)
+ before
+ 1e6c85e9dede4da0.dd43dcadf24b7f26.7586faa5e04adaa6.57ffa63f02c6f23b
+ 5ab75fd73068b3d1.a8b170f05141b4be.acd402fbcd1d98f7.e010a04e868e3d00
+ 67b7d9c9c4899884.1c71974b399b479c.45706cdd6c8076b4.64ceaec0c6744ab5
+ 9fb8f12a33cd3665.154eccaac765f5ed.9ca736b95a02b088.be034c7fde85d387
+ cc7cf778e9cc94a2
+ after
+ 0000000000000000.0000000000000000.018401d301510129.011401b101650174
+ 5ab75fd73068b3d1.a8b170f05141b4be.acd402fbcd1d98f7.e010a04e868e3d00
+ 67b7d9c9c4899884.1c71974b399b479c.45706cdd6c8076b4.64ceaec0c6744ab5
+ 9fb8f12a33cd3665.154eccaac765f5ed.9ca736b95a02b088.be034c7fde85d387
+ cc7cf778e9cc94a2
+VMPSADBW_128_0x6(mem)
+ before
+ 69052a9803554b32.6006a2661bc0c91f.6f168bf916ac79dd.0dc55bfa322c8120
+ 716a61ca492db262.04ede9e918ef8f5e.06935124437b9197.f416d70c918c2627
+ c07618f9d75f865e.e9b9c01fc4e6c2d0.b692981769def748.ade5a75b12addb4a
+ 32f7cb13c8f78353.69b52574be2f9f1f.5bdfdebea5e2681b.9480c553521bdb35
+ 05312f60ec636493
+ after
+ 69052a9803554b32.6006a2661bc0c91f.6f168bf916ac79dd.0dc55bfa322c8120
+ 716a61ca492db262.04ede9e918ef8f5e.06935124437b9197.f416d70c918c2627
+ 0000000000000000.0000000000000000.01c7015b00c500bc.00b501d2013202a3
+ 32f7cb13c8f78353.69b52574be2f9f1f.5bdfdebea5e2681b.9480c553521bdb35
+ 05312f60ec636493
+
+VMPSADBW_128_0x7(reg)
+ before
+ 5c45e0ee7d10b011.a3b7f7033802646d.e22e1354a05861f7.d1469e0612929f3d
+ f408d56aa0affb5a.ee8317b5448be6d7.ae70862c06ed4605.f39355d9cdfa59d9
+ 2bc6083ef1cb831b.f127a715079ec5be.2ac77b668d7888f5.9f927d25f127521c
+ 5ccb77d80df082ff.876f230f9e48bd4e.b37fed70d0876372.b00e94d49a244632
+ 01d415d4e5fdf047
+ after
+ 0000000000000000.0000000000000000.013601f3015500e0.02470183007a0196
+ f408d56aa0affb5a.ee8317b5448be6d7.ae70862c06ed4605.f39355d9cdfa59d9
+ 2bc6083ef1cb831b.f127a715079ec5be.2ac77b668d7888f5.9f927d25f127521c
+ 5ccb77d80df082ff.876f230f9e48bd4e.b37fed70d0876372.b00e94d49a244632
+ 01d415d4e5fdf047
+VMPSADBW_128_0x7(mem)
+ before
+ 70b07c10eebf0e85.e3621da390aa34b4.8b270890249489b2.a3e4d8b46ca61529
+ d86e4574d075591b.1cd9f60a1586d7e3.db1ad182b68fe617.574138a0fc5fd8c5
+ 14daedeca72b9033.627aff7b380fa53b.5116fad26f4390a8.2be3099f1d40e9f3
+ 02c0ef6490ee6dfa.1392336196d2db66.cbe5ff6d6cbe4292.7c16481d6ad5845f
+ a426ef8680a8e4b4
+ after
+ 70b07c10eebf0e85.e3621da390aa34b4.8b270890249489b2.a3e4d8b46ca61529
+ d86e4574d075591b.1cd9f60a1586d7e3.db1ad182b68fe617.574138a0fc5fd8c5
+ 0000000000000000.0000000000000000.01bb0150017501ea.010b01090135008e
+ 02c0ef6490ee6dfa.1392336196d2db66.cbe5ff6d6cbe4292.7c16481d6ad5845f
+ a426ef8680a8e4b4
+
+VMPSADBW_128_0x7(reg)
+ before
+ 005ffc46fa47469f.7cebc7c8a6c9ad9b.8a6d8d28ca5ab510.24545c3ec80cb900
+ ec0d6ac9743ee6cb.6029f10406c90c43.22570b3c71336ee6.372f8e309f38b11f
+ c47b367b8b18ffe5.8844ea05ccf8451d.399ba90a26e94494.e14210310e4ee61b
+ e4f75bc9db61ce99.d1092cb512651656.298761fc860970c5.ff585e2c315a131f
+ 6b3ff40d2369f558
+ after
+ 0000000000000000.0000000000000000.018200ee010701b7.009d0117020f00af
+ ec0d6ac9743ee6cb.6029f10406c90c43.22570b3c71336ee6.372f8e309f38b11f
+ c47b367b8b18ffe5.8844ea05ccf8451d.399ba90a26e94494.e14210310e4ee61b
+ e4f75bc9db61ce99.d1092cb512651656.298761fc860970c5.ff585e2c315a131f
+ 6b3ff40d2369f558
+VMPSADBW_128_0x7(mem)
+ before
+ 03c14fc0008648f2.a8cbd41dffa58f92.18443502f719381a.5065317f2c1f3126
+ a1abea32e5bec718.6c449fe593717e7d.37c081d694226a94.08821400b5b5c163
+ 22c9414dee1b2ff6.8caeb88b3450d605.0c4b8a1f078b66f1.af2a06eabc595d27
+ 63e7d0fe36ac3cba.6455197d7dced4d7.71afcec86c60e95d.9fa904a8de97411e
+ 364a08a8b6f9a8f6
+ after
+ 03c14fc0008648f2.a8cbd41dffa58f92.18443502f719381a.5065317f2c1f3126
+ a1abea32e5bec718.6c449fe593717e7d.37c081d694226a94.08821400b5b5c163
+ 0000000000000000.0000000000000000.0218017a01890165.0095014f01170071
+ 63e7d0fe36ac3cba.6455197d7dced4d7.71afcec86c60e95d.9fa904a8de97411e
+ 364a08a8b6f9a8f6
+
+VMPSADBW_128_0x7(reg)
+ before
+ ce5b1055e10dd058.3ed11332d97aaa8d.5084c0260b78b49f.43b9c7bddeaeaf03
+ c426171bfa5ef2f3.905287d3f493349e.ac89a8f27ad9b208.5e36f3ea7a80740f
+ 74f819669d794d71.3537a7cfa2029717.d3aecd4d647e09bf.9eefce3b5be3f3af
+ 3b1e13a267e91b7f.094def1100d48f25.23402ca368f2f66f.e0b3d29c9de2e90c
+ fe4d7dfa5d891155
+ after
+ 0000000000000000.0000000000000000.00a2014e00c400e4.00e0014d025801b0
+ c426171bfa5ef2f3.905287d3f493349e.ac89a8f27ad9b208.5e36f3ea7a80740f
+ 74f819669d794d71.3537a7cfa2029717.d3aecd4d647e09bf.9eefce3b5be3f3af
+ 3b1e13a267e91b7f.094def1100d48f25.23402ca368f2f66f.e0b3d29c9de2e90c
+ fe4d7dfa5d891155
+VMPSADBW_128_0x7(mem)
+ before
+ d5884a3fb7e529b4.73e1003bf43a99c8.e85edb852914d7f3.f78bbf601fc1b5c5
+ 4132b559c601eb55.7990dc9edff903f9.af36e8173ace2dae.abdb84f12877816d
+ 1e153a32a6e91366.a976a335c4b195bd.38a390b34e0e4b81.9a7b76c01ca19712
+ 48fe56b874a95f10.5fde516e40ef8ac1.6070514581e1ed99.22b9913b99cb3360
+ 9edfd2cc3b7f9105
+ after
+ d5884a3fb7e529b4.73e1003bf43a99c8.e85edb852914d7f3.f78bbf601fc1b5c5
+ 4132b559c601eb55.7990dc9edff903f9.af36e8173ace2dae.abdb84f12877816d
+ 0000000000000000.0000000000000000.024b0131015a01f5.009e01910088017d
+ 48fe56b874a95f10.5fde516e40ef8ac1.6070514581e1ed99.22b9913b99cb3360
+ 9edfd2cc3b7f9105
+
+VMOVDDUP_YMMorMEM256_to_YMM(reg)
+ before
+ 693a34e19d4becab.9bb983d64b4e8982.f815e3b4ee3d1fb1.0368a7b9f153d122
+ e116b2e55bba81fe.f3113f7848e44ee6.ce6754726b298f38.fd580cfcb76eb147
+ 60bf4b4412598cab.2cd4068a86756a68.3e20a016523f1803.290dfef8f1404934
+ 4481f86a5eb3485e.22cc52f8220f9835.a48cc30b400af4bd.6550f79bbbd55717
+ 8cf075cf3037951a
+ after
+ f3113f7848e44ee6.f3113f7848e44ee6.fd580cfcb76eb147.fd580cfcb76eb147
+ e116b2e55bba81fe.f3113f7848e44ee6.ce6754726b298f38.fd580cfcb76eb147
+ 60bf4b4412598cab.2cd4068a86756a68.3e20a016523f1803.290dfef8f1404934
+ 4481f86a5eb3485e.22cc52f8220f9835.a48cc30b400af4bd.6550f79bbbd55717
+ 8cf075cf3037951a
+VMOVDDUP_YMMorMEM256_to_YMM(mem)
+ before
+ 7ab8f4826c74c069.e7a7b7c3da54f2c2.b0c6a1ae37be9579.5cf7b9bdd0166013
+ 0b73ee9f8c979431.a77f82bb22c9c684.b48e6e98e28c1d60.c2ac7f989fef97b1
+ 1befe112abadcc9e.de5357bed39d004f.09f035a33e87ec15.32f810084822d642
+ 85f648c7e6c125dc.e9703239895cdbd1.8bb872b967bbbdc4.0728687a683a5973
+ 9f8683589ac45cef
+ after
+ 7ab8f4826c74c069.e7a7b7c3da54f2c2.b0c6a1ae37be9579.5cf7b9bdd0166013
+ 0b73ee9f8c979431.a77f82bb22c9c684.b48e6e98e28c1d60.c2ac7f989fef97b1
+ 1befe112abadcc9e.de5357bed39d004f.09f035a33e87ec15.32f810084822d642
+ e7a7b7c3da54f2c2.e7a7b7c3da54f2c2.5cf7b9bdd0166013.5cf7b9bdd0166013
+ 9f8683589ac45cef
+
+VMOVDDUP_YMMorMEM256_to_YMM(reg)
+ before
+ 555e5e107a4a1a63.27559faa58e05b15.25220d96de9394b3.16b2a2c87b324d9a
+ 85fef40ca55bd07a.dcd862a71e142a78.ecb5e64271cd67a3.85a93fba93fa58c3
+ 8bb141bab780bae2.7f4a0eaa536b4d2f.9b74b8aadb968f4d.b66ac77dcd1f996a
+ c2c241854b471444.ee791ea014f18167.8fad7f39bb7b495d.84c1b5fc45abcdbc
+ ca7a862316adb0e5
+ after
+ dcd862a71e142a78.dcd862a71e142a78.85a93fba93fa58c3.85a93fba93fa58c3
+ 85fef40ca55bd07a.dcd862a71e142a78.ecb5e64271cd67a3.85a93fba93fa58c3
+ 8bb141bab780bae2.7f4a0eaa536b4d2f.9b74b8aadb968f4d.b66ac77dcd1f996a
+ c2c241854b471444.ee791ea014f18167.8fad7f39bb7b495d.84c1b5fc45abcdbc
+ ca7a862316adb0e5
+VMOVDDUP_YMMorMEM256_to_YMM(mem)
+ before
+ 6661b4de5c2efd10.887ef0d9fd3b194f.042f0e737cb0824b.22aa375baa07d17e
+ 3242bd19343c7269.38314b216ae906ad.9c395a11a8b70b08.b1b8dd7c46c6635c
+ 0ce81cc0b9e2c91e.2d274dcc2ddc170a.94647e64b30fd9ca.98236b082b453aa5
+ ce214ebf082cbe59.c5acf243e3a08713.c679f75abac6a8bc.3337df6bf40f9302
+ de4035113eb0aa22
+ after
+ 6661b4de5c2efd10.887ef0d9fd3b194f.042f0e737cb0824b.22aa375baa07d17e
+ 3242bd19343c7269.38314b216ae906ad.9c395a11a8b70b08.b1b8dd7c46c6635c
+ 0ce81cc0b9e2c91e.2d274dcc2ddc170a.94647e64b30fd9ca.98236b082b453aa5
+ 887ef0d9fd3b194f.887ef0d9fd3b194f.22aa375baa07d17e.22aa375baa07d17e
+ de4035113eb0aa22
+
+VMOVDDUP_YMMorMEM256_to_YMM(reg)
+ before
+ f5896766a4b5baaf.56b7cd033c270f46.5b0c36f327c19374.104740ded8e7340a
+ d45f73d7c2a90155.7e77177672de7612.4a92164896cc77d8.4c99d5dc297e38e2
+ d70f54ce3518b9c2.232da706c55eb0e9.f08b8dafcb4d6fec.573a3240ca98716d
+ 5ae306b9998f1e9f.22a4f99e52b179f6.a743979263ceb65c.0ef8d4f6d7409bda
+ 4b9d36ea6b837153
+ after
+ 7e77177672de7612.7e77177672de7612.4c99d5dc297e38e2.4c99d5dc297e38e2
+ d45f73d7c2a90155.7e77177672de7612.4a92164896cc77d8.4c99d5dc297e38e2
+ d70f54ce3518b9c2.232da706c55eb0e9.f08b8dafcb4d6fec.573a3240ca98716d
+ 5ae306b9998f1e9f.22a4f99e52b179f6.a743979263ceb65c.0ef8d4f6d7409bda
+ 4b9d36ea6b837153
+VMOVDDUP_YMMorMEM256_to_YMM(mem)
+ before
+ ebf6d408a26cb005.b928850289996e9b.55aa892934e68c66.cd06305ff9dd89d3
+ cbce2a3d9907141b.5029cd17a1c3e360.9909d4958806a664.bc2054812a0524fd
+ c5f3b4736b6059c2.7b34db637e98ba9a.cb8f55cd691f831d.d1dd006391d3c288
+ b630ef9835843a25.9693aa52bba42ef6.c50688bdf33cdebd.69882f73cbd2a01d
+ de6fdd1c738efa6b
+ after
+ ebf6d408a26cb005.b928850289996e9b.55aa892934e68c66.cd06305ff9dd89d3
+ cbce2a3d9907141b.5029cd17a1c3e360.9909d4958806a664.bc2054812a0524fd
+ c5f3b4736b6059c2.7b34db637e98ba9a.cb8f55cd691f831d.d1dd006391d3c288
+ b928850289996e9b.b928850289996e9b.cd06305ff9dd89d3.cd06305ff9dd89d3
+ de6fdd1c738efa6b
+
+VMOVLPS_128_M64_XMM_XMM(reg)
+ before
+ 8ddc06ca25940c1c.7a505697127e7471.fd943650f5737c20.643be951436a746f
+ d31ca7ea7e6f11dd.ed20655b1f5bc3d2.0b817cc9c792e0c3.84f9f47675b40160
+ 0a7bbae61aab4659.eb6c98d27726e273.1ea77629ce8c968c.010e2616a42641bc
+ 8f443d2b93d5e73d.51006ce737eb8f81.915122dda5eed927.b744fa1eecccefae
+ 8269ec7b6ab3c862
+ after
+ 8ddc06ca25940c1c.7a505697127e7471.fd943650f5737c20.643be951436a746f
+ d31ca7ea7e6f11dd.ed20655b1f5bc3d2.0b817cc9c792e0c3.84f9f47675b40160
+ 0a7bbae61aab4659.eb6c98d27726e273.1ea77629ce8c968c.010e2616a42641bc
+ 8f443d2b93d5e73d.51006ce737eb8f81.915122dda5eed927.b744fa1eecccefae
+ 8269ec7b6ab3c862
+VMOVLPS_128_M64_XMM_XMM(mem)
+ before
+ 3f4779173ae78805.bec52b2688782f34.f9a85b867ab78427.c0cd7b4fe943e63f
+ c8ab1be07672eac3.f348814193215ceb.c02fe39c5d957d92.06667ded3517f981
+ f96150c13d62acc7.8a1b39ea505aa70e.82637f13fb9138ee.c167252125f64e98
+ b03493a6a9c2883e.df88518c5cb14f48.1b0eacd870b76f66.4b1d6e59566d2031
+ 02d454006408acf8
+ after
+ 3f4779173ae78805.bec52b2688782f34.f9a85b867ab78427.c0cd7b4fe943e63f
+ c8ab1be07672eac3.f348814193215ceb.c02fe39c5d957d92.06667ded3517f981
+ 0000000000000000.0000000000000000.c02fe39c5d957d92.c0cd7b4fe943e63f
+ b03493a6a9c2883e.df88518c5cb14f48.1b0eacd870b76f66.4b1d6e59566d2031
+ 02d454006408acf8
+
+VMOVLPS_128_M64_XMM_XMM(reg)
+ before
+ 40d8d382ea512e98.c8f2607bd69f3a54.4edcc49252b28e46.67fde4d8d914de27
+ 6375e74a84d6e1bd.1d65332ce1048034.33628f6acfe8a2b3.41fca5fd52b4435c
+ c5f68dc7cf220215.8b5a89a5e5fd140b.ea68ac7f6edfc43c.87d76a35f6a15832
+ c4a8bf6267c2cd49.ee9dddd2fe97b304.cf38193ecc23338d.1459b06ae1e9dad5
+ c450f18a30988570
+ after
+ 40d8d382ea512e98.c8f2607bd69f3a54.4edcc49252b28e46.67fde4d8d914de27
+ 6375e74a84d6e1bd.1d65332ce1048034.33628f6acfe8a2b3.41fca5fd52b4435c
+ c5f68dc7cf220215.8b5a89a5e5fd140b.ea68ac7f6edfc43c.87d76a35f6a15832
+ c4a8bf6267c2cd49.ee9dddd2fe97b304.cf38193ecc23338d.1459b06ae1e9dad5
+ c450f18a30988570
+VMOVLPS_128_M64_XMM_XMM(mem)
+ before
+ 7386ab80feb8142f.bad87b88e7417e08.22faaba04add184c.3e20d11184412951
+ fcc8593868574440.05d0bda5eb2b50fc.023d6ff9e2db000f.936ad06532c4e335
+ 3de2779e8a81d1cd.ffdd7f26100d80d2.6c32a6cbe49e2778.2a6312a674389de4
+ 11a0819e7e407702.054abf75f1724a35.3ba4cb006c3149b4.5f579441e32a920b
+ 8e9150a11d25ff55
+ after
+ 7386ab80feb8142f.bad87b88e7417e08.22faaba04add184c.3e20d11184412951
+ fcc8593868574440.05d0bda5eb2b50fc.023d6ff9e2db000f.936ad06532c4e335
+ 0000000000000000.0000000000000000.023d6ff9e2db000f.3e20d11184412951
+ 11a0819e7e407702.054abf75f1724a35.3ba4cb006c3149b4.5f579441e32a920b
+ 8e9150a11d25ff55
+
+VMOVLPS_128_M64_XMM_XMM(reg)
+ before
+ 125f4431beb6206f.53cef42563a2f10c.746578002be6e9d2.4a605a8695a021ee
+ 490b6c5f61683105.e1374a1d52b3fc17.a678a63259f69b54.7732cf487bf86d53
+ 8ee2c296a2c76dc3.96a90274697e544e.f8d14577182d9968.9de6a6323b44e60e
+ 3d3144421e601153.4dee9514c40fb4de.c6ba523a031722ba.97485c30f1914b4c
+ 43246c2eb7e95639
+ after
+ 125f4431beb6206f.53cef42563a2f10c.746578002be6e9d2.4a605a8695a021ee
+ 490b6c5f61683105.e1374a1d52b3fc17.a678a63259f69b54.7732cf487bf86d53
+ 8ee2c296a2c76dc3.96a90274697e544e.f8d14577182d9968.9de6a6323b44e60e
+ 3d3144421e601153.4dee9514c40fb4de.c6ba523a031722ba.97485c30f1914b4c
+ 43246c2eb7e95639
+VMOVLPS_128_M64_XMM_XMM(mem)
+ before
+ 7b455218ac5ac400.b141edcf70bd5864.e4d380eb7e72d9f3.6c80c8e9b64170f5
+ 1d798adbeaf051ce.4861b9a9356d80a0.352440e4b4b47fb8.466fa3f0cf36c0c6
+ 038a91618db6b8cf.5cdca43c08f9c3b4.1ead50ea81e0625a.b1d2dfb9e7834ed8
+ 0b45e197b2b8b72e.4bfdabf586ef5e4b.79392ceb01023d04.07f778b19cb256d8
+ a5286b448a511372
+ after
+ 7b455218ac5ac400.b141edcf70bd5864.e4d380eb7e72d9f3.6c80c8e9b64170f5
+ 1d798adbeaf051ce.4861b9a9356d80a0.352440e4b4b47fb8.466fa3f0cf36c0c6
+ 0000000000000000.0000000000000000.352440e4b4b47fb8.6c80c8e9b64170f5
+ 0b45e197b2b8b72e.4bfdabf586ef5e4b.79392ceb01023d04.07f778b19cb256d8
+ a5286b448a511372
+
+VMOVLPS_128_XMM_M64(reg)
+ before
+ e7b2b3df4cecc251.0f76f86a74020718.6f11c83e4ada8c12.239650d25127cde3
+ 29e14cec7e0e9e22.ece851c5f0a167b8.2665f985f1478bb4.f98e398c8d5ace22
+ c70132d9bd43e590.7f69699341a0913b.ca43393416c195df.d5ee6103d0a8fbee
+ 1c5e6211a417d148.a2c3bac2830c42cc.b9f785b956d4e63c.94824624361c1173
+ 131664dbdcc2ccdc
+ after
+ e7b2b3df4cecc251.0f76f86a74020718.6f11c83e4ada8c12.239650d25127cde3
+ 29e14cec7e0e9e22.ece851c5f0a167b8.2665f985f1478bb4.f98e398c8d5ace22
+ c70132d9bd43e590.7f69699341a0913b.ca43393416c195df.d5ee6103d0a8fbee
+ 1c5e6211a417d148.a2c3bac2830c42cc.b9f785b956d4e63c.94824624361c1173
+ 131664dbdcc2ccdc
+VMOVLPS_128_XMM_M64(mem)
+ before
+ 2c763515dda6e856.8644d600d0179ff6.32c4c23dd3f03698.4dcfd87f4c0dbc79
+ bc6d37bd56d5200c.60fe8c12dcce8a45.0b36fcf04d5829cb.e3162df295f75142
+ 9fc8e5be625a312b.06d97fb365c9d0e2.0ae6e4c70c50d690.d817827ecc1ee243
+ b154bb061e42d7df.d421ac4f0693aa78.099ff7af2de5fa14.861fd38f8d0fab27
+ 4a7a1a917555e79a
+ after
+ 2c763515dda6e856.8644d600d0179ff6.32c4c23dd3f03698.d817827ecc1ee243
+ bc6d37bd56d5200c.60fe8c12dcce8a45.0b36fcf04d5829cb.e3162df295f75142
+ 9fc8e5be625a312b.06d97fb365c9d0e2.0ae6e4c70c50d690.d817827ecc1ee243
+ b154bb061e42d7df.d421ac4f0693aa78.099ff7af2de5fa14.861fd38f8d0fab27
+ 4a7a1a917555e79a
+
+VMOVLPS_128_XMM_M64(reg)
+ before
+ 817455f01f7cd34a.cfdb3580a598cd53.25220d525cb857b4.e52fb092cb225082
+ 85597f192811abe1.d32acf181468d1b4.5728a02802c41241.7a608a5d02149607
+ b37494762c9faa0b.9a0c06ba86bf9d2d.c57f603e954416cd.a40004fdefc686cf
+ 67139075c6b20d75.004f555218a8edeb.cb724afeb0c3a001.3fd9975dad44dc05
+ 27b8c068599b56d6
+ after
+ 817455f01f7cd34a.cfdb3580a598cd53.25220d525cb857b4.e52fb092cb225082
+ 85597f192811abe1.d32acf181468d1b4.5728a02802c41241.7a608a5d02149607
+ b37494762c9faa0b.9a0c06ba86bf9d2d.c57f603e954416cd.a40004fdefc686cf
+ 67139075c6b20d75.004f555218a8edeb.cb724afeb0c3a001.3fd9975dad44dc05
+ 27b8c068599b56d6
+VMOVLPS_128_XMM_M64(mem)
+ before
+ 3869fc0c0ed6ae6d.fd80708092d710cb.e1bd38cce52f7f1a.c44f58d6f0ceeb8c
+ 4eb7c634e901a1f7.d1082f052d99efb8.19232c1509610de5.0e608831f0f03417
+ 45709acc0629eba0.3ff7c96f3285e5e9.844eab17a1495379.03f2d57a4cb5b751
+ f95ef5c07f594793.a3993a2a3e252f09.fd0833c0c9f30f01.01513b1fa1aab0e4
+ 62c8b68b8b5a5a7d
+ after
+ 3869fc0c0ed6ae6d.fd80708092d710cb.e1bd38cce52f7f1a.03f2d57a4cb5b751
+ 4eb7c634e901a1f7.d1082f052d99efb8.19232c1509610de5.0e608831f0f03417
+ 45709acc0629eba0.3ff7c96f3285e5e9.844eab17a1495379.03f2d57a4cb5b751
+ f95ef5c07f594793.a3993a2a3e252f09.fd0833c0c9f30f01.01513b1fa1aab0e4
+ 62c8b68b8b5a5a7d
+
+VMOVLPS_128_XMM_M64(reg)
+ before
+ 84a5432aa551f3c7.464e52fc729d72fd.59397fa2ec0809c5.621d3ffa9c6bfbaa
+ c132dd698b1bb46f.070c2c6cfb022809.bd259243d9b7afc9.8e5b4bb336bed4a0
+ 77bc80b2da45dc20.1a6401fd359325e4.2ba77179a0c05cc0.5d8cd4d6b4f8560e
+ 009028722d5ba587.5a224d993d5c24b9.ff0c17b0ddae4d56.ab7e554f32233c21
+ 53fb4a0aca4d4304
+ after
+ 84a5432aa551f3c7.464e52fc729d72fd.59397fa2ec0809c5.621d3ffa9c6bfbaa
+ c132dd698b1bb46f.070c2c6cfb022809.bd259243d9b7afc9.8e5b4bb336bed4a0
+ 77bc80b2da45dc20.1a6401fd359325e4.2ba77179a0c05cc0.5d8cd4d6b4f8560e
+ 009028722d5ba587.5a224d993d5c24b9.ff0c17b0ddae4d56.ab7e554f32233c21
+ 53fb4a0aca4d4304
+VMOVLPS_128_XMM_M64(mem)
+ before
+ 33d02ff39b8227e4.b9f7d11621e74c50.a3128a2e2e6ae2b6.95a081552d0dbd39
+ 26c980f6bfcda4ec.ff40780851770d26.d0ff36a624c81b04.49afa9d22c6aea13
+ 07b1baff523a754a.2cb618b65a9724b6.bfb6ccef3c828ad2.76858d9575500e90
+ b45657fb70d55727.9da4ad8bd7d1ccac.4b03c8f492a5ec4a.7a6d2809a54c665d
+ b0b5769956e92d26
+ after
+ 33d02ff39b8227e4.b9f7d11621e74c50.a3128a2e2e6ae2b6.76858d9575500e90
+ 26c980f6bfcda4ec.ff40780851770d26.d0ff36a624c81b04.49afa9d22c6aea13
+ 07b1baff523a754a.2cb618b65a9724b6.bfb6ccef3c828ad2.76858d9575500e90
+ b45657fb70d55727.9da4ad8bd7d1ccac.4b03c8f492a5ec4a.7a6d2809a54c665d
+ b0b5769956e92d26
+
+VRCPSS_128(reg)
+ before
+ 74a774b327b3a197.0882d5d437ab06b2.ae5833f265b342b3.4fb2a7a1413cfd98
+ 21901cc2b236fb5a.de03b078c0c73d14.bc1ca7599fc9c177.a98fe3e2655378e9
+ 15bc6c3293ff7a1e.14a362d12935b97c.213d042b229e87a5.3366faa31bf71b69
+ ab765f6f679a598d.842e69cd8e023614.3a0646d489becee9.cb0267d07f33a043
+ 4b31a656ab14c3a4
+ after
+ 0000000000000000.0000000000000000.bc1ca7599fc9c177.a98fe3e26304a000
+ 21901cc2b236fb5a.de03b078c0c73d14.bc1ca7599fc9c177.a98fe3e2655378e9
+ 15bc6c3293ff7a1e.14a362d12935b97c.213d042b229e87a5.3366faa31bf71b69
+ ab765f6f679a598d.842e69cd8e023614.3a0646d489becee9.cb0267d07f33a043
+ 4b31a656ab14c3a4
+VRCPSS_128(mem)
+ before
+ 91bd341fbea442b8.3e0cf2e6c991d354.0c7240570a397009.63c569c171b5d2ef
+ 77738c18d1f1d7aa.2cc81f015672251e.863a635bbae72286.f8c5695c7510d162
+ db1f2a2e03073fa6.cff8e42da9c88a98.cf514ec5b91609b8.55514312315a05ee
+ 978c8a4c6df136da.85e63cd75f203f6d.c4857e8123d5e1ca.d6b6f250421fab40
+ d740728043ecff04
+ after
+ 91bd341fbea442b8.3e0cf2e6c991d354.0c7240570a397009.63c569c171b5d2ef
+ 77738c18d1f1d7aa.2cc81f015672251e.863a635bbae72286.f8c5695c7510d162
+ 0000000000000000.0000000000000000.863a635bbae72286.f8c5695c0d343000
+ 978c8a4c6df136da.85e63cd75f203f6d.c4857e8123d5e1ca.d6b6f250421fab40
+ d740728043ecff04
+
+VRCPSS_128(reg)
+ before
+ b43bbf10d14c3ce6.8888285d2dbb776f.a8df236a1305804b.3fa06d7b152d65e9
+ c9f3d66b88cc9f91.8add814f5f71bf94.962f9651620389db.1d6f99a0aa2c5241
+ 72b3b1fd03f664b1.7a590f0d1e20ca73.a9218ffae7a796cb.3bbd7edaffdd64fd
+ 0ac94e32de59c7f3.32c6508387d35338.3e030cd03e7ce2c7.73589617304d574a
+ a20b5f415786e654
+ after
+ 0000000000000000.0000000000000000.962f9651620389db.1d6f99a0ffdd64fd
+ c9f3d66b88cc9f91.8add814f5f71bf94.962f9651620389db.1d6f99a0aa2c5241
+ 72b3b1fd03f664b1.7a590f0d1e20ca73.a9218ffae7a796cb.3bbd7edaffdd64fd
+ 0ac94e32de59c7f3.32c6508387d35338.3e030cd03e7ce2c7.73589617304d574a
+ a20b5f415786e654
+VRCPSS_128(mem)
+ before
+ a4a153469397ce46.ef7fa976b67e0303.8ff1c09eb5971711.b21f083f040eaa7b
+ 55e7f111fd89cb4c.7c22bc3526f3558c.6da5d948c477d228.5fc27fb3d5ea2992
+ 92a9b28eb46a9893.0dfe85dbcb43f83b.a8b0196ed17f40a9.a2386e984c9b9db8
+ 35b313a8d145f347.fd5ffed440fb2abc.1ddcfbfcf8bc1cc1.d7cdd05a05ad409b
+ 5bcda1669dad4ee4
+ after
+ a4a153469397ce46.ef7fa976b67e0303.8ff1c09eb5971711.b21f083f040eaa7b
+ 55e7f111fd89cb4c.7c22bc3526f3558c.6da5d948c477d228.5fc27fb3d5ea2992
+ 0000000000000000.0000000000000000.6da5d948c477d228.5fc27fb37ae5b000
+ 35b313a8d145f347.fd5ffed440fb2abc.1ddcfbfcf8bc1cc1.d7cdd05a05ad409b
+ 5bcda1669dad4ee4
+
+VRCPSS_128(reg)
+ before
+ 8883dd26b0260542.1bd1914e72279594.aa91258d21a525ba.a6f7fbdf5439239c
+ bb3d8008d9a49f5f.20cea769b31b3da5.6fdff6700cd026e2.20cb950201021165
+ 50458777b4b459e8.2078d1e6af2da5a6.a7966beb9a0568df.672546501c23a149
+ a3e8ecdedee16f88.f7998cb1836a8bc4.b003826969d2295e.57d189b7c0a99173
+ cc9ada220aa09b10
+ after
+ 0000000000000000.0000000000000000.6fdff6700cd026e2.20cb950262c83800
+ bb3d8008d9a49f5f.20cea769b31b3da5.6fdff6700cd026e2.20cb950201021165
+ 50458777b4b459e8.2078d1e6af2da5a6.a7966beb9a0568df.672546501c23a149
+ a3e8ecdedee16f88.f7998cb1836a8bc4.b003826969d2295e.57d189b7c0a99173
+ cc9ada220aa09b10
+VRCPSS_128(mem)
+ before
+ a14eb57d15127b4b.1072adabf2b81cec.81fe52b74adda82b.e570365515c2a30a
+ b4b796b4fe0def52.f32fc6498dc39dbf.9a73a1e22092bb06.a129831d39621291
+ e0a2fab3e09db14e.a86b31244a902eae.1dc4f42022967e82.427c652c713db49c
+ 01db5c67d8cc7e6e.8b71eca8c6ab0a64.e8bcc75c6cf4aecb.22b4d9ee5adfc3da
+ 9e1cdacf90d57cf4
+ after
+ a14eb57d15127b4b.1072adabf2b81cec.81fe52b74adda82b.e570365515c2a30a
+ b4b796b4fe0def52.f32fc6498dc39dbf.9a73a1e22092bb06.a129831d39621291
+ 0000000000000000.0000000000000000.9a73a1e22092bb06.a129831d69285800
+ 01db5c67d8cc7e6e.8b71eca8c6ab0a64.e8bcc75c6cf4aecb.22b4d9ee5adfc3da
+ 9e1cdacf90d57cf4
+
+VRCPPS_128(reg)
+ before
+ 1301643cadaa1a99.f32e38ba01a811dc.f88ef2419c9f6f8f.d629978118b8070c
+ dbaf739f50eadb73.92670a99783d27c4.4b0e3f5c68f896d8.c3d5de7d45ef4472
+ 547203651322f92f.b9524ff158957c53.e03dcf63c742beee.8a8d1a3b0da42228
+ d89611fb92ddb078.46ba81adbdbeccb5.13679fc4550a227b.091dc7a78ce35d5b
+ 1b515faedfb9b137
+ after
+ 1301643cadaa1a99.f32e38ba01a811dc.f88ef2419c9f6f8f.d629978118b8070c
+ 0000000000000000.0000000000000000.9eaca800b7a84800.f46840007147a000
+ 547203651322f92f.b9524ff158957c53.e03dcf63c742beee.8a8d1a3b0da42228
+ d89611fb92ddb078.46ba81adbdbeccb5.13679fc4550a227b.091dc7a78ce35d5b
+ 1b515faedfb9b137
+VRCPPS_128(mem)
+ before
+ 9cf55f3a2131d9e7.c46798cc6aa73efb.146c1eb8c4c4d215.3fd8aae9addbfd2b
+ 67d444386f579297.74309443360ddd63.fe34a20089b14ca0.c2dbec406b428bab
+ 5abc8995e4389875.453e01ce939aca5d.e2de87702793f382.f7be61342cca0aa7
+ 4f77aa3b9cdfa6ab.91dddcd81cda4195.9a364bf4ba7686e6.39cb05318cffb4ca
+ e64fd5a2266dc6c1
+ after
+ 9cf55f3a2131d9e7.c46798cc6aa73efb.146c1eb8c4c4d215.3fd8aae9addbfd2b
+ 0000000000000000.0000000000000000.6a8ac800ba267800.3f174000d114f800
+ 5abc8995e4389875.453e01ce939aca5d.e2de87702793f382.f7be61342cca0aa7
+ 4f77aa3b9cdfa6ab.91dddcd81cda4195.9a364bf4ba7686e6.39cb05318cffb4ca
+ e64fd5a2266dc6c1
+
+VRCPPS_128(reg)
+ before
+ 5996ccf696a17c38.24d22418b5587965.b55920cd6d5a7db6.040868785f65bff9
+ edece696792711da.b399721748b0cdd0.0dfec91923a5bb6d.fa1f5ce8316c5be6
+ 009c1fef6a89c254.da980f2473f25e18.f518d328da473765.5a49a3314d9716da
+ ecf4746d0655cb51.739a7a2b522be768.c9f23a672dcd2c4b.fe50b73dcef3ab00
+ c40116fad18bd885
+ after
+ 5996ccf696a17c38.24d22418b5587965.b55920cd6d5a7db6.040868785f65bff9
+ 0000000000000000.0000000000000000.89d66000a4a47800.24a280003158e000
+ 009c1fef6a89c254.da980f2473f25e18.f518d328da473765.5a49a3314d9716da
+ ecf4746d0655cb51.739a7a2b522be768.c9f23a672dcd2c4b.fe50b73dcef3ab00
+ c40116fad18bd885
+VRCPPS_128(mem)
+ before
+ 86283b52716c5695.0f3ee07de816687e.5c6d2c18006625ed.e5dafb40b8c2d7cb
+ 2190a233cba0e45b.c3c75f89ad59d486.6fdba2d799afd4d3.a51a112118b37490
+ 7207c788fa363c04.66dbedfff0a94c16.89b159543a12af45.65ff7874e92a3f47
+ 5357273c1b371bbc.52c6864a4e920cda.87bbcc7bff9c736f.81d52ca7c6b6739b
+ 55e82a254be04d39
+ after
+ 86283b52716c5695.0f3ee07de816687e.5c6d2c18006625ed.e5dafb40b8c2d7cb
+ 0000000000000000.0000000000000000.228a28007f800000.9915a800c6283000
+ 7207c788fa363c04.66dbedfff0a94c16.89b159543a12af45.65ff7874e92a3f47
+ 5357273c1b371bbc.52c6864a4e920cda.87bbcc7bff9c736f.81d52ca7c6b6739b
+ 55e82a254be04d39
+
+VRCPPS_128(reg)
+ before
+ 3d836d59153609cd.a14e3d3d49b13dae.e5d427d562a14f7d.43c577390258dc7e
+ 95f4f0b1bf43e302.39b68576a0af5e06.7950cb0ec86153ac.9a9bd7786253a69e
+ b985b298e6931685.f55c7bd43d3e39f1.6b876e601d5e5113.6808662639988cfb
+ 0483ac7b25b3df01.b20b9c413c698b9b.18c60c37fd25885d.89d9a22da3334bc0
+ dadb067bbd309f19
+ after
+ 3d836d59153609cd.a14e3d3d49b13dae.e5d427d562a14f7d.43c577390258dc7e
+ 0000000000000000.0000000000000000.1372000061936000.16f038004556d000
+ b985b298e6931685.f55c7bd43d3e39f1.6b876e601d5e5113.6808662639988cfb
+ 0483ac7b25b3df01.b20b9c413c698b9b.18c60c37fd25885d.89d9a22da3334bc0
+ dadb067bbd309f19
+VRCPPS_128(mem)
+ before
+ 35d80ffba29c4334.d43adcc4192e7a23.4c9162aab83c0f30.da57a10003413236
+ 779d37996e82f53a.84f63ce05d912296.9fb84bfccdc383db.0e862a25cb3e8c4c
+ 7cf5fc413fef6e5a.6f02cb3c8e671407.874ed221980ba1c8.10a1a213f2a9d248
+ 20aed9df2eee6dbe.f3ac8242473c8c22.e01d7407351f2524.3df30537140d40d9
+ efc750fbccf611a9
+ after
+ 35d80ffba29c4334.d43adcc4192e7a23.4c9162aab83c0f30.da57a10003413236
+ 0000000000000000.0000000000000000.32615800c6ae4800.a497f0007ba99800
+ 7cf5fc413fef6e5a.6f02cb3c8e671407.874ed221980ba1c8.10a1a213f2a9d248
+ 20aed9df2eee6dbe.f3ac8242473c8c22.e01d7407351f2524.3df30537140d40d9
+ efc750fbccf611a9
+
+VRCPPS_256(reg)
+ before
+ 836a7dcdb6f18265.3f924a60598bac92.6b3e5e60259dc692.86f2ab98bf0ccd1b
+ 55288a186f89ceb8.b56fcbaedcd3e904.32055c00c315fd04.5599f5c252dd53d9
+ c14d7247924a334f.5e0fd9b6d2d1dd3d.a64d7790bd306e24.29ddcd700b9e7489
+ 232531c8bcc1ebd5.163fef655791476c.2162ab7bb07a559d.de8caf8e055cec57
+ 507018085d227670
+ after
+ 836a7dcdb6f18265.3f924a60598bac92.6b3e5e60259dc692.86f2ab98bf0ccd1b
+ bd9f7800eca20800.20e3d000ac1c2800.d89f7800c1b9c000.5513c000734ec800
+ c14d7247924a334f.5e0fd9b6d2d1dd3d.a64d7790bd306e24.29ddcd700b9e7489
+ 232531c8bcc1ebd5.163fef655791476c.2162ab7bb07a559d.de8caf8e055cec57
+ 507018085d227670
+VRCPPS_256(mem)
+ before
+ 5b5682ca2efccf00.d7fcc406887933f7.b8ca89a68820e1bb.0190f42d3880ed1c
+ db0a6bc194f7b332.391d266e93ff4660.227e236481896856.a0224f12f0ce734c
+ ab584ed7ad1ede33.a5d6526a78de61be.2f253a8d5dd8986a.5c66b79674ee23da
+ a90ca8f9927d0b2f.77714767d3a2c0ba.bb8d480c381a2c23.8fa62825616e3971
+ 972f9e2c52daf0be
+ after
+ 5b5682ca2efccf00.d7fcc406887933f7.b8ca89a68820e1bb.0190f42d3880ed1c
+ 2398c0005001a000.a701a000f6837800.c621c800f6cba800.7d620800467e3000
+ ab584ed7ad1ede33.a5d6526a78de61be.2f253a8d5dd8986a.5c66b79674ee23da
+ a90ca8f9927d0b2f.77714767d3a2c0ba.bb8d480c381a2c23.8fa62825616e3971
+ 972f9e2c52daf0be
+
+VRCPPS_256(reg)
+ before
+ ce4d1615e4bc856d.b0f2f3146121f751.0a3bfed141d79f03.a280cbcd2f5ae1ac
+ 914c8a4eb2a23429.9bd5ad1336155dc6.bc8074155e0a3943.bfcb3ebc5da47332
+ 3c77f8415918389f.488251e12c65fbb9.e88ba69ec5c6cb26.f03a1ec5df059ee1
+ 2c1c5b5c74a8ce7b.92c55b6c5f1e8b57.eaaa8fd712989159.1098e5d5d0881de4
+ fab311d64d39ad68
+ after
+ ce4d1615e4bc856d.b0f2f3146121f751.0a3bfed141d79f03.a280cbcd2f5ae1ac
+ 4284280025d74800.367b6800528e8000.966aa000b924d800.8eb018009ff54800
+ 3c77f8415918389f.488251e12c65fbb9.e88ba69ec5c6cb26.f03a1ec5df059ee1
+ 2c1c5b5c74a8ce7b.92c55b6c5f1e8b57.eaaa8fd712989159.1098e5d5d0881de4
+ fab311d64d39ad68
+VRCPPS_256(mem)
+ before
+ 8c551db571250a98.bb85b00aa0e03268.546a479fec4bcacc.1e272b2ee20bc788
+ a04c855f5957efa1.46fff1b7784ca012.6c3d9266eff97343.df4f770ed1aba85e
+ 1462c6bf20dc19ae.29d61ccf99765326.b40ab7ad833244e8.8b6e6ee37a047188
+ c2645ac0e2be44ec.c0562cbe9eec8850.0a9c3260c404f7e9.7dd00b1979a35eb2
+ 10c14d1c6b13aa87
+ after
+ 8c551db571250a98.bb85b00aa0e03268.546a479fec4bcacc.1e272b2ee20bc788
+ f299c8000dc69000.c3751000de122800.2a8be00092a0d000.60c408009cea7000
+ 1462c6bf20dc19ae.29d61ccf99765326.b40ab7ad833244e8.8b6e6ee37a047188
+ c2645ac0e2be44ec.c0562cbe9eec8850.0a9c3260c404f7e9.7dd00b1979a35eb2
+ 10c14d1c6b13aa87
+
+VRCPPS_256(reg)
+ before
+ a28d2d58ebe192b4.881dbf50bc0b2c87.67cb1df0233a7b3c.48c17f6ccf7b486f
+ 8d7fa83a969852e4.405b705acacf8caa.7b80ebd2c5eb6795.4c431bbbbfa2f5a9
+ 2fe4bb2c07c426c4.c8e8eaca27152182.56c393ce208b8a07.f0ef803bb185b8c1
+ e208619cdbf249ff.fa92a78cefe9a73b.55de1051cfa61e3f.12912cd6c0304ee4
+ 8cf49a7a09b0723d
+ after
+ a28d2d58ebe192b4.881dbf50bc0b2c87.67cb1df0233a7b3c.48c17f6ccf7b486f
+ 4f0f480077271000.b60cb00057dbb000.282788005e6ad800.8e08d000cd751000
+ 2fe4bb2c07c426c4.c8e8eaca27152182.56c393ce208b8a07.f0ef803bb185b8c1
+ e208619cdbf249ff.fa92a78cefe9a73b.55de1051cfa61e3f.12912cd6c0304ee4
+ 8cf49a7a09b0723d
+VRCPPS_256(mem)
+ before
+ 3be64712a710e2f9.043796f4adadf842.b323258d3f57d900.d41e5ec86ec95fe9
+ fc31ad8ab65d5843.efbd57a21a816f39.d068dfb7336c74fd.2ecf799e9a7f8bb1
+ a9a34acd54a29148.01e69e11bdfbe98f.2b2d51f7e6333460.c13c5e3eef54dc42
+ 1f0699ca9aeb4834.94fd69ad32a6a3f1.a13df83a74b9d553.e8b3081607d58e48
+ ff7e7391818ddf70
+ after
+ 3be64712a710e2f9.043796f4adadf842.b323258d3f57d900.d41e5ec86ec95fe9
+ 430e4800d7e22000.7ab27800d13c5800.cbc8d8003f97d000.aacef0001022c000
+ a9a34acd54a29148.01e69e11bdfbe98f.2b2d51f7e6333460.c13c5e3eef54dc42
+ 1f0699ca9aeb4834.94fd69ad32a6a3f1.a13df83a74b9d553.e8b3081607d58e48
+ ff7e7391818ddf70
+
+VPSADBW_128(reg)
+ before
+ 62eb9b1bf7090966.3a27166aa6443a32.0550b3e2160ed90b.0e664e6afa091202
+ 6d447c2005d449d5.d6d13e9a94ba236f.b029791c05c0c788.4e72d175932fa89a
+ 7bd6130d477adb6a.d0d28c467f58bf16.f2d5b5c79a47a814.3e2efc465c375347
+ eaec5b4c5b87fad1.02f47c5b832bc954.25a0654f712fb95d.b8664cc9702ece34
+ 99e63beaec20d78e
+ after
+ 0000000000000000.0000000000000000.0000000000000376.0000000000000195
+ 6d447c2005d449d5.d6d13e9a94ba236f.b029791c05c0c788.4e72d175932fa89a
+ 7bd6130d477adb6a.d0d28c467f58bf16.f2d5b5c79a47a814.3e2efc465c375347
+ eaec5b4c5b87fad1.02f47c5b832bc954.25a0654f712fb95d.b8664cc9702ece34
+ 99e63beaec20d78e
+VPSADBW_128(mem)
+ before
+ bd7a4795eb172780.15d4504ada88e3b5.49058ac3bd3efe55.a6d584212705360c
+ 00edebb689217d37.57d9ee746209d2c3.81cf326c489d1a44.d1c20ea758545ad0
+ 3e0da339e34993df.0e4631348f9403a6.861ff1414155d84e.02b1ff4f9ea86353
+ 53a4eb0a159c27a3.956816f8fcb7b10b.34c1412dc471f69e.96f05483988e8a41
+ e7c908b1e0910e48
+ after
+ bd7a4795eb172780.15d4504ada88e3b5.49058ac3bd3efe55.a6d584212705360c
+ 00edebb689217d37.57d9ee746209d2c3.81cf326c489d1a44.d1c20ea758545ad0
+ 0000000000000000.0000000000000000.000000000000037a.00000000000002a2
+ 53a4eb0a159c27a3.956816f8fcb7b10b.34c1412dc471f69e.96f05483988e8a41
+ e7c908b1e0910e48
+
+VPSADBW_128(reg)
+ before
+ 52891744123d2911.1b7f40163a25f2b0.478b982b46fd199d.6780a01eebfd2e61
+ 337b7da8cb1f194b.726a1d476ef0b331.82fbb33908f37709.fb2a8affd5063cc3
+ e6ed3649a6c217a0.3331fe8bce0a2453.a004648ede2406fb.cb8979bc9b97deef
+ c72a3f933fb362bc.3c9f5fcd767e0241.fff1a596651c031e.b56aeb415bbcce12
+ 94995a7b3182c957
+ after
+ 0000000000000000.0000000000000000.00000000000004c1.000000000000027c
+ 337b7da8cb1f194b.726a1d476ef0b331.82fbb33908f37709.fb2a8affd5063cc3
+ e6ed3649a6c217a0.3331fe8bce0a2453.a004648ede2406fb.cb8979bc9b97deef
+ c72a3f933fb362bc.3c9f5fcd767e0241.fff1a596651c031e.b56aeb415bbcce12
+ 94995a7b3182c957
+VPSADBW_128(mem)
+ before
+ 44e2455438f48aeb.327d93f2347c344d.6882bcf981580929.f91074bd3868aa1f
+ a11125ba8d1ecefa.82332ed21eaccafc.93a492fb0ba5f434.ebabcc6ff49337aa
+ 86f277974b0d51af.15980da09bcc6078.99d25cbf31708091.320fa9193529e56a
+ d150b8d98ecccf36.46f82ac6476a316b.55d896310ec5696a.2888082595b7f10b
+ 2b62e301b3c8973b
+ after
+ 44e2455438f48aeb.327d93f2347c344d.6882bcf981580929.f91074bd3868aa1f
+ a11125ba8d1ecefa.82332ed21eaccafc.93a492fb0ba5f434.ebabcc6ff49337aa
+ 0000000000000000.0000000000000000.0000000000000232.0000000000000334
+ d150b8d98ecccf36.46f82ac6476a316b.55d896310ec5696a.2888082595b7f10b
+ 2b62e301b3c8973b
+
+VPSADBW_128(reg)
+ before
+ 95e8381728e812a4.5df8636a736703bd.719e83b2bd117a81.a582bd3dbfb16beb
+ c36802d593a4a0f2.05b6f43816ebab6e.f2d813cf994e7767.649c4bcf5f3f4141
+ 112c3ea68d877ad2.a756e82e92638075.24f0d68878ab63c9.6df1bed30b7ba898
+ db81e6f6b51ddff0.1da4b93803db41ff.6534c94bf6b77c52.9e4f9136de725c1b
+ d18040e3f52f18f7
+ after
+ 0000000000000000.0000000000000000.00000000000002e4.0000000000000223
+ c36802d593a4a0f2.05b6f43816ebab6e.f2d813cf994e7767.649c4bcf5f3f4141
+ 112c3ea68d877ad2.a756e82e92638075.24f0d68878ab63c9.6df1bed30b7ba898
+ db81e6f6b51ddff0.1da4b93803db41ff.6534c94bf6b77c52.9e4f9136de725c1b
+ d18040e3f52f18f7
+VPSADBW_128(mem)
+ before
+ e45148c56bbf9958.7eb3f831a4f309f7.456ce5428660a838.10eee683aefbfcaf
+ b18e23ca5d2c9b69.540e6fc3f8943594.fa79e73937fd724b.806b2b9c3c051f8c
+ 16034fdde685da56.badd47184d8c9f72.17993b0730be5b65.13f693023d602394
+ ed7b47ea22d3114d.0c6e7d9c3e68833e.79965e9990b01eb2.24dd1a224c994274
+ 0e6abd66063bb9d7
+ after
+ e45148c56bbf9958.7eb3f831a4f309f7.456ce5428660a838.10eee683aefbfcaf
+ b18e23ca5d2c9b69.540e6fc3f8943594.fa79e73937fd724b.806b2b9c3c051f8c
+ 0000000000000000.0000000000000000.0000000000000202.000000000000042f
+ ed7b47ea22d3114d.0c6e7d9c3e68833e.79965e9990b01eb2.24dd1a224c994274
+ 0e6abd66063bb9d7
+
+VPSIGNB_128(reg)
+ before
+ 2feb773b06d2c36a.14c488dd2e24fd77.a60b0bbc67b31ca4.fd3dcbdc70de795d
+ e1aa440ee9eb9ed8.65a88ca226835a03.e402efe265f9a74f.7d5afebaef552592
+ 82f4204a4a1184ce.bdf4d12524fce31b.229d247cd4c75fec.d7b873212620e17f
+ 6c14075ac6d0b1f8.f974d252479c55ec.bc28a7f44fa88226.e525a6fc334b674e
+ 846b143732e2742b
+ after
+ 0000000000000000.0000000000000000.e4feefe29b07a7b1.83a6febaef55db92
+ e1aa440ee9eb9ed8.65a88ca226835a03.e402efe265f9a74f.7d5afebaef552592
+ 82f4204a4a1184ce.bdf4d12524fce31b.229d247cd4c75fec.d7b873212620e17f
+ 6c14075ac6d0b1f8.f974d252479c55ec.bc28a7f44fa88226.e525a6fc334b674e
+ 846b143732e2742b
+VPSIGNB_128(mem)
+ before
+ 905838be3ef2c443.fc58f6acf8b56301.f3f40b16a96e6ca1.0ef172b872294aaa
+ e6b68e7d748613c2.8f0be8ab7c4bd496.8840f95b667fe467.74438333dad5f424
+ 60529260efab1cd3.7f78d9c3ef1e4163.9423160f9bda7869.4969d5d12238bb3f
+ dbf7c053cb6c9ca3.29ecc560edbbe613.f46be01d638be5d4.ebb064fee7dedca7
+ b5652c26c454930a
+ after
+ 905838be3ef2c443.fc58f6acf8b56301.f3f40b16a96e6ca1.0ef172b872294aaa
+ e6b68e7d748613c2.8f0be8ab7c4bd496.8840f95b667fe467.74438333dad5f424
+ 0000000000000000.0000000000000000.78c0f95b9a7fe499.74bd83cddad5f4dc
+ dbf7c053cb6c9ca3.29ecc560edbbe613.f46be01d638be5d4.ebb064fee7dedca7
+ b5652c26c454930a
+
+VPSIGNB_128(reg)
+ before
+ 03d12ab556251c12.3373954225d54e5d.eab3a9ee11adfe52.82e2d270db9fe7d4
+ 3043591838deb36b.44908c1a19f3f02e.1c197fd9f780c6ce.1b5568f61e213994
+ 9a06b5b9070a93c2.ea1c21c5c2d13c42.1c6a458e3cc17a30.9b901f9a491d9941
+ 9c653a065e35f8c3.01e1d0313c7beec4.46f1f7777cfb5527.de5e7248779fc006
+ c08dddecc5b46d10
+ after
+ 0000000000000000.0000000000000000.1c197f27f780c6ce.e5ab680a1e21c794
+ 3043591838deb36b.44908c1a19f3f02e.1c197fd9f780c6ce.1b5568f61e213994
+ 9a06b5b9070a93c2.ea1c21c5c2d13c42.1c6a458e3cc17a30.9b901f9a491d9941
+ 9c653a065e35f8c3.01e1d0313c7beec4.46f1f7777cfb5527.de5e7248779fc006
+ c08dddecc5b46d10
+VPSIGNB_128(mem)
+ before
+ 1de7dc734e685a8b.91aee569d9eb2019.65ac1649a4fdc4e1.f6fc8f0251ba945d
+ d13aebc72ec545a2.d72bb05016b94571.f2496ef8156478c4.88d50a9a5a8b737e
+ b85087d682d9e782.c8299926ae2ba477.8483542cacbcc79a.58c965aa30f92e38
+ aef62b8a66afff56.c2f49b573fcb79d6.f72844d0840f6d8f.c3249ba072900034
+ 2332a9e7b9dd2621
+ after
+ 1de7dc734e685a8b.91aee569d9eb2019.65ac1649a4fdc4e1.f6fc8f0251ba945d
+ d13aebc72ec545a2.d72bb05016b94571.f2496ef8156478c4.88d50a9a5a8b737e
+ 0000000000000000.0000000000000000.f2b76ef8eb9c883c.782bf69a5a758d7e
+ aef62b8a66afff56.c2f49b573fcb79d6.f72844d0840f6d8f.c3249ba072900034
+ 2332a9e7b9dd2621
+
+VPSIGNB_128(reg)
+ before
+ d43e89eba46bdca9.8ff753d1f554474b.20d7b34f6527ff3b.2702bad0ba6b25ce
+ 34963918ccc75e78.36217b954bd37c8d.3d20db7abaca7451.f0de331969dcac84
+ 9e84b4dad07be73c.813e1fc485385a47.76191144dd4111c5.2e892a95ae6cbedc
+ 6e55f69e4915b49e.4b1cbc49be909ca5.2810501968171542.bccc1b31a4291703
+ 787682da681f7224
+ after
+ 0000000000000000.0000000000000000.3d20db7a46ca74af.f02233e797dc547c
+ 34963918ccc75e78.36217b954bd37c8d.3d20db7abaca7451.f0de331969dcac84
+ 9e84b4dad07be73c.813e1fc485385a47.76191144dd4111c5.2e892a95ae6cbedc
+ 6e55f69e4915b49e.4b1cbc49be909ca5.2810501968171542.bccc1b31a4291703
+ 787682da681f7224
+VPSIGNB_128(mem)
+ before
+ 3d52dc7a15588c6c.0055fbced521004d.7085cd1013e6ffd5.ad4f9466f7d8ba75
+ e72ba4ffc7e22007.b0d0c0d8102a09f3.cb46ce059f463f01.6323da9527113d0a
+ 51ce55549bc9ec21.da123f2695bc093c.3a2b3b147fbd1855.a4d71c14934ddaac
+ 59086e64ad17aae4.d966762600633dd5.98ff912ace5645fe.cdb9584dd818cd08
+ 3a1389ae91ff51c9
+ after
+ 3d52dc7a15588c6c.0055fbced521004d.7085cd1013e6ffd5.ad4f9466f7d8ba75
+ e72ba4ffc7e22007.b0d0c0d8102a09f3.cb46ce059f463f01.6323da9527113d0a
+ 0000000000000000.0000000000000000.cbba32059fbac1ff.9d232695d9efc30a
+ 59086e64ad17aae4.d966762600633dd5.98ff912ace5645fe.cdb9584dd818cd08
+ 3a1389ae91ff51c9
+
+VPSIGNW_128(reg)
+ before
+ 4833aca25b8da39c.d9a2681d18da177f.0b1a6143eeace06a.c0904b31a91e8328
+ 5163bb95d14efe2d.af6bc16af81eee1c.cb78fae9fb232fa6.90a8e5172b1f8efe
+ b2f0b4f390cfa027.b62ef4376aeeede8.75cd3f83c1526636.e215dbc6716721ad
+ c7269228339bc337.c9b67d718956ce0e.64652b80dfc7c1c6.94a1aa2c9602f961
+ 8019cc34b7fbd245
+ after
+ 0000000000000000.0000000000000000.cb78fae904dd2fa6.6f581ae92b1f8efe
+ 5163bb95d14efe2d.af6bc16af81eee1c.cb78fae9fb232fa6.90a8e5172b1f8efe
+ b2f0b4f390cfa027.b62ef4376aeeede8.75cd3f83c1526636.e215dbc6716721ad
+ c7269228339bc337.c9b67d718956ce0e.64652b80dfc7c1c6.94a1aa2c9602f961
+ 8019cc34b7fbd245
+VPSIGNW_128(mem)
+ before
+ 8448bfc9ef5e6886.ec5051a0563fa309.c6d1d80272624dbb.f68cba49ef0d7c01
+ 7afcfed95a37764f.7dbceec796457e48.874981d7401f281a.858de84b8db1d294
+ 40ff064f1593b9cd.d6b4630a8f3b8ea0.e9ebf5dd10981958.6fb6b2f2563e002a
+ b01f51173c7ded2b.5385aed3dcad10be.c983affefddadda1.0e5112abe5404170
+ c0ab06e0d744d211
+ after
+ 8448bfc9ef5e6886.ec5051a0563fa309.c6d1d80272624dbb.f68cba49ef0d7c01
+ 7afcfed95a37764f.7dbceec796457e48.874981d7401f281a.858de84b8db1d294
+ 0000000000000000.0000000000000000.78b77e29401f281a.7a7317b5724fd294
+ b01f51173c7ded2b.5385aed3dcad10be.c983affefddadda1.0e5112abe5404170
+ c0ab06e0d744d211
+
+VPSIGNW_128(reg)
+ before
+ df108affc7d5efba.a7265d1eea02cd96.507bca901926404e.01dc2b2824ef2f20
+ c9cc9873517fd417.02e1a54e3b2c163a.29e2b4abe33259fb.6ec4e646a0e5cd02
+ d82a2ea713cebdd3.9b1ca5944c0a8442.3a066692d55d9872.ed055a448ec87173
+ 69784609a64fe59b.4fa2d9dd38a5d3db.df33deb08c34395f.586d050e09a3d89e
+ 8cc662902d82bdaf
+ after
+ 0000000000000000.0000000000000000.29e2b4ab1ccea605.913ce6465f1bcd02
+ c9cc9873517fd417.02e1a54e3b2c163a.29e2b4abe33259fb.6ec4e646a0e5cd02
+ d82a2ea713cebdd3.9b1ca5944c0a8442.3a066692d55d9872.ed055a448ec87173
+ 69784609a64fe59b.4fa2d9dd38a5d3db.df33deb08c34395f.586d050e09a3d89e
+ 8cc662902d82bdaf
+VPSIGNW_128(mem)
+ before
+ 65ddedb61772ddd4.d900df04a88e891b.fa41be141c0bbe30.74b41771a442776d
+ c07d236ce37df436.820ff204b515e4fe.79c3cf241347026e.54d60d41b7149049
+ 77747e9eacb2be04.c1f17c76687234f0.a6f588fb3a665bc1.dde5bc8c6435be9e
+ 678c7c398e1af668.f3f27ac45d31b39f.5ea36584ac738454.6a2d21be44313d19
+ 57fa3744f6944b66
+ after
+ 65ddedb61772ddd4.d900df04a88e891b.fa41be141c0bbe30.74b41771a442776d
+ c07d236ce37df436.820ff204b515e4fe.79c3cf241347026e.54d60d41b7149049
+ 0000000000000000.0000000000000000.863d30dc1347fd92.54d60d4148ec9049
+ 678c7c398e1af668.f3f27ac45d31b39f.5ea36584ac738454.6a2d21be44313d19
+ 57fa3744f6944b66
+
+VPSIGNW_128(reg)
+ before
+ ff98fa8813eb2230.6c939827a6c3598e.725ee75b31dc9db4.7d99e3ab867a3b54
+ c05266f839c1ff24.62534f5610b8a3a4.9b81bfa87f0230de.dfa37d5ce38739ec
+ f57578fe04a31ded.25991bb1e7068fd3.caa6ff15e42ca6c7.608cae83e0a73d49
+ f94e2a080f1cba38.91317a2347b8db4a.5b1aa110fce83c1b.dc22f50c98e60197
+ 2f2fcbe4274e4301
+ after
+ 0000000000000000.0000000000000000.647f405880fecf22.dfa382a41c7939ec
+ c05266f839c1ff24.62534f5610b8a3a4.9b81bfa87f0230de.dfa37d5ce38739ec
+ f57578fe04a31ded.25991bb1e7068fd3.caa6ff15e42ca6c7.608cae83e0a73d49
+ f94e2a080f1cba38.91317a2347b8db4a.5b1aa110fce83c1b.dc22f50c98e60197
+ 2f2fcbe4274e4301
+VPSIGNW_128(mem)
+ before
+ 3580aef5aaedbcb4.2a277a81f7b810b0.82e6e79a4dda4133.aa29a30461c12e88
+ cae1182d3dcf2bdb.e24c63d556045b02.d486de0114797dba.131f005cb243b7b7
+ ca1e8776fbfe4aa3.7f0be270cb8bd9da.63dbdc44b9a04d0c.f248b48688fb1457
+ 100377be0088d638.5baff1bef0d9c4e3.0ab25b50575b6b55.a3f0bced82748112
+ 826212fe393a3994
+ after
+ 3580aef5aaedbcb4.2a277a81f7b810b0.82e6e79a4dda4133.aa29a30461c12e88
+ cae1182d3dcf2bdb.e24c63d556045b02.d486de0114797dba.131f005cb243b7b7
+ 0000000000000000.0000000000000000.2b7a21ff14797dba.ece1ffa4b243b7b7
+ 100377be0088d638.5baff1bef0d9c4e3.0ab25b50575b6b55.a3f0bced82748112
+ 826212fe393a3994
+
+VPSIGND_128(reg)
+ before
+ ebebb4234bda7a8b.7a5b62f069798bc5.d4838e2b617a59ca.a7d8d90f0bb794c1
+ 3ad89dc954df7da0.e3f3c6f852db2477.44d4b423bbfbd33b.1516d16ef0bf837b
+ cb73ca5cefd68182.27971ec2d5bc5e79.08ee5f129ae870e1.303bc05a227ff5af
+ fa083549b94ac1db.2113e63a1128f5f8.7d1d8c6598cb6a68.d31220bdbe04a68a
+ dc666f85e0595238
+ after
+ 0000000000000000.0000000000000000.44d4b42344042cc5.1516d16ef0bf837b
+ 3ad89dc954df7da0.e3f3c6f852db2477.44d4b423bbfbd33b.1516d16ef0bf837b
+ cb73ca5cefd68182.27971ec2d5bc5e79.08ee5f129ae870e1.303bc05a227ff5af
+ fa083549b94ac1db.2113e63a1128f5f8.7d1d8c6598cb6a68.d31220bdbe04a68a
+ dc666f85e0595238
+VPSIGND_128(mem)
+ before
+ 2604289da38ab4e4.23e5dcfb4dc77857.af339a4c1f29a51f.fdad36865432fd7e
+ 8cb9c7f023a48abb.a155badd47d9e2a3.acc3b7e41ecd291c.e5ea58e367a967cc
+ ec4ec86c7db28de9.d2a3cb5d440d3d6b.f38fb8ef27203e18.921ff1e770bae201
+ 2192a8fccdc07c99.111c0ce6e0eec35a.62621957592ca042.5e99fafe08f3abc7
+ a6a57093cde0fecb
+ after
+ 2604289da38ab4e4.23e5dcfb4dc77857.af339a4c1f29a51f.fdad36865432fd7e
+ 8cb9c7f023a48abb.a155badd47d9e2a3.acc3b7e41ecd291c.e5ea58e367a967cc
+ 0000000000000000.0000000000000000.533c481c1ecd291c.1a15a71d67a967cc
+ 2192a8fccdc07c99.111c0ce6e0eec35a.62621957592ca042.5e99fafe08f3abc7
+ a6a57093cde0fecb
+
+VPSIGND_128(reg)
+ before
+ c68d50145b0c16b8.0650e28d2edb11f7.b90c77e4b509b11d.d309560acd000ac4
+ 1a9d95ed4d03303b.7953f209bc0e0931.28bf0ac362e94360.2450ebf2a1a539ca
+ fe233b88405188ff.5469545d94662071.b981c0ef811ab4ce.2f0355fdf129e981
+ ce6a3f52cf8359b1.755c8575d1ee11e3.c79d96d4ae294114.d2ee0f16d897d615
+ e7dc952972fbbbb1
+ after
+ 0000000000000000.0000000000000000.d740f53d9d16bca0.2450ebf25e5ac636
+ 1a9d95ed4d03303b.7953f209bc0e0931.28bf0ac362e94360.2450ebf2a1a539ca
+ fe233b88405188ff.5469545d94662071.b981c0ef811ab4ce.2f0355fdf129e981
+ ce6a3f52cf8359b1.755c8575d1ee11e3.c79d96d4ae294114.d2ee0f16d897d615
+ e7dc952972fbbbb1
+VPSIGND_128(mem)
+ before
+ 4c9b6322dc625582.e6bd9bb79624e0fd.b6f9ff3e90b29ab4.b06186df86a126dd
+ dbf5f6ed32d760b3.a2694d2432c0598e.f40c40a2ecbe7410.ce178e7aa40e9fd6
+ 71b7c9768f679771.5eba50033fe40011.0c61c48f021f5e22.7f0ca913a5fce7aa
+ ebad58aa0f1db7e8.76fca1c2581b1031.d8c305f0ede01217.1d8cd31424f83b06
+ 06e309ebbd8ed796
+ after
+ 4c9b6322dc625582.e6bd9bb79624e0fd.b6f9ff3e90b29ab4.b06186df86a126dd
+ dbf5f6ed32d760b3.a2694d2432c0598e.f40c40a2ecbe7410.ce178e7aa40e9fd6
+ 0000000000000000.0000000000000000.0bf3bf5e13418bf0.31e871865bf1602a
+ ebad58aa0f1db7e8.76fca1c2581b1031.d8c305f0ede01217.1d8cd31424f83b06
+ 06e309ebbd8ed796
+
+VPSIGND_128(reg)
+ before
+ 945d45030e48f605.23a31f73cf057c43.467b3acc19f2c69b.35ff80b1c90e4d1a
+ 244585c8b0b4d600.f6659abfea2ba2af.2a82198d1ff35efa.00e2b2beb4b3cb58
+ 13e8c4a6415eb033.40be46787d9ce458.7e5f397105ad14fc.13361603c7de48fd
+ bb93fe095dd0c349.de7c9e8ca363ff69.9e5c96e468a9234a.4bc8296c20987f34
+ 846365e5dbef2d2a
+ after
+ 0000000000000000.0000000000000000.2a82198d1ff35efa.00e2b2be4b4c34a8
+ 244585c8b0b4d600.f6659abfea2ba2af.2a82198d1ff35efa.00e2b2beb4b3cb58
+ 13e8c4a6415eb033.40be46787d9ce458.7e5f397105ad14fc.13361603c7de48fd
+ bb93fe095dd0c349.de7c9e8ca363ff69.9e5c96e468a9234a.4bc8296c20987f34
+ 846365e5dbef2d2a
+VPSIGND_128(mem)
+ before
+ 9ad5485a13ee0d0a.7990305d9f9849ee.aa691ee6798daf0e.e6c62d52e375c893
+ 69e94db8e4a2dd02.a92c550ea3427fcf.815242711a25af74.b1e9f827139c3f81
+ cd6af0e96b16573b.a8b269890658a198.3f03871ba337bdc7.5d11f5cf93abc3c0
+ a225addbc35637e3.d07068386368ebf5.c04767cf2fd09233.45891fb7002c91fd
+ c49f7249f5aee5e4
+ after
+ 9ad5485a13ee0d0a.7990305d9f9849ee.aa691ee6798daf0e.e6c62d52e375c893
+ 69e94db8e4a2dd02.a92c550ea3427fcf.815242711a25af74.b1e9f827139c3f81
+ 0000000000000000.0000000000000000.7eadbd8f1a25af74.4e1607d9ec63c07f
+ a225addbc35637e3.d07068386368ebf5.c04767cf2fd09233.45891fb7002c91fd
+ c49f7249f5aee5e4
+
+VPMULHRSW_128(reg)
+ before
+ 389debf30ebafb20.c4e60179096f3b26.7eb04e8957fe9891.e0ec607adbfbede3
+ fcd08420e8de0e5e.0f7966af596c1d2f.0ebf18e67ea5e518.7bbced06c2c48803
+ 6b843b3b1fa55b4a.5fa95a68cd599a2b.dceac1bd72e90d38.6d858b60013721c0
+ e3050cb24e9c1d8f.9044599284436e46.447a4579d2564e9a.9211b475b3617146
+ c62de62ff44e37c1
+ after
+ 0000000000000000.0000000000000000.fbf5f3e471b1fd39.69df114aff6be05d
+ fcd08420e8de0e5e.0f7966af596c1d2f.0ebf18e67ea5e518.7bbced06c2c48803
+ 6b843b3b1fa55b4a.5fa95a68cd599a2b.dceac1bd72e90d38.6d858b60013721c0
+ e3050cb24e9c1d8f.9044599284436e46.447a4579d2564e9a.9211b475b3617146
+ c62de62ff44e37c1
+VPMULHRSW_128(mem)
+ before
+ e5a49c7ce1082d5b.be9ff1f0114e92da.7e14dd19973454ab.a2bea0863779e2ed
+ ca445347959d1043.5a9ee7610547f4d6.05e764e7253b0987.5201ce5040dd06db
+ 53d8857b2d199ca3.114deb72c6148030.018769e947614905.b08ecc43860ef510
+ 5b2bb006c5868ca8.40f9f88def407293.4ec0680b1bb4d052.18b395cba799ec39
+ e6ba25543f092702
+ after
+ e5a49c7ce1082d5b.be9ff1f0114e92da.7e14dd19973454ab.a2bea0863779e2ed
+ ca445347959d1043.5a9ee7610547f4d6.05e764e7253b0987.5201ce5040dd06db
+ 0000000000000000.0000000000000000.05d0e47de185064d.c44125101c1cfe71
+ 5b2bb006c5868ca8.40f9f88def407293.4ec0680b1bb4d052.18b395cba799ec39
+ e6ba25543f092702
+
+VPMULHRSW_128(reg)
+ before
+ 76f0784be9ebe217.be0a4fd378f29d7d.44ee0b1f1c5705ac.c760dd3abd40599a
+ 24a18b1a42ca5823.5741dece62698b4f.77781e95eae67627.4a3244604810a108
+ 4b18592fe532c6d2.049cd9e4a0f5124a.36e32f59f47801af.b2011a6bd93063c9
+ 49a3def56eaf68d1.a0e7bdff4da4ed99.de7a39d9d799e1f1.da9ada468bac5d08
+ a0ca00dd7a9149f2
+ after
+ 0000000000000000.0000000000000000.333a0b5001e7018e.d2ca0e1dea26b5f7
+ 24a18b1a42ca5823.5741dece62698b4f.77781e95eae67627.4a3244604810a108
+ 4b18592fe532c6d2.049cd9e4a0f5124a.36e32f59f47801af.b2011a6bd93063c9
+ 49a3def56eaf68d1.a0e7bdff4da4ed99.de7a39d9d799e1f1.da9ada468bac5d08
+ a0ca00dd7a9149f2
+VPMULHRSW_128(mem)
+ before
+ df5b091bc3eae4b2.798c16d77ace7acc.06ed050c8682d969.c98b38802ed65398
+ 72196fee81c3e975.3620fd43a41a376e.147b2df8669a92e5.546028b996ba9351
+ 37d2b042d1291667.deab90a48920dc64.a55eb1ad09f8d33a.db4606f2aad1ddc8
+ 08504701cf2725b3.cc79ca66c56ba55a.94600d198ca85993.ba89cc9606a86ca8
+ 4e75781148ca7d9e
+ after
+ df5b091bc3eae4b2.798c16d77ace7acc.06ed050c8682d969.c98b38802ed65398
+ 72196fee81c3e975.3620fd43a41a376e.147b2df8669a92e5.546028b996ba9351
+ 0000000000000000.0000000000000000.011c01d09e9d20e5.dc1a11fad97bb905
+ 08504701cf2725b3.cc79ca66c56ba55a.94600d198ca85993.ba89cc9606a86ca8
+ 4e75781148ca7d9e
+
+VPMULHRSW_128(reg)
+ before
+ f15606d009c34c55.c361b11895c9d286.5bd6a7f5f387cdfb.bf4ebe270bb7e01d
+ 0077703de720147a.42cf6873421cdb0c.e90e23beaf0191f4.00f33fc3a1302404
+ d726b4c57e6c13b9.6267eaffef2bfa70.d16c3b2b96632df0.341d0cd86b1fe073
+ d2adccd5693483bd.00f5b2a7bb03ecdf.6e3deaa9433cdd9c.3896a1558491d197
+ e62c7b230891b39c
+ after
+ 0000000000000000.0000000000000000.0859108642d5d881.00630666b0a7f71f
+ 0077703de720147a.42cf6873421cdb0c.e90e23beaf0191f4.00f33fc3a1302404
+ d726b4c57e6c13b9.6267eaffef2bfa70.d16c3b2b96632df0.341d0cd86b1fe073
+ d2adccd5693483bd.00f5b2a7bb03ecdf.6e3deaa9433cdd9c.3896a1558491d197
+ e62c7b230891b39c
+VPMULHRSW_128(mem)
+ before
+ 1ba9152f142c41ad.4d59b7d74402a033.f6453c56bfaf6c84.1ece2ca55315dca3
+ b4daeb65c36d38f6.a4766e39ac65a8c6.222204fa1a3b388c.3b68fd8a617c67b2
+ 8b8b79b2326054a5.3350ee663ce6d523.5e59877ee5b30a22.225a59c309fdba75
+ 7d873b007d1151e3.553234ca911363f6.87b740ce3e249f73.30ef3dbee8221097
+ bf72a4e69a79a6c5
+ after
+ 1ba9152f142c41ad.4d59b7d74402a033.f6453c56bfaf6c84.1ece2ca55315dca3
+ b4daeb65c36d38f6.a4766e39ac65a8c6.222204fa1a3b388c.3b68fd8a617c67b2
+ 0000000000000000.0000000000000000.fd680259f2d22ff0.0e4cff243f46e35a
+ 7d873b007d1151e3.553234ca911363f6.87b740ce3e249f73.30ef3dbee8221097
+ bf72a4e69a79a6c5
+
+VBROADCASTF128(reg)
+ before
+ 2c318aa7ba8eb8ab.679cae3dbe8deadf.68693bd1467790ea.7906abd64199b2ab
+ d476eb6de5eb82f4.23944d5314e0dcc3.c742ffe7f89e96ac.10134482091f00f5
+ 118ec4a4b61e3f4c.8e3c94309814e3bb.ce077d784315b2e7.29a987beb2c1457e
+ 40c50fb8c9b32c60.8460ffbf6937baf5.d905aff0c1672048.9e96f177598b3d71
+ 4ca5fd971a8aa3fb
+ after
+ 2c318aa7ba8eb8ab.679cae3dbe8deadf.68693bd1467790ea.7906abd64199b2ab
+ d476eb6de5eb82f4.23944d5314e0dcc3.c742ffe7f89e96ac.10134482091f00f5
+ 118ec4a4b61e3f4c.8e3c94309814e3bb.ce077d784315b2e7.29a987beb2c1457e
+ 40c50fb8c9b32c60.8460ffbf6937baf5.d905aff0c1672048.9e96f177598b3d71
+ 4ca5fd971a8aa3fb
+VBROADCASTF128(mem)
+ before
+ 0fa1270c10c83448.bd67ca16bb3485dc.e1cc0beca0541f9a.438893bb10211b7b
+ c357ebc05754ac83.e5bff028272f856c.814c32a35b78cbd9.6adb2446cccee02b
+ 4493c6a10c37c6d9.121b7e5caa306abb.40abf2d0b6ae7ddc.a94c5efb90faab04
+ 6e21339a4a7f4075.a1c56e1ddfc16d75.fab7c65fcc02efcf.5b253e48f932b8b4
+ deb3bf98a20142e5
+ after
+ 0fa1270c10c83448.bd67ca16bb3485dc.e1cc0beca0541f9a.438893bb10211b7b
+ c357ebc05754ac83.e5bff028272f856c.814c32a35b78cbd9.6adb2446cccee02b
+ 4493c6a10c37c6d9.121b7e5caa306abb.40abf2d0b6ae7ddc.a94c5efb90faab04
+ e1cc0beca0541f9a.438893bb10211b7b.e1cc0beca0541f9a.438893bb10211b7b
+ deb3bf98a20142e5
+
+VBROADCASTF128(reg)
+ before
+ 8c42dd5627f38643.1dccae972e38d484.ee0abed66371cd48.8b3a2b3dba81dfe0
+ c31e94f02594c07b.2d62b384d36c3e32.553669f5d2c9c4dd.cf019b549b360638
+ dd93e0d138712b39.7aadbe4d56293caa.32956be5c6578fe3.a2d894928b2d2306
+ 38ecbe65fb160428.df7b4cded27a8819.e172c112dda66a04.e08b91e1a773f074
+ 65e60e2f0b122aae
+ after
+ 8c42dd5627f38643.1dccae972e38d484.ee0abed66371cd48.8b3a2b3dba81dfe0
+ c31e94f02594c07b.2d62b384d36c3e32.553669f5d2c9c4dd.cf019b549b360638
+ dd93e0d138712b39.7aadbe4d56293caa.32956be5c6578fe3.a2d894928b2d2306
+ 38ecbe65fb160428.df7b4cded27a8819.e172c112dda66a04.e08b91e1a773f074
+ 65e60e2f0b122aae
+VBROADCASTF128(mem)
+ before
+ 0cb48867d1198de1.2e7728180a0d87f5.3a96d823646cdfaa.be1b66e8b34291ec
+ b3c27a751891d439.1d7e1c5702e4f04c.66cade08270afc8a.25da56d3e3b83f48
+ 35dd6045fa89bce1.5f4e968c7e277ad8.3fe5da7a38609ce4.72fc8d400a93b1c4
+ 6ecfb6c3930a0106.513390241b606245.a1b24963b27b7be6.01cd0799c360230c
+ 2d99c14caba9d0ca
+ after
+ 0cb48867d1198de1.2e7728180a0d87f5.3a96d823646cdfaa.be1b66e8b34291ec
+ b3c27a751891d439.1d7e1c5702e4f04c.66cade08270afc8a.25da56d3e3b83f48
+ 35dd6045fa89bce1.5f4e968c7e277ad8.3fe5da7a38609ce4.72fc8d400a93b1c4
+ 3a96d823646cdfaa.be1b66e8b34291ec.3a96d823646cdfaa.be1b66e8b34291ec
+ 2d99c14caba9d0ca
+
+VBROADCASTF128(reg)
+ before
+ 54acb5c35dfdf5ad.3964f8db00225fd4.5079088c741de441.67fca6b1b16655b9
+ d151e16c75e5ce5f.746aa3795cdc9176.b66bf92f26ea3b75.6f906d4f522ee58c
+ 00d541b290ef968d.f9ac318ac4445419.e0575f78cc51a490.943b1a29b1dde889
+ 3c85cf0149a68be2.a6f520f8536764e8.2a8736d503e05b3c.b1c7292be9811adc
+ a4001741162637b2
+ after
+ 54acb5c35dfdf5ad.3964f8db00225fd4.5079088c741de441.67fca6b1b16655b9
+ d151e16c75e5ce5f.746aa3795cdc9176.b66bf92f26ea3b75.6f906d4f522ee58c
+ 00d541b290ef968d.f9ac318ac4445419.e0575f78cc51a490.943b1a29b1dde889
+ 3c85cf0149a68be2.a6f520f8536764e8.2a8736d503e05b3c.b1c7292be9811adc
+ a4001741162637b2
+VBROADCASTF128(mem)
+ before
+ 47b45f5755d7fa37.e3ab89c43d97e70b.5612ecb126507c10.f1487bb166239c26
+ 78ad7d59c1a02096.50946a6a084de6b4.e4cf0fa0580b59bc.8fe6287892a4a2f9
+ 11b9ed33778d65fc.de8b6e5c4454c688.2ef807b005a5b71a.61ad3b9622f1aa62
+ f0a22bd292ab8495.ebde91079038c133.0e594fcf4a295253.c3e9b077b396f00c
+ 11e58188e01eb0a4
+ after
+ 47b45f5755d7fa37.e3ab89c43d97e70b.5612ecb126507c10.f1487bb166239c26
+ 78ad7d59c1a02096.50946a6a084de6b4.e4cf0fa0580b59bc.8fe6287892a4a2f9
+ 11b9ed33778d65fc.de8b6e5c4454c688.2ef807b005a5b71a.61ad3b9622f1aa62
+ 5612ecb126507c10.f1487bb166239c26.5612ecb126507c10.f1487bb166239c26
+ 11e58188e01eb0a4
+
+VPEXTRW_128_0x0(reg)
+ before
+ a7eeac33451525d6.ef35b4202f053a8c.d1d7d0d786861463.61bd63e843a4e595
+ e1512ce67f078c4d.eb3e030b69a7430d.eec42539c2cafac2.04f2bfe70b202d0c
+ 1b58fd0b298120b5.c189947d5d9e5b45.9cef8e97e08eb1fc.d1c2e0b8beace6e4
+ b1501b10e00e1fbc.4be1e46426f53d60.39a5065f7e6073be.a6fa40477951cb48
+ 5d665d81581d9964
+ after
+ a7eeac33451525d6.ef35b4202f053a8c.d1d7d0d786861463.61bd63e843a4e595
+ e1512ce67f078c4d.eb3e030b69a7430d.eec42539c2cafac2.04f2bfe70b202d0c
+ 1b58fd0b298120b5.c189947d5d9e5b45.9cef8e97e08eb1fc.d1c2e0b8beace6e4
+ b1501b10e00e1fbc.4be1e46426f53d60.39a5065f7e6073be.a6fa40477951cb48
+ 000000000000e595
+VPEXTRW_128_0x0(mem)
+ before
+ d3d2b350751b0c66.ff848260403ac30c.66136dabe1b9a68a.1f328afc35cc7cb4
+ e40abca2ef58e078.61422f66e4924951.efecad3ea9f552ee.ace114d9a35c0a89
+ 6dd9f661e0ded0c6.33d41d9068a1ec39.c0361f099bb5fdb8.3a00a264649e57ea
+ 480ddc7b64bc997d.d088484969f4e96d.b6be3ff8d2066216.26d92f08131da082
+ cdb9b8314c6620ff
+ after
+ d3d2b350751b0c66.ff848260403ac30c.66136dabe1b9a68a.1f328afc35cc57ea
+ e40abca2ef58e078.61422f66e4924951.efecad3ea9f552ee.ace114d9a35c0a89
+ 6dd9f661e0ded0c6.33d41d9068a1ec39.c0361f099bb5fdb8.3a00a264649e57ea
+ 480ddc7b64bc997d.d088484969f4e96d.b6be3ff8d2066216.26d92f08131da082
+ cdb9b8314c6620ff
+
+VPEXTRW_128_0x0(reg)
+ before
+ 89ec374cac04150a.5270eadb98fbf7c9.96a8adfe82167c9c.ad4f8af76af23e32
+ b7beaac3cf83b951.67cf9c6d97a9a5d5.e08146195093e170.81b77af380884c38
+ b37b0c0350704980.63f66e1d7dd161ce.0a5e11076ef75395.0ec18dd62fd14a55
+ d96e5979cb560043.22b0ddd76880e4df.6f8d093578cf10b8.30383e8e94dbf2b5
+ c4e90a05cbb10083
+ after
+ 89ec374cac04150a.5270eadb98fbf7c9.96a8adfe82167c9c.ad4f8af76af23e32
+ b7beaac3cf83b951.67cf9c6d97a9a5d5.e08146195093e170.81b77af380884c38
+ b37b0c0350704980.63f66e1d7dd161ce.0a5e11076ef75395.0ec18dd62fd14a55
+ d96e5979cb560043.22b0ddd76880e4df.6f8d093578cf10b8.30383e8e94dbf2b5
+ 0000000000003e32
+VPEXTRW_128_0x0(mem)
+ before
+ a4a06b29ef6032ec.86e58d8fddc21b45.80cb648771c1ed35.6d582b0d0ca75185
+ ac29dfe51cf3421b.142aa5b3213ed632.59117f19b6a036fc.5f0d71fdc30955a7
+ ba4fe1256f76ed3d.e08a9c5034586db7.8950ab79532a7d5f.a0f6d96f3b8356cb
+ a9e0edd503f6ef7d.46516ed1b19c1b80.ec526294636a7b8b.8e605ed110a0919d
+ 8397fc8edded42c8
+ after
+ a4a06b29ef6032ec.86e58d8fddc21b45.80cb648771c1ed35.6d582b0d0ca756cb
+ ac29dfe51cf3421b.142aa5b3213ed632.59117f19b6a036fc.5f0d71fdc30955a7
+ ba4fe1256f76ed3d.e08a9c5034586db7.8950ab79532a7d5f.a0f6d96f3b8356cb
+ a9e0edd503f6ef7d.46516ed1b19c1b80.ec526294636a7b8b.8e605ed110a0919d
+ 8397fc8edded42c8
+
+VPEXTRW_128_0x0(reg)
+ before
+ dde7af123ef5a4f8.55a680e1f57e0309.a2cb17a435951d39.5ee42254026cefab
+ f69b74c9d044f5db.9a6f1435601ae60a.504394345bcfaf8d.bbd166a74d3d93ec
+ 2c00461f2f676e1b.540527bd61d754af.ac07dfeec0d60d28.dfe7aa7860e82479
+ d9632181f5e94e64.5f34346513c00922.1261f63cff3772b7.a5f16bb356795e80
+ ebba24434bfdfc2a
+ after
+ dde7af123ef5a4f8.55a680e1f57e0309.a2cb17a435951d39.5ee42254026cefab
+ f69b74c9d044f5db.9a6f1435601ae60a.504394345bcfaf8d.bbd166a74d3d93ec
+ 2c00461f2f676e1b.540527bd61d754af.ac07dfeec0d60d28.dfe7aa7860e82479
+ d9632181f5e94e64.5f34346513c00922.1261f63cff3772b7.a5f16bb356795e80
+ 000000000000efab
+VPEXTRW_128_0x0(mem)
+ before
+ 8c0f50165c7fbba6.5a0e0159c156cf63.96cab81a92e1c08f.dd9ed48bb57d1be6
+ 64bc6e18a40b571e.0c4ee2142d3b2ec4.d7922dc7fb473623.6b0a76477d354361
+ 4e8df73340ae8cbe.496ec11fd523a732.fd5711576afd260a.17f1d6ddf3e928d2
+ 284e69544b7315b3.6ebc99e4569a765a.e3e7dfb8fa0f4e6f.3d9ff2b8b42804e8
+ 395fc5435c7b144d
+ after
+ 8c0f50165c7fbba6.5a0e0159c156cf63.96cab81a92e1c08f.dd9ed48bb57d28d2
+ 64bc6e18a40b571e.0c4ee2142d3b2ec4.d7922dc7fb473623.6b0a76477d354361
+ 4e8df73340ae8cbe.496ec11fd523a732.fd5711576afd260a.17f1d6ddf3e928d2
+ 284e69544b7315b3.6ebc99e4569a765a.e3e7dfb8fa0f4e6f.3d9ff2b8b42804e8
+ 395fc5435c7b144d
+
+VPEXTRW_128_0x1(reg)
+ before
+ 667f4bec867093ae.cdca3e67e266af29.d88266d14b2dd6e7.670c13d5c78a687f
+ 2249811ece92beb6.18cef4592094164b.e10e245151670486.64932a9aee793166
+ c80a6145d16ed112.e727071422080546.e6aad0d003d43be3.b5479ef38be8644f
+ b30ee9cd2b8f086e.149ff18603ce3946.43a365bafd01b9a9.38f6edccb9e4bf67
+ c76a92119478fcd9
+ after
+ 667f4bec867093ae.cdca3e67e266af29.d88266d14b2dd6e7.670c13d5c78a687f
+ 2249811ece92beb6.18cef4592094164b.e10e245151670486.64932a9aee793166
+ c80a6145d16ed112.e727071422080546.e6aad0d003d43be3.b5479ef38be8644f
+ b30ee9cd2b8f086e.149ff18603ce3946.43a365bafd01b9a9.38f6edccb9e4bf67
+ 000000000000c78a
+VPEXTRW_128_0x1(mem)
+ before
+ 407109ae39b1d7d2.41a1142276819f75.7d03309adff36e76.5445df7bdc79b885
+ 7dd5cf90c39a0e7d.cd0edfb051d0d1d3.fc1e3f3cd3826002.75db3a7f3cc87422
+ 5c635fa14f3f5b07.b2a344e45509db36.6fbe9a58fb88ca18.02b37233b87b2b2d
+ b7e734cff8ac7b9c.4eaa412821b8f848.b0adbdda721069e2.57178401ed1d1752
+ d0546b56753a753c
+ after
+ 407109ae39b1d7d2.41a1142276819f75.7d03309adff36e76.5445df7bdc79b87b
+ 7dd5cf90c39a0e7d.cd0edfb051d0d1d3.fc1e3f3cd3826002.75db3a7f3cc87422
+ 5c635fa14f3f5b07.b2a344e45509db36.6fbe9a58fb88ca18.02b37233b87b2b2d
+ b7e734cff8ac7b9c.4eaa412821b8f848.b0adbdda721069e2.57178401ed1d1752
+ d0546b56753a753c
+
+VPEXTRW_128_0x1(reg)
+ before
+ c9b6239fef5f8198.6b2dcd04dbee2967.fb70d1ea4e6765b5.9cb925ae5426f98c
+ 9e89a847f5177611.5500a32e13102395.1741f0947ba45e2a.10ac4cc0bed63543
+ ab19f7b923ef9154.4f2e3438bd1f2352.fc699a9441fa1f53.e653b0fccc2dda33
+ 4cb20a6316720e0d.3681fa0ef425e6c9.0733cc553ef6e4db.fb7acc4f9936a487
+ 2bec1da341fe4f6c
+ after
+ c9b6239fef5f8198.6b2dcd04dbee2967.fb70d1ea4e6765b5.9cb925ae5426f98c
+ 9e89a847f5177611.5500a32e13102395.1741f0947ba45e2a.10ac4cc0bed63543
+ ab19f7b923ef9154.4f2e3438bd1f2352.fc699a9441fa1f53.e653b0fccc2dda33
+ 4cb20a6316720e0d.3681fa0ef425e6c9.0733cc553ef6e4db.fb7acc4f9936a487
+ 0000000000005426
+VPEXTRW_128_0x1(mem)
+ before
+ 53771ee6e190960d.dd9fdfb0692c28e7.e6c6739cd4312726.95ed81430e23e86f
+ 4de54a0394f83697.ba2d710cb9a91d8f.3cc91bce7a4ca396.00e1b5ca4c0d68ba
+ f6031fe57742eb36.3ea8bde3a17627b0.12566c9002841645.a55c645694419f69
+ 2a9d197aa57b7015.c75cbda2be1e82f7.4538e4cf87e43c5f.e1ab8b53834acb28
+ 0e17242db5b426a2
+ after
+ 53771ee6e190960d.dd9fdfb0692c28e7.e6c6739cd4312726.95ed81430e239441
+ 4de54a0394f83697.ba2d710cb9a91d8f.3cc91bce7a4ca396.00e1b5ca4c0d68ba
+ f6031fe57742eb36.3ea8bde3a17627b0.12566c9002841645.a55c645694419f69
+ 2a9d197aa57b7015.c75cbda2be1e82f7.4538e4cf87e43c5f.e1ab8b53834acb28
+ 0e17242db5b426a2
+
+VPEXTRW_128_0x1(reg)
+ before
+ 89ef2d51c50cec84.c57fb2ad3bae8361.b0956fb3ab2e6c10.b13dfe752579d00f
+ ae7ea2294fdd5b7a.a375686a54e8dd45.559fce8305311fa6.322f3670f94e8f81
+ d90f7d23f0b4ad2f.a04bb69d0c343dee.11c5d77f67b3d865.a4db08aa1e6f35e2
+ 66efbca9431b1f4f.98cc1833819e5d88.425584116e40d2fb.e30df111b1e97d5e
+ cb916c90cec72521
+ after
+ 89ef2d51c50cec84.c57fb2ad3bae8361.b0956fb3ab2e6c10.b13dfe752579d00f
+ ae7ea2294fdd5b7a.a375686a54e8dd45.559fce8305311fa6.322f3670f94e8f81
+ d90f7d23f0b4ad2f.a04bb69d0c343dee.11c5d77f67b3d865.a4db08aa1e6f35e2
+ 66efbca9431b1f4f.98cc1833819e5d88.425584116e40d2fb.e30df111b1e97d5e
+ 0000000000002579
+VPEXTRW_128_0x1(mem)
+ before
+ 3833f5138f15e756.b16a5929e5a0ed87.67c50a16cc33fb3e.4299d3a7b5654b12
+ 06be088613df7f29.17cc520e71cf5283.e90209330bfed03d.6fdebfacd8ae7d56
+ 11ff21d57332abc7.f261a3c484328bef.fa4f90775a0b9bb0.2470448c74a5a474
+ 35c3bdecce1a255c.9f7546b7b958d476.76781bcdd46716c4.bc9a5eb325d8fe18
+ 94aa0a8d86d2c5ed
+ after
+ 3833f5138f15e756.b16a5929e5a0ed87.67c50a16cc33fb3e.4299d3a7b56574a5
+ 06be088613df7f29.17cc520e71cf5283.e90209330bfed03d.6fdebfacd8ae7d56
+ 11ff21d57332abc7.f261a3c484328bef.fa4f90775a0b9bb0.2470448c74a5a474
+ 35c3bdecce1a255c.9f7546b7b958d476.76781bcdd46716c4.bc9a5eb325d8fe18
+ 94aa0a8d86d2c5ed
+
+VPEXTRW_128_0x2(reg)
+ before
+ 09ea4386332036a0.4dd457b73da1aa13.79533953adca68c4.39492620951dfea5
+ 75a7050ac94d8cdd.37ff6b23ded5f519.de487704fb168486.1e8d2e5eba390f7e
+ 362e4c86e3e5054f.ce0f751acdc2c39a.29a1fc3640c76468.0311ad725ec8047c
+ a6c814641e75dba2.eed2f28a2572d0c1.b6a8c45617694415.c3a221489ed59aca
+ 3a0a05cc956c8d95
+ after
+ 09ea4386332036a0.4dd457b73da1aa13.79533953adca68c4.39492620951dfea5
+ 75a7050ac94d8cdd.37ff6b23ded5f519.de487704fb168486.1e8d2e5eba390f7e
+ 362e4c86e3e5054f.ce0f751acdc2c39a.29a1fc3640c76468.0311ad725ec8047c
+ a6c814641e75dba2.eed2f28a2572d0c1.b6a8c45617694415.c3a221489ed59aca
+ 0000000000002620
+VPEXTRW_128_0x2(mem)
+ before
+ 4315d6ea609a9908.22c45a1215884a83.72125c5d03f3d8bb.e1a9ccce1c895f3a
+ bc910e8f1a6a7950.076d19fa65aa909e.389d3181825196b3.06f20f0cecb2f383
+ 80492ba5e0e8ea99.af0e4d8aa968e79f.1b3dece1be97c7d6.80ce897b2371399b
+ 6a08a819cd21a80e.77f5f22d7e4d8c31.f6bf0a69d4d1274f.ad8836865c51702f
+ e86d129b33ded2ea
+ after
+ 4315d6ea609a9908.22c45a1215884a83.72125c5d03f3d8bb.e1a9ccce1c89897b
+ bc910e8f1a6a7950.076d19fa65aa909e.389d3181825196b3.06f20f0cecb2f383
+ 80492ba5e0e8ea99.af0e4d8aa968e79f.1b3dece1be97c7d6.80ce897b2371399b
+ 6a08a819cd21a80e.77f5f22d7e4d8c31.f6bf0a69d4d1274f.ad8836865c51702f
+ e86d129b33ded2ea
+
+VPEXTRW_128_0x2(reg)
+ before
+ 8dc91a2545a59c79.589b01d8fe206edc.bb6c054f7fe5ba00.a7ee0605df0b724c
+ f7e849902d300a88.24ceb3cd8ef2f92f.d7c0815c49bdafba.08985ba1fc5263f6
+ 84169b48880e57c2.ac6d39e39aa10532.283c62c07760a508.f788872947b1b77c
+ 8e9f0cbaf2c8c0d3.ca440e083d3b4e12.082ea4e7a55bd999.4e890689da342a07
+ eb6852aed4e877c6
+ after
+ 8dc91a2545a59c79.589b01d8fe206edc.bb6c054f7fe5ba00.a7ee0605df0b724c
+ f7e849902d300a88.24ceb3cd8ef2f92f.d7c0815c49bdafba.08985ba1fc5263f6
+ 84169b48880e57c2.ac6d39e39aa10532.283c62c07760a508.f788872947b1b77c
+ 8e9f0cbaf2c8c0d3.ca440e083d3b4e12.082ea4e7a55bd999.4e890689da342a07
+ 0000000000000605
+VPEXTRW_128_0x2(mem)
+ before
+ a8f1e9824ed85be3.73ce995005ec8169.5c1fb12793cc8ffa.d4e1433d70388617
+ 63f046f36711928b.8df03c776005d62e.3cc99b2cb95f8517.e8a03c2f7485e92e
+ f631e5eb389ed8e9.3a51f39c9ca0face.470f4903cb00ec94.a0b88a274cce3e8c
+ 3e7f4258e08be82a.d43dba2a57482af6.5abd3899e4bb7f9e.58752993949ec1da
+ 6c2315dee981adc7
+ after
+ a8f1e9824ed85be3.73ce995005ec8169.5c1fb12793cc8ffa.d4e1433d70388a27
+ 63f046f36711928b.8df03c776005d62e.3cc99b2cb95f8517.e8a03c2f7485e92e
+ f631e5eb389ed8e9.3a51f39c9ca0face.470f4903cb00ec94.a0b88a274cce3e8c
+ 3e7f4258e08be82a.d43dba2a57482af6.5abd3899e4bb7f9e.58752993949ec1da
+ 6c2315dee981adc7
+
+VPEXTRW_128_0x2(reg)
+ before
+ 370e4b73e7033ffd.17a8da2578e47f79.b9008b8c2d89a252.4f9fe3d8209dfb61
+ 1781c5c028b1b328.5e76283e1eb65903.43e66430b9f09d8d.0381c6ad9cb11c08
+ 67ca81304b1645f5.edb6a88fee0c32f4.d03a408198085854.522f5e0573049ec0
+ 83337b2feabf3010.a134d60403f3c577.ba4a1beb655d0f52.197425cac2a13cb4
+ 321e99eaa494b311
+ after
+ 370e4b73e7033ffd.17a8da2578e47f79.b9008b8c2d89a252.4f9fe3d8209dfb61
+ 1781c5c028b1b328.5e76283e1eb65903.43e66430b9f09d8d.0381c6ad9cb11c08
+ 67ca81304b1645f5.edb6a88fee0c32f4.d03a408198085854.522f5e0573049ec0
+ 83337b2feabf3010.a134d60403f3c577.ba4a1beb655d0f52.197425cac2a13cb4
+ 000000000000e3d8
+VPEXTRW_128_0x2(mem)
+ before
+ 7af7355036eabf03.c709ad29a136b125.56bc2e8a7976cfb9.5e60f1dabc7cfe34
+ cdcc76e893ad1bb5.8f98158a0d0a04df.e8192d0b6da10be5.18c9beba3af060a6
+ 0769d69ed8ec8554.362cadbfc9c464ea.34194e74fb803728.45d17ff77b457253
+ 0499d35e20b0b60b.1a11733271f20ef3.14860db23e200dae.3fc32ffe1a0870e8
+ 63edca39b3c49611
+ after
+ 7af7355036eabf03.c709ad29a136b125.56bc2e8a7976cfb9.5e60f1dabc7c7ff7
+ cdcc76e893ad1bb5.8f98158a0d0a04df.e8192d0b6da10be5.18c9beba3af060a6
+ 0769d69ed8ec8554.362cadbfc9c464ea.34194e74fb803728.45d17ff77b457253
+ 0499d35e20b0b60b.1a11733271f20ef3.14860db23e200dae.3fc32ffe1a0870e8
+ 63edca39b3c49611
+
+VPEXTRW_128_0x3(reg)
+ before
+ 0d994d16e3051f79.a02ae81488076d07.96926351a21f3ea6.652de7af528d49a2
+ 9915b200455848cc.b7e691ac2bfc6474.05fc7786f8d82fae.03da565954d1a931
+ 63abf76276484cb7.259b4a13259c597d.c59cad3f0ea81fb8.ca59d89b5ffae786
+ c7a817aa116269e6.c613903393f2054f.30bc00e7811b4870.9676e8619013c0ce
+ 42fc02970229f035
+ after
+ 0d994d16e3051f79.a02ae81488076d07.96926351a21f3ea6.652de7af528d49a2
+ 9915b200455848cc.b7e691ac2bfc6474.05fc7786f8d82fae.03da565954d1a931
+ 63abf76276484cb7.259b4a13259c597d.c59cad3f0ea81fb8.ca59d89b5ffae786
+ c7a817aa116269e6.c613903393f2054f.30bc00e7811b4870.9676e8619013c0ce
+ 000000000000652d
+VPEXTRW_128_0x3(mem)
+ before
+ acb8a329d24732e6.21570e43b330d905.761bdefa910a2715.a4a86ceaecbee681
+ af7745031b79430e.cd06d999f741d9bf.117fb0523af179fc.7baeedb4eb1c3797
+ 27036611faccdfd8.27ff72187a1ea4c0.730a8229aab2b830.131980b11bc17560
+ f02981408a4bc271.8b90d72cd75577b5.778ad16afe59a0dc.c634204d1739dd86
+ f24cc9f47c11aab5
+ after
+ acb8a329d24732e6.21570e43b330d905.761bdefa910a2715.a4a86ceaecbe1319
+ af7745031b79430e.cd06d999f741d9bf.117fb0523af179fc.7baeedb4eb1c3797
+ 27036611faccdfd8.27ff72187a1ea4c0.730a8229aab2b830.131980b11bc17560
+ f02981408a4bc271.8b90d72cd75577b5.778ad16afe59a0dc.c634204d1739dd86
+ f24cc9f47c11aab5
+
+VPEXTRW_128_0x3(reg)
+ before
+ f1ad7713e6d51a9a.e6b4127ae802a705.55030442ab718e4a.fbc9170151f3ec2d
+ 20a32614ef0f67e1.e47296ad2ffe4bbf.e1a5f3c491fe252a.da94d2dac08b594e
+ dc7ad365364dce35.c82d88c37b4a69cb.8bc2a12025897702.f0b77de1672da36c
+ 7f7e7970551b8a43.6db364aae9f3bf57.afa50bc0049dc17e.18fe950260e686b3
+ 30359429cac1bd4e
+ after
+ f1ad7713e6d51a9a.e6b4127ae802a705.55030442ab718e4a.fbc9170151f3ec2d
+ 20a32614ef0f67e1.e47296ad2ffe4bbf.e1a5f3c491fe252a.da94d2dac08b594e
+ dc7ad365364dce35.c82d88c37b4a69cb.8bc2a12025897702.f0b77de1672da36c
+ 7f7e7970551b8a43.6db364aae9f3bf57.afa50bc0049dc17e.18fe950260e686b3
+ 000000000000fbc9
+VPEXTRW_128_0x3(mem)
+ before
+ 1327f843beca0569.66fa14a3e803d8b6.aecea64d9503078d.a89c2c12cac73f49
+ 9ca23c3a5a0e1932.ed3ba0698b93f43b.694bca989a88fe99.d4f1008112922d10
+ a970dcfcba98b7d3.718d1a2edc571a7e.78f54d77148e5fa8.8ef28479788ac67e
+ 145e5573f9759978.4c3c7d5e74d9852a.b99aaad6201fe8e6.31e9b365993b4740
+ 1b2288b41032ec02
+ after
+ 1327f843beca0569.66fa14a3e803d8b6.aecea64d9503078d.a89c2c12cac78ef2
+ 9ca23c3a5a0e1932.ed3ba0698b93f43b.694bca989a88fe99.d4f1008112922d10
+ a970dcfcba98b7d3.718d1a2edc571a7e.78f54d77148e5fa8.8ef28479788ac67e
+ 145e5573f9759978.4c3c7d5e74d9852a.b99aaad6201fe8e6.31e9b365993b4740
+ 1b2288b41032ec02
+
+VPEXTRW_128_0x3(reg)
+ before
+ a7eb02cf7afbf06f.bb38218d34b07c4e.db94c565f1a872ec.06055da1d94a537e
+ 308f1a2373209033.78c9be3586551b81.7ae1eeafef4d1d6f.3d01e2c45c185c9d
+ 1459cd1c952f08fc.29dfa7570b70343c.856ef4a80956c160.385bb62cc497c16f
+ ad9618277fb39474.a84559dfe00e81ac.5889d4bddb4e9c6b.d5df53c32ed23c1f
+ ee593777b5d58ad9
+ after
+ a7eb02cf7afbf06f.bb38218d34b07c4e.db94c565f1a872ec.06055da1d94a537e
+ 308f1a2373209033.78c9be3586551b81.7ae1eeafef4d1d6f.3d01e2c45c185c9d
+ 1459cd1c952f08fc.29dfa7570b70343c.856ef4a80956c160.385bb62cc497c16f
+ ad9618277fb39474.a84559dfe00e81ac.5889d4bddb4e9c6b.d5df53c32ed23c1f
+ 0000000000000605
+VPEXTRW_128_0x3(mem)
+ before
+ 6095dd3376ad66cb.5993f6aeca396f47.d2c64eb9213abffc.4f7c895802c1e83b
+ 085ec2e28c658e1e.729a631f144cd622.842f04d1e901a959.c6940fe71a3ce17d
+ c0826072140abc01.56f75ce5f97805b1.984cf614546dfcef.191d62d4be4ac5dc
+ 65cb35ce29a7ad9e.5ff8db6b144a379f.ebe9a06c7f8d74e9.a4637f8d8a78ce05
+ c3b1617d1b5038a4
+ after
+ 6095dd3376ad66cb.5993f6aeca396f47.d2c64eb9213abffc.4f7c895802c1191d
+ 085ec2e28c658e1e.729a631f144cd622.842f04d1e901a959.c6940fe71a3ce17d
+ c0826072140abc01.56f75ce5f97805b1.984cf614546dfcef.191d62d4be4ac5dc
+ 65cb35ce29a7ad9e.5ff8db6b144a379f.ebe9a06c7f8d74e9.a4637f8d8a78ce05
+ c3b1617d1b5038a4
+
+VPEXTRW_128_0x4(reg)
+ before
+ d15504100c614164.d406bce2e8481c22.eae8de1f024da999.5ad17fc6856acd74
+ 2c9964b2fa3423f2.e7ff719a6cf9c6b8.5412606c5e0d974a.bfd20d0f8312c2bc
+ 2fca7dcf80571bf9.7b82d1e3d1c7678d.f7c35ebec4173d5f.f7b6c832949010ec
+ 36344cd33b556526.6c5a57a734bebbcc.3047d282d1f6d684.de4a2b1bd5f17330
+ 505ab2b56140a6b5
+ after
+ d15504100c614164.d406bce2e8481c22.eae8de1f024da999.5ad17fc6856acd74
+ 2c9964b2fa3423f2.e7ff719a6cf9c6b8.5412606c5e0d974a.bfd20d0f8312c2bc
+ 2fca7dcf80571bf9.7b82d1e3d1c7678d.f7c35ebec4173d5f.f7b6c832949010ec
+ 36344cd33b556526.6c5a57a734bebbcc.3047d282d1f6d684.de4a2b1bd5f17330
+ 000000000000a999
+VPEXTRW_128_0x4(mem)
+ before
+ 29b2daee558966a7.9d23cc2bc6bb3c24.96557ed3b1e87da2.5beaba2221369f64
+ 451e1eb1ccd86f32.bfe2f941be13dda1.d53dc55462536a3b.d5f8110b4f64d4ac
+ 806afaebe33a7d81.fabfcf83beec8446.05dfa514660a3ec2.f8bcd3aaf70bb008
+ b661ea86b5bb4bc0.a8044a5b62cf6dc2.02079b01d71ab464.2184fc69b6b77023
+ ac9a89b627f550a9
+ after
+ 29b2daee558966a7.9d23cc2bc6bb3c24.96557ed3b1e87da2.5beaba2221363ec2
+ 451e1eb1ccd86f32.bfe2f941be13dda1.d53dc55462536a3b.d5f8110b4f64d4ac
+ 806afaebe33a7d81.fabfcf83beec8446.05dfa514660a3ec2.f8bcd3aaf70bb008
+ b661ea86b5bb4bc0.a8044a5b62cf6dc2.02079b01d71ab464.2184fc69b6b77023
+ ac9a89b627f550a9
+
+VPEXTRW_128_0x4(reg)
+ before
+ f54b75fce7508c47.c3d06a6f5e65961c.27fe6737484ad3bf.a8812406d18e8a4c
+ 58e3bca691555fa9.8383f793fb461ac1.d2f9218209e8f3e9.d319bb0f71727aa7
+ 31ae5a22c28e067b.d2460cdca86993db.044174a8433609ed.5f9adc08d2d340a1
+ dcf74bdb1589bd68.8ce5253880dbbc95.1b225c1592bf5077.28d104dd11bc9a65
+ 0a8bae7a4939421f
+ after
+ f54b75fce7508c47.c3d06a6f5e65961c.27fe6737484ad3bf.a8812406d18e8a4c
+ 58e3bca691555fa9.8383f793fb461ac1.d2f9218209e8f3e9.d319bb0f71727aa7
+ 31ae5a22c28e067b.d2460cdca86993db.044174a8433609ed.5f9adc08d2d340a1
+ dcf74bdb1589bd68.8ce5253880dbbc95.1b225c1592bf5077.28d104dd11bc9a65
+ 000000000000d3bf
+VPEXTRW_128_0x4(mem)
+ before
+ e19255cb9757f4fd.b50c8c3e27d2c01c.8d2cbe919fa7521b.71e7d635900f0532
+ 88b378bd16216e29.183718b593f44a44.b1e653d522d9119a.64dedd74dcb364cb
+ ddb9903ae2a36acf.61c5ebadf67b988c.d3e061ef257eb43e.4e516d3e1036a9ed
+ bb721a3018eaa51c.ec020192ebf3e69f.d1e763cbc2a1f832.8c8d82ffc8240f46
+ 7bde1924a10ad37f
+ after
+ e19255cb9757f4fd.b50c8c3e27d2c01c.8d2cbe919fa7521b.71e7d635900fb43e
+ 88b378bd16216e29.183718b593f44a44.b1e653d522d9119a.64dedd74dcb364cb
+ ddb9903ae2a36acf.61c5ebadf67b988c.d3e061ef257eb43e.4e516d3e1036a9ed
+ bb721a3018eaa51c.ec020192ebf3e69f.d1e763cbc2a1f832.8c8d82ffc8240f46
+ 7bde1924a10ad37f
+
+VPEXTRW_128_0x4(reg)
+ before
+ 75902c1736733146.fda89389d401db3c.153a57d10ee96f2a.86c5d555184e99a3
+ d7eeb94624eb6447.8129763331f4c75a.37b9e8d5fce870d9.cd46347a409253bd
+ fd46bb1c06ffa92e.22bf3f194bd026a3.b0cab009517d2557.8438fa245978e1ab
+ 44e22f05793a3ca6.bb376b273fa0b443.dbbbabdba833c951.8666a5407c0d009a
+ ae9bb0bbc85b6bb5
+ after
+ 75902c1736733146.fda89389d401db3c.153a57d10ee96f2a.86c5d555184e99a3
+ d7eeb94624eb6447.8129763331f4c75a.37b9e8d5fce870d9.cd46347a409253bd
+ fd46bb1c06ffa92e.22bf3f194bd026a3.b0cab009517d2557.8438fa245978e1ab
+ 44e22f05793a3ca6.bb376b273fa0b443.dbbbabdba833c951.8666a5407c0d009a
+ 0000000000006f2a
+VPEXTRW_128_0x4(mem)
+ before
+ daa4977f5670e029.060f0f6c1828595b.2a5c744929702d65.14d6d5b69d969a72
+ e44dd77a44581921.a01959bf80563bfb.49fcd86b244d4c36.b6682b06cd32d267
+ aa62ea97ae1ed3ca.6e4c086a4c4f1f2f.f6e212794c42cee1.1fbda837d394addc
+ 06af4ec1afcec950.ccf418d7189f41a6.0bd99e60be5c6f93.a92048b54c47697c
+ b2df07ecd3d840f3
+ after
+ daa4977f5670e029.060f0f6c1828595b.2a5c744929702d65.14d6d5b69d96cee1
+ e44dd77a44581921.a01959bf80563bfb.49fcd86b244d4c36.b6682b06cd32d267
+ aa62ea97ae1ed3ca.6e4c086a4c4f1f2f.f6e212794c42cee1.1fbda837d394addc
+ 06af4ec1afcec950.ccf418d7189f41a6.0bd99e60be5c6f93.a92048b54c47697c
+ b2df07ecd3d840f3
+
+VPEXTRW_128_0x5(reg)
+ before
+ 9544e24905d26fef.d6007ee66474b9de.165c867381d3dd0a.66aef90a95a5ea77
+ ad9dd4367dc1311a.f420f7f1e81d5da1.a8d24caa23762e07.e12d9e64ee2cfcba
+ 5834d921d832c420.3ddc33cf57d472c5.dea068e99915714b.5a22095be4fa6188
+ f056ed74b1b062ae.8e00b06acea6b375.1413d59b7f3ae17f.ab59b6da941dd50c
+ b19d21cc19a01373
+ after
+ 9544e24905d26fef.d6007ee66474b9de.165c867381d3dd0a.66aef90a95a5ea77
+ ad9dd4367dc1311a.f420f7f1e81d5da1.a8d24caa23762e07.e12d9e64ee2cfcba
+ 5834d921d832c420.3ddc33cf57d472c5.dea068e99915714b.5a22095be4fa6188
+ f056ed74b1b062ae.8e00b06acea6b375.1413d59b7f3ae17f.ab59b6da941dd50c
+ 00000000000081d3
+VPEXTRW_128_0x5(mem)
+ before
+ 49bcc71f9090d8e9.d24f0c9da5c74770.c158e9af689ddddd.a6778f2b7274bc52
+ 4d8022be14f7e099.5b6a33074f04b111.b3b05a8b42c8ac2b.f01793070d4c3c6e
+ 9ab6b195c1e4e6af.e5f55d1e4cf2da3e.41d47fe87830dc88.4e41dc9aed509e7f
+ 0c2aed90b460a859.cd3a864e371dffa2.458fd5b424e32823.1c3f6650ae0b1d32
+ b65f2d95ea09f633
+ after
+ 49bcc71f9090d8e9.d24f0c9da5c74770.c158e9af689ddddd.a6778f2b72747830
+ 4d8022be14f7e099.5b6a33074f04b111.b3b05a8b42c8ac2b.f01793070d4c3c6e
+ 9ab6b195c1e4e6af.e5f55d1e4cf2da3e.41d47fe87830dc88.4e41dc9aed509e7f
+ 0c2aed90b460a859.cd3a864e371dffa2.458fd5b424e32823.1c3f6650ae0b1d32
+ b65f2d95ea09f633
+
+VPEXTRW_128_0x5(reg)
+ before
+ 77eb2dd540d7652d.7fa8539c0979e0c0.7086aa03ac125bea.9cafd7d965ec4d26
+ bd30637c4900a6cd.d0fb60a3db3a4a13.2825c6a9485c2cc2.22fe0145545807bd
+ e379caf6a411f4bf.d9f18f9246b0a47c.5263d4aca787acd5.b349cfe310321116
+ 45145eb0ea958dae.77545c5667e6a827.4a8cd279642018d0.2b5cbe9fb286285a
+ 66034965586108b8
+ after
+ 77eb2dd540d7652d.7fa8539c0979e0c0.7086aa03ac125bea.9cafd7d965ec4d26
+ bd30637c4900a6cd.d0fb60a3db3a4a13.2825c6a9485c2cc2.22fe0145545807bd
+ e379caf6a411f4bf.d9f18f9246b0a47c.5263d4aca787acd5.b349cfe310321116
+ 45145eb0ea958dae.77545c5667e6a827.4a8cd279642018d0.2b5cbe9fb286285a
+ 000000000000ac12
+VPEXTRW_128_0x5(mem)
+ before
+ 4009ec211ecd6d5a.3e4c1b14b918aa47.86f143da59e81242.6debbb7a1bb2ab5e
+ 953c23bf1fd9126c.2c6cfd90ad278a35.e294c10939c3a0f6.15ce8c1d69c9a22d
+ 41666a2c788eb41c.69c1018f614d6725.670951d123810c72.9f7f3fcce9f239e6
+ 20543e5244fa0f93.5397227c72167ec3.f11c6f1d313113e0.674bd2f538b8ac37
+ c97e4003f1a736cc
+ after
+ 4009ec211ecd6d5a.3e4c1b14b918aa47.86f143da59e81242.6debbb7a1bb22381
+ 953c23bf1fd9126c.2c6cfd90ad278a35.e294c10939c3a0f6.15ce8c1d69c9a22d
+ 41666a2c788eb41c.69c1018f614d6725.670951d123810c72.9f7f3fcce9f239e6
+ 20543e5244fa0f93.5397227c72167ec3.f11c6f1d313113e0.674bd2f538b8ac37
+ c97e4003f1a736cc
+
+VPEXTRW_128_0x5(reg)
+ before
+ 21648662b14c1450.0ed21a1f9f29df00.443a5cc57b0e0bba.5c9897d982dc716c
+ cb499e7e13328270.e7ac7a7da625df8d.9af6acd518c249b6.834a45f12f90e143
+ 237886c3b4e6bbd8.87adda5a74fccc66.af160c18e6be7665.44fff65157592091
+ 853e399d2ff3fd33.caa3b6a126ba62b8.e1e87afb808ccb70.7a8125e51341ea82
+ 019d4e9a8156fb40
+ after
+ 21648662b14c1450.0ed21a1f9f29df00.443a5cc57b0e0bba.5c9897d982dc716c
+ cb499e7e13328270.e7ac7a7da625df8d.9af6acd518c249b6.834a45f12f90e143
+ 237886c3b4e6bbd8.87adda5a74fccc66.af160c18e6be7665.44fff65157592091
+ 853e399d2ff3fd33.caa3b6a126ba62b8.e1e87afb808ccb70.7a8125e51341ea82
+ 0000000000007b0e
+VPEXTRW_128_0x5(mem)
+ before
+ b51eed5abda40efa.4de7b37821e5822e.8b588b3ed8695caf.8ab6f1e883ba8786
+ 71d27f13e235e0da.d7bff0c125488674.a899d41da5177777.08cd6d4c8bd4e451
+ 13837eaf0d172c0d.7e12ede2d7a947b2.fc320d2aa9d06f3a.b579eb9432641f7e
+ 76ff681c5956b0be.a02ca449d493ff94.62efb251019e0027.ee06652a17f874b8
+ 10bfd97cd31b1fac
+ after
+ b51eed5abda40efa.4de7b37821e5822e.8b588b3ed8695caf.8ab6f1e883baa9d0
+ 71d27f13e235e0da.d7bff0c125488674.a899d41da5177777.08cd6d4c8bd4e451
+ 13837eaf0d172c0d.7e12ede2d7a947b2.fc320d2aa9d06f3a.b579eb9432641f7e
+ 76ff681c5956b0be.a02ca449d493ff94.62efb251019e0027.ee06652a17f874b8
+ 10bfd97cd31b1fac
+
+VPEXTRW_128_0x6(reg)
+ before
+ 75f242f5055a5b05.7510b945e2fd261a.98581361b893ebc5.b89c407ec88fe568
+ 7ae99d0046406570.ee83eb16c5184b4d.c2e436951e3446f2.d904329e1bafdb2a
+ 7bf1e40b345a7899.bb237c7b1db3da82.791a0753a2024dc6.a0f5049b15099d98
+ d45615816b32d22b.babee66007db91e5.1b478406e1893cee.eb393263d2a9e9df
+ 949d38e0709b792a
+ after
+ 75f242f5055a5b05.7510b945e2fd261a.98581361b893ebc5.b89c407ec88fe568
+ 7ae99d0046406570.ee83eb16c5184b4d.c2e436951e3446f2.d904329e1bafdb2a
+ 7bf1e40b345a7899.bb237c7b1db3da82.791a0753a2024dc6.a0f5049b15099d98
+ d45615816b32d22b.babee66007db91e5.1b478406e1893cee.eb393263d2a9e9df
+ 0000000000001361
+VPEXTRW_128_0x6(mem)
+ before
+ 79ed930008ec0aa7.e1642bce8656add3.c61fa8b19f9b2aa4.03b7a81a76564f15
+ 74f5beaeb8a7577f.ff66225f2252453c.ba113b5bffff61e9.8cb66ffbfef4c2e9
+ 638035d69cd81ee1.88aaf79edab1d813.73611c484614f4e0.148fd51614f0d013
+ 205c7464cf8c19f6.d97aa4f84affa004.cedbc8658ee59db6.f590d7d555d5b542
+ 8d036fa55c2faf1f
+ after
+ 79ed930008ec0aa7.e1642bce8656add3.c61fa8b19f9b2aa4.03b7a81a76561c48
+ 74f5beaeb8a7577f.ff66225f2252453c.ba113b5bffff61e9.8cb66ffbfef4c2e9
+ 638035d69cd81ee1.88aaf79edab1d813.73611c484614f4e0.148fd51614f0d013
+ 205c7464cf8c19f6.d97aa4f84affa004.cedbc8658ee59db6.f590d7d555d5b542
+ 8d036fa55c2faf1f
+
+VPEXTRW_128_0x6(reg)
+ before
+ 36359bf3c68bf859.8853f8446dce05ed.4e2327da0fc8daba.a54bba9ff37f1997
+ 4e72572a2e74cd9a.78323c6293ab9df0.43f27baec599c2e2.d67d6ee191ed23ae
+ 2f069db531766a8f.cac5bcab5c2e9e2c.13309de207fd9327.3b3c6017863b7928
+ 373d6b026a1e0be3.5bd8f409e563c4cc.1c2c87e171808a36.b1560d2ceb75d530
+ 1495f00edea8f4f3
+ after
+ 36359bf3c68bf859.8853f8446dce05ed.4e2327da0fc8daba.a54bba9ff37f1997
+ 4e72572a2e74cd9a.78323c6293ab9df0.43f27baec599c2e2.d67d6ee191ed23ae
+ 2f069db531766a8f.cac5bcab5c2e9e2c.13309de207fd9327.3b3c6017863b7928
+ 373d6b026a1e0be3.5bd8f409e563c4cc.1c2c87e171808a36.b1560d2ceb75d530
+ 00000000000027da
+VPEXTRW_128_0x6(mem)
+ before
+ 41c685a87bdf919d.c062bb7c76f7eb43.0836606a4a56cbfd.b9313717a0afe3bb
+ 12b548e7dd276959.27c28b8ff08d475a.abad7db8a5146eea.468aa8f02f15d961
+ 642eb6b5208b3854.c9aad7a7746d5ad5.2107c6e115a86ac0.1f84d6d8bb3faad5
+ 13fc49ff6117bab9.006499309f226260.4611b7d0b31f7bab.a06bbd3bdfb890c2
+ 248b5a85380cc7d5
+ after
+ 41c685a87bdf919d.c062bb7c76f7eb43.0836606a4a56cbfd.b9313717a0afc6e1
+ 12b548e7dd276959.27c28b8ff08d475a.abad7db8a5146eea.468aa8f02f15d961
+ 642eb6b5208b3854.c9aad7a7746d5ad5.2107c6e115a86ac0.1f84d6d8bb3faad5
+ 13fc49ff6117bab9.006499309f226260.4611b7d0b31f7bab.a06bbd3bdfb890c2
+ 248b5a85380cc7d5
+
+VPEXTRW_128_0x6(reg)
+ before
+ 0930a82261c78db9.fbed7fb2bcd7aab5.293ccf970d3899a6.f697cc719e845cd6
+ aaa6a37ff7761c1c.f8cbd3b84cd8c574.a0807446593c3b54.0d6582b0efe3ca6e
+ 6238470695a4b1a7.e663c2ff2d26c721.c17b84aa1fb98615.67475379c549819e
+ 8f349125d7de8709.a181c6717ccb6be9.e978fb30fc3bb496.e009bdb839c13d93
+ 54763c596957b979
+ after
+ 0930a82261c78db9.fbed7fb2bcd7aab5.293ccf970d3899a6.f697cc719e845cd6
+ aaa6a37ff7761c1c.f8cbd3b84cd8c574.a0807446593c3b54.0d6582b0efe3ca6e
+ 6238470695a4b1a7.e663c2ff2d26c721.c17b84aa1fb98615.67475379c549819e
+ 8f349125d7de8709.a181c6717ccb6be9.e978fb30fc3bb496.e009bdb839c13d93
+ 000000000000cf97
+VPEXTRW_128_0x6(mem)
+ before
+ 9f5b4a487117b27b.8ce47b475aafdbeb.05f15dfc54d56ff7.72c4d6438b4f0283
+ 9d8465726c0ee4c6.b49503d7baa3e9fc.ee7f028bd24f8d78.b9ab104e6980ac87
+ 2abd07c176480b85.659324439247ede6.38f6310a11468198.1a79a5bf315aed4f
+ 22d2ae23accfe2e5.f929dbf67e262356.bf2367652ec50982.f17a9101806a0286
+ 9afad180f13b27d9
+ after
+ 9f5b4a487117b27b.8ce47b475aafdbeb.05f15dfc54d56ff7.72c4d6438b4f310a
+ 9d8465726c0ee4c6.b49503d7baa3e9fc.ee7f028bd24f8d78.b9ab104e6980ac87
+ 2abd07c176480b85.659324439247ede6.38f6310a11468198.1a79a5bf315aed4f
+ 22d2ae23accfe2e5.f929dbf67e262356.bf2367652ec50982.f17a9101806a0286
+ 9afad180f13b27d9
+
+VPEXTRW_128_0x7(reg)
+ before
+ 71445fa8215a97f4.618fd6832ab12612.cea5225c1bccc6f7.5fd31e8844d8df63
+ d2a639e5ab518f82.c3bff9cc0bfa9337.3e51f7e105c61376.f4d0d460708cbf66
+ 186a5aa42baf4b30.233095ec6bb4e480.a77b55f2d79f457e.59e704d7cdec67b8
+ a1ddbf4f3ffd07a9.5fac25ce67edd61b.636d38f92de39abc.6ce32bda78049185
+ 0892c3568ce1faf8
+ after
+ 71445fa8215a97f4.618fd6832ab12612.cea5225c1bccc6f7.5fd31e8844d8df63
+ d2a639e5ab518f82.c3bff9cc0bfa9337.3e51f7e105c61376.f4d0d460708cbf66
+ 186a5aa42baf4b30.233095ec6bb4e480.a77b55f2d79f457e.59e704d7cdec67b8
+ a1ddbf4f3ffd07a9.5fac25ce67edd61b.636d38f92de39abc.6ce32bda78049185
+ 000000000000cea5
+VPEXTRW_128_0x7(mem)
+ before
+ 09be4a36258e5e3e.c84b625480c9fe9a.5200255e1ab12532.cf749d63a41f4cdc
+ 4a353b6560177882.e9ff411d8c9e6eaf.d8f81189a10a8df1.48db7f9dd7de9789
+ a9c112d1598905f1.60475718ff099093.cc5f66391707c985.28f0d91263acb970
+ 002f4b652befc1b6.886da0b07494a3f3.0c039f5b99b1961a.ccfdaa2de316ec3d
+ 9050eb5cf4a76d9b
+ after
+ 09be4a36258e5e3e.c84b625480c9fe9a.5200255e1ab12532.cf749d63a41fcc5f
+ 4a353b6560177882.e9ff411d8c9e6eaf.d8f81189a10a8df1.48db7f9dd7de9789
+ a9c112d1598905f1.60475718ff099093.cc5f66391707c985.28f0d91263acb970
+ 002f4b652befc1b6.886da0b07494a3f3.0c039f5b99b1961a.ccfdaa2de316ec3d
+ 9050eb5cf4a76d9b
+
+VPEXTRW_128_0x7(reg)
+ before
+ d033990a31eb7736.2d4a630df25668fe.bfbe195187cee17a.72ae38dc4216afdb
+ e9f3b1a3366f48bb.0be0d5b5cbc8b5f5.6086bc67d54087d5.dc2dada62f41d2f5
+ 35dc2e93a1be1ad6.75bc1d49d15465c6.c611875ef978d1af.244c7aa77b3eb994
+ 11390c460b642a33.49a9b7b62103349e.4fab75a29001fab6.28d71cca421a21e3
+ c29a0efba1e0c50e
+ after
+ d033990a31eb7736.2d4a630df25668fe.bfbe195187cee17a.72ae38dc4216afdb
+ e9f3b1a3366f48bb.0be0d5b5cbc8b5f5.6086bc67d54087d5.dc2dada62f41d2f5
+ 35dc2e93a1be1ad6.75bc1d49d15465c6.c611875ef978d1af.244c7aa77b3eb994
+ 11390c460b642a33.49a9b7b62103349e.4fab75a29001fab6.28d71cca421a21e3
+ 000000000000bfbe
+VPEXTRW_128_0x7(mem)
+ before
+ d061cc26b49d6343.d958482912eeb37d.617420e6d6e3dda9.56a0839f35683f93
+ 2cf7d237965bb5ac.e983dca652e7f260.9ae9d2c70dff1d12.363babc18538dcf5
+ b4299d1a63287875.9d07c62b66db2389.d1d44b43e163b006.4dc9eb751bfd0d85
+ 42c3a8bb381067cb.51300122ea5782a4.e00106486f1c52b0.f5963e2594440df2
+ 8ceea03f8b9819e6
+ after
+ d061cc26b49d6343.d958482912eeb37d.617420e6d6e3dda9.56a0839f3568d1d4
+ 2cf7d237965bb5ac.e983dca652e7f260.9ae9d2c70dff1d12.363babc18538dcf5
+ b4299d1a63287875.9d07c62b66db2389.d1d44b43e163b006.4dc9eb751bfd0d85
+ 42c3a8bb381067cb.51300122ea5782a4.e00106486f1c52b0.f5963e2594440df2
+ 8ceea03f8b9819e6
+
+VPEXTRW_128_0x7(reg)
+ before
+ 6c1d0e2e9d856d0e.b3916f06311e3fda.614a8af97be64a5d.a43b80c1d235be3d
+ f26f825d65984415.e35f6ee8695ebccd.29a15b1bb415b85f.fa50339927bbb1d8
+ 7b2ffa3a805cdba8.aff9214bfcdc9ad1.058072f3326f0856.bc0a9dbe89b9e7ae
+ 61ab7130895d6e72.f12a051d07a59411.5035caef908076ef.c736391b153b1beb
+ f7a0839de64d0bba
+ after
+ 6c1d0e2e9d856d0e.b3916f06311e3fda.614a8af97be64a5d.a43b80c1d235be3d
+ f26f825d65984415.e35f6ee8695ebccd.29a15b1bb415b85f.fa50339927bbb1d8
+ 7b2ffa3a805cdba8.aff9214bfcdc9ad1.058072f3326f0856.bc0a9dbe89b9e7ae
+ 61ab7130895d6e72.f12a051d07a59411.5035caef908076ef.c736391b153b1beb
+ 000000000000614a
+VPEXTRW_128_0x7(mem)
+ before
+ 2914f82e18fc7148.012de3ab1c283920.86c09548a5c567ba.680a5f7a6bd43dd6
+ 375d13bbc85409c0.b8024d18d648775e.4a854dbaf346cff8.a84c2d015ff89ab6
+ fe495031125f914f.e076aae1534965d7.1946a95e0c3687f6.6c4731ee0677c93c
+ 5aa22b7a102bc321.d6d4f6732db83f38.cfcf26200da04ce1.0f4766aefede0514
+ ef98c8aee3b88be9
+ after
+ 2914f82e18fc7148.012de3ab1c283920.86c09548a5c567ba.680a5f7a6bd41946
+ 375d13bbc85409c0.b8024d18d648775e.4a854dbaf346cff8.a84c2d015ff89ab6
+ fe495031125f914f.e076aae1534965d7.1946a95e0c3687f6.6c4731ee0677c93c
+ 5aa22b7a102bc321.d6d4f6732db83f38.cfcf26200da04ce1.0f4766aefede0514
+ ef98c8aee3b88be9
+
+VAESENC(reg)
+ before
+ 6785535850919768.27352084e1c35b61.f66a2d3b0320412c.48ec3eec1191dae4
+ d25b041ae2f5643c.41ceac399f34173c.9c824ba36f0da660.60686fae3414ed2c
+ 8e67d55e34713012.843949876689b1dd.246a4d190d0cab80.f3113453933540e5
+ f6f3c492e2913595.cc42755953cee671.eb6c2d087aa88b37.ddb10ac54a01903a
+ fa156bf174839958
+ after
+ 0000000000000000.0000000000000000.615c8a1f94ebc3df.c3dfb5e7d820c6ed
+ d25b041ae2f5643c.41ceac399f34173c.9c824ba36f0da660.60686fae3414ed2c
+ 8e67d55e34713012.843949876689b1dd.246a4d190d0cab80.f3113453933540e5
+ f6f3c492e2913595.cc42755953cee671.eb6c2d087aa88b37.ddb10ac54a01903a
+ fa156bf174839958
+VAESENC(mem)
+ before
+ 2609d5c42dc7176a.654bcc2189dfaf73.f5b4ac9b81107224.4bd5eadb516d8432
+ 3d59c32992dac59d.39bdea77c5e9dc55.db5c68390d5a1021.a1f07d002fe8d01c
+ 1bd0b20bbfc7601d.cc941800313af6e9.5907271f12b87d95.490be3e2afa4aba2
+ 9c3c1c58cf9aa415.7b1b5428695f3adb.4d7f643aad3775ab.9e7119ee6e2e5370
+ fe6d1a8e07100231
+ after
+ 2609d5c42dc7176a.654bcc2189dfaf73.f5b4ac9b81107224.4bd5eadb516d8432
+ 3d59c32992dac59d.39bdea77c5e9dc55.db5c68390d5a1021.a1f07d002fe8d01c
+ 0000000000000000.0000000000000000.8ab7067427d381a3.44d7cd07c6b99d0c
+ 9c3c1c58cf9aa415.7b1b5428695f3adb.4d7f643aad3775ab.9e7119ee6e2e5370
+ fe6d1a8e07100231
+
+VAESENC(reg)
+ before
+ c44ce22f16d8f592.9b677ffbde604cb2.a39f995c0ae3e3d7.92919b74f9e2b390
+ 4c5a6d3d3812683e.f61e56e00924151f.9e6ce306af522f88.040848ba12c5f56f
+ f2e3b825094996e2.882d1df36bf2bb89.cace2f93f539589b.7eb2e7f915edf576
+ 1232be522409bc2a.2d60502021d7fa1b.8111787077239bbb.de59f51c1e656fce
+ ffcbed0e483921a6
+ after
+ 0000000000000000.0000000000000000.5facbe35eab6bd6f.b5b300acb20af2c0
+ 4c5a6d3d3812683e.f61e56e00924151f.9e6ce306af522f88.040848ba12c5f56f
+ f2e3b825094996e2.882d1df36bf2bb89.cace2f93f539589b.7eb2e7f915edf576
+ 1232be522409bc2a.2d60502021d7fa1b.8111787077239bbb.de59f51c1e656fce
+ ffcbed0e483921a6
+VAESENC(mem)
+ before
+ bcd24bbdaf76c528.08957b2f26de16c1.c0836c5446de8d03.2081ba08d29c3395
+ f33b8c1470271880.2f56eb2aa955e054.1f61ec79f713316a.0369f1c6a1315dd4
+ 7fd22affa758d5db.e5c30aae4cfa558e.24c84c7c4f83a17f.87161918816d5525
+ 3b62a36a6f16ba65.8526d527a957b21c.ad82084a6b399b6b.06d52f690ddc5734
+ ddef2d25e20b9eac
+ after
+ bcd24bbdaf76c528.08957b2f26de16c1.c0836c5446de8d03.2081ba08d29c3395
+ f33b8c1470271880.2f56eb2aa955e054.1f61ec79f713316a.0369f1c6a1315dd4
+ 0000000000000000.0000000000000000.64283a66bf0a21f2.ab6183f44dd46540
+ 3b62a36a6f16ba65.8526d527a957b21c.ad82084a6b399b6b.06d52f690ddc5734
+ ddef2d25e20b9eac
+
+VAESENC(reg)
+ before
+ 68b311b89b85673a.05b97241e46c8149.6acc47015cfa33a9.945c9cce6641d95d
+ 036cd68ed5d7ee89.b7a114712367e6b4.f2005ca8026e13e3.b72285f35ca8187f
+ 0a6579142b8b6e46.2fe703e44711a7d1.7710108836408f73.f0a03ea76b7913fe
+ d9ecf5b4392f251d.4757bd886d797ece.5746600e95fbe308.1da143d5acc18805
+ 18f310693d8a31c1
+ after
+ 0000000000000000.0000000000000000.fadb4a1fc464fee4.6dc826130799c7f5
+ 036cd68ed5d7ee89.b7a114712367e6b4.f2005ca8026e13e3.b72285f35ca8187f
+ 0a6579142b8b6e46.2fe703e44711a7d1.7710108836408f73.f0a03ea76b7913fe
+ d9ecf5b4392f251d.4757bd886d797ece.5746600e95fbe308.1da143d5acc18805
+ 18f310693d8a31c1
+VAESENC(mem)
+ before
+ bf60224f3ae3cb5d.cc4b45db9c4f4cb9.dcbdbd47b0a828d4.ecf047a4ba2b4b4b
+ ecb5f374bdd51106.3fcf67f6ef7622c7.cbe57f0f2dac6011.9458c1b8425d02eb
+ 7cbe01c2e56ec0e8.8ec45770cf30e1f2.ee9a7fcbff90e4b1.a9cbcab4c81b4592
+ 4c47c826ccb9942e.15760fb4d809c7e7.22aa3a6743606ee0.89945e06e9f450ed
+ 8e017a1940715ea7
+ after
+ bf60224f3ae3cb5d.cc4b45db9c4f4cb9.dcbdbd47b0a828d4.ecf047a4ba2b4b4b
+ ecb5f374bdd51106.3fcf67f6ef7622c7.cbe57f0f2dac6011.9458c1b8425d02eb
+ 0000000000000000.0000000000000000.f01b4380f706e3c8.0991cce24da2e584
+ 4c47c826ccb9942e.15760fb4d809c7e7.22aa3a6743606ee0.89945e06e9f450ed
+ 8e017a1940715ea7
+
+VAESENCLAST(reg)
+ before
+ 165d19596920ac6d.361bc28d8ec34905.30308d30a58e0d52.43df2bcf1429bac9
+ 7bf33732018d76ea.17086de148969a98.3b40cc4fd24af2de.2e06ceef8ef78698
+ 1a10d010a442f8cb.cbd8441015414414.92f0c87dfccab038.bdeb9fb3ced48c7b
+ 4f00e05fedcd6dbc.2e58c30512cd03a5.908d7e26be98840b.cd5a1a07f0ce899b
+ 3a1ebcd70ff03927
+ after
+ 0000000000000000.0000000000000000.279f8cf9cda2fb25.a4e2166c2c02073d
+ 7bf33732018d76ea.17086de148969a98.3b40cc4fd24af2de.2e06ceef8ef78698
+ 1a10d010a442f8cb.cbd8441015414414.92f0c87dfccab038.bdeb9fb3ced48c7b
+ 4f00e05fedcd6dbc.2e58c30512cd03a5.908d7e26be98840b.cd5a1a07f0ce899b
+ 3a1ebcd70ff03927
+VAESENCLAST(mem)
+ before
+ e005001047475749.770f648b78ba1268.1c5566ac5a489276.9363e8b7b543aa04
+ 9bd9629cb5dea02e.ec895701e293237c.7198a9f10abdaeb4.f6be049a7c545dce
+ 47675e6975c1d001.0bb9b52bc7e7dba3.09f009c03d39138b.14e9cd3caf59da16
+ c07b7162a1fca2ee.30ed7b77c23f778a.c128010510c77d26.4b323f0aecdd5d88
+ f6e3576fcc6d22cf
+ after
+ e005001047475749.770f648b78ba1268.1c5566ac5a489276.9363e8b7b543aa04
+ 9bd9629cb5dea02e.ec895701e293237c.7198a9f10abdaeb4.f6be049a7c545dce
+ 0000000000000000.0000000000000000.7bfb2a0d186841fb.83250c0f1639588f
+ c07b7162a1fca2ee.30ed7b77c23f778a.c128010510c77d26.4b323f0aecdd5d88
+ f6e3576fcc6d22cf
+
+VAESENCLAST(reg)
+ before
+ 704910d6ed946498.e2e11672589cd423.b76fa34f6f2933dd.730b0dac9e73a7b1
+ 17b065adebde608f.8965c987b3ad20ca.fc8c2b216b304b47.fb66aaa2034a4e59
+ 4564555f61d8525f.91d2068cd139420f.5b900e5851e0fa75.370552d15c572e4a
+ 58b1d958eb0d75b5.d6f6496dcb4ef820.30c74860bec67d12.02b48326c5a603af
+ 383fb88e594488b5
+ after
+ 0000000000000000.0000000000000000.24a321a55e360bd5.4c61e1ebec538281
+ 17b065adebde608f.8965c987b3ad20ca.fc8c2b216b304b47.fb66aaa2034a4e59
+ 4564555f61d8525f.91d2068cd139420f.5b900e5851e0fa75.370552d15c572e4a
+ 58b1d958eb0d75b5.d6f6496dcb4ef820.30c74860bec67d12.02b48326c5a603af
+ 383fb88e594488b5
+VAESENCLAST(mem)
+ before
+ b5726df4343c7a88.aae2ef042609063c.349b0f16c0f8fc26.d77cd6a54d6d10cb
+ 55181f44739a9553.994591cfae5841a1.878ed374c9410a50.acfdb3939b61ef4c
+ f4ff496a316b9443.7f24bd251d87628f.ab9b11710437e0c8.0b94da96432f5540
+ 6df167528bba3483.bacc6f731222a4b3.7b8d45fb8de638ba.508e4a1ae1627f54
+ d737fc8c1287a933
+ after
+ b5726df4343c7a88.aae2ef042609063c.349b0f16c0f8fc26.d77cd6a54d6d10cb
+ 55181f44739a9553.994591cfae5841a1.878ed374c9410a50.acfdb3939b61ef4c
+ 0000000000000000.0000000000000000.e9cfd08451179a75.c365b1795aee7de2
+ 6df167528bba3483.bacc6f731222a4b3.7b8d45fb8de638ba.508e4a1ae1627f54
+ d737fc8c1287a933
+
+VAESENCLAST(reg)
+ before
+ fcdbed5672290e8a.9ebbf5e89c933140.a489a12327b344b9.d532ecfc7f58cf53
+ 1bc61ae69cd4eb05.62296f18810347a6.9aa751a3f8c87e4c.94548162f79b61bf
+ 8f437ea72c147c4f.940652ce551531e0.f8717a5d22ed8d19.93c1801710bba929
+ b6a01604bf76fc15.122018f735d5ac1a.1b3518bf40acaecc.b0436509e6c264be
+ c6a7ac2396bf4eaa
+ after
+ 0000000000000000.0000000000000000.b951955700f95c30.fb9d73bda853a521
+ 1bc61ae69cd4eb05.62296f18810347a6.9aa751a3f8c87e4c.94548162f79b61bf
+ 8f437ea72c147c4f.940652ce551531e0.f8717a5d22ed8d19.93c1801710bba929
+ b6a01604bf76fc15.122018f735d5ac1a.1b3518bf40acaecc.b0436509e6c264be
+ c6a7ac2396bf4eaa
+VAESENCLAST(mem)
+ before
+ b0b9d2513bbb2318.eb27dc6bf185a902.b6413f7d3c507382.5d3d2734ef931d10
+ 4c44527ff2c49e35.8925ce475dcebdc3.5e36434e87914442.1bd6a428ca2e1691
+ 7416a89ad7e57c2c.eee6e6049fdc7403.e5cb9e5431a4d986.b14c89076d07d4fc
+ 06f9508c052a792a.75b6230e543b0c6f.26ccce7d5796ef7b.7bebd43d75ad94fd
+ d5ff81367ea99240
+ after
+ b0b9d2513bbb2318.eb27dc6bf185a902.b6413f7d3c507382.5d3d2734ef931d10
+ 4c44527ff2c49e35.8925ce475dcebdc3.5e36434e87914442.1bd6a428ca2e1691
+ 0000000000000000.0000000000000000.a1b77852936169ae.29383c00b7125491
+ 06f9508c052a792a.75b6230e543b0c6f.26ccce7d5796ef7b.7bebd43d75ad94fd
+ d5ff81367ea99240
+
+VAESDEC(reg)
+ before
+ 1bd38a5e23890a70.dcbac64298a0505a.79e07ed21778bfb3.fe054eb41472414d
+ aab5ed2201d83739.d32587a9ad52bee9.58b2f4ba851eca7a.4a429ae584458d27
+ dcefa5ecb2225648.c8060eab5f4d7f03.6c76823339b96871.e44e2efcc41a8d36
+ 0dceae2ad5f4a249.9529d736ca9b4fd3.137923aad0d5d744.aaf687e5f0fdfea5
+ 76071f8c23fa9ba2
+ after
+ 0000000000000000.0000000000000000.4d3d2e9c2eef7591.dd37510456469dda
+ aab5ed2201d83739.d32587a9ad52bee9.58b2f4ba851eca7a.4a429ae584458d27
+ dcefa5ecb2225648.c8060eab5f4d7f03.6c76823339b96871.e44e2efcc41a8d36
+ 0dceae2ad5f4a249.9529d736ca9b4fd3.137923aad0d5d744.aaf687e5f0fdfea5
+ 76071f8c23fa9ba2
+VAESDEC(mem)
+ before
+ 254a74dd791e2156.9b9e044704d959e8.18595f350c4be986.a707d38ae5ff519e
+ 948e02c50f744cef.e1aaa3aedb5eb5d0.2b6420943e660a47.866c8f3e15c3122c
+ 9d9e432e0009d899.3b4088cdf70df3ad.ab14983f7efa6e44.0af35134fbab5899
+ 1d45b50669e88080.05aaae0ff3754e2c.74364222e812d0a6.90ea17d733455d92
+ 759bdc935a1d5ec2
+ after
+ 254a74dd791e2156.9b9e044704d959e8.18595f350c4be986.a707d38ae5ff519e
+ 948e02c50f744cef.e1aaa3aedb5eb5d0.2b6420943e660a47.866c8f3e15c3122c
+ 0000000000000000.0000000000000000.aba2dd2c451f624d.91347c95d991d753
+ 1d45b50669e88080.05aaae0ff3754e2c.74364222e812d0a6.90ea17d733455d92
+ 759bdc935a1d5ec2
+
+VAESDEC(reg)
+ before
+ 13539dd40cbd96d6.f051d238651d01cf.9b3611e06c1f03f9.62969a2997bbee9b
+ c75e5406e4b3437a.f28c19af11b417b2.592eaeacfd994ebf.52001d40a700824f
+ ed08ff967e8b9f59.ffc3035988ba7d57.9adf7fdf436e6b2b.1e3f455335ed48ee
+ e29d99ee77cfe720.f4c20d21e73bf0e7.bc9582e6d92b95e9.a321904f5d8efea3
+ bd70791e3af05e9a
+ after
+ 0000000000000000.0000000000000000.0c484325a6349f0d.bc34cef03ec3948a
+ c75e5406e4b3437a.f28c19af11b417b2.592eaeacfd994ebf.52001d40a700824f
+ ed08ff967e8b9f59.ffc3035988ba7d57.9adf7fdf436e6b2b.1e3f455335ed48ee
+ e29d99ee77cfe720.f4c20d21e73bf0e7.bc9582e6d92b95e9.a321904f5d8efea3
+ bd70791e3af05e9a
+VAESDEC(mem)
+ before
+ 48f97daee81f2400.00691e7b6b0d567a.ab55b4f349412c91.1a9bb22b5c5a0aa4
+ 208816ea84250e01.a4b78aaaf5d12914.014773bccbdaed7f.0f3f0b1c678a0309
+ 21e9c2bd2910d6c9.2ad4dae6b1a69c9a.d266c6668811eedd.f9cb8a239744bfc3
+ 27e8fc15f4eb3983.ee0c099a3c18ebb7.fa7c2ade9cf3ecd8.338c2aae8716787f
+ 18cee728d38b6be8
+ after
+ 48f97daee81f2400.00691e7b6b0d567a.ab55b4f349412c91.1a9bb22b5c5a0aa4
+ 208816ea84250e01.a4b78aaaf5d12914.014773bccbdaed7f.0f3f0b1c678a0309
+ 0000000000000000.0000000000000000.1e6550965e0fca1d.fcee643009d9b781
+ 27e8fc15f4eb3983.ee0c099a3c18ebb7.fa7c2ade9cf3ecd8.338c2aae8716787f
+ 18cee728d38b6be8
+
+VAESDEC(reg)
+ before
+ 06ddbdfd1830d4ab.0e5040dd00c3f35b.4cab133431b35118.54561911248ba39c
+ 5705a899f290ee74.b2ef0b016aa3bf7e.a0fdf41f2d040b68.bec011e93ce5cf55
+ 6991a568fc37f6ee.ee8fd76e4d975a18.464ea8c7cb965554.13868d54ff0e2b2e
+ 96cfaed6d2b228c6.a0fd220ec6ac8054.9ae92c98a8f56a88.2f73093c89117453
+ ee55028ff7fa66f1
+ after
+ 0000000000000000.0000000000000000.99cccadfcda3054e.5335b6f3b37dfdfa
+ 5705a899f290ee74.b2ef0b016aa3bf7e.a0fdf41f2d040b68.bec011e93ce5cf55
+ 6991a568fc37f6ee.ee8fd76e4d975a18.464ea8c7cb965554.13868d54ff0e2b2e
+ 96cfaed6d2b228c6.a0fd220ec6ac8054.9ae92c98a8f56a88.2f73093c89117453
+ ee55028ff7fa66f1
+VAESDEC(mem)
+ before
+ 2cf6f23864d6bc34.3b09c14f118cc0a8.a30567cef0edec5f.f81b7bfe5fae88af
+ c4235723edb03347.b58cda405451f93f.d372239be8665c65.bc3191668c4ce976
+ 94a8ad3cae948757.5ea4f313388e1037.0c12d05fc9248a91.42756b3acc5cc988
+ 77516e6fc18f7390.939d0a3658ce413e.29afec08af323210.e63303e8bb696692
+ 03b957daf4fffa40
+ after
+ 2cf6f23864d6bc34.3b09c14f118cc0a8.a30567cef0edec5f.f81b7bfe5fae88af
+ c4235723edb03347.b58cda405451f93f.d372239be8665c65.bc3191668c4ce976
+ 0000000000000000.0000000000000000.51ccfbf8e26f28ef.5574329bb0271acd
+ 77516e6fc18f7390.939d0a3658ce413e.29afec08af323210.e63303e8bb696692
+ 03b957daf4fffa40
+
+VAESDECLAST(reg)
+ before
+ f752627e13aac23d.48ea17a945acb51d.b1c21a13519dc7fe.0817f281b79c120d
+ 1d49203fb5f7f936.e53e25d453f7072b.12611f18be88e023.84145eb5fd6fe4b5
+ d1eb8e897671dcd6.291b13de0a7d25e5.13c415b03c1ac65a.7873ac929cb66533
+ 6e84a6c8f1a5a7ca.ef4b5db18349cd78.1038f94766dfb54f.c2005903b07e50b5
+ 3c86e0f456d16364
+ after
+ 0000000000000000.0000000000000000.325fb584051c5b68.22ab0240d321aee1
+ 1d49203fb5f7f936.e53e25d453f7072b.12611f18be88e023.84145eb5fd6fe4b5
+ d1eb8e897671dcd6.291b13de0a7d25e5.13c415b03c1ac65a.7873ac929cb66533
+ 6e84a6c8f1a5a7ca.ef4b5db18349cd78.1038f94766dfb54f.c2005903b07e50b5
+ 3c86e0f456d16364
+VAESDECLAST(mem)
+ before
+ c4d3bd52a9bd586f.52606668c21e96bd.159b803bdc68b90f.6609c649d964ebad
+ 34b16c07c64eebff.d7cbc9d58668e45c.75d7f76731e4a6d7.6f8378223034a221
+ 6aed6a00c88fda43.5b10cc7bd810cf53.edcb3d209dcc4ffc.88f20b3e07db1656
+ 4053312acc8cdf65.397d69c655a0904d.5742d1543c2972a9.0da17b09fbe685f9
+ 5addc5f0a8e029b6
+ after
+ c4d3bd52a9bd586f.52606668c21e96bd.159b803bdc68b90f.6609c649d964ebad
+ 34b16c07c64eebff.d7cbc9d58668e45c.75d7f76731e4a6d7.6f8378223034a221
+ 0000000000000000.0000000000000000.1dda4531e3407802.4804dcdddfcacdd6
+ 4053312acc8cdf65.397d69c655a0904d.5742d1543c2972a9.0da17b09fbe685f9
+ 5addc5f0a8e029b6
+
+VAESDECLAST(reg)
+ before
+ cbf3e45da9563f38.93af3f6fed51b792.cc5c9e2398a766f7.900a2cee2b09c90b
+ bc2dd4be9ad2032c.40cd10bd48eb1df5.72fa66fc3eae8bfd.75edcbda8677104e
+ 89d8917d18e3b03d.21781efff865cfbb.85a3bdbfe2433c0a.e0b82b05687f059d
+ 8e3f1808bf128318.137ee7211acc870f.62a39fd721f2b5cb.ae37c759ed2e6224
+ bc361bc3328fe411
+ after
+ 0000000000000000.0000000000000000.59f073eafc41652b.31ac577f57c1d62b
+ bc2dd4be9ad2032c.40cd10bd48eb1df5.72fa66fc3eae8bfd.75edcbda8677104e
+ 89d8917d18e3b03d.21781efff865cfbb.85a3bdbfe2433c0a.e0b82b05687f059d
+ 8e3f1808bf128318.137ee7211acc870f.62a39fd721f2b5cb.ae37c759ed2e6224
+ bc361bc3328fe411
+VAESDECLAST(mem)
+ before
+ e480a43052af478d.26b063ca29edb869.f3a9e50fc92b011e.664609af964532eb
+ 03e3dc8b6a9946c7.af75702ff5ff8adb.9bc696b5228efb14.ebd7f6b5ddcaee17
+ f52941bf95599ee9.84db3aa3bdd4371a.e8a176ff40012f1c.4ea36254930d26fa
+ 96204ebaf0fc0b20.012fbe921df9f9d4.b606ffd93f915a63.ecf749f854981541
+ 1f1da80ebbf9f898
+ after
+ e480a43052af478d.26b063ca29edb869.f3a9e50fc92b011e.664609af964532eb
+ 03e3dc8b6a9946c7.af75702ff5ff8adb.9bc696b5228efb14.ebd7f6b5ddcaee17
+ 0000000000000000.0000000000000000.3aa486dd213bd785.f281907daaa3076c
+ 96204ebaf0fc0b20.012fbe921df9f9d4.b606ffd93f915a63.ecf749f854981541
+ 1f1da80ebbf9f898
+
+VAESDECLAST(reg)
+ before
+ 4462790064bc0caa.c2928067968c4897.82bbf668b2f90cb3.e1c0af2f3c493814
+ b711ba3bec6b8a24.564b51b2a418127b.62cbe0921761ae63.459d01ee5336845c
+ d578672cef94b1b1.2c193f8735a925f7.ffad777ae8bc1991.be6771009e63fb67
+ f8e17a3d07c3bbfe.21c7c5d2664d3d38.b4abb88ec2968ae9.28eb7b533cdc5960
+ 5ff59cd247ae5974
+ after
+ 0000000000000000.0000000000000000.afd8c90e43981091.393e3e99f6bb5bc0
+ b711ba3bec6b8a24.564b51b2a418127b.62cbe0921761ae63.459d01ee5336845c
+ d578672cef94b1b1.2c193f8735a925f7.ffad777ae8bc1991.be6771009e63fb67
+ f8e17a3d07c3bbfe.21c7c5d2664d3d38.b4abb88ec2968ae9.28eb7b533cdc5960
+ 5ff59cd247ae5974
+VAESDECLAST(mem)
+ before
+ 3f514e69dbe4b9ce.7d99f1dcd382e5b7.11205f7f520f156a.dc139d38417c3c16
+ a4cb0f03158a339b.c0edc674ed606a87.d8f1897b15fc6ab8.d52f24e600f96cc5
+ 6a2e5b8e10ad8307.1d26f770f1e6881b.5106c0b0cd1ff84e.f94c48039c9956a2
+ 6d48acf5e958673d.f093803e7ca2791e.5a2b7f0c93847b5a.a6b605fbb0e83658
+ 36b8573ad8734894
+ after
+ 3f514e69dbe4b9ce.7d99f1dcd382e5b7.11205f7f520f156a.dc139d38417c3c16
+ a4cb0f03158a339b.c0edc674ed606a87.d8f1897b15fc6ab8.d52f24e600f96cc5
+ 0000000000000000.0000000000000000.436e077c7f66b3f0.f33825cdf429ce11
+ 6d48acf5e958673d.f093803e7ca2791e.5a2b7f0c93847b5a.a6b605fbb0e83658
+ 36b8573ad8734894
+
+VAESIMC(reg)
+ before
+ 07a03b2cb1c6c701.89e38025bb97996a.957f5b49291f7a3d.ce2c42798538ae06
+ 73b8ac3dd66bf04c.9acc5208a377d5b9.683586fe94e9c624.89d585e5be464e7e
+ d84ea6d9e4f0fe20.7ccf9e8bbc03d957.c503fcc75b8d9a7e.67f1c53b5bba17ef
+ 90ac256c77e02e2a.0ab7e09b22475f70.0833b911179632f8.444e7c6778a1c485
+ fbb628552f06126c
+ after
+ 0000000000000000.0000000000000000.71fda9d8816224f5.64c616dcd2fdac9a
+ 73b8ac3dd66bf04c.9acc5208a377d5b9.683586fe94e9c624.89d585e5be464e7e
+ d84ea6d9e4f0fe20.7ccf9e8bbc03d957.c503fcc75b8d9a7e.67f1c53b5bba17ef
+ 90ac256c77e02e2a.0ab7e09b22475f70.0833b911179632f8.444e7c6778a1c485
+ fbb628552f06126c
+VAESIMC(mem)
+ before
+ 6af644f19ff5bdcf.f81f256329c8bd16.22529522f250242f.8d12b9486691ca3d
+ 6cda4d27e27b80da.6df2a3289933e48f.9f6a370e4829e4c0.afecf9d9e4089dfa
+ dc2dbde314a319ba.49739a2961ade242.5ccd444a3fde5a51.cc0c742f2c8ae9db
+ 98bd1212527a429b.e9ec06d11dc3f1da.374537c1f37c430c.3fc026b5daa0e78b
+ 64520bd98bd8d6b7
+ after
+ 6af644f19ff5bdcf.f81f256329c8bd16.22529522f250242f.8d12b9486691ca3d
+ 6cda4d27e27b80da.6df2a3289933e48f.9f6a370e4829e4c0.afecf9d9e4089dfa
+ 0000000000000000.0000000000000000.6dcc4f29b07e2f48.ff7717f156e2fa4e
+ 98bd1212527a429b.e9ec06d11dc3f1da.374537c1f37c430c.3fc026b5daa0e78b
+ 64520bd98bd8d6b7
+
+VAESIMC(reg)
+ before
+ 960f1f06dbbdf00a.7b54c79eb70ab7a8.aaabe38c69004e04.0b9f8d61810e5b1d
+ 33435fa865dc7231.60bf58755f61360e.e6fa2ec5e3f1346c.b3a7c01505a05eb1
+ 963ac62bc5c098d7.25ca4281678b79f9.fa26e2ea2420e1bd.0d284eca9a3f07f4
+ 1a4050fb98f59da9.a441ffb0eb933d94.427bfb67ca1b8fa4.f3f0b26a5cf61311
+ 43c969e268d23e35
+ after
+ 0000000000000000.0000000000000000.94b63fc99ac4efe9.51194ba2d4bfe5d8
+ 33435fa865dc7231.60bf58755f61360e.e6fa2ec5e3f1346c.b3a7c01505a05eb1
+ 963ac62bc5c098d7.25ca4281678b79f9.fa26e2ea2420e1bd.0d284eca9a3f07f4
+ 1a4050fb98f59da9.a441ffb0eb933d94.427bfb67ca1b8fa4.f3f0b26a5cf61311
+ 43c969e268d23e35
+VAESIMC(mem)
+ before
+ d780ed1ed9dd438c.1da1f9847907be53.bbf00ded06853d0b.1a4475a6716e7bcd
+ 8de1bc0bcc25df41.f9a8be3305833780.44a3e724d56d378c.decf4c14b4a3e0e3
+ 3fb851945cb6ce80.0ca29972d7f544dd.1c250a417358e540.ea667d1d2f49fb92
+ cad128a4a69bcc77.b0dc88af8ce72016.2043f030fc510356.9a56032e7fe90887
+ 4aebdab24011436e
+ after
+ d780ed1ed9dd438c.1da1f9847907be53.bbf00ded06853d0b.1a4475a6716e7bcd
+ 8de1bc0bcc25df41.f9a8be3305833780.44a3e724d56d378c.decf4c14b4a3e0e3
+ 0000000000000000.0000000000000000.7d9686c69afcd003.57d43937ac7cef96
+ cad128a4a69bcc77.b0dc88af8ce72016.2043f030fc510356.9a56032e7fe90887
+ 4aebdab24011436e
+
+VAESIMC(reg)
+ before
+ 5671fe140d4ce7f2.0bf7bd29c5e0944f.439f8754bfe708d6.2aca17dd8d654ff8
+ 1a346cc2822631c0.dcf88d0ed691e337.1f3a90cf0d8038ca.1784fa35419e8353
+ f2801e273c2c5d84.1a9e133ff4bb7559.a2f8a18b113feb9d.c43d1522350b5c92
+ 3aa012afd6e9a7e9.a1b6cba83b6905e2.2624b4f467af5efc.0bc3e59285b596e2
+ c9e1e46f4baaec6e
+ after
+ 0000000000000000.0000000000000000.2146c2d579733361.9e4cc8d4ee147c76
+ 1a346cc2822631c0.dcf88d0ed691e337.1f3a90cf0d8038ca.1784fa35419e8353
+ f2801e273c2c5d84.1a9e133ff4bb7559.a2f8a18b113feb9d.c43d1522350b5c92
+ 3aa012afd6e9a7e9.a1b6cba83b6905e2.2624b4f467af5efc.0bc3e59285b596e2
+ c9e1e46f4baaec6e
+VAESIMC(mem)
+ before
+ da6290a7a6f51b63.4de144c6edea4a9c.4e0c3135c8a851fd.080cc876ac5ccd92
+ 1a136425afa3dfed.898faed81cba8348.fb6cc1d2b78313d7.a5fad67d7cd3740c
+ 66c0ddd485bff337.49f64e5100e58e9a.85a1f86c2306079b.573bdb75729f8e16
+ 983575a24155146e.e9621e9d34f7a63e.c87951ed283eea76.7b1bd4ca2a4c585b
+ 6de6bce941670e88
+ after
+ da6290a7a6f51b63.4de144c6edea4a9c.4e0c3135c8a851fd.080cc876ac5ccd92
+ 1a136425afa3dfed.898faed81cba8348.fb6cc1d2b78313d7.a5fad67d7cd3740c
+ 0000000000000000.0000000000000000.1f2cec9906d11c07.c4ea6bffef12cb99
+ 983575a24155146e.e9621e9d34f7a63e.c87951ed283eea76.7b1bd4ca2a4c585b
+ 6de6bce941670e88
+
+VAESKEYGENASSIST_0x00(reg)
+ before
+ 89e78f3c537beb48.8d3eaa7b0171febd.c41f1c29557d08df.a0be4842e3367994
+ 2c6c4a31fa152d48.21a6f749e1206d51.3878445ffe02f02a.e93d595870fa6d20
+ b0bfe732d5bf0e34.303bd8f9fc6e1c56.a0bb90adcb1399ca.7fc2011ae9968547
+ 722d64ad7e07cab7.96c7c9776f65c8f7.5732fe7e5a3b416c.3e19bb746d177b34
+ 020e035116890c14
+ after
+ 0000000000000000.0000000000000000.95e0ea60e0ea6095.a2d2257cd2257ca2
+ 2c6c4a31fa152d48.21a6f749e1206d51.3878445ffe02f02a.e93d595870fa6d20
+ b0bfe732d5bf0e34.303bd8f9fc6e1c56.a0bb90adcb1399ca.7fc2011ae9968547
+ 722d64ad7e07cab7.96c7c9776f65c8f7.5732fe7e5a3b416c.3e19bb746d177b34
+ 020e035116890c14
+VAESKEYGENASSIST_0x00(mem)
+ before
+ a76c559f00f6f413.ce02bc0d91799f7e.2f1747b055132d61.bb2a893e440622bb
+ 09012d4a476cee5c.208aebbeaba0c734.d6f7cd8eca8307bf.26ef2d5827017864
+ 0497083c09f7b71b.c410ee2c67087e86.6933d7ffebc2113e.f6cce63a9fb78113
+ 73fb61625fa10b7e.16e2bfc3613d0220.c396e1eed4db080a.850fb14f46b47773
+ 31028904bb859731
+ after
+ a76c559f00f6f413.ce02bc0d91799f7e.2f1747b055132d61.bb2a893e440622bb
+ 09012d4a476cee5c.208aebbeaba0c734.d6f7cd8eca8307bf.26ef2d5827017864
+ 0000000000000000.0000000000000000.e715f0a015f0a0e7.b2eae5a7eae5a7b2
+ 73fb61625fa10b7e.16e2bfc3613d0220.c396e1eed4db080a.850fb14f46b47773
+ 31028904bb859731
+
+VAESKEYGENASSIST_0x00(reg)
+ before
+ 54f26ac398b51cf9.34f9b4a86778a5af.724a5cef37cc8dad.c0ee67469fdaa84e
+ 4b2b50f979d04476.225c7dfb3d8843da.3495c01c82405cda.3c05e6f56bccac36
+ 73f93713fb634954.19f23945fcdb9f2c.b70fe8b7e026ab52.12a8d9e652bcd1f0
+ 26a81c7bb9f96741.f4856374c17f75d1.5904ce2aed08b5c2.20a3bc0570b7d3a6
+ 41c20c3fe2c76d84
+ after
+ 0000000000000000.0000000000000000.a9a9769ba9769ba9.8ec9c235c9c2358e
+ 4b2b50f979d04476.225c7dfb3d8843da.3495c01c82405cda.3c05e6f56bccac36
+ 73f93713fb634954.19f23945fcdb9f2c.b70fe8b7e026ab52.12a8d9e652bcd1f0
+ 26a81c7bb9f96741.f4856374c17f75d1.5904ce2aed08b5c2.20a3bc0570b7d3a6
+ 41c20c3fe2c76d84
+VAESKEYGENASSIST_0x00(mem)
+ before
+ 50d1437ec3fa5db7.c184fa9f501edce6.91e37773a78083f4.75c070e34475b7d6
+ 2b9bdfaf305c5d6b.a1d8cdea5b5fe2f2.cbd6f12ecae883c2.678ec94d81f6ed39
+ adee5bbf44f729cb.20f191c77747b60f.7d2b4d9047c53267.8abbd5d341199397
+ b19433981cd97f04.9b1c43a43f6294ea.85ae08883a234b0e.3c9491e32069e49e
+ d863f7e8b9731df8
+ after
+ 50d1437ec3fa5db7.c184fa9f501edce6.91e37773a78083f4.75c070e34475b7d6
+ 2b9bdfaf305c5d6b.a1d8cdea5b5fe2f2.cbd6f12ecae883c2.678ec94d81f6ed39
+ 0000000000000000.0000000000000000.8f8111f58111f58f.119dba519dba5111
+ b19433981cd97f04.9b1c43a43f6294ea.85ae08883a234b0e.3c9491e32069e49e
+ d863f7e8b9731df8
+
+VAESKEYGENASSIST_0x00(reg)
+ before
+ b975054ea8c27a51.155ae428d30e1942.6ea3deec503db72e.bd2a9dffbd0d8ce4
+ 3d15b6818ae23656.b30ce85a85a1b4b0.f5d25e0b45635c88.036d88e2ef8faf14
+ bf9107eefa5f8eb3.6976bd1a4f9e0b7b.8cf7bf6eba60bfa3.3141451deab570cb
+ 9a33f2ff95c6be13.1163de544d11dcce.8f5dfd7f4cc11b2c.2573509dca8c8d34
+ b9cf264cac1fc07c
+ after
+ 0000000000000000.0000000000000000.9f6468086468089f.a4c7836ec7836ea4
+ 3d15b6818ae23656.b30ce85a85a1b4b0.f5d25e0b45635c88.036d88e2ef8faf14
+ bf9107eefa5f8eb3.6976bd1a4f9e0b7b.8cf7bf6eba60bfa3.3141451deab570cb
+ 9a33f2ff95c6be13.1163de544d11dcce.8f5dfd7f4cc11b2c.2573509dca8c8d34
+ b9cf264cac1fc07c
+VAESKEYGENASSIST_0x00(mem)
+ before
+ cb214218ab7bc6cf.2c497521f6a30223.88a1c8f49a07e1d6.5a4f15ab9711aecf
+ 353520ebe4aa5a58.cf1d8bc1ba80958f.abfaf5e6528bd6be.491a025f36dcb137
+ d4d63db372bb3a44.e1fc304a7cebb402.543be31692aa79b3.b80ac005c5af6311
+ 84d2135b71b720bf.bc326127d86f9b28.60300d70766f84e1.036b4b0be115fe08
+ 8689a0dc259bc0c9
+ after
+ cb214218ab7bc6cf.2c497521f6a30223.88a1c8f49a07e1d6.5a4f15ab9711aecf
+ 353520ebe4aa5a58.cf1d8bc1ba80958f.abfaf5e6528bd6be.491a025f36dcb137
+ 0000000000000000.0000000000000000.bfc432e8c432e8bf.62be8459be845962
+ 84d2135b71b720bf.bc326127d86f9b28.60300d70766f84e1.036b4b0be115fe08
+ 8689a0dc259bc0c9
+
+VAESKEYGENASSIST_0x31(reg)
+ before
+ 9dafbae42ecce2ff.22f320cffeacc8f4.bd0a18c66c9985af.aca5efe118e6b473
+ a42b948f9834a358.8806dffb35a5f00f.41d25392d1f4af41.12660653971bc596
+ f7472d49fd5f3d7d.93d7cccb31af523e.a2d40df7a50c558a.6f3eccb40d1b7275
+ f2507e7efcdaed1d.1f32642b0fd5abaa.3d5d4261846eb337.9ffabfee96f1783d
+ 7e675aef4faa931a
+ after
+ 0000000000000000.0000000000000000.683a48e63a48d768.8da8b27aa8b24b8d
+ a42b948f9834a358.8806dffb35a5f00f.41d25392d1f4af41.12660653971bc596
+ f7472d49fd5f3d7d.93d7cccb31af523e.a2d40df7a50c558a.6f3eccb40d1b7275
+ f2507e7efcdaed1d.1f32642b0fd5abaa.3d5d4261846eb337.9ffabfee96f1783d
+ 7e675aef4faa931a
+VAESKEYGENASSIST_0x31(mem)
+ before
+ e94f19a253517e37.f092859a2e30efe2.08e22108e923b782.6fb9ef3c09a504f4
+ ba7e79f3bef2f6c1.4f593c0932ee7e78.2bb5814cdea531f0.92340ff5d03d856c
+ cec2f5ceae9ab7e3.6af1a238a19fd78c.627500e50868d620.031a9ef676c3724c
+ 01e6091f3c537dca.9ca5b09119cf36ca.8aef18bd83776240.1eb698ac96c2063f
+ 3f56f984cdc67ef2
+ after
+ e94f19a253517e37.f092859a2e30efe2.08e22108e923b782.6fb9ef3c09a504f4
+ ba7e79f3bef2f6c1.4f593c0932ee7e78.2bb5814cdea531f0.92340ff5d03d856c
+ 0000000000000000.0000000000000000.303098cc3098fd30.eba856eea856dfeb
+ 01e6091f3c537dca.9ca5b09119cf36ca.8aef18bd83776240.1eb698ac96c2063f
+ 3f56f984cdc67ef2
+
+VAESKEYGENASSIST_0x31(reg)
+ before
+ c244bee9b75c1611.2fb531d3862c03a2.43c26382360ad7dd.7fef46c26cdf9079
+ 04cde246ee0f0a47.34fce9d4a82e0696.ba94b87693ddf572.1d4107dfdeab1efa
+ 5f3d6109116c9541.ec88ae0fbd6742d3.5c67aad8cdd4cd35.40b1d600f6e7c5ed
+ 30e0379db9fdf4aa.3222fb71e1e37384.878735167f799bd1.c30a2f11cfa0447e
+ 841a8ffe86e156da
+ after
+ 0000000000000000.0000000000000000.614a859d4a85ac61.6309c8c709c8f663
+ 04cde246ee0f0a47.34fce9d4a82e0696.ba94b87693ddf572.1d4107dfdeab1efa
+ 5f3d6109116c9541.ec88ae0fbd6742d3.5c67aad8cdd4cd35.40b1d600f6e7c5ed
+ 30e0379db9fdf4aa.3222fb71e1e37384.878735167f799bd1.c30a2f11cfa0447e
+ 841a8ffe86e156da
+VAESKEYGENASSIST_0x31(mem)
+ before
+ 5eab70b336b6b62d.d301606e8551632f.e4994ce431ac54d6.9540559b455a9af3
+ 2d8a501cfc2c20a3.a4eed9e80ef11e7c.ddb81d56c9d0a2f5.e4de07d3bc020746
+ cd83aa25f34e5266.fef19d77f26b603c.f94aeab2c45b190c.ceac462a7ffe1e77
+ 1961fbbb382806a5.3f57a888cd4a661c.141d30e43e577448.b0f70e0d2bd91b31
+ e70b5be65c1f3921
+ after
+ 5eab70b336b6b62d.d301606e8551632f.e4994ce431ac54d6.9540559b455a9af3
+ 2d8a501cfc2c20a3.a4eed9e80ef11e7c.ddb81d56c9d0a2f5.e4de07d3bc020746
+ 0000000000000000.0000000000000000.6969ee1869ee2969.142a09cd2a09fc14
+ 1961fbbb382806a5.3f57a888cd4a661c.141d30e43e577448.b0f70e0d2bd91b31
+ e70b5be65c1f3921
+
+VAESKEYGENASSIST_0x31(reg)
+ before
+ cd342a23ac5db5f3.eff2bdc8e6c7f98a.c26cf6853a1a6cc7.09fb6ad854d270d4
+ bfbe752eba1ecb52.2a006e3a1936e742.e37c84dcd668adea.b6b1147a21d8c9dd
+ 1af53a751feeb6eb.a65989fcee818bf8.fed34df73cbf6631.f60baab6c2733a8e
+ 382474627a5ab369.3ec78afa81b5a2d9.6fbc4d4408acd347.a5d4a97852b18115
+ 9eda8cadee9e589b
+ after
+ 0000000000000000.0000000000000000.68bb66d2bb66e368.4e422b9d422bac4e
+ bfbe752eba1ecb52.2a006e3a1936e742.e37c84dcd668adea.b6b1147a21d8c9dd
+ 1af53a751feeb6eb.a65989fcee818bf8.fed34df73cbf6631.f60baab6c2733a8e
+ 382474627a5ab369.3ec78afa81b5a2d9.6fbc4d4408acd347.a5d4a97852b18115
+ 9eda8cadee9e589b
+VAESKEYGENASSIST_0x31(mem)
+ before
+ bfe7cf3fb1457b4f.7698206364edfe79.d017ee20eddde811.9185802ed7ba2fd8
+ e2c8ee1cb8b2a85a.309d38e37b33d3c7.36152f5a4e0619cb.c278e2214575b892
+ e54a662f1ef199eb.c27fba4e5bb96dfe.4e8ccb94c13af033.5de27089ec6aa81f
+ a236b163ff0f0b2c.898aa1109f0a09cb.f24a3dba61872a77.bd0f25d26b233b2b
+ 404bfd685c2faf63
+ after
+ bfe7cf3fb1457b4f.7698206364edfe79.d017ee20eddde811.9185802ed7ba2fd8
+ e2c8ee1cb8b2a85a.309d38e37b33d3c7.36152f5a4e0619cb.c278e2214575b892
+ 0000000000000000.0000000000000000.b770f01970f028b7.318197fc8197cd31
+ a236b163ff0f0b2c.898aa1109f0a09cb.f24a3dba61872a77.bd0f25d26b233b2b
+ 404bfd685c2faf63
+
+VAESKEYGENASSIST_0xB2(reg)
+ before
+ 40e1f4b75b173e73.f75b4da67817b94a.df0ae995e4b3e3d9.001901b84bf983c1
+ 1b1f072b05692506.be84b5e3a5156170.214a8e4ac53e37d5.52c6947b9b9bb63d
+ 2b4f3131f5b09fc9.d57c6606a116bdcb.ab988d99de39406b.c61d71ed6b798018
+ cebe6e33c879ea68.1610dafb88258986.d93ee1f0cc303b46.36ea14fcda9f9d7e
+ 7ff9f992011ac99a
+ after
+ 0000000000000000.0000000000000000.ee6246ef62465dee.55b4a411b4a4a355
+ 1b1f072b05692506.be84b5e3a5156170.214a8e4ac53e37d5.52c6947b9b9bb63d
+ 2b4f3131f5b09fc9.d57c6606a116bdcb.ab988d99de39406b.c61d71ed6b798018
+ cebe6e33c879ea68.1610dafb88258986.d93ee1f0cc303b46.36ea14fcda9f9d7e
+ 7ff9f992011ac99a
+VAESKEYGENASSIST_0xB2(mem)
+ before
+ 7e159c9dfef5bf99.5eb8ba9f194f408e.5e0d8fae774f83ce.078986b92bae6313
+ 0d0c7a08ed3d3ca6.398911e084bedde7.8a3d000c8a9f65cf.91c57862963ff67d
+ 09a80dbfe9fdfcee.b97c7061a753ff21.746ca9ffdc21ecb4.d33eb456a96f2e31
+ 4eb6d3ae0f41ba9d.3cdfd2901b99e0e6.f968067589e1d4aa.283f350001cb48db
+ ee16f7ce39de7f26
+ after
+ 7e159c9dfef5bf99.5eb8ba9f194f408e.5e0d8fae774f83ce.078986b92bae6313
+ 0d0c7a08ed3d3ca6.398911e084bedde7.8a3d000c8a9f65cf.91c57862963ff67d
+ 0000000000000000.0000000000000000.e458d7c158d773e4.56c5a7f6c5a74456
+ 4eb6d3ae0f41ba9d.3cdfd2901b99e0e6.f968067589e1d4aa.283f350001cb48db
+ ee16f7ce39de7f26
+
+VAESKEYGENASSIST_0xB2(reg)
+ before
+ 800df62bee3510bf.b90248c17a1534de.1cfc33d87e1cbde2.f5fc9458aeecd8dd
+ 3a712e84bb5a3751.2458e6e4468624de.b6208fa56c69d1c2.44f3ce96664db578
+ 788e9c433ddc3089.6c832b04909f46c8.6698e364800b5a32.c31a301ace1127a7
+ 95b03bd50f443613.6d51920b746d57c9.89ad297f568e92dd.4c3d36d00143e997
+ bc285da41cefb874
+ after
+ 0000000000000000.0000000000000000.433346a333461143.a22ea2b62ea204a2
+ 3a712e84bb5a3751.2458e6e4468624de.b6208fa56c69d1c2.44f3ce96664db578
+ 788e9c433ddc3089.6c832b04909f46c8.6698e364800b5a32.c31a301ace1127a7
+ 95b03bd50f443613.6d51920b746d57c9.89ad297f568e92dd.4c3d36d00143e997
+ bc285da41cefb874
+VAESKEYGENASSIST_0xB2(mem)
+ before
+ efa720823a22506a.ef2207a7ce20879a.038c97e70dfb140d.79ae5f638b7fb570
+ c185fa5677e76da4.e132fc2315fb5cca.0a01b682775536bf.93e6807dba690196
+ 0e906a0cf04aca4e.c62a16b78062f451.5e7c6ccacf887c0c.33a0893780d8b0fc
+ b292e990c1582495.fc5752cdace089d9.dbc934aa309fa01f.b52974ff7959ff4e
+ 75cd3f403f772a37
+ after
+ efa720823a22506a.ef2207a7ce20879a.038c97e70dfb140d.79ae5f638b7fb570
+ c185fa5677e76da4.e132fc2315fb5cca.0a01b682775536bf.93e6807dba690196
+ 0000000000000000.0000000000000000.947b643a7b648894.fbb6e47db6e4cffb
+ b292e990c1582495.fc5752cdace089d9.dbc934aa309fa01f.b52974ff7959ff4e
+ 75cd3f403f772a37
+
+VAESKEYGENASSIST_0xB2(reg)
+ before
+ cfd8e56571bf6c64.8958f5cf051b37a5.dd05abd33501580e.5db48a0eb7a65f25
+ 1f9662dca8bb0280.6fae08b3d9a2bfa9.c7801d34b6529d9d.c008eae27faa754a
+ c153b31083f92838.3f60a02a58f677ce.1414a55ccb5e9332.e093d012a5b69db9
+ 115ad36e9b051938.d739391f9e251c40.220c3db711b17778.991fb98a44d6949f
+ c779203679171627
+ after
+ 0000000000000000.0000000000000000.4afafab4fafa064a.c9e1dcc2e1dc70c9
+ 1f9662dca8bb0280.6fae08b3d9a2bfa9.c7801d34b6529d9d.c008eae27faa754a
+ c153b31083f92838.3f60a02a58f677ce.1414a55ccb5e9332.e093d012a5b69db9
+ 115ad36e9b051938.d739391f9e251c40.220c3db711b17778.991fb98a44d6949f
+ c779203679171627
+VAESKEYGENASSIST_0xB2(mem)
+ before
+ 456d81035f84de7e.6bf8be608e6a132b.12074d7ec83b6a2a.4bb6e3b124d7851c
+ f1c758db1229aad0.2b7a7053f8b450be.cc945a32f1421cb9.ed5c92b79f5df9ca
+ a65222acaf133448.ad2ae5b3746f0c9c.e1addb293648ef18.624b46331ecf0e2d
+ 3fdc5960524d3813.4d541aed9f288572.2c1e4c4fb2599f74.07cffc923eb701f1
+ 3934ae419aa30ec4
+ after
+ 456d81035f84de7e.6bf8be608e6a132b.12074d7ec83b6a2a.4bb6e3b124d7851c
+ f1c758db1229aad0.2b7a7053f8b450be.cc945a32f1421cb9.ed5c92b79f5df9ca
+ 0000000000000000.0000000000000000.f3c9c551c9c5e3f3.c8b34ea3b34e11c8
+ 3fdc5960524d3813.4d541aed9f288572.2c1e4c4fb2599f74.07cffc923eb701f1
+ 3934ae419aa30ec4
+
+VAESKEYGENASSIST_0xFF(reg)
+ before
+ 52c55aabcf1f704f.9a2f7be516e3745c.6746096c146af5ec.8bb3298e8280e7f9
+ afd0fb3b78b56541.9218042618e2a250.564bb09b6fc299b5.d938efd3c1c985d2
+ ac9f8e5f32f32744.02636e0f72557f1a.78ae0be84dbbac79.f178190a8c40332b
+ a67f0d829865f204.c8dc378c4348c6e7.28bc14be49e16be6.b1412320fef2ad32
+ f35d89ff34eab111
+ after
+ 0000000000000000.0000000000000000.9bbce4d4bce42b9b.67a1bc2ba1bcd467
+ afd0fb3b78b56541.9218042618e2a250.564bb09b6fc299b5.d938efd3c1c985d2
+ ac9f8e5f32f32744.02636e0f72557f1a.78ae0be84dbbac79.f178190a8c40332b
+ a67f0d829865f204.c8dc378c4348c6e7.28bc14be49e16be6.b1412320fef2ad32
+ f35d89ff34eab111
+VAESKEYGENASSIST_0xFF(mem)
+ before
+ 9599c7954934f9f4.f7bc76104695032f.be4ed989a5c835e3.c1c1c98900c012a6
+ 71c15acd5add4208.fca2c475da12976f.c287d2f2b4e08639.a10925b50ee5dd65
+ 65a1bd9382f04779.117df31ded65e770.ae519eb38d9c7516.23e024ae0edc07d0
+ 4b046cd3dd7ac672.929800751d1c32df.6079b7b94b09c0a6.a292c2e09c2fce93
+ 7c6afcb8556c6b59
+ after
+ 9599c7954934f9f4.f7bc76104695032f.be4ed989a5c835e3.c1c1c98900c012a6
+ 71c15acd5add4208.fca2c475da12976f.c287d2f2b4e08639.a10925b50ee5dd65
+ 0000000000000000.0000000000000000.a7ae2fcaae2f35a7.a77878227878dda7
+ 4b046cd3dd7ac672.929800751d1c32df.6079b7b94b09c0a6.a292c2e09c2fce93
+ 7c6afcb8556c6b59
+
+VAESKEYGENASSIST_0xFF(reg)
+ before
+ 0bb5cca0d41e1dcf.01b8e37988857920.db40e5e706c2b268.b2cb9bee0b322114
+ adbf3006b6d21ea1.61879f719f201caf.48c2a0e043e3a4b6.8213c540e824558c
+ bcd423549613ab7a.483e1ba73d546d4a.35682ccd700c4475.aa1db199ffea173c
+ 9640a2f8106d0006.93a9d3077e2f261d.fe7f85192ac8cd53.07b4dbe76b90254e
+ 76a6c015492239ee
+ after
+ 0000000000000000.0000000000000000.bd96458e964571bd.eeaca437aca4c8ee
+ adbf3006b6d21ea1.61879f719f201caf.48c2a0e043e3a4b6.8213c540e824558c
+ bcd423549613ab7a.483e1ba73d546d4a.35682ccd700c4475.aa1db199ffea173c
+ 9640a2f8106d0006.93a9d3077e2f261d.fe7f85192ac8cd53.07b4dbe76b90254e
+ 76a6c015492239ee
+VAESKEYGENASSIST_0xFF(mem)
+ before
+ d1bddb0fb4ad0f49.954fa75dc16d58f3.1c94437e7fbc0455.ff52a82f0ca47cfa
+ f5c6a8c1c83c658b.164c30ef459ef1eb.c0cbe7f65b08c31e.942f907db32a8d16
+ be8da317a2dcf5df.7685381a378c059a.5b193c5d2f1d1ea4.1960396ebae93b55
+ 08de49fd5e987c72.0f44bc4a34c4d0ad.c94bbd9e160ad212.e9339f6ebe6ac460
+ 62f2bee95b3b62e6
+ after
+ d1bddb0fb4ad0f49.954fa75dc16d58f3.1c94437e7fbc0455.ff52a82f0ca47cfa
+ f5c6a8c1c83c658b.164c30ef459ef1eb.c0cbe7f65b08c31e.942f907db32a8d16
+ 0000000000000000.0000000000000000.f39c22e59c221af3.1516003d1600c215
+ 08de49fd5e987c72.0f44bc4a34c4d0ad.c94bbd9e160ad212.e9339f6ebe6ac460
+ 62f2bee95b3b62e6
+
+VAESKEYGENASSIST_0xFF(reg)
+ before
+ dfea934c2be75191.b0841460177cb66f.3ed6b6ebd7d18fd0.e72ee6a42dd89b94
+ bc661901ccfbcf0d.904d822ae9955e03.5f872469bc3f7eae.8f8c335d8f953458
+ 54b44c75da011607.85030e49f1ee315a.cfa20131809bd9f4.9e3221b4594c5a87
+ 051f2815f088632b.6b7335a74b93eb9f.e87549adbe70dc4d.f0eb2a95a60ac950
+ 6185ccec93da3ddd
+ after
+ 0000000000000000.0000000000000000.c78a3a838a3a7cc7.8d0b23020b23fd8d
+ bc661901ccfbcf0d.904d822ae9955e03.5f872469bc3f7eae.8f8c335d8f953458
+ 54b44c75da011607.85030e49f1ee315a.cfa20131809bd9f4.9e3221b4594c5a87
+ 051f2815f088632b.6b7335a74b93eb9f.e87549adbe70dc4d.f0eb2a95a60ac950
+ 6185ccec93da3ddd
+VAESKEYGENASSIST_0xFF(mem)
+ before
+ cdca82a63bc8715a.2af2aa4cab19f124.1e697132119047ff.074af84b134ac266
+ 1087c9adbae122f5.1e7acc85a642fd9f.7ab140d562f203a5.886f0b751bb6c8eb
+ 06891bee2d300cd7.3f038c2e7d8ec348.5b171d7c58c5d8be.c72e7d99703f2987
+ 8b99f656b0c1eb2f.e7d9e5b2cd8a7fca.9d6684130f138576.20d44a22b17223e7
+ efac6e7c77d9f0b6
+ after
+ cdca82a63bc8715a.2af2aa4cab19f124.1e697132119047ff.074af84b134ac266
+ 1087c9adbae122f5.1e7acc85a642fd9f.7ab140d562f203a5.886f0b751bb6c8eb
+ 0000000000000000.0000000000000000.2372f95c72f9a323.b3c5d6bec5d641b3
+ 8b99f656b0c1eb2f.e7d9e5b2cd8a7fca.9d6684130f138576.20d44a22b17223e7
+ efac6e7c77d9f0b6
+
+VPCLMULQDQ_0x00(reg)
+ before
+ 9004e6136102cda1.7a86d5d05ea17a27.7448d47d32c16dd1.1b6cf286a4eac5f8
+ 5f26ac530879f554.b11b354753db76eb.409b53fb47bfc80b.b3f3e1c132565371
+ b860bea80ac9a57a.0b2390a9ac7b9ba8.a91f6098a811cd22.40c8cfb0d561eb0c
+ f7fc177e037e19c0.646c64e1848ea48a.0921f6c0f242b7c2.9eb73740ab194bf6
+ a98c955bcd8a2d5a
+ after
+ 0000000000000000.0000000000000000.2c8c11225abcbb66.5296f4c8e09e2d4c
+ 5f26ac530879f554.b11b354753db76eb.409b53fb47bfc80b.b3f3e1c132565371
+ b860bea80ac9a57a.0b2390a9ac7b9ba8.a91f6098a811cd22.40c8cfb0d561eb0c
+ f7fc177e037e19c0.646c64e1848ea48a.0921f6c0f242b7c2.9eb73740ab194bf6
+ a98c955bcd8a2d5a
+VPCLMULQDQ_0x00(mem)
+ before
+ 3c1266ef59be4e66.7847b4428e248dd1.98c02cdbf81f4ebc.bdeb11e0c0dec398
+ 351725e66bc36a43.978d8f5e48483c5a.82ec6483243a556b.22caae62af722d50
+ 6f654e2e1ea53c20.af19a640cc756306.00bc88c522ec74c3.9209c7b45a893195
+ c5c95db28e6e8127.1e39f453b6383e83.edfb158e114069ef.6af65a405eaf0b14
+ 07dc62745671f678
+ after
+ 3c1266ef59be4e66.7847b4428e248dd1.98c02cdbf81f4ebc.bdeb11e0c0dec398
+ 351725e66bc36a43.978d8f5e48483c5a.82ec6483243a556b.22caae62af722d50
+ 0000000000000000.0000000000000000.16b3e0cfc6feb0bc.d94a6e02924ee780
+ c5c95db28e6e8127.1e39f453b6383e83.edfb158e114069ef.6af65a405eaf0b14
+ 07dc62745671f678
+
+VPCLMULQDQ_0x00(reg)
+ before
+ c306dcbbdf5a2f6e.150fce5ed82cf584.3f377502a31c097a.247786c80a42ee1c
+ fbc1c28194f6f1a2.39031e1e18eb5464.6e6126bb2eadff9a.83fa57612bffbf75
+ 0b59123212d27abf.0f70c8de68b659f3.060101e9f4775d8d.e452044390829a27
+ 4f1ac73af4790472.7124488ae799c15c.656304f891075fff.2549095c54d7395d
+ 20abe396940b5944
+ after
+ 0000000000000000.0000000000000000.735ad933a40eb309.588140f89eab40eb
+ fbc1c28194f6f1a2.39031e1e18eb5464.6e6126bb2eadff9a.83fa57612bffbf75
+ 0b59123212d27abf.0f70c8de68b659f3.060101e9f4775d8d.e452044390829a27
+ 4f1ac73af4790472.7124488ae799c15c.656304f891075fff.2549095c54d7395d
+ 20abe396940b5944
+VPCLMULQDQ_0x00(mem)
+ before
+ b3460ddf6b29b508.234fdd05d777cc66.3de91a0eafa048cc.e5d52a549fe8409d
+ b8e50322f53e0bd4.e34651ff56590d48.4d8cbb57dcd8a96e.e4a2706abda73d13
+ 0d53414b4f5515d5.eb491d950daa04c4.7fd9a54f8b4ca170.bd15d0a485cf920c
+ 8c5e4446957a8f37.97a53f3199f7ed85.ad9c56e4d709ecfb.cb7c486f93ec7b35
+ 6c21d338838b333a
+ after
+ b3460ddf6b29b508.234fdd05d777cc66.3de91a0eafa048cc.e5d52a549fe8409d
+ b8e50322f53e0bd4.e34651ff56590d48.4d8cbb57dcd8a96e.e4a2706abda73d13
+ 0000000000000000.0000000000000000.54dd9e776e523e7b.bf255339b613b977
+ 8c5e4446957a8f37.97a53f3199f7ed85.ad9c56e4d709ecfb.cb7c486f93ec7b35
+ 6c21d338838b333a
+
+VPCLMULQDQ_0x00(reg)
+ before
+ fa516d6af337f7c6.12d08700e2b93725.43a6b24195ca0438.b5a14901dd19463d
+ d25712707c7c0385.7c768663521fc7cb.4b9873309eb28488.71b3fb91b88b6a62
+ 5181bfb8bce79225.a41bbd5c02b7fc57.0bc77c695038aa22.bea0e68284681596
+ d11a6fad4f03e14f.678da8d80d8e92f3.df7fcb5a46eab2b2.783288bf5ebe0304
+ 7c365c346298efd8
+ after
+ 0000000000000000.0000000000000000.336a4eda75b3669d.38cea2c0418d206c
+ d25712707c7c0385.7c768663521fc7cb.4b9873309eb28488.71b3fb91b88b6a62
+ 5181bfb8bce79225.a41bbd5c02b7fc57.0bc77c695038aa22.bea0e68284681596
+ d11a6fad4f03e14f.678da8d80d8e92f3.df7fcb5a46eab2b2.783288bf5ebe0304
+ 7c365c346298efd8
+VPCLMULQDQ_0x00(mem)
+ before
+ a478decdab039740.af6d1ebbd05c2cb2.a197c4c190af44cb.230b5b6e1c53d8e3
+ cdc48b775609b465.48c7c84edc7faff8.2e048c05a626cf0c.33b828116fff5762
+ d3e5de1c7eb90576.f6746ad20df7a5ce.eba17c8f6cffefe2.6ad22eafda7b6cda
+ 92a952a93f1c449d.16c0ffb402504bdf.b23a104bfd475f78.26a56ab5fa5252f8
+ c27dd78d6a114768
+ after
+ a478decdab039740.af6d1ebbd05c2cb2.a197c4c190af44cb.230b5b6e1c53d8e3
+ cdc48b775609b465.48c7c84edc7faff8.2e048c05a626cf0c.33b828116fff5762
+ 0000000000000000.0000000000000000.06220a640873521d.09c32f5fd137cc66
+ 92a952a93f1c449d.16c0ffb402504bdf.b23a104bfd475f78.26a56ab5fa5252f8
+ c27dd78d6a114768
+
+VPCLMULQDQ_0x01(reg)
+ before
+ 9aa671a4c74385d5.e6da660bb6402f06.04f7825e5517ddd8.609bc5257609dcfb
+ 096b3467ac7449eb.ab45932cfe307fdf.1d64f23da2d79664.d1901509f2522296
+ 6d1a1d40b531ce58.bdb657fa34f9f351.bb5548be861cb430.e1e47ee38e2ded76
+ 20fd269d7f0552c6.f8f92c6073a6458b.3b14824c9c7371e8.6c657b9f65a6f8c7
+ 4edd892a93ca00b4
+ after
+ 0000000000000000.0000000000000000.0a5088e1d0e8830e.a0aa6a2f2dd01298
+ 096b3467ac7449eb.ab45932cfe307fdf.1d64f23da2d79664.d1901509f2522296
+ 6d1a1d40b531ce58.bdb657fa34f9f351.bb5548be861cb430.e1e47ee38e2ded76
+ 20fd269d7f0552c6.f8f92c6073a6458b.3b14824c9c7371e8.6c657b9f65a6f8c7
+ 4edd892a93ca00b4
+VPCLMULQDQ_0x01(mem)
+ before
+ 6319226e35a4c16a.80614de9a67c0fe1.38da904ad84332b7.f9ee9a5281670937
+ 87e5c4596740f714.e7928d90c5224156.5924fea47edd7601.512f8e3ed084baca
+ 960dead544ab5ddf.b3dbe3fe788426d1.37a5f35a827fcc97.9f235a7b2657be4c
+ 6b5c10d0e8f0b0f6.3e8a499f5c2ef8fd.ae27ea58ff35f1a2.3f15f8751e6b516a
+ 8d536698554db1d0
+ after
+ 6319226e35a4c16a.80614de9a67c0fe1.38da904ad84332b7.f9ee9a5281670937
+ 87e5c4596740f714.e7928d90c5224156.5924fea47edd7601.512f8e3ed084baca
+ 0000000000000000.0000000000000000.36cf5884a96c4d7f.823aa4f8fbcaeb37
+ 6b5c10d0e8f0b0f6.3e8a499f5c2ef8fd.ae27ea58ff35f1a2.3f15f8751e6b516a
+ 8d536698554db1d0
+
+VPCLMULQDQ_0x01(reg)
+ before
+ e5279f5066881829.e4a0b335701bac87.e6e9bddf0daaf487.9a775e8a120ca151
+ a3de9f0aeea8c322.dca34ef0f8390cbb.05453a2a2586551b.d661ceddd60f97ce
+ 23c462308839ee66.2f325ded9a558dc1.f9ebbced434d5964.40b1b33b684a9145
+ c025e530d0c8d4a2.b8195c18757bebc3.1c244092018c3a0e.b3328a92e3ca49e3
+ 0bb2d0cc639a7bd4
+ after
+ 0000000000000000.0000000000000000.015317f73fc3dac8.363f717627ad6cb7
+ a3de9f0aeea8c322.dca34ef0f8390cbb.05453a2a2586551b.d661ceddd60f97ce
+ 23c462308839ee66.2f325ded9a558dc1.f9ebbced434d5964.40b1b33b684a9145
+ c025e530d0c8d4a2.b8195c18757bebc3.1c244092018c3a0e.b3328a92e3ca49e3
+ 0bb2d0cc639a7bd4
+VPCLMULQDQ_0x01(mem)
+ before
+ 23fb00d705c6e543.d84d237463e0b281.5524c75da2b8e1ed.cb3fc187fbce34c6
+ d9da969ee55b415d.c687186add0ec4b1.e11f1ba840172d6c.63873a36ce9f8538
+ 071b0f0d1e644c4e.e621c07dd9dd46db.37d5d2e668a4896c.3e47aa0d158c6710
+ 8b8ae510cceec141.93651719f3d973ae.35146a01396cb118.b9cd0a776d2017f9
+ 306357e071e8d19f
+ after
+ 23fb00d705c6e543.d84d237463e0b281.5524c75da2b8e1ed.cb3fc187fbce34c6
+ d9da969ee55b415d.c687186add0ec4b1.e11f1ba840172d6c.63873a36ce9f8538
+ 0000000000000000.0000000000000000.4ef44723fa300780.dbf196dab8e9f268
+ 8b8ae510cceec141.93651719f3d973ae.35146a01396cb118.b9cd0a776d2017f9
+ 306357e071e8d19f
+
+VPCLMULQDQ_0x01(reg)
+ before
+ ff568eb4bd6ed0b0.40f296930c035e63.2ba01aaac88e88d4.b5a65fe7cc7a639d
+ 82f2aa5fee4051d5.01219d82f9b1dddf.091ec49cf489c1f9.95582b823fdb5927
+ 1682a74da0ea90bd.ace176c9b004fae2.882a115b115559ca.aff64cc0ae9950e1
+ 155482ea6ef6c812.1bff9e554d077397.0612fd53be7f8df3.e14c3d8c34c203f7
+ 05257ad2ee623097
+ after
+ 0000000000000000.0000000000000000.05dc5a2a0cf6384f.cf7fdc1cbc61ac19
+ 82f2aa5fee4051d5.01219d82f9b1dddf.091ec49cf489c1f9.95582b823fdb5927
+ 1682a74da0ea90bd.ace176c9b004fae2.882a115b115559ca.aff64cc0ae9950e1
+ 155482ea6ef6c812.1bff9e554d077397.0612fd53be7f8df3.e14c3d8c34c203f7
+ 05257ad2ee623097
+VPCLMULQDQ_0x01(mem)
+ before
+ f94f7f7ef68491ea.dcb235a3f5f33680.2b479010eac6022b.dd2185f09492991f
+ 9794c97c6b34e21f.c7e9bee2cf6a16b5.b985c8e8a64d64ca.6ba2a49f321ab8fb
+ bcc1d2b8677ee160.324518159be9a45a.9f85c2c89aa9549f.0ae255ca31a42833
+ 45a2181f066f48da.791240a6f3fb1b1e.ba12fa9be4e590d7.182d97df30bb2372
+ efcf6349c8ebe664
+ after
+ f94f7f7ef68491ea.dcb235a3f5f33680.2b479010eac6022b.dd2185f09492991f
+ 9794c97c6b34e21f.c7e9bee2cf6a16b5.b985c8e8a64d64ca.6ba2a49f321ab8fb
+ 0000000000000000.0000000000000000.7ebfa1a30226519e.c6c4f8a60f006e86
+ 45a2181f066f48da.791240a6f3fb1b1e.ba12fa9be4e590d7.182d97df30bb2372
+ efcf6349c8ebe664
+
+VPCLMULQDQ_0x10(reg)
+ before
+ ed13b77397c1acb7.0c03179b6512d4b8.f79c3003732cb9ab.e7faed4fa00ed29d
+ 6c478ecb39c8b214.eeb049199f744127.0a2ee697b809b7ad.000716cfe92fd61e
+ c9b5e4bc498c342a.c7742c86d1a04a52.0d165dce5d1d54d1.e206f107dc545a86
+ 61aab5b2639a6ea3.741c3bcd17a2ac66.5c9e9114fff5cac3.69c3fae394891800
+ 720aad502ddbcdb9
+ after
+ 0000000000000000.0000000000000000.00002399001b0258.b0ecdfbdb904277e
+ 6c478ecb39c8b214.eeb049199f744127.0a2ee697b809b7ad.000716cfe92fd61e
+ c9b5e4bc498c342a.c7742c86d1a04a52.0d165dce5d1d54d1.e206f107dc545a86
+ 61aab5b2639a6ea3.741c3bcd17a2ac66.5c9e9114fff5cac3.69c3fae394891800
+ 720aad502ddbcdb9
+VPCLMULQDQ_0x10(mem)
+ before
+ d7a68738c45535dd.8e72fd1a247d9b2c.cf75f2da8b86238f.53137fd5391c562f
+ 7565038875040b97.ad59b95e28c1f870.b549cd984c596af8.4dc1217da81e34bf
+ 28119d2d5bf30c13.1aabe4eb0af3c11c.026548f573273ece.a8f47579e7879f22
+ cc77d112922ef47e.31b37a2e669e31db.9294e0dc1efa5b3c.bff8763393e4d402
+ ee18201947c00f0c
+ after
+ d7a68738c45535dd.8e72fd1a247d9b2c.cf75f2da8b86238f.53137fd5391c562f
+ 7565038875040b97.ad59b95e28c1f870.b549cd984c596af8.4dc1217da81e34bf
+ 0000000000000000.0000000000000000.3600c0eb113bbbb7.49138f7dae795445
+ cc77d112922ef47e.31b37a2e669e31db.9294e0dc1efa5b3c.bff8763393e4d402
+ ee18201947c00f0c
+
+VPCLMULQDQ_0x10(reg)
+ before
+ 90a17095a0a88ceb.3d631c2237c27e04.4fbf7891d94e855a.41a4103a69e07d6f
+ 03e060153927864c.57a1f94b65ba68d1.ce19d882fe90f945.eb5f54f96fe45f93
+ a11fee04aec93adb.f6fde47839226b10.0b0e986c72efc947.6c9329064d13bed3
+ c8aa16ce9c1be443.f6425995ce0746ed.62eab3bad0f7300d.a00a094e1e78565c
+ 639172bbfe1fe359
+ after
+ 0000000000000000.0000000000000000.066246005bb74b09.c62964a603653139
+ 03e060153927864c.57a1f94b65ba68d1.ce19d882fe90f945.eb5f54f96fe45f93
+ a11fee04aec93adb.f6fde47839226b10.0b0e986c72efc947.6c9329064d13bed3
+ c8aa16ce9c1be443.f6425995ce0746ed.62eab3bad0f7300d.a00a094e1e78565c
+ 639172bbfe1fe359
+VPCLMULQDQ_0x10(mem)
+ before
+ 91f3df3b0a1520f7.d2cfd2df9fa8bf30.333ed48e4174b395.2ff925dab5356b42
+ 05feccb95d65ca62.1dd91fa352fc0850.88bbd24fad757034.ce87eb37bc34b693
+ 9d7cb620141b9dc5.0313fa8651a4fb4d.d386cec42f1636f5.9bdfff3e82814dac
+ 343b185e4b44544d.e2ca5ef4392bd4d3.ef6b44dae264c405.f24e5f59a2a66b38
+ 2f2007f5b9324de4
+ after
+ 91f3df3b0a1520f7.d2cfd2df9fa8bf30.333ed48e4174b395.2ff925dab5356b42
+ 05feccb95d65ca62.1dd91fa352fc0850.88bbd24fad757034.ce87eb37bc34b693
+ 0000000000000000.0000000000000000.147abb17efd82d55.0cd5b295d803296f
+ 343b185e4b44544d.e2ca5ef4392bd4d3.ef6b44dae264c405.f24e5f59a2a66b38
+ 2f2007f5b9324de4
+
+VPCLMULQDQ_0x10(reg)
+ before
+ ada1f17e62ae2e5b.a6056d5e1debac25.144a4859a51dce8f.b836b07be26bd490
+ ca1d1a6139a84c4a.cea7340ca61c617a.f6dfb2223207262d.09b28f954d3623c1
+ e1e07f09dbabe15c.8aede65503e42e77.e5d59ab97b741858.c0ad5b123cd16dc5
+ 4e351be1e4442a3f.b5a201234f4ed149.3b78fb8c1df0dfbd.b8f192e0cd486dc7
+ cc4bb0ea1ca8e0f4
+ after
+ 0000000000000000.0000000000000000.07aac8c156b5f1c8.ac47d456240dca58
+ ca1d1a6139a84c4a.cea7340ca61c617a.f6dfb2223207262d.09b28f954d3623c1
+ e1e07f09dbabe15c.8aede65503e42e77.e5d59ab97b741858.c0ad5b123cd16dc5
+ 4e351be1e4442a3f.b5a201234f4ed149.3b78fb8c1df0dfbd.b8f192e0cd486dc7
+ cc4bb0ea1ca8e0f4
+VPCLMULQDQ_0x10(mem)
+ before
+ da872f1c43fc8277.6c6aea57effd629c.2a94ff63a766041c.5513d106b308b807
+ bd718d6261500f7e.99c9e9d69865c722.c78d5e022639831b.8ff31893da47dfe3
+ 50d444a890b14232.309f13ca7c05937b.665b9aeae8d20c73.4664cd9e2d3990fd
+ 717ed3daec2ad8c2.8c38639f376b0253.e5c82d090b3e5950.d4b2ea96496b0600
+ 96296de4c9687e99
+ after
+ da872f1c43fc8277.6c6aea57effd629c.2a94ff63a766041c.5513d106b308b807
+ bd718d6261500f7e.99c9e9d69865c722.c78d5e022639831b.8ff31893da47dfe3
+ 0000000000000000.0000000000000000.14d35e71fee1952d.759d628e8dc9f2a4
+ 717ed3daec2ad8c2.8c38639f376b0253.e5c82d090b3e5950.d4b2ea96496b0600
+ 96296de4c9687e99
+
+VPCLMULQDQ_0x11(reg)
+ before
+ e81552f549bc3473.fa39b3e592c78d57.0be0d8c163225257.1ea1954aa88727dd
+ 26c1933566f4643b.c9d261b39d951c20.08e26b9c9fb7bd33.efb14d98ddbc3147
+ ac7b2e10bc9b499d.b8155a312a9f4247.de8c199d84b58092.32c6d1e1c6e635b9
+ d68d1df3e63d2044.a4ce194c54f2bbf9.eb28df2eb1a8d621.c5aa9d107e13ed60
+ 822b2e12214e1567
+ after
+ 0000000000000000.0000000000000000.06b6c2df721a31e9.ac65a9e5287cb0d6
+ 26c1933566f4643b.c9d261b39d951c20.08e26b9c9fb7bd33.efb14d98ddbc3147
+ ac7b2e10bc9b499d.b8155a312a9f4247.de8c199d84b58092.32c6d1e1c6e635b9
+ d68d1df3e63d2044.a4ce194c54f2bbf9.eb28df2eb1a8d621.c5aa9d107e13ed60
+ 822b2e12214e1567
+VPCLMULQDQ_0x11(mem)
+ before
+ 4613fed1cca36bfb.00445f49806724dd.6ac91aef38994361.8903b8bdbf1dfd8c
+ ee2f8b3a9a1fa948.86eced7d27a49313.e4d1da05f1a095ac.1669a0b44c9f2f7e
+ 544a503aa8cd8c79.c4d1c4fd7781a793.efb4d37c9c136e05.eca69481f4baa8a3
+ 5532cabb12bad0bb.163ee1340a899d09.673c833f54ff8a99.68068e8f52fba6a9
+ e7d48c4a03ec6339
+ after
+ 4613fed1cca36bfb.00445f49806724dd.6ac91aef38994361.8903b8bdbf1dfd8c
+ ee2f8b3a9a1fa948.86eced7d27a49313.e4d1da05f1a095ac.1669a0b44c9f2f7e
+ 0000000000000000.0000000000000000.230df69114c9af48.8c5775bcfd4ebf2c
+ 5532cabb12bad0bb.163ee1340a899d09.673c833f54ff8a99.68068e8f52fba6a9
+ e7d48c4a03ec6339
+
+VPCLMULQDQ_0x11(reg)
+ before
+ c35d891ea21c1c02.cdb274abf2f13039.d7813f8e7f48b020.2936653a356fa494
+ 59ee8277cb140cae.9995c9f4677e6920.65e4da77704a1d85.0f6ef5595c707a21
+ 06d171c11b6371ea.93a847848a6e379c.1bb4af5b791c20e3.f6b0b089e50dc56d
+ 245254682e928561.98b76a467acb55d8.553db8a63749f5e7.bac710b4eb5244a3
+ 378193c78a4cb1f0
+ after
+ 0000000000000000.0000000000000000.05e6fd7636ee20be.525db08cb2c895ef
+ 59ee8277cb140cae.9995c9f4677e6920.65e4da77704a1d85.0f6ef5595c707a21
+ 06d171c11b6371ea.93a847848a6e379c.1bb4af5b791c20e3.f6b0b089e50dc56d
+ 245254682e928561.98b76a467acb55d8.553db8a63749f5e7.bac710b4eb5244a3
+ 378193c78a4cb1f0
+VPCLMULQDQ_0x11(mem)
+ before
+ 49a8b4afdf05ca80.10bf26d99f2f84c0.848eac2650a48001.6ecbf3c4455ed73c
+ cc09f057068c487e.2663e37e0ac5acb2.33f98b102b027442.c4a95b223fe60390
+ 9c70c1aa19eaea17.c28987c50ce037e4.81c382f024f3edc8.b225ec2ac26db58c
+ 95a9a596372d6a76.407e0f18400d6202.4aba0db25983a6bf.9389a34a6a7f29df
+ c5227bedd2a99a33
+ after
+ 49a8b4afdf05ca80.10bf26d99f2f84c0.848eac2650a48001.6ecbf3c4455ed73c
+ cc09f057068c487e.2663e37e0ac5acb2.33f98b102b027442.c4a95b223fe60390
+ 0000000000000000.0000000000000000.192bf66db9bd363f.7e548074c96b7442
+ 95a9a596372d6a76.407e0f18400d6202.4aba0db25983a6bf.9389a34a6a7f29df
+ c5227bedd2a99a33
+
+VPCLMULQDQ_0x11(reg)
+ before
+ a33c707f97774534.938017067a6185c8.fd8e76e543d769b7.6aa8a843e6bc5c52
+ 88237e6b5473668f.72c093e6fe90f739.5305b897b0ca87b0.bd5ad08de6accbae
+ d223a11fa52b38f0.0e379622e0c87bf4.9f2fd19a2473f998.1f9c007e755eaffe
+ db87d606272af802.43af9aa63b14ce26.3d58bd5a3a5dfb1c.6c3ab400b0dfc36f
+ 7fff6801b33ac42d
+ after
+ 0000000000000000.0000000000000000.2f9acba16e991d29.40523864426cae80
+ 88237e6b5473668f.72c093e6fe90f739.5305b897b0ca87b0.bd5ad08de6accbae
+ d223a11fa52b38f0.0e379622e0c87bf4.9f2fd19a2473f998.1f9c007e755eaffe
+ db87d606272af802.43af9aa63b14ce26.3d58bd5a3a5dfb1c.6c3ab400b0dfc36f
+ 7fff6801b33ac42d
+VPCLMULQDQ_0x11(mem)
+ before
+ 36b9996c997b6e63.009d178d75fde272.edf51d5f2b81acfa.89cb79438f15c8e8
+ 6c32c12d7eaf7c3e.9eaf621e2c2f32eb.e8d59a37ce1ad09d.ded600c1be259ea7
+ fd375e307fe1abe9.0f0ab326e84c231b.0f1b8e1b3debf83b.9ac34e40641bb706
+ c494eb61b71db791.b1fa041243e1f2ab.409273f89601deff.18df5f2d1c834fb0
+ b47630f282e8a452
+ after
+ 36b9996c997b6e63.009d178d75fde272.edf51d5f2b81acfa.89cb79438f15c8e8
+ 6c32c12d7eaf7c3e.9eaf621e2c2f32eb.e8d59a37ce1ad09d.ded600c1be259ea7
+ 0000000000000000.0000000000000000.5716be80339de308.b25ec1f9bb4eea62
+ c494eb61b71db791.b1fa041243e1f2ab.409273f89601deff.18df5f2d1c834fb0
+ b47630f282e8a452
+
+VPCLMULQDQ_0xFF(reg)
+ before
+ cad3bcfd33d6f097.9f15e5ac43705b62.decb534cdc79db49.5608c7b9f5673e15
+ b644ffb9cbd9702d.6986c6fd3ee55587.f3c89b424da019a1.2c470549752ad6ab
+ d313f591e57e5fbd.fdb20c41c5895f2c.4c3fd85f32e3ea5f.a01ca996325460eb
+ 7f8d9bf31d51faf6.39673262f366357f.467a060e27cd872e.8d532f8b49f39901
+ ceb81414d6133c1a
+ after
+ 0000000000000000.0000000000000000.38b70d4073f4b52f.ac7d27dba216d93f
+ b644ffb9cbd9702d.6986c6fd3ee55587.f3c89b424da019a1.2c470549752ad6ab
+ d313f591e57e5fbd.fdb20c41c5895f2c.4c3fd85f32e3ea5f.a01ca996325460eb
+ 7f8d9bf31d51faf6.39673262f366357f.467a060e27cd872e.8d532f8b49f39901
+ ceb81414d6133c1a
+VPCLMULQDQ_0xFF(mem)
+ before
+ 4116d31df3bf0762.15feeb4a10dc7d82.f86fb44ee58a95aa.3bc622bdcaea2fba
+ c03be892bf03b404.f0b2e30259ad240d.15970fefb60139d9.886f26d7b4c71cb1
+ 29f1cf6054ebff2d.6ef57e87954f2a44.6eabbe3382d6de39.89c110c883ef8bbc
+ 56050571ce84a609.e913b846604fcdd3.dd773c0566153ff6.9a08dcfdd3efb88a
+ 178f84e03f51dfc5
+ after
+ 4116d31df3bf0762.15feeb4a10dc7d82.f86fb44ee58a95aa.3bc622bdcaea2fba
+ c03be892bf03b404.f0b2e30259ad240d.15970fefb60139d9.886f26d7b4c71cb1
+ 0000000000000000.0000000000000000.0cee777ce3eff815.7ad54f379ae5c7da
+ 56050571ce84a609.e913b846604fcdd3.dd773c0566153ff6.9a08dcfdd3efb88a
+ 178f84e03f51dfc5
+
+VPCLMULQDQ_0xFF(reg)
+ before
+ 5ca406de63a33b19.244304b34ad963c3.bf578ea954384665.3fc608517eca1a3b
+ c5915d64dc710934.70774a10e3f6f387.4b0efb1d1096d4a7.71669b03e5022935
+ aea385dc464685bf.146d5276b6e81183.e884fb0f2df6b144.4d217207b7c8280f
+ 73267ab43caeea69.eef099d0deba7be0.f3058aea49e21aea.b0c40a491129d5f6
+ 771bdeb60f2fea16
+ after
+ 0000000000000000.0000000000000000.3c59f8a7d0706976.0521f19490b5cc5c
+ c5915d64dc710934.70774a10e3f6f387.4b0efb1d1096d4a7.71669b03e5022935
+ aea385dc464685bf.146d5276b6e81183.e884fb0f2df6b144.4d217207b7c8280f
+ 73267ab43caeea69.eef099d0deba7be0.f3058aea49e21aea.b0c40a491129d5f6
+ 771bdeb60f2fea16
+VPCLMULQDQ_0xFF(mem)
+ before
+ 7cf26a38cce9249a.706538575a3575dc.d8ce99097779ebcd.c9dda41900e94b42
+ 9c152bbd64603faf.01aebc313d6862c4.afd1d00f9e301d74.c458460aed947ffb
+ b34f9b2ff4a2f681.824b01ae80d2ecce.4fc6b9cd6febcf02.42c16b28ad71f4be
+ 9e6e387c97ba063b.4f8a033ac00051a6.9479d13005b7bba2.9d660fdfdb0ce33a
+ 32912e9b13ef8b19
+ after
+ 7cf26a38cce9249a.706538575a3575dc.d8ce99097779ebcd.c9dda41900e94b42
+ 9c152bbd64603faf.01aebc313d6862c4.afd1d00f9e301d74.c458460aed947ffb
+ 0000000000000000.0000000000000000.73e5d5b385769538.ca2f927307e8d804
+ 9e6e387c97ba063b.4f8a033ac00051a6.9479d13005b7bba2.9d660fdfdb0ce33a
+ 32912e9b13ef8b19
+
+VPCLMULQDQ_0xFF(reg)
+ before
+ 5d8fc5c8f2a82608.373c7d8f6ab52b09.c3b5bf41987ccbf7.5bb692227d9e9e81
+ 7bacced314c3f1b2.5b86e754889e2018.3c192f2fa5d5966e.7e487a90f2af34ca
+ e633472614ca28c4.e618f0b70e81a294.150251708294f0b7.dafd046780f338aa
+ fb722b2e8e4c07e9.b4bd16a4176a6da9.a9bb2071cc47137d.4b9fac914478674d
+ adfbeefc59497dde
+ after
+ 0000000000000000.0000000000000000.030d9ba3afb3fc92.a42a0615e557df2a
+ 7bacced314c3f1b2.5b86e754889e2018.3c192f2fa5d5966e.7e487a90f2af34ca
+ e633472614ca28c4.e618f0b70e81a294.150251708294f0b7.dafd046780f338aa
+ fb722b2e8e4c07e9.b4bd16a4176a6da9.a9bb2071cc47137d.4b9fac914478674d
+ adfbeefc59497dde
+VPCLMULQDQ_0xFF(mem)
+ before
+ dcdd4792dc73358a.16b377581fd2c9ce.a143d407bf663d82.5692999c1e793c6d
+ b4113141e8014d7c.9344250f62eaab1f.8974a6cc2381cd4b.77d1b65f15b7a632
+ 11632af49aff7ee1.ce6f33bef41fe887.481e08df5fc5da31.67c575254c8c8e79
+ cf9eae970e7a87e5.23819cd370fdbeb3.ba0b772d8e402060.84bad1595f8430ee
+ 28fcc669eb2cc83c
+ after
+ dcdd4792dc73358a.16b377581fd2c9ce.a143d407bf663d82.5692999c1e793c6d
+ b4113141e8014d7c.9344250f62eaab1f.8974a6cc2381cd4b.77d1b65f15b7a632
+ 0000000000000000.0000000000000000.553e19fb07647dca.51d05f1f8710d016
+ cf9eae970e7a87e5.23819cd370fdbeb3.ba0b772d8e402060.84bad1595f8430ee
+ 28fcc669eb2cc83c
+
+VCMPSS_128_0x9(reg)
+ before
+ b1d750c08c0f920f.ca9037165e7d22b3.eec55db97311674e.bb086ea0ccfe5b04
+ 79966ccadcb9c915.dd03435da8140d77.8b8970dc98e62005.27e0692636094647
+ de8715f37ab6aaf7.e6c44d59084c015f.5618d3a87c082484.da61e4aae86f9e58
+ 3af447a800937064.c09fd1f49930bd95.abbd8189ba04b076.af555c18fd3b1f61
+ 848a4b5b917a848f
+ after
+ 0000000000000000.0000000000000000.8b8970dc98e62005.27e0692600000000
+ 79966ccadcb9c915.dd03435da8140d77.8b8970dc98e62005.27e0692636094647
+ de8715f37ab6aaf7.e6c44d59084c015f.5618d3a87c082484.da61e4aae86f9e58
+ 3af447a800937064.c09fd1f49930bd95.abbd8189ba04b076.af555c18fd3b1f61
+ 848a4b5b917a848f
+VCMPSS_128_0x9(mem)
+ before
+ 34ca2f61c1378a0d.eb2afe530adc5806.47604b1b78ccfb45.e6c576ecef650087
+ 9be28316a87fed08.4b753662351b9e8a.57d237bbc02d789c.637cae3bb6b85065
+ 949ec464635c68ac.b721ec3f1cde7e9b.cbc312bf8d5ef0c6.7e2e26e4ab88dbba
+ fdc96c380ddcb924.8b791b585cb134e6.81fd5712fc6b1eee.9327d8516b61de32
+ fdb2c2f092cf957a
+ after
+ 34ca2f61c1378a0d.eb2afe530adc5806.47604b1b78ccfb45.e6c576ecef650087
+ 9be28316a87fed08.4b753662351b9e8a.57d237bbc02d789c.637cae3bb6b85065
+ 0000000000000000.0000000000000000.57d237bbc02d789c.637cae3b00000000
+ fdc96c380ddcb924.8b791b585cb134e6.81fd5712fc6b1eee.9327d8516b61de32
+ fdb2c2f092cf957a
+
+VCMPSS_128_0x9(reg)
+ before
+ 1a1ce02cbb5f3c3e.b031f97ec30b9a9d.24cbbf17901efb16.544d82a22961bf41
+ 45b22c71829c0e2a.8ba0e623a0f3c742.dc61d4ea55b310d8.1f7f105a2f4b8feb
+ d9bea42b841348e8.69e4af11c1a3fe40.1088573c46fcaed8.c05f7b262a354a17
+ 348d43c65c4f2627.25c7d1364124f9c2.1c8c4379008313c1.11b841f2372cabf2
+ f058ddaa713b6fa7
+ after
+ 0000000000000000.0000000000000000.dc61d4ea55b310d8.1f7f105a00000000
+ 45b22c71829c0e2a.8ba0e623a0f3c742.dc61d4ea55b310d8.1f7f105a2f4b8feb
+ d9bea42b841348e8.69e4af11c1a3fe40.1088573c46fcaed8.c05f7b262a354a17
+ 348d43c65c4f2627.25c7d1364124f9c2.1c8c4379008313c1.11b841f2372cabf2
+ f058ddaa713b6fa7
+VCMPSS_128_0x9(mem)
+ before
+ 3709cc3bf56f5263.b16a05aea7dce391.9d16c67d3c8475f5.5cb9940d1ed77940
+ c498888fdfd30f51.aba3e64f0047bcd3.ab9c0cd2d0ce2d05.2c5a46643c811d00
+ 71d18f944973639e.8082e315041bed98.2c271e21160edf1d.e9bd55ebf70f3aae
+ 1b805c34525b0a76.8a55f66d4ee4b28d.fd8179562c51456a.ed2cbe0ceb0c0df6
+ 95f57c35b304d283
+ after
+ 3709cc3bf56f5263.b16a05aea7dce391.9d16c67d3c8475f5.5cb9940d1ed77940
+ c498888fdfd30f51.aba3e64f0047bcd3.ab9c0cd2d0ce2d05.2c5a46643c811d00
+ 0000000000000000.0000000000000000.ab9c0cd2d0ce2d05.2c5a466400000000
+ 1b805c34525b0a76.8a55f66d4ee4b28d.fd8179562c51456a.ed2cbe0ceb0c0df6
+ 95f57c35b304d283
+
+VCMPSS_128_0x9(reg)
+ before
+ 3d628bd0eb84c502.9f716b5d1398c004.27661dc17b2e465d.f878975d2da21b18
+ 40bfe74b3017211e.d77038faaa354075.b102547f2686e6b6.fbd6f622360e1f52
+ fc5a8d111d4a2384.a04840f7333f47f5.86749512ec78ce41.e068119163a00b44
+ cc7e778d4fa707e0.d7c6fe3fc9c091af.000adee5688e39ac.84fa6497cf649c1c
+ c3576c1e96668e03
+ after
+ 0000000000000000.0000000000000000.b102547f2686e6b6.fbd6f622ffffffff
+ 40bfe74b3017211e.d77038faaa354075.b102547f2686e6b6.fbd6f622360e1f52
+ fc5a8d111d4a2384.a04840f7333f47f5.86749512ec78ce41.e068119163a00b44
+ cc7e778d4fa707e0.d7c6fe3fc9c091af.000adee5688e39ac.84fa6497cf649c1c
+ c3576c1e96668e03
+VCMPSS_128_0x9(mem)
+ before
+ 7a4da314d5b39c28.0c76a32d62bd09dd.56b6eec189c7d9cf.7c0f2966375664a3
+ 83a68764a75683b5.188f0c5cf0156428.fae48c668e5ddd82.57ce7400f45c8bd2
+ bb2f93f9295cffd6.4c16af87983d556c.9f1c541bf49056f4.eb94bb1f3b2aeae4
+ feb443c176d0cbb9.03548618f3c01756.212ac3ccd86b0351.95adf830a94ebc85
+ b165299dda543e63
+ after
+ 7a4da314d5b39c28.0c76a32d62bd09dd.56b6eec189c7d9cf.7c0f2966375664a3
+ 83a68764a75683b5.188f0c5cf0156428.fae48c668e5ddd82.57ce7400f45c8bd2
+ 0000000000000000.0000000000000000.fae48c668e5ddd82.57ce7400ffffffff
+ feb443c176d0cbb9.03548618f3c01756.212ac3ccd86b0351.95adf830a94ebc85
+ b165299dda543e63
+
diff --git a/main/none/tests/amd64/avx-1.vgtest b/main/none/tests/amd64/avx-1.vgtest
new file mode 100644
index 0000000..0f650d1
--- /dev/null
+++ b/main/none/tests/amd64/avx-1.vgtest
@@ -0,0 +1,3 @@
+prog: avx-1
+prereq: ../../../tests/x86_amd64_features amd64-avx
+vgopts: -q
diff --git a/main/none/tests/amd64/bug132918.stdout.exp-older-glibc b/main/none/tests/amd64/bug132918.stdout.exp-older-glibc
new file mode 100644
index 0000000..9427c84
--- /dev/null
+++ b/main/none/tests/amd64/bug132918.stdout.exp-older-glibc
@@ -0,0 +1,22 @@
+xx1 -> 0x4200 8.300000
+xx2 -> 0x0000 1.440000
+xx -> 0x0000 nan
+xx -> 0x0000 0.809017
+xx -> 0x0000 0.309018
+xx -> 0x0000 -0.309015
+xx -> 0x0000 -0.809016
+xx -> 0x4100 -0.000002
+xx -> 0x0000 -0.809019
+xx -> 0x0000 -0.309021
+xx -> 0x0000 0.309013
+xx -> 0x0000 0.809014
+xx -> 0x4300 0.000002
+xx -> 0x0000 0.809020
+xx -> 0x0000 0.309023
+xx -> 0x0000 -0.309010
+xx -> 0x0000 -0.809013
+xx -> 0x0100 -0.000067
+xx -> 0x0000 -0.809022
+xx -> 0x0000 -0.309026
+xx -> 0x0000 0.309008
+xx -> 0x0000 0.809011
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/amd64/crc32.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/amd64/crc32.stderr.exp
diff --git a/main/none/tests/amd64/fxtract.stdout.exp-older-glibc b/main/none/tests/amd64/fxtract.stdout.exp-older-glibc
new file mode 100644
index 0000000..4508fd6
--- /dev/null
+++ b/main/none/tests/amd64/fxtract.stdout.exp-older-glibc
@@ -0,0 +1,131 @@
+-2.8104666125e+02 -> -1.0978385205 8.0000000000
+-2.6690452563e+02 -> -1.0425958032 8.0000000000
+-2.5276239000e+02 -> -1.9747061719 7.0000000000
+-2.3862025438e+02 -> -1.8642207373 7.0000000000
+-2.2447811876e+02 -> -1.7537353028 7.0000000000
+-2.1033598313e+02 -> -1.6432498682 7.0000000000
+-1.9619384751e+02 -> -1.5327644337 7.0000000000
+-1.8205171188e+02 -> -1.4222789991 7.0000000000
+-1.6790957626e+02 -> -1.3117935645 7.0000000000
+-1.5376744064e+02 -> -1.2013081300 7.0000000000
+-1.3962530501e+02 -> -1.0908226954 7.0000000000
+-1.2548316939e+02 -> -1.9606745217 6.0000000000
+-1.1134103377e+02 -> -1.7397036526 6.0000000000
+-9.7198898142e+01 -> -1.5187327835 6.0000000000
+-8.3056762518e+01 -> -1.2977619143 6.0000000000
+-6.8914626894e+01 -> -1.0767910452 6.0000000000
+-5.4772491271e+01 -> -1.7116403522 5.0000000000
+-4.0630355647e+01 -> -1.2696986140 5.0000000000
+-2.6488220023e+01 -> -1.6555137515 4.0000000000
+-1.2346084400e+01 -> -1.5432605499 3.0000000000
+ 1.7960512242e+00 -> 1.7960512242 0.0000000000
+ 1.5938186848e+01 -> 1.9922733560 3.0000000000
+ 3.0080322472e+01 -> 1.8800201545 4.0000000000
+ 4.4222458095e+01 -> 1.3819518155 5.0000000000
+ 5.8364593719e+01 -> 1.8238935537 5.0000000000
+ 7.2506729343e+01 -> 1.1329176460 6.0000000000
+ 8.6648864967e+01 -> 1.3538885151 6.0000000000
+ 1.0079100059e+02 -> 1.5748593842 6.0000000000
+ 1.1493313621e+02 -> 1.7958302533 6.0000000000
+ 1.2907527184e+02 -> 1.0084005612 7.0000000000
+ 1.4321740746e+02 -> 1.1188859958 7.0000000000
+ 1.5735954309e+02 -> 1.2293714304 7.0000000000
+ 1.7150167871e+02 -> 1.3398568649 7.0000000000
+ 1.8564381433e+02 -> 1.4503422995 7.0000000000
+ 1.9978594996e+02 -> 1.5608277340 7.0000000000
+ 2.1392808558e+02 -> 1.6713131686 7.0000000000
+ 2.2807022120e+02 -> 1.7817986032 7.0000000000
+ 2.4221235683e+02 -> 1.8922840377 7.0000000000
+ 2.5635449245e+02 -> 1.0013847361 8.0000000000
+ 2.7049662808e+02 -> 1.0566274534 8.0000000000
+ 0.0000000000e+00 -> 0.0000000000 -inf
+ inf -> inf inf
+ nan -> nan nan
+7.2124891681e-308 -> 1.6207302828 -1021.0000000000
+5.7982756057e-308 -> 1.3029400313 -1021.0000000000
+4.3840620434e-308 -> 1.9702995595 -1022.0000000000
+2.9698484810e-308 -> 1.3347190565 -1022.0000000000
+1.5556349186e-308 -> 1.3982771068 -1023.0000000000
+1.2727922061e-308 -> 1.1440449055 -1023.0000000000
+9.8994949366e-309 -> 1.7796254086 -1024.0000000000
+8.4852813742e-309 -> 1.5253932074 -1024.0000000000
+7.0710678119e-309 -> 1.2711610062 -1024.0000000000
+5.6568542495e-309 -> 1.0169288049 -1024.0000000000
+4.2426406871e-309 -> 1.5253932074 -1025.0000000000
+1.4142135624e-309 -> 1.0169288049 -1026.0000000000
+1.8384182682e-320 -> 1.8168945312 -1063.0000000000
+1.8379242025e-321 -> 1.4531250000 -1066.0000000000
+1.8280428896e-322 -> 1.1562500000 -1069.0000000000
+1.9762625834e-323 -> 1.0000000000 -1072.0000000000
+1.4821969375e-323 -> 1.5000000000 -1073.0000000000
+4.9406564584e-324 -> 1.0000000000 -1074.0000000000
+4.9406564584e-324 -> 1.0000000000 -1074.0000000000
+4.9406564584e-324 -> 1.0000000000 -1074.0000000000
+ 0.0000000000e+00 -> 0.0000000000 -inf
+ 0.0000000000e+00 -> 0.0000000000 -inf
+
+ 2.8104666125e+02 -> 1.0978385205 8.0000000000
+ 2.6690452563e+02 -> 1.0425958032 8.0000000000
+ 2.5276239000e+02 -> 1.9747061719 7.0000000000
+ 2.3862025438e+02 -> 1.8642207373 7.0000000000
+ 2.2447811876e+02 -> 1.7537353028 7.0000000000
+ 2.1033598313e+02 -> 1.6432498682 7.0000000000
+ 1.9619384751e+02 -> 1.5327644337 7.0000000000
+ 1.8205171188e+02 -> 1.4222789991 7.0000000000
+ 1.6790957626e+02 -> 1.3117935645 7.0000000000
+ 1.5376744064e+02 -> 1.2013081300 7.0000000000
+ 1.3962530501e+02 -> 1.0908226954 7.0000000000
+ 1.2548316939e+02 -> 1.9606745217 6.0000000000
+ 1.1134103377e+02 -> 1.7397036526 6.0000000000
+ 9.7198898142e+01 -> 1.5187327835 6.0000000000
+ 8.3056762518e+01 -> 1.2977619143 6.0000000000
+ 6.8914626894e+01 -> 1.0767910452 6.0000000000
+ 5.4772491271e+01 -> 1.7116403522 5.0000000000
+ 4.0630355647e+01 -> 1.2696986140 5.0000000000
+ 2.6488220023e+01 -> 1.6555137515 4.0000000000
+ 1.2346084400e+01 -> 1.5432605499 3.0000000000
+-1.7960512242e+00 -> -1.7960512242 0.0000000000
+-1.5938186848e+01 -> -1.9922733560 3.0000000000
+-3.0080322472e+01 -> -1.8800201545 4.0000000000
+-4.4222458095e+01 -> -1.3819518155 5.0000000000
+-5.8364593719e+01 -> -1.8238935537 5.0000000000
+-7.2506729343e+01 -> -1.1329176460 6.0000000000
+-8.6648864967e+01 -> -1.3538885151 6.0000000000
+-1.0079100059e+02 -> -1.5748593842 6.0000000000
+-1.1493313621e+02 -> -1.7958302533 6.0000000000
+-1.2907527184e+02 -> -1.0084005612 7.0000000000
+-1.4321740746e+02 -> -1.1188859958 7.0000000000
+-1.5735954309e+02 -> -1.2293714304 7.0000000000
+-1.7150167871e+02 -> -1.3398568649 7.0000000000
+-1.8564381433e+02 -> -1.4503422995 7.0000000000
+-1.9978594996e+02 -> -1.5608277340 7.0000000000
+-2.1392808558e+02 -> -1.6713131686 7.0000000000
+-2.2807022120e+02 -> -1.7817986032 7.0000000000
+-2.4221235683e+02 -> -1.8922840377 7.0000000000
+-2.5635449245e+02 -> -1.0013847361 8.0000000000
+-2.7049662808e+02 -> -1.0566274534 8.0000000000
+-0.0000000000e+00 -> -0.0000000000 -inf
+ -inf -> -inf inf
+ nan -> nan nan
+-7.2124891681e-308 -> -1.6207302828 -1021.0000000000
+-5.7982756057e-308 -> -1.3029400313 -1021.0000000000
+-4.3840620434e-308 -> -1.9702995595 -1022.0000000000
+-2.9698484810e-308 -> -1.3347190565 -1022.0000000000
+-1.5556349186e-308 -> -1.3982771068 -1023.0000000000
+-1.2727922061e-308 -> -1.1440449055 -1023.0000000000
+-9.8994949366e-309 -> -1.7796254086 -1024.0000000000
+-8.4852813742e-309 -> -1.5253932074 -1024.0000000000
+-7.0710678119e-309 -> -1.2711610062 -1024.0000000000
+-5.6568542495e-309 -> -1.0169288049 -1024.0000000000
+-4.2426406871e-309 -> -1.5253932074 -1025.0000000000
+-1.4142135624e-309 -> -1.0169288049 -1026.0000000000
+-1.8384182682e-320 -> -1.8168945312 -1063.0000000000
+-1.8379242025e-321 -> -1.4531250000 -1066.0000000000
+-1.8280428896e-322 -> -1.1562500000 -1069.0000000000
+-1.9762625834e-323 -> -1.0000000000 -1072.0000000000
+-1.4821969375e-323 -> -1.5000000000 -1073.0000000000
+-4.9406564584e-324 -> -1.0000000000 -1074.0000000000
+-4.9406564584e-324 -> -1.0000000000 -1074.0000000000
+-4.9406564584e-324 -> -1.0000000000 -1074.0000000000
+-0.0000000000e+00 -> -0.0000000000 -inf
+-0.0000000000e+00 -> -0.0000000000 -inf
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/amd64/insn_pclmulqdq.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/amd64/insn_pclmulqdq.stderr.exp
diff --git a/main/none/tests/amd64/lzcnt64.c b/main/none/tests/amd64/lzcnt64.c
new file mode 100644
index 0000000..22fa353
--- /dev/null
+++ b/main/none/tests/amd64/lzcnt64.c
@@ -0,0 +1,93 @@
+
+#include <stdio.h>
+
+typedef unsigned long long int ULong;
+typedef unsigned int UInt;
+
+__attribute__((noinline))
+void do_lzcnt64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+ ULong block[3] = { arg, 0ULL, 0ULL };
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %%r11" "\n\t"
+ "lzcntq 0(%0), %%r11" "\n\t"
+ "movq %%r11, 8(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r11" "\n\t"
+ "movq %%r11, 16(%0)" "\n"
+ : : "r"(&block[0]) : "r11","cc","memory"
+ );
+ *res = block[1];
+ *flags = block[2] & 0x8d5;
+}
+
+__attribute__((noinline))
+void do_lzcnt32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+ ULong block[3] = { arg, 0ULL, 0ULL };
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %%r11" "\n\t"
+ "lzcntl 0(%0), %%r11d" "\n\t"
+ "movq %%r11, 8(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r11" "\n\t"
+ "movq %%r11, 16(%0)" "\n"
+ : : "r"(&block[0]) : "r11","cc","memory"
+ );
+ *res = block[1];
+ *flags = block[2] & 0x8d5;
+}
+
+__attribute__((noinline))
+void do_lzcnt16 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+ ULong block[3] = { arg, 0ULL, 0ULL };
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %%r11" "\n\t"
+ "lzcntw 0(%0), %%r11w" "\n\t"
+ "movq %%r11, 8(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r11" "\n\t"
+ "movq %%r11, 16(%0)" "\n"
+ : : "r"(&block[0]) : "r11","cc","memory"
+ );
+ *res = block[1];
+ *flags = block[2] & 0x8d5;
+}
+
+int main ( void )
+{
+ ULong w;
+
+ w = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_lzcnt64(&flags, &res, w);
+ printf("lzcntq %016llx -> %016llx %04x\n", w, res, flags);
+ if (w == 0) break;
+ w = ((w >> 2) | (w >> 1)) + (w / 17ULL);
+ }
+
+ w = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_lzcnt32(&flags, &res, w);
+ printf("lzcntl %016llx -> %016llx %04x\n", w, res, flags);
+ if (w == 0) break;
+ w = ((w >> 2) | (w >> 1)) + (w / 17ULL);
+ }
+
+ w = 0xFEDC192837475675ULL;
+ while (1) {
+ ULong res;
+ UInt flags;
+ do_lzcnt16(&flags, &res, w);
+ printf("lzcntw %016llx -> %016llx %04x\n", w, res, flags);
+ if (w == 0) break;
+ w = ((w >> 2) | (w >> 1)) + (w / 17ULL);
+ }
+
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/amd64/lzcnt64.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/amd64/lzcnt64.stderr.exp
diff --git a/main/none/tests/amd64/lzcnt64.stdout.exp b/main/none/tests/amd64/lzcnt64.stdout.exp
new file mode 100644
index 0000000..fd73687
--- /dev/null
+++ b/main/none/tests/amd64/lzcnt64.stdout.exp
@@ -0,0 +1,375 @@
+lzcntq fedc192837475675 -> 0000000000000000 0040
+lzcntq 8efcf23ad7e922f3 -> 0000000000000000 0040
+lzcntq 7068b90cdf850938 -> 0000000000000001 0000
+lzcntq 42db3e5ed85503a5 -> 0000000000000001 0000
+lzcntq 35eea72efbea67d7 -> 0000000000000002 0000
+lzcntq 232c23d3b476ef47 -> 0000000000000002 0000
+lzcntq 1bf0c1bf27fbb3ab -> 0000000000000003 0000
+lzcntq 11a1311a29a562ea -> 0000000000000003 0000
+lzcntq 0e02582b8350ffd0 -> 0000000000000004 0000
+lzcntq 0854b4408f5b9e17 -> 0000000000000004 0000
+lzcntq 06bcf33434328063 -> 0000000000000005 0000
+lzcntq 0464f596e5f3ab8a -> 0000000000000005 0000
+lzcntq 037dac8063df281c -> 0000000000000006 0000
+lzcntq 0234910d6d0cfe89 -> 0000000000000006 0000
+lzcntq 01c0a27d7eaa2575 -> 0000000000000007 0000
+lzcntq 010adda943af43d8 -> 0000000000000007 0000
+lzcntq 00d7b2ae8c91c8ce -> 0000000000000008 0000
+lzcntq 008cae284a0c2065 -> 0000000000000008 0000
+lzcntq 006fc6190eb4fc04 -> 0000000000000009 0000
+lzcntq 004686bd6e829ce5 -> 0000000000000009 0000
+lzcntq 00380a0b248034f1 -> 000000000000000a 0000
+lzcntq 0021536a650d4fc6 -> 000000000000000a 0000
+lzcntq 001af3d8d0c8c068 -> 000000000000000b 0000
+lzcntq 001193de10460316 -> 000000000000000b 0000
+lzcntq 000df6b241dd45c1 -> 000000000000000c 0000
+lzcntq 0008d24469947f91 -> 000000000000000c 0000
+lzcntq 0007028a17f7fc21 -> 000000000000000d 0000
+lzcntq 00042b77370e9574 -> 000000000000000d 0000
+lzcntq 00035ecaa6c8cb9c -> 000000000000000e 0000
+lzcntq 000232b89c5ca207 -> 000000000000000e 0000
+lzcntq 0001bf185a53fb83 -> 000000000000000f 0000
+lzcntq 00011a1af9c2f08e -> 000000000000000f 0000
+lzcntq 0000e0282bc137ba -> 0000000000000010 0000
+lzcntq 0000854daa0b4caf -> 0000000000000010 0000
+lzcntq 00006bcf63e2fc01 -> 0000000000000011 0000
+lzcntq 0000464f7852a469 -> 0000000000000011 0000
+lzcntq 000037dac915aa8f -> 0000000000000012 0000
+lzcntq 0000234911b3280d -> 0000000000000012 0000
+lzcntq 00001c0a2862c244 -> 0000000000000013 0000
+lzcntq 000010addcd6577a -> 0000000000000013 0000
+lzcntq 00000d7b2a9b6ac9 -> 0000000000000014 0000
+lzcntq 000008cae2719cd4 -> 0000000000000014 0000
+lzcntq 000006fc61694403 -> 0000000000000015 0000
+lzcntq 000004686be70610 -> 0000000000000015 0000
+lzcntq 00000380a0af0023 -> 0000000000000016 0000
+lzcntq 0000021536a82984 -> 0000000000000016 0000
+lzcntq 000001af3d8f8abd -> 0000000000000017 0000
+lzcntq 000001193de14a82 -> 0000000000000017 0000
+lzcntq 000000df6b24569d -> 0000000000000018 0000
+lzcntq 0000008d2446cc8e -> 0000000000000018 0000
+lzcntq 0000007028a18af6 -> 0000000000000019 0000
+lzcntq 00000042b7735995 -> 0000000000000019 0000
+lzcntq 00000035ecaa6d9d -> 000000000000001a 0000
+lzcntq 000000232b89c661 -> 000000000000001a 0000
+lzcntq 0000001bf185a509 -> 000000000000001b 0000
+lzcntq 00000011a1af9c11 -> 000000000000001b 0000
+lzcntq 0000000e0282bbfd -> 000000000000001c 0000
+lzcntq 0000000854daa1a4 -> 000000000000001c 0000
+lzcntq 00000006bcf63eb9 -> 000000000000001d 0000
+lzcntq 0000000464f78590 -> 000000000000001d 0000
+lzcntq 000000037dac916c -> 000000000000001e 0000
+lzcntq 0000000234911b32 -> 000000000000001e 0000
+lzcntq 00000001c0a2862b -> 000000000000001f 0000
+lzcntq 000000010addcd65 -> 000000000000001f 0000
+lzcntq 00000000d7b2a9b5 -> 0000000000000020 0000
+lzcntq 000000008cae2718 -> 0000000000000020 0000
+lzcntq 000000006fc61693 -> 0000000000000021 0000
+lzcntq 000000004686be6e -> 0000000000000021 0000
+lzcntq 00000000380a0af2 -> 0000000000000022 0000
+lzcntq 0000000021536a83 -> 0000000000000022 0000
+lzcntq 000000001af3d8f7 -> 0000000000000023 0000
+lzcntq 000000001193de15 -> 0000000000000023 0000
+lzcntq 000000000df6b244 -> 0000000000000024 0000
+lzcntq 0000000008d2446b -> 0000000000000024 0000
+lzcntq 0000000007028a18 -> 0000000000000025 0000
+lzcntq 00000000042b7735 -> 0000000000000025 0000
+lzcntq 00000000035ecaa5 -> 0000000000000026 0000
+lzcntq 000000000232b89b -> 0000000000000026 0000
+lzcntq 0000000001bf185a -> 0000000000000027 0000
+lzcntq 00000000011a1af9 -> 0000000000000027 0000
+lzcntq 0000000000e0282a -> 0000000000000028 0000
+lzcntq 0000000000854da9 -> 0000000000000028 0000
+lzcntq 00000000006bcf62 -> 0000000000000029 0000
+lzcntq 0000000000464f77 -> 0000000000000029 0000
+lzcntq 000000000037dac9 -> 000000000000002a 0000
+lzcntq 0000000000234910 -> 000000000000002a 0000
+lzcntq 00000000001c0a27 -> 000000000000002b 0000
+lzcntq 000000000010add9 -> 000000000000002b 0000
+lzcntq 00000000000d7b28 -> 000000000000002c 0000
+lzcntq 000000000008cae0 -> 000000000000002c 0000
+lzcntq 000000000006fc5f -> 000000000000002d 0000
+lzcntq 0000000000046871 -> 000000000000002d 0000
+lzcntq 000000000003809d -> 000000000000002e 0000
+lzcntq 000000000002152c -> 000000000000002e 0000
+lzcntq 000000000001af3b -> 000000000000002f 0000
+lzcntq 000000000001193c -> 000000000000002f 0000
+lzcntq 000000000000df6a -> 0000000000000030 0000
+lzcntq 0000000000008d23 -> 0000000000000030 0000
+lzcntq 0000000000007026 -> 0000000000000031 0000
+lzcntq 00000000000042b3 -> 0000000000000031 0000
+lzcntq 00000000000035e9 -> 0000000000000032 0000
+lzcntq 0000000000002329 -> 0000000000000032 0000
+lzcntq 0000000000001bef -> 0000000000000033 0000
+lzcntq 00000000000011a3 -> 0000000000000033 0000
+lzcntq 0000000000000e02 -> 0000000000000034 0000
+lzcntq 0000000000000853 -> 0000000000000034 0000
+lzcntq 00000000000006ba -> 0000000000000035 0000
+lzcntq 0000000000000464 -> 0000000000000035 0000
+lzcntq 000000000000037d -> 0000000000000036 0000
+lzcntq 0000000000000233 -> 0000000000000036 0000
+lzcntq 00000000000001be -> 0000000000000037 0000
+lzcntq 0000000000000119 -> 0000000000000037 0000
+lzcntq 00000000000000de -> 0000000000000038 0000
+lzcntq 000000000000008c -> 0000000000000038 0000
+lzcntq 000000000000006f -> 0000000000000039 0000
+lzcntq 0000000000000045 -> 0000000000000039 0000
+lzcntq 0000000000000037 -> 000000000000003a 0000
+lzcntq 0000000000000022 -> 000000000000003a 0000
+lzcntq 000000000000001b -> 000000000000003b 0000
+lzcntq 0000000000000010 -> 000000000000003b 0000
+lzcntq 000000000000000c -> 000000000000003c 0000
+lzcntq 0000000000000007 -> 000000000000003d 0000
+lzcntq 0000000000000003 -> 000000000000003e 0000
+lzcntq 0000000000000001 -> 000000000000003f 0000
+lzcntq 0000000000000000 -> 0000000000000040 0001
+lzcntl fedc192837475675 -> 0000000000000002 0000
+lzcntl 8efcf23ad7e922f3 -> 0000000000000000 0040
+lzcntl 7068b90cdf850938 -> 0000000000000000 0040
+lzcntl 42db3e5ed85503a5 -> 0000000000000000 0040
+lzcntl 35eea72efbea67d7 -> 0000000000000000 0040
+lzcntl 232c23d3b476ef47 -> 0000000000000000 0040
+lzcntl 1bf0c1bf27fbb3ab -> 0000000000000002 0000
+lzcntl 11a1311a29a562ea -> 0000000000000002 0000
+lzcntl 0e02582b8350ffd0 -> 0000000000000000 0040
+lzcntl 0854b4408f5b9e17 -> 0000000000000000 0040
+lzcntl 06bcf33434328063 -> 0000000000000002 0000
+lzcntl 0464f596e5f3ab8a -> 0000000000000000 0040
+lzcntl 037dac8063df281c -> 0000000000000001 0000
+lzcntl 0234910d6d0cfe89 -> 0000000000000001 0000
+lzcntl 01c0a27d7eaa2575 -> 0000000000000001 0000
+lzcntl 010adda943af43d8 -> 0000000000000001 0000
+lzcntl 00d7b2ae8c91c8ce -> 0000000000000000 0040
+lzcntl 008cae284a0c2065 -> 0000000000000001 0000
+lzcntl 006fc6190eb4fc04 -> 0000000000000004 0000
+lzcntl 004686bd6e829ce5 -> 0000000000000001 0000
+lzcntl 00380a0b248034f1 -> 0000000000000002 0000
+lzcntl 0021536a650d4fc6 -> 0000000000000001 0000
+lzcntl 001af3d8d0c8c068 -> 0000000000000000 0040
+lzcntl 001193de10460316 -> 0000000000000003 0000
+lzcntl 000df6b241dd45c1 -> 0000000000000001 0000
+lzcntl 0008d24469947f91 -> 0000000000000001 0000
+lzcntl 0007028a17f7fc21 -> 0000000000000003 0000
+lzcntl 00042b77370e9574 -> 0000000000000002 0000
+lzcntl 00035ecaa6c8cb9c -> 0000000000000000 0040
+lzcntl 000232b89c5ca207 -> 0000000000000000 0040
+lzcntl 0001bf185a53fb83 -> 0000000000000001 0000
+lzcntl 00011a1af9c2f08e -> 0000000000000000 0040
+lzcntl 0000e0282bc137ba -> 0000000000000002 0000
+lzcntl 0000854daa0b4caf -> 0000000000000000 0040
+lzcntl 00006bcf63e2fc01 -> 0000000000000001 0000
+lzcntl 0000464f7852a469 -> 0000000000000001 0000
+lzcntl 000037dac915aa8f -> 0000000000000000 0040
+lzcntl 0000234911b3280d -> 0000000000000003 0000
+lzcntl 00001c0a2862c244 -> 0000000000000002 0000
+lzcntl 000010addcd6577a -> 0000000000000000 0040
+lzcntl 00000d7b2a9b6ac9 -> 0000000000000002 0000
+lzcntl 000008cae2719cd4 -> 0000000000000000 0040
+lzcntl 000006fc61694403 -> 0000000000000001 0000
+lzcntl 000004686be70610 -> 0000000000000001 0000
+lzcntl 00000380a0af0023 -> 0000000000000000 0040
+lzcntl 0000021536a82984 -> 0000000000000002 0000
+lzcntl 000001af3d8f8abd -> 0000000000000002 0000
+lzcntl 000001193de14a82 -> 0000000000000002 0000
+lzcntl 000000df6b24569d -> 0000000000000001 0000
+lzcntl 0000008d2446cc8e -> 0000000000000002 0000
+lzcntl 0000007028a18af6 -> 0000000000000002 0000
+lzcntl 00000042b7735995 -> 0000000000000000 0040
+lzcntl 00000035ecaa6d9d -> 0000000000000000 0040
+lzcntl 000000232b89c661 -> 0000000000000002 0000
+lzcntl 0000001bf185a509 -> 0000000000000000 0040
+lzcntl 00000011a1af9c11 -> 0000000000000000 0040
+lzcntl 0000000e0282bbfd -> 0000000000000006 0000
+lzcntl 0000000854daa1a4 -> 0000000000000001 0000
+lzcntl 00000006bcf63eb9 -> 0000000000000000 0040
+lzcntl 0000000464f78590 -> 0000000000000001 0000
+lzcntl 000000037dac916c -> 0000000000000001 0000
+lzcntl 0000000234911b32 -> 0000000000000002 0000
+lzcntl 00000001c0a2862b -> 0000000000000000 0040
+lzcntl 000000010addcd65 -> 0000000000000004 0000
+lzcntl 00000000d7b2a9b5 -> 0000000000000000 0040
+lzcntl 000000008cae2718 -> 0000000000000000 0040
+lzcntl 000000006fc61693 -> 0000000000000001 0000
+lzcntl 000000004686be6e -> 0000000000000001 0000
+lzcntl 00000000380a0af2 -> 0000000000000002 0000
+lzcntl 0000000021536a83 -> 0000000000000002 0000
+lzcntl 000000001af3d8f7 -> 0000000000000003 0000
+lzcntl 000000001193de15 -> 0000000000000003 0000
+lzcntl 000000000df6b244 -> 0000000000000004 0000
+lzcntl 0000000008d2446b -> 0000000000000004 0000
+lzcntl 0000000007028a18 -> 0000000000000005 0000
+lzcntl 00000000042b7735 -> 0000000000000005 0000
+lzcntl 00000000035ecaa5 -> 0000000000000006 0000
+lzcntl 000000000232b89b -> 0000000000000006 0000
+lzcntl 0000000001bf185a -> 0000000000000007 0000
+lzcntl 00000000011a1af9 -> 0000000000000007 0000
+lzcntl 0000000000e0282a -> 0000000000000008 0000
+lzcntl 0000000000854da9 -> 0000000000000008 0000
+lzcntl 00000000006bcf62 -> 0000000000000009 0000
+lzcntl 0000000000464f77 -> 0000000000000009 0000
+lzcntl 000000000037dac9 -> 000000000000000a 0000
+lzcntl 0000000000234910 -> 000000000000000a 0000
+lzcntl 00000000001c0a27 -> 000000000000000b 0000
+lzcntl 000000000010add9 -> 000000000000000b 0000
+lzcntl 00000000000d7b28 -> 000000000000000c 0000
+lzcntl 000000000008cae0 -> 000000000000000c 0000
+lzcntl 000000000006fc5f -> 000000000000000d 0000
+lzcntl 0000000000046871 -> 000000000000000d 0000
+lzcntl 000000000003809d -> 000000000000000e 0000
+lzcntl 000000000002152c -> 000000000000000e 0000
+lzcntl 000000000001af3b -> 000000000000000f 0000
+lzcntl 000000000001193c -> 000000000000000f 0000
+lzcntl 000000000000df6a -> 0000000000000010 0000
+lzcntl 0000000000008d23 -> 0000000000000010 0000
+lzcntl 0000000000007026 -> 0000000000000011 0000
+lzcntl 00000000000042b3 -> 0000000000000011 0000
+lzcntl 00000000000035e9 -> 0000000000000012 0000
+lzcntl 0000000000002329 -> 0000000000000012 0000
+lzcntl 0000000000001bef -> 0000000000000013 0000
+lzcntl 00000000000011a3 -> 0000000000000013 0000
+lzcntl 0000000000000e02 -> 0000000000000014 0000
+lzcntl 0000000000000853 -> 0000000000000014 0000
+lzcntl 00000000000006ba -> 0000000000000015 0000
+lzcntl 0000000000000464 -> 0000000000000015 0000
+lzcntl 000000000000037d -> 0000000000000016 0000
+lzcntl 0000000000000233 -> 0000000000000016 0000
+lzcntl 00000000000001be -> 0000000000000017 0000
+lzcntl 0000000000000119 -> 0000000000000017 0000
+lzcntl 00000000000000de -> 0000000000000018 0000
+lzcntl 000000000000008c -> 0000000000000018 0000
+lzcntl 000000000000006f -> 0000000000000019 0000
+lzcntl 0000000000000045 -> 0000000000000019 0000
+lzcntl 0000000000000037 -> 000000000000001a 0000
+lzcntl 0000000000000022 -> 000000000000001a 0000
+lzcntl 000000000000001b -> 000000000000001b 0000
+lzcntl 0000000000000010 -> 000000000000001b 0000
+lzcntl 000000000000000c -> 000000000000001c 0000
+lzcntl 0000000000000007 -> 000000000000001d 0000
+lzcntl 0000000000000003 -> 000000000000001e 0000
+lzcntl 0000000000000001 -> 000000000000001f 0000
+lzcntl 0000000000000000 -> 0000000000000020 0001
+lzcntw fedc192837475675 -> 5555555555550001 0000
+lzcntw 8efcf23ad7e922f3 -> 5555555555550002 0000
+lzcntw 7068b90cdf850938 -> 5555555555550004 0000
+lzcntw 42db3e5ed85503a5 -> 5555555555550006 0000
+lzcntw 35eea72efbea67d7 -> 5555555555550001 0000
+lzcntw 232c23d3b476ef47 -> 5555555555550000 0040
+lzcntw 1bf0c1bf27fbb3ab -> 5555555555550000 0040
+lzcntw 11a1311a29a562ea -> 5555555555550001 0000
+lzcntw 0e02582b8350ffd0 -> 5555555555550000 0040
+lzcntw 0854b4408f5b9e17 -> 5555555555550000 0040
+lzcntw 06bcf33434328063 -> 5555555555550000 0040
+lzcntw 0464f596e5f3ab8a -> 5555555555550000 0040
+lzcntw 037dac8063df281c -> 5555555555550002 0000
+lzcntw 0234910d6d0cfe89 -> 5555555555550000 0040
+lzcntw 01c0a27d7eaa2575 -> 5555555555550002 0000
+lzcntw 010adda943af43d8 -> 5555555555550001 0000
+lzcntw 00d7b2ae8c91c8ce -> 5555555555550000 0040
+lzcntw 008cae284a0c2065 -> 5555555555550002 0000
+lzcntw 006fc6190eb4fc04 -> 5555555555550000 0040
+lzcntw 004686bd6e829ce5 -> 5555555555550000 0040
+lzcntw 00380a0b248034f1 -> 5555555555550002 0000
+lzcntw 0021536a650d4fc6 -> 5555555555550001 0000
+lzcntw 001af3d8d0c8c068 -> 5555555555550000 0040
+lzcntw 001193de10460316 -> 5555555555550006 0000
+lzcntw 000df6b241dd45c1 -> 5555555555550001 0000
+lzcntw 0008d24469947f91 -> 5555555555550001 0000
+lzcntw 0007028a17f7fc21 -> 5555555555550000 0040
+lzcntw 00042b77370e9574 -> 5555555555550000 0040
+lzcntw 00035ecaa6c8cb9c -> 5555555555550000 0040
+lzcntw 000232b89c5ca207 -> 5555555555550000 0040
+lzcntw 0001bf185a53fb83 -> 5555555555550000 0040
+lzcntw 00011a1af9c2f08e -> 5555555555550000 0040
+lzcntw 0000e0282bc137ba -> 5555555555550002 0000
+lzcntw 0000854daa0b4caf -> 5555555555550001 0000
+lzcntw 00006bcf63e2fc01 -> 5555555555550000 0040
+lzcntw 0000464f7852a469 -> 5555555555550000 0040
+lzcntw 000037dac915aa8f -> 5555555555550000 0040
+lzcntw 0000234911b3280d -> 5555555555550002 0000
+lzcntw 00001c0a2862c244 -> 5555555555550000 0040
+lzcntw 000010addcd6577a -> 5555555555550001 0000
+lzcntw 00000d7b2a9b6ac9 -> 5555555555550001 0000
+lzcntw 000008cae2719cd4 -> 5555555555550000 0040
+lzcntw 000006fc61694403 -> 5555555555550001 0000
+lzcntw 000004686be70610 -> 5555555555550005 0000
+lzcntw 00000380a0af0023 -> 555555555555000a 0000
+lzcntw 0000021536a82984 -> 5555555555550002 0000
+lzcntw 000001af3d8f8abd -> 5555555555550000 0040
+lzcntw 000001193de14a82 -> 5555555555550001 0000
+lzcntw 000000df6b24569d -> 5555555555550001 0000
+lzcntw 0000008d2446cc8e -> 5555555555550000 0040
+lzcntw 0000007028a18af6 -> 5555555555550000 0040
+lzcntw 00000042b7735995 -> 5555555555550001 0000
+lzcntw 00000035ecaa6d9d -> 5555555555550001 0000
+lzcntw 000000232b89c661 -> 5555555555550000 0040
+lzcntw 0000001bf185a509 -> 5555555555550000 0040
+lzcntw 00000011a1af9c11 -> 5555555555550000 0040
+lzcntw 0000000e0282bbfd -> 5555555555550000 0040
+lzcntw 0000000854daa1a4 -> 5555555555550000 0040
+lzcntw 00000006bcf63eb9 -> 5555555555550002 0000
+lzcntw 0000000464f78590 -> 5555555555550000 0040
+lzcntw 000000037dac916c -> 5555555555550000 0040
+lzcntw 0000000234911b32 -> 5555555555550003 0000
+lzcntw 00000001c0a2862b -> 5555555555550000 0040
+lzcntw 000000010addcd65 -> 5555555555550000 0040
+lzcntw 00000000d7b2a9b5 -> 5555555555550000 0040
+lzcntw 000000008cae2718 -> 5555555555550002 0000
+lzcntw 000000006fc61693 -> 5555555555550003 0000
+lzcntw 000000004686be6e -> 5555555555550000 0040
+lzcntw 00000000380a0af2 -> 5555555555550004 0000
+lzcntw 0000000021536a83 -> 5555555555550001 0000
+lzcntw 000000001af3d8f7 -> 5555555555550000 0040
+lzcntw 000000001193de15 -> 5555555555550000 0040
+lzcntw 000000000df6b244 -> 5555555555550000 0040
+lzcntw 0000000008d2446b -> 5555555555550001 0000
+lzcntw 0000000007028a18 -> 5555555555550000 0040
+lzcntw 00000000042b7735 -> 5555555555550001 0000
+lzcntw 00000000035ecaa5 -> 5555555555550000 0040
+lzcntw 000000000232b89b -> 5555555555550000 0040
+lzcntw 0000000001bf185a -> 5555555555550003 0000
+lzcntw 00000000011a1af9 -> 5555555555550003 0000
+lzcntw 0000000000e0282a -> 5555555555550002 0000
+lzcntw 0000000000854da9 -> 5555555555550001 0000
+lzcntw 00000000006bcf62 -> 5555555555550000 0040
+lzcntw 0000000000464f77 -> 5555555555550001 0000
+lzcntw 000000000037dac9 -> 5555555555550000 0040
+lzcntw 0000000000234910 -> 5555555555550001 0000
+lzcntw 00000000001c0a27 -> 5555555555550004 0000
+lzcntw 000000000010add9 -> 5555555555550000 0040
+lzcntw 00000000000d7b28 -> 5555555555550001 0000
+lzcntw 000000000008cae0 -> 5555555555550000 0040
+lzcntw 000000000006fc5f -> 5555555555550000 0040
+lzcntw 0000000000046871 -> 5555555555550001 0000
+lzcntw 000000000003809d -> 5555555555550000 0040
+lzcntw 000000000002152c -> 5555555555550003 0000
+lzcntw 000000000001af3b -> 5555555555550000 0040
+lzcntw 000000000001193c -> 5555555555550003 0000
+lzcntw 000000000000df6a -> 5555555555550000 0040
+lzcntw 0000000000008d23 -> 5555555555550000 0040
+lzcntw 0000000000007026 -> 5555555555550001 0000
+lzcntw 00000000000042b3 -> 5555555555550001 0000
+lzcntw 00000000000035e9 -> 5555555555550002 0000
+lzcntw 0000000000002329 -> 5555555555550002 0000
+lzcntw 0000000000001bef -> 5555555555550003 0000
+lzcntw 00000000000011a3 -> 5555555555550003 0000
+lzcntw 0000000000000e02 -> 5555555555550004 0000
+lzcntw 0000000000000853 -> 5555555555550004 0000
+lzcntw 00000000000006ba -> 5555555555550005 0000
+lzcntw 0000000000000464 -> 5555555555550005 0000
+lzcntw 000000000000037d -> 5555555555550006 0000
+lzcntw 0000000000000233 -> 5555555555550006 0000
+lzcntw 00000000000001be -> 5555555555550007 0000
+lzcntw 0000000000000119 -> 5555555555550007 0000
+lzcntw 00000000000000de -> 5555555555550008 0000
+lzcntw 000000000000008c -> 5555555555550008 0000
+lzcntw 000000000000006f -> 5555555555550009 0000
+lzcntw 0000000000000045 -> 5555555555550009 0000
+lzcntw 0000000000000037 -> 555555555555000a 0000
+lzcntw 0000000000000022 -> 555555555555000a 0000
+lzcntw 000000000000001b -> 555555555555000b 0000
+lzcntw 0000000000000010 -> 555555555555000b 0000
+lzcntw 000000000000000c -> 555555555555000c 0000
+lzcntw 0000000000000007 -> 555555555555000d 0000
+lzcntw 0000000000000003 -> 555555555555000e 0000
+lzcntw 0000000000000001 -> 555555555555000f 0000
+lzcntw 0000000000000000 -> 5555555555550010 0001
diff --git a/main/none/tests/amd64/lzcnt64.vgtest b/main/none/tests/amd64/lzcnt64.vgtest
new file mode 100644
index 0000000..74d82b5
--- /dev/null
+++ b/main/none/tests/amd64/lzcnt64.vgtest
@@ -0,0 +1,3 @@
+prog: lzcnt64
+prereq: ../../../tests/x86_amd64_features amd64-lzcnt
+vgopts: -q
diff --git a/main/none/tests/amd64/movbe.c b/main/none/tests/amd64/movbe.c
new file mode 100644
index 0000000..4b23696
--- /dev/null
+++ b/main/none/tests/amd64/movbe.c
@@ -0,0 +1,81 @@
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <malloc.h>
+
+typedef unsigned char UChar;
+typedef unsigned int UInt;
+typedef unsigned long int UWord;
+typedef unsigned long long int ULong;
+
+
+typedef struct { UChar cs[40]; } Block;
+
+void showBlock ( char* msg, Block* b )
+{
+ int i;
+ printf(" %s ", msg);
+ for (i = 0; i < 40; i++)
+ printf("%02x", (UInt)b->cs[i]);
+ printf("\n");
+}
+
+UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+void randBlock ( Block* b )
+{
+ int i;
+ UChar* p = (UChar*)b;
+ for (i = 0; i < sizeof(Block); i++)
+ p[i] = randUChar();
+}
+
+/* Generate a function test_NAME, that tests the given insn.
+ The insn may only mention (%rax) and r9. */
+
+#define GEN_test_Monly(_name, _mem_form) \
+ \
+ __attribute__ ((noinline)) static void test_##_name ( void ) \
+ { \
+ Block* b = memalign(32, sizeof(Block)); \
+ randBlock(b); \
+ printf("%s\n", #_name); \
+ showBlock("before", b); \
+ __asm__ __volatile__( \
+ "leaq 16(%0),%%rax" "\n\t" \
+ "movq 24(%0),%%r9" "\n\t" \
+ _mem_form "\n\t" \
+ "movq %%r9, 32(%0)" "\n\t" \
+ : /*OUT*/ \
+ : /*IN*/"r"(b) \
+ : /*TRASH*/"r9","rax","memory","cc" \
+ ); \
+ showBlock("after ", b); \
+ printf("\n"); \
+ free(b); \
+ }
+
+GEN_test_Monly( MOVBE_RtoM_64, "movbe %%r9, 1(%%rax)")
+GEN_test_Monly( MOVBE_RtoM_32, "movbe %%r9d,1(%%rax)")
+GEN_test_Monly( MOVBE_RtoM_16, "movbe %%r9w,1(%%rax)")
+
+GEN_test_Monly( MOVBE_MtoR_64, "movbe 1(%%rax), %%r9")
+GEN_test_Monly( MOVBE_MtoR_32, "movbe 1(%%rax), %%r9d")
+GEN_test_Monly( MOVBE_MtoR_16, "movbe 1(%%rax), %%r9w")
+
+int main ( void )
+{
+ test_MOVBE_RtoM_64();
+ test_MOVBE_RtoM_32();
+ test_MOVBE_RtoM_16();
+ test_MOVBE_MtoR_64();
+ test_MOVBE_MtoR_32();
+ test_MOVBE_MtoR_16();
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/amd64/movbe.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/amd64/movbe.stderr.exp
diff --git a/main/none/tests/amd64/movbe.stdout.exp b/main/none/tests/amd64/movbe.stdout.exp
new file mode 100644
index 0000000..ad779ba
--- /dev/null
+++ b/main/none/tests/amd64/movbe.stdout.exp
@@ -0,0 +1,24 @@
+MOVBE_RtoM_64
+ before 00571784494af2981ecac9199de375513bd127afa6e9c3690d6a95fac528657d501eefeec0d8b847
+ after 00571784494af2981ecac9199de375513b7d6528c5fa956a0d6a95fac528657d0d6a95fac528657d
+
+MOVBE_RtoM_32
+ before 84c4457d8560b160b244a056e51599fe2751bca75afbd2b6382dccdbc2829139fd673a5c2148a319
+ after 84c4457d8560b160b244a056e51599fe27dbcc2d38fbd2b6382dccdbc2829139382dccdbc2829139
+
+MOVBE_RtoM_16
+ before 179e655064dc2a846b3e625d19775d06e540bc6839c44b4a36ed3550df9899d8979b83b70eb840d7
+ after 179e655064dc2a846b3e625d19775d06e5ed366839c44b4a36ed3550df9899d836ed3550df9899d8
+
+MOVBE_MtoR_64
+ before 856c13b8709950cb8315cab0121ab056db93c0f8294addf95df605a7d127a7d31f195c53c95bf85f
+ after 856c13b8709950cb8315cab0121ab056db93c0f8294addf95df605a7d127a7d35df9dd4a29f8c093
+
+MOVBE_MtoR_32
+ before 3d6603cf39008e39979569ee6d5cbcd8966cf73d98a42d54e87fc9cb92bba12040ef72e29bf3afcf
+ after 3d6603cf39008e39979569ee6d5cbcd8966cf73d98a42d54e87fc9cb92bba120983df76c00000000
+
+MOVBE_MtoR_16
+ before 172ebcce16c982d16eb865944fab9d368adae4bb36b59768b76e2305226ee0f4069b4435908d7b40
+ after 172ebcce16c982d16eb865944fab9d368adae4bb36b59768b76e2305226ee0f4e4da2305226ee0f4
+
diff --git a/main/none/tests/amd64/movbe.vgtest b/main/none/tests/amd64/movbe.vgtest
new file mode 100644
index 0000000..a34320b
--- /dev/null
+++ b/main/none/tests/amd64/movbe.vgtest
@@ -0,0 +1,3 @@
+prereq: test -e movbe
+prog: movbe
+vgopts: -q
diff --git a/main/none/tests/amd64/nan80and64.c b/main/none/tests/amd64/nan80and64.c
new file mode 100644
index 0000000..6fa46c3
--- /dev/null
+++ b/main/none/tests/amd64/nan80and64.c
@@ -0,0 +1,140 @@
+
+/* Test conversions between 64- and 80- bit quiet NaNs. Uses
+ "canonical forms" for qNaNs. It also tests sNaNs but it's not
+ clear what the canonical form of them should be, so the results are
+ pretty much irrelevant. Failure to do this right is the cause
+ of https://bugzilla.mozilla.org/show_bug.cgi?id=738117
+*/
+
+#include <assert.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+typedef unsigned char UChar;
+
+
+void do_64_to_80 ( UChar* dst, UChar* src )
+{
+ __asm__ __volatile__(
+ "fldl (%0); fstpt (%1)"
+ : : "r"(src), "r"(dst) : "memory"
+ );
+}
+
+void do_80_to_64 ( UChar* dst, UChar* src )
+{
+ __asm__ __volatile__(
+ "fldt (%0); fstpl (%1)"
+ : : "r"(src), "r"(dst) : "memory"
+ );
+}
+
+void print80 ( char* s, UChar* v )
+{
+ int i;
+ printf("%s", s);
+ for (i = 9; i >= 0; i--)
+ printf("%02x", (unsigned int)v[i]);
+ printf("\n");
+}
+
+void print64 ( char* s, UChar* v )
+{
+ int i;
+ printf("%s", s);
+ for (i = 7; i >= 0; i--) {
+ printf("%02x", (unsigned int)v[i]);
+ }
+ printf("\n");
+}
+
+#if 0
+void gen_qnan_64 ( UChar* dst )
+{
+
+}
+#endif
+
+#define SWAPC(_xx,_yy) { UChar tmp = _xx; _xx = _yy; _yy = tmp; }
+
+static void rev64 ( UChar* f64 )
+{
+ SWAPC( f64[0], f64[7] );
+ SWAPC( f64[1], f64[6] );
+ SWAPC( f64[2], f64[5] );
+ SWAPC( f64[3], f64[4] );
+}
+
+static void rev80 ( UChar* f80 )
+{
+ SWAPC( f80[0], f80[9] );
+ SWAPC( f80[1], f80[8] );
+ SWAPC( f80[2], f80[7] );
+ SWAPC( f80[3], f80[6] );
+ SWAPC( f80[4], f80[5] );
+}
+
+#undef SWAPC
+
+int main ( void )
+{
+ UChar ref_qnan64[8]
+ = { 0x7f, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+ UChar ref_snan64[8]
+ = { 0x7f, 0xf4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+ UChar ref_qnan80[10]
+ = { 0x7f, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+ UChar ref_snan80[10]
+ = { 0x7f, 0xff, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+ rev64( ref_qnan64 );
+ rev64( ref_snan64 );
+ rev80( ref_qnan80 );
+ rev80( ref_snan80 );
+
+ UChar* res = malloc(10);
+#define ZAP memset(res, 0x55, 10)
+
+
+ int pass;
+ for (pass = 1; pass <= 2; pass++) {
+
+ ZAP; do_64_to_80( res, ref_qnan64 );
+ print64( "src = qnan64: ", ref_qnan64 );
+ print80( "dst = qnan80: ", res );
+ printf("\n");
+
+ ZAP; do_64_to_80( res, ref_snan64 );
+ print64( "src = snan64: ", ref_snan64 );
+ print80( "dst = snan80: ", res );
+ printf("\n");
+
+ ZAP; do_80_to_64( res, ref_qnan80 );
+ print80( "src = qnan80: ", ref_qnan80 );
+ print64( "dst = qnan64: ", res );
+ printf("\n");
+
+ ZAP; do_80_to_64( res, ref_snan80 );
+ print80( "src = snan80: ", ref_snan80 );
+ print64( "dst = snan64: ", res );
+ printf("\n");
+
+ /* now make all the reference inputs negative and do it again */
+
+ ref_qnan64[7] ^= 0x80;
+ ref_snan64[7] ^= 0x80;
+
+ ref_qnan80[9] ^= 0x80;
+ ref_snan80[9] ^= 0x80;
+
+ }
+
+#undef ZAP
+
+ free(res);
+ return 0;
+}
diff --git a/main/none/tests/amd64/nan80and64.stderr.exp b/main/none/tests/amd64/nan80and64.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/amd64/nan80and64.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/amd64/nan80and64.stdout.exp b/main/none/tests/amd64/nan80and64.stdout.exp
new file mode 100644
index 0000000..aa10807
--- /dev/null
+++ b/main/none/tests/amd64/nan80and64.stdout.exp
@@ -0,0 +1,24 @@
+src = qnan64: 7ff8000000000000
+dst = qnan80: 7fffc000000000000000
+
+src = snan64: 7ff4000000000000
+dst = snan80: 7fffbfffffffffffffff
+
+src = qnan80: 7fffc000000000000000
+dst = qnan64: 7ff8000000000000
+
+src = snan80: 7fffa000000000000000
+dst = snan64: 7ff7ffffffffffff
+
+src = qnan64: fff8000000000000
+dst = qnan80: ffffc000000000000000
+
+src = snan64: fff4000000000000
+dst = snan80: ffffbfffffffffffffff
+
+src = qnan80: ffffc000000000000000
+dst = qnan64: fff8000000000000
+
+src = snan80: ffffa000000000000000
+dst = snan64: fff7ffffffffffff
+
diff --git a/main/none/tests/amd64/nan80and64.vgtest b/main/none/tests/amd64/nan80and64.vgtest
new file mode 100644
index 0000000..8047e20
--- /dev/null
+++ b/main/none/tests/amd64/nan80and64.vgtest
@@ -0,0 +1 @@
+prog: nan80and64
diff --git a/main/none/tests/amd64/pcmpstr64.c b/main/none/tests/amd64/pcmpstr64.c
index d4184f8..b3a07b5 100644
--- a/main/none/tests/amd64/pcmpstr64.c
+++ b/main/none/tests/amd64/pcmpstr64.c
@@ -305,9 +305,6 @@
UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
for (hi = 0; hi < 16; hi++) {
- if ((validL & (1 << hi)) == 0)
- // run off the end of the haystack
- break;
UInt m = 1;
for (ni = 0; ni < 16; ni++) {
if ((validR & (1 << ni)) == 0) break;
@@ -316,6 +313,9 @@
if (argL[i] != argR[ni]) { m = 0; break; }
}
boolRes |= (m << hi);
+ if ((validL & (1 << hi)) == 0)
+ // run off the end of the haystack
+ break;
}
// boolRes is "pre-invalidated"
@@ -573,8 +573,8 @@
memcpy(&block[1], argR, sizeof(V128));
ULong res = 0, flags = 0;
__asm__ __volatile__(
- "movdqa 0(%2), %%xmm2" "\n\t"
- "movdqa 16(%2), %%xmm11" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
"pcmpistri $0x0C, %%xmm2, %%xmm11" "\n\t"
//"pcmpistrm $0x0C, %%xmm2, %%xmm11" "\n\t"
//"movd %%xmm0, %%ecx" "\n\t"
@@ -639,6 +639,11 @@
try_istri(wot,h,s, "1111111111111234", "1111111111111234");
try_istri(wot,h,s, "a111111111111111", "000000000000000a");
try_istri(wot,h,s, "b111111111111111", "000000000000000a");
+
+ try_istri(wot,h,s, "b111111111111111", "0000000000000000");
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "123456789abcdef1", "0000000000000000");
+ try_istri(wot,h,s, "0000000000000000", "123456789abcdef1");
}
@@ -1264,1101 +1269,6 @@
istri_0C();
istri_12();
istri_44();
- return 0;
-}
-
-/* Tests in detail the core arithmetic for pcmp{e,i}str{i,m} using
- pcmpistri to drive it. Does not check the e-vs-i or i-vs-m
- aspect. */
-
-#include <string.h>
-#include <stdio.h>
-#include <assert.h>
-
-typedef unsigned int UInt;
-typedef signed int Int;
-typedef unsigned char UChar;
-typedef unsigned long long int ULong;
-typedef UChar Bool;
-#define False ((Bool)0)
-#define True ((Bool)1)
-
-//typedef unsigned char V128[16];
-typedef
- union {
- UChar uChar[16];
- UInt uInt[4];
- }
- V128;
-
-#define SHIFT_O 11
-#define SHIFT_S 7
-#define SHIFT_Z 6
-#define SHIFT_A 4
-#define SHIFT_C 0
-#define SHIFT_P 2
-
-#define MASK_O (1ULL << SHIFT_O)
-#define MASK_S (1ULL << SHIFT_S)
-#define MASK_Z (1ULL << SHIFT_Z)
-#define MASK_A (1ULL << SHIFT_A)
-#define MASK_C (1ULL << SHIFT_C)
-#define MASK_P (1ULL << SHIFT_P)
-
-
-UInt clz32 ( UInt x )
-{
- Int y, m, n;
- y = -(x >> 16);
- m = (y >> 16) & 16;
- n = 16 - m;
- x = x >> m;
- y = x - 0x100;
- m = (y >> 16) & 8;
- n = n + m;
- x = x << m;
- y = x - 0x1000;
- m = (y >> 16) & 4;
- n = n + m;
- x = x << m;
- y = x - 0x4000;
- m = (y >> 16) & 2;
- n = n + m;
- x = x << m;
- y = x >> 14;
- m = y & ~(y >> 1);
- return n + 2 - m;
-}
-
-UInt ctz32 ( UInt x )
-{
- return 32 - clz32((~x) & (x-1));
-}
-
-void expand ( V128* dst, char* summary )
-{
- Int i;
- assert( strlen(summary) == 16 );
- for (i = 0; i < 16; i++) {
- UChar xx = 0;
- UChar x = summary[15-i];
- if (x >= '0' && x <= '9') { xx = x - '0'; }
- else if (x >= 'A' && x <= 'F') { xx = x - 'A' + 10; }
- else if (x >= 'a' && x <= 'f') { xx = x - 'a' + 10; }
- else assert(0);
-
- assert(xx < 16);
- xx = (xx << 4) | xx;
- assert(xx < 256);
- dst->uChar[i] = xx;
- }
-}
-
-void try_istri ( char* which,
- UInt(*h_fn)(V128*,V128*),
- UInt(*s_fn)(V128*,V128*),
- char* summL, char* summR )
-{
- assert(strlen(which) == 2);
- V128 argL, argR;
- expand(&argL, summL);
- expand(&argR, summR);
- UInt h_res = h_fn(&argL, &argR);
- UInt s_res = s_fn(&argL, &argR);
- printf("istri %s %s %s -> %08x %08x %s\n",
- which, summL, summR, h_res, s_res, h_res == s_res ? "" : "!!!!");
-}
-
-UInt zmask_from_V128 ( V128* arg )
-{
- UInt i, res = 0;
- for (i = 0; i < 16; i++) {
- res |= ((arg->uChar[i] == 0) ? 1 : 0) << i;
- }
- return res;
-}
-
-//////////////////////////////////////////////////////////
-// //
-// GENERAL //
-// //
-//////////////////////////////////////////////////////////
-
-
-/* Given partial results from a pcmpXstrX operation (intRes1,
- basically), generate an I format (index value for ECX) output, and
- also the new OSZACP flags.
-*/
-static
-void pcmpXstrX_WRK_gen_output_fmt_I(/*OUT*/V128* resV,
- /*OUT*/UInt* resOSZACP,
- UInt intRes1,
- UInt zmaskL, UInt zmaskR,
- UInt validL,
- UInt pol, UInt idx )
-{
- assert((pol >> 2) == 0);
- assert((idx >> 1) == 0);
-
- UInt intRes2 = 0;
- switch (pol) {
- case 0: intRes2 = intRes1; break; // pol +
- case 1: intRes2 = ~intRes1; break; // pol -
- case 2: intRes2 = intRes1; break; // pol m+
- case 3: intRes2 = intRes1 ^ validL; break; // pol m-
- }
- intRes2 &= 0xFFFF;
-
- // generate ecx value
- UInt newECX = 0;
- if (idx) {
- // index of ms-1-bit
- newECX = intRes2 == 0 ? 16 : (31 - clz32(intRes2));
- } else {
- // index of ls-1-bit
- newECX = intRes2 == 0 ? 16 : ctz32(intRes2);
- }
-
- *(UInt*)(&resV[0]) = newECX;
-
- // generate new flags, common to all ISTRI and ISTRM cases
- *resOSZACP // A, P are zero
- = ((intRes2 == 0) ? 0 : MASK_C) // C == 0 iff intRes2 == 0
- | ((zmaskL == 0) ? 0 : MASK_Z) // Z == 1 iff any in argL is 0
- | ((zmaskR == 0) ? 0 : MASK_S) // S == 1 iff any in argR is 0
- | ((intRes2 & 1) << SHIFT_O); // O == IntRes2[0]
-}
-
-
-/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M}
- variants.
-
- For xSTRI variants, the new ECX value is placed in the 32 bits
- pointed to by *resV. For xSTRM variants, the result is a 128 bit
- value and is placed at *resV in the obvious way.
-
- For all variants, the new OSZACP value is placed at *resOSZACP.
-
- argLV and argRV are the vector args. The caller must prepare a
- 16-bit mask for each, zmaskL and zmaskR. For ISTRx variants this
- must be 1 for each zero byte of of the respective arg. For ESTRx
- variants this is derived from the explicit length indication, and
- must be 0 in all places except at the bit index corresponding to
- the valid length (0 .. 16). If the valid length is 16 then the
- mask must be all zeroes. In all cases, bits 31:16 must be zero.
-
- imm8 is the original immediate from the instruction. isSTRM
- indicates whether this is a xSTRM or xSTRI variant, which controls
- how much of *res is written.
-
- If the given imm8 case can be handled, the return value is True.
- If not, False is returned, and neither *res not *resOSZACP are
- altered.
-*/
-
-Bool pcmpXstrX_WRK ( /*OUT*/V128* resV,
- /*OUT*/UInt* resOSZACP,
- V128* argLV, V128* argRV,
- UInt zmaskL, UInt zmaskR,
- UInt imm8, Bool isSTRM )
-{
- assert(imm8 < 0x80);
- assert((zmaskL >> 16) == 0);
- assert((zmaskR >> 16) == 0);
-
- /* Explicitly reject any imm8 values that haven't been validated,
- even if they would probably work. Life is too short to have
- unvalidated cases in the code base. */
- switch (imm8) {
- case 0x02: case 0x08: case 0x0C: case 0x12: case 0x1A:
- case 0x3A: case 0x44: case 0x4A:
- break;
- default:
- return False;
- }
-
- UInt fmt = (imm8 >> 0) & 3; // imm8[1:0] data format
- UInt agg = (imm8 >> 2) & 3; // imm8[3:2] aggregation fn
- UInt pol = (imm8 >> 4) & 3; // imm8[5:4] polarity
- UInt idx = (imm8 >> 6) & 1; // imm8[6] 1==msb/bytemask
-
- /*----------------------------------------*/
- /*-- strcmp on byte data --*/
- /*----------------------------------------*/
-
- if (agg == 2/*equal each, aka strcmp*/
- && (fmt == 0/*ub*/ || fmt == 2/*sb*/)
- && !isSTRM) {
- Int i;
- UChar* argL = (UChar*)argLV;
- UChar* argR = (UChar*)argRV;
- UInt boolResII = 0;
- for (i = 15; i >= 0; i--) {
- UChar cL = argL[i];
- UChar cR = argR[i];
- boolResII = (boolResII << 1) | (cL == cR ? 1 : 0);
- }
- UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
- UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
-
- // do invalidation, common to all equal-each cases
- UInt intRes1
- = (boolResII & validL & validR) // if both valid, use cmpres
- | (~ (validL | validR)); // if both invalid, force 1
- // else force 0
- intRes1 &= 0xFFFF;
-
- // generate I-format output
- pcmpXstrX_WRK_gen_output_fmt_I(
- resV, resOSZACP,
- intRes1, zmaskL, zmaskR, validL, pol, idx
- );
-
- return True;
- }
-
- /*----------------------------------------*/
- /*-- set membership on byte data --*/
- /*----------------------------------------*/
-
- if (agg == 0/*equal any, aka find chars in a set*/
- && (fmt == 0/*ub*/ || fmt == 2/*sb*/)
- && !isSTRM) {
- /* argL: the string, argR: charset */
- UInt si, ci;
- UChar* argL = (UChar*)argLV;
- UChar* argR = (UChar*)argRV;
- UInt boolRes = 0;
- UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
- UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
-
- for (si = 0; si < 16; si++) {
- if ((validL & (1 << si)) == 0)
- // run off the end of the string.
- break;
- UInt m = 0;
- for (ci = 0; ci < 16; ci++) {
- if ((validR & (1 << ci)) == 0) break;
- if (argR[ci] == argL[si]) { m = 1; break; }
- }
- boolRes |= (m << si);
- }
-
- // boolRes is "pre-invalidated"
- UInt intRes1 = boolRes & 0xFFFF;
-
- // generate I-format output
- pcmpXstrX_WRK_gen_output_fmt_I(
- resV, resOSZACP,
- intRes1, zmaskL, zmaskR, validL, pol, idx
- );
-
- return True;
- }
-
- /*----------------------------------------*/
- /*-- substring search on byte data --*/
- /*----------------------------------------*/
-
- if (agg == 3/*equal ordered, aka substring search*/
- && (fmt == 0/*ub*/ || fmt == 2/*sb*/)
- && !isSTRM) {
-
- /* argL: haystack, argR: needle */
- UInt ni, hi;
- UChar* argL = (UChar*)argLV;
- UChar* argR = (UChar*)argRV;
- UInt boolRes = 0;
- UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
- UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
- for (hi = 0; hi < 16; hi++) {
- if ((validL & (1 << hi)) == 0)
- // run off the end of the haystack
- break;
- UInt m = 1;
- for (ni = 0; ni < 16; ni++) {
- if ((validR & (1 << ni)) == 0) break;
- UInt i = ni + hi;
- if (i >= 16) break;
- if (argL[i] != argR[ni]) { m = 0; break; }
- }
- boolRes |= (m << hi);
- }
-
- // boolRes is "pre-invalidated"
- UInt intRes1 = boolRes & 0xFFFF;
-
- // generate I-format output
- pcmpXstrX_WRK_gen_output_fmt_I(
- resV, resOSZACP,
- intRes1, zmaskL, zmaskR, validL, pol, idx
- );
-
- return True;
- }
-
- /*----------------------------------------*/
- /*-- ranges, unsigned byte data --*/
- /*----------------------------------------*/
-
- if (agg == 1/*ranges*/
- && fmt == 0/*ub*/
- && !isSTRM) {
-
- /* argL: string, argR: range-pairs */
- UInt ri, si;
- UChar* argL = (UChar*)argLV;
- UChar* argR = (UChar*)argRV;
- UInt boolRes = 0;
- UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
- UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
- for (si = 0; si < 16; si++) {
- if ((validL & (1 << si)) == 0)
- // run off the end of the string
- break;
- UInt m = 0;
- for (ri = 0; ri < 16; ri += 2) {
- if ((validR & (3 << ri)) != (3 << ri)) break;
- if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) {
- m = 1; break;
- }
- }
- boolRes |= (m << si);
- }
-
- // boolRes is "pre-invalidated"
- UInt intRes1 = boolRes & 0xFFFF;
-
- // generate I-format output
- pcmpXstrX_WRK_gen_output_fmt_I(
- resV, resOSZACP,
- intRes1, zmaskL, zmaskR, validL, pol, idx
- );
-
- return True;
- }
-
- return False;
-}
-
-
-//////////////////////////////////////////////////////////
-// //
-// ISTRI_4A //
-// //
-//////////////////////////////////////////////////////////
-
-UInt h_pcmpistri_4A ( V128* argL, V128* argR )
-{
- V128 block[2];
- memcpy(&block[0], argL, sizeof(V128));
- memcpy(&block[1], argR, sizeof(V128));
- ULong res, flags;
- __asm__ __volatile__(
- "subq $1024, %%rsp" "\n\t"
- "movdqu 0(%2), %%xmm2" "\n\t"
- "movdqu 16(%2), %%xmm11" "\n\t"
- "pcmpistri $0x4A, %%xmm2, %%xmm11" "\n\t"
- "pushfq" "\n\t"
- "popq %%rdx" "\n\t"
- "movq %%rcx, %0" "\n\t"
- "movq %%rdx, %1" "\n\t"
- "addq $1024, %%rsp" "\n\t"
- : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
- : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
- );
- return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
-}
-
-UInt s_pcmpistri_4A ( V128* argLU, V128* argRU )
-{
- V128 resV;
- UInt resOSZACP, resECX;
- Bool ok
- = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
- zmask_from_V128(argLU),
- zmask_from_V128(argRU),
- 0x4A, False/*!isSTRM*/
- );
- assert(ok);
- resECX = resV.uInt[0];
- return (resOSZACP << 16) | resECX;
-}
-
-void istri_4A ( void )
-{
- char* wot = "4A";
- UInt(*h)(V128*,V128*) = h_pcmpistri_4A;
- UInt(*s)(V128*,V128*) = s_pcmpistri_4A;
-
- try_istri(wot,h,s, "0000000000000000", "0000000000000000");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa");
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa");
-
- try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa");
- try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa");
-
- try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa");
-
- try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
-}
-
-//////////////////////////////////////////////////////////
-// //
-// ISTRI_3A //
-// //
-//////////////////////////////////////////////////////////
-
-UInt h_pcmpistri_3A ( V128* argL, V128* argR )
-{
- V128 block[2];
- memcpy(&block[0], argL, sizeof(V128));
- memcpy(&block[1], argR, sizeof(V128));
- ULong res, flags;
- __asm__ __volatile__(
- "subq $1024, %%rsp" "\n\t"
- "movdqu 0(%2), %%xmm2" "\n\t"
- "movdqu 16(%2), %%xmm11" "\n\t"
- "pcmpistri $0x3A, %%xmm2, %%xmm11" "\n\t"
- "pushfq" "\n\t"
- "popq %%rdx" "\n\t"
- "movq %%rcx, %0" "\n\t"
- "movq %%rdx, %1" "\n\t"
- "addq $1024, %%rsp" "\n\t"
- : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
- : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
- );
- return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
-}
-
-UInt s_pcmpistri_3A ( V128* argLU, V128* argRU )
-{
- V128 resV;
- UInt resOSZACP, resECX;
- Bool ok
- = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
- zmask_from_V128(argLU),
- zmask_from_V128(argRU),
- 0x3A, False/*!isSTRM*/
- );
- assert(ok);
- resECX = resV.uInt[0];
- return (resOSZACP << 16) | resECX;
-}
-
-void istri_3A ( void )
-{
- char* wot = "3A";
- UInt(*h)(V128*,V128*) = h_pcmpistri_3A;
- UInt(*s)(V128*,V128*) = s_pcmpistri_3A;
-
- try_istri(wot,h,s, "0000000000000000", "0000000000000000");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa");
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa");
-
- try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa");
- try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa");
-
- try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa");
-
- try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
-}
-
-
-
-//////////////////////////////////////////////////////////
-// //
-// ISTRI_0C //
-// //
-//////////////////////////////////////////////////////////
-
-__attribute__((noinline))
-UInt h_pcmpistri_0C ( V128* argL, V128* argR )
-{
- V128 block[2];
- memcpy(&block[0], argL, sizeof(V128));
- memcpy(&block[1], argR, sizeof(V128));
- ULong res = 0, flags = 0;
- __asm__ __volatile__(
- "movdqa 0(%2), %%xmm2" "\n\t"
- "movdqa 16(%2), %%xmm11" "\n\t"
- "pcmpistri $0x0C, %%xmm2, %%xmm11" "\n\t"
- //"pcmpistrm $0x0C, %%xmm2, %%xmm11" "\n\t"
- //"movd %%xmm0, %%ecx" "\n\t"
- "pushfq" "\n\t"
- "popq %%rdx" "\n\t"
- "movq %%rcx, %0" "\n\t"
- "movq %%rdx, %1" "\n\t"
- : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
- : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
- );
- return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
-}
-
-UInt s_pcmpistri_0C ( V128* argLU, V128* argRU )
-{
- V128 resV;
- UInt resOSZACP, resECX;
- Bool ok
- = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
- zmask_from_V128(argLU),
- zmask_from_V128(argRU),
- 0x0C, False/*!isSTRM*/
- );
- assert(ok);
- resECX = resV.uInt[0];
- return (resOSZACP << 16) | resECX;
-}
-
-void istri_0C ( void )
-{
- char* wot = "0C";
- UInt(*h)(V128*,V128*) = h_pcmpistri_0C;
- UInt(*s)(V128*,V128*) = s_pcmpistri_0C;
-
- try_istri(wot,h,s, "111111111abcde11", "00000000000abcde");
-
- try_istri(wot,h,s, "111111111abcde11", "0000abcde00abcde");
-
- try_istri(wot,h,s, "1111111111abcde1", "00000000000abcde");
- try_istri(wot,h,s, "11111111111abcde", "00000000000abcde");
- try_istri(wot,h,s, "111111111111abcd", "00000000000abcde");
-
- try_istri(wot,h,s, "111abcde1abcde11", "00000000000abcde");
-
- try_istri(wot,h,s, "11abcde11abcde11", "00000000000abcde");
- try_istri(wot,h,s, "1abcde111abcde11", "00000000000abcde");
- try_istri(wot,h,s, "abcde1111abcde11", "00000000000abcde");
- try_istri(wot,h,s, "bcde11111abcde11", "00000000000abcde");
- try_istri(wot,h,s, "cde111111abcde11", "00000000000abcde");
-
- try_istri(wot,h,s, "01abcde11abcde11", "00000000000abcde");
- try_istri(wot,h,s, "00abcde11abcde11", "00000000000abcde");
- try_istri(wot,h,s, "000bcde11abcde11", "00000000000abcde");
-
- try_istri(wot,h,s, "00abcde10abcde11", "00000000000abcde");
- try_istri(wot,h,s, "00abcde100bcde11", "00000000000abcde");
-
- try_istri(wot,h,s, "1111111111111234", "0000000000000000");
- try_istri(wot,h,s, "1111111111111234", "0000000000000001");
- try_istri(wot,h,s, "1111111111111234", "0000000000000011");
-
- try_istri(wot,h,s, "1111111111111234", "1111111111111234");
- try_istri(wot,h,s, "a111111111111111", "000000000000000a");
- try_istri(wot,h,s, "b111111111111111", "000000000000000a");
-}
-
-
-//////////////////////////////////////////////////////////
-// //
-// ISTRI_08 //
-// //
-//////////////////////////////////////////////////////////
-
-UInt h_pcmpistri_08 ( V128* argL, V128* argR )
-{
- V128 block[2];
- memcpy(&block[0], argL, sizeof(V128));
- memcpy(&block[1], argR, sizeof(V128));
- ULong res, flags;
- __asm__ __volatile__(
- "subq $1024, %%rsp" "\n\t"
- "movdqu 0(%2), %%xmm2" "\n\t"
- "movdqu 16(%2), %%xmm11" "\n\t"
- "pcmpistri $0x08, %%xmm2, %%xmm11" "\n\t"
- "pushfq" "\n\t"
- "popq %%rdx" "\n\t"
- "movq %%rcx, %0" "\n\t"
- "movq %%rdx, %1" "\n\t"
- "addq $1024, %%rsp" "\n\t"
- : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
- : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
- );
- return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
-}
-
-UInt s_pcmpistri_08 ( V128* argLU, V128* argRU )
-{
- V128 resV;
- UInt resOSZACP, resECX;
- Bool ok
- = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
- zmask_from_V128(argLU),
- zmask_from_V128(argRU),
- 0x08, False/*!isSTRM*/
- );
- assert(ok);
- resECX = resV.uInt[0];
- return (resOSZACP << 16) | resECX;
-}
-
-void istri_08 ( void )
-{
- char* wot = "08";
- UInt(*h)(V128*,V128*) = h_pcmpistri_08;
- UInt(*s)(V128*,V128*) = s_pcmpistri_08;
-
- try_istri(wot,h,s, "0000000000000000", "0000000000000000");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa");
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa");
-
- try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa");
- try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa");
-
- try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa");
-
- try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
-}
-
-
-
-//////////////////////////////////////////////////////////
-// //
-// ISTRI_1A //
-// //
-//////////////////////////////////////////////////////////
-
-UInt h_pcmpistri_1A ( V128* argL, V128* argR )
-{
- V128 block[2];
- memcpy(&block[0], argL, sizeof(V128));
- memcpy(&block[1], argR, sizeof(V128));
- ULong res, flags;
- __asm__ __volatile__(
- "subq $1024, %%rsp" "\n\t"
- "movdqu 0(%2), %%xmm2" "\n\t"
- "movdqu 16(%2), %%xmm11" "\n\t"
- "pcmpistri $0x1A, %%xmm2, %%xmm11" "\n\t"
- "pushfq" "\n\t"
- "popq %%rdx" "\n\t"
- "movq %%rcx, %0" "\n\t"
- "movq %%rdx, %1" "\n\t"
- "addq $1024, %%rsp" "\n\t"
- : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
- : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
- );
- return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
-}
-
-UInt s_pcmpistri_1A ( V128* argLU, V128* argRU )
-{
- V128 resV;
- UInt resOSZACP, resECX;
- Bool ok
- = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
- zmask_from_V128(argLU),
- zmask_from_V128(argRU),
- 0x1A, False/*!isSTRM*/
- );
- assert(ok);
- resECX = resV.uInt[0];
- return (resOSZACP << 16) | resECX;
-}
-
-void istri_1A ( void )
-{
- char* wot = "1A";
- UInt(*h)(V128*,V128*) = h_pcmpistri_1A;
- UInt(*s)(V128*,V128*) = s_pcmpistri_1A;
-
- try_istri(wot,h,s, "0000000000000000", "0000000000000000");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
- try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa");
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa");
-
- try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa");
- try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa");
-
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa");
-
- try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa");
- try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa");
-
- try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
-}
-
-
-
-//////////////////////////////////////////////////////////
-// //
-// ISTRI_02 //
-// //
-//////////////////////////////////////////////////////////
-
-UInt h_pcmpistri_02 ( V128* argL, V128* argR )
-{
- V128 block[2];
- memcpy(&block[0], argL, sizeof(V128));
- memcpy(&block[1], argR, sizeof(V128));
- ULong res, flags;
- __asm__ __volatile__(
- "subq $1024, %%rsp" "\n\t"
- "movdqu 0(%2), %%xmm2" "\n\t"
- "movdqu 16(%2), %%xmm11" "\n\t"
- "pcmpistri $0x02, %%xmm2, %%xmm11" "\n\t"
-//"pcmpistrm $0x02, %%xmm2, %%xmm11" "\n\t"
-//"movd %%xmm0, %%ecx" "\n\t"
- "pushfq" "\n\t"
- "popq %%rdx" "\n\t"
- "movq %%rcx, %0" "\n\t"
- "movq %%rdx, %1" "\n\t"
- "addq $1024, %%rsp" "\n\t"
- : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
- : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
- );
- return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
-}
-
-UInt s_pcmpistri_02 ( V128* argLU, V128* argRU )
-{
- V128 resV;
- UInt resOSZACP, resECX;
- Bool ok
- = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
- zmask_from_V128(argLU),
- zmask_from_V128(argRU),
- 0x02, False/*!isSTRM*/
- );
- assert(ok);
- resECX = resV.uInt[0];
- return (resOSZACP << 16) | resECX;
-}
-
-void istri_02 ( void )
-{
- char* wot = "02";
- UInt(*h)(V128*,V128*) = h_pcmpistri_02;
- UInt(*s)(V128*,V128*) = s_pcmpistri_02;
-
- try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab");
- try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
-
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
- try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd");
- try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd");
- try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd");
- try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd");
-
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0");
-
- try_istri(wot,h,s, "0000000000000000", "0000000000000000");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
- try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
- try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb");
- try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba");
-
- try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0");
-
- try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
- try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
-}
-
-
-//////////////////////////////////////////////////////////
-// //
-// ISTRI_12 //
-// //
-//////////////////////////////////////////////////////////
-
-UInt h_pcmpistri_12 ( V128* argL, V128* argR )
-{
- V128 block[2];
- memcpy(&block[0], argL, sizeof(V128));
- memcpy(&block[1], argR, sizeof(V128));
- ULong res, flags;
- __asm__ __volatile__(
- "subq $1024, %%rsp" "\n\t"
- "movdqu 0(%2), %%xmm2" "\n\t"
- "movdqu 16(%2), %%xmm11" "\n\t"
- "pcmpistri $0x12, %%xmm2, %%xmm11" "\n\t"
-//"pcmpistrm $0x12, %%xmm2, %%xmm11" "\n\t"
-//"movd %%xmm0, %%ecx" "\n\t"
- "pushfq" "\n\t"
- "popq %%rdx" "\n\t"
- "movq %%rcx, %0" "\n\t"
- "movq %%rdx, %1" "\n\t"
- "addq $1024, %%rsp" "\n\t"
- : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
- : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
- );
- return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
-}
-
-UInt s_pcmpistri_12 ( V128* argLU, V128* argRU )
-{
- V128 resV;
- UInt resOSZACP, resECX;
- Bool ok
- = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
- zmask_from_V128(argLU),
- zmask_from_V128(argRU),
- 0x12, False/*!isSTRM*/
- );
- assert(ok);
- resECX = resV.uInt[0];
- return (resOSZACP << 16) | resECX;
-}
-
-void istri_12 ( void )
-{
- char* wot = "12";
- UInt(*h)(V128*,V128*) = h_pcmpistri_12;
- UInt(*s)(V128*,V128*) = s_pcmpistri_12;
-
- try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab");
- try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
-
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
- try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd");
- try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd");
- try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd");
- try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd");
-
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d");
- try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0");
-
- try_istri(wot,h,s, "0000000000000000", "0000000000000000");
- try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
-
- try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
- try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
- try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb");
- try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba");
-
- try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0");
-
- try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
- try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
-}
-
-
-
-//////////////////////////////////////////////////////////
-// //
-// ISTRI_44 //
-// //
-//////////////////////////////////////////////////////////
-
-UInt h_pcmpistri_44 ( V128* argL, V128* argR )
-{
- V128 block[2];
- memcpy(&block[0], argL, sizeof(V128));
- memcpy(&block[1], argR, sizeof(V128));
- ULong res, flags;
- __asm__ __volatile__(
- "subq $1024, %%rsp" "\n\t"
- "movdqu 0(%2), %%xmm2" "\n\t"
- "movdqu 16(%2), %%xmm11" "\n\t"
- "pcmpistri $0x44, %%xmm2, %%xmm11" "\n\t"
-//"pcmpistrm $0x04, %%xmm2, %%xmm11" "\n\t"
-//"movd %%xmm0, %%ecx" "\n\t"
- "pushfq" "\n\t"
- "popq %%rdx" "\n\t"
- "movq %%rcx, %0" "\n\t"
- "movq %%rdx, %1" "\n\t"
- "addq $1024, %%rsp" "\n\t"
- : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
- : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
- );
- return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
-}
-
-UInt s_pcmpistri_44 ( V128* argLU, V128* argRU )
-{
- V128 resV;
- UInt resOSZACP, resECX;
- Bool ok
- = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
- zmask_from_V128(argLU),
- zmask_from_V128(argRU),
- 0x44, False/*!isSTRM*/
- );
- assert(ok);
- resECX = resV.uInt[0];
- return (resOSZACP << 16) | resECX;
-}
-
-void istri_44 ( void )
-{
- char* wot = "44";
- UInt(*h)(V128*,V128*) = h_pcmpistri_44;
- UInt(*s)(V128*,V128*) = s_pcmpistri_44;
-
- try_istri(wot,h,s, "aaaabbbbccccdddd", "00000000000000bc");
- try_istri(wot,h,s, "aaaabbbbccccdddd", "00000000000000cb");
- try_istri(wot,h,s, "baaabbbbccccdddd", "00000000000000cb");
- try_istri(wot,h,s, "baaabbbbccccdddc", "00000000000000cb");
-
- try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "00000000000000cb");
- try_istri(wot,h,s, "bbbbbbbb0bbbbbbb", "00000000000000cb");
- try_istri(wot,h,s, "bbbbbbbbbbbbbb0b", "00000000000000cb");
- try_istri(wot,h,s, "bbbbbbbbbbbbbbb0", "00000000000000cb");
- try_istri(wot,h,s, "0000000000000000", "00000000000000cb");
-
- try_istri(wot,h,s, "0000000000000000", "0000000000000000");
-
- try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "00000000000000cb");
- try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "000000000000000b");
- try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000062cb");
-
- try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000002cb");
- try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000000cb");
- try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "000000000000000b");
-
- try_istri(wot,h,s, "0123456789abcdef", "000000fecb975421");
- try_istri(wot,h,s, "123456789abcdef1", "000000fecb975421");
-
- try_istri(wot,h,s, "0123456789abcdef", "00000000dca86532");
- try_istri(wot,h,s, "123456789abcdef1", "00000000dca86532");
-}
-
-
-
-
-
-//////////////////////////////////////////////////////////
-// //
-// main //
-// //
-//////////////////////////////////////////////////////////
-
-int main ( void )
-{
- istri_4A();
- istri_3A();
- istri_08();
- istri_1A();
- istri_02();
- istri_0C();
- istri_12();
- istri_44();
istri_00();
istri_38();
return 0;
diff --git a/main/memcheck/tests/amd64/int3-amd64.stderr.exp b/main/none/tests/amd64/pcmpstr64.stderr.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stderr.exp
copy to main/none/tests/amd64/pcmpstr64.stderr.exp
diff --git a/main/none/tests/amd64/pcmpstr64.stdout.exp b/main/none/tests/amd64/pcmpstr64.stdout.exp
index eaf6531..c94e0a4 100644
--- a/main/none/tests/amd64/pcmpstr64.stdout.exp
+++ b/main/none/tests/amd64/pcmpstr64.stdout.exp
@@ -162,6 +162,10 @@
istri 0C 1111111111111234 1111111111111234 -> 08010000 08010000
istri 0C a111111111111111 000000000000000a -> 0081000f 0081000f
istri 0C b111111111111111 000000000000000a -> 00800010 00800010
+istri 0C b111111111111111 0000000000000000 -> 08810000 08810000
+istri 0C 0000000000000000 0000000000000000 -> 08c10000 08c10000
+istri 0C 123456789abcdef1 0000000000000000 -> 08810000 08810000
+istri 0C 0000000000000000 123456789abcdef1 -> 00400010 00400010
istri 12 abcdacbdabcdabcd 000000000000000a -> 08810000 08810000
istri 12 abcdabcdabcdabcd 000000000000000b -> 08810000 08810000
istri 12 abcdabcdabcdabcd 00000000000000ab -> 08810000 08810000
diff --git a/main/none/tests/amd64/pcmpstr64w.c b/main/none/tests/amd64/pcmpstr64w.c
new file mode 100644
index 0000000..7c08b25
--- /dev/null
+++ b/main/none/tests/amd64/pcmpstr64w.c
@@ -0,0 +1,1274 @@
+
+/* Tests in detail the core arithmetic for pcmp{e,i}str{i,m} using
+ pcmpistri to drive it. Does not check the e-vs-i or i-vs-m
+ aspect. */
+
+#include <string.h>
+#include <stdio.h>
+#include <assert.h>
+
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef unsigned short UShort;
+typedef unsigned long long int ULong;
+typedef UChar Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+//typedef unsigned char V128[16];
+typedef
+ union {
+ UChar uChar[16];
+ UShort uShort[8];
+ UInt uInt[4];
+ UInt w32[4];
+ }
+ V128;
+
+#define SHIFT_O 11
+#define SHIFT_S 7
+#define SHIFT_Z 6
+#define SHIFT_A 4
+#define SHIFT_C 0
+#define SHIFT_P 2
+
+#define MASK_O (1ULL << SHIFT_O)
+#define MASK_S (1ULL << SHIFT_S)
+#define MASK_Z (1ULL << SHIFT_Z)
+#define MASK_A (1ULL << SHIFT_A)
+#define MASK_C (1ULL << SHIFT_C)
+#define MASK_P (1ULL << SHIFT_P)
+
+
+UInt clz32 ( UInt x )
+{
+ Int y, m, n;
+ y = -(x >> 16);
+ m = (y >> 16) & 16;
+ n = 16 - m;
+ x = x >> m;
+ y = x - 0x100;
+ m = (y >> 16) & 8;
+ n = n + m;
+ x = x << m;
+ y = x - 0x1000;
+ m = (y >> 16) & 4;
+ n = n + m;
+ x = x << m;
+ y = x - 0x4000;
+ m = (y >> 16) & 2;
+ n = n + m;
+ x = x << m;
+ y = x >> 14;
+ m = y & ~(y >> 1);
+ return n + 2 - m;
+}
+
+UInt ctz32 ( UInt x )
+{
+ return 32 - clz32((~x) & (x-1));
+}
+
+void expand ( V128* dst, char* summary )
+{
+ Int i;
+ assert( strlen(summary) == 16 );
+ for (i = 0; i < 16; i++) {
+ UChar xx = 0;
+ UChar x = summary[15-i];
+ if (x >= '0' && x <= '9') { xx = x - '0'; }
+ else if (x >= 'A' && x <= 'F') { xx = x - 'A' + 10; }
+ else if (x >= 'a' && x <= 'f') { xx = x - 'a' + 10; }
+ else assert(0);
+
+ assert(xx < 16);
+ xx = (xx << 4) | xx;
+ assert(xx < 256);
+ dst->uChar[i] = xx;
+ }
+}
+
+void try_istri ( char* which,
+ UInt(*h_fn)(V128*,V128*),
+ UInt(*s_fn)(V128*,V128*),
+ char* summL, char* summR )
+{
+ assert(strlen(which) == 2);
+ V128 argL, argR;
+ expand(&argL, summL);
+ expand(&argR, summR);
+ UInt h_res = h_fn(&argL, &argR);
+ UInt s_res = s_fn(&argL, &argR);
+ printf("istri %s %s %s -> %08x %08x %s\n",
+ which, summL, summR, h_res, s_res, h_res == s_res ? "" : "!!!!");
+}
+
+UInt zmask_from_V128 ( V128* arg )
+{
+ UInt i, res = 0;
+ for (i = 0; i < 8; i++) {
+ res |= ((arg->uShort[i] == 0) ? 1 : 0) << i;
+ }
+ return res;
+}
+
+//////////////////////////////////////////////////////////
+// //
+// GENERAL //
+// //
+//////////////////////////////////////////////////////////
+
+
+/* Given partial results from a 16-bit pcmpXstrX operation (intRes1,
+ basically), generate an I- or M-format output value, also the new
+ OSZACP flags. */
+static
+void PCMPxSTRx_WRK_gen_output_fmt_I_wide ( /*OUT*/V128* resV,
+ /*OUT*/UInt* resOSZACP,
+ UInt intRes1,
+ UInt zmaskL, UInt zmaskR,
+ UInt validL,
+ UInt pol, UInt idx )
+{
+ assert((pol >> 2) == 0);
+ assert((idx >> 1) == 0);
+
+ UInt intRes2 = 0;
+ switch (pol) {
+ case 0: intRes2 = intRes1; break; // pol +
+ case 1: intRes2 = ~intRes1; break; // pol -
+ case 2: intRes2 = intRes1; break; // pol m+
+ case 3: intRes2 = intRes1 ^ validL; break; // pol m-
+ }
+ intRes2 &= 0xFF;
+
+ // generate I-format output (an index in ECX)
+ // generate ecx value
+ UInt newECX = 0;
+ if (idx) {
+ // index of ms-1-bit
+ newECX = intRes2 == 0 ? 8 : (31 - clz32(intRes2));
+ } else {
+ // index of ls-1-bit
+ newECX = intRes2 == 0 ? 8 : ctz32(intRes2);
+ }
+
+ resV->w32[0] = newECX;
+ resV->w32[1] = 0;
+ resV->w32[2] = 0;
+ resV->w32[3] = 0;
+
+ // generate new flags, common to all ISTRI and ISTRM cases
+ *resOSZACP // A, P are zero
+ = ((intRes2 == 0) ? 0 : MASK_C) // C == 0 iff intRes2 == 0
+ | ((zmaskL == 0) ? 0 : MASK_Z) // Z == 1 iff any in argL is 0
+ | ((zmaskR == 0) ? 0 : MASK_S) // S == 1 iff any in argR is 0
+ | ((intRes2 & 1) << SHIFT_O); // O == IntRes2[0]
+}
+
+/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M}
+ variants on 16-bit characters.
+
+ For xSTRI variants, the new ECX value is placed in the 32 bits
+ pointed to by *resV, and the top 96 bits are zeroed. For xSTRM
+ variants, the result is a 128 bit value and is placed at *resV in
+ the obvious way.
+
+ For all variants, the new OSZACP value is placed at *resOSZACP.
+
+ argLV and argRV are the vector args. The caller must prepare a
+ 8-bit mask for each, zmaskL and zmaskR. For ISTRx variants this
+ must be 1 for each zero byte of of the respective arg. For ESTRx
+ variants this is derived from the explicit length indication, and
+ must be 0 in all places except at the bit index corresponding to
+ the valid length (0 .. 8). If the valid length is 8 then the
+ mask must be all zeroes. In all cases, bits 31:8 must be zero.
+
+ imm8 is the original immediate from the instruction. isSTRM
+ indicates whether this is a xSTRM or xSTRI variant, which controls
+ how much of *res is written.
+
+ If the given imm8 case can be handled, the return value is True.
+ If not, False is returned, and neither *res not *resOSZACP are
+ altered.
+*/
+
+Bool pcmpXstrX_WRK_wide ( /*OUT*/V128* resV,
+ /*OUT*/UInt* resOSZACP,
+ V128* argLV, V128* argRV,
+ UInt zmaskL, UInt zmaskR,
+ UInt imm8, Bool isxSTRM )
+{
+ assert(imm8 < 0x80);
+ assert((zmaskL >> 8) == 0);
+ assert((zmaskR >> 8) == 0);
+
+ /* Explicitly reject any imm8 values that haven't been validated,
+ even if they would probably work. Life is too short to have
+ unvalidated cases in the code base. */
+ switch (imm8) {
+ case 0x01:
+ case 0x03: case 0x09: case 0x0B: case 0x0D: case 0x13:
+ case 0x1B: case 0x39: case 0x3B: case 0x45: case 0x4B:
+ break;
+ default:
+ return False;
+ }
+
+ UInt fmt = (imm8 >> 0) & 3; // imm8[1:0] data format
+ UInt agg = (imm8 >> 2) & 3; // imm8[3:2] aggregation fn
+ UInt pol = (imm8 >> 4) & 3; // imm8[5:4] polarity
+ UInt idx = (imm8 >> 6) & 1; // imm8[6] 1==msb/bytemask
+
+ /*----------------------------------------*/
+ /*-- strcmp on wide data --*/
+ /*----------------------------------------*/
+
+ if (agg == 2/*equal each, aka strcmp*/
+ && (fmt == 1/*uw*/ || fmt == 3/*sw*/)) {
+ Int i;
+ UShort* argL = (UShort*)argLV;
+ UShort* argR = (UShort*)argRV;
+ UInt boolResII = 0;
+ for (i = 7; i >= 0; i--) {
+ UShort cL = argL[i];
+ UShort cR = argR[i];
+ boolResII = (boolResII << 1) | (cL == cR ? 1 : 0);
+ }
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+
+ // do invalidation, common to all equal-each cases
+ UInt intRes1
+ = (boolResII & validL & validR) // if both valid, use cmpres
+ | (~ (validL | validR)); // if both invalid, force 1
+ // else force 0
+ intRes1 &= 0xFF;
+
+ // generate I-format output
+ PCMPxSTRx_WRK_gen_output_fmt_I_wide(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx
+ );
+
+ return True;
+ }
+
+ /*----------------------------------------*/
+ /*-- set membership on wide data --*/
+ /*----------------------------------------*/
+
+ if (agg == 0/*equal any, aka find chars in a set*/
+ && (fmt == 1/*uw*/ || fmt == 3/*sw*/)) {
+ /* argL: the string, argR: charset */
+ UInt si, ci;
+ UShort* argL = (UShort*)argLV;
+ UShort* argR = (UShort*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+
+ for (si = 0; si < 8; si++) {
+ if ((validL & (1 << si)) == 0)
+ // run off the end of the string.
+ break;
+ UInt m = 0;
+ for (ci = 0; ci < 8; ci++) {
+ if ((validR & (1 << ci)) == 0) break;
+ if (argR[ci] == argL[si]) { m = 1; break; }
+ }
+ boolRes |= (m << si);
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFF;
+
+ // generate I-format output
+ PCMPxSTRx_WRK_gen_output_fmt_I_wide(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx
+ );
+
+ return True;
+ }
+
+ /*----------------------------------------*/
+ /*-- substring search on wide data --*/
+ /*----------------------------------------*/
+
+ if (agg == 3/*equal ordered, aka substring search*/
+ && (fmt == 1/*uw*/ || fmt == 3/*sw*/)) {
+
+ /* argL: haystack, argR: needle */
+ UInt ni, hi;
+ UShort* argL = (UShort*)argLV;
+ UShort* argR = (UShort*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+ for (hi = 0; hi < 8; hi++) {
+ UInt m = 1;
+ for (ni = 0; ni < 8; ni++) {
+ if ((validR & (1 << ni)) == 0) break;
+ UInt i = ni + hi;
+ if (i >= 8) break;
+ if (argL[i] != argR[ni]) { m = 0; break; }
+ }
+ boolRes |= (m << hi);
+ if ((validL & (1 << hi)) == 0)
+ // run off the end of the haystack
+ break;
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFF;
+
+ // generate I-format output
+ PCMPxSTRx_WRK_gen_output_fmt_I_wide(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx
+ );
+
+ return True;
+ }
+
+ /*----------------------------------------*/
+ /*-- ranges, unsigned wide data --*/
+ /*----------------------------------------*/
+
+ if (agg == 1/*ranges*/
+ && fmt == 1/*uw*/) {
+
+ /* argL: string, argR: range-pairs */
+ UInt ri, si;
+ UShort* argL = (UShort*)argLV;
+ UShort* argR = (UShort*)argRV;
+ UInt boolRes = 0;
+ UInt validL = ~(zmaskL | -zmaskL); // not(left(zmaskL))
+ UInt validR = ~(zmaskR | -zmaskR); // not(left(zmaskR))
+ for (si = 0; si < 8; si++) {
+ if ((validL & (1 << si)) == 0)
+ // run off the end of the string
+ break;
+ UInt m = 0;
+ for (ri = 0; ri < 8; ri += 2) {
+ if ((validR & (3 << ri)) != (3 << ri)) break;
+ if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) {
+ m = 1; break;
+ }
+ }
+ boolRes |= (m << si);
+ }
+
+ // boolRes is "pre-invalidated"
+ UInt intRes1 = boolRes & 0xFF;
+
+ // generate I-format output
+ PCMPxSTRx_WRK_gen_output_fmt_I_wide(
+ resV, resOSZACP,
+ intRes1, zmaskL, zmaskR, validL, pol, idx
+ );
+
+ return True;
+ }
+
+ return False;
+}
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_4B //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_4B ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x4B, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_4B ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x4B, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_4B ( void )
+{
+ char* wot = "4B";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_4B;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_4B;
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "8000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "0000000000000001", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
+}
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_3B //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_3B ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x3B, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_3B ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x3B, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_3B ( void )
+{
+ char* wot = "3B";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_3B;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_3B;
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "8000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "0000000000000001", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
+}
+
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_0D //
+// //
+//////////////////////////////////////////////////////////
+
+__attribute__((noinline))
+UInt h_pcmpistri_0D ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res = 0, flags = 0;
+ __asm__ __volatile__(
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x0D, %%xmm2, %%xmm11" "\n\t"
+ //"pcmpistrm $0x0D, %%xmm2, %%xmm11" "\n\t"
+ //"movd %%xmm0, %%ecx" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_0D ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x0D, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_0D ( void )
+{
+ char* wot = "0D";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_0D;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_0D;
+
+ try_istri(wot,h,s, "11111111abcdef11", "0000000000abcdef");
+
+ try_istri(wot,h,s, "11111111abcdef11", "00abcdef00abcdef");
+
+ try_istri(wot,h,s, "11111111abcdef11", "0000000000abcdef");
+ try_istri(wot,h,s, "1111111111abcdef", "0000000000abcdef");
+ try_istri(wot,h,s, "111111111111abcd", "0000000000abcdef");
+
+ try_istri(wot,h,s, "1111abcd11abcd11", "000000000000abcd");
+
+ try_istri(wot,h,s, "11abcd1111abcd11", "000000000000abcd");
+ try_istri(wot,h,s, "abcd111111abcd11", "000000000000abcd");
+ try_istri(wot,h,s, "cd11111111abcd11", "000000000000abcd");
+
+ try_istri(wot,h,s, "01abcd11abcd1111", "000000000000abcd");
+ try_istri(wot,h,s, "00abcd11abcd1111", "000000000000abcd");
+ try_istri(wot,h,s, "0000cd11abcd1111", "000000000000abcd");
+
+ try_istri(wot,h,s, "00abcd1100abcd11", "000000000000abcd");
+ try_istri(wot,h,s, "00abcd110000cd11", "000000000000abcd");
+
+ try_istri(wot,h,s, "1111111111111234", "0000000000000000");
+ try_istri(wot,h,s, "1111111111111234", "0000000000000011");
+ try_istri(wot,h,s, "1111111111111234", "0000000000001111");
+
+ try_istri(wot,h,s, "1111111111111234", "1111111111111234");
+ try_istri(wot,h,s, "0a11111111111111", "000000000000000a");
+ try_istri(wot,h,s, "0b11111111111111", "000000000000000a");
+
+ try_istri(wot,h,s, "b111111111111111", "0000000000000000");
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "123456789abcdef1", "0000000000000000");
+ try_istri(wot,h,s, "0000000000000000", "123456789abcdef1");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_09 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_09 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x09, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_09 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x09, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_09 ( void )
+{
+ char* wot = "09";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_09;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_09;
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "8000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "0000000000000001", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
+}
+
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_1B //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_1B ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x1B, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_1B ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x1B, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_1B ( void )
+{
+ char* wot = "1B";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_1B;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_1B;
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "8000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "0000000000000001", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
+}
+
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_03 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_03 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x03, %%xmm2, %%xmm11" "\n\t"
+//"pcmpistrm $0x03, %%xmm2, %%xmm11" "\n\t"
+//"movd %%xmm0, %%ecx" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_03 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x03, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_03 ( void )
+{
+ char* wot = "03";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_03;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_03;
+
+ try_istri(wot,h,s, "aacdacbdaacdaacd", "00000000000000aa");
+ try_istri(wot,h,s, "aabbaabbaabbaabb", "00000000000000bb");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "000000000000aabb");
+ try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
+
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "00bbccddaabbccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaa00ccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaabb00dd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaabbcc00", "00000000aabbccdd");
+
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aa00ccdd");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabb00dd");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabbcc00");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
+ try_istri(wot,h,s, "0000aabbaabbaabb", "000000000000bbbb");
+ try_istri(wot,h,s, "0000ccddaabbccdd", "00000000bbaabbaa");
+
+ try_istri(wot,h,s, "0000ccddaabbccdd", "000000bbaabbaa00");
+
+ try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
+ try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_13 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_13 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x13, %%xmm2, %%xmm11" "\n\t"
+//"pcmpistrm $0x13, %%xmm2, %%xmm11" "\n\t"
+//"movd %%xmm0, %%ecx" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_13 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x13, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_13 ( void )
+{
+ char* wot = "13";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_13;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_13;
+
+ try_istri(wot,h,s, "aacdacbdaacdaacd", "00000000000000aa");
+ try_istri(wot,h,s, "aabbaabbaabbaabb", "00000000000000bb");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "000000000000aabb");
+ try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
+
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "00bbccddaabbccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaa00ccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaabb00dd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaabbcc00", "00000000aabbccdd");
+
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aa00ccdd");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabb00dd");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabbcc00");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
+ try_istri(wot,h,s, "0000aabbaabbaabb", "000000000000bbbb");
+ try_istri(wot,h,s, "0000ccddaabbccdd", "00000000bbaabbaa");
+
+ try_istri(wot,h,s, "0000ccddaabbccdd", "000000bbaabbaa00");
+
+ try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
+ try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
+}
+
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_45 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_45 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x45, %%xmm2, %%xmm11" "\n\t"
+//"pcmpistrm $0x04, %%xmm2, %%xmm11" "\n\t"
+//"movd %%xmm0, %%ecx" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_45 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x45, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_45 ( void )
+{
+ char* wot = "45";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_45;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_45;
+
+ try_istri(wot,h,s, "aaaabbbbccccdddd", "000000000000bbcc");
+ try_istri(wot,h,s, "aaaabbbbccccdddd", "000000000000ccbb");
+ try_istri(wot,h,s, "baaabbbbccccdddd", "000000000000ccbb");
+ try_istri(wot,h,s, "baaabbbbccccdddc", "000000000000ccbb");
+
+ try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "000000000000ccbb");
+ try_istri(wot,h,s, "bbbbbbbb00bbbbbb", "000000000000ccbb");
+ try_istri(wot,h,s, "bbbbbbbbbbbb00bb", "000000000000ccbb");
+ try_istri(wot,h,s, "bbbbbbbbbbbbbb00", "000000000000ccbb");
+ try_istri(wot,h,s, "0000000000000000", "000000000000ccbb");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+
+ try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "000000000000ccbb");
+ try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "00000000000000bb");
+ try_istri(wot,h,s, "bb44bb44bb44bb44", "000000006622ccbb");
+
+ try_istri(wot,h,s, "bb44bb44bb44bb44", "000000000022ccbb");
+ try_istri(wot,h,s, "bb44bb44bb44bb44", "000000000000ccbb");
+ try_istri(wot,h,s, "bb44bb44bb44bb44", "00000000000000bb");
+
+ try_istri(wot,h,s, "0011223344556677", "0000997755442211");
+ try_istri(wot,h,s, "1122334455667711", "0000997755442211");
+
+ try_istri(wot,h,s, "0011223344556677", "0000aa8866553322");
+ try_istri(wot,h,s, "1122334455667711", "0000aa8866553322");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_01 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_01 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x01, %%xmm2, %%xmm11" "\n\t"
+//"pcmpistrm $0x01, %%xmm2, %%xmm11" "\n\t"
+//"movd %%xmm0, %%ecx" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_01 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x01, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_01 ( void )
+{
+ char* wot = "01";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_01;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_01;
+
+ try_istri(wot,h,s, "aacdacbdaacdaacd", "00000000000000aa");
+ try_istri(wot,h,s, "aabbaabbaabbaabb", "00000000000000bb");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "000000000000aabb");
+ try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
+
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "00bbccddaabbccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaa00ccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaabb00dd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaabbcc00", "00000000aabbccdd");
+
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabbccdd");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aa00ccdd");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabb00dd");
+ try_istri(wot,h,s, "aabbccddaabbccdd", "00000000aabbcc00");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
+ try_istri(wot,h,s, "0000aabbaabbaabb", "000000000000bbbb");
+ try_istri(wot,h,s, "0000ccddaabbccdd", "00000000bbaabbaa");
+
+ try_istri(wot,h,s, "0000ccddaabbccdd", "000000bbaabbaa00");
+
+ try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
+ try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_39 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_39 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x39, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_39 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x39, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_39 ( void )
+{
+ char* wot = "39";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_39;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_39;
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "8000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "0000000000000001", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
+}
+
+
+
+//////////////////////////////////////////////////////////
+// //
+// main //
+// //
+//////////////////////////////////////////////////////////
+
+int main ( void )
+{
+ istri_4B();
+ istri_3B();
+ istri_09();
+ istri_1B();
+ istri_03();
+ istri_0D();
+ istri_13();
+ istri_45();
+ istri_01();
+ istri_39();
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/amd64/pcmpstr64w.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/amd64/pcmpstr64w.stderr.exp
diff --git a/main/none/tests/amd64/pcmpstr64w.stdout.exp b/main/none/tests/amd64/pcmpstr64w.stdout.exp
new file mode 100644
index 0000000..77d555d
--- /dev/null
+++ b/main/none/tests/amd64/pcmpstr64w.stdout.exp
@@ -0,0 +1,260 @@
+istri 4B 0000000000000000 0000000000000000 -> 08c10007 08c10007
+istri 4B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010007 08010007
+istri 4B aaaa2aaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010007 08010007
+istri 4B aaaaaaaaa2aaaaaa aaaaaaaaaaaaaaaa -> 08010007 08010007
+istri 4B aaaaaaaaaaaaa2aa aaaaaaaaaaaaaaaa -> 08010007 08010007
+istri 4B aaaaaaaaaaaaaaaa aaaa2aaaaaaaaaaa -> 08010007 08010007
+istri 4B aaaaaaaaaaaaaaaa aaaaaaaaa2aaaaaa -> 08010007 08010007
+istri 4B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa2a -> 00010007 00010007
+istri 4B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010007 08010007
+istri 4B baaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010006 08010006
+istri 4B b9aaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010006 08010006
+istri 4B b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010005 08010005
+istri 4B b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010005 08010005
+istri 4B b9baaaaaaaaaaaaa aaaaaaaaaaaa7aaa -> 08010005 08010005
+istri 4B b9baaaaaaaaaaaaa aaaaaaaa2aaa4aaa -> 08010005 08010005
+istri 4B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010007 08010007
+istri 4B aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 08410000 08410000
+istri 4B aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 08810000 08810000
+istri 4B aaaaaaaaaaaa00aa aaaaaaaaaaaa00aa -> 08c10007 08c10007
+istri 4B aaaaaaaa00aaaaaa aaaaaaaaaaaaaaaa -> 08410002 08410002
+istri 4B aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 08810000 08810000
+istri 4B aaaaaaaa00aaaaaa aaaaaaaaaaaa00aa -> 08c10007 08c10007
+istri 4B aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 08410000 08410000
+istri 4B aaaaaaaaaaaaaaaa aaaaaaaa00aaaaaa -> 08810002 08810002
+istri 4B aaaaaaaaaaaa00aa aaaaaaaa00aaaaaa -> 08c10007 08c10007
+istri 4B 0000000000000000 aaaaaaaa00aaaaaa -> 00c10007 00c10007
+istri 4B 8000000000000000 aaaaaaaa00aaaaaa -> 00c10007 00c10007
+istri 4B 0000000000000001 aaaaaaaa00aaaaaa -> 00c10007 00c10007
+istri 4B 0000000000000000 aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 4B aaaaaaaaaaaaaaaa 0000000000000000 -> 00800008 00800008
+istri 3B 0000000000000000 0000000000000000 -> 08c10000 08c10000
+istri 3B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 3B aaaa2aaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010005 00010005
+istri 3B aaaaaaaaa2aaaaaa aaaaaaaaaaaaaaaa -> 00010003 00010003
+istri 3B aaaaaaaaaaaaa2aa aaaaaaaaaaaaaaaa -> 00010001 00010001
+istri 3B aaaaaaaaaaaaaaaa aaaa2aaaaaaaaaaa -> 00010005 00010005
+istri 3B aaaaaaaaaaaaaaaa aaaaaaaaa2aaaaaa -> 00010003 00010003
+istri 3B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa2a -> 08010000 08010000
+istri 3B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 3B baaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 3B b9aaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 3B b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 3B b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 3B b9baaaaaaaaaaaaa aaaaaaaaaaaa7aaa -> 00010001 00010001
+istri 3B b9baaaaaaaaaaaaa aaaaaaaa2aaa4aaa -> 00010001 00010001
+istri 3B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 3B aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 3B aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 3B aaaaaaaaaaaa00aa aaaaaaaaaaaa00aa -> 00c10001 00c10001
+istri 3B aaaaaaaa00aaaaaa aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 3B aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 3B aaaaaaaa00aaaaaa aaaaaaaaaaaa00aa -> 00c10001 00c10001
+istri 3B aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 3B aaaaaaaaaaaaaaaa aaaaaaaa00aaaaaa -> 00810003 00810003
+istri 3B aaaaaaaaaaaa00aa aaaaaaaa00aaaaaa -> 00c10003 00c10003
+istri 3B 0000000000000000 aaaaaaaa00aaaaaa -> 00c10003 00c10003
+istri 3B 8000000000000000 aaaaaaaa00aaaaaa -> 00c10003 00c10003
+istri 3B 0000000000000001 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 3B 0000000000000000 aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 3B aaaaaaaaaaaaaaaa 0000000000000000 -> 08810000 08810000
+istri 09 0000000000000000 0000000000000000 -> 08c10000 08c10000
+istri 09 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 aaaa2aaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 aaaaaaaaa2aaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 aaaaaaaaaaaaa2aa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 aaaaaaaaaaaaaaaa aaaa2aaaaaaaaaaa -> 08010000 08010000
+istri 09 aaaaaaaaaaaaaaaa aaaaaaaaa2aaaaaa -> 08010000 08010000
+istri 09 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa2a -> 00010001 00010001
+istri 09 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 baaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 b9aaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 b9baaaaaaaaaaaaa aaaaaaaaaaaa7aaa -> 08010000 08010000
+istri 09 b9baaaaaaaaaaaaa aaaaaaaa2aaa4aaa -> 08010000 08010000
+istri 09 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 09 aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 08410000 08410000
+istri 09 aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 08810000 08810000
+istri 09 aaaaaaaaaaaa00aa aaaaaaaaaaaa00aa -> 08c10000 08c10000
+istri 09 aaaaaaaa00aaaaaa aaaaaaaaaaaaaaaa -> 08410000 08410000
+istri 09 aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 08810000 08810000
+istri 09 aaaaaaaa00aaaaaa aaaaaaaaaaaa00aa -> 08c10000 08c10000
+istri 09 aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 08410000 08410000
+istri 09 aaaaaaaaaaaaaaaa aaaaaaaa00aaaaaa -> 08810000 08810000
+istri 09 aaaaaaaaaaaa00aa aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 09 0000000000000000 aaaaaaaa00aaaaaa -> 00c10003 00c10003
+istri 09 8000000000000000 aaaaaaaa00aaaaaa -> 00c10003 00c10003
+istri 09 0000000000000001 aaaaaaaa00aaaaaa -> 00c10003 00c10003
+istri 09 0000000000000000 aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 09 aaaaaaaaaaaaaaaa 0000000000000000 -> 00800008 00800008
+istri 1B 0000000000000000 0000000000000000 -> 00c00008 00c00008
+istri 1B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 1B aaaa2aaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010005 00010005
+istri 1B aaaaaaaaa2aaaaaa aaaaaaaaaaaaaaaa -> 00010003 00010003
+istri 1B aaaaaaaaaaaaa2aa aaaaaaaaaaaaaaaa -> 00010001 00010001
+istri 1B aaaaaaaaaaaaaaaa aaaa2aaaaaaaaaaa -> 00010005 00010005
+istri 1B aaaaaaaaaaaaaaaa aaaaaaaaa2aaaaaa -> 00010003 00010003
+istri 1B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa2a -> 08010000 08010000
+istri 1B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 1B baaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 1B b9aaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 1B b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 1B b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 1B b9baaaaaaaaaaaaa aaaaaaaaaaaa7aaa -> 00010001 00010001
+istri 1B b9baaaaaaaaaaaaa aaaaaaaa2aaa4aaa -> 00010001 00010001
+istri 1B aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 1B aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00410001 00410001
+istri 1B aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 1B aaaaaaaaaaaa00aa aaaaaaaaaaaa00aa -> 00c00008 00c00008
+istri 1B aaaaaaaa00aaaaaa aaaaaaaaaaaaaaaa -> 00410003 00410003
+istri 1B aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 1B aaaaaaaa00aaaaaa aaaaaaaaaaaa00aa -> 00c10001 00c10001
+istri 1B aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00410001 00410001
+istri 1B aaaaaaaaaaaaaaaa aaaaaaaa00aaaaaa -> 00810003 00810003
+istri 1B aaaaaaaaaaaa00aa aaaaaaaa00aaaaaa -> 00c10001 00c10001
+istri 1B 0000000000000000 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 1B 8000000000000000 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 1B 0000000000000001 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 1B 0000000000000000 aaaaaaaaaaaaaaaa -> 08410000 08410000
+istri 1B aaaaaaaaaaaaaaaa 0000000000000000 -> 08810000 08810000
+istri 03 aacdacbdaacdaacd 00000000000000aa -> 00810001 00810001
+istri 03 aabbaabbaabbaabb 00000000000000bb -> 08810000 08810000
+istri 03 aabbccddaabbccdd 000000000000aabb -> 00810002 00810002
+istri 03 abcdabc0abcdabcd 000000000000abcd -> 08810000 08810000
+istri 03 aabbccddaabbccdd 00000000aabbccdd -> 08810000 08810000
+istri 03 00bbccddaabbccdd 00000000aabbccdd -> 08c10000 08c10000
+istri 03 aabbccddaa00ccdd 00000000aabbccdd -> 08c10000 08c10000
+istri 03 aabbccddaabb00dd 00000000aabbccdd -> 08c10000 08c10000
+istri 03 aabbccddaabbcc00 00000000aabbccdd -> 00c00008 00c00008
+istri 03 aabbccddaabbccdd 00000000aabbccdd -> 08810000 08810000
+istri 03 aabbccddaabbccdd 00000000aa00ccdd -> 08810000 08810000
+istri 03 aabbccddaabbccdd 00000000aabb00dd -> 08810000 08810000
+istri 03 aabbccddaabbccdd 00000000aabbcc00 -> 00800008 00800008
+istri 03 0000000000000000 0000000000000000 -> 00c00008 00c00008
+istri 03 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 03 0000abcdabcdabcd 000000000000abcd -> 08c10000 08c10000
+istri 03 0000abcdabcdabcd 000000000000dcba -> 00c00008 00c00008
+istri 03 0000aabbaabbaabb 000000000000bbbb -> 08c10000 08c10000
+istri 03 0000ccddaabbccdd 00000000bbaabbaa -> 00c10002 00c10002
+istri 03 0000ccddaabbccdd 000000bbaabbaa00 -> 00c00008 00c00008
+istri 03 0ddc0ffeebadf00d 00000000cafebabe -> 00810004 00810004
+istri 03 0ddc0ffeebadfeed 00000000cafebabe -> 00810001 00810001
+istri 0D 11111111abcdef11 0000000000abcdef -> 00810001 00810001
+istri 0D 11111111abcdef11 00abcdef00abcdef -> 00810001 00810001
+istri 0D 11111111abcdef11 0000000000abcdef -> 00810001 00810001
+istri 0D 1111111111abcdef 0000000000abcdef -> 08810000 08810000
+istri 0D 111111111111abcd 0000000000abcdef -> 00800008 00800008
+istri 0D 1111abcd11abcd11 000000000000abcd -> 00810001 00810001
+istri 0D 11abcd1111abcd11 000000000000abcd -> 00810001 00810001
+istri 0D abcd111111abcd11 000000000000abcd -> 00810001 00810001
+istri 0D cd11111111abcd11 000000000000abcd -> 00810001 00810001
+istri 0D 01abcd11abcd1111 000000000000abcd -> 00810002 00810002
+istri 0D 00abcd11abcd1111 000000000000abcd -> 00c10002 00c10002
+istri 0D 0000cd11abcd1111 000000000000abcd -> 00c10002 00c10002
+istri 0D 00abcd1100abcd11 000000000000abcd -> 00c10001 00c10001
+istri 0D 00abcd110000cd11 000000000000abcd -> 00c00008 00c00008
+istri 0D 1111111111111234 0000000000000000 -> 08810000 08810000
+istri 0D 1111111111111234 0000000000000011 -> 00810002 00810002
+istri 0D 1111111111111234 0000000000001111 -> 00810002 00810002
+istri 0D 1111111111111234 1111111111111234 -> 08010000 08010000
+istri 0D 0a11111111111111 000000000000000a -> 00810007 00810007
+istri 0D 0b11111111111111 000000000000000a -> 00800008 00800008
+istri 0D b111111111111111 0000000000000000 -> 08810000 08810000
+istri 0D 0000000000000000 0000000000000000 -> 08c10000 08c10000
+istri 0D 123456789abcdef1 0000000000000000 -> 08810000 08810000
+istri 0D 0000000000000000 123456789abcdef1 -> 00400008 00400008
+istri 13 aacdacbdaacdaacd 00000000000000aa -> 08810000 08810000
+istri 13 aabbaabbaabbaabb 00000000000000bb -> 00810001 00810001
+istri 13 aabbccddaabbccdd 000000000000aabb -> 08810000 08810000
+istri 13 abcdabc0abcdabcd 000000000000abcd -> 00810004 00810004
+istri 13 aabbccddaabbccdd 00000000aabbccdd -> 00800008 00800008
+istri 13 00bbccddaabbccdd 00000000aabbccdd -> 00c10007 00c10007
+istri 13 aabbccddaa00ccdd 00000000aabbccdd -> 00c10002 00c10002
+istri 13 aabbccddaabb00dd 00000000aabbccdd -> 00c10001 00c10001
+istri 13 aabbccddaabbcc00 00000000aabbccdd -> 08c10000 08c10000
+istri 13 aabbccddaabbccdd 00000000aabbccdd -> 00800008 00800008
+istri 13 aabbccddaabbccdd 00000000aa00ccdd -> 00810002 00810002
+istri 13 aabbccddaabbccdd 00000000aabb00dd -> 00810001 00810001
+istri 13 aabbccddaabbccdd 00000000aabbcc00 -> 08810000 08810000
+istri 13 0000000000000000 0000000000000000 -> 08c10000 08c10000
+istri 13 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 13 0000abcdabcdabcd 000000000000abcd -> 00c10006 00c10006
+istri 13 0000abcdabcdabcd 000000000000dcba -> 08c10000 08c10000
+istri 13 0000aabbaabbaabb 000000000000bbbb -> 00c10001 00c10001
+istri 13 0000ccddaabbccdd 00000000bbaabbaa -> 08c10000 08c10000
+istri 13 0000ccddaabbccdd 000000bbaabbaa00 -> 08c10000 08c10000
+istri 13 0ddc0ffeebadf00d 00000000cafebabe -> 08810000 08810000
+istri 13 0ddc0ffeebadfeed 00000000cafebabe -> 08810000 08810000
+istri 45 aaaabbbbccccdddd 000000000000bbcc -> 00800008 00800008
+istri 45 aaaabbbbccccdddd 000000000000ccbb -> 00810005 00810005
+istri 45 baaabbbbccccdddd 000000000000ccbb -> 00810005 00810005
+istri 45 baaabbbbccccdddc 000000000000ccbb -> 00810005 00810005
+istri 45 bbbbbbbbbbbbbbbb 000000000000ccbb -> 08810007 08810007
+istri 45 bbbbbbbb00bbbbbb 000000000000ccbb -> 08c10002 08c10002
+istri 45 bbbbbbbbbbbb00bb 000000000000ccbb -> 08c10000 08c10000
+istri 45 bbbbbbbbbbbbbb00 000000000000ccbb -> 00c00008 00c00008
+istri 45 0000000000000000 000000000000ccbb -> 00c00008 00c00008
+istri 45 0000000000000000 0000000000000000 -> 00c00008 00c00008
+istri 45 bbbbbbbbbbbbbbbb 000000000000ccbb -> 08810007 08810007
+istri 45 bbbbbbbbbbbbbbbb 00000000000000bb -> 00800008 00800008
+istri 45 bb44bb44bb44bb44 000000006622ccbb -> 08810007 08810007
+istri 45 bb44bb44bb44bb44 000000000022ccbb -> 00810007 00810007
+istri 45 bb44bb44bb44bb44 000000000000ccbb -> 00810007 00810007
+istri 45 bb44bb44bb44bb44 00000000000000bb -> 00800008 00800008
+istri 45 0011223344556677 0000997755442211 -> 08c10006 08c10006
+istri 45 1122334455667711 0000997755442211 -> 08810007 08810007
+istri 45 0011223344556677 0000aa8866553322 -> 00c10005 00c10005
+istri 45 1122334455667711 0000aa8866553322 -> 00810006 00810006
+istri 01 aacdacbdaacdaacd 00000000000000aa -> 00810001 00810001
+istri 01 aabbaabbaabbaabb 00000000000000bb -> 08810000 08810000
+istri 01 aabbccddaabbccdd 000000000000aabb -> 00810002 00810002
+istri 01 abcdabc0abcdabcd 000000000000abcd -> 08810000 08810000
+istri 01 aabbccddaabbccdd 00000000aabbccdd -> 08810000 08810000
+istri 01 00bbccddaabbccdd 00000000aabbccdd -> 08c10000 08c10000
+istri 01 aabbccddaa00ccdd 00000000aabbccdd -> 08c10000 08c10000
+istri 01 aabbccddaabb00dd 00000000aabbccdd -> 08c10000 08c10000
+istri 01 aabbccddaabbcc00 00000000aabbccdd -> 00c00008 00c00008
+istri 01 aabbccddaabbccdd 00000000aabbccdd -> 08810000 08810000
+istri 01 aabbccddaabbccdd 00000000aa00ccdd -> 08810000 08810000
+istri 01 aabbccddaabbccdd 00000000aabb00dd -> 08810000 08810000
+istri 01 aabbccddaabbccdd 00000000aabbcc00 -> 00800008 00800008
+istri 01 0000000000000000 0000000000000000 -> 00c00008 00c00008
+istri 01 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 08010000 08010000
+istri 01 0000abcdabcdabcd 000000000000abcd -> 08c10000 08c10000
+istri 01 0000abcdabcdabcd 000000000000dcba -> 00c00008 00c00008
+istri 01 0000aabbaabbaabb 000000000000bbbb -> 08c10000 08c10000
+istri 01 0000ccddaabbccdd 00000000bbaabbaa -> 00c10002 00c10002
+istri 01 0000ccddaabbccdd 000000bbaabbaa00 -> 00c00008 00c00008
+istri 01 0ddc0ffeebadf00d 00000000cafebabe -> 00810004 00810004
+istri 01 0ddc0ffeebadfeed 00000000cafebabe -> 00810001 00810001
+istri 39 0000000000000000 0000000000000000 -> 08c10000 08c10000
+istri 39 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 39 aaaa2aaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010005 00010005
+istri 39 aaaaaaaaa2aaaaaa aaaaaaaaaaaaaaaa -> 00010003 00010003
+istri 39 aaaaaaaaaaaaa2aa aaaaaaaaaaaaaaaa -> 00010001 00010001
+istri 39 aaaaaaaaaaaaaaaa aaaa2aaaaaaaaaaa -> 00010005 00010005
+istri 39 aaaaaaaaaaaaaaaa aaaaaaaaa2aaaaaa -> 00010003 00010003
+istri 39 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa2a -> 08010000 08010000
+istri 39 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 39 baaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 39 b9aaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 39 b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 39 b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 39 b9baaaaaaaaaaaaa aaaaaaaaaaaa7aaa -> 00010001 00010001
+istri 39 b9baaaaaaaaaaaaa aaaaaaaa2aaa4aaa -> 00010001 00010001
+istri 39 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 39 aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 39 aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 39 aaaaaaaaaaaa00aa aaaaaaaaaaaa00aa -> 00c10001 00c10001
+istri 39 aaaaaaaa00aaaaaa aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 39 aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 39 aaaaaaaa00aaaaaa aaaaaaaaaaaa00aa -> 00c10001 00c10001
+istri 39 aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 39 aaaaaaaaaaaaaaaa aaaaaaaa00aaaaaa -> 00810003 00810003
+istri 39 aaaaaaaaaaaa00aa aaaaaaaa00aaaaaa -> 00c10003 00c10003
+istri 39 0000000000000000 aaaaaaaa00aaaaaa -> 00c10003 00c10003
+istri 39 8000000000000000 aaaaaaaa00aaaaaa -> 00c10003 00c10003
+istri 39 0000000000000001 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 39 0000000000000000 aaaaaaaaaaaaaaaa -> 00400008 00400008
+istri 39 aaaaaaaaaaaaaaaa 0000000000000000 -> 08810000 08810000
diff --git a/main/none/tests/amd64/pcmpstr64w.vgtest b/main/none/tests/amd64/pcmpstr64w.vgtest
new file mode 100644
index 0000000..d088a43
--- /dev/null
+++ b/main/none/tests/amd64/pcmpstr64w.vgtest
@@ -0,0 +1,3 @@
+prog: pcmpstr64w
+prereq: ../../../tests/x86_amd64_features amd64-sse42
+vgopts: -q
diff --git a/main/none/tests/amd64/pcmpxstrx64.c b/main/none/tests/amd64/pcmpxstrx64.c
index 80d28e8..6d67aa7 100644
--- a/main/none/tests/amd64/pcmpxstrx64.c
+++ b/main/none/tests/amd64/pcmpxstrx64.c
@@ -332,337 +332,3 @@
return 0;
}
-
-/* Tests e-vs-i or i-vs-m aspects for pcmp{e,i}str{i,m}. Does not
- check the core arithmetic in any detail. */
-
-#include <string.h>
-#include <stdio.h>
-#include <assert.h>
-
-typedef unsigned char V128[16];
-typedef unsigned int UInt;
-typedef signed int Int;
-typedef unsigned char UChar;
-typedef unsigned long long int ULong;
-typedef UChar Bool;
-#define False ((Bool)0)
-#define True ((Bool)1)
-
-void show_V128 ( V128* vec )
-{
- Int i;
- for (i = 15; i >= 0; i--)
- printf("%02x", (UInt)( (*vec)[i] ));
-}
-
-void expand ( V128* dst, char* summary )
-{
- Int i;
- assert( strlen(summary) == 16 );
- for (i = 0; i < 16; i++) {
- UChar xx = 0;
- UChar x = summary[15-i];
- if (x >= '0' && x <= '9') { xx = x - '0'; }
- else if (x >= 'A' && x <= 'F') { xx = x - 'A' + 10; }
- else if (x >= 'a' && x <= 'f') { xx = x - 'a' + 10; }
- else assert(0);
-
- assert(xx < 16);
- xx = (xx << 4) | xx;
- assert(xx < 256);
- (*dst)[i] = xx;
- }
-}
-
-void one_test ( char* summL, ULong rdxIN, char* summR, ULong raxIN )
-{
- V128 argL, argR;
- expand( &argL, summL );
- expand( &argR, summR );
- printf("\n");
- printf("rdx %016llx argL ", rdxIN);
- show_V128(&argL);
- printf(" rax %016llx argR ", raxIN);
- show_V128(&argR);
- printf("\n");
-
- ULong block[ 2/*in:argL*/ // 0 0
- + 2/*in:argR*/ // 2 16
- + 1/*in:rdx*/ // 4 32
- + 1/*in:rax*/ // 5 40
- + 2/*inout:xmm0*/ // 6 48
- + 1/*inout:rcx*/ // 8 64
- + 1/*out:rflags*/ ]; // 9 72
- assert(sizeof(block) == 80);
-
- UChar* blockC = (UChar*)&block[0];
-
- /* ---------------- ISTRI_4A ---------------- */
- memset(blockC, 0x55, 80);
- memcpy(blockC + 0, &argL, 16);
- memcpy(blockC + 16, &argR, 16);
- memcpy(blockC + 24, &rdxIN, 8);
- memcpy(blockC + 32, &raxIN, 8);
- memcpy(blockC + 40, &rdxIN, 8);
- __asm__ __volatile__(
- "movupd 0(%0), %%xmm2" "\n\t"
- "movupd 16(%0), %%xmm13" "\n\t"
- "movq 32(%0), %%rdx" "\n\t"
- "movq 40(%0), %%rax" "\n\t"
- "movupd 48(%0), %%xmm0" "\n\t"
- "movw 64(%0), %%rcx" "\n\t"
- "pcmpistri $0x4A, %%xmm2, %%xmm13" "\n\t"
- "movupd %%xmm0, 48(%0)" "\n\t"
- "movw %%rcx, 64(%0)" "\n\t"
- "pushfq" "\n\t"
- "popq %%r15" "\n\t"
- "movq %%r15, 72(%0)" "\n\t"
- : /*out*/
- : /*in*/"r"(blockC)
- : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
- );
- printf(" istri $0x4A: ");
- printf(" xmm0 ");
- show_V128( (V128*)(blockC+48) );
- printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
-
- /* ---------------- ISTRI_0A ---------------- */
- memset(blockC, 0x55, 80);
- memcpy(blockC + 0, &argL, 16);
- memcpy(blockC + 16, &argR, 16);
- memcpy(blockC + 24, &rdxIN, 8);
- memcpy(blockC + 32, &raxIN, 8);
- memcpy(blockC + 40, &rdxIN, 8);
- __asm__ __volatile__(
- "movupd 0(%0), %%xmm2" "\n\t"
- "movupd 16(%0), %%xmm13" "\n\t"
- "movq 32(%0), %%rdx" "\n\t"
- "movq 40(%0), %%rax" "\n\t"
- "movupd 48(%0), %%xmm0" "\n\t"
- "movw 64(%0), %%rcx" "\n\t"
- "pcmpistri $0x0A, %%xmm2, %%xmm13" "\n\t"
- "movupd %%xmm0, 48(%0)" "\n\t"
- "movw %%rcx, 64(%0)" "\n\t"
- "pushfq" "\n\t"
- "popq %%r15" "\n\t"
- "movq %%r15, 72(%0)" "\n\t"
- : /*out*/
- : /*in*/"r"(blockC)
- : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
- );
- printf(" istri $0x0A: ");
- printf(" xmm0 ");
- show_V128( (V128*)(blockC+48) );
- printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
-
- /* ---------------- ISTRM_4A ---------------- */
- memset(blockC, 0x55, 80);
- memcpy(blockC + 0, &argL, 16);
- memcpy(blockC + 16, &argR, 16);
- memcpy(blockC + 24, &rdxIN, 8);
- memcpy(blockC + 32, &raxIN, 8);
- memcpy(blockC + 40, &rdxIN, 8);
- __asm__ __volatile__(
- "movupd 0(%0), %%xmm2" "\n\t"
- "movupd 16(%0), %%xmm13" "\n\t"
- "movq 32(%0), %%rdx" "\n\t"
- "movq 40(%0), %%rax" "\n\t"
- "movupd 48(%0), %%xmm0" "\n\t"
- "movw 64(%0), %%rcx" "\n\t"
- "pcmpistrm $0x4A, %%xmm2, %%xmm13" "\n\t"
- "movupd %%xmm0, 48(%0)" "\n\t"
- "movw %%rcx, 64(%0)" "\n\t"
- "pushfq" "\n\t"
- "popq %%r15" "\n\t"
- "movq %%r15, 72(%0)" "\n\t"
- : /*out*/
- : /*in*/"r"(blockC)
- : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
- );
- printf(" istrm $0x4A: ");
- printf(" xmm0 ");
- show_V128( (V128*)(blockC+48) );
- printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
-
- /* ---------------- ISTRM_0A ---------------- */
- memset(blockC, 0x55, 80);
- memcpy(blockC + 0, &argL, 16);
- memcpy(blockC + 16, &argR, 16);
- memcpy(blockC + 24, &rdxIN, 8);
- memcpy(blockC + 32, &raxIN, 8);
- memcpy(blockC + 40, &rdxIN, 8);
- __asm__ __volatile__(
- "movupd 0(%0), %%xmm2" "\n\t"
- "movupd 16(%0), %%xmm13" "\n\t"
- "movq 32(%0), %%rdx" "\n\t"
- "movq 40(%0), %%rax" "\n\t"
- "movupd 48(%0), %%xmm0" "\n\t"
- "movw 64(%0), %%rcx" "\n\t"
- "pcmpistrm $0x0A, %%xmm2, %%xmm13" "\n\t"
- "movupd %%xmm0, 48(%0)" "\n\t"
- "movw %%rcx, 64(%0)" "\n\t"
- "pushfq" "\n\t"
- "popq %%r15" "\n\t"
- "movq %%r15, 72(%0)" "\n\t"
- : /*out*/
- : /*in*/"r"(blockC)
- : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
- );
- printf(" istrm $0x0A: ");
- printf(" xmm0 ");
- show_V128( (V128*)(blockC+48) );
- printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
-
- /* ---------------- ESTRI_4A ---------------- */
- memset(blockC, 0x55, 80);
- memcpy(blockC + 0, &argL, 16);
- memcpy(blockC + 16, &argR, 16);
- memcpy(blockC + 24, &rdxIN, 8);
- memcpy(blockC + 32, &raxIN, 8);
- memcpy(blockC + 40, &rdxIN, 8);
- __asm__ __volatile__(
- "movupd 0(%0), %%xmm2" "\n\t"
- "movupd 16(%0), %%xmm13" "\n\t"
- "movq 32(%0), %%rdx" "\n\t"
- "movq 40(%0), %%rax" "\n\t"
- "movupd 48(%0), %%xmm0" "\n\t"
- "movw 64(%0), %%rcx" "\n\t"
- "pcmpestri $0x4A, %%xmm2, %%xmm13" "\n\t"
- "movupd %%xmm0, 48(%0)" "\n\t"
- "movw %%rcx, 64(%0)" "\n\t"
- "pushfq" "\n\t"
- "popq %%r15" "\n\t"
- "movq %%r15, 72(%0)" "\n\t"
- : /*out*/
- : /*in*/"r"(blockC)
- : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
- );
- printf(" estri $0x4A: ");
- printf(" xmm0 ");
- show_V128( (V128*)(blockC+48) );
- printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
-
- /* ---------------- ESTRI_0A ---------------- */
- memset(blockC, 0x55, 80);
- memcpy(blockC + 0, &argL, 16);
- memcpy(blockC + 16, &argR, 16);
- memcpy(blockC + 24, &rdxIN, 8);
- memcpy(blockC + 32, &raxIN, 8);
- memcpy(blockC + 40, &rdxIN, 8);
- __asm__ __volatile__(
- "movupd 0(%0), %%xmm2" "\n\t"
- "movupd 16(%0), %%xmm13" "\n\t"
- "movq 32(%0), %%rdx" "\n\t"
- "movq 40(%0), %%rax" "\n\t"
- "movupd 48(%0), %%xmm0" "\n\t"
- "movw 64(%0), %%rcx" "\n\t"
- "pcmpestri $0x0A, %%xmm2, %%xmm13" "\n\t"
- "movupd %%xmm0, 48(%0)" "\n\t"
- "movw %%rcx, 64(%0)" "\n\t"
- "pushfq" "\n\t"
- "popq %%r15" "\n\t"
- "movq %%r15, 72(%0)" "\n\t"
- : /*out*/
- : /*in*/"r"(blockC)
- : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
- );
- printf(" estri $0x0A: ");
- printf(" xmm0 ");
- show_V128( (V128*)(blockC+48) );
- printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
-
- /* ---------------- ESTRM_4A ---------------- */
- memset(blockC, 0x55, 80);
- memcpy(blockC + 0, &argL, 16);
- memcpy(blockC + 16, &argR, 16);
- memcpy(blockC + 24, &rdxIN, 8);
- memcpy(blockC + 32, &raxIN, 8);
- memcpy(blockC + 40, &rdxIN, 8);
- __asm__ __volatile__(
- "movupd 0(%0), %%xmm2" "\n\t"
- "movupd 16(%0), %%xmm13" "\n\t"
- "movq 32(%0), %%rdx" "\n\t"
- "movq 40(%0), %%rax" "\n\t"
- "movupd 48(%0), %%xmm0" "\n\t"
- "movw 64(%0), %%rcx" "\n\t"
- "pcmpestrm $0x4A, %%xmm2, %%xmm13" "\n\t"
- "movupd %%xmm0, 48(%0)" "\n\t"
- "movw %%rcx, 64(%0)" "\n\t"
- "pushfq" "\n\t"
- "popq %%r15" "\n\t"
- "movq %%r15, 72(%0)" "\n\t"
- : /*out*/
- : /*in*/"r"(blockC)
- : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
- );
- printf(" estrm $0x4A: ");
- printf(" xmm0 ");
- show_V128( (V128*)(blockC+48) );
- printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
-
- /* ---------------- ESTRM_0A ---------------- */
- memset(blockC, 0x55, 80);
- memcpy(blockC + 0, &argL, 16);
- memcpy(blockC + 16, &argR, 16);
- memcpy(blockC + 24, &rdxIN, 8);
- memcpy(blockC + 32, &raxIN, 8);
- memcpy(blockC + 40, &rdxIN, 8);
- __asm__ __volatile__(
- "movupd 0(%0), %%xmm2" "\n\t"
- "movupd 16(%0), %%xmm13" "\n\t"
- "movq 32(%0), %%rdx" "\n\t"
- "movq 40(%0), %%rax" "\n\t"
- "movupd 48(%0), %%xmm0" "\n\t"
- "movw 64(%0), %%rcx" "\n\t"
- "pcmpestrm $0x0A, %%xmm2, %%xmm13" "\n\t"
- "movupd %%xmm0, 48(%0)" "\n\t"
- "movw %%rcx, 64(%0)" "\n\t"
- "pushfq" "\n\t"
- "popq %%r15" "\n\t"
- "movq %%r15, 72(%0)" "\n\t"
- : /*out*/
- : /*in*/"r"(blockC)
- : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
- );
- printf(" estrm $0x0A: ");
- printf(" xmm0 ");
- show_V128( (V128*)(blockC+48) );
- printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
-
-
-
-
-}
-
-int main ( void )
-{
- one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaa0aaaaaaa", 0 );
- one_test("0000000000000000", 0, "aaaaaaaa0aaaaaaa", 0 );
-
- one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaaaaaaaaaa", 0 );
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 0 );
- one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaaaaaaaaaa", 6 );
-
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 6 );
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 15 );
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 16 );
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 17 );
-
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -6 );
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -15 );
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -16 );
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -17 );
-
- one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 6 );
- one_test("aaaaaaaaaaaaaaaa", 15, "aaaaaaaaaaaaaaaa", 6 );
- one_test("aaaaaaaaaaaaaaaa", 16, "aaaaaaaaaaaaaaaa", 6 );
- one_test("aaaaaaaaaaaaaaaa", 17, "aaaaaaaaaaaaaaaa", 6 );
-
- one_test("aaaaaaaaaaaaaaaa", -5, "aaaaaaaaaaaaaaaa", 6 );
- one_test("aaaaaaaaaaaaaaaa", -15, "aaaaaaaaaaaaaaaa", 6 );
- one_test("aaaaaaaaaaaaaaaa", -16, "aaaaaaaaaaaaaaaa", 6 );
- one_test("aaaaaaaaaaaaaaaa", -17, "aaaaaaaaaaaaaaaa", 6 );
-
- return 0;
-}
diff --git a/main/memcheck/tests/amd64/int3-amd64.stderr.exp b/main/none/tests/amd64/pcmpxstrx64.stderr.exp
similarity index 100%
copy from main/memcheck/tests/amd64/int3-amd64.stderr.exp
copy to main/none/tests/amd64/pcmpxstrx64.stderr.exp
diff --git a/main/none/tests/amd64/pcmpxstrx64w.c b/main/none/tests/amd64/pcmpxstrx64w.c
new file mode 100644
index 0000000..f44b9e2
--- /dev/null
+++ b/main/none/tests/amd64/pcmpxstrx64w.c
@@ -0,0 +1,335 @@
+
+/* Tests e-vs-i or i-vs-m aspects for pcmp{e,i}str{i,m}. Does not
+ check the core arithmetic in any detail. This file checks the 16-bit
+ character versions (w is for wide) */
+
+#include <string.h>
+#include <stdio.h>
+#include <assert.h>
+
+typedef unsigned char V128[16];
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef unsigned long long int ULong;
+typedef UChar Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+void show_V128 ( V128* vec )
+{
+ Int i;
+ for (i = 15; i >= 0; i--)
+ printf("%02x", (UInt)( (*vec)[i] ));
+}
+
+void expand ( V128* dst, char* summary )
+{
+ Int i;
+ assert( strlen(summary) == 16 );
+ for (i = 0; i < 16; i++) {
+ UChar xx = 0;
+ UChar x = summary[15-i];
+ if (x >= '0' && x <= '9') { xx = x - '0'; }
+ else if (x >= 'A' && x <= 'F') { xx = x - 'A' + 10; }
+ else if (x >= 'a' && x <= 'f') { xx = x - 'a' + 10; }
+ else assert(0);
+
+ assert(xx < 16);
+ xx = (xx << 4) | xx;
+ assert(xx < 256);
+ (*dst)[i] = xx;
+ }
+}
+
+void one_test ( char* summL, ULong rdxIN, char* summR, ULong raxIN )
+{
+ V128 argL, argR;
+ expand( &argL, summL );
+ expand( &argR, summR );
+ printf("\n");
+ printf("rdx %016llx argL ", rdxIN);
+ show_V128(&argL);
+ printf(" rax %016llx argR ", raxIN);
+ show_V128(&argR);
+ printf("\n");
+
+ ULong block[ 2/*in:argL*/ // 0 0
+ + 2/*in:argR*/ // 2 16
+ + 1/*in:rdx*/ // 4 32
+ + 1/*in:rax*/ // 5 40
+ + 2/*inout:xmm0*/ // 6 48
+ + 1/*inout:rcx*/ // 8 64
+ + 1/*out:rflags*/ ]; // 9 72
+ assert(sizeof(block) == 80);
+
+ UChar* blockC = (UChar*)&block[0];
+
+ /* ---------------- ISTRI_4B ---------------- */
+ memset(blockC, 0x55, 80);
+ memcpy(blockC + 0, &argL, 16);
+ memcpy(blockC + 16, &argR, 16);
+ memcpy(blockC + 24, &rdxIN, 8);
+ memcpy(blockC + 32, &raxIN, 8);
+ memcpy(blockC + 40, &rdxIN, 8);
+ __asm__ __volatile__(
+ "movupd 0(%0), %%xmm2" "\n\t"
+ "movupd 16(%0), %%xmm13" "\n\t"
+ "movq 32(%0), %%rdx" "\n\t"
+ "movq 40(%0), %%rax" "\n\t"
+ "movupd 48(%0), %%xmm0" "\n\t"
+ "movw 64(%0), %%rcx" "\n\t"
+ "pcmpistri $0x4B, %%xmm2, %%xmm13" "\n\t"
+ "movupd %%xmm0, 48(%0)" "\n\t"
+ "movw %%rcx, 64(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r15" "\n\t"
+ "movq %%r15, 72(%0)" "\n\t"
+ : /*out*/
+ : /*in*/"r"(blockC)
+ : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+ );
+ printf(" istri $0x4B: ");
+ printf(" xmm0 ");
+ show_V128( (V128*)(blockC+48) );
+ printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
+
+ /* ---------------- ISTRI_0B ---------------- */
+ memset(blockC, 0x55, 80);
+ memcpy(blockC + 0, &argL, 16);
+ memcpy(blockC + 16, &argR, 16);
+ memcpy(blockC + 24, &rdxIN, 8);
+ memcpy(blockC + 32, &raxIN, 8);
+ memcpy(blockC + 40, &rdxIN, 8);
+ __asm__ __volatile__(
+ "movupd 0(%0), %%xmm2" "\n\t"
+ "movupd 16(%0), %%xmm13" "\n\t"
+ "movq 32(%0), %%rdx" "\n\t"
+ "movq 40(%0), %%rax" "\n\t"
+ "movupd 48(%0), %%xmm0" "\n\t"
+ "movw 64(%0), %%rcx" "\n\t"
+ "pcmpistri $0x0B, %%xmm2, %%xmm13" "\n\t"
+ "movupd %%xmm0, 48(%0)" "\n\t"
+ "movw %%rcx, 64(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r15" "\n\t"
+ "movq %%r15, 72(%0)" "\n\t"
+ : /*out*/
+ : /*in*/"r"(blockC)
+ : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+ );
+ printf(" istri $0x0B: ");
+ printf(" xmm0 ");
+ show_V128( (V128*)(blockC+48) );
+ printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
+
+ /* ---------------- ISTRM_4B ---------------- */
+ memset(blockC, 0x55, 80);
+ memcpy(blockC + 0, &argL, 16);
+ memcpy(blockC + 16, &argR, 16);
+ memcpy(blockC + 24, &rdxIN, 8);
+ memcpy(blockC + 32, &raxIN, 8);
+ memcpy(blockC + 40, &rdxIN, 8);
+ __asm__ __volatile__(
+ "movupd 0(%0), %%xmm2" "\n\t"
+ "movupd 16(%0), %%xmm13" "\n\t"
+ "movq 32(%0), %%rdx" "\n\t"
+ "movq 40(%0), %%rax" "\n\t"
+ "movupd 48(%0), %%xmm0" "\n\t"
+ "movw 64(%0), %%rcx" "\n\t"
+ "pcmpistrm $0x4B, %%xmm2, %%xmm13" "\n\t"
+ "movupd %%xmm0, 48(%0)" "\n\t"
+ "movw %%rcx, 64(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r15" "\n\t"
+ "movq %%r15, 72(%0)" "\n\t"
+ : /*out*/
+ : /*in*/"r"(blockC)
+ : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+ );
+ printf(" istrm $0x4B: ");
+ printf(" xmm0 ");
+ show_V128( (V128*)(blockC+48) );
+ printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
+
+ /* ---------------- ISTRM_0B ---------------- */
+ memset(blockC, 0x55, 80);
+ memcpy(blockC + 0, &argL, 16);
+ memcpy(blockC + 16, &argR, 16);
+ memcpy(blockC + 24, &rdxIN, 8);
+ memcpy(blockC + 32, &raxIN, 8);
+ memcpy(blockC + 40, &rdxIN, 8);
+ __asm__ __volatile__(
+ "movupd 0(%0), %%xmm2" "\n\t"
+ "movupd 16(%0), %%xmm13" "\n\t"
+ "movq 32(%0), %%rdx" "\n\t"
+ "movq 40(%0), %%rax" "\n\t"
+ "movupd 48(%0), %%xmm0" "\n\t"
+ "movw 64(%0), %%rcx" "\n\t"
+ "pcmpistrm $0x0B, %%xmm2, %%xmm13" "\n\t"
+ "movupd %%xmm0, 48(%0)" "\n\t"
+ "movw %%rcx, 64(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r15" "\n\t"
+ "movq %%r15, 72(%0)" "\n\t"
+ : /*out*/
+ : /*in*/"r"(blockC)
+ : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+ );
+ printf(" istrm $0x0B: ");
+ printf(" xmm0 ");
+ show_V128( (V128*)(blockC+48) );
+ printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
+
+ /* ---------------- ESTRI_4B ---------------- */
+ memset(blockC, 0x55, 80);
+ memcpy(blockC + 0, &argL, 16);
+ memcpy(blockC + 16, &argR, 16);
+ memcpy(blockC + 24, &rdxIN, 8);
+ memcpy(blockC + 32, &raxIN, 8);
+ memcpy(blockC + 40, &rdxIN, 8);
+ __asm__ __volatile__(
+ "movupd 0(%0), %%xmm2" "\n\t"
+ "movupd 16(%0), %%xmm13" "\n\t"
+ "movq 32(%0), %%rdx" "\n\t"
+ "movq 40(%0), %%rax" "\n\t"
+ "movupd 48(%0), %%xmm0" "\n\t"
+ "movw 64(%0), %%rcx" "\n\t"
+ "pcmpestri $0x4B, %%xmm2, %%xmm13" "\n\t"
+ "movupd %%xmm0, 48(%0)" "\n\t"
+ "movw %%rcx, 64(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r15" "\n\t"
+ "movq %%r15, 72(%0)" "\n\t"
+ : /*out*/
+ : /*in*/"r"(blockC)
+ : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+ );
+ printf(" estri $0x4B: ");
+ printf(" xmm0 ");
+ show_V128( (V128*)(blockC+48) );
+ printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
+
+ /* ---------------- ESTRI_0B ---------------- */
+ memset(blockC, 0x55, 80);
+ memcpy(blockC + 0, &argL, 16);
+ memcpy(blockC + 16, &argR, 16);
+ memcpy(blockC + 24, &rdxIN, 8);
+ memcpy(blockC + 32, &raxIN, 8);
+ memcpy(blockC + 40, &rdxIN, 8);
+ __asm__ __volatile__(
+ "movupd 0(%0), %%xmm2" "\n\t"
+ "movupd 16(%0), %%xmm13" "\n\t"
+ "movq 32(%0), %%rdx" "\n\t"
+ "movq 40(%0), %%rax" "\n\t"
+ "movupd 48(%0), %%xmm0" "\n\t"
+ "movw 64(%0), %%rcx" "\n\t"
+ "pcmpestri $0x0B, %%xmm2, %%xmm13" "\n\t"
+ "movupd %%xmm0, 48(%0)" "\n\t"
+ "movw %%rcx, 64(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r15" "\n\t"
+ "movq %%r15, 72(%0)" "\n\t"
+ : /*out*/
+ : /*in*/"r"(blockC)
+ : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+ );
+ printf(" estri $0x0B: ");
+ printf(" xmm0 ");
+ show_V128( (V128*)(blockC+48) );
+ printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
+
+ /* ---------------- ESTRM_4B ---------------- */
+ memset(blockC, 0x55, 80);
+ memcpy(blockC + 0, &argL, 16);
+ memcpy(blockC + 16, &argR, 16);
+ memcpy(blockC + 24, &rdxIN, 8);
+ memcpy(blockC + 32, &raxIN, 8);
+ memcpy(blockC + 40, &rdxIN, 8);
+ __asm__ __volatile__(
+ "movupd 0(%0), %%xmm2" "\n\t"
+ "movupd 16(%0), %%xmm13" "\n\t"
+ "movq 32(%0), %%rdx" "\n\t"
+ "movq 40(%0), %%rax" "\n\t"
+ "movupd 48(%0), %%xmm0" "\n\t"
+ "movw 64(%0), %%rcx" "\n\t"
+ "pcmpestrm $0x4B, %%xmm2, %%xmm13" "\n\t"
+ "movupd %%xmm0, 48(%0)" "\n\t"
+ "movw %%rcx, 64(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r15" "\n\t"
+ "movq %%r15, 72(%0)" "\n\t"
+ : /*out*/
+ : /*in*/"r"(blockC)
+ : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+ );
+ printf(" estrm $0x4B: ");
+ printf(" xmm0 ");
+ show_V128( (V128*)(blockC+48) );
+ printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
+
+ /* ---------------- ESTRM_0B ---------------- */
+ memset(blockC, 0x55, 80);
+ memcpy(blockC + 0, &argL, 16);
+ memcpy(blockC + 16, &argR, 16);
+ memcpy(blockC + 24, &rdxIN, 8);
+ memcpy(blockC + 32, &raxIN, 8);
+ memcpy(blockC + 40, &rdxIN, 8);
+ __asm__ __volatile__(
+ "movupd 0(%0), %%xmm2" "\n\t"
+ "movupd 16(%0), %%xmm13" "\n\t"
+ "movq 32(%0), %%rdx" "\n\t"
+ "movq 40(%0), %%rax" "\n\t"
+ "movupd 48(%0), %%xmm0" "\n\t"
+ "movw 64(%0), %%rcx" "\n\t"
+ "pcmpestrm $0x0B, %%xmm2, %%xmm13" "\n\t"
+ "movupd %%xmm0, 48(%0)" "\n\t"
+ "movw %%rcx, 64(%0)" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%r15" "\n\t"
+ "movq %%r15, 72(%0)" "\n\t"
+ : /*out*/
+ : /*in*/"r"(blockC)
+ : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+ );
+ printf(" estrm $0x0B: ");
+ printf(" xmm0 ");
+ show_V128( (V128*)(blockC+48) );
+ printf(" rcx %016llx flags %08llx\n", block[8], block[9] & 0x8D5);
+
+
+
+
+}
+
+int main ( void )
+{
+ one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaa00aaaaaa", 0 );
+ one_test("0000000000000000", 0, "aaaaaaaa00aaaaaa", 0 );
+
+ one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaaaaaaaaaa", 0 );
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 0 );
+ one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaaaaaaaaaa", 6 );
+
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 6 );
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 15 );
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 16 );
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 17 );
+
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -6 );
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -15 );
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -16 );
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -17 );
+
+ one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 6 );
+ one_test("aaaaaaaaaaaaaaaa", 15, "aaaaaaaaaaaaaaaa", 6 );
+ one_test("aaaaaaaaaaaaaaaa", 16, "aaaaaaaaaaaaaaaa", 6 );
+ one_test("aaaaaaaaaaaaaaaa", 17, "aaaaaaaaaaaaaaaa", 6 );
+
+ one_test("aaaaaaaaaaaaaaaa", -5, "aaaaaaaaaaaaaaaa", 6 );
+ one_test("aaaaaaaaaaaaaaaa", -15, "aaaaaaaaaaaaaaaa", 6 );
+ one_test("aaaaaaaaaaaaaaaa", -16, "aaaaaaaaaaaaaaaa", 6 );
+ one_test("aaaaaaaaaaaaaaaa", -17, "aaaaaaaaaaaaaaaa", 6 );
+
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/amd64/pcmpxstrx64w.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/amd64/pcmpxstrx64w.stderr.exp
diff --git a/main/none/tests/amd64/pcmpxstrx64w.stdout.exp b/main/none/tests/amd64/pcmpxstrx64w.stdout.exp
new file mode 100644
index 0000000..d19ebdd
--- /dev/null
+++ b/main/none/tests/amd64/pcmpxstrx64w.stdout.exp
@@ -0,0 +1,210 @@
+
+rdx 0000000000000000 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000000 argR aaaaaaaaaaaaaaaa0000aaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550002 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 00000000000000000000ffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 00000000000000000000000000000007 rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000008c1
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 000008c1
+ estrm $0x4B: xmm0 ffffffffffffffffffffffffffffffff rcx 5555555555555555 flags 000008c1
+ estrm $0x0B: xmm0 000000000000000000000000000000ff rcx 5555555555555555 flags 000008c1
+
+rdx 0000000000000000 argL 00000000000000000000000000000000 rax 0000000000000000 argR aaaaaaaaaaaaaaaa0000aaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000000c1
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 000000c1
+ istrm $0x4B: xmm0 ffffffffffffffffffff000000000000 rcx 5555555555555555 flags 000000c1
+ istrm $0x0B: xmm0 000000000000000000000000000000f8 rcx 5555555555555555 flags 000000c1
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000008c1
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 000008c1
+ estrm $0x4B: xmm0 ffffffffffffffffffffffffffffffff rcx 5555555555555555 flags 000008c1
+ estrm $0x0B: xmm0 000000000000000000000000000000ff rcx 5555555555555555 flags 000008c1
+
+rdx 0000000000000000 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000000 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000008c1
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 000008c1
+ estrm $0x4B: xmm0 ffffffffffffffffffffffffffffffff rcx 5555555555555555 flags 000008c1
+ estrm $0x0B: xmm0 000000000000000000000000000000ff rcx 5555555555555555 flags 000008c1
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000000 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000000c1
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550005 flags 000000c1
+ estrm $0x4B: xmm0 ffffffffffff00000000000000000000 rcx 5555555555555555 flags 000000c1
+ estrm $0x0B: xmm0 000000000000000000000000000000e0 rcx 5555555555555555 flags 000000c1
+
+rdx 0000000000000000 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000000c1
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550006 flags 000000c1
+ estrm $0x4B: xmm0 ffffffff000000000000000000000000 rcx 5555555555555555 flags 000000c1
+ estrm $0x0B: xmm0 000000000000000000000000000000c0 rcx 5555555555555555 flags 000000c1
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000008c1
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 000008c1
+ estrm $0x4B: xmm0 ffffffff00000000ffffffffffffffff rcx 5555555555555555 flags 000008c1
+ estrm $0x0B: xmm0 000000000000000000000000000000cf rcx 5555555555555555 flags 000008c1
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 000000000000000f argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000010 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000011 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax fffffffffffffffa argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000008c1
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 000008c1
+ estrm $0x4B: xmm0 ffffffff00000000ffffffffffffffff rcx 5555555555555555 flags 000008c1
+ estrm $0x0B: xmm0 000000000000000000000000000000cf rcx 5555555555555555 flags 000008c1
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax fffffffffffffff1 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax fffffffffffffff0 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax ffffffffffffffef argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+
+rdx 0000000000000005 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000008c1
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 000008c1
+ estrm $0x4B: xmm0 ffffffff00000000ffffffffffffffff rcx 5555555555555555 flags 000008c1
+ estrm $0x0B: xmm0 000000000000000000000000000000cf rcx 5555555555555555 flags 000008c1
+
+rdx 000000000000000f argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000841
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000841
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000841
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000841
+
+rdx 0000000000000010 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000841
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000841
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000841
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000841
+
+rdx 0000000000000011 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000881
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000881
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000881
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000881
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000841
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000841
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000841
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000841
+
+rdx fffffffffffffffb argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000801
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000801
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000801
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000801
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550007 flags 000008c1
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 000008c1
+ estrm $0x4B: xmm0 ffffffff00000000ffffffffffffffff rcx 5555555555555555 flags 000008c1
+ estrm $0x0B: xmm0 000000000000000000000000000000cf rcx 5555555555555555 flags 000008c1
+
+rdx fffffffffffffff1 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000801
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000801
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000801
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000801
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000841
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000841
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000841
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000841
+
+rdx fffffffffffffff0 argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000801
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000801
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000801
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000801
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000841
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000841
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000841
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000841
+
+rdx ffffffffffffffef argL aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa rax 0000000000000006 argR aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+ istri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000801
+ istri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000801
+ istrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000801
+ istrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000801
+ estri $0x4B: xmm0 55555555555555555555555555555555 rcx 5555555555550003 flags 00000841
+ estri $0x0B: xmm0 55555555555555555555555555555555 rcx 5555555555550000 flags 00000841
+ estrm $0x4B: xmm0 0000000000000000ffffffffffffffff rcx 5555555555555555 flags 00000841
+ estrm $0x0B: xmm0 0000000000000000000000000000000f rcx 5555555555555555 flags 00000841
diff --git a/main/none/tests/amd64/pcmpxstrx64w.vgtest b/main/none/tests/amd64/pcmpxstrx64w.vgtest
new file mode 100644
index 0000000..4b49c51
--- /dev/null
+++ b/main/none/tests/amd64/pcmpxstrx64w.vgtest
@@ -0,0 +1,3 @@
+prog: pcmpxstrx64w
+prereq: ../../../tests/x86_amd64_features amd64-sse42
+vgopts: -q
diff --git a/main/none/tests/amd64/sse4-64.c b/main/none/tests/amd64/sse4-64.c
index 1506743..de0431c 100644
--- a/main/none/tests/amd64/sse4-64.c
+++ b/main/none/tests/amd64/sse4-64.c
@@ -1268,7 +1268,7 @@
{
V128 src, dst;
Int i;
- for (i = 0; i < 10; i++) {
+ for (i = 0; i < 50; i++) {
randV128(&src);
randV128(&dst);
DO_imm_mandr_r("mpsadbw", 0, src, dst);
@@ -1745,11 +1745,14 @@
{
V128 src, dst;
Int i;
- for (i = 0; i < 10; i++) {
+ for (i = 0; i < 20; i++) {
randV128(&src);
randV128(&dst);
DO_mandr_r("phminposuw", src, dst);
}
+ memset(src, 0x55, sizeof(src));
+ memset(dst, 0xAA, sizeof(dst));
+ DO_mandr_r("phminposuw", src, dst);
}
void test_PMAXSB ( void )
@@ -3790,7 +3793,6 @@
test_EXTRACTPS();
test_INSERTPS(); // done Apr.01.2010
// MOVNTDQA ***
- //test_MPSADBW();
test_PCMPEQQ();
test_PEXTRB(); // done Apr.15.2010
test_PEXTRD(); // done Apr.14.2010
@@ -3800,7 +3802,6 @@
test_PINSRD(); // todo
test_PINSRW(); /* Umm, this is SSE2, not SSE4. Right? */
test_PINSRB(); // todo
- //test_PHMINPOSUW();
test_PMAXSB();
test_PMAXSD(); // done Apr.09.2010
test_PMAXUD(); // done Apr.16.2010
@@ -3839,14 +3840,10 @@
test_PCMPGTQ();
// CRC32B,Q
test_PACKUSDW();
-
-#else
-#if 0
- test_MPSADBW();
- test_PCMPEQQ();
test_PHMINPOSUW();
- test_PMULDQ();
-#endif
+ test_MPSADBW();
+#else
+ test_MPSADBW();
#endif
return 0;
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/amd64/sse4-64.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/amd64/sse4-64.stderr.exp
diff --git a/main/none/tests/amd64/sse4-64.stdout.exp b/main/none/tests/amd64/sse4-64.stdout.exp
index 2d760e1..229be14 100644
--- a/main/none/tests/amd64/sse4-64.stdout.exp
+++ b/main/none/tests/amd64/sse4-64.stdout.exp
@@ -4764,3 +4764,845 @@
m packusdw 345b9435a82b7aa021e5743791468b3a 45c3a01a18057c2eb339a641d44bfe80 ffff0000ffff0000ffffffff00000000
r packusdw 00008877000066550000443300002211 0000b2a10000ffee0000ddcc0000bbaa 8877665544332211b2a1ffeeddccbbaa
m packusdw 00008877000066550000443300002211 0000b2a10000ffee0000ddcc0000bbaa 8877665544332211b2a1ffeeddccbbaa
+r phminposuw 195b915f616012933094686132b36c7f ce7c3660e5fc1354c39f1bc21e903f8c 00000000000000000000000000041293
+m phminposuw 195b915f616012933094686132b36c7f ce7c3660e5fc1354c39f1bc21e903f8c 00000000000000000000000000041293
+r phminposuw 5ee03fdceafb37577864fef3ed53bd5b a5a03bf091df16e23a4d30e1d0cf0d03 00000000000000000000000000043757
+m phminposuw 5ee03fdceafb37577864fef3ed53bd5b a5a03bf091df16e23a4d30e1d0cf0d03 00000000000000000000000000043757
+r phminposuw 5f369a18df8a2799d523b2dadd3438fa 267aab34b83cc183f40f628a05142414 00000000000000000000000000042799
+m phminposuw 5f369a18df8a2799d523b2dadd3438fa 267aab34b83cc183f40f628a05142414 00000000000000000000000000042799
+r phminposuw 77a89e80de981b05239b00001e619a87 ad58829af49f4fe4cdb02ca9da6c40e9 00000000000000000000000000020000
+m phminposuw 77a89e80de981b05239b00001e619a87 ad58829af49f4fe4cdb02ca9da6c40e9 00000000000000000000000000020000
+r phminposuw 0483477f80b252463e996553cde79e2f 9684bd8ce493fdb1a1fe0a2b6ae31cae 00000000000000000000000000070483
+m phminposuw 0483477f80b252463e996553cde79e2f 9684bd8ce493fdb1a1fe0a2b6ae31cae 00000000000000000000000000070483
+r phminposuw 601492806363060902e95cbe05d1011d 3d4b577822a406954cc379fad2837591 0000000000000000000000000000011d
+m phminposuw 601492806363060902e95cbe05d1011d 3d4b577822a406954cc379fad2837591 0000000000000000000000000000011d
+r phminposuw e9a57af1233774fa4b56612de32b7f7e fef94cc94a5ea83daaccf3042d5a07bb 00000000000000000000000000052337
+m phminposuw e9a57af1233774fa4b56612de32b7f7e fef94cc94a5ea83daaccf3042d5a07bb 00000000000000000000000000052337
+r phminposuw fa82fb3d5bbbd8c4f5aef08c8202d47e 36da98ebf94e1d5497e5f63397738e5b 00000000000000000000000000055bbb
+m phminposuw fa82fb3d5bbbd8c4f5aef08c8202d47e 36da98ebf94e1d5497e5f63397738e5b 00000000000000000000000000055bbb
+r phminposuw eef911d0a7796d14dcbb85c7ff61bb48 3e3a374acaffa187efdafd752ddbc59b 000000000000000000000000000611d0
+m phminposuw eef911d0a7796d14dcbb85c7ff61bb48 3e3a374acaffa187efdafd752ddbc59b 000000000000000000000000000611d0
+r phminposuw 2255b916a4007195dc4a9dca7554f109 7564265259fd72828e7684b40a9d69a7 00000000000000000000000000072255
+m phminposuw 2255b916a4007195dc4a9dca7554f109 7564265259fd72828e7684b40a9d69a7 00000000000000000000000000072255
+r phminposuw f3e1ee7bedd91df4d027b38101e832ec 36a5606f44d5caf04f8708de4bc535ac 000000000000000000000000000101e8
+m phminposuw f3e1ee7bedd91df4d027b38101e832ec 36a5606f44d5caf04f8708de4bc535ac 000000000000000000000000000101e8
+r phminposuw bbeaac6b1f92b0dc961e43d9be283a1e dd49e10d2412e67e10d704de0c60e7d6 00000000000000000000000000051f92
+m phminposuw bbeaac6b1f92b0dc961e43d9be283a1e dd49e10d2412e67e10d704de0c60e7d6 00000000000000000000000000051f92
+r phminposuw d8bcef53d6b764fa09fbc9bcc820c4ca c69ca599974102d7ac33f4a068793950 000000000000000000000000000309fb
+m phminposuw d8bcef53d6b764fa09fbc9bcc820c4ca c69ca599974102d7ac33f4a068793950 000000000000000000000000000309fb
+r phminposuw a4a3b49dadd276fa058ac2183cdd8d1e 4deaa97d39ed59a8ff6754107b1de847 0000000000000000000000000003058a
+m phminposuw a4a3b49dadd276fa058ac2183cdd8d1e 4deaa97d39ed59a8ff6754107b1de847 0000000000000000000000000003058a
+r phminposuw 7cebf5b7407122876596a9d7366a5143 ce7fe827a5a2289de43fa01a6256afe7 00000000000000000000000000042287
+m phminposuw 7cebf5b7407122876596a9d7366a5143 ce7fe827a5a2289de43fa01a6256afe7 00000000000000000000000000042287
+r phminposuw bde0b00b2c20a34e07ecfae7d1d3cb68 a4a65e0277ecab61398755ab38324c5b 000000000000000000000000000307ec
+m phminposuw bde0b00b2c20a34e07ecfae7d1d3cb68 a4a65e0277ecab61398755ab38324c5b 000000000000000000000000000307ec
+r phminposuw c1cde0070c6937fac65831332a25b8b7 2dad07794c581ea0d90aedad1abd79d0 00000000000000000000000000050c69
+m phminposuw c1cde0070c6937fac65831332a25b8b7 2dad07794c581ea0d90aedad1abd79d0 00000000000000000000000000050c69
+r phminposuw e5ff82167cda18387da6caa75b6bd45c c4dedffac071bc089f96e60e2301f271 00000000000000000000000000041838
+m phminposuw e5ff82167cda18387da6caa75b6bd45c c4dedffac071bc089f96e60e2301f271 00000000000000000000000000041838
+r phminposuw 85c290a41aff82b40aa2422f83b1db84 c586e3f06ec4c24369f5bcb86f0c756b 00000000000000000000000000030aa2
+m phminposuw 85c290a41aff82b40aa2422f83b1db84 c586e3f06ec4c24369f5bcb86f0c756b 00000000000000000000000000030aa2
+r phminposuw fd62081d7f62b319471814b7bc04885b 8bf10ec7f2dc6cfd11f4e9991beabce9 0000000000000000000000000006081d
+m phminposuw fd62081d7f62b319471814b7bc04885b 8bf10ec7f2dc6cfd11f4e9991beabce9 0000000000000000000000000006081d
+r phminposuw 55555555555555555555555555555555 aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa 00000000000000000000000000005555
+m phminposuw 55555555555555555555555555555555 aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa 00000000000000000000000000005555
+r mpsadbw $0 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 015d01bd01df014600f401e5012c0079
+m mpsadbw $0 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 015d01bd01df014600f401e5012c0079
+r mpsadbw $1 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 00c6016e024c0177009d0204018900a8
+m mpsadbw $1 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 00c6016e024c0177009d0204018900a8
+r mpsadbw $2 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 00ca01b8021400ed00e701e001510080
+m mpsadbw $2 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 00ca01b8021400ed00e701e001510080
+r mpsadbw $3 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 01a80202010c00bf01fd019c00cd0216
+m mpsadbw $3 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 01a80202010c00bf01fd019c00cd0216
+r mpsadbw $4 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 018c0140027f0225015d01bd01df0146
+m mpsadbw $4 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 018c0140027f0225015d01bd01df0146
+r mpsadbw $5 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 01bd00a90230025600c6016e024c0177
+m mpsadbw $5 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 01bd00a90230025600c6016e024c0177
+r mpsadbw $6 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 013300a1027a01cc00ca01b8021400ed
+m mpsadbw $6 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 013300a1027a01cc00ca01b8021400ed
+r mpsadbw $7 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 007901b901a8007401a80202010c00bf
+m mpsadbw $7 a92be5ed4992e51412d3bc2b226f980c 746b5cebe945f5e3755feb9c43a68419 007901b901a8007401a80202010c00bf
+r mpsadbw $0 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 012601b0020d0202026f022501da0262
+m mpsadbw $0 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 012601b0020d0202026f022501da0262
+r mpsadbw $1 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 006b0111017c0177012600f201810119
+m mpsadbw $1 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 006b0111017c0177012600f201810119
+r mpsadbw $2 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 01660178014900e400dd011300ee00a6
+m mpsadbw $2 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 01660178014900e400dd011300ee00a6
+r mpsadbw $3 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 011a014e00af01240217014100d201c2
+m mpsadbw $3 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 011a014e00af01240217014100d201c2
+r mpsadbw $4 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 00f5009e007f00df012601b0020d0202
+m mpsadbw $4 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 00f5009e007f00df012601b0020d0202
+r mpsadbw $5 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 00b800f9011e0104006b0111017c0177
+m mpsadbw $5 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 00b800f9011e0104006b0111017c0177
+r mpsadbw $6 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 01ef023c020d01e501660178014900e4
+m mpsadbw $6 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 01ef023c020d01e501660178014900e4
+r mpsadbw $7 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 021b0154012500c3011a014e00af0124
+m mpsadbw $7 e66923801418545045a1b677d2ffc7c4 da3fc9c9ee8c9aa16f023dac024c8824 021b0154012500c3011a014e00af0124
+r mpsadbw $0 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 0112008800a0009d00f5012700ba015d
+m mpsadbw $0 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 0112008800a0009d00f5012700ba015d
+r mpsadbw $1 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 0186013c010c00cd00710137009c013d
+m mpsadbw $1 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 0186013c010c00cd00710137009c013d
+r mpsadbw $2 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 015b0149014b00e200d200fa00ff00f6
+m mpsadbw $2 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 015b0149014b00e200d200fa00ff00f6
+r mpsadbw $3 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 011c0188017a01e900e1018d0124012b
+m mpsadbw $3 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 011c0188017a01e900e1018d0124012b
+r mpsadbw $4 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 00ae014700e801370112008800a0009d
+m mpsadbw $4 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 00ae014700e801370112008800a0009d
+r mpsadbw $5 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 006c015700b000a30186013c010c00cd
+m mpsadbw $5 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 006c015700b000a30186013c010c00cd
+r mpsadbw $6 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 01210110008b012a015b0149014b00e2
+m mpsadbw $6 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 01210110008b012a015b0149014b00e2
+r mpsadbw $7 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 012a00cf01cc0183011c0188017a01e9
+m mpsadbw $7 0e67bf427b823e7abe4c7e88e7bed0af 1bbb52cb9e3c97e2dda85bb775e88638 012a00cf01cc0183011c0188017a01e9
+r mpsadbw $0 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 017201c000d5015800de010e0105011c
+m mpsadbw $0 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 017201c000d5015800de010e0105011c
+r mpsadbw $1 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 019200ae00f7015400de00d60081010c
+m mpsadbw $1 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 019200ae00f7015400de00d60081010c
+r mpsadbw $2 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 01df007901b8014101190163014601b1
+m mpsadbw $2 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 01df007901b8014101190163014601b1
+r mpsadbw $3 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 011501110106008500cf0095010200e7
+m mpsadbw $3 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 011501110106008500cf0095010200e7
+r mpsadbw $4 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 0102010c01880129017201c000d50158
+m mpsadbw $4 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 0102010c01880129017201c000d50158
+r mpsadbw $5 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 00fe017a008400f1019200ae00f70154
+m mpsadbw $5 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 00fe017a008400f1019200ae00f70154
+r mpsadbw $6 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 017b01c7009701ca01df007901b80141
+m mpsadbw $6 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 017b01c7009701ca01df007901b80141
+r mpsadbw $7 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 013500e900e7015c0115011101060085
+m mpsadbw $7 7e73b3a01a5bdd3e57a191487ebb70f8 9129f25e94e12853991fc1a8b7873881 013500e900e7015c0115011101060085
+r mpsadbw $0 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 01aa014000e401e900b501e6010201a6
+m mpsadbw $0 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 01aa014000e401e900b501e6010201a6
+r mpsadbw $1 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 015d012300e10164017c00ed017b00cb
+m mpsadbw $1 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 015d012300e10164017c00ed017b00cb
+r mpsadbw $2 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 014b009f014500b201ba01230125008b
+m mpsadbw $2 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 014b009f014500b201ba01230125008b
+r mpsadbw $3 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 01b300eb0219013001e8010f015301bf
+m mpsadbw $3 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 01b300eb0219013001e8010f015301bf
+r mpsadbw $4 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 016800eb016e018d01aa014000e401e9
+m mpsadbw $4 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 016800eb016e018d01aa014000e401e9
+r mpsadbw $5 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 010d016c00830108015d012300e10164
+m mpsadbw $5 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 010d016c00830108015d012300e10164
+r mpsadbw $6 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 01650118014700bc014b009f014500b2
+m mpsadbw $6 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 01650118014700bc014b009f014500b2
+r mpsadbw $7 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 00ed00be0241020601b300eb02190130
+m mpsadbw $7 92d7fd048e2f6e47ed6c6aa5b2ff63cb 9ad6a5ef6d0788a08031ec6be4345a2b 00ed00be0241020601b300eb02190130
+r mpsadbw $0 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 00e900d7009b00ea0112019101b7013b
+m mpsadbw $0 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 00e900d7009b00ea0112019101b7013b
+r mpsadbw $1 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 00ca00d2007a00d70149015a01860116
+m mpsadbw $1 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 00ca00d2007a00d70149015a01860116
+r mpsadbw $2 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 0115014300af00f80156014d02230167
+m mpsadbw $2 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 0115014300af00f80156014d02230167
+r mpsadbw $3 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 01100114013c00bf01a700fc01a40136
+m mpsadbw $3 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 01100114013c00bf01a700fc01a40136
+r mpsadbw $4 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 01b50104013d012e00e900d7009b00ea
+m mpsadbw $4 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 01b50104013d012e00e900d7009b00ea
+r mpsadbw $5 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 00fe0109018c012900ca00d2007a00d7
+m mpsadbw $5 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 00fe0109018c012900ca00d2007a00d7
+r mpsadbw $6 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 01c70108016f019a0115014300af00f8
+m mpsadbw $6 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 01c70108016f019a0115014300af00f8
+r mpsadbw $7 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 017a011500d4018701100114013c00bf
+m mpsadbw $7 a6e098dc738b2d425d78858aa0986556 900e67e9c43bf4746fab56ed19fcaa61 017a011500d4018701100114013c00bf
+r mpsadbw $0 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 013d00d300d60151008800fb0144018a
+m mpsadbw $0 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 013d00d300d60151008800fb0144018a
+r mpsadbw $1 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 014b00e700c4016300f600990116017c
+m mpsadbw $1 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 014b00e700c4016300f600990116017c
+r mpsadbw $2 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 016d0159013201af012e012701720134
+m mpsadbw $2 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 016d0159013201af012e012701720134
+r mpsadbw $3 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 0097016b013c0129012a018f01240110
+m mpsadbw $3 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 0097016b013c0129012a018f01240110
+r mpsadbw $4 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 01b5011300f10173013d00d300d60151
+m mpsadbw $4 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 01b5011300f10173013d00d300d60151
+r mpsadbw $5 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 01c7017301230185014b00e700c40163
+m mpsadbw $5 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 01c7017301230185014b00e700c40163
+r mpsadbw $6 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 02130163019501d1016d0159013201af
+m mpsadbw $6 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 02130163019501d1016d0159013201af
+r mpsadbw $7 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 0141011501d101310097016b013c0129
+m mpsadbw $7 16da809364fa55da81935fe2639131c2 d11d34b73609a87b40597d1871eae250 0141011501d101310097016b013c0129
+r mpsadbw $0 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 01ae01de018e029c00b5019202aa0152
+m mpsadbw $0 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 01ae01de018e029c00b5019202aa0152
+r mpsadbw $1 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 016101bf012301c3017e01f301ad016f
+m mpsadbw $1 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 016101bf012301c3017e01f301ad016f
+r mpsadbw $2 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 012c01da019e0106033301bc0040022a
+m mpsadbw $2 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 012c01da019e0106033301bc0040022a
+r mpsadbw $3 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 0217019f01d9010d01b4029b017700b9
+m mpsadbw $3 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 0217019f01d9010d01b4029b017700b9
+r mpsadbw $4 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 01880122026000ca01ae01de018e029c
+m mpsadbw $4 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 01880122026000ca01ae01de018e029c
+r mpsadbw $5 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 012900e101870141016101bf012301c3
+m mpsadbw $5 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 012900e101870141016101bf012301c3
+r mpsadbw $6 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 01b0022c018602a6012c01da019e0106
+m mpsadbw $6 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 01b0022c018602a6012c01da019e0106
+r mpsadbw $7 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 006501a5016b01690217019f01d9010d
+m mpsadbw $7 3d11b294fd0923bc3687729b18f7843e b74f09c75efbdf63d007ddd9090abf23 006501a5016b01690217019f01d9010d
+r mpsadbw $0 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 0100015a009602210081023c013c025e
+m mpsadbw $0 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 0100015a009602210081023c013c025e
+r mpsadbw $1 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 01ef020f01eb023801720195019f0243
+m mpsadbw $1 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 01ef020f01eb023801720195019f0243
+r mpsadbw $2 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 013a00d4016c00f302270090024c00fe
+m mpsadbw $2 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 013a00d4016c00f302270090024c00fe
+r mpsadbw $3 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 01870169018301c800e4021901770205
+m mpsadbw $3 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 01870169018301c800e4021901770205
+r mpsadbw $4 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 00a8016a00fd01110100015a00960221
+m mpsadbw $4 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 00a8016a00fd01110100015a00960221
+r mpsadbw $5 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 01d50187017a01cc01ef020f01eb0238
+m mpsadbw $5 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 01d50187017a01cc01ef020f01eb0238
+r mpsadbw $6 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 01460058016300a5013a00d4016c00f3
+m mpsadbw $6 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 01460058016300a5013a00d4016c00f3
+r mpsadbw $7 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 016d01b5011201c601870169018301c8
+m mpsadbw $7 79d0294ddb42d39459223ca0dad41af4 9fefe184d89fd6d6fb81f01dfd68fc07 016d01b5011201c601870169018301c8
+r mpsadbw $0 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 019200df00ec01bb00ae0171011e00f2
+m mpsadbw $0 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 019200df00ec01bb00ae0171011e00f2
+r mpsadbw $1 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 0165010801b7009c0145022c00f1014f
+m mpsadbw $1 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 0165010801b7009c0145022c00f1014f
+r mpsadbw $2 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 015e010300b801910090013d014200b8
+m mpsadbw $2 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 015e010300b801910090013d014200b8
+r mpsadbw $3 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 0196016b00ee01f900ee010b01aa0122
+m mpsadbw $3 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 0196016b00ee01f900ee010b01aa0122
+r mpsadbw $4 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 0181010e015b0159019200df00ec01bb
+m mpsadbw $4 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 0181010e015b0159019200df00ec01bb
+r mpsadbw $5 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 01c2009d00da01c40165010801b7009c
+m mpsadbw $5 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 01c2009d00da01c40165010801b7009c
+r mpsadbw $6 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 014d011801270141015e010300b80191
+m mpsadbw $6 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 014d011801270141015e010300b80191
+r mpsadbw $7 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 01170196015900a70196016b00ee01f9
+m mpsadbw $7 2565e1299934a00dc42e38ddc537ae10 e64ab85a4181c9809e9234cf67115727 01170196015900a70196016b00ee01f9
+r mpsadbw $0 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 02b2013f02e40178017102cb017c012c
+m mpsadbw $0 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 02b2013f02e40178017102cb017c012c
+r mpsadbw $1 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 01ce018f0156020a00d1013d01b60144
+m mpsadbw $1 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 01ce018f0156020a00d1013d01b60144
+r mpsadbw $2 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 0230017b0262014c01910249010a0128
+m mpsadbw $2 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 0230017b0262014c01910249010a0128
+r mpsadbw $3 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 021501320247011500d0022e015900a9
+m mpsadbw $3 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 021501320247011500d0022e015900a9
+r mpsadbw $4 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 017d02550153017e02b2013f02e40178
+m mpsadbw $4 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 017d02550153017e02b2013f02e40178
+r mpsadbw $5 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 00a10133021100ae01ce018f0156020a
+m mpsadbw $5 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 00a10133021100ae01ce018f0156020a
+r mpsadbw $6 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 00fb01d3010f01ce0230017b0262014c
+m mpsadbw $6 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 00fb01d3010f01ce0230017b0262014c
+r mpsadbw $7 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 010001b8013e011d0215013202470115
+m mpsadbw $7 9d1ad694d468c8d45478e23ef629fdc0 e6ad8ab5352bf40e930823da66108ab0 010001b8013e011d0215013202470115
+r mpsadbw $0 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 01a40120008200c2015201cd017701cd
+m mpsadbw $0 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 01a40120008200c2015201cd017701cd
+r mpsadbw $1 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 018500f5014b014b01ef022a021401ae
+m mpsadbw $1 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 018500f5014b014b01ef022a021401ae
+r mpsadbw $2 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 00a600f600d00182019000e900b30087
+m mpsadbw $2 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 00a600f600d00182019000e900b30087
+r mpsadbw $3 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 00d3016501f301f1017f00a8015000da
+m mpsadbw $3 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 00d3016501f301f1017f00a8015000da
+r mpsadbw $4 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 016e016301ed00fa01a40120008200c2
+m mpsadbw $4 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 016e016301ed00fa01a40120008200c2
+r mpsadbw $5 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 02110248020a01df018500f5014b014b
+m mpsadbw $5 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 02110248020a01df018500f5014b014b
+r mpsadbw $6 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 011c0137009f00de00a600f600d00182
+m mpsadbw $6 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 011c0137009f00de00a600f600d00182
+r mpsadbw $7 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 00eb016c00de017f00d3016501f301f1
+m mpsadbw $7 3d3c04fa276c8594e5cbb7b089b8c32e fc6254014f2b922cb7ad3c2c137252ce 00eb016c00de017f00d3016501f301f1
+r mpsadbw $0 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 0132011300fd015400670111010f0131
+m mpsadbw $0 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 0132011300fd015400670111010f0131
+r mpsadbw $1 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 017801e30139029400f7016b012301b5
+m mpsadbw $1 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 017801e30139029400f7016b012301b5
+r mpsadbw $2 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 00bd027600ae026301560216017e018c
+m mpsadbw $2 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 00bd027600ae026301560216017e018c
+r mpsadbw $3 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 015701e6013e0165017601dc014a0076
+m mpsadbw $3 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 015701e6013e0165017601dc014a0076
+r mpsadbw $4 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 016801d701df01750132011300fd0154
+m mpsadbw $4 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 016801d701df01750132011300fd0154
+r mpsadbw $5 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 01d000a302090227017801e301390294
+m mpsadbw $5 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 01d000a302090227017801e301390294
+r mpsadbw $6 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 02a90144013c020400bd027600ae0263
+m mpsadbw $6 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 02a90144013c020400bd027600ae0263
+r mpsadbw $7 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 013d01dc00d200fa015701e6013e0165
+m mpsadbw $7 601768c82fcb13fa53f5311d99efbc86 85b610ab2b0de085e64ef8b08d426aac 013d01dc00d200fa015701e6013e0165
+r mpsadbw $0 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 010400d400da01b200d501ce009f018c
+m mpsadbw $0 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 010400d400da01b200d501ce009f018c
+r mpsadbw $1 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 015700d9010100b10148010100b400eb
+m mpsadbw $1 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 015700d9010100b10148010100b400eb
+r mpsadbw $2 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 009401720152019e018b00f00157013c
+m mpsadbw $2 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 009401720152019e018b00f00157013c
+r mpsadbw $3 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 01b100cb0119011701a6014900b40171
+m mpsadbw $3 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 01b100cb0119011701a6014900b40171
+r mpsadbw $4 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 01e6020f01bd015c010400d400da01b2
+m mpsadbw $4 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 01e6020f01bd015c010400d400da01b2
+r mpsadbw $5 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 013b016401820181015700d9010100b1
+m mpsadbw $5 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 013b016401820181015700d9010100b1
+r mpsadbw $6 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 01f600e101ab0114009401720152019e
+m mpsadbw $6 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 01f600e101ab0114009401720152019e
+r mpsadbw $7 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 01ad01d601c801df01b100cb01190117
+m mpsadbw $7 64f7fd688712b0b27ac0ce7242dba3f5 dbf4bc1d665b1ac6fcb7d452ed8c8f77 01ad01d601c801df01b100cb01190117
+r mpsadbw $0 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 00a100e5012d00cf016b013100e5010f
+m mpsadbw $0 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 00a100e5012d00cf016b013100e5010f
+r mpsadbw $1 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 01b501870181018b026900a101e3016d
+m mpsadbw $1 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 01b501870181018b026900a101e3016d
+r mpsadbw $2 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 00eb010d007301010115010100fb010f
+m mpsadbw $2 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 00eb010d007301010115010100fb010f
+r mpsadbw $3 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 0108011e00ca01e6007e01b2011c00de
+m mpsadbw $3 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 0108011e00ca01e6007e01b2011c00de
+r mpsadbw $4 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 010500f600d2007400a100e5012d00cf
+m mpsadbw $4 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 010500f600d2007400a100e5012d00cf
+r mpsadbw $5 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 019500ec01a6013001b501870181018b
+m mpsadbw $5 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 019500ec01a6013001b501870181018b
+r mpsadbw $6 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 013d00c2005800a600eb010d00730101
+m mpsadbw $6 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 013d00c2005800a600eb010d00730101
+r mpsadbw $7 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 00c0016d00e5011b0108011e00ca01e6
+m mpsadbw $7 a427bf47cccb966737fa099ca18735a7 5b6a53c49ca37b9ad5b34dfe515d7d5a 00c0016d00e5011b0108011e00ca01e6
+r mpsadbw $0 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 021a01b9010b024b0163011901170149
+m mpsadbw $0 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 021a01b9010b024b0163011901170149
+r mpsadbw $1 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 00c100ec0112010e0156015e01700158
+m mpsadbw $1 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 00c100ec0112010e0156015e01700158
+r mpsadbw $2 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 01910182007401c201900138014001a8
+m mpsadbw $2 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 01910182007401c201900138014001a8
+r mpsadbw $3 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 014901a20180017a009000f400780124
+m mpsadbw $3 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 014901a20180017a009000f400780124
+r mpsadbw $4 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 011e018102270124021a01b9010b024b
+m mpsadbw $4 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 011e018102270124021a01b9010b024b
+r mpsadbw $5 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 00d700ea00b4004f00c100ec0112010e
+m mpsadbw $5 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 00d700ea00b4004f00c100ec0112010e
+r mpsadbw $6 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 00ed016a019e009b01910182007401c2
+m mpsadbw $6 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 00ed016a019e009b01910182007401c2
+r mpsadbw $7 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 014501e201c80127014901a20180017a
+m mpsadbw $7 7cf5aad2998502c5646d5f85d2ff2ec7 6162d20d677140ae4d10dea0d5c0f082 014501e201c80127014901a20180017a
+r mpsadbw $0 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 019b00c8011e019c00dc01a101a7018c
+m mpsadbw $0 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 019b00c8011e019c00dc01a101a7018c
+r mpsadbw $1 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 015900f8013c013c01c8028d020b00c8
+m mpsadbw $1 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 015900f8013c013c01c8028d020b00c8
+r mpsadbw $2 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 01190064018c00fe00f801d9015700e4
+m mpsadbw $2 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 01190064018c00fe00f801d9015700e4
+r mpsadbw $3 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 004d01000164012001b0013f007100d2
+m mpsadbw $3 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 004d01000164012001b0013f007100d2
+r mpsadbw $4 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 0118011e00ca0111019b00c8011e019c
+m mpsadbw $4 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 0118011e00ca0111019b00c8011e019c
+r mpsadbw $5 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 01cc017e018a01fd015900f8013c013c
+m mpsadbw $5 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 01cc017e018a01fd015900f8013c013c
+r mpsadbw $6 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 0140012000d6014901190064018c00fe
+m mpsadbw $6 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 0140012000d6014901190064018c00fe
+r mpsadbw $7 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 00fa00d400fe00cb004d010001640120
+m mpsadbw $7 47abba738bc92f7adee64a1bef504a82 49293363664fa5ae4098032494c1a31b 00fa00d400fe00cb004d010001640120
+r mpsadbw $0 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 019e016b0094015e0129010000fe0109
+m mpsadbw $0 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 019e016b0094015e0129010000fe0109
+r mpsadbw $1 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 014400eb00d4005e0101011400b20077
+m mpsadbw $1 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 014400eb00d4005e0101011400b20077
+r mpsadbw $2 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 01bf011000b700c100d000e300f500dc
+m mpsadbw $2 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 01bf011000b700c100d000e300f500dc
+r mpsadbw $3 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 016e01b5015c0178012f00b600ee0153
+m mpsadbw $3 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 016e01b5015c0178012f00b600ee0153
+r mpsadbw $4 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 0060018b01d70147019e016b0094015e
+m mpsadbw $4 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 0060018b01d70147019e016b0094015e
+r mpsadbw $5 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 00e600a50173018b014400eb00d4005e
+m mpsadbw $5 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 00e600a50173018b014400eb00d4005e
+r mpsadbw $6 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 00ad01060142015201bf011000b700c1
+m mpsadbw $6 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 00ad01060142015201bf011000b700c1
+r mpsadbw $7 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 019a0163010300bf016e01b5015c0178
+m mpsadbw $7 6396ec983d255a308131484917854403 6f0b743133cce6458a193977ab6c5350 019a0163010300bf016e01b5015c0178
+r mpsadbw $0 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 01a2019c01e600d700ef01b800e40099
+m mpsadbw $0 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 01a2019c01e600d700ef01b800e40099
+r mpsadbw $1 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 0216018800920103022d020800bc0187
+m mpsadbw $1 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 0216018800920103022d020800bc0187
+r mpsadbw $2 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 016b00ff011100c8018201d300810108
+m mpsadbw $2 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 016b00ff011100c8018201d300810108
+r mpsadbw $3 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 014300b5007f016601ea0179012f01b6
+m mpsadbw $3 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 014300b5007f016601ea0179012f01b6
+r mpsadbw $4 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 004300dc0162013101a2019c01e600d7
+m mpsadbw $4 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 004300dc0162013101a2019c01e600d7
+r mpsadbw $5 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 01450228022e020b0216018800920103
+m mpsadbw $5 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 01450228022e020b0216018800920103
+r mpsadbw $6 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 00c4017d01830160016b00ff011100c8
+m mpsadbw $6 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 00c4017d01830160016b00ff011100c8
+r mpsadbw $7 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 01a401b301c7013e014300b5007f0166
+m mpsadbw $7 2a023bac4b24bf932819d4fb64aad977 2f5490e56a713e20075dfa8335cebc4e 01a401b301c7013e014300b5007f0166
+r mpsadbw $0 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 00f50080018e0126019b022301f9012d
+m mpsadbw $0 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 00f50080018e0126019b022301f9012d
+r mpsadbw $1 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 018f00f4014000cc013d013b019f013d
+m mpsadbw $1 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 018f00f4014000cc013d013b019f013d
+r mpsadbw $2 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 01a4015501b500a700f8017e00c400b4
+m mpsadbw $2 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 01a4015501b500a700f8017e00c400b4
+r mpsadbw $3 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 019c00e5018300ad01f2016801a60192
+m mpsadbw $3 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 019c00e5018300ad01f2016801a60192
+r mpsadbw $4 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 01ae016c0114015200f50080018e0126
+m mpsadbw $4 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 01ae016c0114015200f50080018e0126
+r mpsadbw $5 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 0184019801a401b6018f00f4014000cc
+m mpsadbw $5 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 0184019801a401b6018f00f4014000cc
+r mpsadbw $6 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 00db015301b901b901a4015501b500a7
+m mpsadbw $6 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 00db015301b901b901a4015501b500a7
+r mpsadbw $7 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 01c701db017501f9019c00e5018300ad
+m mpsadbw $7 fa3ba31b52539a50b16c6a1df2cbc409 e55084eaa8cceaea9331c4364ef39a40 01c701db017501f9019c00e5018300ad
+r mpsadbw $0 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 0295029d02b10287027e01f901a7018a
+m mpsadbw $0 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 0295029d02b10287027e01f901a7018a
+r mpsadbw $1 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 0225022d02410217020e021d01c9015c
+m mpsadbw $1 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 0225022d02410217020e021d01c9015c
+r mpsadbw $2 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 00cf0145010b0183010c01ff01f10244
+m mpsadbw $2 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 00cf0145010b0183010c01ff01f10244
+r mpsadbw $3 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 0118006a01240088014500d001e200fb
+m mpsadbw $3 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 0118006a01240088014500d001e200fb
+r mpsadbw $4 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 01b4019701bb02170295029d02b10287
+m mpsadbw $4 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 01b4019701bb02170295029d02b10287
+r mpsadbw $5 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 018e0129014b01a70225022d02410217
+m mpsadbw $5 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 018e0129014b01a70225022d02410217
+r mpsadbw $6 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 01aa01c900e100cf00cf0145010b0183
+m mpsadbw $6 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 01aa01c900e100cf00cf0145010b0183
+r mpsadbw $7 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 012300ba00f600860118006a01240088
+m mpsadbw $7 2d8d2151ee3d2713f7f4879bdef5c3e7 ed4b4aac886826500a60127a13e5a853 012300ba00f600860118006a01240088
+r mpsadbw $0 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 011001a5011d00bc015a00ae00fd0166
+m mpsadbw $0 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 011001a5011d00bc015a00ae00fd0166
+r mpsadbw $1 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 00c701dc0072013100e3010d010a00bd
+m mpsadbw $1 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 00c701dc0072013100e3010d010a00bd
+r mpsadbw $2 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 00f301a600a80147008d00b700dc008b
+m mpsadbw $2 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 00f301a600a80147008d00b700dc008b
+r mpsadbw $3 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 01860131014501680140005c00930102
+m mpsadbw $3 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 01860131014501680140005c00930102
+r mpsadbw $4 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 016c01ad01130226011001a5011d00bc
+m mpsadbw $4 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 016c01ad01130226011001a5011d00bc
+r mpsadbw $5 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 00fb009400c6019700c701dc00720131
+m mpsadbw $5 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 00fb009400c6019700c701dc00720131
+r mpsadbw $6 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 00c5009e00e4016100f301a600a80147
+m mpsadbw $6 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 00c5009e00e4016100f301a600a80147
+r mpsadbw $7 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 01380133018701d80186013101450168
+m mpsadbw $7 2143afbaba6ea187d67ea5614334903a a390e097a6d12efe48b8603da0b2a3b2 01380133018701d80186013101450168
+r mpsadbw $0 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 00fe00fb01b7019a0140014701460155
+m mpsadbw $0 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 00fe00fb01b7019a0140014701460155
+r mpsadbw $1 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 019300bc019200fb014500aa013f00be
+m mpsadbw $1 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 019300bc019200fb014500aa013f00be
+r mpsadbw $2 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 010300b4010800c50105007200af0082
+m mpsadbw $2 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 010300b4010800c50105007200af0082
+r mpsadbw $3 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 01c000fb01d10128017e00dd016c00a1
+m mpsadbw $3 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 01c000fb01d10128017e00dd016c00a1
+r mpsadbw $4 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 01c001290093017e00fe00fb01b7019a
+m mpsadbw $4 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 01c001290093017e00fe00fb01b7019a
+r mpsadbw $5 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 0147016c00b80101019300bc019200fb
+m mpsadbw $5 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 0147016c00b80101019300bc019200fb
+r mpsadbw $6 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 00c1010200d200bd010300b4010800c5
+m mpsadbw $6 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 00c1010200d200bd010300b4010800c5
+r mpsadbw $7 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 00fc012700f100b801c000fb01d10128
+m mpsadbw $7 30ab4bc2527345592ad6425b3d92e831 636d4118a0943d9f28032b6a1066468b 00fc012700f100b801c000fb01d10128
+r mpsadbw $0 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 01e9020600f500e0028901c5018701a3
+m mpsadbw $0 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 01e9020600f500e0028901c5018701a3
+r mpsadbw $1 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 00e4010f0192018b01020108015c0206
+m mpsadbw $1 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 00e4010f0192018b01020108015c0206
+r mpsadbw $2 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 014300a601d302540143010b014f0127
+m mpsadbw $2 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 014300a601d302540143010b014f0127
+r mpsadbw $3 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 015a0227019a004b01e0024e021001ac
+m mpsadbw $3 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 015a0227019a004b01e0024e021001ac
+r mpsadbw $4 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 0204022e010f011a01e9020600f500e0
+m mpsadbw $4 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 0204022e010f011a01e9020600f500e0
+r mpsadbw $5 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 01a9019901a601ff00e4010f0192018b
+m mpsadbw $5 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 01a9019901a601ff00e4010f0192018b
+r mpsadbw $6 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 0106009a017b01cc014300a601d30254
+m mpsadbw $6 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 0106009a017b01cc014300a601d30254
+r mpsadbw $7 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 0203025301180141015a0227019a004b
+m mpsadbw $7 b80ff0d553d74e35cfc8d976ea1d86f6 892c69990f3c90e0880feded7f0b4f07 0203025301180141015a0227019a004b
+r mpsadbw $0 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 014200a001b700610236009101eb013c
+m mpsadbw $0 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 014200a001b700610236009101eb013c
+r mpsadbw $1 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 01610137011001bc00d101fe008401db
+m mpsadbw $1 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 01610137011001bc00d101fe008401db
+r mpsadbw $2 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 015001280127017f015401c7010f01ca
+m mpsadbw $2 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 015001280127017f015401c7010f01ca
+r mpsadbw $3 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 00e7013d011a010e019900fa017e0043
+m mpsadbw $3 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 00e7013d011a010e019900fa017e0043
+r mpsadbw $4 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 015a013200f5013e014200a001b70061
+m mpsadbw $4 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 015a013200f5013e014200a001b70061
+r mpsadbw $5 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 0125014f015400f901610137011001bc
+m mpsadbw $5 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 0125014f015400f901610137011001bc
+r mpsadbw $6 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 0114013e01a1015a015001280127017f
+m mpsadbw $6 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 0114013e01a1015a015001280127017f
+r mpsadbw $7 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 00b3008900e6012700e7013d011a010e
+m mpsadbw $7 13bc9a605826fac6a020e79c63e127b5 711a54879156636c43a624b20aaf7855 00b3008900e6012700e7013d011a010e
+r mpsadbw $0 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 0131008b013a0129011c013f0083009d
+m mpsadbw $0 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 0131008b013a0129011c013f0083009d
+r mpsadbw $1 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 00e5019301aa010b00ca00ab01110121
+m mpsadbw $1 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 00e5019301aa010b00ca00ab01110121
+r mpsadbw $2 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 018500810144016b0140019d00d900df
+m mpsadbw $2 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 018500810144016b0140019d00d900df
+r mpsadbw $3 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 018000aa01eb0100011b01a000a00134
+m mpsadbw $3 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 018000aa01eb0100011b01a000a00134
+r mpsadbw $4 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 00b9013b010d013e0131008b013a0129
+m mpsadbw $4 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 00b9013b010d013e0131008b013a0129
+r mpsadbw $5 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 00fb015100f300c400e5019301aa010b
+m mpsadbw $5 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 00fb015100f300c400e5019301aa010b
+r mpsadbw $6 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 00cb012901290162018500810144016b
+m mpsadbw $6 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 00cb012901290162018500810144016b
+r mpsadbw $7 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 003001ec00d60183018000aa01eb0100
+m mpsadbw $7 9efe46cdfeed83b87baae6bbc6e8879b 7783ff4fc26df1f035954ca5cc5e7e9f 003001ec00d60183018000aa01eb0100
+r mpsadbw $0 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 013e00c5006f011101760254021d01da
+m mpsadbw $0 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 013e00c5006f011101760254021d01da
+r mpsadbw $1 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0134008500a1010f019e024e01fb019a
+m mpsadbw $1 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0134008500a1010f019e024e01fb019a
+r mpsadbw $2 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 01a0012d01ef01770116015a00f90148
+m mpsadbw $2 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 01a0012d01ef01770116015a00f90148
+r mpsadbw $3 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0226011b0151013b0160012e01ff0178
+m mpsadbw $3 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0226011b0151013b0160012e01ff0178
+r mpsadbw $4 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0145013c00e10112013e00c5006f0111
+m mpsadbw $4 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0145013c00e10112013e00c5006f0111
+r mpsadbw $5 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0131011a00b900ee0134008500a1010f
+m mpsadbw $5 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0131011a00b900ee0134008500a1010f
+r mpsadbw $6 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0133019c0159024001a0012d01ef0177
+m mpsadbw $6 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 0133019c0159024001a0012d01ef0177
+r mpsadbw $7 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 012701ba016b01760226011b0151013b
+m mpsadbw $7 b621ee8ae0b725b93b3154bd2f4062d4 f7b2645b3d0d771839a8dfb2e2221c11 012701ba016b01760226011b0151013b
+r mpsadbw $0 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 014601540159012b011f011e018001ef
+m mpsadbw $0 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 014601540159012b011f011e018001ef
+r mpsadbw $1 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 00d7013100ba013e007c0171014701b2
+m mpsadbw $1 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 00d7013100ba013e007c0171014701b2
+r mpsadbw $2 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 00fe013000cd0197010b01a800f800af
+m mpsadbw $2 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 00fe013000cd0197010b01a800f800af
+r mpsadbw $3 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 007901af00dc01bc00bc00e100af020c
+m mpsadbw $3 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 007901af00dc01bc00bc00e100af020c
+r mpsadbw $4 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 011e0175019f0095014601540159012b
+m mpsadbw $4 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 011e0175019f0095014601540159012b
+r mpsadbw $5 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 00db00e4013400da00d7013100ba013e
+m mpsadbw $5 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 00db00e4013400da00d7013100ba013e
+r mpsadbw $6 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 00fc00f301f500e500fe013000cd0197
+m mpsadbw $6 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 00fc00f301f500e500fe013000cd0197
+r mpsadbw $7 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 0165015a012c0156007901af00dc01bc
+m mpsadbw $7 b57090019b101e72bc82ac90b9f5748b 4cf581199ec2318f2daa5ac5670910d8 0165015a012c0156007901af00dc01bc
+r mpsadbw $0 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 0127012f021b0123010701cd01e30146
+m mpsadbw $0 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 0127012f021b0123010701cd01e30146
+r mpsadbw $1 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 020601b4017600f0015a010e00720103
+m mpsadbw $1 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 020601b4017600f0015a010e00720103
+r mpsadbw $2 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 01dd016101c700e500e90179011501be
+m mpsadbw $2 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 01dd016101c700e500e90179011501be
+r mpsadbw $3 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 017201d20252007a015c02220100012d
+m mpsadbw $3 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 017201d20252007a015c02220100012d
+r mpsadbw $4 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 013d01ee01d601130127012f021b0123
+m mpsadbw $4 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 013d01ee01d601130127012f021b0123
+r mpsadbw $5 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 0148012f00bf00d6020601b4017600f0
+m mpsadbw $5 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 0148012f00bf00d6020601b4017600f0
+r mpsadbw $6 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 00c3018600f4019301dd016101c700e5
+m mpsadbw $6 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 00c3018600f4019301dd016101c700e5
+r mpsadbw $7 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 0166024300a10168017201d20252007a
+m mpsadbw $7 f83927a0ca85a892d96a6a1f801278ed d49652f482195a01ec693acb781f1420 0166024300a10168017201d20252007a
+r mpsadbw $0 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 00b101a7022f01b300f200b201820170
+m mpsadbw $0 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 00b101a7022f01b300f200b201820170
+r mpsadbw $1 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 00c6017601fe016a015100cd01b3019f
+m mpsadbw $1 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 00c6017601fe016a015100cd01b3019f
+r mpsadbw $2 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 0192011001480164023f018101a501eb
+m mpsadbw $2 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 0192011001480164023f018101a501eb
+r mpsadbw $3 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 01e901d7015d010f0104011a011601f4
+m mpsadbw $3 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 01e901d7015d010f0104011a011601f4
+r mpsadbw $4 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 00fb014c00e3003100b101a7022f01b3
+m mpsadbw $4 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 00fb014c00e3003100b101a7022f01b3
+r mpsadbw $5 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 010e017d00fe008a00c6017601fe016a
+m mpsadbw $5 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 010e017d00fe008a00c6017601fe016a
+r mpsadbw $6 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 019e01bb019a01560192011001480164
+m mpsadbw $6 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 019e01bb019a01560192011001480164
+r mpsadbw $7 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 00b700d8017901b501e901d7015d010f
+m mpsadbw $7 dbc6b0d20aa100c370b20a56a1a32b26 eae2d158859d301c51affaae306fe414 00b700d8017901b501e901d7015d010f
+r mpsadbw $0 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 01450104011900a3010f013a009201ad
+m mpsadbw $0 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 01450104011900a3010f013a009201ad
+r mpsadbw $1 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 01de014d008c008a0102013700a5016a
+m mpsadbw $1 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 01de014d008c008a0102013700a5016a
+r mpsadbw $2 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 00be00fd01d402020190026b01ad0188
+m mpsadbw $2 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 00be00fd01d402020190026b01ad0188
+r mpsadbw $3 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 014500b400930103019f013601020165
+m mpsadbw $3 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 014500b400930103019f013601020165
+r mpsadbw $4 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 00e30147020a00ff01450104011900a3
+m mpsadbw $4 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 00e30147020a00ff01450104011900a3
+r mpsadbw $5 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 01d2021c020d021801de014d008c008a
+m mpsadbw $5 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 01d2021c020d021801de014d008c008a
+r mpsadbw $6 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 019c008e01a9017c00be00fd01d40202
+m mpsadbw $6 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 019c008e01a9017c00be00fd01d40202
+r mpsadbw $7 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 01f9018301cc023f014500b400930103
+m mpsadbw $7 bb642503f6f061b15b29092138b44861 e925fcb142dbed8a3a4a165cac053ee1 01f9018301cc023f014500b400930103
+r mpsadbw $0 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 013101e5020f00fd01990168011d015b
+m mpsadbw $0 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 013101e5020f00fd01990168011d015b
+r mpsadbw $1 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 0077017b01d701c9018b01ee01550111
+m mpsadbw $1 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 0077017b01d701c9018b01ee01550111
+r mpsadbw $2 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 01ca01280150020801d40145034201b2
+m mpsadbw $2 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 01ca01280150020801d40145034201b2
+r mpsadbw $3 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 0193015b013b016502150212013101e5
+m mpsadbw $3 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 0193015b013b016502150212013101e5
+r mpsadbw $4 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 015f012c003f0083013101e5020f00fd
+m mpsadbw $4 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 015f012c003f0083013101e5020f00fd
+r mpsadbw $5 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 00f50120013700ff0077017b01d701c9
+m mpsadbw $5 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 00f50120013700ff0077017b01d701c9
+r mpsadbw $6 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 015e01d70202027c01ca012801500208
+m mpsadbw $6 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 015e01d70202027c01ca012801500208
+r mpsadbw $7 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 011900a000e5013f0193015b013b0165
+m mpsadbw $7 f25f849f2bff090a789ae26c5f528ccb 2fabce6b555ecdf781040bbf07eddcb3 011900a000e5013f0193015b013b0165
+r mpsadbw $0 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 0225016900ed00e800ed010d014e00da
+m mpsadbw $0 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 0225016900ed00e800ed010d014e00da
+r mpsadbw $1 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 00f301e7022701a8017300b5011201dc
+m mpsadbw $1 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 00f301e7022701a8017300b5011201dc
+r mpsadbw $2 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 014f00df01250100011900eb008a00c4
+m mpsadbw $2 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 014f00df01250100011900eb008a00c4
+r mpsadbw $3 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 00fc0238012e02a700d201d8016f01a1
+m mpsadbw $3 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 00fc0238012e02a700d201d8016f01a1
+r mpsadbw $4 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 014300f3016c01740225016900ed00e8
+m mpsadbw $4 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 014300f3016c01740225016900ed00e8
+r mpsadbw $5 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 01c50159017c007a00f301e7022701a8
+m mpsadbw $5 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 01c50159017c007a00f301e7022701a8
+r mpsadbw $6 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 016f00fd019a00fc014f00df01250100
+m mpsadbw $6 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 016f00fd019a00fc014f00df01250100
+r mpsadbw $7 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 00d00296008701ed00fc0238012e02a7
+m mpsadbw $7 dd03c81244593278a1d011233588b38f 17c043f25bb20e1004aa54c55d347bb5 00d00296008701ed00fc0238012e02a7
+r mpsadbw $0 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 013d012c016e0120010600ce015401b0
+m mpsadbw $0 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 013d012c016e0120010600ce015401b0
+r mpsadbw $1 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 017a0105007b012901b901f302030147
+m mpsadbw $1 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 017a0105007b012901b901f302030147
+r mpsadbw $2 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 014b013a00bc01640158019201c001be
+m mpsadbw $2 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 014b013a00bc01640158019201c001be
+r mpsadbw $3 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 0159013e019a01c0019800ee00c40122
+m mpsadbw $3 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 0159013e019a01c0019800ee00c40122
+r mpsadbw $4 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 007d01b900d400e7013d012c016e0120
+m mpsadbw $4 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 007d01b900d400e7013d012c016e0120
+r mpsadbw $5 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 01a2018401610196017a0105007b0129
+m mpsadbw $5 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 01a2018401610196017a0105007b0129
+r mpsadbw $6 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 014101c7011e012f014b013a00bc0164
+m mpsadbw $6 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 014101c7011e012f014b013a00bc0164
+r mpsadbw $7 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 00cf00fd012400990159013e019a01c0
+m mpsadbw $7 d89cedc8dd8a19a7b4991233d46279da fcb057b2ef64ea819d076c59cbe5d613 00cf00fd012400990159013e019a01c0
+r mpsadbw $0 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 01fd00d001b400da014901f80149012b
+m mpsadbw $0 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 01fd00d001b400da014901f80149012b
+r mpsadbw $1 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 018300e401d2011a008f012400f1018f
+m mpsadbw $1 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 018300e401d2011a008f012400f1018f
+r mpsadbw $2 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 01080255010b017d01c4014b01ce013e
+m mpsadbw $2 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 01080255010b017d01c4014b01ce013e
+r mpsadbw $3 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 00f0026101ad00e101d00145019201aa
+m mpsadbw $3 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 00f0026101ad00e101d00145019201aa
+r mpsadbw $4 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 02000162011d008901fd00d001b400da
+m mpsadbw $4 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 02000162011d008901fd00d001b400da
+r mpsadbw $5 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 016601f00139010d018300e401d2011a
+m mpsadbw $5 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 016601f00139010d018300e401d2011a
+r mpsadbw $6 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 01970199016a020601080255010b017d
+m mpsadbw $6 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 01970199016a020601080255010b017d
+r mpsadbw $7 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 024f01a900e0021200f0026101ad00e1
+m mpsadbw $7 3f75f02d931ff9448bbf628658ed9ad7 3cc60717aefe9ef52ae9d2676d0cabfb 024f01a900e0021200f0026101ad00e1
+r mpsadbw $0 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 01e60179021900c901ee013e0049013b
+m mpsadbw $0 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 01e60179021900c901ee013e0049013b
+r mpsadbw $1 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 013f008601e201e201bb0291020c01c8
+m mpsadbw $1 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 013f008601e201e201bb0291020c01c8
+r mpsadbw $2 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 00cb02440044021c01dd01c9020c0178
+m mpsadbw $2 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 00cb02440044021c01dd01c9020c0178
+r mpsadbw $3 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 01b101a601ae013a00d7010701060064
+m mpsadbw $3 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 01b101a601ae013a00d7010701060064
+r mpsadbw $4 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 016b022d016101d601e60179021900c9
+m mpsadbw $4 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 016b022d016101d601e60179021900c9
+r mpsadbw $5 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 00c6011601760055013f008601e201e2
+m mpsadbw $5 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 00c6011601760055013f008601e201e2
+r mpsadbw $6 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 01ea0170019201fd00cb02440044021c
+m mpsadbw $6 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 01ea0170019201fd00cb02440044021c
+r mpsadbw $7 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 016601a601ce020301b101a601ae013a
+m mpsadbw $7 6edccbae02a30ffb040f7b09de34d1b3 314f4d8e330f6519851affdb5eb6b497 016601a601ce020301b101a601ae013a
+r mpsadbw $0 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 00eb00db00fc00a0009f00e300bc0198
+m mpsadbw $0 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 00eb00db00fc00a0009f00e300bc0198
+r mpsadbw $1 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 01610151014200f400f7013b00d4019c
+m mpsadbw $1 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 01610151014200f400f7013b00d4019c
+r mpsadbw $2 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 00e1006d007a00c600dd00f100c800d0
+m mpsadbw $2 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 00e1006d007a00c600dd00f100c800d0
+r mpsadbw $3 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 014a011e00f100a300d8014e013901ad
+m mpsadbw $3 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 014a011e00f100a300d8014e013901ad
+r mpsadbw $4 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 010c01d1010100e900eb00db00fc00a0
+m mpsadbw $4 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 010c01d1010100e900eb00db00fc00a0
+r mpsadbw $5 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 017802470199018101610151014200f4
+m mpsadbw $5 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 017802470199018101610151014200f4
+r mpsadbw $6 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 011c01930149016900e1006d007a00c6
+m mpsadbw $6 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 011c01930149016900e1006d007a00c6
+r mpsadbw $7 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 00d501f600d400c8014a011e00f100a3
+m mpsadbw $7 c11b7cb5c5a39777f955dba98144db9a 399727811b207d998b6870a1baeead13 00d501f600d400c8014a011e00f100a3
+r mpsadbw $0 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 015a00ba008c00fb010400f6016e0113
+m mpsadbw $0 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 015a00ba008c00fb010400f6016e0113
+r mpsadbw $1 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01ca0194011c011f0142017400e001b1
+m mpsadbw $1 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01ca0194011c011f0142017400e001b1
+r mpsadbw $2 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01c801ce015600d7008e00ba005400ef
+m mpsadbw $2 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01c801ce015600d7008e00ba005400ef
+r mpsadbw $3 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01ff01cb01490100009700a500c9010a
+m mpsadbw $3 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01ff01cb01490100009700a500c9010a
+r mpsadbw $4 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01bf00e2010a01de015a00ba008c00fb
+m mpsadbw $4 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01bf00e2010a01de015a00ba008c00fb
+r mpsadbw $5 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01c701b600e201b801ca0194011c011f
+m mpsadbw $5 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01c701b600e201b801ca0194011c011f
+r mpsadbw $6 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 015d018a0114017e01c801ce015600d7
+m mpsadbw $6 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 015d018a0114017e01c801ce015600d7
+r mpsadbw $7 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01b601310183024101ff01cb01490100
+m mpsadbw $7 947ffeb078a9cd64475cfe515e2873b7 aeea905e01bf2020199da2a59ec1549c 01b601310183024101ff01cb01490100
+r mpsadbw $0 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 00ac0134017001d0017500cb01520150
+m mpsadbw $0 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 00ac0134017001d0017500cb01520150
+r mpsadbw $1 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 01a20194025e0194026301c3018201f0
+m mpsadbw $1 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 01a20194025e0194026301c3018201f0
+r mpsadbw $2 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 0180013e015e023200c7023500f80136
+m mpsadbw $2 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 0180013e015e023200c7023500f80136
+r mpsadbw $3 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 0077010f00a10175012a010c012d00a1
+m mpsadbw $3 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 0077010f00a10175012a010c012d00a1
+r mpsadbw $4 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 00f000d400df00d900ac0134017001d0
+m mpsadbw $4 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 00f000d400df00d900ac0134017001d0
+r mpsadbw $5 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 014001400127018101a20194025e0194
+m mpsadbw $5 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 014001400127018101a20194025e0194
+r mpsadbw $6 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 00d400f200f500e30180013e015e0232
+m mpsadbw $6 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 00d400f200f500e30180013e015e0232
+r mpsadbw $7 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 013d0121012600f00077010f00a10175
+m mpsadbw $7 43544e09b843ec70cbf25eec90ec5637 ee94859082788a5a098610d4263a635e 013d0121012600f00077010f00a10175
+r mpsadbw $0 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 01c201d001e50090017000d200c10105
+m mpsadbw $0 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 01c201d001e50090017000d200c10105
+r mpsadbw $1 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 013a017601e700c801a0010200ff00c3
+m mpsadbw $1 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 013a017601e700c801a0010200ff00c3
+r mpsadbw $2 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 018901910266005701d5015501200188
+m mpsadbw $2 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 018901910266005701d5015501200188
+r mpsadbw $3 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 015801ce0209005e0200011600f50149
+m mpsadbw $3 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 015801ce0209005e0200011600f50149
+r mpsadbw $4 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 019800e201fa01a701c201d001e50090
+m mpsadbw $4 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 019800e201fa01a701c201d001e50090
+r mpsadbw $5 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 019a016a01b8013f013a017601e700c8
+m mpsadbw $5 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 019a016a01b8013f013a017601e700c8
+r mpsadbw $6 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 02190133027d01b80189019102660057
+m mpsadbw $6 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 02190133027d01b80189019102660057
+r mpsadbw $7 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 01c20160023e0179015801ce0209005e
+m mpsadbw $7 2ae5662e21fd31455fe17968339c4046 53e1018239d5f9f538ef36186c659784 01c20160023e0179015801ce0209005e
+r mpsadbw $0 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 0127019801400128019900e4018a00a2
+m mpsadbw $0 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 0127019801400128019900e4018a00a2
+r mpsadbw $1 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 012800e900ff013b012e01830169018d
+m mpsadbw $1 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 012800e900ff013b012e01830169018d
+r mpsadbw $2 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 00a600fd00a500ed00fe00d100e500d7
+m mpsadbw $2 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 00a600fd00a500ed00fe00d100e500d7
+r mpsadbw $3 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 00c70074007200be003300bc008000fe
+m mpsadbw $3 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 00c70074007200be003300bc008000fe
+r mpsadbw $4 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 0200017801dc014f0127019801400128
+m mpsadbw $4 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 0200017801dc014f0127019801400128
+r mpsadbw $5 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 010500c700e100e8012800e900ff013b
+m mpsadbw $5 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 010500c700e100e8012800e900ff013b
+r mpsadbw $6 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 01370133014100b400a600fd00a500ed
+m mpsadbw $6 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 01370133014100b400a600fd00a500ed
+r mpsadbw $7 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 019e0120008200ad00c70074007200be
+m mpsadbw $7 a580448a4d62d88fe0f7c9b06445ed0f 3a1cffa2c264a79b82a3915f8f4eab3b 019e0120008200ad00c70074007200be
+r mpsadbw $0 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 01770191016101b401170207011501ae
+m mpsadbw $0 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 01770191016101b401170207011501ae
+r mpsadbw $1 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 00f300f50179017600e901ad01db01ec
+m mpsadbw $1 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 00f300f50179017600e901ad01db01ec
+r mpsadbw $2 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 016b0143010b018c01970231015701bc
+m mpsadbw $2 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 016b0143010b018c01970231015701bc
+r mpsadbw $3 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 0153018301c3010800fd017101cb01b2
+m mpsadbw $3 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 0153018301c3010800fd017101cb01b2
+r mpsadbw $4 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 010f018400fe01af01770191016101b4
+m mpsadbw $4 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 010f018400fe01af01770191016101b4
+r mpsadbw $5 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 0165010800b2012b00f300f501790176
+m mpsadbw $5 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 0165010800b2012b00f300f501790176
+r mpsadbw $6 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 014901ea01820127016b0143010b018c
+m mpsadbw $6 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 014901ea01820127016b0143010b018c
+r mpsadbw $7 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 014b00d20112016d0153018301c30108
+m mpsadbw $7 0f6fe389dbfe1dfc2afeccb03ff219be 00937d5bbab0d1f8c4709b93a9025dae 014b00d20112016d0153018301c30108
+r mpsadbw $0 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 012d00ef00ff010c015a007e008900bb
+m mpsadbw $0 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 012d00ef00ff010c015a007e008900bb
+r mpsadbw $1 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 010600fc021001db00f30139012001d4
+m mpsadbw $1 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 010600fc021001db00f30139012001d4
+r mpsadbw $2 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 0194015c018801b501c101a5013a00f8
+m mpsadbw $2 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 0194015c018801b501c101a5013a00f8
+r mpsadbw $3 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 01ed01dd013f00d0021a015001770151
+m mpsadbw $3 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 01ed01dd013f00d0021a015001770151
+r mpsadbw $4 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 012b0177013e00f8012d00ef00ff010c
+m mpsadbw $4 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 012b0177013e00f8012d00ef00ff010c
+r mpsadbw $5 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 02100156011d01d1010600fc021001db
+m mpsadbw $5 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 02100156011d01d1010600fc021001db
+r mpsadbw $6 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 00f000ea0133016b0194015c018801b5
+m mpsadbw $6 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 00f000ea0133016b0194015c018801b5
+r mpsadbw $7 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 00f90137018c00e401ed01dd013f00d0
+m mpsadbw $7 c6003f97645d3b351ac3fe54dfb07f80 ff907719bd46b2b9d820d2a2d68c670a 00f90137018c00e401ed01dd013f00d0
+r mpsadbw $0 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 00be006900c6007900f90184008f00f9
+m mpsadbw $0 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 00be006900c6007900f90184008f00f9
+r mpsadbw $1 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 00ff00c2010b00ba016201a3005801a0
+m mpsadbw $1 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 00ff00c2010b00ba016201a3005801a0
+r mpsadbw $2 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 010f011400db013c016a00e1012401c6
+m mpsadbw $2 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 010f011400db013c016a00e1012401c6
+r mpsadbw $3 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 014801170140012d00c5018c01a70117
+m mpsadbw $3 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 014801170140012d00c5018c01a70117
+r mpsadbw $4 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 010c016d006e008900be006900c60079
+m mpsadbw $4 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 010c016d006e008900be006900c60079
+r mpsadbw $5 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 01b3013000bf011600ff00c2010b00ba
+m mpsadbw $5 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 01b3013000bf011600ff00c2010b00ba
+r mpsadbw $6 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 01ab00de013b013e010f011400db013c
+m mpsadbw $6 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 01ab00de013b013e010f011400db013c
+r mpsadbw $7 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 00f6019901000113014801170140012d
+m mpsadbw $7 257d5420870c6fe98a11d989618adc81 9460e74966b1888a9b80b17733f9867b 00f6019901000113014801170140012d
+r mpsadbw $0 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 013c015c01ee007f00d10145017b0174
+m mpsadbw $0 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 013c015c01ee007f00d10145017b0174
+r mpsadbw $1 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 01c50107016f01d600ca00c0018e0159
+m mpsadbw $1 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 01c50107016f01d600ca00c0018e0159
+r mpsadbw $2 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 016e014201c000c100c101170153015a
+m mpsadbw $2 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 016e014201c000c100c101170153015a
+r mpsadbw $3 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 00c60120018a018d01d701ef016d012e
+m mpsadbw $3 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 00c60120018a018d01d701ef016d012e
+r mpsadbw $4 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 02020155019301d2013c015c01ee007f
+m mpsadbw $4 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 02020155019301d2013c015c01ee007f
+r mpsadbw $5 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 00bb01a4011800af01c50107016f01d6
+m mpsadbw $5 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 00bb01a4011800af01c50107016f01d6
+r mpsadbw $6 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 01d4013b017901b8016e014201c000c1
+m mpsadbw $6 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 01d4013b017901b8016e014201c000c1
+r mpsadbw $7 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 014600a900b3016a00c60120018a018d
+m mpsadbw $7 88331f90dd96f5c257b6db39e08cebed 1b4fcb55517e8d16e95cb5fddb54752c 014600a900b3016a00c60120018a018d
+r mpsadbw $0 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 012e01e1013f014700bf018600bf01b7
+m mpsadbw $0 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 012e01e1013f014700bf018600bf01b7
+r mpsadbw $1 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 016a0161007d009b013d012201730133
+m mpsadbw $1 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 016a0161007d009b013d012201730133
+r mpsadbw $2 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 00dc022100a7013b014301d801a50211
+m mpsadbw $2 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 00dc022100a7013b014301d801a50211
+r mpsadbw $3 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 017e0147008f00db015b00fe014f013b
+m mpsadbw $3 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 017e0147008f00db015b00fe014f013b
+r mpsadbw $4 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 01e80179011b0261012e01e1013f0147
+m mpsadbw $4 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 01e80179011b0261012e01e1013f0147
+r mpsadbw $5 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 010a00eb01a3014d016a0161007d009b
+m mpsadbw $5 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 010a00eb01a3014d016a0161007d009b
+r mpsadbw $6 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 0200008301d301bf00dc022100a7013b
+m mpsadbw $6 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 0200008301d301bf00dc022100a7013b
+r mpsadbw $7 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 00f6010501c10113017e0147008f00db
+m mpsadbw $7 4a6e9b540588086c5d7c7f5178c26aef f1a81eaa1b37fe0a9e805822eaa9f14a 00f6010501c10113017e0147008f00db
+r mpsadbw $0 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 006600e001d200f3018701e000e201c2
+m mpsadbw $0 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 006600e001d200f3018701e000e201c2
+r mpsadbw $1 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 008100dd01e900e2012a01f700eb0165
+m mpsadbw $1 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 008100dd01e900e2012a01f700eb0165
+r mpsadbw $2 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 015b015101590158009e01db014d0145
+m mpsadbw $2 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 015b015101590158009e01db014d0145
+r mpsadbw $3 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 01b50167019f012200d8022100ed01a3
+m mpsadbw $3 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 01b50167019f012200d8022100ed01a3
+r mpsadbw $4 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 020c01a7018900ef006600e001d200f3
+m mpsadbw $4 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 020c01a7018900ef006600e001d200f3
+r mpsadbw $5 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 01bf015a013c012a008100dd01e900e2
+m mpsadbw $5 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 01bf015a013c012a008100dd01e900e2
+r mpsadbw $6 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 00f5013c0124018e015b015101590158
+m mpsadbw $6 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 00f5013c0124018e015b015101590158
+r mpsadbw $7 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 00f90120014801ec01b50167019f0122
+m mpsadbw $7 c979c4d6986de594783141be463913b3 70b9dcb55f6a161196b818d27e05b600 00f90120014801ec01b50167019f0122
+r mpsadbw $0 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 01a500eb00f9013a0195002b0129010d
+m mpsadbw $0 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 01a500eb00f9013a0195002b0129010d
+r mpsadbw $1 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 0129011f009901120119008700c30085
+m mpsadbw $1 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 0129011f009901120119008700c30085
+r mpsadbw $2 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 0177005b014500e4016100ed019f018d
+m mpsadbw $2 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 0177005b014500e4016100ed019f018d
+r mpsadbw $3 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 013e00e600d00113012e009000cc009e
+m mpsadbw $3 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 013e00e600d00113012e009000cc009e
+r mpsadbw $4 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 01f400d5011201b201a500eb00f9013a
+m mpsadbw $4 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 01f400d5011201b201a500eb00f9013a
+r mpsadbw $5 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 0178011900d601320129011f00990112
+m mpsadbw $5 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 0178011900d601320129011f00990112
+r mpsadbw $6 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 01ac009301bc01780177005b014500e4
+m mpsadbw $6 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 01ac009301bc01780177005b014500e4
+r mpsadbw $7 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 018d00e001170133013e00e600d00113
+m mpsadbw $7 60a2968434d1c8e6849f9d6b65fda366 f5cc01e0baa312d8adcf70f7b073807b 018d00e001170133013e00e600d00113
+r mpsadbw $0 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 01f10146027800ff01e4017e014e02b9
+m mpsadbw $0 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 01f10146027800ff01e4017e014e02b9
+r mpsadbw $1 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 00f501b6019a0169014801de01540157
+m mpsadbw $1 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 00f501b6019a0169014801de01540157
+r mpsadbw $2 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 01af01300210011d01b801e4007c02a3
+m mpsadbw $2 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 01af01300210011d01b801e4007c02a3
+r mpsadbw $3 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 0013014a018401cd016c0184022e0123
+m mpsadbw $3 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 0013014a018401cd016c0184022e0123
+r mpsadbw $4 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 0205012e0178014e01f10146027800ff
+m mpsadbw $4 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 0205012e0178014e01f10146027800ff
+r mpsadbw $5 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 0145011400e200e800f501b6019a0169
+m mpsadbw $5 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 0145011400e200e800f501b6019a0169
+r mpsadbw $6 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 019d00f0014c013e01af01300210011d
+m mpsadbw $6 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 019d00f0014c013e01af01300210011d
+r mpsadbw $7 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 011d019c01bc01740013014a018401cd
+m mpsadbw $7 6a330ec87541ec0d5d931043f218d534 dc2f8a99c86c2e0bbf93dc7e9eff0ae7 011d019c01bc01740013014a018401cd
+r mpsadbw $0 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 00c901a80154015201340184010700f5
+m mpsadbw $0 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 00c901a80154015201340184010700f5
+r mpsadbw $1 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 017401eb021901250081015f01c600dc
+m mpsadbw $1 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 017401eb021901250081015f01c600dc
+r mpsadbw $2 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 0149008e0162018001460054018b01c5
+m mpsadbw $2 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 0149008e0162018001460054018b01c5
+r mpsadbw $3 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 010201c501af01ad0169019d00b400d0
+m mpsadbw $3 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 010201c501af01ad0169019d00b400d0
+r mpsadbw $4 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 008b0104012800ac00c901a801540152
+m mpsadbw $4 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 008b0104012800ac00c901a801540152
+r mpsadbw $5 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 0162012901fb01f5017401eb02190125
+m mpsadbw $5 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 0162012901fb01f5017401eb02190125
+r mpsadbw $6 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 01cb0156011c01560149008e01620180
+m mpsadbw $6 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 01cb0156011c01560149008e01620180
+r mpsadbw $7 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 005800a1011f010d010201c501af01ad
+m mpsadbw $7 45792610f6488fb6dfd9143408986649 812c724b2353a655a8ced85364b6116f 005800a1011f010d010201c501af01ad
diff --git a/main/none/tests/amd64/sse4-64.stdout.exp-older-glibc b/main/none/tests/amd64/sse4-64.stdout.exp-older-glibc
new file mode 100644
index 0000000..d3fb8ea
--- /dev/null
+++ b/main/none/tests/amd64/sse4-64.stdout.exp-older-glibc
@@ -0,0 +1,4726 @@
+r blendpd $0 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 7d6528c5fa956a0d69c3e9a6af27d13b
+m blendpd $0 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 7d6528c5fa956a0d69c3e9a6af27d13b
+r blendpd $1 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 7d6528c5fa956a0d98f24a4984175700
+m blendpd $1 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 7d6528c5fa956a0d98f24a4984175700
+r blendpd $2 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 5175e39d19c9ca1e69c3e9a6af27d13b
+m blendpd $2 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 5175e39d19c9ca1e69c3e9a6af27d13b
+r blendpd $3 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 5175e39d19c9ca1e98f24a4984175700
+m blendpd $3 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 5175e39d19c9ca1e98f24a4984175700
+r blendpd $0 60b160857d45c48447b8d8c0eeef1e50 b6d2fb5aa7bc5127fe9915e556a044b2 b6d2fb5aa7bc5127fe9915e556a044b2
+m blendpd $0 60b160857d45c48447b8d8c0eeef1e50 b6d2fb5aa7bc5127fe9915e556a044b2 b6d2fb5aa7bc5127fe9915e556a044b2
+r blendpd $1 60b160857d45c48447b8d8c0eeef1e50 b6d2fb5aa7bc5127fe9915e556a044b2 b6d2fb5aa7bc512747b8d8c0eeef1e50
+m blendpd $1 60b160857d45c48447b8d8c0eeef1e50 b6d2fb5aa7bc5127fe9915e556a044b2 b6d2fb5aa7bc512747b8d8c0eeef1e50
+r blendpd $2 60b160857d45c48447b8d8c0eeef1e50 b6d2fb5aa7bc5127fe9915e556a044b2 60b160857d45c484fe9915e556a044b2
+m blendpd $2 60b160857d45c48447b8d8c0eeef1e50 b6d2fb5aa7bc5127fe9915e556a044b2 60b160857d45c484fe9915e556a044b2
+r blendpd $3 60b160857d45c48447b8d8c0eeef1e50 b6d2fb5aa7bc5127fe9915e556a044b2 60b160857d45c48447b8d8c0eeef1e50
+m blendpd $3 60b160857d45c48447b8d8c0eeef1e50 b6d2fb5aa7bc5127fe9915e556a044b2 60b160857d45c48447b8d8c0eeef1e50
+r blendpd $0 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 065d77195d623e6b842adc6450659e17
+m blendpd $0 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 065d77195d623e6b842adc6450659e17
+r blendpd $1 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 065d77195d623e6b399182c2dbcc2d38
+m blendpd $1 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 065d77195d623e6b399182c2dbcc2d38
+r blendpd $2 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 19a348215c3a67fd842adc6450659e17
+m blendpd $2 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 19a348215c3a67fd842adc6450659e17
+r blendpd $3 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 19a348215c3a67fd399182c2dbcc2d38
+m blendpd $3 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 19a348215c3a67fd399182c2dbcc2d38
+r blendpd $0 d89998df5035ed364a4bc43968bc40e5 cb509970b8136c85d740b80eb7839b97 cb509970b8136c85d740b80eb7839b97
+m blendpd $0 d89998df5035ed364a4bc43968bc40e5 cb509970b8136c85d740b80eb7839b97 cb509970b8136c85d740b80eb7839b97
+r blendpd $1 d89998df5035ed364a4bc43968bc40e5 cb509970b8136c85d740b80eb7839b97 cb509970b8136c854a4bc43968bc40e5
+m blendpd $1 d89998df5035ed364a4bc43968bc40e5 cb509970b8136c85d740b80eb7839b97 cb509970b8136c854a4bc43968bc40e5
+r blendpd $2 d89998df5035ed364a4bc43968bc40e5 cb509970b8136c85d740b80eb7839b97 d89998df5035ed36d740b80eb7839b97
+m blendpd $2 d89998df5035ed364a4bc43968bc40e5 cb509970b8136c85d740b80eb7839b97 d89998df5035ed36d740b80eb7839b97
+r blendpd $3 d89998df5035ed364a4bc43968bc40e5 cb509970b8136c85d740b80eb7839b97 d89998df5035ed364a4bc43968bc40e5
+m blendpd $3 d89998df5035ed364a4bc43968bc40e5 cb509970b8136c85d740b80eb7839b97 d89998df5035ed364a4bc43968bc40e5
+r blendpd $0 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d 5ff85bc9535c191fd3a727d1a705f65d
+m blendpd $0 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d 5ff85bc9535c191fd3a727d1a705f65d
+r blendpd $1 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d 5ff85bc9535c191f56b01a12b0ca1583
+m blendpd $1 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d 5ff85bc9535c191f56b01a12b0ca1583
+r blendpd $2 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d f9dd4a29f8c093dbd3a727d1a705f65d
+m blendpd $2 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d f9dd4a29f8c093dbd3a727d1a705f65d
+r blendpd $3 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d f9dd4a29f8c093db56b01a12b0ca1583
+m blendpd $3 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d f9dd4a29f8c093db56b01a12b0ca1583
+r blendpd $0 d8bc5c6dee699597398e0039cf03663d 20a1bb92cbc97fe8542da4983df76c96 20a1bb92cbc97fe8542da4983df76c96
+m blendpd $0 d8bc5c6dee699597398e0039cf03663d 20a1bb92cbc97fe8542da4983df76c96 20a1bb92cbc97fe8542da4983df76c96
+r blendpd $1 d8bc5c6dee699597398e0039cf03663d 20a1bb92cbc97fe8542da4983df76c96 20a1bb92cbc97fe8398e0039cf03663d
+m blendpd $1 d8bc5c6dee699597398e0039cf03663d 20a1bb92cbc97fe8542da4983df76c96 20a1bb92cbc97fe8398e0039cf03663d
+r blendpd $2 d8bc5c6dee699597398e0039cf03663d 20a1bb92cbc97fe8542da4983df76c96 d8bc5c6dee699597542da4983df76c96
+m blendpd $2 d8bc5c6dee699597398e0039cf03663d 20a1bb92cbc97fe8542da4983df76c96 d8bc5c6dee699597542da4983df76c96
+r blendpd $3 d8bc5c6dee699597398e0039cf03663d 20a1bb92cbc97fe8542da4983df76c96 d8bc5c6dee699597398e0039cf03663d
+m blendpd $3 d8bc5c6dee699597398e0039cf03663d 20a1bb92cbc97fe8542da4983df76c96 d8bc5c6dee699597398e0039cf03663d
+r blendpd $0 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e 6897b536bbe4da8a369dab4f9465b86e
+m blendpd $0 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e 6897b536bbe4da8a369dab4f9465b86e
+r blendpd $1 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e 6897b536bbe4da8acfaff39be272ef40
+m blendpd $1 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e 6897b536bbe4da8acfaff39be272ef40
+r blendpd $2 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e d182c916cebc2e17369dab4f9465b86e
+m blendpd $2 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e d182c916cebc2e17369dab4f9465b86e
+r blendpd $3 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e d182c916cebc2e17cfaff39be272ef40
+m blendpd $3 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e d182c916cebc2e17cfaff39be272ef40
+r blendpd $0 407b8d9035449b06f4e06e2205236eb7 95264321bf3b68b255c2b9e2c95c9810 95264321bf3b68b255c2b9e2c95c9810
+m blendpd $0 407b8d9035449b06f4e06e2205236eb7 95264321bf3b68b255c2b9e2c95c9810 95264321bf3b68b255c2b9e2c95c9810
+r blendpd $1 407b8d9035449b06f4e06e2205236eb7 95264321bf3b68b255c2b9e2c95c9810 95264321bf3b68b2f4e06e2205236eb7
+m blendpd $1 407b8d9035449b06f4e06e2205236eb7 95264321bf3b68b255c2b9e2c95c9810 95264321bf3b68b2f4e06e2205236eb7
+r blendpd $2 407b8d9035449b06f4e06e2205236eb7 95264321bf3b68b255c2b9e2c95c9810 407b8d9035449b0655c2b9e2c95c9810
+m blendpd $2 407b8d9035449b06f4e06e2205236eb7 95264321bf3b68b255c2b9e2c95c9810 407b8d9035449b0655c2b9e2c95c9810
+r blendpd $3 407b8d9035449b06f4e06e2205236eb7 95264321bf3b68b255c2b9e2c95c9810 407b8d9035449b06f4e06e2205236eb7
+m blendpd $3 407b8d9035449b06f4e06e2205236eb7 95264321bf3b68b255c2b9e2c95c9810 407b8d9035449b06f4e06e2205236eb7
+r blendpd $0 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 019963bf7459630b8d69483df7e8c6a9
+m blendpd $0 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 019963bf7459630b8d69483df7e8c6a9
+r blendpd $1 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 019963bf7459630b84ededbc53239dcf
+m blendpd $1 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 019963bf7459630b84ededbc53239dcf
+r blendpd $2 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 81f2a547be8d18118d69483df7e8c6a9
+m blendpd $2 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 81f2a547be8d18118d69483df7e8c6a9
+r blendpd $3 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 81f2a547be8d181184ededbc53239dcf
+m blendpd $3 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 81f2a547be8d181184ededbc53239dcf
+r blendpd $0 f0350ca70523e0e45ba1ec54e87d39b3 0a3e0f7c75cb0842b95ed64d3b13ff64 0a3e0f7c75cb0842b95ed64d3b13ff64
+m blendpd $0 f0350ca70523e0e45ba1ec54e87d39b3 0a3e0f7c75cb0842b95ed64d3b13ff64 0a3e0f7c75cb0842b95ed64d3b13ff64
+r blendpd $1 f0350ca70523e0e45ba1ec54e87d39b3 0a3e0f7c75cb0842b95ed64d3b13ff64 0a3e0f7c75cb08425ba1ec54e87d39b3
+m blendpd $1 f0350ca70523e0e45ba1ec54e87d39b3 0a3e0f7c75cb0842b95ed64d3b13ff64 0a3e0f7c75cb08425ba1ec54e87d39b3
+r blendpd $2 f0350ca70523e0e45ba1ec54e87d39b3 0a3e0f7c75cb0842b95ed64d3b13ff64 f0350ca70523e0e4b95ed64d3b13ff64
+m blendpd $2 f0350ca70523e0e45ba1ec54e87d39b3 0a3e0f7c75cb0842b95ed64d3b13ff64 f0350ca70523e0e4b95ed64d3b13ff64
+r blendpd $3 f0350ca70523e0e45ba1ec54e87d39b3 0a3e0f7c75cb0842b95ed64d3b13ff64 f0350ca70523e0e45ba1ec54e87d39b3
+m blendpd $3 f0350ca70523e0e45ba1ec54e87d39b3 0a3e0f7c75cb0842b95ed64d3b13ff64 f0350ca70523e0e45ba1ec54e87d39b3
+r blendps $0 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c55f1c9202b76ddefcb0ebfe6e
+m blendps $0 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c55f1c9202b76ddefcb0ebfe6e
+r blendps $1 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c55f1c9202b76ddefce13dfe91
+m blendps $1 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c55f1c9202b76ddefce13dfe91
+r blendps $2 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c55f1c920254cae7d5b0ebfe6e
+m blendps $2 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c55f1c920254cae7d5b0ebfe6e
+r blendps $3 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c55f1c920254cae7d5e13dfe91
+m blendps $3 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c55f1c920254cae7d5e13dfe91
+r blendps $4 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c5a893312ab76ddefcb0ebfe6e
+m blendps $4 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c5a893312ab76ddefcb0ebfe6e
+r blendps $5 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c5a893312ab76ddefce13dfe91
+m blendps $5 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c5a893312ab76ddefce13dfe91
+r blendps $6 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c5a893312a54cae7d5b0ebfe6e
+m blendps $6 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c5a893312a54cae7d5b0ebfe6e
+r blendps $7 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c5a893312a54cae7d5e13dfe91
+m blendps $7 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 0a5f45c5a893312a54cae7d5e13dfe91
+r blendps $8 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1c5f1c9202b76ddefcb0ebfe6e
+m blendps $8 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1c5f1c9202b76ddefcb0ebfe6e
+r blendps $9 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1c5f1c9202b76ddefce13dfe91
+m blendps $9 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1c5f1c9202b76ddefce13dfe91
+r blendps $10 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1c5f1c920254cae7d5b0ebfe6e
+m blendps $10 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1c5f1c920254cae7d5b0ebfe6e
+r blendps $11 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1c5f1c920254cae7d5e13dfe91
+m blendps $11 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1c5f1c920254cae7d5e13dfe91
+r blendps $12 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1ca893312ab76ddefcb0ebfe6e
+m blendps $12 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1ca893312ab76ddefcb0ebfe6e
+r blendps $13 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1ca893312ab76ddefce13dfe91
+m blendps $13 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1ca893312ab76ddefce13dfe91
+r blendps $14 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1ca893312a54cae7d5b0ebfe6e
+m blendps $14 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1ca893312a54cae7d5b0ebfe6e
+r blendps $15 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1ca893312a54cae7d5e13dfe91
+m blendps $15 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e e98ebd1ca893312a54cae7d5e13dfe91
+r blendps $0 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104ced83ff86262dd37727c80f3
+m blendps $0 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104ced83ff86262dd37727c80f3
+r blendps $1 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104ced83ff86262dd375a70a792
+m blendps $1 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104ced83ff86262dd375a70a792
+r blendps $2 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104ced83ff84d325b2d727c80f3
+m blendps $2 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104ced83ff84d325b2d727c80f3
+r blendps $3 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104ced83ff84d325b2d5a70a792
+m blendps $3 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104ced83ff84d325b2d5a70a792
+r blendps $4 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104406845906262dd37727c80f3
+m blendps $4 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104406845906262dd37727c80f3
+r blendps $5 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104406845906262dd375a70a792
+m blendps $5 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104406845906262dd375a70a792
+r blendps $6 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104406845904d325b2d727c80f3
+m blendps $6 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104406845904d325b2d727c80f3
+r blendps $7 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104406845904d325b2d5a70a792
+m blendps $7 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 5f490104406845904d325b2d5a70a792
+r blendps $8 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713ced83ff86262dd37727c80f3
+m blendps $8 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713ced83ff86262dd37727c80f3
+r blendps $9 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713ced83ff86262dd375a70a792
+m blendps $9 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713ced83ff86262dd375a70a792
+r blendps $10 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713ced83ff84d325b2d727c80f3
+m blendps $10 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713ced83ff84d325b2d727c80f3
+r blendps $11 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713ced83ff84d325b2d5a70a792
+m blendps $11 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713ced83ff84d325b2d5a70a792
+r blendps $12 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713406845906262dd37727c80f3
+m blendps $12 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713406845906262dd37727c80f3
+r blendps $13 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713406845906262dd375a70a792
+m blendps $13 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713406845906262dd375a70a792
+r blendps $14 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713406845904d325b2d727c80f3
+m blendps $14 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713406845904d325b2d727c80f3
+r blendps $15 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713406845904d325b2d5a70a792
+m blendps $15 c84ab713406845904d325b2d5a70a792 5f490104ced83ff86262dd37727c80f3 c84ab713406845904d325b2d5a70a792
+r blendps $0 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da65c8c49d096084deb9ed0411e
+m blendps $0 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da65c8c49d096084deb9ed0411e
+r blendps $1 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da65c8c49d096084deb6d21f1e5
+m blendps $1 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da65c8c49d096084deb6d21f1e5
+r blendps $2 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da65c8c49d021a6c3479ed0411e
+m blendps $2 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da65c8c49d021a6c3479ed0411e
+r blendps $3 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da65c8c49d021a6c3476d21f1e5
+m blendps $3 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da65c8c49d021a6c3476d21f1e5
+r blendps $4 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da66b2e58c196084deb9ed0411e
+m blendps $4 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da66b2e58c196084deb9ed0411e
+r blendps $5 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da66b2e58c196084deb6d21f1e5
+m blendps $5 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da66b2e58c196084deb6d21f1e5
+r blendps $6 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da66b2e58c121a6c3479ed0411e
+m blendps $6 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da66b2e58c121a6c3479ed0411e
+r blendps $7 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da66b2e58c121a6c3476d21f1e5
+m blendps $7 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 63483da66b2e58c121a6c3476d21f1e5
+r blendps $8 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f65c8c49d096084deb9ed0411e
+m blendps $8 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f65c8c49d096084deb9ed0411e
+r blendps $9 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f65c8c49d096084deb6d21f1e5
+m blendps $9 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f65c8c49d096084deb6d21f1e5
+r blendps $10 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f65c8c49d021a6c3479ed0411e
+m blendps $10 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f65c8c49d021a6c3479ed0411e
+r blendps $11 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f65c8c49d021a6c3476d21f1e5
+m blendps $11 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f65c8c49d021a6c3476d21f1e5
+r blendps $12 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f66b2e58c196084deb9ed0411e
+m blendps $12 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f66b2e58c196084deb9ed0411e
+r blendps $13 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f66b2e58c196084deb6d21f1e5
+m blendps $13 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f66b2e58c196084deb6d21f1e5
+r blendps $14 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f66b2e58c121a6c3479ed0411e
+m blendps $14 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f66b2e58c121a6c3479ed0411e
+r blendps $15 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f66b2e58c121a6c3476d21f1e5
+m blendps $15 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e e9b5f3f66b2e58c121a6c3476d21f1e5
+r blendps $0 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718a8c3ec352e2dac0350f6fd1c
+m blendps $0 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718a8c3ec352e2dac0350f6fd1c
+r blendps $1 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718a8c3ec352e2dac03395c98b4
+m blendps $1 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718a8c3ec352e2dac03395c98b4
+r blendps $2 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718a8c3ec35acf29b0f50f6fd1c
+m blendps $2 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718a8c3ec35acf29b0f50f6fd1c
+r blendps $3 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718a8c3ec35acf29b0f395c98b4
+m blendps $3 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718a8c3ec35acf29b0f395c98b4
+r blendps $4 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718c572a86a2e2dac0350f6fd1c
+m blendps $4 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718c572a86a2e2dac0350f6fd1c
+r blendps $5 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718c572a86a2e2dac03395c98b4
+m blendps $5 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718c572a86a2e2dac03395c98b4
+r blendps $6 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718c572a86aacf29b0f50f6fd1c
+m blendps $6 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718c572a86aacf29b0f50f6fd1c
+r blendps $7 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718c572a86aacf29b0f395c98b4
+m blendps $7 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c 73a8f718c572a86aacf29b0f395c98b4
+r blendps $8 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33a8c3ec352e2dac0350f6fd1c
+m blendps $8 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33a8c3ec352e2dac0350f6fd1c
+r blendps $9 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33a8c3ec352e2dac03395c98b4
+m blendps $9 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33a8c3ec352e2dac03395c98b4
+r blendps $10 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33a8c3ec35acf29b0f50f6fd1c
+m blendps $10 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33a8c3ec35acf29b0f50f6fd1c
+r blendps $11 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33a8c3ec35acf29b0f395c98b4
+m blendps $11 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33a8c3ec35acf29b0f395c98b4
+r blendps $12 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33c572a86a2e2dac0350f6fd1c
+m blendps $12 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33c572a86a2e2dac0350f6fd1c
+r blendps $13 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33c572a86a2e2dac03395c98b4
+m blendps $13 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33c572a86a2e2dac03395c98b4
+r blendps $14 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33c572a86aacf29b0f50f6fd1c
+m blendps $14 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33c572a86aacf29b0f50f6fd1c
+r blendps $15 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33c572a86aacf29b0f395c98b4
+m blendps $15 a81b6e33c572a86aacf29b0f395c98b4 73a8f718a8c3ec352e2dac0350f6fd1c a81b6e33c572a86aacf29b0f395c98b4
+r blendps $0 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac54b0966d4089b756aa3f77018
+m blendps $0 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac54b0966d4089b756aa3f77018
+r blendps $1 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac54b0966d4089b756ad82e582b
+m blendps $1 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac54b0966d4089b756ad82e582b
+r blendps $2 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac54b0966d4c9e25f72a3f77018
+m blendps $2 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac54b0966d4c9e25f72a3f77018
+r blendps $3 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac54b0966d4c9e25f72d82e582b
+m blendps $3 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac54b0966d4c9e25f72d82e582b
+r blendps $4 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac5e9bf6f37089b756aa3f77018
+m blendps $4 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac5e9bf6f37089b756aa3f77018
+r blendps $5 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac5e9bf6f37089b756ad82e582b
+m blendps $5 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac5e9bf6f37089b756ad82e582b
+r blendps $6 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac5e9bf6f37c9e25f72a3f77018
+m blendps $6 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac5e9bf6f37c9e25f72a3f77018
+r blendps $7 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac5e9bf6f37c9e25f72d82e582b
+m blendps $7 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 ecb42ac5e9bf6f37c9e25f72d82e582b
+r blendps $8 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c825344b0966d4089b756aa3f77018
+m blendps $8 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c825344b0966d4089b756aa3f77018
+r blendps $9 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c825344b0966d4089b756ad82e582b
+m blendps $9 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c825344b0966d4089b756ad82e582b
+r blendps $10 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c825344b0966d4c9e25f72a3f77018
+m blendps $10 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c825344b0966d4c9e25f72a3f77018
+r blendps $11 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c825344b0966d4c9e25f72d82e582b
+m blendps $11 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c825344b0966d4c9e25f72d82e582b
+r blendps $12 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c82534e9bf6f37089b756aa3f77018
+m blendps $12 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c82534e9bf6f37089b756aa3f77018
+r blendps $13 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c82534e9bf6f37089b756ad82e582b
+m blendps $13 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c82534e9bf6f37089b756ad82e582b
+r blendps $14 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c82534e9bf6f37c9e25f72a3f77018
+m blendps $14 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c82534e9bf6f37c9e25f72a3f77018
+r blendps $15 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c82534e9bf6f37c9e25f72d82e582b
+m blendps $15 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 61c82534e9bf6f37c9e25f72d82e582b
+r blendps $0 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad218e4ebf159ff1f240eb3e1553f
+m blendps $0 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad218e4ebf159ff1f240eb3e1553f
+r blendps $1 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad218e4ebf159ff1f240e66a2ec77
+m blendps $1 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad218e4ebf159ff1f240e66a2ec77
+r blendps $2 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad218e4ebf15956428c5ab3e1553f
+m blendps $2 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad218e4ebf15956428c5ab3e1553f
+r blendps $3 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad218e4ebf15956428c5a66a2ec77
+m blendps $3 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad218e4ebf15956428c5a66a2ec77
+r blendps $4 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad21873a2ead3ff1f240eb3e1553f
+m blendps $4 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad21873a2ead3ff1f240eb3e1553f
+r blendps $5 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad21873a2ead3ff1f240e66a2ec77
+m blendps $5 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad21873a2ead3ff1f240e66a2ec77
+r blendps $6 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad21873a2ead356428c5ab3e1553f
+m blendps $6 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad21873a2ead356428c5ab3e1553f
+r blendps $7 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad21873a2ead356428c5a66a2ec77
+m blendps $7 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 28bad21873a2ead356428c5a66a2ec77
+r blendps $8 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f071367e4ebf159ff1f240eb3e1553f
+m blendps $8 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f071367e4ebf159ff1f240eb3e1553f
+r blendps $9 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f071367e4ebf159ff1f240e66a2ec77
+m blendps $9 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f071367e4ebf159ff1f240e66a2ec77
+r blendps $10 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f071367e4ebf15956428c5ab3e1553f
+m blendps $10 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f071367e4ebf15956428c5ab3e1553f
+r blendps $11 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f071367e4ebf15956428c5a66a2ec77
+m blendps $11 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f071367e4ebf15956428c5a66a2ec77
+r blendps $12 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f07136773a2ead3ff1f240eb3e1553f
+m blendps $12 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f07136773a2ead3ff1f240eb3e1553f
+r blendps $13 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f07136773a2ead3ff1f240e66a2ec77
+m blendps $13 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f07136773a2ead3ff1f240e66a2ec77
+r blendps $14 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f07136773a2ead356428c5ab3e1553f
+m blendps $14 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f07136773a2ead356428c5ab3e1553f
+r blendps $15 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f07136773a2ead356428c5a66a2ec77
+m blendps $15 6f07136773a2ead356428c5a66a2ec77 28bad218e4ebf159ff1f240eb3e1553f 6f07136773a2ead356428c5a66a2ec77
+r blendps $0 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f0cf4ca6fee8536da9dbf68bc
+m blendps $0 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f0cf4ca6fee8536da9dbf68bc
+r blendps $1 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f0cf4ca6fee8536daffc411c4
+m blendps $1 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f0cf4ca6fee8536daffc411c4
+r blendps $2 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f0cf4ca6f2ddd9db49dbf68bc
+m blendps $2 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f0cf4ca6f2ddd9db49dbf68bc
+r blendps $3 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f0cf4ca6f2ddd9db4ffc411c4
+m blendps $3 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f0cf4ca6f2ddd9db4ffc411c4
+r blendps $4 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f00a654ebee8536da9dbf68bc
+m blendps $4 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f00a654ebee8536da9dbf68bc
+r blendps $5 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f00a654ebee8536daffc411c4
+m blendps $5 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f00a654ebee8536daffc411c4
+r blendps $6 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f00a654eb2ddd9db49dbf68bc
+m blendps $6 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f00a654eb2ddd9db49dbf68bc
+r blendps $7 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f00a654eb2ddd9db4ffc411c4
+m blendps $7 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 8404eb7f00a654eb2ddd9db4ffc411c4
+r blendps $8 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 302634370cf4ca6fee8536da9dbf68bc
+m blendps $8 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 302634370cf4ca6fee8536da9dbf68bc
+r blendps $9 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 302634370cf4ca6fee8536daffc411c4
+m blendps $9 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 302634370cf4ca6fee8536daffc411c4
+r blendps $10 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 302634370cf4ca6f2ddd9db49dbf68bc
+m blendps $10 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 302634370cf4ca6f2ddd9db49dbf68bc
+r blendps $11 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 302634370cf4ca6f2ddd9db4ffc411c4
+m blendps $11 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 302634370cf4ca6f2ddd9db4ffc411c4
+r blendps $12 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 3026343700a654ebee8536da9dbf68bc
+m blendps $12 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 3026343700a654ebee8536da9dbf68bc
+r blendps $13 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 3026343700a654ebee8536daffc411c4
+m blendps $13 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 3026343700a654ebee8536daffc411c4
+r blendps $14 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 3026343700a654eb2ddd9db49dbf68bc
+m blendps $14 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 3026343700a654eb2ddd9db49dbf68bc
+r blendps $15 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 3026343700a654eb2ddd9db4ffc411c4
+m blendps $15 3026343700a654eb2ddd9db4ffc411c4 8404eb7f0cf4ca6fee8536da9dbf68bc 3026343700a654eb2ddd9db4ffc411c4
+r blendps $0 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf726562b02dc2b39925ba7d9d67bc
+m blendps $0 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf726562b02dc2b39925ba7d9d67bc
+r blendps $1 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf726562b02dc2b39925bac1a1833d
+m blendps $1 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf726562b02dc2b39925bac1a1833d
+r blendps $2 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf726562b02dc22c810e6d7d9d67bc
+m blendps $2 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf726562b02dc22c810e6d7d9d67bc
+r blendps $3 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf726562b02dc22c810e6dc1a1833d
+m blendps $3 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf726562b02dc22c810e6dc1a1833d
+r blendps $4 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf72652c57ea2ab39925ba7d9d67bc
+m blendps $4 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf72652c57ea2ab39925ba7d9d67bc
+r blendps $5 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf72652c57ea2ab39925bac1a1833d
+m blendps $5 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf72652c57ea2ab39925bac1a1833d
+r blendps $6 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf72652c57ea2a2c810e6d7d9d67bc
+m blendps $6 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf72652c57ea2a2c810e6d7d9d67bc
+r blendps $7 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf72652c57ea2a2c810e6dc1a1833d
+m blendps $7 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc 5cdf72652c57ea2a2c810e6dc1a1833d
+r blendps $8 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f62b02dc2b39925ba7d9d67bc
+m blendps $8 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f62b02dc2b39925ba7d9d67bc
+r blendps $9 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f62b02dc2b39925bac1a1833d
+m blendps $9 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f62b02dc2b39925bac1a1833d
+r blendps $10 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f62b02dc22c810e6d7d9d67bc
+m blendps $10 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f62b02dc22c810e6d7d9d67bc
+r blendps $11 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f62b02dc22c810e6dc1a1833d
+m blendps $11 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f62b02dc22c810e6dc1a1833d
+r blendps $12 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f2c57ea2ab39925ba7d9d67bc
+m blendps $12 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f2c57ea2ab39925ba7d9d67bc
+r blendps $13 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f2c57ea2ab39925bac1a1833d
+m blendps $13 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f2c57ea2ab39925bac1a1833d
+r blendps $14 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f2c57ea2a2c810e6d7d9d67bc
+m blendps $14 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f2c57ea2a2c810e6d7d9d67bc
+r blendps $15 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f2c57ea2a2c810e6dc1a1833d
+m blendps $15 ff6f850f2c57ea2a2c810e6dc1a1833d 5cdf726562b02dc2b39925ba7d9d67bc ff6f850f2c57ea2a2c810e6dc1a1833d
+r blendps $0 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761367fac55ff28276f9a6e880c6b
+m blendps $0 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761367fac55ff28276f9a6e880c6b
+r blendps $1 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761367fac55ff28276f9ac544fd0f
+m blendps $1 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761367fac55ff28276f9ac544fd0f
+r blendps $2 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761367fac55ff2ef85b6f6e880c6b
+m blendps $2 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761367fac55ff2ef85b6f6e880c6b
+r blendps $3 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761367fac55ff2ef85b6fc544fd0f
+m blendps $3 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761367fac55ff2ef85b6fc544fd0f
+r blendps $4 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761369242e83d28276f9a6e880c6b
+m blendps $4 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761369242e83d28276f9a6e880c6b
+r blendps $5 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761369242e83d28276f9ac544fd0f
+m blendps $5 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761369242e83d28276f9ac544fd0f
+r blendps $6 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761369242e83d2ef85b6f6e880c6b
+m blendps $6 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761369242e83d2ef85b6f6e880c6b
+r blendps $7 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761369242e83d2ef85b6fc544fd0f
+m blendps $7 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 0c9761369242e83d2ef85b6fc544fd0f
+r blendps $8 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d7fac55ff28276f9a6e880c6b
+m blendps $8 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d7fac55ff28276f9a6e880c6b
+r blendps $9 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d7fac55ff28276f9ac544fd0f
+m blendps $9 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d7fac55ff28276f9ac544fd0f
+r blendps $10 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d7fac55ff2ef85b6f6e880c6b
+m blendps $10 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d7fac55ff2ef85b6f6e880c6b
+r blendps $11 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d7fac55ff2ef85b6fc544fd0f
+m blendps $11 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d7fac55ff2ef85b6fc544fd0f
+r blendps $12 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d9242e83d28276f9a6e880c6b
+m blendps $12 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d9242e83d28276f9a6e880c6b
+r blendps $13 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d9242e83d28276f9ac544fd0f
+m blendps $13 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d9242e83d28276f9ac544fd0f
+r blendps $14 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d9242e83d2ef85b6f6e880c6b
+m blendps $14 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d9242e83d2ef85b6f6e880c6b
+r blendps $15 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d9242e83d2ef85b6fc544fd0f
+m blendps $15 372f015d9242e83d2ef85b6fc544fd0f 0c9761367fac55ff28276f9a6e880c6b 372f015d9242e83d2ef85b6fc544fd0f
+r blendps $0 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65e01737fd22bfa8f668c8b14f4
+m blendps $0 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65e01737fd22bfa8f668c8b14f4
+r blendps $1 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65e01737fd22bfa8f6629ba3c66
+m blendps $1 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65e01737fd22bfa8f6629ba3c66
+r blendps $2 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65e01737fd20e0f01a88c8b14f4
+m blendps $2 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65e01737fd20e0f01a88c8b14f4
+r blendps $3 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65e01737fd20e0f01a829ba3c66
+m blendps $3 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65e01737fd20e0f01a829ba3c66
+r blendps $4 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65ecef18acf2bfa8f668c8b14f4
+m blendps $4 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65ecef18acf2bfa8f668c8b14f4
+r blendps $5 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65ecef18acf2bfa8f6629ba3c66
+m blendps $5 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65ecef18acf2bfa8f6629ba3c66
+r blendps $6 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65ecef18acf0e0f01a88c8b14f4
+m blendps $6 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65ecef18acf0e0f01a88c8b14f4
+r blendps $7 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65ecef18acf0e0f01a829ba3c66
+m blendps $7 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 f078b65ecef18acf0e0f01a829ba3c66
+r blendps $8 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38d01737fd22bfa8f668c8b14f4
+m blendps $8 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38d01737fd22bfa8f668c8b14f4
+r blendps $9 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38d01737fd22bfa8f6629ba3c66
+m blendps $9 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38d01737fd22bfa8f6629ba3c66
+r blendps $10 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38d01737fd20e0f01a88c8b14f4
+m blendps $10 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38d01737fd20e0f01a88c8b14f4
+r blendps $11 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38d01737fd20e0f01a829ba3c66
+m blendps $11 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38d01737fd20e0f01a829ba3c66
+r blendps $12 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38dcef18acf2bfa8f668c8b14f4
+m blendps $12 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38dcef18acf2bfa8f668c8b14f4
+r blendps $13 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38dcef18acf2bfa8f6629ba3c66
+m blendps $13 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38dcef18acf2bfa8f6629ba3c66
+r blendps $14 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38dcef18acf0e0f01a88c8b14f4
+m blendps $14 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38dcef18acf0e0f01a88c8b14f4
+r blendps $15 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38dcef18acf0e0f01a829ba3c66
+m blendps $15 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 36b2a38dcef18acf0e0f01a829ba3c66
+r pblendw $0 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df010bf4b23b84
+m pblendw $0 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df010bf4b23b84
+r pblendw $1 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df010bf4b2fc6d
+m pblendw $1 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df010bf4b2fc6d
+r pblendw $2 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df010b090d3b84
+m pblendw $2 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df010b090d3b84
+r pblendw $3 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df010b090dfc6d
+m pblendw $3 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df010b090dfc6d
+r pblendw $4 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df7a03f4b23b84
+m pblendw $4 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df7a03f4b23b84
+r pblendw $5 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df7a03f4b2fc6d
+m pblendw $5 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df7a03f4b2fc6d
+r pblendw $6 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df7a03090d3b84
+m pblendw $6 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df7a03090d3b84
+r pblendw $7 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df7a03090dfc6d
+m pblendw $7 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e796df7a03090dfc6d
+r pblendw $8 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa92010bf4b23b84
+m pblendw $8 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa92010bf4b23b84
+r pblendw $9 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa92010bf4b2fc6d
+m pblendw $9 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa92010bf4b2fc6d
+r pblendw $10 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa92010b090d3b84
+m pblendw $10 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa92010b090d3b84
+r pblendw $11 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa92010b090dfc6d
+m pblendw $11 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa92010b090dfc6d
+r pblendw $12 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa927a03f4b23b84
+m pblendw $12 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa927a03f4b23b84
+r pblendw $13 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa927a03f4b2fc6d
+m pblendw $13 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa927a03f4b2fc6d
+r pblendw $14 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa927a03090d3b84
+m pblendw $14 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa927a03090d3b84
+r pblendw $15 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa927a03090dfc6d
+m pblendw $15 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d498492e7e7aa927a03090dfc6d
+r pblendw $16 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df010bf4b23b84
+m pblendw $16 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df010bf4b23b84
+r pblendw $17 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df010bf4b2fc6d
+m pblendw $17 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df010bf4b2fc6d
+r pblendw $18 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df010b090d3b84
+m pblendw $18 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df010b090d3b84
+r pblendw $19 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df010b090dfc6d
+m pblendw $19 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df010b090dfc6d
+r pblendw $20 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df7a03f4b23b84
+m pblendw $20 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df7a03f4b23b84
+r pblendw $21 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df7a03f4b2fc6d
+m pblendw $21 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df7a03f4b2fc6d
+r pblendw $22 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df7a03090d3b84
+m pblendw $22 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df7a03090d3b84
+r pblendw $23 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df7a03090dfc6d
+m pblendw $23 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8d96df7a03090dfc6d
+r pblendw $24 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa92010bf4b23b84
+m pblendw $24 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa92010bf4b23b84
+r pblendw $25 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa92010bf4b2fc6d
+m pblendw $25 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa92010bf4b2fc6d
+r pblendw $26 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa92010b090d3b84
+m pblendw $26 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa92010b090d3b84
+r pblendw $27 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa92010b090dfc6d
+m pblendw $27 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa92010b090dfc6d
+r pblendw $28 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa927a03f4b23b84
+m pblendw $28 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa927a03f4b23b84
+r pblendw $29 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa927a03f4b2fc6d
+m pblendw $29 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa927a03f4b2fc6d
+r pblendw $30 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa927a03090d3b84
+m pblendw $30 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa927a03090d3b84
+r pblendw $31 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa927a03090dfc6d
+m pblendw $31 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d4984920b8daa927a03090dfc6d
+r pblendw $32 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df010bf4b23b84
+m pblendw $32 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df010bf4b23b84
+r pblendw $33 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df010bf4b2fc6d
+m pblendw $33 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df010bf4b2fc6d
+r pblendw $34 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df010b090d3b84
+m pblendw $34 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df010b090d3b84
+r pblendw $35 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df010b090dfc6d
+m pblendw $35 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df010b090dfc6d
+r pblendw $36 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df7a03f4b23b84
+m pblendw $36 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df7a03f4b23b84
+r pblendw $37 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df7a03f4b2fc6d
+m pblendw $37 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df7a03f4b2fc6d
+r pblendw $38 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df7a03090d3b84
+m pblendw $38 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df7a03090d3b84
+r pblendw $39 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df7a03090dfc6d
+m pblendw $39 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e796df7a03090dfc6d
+r pblendw $40 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa92010bf4b23b84
+m pblendw $40 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa92010bf4b23b84
+r pblendw $41 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa92010bf4b2fc6d
+m pblendw $41 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa92010bf4b2fc6d
+r pblendw $42 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa92010b090d3b84
+m pblendw $42 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa92010b090d3b84
+r pblendw $43 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa92010b090dfc6d
+m pblendw $43 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa92010b090dfc6d
+r pblendw $44 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa927a03f4b23b84
+m pblendw $44 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa927a03f4b23b84
+r pblendw $45 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa927a03f4b2fc6d
+m pblendw $45 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa927a03f4b2fc6d
+r pblendw $46 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa927a03090d3b84
+m pblendw $46 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa927a03090d3b84
+r pblendw $47 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa927a03090dfc6d
+m pblendw $47 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df3e7e7aa927a03090dfc6d
+r pblendw $48 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df010bf4b23b84
+m pblendw $48 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df010bf4b23b84
+r pblendw $49 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df010bf4b2fc6d
+m pblendw $49 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df010bf4b2fc6d
+r pblendw $50 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df010b090d3b84
+m pblendw $50 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df010b090d3b84
+r pblendw $51 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df010b090dfc6d
+m pblendw $51 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df010b090dfc6d
+r pblendw $52 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df7a03f4b23b84
+m pblendw $52 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df7a03f4b23b84
+r pblendw $53 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df7a03f4b2fc6d
+m pblendw $53 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df7a03f4b2fc6d
+r pblendw $54 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df7a03090d3b84
+m pblendw $54 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df7a03090d3b84
+r pblendw $55 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df7a03090dfc6d
+m pblendw $55 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8d96df7a03090dfc6d
+r pblendw $56 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa92010bf4b23b84
+m pblendw $56 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa92010bf4b23b84
+r pblendw $57 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa92010bf4b2fc6d
+m pblendw $57 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa92010bf4b2fc6d
+r pblendw $58 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa92010b090d3b84
+m pblendw $58 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa92010b090d3b84
+r pblendw $59 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa92010b090dfc6d
+m pblendw $59 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa92010b090dfc6d
+r pblendw $60 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa927a03f4b23b84
+m pblendw $60 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa927a03f4b23b84
+r pblendw $61 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa927a03f4b2fc6d
+m pblendw $61 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa927a03f4b2fc6d
+r pblendw $62 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa927a03090d3b84
+m pblendw $62 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa927a03090d3b84
+r pblendw $63 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa927a03090dfc6d
+m pblendw $63 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6d497df30b8daa927a03090dfc6d
+r pblendw $64 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df010bf4b23b84
+m pblendw $64 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df010bf4b23b84
+r pblendw $65 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df010bf4b2fc6d
+m pblendw $65 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df010bf4b2fc6d
+r pblendw $66 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df010b090d3b84
+m pblendw $66 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df010b090d3b84
+r pblendw $67 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df010b090dfc6d
+m pblendw $67 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df010b090dfc6d
+r pblendw $68 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df7a03f4b23b84
+m pblendw $68 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df7a03f4b23b84
+r pblendw $69 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df7a03f4b2fc6d
+m pblendw $69 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df7a03f4b2fc6d
+r pblendw $70 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df7a03090d3b84
+m pblendw $70 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df7a03090d3b84
+r pblendw $71 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df7a03090dfc6d
+m pblendw $71 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e796df7a03090dfc6d
+r pblendw $72 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa92010bf4b23b84
+m pblendw $72 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa92010bf4b23b84
+r pblendw $73 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa92010bf4b2fc6d
+m pblendw $73 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa92010bf4b2fc6d
+r pblendw $74 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa92010b090d3b84
+m pblendw $74 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa92010b090d3b84
+r pblendw $75 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa92010b090dfc6d
+m pblendw $75 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa92010b090dfc6d
+r pblendw $76 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa927a03f4b23b84
+m pblendw $76 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa927a03f4b23b84
+r pblendw $77 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa927a03f4b2fc6d
+m pblendw $77 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa927a03f4b2fc6d
+r pblendw $78 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa927a03090d3b84
+m pblendw $78 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa927a03090d3b84
+r pblendw $79 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa927a03090dfc6d
+m pblendw $79 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a098492e7e7aa927a03090dfc6d
+r pblendw $80 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df010bf4b23b84
+m pblendw $80 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df010bf4b23b84
+r pblendw $81 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df010bf4b2fc6d
+m pblendw $81 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df010bf4b2fc6d
+r pblendw $82 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df010b090d3b84
+m pblendw $82 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df010b090d3b84
+r pblendw $83 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df010b090dfc6d
+m pblendw $83 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df010b090dfc6d
+r pblendw $84 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df7a03f4b23b84
+m pblendw $84 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df7a03f4b23b84
+r pblendw $85 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df7a03f4b2fc6d
+m pblendw $85 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df7a03f4b2fc6d
+r pblendw $86 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df7a03090d3b84
+m pblendw $86 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df7a03090d3b84
+r pblendw $87 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df7a03090dfc6d
+m pblendw $87 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8d96df7a03090dfc6d
+r pblendw $88 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa92010bf4b23b84
+m pblendw $88 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa92010bf4b23b84
+r pblendw $89 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa92010bf4b2fc6d
+m pblendw $89 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa92010bf4b2fc6d
+r pblendw $90 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa92010b090d3b84
+m pblendw $90 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa92010b090d3b84
+r pblendw $91 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa92010b090dfc6d
+m pblendw $91 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa92010b090dfc6d
+r pblendw $92 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa927a03f4b23b84
+m pblendw $92 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa927a03f4b23b84
+r pblendw $93 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa927a03f4b2fc6d
+m pblendw $93 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa927a03f4b2fc6d
+r pblendw $94 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa927a03090d3b84
+m pblendw $94 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa927a03090d3b84
+r pblendw $95 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa927a03090dfc6d
+m pblendw $95 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a0984920b8daa927a03090dfc6d
+r pblendw $96 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df010bf4b23b84
+m pblendw $96 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df010bf4b23b84
+r pblendw $97 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df010bf4b2fc6d
+m pblendw $97 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df010bf4b2fc6d
+r pblendw $98 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df010b090d3b84
+m pblendw $98 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df010b090d3b84
+r pblendw $99 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df010b090dfc6d
+m pblendw $99 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df010b090dfc6d
+r pblendw $100 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df7a03f4b23b84
+m pblendw $100 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df7a03f4b23b84
+r pblendw $101 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df7a03f4b2fc6d
+m pblendw $101 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df7a03f4b2fc6d
+r pblendw $102 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df7a03090d3b84
+m pblendw $102 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df7a03090d3b84
+r pblendw $103 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df7a03090dfc6d
+m pblendw $103 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e796df7a03090dfc6d
+r pblendw $104 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa92010bf4b23b84
+m pblendw $104 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa92010bf4b23b84
+r pblendw $105 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa92010bf4b2fc6d
+m pblendw $105 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa92010bf4b2fc6d
+r pblendw $106 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa92010b090d3b84
+m pblendw $106 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa92010b090d3b84
+r pblendw $107 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa92010b090dfc6d
+m pblendw $107 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa92010b090dfc6d
+r pblendw $108 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa927a03f4b23b84
+m pblendw $108 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa927a03f4b23b84
+r pblendw $109 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa927a03f4b2fc6d
+m pblendw $109 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa927a03f4b2fc6d
+r pblendw $110 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa927a03090d3b84
+m pblendw $110 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa927a03090d3b84
+r pblendw $111 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa927a03090dfc6d
+m pblendw $111 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df3e7e7aa927a03090dfc6d
+r pblendw $112 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df010bf4b23b84
+m pblendw $112 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df010bf4b23b84
+r pblendw $113 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df010bf4b2fc6d
+m pblendw $113 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df010bf4b2fc6d
+r pblendw $114 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df010b090d3b84
+m pblendw $114 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df010b090d3b84
+r pblendw $115 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df010b090dfc6d
+m pblendw $115 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df010b090dfc6d
+r pblendw $116 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df7a03f4b23b84
+m pblendw $116 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df7a03f4b23b84
+r pblendw $117 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df7a03f4b2fc6d
+m pblendw $117 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df7a03f4b2fc6d
+r pblendw $118 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df7a03090d3b84
+m pblendw $118 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df7a03090d3b84
+r pblendw $119 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df7a03090dfc6d
+m pblendw $119 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8d96df7a03090dfc6d
+r pblendw $120 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa92010bf4b23b84
+m pblendw $120 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa92010bf4b23b84
+r pblendw $121 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa92010bf4b2fc6d
+m pblendw $121 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa92010bf4b2fc6d
+r pblendw $122 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa92010b090d3b84
+m pblendw $122 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa92010b090d3b84
+r pblendw $123 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa92010b090dfc6d
+m pblendw $123 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa92010b090dfc6d
+r pblendw $124 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa927a03f4b23b84
+m pblendw $124 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa927a03f4b23b84
+r pblendw $125 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa927a03f4b2fc6d
+m pblendw $125 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa927a03f4b2fc6d
+r pblendw $126 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa927a03090d3b84
+m pblendw $126 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa927a03090d3b84
+r pblendw $127 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa927a03090dfc6d
+m pblendw $127 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 65ce6a097df30b8daa927a03090dfc6d
+r pblendw $128 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df010bf4b23b84
+m pblendw $128 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df010bf4b23b84
+r pblendw $129 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df010bf4b2fc6d
+m pblendw $129 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df010bf4b2fc6d
+r pblendw $130 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df010b090d3b84
+m pblendw $130 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df010b090d3b84
+r pblendw $131 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df010b090dfc6d
+m pblendw $131 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df010b090dfc6d
+r pblendw $132 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df7a03f4b23b84
+m pblendw $132 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df7a03f4b23b84
+r pblendw $133 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df7a03f4b2fc6d
+m pblendw $133 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df7a03f4b2fc6d
+r pblendw $134 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df7a03090d3b84
+m pblendw $134 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df7a03090d3b84
+r pblendw $135 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df7a03090dfc6d
+m pblendw $135 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e796df7a03090dfc6d
+r pblendw $136 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa92010bf4b23b84
+m pblendw $136 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa92010bf4b23b84
+r pblendw $137 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa92010bf4b2fc6d
+m pblendw $137 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa92010bf4b2fc6d
+r pblendw $138 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa92010b090d3b84
+m pblendw $138 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa92010b090d3b84
+r pblendw $139 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa92010b090dfc6d
+m pblendw $139 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa92010b090dfc6d
+r pblendw $140 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa927a03f4b23b84
+m pblendw $140 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa927a03f4b23b84
+r pblendw $141 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa927a03f4b2fc6d
+m pblendw $141 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa927a03f4b2fc6d
+r pblendw $142 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa927a03090d3b84
+m pblendw $142 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa927a03090d3b84
+r pblendw $143 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa927a03090dfc6d
+m pblendw $143 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d498492e7e7aa927a03090dfc6d
+r pblendw $144 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df010bf4b23b84
+m pblendw $144 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df010bf4b23b84
+r pblendw $145 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df010bf4b2fc6d
+m pblendw $145 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df010bf4b2fc6d
+r pblendw $146 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df010b090d3b84
+m pblendw $146 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df010b090d3b84
+r pblendw $147 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df010b090dfc6d
+m pblendw $147 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df010b090dfc6d
+r pblendw $148 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df7a03f4b23b84
+m pblendw $148 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df7a03f4b23b84
+r pblendw $149 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df7a03f4b2fc6d
+m pblendw $149 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df7a03f4b2fc6d
+r pblendw $150 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df7a03090d3b84
+m pblendw $150 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df7a03090d3b84
+r pblendw $151 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df7a03090dfc6d
+m pblendw $151 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8d96df7a03090dfc6d
+r pblendw $152 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa92010bf4b23b84
+m pblendw $152 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa92010bf4b23b84
+r pblendw $153 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa92010bf4b2fc6d
+m pblendw $153 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa92010bf4b2fc6d
+r pblendw $154 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa92010b090d3b84
+m pblendw $154 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa92010b090d3b84
+r pblendw $155 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa92010b090dfc6d
+m pblendw $155 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa92010b090dfc6d
+r pblendw $156 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa927a03f4b23b84
+m pblendw $156 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa927a03f4b23b84
+r pblendw $157 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa927a03f4b2fc6d
+m pblendw $157 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa927a03f4b2fc6d
+r pblendw $158 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa927a03090d3b84
+m pblendw $158 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa927a03090d3b84
+r pblendw $159 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa927a03090dfc6d
+m pblendw $159 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d4984920b8daa927a03090dfc6d
+r pblendw $160 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df010bf4b23b84
+m pblendw $160 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df010bf4b23b84
+r pblendw $161 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df010bf4b2fc6d
+m pblendw $161 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df010bf4b2fc6d
+r pblendw $162 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df010b090d3b84
+m pblendw $162 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df010b090d3b84
+r pblendw $163 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df010b090dfc6d
+m pblendw $163 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df010b090dfc6d
+r pblendw $164 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df7a03f4b23b84
+m pblendw $164 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df7a03f4b23b84
+r pblendw $165 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df7a03f4b2fc6d
+m pblendw $165 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df7a03f4b2fc6d
+r pblendw $166 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df7a03090d3b84
+m pblendw $166 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df7a03090d3b84
+r pblendw $167 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df7a03090dfc6d
+m pblendw $167 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e796df7a03090dfc6d
+r pblendw $168 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa92010bf4b23b84
+m pblendw $168 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa92010bf4b23b84
+r pblendw $169 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa92010bf4b2fc6d
+m pblendw $169 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa92010bf4b2fc6d
+r pblendw $170 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa92010b090d3b84
+m pblendw $170 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa92010b090d3b84
+r pblendw $171 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa92010b090dfc6d
+m pblendw $171 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa92010b090dfc6d
+r pblendw $172 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa927a03f4b23b84
+m pblendw $172 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa927a03f4b23b84
+r pblendw $173 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa927a03f4b2fc6d
+m pblendw $173 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa927a03f4b2fc6d
+r pblendw $174 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa927a03090d3b84
+m pblendw $174 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa927a03090d3b84
+r pblendw $175 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa927a03090dfc6d
+m pblendw $175 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df3e7e7aa927a03090dfc6d
+r pblendw $176 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df010bf4b23b84
+m pblendw $176 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df010bf4b23b84
+r pblendw $177 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df010bf4b2fc6d
+m pblendw $177 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df010bf4b2fc6d
+r pblendw $178 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df010b090d3b84
+m pblendw $178 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df010b090d3b84
+r pblendw $179 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df010b090dfc6d
+m pblendw $179 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df010b090dfc6d
+r pblendw $180 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df7a03f4b23b84
+m pblendw $180 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df7a03f4b23b84
+r pblendw $181 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df7a03f4b2fc6d
+m pblendw $181 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df7a03f4b2fc6d
+r pblendw $182 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df7a03090d3b84
+m pblendw $182 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df7a03090d3b84
+r pblendw $183 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df7a03090dfc6d
+m pblendw $183 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8d96df7a03090dfc6d
+r pblendw $184 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa92010bf4b23b84
+m pblendw $184 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa92010bf4b23b84
+r pblendw $185 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa92010bf4b2fc6d
+m pblendw $185 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa92010bf4b2fc6d
+r pblendw $186 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa92010b090d3b84
+m pblendw $186 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa92010b090d3b84
+r pblendw $187 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa92010b090dfc6d
+m pblendw $187 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa92010b090dfc6d
+r pblendw $188 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa927a03f4b23b84
+m pblendw $188 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa927a03f4b23b84
+r pblendw $189 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa927a03f4b2fc6d
+m pblendw $189 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa927a03f4b2fc6d
+r pblendw $190 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa927a03090d3b84
+m pblendw $190 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa927a03090d3b84
+r pblendw $191 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa927a03090dfc6d
+m pblendw $191 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436d497df30b8daa927a03090dfc6d
+r pblendw $192 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df010bf4b23b84
+m pblendw $192 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df010bf4b23b84
+r pblendw $193 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df010bf4b2fc6d
+m pblendw $193 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df010bf4b2fc6d
+r pblendw $194 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df010b090d3b84
+m pblendw $194 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df010b090d3b84
+r pblendw $195 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df010b090dfc6d
+m pblendw $195 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df010b090dfc6d
+r pblendw $196 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df7a03f4b23b84
+m pblendw $196 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df7a03f4b23b84
+r pblendw $197 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df7a03f4b2fc6d
+m pblendw $197 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df7a03f4b2fc6d
+r pblendw $198 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df7a03090d3b84
+m pblendw $198 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df7a03090d3b84
+r pblendw $199 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df7a03090dfc6d
+m pblendw $199 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e796df7a03090dfc6d
+r pblendw $200 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa92010bf4b23b84
+m pblendw $200 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa92010bf4b23b84
+r pblendw $201 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa92010bf4b2fc6d
+m pblendw $201 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa92010bf4b2fc6d
+r pblendw $202 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa92010b090d3b84
+m pblendw $202 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa92010b090d3b84
+r pblendw $203 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa92010b090dfc6d
+m pblendw $203 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa92010b090dfc6d
+r pblendw $204 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa927a03f4b23b84
+m pblendw $204 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa927a03f4b23b84
+r pblendw $205 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa927a03f4b2fc6d
+m pblendw $205 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa927a03f4b2fc6d
+r pblendw $206 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa927a03090d3b84
+m pblendw $206 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa927a03090d3b84
+r pblendw $207 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa927a03090dfc6d
+m pblendw $207 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a098492e7e7aa927a03090dfc6d
+r pblendw $208 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df010bf4b23b84
+m pblendw $208 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df010bf4b23b84
+r pblendw $209 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df010bf4b2fc6d
+m pblendw $209 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df010bf4b2fc6d
+r pblendw $210 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df010b090d3b84
+m pblendw $210 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df010b090d3b84
+r pblendw $211 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df010b090dfc6d
+m pblendw $211 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df010b090dfc6d
+r pblendw $212 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df7a03f4b23b84
+m pblendw $212 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df7a03f4b23b84
+r pblendw $213 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df7a03f4b2fc6d
+m pblendw $213 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df7a03f4b2fc6d
+r pblendw $214 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df7a03090d3b84
+m pblendw $214 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df7a03090d3b84
+r pblendw $215 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df7a03090dfc6d
+m pblendw $215 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8d96df7a03090dfc6d
+r pblendw $216 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa92010bf4b23b84
+m pblendw $216 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa92010bf4b23b84
+r pblendw $217 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa92010bf4b2fc6d
+m pblendw $217 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa92010bf4b2fc6d
+r pblendw $218 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa92010b090d3b84
+m pblendw $218 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa92010b090d3b84
+r pblendw $219 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa92010b090dfc6d
+m pblendw $219 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa92010b090dfc6d
+r pblendw $220 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa927a03f4b23b84
+m pblendw $220 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa927a03f4b23b84
+r pblendw $221 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa927a03f4b2fc6d
+m pblendw $221 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa927a03f4b2fc6d
+r pblendw $222 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa927a03090d3b84
+m pblendw $222 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa927a03090d3b84
+r pblendw $223 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa927a03090dfc6d
+m pblendw $223 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a0984920b8daa927a03090dfc6d
+r pblendw $224 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df010bf4b23b84
+m pblendw $224 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df010bf4b23b84
+r pblendw $225 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df010bf4b2fc6d
+m pblendw $225 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df010bf4b2fc6d
+r pblendw $226 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df010b090d3b84
+m pblendw $226 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df010b090d3b84
+r pblendw $227 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df010b090dfc6d
+m pblendw $227 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df010b090dfc6d
+r pblendw $228 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df7a03f4b23b84
+m pblendw $228 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df7a03f4b23b84
+r pblendw $229 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df7a03f4b2fc6d
+m pblendw $229 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df7a03f4b2fc6d
+r pblendw $230 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df7a03090d3b84
+m pblendw $230 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df7a03090d3b84
+r pblendw $231 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df7a03090dfc6d
+m pblendw $231 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e796df7a03090dfc6d
+r pblendw $232 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa92010bf4b23b84
+m pblendw $232 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa92010bf4b23b84
+r pblendw $233 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa92010bf4b2fc6d
+m pblendw $233 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa92010bf4b2fc6d
+r pblendw $234 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa92010b090d3b84
+m pblendw $234 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa92010b090d3b84
+r pblendw $235 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa92010b090dfc6d
+m pblendw $235 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa92010b090dfc6d
+r pblendw $236 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa927a03f4b23b84
+m pblendw $236 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa927a03f4b23b84
+r pblendw $237 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa927a03f4b2fc6d
+m pblendw $237 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa927a03f4b2fc6d
+r pblendw $238 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa927a03090d3b84
+m pblendw $238 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa927a03090d3b84
+r pblendw $239 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa927a03090dfc6d
+m pblendw $239 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df3e7e7aa927a03090dfc6d
+r pblendw $240 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df010bf4b23b84
+m pblendw $240 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df010bf4b23b84
+r pblendw $241 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df010bf4b2fc6d
+m pblendw $241 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df010bf4b2fc6d
+r pblendw $242 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df010b090d3b84
+m pblendw $242 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df010b090d3b84
+r pblendw $243 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df010b090dfc6d
+m pblendw $243 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df010b090dfc6d
+r pblendw $244 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df7a03f4b23b84
+m pblendw $244 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df7a03f4b23b84
+r pblendw $245 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df7a03f4b2fc6d
+m pblendw $245 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df7a03f4b2fc6d
+r pblendw $246 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df7a03090d3b84
+m pblendw $246 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df7a03090d3b84
+r pblendw $247 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df7a03090dfc6d
+m pblendw $247 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8d96df7a03090dfc6d
+r pblendw $248 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa92010bf4b23b84
+m pblendw $248 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa92010bf4b23b84
+r pblendw $249 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa92010bf4b2fc6d
+m pblendw $249 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa92010bf4b2fc6d
+r pblendw $250 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa92010b090d3b84
+m pblendw $250 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa92010b090d3b84
+r pblendw $251 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa92010b090dfc6d
+m pblendw $251 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa92010b090dfc6d
+r pblendw $252 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa927a03f4b23b84
+m pblendw $252 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa927a03f4b23b84
+r pblendw $253 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa927a03f4b2fc6d
+m pblendw $253 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa927a03f4b2fc6d
+r pblendw $254 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa927a03090d3b84
+m pblendw $254 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa927a03090d3b84
+r pblendw $255 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa927a03090dfc6d
+m pblendw $255 57436a097df30b8daa927a03090dfc6d 65ce6d498492e7e796df010bf4b23b84 57436a097df30b8daa927a03090dfc6d
+r pblendvb f5304f3e3ad1a923dc4c446c804bf950 c5e48064a393c8e947a34273c10a3c47 6ec34f98a2199d3c810bdacfab80ee3d -> c5c34f98a293c83c470bdacfc1803c3d
+m pblendvb f5304f3e3ad1a923dc4c446c804bf950 c5e48064a393c8e947a34273c10a3c47 6ec34f98a2199d3c810bdacfab80ee3d -> c5c34f98a293c83c470bdacfc1803c3d
+r pblendvb 6d08ed19fa045f841810cd8c109ed568 1c4a678450562685769ab818a5b7985e b984aed62671e865e6f21d40fc7bc013 -> b98467d65071e885e6f2b818fcb79813
+m pblendvb 6d08ed19fa045f841810cd8c109ed568 1c4a678450562685769ab818a5b7985e b984aed62671e865e6f21d40fc7bc013 -> b98467d65071e885e6f2b818fcb79813
+r pblendvb 5d0f926ce1157eaa95c45b338afcb3df 05a5c205c3659f388e17b17da2acb976 8b5fccbef0e1e256bc563e0c775bfaed -> 8b5fc2bec3e1e2388e173e0ca2acb976
+m pblendvb 5d0f926ce1157eaa95c45b338afcb3df 05a5c205c3659f388e17b17da2acb976 8b5fccbef0e1e256bc563e0c775bfaed -> 8b5fc2bec3e1e2388e173e0ca2acb976
+r pblendvb acb722146c6cbfa9ea4a022e1d3d7dbb 048612e51a468e36c51cdd8f87e12ab4 0c05cb6ebd128663d7568e3e8a3ac80e -> 0486cb6ebd128e36c5568e3e8a3ac8b4
+m pblendvb acb722146c6cbfa9ea4a022e1d3d7dbb 048612e51a468e36c51cdd8f87e12ab4 0c05cb6ebd128663d7568e3e8a3ac80e -> 0486cb6ebd128e36c5568e3e8a3ac8b4
+r pblendvb 22cf5e4cfad1bdf58de2b4a9d799ff5f 80ddba7e53e42d123208cf9b04b0569c 4288ae612c0dad40f0733f448390351b -> 42ddae6153e42d123208cf9b04b0561b
+m pblendvb 22cf5e4cfad1bdf58de2b4a9d799ff5f 80ddba7e53e42d123208cf9b04b0569c 4288ae612c0dad40f0733f448390351b -> 42ddae6153e42d123208cf9b04b0561b
+r pblendvb 6489eab2c96df363d52c4330a7aae391 c1fbfd8f4d8698c2cb9dfb4ea5d18713 14575775bc3a12029d8e66ea90352a18 -> 14fbfd8f4d3a9802cb8e66eaa5d18713
+m pblendvb 6489eab2c96df363d52c4330a7aae391 c1fbfd8f4d8698c2cb9dfb4ea5d18713 14575775bc3a12029d8e66ea90352a18 -> 14fbfd8f4d3a9802cb8e66eaa5d18713
+r pblendvb f9754842f9c9ba28f82a63b15c68b274 ec91fe34c7d6c79a66fab2b3db5ce85e 474289e7cb61501e54e7f35bc162726a -> ec4289e7c7d6c71e66e7f3b3c162e86a
+m pblendvb f9754842f9c9ba28f82a63b15c68b274 ec91fe34c7d6c79a66fab2b3db5ce85e 474289e7cb61501e54e7f35bc162726a -> ec4289e7c7d6c71e66e7f3b3c162e86a
+r pblendvb 4784d95987cd4ed80c3ca578a32bd88e 08aebee85fda964fbba02737f3c98220 837be65197abe2686b1fba2604afb8d5 -> 83aebe515fdae24f6b1f2726f3af8220
+m pblendvb 4784d95987cd4ed80c3ca578a32bd88e 08aebee85fda964fbba02737f3c98220 837be65197abe2686b1fba2604afb8d5 -> 83aebe515fdae24f6b1f2726f3af8220
+r pblendvb 9605e2b252c1c86809217c310baca0c3 fbc4208894fdc0f55f706da71bf2425f 4e92f1b240a122141a366d352714867e -> fb92208840fdc0141a366d3527f2425f
+m pblendvb 9605e2b252c1c86809217c310baca0c3 fbc4208894fdc0f55f706da71bf2425f 4e92f1b240a122141a366d352714867e -> fb92208840fdc0141a366d3527f2425f
+r pblendvb 0aaa836b194e242cc5fc3ae904033357 8ca3e752c306df00caab752f630ff07e 0e780c65c22b4ab8778d9ed6d9eb46ea -> 0ea3e765c22b4ab8caab9e2fd9eb46ea
+m pblendvb 0aaa836b194e242cc5fc3ae904033357 8ca3e752c306df00caab752f630ff07e 0e780c65c22b4ab8778d9ed6d9eb46ea -> 0ea3e765c22b4ab8caab9e2fd9eb46ea
+r blendvpd ac82c1007a7d3cd8f54b130cdaa89cef 627bb6e12d1f6d4651ef145cb9b83843 0a7c7a27fe91744777e3c0b6a9ec44fc -> 627bb6e12d1f6d4651ef145cb9b83843
+m blendvpd ac82c1007a7d3cd8f54b130cdaa89cef 627bb6e12d1f6d4651ef145cb9b83843 0a7c7a27fe91744777e3c0b6a9ec44fc -> 627bb6e12d1f6d4651ef145cb9b83843
+r blendvpd 61ff7d4df3b6ca8131f01866bd76c58f 02dd0e32eecfc5fa2c3ffa1aebe6a4d2 69505d14b27d9d16f25b26e0042fa9fa -> 69505d14b27d9d16f25b26e0042fa9fa
+m blendvpd 61ff7d4df3b6ca8131f01866bd76c58f 02dd0e32eecfc5fa2c3ffa1aebe6a4d2 69505d14b27d9d16f25b26e0042fa9fa -> 69505d14b27d9d16f25b26e0042fa9fa
+r blendvpd f0f1798fe3c1699cf02b3b25bca27a9c d4ba52a206ff21b170fbbab6a7f19faf 3004b7a97cf69dda9f7301c1392d8087 -> d4ba52a206ff21b170fbbab6a7f19faf
+m blendvpd f0f1798fe3c1699cf02b3b25bca27a9c d4ba52a206ff21b170fbbab6a7f19faf 3004b7a97cf69dda9f7301c1392d8087 -> d4ba52a206ff21b170fbbab6a7f19faf
+r blendvpd 0088596389c893fd879d51d4c5c764db 1e61c5ec52f79c6015e3c8dc7e9273bf 47086cc3da642fa7130d662777beb4a9 -> 47086cc3da642fa715e3c8dc7e9273bf
+m blendvpd 0088596389c893fd879d51d4c5c764db 1e61c5ec52f79c6015e3c8dc7e9273bf 47086cc3da642fa7130d662777beb4a9 -> 47086cc3da642fa715e3c8dc7e9273bf
+r blendvpd 16559ec50352a3d92d460a61a5dd0f6f 0784892e9360315bf0177599dbe14b46 742c3e9e2b92eef2c569453ccd1b0fc4 -> 742c3e9e2b92eef2c569453ccd1b0fc4
+m blendvpd 16559ec50352a3d92d460a61a5dd0f6f 0784892e9360315bf0177599dbe14b46 742c3e9e2b92eef2c569453ccd1b0fc4 -> 742c3e9e2b92eef2c569453ccd1b0fc4
+r blendvpd 9a49ac115048d4c4f987fa170d3ce4dd 9432a2e46543b956b819f459105730e9 5da3cfd6aea6558e0c28728e28dc3c9c -> 9432a2e46543b956b819f459105730e9
+m blendvpd 9a49ac115048d4c4f987fa170d3ce4dd 9432a2e46543b956b819f459105730e9 5da3cfd6aea6558e0c28728e28dc3c9c -> 9432a2e46543b956b819f459105730e9
+r blendvpd d2b3c4044ef23fb2e22093a48a9d2e0b adddf0eb4808f06704c857e949cc0fac 89fba268812abdb21e4a9e0958fac555 -> adddf0eb4808f06704c857e949cc0fac
+m blendvpd d2b3c4044ef23fb2e22093a48a9d2e0b adddf0eb4808f06704c857e949cc0fac 89fba268812abdb21e4a9e0958fac555 -> adddf0eb4808f06704c857e949cc0fac
+r blendvpd e4450ababbfae0f9bc3127138b19183c 1755377e9a786f014a6592749579b0f4 5f2619b1a20662f012305efa0acd1475 -> 1755377e9a786f014a6592749579b0f4
+m blendvpd e4450ababbfae0f9bc3127138b19183c 1755377e9a786f014a6592749579b0f4 5f2619b1a20662f012305efa0acd1475 -> 1755377e9a786f014a6592749579b0f4
+r blendvpd d70f7fb13667914c413cead25e27ac14 7acb193b9abab2f9e1917689e3f6bf86 2573776df1835e3ede9a220dce0e75e0 -> 7acb193b9abab2f9de9a220dce0e75e0
+m blendvpd d70f7fb13667914c413cead25e27ac14 7acb193b9abab2f9e1917689e3f6bf86 2573776df1835e3ede9a220dce0e75e0 -> 7acb193b9abab2f9de9a220dce0e75e0
+r blendvpd 918107c43ea20cc00420edac31a0d599 5cce191e65591384ff4cb613013cc685 0194ddb82b49abf059a93d4f11d611db -> 5cce191e6559138459a93d4f11d611db
+m blendvpd 918107c43ea20cc00420edac31a0d599 5cce191e65591384ff4cb613013cc685 0194ddb82b49abf059a93d4f11d611db -> 5cce191e6559138459a93d4f11d611db
+r blendvps da6c63303173ecc97e1e22cf15bd5c2f 24509983fc3bcc36baf7e45e9fa43077 fa99500fef6024ba39dce32c239cf309 -> 24509983ef6024ba39dce32c239cf309
+m blendvps da6c63303173ecc97e1e22cf15bd5c2f 24509983fc3bcc36baf7e45e9fa43077 fa99500fef6024ba39dce32c239cf309 -> 24509983ef6024ba39dce32c239cf309
+r blendvps 570037914d04ab3d05d75ec6f616ee9a 17a0dc273ba9f8030a52741849e54740 f6f2b14fbb3184b2141625713239066f -> f6f2b14fbb3184b21416257149e54740
+m blendvps 570037914d04ab3d05d75ec6f616ee9a 17a0dc273ba9f8030a52741849e54740 f6f2b14fbb3184b2141625713239066f -> f6f2b14fbb3184b21416257149e54740
+r blendvps 8fcf04e5b2dca44fcf4c517ea3a413ff 5d700527e24d9241c57eb74d70183523 bc70c3b3ef84644b6295f64a4ce61473 -> 5d700527e24d9241c57eb74d70183523
+m blendvps 8fcf04e5b2dca44fcf4c517ea3a413ff 5d700527e24d9241c57eb74d70183523 bc70c3b3ef84644b6295f64a4ce61473 -> 5d700527e24d9241c57eb74d70183523
+r blendvps e8c72e865de41295f2db8f44cbbf37e2 fcd015ff8f2e73a3a0fae06860b606c7 f34428d9c8833f5b78fb29445f3bc8d7 -> fcd015ffc8833f5ba0fae06860b606c7
+m blendvps e8c72e865de41295f2db8f44cbbf37e2 fcd015ff8f2e73a3a0fae06860b606c7 f34428d9c8833f5b78fb29445f3bc8d7 -> fcd015ffc8833f5ba0fae06860b606c7
+r blendvps a93bf6332d650e0266478ac4fc21a428 da30ef8bc0b5573e34a901384a97a32f 20fd62bd65b571158e48704b3c31abc2 -> da30ef8b65b571158e48704b4a97a32f
+m blendvps a93bf6332d650e0266478ac4fc21a428 da30ef8bc0b5573e34a901384a97a32f 20fd62bd65b571158e48704b3c31abc2 -> da30ef8b65b571158e48704b4a97a32f
+r blendvps f9da7f07e00794eb00b0940ba5e08516 be625608d5abd787f5c90ee73af5d7c0 ac8dd5bbc503330eb9dd5dab8e212ab7 -> be625608d5abd787b9dd5dab3af5d7c0
+m blendvps f9da7f07e00794eb00b0940ba5e08516 be625608d5abd787f5c90ee73af5d7c0 ac8dd5bbc503330eb9dd5dab8e212ab7 -> be625608d5abd787b9dd5dab3af5d7c0
+r blendvps ddb5cd8016d27d057796e0861576e44f 4e94ec120b386f523bfcd80321664d3e db43c391c6b69f3af17a6312e7c28d9a -> 4e94ec12c6b69f3af17a6312e7c28d9a
+m blendvps ddb5cd8016d27d057796e0861576e44f 4e94ec120b386f523bfcd80321664d3e db43c391c6b69f3af17a6312e7c28d9a -> 4e94ec12c6b69f3af17a6312e7c28d9a
+r blendvps 3d3cc0784c2f856363d9810079bbabd9 125934a781e479d33d431279cce48fce d4d14e592776b1ef0b40d58cb22d00b1 -> d4d14e592776b1ef0b40d58cb22d00b1
+m blendvps 3d3cc0784c2f856363d9810079bbabd9 125934a781e479d33d431279cce48fce d4d14e592776b1ef0b40d58cb22d00b1 -> d4d14e592776b1ef0b40d58cb22d00b1
+r blendvps df411d2ee2e7467c38bb69a6e1e9a617 6f9f902235982fa010fd4e94e9c808f5 9e477892854b43e0beafe48541dc8da0 -> 6f9f902235982fa0beafe485e9c808f5
+m blendvps df411d2ee2e7467c38bb69a6e1e9a617 6f9f902235982fa010fd4e94e9c808f5 9e477892854b43e0beafe48541dc8da0 -> 6f9f902235982fa0beafe485e9c808f5
+r blendvps 69f2843d15223a224edb6a053a967ecf acb9433f079dacacabeb000208c90296 20162517609f0f22a1a7a4c9c0a51f6b -> 20162517609f0f22a1a7a4c9c0a51f6b
+m blendvps 69f2843d15223a224edb6a053a967ecf acb9433f079dacacabeb000208c90296 20162517609f0f22a1a7a4c9c0a51f6b -> 20162517609f0f22a1a7a4c9c0a51f6b
+r dppd $0 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $0 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $1 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $1 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $2 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $2 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $3 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $3 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $4 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $4 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $5 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $5 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $6 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $6 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $7 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $7 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $8 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $8 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $9 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $9 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $10 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $10 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $11 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $11 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $12 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $12 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $13 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $13 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $14 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $14 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $15 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $15 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $16 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $16 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $17 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $17 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $18 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $18 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $19 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $19 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $20 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $20 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $21 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $21 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $22 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $22 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $23 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $23 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $24 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $24 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $25 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $25 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $26 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $26 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $27 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $27 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $28 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $28 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $29 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $29 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $30 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $30 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $31 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $31 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $32 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $32 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $33 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $33 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $34 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $34 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $35 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $35 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $36 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $36 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $37 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $37 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $38 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $38 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $39 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $39 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $40 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $40 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $41 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $41 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $42 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $42 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $43 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $43 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $44 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $44 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $45 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $45 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $46 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $46 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $47 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $47 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $48 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $48 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $49 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $49 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $50 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $50 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $51 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $51 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $52 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $52 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $53 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $53 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $54 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $54 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $55 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $55 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $56 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $56 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $57 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $57 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $58 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $58 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $59 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $59 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $60 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $60 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $61 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $61 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $62 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $62 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $63 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $63 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $64 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $64 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $65 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $65 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $66 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $66 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $67 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $67 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $68 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $68 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $69 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $69 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $70 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $70 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $71 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $71 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $72 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $72 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $73 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $73 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $74 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $74 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $75 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $75 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $76 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $76 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $77 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $77 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $78 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $78 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $79 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $79 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $80 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $80 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $81 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $81 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $82 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $82 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $83 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $83 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $84 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $84 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $85 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $85 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $86 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $86 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $87 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $87 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $88 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $88 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $89 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $89 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $90 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $90 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $91 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $91 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $92 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $92 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $93 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $93 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $94 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $94 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $95 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $95 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $96 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $96 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $97 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $97 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $98 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $98 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $99 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $99 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $100 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $100 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $101 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $101 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $102 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $102 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $103 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $103 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $104 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $104 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $105 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $105 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $106 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $106 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $107 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $107 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $108 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $108 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $109 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $109 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $110 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $110 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $111 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $111 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $112 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $112 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $113 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $113 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $114 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $114 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $115 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $115 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $116 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $116 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $117 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $117 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $118 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $118 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $119 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $119 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $120 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $120 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $121 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $121 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $122 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $122 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $123 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $123 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $124 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $124 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $125 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $125 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $126 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $126 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $127 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $127 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $128 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $128 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $129 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $129 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $130 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $130 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $131 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $131 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $132 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $132 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $133 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $133 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $134 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $134 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $135 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $135 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $136 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $136 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $137 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $137 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $138 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $138 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $139 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $139 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $140 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $140 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $141 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $141 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $142 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $142 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $143 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $143 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $144 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $144 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $145 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $145 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $146 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $146 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $147 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $147 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $148 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $148 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $149 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $149 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $150 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $150 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $151 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $151 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $152 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $152 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $153 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $153 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $154 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $154 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $155 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $155 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $156 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $156 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $157 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $157 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $158 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $158 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $159 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $159 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $160 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $160 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $161 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $161 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $162 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $162 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $163 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $163 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $164 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $164 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $165 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $165 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $166 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $166 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $167 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $167 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $168 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $168 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $169 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $169 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $170 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $170 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $171 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $171 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $172 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $172 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $173 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $173 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $174 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $174 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $175 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $175 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $176 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $176 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $177 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $177 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $178 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $178 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $179 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $179 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $180 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $180 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $181 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $181 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $182 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $182 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $183 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $183 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $184 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $184 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $185 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $185 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $186 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $186 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $187 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $187 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $188 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $188 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $189 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $189 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $190 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $190 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $191 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $191 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $192 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $192 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $193 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $193 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $194 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $194 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $195 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $195 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $196 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $196 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $197 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $197 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $198 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $198 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $199 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $199 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $200 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $200 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $201 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $201 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $202 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $202 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $203 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $203 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $204 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $204 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $205 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $205 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $206 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $206 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $207 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $207 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $208 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $208 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $209 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $209 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $210 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $210 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $211 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $211 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $212 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $212 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $213 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $213 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $214 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $214 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $215 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $215 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $216 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $216 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $217 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $217 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $218 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $218 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $219 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $219 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $220 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $220 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $221 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+m dppd $221 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c02b7561d8a6e474
+r dppd $222 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+m dppd $222 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e4740000000000000000
+r dppd $223 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+m dppd $223 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c02b7561d8a6e474c02b7561d8a6e474
+r dppd $224 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $224 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $225 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $225 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $226 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $226 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $227 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $227 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $228 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $228 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $229 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $229 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $230 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $230 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $231 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $231 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $232 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $232 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $233 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $233 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $234 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $234 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $235 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $235 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $236 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $236 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $237 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+m dppd $237 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c059bbcd882ced71
+r dppd $238 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+m dppd $238 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced710000000000000000
+r dppd $239 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+m dppd $239 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c059bbcd882ced71c059bbcd882ced71
+r dppd $240 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $240 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $241 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $241 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $242 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $242 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $243 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $243 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $244 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $244 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $245 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $245 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $246 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $246 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $247 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $247 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $248 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $248 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $249 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $249 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $250 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $250 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $251 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $251 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dppd $252 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+m dppd $252 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 00000000000000000000000000000000
+r dppd $253 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+m dppd $253 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 0000000000000000c05d2a79c341ca00
+r dppd $254 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+m dppd $254 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca000000000000000000
+r dppd $255 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+m dppd $255 c01b2809d495182b3ff3c083126e978d 402e52ccb3a2595cc0263e1cde5d1809 c05d2a79c341ca00c05d2a79c341ca00
+r dpps $0 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $0 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $1 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $1 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $2 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $2 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $3 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $3 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $4 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $4 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $5 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $5 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $6 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $6 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $7 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $7 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $8 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $8 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $9 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $9 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $10 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $10 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $11 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $11 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $12 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $12 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $13 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $13 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $14 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $14 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $15 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $15 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $16 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $16 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $17 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c1421cac
+m dpps $17 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c1421cac
+r dpps $18 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c1421cac00000000
+m dpps $18 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c1421cac00000000
+r dpps $19 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c1421cacc1421cac
+m dpps $19 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c1421cacc1421cac
+r dpps $20 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c1421cac0000000000000000
+m dpps $20 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c1421cac0000000000000000
+r dpps $21 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c1421cac00000000c1421cac
+m dpps $21 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c1421cac00000000c1421cac
+r dpps $22 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c1421cacc1421cac00000000
+m dpps $22 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c1421cacc1421cac00000000
+r dpps $23 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c1421cacc1421cacc1421cac
+m dpps $23 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c1421cacc1421cacc1421cac
+r dpps $24 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cac000000000000000000000000
+m dpps $24 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cac000000000000000000000000
+r dpps $25 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cac0000000000000000c1421cac
+m dpps $25 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cac0000000000000000c1421cac
+r dpps $26 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cac00000000c1421cac00000000
+m dpps $26 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cac00000000c1421cac00000000
+r dpps $27 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cac00000000c1421cacc1421cac
+m dpps $27 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cac00000000c1421cacc1421cac
+r dpps $28 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cacc1421cac0000000000000000
+m dpps $28 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cacc1421cac0000000000000000
+r dpps $29 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cacc1421cac00000000c1421cac
+m dpps $29 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cacc1421cac00000000c1421cac
+r dpps $30 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cacc1421cacc1421cac00000000
+m dpps $30 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cacc1421cacc1421cac00000000
+r dpps $31 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cacc1421cacc1421cacc1421cac
+m dpps $31 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1421cacc1421cacc1421cacc1421cac
+r dpps $32 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $32 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $33 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c224f7cf
+m dpps $33 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c224f7cf
+r dpps $34 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c224f7cf00000000
+m dpps $34 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c224f7cf00000000
+r dpps $35 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c224f7cfc224f7cf
+m dpps $35 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c224f7cfc224f7cf
+r dpps $36 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c224f7cf0000000000000000
+m dpps $36 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c224f7cf0000000000000000
+r dpps $37 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c224f7cf00000000c224f7cf
+m dpps $37 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c224f7cf00000000c224f7cf
+r dpps $38 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c224f7cfc224f7cf00000000
+m dpps $38 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c224f7cfc224f7cf00000000
+r dpps $39 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c224f7cfc224f7cfc224f7cf
+m dpps $39 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c224f7cfc224f7cfc224f7cf
+r dpps $40 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cf000000000000000000000000
+m dpps $40 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cf000000000000000000000000
+r dpps $41 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cf0000000000000000c224f7cf
+m dpps $41 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cf0000000000000000c224f7cf
+r dpps $42 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cf00000000c224f7cf00000000
+m dpps $42 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cf00000000c224f7cf00000000
+r dpps $43 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cf00000000c224f7cfc224f7cf
+m dpps $43 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cf00000000c224f7cfc224f7cf
+r dpps $44 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cfc224f7cf0000000000000000
+m dpps $44 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cfc224f7cf0000000000000000
+r dpps $45 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cfc224f7cf00000000c224f7cf
+m dpps $45 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cfc224f7cf00000000c224f7cf
+r dpps $46 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cfc224f7cfc224f7cf00000000
+m dpps $46 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cfc224f7cfc224f7cf00000000
+r dpps $47 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cfc224f7cfc224f7cfc224f7cf
+m dpps $47 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c224f7cfc224f7cfc224f7cfc224f7cf
+r dpps $48 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $48 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $49 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c2557efa
+m dpps $49 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c2557efa
+r dpps $50 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2557efa00000000
+m dpps $50 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2557efa00000000
+r dpps $51 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2557efac2557efa
+m dpps $51 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2557efac2557efa
+r dpps $52 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2557efa0000000000000000
+m dpps $52 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2557efa0000000000000000
+r dpps $53 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2557efa00000000c2557efa
+m dpps $53 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2557efa00000000c2557efa
+r dpps $54 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2557efac2557efa00000000
+m dpps $54 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2557efac2557efa00000000
+r dpps $55 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2557efac2557efac2557efa
+m dpps $55 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2557efac2557efac2557efa
+r dpps $56 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efa000000000000000000000000
+m dpps $56 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efa000000000000000000000000
+r dpps $57 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efa0000000000000000c2557efa
+m dpps $57 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efa0000000000000000c2557efa
+r dpps $58 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efa00000000c2557efa00000000
+m dpps $58 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efa00000000c2557efa00000000
+r dpps $59 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efa00000000c2557efac2557efa
+m dpps $59 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efa00000000c2557efac2557efa
+r dpps $60 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efac2557efa0000000000000000
+m dpps $60 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efac2557efa0000000000000000
+r dpps $61 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efac2557efa00000000c2557efa
+m dpps $61 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efac2557efa00000000c2557efa
+r dpps $62 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efac2557efac2557efa00000000
+m dpps $62 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efac2557efac2557efa00000000
+r dpps $63 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efac2557efac2557efac2557efa
+m dpps $63 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2557efac2557efac2557efac2557efa
+r dpps $64 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $64 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $65 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c2bd9c28
+m dpps $65 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c2bd9c28
+r dpps $66 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2bd9c2800000000
+m dpps $66 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2bd9c2800000000
+r dpps $67 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2bd9c28c2bd9c28
+m dpps $67 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2bd9c28c2bd9c28
+r dpps $68 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2bd9c280000000000000000
+m dpps $68 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2bd9c280000000000000000
+r dpps $69 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2bd9c2800000000c2bd9c28
+m dpps $69 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2bd9c2800000000c2bd9c28
+r dpps $70 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2bd9c28c2bd9c2800000000
+m dpps $70 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2bd9c28c2bd9c2800000000
+r dpps $71 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2bd9c28c2bd9c28c2bd9c28
+m dpps $71 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2bd9c28c2bd9c28c2bd9c28
+r dpps $72 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28000000000000000000000000
+m dpps $72 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28000000000000000000000000
+r dpps $73 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c280000000000000000c2bd9c28
+m dpps $73 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c280000000000000000c2bd9c28
+r dpps $74 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c2800000000c2bd9c2800000000
+m dpps $74 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c2800000000c2bd9c2800000000
+r dpps $75 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c2800000000c2bd9c28c2bd9c28
+m dpps $75 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c2800000000c2bd9c28c2bd9c28
+r dpps $76 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28c2bd9c280000000000000000
+m dpps $76 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28c2bd9c280000000000000000
+r dpps $77 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28c2bd9c2800000000c2bd9c28
+m dpps $77 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28c2bd9c2800000000c2bd9c28
+r dpps $78 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28c2bd9c28c2bd9c2800000000
+m dpps $78 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28c2bd9c28c2bd9c2800000000
+r dpps $79 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28c2bd9c28c2bd9c28c2bd9c28
+m dpps $79 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2bd9c28c2bd9c28c2bd9c28c2bd9c28
+r dpps $80 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $80 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $81 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c2d5dfbe
+m dpps $81 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c2d5dfbe
+r dpps $82 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2d5dfbe00000000
+m dpps $82 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2d5dfbe00000000
+r dpps $83 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2d5dfbec2d5dfbe
+m dpps $83 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c2d5dfbec2d5dfbe
+r dpps $84 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2d5dfbe0000000000000000
+m dpps $84 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2d5dfbe0000000000000000
+r dpps $85 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2d5dfbe00000000c2d5dfbe
+m dpps $85 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2d5dfbe00000000c2d5dfbe
+r dpps $86 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2d5dfbec2d5dfbe00000000
+m dpps $86 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2d5dfbec2d5dfbe00000000
+r dpps $87 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2d5dfbec2d5dfbec2d5dfbe
+m dpps $87 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c2d5dfbec2d5dfbec2d5dfbe
+r dpps $88 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbe000000000000000000000000
+m dpps $88 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbe000000000000000000000000
+r dpps $89 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbe0000000000000000c2d5dfbe
+m dpps $89 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbe0000000000000000c2d5dfbe
+r dpps $90 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbe00000000c2d5dfbe00000000
+m dpps $90 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbe00000000c2d5dfbe00000000
+r dpps $91 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbe00000000c2d5dfbec2d5dfbe
+m dpps $91 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbe00000000c2d5dfbec2d5dfbe
+r dpps $92 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbec2d5dfbe0000000000000000
+m dpps $92 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbec2d5dfbe0000000000000000
+r dpps $93 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbec2d5dfbe00000000c2d5dfbe
+m dpps $93 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbec2d5dfbe00000000c2d5dfbe
+r dpps $94 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbec2d5dfbec2d5dfbe00000000
+m dpps $94 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbec2d5dfbec2d5dfbe00000000
+r dpps $95 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbec2d5dfbec2d5dfbec2d5dfbe
+m dpps $95 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c2d5dfbec2d5dfbec2d5dfbec2d5dfbe
+r dpps $96 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $96 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $97 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c3080c08
+m dpps $97 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c3080c08
+r dpps $98 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3080c0800000000
+m dpps $98 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3080c0800000000
+r dpps $99 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3080c08c3080c08
+m dpps $99 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3080c08c3080c08
+r dpps $100 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3080c080000000000000000
+m dpps $100 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3080c080000000000000000
+r dpps $101 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3080c0800000000c3080c08
+m dpps $101 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3080c0800000000c3080c08
+r dpps $102 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3080c08c3080c0800000000
+m dpps $102 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3080c08c3080c0800000000
+r dpps $103 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3080c08c3080c08c3080c08
+m dpps $103 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3080c08c3080c08c3080c08
+r dpps $104 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08000000000000000000000000
+m dpps $104 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08000000000000000000000000
+r dpps $105 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c080000000000000000c3080c08
+m dpps $105 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c080000000000000000c3080c08
+r dpps $106 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c0800000000c3080c0800000000
+m dpps $106 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c0800000000c3080c0800000000
+r dpps $107 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c0800000000c3080c08c3080c08
+m dpps $107 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c0800000000c3080c08c3080c08
+r dpps $108 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08c3080c080000000000000000
+m dpps $108 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08c3080c080000000000000000
+r dpps $109 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08c3080c0800000000c3080c08
+m dpps $109 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08c3080c0800000000c3080c08
+r dpps $110 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08c3080c08c3080c0800000000
+m dpps $110 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08c3080c08c3080c0800000000
+r dpps $111 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08c3080c08c3080c08c3080c08
+m dpps $111 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3080c08c3080c08c3080c08c3080c08
+r dpps $112 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $112 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $113 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c3142dd2
+m dpps $113 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c3142dd2
+r dpps $114 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3142dd200000000
+m dpps $114 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3142dd200000000
+r dpps $115 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3142dd2c3142dd2
+m dpps $115 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3142dd2c3142dd2
+r dpps $116 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3142dd20000000000000000
+m dpps $116 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3142dd20000000000000000
+r dpps $117 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3142dd200000000c3142dd2
+m dpps $117 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3142dd200000000c3142dd2
+r dpps $118 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3142dd2c3142dd200000000
+m dpps $118 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3142dd2c3142dd200000000
+r dpps $119 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3142dd2c3142dd2c3142dd2
+m dpps $119 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3142dd2c3142dd2c3142dd2
+r dpps $120 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2000000000000000000000000
+m dpps $120 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2000000000000000000000000
+r dpps $121 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd20000000000000000c3142dd2
+m dpps $121 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd20000000000000000c3142dd2
+r dpps $122 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd200000000c3142dd200000000
+m dpps $122 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd200000000c3142dd200000000
+r dpps $123 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd200000000c3142dd2c3142dd2
+m dpps $123 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd200000000c3142dd2c3142dd2
+r dpps $124 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2c3142dd20000000000000000
+m dpps $124 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2c3142dd20000000000000000
+r dpps $125 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2c3142dd200000000c3142dd2
+m dpps $125 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2c3142dd200000000c3142dd2
+r dpps $126 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2c3142dd2c3142dd200000000
+m dpps $126 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2c3142dd2c3142dd200000000
+r dpps $127 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2c3142dd2c3142dd2c3142dd2
+m dpps $127 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3142dd2c3142dd2c3142dd2c3142dd2
+r dpps $128 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $128 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $129 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c30fe9ba
+m dpps $129 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c30fe9ba
+r dpps $130 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c30fe9ba00000000
+m dpps $130 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c30fe9ba00000000
+r dpps $131 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c30fe9bac30fe9ba
+m dpps $131 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c30fe9bac30fe9ba
+r dpps $132 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c30fe9ba0000000000000000
+m dpps $132 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c30fe9ba0000000000000000
+r dpps $133 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c30fe9ba00000000c30fe9ba
+m dpps $133 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c30fe9ba00000000c30fe9ba
+r dpps $134 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c30fe9bac30fe9ba00000000
+m dpps $134 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c30fe9bac30fe9ba00000000
+r dpps $135 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c30fe9bac30fe9bac30fe9ba
+m dpps $135 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c30fe9bac30fe9bac30fe9ba
+r dpps $136 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9ba000000000000000000000000
+m dpps $136 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9ba000000000000000000000000
+r dpps $137 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9ba0000000000000000c30fe9ba
+m dpps $137 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9ba0000000000000000c30fe9ba
+r dpps $138 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9ba00000000c30fe9ba00000000
+m dpps $138 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9ba00000000c30fe9ba00000000
+r dpps $139 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9ba00000000c30fe9bac30fe9ba
+m dpps $139 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9ba00000000c30fe9bac30fe9ba
+r dpps $140 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9bac30fe9ba0000000000000000
+m dpps $140 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9bac30fe9ba0000000000000000
+r dpps $141 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9bac30fe9ba00000000c30fe9ba
+m dpps $141 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9bac30fe9ba00000000c30fe9ba
+r dpps $142 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9bac30fe9bac30fe9ba00000000
+m dpps $142 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9bac30fe9bac30fe9ba00000000
+r dpps $143 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9bac30fe9bac30fe9bac30fe9ba
+m dpps $143 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c30fe9bac30fe9bac30fe9bac30fe9ba
+r dpps $144 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $144 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $145 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c31c0b85
+m dpps $145 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c31c0b85
+r dpps $146 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c31c0b8500000000
+m dpps $146 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c31c0b8500000000
+r dpps $147 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c31c0b85c31c0b85
+m dpps $147 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c31c0b85c31c0b85
+r dpps $148 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c31c0b850000000000000000
+m dpps $148 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c31c0b850000000000000000
+r dpps $149 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c31c0b8500000000c31c0b85
+m dpps $149 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c31c0b8500000000c31c0b85
+r dpps $150 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c31c0b85c31c0b8500000000
+m dpps $150 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c31c0b85c31c0b8500000000
+r dpps $151 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c31c0b85c31c0b85c31c0b85
+m dpps $151 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c31c0b85c31c0b85c31c0b85
+r dpps $152 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85000000000000000000000000
+m dpps $152 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85000000000000000000000000
+r dpps $153 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b850000000000000000c31c0b85
+m dpps $153 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b850000000000000000c31c0b85
+r dpps $154 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b8500000000c31c0b8500000000
+m dpps $154 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b8500000000c31c0b8500000000
+r dpps $155 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b8500000000c31c0b85c31c0b85
+m dpps $155 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b8500000000c31c0b85c31c0b85
+r dpps $156 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85c31c0b850000000000000000
+m dpps $156 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85c31c0b850000000000000000
+r dpps $157 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85c31c0b8500000000c31c0b85
+m dpps $157 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85c31c0b8500000000c31c0b85
+r dpps $158 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85c31c0b85c31c0b8500000000
+m dpps $158 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85c31c0b85c31c0b8500000000
+r dpps $159 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85c31c0b85c31c0b85c31c0b85
+m dpps $159 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c31c0b85c31c0b85c31c0b85c31c0b85
+r dpps $160 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $160 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $161 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c33927ae
+m dpps $161 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c33927ae
+r dpps $162 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c33927ae00000000
+m dpps $162 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c33927ae00000000
+r dpps $163 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c33927aec33927ae
+m dpps $163 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c33927aec33927ae
+r dpps $164 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c33927ae0000000000000000
+m dpps $164 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c33927ae0000000000000000
+r dpps $165 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c33927ae00000000c33927ae
+m dpps $165 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c33927ae00000000c33927ae
+r dpps $166 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c33927aec33927ae00000000
+m dpps $166 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c33927aec33927ae00000000
+r dpps $167 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c33927aec33927aec33927ae
+m dpps $167 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c33927aec33927aec33927ae
+r dpps $168 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927ae000000000000000000000000
+m dpps $168 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927ae000000000000000000000000
+r dpps $169 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927ae0000000000000000c33927ae
+m dpps $169 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927ae0000000000000000c33927ae
+r dpps $170 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927ae00000000c33927ae00000000
+m dpps $170 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927ae00000000c33927ae00000000
+r dpps $171 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927ae00000000c33927aec33927ae
+m dpps $171 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927ae00000000c33927aec33927ae
+r dpps $172 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927aec33927ae0000000000000000
+m dpps $172 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927aec33927ae0000000000000000
+r dpps $173 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927aec33927ae00000000c33927ae
+m dpps $173 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927aec33927ae00000000c33927ae
+r dpps $174 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927aec33927aec33927ae00000000
+m dpps $174 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927aec33927aec33927ae00000000
+r dpps $175 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927aec33927aec33927aec33927ae
+m dpps $175 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c33927aec33927aec33927aec33927ae
+r dpps $176 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $176 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $177 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c3454978
+m dpps $177 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c3454978
+r dpps $178 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c345497800000000
+m dpps $178 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c345497800000000
+r dpps $179 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3454978c3454978
+m dpps $179 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3454978c3454978
+r dpps $180 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c34549780000000000000000
+m dpps $180 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c34549780000000000000000
+r dpps $181 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c345497800000000c3454978
+m dpps $181 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c345497800000000c3454978
+r dpps $182 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3454978c345497800000000
+m dpps $182 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3454978c345497800000000
+r dpps $183 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3454978c3454978c3454978
+m dpps $183 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3454978c3454978c3454978
+r dpps $184 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978000000000000000000000000
+m dpps $184 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978000000000000000000000000
+r dpps $185 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c34549780000000000000000c3454978
+m dpps $185 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c34549780000000000000000c3454978
+r dpps $186 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c345497800000000c345497800000000
+m dpps $186 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c345497800000000c345497800000000
+r dpps $187 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c345497800000000c3454978c3454978
+m dpps $187 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c345497800000000c3454978c3454978
+r dpps $188 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978c34549780000000000000000
+m dpps $188 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978c34549780000000000000000
+r dpps $189 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978c345497800000000c3454978
+m dpps $189 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978c345497800000000c3454978
+r dpps $190 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978c3454978c345497800000000
+m dpps $190 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978c3454978c345497800000000
+r dpps $191 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978c3454978c3454978c3454978
+m dpps $191 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3454978c3454978c3454978c3454978
+r dpps $192 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $192 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $193 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c36eb7ce
+m dpps $193 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c36eb7ce
+r dpps $194 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c36eb7ce00000000
+m dpps $194 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c36eb7ce00000000
+r dpps $195 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c36eb7cec36eb7ce
+m dpps $195 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c36eb7cec36eb7ce
+r dpps $196 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c36eb7ce0000000000000000
+m dpps $196 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c36eb7ce0000000000000000
+r dpps $197 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c36eb7ce00000000c36eb7ce
+m dpps $197 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c36eb7ce00000000c36eb7ce
+r dpps $198 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c36eb7cec36eb7ce00000000
+m dpps $198 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c36eb7cec36eb7ce00000000
+r dpps $199 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c36eb7cec36eb7cec36eb7ce
+m dpps $199 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c36eb7cec36eb7cec36eb7ce
+r dpps $200 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7ce000000000000000000000000
+m dpps $200 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7ce000000000000000000000000
+r dpps $201 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7ce0000000000000000c36eb7ce
+m dpps $201 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7ce0000000000000000c36eb7ce
+r dpps $202 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7ce00000000c36eb7ce00000000
+m dpps $202 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7ce00000000c36eb7ce00000000
+r dpps $203 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7ce00000000c36eb7cec36eb7ce
+m dpps $203 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7ce00000000c36eb7cec36eb7ce
+r dpps $204 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7cec36eb7ce0000000000000000
+m dpps $204 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7cec36eb7ce0000000000000000
+r dpps $205 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7cec36eb7ce00000000c36eb7ce
+m dpps $205 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7cec36eb7ce00000000c36eb7ce
+r dpps $206 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7cec36eb7cec36eb7ce00000000
+m dpps $206 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7cec36eb7cec36eb7ce00000000
+r dpps $207 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7cec36eb7cec36eb7cec36eb7ce
+m dpps $207 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c36eb7cec36eb7cec36eb7cec36eb7ce
+r dpps $208 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $208 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $209 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c37ad999
+m dpps $209 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c37ad999
+r dpps $210 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c37ad99900000000
+m dpps $210 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c37ad99900000000
+r dpps $211 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c37ad999c37ad999
+m dpps $211 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c37ad999c37ad999
+r dpps $212 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c37ad9990000000000000000
+m dpps $212 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c37ad9990000000000000000
+r dpps $213 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c37ad99900000000c37ad999
+m dpps $213 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c37ad99900000000c37ad999
+r dpps $214 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c37ad999c37ad99900000000
+m dpps $214 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c37ad999c37ad99900000000
+r dpps $215 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c37ad999c37ad999c37ad999
+m dpps $215 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c37ad999c37ad999c37ad999
+r dpps $216 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999000000000000000000000000
+m dpps $216 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999000000000000000000000000
+r dpps $217 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad9990000000000000000c37ad999
+m dpps $217 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad9990000000000000000c37ad999
+r dpps $218 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad99900000000c37ad99900000000
+m dpps $218 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad99900000000c37ad99900000000
+r dpps $219 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad99900000000c37ad999c37ad999
+m dpps $219 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad99900000000c37ad999c37ad999
+r dpps $220 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999c37ad9990000000000000000
+m dpps $220 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999c37ad9990000000000000000
+r dpps $221 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999c37ad99900000000c37ad999
+m dpps $221 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999c37ad99900000000c37ad999
+r dpps $222 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999c37ad999c37ad99900000000
+m dpps $222 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999c37ad999c37ad99900000000
+r dpps $223 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999c37ad999c37ad999c37ad999
+m dpps $223 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c37ad999c37ad999c37ad999c37ad999
+r dpps $224 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $224 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $225 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c38bfae1
+m dpps $225 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c38bfae1
+r dpps $226 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c38bfae100000000
+m dpps $226 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c38bfae100000000
+r dpps $227 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c38bfae1c38bfae1
+m dpps $227 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c38bfae1c38bfae1
+r dpps $228 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c38bfae10000000000000000
+m dpps $228 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c38bfae10000000000000000
+r dpps $229 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c38bfae100000000c38bfae1
+m dpps $229 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c38bfae100000000c38bfae1
+r dpps $230 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c38bfae1c38bfae100000000
+m dpps $230 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c38bfae1c38bfae100000000
+r dpps $231 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c38bfae1c38bfae1c38bfae1
+m dpps $231 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c38bfae1c38bfae1c38bfae1
+r dpps $232 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1000000000000000000000000
+m dpps $232 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1000000000000000000000000
+r dpps $233 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae10000000000000000c38bfae1
+m dpps $233 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae10000000000000000c38bfae1
+r dpps $234 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae100000000c38bfae100000000
+m dpps $234 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae100000000c38bfae100000000
+r dpps $235 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae100000000c38bfae1c38bfae1
+m dpps $235 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae100000000c38bfae1c38bfae1
+r dpps $236 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1c38bfae10000000000000000
+m dpps $236 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1c38bfae10000000000000000
+r dpps $237 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1c38bfae100000000c38bfae1
+m dpps $237 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1c38bfae100000000c38bfae1
+r dpps $238 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1c38bfae1c38bfae100000000
+m dpps $238 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1c38bfae1c38bfae100000000
+r dpps $239 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1c38bfae1c38bfae1c38bfae1
+m dpps $239 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c38bfae1c38bfae1c38bfae1c38bfae1
+r dpps $240 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m dpps $240 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r dpps $241 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c3920bc6
+m dpps $241 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c3920bc6
+r dpps $242 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3920bc600000000
+m dpps $242 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3920bc600000000
+r dpps $243 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3920bc6c3920bc6
+m dpps $243 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c3920bc6c3920bc6
+r dpps $244 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3920bc60000000000000000
+m dpps $244 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3920bc60000000000000000
+r dpps $245 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3920bc600000000c3920bc6
+m dpps $245 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3920bc600000000c3920bc6
+r dpps $246 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3920bc6c3920bc600000000
+m dpps $246 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3920bc6c3920bc600000000
+r dpps $247 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3920bc6c3920bc6c3920bc6
+m dpps $247 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c3920bc6c3920bc6c3920bc6
+r dpps $248 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6000000000000000000000000
+m dpps $248 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6000000000000000000000000
+r dpps $249 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc60000000000000000c3920bc6
+m dpps $249 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc60000000000000000c3920bc6
+r dpps $250 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc600000000c3920bc600000000
+m dpps $250 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc600000000c3920bc600000000
+r dpps $251 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc600000000c3920bc6c3920bc6
+m dpps $251 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc600000000c3920bc6c3920bc6
+r dpps $252 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6c3920bc60000000000000000
+m dpps $252 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6c3920bc60000000000000000
+r dpps $253 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6c3920bc600000000c3920bc6
+m dpps $253 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6c3920bc600000000c3920bc6
+r dpps $254 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6c3920bc6c3920bc600000000
+m dpps $254 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6c3920bc6c3920bc600000000
+r dpps $255 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6c3920bc6c3920bc6c3920bc6
+m dpps $255 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c3920bc6c3920bc6c3920bc6c3920bc6
+r extractps $0 63e279a20368bc8bdb3b370954bcbf24 5555555555555555 0000000054bcbf24
+m extractps $0 63e279a20368bc8bdb3b370954bcbf24 5555555555555555 5555555554bcbf24
+r extractps $1 63e279a20368bc8bdb3b370954bcbf24 5555555555555555 00000000db3b3709
+m extractps $1 63e279a20368bc8bdb3b370954bcbf24 5555555555555555 55555555db3b3709
+r extractps $2 63e279a20368bc8bdb3b370954bcbf24 5555555555555555 000000000368bc8b
+m extractps $2 63e279a20368bc8bdb3b370954bcbf24 5555555555555555 555555550368bc8b
+r extractps $3 63e279a20368bc8bdb3b370954bcbf24 5555555555555555 0000000063e279a2
+m extractps $3 63e279a20368bc8bdb3b370954bcbf24 5555555555555555 5555555563e279a2
+r insertps $0 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b3f99999a
+m insertps $0 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b3f99999a
+r insertps $1 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b00000000
+m insertps $1 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b00000000
+r insertps $2 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666000000003f99999a
+m insertps $2 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666000000003f99999a
+r insertps $3 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+m insertps $3 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+r insertps $4 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b3f99999a
+m insertps $4 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b3f99999a
+r insertps $5 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+m insertps $5 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+r insertps $6 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000000000003f99999a
+m insertps $6 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000000000003f99999a
+r insertps $7 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $7 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $8 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b3f99999a
+m insertps $8 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b3f99999a
+r insertps $9 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+m insertps $9 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+r insertps $10 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666000000003f99999a
+m insertps $10 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666000000003f99999a
+r insertps $11 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $11 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $12 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b3f99999a
+m insertps $12 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b3f99999a
+r insertps $13 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $13 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $14 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000000000003f99999a
+m insertps $14 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000000000003f99999a
+r insertps $15 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $15 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $16 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999ac121c28f
+m insertps $16 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999ac121c28f
+r insertps $17 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999a00000000
+m insertps $17 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999a00000000
+r insertps $18 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c121c28f
+m insertps $18 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c121c28f
+r insertps $19 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+m insertps $19 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+r insertps $20 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999ac121c28f
+m insertps $20 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999ac121c28f
+r insertps $21 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999a00000000
+m insertps $21 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999a00000000
+r insertps $22 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+m insertps $22 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+r insertps $23 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $23 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $24 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999ac121c28f
+m insertps $24 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999ac121c28f
+r insertps $25 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999a00000000
+m insertps $25 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999a00000000
+r insertps $26 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+m insertps $26 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+r insertps $27 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $27 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $28 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999ac121c28f
+m insertps $28 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999ac121c28f
+r insertps $29 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999a00000000
+m insertps $29 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999a00000000
+r insertps $30 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $30 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $31 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $31 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $32 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147bc121c28f
+m insertps $32 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147bc121c28f
+r insertps $33 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147b00000000
+m insertps $33 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147b00000000
+r insertps $34 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a00000000c121c28f
+m insertps $34 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a00000000c121c28f
+r insertps $35 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a0000000000000000
+m insertps $35 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a0000000000000000
+r insertps $36 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc121c28f
+m insertps $36 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc121c28f
+r insertps $37 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+m insertps $37 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+r insertps $38 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+m insertps $38 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+r insertps $39 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $39 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $40 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147bc121c28f
+m insertps $40 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147bc121c28f
+r insertps $41 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147b00000000
+m insertps $41 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147b00000000
+r insertps $42 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a00000000c121c28f
+m insertps $42 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a00000000c121c28f
+r insertps $43 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a0000000000000000
+m insertps $43 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a0000000000000000
+r insertps $44 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+m insertps $44 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+r insertps $45 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $45 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $46 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $46 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $47 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $47 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $48 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147bc121c28f
+m insertps $48 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147bc121c28f
+r insertps $49 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147b00000000
+m insertps $49 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147b00000000
+r insertps $50 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a4162666600000000c121c28f
+m insertps $50 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a4162666600000000c121c28f
+r insertps $51 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266660000000000000000
+m insertps $51 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266660000000000000000
+r insertps $52 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147bc121c28f
+m insertps $52 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147bc121c28f
+r insertps $53 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147b00000000
+m insertps $53 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147b00000000
+r insertps $54 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a0000000000000000c121c28f
+m insertps $54 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a0000000000000000c121c28f
+r insertps $55 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000000000000000000000
+m insertps $55 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000000000000000000000
+r insertps $56 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc121c28f
+m insertps $56 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc121c28f
+r insertps $57 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+m insertps $57 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+r insertps $58 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+m insertps $58 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+r insertps $59 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $59 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $60 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+m insertps $60 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+r insertps $61 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $61 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $62 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $62 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $63 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $63 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $64 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147bc059999a
+m insertps $64 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b3f99999a
+r insertps $65 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b00000000
+m insertps $65 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b00000000
+r insertps $66 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c059999a
+m insertps $66 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666000000003f99999a
+r insertps $67 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+m insertps $67 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+r insertps $68 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc059999a
+m insertps $68 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b3f99999a
+r insertps $69 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+m insertps $69 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+r insertps $70 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c059999a
+m insertps $70 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000000000003f99999a
+r insertps $71 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $71 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $72 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc059999a
+m insertps $72 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b3f99999a
+r insertps $73 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+m insertps $73 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+r insertps $74 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c059999a
+m insertps $74 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666000000003f99999a
+r insertps $75 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $75 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $76 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc059999a
+m insertps $76 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b3f99999a
+r insertps $77 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $77 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $78 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c059999a
+m insertps $78 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000000000003f99999a
+r insertps $79 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $79 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $80 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666c059999ac121c28f
+m insertps $80 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999ac121c28f
+r insertps $81 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666c059999a00000000
+m insertps $81 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999a00000000
+r insertps $82 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c121c28f
+m insertps $82 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c121c28f
+r insertps $83 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+m insertps $83 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+r insertps $84 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000c059999ac121c28f
+m insertps $84 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999ac121c28f
+r insertps $85 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000c059999a00000000
+m insertps $85 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999a00000000
+r insertps $86 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+m insertps $86 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+r insertps $87 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $87 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $88 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666c059999ac121c28f
+m insertps $88 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999ac121c28f
+r insertps $89 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666c059999a00000000
+m insertps $89 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999a00000000
+r insertps $90 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+m insertps $90 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+r insertps $91 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $91 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $92 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c059999ac121c28f
+m insertps $92 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999ac121c28f
+r insertps $93 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c059999a00000000
+m insertps $93 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999a00000000
+r insertps $94 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $94 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $95 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $95 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $96 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29c059999a4142147bc121c28f
+m insertps $96 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147bc121c28f
+r insertps $97 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29c059999a4142147b00000000
+m insertps $97 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147b00000000
+r insertps $98 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29c059999a00000000c121c28f
+m insertps $98 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a00000000c121c28f
+r insertps $99 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29c059999a0000000000000000
+m insertps $99 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a0000000000000000
+r insertps $100 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc121c28f
+m insertps $100 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc121c28f
+r insertps $101 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+m insertps $101 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+r insertps $102 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+m insertps $102 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+r insertps $103 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $103 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $104 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c059999a4142147bc121c28f
+m insertps $104 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147bc121c28f
+r insertps $105 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c059999a4142147b00000000
+m insertps $105 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147b00000000
+r insertps $106 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c059999a00000000c121c28f
+m insertps $106 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a00000000c121c28f
+r insertps $107 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c059999a0000000000000000
+m insertps $107 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a0000000000000000
+r insertps $108 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+m insertps $108 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+r insertps $109 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $109 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $110 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $110 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $111 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $111 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $112 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c059999a416266664142147bc121c28f
+m insertps $112 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147bc121c28f
+r insertps $113 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c059999a416266664142147b00000000
+m insertps $113 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147b00000000
+r insertps $114 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c059999a4162666600000000c121c28f
+m insertps $114 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a4162666600000000c121c28f
+r insertps $115 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c059999a416266660000000000000000
+m insertps $115 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266660000000000000000
+r insertps $116 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c059999a000000004142147bc121c28f
+m insertps $116 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147bc121c28f
+r insertps $117 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c059999a000000004142147b00000000
+m insertps $117 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147b00000000
+r insertps $118 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c059999a0000000000000000c121c28f
+m insertps $118 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a0000000000000000c121c28f
+r insertps $119 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c059999a000000000000000000000000
+m insertps $119 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000000000000000000000
+r insertps $120 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc121c28f
+m insertps $120 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc121c28f
+r insertps $121 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+m insertps $121 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+r insertps $122 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+m insertps $122 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+r insertps $123 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $123 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $124 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+m insertps $124 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+r insertps $125 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $125 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $126 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $126 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $127 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $127 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $128 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147bc0d66666
+m insertps $128 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b3f99999a
+r insertps $129 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b00000000
+m insertps $129 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b00000000
+r insertps $130 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c0d66666
+m insertps $130 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666000000003f99999a
+r insertps $131 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+m insertps $131 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+r insertps $132 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc0d66666
+m insertps $132 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b3f99999a
+r insertps $133 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+m insertps $133 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+r insertps $134 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c0d66666
+m insertps $134 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000000000003f99999a
+r insertps $135 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $135 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $136 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc0d66666
+m insertps $136 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b3f99999a
+r insertps $137 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+m insertps $137 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+r insertps $138 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c0d66666
+m insertps $138 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666000000003f99999a
+r insertps $139 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $139 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $140 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc0d66666
+m insertps $140 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b3f99999a
+r insertps $141 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $141 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $142 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c0d66666
+m insertps $142 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000000000003f99999a
+r insertps $143 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $143 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $144 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666c0d66666c121c28f
+m insertps $144 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999ac121c28f
+r insertps $145 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666c0d6666600000000
+m insertps $145 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999a00000000
+r insertps $146 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c121c28f
+m insertps $146 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c121c28f
+r insertps $147 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+m insertps $147 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+r insertps $148 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000c0d66666c121c28f
+m insertps $148 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999ac121c28f
+r insertps $149 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000c0d6666600000000
+m insertps $149 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999a00000000
+r insertps $150 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+m insertps $150 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+r insertps $151 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $151 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $152 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666c0d66666c121c28f
+m insertps $152 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999ac121c28f
+r insertps $153 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666c0d6666600000000
+m insertps $153 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999a00000000
+r insertps $154 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+m insertps $154 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+r insertps $155 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $155 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $156 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c0d66666c121c28f
+m insertps $156 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999ac121c28f
+r insertps $157 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000c0d6666600000000
+m insertps $157 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999a00000000
+r insertps $158 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $158 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $159 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $159 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $160 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29c0d666664142147bc121c28f
+m insertps $160 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147bc121c28f
+r insertps $161 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29c0d666664142147b00000000
+m insertps $161 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147b00000000
+r insertps $162 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29c0d6666600000000c121c28f
+m insertps $162 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a00000000c121c28f
+r insertps $163 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29c0d666660000000000000000
+m insertps $163 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a0000000000000000
+r insertps $164 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc121c28f
+m insertps $164 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc121c28f
+r insertps $165 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+m insertps $165 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+r insertps $166 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+m insertps $166 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+r insertps $167 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $167 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $168 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c0d666664142147bc121c28f
+m insertps $168 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147bc121c28f
+r insertps $169 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c0d666664142147b00000000
+m insertps $169 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147b00000000
+r insertps $170 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c0d6666600000000c121c28f
+m insertps $170 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a00000000c121c28f
+r insertps $171 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000c0d666660000000000000000
+m insertps $171 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a0000000000000000
+r insertps $172 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+m insertps $172 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+r insertps $173 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $173 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $174 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $174 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $175 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $175 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $176 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c0d66666416266664142147bc121c28f
+m insertps $176 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147bc121c28f
+r insertps $177 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c0d66666416266664142147b00000000
+m insertps $177 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147b00000000
+r insertps $178 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c0d666664162666600000000c121c28f
+m insertps $178 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a4162666600000000c121c28f
+r insertps $179 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c0d66666416266660000000000000000
+m insertps $179 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266660000000000000000
+r insertps $180 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c0d66666000000004142147bc121c28f
+m insertps $180 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147bc121c28f
+r insertps $181 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c0d66666000000004142147b00000000
+m insertps $181 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147b00000000
+r insertps $182 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c0d666660000000000000000c121c28f
+m insertps $182 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a0000000000000000c121c28f
+r insertps $183 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c0d66666000000000000000000000000
+m insertps $183 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000000000000000000000
+r insertps $184 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc121c28f
+m insertps $184 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc121c28f
+r insertps $185 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+m insertps $185 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+r insertps $186 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+m insertps $186 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+r insertps $187 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $187 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $188 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+m insertps $188 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+r insertps $189 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $189 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $190 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $190 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $191 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $191 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $192 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b410e6666
+m insertps $192 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b3f99999a
+r insertps $193 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b00000000
+m insertps $193 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266664142147b00000000
+r insertps $194 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000410e6666
+m insertps $194 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666000000003f99999a
+r insertps $195 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+m insertps $195 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+r insertps $196 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b410e6666
+m insertps $196 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b3f99999a
+r insertps $197 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+m insertps $197 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+r insertps $198 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000410e6666
+m insertps $198 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000000000003f99999a
+r insertps $199 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $199 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $200 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b410e6666
+m insertps $200 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b3f99999a
+r insertps $201 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+m insertps $201 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+r insertps $202 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000410e6666
+m insertps $202 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666000000003f99999a
+r insertps $203 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $203 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $204 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b410e6666
+m insertps $204 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b3f99999a
+r insertps $205 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $205 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $206 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000410e6666
+m insertps $206 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000000000003f99999a
+r insertps $207 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $207 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $208 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666410e6666c121c28f
+m insertps $208 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999ac121c28f
+r insertps $209 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2941626666410e666600000000
+m insertps $209 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266663f99999a00000000
+r insertps $210 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c121c28f
+m insertps $210 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c294162666600000000c121c28f
+r insertps $211 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+m insertps $211 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29416266660000000000000000
+r insertps $212 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000410e6666c121c28f
+m insertps $212 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999ac121c28f
+r insertps $213 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c2900000000410e666600000000
+m insertps $213 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000003f99999a00000000
+r insertps $214 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+m insertps $214 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+r insertps $215 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $215 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $216 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666410e6666c121c28f
+m insertps $216 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999ac121c28f
+r insertps $217 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000041626666410e666600000000
+m insertps $217 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266663f99999a00000000
+r insertps $218 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+m insertps $218 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+r insertps $219 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $219 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $220 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000410e6666c121c28f
+m insertps $220 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999ac121c28f
+r insertps $221 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 0000000000000000410e666600000000
+m insertps $221 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000003f99999a00000000
+r insertps $222 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $222 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $223 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $223 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $224 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29410e66664142147bc121c28f
+m insertps $224 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147bc121c28f
+r insertps $225 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29410e66664142147b00000000
+m insertps $225 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a4142147b00000000
+r insertps $226 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29410e666600000000c121c28f
+m insertps $226 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a00000000c121c28f
+r insertps $227 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29410e66660000000000000000
+m insertps $227 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c293f99999a0000000000000000
+r insertps $228 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc121c28f
+m insertps $228 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147bc121c28f
+r insertps $229 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+m insertps $229 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000004142147b00000000
+r insertps $230 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+m insertps $230 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c290000000000000000c121c28f
+r insertps $231 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+m insertps $231 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f c1815c29000000000000000000000000
+r insertps $232 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000410e66664142147bc121c28f
+m insertps $232 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147bc121c28f
+r insertps $233 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000410e66664142147b00000000
+m insertps $233 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a4142147b00000000
+r insertps $234 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000410e666600000000c121c28f
+m insertps $234 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a00000000c121c28f
+r insertps $235 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000410e66660000000000000000
+m insertps $235 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000003f99999a0000000000000000
+r insertps $236 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+m insertps $236 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+r insertps $237 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $237 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $238 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $238 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $239 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $239 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r insertps $240 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 410e6666416266664142147bc121c28f
+m insertps $240 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147bc121c28f
+r insertps $241 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 410e6666416266664142147b00000000
+m insertps $241 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266664142147b00000000
+r insertps $242 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 410e66664162666600000000c121c28f
+m insertps $242 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a4162666600000000c121c28f
+r insertps $243 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 410e6666416266660000000000000000
+m insertps $243 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a416266660000000000000000
+r insertps $244 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 410e6666000000004142147bc121c28f
+m insertps $244 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147bc121c28f
+r insertps $245 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 410e6666000000004142147b00000000
+m insertps $245 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000004142147b00000000
+r insertps $246 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 410e66660000000000000000c121c28f
+m insertps $246 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a0000000000000000c121c28f
+r insertps $247 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 410e6666000000000000000000000000
+m insertps $247 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 3f99999a000000000000000000000000
+r insertps $248 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc121c28f
+m insertps $248 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147bc121c28f
+r insertps $249 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+m insertps $249 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266664142147b00000000
+r insertps $250 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+m insertps $250 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000004162666600000000c121c28f
+r insertps $251 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+m insertps $251 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000416266660000000000000000
+r insertps $252 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+m insertps $252 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147bc121c28f
+r insertps $253 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+m insertps $253 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000004142147b00000000
+r insertps $254 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+m insertps $254 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 000000000000000000000000c121c28f
+r insertps $255 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+m insertps $255 410e6666c0d66666c059999a3f99999a c1815c29416266664142147bc121c28f 00000000000000000000000000000000
+r pextrb $0 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 00000000000000f7
+m pextrb $0 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 55555555555555f7
+r pextrb $1 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 00000000000000a7
+m pextrb $1 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 55555555555555a7
+r pextrb $2 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 0000000000000000
+m pextrb $2 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 5555555555555500
+r pextrb $3 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 0000000000000097
+m pextrb $3 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 5555555555555597
+r pextrb $4 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 00000000000000ce
+m pextrb $4 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 55555555555555ce
+r pextrb $5 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 0000000000000079
+m pextrb $5 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 5555555555555579
+r pextrb $6 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 000000000000002e
+m pextrb $6 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 555555555555552e
+r pextrb $7 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 00000000000000e5
+m pextrb $7 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 55555555555555e5
+r pextrb $8 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 000000000000004c
+m pextrb $8 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 555555555555554c
+r pextrb $9 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 00000000000000ea
+m pextrb $9 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 55555555555555ea
+r pextrb $10 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 000000000000009b
+m pextrb $10 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 555555555555559b
+r pextrb $11 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 00000000000000b4
+m pextrb $11 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 55555555555555b4
+r pextrb $12 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 000000000000001d
+m pextrb $12 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 555555555555551d
+r pextrb $13 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 0000000000000070
+m pextrb $13 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 5555555555555570
+r pextrb $14 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 0000000000000056
+m pextrb $14 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 5555555555555556
+r pextrb $15 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 00000000000000ef
+m pextrb $15 ef56701db49bea4ce52e79ce9700a7f7 5555555555555555 55555555555555ef
+r pextrd $0 200d17261638b12a2a6a07863ec28077 5555555555555555 000000003ec28077
+m pextrd $0 200d17261638b12a2a6a07863ec28077 5555555555555555 555555553ec28077
+r pextrd $1 200d17261638b12a2a6a07863ec28077 5555555555555555 000000002a6a0786
+m pextrd $1 200d17261638b12a2a6a07863ec28077 5555555555555555 555555552a6a0786
+r pextrd $2 200d17261638b12a2a6a07863ec28077 5555555555555555 000000001638b12a
+m pextrd $2 200d17261638b12a2a6a07863ec28077 5555555555555555 555555551638b12a
+r pextrd $3 200d17261638b12a2a6a07863ec28077 5555555555555555 00000000200d1726
+m pextrd $3 200d17261638b12a2a6a07863ec28077 5555555555555555 55555555200d1726
+r pextrq $0 31005fb9ada2074bf63a63fedcb4d29c 5555555555555555 f63a63fedcb4d29c
+m pextrq $0 31005fb9ada2074bf63a63fedcb4d29c 5555555555555555 f63a63fedcb4d29c
+r pextrq $1 31005fb9ada2074bf63a63fedcb4d29c 5555555555555555 31005fb9ada2074b
+m pextrq $1 31005fb9ada2074bf63a63fedcb4d29c 5555555555555555 31005fb9ada2074b
+r pextrw $0 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 00000000000003bb
+m pextrw $0 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 55555555555503bb
+r pextrw $1 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 000000000000e4e7
+m pextrw $1 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 555555555555e4e7
+r pextrw $2 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 000000000000eb65
+m pextrw $2 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 555555555555eb65
+r pextrw $3 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 0000000000007446
+m pextrw $3 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 5555555555557446
+r pextrw $4 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 000000000000c535
+m pextrw $4 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 555555555555c535
+r pextrw $5 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 000000000000dc9a
+m pextrw $5 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 555555555555dc9a
+r pextrw $6 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 0000000000001736
+m pextrw $6 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 5555555555551736
+r pextrw $7 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 0000000000003f87
+m pextrw $7 3f871736dc9ac5357446eb65e4e703bb 5555555555555555 5555555555553f87
+r pinsrq $0 895bccaa47e097b0 55555555555555555555555555555555 5555555555555555895bccaa47e097b0
+m pinsrq $0 895bccaa47e097b0 55555555555555555555555555555555 5555555555555555895bccaa47e097b0
+r pinsrq $1 cca141e659f05e44 55555555555555555555555555555555 cca141e659f05e445555555555555555
+m pinsrq $1 cca141e659f05e44 55555555555555555555555555555555 cca141e659f05e445555555555555555
+r pinsrd $0 1b02356292609995 55555555555555555555555555555555 55555555555555555555555592609995
+m pinsrd $0 1b02356292609995 55555555555555555555555555555555 55555555555555555555555592609995
+r pinsrd $1 573419ef40779c1c 55555555555555555555555555555555 555555555555555540779c1c55555555
+m pinsrd $1 573419ef40779c1c 55555555555555555555555555555555 555555555555555540779c1c55555555
+r pinsrd $2 e8ff541e946b13ef 55555555555555555555555555555555 55555555946b13ef5555555555555555
+m pinsrd $2 e8ff541e946b13ef 55555555555555555555555555555555 55555555946b13ef5555555555555555
+r pinsrd $3 7bf503fb681ebd83 55555555555555555555555555555555 681ebd83555555555555555555555555
+m pinsrd $3 7bf503fb681ebd83 55555555555555555555555555555555 681ebd83555555555555555555555555
+r pinsrw $0 c439bad3fae03069 55555555555555555555555555555555 55555555555555555555555555553069
+m pinsrw $0 c439bad3fae03069 55555555555555555555555555555555 55555555555555555555555555553069
+r pinsrw $1 3d3c42eeaf329813 55555555555555555555555555555555 55555555555555555555555598135555
+m pinsrw $1 3d3c42eeaf329813 55555555555555555555555555555555 55555555555555555555555598135555
+r pinsrw $2 e5795953d180798f 55555555555555555555555555555555 55555555555555555555798f55555555
+m pinsrw $2 e5795953d180798f 55555555555555555555555555555555 55555555555555555555798f55555555
+r pinsrw $3 033f758952e56949 55555555555555555555555555555555 55555555555555556949555555555555
+m pinsrw $3 033f758952e56949 55555555555555555555555555555555 55555555555555556949555555555555
+r pinsrw $4 e166815387e9d7cc 55555555555555555555555555555555 555555555555d7cc5555555555555555
+m pinsrw $4 e166815387e9d7cc 55555555555555555555555555555555 555555555555d7cc5555555555555555
+r pinsrw $5 92179f72ef45c780 55555555555555555555555555555555 55555555c78055555555555555555555
+m pinsrw $5 92179f72ef45c780 55555555555555555555555555555555 55555555c78055555555555555555555
+r pinsrw $6 ae87e666ea9c946c 55555555555555555555555555555555 5555946c555555555555555555555555
+m pinsrw $6 ae87e666ea9c946c 55555555555555555555555555555555 5555946c555555555555555555555555
+r pinsrw $7 11ba222c8341adf4 55555555555555555555555555555555 adf45555555555555555555555555555
+m pinsrw $7 11ba222c8341adf4 55555555555555555555555555555555 adf45555555555555555555555555555
+r pinsrb $0 9f4397ff27f65a9a 55555555555555555555555555555555 5555555555555555555555555555559a
+m pinsrb $0 9f4397ff27f65a9a 55555555555555555555555555555555 5555555555555555555555555555559a
+r pinsrb $1 0301be1a6caa75bf 55555555555555555555555555555555 5555555555555555555555555555bf55
+m pinsrb $1 0301be1a6caa75bf 55555555555555555555555555555555 5555555555555555555555555555bf55
+r pinsrb $2 6ce30772cb393162 55555555555555555555555555555555 55555555555555555555555555625555
+m pinsrb $2 6ce30772cb393162 55555555555555555555555555555555 55555555555555555555555555625555
+r pinsrb $3 50a3967f672fd7de 55555555555555555555555555555555 555555555555555555555555de555555
+m pinsrb $3 50a3967f672fd7de 55555555555555555555555555555555 555555555555555555555555de555555
+r pinsrb $4 2a8d07f3c58484af 55555555555555555555555555555555 5555555555555555555555af55555555
+m pinsrb $4 2a8d07f3c58484af 55555555555555555555555555555555 5555555555555555555555af55555555
+r pinsrb $5 3c382b7f925fed2c 55555555555555555555555555555555 555555555555555555552c5555555555
+m pinsrb $5 3c382b7f925fed2c 55555555555555555555555555555555 555555555555555555552c5555555555
+r pinsrb $6 4e4ac99461d51c4c 55555555555555555555555555555555 5555555555555555554c555555555555
+m pinsrb $6 4e4ac99461d51c4c 55555555555555555555555555555555 5555555555555555554c555555555555
+r pinsrb $7 6d365e1e6aaa3164 55555555555555555555555555555555 55555555555555556455555555555555
+m pinsrb $7 6d365e1e6aaa3164 55555555555555555555555555555555 55555555555555556455555555555555
+r pinsrb $8 ad00dd4a4d0d23e6 55555555555555555555555555555555 55555555555555e65555555555555555
+m pinsrb $8 ad00dd4a4d0d23e6 55555555555555555555555555555555 55555555555555e65555555555555555
+r pinsrb $9 e8f6713fcd5f7d23 55555555555555555555555555555555 55555555555523555555555555555555
+m pinsrb $9 e8f6713fcd5f7d23 55555555555555555555555555555555 55555555555523555555555555555555
+r pinsrb $10 7e7737e796eb2108 55555555555555555555555555555555 55555555550855555555555555555555
+m pinsrb $10 7e7737e796eb2108 55555555555555555555555555555555 55555555550855555555555555555555
+r pinsrb $11 13af05a6f8ae09e3 55555555555555555555555555555555 55555555e35555555555555555555555
+m pinsrb $11 13af05a6f8ae09e3 55555555555555555555555555555555 55555555e35555555555555555555555
+r pinsrb $12 55572620ab0f011d 55555555555555555555555555555555 5555551d555555555555555555555555
+m pinsrb $12 55572620ab0f011d 55555555555555555555555555555555 5555551d555555555555555555555555
+r pinsrb $13 b4781cf689a66f00 55555555555555555555555555555555 55550055555555555555555555555555
+m pinsrb $13 b4781cf689a66f00 55555555555555555555555555555555 55550055555555555555555555555555
+r pinsrb $14 28275d8857f70c71 55555555555555555555555555555555 55715555555555555555555555555555
+m pinsrb $14 28275d8857f70c71 55555555555555555555555555555555 55715555555555555555555555555555
+r pinsrb $15 ef4917b37e37a9b5 55555555555555555555555555555555 b5555555555555555555555555555555
+m pinsrb $15 ef4917b37e37a9b5 55555555555555555555555555555555 b5555555555555555555555555555555
+r pmaxsb 1f1030333fb8fa4b2feb05cb92ed4f4d 385e4166df2141ad63a8769192481679 385e41663f21414b63eb76cb92484f79
+m pmaxsb 1f1030333fb8fa4b2feb05cb92ed4f4d 385e4166df2141ad63a8769192481679 385e41663f21414b63eb76cb92484f79
+r pmaxsb dbacfa35b7d2b75af8ad6b99bb3fa4c2 c673c91ec9aed3f8b9c3e32f2103009d db73fa35c9d2d35af8c36b2f213f00c2
+m pmaxsb dbacfa35b7d2b75af8ad6b99bb3fa4c2 c673c91ec9aed3f8b9c3e32f2103009d db73fa35c9d2d35af8c36b2f213f00c2
+r pmaxsb 928efefdf9f5ec8d5313bd01b82612e0 bc36ca100a4a3a7d5127ba1c529aa0bf bc36fe100a4a3a7d5327bd1c522612e0
+m pmaxsb 928efefdf9f5ec8d5313bd01b82612e0 bc36ca100a4a3a7d5127ba1c529aa0bf bc36fe100a4a3a7d5327bd1c522612e0
+r pmaxsb 9f043af6a1aed58f1ee978efa4b054d2 76f140aa4182b4e706a17746411ab40c 760440f641aed5e71ee97846411a540c
+m pmaxsb 9f043af6a1aed58f1ee978efa4b054d2 76f140aa4182b4e706a17746411ab40c 760440f641aed5e71ee97846411a540c
+r pmaxsb 5e58aa8b4c88ae0d34fa174f9ce927c4 51f2275707e17ae4b3fd9698098ef5b0 5e5827574ce17a0d34fd174f09e927c4
+m pmaxsb 5e58aa8b4c88ae0d34fa174f9ce927c4 51f2275707e17ae4b3fd9698098ef5b0 5e5827574ce17a0d34fd174f09e927c4
+r pmaxsb 2ad7482a960fb2b27014160ebbdb47e4 a7837c83faf3cb1d360794fec60222d6 2ad77c2afa0fcb1d7014160ec60247e4
+m pmaxsb 2ad7482a960fb2b27014160ebbdb47e4 a7837c83faf3cb1d360794fec60222d6 2ad77c2afa0fcb1d7014160ec60247e4
+r pmaxsb 61cd123e19cf1e2bb001f1161e946f5c d5f13a9ab645e140698bec649583f5aa 61f13a3e19451e406901f1641e946f5c
+m pmaxsb 61cd123e19cf1e2bb001f1161e946f5c d5f13a9ab645e140698bec649583f5aa 61f13a3e19451e406901f1641e946f5c
+r pmaxsb 5e86033374552e23ce8e2455e0205c58 37885d08d662faf92a541ab7911c2b5a 5e885d3374622e232a542455e0205c5a
+m pmaxsb 5e86033374552e23ce8e2455e0205c58 37885d08d662faf92a541ab7911c2b5a 5e885d3374622e232a542455e0205c5a
+r pmaxsb 7c4e1775412d1d47a8872cb61d8aca05 2993e139f7d64ff4532f9ae1d7da8010 7c4e1775412d4f47532f2ce11ddaca10
+m pmaxsb 7c4e1775412d1d47a8872cb61d8aca05 2993e139f7d64ff4532f9ae1d7da8010 7c4e1775412d4f47532f2ce11ddaca10
+r pmaxsb 19714a711ce1284318b88425f2de758f 0760c299b42e1fdcc2e9e9cf82c7aff8 19714a711c2e284318e9e925f2de75f8
+m pmaxsb 19714a711ce1284318b88425f2de758f 0760c299b42e1fdcc2e9e9cf82c7aff8 19714a711c2e284318e9e925f2de75f8
+r pmaxsd 8f3a9991a2ff8bc2fceca88e7b281821 2d39fd95a9f5a45d514c816eaff2763f 2d39fd95a9f5a45d514c816e7b281821
+m pmaxsd 8f3a9991a2ff8bc2fceca88e7b281821 2d39fd95a9f5a45d514c816eaff2763f 2d39fd95a9f5a45d514c816e7b281821
+r pmaxsd 3cf6fe426e1281712ef114ddd37570e8 f76b8d9773b81b24de24e0a879648e11 3cf6fe4273b81b242ef114dd79648e11
+m pmaxsd 3cf6fe426e1281712ef114ddd37570e8 f76b8d9773b81b24de24e0a879648e11 3cf6fe4273b81b242ef114dd79648e11
+r pmaxsd 7af177f11da748fc8b9145fe16d0390f c1426e0dae01c0dd433f816bfd2bb699 7af177f11da748fc433f816b16d0390f
+m pmaxsd 7af177f11da748fc8b9145fe16d0390f c1426e0dae01c0dd433f816bfd2bb699 7af177f11da748fc433f816b16d0390f
+r pmaxsd a77700084a491a0ef099b6dd61462ec3 e70a9c61f55fce335d68e1a25652a804 e70a9c614a491a0e5d68e1a261462ec3
+m pmaxsd a77700084a491a0ef099b6dd61462ec3 e70a9c61f55fce335d68e1a25652a804 e70a9c614a491a0e5d68e1a261462ec3
+r pmaxsd 1dd493f59184345437d5e366d0e20c30 c50f1401e45b82d3086a7a39a1e6217d 1dd493f5e45b82d337d5e366d0e20c30
+m pmaxsd 1dd493f59184345437d5e366d0e20c30 c50f1401e45b82d3086a7a39a1e6217d 1dd493f5e45b82d337d5e366d0e20c30
+r pmaxsd 3a542e238fe5d1793d1148867eb08f81 b79cd058188318692112ca1cf9f1dd31 3a542e23188318693d1148867eb08f81
+m pmaxsd 3a542e238fe5d1793d1148867eb08f81 b79cd058188318692112ca1cf9f1dd31 3a542e23188318693d1148867eb08f81
+r pmaxsd 5842cbfee0f72e2ade18612787bc73e3 19ffced22c62cba0822c4c377b82984c 5842cbfe2c62cba0de1861277b82984c
+m pmaxsd 5842cbfee0f72e2ade18612787bc73e3 19ffced22c62cba0822c4c377b82984c 5842cbfe2c62cba0de1861277b82984c
+r pmaxsd d4ec68f21f468712f7b8ab3708137382 478209dbbd84d92508847c7642a20df9 478209db1f46871208847c7642a20df9
+m pmaxsd d4ec68f21f468712f7b8ab3708137382 478209dbbd84d92508847c7642a20df9 478209db1f46871208847c7642a20df9
+r pmaxsd 0b9c016be95f18de62bba1a11cc04c89 9c727edf66767ca38fe6d7c56a5ff965 0b9c016b66767ca362bba1a16a5ff965
+m pmaxsd 0b9c016be95f18de62bba1a11cc04c89 9c727edf66767ca38fe6d7c56a5ff965 0b9c016b66767ca362bba1a16a5ff965
+r pmaxsd 579f90d5d9cd1c3afceebf50e0d0ba24 761b274ac4c4f0c7f31ed81010c417bc 761b274ad9cd1c3afceebf5010c417bc
+m pmaxsd 579f90d5d9cd1c3afceebf50e0d0ba24 761b274ac4c4f0c7f31ed81010c417bc 761b274ad9cd1c3afceebf5010c417bc
+r pmaxud 1541139c8b1cd0d1a11d81326f4e7880 30c9028972f8733d11f7fa4450de2529 30c902898b1cd0d1a11d81326f4e7880
+m pmaxud 1541139c8b1cd0d1a11d81326f4e7880 30c9028972f8733d11f7fa4450de2529 30c902898b1cd0d1a11d81326f4e7880
+r pmaxud a1cd852d9cd970502d146432e64644c9 25c80a060da03fb0c33ebc4b44b8ddd8 a1cd852d9cd97050c33ebc4be64644c9
+m pmaxud a1cd852d9cd970502d146432e64644c9 25c80a060da03fb0c33ebc4b44b8ddd8 a1cd852d9cd97050c33ebc4be64644c9
+r pmaxud 5791e2f2a78f37627c9fe23c60c5d82b b3633c2f304791cde6c097130b5efcf6 b3633c2fa78f3762e6c0971360c5d82b
+m pmaxud 5791e2f2a78f37627c9fe23c60c5d82b b3633c2f304791cde6c097130b5efcf6 b3633c2fa78f3762e6c0971360c5d82b
+r pmaxud 94d7265949ca62b46a8a793cf9d5f0d1 35e7926e777aa43f56470887bfdd3daf 94d72659777aa43f6a8a793cf9d5f0d1
+m pmaxud 94d7265949ca62b46a8a793cf9d5f0d1 35e7926e777aa43f56470887bfdd3daf 94d72659777aa43f6a8a793cf9d5f0d1
+r pmaxud b2ed4ecc1e172df2d3a0a41fce854ae7 06a10a317fc4b5b3ef9f8c927c405d2f b2ed4ecc7fc4b5b3ef9f8c92ce854ae7
+m pmaxud b2ed4ecc1e172df2d3a0a41fce854ae7 06a10a317fc4b5b3ef9f8c927c405d2f b2ed4ecc7fc4b5b3ef9f8c92ce854ae7
+r pmaxud 0e1d55b9c001d4c793aee0cffbdea09a 84db9fe3e4b100d48d969e225f9318a0 84db9fe3e4b100d493aee0cffbdea09a
+m pmaxud 0e1d55b9c001d4c793aee0cffbdea09a 84db9fe3e4b100d48d969e225f9318a0 84db9fe3e4b100d493aee0cffbdea09a
+r pmaxud 04b4378bce1492e08680a7399beeae16 09e14df041cdc14f0bf7ba2283e22a31 09e14df0ce1492e08680a7399beeae16
+m pmaxud 04b4378bce1492e08680a7399beeae16 09e14df041cdc14f0bf7ba2283e22a31 09e14df0ce1492e08680a7399beeae16
+r pmaxud f0fdf0aee1dda4e888e2774acbc13287 f30110c432a534d0478d5d7e053a4e0c f30110c4e1dda4e888e2774acbc13287
+m pmaxud f0fdf0aee1dda4e888e2774acbc13287 f30110c432a534d0478d5d7e053a4e0c f30110c4e1dda4e888e2774acbc13287
+r pmaxud 2e467d8e98e7468c75a0cbeda561e618 9c86e5cb54c594021c25022200a7415e 9c86e5cb98e7468c75a0cbeda561e618
+m pmaxud 2e467d8e98e7468c75a0cbeda561e618 9c86e5cb54c594021c25022200a7415e 9c86e5cb98e7468c75a0cbeda561e618
+r pmaxud 1adad8978cbfb47829861f0d48dc87f5 62bbc77143b71e92668b24fb9133bf52 62bbc7718cbfb478668b24fb9133bf52
+m pmaxud 1adad8978cbfb47829861f0d48dc87f5 62bbc77143b71e92668b24fb9133bf52 62bbc7718cbfb478668b24fb9133bf52
+r pmaxuw 1004ff355bf02957805ff098ce3ed14b 9fedb2229a090d2c018b42f3d3ec8415 9fedff359a092957805ff098d3ecd14b
+m pmaxuw 1004ff355bf02957805ff098ce3ed14b 9fedb2229a090d2c018b42f3d3ec8415 9fedff359a092957805ff098d3ecd14b
+r pmaxuw 6c11edd5a106e2d655f9b97953917f46 b168a24af5479e7bc9f1d5f8e2de4bd3 b168edd5f547e2d6c9f1d5f8e2de7f46
+m pmaxuw 6c11edd5a106e2d655f9b97953917f46 b168a24af5479e7bc9f1d5f8e2de4bd3 b168edd5f547e2d6c9f1d5f8e2de7f46
+r pmaxuw 894d9fe1f98d1aa0861ef69cf4e34e11 f2789356f1fb0d2b99885af4db13d1b7 f2789fe1f98d1aa09988f69cf4e3d1b7
+m pmaxuw 894d9fe1f98d1aa0861ef69cf4e34e11 f2789356f1fb0d2b99885af4db13d1b7 f2789fe1f98d1aa09988f69cf4e3d1b7
+r pmaxuw c5040fc700120f62ee9b23edcc40fad9 bf6982b029b396ea4f1e4ed5da99d2ee c50482b029b396eaee9b4ed5da99fad9
+m pmaxuw c5040fc700120f62ee9b23edcc40fad9 bf6982b029b396ea4f1e4ed5da99d2ee c50482b029b396eaee9b4ed5da99fad9
+r pmaxuw 7b813bf15120fbc8683cbc58f8b23fca 74876ac63afb7562c67d2c86fa7c09a3 7b816ac65120fbc8c67dbc58fa7c3fca
+m pmaxuw 7b813bf15120fbc8683cbc58f8b23fca 74876ac63afb7562c67d2c86fa7c09a3 7b816ac65120fbc8c67dbc58fa7c3fca
+r pmaxuw 07121ecd88441b7dd2cc3eca9347d80f 6e1d4703bf5de53fd97270f257c73303 6e1d4703bf5de53fd97270f29347d80f
+m pmaxuw 07121ecd88441b7dd2cc3eca9347d80f 6e1d4703bf5de53fd97270f257c73303 6e1d4703bf5de53fd97270f29347d80f
+r pmaxuw c501b4c64209aa2e0719232dba0b82d5 077815d35567232e66c997070e860c39 c501b4c65567aa2e66c99707ba0b82d5
+m pmaxuw c501b4c64209aa2e0719232dba0b82d5 077815d35567232e66c997070e860c39 c501b4c65567aa2e66c99707ba0b82d5
+r pmaxuw 109cfa471afbe686e2ede96f8809f947 9ce5d1a297a56adb474e1bb03bc55073 9ce5fa4797a5e686e2ede96f8809f947
+m pmaxuw 109cfa471afbe686e2ede96f8809f947 9ce5d1a297a56adb474e1bb03bc55073 9ce5fa4797a5e686e2ede96f8809f947
+r pmaxuw 462deabeada6093241150c7a1a4df892 89ad76dc21a1f8f15acd7ad9f991bada 89adeabeada6f8f15acd7ad9f991f892
+m pmaxuw 462deabeada6093241150c7a1a4df892 89ad76dc21a1f8f15acd7ad9f991bada 89adeabeada6f8f15acd7ad9f991f892
+r pmaxuw c201829797974fddfe5d063c8be33ce1 2a1f00ed91e9071d79112f6f64f5079c c201829797974fddfe5d2f6f8be33ce1
+m pmaxuw c201829797974fddfe5d063c8be33ce1 2a1f00ed91e9071d79112f6f64f5079c c201829797974fddfe5d2f6f8be33ce1
+r pminsb df63bd3c7359f634f791559ff8d88161 db866b418009d40a82e7b65c99fdf3e5 db86bd3c8009d40a8291b69f99d881e5
+m pminsb df63bd3c7359f634f791559ff8d88161 db866b418009d40a82e7b65c99fdf3e5 db86bd3c8009d40a8291b69f99d881e5
+r pminsb fba1981add7938e3067d74917c37833e f82db3448c8c9a654f1c8c8db3b639e1 f8a1981a8c8c9ae3061c8c8db3b683e1
+m pminsb fba1981add7938e3067d74917c37833e f82db3448c8c9a654f1c8c8db3b639e1 f8a1981a8c8c9ae3061c8c8db3b683e1
+r pminsb 70050d9d7282529509eddffd330cfda3 de62d56351fe96dabe7a2cefcf2b96bb de05d59d51829695beeddfefcf0c96a3
+m pminsb 70050d9d7282529509eddffd330cfda3 de62d56351fe96dabe7a2cefcf2b96bb de05d59d51829695beeddfefcf0c96a3
+r pminsb 9cdd1a32cd007ff7daac12cf3a64acbd e76fcc086aeb0414a9cd126c0869c6a0 9cddcc08cdeb04f7a9ac12cf0864aca0
+m pminsb 9cdd1a32cd007ff7daac12cf3a64acbd e76fcc086aeb0414a9cd126c0869c6a0 9cddcc08cdeb04f7a9ac12cf0864aca0
+r pminsb d973ba438b80fdb556878af3ad4a4cb8 6fa194a173e020c0ede3baf27b7b85bb d9a194a18b80fdb5ed878af2ad4a85b8
+m pminsb d973ba438b80fdb556878af3ad4a4cb8 6fa194a173e020c0ede3baf27b7b85bb d9a194a18b80fdb5ed878af2ad4a85b8
+r pminsb 8514e93e478d067a5a4ac156a6cb98bf d4442998096825896787a06c436d8e39 8514e998098d06895a87a056a6cb8ebf
+m pminsb 8514e93e478d067a5a4ac156a6cb98bf d4442998096825896787a06c436d8e39 8514e998098d06895a87a056a6cb8ebf
+r pminsb fa0ba48e9db3d6f2c0c135e244f24dfe 71a4885bc70f501cf18441c67d4b9e45 faa4888e9db3d6f2c08435c644f29efe
+m pminsb fa0ba48e9db3d6f2c0c135e244f24dfe 71a4885bc70f501cf18441c67d4b9e45 faa4888e9db3d6f2c08435c644f29efe
+r pminsb 95a6e59e2a7fabcb65b86284a1cb27a3 a20cab554a62dd2468a718ec4422710c 95a6ab9e2a62abcb65a71884a1cb27a3
+m pminsb 95a6e59e2a7fabcb65b86284a1cb27a3 a20cab554a62dd2468a718ec4422710c 95a6ab9e2a62abcb65a71884a1cb27a3
+r pminsb b330aadc8a7cbfaf26fbc229d962e2d7 c3ca90f22dec084fa9bca1cab4fdc2ba b3ca90dc8aecbfafa9bca1cab4fdc2ba
+m pminsb b330aadc8a7cbfaf26fbc229d962e2d7 c3ca90f22dec084fa9bca1cab4fdc2ba b3ca90dc8aecbfafa9bca1cab4fdc2ba
+r pminsb aef4eeb358364f4add55d3bb09c439c9 3028339e0d3a0c468e8f584ceae94e7a aef4ee9e0d360c468e8fd3bbeac439c9
+m pminsb aef4eeb358364f4add55d3bb09c439c9 3028339e0d3a0c468e8f584ceae94e7a aef4ee9e0d360c468e8fd3bbeac439c9
+r pminsd e33fad8f313a964967940f284cfce9a3 45738ec585d726b8f4ecb95e02f1d179 e33fad8f85d726b8f4ecb95e02f1d179
+m pminsd e33fad8f313a964967940f284cfce9a3 45738ec585d726b8f4ecb95e02f1d179 e33fad8f85d726b8f4ecb95e02f1d179
+r pminsd af5de4ddb013d258a082f55bbf17ae91 5df79fd3324f914fb79f41ec172107e2 af5de4ddb013d258a082f55bbf17ae91
+m pminsd af5de4ddb013d258a082f55bbf17ae91 5df79fd3324f914fb79f41ec172107e2 af5de4ddb013d258a082f55bbf17ae91
+r pminsd 6c9a8e07714d3d2264ecfe407d2043c1 d6006035af2e8bb7b3736be34585abe2 d6006035af2e8bb7b3736be34585abe2
+m pminsd 6c9a8e07714d3d2264ecfe407d2043c1 d6006035af2e8bb7b3736be34585abe2 d6006035af2e8bb7b3736be34585abe2
+r pminsd 7742a77a117513548f9ea7c3a323665c 0bd9cf5599014e9dc435b32da92a7aa5 0bd9cf5599014e9d8f9ea7c3a323665c
+m pminsd 7742a77a117513548f9ea7c3a323665c 0bd9cf5599014e9dc435b32da92a7aa5 0bd9cf5599014e9d8f9ea7c3a323665c
+r pminsd 2ca02ba32b169299fd646dd04c2dd191 57d0e8a18b5417adc6b295b85f1c3056 2ca02ba38b5417adc6b295b84c2dd191
+m pminsd 2ca02ba32b169299fd646dd04c2dd191 57d0e8a18b5417adc6b295b85f1c3056 2ca02ba38b5417adc6b295b84c2dd191
+r pminsd e70216ec5cbcf49e8a09cb539549408a 182fa58322b1219295b48e6f81658922 e70216ec22b121928a09cb5381658922
+m pminsd e70216ec5cbcf49e8a09cb539549408a 182fa58322b1219295b48e6f81658922 e70216ec22b121928a09cb5381658922
+r pminsd 05b265c33ff4760f125b3d3899837173 a9430469f9a6aaf90d07193d2e134034 a9430469f9a6aaf90d07193d99837173
+m pminsd 05b265c33ff4760f125b3d3899837173 a9430469f9a6aaf90d07193d2e134034 a9430469f9a6aaf90d07193d99837173
+r pminsd e0fd1393714954977124406c74e81e7a 655800beacbeec8e0a79b210803112b9 e0fd1393acbeec8e0a79b210803112b9
+m pminsd e0fd1393714954977124406c74e81e7a 655800beacbeec8e0a79b210803112b9 e0fd1393acbeec8e0a79b210803112b9
+r pminsd d52f1cc78e47c9e383314ed9438203c8 aaba95edd88623fc68d5d5d393ccbadd aaba95ed8e47c9e383314ed993ccbadd
+m pminsd d52f1cc78e47c9e383314ed9438203c8 aaba95edd88623fc68d5d5d393ccbadd aaba95ed8e47c9e383314ed993ccbadd
+r pminsd 40947ccd307b129e244ee56d2260de8c d2b5bf6419898df003e6fe7283eff6cb d2b5bf6419898df003e6fe7283eff6cb
+m pminsd 40947ccd307b129e244ee56d2260de8c d2b5bf6419898df003e6fe7283eff6cb d2b5bf6419898df003e6fe7283eff6cb
+r pminud 7d772f10f5706b75304780122c8b69f0 3b947b8f0a536415b779aada6ea680b0 3b947b8f0a536415304780122c8b69f0
+m pminud 7d772f10f5706b75304780122c8b69f0 3b947b8f0a536415b779aada6ea680b0 3b947b8f0a536415304780122c8b69f0
+r pminud e82632fc79b30f1483e79bb67d116120 3fa5c4d84771e518605a54f56dfe15b7 3fa5c4d84771e518605a54f56dfe15b7
+m pminud e82632fc79b30f1483e79bb67d116120 3fa5c4d84771e518605a54f56dfe15b7 3fa5c4d84771e518605a54f56dfe15b7
+r pminud ddeb80fe57ce3c26f9fcb34432fe8249 3b3296ac6d6e4ba4d95578b09e02700d 3b3296ac57ce3c26d95578b032fe8249
+m pminud ddeb80fe57ce3c26f9fcb34432fe8249 3b3296ac6d6e4ba4d95578b09e02700d 3b3296ac57ce3c26d95578b032fe8249
+r pminud b71315802c502c586d5043a8665c8797 8c88ed7717d6d466003692f81dbe4ede 8c88ed7717d6d466003692f81dbe4ede
+m pminud b71315802c502c586d5043a8665c8797 8c88ed7717d6d466003692f81dbe4ede 8c88ed7717d6d466003692f81dbe4ede
+r pminud d4eaedef93c21b55bdb0c6ce36392d36 8cf3c5a6e236ba0ab0c81fb7053f6b55 8cf3c5a693c21b55b0c81fb7053f6b55
+m pminud d4eaedef93c21b55bdb0c6ce36392d36 8cf3c5a6e236ba0ab0c81fb7053f6b55 8cf3c5a693c21b55b0c81fb7053f6b55
+r pminud 8fbc05b829b247cac4e8bba2bda13050 98bf1ba36919393bc4d999db7390839e 8fbc05b829b247cac4d999db7390839e
+m pminud 8fbc05b829b247cac4e8bba2bda13050 98bf1ba36919393bc4d999db7390839e 8fbc05b829b247cac4d999db7390839e
+r pminud 44d5584589abea635dc49b10189f4c14 0d37eadc490b8fa61a337e4f82bd51e7 0d37eadc490b8fa61a337e4f189f4c14
+m pminud 44d5584589abea635dc49b10189f4c14 0d37eadc490b8fa61a337e4f82bd51e7 0d37eadc490b8fa61a337e4f189f4c14
+r pminud 4f80e2044f3a41cb6610e404623f3cac 45a92ebc1d99f6f68da34afe4ed3935a 45a92ebc1d99f6f66610e4044ed3935a
+m pminud 4f80e2044f3a41cb6610e404623f3cac 45a92ebc1d99f6f68da34afe4ed3935a 45a92ebc1d99f6f66610e4044ed3935a
+r pminud 0b0b9f6018e987aeba97106bb88dbd45 9d5fe4af824eabd8f8f577d6f4dd0223 0b0b9f6018e987aeba97106bb88dbd45
+m pminud 0b0b9f6018e987aeba97106bb88dbd45 9d5fe4af824eabd8f8f577d6f4dd0223 0b0b9f6018e987aeba97106bb88dbd45
+r pminud d6c08bc57f47f9ba34279d2f35968b0a 71a6062013b6eaf839f583c290e85d6f 71a6062013b6eaf834279d2f35968b0a
+m pminud d6c08bc57f47f9ba34279d2f35968b0a 71a6062013b6eaf839f583c290e85d6f 71a6062013b6eaf834279d2f35968b0a
+r pminuw 0beca39f21ddd399b28a073ef6656128 1eca927d6d5eee012a6fe8ae3cfe5e6a 0bec927d21ddd3992a6f073e3cfe5e6a
+m pminuw 0beca39f21ddd399b28a073ef6656128 1eca927d6d5eee012a6fe8ae3cfe5e6a 0bec927d21ddd3992a6f073e3cfe5e6a
+r pminuw 05dbe25a9a3951f70e8dc8821606fcca fe1783322bd1f4a0a92e2587172ec23f 05db83322bd151f70e8d25871606c23f
+m pminuw 05dbe25a9a3951f70e8dc8821606fcca fe1783322bd1f4a0a92e2587172ec23f 05db83322bd151f70e8d25871606c23f
+r pminuw 22d9446284e6ae8126fc5ee9b286181e 6ed9d5a9ea9b388090ffb3373b81451b 22d9446284e6388026fc5ee93b81181e
+m pminuw 22d9446284e6ae8126fc5ee9b286181e 6ed9d5a9ea9b388090ffb3373b81451b 22d9446284e6388026fc5ee93b81181e
+r pminuw bd31c5237e7128e3d4a3445ee5f0714d ca5b844f4549f54ebdaf0fabc405a22a bd31844f454928e3bdaf0fabc405714d
+m pminuw bd31c5237e7128e3d4a3445ee5f0714d ca5b844f4549f54ebdaf0fabc405a22a bd31844f454928e3bdaf0fabc405714d
+r pminuw 3131620a2265f8c8f64df6cdcb51c286 6eeb8d90d86668b60a08b6d0cfc59797 3131620a226568b60a08b6d0cb519797
+m pminuw 3131620a2265f8c8f64df6cdcb51c286 6eeb8d90d86668b60a08b6d0cfc59797 3131620a226568b60a08b6d0cb519797
+r pminuw dc2316810c4e5ddd66c8f02281b3c8f2 b6d3ebd9407ecd6355d7239077cddd8e b6d316810c4e5ddd55d7239077cdc8f2
+m pminuw dc2316810c4e5ddd66c8f02281b3c8f2 b6d3ebd9407ecd6355d7239077cddd8e b6d316810c4e5ddd55d7239077cdc8f2
+r pminuw 1854ddf6d8b991ce01deaf4923243fc0 fe609a94181e600278e7d2d9d92a333d 18549a94181e600201deaf492324333d
+m pminuw 1854ddf6d8b991ce01deaf4923243fc0 fe609a94181e600278e7d2d9d92a333d 18549a94181e600201deaf492324333d
+r pminuw 4210b3d32431d146a45cad2eccb0e21a a2de962ffdd15c3e50063f9610e753cd 4210962f24315c3e50063f9610e753cd
+m pminuw 4210b3d32431d146a45cad2eccb0e21a a2de962ffdd15c3e50063f9610e753cd 4210962f24315c3e50063f9610e753cd
+r pminuw b7a39486894259f1290e68be98626e2d fe98dc158b24fec4bafee7b33811fa6d b7a39486894259f1290e68be38116e2d
+m pminuw b7a39486894259f1290e68be98626e2d fe98dc158b24fec4bafee7b33811fa6d b7a39486894259f1290e68be38116e2d
+r pminuw d1587d7aa579647d6dc05be3a4469f24 6ddc67b25da28240909c451c6eb3e447 6ddc67b25da2647d6dc0451c6eb39f24
+m pminuw d1587d7aa579647d6dc05be3a4469f24 6ddc67b25da28240909c451c6eb3e447 6ddc67b25da2647d6dc0451c6eb39f24
+r pmovsxbw ee7d691b146130944d3d038a0b69312c 4df433720fd7245dafacd5bdced9cd88 004d003d0003ff8a000b00690031002c
+m pmovsxbw ee7d691b146130944d3d038a0b69312c 4df433720fd7245dafacd5bdced9cd88 004d003d0003ff8a000b00690031002c
+r pmovsxbw 685c54d57186f6e2a353dba0ead5df70 f92e3cc13e4f1fc8f3fa1382738f705b ffa30053ffdbffa0ffeaffd5ffdf0070
+m pmovsxbw 685c54d57186f6e2a353dba0ead5df70 f92e3cc13e4f1fc8f3fa1382738f705b ffa30053ffdbffa0ffeaffd5ffdf0070
+r pmovsxbw 9c423a145875f5144ccc5e105c99661d cdd47e0b8597b02c38527c577ae28aed 004cffcc005e0010005cff990066001d
+m pmovsxbw 9c423a145875f5144ccc5e105c99661d cdd47e0b8597b02c38527c577ae28aed 004cffcc005e0010005cff990066001d
+r pmovsxbw e77b184466b967d624750ac67ebe825f 2533f6bc813a13365b808a28feded669 00240075000affc6007effbeff82005f
+m pmovsxbw e77b184466b967d624750ac67ebe825f 2533f6bc813a13365b808a28feded669 00240075000affc6007effbeff82005f
+r pmovsxbw a353e8d137de89d3071b5bad6b52ee61 5c979f40cdc58392364fbbe21b8d12fc 0007001b005bffad006b0052ffee0061
+m pmovsxbw a353e8d137de89d3071b5bad6b52ee61 5c979f40cdc58392364fbbe21b8d12fc 0007001b005bffad006b0052ffee0061
+r pmovsxbw 2d16a827667197b8d187cbb340606850 d04b750405c33deba68d8a6feefdf8d2 ffd1ff87ffcbffb30040006000680050
+m pmovsxbw 2d16a827667197b8d187cbb340606850 d04b750405c33deba68d8a6feefdf8d2 ffd1ff87ffcbffb30040006000680050
+r pmovsxbw e11053b38ffdcd305e88d8c318f5aa57 dc9d7472c7c07dee870474bd92394516 005eff88ffd8ffc30018fff5ffaa0057
+m pmovsxbw e11053b38ffdcd305e88d8c318f5aa57 dc9d7472c7c07dee870474bd92394516 005eff88ffd8ffc30018fff5ffaa0057
+r pmovsxbw 1b8ce6e04f0e66e88ae9fdca101c70a3 dbd798f8ac487f46b581f3b7244eb4f5 ff8affe9fffdffca0010001c0070ffa3
+m pmovsxbw 1b8ce6e04f0e66e88ae9fdca101c70a3 dbd798f8ac487f46b581f3b7244eb4f5 ff8affe9fffdffca0010001c0070ffa3
+r pmovsxbw 37d75b1941319f8c3175b6b243e17860 2b46de0152e87ea00ccf8549bf47029a 00310075ffb6ffb20043ffe100780060
+m pmovsxbw 37d75b1941319f8c3175b6b243e17860 2b46de0152e87ea00ccf8549bf47029a 00310075ffb6ffb20043ffe100780060
+r pmovsxbw 913db0cc02f1b3c72ff97f68cd517cb9 263641f8552cb7a768bca55e8030eb32 002ffff9007f0068ffcd0051007cffb9
+m pmovsxbw 913db0cc02f1b3c72ff97f68cd517cb9 263641f8552cb7a768bca55e8030eb32 002ffff9007f0068ffcd0051007cffb9
+r pmovsxbd 850ae0642ddae0466041d5d9cb7738db 2af3bd4b509e6608a513cfe482162be8 ffffffcb0000007700000038ffffffdb
+m pmovsxbd 850ae0642ddae0466041d5d9cb7738db 2af3bd4b509e6608a513cfe482162be8 ffffffcb0000007700000038ffffffdb
+r pmovsxbd 6f8ae74d5f7960b4a01933ef595f6af1 91c94f65dfccc66f9e9f80c6e2047dea 000000590000005f0000006afffffff1
+m pmovsxbd 6f8ae74d5f7960b4a01933ef595f6af1 91c94f65dfccc66f9e9f80c6e2047dea 000000590000005f0000006afffffff1
+r pmovsxbd ab09c2f3335970becb4d15989216cc28 b903f1b29f411487312d32f1bb069e61 ffffff9200000016ffffffcc00000028
+m pmovsxbd ab09c2f3335970becb4d15989216cc28 b903f1b29f411487312d32f1bb069e61 ffffff9200000016ffffffcc00000028
+r pmovsxbd 95d26cc246074b10bda9f7bf92a71bac fcefa19f2c8a8cfd3989634f2a294a7c ffffff92ffffffa70000001bffffffac
+m pmovsxbd 95d26cc246074b10bda9f7bf92a71bac fcefa19f2c8a8cfd3989634f2a294a7c ffffff92ffffffa70000001bffffffac
+r pmovsxbd 8932e026330d2e5552f8564f761e13a8 b8d75a9620326a7d927f8ecd4a783d65 000000760000001e00000013ffffffa8
+m pmovsxbd 8932e026330d2e5552f8564f761e13a8 b8d75a9620326a7d927f8ecd4a783d65 000000760000001e00000013ffffffa8
+r pmovsxbd e3761d8b97fa553a6508ac365a886f48 470818041ac5e9b218db305838ff3248 0000005affffff880000006f00000048
+m pmovsxbd e3761d8b97fa553a6508ac365a886f48 470818041ac5e9b218db305838ff3248 0000005affffff880000006f00000048
+r pmovsxbd ffe81c5e0d57fc6ad4a3775f58f0ecba 06ced856b4d04648a668c3da0fcbe652 00000058fffffff0ffffffecffffffba
+m pmovsxbd ffe81c5e0d57fc6ad4a3775f58f0ecba 06ced856b4d04648a668c3da0fcbe652 00000058fffffff0ffffffecffffffba
+r pmovsxbd 39d4db0931b25e927a9632b68f624628 527594f68adebded1af4c541ebe715af ffffff8f000000620000004600000028
+m pmovsxbd 39d4db0931b25e927a9632b68f624628 527594f68adebded1af4c541ebe715af ffffff8f000000620000004600000028
+r pmovsxbd ed8854faa096b85e32ad5a2818eb39be 85484a52397b894a4f49b178e95f7a8a 00000018ffffffeb00000039ffffffbe
+m pmovsxbd ed8854faa096b85e32ad5a2818eb39be 85484a52397b894a4f49b178e95f7a8a 00000018ffffffeb00000039ffffffbe
+r pmovsxbd 764f859cf68f4679dab3699f129680a9 fc95f5d55c34e70e2034036b2540d210 00000012ffffff96ffffff80ffffffa9
+m pmovsxbd 764f859cf68f4679dab3699f129680a9 fc95f5d55c34e70e2034036b2540d210 00000012ffffff96ffffff80ffffffa9
+r pmovsxbq 32746a5ace2a448f4d76dd08966fd815 13a692ea909413e36b813705ba95d96d ffffffffffffffd80000000000000015
+m pmovsxbq 32746a5ace2a448f4d76dd08966fd815 13a692ea909413e36b813705ba95d96d ffffffffffffffd80000000000000015
+r pmovsxbq 7c44fda2c4f3ed4e66c03150c383fd2d 27c81bff702749760afcca34c46a4acc fffffffffffffffd000000000000002d
+m pmovsxbq 7c44fda2c4f3ed4e66c03150c383fd2d 27c81bff702749760afcca34c46a4acc fffffffffffffffd000000000000002d
+r pmovsxbq b00b3cdf75747e60035ee161b2ddaa1e 92478e7f987ac472db7137e460cce35a ffffffffffffffaa000000000000001e
+m pmovsxbq b00b3cdf75747e60035ee161b2ddaa1e 92478e7f987ac472db7137e460cce35a ffffffffffffffaa000000000000001e
+r pmovsxbq 2915227d7d3b3371fe1c6a2981899c14 b16fe6d6a518c184b9abfaffa9c65e42 ffffffffffffff9c0000000000000014
+m pmovsxbq 2915227d7d3b3371fe1c6a2981899c14 b16fe6d6a518c184b9abfaffa9c65e42 ffffffffffffff9c0000000000000014
+r pmovsxbq 45aeabe876d3472e35c647934c948f3a e08c1f71338e7c577f778f72bc6577b1 ffffffffffffff8f000000000000003a
+m pmovsxbq 45aeabe876d3472e35c647934c948f3a e08c1f71338e7c577f778f72bc6577b1 ffffffffffffff8f000000000000003a
+r pmovsxbq 5e21d38dffc9f7438228f38b2e093fbc 7be936badd6630980aa27329b5b3ecd2 000000000000003fffffffffffffffbc
+m pmovsxbq 5e21d38dffc9f7438228f38b2e093fbc 7be936badd6630980aa27329b5b3ecd2 000000000000003fffffffffffffffbc
+r pmovsxbq d2bc96d6b1a87f5bc30eedfc43f567c8 ded3251e3f2e1bf337f62011aebf77d2 0000000000000067ffffffffffffffc8
+m pmovsxbq d2bc96d6b1a87f5bc30eedfc43f567c8 ded3251e3f2e1bf337f62011aebf77d2 0000000000000067ffffffffffffffc8
+r pmovsxbq fbc9f1302bfc1b23d243aed4a862c488 6597ea0af6727713e0401415c692d5dd ffffffffffffffc4ffffffffffffff88
+m pmovsxbq fbc9f1302bfc1b23d243aed4a862c488 6597ea0af6727713e0401415c692d5dd ffffffffffffffc4ffffffffffffff88
+r pmovsxbq 3795df08065206478d94b3ff795f1228 6c7f80e89ebd80a5e34bca20163ac21e 00000000000000120000000000000028
+m pmovsxbq 3795df08065206478d94b3ff795f1228 6c7f80e89ebd80a5e34bca20163ac21e 00000000000000120000000000000028
+r pmovsxbq e06c5cc8e1357d72cece7967d1f50cd5 4fd7e326d29b74541ae5bf20bcc2f9c2 000000000000000cffffffffffffffd5
+m pmovsxbq e06c5cc8e1357d72cece7967d1f50cd5 4fd7e326d29b74541ae5bf20bcc2f9c2 000000000000000cffffffffffffffd5
+r pmovsxwd 549a65de5531bc5072bb7bf9cc326fbb 6aed102f2e988dcd62d86d00d43737f5 000072bb00007bf9ffffcc3200006fbb
+m pmovsxwd 549a65de5531bc5072bb7bf9cc326fbb 6aed102f2e988dcd62d86d00d43737f5 000072bb00007bf9ffffcc3200006fbb
+r pmovsxwd ed6bf4b500d2fe8f552735a28721f705 190c026f4f4108bb97f152ac79a338e2 00005527000035a2ffff8721fffff705
+m pmovsxwd ed6bf4b500d2fe8f552735a28721f705 190c026f4f4108bb97f152ac79a338e2 00005527000035a2ffff8721fffff705
+r pmovsxwd 082a07b97ea580d954e0244c1dcf60e0 b87fb552d02120cc96fce910c815b7b5 000054e00000244c00001dcf000060e0
+m pmovsxwd 082a07b97ea580d954e0244c1dcf60e0 b87fb552d02120cc96fce910c815b7b5 000054e00000244c00001dcf000060e0
+r pmovsxwd 022499566a367eda49b0c2e5ab476577 a29325444ec512a939c5af18dc96719b 000049b0ffffc2e5ffffab4700006577
+m pmovsxwd 022499566a367eda49b0c2e5ab476577 a29325444ec512a939c5af18dc96719b 000049b0ffffc2e5ffffab4700006577
+r pmovsxwd 35a6a7f8600f343f11658d574d95c3f7 35954eb164b81a015d181eb0d13422c0 00001165ffff8d5700004d95ffffc3f7
+m pmovsxwd 35a6a7f8600f343f11658d574d95c3f7 35954eb164b81a015d181eb0d13422c0 00001165ffff8d5700004d95ffffc3f7
+r pmovsxwd fefa2b0bfdbeddb488c900901dc5368c cccf2d05af86747edec1b4c5c4fa8650 ffff88c90000009000001dc50000368c
+m pmovsxwd fefa2b0bfdbeddb488c900901dc5368c cccf2d05af86747edec1b4c5c4fa8650 ffff88c90000009000001dc50000368c
+r pmovsxwd ba6d23fbddcfb6e48aa9987b39e47961 c38dbdaccabb5bcc988bec41d1f55876 ffff8aa9ffff987b000039e400007961
+m pmovsxwd ba6d23fbddcfb6e48aa9987b39e47961 c38dbdaccabb5bcc988bec41d1f55876 ffff8aa9ffff987b000039e400007961
+r pmovsxwd c34a8a359bcdfb7cf3d1cf04bdfd4aa3 751dfa1352e40c98674442111330555e fffff3d1ffffcf04ffffbdfd00004aa3
+m pmovsxwd c34a8a359bcdfb7cf3d1cf04bdfd4aa3 751dfa1352e40c98674442111330555e fffff3d1ffffcf04ffffbdfd00004aa3
+r pmovsxwd 76df5c23d344e7279f0d2317c41d637d 40c9e0a4e28cc38e27b63222a6b73935 ffff9f0d00002317ffffc41d0000637d
+m pmovsxwd 76df5c23d344e7279f0d2317c41d637d 40c9e0a4e28cc38e27b63222a6b73935 ffff9f0d00002317ffffc41d0000637d
+r pmovsxwd 2f76953322c0b8926a280fa06b4f801c 7fdf6bcd1740bc59b4ae395fa797c027 00006a2800000fa000006b4fffff801c
+m pmovsxwd 2f76953322c0b8926a280fa06b4f801c 7fdf6bcd1740bc59b4ae395fa797c027 00006a2800000fa000006b4fffff801c
+r pmovsxwq 4a5c32cf23cea86930f00f8bcd9f5fac 8da998f88c8b32a6eaf8d1b431daa560 ffffffffffffcd9f0000000000005fac
+m pmovsxwq 4a5c32cf23cea86930f00f8bcd9f5fac 8da998f88c8b32a6eaf8d1b431daa560 ffffffffffffcd9f0000000000005fac
+r pmovsxwq 23de2e6573f9f357cd2f9fc5071aba58 c8746293ddf96221a55f780d618fa50b 000000000000071affffffffffffba58
+m pmovsxwq 23de2e6573f9f357cd2f9fc5071aba58 c8746293ddf96221a55f780d618fa50b 000000000000071affffffffffffba58
+r pmovsxwq 16458560adcdd7091db23c3834cb4d4d 8a8cc509a7178875c1b1aa5552bf7b54 00000000000034cb0000000000004d4d
+m pmovsxwq 16458560adcdd7091db23c3834cb4d4d 8a8cc509a7178875c1b1aa5552bf7b54 00000000000034cb0000000000004d4d
+r pmovsxwq 7fe0332c6ed78e2afc4561d270bed6b6 313cbec68670df4e1ab8e17b2178e568 00000000000070beffffffffffffd6b6
+m pmovsxwq 7fe0332c6ed78e2afc4561d270bed6b6 313cbec68670df4e1ab8e17b2178e568 00000000000070beffffffffffffd6b6
+r pmovsxwq bafa353551a2546746b48a7dd8000fc0 17d247361590a45a8c419b68e9c69d73 ffffffffffffd8000000000000000fc0
+m pmovsxwq bafa353551a2546746b48a7dd8000fc0 17d247361590a45a8c419b68e9c69d73 ffffffffffffd8000000000000000fc0
+r pmovsxwq 23de85e7f3ba676cd7ca3327879cb597 9a985ec5f0031343f3185309c7b360a0 ffffffffffff879cffffffffffffb597
+m pmovsxwq 23de85e7f3ba676cd7ca3327879cb597 9a985ec5f0031343f3185309c7b360a0 ffffffffffff879cffffffffffffb597
+r pmovsxwq 16da21aeefac01e48b55d9bb9a9e8466 14dcfee0b45668b52a09854ad64de91c ffffffffffff9a9effffffffffff8466
+m pmovsxwq 16da21aeefac01e48b55d9bb9a9e8466 14dcfee0b45668b52a09854ad64de91c ffffffffffff9a9effffffffffff8466
+r pmovsxwq ef3804f7e2035f7c3d1ff6252d13375a e2e823f1fc15de5d0fe0ad1832a0f513 0000000000002d13000000000000375a
+m pmovsxwq ef3804f7e2035f7c3d1ff6252d13375a e2e823f1fc15de5d0fe0ad1832a0f513 0000000000002d13000000000000375a
+r pmovsxwq 0a452b2c674cbddfcbf508515b068b9e 6109ca6565cab2e77d69475df9b640b0 0000000000005b06ffffffffffff8b9e
+m pmovsxwq 0a452b2c674cbddfcbf508515b068b9e 6109ca6565cab2e77d69475df9b640b0 0000000000005b06ffffffffffff8b9e
+r pmovsxwq c34d90bb1a1256ba10a38a2b40833c5f eb8aeda98a0320fe506fd007449d8620 00000000000040830000000000003c5f
+m pmovsxwq c34d90bb1a1256ba10a38a2b40833c5f eb8aeda98a0320fe506fd007449d8620 00000000000040830000000000003c5f
+r pmovsxdq 759b310e98e167b9e8f5f99ff99706c8 ddb98a28084c634f63bfc3013161828e ffffffffe8f5f99ffffffffff99706c8
+m pmovsxdq 759b310e98e167b9e8f5f99ff99706c8 ddb98a28084c634f63bfc3013161828e ffffffffe8f5f99ffffffffff99706c8
+r pmovsxdq 7e7d09937d452c872eb7cf99a14da407 94e09c4d7a2fb98594259c37dc0df227 000000002eb7cf99ffffffffa14da407
+m pmovsxdq 7e7d09937d452c872eb7cf99a14da407 94e09c4d7a2fb98594259c37dc0df227 000000002eb7cf99ffffffffa14da407
+r pmovsxdq 393d14b564cbe1d0c0b48a0655b1d345 6a4d20867d3a5b4dbd6dd8955fad8f17 ffffffffc0b48a060000000055b1d345
+m pmovsxdq 393d14b564cbe1d0c0b48a0655b1d345 6a4d20867d3a5b4dbd6dd8955fad8f17 ffffffffc0b48a060000000055b1d345
+r pmovsxdq 02284fdfe9fec14278baa5d030d04fb1 bc4a103eacf98853bc63f107d94d1889 0000000078baa5d00000000030d04fb1
+m pmovsxdq 02284fdfe9fec14278baa5d030d04fb1 bc4a103eacf98853bc63f107d94d1889 0000000078baa5d00000000030d04fb1
+r pmovsxdq 348ab47fa96b098734939ce54eb5d374 e6246ae1a4f77a426cd3657964fa47a9 0000000034939ce5000000004eb5d374
+m pmovsxdq 348ab47fa96b098734939ce54eb5d374 e6246ae1a4f77a426cd3657964fa47a9 0000000034939ce5000000004eb5d374
+r pmovsxdq 2daf41013f9df44bce0cec2fcc6d1cbd 442729db00c06ec7a888afd71cbfd9a5 ffffffffce0cec2fffffffffcc6d1cbd
+m pmovsxdq 2daf41013f9df44bce0cec2fcc6d1cbd 442729db00c06ec7a888afd71cbfd9a5 ffffffffce0cec2fffffffffcc6d1cbd
+r pmovsxdq 48e3f1cf4820c03b24f10f9cc602e6b6 329e49985ce0a08d4e504c0d1ea88aa7 0000000024f10f9cffffffffc602e6b6
+m pmovsxdq 48e3f1cf4820c03b24f10f9cc602e6b6 329e49985ce0a08d4e504c0d1ea88aa7 0000000024f10f9cffffffffc602e6b6
+r pmovsxdq e072c1566081a703100e83175782ed8c 0cd7c78555e44c4138f5b60885c215db 00000000100e8317000000005782ed8c
+m pmovsxdq e072c1566081a703100e83175782ed8c 0cd7c78555e44c4138f5b60885c215db 00000000100e8317000000005782ed8c
+r pmovsxdq 53a7ab02214be64e702ec38c9cf9ec6a 2e1c9d0c8757ad8f43446bb26e18386e 00000000702ec38cffffffff9cf9ec6a
+m pmovsxdq 53a7ab02214be64e702ec38c9cf9ec6a 2e1c9d0c8757ad8f43446bb26e18386e 00000000702ec38cffffffff9cf9ec6a
+r pmovsxdq fbcfad402a0ab8c91e1f4ce7b072a07d f4bac99b8dc500224c09e6f9f4b7ac8c 000000001e1f4ce7ffffffffb072a07d
+m pmovsxdq fbcfad402a0ab8c91e1f4ce7b072a07d f4bac99b8dc500224c09e6f9f4b7ac8c 000000001e1f4ce7ffffffffb072a07d
+r pmovzxbw 3637c27a144a5b20f8ab9814aff9c5f0 bafd469c03bb81a72d0fa3c734a93060 00f800ab0098001400af00f900c500f0
+m pmovzxbw 3637c27a144a5b20f8ab9814aff9c5f0 bafd469c03bb81a72d0fa3c734a93060 00f800ab0098001400af00f900c500f0
+r pmovzxbw 5e28e61e7d9809fed89f25ffb69a16f0 dc31117d86c46bc9c3241e0a49fd7e17 00d8009f002500ff00b6009a001600f0
+m pmovzxbw 5e28e61e7d9809fed89f25ffb69a16f0 dc31117d86c46bc9c3241e0a49fd7e17 00d8009f002500ff00b6009a001600f0
+r pmovzxbw d1f115970180fe0f9bc76e95e06250a9 b6a224a9b26dfb35eb12d4ad50bc53dc 009b00c7006e009500e00062005000a9
+m pmovzxbw d1f115970180fe0f9bc76e95e06250a9 b6a224a9b26dfb35eb12d4ad50bc53dc 009b00c7006e009500e00062005000a9
+r pmovzxbw e9dd4c503b8c78011defefc04a5c2f46 a49c7d8b21406d977fa6409c64f46bdc 001d00ef00ef00c0004a005c002f0046
+m pmovzxbw e9dd4c503b8c78011defefc04a5c2f46 a49c7d8b21406d977fa6409c64f46bdc 001d00ef00ef00c0004a005c002f0046
+r pmovzxbw 033786b7c84ab17d3be2256e10956ff4 026a179172ccfc9a5caddec3a1b08243 003b00e20025006e00100095006f00f4
+m pmovzxbw 033786b7c84ab17d3be2256e10956ff4 026a179172ccfc9a5caddec3a1b08243 003b00e20025006e00100095006f00f4
+r pmovzxbw 7c4dbf374346e632cf6e8a894c18cbde 2c59ee263f9ae6eb5ef02a0e24fd533c 00cf006e008a0089004c001800cb00de
+m pmovzxbw 7c4dbf374346e632cf6e8a894c18cbde 2c59ee263f9ae6eb5ef02a0e24fd533c 00cf006e008a0089004c001800cb00de
+r pmovzxbw ae69f33c480a53cab65d9cff1df10031 7db5feb724386535623ea06909e69bf4 00b6005d009c00ff001d00f100000031
+m pmovzxbw ae69f33c480a53cab65d9cff1df10031 7db5feb724386535623ea06909e69bf4 00b6005d009c00ff001d00f100000031
+r pmovzxbw f6d81f33742433f2cc7dd6bb9c2cca19 53ca44aebd31b5254262bdc16b771596 00cc007d00d600bb009c002c00ca0019
+m pmovzxbw f6d81f33742433f2cc7dd6bb9c2cca19 53ca44aebd31b5254262bdc16b771596 00cc007d00d600bb009c002c00ca0019
+r pmovzxbw b0e63d866320c355ed98b4a9e8d6e4c1 09e4bb78a8121467db27fc0066bc7f4f 00ed009800b400a900e800d600e400c1
+m pmovzxbw b0e63d866320c355ed98b4a9e8d6e4c1 09e4bb78a8121467db27fc0066bc7f4f 00ed009800b400a900e800d600e400c1
+r pmovzxbw 39df4ba2b0883fa0f57ab3b51afb0c56 fb4f5f827e66bca6095bd91417c2934b 00f5007a00b300b5001a00fb000c0056
+m pmovzxbw 39df4ba2b0883fa0f57ab3b51afb0c56 fb4f5f827e66bca6095bd91417c2934b 00f5007a00b300b5001a00fb000c0056
+r pmovzxbd eb0e45f4f7eae27ec0f14ecb50a5fc04 84562c36ddb9ea8ea8c8d0e79a950eb5 00000050000000a5000000fc00000004
+m pmovzxbd eb0e45f4f7eae27ec0f14ecb50a5fc04 84562c36ddb9ea8ea8c8d0e79a950eb5 00000050000000a5000000fc00000004
+r pmovzxbd 23c025e6d5d2e99c2ac801d7a6e270f6 02471f026197d9cd943b5e67093fabba 000000a6000000e200000070000000f6
+m pmovzxbd 23c025e6d5d2e99c2ac801d7a6e270f6 02471f026197d9cd943b5e67093fabba 000000a6000000e200000070000000f6
+r pmovzxbd 3d42e9e6e5cb90a60fca48c537bd2658 cf6c3250a58dc60da980fe7f83ce2785 00000037000000bd0000002600000058
+m pmovzxbd 3d42e9e6e5cb90a60fca48c537bd2658 cf6c3250a58dc60da980fe7f83ce2785 00000037000000bd0000002600000058
+r pmovzxbd 95de8b5fc46113474bc49f812043d857 4912638e4626edfac3622c1b224d3e43 0000002000000043000000d800000057
+m pmovzxbd 95de8b5fc46113474bc49f812043d857 4912638e4626edfac3622c1b224d3e43 0000002000000043000000d800000057
+r pmovzxbd 87e109bc0d20ad2cba8283f87c7f421f cb85ad27dfef8a41beaf642702c9ac20 0000007c0000007f000000420000001f
+m pmovzxbd 87e109bc0d20ad2cba8283f87c7f421f cb85ad27dfef8a41beaf642702c9ac20 0000007c0000007f000000420000001f
+r pmovzxbd 6f975f6b5d959b0038d06f14677d22db b0100d870c73d98e7631228f404d2c47 000000670000007d00000022000000db
+m pmovzxbd 6f975f6b5d959b0038d06f14677d22db b0100d870c73d98e7631228f404d2c47 000000670000007d00000022000000db
+r pmovzxbd a94b87d74f4b1970a17adfc3fe4a32b8 56017d1a6a3e158cc6b5e33ff7e57be5 000000fe0000004a00000032000000b8
+m pmovzxbd a94b87d74f4b1970a17adfc3fe4a32b8 56017d1a6a3e158cc6b5e33ff7e57be5 000000fe0000004a00000032000000b8
+r pmovzxbd 914b7f6c80ce6328d14c4ff05df12fe2 17a2fb4c94dd7be88c072223439e5525 0000005d000000f10000002f000000e2
+m pmovzxbd 914b7f6c80ce6328d14c4ff05df12fe2 17a2fb4c94dd7be88c072223439e5525 0000005d000000f10000002f000000e2
+r pmovzxbd 83e142978babb4d3a4113b879f7ed584 5040828927db464ea3f35b2742837634 0000009f0000007e000000d500000084
+m pmovzxbd 83e142978babb4d3a4113b879f7ed584 5040828927db464ea3f35b2742837634 0000009f0000007e000000d500000084
+r pmovzxbd db5accc20d6d491ef5972073e0fedfcb 5e270e3ebfc4b369e7450a380da0993e 000000e0000000fe000000df000000cb
+m pmovzxbd db5accc20d6d491ef5972073e0fedfcb 5e270e3ebfc4b369e7450a380da0993e 000000e0000000fe000000df000000cb
+r pmovzxbq f502195aa1a15db4a2a879a23d7c0ae2 9ba39cd5f625fee533c9ac40c2027b6e 000000000000000a00000000000000e2
+m pmovzxbq f502195aa1a15db4a2a879a23d7c0ae2 9ba39cd5f625fee533c9ac40c2027b6e 000000000000000a00000000000000e2
+r pmovzxbq 2c2526cce3d22e428611c200d10412f6 640027bc6b896370654abc2d7db4d8f1 000000000000001200000000000000f6
+m pmovzxbq 2c2526cce3d22e428611c200d10412f6 640027bc6b896370654abc2d7db4d8f1 000000000000001200000000000000f6
+r pmovzxbq de0fee83708cf6737d9e7877b9a3b333 168aaa5db77c1eb35895b6ea59c26bf2 00000000000000b30000000000000033
+m pmovzxbq de0fee83708cf6737d9e7877b9a3b333 168aaa5db77c1eb35895b6ea59c26bf2 00000000000000b30000000000000033
+r pmovzxbq 660b6deae45bf2f5621a15f41064a8c4 0b8c2426798b6a5de77616637239f19e 00000000000000a800000000000000c4
+m pmovzxbq 660b6deae45bf2f5621a15f41064a8c4 0b8c2426798b6a5de77616637239f19e 00000000000000a800000000000000c4
+r pmovzxbq 20669f6fdacc5d7113531763f353aed5 a0538e824a418418f0b95884e5242620 00000000000000ae00000000000000d5
+m pmovzxbq 20669f6fdacc5d7113531763f353aed5 a0538e824a418418f0b95884e5242620 00000000000000ae00000000000000d5
+r pmovzxbq 676d807dee6a75966a13f9b17d7d8194 312ce5ddc92aa7904e2af939ce90c5a5 00000000000000810000000000000094
+m pmovzxbq 676d807dee6a75966a13f9b17d7d8194 312ce5ddc92aa7904e2af939ce90c5a5 00000000000000810000000000000094
+r pmovzxbq 996a0d80bdc2740e452737c8cbeddc2b 1a6126a38fd31173dc95746e47878c59 00000000000000dc000000000000002b
+m pmovzxbq 996a0d80bdc2740e452737c8cbeddc2b 1a6126a38fd31173dc95746e47878c59 00000000000000dc000000000000002b
+r pmovzxbq 11aa41e4e25f96857f5b4e96f8b07cc6 b83e4c403ac7fc6a78c5450f6f173567 000000000000007c00000000000000c6
+m pmovzxbq 11aa41e4e25f96857f5b4e96f8b07cc6 b83e4c403ac7fc6a78c5450f6f173567 000000000000007c00000000000000c6
+r pmovzxbq 2a781815facd19a8f37bb80620d01d92 651153206692a424fc88e808604c7cfc 000000000000001d0000000000000092
+m pmovzxbq 2a781815facd19a8f37bb80620d01d92 651153206692a424fc88e808604c7cfc 000000000000001d0000000000000092
+r pmovzxbq 42228e7fa19937237e53f304605c7bbb 7e2538b0aec1474b46a8d94636311f44 000000000000007b00000000000000bb
+m pmovzxbq 42228e7fa19937237e53f304605c7bbb 7e2538b0aec1474b46a8d94636311f44 000000000000007b00000000000000bb
+r pmovzxwd b3f2a08f714e2da1fdaf7a7cd45d516c 5fc5f55aaedf1f8b30f295b30ed2d86a 0000fdaf00007a7c0000d45d0000516c
+m pmovzxwd b3f2a08f714e2da1fdaf7a7cd45d516c 5fc5f55aaedf1f8b30f295b30ed2d86a 0000fdaf00007a7c0000d45d0000516c
+r pmovzxwd db3648af097836cf4a5aca5a97e15cd2 643e888b037969929732973d033b649a 00004a5a0000ca5a000097e100005cd2
+m pmovzxwd db3648af097836cf4a5aca5a97e15cd2 643e888b037969929732973d033b649a 00004a5a0000ca5a000097e100005cd2
+r pmovzxwd 1438844d02a38f5943215d8ac5f35818 e9dcecb04919610958335bce32797f02 0000432100005d8a0000c5f300005818
+m pmovzxwd 1438844d02a38f5943215d8ac5f35818 e9dcecb04919610958335bce32797f02 0000432100005d8a0000c5f300005818
+r pmovzxwd bc4550d3fa5c74eac2d1b1f87b9f006c 4aeb1e341b4e429f4dc35e54b697e4cc 0000c2d10000b1f800007b9f0000006c
+m pmovzxwd bc4550d3fa5c74eac2d1b1f87b9f006c 4aeb1e341b4e429f4dc35e54b697e4cc 0000c2d10000b1f800007b9f0000006c
+r pmovzxwd 2da9a6af8d2f212ea4344190d5f211f7 e3b7188215a149fe53ac1abaaba25024 0000a434000041900000d5f2000011f7
+m pmovzxwd 2da9a6af8d2f212ea4344190d5f211f7 e3b7188215a149fe53ac1abaaba25024 0000a434000041900000d5f2000011f7
+r pmovzxwd c5af844c56a6d2d3c616893fedf747e7 0f8bd808d4a0b2d247bb0dec2ea57f37 0000c6160000893f0000edf7000047e7
+m pmovzxwd c5af844c56a6d2d3c616893fedf747e7 0f8bd808d4a0b2d247bb0dec2ea57f37 0000c6160000893f0000edf7000047e7
+r pmovzxwd dea5e516f24fc282024505efe2bb5e68 2cb55931f3d6b9c803bdb2d65bac2c31 00000245000005ef0000e2bb00005e68
+m pmovzxwd dea5e516f24fc282024505efe2bb5e68 2cb55931f3d6b9c803bdb2d65bac2c31 00000245000005ef0000e2bb00005e68
+r pmovzxwd d5d5c579fcb62eea358c328ece4911a6 957f97690fcf998c647b85644dc3143d 0000358c0000328e0000ce49000011a6
+m pmovzxwd d5d5c579fcb62eea358c328ece4911a6 957f97690fcf998c647b85644dc3143d 0000358c0000328e0000ce49000011a6
+r pmovzxwd 078c20e1106551b53bb68b07cdad1dcc a6368e1cc3188fca46c4038221f7f388 00003bb600008b070000cdad00001dcc
+m pmovzxwd 078c20e1106551b53bb68b07cdad1dcc a6368e1cc3188fca46c4038221f7f388 00003bb600008b070000cdad00001dcc
+r pmovzxwd ce16f2bacbea6990f0908c45fcf43e06 bb263bb7ac3dd62d8563a61df253853d 0000f09000008c450000fcf400003e06
+m pmovzxwd ce16f2bacbea6990f0908c45fcf43e06 bb263bb7ac3dd62d8563a61df253853d 0000f09000008c450000fcf400003e06
+r pmovzxwq 87bf3870c9d1b02630e6b13676282f82 2f9b99a465c8ac61fd23ec1fdce48589 00000000000076280000000000002f82
+m pmovzxwq 87bf3870c9d1b02630e6b13676282f82 2f9b99a465c8ac61fd23ec1fdce48589 00000000000076280000000000002f82
+r pmovzxwq 8ed3ed6fa5a46224d78477c55858ae69 60e0a4508b474b138ad25076fcb5b098 0000000000005858000000000000ae69
+m pmovzxwq 8ed3ed6fa5a46224d78477c55858ae69 60e0a4508b474b138ad25076fcb5b098 0000000000005858000000000000ae69
+r pmovzxwq 409d0d24fbf1bd35c23659debd8d75ea a9435828b945f0ef083a4f0c6dd2c295 000000000000bd8d00000000000075ea
+m pmovzxwq 409d0d24fbf1bd35c23659debd8d75ea a9435828b945f0ef083a4f0c6dd2c295 000000000000bd8d00000000000075ea
+r pmovzxwq f76b95fa6844fb06cbc7d36dc1d5402f 650eb2968b4fd6a0532863cf4c4877ad 000000000000c1d5000000000000402f
+m pmovzxwq f76b95fa6844fb06cbc7d36dc1d5402f 650eb2968b4fd6a0532863cf4c4877ad 000000000000c1d5000000000000402f
+r pmovzxwq 10877f5c87275943cf05615f813bcd64 f28eac089ff03bd347680aaab4228a0b 000000000000813b000000000000cd64
+m pmovzxwq 10877f5c87275943cf05615f813bcd64 f28eac089ff03bd347680aaab4228a0b 000000000000813b000000000000cd64
+r pmovzxwq e73ec9b8f5291397a9ba7f9e19ccd6b6 aa0f44e98eb45934c0c5bf89c26cb8dc 00000000000019cc000000000000d6b6
+m pmovzxwq e73ec9b8f5291397a9ba7f9e19ccd6b6 aa0f44e98eb45934c0c5bf89c26cb8dc 00000000000019cc000000000000d6b6
+r pmovzxwq d8dc6e794dd364af37b3aa17a4931751 ebdd75a5f6276c6e9a0dfe589133bc4c 000000000000a4930000000000001751
+m pmovzxwq d8dc6e794dd364af37b3aa17a4931751 ebdd75a5f6276c6e9a0dfe589133bc4c 000000000000a4930000000000001751
+r pmovzxwq 3fad6a0b2cb3893654bc5db73e9c4e61 0f443ca873d6b22db10a44033e825486 0000000000003e9c0000000000004e61
+m pmovzxwq 3fad6a0b2cb3893654bc5db73e9c4e61 0f443ca873d6b22db10a44033e825486 0000000000003e9c0000000000004e61
+r pmovzxwq 78fcbada2d54bed9dca1146904f43511 7490935e9f4d651fe1890b76e4653ab7 00000000000004f40000000000003511
+m pmovzxwq 78fcbada2d54bed9dca1146904f43511 7490935e9f4d651fe1890b76e4653ab7 00000000000004f40000000000003511
+r pmovzxwq df175852ed423e44ab2d4b1812a6898d 740c78331916c2ee0656d19da0e92b0a 00000000000012a6000000000000898d
+m pmovzxwq df175852ed423e44ab2d4b1812a6898d 740c78331916c2ee0656d19da0e92b0a 00000000000012a6000000000000898d
+r pmovzxdq d04842df070a47229d2e7eb283be0602 6d05e6937bbf0446fc3d11658d19e2ac 000000009d2e7eb20000000083be0602
+m pmovzxdq d04842df070a47229d2e7eb283be0602 6d05e6937bbf0446fc3d11658d19e2ac 000000009d2e7eb20000000083be0602
+r pmovzxdq a7dc73ed183713208e6e2a227349679c b9c7d9eb61d469d49e0a48b8c8011cc8 000000008e6e2a22000000007349679c
+m pmovzxdq a7dc73ed183713208e6e2a227349679c b9c7d9eb61d469d49e0a48b8c8011cc8 000000008e6e2a22000000007349679c
+r pmovzxdq bf1fe8e9bb56dee959baca54ff526986 b59e4ea568df2b44ca89f0846cae958b 0000000059baca5400000000ff526986
+m pmovzxdq bf1fe8e9bb56dee959baca54ff526986 b59e4ea568df2b44ca89f0846cae958b 0000000059baca5400000000ff526986
+r pmovzxdq 765d9b3d8cf2e62adcdeda3442e5c8ed bed6402f2b6e86415b8587b3952b0921 00000000dcdeda340000000042e5c8ed
+m pmovzxdq 765d9b3d8cf2e62adcdeda3442e5c8ed bed6402f2b6e86415b8587b3952b0921 00000000dcdeda340000000042e5c8ed
+r pmovzxdq 27e28a572897658ef2a6d6ae590f40fd 2ebbabf3470db8782ccb8833608433b6 00000000f2a6d6ae00000000590f40fd
+m pmovzxdq 27e28a572897658ef2a6d6ae590f40fd 2ebbabf3470db8782ccb8833608433b6 00000000f2a6d6ae00000000590f40fd
+r pmovzxdq 2ef9b0a22bd197c376de3baf5fdb8ce1 62988b5f5746fb941b276fefe9c6d174 0000000076de3baf000000005fdb8ce1
+m pmovzxdq 2ef9b0a22bd197c376de3baf5fdb8ce1 62988b5f5746fb941b276fefe9c6d174 0000000076de3baf000000005fdb8ce1
+r pmovzxdq e7f00989302dba7246518421715669c6 b6badcdef8a78c420365b8d34bfc9c8a 000000004651842100000000715669c6
+m pmovzxdq e7f00989302dba7246518421715669c6 b6badcdef8a78c420365b8d34bfc9c8a 000000004651842100000000715669c6
+r pmovzxdq ad11927ad336084a3ccd2df1aa8a93d7 876d9bdcc5bca72ebf51e0cba2325322 000000003ccd2df100000000aa8a93d7
+m pmovzxdq ad11927ad336084a3ccd2df1aa8a93d7 876d9bdcc5bca72ebf51e0cba2325322 000000003ccd2df100000000aa8a93d7
+r pmovzxdq dea946e0b179bef5361cb20c2785c541 2ffdc2c55b0f87032db762c30b75b069 00000000361cb20c000000002785c541
+m pmovzxdq dea946e0b179bef5361cb20c2785c541 2ffdc2c55b0f87032db762c30b75b069 00000000361cb20c000000002785c541
+r pmovzxdq d50420276581181f0f0b8f5d0353bc2f 0bb64f05552e696e2762baa7a1d0708a 000000000f0b8f5d000000000353bc2f
+m pmovzxdq d50420276581181f0f0b8f5d0353bc2f 0bb64f05552e696e2762baa7a1d0708a 000000000f0b8f5d000000000353bc2f
+r popcntw 0000000000000000 ce34ff5acf4166a2 ce34ff5acf410000 0000000000000040
+m popcntw 0000000000000000 1a89a54f083de477 1a89a54f083d0000 0000000000000040
+r popcntw 0c08ffc7e4ddbb33 b422ffe63a89d2cf b422ffe63a89000a 0000000000000000
+m popcntw c559ec8d149f00fc e871c8b6082ece6f e871c8b6082e0006 0000000000000000
+r popcntw 09fb20f2e128bbc3 61b28c5adc2722b3 61b28c5adc27000a 0000000000000000
+m popcntw 03ada90f35f4b762 cc21d86e24721bf7 cc21d86e24720009 0000000000000000
+r popcntw e0299202fe7dc2b7 d4f9378f4a0b0597 d4f9378f4a0b0009 0000000000000000
+m popcntw cc2ce7e72741a69c 26773558bcec2cef 26773558bcec0008 0000000000000000
+r popcntw f272b5d99cba30ee 6ed75f66e513db5b 6ed75f66e5130008 0000000000000000
+m popcntw 7eb707f549662d89 57554055317b6037 57554055317b0007 0000000000000000
+r popcntw 9eb6ea561ac16649 8e2c65bf0c2005de 8e2c65bf0c200007 0000000000000000
+m popcntw 7b2c6918fb45aa0b be995943e2ff17ae be995943e2ff0007 0000000000000000
+r popcntw 44d49058d970c4a9 94d8a87a1f12e202 94d8a87a1f120007 0000000000000000
+m popcntw 236c6c329ebd7f00 bc24de033057b236 bc24de0330570007 0000000000000000
+r popcntw 44ae08c138a8a9ec e1ba88777fc9d2a5 e1ba88777fc90009 0000000000000000
+m popcntw d556702191ad0c49 afd632747a6490ad afd632747a640005 0000000000000000
+r popcntw ff22b06f974975f3 d4b466968b2536a9 d4b466968b25000b 0000000000000000
+m popcntw f1ccd5c635f6b0c6 fa8fb278200711f4 fa8fb27820070007 0000000000000000
+r popcntw d511eb435732889e cda4a1b6a4056dec cda4a1b6a4050007 0000000000000000
+m popcntw d7adfc01e979cb57 fa2fc0ed831e96eb fa2fc0ed831e000a 0000000000000000
+r popcntl 0000000000000000 245b161dd74543cd 0000000000000000 0000000000000040
+m popcntl 0000000000000000 a243bdeb3ccc0e27 0000000000000000 0000000000000040
+r popcntl 98c3bba7a1276f65 c0fa163a9712430d 0000000000000011 0000000000000000
+m popcntl e0175e473ea1aa76 d1b9c96387230ffd 0000000000000011 0000000000000000
+r popcntl cdcff4e63114a606 82bc610379fbbf52 000000000000000b 0000000000000000
+m popcntl 8ba888a166fb2df0 7e3f6bb5d7969d6a 0000000000000013 0000000000000000
+r popcntl 445e2793c9d20c12 727d71150ff1f5a0 000000000000000c 0000000000000000
+m popcntl 27addbd946150f47 09b302c08b071550 000000000000000e 0000000000000000
+r popcntl 5e50b28ec941016a f11da752b9d448d6 000000000000000b 0000000000000000
+m popcntl 1604b8cf3fd1b059 d3f7ee660454d98d 0000000000000011 0000000000000000
+r popcntl 7a85f7b79241e6ef 5e7c6298d88315d3 0000000000000011 0000000000000000
+m popcntl b78e7e63b00d7007 3ce99085a05e4803 000000000000000c 0000000000000000
+r popcntl f9dc56ee83b11b7f 197a03c8cbe0be78 0000000000000012 0000000000000000
+m popcntl 6b2b8d75f9aab031 a26a47fec205c390 0000000000000010 0000000000000000
+r popcntl 39372e13fd73fefb 83f6e8c2f2c9a3a6 000000000000001a 0000000000000000
+m popcntl 91bb45e47b88d0b7 675a73b1c729a915 0000000000000011 0000000000000000
+r popcntl 9c74df055f65f142 fbd27466ae20223b 0000000000000011 0000000000000000
+m popcntl 891e079295872f79 eb99757e11aa5a72 0000000000000012 0000000000000000
+r popcntl 8274caa609695436 e2ec04945ec39d18 000000000000000d 0000000000000000
+m popcntl b433335da7872d56 8c07ac4500673787 0000000000000011 0000000000000000
+r popcntq 0000000000000000 4a174ed45c5d85b6 0000000000000000 0000000000000040
+m popcntq 0000000000000000 69dd7fd9222e8b86 0000000000000000 0000000000000040
+r popcntq 2c21c36e1cfbfdf0 45d10b96917d6a21 0000000000000023 0000000000000000
+m popcntq 5e37713e30dcb20f ef9f5a500f89eb08 0000000000000022 0000000000000000
+r popcntq cf443bf0d567f0af 1283f9a2084f5896 0000000000000025 0000000000000000
+m popcntq ab042d9ff51985ac 5bb97329e8c9fe29 0000000000000020 0000000000000000
+r popcntq 1d3253677d6d3be2 767c55801cf5281c 0000000000000024 0000000000000000
+m popcntq 518bba655adfe02d 0e092a440ece24cb 0000000000000022 0000000000000000
+r popcntq 74cb6eb576ec3e6a d09c7e102c503d91 0000000000000026 0000000000000000
+m popcntq b2ad7971bf0e2273 6771dd80e078becc 0000000000000023 0000000000000000
+r popcntq 36efe9b820c35824 80c3d4319841f4d6 000000000000001e 0000000000000000
+m popcntq 2d4bc9a48586ab5b c7cfefbfbfa72b0d 000000000000001f 0000000000000000
+r popcntq c37d2651dad3e9f3 e7d1b8c5c1a6afcb 0000000000000025 0000000000000000
+m popcntq 23430bdc0b26dcc8 8c04bddf093acc6e 000000000000001c 0000000000000000
+r popcntq 7a57846004fc51b6 64a589aa0660cd50 000000000000001d 0000000000000000
+m popcntq f3769ef9b1d01499 18f0a9c22112ffcf 0000000000000023 0000000000000000
+r popcntq bb5b64c5ff1ef14d 5721a8c2c74eaf45 0000000000000027 0000000000000000
+m popcntq fec3e2ddd862b4ad cb73124664102710 0000000000000025 0000000000000000
+r popcntq e76a255f2a192997 212374eb6552b48a 0000000000000021 0000000000000000
+m popcntq a30c3867dfbe1be6 046d594c3412a110 0000000000000024 0000000000000000
+r pmulld ff3c4b3f064d8c217557cde51027645d 5df6d73059dd837e3e8527449ee9f43b b00a04d03a5cdb3ef9a993d40361c56f
+m pmulld ff3c4b3f064d8c217557cde51027645d 5df6d73059dd837e3e8527449ee9f43b b00a04d03a5cdb3ef9a993d40361c56f
+r pmulld b1cff9f1b4ddbe2322a9c22776ff3042 14227fde7c0f14944c6efdbc0d7a7fc6 655b4dfefb19a83c3a4d1fa4fbc4110c
+m pmulld b1cff9f1b4ddbe2322a9c22776ff3042 14227fde7c0f14944c6efdbc0d7a7fc6 655b4dfefb19a83c3a4d1fa4fbc4110c
+r pmulld 83a818b6f3943cb7c8dd1991b6cb297d d97955953deed0d281603593a4c5577d 6510cfee4e107e1ec4a0b3434d7dbd09
+m pmulld 83a818b6f3943cb7c8dd1991b6cb297d d97955953deed0d281603593a4c5577d 6510cfee4e107e1ec4a0b3434d7dbd09
+r pmulld d111a5f95efe458942bf4f0fec980e3b 084857c13907f4e2b82548b37fd6378d 13bdbfb99e7ef6f2af2b7f7d2520837f
+m pmulld d111a5f95efe458942bf4f0fec980e3b 084857c13907f4e2b82548b37fd6378d 13bdbfb99e7ef6f2af2b7f7d2520837f
+r pmulld f7579b2891a813446e1bdf8d327099a8 fcd880ce0be4bb73cf8ab30ab9b9dc22 1fd2da304923538c4f685282e968c850
+m pmulld f7579b2891a813446e1bdf8d327099a8 fcd880ce0be4bb73cf8ab30ab9b9dc22 1fd2da304923538c4f685282e968c850
+r pmulld 51c6f6af2a1de39526bc45f7a76187ef 1378cc285014632fa05bf3836f7b0267 f2b1ff58a223675bc78e42650c228f29
+m pmulld 51c6f6af2a1de39526bc45f7a76187ef 1378cc285014632fa05bf3836f7b0267 f2b1ff58a223675bc78e42650c228f29
+r pmulld 3ca9b2f8c2eaf1274870fd3a6577943d a773373ba32026c309648309bc276589 9df7872852a17ab55235950adbc565a5
+m pmulld 3ca9b2f8c2eaf1274870fd3a6577943d a773373ba32026c309648309bc276589 9df7872852a17ab55235950adbc565a5
+r pmulld 124ecb70f79979a7ae01844088bd7bbe 1614be74a19641dae470df8abcc9c0b3 4b714ec01f6eff36fb050a80697a05da
+m pmulld 124ecb70f79979a7ae01844088bd7bbe 1614be74a19641dae470df8abcc9c0b3 4b714ec01f6eff36fb050a80697a05da
+r pmulld 30ff3e8365b8b6c1363c54f62d3ffa9d baa85b3de501ef210e4d83f18c6ed012 9c027637eb2ebde1f043dd96b5952f0a
+m pmulld 30ff3e8365b8b6c1363c54f62d3ffa9d baa85b3de501ef210e4d83f18c6ed012 9c027637eb2ebde1f043dd96b5952f0a
+r pmulld f209069ea7d3e520baedeb496f09ca07 f17c0c040cee6e4364c5ec2b482151d1 26fb82787ca8b7604e0ad143c2d126b7
+m pmulld f209069ea7d3e520baedeb496f09ca07 f17c0c040cee6e4364c5ec2b482151d1 26fb82787ca8b7604e0ad143c2d126b7
+r ptest 00000000000000000000000000000000 00000000000000000000000000000000 -> eflags 0041
+r ptest 00000000000000000000000000000000 00000000000000000000000000000001 -> eflags 0040
+r ptest 00000000000000000000000000000000 00000000000000010000000000000000 -> eflags 0040
+r ptest 00000000000000000000000000000000 00000000000000010000000000000001 -> eflags 0040
+r ptest 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff -> eflags 0040
+r ptest 00000000000000000000000000000000 fffffffffffffffffffffffffffffffe -> eflags 0040
+r ptest 00000000000000000000000000000000 fffffffffffffffeffffffffffffffff -> eflags 0040
+r ptest 00000000000000000000000000000000 fffffffffffffffefffffffffffffffe -> eflags 0040
+r ptest 00000000000000000000000000000001 00000000000000000000000000000000 -> eflags 0041
+r ptest 00000000000000000000000000000001 00000000000000000000000000000001 -> eflags 0001
+r ptest 00000000000000000000000000000001 00000000000000010000000000000000 -> eflags 0040
+r ptest 00000000000000000000000000000001 00000000000000010000000000000001 -> eflags 0000
+r ptest 00000000000000000000000000000001 ffffffffffffffffffffffffffffffff -> eflags 0000
+r ptest 00000000000000000000000000000001 fffffffffffffffffffffffffffffffe -> eflags 0040
+r ptest 00000000000000000000000000000001 fffffffffffffffeffffffffffffffff -> eflags 0000
+r ptest 00000000000000000000000000000001 fffffffffffffffefffffffffffffffe -> eflags 0040
+r ptest 00000000000000010000000000000000 00000000000000000000000000000000 -> eflags 0041
+r ptest 00000000000000010000000000000000 00000000000000000000000000000001 -> eflags 0040
+r ptest 00000000000000010000000000000000 00000000000000010000000000000000 -> eflags 0001
+r ptest 00000000000000010000000000000000 00000000000000010000000000000001 -> eflags 0000
+r ptest 00000000000000010000000000000000 ffffffffffffffffffffffffffffffff -> eflags 0000
+r ptest 00000000000000010000000000000000 fffffffffffffffffffffffffffffffe -> eflags 0000
+r ptest 00000000000000010000000000000000 fffffffffffffffeffffffffffffffff -> eflags 0040
+r ptest 00000000000000010000000000000000 fffffffffffffffefffffffffffffffe -> eflags 0040
+r ptest 00000000000000010000000000000001 00000000000000000000000000000000 -> eflags 0041
+r ptest 00000000000000010000000000000001 00000000000000000000000000000001 -> eflags 0001
+r ptest 00000000000000010000000000000001 00000000000000010000000000000000 -> eflags 0001
+r ptest 00000000000000010000000000000001 00000000000000010000000000000001 -> eflags 0001
+r ptest 00000000000000010000000000000001 ffffffffffffffffffffffffffffffff -> eflags 0000
+r ptest 00000000000000010000000000000001 fffffffffffffffffffffffffffffffe -> eflags 0000
+r ptest 00000000000000010000000000000001 fffffffffffffffeffffffffffffffff -> eflags 0000
+r ptest 00000000000000010000000000000001 fffffffffffffffefffffffffffffffe -> eflags 0040
+r ptest ffffffffffffffffffffffffffffffff 00000000000000000000000000000000 -> eflags 0041
+r ptest ffffffffffffffffffffffffffffffff 00000000000000000000000000000001 -> eflags 0001
+r ptest ffffffffffffffffffffffffffffffff 00000000000000010000000000000000 -> eflags 0001
+r ptest ffffffffffffffffffffffffffffffff 00000000000000010000000000000001 -> eflags 0001
+r ptest ffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffff -> eflags 0001
+r ptest ffffffffffffffffffffffffffffffff fffffffffffffffffffffffffffffffe -> eflags 0001
+r ptest ffffffffffffffffffffffffffffffff fffffffffffffffeffffffffffffffff -> eflags 0001
+r ptest ffffffffffffffffffffffffffffffff fffffffffffffffefffffffffffffffe -> eflags 0001
+r ptest fffffffffffffffffffffffffffffffe 00000000000000000000000000000000 -> eflags 0041
+r ptest fffffffffffffffffffffffffffffffe 00000000000000000000000000000001 -> eflags 0040
+r ptest fffffffffffffffffffffffffffffffe 00000000000000010000000000000000 -> eflags 0001
+r ptest fffffffffffffffffffffffffffffffe 00000000000000010000000000000001 -> eflags 0000
+r ptest fffffffffffffffffffffffffffffffe ffffffffffffffffffffffffffffffff -> eflags 0000
+r ptest fffffffffffffffffffffffffffffffe fffffffffffffffffffffffffffffffe -> eflags 0001
+r ptest fffffffffffffffffffffffffffffffe fffffffffffffffeffffffffffffffff -> eflags 0000
+r ptest fffffffffffffffffffffffffffffffe fffffffffffffffefffffffffffffffe -> eflags 0001
+r ptest fffffffffffffffeffffffffffffffff 00000000000000000000000000000000 -> eflags 0041
+r ptest fffffffffffffffeffffffffffffffff 00000000000000000000000000000001 -> eflags 0001
+r ptest fffffffffffffffeffffffffffffffff 00000000000000010000000000000000 -> eflags 0040
+r ptest fffffffffffffffeffffffffffffffff 00000000000000010000000000000001 -> eflags 0000
+r ptest fffffffffffffffeffffffffffffffff ffffffffffffffffffffffffffffffff -> eflags 0000
+r ptest fffffffffffffffeffffffffffffffff fffffffffffffffffffffffffffffffe -> eflags 0000
+r ptest fffffffffffffffeffffffffffffffff fffffffffffffffeffffffffffffffff -> eflags 0001
+r ptest fffffffffffffffeffffffffffffffff fffffffffffffffefffffffffffffffe -> eflags 0001
+r ptest fffffffffffffffefffffffffffffffe 00000000000000000000000000000000 -> eflags 0041
+r ptest fffffffffffffffefffffffffffffffe 00000000000000000000000000000001 -> eflags 0040
+r ptest fffffffffffffffefffffffffffffffe 00000000000000010000000000000000 -> eflags 0040
+r ptest fffffffffffffffefffffffffffffffe 00000000000000010000000000000001 -> eflags 0040
+r ptest fffffffffffffffefffffffffffffffe ffffffffffffffffffffffffffffffff -> eflags 0000
+r ptest fffffffffffffffefffffffffffffffe fffffffffffffffffffffffffffffffe -> eflags 0000
+r ptest fffffffffffffffefffffffffffffffe fffffffffffffffeffffffffffffffff -> eflags 0000
+r ptest fffffffffffffffefffffffffffffffe fffffffffffffffefffffffffffffffe -> eflags 0001
+r roundsd_000 b4b81f2b597541710000000000000000 15dacc33b1e8f8ee0000000000000000 0.000000 0.000000
+m roundsd_000 d2588598182a085f0000000000000000 840e9838717bc9cb0000000000000000 0.000000 0.000000
+r roundsd_001 a73535507f7e74970000000000000000 98666b7ee7341f880000000000000000 0.000000 0.000000
+m roundsd_001 919b29bf2bfec2c50000000000000000 ae2d4071b09e34d10000000000000000 0.000000 0.000000
+r roundsd_010 ebd55f51b7352d940000000000000000 23ae157d674545520000000000000000 0.000000 0.000000
+m roundsd_010 1130d272c0b0f3b10000000000000000 5136e60ea8b68eb60000000000000000 0.000000 0.000000
+r roundsd_011 5ff87f8ee1fa4dc70000000000000000 9511ad90107c4aa90000000000000000 0.000000 0.000000
+m roundsd_011 30796011b79f7a830000000000000000 4c8b686f3a23b6d90000000000000000 0.000000 0.000000
+r roundsd_000 e2ff7367dd2bb5908000000000000000 d0f01218c3380ef08000000000000000 -0.000000 -0.000000
+m roundsd_000 d0d6b3fdf02b399c8000000000000000 7e8ba7f547468d9a8000000000000000 -0.000000 -0.000000
+r roundsd_001 56491d3d8b2a43508000000000000000 b2aa237461d970848000000000000000 -0.000000 -0.000000
+m roundsd_001 cfa6ab954bb50e5b8000000000000000 c89783ffad7ef35a8000000000000000 -0.000000 -0.000000
+r roundsd_010 99375b70cb57d7668000000000000000 1c9fc204c8c052c78000000000000000 -0.000000 -0.000000
+m roundsd_010 0e492839a79cda208000000000000000 0a0edcee4d2cc8788000000000000000 -0.000000 -0.000000
+r roundsd_011 8c280e5e7c1153338000000000000000 ee30cd29d94c92188000000000000000 -0.000000 -0.000000
+m roundsd_011 6d1f094ae6417d4c8000000000000000 2450922107afec548000000000000000 -0.000000 -0.000000
+r roundsd_000 0f7c166980b896167ff0000000000000 08bc254274de12d87ff0000000000000 inf inf
+m roundsd_000 cc893028e602d73e7ff0000000000000 f6be84f8bb673f4f7ff0000000000000 inf inf
+r roundsd_001 029353f1b5ac7f6f7ff0000000000000 4aa3aaaf78d5b0657ff0000000000000 inf inf
+m roundsd_001 0be77b318842c8567ff0000000000000 60b794d448b4a0c87ff0000000000000 inf inf
+r roundsd_010 44cea455fc4eef9f7ff0000000000000 94463cd1c7914d227ff0000000000000 inf inf
+m roundsd_010 0a97cbc7ac5e30f57ff0000000000000 419ca01490f7f11f7ff0000000000000 inf inf
+r roundsd_011 b78debf535fec7057ff0000000000000 c504bb084073c96c7ff0000000000000 inf inf
+m roundsd_011 a8fb004a32b8ef7b7ff0000000000000 7bcc8918719010b57ff0000000000000 inf inf
+r roundsd_000 392f0631401ae502fff0000000000000 bf3e07b2c2da04a6fff0000000000000 -inf -inf
+m roundsd_000 c773fa18fab0e446fff0000000000000 eca72f41cddddee9fff0000000000000 -inf -inf
+r roundsd_001 ac14d76afd052af4fff0000000000000 6053ff312e26dd2dfff0000000000000 -inf -inf
+m roundsd_001 455d9993e4a5f1b8fff0000000000000 768d72ee82413c1cfff0000000000000 -inf -inf
+r roundsd_010 ee9c3c004c1c753efff0000000000000 89a385e564b83663fff0000000000000 -inf -inf
+m roundsd_010 031cbc1bd0f7f431fff0000000000000 f7df3280711908adfff0000000000000 -inf -inf
+r roundsd_011 e02816510cc1a83dfff0000000000000 1a8f772c44efeda7fff0000000000000 -inf -inf
+m roundsd_011 e10d450f9d06ce0ffff0000000000000 50fd4f567ac722fcfff0000000000000 -inf -inf
+r roundsd_000 621745bf1e53a253fff8000000000000 f376b669ae2ce35afff8000000000000 nan nan
+m roundsd_000 bf9212cf2c335fb5fff8000000000000 6146a9d07daa6c6afff8000000000000 nan nan
+r roundsd_001 54caa9aa633342e0fff8000000000000 f4b822f982cef9dafff8000000000000 nan nan
+m roundsd_001 7d0a04bc5edd8780fff8000000000000 091a1f4f5923c556fff8000000000000 nan nan
+r roundsd_010 95a02171b9c06a42fff8000000000000 fdb69b3e9f350d8afff8000000000000 nan nan
+m roundsd_010 fad6fc35116526d2fff8000000000000 2ad99232f0910c21fff8000000000000 nan nan
+r roundsd_011 07f98f74015af8dbfff8000000000000 edcf0197e7c200c7fff8000000000000 nan nan
+m roundsd_011 1855d89a262a1b0afff8000000000000 a2e4e3d92054232afff8000000000000 nan nan
+r roundsd_000 8836d1131b62cd0b7ff8000000000000 a664346538d4b1f37ff8000000000000 nan nan
+m roundsd_000 b5e8784c7c8c48897ff8000000000000 539af0a5cbcde8d17ff8000000000000 nan nan
+r roundsd_001 fab6c9afe737c9317ff8000000000000 06d4130774cb026e7ff8000000000000 nan nan
+m roundsd_001 b2edbeaaf5ec8bae7ff8000000000000 1b5c9af6cf5b3c777ff8000000000000 nan nan
+r roundsd_010 3bda55a84439ccad7ff8000000000000 ee7f7fdd7908d2977ff8000000000000 nan nan
+m roundsd_010 f0c7891470a9c6d97ff8000000000000 db89c02a0d5fff7b7ff8000000000000 nan nan
+r roundsd_011 2c00565c14c9b5e07ff8000000000000 3ec6594828ea00ce7ff8000000000000 nan nan
+m roundsd_011 4dd3b8ebcc24d76b7ff8000000000000 738244a36537113d7ff8000000000000 nan nan
+r roundsd_000 ad8bac2d35466629bff4cccccccccccd d6087fa761d26d73bff0000000000000 -1.300000 -1.000000
+m roundsd_000 a9732d8eebbc9fc3bff4cccccccccccd c3a505c0b746521ebff0000000000000 -1.300000 -1.000000
+r roundsd_001 9ed8377b8811bde8bff4cccccccccccd 96a5d25b031ff9e7c000000000000000 -1.300000 -2.000000
+m roundsd_001 e606c65eabd1fe42bff4cccccccccccd ab54e2e2e2e9a17dc000000000000000 -1.300000 -2.000000
+r roundsd_010 df49d6a4ee899c7ebff4cccccccccccd 5efe32c3f031858abff0000000000000 -1.300000 -1.000000
+m roundsd_010 e3ed64baedc4d347bff4cccccccccccd 0aefbd68c882e0babff0000000000000 -1.300000 -1.000000
+r roundsd_011 4f3e6b0b450ee14abff4cccccccccccd 0d727f3f0669eebabff0000000000000 -1.300000 -1.000000
+m roundsd_011 7f87e70291f40032bff4cccccccccccd c2d574b34771ed36bff0000000000000 -1.300000 -1.000000
+r roundsd_000 d015d40d6e016dacbff199999999999a 84629830272617d9bff0000000000000 -1.100000 -1.000000
+m roundsd_000 9c342f9777c16464bff199999999999a b166e8214114a950bff0000000000000 -1.100000 -1.000000
+r roundsd_001 4030f30c48c12005bff199999999999a a42d5ff531c8df47c000000000000000 -1.100000 -2.000000
+m roundsd_001 18551cd87e8cde3cbff199999999999a b803f91594cef469c000000000000000 -1.100000 -2.000000
+r roundsd_010 80efa667b5aedab4bff199999999999a 4b33b2ee05b02563bff0000000000000 -1.100000 -1.000000
+m roundsd_010 d4498d2688b44f1abff199999999999a b70b87ec21fcaee0bff0000000000000 -1.100000 -1.000000
+r roundsd_011 70b1ce7f93297a1abff199999999999a 5ad5737c833dcb8dbff0000000000000 -1.100000 -1.000000
+m roundsd_011 b07164e0739a975fbff199999999999a 8ede7208c800b715bff0000000000000 -1.100000 -1.000000
+r roundsd_000 f0d64bb3c491e296bfeccccccccccccd b17280fe8bd0af25bff0000000000000 -0.900000 -1.000000
+m roundsd_000 8c2c7f66219d966abfeccccccccccccd 1ddd99c96939ef69bff0000000000000 -0.900000 -1.000000
+r roundsd_001 e0bffd642647f088bfeccccccccccccd 306bbad4fdc8b28cbff0000000000000 -0.900000 -1.000000
+m roundsd_001 48dac018701d2c9cbfeccccccccccccd 4467de8de308363bbff0000000000000 -0.900000 -1.000000
+r roundsd_010 20cbc3f09aaa8651bfeccccccccccccd b61e015fb885b4228000000000000000 -0.900000 -0.000000
+m roundsd_010 c4dc0557417a3954bfeccccccccccccd e3dd1fb618cc6bec8000000000000000 -0.900000 -0.000000
+r roundsd_011 8f5a7fba001a8250bfeccccccccccccd 25ee34ff9e6895458000000000000000 -0.900000 -0.000000
+m roundsd_011 df912f8374159df2bfeccccccccccccd d99d3da4e6e56fdb8000000000000000 -0.900000 -0.000000
+r roundsd_000 0fcd0f1f38f8c5e5bfe6666666666666 5b3835128dd03557bff0000000000000 -0.700000 -1.000000
+m roundsd_000 7a591efbe94e37d6bfe6666666666666 080a18b62fb42368bff0000000000000 -0.700000 -1.000000
+r roundsd_001 7e83558122a32f71bfe6666666666666 3a5ee3fa671d74b8bff0000000000000 -0.700000 -1.000000
+m roundsd_001 7695b11f8084e961bfe6666666666666 4e81904cd19865f4bff0000000000000 -0.700000 -1.000000
+r roundsd_010 bddc2f3f9e7ca053bfe6666666666666 a0bf1d170ab031c78000000000000000 -0.700000 -0.000000
+m roundsd_010 b1a4ca4f181791f3bfe6666666666666 8c6485c6adf116de8000000000000000 -0.700000 -0.000000
+r roundsd_011 ac397eba8be1f8ecbfe6666666666666 6ebcc4c757e84ee48000000000000000 -0.700000 -0.000000
+m roundsd_011 0ce747ec936710ebbfe6666666666666 a213d785a32016868000000000000000 -0.700000 -0.000000
+r roundsd_000 2bf92251cb35169bbfe00014f8b588e3 84b4b96d2e26a96fbff0000000000000 -0.500010 -1.000000
+m roundsd_000 67bd0a55cfd546a9bfe00014f8b588e3 70ed65e99385444dbff0000000000000 -0.500010 -1.000000
+r roundsd_001 1a7dfb643cd5dcc0bfe00014f8b588e3 c208da666ec923c9bff0000000000000 -0.500010 -1.000000
+m roundsd_001 a286f1ebadc1138dbfe00014f8b588e3 d55211505c7e8292bff0000000000000 -0.500010 -1.000000
+r roundsd_010 5924e954bf2328bcbfe00014f8b588e3 07170714f9319c528000000000000000 -0.500010 -0.000000
+m roundsd_010 9ca3dd0d0d8957f8bfe00014f8b588e3 b3a2b91de06daeb58000000000000000 -0.500010 -0.000000
+r roundsd_011 c74ecb80347fdbeebfe00014f8b588e3 354122d6adbff4688000000000000000 -0.500010 -0.000000
+m roundsd_011 3773ae1bcf8ff14abfe00014f8b588e3 e93e3eadfdb2aa178000000000000000 -0.500010 -0.000000
+r roundsd_000 465c83497b47d5b7bfdfffd60e94ee39 2ae60a0d6cd20b6d8000000000000000 -0.499990 -0.000000
+m roundsd_000 51564476d333c3e1bfdfffd60e94ee39 5685816295ab54178000000000000000 -0.499990 -0.000000
+r roundsd_001 b4adef0e74ddf675bfdfffd60e94ee39 c8679e1814cac1c1bff0000000000000 -0.499990 -1.000000
+m roundsd_001 cbad7f7df9d3ab1fbfdfffd60e94ee39 dbd8609b86ba8d16bff0000000000000 -0.499990 -1.000000
+r roundsd_010 f2a2f02ffea11e8bbfdfffd60e94ee39 ed24c0578608f5c38000000000000000 -0.499990 -0.000000
+m roundsd_010 86d73e9120d28a64bfdfffd60e94ee39 5896bbb9b13f35738000000000000000 -0.499990 -0.000000
+r roundsd_011 e19a660dfbf22d56bfdfffd60e94ee39 7a7b4e2ba2eb89d38000000000000000 -0.499990 -0.000000
+m roundsd_011 603563102a8d410ebfdfffd60e94ee39 ad1f741bf6992c8e8000000000000000 -0.499990 -0.000000
+r roundsd_000 5ff5310749300238bfd3333333333333 4fce29f348d45b518000000000000000 -0.300000 -0.000000
+m roundsd_000 3926cc5df566ae80bfd3333333333333 bad46a21352852c88000000000000000 -0.300000 -0.000000
+r roundsd_001 4c13317dcabb7f91bfd3333333333333 4c7d311058224c9ebff0000000000000 -0.300000 -1.000000
+m roundsd_001 f30a5bd562bcb117bfd3333333333333 5f147c2c4d4d8680bff0000000000000 -0.300000 -1.000000
+r roundsd_010 8a5546d05cf482bfbfd3333333333333 50e746e1b1353c1a8000000000000000 -0.300000 -0.000000
+m roundsd_010 6d42eeda52f02c35bfd3333333333333 7b408c9b2067aa178000000000000000 -0.300000 -0.000000
+r roundsd_011 f81b4f5fe03bec24bfd3333333333333 3d6c48c6356e0b238000000000000000 -0.300000 -0.000000
+m roundsd_011 862d66cca261fe39bfd3333333333333 f0b778ce8cd69cec8000000000000000 -0.300000 -0.000000
+r roundsd_000 75c32e8b36ee9d20bfb999999999999a f16c1720c22c991b8000000000000000 -0.100000 -0.000000
+m roundsd_000 202ba309356f0684bfb999999999999a 9cd9212673fb3d5f8000000000000000 -0.100000 -0.000000
+r roundsd_001 e2b0c1b33d707512bfb999999999999a 4d48924e39cfc662bff0000000000000 -0.100000 -1.000000
+m roundsd_001 199d84f3ea7b2675bfb999999999999a 61076702b3356dd0bff0000000000000 -0.100000 -1.000000
+r roundsd_010 203fe937d71e545abfb999999999999a 32609bb07bb871578000000000000000 -0.100000 -0.000000
+m roundsd_010 52e2ebeaa1e43c6cbfb999999999999a 1da02ac32de40ca08000000000000000 -0.100000 -0.000000
+r roundsd_011 0dd28678e35a1a58bfb999999999999a 7e1210a766467c5a8000000000000000 -0.100000 -0.000000
+m roundsd_011 ab5bb74d390b29cabfb999999999999a b10449c8c169fa2f8000000000000000 -0.100000 -0.000000
+r roundsd_000 8ac878d54083a66d3fb999999999999a 12c1d292dadac5cb0000000000000000 0.100000 0.000000
+m roundsd_000 0467c77c934fcdee3fb999999999999a fd94a6714f2317dc0000000000000000 0.100000 0.000000
+r roundsd_001 76829faecffadaf93fb999999999999a cdcac1d1b9d32d0b0000000000000000 0.100000 0.000000
+m roundsd_001 3d66fcd8901008393fb999999999999a e0af201fb67343070000000000000000 0.100000 0.000000
+r roundsd_010 b35fdb64701e945a3fb999999999999a 918fbdc5e291947a3ff0000000000000 0.100000 1.000000
+m roundsd_010 36b936c00eafba0a3fb999999999999a 3cb59631d8b85d103ff0000000000000 0.100000 1.000000
+r roundsd_011 20bf0b56034fb5f33fb999999999999a 3d6fa6ce3475da760000000000000000 0.100000 0.000000
+m roundsd_011 cebf5594ee8bc3c13fb999999999999a ef07e907935246580000000000000000 0.100000 0.000000
+r roundsd_000 9c0311e568ee1d213fd3333333333333 b0cb5c4a91dedf610000000000000000 0.300000 0.000000
+m roundsd_000 e6d839b5100402bf3fd3333333333333 db05f902c9a2df3e0000000000000000 0.300000 0.000000
+r roundsd_001 098acb707f5aac463fd3333333333333 cb02be9bd72c829b0000000000000000 0.300000 0.000000
+m roundsd_001 5f65c282537b58633fd3333333333333 de0da681580706230000000000000000 0.300000 0.000000
+r roundsd_010 45b41a5728f342c13fd3333333333333 6f74ad21e7c0a5833ff0000000000000 0.300000 1.000000
+m roundsd_010 17c5d05b994fa60d3fd3333333333333 d981d0e521e29c663ff0000000000000 0.300000 1.000000
+r roundsd_011 31e2defb421abff33fd3333333333333 7a820a3aa1f926790000000000000000 0.300000 0.000000
+m roundsd_011 ef5942a1c0e0ca1e3fd3333333333333 acc1578d049281670000000000000000 0.300000 0.000000
+r roundsd_000 ad74f7bbaf2e023b3fdfffd60e94ee39 cd8bb349e538e7dd0000000000000000 0.499990 0.000000
+m roundsd_000 c77ffab3aa8fa5f53fdfffd60e94ee39 372b1ad9e17794870000000000000000 0.499990 0.000000
+r roundsd_001 99c845f74d90edf93fdfffd60e94ee39 47ef89ab93dcc6100000000000000000 0.499990 0.000000
+m roundsd_001 7f9ad6f235bc17f33fdfffd60e94ee39 5a22fb2a97f2b7250000000000000000 0.499990 0.000000
+r roundsd_010 d440a810fd9f5e8e3fdfffd60e94ee39 ca0f6cc28a45a4723ff0000000000000 0.499990 1.000000
+m roundsd_010 f607b7bd42c5ff763fdfffd60e94ee39 f403d8df0862c9a23ff0000000000000 0.499990 1.000000
+r roundsd_011 403cff659fbb36593fdfffd60e94ee39 354a3cedacd461610000000000000000 0.499990 0.000000
+m roundsd_011 0e287d74b10c3fe13fdfffd60e94ee39 e73092581227a95d0000000000000000 0.499990 0.000000
+r roundsd_000 bb1a2c57134556ba3fe00014f8b588e3 6701d88dd7e8dd3f3ff0000000000000 0.500010 1.000000
+m roundsd_000 a55d087862f1b6913fe00014f8b588e3 11080af697a238b63ff0000000000000 0.500010 1.000000
+r roundsd_001 273c0d45399c9b123fe00014f8b588e3 41932201ece1f76c0000000000000000 0.500010 0.000000
+m roundsd_001 9c05382834d243e83fe00014f8b588e3 53ec1d197532560d0000000000000000 0.500010 0.000000
+r roundsd_010 6202838ff120e8c03fe00014f8b588e3 a360f8a9cb2091473ff0000000000000 0.500010 1.000000
+m roundsd_010 d380ece50912c7463fe00014f8b588e3 8e3bae1f8d37e3c33ff0000000000000 0.500010 1.000000
+r roundsd_011 4dcb6e961a321c253fe00014f8b588e3 6ec93ce6540489300000000000000000 0.500010 0.000000
+m roundsd_011 2b2e060ec00e220a3fe00014f8b588e3 9f559c6abf12bf380000000000000000 0.500010 0.000000
+r roundsd_000 c8f7aeb9953117a03fe6666666666666 7f2dcc1767eec1873ff0000000000000 0.700000 1.000000
+m roundsd_000 81706403382834943fe6666666666666 699bc759eb22cacb3ff0000000000000 0.700000 1.000000
+r roundsd_001 b3e72358437eb8913fe6666666666666 b9ec899de43c17ad0000000000000000 0.700000 0.000000
+m roundsd_001 b8a6e72552bfdd443fe6666666666666 cb6c0e4df0c8e3dc0000000000000000 0.700000 0.000000
+r roundsd_010 eefaadd40278e0593fe6666666666666 fb6753d7ab516c023ff0000000000000 0.700000 1.000000
+m roundsd_010 af2e6fd3ee34fd7b3fe6666666666666 a52952a5b063eccb3ff0000000000000 0.700000 1.000000
+r roundsd_011 58902b8cb37f70573fe6666666666666 24fd09259b8aa0e40000000000000000 0.700000 0.000000
+m roundsd_011 456adc6dece674983fe6666666666666 d63174c20953c3f90000000000000000 0.700000 0.000000
+r roundsd_000 d30a7fe136f446eb3feccccccccccccd 160f8de8964a92b53ff0000000000000 0.900000 1.000000
+m roundsd_000 5cba0e542c3521fc3feccccccccccccd 40e45202dcf949c53ff0000000000000 0.900000 1.000000
+r roundsd_001 3dc787326b3643763feccccccccccccd affcbe7f7aee24d50000000000000000 0.900000 0.000000
+m roundsd_001 d27de5e78e82e6063feccccccccccccd c1a3cdc80ab45f900000000000000000 0.900000 0.000000
+r roundsd_010 772724df31a646583feccccccccccccd d0247b4a28d835a33ff0000000000000 0.900000 1.000000
+m roundsd_010 88134186f12ca1173feccccccccccccd 3acdc57171e5e3b93ff0000000000000 0.900000 1.000000
+r roundsd_011 618b36496aa231ef3feccccccccccccd 59e8a5aa8067a47f0000000000000000 0.900000 0.000000
+m roundsd_011 5edc01923794338d3feccccccccccccd 8bc2195ff2ebb5a00000000000000000 0.900000 0.000000
+r roundsd_000 db529dcff48de39d3ff199999999999a 2aa71dfe62fc52c93ff0000000000000 1.100000 1.000000
+m roundsd_000 3439076a3e197cca3ff199999999999a 94e3abf26c26b7a63ff0000000000000 1.100000 1.000000
+r roundsd_001 c5dd39d1b0c43bc13ff199999999999a 23c1c1a6aef520e23ff0000000000000 1.100000 1.000000
+m roundsd_001 ea8a316fe71b5c2e3ff199999999999a 348f5988c1f6c82a3ff0000000000000 1.100000 1.000000
+r roundsd_010 ff8beab07fa91abc3ff199999999999a 2497720343b5ec2a4000000000000000 1.100000 2.000000
+m roundsd_010 5f2d600012fbb3183ff199999999999a 4d260583d0bcc78d4000000000000000 1.100000 2.000000
+r roundsd_011 68bc8fcb3f9c61ed3ff199999999999a 0c880f75039997ff3ff0000000000000 1.100000 1.000000
+m roundsd_011 7584747d9f1860e83ff199999999999a be098d4378d8962e3ff0000000000000 1.100000 1.000000
+r roundsd_000 e2d10a83d1fbeeb53ff4cccccccccccd bdf57a5acc0300c33ff0000000000000 1.300000 1.000000
+m roundsd_000 0aef4d476ed245ff3ff4cccccccccccd 6698d2279aa9136d3ff0000000000000 1.300000 1.000000
+r roundsd_001 4b2939371428a2733ff4cccccccccccd 153d92147f5309d63ff0000000000000 1.300000 1.000000
+m roundsd_001 00cccbbd5f8a40bc3ff4cccccccccccd 2631b48f178f1faa3ff0000000000000 1.300000 1.000000
+r roundsd_010 8425fd47ea835d873ff4cccccccccccd f5c03603fce891974000000000000000 1.300000 2.000000
+m roundsd_010 357ecd40529f337f3ff4cccccccccccd de3613dbcdea9a464000000000000000 1.300000 2.000000
+r roundsd_011 6d233614316bfe513ff4cccccccccccd 3ddf4785232277663ff0000000000000 1.300000 1.000000
+m roundsd_011 8a62352f2672fca93ff4cccccccccccd 6e07cf6c9d1b64a13ff0000000000000 1.300000 1.000000
+r roundss_000 e686c4fdcb40673235a9ceaf00000000 cdf9a5fdd4619ca3fbbaaadd00000000 0.000000 0.000000
+m roundss_000 dfdae1eabc617c99524fccee00000000 b602c7a266815d1ae592158f00000000 0.000000 0.000000
+r roundss_001 cfab87629662768a400d44cd00000000 856f30c8ef06e0afceaaf91700000000 0.000000 0.000000
+m roundss_001 1345b2d1f5cf93b0dbb2b33900000000 968adddb0a7d641192ced16100000000 0.000000 0.000000
+r roundss_010 08f45fa473320db7fe09931c00000000 459fc848547124ea0cca195900000000 0.000000 0.000000
+m roundss_010 08048945af19204d87dd626400000000 eefcef7a686e5be61a6a4deb00000000 0.000000 0.000000
+r roundss_011 70c12b2242100a1b51fb9bfc00000000 ecec4ddce20045b2977aea0300000000 0.000000 0.000000
+m roundss_011 9d7644a6cba105d03730bacf00000000 9dbadedc5fb420fa5ec66b8e00000000 0.000000 0.000000
+r roundss_000 e970cd3de35a4e1617453bcb80000000 5cb39fe57b1526694d194c7680000000 -0.000000 -0.000000
+m roundss_000 b1fcc35228c7219acc099bdb80000000 84238a63d0b094ac3e4009a980000000 -0.000000 -0.000000
+r roundss_001 516423533673b907314755ec80000000 73569dc2fd10a66f0f071e1180000000 -0.000000 -0.000000
+m roundss_001 25f4e8aca8ea530a24cae5e880000000 8498d36e9cc1975d9a3a089c80000000 -0.000000 -0.000000
+r roundss_010 89fa0ec71bb82b4e7f60c7bc80000000 123429d34950a423bda5423580000000 -0.000000 -0.000000
+m roundss_010 d9c192112a6a7c8020d3785480000000 7b78995ea148096c521348c880000000 -0.000000 -0.000000
+r roundss_011 71946ef6718b834ce1f0729d80000000 19ae21793f3502e53752964180000000 -0.000000 -0.000000
+m roundss_011 adc0a0e38da77c5d9f83338180000000 4a23bc92c0a3ca39462ca98c80000000 -0.000000 -0.000000
+r roundss_000 e99123421a4ba360375837ee7f800000 68236613bf1f9e155c6efc957f800000 inf inf
+m roundss_000 8153f481b3023300833af8cf7f800000 d1fa1c6ad835ba2556e40b497f800000 inf inf
+r roundss_001 d1520d0bf45969ea60f6f3107f800000 dff4d802a96f59140e5a52927f800000 inf inf
+m roundss_001 35d96c4c7ada81c9ab59a59d7f800000 ef5c9847cb5bb98f619c4d5e7f800000 inf inf
+r roundss_010 09360cb0e014b74b3e2d89627f800000 5e7f57a5dc8513422b7579977f800000 inf inf
+m roundss_010 a9b3e9a3c3904619f63f1c4b7f800000 86aa11887877a6d849b3512b7f800000 inf inf
+r roundss_011 719d0091bedc6be2af5ad8447f800000 c427c35c3abfacfd952051057f800000 inf inf
+m roundss_011 bc404be66e836250454c3b397f800000 7443688dbee9625eec89f5107f800000 inf inf
+r roundss_000 e8e8c80e6e12660f94e0c017ff800000 f349fc88a17f04a72ababa3aff800000 -inf -inf
+m roundss_000 50e072765b13b4cc78e1e3c8ff800000 9b877bb77e0fce842b7e1a6eff800000 -inf -inf
+r roundss_001 4f764588d0158833cd1c203aff800000 c947e188f225fba0cba39399ff800000 -inf -inf
+m roundss_001 43f43eb269a11eef6f5df458ff800000 d9d62b65994cc8a7e6f3a0a5ff800000 -inf -inf
+r roundss_010 87a7575fc345b1ad3a70d90eff800000 278154bc0d107047583cbe7fff800000 -inf -inf
+m roundss_010 76db8efa7a8c7e190a204d47ff800000 0f9158f8edfd3129fd486714ff800000 -inf -inf
+r roundss_011 6edcdff12903c0debb3bccf1ff800000 ed553385d2a045fcb1e4194eff800000 -inf -inf
+m roundss_011 c9f644af6c35b5a9298bd0f8ff800000 1d18e1cf5b84e96a50db4f1bff800000 -inf -inf
+r roundss_000 e575baa0e0ae972530ded746ffc00000 fb255f422135581fb5fb8666ffc00000 nan nan
+m roundss_000 1ca43e3121fba3ffacfe5cc8ffc00000 e3caa84ac240cfc8be0f381affc00000 nan nan
+r roundss_001 cbd0cbcccaa715e279b7db6affc00000 3151b853da308a1146e2e325ffc00000 nan nan
+m roundss_001 4f455ede773e287b72d7d019ffc00000 41078bca0492c5a629410272ffc00000 nan nan
+r roundss_010 024ff1d4c54d19767529b7bfffc00000 6f381e19ddf1bb3242f811edffc00000 nan nan
+m roundss_010 413a82184f5f247e5d780d4affc00000 162f6cae00d9a9616fd38c83ffc00000 nan nan
+r roundss_011 69510c18b200844005914da5ffc00000 943a71f409d6cbe08b9ef01effc00000 nan nan
+m roundss_011 d4e28b3f89bd76674b41f3bcffc00000 44a3295695755d5b7124b8abffc00000 nan nan
+r roundss_000 df37fbf8712136a00a527c7a7fc00000 81b790423f419a7dff3260177fc00000 nan nan
+m roundss_000 e69d59b105b800971d9062cd7fc00000 a9c2a323a4c7bff31095644c7fc00000 nan nan
+r roundss_001 45609fd5e10f0ff762c923a17fc00000 17105d65609208697f1740387fc00000 nan nan
+m roundss_001 59cccbd0a3b1a06db3c73ae07fc00000 26edba740e2eb08a2a8571c67fc00000 nan nan
+r roundss_010 7c2dd90fe42aefa4ee5824777fc00000 34a5b6bd4a28f403ebaa72e27fc00000 nan nan
+m roundss_010 0bcec3fc42073749ed465b527fc00000 9c834eaab10a107f9f54bf777fc00000 nan nan
+r roundss_011 62fd870459d3b6088d5e5d5e7fc00000 b9d47da8de6340ab234dd4747fc00000 nan nan
+m roundss_011 dd041f94c41ba68cab6ca5867fc00000 e9e53f246ebcbf3251632ec27fc00000 nan nan
+r roundss_000 d8308a161f694382213cafb5bfa66666 86ff9089fca3cac10660484ebf800000 -1.300000 -1.000000
+m roundss_000 afcdc1f8074ccb95cd99f7d9bfa66666 ed716c4224a49d041f119e04bf800000 -1.300000 -1.000000
+r roundss_001 be27c1a5174d78728950faddbfa66666 7b86d0bd834973a67642acd1c0000000 -1.300000 -2.000000
+m roundss_001 60898789ecfa86c5322e33adbfa66666 8a89b765b5208954e8beee9fc0000000 -1.300000 -2.000000
+r roundss_010 f3400e1021de3339a4fd1e35bfa66666 77c81da655b51bba5253e15cbf800000 -1.300000 -1.000000
+m roundss_010 d29952a65385b97bbb8a3761bfa66666 9f8dfeec009265838ecb00f2bf800000 -1.300000 -1.000000
+r roundss_011 59de50b71e7c553654a0fa1dbfa66666 5c2557a35145a25b79f3c74fbf800000 -1.300000 -1.000000
+m roundss_011 e45c02af1c4e4317490de456bfa66666 0bdc2237e45a0fefef97b25ebf800000 -1.300000 -1.000000
+r roundss_000 ce5f66faeb88beca779c70f6bf8ccccd 08fe5d15565be8ebcc833e0bbf800000 -1.100000 -1.000000
+m roundss_000 7532770527b503faba181aebbf8ccccd b0d603a742d668fbec83e542bf800000 -1.100000 -1.000000
+r roundss_001 3423313a6b614e53ee4e5e1fbf8ccccd 5db2115b4557cdca2b6225efc0000000 -1.100000 -2.000000
+m roundss_001 667c91075419db83ef0ab980bf8ccccd 6cdc819cfa68500465ee79fec0000000 -1.100000 -2.000000
+r roundss_010 698a92d77d68e5349918a6f9bf8ccccd 39a151d5fe98305776f15e5cbf800000 -1.100000 -1.000000
+m roundss_010 9799301582daa912c843a176bf8ccccd 204d7c74ed70a76c3a384ef3bf800000 -1.100000 -1.000000
+r roundss_011 4ef5672f00fb63ca585926e3bf8ccccd 7d2cfee4617ef2f28d8fc7b1bf800000 -1.100000 -1.000000
+m roundss_011 e8ea339093584e082524b12cbf8ccccd ac89d491f84d4d934bc24480bf800000 -1.100000 -1.000000
+r roundss_000 c3c391a4d67da7770a72bf3dbf666666 09b2f9e74e69f4fb509d414ebf800000 -0.900000 -1.000000
+m roundss_000 39ce7bd765f4aac4e50dcb02bf666666 f0f16952fe5f22d777eb3b06bf800000 -0.900000 -1.000000
+r roundss_001 a855ef96dd4b939b91c15167bf666666 bd93203fa5ba14d39e79ad94bf800000 -0.900000 -1.000000
+m roundss_001 6aa5e94bd90e9da7ea5ccd59bf666666 cce41a18de07069ba01413e4bf800000 -0.900000 -1.000000
+r roundss_010 dc0a6363f6c70594cca9bcc2bf666666 7830544b46d033d95986e9e280000000 -0.900000 -0.000000
+m roundss_010 5bd05b4bcf04071012739990bf666666 1fc3c84278a4d83ca49bab7a80000000 -0.900000 -0.000000
+r roundss_011 4142cc6e0151dec49a87e0aebf666666 1ce8746b100c316e5f21d69880000000 -0.900000 -0.000000
+m roundss_011 ebaeb2372738c75f3fb20d08bf666666 cbec5431ab96791c64e3e42980000000 -0.900000 -0.000000
+r roundss_000 b55e0914de47fe8bdcbe9c8abf333333 871c6200e4cdeef191ac5317bf800000 -0.700000 -1.000000
+m roundss_000 fc9fce70c10abff54f770a20bf333333 aec29c43583eca9ac1499f50bf800000 -0.700000 -1.000000
+r roundss_001 1abdfbb76d0b454872abd2b6bf333333 9b2bfd69a37449c3cf8642bfbf800000 -0.700000 -1.000000
+m roundss_001 6c048e557dd8cd3123247038bf333333 a9a281db5ffba917992fba4fbf800000 -0.700000 -1.000000
+r roundss_010 4ec083b68efd935b3cb06092bf333333 367524062b5f2442f91082ee80000000 -0.700000 -0.000000
+m roundss_010 1c3cd4473b05d3739b191eb1bf333333 9ceee356a12df7f2ccf4168780000000 -0.700000 -0.000000
+r roundss_011 32c57f72207cc8251a2c277fbf333333 395bb8385df15dd1efa9f20680000000 -0.700000 -0.000000
+m roundss_011 eca87fa5daeeaf1c96b5f6eabf333333 6706a116fb35948b3cf9935780000000 -0.700000 -0.000000
+r roundss_000 a62fd04a04e8c304ec8007dcbf0000a8 843c995e1987d6cd91b17366bf800000 -0.500010 -1.000000
+m roundss_000 bca76ecf3bf5428bf658d743bf0000a8 ea499d7b50735f43c89d1020bf800000 -0.500010 -1.000000
+r roundss_001 8a5b559f1ba1665b910ae00abf0000a8 f778a7d83e836d98be89e66fbf800000 -0.500010 -1.000000
+m roundss_001 6c9982253f796c209a63a01dbf0000a8 0517b5e37f453a794f416f41bf800000 -0.500010 -1.000000
+r roundss_010 beabf0cf43088f88eb2d9268bf0000a8 7170c207ae4403915890298080000000 -0.500010 -0.000000
+m roundss_010 dbdf9b08c4db0c3c613532d7bf0000a8 98d0cbb0670d038eb3448f1a80000000 -0.500010 -0.000000
+r roundss_011 217f803d5d7d1febd846fd56bf0000a8 d483ca4b472b78193d271dfa80000000 -0.500010 -0.000000
+m roundss_011 ebd899d8ab7a043f2c2e6dd2bf0000a8 82d5bd42ea2a9ce0d2064f0c80000000 -0.500010 -0.000000
+r roundss_000 9535e446495ef6e439b80035befffeb0 fe129f02eb97ac8f4eada13c80000000 -0.499990 -0.000000
+m roundss_000 7ae45cf4d3b63387dbaf316dbefffeb0 a4856cf8e6fde3d28de7907680000000 -0.499990 -0.000000
+r roundss_001 f82ffe4ce70ef4d4efe07d64befffeb0 d17c208e78e97e546b8297a6bf800000 -0.499990 -1.000000
+m roundss_001 6a64c4bc1ef078764f175e08befffeb0 df41b8323ce5b9c1c44832b8bf800000 -0.499990 -1.000000
+r roundss_010 2bcdacae16eaf91ad7205244befffeb0 2b212f4fcf7fd0c67407de9880000000 -0.499990 -0.000000
+m roundss_010 99b7b1906b87b46c65c6d404befffeb0 11688150cc43fe0f5789153380000000 -0.499990 -0.000000
+r roundss_011 0e6ecfcdb854e517d4d76034befffeb0 ed62aaa3d0bc8048499b557380000000 -0.499990 -0.000000
+m roundss_011 e83e02d199dcc7c7001d73c0befffeb0 1b5aa7b37676921c2608194680000000 -0.499990 -0.000000
+r roundss_000 81724708abab982ac5668794be99999a f79e72ed5bfd7037ca9edd9780000000 -0.300000 -0.000000
+m roundss_000 375799de8a4e91eaff7c1a9cbe99999a dd7809bb1ade554610281e5280000000 -0.300000 -0.000000
+r roundss_001 643af4c0d050f1b38a2ba7c4be99999a 2835678a50a47ef5d6715762bf800000 -0.300000 -1.000000
+m roundss_001 656554181c3df2324141abf9be99999a 362189c698dc26f0f74603b5bf800000 -0.300000 -1.000000
+r roundss_010 9725b55308a2d1130289a026be99999a 628869dc8e108be14f73a13780000000 -0.300000 -0.000000
+m roundss_010 54c514de300aca01a8ce0436be99999a 08b60537cfcfe777b9c4aad280000000 -0.300000 -0.000000
+r roundss_011 f9936c23310119a90ede5217be99999a 84f65842f7a2775c13059c7380000000 -0.300000 -0.000000
+m roundss_011 e3d9b990a614f9b6128306b4be99999a 31965e6ba117763d3801f10680000000 -0.300000 -0.000000
+r roundss_000 6ce5f7902ccea7d58f8a9df9bdcccccd 6de0141d69b921c50385277880000000 -0.100000 -0.000000
+m roundss_000 f101238f5ebb5eb260be91d2bdcccccd 932174c4ec15b4a1525ebab380000000 -0.100000 -0.000000
+r roundss_001 ce7a38f9d8685cf863ed602bbdcccccd fea57cccc6b66b7dff5624a5bf800000 -0.100000 -1.000000
+m roundss_001 5f9c323a3760db5472e185f0bdcccccd 0cb827a191288204e83ae339bf800000 -0.100000 -1.000000
+r roundss_010 00b20dbe172f17716b687c0dbdcccccd 18a572afecf734e2e7d5725b80000000 -0.100000 -0.000000
+m roundss_010 0d0ac5f213624efc284cc26fbdcccccd 7dba576370b0bec5daf54df780000000 -0.100000 -0.000000
+r roundss_011 e2ee5740c884baa1875ad200bdcccccd 9941d427bcdf5b579b64f0f980000000 -0.100000 -0.000000
+m roundss_011 dbabbe15d021980b625e27aebdcccccd c687e469690e484407f0d84d80000000 -0.100000 -0.000000
+r roundss_000 548df6decac624e7962440633dcccccd 62d8839316cbc139fb637fdf00000000 0.100000 0.000000
+m roundss_000 a9e0fb0650fe99e00077960d3dcccccd c780ad135ca102e2518a639b00000000 0.100000 0.000000
+r roundss_001 36f0caf8fe5634a37a25a7973dcccccd 52ca5f54d91d47eae631ff6e00000000 0.100000 0.000000
+m roundss_001 57095d22715931dce1f8eded3dcccccd 600494c229cacbfe9623d04200000000 0.100000 0.000000
+r roundss_010 6876b2ef4493cb3611bde6fb3dcccccd 4b7848c9e734cbc93e2e51053f800000 0.100000 1.000000
+m roundss_010 c584c4cb1490405ee7400ead3dcccccd 707377d5afe882f8b81cfda23f800000 0.100000 1.000000
+r roundss_011 c97f90227cddcaff3d4ddfef3dcccccd 2c421e521e712e37e1ba520400000000 0.100000 0.000000
+m roundss_011 d2b310611905a5c6f0afd7ae3dcccccd d92e37acd05b093195d4cc1900000000 0.100000 0.000000
+r roundss_000 3b6c42f286950f5fdc3471d43e99999a d486c05060334f93b036e5cc00000000 0.300000 0.000000
+m roundss_000 60f6214260184275dda6294f3e99999a 7995b5a86a843e090eac1b0900000000 0.300000 0.000000
+r roundss_001 9c9caabe421a7bb4cfd27b093e99999a 24a610228bdb103e8b02e9bc00000000 0.300000 0.000000
+m roundss_001 4dacd7d0c927f5ca8e84e4f03e99999a 3106cf285ec202de0303cbd200000000 0.300000 0.000000
+r roundss_010 cd70a6e690ccee61f688dfef3e99999a fc01ec2880c75096527c3d353f800000 0.300000 1.000000
+m roundss_010 7a35126b3395a025e3aae8f23e99999a e2e3658d8c7635125439bcd23f800000 0.300000 1.000000
+r roundss_011 af4717cb4f0c47c331b57be53e99999a 3df836c31f59eefee506c39600000000 0.300000 0.000000
+m roundss_011 c7f1b17280bf21e7bc7614b43e99999a 6a8c5936d4ffb705e1afce6c00000000 0.300000 0.000000
+r roundss_000 1f81ddcc6139683c60ba304b3efffeb0 c4eacc5248f1cbd32400593f00000000 0.499990 0.000000
+m roundss_000 144196458e07596ff84b4a963efffeb0 a95f8a8316bd671589c4e1fd00000000 0.499990 0.000000
+r roundss_001 007ed849a4b42f2c62f6de823efffeb0 74388f35dbeec777eec8e09100000000 0.499990 0.000000
+m roundss_001 41859f453ecc281e798668f93efffeb0 81bfd7d5321027a42ed9d4e700000000 0.499990 0.000000
+r roundss_010 319fe7a3f9dc7ef119c965e93efffeb0 2c405fcdb7b0c24925c138eb3f800000 0.499990 1.000000
+m roundss_010 2d1badd1706f6d521d894f3c3efffeb0 d109228b0759d612ae4c89893f800000 0.499990 1.000000
+r roundss_011 9244ec39401133ed6394a4e03efffeb0 cb651c7abe989caaa74841ae00000000 0.499990 0.000000
+m roundss_011 ba65a049044f0a6ec6b4dfc03efffeb0 789f490577f853beeb80de4400000000 0.499990 0.000000
+r roundss_000 02ccc56c59b42f8021b67dc83f0000a8 3304a59ace0535f955bfdb383f800000 0.500010 1.000000
+m roundss_000 c6c3580edaccddcf5265f9e43f0000a8 58e02da4604c7f08c3d2b4773f800000 0.500010 1.000000
+r roundss_001 6297549b24245209338fce003f0000a8 427fdc8fc8576d970f85e6ec00000000 0.500010 0.000000
+m roundss_001 3393b57fd247c8d7a2ff7a083f0000a8 4f2daec7a3b53a5117a4ec8200000000 0.500010 0.000000
+r roundss_010 9305772680c27ce8798079e83f0000a8 d9369fb98def23e2b5fb41273f800000 0.500010 1.000000
+m roundss_010 df3896fccb1fa9e696df458d3f0000a8 3ee5accf209364f8c75664c63f800000 0.500010 1.000000
+r roundss_011 73770f6e4fec8c7dd3e85ce13f0000a8 d887cf76fb2c393d2780ce4b00000000 0.500010 0.000000
+m roundss_011 ab0fdde6a7b5615b0e6739d23f0000a8 0568061bb747dd5db246fca200000000 0.500010 0.000000
+r roundss_000 e34cfcd26f0564292128584a3f333333 1fd44d29f26f8d0545746bb83f800000 0.700000 1.000000
+m roundss_000 777a689d4468d096e9f635373f333333 84179e0b483085e1bad696773f800000 0.700000 1.000000
+r roundss_001 c2e51eb2c26ae24c429f4d843f333333 8e7df72f5417009cee38f9cc00000000 0.700000 0.000000
+m roundss_001 22d8187f8398d6f709ed1b1d3f333333 9b515300b3af3be3bd6611a400000000 0.700000 0.000000
+r roundss_010 f2a1546f267de84418ad1bee3f333333 05e1aeea00847261042b58e93f800000 0.700000 1.000000
+m roundss_010 8e8aceee45a653df4cabc9e33f333333 29770459d723e1c39d554c893f800000 0.700000 1.000000
+r roundss_011 52e080687c9d547481b3a1e93f333333 636051b9d517c3b565ae686f00000000 0.700000 0.000000
+m roundss_011 9aef684968f127ae939020ea3f333333 10e8927696ec55e23803298700000000 0.700000 0.000000
+r roundss_000 c10380fea42b07395f10c1d33f666666 8a5ac2fdb52fd3f7f22009bd3f800000 0.900000 1.000000
+m roundss_000 2568c6f1ccd931c2bffd00913f666666 2e04ddb8ce6b79a06fd086fd3f800000 0.900000 1.000000
+r roundss_001 216936907d86e1f590245a0e3f666666 5830e0157e2c82888be11b3300000000 0.900000 0.000000
+m roundss_001 1053ca4553bf527dae5149383f666666 642cc57f60ff2b5b221d444b00000000 0.900000 0.000000
+r roundss_010 5073807ee90fc207f5504bfa3f666666 ae428a61116fafc610527d323f800000 0.900000 1.000000
+m roundss_010 3b1353a6dc026b3f41eddb403f666666 92bf2a292c094c75314a43d23f800000 0.900000 1.000000
+r roundss_011 2f7f3f29c72589d06df375f63f666666 6ceea1424e573c1461d2111900000000 0.900000 0.000000
+m roundss_011 8605407346035a66572f96083f666666 981dec1812e8bc4e7cb663f100000000 0.900000 0.000000
+r roundss_000 9ef053f0f62818afda6eb8623f8ccccd 72960517154507cf5ec1b5483f800000 1.100000 1.000000
+m roundss_000 d18b730c72200055d27a59f03f8ccccd 56a7eaabf2fc5a44e2c184093f800000 1.100000 1.000000
+r roundss_001 7d239c3357784d041b20f49f3f8ccccd a09a97414698f159e6804a203f800000 1.100000 1.000000
+m roundss_001 fc04cad241bc3d69912b05593f8ccccd acbc0643aca508b945cb85793f800000 1.100000 1.000000
+r roundss_010 ab7af953ca760a300f69090c3f8ccccd d659341fc0b0da11db6eb00040000000 1.100000 2.000000
+m roundss_010 e7d126249134f10473a47ba23f8ccccd 7abc1e3f1f44a40d833548a140000000 1.100000 2.000000
+r roundss_011 0a554caf30822d9298aad7093f8ccccd f333bf1165eea2581becc7483f800000 1.100000 1.000000
+m roundss_011 7151676243eafb855945992c3f8ccccd 9f0813002d39109f7e5eabe23f800000 1.100000 1.000000
+r roundss_000 781273a866fa978a94423df73fa66666 d989177813b1298d87596f593f800000 1.300000 1.000000
+m roundss_000 7ce46ded373e3d4d236c40563fa66666 fc00c6e4b4e22acf14a78f9b3f800000 1.300000 1.000000
+r roundss_001 d713509d4f402879e4911d353fa66666 66b91bb3ab594f11ff1588923f800000 1.300000 1.000000
+m roundss_001 e6eb18244c8f95bbb17c50803fa66666 7202154e95a2d3fe266fd42c3f800000 1.300000 1.000000
+r roundss_010 05b8c1eecab4c0be68f855233fa66666 7b26ad220e47f3426380f15440000000 1.300000 2.000000
+m roundss_010 90c54767643de42fe3d2a90b3fa66666 df70e09bb0d6eb8b94165af640000000 1.300000 2.000000
+r roundss_011 e360a7fcb6b53fba00d6c6223fa66666 f82dab261adaf78393fc8cfe3f800000 1.300000 1.000000
+m roundss_011 5ad3dc175da80b0a99d02a563fa66666 24aa092de5e052d63dfd01583f800000 1.300000 1.000000
+r roundpd_000 bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+m roundpd_000 bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+r roundpd_001 bfdfffd60e94ee390000000000000000 bff00000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -1.000000
+m roundpd_001 bfdfffd60e94ee390000000000000000 bff00000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -1.000000
+r roundpd_010 bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+m roundpd_010 bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+r roundpd_011 bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+m roundpd_011 bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+r roundpd_000 bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+m roundpd_000 bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+r roundpd_001 bfd33333333333338000000000000000 bff00000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -1.000000
+m roundpd_001 bfd33333333333338000000000000000 bff00000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -1.000000
+r roundpd_010 bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+m roundpd_010 bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+r roundpd_011 bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+m roundpd_011 bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+r roundpd_000 bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+m roundpd_000 bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+r roundpd_001 bfb999999999999a7ff0000000000000 bff00000000000007ff0000000000000 inf -> inf -0.100000 -> -1.000000
+m roundpd_001 bfb999999999999a7ff0000000000000 bff00000000000007ff0000000000000 inf -> inf -0.100000 -> -1.000000
+r roundpd_010 bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+m roundpd_010 bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+r roundpd_011 bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+m roundpd_011 bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+r roundpd_000 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+m roundpd_000 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+r roundpd_001 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+m roundpd_001 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+r roundpd_010 3fb999999999999afff0000000000000 3ff0000000000000fff0000000000000 -inf -> -inf 0.100000 -> 1.000000
+m roundpd_010 3fb999999999999afff0000000000000 3ff0000000000000fff0000000000000 -inf -> -inf 0.100000 -> 1.000000
+r roundpd_011 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+m roundpd_011 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+r roundpd_000 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+m roundpd_000 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+r roundpd_001 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+m roundpd_001 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+r roundpd_010 3fd3333333333333fff8000000000000 3ff0000000000000fff8000000000000 nan -> nan 0.300000 -> 1.000000
+m roundpd_010 3fd3333333333333fff8000000000000 3ff0000000000000fff8000000000000 nan -> nan 0.300000 -> 1.000000
+r roundpd_011 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+m roundpd_011 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+r roundpd_000 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+m roundpd_000 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+r roundpd_001 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+m roundpd_001 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+r roundpd_010 3fdfffd60e94ee397ff8000000000000 3ff00000000000007ff8000000000000 nan -> nan 0.499990 -> 1.000000
+m roundpd_010 3fdfffd60e94ee397ff8000000000000 3ff00000000000007ff8000000000000 nan -> nan 0.499990 -> 1.000000
+r roundpd_011 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+m roundpd_011 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+r roundpd_000 3fe00014f8b588e3bff4cccccccccccd 3ff0000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 1.000000
+m roundpd_000 3fe00014f8b588e3bff4cccccccccccd 3ff0000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 1.000000
+r roundpd_001 3fe00014f8b588e3bff4cccccccccccd 0000000000000000c000000000000000 -1.300000 -> -2.000000 0.500010 -> 0.000000
+m roundpd_001 3fe00014f8b588e3bff4cccccccccccd 0000000000000000c000000000000000 -1.300000 -> -2.000000 0.500010 -> 0.000000
+r roundpd_010 3fe00014f8b588e3bff4cccccccccccd 3ff0000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 1.000000
+m roundpd_010 3fe00014f8b588e3bff4cccccccccccd 3ff0000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 1.000000
+r roundpd_011 3fe00014f8b588e3bff4cccccccccccd 0000000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 0.000000
+m roundpd_011 3fe00014f8b588e3bff4cccccccccccd 0000000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 0.000000
+r roundpd_000 3fe6666666666666bff199999999999a 3ff0000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 1.000000
+m roundpd_000 3fe6666666666666bff199999999999a 3ff0000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 1.000000
+r roundpd_001 3fe6666666666666bff199999999999a 0000000000000000c000000000000000 -1.100000 -> -2.000000 0.700000 -> 0.000000
+m roundpd_001 3fe6666666666666bff199999999999a 0000000000000000c000000000000000 -1.100000 -> -2.000000 0.700000 -> 0.000000
+r roundpd_010 3fe6666666666666bff199999999999a 3ff0000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 1.000000
+m roundpd_010 3fe6666666666666bff199999999999a 3ff0000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 1.000000
+r roundpd_011 3fe6666666666666bff199999999999a 0000000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 0.000000
+m roundpd_011 3fe6666666666666bff199999999999a 0000000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 0.000000
+r roundpd_000 3feccccccccccccdbfeccccccccccccd 3ff0000000000000bff0000000000000 -0.900000 -> -1.000000 0.900000 -> 1.000000
+m roundpd_000 3feccccccccccccdbfeccccccccccccd 3ff0000000000000bff0000000000000 -0.900000 -> -1.000000 0.900000 -> 1.000000
+r roundpd_001 3feccccccccccccdbfeccccccccccccd 0000000000000000bff0000000000000 -0.900000 -> -1.000000 0.900000 -> 0.000000
+m roundpd_001 3feccccccccccccdbfeccccccccccccd 0000000000000000bff0000000000000 -0.900000 -> -1.000000 0.900000 -> 0.000000
+r roundpd_010 3feccccccccccccdbfeccccccccccccd 3ff00000000000008000000000000000 -0.900000 -> -0.000000 0.900000 -> 1.000000
+m roundpd_010 3feccccccccccccdbfeccccccccccccd 3ff00000000000008000000000000000 -0.900000 -> -0.000000 0.900000 -> 1.000000
+r roundpd_011 3feccccccccccccdbfeccccccccccccd 00000000000000008000000000000000 -0.900000 -> -0.000000 0.900000 -> 0.000000
+m roundpd_011 3feccccccccccccdbfeccccccccccccd 00000000000000008000000000000000 -0.900000 -> -0.000000 0.900000 -> 0.000000
+r roundpd_000 3ff199999999999abfe6666666666666 3ff0000000000000bff0000000000000 -0.700000 -> -1.000000 1.100000 -> 1.000000
+m roundpd_000 3ff199999999999abfe6666666666666 3ff0000000000000bff0000000000000 -0.700000 -> -1.000000 1.100000 -> 1.000000
+r roundpd_001 3ff199999999999abfe6666666666666 3ff0000000000000bff0000000000000 -0.700000 -> -1.000000 1.100000 -> 1.000000
+m roundpd_001 3ff199999999999abfe6666666666666 3ff0000000000000bff0000000000000 -0.700000 -> -1.000000 1.100000 -> 1.000000
+r roundpd_010 3ff199999999999abfe6666666666666 40000000000000008000000000000000 -0.700000 -> -0.000000 1.100000 -> 2.000000
+m roundpd_010 3ff199999999999abfe6666666666666 40000000000000008000000000000000 -0.700000 -> -0.000000 1.100000 -> 2.000000
+r roundpd_011 3ff199999999999abfe6666666666666 3ff00000000000008000000000000000 -0.700000 -> -0.000000 1.100000 -> 1.000000
+m roundpd_011 3ff199999999999abfe6666666666666 3ff00000000000008000000000000000 -0.700000 -> -0.000000 1.100000 -> 1.000000
+r roundpd_000 3ff4cccccccccccdbfe00014f8b588e3 3ff0000000000000bff0000000000000 -0.500010 -> -1.000000 1.300000 -> 1.000000
+m roundpd_000 3ff4cccccccccccdbfe00014f8b588e3 3ff0000000000000bff0000000000000 -0.500010 -> -1.000000 1.300000 -> 1.000000
+r roundpd_001 3ff4cccccccccccdbfe00014f8b588e3 3ff0000000000000bff0000000000000 -0.500010 -> -1.000000 1.300000 -> 1.000000
+m roundpd_001 3ff4cccccccccccdbfe00014f8b588e3 3ff0000000000000bff0000000000000 -0.500010 -> -1.000000 1.300000 -> 1.000000
+r roundpd_010 3ff4cccccccccccdbfe00014f8b588e3 40000000000000008000000000000000 -0.500010 -> -0.000000 1.300000 -> 2.000000
+m roundpd_010 3ff4cccccccccccdbfe00014f8b588e3 40000000000000008000000000000000 -0.500010 -> -0.000000 1.300000 -> 2.000000
+r roundpd_011 3ff4cccccccccccdbfe00014f8b588e3 3ff00000000000008000000000000000 -0.500010 -> -0.000000 1.300000 -> 1.000000
+m roundpd_011 3ff4cccccccccccdbfe00014f8b588e3 3ff00000000000008000000000000000 -0.500010 -> -0.000000 1.300000 -> 1.000000
+r roundpd_000 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+m roundpd_000 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+r roundpd_001 0000000000000000bfdfffd60e94ee39 0000000000000000bff0000000000000 -0.499990 -> -1.000000 0.000000 -> 0.000000
+m roundpd_001 0000000000000000bfdfffd60e94ee39 0000000000000000bff0000000000000 -0.499990 -> -1.000000 0.000000 -> 0.000000
+r roundpd_010 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+m roundpd_010 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+r roundpd_011 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+m roundpd_011 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+r roundpd_000 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+m roundpd_000 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+r roundpd_001 8000000000000000bfd3333333333333 8000000000000000bff0000000000000 -0.300000 -> -1.000000 -0.000000 -> -0.000000
+m roundpd_001 8000000000000000bfd3333333333333 8000000000000000bff0000000000000 -0.300000 -> -1.000000 -0.000000 -> -0.000000
+r roundpd_010 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+m roundpd_010 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+r roundpd_011 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+m roundpd_011 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+r roundpd_000 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+m roundpd_000 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+r roundpd_001 7ff0000000000000bfb999999999999a 7ff0000000000000bff0000000000000 -0.100000 -> -1.000000 inf -> inf
+m roundpd_001 7ff0000000000000bfb999999999999a 7ff0000000000000bff0000000000000 -0.100000 -> -1.000000 inf -> inf
+r roundpd_010 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+m roundpd_010 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+r roundpd_011 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+m roundpd_011 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+r roundpd_000 fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+m roundpd_000 fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+r roundpd_001 fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+m roundpd_001 fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+r roundpd_010 fff00000000000003fb999999999999a fff00000000000003ff0000000000000 0.100000 -> 1.000000 -inf -> -inf
+m roundpd_010 fff00000000000003fb999999999999a fff00000000000003ff0000000000000 0.100000 -> 1.000000 -inf -> -inf
+r roundpd_011 fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+m roundpd_011 fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+r roundpd_000 fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+m roundpd_000 fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+r roundpd_001 fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+m roundpd_001 fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+r roundpd_010 fff80000000000003fd3333333333333 fff80000000000003ff0000000000000 0.300000 -> 1.000000 nan -> nan
+m roundpd_010 fff80000000000003fd3333333333333 fff80000000000003ff0000000000000 0.300000 -> 1.000000 nan -> nan
+r roundpd_011 fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+m roundpd_011 fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+r roundpd_000 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+m roundpd_000 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+r roundpd_001 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+m roundpd_001 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+r roundpd_010 7ff80000000000003fdfffd60e94ee39 7ff80000000000003ff0000000000000 0.499990 -> 1.000000 nan -> nan
+m roundpd_010 7ff80000000000003fdfffd60e94ee39 7ff80000000000003ff0000000000000 0.499990 -> 1.000000 nan -> nan
+r roundpd_011 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+m roundpd_011 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+r roundpd_000 bff4cccccccccccd3fe00014f8b588e3 bff00000000000003ff0000000000000 0.500010 -> 1.000000 -1.300000 -> -1.000000
+m roundpd_000 bff4cccccccccccd3fe00014f8b588e3 bff00000000000003ff0000000000000 0.500010 -> 1.000000 -1.300000 -> -1.000000
+r roundpd_001 bff4cccccccccccd3fe00014f8b588e3 c0000000000000000000000000000000 0.500010 -> 0.000000 -1.300000 -> -2.000000
+m roundpd_001 bff4cccccccccccd3fe00014f8b588e3 c0000000000000000000000000000000 0.500010 -> 0.000000 -1.300000 -> -2.000000
+r roundpd_010 bff4cccccccccccd3fe00014f8b588e3 bff00000000000003ff0000000000000 0.500010 -> 1.000000 -1.300000 -> -1.000000
+m roundpd_010 bff4cccccccccccd3fe00014f8b588e3 bff00000000000003ff0000000000000 0.500010 -> 1.000000 -1.300000 -> -1.000000
+r roundpd_011 bff4cccccccccccd3fe00014f8b588e3 bff00000000000000000000000000000 0.500010 -> 0.000000 -1.300000 -> -1.000000
+m roundpd_011 bff4cccccccccccd3fe00014f8b588e3 bff00000000000000000000000000000 0.500010 -> 0.000000 -1.300000 -> -1.000000
+r roundpd_000 bff199999999999a3fe6666666666666 bff00000000000003ff0000000000000 0.700000 -> 1.000000 -1.100000 -> -1.000000
+m roundpd_000 bff199999999999a3fe6666666666666 bff00000000000003ff0000000000000 0.700000 -> 1.000000 -1.100000 -> -1.000000
+r roundpd_001 bff199999999999a3fe6666666666666 c0000000000000000000000000000000 0.700000 -> 0.000000 -1.100000 -> -2.000000
+m roundpd_001 bff199999999999a3fe6666666666666 c0000000000000000000000000000000 0.700000 -> 0.000000 -1.100000 -> -2.000000
+r roundpd_010 bff199999999999a3fe6666666666666 bff00000000000003ff0000000000000 0.700000 -> 1.000000 -1.100000 -> -1.000000
+m roundpd_010 bff199999999999a3fe6666666666666 bff00000000000003ff0000000000000 0.700000 -> 1.000000 -1.100000 -> -1.000000
+r roundpd_011 bff199999999999a3fe6666666666666 bff00000000000000000000000000000 0.700000 -> 0.000000 -1.100000 -> -1.000000
+m roundpd_011 bff199999999999a3fe6666666666666 bff00000000000000000000000000000 0.700000 -> 0.000000 -1.100000 -> -1.000000
+r roundpd_000 bfeccccccccccccd3feccccccccccccd bff00000000000003ff0000000000000 0.900000 -> 1.000000 -0.900000 -> -1.000000
+m roundpd_000 bfeccccccccccccd3feccccccccccccd bff00000000000003ff0000000000000 0.900000 -> 1.000000 -0.900000 -> -1.000000
+r roundpd_001 bfeccccccccccccd3feccccccccccccd bff00000000000000000000000000000 0.900000 -> 0.000000 -0.900000 -> -1.000000
+m roundpd_001 bfeccccccccccccd3feccccccccccccd bff00000000000000000000000000000 0.900000 -> 0.000000 -0.900000 -> -1.000000
+r roundpd_010 bfeccccccccccccd3feccccccccccccd 80000000000000003ff0000000000000 0.900000 -> 1.000000 -0.900000 -> -0.000000
+m roundpd_010 bfeccccccccccccd3feccccccccccccd 80000000000000003ff0000000000000 0.900000 -> 1.000000 -0.900000 -> -0.000000
+r roundpd_011 bfeccccccccccccd3feccccccccccccd 80000000000000000000000000000000 0.900000 -> 0.000000 -0.900000 -> -0.000000
+m roundpd_011 bfeccccccccccccd3feccccccccccccd 80000000000000000000000000000000 0.900000 -> 0.000000 -0.900000 -> -0.000000
+r roundpd_000 bfe66666666666663ff199999999999a bff00000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -1.000000
+m roundpd_000 bfe66666666666663ff199999999999a bff00000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -1.000000
+r roundpd_001 bfe66666666666663ff199999999999a bff00000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -1.000000
+m roundpd_001 bfe66666666666663ff199999999999a bff00000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -1.000000
+r roundpd_010 bfe66666666666663ff199999999999a 80000000000000004000000000000000 1.100000 -> 2.000000 -0.700000 -> -0.000000
+m roundpd_010 bfe66666666666663ff199999999999a 80000000000000004000000000000000 1.100000 -> 2.000000 -0.700000 -> -0.000000
+r roundpd_011 bfe66666666666663ff199999999999a 80000000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -0.000000
+m roundpd_011 bfe66666666666663ff199999999999a 80000000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -0.000000
+r roundpd_000 bfe00014f8b588e33ff4cccccccccccd bff00000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -1.000000
+m roundpd_000 bfe00014f8b588e33ff4cccccccccccd bff00000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -1.000000
+r roundpd_001 bfe00014f8b588e33ff4cccccccccccd bff00000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -1.000000
+m roundpd_001 bfe00014f8b588e33ff4cccccccccccd bff00000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -1.000000
+r roundpd_010 bfe00014f8b588e33ff4cccccccccccd 80000000000000004000000000000000 1.300000 -> 2.000000 -0.500010 -> -0.000000
+m roundpd_010 bfe00014f8b588e33ff4cccccccccccd 80000000000000004000000000000000 1.300000 -> 2.000000 -0.500010 -> -0.000000
+r roundpd_011 bfe00014f8b588e33ff4cccccccccccd 80000000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -0.000000
+m roundpd_011 bfe00014f8b588e33ff4cccccccccccd 80000000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -0.000000
+r roundps_000 3f0000a8befffeb07fc0000000000000 3f800000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 1.000000
+m roundps_000 3f0000a8befffeb07fc0000000000000 3f800000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 1.000000
+r roundps_001 3f0000a8befffeb07fc0000000000000 00000000bf8000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-1.000000 0.500010: 0.000000
+m roundps_001 3f0000a8befffeb07fc0000000000000 00000000bf8000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-1.000000 0.500010: 0.000000
+r roundps_010 3f0000a8befffeb07fc0000000000000 3f800000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 1.000000
+m roundps_010 3f0000a8befffeb07fc0000000000000 3f800000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 1.000000
+r roundps_011 3f0000a8befffeb07fc0000000000000 00000000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 0.000000
+m roundps_011 3f0000a8befffeb07fc0000000000000 00000000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 0.000000
+r roundps_000 3f333333be99999abfa6666680000000 3f80000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000
+m roundps_000 3f333333be99999abfa6666680000000 3f80000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000
+r roundps_001 3f333333be99999abfa6666680000000 00000000bf800000c000000080000000 -0.000000:-0.000000 -1.300000:-2.000000 -0.300000:-1.000000 0.700000: 0.000000
+m roundps_001 3f333333be99999abfa6666680000000 00000000bf800000c000000080000000 -0.000000:-0.000000 -1.300000:-2.000000 -0.300000:-1.000000 0.700000: 0.000000
+r roundps_010 3f333333be99999abfa6666680000000 3f80000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000
+m roundps_010 3f333333be99999abfa6666680000000 3f80000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000
+r roundps_011 3f333333be99999abfa6666680000000 0000000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 0.000000
+m roundps_011 3f333333be99999abfa6666680000000 0000000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 0.000000
+r roundps_000 3f666666bdcccccdbf8ccccd7f800000 3f80000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000
+m roundps_000 3f666666bdcccccdbf8ccccd7f800000 3f80000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000
+r roundps_001 3f666666bdcccccdbf8ccccd7f800000 00000000bf800000c00000007f800000 inf: inf -1.100000:-2.000000 -0.100000:-1.000000 0.900000: 0.000000
+m roundps_001 3f666666bdcccccdbf8ccccd7f800000 00000000bf800000c00000007f800000 inf: inf -1.100000:-2.000000 -0.100000:-1.000000 0.900000: 0.000000
+r roundps_010 3f666666bdcccccdbf8ccccd7f800000 3f80000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000
+m roundps_010 3f666666bdcccccdbf8ccccd7f800000 3f80000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000
+r roundps_011 3f666666bdcccccdbf8ccccd7f800000 0000000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 0.000000
+m roundps_011 3f666666bdcccccdbf8ccccd7f800000 0000000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 0.000000
+r roundps_000 3f8ccccd3dcccccdbf666666ff800000 3f80000000000000bf800000ff800000 -inf: -inf -0.900000:-1.000000 0.100000: 0.000000 1.100000: 1.000000
+m roundps_000 3f8ccccd3dcccccdbf666666ff800000 3f80000000000000bf800000ff800000 -inf: -inf -0.900000:-1.000000 0.100000: 0.000000 1.100000: 1.000000
+r roundps_001 3f8ccccd3dcccccdbf666666ff800000 3f80000000000000bf800000ff800000 -inf: -inf -0.900000:-1.000000 0.100000: 0.000000 1.100000: 1.000000
+m roundps_001 3f8ccccd3dcccccdbf666666ff800000 3f80000000000000bf800000ff800000 -inf: -inf -0.900000:-1.000000 0.100000: 0.000000 1.100000: 1.000000
+r roundps_010 3f8ccccd3dcccccdbf666666ff800000 400000003f80000080000000ff800000 -inf: -inf -0.900000:-0.000000 0.100000: 1.000000 1.100000: 2.000000
+m roundps_010 3f8ccccd3dcccccdbf666666ff800000 400000003f80000080000000ff800000 -inf: -inf -0.900000:-0.000000 0.100000: 1.000000 1.100000: 2.000000
+r roundps_011 3f8ccccd3dcccccdbf666666ff800000 3f8000000000000080000000ff800000 -inf: -inf -0.900000:-0.000000 0.100000: 0.000000 1.100000: 1.000000
+m roundps_011 3f8ccccd3dcccccdbf666666ff800000 3f8000000000000080000000ff800000 -inf: -inf -0.900000:-0.000000 0.100000: 0.000000 1.100000: 1.000000
+r roundps_000 3fa666663e99999abf333333ffc00000 3f80000000000000bf800000ffc00000 nan: nan -0.700000:-1.000000 0.300000: 0.000000 1.300000: 1.000000
+m roundps_000 3fa666663e99999abf333333ffc00000 3f80000000000000bf800000ffc00000 nan: nan -0.700000:-1.000000 0.300000: 0.000000 1.300000: 1.000000
+r roundps_001 3fa666663e99999abf333333ffc00000 3f80000000000000bf800000ffc00000 nan: nan -0.700000:-1.000000 0.300000: 0.000000 1.300000: 1.000000
+m roundps_001 3fa666663e99999abf333333ffc00000 3f80000000000000bf800000ffc00000 nan: nan -0.700000:-1.000000 0.300000: 0.000000 1.300000: 1.000000
+r roundps_010 3fa666663e99999abf333333ffc00000 400000003f80000080000000ffc00000 nan: nan -0.700000:-0.000000 0.300000: 1.000000 1.300000: 2.000000
+m roundps_010 3fa666663e99999abf333333ffc00000 400000003f80000080000000ffc00000 nan: nan -0.700000:-0.000000 0.300000: 1.000000 1.300000: 2.000000
+r roundps_011 3fa666663e99999abf333333ffc00000 3f8000000000000080000000ffc00000 nan: nan -0.700000:-0.000000 0.300000: 0.000000 1.300000: 1.000000
+m roundps_011 3fa666663e99999abf333333ffc00000 3f8000000000000080000000ffc00000 nan: nan -0.700000:-0.000000 0.300000: 0.000000 1.300000: 1.000000
+r roundps_000 000000003efffeb0bf0000a87fc00000 0000000000000000bf8000007fc00000 nan: nan -0.500010:-1.000000 0.499990: 0.000000 0.000000: 0.000000
+m roundps_000 000000003efffeb0bf0000a87fc00000 0000000000000000bf8000007fc00000 nan: nan -0.500010:-1.000000 0.499990: 0.000000 0.000000: 0.000000
+r roundps_001 000000003efffeb0bf0000a87fc00000 0000000000000000bf8000007fc00000 nan: nan -0.500010:-1.000000 0.499990: 0.000000 0.000000: 0.000000
+m roundps_001 000000003efffeb0bf0000a87fc00000 0000000000000000bf8000007fc00000 nan: nan -0.500010:-1.000000 0.499990: 0.000000 0.000000: 0.000000
+r roundps_010 000000003efffeb0bf0000a87fc00000 000000003f800000800000007fc00000 nan: nan -0.500010:-0.000000 0.499990: 1.000000 0.000000: 0.000000
+m roundps_010 000000003efffeb0bf0000a87fc00000 000000003f800000800000007fc00000 nan: nan -0.500010:-0.000000 0.499990: 1.000000 0.000000: 0.000000
+r roundps_011 000000003efffeb0bf0000a87fc00000 0000000000000000800000007fc00000 nan: nan -0.500010:-0.000000 0.499990: 0.000000 0.000000: 0.000000
+m roundps_011 000000003efffeb0bf0000a87fc00000 0000000000000000800000007fc00000 nan: nan -0.500010:-0.000000 0.499990: 0.000000 0.000000: 0.000000
+r roundps_000 800000003f0000a8befffeb0bfa66666 800000003f80000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 1.000000 -0.000000:-0.000000
+m roundps_000 800000003f0000a8befffeb0bfa66666 800000003f80000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 1.000000 -0.000000:-0.000000
+r roundps_001 800000003f0000a8befffeb0bfa66666 8000000000000000bf800000c0000000 -1.300000:-2.000000 -0.499990:-1.000000 0.500010: 0.000000 -0.000000:-0.000000
+m roundps_001 800000003f0000a8befffeb0bfa66666 8000000000000000bf800000c0000000 -1.300000:-2.000000 -0.499990:-1.000000 0.500010: 0.000000 -0.000000:-0.000000
+r roundps_010 800000003f0000a8befffeb0bfa66666 800000003f80000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 1.000000 -0.000000:-0.000000
+m roundps_010 800000003f0000a8befffeb0bfa66666 800000003f80000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 1.000000 -0.000000:-0.000000
+r roundps_011 800000003f0000a8befffeb0bfa66666 800000000000000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 0.000000 -0.000000:-0.000000
+m roundps_011 800000003f0000a8befffeb0bfa66666 800000000000000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 0.000000 -0.000000:-0.000000
+r roundps_000 7f8000003f333333be99999abf8ccccd 7f8000003f80000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000 inf: inf
+m roundps_000 7f8000003f333333be99999abf8ccccd 7f8000003f80000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000 inf: inf
+r roundps_001 7f8000003f333333be99999abf8ccccd 7f80000000000000bf800000c0000000 -1.100000:-2.000000 -0.300000:-1.000000 0.700000: 0.000000 inf: inf
+m roundps_001 7f8000003f333333be99999abf8ccccd 7f80000000000000bf800000c0000000 -1.100000:-2.000000 -0.300000:-1.000000 0.700000: 0.000000 inf: inf
+r roundps_010 7f8000003f333333be99999abf8ccccd 7f8000003f80000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000 inf: inf
+m roundps_010 7f8000003f333333be99999abf8ccccd 7f8000003f80000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000 inf: inf
+r roundps_011 7f8000003f333333be99999abf8ccccd 7f8000000000000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 0.000000 inf: inf
+m roundps_011 7f8000003f333333be99999abf8ccccd 7f8000000000000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 0.000000 inf: inf
+r roundps_000 ff8000003f666666bdcccccdbf666666 ff8000003f80000080000000bf800000 -0.900000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000 -inf: -inf
+m roundps_000 ff8000003f666666bdcccccdbf666666 ff8000003f80000080000000bf800000 -0.900000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000 -inf: -inf
+r roundps_001 ff8000003f666666bdcccccdbf666666 ff80000000000000bf800000bf800000 -0.900000:-1.000000 -0.100000:-1.000000 0.900000: 0.000000 -inf: -inf
+m roundps_001 ff8000003f666666bdcccccdbf666666 ff80000000000000bf800000bf800000 -0.900000:-1.000000 -0.100000:-1.000000 0.900000: 0.000000 -inf: -inf
+r roundps_010 ff8000003f666666bdcccccdbf666666 ff8000003f8000008000000080000000 -0.900000:-0.000000 -0.100000:-0.000000 0.900000: 1.000000 -inf: -inf
+m roundps_010 ff8000003f666666bdcccccdbf666666 ff8000003f8000008000000080000000 -0.900000:-0.000000 -0.100000:-0.000000 0.900000: 1.000000 -inf: -inf
+r roundps_011 ff8000003f666666bdcccccdbf666666 ff800000000000008000000080000000 -0.900000:-0.000000 -0.100000:-0.000000 0.900000: 0.000000 -inf: -inf
+m roundps_011 ff8000003f666666bdcccccdbf666666 ff800000000000008000000080000000 -0.900000:-0.000000 -0.100000:-0.000000 0.900000: 0.000000 -inf: -inf
+r roundps_000 ffc000003f8ccccd3dcccccdbf333333 ffc000003f80000000000000bf800000 -0.700000:-1.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+m roundps_000 ffc000003f8ccccd3dcccccdbf333333 ffc000003f80000000000000bf800000 -0.700000:-1.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+r roundps_001 ffc000003f8ccccd3dcccccdbf333333 ffc000003f80000000000000bf800000 -0.700000:-1.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+m roundps_001 ffc000003f8ccccd3dcccccdbf333333 ffc000003f80000000000000bf800000 -0.700000:-1.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+r roundps_010 ffc000003f8ccccd3dcccccdbf333333 ffc00000400000003f80000080000000 -0.700000:-0.000000 0.100000: 1.000000 1.100000: 2.000000 nan: nan
+m roundps_010 ffc000003f8ccccd3dcccccdbf333333 ffc00000400000003f80000080000000 -0.700000:-0.000000 0.100000: 1.000000 1.100000: 2.000000 nan: nan
+r roundps_011 ffc000003f8ccccd3dcccccdbf333333 ffc000003f8000000000000080000000 -0.700000:-0.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+m roundps_011 ffc000003f8ccccd3dcccccdbf333333 ffc000003f8000000000000080000000 -0.700000:-0.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+r roundps_000 7fc000003fa666663e99999abf0000a8 7fc000003f80000000000000bf800000 -0.500010:-1.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+m roundps_000 7fc000003fa666663e99999abf0000a8 7fc000003f80000000000000bf800000 -0.500010:-1.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+r roundps_001 7fc000003fa666663e99999abf0000a8 7fc000003f80000000000000bf800000 -0.500010:-1.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+m roundps_001 7fc000003fa666663e99999abf0000a8 7fc000003f80000000000000bf800000 -0.500010:-1.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+r roundps_010 7fc000003fa666663e99999abf0000a8 7fc00000400000003f80000080000000 -0.500010:-0.000000 0.300000: 1.000000 1.300000: 2.000000 nan: nan
+m roundps_010 7fc000003fa666663e99999abf0000a8 7fc00000400000003f80000080000000 -0.500010:-0.000000 0.300000: 1.000000 1.300000: 2.000000 nan: nan
+r roundps_011 7fc000003fa666663e99999abf0000a8 7fc000003f8000000000000080000000 -0.500010:-0.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+m roundps_011 7fc000003fa666663e99999abf0000a8 7fc000003f8000000000000080000000 -0.500010:-0.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+r roundps_000 bfa66666000000003efffeb0befffeb0 bf800000000000000000000080000000 -0.499990:-0.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-1.000000
+m roundps_000 bfa66666000000003efffeb0befffeb0 bf800000000000000000000080000000 -0.499990:-0.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-1.000000
+r roundps_001 bfa66666000000003efffeb0befffeb0 c00000000000000000000000bf800000 -0.499990:-1.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-2.000000
+m roundps_001 bfa66666000000003efffeb0befffeb0 c00000000000000000000000bf800000 -0.499990:-1.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-2.000000
+r roundps_010 bfa66666000000003efffeb0befffeb0 bf800000000000003f80000080000000 -0.499990:-0.000000 0.499990: 1.000000 0.000000: 0.000000 -1.300000:-1.000000
+m roundps_010 bfa66666000000003efffeb0befffeb0 bf800000000000003f80000080000000 -0.499990:-0.000000 0.499990: 1.000000 0.000000: 0.000000 -1.300000:-1.000000
+r roundps_011 bfa66666000000003efffeb0befffeb0 bf800000000000000000000080000000 -0.499990:-0.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-1.000000
+m roundps_011 bfa66666000000003efffeb0befffeb0 bf800000000000000000000080000000 -0.499990:-0.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-1.000000
+r roundps_000 bf8ccccd800000003f0000a8be99999a bf800000800000003f80000080000000 -0.300000:-0.000000 0.500010: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000
+m roundps_000 bf8ccccd800000003f0000a8be99999a bf800000800000003f80000080000000 -0.300000:-0.000000 0.500010: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000
+r roundps_001 bf8ccccd800000003f0000a8be99999a c00000008000000000000000bf800000 -0.300000:-1.000000 0.500010: 0.000000 -0.000000:-0.000000 -1.100000:-2.000000
+m roundps_001 bf8ccccd800000003f0000a8be99999a c00000008000000000000000bf800000 -0.300000:-1.000000 0.500010: 0.000000 -0.000000:-0.000000 -1.100000:-2.000000
+r roundps_010 bf8ccccd800000003f0000a8be99999a bf800000800000003f80000080000000 -0.300000:-0.000000 0.500010: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000
+m roundps_010 bf8ccccd800000003f0000a8be99999a bf800000800000003f80000080000000 -0.300000:-0.000000 0.500010: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000
+r roundps_011 bf8ccccd800000003f0000a8be99999a bf800000800000000000000080000000 -0.300000:-0.000000 0.500010: 0.000000 -0.000000:-0.000000 -1.100000:-1.000000
+m roundps_011 bf8ccccd800000003f0000a8be99999a bf800000800000000000000080000000 -0.300000:-0.000000 0.500010: 0.000000 -0.000000:-0.000000 -1.100000:-1.000000
+r roundps_000 bf6666667f8000003f333333bdcccccd bf8000007f8000003f80000080000000 -0.100000:-0.000000 0.700000: 1.000000 inf: inf -0.900000:-1.000000
+m roundps_000 bf6666667f8000003f333333bdcccccd bf8000007f8000003f80000080000000 -0.100000:-0.000000 0.700000: 1.000000 inf: inf -0.900000:-1.000000
+r roundps_001 bf6666667f8000003f333333bdcccccd bf8000007f80000000000000bf800000 -0.100000:-1.000000 0.700000: 0.000000 inf: inf -0.900000:-1.000000
+m roundps_001 bf6666667f8000003f333333bdcccccd bf8000007f80000000000000bf800000 -0.100000:-1.000000 0.700000: 0.000000 inf: inf -0.900000:-1.000000
+r roundps_010 bf6666667f8000003f333333bdcccccd 800000007f8000003f80000080000000 -0.100000:-0.000000 0.700000: 1.000000 inf: inf -0.900000:-0.000000
+m roundps_010 bf6666667f8000003f333333bdcccccd 800000007f8000003f80000080000000 -0.100000:-0.000000 0.700000: 1.000000 inf: inf -0.900000:-0.000000
+r roundps_011 bf6666667f8000003f333333bdcccccd 800000007f8000000000000080000000 -0.100000:-0.000000 0.700000: 0.000000 inf: inf -0.900000:-0.000000
+m roundps_011 bf6666667f8000003f333333bdcccccd 800000007f8000000000000080000000 -0.100000:-0.000000 0.700000: 0.000000 inf: inf -0.900000:-0.000000
+r roundps_000 bf333333ff8000003f6666663dcccccd bf800000ff8000003f80000000000000 0.100000: 0.000000 0.900000: 1.000000 -inf: -inf -0.700000:-1.000000
+m roundps_000 bf333333ff8000003f6666663dcccccd bf800000ff8000003f80000000000000 0.100000: 0.000000 0.900000: 1.000000 -inf: -inf -0.700000:-1.000000
+r roundps_001 bf333333ff8000003f6666663dcccccd bf800000ff8000000000000000000000 0.100000: 0.000000 0.900000: 0.000000 -inf: -inf -0.700000:-1.000000
+m roundps_001 bf333333ff8000003f6666663dcccccd bf800000ff8000000000000000000000 0.100000: 0.000000 0.900000: 0.000000 -inf: -inf -0.700000:-1.000000
+r roundps_010 bf333333ff8000003f6666663dcccccd 80000000ff8000003f8000003f800000 0.100000: 1.000000 0.900000: 1.000000 -inf: -inf -0.700000:-0.000000
+m roundps_010 bf333333ff8000003f6666663dcccccd 80000000ff8000003f8000003f800000 0.100000: 1.000000 0.900000: 1.000000 -inf: -inf -0.700000:-0.000000
+r roundps_011 bf333333ff8000003f6666663dcccccd 80000000ff8000000000000000000000 0.100000: 0.000000 0.900000: 0.000000 -inf: -inf -0.700000:-0.000000
+m roundps_011 bf333333ff8000003f6666663dcccccd 80000000ff8000000000000000000000 0.100000: 0.000000 0.900000: 0.000000 -inf: -inf -0.700000:-0.000000
+r roundps_000 bf0000a8ffc000003f8ccccd3e99999a bf800000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-1.000000
+m roundps_000 bf0000a8ffc000003f8ccccd3e99999a bf800000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-1.000000
+r roundps_001 bf0000a8ffc000003f8ccccd3e99999a bf800000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-1.000000
+m roundps_001 bf0000a8ffc000003f8ccccd3e99999a bf800000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-1.000000
+r roundps_010 bf0000a8ffc000003f8ccccd3e99999a 80000000ffc00000400000003f800000 0.300000: 1.000000 1.100000: 2.000000 nan: nan -0.500010:-0.000000
+m roundps_010 bf0000a8ffc000003f8ccccd3e99999a 80000000ffc00000400000003f800000 0.300000: 1.000000 1.100000: 2.000000 nan: nan -0.500010:-0.000000
+r roundps_011 bf0000a8ffc000003f8ccccd3e99999a 80000000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-0.000000
+m roundps_011 bf0000a8ffc000003f8ccccd3e99999a 80000000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-0.000000
+r roundps_000 befffeb07fc000003fa666663efffeb0 800000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-0.000000
+m roundps_000 befffeb07fc000003fa666663efffeb0 800000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-0.000000
+r roundps_001 befffeb07fc000003fa666663efffeb0 bf8000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-1.000000
+m roundps_001 befffeb07fc000003fa666663efffeb0 bf8000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-1.000000
+r roundps_010 befffeb07fc000003fa666663efffeb0 800000007fc00000400000003f800000 0.499990: 1.000000 1.300000: 2.000000 nan: nan -0.499990:-0.000000
+m roundps_010 befffeb07fc000003fa666663efffeb0 800000007fc00000400000003f800000 0.499990: 1.000000 1.300000: 2.000000 nan: nan -0.499990:-0.000000
+r roundps_011 befffeb07fc000003fa666663efffeb0 800000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-0.000000
+m roundps_011 befffeb07fc000003fa666663efffeb0 800000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-0.000000
+r roundps_000 be99999abfa66666000000003f0000a8 80000000bf800000000000003f800000 0.500010: 1.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+m roundps_000 be99999abfa66666000000003f0000a8 80000000bf800000000000003f800000 0.500010: 1.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+r roundps_001 be99999abfa66666000000003f0000a8 bf800000c00000000000000000000000 0.500010: 0.000000 0.000000: 0.000000 -1.300000:-2.000000 -0.300000:-1.000000
+m roundps_001 be99999abfa66666000000003f0000a8 bf800000c00000000000000000000000 0.500010: 0.000000 0.000000: 0.000000 -1.300000:-2.000000 -0.300000:-1.000000
+r roundps_010 be99999abfa66666000000003f0000a8 80000000bf800000000000003f800000 0.500010: 1.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+m roundps_010 be99999abfa66666000000003f0000a8 80000000bf800000000000003f800000 0.500010: 1.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+r roundps_011 be99999abfa66666000000003f0000a8 80000000bf8000000000000000000000 0.500010: 0.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+m roundps_011 be99999abfa66666000000003f0000a8 80000000bf8000000000000000000000 0.500010: 0.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+r roundps_000 bdcccccdbf8ccccd800000003f333333 80000000bf800000800000003f800000 0.700000: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+m roundps_000 bdcccccdbf8ccccd800000003f333333 80000000bf800000800000003f800000 0.700000: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+r roundps_001 bdcccccdbf8ccccd800000003f333333 bf800000c00000008000000000000000 0.700000: 0.000000 -0.000000:-0.000000 -1.100000:-2.000000 -0.100000:-1.000000
+m roundps_001 bdcccccdbf8ccccd800000003f333333 bf800000c00000008000000000000000 0.700000: 0.000000 -0.000000:-0.000000 -1.100000:-2.000000 -0.100000:-1.000000
+r roundps_010 bdcccccdbf8ccccd800000003f333333 80000000bf800000800000003f800000 0.700000: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+m roundps_010 bdcccccdbf8ccccd800000003f333333 80000000bf800000800000003f800000 0.700000: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+r roundps_011 bdcccccdbf8ccccd800000003f333333 80000000bf8000008000000000000000 0.700000: 0.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+m roundps_011 bdcccccdbf8ccccd800000003f333333 80000000bf8000008000000000000000 0.700000: 0.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+r roundps_000 3dcccccdbf6666667f8000003f666666 00000000bf8000007f8000003f800000 0.900000: 1.000000 inf: inf -0.900000:-1.000000 0.100000: 0.000000
+m roundps_000 3dcccccdbf6666667f8000003f666666 00000000bf8000007f8000003f800000 0.900000: 1.000000 inf: inf -0.900000:-1.000000 0.100000: 0.000000
+r roundps_001 3dcccccdbf6666667f8000003f666666 00000000bf8000007f80000000000000 0.900000: 0.000000 inf: inf -0.900000:-1.000000 0.100000: 0.000000
+m roundps_001 3dcccccdbf6666667f8000003f666666 00000000bf8000007f80000000000000 0.900000: 0.000000 inf: inf -0.900000:-1.000000 0.100000: 0.000000
+r roundps_010 3dcccccdbf6666667f8000003f666666 3f800000800000007f8000003f800000 0.900000: 1.000000 inf: inf -0.900000:-0.000000 0.100000: 1.000000
+m roundps_010 3dcccccdbf6666667f8000003f666666 3f800000800000007f8000003f800000 0.900000: 1.000000 inf: inf -0.900000:-0.000000 0.100000: 1.000000
+r roundps_011 3dcccccdbf6666667f8000003f666666 00000000800000007f80000000000000 0.900000: 0.000000 inf: inf -0.900000:-0.000000 0.100000: 0.000000
+m roundps_011 3dcccccdbf6666667f8000003f666666 00000000800000007f80000000000000 0.900000: 0.000000 inf: inf -0.900000:-0.000000 0.100000: 0.000000
+r roundps_000 3e99999abf333333ff8000003f8ccccd 00000000bf800000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-1.000000 0.300000: 0.000000
+m roundps_000 3e99999abf333333ff8000003f8ccccd 00000000bf800000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-1.000000 0.300000: 0.000000
+r roundps_001 3e99999abf333333ff8000003f8ccccd 00000000bf800000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-1.000000 0.300000: 0.000000
+m roundps_001 3e99999abf333333ff8000003f8ccccd 00000000bf800000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-1.000000 0.300000: 0.000000
+r roundps_010 3e99999abf333333ff8000003f8ccccd 3f80000080000000ff80000040000000 1.100000: 2.000000 -inf: -inf -0.700000:-0.000000 0.300000: 1.000000
+m roundps_010 3e99999abf333333ff8000003f8ccccd 3f80000080000000ff80000040000000 1.100000: 2.000000 -inf: -inf -0.700000:-0.000000 0.300000: 1.000000
+r roundps_011 3e99999abf333333ff8000003f8ccccd 0000000080000000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-0.000000 0.300000: 0.000000
+m roundps_011 3e99999abf333333ff8000003f8ccccd 0000000080000000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-0.000000 0.300000: 0.000000
+r roundps_000 3efffeb0bf0000a8ffc000003fa66666 00000000bf800000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-1.000000 0.499990: 0.000000
+m roundps_000 3efffeb0bf0000a8ffc000003fa66666 00000000bf800000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-1.000000 0.499990: 0.000000
+r roundps_001 3efffeb0bf0000a8ffc000003fa66666 00000000bf800000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-1.000000 0.499990: 0.000000
+m roundps_001 3efffeb0bf0000a8ffc000003fa66666 00000000bf800000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-1.000000 0.499990: 0.000000
+r roundps_010 3efffeb0bf0000a8ffc000003fa66666 3f80000080000000ffc0000040000000 1.300000: 2.000000 nan: nan -0.500010:-0.000000 0.499990: 1.000000
+m roundps_010 3efffeb0bf0000a8ffc000003fa66666 3f80000080000000ffc0000040000000 1.300000: 2.000000 nan: nan -0.500010:-0.000000 0.499990: 1.000000
+r roundps_011 3efffeb0bf0000a8ffc000003fa66666 0000000080000000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-0.000000 0.499990: 0.000000
+m roundps_011 3efffeb0bf0000a8ffc000003fa66666 0000000080000000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-0.000000 0.499990: 0.000000
+r (rm=0) roundsd_1XX ce7d85807031a7870000000000000000 45e800698e5e5ad50000000000000000 0.000000 0.000000
+m (rm=0) roundsd_1XX 56efc6eff999a7570000000000000000 9d6e25ef9723e6140000000000000000 0.000000 0.000000
+r (rm=1) roundsd_1XX 969e4fa82b9f4d710000000000000000 9c1852b7570ef5340000000000000000 0.000000 0.000000
+m (rm=1) roundsd_1XX ead61e19a1d1d5810000000000000000 9c31822c6aaac4de0000000000000000 0.000000 0.000000
+r (rm=2) roundsd_1XX aee22eadf7ba7b320000000000000000 fa04b1ba6b838fc10000000000000000 0.000000 0.000000
+m (rm=2) roundsd_1XX 3e0f7bd0cae67a310000000000000000 13dedbcdf72692870000000000000000 0.000000 0.000000
+r (rm=3) roundsd_1XX f5a901eeb5e20f290000000000000000 410bfdd1a81e08dd0000000000000000 0.000000 0.000000
+m (rm=3) roundsd_1XX 31fcbd74553975c70000000000000000 e1d712331df72e6e0000000000000000 0.000000 0.000000
+r (rm=0) roundsd_1XX 4d54aacc4578eab78000000000000000 4f8e155df03e40e78000000000000000 -0.000000 -0.000000
+m (rm=0) roundsd_1XX a5fdc463222aa8a48000000000000000 e87b05bcbd7e79f38000000000000000 -0.000000 -0.000000
+r (rm=1) roundsd_1XX 944207a687dbec3a8000000000000000 06ecdbbd2143173f8000000000000000 -0.000000 -0.000000
+m (rm=1) roundsd_1XX 787170ff1018f1278000000000000000 062b95cbb71a54778000000000000000 -0.000000 -0.000000
+r (rm=2) roundsd_1XX abd4f9dc5a6cf5158000000000000000 44852d511c8e6c468000000000000000 -0.000000 -0.000000
+m (rm=2) roundsd_1XX 8bb8a0a8016332b08000000000000000 1c46a1bdeb2b9d598000000000000000 -0.000000 -0.000000
+r (rm=3) roundsd_1XX 726960cfa089e4a58000000000000000 eabaed7ac17e215b8000000000000000 -0.000000 -0.000000
+m (rm=3) roundsd_1XX be3236bdd36b49a08000000000000000 0a2c0bf4391234f98000000000000000 -0.000000 -0.000000
+r (rm=0) roundsd_1XX c9611cde37959b4c7ff0000000000000 d8eaf997f07414df7ff0000000000000 inf inf
+m (rm=0) roundsd_1XX f140109e689117567ff0000000000000 b03eb2cf812ffbb87ff0000000000000 inf inf
+r (rm=1) roundsd_1XX 901c0d6900edf86a7ff0000000000000 ee75320989cf26317ff0000000000000 inf inf
+m (rm=1) roundsd_1XX 04420fac9e347c337ff0000000000000 eedb75afa3e0d1f57ff0000000000000 inf inf
+r (rm=2) roundsd_1XX a7fb13d1dcf3dd5d7ff0000000000000 0bbc782f6bef37b17ff0000000000000 inf inf
+m (rm=2) roundsd_1XX d696144656b557957ff0000000000000 a36436f37e8795107ff0000000000000 inf inf
+r (rm=3) roundsd_1XX ee5e0d75a90628877ff0000000000000 111eab69783527c07ff0000000000000 inf inf
+m (rm=3) roundsd_1XX 499efdcc70738adf7ff0000000000000 b138d3fcf484296a7ff0000000000000 inf inf
+r (rm=0) roundsd_1XX 44a4ddb64887ba48fff0000000000000 defcaa188e00d6bdfff0000000000000 -inf -inf
+m (rm=0) roundsd_1XX 3bbaaa9fcccff46efff0000000000000 f6b72d29e3356b63fff0000000000000 -inf -inf
+r (rm=1) roundsd_1XX 8a2d61f398d573fffff0000000000000 54b5579b8fb02408fff0000000000000 -inf -inf
+m (rm=1) roundsd_1XX 8d49fd1e492774a4fff0000000000000 534124da2cfc3c59fff0000000000000 -inf -inf
+r (rm=2) roundsd_1XX a1597a8c7b51330cfff0000000000000 51a9905259a6f002fff0000000000000 -inf -inf
+m (rm=2) roundsd_1XX 20abd5a9c9ddebe1fff0000000000000 a838986faf397caefff0000000000000 -inf -inf
+r (rm=3) roundsd_1XX 678908e2d05ad9cffff0000000000000 b639379ecd411b0afff0000000000000 -inf -inf
+m (rm=3) roundsd_1XX d24011a12a513984fff0000000000000 d5f968494c4b0bc2fff0000000000000 -inf -inf
+r (rm=0) roundsd_1XX bd1ceb54765047a9fff8000000000000 63c42adecbe28681fff8000000000000 nan nan
+m (rm=0) roundsd_1XX 846993654ee23eedfff8000000000000 bae676c8e392c9f3fff8000000000000 nan nan
+r (rm=1) roundsd_1XX 827303424e935cfafff8000000000000 38aa4a7232e80fc6fff8000000000000 nan nan
+m (rm=1) roundsd_1XX 1585395613f0da7cfff8000000000000 375ea14a546f95a3fff8000000000000 nan nan
+r (rm=2) roundsd_1XX 98ed300d3884f720fff8000000000000 144c77bbe4b39739fff8000000000000 nan nan
+m (rm=2) roundsd_1XX 67f5e4d35adced92fff8000000000000 2cc1c8317e415132fff8000000000000 nan nan
+r (rm=3) roundsd_1XX deea52141483f97efff8000000000000 d9099019bfa4fe3bfff8000000000000 nan nan
+m (rm=3) roundsd_1XX 5818743c0305578efff8000000000000 7870ccdd4368dbfffff8000000000000 nan nan
+r (rm=0) roundsd_1XX 33cb48b8c2ee42717ff8000000000000 654277eaa51a242b7ff8000000000000 nan nan
+m (rm=0) roundsd_1XX ca4fc9f2eecbf7d17ff8000000000000 fcca8dad8145146a7ff8000000000000 nan nan
+r (rm=1) roundsd_1XX 79eff3582227b25b7ff8000000000000 9a560b907475e8697ff8000000000000 nan nan
+m (rm=1) roundsd_1XX 9bf8c354fb8fafba7ff8000000000000 9930eb011937dcd47ff8000000000000 nan nan
+r (rm=2) roundsd_1XX 8eb73354148e299b7ff8000000000000 56a52b6b0d162c567ff8000000000000 nan nan
+m (rm=2) roundsd_1XX ac7641c309b05daa7ff8000000000000 2d01c639eb9e139c7ff8000000000000 nan nan
+r (rm=3) roundsd_1XX 5381e90d778287927ff8000000000000 7a90b8d9505cce517ff8000000000000 nan nan
+m (rm=3) roundsd_1XX dd26259efa8fe2ff7ff8000000000000 999efeb6d7db99227ff8000000000000 nan nan
+r (rm=0) roundsd_1XX a8b0f2e22d63ab9fbff4cccccccccccd e676923d1da8b0bbbff0000000000000 -1.300000 -1.000000
+m (rm=0) roundsd_1XX 0e6a4d45ac8b1e1cbff4cccccccccccd bd6572d8bd4d4ec7bff0000000000000 -1.300000 -1.000000
+r (rm=1) roundsd_1XX 6da1313314927722bff4cccccccccccd 7ab79af45459b0f3c000000000000000 -1.300000 -2.000000
+m (rm=1) roundsd_1XX 1fa19b180004f15ebff4cccccccccccd 78b804fd7d5511eac000000000000000 -1.300000 -2.000000
+r (rm=2) roundsd_1XX 81b685610d6ec97cbff4cccccccccccd 15b4ad60d4cfaf59bff0000000000000 -1.300000 -1.000000
+m (rm=2) roundsd_1XX f02ced78d65b3b27bff4cccccccccccd acf79288f652c4ebbff0000000000000 -1.300000 -1.000000
+r (rm=3) roundsd_1XX c64fcecbf857820cbff4cccccccccccd 99ccaee07f6b8d4ebff0000000000000 -1.300000 -1.000000
+m (rm=3) roundsd_1XX 606a24c50eefdbd6bff4cccccccccccd 3781fdd60aa4452bbff0000000000000 -1.300000 -1.000000
+r (rm=0) roundsd_1XX 1acaebd2b5ae8232bff199999999999a e4607cd5338c2a31bff0000000000000 -1.100000 -1.000000
+m (rm=0) roundsd_1XX 51bb205d8820b3ccbff199999999999a fbb6264997ac760abff0000000000000 -1.100000 -1.000000
+r (rm=1) roundsd_1XX 5f89bdd524d2a94fbff199999999999a d7cff69ed2926562c000000000000000 -1.100000 -2.000000
+m (rm=1) roundsd_1XX a180c0a3244fa168bff199999999999a d6f7eb407ec935e6c000000000000000 -1.100000 -2.000000
+r (rm=2) roundsd_1XX 73ec25342423d7c2bff199999999999a 5379fe9b3ade2042bff0000000000000 -1.100000 -1.000000
+m (rm=2) roundsd_1XX 3118e6f4c1db870abff199999999999a a9a32c1c9f5c6321bff0000000000000 -1.100000 -1.000000
+r (rm=3) roundsd_1XX 3752014f9702ececbff199999999999a 36bf722d4ccf3930bff0000000000000 -1.100000 -1.000000
+m (rm=3) roundsd_1XX e1e470b241244313bff199999999999a 541acb3cdac4e01bbff0000000000000 -1.100000 -1.000000
+r (rm=0) roundsd_1XX 8b1b32885bcec72cbfeccccccccccccd 610033b3e7c6928dbff0000000000000 -0.900000 -1.000000
+m (rm=0) roundsd_1XX 9143403c828bb6e2bfeccccccccccccd b7bda7000f618b32bff0000000000000 -0.900000 -1.000000
+r (rm=1) roundsd_1XX 4fa8973c52e84ae2bfeccccccccccccd b39d218eed2209b8bff0000000000000 -0.900000 -1.000000
+m (rm=1) roundsd_1XX 219534f36570c0d8bfeccccccccccccd b2eb9fc91e9346c8bff0000000000000 -0.900000 -1.000000
+r (rm=2) roundsd_1XX 625812cd5aaf536fbfeccccccccccccd 0ef41c1d3d437f118000000000000000 -0.900000 -0.000000
+m (rm=2) roundsd_1XX 703b2d36cb314054bfeccccccccccccd 240595f6e6bbef3d8000000000000000 -0.900000 -0.000000
+r (rm=3) roundsd_1XX a68b829a5483c332bfeccccccccccccd 516804c0b68ad4f98000000000000000 -0.900000 -0.000000
+m (rm=3) roundsd_1XX 60940b65923018b6bfeccccccccccccd ef6967e7493968f08000000000000000 -0.900000 -0.000000
+r (rm=0) roundsd_1XX f9a2c60320c57a8bbfe6666666666666 5b56b9d83a56e7cfbff0000000000000 -0.700000 -1.000000
+m (rm=0) roundsd_1XX cf00aee19acd265fbfe6666666666666 f17af6fd256c8f41bff0000000000000 -0.700000 -1.000000
+r (rm=1) roundsd_1XX 3dfcbf699dd458dbbfe6666666666666 0d201ac4a7079af3bff0000000000000 -0.700000 -1.000000
+m (rm=1) roundsd_1XX 9ee0f609c5664caebfe6666666666666 0b9522975bb44591bff0000000000000 -0.700000 -1.000000
+r (rm=2) roundsd_1XX 50f94e2cad103d82bfe6666666666666 482509e4defeccc68000000000000000 -0.700000 -0.000000
+m (rm=2) roundsd_1XX ae93c33ef25e6803bfe6666666666666 1e1ccb16cb716a3f8000000000000000 -0.700000 -0.000000
+r (rm=3) roundsd_1XX 13fa51aa2fda09debfe6666666666666 eac66499bf9a5ca78000000000000000 -0.700000 -0.000000
+m (rm=3) roundsd_1XX dd7af4de00125bbfbfe6666666666666 086fd0d95504deab8000000000000000 -0.700000 -0.000000
+r (rm=0) roundsd_1XX 665ea94502919b51bfe00014f8b588e3 d4620c422a3c2bf7bff0000000000000 -0.500010 -1.000000
+m (rm=0) roundsd_1XX 0bf46a4cd0e40541bfe00014f8b588e3 a9ed1340d9cc8136bff0000000000000 -0.500010 -1.000000
+r (rm=1) roundsd_1XX 2986355d0796d53abfe00014f8b588e3 e55ae13fff421a15bff0000000000000 -0.500010 -1.000000
+m (rm=1) roundsd_1XX 1a6106e5433346eabfe00014f8b588e3 e3f672ac372a323fbff0000000000000 -0.500010 -1.000000
+r (rm=2) roundsd_1XX 3cd1d7511e4895fabfe00014f8b588e3 ff0dc3f11d0f07618000000000000000 -0.500010 -0.000000
+m (rm=2) roundsd_1XX e922a60b3760fe18bfe00014f8b588e3 95eacf7c4e7dd3268000000000000000 -0.500010 -0.000000
+r (rm=3) roundsd_1XX 7e9f6e812807bcf0bfe00014f8b588e3 01db92b86600d33c8000000000000000 -0.500010 -0.000000
+m (rm=3) roundsd_1XX 57962b1e8dca0d2ebfe00014f8b588e3 9e2a08100025424c8000000000000000 -0.500010 -0.000000
+r (rm=0) roundsd_1XX d151d94d02342a7dbfdfffd60e94ee39 ca242ef2b8785d058000000000000000 -0.499990 -0.000000
+m (rm=0) roundsd_1XX 461d757c25d15289bfdfffd60e94ee39 e015fec92b8360118000000000000000 -0.499990 -0.000000
+r (rm=1) roundsd_1XX 1346f9168f2ebf00bfdfffd60e94ee39 3b497601f4d4871cbff0000000000000 -0.499990 -1.000000
+m (rm=1) roundsd_1XX 94186387ded6ae8bbfdfffd60e94ee39 390c9106b0f60dd3bff0000000000000 -0.499990 -1.000000
+r (rm=2) roundsd_1XX 25dfaf3cae565bd9bfdfffd60e94ee39 34aa4b45fb7630e28000000000000000 -0.499990 -0.000000
+m (rm=2) roundsd_1XX 22e6d79f9a380294bfdfffd60e94ee39 8a6ea1286fdf29f48000000000000000 -0.499990 -0.000000
+r (rm=3) roundsd_1XX e77bd91d3e0ade68bfdfffd60e94ee39 96a58e1cabbd37b68000000000000000 -0.499990 -0.000000
+m (rm=3) roundsd_1XX d0e8b02337582c03bfdfffd60e94ee39 b39b0e8e489d94d38000000000000000 -0.499990 -0.000000
+r (rm=0) roundsd_1XX 397a581b21ad280ebfd3333333333333 3e9c1de9e4097df98000000000000000 -0.300000 -0.000000
+m (rm=0) roundsd_1XX 7e7dcd7397950d38bfd3333333333333 94f4b7981b902ed18000000000000000 -0.300000 -0.000000
+r (rm=1) roundsd_1XX fb3c0b96359c182bbfd3333333333333 0fefd90988bbe20abff0000000000000 -0.300000 -1.000000
+m (rm=1) roundsd_1XX 0c050ff0984f8593bfd3333333333333 0dd87ea7c818d74dbff0000000000000 -0.300000 -1.000000
+r (rm=2) roundsd_1XX 0d22d4ed5b398f1dbfd3333333333333 e8fda2de763346498000000000000000 -0.300000 -0.000000
+m (rm=2) roundsd_1XX 5ae156f91be77475bfd3333333333333 fda8411a2e966ea88000000000000000 -0.300000 -0.000000
+r (rm=3) roundsd_1XX 4e8c928073e36e46bfd3333333333333 a82658c78dcf89178000000000000000 -0.300000 -0.000000
+m (rm=3) roundsd_1XX 477082ee00bcb93dbfd3333333333333 46c3e1522f6ad4418000000000000000 -0.300000 -0.000000
+r (rm=0) roundsd_1XX a0d924af5dfb9306bfb999999999999a 31cada25aff18bd38000000000000000 -0.100000 -0.000000
+m (rm=0) roundsd_1XX b4127330272e364cbfb999999999999a c6893eada9f3ea788000000000000000 -0.100000 -0.000000
+r (rm=1) roundsd_1XX e1696cdbf9e0dfbcbfb999999999999a 614a0a57baf92cddbff0000000000000 -0.100000 -1.000000
+m (rm=1) roundsd_1XX 8228091e709ec901bfb999999999999a 5e5b388e7d918eaebff0000000000000 -0.100000 -1.000000
+r (rm=2) roundsd_1XX f29c486427f331c8bfb999999999999a 1906c6bd8f464b968000000000000000 -0.100000 -0.000000
+m (rm=2) roundsd_1XX 8f112418ba6b53bdbfb999999999999a ee98af528ba4a1428000000000000000 -0.100000 -0.000000
+r (rm=3) roundsd_1XX b3d399a8c6936b8bbfb999999999999a 395cf0b80e38ca5d8000000000000000 -0.100000 -0.000000
+m (rm=3) roundsd_1XX bc2ea37fe7f6b5debfb999999999999a 56a0835bb38d03948000000000000000 -0.100000 -0.000000
+r (rm=0) roundsd_1XX 046d3f09b7206c643fb999999999999a a1af66a7172f87930000000000000000 0.100000 0.000000
+m (rm=0) roundsd_1XX e9de68b2d59dcdc63fb999999999999a 76d49408d5ab93050000000000000000 0.100000 0.000000
+r (rm=1) roundsd_1XX c5cb1ae7dbfa13b33fb999999999999a 315c09eb8a8c63960000000000000000 0.100000 0.000000
+m (rm=1) roundsd_1XX f681511265c37bd53fb999999999999a 2e93c1bad15f33f40000000000000000 0.100000 0.000000
+r (rm=2) roundsd_1XX d64c09a1108241d93fb999999999999a c9c5b9e346af3ec93ff0000000000000 0.100000 1.000000
+m (rm=2) roundsd_1XX c2783ffe77c5a16a3fb999999999999a 5e3eebd08608c1c13ff0000000000000 0.100000 1.000000
+r (rm=3) roundsd_1XX 1650ee973718d7353fb999999999999a 484955ef2df6f8890000000000000000 0.100000 0.000000
+m (rm=3) roundsd_1XX 2f2212d6eb051ee53fb999999999999a e533f3abd6061fcd0000000000000000 0.100000 0.000000
+r (rm=0) roundsd_1XX 6738a729301ab3273fd3333333333333 9049bf701dc371390000000000000000 0.300000 0.000000
+m (rm=0) roundsd_1XX 1bdfaafba1e3d1a73fd3333333333333 a4d5b7aa9fba2b770000000000000000 0.300000 0.000000
+r (rm=1) roundsd_1XX a76316b8dbeab6103fd3333333333333 7f24d6c5f77689360000000000000000 0.300000 0.000000
+m (rm=1) roundsd_1XX 6710e7cc79be9c0f3fd3333333333333 7c81182dc283c6200000000000000000 0.300000 0.000000
+r (rm=2) roundsd_1XX b73119a317e8c04f3fd3333333333333 f63a794e9b6e1fe23ff0000000000000 0.300000 1.000000
+m (rm=2) roundsd_1XX f414a8aa52f65d7d3fd3333333333333 4b99f6941fc2d0273ff0000000000000 0.300000 1.000000
+r (rm=3) roundsd_1XX 7803914bc673b0453fd3333333333333 d5ec896ce90b159c0000000000000000 0.300000 0.000000
+m (rm=3) roundsd_1XX a04ccff40eebf5523fd3333333333333 f27d304096d529ec0000000000000000 0.300000 0.000000
+r (rm=0) roundsd_1XX c8395e0fc6eb68513fdfffd60e94ee39 fc99e77ec1ad49c50000000000000000 0.499990 0.000000
+m (rm=0) roundsd_1XX 4b163a0a8bfe44ed3fdfffd60e94ee39 518ba891071fb1d00000000000000000 0.499990 0.000000
+r (rm=1) roundsd_1XX 87316050f8b1c6d33fdfffd60e94ee39 4ba171e403b59cbb0000000000000000 0.499990 0.000000
+m (rm=1) roundsd_1XX d7d5ca4caa8e2aaf3fdfffd60e94ee39 47263ce552fd47320000000000000000 0.499990 0.000000
+r (rm=2) roundsd_1XX 974d766c3d24ac2c3fdfffd60e94ee39 a26507ff8f83eee13ff0000000000000 0.499990 1.000000
+m (rm=2) roundsd_1XX 23e65f1b4bfc87f73fdfffd60e94ee39 b6abce9e56d1cd733ff0000000000000 0.499990 1.000000
+r (rm=3) roundsd_1XX d7ed82c673a4f8bb3fdfffd60e94ee39 e0448b2f44751f940000000000000000 0.499990 0.000000
+m (rm=3) roundsd_1XX 0eabd9d74ea73a253fdfffd60e94ee39 7c7c3c1cf5fb21f20000000000000000 0.499990 0.000000
+r (rm=0) roundsd_1XX 266f62bb7b928be03fe00014f8b588e3 e79fdcd204ed0f373ff0000000000000 0.500010 1.000000
+m (rm=0) roundsd_1XX 7a8418df93ef259a3fe00014f8b588e3 7bf867be0dd9240f3ff0000000000000 0.500010 1.000000
+r (rm=1) roundsd_1XX 6535f8ad344d45fc3fe00014f8b588e3 95d5d94aad4b9e270000000000000000 0.500010 0.000000
+m (rm=1) roundsd_1XX 45d0fc93fa3526b53fe00014f8b588e3 91802fe47fceb72b0000000000000000 0.500010 0.000000
+r (rm=2) roundsd_1XX 759f22fb8035066e3fe00014f8b588e3 cb4664f720eeabc63ff0000000000000 0.500010 1.000000
+m (rm=2) roundsd_1XX 50ef655363d81fd63fe00014f8b588e3 9f7374ee2b37b8a53ff0000000000000 0.500010 1.000000
+r (rm=3) roundsd_1XX 340cc1063eabad973fe00014f8b588e3 69535b373d3618730000000000000000 0.500010 0.000000
+m (rm=3) roundsd_1XX 7b413280ad39ee5e3fe00014f8b588e3 8531163df17607dd0000000000000000 0.500010 0.000000
+r (rm=0) roundsd_1XX 83dcb52d4d0e1cd63fe6666666666666 4f5b9f6de483c38f3ff0000000000000 0.700000 1.000000
+m (rm=0) roundsd_1XX a6274579b9b774ac3fe6666666666666 231bf431b1ea86343ff0000000000000 0.700000 1.000000
+r (rm=1) roundsd_1XX 4270ded18ebf318b3fe6666666666666 5dbe10f6f5368d780000000000000000 0.700000 0.000000
+m (rm=1) roundsd_1XX b1017c9f68b291203fe6666666666666 5990f0284bf414090000000000000000 0.700000 0.000000
+r (rm=2) roundsd_1XX 50271b50e11dce173fe6666666666666 73dd8e344faf56913ff0000000000000 0.700000 1.000000
+m (rm=2) roundsd_1XX 7c2db851988b241b3fe6666666666666 06f1e8859ef390bc3ff0000000000000 0.700000 1.000000
+r (rm=3) roundsd_1XX 8f614e0d2688d1d93fe6666666666666 7017f986d44cfe370000000000000000 0.700000 0.000000
+m (rm=3) roundsd_1XX e60dd9ef2aa10ffd3fe6666666666666 0c9dbda58c47dcae0000000000000000 0.700000 0.000000
+r (rm=0) roundsd_1XX dd7f55653d611b323feccccccccccccd 36cd314d626f65cd3ff0000000000000 0.900000 1.000000
+m (rm=0) roundsd_1XX d001bfdafd5431243feccccccccccccd 49f44feaf351d63e3ff0000000000000 0.900000 1.000000
+r (rm=1) roundsd_1XX 1ce012ba06078c803feccccccccccccd a35e15e8da786ab00000000000000000 0.900000 0.000000
+m (rm=1) roundsd_1XX 1b684a71f30569f23feccccccccccccd 9e577eb3b4705fcd0000000000000000 0.900000 0.000000
+r (rm=2) roundsd_1XX 2ae4636b61da04263feccccccccccccd 982a87b71cc6ef423ff0000000000000 0.900000 1.000000
+m (rm=2) roundsd_1XX a5a25915eb1398c73feccccccccccccd ec252a61af0457ba3ff0000000000000 0.900000 1.000000
+r (rm=3) roundsd_1XX e8ec29d92d3b62813feccccccccccccd f592651b08b9d2e20000000000000000 0.900000 0.000000
+m (rm=3) roundsd_1XX 4f0fce24c4df9e013feccccccccccccd 11be3353c46e9e650000000000000000 0.900000 0.000000
+r (rm=0) roundsd_1XX 365744634c8988f33ff199999999999a 9af590737eb1f5f03ff0000000000000 1.100000 1.000000
+m (rm=0) roundsd_1XX f910870160c85b033ff199999999999a ed8379e9d30e132f3ff0000000000000 1.100000 1.000000
+r (rm=1) roundsd_1XX f48694699c2554dc3ff199999999999a 67b3e8205e0f36cd3ff0000000000000 1.100000 1.000000
+m (rm=1) roundsd_1XX 830565099d2eaf2a3ff199999999999a 62d3db84bc4298773ff0000000000000 1.100000 1.000000
+r (rm=2) roundsd_1XX 01d8f84cfe6ea89a3ff199999999999a 3c2d4d81883376d94000000000000000 1.100000 2.000000
+m (rm=2) roundsd_1XX cc4c499e5c717ad83ff199999999999a 4f0e3a835e6c0c9e4000000000000000 1.100000 2.000000
+r (rm=3) roundsd_1XX 3fad526b52c4628f3ff199999999999a f8c29ff6db7b95723ff0000000000000 1.100000 1.000000
+m (rm=3) roundsd_1XX b64711207df29c6c3ff199999999999a 939577469bec4e033ff0000000000000 1.100000 1.000000
+r (rm=0) roundsd_1XX 8c6680277888631b3ff4cccccccccccd 7cd3bee0394973fa3ff0000000000000 1.300000 1.000000
+m (rm=0) roundsd_1XX 1f569dede011f4473ff4cccccccccccd 10c8702e51203f063ff0000000000000 1.300000 1.000000
+r (rm=1) roundsd_1XX ca6264df50198b9d3ff4cccccccccccd a9bf899e80fdefd13ff0000000000000 1.300000 1.000000
+m (rm=1) roundsd_1XX e8d7cf68642d64c83ff4cccccccccccd a405069a616abf083ff0000000000000 1.300000 1.000000
+r (rm=2) roundsd_1XX d702dcf3b9d8ba753ff4cccccccccccd 5de6e29091f5eb564000000000000000 1.300000 2.000000
+m (rm=2) roundsd_1XX f12d86eeeba6ca4f3ff4cccccccccccd 30ae19ebab2aae684000000000000000 1.300000 2.000000
+r (rm=3) roundsd_1XX 94a5c9c49523d0043ff4cccccccccccd 79a9a7174c9445e93ff0000000000000 1.300000 1.000000
+m (rm=3) roundsd_1XX 1bb5a1e153dc073d3ff4cccccccccccd 942388800fbfec863ff0000000000000 1.300000 1.000000
+r (rm=0) roundss_1XX e1ab0bb1c25daca8dec2a64b00000000 dd67b9929137dfea19fbaf3a00000000 0.000000 0.000000
+m (rm=0) roundss_1XX 43d102a07e30fbf124f93e4c00000000 b0c235b96d8959c3ace6342e00000000 0.000000 0.000000
+r (rm=1) roundss_1XX 9e74821a22e330c43c4a50ed00000000 6981f8613f4097ba3f1032f800000000 0.000000 0.000000
+m (rm=1) roundss_1XX 4ce0878c4a0186cc0181591b00000000 64eefef7a5e9d47ead46248400000000 0.000000 0.000000
+r (rm=2) roundss_1XX ab610d6093173ab64f69d3c000000000 fc5544e5380e4eb9d25486be00000000 0.000000 0.000000
+m (rm=2) roundss_1XX 1543110498b0882d01d03cca00000000 8f04c599963e3f178906d49200000000 0.000000 0.000000
+r (rm=3) roundss_1XX e7d28ee2f658abdef5800f2400000000 78467d7e5b02e445b0288bec00000000 0.000000 0.000000
+m (rm=3) roundss_1XX 7d598068489ce0740646c8b900000000 136668ff22e878ef228526b900000000 0.000000 0.000000
+r (rm=0) roundss_1XX 3425e3012b07639c0feee47780000000 bbb1828a877b39c0baea21e380000000 -0.000000 -0.000000
+m (rm=0) roundss_1XX 6683b4193a267002ee44dd4980000000 ce73c88a274861655624f85880000000 -0.000000 -0.000000
+r (rm=1) roundss_1XX 70bdee1c118342517d13311b80000000 a7f8356b9dda2c8ad0fd270280000000 -0.000000 -0.000000
+m (rm=1) roundss_1XX ae1f8d764eac16369a295bda80000000 a18cc59986bdd8da06422bcf80000000 -0.000000 -0.000000
+r (rm=2) roundss_1XX 7cf78d938a2d285c1f50d77080000000 1a7a74817d7d9f02d2be7faa80000000 -0.000000 -0.000000
+m (rm=2) roundss_1XX 3690eadf6390b370ea5522ca80000000 6c103f8d1fa7bead123f9f7f80000000 -0.000000 -0.000000
+r (rm=3) roundss_1XX 3835a1c77564f51ed504b7d580000000 f598212a07c77088a08f073a80000000 -0.000000 -0.000000
+m (rm=3) roundss_1XX de33adb55b322811be29117b80000000 0f5f16c5d267f23e597c34c780000000 -0.000000 -0.000000
+r (rm=0) roundss_1XX 84d60a17b18888f67f90afaa7f800000 18b11ac91b15807c1ad0a1127f800000 inf inf
+m (rm=0) roundss_1XX 866ab45814f15378f5050a4d7f800000 6ada29a17f5c56eebd58ca077f800000 inf inf
+r (rm=1) roundss_1XX 403ba8e31ff9c344fc53a0507f800000 632640bb99c9b03f1fe02b937f800000 inf inf
+m (rm=1) roundss_1XX 0e94e1266f2d15067147eb9f7f800000 5de05a8206e7c91c1c3340a07f800000 inf inf
+r (rm=2) roundss_1XX 4cc35b8c9f1884692ead69267f800000 b55673626142de31911f861c7f800000 inf inf
+m (rm=2) roundss_1XX 551212814c474d1a105196d17f800000 c8d287c746672a29586e78f27f800000 inf inf
+r (rm=3) roundss_1XX 87ce02711245acc4f3ffec8c7f800000 f0a1931d52e1ebb04eed920d7f800000 inf inf
+m (rm=3) roundss_1XX 3d4328c98b9edd14b383e9437f800000 8a0f91d1213c5b744f68505b7f800000 inf inf
+r (rm=0) roundss_1XX d3bd7ff355de1bb52ca808e3ff800000 f2677f4d4d05b61e37ab2fc7ff800000 -inf -inf
+m (rm=0) roundss_1XX a487035c0c92a3543b3bc556ff800000 84f758fe75c73a5de282a93dff800000 -inf -inf
+r (rm=1) roundss_1XX 0eefb0714b45b19dba089c8aff800000 9d091951330f21db2cb83caaff800000 -inf -inf
+m (rm=1) roundss_1XX 6c3f829caf84813b86db0a6aff800000 97eabcb12367a844f11b64f8ff800000 -inf -inf
+r (rm=2) roundss_1XX 19c4764bd3da4edb7b8089e1ff800000 cfe73f89e25d0b460d759b14ff800000 -inf -inf
+m (rm=2) roundss_1XX 73ca87e953d3552975c397ddff800000 a14a9d470b7d858a5c935febff800000 -inf -inf
+r (rm=3) roundss_1XX d49db1e2ccfcd2d04f6fb049ff800000 695fd2563b5253bfba412a67ff800000 -inf -inf
+m (rm=3) roundss_1XX 9a89f0a2dae0007de7524e11ff800000 8374db220d68b18f034b7a76ff800000 -inf -inf
+r (rm=0) roundss_1XX 1fda4195180b1cdb1836ef22ffc00000 4bd3b3171e4bdaa6137dcb02ffc00000 nan nan
+m (rm=0) roundss_1XX c1db9f27220a6297bee80e66ffc00000 1dca55a109880cb2c5a297f9ffc00000 nan nan
+r (rm=1) roundss_1XX dad906c495680e5cb53427caffc00000 55a3c02d6aaa815cf7875c46ffc00000 nan nan
+m (rm=1) roundss_1XX c72072d90cb15bd7d8e6b63bffc00000 4eabed25de3e755384f995d5ffc00000 nan nan
+r (rm=2) roundss_1XX e5fce0d0247286b405c938a3ffc00000 662edaf701ce264148c2be92ffc00000 nan nan
+m (rm=2) roundss_1XX 8eb94a177836cb9e17ab27f0ffc00000 f877810d6ee9ced21eae5369ffc00000 nan nan
+r (rm=3) roundss_1XX 1fa2ae18a5896542ea56010dffc00000 60d4e0d5c218aab3e48bd147ffc00000 nan nan
+m (rm=3) roundss_1XX f505074146f8924c599741e5ffc00000 fa8ff3ba97e9f5907524b316ffc00000 nan nan
+r (rm=0) roundss_1XX 6a2c52fdf80e8b67423a64667fc00000 21f5b4288ce7ec14ac4475c47fc00000 nan nan
+m (rm=0) roundss_1XX db6489b856578f3f7f0be47b7fc00000 3352218b3b9fcbec67b8933b7fc00000 nan nan
+r (rm=1) roundss_1XX a4f9aadefd60d881eed53f107fc00000 8bf2354f409ccec4804c89697fc00000 nan nan
+m (rm=1) roundss_1XX 2137b0db88b4a3d96966f0127fc00000 8421ece0386a3047d5ccd4397fc00000 nan nan
+r (rm=2) roundss_1XX ae6a971b94df2cf3ce88746b7fc00000 7c2b42aabe952f224004ef967fc00000 nan nan
+m (rm=2) roundss_1XX a7dd5c0abc6eaf7af70845087fc00000 cd5b33196faa04009fbf566e7fc00000 nan nan
+r (rm=3) roundss_1XX 68def9159cec671ac2b2e1d67fc00000 d5febc9ae635ee8ecccb85ac7fc00000 nan nan
+m (rm=3) roundss_1XX 4db76ca6d1e591800952c3bf7fc00000 ee61d897c0c02777a4f2f93d7fc00000 nan nan
+r (rm=0) roundss_1XX b2b5b02bf6e66958a9b467b1bfa66666 76cd837e98d9ec6804012d0bbf800000 -1.300000 -1.000000
+m (rm=0) roundss_1XX f324c10ea87a2a4e7fa44997bfa66666 c791baba0b0b790dc6c49d03bf800000 -1.300000 -1.000000
+r (rm=1) roundss_1XX 6c509cbd832e110d65ede65dbfa66666 3ef877b6b4e30911c707c511c0000000 -1.300000 -2.000000
+m (rm=1) roundss_1XX 79843ca3228d5a41385cb9efbfa66666 384db8e02fecda21e4962122c0000000 -1.300000 -2.000000
+r (rm=2) roundss_1XX 760e9d2c21234097d4bd3e39bfa66666 0fde78a31ab225e9f73c2e21bf800000 -1.300000 -1.000000
+m (rm=2) roundss_1XX bf38bbc41d7c01bb16dcf127bfa66666 20f5b46b0ec22914ddc767f9bf800000 -1.300000 -1.000000
+r (rm=3) roundss_1XX b04f92d7b125d758d8854ea5bfa66666 c8df66a5a9a7204e72014898bf800000 -1.300000 -1.000000
+m (rm=3) roundss_1XX a49f1fd17aa9fe1bf784d29fbfa66666 61e88cbb86ed474592b74de9bf800000 -1.300000 -1.000000
+r (rm=0) roundss_1XX f9745d1f1395b4b04fa4f802bf8ccccd 485c211a4221daa219b5f3d8bf800000 -1.100000 -1.000000
+m (rm=0) roundss_1XX 0a19482b197433c2bcb23cb8bf8ccccd d986212f79ce1514e3c6b451bf800000 -1.100000 -1.000000
+r (rm=1) roundss_1XX 32dcdc6327d2b8fe1a7a1bafbf8ccccd 70b48864c6803345ccb80e40c0000000 -1.100000 -2.000000
+m (rm=1) roundss_1XX cf071531d93b7e0f45c80fd2bf8ccccd 6a305327c5c471e1b0557c91c0000000 -1.100000 -2.000000
+r (rm=2) roundss_1XX 3ce7f003cc3cc2a21968960dbf8ccccd 21477de313250a966b6b7b31bf800000 -1.100000 -1.000000
+m (rm=2) roundss_1XX d4c868449c61c06272262b4bbf8ccccd f24502044b303c0dd9c4850abf800000 -1.100000 -1.000000
+r (rm=3) roundss_1XX f5f67960e434b4fc2ccd4a7abf8ccccd 3976def50a6f41f5d62d180abf800000 -1.100000 -1.000000
+m (rm=3) roundss_1XX f9bd20c34043d91c232b6f85bf8ccccd 52250d24eb7156f83e71af1bbf800000 -1.100000 -1.000000
+r (rm=0) roundss_1XX 3e6857d94d196d6d330a1759bf666666 99a08cfd8bbfb6c2ed5ec72bbf800000 -0.900000 -1.000000
+m (rm=0) roundss_1XX 1e451c0ea743aa9c3837bde0bf666666 693156ea85e79e01bfbfda25bf800000 -0.900000 -1.000000
+r (rm=1) roundss_1XX f69e6acee84ccc550d7edd07bf666666 2025675875744a5e8f5f66f5bf800000 -0.900000 -1.000000
+m (rm=1) roundss_1XX 23c03d85afc0104390abf3bbbf666666 19c8bcb4f8f2f6883b0be687bf800000 -0.900000 -1.000000
+r (rm=2) roundss_1XX fff792a0962cb2129c897ce6bf666666 b0664f68aaeedd299e8fd6c780000000 -0.900000 -0.000000
+m (rm=2) roundss_1XX e78f6389391bee700ce6f376bf666666 414b1ee226f33ced93b7b2a180000000 -0.900000 -0.000000
+r (rm=3) roundss_1XX 38d3aeae35190007be8cd456bf666666 28c2248c088e4f81f84ff70180000000 -0.900000 -0.000000
+m (rm=3) roundss_1XX 4c116e7a25b323838d489b72bf666666 c0185dd4ed4a5291a82220d480000000 -0.900000 -0.000000
+r (rm=0) roundss_1XX 8093a059a674949154e6c4b5bf333333 679ac62571b380c87efda904bf800000 -0.700000 -1.000000
+m (rm=0) roundss_1XX 30a63eb753e88eddf132cc0dbf333333 789259eb2f5616d358ad0e7fbf800000 -0.700000 -1.000000
+r (rm=1) roundss_1XX b8964600c89c4f123ef72e66bf333333 4e4d1492c3bd505e10fccb2fbf800000 -0.700000 -1.000000
+m (rm=1) roundss_1XX 75afb3a0a21b11dd190366aabf333333 4716f286ca77691484b75d02bf800000 -0.700000 -1.000000
+r (rm=2) roundss_1XX c13d81037df210e95c20f0c6bf333333 bd3bf033df0d9ea28ea93fe380000000 -0.700000 -0.000000
+m (rm=2) roundss_1XX f98bad95f4ab8ae3e51b49a6bf333333 0e0608069f0d2bb30ca0edbe80000000 -0.700000 -0.000000
+r (rm=3) roundss_1XX 79e631c3a4d4b9778ec0eb37bf333333 95c53869a5024cf4d866e37f80000000 -0.700000 -0.000000
+m (rm=3) roundss_1XX 9d9b0bf727f9da5035db5464bf333333 adc27bca8e793c10cfc99e1280000000 -0.700000 -0.000000
+r (rm=0) roundss_1XX c1f4369f1ca5291bb438ff18bf0000a8 b34acd93f5fd38b4ce939863bf800000 -0.500010 -1.000000
+m (rm=0) roundss_1XX 413eaf251d64e183e8a36941bf0000a8 04a92a32771a7c8caf914f5fbf800000 -0.500010 -1.000000
+r (rm=1) roundss_1XX 79c470f7c6c23f35aee70ccabf0000a8 fa2a8f12af5d43434f8f3ff0bf800000 -0.500010 -1.000000
+m (rm=1) roundss_1XX c4d47780b44c7fdde0d1669fbf0000a8 f31bf79f3951ca868b58e204bf800000 -0.500010 -1.000000
+r (rm=2) roundss_1XX 80b8bf2c828ddd265b2df2acbf0000a8 49c65e45b2824d013dbab68580000000 -0.500010 -0.000000
+m (rm=2) roundss_1XX 08be4467cd1294bcfbc72cddbf0000a8 5978c070b67d085f427f366180000000 -0.500010 -0.000000
+r (rm=3) roundss_1XX b830029d3065e14d9c6b911ebf0000a8 7f7d1a8ce0cd364c7674de8380000000 -0.500010 -0.000000
+m (rm=3) roundss_1XX ec5bf63a4815ff831be59c5cbf0000a8 18216605ccfe1476b5652ad780000000 -0.500010 -0.000000
+r (rm=0) roundss_1XX ff8a1babb0ab2c0a5200c881befffeb0 7eb0a248179dde86db1e964880000000 -0.499990 -0.000000
+m (rm=0) roundss_1XX 4f0b6d5a05b5a28f1e89947bbefffeb0 0e75cabf5d35cf2bc46b9fc580000000 -0.499990 -0.000000
+r (rm=1) roundss_1XX 3728e8b4e2be9ebe5b4d7934befffeb0 24bed8d83952250f4c18c037bf800000 -0.499990 -1.000000
+m (rm=1) roundss_1XX 122f8926e4535b42e515f49abefffeb0 1cd5cafd47811ade4ff0758bbf800000 -0.499990 -1.000000
+r (rm=2) roundss_1XX 3e6a4a1ba6ff17c898b08298befffeb0 52079a9c244dea46a9c03bad80000000 -0.499990 -0.000000
+m (rm=2) roundss_1XX 152629ffc44e0cfc50e99e1abefffeb0 22a046206b43d2f036548c8a80000000 -0.499990 -0.000000
+r (rm=3) roundss_1XX f5af213ddbcd7689e98cc40cbefffeb0 e8eccaf5b9ed0f8bd278e60c80000000 -0.499990 -0.000000
+m (rm=3) roundss_1XX 38512f438707931c3e64715abefffeb0 00362087a9d9dac159f8c42180000000 -0.499990 -0.000000
+r (rm=0) roundss_1XX 3c574d7c63889d602d3e20f0be99999a c6cc4642d893723ea7a0a2b480000000 -0.300000 -0.000000
+m (rm=0) roundss_1XX 5b0e79550bdcd10291e64cbabe99999a 96f83792e1a611b0983bfdb080000000 -0.300000 -0.000000
+r (rm=1) roundss_1XX f3c3ae381c906aad462873a4be99999a cc07efe3609ef4c007965003bf800000 -0.300000 -1.000000
+m (rm=1) roundss_1XX 5ec0e8923130a60e28d0119bbe99999a c4456aa2f207571dd27e1798bf800000 -0.300000 -1.000000
+r (rm=2) roundss_1XX f95224d0e746bfd112a9a089be99999a dafea539336e7571d4bdce5b80000000 -0.300000 -0.000000
+m (rm=2) roundss_1XX 21c45c5cd960f1a1e2819e5cbe99999a 6a7e9b16be5e8b68e81ff13980000000 -0.300000 -0.000000
+r (rm=3) roundss_1XX 30648ea4a40a7a2b732286ffbe99999a cf1048a42f64d5afec72fd1c80000000 -0.300000 -0.000000
+m (rm=3) roundss_1XX 837cb613e3ce941aa059d45ebe99999a 6702a84e230b8ff2bb816cf180000000 -0.300000 -0.000000
+r (rm=0) roundss_1XX 765ace14333a7c1b47f20565bdcccccd 8d9eb78236dff4dc3017bca580000000 -0.100000 -0.000000
+m (rm=0) roundss_1XX 6648d3152fda6eda42b99300bdcccccd 9c3172ab036c411a2901692280000000 -0.100000 -0.000000
+r (rm=1) roundss_1XX ad93c2817438a5026f7afc1bbdcccccd f207d435263fb158800bed56bf800000 -0.100000 -1.000000
+m (rm=1) roundss_1XX a88796c49de35e40a800bba2bdcccccd ea6cd98c3ce482411301c62cbf800000 -0.100000 -1.000000
+r (rm=2) roundss_1XX b36f4b4b4664d540cb184c81bdcccccd dfab7d1de0e5ee82bcaf6f9080000000 -0.100000 -0.000000
+m (rm=2) roundss_1XX 2a99de800c4945adb28f2ca5bdcccccd 2f12bd52afd032c659e1646e80000000 -0.100000 -0.000000
+r (rm=3) roundss_1XX 694f49d08b1deb333b2fd6f8bdcccccd 34eb9398443089bac46221b280000000 -0.100000 -0.000000
+m (rm=3) roundss_1XX ccde8aa85e6c037f40c4c668bdcccccd 4c83fd5c3c923109daff234880000000 -0.100000 -0.000000
+r (rm=0) roundss_1XX af929c7221c3c93d9f1c78df3dcccccd d126f709328164607884e41c00000000 0.100000 0.000000
+m (rm=0) roundss_1XX 6eb77c9c71ad78183202684b3dcccccd 21207b0ac3895e6b78bde21a00000000 0.100000 0.000000
+r (rm=1) roundss_1XX 65992491eab74dbdd64113973dcccccd 96bc87cd8a375dd5b776992f00000000 0.100000 0.000000
+m (rm=1) roundss_1XX f08492bd266b84d867a6f3af3dcccccd 8d4815bd23169b4b127b834500000000 0.100000 0.000000
+r (rm=2) roundss_1XX 6bc3c18cc4585914c2fd867f3dcccccd 630e24462bb2557963971e4a3f800000 0.100000 1.000000
+m (rm=2) roundss_1XX 31a3ad6a5e07071ec11248f33dcccccd 725cadd43e98c70a8798e4283f800000 0.100000 1.000000
+r (rm=3) roundss_1XX a07052c39006cba141b1b3f73dcccccd 177cadd3f7532caa5a4854cd00000000 0.100000 0.000000
+m (rm=3) roundss_1XX 1376ad03f7e0e14a1ea645783dcccccd afba21b0f26fc107b874e72400000000 0.100000 0.000000
+r (rm=0) roundss_1XX e601b9962e2284c534bc79603e99999a 946404d5cc79c2ca7de81a1900000000 0.300000 0.000000
+m (rm=0) roundss_1XX 745d72e9d156f1bd5fc0cb9d3e99999a 23c552af21fc6aa2856f6a9800000000 0.300000 0.000000
+r (rm=1) roundss_1XX 1bd5d4667d0b64df7b7fb7193e99999a b82808ab8b84f639acd7528d00000000 0.300000 0.000000
+m (rm=1) roundss_1XX 36b7dc7bceca19d664c3bac23e99999a afda2034a99ea23bceea4ee500000000 0.300000 0.000000
+r (rm=2) roundss_1XX 204d84935f214b4ff6584f833e99999a 642798b515d5aa56c776db8a3f800000 0.300000 1.000000
+m (rm=2) roundss_1XX 37e4ca19cd9b37f50d0cf2483e99999a 335b6b9c6bb64933734573693f800000 0.300000 1.000000
+r (rm=3) roundss_1XX d5c8a97bb3c5197585aa1ffd3e99999a 78c2955448cbbc81ae24946f00000000 0.300000 0.000000
+m (rm=3) roundss_1XX 58441e24ad2a2c7b3afd528e3e99999a 8fa8134947a23fea54dfb98600000000 0.300000 0.000000
+r (rm=0) roundss_1XX 1aa623805856adb208d208e73efffeb0 d458dfe704c70e1a41415e9c00000000 0.499990 0.000000
+m (rm=0) roundss_1XX 7938b6fb4fd6d8c7cbf5bcf43efffeb0 a31ff79a1dc564be5118009c00000000 0.499990 0.000000
+r (rm=1) roundss_1XX cf47d2022f35e9665e32eaa13efffeb0 584a56cf2b287e825f2e197200000000 0.499990 0.000000
+m (rm=1) roundss_1XX 792073ff94ff1b3a9f550edb3efffeb0 4f23f9f0cc7c97124950270a00000000 0.499990 0.000000
+r (rm=2) roundss_1XX d40c966019c1abef6929a58c3efffeb0 e4f6da6b9c4eed19ea4aa6503f800000 0.499990 1.000000
+m (rm=2) roundss_1XX 3a5a368f5a06d533987c29a23efffeb0 7211f7aa3629ba431ee810303f800000 0.499990 1.000000
+r (rm=3) roundss_1XX 08554ffaf45ad4af071818083efffeb0 57bf4b1b369a3b3dc0f6e29700000000 0.499990 0.000000
+m (rm=3) roundss_1XX 9b48dd0b824ae51294caeeaa3efffeb0 ee4bd229392cabb3ae3f996f00000000 0.499990 0.000000
+r (rm=0) roundss_1XX 4d81dc30a0614406195e25743f0000a8 93028940db6b4850c291b0a53f800000 0.500010 1.000000
+m (rm=0) roundss_1XX 7b4a49d4ec2b2d3874a03b523f0000a8 a1306accb7e34cc1dab6a3263f800000 0.500010 1.000000
+r (rm=1) roundss_1XX 81f01e63ff35db53805caa303f0000a8 762173396921f3b2d07befdd00000000 0.500010 0.000000
+m (rm=1) roundss_1XX bbbe5949770a8b04185df0fa3f0000a8 6d219ff38eb07bce82ac0fb500000000 0.500010 0.000000
+r (rm=2) roundss_1XX 8502f5f2f03679f61a70899c3f0000a8 e17ceb66c11d1ec2ca147e9c3f800000 0.500010 1.000000
+m (rm=2) roundss_1XX 3b07efcb0546e0d66062ef033f0000a8 307d51fe9ff319398681bb7d3f800000 0.500010 1.000000
+r (rm=3) roundss_1XX 3918423e52c5fe50c7fda0193f0000a8 b471cf28c3bea7e090bd3f4400000000 0.500010 0.000000
+m (rm=3) roundss_1XX db82e9b974400d0f2c0d17cc3f0000a8 cba4604eca0b0562c69687dd00000000 0.500010 0.000000
+r (rm=0) roundss_1XX 7d91e2a6074149c06960d0063f333333 cf6200de4f656f6c02d610353f800000 0.700000 1.000000
+m (rm=0) roundss_1XX 7b912973a656f00e5bc147b53f333333 1df7ac43ef5821aa214a55363f800000 0.700000 1.000000
+r (rm=1) roundss_1XX 31ceb88bed0b3ca6dffbf9c43f333333 12af5ee8457157c7ffbed2cd00000000 0.700000 0.000000
+m (rm=1) roundss_1XX fb938d5a79eb6a33cfdb611f3f333333 08d5143bed3b4c7079fd04e700000000 0.700000 0.000000
+r (rm=2) roundss_1XX 352ea34be582b563082dfbb23f333333 5db7c9a784423d5169d5656e3f800000 0.700000 1.000000
+m (rm=2) roundss_1XX 3be9f6ccce5c5adf66bd43693f333333 6b9f7998a6136515ac1073503f800000 0.700000 1.000000
+r (rm=3) roundss_1XX 68118349cf069556c557b6303f333333 8fda217bee3902681e7ba97800000000 0.700000 0.000000
+m (rm=3) roundss_1XX 1af2442c850ba27202c7cef43f333333 25b4bcbaf8404ef79be284d200000000 0.700000 0.000000
+r (rm=0) roundss_1XX acd837e28bf8bcdff7d8099f3f666666 8a7846c261b5856eff117e4a3f800000 0.900000 1.000000
+m (rm=0) roundss_1XX 7a0f57d87e58204a8157e21f3f666666 1874bb00c523e57926d415cc3f800000 0.900000 1.000000
+r (rm=1) roundss_1XX dfe2a078f9b70a5f7c11d65e3f666666 2cf217debe16a8c3ecf7c44400000000 0.900000 0.000000
+m (rm=1) roundss_1XX 399e0f3099a2b6c9c4d05f4a3f666666 224057caeb1b0bf82d45079e00000000 0.900000 0.000000
+r (rm=2) roundss_1XX e2909f6af9a45f353560fbce3f666666 56a8762fe6bd4ac6c58b5ac63f800000 0.900000 1.000000
+m (rm=2) roundss_1XX 38024b94b549424fab8f25d63f666666 247770794b88a0d690953aa93f800000 0.900000 1.000000
+r (rm=3) roundss_1XX 964012196a1d9bc20228594e3f666666 e8f84113b7094ad76a2f223100000000 0.900000 0.000000
+m (rm=3) roundss_1XX 5798ed65b4ada53b16f614223f666666 fe79e56bc5cb84732f258e4c00000000 0.900000 0.000000
+r (rm=0) roundss_1XX d955dae42e859d65c2c6d03e3f8ccccd c24459ed115b8956bb43fae53f800000 1.100000 1.000000
+m (rm=0) roundss_1XX 76c2d302742fbfede4640b8e3f8ccccd 90a798033944972dea54e3e83f800000 1.100000 1.000000
+r (rm=1) roundss_1XX 8b2cd62c2339477e579c40ff3f8ccccd c4ec9e1ad612e8a49725c3413f800000 1.100000 1.000000
+m (rm=1) roundss_1XX 75dfdfccd62e70c5f73aec7b3f8ccccd ba60679f8651b867a08318dc3f800000 1.100000 1.000000
+r (rm=2) roundss_1XX 8e27e84f2a9b776e9f0989f03f8ccccd cd4ff0fce58e4521e0385da540000000 1.100000 2.000000
+m (rm=2) roundss_1XX 3350ef22ba0b98242dd795483f8ccccd 5b04349f8e54c97e33100f8840000000 1.100000 2.000000
+r (rm=3) roundss_1XX c1a6efb0230a0e947c6e8b713f8ccccd bfcd2ff21d30802b74d9a8713f800000 1.100000 1.000000
+m (rm=3) roundss_1XX 9274e46400251769679be7563f8ccccd 55f4dd632faca8d4815ea64c3f800000 1.100000 1.000000
+r (rm=0) roundss_1XX 0307caaceee7ec50cc2a25e33fa66666 78c73a5d60577b24346a84063f800000 1.300000 1.000000
+m (rm=0) roundss_1XX 70ab9ef388ddccf586e7c2043fa66666 8690434c4bba36c86bcabe8a3f800000 1.300000 1.000000
+r (rm=1) roundss_1XX 35ac5aa56b91f103709e39a53fa66666 da9bf39c8c63156c004ad1c33f800000 1.300000 1.000000
+m (rm=1) roundss_1XX af56fc2e32919827681a06b23fa66666 cf3646b9c0dd53bbd1b6379f3f800000 1.300000 1.000000
+r (rm=2) roundss_1XX 38f580fa7969fd0c4828a5173fa66666 c3ac380f82b52d62b8da6e0940000000 1.300000 2.000000
+m (rm=2) roundss_1XX 2dd4e076dda35c5fee9593c13fa66666 1048c60b6f76df0c9382f1ed40000000 1.300000 2.000000
+r (rm=3) roundss_1XX ea411a0cfacef0cc342b4a9a3fa66666 1458eb1722aca5663c793d373f800000 1.300000 1.000000
+m (rm=3) roundss_1XX cb8629296b73f6fef7b648903fa66666 2926a3a138e4ba1b918cccd33f800000 1.300000 1.000000
+r (rm=0) roundpd_1XX bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+m (rm=0) roundpd_1XX bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+r (rm=1) roundpd_1XX bfdfffd60e94ee390000000000000000 bff00000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -1.000000
+m (rm=1) roundpd_1XX bfdfffd60e94ee390000000000000000 bff00000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -1.000000
+r (rm=2) roundpd_1XX bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+m (rm=2) roundpd_1XX bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+r (rm=3) roundpd_1XX bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+m (rm=3) roundpd_1XX bfdfffd60e94ee390000000000000000 80000000000000000000000000000000 0.000000 -> 0.000000 -0.499990 -> -0.000000
+r (rm=0) roundpd_1XX bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+m (rm=0) roundpd_1XX bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+r (rm=1) roundpd_1XX bfd33333333333338000000000000000 bff00000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -1.000000
+m (rm=1) roundpd_1XX bfd33333333333338000000000000000 bff00000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -1.000000
+r (rm=2) roundpd_1XX bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+m (rm=2) roundpd_1XX bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+r (rm=3) roundpd_1XX bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+m (rm=3) roundpd_1XX bfd33333333333338000000000000000 80000000000000008000000000000000 -0.000000 -> -0.000000 -0.300000 -> -0.000000
+r (rm=0) roundpd_1XX bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+m (rm=0) roundpd_1XX bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+r (rm=1) roundpd_1XX bfb999999999999a7ff0000000000000 bff00000000000007ff0000000000000 inf -> inf -0.100000 -> -1.000000
+m (rm=1) roundpd_1XX bfb999999999999a7ff0000000000000 bff00000000000007ff0000000000000 inf -> inf -0.100000 -> -1.000000
+r (rm=2) roundpd_1XX bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+m (rm=2) roundpd_1XX bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+r (rm=3) roundpd_1XX bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+m (rm=3) roundpd_1XX bfb999999999999a7ff0000000000000 80000000000000007ff0000000000000 inf -> inf -0.100000 -> -0.000000
+r (rm=0) roundpd_1XX 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+m (rm=0) roundpd_1XX 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+r (rm=1) roundpd_1XX 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+m (rm=1) roundpd_1XX 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+r (rm=2) roundpd_1XX 3fb999999999999afff0000000000000 3ff0000000000000fff0000000000000 -inf -> -inf 0.100000 -> 1.000000
+m (rm=2) roundpd_1XX 3fb999999999999afff0000000000000 3ff0000000000000fff0000000000000 -inf -> -inf 0.100000 -> 1.000000
+r (rm=3) roundpd_1XX 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+m (rm=3) roundpd_1XX 3fb999999999999afff0000000000000 0000000000000000fff0000000000000 -inf -> -inf 0.100000 -> 0.000000
+r (rm=0) roundpd_1XX 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+m (rm=0) roundpd_1XX 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+r (rm=1) roundpd_1XX 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+m (rm=1) roundpd_1XX 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+r (rm=2) roundpd_1XX 3fd3333333333333fff8000000000000 3ff0000000000000fff8000000000000 nan -> nan 0.300000 -> 1.000000
+m (rm=2) roundpd_1XX 3fd3333333333333fff8000000000000 3ff0000000000000fff8000000000000 nan -> nan 0.300000 -> 1.000000
+r (rm=3) roundpd_1XX 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+m (rm=3) roundpd_1XX 3fd3333333333333fff8000000000000 0000000000000000fff8000000000000 nan -> nan 0.300000 -> 0.000000
+r (rm=0) roundpd_1XX 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+m (rm=0) roundpd_1XX 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+r (rm=1) roundpd_1XX 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+m (rm=1) roundpd_1XX 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+r (rm=2) roundpd_1XX 3fdfffd60e94ee397ff8000000000000 3ff00000000000007ff8000000000000 nan -> nan 0.499990 -> 1.000000
+m (rm=2) roundpd_1XX 3fdfffd60e94ee397ff8000000000000 3ff00000000000007ff8000000000000 nan -> nan 0.499990 -> 1.000000
+r (rm=3) roundpd_1XX 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+m (rm=3) roundpd_1XX 3fdfffd60e94ee397ff8000000000000 00000000000000007ff8000000000000 nan -> nan 0.499990 -> 0.000000
+r (rm=0) roundpd_1XX 3fe00014f8b588e3bff4cccccccccccd 3ff0000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 1.000000
+m (rm=0) roundpd_1XX 3fe00014f8b588e3bff4cccccccccccd 3ff0000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 1.000000
+r (rm=1) roundpd_1XX 3fe00014f8b588e3bff4cccccccccccd 0000000000000000c000000000000000 -1.300000 -> -2.000000 0.500010 -> 0.000000
+m (rm=1) roundpd_1XX 3fe00014f8b588e3bff4cccccccccccd 0000000000000000c000000000000000 -1.300000 -> -2.000000 0.500010 -> 0.000000
+r (rm=2) roundpd_1XX 3fe00014f8b588e3bff4cccccccccccd 3ff0000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 1.000000
+m (rm=2) roundpd_1XX 3fe00014f8b588e3bff4cccccccccccd 3ff0000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 1.000000
+r (rm=3) roundpd_1XX 3fe00014f8b588e3bff4cccccccccccd 0000000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 0.000000
+m (rm=3) roundpd_1XX 3fe00014f8b588e3bff4cccccccccccd 0000000000000000bff0000000000000 -1.300000 -> -1.000000 0.500010 -> 0.000000
+r (rm=0) roundpd_1XX 3fe6666666666666bff199999999999a 3ff0000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 1.000000
+m (rm=0) roundpd_1XX 3fe6666666666666bff199999999999a 3ff0000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 1.000000
+r (rm=1) roundpd_1XX 3fe6666666666666bff199999999999a 0000000000000000c000000000000000 -1.100000 -> -2.000000 0.700000 -> 0.000000
+m (rm=1) roundpd_1XX 3fe6666666666666bff199999999999a 0000000000000000c000000000000000 -1.100000 -> -2.000000 0.700000 -> 0.000000
+r (rm=2) roundpd_1XX 3fe6666666666666bff199999999999a 3ff0000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 1.000000
+m (rm=2) roundpd_1XX 3fe6666666666666bff199999999999a 3ff0000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 1.000000
+r (rm=3) roundpd_1XX 3fe6666666666666bff199999999999a 0000000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 0.000000
+m (rm=3) roundpd_1XX 3fe6666666666666bff199999999999a 0000000000000000bff0000000000000 -1.100000 -> -1.000000 0.700000 -> 0.000000
+r (rm=0) roundpd_1XX 3feccccccccccccdbfeccccccccccccd 3ff0000000000000bff0000000000000 -0.900000 -> -1.000000 0.900000 -> 1.000000
+m (rm=0) roundpd_1XX 3feccccccccccccdbfeccccccccccccd 3ff0000000000000bff0000000000000 -0.900000 -> -1.000000 0.900000 -> 1.000000
+r (rm=1) roundpd_1XX 3feccccccccccccdbfeccccccccccccd 0000000000000000bff0000000000000 -0.900000 -> -1.000000 0.900000 -> 0.000000
+m (rm=1) roundpd_1XX 3feccccccccccccdbfeccccccccccccd 0000000000000000bff0000000000000 -0.900000 -> -1.000000 0.900000 -> 0.000000
+r (rm=2) roundpd_1XX 3feccccccccccccdbfeccccccccccccd 3ff00000000000008000000000000000 -0.900000 -> -0.000000 0.900000 -> 1.000000
+m (rm=2) roundpd_1XX 3feccccccccccccdbfeccccccccccccd 3ff00000000000008000000000000000 -0.900000 -> -0.000000 0.900000 -> 1.000000
+r (rm=3) roundpd_1XX 3feccccccccccccdbfeccccccccccccd 00000000000000008000000000000000 -0.900000 -> -0.000000 0.900000 -> 0.000000
+m (rm=3) roundpd_1XX 3feccccccccccccdbfeccccccccccccd 00000000000000008000000000000000 -0.900000 -> -0.000000 0.900000 -> 0.000000
+r (rm=0) roundpd_1XX 3ff199999999999abfe6666666666666 3ff0000000000000bff0000000000000 -0.700000 -> -1.000000 1.100000 -> 1.000000
+m (rm=0) roundpd_1XX 3ff199999999999abfe6666666666666 3ff0000000000000bff0000000000000 -0.700000 -> -1.000000 1.100000 -> 1.000000
+r (rm=1) roundpd_1XX 3ff199999999999abfe6666666666666 3ff0000000000000bff0000000000000 -0.700000 -> -1.000000 1.100000 -> 1.000000
+m (rm=1) roundpd_1XX 3ff199999999999abfe6666666666666 3ff0000000000000bff0000000000000 -0.700000 -> -1.000000 1.100000 -> 1.000000
+r (rm=2) roundpd_1XX 3ff199999999999abfe6666666666666 40000000000000008000000000000000 -0.700000 -> -0.000000 1.100000 -> 2.000000
+m (rm=2) roundpd_1XX 3ff199999999999abfe6666666666666 40000000000000008000000000000000 -0.700000 -> -0.000000 1.100000 -> 2.000000
+r (rm=3) roundpd_1XX 3ff199999999999abfe6666666666666 3ff00000000000008000000000000000 -0.700000 -> -0.000000 1.100000 -> 1.000000
+m (rm=3) roundpd_1XX 3ff199999999999abfe6666666666666 3ff00000000000008000000000000000 -0.700000 -> -0.000000 1.100000 -> 1.000000
+r (rm=0) roundpd_1XX 3ff4cccccccccccdbfe00014f8b588e3 3ff0000000000000bff0000000000000 -0.500010 -> -1.000000 1.300000 -> 1.000000
+m (rm=0) roundpd_1XX 3ff4cccccccccccdbfe00014f8b588e3 3ff0000000000000bff0000000000000 -0.500010 -> -1.000000 1.300000 -> 1.000000
+r (rm=1) roundpd_1XX 3ff4cccccccccccdbfe00014f8b588e3 3ff0000000000000bff0000000000000 -0.500010 -> -1.000000 1.300000 -> 1.000000
+m (rm=1) roundpd_1XX 3ff4cccccccccccdbfe00014f8b588e3 3ff0000000000000bff0000000000000 -0.500010 -> -1.000000 1.300000 -> 1.000000
+r (rm=2) roundpd_1XX 3ff4cccccccccccdbfe00014f8b588e3 40000000000000008000000000000000 -0.500010 -> -0.000000 1.300000 -> 2.000000
+m (rm=2) roundpd_1XX 3ff4cccccccccccdbfe00014f8b588e3 40000000000000008000000000000000 -0.500010 -> -0.000000 1.300000 -> 2.000000
+r (rm=3) roundpd_1XX 3ff4cccccccccccdbfe00014f8b588e3 3ff00000000000008000000000000000 -0.500010 -> -0.000000 1.300000 -> 1.000000
+m (rm=3) roundpd_1XX 3ff4cccccccccccdbfe00014f8b588e3 3ff00000000000008000000000000000 -0.500010 -> -0.000000 1.300000 -> 1.000000
+r (rm=0) roundpd_1XX 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+m (rm=0) roundpd_1XX 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+r (rm=1) roundpd_1XX 0000000000000000bfdfffd60e94ee39 0000000000000000bff0000000000000 -0.499990 -> -1.000000 0.000000 -> 0.000000
+m (rm=1) roundpd_1XX 0000000000000000bfdfffd60e94ee39 0000000000000000bff0000000000000 -0.499990 -> -1.000000 0.000000 -> 0.000000
+r (rm=2) roundpd_1XX 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+m (rm=2) roundpd_1XX 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+r (rm=3) roundpd_1XX 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+m (rm=3) roundpd_1XX 0000000000000000bfdfffd60e94ee39 00000000000000008000000000000000 -0.499990 -> -0.000000 0.000000 -> 0.000000
+r (rm=0) roundpd_1XX 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+m (rm=0) roundpd_1XX 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+r (rm=1) roundpd_1XX 8000000000000000bfd3333333333333 8000000000000000bff0000000000000 -0.300000 -> -1.000000 -0.000000 -> -0.000000
+m (rm=1) roundpd_1XX 8000000000000000bfd3333333333333 8000000000000000bff0000000000000 -0.300000 -> -1.000000 -0.000000 -> -0.000000
+r (rm=2) roundpd_1XX 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+m (rm=2) roundpd_1XX 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+r (rm=3) roundpd_1XX 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+m (rm=3) roundpd_1XX 8000000000000000bfd3333333333333 80000000000000008000000000000000 -0.300000 -> -0.000000 -0.000000 -> -0.000000
+r (rm=0) roundpd_1XX 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+m (rm=0) roundpd_1XX 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+r (rm=1) roundpd_1XX 7ff0000000000000bfb999999999999a 7ff0000000000000bff0000000000000 -0.100000 -> -1.000000 inf -> inf
+m (rm=1) roundpd_1XX 7ff0000000000000bfb999999999999a 7ff0000000000000bff0000000000000 -0.100000 -> -1.000000 inf -> inf
+r (rm=2) roundpd_1XX 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+m (rm=2) roundpd_1XX 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+r (rm=3) roundpd_1XX 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+m (rm=3) roundpd_1XX 7ff0000000000000bfb999999999999a 7ff00000000000008000000000000000 -0.100000 -> -0.000000 inf -> inf
+r (rm=0) roundpd_1XX fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+m (rm=0) roundpd_1XX fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+r (rm=1) roundpd_1XX fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+m (rm=1) roundpd_1XX fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+r (rm=2) roundpd_1XX fff00000000000003fb999999999999a fff00000000000003ff0000000000000 0.100000 -> 1.000000 -inf -> -inf
+m (rm=2) roundpd_1XX fff00000000000003fb999999999999a fff00000000000003ff0000000000000 0.100000 -> 1.000000 -inf -> -inf
+r (rm=3) roundpd_1XX fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+m (rm=3) roundpd_1XX fff00000000000003fb999999999999a fff00000000000000000000000000000 0.100000 -> 0.000000 -inf -> -inf
+r (rm=0) roundpd_1XX fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+m (rm=0) roundpd_1XX fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+r (rm=1) roundpd_1XX fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+m (rm=1) roundpd_1XX fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+r (rm=2) roundpd_1XX fff80000000000003fd3333333333333 fff80000000000003ff0000000000000 0.300000 -> 1.000000 nan -> nan
+m (rm=2) roundpd_1XX fff80000000000003fd3333333333333 fff80000000000003ff0000000000000 0.300000 -> 1.000000 nan -> nan
+r (rm=3) roundpd_1XX fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+m (rm=3) roundpd_1XX fff80000000000003fd3333333333333 fff80000000000000000000000000000 0.300000 -> 0.000000 nan -> nan
+r (rm=0) roundpd_1XX 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+m (rm=0) roundpd_1XX 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+r (rm=1) roundpd_1XX 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+m (rm=1) roundpd_1XX 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+r (rm=2) roundpd_1XX 7ff80000000000003fdfffd60e94ee39 7ff80000000000003ff0000000000000 0.499990 -> 1.000000 nan -> nan
+m (rm=2) roundpd_1XX 7ff80000000000003fdfffd60e94ee39 7ff80000000000003ff0000000000000 0.499990 -> 1.000000 nan -> nan
+r (rm=3) roundpd_1XX 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+m (rm=3) roundpd_1XX 7ff80000000000003fdfffd60e94ee39 7ff80000000000000000000000000000 0.499990 -> 0.000000 nan -> nan
+r (rm=0) roundpd_1XX bff4cccccccccccd3fe00014f8b588e3 bff00000000000003ff0000000000000 0.500010 -> 1.000000 -1.300000 -> -1.000000
+m (rm=0) roundpd_1XX bff4cccccccccccd3fe00014f8b588e3 bff00000000000003ff0000000000000 0.500010 -> 1.000000 -1.300000 -> -1.000000
+r (rm=1) roundpd_1XX bff4cccccccccccd3fe00014f8b588e3 c0000000000000000000000000000000 0.500010 -> 0.000000 -1.300000 -> -2.000000
+m (rm=1) roundpd_1XX bff4cccccccccccd3fe00014f8b588e3 c0000000000000000000000000000000 0.500010 -> 0.000000 -1.300000 -> -2.000000
+r (rm=2) roundpd_1XX bff4cccccccccccd3fe00014f8b588e3 bff00000000000003ff0000000000000 0.500010 -> 1.000000 -1.300000 -> -1.000000
+m (rm=2) roundpd_1XX bff4cccccccccccd3fe00014f8b588e3 bff00000000000003ff0000000000000 0.500010 -> 1.000000 -1.300000 -> -1.000000
+r (rm=3) roundpd_1XX bff4cccccccccccd3fe00014f8b588e3 bff00000000000000000000000000000 0.500010 -> 0.000000 -1.300000 -> -1.000000
+m (rm=3) roundpd_1XX bff4cccccccccccd3fe00014f8b588e3 bff00000000000000000000000000000 0.500010 -> 0.000000 -1.300000 -> -1.000000
+r (rm=0) roundpd_1XX bff199999999999a3fe6666666666666 bff00000000000003ff0000000000000 0.700000 -> 1.000000 -1.100000 -> -1.000000
+m (rm=0) roundpd_1XX bff199999999999a3fe6666666666666 bff00000000000003ff0000000000000 0.700000 -> 1.000000 -1.100000 -> -1.000000
+r (rm=1) roundpd_1XX bff199999999999a3fe6666666666666 c0000000000000000000000000000000 0.700000 -> 0.000000 -1.100000 -> -2.000000
+m (rm=1) roundpd_1XX bff199999999999a3fe6666666666666 c0000000000000000000000000000000 0.700000 -> 0.000000 -1.100000 -> -2.000000
+r (rm=2) roundpd_1XX bff199999999999a3fe6666666666666 bff00000000000003ff0000000000000 0.700000 -> 1.000000 -1.100000 -> -1.000000
+m (rm=2) roundpd_1XX bff199999999999a3fe6666666666666 bff00000000000003ff0000000000000 0.700000 -> 1.000000 -1.100000 -> -1.000000
+r (rm=3) roundpd_1XX bff199999999999a3fe6666666666666 bff00000000000000000000000000000 0.700000 -> 0.000000 -1.100000 -> -1.000000
+m (rm=3) roundpd_1XX bff199999999999a3fe6666666666666 bff00000000000000000000000000000 0.700000 -> 0.000000 -1.100000 -> -1.000000
+r (rm=0) roundpd_1XX bfeccccccccccccd3feccccccccccccd bff00000000000003ff0000000000000 0.900000 -> 1.000000 -0.900000 -> -1.000000
+m (rm=0) roundpd_1XX bfeccccccccccccd3feccccccccccccd bff00000000000003ff0000000000000 0.900000 -> 1.000000 -0.900000 -> -1.000000
+r (rm=1) roundpd_1XX bfeccccccccccccd3feccccccccccccd bff00000000000000000000000000000 0.900000 -> 0.000000 -0.900000 -> -1.000000
+m (rm=1) roundpd_1XX bfeccccccccccccd3feccccccccccccd bff00000000000000000000000000000 0.900000 -> 0.000000 -0.900000 -> -1.000000
+r (rm=2) roundpd_1XX bfeccccccccccccd3feccccccccccccd 80000000000000003ff0000000000000 0.900000 -> 1.000000 -0.900000 -> -0.000000
+m (rm=2) roundpd_1XX bfeccccccccccccd3feccccccccccccd 80000000000000003ff0000000000000 0.900000 -> 1.000000 -0.900000 -> -0.000000
+r (rm=3) roundpd_1XX bfeccccccccccccd3feccccccccccccd 80000000000000000000000000000000 0.900000 -> 0.000000 -0.900000 -> -0.000000
+m (rm=3) roundpd_1XX bfeccccccccccccd3feccccccccccccd 80000000000000000000000000000000 0.900000 -> 0.000000 -0.900000 -> -0.000000
+r (rm=0) roundpd_1XX bfe66666666666663ff199999999999a bff00000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -1.000000
+m (rm=0) roundpd_1XX bfe66666666666663ff199999999999a bff00000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -1.000000
+r (rm=1) roundpd_1XX bfe66666666666663ff199999999999a bff00000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -1.000000
+m (rm=1) roundpd_1XX bfe66666666666663ff199999999999a bff00000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -1.000000
+r (rm=2) roundpd_1XX bfe66666666666663ff199999999999a 80000000000000004000000000000000 1.100000 -> 2.000000 -0.700000 -> -0.000000
+m (rm=2) roundpd_1XX bfe66666666666663ff199999999999a 80000000000000004000000000000000 1.100000 -> 2.000000 -0.700000 -> -0.000000
+r (rm=3) roundpd_1XX bfe66666666666663ff199999999999a 80000000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -0.000000
+m (rm=3) roundpd_1XX bfe66666666666663ff199999999999a 80000000000000003ff0000000000000 1.100000 -> 1.000000 -0.700000 -> -0.000000
+r (rm=0) roundpd_1XX bfe00014f8b588e33ff4cccccccccccd bff00000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -1.000000
+m (rm=0) roundpd_1XX bfe00014f8b588e33ff4cccccccccccd bff00000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -1.000000
+r (rm=1) roundpd_1XX bfe00014f8b588e33ff4cccccccccccd bff00000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -1.000000
+m (rm=1) roundpd_1XX bfe00014f8b588e33ff4cccccccccccd bff00000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -1.000000
+r (rm=2) roundpd_1XX bfe00014f8b588e33ff4cccccccccccd 80000000000000004000000000000000 1.300000 -> 2.000000 -0.500010 -> -0.000000
+m (rm=2) roundpd_1XX bfe00014f8b588e33ff4cccccccccccd 80000000000000004000000000000000 1.300000 -> 2.000000 -0.500010 -> -0.000000
+r (rm=3) roundpd_1XX bfe00014f8b588e33ff4cccccccccccd 80000000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -0.000000
+m (rm=3) roundpd_1XX bfe00014f8b588e33ff4cccccccccccd 80000000000000003ff0000000000000 1.300000 -> 1.000000 -0.500010 -> -0.000000
+r (rm=0) roundps_1XX 3f0000a8befffeb07fc0000000000000 3f800000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 1.000000
+m (rm=0) roundps_1XX 3f0000a8befffeb07fc0000000000000 3f800000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 1.000000
+r (rm=1) roundps_1XX 3f0000a8befffeb07fc0000000000000 00000000bf8000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-1.000000 0.500010: 0.000000
+m (rm=1) roundps_1XX 3f0000a8befffeb07fc0000000000000 00000000bf8000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-1.000000 0.500010: 0.000000
+r (rm=2) roundps_1XX 3f0000a8befffeb07fc0000000000000 3f800000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 1.000000
+m (rm=2) roundps_1XX 3f0000a8befffeb07fc0000000000000 3f800000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 1.000000
+r (rm=3) roundps_1XX 3f0000a8befffeb07fc0000000000000 00000000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 0.000000
+m (rm=3) roundps_1XX 3f0000a8befffeb07fc0000000000000 00000000800000007fc0000000000000 0.000000: 0.000000 nan: nan -0.499990:-0.000000 0.500010: 0.000000
+r (rm=0) roundps_1XX 3f333333be99999abfa6666680000000 3f80000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000
+m (rm=0) roundps_1XX 3f333333be99999abfa6666680000000 3f80000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000
+r (rm=1) roundps_1XX 3f333333be99999abfa6666680000000 00000000bf800000c000000080000000 -0.000000:-0.000000 -1.300000:-2.000000 -0.300000:-1.000000 0.700000: 0.000000
+m (rm=1) roundps_1XX 3f333333be99999abfa6666680000000 00000000bf800000c000000080000000 -0.000000:-0.000000 -1.300000:-2.000000 -0.300000:-1.000000 0.700000: 0.000000
+r (rm=2) roundps_1XX 3f333333be99999abfa6666680000000 3f80000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000
+m (rm=2) roundps_1XX 3f333333be99999abfa6666680000000 3f80000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000
+r (rm=3) roundps_1XX 3f333333be99999abfa6666680000000 0000000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 0.000000
+m (rm=3) roundps_1XX 3f333333be99999abfa6666680000000 0000000080000000bf80000080000000 -0.000000:-0.000000 -1.300000:-1.000000 -0.300000:-0.000000 0.700000: 0.000000
+r (rm=0) roundps_1XX 3f666666bdcccccdbf8ccccd7f800000 3f80000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000
+m (rm=0) roundps_1XX 3f666666bdcccccdbf8ccccd7f800000 3f80000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000
+r (rm=1) roundps_1XX 3f666666bdcccccdbf8ccccd7f800000 00000000bf800000c00000007f800000 inf: inf -1.100000:-2.000000 -0.100000:-1.000000 0.900000: 0.000000
+m (rm=1) roundps_1XX 3f666666bdcccccdbf8ccccd7f800000 00000000bf800000c00000007f800000 inf: inf -1.100000:-2.000000 -0.100000:-1.000000 0.900000: 0.000000
+r (rm=2) roundps_1XX 3f666666bdcccccdbf8ccccd7f800000 3f80000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000
+m (rm=2) roundps_1XX 3f666666bdcccccdbf8ccccd7f800000 3f80000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000
+r (rm=3) roundps_1XX 3f666666bdcccccdbf8ccccd7f800000 0000000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 0.000000
+m (rm=3) roundps_1XX 3f666666bdcccccdbf8ccccd7f800000 0000000080000000bf8000007f800000 inf: inf -1.100000:-1.000000 -0.100000:-0.000000 0.900000: 0.000000
+r (rm=0) roundps_1XX 3f8ccccd3dcccccdbf666666ff800000 3f80000000000000bf800000ff800000 -inf: -inf -0.900000:-1.000000 0.100000: 0.000000 1.100000: 1.000000
+m (rm=0) roundps_1XX 3f8ccccd3dcccccdbf666666ff800000 3f80000000000000bf800000ff800000 -inf: -inf -0.900000:-1.000000 0.100000: 0.000000 1.100000: 1.000000
+r (rm=1) roundps_1XX 3f8ccccd3dcccccdbf666666ff800000 3f80000000000000bf800000ff800000 -inf: -inf -0.900000:-1.000000 0.100000: 0.000000 1.100000: 1.000000
+m (rm=1) roundps_1XX 3f8ccccd3dcccccdbf666666ff800000 3f80000000000000bf800000ff800000 -inf: -inf -0.900000:-1.000000 0.100000: 0.000000 1.100000: 1.000000
+r (rm=2) roundps_1XX 3f8ccccd3dcccccdbf666666ff800000 400000003f80000080000000ff800000 -inf: -inf -0.900000:-0.000000 0.100000: 1.000000 1.100000: 2.000000
+m (rm=2) roundps_1XX 3f8ccccd3dcccccdbf666666ff800000 400000003f80000080000000ff800000 -inf: -inf -0.900000:-0.000000 0.100000: 1.000000 1.100000: 2.000000
+r (rm=3) roundps_1XX 3f8ccccd3dcccccdbf666666ff800000 3f8000000000000080000000ff800000 -inf: -inf -0.900000:-0.000000 0.100000: 0.000000 1.100000: 1.000000
+m (rm=3) roundps_1XX 3f8ccccd3dcccccdbf666666ff800000 3f8000000000000080000000ff800000 -inf: -inf -0.900000:-0.000000 0.100000: 0.000000 1.100000: 1.000000
+r (rm=0) roundps_1XX 3fa666663e99999abf333333ffc00000 3f80000000000000bf800000ffc00000 nan: nan -0.700000:-1.000000 0.300000: 0.000000 1.300000: 1.000000
+m (rm=0) roundps_1XX 3fa666663e99999abf333333ffc00000 3f80000000000000bf800000ffc00000 nan: nan -0.700000:-1.000000 0.300000: 0.000000 1.300000: 1.000000
+r (rm=1) roundps_1XX 3fa666663e99999abf333333ffc00000 3f80000000000000bf800000ffc00000 nan: nan -0.700000:-1.000000 0.300000: 0.000000 1.300000: 1.000000
+m (rm=1) roundps_1XX 3fa666663e99999abf333333ffc00000 3f80000000000000bf800000ffc00000 nan: nan -0.700000:-1.000000 0.300000: 0.000000 1.300000: 1.000000
+r (rm=2) roundps_1XX 3fa666663e99999abf333333ffc00000 400000003f80000080000000ffc00000 nan: nan -0.700000:-0.000000 0.300000: 1.000000 1.300000: 2.000000
+m (rm=2) roundps_1XX 3fa666663e99999abf333333ffc00000 400000003f80000080000000ffc00000 nan: nan -0.700000:-0.000000 0.300000: 1.000000 1.300000: 2.000000
+r (rm=3) roundps_1XX 3fa666663e99999abf333333ffc00000 3f8000000000000080000000ffc00000 nan: nan -0.700000:-0.000000 0.300000: 0.000000 1.300000: 1.000000
+m (rm=3) roundps_1XX 3fa666663e99999abf333333ffc00000 3f8000000000000080000000ffc00000 nan: nan -0.700000:-0.000000 0.300000: 0.000000 1.300000: 1.000000
+r (rm=0) roundps_1XX 000000003efffeb0bf0000a87fc00000 0000000000000000bf8000007fc00000 nan: nan -0.500010:-1.000000 0.499990: 0.000000 0.000000: 0.000000
+m (rm=0) roundps_1XX 000000003efffeb0bf0000a87fc00000 0000000000000000bf8000007fc00000 nan: nan -0.500010:-1.000000 0.499990: 0.000000 0.000000: 0.000000
+r (rm=1) roundps_1XX 000000003efffeb0bf0000a87fc00000 0000000000000000bf8000007fc00000 nan: nan -0.500010:-1.000000 0.499990: 0.000000 0.000000: 0.000000
+m (rm=1) roundps_1XX 000000003efffeb0bf0000a87fc00000 0000000000000000bf8000007fc00000 nan: nan -0.500010:-1.000000 0.499990: 0.000000 0.000000: 0.000000
+r (rm=2) roundps_1XX 000000003efffeb0bf0000a87fc00000 000000003f800000800000007fc00000 nan: nan -0.500010:-0.000000 0.499990: 1.000000 0.000000: 0.000000
+m (rm=2) roundps_1XX 000000003efffeb0bf0000a87fc00000 000000003f800000800000007fc00000 nan: nan -0.500010:-0.000000 0.499990: 1.000000 0.000000: 0.000000
+r (rm=3) roundps_1XX 000000003efffeb0bf0000a87fc00000 0000000000000000800000007fc00000 nan: nan -0.500010:-0.000000 0.499990: 0.000000 0.000000: 0.000000
+m (rm=3) roundps_1XX 000000003efffeb0bf0000a87fc00000 0000000000000000800000007fc00000 nan: nan -0.500010:-0.000000 0.499990: 0.000000 0.000000: 0.000000
+r (rm=0) roundps_1XX 800000003f0000a8befffeb0bfa66666 800000003f80000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 1.000000 -0.000000:-0.000000
+m (rm=0) roundps_1XX 800000003f0000a8befffeb0bfa66666 800000003f80000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 1.000000 -0.000000:-0.000000
+r (rm=1) roundps_1XX 800000003f0000a8befffeb0bfa66666 8000000000000000bf800000c0000000 -1.300000:-2.000000 -0.499990:-1.000000 0.500010: 0.000000 -0.000000:-0.000000
+m (rm=1) roundps_1XX 800000003f0000a8befffeb0bfa66666 8000000000000000bf800000c0000000 -1.300000:-2.000000 -0.499990:-1.000000 0.500010: 0.000000 -0.000000:-0.000000
+r (rm=2) roundps_1XX 800000003f0000a8befffeb0bfa66666 800000003f80000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 1.000000 -0.000000:-0.000000
+m (rm=2) roundps_1XX 800000003f0000a8befffeb0bfa66666 800000003f80000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 1.000000 -0.000000:-0.000000
+r (rm=3) roundps_1XX 800000003f0000a8befffeb0bfa66666 800000000000000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 0.000000 -0.000000:-0.000000
+m (rm=3) roundps_1XX 800000003f0000a8befffeb0bfa66666 800000000000000080000000bf800000 -1.300000:-1.000000 -0.499990:-0.000000 0.500010: 0.000000 -0.000000:-0.000000
+r (rm=0) roundps_1XX 7f8000003f333333be99999abf8ccccd 7f8000003f80000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000 inf: inf
+m (rm=0) roundps_1XX 7f8000003f333333be99999abf8ccccd 7f8000003f80000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000 inf: inf
+r (rm=1) roundps_1XX 7f8000003f333333be99999abf8ccccd 7f80000000000000bf800000c0000000 -1.100000:-2.000000 -0.300000:-1.000000 0.700000: 0.000000 inf: inf
+m (rm=1) roundps_1XX 7f8000003f333333be99999abf8ccccd 7f80000000000000bf800000c0000000 -1.100000:-2.000000 -0.300000:-1.000000 0.700000: 0.000000 inf: inf
+r (rm=2) roundps_1XX 7f8000003f333333be99999abf8ccccd 7f8000003f80000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000 inf: inf
+m (rm=2) roundps_1XX 7f8000003f333333be99999abf8ccccd 7f8000003f80000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 1.000000 inf: inf
+r (rm=3) roundps_1XX 7f8000003f333333be99999abf8ccccd 7f8000000000000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 0.000000 inf: inf
+m (rm=3) roundps_1XX 7f8000003f333333be99999abf8ccccd 7f8000000000000080000000bf800000 -1.100000:-1.000000 -0.300000:-0.000000 0.700000: 0.000000 inf: inf
+r (rm=0) roundps_1XX ff8000003f666666bdcccccdbf666666 ff8000003f80000080000000bf800000 -0.900000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000 -inf: -inf
+m (rm=0) roundps_1XX ff8000003f666666bdcccccdbf666666 ff8000003f80000080000000bf800000 -0.900000:-1.000000 -0.100000:-0.000000 0.900000: 1.000000 -inf: -inf
+r (rm=1) roundps_1XX ff8000003f666666bdcccccdbf666666 ff80000000000000bf800000bf800000 -0.900000:-1.000000 -0.100000:-1.000000 0.900000: 0.000000 -inf: -inf
+m (rm=1) roundps_1XX ff8000003f666666bdcccccdbf666666 ff80000000000000bf800000bf800000 -0.900000:-1.000000 -0.100000:-1.000000 0.900000: 0.000000 -inf: -inf
+r (rm=2) roundps_1XX ff8000003f666666bdcccccdbf666666 ff8000003f8000008000000080000000 -0.900000:-0.000000 -0.100000:-0.000000 0.900000: 1.000000 -inf: -inf
+m (rm=2) roundps_1XX ff8000003f666666bdcccccdbf666666 ff8000003f8000008000000080000000 -0.900000:-0.000000 -0.100000:-0.000000 0.900000: 1.000000 -inf: -inf
+r (rm=3) roundps_1XX ff8000003f666666bdcccccdbf666666 ff800000000000008000000080000000 -0.900000:-0.000000 -0.100000:-0.000000 0.900000: 0.000000 -inf: -inf
+m (rm=3) roundps_1XX ff8000003f666666bdcccccdbf666666 ff800000000000008000000080000000 -0.900000:-0.000000 -0.100000:-0.000000 0.900000: 0.000000 -inf: -inf
+r (rm=0) roundps_1XX ffc000003f8ccccd3dcccccdbf333333 ffc000003f80000000000000bf800000 -0.700000:-1.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+m (rm=0) roundps_1XX ffc000003f8ccccd3dcccccdbf333333 ffc000003f80000000000000bf800000 -0.700000:-1.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+r (rm=1) roundps_1XX ffc000003f8ccccd3dcccccdbf333333 ffc000003f80000000000000bf800000 -0.700000:-1.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+m (rm=1) roundps_1XX ffc000003f8ccccd3dcccccdbf333333 ffc000003f80000000000000bf800000 -0.700000:-1.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+r (rm=2) roundps_1XX ffc000003f8ccccd3dcccccdbf333333 ffc00000400000003f80000080000000 -0.700000:-0.000000 0.100000: 1.000000 1.100000: 2.000000 nan: nan
+m (rm=2) roundps_1XX ffc000003f8ccccd3dcccccdbf333333 ffc00000400000003f80000080000000 -0.700000:-0.000000 0.100000: 1.000000 1.100000: 2.000000 nan: nan
+r (rm=3) roundps_1XX ffc000003f8ccccd3dcccccdbf333333 ffc000003f8000000000000080000000 -0.700000:-0.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+m (rm=3) roundps_1XX ffc000003f8ccccd3dcccccdbf333333 ffc000003f8000000000000080000000 -0.700000:-0.000000 0.100000: 0.000000 1.100000: 1.000000 nan: nan
+r (rm=0) roundps_1XX 7fc000003fa666663e99999abf0000a8 7fc000003f80000000000000bf800000 -0.500010:-1.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+m (rm=0) roundps_1XX 7fc000003fa666663e99999abf0000a8 7fc000003f80000000000000bf800000 -0.500010:-1.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+r (rm=1) roundps_1XX 7fc000003fa666663e99999abf0000a8 7fc000003f80000000000000bf800000 -0.500010:-1.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+m (rm=1) roundps_1XX 7fc000003fa666663e99999abf0000a8 7fc000003f80000000000000bf800000 -0.500010:-1.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+r (rm=2) roundps_1XX 7fc000003fa666663e99999abf0000a8 7fc00000400000003f80000080000000 -0.500010:-0.000000 0.300000: 1.000000 1.300000: 2.000000 nan: nan
+m (rm=2) roundps_1XX 7fc000003fa666663e99999abf0000a8 7fc00000400000003f80000080000000 -0.500010:-0.000000 0.300000: 1.000000 1.300000: 2.000000 nan: nan
+r (rm=3) roundps_1XX 7fc000003fa666663e99999abf0000a8 7fc000003f8000000000000080000000 -0.500010:-0.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+m (rm=3) roundps_1XX 7fc000003fa666663e99999abf0000a8 7fc000003f8000000000000080000000 -0.500010:-0.000000 0.300000: 0.000000 1.300000: 1.000000 nan: nan
+r (rm=0) roundps_1XX bfa66666000000003efffeb0befffeb0 bf800000000000000000000080000000 -0.499990:-0.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-1.000000
+m (rm=0) roundps_1XX bfa66666000000003efffeb0befffeb0 bf800000000000000000000080000000 -0.499990:-0.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-1.000000
+r (rm=1) roundps_1XX bfa66666000000003efffeb0befffeb0 c00000000000000000000000bf800000 -0.499990:-1.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-2.000000
+m (rm=1) roundps_1XX bfa66666000000003efffeb0befffeb0 c00000000000000000000000bf800000 -0.499990:-1.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-2.000000
+r (rm=2) roundps_1XX bfa66666000000003efffeb0befffeb0 bf800000000000003f80000080000000 -0.499990:-0.000000 0.499990: 1.000000 0.000000: 0.000000 -1.300000:-1.000000
+m (rm=2) roundps_1XX bfa66666000000003efffeb0befffeb0 bf800000000000003f80000080000000 -0.499990:-0.000000 0.499990: 1.000000 0.000000: 0.000000 -1.300000:-1.000000
+r (rm=3) roundps_1XX bfa66666000000003efffeb0befffeb0 bf800000000000000000000080000000 -0.499990:-0.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-1.000000
+m (rm=3) roundps_1XX bfa66666000000003efffeb0befffeb0 bf800000000000000000000080000000 -0.499990:-0.000000 0.499990: 0.000000 0.000000: 0.000000 -1.300000:-1.000000
+r (rm=0) roundps_1XX bf8ccccd800000003f0000a8be99999a bf800000800000003f80000080000000 -0.300000:-0.000000 0.500010: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000
+m (rm=0) roundps_1XX bf8ccccd800000003f0000a8be99999a bf800000800000003f80000080000000 -0.300000:-0.000000 0.500010: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000
+r (rm=1) roundps_1XX bf8ccccd800000003f0000a8be99999a c00000008000000000000000bf800000 -0.300000:-1.000000 0.500010: 0.000000 -0.000000:-0.000000 -1.100000:-2.000000
+m (rm=1) roundps_1XX bf8ccccd800000003f0000a8be99999a c00000008000000000000000bf800000 -0.300000:-1.000000 0.500010: 0.000000 -0.000000:-0.000000 -1.100000:-2.000000
+r (rm=2) roundps_1XX bf8ccccd800000003f0000a8be99999a bf800000800000003f80000080000000 -0.300000:-0.000000 0.500010: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000
+m (rm=2) roundps_1XX bf8ccccd800000003f0000a8be99999a bf800000800000003f80000080000000 -0.300000:-0.000000 0.500010: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000
+r (rm=3) roundps_1XX bf8ccccd800000003f0000a8be99999a bf800000800000000000000080000000 -0.300000:-0.000000 0.500010: 0.000000 -0.000000:-0.000000 -1.100000:-1.000000
+m (rm=3) roundps_1XX bf8ccccd800000003f0000a8be99999a bf800000800000000000000080000000 -0.300000:-0.000000 0.500010: 0.000000 -0.000000:-0.000000 -1.100000:-1.000000
+r (rm=0) roundps_1XX bf6666667f8000003f333333bdcccccd bf8000007f8000003f80000080000000 -0.100000:-0.000000 0.700000: 1.000000 inf: inf -0.900000:-1.000000
+m (rm=0) roundps_1XX bf6666667f8000003f333333bdcccccd bf8000007f8000003f80000080000000 -0.100000:-0.000000 0.700000: 1.000000 inf: inf -0.900000:-1.000000
+r (rm=1) roundps_1XX bf6666667f8000003f333333bdcccccd bf8000007f80000000000000bf800000 -0.100000:-1.000000 0.700000: 0.000000 inf: inf -0.900000:-1.000000
+m (rm=1) roundps_1XX bf6666667f8000003f333333bdcccccd bf8000007f80000000000000bf800000 -0.100000:-1.000000 0.700000: 0.000000 inf: inf -0.900000:-1.000000
+r (rm=2) roundps_1XX bf6666667f8000003f333333bdcccccd 800000007f8000003f80000080000000 -0.100000:-0.000000 0.700000: 1.000000 inf: inf -0.900000:-0.000000
+m (rm=2) roundps_1XX bf6666667f8000003f333333bdcccccd 800000007f8000003f80000080000000 -0.100000:-0.000000 0.700000: 1.000000 inf: inf -0.900000:-0.000000
+r (rm=3) roundps_1XX bf6666667f8000003f333333bdcccccd 800000007f8000000000000080000000 -0.100000:-0.000000 0.700000: 0.000000 inf: inf -0.900000:-0.000000
+m (rm=3) roundps_1XX bf6666667f8000003f333333bdcccccd 800000007f8000000000000080000000 -0.100000:-0.000000 0.700000: 0.000000 inf: inf -0.900000:-0.000000
+r (rm=0) roundps_1XX bf333333ff8000003f6666663dcccccd bf800000ff8000003f80000000000000 0.100000: 0.000000 0.900000: 1.000000 -inf: -inf -0.700000:-1.000000
+m (rm=0) roundps_1XX bf333333ff8000003f6666663dcccccd bf800000ff8000003f80000000000000 0.100000: 0.000000 0.900000: 1.000000 -inf: -inf -0.700000:-1.000000
+r (rm=1) roundps_1XX bf333333ff8000003f6666663dcccccd bf800000ff8000000000000000000000 0.100000: 0.000000 0.900000: 0.000000 -inf: -inf -0.700000:-1.000000
+m (rm=1) roundps_1XX bf333333ff8000003f6666663dcccccd bf800000ff8000000000000000000000 0.100000: 0.000000 0.900000: 0.000000 -inf: -inf -0.700000:-1.000000
+r (rm=2) roundps_1XX bf333333ff8000003f6666663dcccccd 80000000ff8000003f8000003f800000 0.100000: 1.000000 0.900000: 1.000000 -inf: -inf -0.700000:-0.000000
+m (rm=2) roundps_1XX bf333333ff8000003f6666663dcccccd 80000000ff8000003f8000003f800000 0.100000: 1.000000 0.900000: 1.000000 -inf: -inf -0.700000:-0.000000
+r (rm=3) roundps_1XX bf333333ff8000003f6666663dcccccd 80000000ff8000000000000000000000 0.100000: 0.000000 0.900000: 0.000000 -inf: -inf -0.700000:-0.000000
+m (rm=3) roundps_1XX bf333333ff8000003f6666663dcccccd 80000000ff8000000000000000000000 0.100000: 0.000000 0.900000: 0.000000 -inf: -inf -0.700000:-0.000000
+r (rm=0) roundps_1XX bf0000a8ffc000003f8ccccd3e99999a bf800000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-1.000000
+m (rm=0) roundps_1XX bf0000a8ffc000003f8ccccd3e99999a bf800000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-1.000000
+r (rm=1) roundps_1XX bf0000a8ffc000003f8ccccd3e99999a bf800000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-1.000000
+m (rm=1) roundps_1XX bf0000a8ffc000003f8ccccd3e99999a bf800000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-1.000000
+r (rm=2) roundps_1XX bf0000a8ffc000003f8ccccd3e99999a 80000000ffc00000400000003f800000 0.300000: 1.000000 1.100000: 2.000000 nan: nan -0.500010:-0.000000
+m (rm=2) roundps_1XX bf0000a8ffc000003f8ccccd3e99999a 80000000ffc00000400000003f800000 0.300000: 1.000000 1.100000: 2.000000 nan: nan -0.500010:-0.000000
+r (rm=3) roundps_1XX bf0000a8ffc000003f8ccccd3e99999a 80000000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-0.000000
+m (rm=3) roundps_1XX bf0000a8ffc000003f8ccccd3e99999a 80000000ffc000003f80000000000000 0.300000: 0.000000 1.100000: 1.000000 nan: nan -0.500010:-0.000000
+r (rm=0) roundps_1XX befffeb07fc000003fa666663efffeb0 800000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-0.000000
+m (rm=0) roundps_1XX befffeb07fc000003fa666663efffeb0 800000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-0.000000
+r (rm=1) roundps_1XX befffeb07fc000003fa666663efffeb0 bf8000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-1.000000
+m (rm=1) roundps_1XX befffeb07fc000003fa666663efffeb0 bf8000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-1.000000
+r (rm=2) roundps_1XX befffeb07fc000003fa666663efffeb0 800000007fc00000400000003f800000 0.499990: 1.000000 1.300000: 2.000000 nan: nan -0.499990:-0.000000
+m (rm=2) roundps_1XX befffeb07fc000003fa666663efffeb0 800000007fc00000400000003f800000 0.499990: 1.000000 1.300000: 2.000000 nan: nan -0.499990:-0.000000
+r (rm=3) roundps_1XX befffeb07fc000003fa666663efffeb0 800000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-0.000000
+m (rm=3) roundps_1XX befffeb07fc000003fa666663efffeb0 800000007fc000003f80000000000000 0.499990: 0.000000 1.300000: 1.000000 nan: nan -0.499990:-0.000000
+r (rm=0) roundps_1XX be99999abfa66666000000003f0000a8 80000000bf800000000000003f800000 0.500010: 1.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+m (rm=0) roundps_1XX be99999abfa66666000000003f0000a8 80000000bf800000000000003f800000 0.500010: 1.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+r (rm=1) roundps_1XX be99999abfa66666000000003f0000a8 bf800000c00000000000000000000000 0.500010: 0.000000 0.000000: 0.000000 -1.300000:-2.000000 -0.300000:-1.000000
+m (rm=1) roundps_1XX be99999abfa66666000000003f0000a8 bf800000c00000000000000000000000 0.500010: 0.000000 0.000000: 0.000000 -1.300000:-2.000000 -0.300000:-1.000000
+r (rm=2) roundps_1XX be99999abfa66666000000003f0000a8 80000000bf800000000000003f800000 0.500010: 1.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+m (rm=2) roundps_1XX be99999abfa66666000000003f0000a8 80000000bf800000000000003f800000 0.500010: 1.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+r (rm=3) roundps_1XX be99999abfa66666000000003f0000a8 80000000bf8000000000000000000000 0.500010: 0.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+m (rm=3) roundps_1XX be99999abfa66666000000003f0000a8 80000000bf8000000000000000000000 0.500010: 0.000000 0.000000: 0.000000 -1.300000:-1.000000 -0.300000:-0.000000
+r (rm=0) roundps_1XX bdcccccdbf8ccccd800000003f333333 80000000bf800000800000003f800000 0.700000: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+m (rm=0) roundps_1XX bdcccccdbf8ccccd800000003f333333 80000000bf800000800000003f800000 0.700000: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+r (rm=1) roundps_1XX bdcccccdbf8ccccd800000003f333333 bf800000c00000008000000000000000 0.700000: 0.000000 -0.000000:-0.000000 -1.100000:-2.000000 -0.100000:-1.000000
+m (rm=1) roundps_1XX bdcccccdbf8ccccd800000003f333333 bf800000c00000008000000000000000 0.700000: 0.000000 -0.000000:-0.000000 -1.100000:-2.000000 -0.100000:-1.000000
+r (rm=2) roundps_1XX bdcccccdbf8ccccd800000003f333333 80000000bf800000800000003f800000 0.700000: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+m (rm=2) roundps_1XX bdcccccdbf8ccccd800000003f333333 80000000bf800000800000003f800000 0.700000: 1.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+r (rm=3) roundps_1XX bdcccccdbf8ccccd800000003f333333 80000000bf8000008000000000000000 0.700000: 0.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+m (rm=3) roundps_1XX bdcccccdbf8ccccd800000003f333333 80000000bf8000008000000000000000 0.700000: 0.000000 -0.000000:-0.000000 -1.100000:-1.000000 -0.100000:-0.000000
+r (rm=0) roundps_1XX 3dcccccdbf6666667f8000003f666666 00000000bf8000007f8000003f800000 0.900000: 1.000000 inf: inf -0.900000:-1.000000 0.100000: 0.000000
+m (rm=0) roundps_1XX 3dcccccdbf6666667f8000003f666666 00000000bf8000007f8000003f800000 0.900000: 1.000000 inf: inf -0.900000:-1.000000 0.100000: 0.000000
+r (rm=1) roundps_1XX 3dcccccdbf6666667f8000003f666666 00000000bf8000007f80000000000000 0.900000: 0.000000 inf: inf -0.900000:-1.000000 0.100000: 0.000000
+m (rm=1) roundps_1XX 3dcccccdbf6666667f8000003f666666 00000000bf8000007f80000000000000 0.900000: 0.000000 inf: inf -0.900000:-1.000000 0.100000: 0.000000
+r (rm=2) roundps_1XX 3dcccccdbf6666667f8000003f666666 3f800000800000007f8000003f800000 0.900000: 1.000000 inf: inf -0.900000:-0.000000 0.100000: 1.000000
+m (rm=2) roundps_1XX 3dcccccdbf6666667f8000003f666666 3f800000800000007f8000003f800000 0.900000: 1.000000 inf: inf -0.900000:-0.000000 0.100000: 1.000000
+r (rm=3) roundps_1XX 3dcccccdbf6666667f8000003f666666 00000000800000007f80000000000000 0.900000: 0.000000 inf: inf -0.900000:-0.000000 0.100000: 0.000000
+m (rm=3) roundps_1XX 3dcccccdbf6666667f8000003f666666 00000000800000007f80000000000000 0.900000: 0.000000 inf: inf -0.900000:-0.000000 0.100000: 0.000000
+r (rm=0) roundps_1XX 3e99999abf333333ff8000003f8ccccd 00000000bf800000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-1.000000 0.300000: 0.000000
+m (rm=0) roundps_1XX 3e99999abf333333ff8000003f8ccccd 00000000bf800000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-1.000000 0.300000: 0.000000
+r (rm=1) roundps_1XX 3e99999abf333333ff8000003f8ccccd 00000000bf800000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-1.000000 0.300000: 0.000000
+m (rm=1) roundps_1XX 3e99999abf333333ff8000003f8ccccd 00000000bf800000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-1.000000 0.300000: 0.000000
+r (rm=2) roundps_1XX 3e99999abf333333ff8000003f8ccccd 3f80000080000000ff80000040000000 1.100000: 2.000000 -inf: -inf -0.700000:-0.000000 0.300000: 1.000000
+m (rm=2) roundps_1XX 3e99999abf333333ff8000003f8ccccd 3f80000080000000ff80000040000000 1.100000: 2.000000 -inf: -inf -0.700000:-0.000000 0.300000: 1.000000
+r (rm=3) roundps_1XX 3e99999abf333333ff8000003f8ccccd 0000000080000000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-0.000000 0.300000: 0.000000
+m (rm=3) roundps_1XX 3e99999abf333333ff8000003f8ccccd 0000000080000000ff8000003f800000 1.100000: 1.000000 -inf: -inf -0.700000:-0.000000 0.300000: 0.000000
+r (rm=0) roundps_1XX 3efffeb0bf0000a8ffc000003fa66666 00000000bf800000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-1.000000 0.499990: 0.000000
+m (rm=0) roundps_1XX 3efffeb0bf0000a8ffc000003fa66666 00000000bf800000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-1.000000 0.499990: 0.000000
+r (rm=1) roundps_1XX 3efffeb0bf0000a8ffc000003fa66666 00000000bf800000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-1.000000 0.499990: 0.000000
+m (rm=1) roundps_1XX 3efffeb0bf0000a8ffc000003fa66666 00000000bf800000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-1.000000 0.499990: 0.000000
+r (rm=2) roundps_1XX 3efffeb0bf0000a8ffc000003fa66666 3f80000080000000ffc0000040000000 1.300000: 2.000000 nan: nan -0.500010:-0.000000 0.499990: 1.000000
+m (rm=2) roundps_1XX 3efffeb0bf0000a8ffc000003fa66666 3f80000080000000ffc0000040000000 1.300000: 2.000000 nan: nan -0.500010:-0.000000 0.499990: 1.000000
+r (rm=3) roundps_1XX 3efffeb0bf0000a8ffc000003fa66666 0000000080000000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-0.000000 0.499990: 0.000000
+m (rm=3) roundps_1XX 3efffeb0bf0000a8ffc000003fa66666 0000000080000000ffc000003f800000 1.300000: 1.000000 nan: nan -0.500010:-0.000000 0.499990: 0.000000
+r pcmpgtq 69c36c54086e8c1d28d0341bc599e8b2 f576b41eea543c3cbbe85f9caf91f60a 00000000000000000000000000000000
+m pcmpgtq 69c36c54086e8c1d28d0341bc599e8b2 f576b41eea543c3cbbe85f9caf91f60a 00000000000000000000000000000000
+r pcmpgtq 5b0686c55b87c7cf8ef500eeaafc86f9 374e33273e4b82dd4e20f8c1a9698053 0000000000000000ffffffffffffffff
+m pcmpgtq 5b0686c55b87c7cf8ef500eeaafc86f9 374e33273e4b82dd4e20f8c1a9698053 0000000000000000ffffffffffffffff
+r pcmpgtq 0587ea815640a7cb85f3052180cbab4e 204aba7048674c5fa058c97ce373af80 ffffffffffffffffffffffffffffffff
+m pcmpgtq 0587ea815640a7cb85f3052180cbab4e 204aba7048674c5fa058c97ce373af80 ffffffffffffffffffffffffffffffff
+r pcmpgtq c39192f4962468bdea98c1a0641313de 0ab54467a435d56c8d5c4eba78bc3ebe ffffffffffffffff0000000000000000
+m pcmpgtq c39192f4962468bdea98c1a0641313de 0ab54467a435d56c8d5c4eba78bc3ebe ffffffffffffffff0000000000000000
+r pcmpgtq f16f7c89b6bf485097aeaf5772df79d5 52dacd77ef415ab0f2f70465854feb39 ffffffffffffffffffffffffffffffff
+m pcmpgtq f16f7c89b6bf485097aeaf5772df79d5 52dacd77ef415ab0f2f70465854feb39 ffffffffffffffffffffffffffffffff
+r pcmpgtq ea6ea4af539d813169024c32c53c9a5e 5406510cc51516d8a9f6666b2538701c ffffffffffffffff0000000000000000
+m pcmpgtq ea6ea4af539d813169024c32c53c9a5e 5406510cc51516d8a9f6666b2538701c ffffffffffffffff0000000000000000
+r pcmpgtq 0cda04cf084b500b3c5f121d7a3532a6 6d85cc93c13f47908f26f0b775848a93 ffffffffffffffff0000000000000000
+m pcmpgtq 0cda04cf084b500b3c5f121d7a3532a6 6d85cc93c13f47908f26f0b775848a93 ffffffffffffffff0000000000000000
+r pcmpgtq b2ff9a567254f18bec937f05abd6fdd9 f7a33b767f4b278380511e35903df4cb ffffffffffffffff0000000000000000
+m pcmpgtq b2ff9a567254f18bec937f05abd6fdd9 f7a33b767f4b278380511e35903df4cb ffffffffffffffff0000000000000000
+r pcmpgtq 382960b02c459f5d55680ed4772cb622 4fac99229cc4f25e58446dd193726bf0 ffffffffffffffffffffffffffffffff
+m pcmpgtq 382960b02c459f5d55680ed4772cb622 4fac99229cc4f25e58446dd193726bf0 ffffffffffffffffffffffffffffffff
+r pcmpgtq f9a4544ad3a9972c53ac3b78f8411aad d1ebe204b436e6ccf3ca5777992cab2e 00000000000000000000000000000000
+m pcmpgtq f9a4544ad3a9972c53ac3b78f8411aad d1ebe204b436e6ccf3ca5777992cab2e 00000000000000000000000000000000
+r pcmpgtq 0000000000000000ffffffffffffffff 0000000000000000ffffffffffffffff 00000000000000000000000000000000
+m pcmpgtq 0000000000000000ffffffffffffffff 0000000000000000ffffffffffffffff 00000000000000000000000000000000
+r pcmpgtq 0000000000000000ffffffffffffffff 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000
+m pcmpgtq 0000000000000000ffffffffffffffff 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000
+r pcmpgtq 0000000000000000ffffffffffffffff 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+m pcmpgtq 0000000000000000ffffffffffffffff 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+r pcmpgtq 0000000000000000ffffffffffffffff 80000000000000008000000000000000 00000000000000000000000000000000
+m pcmpgtq 0000000000000000ffffffffffffffff 80000000000000008000000000000000 00000000000000000000000000000000
+r pcmpgtq 0000000000000000ffffffffffffffff 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+m pcmpgtq 0000000000000000ffffffffffffffff 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+r pcmpgtq 0000000000000000ffffffffffffffff fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff
+m pcmpgtq 0000000000000000ffffffffffffffff fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff
+r pcmpgtq 0000000000000000ffffffffffffffff ffffffffffffffff0000000000000000 0000000000000000ffffffffffffffff
+m pcmpgtq 0000000000000000ffffffffffffffff ffffffffffffffff0000000000000000 0000000000000000ffffffffffffffff
+r pcmpgtq 0000000000000001fffffffffffffffe 0000000000000000ffffffffffffffff 0000000000000000ffffffffffffffff
+m pcmpgtq 0000000000000001fffffffffffffffe 0000000000000000ffffffffffffffff 0000000000000000ffffffffffffffff
+r pcmpgtq 0000000000000001fffffffffffffffe 0000000000000001fffffffffffffffe 00000000000000000000000000000000
+m pcmpgtq 0000000000000001fffffffffffffffe 0000000000000001fffffffffffffffe 00000000000000000000000000000000
+r pcmpgtq 0000000000000001fffffffffffffffe 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+m pcmpgtq 0000000000000001fffffffffffffffe 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+r pcmpgtq 0000000000000001fffffffffffffffe 80000000000000008000000000000000 00000000000000000000000000000000
+m pcmpgtq 0000000000000001fffffffffffffffe 80000000000000008000000000000000 00000000000000000000000000000000
+r pcmpgtq 0000000000000001fffffffffffffffe 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+m pcmpgtq 0000000000000001fffffffffffffffe 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+r pcmpgtq 0000000000000001fffffffffffffffe fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff
+m pcmpgtq 0000000000000001fffffffffffffffe fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff
+r pcmpgtq 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000 0000000000000000ffffffffffffffff
+m pcmpgtq 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000 0000000000000000ffffffffffffffff
+r pcmpgtq 7fffffffffffffff8000000000000001 0000000000000000ffffffffffffffff 0000000000000000ffffffffffffffff
+m pcmpgtq 7fffffffffffffff8000000000000001 0000000000000000ffffffffffffffff 0000000000000000ffffffffffffffff
+r pcmpgtq 7fffffffffffffff8000000000000001 0000000000000001fffffffffffffffe 0000000000000000ffffffffffffffff
+m pcmpgtq 7fffffffffffffff8000000000000001 0000000000000001fffffffffffffffe 0000000000000000ffffffffffffffff
+r pcmpgtq 7fffffffffffffff8000000000000001 7fffffffffffffff8000000000000001 00000000000000000000000000000000
+m pcmpgtq 7fffffffffffffff8000000000000001 7fffffffffffffff8000000000000001 00000000000000000000000000000000
+r pcmpgtq 7fffffffffffffff8000000000000001 80000000000000008000000000000000 00000000000000000000000000000000
+m pcmpgtq 7fffffffffffffff8000000000000001 80000000000000008000000000000000 00000000000000000000000000000000
+r pcmpgtq 7fffffffffffffff8000000000000001 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+m pcmpgtq 7fffffffffffffff8000000000000001 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+r pcmpgtq 7fffffffffffffff8000000000000001 fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff
+m pcmpgtq 7fffffffffffffff8000000000000001 fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff
+r pcmpgtq 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000 0000000000000000ffffffffffffffff
+m pcmpgtq 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000 0000000000000000ffffffffffffffff
+r pcmpgtq 80000000000000008000000000000000 0000000000000000ffffffffffffffff ffffffffffffffffffffffffffffffff
+m pcmpgtq 80000000000000008000000000000000 0000000000000000ffffffffffffffff ffffffffffffffffffffffffffffffff
+r pcmpgtq 80000000000000008000000000000000 0000000000000001fffffffffffffffe ffffffffffffffffffffffffffffffff
+m pcmpgtq 80000000000000008000000000000000 0000000000000001fffffffffffffffe ffffffffffffffffffffffffffffffff
+r pcmpgtq 80000000000000008000000000000000 7fffffffffffffff8000000000000001 ffffffffffffffffffffffffffffffff
+m pcmpgtq 80000000000000008000000000000000 7fffffffffffffff8000000000000001 ffffffffffffffffffffffffffffffff
+r pcmpgtq 80000000000000008000000000000000 80000000000000008000000000000000 00000000000000000000000000000000
+m pcmpgtq 80000000000000008000000000000000 80000000000000008000000000000000 00000000000000000000000000000000
+r pcmpgtq 80000000000000008000000000000000 80000000000000017fffffffffffffff ffffffffffffffffffffffffffffffff
+m pcmpgtq 80000000000000008000000000000000 80000000000000017fffffffffffffff ffffffffffffffffffffffffffffffff
+r pcmpgtq 80000000000000008000000000000000 fffffffffffffffe0000000000000001 ffffffffffffffffffffffffffffffff
+m pcmpgtq 80000000000000008000000000000000 fffffffffffffffe0000000000000001 ffffffffffffffffffffffffffffffff
+r pcmpgtq 80000000000000008000000000000000 ffffffffffffffff0000000000000000 ffffffffffffffffffffffffffffffff
+m pcmpgtq 80000000000000008000000000000000 ffffffffffffffff0000000000000000 ffffffffffffffffffffffffffffffff
+r pcmpgtq 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff ffffffffffffffff0000000000000000
+m pcmpgtq 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff ffffffffffffffff0000000000000000
+r pcmpgtq 80000000000000017fffffffffffffff 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000
+m pcmpgtq 80000000000000017fffffffffffffff 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000
+r pcmpgtq 80000000000000017fffffffffffffff 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+m pcmpgtq 80000000000000017fffffffffffffff 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+r pcmpgtq 80000000000000017fffffffffffffff 80000000000000008000000000000000 00000000000000000000000000000000
+m pcmpgtq 80000000000000017fffffffffffffff 80000000000000008000000000000000 00000000000000000000000000000000
+r pcmpgtq 80000000000000017fffffffffffffff 80000000000000017fffffffffffffff 00000000000000000000000000000000
+m pcmpgtq 80000000000000017fffffffffffffff 80000000000000017fffffffffffffff 00000000000000000000000000000000
+r pcmpgtq 80000000000000017fffffffffffffff fffffffffffffffe0000000000000001 ffffffffffffffff0000000000000000
+m pcmpgtq 80000000000000017fffffffffffffff fffffffffffffffe0000000000000001 ffffffffffffffff0000000000000000
+r pcmpgtq 80000000000000017fffffffffffffff ffffffffffffffff0000000000000000 ffffffffffffffff0000000000000000
+m pcmpgtq 80000000000000017fffffffffffffff ffffffffffffffff0000000000000000 ffffffffffffffff0000000000000000
+r pcmpgtq fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff ffffffffffffffff0000000000000000
+m pcmpgtq fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff ffffffffffffffff0000000000000000
+r pcmpgtq fffffffffffffffe0000000000000001 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000
+m pcmpgtq fffffffffffffffe0000000000000001 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000
+r pcmpgtq fffffffffffffffe0000000000000001 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+m pcmpgtq fffffffffffffffe0000000000000001 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+r pcmpgtq fffffffffffffffe0000000000000001 80000000000000008000000000000000 00000000000000000000000000000000
+m pcmpgtq fffffffffffffffe0000000000000001 80000000000000008000000000000000 00000000000000000000000000000000
+r pcmpgtq fffffffffffffffe0000000000000001 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+m pcmpgtq fffffffffffffffe0000000000000001 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+r pcmpgtq fffffffffffffffe0000000000000001 fffffffffffffffe0000000000000001 00000000000000000000000000000000
+m pcmpgtq fffffffffffffffe0000000000000001 fffffffffffffffe0000000000000001 00000000000000000000000000000000
+r pcmpgtq fffffffffffffffe0000000000000001 ffffffffffffffff0000000000000000 ffffffffffffffff0000000000000000
+m pcmpgtq fffffffffffffffe0000000000000001 ffffffffffffffff0000000000000000 ffffffffffffffff0000000000000000
+r pcmpgtq ffffffffffffffff0000000000000000 0000000000000000ffffffffffffffff ffffffffffffffff0000000000000000
+m pcmpgtq ffffffffffffffff0000000000000000 0000000000000000ffffffffffffffff ffffffffffffffff0000000000000000
+r pcmpgtq ffffffffffffffff0000000000000000 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000
+m pcmpgtq ffffffffffffffff0000000000000000 0000000000000001fffffffffffffffe ffffffffffffffff0000000000000000
+r pcmpgtq ffffffffffffffff0000000000000000 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+m pcmpgtq ffffffffffffffff0000000000000000 7fffffffffffffff8000000000000001 ffffffffffffffff0000000000000000
+r pcmpgtq ffffffffffffffff0000000000000000 80000000000000008000000000000000 00000000000000000000000000000000
+m pcmpgtq ffffffffffffffff0000000000000000 80000000000000008000000000000000 00000000000000000000000000000000
+r pcmpgtq ffffffffffffffff0000000000000000 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+m pcmpgtq ffffffffffffffff0000000000000000 80000000000000017fffffffffffffff 0000000000000000ffffffffffffffff
+r pcmpgtq ffffffffffffffff0000000000000000 fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff
+m pcmpgtq ffffffffffffffff0000000000000000 fffffffffffffffe0000000000000001 0000000000000000ffffffffffffffff
+r pcmpgtq ffffffffffffffff0000000000000000 ffffffffffffffff0000000000000000 00000000000000000000000000000000
+m pcmpgtq ffffffffffffffff0000000000000000 ffffffffffffffff0000000000000000 00000000000000000000000000000000
+r packusdw 53bb728e020c15a5c22982db4a24e5a7 d9ae1386622d3d7a2db15a13bf7970b0 ffffffff0000ffff0000ffffffff0000
+m packusdw 53bb728e020c15a5c22982db4a24e5a7 d9ae1386622d3d7a2db15a13bf7970b0 ffffffff0000ffff0000ffffffff0000
+r packusdw a1bcb4ea56fa55737eac60eb8aded33c c43f261642363414e2c3f191206475a2 0000ffffffff00000000ffff0000ffff
+m packusdw a1bcb4ea56fa55737eac60eb8aded33c c43f261642363414e2c3f191206475a2 0000ffffffff00000000ffff0000ffff
+r packusdw 3ef118c86a00924363014f93d37d9f97 eceb191ff1dc0745eece99ded8fa7731 ffffffffffff00000000000000000000
+m packusdw 3ef118c86a00924363014f93d37d9f97 eceb191ff1dc0745eece99ded8fa7731 ffffffffffff00000000000000000000
+r packusdw 88a79996daaa09c04df3cdbf420d06e5 aefee70d0aabf1ba2d9ccce404463289 00000000ffffffff0000ffffffffffff
+m packusdw 88a79996daaa09c04df3cdbf420d06e5 aefee70d0aabf1ba2d9ccce404463289 00000000ffffffff0000ffffffffffff
+r packusdw d92a33bf4382f6971850565bf298c352 66c48c4b2a302f1e7bfa0890c05462d6 0000ffffffff0000ffffffffffff0000
+m packusdw d92a33bf4382f6971850565bf298c352 66c48c4b2a302f1e7bfa0890c05462d6 0000ffffffff0000ffffffffffff0000
+r packusdw 8fc5e2af41169474a0e26453002c9409 70880548ecf6fd1eb4b3c8cf2731c242 0000ffff0000ffffffff00000000ffff
+m packusdw 8fc5e2af41169474a0e26453002c9409 70880548ecf6fd1eb4b3c8cf2731c242 0000ffff0000ffffffff00000000ffff
+r packusdw 04c6a3d26ff12002c176759387d43337 28984c6ded8a9666b495898c55e80ffc ffffffff00000000ffff00000000ffff
+m packusdw 04c6a3d26ff12002c176759387d43337 28984c6ded8a9666b495898c55e80ffc ffffffff00000000ffff00000000ffff
+r packusdw 9677719469a0d6ee57d80407a49d5d07 ea3e5f27c87637a1566ac5b36785042e 0000ffffffff000000000000ffffffff
+m packusdw 9677719469a0d6ee57d80407a49d5d07 ea3e5f27c87637a1566ac5b36785042e 0000ffffffff000000000000ffffffff
+r packusdw 9f264862ccaef2e43ed48d9c7292cda6 11c739e219481c7c7800fa3079155f05 00000000ffffffffffffffffffffffff
+m packusdw 9f264862ccaef2e43ed48d9c7292cda6 11c739e219481c7c7800fa3079155f05 00000000ffffffffffffffffffffffff
+r packusdw 00008877000066550000443300002211 0000b2a10000ffee0000ddcc0000bbaa 8877665544332211b2a1ffeeddccbbaa
+m packusdw 00008877000066550000443300002211 0000b2a10000ffee0000ddcc0000bbaa 8877665544332211b2a1ffeeddccbbaa
diff --git a/main/none/tests/arm/Makefile.am b/main/none/tests/arm/Makefile.am
index ffa52bd..418ad0a 100644
--- a/main/none/tests/arm/Makefile.am
+++ b/main/none/tests/arm/Makefile.am
@@ -9,20 +9,26 @@
v6intARM.stdout.exp v6intARM.stderr.exp v6intARM.vgtest \
v6intThumb.stdout.exp v6intThumb.stderr.exp v6intThumb.vgtest \
v6media.stdout.exp v6media.stderr.exp v6media.vgtest \
+ vcvt_fixed_float_VFP.stdout.exp vcvt_fixed_float_VFP.stderr.exp \
+ vcvt_fixed_float_VFP.vgtest \
vfp.stdout.exp vfp.stderr.exp vfp.vgtest
check_PROGRAMS = \
+ allexec \
neon128 \
neon64 \
v6intARM \
v6intThumb \
v6media \
+ vcvt_fixed_float_VFP \
vfp
AM_CFLAGS += @FLAG_M32@
AM_CXXFLAGS += @FLAG_M32@
AM_CCASFLAGS += @FLAG_M32@
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+
# These two are specific to their ARM/Thumb respectively and so we
# hardwire -marm/-mthumb. neon64 and neon128 are compilable on both,
# however, ask for them to be compiled on thumb, as that looks
@@ -36,14 +42,14 @@
v6media_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
vfp_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
- -mfpu=neon -mfloat-abi=softfp \
+ -mfpu=neon \
-mthumb
neon128_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
- -mfpu=neon -mfloat-abi=softfp \
+ -mfpu=neon \
-mthumb
neon64_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
- -mfpu=neon -mfloat-abi=softfp \
+ -mfpu=neon \
-mthumb
diff --git a/main/none/tests/arm/Makefile.in b/main/none/tests/arm/Makefile.in
new file mode 100644
index 0000000..5dff4ef
--- /dev/null
+++ b/main/none/tests/arm/Makefile.in
@@ -0,0 +1,892 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = allexec$(EXEEXT) neon128$(EXEEXT) neon64$(EXEEXT) \
+ v6intARM$(EXEEXT) v6intThumb$(EXEEXT) v6media$(EXEEXT) \
+ vcvt_fixed_float_VFP$(EXEEXT) vfp$(EXEEXT)
+subdir = none/tests/arm
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+neon128_SOURCES = neon128.c
+neon128_OBJECTS = neon128-neon128.$(OBJEXT)
+neon128_LDADD = $(LDADD)
+neon128_LINK = $(CCLD) $(neon128_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+neon64_SOURCES = neon64.c
+neon64_OBJECTS = neon64-neon64.$(OBJEXT)
+neon64_LDADD = $(LDADD)
+neon64_LINK = $(CCLD) $(neon64_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v6intARM_SOURCES = v6intARM.c
+v6intARM_OBJECTS = v6intARM-v6intARM.$(OBJEXT)
+v6intARM_LDADD = $(LDADD)
+v6intARM_LINK = $(CCLD) $(v6intARM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v6intThumb_SOURCES = v6intThumb.c
+v6intThumb_OBJECTS = v6intThumb-v6intThumb.$(OBJEXT)
+v6intThumb_LDADD = $(LDADD)
+v6intThumb_LINK = $(CCLD) $(v6intThumb_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v6media_SOURCES = v6media.c
+v6media_OBJECTS = v6media-v6media.$(OBJEXT)
+v6media_LDADD = $(LDADD)
+v6media_LINK = $(CCLD) $(v6media_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+vcvt_fixed_float_VFP_SOURCES = vcvt_fixed_float_VFP.c
+vcvt_fixed_float_VFP_OBJECTS = vcvt_fixed_float_VFP.$(OBJEXT)
+vcvt_fixed_float_VFP_LDADD = $(LDADD)
+vfp_SOURCES = vfp.c
+vfp_OBJECTS = vfp-vfp.$(OBJEXT)
+vfp_LDADD = $(LDADD)
+vfp_LINK = $(CCLD) $(vfp_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o \
+ $@
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = allexec.c neon128.c neon64.c v6intARM.c v6intThumb.c \
+ v6media.c vcvt_fixed_float_VFP.c vfp.c
+DIST_SOURCES = allexec.c neon128.c neon64.c v6intARM.c v6intThumb.c \
+ v6media.c vcvt_fixed_float_VFP.c vfp.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ neon128.stdout.exp neon128.stderr.exp neon128.vgtest \
+ neon64.stdout.exp neon64.stderr.exp neon64.vgtest \
+ v6intARM.stdout.exp v6intARM.stderr.exp v6intARM.vgtest \
+ v6intThumb.stdout.exp v6intThumb.stderr.exp v6intThumb.vgtest \
+ v6media.stdout.exp v6media.stderr.exp v6media.vgtest \
+ vcvt_fixed_float_VFP.stdout.exp vcvt_fixed_float_VFP.stderr.exp \
+ vcvt_fixed_float_VFP.vgtest \
+ vfp.stdout.exp vfp.stderr.exp vfp.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+
+# These two are specific to their ARM/Thumb respectively and so we
+# hardwire -marm/-mthumb. neon64 and neon128 are compilable on both,
+# however, ask for them to be compiled on thumb, as that looks
+# like that's going to be the more common use case. They also
+# need special helping w.r.t -mfpu and -mfloat-abi, though.
+# Also force -O0 since -O takes hundreds of MB of memory
+# for v6intThumb.c.
+v6intARM_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -marm
+v6intThumb_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
+v6media_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
+vfp_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+ -mfpu=neon \
+ -mthumb
+
+neon128_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+ -mfpu=neon \
+ -mthumb
+
+neon64_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+ -mfpu=neon \
+ -mthumb
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/arm/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/arm/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+neon128$(EXEEXT): $(neon128_OBJECTS) $(neon128_DEPENDENCIES)
+ @rm -f neon128$(EXEEXT)
+ $(neon128_LINK) $(neon128_OBJECTS) $(neon128_LDADD) $(LIBS)
+neon64$(EXEEXT): $(neon64_OBJECTS) $(neon64_DEPENDENCIES)
+ @rm -f neon64$(EXEEXT)
+ $(neon64_LINK) $(neon64_OBJECTS) $(neon64_LDADD) $(LIBS)
+v6intARM$(EXEEXT): $(v6intARM_OBJECTS) $(v6intARM_DEPENDENCIES)
+ @rm -f v6intARM$(EXEEXT)
+ $(v6intARM_LINK) $(v6intARM_OBJECTS) $(v6intARM_LDADD) $(LIBS)
+v6intThumb$(EXEEXT): $(v6intThumb_OBJECTS) $(v6intThumb_DEPENDENCIES)
+ @rm -f v6intThumb$(EXEEXT)
+ $(v6intThumb_LINK) $(v6intThumb_OBJECTS) $(v6intThumb_LDADD) $(LIBS)
+v6media$(EXEEXT): $(v6media_OBJECTS) $(v6media_DEPENDENCIES)
+ @rm -f v6media$(EXEEXT)
+ $(v6media_LINK) $(v6media_OBJECTS) $(v6media_LDADD) $(LIBS)
+vcvt_fixed_float_VFP$(EXEEXT): $(vcvt_fixed_float_VFP_OBJECTS) $(vcvt_fixed_float_VFP_DEPENDENCIES)
+ @rm -f vcvt_fixed_float_VFP$(EXEEXT)
+ $(LINK) $(vcvt_fixed_float_VFP_OBJECTS) $(vcvt_fixed_float_VFP_LDADD) $(LIBS)
+vfp$(EXEEXT): $(vfp_OBJECTS) $(vfp_DEPENDENCIES)
+ @rm -f vfp$(EXEEXT)
+ $(vfp_LINK) $(vfp_OBJECTS) $(vfp_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/neon128-neon128.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/neon64-neon64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v6intARM-v6intARM.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v6intThumb-v6intThumb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v6media-v6media.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vcvt_fixed_float_VFP.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vfp-vfp.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+allexec-allexec.o: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.o -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+
+allexec-allexec.obj: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.obj -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+
+neon128-neon128.o: neon128.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon128_CFLAGS) $(CFLAGS) -MT neon128-neon128.o -MD -MP -MF $(DEPDIR)/neon128-neon128.Tpo -c -o neon128-neon128.o `test -f 'neon128.c' || echo '$(srcdir)/'`neon128.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/neon128-neon128.Tpo $(DEPDIR)/neon128-neon128.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='neon128.c' object='neon128-neon128.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon128_CFLAGS) $(CFLAGS) -c -o neon128-neon128.o `test -f 'neon128.c' || echo '$(srcdir)/'`neon128.c
+
+neon128-neon128.obj: neon128.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon128_CFLAGS) $(CFLAGS) -MT neon128-neon128.obj -MD -MP -MF $(DEPDIR)/neon128-neon128.Tpo -c -o neon128-neon128.obj `if test -f 'neon128.c'; then $(CYGPATH_W) 'neon128.c'; else $(CYGPATH_W) '$(srcdir)/neon128.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/neon128-neon128.Tpo $(DEPDIR)/neon128-neon128.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='neon128.c' object='neon128-neon128.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon128_CFLAGS) $(CFLAGS) -c -o neon128-neon128.obj `if test -f 'neon128.c'; then $(CYGPATH_W) 'neon128.c'; else $(CYGPATH_W) '$(srcdir)/neon128.c'; fi`
+
+neon64-neon64.o: neon64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon64_CFLAGS) $(CFLAGS) -MT neon64-neon64.o -MD -MP -MF $(DEPDIR)/neon64-neon64.Tpo -c -o neon64-neon64.o `test -f 'neon64.c' || echo '$(srcdir)/'`neon64.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/neon64-neon64.Tpo $(DEPDIR)/neon64-neon64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='neon64.c' object='neon64-neon64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon64_CFLAGS) $(CFLAGS) -c -o neon64-neon64.o `test -f 'neon64.c' || echo '$(srcdir)/'`neon64.c
+
+neon64-neon64.obj: neon64.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon64_CFLAGS) $(CFLAGS) -MT neon64-neon64.obj -MD -MP -MF $(DEPDIR)/neon64-neon64.Tpo -c -o neon64-neon64.obj `if test -f 'neon64.c'; then $(CYGPATH_W) 'neon64.c'; else $(CYGPATH_W) '$(srcdir)/neon64.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/neon64-neon64.Tpo $(DEPDIR)/neon64-neon64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='neon64.c' object='neon64-neon64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon64_CFLAGS) $(CFLAGS) -c -o neon64-neon64.obj `if test -f 'neon64.c'; then $(CYGPATH_W) 'neon64.c'; else $(CYGPATH_W) '$(srcdir)/neon64.c'; fi`
+
+v6intARM-v6intARM.o: v6intARM.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intARM_CFLAGS) $(CFLAGS) -MT v6intARM-v6intARM.o -MD -MP -MF $(DEPDIR)/v6intARM-v6intARM.Tpo -c -o v6intARM-v6intARM.o `test -f 'v6intARM.c' || echo '$(srcdir)/'`v6intARM.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/v6intARM-v6intARM.Tpo $(DEPDIR)/v6intARM-v6intARM.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='v6intARM.c' object='v6intARM-v6intARM.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intARM_CFLAGS) $(CFLAGS) -c -o v6intARM-v6intARM.o `test -f 'v6intARM.c' || echo '$(srcdir)/'`v6intARM.c
+
+v6intARM-v6intARM.obj: v6intARM.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intARM_CFLAGS) $(CFLAGS) -MT v6intARM-v6intARM.obj -MD -MP -MF $(DEPDIR)/v6intARM-v6intARM.Tpo -c -o v6intARM-v6intARM.obj `if test -f 'v6intARM.c'; then $(CYGPATH_W) 'v6intARM.c'; else $(CYGPATH_W) '$(srcdir)/v6intARM.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/v6intARM-v6intARM.Tpo $(DEPDIR)/v6intARM-v6intARM.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='v6intARM.c' object='v6intARM-v6intARM.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intARM_CFLAGS) $(CFLAGS) -c -o v6intARM-v6intARM.obj `if test -f 'v6intARM.c'; then $(CYGPATH_W) 'v6intARM.c'; else $(CYGPATH_W) '$(srcdir)/v6intARM.c'; fi`
+
+v6intThumb-v6intThumb.o: v6intThumb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intThumb_CFLAGS) $(CFLAGS) -MT v6intThumb-v6intThumb.o -MD -MP -MF $(DEPDIR)/v6intThumb-v6intThumb.Tpo -c -o v6intThumb-v6intThumb.o `test -f 'v6intThumb.c' || echo '$(srcdir)/'`v6intThumb.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/v6intThumb-v6intThumb.Tpo $(DEPDIR)/v6intThumb-v6intThumb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='v6intThumb.c' object='v6intThumb-v6intThumb.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intThumb_CFLAGS) $(CFLAGS) -c -o v6intThumb-v6intThumb.o `test -f 'v6intThumb.c' || echo '$(srcdir)/'`v6intThumb.c
+
+v6intThumb-v6intThumb.obj: v6intThumb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intThumb_CFLAGS) $(CFLAGS) -MT v6intThumb-v6intThumb.obj -MD -MP -MF $(DEPDIR)/v6intThumb-v6intThumb.Tpo -c -o v6intThumb-v6intThumb.obj `if test -f 'v6intThumb.c'; then $(CYGPATH_W) 'v6intThumb.c'; else $(CYGPATH_W) '$(srcdir)/v6intThumb.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/v6intThumb-v6intThumb.Tpo $(DEPDIR)/v6intThumb-v6intThumb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='v6intThumb.c' object='v6intThumb-v6intThumb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intThumb_CFLAGS) $(CFLAGS) -c -o v6intThumb-v6intThumb.obj `if test -f 'v6intThumb.c'; then $(CYGPATH_W) 'v6intThumb.c'; else $(CYGPATH_W) '$(srcdir)/v6intThumb.c'; fi`
+
+v6media-v6media.o: v6media.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6media_CFLAGS) $(CFLAGS) -MT v6media-v6media.o -MD -MP -MF $(DEPDIR)/v6media-v6media.Tpo -c -o v6media-v6media.o `test -f 'v6media.c' || echo '$(srcdir)/'`v6media.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/v6media-v6media.Tpo $(DEPDIR)/v6media-v6media.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='v6media.c' object='v6media-v6media.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6media_CFLAGS) $(CFLAGS) -c -o v6media-v6media.o `test -f 'v6media.c' || echo '$(srcdir)/'`v6media.c
+
+v6media-v6media.obj: v6media.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6media_CFLAGS) $(CFLAGS) -MT v6media-v6media.obj -MD -MP -MF $(DEPDIR)/v6media-v6media.Tpo -c -o v6media-v6media.obj `if test -f 'v6media.c'; then $(CYGPATH_W) 'v6media.c'; else $(CYGPATH_W) '$(srcdir)/v6media.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/v6media-v6media.Tpo $(DEPDIR)/v6media-v6media.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='v6media.c' object='v6media-v6media.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6media_CFLAGS) $(CFLAGS) -c -o v6media-v6media.obj `if test -f 'v6media.c'; then $(CYGPATH_W) 'v6media.c'; else $(CYGPATH_W) '$(srcdir)/v6media.c'; fi`
+
+vfp-vfp.o: vfp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vfp_CFLAGS) $(CFLAGS) -MT vfp-vfp.o -MD -MP -MF $(DEPDIR)/vfp-vfp.Tpo -c -o vfp-vfp.o `test -f 'vfp.c' || echo '$(srcdir)/'`vfp.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vfp-vfp.Tpo $(DEPDIR)/vfp-vfp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vfp.c' object='vfp-vfp.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vfp_CFLAGS) $(CFLAGS) -c -o vfp-vfp.o `test -f 'vfp.c' || echo '$(srcdir)/'`vfp.c
+
+vfp-vfp.obj: vfp.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vfp_CFLAGS) $(CFLAGS) -MT vfp-vfp.obj -MD -MP -MF $(DEPDIR)/vfp-vfp.Tpo -c -o vfp-vfp.obj `if test -f 'vfp.c'; then $(CYGPATH_W) 'vfp.c'; else $(CYGPATH_W) '$(srcdir)/vfp.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/vfp-vfp.Tpo $(DEPDIR)/vfp-vfp.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='vfp.c' object='vfp-vfp.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vfp_CFLAGS) $(CFLAGS) -c -o vfp-vfp.obj `if test -f 'vfp.c'; then $(CYGPATH_W) 'vfp.c'; else $(CYGPATH_W) '$(srcdir)/vfp.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/arm/allexec.c b/main/none/tests/arm/allexec.c
new file mode 100644
index 0000000..b7177e8
--- /dev/null
+++ b/main/none/tests/arm/allexec.c
@@ -0,0 +1,50 @@
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+extern char **environ;
+
+#define S(...) (fprintf(stdout, __VA_ARGS__),fflush(stdout))
+#define FORKEXECWAIT(exec_call) do { \
+ int status;\
+ pid_t child = fork(); \
+ if (child == 0) {exec_call; perror ("exec failed");} \
+ else if (child == -1) perror ("cannot fork\n"); \
+ else if (child != wait (&status)) perror ("error waiting child"); \
+ else S("child exited\n"); \
+ } while (0)
+
+void test_allexec (char *exec)
+{
+ FORKEXECWAIT (execlp(exec, exec, NULL));
+ FORKEXECWAIT (execlp(exec, exec, "constant_arg1", "constant_arg2", NULL));
+ FORKEXECWAIT (execve(exec, NULL, environ));
+}
+
+
+/* If a single argument "exec" is given, will execute itself
+ (in bi-arch, a 32 bit and 64 bit variant) via various exec system calls.
+ Note that this test can only be run after the prerequisite have been
+ prepared by allexec_prepare_prereq, which will a.o. make links
+ for the allexec32 and allexec64 executables. On single arch build,
+ these links points to the same executable to ensure this test works
+ everywhere the same.
+ No arguments or more arguments means just print its args. */
+int main(int argc, char **argv, char **envp)
+{
+ if ( (argc == 2) && (strcmp (argv[1], "exec") == 0)) {
+ S("%s will exec ./allexec32\n", argv[0]);
+ test_allexec ("./allexec32");
+ S("%s will exec ./allexec64\n", argv[0]);
+ test_allexec ("./allexec64");
+ } else {
+ int i;
+ S("program exec-ed:");
+ for (i = 0; i < argc; i++) S(" %s", argv[i]);
+ S("\n");
+ }
+ return 0;
+}
diff --git a/main/none/tests/arm/neon128.c b/main/none/tests/arm/neon128.c
index cfb7d94..401b65d 100644
--- a/main/none/tests/arm/neon128.c
+++ b/main/none/tests/arm/neon128.c
@@ -3252,3096 +3252,3 @@
return 0;
}
-
-/* How to compile:
-
- gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \
- -marm -o neon128-a neon128.c
-
- or
-
- gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \
- -mthumb -o neon128-t neon128.c
-
-*/
-
-#include <stdio.h>
-#include <math.h>
-
-#ifndef __thumb__
-// ARM
-#define MOVE_to_FPSCR_from_R4 \
- ".word 0xEEE14A10 @ vmsr FPSCR, r4\n\t"
-#define MOVE_to_R4_from_FPSCR \
- ".word 0xEEF14A10 @ vmrs r4, FPSCR\n\t"
-#endif
-
-#ifdef __thumb__
-// Thumb
-#define MOVE_to_FPSCR_from_R4 \
- ".word 0x4A10EEE1 @ vmsr FPSCR, r4\n\t"
-#define MOVE_to_R4_from_FPSCR \
- ".word 0x4A10EEF1 @ vmrs r4, FPSCR\n\t"
-#endif
-
-static inline unsigned int f2u(float x) {
- union {
- float f;
- unsigned int u;
- } cvt;
- cvt.f = x;
- return cvt.u;
-}
-
-/* test macros to generate and output the result of a single instruction */
-
-#define TESTINSN_imm(instruction, QD, imm) \
-{ \
- unsigned int out[4]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- instruction ", #" #imm "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out) \
- : #QD, "memory" \
- ); \
- printf("%s, #" #imm " :: Qd 0x%08x 0x%08x 0x%08x 0x%08x\n", \
- instruction, out[3], out[2], out[1], out[0]); \
-}
-
-#define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \
-{ \
- unsigned int out[4]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval) \
- : #QD, #QM, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x\n", \
- instruction, out[3], out[2], out[1], out[0], QMval); \
-}
-
-#define TESTINSN_un_q(instruction, QD, QM, QMtype, QMval) \
-{ \
- unsigned int out[4]; \
- unsigned int fpscr; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "mov r4, #0\n\t" \
- MOVE_to_FPSCR_from_R4 \
- "vdup." #QMtype " " #QM ", %2\n\t" \
- instruction "\n\t" \
- "vstmia %1, {" #QD "}\n\t" \
- MOVE_to_R4_from_FPSCR \
- "mov %0, r4" \
- : "=r" (fpscr) \
- : "r" (out), "r" (QMval) \
- : #QD, #QM, "memory", "r4" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " fpscr: %08x\n", \
- instruction, out[3], out[2], out[1], out[0], QMval, fpscr); \
-}
-
-#define TESTINSN_bin(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out[4]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- "vdup." #QNtype " " #QN ", %2\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval), "r" (QNval) \
- : #QD, #QM, #QN, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn (" #QNtype ")0x%08x\n", \
- instruction, out[3], out[2], out[1], out[0], QMval, QNval); \
-}
-
-#define TESTINSN_bin_f(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out[4]; \
-\
- __asm__ volatile( \
- "vdup.i32 " #QD ", %3\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- "vdup." #QNtype " " #QN ", %2\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval), "r" (QNval), "r" (0x3f800000) \
- : #QD, #QM, #QN, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn (" #QNtype ")0x%08x\n", \
- instruction, out[3], out[2], out[1], out[0], QMval, QNval); \
-}
-
-#define TESTINSN_bin_q(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out[4]; \
- unsigned int fpscr; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "mov r4, #0\n\t" \
- MOVE_to_FPSCR_from_R4 \
- "vdup." #QMtype " " #QM ", %2\n\t" \
- "vdup." #QNtype " " #QN ", %3\n\t" \
- instruction "\n\t" \
- "vstmia %1, {" #QD "}\n\t" \
- MOVE_to_R4_from_FPSCR \
- "mov %0, r4" \
- : "=r" (fpscr) \
- : "r" (out), "r" (QMval), "r" (QNval) \
- : #QD, #QM, #QN, "memory", "r4" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn (" #QNtype ")0x%08x fpscr: %08x\n", \
- instruction, out[3], out[2], out[1], out[0], QMval, QNval, fpscr); \
-}
-
-#define TESTINSN_dual(instruction, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out1[4]; \
- unsigned int out2[4]; \
-\
- __asm__ volatile( \
- "vdup." #QMtype " " #QM ", %2\n\t" \
- "vdup." #QNtype " " #QN ", %3\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QM "}\n\t" \
- "vstmia %1, {" #QN "}\n\t" \
- : \
- : "r" (out1), "r" (out2), "r" (QMval), "r" (QNval) \
- : #QM, #QN, "memory" \
- ); \
- printf("%s :: Qm 0x%08x 0x%08x 0x%08x 0x%08x Qn 0x%08x 0x%08x 0x%08x 0x%08x" \
- " Qm (" #QMtype ")0x%08x Qn (" #QNtype ")0x%08x\n", \
- instruction, out1[3], out1[2], out1[1], out1[0], \
- out2[3], out2[2], out2[1], out2[0], QMval, QNval); \
-}
-
-// Ditto TESTING_bin(), but in QD all zeros
-#define TESTINSN_bin_0s(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out[4]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x00" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- "vdup." #QNtype " " #QN ", %2\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval), "r" (QNval) \
- : #QD, #QM, #QN, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn (" #QNtype ")0x%08x\n", \
- instruction, out[3], out[2], out[1], out[0], QMval, QNval); \
-}
-
-#if 0
-#define TESTINSN_2reg_shift(instruction, QD, QM, QMtype, QMval, imm) \
-{ \
- unsigned int out[4]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- instruction ", #" #imm "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval) \
- : #QD, #QM, "memory" \
- ); \
- printf("%s, #" #imm " :: Qd 0x%08x 0x%08x 0x%08x 0x%08x Qm (" #QMtype ")0x%08x", \
- instruction, out[3], out[2], out[1], out[0], QMval); \
-}
-#endif
-
-int main(int argc, char **argv)
-{
- printf("----- VMOV (immediate) -----\n");
- TESTINSN_imm("vmov.i32 q0", q0, 0x7);
- TESTINSN_imm("vmov.i16 q1", q1, 0x7);
- TESTINSN_imm("vmov.i8 q2", q2, 0x7);
- TESTINSN_imm("vmov.i32 q5", q5, 0x700);
- TESTINSN_imm("vmov.i16 q7", q7, 0x700);
- TESTINSN_imm("vmov.i32 q10", q10, 0x70000);
- TESTINSN_imm("vmov.i32 q12", q12, 0x7000000);
- TESTINSN_imm("vmov.i32 q13", q13, 0x7FF);
- TESTINSN_imm("vmov.i32 q14", q14, 0x7FFFF);
- TESTINSN_imm("vmov.i64 q15", q15, 0xFF0000FF00FFFF00);
-
- printf("----- VMVN (immediate) -----\n");
- TESTINSN_imm("vmvn.i32 q0", q0, 0x7);
- TESTINSN_imm("vmvn.i16 q1", q1, 0x7);
- TESTINSN_imm("vmvn.i8 q2", q2, 0x7);
- TESTINSN_imm("vmvn.i32 q5", q5, 0x700);
- TESTINSN_imm("vmvn.i16 q7", q7, 0x700);
- TESTINSN_imm("vmvn.i32 q10", q10, 0x70000);
- TESTINSN_imm("vmvn.i32 q13", q13, 0x7000000);
- TESTINSN_imm("vmvn.i32 q11", q11, 0x7FF);
- TESTINSN_imm("vmvn.i32 q14", q14, 0x7FFFF);
- TESTINSN_imm("vmvn.i64 q15", q15, 0xFF0000FF00FFFF00);
-
- printf("----- VORR (immediate) -----\n");
- TESTINSN_imm("vorr.i32 q0", q0, 0x7);
- TESTINSN_imm("vorr.i16 q2", q2, 0x7);
- TESTINSN_imm("vorr.i32 q8", q8, 0x700);
- TESTINSN_imm("vorr.i16 q6", q6, 0x700);
- TESTINSN_imm("vorr.i32 q14", q14, 0x70000);
- TESTINSN_imm("vorr.i32 q15", q15, 0x7000000);
-
- printf("----- VBIC (immediate) -----\n");
- TESTINSN_imm("vbic.i32 q0", q0, 0x7);
- TESTINSN_imm("vbic.i16 q3", q3, 0x7);
- TESTINSN_imm("vbic.i32 q5", q5, 0x700);
- TESTINSN_imm("vbic.i16 q8", q8, 0x700);
- TESTINSN_imm("vbic.i32 q10", q10, 0x70000);
- TESTINSN_imm("vbic.i32 q15", q15, 0x7000000);
-
- printf("---- VMVN (register) ----\n");
- TESTINSN_un("vmvn q0, q1", q0, q1, i32, 24);
- TESTINSN_un("vmvn q10, q15", q10, q15, i32, 24);
- TESTINSN_un("vmvn q0, q14", q0, q14, i32, 24);
-
- printf("---- VMOV (register) ----\n");
- TESTINSN_un("vmov q0, q1", q0, q1, i32, 24);
- TESTINSN_un("vmov q10, q15", q10, q15, i32, 24);
- TESTINSN_un("vmov q0, q14", q0, q14, i32, 24);
-
- printf("---- VDUP (ARM core register) (tested indirectly) ----\n");
- TESTINSN_un("vmov q0, q1", q0, q1, i8, 7);
- TESTINSN_un("vmov q10, q11", q10, q11, i16, 7);
- TESTINSN_un("vmov q0, q15", q0, q15, i32, 7);
-
- printf("---- VADD ----\n");
- TESTINSN_bin("vadd.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin("vadd.i64 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vadd.i32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vadd.i16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vadd.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vadd.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vadd.i16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vadd.i32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vadd.i64 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vadd.i32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vadd.i64 q13, q14, q15", q13, q14, i32, 140, q15, i32, 120);
-
- printf("---- VSUB ----\n");
- TESTINSN_bin("vsub.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin("vsub.i64 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vsub.i32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vsub.i16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vsub.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vsub.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vsub.i16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vsub.i32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vsub.i64 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vsub.i32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vsub.i64 q13, q14, q15", q13, q14, i32, 140, q15, i32, 120);
-
- printf("---- VAND ----\n");
- TESTINSN_bin("vand q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
- TESTINSN_bin("vand q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
- TESTINSN_bin("vand q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
- TESTINSN_bin("vand q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
-
- printf("---- VBIC ----\n");
- TESTINSN_bin("vbic q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
- TESTINSN_bin("vbic q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
- TESTINSN_bin("vbic q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
- TESTINSN_bin("vbic q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
-
- printf("---- VORR ----\n");
- TESTINSN_bin("vorr q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
- TESTINSN_bin("vorr q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
- TESTINSN_bin("vorr q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
- TESTINSN_bin("vorr q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
-
- printf("---- VORN ----\n");
- TESTINSN_bin("vorn q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
- TESTINSN_bin("vorn q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
- TESTINSN_bin("vorn q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
- TESTINSN_bin("vorn q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
-
- printf("---- VEOR ----\n");
- TESTINSN_bin("veor q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
- TESTINSN_bin("veor q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
- TESTINSN_bin("veor q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
- TESTINSN_bin("veor q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
- TESTINSN_bin("veor q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
- TESTINSN_bin("veor q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
- TESTINSN_bin("veor q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
- TESTINSN_bin("veor q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
-
- printf("---- VBSL ----\n");
- TESTINSN_bin("vbsl q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
- TESTINSN_bin("vbsl q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
- TESTINSN_bin("vbsl q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
- TESTINSN_bin("vbsl q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
- TESTINSN_bin("vbsl q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
- TESTINSN_bin("vbsl q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
- TESTINSN_bin("vbsl q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
- TESTINSN_bin("vbsl q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
-
- printf("---- VBIT ----\n");
- TESTINSN_bin("vbit q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
- TESTINSN_bin("vbit q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
- TESTINSN_bin("vbit q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
- TESTINSN_bin("vbit q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
- TESTINSN_bin("vbit q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
- TESTINSN_bin("vbit q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
- TESTINSN_bin("vbit q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
- TESTINSN_bin("vbit q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
-
- printf("---- VBIF ----\n");
- TESTINSN_bin("vbif q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
- TESTINSN_bin("vbif q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
- TESTINSN_bin("vbif q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
- TESTINSN_bin("vbif q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
- TESTINSN_bin("vbif q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
- TESTINSN_bin("vbif q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
- TESTINSN_bin("vbif q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
- TESTINSN_bin("vbif q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
-
- printf("---- VEXT ----\n");
- TESTINSN_bin("vext.8 q0, q1, q2, #0", q0, q1, i8, 0x77, q2, i8, 0xff);
- TESTINSN_bin("vext.8 q0, q1, q2, #1", q0, q1, i8, 0x77, q2, i8, 0xff);
- TESTINSN_bin("vext.8 q0, q1, q2, #9", q0, q1, i8, 0x77, q2, i8, 0xff);
- TESTINSN_bin("vext.8 q0, q1, q2, #15", q0, q1, i8, 0x77, q2, i8, 0xff);
- TESTINSN_bin("vext.8 q10, q11, q12, #4", q10, q11, i8, 0x77, q12, i8, 0xff);
- TESTINSN_bin("vext.8 q0, q5, q15, #12", q0, q5, i8, 0x77, q15, i8, 0xff);
-
- printf("---- VHADD ----\n");
- TESTINSN_bin("vhadd.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin("vhadd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhadd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhadd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhadd.s8 q0, q1, q2", q0, q1, i8, 141, q2, i8, 121);
- TESTINSN_bin("vhadd.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vhadd.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin("vhadd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhadd.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhadd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhadd.u8 q0, q1, q2", q0, q1, i8, 141, q2, i8, 121);
- TESTINSN_bin("vhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VHSUB ----\n");
- TESTINSN_bin("vhsub.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin("vhsub.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhsub.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhsub.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhsub.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vhsub.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin("vhsub.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhsub.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhsub.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vhsub.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VQADD ----\n");
- TESTINSN_bin_q("vqadd.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin_q("vqadd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqadd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqadd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqadd.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin_q("vqadd.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin_q("vqadd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqadd.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqadd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VQSUB ----\n");
- TESTINSN_bin_q("vqsub.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin_q("vqsub.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqsub.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqsub.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqsub.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin_q("vqsub.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin_q("vqsub.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqsub.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqsub.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin_q("vqsub.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VRHADD ----\n");
- TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
- TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vrhadd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vrhadd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VCGT ----\n");
- TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
- TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcgt.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcgt.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
- TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
- TESTINSN_bin("vcgt.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
- TESTINSN_bin("vcgt.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 3, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 2, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VCGE ----\n");
- TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
- TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcge.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcge.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
- TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
- TESTINSN_bin("vcge.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
- TESTINSN_bin("vcge.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 3, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 2, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VSHL (register) ----\n");
- TESTINSN_bin("vshl.s8 q0, q1, q2", q0, q1, i32, 24, q2, i32, 1);
- TESTINSN_bin("vshl.s8 q8, q1, q12", q8, q1, i32, 24, q12, i32, 8);
- TESTINSN_bin("vshl.s8 q10, q11, q7", q10, q11, i32, 24, q7, i32, 4);
- TESTINSN_bin("vshl.s16 q3, q8, q11", q3, q8, i32, 14, q11, i32, 2);
- TESTINSN_bin("vshl.s16 q5, q12, q14", q5, q12, i32, (1 << 30), q14, i32, 1);
- TESTINSN_bin("vshl.s16 q15, q2, q1", q15, q2, i32, (1 << 30), q1, i32, 11);
- TESTINSN_bin("vshl.s32 q9, q12, q15", q9, q12, i32, (1 << 31) + 2, q15, i32, 2);
- TESTINSN_bin("vshl.s32 q11, q2, q0", q11, q2, i32, -1, q0, i32, 12);
- TESTINSN_bin("vshl.s32 q5, q2, q3", q5, q2, i32, (1 << 30), q3, i32, 21);
- TESTINSN_bin("vshl.s64 q15, q12, q4", q15, q12, i32, 5, q4, i32, 20);
- TESTINSN_bin("vshl.s64 q8, q2, q4", q8, q2, i32, 15, q4, i32, 4);
- TESTINSN_bin("vshl.s64 q5, q12, q4", q5, q12, i32, (1 << 31) + 1, q4, i32, 30);
- TESTINSN_bin("vshl.u8 q0, q1, q2", q0, q1, i32, 24, q2, i32, 1);
- TESTINSN_bin("vshl.u8 q8, q1, q12", q8, q1, i32, 24, q12, i32, 8);
- TESTINSN_bin("vshl.u8 q10, q11, q7", q10, q11, i32, 24, q7, i32, 4);
- TESTINSN_bin("vshl.u16 q3, q8, q11", q3, q8, i32, 14, q11, i32, 2);
- TESTINSN_bin("vshl.u16 q5, q12, q14", q5, q12, i32, (1 << 30), q14, i32, 1);
- TESTINSN_bin("vshl.u16 q15, q2, q1", q15, q2, i32, (1 << 30), q1, i32, 11);
- TESTINSN_bin("vshl.u32 q9, q12, q15", q9, q12, i32, (1 << 31) + 2, q15, i32, 2);
- TESTINSN_bin("vshl.u32 q11, q2, q0", q11, q2, i32, -1, q0, i32, 12);
- TESTINSN_bin("vshl.u32 q5, q2, q3", q5, q2, i32, (1 << 30), q3, i32, 21);
- TESTINSN_bin("vshl.u64 q15, q12, q4", q15, q12, i32, 5, q4, i32, 20);
- TESTINSN_bin("vshl.u64 q8, q2, q4", q8, q2, i32, 15, q4, i32, 4);
- TESTINSN_bin("vshl.u64 q5, q12, q4", q5, q12, i32, (1 << 31) + 1, q4, i32, 30);
-
- printf("---- VQSHL (register) ----\n");
- TESTINSN_bin_q("vqshl.s64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
- TESTINSN_bin_q("vqshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
- TESTINSN_bin_q("vqshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
- TESTINSN_bin_q("vqshl.s64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
- TESTINSN_bin_q("vqshl.s64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
- TESTINSN_bin_q("vqshl.s64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
- TESTINSN_bin_q("vqshl.s32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
- TESTINSN_bin_q("vqshl.s32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
- TESTINSN_bin_q("vqshl.s32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
- TESTINSN_bin_q("vqshl.s32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
- TESTINSN_bin_q("vqshl.s32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
- TESTINSN_bin_q("vqshl.s32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
- TESTINSN_bin_q("vqshl.s16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
- TESTINSN_bin_q("vqshl.s16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
- TESTINSN_bin_q("vqshl.s16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
- TESTINSN_bin_q("vqshl.s16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
- TESTINSN_bin_q("vqshl.s16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
- TESTINSN_bin_q("vqshl.s16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
- TESTINSN_bin_q("vqshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
- TESTINSN_bin_q("vqshl.s8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
- TESTINSN_bin_q("vqshl.s8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
- TESTINSN_bin_q("vqshl.s8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
- TESTINSN_bin_q("vqshl.s8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
- TESTINSN_bin_q("vqshl.s8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin_q("vqshl.u64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
- TESTINSN_bin_q("vqshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
- TESTINSN_bin_q("vqshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
- TESTINSN_bin_q("vqshl.u64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
- TESTINSN_bin_q("vqshl.u64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
- TESTINSN_bin_q("vqshl.u64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
- TESTINSN_bin_q("vqshl.u32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
- TESTINSN_bin_q("vqshl.u32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
- TESTINSN_bin_q("vqshl.u32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
- TESTINSN_bin_q("vqshl.u32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
- TESTINSN_bin_q("vqshl.u32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
- TESTINSN_bin_q("vqshl.u32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
- TESTINSN_bin_q("vqshl.u16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
- TESTINSN_bin_q("vqshl.u16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
- TESTINSN_bin_q("vqshl.u16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
- TESTINSN_bin_q("vqshl.u16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
- TESTINSN_bin_q("vqshl.u16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
- TESTINSN_bin_q("vqshl.u16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
- TESTINSN_bin_q("vqshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
- TESTINSN_bin_q("vqshl.u8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
- TESTINSN_bin_q("vqshl.u8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
- TESTINSN_bin_q("vqshl.u8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
- TESTINSN_bin_q("vqshl.u8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
- TESTINSN_bin_q("vqshl.u8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VQSHL / VQSHLU (immediate) ----\n");
- TESTINSN_un_q("vqshl.s64 q0, q1, #1", q0, q1, i32, 1);
- TESTINSN_un_q("vqshl.s64 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshl.s64 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshl.s64 q5, q4, #63", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s64 q5, q4, #60", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s64 q5, q4, #59", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s64 q5, q4, #58", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s64 q5, q4, #17", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s64 q5, q4, #63", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.s64 q5, q4, #60", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.s64 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.s32 q10, q11, #1", q10, q11, i32, 1);
- TESTINSN_un_q("vqshl.s32 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshl.s32 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshl.s32 q5, q4, #31", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s32 q5, q4, #28", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s32 q5, q4, #27", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s32 q5, q4, #26", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s32 q5, q4, #17", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s32 q5, q4, #31", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.s32 q5, q4, #29", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.s32 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.s16 q9, q8, #1", q9, q8, i32, 1);
- TESTINSN_un_q("vqshl.s16 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshl.s16 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshl.s16 q9, q8, #15", q9, q8, i32, 16);
- TESTINSN_un_q("vqshl.s16 q5, q4, #12", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s16 q5, q4, #11", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s16 q5, q4, #10", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s16 q5, q4, #4", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s16 q5, q4, #15", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.s16 q5, q4, #12", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.s16 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.s8 q0, q1, #1", q0, q1, i32, 1);
- TESTINSN_un_q("vqshl.s8 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshl.s8 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshl.s8 q5, q4, #7", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s8 q5, q4, #4", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s8 q5, q4, #3", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s8 q5, q4, #2", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s8 q5, q4, #1", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.s8 q5, q4, #7", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.s8 q5, q4, #5", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.s8 q5, q4, #2", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.u64 q0, q1, #1", q0, q1, i32, 1);
- TESTINSN_un_q("vqshl.u64 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshl.u64 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshl.u64 q5, q4, #63", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u64 q5, q4, #60", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u64 q5, q4, #59", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u64 q5, q4, #58", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u64 q5, q4, #17", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u64 q5, q4, #63", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.u64 q5, q4, #60", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.u64 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.u32 q10, q11, #1", q10, q11, i32, 1);
- TESTINSN_un_q("vqshl.u32 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshl.u32 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshl.u32 q5, q4, #31", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u32 q5, q4, #28", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u32 q5, q4, #27", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u32 q5, q4, #26", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u32 q5, q4, #17", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u32 q5, q4, #31", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.u32 q5, q4, #29", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.u32 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.u16 q9, q8, #1", q9, q8, i32, 1);
- TESTINSN_un_q("vqshl.u16 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshl.u16 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshl.u16 q9, q8, #15", q9, q8, i32, 16);
- TESTINSN_un_q("vqshl.u16 q5, q4, #12", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u16 q5, q4, #11", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u16 q5, q4, #10", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u16 q5, q4, #4", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u16 q5, q4, #15", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.u16 q5, q4, #12", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.u16 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.u8 q0, q1, #1", q0, q1, i32, 1);
- TESTINSN_un_q("vqshl.u8 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshl.u8 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshl.u8 q5, q4, #7", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u8 q5, q4, #4", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u8 q5, q4, #3", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u8 q5, q4, #2", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u8 q5, q4, #1", q5, q4, i32, 16);
- TESTINSN_un_q("vqshl.u8 q5, q4, #7", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.u8 q5, q4, #5", q5, q4, i32, -1);
- TESTINSN_un_q("vqshl.u8 q5, q4, #2", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshlu.s64 q0, q1, #1", q0, q1, i32, 1);
- TESTINSN_un_q("vqshlu.s64 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshlu.s64 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshlu.s64 q5, q4, #63", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 q5, q4, #60", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 q5, q4, #59", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 q5, q4, #58", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 q5, q4, #17", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 q5, q4, #63", q5, q4, i32, -1);
- TESTINSN_un_q("vqshlu.s64 q5, q4, #60", q5, q4, i32, -1);
- TESTINSN_un_q("vqshlu.s64 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshlu.s32 q10, q11, #1", q10, q11, i32, 1);
- TESTINSN_un_q("vqshlu.s32 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshlu.s32 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshlu.s32 q5, q4, #31", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s32 q5, q4, #28", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s32 q5, q4, #27", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s32 q5, q4, #26", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s32 q5, q4, #17", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s32 q5, q4, #31", q5, q4, i32, -1);
- TESTINSN_un_q("vqshlu.s32 q5, q4, #29", q5, q4, i32, -1);
- TESTINSN_un_q("vqshlu.s32 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshlu.s16 q9, q8, #1", q9, q8, i32, 1);
- TESTINSN_un_q("vqshlu.s16 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshlu.s16 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshlu.s16 q9, q8, #15", q9, q8, i32, 16);
- TESTINSN_un_q("vqshlu.s16 q5, q4, #12", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s16 q5, q4, #11", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s16 q5, q4, #10", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s16 q5, q4, #4", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s16 q5, q4, #15", q5, q4, i32, -1);
- TESTINSN_un_q("vqshlu.s16 q5, q4, #12", q5, q4, i32, -1);
- TESTINSN_un_q("vqshlu.s16 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshlu.s8 q0, q1, #1", q0, q1, i32, 1);
- TESTINSN_un_q("vqshlu.s8 q15, q14, #1", q15, q14, i32, -127);
- TESTINSN_un_q("vqshlu.s8 q5, q4, #0", q5, q4, i32, -127);
- TESTINSN_un_q("vqshlu.s8 q5, q4, #7", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 q5, q4, #4", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 q5, q4, #3", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 q5, q4, #2", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 q5, q4, #1", q5, q4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 q5, q4, #7", q5, q4, i32, -1);
- TESTINSN_un_q("vqshlu.s8 q5, q4, #5", q5, q4, i32, -1);
- TESTINSN_un_q("vqshlu.s8 q5, q4, #2", q5, q4, i32, (1 << 31) + 2);
-
- printf("---- VQRSHL (register) ----\n");
- TESTINSN_bin_q("vqrshl.s64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
- TESTINSN_bin_q("vqrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
- TESTINSN_bin_q("vqrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
- TESTINSN_bin_q("vqrshl.s64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
- TESTINSN_bin_q("vqrshl.s64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
- TESTINSN_bin_q("vqrshl.s64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
- TESTINSN_bin_q("vqrshl.s32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
- TESTINSN_bin_q("vqrshl.s32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
- TESTINSN_bin_q("vqrshl.s32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
- TESTINSN_bin_q("vqrshl.s32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
- TESTINSN_bin_q("vqrshl.s32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
- TESTINSN_bin_q("vqrshl.s16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
- TESTINSN_bin_q("vqrshl.s16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
- TESTINSN_bin_q("vqrshl.s16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
- TESTINSN_bin_q("vqrshl.s16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
- TESTINSN_bin_q("vqrshl.s16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
- TESTINSN_bin_q("vqrshl.s16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
- TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
- TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
- TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
- TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
- TESTINSN_bin_q("vqrshl.s8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
- TESTINSN_bin_q("vqrshl.s8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
- TESTINSN_bin_q("vqrshl.s8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
- TESTINSN_bin_q("vqrshl.s8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
- TESTINSN_bin_q("vqrshl.s8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin_q("vqrshl.u64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
- TESTINSN_bin_q("vqrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
- TESTINSN_bin_q("vqrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
- TESTINSN_bin_q("vqrshl.u64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
- TESTINSN_bin_q("vqrshl.u64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
- TESTINSN_bin_q("vqrshl.u64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
- TESTINSN_bin_q("vqrshl.u32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
- TESTINSN_bin_q("vqrshl.u32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
- TESTINSN_bin_q("vqrshl.u32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
- TESTINSN_bin_q("vqrshl.u32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
- TESTINSN_bin_q("vqrshl.u32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.u32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
- TESTINSN_bin_q("vqrshl.u16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
- TESTINSN_bin_q("vqrshl.u16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
- TESTINSN_bin_q("vqrshl.u16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
- TESTINSN_bin_q("vqrshl.u16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
- TESTINSN_bin_q("vqrshl.u16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
- TESTINSN_bin_q("vqrshl.u16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
- TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
- TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.u16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.u32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.u16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.u32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
- TESTINSN_bin_q("vqrshl.u16 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
- TESTINSN_bin_q("vqrshl.u32 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
- TESTINSN_bin_q("vqrshl.u8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
- TESTINSN_bin_q("vqrshl.u8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
- TESTINSN_bin_q("vqrshl.u8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
- TESTINSN_bin_q("vqrshl.u8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
- TESTINSN_bin_q("vqrshl.u8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VRSHL (register) ----\n");
- TESTINSN_bin("vrshl.s64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
- TESTINSN_bin("vrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
- TESTINSN_bin("vrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
- TESTINSN_bin("vrshl.s64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
- TESTINSN_bin("vrshl.s64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
- TESTINSN_bin("vrshl.s64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
- TESTINSN_bin("vrshl.s32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
- TESTINSN_bin("vrshl.s32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
- TESTINSN_bin("vrshl.s32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
- TESTINSN_bin("vrshl.s32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
- TESTINSN_bin("vrshl.s32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
- TESTINSN_bin("vrshl.s32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
- TESTINSN_bin("vrshl.s16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
- TESTINSN_bin("vrshl.s16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
- TESTINSN_bin("vrshl.s16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
- TESTINSN_bin("vrshl.s16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
- TESTINSN_bin("vrshl.s16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
- TESTINSN_bin("vrshl.s16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
- TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
- TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
- TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
- TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
- TESTINSN_bin("vrshl.s8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
- TESTINSN_bin("vrshl.s8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
- TESTINSN_bin("vrshl.s8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
- TESTINSN_bin("vrshl.s8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
- TESTINSN_bin("vrshl.s8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vrshl.u64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
- TESTINSN_bin("vrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
- TESTINSN_bin("vrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
- TESTINSN_bin("vrshl.u64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
- TESTINSN_bin("vrshl.u64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
- TESTINSN_bin("vrshl.u64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
- TESTINSN_bin("vrshl.u32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
- TESTINSN_bin("vrshl.u32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
- TESTINSN_bin("vrshl.u32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
- TESTINSN_bin("vrshl.u32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
- TESTINSN_bin("vrshl.u32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
- TESTINSN_bin("vrshl.u32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
- TESTINSN_bin("vrshl.u16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
- TESTINSN_bin("vrshl.u16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
- TESTINSN_bin("vrshl.u16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
- TESTINSN_bin("vrshl.u16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
- TESTINSN_bin("vrshl.u16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
- TESTINSN_bin("vrshl.u16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
- TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
- TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin("vrshl.u16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin("vrshl.u32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
- TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin("vrshl.u16 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin("vrshl.u32 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
- TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin("vrshl.u16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin("vrshl.u32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
- TESTINSN_bin("vrshl.u8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
- TESTINSN_bin("vrshl.u8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
- TESTINSN_bin("vrshl.u8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
- TESTINSN_bin("vrshl.u8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
- TESTINSN_bin("vrshl.u8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VMAX (integer) ----\n");
- TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
- TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 121);
- TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vmax.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vmax.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 120);
- TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VMIN (integer) ----\n");
- TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
- TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 121);
- TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vmin.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vmin.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 120);
- TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
- TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
- TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VABD ----\n");
- TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
- TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, -120);
- TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vabd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200);
- TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, -140, q2, i32, 120);
- TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vabd.u8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200);
- TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VABA ----\n");
- TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
- TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vaba.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200);
- TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
- TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
- TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vaba.u8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200);
- TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VABAL ----\n");
- TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabal.s8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200);
- TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.s32 q10, d31, d12", q10, d31, i32, 24, d12, i32, 120);
- TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabal.u8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.u8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200);
- TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabal.u32 q10, d11, d12", q10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VABDL ----\n");
- TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabdl.s8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200);
- TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.s32 q10, d31, d12", q10, d31, i32, 24, d12, i32, 120);
- TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabdl.u8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.u8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200);
- TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabdl.u32 q10, d11, d12", q10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VTST ----\n");
- TESTINSN_bin("vtst.32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin("vtst.32 q3, q4, q5", q3, q4, i32, 140, q5, i32, 120);
- TESTINSN_bin("vtst.16 q6, q7, q8", q6, q7, i32, 120, q8, i32, 120);
- TESTINSN_bin("vtst.8 q9, q10, q12", q9, q10, i32, 140, q12, i32, 120);
- TESTINSN_bin("vtst.8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vtst.16 q0, q1, q2", q0, q1, i32, (1 << 14) + 1, q2, i32, (1 << 14) + 1);
- TESTINSN_bin("vtst.32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vtst.8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, 2);
- TESTINSN_bin("vtst.16 q0, q1, q2", q0, q1, i32, (1 << 14) + 1, q2, i32, (1 << 14) + 1);
- TESTINSN_bin("vtst.32 q0, q1, q2", q0, q1, i32, 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vtst.32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VCEQ ----\n");
- TESTINSN_bin("vceq.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin("vceq.i32 q3, q4, q5", q3, q4, i32, 140, q5, i32, 120);
- TESTINSN_bin("vceq.i16 q6, q7, q8", q6, q7, i32, 120, q8, i32, 120);
- TESTINSN_bin("vceq.i8 q9, q10, q12", q9, q10, i32, 140, q12, i32, 120);
- TESTINSN_bin("vceq.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vceq.i16 q0, q1, q2", q0, q1, i32, (1 << 14) + 1, q2, i32, (1 << 14) + 1);
- TESTINSN_bin("vceq.i32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vceq.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, 2);
- TESTINSN_bin("vceq.i16 q0, q1, q2", q0, q1, i32, 1, q2, i32, (1 << 14) + 1);
- TESTINSN_bin("vceq.i32 q0, q1, q2", q0, q1, i32, 1, q2, i32, (1 << 31) + 2);
- TESTINSN_bin("vceq.i32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
-
- printf("---- VMLA ----\n");
- TESTINSN_bin("vmla.i32 q0, q1, q2", q0, q1, i32, -24, q2, i32, 120);
- TESTINSN_bin("vmla.i32 q6, q7, q8", q6, q7, i32, 140, q8, i32, 120);
- TESTINSN_bin("vmla.i16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
- TESTINSN_bin("vmla.i16 q7, q1, q2", q7, q1, i32, 0x140, q2, i32, 0x120);
- TESTINSN_bin("vmla.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, -120);
- TESTINSN_bin("vmla.i8 q10, q11, q12", q10, q11, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmla.i16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i16 q14, q5, q9", q14, q5, i32, (1 << 14) + 1, q9, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmla.i8 q10, q13, q12", q10, q13, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmla.i16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmla.i32 q10, q11, q15", q10, q11, i32, 24, q15, i32, -120);
-
- printf("---- VMLS ----\n");
- TESTINSN_bin("vmls.i32 q0, q1, q2", q0, q1, i32, -24, q2, i32, 120);
- TESTINSN_bin("vmls.i32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120);
- TESTINSN_bin("vmls.i16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
- TESTINSN_bin("vmls.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vmls.i8 q10, q11, q12", q10, q11, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmls.i16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmls.i8 q10, q13, q12", q10, q13, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmls.i16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmls.i32 q10, q11, q15", q10, q11, i32, -24, q15, i32, 120);
-
- printf("---- VMUL ----\n");
- TESTINSN_bin("vmul.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin("vmul.i32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120);
- TESTINSN_bin("vmul.i16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
- TESTINSN_bin("vmul.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
- TESTINSN_bin("vmul.i8 q10, q11, q12", q10, q11, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmul.i16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmul.i8 q10, q11, q12", q10, q11, i32, (1 << 25) + 0xfeb2, q12, i32, (1 << 13) + 0xdf);
- TESTINSN_bin("vmul.i16 q4, q5, q6", q4, q5, i32, (1 << 14) - 0xabcd, q6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 q7, q8, q9", q7, q8, i32, (1 << 31), q9, i32, 12);
- TESTINSN_bin("vmul.i8 q10, q13, q12", q10, q13, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmul.i16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmul.i32 q10, q11, q15", q10, q11, i32, 24, q15, i32, 120);
- TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 3, q2, i32, 3);
- TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 12, q2, i8, 0x0f);
-
- printf("---- VMUL (by scalar) ----\n");
- TESTINSN_bin("vmul.i32 q0, q1, d4[0]", q0, q1, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmul.i32 q15, q8, d7[1]", q15, q8, i32, 140, d4, i32, -120);
- TESTINSN_bin("vmul.i16 q10, q9, d7[3]", q10, q9, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmul.i16 q4, q5, d6[2]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmul.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmul.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
-
- printf("---- VMLA (by scalar) ----\n");
- TESTINSN_bin("vmla.i32 q0, q1, d4[0]", q0, q1, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmla.i32 q15, q8, d7[1]", q15, q8, i32, 140, d7, i32, -120);
- TESTINSN_bin("vmla.i16 q10, q9, d7[3]", q10, q9, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmla.i16 q4, q5, d6[2]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmla.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmla.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
-
- printf("---- VMLS (by scalar) ----\n");
- TESTINSN_bin("vmls.i32 q0, q1, d4[0]", q0, q1, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmls.i32 q15, q8, d7[1]", q15, q8, i32, 140, d7, i32, -120);
- TESTINSN_bin("vmls.i16 q10, q9, d7[3]", q10, q9, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmls.i16 q4, q5, d6[2]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmls.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmls.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
-
- printf("---- VMULL (by scalar) ----\n");
- TESTINSN_bin("vmull.s32 q0, d2, d4[0]", q0, d2, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmull.s32 q15, d8, d7[1]", q15, d8, i32, 140, d7, i32, -120);
- TESTINSN_bin("vmull.s16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmull.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.s32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmull.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmull.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
- TESTINSN_bin("vmull.u32 q0, d1, d4[0]", q0, d1, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmull.u32 q15, d8, d7[1]", q15, d8, i32, 140, d4, i32, -120);
- TESTINSN_bin("vmull.u16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmull.u16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.u32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmull.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmull.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
-
- printf("---- VMLAL (by scalar) ----\n");
- TESTINSN_bin("vmlal.s32 q0, d2, d4[0]", q0, d2, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmlal.s32 q15, d8, d7[1]", q15, d8, i32, 140, d7, i32, -120);
- TESTINSN_bin("vmlal.s16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmlal.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.s32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlal.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmlal.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlal.u32 q0, d1, d4[0]", q0, d1, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmlal.u32 q15, d8, d7[1]", q15, d8, i32, 140, d4, i32, -120);
- TESTINSN_bin("vmlal.u16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmlal.u16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.u32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlal.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmlal.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
-
- printf("---- VMLSL (by scalar) ----\n");
- TESTINSN_bin("vmlsl.s32 q0, d2, d4[0]", q0, d2, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmlsl.s32 q15, d8, d7[1]", q15, d8, i32, 140, d7, i32, -120);
- TESTINSN_bin("vmlsl.s16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmlsl.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.s32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlsl.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmlsl.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlsl.u32 q0, d1, d4[0]", q0, d1, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmlsl.u32 q15, d8, d7[1]", q15, d8, i32, 140, d4, i32, -120);
- TESTINSN_bin("vmlsl.u16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmlsl.u16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.u32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlsl.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmlsl.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
-
- printf("---- VRSHR ----\n");
- TESTINSN_un("vrshr.s8 q0, q1, #0", q0, q1, i32, -1);
- TESTINSN_un("vrshr.s8 q0, q1, #1", q0, q1, i32, -1);
- TESTINSN_un("vrshr.s16 q3, q4, #2", q3, q4, i32, -0x7c);
- TESTINSN_un("vrshr.s32 q2, q5, #31", q2, q5, i32, -1);
- TESTINSN_un("vrshr.s8 q6, q7, #7", q6, q7, i32, 0xffff);
- TESTINSN_un("vrshr.s16 q8, q9, #12", q8, q9, i32, -10);
- TESTINSN_un("vrshr.s32 q10, q11, #5", q10, q11, i32, 10234);
- TESTINSN_un("vrshr.u8 q12, q13, #1", q12, q13, i32, -1);
- TESTINSN_un("vrshr.u16 q14, q15, #11", q14, q15, i32, -1);
- TESTINSN_un("vrshr.u32 q10, q11, #9", q10, q11, i32, 1000);
- TESTINSN_un("vrshr.u8 q7, q13, #7", q7, q13, i32, -1);
- TESTINSN_un("vrshr.u16 q8, q1, #5", q8, q1, i32, 0xabcf);
- TESTINSN_un("vrshr.u32 q12, q3, #15", q12, q3, i32, -0x1b0);
- TESTINSN_un("vrshr.u64 q0, q1, #42", q0, q1, i32, -1);
- TESTINSN_un("vrshr.s64 q6, q7, #12", q6, q7, i32, 0xfac);
- TESTINSN_un("vrshr.u64 q8, q4, #9", q8, q4, i32, 13560);
- TESTINSN_un("vrshr.s64 q9, q12, #11", q9, q12, i32, 98710);
-
- printf("---- VRSRA ----\n");
- TESTINSN_un("vrsra.s8 q0, q1, #1", q0, q1, i32, -1);
- TESTINSN_un("vrsra.s16 q3, q4, #2", q3, q4, i32, -0x7c);
- TESTINSN_un("vrsra.s32 q2, q5, #31", q2, q5, i32, -1);
- TESTINSN_un("vrsra.s8 q6, q7, #7", q6, q7, i32, 0xffff);
- TESTINSN_un("vrsra.s16 q8, q9, #12", q8, q9, i32, -10);
- TESTINSN_un("vrsra.s32 q10, q11, #5", q10, q11, i32, 10234);
- TESTINSN_un("vrsra.u8 q12, q13, #1", q12, q13, i32, -1);
- TESTINSN_un("vrsra.u16 q14, q15, #11", q14, q15, i32, -1);
- TESTINSN_un("vrsra.u32 q10, q11, #9", q10, q11, i32, 1000);
- TESTINSN_un("vrsra.u8 q7, q13, #7", q7, q13, i32, -1);
- TESTINSN_un("vrsra.u16 q8, q1, #5", q8, q1, i32, 0xabcf);
- TESTINSN_un("vrsra.u32 q12, q3, #15", q12, q3, i32, -0x1b0);
- TESTINSN_un("vrsra.u64 q0, q1, #42", q0, q1, i32, -1);
- TESTINSN_un("vrsra.s64 q6, q7, #12", q6, q7, i32, 0xfac);
- TESTINSN_un("vrsra.u64 q8, q4, #9", q8, q4, i32, 13560);
- TESTINSN_un("vrsra.s64 q9, q12, #11", q9, q12, i32, 98710);
-
- printf("---- VSHR ----\n");
- TESTINSN_un("vshr.s8 q0, q1, #0", q0, q1, i32, -1);
- TESTINSN_un("vshr.s8 q0, q1, #1", q0, q1, i32, -1);
- TESTINSN_un("vshr.s16 q3, q4, #2", q3, q4, i32, -0x7c);
- TESTINSN_un("vshr.s32 q2, q5, #31", q2, q5, i32, -1);
- TESTINSN_un("vshr.s8 q6, q7, #7", q6, q7, i32, 0xffff);
- TESTINSN_un("vshr.s16 q8, q9, #12", q8, q9, i32, -10);
- TESTINSN_un("vshr.s32 q10, q11, #5", q10, q11, i32, 10234);
- TESTINSN_un("vshr.u8 q12, q13, #1", q12, q13, i32, -1);
- TESTINSN_un("vshr.u16 q14, q15, #11", q14, q15, i32, -1);
- TESTINSN_un("vshr.u32 q10, q11, #9", q10, q11, i32, 1000);
- TESTINSN_un("vshr.u8 q7, q13, #7", q7, q13, i32, -1);
- TESTINSN_un("vshr.u16 q8, q1, #5", q8, q1, i32, 0xabcf);
- TESTINSN_un("vshr.u32 q12, q3, #15", q12, q3, i32, -0x1b0);
- TESTINSN_un("vshr.u64 q0, q1, #42", q0, q1, i32, -1);
- TESTINSN_un("vshr.s64 q6, q7, #12", q6, q7, i32, 0xfac);
- TESTINSN_un("vshr.u64 q8, q4, #9", q8, q4, i32, 13560);
- TESTINSN_un("vshr.s64 q9, q12, #11", q9, q12, i32, 98710);
-
- printf("---- VSRA ----\n");
- TESTINSN_un("vsra.s8 q0, q1, #1", q0, q1, i32, -1);
- TESTINSN_un("vsra.s16 q3, q4, #2", q3, q4, i32, -0x7c);
- TESTINSN_un("vsra.s32 q2, q5, #31", q2, q5, i32, -1);
- TESTINSN_un("vsra.s8 q6, q7, #7", q6, q7, i32, 0xffff);
- TESTINSN_un("vsra.s16 q8, q9, #12", q8, q9, i32, -10);
- TESTINSN_un("vsra.s32 q10, q11, #5", q10, q11, i32, 10234);
- TESTINSN_un("vsra.u8 q12, q13, #1", q12, q13, i32, -1);
- TESTINSN_un("vsra.u16 q14, q15, #11", q14, q15, i32, -1);
- TESTINSN_un("vsra.u32 q10, q11, #9", q10, q11, i32, 1000);
- TESTINSN_un("vsra.u8 q7, q13, #7", q7, q13, i32, -1);
- TESTINSN_un("vsra.u16 q8, q1, #5", q8, q1, i32, 0xabcf);
- TESTINSN_un("vsra.u32 q12, q3, #15", q12, q3, i32, -0x1b0);
- TESTINSN_un("vsra.u64 q0, q1, #42", q0, q1, i32, -1);
- TESTINSN_un("vsra.s64 q6, q7, #12", q6, q7, i32, 0xfac);
- TESTINSN_un("vsra.u64 q8, q4, #9", q8, q4, i32, 13560);
- TESTINSN_un("vsra.s64 q9, q12, #11", q9, q12, i32, 98710);
-
- printf("---- VSRI ----\n");
- TESTINSN_un("vsri.16 q0, q1, #1", q0, q1, i32, -1);
- TESTINSN_un("vsri.16 q3, q4, #2", q3, q4, i32, -0x7c);
- TESTINSN_un("vsri.32 q2, q5, #31", q2, q5, i32, -1);
- TESTINSN_un("vsri.8 q6, q7, #7", q6, q7, i32, 0xffff);
- TESTINSN_un("vsri.16 q8, q9, #12", q8, q9, i32, -10);
- TESTINSN_un("vsri.32 q10, q11, #5", q10, q11, i32, 10234);
- TESTINSN_un("vsri.8 q12, q13, #1", q12, q13, i32, -1);
- TESTINSN_un("vsri.16 q14, q15, #11", q14, q15, i32, -1);
- TESTINSN_un("vsri.32 q10, q11, #9", q10, q11, i32, 1000);
- TESTINSN_un("vsri.8 q7, q13, #7", q7, q13, i32, -1);
- TESTINSN_un("vsri.16 q8, q1, #5", q8, q1, i32, 0xabcf);
- TESTINSN_un("vsri.32 q12, q3, #15", q12, q3, i32, -0x1b0);
- TESTINSN_un("vsri.64 q0, q1, #42", q0, q1, i32, -1);
- TESTINSN_un("vsri.64 q6, q7, #12", q6, q7, i32, 0xfac);
- TESTINSN_un("vsri.64 q8, q4, #9", q8, q4, i32, 13560);
- TESTINSN_un("vsri.64 q9, q12, #11", q9, q12, i32, 98710);
-
- printf("---- VMOVL ----\n");
- TESTINSN_un("vmovl.u32 q0, d2", q0, d2, i32, 0x42);
- TESTINSN_un("vmovl.u16 q15, d2", q15, d2, i32, 0x42);
- TESTINSN_un("vmovl.u8 q3, d31", q0, d31, i32, 0x42);
- TESTINSN_un("vmovl.s32 q0, d2", q0, d2, i32, 0x42);
- TESTINSN_un("vmovl.s16 q15, d2", q15, d2, i32, 0x42);
- TESTINSN_un("vmovl.s8 q3, d31", q0, d31, i32, 0x42);
- TESTINSN_un("vmovl.u32 q0, d2", q0, d2, i8, 0xed);
- TESTINSN_un("vmovl.u16 q15, d2", q15, d2, i8, 0xed);
- TESTINSN_un("vmovl.u8 q3, d31", q0, d31, i8, 0xed);
- TESTINSN_un("vmovl.s32 q0, d2", q0, d2, i8, 0xed);
- TESTINSN_un("vmovl.s16 q15, d2", q15, d2, i8, 0xed);
- TESTINSN_un("vmovl.s8 q3, d31", q0, d31, i8, 0xed);
-
- printf("---- VABS ----\n");
- TESTINSN_un("vabs.s32 q0, q1", q0, q1, i32, 0x73);
- TESTINSN_un("vabs.s16 q15, q4", q15, q4, i32, 0x73);
- TESTINSN_un("vabs.s8 q8, q7", q8, q7, i32, 0x73);
- TESTINSN_un("vabs.s32 q0, q1", q0, q1, i32, 0xfe);
- TESTINSN_un("vabs.s16 q15, q4", q15, q4, i32, 0xef);
- TESTINSN_un("vabs.s8 q8, q7", q8, q7, i32, 0xde);
- TESTINSN_un("vabs.s32 q0, q1", q0, q1, i16, 0xfe0a);
- TESTINSN_un("vabs.s16 q15, q4", q15, q4, i16, 0xef0b);
- TESTINSN_un("vabs.s8 q8, q7", q8, q7, i16, 0xde0c);
-
- printf("---- VQABS ----\n");
- TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i32, 0x73);
- TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i32, 1 << 31);
- TESTINSN_un_q("vqabs.s16 q0, q1", q0, q1, i32, 1 << 31);
- TESTINSN_un_q("vqabs.s8 q0, q1", q0, q1, i32, 1 << 31);
- TESTINSN_un_q("vqabs.s16 q15, q4", q15, q4, i32, 0x73);
- TESTINSN_un_q("vqabs.s8 q8, q7", q8, q7, i32, 0x73);
- TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i32, 0xfe);
- TESTINSN_un_q("vqabs.s16 q15, q4", q15, q4, i32, 0xef);
- TESTINSN_un_q("vqabs.s8 q8, q7", q8, q7, i32, 0xde);
- TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i16, 0xfe0a);
- TESTINSN_un_q("vqabs.s16 q15, q4", q15, q4, i16, 0xef0b);
- TESTINSN_un_q("vqabs.s8 q8, q7", q8, q7, i16, 0xde0c);
-
- printf("---- VADDW ----\n");
- TESTINSN_bin("vaddw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0x12);
- TESTINSN_bin("vaddw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vaddw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vaddw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0xe2);
- TESTINSN_bin("vaddw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vaddw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vaddw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
-
- printf("---- VADDL ----\n");
- TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0x12);
- TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0xe2);
- TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i8, 0x99, d31, i8, 0x12);
- TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
- TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0xe2);
- TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i8, 0x93, d31, i8, 0xe2);
- TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
- TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
- TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
-
- printf("---- VSUBW ----\n");
- TESTINSN_bin("vsubw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0x12);
- TESTINSN_bin("vsubw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vsubw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vsubw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0xe2);
- TESTINSN_bin("vsubw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vsubw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vsubw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
-
- printf("---- VSUBL ----\n");
- TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0x12);
- TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
- TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0xe2);
- TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
- TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i8, 0x99, d31, i8, 0x12);
- TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
- TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
- TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0xe2);
- TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i8, 0x93, d31, i8, 0xe2);
- TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
- TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
- TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
-
- printf("---- VCEQ #0 ----\n");
- TESTINSN_un("vceq.i32 q0, q1, #0", q0, q1, i32, 0x21);
- TESTINSN_un("vceq.i16 q2, q1, #0", q2, q1, i32, 0x21);
- TESTINSN_un("vceq.i8 q10, q11, #0", q10, q11, i32, 0x21);
- TESTINSN_un("vceq.i32 q0, q1, #0", q0, q1, i32, 0x0);
- TESTINSN_un("vceq.i16 q2, q1, #0", q2, q1, i32, 0x0);
- TESTINSN_un("vceq.i8 q10, q11, #0", q10, q11, i32, 0x0);
-
- printf("---- VCGT #0 ----\n");
- TESTINSN_un("vcgt.s32 q0, q1, #0", q0, q1, i32, 0x21);
- TESTINSN_un("vcgt.s16 q2, q1, #0", q2, q1, i32, 0x21);
- TESTINSN_un("vcgt.s8 q10, q11, #0", q10, q11, i32, 0x21);
- TESTINSN_un("vcgt.s32 q0, q1, #0", q0, q1, i32, 0x0);
- TESTINSN_un("vcgt.s16 q2, q1, #0", q2, q1, i32, 0x0);
- TESTINSN_un("vcgt.s8 q10, q11, #0", q10, q11, i32, 0x0);
- TESTINSN_un("vcgt.s32 q0, q1, #0", q0, q1, i8, 0xef);
- TESTINSN_un("vcgt.s16 q2, q1, #0", q2, q1, i8, 0xed);
- TESTINSN_un("vcgt.s8 q10, q11, #0", q10, q11, i8, 0xae);
-
- printf("---- VCGE #0 ----\n");
- TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i32, 0x21);
- TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i32, 0x21);
- TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i32, 0x21);
- TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i32, 0x0);
- TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i32, 0x0);
- TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i32, 0x0);
- TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i8, 0xef);
- TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i8, 0xed);
- TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i8, 0xae);
- TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i32, 0xef);
- TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i32, 0xed);
- TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i32, 0xae);
-
- printf("---- VCLE #0 ----\n");
- TESTINSN_un("vcle.s32 q0, q1, #0", q0, q1, i32, 0x21);
- TESTINSN_un("vcle.s16 q2, q1, #0", q2, q1, i32, 0x21);
- TESTINSN_un("vcle.s8 q10, q11, #0", q10, q11, i32, 0x21);
- TESTINSN_un("vcle.s32 q0, q1, #0", q0, q1, i32, 0x0);
- TESTINSN_un("vcle.s16 q2, q1, #0", q2, q1, i32, 0x0);
- TESTINSN_un("vcle.s8 q10, q11, #0", q10, q11, i32, 0x0);
- TESTINSN_un("vcle.s32 q0, q1, #0", q0, q1, i8, 0xef);
- TESTINSN_un("vcle.s16 q2, q1, #0", q2, q1, i8, 0xed);
- TESTINSN_un("vcle.s8 q10, q11, #0", q10, q11, i8, 0xae);
-
- printf("---- VCLT #0 ----\n");
- TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i32, 0x21);
- TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i32, 0x21);
- TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i32, 0x21);
- TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i32, 0x0);
- TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i32, 0x0);
- TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i32, 0x0);
- TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i8, 0xef);
- TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i8, 0xed);
- TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i8, 0xae);
- TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i32, 0xef);
- TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i32, 0xed);
- TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i32, 0xae);
-
- printf("---- VCNT ----\n");
- TESTINSN_un("vcnt.8 q0, q1", q0, q1, i32, 0xac3d25eb);
- TESTINSN_un("vcnt.8 q11, q14", q11, q14, i32, 0xac3d25eb);
- TESTINSN_un("vcnt.8 q6, q2", q6, q2, i32, 0xad0eb);
-
- printf("---- VCLS ----\n");
- TESTINSN_un("vcls.s8 q0, q1", q0, q1, i32, 0x21);
- TESTINSN_un("vcls.s8 q10, q15", q10, q15, i8, 0x82);
- TESTINSN_un("vcls.s16 q0, q1", q0, q1, i32, 0x21);
- TESTINSN_un("vcls.s16 q15, q10", q15, q10, i8, 0x82);
- TESTINSN_un("vcls.s32 q6, q1", q6, q1, i32, 0x21);
- TESTINSN_un("vcls.s32 q10, q5", q10, q5, i8, 0x82);
- TESTINSN_un("vcls.s8 q2, q4", q2, q4, i8, 0xff);
- TESTINSN_un("vcls.s16 q2, q4", q2, q4, i8, 0xff);
- TESTINSN_un("vcls.s32 q2, q4", q2, q4, i8, 0xff);
- TESTINSN_un("vcls.s8 q2, q4", q2, q4, i16, 0xffef);
- TESTINSN_un("vcls.s16 q2, q4", q2, q4, i16, 0xffef);
- TESTINSN_un("vcls.s32 q2, q4", q2, q4, i16, 0xffef);
- TESTINSN_un("vcls.s8 q2, q4", q2, q4, i8, 0x00);
- TESTINSN_un("vcls.s16 q2, q4", q2, q4, i8, 0x00);
- TESTINSN_un("vcls.s32 q2, q4", q2, q4, i8, 0x00);
- TESTINSN_un("vcls.s8 q2, q4", q2, q4, i16, 0x00ef);
- TESTINSN_un("vcls.s16 q2, q4", q2, q4, i16, 0x00ef);
- TESTINSN_un("vcls.s32 q2, q4", q2, q4, i16, 0x00ef);
-
- printf("---- VCLZ ----\n");
- TESTINSN_un("vclz.i8 q0, q1", q0, q1, i32, 0x21);
- TESTINSN_un("vclz.i8 q10, q15", q10, q15, i8, 0x82);
- TESTINSN_un("vclz.i16 q0, q1", q0, q1, i32, 0x21);
- TESTINSN_un("vclz.i16 q15, q10", q15, q10, i8, 0x82);
- TESTINSN_un("vclz.i32 q6, q1", q6, q1, i32, 0x21);
- TESTINSN_un("vclz.i32 q10, q5", q10, q5, i8, 0x82);
- TESTINSN_un("vclz.i8 q2, q4", q2, q4, i8, 0xff);
- TESTINSN_un("vclz.i16 q2, q4", q2, q4, i8, 0xff);
- TESTINSN_un("vclz.i32 q2, q4", q2, q4, i8, 0xff);
- TESTINSN_un("vclz.i8 q2, q4", q2, q4, i16, 0xffef);
- TESTINSN_un("vclz.i16 q2, q4", q2, q4, i16, 0xffef);
- TESTINSN_un("vclz.i32 q2, q4", q2, q4, i16, 0xffef);
- TESTINSN_un("vclz.i8 q2, q4", q2, q4, i8, 0x00);
- TESTINSN_un("vclz.i16 q2, q4", q2, q4, i8, 0x00);
- TESTINSN_un("vclz.i32 q2, q4", q2, q4, i8, 0x00);
- TESTINSN_un("vclz.i8 q2, q4", q2, q4, i16, 0x00ef);
- TESTINSN_un("vclz.i16 q2, q4", q2, q4, i16, 0x00ef);
- TESTINSN_un("vclz.i32 q2, q4", q2, q4, i16, 0x00ef);
-
- printf("---- VSLI ----\n");
- TESTINSN_un("vsli.16 q0, q1, #1", q0, q1, i32, -1);
- TESTINSN_un("vsli.16 q3, q4, #2", q3, q4, i32, -0x7c);
- TESTINSN_un("vsli.32 q2, q5, #31", q2, q5, i32, -1);
- TESTINSN_un("vsli.8 q6, q7, #7", q6, q7, i32, 0xffff);
- TESTINSN_un("vsli.16 q8, q9, #12", q8, q9, i32, -10);
- TESTINSN_un("vsli.32 q10, q11, #5", q10, q11, i32, 10234);
- TESTINSN_un("vsli.8 q12, q13, #1", q12, q13, i32, -1);
- TESTINSN_un("vsli.16 q14, q15, #11", q14, q15, i32, -1);
- TESTINSN_un("vsli.32 q10, q11, #9", q10, q11, i32, 1000);
- TESTINSN_un("vsli.8 q7, q13, #7", q7, q13, i32, -1);
- TESTINSN_un("vsli.16 q8, q1, #1", q8, q1, i32, 0xabcf);
- TESTINSN_un("vsli.32 q12, q3, #15", q12, q3, i32, -0x1b0);
- TESTINSN_un("vsli.64 q0, q1, #42", q0, q1, i32, -1);
- TESTINSN_un("vsli.64 q6, q7, #12", q6, q7, i32, 0xfac);
- TESTINSN_un("vsli.64 q8, q4, #9", q8, q4, i32, 13560);
- TESTINSN_un("vsli.64 q9, q12, #11", q9, q12, i32, 98710);
-
- printf("---- VPADDL ----\n");
- TESTINSN_un("vpaddl.u32 q0, q1", q0, q1, i32, 24);
- TESTINSN_un("vpaddl.u32 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpaddl.u16 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpaddl.u8 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpaddl.u8 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.u16 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.u32 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.u32 q10, q11", q10, q11, i32, 24);
- TESTINSN_un("vpaddl.s32 q0, q1", q0, q1, i32, 24);
- TESTINSN_un("vpaddl.s32 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpaddl.s16 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpaddl.s8 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpaddl.s8 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.s16 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.s32 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.s32 q10, q11", q10, q11, i32, 24);
-
- printf("---- VPADAL ----\n");
- TESTINSN_un("vpadal.u32 q0, q1", q0, q1, i32, 24);
- TESTINSN_un("vpadal.u32 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpadal.u16 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpadal.u8 q0, q1", q0, q1, i8, 140);
- TESTINSN_un("vpadal.u8 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.u16 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.u32 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.u32 q10, q11", q10, q11, i32, 24);
- TESTINSN_un("vpadal.s32 q0, q1", q0, q1, i32, 24);
- TESTINSN_un("vpadal.s32 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpadal.s16 q0, q1", q0, q1, i32, 140);
- TESTINSN_un("vpadal.s8 q0, q1", q0, q1, i8, 140);
- TESTINSN_un("vpadal.s8 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.s16 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.s32 q0, q1", q0, q1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.s32 q10, q11", q10, q11, i32, 24);
-
- printf("---- VZIP ----\n");
- TESTINSN_dual("vzip.32 q0, q1", q0, i8, 0x12, q1, i8, 0x34);
- TESTINSN_dual("vzip.16 q1, q0", q0, i8, 0x12, q1, i8, 0x34);
- TESTINSN_dual("vzip.8 q10, q11", q10, i8, 0x12, q11, i8, 0x34);
- TESTINSN_dual("vzip.32 q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vzip.16 q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vzip.8 q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d);
-
- printf("---- VUZP ----\n");
- TESTINSN_dual("vuzp.32 q0, q1", q0, i8, 0x12, q1, i8, 0x34);
- TESTINSN_dual("vuzp.16 q1, q0", q0, i8, 0x12, q1, i8, 0x34);
- TESTINSN_dual("vuzp.8 q10, q11", q10, i8, 0x12, q11, i8, 0x34);
- TESTINSN_dual("vuzp.32 q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vuzp.16 q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vuzp.8 q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d);
-
- printf("---- VTRN ----\n");
- TESTINSN_dual("vtrn.32 q0, q1", q0, i8, 0x12, q1, i8, 0x34);
- TESTINSN_dual("vtrn.16 q1, q0", q0, i8, 0x12, q1, i8, 0x34);
- TESTINSN_dual("vtrn.8 q10, q11", q10, i8, 0x12, q11, i8, 0x34);
- TESTINSN_dual("vtrn.32 q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vtrn.16 q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vtrn.8 q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d);
-
- printf("---- VSWP ----\n");
- TESTINSN_dual("vswp q0, q1", q0, i8, 0x12, q1, i8, 0x34);
- TESTINSN_dual("vswp q1, q0", q0, i8, 0x12, q1, i8, 0x34);
- TESTINSN_dual("vswp q10, q11", q10, i8, 0x12, q11, i8, 0x34);
- TESTINSN_dual("vswp q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vswp q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vswp q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d);
-
- printf("---- VDUP ----\n");
- TESTINSN_un("vdup.8 q2, d2[0]", q2, d2, i32, 0xabc4657);
- TESTINSN_un("vdup.8 q3, d3[2]", q3, d3, i32, 0x7a1b3);
- TESTINSN_un("vdup.8 q1, d0[7]", q1, d0, i32, 0x713aaa);
- TESTINSN_un("vdup.8 q0, d4[3]", q0, d4, i32, 0xaa713);
- TESTINSN_un("vdup.8 q4, d28[4]", q4, d28, i32, 0x7b1c3);
- TESTINSN_un("vdup.16 q7, d19[3]", q7, d19, i32, 0x713ffff);
- TESTINSN_un("vdup.16 q15, d31[0]", q15, d31, i32, 0x7f00fa);
- TESTINSN_un("vdup.16 q6, d2[0]", q6, d2, i32, 0xffabcde);
- TESTINSN_un("vdup.16 q8, d22[3]", q8, d22, i32, 0x713);
- TESTINSN_un("vdup.16 q9, d2[0]", q9, d2, i32, 0x713);
- TESTINSN_un("vdup.32 q10, d17[1]", q10, d17, i32, 0x713);
- TESTINSN_un("vdup.32 q15, d11[0]", q15, d11, i32, 0x3);
- TESTINSN_un("vdup.32 q10, d29[1]", q10, d29, i32, 0xf00000aa);
- TESTINSN_un("vdup.32 q12, d0[1]", q12, d0, i32, 0xf);
- TESTINSN_un("vdup.32 q13, d13[0]", q13, d13, i32, -1);
-
- printf("---- VQDMULL ----\n");
- TESTINSN_bin_q("vqdmull.s32 q0, d1, d2", q0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin_q("vqdmull.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin_q("vqdmull.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin_q("vqdmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin_q("vqdmull.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmull.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqdmull.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmull.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
-
- printf("---- VQDMULL (by scalar) ----\n");
- TESTINSN_bin_q("vqdmull.s32 q0, d1, d7[0]", q0, d1, i32, 24, d7, i32, 120);
- TESTINSN_bin_q("vqdmull.s32 q6, d7, d6[0]", q6, d7, i32, 140, d6, i32, -120);
- TESTINSN_bin_q("vqdmull.s16 q9, d11, d7[2]", q9, d11, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin_q("vqdmull.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmull.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmull.s16 q4, d5, d6[1]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmull.s32 q7, d8, d3[0]", q7, d8, i32, (1 << 31), d3, i32, 12);
- TESTINSN_bin_q("vqdmull.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmull.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmull.s32 q10, d11, d15[1]", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqdmull.s32 q10, d30, d1[0]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
- TESTINSN_bin_q("vqdmull.s16 q10, d30, d1[1]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
- TESTINSN_bin_q("vqdmull.s32 q10, d30, d1[1]", q10, d30, i32, 1 << 30, d1, i32, 1 << 31);
- TESTINSN_bin_q("vqdmull.s16 q10, d30, d1[3]", q10, d30, i32, 1 << 31, d1, i32, 1 << 30);
-
- printf("---- VQDMLSL ----\n");
- TESTINSN_bin_q("vqdmlsl.s32 q0, d1, d2", q0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin_q("vqdmlsl.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin_q("vqdmlsl.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmlsl.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
-
- printf("---- VQDMLSL (by scalar) ----\n");
- TESTINSN_bin_q("vqdmlsl.s32 q0, d1, d7[0]", q0, d1, i32, 24, d7, i32, 120);
- TESTINSN_bin_q("vqdmlsl.s32 q6, d7, d6[0]", q6, d7, i32, 140, d6, i32, -120);
- TESTINSN_bin_q("vqdmlsl.s16 q9, d11, d7[2]", q9, d11, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6[1]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d3[0]", q7, d8, i32, (1 << 31), d3, i32, 12);
- TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmlsl.s32 q10, d11, d15[1]", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d1[0]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d1[1]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d1[1]", q10, d30, i32, 1 << 30, d1, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d1[3]", q10, d30, i32, 1 << 31, d1, i32, 1 << 30);
-
- printf("---- VQDMLAL ----\n");
- TESTINSN_bin_q("vqdmlal.s32 q0, d1, d2", q0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin_q("vqdmlal.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin_q("vqdmlal.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmlal.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqdmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
-
- printf("---- VQDMLAL (by scalar) ----\n");
- TESTINSN_bin_q("vqdmlal.s32 q0, d1, d7[0]", q0, d1, i32, 24, d7, i32, 120);
- TESTINSN_bin_q("vqdmlal.s32 q6, d7, d6[0]", q6, d7, i32, 140, d6, i32, -120);
- TESTINSN_bin_q("vqdmlal.s16 q9, d11, d7[2]", q9, d11, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlal.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6[1]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlal.s32 q7, d8, d3[0]", q7, d8, i32, (1 << 31), d3, i32, 12);
- TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmlal.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmlal.s32 q10, d11, d15[1]", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqdmlal.s32 q10, d30, d1[0]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlal.s16 q10, d30, d1[1]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlal.s32 q10, d30, d1[1]", q10, d30, i32, 1 << 30, d1, i32, 1 << 31);
- TESTINSN_bin_q("vqdmlal.s16 q10, d30, d1[3]", q10, d30, i32, 1 << 31, d1, i32, 1 << 30);
-
- printf("---- VQDMULH ----\n");
- TESTINSN_bin_q("vqdmulh.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin_q("vqdmulh.s32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120);
- TESTINSN_bin_q("vqdmulh.s16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
- TESTINSN_bin_q("vqdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) - 0xabcd, q6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31), q9, i32, 12);
- TESTINSN_bin_q("vqdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmulh.s32 q10, q11, q15", q10, q11, i32, 24, q15, i32, 120);
- TESTINSN_bin_q("vqdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 30, q15, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 30);
-
- printf("---- VQDMULH (by scalar) ----\n");
- TESTINSN_bin_q("vqdmulh.s32 q0, q1, d6[0]", q0, q1, i32, 24, d6, i32, 120);
- TESTINSN_bin_q("vqdmulh.s32 q6, q7, d1[1]", q6, q7, i32, 140, d1, i32, -120);
- TESTINSN_bin_q("vqdmulh.s16 q9, q11, d7[0]", q9, q11, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin_q("vqdmulh.s16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 q7, q8, d9[1]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmulh.s16 q4, q5, d6[1]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin_q("vqdmulh.s16 q4, q5, d6[2]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmulh.s32 q10, q11, d15[0]", q10, q11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s16 q10, q14, d7[3]", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 30, d15, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s16 q10, q14, d7[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 30);
-
- printf("---- VSHL (immediate) ----\n");
- TESTINSN_un("vshl.i64 q0, q1, #1", q0, q1, i32, 24);
- TESTINSN_un("vshl.i64 q5, q2, #1", q5, q2, i32, (1 << 30));
- TESTINSN_un("vshl.i64 q9, q12, #2", q9, q12, i32, (1 << 31) + 2);
- TESTINSN_un("vshl.i64 q11, q2, #12", q11, q2, i32, -1);
- TESTINSN_un("vshl.i64 q15, q12, #63", q15, q12, i32, 5);
- TESTINSN_un("vshl.i64 q5, q12, #62", q5, q12, i32, (1 << 31) + 1);
- TESTINSN_un("vshl.i32 q0, q1, #1", q0, q1, i32, 24);
- TESTINSN_un("vshl.i32 q5, q2, #1", q5, q2, i32, (1 << 30));
- TESTINSN_un("vshl.i32 q9, q12, #2", q9, q12, i32, (1 << 31) + 2);
- TESTINSN_un("vshl.i32 q11, q2, #12", q11, q2, i32, -1);
- TESTINSN_un("vshl.i32 q15, q12, #20", q15, q12, i32, 5);
- TESTINSN_un("vshl.i32 q5, q12, #30", q5, q12, i32, (1 << 31) + 1);
- TESTINSN_un("vshl.i16 q0, q1, #1", q0, q1, i16, 24);
- TESTINSN_un("vshl.i16 q5, q2, #1", q5, q2, i32, (1 << 30));
- TESTINSN_un("vshl.i16 q9, q12, #2", q9, q12, i32, (1 << 31) + 2);
- TESTINSN_un("vshl.i16 q11, q2, #12", q11, q2, i16, -1);
- TESTINSN_un("vshl.i16 q15, q12, #3", q15, q12, i16, 5);
- TESTINSN_un("vshl.i16 q5, q12, #14", q5, q12, i32, (1 << 31) + 1);
- TESTINSN_un("vshl.i8 q0, q1, #1", q0, q1, i8, 24);
- TESTINSN_un("vshl.i8 q5, q2, #1", q5, q2, i32, (1 << 30));
- TESTINSN_un("vshl.i8 q9, q12, #2", q9, q12, i32, (1 << 31) + 2);
- TESTINSN_un("vshl.i8 q11, q2, #7", q11, q2, i8, -1);
- TESTINSN_un("vshl.i8 q15, q12, #3", q15, q12, i8, 5);
- TESTINSN_un("vshl.i8 q5, q12, #6", q5, q12, i32, (1 << 31) + 1);
-
- printf("---- VNEG ----\n");
- TESTINSN_un("vneg.s32 q0, q1", q0, q1, i32, 0x73);
- TESTINSN_un("vneg.s16 q15, q4", q15, q4, i32, 0x73);
- TESTINSN_un("vneg.s8 q8, q7", q8, q7, i32, 0x73);
- TESTINSN_un("vneg.s32 q0, q1", q0, q1, i32, 0xfe);
- TESTINSN_un("vneg.s16 q15, q4", q15, q4, i32, 0xef);
- TESTINSN_un("vneg.s8 q8, q7", q8, q7, i32, 0xde);
- TESTINSN_un("vneg.s32 q0, q1", q0, q1, i16, 0xfe0a);
- TESTINSN_un("vneg.s16 q15, q4", q15, q4, i16, 0xef0b);
- TESTINSN_un("vneg.s8 q8, q7", q8, q7, i16, 0xde0c);
-
- printf("---- VQNEG ----\n");
- TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i32, 0x73);
- TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i32, 1 << 31);
- TESTINSN_un_q("vqneg.s16 q0, q1", q0, q1, i32, 1 << 31);
- TESTINSN_un_q("vqneg.s8 q0, q1", q0, q1, i32, 1 << 31);
- TESTINSN_un_q("vqneg.s16 q15, q4", q15, q4, i32, 0x73);
- TESTINSN_un_q("vqneg.s8 q8, q7", q8, q7, i32, 0x73);
- TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i32, 0xfe);
- TESTINSN_un_q("vqneg.s16 q15, q4", q15, q4, i32, 0xef);
- TESTINSN_un_q("vqneg.s8 q8, q7", q8, q7, i32, 0xde);
- TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i16, 0xfe0a);
- TESTINSN_un_q("vqneg.s16 q15, q4", q15, q4, i16, 0xef0b);
- TESTINSN_un_q("vqneg.s8 q8, q7", q8, q7, i16, 0xde0c);
-
- printf("---- VREV ----\n");
- TESTINSN_un("vrev64.8 q0, q1", q0, q1, i32, 0xaabbccdd);
- TESTINSN_un("vrev64.16 q10, q15", q10, q15, i32, 0xaabbccdd);
- TESTINSN_un("vrev64.32 q1, q14", q1, q14, i32, 0xaabbccdd);
- TESTINSN_un("vrev32.8 q0, q1", q0, q1, i32, 0xaabbccdd);
- TESTINSN_un("vrev32.16 q10, q15", q10, q15, i32, 0xaabbccdd);
- TESTINSN_un("vrev16.8 q0, q1", q0, q1, i32, 0xaabbccdd);
-
- printf("---- VSHLL ----\n");
- TESTINSN_un("vshll.s32 q0, d1, #1", q0, d1, i32, 24);
- TESTINSN_un("vshll.s32 q5, d2, #1", q5, d2, i32, (1 << 30));
- TESTINSN_un("vshll.s32 q9, d12, #2", q9, d12, i32, (1 << 31) + 2);
- TESTINSN_un("vshll.u32 q11, d2, #12", q11, d2, i32, -1);
- TESTINSN_un("vshll.u32 q15, d12, #20", q15, d12, i32, 5);
- TESTINSN_un("vshll.u32 q5, d22, #30", q5, d22, i32, (1 << 31) + 1);
- TESTINSN_un("vshll.s16 q0, d1, #1", q0, d1, i16, 24);
- TESTINSN_un("vshll.s16 q5, d2, #1", q5, d2, i32, (1 << 30));
- TESTINSN_un("vshll.s16 q9, d12, #2", q9, d12, i32, (1 << 31) + 2);
- TESTINSN_un("vshll.u16 q11, d2, #12", q11, d2, i16, -1);
- TESTINSN_un("vshll.u16 q15, d22, #3", q15, d22, i16, 5);
- TESTINSN_un("vshll.u16 q5, d12, #14", q5, d12, i32, (1 << 31) + 1);
- TESTINSN_un("vshll.s8 q0, d1, #1", q0, d1, i8, 24);
- TESTINSN_un("vshll.s8 q5, d2, #1", q5, d2, i32, (1 << 30));
- TESTINSN_un("vshll.s8 q9, d12, #2", q9, d12, i32, (1 << 31) + 2);
- TESTINSN_un("vshll.u8 q11, d2, #7", q11, d2, i8, -1);
- TESTINSN_un("vshll.u8 q15, d19, #3", q15, d19, i8, 5);
- TESTINSN_un("vshll.u8 q5, d12, #6", q5, d12, i32, (1 << 31) + 1);
-
- printf("---- VSHLL (max shift) ----\n");
- TESTINSN_un("vshll.i32 q0, d1, #32", q0, d1, i32, 24);
- TESTINSN_un("vshll.i32 q5, d2, #32", q5, d2, i32, (1 << 30));
- TESTINSN_un("vshll.i32 q11, d2, #32", q11, d2, i32, -1);
- TESTINSN_un("vshll.i32 q15, d12, #32", q15, d12, i32, 5);
- TESTINSN_un("vshll.i16 q0, d1, #16", q0, d1, i16, 24);
- TESTINSN_un("vshll.i16 q5, d2, #16", q5, d2, i32, (1 << 30));
- TESTINSN_un("vshll.i16 q11, d2, #16", q11, d2, i16, -1);
- TESTINSN_un("vshll.i16 q15, d22, #16", q15, d22, i16, 5);
- TESTINSN_un("vshll.i8 q0, d1, #8", q0, d1, i8, 24);
- TESTINSN_un("vshll.i8 q5, d2, #8", q5, d2, i32, (1 << 30));
- TESTINSN_un("vshll.i8 q11, d2, #8", q11, d2, i8, -1);
- TESTINSN_un("vshll.i8 q15, d19, #8", q15, d19, i8, 5);
-
- printf("---- VMULL ----\n");
- TESTINSN_bin("vmull.s8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmull.s8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmull.s8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.s8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmull.s8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmull.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmull.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmull.u8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmull.u8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmull.u8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.u8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmull.u8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmull.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmull.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmull.s16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmull.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmull.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmull.u16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmull.u16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmull.u16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.u16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmull.u16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmull.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmull.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmull.s32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
- TESTINSN_bin("vmull.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin("vmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin("vmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmull.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin("vmull.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmull.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
- TESTINSN_bin("vmull.u32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
- TESTINSN_bin("vmull.u32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin("vmull.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmull.u32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin("vmull.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmull.u32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin("vmull.u32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmull.u32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
- TESTINSN_bin("vmull.p8 q9, d11, d12", q9, d11, i32, 0x1a4b0c, d12, i32, 0xd1e2f0);
- TESTINSN_bin("vmull.p8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmull.p8 q4, d15, d26", q4, d15, i32, (1 << 14) - 0xabcd, d26, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmull.p8 q14, d5, d6", q14, d5, i32, (1 << 28) + 0xefe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmull.p8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmull.p8 q10, d27, d31", q10, d27, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmull.p8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmull.p8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmull.p8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
-
- printf("---- VMLAL ----\n");
- TESTINSN_bin("vmlal.s8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmlal.s8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmlal.s8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.s8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmlal.s8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmlal.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlal.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmlal.u8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmlal.u8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmlal.u8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.u8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmlal.u8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmlal.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlal.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmlal.s16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmlal.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmlal.u16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmlal.u16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmlal.u16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlal.u16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmlal.u16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmlal.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlal.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmlal.s32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
- TESTINSN_bin("vmlal.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin("vmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin("vmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlal.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin("vmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
- TESTINSN_bin("vmlal.u32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
- TESTINSN_bin("vmlal.u32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin("vmlal.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlal.u32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin("vmlal.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlal.u32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin("vmlal.u32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlal.u32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
-
- printf("---- VMLSL ----\n");
- TESTINSN_bin("vmlsl.s8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmlsl.s8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmlsl.s8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.s8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmlsl.s8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmlsl.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlsl.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmlsl.u8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmlsl.u8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmlsl.u8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.u8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmlsl.u8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmlsl.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlsl.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmlsl.s16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmlsl.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmlsl.u16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
- TESTINSN_bin("vmlsl.u16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmlsl.u16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmlsl.u16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
- TESTINSN_bin("vmlsl.u16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
- TESTINSN_bin("vmlsl.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlsl.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
- TESTINSN_bin("vmlsl.s32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
- TESTINSN_bin("vmlsl.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin("vmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin("vmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlsl.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin("vmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
- TESTINSN_bin("vmlsl.u32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
- TESTINSN_bin("vmlsl.u32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin("vmlsl.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlsl.u32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin("vmlsl.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmlsl.u32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin("vmlsl.u32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin("vmlsl.u32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
-
- printf("---- VQRDMULH ----\n");
- TESTINSN_bin_q("vqrdmulh.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
- TESTINSN_bin_q("vqrdmulh.s32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120);
- TESTINSN_bin_q("vqrdmulh.s16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
- TESTINSN_bin_q("vqrdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqrdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) - 0xabcd, q6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31), q9, i32, 12);
- TESTINSN_bin_q("vqrdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 q10, q11, q15", q10, q11, i32, 24, q15, i32, 120);
- TESTINSN_bin_q("vqrdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
- TESTINSN_bin_q("vqrdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, (1 << 31) + 1);
- TESTINSN_bin_q("vqrdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
- TESTINSN_bin_q("vqrdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 30, q15, i32, 1 << 31);
- TESTINSN_bin_q("vqrdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 30);
-
- printf("---- VQRDMULH (by scalar) ----\n");
- TESTINSN_bin_q("vqrdmulh.s32 q0, q1, d6[0]", q0, q1, i32, 24, d6, i32, 120);
- TESTINSN_bin_q("vqrdmulh.s32 q6, q7, d1[1]", q6, q7, i32, 140, d1, i32, -120);
- TESTINSN_bin_q("vqrdmulh.s16 q9, q11, d7[0]", q9, q11, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin_q("vqrdmulh.s16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 q7, q8, d9[1]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqrdmulh.s16 q4, q5, d6[1]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin_q("vqrdmulh.s16 q4, q5, d6[2]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 q10, q11, d15[0]", q10, q11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqrdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 31);
- TESTINSN_bin_q("vqrdmulh.s16 q10, q14, d7[3]", q10, q14, i32, 1 << 31, q15, i32, (1 << 31) + 1);
- TESTINSN_bin_q("vqrdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 30, d15, i32, 1 << 31);
- TESTINSN_bin_q("vqrdmulh.s16 q10, q14, d7[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 30);
-
- printf("---- VADD (fp) ----\n");
- TESTINSN_bin("vadd.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vadd.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vadd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vadd.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vadd.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vadd.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vadd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vadd.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vadd.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vadd.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vadd.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vadd.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vadd.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vadd.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vadd.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vadd.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vadd.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vadd.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VSUB (fp) ----\n");
- TESTINSN_bin("vsub.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vsub.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vsub.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vsub.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vsub.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vsub.f32 q3, q4, q5", q3, q4, i32, f2u(24.89), q5, i32, f2u(1346));
- TESTINSN_bin("vsub.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vsub.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vsub.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vsub.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vsub.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vsub.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vsub.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vsub.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vsub.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vsub.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vsub.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vsub.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VABD (fp) ----\n");
- TESTINSN_bin("vabd.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vabd.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vabd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vabd.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vabd.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vabd.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vabd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vabd.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vabd.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vabd.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vabd.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vabd.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vabd.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vabd.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vabd.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vabd.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vabd.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vabd.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VMUL (fp) ----\n");
- TESTINSN_bin("vmul.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vmul.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vmul.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vmul.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vmul.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vmul.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vmul.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vmul.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vmul.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vmul.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vmul.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vmul.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vmul.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vmul.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vmul.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vmul.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vmul.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vmul.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VMLA (fp) ----\n");
- TESTINSN_bin_f("vmla.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin_f("vmla.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin_f("vmla.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin_f("vmla.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin_f("vmla.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin_f("vmla.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin_f("vmla.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin_f("vmla.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin_f("vmla.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin_f("vmla.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin_f("vmla.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin_f("vmla.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin_f("vmla.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin_f("vmla.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin_f("vmla.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin_f("vmla.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin_f("vmla.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin_f("vmla.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VMLA (fp by scalar) ----\n");
- TESTINSN_bin_f("vmla.f32 q0, q1, d4[0]", q0, q1, i32, f2u(24), d4, i32, f2u(120));
- TESTINSN_bin_f("vmla.f32 q15, q8, d7[1]", q15, q8, i32, f2u(140), d7, i32, f2u(-120));
- TESTINSN_bin_f("vmla.f32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin_f("vmla.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin_f("vmla.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
- TESTINSN_bin_f("vmla.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e22), d1, i32, f2u(1e-19));
- TESTINSN_bin_f("vmla.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e12), d1, i32, f2u(1e11));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VMLS (fp) ----\n");
- TESTINSN_bin_f("vmls.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin_f("vmls.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin_f("vmls.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin_f("vmls.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin_f("vmls.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin_f("vmls.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin_f("vmls.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin_f("vmls.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin_f("vmls.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin_f("vmls.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin_f("vmls.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin_f("vmls.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin_f("vmls.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin_f("vmls.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin_f("vmls.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin_f("vmls.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin_f("vmls.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin_f("vmls.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VMLS (fp by scalar) ----\n");
- TESTINSN_bin_f("vmls.f32 q0, q1, d4[0]", q0, q1, i32, f2u(24), d4, i32, f2u(120));
- TESTINSN_bin_f("vmls.f32 q15, q8, d7[1]", q15, q8, i32, f2u(140), d7, i32, f2u(-120));
- TESTINSN_bin_f("vmls.f32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin_f("vmls.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin_f("vmls.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
- TESTINSN_bin_f("vmls.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e22), d1, i32, f2u(1e-19));
- TESTINSN_bin_f("vmls.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e12), d1, i32, f2u(1e11));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VCVT (integer <-> fp) ----\n");
- TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vcvt.u32.f32 q10, q11", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vcvt.u32.f32 q15, q4", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vcvt.u32.f32 q15, q4", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vcvt.u32.f32 q15, q4", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vcvt.u32.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vcvt.u32.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vcvt.s32.f32 q10, q11", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vcvt.s32.f32 q15, q4", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vcvt.s32.f32 q15, q4", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vcvt.s32.f32 q15, q4", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vcvt.s32.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vcvt.s32.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vcvt.f32.u32 q0, q1", q0, q1, i32, 7);
- TESTINSN_un("vcvt.f32.u32 q10, q11", q10, q11, i32, 1 << 31);
- TESTINSN_un("vcvt.f32.u32 q0, q1", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vcvt.f32.u32 q0, q1", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vcvt.f32.u32 q0, q14", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vcvt.f32.s32 q0, q1", q0, q1, i32, 7);
- TESTINSN_un("vcvt.f32.s32 q10, q11", q10, q11, i32, 1 << 31);
- TESTINSN_un("vcvt.f32.s32 q0, q1", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vcvt.f32.s32 q0, q1", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vcvt.f32.s32 q0, q14", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
- TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VCVT (fixed <-> fp) ----\n");
- TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vcvt.u32.f32 q10, q11, #1", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vcvt.u32.f32 q15, q4, #32", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vcvt.u32.f32 q15, q4, #7", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vcvt.u32.f32 q15, q4, #4", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vcvt.u32.f32 q12, q8, #3", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vcvt.u32.f32 q12, q8, #3", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vcvt.s32.f32 q0, q1, #5", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vcvt.s32.f32 q10, q11, #1", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vcvt.s32.f32 q15, q4, #8", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vcvt.s32.f32 q15, q4, #2", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vcvt.s32.f32 q15, q4, #1", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vcvt.s32.f32 q12, q8, #2", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vcvt.s32.f32 q12, q8, #2", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vcvt.f32.u32 q0, q1, #5", q0, q1, i32, 7);
- TESTINSN_un("vcvt.f32.u32 q10, q11, #9", q10, q11, i32, 1 << 31);
- TESTINSN_un("vcvt.f32.u32 q0, q1, #4", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vcvt.f32.u32 q0, q1, #6", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vcvt.f32.u32 q0, q14, #5", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vcvt.f32.s32 q0, q1, #12", q0, q1, i32, 7);
- TESTINSN_un("vcvt.f32.s32 q10, q11, #8", q10, q11, i32, 1 << 31);
- TESTINSN_un("vcvt.f32.s32 q0, q1, #2", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vcvt.f32.s32 q0, q1, #1", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vcvt.f32.s32 q0, q14, #6", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(-INFINITY));
- TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VMAX (fp) ----\n");
- TESTINSN_bin("vmax.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vmax.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vmax.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vmax.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vmax.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vmax.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vmax.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vmax.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vmax.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vmax.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vmax.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vmax.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vmax.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vmax.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vmax.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vmax.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vmax.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vmax.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VMIN (fp) ----\n");
- TESTINSN_bin("vmin.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vmin.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vmin.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vmin.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vmin.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vmin.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vmin.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vmin.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vmin.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vmin.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vmin.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vmin.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vmin.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vmin.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vmin.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vmin.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vmin.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vmin.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VRECPE ----\n");
- TESTINSN_un("vrecpe.u32 q0, q1", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vrecpe.u32 q10, q11", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vrecpe.u32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vrecpe.u32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vrecpe.u32 q0, q1", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vrecpe.u32 q10, q11", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vrecpe.f32 q15, q4", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vrecpe.f32 q15, q4", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vrecpe.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vrecpe.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, 7);
- TESTINSN_un("vrecpe.f32 q10, q11", q10, q11, i32, 1 << 31);
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vrecpe.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, 7);
- TESTINSN_un("vrecpe.f32 q10, q11", q10, q11, i32, 1 << 31);
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vrecpe.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VRECPS ----\n");
- TESTINSN_bin("vrecps.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vrecps.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vrecps.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vrecps.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vrecps.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vrecps.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vrecps.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vrecps.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vrecps.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vrecps.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vrecps.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vrecps.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vrecps.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vrecps.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vrecps.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vrecps.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vrecps.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vrecps.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VABS (fp) ----\n");
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, 7);
- TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, 1 << 31);
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vabs.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, 7);
- TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, 1 << 31);
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vabs.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VCGT (fp) ----\n");
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
- TESTINSN_bin("vcgt.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
- TESTINSN_bin("vcgt.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
- TESTINSN_bin("vcgt.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vcgt.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vcgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vcgt.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vcgt.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vcgt.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vcgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vcgt.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vcgt.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vcgt.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vcgt.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vcgt.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vcgt.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vcgt.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vcgt.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vcgt.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vcgt.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vcgt.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VCGE (fp) ----\n");
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
- TESTINSN_bin("vcge.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
- TESTINSN_bin("vcge.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
- TESTINSN_bin("vcge.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vcge.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vcge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vcge.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vcge.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vcge.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vcge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vcge.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vcge.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vcge.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vcge.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vcge.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vcge.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vcge.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vcge.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vcge.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vcge.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vcge.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VACGT (fp) ----\n");
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
- TESTINSN_bin("vacgt.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
- TESTINSN_bin("vacgt.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
- TESTINSN_bin("vacgt.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vacgt.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vacgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vacgt.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vacgt.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vacgt.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vacgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vacgt.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vacgt.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vacgt.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vacgt.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vacgt.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vacgt.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vacgt.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vacgt.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vacgt.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vacgt.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vacgt.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VACGE (fp) ----\n");
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
- TESTINSN_bin("vacge.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
- TESTINSN_bin("vacge.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
- TESTINSN_bin("vacge.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vacge.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vacge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vacge.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vacge.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vacge.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vacge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vacge.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vacge.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vacge.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vacge.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vacge.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vacge.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vacge.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vacge.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vacge.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vacge.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vacge.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VCEQ (fp) ----\n");
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
- TESTINSN_bin("vceq.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
- TESTINSN_bin("vceq.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
- TESTINSN_bin("vceq.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vceq.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vceq.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vceq.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vceq.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vceq.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vceq.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vceq.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vceq.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vceq.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vceq.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vceq.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vceq.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vceq.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vceq.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vceq.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vceq.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vceq.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VCEQ (fp) #0 ----\n");
- TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
- TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, 0x1);
- TESTINSN_un("vceq.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
- TESTINSN_un("vceq.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
- TESTINSN_un("vceq.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
- TESTINSN_un("vceq.f32 q10, q15, #0", q10, q15, i32, 0x0);
- TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VCGT (fp) #0 ----\n");
- TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
- TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, 0x1);
- TESTINSN_un("vcgt.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
- TESTINSN_un("vcgt.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
- TESTINSN_un("vcgt.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
- TESTINSN_un("vcgt.f32 q10, q15, #0", q10, q15, i32, 0x0);
- TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VCLT (fp) #0 ----\n");
- TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
- TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, 0x1);
- TESTINSN_un("vclt.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
- TESTINSN_un("vclt.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
- TESTINSN_un("vclt.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
- TESTINSN_un("vclt.f32 q10, q15, #0", q10, q15, i32, 0x0);
- TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VCGE (fp) #0 ----\n");
- TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
- TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, 0x1);
- TESTINSN_un("vcge.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
- TESTINSN_un("vcge.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
- TESTINSN_un("vcge.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
- TESTINSN_un("vcge.f32 q10, q15, #0", q10, q15, i32, 0x0);
- TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VCLE (fp) #0 ----\n");
- TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
- TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, 0x1);
- TESTINSN_un("vcle.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
- TESTINSN_un("vcle.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
- TESTINSN_un("vcle.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
- TESTINSN_un("vcle.f32 q10, q15, #0", q10, q15, i32, 0x0);
- TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VNEG (fp) ----\n");
- TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, 0x01000000);
- TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, 0x1);
- TESTINSN_un("vneg.f32 q2, q1", q2, q1, i32, 1 << 31);
- TESTINSN_un("vneg.f32 q2, q1", q2, q1, i32, f2u(23.04));
- TESTINSN_un("vneg.f32 q2, q1", q2, q1, i32, f2u(-23.04));
- TESTINSN_un("vneg.f32 q10, q15", q10, q15, i32, 0x0);
- TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
-
- printf("---- VRSQRTS ----\n");
- TESTINSN_bin("vrsqrts.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
- TESTINSN_bin("vrsqrts.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
- TESTINSN_bin("vrsqrts.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
- TESTINSN_bin("vrsqrts.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
- TESTINSN_bin("vrsqrts.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
- TESTINSN_bin("vrsqrts.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
- TESTINSN_bin("vrsqrts.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
- TESTINSN_bin("vrsqrts.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
- TESTINSN_bin("vrsqrts.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
- TESTINSN_bin("vrsqrts.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
- TESTINSN_bin("vrsqrts.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
- TESTINSN_bin("vrsqrts.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
- TESTINSN_bin("vrsqrts.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
- TESTINSN_bin("vrsqrts.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
- TESTINSN_bin("vrsqrts.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
- TESTINSN_bin("vrsqrts.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
- TESTINSN_bin("vrsqrts.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
- TESTINSN_bin("vrsqrts.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
- TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
-
- printf("---- VRSQRTE (fp) ----\n");
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(3.2));
- TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, f2u(3e22));
- TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(3e9));
- TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-0.5));
- TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-7.1));
- TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, 7);
- TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, 1 << 31);
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vrsqrte.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, 7);
- TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, 1 << 31);
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
- TESTINSN_un("vrsqrte.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(NAN));
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(0.0));
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
- TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
-
- return 0;
-}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/arm/neon128.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/arm/neon128.stderr.exp
diff --git a/main/none/tests/arm/neon128.stdout.exp b/main/none/tests/arm/neon128.stdout.exp
index e2e512b..aee0ebc 100644
--- a/main/none/tests/arm/neon128.stdout.exp
+++ b/main/none/tests/arm/neon128.stdout.exp
@@ -4220,2752 +4220,6 @@
vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000
---- VRSQRTE (fp) ----
vrsqrte.f32 q0, q1 :: Qd 0x3f0f0000 0x3f0f0000 0x3f0f0000 0x3f0f0000 Qm (i32)0x404ccccd
-vrsqrte.f32 q10, q11 :: Qd 0x2ccb0000 0x2ccb0000 0x2ccb0000 0x2ccb0000 Qm (i32)0x64cb49b4
-vrsqrte.f32 q15, q4 :: Qd 0x37998000 0x37998000 0x37998000 0x37998000 Qm (i32)0x4f32d05e
-vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xbf000000
-vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xc0e33333
-vrsqrte.f32 q12, q8 :: Qd 0x3eb50000 0x3eb50000 0x3eb50000 0x3eb50000 Qm (i32)0x40fff800
-vrsqrte.f32 q12, q8 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xc0fff800
-vrsqrte.f32 q0, q1 :: Qd 0x3f0f0000 0x3f0f0000 0x3f0f0000 0x3f0f0000 Qm (i32)0x404ccccd
-vrsqrte.f32 q10, q11 :: Qd 0x2ccb0000 0x2ccb0000 0x2ccb0000 0x2ccb0000 Qm (i32)0x64cb49b4
-vrsqrte.f32 q15, q4 :: Qd 0x37998000 0x37998000 0x37998000 0x37998000 Qm (i32)0x4f32d05e
-vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xbf000000
-vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xc0e33333
-vrsqrte.f32 q12, q8 :: Qd 0x3eb50000 0x3eb50000 0x3eb50000 0x3eb50000 Qm (i32)0x40fff800
-vrsqrte.f32 q12, q8 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xc0fff800
-vrsqrte.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000007
-vrsqrte.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000000
-vrsqrte.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000001
-vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff
-vrsqrte.f32 q0, q14 :: Qd 0x46e48000 0x46e48000 0x46e48000 0x46e48000 Qm (i32)0x30a0bcef
-vrsqrte.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000007
-vrsqrte.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000000
-vrsqrte.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000001
-vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff
-vrsqrte.f32 q0, q14 :: Qd 0x46e48000 0x46e48000 0x46e48000 0x46e48000 Qm (i32)0x30a0bcef
-vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000
-vrsqrte.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000
-vrsqrte.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000
-vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000
------ VMOV (immediate) -----
-vmov.i32 q0, #0x7 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007
-vmov.i16 q1, #0x7 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007
-vmov.i8 q2, #0x7 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707
-vmov.i32 q5, #0x700 :: Qd 0x00000700 0x00000700 0x00000700 0x00000700
-vmov.i16 q7, #0x700 :: Qd 0x07000700 0x07000700 0x07000700 0x07000700
-vmov.i32 q10, #0x70000 :: Qd 0x00070000 0x00070000 0x00070000 0x00070000
-vmov.i32 q12, #0x7000000 :: Qd 0x07000000 0x07000000 0x07000000 0x07000000
-vmov.i32 q13, #0x7FF :: Qd 0x000007ff 0x000007ff 0x000007ff 0x000007ff
-vmov.i32 q14, #0x7FFFF :: Qd 0x0007ffff 0x0007ffff 0x0007ffff 0x0007ffff
-vmov.i64 q15, #0xFF0000FF00FFFF00 :: Qd 0xff0000ff 0x00ffff00 0xff0000ff 0x00ffff00
------ VMVN (immediate) -----
-vmvn.i32 q0, #0x7 :: Qd 0xfffffff8 0xfffffff8 0xfffffff8 0xfffffff8
-vmvn.i16 q1, #0x7 :: Qd 0xfff8fff8 0xfff8fff8 0xfff8fff8 0xfff8fff8
-vmvn.i8 q2, #0x7 :: Qd 0xf8f8f8f8 0xf8f8f8f8 0xf8f8f8f8 0xf8f8f8f8
-vmvn.i32 q5, #0x700 :: Qd 0xfffff8ff 0xfffff8ff 0xfffff8ff 0xfffff8ff
-vmvn.i16 q7, #0x700 :: Qd 0xf8fff8ff 0xf8fff8ff 0xf8fff8ff 0xf8fff8ff
-vmvn.i32 q10, #0x70000 :: Qd 0xfff8ffff 0xfff8ffff 0xfff8ffff 0xfff8ffff
-vmvn.i32 q13, #0x7000000 :: Qd 0xf8ffffff 0xf8ffffff 0xf8ffffff 0xf8ffffff
-vmvn.i32 q11, #0x7FF :: Qd 0xfffff800 0xfffff800 0xfffff800 0xfffff800
-vmvn.i32 q14, #0x7FFFF :: Qd 0xfff80000 0xfff80000 0xfff80000 0xfff80000
-vmvn.i64 q15, #0xFF0000FF00FFFF00 :: Qd 0x00ffff00 0xff0000ff 0x00ffff00 0xff0000ff
------ VORR (immediate) -----
-vorr.i32 q0, #0x7 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557
-vorr.i16 q2, #0x7 :: Qd 0x55575557 0x55575557 0x55575557 0x55575557
-vorr.i32 q8, #0x700 :: Qd 0x55555755 0x55555755 0x55555755 0x55555755
-vorr.i16 q6, #0x700 :: Qd 0x57555755 0x57555755 0x57555755 0x57555755
-vorr.i32 q14, #0x70000 :: Qd 0x55575555 0x55575555 0x55575555 0x55575555
-vorr.i32 q15, #0x7000000 :: Qd 0x57555555 0x57555555 0x57555555 0x57555555
------ VBIC (immediate) -----
-vbic.i32 q0, #0x7 :: Qd 0x55555550 0x55555550 0x55555550 0x55555550
-vbic.i16 q3, #0x7 :: Qd 0x55505550 0x55505550 0x55505550 0x55505550
-vbic.i32 q5, #0x700 :: Qd 0x55555055 0x55555055 0x55555055 0x55555055
-vbic.i16 q8, #0x700 :: Qd 0x50555055 0x50555055 0x50555055 0x50555055
-vbic.i32 q10, #0x70000 :: Qd 0x55505555 0x55505555 0x55505555 0x55505555
-vbic.i32 q15, #0x7000000 :: Qd 0x50555555 0x50555555 0x50555555 0x50555555
----- VMVN (register) ----
-vmvn q0, q1 :: Qd 0xffffffe7 0xffffffe7 0xffffffe7 0xffffffe7 Qm (i32)0x00000018
-vmvn q10, q15 :: Qd 0xffffffe7 0xffffffe7 0xffffffe7 0xffffffe7 Qm (i32)0x00000018
-vmvn q0, q14 :: Qd 0xffffffe7 0xffffffe7 0xffffffe7 0xffffffe7 Qm (i32)0x00000018
----- VMOV (register) ----
-vmov q0, q1 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018
-vmov q10, q15 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018
-vmov q0, q14 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018
----- VDUP (ARM core register) (tested indirectly) ----
-vmov q0, q1 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 Qm (i8)0x00000007
-vmov q10, q11 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007 Qm (i16)0x00000007
-vmov q0, q15 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x00000007
----- VADD ----
-vadd.i32 q0, q1, q2 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078
-vadd.i64 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078
-vadd.i32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078
-vadd.i16 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078
-vadd.i8 q0, q1, q2 :: Qd 0x00000004 0x00000004 0x00000004 0x00000004 Qm (i32)0x0000008c Qn (i32)0x00000078
-vadd.i8 q0, q1, q2 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002
-vadd.i16 q0, q1, q2 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002
-vadd.i32 q0, q1, q2 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002
-vadd.i64 q0, q1, q2 :: Qd 0x00000004 0x00000003 0x00000004 0x00000003 Qm (i32)0x80000001 Qn (i32)0x80000002
-vadd.i32 q10, q11, q12 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078
-vadd.i64 q13, q14, q15 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078
----- VSUB ----
-vsub.i32 q0, q1, q2 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078
-vsub.i64 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vsub.i32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vsub.i16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vsub.i8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vsub.i8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002
-vsub.i16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002
-vsub.i32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002
-vsub.i64 q0, q1, q2 :: Qd 0xfffffffe 0xffffffff 0xfffffffe 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002
-vsub.i32 q10, q11, q12 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078
-vsub.i64 q13, q14, q15 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
----- VAND ----
-vand q0, q1, q2 :: Qd 0x00240024 0x00240024 0x00240024 0x00240024 Qm (i8)0x00000024 Qn (i16)0x00000077
-vand q4, q6, q5 :: Qd 0x00570057 0x00570057 0x00570057 0x00570057 Qm (i8)0x000000ff Qn (i16)0x00000057
-vand q10, q11, q12 :: Qd 0xecececec 0xecececec 0xecececec 0xecececec Qm (i8)0x000000fe Qn (i8)0x000000ed
-vand q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff
----- VBIC ----
-vbic q0, q1, q2 :: Qd 0x24002400 0x24002400 0x24002400 0x24002400 Qm (i8)0x00000024 Qn (i16)0x00000077
-vbic q4, q6, q5 :: Qd 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 Qm (i8)0x000000ff Qn (i16)0x00000057
-vbic q10, q11, q12 :: Qd 0x12121212 0x12121212 0x12121212 0x12121212 Qm (i8)0x000000fe Qn (i8)0x000000ed
-vbic q15, q15, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff
----- VORR ----
-vorr q0, q1, q2 :: Qd 0x24772477 0x24772477 0x24772477 0x24772477 Qm (i8)0x00000024 Qn (i16)0x00000073
-vorr q7, q3, q0 :: Qd 0x24ff24ff 0x24ff24ff 0x24ff24ff 0x24ff24ff Qm (i8)0x00000024 Qn (i16)0x000000ff
-vorr q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff
-vorr q2, q3, q15 :: Qd 0x0000003f 0x0000003f 0x0000003f 0x0000003f Qm (i32)0x00000024 Qn (i32)0x0000001f
----- VORN ----
-vorn q0, q1, q2 :: Qd 0xffacffac 0xffacffac 0xffacffac 0xffacffac Qm (i8)0x00000024 Qn (i16)0x00000073
-vorn q7, q3, q0 :: Qd 0xff24ff24 0xff24ff24 0xff24ff24 0xff24ff24 Qm (i8)0x00000024 Qn (i16)0x000000ff
-vorn q4, q4, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i16)0x000000ff Qn (i16)0x000000ff
-vorn q2, q3, q15 :: Qd 0xffffffe4 0xffffffe4 0xffffffe4 0xffffffe4 Qm (i32)0x00000024 Qn (i32)0x0000001f
----- VEOR ----
-veor q0, q1, q2 :: Qd 0x24532453 0x24532453 0x24532453 0x24532453 Qm (i8)0x00000024 Qn (i16)0x00000077
-veor q4, q6, q5 :: Qd 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 Qm (i8)0x000000ff Qn (i16)0x00000057
-veor q10, q11, q12 :: Qd 0x13131313 0x13131313 0x13131313 0x13131313 Qm (i8)0x000000fe Qn (i8)0x000000ed
-veor q15, q15, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff Qn (i8)0x000000ff
-veor q0, q1, q2 :: Qd 0x24572457 0x24572457 0x24572457 0x24572457 Qm (i8)0x00000024 Qn (i16)0x00000073
-veor q7, q3, q0 :: Qd 0x24db24db 0x24db24db 0x24db24db 0x24db24db Qm (i8)0x00000024 Qn (i16)0x000000ff
-veor q4, q4, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i16)0x000000ff Qn (i16)0x000000ff
-veor q2, q3, q15 :: Qd 0x0000003b 0x0000003b 0x0000003b 0x0000003b Qm (i32)0x00000024 Qn (i32)0x0000001f
----- VBSL ----
-vbsl q0, q1, q2 :: Qd 0x04260426 0x04260426 0x04260426 0x04260426 Qm (i8)0x00000024 Qn (i16)0x00000077
-vbsl q4, q6, q5 :: Qd 0x55575557 0x55575557 0x55575557 0x55575557 Qm (i8)0x000000ff Qn (i16)0x00000057
-vbsl q10, q11, q12 :: Qd 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc Qm (i8)0x000000fe Qn (i8)0x000000ed
-vbsl q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff
-vbsl q0, q1, q2 :: Qd 0x04260426 0x04260426 0x04260426 0x04260426 Qm (i8)0x00000024 Qn (i16)0x00000073
-vbsl q7, q3, q0 :: Qd 0x04ae04ae 0x04ae04ae 0x04ae04ae 0x04ae04ae Qm (i8)0x00000024 Qn (i16)0x000000ff
-vbsl q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff
-vbsl q2, q3, q15 :: Qd 0x0000000e 0x0000000e 0x0000000e 0x0000000e Qm (i32)0x00000024 Qn (i32)0x0000001f
----- VBIT ----
-vbit q0, q1, q2 :: Qd 0x55245524 0x55245524 0x55245524 0x55245524 Qm (i8)0x00000024 Qn (i16)0x00000077
-vbit q4, q6, q5 :: Qd 0x55575557 0x55575557 0x55575557 0x55575557 Qm (i8)0x000000ff Qn (i16)0x00000057
-vbit q10, q11, q12 :: Qd 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc Qm (i8)0x000000fe Qn (i8)0x000000ed
-vbit q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff
-vbit q0, q1, q2 :: Qd 0x55245524 0x55245524 0x55245524 0x55245524 Qm (i8)0x00000024 Qn (i16)0x00000073
-vbit q7, q3, q0 :: Qd 0x55245524 0x55245524 0x55245524 0x55245524 Qm (i8)0x00000024 Qn (i16)0x000000ff
-vbit q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff
-vbit q2, q3, q15 :: Qd 0x55555544 0x55555544 0x55555544 0x55555544 Qm (i32)0x00000024 Qn (i32)0x0000001f
----- VBIF ----
-vbif q0, q1, q2 :: Qd 0x24552455 0x24552455 0x24552455 0x24552455 Qm (i8)0x00000024 Qn (i16)0x00000077
-vbif q4, q6, q5 :: Qd 0xfffdfffd 0xfffdfffd 0xfffdfffd 0xfffdfffd Qm (i8)0x000000ff Qn (i16)0x00000057
-vbif q10, q11, q12 :: Qd 0x57575757 0x57575757 0x57575757 0x57575757 Qm (i8)0x000000fe Qn (i8)0x000000ed
-vbif q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff
-vbif q0, q1, q2 :: Qd 0x24552455 0x24552455 0x24552455 0x24552455 Qm (i8)0x00000024 Qn (i16)0x00000073
-vbif q7, q3, q0 :: Qd 0x24552455 0x24552455 0x24552455 0x24552455 Qm (i8)0x00000024 Qn (i16)0x000000ff
-vbif q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff Qm (i16)0x000000ff Qn (i16)0x000000ff
-vbif q2, q3, q15 :: Qd 0x00000035 0x00000035 0x00000035 0x00000035 Qm (i32)0x00000024 Qn (i32)0x0000001f
----- VEXT ----
-vext.8 q0, q1, q2, #0 :: Qd 0x77777777 0x77777777 0x77777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff
-vext.8 q0, q1, q2, #1 :: Qd 0xff777777 0x77777777 0x77777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff
-vext.8 q0, q1, q2, #9 :: Qd 0xffffffff 0xffffffff 0xff777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff
-vext.8 q0, q1, q2, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffff77 Qm (i8)0x00000077 Qn (i8)0x000000ff
-vext.8 q10, q11, q12, #4 :: Qd 0xffffffff 0x77777777 0x77777777 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff
-vext.8 q0, q5, q15, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0x77777777 Qm (i8)0x00000077 Qn (i8)0x000000ff
----- VHADD ----
-vhadd.s32 q0, q1, q2 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078
-vhadd.s32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vhadd.s16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vhadd.s8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x0000008c Qn (i32)0x00000078
-vhadd.s8 q0, q1, q2 :: Qd 0x03030303 0x03030303 0x03030303 0x03030303 Qm (i8)0x0000008d Qn (i8)0x00000079
-vhadd.s8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vhadd.s16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vhadd.s32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vhadd.s32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078
-vhadd.u32 q0, q1, q2 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078
-vhadd.u32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vhadd.u16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vhadd.u8 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vhadd.u8 q0, q1, q2 :: Qd 0x83838383 0x83838383 0x83838383 0x83838383 Qm (i8)0x0000008d Qn (i8)0x00000079
-vhadd.u8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vhadd.u16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vhadd.u32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vhadd.u32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VHSUB ----
-vhsub.s32 q0, q1, q2 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078
-vhsub.s32 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078
-vhsub.s16 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078
-vhsub.s8 q0, q1, q2 :: Qd 0x0000008a 0x0000008a 0x0000008a 0x0000008a Qm (i32)0x0000008c Qn (i32)0x00000078
-vhsub.s8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002
-vhsub.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002
-vhsub.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002
-vhsub.s32 q10, q11, q12 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078
-vhsub.u32 q0, q1, q2 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078
-vhsub.u32 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078
-vhsub.u16 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078
-vhsub.u8 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i32)0x0000008c Qn (i32)0x00000078
-vhsub.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002
-vhsub.u16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002
-vhsub.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002
-vhsub.u32 q10, q11, q12 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VQADD ----
-vqadd.s32 q0, q1, q2 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqadd.s32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqadd.s16 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqadd.s8 q0, q1, q2 :: Qd 0x00000004 0x00000004 0x00000004 0x00000004 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqadd.s8 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqadd.s16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqadd.s32 q0, q1, q2 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqadd.s32 q10, q11, q12 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqadd.u32 q0, q1, q2 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqadd.u32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqadd.u16 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqadd.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000
-vqadd.u8 q0, q1, q2 :: Qd 0xff000003 0xff000003 0xff000003 0xff000003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqadd.u16 q0, q1, q2 :: Qd 0xffff0003 0xffff0003 0xffff0003 0xffff0003 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqadd.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqadd.u32 q10, q11, q12 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
----- VQSUB ----
-vqsub.s32 q0, q1, q2 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqsub.s32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqsub.s16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqsub.s8 q0, q1, q2 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000
-vqsub.s8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqsub.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqsub.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqsub.s32 q10, q11, q12 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqsub.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000
-vqsub.u32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqsub.u16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqsub.u8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
-vqsub.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqsub.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqsub.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqsub.u32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000
----- VRHADD ----
-vrhadd.s32 q0, q1, q2 :: Qd 0x00000049 0x00000049 0x00000049 0x00000049 Qm (i32)0x00000019 Qn (i32)0x00000078
-vrhadd.s32 q0, q1, q2 :: Qd 0x00000049 0x00000049 0x00000049 0x00000049 Qm (i32)0x00000019 Qn (i32)0x00000079
-vrhadd.s32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vrhadd.s16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vrhadd.s8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x0000008c Qn (i32)0x00000078
-vrhadd.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vrhadd.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vrhadd.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vrhadd.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vrhadd.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vrhadd.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vrhadd.s8 q5, q7, q5 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002
-vrhadd.s16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002
-vrhadd.s32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002
-vrhadd.s32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078
-vrhadd.u32 q0, q1, q2 :: Qd 0x00000049 0x00000049 0x00000049 0x00000049 Qm (i32)0x00000019 Qn (i32)0x00000078
-vrhadd.u32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vrhadd.u16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vrhadd.u8 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082 Qm (i32)0x0000008c Qn (i32)0x00000078
-vrhadd.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vrhadd.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vrhadd.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vrhadd.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vrhadd.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vrhadd.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vrhadd.u8 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002
-vrhadd.u16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002
-vrhadd.u32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000004 Qn (i32)0x80000002
-vrhadd.u32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VCGT ----
-vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078
-vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000079
-vcgt.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcgt.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcgt.s8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078
-vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078
-vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078
-vcgt.s8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078
-vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x0000008c
-vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x0000008c
-vcgt.s8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000078 Qn (i32)0x0000008c
-vcgt.s8 q5, q7, q5 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcgt.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcgt.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcgt.s8 q5, q7, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcgt.s8 q5, q7, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002
-vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002
-vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002
-vcgt.s32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
-vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078
-vcgt.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcgt.u16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcgt.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078
-vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078
-vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078
-vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x0000008c
-vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x0000008c
-vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x0000008c
-vcgt.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcgt.u16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcgt.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002
-vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002
-vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 Qn (i32)0x80000002
-vcgt.u32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VCGE ----
-vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078
-vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000079
-vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcge.s8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078
-vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078
-vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078
-vcge.s8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078
-vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x0000008c
-vcge.s16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000078 Qn (i32)0x0000008c
-vcge.s8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x0000008c
-vcge.s8 q5, q7, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcge.s8 q5, q7, q5 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcge.s16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcge.s8 q5, q7, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002
-vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002
-vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002
-vcge.s32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
-vcge.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000019 Qn (i32)0x00000078
-vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078
-vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078
-vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078
-vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c
-vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c
-vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x0000008c
-vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000003 Qn (i32)0x80000002
-vcge.u8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcge.u16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcge.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000003
-vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002
-vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002
-vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 Qn (i32)0x80000002
-vcge.u32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VSHL (register) ----
-vshl.s8 q0, q1, q2 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i32)0x00000018 Qn (i32)0x00000001
-vshl.s8 q8, q1, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000008
-vshl.s8 q10, q11, q7 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x00000018 Qn (i32)0x00000004
-vshl.s16 q3, q8, q11 :: Qd 0x00000038 0x00000038 0x00000038 0x00000038 Qm (i32)0x0000000e Qn (i32)0x00000002
-vshl.s16 q5, q12, q14 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000001
-vshl.s16 q15, q2, q1 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x0000000b
-vshl.s32 q9, q12, q15 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002 Qn (i32)0x00000002
-vshl.s32 q11, q2, q0 :: Qd 0xfffff000 0xfffff000 0xfffff000 0xfffff000 Qm (i32)0xffffffff Qn (i32)0x0000000c
-vshl.s32 q5, q2, q3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x00000015
-vshl.s64 q15, q12, q4 :: Qd 0x00500000 0x00500000 0x00500000 0x00500000 Qm (i32)0x00000005 Qn (i32)0x00000014
-vshl.s64 q8, q2, q4 :: Qd 0x000000f0 0x000000f0 0x000000f0 0x000000f0 Qm (i32)0x0000000f Qn (i32)0x00000004
-vshl.s64 q5, q12, q4 :: Qd 0x60000000 0x40000000 0x60000000 0x40000000 Qm (i32)0x80000001 Qn (i32)0x0000001e
-vshl.u8 q0, q1, q2 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i32)0x00000018 Qn (i32)0x00000001
-vshl.u8 q8, q1, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000008
-vshl.u8 q10, q11, q7 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x00000018 Qn (i32)0x00000004
-vshl.u16 q3, q8, q11 :: Qd 0x00000038 0x00000038 0x00000038 0x00000038 Qm (i32)0x0000000e Qn (i32)0x00000002
-vshl.u16 q5, q12, q14 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000001
-vshl.u16 q15, q2, q1 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x0000000b
-vshl.u32 q9, q12, q15 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002 Qn (i32)0x00000002
-vshl.u32 q11, q2, q0 :: Qd 0xfffff000 0xfffff000 0xfffff000 0xfffff000 Qm (i32)0xffffffff Qn (i32)0x0000000c
-vshl.u32 q5, q2, q3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x00000015
-vshl.u64 q15, q12, q4 :: Qd 0x00500000 0x00500000 0x00500000 0x00500000 Qm (i32)0x00000005 Qn (i32)0x00000014
-vshl.u64 q8, q2, q4 :: Qd 0x000000f0 0x000000f0 0x000000f0 0x000000f0 Qm (i32)0x0000000f Qn (i32)0x00000004
-vshl.u64 q5, q12, q4 :: Qd 0x60000000 0x40000000 0x60000000 0x40000000 Qm (i32)0x80000001 Qn (i32)0x0000001e
----- VQSHL (register) ----
-vqshl.s64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000
-vqshl.s64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000
-vqshl.s64 q3, q4, q5 :: Qd 0xfffffff0 0x3ffffff0 0xfffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000
-vqshl.s64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000
-vqshl.s64 q13, q14, q15 :: Qd 0xffffffff 0xfffffbff 0xffffffff 0xfffffbff Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000
-vqshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000
-vqshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000
-vqshl.s32 q2, q8, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000
-vqshl.s32 q12, q11, q13 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000
-vqshl.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000
-vqshl.s32 q9, q10, q11 :: Qd 0xc0000004 0xc0000004 0xc0000004 0xc0000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000
-vqshl.s32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000
-vqshl.s16 q11, q10, q2 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000
-vqshl.s16 q3, q14, q7 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000
-vqshl.s16 q0, q11, q2 :: Qd 0xc0000080 0xc0000080 0xc0000080 0xc0000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000
-vqshl.s16 q1, q2, q3 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000
-vqshl.s16 q3, q4, q5 :: Qd 0xd0000000 0xd0000000 0xd0000000 0xd0000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000
-vqshl.s16 q0, q15, q2 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000
-vqshl.s8 q2, q7, q11 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80 Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000
-vqshl.s8 q13, q1, q2 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80 Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000
-vqshl.s8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000
-vqshl.s8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000
-vqshl.s8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000
-vqshl.s8 q10, q11, q12 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000
-vqshl.u64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000
-vqshl.u64 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 08000000
-vqshl.u64 q3, q4, q5 :: Qd 0x1ffffff0 0x3ffffff0 0x1ffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000
-vqshl.u64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000
-vqshl.u64 q13, q14, q15 :: Qd 0x0000003f 0xfffffbff 0x0000003f 0xfffffbff Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000
-vqshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000
-vqshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000
-vqshl.u32 q2, q8, q4 :: Qd 0x0fffffff 0x0fffffff 0x0fffffff 0x0fffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000
-vqshl.u32 q12, q11, q13 :: Qd 0x007fffff 0x007fffff 0x007fffff 0x007fffff Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000
-vqshl.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000
-vqshl.u32 q9, q10, q11 :: Qd 0x40000004 0x40000004 0x40000004 0x40000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000
-vqshl.u32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000
-vqshl.u16 q11, q10, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000
-vqshl.u16 q3, q14, q7 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000
-vqshl.u16 q0, q11, q2 :: Qd 0x40000080 0x40000080 0x40000080 0x40000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000
-vqshl.u16 q1, q2, q3 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000
-vqshl.u16 q3, q4, q5 :: Qd 0x50000000 0x50000000 0x50000000 0x50000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000
-vqshl.u16 q0, q15, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000
-vqshl.u8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000
-vqshl.u8 q13, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000
-vqshl.u8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000
-vqshl.u8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000
-vqshl.u8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000
-vqshl.u8 q10, q11, q12 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000
----- VQSHL / VQSHLU (immediate) ----
-vqshl.s64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshl.s64 q15, q14, #1 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.s64 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.s64 q5, q4, #63 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s64 q5, q4, #60 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s64 q5, q4, #59 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s64 q5, q4, #58 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s64 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.s64 q5, q4, #63 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000 Qm (i32)0xffffffff fpscr: 00000000
-vqshl.s64 q5, q4, #60 :: Qd 0xf0000000 0x00000000 0xf0000000 0x00000000 Qm (i32)0xffffffff fpscr: 00000000
-vqshl.s64 q5, q4, #7 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000 Qm (i32)0x80000002 fpscr: 08000000
-vqshl.s32 q10, q11, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshl.s32 q15, q14, #1 :: Qd 0xffffff02 0xffffff02 0xffffff02 0xffffff02 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.s32 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.s32 q5, q4, #31 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s32 q5, q4, #28 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s32 q5, q4, #27 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s32 q5, q4, #26 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.s32 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.s32 q5, q4, #31 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xffffffff fpscr: 00000000
-vqshl.s32 q5, q4, #29 :: Qd 0xe0000000 0xe0000000 0xe0000000 0xe0000000 Qm (i32)0xffffffff fpscr: 00000000
-vqshl.s32 q5, q4, #7 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x80000002 fpscr: 08000000
-vqshl.s16 q9, q8, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshl.s16 q15, q14, #1 :: Qd 0xfffeff02 0xfffeff02 0xfffeff02 0xfffeff02 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.s16 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.s16 q9, q8, #15 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s16 q5, q4, #12 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s16 q5, q4, #11 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s16 q5, q4, #10 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.s16 q5, q4, #4 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.s16 q5, q4, #15 :: Qd 0x80008000 0x80008000 0x80008000 0x80008000 Qm (i32)0xffffffff fpscr: 00000000
-vqshl.s16 q5, q4, #12 :: Qd 0xf000f000 0xf000f000 0xf000f000 0xf000f000 Qm (i32)0xffffffff fpscr: 00000000
-vqshl.s16 q5, q4, #7 :: Qd 0x80000100 0x80000100 0x80000100 0x80000100 Qm (i32)0x80000002 fpscr: 08000000
-vqshl.s8 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshl.s8 q15, q14, #1 :: Qd 0xfefefe80 0xfefefe80 0xfefefe80 0xfefefe80 Qm (i32)0xffffff81 fpscr: 08000000
-vqshl.s8 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.s8 q5, q4, #7 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s8 q5, q4, #4 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s8 q5, q4, #3 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000010 fpscr: 08000000
-vqshl.s8 q5, q4, #2 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.s8 q5, q4, #1 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.s8 q5, q4, #7 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff fpscr: 00000000
-vqshl.s8 q5, q4, #5 :: Qd 0xe0e0e0e0 0xe0e0e0e0 0xe0e0e0e0 0xe0e0e0e0 Qm (i32)0xffffffff fpscr: 00000000
-vqshl.s8 q5, q4, #2 :: Qd 0x80000008 0x80000008 0x80000008 0x80000008 Qm (i32)0x80000002 fpscr: 08000000
-vqshl.u64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshl.u64 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr: 08000000
-vqshl.u64 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.u64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u64 q5, q4, #59 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u64 q5, q4, #58 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u64 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000
-vqshl.u64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000
-vqshl.u64 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000
-vqshl.u32 q10, q11, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshl.u32 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr: 08000000
-vqshl.u32 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.u32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u32 q5, q4, #28 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u32 q5, q4, #27 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u32 q5, q4, #26 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u32 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000
-vqshl.u32 q5, q4, #29 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000
-vqshl.u32 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000002 fpscr: 08000000
-vqshl.u16 q9, q8, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshl.u16 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr: 08000000
-vqshl.u16 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.u16 q9, q8, #15 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u16 q5, q4, #12 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u16 q5, q4, #11 :: Qd 0x00008000 0x00008000 0x00008000 0x00008000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u16 q5, q4, #10 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u16 q5, q4, #4 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u16 q5, q4, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000
-vqshl.u16 q5, q4, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000
-vqshl.u16 q5, q4, #7 :: Qd 0xffff0100 0xffff0100 0xffff0100 0xffff0100 Qm (i32)0x80000002 fpscr: 08000000
-vqshl.u8 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshl.u8 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 fpscr: 08000000
-vqshl.u8 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81 Qm (i32)0xffffff81 fpscr: 00000000
-vqshl.u8 q5, q4, #7 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u8 q5, q4, #4 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr: 08000000
-vqshl.u8 q5, q4, #3 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u8 q5, q4, #2 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u8 q5, q4, #1 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020 Qm (i32)0x00000010 fpscr: 00000000
-vqshl.u8 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000
-vqshl.u8 q5, q4, #5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff fpscr: 08000000
-vqshl.u8 q5, q4, #2 :: Qd 0xff000008 0xff000008 0xff000008 0xff000008 Qm (i32)0x80000002 fpscr: 08000000
-vqshlu.s64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshlu.s64 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
-vqshlu.s64 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
-vqshlu.s64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s64 q5, q4, #59 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s64 q5, q4, #58 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s64 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s64 q5, q4, #63 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000
-vqshlu.s64 q5, q4, #60 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000
-vqshlu.s64 q5, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 fpscr: 08000000
-vqshlu.s32 q10, q11, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshlu.s32 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
-vqshlu.s32 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
-vqshlu.s32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s32 q5, q4, #28 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s32 q5, q4, #27 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s32 q5, q4, #26 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s32 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s32 q5, q4, #31 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000
-vqshlu.s32 q5, q4, #29 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000
-vqshlu.s32 q5, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000002 fpscr: 08000000
-vqshlu.s16 q9, q8, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshlu.s16 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
-vqshlu.s16 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
-vqshlu.s16 q9, q8, #15 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s16 q5, q4, #12 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s16 q5, q4, #11 :: Qd 0x00008000 0x00008000 0x00008000 0x00008000 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s16 q5, q4, #10 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s16 q5, q4, #4 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s16 q5, q4, #15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000
-vqshlu.s16 q5, q4, #12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000
-vqshlu.s16 q5, q4, #7 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100 Qm (i32)0x80000002 fpscr: 08000000
-vqshlu.s8 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 fpscr: 00000000
-vqshlu.s8 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
-vqshlu.s8 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff81 fpscr: 08000000
-vqshlu.s8 q5, q4, #7 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s8 q5, q4, #4 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000010 fpscr: 08000000
-vqshlu.s8 q5, q4, #3 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s8 q5, q4, #2 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s8 q5, q4, #1 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020 Qm (i32)0x00000010 fpscr: 00000000
-vqshlu.s8 q5, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000
-vqshlu.s8 q5, q4, #5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff fpscr: 08000000
-vqshlu.s8 q5, q4, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002 fpscr: 08000000
----- VQRSHL (register) ----
-vqrshl.s64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000
-vqrshl.s64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 00000000
-vqrshl.s64 q3, q4, q5 :: Qd 0xfffffff0 0x3ffffff0 0xfffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000
-vqrshl.s64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000
-vqrshl.s64 q13, q14, q15 :: Qd 0xffffffff 0xfffffc00 0xffffffff 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000
-vqrshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000
-vqrshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000
-vqrshl.s32 q2, q8, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000
-vqrshl.s32 q12, q11, q13 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000
-vqrshl.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000
-vqrshl.s32 q9, q10, q11 :: Qd 0xc0000004 0xc0000004 0xc0000004 0xc0000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000
-vqrshl.s16 q11, q10, q2 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000
-vqrshl.s16 q3, q14, q7 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000
-vqrshl.s16 q0, q11, q2 :: Qd 0xc0000080 0xc0000080 0xc0000080 0xc0000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s16 q1, q2, q3 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000
-vqrshl.s16 q3, q4, q5 :: Qd 0xd0000000 0xd0000000 0xd0000000 0xd0000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000
-vqrshl.s16 q0, q15, q2 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000
-vqrshl.s8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s8 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s16 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s32 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s8 q2, q7, q11 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s16 q2, q7, q11 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.s8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000
-vqrshl.s16 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000
-vqrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000
-vqrshl.s8 q2, q7, q11 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80 Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000
-vqrshl.s8 q13, q1, q2 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80 Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000
-vqrshl.s8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000
-vqrshl.s8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000
-vqrshl.s8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000
-vqrshl.s8 q10, q11, q12 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000
-vqrshl.u64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001 fpscr: 00000000
-vqrshl.u64 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffff81 Qn (i32)0x00000001 fpscr: 08000000
-vqrshl.u64 q3, q4, q5 :: Qd 0x1ffffff0 0x3ffffff0 0x1ffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd fpscr: 00000000
-vqrshl.u64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e fpscr: 00000000
-vqrshl.u64 q13, q14, q15 :: Qd 0x0000003f 0xfffffc00 0x0000003f 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6 fpscr: 00000000
-vqrshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4 fpscr: 00000000
-vqrshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2 fpscr: 00000000
-vqrshl.u32 q2, q8, q4 :: Qd 0x0fffffff 0x0fffffff 0x0fffffff 0x0fffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc fpscr: 00000000
-vqrshl.u32 q12, q11, q13 :: Qd 0x00800000 0x00800000 0x00800000 0x00800000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7 fpscr: 00000000
-vqrshl.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9 fpscr: 00000000
-vqrshl.u32 q9, q10, q11 :: Qd 0x40000004 0x40000004 0x40000004 0x40000004 Qm (i32)0x80000008 Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.u32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003 fpscr: 00000000
-vqrshl.u16 q11, q10, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1 fpscr: 00000000
-vqrshl.u16 q3, q14, q7 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd fpscr: 00000000
-vqrshl.u16 q0, q11, q2 :: Qd 0x40000080 0x40000080 0x40000080 0x40000080 Qm (i32)0x80000100 Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.u16 q1, q2, q3 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1 fpscr: 00000000
-vqrshl.u16 q3, q4, q5 :: Qd 0x50000000 0x50000000 0x50000000 0x50000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3 fpscr: 00000000
-vqrshl.u16 q0, q15, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000001 Qn (i32)0x0000001e fpscr: 08000000
-vqrshl.u8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000028 fpscr: 08000000
-vqrshl.u8 q2, q7, q11 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.u8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.u16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.u32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.u8 q2, q7, q11 :: Qd 0x8080807f 0x8080807f 0x8080807f 0x8080807f Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.u16 q2, q7, q11 :: Qd 0x80007fff 0x80007fff 0x80007fff 0x80007fff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.u32 q2, q7, q11 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff fpscr: 00000000
-vqrshl.u8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000
-vqrshl.u16 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000
-vqrshl.u32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000 fpscr: 00000000
-vqrshl.u8 q13, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffffc Qn (i32)0x0000001e fpscr: 08000000
-vqrshl.u8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003 fpscr: 00000000
-vqrshl.u8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010 fpscr: 00000000
-vqrshl.u8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002 fpscr: 00000000
-vqrshl.u8 q10, q11, q12 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 08000000
----- VRSHL (register) ----
-vrshl.s64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001
-vrshl.s64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001
-vrshl.s64 q3, q4, q5 :: Qd 0xfffffff0 0x3ffffff0 0xfffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd
-vrshl.s64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e
-vrshl.s64 q13, q14, q15 :: Qd 0xffffffff 0xfffffc00 0xffffffff 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6
-vrshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4
-vrshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2
-vrshl.s32 q2, q8, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc
-vrshl.s32 q12, q11, q13 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7
-vrshl.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9
-vrshl.s32 q9, q10, q11 :: Qd 0xc0000004 0xc0000004 0xc0000004 0xc0000004 Qm (i32)0x80000008 Qn (i32)0xffffffff
-vrshl.s32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003
-vrshl.s16 q11, q10, q2 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1
-vrshl.s16 q3, q14, q7 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd
-vrshl.s16 q0, q11, q2 :: Qd 0xc0000080 0xc0000080 0xc0000080 0xc0000080 Qm (i32)0x80000100 Qn (i32)0xffffffff
-vrshl.s16 q1, q2, q3 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1
-vrshl.s16 q3, q4, q5 :: Qd 0xd0000000 0xd0000000 0xd0000000 0xd0000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3
-vrshl.s16 q0, q15, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x0000001e
-vrshl.s8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff
-vrshl.s16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff
-vrshl.s32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff
-vrshl.s8 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff
-vrshl.s16 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff
-vrshl.s32 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff Qn (i32)0xffffffff
-vrshl.s8 q2, q7, q11 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0xfffffffe Qn (i32)0xffffffff
-vrshl.s16 q2, q7, q11 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0xfffffffe Qn (i32)0xffffffff
-vrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff
-vrshl.s8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000
-vrshl.s16 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000
-vrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff Qn (i32)0x00000000
-vrshl.s8 q2, q7, q11 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0xffffffff Qn (i32)0x00000028
-vrshl.s8 q13, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0xfffffffc Qn (i32)0x0000001e
-vrshl.s8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003
-vrshl.s8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010
-vrshl.s8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002
-vrshl.s8 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
-vrshl.u64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000001 Qn (i32)0x00000001
-vrshl.u64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02 Qm (i32)0xffffff81 Qn (i32)0x00000001
-vrshl.u64 q3, q4, q5 :: Qd 0x1ffffff0 0x3ffffff0 0x1ffffff0 0x3ffffff0 Qm (i32)0xffffff81 Qn (i32)0xfffffffd
-vrshl.u64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000 Qm (i32)0x00000010 Qn (i32)0x0000000e
-vrshl.u64 q13, q14, q15 :: Qd 0x0000003f 0xfffffc00 0x0000003f 0xfffffc00 Qm (i32)0xffffffef Qn (i32)0xffffffe6
-vrshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0xffffffc4
-vrshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000007f Qn (i32)0xffffffe2
-vrshl.u32 q2, q8, q4 :: Qd 0x0fffffff 0x0fffffff 0x0fffffff 0x0fffffff Qm (i32)0xfffffff5 Qn (i32)0xfffffffc
-vrshl.u32 q12, q11, q13 :: Qd 0x00800000 0x00800000 0x00800000 0x00800000 Qm (i32)0xffffff88 Qn (i32)0xfffffff7
-vrshl.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000022 Qn (i32)0xfffffff9
-vrshl.u32 q9, q10, q11 :: Qd 0x40000004 0x40000004 0x40000004 0x40000004 Qm (i32)0x80000008 Qn (i32)0xffffffff
-vrshl.u32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x08000000 Qn (i32)0x00000003
-vrshl.u16 q11, q10, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xffffffe1
-vrshl.u16 q3, q14, q7 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000000 Qn (i32)0xfffffffd
-vrshl.u16 q0, q11, q2 :: Qd 0x40000080 0x40000080 0x40000080 0x40000080 Qm (i32)0x80000100 Qn (i32)0xffffffff
-vrshl.u16 q1, q2, q3 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000100 Qn (i32)0xffffffe1
-vrshl.u16 q3, q4, q5 :: Qd 0x50000000 0x50000000 0x50000000 0x50000000 Qm (i32)0xa0000000 Qn (i32)0xfffffff3
-vrshl.u16 q0, q15, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x0000001e
-vrshl.u8 q2, q7, q11 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0xffffffff Qn (i32)0x00000028
-vrshl.u8 q2, q7, q11 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff Qn (i32)0xffffffff
-vrshl.u8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff
-vrshl.u16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff
-vrshl.u32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x0000000f Qn (i32)0xffffffff
-vrshl.u8 q2, q7, q11 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff Qn (i32)0xffffffff
-vrshl.u16 q2, q7, q11 :: Qd 0x80008000 0x80008000 0x80008000 0x80008000 Qm (i32)0xffffffff Qn (i32)0xffffffff
-vrshl.u32 q2, q7, q11 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xffffffff Qn (i32)0xffffffff
-vrshl.u8 q2, q7, q11 :: Qd 0x8080807f 0x8080807f 0x8080807f 0x8080807f Qm (i32)0xfffffffe Qn (i32)0xffffffff
-vrshl.u16 q2, q7, q11 :: Qd 0x80007fff 0x80007fff 0x80007fff 0x80007fff Qm (i32)0xfffffffe Qn (i32)0xffffffff
-vrshl.u32 q2, q7, q11 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0xfffffffe Qn (i32)0xffffffff
-vrshl.u8 q13, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0xfffffffc Qn (i32)0x0000001e
-vrshl.u8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058 Qm (i32)0x8000000b Qn (i32)0x00000003
-vrshl.u8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000 Qm (i32)0x00010000 Qn (i32)0x00000010
-vrshl.u8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x40000000 Qn (i32)0x00000002
-vrshl.u8 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VMAX (integer) ----
-vmax.s32 q0, q1, q2 :: Qd 0x00000079 0x00000079 0x00000079 0x00000079 Qm (i32)0x00000019 Qn (i32)0x00000079
-vmax.s32 q0, q1, q2 :: Qd 0x000000fa 0x000000fa 0x000000fa 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000079
-vmax.s32 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c
-vmax.s16 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x00000078
-vmax.s8 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078
-vmax.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmax.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmax.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmax.s8 q5, q7, q5 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmax.s16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmax.s32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmax.s8 q5, q7, q5 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmax.s16 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmax.s32 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmax.s32 q10, q11, q12 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmax.u32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000019 Qn (i32)0x00000078
-vmax.u32 q0, q1, q2 :: Qd 0x000000fa 0x000000fa 0x000000fa 0x000000fa Qm (i32)0x000000fa Qn (i32)0x00000078
-vmax.u32 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c
-vmax.u16 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x00000078
-vmax.u8 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078
-vmax.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmax.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmax.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmax.u8 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmax.u16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmax.u32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmax.u8 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmax.u16 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmax.u32 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmax.u32 q10, q11, q12 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VMIN (integer) ----
-vmin.s32 q0, q1, q2 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000079
-vmin.s32 q0, q1, q2 :: Qd 0x00000079 0x00000079 0x00000079 0x00000079 Qm (i32)0x000000fa Qn (i32)0x00000079
-vmin.s32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x0000008c Qn (i32)0x00000078
-vmin.s16 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078
-vmin.s8 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c
-vmin.s8 q5, q7, q5 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmin.s16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmin.s32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmin.s8 q5, q7, q5 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmin.s16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmin.s32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmin.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmin.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmin.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmin.s32 q10, q11, q12 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmin.u32 q0, q1, q2 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019 Qm (i32)0x00000019 Qn (i32)0x00000078
-vmin.u32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x000000fa Qn (i32)0x00000078
-vmin.u32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x0000008c Qn (i32)0x00000078
-vmin.u16 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078 Qm (i32)0x00000078 Qn (i32)0x00000078
-vmin.u8 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c Qn (i32)0x0000008c
-vmin.u8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmin.u16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmin.u32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmin.u8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmin.u16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmin.u32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x80000001 Qn (i32)0x80000003
-vmin.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmin.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmin.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vmin.u32 q10, q11, q12 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VABD ----
-vabd.s32 q0, q1, q2 :: Qd 0x0000005f 0x0000005f 0x0000005f 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078
-vabd.s32 q0, q1, q2 :: Qd 0x00000060 0x00000060 0x00000060 0x00000060 Qm (i32)0x00000019 Qn (i32)0x00000079
-vabd.s32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vabd.s16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabd.s8 q0, q1, q2 :: Qd 0x000000ec 0x000000ec 0x000000ec 0x000000ec Qm (i32)0x0000008c Qn (i32)0x00000078
-vabd.s8 q5, q7, q5 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabd.s8 q5, q7, q5 :: Qd 0x7f010101 0x7f010101 0x7f010101 0x7f010101 Qm (i32)0xffffff01 Qn (i32)0x80000002
-vabd.s8 q5, q7, q5 :: Qd 0x7f010137 0x7f010137 0x7f010137 0x7f010137 Qm (i32)0x80000001 Qn (i32)0xffffff38
-vabd.s16 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabd.s32 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabd.s8 q5, q7, q5 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabd.s16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabd.s32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabd.s8 q5, q7, q5 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabd.s16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabd.s32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabd.s32 q10, q11, q12 :: Qd 0x00000060 0x00000060 0x00000060 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078
-vabd.u32 q0, q1, q2 :: Qd 0x0000005f 0x0000005f 0x0000005f 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078
-vabd.u32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabd.u16 q0, q1, q2 :: Qd 0xfffffefc 0xfffffefc 0xfffffefc 0xfffffefc Qm (i32)0xffffff74 Qn (i32)0x00000078
-vabd.u8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabd.u8 q5, q7, q5 :: Qd 0x7fffff01 0x7fffff01 0x7fffff01 0x7fffff01 Qm (i32)0xffffff01 Qn (i32)0x80000002
-vabd.u8 q5, q7, q5 :: Qd 0x7fffff37 0x7fffff37 0x7fffff37 0x7fffff37 Qm (i32)0x80000001 Qn (i32)0xffffff38
-vabd.u8 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabd.u16 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabd.u32 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabd.u8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabd.u16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabd.u32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabd.u8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabd.u16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabd.u32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabd.u32 q10, q11, q12 :: Qd 0x00000060 0x00000060 0x00000060 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VABA ----
-vaba.s32 q0, q1, q2 :: Qd 0x555555b4 0x555555b4 0x555555b4 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078
-vaba.s32 q0, q1, q2 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x00000019 Qn (i32)0x00000079
-vaba.s32 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vaba.s16 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vaba.s8 q0, q1, q2 :: Qd 0x55555541 0x55555541 0x55555541 0x55555541 Qm (i32)0x0000008c Qn (i32)0x00000078
-vaba.s8 q5, q7, q5 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003 Qm (i32)0x80000001 Qn (i32)0x80000002
-vaba.s8 q5, q7, q5 :: Qd 0xff010103 0xff010103 0xff010103 0xff010103 Qm (i32)0xffffff01 Qn (i32)0x80000002
-vaba.s8 q5, q7, q5 :: Qd 0x7e00006f 0x7e00006f 0x7e00006f 0x7e00006f Qm (i32)0x80000001 Qn (i32)0xffffff38
-vaba.s16 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vaba.s32 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vaba.s8 q5, q7, q5 :: Qd 0x80000005 0x80000005 0x80000005 0x80000005 Qm (i32)0x80000001 Qn (i32)0x80000003
-vaba.s16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vaba.s32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vaba.s8 q5, q7, q5 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004 Qm (i32)0x80000004 Qn (i32)0x80000002
-vaba.s16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vaba.s32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vaba.s32 q10, q11, q12 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078
-vaba.u32 q0, q1, q2 :: Qd 0x555555b4 0x555555b4 0x555555b4 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078
-vaba.u32 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vaba.u16 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vaba.u8 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vaba.u8 q5, q7, q5 :: Qd 0xffffff03 0xffffff03 0xffffff03 0xffffff03 Qm (i32)0xffffff01 Qn (i32)0x80000002
-vaba.u8 q5, q7, q5 :: Qd 0x7efefe6f 0x7efefe6f 0x7efefe6f 0x7efefe6f Qm (i32)0x80000001 Qn (i32)0xffffff38
-vaba.u8 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vaba.u16 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vaba.u32 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vaba.u8 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vaba.u16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vaba.u32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vaba.u8 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vaba.u16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vaba.u32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vaba.u32 q10, q11, q12 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VABAL ----
-vabal.s32 q0, d1, d2 :: Qd 0x00000019 0x00000078 0x55555555 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078
-vabal.s32 q0, d1, d2 :: Qd 0x00000019 0x00000079 0x55555555 0x555555b5 Qm (i32)0x00000019 Qn (i32)0x00000079
-vabal.s32 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabal.s16 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabal.s8 q0, d1, d2 :: Qd 0x0000008c 0x00000178 0x55555555 0x55555641 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabal.s8 q5, d7, d5 :: Qd 0x55555555 0x55555556 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabal.s8 q5, d7, d5 :: Qd 0x55d45556 0x55565556 0x55d45556 0x55565556 Qm (i32)0xffffff01 Qn (i32)0x80000002
-vabal.s8 q5, d7, d5 :: Qd 0x55d45556 0x5556558c 0x55d45556 0x5556558c Qm (i32)0x80000001 Qn (i32)0xffffff38
-vabal.s16 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabal.s32 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabal.s8 q5, d7, d5 :: Qd 0x55555555 0x55555557 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabal.s16 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabal.s32 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabal.s8 q5, d7, d5 :: Qd 0x55555555 0x55555557 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabal.s16 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabal.s32 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabal.s32 q10, d31, d12 :: Qd 0x55555555 0x555555b5 0x55555555 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078
-vabal.u32 q0, d1, d2 :: Qd 0x00000019 0x00000078 0x55555555 0x555555b4 Qm (i32)0x00000019 Qn (i32)0x00000078
-vabal.u32 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabal.u16 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabal.u8 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabal.u8 q5, d7, d5 :: Qd 0x55d45654 0x56545556 0x55d45654 0x56545556 Qm (i32)0xffffff01 Qn (i32)0x80000002
-vabal.u8 q5, d7, d5 :: Qd 0x55d45654 0x5654558c 0x55d45654 0x5654558c Qm (i32)0x80000001 Qn (i32)0xffffff38
-vabal.u8 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabal.u16 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabal.u32 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabal.u8 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabal.u16 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabal.u32 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabal.u8 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabal.u16 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabal.u32 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabal.u32 q10, d11, d12 :: Qd 0x55555555 0x555555b5 0x55555555 0x555555b5 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VABDL ----
-vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x0000005f 0x00000000 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078
-vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000060 0x00000000 0x00000060 Qm (i32)0x00000019 Qn (i32)0x00000079
-vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabdl.s8 q0, d1, d2 :: Qd 0x00000000 0x000000ec 0x00000000 0x000000ec Qm (i32)0x0000008c Qn (i32)0x00000078
-vabdl.s8 q5, d7, d5 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabdl.s8 q5, d7, d5 :: Qd 0x007f0001 0x00010001 0x007f0001 0x00010001 Qm (i32)0xffffff01 Qn (i32)0x80000002
-vabdl.s8 q5, d7, d5 :: Qd 0x007f0001 0x00010037 0x007f0001 0x00010037 Qm (i32)0x80000001 Qn (i32)0xffffff38
-vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabdl.s8 q5, d7, d5 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabdl.s8 q5, d7, d5 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabdl.s32 q10, d31, d12 :: Qd 0x00000000 0x00000060 0x00000000 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078
-vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x0000005f 0x00000000 0x0000005f Qm (i32)0x00000019 Qn (i32)0x00000078
-vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
-vabdl.u8 q5, d7, d5 :: Qd 0x007f00ff 0x00ff0001 0x007f00ff 0x00ff0001 Qm (i32)0xffffff01 Qn (i32)0x80000002
-vabdl.u8 q5, d7, d5 :: Qd 0x007f00ff 0x00ff0037 0x007f00ff 0x00ff0037 Qm (i32)0x80000001 Qn (i32)0xffffff38
-vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001 Qm (i32)0x80000001 Qn (i32)0x80000002
-vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000001 Qn (i32)0x80000003
-vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002 Qm (i32)0x80000004 Qn (i32)0x80000002
-vabdl.u32 q10, d11, d12 :: Qd 0x00000000 0x00000060 0x00000000 0x00000060 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VTST ----
-vtst.32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078
-vtst.32 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0x00000078
-vtst.16 q6, q7, q8 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000078 Qn (i32)0x00000078
-vtst.8 q9, q10, q12 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x0000008c Qn (i32)0x00000078
-vtst.8 q0, q1, q2 :: Qd 0xff000000 0xff000000 0xff000000 0xff000000 Qm (i32)0x80000001 Qn (i32)0x80000002
-vtst.16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00004001 Qn (i32)0x00004001
-vtst.32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002
-vtst.8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x00000002
-vtst.16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00004001 Qn (i32)0x00004001
-vtst.32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x80000002
-vtst.32 q10, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000018 Qn (i32)0x00000078
----- VCEQ ----
-vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
-vceq.i32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078
-vceq.i16 q6, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078
-vceq.i8 q9, q10, q12 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078
-vceq.i8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000002
-vceq.i16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00004001 Qn (i32)0x00004001
-vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002
-vceq.i8 q0, q1, q2 :: Qd 0x00ffff00 0x00ffff00 0x00ffff00 0x00ffff00 Qm (i32)0x80000001 Qn (i32)0x00000002
-vceq.i16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000001 Qn (i32)0x00004001
-vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001 Qn (i32)0x80000002
-vceq.i32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
----- VMLA ----
-vmla.i32 q0, q1, q2 :: Qd 0x55554a15 0x55554a15 0x55554a15 0x55554a15 Qm (i32)0xffffffe8 Qn (i32)0x00000078
-vmla.i32 q6, q7, q8 :: Qd 0x555596f5 0x555596f5 0x555596f5 0x555596f5 Qm (i32)0x0000008c Qn (i32)0x00000078
-vmla.i16 q9, q11, q12 :: Qd 0x5555bd55 0x5555bd55 0x5555bd55 0x5555bd55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmla.i16 q7, q1, q2 :: Qd 0x5555bd55 0x5555bd55 0x5555bd55 0x5555bd55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmla.i8 q0, q1, q2 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmla.i8 q10, q11, q12 :: Qd 0x5555559f 0x5555559f 0x5555559f 0x5555559f Qm (i32)0x00000021 Qn (i32)0x0000000a
-vmla.i16 q4, q5, q6 :: Qd 0x5555f557 0x5555f557 0x5555f557 0x5555f557 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmla.i16 q14, q5, q9 :: Qd 0x5555f557 0x5555f557 0x5555f557 0x5555f557 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmla.i32 q7, q8, q9 :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmla.i8 q10, q13, q12 :: Qd 0x5555559f 0x5555559f 0x5555559f 0x5555559f Qm (i32)0x00000021 Qn (i32)0x0000000a
-vmla.i16 q4, q5, q6 :: Qd 0x55551751 0x55551751 0x55551751 0x55551751 Qm (i32)0x100000fe Qn (i32)0x00002002
-vmla.i32 q7, q8, q9 :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmla.i32 q10, q11, q15 :: Qd 0x55554a15 0x55554a15 0x55554a15 0x55554a15 Qm (i32)0x00000018 Qn (i32)0xffffff88
----- VMLS ----
-vmls.i32 q0, q1, q2 :: Qd 0x55556095 0x55556095 0x55556095 0x55556095 Qm (i32)0xffffffe8 Qn (i32)0x00000078
-vmls.i32 q6, q7, q8 :: Qd 0x555596f5 0x555596f5 0x555596f5 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmls.i16 q9, q11, q12 :: Qd 0x5555ed55 0x5555ed55 0x5555ed55 0x5555ed55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmls.i8 q0, q1, q2 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5 Qm (i32)0x0000008c Qn (i32)0x00000078
-vmls.i8 q10, q11, q12 :: Qd 0x5555550b 0x5555550b 0x5555550b 0x5555550b Qm (i32)0x00000021 Qn (i32)0x0000000a
-vmls.i16 q4, q5, q6 :: Qd 0x5555b553 0x5555b553 0x5555b553 0x5555b553 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmls.i32 q7, q8, q9 :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmls.i8 q10, q13, q12 :: Qd 0x5555550b 0x5555550b 0x5555550b 0x5555550b Qm (i32)0x00000021 Qn (i32)0x0000000a
-vmls.i16 q4, q5, q6 :: Qd 0x55559359 0x55559359 0x55559359 0x55559359 Qm (i32)0x100000fe Qn (i32)0x00002002
-vmls.i32 q7, q8, q9 :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmls.i32 q10, q11, q15 :: Qd 0x55556095 0x55556095 0x55556095 0x55556095 Qm (i32)0xffffffe8 Qn (i32)0x00000078
----- VMUL ----
-vmul.i32 q0, q1, q2 :: Qd 0x00000b40 0x00000b40 0x00000b40 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmul.i32 q6, q7, q8 :: Qd 0xffffbe60 0xffffbe60 0xffffbe60 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmul.i16 q9, q11, q12 :: Qd 0x00006800 0x00006800 0x00006800 0x00006800 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmul.i8 q0, q1, q2 :: Qd 0x000000a0 0x000000a0 0x000000a0 0x000000a0 Qm (i32)0x0000008c Qn (i32)0x00000078
-vmul.i8 q10, q11, q12 :: Qd 0x0000004a 0x0000004a 0x0000004a 0x0000004a Qm (i32)0x00000021 Qn (i32)0x0000000a
-vmul.i16 q4, q5, q6 :: Qd 0x0000a002 0x0000a002 0x0000a002 0x0000a002 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmul.i32 q7, q8, q9 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmul.i8 q10, q11, q12 :: Qd 0x0000c00e 0x0000c00e 0x0000c00e 0x0000c00e Qm (i32)0x0200feb2 Qn (i32)0x000020df
-vmul.i16 q4, q5, q6 :: Qd 0x00008866 0x00008866 0x00008866 0x00008866 Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmul.i32 q7, q8, q9 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c
-vmul.i8 q10, q13, q12 :: Qd 0x0000004a 0x0000004a 0x0000004a 0x0000004a Qm (i32)0x00000021 Qn (i32)0x0000000a
-vmul.i16 q4, q5, q6 :: Qd 0x0000c1fc 0x0000c1fc 0x0000c1fc 0x0000c1fc Qm (i32)0x100000fe Qn (i32)0x00002002
-vmul.i32 q7, q8, q9 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmul.i32 q10, q11, q15 :: Qd 0x00000b40 0x00000b40 0x00000b40 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmul.p8 q0, q1, q2 :: Qd 0x00000005 0x00000005 0x00000005 0x00000005 Qm (i32)0x00000003 Qn (i32)0x00000003
-vmul.p8 q0, q1, q2 :: Qd 0x00000044 0x00000044 0x00000044 0x00000044 Qm (i32)0x0000000c Qn (i8)0x0000000f
----- VMUL (by scalar) ----
-vmul.i32 q0, q1, d4[0] :: Qd 0x00000b40 0x00000b40 0x00000b40 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmul.i32 q15, q8, d7[1] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmul.i16 q10, q9, d7[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmul.i16 q4, q5, d6[2] :: Qd 0x0000a002 0x0000a002 0x0000a002 0x0000a002 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmul.i32 q4, q8, d15[1] :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmul.i16 q4, q5, d6[0] :: Qd 0xdffe8866 0xdffe8866 0xdffe8866 0xdffe8866 Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmul.i32 q7, q8, d1[1] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmul.i16 q4, q5, d6[0] :: Qd 0x2000c1fc 0x2000c1fc 0x2000c1fc 0x2000c1fc Qm (i32)0x100000fe Qn (i32)0x00002002
-vmul.i32 q7, q8, d1[1] :: Qd 0x80000002 0x80000002 0x80000002 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
----- VMLA (by scalar) ----
-vmla.i32 q0, q1, d4[0] :: Qd 0x55556095 0x55556095 0x55556095 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmla.i32 q15, q8, d7[1] :: Qd 0x555513b5 0x555513b5 0x555513b5 0x555513b5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmla.i16 q10, q9, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmla.i16 q4, q5, d6[2] :: Qd 0x5555f557 0x5555f557 0x5555f557 0x5555f557 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmla.i32 q4, q8, d15[1] :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmla.i16 q4, q5, d6[0] :: Qd 0x3553ddbb 0x3553ddbb 0x3553ddbb 0x3553ddbb Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmla.i32 q7, q8, d1[1] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmla.i16 q4, q5, d6[0] :: Qd 0x75551751 0x75551751 0x75551751 0x75551751 Qm (i32)0x100000fe Qn (i32)0x00002002
-vmla.i32 q7, q8, d1[1] :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
----- VMLS (by scalar) ----
-vmls.i32 q0, q1, d4[0] :: Qd 0x55554a15 0x55554a15 0x55554a15 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmls.i32 q15, q8, d7[1] :: Qd 0x555596f5 0x555596f5 0x555596f5 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmls.i16 q10, q9, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmls.i16 q4, q5, d6[2] :: Qd 0x5555b553 0x5555b553 0x5555b553 0x5555b553 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmls.i32 q4, q8, d15[1] :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmls.i16 q4, q5, d6[0] :: Qd 0x7557ccef 0x7557ccef 0x7557ccef 0x7557ccef Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmls.i32 q7, q8, d1[1] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmls.i16 q4, q5, d6[0] :: Qd 0x35559359 0x35559359 0x35559359 0x35559359 Qm (i32)0x100000fe Qn (i32)0x00002002
-vmls.i32 q7, q8, d1[1] :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
----- VMULL (by scalar) ----
-vmull.s32 q0, d2, d4[0] :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmull.s32 q15, d8, d7[1] :: Qd 0xffffffff 0xffffbe60 0xffffffff 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmull.s16 q10, d31, d7[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmull.s16 q4, d5, d6[2] :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmull.s32 q4, d7, d15[1] :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmull.s16 q4, d5, d6[0] :: Qd 0xffffdffe 0xf2858866 0xffffdffe 0xf2858866 Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmull.s32 q7, d7, d1[1] :: Qd 0xfff9fffa 0x00000000 0xfff9fffa 0x00000000 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmull.s16 q4, d5, d6[0] :: Qd 0x02002000 0x001fc1fc 0x02002000 0x001fc1fc Qm (i32)0x100000fe Qn (i32)0x00002002
-vmull.s32 q7, d7, d1[1] :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmull.u32 q0, d1, d4[0] :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmull.u32 q15, d8, d7[1] :: Qd 0x00000046 0x0000008c 0x00000046 0x0000008c Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmull.u16 q10, d31, d7[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmull.u16 q4, d5, d6[2] :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmull.u32 q4, d7, d15[1] :: Qd 0x40000001 0x80000002 0x40000001 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmull.u16 q4, d5, d6[0] :: Qd 0x2001dffe 0x12878866 0x2001dffe 0x12878866 Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmull.u32 q7, d7, d1[1] :: Qd 0x00060006 0x00000000 0x00060006 0x00000000 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmull.u16 q4, d5, d6[0] :: Qd 0x02002000 0x001fc1fc 0x02002000 0x001fc1fc Qm (i32)0x100000fe Qn (i32)0x00002002
-vmull.u32 q7, d7, d1[1] :: Qd 0x40000001 0x80000002 0x40000001 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
----- VMLAL (by scalar) ----
-vmlal.s32 q0, d2, d4[0] :: Qd 0x55555555 0x55556095 0x55555555 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmlal.s32 q15, d8, d7[1] :: Qd 0x55555555 0x555513b5 0x55555555 0x555513b5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmlal.s16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlal.s16 q4, d5, d6[2] :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlal.s32 q4, d7, d15[1] :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlal.s16 q4, d5, d6[0] :: Qd 0x55553553 0x47daddbb 0x55553553 0x47daddbb Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmlal.s32 q7, d7, d1[1] :: Qd 0x554f554f 0x55555555 0x554f554f 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmlal.s16 q4, d5, d6[0] :: Qd 0x57557555 0x55751751 0x57557555 0x55751751 Qm (i32)0x100000fe Qn (i32)0x00002002
-vmlal.s32 q7, d7, d1[1] :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlal.u32 q0, d1, d4[0] :: Qd 0x00000018 0x00000b58 0x55555555 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmlal.u32 q15, d8, d7[1] :: Qd 0x5555559b 0x555555e1 0x5555559b 0x555555e1 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmlal.u16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlal.u16 q4, d5, d6[2] :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlal.u32 q4, d7, d15[1] :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlal.u16 q4, d5, d6[0] :: Qd 0x75573553 0x67dcddbb 0x75573553 0x67dcddbb Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmlal.u32 q7, d7, d1[1] :: Qd 0x555b555b 0x55555555 0x555b555b 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmlal.u16 q4, d5, d6[0] :: Qd 0x57557555 0x55751751 0x57557555 0x55751751 Qm (i32)0x100000fe Qn (i32)0x00002002
-vmlal.u32 q7, d7, d1[1] :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
----- VMLSL (by scalar) ----
-vmlsl.s32 q0, d2, d4[0] :: Qd 0x55555555 0x55554a15 0x55555555 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmlsl.s32 q15, d8, d7[1] :: Qd 0x55555555 0x555596f5 0x55555555 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmlsl.s16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlsl.s16 q4, d5, d6[2] :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlsl.s32 q4, d7, d15[1] :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlsl.s16 q4, d5, d6[0] :: Qd 0x55557557 0x62cfccef 0x55557557 0x62cfccef Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmlsl.s32 q7, d7, d1[1] :: Qd 0x555b555b 0x55555555 0x555b555b 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmlsl.s16 q4, d5, d6[0] :: Qd 0x53553555 0x55359359 0x53553555 0x55359359 Qm (i32)0x100000fe Qn (i32)0x00002002
-vmlsl.s32 q7, d7, d1[1] :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlsl.u32 q0, d1, d4[0] :: Qd 0x00000017 0xfffff4d8 0x55555555 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmlsl.u32 q15, d8, d7[1] :: Qd 0x5555550f 0x555554c9 0x5555550f 0x555554c9 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmlsl.u16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlsl.u16 q4, d5, d6[2] :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlsl.u32 q4, d7, d15[1] :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlsl.u16 q4, d5, d6[0] :: Qd 0x35537557 0x42cdccef 0x35537557 0x42cdccef Qm (i32)0xffff9433 Qn (i32)0x00002002
-vmlsl.u32 q7, d7, d1[1] :: Qd 0x554f554f 0x55555555 0x554f554f 0x55555555 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmlsl.u16 q4, d5, d6[0] :: Qd 0x53553555 0x55359359 0x53553555 0x55359359 Qm (i32)0x100000fe Qn (i32)0x00002002
-vmlsl.u32 q7, d7, d1[1] :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
----- VRSHR ----
-vrshr.s8 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff
-vrshr.s8 q0, q1, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff
-vrshr.s16 q3, q4, #2 :: Qd 0x0000ffe1 0x0000ffe1 0x0000ffe1 0x0000ffe1 Qm (i32)0xffffff84
-vrshr.s32 q2, q5, #31 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xffffffff
-vrshr.s8 q6, q7, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000ffff
-vrshr.s16 q8, q9, #12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xfffffff6
-vrshr.s32 q10, q11, #5 :: Qd 0x00000140 0x00000140 0x00000140 0x00000140 Qm (i32)0x000027fa
-vrshr.u8 q12, q13, #1 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i32)0xffffffff
-vrshr.u16 q14, q15, #11 :: Qd 0x00200020 0x00200020 0x00200020 0x00200020 Qm (i32)0xffffffff
-vrshr.u32 q10, q11, #9 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x000003e8
-vrshr.u8 q7, q13, #7 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202 Qm (i32)0xffffffff
-vrshr.u16 q8, q1, #5 :: Qd 0x0000055e 0x0000055e 0x0000055e 0x0000055e Qm (i32)0x0000abcf
-vrshr.u32 q12, q3, #15 :: Qd 0x00020000 0x00020000 0x00020000 0x00020000 Qm (i32)0xfffffe50
-vrshr.u64 q0, q1, #42 :: Qd 0x00000000 0x00400000 0x00000000 0x00400000 Qm (i32)0xffffffff
-vrshr.s64 q6, q7, #12 :: Qd 0x00000000 0xfac00001 0x00000000 0xfac00001 Qm (i32)0x00000fac
-vrshr.u64 q8, q4, #9 :: Qd 0x0000001a 0x7c00001a 0x0000001a 0x7c00001a Qm (i32)0x000034f8
-vrshr.s64 q9, q12, #11 :: Qd 0x00000030 0x32c00030 0x00000030 0x32c00030 Qm (i32)0x00018196
----- VRSRA ----
-vrsra.s8 q0, q1, #1 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xffffffff
-vrsra.s16 q3, q4, #2 :: Qd 0x55555536 0x55555536 0x55555536 0x55555536 Qm (i32)0xffffff84
-vrsra.s32 q2, q5, #31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xffffffff
-vrsra.s8 q6, q7, #7 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x0000ffff
-vrsra.s16 q8, q9, #12 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xfffffff6
-vrsra.s32 q10, q11, #5 :: Qd 0x55555695 0x55555695 0x55555695 0x55555695 Qm (i32)0x000027fa
-vrsra.u8 q12, q13, #1 :: Qd 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 Qm (i32)0xffffffff
-vrsra.u16 q14, q15, #11 :: Qd 0x55755575 0x55755575 0x55755575 0x55755575 Qm (i32)0xffffffff
-vrsra.u32 q10, q11, #9 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557 Qm (i32)0x000003e8
-vrsra.u8 q7, q13, #7 :: Qd 0x57575757 0x57575757 0x57575757 0x57575757 Qm (i32)0xffffffff
-vrsra.u16 q8, q1, #5 :: Qd 0x55555ab3 0x55555ab3 0x55555ab3 0x55555ab3 Qm (i32)0x0000abcf
-vrsra.u32 q12, q3, #15 :: Qd 0x55575555 0x55575555 0x55575555 0x55575555 Qm (i32)0xfffffe50
-vrsra.u64 q0, q1, #42 :: Qd 0x55555555 0x55955555 0x55555555 0x55955555 Qm (i32)0xffffffff
-vrsra.s64 q6, q7, #12 :: Qd 0x55555556 0x50155556 0x55555556 0x50155556 Qm (i32)0x00000fac
-vrsra.u64 q8, q4, #9 :: Qd 0x5555556f 0xd155556f 0x5555556f 0xd155556f Qm (i32)0x000034f8
-vrsra.s64 q9, q12, #11 :: Qd 0x55555585 0x88155585 0x55555585 0x88155585 Qm (i32)0x00018196
----- VSHR ----
-vshr.s8 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff
-vshr.s8 q0, q1, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff
-vshr.s16 q3, q4, #2 :: Qd 0xffffffe1 0xffffffe1 0xffffffe1 0xffffffe1 Qm (i32)0xffffff84
-vshr.s32 q2, q5, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff
-vshr.s8 q6, q7, #7 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x0000ffff
-vshr.s16 q8, q9, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xfffffff6
-vshr.s32 q10, q11, #5 :: Qd 0x0000013f 0x0000013f 0x0000013f 0x0000013f Qm (i32)0x000027fa
-vshr.u8 q12, q13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff
-vshr.u16 q14, q15, #11 :: Qd 0x001f001f 0x001f001f 0x001f001f 0x001f001f Qm (i32)0xffffffff
-vshr.u32 q10, q11, #9 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x000003e8
-vshr.u8 q7, q13, #7 :: Qd 0x01010101 0x01010101 0x01010101 0x01010101 Qm (i32)0xffffffff
-vshr.u16 q8, q1, #5 :: Qd 0x0000055e 0x0000055e 0x0000055e 0x0000055e Qm (i32)0x0000abcf
-vshr.u32 q12, q3, #15 :: Qd 0x0001ffff 0x0001ffff 0x0001ffff 0x0001ffff Qm (i32)0xfffffe50
-vshr.u64 q0, q1, #42 :: Qd 0x00000000 0x003fffff 0x00000000 0x003fffff Qm (i32)0xffffffff
-vshr.s64 q6, q7, #12 :: Qd 0x00000000 0xfac00000 0x00000000 0xfac00000 Qm (i32)0x00000fac
-vshr.u64 q8, q4, #9 :: Qd 0x0000001a 0x7c00001a 0x0000001a 0x7c00001a Qm (i32)0x000034f8
-vshr.s64 q9, q12, #11 :: Qd 0x00000030 0x32c00030 0x00000030 0x32c00030 Qm (i32)0x00018196
----- VSRA ----
-vsra.s8 q0, q1, #1 :: Qd 0x54545454 0x54545454 0x54545454 0x54545454 Qm (i32)0xffffffff
-vsra.s16 q3, q4, #2 :: Qd 0x55545536 0x55545536 0x55545536 0x55545536 Qm (i32)0xffffff84
-vsra.s32 q2, q5, #31 :: Qd 0x55555554 0x55555554 0x55555554 0x55555554 Qm (i32)0xffffffff
-vsra.s8 q6, q7, #7 :: Qd 0x55555454 0x55555454 0x55555454 0x55555454 Qm (i32)0x0000ffff
-vsra.s16 q8, q9, #12 :: Qd 0x55545554 0x55545554 0x55545554 0x55545554 Qm (i32)0xfffffff6
-vsra.s32 q10, q11, #5 :: Qd 0x55555694 0x55555694 0x55555694 0x55555694 Qm (i32)0x000027fa
-vsra.u8 q12, q13, #1 :: Qd 0xd4d4d4d4 0xd4d4d4d4 0xd4d4d4d4 0xd4d4d4d4 Qm (i32)0xffffffff
-vsra.u16 q14, q15, #11 :: Qd 0x55745574 0x55745574 0x55745574 0x55745574 Qm (i32)0xffffffff
-vsra.u32 q10, q11, #9 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556 Qm (i32)0x000003e8
-vsra.u8 q7, q13, #7 :: Qd 0x56565656 0x56565656 0x56565656 0x56565656 Qm (i32)0xffffffff
-vsra.u16 q8, q1, #5 :: Qd 0x55555ab3 0x55555ab3 0x55555ab3 0x55555ab3 Qm (i32)0x0000abcf
-vsra.u32 q12, q3, #15 :: Qd 0x55575554 0x55575554 0x55575554 0x55575554 Qm (i32)0xfffffe50
-vsra.u64 q0, q1, #42 :: Qd 0x55555555 0x55955554 0x55555555 0x55955554 Qm (i32)0xffffffff
-vsra.s64 q6, q7, #12 :: Qd 0x55555556 0x50155555 0x55555556 0x50155555 Qm (i32)0x00000fac
-vsra.u64 q8, q4, #9 :: Qd 0x5555556f 0xd155556f 0x5555556f 0xd155556f Qm (i32)0x000034f8
-vsra.s64 q9, q12, #11 :: Qd 0x55555585 0x88155585 0x55555585 0x88155585 Qm (i32)0x00018196
----- VSRI ----
-vsri.16 q0, q1, #1 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff Qm (i32)0xffffffff
-vsri.16 q3, q4, #2 :: Qd 0x7fff7fe1 0x7fff7fe1 0x7fff7fe1 0x7fff7fe1 Qm (i32)0xffffff84
-vsri.32 q2, q5, #31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xffffffff
-vsri.8 q6, q7, #7 :: Qd 0x54545555 0x54545555 0x54545555 0x54545555 Qm (i32)0x0000ffff
-vsri.16 q8, q9, #12 :: Qd 0x555f555f 0x555f555f 0x555f555f 0x555f555f Qm (i32)0xfffffff6
-vsri.32 q10, q11, #5 :: Qd 0x5000013f 0x5000013f 0x5000013f 0x5000013f Qm (i32)0x000027fa
-vsri.8 q12, q13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f Qm (i32)0xffffffff
-vsri.16 q14, q15, #11 :: Qd 0x555f555f 0x555f555f 0x555f555f 0x555f555f Qm (i32)0xffffffff
-vsri.32 q10, q11, #9 :: Qd 0x55000001 0x55000001 0x55000001 0x55000001 Qm (i32)0x000003e8
-vsri.8 q7, q13, #7 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0xffffffff
-vsri.16 q8, q1, #5 :: Qd 0x5000555e 0x5000555e 0x5000555e 0x5000555e Qm (i32)0x0000abcf
-vsri.32 q12, q3, #15 :: Qd 0x5555ffff 0x5555ffff 0x5555ffff 0x5555ffff Qm (i32)0xfffffe50
-vsri.64 q0, q1, #42 :: Qd 0x55555555 0x557fffff 0x55555555 0x557fffff Qm (i32)0xffffffff
-vsri.64 q6, q7, #12 :: Qd 0x55500000 0xfac00000 0x55500000 0xfac00000 Qm (i32)0x00000fac
-vsri.64 q8, q4, #9 :: Qd 0x5500001a 0x7c00001a 0x5500001a 0x7c00001a Qm (i32)0x000034f8
-vsri.64 q9, q12, #11 :: Qd 0x55400030 0x32c00030 0x55400030 0x32c00030 Qm (i32)0x00018196
----- VMOVL ----
-vmovl.u32 q0, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042 Qm (i32)0x00000042
-vmovl.u16 q15, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042 Qm (i32)0x00000042
-vmovl.u8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000042
-vmovl.s32 q0, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042 Qm (i32)0x00000042
-vmovl.s16 q15, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042 Qm (i32)0x00000042
-vmovl.s8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i32)0x00000042
-vmovl.u32 q0, d2 :: Qd 0x00000000 0xedededed 0x00000000 0xedededed Qm (i8)0x000000ed
-vmovl.u16 q15, d2 :: Qd 0x0000eded 0x0000eded 0x0000eded 0x0000eded Qm (i8)0x000000ed
-vmovl.u8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i8)0x000000ed
-vmovl.s32 q0, d2 :: Qd 0xffffffff 0xedededed 0xffffffff 0xedededed Qm (i8)0x000000ed
-vmovl.s16 q15, d2 :: Qd 0xffffeded 0xffffeded 0xffffeded 0xffffeded Qm (i8)0x000000ed
-vmovl.s8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555 Qm (i8)0x000000ed
----- VABS ----
-vabs.s32 q0, q1 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073
-vabs.s16 q15, q4 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073
-vabs.s8 q8, q7 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073
-vabs.s32 q0, q1 :: Qd 0x000000fe 0x000000fe 0x000000fe 0x000000fe Qm (i32)0x000000fe
-vabs.s16 q15, q4 :: Qd 0x000000ef 0x000000ef 0x000000ef 0x000000ef Qm (i32)0x000000ef
-vabs.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022 Qm (i32)0x000000de
-vabs.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a
-vabs.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b
-vabs.s8 q8, q7 :: Qd 0x220c220c 0x220c220c 0x220c220c 0x220c220c Qm (i16)0x0000de0c
----- VQABS ----
-vqabs.s32 q0, q1 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073 fpscr: 00000000
-vqabs.s32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 fpscr: 08000000
-vqabs.s16 q0, q1 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 fpscr: 08000000
-vqabs.s8 q0, q1 :: Qd 0x7f000000 0x7f000000 0x7f000000 0x7f000000 Qm (i32)0x80000000 fpscr: 08000000
-vqabs.s16 q15, q4 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073 fpscr: 00000000
-vqabs.s8 q8, q7 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073 Qm (i32)0x00000073 fpscr: 00000000
-vqabs.s32 q0, q1 :: Qd 0x000000fe 0x000000fe 0x000000fe 0x000000fe Qm (i32)0x000000fe fpscr: 00000000
-vqabs.s16 q15, q4 :: Qd 0x000000ef 0x000000ef 0x000000ef 0x000000ef Qm (i32)0x000000ef fpscr: 00000000
-vqabs.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022 Qm (i32)0x000000de fpscr: 00000000
-vqabs.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a fpscr: 00000000
-vqabs.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b fpscr: 00000000
-vqabs.s8 q8, q7 :: Qd 0x220c220c 0x220c220c 0x220c220c 0x220c220c Qm (i16)0x0000de0c fpscr: 00000000
----- VADDW ----
-vaddw.s32 q0, q1, d4 :: Qd 0x00000073 0x12121285 0x00000073 0x12121285 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddw.s16 q15, q14, d4 :: Qd 0x00001285 0x00001285 0x00001285 0x00001285 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddw.s8 q0, q1, d31 :: Qd 0x00120085 0x00120085 0x00120085 0x00120085 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddw.u32 q0, q1, d4 :: Qd 0x00000073 0x12121285 0x00000073 0x12121285 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddw.u16 q0, q1, d4 :: Qd 0x00001285 0x00001285 0x00001285 0x00001285 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddw.u8 q0, q1, d4 :: Qd 0x00120085 0x00120085 0x00120085 0x00120085 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddw.s32 q0, q1, d4 :: Qd 0x00000072 0xe2e2e355 0x00000072 0xe2e2e355 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddw.s16 q15, q14, d4 :: Qd 0xffffe355 0xffffe355 0xffffe355 0xffffe355 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddw.s8 q0, q1, d31 :: Qd 0xffe20055 0xffe20055 0xffe20055 0xffe20055 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddw.u32 q0, q1, d4 :: Qd 0x00000073 0xe2e2e355 0x00000073 0xe2e2e355 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddw.u16 q0, q1, d4 :: Qd 0x0000e355 0x0000e355 0x0000e355 0x0000e355 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddw.u8 q0, q1, d4 :: Qd 0x00e20155 0x00e20155 0x00e20155 0x00e20155 Qm (i32)0x00000073 Qn (i8)0x000000e2
----- VADDL ----
-vaddl.s32 q0, d2, d4 :: Qd 0x00000000 0x12121285 0x00000000 0x12121285 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddl.s16 q15, d14, d4 :: Qd 0x00001212 0x00001285 0x00001212 0x00001285 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddl.s8 q0, d2, d31 :: Qd 0x00120012 0x00120085 0x00120012 0x00120085 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddl.u32 q0, d2, d4 :: Qd 0x00000000 0x12121285 0x00000000 0x12121285 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddl.u16 q0, d2, d4 :: Qd 0x00001212 0x00001285 0x00001212 0x00001285 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddl.u8 q0, d2, d4 :: Qd 0x00120012 0x00120085 0x00120012 0x00120085 Qm (i32)0x00000073 Qn (i8)0x00000012
-vaddl.s32 q0, d2, d4 :: Qd 0xffffffff 0xe2e2e355 0xffffffff 0xe2e2e355 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddl.s16 q15, d14, d4 :: Qd 0xffffe2e2 0xffffe355 0xffffe2e2 0xffffe355 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddl.s8 q0, d2, d31 :: Qd 0xffe2ffe2 0xffe20055 0xffe2ffe2 0xffe20055 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddl.u32 q0, d2, d4 :: Qd 0x00000000 0xe2e2e355 0x00000000 0xe2e2e355 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddl.u16 q0, d2, d4 :: Qd 0x0000e2e2 0x0000e355 0x0000e2e2 0x0000e355 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddl.u8 q0, d2, d4 :: Qd 0x00e200e2 0x00e20155 0x00e200e2 0x00e20155 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vaddl.s32 q0, d2, d4 :: Qd 0xffffffff 0xa5a5a5a5 0xffffffff 0xa5a5a5a5 Qm (i8)0x00000093 Qn (i8)0x00000012
-vaddl.s16 q15, d14, d4 :: Qd 0xffffa5a5 0xffffa5a5 0xffffa5a5 0xffffa5a5 Qm (i8)0x00000093 Qn (i8)0x00000012
-vaddl.s8 q0, d2, d31 :: Qd 0xffabffab 0xffabffab 0xffabffab 0xffabffab Qm (i8)0x00000099 Qn (i8)0x00000012
-vaddl.u32 q0, d2, d4 :: Qd 0x00000000 0xa5a5a5a5 0x00000000 0xa5a5a5a5 Qm (i8)0x00000093 Qn (i8)0x00000012
-vaddl.u16 q0, d2, d4 :: Qd 0x0000a5a5 0x0000a5a5 0x0000a5a5 0x0000a5a5 Qm (i8)0x00000093 Qn (i8)0x00000012
-vaddl.u8 q0, d2, d4 :: Qd 0x00a500a5 0x00a500a5 0x00a500a5 0x00a500a5 Qm (i8)0x00000093 Qn (i8)0x00000012
-vaddl.s32 q0, d2, d4 :: Qd 0xffffffff 0x76767675 0xffffffff 0x76767675 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vaddl.s16 q15, d14, d4 :: Qd 0xffff7675 0xffff7675 0xffff7675 0xffff7675 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vaddl.s8 q0, d2, d31 :: Qd 0xff75ff75 0xff75ff75 0xff75ff75 0xff75ff75 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vaddl.u32 q0, d2, d4 :: Qd 0x00000001 0x76767675 0x00000001 0x76767675 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vaddl.u16 q0, d2, d4 :: Qd 0x00017675 0x00017675 0x00017675 0x00017675 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vaddl.u8 q0, d2, d4 :: Qd 0x01750175 0x01750175 0x01750175 0x01750175 Qm (i8)0x00000093 Qn (i8)0x000000e2
----- VSUBW ----
-vsubw.s32 q0, q1, d4 :: Qd 0x00000072 0xededee61 0x00000072 0xededee61 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubw.s16 q15, q14, d4 :: Qd 0xffffee61 0xffffee61 0xffffee61 0xffffee61 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubw.s8 q0, q1, d31 :: Qd 0xffee0061 0xffee0061 0xffee0061 0xffee0061 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubw.u32 q0, q1, d4 :: Qd 0x00000072 0xededee61 0x00000072 0xededee61 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubw.u16 q0, q1, d4 :: Qd 0xffffee61 0xffffee61 0xffffee61 0xffffee61 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubw.u8 q0, q1, d4 :: Qd 0xffee0061 0xffee0061 0xffee0061 0xffee0061 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubw.s32 q0, q1, d4 :: Qd 0x00000073 0x1d1d1d91 0x00000073 0x1d1d1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubw.s16 q15, q14, d4 :: Qd 0x00001d91 0x00001d91 0x00001d91 0x00001d91 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubw.s8 q0, q1, d31 :: Qd 0x001e0091 0x001e0091 0x001e0091 0x001e0091 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubw.u32 q0, q1, d4 :: Qd 0x00000072 0x1d1d1d91 0x00000072 0x1d1d1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubw.u16 q0, q1, d4 :: Qd 0xffff1d91 0xffff1d91 0xffff1d91 0xffff1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubw.u8 q0, q1, d4 :: Qd 0xff1eff91 0xff1eff91 0xff1eff91 0xff1eff91 Qm (i32)0x00000073 Qn (i8)0x000000e2
----- VSUBL ----
-vsubl.s32 q0, d2, d4 :: Qd 0xffffffff 0xededee61 0xffffffff 0xededee61 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubl.s16 q15, d14, d4 :: Qd 0xffffedee 0xffffee61 0xffffedee 0xffffee61 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubl.s8 q0, d2, d31 :: Qd 0xffeeffee 0xffee0061 0xffeeffee 0xffee0061 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubl.u32 q0, d2, d4 :: Qd 0xffffffff 0xededee61 0xffffffff 0xededee61 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubl.u16 q0, d2, d4 :: Qd 0xffffedee 0xffffee61 0xffffedee 0xffffee61 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubl.u8 q0, d2, d4 :: Qd 0xffeeffee 0xffee0061 0xffeeffee 0xffee0061 Qm (i32)0x00000073 Qn (i8)0x00000012
-vsubl.s32 q0, d2, d4 :: Qd 0x00000000 0x1d1d1d91 0x00000000 0x1d1d1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubl.s16 q15, d14, d4 :: Qd 0x00001d1e 0x00001d91 0x00001d1e 0x00001d91 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubl.s8 q0, d2, d31 :: Qd 0x001e001e 0x001e0091 0x001e001e 0x001e0091 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubl.u32 q0, d2, d4 :: Qd 0xffffffff 0x1d1d1d91 0xffffffff 0x1d1d1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubl.u16 q0, d2, d4 :: Qd 0xffff1d1e 0xffff1d91 0xffff1d1e 0xffff1d91 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubl.u8 q0, d2, d4 :: Qd 0xff1eff1e 0xff1eff91 0xff1eff1e 0xff1eff91 Qm (i32)0x00000073 Qn (i8)0x000000e2
-vsubl.s32 q0, d2, d4 :: Qd 0xffffffff 0x81818181 0xffffffff 0x81818181 Qm (i8)0x00000093 Qn (i8)0x00000012
-vsubl.s16 q15, d14, d4 :: Qd 0xffff8181 0xffff8181 0xffff8181 0xffff8181 Qm (i8)0x00000093 Qn (i8)0x00000012
-vsubl.s8 q0, d2, d31 :: Qd 0xff87ff87 0xff87ff87 0xff87ff87 0xff87ff87 Qm (i8)0x00000099 Qn (i8)0x00000012
-vsubl.u32 q0, d2, d4 :: Qd 0x00000000 0x81818181 0x00000000 0x81818181 Qm (i8)0x00000093 Qn (i8)0x00000012
-vsubl.u16 q0, d2, d4 :: Qd 0x00008181 0x00008181 0x00008181 0x00008181 Qm (i8)0x00000093 Qn (i8)0x00000012
-vsubl.u8 q0, d2, d4 :: Qd 0x00810081 0x00810081 0x00810081 0x00810081 Qm (i8)0x00000093 Qn (i8)0x00000012
-vsubl.s32 q0, d2, d4 :: Qd 0xffffffff 0xb0b0b0b1 0xffffffff 0xb0b0b0b1 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vsubl.s16 q15, d14, d4 :: Qd 0xffffb0b1 0xffffb0b1 0xffffb0b1 0xffffb0b1 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vsubl.s8 q0, d2, d31 :: Qd 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vsubl.u32 q0, d2, d4 :: Qd 0xffffffff 0xb0b0b0b1 0xffffffff 0xb0b0b0b1 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vsubl.u16 q0, d2, d4 :: Qd 0xffffb0b1 0xffffb0b1 0xffffb0b1 0xffffb0b1 Qm (i8)0x00000093 Qn (i8)0x000000e2
-vsubl.u8 q0, d2, d4 :: Qd 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 Qm (i8)0x00000093 Qn (i8)0x000000e2
----- VCEQ #0 ----
-vceq.i32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021
-vceq.i16 q2, q1, #0 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000021
-vceq.i8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x00000021
-vceq.i32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vceq.i16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vceq.i8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
----- VCGT #0 ----
-vcgt.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021
-vcgt.s16 q2, q1, #0 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x00000021
-vcgt.s8 q10, q11, #0 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x00000021
-vcgt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vcgt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vcgt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vcgt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ef
-vcgt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ed
-vcgt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ae
----- VCGE #0 ----
-vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021
-vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021
-vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000021
-vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcge.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ef
-vcge.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ed
-vcge.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ae
-vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x000000ef
-vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x000000ed
-vcge.s8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x000000ae
----- VCLE #0 ----
-vcle.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021
-vcle.s16 q2, q1, #0 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000021
-vcle.s8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x00000021
-vcle.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcle.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcle.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcle.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ef
-vcle.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ed
-vcle.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ae
----- VCLT #0 ----
-vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021
-vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021
-vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000021
-vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vclt.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ef
-vclt.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ed
-vclt.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i8)0x000000ae
-vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x000000ef
-vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x000000ed
-vclt.s8 q10, q11, #0 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x000000ae
----- VCNT ----
-vcnt.8 q0, q1 :: Qd 0x04050306 0x04050306 0x04050306 0x04050306 Qm (i32)0xac3d25eb
-vcnt.8 q11, q14 :: Qd 0x04050306 0x04050306 0x04050306 0x04050306 Qm (i32)0xac3d25eb
-vcnt.8 q6, q2 :: Qd 0x00020306 0x00020306 0x00020306 0x00020306 Qm (i32)0x000ad0eb
----- VCLS ----
-vcls.s8 q0, q1 :: Qd 0x07070701 0x07070701 0x07070701 0x07070701 Qm (i32)0x00000021
-vcls.s8 q10, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082
-vcls.s16 q0, q1 :: Qd 0x000f0009 0x000f0009 0x000f0009 0x000f0009 Qm (i32)0x00000021
-vcls.s16 q15, q10 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082
-vcls.s32 q6, q1 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019 Qm (i32)0x00000021
-vcls.s32 q10, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082
-vcls.s8 q2, q4 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 Qm (i8)0x000000ff
-vcls.s16 q2, q4 :: Qd 0x000f000f 0x000f000f 0x000f000f 0x000f000f Qm (i8)0x000000ff
-vcls.s32 q2, q4 :: Qd 0x0000001f 0x0000001f 0x0000001f 0x0000001f Qm (i8)0x000000ff
-vcls.s8 q2, q4 :: Qd 0x07020702 0x07020702 0x07020702 0x07020702 Qm (i16)0x0000ffef
-vcls.s16 q2, q4 :: Qd 0x000a000a 0x000a000a 0x000a000a 0x000a000a Qm (i16)0x0000ffef
-vcls.s32 q2, q4 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a Qm (i16)0x0000ffef
-vcls.s8 q2, q4 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 Qm (i8)0x00000000
-vcls.s16 q2, q4 :: Qd 0x000f000f 0x000f000f 0x000f000f 0x000f000f Qm (i8)0x00000000
-vcls.s32 q2, q4 :: Qd 0x0000001f 0x0000001f 0x0000001f 0x0000001f Qm (i8)0x00000000
-vcls.s8 q2, q4 :: Qd 0x07020702 0x07020702 0x07020702 0x07020702 Qm (i16)0x000000ef
-vcls.s16 q2, q4 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007 Qm (i16)0x000000ef
-vcls.s32 q2, q4 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i16)0x000000ef
----- VCLZ ----
-vclz.i8 q0, q1 :: Qd 0x08080802 0x08080802 0x08080802 0x08080802 Qm (i32)0x00000021
-vclz.i8 q10, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082
-vclz.i16 q0, q1 :: Qd 0x0010000a 0x0010000a 0x0010000a 0x0010000a Qm (i32)0x00000021
-vclz.i16 q15, q10 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082
-vclz.i32 q6, q1 :: Qd 0x0000001a 0x0000001a 0x0000001a 0x0000001a Qm (i32)0x00000021
-vclz.i32 q10, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x00000082
-vclz.i8 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff
-vclz.i16 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff
-vclz.i32 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i8)0x000000ff
-vclz.i8 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i16)0x0000ffef
-vclz.i16 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i16)0x0000ffef
-vclz.i32 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i16)0x0000ffef
-vclz.i8 q2, q4 :: Qd 0x08080808 0x08080808 0x08080808 0x08080808 Qm (i8)0x00000000
-vclz.i16 q2, q4 :: Qd 0x00100010 0x00100010 0x00100010 0x00100010 Qm (i8)0x00000000
-vclz.i32 q2, q4 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020 Qm (i8)0x00000000
-vclz.i8 q2, q4 :: Qd 0x08000800 0x08000800 0x08000800 0x08000800 Qm (i16)0x000000ef
-vclz.i16 q2, q4 :: Qd 0x00080008 0x00080008 0x00080008 0x00080008 Qm (i16)0x000000ef
-vclz.i32 q2, q4 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i16)0x000000ef
----- VSLI ----
-vsli.16 q0, q1, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff
-vsli.16 q3, q4, #2 :: Qd 0xfffdfe11 0xfffdfe11 0xfffdfe11 0xfffdfe11 Qm (i32)0xffffff84
-vsli.32 q2, q5, #31 :: Qd 0xd5555555 0xd5555555 0xd5555555 0xd5555555 Qm (i32)0xffffffff
-vsli.8 q6, q7, #7 :: Qd 0x5555d5d5 0x5555d5d5 0x5555d5d5 0x5555d5d5 Qm (i32)0x0000ffff
-vsli.16 q8, q9, #12 :: Qd 0xf5556555 0xf5556555 0xf5556555 0xf5556555 Qm (i32)0xfffffff6
-vsli.32 q10, q11, #5 :: Qd 0x0004ff55 0x0004ff55 0x0004ff55 0x0004ff55 Qm (i32)0x000027fa
-vsli.8 q12, q13, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff
-vsli.16 q14, q15, #11 :: Qd 0xfd55fd55 0xfd55fd55 0xfd55fd55 0xfd55fd55 Qm (i32)0xffffffff
-vsli.32 q10, q11, #9 :: Qd 0x0007d155 0x0007d155 0x0007d155 0x0007d155 Qm (i32)0x000003e8
-vsli.8 q7, q13, #7 :: Qd 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 Qm (i32)0xffffffff
-vsli.16 q8, q1, #1 :: Qd 0x0001579f 0x0001579f 0x0001579f 0x0001579f Qm (i32)0x0000abcf
-vsli.32 q12, q3, #15 :: Qd 0xff285555 0xff285555 0xff285555 0xff285555 Qm (i32)0xfffffe50
-vsli.64 q0, q1, #42 :: Qd 0xfffffd55 0x55555555 0xfffffd55 0x55555555 Qm (i32)0xffffffff
-vsli.64 q6, q7, #12 :: Qd 0x00fac000 0x00fac555 0x00fac000 0x00fac555 Qm (i32)0x00000fac
-vsli.64 q8, q4, #9 :: Qd 0x0069f000 0x0069f155 0x0069f000 0x0069f155 Qm (i32)0x000034f8
-vsli.64 q9, q12, #11 :: Qd 0x0c0cb000 0x0c0cb555 0x0c0cb000 0x0c0cb555 Qm (i32)0x00018196
----- VPADDL ----
-vpaddl.u32 q0, q1 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018
-vpaddl.u32 q0, q1 :: Qd 0x00000000 0x00000118 0x00000000 0x00000118 Qm (i32)0x0000008c
-vpaddl.u16 q0, q1 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c
-vpaddl.u8 q0, q1 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c
-vpaddl.u8 q0, q1 :: Qd 0x00800001 0x00800001 0x00800001 0x00800001 Qm (i32)0x80000001
-vpaddl.u16 q0, q1 :: Qd 0x00008001 0x00008001 0x00008001 0x00008001 Qm (i32)0x80000001
-vpaddl.u32 q0, q1 :: Qd 0x00000001 0x00000002 0x00000001 0x00000002 Qm (i32)0x80000001
-vpaddl.u32 q10, q11 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018
-vpaddl.s32 q0, q1 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018
-vpaddl.s32 q0, q1 :: Qd 0x00000000 0x00000118 0x00000000 0x00000118 Qm (i32)0x0000008c
-vpaddl.s16 q0, q1 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c Qm (i32)0x0000008c
-vpaddl.s8 q0, q1 :: Qd 0x0000ff8c 0x0000ff8c 0x0000ff8c 0x0000ff8c Qm (i32)0x0000008c
-vpaddl.s8 q0, q1 :: Qd 0xff800001 0xff800001 0xff800001 0xff800001 Qm (i32)0x80000001
-vpaddl.s16 q0, q1 :: Qd 0xffff8001 0xffff8001 0xffff8001 0xffff8001 Qm (i32)0x80000001
-vpaddl.s32 q0, q1 :: Qd 0xffffffff 0x00000002 0xffffffff 0x00000002 Qm (i32)0x80000001
-vpaddl.s32 q10, q11 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018
----- VPADAL ----
-vpadal.u32 q0, q1 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585 Qm (i32)0x00000018
-vpadal.u32 q0, q1 :: Qd 0x55555555 0x5555566d 0x55555555 0x5555566d Qm (i32)0x0000008c
-vpadal.u16 q0, q1 :: Qd 0x555555e1 0x555555e1 0x555555e1 0x555555e1 Qm (i32)0x0000008c
-vpadal.u8 q0, q1 :: Qd 0x566d566d 0x566d566d 0x566d566d 0x566d566d Qm (i8)0x0000008c
-vpadal.u8 q0, q1 :: Qd 0x55d55556 0x55d55556 0x55d55556 0x55d55556 Qm (i32)0x80000001
-vpadal.u16 q0, q1 :: Qd 0x5555d556 0x5555d556 0x5555d556 0x5555d556 Qm (i32)0x80000001
-vpadal.u32 q0, q1 :: Qd 0x55555556 0x55555557 0x55555556 0x55555557 Qm (i32)0x80000001
-vpadal.u32 q10, q11 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585 Qm (i32)0x00000018
-vpadal.s32 q0, q1 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585 Qm (i32)0x00000018
-vpadal.s32 q0, q1 :: Qd 0x55555555 0x5555566d 0x55555555 0x5555566d Qm (i32)0x0000008c
-vpadal.s16 q0, q1 :: Qd 0x555555e1 0x555555e1 0x555555e1 0x555555e1 Qm (i32)0x0000008c
-vpadal.s8 q0, q1 :: Qd 0x546d546d 0x546d546d 0x546d546d 0x546d546d Qm (i8)0x0000008c
-vpadal.s8 q0, q1 :: Qd 0x54d55556 0x54d55556 0x54d55556 0x54d55556 Qm (i32)0x80000001
-vpadal.s16 q0, q1 :: Qd 0x5554d556 0x5554d556 0x5554d556 0x5554d556 Qm (i32)0x80000001
-vpadal.s32 q0, q1 :: Qd 0x55555554 0x55555557 0x55555554 0x55555557 Qm (i32)0x80000001
-vpadal.s32 q10, q11 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585 Qm (i32)0x00000018
----- VZIP ----
-vzip.32 q0, q1 :: Qm 0x34343434 0x12121212 0x34343434 0x12121212 Qn 0x34343434 0x12121212 0x34343434 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034
-vzip.16 q1, q0 :: Qm 0x12123434 0x12123434 0x12123434 0x12123434 Qn 0x12123434 0x12123434 0x12123434 0x12123434 Qm (i8)0x00000012 Qn (i8)0x00000034
-vzip.8 q10, q11 :: Qm 0x34123412 0x34123412 0x34123412 0x34123412 Qn 0x34123412 0x34123412 0x34123412 0x34123412 Qm (i8)0x00000012 Qn (i8)0x00000034
-vzip.32 q0, q1 :: Qm 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678 Qn 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
-vzip.16 q1, q0 :: Qm 0x12340a0b 0x56780c0d 0x12340a0b 0x56780c0d Qn 0x12340a0b 0x56780c0d 0x12340a0b 0x56780c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
-vzip.8 q10, q11 :: Qm 0x0a120b34 0x0c560d78 0x0a120b34 0x0c560d78 Qn 0x0a120b34 0x0c560d78 0x0a120b34 0x0c560d78 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
----- VUZP ----
-vuzp.32 q0, q1 :: Qm 0x34343434 0x34343434 0x12121212 0x12121212 Qn 0x34343434 0x34343434 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034
-vuzp.16 q1, q0 :: Qm 0x12121212 0x12121212 0x34343434 0x34343434 Qn 0x12121212 0x12121212 0x34343434 0x34343434 Qm (i8)0x00000012 Qn (i8)0x00000034
-vuzp.8 q10, q11 :: Qm 0x34343434 0x34343434 0x12121212 0x12121212 Qn 0x34343434 0x34343434 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034
-vuzp.32 q0, q1 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x12345678 0x12345678 Qn 0x0a0b0c0d 0x0a0b0c0d 0x12345678 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
-vuzp.16 q1, q0 :: Qm 0x12341234 0x12341234 0x0a0b0a0b 0x0a0b0a0b Qn 0x56785678 0x56785678 0x0c0d0c0d 0x0c0d0c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
-vuzp.8 q10, q11 :: Qm 0x0b0d0b0d 0x0b0d0b0d 0x34783478 0x34783478 Qn 0x0a0c0a0c 0x0a0c0a0c 0x12561256 0x12561256 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
----- VTRN ----
-vtrn.32 q0, q1 :: Qm 0x34343434 0x12121212 0x34343434 0x12121212 Qn 0x34343434 0x12121212 0x34343434 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034
-vtrn.16 q1, q0 :: Qm 0x12123434 0x12123434 0x12123434 0x12123434 Qn 0x12123434 0x12123434 0x12123434 0x12123434 Qm (i8)0x00000012 Qn (i8)0x00000034
-vtrn.8 q10, q11 :: Qm 0x34123412 0x34123412 0x34123412 0x34123412 Qn 0x34123412 0x34123412 0x34123412 0x34123412 Qm (i8)0x00000012 Qn (i8)0x00000034
-vtrn.32 q0, q1 :: Qm 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678 Qn 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
-vtrn.16 q1, q0 :: Qm 0x12340a0b 0x12340a0b 0x12340a0b 0x12340a0b Qn 0x56780c0d 0x56780c0d 0x56780c0d 0x56780c0d Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
-vtrn.8 q10, q11 :: Qm 0x0b340d78 0x0b340d78 0x0b340d78 0x0b340d78 Qn 0x0a120c56 0x0a120c56 0x0a120c56 0x0a120c56 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
----- VSWP ----
-vswp q0, q1 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434 Qn 0x12121212 0x12121212 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034
-vswp q1, q0 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434 Qn 0x12121212 0x12121212 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034
-vswp q10, q11 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434 Qn 0x12121212 0x12121212 0x12121212 0x12121212 Qm (i8)0x00000012 Qn (i8)0x00000034
-vswp q0, q1 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d Qn 0x12345678 0x12345678 0x12345678 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
-vswp q1, q0 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d Qn 0x12345678 0x12345678 0x12345678 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
-vswp q10, q11 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d Qn 0x12345678 0x12345678 0x12345678 0x12345678 Qm (i32)0x12345678 Qn (i32)0x0a0b0c0d
----- VDUP ----
-vdup.8 q2, d2[0] :: Qd 0x57575757 0x57575757 0x57575757 0x57575757 Qm (i32)0x0abc4657
-vdup.8 q3, d3[2] :: Qd 0x07070707 0x07070707 0x07070707 0x07070707 Qm (i32)0x0007a1b3
-vdup.8 q1, d0[7] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00713aaa
-vdup.8 q0, d4[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x000aa713
-vdup.8 q4, d28[4] :: Qd 0xc3c3c3c3 0xc3c3c3c3 0xc3c3c3c3 0xc3c3c3c3 Qm (i32)0x0007b1c3
-vdup.16 q7, d19[3] :: Qd 0x07130713 0x07130713 0x07130713 0x07130713 Qm (i32)0x0713ffff
-vdup.16 q15, d31[0] :: Qd 0x00fa00fa 0x00fa00fa 0x00fa00fa 0x00fa00fa Qm (i32)0x007f00fa
-vdup.16 q6, d2[0] :: Qd 0xbcdebcde 0xbcdebcde 0xbcdebcde 0xbcdebcde Qm (i32)0x0ffabcde
-vdup.16 q8, d22[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000713
-vdup.16 q9, d2[0] :: Qd 0x07130713 0x07130713 0x07130713 0x07130713 Qm (i32)0x00000713
-vdup.32 q10, d17[1] :: Qd 0x00000713 0x00000713 0x00000713 0x00000713 Qm (i32)0x00000713
-vdup.32 q15, d11[0] :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x00000003
-vdup.32 q10, d29[1] :: Qd 0xf00000aa 0xf00000aa 0xf00000aa 0xf00000aa Qm (i32)0xf00000aa
-vdup.32 q12, d0[1] :: Qd 0x0000000f 0x0000000f 0x0000000f 0x0000000f Qm (i32)0x0000000f
-vdup.32 q13, d13[0] :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xffffffff
----- VQDMULL ----
-vqdmull.s32 q0, d1, d2 :: Qd 0x00000000 0x00001680 0x00000000 0x00001680 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmull.s32 q6, d7, d8 :: Qd 0xffffffff 0xffff7cc0 0xffffffff 0xffff7cc0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqdmull.s16 q9, d11, d12 :: Qd 0x00000000 0x0002d000 0x00000000 0x0002d000 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x10014004 0x00000000 0x10014004 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqdmull.s32 q7, d8, d9 :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0xe50b10cc 0x00000000 0xe50b10cc Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000
-vqdmull.s32 q7, d8, d9 :: Qd 0xfffffff4 0x00000000 0xfffffff4 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x003f83f8 0x00000000 0x003f83f8 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqdmull.s32 q7, d8, d9 :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmull.s32 q10, d11, d15 :: Qd 0x00000000 0x00001680 0x00000000 0x00001680 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmull.s32 q10, d30, d31 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmull.s16 q10, d30, d31 :: Qd 0x7fffffff 0x00000000 0x7fffffff 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmull.s32 q10, d30, d31 :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000
-vqdmull.s16 q10, d30, d31 :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000
----- VQDMULL (by scalar) ----
-vqdmull.s32 q0, d1, d7[0] :: Qd 0x00000000 0x00001680 0x00000000 0x00001680 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmull.s32 q6, d7, d6[0] :: Qd 0xffffffff 0xffff7cc0 0xffffffff 0xffff7cc0 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqdmull.s16 q9, d11, d7[2] :: Qd 0x00000000 0x0002d000 0x00000000 0x0002d000 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqdmull.s16 q4, d5, d6[2] :: Qd 0x00000000 0x10014004 0x00000000 0x10014004 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqdmull.s32 q7, d8, d3[1] :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmull.s16 q4, d5, d6[1] :: Qd 0xffffbffc 0xe50b10cc 0xffffbffc 0xe50b10cc Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000
-vqdmull.s32 q7, d8, d3[0] :: Qd 0xfffffff4 0x00000000 0xfffffff4 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqdmull.s16 q4, d5, d6[2] :: Qd 0x04004000 0x003f83f8 0x04004000 0x003f83f8 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqdmull.s32 q7, d8, d3[1] :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmull.s32 q10, d11, d15[1] :: Qd 0x00000000 0x00001680 0x00000000 0x00001680 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmull.s32 q10, d30, d1[0] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmull.s16 q10, d30, d1[1] :: Qd 0x7fffffff 0x00000000 0x7fffffff 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmull.s32 q10, d30, d1[1] :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000
-vqdmull.s16 q10, d30, d1[3] :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000
----- VQDMLSL ----
-vqdmlsl.s32 q0, d1, d2 :: Qd 0x00000017 0xffffe998 0x55555555 0x55553ed5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmlsl.s32 q6, d7, d8 :: Qd 0x55555555 0x5555d895 0x55555555 0x5555d895 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqdmlsl.s16 q9, d11, d12 :: Qd 0x55555555 0x55528555 0x55555555 0x55528555 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x45541551 0x55555555 0x45541551 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqdmlsl.s32 q7, d8, d9 :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x704a4489 0x55555555 0x704a4489 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000
-vqdmlsl.s32 q7, d8, d9 :: Qd 0x55555561 0x55555555 0x55555561 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x5515d15d 0x55555555 0x5515d15d Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqdmlsl.s32 q7, d8, d9 :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmlsl.s32 q10, d11, d15 :: Qd 0x55555555 0x55553ed5 0x55555555 0x55553ed5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmlsl.s32 q10, d30, d31 :: Qd 0xd5555555 0x55555556 0xd5555555 0x55555556 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlsl.s16 q10, d30, d31 :: Qd 0xd5555556 0x55555555 0xd5555556 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlsl.s32 q10, d30, d31 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlsl.s16 q10, d30, d31 :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 08000000
----- VQDMLSL (by scalar) ----
-vqdmlsl.s32 q0, d1, d7[0] :: Qd 0x00000017 0xffffe998 0x55555555 0x55553ed5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmlsl.s32 q6, d7, d6[0] :: Qd 0x55555555 0x5555d895 0x55555555 0x5555d895 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqdmlsl.s16 q9, d11, d7[2] :: Qd 0x55555555 0x55528555 0x55555555 0x55528555 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x55555555 0x45541551 0x55555555 0x45541551 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqdmlsl.s32 q7, d8, d3[1] :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmlsl.s16 q4, d5, d6[1] :: Qd 0x55559559 0x704a4489 0x55559559 0x704a4489 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000
-vqdmlsl.s32 q7, d8, d3[0] :: Qd 0x55555561 0x55555555 0x55555561 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x51551555 0x5515d15d 0x51551555 0x5515d15d Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqdmlsl.s32 q7, d8, d3[1] :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551 Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmlsl.s32 q10, d11, d15[1] :: Qd 0x55555555 0x55553ed5 0x55555555 0x55553ed5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmlsl.s32 q10, d30, d1[0] :: Qd 0xd5555555 0x55555556 0xd5555555 0x55555556 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlsl.s16 q10, d30, d1[1] :: Qd 0xd5555556 0x55555555 0xd5555556 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlsl.s32 q10, d30, d1[1] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlsl.s16 q10, d30, d1[3] :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 08000000
----- VQDMLAL ----
-vqdmlal.s32 q0, d1, d2 :: Qd 0x00000018 0x00001698 0x55555555 0x55556bd5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmlal.s32 q6, d7, d8 :: Qd 0x55555555 0x5554d215 0x55555555 0x5554d215 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqdmlal.s16 q9, d11, d12 :: Qd 0x55555555 0x55582555 0x55555555 0x55582555 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x65569559 0x55555555 0x65569559 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqdmlal.s32 q7, d8, d9 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x3a606621 0x55555555 0x3a606621 Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000
-vqdmlal.s32 q7, d8, d9 :: Qd 0x55555549 0x55555555 0x55555549 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5594d94d 0x55555555 0x5594d94d Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqdmlal.s32 q7, d8, d9 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqdmlal.s32 q10, d11, d15 :: Qd 0x55555555 0x55556bd5 0x55555555 0x55556bd5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmlal.s32 q10, d30, d31 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlal.s16 q10, d30, d31 :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlal.s32 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000
-vqdmlal.s16 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000
----- VQDMLAL (by scalar) ----
-vqdmlal.s32 q0, d1, d7[0] :: Qd 0x00000018 0x00001698 0x55555555 0x55556bd5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmlal.s32 q6, d7, d6[0] :: Qd 0x55555555 0x5554d215 0x55555555 0x5554d215 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqdmlal.s16 q9, d11, d7[2] :: Qd 0x55555555 0x55582555 0x55555555 0x55582555 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqdmlal.s16 q4, d5, d6[2] :: Qd 0x55555555 0x65569559 0x55555555 0x65569559 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqdmlal.s32 q7, d8, d3[1] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqdmlal.s16 q4, d5, d6[1] :: Qd 0x55551551 0x3a606621 0x55551551 0x3a606621 Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000
-vqdmlal.s32 q7, d8, d3[0] :: Qd 0x55555549 0x55555555 0x55555549 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqdmlal.s16 q4, d5, d6[2] :: Qd 0x59559555 0x5594d94d 0x59559555 0x5594d94d Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqdmlal.s32 q7, d8, d3[1] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 08000000
-vqdmlal.s32 q10, d11, d15[1] :: Qd 0x55555555 0x55556bd5 0x55555555 0x55556bd5 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmlal.s32 q10, d30, d1[0] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlal.s16 q10, d30, d1[1] :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmlal.s32 q10, d30, d1[1] :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000
-vqdmlal.s16 q10, d30, d1[3] :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000
----- VQDMULH ----
-vqdmulh.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmulh.s32 q6, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqdmulh.s16 q9, q11, q12 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqdmulh.s16 q4, q5, q6 :: Qd 0x00001001 0x00001001 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmulh.s16 q4, q5, q6 :: Qd 0x0000e50b 0x0000e50b 0x0000e50b 0x0000e50b Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000
-vqdmulh.s32 q7, q8, q9 :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqdmulh.s16 q4, q5, q6 :: Qd 0x0000003f 0x0000003f 0x0000003f 0x0000003f Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmulh.s32 q10, q11, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmulh.s32 q10, q14, q15 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmulh.s16 q10, q14, q15 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmulh.s32 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000
-vqdmulh.s16 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000
----- VQDMULH (by scalar) ----
-vqdmulh.s32 q0, q1, d6[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmulh.s32 q6, q7, d1[1] :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqdmulh.s16 q9, q11, d7[0] :: Qd 0x00000002 0x00000002 0x00000002 0x00000002 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqdmulh.s16 q4, q5, d6[0] :: Qd 0x00001001 0x00001001 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqdmulh.s32 q7, q8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmulh.s16 q4, q5, d6[1] :: Qd 0xffffe50b 0xffffe50b 0xffffe50b 0xffffe50b Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000
-vqdmulh.s32 q7, q8, d9[0] :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqdmulh.s16 q4, q5, d6[2] :: Qd 0x0400003f 0x0400003f 0x0400003f 0x0400003f Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqdmulh.s32 q7, q8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqdmulh.s32 q10, q11, d15[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqdmulh.s32 q10, q14, d15[1] :: Qd 0xffffff88 0xffffff88 0xffffff88 0xffffff88 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000
-vqdmulh.s16 q10, q14, d7[3] :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqdmulh.s32 q10, q14, d15[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000
-vqdmulh.s16 q10, q14, d7[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000
----- VSHL (immediate) ----
-vshl.i64 q0, q1, #1 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i32)0x00000018
-vshl.i64 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x40000000
-vshl.i64 q9, q12, #2 :: Qd 0x0000000a 0x00000008 0x0000000a 0x00000008 Qm (i32)0x80000002
-vshl.i64 q11, q2, #12 :: Qd 0xffffffff 0xfffff000 0xffffffff 0xfffff000 Qm (i32)0xffffffff
-vshl.i64 q15, q12, #63 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000 Qm (i32)0x00000005
-vshl.i64 q5, q12, #62 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000001
-vshl.i32 q0, q1, #1 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i32)0x00000018
-vshl.i32 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x40000000
-vshl.i32 q9, q12, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002
-vshl.i32 q11, q2, #12 :: Qd 0xfffff000 0xfffff000 0xfffff000 0xfffff000 Qm (i32)0xffffffff
-vshl.i32 q15, q12, #20 :: Qd 0x00500000 0x00500000 0x00500000 0x00500000 Qm (i32)0x00000005
-vshl.i32 q5, q12, #30 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x80000001
-vshl.i16 q0, q1, #1 :: Qd 0x00300030 0x00300030 0x00300030 0x00300030 Qm (i16)0x00000018
-vshl.i16 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x40000000
-vshl.i16 q9, q12, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002
-vshl.i16 q11, q2, #12 :: Qd 0xf000f000 0xf000f000 0xf000f000 0xf000f000 Qm (i16)0xffffffff
-vshl.i16 q15, q12, #3 :: Qd 0x00280028 0x00280028 0x00280028 0x00280028 Qm (i16)0x00000005
-vshl.i16 q5, q12, #14 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000 Qm (i32)0x80000001
-vshl.i8 q0, q1, #1 :: Qd 0x30303030 0x30303030 0x30303030 0x30303030 Qm (i8)0x00000018
-vshl.i8 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x40000000
-vshl.i8 q9, q12, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008 Qm (i32)0x80000002
-vshl.i8 q11, q2, #7 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080 Qm (i8)0xffffffff
-vshl.i8 q15, q12, #3 :: Qd 0x28282828 0x28282828 0x28282828 0x28282828 Qm (i8)0x00000005
-vshl.i8 q5, q12, #6 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x80000001
----- VNEG ----
-vneg.s32 q0, q1 :: Qd 0xffffff8d 0xffffff8d 0xffffff8d 0xffffff8d Qm (i32)0x00000073
-vneg.s16 q15, q4 :: Qd 0x0000ff8d 0x0000ff8d 0x0000ff8d 0x0000ff8d Qm (i32)0x00000073
-vneg.s8 q8, q7 :: Qd 0x0000008d 0x0000008d 0x0000008d 0x0000008d Qm (i32)0x00000073
-vneg.s32 q0, q1 :: Qd 0xffffff02 0xffffff02 0xffffff02 0xffffff02 Qm (i32)0x000000fe
-vneg.s16 q15, q4 :: Qd 0x0000ff11 0x0000ff11 0x0000ff11 0x0000ff11 Qm (i32)0x000000ef
-vneg.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022 Qm (i32)0x000000de
-vneg.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a
-vneg.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b
-vneg.s8 q8, q7 :: Qd 0x22f422f4 0x22f422f4 0x22f422f4 0x22f422f4 Qm (i16)0x0000de0c
----- VQNEG ----
-vqneg.s32 q0, q1 :: Qd 0xffffff8d 0xffffff8d 0xffffff8d 0xffffff8d Qm (i32)0x00000073 fpscr: 00000000
-vqneg.s32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 fpscr: 08000000
-vqneg.s16 q0, q1 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 fpscr: 08000000
-vqneg.s8 q0, q1 :: Qd 0x7f000000 0x7f000000 0x7f000000 0x7f000000 Qm (i32)0x80000000 fpscr: 08000000
-vqneg.s16 q15, q4 :: Qd 0x0000ff8d 0x0000ff8d 0x0000ff8d 0x0000ff8d Qm (i32)0x00000073 fpscr: 00000000
-vqneg.s8 q8, q7 :: Qd 0x0000008d 0x0000008d 0x0000008d 0x0000008d Qm (i32)0x00000073 fpscr: 00000000
-vqneg.s32 q0, q1 :: Qd 0xffffff02 0xffffff02 0xffffff02 0xffffff02 Qm (i32)0x000000fe fpscr: 00000000
-vqneg.s16 q15, q4 :: Qd 0x0000ff11 0x0000ff11 0x0000ff11 0x0000ff11 Qm (i32)0x000000ef fpscr: 00000000
-vqneg.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022 Qm (i32)0x000000de fpscr: 00000000
-vqneg.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6 Qm (i16)0x0000fe0a fpscr: 00000000
-vqneg.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5 Qm (i16)0x0000ef0b fpscr: 00000000
-vqneg.s8 q8, q7 :: Qd 0x22f422f4 0x22f422f4 0x22f422f4 0x22f422f4 Qm (i16)0x0000de0c fpscr: 00000000
----- VREV ----
-vrev64.8 q0, q1 :: Qd 0xddccbbaa 0xddccbbaa 0xddccbbaa 0xddccbbaa Qm (i32)0xaabbccdd
-vrev64.16 q10, q15 :: Qd 0xccddaabb 0xccddaabb 0xccddaabb 0xccddaabb Qm (i32)0xaabbccdd
-vrev64.32 q1, q14 :: Qd 0xaabbccdd 0xaabbccdd 0xaabbccdd 0xaabbccdd Qm (i32)0xaabbccdd
-vrev32.8 q0, q1 :: Qd 0xddccbbaa 0xddccbbaa 0xddccbbaa 0xddccbbaa Qm (i32)0xaabbccdd
-vrev32.16 q10, q15 :: Qd 0xccddaabb 0xccddaabb 0xccddaabb 0xccddaabb Qm (i32)0xaabbccdd
-vrev16.8 q0, q1 :: Qd 0xbbaaddcc 0xbbaaddcc 0xbbaaddcc 0xbbaaddcc Qm (i32)0xaabbccdd
----- VSHLL ----
-vshll.s32 q0, d1, #1 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030 Qm (i32)0x00000018
-vshll.s32 q5, d2, #1 :: Qd 0x00000000 0x80000000 0x00000000 0x80000000 Qm (i32)0x40000000
-vshll.s32 q9, d12, #2 :: Qd 0xfffffffe 0x00000008 0xfffffffe 0x00000008 Qm (i32)0x80000002
-vshll.u32 q11, d2, #12 :: Qd 0x00000fff 0xfffff000 0x00000fff 0xfffff000 Qm (i32)0xffffffff
-vshll.u32 q15, d12, #20 :: Qd 0x00000000 0x00500000 0x00000000 0x00500000 Qm (i32)0x00000005
-vshll.u32 q5, d22, #30 :: Qd 0x20000000 0x40000000 0x20000000 0x40000000 Qm (i32)0x80000001
-vshll.s16 q0, d1, #1 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030 Qm (i16)0x00000018
-vshll.s16 q5, d2, #1 :: Qd 0x00008000 0x00000000 0x00008000 0x00000000 Qm (i32)0x40000000
-vshll.s16 q9, d12, #2 :: Qd 0xfffe0000 0x00000008 0xfffe0000 0x00000008 Qm (i32)0x80000002
-vshll.u16 q11, d2, #12 :: Qd 0x0ffff000 0x0ffff000 0x0ffff000 0x0ffff000 Qm (i16)0xffffffff
-vshll.u16 q15, d22, #3 :: Qd 0x00000028 0x00000028 0x00000028 0x00000028 Qm (i16)0x00000005
-vshll.u16 q5, d12, #14 :: Qd 0x20000000 0x00004000 0x20000000 0x00004000 Qm (i32)0x80000001
-vshll.s8 q0, d1, #1 :: Qd 0x00300030 0x00300030 0x00300030 0x00300030 Qm (i8)0x00000018
-vshll.s8 q5, d2, #1 :: Qd 0x00800000 0x00000000 0x00800000 0x00000000 Qm (i32)0x40000000
-vshll.s8 q9, d12, #2 :: Qd 0xfe000000 0x00000008 0xfe000000 0x00000008 Qm (i32)0x80000002
-vshll.u8 q11, d2, #7 :: Qd 0x7f807f80 0x7f807f80 0x7f807f80 0x7f807f80 Qm (i8)0xffffffff
-vshll.u8 q15, d19, #3 :: Qd 0x00280028 0x00280028 0x00280028 0x00280028 Qm (i8)0x00000005
-vshll.u8 q5, d12, #6 :: Qd 0x20000000 0x00000040 0x20000000 0x00000040 Qm (i32)0x80000001
----- VSHLL (max shift) ----
-vshll.i32 q0, d1, #32 :: Qd 0x00000018 0x00000000 0x00000018 0x00000000 Qm (i32)0x00000018
-vshll.i32 q5, d2, #32 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x40000000
-vshll.i32 q11, d2, #32 :: Qd 0xffffffff 0x00000000 0xffffffff 0x00000000 Qm (i32)0xffffffff
-vshll.i32 q15, d12, #32 :: Qd 0x00000005 0x00000000 0x00000005 0x00000000 Qm (i32)0x00000005
-vshll.i16 q0, d1, #16 :: Qd 0x00180000 0x00180000 0x00180000 0x00180000 Qm (i16)0x00000018
-vshll.i16 q5, d2, #16 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x40000000
-vshll.i16 q11, d2, #16 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i16)0xffffffff
-vshll.i16 q15, d22, #16 :: Qd 0x00050000 0x00050000 0x00050000 0x00050000 Qm (i16)0x00000005
-vshll.i8 q0, d1, #8 :: Qd 0x18001800 0x18001800 0x18001800 0x18001800 Qm (i8)0x00000018
-vshll.i8 q5, d2, #8 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x40000000
-vshll.i8 q11, d2, #8 :: Qd 0xff00ff00 0xff00ff00 0xff00ff00 0xff00ff00 Qm (i8)0xffffffff
-vshll.i8 q15, d19, #8 :: Qd 0x05000500 0x05000500 0x05000500 0x05000500 Qm (i8)0x00000005
----- VMULL ----
-vmull.s8 q0, d1, d12 :: Qd 0x0000fe0c 0x01980d94 0x0000fe0c 0x01980d94 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmull.s8 q9, d11, d12 :: Qd 0x00000000 0x00010800 0x00000000 0x00010800 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmull.s8 q4, d5, d6 :: Qd 0x00000000 0x08000002 0x00000000 0x08000002 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmull.s8 q4, d5, d6 :: Qd 0x00000000 0xee48ed46 0x00000000 0xee48ed46 Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmull.s8 q4, d5, d6 :: Qd 0x00000000 0x0000ffa6 0x00000000 0x0000ffa6 Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmull.s8 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmull.s8 q10, d30, d31 :: Qd 0xe0000000 0x00000000 0xe0000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmull.u8 q0, d1, d12 :: Qd 0x0000080c 0xb7989294 0x0000080c 0xb7989294 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmull.u8 q9, d11, d12 :: Qd 0x00000000 0x00010800 0x00000000 0x00010800 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmull.u8 q4, d5, d6 :: Qd 0x00000000 0x08000002 0x00000000 0x08000002 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmull.u8 q4, d5, d6 :: Qd 0x00000000 0x18482046 0x00000000 0x18482046 Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmull.u8 q4, d5, d6 :: Qd 0x00000000 0x00002ca6 0x00000000 0x00002ca6 Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmull.u8 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmull.u8 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmull.s16 q0, d1, d12 :: Qd 0x0000080c 0x01649694 0x0000080c 0x01649694 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmull.s16 q9, d11, d12 :: Qd 0x00000000 0x00016800 0x00000000 0x00016800 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmull.s16 q4, d5, d6 :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmull.s16 q4, d5, d6 :: Qd 0x00000000 0xee0c2646 0x00000000 0xee0c2646 Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmull.s16 q4, d5, d6 :: Qd 0x0002b000 0xffdc74a6 0x0002b000 0xffdc74a6 Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmull.s16 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmull.s16 q10, d30, d31 :: Qd 0xe0000000 0x00000000 0xe0000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmull.u16 q0, d1, d12 :: Qd 0x0000080c 0xb8e99694 0x0000080c 0xb8e99694 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmull.u16 q9, d11, d12 :: Qd 0x00000000 0x00016800 0x00000000 0x00016800 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmull.u16 q4, d5, d6 :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmull.u16 q4, d5, d6 :: Qd 0x00000000 0x18ae2646 0x00000000 0x18ae2646 Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmull.u16 q4, d5, d6 :: Qd 0x0002b000 0x00da74a6 0x0002b000 0x00da74a6 Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmull.u16 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmull.u16 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmull.s32 q0, d1, d2 :: Qd 0x000121f2 0xd7d30fa8 0x000121f2 0xd7d30fa8 Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a
-vmull.s32 q6, d7, d8 :: Qd 0xffffffff 0xffffbe60 0xffffffff 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmull.s32 q7, d8, d9 :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmull.s32 q7, d8, d9 :: Qd 0xfffffffa 0x00000000 0xfffffffa 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c
-vmull.s32 q7, d8, d9 :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmull.s32 q10, d11, d15 :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmull.s32 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmull.s32 q10, d30, d31 :: Qd 0xe0000000 0x00000000 0xe0000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000
-vmull.u32 q0, d1, d2 :: Qd 0x000121f2 0xd7d30fa8 0x000121f2 0xd7d30fa8 Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a
-vmull.u32 q6, d7, d8 :: Qd 0x0000008b 0xffffbe60 0x0000008b 0xffffbe60 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmull.u32 q7, d8, d9 :: Qd 0x40000001 0x80000002 0x40000001 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmull.u32 q7, d8, d9 :: Qd 0x00000006 0x00000000 0x00000006 0x00000000 Qm (i32)0x80000000 Qn (i32)0x0000000c
-vmull.u32 q7, d8, d9 :: Qd 0x40000001 0x80000002 0x40000001 0x80000002 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmull.u32 q10, d11, d15 :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmull.u32 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmull.u32 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x40000000 Qn (i32)0x80000000
-vmull.p8 q9, d11, d12 :: Qd 0x00000a3a 0x3eb60440 0x00000a3a 0x3eb60440 Qm (i32)0x001a4b0c Qn (i32)0x00d1e2f0
-vmull.p8 q4, d5, d6 :: Qd 0x00000000 0x08000002 0x00000000 0x08000002 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmull.p8 q4, d15, d26 :: Qd 0x00000000 0x17081f86 0x00000000 0x17081f86 Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmull.p8 q14, d5, d6 :: Qd 0x00000000 0x04281b36 0x00000000 0x04281b36 Qm (i32)0x10000efe Qn (i32)0x002bdc2d
-vmull.p8 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmull.p8 q10, d27, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmull.p8 q9, d11, d12 :: Qd 0x00000000 0x00010800 0x00000000 0x00010800 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmull.p8 q4, d5, d6 :: Qd 0x00000000 0x00001b36 0x00000000 0x00001b36 Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmull.p8 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000 Qm (i32)0x80000000 Qn (i32)0x40000000
----- VMLAL ----
-vmlal.s8 q0, d1, d12 :: Qd 0x000abae0 0x01a2ca68 0x55555361 0x56ed62e9 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmlal.s8 q9, d11, d12 :: Qd 0x55555555 0x55565d55 0x55555555 0x55565d55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlal.s8 q4, d5, d6 :: Qd 0x55555555 0x5d555557 0x55555555 0x5d555557 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlal.s8 q4, d5, d6 :: Qd 0x55555555 0x439d429b 0x55555555 0x439d429b Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmlal.s8 q4, d5, d6 :: Qd 0x55555555 0x555554fb 0x55555555 0x555554fb Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmlal.s8 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlal.s8 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmlal.u8 q0, d1, d12 :: Qd 0x000ac4e0 0xb7a24f68 0x55555d61 0x0cede7e9 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmlal.u8 q9, d11, d12 :: Qd 0x55555555 0x55565d55 0x55555555 0x55565d55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlal.u8 q4, d5, d6 :: Qd 0x55555555 0x5d555557 0x55555555 0x5d555557 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlal.u8 q4, d5, d6 :: Qd 0x55555555 0x6d9d759b 0x55555555 0x6d9d759b Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmlal.u8 q4, d5, d6 :: Qd 0x55555555 0x555581fb 0x55555555 0x555581fb Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmlal.u8 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlal.u8 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmlal.s16 q0, d1, d12 :: Qd 0x000ac4e0 0x016f5368 0x55555d61 0x56b9ebe9 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmlal.s16 q9, d11, d12 :: Qd 0x55555555 0x5556bd55 0x55555555 0x5556bd55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x43617b9b 0x55555555 0x43617b9b Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmlal.s16 q4, d5, d6 :: Qd 0x55580555 0x5531c9fb 0x55580555 0x5531c9fb Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmlal.s16 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlal.s16 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmlal.u16 q0, d1, d12 :: Qd 0x000ac4e0 0xb8f45368 0x55555d61 0x0e3eebe9 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmlal.u16 q9, d11, d12 :: Qd 0x55555555 0x5556bd55 0x55555555 0x5556bd55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlal.u16 q4, d5, d6 :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlal.u16 q4, d5, d6 :: Qd 0x55555555 0x6e037b9b 0x55555555 0x6e037b9b Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmlal.u16 q4, d5, d6 :: Qd 0x55580555 0x562fc9fb 0x55580555 0x562fc9fb Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmlal.u16 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlal.u16 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmlal.s32 q0, d1, d2 :: Qd 0x0aacdeb6 0xe27ecc6c 0x55567748 0x2d2864fd Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a
-vmlal.s32 q6, d7, d8 :: Qd 0x55555555 0x555513b5 0x55555555 0x555513b5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmlal.s32 q7, d8, d9 :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlal.s32 q7, d8, d9 :: Qd 0x5555554f 0x55555555 0x5555554f 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c
-vmlal.s32 q7, d8, d9 :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlal.s32 q10, d11, d15 :: Qd 0x55555555 0x55556095 0x55555555 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmlal.s32 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlal.s32 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000
-vmlal.u32 q0, d1, d2 :: Qd 0x0aacdeb6 0xe27ecc6c 0x55567748 0x2d2864fd Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a
-vmlal.u32 q6, d7, d8 :: Qd 0x555555e1 0x555513b5 0x555555e1 0x555513b5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmlal.u32 q7, d8, d9 :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlal.u32 q7, d8, d9 :: Qd 0x5555555b 0x55555555 0x5555555b 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c
-vmlal.u32 q7, d8, d9 :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlal.u32 q10, d11, d15 :: Qd 0x55555555 0x55556095 0x55555555 0x55556095 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmlal.u32 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlal.u32 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000
----- VMLSL ----
-vmlsl.s8 q0, d1, d12 :: Qd 0x000abec8 0xfe72af40 0x55555749 0x53bd47c1 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmlsl.s8 q9, d11, d12 :: Qd 0x55555555 0x55544d55 0x55555555 0x55544d55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlsl.s8 q4, d5, d6 :: Qd 0x55555555 0x4d555553 0x55555555 0x4d555553 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlsl.s8 q4, d5, d6 :: Qd 0x55555555 0x670d680f 0x55555555 0x670d680f Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmlsl.s8 q4, d5, d6 :: Qd 0x55555555 0x555555af 0x55555555 0x555555af Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmlsl.s8 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlsl.s8 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmlsl.u8 q0, d1, d12 :: Qd 0x000ab4c8 0x48722a40 0x55554d49 0x9dbdc2c1 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmlsl.u8 q9, d11, d12 :: Qd 0x55555555 0x55544d55 0x55555555 0x55544d55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlsl.u8 q4, d5, d6 :: Qd 0x55555555 0x4d555553 0x55555555 0x4d555553 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlsl.u8 q4, d5, d6 :: Qd 0x55555555 0x3d0d350f 0x55555555 0x3d0d350f Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmlsl.u8 q4, d5, d6 :: Qd 0x55555555 0x555528af 0x55555555 0x555528af Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmlsl.u8 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlsl.u8 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmlsl.s16 q0, d1, d12 :: Qd 0x000ab4c8 0xfea62640 0x55554d49 0x53f0bec1 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmlsl.s16 q9, d11, d12 :: Qd 0x55555555 0x5553ed55 0x55555555 0x5553ed55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x67492f0f 0x55555555 0x67492f0f Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmlsl.s16 q4, d5, d6 :: Qd 0x5552a555 0x5578e0af 0x5552a555 0x5578e0af Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmlsl.s16 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlsl.s16 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmlsl.u16 q0, d1, d12 :: Qd 0x000ab4c8 0x47212640 0x55554d49 0x9c6bbec1 Qm (i32)0x000abcd4 Qn (i32)0x00cefab1
-vmlsl.u16 q9, d11, d12 :: Qd 0x55555555 0x5553ed55 0x55555555 0x5553ed55 Qm (i32)0x00000140 Qn (i32)0x00000120
-vmlsl.u16 q4, d5, d6 :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553 Qm (i32)0x00004001 Qn (i32)0x00002002
-vmlsl.u16 q4, d5, d6 :: Qd 0x55555555 0x3ca72f0f 0x55555555 0x3ca72f0f Qm (i32)0xffff9433 Qn (i32)0x00002aa2
-vmlsl.u16 q4, d5, d6 :: Qd 0x5552a555 0x547ae0af 0x5552a555 0x547ae0af Qm (i32)0x100000fe Qn (i32)0x002bdc2d
-vmlsl.u16 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlsl.u16 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x40000000
-vmlsl.s32 q0, d1, d2 :: Qd 0x0aaa9ad1 0x32d8ad1c 0x55543362 0x7d8245ad Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a
-vmlsl.s32 q6, d7, d8 :: Qd 0x55555555 0x555596f5 0x55555555 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmlsl.s32 q7, d8, d9 :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlsl.s32 q7, d8, d9 :: Qd 0x5555555b 0x55555555 0x5555555b 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c
-vmlsl.s32 q7, d8, d9 :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlsl.s32 q10, d11, d15 :: Qd 0x55555555 0x55554a15 0x55555555 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmlsl.s32 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlsl.s32 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000
-vmlsl.u32 q0, d1, d2 :: Qd 0x0aaa9ad1 0x32d8ad1c 0x55543362 0x7d8245ad Qm (i32)0x0aabbcc4 Qn (i32)0x001b2c0a
-vmlsl.u32 q6, d7, d8 :: Qd 0x555554c9 0x555596f5 0x555554c9 0x555596f5 Qm (i32)0x0000008c Qn (i32)0xffffff88
-vmlsl.u32 q7, d8, d9 :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlsl.u32 q7, d8, d9 :: Qd 0x5555554f 0x55555555 0x5555554f 0x55555555 Qm (i32)0x80000000 Qn (i32)0x0000000c
-vmlsl.u32 q7, d8, d9 :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmlsl.u32 q10, d11, d15 :: Qd 0x55555555 0x55554a15 0x55555555 0x55554a15 Qm (i32)0x00000018 Qn (i32)0x00000078
-vmlsl.u32 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555 Qm (i32)0x80000000 Qn (i32)0x80000000
-vmlsl.u32 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555 Qm (i32)0x40000000 Qn (i32)0x80000000
----- VQRDMULH ----
-vqrdmulh.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqrdmulh.s32 q6, q7, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqrdmulh.s16 q9, q11, q12 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqrdmulh.s16 q4, q5, q6 :: Qd 0x00001001 0x00001001 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqrdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqrdmulh.s16 q4, q5, q6 :: Qd 0x0000e50b 0x0000e50b 0x0000e50b 0x0000e50b Qm (i32)0xffff9433 Qn (i32)0x00002002 fpscr: 00000000
-vqrdmulh.s32 q7, q8, q9 :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqrdmulh.s16 q4, q5, q6 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqrdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqrdmulh.s32 q10, q11, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqrdmulh.s32 q10, q14, q15 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqrdmulh.s32 q10, q14, q15 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 00000000
-vqrdmulh.s16 q10, q14, q15 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 08000000
-vqrdmulh.s32 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000
-vqrdmulh.s16 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000
----- VQRDMULH (by scalar) ----
-vqrdmulh.s32 q0, q1, d6[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqrdmulh.s32 q6, q7, d1[1] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0xffffff88 fpscr: 00000000
-vqrdmulh.s16 q9, q11, d7[0] :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x00000140 Qn (i32)0x00000120 fpscr: 00000000
-vqrdmulh.s16 q4, q5, d6[0] :: Qd 0x00001001 0x00001001 0x00001001 0x00001001 Qm (i32)0x00004001 Qn (i32)0x00002002 fpscr: 00000000
-vqrdmulh.s32 q7, q8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqrdmulh.s16 q4, q5, d6[1] :: Qd 0x0000e50b 0x0000e50b 0x0000e50b 0x0000e50b Qm (i32)0xffff9433 Qn (i16)0x00002002 fpscr: 00000000
-vqrdmulh.s32 q7, q8, d9[0] :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4 Qm (i32)0x80000000 Qn (i32)0x0000000c fpscr: 00000000
-vqrdmulh.s16 q4, q5, d6[2] :: Qd 0x04000040 0x04000040 0x04000040 0x04000040 Qm (i32)0x100000fe Qn (i32)0x00002002 fpscr: 00000000
-vqrdmulh.s32 q7, q8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
-vqrdmulh.s32 q10, q11, d15[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
-vqrdmulh.s32 q10, q14, d15[1] :: Qd 0xffffff88 0xffffff88 0xffffff88 0xffffff88 Qm (i32)0x80000000 Qn (i32)0x80000000 fpscr: 00000000
-vqrdmulh.s16 q10, q14, d7[3] :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000 Qm (i32)0x80000000 Qn (i32)0x80000001 fpscr: 08000000
-vqrdmulh.s32 q10, q14, d15[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x40000000 Qn (i32)0x80000000 fpscr: 00000000
-vqrdmulh.s16 q10, q14, d7[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000 Qm (i32)0x80000000 Qn (i32)0x40000000 fpscr: 00000000
----- VADD (fp) ----
-vadd.f32 q0, q5, q2 :: Qd 0xc1b43ac6 0xc1b43ac6 0xc1b43ac6 0xc1b43ac6 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vadd.f32 q3, q4, q5 :: Qd 0xc8a931cf 0xc8a931cf 0xc8a931cf 0xc8a931cf Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vadd.f32 q10, q11, q2 :: Qd 0x45398860 0x45398860 0x45398860 0x45398860 Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vadd.f32 q9, q5, q7 :: Qd 0x47dc9261 0x47dc9261 0x47dc9261 0x47dc9261 Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vadd.f32 q0, q5, q2 :: Qd 0xc88faac0 0xc88faac0 0xc88faac0 0xc88faac0 Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vadd.f32 q3, q4, q5 :: Qd 0x44ab4000 0x44ab4000 0x44ab4000 0x44ab4000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vadd.f32 q10, q11, q2 :: Qd 0x4742b400 0x4742b400 0x4742b400 0x4742b400 Qm (i32)0x473e7300 Qn (i32)0x44882000
-vadd.f32 q9, q5, q7 :: Qd 0x49d5e6b8 0x49d5e6b8 0x49d5e6b8 0x49d5e6b8 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vadd.f32 q0, q11, q12 :: Qd 0x48b0b752 0x48b0b752 0x48b0b752 0x48b0b752 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vadd.f32 q7, q1, q6 :: Qd 0x420802fd 0x420802fd 0x420802fd 0x420802fd Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vadd.f32 q0, q1, q2 :: Qd 0x4532d000 0x4532d000 0x4532d000 0x4532d000 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vadd.f32 q3, q4, q5 :: Qd 0x450d299a 0x450d299a 0x450d299a 0x450d299a Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vadd.f32 q10, q11, q2 :: Qd 0x44152592 0x44152592 0x44152592 0x44152592 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vadd.f32 q9, q5, q7 :: Qd 0x4573a000 0x4573a000 0x4573a000 0x4573a000 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vadd.f32 q0, q11, q12 :: Qd 0xc5b695c3 0xc5b695c3 0xc5b695c3 0xc5b695c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vadd.f32 q7, q1, q6 :: Qd 0x43e07a2a 0x43e07a2a 0x43e07a2a 0x43e07a2a Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vadd.f32 q0, q5, q2 :: Qd 0x44053ee0 0x44053ee0 0x44053ee0 0x44053ee0 Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vadd.f32 q10, q13, q15 :: Qd 0xc4838fb4 0xc4838fb4 0xc4838fb4 0xc4838fb4 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vadd.f32 q10, q13, q15 :: Qd 0x488c3d8e 0x488c3d8e 0x488c3d8e 0x488c3d8e Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vadd.f32 q0, q1, q2 :: Qd 0x4efa8dc5 0x4efa8dc5 0x4efa8dc5 0x4efa8dc5 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vadd.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vadd.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VSUB (fp) ----
-vsub.f32 q0, q5, q2 :: Qd 0x428937a8 0x428937a8 0x428937a8 0x428937a8 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vsub.f32 q3, q4, q5 :: Qd 0xc8aa824f 0xc8aa824f 0xc8aa824f 0xc8aa824f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vsub.f32 q10, q11, q2 :: Qd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vsub.f32 q9, q5, q7 :: Qd 0x4799e961 0x4799e961 0x4799e961 0x4799e961 Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vsub.f32 q0, q5, q2 :: Qd 0x484623e2 0x484623e2 0x484623e2 0x484623e2 Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vsub.f32 q3, q4, q5 :: Qd 0xc4a52385 0xc4a52385 0xc4a52385 0xc4a52385 Qm (i32)0x41c71eb8 Qn (i32)0x44a84000
-vsub.f32 q10, q11, q2 :: Qd 0x473a3200 0x473a3200 0x473a3200 0x473a3200 Qm (i32)0x473e7300 Qn (i32)0x44882000
-vsub.f32 q9, q5, q7 :: Qd 0xc9d5d958 0xc9d5d958 0xc9d5d958 0xc9d5d958 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vsub.f32 q0, q11, q12 :: Qd 0x48aafc92 0x48aafc92 0x48aafc92 0x48aafc92 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vsub.f32 q7, q1, q6 :: Qd 0x4207fdf5 0x4207fdf5 0x4207fdf5 0x4207fdf5 Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vsub.f32 q0, q1, q2 :: Qd 0x45257000 0x45257000 0x45257000 0x45257000 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vsub.f32 q3, q4, q5 :: Qd 0xc3ff4ccc 0xc3ff4ccc 0xc3ff4ccc 0xc3ff4ccc Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vsub.f32 q10, q11, q2 :: Qd 0x43bd4b23 0x43bd4b23 0x43bd4b23 0x43bd4b23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vsub.f32 q9, q5, q7 :: Qd 0x43c50000 0x43c50000 0x43c50000 0x43c50000 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vsub.f32 q0, q11, q12 :: Qd 0x45b311c3 0x45b311c3 0x45b311c3 0x45b311c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vsub.f32 q7, q1, q6 :: Qd 0x43e7c592 0x43e7c592 0x43e7c592 0x43e7c592 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vsub.f32 q0, q5, q2 :: Qd 0x44053f76 0x44053f76 0x44053f76 0x44053f76 Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vsub.f32 q10, q13, q15 :: Qd 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vsub.f32 q10, q13, q15 :: Qd 0x4883b08e 0x4883b08e 0x4883b08e 0x4883b08e Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vsub.f32 q0, q1, q2 :: Qd 0xcda5da84 0xcda5da84 0xcda5da84 0xcda5da84 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vsub.f32 q0, q1, q2 :: Qd 0xbf800000 0xbf800000 0xbf800000 0xbf800000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vsub.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VABD (fp) ----
-vabd.f32 q0, q5, q2 :: Qd 0x428937a8 0x428937a8 0x428937a8 0x428937a8 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vabd.f32 q3, q4, q5 :: Qd 0x48aa824f 0x48aa824f 0x48aa824f 0x48aa824f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vabd.f32 q10, q11, q2 :: Qd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vabd.f32 q9, q5, q7 :: Qd 0x4799e961 0x4799e961 0x4799e961 0x4799e961 Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vabd.f32 q0, q5, q2 :: Qd 0x484623e2 0x484623e2 0x484623e2 0x484623e2 Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vabd.f32 q3, q4, q5 :: Qd 0x44a54000 0x44a54000 0x44a54000 0x44a54000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vabd.f32 q10, q11, q2 :: Qd 0x473a3200 0x473a3200 0x473a3200 0x473a3200 Qm (i32)0x473e7300 Qn (i32)0x44882000
-vabd.f32 q9, q5, q7 :: Qd 0x49d5d958 0x49d5d958 0x49d5d958 0x49d5d958 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vabd.f32 q0, q11, q12 :: Qd 0x48aafc92 0x48aafc92 0x48aafc92 0x48aafc92 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vabd.f32 q7, q1, q6 :: Qd 0x4207fdf5 0x4207fdf5 0x4207fdf5 0x4207fdf5 Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vabd.f32 q0, q1, q2 :: Qd 0x45257000 0x45257000 0x45257000 0x45257000 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vabd.f32 q3, q4, q5 :: Qd 0x43ff4ccc 0x43ff4ccc 0x43ff4ccc 0x43ff4ccc Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vabd.f32 q10, q11, q2 :: Qd 0x43bd4b23 0x43bd4b23 0x43bd4b23 0x43bd4b23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vabd.f32 q9, q5, q7 :: Qd 0x43c50000 0x43c50000 0x43c50000 0x43c50000 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vabd.f32 q0, q11, q12 :: Qd 0x45b311c3 0x45b311c3 0x45b311c3 0x45b311c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vabd.f32 q7, q1, q6 :: Qd 0x43e7c592 0x43e7c592 0x43e7c592 0x43e7c592 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vabd.f32 q0, q5, q2 :: Qd 0x44053f76 0x44053f76 0x44053f76 0x44053f76 Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vabd.f32 q10, q13, q15 :: Qd 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vabd.f32 q10, q13, q15 :: Qd 0x4883b08e 0x4883b08e 0x4883b08e 0x4883b08e Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vabd.f32 q0, q1, q2 :: Qd 0x4da5da84 0x4da5da84 0x4da5da84 0x4da5da84 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vabd.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vabd.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VMUL (fp) ----
-vmul.f32 q0, q5, q2 :: Qd 0xc4833ce4 0xc4833ce4 0xc4833ce4 0xc4833ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vmul.f32 q3, q4, q5 :: Qd 0xcddf4321 0xcddf4321 0xcddf4321 0xcddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vmul.f32 q10, q11, q2 :: Qd 0xcf050e7f 0xcf050e7f 0xcf050e7f 0xcf050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vmul.f32 q9, q5, q7 :: Qd 0x4ec3063f 0x4ec3063f 0x4ec3063f 0x4ec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vmul.f32 q0, q5, q2 :: Qd 0x5029254c 0x5029254c 0x5029254c 0x5029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vmul.f32 q3, q4, q5 :: Qd 0x46fc6000 0x46fc6000 0x46fc6000 0x46fc6000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vmul.f32 q10, q11, q2 :: Qd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd Qm (i32)0x473e7300 Qn (i32)0x44882000
-vmul.f32 q9, q5, q7 :: Qd 0x4db2c947 0x4db2c947 0x4db2c947 0x4db2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vmul.f32 q0, q11, q12 :: Qd 0x4ef90536 0x4ef90536 0x4ef90536 0x4ef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vmul.f32 q7, q1, q6 :: Qd 0x3dab1f7a 0x3dab1f7a 0x3dab1f7a 0x3dab1f7a Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vmul.f32 q0, q1, q2 :: Qd 0x488fe2c0 0x488fe2c0 0x488fe2c0 0x488fe2c0 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vmul.f32 q3, q4, q5 :: Qd 0x4993b8e3 0x4993b8e3 0x4993b8e3 0x4993b8e3 Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vmul.f32 q10, q11, q2 :: Qd 0x474f9afc 0x474f9afc 0x474f9afc 0x474f9afc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vmul.f32 q9, q5, q7 :: Qd 0x4a657ac0 0x4a657ac0 0x4a657ac0 0x4a657ac0 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vmul.f32 q0, q11, q12 :: Qd 0x489eee1e 0x489eee1e 0x489eee1e 0x489eee1e Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vmul.f32 q7, q1, q6 :: Qd 0xc5500239 0xc5500239 0xc5500239 0xc5500239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vmul.f32 q0, q5, q2 :: Qd 0xc01c7d07 0xc01c7d07 0xc01c7d07 0xc01c7d07 Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vmul.f32 q10, q13, q15 :: Qd 0x488666a6 0x488666a6 0x488666a6 0x488666a6 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vmul.f32 q10, q13, q15 :: Qd 0x4f115379 0x4f115379 0x4f115379 0x4f115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vmul.f32 q0, q1, q2 :: Qd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vmul.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vmul.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vmul.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vmul.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vmul.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vmul.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vmul.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vmul.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VMLA (fp) ----
-vmla.f32 q0, q5, q2 :: Qd 0xc4831ce4 0xc4831ce4 0xc4831ce4 0xc4831ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vmla.f32 q3, q4, q5 :: Qd 0xcddf4321 0xcddf4321 0xcddf4321 0xcddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vmla.f32 q10, q11, q2 :: Qd 0xcf050e7f 0xcf050e7f 0xcf050e7f 0xcf050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vmla.f32 q9, q5, q7 :: Qd 0x4ec3063f 0x4ec3063f 0x4ec3063f 0x4ec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vmla.f32 q0, q5, q2 :: Qd 0x5029254c 0x5029254c 0x5029254c 0x5029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vmla.f32 q3, q4, q5 :: Qd 0x46fc6200 0x46fc6200 0x46fc6200 0x46fc6200 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vmla.f32 q10, q11, q2 :: Qd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd Qm (i32)0x473e7300 Qn (i32)0x44882000
-vmla.f32 q9, q5, q7 :: Qd 0x4db2c947 0x4db2c947 0x4db2c947 0x4db2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vmla.f32 q0, q11, q12 :: Qd 0x4ef90536 0x4ef90536 0x4ef90536 0x4ef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vmla.f32 q7, q1, q6 :: Qd 0x3f8ab1f8 0x3f8ab1f8 0x3f8ab1f8 0x3f8ab1f8 Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vmla.f32 q0, q1, q2 :: Qd 0x488fe2e0 0x488fe2e0 0x488fe2e0 0x488fe2e0 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vmla.f32 q3, q4, q5 :: Qd 0x4993b8eb 0x4993b8eb 0x4993b8eb 0x4993b8eb Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vmla.f32 q10, q11, q2 :: Qd 0x474f9bfc 0x474f9bfc 0x474f9bfc 0x474f9bfc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vmla.f32 q9, q5, q7 :: Qd 0x4a657ac4 0x4a657ac4 0x4a657ac4 0x4a657ac4 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vmla.f32 q0, q11, q12 :: Qd 0x489eee3e 0x489eee3e 0x489eee3e 0x489eee3e Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vmla.f32 q7, q1, q6 :: Qd 0xc54ff239 0xc54ff239 0xc54ff239 0xc54ff239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vmla.f32 q0, q5, q2 :: Qd 0xbfb8fa0e 0xbfb8fa0e 0xbfb8fa0e 0xbfb8fa0e Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vmla.f32 q10, q13, q15 :: Qd 0x488666c6 0x488666c6 0x488666c6 0x488666c6 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vmla.f32 q10, q13, q15 :: Qd 0x4f115379 0x4f115379 0x4f115379 0x4f115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vmla.f32 q0, q1, q2 :: Qd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VMLA (fp by scalar) ----
-vmla.f32 q0, q1, d4[0] :: Qd 0x45341000 0x45341000 0x45341000 0x45341000 Qm (i32)0x41c00000 Qn (i32)0x42f00000
-vmla.f32 q15, q8, d7[1] :: Qd 0xc6833e00 0xc6833e00 0xc6833e00 0xc6833e00 Qm (i32)0x430c0000 Qn (i32)0xc2f00000
-vmla.f32 q4, q8, d15[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmla.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmla.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmla.f32 q7, q8, d1[0] :: Qd 0x447a3fff 0x447a3fff 0x447a3fff 0x447a3fff Qm (i32)0x64078678 Qn (i32)0x1fec1e4a
-vmla.f32 q7, q8, d1[0] :: Qd 0x65a96816 0x65a96816 0x65a96816 0x65a96816 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x40000000 0x40000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x40000000 0x40000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x40000000 0x40000000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VMLS (fp) ----
-vmls.f32 q0, q5, q2 :: Qd 0x44835ce4 0x44835ce4 0x44835ce4 0x44835ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vmls.f32 q3, q4, q5 :: Qd 0x4ddf4321 0x4ddf4321 0x4ddf4321 0x4ddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vmls.f32 q10, q11, q2 :: Qd 0x4f050e7f 0x4f050e7f 0x4f050e7f 0x4f050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vmls.f32 q9, q5, q7 :: Qd 0xcec3063f 0xcec3063f 0xcec3063f 0xcec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vmls.f32 q0, q5, q2 :: Qd 0xd029254c 0xd029254c 0xd029254c 0xd029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vmls.f32 q3, q4, q5 :: Qd 0xc6fc5e00 0xc6fc5e00 0xc6fc5e00 0xc6fc5e00 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vmls.f32 q10, q11, q2 :: Qd 0xcc4a89cd 0xcc4a89cd 0xcc4a89cd 0xcc4a89cd Qm (i32)0x473e7300 Qn (i32)0x44882000
-vmls.f32 q9, q5, q7 :: Qd 0xcdb2c947 0xcdb2c947 0xcdb2c947 0xcdb2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vmls.f32 q0, q11, q12 :: Qd 0xcef90536 0xcef90536 0xcef90536 0xcef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vmls.f32 q7, q1, q6 :: Qd 0x3f6a9c11 0x3f6a9c11 0x3f6a9c11 0x3f6a9c11 Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vmls.f32 q0, q1, q2 :: Qd 0xc88fe2a0 0xc88fe2a0 0xc88fe2a0 0xc88fe2a0 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vmls.f32 q3, q4, q5 :: Qd 0xc993b8db 0xc993b8db 0xc993b8db 0xc993b8db Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vmls.f32 q10, q11, q2 :: Qd 0xc74f99fc 0xc74f99fc 0xc74f99fc 0xc74f99fc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vmls.f32 q9, q5, q7 :: Qd 0xca657abc 0xca657abc 0xca657abc 0xca657abc Qm (i32)0x45062000 Qn (i32)0x44db0000
-vmls.f32 q0, q11, q12 :: Qd 0xc89eedfe 0xc89eedfe 0xc89eedfe 0xc89eedfe Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vmls.f32 q7, q1, q6 :: Qd 0x45501239 0x45501239 0x45501239 0x45501239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vmls.f32 q0, q5, q2 :: Qd 0x405c7d07 0x405c7d07 0x405c7d07 0x405c7d07 Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vmls.f32 q10, q13, q15 :: Qd 0xc8866686 0xc8866686 0xc8866686 0xc8866686 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vmls.f32 q10, q13, q15 :: Qd 0xcf115379 0xcf115379 0xcf115379 0xcf115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vmls.f32 q0, q1, q2 :: Qd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VMLS (fp by scalar) ----
-vmls.f32 q0, q1, d4[0] :: Qd 0xc533f000 0xc533f000 0xc533f000 0xc533f000 Qm (i32)0x41c00000 Qn (i32)0x42f00000
-vmls.f32 q15, q8, d7[1] :: Qd 0x46834200 0x46834200 0x46834200 0x46834200 Qm (i32)0x430c0000 Qn (i32)0xc2f00000
-vmls.f32 q4, q8, d15[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmls.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000000 Qn (i16)0x0000000c
-vmls.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x80000001 Qn (i32)0x80000002
-vmls.f32 q7, q8, d1[0] :: Qd 0xc479bfff 0xc479bfff 0xc479bfff 0xc479bfff Qm (i32)0x64078678 Qn (i32)0x1fec1e4a
-vmls.f32 q7, q8, d1[0] :: Qd 0xe5a96816 0xe5a96816 0xe5a96816 0xe5a96816 Qm (i32)0x5368d4a5 Qn (i32)0x51ba43b7
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VCVT (integer <-> fp) ----
-vcvt.u32.f32 q0, q1 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x404ccccd
-vcvt.u32.f32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4
-vcvt.u32.f32 q15, q4 :: Qd 0xb2d05e00 0xb2d05e00 0xb2d05e00 0xb2d05e00 Qm (i32)0x4f32d05e
-vcvt.u32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000
-vcvt.u32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0e33333
-vcvt.u32.f32 q12, q8 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x40fff800
-vcvt.u32.f32 q12, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0fff800
-vcvt.s32.f32 q0, q1 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003 Qm (i32)0x404ccccd
-vcvt.s32.f32 q10, q11 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x64cb49b4
-vcvt.s32.f32 q15, q4 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x4f32d05e
-vcvt.s32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000
-vcvt.s32.f32 q15, q4 :: Qd 0xfffffff9 0xfffffff9 0xfffffff9 0xfffffff9 Qm (i32)0xc0e33333
-vcvt.s32.f32 q12, q8 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x40fff800
-vcvt.s32.f32 q12, q8 :: Qd 0xfffffff9 0xfffffff9 0xfffffff9 0xfffffff9 Qm (i32)0xc0fff800
-vcvt.f32.u32 q0, q1 :: Qd 0x40e00000 0x40e00000 0x40e00000 0x40e00000 Qm (i32)0x00000007
-vcvt.f32.u32 q10, q11 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000 Qm (i32)0x80000000
-vcvt.f32.u32 q0, q1 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000 Qm (i32)0x80000001
-vcvt.f32.u32 q0, q1 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000 Qm (i32)0x7fffffff
-vcvt.f32.u32 q0, q14 :: Qd 0x4e4282f4 0x4e4282f4 0x4e4282f4 0x4e4282f4 Qm (i32)0x30a0bcef
-vcvt.f32.s32 q0, q1 :: Qd 0x40e00000 0x40e00000 0x40e00000 0x40e00000 Qm (i32)0x00000007
-vcvt.f32.s32 q10, q11 :: Qd 0xcf000000 0xcf000000 0xcf000000 0xcf000000 Qm (i32)0x80000000
-vcvt.f32.s32 q0, q1 :: Qd 0xcf000000 0xcf000000 0xcf000000 0xcf000000 Qm (i32)0x80000001
-vcvt.f32.s32 q0, q1 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000 Qm (i32)0x7fffffff
-vcvt.f32.s32 q0, q14 :: Qd 0x4e4282f4 0x4e4282f4 0x4e4282f4 0x4e4282f4 Qm (i32)0x30a0bcef
-vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000
-vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vcvt.u32.f32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000
-vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000
-vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000
-vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vcvt.s32.f32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x7f800000
-vcvt.s32.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xff800000
----- VCVT (fixed <-> fp) ----
-vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019 Qm (i32)0x404ccccd
-vcvt.u32.f32 q10, q11, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4
-vcvt.u32.f32 q15, q4, #32 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4f32d05e
-vcvt.u32.f32 q15, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf000000
-vcvt.u32.f32 q15, q4, #4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0e33333
-vcvt.u32.f32 q12, q8, #3 :: Qd 0x0000003f 0x0000003f 0x0000003f 0x0000003f Qm (i32)0x40fff800
-vcvt.u32.f32 q12, q8, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc0fff800
-vcvt.s32.f32 q0, q1, #5 :: Qd 0x00000066 0x00000066 0x00000066 0x00000066 Qm (i32)0x404ccccd
-vcvt.s32.f32 q10, q11, #1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x64cb49b4
-vcvt.s32.f32 q15, q4, #8 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x4f32d05e
-vcvt.s32.f32 q15, q4, #2 :: Qd 0xfffffffe 0xfffffffe 0xfffffffe 0xfffffffe Qm (i32)0xbf000000
-vcvt.s32.f32 q15, q4, #1 :: Qd 0xfffffff2 0xfffffff2 0xfffffff2 0xfffffff2 Qm (i32)0xc0e33333
-vcvt.s32.f32 q12, q8, #2 :: Qd 0x0000001f 0x0000001f 0x0000001f 0x0000001f Qm (i32)0x40fff800
-vcvt.s32.f32 q12, q8, #2 :: Qd 0xffffffe1 0xffffffe1 0xffffffe1 0xffffffe1 Qm (i32)0xc0fff800
-vcvt.f32.u32 q0, q1, #5 :: Qd 0x3e600000 0x3e600000 0x3e600000 0x3e600000 Qm (i32)0x00000007
-vcvt.f32.u32 q10, q11, #9 :: Qd 0x4a800000 0x4a800000 0x4a800000 0x4a800000 Qm (i32)0x80000000
-vcvt.f32.u32 q0, q1, #4 :: Qd 0x4d000000 0x4d000000 0x4d000000 0x4d000000 Qm (i32)0x80000001
-vcvt.f32.u32 q0, q1, #6 :: Qd 0x4c000000 0x4c000000 0x4c000000 0x4c000000 Qm (i32)0x7fffffff
-vcvt.f32.u32 q0, q14, #5 :: Qd 0x4bc282f4 0x4bc282f4 0x4bc282f4 0x4bc282f4 Qm (i32)0x30a0bcef
-vcvt.f32.s32 q0, q1, #12 :: Qd 0x3ae00000 0x3ae00000 0x3ae00000 0x3ae00000 Qm (i32)0x00000007
-vcvt.f32.s32 q10, q11, #8 :: Qd 0xcb000000 0xcb000000 0xcb000000 0xcb000000 Qm (i32)0x80000000
-vcvt.f32.s32 q0, q1, #2 :: Qd 0xce000000 0xce000000 0xce000000 0xce000000 Qm (i32)0x80000001
-vcvt.f32.s32 q0, q1, #1 :: Qd 0x4e800000 0x4e800000 0x4e800000 0x4e800000 Qm (i32)0x7fffffff
-vcvt.f32.s32 q0, q14, #6 :: Qd 0x4b4282f4 0x4b4282f4 0x4b4282f4 0x4b4282f4 Qm (i32)0x30a0bcef
-vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000
-vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vcvt.u32.f32 q0, q1, #3 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000
-vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000
-vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000
-vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vcvt.s32.f32 q0, q1, #3 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x7f800000
-vcvt.s32.f32 q0, q1, #3 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xff800000
----- VMAX (fp) ----
-vmax.f32 q0, q5, q2 :: Qd 0x41b851ec 0x41b851ec 0x41b851ec 0x41b851ec Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vmax.f32 q3, q4, q5 :: Qd 0x44a84000 0x44a84000 0x44a84000 0x44a84000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vmax.f32 q10, q11, q2 :: Qd 0x473e7300 0x473e7300 0x473e7300 0x473e7300 Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vmax.f32 q9, q5, q7 :: Qd 0x47bb3de1 0x47bb3de1 0x47bb3de1 0x47bb3de1 Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vmax.f32 q0, q5, q2 :: Qd 0xc732633d 0xc732633d 0xc732633d 0xc732633d Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vmax.f32 q3, q4, q5 :: Qd 0x44a84000 0x44a84000 0x44a84000 0x44a84000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vmax.f32 q10, q11, q2 :: Qd 0x473e7300 0x473e7300 0x473e7300 0x473e7300 Qm (i32)0x473e7300 Qn (i32)0x44882000
-vmax.f32 q9, q5, q7 :: Qd 0x49d5e008 0x49d5e008 0x49d5e008 0x49d5e008 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vmax.f32 q0, q11, q12 :: Qd 0x48add9f2 0x48add9f2 0x48add9f2 0x48add9f2 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vmax.f32 q7, q1, q6 :: Qd 0x42080079 0x42080079 0x42080079 0x42080079 Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vmax.f32 q0, q1, q2 :: Qd 0x452c2000 0x452c2000 0x452c2000 0x452c2000 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vmax.f32 q3, q4, q5 :: Qd 0x44ad1333 0x44ad1333 0x44ad1333 0x44ad1333 Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vmax.f32 q10, q11, q2 :: Qd 0x43f3cb23 0x43f3cb23 0x43f3cb23 0x43f3cb23 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vmax.f32 q9, q5, q7 :: Qd 0x45062000 0x45062000 0x45062000 0x45062000 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vmax.f32 q0, q11, q12 :: Qd 0xc2610000 0xc2610000 0xc2610000 0xc2610000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vmax.f32 q7, q1, q6 :: Qd 0x43e41fde 0x43e41fde 0x43e41fde 0x43e41fde Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vmax.f32 q0, q5, q2 :: Qd 0x44053f2b 0x44053f2b 0x44053f2b 0x44053f2b Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vmax.f32 q10, q13, q15 :: Qd 0xc3f29f73 0xc3f29f73 0xc3f29f73 0xc3f29f73 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vmax.f32 q10, q13, q15 :: Qd 0x4887f70e 0x4887f70e 0x4887f70e 0x4887f70e Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vmax.f32 q0, q1, q2 :: Qd 0x4e920233 0x4e920233 0x4e920233 0x4e920233 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vmax.f32 q0, q1, q2 :: Qd 0x3a800000 0x3a800000 0x3a800000 0x3a800000 Qm (i32)0x3a800000 Qn (i32)0xba800000
-vmax.f32 q0, q1, q2 :: Qd 0x3a800000 0x3a800000 0x3a800000 0x3a800000 Qm (i32)0xba800000 Qn (i32)0x3a800000
-vmax.f32 q0, q1, q2 :: Qd 0x45126004 0x45126004 0x45126004 0x45126004 Qm (i32)0x45126004 Qn (i32)0x45125ffc
-vmax.f32 q0, q1, q2 :: Qd 0xc5125ffc 0xc5125ffc 0xc5125ffc 0xc5125ffc Qm (i32)0xc5125ffc Qn (i32)0xc5126004
-vmax.f32 q0, q1, q2 :: Qd 0x47ae5e00 0x47ae5e00 0x47ae5e00 0x47ae5e00 Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00
-vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vmax.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vmax.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vmax.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VMIN (fp) ----
-vmin.f32 q0, q5, q2 :: Qd 0xc2364659 0xc2364659 0xc2364659 0xc2364659 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vmin.f32 q3, q4, q5 :: Qd 0xc8a9da0f 0xc8a9da0f 0xc8a9da0f 0xc8a9da0f Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vmin.f32 q10, q11, q2 :: Qd 0xc732da7a 0xc732da7a 0xc732da7a 0xc732da7a Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vmin.f32 q9, q5, q7 :: Qd 0x46855200 0x46855200 0x46855200 0x46855200 Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vmin.f32 q0, q5, q2 :: Qd 0xc872bcb1 0xc872bcb1 0xc872bcb1 0xc872bcb1 Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vmin.f32 q3, q4, q5 :: Qd 0x41c00000 0x41c00000 0x41c00000 0x41c00000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vmin.f32 q10, q11, q2 :: Qd 0x44882000 0x44882000 0x44882000 0x44882000 Qm (i32)0x473e7300 Qn (i32)0x44882000
-vmin.f32 q9, q5, q7 :: Qd 0x43560000 0x43560000 0x43560000 0x43560000 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vmin.f32 q0, q11, q12 :: Qd 0x45b75812 0x45b75812 0x45b75812 0x45b75812 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vmin.f32 q7, q1, q6 :: Qd 0x3b210e02 0x3b210e02 0x3b210e02 0x3b210e02 Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vmin.f32 q0, q1, q2 :: Qd 0x42d60000 0x42d60000 0x42d60000 0x42d60000 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vmin.f32 q3, q4, q5 :: Qd 0x445a8000 0x445a8000 0x445a8000 0x445a8000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vmin.f32 q10, q11, q2 :: Qd 0x42da0000 0x42da0000 0x42da0000 0x42da0000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vmin.f32 q9, q5, q7 :: Qd 0x44db0000 0x44db0000 0x44db0000 0x44db0000 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vmin.f32 q0, q11, q12 :: Qd 0xc5b4d3c3 0xc5b4d3c3 0xc5b4d3c3 0xc5b4d3c3 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vmin.f32 q7, q1, q6 :: Qd 0xc0e96d19 0xc0e96d19 0xc0e96d19 0xc0e96d19 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vmin.f32 q0, q5, q2 :: Qd 0xbb965394 0xbb965394 0xbb965394 0xbb965394 Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vmin.f32 q10, q13, q15 :: Qd 0xc40dcfae 0xc40dcfae 0xc40dcfae 0xc40dcfae Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vmin.f32 q10, q13, q15 :: Qd 0x4608d008 0x4608d008 0x4608d008 0x4608d008 Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vmin.f32 q0, q1, q2 :: Qd 0x4e511724 0x4e511724 0x4e511724 0x4e511724 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vmin.f32 q0, q1, q2 :: Qd 0xba800000 0xba800000 0xba800000 0xba800000 Qm (i32)0x3a800000 Qn (i32)0xba800000
-vmin.f32 q0, q1, q2 :: Qd 0xba800000 0xba800000 0xba800000 0xba800000 Qm (i32)0xba800000 Qn (i32)0x3a800000
-vmin.f32 q0, q1, q2 :: Qd 0x45125ffc 0x45125ffc 0x45125ffc 0x45125ffc Qm (i32)0x45126004 Qn (i32)0x45125ffc
-vmin.f32 q0, q1, q2 :: Qd 0xc5126004 0xc5126004 0xc5126004 0xc5126004 Qm (i32)0xc5125ffc Qn (i32)0xc5126004
-vmin.f32 q0, q1, q2 :: Qd 0x47ae5e00 0x47ae5e00 0x47ae5e00 0x47ae5e00 Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00
-vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vmin.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vmin.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VRECPE ----
-vrecpe.u32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x404ccccd
-vrecpe.u32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4
-vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4f32d05e
-vrecpe.u32 q15, q4 :: Qd 0xab800000 0xab800000 0xab800000 0xab800000 Qm (i32)0xbf000000
-vrecpe.u32 q15, q4 :: Qd 0xaa000000 0xaa000000 0xaa000000 0xaa000000 Qm (i32)0xc0e33333
-vrecpe.u32 q12, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x40fff800
-vrecpe.u32 q12, q8 :: Qd 0xaa000000 0xaa000000 0xaa000000 0xaa000000 Qm (i32)0xc0fff800
-vrecpe.u32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x404ccccd
-vrecpe.u32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x64cb49b4
-vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4f32d05e
-vrecpe.f32 q15, q4 :: Qd 0xbfff8000 0xbfff8000 0xbfff8000 0xbfff8000 Qm (i32)0xbf000000
-vrecpe.f32 q15, q4 :: Qd 0xbe100000 0xbe100000 0xbe100000 0xbe100000 Qm (i32)0xc0e33333
-vrecpe.f32 q12, q8 :: Qd 0x3e000000 0x3e000000 0x3e000000 0x3e000000 Qm (i32)0x40fff800
-vrecpe.f32 q12, q8 :: Qd 0xbe000000 0xbe000000 0xbe000000 0xbe000000 Qm (i32)0xc0fff800
-vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000007
-vrecpe.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000000
-vrecpe.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000001
-vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff
-vrecpe.f32 q0, q14 :: Qd 0x4e4c0000 0x4e4c0000 0x4e4c0000 0x4e4c0000 Qm (i32)0x30a0bcef
-vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000007
-vrecpe.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000000
-vrecpe.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x80000001
-vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fffffff
-vrecpe.f32 q0, q14 :: Qd 0x4e4c0000 0x4e4c0000 0x4e4c0000 0x4e4c0000 Qm (i32)0x30a0bcef
-vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000
-vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000
-vrecpe.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000
-vrecpe.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xff800000
-vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000
-vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x00000000
-vrecpe.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000
-vrecpe.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0xff800000
----- VRECPS ----
-vrecps.f32 q0, q5, q2 :: Qd 0x44837ce4 0x44837ce4 0x44837ce4 0x44837ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vrecps.f32 q3, q4, q5 :: Qd 0x4ddf4321 0x4ddf4321 0x4ddf4321 0x4ddf4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vrecps.f32 q10, q11, q2 :: Qd 0x4f050e7f 0x4f050e7f 0x4f050e7f 0x4f050e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vrecps.f32 q9, q5, q7 :: Qd 0xcec3063f 0xcec3063f 0xcec3063f 0xcec3063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vrecps.f32 q0, q5, q2 :: Qd 0xd029254c 0xd029254c 0xd029254c 0xd029254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vrecps.f32 q3, q4, q5 :: Qd 0xc6fc5c00 0xc6fc5c00 0xc6fc5c00 0xc6fc5c00 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vrecps.f32 q10, q11, q2 :: Qd 0xcc4a89cc 0xcc4a89cc 0xcc4a89cc 0xcc4a89cc Qm (i32)0x473e7300 Qn (i32)0x44882000
-vrecps.f32 q9, q5, q7 :: Qd 0xcdb2c947 0xcdb2c947 0xcdb2c947 0xcdb2c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vrecps.f32 q0, q11, q12 :: Qd 0xcef90536 0xcef90536 0xcef90536 0xcef90536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vrecps.f32 q7, q1, q6 :: Qd 0x3ff54e08 0x3ff54e08 0x3ff54e08 0x3ff54e08 Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vrecps.f32 q0, q1, q2 :: Qd 0xc88fe280 0xc88fe280 0xc88fe280 0xc88fe280 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vrecps.f32 q3, q4, q5 :: Qd 0xc993b8d3 0xc993b8d3 0xc993b8d3 0xc993b8d3 Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vrecps.f32 q10, q11, q2 :: Qd 0xc74f98fc 0xc74f98fc 0xc74f98fc 0xc74f98fc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vrecps.f32 q9, q5, q7 :: Qd 0xca657ab8 0xca657ab8 0xca657ab8 0xca657ab8 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vrecps.f32 q0, q11, q12 :: Qd 0xc89eedde 0xc89eedde 0xc89eedde 0xc89eedde Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vrecps.f32 q7, q1, q6 :: Qd 0x45502239 0x45502239 0x45502239 0x45502239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vrecps.f32 q0, q5, q2 :: Qd 0x408e3e84 0x408e3e84 0x408e3e84 0x408e3e84 Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vrecps.f32 q10, q13, q15 :: Qd 0xc8866666 0xc8866666 0xc8866666 0xc8866666 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vrecps.f32 q10, q13, q15 :: Qd 0xcf115379 0xcf115379 0xcf115379 0xcf115379 Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vrecps.f32 q0, q1, q2 :: Qd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vrecps.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vrecps.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vrecps.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vrecps.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vrecps.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vrecps.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VABS (fp) ----
-vabs.f32 q0, q1 :: Qd 0x404ccccd 0x404ccccd 0x404ccccd 0x404ccccd Qm (i32)0x404ccccd
-vabs.f32 q10, q11 :: Qd 0x64cb49b4 0x64cb49b4 0x64cb49b4 0x64cb49b4 Qm (i32)0x64cb49b4
-vabs.f32 q15, q4 :: Qd 0x4f32d05e 0x4f32d05e 0x4f32d05e 0x4f32d05e Qm (i32)0x4f32d05e
-vabs.f32 q15, q4 :: Qd 0x3f000000 0x3f000000 0x3f000000 0x3f000000 Qm (i32)0xbf000000
-vabs.f32 q15, q4 :: Qd 0x40e33333 0x40e33333 0x40e33333 0x40e33333 Qm (i32)0xc0e33333
-vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800 Qm (i32)0x40fff800
-vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800 Qm (i32)0xc0fff800
-vabs.f32 q0, q1 :: Qd 0x404ccccd 0x404ccccd 0x404ccccd 0x404ccccd Qm (i32)0x404ccccd
-vabs.f32 q10, q11 :: Qd 0x64cb49b4 0x64cb49b4 0x64cb49b4 0x64cb49b4 Qm (i32)0x64cb49b4
-vabs.f32 q15, q4 :: Qd 0x4f32d05e 0x4f32d05e 0x4f32d05e 0x4f32d05e Qm (i32)0x4f32d05e
-vabs.f32 q15, q4 :: Qd 0x3f000000 0x3f000000 0x3f000000 0x3f000000 Qm (i32)0xbf000000
-vabs.f32 q15, q4 :: Qd 0x40e33333 0x40e33333 0x40e33333 0x40e33333 Qm (i32)0xc0e33333
-vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800 Qm (i32)0x40fff800
-vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800 Qm (i32)0xc0fff800
-vabs.f32 q0, q1 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x00000007
-vabs.f32 q10, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000
-vabs.f32 q0, q1 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001
-vabs.f32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x7fffffff
-vabs.f32 q0, q14 :: Qd 0x30a0bcef 0x30a0bcef 0x30a0bcef 0x30a0bcef Qm (i32)0x30a0bcef
-vabs.f32 q0, q1 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007 Qm (i32)0x00000007
-vabs.f32 q10, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000
-vabs.f32 q0, q1 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001 Qm (i32)0x80000001
-vabs.f32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff Qm (i32)0x7fffffff
-vabs.f32 q0, q14 :: Qd 0x30a0bcef 0x30a0bcef 0x30a0bcef 0x30a0bcef Qm (i32)0x30a0bcef
-vabs.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000
-vabs.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000
-vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000
-vabs.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000
-vabs.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000
-vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000
----- VCGT (fp) ----
-vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000
-vcgt.f32 q2, q15, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8
-vcgt.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333
-vcgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vcgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vcgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vcgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vcgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vcgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vcgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0x44882000
-vcgt.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vcgt.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vcgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vcgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vcgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vcgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000
-vcgt.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vcgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vcgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vcgt.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vcgt.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000
-vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc
-vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc5125ffc Qn (i32)0xc5126004
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0xff800000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VCGE (fp) ----
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000
-vcge.f32 q2, q15, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8
-vcge.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333
-vcge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vcge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vcge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vcge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vcge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vcge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vcge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0x44882000
-vcge.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vcge.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vcge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vcge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vcge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vcge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000
-vcge.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vcge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vcge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vcge.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vcge.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc5125ffc Qn (i32)0xc5126004
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0xff800000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000
----- VACGT (fp) ----
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x3f000000 Qn (i32)0xbf000000
-vacgt.f32 q2, q15, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8
-vacgt.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333
-vacgt.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vacgt.f32 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vacgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vacgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vacgt.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vacgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vacgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0x44882000
-vacgt.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vacgt.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vacgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vacgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vacgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vacgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000
-vacgt.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vacgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vacgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vacgt.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vacgt.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x3a800000 Qn (i32)0xba800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000
-vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x3f800000
-vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VACGE (fp) ----
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3f000000 Qn (i32)0xbf000000
-vacge.f32 q2, q15, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8
-vacge.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43677333 Qn (i32)0x43677333
-vacge.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vacge.f32 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vacge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vacge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vacge.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vacge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vacge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x473e7300 Qn (i32)0x44882000
-vacge.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vacge.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vacge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vacge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vacge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vacge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45062000 Qn (i32)0x44db0000
-vacge.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vacge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vacge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vacge.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vacge.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x3a800000 Qn (i32)0xba800000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xba800000 Qn (i32)0x3a800000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x45126004 Qn (i32)0x45125ffc
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x00000000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0xff800000
-vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x3f800000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x00000000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0x7f800000
-vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000
----- VCEQ (fp) ----
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x3f000000 Qn (i32)0xbf000000
-vceq.f32 q2, q15, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xbf07ae14 Qn (i32)0x3f051eb8
-vceq.f32 q15, q7, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43677333 Qn (i32)0x43677333
-vceq.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vceq.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vceq.f32 q10, q11, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vceq.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vceq.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vceq.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vceq.f32 q10, q11, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x473e7300 Qn (i32)0x44882000
-vceq.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vceq.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vceq.f32 q7, q1, q6 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vceq.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vceq.f32 q10, q11, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vceq.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vceq.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vceq.f32 q7, q1, q6 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vceq.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vceq.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vceq.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x3a800000 Qn (i32)0xba800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xba800000 Qn (i32)0x3a800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x45126004 Qn (i32)0x45125ffc
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc5125ffc Qn (i32)0xc5126004
-vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x47ae5e00 Qn (i32)0x47ae5e00
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000 Qn (i32)0x00000000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000 Qn (i32)0xff800000
----- VCEQ (fp) #0 ----
-vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x01000000
-vceq.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000001
-vceq.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000000
-vceq.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec
-vceq.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc1b851ec
-vceq.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000
-vceq.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000
-vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000
----- VCGT (fp) #0 ----
-vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x01000000
-vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001
-vcgt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000
-vcgt.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec
-vcgt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc1b851ec
-vcgt.f32 q10, q15, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000
-vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000
-vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000
----- VCLT (fp) #0 ----
-vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x01000000
-vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000001
-vclt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000
-vclt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec
-vclt.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc1b851ec
-vclt.f32 q10, q15, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000
-vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000000
-vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000
-vclt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000
----- VCGE (fp) #0 ----
-vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x01000000
-vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000001
-vcge.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000000
-vcge.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x41b851ec
-vcge.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xc1b851ec
-vcge.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcge.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000
-vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x7f800000
-vcge.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0xff800000
----- VCLE (fp) #0 ----
-vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x01000000
-vcle.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000001
-vcle.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000000
-vcle.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x41b851ec
-vcle.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xc1b851ec
-vcle.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7fc00000
-vcle.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000000
-vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x7f800000
-vcle.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0xff800000
----- VNEG (fp) ----
-vneg.f32 q0, q1 :: Qd 0x81000000 0x81000000 0x81000000 0x81000000 Qm (i32)0x01000000
-vneg.f32 q0, q1 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001 Qm (i32)0x00000001
-vneg.f32 q2, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000000
-vneg.f32 q2, q1 :: Qd 0xc1b851ec 0xc1b851ec 0xc1b851ec 0xc1b851ec Qm (i32)0x41b851ec
-vneg.f32 q2, q1 :: Qd 0x41b851ec 0x41b851ec 0x41b851ec 0x41b851ec Qm (i32)0xc1b851ec
-vneg.f32 q10, q15 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x00000000
-vneg.f32 q0, q1 :: Qd 0xffc00000 0xffc00000 0xffc00000 0xffc00000 Qm (i32)0x7fc00000
-vneg.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000 Qm (i32)0x00000000
-vneg.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000
-vneg.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000
----- VRSQRTS ----
-vrsqrts.f32 q0, q5, q2 :: Qd 0x44039ce4 0x44039ce4 0x44039ce4 0x44039ce4 Qm (i32)0x41b851ec Qn (i32)0xc2364659
-vrsqrts.f32 q3, q4, q5 :: Qd 0x4d5f4321 0x4d5f4321 0x4d5f4321 0x4d5f4321 Qm (i32)0xc8a9da0f Qn (i32)0x44a84000
-vrsqrts.f32 q10, q11, q2 :: Qd 0x4e850e7f 0x4e850e7f 0x4e850e7f 0x4e850e7f Qm (i32)0x473e7300 Qn (i32)0xc732da7a
-vrsqrts.f32 q9, q5, q7 :: Qd 0xce43063f 0xce43063f 0xce43063f 0xce43063f Qm (i32)0x47bb3de1 Qn (i32)0x46855200
-vrsqrts.f32 q0, q5, q2 :: Qd 0xcfa9254c 0xcfa9254c 0xcfa9254c 0xcfa9254c Qm (i32)0xc732633d Qn (i32)0xc872bcb1
-vrsqrts.f32 q3, q4, q5 :: Qd 0xc67c5a00 0xc67c5a00 0xc67c5a00 0xc67c5a00 Qm (i32)0x41c00000 Qn (i32)0x44a84000
-vrsqrts.f32 q10, q11, q2 :: Qd 0xcbca89cc 0xcbca89cc 0xcbca89cc 0xcbca89cc Qm (i32)0x473e7300 Qn (i32)0x44882000
-vrsqrts.f32 q9, q5, q7 :: Qd 0xcd32c947 0xcd32c947 0xcd32c947 0xcd32c947 Qm (i32)0x43560000 Qn (i32)0x49d5e008
-vrsqrts.f32 q0, q11, q12 :: Qd 0xce790536 0xce790536 0xce790536 0xce790536 Qm (i32)0x48add9f2 Qn (i32)0x45b75812
-vrsqrts.f32 q7, q1, q6 :: Qd 0x3fbaa704 0x3fbaa704 0x3fbaa704 0x3fbaa704 Qm (i32)0x42080079 Qn (i32)0x3b210e02
-vrsqrts.f32 q0, q1, q2 :: Qd 0xc80fe260 0xc80fe260 0xc80fe260 0xc80fe260 Qm (i32)0x452c2000 Qn (i32)0x42d60000
-vrsqrts.f32 q3, q4, q5 :: Qd 0xc913b8cb 0xc913b8cb 0xc913b8cb 0xc913b8cb Qm (i32)0x445a8000 Qn (i32)0x44ad1333
-vrsqrts.f32 q10, q11, q2 :: Qd 0xc6cf97fc 0xc6cf97fc 0xc6cf97fc 0xc6cf97fc Qm (i32)0x43f3cb23 Qn (i32)0x42da0000
-vrsqrts.f32 q9, q5, q7 :: Qd 0xc9e57ab4 0xc9e57ab4 0xc9e57ab4 0xc9e57ab4 Qm (i32)0x45062000 Qn (i32)0x44db0000
-vrsqrts.f32 q0, q11, q12 :: Qd 0xc81eedbe 0xc81eedbe 0xc81eedbe 0xc81eedbe Qm (i32)0xc2610000 Qn (i32)0xc5b4d3c3
-vrsqrts.f32 q7, q1, q6 :: Qd 0x44d03239 0x44d03239 0x44d03239 0x44d03239 Qm (i32)0x43e41fde Qn (i32)0xc0e96d19
-vrsqrts.f32 q0, q5, q2 :: Qd 0x402e3e84 0x402e3e84 0x402e3e84 0x402e3e84 Qm (i32)0x44053f2b Qn (i32)0xbb965394
-vrsqrts.f32 q10, q13, q15 :: Qd 0xc8066646 0xc8066646 0xc8066646 0xc8066646 Qm (i32)0xc3f29f73 Qn (i32)0xc40dcfae
-vrsqrts.f32 q10, q13, q15 :: Qd 0xce915379 0xce915379 0xce915379 0xce915379 Qm (i32)0x4887f70e Qn (i32)0x4608d008
-vrsqrts.f32 q0, q1, q2 :: Qd 0xdcee81fd 0xdcee81fd 0xdcee81fd 0xdcee81fd Qm (i32)0x4e511724 Qn (i32)0x4e920233
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7fc00000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x3f800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x00000000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0x7f800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7fc00000 Qn (i32)0xff800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x00000000 Qn (i32)0x7fc00000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x3f800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x00000000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0x7f800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x00000000 Qn (i32)0xff800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0x7f800000 Qn (i32)0x7fc00000
-vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x3f800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0x7f800000 Qn (i32)0x00000000
-vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0x7f800000 Qn (i32)0x7f800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0x7f800000 Qn (i32)0xff800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000 Qm (i32)0xff800000 Qn (i32)0x7fc00000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x3f800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000 Qm (i32)0xff800000 Qn (i32)0x00000000
-vrsqrts.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000 Qm (i32)0xff800000 Qn (i32)0x7f800000
-vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000 Qm (i32)0xff800000 Qn (i32)0xff800000
----- VRSQRTE (fp) ----
-vrsqrte.f32 q0, q1 :: Qd 0x3f0f0000 0x3f0f0000 0x3f0f0000 0x3f0f0000 Qm (i32)0x404ccccd
vrsqrte.f32 q0, q1 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x404ccccd
vrsqrte.f32 q10, q11 :: Qd 0x2ccb0000 0x2ccb0000 0x2ccb0000 0x2ccb0000 Qm (i32)0x64cb49b4
vrsqrte.f32 q10, q11 :: Qd 0x4c1b8000 0x4c9d0000 0x4d1c0000 0x4d9a8000 Qm (i32)0x64cb49b4
diff --git a/main/none/tests/arm/neon128.vgtest b/main/none/tests/arm/neon128.vgtest
index e742dc4..d73f24b 100644
--- a/main/none/tests/arm/neon128.vgtest
+++ b/main/none/tests/arm/neon128.vgtest
@@ -1,4 +1,2 @@
prog: neon128
vgopts: -q
-prog: neon128
-vgopts: -q
diff --git a/main/none/tests/arm/neon64.c b/main/none/tests/arm/neon64.c
index 99dccdc..8d6f6cd 100644
--- a/main/none/tests/arm/neon64.c
+++ b/main/none/tests/arm/neon64.c
@@ -4535,3637 +4535,3 @@
return 0;
}
-
-/* How to compile:
-
- gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \
- -marm -o neon64-a neon64.c
-
- or
-
- gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \
- -mthumb -o neon64-t neon64.c
-
-*/
-
-#include <stdio.h>
-#include <string.h>
-#include <math.h>
-
-#ifndef __thumb__
-// ARM
-#define MOVE_to_FPSCR_from_R4 \
- ".word 0xEEE14A10 @ vmsr FPSCR, r4\n\t"
-#define MOVE_to_R4_from_FPSCR \
- ".word 0xEEF14A10 @ vmrs r4, FPSCR\n\t"
-#endif
-
-#ifdef __thumb__
-// Thumb
-#define MOVE_to_FPSCR_from_R4 \
- ".word 0x4A10EEE1 @ vmsr FPSCR, r4\n\t"
-#define MOVE_to_R4_from_FPSCR \
- ".word 0x4A10EEF1 @ vmrs r4, FPSCR\n\t"
-#endif
-
-static inline unsigned int f2u(float x) {
- union {
- float f;
- unsigned int u;
- } cvt;
- cvt.f = x;
- return cvt.u;
-}
-
-/* test macros to generate and output the result of a single instruction */
-
-const unsigned int mem[] = {
- 0x121f1e1f, 0x131b1a1b, 0x141c1f1c, 0x151d191d,
- 0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a,
- 0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a,
- 0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
-};
-
-#define TESTINSN_imm(instruction, QD, imm) \
-{ \
- unsigned int out[2]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- instruction ", #" #imm "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out) \
- : #QD, "memory" \
- ); \
- printf("%s, #" #imm " :: Qd 0x%08x 0x%08x\n", \
- instruction, out[1], out[0]); \
-}
-
-#define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \
-{ \
- unsigned int out[2]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval) \
- : #QD, #QM, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x\n", \
- instruction, out[1], out[0], QMval); \
-}
-
-#define TESTINSN_un_q(instruction, QD, QM, QMtype, QMval) \
-{ \
- unsigned int out[2]; \
- unsigned int fpscr; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "mov r4, #0\n\t" \
- MOVE_to_FPSCR_from_R4 \
- "vdup." #QMtype " " #QM ", %2\n\t" \
- instruction "\n\t" \
- "vstmia %1, {" #QD "}\n\t" \
- MOVE_to_R4_from_FPSCR \
- "mov %0, r4" \
- : "=r" (fpscr) \
- : "r" (out), "r" (QMval) \
- : #QD, #QM, "memory", "r4" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x fpscr %08x\n", \
- instruction, out[1], out[0], QMval, fpscr); \
-}
-
-#define TESTINSN_core_to_scalar(instruction, QD, QM, QMval) \
-{ \
- unsigned int out[2]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "mov " #QM ", %1\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval) \
- : #QD, #QM, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x Qm 0x%08x\n", \
- instruction, out[1], out[0], QMval); \
-}
-
-#define TESTINSN_scalar_to_core(instruction, QD, QM, QMtype, QMval) \
-{ \
- unsigned int out[2]; \
-\
- __asm__ volatile( \
- "mov " #QD ", #0x55" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- instruction "\n\t" \
- "str " #QD ", [%0]\n\t" \
- : \
- : "r" (out), "r" (QMval) \
- : #QD, #QM, "memory" \
- ); \
- printf("%s :: Rd 0x%08x Qm (" #QMtype ")0x%08x\n", \
- instruction, out[0], QMval); \
-}
-
-#define TESTINSN_VLDn(instruction, QD1, QD2, QD3, QD4) \
-{ \
- unsigned int out[8]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD1 ", #0x55" "\n\t" \
- "vmov.i8 " #QD2 ", #0x55" "\n\t" \
- "vmov.i8 " #QD3 ", #0x55" "\n\t" \
- "vmov.i8 " #QD4 ", #0x55" "\n\t" \
- instruction ", [%1]\n\t" \
- "mov r4, %0\n\t" \
- "vstmia %0!, {" #QD1 "}\n\t" \
- "vstmia %0!, {" #QD2 "}\n\t" \
- "vstmia %0!, {" #QD3 "}\n\t" \
- "vstmia %0!, {" #QD4 "}\n\t" \
- "mov %0, r4\n\t" \
- : \
- : "r" (out), "r" (mem) \
- : #QD1, #QD2, #QD3, #QD4, "memory", "r4" \
- ); \
- printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\
- "0x%08x 0x%08x 0x%08x 0x%08x\n", \
- instruction, out[0], out[1], out[2], out[3], out[4],\
- out[5], out[6], out[7]); \
-}
-
-#define TESTINSN_VSTn(instruction, QD1, QD2, QD3, QD4) \
-{ \
- unsigned int out[8]; \
-\
- memset(out, 0x55, 8 * (sizeof(unsigned int)));\
- __asm__ volatile( \
- "mov r4, %1\n\t" \
- "vldmia %1!, {" #QD1 "}\n\t" \
- "vldmia %1!, {" #QD2 "}\n\t" \
- "vldmia %1!, {" #QD3 "}\n\t" \
- "vldmia %1!, {" #QD4 "}\n\t" \
- "mov %1, r4\n\t" \
- instruction ", [%0]\n\t" \
- : \
- : "r" (out), "r" (mem) \
- : #QD1, #QD2, #QD3, #QD4, "memory", "r4" \
- ); \
- printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\
- "0x%08x 0x%08x 0x%08x 0x%08x\n", \
- instruction, out[0], out[1], out[2], out[3], out[4],\
- out[5], out[6], out[7]); \
-}
-
-#define TESTINSN_bin(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out[2]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- "vdup." #QNtype " " #QN ", %2\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval), "r" (QNval) \
- : #QD, #QM, #QN, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn (" #QNtype ")0x%08x\n", \
- instruction, out[1], out[0], QMval, QNval); \
-}
-
-#define TESTINSN_bin_f(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out[2]; \
-\
- __asm__ volatile( \
- "vdup.i32 " #QD ", %3\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- "vdup." #QNtype " " #QN ", %2\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval), "r" (QNval), "r"(0x3f800000) \
- : #QD, #QM, #QN, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn (" #QNtype ")0x%08x\n", \
- instruction, out[1], out[0], QMval, QNval); \
-}
-
-#define TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
- QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN4, QN4type, QN4val) \
-{ \
- unsigned int out[2]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- "vdup." #QN1type " " #QN1 ", %2\n\t" \
- "vdup." #QN2type " " #QN2 ", %3\n\t" \
- "vdup." #QN3type " " #QN3 ", %4\n\t" \
- "vdup." #QN4type " " #QN4 ", %5\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval), "r" (QN1val), "r" (QN2val), "r" (QN3val), \
- "r" (QN4val) \
- : #QD, #QM, #QN1, #QN2, #QN3, #QN4, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn1 (" #QN1type ")0x%08x" \
- " Qn2 (" #QN2type ")0x%08x" \
- " Qn3 (" #QN3type ")0x%08x" \
- " Qn4 (" #QN4type ")0x%08x\n", \
- instruction, out[1], out[0], QMval, QN1val, QN2val, QN3val, QN4val); \
-}
-#define TESTINSN_tbl_1(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val) \
- TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
- QN1, QN1type, QN1val, QN1, QN1type, QN1val, QN1, QN1type, QN1val)
-#define TESTINSN_tbl_2(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
- QN2, QN2type, QN2val) \
- TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
- QN2, QN2type, QN2val, QN1, QN1type, QN1val, QN2, QN2type, QN2val)
-#define TESTINSN_tbl_3(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
- QN2, QN2type, QN2val, QN3, QN3type, QN3val) \
- TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
- QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN2, QN2type, QN2val)
-#define TESTINSN_tbl_4(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
- QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN4, QN4type, QN4val) \
- TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
- QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN4, QN4type, QN4val)
-
-#define TESTINSN_bin_q(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out[2]; \
- unsigned int fpscr; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "mov r4, #0\n\t" \
- MOVE_to_FPSCR_from_R4 \
- "vdup." #QMtype " " #QM ", %2\n\t" \
- "vdup." #QNtype " " #QN ", %3\n\t" \
- instruction "\n\t" \
- "vstmia %1, {" #QD "}\n\t" \
- MOVE_to_R4_from_FPSCR \
- "mov %0, r4" \
- : "=r" (fpscr) \
- : "r" (out), "r" (QMval), "r" (QNval) \
- : #QD, #QM, #QN, "memory", "r4" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn (" #QNtype ")0x%08x fpscr: %08x\n", \
- instruction, out[1], out[0], QMval, QNval, fpscr); \
-}
-
-#define TESTINSN_dual(instruction, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out1[2]; \
- unsigned int out2[2]; \
-\
- __asm__ volatile( \
- "vdup." #QMtype " " #QM ", %2\n\t" \
- "vdup." #QNtype " " #QN ", %3\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QM "}\n\t" \
- "vstmia %1, {" #QN "}\n\t" \
- : \
- : "r" (out1), "r" (out2), "r" (QMval), "r" (QNval) \
- : #QM, #QN, "memory" \
- ); \
- printf("%s :: Qm 0x%08x 0x%08x Qn 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn (" #QNtype ")0x%08x\n", \
- instruction, out1[1], out1[0], out2[1], out2[0], QMval, QNval); \
-}
-
-// Ditto TESTING_bin(), but in QD all zeros
-#define TESTINSN_bin_0s(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
-{ \
- unsigned int out[2]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x00" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- "vdup." #QNtype " " #QN ", %2\n\t" \
- instruction "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval), "r" (QNval) \
- : #QD, #QM, #QN, "memory" \
- ); \
- printf("%s :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x" \
- " Qn (" #QNtype ")0x%08x\n", \
- instruction, out[1], out[0], QMval, QNval); \
-}
-
-#if 0
-#define TESTINSN_2reg_shift(instruction, QD, QM, QMtype, QMval, imm) \
-{ \
- unsigned int out[2]; \
-\
- __asm__ volatile( \
- "vmov.i8 " #QD ", #0x55" "\n\t" \
- "vdup." #QMtype " " #QM ", %1\n\t" \
- instruction ", #" #imm "\n\t" \
- "vstmia %0, {" #QD "}\n\t" \
- : \
- : "r" (out), "r" (QMval) \
- : #QD, #QM, "memory" \
- ); \
- printf("%s, #" #imm " :: Qd 0x%08x 0x%08x Qm (" #QMtype ")0x%08x", \
- instruction, out[1], out[0], QMval); \
-}
-#endif
-
-int main(int argc, char **argv)
-{
- printf("----- VMOV (immediate) -----\n");
- TESTINSN_imm("vmov.i32 d0", d0, 0x7);
- TESTINSN_imm("vmov.i16 d1", d1, 0x7);
- TESTINSN_imm("vmov.i8 d2", d2, 0x7);
- TESTINSN_imm("vmov.i32 d5", d5, 0x700);
- TESTINSN_imm("vmov.i16 d7", d7, 0x700);
- TESTINSN_imm("vmov.i32 d10", d10, 0x70000);
- TESTINSN_imm("vmov.i32 d12", d12, 0x7000000);
- TESTINSN_imm("vmov.i32 d13", d13, 0x7FF);
- TESTINSN_imm("vmov.i32 d14", d14, 0x7FFFF);
- TESTINSN_imm("vmov.i64 d15", d15, 0xFF0000FF00FFFF00);
-
- printf("----- VMVN (immediate) -----\n");
- TESTINSN_imm("vmvn.i32 d0", d0, 0x7);
- TESTINSN_imm("vmvn.i16 d1", d1, 0x7);
- TESTINSN_imm("vmvn.i8 d2", d2, 0x7);
- TESTINSN_imm("vmvn.i32 d5", d5, 0x700);
- TESTINSN_imm("vmvn.i16 d7", d7, 0x700);
- TESTINSN_imm("vmvn.i32 d10", d10, 0x70000);
- TESTINSN_imm("vmvn.i32 d13", d13, 0x7000000);
- TESTINSN_imm("vmvn.i32 d11", d11, 0x7FF);
- TESTINSN_imm("vmvn.i32 d14", d14, 0x7FFFF);
- TESTINSN_imm("vmvn.i64 d15", d15, 0xFF0000FF00FFFF00);
-
- printf("----- VORR (immediate) -----\n");
- TESTINSN_imm("vorr.i32 d0", d0, 0x7);
- TESTINSN_imm("vorr.i16 d2", d2, 0x7);
- TESTINSN_imm("vorr.i32 d8", d8, 0x700);
- TESTINSN_imm("vorr.i16 d6", d6, 0x700);
- TESTINSN_imm("vorr.i32 d14", d14, 0x70000);
- TESTINSN_imm("vorr.i32 d15", d15, 0x7000000);
-
- printf("----- VBIC (immediate) -----\n");
- TESTINSN_imm("vbic.i32 d0", d0, 0x7);
- TESTINSN_imm("vbic.i16 d3", d3, 0x7);
- TESTINSN_imm("vbic.i32 d5", d5, 0x700);
- TESTINSN_imm("vbic.i16 d8", d8, 0x700);
- TESTINSN_imm("vbic.i32 d10", d10, 0x70000);
- TESTINSN_imm("vbic.i32 d15", d15, 0x7000000);
-
- printf("---- VMVN (register) ----\n");
- TESTINSN_un("vmvn d0, d1", d0, d1, i32, 24);
- TESTINSN_un("vmvn d10, d15", d10, d15, i32, 24);
- TESTINSN_un("vmvn d0, d14", d0, d14, i32, 24);
-
- printf("---- VMOV (register) ----\n");
- TESTINSN_un("vmov d0, d1", d0, d1, i32, 24);
- TESTINSN_un("vmov d10, d15", d10, d15, i32, 24);
- TESTINSN_un("vmov d0, d14", d0, d14, i32, 24);
-
- printf("---- VDUP (ARM core register) (tested indirectly) ----\n");
- TESTINSN_un("vmov d0, d1", d0, d1, i8, 7);
- TESTINSN_un("vmov d10, d11", d10, d11, i16, 7);
- TESTINSN_un("vmov d0, d15", d0, d15, i32, 7);
-
- printf("---- VADD ----\n");
- TESTINSN_bin("vadd.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vadd.i64 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vadd.i32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vadd.i16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vadd.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vadd.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vadd.i16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vadd.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vadd.i64 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vadd.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vadd.i64 d13, d14, d15", d13, d14, i32, 140, d15, i32, 120);
-
- printf("---- VSUB ----\n");
- TESTINSN_bin("vsub.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vsub.i64 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vsub.i32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vsub.i16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vsub.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vsub.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vsub.i16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vsub.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vsub.i64 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vsub.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vsub.i64 d13, d14, d15", d13, d14, i32, 140, d15, i32, 120);
-
- printf("---- VAND ----\n");
- TESTINSN_bin("vand d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
- TESTINSN_bin("vand d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
- TESTINSN_bin("vand d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
- TESTINSN_bin("vand d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
-
- printf("---- VBIC ----\n");
- TESTINSN_bin("vbic d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
- TESTINSN_bin("vbic d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
- TESTINSN_bin("vbic d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
- TESTINSN_bin("vbic d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
-
- printf("---- VORR ----\n");
- TESTINSN_bin("vorr d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
- TESTINSN_bin("vorr d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
- TESTINSN_bin("vorr d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
- TESTINSN_bin("vorr d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
-
- printf("---- VORN ----\n");
- TESTINSN_bin("vorn d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
- TESTINSN_bin("vorn d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
- TESTINSN_bin("vorn d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
- TESTINSN_bin("vorn d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
-
- printf("---- VEOR ----\n");
- TESTINSN_bin("veor d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
- TESTINSN_bin("veor d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
- TESTINSN_bin("veor d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
- TESTINSN_bin("veor d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
- TESTINSN_bin("veor d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
- TESTINSN_bin("veor d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
- TESTINSN_bin("veor d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
- TESTINSN_bin("veor d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
-
- printf("---- VBSL ----\n");
- TESTINSN_bin("vbsl d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
- TESTINSN_bin("vbsl d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
- TESTINSN_bin("vbsl d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
- TESTINSN_bin("vbsl d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
- TESTINSN_bin("vbsl d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
- TESTINSN_bin("vbsl d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
- TESTINSN_bin("vbsl d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
- TESTINSN_bin("vbsl d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
-
- printf("---- VBIT ----\n");
- TESTINSN_bin("vbit d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
- TESTINSN_bin("vbit d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
- TESTINSN_bin("vbit d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
- TESTINSN_bin("vbit d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
- TESTINSN_bin("vbit d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
- TESTINSN_bin("vbit d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
- TESTINSN_bin("vbit d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
- TESTINSN_bin("vbit d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
-
- printf("---- VBIF ----\n");
- TESTINSN_bin("vbif d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
- TESTINSN_bin("vbif d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
- TESTINSN_bin("vbif d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
- TESTINSN_bin("vbif d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
- TESTINSN_bin("vbif d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
- TESTINSN_bin("vbif d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
- TESTINSN_bin("vbif d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
- TESTINSN_bin("vbif d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
-
- printf("---- VEXT ----\n");
- TESTINSN_bin("vext.8 d0, d1, d2, #0", d0, d1, i8, 0x77, d2, i8, 0xff);
- TESTINSN_bin("vext.8 d0, d1, d2, #1", d0, d1, i8, 0x77, d2, i8, 0xff);
- TESTINSN_bin("vext.8 d0, d1, d2, #7", d0, d1, i8, 0x77, d2, i8, 0xff);
- TESTINSN_bin("vext.8 d0, d1, d2, #6", d0, d1, i8, 0x77, d2, i8, 0xff);
- TESTINSN_bin("vext.8 d10, d11, d12, #4", d10, d11, i8, 0x77, d12, i8, 0xff);
- TESTINSN_bin("vext.8 d0, d5, d15, #5", d0, d5, i8, 0x77, d15, i8, 0xff);
-
- printf("---- VHADD ----\n");
- TESTINSN_bin("vhadd.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vhadd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhadd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhadd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhadd.s8 d0, d1, d2", d0, d1, i8, 141, d2, i8, 121);
- TESTINSN_bin("vhadd.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vhadd.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vhadd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhadd.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhadd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhadd.u8 d0, d1, d2", d0, d1, i8, 141, d2, i8, 121);
- TESTINSN_bin("vhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhadd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VHSUB ----\n");
- TESTINSN_bin("vhsub.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vhsub.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhsub.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhsub.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhsub.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vhsub.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vhsub.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhsub.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhsub.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vhsub.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vhsub.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VQADD ----\n");
- TESTINSN_bin_q("vqadd.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin_q("vqadd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqadd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqadd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqadd.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin_q("vqadd.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin_q("vqadd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqadd.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqadd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqadd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VQSUB ----\n");
- TESTINSN_bin_q("vqsub.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin_q("vqsub.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqsub.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqsub.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqsub.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin_q("vqsub.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin_q("vqsub.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqsub.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqsub.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin_q("vqsub.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqsub.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VRHADD ----\n");
- TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vrhadd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vrhadd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VCGT ----\n");
- TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcgt.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcgt.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
- TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
- TESTINSN_bin("vcgt.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
- TESTINSN_bin("vcgt.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 3, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 2, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcgt.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VCGE ----\n");
- TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcge.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcge.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
- TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
- TESTINSN_bin("vcge.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
- TESTINSN_bin("vcge.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 3, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 2, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vcge.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VSHL (register) ----\n");
- TESTINSN_bin("vshl.s8 d0, d1, d2", d0, d1, i32, 24, d2, i32, 1);
- TESTINSN_bin("vshl.s8 d8, d1, d12", d8, d1, i32, 24, d12, i32, 8);
- TESTINSN_bin("vshl.s8 d10, d31, d7", d10, d31, i32, 24, d7, i32, 4);
- TESTINSN_bin("vshl.s16 d3, d8, d11", d3, d8, i32, 14, d11, i32, 2);
- TESTINSN_bin("vshl.s16 d5, d12, d14", d5, d12, i32, (1 << 30), d14, i32, 1);
- TESTINSN_bin("vshl.s16 d15, d2, d1", d15, d2, i32, (1 << 30), d1, i32, 11);
- TESTINSN_bin("vshl.s32 d9, d12, d19", d9, d12, i32, (1 << 31) + 2, d19, i32, 2);
- TESTINSN_bin("vshl.s32 d11, d22, d0", d11, d22, i32, -1, d0, i32, 12);
- TESTINSN_bin("vshl.s32 d5, d2, d3", d5, d2, i32, (1 << 30), d3, i32, 21);
- TESTINSN_bin("vshl.s64 d15, d12, d4", d15, d12, i32, 5, d4, i32, 20);
- TESTINSN_bin("vshl.s64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 4);
- TESTINSN_bin("vshl.s64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 30);
- TESTINSN_bin("vshl.s64 d15, d2, d4", d15, d2, i32, 0xffabcd59, d4, i32, 0xabcdefab);
- TESTINSN_bin("vshl.s64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 0x400bb5);
- TESTINSN_bin("vshl.s64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 0x30abcff);
- TESTINSN_bin("vshl.u8 d0, d1, d2", d0, d1, i32, 24, d2, i32, 1);
- TESTINSN_bin("vshl.u8 d8, d1, d12", d8, d1, i32, 24, d12, i32, 8);
- TESTINSN_bin("vshl.u8 d10, d11, d7", d10, d11, i32, 24, d7, i32, 4);
- TESTINSN_bin("vshl.u16 d3, d8, d11", d3, d8, i32, 14, d11, i32, 2);
- TESTINSN_bin("vshl.u16 d5, d12, d14", d5, d12, i32, (1 << 30), d14, i32, 1);
- TESTINSN_bin("vshl.u16 d15, d2, d1", d15, d2, i32, (1 << 30), d1, i32, 11);
- TESTINSN_bin("vshl.u32 d9, d12, d15", d9, d12, i32, (1 << 31) + 2, d15, i32, 2);
- TESTINSN_bin("vshl.u32 d11, d2, d0", d11, d2, i32, -1, d0, i32, 12);
- TESTINSN_bin("vshl.u32 d5, d2, d3", d5, d2, i32, (1 << 30), d3, i32, 21);
- TESTINSN_bin("vshl.u64 d15, d12, d4", d15, d12, i32, 5, d4, i32, 20);
- TESTINSN_bin("vshl.u64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 4);
- TESTINSN_bin("vshl.u64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 30);
- TESTINSN_bin("vshl.u64 d15, d2, d4", d15, d2, i32, 0xffabcd59, d4, i32, 0xabcdefab);
- TESTINSN_bin("vshl.u64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 0x400bb5);
- TESTINSN_bin("vshl.u64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 0x30abcff);
-
- printf("---- VQSHL (register) ----\n");
- TESTINSN_bin_q("vqshl.s64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
- TESTINSN_bin_q("vqshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
- TESTINSN_bin_q("vqshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
- TESTINSN_bin_q("vqshl.s64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
- TESTINSN_bin_q("vqshl.s64 d13, d14, d31", d13, d14, i32, -17, d31, i32, -26);
- TESTINSN_bin_q("vqshl.s64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
- TESTINSN_bin_q("vqshl.s32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
- TESTINSN_bin_q("vqshl.s32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
- TESTINSN_bin_q("vqshl.s32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
- TESTINSN_bin_q("vqshl.s32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
- TESTINSN_bin_q("vqshl.s32 d9, d30, d11", d9, d30, i32, (1 << 31) + 8, d11, i32, -1);
- TESTINSN_bin_q("vqshl.s32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
- TESTINSN_bin_q("vqshl.s16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
- TESTINSN_bin_q("vqshl.s16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
- TESTINSN_bin_q("vqshl.s16 d0, d11, d2", d0, d11, i32, (1 << 31) + 256, d2, i32, -1);
- TESTINSN_bin_q("vqshl.s16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
- TESTINSN_bin_q("vqshl.s16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
- TESTINSN_bin_q("vqshl.s16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
- TESTINSN_bin_q("vqshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
- TESTINSN_bin_q("vqshl.s8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
- TESTINSN_bin_q("vqshl.s8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
- TESTINSN_bin_q("vqshl.s8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
- TESTINSN_bin_q("vqshl.s8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
- TESTINSN_bin_q("vqshl.s8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin_q("vqshl.u64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
- TESTINSN_bin_q("vqshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
- TESTINSN_bin_q("vqshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
- TESTINSN_bin_q("vqshl.u64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
- TESTINSN_bin_q("vqshl.u64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
- TESTINSN_bin_q("vqshl.u64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
- TESTINSN_bin_q("vqshl.u32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
- TESTINSN_bin_q("vqshl.u32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
- TESTINSN_bin_q("vqshl.u32 d12, d31, d13", d12, d31, i32, -120, d13, i32, -9);
- TESTINSN_bin_q("vqshl.u32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
- TESTINSN_bin_q("vqshl.u32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
- TESTINSN_bin_q("vqshl.u32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
- TESTINSN_bin_q("vqshl.u16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
- TESTINSN_bin_q("vqshl.u16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
- TESTINSN_bin_q("vqshl.u16 d0, d11, d2", d0, d11, i32, (1 << 31) + 256, d2, i32, -1);
- TESTINSN_bin_q("vqshl.u16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
- TESTINSN_bin_q("vqshl.u16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
- TESTINSN_bin_q("vqshl.u16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
- TESTINSN_bin_q("vqshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
- TESTINSN_bin_q("vqshl.u8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
- TESTINSN_bin_q("vqshl.u8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
- TESTINSN_bin_q("vqshl.u8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
- TESTINSN_bin_q("vqshl.u8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
- TESTINSN_bin_q("vqshl.u8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VQSHL / VQSHLU (immediate) ----\n");
- TESTINSN_un_q("vqshl.s64 d0, d1, #1", d0, d1, i32, 1);
- TESTINSN_un_q("vqshl.s64 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshl.s64 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshl.s64 d5, d4, #63", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s64 d5, d4, #60", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s64 d5, d4, #59", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s64 d5, d4, #58", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s64 d5, d4, #17", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s64 d5, d4, #63", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.s64 d5, d4, #60", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.s64 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.s32 d10, d11, #1", d10, d11, i32, 1);
- TESTINSN_un_q("vqshl.s32 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshl.s32 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshl.s32 d5, d4, #31", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s32 d5, d4, #28", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s32 d5, d4, #27", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s32 d5, d4, #26", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s32 d5, d4, #17", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s32 d5, d4, #31", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.s32 d5, d4, #29", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.s32 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.s16 d9, d8, #1", d9, d8, i32, 1);
- TESTINSN_un_q("vqshl.s16 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshl.s16 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshl.s16 d9, d8, #15", d9, d8, i32, 16);
- TESTINSN_un_q("vqshl.s16 d5, d4, #12", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s16 d5, d4, #11", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s16 d5, d4, #10", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s16 d5, d4, #4", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s16 d5, d4, #15", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.s16 d5, d4, #12", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.s16 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.s8 d0, d1, #1", d0, d1, i32, 1);
- TESTINSN_un_q("vqshl.s8 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshl.s8 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshl.s8 d5, d4, #7", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s8 d25, d4, #4", d25, d4, i32, 16);
- TESTINSN_un_q("vqshl.s8 d5, d4, #3", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s8 d5, d4, #2", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s8 d5, d4, #1", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.s8 d5, d4, #7", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.s8 d5, d4, #5", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.s8 d5, d4, #2", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.u64 d0, d1, #1", d0, d1, i32, 1);
- TESTINSN_un_q("vqshl.u64 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshl.u64 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshl.u64 d5, d4, #63", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u64 d5, d4, #60", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u64 d5, d4, #59", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u64 d5, d4, #58", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u64 d5, d4, #17", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u64 d5, d4, #63", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.u64 d5, d4, #60", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.u64 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.u32 d10, d11, #1", d10, d11, i32, 1);
- TESTINSN_un_q("vqshl.u32 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshl.u32 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshl.u32 d5, d4, #31", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u32 d5, d4, #28", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u32 d5, d4, #27", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u32 d5, d4, #26", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u32 d5, d4, #17", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u32 d5, d4, #31", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.u32 d5, d4, #29", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.u32 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.u16 d9, d8, #1", d9, d8, i32, 1);
- TESTINSN_un_q("vqshl.u16 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshl.u16 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshl.u16 d9, d8, #15", d9, d8, i32, 16);
- TESTINSN_un_q("vqshl.u16 d5, d4, #12", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u16 d5, d4, #11", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u16 d5, d4, #10", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u16 d5, d4, #4", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u16 d5, d4, #15", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.u16 d5, d4, #12", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.u16 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshl.u8 d0, d1, #1", d0, d1, i32, 1);
- TESTINSN_un_q("vqshl.u8 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshl.u8 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshl.u8 d5, d4, #7", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u8 d5, d4, #4", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u8 d5, d4, #3", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u8 d5, d4, #2", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u8 d5, d4, #1", d5, d4, i32, 16);
- TESTINSN_un_q("vqshl.u8 d5, d4, #7", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.u8 d5, d4, #5", d5, d4, i32, -1);
- TESTINSN_un_q("vqshl.u8 d5, d4, #2", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshlu.s64 d0, d1, #1", d0, d1, i32, 1);
- TESTINSN_un_q("vqshlu.s64 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshlu.s64 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshlu.s64 d5, d4, #63", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 d5, d4, #60", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 d5, d4, #59", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 d5, d4, #58", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 d5, d4, #17", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s64 d5, d4, #63", d5, d4, i32, -1);
- TESTINSN_un_q("vqshlu.s64 d5, d4, #60", d5, d4, i32, -1);
- TESTINSN_un_q("vqshlu.s64 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshlu.s32 d10, d11, #1", d10, d11, i32, 1);
- TESTINSN_un_q("vqshlu.s32 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshlu.s32 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshlu.s32 d5, d4, #31", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s32 d25, d24, #28", d25, d24, i32, 16);
- TESTINSN_un_q("vqshlu.s32 d5, d4, #27", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s32 d5, d4, #26", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s32 d5, d4, #17", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s32 d5, d24, #31", d5, d24, i32, -1);
- TESTINSN_un_q("vqshlu.s32 d5, d4, #29", d5, d4, i32, -1);
- TESTINSN_un_q("vqshlu.s32 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshlu.s16 d9, d8, #1", d9, d8, i32, 1);
- TESTINSN_un_q("vqshlu.s16 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshlu.s16 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshlu.s16 d9, d8, #15", d9, d8, i32, 16);
- TESTINSN_un_q("vqshlu.s16 d5, d4, #12", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s16 d5, d4, #11", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s16 d5, d4, #10", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s16 d5, d4, #4", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s16 d15, d14, #15", d15, d14, i32, -1);
- TESTINSN_un_q("vqshlu.s16 d5, d4, #12", d5, d4, i32, -1);
- TESTINSN_un_q("vqshlu.s16 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
- TESTINSN_un_q("vqshlu.s8 d0, d1, #1", d0, d1, i32, 1);
- TESTINSN_un_q("vqshlu.s8 d31, d30, #1", d31, d30, i32, -127);
- TESTINSN_un_q("vqshlu.s8 d5, d4, #0", d5, d4, i32, -127);
- TESTINSN_un_q("vqshlu.s8 d5, d4, #7", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 d5, d4, #4", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 d5, d4, #3", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 d5, d4, #2", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 d5, d4, #1", d5, d4, i32, 16);
- TESTINSN_un_q("vqshlu.s8 d5, d4, #7", d5, d4, i32, -1);
- TESTINSN_un_q("vqshlu.s8 d5, d4, #5", d5, d4, i32, -1);
- TESTINSN_un_q("vqshlu.s8 d5, d4, #2", d5, d4, i32, (1 << 31) + 2);
-
- printf("---- VQRSHL (register) ----\n");
- TESTINSN_bin_q("vqrshl.s64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
- TESTINSN_bin_q("vqrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
- TESTINSN_bin_q("vqrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
- TESTINSN_bin_q("vqrshl.s64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
- TESTINSN_bin_q("vqrshl.s64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
- TESTINSN_bin_q("vqrshl.s64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
- TESTINSN_bin_q("vqrshl.s32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
- TESTINSN_bin_q("vqrshl.s32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
- TESTINSN_bin_q("vqrshl.s32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
- TESTINSN_bin_q("vqrshl.s32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
- TESTINSN_bin_q("vqrshl.s32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
- TESTINSN_bin_q("vqrshl.s16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
- TESTINSN_bin_q("vqrshl.s16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
- TESTINSN_bin_q("vqrshl.s16 d0, d31, d2", d0, d31, i32, (1 << 31) + 256, d2, i32, -1);
- TESTINSN_bin_q("vqrshl.s16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
- TESTINSN_bin_q("vqrshl.s16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
- TESTINSN_bin_q("vqrshl.s16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
- TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s32 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s32 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
- TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
- TESTINSN_bin_q("vqrshl.s32 d2, d7, d31", d2, d7, i32, -1, d31, i32, 0);
- TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
- TESTINSN_bin_q("vqrshl.s8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
- TESTINSN_bin_q("vqrshl.s8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
- TESTINSN_bin_q("vqrshl.s8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
- TESTINSN_bin_q("vqrshl.s8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
- TESTINSN_bin_q("vqrshl.s8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin_q("vqrshl.u64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
- TESTINSN_bin_q("vqrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
- TESTINSN_bin_q("vqrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
- TESTINSN_bin_q("vqrshl.u64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
- TESTINSN_bin_q("vqrshl.u64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
- TESTINSN_bin_q("vqrshl.u64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
- TESTINSN_bin_q("vqrshl.u32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
- TESTINSN_bin_q("vqrshl.u32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
- TESTINSN_bin_q("vqrshl.u32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
- TESTINSN_bin_q("vqrshl.u32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
- TESTINSN_bin_q("vqrshl.u32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.u32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
- TESTINSN_bin_q("vqrshl.u16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
- TESTINSN_bin_q("vqrshl.u16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
- TESTINSN_bin_q("vqrshl.u16 d0, d31, d2", d0, d31, i32, (1 << 31) + 256, d2, i32, -1);
- TESTINSN_bin_q("vqrshl.u16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
- TESTINSN_bin_q("vqrshl.u16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
- TESTINSN_bin_q("vqrshl.u16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
- TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
- TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.u16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.u32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.u16 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.u32 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
- TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
- TESTINSN_bin_q("vqrshl.u16 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
- TESTINSN_bin_q("vqrshl.u32 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
- TESTINSN_bin_q("vqrshl.u8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
- TESTINSN_bin_q("vqrshl.u8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
- TESTINSN_bin_q("vqrshl.u8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
- TESTINSN_bin_q("vqrshl.u8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
- TESTINSN_bin_q("vqrshl.u8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VRSHL (register) ----\n");
- TESTINSN_bin("vrshl.s64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
- TESTINSN_bin("vrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
- TESTINSN_bin("vrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
- TESTINSN_bin("vrshl.s64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
- TESTINSN_bin("vrshl.s64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
- TESTINSN_bin("vrshl.s64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
- TESTINSN_bin("vrshl.s32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
- TESTINSN_bin("vrshl.s32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
- TESTINSN_bin("vrshl.s32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
- TESTINSN_bin("vrshl.s32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
- TESTINSN_bin("vrshl.s32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
- TESTINSN_bin("vrshl.s32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
- TESTINSN_bin("vrshl.s16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
- TESTINSN_bin("vrshl.s16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
- TESTINSN_bin("vrshl.s16 d0, d11, d2", d0, d11, i32, (1 << 31) + 256, d2, i32, -1);
- TESTINSN_bin("vrshl.s16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
- TESTINSN_bin("vrshl.s16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
- TESTINSN_bin("vrshl.s16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
- TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin("vrshl.s16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin("vrshl.s32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin("vrshl.s8 d2, d7, d31", d2, d7, i32, -1, d31, i32, -1);
- TESTINSN_bin("vrshl.s16 d2, d7, d31", d2, d7, i32, -1, d31, i32, -1);
- TESTINSN_bin("vrshl.s32 d2, d7, d31", d2, d7, i32, -1, d31, i32, -1);
- TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
- TESTINSN_bin("vrshl.s16 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
- TESTINSN_bin("vrshl.s32 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
- TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
- TESTINSN_bin("vrshl.s16 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
- TESTINSN_bin("vrshl.s32 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
- TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
- TESTINSN_bin("vrshl.s8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
- TESTINSN_bin("vrshl.s8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
- TESTINSN_bin("vrshl.s8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
- TESTINSN_bin("vrshl.s8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
- TESTINSN_bin("vrshl.s8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vrshl.u64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
- TESTINSN_bin("vrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
- TESTINSN_bin("vrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
- TESTINSN_bin("vrshl.u64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
- TESTINSN_bin("vrshl.u64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
- TESTINSN_bin("vrshl.u64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
- TESTINSN_bin("vrshl.u32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
- TESTINSN_bin("vrshl.u32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
- TESTINSN_bin("vrshl.u32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
- TESTINSN_bin("vrshl.u32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
- TESTINSN_bin("vrshl.u32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
- TESTINSN_bin("vrshl.u32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
- TESTINSN_bin("vrshl.u16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
- TESTINSN_bin("vrshl.u16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
- TESTINSN_bin("vrshl.u16 d0, d31, d2", d0, d31, i32, (1 << 31) + 256, d2, i32, -1);
- TESTINSN_bin("vrshl.u16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
- TESTINSN_bin("vrshl.u16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
- TESTINSN_bin("vrshl.u16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
- TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
- TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
- TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin("vrshl.u16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin("vrshl.u32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
- TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
- TESTINSN_bin("vrshl.u16 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
- TESTINSN_bin("vrshl.u32 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
- TESTINSN_bin("vrshl.u8 d2, d7, d31", d2, d7, i32, -2, d31, i32, -1);
- TESTINSN_bin("vrshl.u16 d2, d7, d31", d2, d7, i32, -2, d31, i32, -1);
- TESTINSN_bin("vrshl.u32 d2, d7, d31", d2, d7, i32, -2, d31, i32, -1);
- TESTINSN_bin("vrshl.u8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
- TESTINSN_bin("vrshl.u8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
- TESTINSN_bin("vrshl.u8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
- TESTINSN_bin("vrshl.u8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
- TESTINSN_bin("vrshl.u8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VMAX (integer) ----\n");
- TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121);
- TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vmax.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120);
- TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmax.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VMIN (integer) ----\n");
- TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121);
- TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vmin.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120);
- TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vmin.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VABD ----\n");
- TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, -120);
- TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200);
- TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, -140, d2, i32, 120);
- TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vabd.u8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200);
- TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vabd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VABA ----\n");
- TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vaba.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200);
- TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vaba.u8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200);
- TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vaba.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VTST ----\n");
- TESTINSN_bin("vtst.32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vtst.32 d3, d4, d5", d3, d4, i32, 140, d5, i32, 120);
- TESTINSN_bin("vtst.16 d6, d7, d8", d6, d7, i32, 120, d8, i32, 120);
- TESTINSN_bin("vtst.8 d9, d10, d12", d9, d10, i32, 140, d12, i32, 120);
- TESTINSN_bin("vtst.8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vtst.16 d0, d1, d2", d0, d1, i32, (1 << 14) + 1, d2, i32, (1 << 14) + 1);
- TESTINSN_bin("vtst.32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vtst.8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, 2);
- TESTINSN_bin("vtst.16 d0, d1, d2", d0, d1, i32, (1 << 14) + 1, d2, i32, (1 << 14) + 1);
- TESTINSN_bin("vtst.32 d0, d1, d2", d0, d1, i32, 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vtst.32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VCEQ ----\n");
- TESTINSN_bin("vceq.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vceq.i32 d3, d4, d5", d3, d4, i32, 140, d5, i32, 120);
- TESTINSN_bin("vceq.i16 d6, d7, d8", d6, d7, i32, 120, d8, i32, 120);
- TESTINSN_bin("vceq.i8 d9, d10, d12", d9, d10, i32, 140, d12, i32, 120);
- TESTINSN_bin("vceq.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vceq.i16 d0, d1, d2", d0, d1, i32, (1 << 14) + 1, d2, i32, (1 << 14) + 1);
- TESTINSN_bin("vceq.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vceq.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, 2);
- TESTINSN_bin("vceq.i16 d0, d1, d2", d0, d1, i32, 1, d2, i32, (1 << 14) + 1);
- TESTINSN_bin("vceq.i32 d0, d1, d2", d0, d1, i32, 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vceq.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VMLA ----\n");
- TESTINSN_bin("vmla.i32 d0, d1, d2", d0, d1, i32, -24, d2, i32, 120);
- TESTINSN_bin("vmla.i32 d6, d7, d8", d6, d7, i32, 140, d8, i32, 120);
- TESTINSN_bin("vmla.i16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmla.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, -120);
- TESTINSN_bin("vmla.i8 d10, d11, d12", d10, d11, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmla.i16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmla.i8 d10, d13, d12", d10, d13, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmla.i16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmla.i32 d10, d11, d15", d10, d11, i32, 24, d15, i32, -120);
-
- printf("---- VMLS ----\n");
- TESTINSN_bin("vmls.i32 d0, d1, d2", d0, d1, i32, -24, d2, i32, 120);
- TESTINSN_bin("vmls.i32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin("vmls.i16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmls.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vmls.i8 d10, d11, d12", d10, d11, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmls.i16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmls.i8 d10, d13, d12", d10, d13, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmls.i16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmls.i32 d10, d11, d15", d10, d11, i32, -24, d15, i32, 120);
-
- printf("---- VMUL ----\n");
- TESTINSN_bin("vmul.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vmul.i32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin("vmul.i16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin("vmul.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vmul.i8 d10, d11, d12", d10, d11, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmul.i16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmul.i8 d10, d11, d12", d10, d11, i32, (1 << 25) + 0xfeb2, d12, i32, (1 << 13) + 0xdf);
- TESTINSN_bin("vmul.i16 d4, d5, d6", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 d7, d8, d9", d7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin("vmul.i8 d10, d13, d12", d10, d13, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2);
- TESTINSN_bin("vmul.i16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin("vmul.i32 d10, d11, d15", d10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 3, q2, i32, 3);
- TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 12, q2, i8, 0x0f);
-
- printf("---- VMUL (by scalar) ----\n");
- TESTINSN_bin("vmul.i32 d0, d1, d4[0]", d0, d1, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmul.i32 d31, d8, d7[1]", d31, d8, i32, 140, d7, i32, -120);
- TESTINSN_bin("vmul.i16 d30, d9, d7[3]", d30, d9, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmul.i16 d4, d5, d6[2]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmul.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmul.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmul.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
-
- printf("---- VMLA (by scalar) ----\n");
- TESTINSN_bin("vmla.i32 d0, d1, d4[0]", d0, d1, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmla.i32 d31, d8, d7[1]", d31, d8, i32, 140, d7, i32, -120);
- TESTINSN_bin("vmla.i16 d30, d9, d7[3]", d30, d9, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmla.i16 d4, d5, d6[2]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmla.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmla.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmla.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
-
- printf("---- VMLS (by scalar) ----\n");
- TESTINSN_bin("vmls.i32 d0, d1, d4[0]", q0, q1, i32, 24, d4, i32, 120);
- TESTINSN_bin("vmls.i32 d31, d8, d7[1]", d31, d8, i32, 140, d7, i32, -120);
- TESTINSN_bin("vmls.i16 d30, d9, d7[3]", d30, d9, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin("vmls.i16 d4, d5, d6[2]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin("vmls.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin("vmls.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin("vmls.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
-
- printf("---- VRSHR ----\n");
- TESTINSN_un("vrshr.s8 d0, d1, #0", d0, d1, i32, -1);
- TESTINSN_un("vrshr.s8 d0, d1, #1", d0, d1, i32, -1);
- TESTINSN_un("vrshr.s16 d3, d4, #2", d3, d4, i32, -0x7c);
- TESTINSN_un("vrshr.s32 d2, d5, #31", d2, d5, i32, -1);
- TESTINSN_un("vrshr.s8 d6, d7, #7", d6, d7, i32, 0xffff);
- TESTINSN_un("vrshr.s16 d8, d9, #12", d8, d9, i32, -10);
- TESTINSN_un("vrshr.s32 d10, d11, #5", d10, d11, i32, 10234);
- TESTINSN_un("vrshr.u8 d12, d13, #1", d12, d13, i32, -1);
- TESTINSN_un("vrshr.u16 d14, d15, #11", d14, d15, i32, -1);
- TESTINSN_un("vrshr.u32 d10, d11, #9", d10, d11, i32, 1000);
- TESTINSN_un("vrshr.u8 d7, d13, #7", d7, d13, i32, -1);
- TESTINSN_un("vrshr.u16 d8, d1, #5", d8, d1, i32, 0xabcf);
- TESTINSN_un("vrshr.u32 d12, d3, #15", d12, d3, i32, -0x1b0);
- TESTINSN_un("vrshr.u64 d0, d1, #42", d0, d1, i32, -1);
- TESTINSN_un("vrshr.s64 d6, d7, #12", d6, d7, i32, 0xfac);
- TESTINSN_un("vrshr.u64 d8, d4, #9", d8, d4, i32, 13560);
- TESTINSN_un("vrshr.s64 d9, d12, #11", d9, d12, i32, 98710);
-
- printf("---- VRSRA ----\n");
- TESTINSN_un("vrsra.s8 d0, d1, #1", d0, d1, i32, -1);
- TESTINSN_un("vrsra.s16 d3, d4, #2", d3, d4, i32, -0x7c);
- TESTINSN_un("vrsra.s32 d2, d5, #31", d2, d5, i32, -1);
- TESTINSN_un("vrsra.s8 d6, d7, #7", d6, d7, i32, 0xffff);
- TESTINSN_un("vrsra.s16 d8, d9, #12", d8, d9, i32, -10);
- TESTINSN_un("vrsra.s32 d10, d11, #5", d10, d11, i32, 10234);
- TESTINSN_un("vrsra.u8 d12, d13, #1", d12, d13, i32, -1);
- TESTINSN_un("vrsra.u16 d14, d15, #11", d14, d15, i32, -1);
- TESTINSN_un("vrsra.u32 d10, d11, #9", d10, d11, i32, 1000);
- TESTINSN_un("vrsra.u8 d7, d13, #7", d7, d13, i32, -1);
- TESTINSN_un("vrsra.u16 d8, d1, #5", d8, d1, i32, 0xabcf);
- TESTINSN_un("vrsra.u32 d12, d3, #15", d12, d3, i32, -0x1b0);
- TESTINSN_un("vrsra.u64 d0, d1, #42", d0, d1, i32, -1);
- TESTINSN_un("vrsra.s64 d6, d7, #12", d6, d7, i32, 0xfac);
- TESTINSN_un("vrsra.u64 d8, d4, #9", d8, d4, i32, 13560);
- TESTINSN_un("vrsra.s64 d9, d12, #11", d9, d12, i32, 98710);
-
- printf("---- VSHR ----\n");
- TESTINSN_un("vshr.s8 d0, d1, #0", d0, d1, i32, -1);
- TESTINSN_un("vshr.s8 d0, d1, #1", d0, d1, i32, -1);
- TESTINSN_un("vshr.s16 d3, d4, #2", d3, d4, i32, -0x7c);
- TESTINSN_un("vshr.s32 d2, d5, #31", d2, d5, i32, -1);
- TESTINSN_un("vshr.s8 d6, d7, #7", d6, d7, i32, 0xffff);
- TESTINSN_un("vshr.s16 d8, d9, #12", d8, d9, i32, -10);
- TESTINSN_un("vshr.s32 d10, d11, #5", d10, d11, i32, 10234);
- TESTINSN_un("vshr.u8 d12, d13, #1", d12, d13, i32, -1);
- TESTINSN_un("vshr.u16 d14, d15, #11", d14, d15, i32, -1);
- TESTINSN_un("vshr.u32 d10, d11, #9", d10, d11, i32, 1000);
- TESTINSN_un("vshr.u8 d7, d13, #7", d7, d13, i32, -1);
- TESTINSN_un("vshr.u16 d8, d1, #5", d8, d1, i32, 0xabcf);
- TESTINSN_un("vshr.u32 d12, d3, #15", d12, d3, i32, -0x1b0);
- TESTINSN_un("vshr.u64 d0, d1, #42", d0, d1, i32, -1);
- TESTINSN_un("vshr.s64 d6, d7, #12", d6, d7, i32, 0xfac);
- TESTINSN_un("vshr.u64 d8, d4, #9", d8, d4, i32, 13560);
- TESTINSN_un("vshr.s64 d9, d12, #11", d9, d12, i32, 98710);
-
- printf("---- VSRA ----\n");
- TESTINSN_un("vsra.s8 d0, d1, #1", d0, d1, i32, -1);
- TESTINSN_un("vsra.s16 d3, d4, #2", d3, d4, i32, -0x7c);
- TESTINSN_un("vsra.s32 d2, d5, #31", d2, d5, i32, -1);
- TESTINSN_un("vsra.s8 d6, d7, #7", d6, d7, i32, 0xffff);
- TESTINSN_un("vsra.s16 d8, d9, #12", d8, d9, i32, -10);
- TESTINSN_un("vsra.s32 d10, d11, #5", d10, d11, i32, 10234);
- TESTINSN_un("vsra.u8 d12, d13, #1", d12, d13, i32, -1);
- TESTINSN_un("vsra.u16 d14, d15, #11", d14, d15, i32, -1);
- TESTINSN_un("vsra.u32 d10, d11, #9", d10, d11, i32, 1000);
- TESTINSN_un("vsra.u8 d7, d13, #7", d7, d13, i32, -1);
- TESTINSN_un("vsra.u16 d8, d1, #5", d8, d1, i32, 0xabcf);
- TESTINSN_un("vsra.u32 d12, d3, #15", d12, d3, i32, -0x1b0);
- TESTINSN_un("vsra.u64 d0, d1, #42", d0, d1, i32, -1);
- TESTINSN_un("vsra.s64 d6, d7, #12", d6, d7, i32, 0xfac);
- TESTINSN_un("vsra.u64 d8, d4, #9", d8, d4, i32, 13560);
- TESTINSN_un("vsra.s64 d9, d12, #11", d9, d12, i32, 98710);
-
- printf("---- VSRI ----\n");
- TESTINSN_un("vsri.16 d0, d1, #1", d0, d1, i32, -1);
- TESTINSN_un("vsri.16 d3, d4, #2", d3, d4, i32, -0x7c);
- TESTINSN_un("vsri.32 d2, d5, #31", d2, d5, i32, -1);
- TESTINSN_un("vsri.8 d6, d7, #7", d6, d7, i32, 0xffff);
- TESTINSN_un("vsri.16 d8, d9, #12", d8, d9, i32, -10);
- TESTINSN_un("vsri.32 d10, d11, #5", d10, d11, i32, 10234);
- TESTINSN_un("vsri.8 d12, d13, #1", d12, d13, i32, -1);
- TESTINSN_un("vsri.16 d14, d15, #11", d14, d15, i32, -1);
- TESTINSN_un("vsri.32 d10, d11, #9", d10, d11, i32, 1000);
- TESTINSN_un("vsri.8 d7, d13, #7", d7, d13, i32, -1);
- TESTINSN_un("vsri.16 d8, d1, #5", d8, d1, i32, 0xabcf);
- TESTINSN_un("vsri.32 d12, d3, #15", d12, d3, i32, -0x1b0);
- TESTINSN_un("vsri.64 d0, d1, #42", d0, d1, i32, -1);
- TESTINSN_un("vsri.64 d6, d7, #12", d6, d7, i32, 0xfac);
- TESTINSN_un("vsri.64 d8, d4, #9", d8, d4, i32, 13560);
- TESTINSN_un("vsri.64 d9, d12, #11", d9, d12, i32, 98710);
-
- printf("---- VMOV (ARM core register to scalar) ----\n");
- TESTINSN_core_to_scalar("vmov.32 d0[0], r5", d0, r5, 13);
- TESTINSN_core_to_scalar("vmov.32 d1[1], r3", d1, r3, 12);
- TESTINSN_core_to_scalar("vmov.16 d0[0], r5", d0, r5, 13);
- TESTINSN_core_to_scalar("vmov.16 d2[2], r6", d2, r6, 14);
- TESTINSN_core_to_scalar("vmov.16 d3[3], r1", d3, r1, 17);
- TESTINSN_core_to_scalar("vmov.8 d0[0], r5", d0, r5, 13);
- TESTINSN_core_to_scalar("vmov.8 d0[1], r5", d0, r5, 13);
- TESTINSN_core_to_scalar("vmov.8 d0[2], r5", d0, r5, 13);
- TESTINSN_core_to_scalar("vmov.8 d0[3], r5", d0, r5, 13);
- TESTINSN_core_to_scalar("vmov.8 d0[4], r5", d0, r5, 13);
- TESTINSN_core_to_scalar("vmov.8 d0[5], r5", d0, r5, 13);
- TESTINSN_core_to_scalar("vmov.8 d0[6], r5", d0, r5, 13);
- TESTINSN_core_to_scalar("vmov.8 d31[7], r5", d31, r5, 13);
-
- printf("---- VMOV (scalar toARM core register) ----\n");
- TESTINSN_scalar_to_core("vmov.32 r5, d0[0]", r5, d0, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.32 r6, d5[1]", r6, d5, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u16 r5, d31[0]", r5, d31, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u16 r5, d30[1]", r5, d30, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u16 r5, d31[2]", r5, d31, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u16 r5, d31[3]", r5, d31, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u8 r2, d4[0]", r2, d4, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u8 r2, d4[1]", r2, d4, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u8 r2, d4[2]", r2, d4, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u8 r2, d4[3]", r2, d4, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u8 r2, d4[4]", r2, d4, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u8 r2, d4[5]", r2, d4, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u8 r2, d4[6]", r2, d4, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.u8 r2, d4[7]", r2, d4, i32, 0x11223344);
- TESTINSN_scalar_to_core("vmov.s16 r5, d31[0]", r5, d31, i8, 128);
- TESTINSN_scalar_to_core("vmov.s16 r5, d30[1]", r5, d30, i8, 128);
- TESTINSN_scalar_to_core("vmov.s16 r5, d31[2]", r5, d31, i8, 128);
- TESTINSN_scalar_to_core("vmov.s16 r5, d31[3]", r5, d31, i8, 128);
- TESTINSN_scalar_to_core("vmov.s8 r2, d4[0]", r2, d4, i8, 128);
- TESTINSN_scalar_to_core("vmov.s8 r2, d4[1]", r2, d4, i8, 128);
- TESTINSN_scalar_to_core("vmov.s8 r2, d4[2]", r2, d4, i8, 128);
- TESTINSN_scalar_to_core("vmov.s8 r2, d4[3]", r2, d4, i8, 128);
- TESTINSN_scalar_to_core("vmov.s8 r2, d4[4]", r2, d4, i8, 128);
- TESTINSN_scalar_to_core("vmov.s8 r2, d4[5]", r2, d4, i8, 130);
- TESTINSN_scalar_to_core("vmov.s8 r2, d4[6]", r2, d4, i8, 129);
- TESTINSN_scalar_to_core("vmov.s8 r2, d4[7]", r2, d4, i8, 131);
-
- printf("---- VLD1 (multiple single elements) ----\n");
- TESTINSN_VLDn("vld1.8 {d0}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.16 {d0}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.32 {d0}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.64 {d0}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.8 {d9}", d9, d9, d9, d9);
- TESTINSN_VLDn("vld1.16 {d17}", d17, d17, d17, d17);
- TESTINSN_VLDn("vld1.32 {d31}", d31, d31, d31, d31);
- TESTINSN_VLDn("vld1.64 {d14}", d14, d14, d14, d14);
- TESTINSN_VLDn("vld1.8 {d0-d1}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld1.16 {d0-d1}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld1.32 {d5-d6}", d5, d6, d5, d6);
- TESTINSN_VLDn("vld1.64 {d30-d31}", d30, d31, d30, d31);
- TESTINSN_VLDn("vld1.8 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VLDn("vld1.16 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VLDn("vld1.32 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VLDn("vld1.64 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VLDn("vld1.8 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld1.16 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld1.32 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld1.64 {d0-d3}", d0, d1, d2, d3);
-
- printf("---- VLD1 (single element to one lane) ----\n");
- TESTINSN_VLDn("vld1.32 {d0[0]}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.32 {d0[1]}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.16 {d1[0]}", d1, d1, d1, d1);
- TESTINSN_VLDn("vld1.16 {d1[1]}", d1, d1, d1, d1);
- TESTINSN_VLDn("vld1.16 {d1[2]}", d1, d1, d1, d1);
- TESTINSN_VLDn("vld1.16 {d1[3]}", d1, d1, d1, d1);
- TESTINSN_VLDn("vld1.8 {d0[7]}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.8 {d1[6]}", d1, d1, d1, d1);
- TESTINSN_VLDn("vld1.8 {d0[5]}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.8 {d0[4]}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.8 {d20[3]}", d20, d20, d20, d20);
- TESTINSN_VLDn("vld1.8 {d0[2]}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.8 {d17[1]}", d17, d17, d17, d17);
- TESTINSN_VLDn("vld1.8 {d30[0]}", d30, d30, d30, d30);
-
- printf("---- VLD1 (single element to all lanes) ----\n");
- TESTINSN_VLDn("vld1.8 {d0[]}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.16 {d0[]}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.32 {d0[]}", d0, d0, d0, d0);
- TESTINSN_VLDn("vld1.8 {d9[]}", d9, d9, d9, d9);
- TESTINSN_VLDn("vld1.16 {d17[]}", d17, d17, d17, d17);
- TESTINSN_VLDn("vld1.32 {d31[]}", d31, d31, d31, d31);
- TESTINSN_VLDn("vld1.8 {d0[],d1[]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld1.16 {d0[],d1[]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld1.32 {d5[],d6[]}", d5, d6, d5, d6);
-
- printf("---- VLD2 (multiple 2-elements) ----\n");
- TESTINSN_VLDn("vld2.8 {d30-d31}", d30, d31, d30, d31);
- TESTINSN_VLDn("vld2.16 {d0-d1}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.32 {d0-d1}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.8 {d10,d12}", d10, d12, d10, d12);
- TESTINSN_VLDn("vld2.16 {d20,d22}", d20, d22, d20, d22);
- TESTINSN_VLDn("vld2.32 {d0,d2}", d0, d2, d0, d2);
- TESTINSN_VLDn("vld2.8 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld2.16 {d20-d23}", d20, d21, d22, d23);
- TESTINSN_VLDn("vld2.32 {d0-d3}", d0, d1, d2, d3);
-
- printf("---- VLD2 (single 2-element structure to one lane) ----\n");
- TESTINSN_VLDn("vld2.32 {d0[0],d1[0]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.32 {d0[1],d1[1]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.32 {d0[0],d2[0]}", d0, d2, d0, d2);
- TESTINSN_VLDn("vld2.32 {d0[1],d2[1]}", d0, d2, d0, d2);
- TESTINSN_VLDn("vld2.16 {d1[0],d2[0]}", d1, d2, d1, d2);
- TESTINSN_VLDn("vld2.16 {d1[1],d2[1]}", d1, d2, d1, d2);
- TESTINSN_VLDn("vld2.16 {d1[2],d2[2]}", d1, d2, d1, d2);
- TESTINSN_VLDn("vld2.16 {d1[3],d2[3]}", d1, d2, d1, d2);
- TESTINSN_VLDn("vld2.16 {d1[0],d3[0]}", d1, d3, d1, d3);
- TESTINSN_VLDn("vld2.16 {d1[1],d3[1]}", d1, d3, d1, d3);
- TESTINSN_VLDn("vld2.16 {d1[2],d3[2]}", d1, d3, d1, d3);
- TESTINSN_VLDn("vld2.16 {d1[3],d3[3]}", d1, d3, d1, d3);
- TESTINSN_VLDn("vld2.8 {d0[7],d1[7]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.8 {d1[6],d2[6]}", d1, d2, d1, d2);
- TESTINSN_VLDn("vld2.8 {d0[5],d1[5]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.8 {d0[4],d1[4]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.8 {d20[3],d21[3]}", d20, d21, d20, d21);
- TESTINSN_VLDn("vld2.8 {d0[2],d1[2]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.8 {d17[1],d18[1]}", d17, d18, d17, d18);
- TESTINSN_VLDn("vld2.8 {d30[0],d31[0]}", d30, d31, d30, d31);
-
- printf("---- VLD2 (2-elements to all lanes) ----\n");
- TESTINSN_VLDn("vld2.8 {d0[],d1[]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.16 {d0[],d1[]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.32 {d0[],d1[]}", d0, d1, d0, d1);
- TESTINSN_VLDn("vld2.8 {d9[],d11[]}", d9, d11, d9, d11);
- TESTINSN_VLDn("vld2.16 {d17[],d18[]}", d17, d18, d17, d18);
- TESTINSN_VLDn("vld2.32 {d30[],d31[]}", d30, d31, d30, d31);
- TESTINSN_VLDn("vld2.8 {d0[],d2[]}", d0, d2, d0, d2);
- TESTINSN_VLDn("vld2.16 {d0[],d2[]}", d0, d2, d0, d2);
- TESTINSN_VLDn("vld2.32 {d5[],d7[]}", d5, d7, d5, d7);
-
- printf("---- VLD3 (multiple 3-elements) ----\n");
- TESTINSN_VLDn("vld3.8 {d20-d22}", d20, d21, d22, d20);
- TESTINSN_VLDn("vld3.16 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VLDn("vld3.32 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VLDn("vld3.8 {d0,d2,d4}", d0, d2, d4, d0);
- TESTINSN_VLDn("vld3.16 {d20,d22,d24}", d20, d22, d24, d20);
- TESTINSN_VLDn("vld3.32 {d0,d2,d4}", d0, d2, d4, d0);
-
- printf("---- VLD3 (single 3-element structure to one lane) ----\n");
- TESTINSN_VLDn("vld3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1);
- TESTINSN_VLDn("vld3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1);
- TESTINSN_VLDn("vld3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2);
- TESTINSN_VLDn("vld3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2);
- TESTINSN_VLDn("vld3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2);
- TESTINSN_VLDn("vld3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2);
- TESTINSN_VLDn("vld3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2);
- TESTINSN_VLDn("vld3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2);
- TESTINSN_VLDn("vld3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5);
- TESTINSN_VLDn("vld3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5);
- TESTINSN_VLDn("vld3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5);
- TESTINSN_VLDn("vld3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5);
- TESTINSN_VLDn("vld3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1);
- TESTINSN_VLDn("vld3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2);
- TESTINSN_VLDn("vld3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1);
- TESTINSN_VLDn("vld3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1);
- TESTINSN_VLDn("vld3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21);
- TESTINSN_VLDn("vld3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1);
- TESTINSN_VLDn("vld3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18);
- TESTINSN_VLDn("vld3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31);
-
- printf("---- VLD3 (3-elements to all lanes) ----\n");
- TESTINSN_VLDn("vld3.8 {d0[],d1[],d2[]}", d0, d1, d2, d1);
- TESTINSN_VLDn("vld3.16 {d0[],d1[],d2[]}", d0, d1, d2, d1);
- TESTINSN_VLDn("vld3.32 {d0[],d1[],d2[]}", d0, d1, d2, d1);
- TESTINSN_VLDn("vld3.8 {d9[],d11[],d13[]}", d9, d11, d13, d11);
- TESTINSN_VLDn("vld3.16 {d17[],d18[],d19[]}", d17, d18, d19, d18);
- TESTINSN_VLDn("vld3.32 {d29[],d30[],d31[]}", d29, d30, d30, d31);
- TESTINSN_VLDn("vld3.8 {d0[],d2[],d4[]}", d0, d2, d4, d2);
- TESTINSN_VLDn("vld3.16 {d0[],d2[],d4[]}", d0, d2, d4, d2);
- TESTINSN_VLDn("vld3.32 {d5[],d7[],d9[]}", d5, d7, d9, d7);
-
- printf("---- VLD4 (multiple 3-elements) ----\n");
- TESTINSN_VLDn("vld4.8 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.16 {d20-d23}", d20, d21, d22, d23);
- TESTINSN_VLDn("vld4.32 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.8 {d0,d2,d4,d6}", d0, d2, d4, d6);
- TESTINSN_VLDn("vld4.16 {d1,d3,d5,d7}", d1, d3, d5, d7);
- TESTINSN_VLDn("vld4.32 {d20,d22,d24,d26}", d20, d22, d24, d26);
-
- printf("---- VLD4 (single 4-element structure to one lane) ----\n");
- TESTINSN_VLDn("vld4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4);
- TESTINSN_VLDn("vld4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6);
- TESTINSN_VLDn("vld4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6);
- TESTINSN_VLDn("vld4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4);
- TESTINSN_VLDn("vld4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4);
- TESTINSN_VLDn("vld4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4);
- TESTINSN_VLDn("vld4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4);
- TESTINSN_VLDn("vld4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7);
- TESTINSN_VLDn("vld4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7);
- TESTINSN_VLDn("vld4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7);
- TESTINSN_VLDn("vld4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7);
- TESTINSN_VLDn("vld4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4);
- TESTINSN_VLDn("vld4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23);
- TESTINSN_VLDn("vld4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20);
- TESTINSN_VLDn("vld4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31);
-
- printf("---- VLD4 (4-elements to all lanes) ----\n");
- TESTINSN_VLDn("vld4.8 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.16 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.32 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3);
- TESTINSN_VLDn("vld4.8 {d9[],d11[],d13[],d15[]}", d9, d11, d13, d15);
- TESTINSN_VLDn("vld4.16 {d17[],d18[],d19[],d20[]}", d17, d18, d19, d20);
- TESTINSN_VLDn("vld4.32 {d28[],d29[],d30[],d31[]}", d28, d29, d30, d31);
- TESTINSN_VLDn("vld4.8 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6);
- TESTINSN_VLDn("vld4.16 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6);
- TESTINSN_VLDn("vld4.32 {d5[],d7[],d9[],d11[]}", d5, d7, d9, d11);
-
- printf("---- VST1 (multiple single elements) ----\n");
- TESTINSN_VSTn("vst1.8 {d0}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.16 {d0}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.32 {d0}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.64 {d0}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.8 {d9}", d9, d9, d9, d9);
- TESTINSN_VSTn("vst1.16 {d17}", d17, d17, d17, d17);
- TESTINSN_VSTn("vst1.32 {d31}", d31, d31, d31, d31);
- TESTINSN_VSTn("vst1.64 {d14}", d14, d14, d14, d14);
- TESTINSN_VSTn("vst1.8 {d0-d1}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst1.16 {d0-d1}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst1.32 {d5-d6}", d5, d6, d5, d6);
- TESTINSN_VSTn("vst1.64 {d30-d31}", d30, d31, d30, d31);
- TESTINSN_VSTn("vst1.8 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VSTn("vst1.16 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VSTn("vst1.32 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VSTn("vst1.64 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VSTn("vst1.8 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst1.16 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst1.32 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst1.64 {d0-d3}", d0, d1, d2, d3);
-
- printf("---- VST1 (single element from one lane) ----\n");
- TESTINSN_VSTn("vst1.32 {d0[0]}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.32 {d0[1]}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.16 {d1[0]}", d1, d1, d1, d1);
- TESTINSN_VSTn("vst1.16 {d1[1]}", d1, d1, d1, d1);
- TESTINSN_VSTn("vst1.16 {d1[2]}", d1, d1, d1, d1);
- TESTINSN_VSTn("vst1.16 {d1[3]}", d1, d1, d1, d1);
- TESTINSN_VSTn("vst1.8 {d0[7]}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.8 {d1[6]}", d1, d1, d1, d1);
- TESTINSN_VSTn("vst1.8 {d0[5]}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.8 {d0[4]}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.8 {d20[3]}", d20, d20, d20, d20);
- TESTINSN_VSTn("vst1.8 {d0[2]}", d0, d0, d0, d0);
- TESTINSN_VSTn("vst1.8 {d17[1]}", d17, d17, d17, d17);
- TESTINSN_VSTn("vst1.8 {d30[0]}", d30, d30, d30, d30);
-
- printf("---- VST2 (multiple 2-elements) ----\n");
- TESTINSN_VSTn("vst2.8 {d30-d31}", d30, d31, d30, d31);
- TESTINSN_VSTn("vst2.16 {d0-d1}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst2.32 {d0-d1}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst2.8 {d10,d12}", d10, d12, d10, d12);
- TESTINSN_VSTn("vst2.16 {d20,d22}", d20, d22, d20, d22);
- TESTINSN_VSTn("vst2.32 {d0,d2}", d0, d2, d0, d2);
- TESTINSN_VSTn("vst2.8 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst2.16 {d20-d23}", d20, d21, d22, d23);
- TESTINSN_VSTn("vst2.32 {d0-d3}", d0, d1, d2, d3);
-
- printf("---- VST2 (single 2-element structure from one lane) ----\n");
- TESTINSN_VSTn("vst2.32 {d0[0],d1[0]}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst2.32 {d0[1],d1[1]}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst2.32 {d0[0],d2[0]}", d0, d2, d0, d2);
- TESTINSN_VSTn("vst2.32 {d0[1],d2[1]}", d0, d2, d0, d2);
- TESTINSN_VSTn("vst2.16 {d1[0],d2[0]}", d1, d2, d1, d2);
- TESTINSN_VSTn("vst2.16 {d1[1],d2[1]}", d1, d2, d1, d2);
- TESTINSN_VSTn("vst2.16 {d1[2],d2[2]}", d1, d2, d1, d2);
- TESTINSN_VSTn("vst2.16 {d1[3],d2[3]}", d1, d2, d1, d2);
- TESTINSN_VSTn("vst2.16 {d1[0],d3[0]}", d1, d3, d1, d3);
- TESTINSN_VSTn("vst2.16 {d1[1],d3[1]}", d1, d3, d1, d3);
- TESTINSN_VSTn("vst2.16 {d1[2],d3[2]}", d1, d3, d1, d3);
- TESTINSN_VSTn("vst2.16 {d1[3],d3[3]}", d1, d3, d1, d3);
- TESTINSN_VSTn("vst2.8 {d0[7],d1[7]}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst2.8 {d1[6],d2[6]}", d1, d2, d1, d2);
- TESTINSN_VSTn("vst2.8 {d0[5],d1[5]}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst2.8 {d0[4],d1[4]}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst2.8 {d20[3],d21[3]}", d20, d21, d20, d21);
- TESTINSN_VSTn("vst2.8 {d0[2],d1[2]}", d0, d1, d0, d1);
- TESTINSN_VSTn("vst2.8 {d17[1],d18[1]}", d17, d18, d17, d18);
- TESTINSN_VSTn("vst2.8 {d30[0],d31[0]}", d30, d31, d30, d31);
-
- printf("---- VST3 (multiple 3-elements) ----\n");
- TESTINSN_VSTn("vst3.8 {d20-d22}", d20, d21, d22, d20);
- TESTINSN_VSTn("vst3.16 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VSTn("vst3.32 {d0-d2}", d0, d1, d2, d0);
- TESTINSN_VSTn("vst3.8 {d0,d2,d4}", d0, d2, d4, d0);
- TESTINSN_VSTn("vst3.16 {d20,d22,d24}", d20, d22, d24, d20);
- TESTINSN_VSTn("vst3.32 {d0,d2,d4}", d0, d2, d4, d0);
-
- printf("---- VST3 (single 3-element structure from one lane) ----\n");
- TESTINSN_VSTn("vst3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1);
- TESTINSN_VSTn("vst3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1);
- TESTINSN_VSTn("vst3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2);
- TESTINSN_VSTn("vst3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2);
- TESTINSN_VSTn("vst3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2);
- TESTINSN_VSTn("vst3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2);
- TESTINSN_VSTn("vst3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2);
- TESTINSN_VSTn("vst3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2);
- TESTINSN_VSTn("vst3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5);
- TESTINSN_VSTn("vst3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5);
- TESTINSN_VSTn("vst3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5);
- TESTINSN_VSTn("vst3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5);
- TESTINSN_VSTn("vst3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1);
- TESTINSN_VSTn("vst3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2);
- TESTINSN_VSTn("vst3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1);
- TESTINSN_VSTn("vst3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1);
- TESTINSN_VSTn("vst3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21);
- TESTINSN_VSTn("vst3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1);
- TESTINSN_VSTn("vst3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18);
- TESTINSN_VSTn("vst3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31);
-
- printf("---- VST4 (multiple 4-elements) ----\n");
- TESTINSN_VSTn("vst4.8 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst4.16 {d20-d23}", d20, d21, d22, d23);
- TESTINSN_VSTn("vst4.32 {d0-d3}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst4.8 {d0,d2,d4,d6}", d0, d2, d4, d6);
- TESTINSN_VSTn("vst4.16 {d1,d3,d5,d7}", d1, d3, d5, d7);
- TESTINSN_VSTn("vst4.32 {d20,d22,d24,d26}", d20, d22, d24, d26);
-
- printf("---- VST4 (single 4-element structure from one lane) ----\n");
- TESTINSN_VSTn("vst4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4);
- TESTINSN_VSTn("vst4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6);
- TESTINSN_VSTn("vst4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6);
- TESTINSN_VSTn("vst4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4);
- TESTINSN_VSTn("vst4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4);
- TESTINSN_VSTn("vst4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4);
- TESTINSN_VSTn("vst4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4);
- TESTINSN_VSTn("vst4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7);
- TESTINSN_VSTn("vst4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7);
- TESTINSN_VSTn("vst4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7);
- TESTINSN_VSTn("vst4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7);
- TESTINSN_VSTn("vst4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4);
- TESTINSN_VSTn("vst4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23);
- TESTINSN_VSTn("vst4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3);
- TESTINSN_VSTn("vst4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20);
- TESTINSN_VSTn("vst4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31);
-
- printf("---- VMOVN ----\n");
- TESTINSN_bin("vmovn.i32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24);
- TESTINSN_bin("vmovn.i16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24);
- TESTINSN_bin("vmovn.i64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24);
- TESTINSN_bin("vmovn.i32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0);
- TESTINSN_bin("vmovn.i16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef);
- TESTINSN_bin("vmovn.i64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24);
-
- printf("---- VQMOVN ----\n");
- TESTINSN_bin_q("vqmovn.u32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24);
- TESTINSN_bin_q("vqmovn.u16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24);
- TESTINSN_bin_q("vqmovn.u64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24);
- TESTINSN_bin_q("vqmovn.u32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0);
- TESTINSN_bin_q("vqmovn.u16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef);
- TESTINSN_bin_q("vqmovn.u64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24);
- TESTINSN_bin_q("vqmovn.s32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24);
- TESTINSN_bin_q("vqmovn.s16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24);
- TESTINSN_bin_q("vqmovn.s64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24);
- TESTINSN_bin_q("vqmovn.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0);
- TESTINSN_bin_q("vqmovn.s16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef);
- TESTINSN_bin_q("vqmovn.s64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24);
- TESTINSN_bin_q("vqmovn.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xff);
- TESTINSN_bin_q("vqmovn.s16 d7, q5", d7, d10, i8, 0xff, d11, i16, 0xff);
- TESTINSN_bin_q("vqmovn.s64 d31, q0", d31, d0, i8, 0xff, d1, i8, 0xff);
-
- printf("---- VQMOVN ----\n");
- TESTINSN_bin_q("vqmovun.s32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24);
- TESTINSN_bin_q("vqmovun.s16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24);
- TESTINSN_bin_q("vqmovun.s64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24);
- TESTINSN_bin_q("vqmovun.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0);
- TESTINSN_bin_q("vqmovun.s16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef);
- TESTINSN_bin_q("vqmovun.s64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24);
- TESTINSN_bin_q("vqmovun.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xff);
- TESTINSN_bin_q("vqmovun.s16 d7, q5", d7, d10, i8, 0xff, d11, i16, 0xff);
- TESTINSN_bin_q("vqmovun.s64 d31, q0", d31, d0, i8, 0xff, d1, i8, 0xff);
-
- printf("---- VABS ----\n");
- TESTINSN_un("vabs.s32 d0, d1", d0, d1, i32, 0x73);
- TESTINSN_un("vabs.s16 d15, d4", d15, d4, i32, 0x73);
- TESTINSN_un("vabs.s8 d8, d7", d8, d7, i32, 0x73);
- TESTINSN_un("vabs.s32 d0, d1", d0, d1, i32, 0xfe);
- TESTINSN_un("vabs.s16 d31, d4", d31, d4, i32, 0xef);
- TESTINSN_un("vabs.s8 d8, d7", d8, d7, i32, 0xde);
- TESTINSN_un("vabs.s32 d0, d1", d0, d1, i16, 0xfe0a);
- TESTINSN_un("vabs.s16 d15, d4", d15, d4, i16, 0xef0b);
- TESTINSN_un("vabs.s8 d8, d7", d8, d7, i16, 0xde0c);
-
- printf("---- VQABS ----\n");
- TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i32, 0x73);
- TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i32, 1 << 31);
- TESTINSN_un_q("vqabs.s16 d0, d1", d0, d1, i32, 1 << 31);
- TESTINSN_un_q("vqabs.s8 d0, d1", d0, d1, i32, 1 << 31);
- TESTINSN_un_q("vqabs.s16 d15, d4", d15, d4, i32, 0x73);
- TESTINSN_un_q("vqabs.s8 d8, d7", d8, d7, i32, 0x73);
- TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i32, 0xfe);
- TESTINSN_un_q("vqabs.s16 d31, d4", d31, d4, i32, 0xef);
- TESTINSN_un_q("vqabs.s8 d8, d7", d8, d7, i32, 0xde);
- TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i16, 0xfe0a);
- TESTINSN_un_q("vqabs.s16 d15, d4", d15, d4, i16, 0xef0b);
- TESTINSN_un_q("vqabs.s8 d8, d7", d8, d7, i16, 0xde0c);
-
- printf("---- VADDHN ----\n");
- TESTINSN_bin("vaddhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72);
- TESTINSN_bin("vaddhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vaddhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vaddhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vaddhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172);
- TESTINSN_bin("vaddhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172);
- TESTINSN_bin("vaddhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172);
- TESTINSN_bin("vaddhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72);
- TESTINSN_bin("vaddhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vaddhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vaddhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
-
- printf("---- VRADDHN ----\n");
- TESTINSN_bin("vraddhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72);
- TESTINSN_bin("vraddhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vraddhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vraddhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vraddhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172);
- TESTINSN_bin("vraddhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172);
- TESTINSN_bin("vraddhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172);
- TESTINSN_bin("vraddhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72);
- TESTINSN_bin("vraddhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vraddhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vraddhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vraddhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0102);
- TESTINSN_bin("vraddhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0102);
- TESTINSN_bin("vraddhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0102);
- TESTINSN_bin("vraddhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x02);
- TESTINSN_bin("vraddhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x02);
- TESTINSN_bin("vraddhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x02);
- TESTINSN_bin("vraddhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x02);
-
- printf("---- VSUBHN ----\n");
- TESTINSN_bin("vsubhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72);
- TESTINSN_bin("vsubhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vsubhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vsubhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vsubhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172);
- TESTINSN_bin("vsubhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172);
- TESTINSN_bin("vsubhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172);
- TESTINSN_bin("vsubhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72);
- TESTINSN_bin("vsubhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vsubhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vsubhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
-
- printf("---- VRSUBHN ----\n");
- TESTINSN_bin("vrsubhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72);
- TESTINSN_bin("vrsubhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vrsubhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vrsubhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vrsubhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172);
- TESTINSN_bin("vrsubhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172);
- TESTINSN_bin("vrsubhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172);
- TESTINSN_bin("vrsubhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72);
- TESTINSN_bin("vrsubhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vrsubhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vrsubhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
- TESTINSN_bin("vrsubhn.i16 d0, q15, q2", d0, q15, i16, 0xef93, q2, i32, 0x0102);
- TESTINSN_bin("vrsubhn.i32 d31, q1, q2", d31, q1, i16, 0xef93, q2, i32, 0x0102);
- TESTINSN_bin("vrsubhn.i64 d0, q1, q8", d0, q1, i16, 0xef93, q8, i32, 0x0102);
- TESTINSN_bin("vrsubhn.i32 d0, q1, q1", d0, q1, i8, 0x93, q1, i32, 0x02);
- TESTINSN_bin("vrsubhn.i16 d0, q1, q2", d0, q1, i8, 0x93, q2, i32, 0x02);
- TESTINSN_bin("vrsubhn.i32 d0, q1, q2", d0, q1, i8, 0x93, q2, i32, 0x02);
- TESTINSN_bin("vrsubhn.i64 d0, q1, q2", d0, q1, i8, 0x93, q2, i32, 0x02);
-
- printf("---- VCEQ #0 ----\n");
- TESTINSN_un("vceq.i32 d0, d1, #0", d0, d1, i32, 0x21);
- TESTINSN_un("vceq.i16 d2, d1, #0", d2, d1, i32, 0x21);
- TESTINSN_un("vceq.i8 d10, d11, #0", d10, d11, i32, 0x21);
- TESTINSN_un("vceq.i32 d0, d1, #0", d0, d1, i32, 0x0);
- TESTINSN_un("vceq.i16 d2, d1, #0", d2, d1, i32, 0x0);
- TESTINSN_un("vceq.i8 d10, d31, #0", d10, d31, i32, 0x0);
-
- printf("---- VCGT #0 ----\n");
- TESTINSN_un("vcgt.s32 d0, d1, #0", d0, d1, i32, 0x21);
- TESTINSN_un("vcgt.s16 d2, d1, #0", d2, d1, i32, 0x21);
- TESTINSN_un("vcgt.s8 d10, d31, #0", d10, d31, i32, 0x21);
- TESTINSN_un("vcgt.s32 d0, d1, #0", d0, d1, i32, 0x0);
- TESTINSN_un("vcgt.s16 d2, d1, #0", d2, d1, i32, 0x0);
- TESTINSN_un("vcgt.s8 d10, d11, #0", d10, d11, i32, 0x0);
- TESTINSN_un("vcgt.s32 d0, d1, #0", d0, d1, i8, 0xef);
- TESTINSN_un("vcgt.s16 d2, d1, #0", d2, d1, i8, 0xed);
- TESTINSN_un("vcgt.s8 d10, d11, #0", d10, d11, i8, 0xae);
-
- printf("---- VCGE #0 ----\n");
- TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i32, 0x21);
- TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i32, 0x21);
- TESTINSN_un("vcge.s8 d10, d11, #0", d10, d11, i32, 0x21);
- TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i32, 0x0);
- TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i32, 0x0);
- TESTINSN_un("vcge.s8 d10, d31, #0", d10, d31, i32, 0x0);
- TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i8, 0xef);
- TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i8, 0xed);
- TESTINSN_un("vcge.s8 d10, d11, #0", d10, d11, i8, 0xae);
- TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i32, 0xef);
- TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i32, 0xed);
- TESTINSN_un("vcge.s8 d10, d11, #0", d10, d11, i32, 0xae);
-
- printf("---- VCLE #0 ----\n");
- TESTINSN_un("vcle.s32 d0, d1, #0", d0, d1, i32, 0x21);
- TESTINSN_un("vcle.s16 d2, d1, #0", d2, d1, i32, 0x21);
- TESTINSN_un("vcle.s8 d10, d11, #0", d10, d11, i32, 0x21);
- TESTINSN_un("vcle.s32 d0, d1, #0", d0, d1, i32, 0x0);
- TESTINSN_un("vcle.s16 d2, d1, #0", d2, d1, i32, 0x0);
- TESTINSN_un("vcle.s8 d10, d31, #0", d10, d31, i32, 0x0);
- TESTINSN_un("vcle.s32 d0, d1, #0", d0, d1, i8, 0xef);
- TESTINSN_un("vcle.s16 d2, d1, #0", d2, d1, i8, 0xed);
- TESTINSN_un("vcle.s8 d10, d11, #0", d10, d11, i8, 0xae);
-
- printf("---- VCLT #0 ----\n");
- TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i32, 0x21);
- TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i32, 0x21);
- TESTINSN_un("vclt.s8 d10, d11, #0", d10, d11, i32, 0x21);
- TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i32, 0x0);
- TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i32, 0x0);
- TESTINSN_un("vclt.s8 d10, d11, #0", d10, d11, i32, 0x0);
- TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i8, 0xef);
- TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i8, 0xed);
- TESTINSN_un("vclt.s8 d10, d31, #0", d10, d31, i8, 0xae);
- TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i32, 0xef);
- TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i32, 0xed);
- TESTINSN_un("vclt.s8 d10, d11, #0", d10, d11, i32, 0xae);
-
- printf("---- VCNT ----\n");
- TESTINSN_un("vcnt.8 d0, d1", d0, d1, i32, 0xac3d25eb);
- TESTINSN_un("vcnt.8 d11, d14", d11, d14, i32, 0xac3d25eb);
- TESTINSN_un("vcnt.8 d6, d2", d6, d2, i32, 0xad0eb);
-
- printf("---- VCLS ----\n");
- TESTINSN_un("vcls.s8 d0, d1", d0, d1, i32, 0x21);
- TESTINSN_un("vcls.s8 d30, d31", d30, d31, i8, 0x82);
- TESTINSN_un("vcls.s16 d0, d1", d0, d1, i32, 0x21);
- TESTINSN_un("vcls.s16 d31, d30", d31, d30, i8, 0x82);
- TESTINSN_un("vcls.s32 d6, d1", d6, d1, i32, 0x21);
- TESTINSN_un("vcls.s32 d30, d5", d30, d5, i8, 0x82);
- TESTINSN_un("vcls.s8 d2, d4", d2, d4, i8, 0xff);
- TESTINSN_un("vcls.s16 d2, d4", d2, d4, i8, 0xff);
- TESTINSN_un("vcls.s32 d2, d4", d2, d4, i8, 0xff);
- TESTINSN_un("vcls.s8 d2, d4", d2, d4, i16, 0xffef);
- TESTINSN_un("vcls.s16 d2, d4", d2, d4, i16, 0xffef);
- TESTINSN_un("vcls.s32 d2, d4", d2, d4, i16, 0xffef);
- TESTINSN_un("vcls.s8 d2, d4", d2, d4, i8, 0x00);
- TESTINSN_un("vcls.s16 d2, d4", d2, d4, i8, 0x00);
- TESTINSN_un("vcls.s32 d2, d4", d2, d4, i8, 0x00);
- TESTINSN_un("vcls.s8 d2, d4", d2, d4, i16, 0x00ef);
- TESTINSN_un("vcls.s16 d2, d4", d2, d4, i16, 0x00ef);
- TESTINSN_un("vcls.s32 d2, d4", d2, d4, i16, 0x00ef);
-
- printf("---- VCLZ ----\n");
- TESTINSN_un("vclz.i8 d0, d1", d0, d1, i32, 0x21);
- TESTINSN_un("vclz.i8 d30, d31", d30, d31, i8, 0x82);
- TESTINSN_un("vclz.i16 d0, d1", d0, d1, i32, 0x21);
- TESTINSN_un("vclz.i16 d31, d30", d31, d30, i8, 0x82);
- TESTINSN_un("vclz.i32 d6, d1", d6, d1, i32, 0x21);
- TESTINSN_un("vclz.i32 d30, d5", d30, d5, i8, 0x82);
- TESTINSN_un("vclz.i8 d2, d4", d2, d4, i8, 0xff);
- TESTINSN_un("vclz.i16 d2, d4", d2, d4, i8, 0xff);
- TESTINSN_un("vclz.i32 d2, d4", d2, d4, i8, 0xff);
- TESTINSN_un("vclz.i8 d2, d4", d2, d4, i16, 0xffef);
- TESTINSN_un("vclz.i16 d2, d4", d2, d4, i16, 0xffef);
- TESTINSN_un("vclz.i32 d2, d4", d2, d4, i16, 0xffef);
- TESTINSN_un("vclz.i8 d2, d4", d2, d4, i8, 0x00);
- TESTINSN_un("vclz.i16 d2, d4", d2, d4, i8, 0x00);
- TESTINSN_un("vclz.i32 d2, d4", d2, d4, i8, 0x00);
- TESTINSN_un("vclz.i8 d2, d4", d2, d4, i16, 0x00ef);
- TESTINSN_un("vclz.i16 d2, d4", d2, d4, i16, 0x00ef);
- TESTINSN_un("vclz.i32 d2, d4", d2, d4, i16, 0x00ef);
-
- printf("---- VSLI ----\n");
- TESTINSN_un("vsli.16 d0, d1, #1", d0, d1, i32, 7);
- TESTINSN_un("vsli.16 d3, d4, #2", d3, d4, i32, -0x7c);
- TESTINSN_un("vsli.32 d2, d5, #31", d2, d5, i32, -1);
- TESTINSN_un("vsli.8 d6, d7, #7", d6, d7, i32, 0xffff);
- TESTINSN_un("vsli.16 d8, d9, #12", d8, d9, i32, -10);
- TESTINSN_un("vsli.32 d10, d11, #5", d10, d11, i32, 10234);
- TESTINSN_un("vsli.8 d12, d13, #1", d12, d13, i32, -1);
- TESTINSN_un("vsli.16 d14, d15, #11", d14, d15, i32, -1);
- TESTINSN_un("vsli.32 d10, d11, #9", d10, d11, i32, 1000);
- TESTINSN_un("vsli.8 d7, d13, #7", d7, d13, i32, -1);
- TESTINSN_un("vsli.16 d8, d1, #1", d8, d1, i32, 0xabcf);
- TESTINSN_un("vsli.32 d12, d3, #15", d12, d3, i32, -0x1b0);
- TESTINSN_un("vsli.64 d0, d1, #42", d0, d1, i32, -1);
- TESTINSN_un("vsli.64 d6, d7, #12", d6, d7, i32, 0xfac);
- TESTINSN_un("vsli.64 d8, d4, #9", d8, d4, i32, 13560);
- TESTINSN_un("vsli.64 d9, d12, #11", d9, d12, i32, 98710);
-
- printf("---- VPADD ----\n");
- TESTINSN_bin("vpadd.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin("vpadd.i32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vpadd.i16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vpadd.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
- TESTINSN_bin("vpadd.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpadd.i16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpadd.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpadd.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VPADDL ----\n");
- TESTINSN_un("vpaddl.u32 d0, d1", d0, d1, i32, 24);
- TESTINSN_un("vpaddl.u32 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpaddl.u16 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpaddl.u8 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpaddl.u8 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.u16 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.u32 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.u32 d10, d11", d10, d11, i32, 24);
- TESTINSN_un("vpaddl.s32 d0, d1", d0, d1, i32, 24);
- TESTINSN_un("vpaddl.s32 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpaddl.s16 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpaddl.s8 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpaddl.s8 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.s16 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.s32 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpaddl.s32 d10, d11", d10, d11, i32, 24);
-
- printf("---- VPADAL ----\n");
- TESTINSN_un("vpadal.u32 d0, d1", d0, d1, i32, 24);
- TESTINSN_un("vpadal.u32 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpadal.u16 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpadal.u8 d0, d1", d0, d1, i8, 140);
- TESTINSN_un("vpadal.u8 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.u16 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.u32 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.u32 d10, d11", d10, d11, i32, 24);
- TESTINSN_un("vpadal.s32 d0, d1", d0, d1, i32, 24);
- TESTINSN_un("vpadal.s32 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpadal.s16 d0, d1", d0, d1, i32, 140);
- TESTINSN_un("vpadal.s8 d0, d1", d0, d1, i8, 140);
- TESTINSN_un("vpadal.s8 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.s16 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.s32 d0, d1", d0, d1, i32, (1 << 31) + 1);
- TESTINSN_un("vpadal.s32 d10, d11", d10, d11, i32, 24);
-
- printf("---- VZIP ----\n");
- TESTINSN_dual("vzip.32 d0, d1", d0, i8, 0x12, d1, i8, 0x34);
- TESTINSN_dual("vzip.16 d1, d0", d0, i8, 0x12, d1, i8, 0x34);
- TESTINSN_dual("vzip.8 d10, d11", d10, i8, 0x12, d11, i8, 0x34);
- TESTINSN_dual("vzip.32 d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vzip.16 d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vzip.8 d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d);
-
- printf("---- VUZP ----\n");
- TESTINSN_dual("vuzp.32 d0, d1", d0, i8, 0x12, d1, i8, 0x34);
- TESTINSN_dual("vuzp.16 d1, d0", d0, i8, 0x12, d1, i8, 0x34);
- TESTINSN_dual("vuzp.8 d10, d11", d10, i8, 0x12, d11, i8, 0x34);
- TESTINSN_dual("vuzp.32 d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vuzp.16 d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vuzp.8 d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d);
-
- printf("---- VTRN ----\n");
- TESTINSN_dual("vtrn.32 d0, d1", d0, i8, 0x12, d1, i8, 0x34);
- TESTINSN_dual("vtrn.16 d1, d0", d0, i8, 0x12, d1, i8, 0x34);
- TESTINSN_dual("vtrn.8 d10, d11", d10, i8, 0x12, d11, i8, 0x34);
- TESTINSN_dual("vtrn.32 d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vtrn.16 d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vtrn.8 d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d);
-
- printf("---- VSWP ----\n");
- TESTINSN_dual("vswp d0, d1", d0, i8, 0x12, d1, i8, 0x34);
- TESTINSN_dual("vswp d1, d0", d0, i8, 0x12, d1, i8, 0x34);
- TESTINSN_dual("vswp d10, d11", d10, i8, 0x12, d11, i8, 0x34);
- TESTINSN_dual("vswp d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vswp d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
- TESTINSN_dual("vswp d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d);
-
- printf("---- VSHRN ----\n");
- TESTINSN_un("vshrn.i16 d0, q1, #1", d0, q1, i32, -1);
- TESTINSN_un("vshrn.i16 d3, q4, #2", d3, q4, i32, -0x7c);
- TESTINSN_un("vshrn.i32 d2, q5, #10", d2, q5, i32, -1);
- TESTINSN_un("vshrn.i32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
- TESTINSN_un("vshrn.i64 d6, q7, #7", d6, q7, i32, 0xffff);
- TESTINSN_un("vshrn.i16 d8, q9, #8", d8, q9, i32, -10);
- TESTINSN_un("vshrn.i32 d10, q11, #5", d10, q11, i32, 10234);
- TESTINSN_un("vshrn.i64 d12, q13, #1", d12, q13, i32, -1);
- TESTINSN_un("vshrn.i16 d14, q15, #6", d14, q15, i32, -1);
- TESTINSN_un("vshrn.i32 d10, q11, #9", d10, q11, i32, 1000);
- TESTINSN_un("vshrn.i64 d7, q13, #7", d7, q13, i32, -1);
- TESTINSN_un("vshrn.i16 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un("vshrn.i32 d12, q3, #15", d12, q3, i32, -0x1b0);
- TESTINSN_un("vshrn.i64 d0, q1, #22", d0, q1, i32, -1);
- TESTINSN_un("vshrn.i64 d6, q7, #12", d6, q7, i32, 0xfac);
- TESTINSN_un("vshrn.i64 d8, q4, #9", d8, q4, i32, 13560);
- TESTINSN_un("vshrn.i64 d9, q12, #11", d9, q12, i32, 98710);
-
- printf("---- VDUP ----\n");
- TESTINSN_un("vdup.8 d12, d2[0]", d12, d2, i32, 0xabc4657);
- TESTINSN_un("vdup.8 d0, d3[2]", d0, d3, i32, 0x7a1b3);
- TESTINSN_un("vdup.8 d1, d0[7]", d1, d0, i32, 0x713aaa);
- TESTINSN_un("vdup.8 d10, d4[3]", d10, d4, i32, 0xaa713);
- TESTINSN_un("vdup.8 d4, d28[4]", d4, d28, i32, 0x7b1c3);
- TESTINSN_un("vdup.16 d17, d19[1]", d17, d19, i32, 0x713ffff);
- TESTINSN_un("vdup.16 d15, d31[2]", d15, d31, i32, 0x7f00fa);
- TESTINSN_un("vdup.16 d6, d2[0]", d6, d2, i32, 0xffabcde);
- TESTINSN_un("vdup.16 d8, d22[3]", d8, d22, i32, 0x713);
- TESTINSN_un("vdup.16 d9, d2[0]", d9, d2, i32, 0x713);
- TESTINSN_un("vdup.32 d10, d17[1]", d10, d17, i32, 0x713);
- TESTINSN_un("vdup.32 d15, d11[0]", d15, d11, i32, 0x3);
- TESTINSN_un("vdup.32 d30, d29[1]", d30, d29, i32, 0xf00000aa);
- TESTINSN_un("vdup.32 d22, d0[1]", d22, d0, i32, 0xf);
- TESTINSN_un("vdup.32 d13, d13[0]", d13, d13, i32, -1);
-
- printf("---- VQDMULH ----\n");
- TESTINSN_bin_q("vqdmulh.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin_q("vqdmulh.s32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin_q("vqdmulh.s16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmulh.s32 d10, d11, d15", d10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 30, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 30);
-
- printf("---- VQDMULH (by scalar) ----\n");
- TESTINSN_bin_q("vqdmulh.s32 d0, d1, d6[0]", d0, d1, i32, 24, d6, i32, 120);
- TESTINSN_bin_q("vqdmulh.s32 d6, d7, d1[1]", d6, d7, i32, 140, d1, i32, -120);
- TESTINSN_bin_q("vqdmulh.s16 d9, d11, d7[0]", d9, d11, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9[1]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6[1]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6[2]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqdmulh.s32 d10, d31, d15[0]", d10, d31, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 31, d7, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s16 d10, d14, d7[3]", d10, d14, i32, 1 << 31, q15, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 30, d15, i32, 1 << 31);
- TESTINSN_bin_q("vqdmulh.s16 d31, d14, d7[1]", d31, d14, i32, 1 << 31, d7, i32, 1 << 30);
-
- printf("---- VSHRN ----\n");
- TESTINSN_un("vshrn.i64 d2, q2, #1", d2, q2, i32, 0xabc4657);
- TESTINSN_un("vshrn.i64 d3, q3, #0", d3, q3, i32, 0x7a1b3);
- TESTINSN_un("vshrn.i64 d1, q0, #3", d1, q0, i32, 0x713aaa);
- TESTINSN_un("vshrn.i64 d0, q4, #5", d0, q4, i32, 0xaa713);
- TESTINSN_un("vshrn.i64 d4, q8, #11", d4, q8, i32, 0x7b1c3);
- TESTINSN_un("vshrn.i16 d7, q12, #6", d7, q12, i32, 0x713ffff);
- TESTINSN_un("vshrn.i16 d15, q11, #2", d15, q11, i32, 0x7f00fa);
- TESTINSN_un("vshrn.i16 d6, q2, #4", d6, q2, i32, 0xffabc);
- TESTINSN_un("vshrn.i16 d8, q12, #3", d8, q12, i32, 0x713);
- TESTINSN_un("vshrn.i16 d9, q2, #7", d9, q2, i32, 0x713);
- TESTINSN_un("vshrn.i32 d10, q13, #2", d10, q13, i32, 0x713);
- TESTINSN_un("vshrn.i32 d15, q11, #1", d15, q11, i32, 0x3);
- TESTINSN_un("vshrn.i32 d10, q9, #5", d10, q9, i32, 0xf00000aa);
- TESTINSN_un("vshrn.i32 d12, q0, #6", d12, q0, i32, 0xf);
- TESTINSN_un("vshrn.i32 d13, q13, #2", d13, q13, i32, -1);
-
- printf("---- VQSHRN ----\n");
- TESTINSN_un_q("vqshrn.s16 d0, q1, #1", d0, q1, i32, -1);
- TESTINSN_un_q("vqshrn.s16 d3, q4, #2", d3, q4, i32, -0x7c);
- TESTINSN_un_q("vqshrn.s32 d2, q5, #10", d2, q5, i32, -1);
- TESTINSN_un_q("vqshrn.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
- TESTINSN_un_q("vqshrn.s16 d2, q5, #1", d2, q5, i16, 0x7fff);
- TESTINSN_un_q("vqshrn.s64 d6, q7, #7", d6, q7, i32, 0xffff);
- TESTINSN_un_q("vqshrn.s16 d8, q9, #8", d8, q9, i32, -10);
- TESTINSN_un_q("vqshrn.s32 d10, q11, #5", d10, q11, i32, 10234);
- TESTINSN_un_q("vqshrn.s64 d12, q13, #1", d12, q13, i32, -1);
- TESTINSN_un_q("vqshrn.s16 d14, q15, #6", d14, q15, i32, -1);
- TESTINSN_un_q("vqshrn.s32 d10, q11, #9", d10, q11, i32, 1000);
- TESTINSN_un_q("vqshrn.s64 d7, q13, #7", d7, q13, i32, -1);
- TESTINSN_un_q("vqshrn.s16 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqshrn.s32 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqshrn.s32 d12, q3, #15", d12, q3, i32, -0x1b0);
- TESTINSN_un_q("vqshrn.s64 d0, q1, #22", d0, q1, i32, -1);
- TESTINSN_un_q("vqshrn.s64 d6, q7, #12", d6, q7, i32, 0xfac);
- TESTINSN_un_q("vqshrn.s64 d8, q4, #9", d8, q4, i32, 13560);
- TESTINSN_un_q("vqshrn.s64 d9, q12, #11", d9, q12, i32, 98710);
- TESTINSN_un_q("vqshrn.u16 d0, q1, #1", d0, q1, i32, -1);
- TESTINSN_un_q("vqshrn.u16 d3, q4, #2", d3, q4, i32, -0x7c);
- TESTINSN_un_q("vqshrn.u32 d2, q5, #10", d2, q5, i32, -1);
- TESTINSN_un_q("vqshrn.u32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
- TESTINSN_un_q("vqshrn.u16 d2, q5, #1", d2, q5, i16, 0x7fff);
- TESTINSN_un_q("vqshrn.u64 d6, q7, #7", d6, q7, i32, 0xffff);
- TESTINSN_un_q("vqshrn.u16 d8, q9, #8", d8, q9, i32, -10);
- TESTINSN_un_q("vqshrn.u32 d10, q11, #5", d10, q11, i32, 10234);
- TESTINSN_un_q("vqshrn.u64 d12, q13, #1", d12, q13, i32, -1);
- TESTINSN_un_q("vqshrn.u16 d14, q15, #6", d14, q15, i32, -1);
- TESTINSN_un_q("vqshrn.u32 d10, q11, #9", d10, q11, i32, 1000);
- TESTINSN_un_q("vqshrn.u64 d7, q13, #7", d7, q13, i32, -1);
- TESTINSN_un_q("vqshrn.u16 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqshrn.u32 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqshrn.u32 d12, q3, #15", d12, q3, i32, -0x1b0);
- TESTINSN_un_q("vqshrn.u64 d0, q1, #22", d0, q1, i32, -1);
- TESTINSN_un_q("vqshrn.u64 d6, q7, #12", d6, q7, i32, 0xfac);
- TESTINSN_un_q("vqshrn.u64 d8, q4, #9", d8, q4, i32, 13560);
- TESTINSN_un_q("vqshrn.u64 d9, q12, #11", d9, q12, i32, 98710);
-
- printf("---- VQSHRUN ----\n");
- TESTINSN_un_q("vqshrun.s16 d0, q1, #1", d0, q1, i32, -1);
- TESTINSN_un_q("vqshrun.s16 d3, q4, #2", d3, q4, i32, -0x7c);
- TESTINSN_un_q("vqshrun.s32 d2, q5, #10", d2, q5, i32, -1);
- TESTINSN_un_q("vqshrun.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
- TESTINSN_un_q("vqshrun.s16 d2, q5, #1", d2, q5, i16, 0x7fff);
- TESTINSN_un_q("vqshrun.s64 d6, q7, #7", d6, q7, i32, 0xffff);
- TESTINSN_un_q("vqshrun.s16 d8, q9, #8", d8, q9, i32, -10);
- TESTINSN_un_q("vqshrun.s32 d10, q11, #5", d10, q11, i32, 10234);
- TESTINSN_un_q("vqshrun.s64 d12, q13, #1", d12, q13, i32, -1);
- TESTINSN_un_q("vqshrun.s16 d14, q15, #6", d14, q15, i32, -1);
- TESTINSN_un_q("vqshrun.s32 d10, q11, #9", d10, q11, i32, 1000);
- TESTINSN_un_q("vqshrun.s64 d7, q13, #7", d7, q13, i32, -1);
- TESTINSN_un_q("vqshrun.s16 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqshrun.s32 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqshrun.s32 d12, q3, #15", d12, q3, i32, -0x1b0);
- TESTINSN_un_q("vqshrun.s64 d0, q1, #22", d0, q1, i32, -1);
- TESTINSN_un_q("vqshrun.s64 d6, q7, #12", d6, q7, i32, 0xfac);
- TESTINSN_un_q("vqshrun.s64 d8, q4, #9", d8, q4, i32, 13560);
- TESTINSN_un_q("vqshrun.s64 d9, q12, #11", d9, q12, i32, 98710);
-
- printf("---- VQRSHRN ----\n");
- TESTINSN_un_q("vqrshrn.s16 d0, q1, #1", d0, q1, i32, -1);
- TESTINSN_un_q("vqrshrn.s16 d3, q4, #2", d3, q4, i32, -0x7c);
- TESTINSN_un_q("vqrshrn.s32 d2, q5, #10", d2, q5, i32, -1);
- TESTINSN_un_q("vqrshrn.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
- TESTINSN_un_q("vqrshrn.s16 d2, q5, #1", d2, q5, i16, 0x7fff);
- TESTINSN_un_q("vqrshrn.s64 d6, q7, #7", d6, q7, i32, 0xffff);
- TESTINSN_un_q("vqrshrn.s16 d8, q9, #8", d8, q9, i32, -10);
- TESTINSN_un_q("vqrshrn.s32 d10, q11, #5", d10, q11, i32, 10234);
- TESTINSN_un_q("vqrshrn.s64 d12, q13, #1", d12, q13, i32, -1);
- TESTINSN_un_q("vqrshrn.s16 d14, q15, #6", d14, q15, i32, -1);
- TESTINSN_un_q("vqrshrn.s32 d10, q11, #9", d10, q11, i32, 1000);
- TESTINSN_un_q("vqrshrn.s64 d7, q13, #7", d7, q13, i32, -1);
- TESTINSN_un_q("vqrshrn.s16 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqrshrn.s32 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqrshrn.s32 d12, q3, #15", d12, q3, i32, -0x1b0);
- TESTINSN_un_q("vqrshrn.s64 d0, q1, #22", d0, q1, i32, -1);
- TESTINSN_un_q("vqrshrn.s64 d6, q7, #12", d6, q7, i32, 0xfac);
- TESTINSN_un_q("vqrshrn.s64 d8, q4, #9", d8, q4, i32, 13560);
- TESTINSN_un_q("vqrshrn.s64 d9, q12, #11", d9, q12, i32, 98710);
- TESTINSN_un_q("vqrshrn.u16 d0, q1, #1", d0, q1, i32, -1);
- TESTINSN_un_q("vqrshrn.u16 d3, q4, #2", d3, q4, i32, -0x7c);
- TESTINSN_un_q("vqrshrn.u32 d2, q5, #10", d2, q5, i32, -1);
- TESTINSN_un_q("vqrshrn.u32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
- TESTINSN_un_q("vqrshrn.u16 d2, q5, #1", d2, q5, i16, 0x7fff);
- TESTINSN_un_q("vqrshrn.u64 d6, q7, #7", d6, q7, i32, 0xffff);
- TESTINSN_un_q("vqrshrn.u16 d8, q9, #8", d8, q9, i32, -10);
- TESTINSN_un_q("vqrshrn.u32 d10, q11, #5", d10, q11, i32, 10234);
- TESTINSN_un_q("vqrshrn.u64 d12, q13, #1", d12, q13, i32, -1);
- TESTINSN_un_q("vqrshrn.u16 d14, q15, #6", d14, q15, i32, -1);
- TESTINSN_un_q("vqrshrn.u32 d10, q11, #9", d10, q11, i32, 1000);
- TESTINSN_un_q("vqrshrn.u64 d7, q13, #7", d7, q13, i32, -1);
- TESTINSN_un_q("vqrshrn.u16 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqrshrn.u32 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqrshrn.u32 d12, q3, #15", d12, q3, i32, -0x1b0);
- TESTINSN_un_q("vqrshrn.u64 d0, q1, #22", d0, q1, i32, -1);
- TESTINSN_un_q("vqrshrn.u64 d6, q7, #12", d6, q7, i32, 0xfac);
- TESTINSN_un_q("vqrshrn.u64 d8, q4, #9", d8, q4, i32, 13560);
- TESTINSN_un_q("vqrshrn.u64 d9, q12, #11", d9, q12, i32, 98710);
-
- printf("---- VQRSHRUN ----\n");
- TESTINSN_un_q("vqrshrun.s16 d0, q1, #1", d0, q1, i32, -1);
- TESTINSN_un_q("vqrshrun.s16 d3, q4, #2", d3, q4, i32, -0x7c);
- TESTINSN_un_q("vqrshrun.s32 d2, q5, #10", d2, q5, i32, -1);
- TESTINSN_un_q("vqrshrun.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
- TESTINSN_un_q("vqrshrun.s16 d2, q5, #1", d2, q5, i16, 0x7fff);
- TESTINSN_un_q("vqrshrun.s64 d6, q7, #7", d6, q7, i32, 0xffff);
- TESTINSN_un_q("vqrshrun.s16 d8, q9, #8", d8, q9, i32, -10);
- TESTINSN_un_q("vqrshrun.s32 d10, q11, #5", d10, q11, i32, 10234);
- TESTINSN_un_q("vqrshrun.s64 d12, q13, #1", d12, q13, i32, -1);
- TESTINSN_un_q("vqrshrun.s16 d14, q15, #6", d14, q15, i32, -1);
- TESTINSN_un_q("vqrshrun.s32 d10, q11, #9", d10, q11, i32, 1000);
- TESTINSN_un_q("vqrshrun.s64 d7, q13, #7", d7, q13, i32, -1);
- TESTINSN_un_q("vqrshrun.s16 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqrshrun.s32 d8, q1, #1", d8, q1, i32, 0xabcf);
- TESTINSN_un_q("vqrshrun.s32 d12, q3, #15", d12, q3, i32, -0x1b0);
- TESTINSN_un_q("vqrshrun.s64 d0, q1, #22", d0, q1, i32, -1);
- TESTINSN_un_q("vqrshrun.s64 d6, q7, #12", d6, q7, i32, 0xfac);
- TESTINSN_un_q("vqrshrun.s64 d8, q4, #9", d8, q4, i32, 13560);
- TESTINSN_un_q("vqrshrun.s64 d9, q12, #11", d9, q12, i32, 98710);
-
- printf("---- VRSHRN ----\n");
- TESTINSN_un("vrshrn.i64 d2, q2, #1", d2, q2, i32, 0xabc4657);
- TESTINSN_un("vrshrn.i64 d3, q3, #0", d3, q3, i32, 0x7a1b3);
- TESTINSN_un("vrshrn.i64 d1, q0, #3", d1, q0, i32, 0x713aaa);
- TESTINSN_un("vrshrn.i64 d0, q4, #5", d0, q4, i32, 0xaa713);
- TESTINSN_un("vrshrn.i64 d4, q8, #11", d4, q8, i32, 0x7b1c3);
- TESTINSN_un("vrshrn.i16 d7, q12, #6", d7, q12, i32, 0x713ffff);
- TESTINSN_un("vrshrn.i16 d15, q11, #2", d15, q11, i32, 0x7f00fa);
- TESTINSN_un("vrshrn.i16 d6, q2, #4", d6, q2, i32, 0xffabc);
- TESTINSN_un("vrshrn.i16 d8, q12, #3", d8, q12, i32, 0x713);
- TESTINSN_un("vrshrn.i16 d9, q2, #7", d9, q2, i32, 0x713);
- TESTINSN_un("vrshrn.i32 d10, q13, #2", d10, q13, i32, 0x713);
- TESTINSN_un("vrshrn.i32 d15, q11, #1", d15, q11, i32, 0x3);
- TESTINSN_un("vrshrn.i32 d10, q9, #5", d10, q9, i32, 0xf00000aa);
- TESTINSN_un("vrshrn.i32 d12, q0, #6", d12, q0, i32, 0xf);
- TESTINSN_un("vrshrn.i32 d13, q13, #2", d13, q13, i32, -1);
-
- printf("---- VSHL (immediate) ----\n");
- TESTINSN_un("vshl.i64 d0, d1, #1", d0, d1, i32, 24);
- TESTINSN_un("vshl.i64 d5, d2, #1", d5, d2, i32, (1 << 30));
- TESTINSN_un("vshl.i64 d9, d12, #2", d9, d12, i32, (1 << 31) + 2);
- TESTINSN_un("vshl.i64 d11, d2, #12", d11, d2, i32, -1);
- TESTINSN_un("vshl.i64 d15, d12, #63", d15, d12, i32, 5);
- TESTINSN_un("vshl.i64 d5, d12, #62", d5, d12, i32, (1 << 31) + 1);
- TESTINSN_un("vshl.i32 d0, d1, #1", d0, d1, i32, 24);
- TESTINSN_un("vshl.i32 d5, d2, #1", d5, d2, i32, (1 << 30));
- TESTINSN_un("vshl.i32 d9, d12, #2", d9, d12, i32, (1 << 31) + 2);
- TESTINSN_un("vshl.i32 d11, d2, #12", d11, d2, i32, -1);
- TESTINSN_un("vshl.i32 d15, d12, #20", d15, d12, i32, 5);
- TESTINSN_un("vshl.i32 d5, d12, #30", d5, d12, i32, (1 << 31) + 1);
- TESTINSN_un("vshl.i16 d0, d1, #1", d0, d1, i16, 24);
- TESTINSN_un("vshl.i16 d5, d2, #1", d5, d2, i32, (1 << 30));
- TESTINSN_un("vshl.i16 d9, d12, #2", d9, d12, i32, (1 << 31) + 2);
- TESTINSN_un("vshl.i16 d11, d2, #12", d11, d2, i16, -1);
- TESTINSN_un("vshl.i16 d15, d12, #3", d15, d12, i16, 5);
- TESTINSN_un("vshl.i16 d5, d12, #14", d5, d12, i32, (1 << 31) + 1);
- TESTINSN_un("vshl.i8 d0, d1, #1", d0, d1, i8, 24);
- TESTINSN_un("vshl.i8 d5, d2, #1", d5, d2, i32, (1 << 30));
- TESTINSN_un("vshl.i8 d9, d12, #2", d9, d12, i32, (1 << 31) + 2);
- TESTINSN_un("vshl.i8 d11, d2, #7", d11, d2, i8, -1);
- TESTINSN_un("vshl.i8 d15, d12, #3", d15, d12, i8, 5);
- TESTINSN_un("vshl.i8 d5, d12, #6", d5, d12, i32, (1 << 31) + 1);
-
- printf("---- VNEG ----\n");
- TESTINSN_un("vneg.s32 d0, d1", d0, d1, i32, 0x73);
- TESTINSN_un("vneg.s16 d15, d4", d15, d4, i32, 0x73);
- TESTINSN_un("vneg.s8 d8, d7", d8, d7, i32, 0x73);
- TESTINSN_un("vneg.s32 d0, d1", d0, d1, i32, 0xfe);
- TESTINSN_un("vneg.s16 d31, d4", d31, d4, i32, 0xef);
- TESTINSN_un("vneg.s8 d8, d7", d8, d7, i32, 0xde);
- TESTINSN_un("vneg.s32 d0, d1", d0, d1, i16, 0xfe0a);
- TESTINSN_un("vneg.s16 d15, d4", d15, d4, i16, 0xef0b);
- TESTINSN_un("vneg.s8 d8, d7", d8, d7, i16, 0xde0c);
-
- printf("---- VQNEG ----\n");
- TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i32, 0x73);
- TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i32, 1 << 31);
- TESTINSN_un_q("vqneg.s16 d0, d1", d0, d1, i32, 1 << 31);
- TESTINSN_un_q("vqneg.s8 d0, d1", d0, d1, i32, 1 << 31);
- TESTINSN_un_q("vqneg.s16 d15, d4", d15, d4, i32, 0x73);
- TESTINSN_un_q("vqneg.s8 d8, d7", d8, d7, i32, 0x73);
- TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i32, 0xfe);
- TESTINSN_un_q("vqneg.s16 d31, d4", d31, d4, i32, 0xef);
- TESTINSN_un_q("vqneg.s8 d8, d7", d8, d7, i32, 0xde);
- TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i16, 0xfe0a);
- TESTINSN_un_q("vqneg.s16 d15, d4", d15, d4, i16, 0xef0b);
- TESTINSN_un_q("vqneg.s8 d8, d7", d8, d7, i16, 0xde0c);
-
- printf("---- VREV ----\n");
- TESTINSN_un("vrev64.8 d0, d1", d0, d1, i32, 0xaabbccdd);
- TESTINSN_un("vrev64.16 d10, d31", d10, d31, i32, 0xaabbccdd);
- TESTINSN_un("vrev64.32 d1, d14", d1, d14, i32, 0xaabbccdd);
- TESTINSN_un("vrev32.8 d0, d1", d0, d1, i32, 0xaabbccdd);
- TESTINSN_un("vrev32.16 d30, d15", d30, d15, i32, 0xaabbccdd);
- TESTINSN_un("vrev16.8 d0, d1", d0, d1, i32, 0xaabbccdd);
-
- printf("---- VTBL ----\n");
- TESTINSN_tbl_1("vtbl.8 d0, {d2}, d1", d0, d1, i8, 0, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbl.8 d0, {d31}, d1", d0, d1, i8, 0x07, d31, i32, 0x12345678);
- TESTINSN_tbl_1("vtbl.8 d0, {d20}, d1", d0, d1, i8, 1, d20, i32, 0x12345678);
- TESTINSN_tbl_1("vtbl.8 d0, {d2}, d31", d0, d31, i8, 2, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbl.8 d30, {d2}, d1", d30, d1, i32, 0x07030501, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbl.8 d31, {d2}, d1", d31, d1, i16, 0x0104, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbl.8 d30, {d2}, d1", d30, d1, i32, 0x07080501, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbl.8 d30, {d2}, d1", d30, d1, i32, 0x07ed05ee, d2, i32, 0x12345678);
- TESTINSN_tbl_2("vtbl.8 d0, {d2-d3}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d0, {d1-d2}, d3", d0, d3, i8, 0xa, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d0, {d30-d31}, d1", d0, d1, i8, 0xf, d30, i32, 0x12345678, d31, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 14, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x070e0e01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0d130f01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_3("vtbl.8 d0, {d2-d4}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d0, {d1-d3}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d0, {d29-d31}, d1", d0, d1, i8, 0x17, d29, i32, 0x12345678, d30, i32, 0xa1a2a3a4, d31, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 17, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0a031504, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x170efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0d130f11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x070f1511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_4("vtbl.8 d0, {d2-d5}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d0, {d1-d4}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd, d4, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d0, {d28-d31}, d1", d0, d1, i8, 0x17, d28, i32, 0x12345678, d29, i32, 0xa1a2a3a4, d30, i32, 0xcacbcccd, d31, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1a, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 0x16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1f, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1a0315ff, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x171efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1d130f1a, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x17101c11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
-
- printf("---- VTBX ----\n");
- TESTINSN_tbl_1("vtbx.8 d0, {d2}, d1", d0, d1, i8, 0, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbx.8 d0, {d31}, d1", d0, d1, i8, 0x07, d31, i32, 0x12345678);
- TESTINSN_tbl_1("vtbx.8 d0, {d20}, d1", d0, d1, i8, 1, d20, i32, 0x12345678);
- TESTINSN_tbl_1("vtbx.8 d0, {d2}, d31", d0, d31, i8, 2, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbx.8 d30, {d2}, d1", d30, d1, i32, 0x07030501, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbx.8 d31, {d2}, d1", d31, d1, i16, 0x0104, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbx.8 d30, {d2}, d1", d30, d1, i32, 0x07080501, d2, i32, 0x12345678);
- TESTINSN_tbl_1("vtbx.8 d30, {d2}, d1", d30, d1, i32, 0x07ed05ee, d2, i32, 0x12345678);
- TESTINSN_tbl_2("vtbx.8 d0, {d2-d3}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d0, {d1-d2}, d3", d0, d3, i8, 0xa, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d0, {d30-d31}, d1", d0, d1, i8, 0xf, d30, i32, 0x12345678, d31, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 14, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x070e0e01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0d130f01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
- TESTINSN_tbl_3("vtbx.8 d0, {d2-d4}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d0, {d1-d3}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d0, {d29-d31}, d1", d0, d1, i8, 0x17, d29, i32, 0x12345678, d30, i32, 0xa1a2a3a4, d31, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 17, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0a031504, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x170efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0d130f11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x070f1511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
- TESTINSN_tbl_4("vtbx.8 d0, {d2-d5}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d0, {d1-d4}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd, d4, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d0, {d28-d31}, d1", d0, d1, i8, 0x17, d28, i32, 0x12345678, d29, i32, 0xa1a2a3a4, d30, i32, 0xcacbcccd, d31, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1a, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 0x16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1f, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1a0315ff, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x171efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1d130f1a, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
- TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x17101c11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
-
- printf("---- VPMAX (integer) ----\n");
- TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121);
- TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120);
- TESTINSN_bin("vpmax.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vpmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120);
- TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120);
- TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, 0x01202120, d2, i32, 120);
- TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmax.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VPMIN (integer) ----\n");
- TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
- TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121);
- TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120);
- TESTINSN_bin("vpmin.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
- TESTINSN_bin("vpmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
- TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
- TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120);
- TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
- TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120);
- TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, 0x01202120, d2, i32, 120);
- TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
- TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
- TESTINSN_bin("vpmin.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
-
- printf("---- VQRDMULH ----\n");
- TESTINSN_bin_q("vqrdmulh.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
- TESTINSN_bin_q("vqrdmulh.s32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120);
- TESTINSN_bin_q("vqrdmulh.s16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
- TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 d10, d11, d15", d10, d11, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqrdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqrdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, (1 << 31) + 1);
- TESTINSN_bin_q("vqrdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 30, d31, i32, 1 << 31);
- TESTINSN_bin_q("vqrdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 30);
-
- printf("---- VQRDMULH (by scalar) ----\n");
- TESTINSN_bin_q("vqrdmulh.s32 d0, d1, d6[0]", d0, d1, i32, 24, d6, i32, 120);
- TESTINSN_bin_q("vqrdmulh.s32 d6, d7, d1[1]", d6, d7, i32, 140, d1, i32, -120);
- TESTINSN_bin_q("vqrdmulh.s16 d9, d11, d7[0]", d9, d11, i32, 0x140, d7, i32, 0x120);
- TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9[1]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6[1]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31), d9, i32, 12);
- TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6[2]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
- TESTINSN_bin_q("vqrdmulh.s32 d10, d31, d15[0]", d10, d31, i32, 24, d15, i32, 120);
- TESTINSN_bin_q("vqrdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 31, d7, i32, 1 << 31);
- TESTINSN_bin_q("vqrdmulh.s16 d10, d14, d7[3]", d10, d14, i32, 1 << 31, q15, i32, (1 << 31) + 1);
- TESTINSN_bin_q("vqrdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 30, d15, i32, 1 << 31);
- TESTINSN_bin_q("vqrdmulh.s16 d31, d14, d7[1]", d31, d14, i32, 1 << 31, d7, i32, 1 << 30);
-
- printf("---- VADD (fp) ----\n");
- TESTINSN_bin("vadd.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vadd.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vadd.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vadd.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vadd.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vadd.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vadd.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vadd.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vadd.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vadd.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vadd.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vadd.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vadd.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vadd.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vadd.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vadd.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VSUB (fp) ----\n");
- TESTINSN_bin("vsub.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vsub.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vsub.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vsub.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vsub.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vsub.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
- TESTINSN_bin("vsub.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
- TESTINSN_bin("vsub.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vsub.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vsub.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vsub.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vsub.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vsub.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vsub.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vsub.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vsub.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vsub.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vsub.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VMUL (fp) ----\n");
- TESTINSN_bin("vmul.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vmul.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vmul.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vmul.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vmul.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vmul.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
- TESTINSN_bin("vmul.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
- TESTINSN_bin("vmul.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vmul.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vmul.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vmul.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vmul.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vmul.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vmul.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vmul.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vmul.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vmul.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vmul.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VMLA (fp) ----\n");
- TESTINSN_bin_f("vmla.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin_f("vmla.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin_f("vmla.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin_f("vmla.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin_f("vmla.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin_f("vmla.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
- TESTINSN_bin_f("vmla.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
- TESTINSN_bin_f("vmla.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin_f("vmla.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin_f("vmla.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin_f("vmla.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin_f("vmla.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin_f("vmla.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin_f("vmla.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin_f("vmla.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin_f("vmla.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin_f("vmla.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin_f("vmla.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VMLA (fp by scalar) ----\n");
- TESTINSN_bin_f("vmla.f32 d0, d1, d4[0]", d0, d1, i32, f2u(24), d4, i32, f2u(120));
- TESTINSN_bin_f("vmla.f32 d31, d8, d7[1]", d31, d8, i32, f2u(140), d7, i32, f2u(-120));
- TESTINSN_bin_f("vmla.f32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin_f("vmla.f32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin_f("vmla.f32 d17, d8, d1[1]", d17, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
- TESTINSN_bin_f("vmla.f32 d7, d8, d1[0]", d7, d8, i32, f2u(1e22), d1, i32, f2u(1e-19));
- TESTINSN_bin_f("vmla.f32 d7, d24, d1[0]", d7, d24, i32, f2u(1e12), d1, i32, f2u(1e11));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VMLS (fp) ----\n");
- TESTINSN_bin_f("vmls.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin_f("vmls.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin_f("vmls.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin_f("vmls.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin_f("vmls.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin_f("vmls.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
- TESTINSN_bin_f("vmls.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
- TESTINSN_bin_f("vmls.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin_f("vmls.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin_f("vmls.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin_f("vmls.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin_f("vmls.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin_f("vmls.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin_f("vmls.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin_f("vmls.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin_f("vmls.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin_f("vmls.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin_f("vmls.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VMLS (fp by scalar) ----\n");
- TESTINSN_bin_f("vmls.f32 d0, d1, d4[0]", d0, d1, i32, f2u(24), d4, i32, f2u(120));
- TESTINSN_bin_f("vmls.f32 d31, d8, d7[1]", d31, d8, i32, f2u(140), d7, i32, f2u(-120));
- TESTINSN_bin_f("vmls.f32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
- TESTINSN_bin_f("vmls.f32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
- TESTINSN_bin_f("vmls.f32 d17, d8, d1[1]", d17, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
- TESTINSN_bin_f("vmls.f32 d7, d8, d1[0]", d7, d8, i32, f2u(1e22), d1, i32, f2u(1e-19));
- TESTINSN_bin_f("vmls.f32 d7, d24, d1[0]", d7, d24, i32, f2u(1e12), d1, i32, f2u(1e11));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VABD (fp) ----\n");
- TESTINSN_bin("vabd.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vabd.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vabd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vabd.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vabd.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vabd.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
- TESTINSN_bin("vabd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
- TESTINSN_bin("vabd.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vabd.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vabd.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vabd.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vabd.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vabd.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vabd.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vabd.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vabd.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vabd.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vabd.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vabd.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vabd.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
-
- printf("---- VPADD (fp) ----\n");
- TESTINSN_bin("vpadd.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vpadd.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vpadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vpadd.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vpadd.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vpadd.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
- TESTINSN_bin("vpadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
- TESTINSN_bin("vpadd.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vpadd.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vpadd.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vpadd.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vpadd.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vpadd.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vpadd.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vpadd.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vpadd.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vpadd.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vpadd.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VCVT (integer <-> fp) ----\n");
- TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vcvt.u32.f32 d10, d11", d10, d11, i32, f2u(3e22));
- TESTINSN_un("vcvt.u32.f32 d15, d4", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vcvt.u32.f32 d15, d4", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vcvt.u32.f32 d15, d4", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vcvt.u32.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vcvt.u32.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vcvt.s32.f32 d20, d21", d20, d21, i32, f2u(3e22));
- TESTINSN_un("vcvt.s32.f32 d15, d4", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vcvt.s32.f32 d15, d4", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vcvt.s32.f32 d15, d4", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vcvt.s32.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vcvt.s32.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vcvt.f32.u32 d0, d1", d0, d1, i32, 7);
- TESTINSN_un("vcvt.f32.u32 d10, d11", d10, d11, i32, 1 << 31);
- TESTINSN_un("vcvt.f32.u32 d0, d1", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vcvt.f32.u32 d24, d26", d24, d26, i32, (1U << 31) - 1);
- TESTINSN_un("vcvt.f32.u32 d0, d14", d0, d14, i32, 0x30a0bcef);
- TESTINSN_un("vcvt.f32.s32 d0, d1", d0, d1, i32, 7);
- TESTINSN_un("vcvt.f32.s32 d30, d31", d30, d31, i32, 1 << 31);
- TESTINSN_un("vcvt.f32.s32 d0, d1", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vcvt.f32.s32 d0, d1", d0, d1, i32, (1U << 31) - 1);
- TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
- TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VCVT (fixed <-> fp) ----\n");
- TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vcvt.u32.f32 d10, d11, #1", d10, d11, i32, f2u(3e22));
- TESTINSN_un("vcvt.u32.f32 d15, d4, #32", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vcvt.u32.f32 d15, d4, #7", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vcvt.u32.f32 d15, d4, #4", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vcvt.u32.f32 d12, d8, #3", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vcvt.u32.f32 d12, d8, #3", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vcvt.s32.f32 d0, d1, #5", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vcvt.s32.f32 d20, d21, #1", d20, d21, i32, f2u(3e22));
- TESTINSN_un("vcvt.s32.f32 d15, d4, #8", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vcvt.s32.f32 d15, d4, #2", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vcvt.s32.f32 d15, d4, #1", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vcvt.s32.f32 d12, d8, #2", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vcvt.s32.f32 d12, d8, #2", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vcvt.f32.u32 d0, d1, #5", d0, d1, i32, 7);
- TESTINSN_un("vcvt.f32.u32 d10, d11, #9", d10, d11, i32, 1 << 31);
- TESTINSN_un("vcvt.f32.u32 d0, d1, #4", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vcvt.f32.u32 d24, d26, #6", d24, d26, i32, (1U << 31) - 1);
- TESTINSN_un("vcvt.f32.u32 d0, d14, #5", d0, d14, i32, 0x30a0bcef);
- TESTINSN_un("vcvt.f32.s32 d0, d1, #12", d0, d1, i32, 7);
- TESTINSN_un("vcvt.f32.s32 d30, d31, #8", d30, d31, i32, 1 << 31);
- TESTINSN_un("vcvt.f32.s32 d0, d1, #1", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vcvt.f32.s32 d0, d1, #6", d0, d1, i32, (1U << 31) - 1);
- TESTINSN_un("vcvt.f32.s32 d0, d14, #2", d0, d14, i32, 0x30a0bcef);
- TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(-INFINITY));
- TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VMAX (fp) ----\n");
- TESTINSN_bin("vmax.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vmax.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vmax.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vmax.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vmax.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vmax.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vmax.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vmax.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vmax.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vmax.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vmax.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vmax.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vmax.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vmax.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vmax.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vmax.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VMIN (fp) ----\n");
- TESTINSN_bin("vmin.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vmin.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vmin.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vmin.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vmin.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vmin.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vmin.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vmin.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vmin.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vmin.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vmin.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vmin.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vmin.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vmin.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vmin.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vmin.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VPMAX (fp) ----\n");
- TESTINSN_bin("vpmax.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vpmax.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vpmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vpmax.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vpmax.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vpmax.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vpmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vpmax.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vpmax.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vpmax.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vpmax.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vpmax.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vpmax.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vpmax.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vpmax.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vpmax.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vpmax.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vpmax.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VPMIN (fp) ----\n");
- TESTINSN_bin("vpmin.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vpmin.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vpmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vpmin.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vpmin.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vpmin.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vpmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vpmin.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vpmin.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vpmin.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vpmin.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vpmin.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vpmin.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vpmin.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vpmin.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vpmin.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vpmin.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vpmin.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VRECPE ----\n");
- TESTINSN_un("vrecpe.u32 d0, d1", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vrecpe.u32 d0, d1", d0, d1, i32, f2u(-653.2));
- TESTINSN_un("vrecpe.u32 d10, d11", d10, d11, i32, f2u(3e22));
- TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vrecpe.u32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vrecpe.u32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vrecpe.u32 d0, d1", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vrecpe.u32 d10, d11", d10, d11, i32, f2u(3e22));
- TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vrecpe.f32 d15, d4", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vrecpe.f32 d15, d4", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vrecpe.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vrecpe.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, 7);
- TESTINSN_un("vrecpe.f32 d10, d11", d10, d11, i32, 1 << 31);
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
- TESTINSN_un("vrecpe.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, 7);
- TESTINSN_un("vrecpe.f32 d10, d11", d10, d11, i32, 1 << 31);
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
- TESTINSN_un("vrecpe.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VRECPS ----\n");
- TESTINSN_bin("vrecps.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vrecps.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vrecps.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vrecps.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vrecps.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vrecps.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
- TESTINSN_bin("vrecps.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
- TESTINSN_bin("vrecps.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vrecps.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vrecps.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vrecps.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vrecps.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vrecps.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vrecps.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vrecps.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vrecps.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vrecps.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vrecps.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VABS (fp) ----\n");
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, f2u(3e22));
- TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, f2u(3e22));
- TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, 7);
- TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, 1 << 31);
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
- TESTINSN_un("vabs.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, 7);
- TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, 1 << 31);
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
- TESTINSN_un("vabs.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VCGT (fp) ----\n");
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
- TESTINSN_bin("vcgt.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
- TESTINSN_bin("vcgt.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
- TESTINSN_bin("vcgt.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vcgt.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vcgt.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vcgt.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vcgt.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vcgt.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vcgt.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vcgt.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vcgt.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vcgt.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vcgt.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vcgt.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vcgt.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vcgt.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vcgt.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vcgt.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vcgt.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vcgt.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VCGE (fp) ----\n");
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
- TESTINSN_bin("vcge.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
- TESTINSN_bin("vcge.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
- TESTINSN_bin("vcge.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vcge.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vcge.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vcge.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vcge.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vcge.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vcge.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vcge.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vcge.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vcge.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vcge.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vcge.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vcge.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vcge.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vcge.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vcge.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vcge.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vcge.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VACGT (fp) ----\n");
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
- TESTINSN_bin("vacgt.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
- TESTINSN_bin("vacgt.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
- TESTINSN_bin("vacgt.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vacgt.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vacgt.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vacgt.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vacgt.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vacgt.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vacgt.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vacgt.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vacgt.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vacgt.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vacgt.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vacgt.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vacgt.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vacgt.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vacgt.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vacgt.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vacgt.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vacgt.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VACGE (fp) ----\n");
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
- TESTINSN_bin("vacge.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
- TESTINSN_bin("vacge.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
- TESTINSN_bin("vacge.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vacge.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vacge.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vacge.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vacge.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vacge.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vacge.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vacge.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vacge.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vacge.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vacge.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vacge.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vacge.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vacge.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vacge.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vacge.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vacge.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vacge.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VCEQ (fp) ----\n");
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
- TESTINSN_bin("vceq.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
- TESTINSN_bin("vceq.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
- TESTINSN_bin("vceq.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vceq.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vceq.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vceq.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vceq.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vceq.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
- TESTINSN_bin("vceq.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
- TESTINSN_bin("vceq.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vceq.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vceq.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vceq.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vceq.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vceq.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vceq.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vceq.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vceq.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vceq.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vceq.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VCEQ (fp) #0 ----\n");
- TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
- TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, 0x1);
- TESTINSN_un("vceq.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
- TESTINSN_un("vceq.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
- TESTINSN_un("vceq.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
- TESTINSN_un("vceq.f32 d30, d15, #0", d30, d15, i32, 0x0);
- TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VCGT (fp) #0 ----\n");
- TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
- TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, 0x1);
- TESTINSN_un("vcgt.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
- TESTINSN_un("vcgt.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
- TESTINSN_un("vcgt.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
- TESTINSN_un("vcgt.f32 d30, d15, #0", d30, d15, i32, 0x0);
- TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VCLT (fp) #0 ----\n");
- TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
- TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, 0x1);
- TESTINSN_un("vclt.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
- TESTINSN_un("vclt.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
- TESTINSN_un("vclt.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
- TESTINSN_un("vclt.f32 d30, d15, #0", d30, d15, i32, 0x0);
- TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VCGE (fp) #0 ----\n");
- TESTINSN_un("vcge.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
- TESTINSN_un("vcge.f32 d0, d1, #0", d0, d1, i32, 0x1);
- TESTINSN_un("vcge.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
- TESTINSN_un("vcge.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
- TESTINSN_un("vcge.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
- TESTINSN_un("vcge.f32 d30, d15, #0", d30, d15, i32, 0x0);
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VCLE (fp) #0 ----\n");
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, 0x1);
- TESTINSN_un("vcle.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
- TESTINSN_un("vcle.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
- TESTINSN_un("vcle.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
- TESTINSN_un("vcle.f32 d30, d15, #0", d30, d15, i32, 0x0);
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VNEG (fp) ----\n");
- TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, 0x01000000);
- TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, 0x1);
- TESTINSN_un("vneg.f32 d2, d1", d2, d1, i32, 1 << 31);
- TESTINSN_un("vneg.f32 d2, d1", d2, d1, i32, f2u(23.04));
- TESTINSN_un("vneg.f32 d2, d31", d2, d31, i32, f2u(-23.04));
- TESTINSN_un("vneg.f32 d30, d15", d30, d15, i32, 0x0);
- TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
-
- printf("---- VRSQRTS ----\n");
- TESTINSN_bin("vrsqrts.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
- TESTINSN_bin("vrsqrts.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
- TESTINSN_bin("vrsqrts.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
- TESTINSN_bin("vrsqrts.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
- TESTINSN_bin("vrsqrts.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
- TESTINSN_bin("vrsqrts.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
- TESTINSN_bin("vrsqrts.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
- TESTINSN_bin("vrsqrts.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
- TESTINSN_bin("vrsqrts.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
- TESTINSN_bin("vrsqrts.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
- TESTINSN_bin("vrsqrts.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
- TESTINSN_bin("vrsqrts.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
- TESTINSN_bin("vrsqrts.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
- TESTINSN_bin("vrsqrts.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
- TESTINSN_bin("vrsqrts.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
- TESTINSN_bin("vrsqrts.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
- TESTINSN_bin("vrsqrts.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
- TESTINSN_bin("vrsqrts.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
- TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
-
- printf("---- VRSQRTE (fp) ----\n");
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, f2u(3e22));
- TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(3.2));
- TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, f2u(3e22));
- TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(3e9));
- TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-0.5));
- TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-7.1));
- TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
- TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, 7);
- TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, 1 << 31);
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
- TESTINSN_un("vrsqrte.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, 7);
- TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, 1 << 31);
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
- TESTINSN_un("vrsqrte.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(NAN));
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(0.0));
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
- TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
-
- return 0;
-}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/arm/neon64.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/arm/neon64.stderr.exp
diff --git a/main/none/tests/arm/neon64.vgtest b/main/none/tests/arm/neon64.vgtest
index 26d75a7..dffebc4 100644
--- a/main/none/tests/arm/neon64.vgtest
+++ b/main/none/tests/arm/neon64.vgtest
@@ -1,4 +1,2 @@
prog: neon64
vgopts: -q
-prog: neon64
-vgopts: -q
diff --git a/main/none/tests/arm/v6int.c b/main/none/tests/arm/v6int.c
deleted file mode 100644
index e69de29..0000000
--- a/main/none/tests/arm/v6int.c
+++ /dev/null
diff --git a/main/none/tests/arm/v6int.vgtest b/main/none/tests/arm/v6int.vgtest
deleted file mode 100644
index e69de29..0000000
--- a/main/none/tests/arm/v6int.vgtest
+++ /dev/null
diff --git a/main/none/tests/arm/v6intARM.c b/main/none/tests/arm/v6intARM.c
index bec48f4..282317a 100644
--- a/main/none/tests/arm/v6intARM.c
+++ b/main/none/tests/arm/v6intARM.c
@@ -845,856 +845,6 @@
}
printf("------------ PLD/PLDW (done) ------------\n");
-
- return 0;
-}
-
-/* How to compile:
- gcc -O -g -Wall -mcpu=cortex-a8 -o testarmv6int testarmv6int.c
-*/
-
-#include <stdio.h>
-
-/* test macros to generate and output the result of a single instruction */
-#define TESTINST2(instruction, RMval, RD, RM, carryin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "movs %3,%3;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
- "mov " #RM ",%2;" \
- /* set #RD to 0x55555555 so we can see which parts get overwritten */ \
- "mov " #RD ", #0x55" "\n\t" \
- "orr " #RD "," #RD "," #RD ", LSL #8" "\n\t" \
- "orr " #RD "," #RD "," #RD ", LSL #16" "\n\t" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (carryin) \
- : #RD, #RM, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, RMval, \
- carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "movs %4,%4;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
- "mov " #RM ",%2;" \
- "mov " #RN ",%3;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (RNval), "r" (carryin) \
- : #RD, #RM, #RN, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, RMval, RNval, \
- carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "movs %5,%5;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
- "mov " #RM ",%2;" \
- "mov " #RN ",%3;" \
- "mov " #RS ",%4;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (RNval), "r" (RSval), "r" (carryin) \
- : #RD, #RM, #RN, #RS, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, RMval, RNval, RSval, \
- carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-#define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \
-{ \
- unsigned int out; \
- unsigned int out2; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "movs %7,%7;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
- "mov " #RD ",%3;" \
- "mov " #RD2 ",%4;" \
- "mov " #RM ",%5;" \
- "mov " #RS ",%6;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mov %1," #RD2 ";" \
- "mrs %2,cpsr;" \
- : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \
- : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (carryin) \
- : #RD, #RD2, #RM, #RS, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, out2, RMval, RSval, \
- carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-/* helpers */
-#define TESTCARRY { int c = 0; for (c = 0; c < 2; c++) {
-#define TESTCARRYEND }}
-
-
-
-
-int main(int argc, char **argv)
-{
-
- printf("MOV\n");
- TESTINST2("mov r0, r1", 1, r0, r1, 0);
- TESTINST2("cpy r0, r1", 1, r0, r1, 0);
- TESTINST2("mov r0, #0", 0, r0, r1, 0);
- TESTINST2("mov r0, #1", 0, r0, r1, 0);
- TESTCARRY
- TESTINST2("movs r0, r1", 1, r0, r1, c);
- TESTINST2("movs r0, r1", 0, r0, r1, c);
- TESTINST2("movs r0, r1", 0x80000000, r0, r1, c);
- TESTINST2("movs r0, #0", 0, r0, r1, c);
- TESTINST2("movs r0, #1", 0, r0, r1, c);
- TESTCARRYEND
-
- printf("MVN\n");
- TESTINST2("mvn r0, r1", 1, r0, r1, 0);
- TESTCARRY
- TESTINST2("mvns r0, r1", 1, r0, r1, c);
- TESTINST2("mvns r0, r1", 0, r0, r1, c);
- TESTINST2("mvns r0, r1", 0x80000000, r0, r1, c);
- TESTCARRYEND
-
- printf("ADD\n");
- TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 1, -1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0x80000000, -1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0x80000000, 0, r0, r1, r2, 0);
-
- printf("ADC\n");
- TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 1);
-
- printf("LSL\n");
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
-
- TESTINST3("lsl r0, r1, r2", 0x1, 0, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0x1, 1, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0x1, 31, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0x2, 31, r0, r1, r2, 0);
-
- printf("LSLS\n");
- TESTCARRY
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0x1, 0, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0x1, 1, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0x1, 31, r0, r1, r2, c);
- TESTINST3("lsls r0, r1, r2", 0x2, 31, r0, r1, r2, c);
- TESTCARRYEND
-
- printf("LSL immediate\n");
- TESTCARRY
- TESTINST2("lsl r0, r1, #0", 0xffffffff, r0, r1, c);
- TESTINST2("lsl r0, r1, #1", 0xffffffff, r0, r1, c);
- TESTINST2("lsl r0, r1, #31", 0xffffffff, r0, r1, c);
- TESTINST2("lsl r0, r1, #0", 0x1, r0, r1, c);
- TESTINST2("lsl r0, r1, #1", 0x1, r0, r1, c);
- TESTINST2("lsl r0, r1, #31", 0x1, r0, r1, c);
- TESTINST2("lsl r0, r1, #31", 0x2, r0, r1, c);
- TESTCARRYEND
-
- printf("LSLS immediate\n");
- TESTCARRY
- TESTINST2("lsls r0, r1, #0", 0xffffffff, r0, r1, c);
- TESTINST2("lsls r0, r1, #1", 0xffffffff, r0, r1, c);
- TESTINST2("lsls r0, r1, #31", 0xffffffff, r0, r1, c);
- TESTINST2("lsls r0, r1, #0", 0x1, r0, r1, c);
- TESTINST2("lsls r0, r1, #1", 0x1, r0, r1, c);
- TESTINST2("lsls r0, r1, #31", 0x1, r0, r1, c);
- TESTINST2("lsls r0, r1, #31", 0x2, r0, r1, c);
- TESTCARRYEND
-
- printf("LSR\n");
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
-
- printf("LSRS\n");
- TESTCARRY
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
- TESTCARRYEND
-
- printf("LSR immediate\n");
- TESTINST2("lsr r0, r1, #0", 0xffffffff, r0, r1, 0);
- TESTINST2("lsr r0, r1, #1", 0xffffffff, r0, r1, 0);
- TESTINST2("lsr r0, r1, #31", 0xffffffff, r0, r1, 0);
- TESTINST2("lsr r0, r1, #32", 0xffffffff, r0, r1, 0);
- TESTINST2("lsr r0, r1, #16", 0x00010000, r0, r1, 0);
- TESTINST2("lsr r0, r1, #17", 0x00010000, r0, r1, 0);
- TESTINST2("lsr r0, r1, #18", 0x00010000, r0, r1, 0);
-
- printf("LSRS immediate\n");
- TESTCARRY
- TESTINST2("lsrs r0, r1, #0", 0xffffffff, r0, r1, c);
- TESTINST2("lsrs r0, r1, #1", 0xffffffff, r0, r1, c);
- TESTINST2("lsrs r0, r1, #31", 0xffffffff, r0, r1, c);
- TESTINST2("lsrs r0, r1, #32", 0xffffffff, r0, r1, c);
- TESTINST2("lsrs r0, r1, #16", 0x00010000, r0, r1, c);
- TESTINST2("lsrs r0, r1, #17", 0x00010000, r0, r1, c);
- TESTINST2("lsrs r0, r1, #18", 0x00010000, r0, r1, c);
- TESTCARRYEND
-
- printf("ASR\n");
- TESTCARRY
- TESTINST3("asr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, c);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, c);
- TESTCARRYEND
-
- printf("ASRS\n");
- TESTCARRY
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, c);
- TESTCARRYEND
-
- TESTCARRY
- TESTINST3("asrs r0, r1, r2", 0x8, 0, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x8, 1, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x8, 2, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x8, 3, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x8, 4, r0, r1, r2, c);
- TESTINST3("asrs r0, r1, r2", 0x8, 5, r0, r1, r2, c);
- TESTCARRYEND
-
- TESTINST3("asrs r0, r1, r2", 0x80000001, 1, r0, r1, r2, 0);
- TESTINST3("asrs r0, r1, r2", 0x80000001, 2, r0, r1, r2, 0);
-
- printf("ASR immediate\n");
- TESTINST2("asr r0, r1, #0", 0xffffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #1", 0xffffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #31", 0xffffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #32", 0xffffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #0", 0x7fffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #1", 0x7fffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #31", 0x7fffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #32", 0x7fffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #16", 0x00010000, r0, r1, 0);
- TESTINST2("asr r0, r1, #17", 0x00010000, r0, r1, 0);
- TESTINST2("asr r0, r1, #18", 0x00010000, r0, r1, 0);
-
- printf("ASRS immediate\n");
- TESTCARRY
- TESTINST2("asrs r0, r1, #0", 0xffffffff, r0, r1, c);
- TESTINST2("asrs r0, r1, #1", 0xffffffff, r0, r1, c);
- TESTINST2("asrs r0, r1, #31", 0xffffffff, r0, r1, c);
- TESTINST2("asrs r0, r1, #32", 0xffffffff, r0, r1, c);
- TESTINST2("asrs r0, r1, #0", 0x7fffffff, r0, r1, c);
- TESTINST2("asrs r0, r1, #1", 0x7fffffff, r0, r1, c);
- TESTINST2("asrs r0, r1, #31", 0x7fffffff, r0, r1, c);
- TESTINST2("asrs r0, r1, #32", 0x7fffffff, r0, r1, c);
- TESTINST2("asrs r0, r1, #16", 0x00010000, r0, r1, c);
- TESTINST2("asrs r0, r1, #17", 0x00010000, r0, r1, c);
- TESTINST2("asrs r0, r1, #18", 0x00010000, r0, r1, c);
- TESTCARRYEND
-
- printf("ROR\n");
- TESTCARRY
- TESTINST3("ror r0, r1, r2", 0x00088000, 0, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x80088000, 1, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 1, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 2, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 31, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 32, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 33, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 63, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 64, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 255, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 256, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x80088000, 256, r0, r1, r2, c);
- TESTINST3("ror r0, r1, r2", 0x00088000, 257, r0, r1, r2, c);
- TESTCARRYEND
-
- printf("RORS\n");
- TESTCARRY
- TESTINST3("rors r0, r1, r2", 0x00088000, 0, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x80088000, 0, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 1, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 2, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 31, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 32, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 33, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 63, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 64, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 255, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 256, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x80088000, 256, r0, r1, r2, c);
- TESTINST3("rors r0, r1, r2", 0x00088000, 257, r0, r1, r2, c);
- TESTCARRYEND
-
- printf("ROR immediate\n");
- TESTCARRY
- TESTINST2("ror r0, r1, #0", 0x00088000, r0, r1, c);
- TESTINST2("ror r0, r1, #1", 0x00088000, r0, r1, c);
- TESTINST2("ror r0, r1, #31", 0x00088000, r0, r1, c);
- TESTINST2("ror r0, r1, #16", 0x00010000, r0, r1, c);
- TESTINST2("ror r0, r1, #17", 0x00010000, r0, r1, c);
- TESTINST2("ror r0, r1, #18", 0x00010000, r0, r1, c);
- TESTCARRYEND
-
- printf("RORS immediate\n");
- TESTCARRY
- TESTINST2("rors r0, r1, #0", 0x00088000, r0, r1, c);
- TESTINST2("rors r0, r1, #1", 0x00088000, r0, r1, c);
- TESTINST2("rors r0, r1, #31", 0x00088000, r0, r1, c);
- TESTINST2("rors r0, r1, #16", 0x00010000, r0, r1, c);
- TESTINST2("rors r0, r1, #17", 0x00010000, r0, r1, c);
- TESTINST2("rors r0, r1, #18", 0x00010000, r0, r1, c);
- TESTCARRYEND
-
- printf("shift with barrel shifter\n");
- TESTCARRY
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 0, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 1, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 31, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 32, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 255, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 256, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
- TESTCARRYEND
-
- TESTCARRY
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 0, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 1, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 2, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 3, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 4, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 5, r0, r1, r2, r3, c);
- TESTCARRYEND
-
- TESTCARRY
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, c);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, c);
- TESTCARRYEND
-
- TESTCARRY
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
-
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, c);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, c);
- TESTCARRYEND
-
- TESTCARRY
- TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
- TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
- TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
- TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
- TESTCARRYEND
-
- printf("MUL\n");
- TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
-
- printf("MULS\n");
- TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
-
- printf("MLA\n");
- TESTINST4("mla r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
- printf("MLAS\n");
- TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
- printf("MLS\n");
- TESTINST4("mls r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
- printf("UMULL\n");
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-
- printf("SMULL\n");
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-
- printf("UMLAL\n");
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-
- printf("SMLAL\n");
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-
- printf("CLZ\n");
- TESTCARRY
- TESTINST2("clz r0, r1", 0, r0, r1, c);
- TESTINST2("clz r0, r1", 1, r0, r1, c);
- TESTINST2("clz r0, r1", 0x10, r0, r1, c);
- TESTINST2("clz r0, r1", 0xffffffff, r0, r1, c);
- TESTCARRYEND
-
- printf("extend instructions\n");
- TESTINST2("uxtb r0, r1", 0, r0, r1, 0);
- TESTINST2("uxtb r0, r1", 1, r0, r1, 0);
- TESTINST2("uxtb r0, r1", 0xff, r0, r1, 0);
- TESTINST2("uxtb r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 0, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 1, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 0xff, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 0xffffffff, r0, r1, 0);
-
- TESTINST2("uxth r0, r1", 0, r0, r1, 0);
- TESTINST2("uxth r0, r1", 1, r0, r1, 0);
- TESTINST2("uxth r0, r1", 0xffff, r0, r1, 0);
- TESTINST2("uxth r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0, r0, r1, 0);
- TESTINST2("sxth r0, r1", 1, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0x7fff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0xffff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0x10ffff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0x107fff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0xffffffff, r0, r1, 0);
-
- TESTINST2("uxtb r0, r1, ror #0", 0x000000ff, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #8", 0x000000ff, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #8", 0x0000ff00, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #16", 0x00ff0000, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #24", 0xff000000, r0, r1, 0);
-
- TESTINST2("uxtb16 r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("uxtb16 r0, r1, ror #16", 0x0000ffff, r0, r1, 0);
- TESTINST2("sxtb16 r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("sxtb16 r0, r1", 0x00ff00ff, r0, r1, 0);
- TESTINST2("sxtb16 r0, r1", 0x007f007f, r0, r1, 0);
-
- printf("------------ BFI ------------\n");
-
- /* bfi rDst, rSrc, #lsb-in-dst, #number-of-bits-to-copy */
- TESTINST2("bfi r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfi r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfi r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("bfi r0, r1, #19, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #20, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #21, #11", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfi r0, r1, #0, #32", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #1, #31", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfi r0, r1, #29, #3", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #30, #2", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #31, #1", 0xFFFFFFFF, r0, r1, 0);
-
- printf("------------ BFC ------------\n");
-
- /* bfi rDst, #lsb-in-dst, #number-of-bits-to-copy */
- TESTINST2("bfc r0, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfc r0, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfc r0, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("bfc r0, #19, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #20, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #21, #11", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfc r0, #0, #32", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #1, #31", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfc r0, #29, #3", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #30, #2", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #31, #1", 0xFFFFFFFF, r0, r1, 0);
-
- printf("------------ SBFX ------------\n");
-
- /* sbfx rDst, rSrc, #lsb, #width */
- TESTINST2("sbfx r0, r1, #0, #1", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #0, #1", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000002, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000003, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #0, #2", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #0, #2", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000002, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000003, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
-
- printf("------------ UBFX ------------\n");
-
- /* ubfx rDst, rSrc, #lsb, #width */
- TESTINST2("ubfx r0, r1, #0, #1", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #0, #1", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000002, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000003, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #0, #2", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #0, #2", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000002, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000003, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
-
- printf("------------ SMULL{B,T}{B,T} ------------\n");
- /* SMULxx rD, rN, rM */
-
- TESTINST3("smulbb r0, r1, r2", 0x00030000, 0x00040000, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x00030001, 0x00040002, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x00038001, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x00037fff, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x0003ffff, 0x0004ffff, r0, r1, r2, 0);
-
- printf("------------ SXTAB ------------\n");
- TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
-
- printf("------------ UXTAB ------------\n");
- TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
-
- printf("------------ SXTAH ------------\n");
- TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
-
- printf("------------ UXTAH ------------\n");
- TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
-
- printf("------------ PLD/PLDW (begin) ------------\n");
- /* These don't have any effect on the architected state, so,
- uh, there's no result values to check. Just _do_ some of
- them and check Valgrind's instruction decoder eats them up
- without complaining. */
- { int alocal;
- printf("pld reg +/- imm12 cases\n");
- __asm__ __volatile__( "pld [%0, #128]" : :/*in*/"r"(&alocal) );
- __asm__ __volatile__( "pld [%0, #-128]" : :/*in*/"r"(&alocal) );
- __asm__ __volatile__( "pld [r15, #-128]" : :/*in*/"r"(&alocal) );
-
- // apparently pldw is v7 only
- //__asm__ __volatile__( "pldw [%0, #128]" : :/*in*/"r"(&alocal) );
- //__asm__ __volatile__( "pldw [%0, #-128]" : :/*in*/"r"(&alocal) );
- //__asm__ __volatile__( "pldw [r15, #128]" : :/*in*/"r"(&alocal) );
-
- printf("pld reg +/- shifted reg cases\n");
- __asm__ __volatile__( "pld [%0, %1]" : : /*in*/"r"(&alocal), "r"(0) );
- __asm__ __volatile__( "pld [%0, %1, LSL #1]" : : /*in*/"r"(&alocal), "r"(0) );
- __asm__ __volatile__( "pld [%0, %1, LSR #1]" : : /*in*/"r"(&alocal), "r"(0) );
- __asm__ __volatile__( "pld [%0, %1, ASR #1]" : : /*in*/"r"(&alocal), "r"(0) );
- __asm__ __volatile__( "pld [%0, %1, ROR #1]" : : /*in*/"r"(&alocal), "r"(0) );
- __asm__ __volatile__( "pld [%0, %1, RRX]" : : /*in*/"r"(&alocal), "r"(0) );
- }
- printf("------------ PLD/PLDW (done) ------------\n");
-
printf("------------ RBIT ------------\n");
TESTINST2("rbit r0, r1", 0x00000000, r0, r1, 0);
TESTINST2("rbit r0, r1", 0xFFFFFFFF, r0, r1, 0);
@@ -1764,5 +914,30 @@
__asm__ __volatile__("nopne" ::: "memory","cc");
printf("------------ NOP (end) ------------\n");
+ printf("------------ SMMUL ------------\n");
+ TESTINST3("smmul r0, r1, r2", 0, 0, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
+
+ TESTINST3("smmulr r0, r1, r2", 0, 0, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
+
return 0;
}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/arm/v6intARM.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/arm/v6intARM.stderr.exp
diff --git a/main/none/tests/arm/v6intARM.stdout.exp b/main/none/tests/arm/v6intARM.stdout.exp
index 0cf02fa..7f500dd 100644
--- a/main/none/tests/arm/v6intARM.stdout.exp
+++ b/main/none/tests/arm/v6intARM.stdout.exp
@@ -737,745 +737,6 @@
pld reg +/- imm12 cases
pld reg +/- shifted reg cases
------------ PLD/PLDW (done) ------------
-MOV
-mov r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-cpy r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-mov r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-mov r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 0, cpsr 0x80000000 N
-movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z
-movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000 ZC
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 1, cpsr 0xa0000000 N C
-movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000 ZC
-movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 1, cpsr 0x20000000 C
-MVN
-mvn r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x00000000
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x80000000 N
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 0, cpsr 0x80000000 N
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 0, cpsr 0x00000000
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 1, cpsr 0xa0000000 N C
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 1, cpsr 0xa0000000 N C
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 1, cpsr 0x20000000 C
-ADD
-adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
-adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x00000000
-adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000
-adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000
-adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x80000000 N
-adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, carryin 0, cpsr 0x60000000 ZC
-adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x90000000 N V
-adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, carryin 0, cpsr 0x30000000 CV
-adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, carryin 0, cpsr 0x80000000 N
-ADC
-adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
-adcs r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, carryin 1, cpsr 0x00000000
-LSL
-lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 0, cpsr 0x00000000
-lsl r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 0, cpsr 0x00000000
-LSLS
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N
-lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x60000000 ZC
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x80000000 N
-lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000
-lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000
-lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 0, cpsr 0x80000000 N
-lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 0, cpsr 0x60000000 ZC
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x60000000 ZC
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 1, cpsr 0x20000000 C
-lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 1, cpsr 0x00000000
-lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 1, cpsr 0x80000000 N
-lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 1, cpsr 0x60000000 ZC
-LSL immediate
-lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 0, cpsr 0x00000000
-lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 0, cpsr 0x00000000
-lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 0, cpsr 0x00000000
-lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 0, cpsr 0x00000000
-lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 0, cpsr 0x00000000
-lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0x20000000 C
-lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 1, cpsr 0x20000000 C
-lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 1, cpsr 0x20000000 C
-lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C
-lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 1, cpsr 0x20000000 C
-lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 1, cpsr 0x20000000 C
-lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 1, cpsr 0x20000000 C
-LSLS immediate
-lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N
-lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C
-lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C
-lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 0, cpsr 0x00000000
-lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 0, cpsr 0x80000000 N
-lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 0, cpsr 0x60000000 ZC
-lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C
-lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C
-lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C
-lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C
-lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 1, cpsr 0x00000000
-lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 1, cpsr 0x80000000 N
-lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 1, cpsr 0x60000000 ZC
-LSR
-lsr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000
-lsr r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000
-lsr r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000
-lsr r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000
-lsr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000
-LSRS
-lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N
-lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x60000000 ZC
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C
-lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x60000000 ZC
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000 Z
-LSR immediate
-lsr r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-lsr r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-lsr r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000
-lsr r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000
-lsr r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000
-lsr r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000
-lsr r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000
-LSRS immediate
-lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N
-lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 0, cpsr 0x20000000 C
-lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x20000000 C
-lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x60000000 ZC
-lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000
-lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x60000000 ZC
-lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x40000000 Z
-lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C
-lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 1, cpsr 0x20000000 C
-lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 1, cpsr 0x20000000 C
-lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x60000000 ZC
-lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000
-lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x60000000 ZC
-lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x40000000 Z
-ASR
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 0, cpsr 0x00000000
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 1, cpsr 0x20000000 C
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 1, cpsr 0x20000000 C
-ASRS
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x80000000 N
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 0, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 0, cpsr 0x60000000 ZC
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 1, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 1, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 1, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 1, cpsr 0x60000000 ZC
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 1, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 1, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 1, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 1, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, carryin 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, carryin 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, carryin 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, carryin 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, carryin 0, cpsr 0x60000000 ZC
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, carryin 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, carryin 1, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, carryin 1, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, carryin 1, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, carryin 1, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, carryin 1, cpsr 0x60000000 ZC
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, carryin 1, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0xc0000000 rm 0x80000001, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xe0000000 rm 0x80000001, rn 0x00000002, carryin 0, cpsr 0x80000000 N
-ASR immediate
-asr r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-asr r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-asr r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-asr r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-asr r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000
-asr r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000
-asr r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x00000000
-asr r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x00000000
-asr r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000
-asr r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000
-asr r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000
-ASRS immediate
-asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N
-asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C
-asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000
-asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 0, cpsr 0x20000000 C
-asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x60000000 ZC
-asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x40000000 Z
-asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000
-asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x60000000 ZC
-asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x40000000 Z
-asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C
-asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 1, cpsr 0x20000000 C
-asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 1, cpsr 0x20000000 C
-asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 1, cpsr 0x60000000 ZC
-asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 1, cpsr 0x40000000 Z
-asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000
-asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x60000000 ZC
-asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x40000000 Z
-ROR
-ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x40044000 rm 0x80088000, rn 0x00000001, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 0, cpsr 0x00000000
-ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x40044000 rm 0x80088000, rn 0x00000001, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 1, cpsr 0x20000000 C
-ror r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 1, cpsr 0x20000000 C
-RORS
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000000, carryin 0, cpsr 0x80000000 N
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 0, cpsr 0x80000000 N
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 0, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 1, cpsr 0x20000000 C
-rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 1, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 1, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 1, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 1, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 1, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 1, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 1, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 1, cpsr 0x00000000
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 1, cpsr 0x20000000 C
-rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 1, cpsr 0x00000000
-ROR immediate
-ror r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 0, cpsr 0x00000000
-ror r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 0, cpsr 0x00000000
-ror r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 0, cpsr 0x00000000
-ror r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000
-ror r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 0, cpsr 0x00000000
-ror r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 0, cpsr 0x00000000
-ror r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 1, cpsr 0x20000000 C
-ror r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 1, cpsr 0x20000000 C
-ror r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 1, cpsr 0x20000000 C
-ror r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x20000000 C
-ror r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 1, cpsr 0x20000000 C
-ror r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 1, cpsr 0x20000000 C
-RORS immediate
-rors r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 0, cpsr 0x00000000
-rors r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 0, cpsr 0x00000000
-rors r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 0, cpsr 0x00000000
-rors r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000
-rors r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 0, cpsr 0xa0000000 N C
-rors r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 0, cpsr 0x00000000
-rors r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 1, cpsr 0x20000000 C
-rors r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 1, cpsr 0x00000000
-rors r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 1, cpsr 0x00000000
-rors r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000
-rors r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 1, cpsr 0xa0000000 N C
-rors r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 1, cpsr 0x00000000
-shift with barrel shifter
-add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000000, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x3fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x0000001f, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x00000020, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x000000ff, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000100, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000
-add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000000, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x3fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000001, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x0000001f, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x00000020, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x000000ff, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000100, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x00000008 rm 0x00000000, rn 0x00000008 rs 0x00000000, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x00000004 rm 0x00000000, rn 0x00000008 rs 0x00000001, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x00000002 rm 0x00000000, rn 0x00000008 rs 0x00000002, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000008 rs 0x00000003, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000004, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000005, carryin 0, cpsr 0x00000000
-add r0, r1, r2, asr r3 :: rd 0x00000008 rm 0x00000000, rn 0x00000008 rs 0x00000000, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x00000004 rm 0x00000000, rn 0x00000008 rs 0x00000001, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x00000002 rm 0x00000000, rn 0x00000008 rs 0x00000002, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000008 rs 0x00000003, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000004, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000005, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 0, cpsr 0x00000000
-add r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 0, cpsr 0x00000000
-add r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 0, cpsr 0x00000000
-add r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 0, cpsr 0x00000000
-add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 0, cpsr 0x00000000
-add r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 0, cpsr 0x00000000
-add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 0, cpsr 0x00000000
-add r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 0, cpsr 0x00000000
-add r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 0, cpsr 0x00000000
-add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 1, cpsr 0x20000000 C
-add r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 1, cpsr 0x20000000 C
-adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N
-adds r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x80000000 N
-adds r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x80000000 N
-adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x40000000 Z
-adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x40000000 Z
-adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x80000000 N
-adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N
-adds r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-adds r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000
-adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x40000000 Z
-adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x40000000 Z
-adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x80000000 N
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 0, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 0, cpsr 0x80000000 N
-adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 0, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 0, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 0, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 0, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 0, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 0, cpsr 0x80000000 N
-adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 0, cpsr 0x00000000
-adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x80000000 N
-adds r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x80000000 N
-adds r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x80000000 N
-adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x40000000 Z
-adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x40000000 Z
-adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x80000000 N
-adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x80000000 N
-adds r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x00000000
-adds r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x00000000
-adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x40000000 Z
-adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x40000000 Z
-adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x80000000 N
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 1, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 1, cpsr 0x80000000 N
-adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 1, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 1, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 1, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 1, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 1, cpsr 0x00000000
-adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 1, cpsr 0x80000000 N
-adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 1, cpsr 0x00000000
-adcs r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N
-adcs r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N
-adcs r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x80000000 N
-adcs r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-adcs r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x60000000 ZC
-adcs r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x60000000 ZC
-adcs r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x80000000 N
-adcs r0, r1, r2, lsr r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x90000000 N V
-MUL
-mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000
-mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000
-mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000
-mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000
-mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000
-mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000
-MULS
-muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
-muls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
-muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x40000000 Z
-muls r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000
-muls r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000
-muls r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x80000000 N
-MLA
-mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-mla r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-mla r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000
-MLAS
-mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-mlas r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-mlas r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-mlas r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x80000000 N
-MLS
-mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-mls r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-mls r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-mls r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000
-mls r0, r1, r2, r3 :: rd 0x00020000 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000
-UMULL
-umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000
-umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-umull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000
-umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000
-umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000 Z
-umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000 Z
-umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000 Z
-umulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-umulls r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000
-umulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x80000000 N
-SMULL
-smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000
-smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-smull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000
-smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000
-smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000 Z
-smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000 Z
-smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000 Z
-smulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-smulls r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000
-smulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000
-UMLAL
-umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000
-umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-umlal r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000
-umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000
-umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000 Z
-umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x80000000 N
-umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000 Z
-umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000 Z
-umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-umlals r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000
-umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x80000000 N
-SMLAL
-smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000
-smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000
-smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-smlal r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000
-smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000
-smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000 Z
-smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000
-smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x80000000 N
-smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000 Z
-smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000 Z
-smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000
-smlals r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000
-smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000
-CLZ
-clz r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 0, cpsr 0x00000000
-clz r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 0, cpsr 0x00000000
-clz r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 0, cpsr 0x00000000
-clz r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000
-clz r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 1, cpsr 0x20000000 C
-clz r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 1, cpsr 0x20000000 C
-clz r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 1, cpsr 0x20000000 C
-clz r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x20000000 C
-extend instructions
-uxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-uxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-uxtb r0, r1 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000
-uxtb r0, r1 :: rd 0x000000ff rm 0xffffffff, carryin 0, cpsr 0x00000000
-sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, carryin 0, cpsr 0x00000000
-sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-uxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-uxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-uxth r0, r1 :: rd 0x0000ffff rm 0x0000ffff, carryin 0, cpsr 0x00000000
-uxth r0, r1 :: rd 0x0000ffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-sxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-sxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, carryin 0, cpsr 0x00000000
-sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, carryin 0, cpsr 0x00000000
-sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, carryin 0, cpsr 0x00000000
-sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, carryin 0, cpsr 0x00000000
-sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000
-uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, carryin 0, cpsr 0x00000000
-uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, carryin 0, cpsr 0x00000000
-uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, carryin 0, cpsr 0x00000000
-uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, carryin 0, cpsr 0x00000000
-uxtb16 r0, r1 :: rd 0x00ff00ff rm 0xffffffff, carryin 0, cpsr 0x00000000
-uxtb16 r0, r1, ror #16 :: rd 0x00ff0000 rm 0x0000ffff, carryin 0, cpsr 0x00000000
-sxtb16 r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-sxtb16 r0, r1 :: rd 0xffffffff rm 0x00ff00ff, carryin 0, cpsr 0x00000000
-sxtb16 r0, r1 :: rd 0x007f007f rm 0x007f007f, carryin 0, cpsr 0x00000000
------------- BFI ------------
-bfi r0, r1, #0, #11 :: rd 0x555552aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-bfi r0, r1, #1, #11 :: rd 0x55555555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-bfi r0, r1, #2, #11 :: rd 0x55554aa9 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-bfi r0, r1, #19, #11 :: rd 0x7ffd5555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfi r0, r1, #20, #11 :: rd 0x7ff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfi r0, r1, #21, #11 :: rd 0xfff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfi r0, r1, #0, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfi r0, r1, #1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfi r0, r1, #29, #3 :: rd 0xf5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfi r0, r1, #30, #2 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfi r0, r1, #31, #1 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000
------------- BFC ------------
-bfc r0, #0, #11 :: rd 0x55555000 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-bfc r0, #1, #11 :: rd 0x55555001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-bfc r0, #2, #11 :: rd 0x55554001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-bfc r0, #19, #11 :: rd 0x40055555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfc r0, #20, #11 :: rd 0x00055555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfc r0, #21, #11 :: rd 0x00155555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfc r0, #0, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfc r0, #1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfc r0, #29, #3 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfc r0, #30, #2 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000
-bfc r0, #31, #1 :: rd 0x55555555 rm 0xffffffff, carryin 0, cpsr 0x00000000
------------- SBFX ------------
-sbfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #0, #1 :: rd 0xffffffff rm 0x00000001, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000002, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000003, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #1, #11 :: rd 0xfffffd55 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #31, #1 :: rd 0xffffffff rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-sbfx r0, r1, #30, #2 :: rd 0xfffffffe rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
------------- UBFX ------------
-ubfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #0, #1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #1, #11 :: rd 0x00000555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #31, #1 :: rd 0x00000001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
-ubfx r0, r1, #30, #2 :: rd 0x00000002 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000
------------- SMULL{B,T}{B,T} ------------
-smulbb r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00040000, carryin 0, cpsr 0x00000000
-smulbb r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00040002, carryin 0, cpsr 0x00000000
-smulbb r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x00047fff, carryin 0, cpsr 0x00000000
-smulbb r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x00047fff, carryin 0, cpsr 0x00000000
-smulbb r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0x0004ffff, carryin 0, cpsr 0x00000000
------------- SXTAB ------------
-sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
-sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
-sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
-sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
------------- UXTAB ------------
-uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-uxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
-uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
-uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
-uxtab r0, r1, r2, ROR #0 :: rd 0x314159c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000
------------- SXTAH ------------
-sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-sxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-sxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000
-sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000
-sxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000
-sxtah r0, r1, r2, ROR #0 :: rd 0x3140f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000
------------- UXTAH ------------
-uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-uxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-uxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000
-uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000
-uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000
-uxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000
-uxtah r0, r1, r2, ROR #0 :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000
------------- PLD/PLDW (begin) ------------
-pld reg +/- imm12 cases
-pld reg +/- shifted reg cases
------------- PLD/PLDW (done) ------------
------------ RBIT ------------
rbit r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
rbit r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000
@@ -1538,3 +799,26 @@
nopeq
nopne
------------ NOP (end) ------------
+------------ SMMUL ------------
+smmul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0x00000000 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0x048e8c61 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0xfd764d51 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0x0657af1f rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0xffe5afbd rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000
+smmul r0, r1, r2 :: rd 0xffc528bc rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0x00000001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0x048e8c61 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0xfd764d52 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0x0657af1f rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0xffe5afbd rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000
+smmulr r0, r1, r2 :: rd 0xffc528bd rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000
diff --git a/main/none/tests/arm/v6intARM.vgtest b/main/none/tests/arm/v6intARM.vgtest
index 0deef0a..b2489f2 100644
--- a/main/none/tests/arm/v6intARM.vgtest
+++ b/main/none/tests/arm/v6intARM.vgtest
@@ -1,4 +1,2 @@
prog: v6intARM
vgopts: -q
-prog: v6intARM
-vgopts: -q
diff --git a/main/none/tests/arm/v6intThumb.c b/main/none/tests/arm/v6intThumb.c
index 48e9e5a..350ec0f 100644
--- a/main/none/tests/arm/v6intThumb.c
+++ b/main/none/tests/arm/v6intThumb.c
@@ -5869,5408 +5869,30 @@
// plus whatever stuff we can throw in from the old ARM test program
old_main();
- return 0;
-}
+ printf("------------ SMMUL ------------\n");
+ TESTINST3("smmul r0, r1, r2", 0, 0, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
+ TESTINST3("smmul r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-/* How to compile:
- gcc -O -g -Wall -mcpu=cortex-a8 -o testarmv6int testarmv6int.c
-*/
-
-#include <stdio.h>
-
-static int gen_cvin(cvin)
-{
- int r = ((cvin & 2) ? (1<<29) : 0) | ((cvin & 1) ? (1<<28) : 0);
- r |= (1 << 31) | (1 << 30);
- return r;
-}
-
-/* test macros to generate and output the result of a single instruction */
-
-
-// 1 registers in the insn, zero args: rD = op()
-#define TESTINST1(instruction, RD, cvin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_f, %2;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (gen_cvin(cvin)) \
- : #RD, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, \
- cvin, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-
-
-// 1 registers in the insn, one args: rD = op(rD)
-#define TESTINST1x(instruction, RDval, RD, cvin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_f, %2;" \
- "mov " #RD ",%3;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (gen_cvin(cvin)), "r"(RDval) \
- : #RD, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, \
- cvin, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-// 2 registers in the insn, one arg: rD = op(rM)
-#define TESTINST2(instruction, RMval, RD, RM, cvin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_f, %3;" \
- "mov " #RM ",%2;" \
- /* set #RD to 0x55555555 so we can see which parts get overwritten */ \
- "mov " #RD ", #0x55" "\n\t" \
- "orr " #RD "," #RD "," #RD ", LSL #8" "\n\t" \
- "orr " #RD "," #RD "," #RD ", LSL #16" "\n\t" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (gen_cvin(cvin)) \
- : #RD, #RM, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, RMval, \
- cvin, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-
-// 2 registers in the insn, two args: rD = op(rD, rM)
-#define TESTINST2x(instruction, RDval, RMval, RD, RM, cvin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_f, %3;" \
- "mov " #RM ",%2;" \
- "mov " #RD ",%4;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (gen_cvin(cvin)), "r"(RDval) \
- : #RD, #RM, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, RMval, \
- cvin, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-
-
-#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, cvin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_f, %4;" \
- "mov " #RM ",%2;" \
- "mov " #RN ",%3;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (RNval), "r" (gen_cvin(cvin)) \
- : #RD, #RM, #RN, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, RMval, RNval, \
- cvin, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, cvin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_f, %5;" \
- "mov " #RM ",%2;" \
- "mov " #RN ",%3;" \
- "mov " #RS ",%4;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (RNval), "r" (RSval), "r" (gen_cvin(cvin)) \
- : #RD, #RM, #RN, #RS, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, RMval, RNval, RSval, \
- cvin, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-#define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, cvin) \
-{ \
- unsigned int out; \
- unsigned int out2; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_f, %7;" \
- "mov " #RD ",%3;" \
- "mov " #RD2 ",%4;" \
- "mov " #RM ",%5;" \
- "mov " #RS ",%6;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mov %1," #RD2 ";" \
- "mrs %2,cpsr;" \
- : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \
- : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (gen_cvin(cvin)) \
- : #RD, #RD2, #RM, #RS, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
- instruction, out, out2, RMval, RSval, \
- cvin, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ' \
- ); \
-}
-
-/* helpers */
-#define NOCARRY { int cv = 0; {
-#define TESTCARRY { int cv = 0; for (cv = 0; cv < 4; cv++) {
-#define TESTCARRYEND }}
-
-////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////
-///////////////////////////////////////////////////////////
-///////////////////////////////////////////////////////////
-
-static int old_main(void)
-{
-
- printf("MOV\n");
- TESTINST2("mov r0, r1", 1, r0, r1, 0);
- TESTINST2("cpy r0, r1", 1, r0, r1, 0);
- TESTINST2("mov r0, #0", 0, r0, r1, 0);
- TESTINST2("mov r0, #1", 0, r0, r1, 0);
- TESTCARRY
- TESTINST2("movs r0, r1", 1, r0, r1, cv);
- TESTINST2("movs r0, r1", 0, r0, r1, cv);
- TESTINST2("movs r0, r1", 0x80000000, r0, r1, cv);
- TESTINST2("movs r0, #0", 0, r0, r1, cv);
- TESTINST2("movs r0, #1", 0, r0, r1, cv);
- TESTCARRYEND
-
- printf("MVN\n");
- TESTINST2("mvn r0, r1", 1, r0, r1, 0);
- TESTCARRY
- TESTINST2("mvns r0, r1", 1, r0, r1, cv);
- TESTINST2("mvns r0, r1", 0, r0, r1, cv);
- TESTINST2("mvns r0, r1", 0x80000000, r0, r1, cv);
- TESTCARRYEND
-
- printf("ADD\n");
- TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 1, -1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0x80000000, -1, r0, r1, r2, 0);
- TESTINST3("adds r0, r1, r2", 0x80000000, 0, r0, r1, r2, 0);
-
- printf("ADC\n");
- TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 1);
-
- printf("LSL\n");
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
-
- TESTINST3("lsl r0, r1, r2", 0x1, 0, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0x1, 1, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0x1, 31, r0, r1, r2, 0);
- TESTINST3("lsl r0, r1, r2", 0x2, 31, r0, r1, r2, 0);
-
- printf("LSLS\n");
- TESTCARRY
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0xffffffff, 256, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0x1, 0, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0x1, 1, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0x1, 31, r0, r1, r2, cv);
- TESTINST3("lsls r0, r1, r2", 0x2, 31, r0, r1, r2, cv);
- TESTCARRYEND
-
- printf("LSL immediate\n");
- TESTCARRY
- TESTINST2("lsl r0, r1, #0", 0xffffffff, r0, r1, cv);
- TESTINST2("lsl r0, r1, #1", 0xffffffff, r0, r1, cv);
- TESTINST2("lsl r0, r1, #31", 0xffffffff, r0, r1, cv);
- TESTINST2("lsl r0, r1, #0", 0x1, r0, r1, cv);
- TESTINST2("lsl r0, r1, #1", 0x1, r0, r1, cv);
- TESTINST2("lsl r0, r1, #31", 0x1, r0, r1, cv);
- TESTINST2("lsl r0, r1, #31", 0x2, r0, r1, cv);
- TESTCARRYEND
-
- printf("LSLS immediate\n");
- TESTCARRY
- TESTINST2("lsls r0, r1, #0", 0xffffffff, r0, r1, cv);
- TESTINST2("lsls r0, r1, #1", 0xffffffff, r0, r1, cv);
- TESTINST2("lsls r0, r1, #31", 0xffffffff, r0, r1, cv);
- TESTINST2("lsls r0, r1, #0", 0x1, r0, r1, cv);
- TESTINST2("lsls r0, r1, #1", 0x1, r0, r1, cv);
- TESTINST2("lsls r0, r1, #31", 0x1, r0, r1, cv);
- TESTINST2("lsls r0, r1, #31", 0x2, r0, r1, cv);
- TESTCARRYEND
-
- printf("LSR\n");
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
- TESTINST3("lsr r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
-
- printf("LSRS\n");
- TESTCARRY
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv);
- TESTINST3("lsrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv);
- TESTCARRYEND
-
- printf("LSR immediate\n");
- TESTINST2("lsr r0, r1, #0", 0xffffffff, r0, r1, 0);
- TESTINST2("lsr r0, r1, #1", 0xffffffff, r0, r1, 0);
- TESTINST2("lsr r0, r1, #31", 0xffffffff, r0, r1, 0);
- TESTINST2("lsr r0, r1, #32", 0xffffffff, r0, r1, 0);
- TESTINST2("lsr r0, r1, #16", 0x00010000, r0, r1, 0);
- TESTINST2("lsr r0, r1, #17", 0x00010000, r0, r1, 0);
- TESTINST2("lsr r0, r1, #18", 0x00010000, r0, r1, 0);
-
- printf("LSRS immediate\n");
- TESTCARRY
- TESTINST2("lsrs r0, r1, #0", 0xffffffff, r0, r1, cv);
- TESTINST2("lsrs r0, r1, #1", 0xffffffff, r0, r1, cv);
- TESTINST2("lsrs r0, r1, #31", 0xffffffff, r0, r1, cv);
- TESTINST2("lsrs r0, r1, #32", 0xffffffff, r0, r1, cv);
- TESTINST2("lsrs r0, r1, #16", 0x00010000, r0, r1, cv);
- TESTINST2("lsrs r0, r1, #17", 0x00010000, r0, r1, cv);
- TESTINST2("lsrs r0, r1, #18", 0x00010000, r0, r1, cv);
- TESTCARRYEND
-
- printf("ASR\n");
- TESTCARRY
- TESTINST3("asr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0xffffffff, 256, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, cv);
- TESTINST3("asr r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, cv);
- TESTCARRYEND
-
- printf("ASRS\n");
- TESTCARRY
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0xffffffff, 256, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, cv);
- TESTCARRYEND
-
- TESTCARRY
- TESTINST3("asrs r0, r1, r2", 0x8, 0, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x8, 1, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x8, 2, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x8, 3, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x8, 4, r0, r1, r2, cv);
- TESTINST3("asrs r0, r1, r2", 0x8, 5, r0, r1, r2, cv);
- TESTCARRYEND
-
- TESTINST3("asrs r0, r1, r2", 0x80000001, 1, r0, r1, r2, 0);
- TESTINST3("asrs r0, r1, r2", 0x80000001, 2, r0, r1, r2, 0);
-
- printf("ASR immediate\n");
- TESTINST2("asr r0, r1, #0", 0xffffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #1", 0xffffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #31", 0xffffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #32", 0xffffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #0", 0x7fffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #1", 0x7fffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #31", 0x7fffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #32", 0x7fffffff, r0, r1, 0);
- TESTINST2("asr r0, r1, #16", 0x00010000, r0, r1, 0);
- TESTINST2("asr r0, r1, #17", 0x00010000, r0, r1, 0);
- TESTINST2("asr r0, r1, #18", 0x00010000, r0, r1, 0);
-
- printf("ASRS immediate\n");
- TESTCARRY
- TESTINST2("asrs r0, r1, #0", 0xffffffff, r0, r1, cv);
- TESTINST2("asrs r0, r1, #1", 0xffffffff, r0, r1, cv);
- TESTINST2("asrs r0, r1, #31", 0xffffffff, r0, r1, cv);
- TESTINST2("asrs r0, r1, #32", 0xffffffff, r0, r1, cv);
- TESTINST2("asrs r0, r1, #0", 0x7fffffff, r0, r1, cv);
- TESTINST2("asrs r0, r1, #1", 0x7fffffff, r0, r1, cv);
- TESTINST2("asrs r0, r1, #31", 0x7fffffff, r0, r1, cv);
- TESTINST2("asrs r0, r1, #32", 0x7fffffff, r0, r1, cv);
- TESTINST2("asrs r0, r1, #16", 0x00010000, r0, r1, cv);
- TESTINST2("asrs r0, r1, #17", 0x00010000, r0, r1, cv);
- TESTINST2("asrs r0, r1, #18", 0x00010000, r0, r1, cv);
- TESTCARRYEND
-
-#if 0
- printf("ROR\n");
- TESTCARRY
- TESTINST3("ror r0, r1, r2", 0x00088000, 0, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x80088000, 1, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 1, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 2, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 31, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 32, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 33, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 63, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 64, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 255, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 256, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x80088000, 256, r0, r1, r2, cv);
- TESTINST3("ror r0, r1, r2", 0x00088000, 257, r0, r1, r2, cv);
- TESTCARRYEND
-
- printf("RORS\n");
- TESTCARRY
- TESTINST3("rors r0, r1, r2", 0x00088000, 0, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x80088000, 0, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 1, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 2, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 31, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 32, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 33, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 63, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 64, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 255, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 256, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x80088000, 256, r0, r1, r2, cv);
- TESTINST3("rors r0, r1, r2", 0x00088000, 257, r0, r1, r2, cv);
- TESTCARRYEND
-
- printf("ROR immediate\n");
- TESTCARRY
- TESTINST2("ror r0, r1, #0", 0x00088000, r0, r1, cv);
- TESTINST2("ror r0, r1, #1", 0x00088000, r0, r1, cv);
- TESTINST2("ror r0, r1, #31", 0x00088000, r0, r1, cv);
- TESTINST2("ror r0, r1, #16", 0x00010000, r0, r1, cv);
- TESTINST2("ror r0, r1, #17", 0x00010000, r0, r1, cv);
- TESTINST2("ror r0, r1, #18", 0x00010000, r0, r1, cv);
- TESTCARRYEND
-
- printf("RORS immediate\n");
- TESTCARRY
- TESTINST2("rors r0, r1, #0", 0x00088000, r0, r1, cv);
- TESTINST2("rors r0, r1, #1", 0x00088000, r0, r1, cv);
- TESTINST2("rors r0, r1, #31", 0x00088000, r0, r1, cv);
- TESTINST2("rors r0, r1, #16", 0x00010000, r0, r1, cv);
- TESTINST2("rors r0, r1, #17", 0x00010000, r0, r1, cv);
- TESTINST2("rors r0, r1, #18", 0x00010000, r0, r1, cv);
- TESTCARRYEND
-#endif
-#if 0
- printf("shift with barrel shifter\n");
- TESTCARRY
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 0, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 1, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 31, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 32, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 255, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x7fffffff, 256, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
- TESTCARRYEND
-
- TESTCARRY
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 0, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 1, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 2, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 3, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 4, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, asr r3", 0, 0x8, 5, r0, r1, r2, r3, cv);
- TESTCARRYEND
-
- TESTCARRY
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, cv);
- TESTINST4("add r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, cv);
- TESTCARRYEND
-#endif
-#if 0
- TESTCARRY
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
-
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, cv);
- TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, cv);
- TESTCARRYEND
-#endif
-
-#if 0
- TESTCARRY
- TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
- TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
- TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
- TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
- TESTCARRYEND
-#endif
-
- printf("MUL\n");
- TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
-
-#if 0
- printf("MULS\n");
- TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
-#endif
-
- printf("MLA\n");
- TESTINST4("mla r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
-#if 0
- printf("MLAS\n");
- TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-#endif
-
- printf("MLS\n");
- TESTINST4("mls r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
- printf("UMULL\n");
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#if 0
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
- printf("SMULL\n");
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#if 0
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
-
-#if 0
- printf("UMLAL\n");
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
-#if 0
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
-#if 0
- printf("SMLAL\n");
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
-#if 0
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
- printf("CLZ\n");
- TESTCARRY
- TESTINST2("clz r0, r1", 0, r0, r1, cv);
- TESTINST2("clz r0, r1", 1, r0, r1, cv);
- TESTINST2("clz r0, r1", 0x10, r0, r1, cv);
- TESTINST2("clz r0, r1", 0xffffffff, r0, r1, cv);
- TESTCARRYEND
-
- printf("extend instructions\n");
- TESTINST2("uxtb r0, r1", 0, r0, r1, 0);
- TESTINST2("uxtb r0, r1", 1, r0, r1, 0);
- TESTINST2("uxtb r0, r1", 0xff, r0, r1, 0);
- TESTINST2("uxtb r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 0, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 1, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 0xff, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 0xffffffff, r0, r1, 0);
-
- TESTINST2("uxth r0, r1", 0, r0, r1, 0);
- TESTINST2("uxth r0, r1", 1, r0, r1, 0);
- TESTINST2("uxth r0, r1", 0xffff, r0, r1, 0);
- TESTINST2("uxth r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0, r0, r1, 0);
- TESTINST2("sxth r0, r1", 1, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0x7fff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0xffff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0x10ffff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0x107fff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0xffffffff, r0, r1, 0);
-
- TESTINST2("uxtb r0, r1, ror #0", 0x000000ff, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #8", 0x000000ff, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #8", 0x0000ff00, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #16", 0x00ff0000, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #24", 0xff000000, r0, r1, 0);
-#if 0
- TESTINST2("uxtb16 r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("uxtb16 r0, r1, ror #16", 0x0000ffff, r0, r1, 0);
- TESTINST2("sxtb16 r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("sxtb16 r0, r1", 0x00ff00ff, r0, r1, 0);
- TESTINST2("sxtb16 r0, r1", 0x007f007f, r0, r1, 0);
-#endif
- printf("------------ BFI ------------\n");
-
- /* bfi rDst, rSrc, #lsb-in-dst, #number-of-bits-to-copy */
- TESTINST2("bfi r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfi r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfi r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("bfi r0, r1, #19, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #20, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #21, #11", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfi r0, r1, #0, #32", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #1, #31", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfi r0, r1, #29, #3", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #30, #2", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #31, #1", 0xFFFFFFFF, r0, r1, 0);
-
- printf("------------ BFC ------------\n");
-
- /* bfi rDst, #lsb-in-dst, #number-of-bits-to-copy */
- TESTINST2("bfc r0, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfc r0, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfc r0, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("bfc r0, #19, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #20, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #21, #11", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfc r0, #0, #32", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #1, #31", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfc r0, #29, #3", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #30, #2", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #31, #1", 0xFFFFFFFF, r0, r1, 0);
-
- printf("------------ SBFX ------------\n");
-
- /* sbfx rDst, rSrc, #lsb, #width */
- TESTINST2("sbfx r0, r1, #0, #1", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #0, #1", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000002, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000003, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #0, #2", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #0, #2", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000002, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000003, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
-
- printf("------------ UBFX ------------\n");
-
- /* ubfx rDst, rSrc, #lsb, #width */
- TESTINST2("ubfx r0, r1, #0, #1", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #0, #1", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000002, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000003, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #0, #2", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #0, #2", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000002, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000003, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
-
- printf("------------ SMULL{B,T}{B,T} ------------\n");
- /* SMULxx rD, rN, rM */
-
- TESTINST3("smulbb r0, r1, r2", 0x00030000, 0x00040000, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x00030001, 0x00040002, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x00038001, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x00037fff, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x0003ffff, 0x0004ffff, r0, r1, r2, 0);
-
- printf("------------ SXTAB ------------\n");
- TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
-#if 0
- printf("------------ SXTAB16 ------------\n");
- TESTINST3("sxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("sxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("sxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("sxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("sxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
-#endif
- printf("------------ UXTAB ------------\n");
- TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
-#if 0
- printf("------------ UXTAB16 ------------\n");
- TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182899,
- r0, r1, r2, 0);
-#endif
- printf("------------ SXTAH ------------\n");
- TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
-
- printf("------------ UXTAH ------------\n");
- TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819,
- r0, r1, r2, 0);
-
- TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819,
- r0, r1, r2, 0);
-#if 0
- printf("------------ PLD/PLDW (begin) ------------\n");
- /* These don't have any effect on the architected state, so,
- uh, there's no result values to check. Just _do_ some of
- them and check Valgrind's instruction decoder eats them up
- without complaining. */
- { int alocal;
- printf("pld reg +/- imm12 cases\n");
- __asm__ __volatile__( "pld [%0, #128]" : :/*in*/"r"(&alocal) );
- __asm__ __volatile__( "pld [%0, #-128]" : :/*in*/"r"(&alocal) );
- __asm__ __volatile__( "pld [r15, #-128]" : :/*in*/"r"(&alocal) );
-
- // apparently pldw is v7 only
- //__asm__ __volatile__( "pldw [%0, #128]" : :/*in*/"r"(&alocal) );
- //__asm__ __volatile__( "pldw [%0, #-128]" : :/*in*/"r"(&alocal) );
- //__asm__ __volatile__( "pldw [r15, #128]" : :/*in*/"r"(&alocal) );
-
- printf("pld reg +/- shifted reg cases\n");
- __asm__ __volatile__( "pld [%0, %1]" : : /*in*/"r"(&alocal), "r"(0) );
- __asm__ __volatile__( "pld [%0, %1, LSL #1]" : : /*in*/"r"(&alocal), "r"(0) );
-#if 0
- __asm__ __volatile__( "pld [%0, %1, LSR #1]" : : /*in*/"r"(&alocal), "r"(0) );
- __asm__ __volatile__( "pld [%0, %1, ASR #1]" : : /*in*/"r"(&alocal), "r"(0) );
- __asm__ __volatile__( "pld [%0, %1, ROR #1]" : : /*in*/"r"(&alocal), "r"(0) );
- __asm__ __volatile__( "pld [%0, %1, RRX]" : : /*in*/"r"(&alocal), "r"(0) );
-#endif
- }
- printf("------------ PLD/PLDW (done) ------------\n");
-#endif
-
- return 0;
-}
-
-
-////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////
-///////////////////////////////////////////////////////////
-///////////////////////////////////////////////////////////
-
-
-int main ( void )
-{
- // 16 bit instructions
-
- printf("CMP-16 0x10a\n");
- TESTCARRY
- TESTINST3("cmp r3, r6", 0, 0, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmp r3, r6", 1, 0, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmp r3, r6", 0, 1, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmp r3, r6", -1, 0, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmp r3, r6", 0, -1, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmp r3, r6", 0, 0x80000000, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmp r3, r6", 0x80000000, 0, r6/*fake*/, r3, r6, 0);
- TESTCARRYEND
-
- printf("CMN-16 0x10a\n");
- TESTCARRY
- TESTINST3("cmn r3, r6", 0, 0, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmn r3, r6", 1, 0, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmn r3, r6", 0, 1, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmn r3, r6", -1, 0, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmn r3, r6", 0, -1, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmn r3, r6", 0, 0x80000000, r6/*fake*/, r3, r6, 0);
- TESTINST3("cmn r3, r6", 0x80000000, 0, r6/*fake*/, r3, r6, 0);
- TESTCARRYEND
-
- printf("TST-16 0x108\n");
- TESTCARRY
- TESTINST3("tst r3, r6", 0, 0, r6/*fake*/, r3, r6, cv);
- TESTINST3("tst r3, r6", 1, 0, r6/*fake*/, r3, r6, cv);
- TESTINST3("tst r3, r6", 0, 1, r6/*fake*/, r3, r6, cv);
- TESTINST3("tst r3, r6", 1, 1, r6/*fake*/, r3, r6, cv);
- TESTINST3("tst r3, r6", -1, 0, r6/*fake*/, r3, r6, cv);
- TESTINST3("tst r3, r6", 0, -1, r6/*fake*/, r3, r6, cv);
- TESTINST3("tst r3, r6", -1, -1, r6/*fake*/, r3, r6, cv);
- TESTCARRYEND
-
- printf("NEGS-16 0x109\n");
- TESTINST2("negs r0, r1", 1, r0, r1, 0);
- TESTCARRY
- TESTINST2("negs r0, r1", 1, r0, r1, cv);
- TESTINST2("negs r0, r1", 0, r0, r1, cv);
- TESTINST2("negs r0, r1", 0x80000000, r0, r1, cv);
- TESTINST2("negs r0, r1", 0x80000001, r0, r1, cv);
- TESTINST2("negs r0, r1", 0xFFFFFFFF, r0, r1, cv);
- TESTINST2("negs r0, r1", 0x7FFFFFFF, r0, r1, cv);
- TESTCARRYEND
-
- printf("MVNS-16 0x10F\n");
- TESTINST2("mvns r0, r1", 1, r0, r1, 0);
- TESTCARRY
- TESTINST2("mvns r0, r1", 1, r0, r1, cv);
- TESTINST2("mvns r0, r1", 0, r0, r1, cv);
- TESTINST2("mvns r0, r1", 0x80000000, r0, r1, cv);
- TESTINST2("mvns r0, r1", 0x80000001, r0, r1, cv);
- TESTINST2("mvns r0, r1", 0xFFFFFFFF, r0, r1, cv);
- TESTINST2("mvns r0, r1", 0x7FFFFFFF, r0, r1, cv);
- TESTCARRYEND
-
- printf("ORRS-16 0x10C\n");
- TESTCARRY
- TESTINST2x("orrs r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
- TESTINST2x("orrs r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
- TESTINST2x("orrs r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
- TESTINST2x("orrs r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
- TESTINST2x("orrs r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
- TESTINST2x("orrs r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
- TESTINST2x("orrs r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
- TESTCARRYEND
-
- printf("ANDS-16 0x100\n");
- TESTCARRY
- TESTINST2x("ands r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
- TESTINST2x("ands r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
- TESTINST2x("ands r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
- TESTINST2x("ands r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
- TESTINST2x("ands r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
- TESTINST2x("ands r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
- TESTINST2x("ands r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
- TESTCARRYEND
-
- printf("EORS-16 0x101\n");
- TESTCARRY
- TESTINST2x("eors r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
- TESTINST2x("eors r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
- TESTINST2x("eors r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
- TESTINST2x("eors r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
- TESTINST2x("eors r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
- TESTINST2x("eors r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
- TESTINST2x("eors r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
- TESTCARRYEND
-
- printf("MULS-16 0x10d\n");
- TESTCARRY
- TESTINST2x("muls r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
- TESTINST2x("muls r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
- TESTINST2x("muls r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
- TESTINST2x("muls r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
- TESTINST2x("muls r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
- TESTINST2x("muls r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
- TESTINST2x("muls r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
- TESTCARRYEND
-
- printf("BICS-16 0x10E\n");
- TESTCARRY
- TESTINST2x("bics r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
- TESTINST2x("bics r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
- TESTINST2x("bics r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
- TESTINST2x("bics r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
- TESTINST2x("bics r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
- TESTINST2x("bics r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
- TESTINST2x("bics r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
- TESTCARRYEND
-
- printf("ADCS-16 0x105\n");
- TESTCARRY
- TESTINST2x("adcs r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
- TESTINST2x("adcs r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
- TESTINST2x("adcs r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
- TESTINST2x("adcs r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
- TESTINST2x("adcs r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
- TESTINST2x("adcs r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
- TESTINST2x("adcs r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
- TESTCARRYEND
-
- printf("SBCS-16 0x100\n");
- TESTCARRY
- TESTINST2x("sbcs r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
- TESTINST2x("sbcs r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
- TESTINST2x("sbcs r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
- TESTINST2x("sbcs r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
- TESTINST2x("sbcs r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
- TESTINST2x("sbcs r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
- TESTINST2x("sbcs r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
- TESTCARRYEND
-
- printf("UXTB-16 0x2CB\n");
- TESTCARRY
- TESTINST2("uxtb r1, r2", 0x31415927, r1, r2, cv);
- TESTINST2("uxtb r1, r2", 0x31415997, r1, r2, cv);
- TESTCARRYEND
-
- printf("SXTB-16 0x2C9\n");
- TESTCARRY
- TESTINST2("sxtb r1, r2", 0x31415927, r1, r2, cv);
- TESTINST2("sxtb r1, r2", 0x31415997, r1, r2, cv);
- TESTCARRYEND
-
- printf("UXTH-16 0x2CA\n");
- TESTCARRY
- TESTINST2("uxth r1, r2", 0x31415927, r1, r2, cv);
- TESTINST2("uxth r1, r2", 0x31419597, r1, r2, cv);
- TESTCARRYEND
-
- printf("SXTH-16 0x2C8\n");
- TESTCARRY
- TESTINST2("sxth r1, r2", 0x31415927, r1, r2, cv);
- TESTINST2("sxth r1, r2", 0x31419597, r1, r2, cv);
- TESTCARRYEND
-
- printf("LSLS-16 0x102\n");
- TESTCARRY
- TESTINST2x("lsls r1, r2", 0x31415927, 0x00000000, r1, r2, cv);
- TESTINST2x("lsls r1, r2", 0x31415927, 0x00000001, r1, r2, cv);
- TESTINST2x("lsls r1, r2", 0x31415927, 0x00000002, r1, r2, cv);
- TESTINST2x("lsls r1, r2", 0x31415927, 0x0000000F, r1, r2, cv);
- TESTINST2x("lsls r1, r2", 0x31415927, 0x00000010, r1, r2, cv);
- TESTINST2x("lsls r1, r2", 0x31415927, 0x0000001F, r1, r2, cv);
- TESTINST2x("lsls r1, r2", 0x31415927, 0x00000020, r1, r2, cv);
- TESTINST2x("lsls r1, r2", 0x31415927, 0x00000021, r1, r2, cv);
- TESTCARRYEND
-
- printf("LSRS-16 0x103\n");
- TESTCARRY
- TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000000, r1, r2, cv);
- TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000001, r1, r2, cv);
- TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000002, r1, r2, cv);
- TESTINST2x("lsrs r1, r2", 0x31415927, 0x0000000F, r1, r2, cv);
- TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000010, r1, r2, cv);
- TESTINST2x("lsrs r1, r2", 0x31415927, 0x0000001F, r1, r2, cv);
- TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000020, r1, r2, cv);
- TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000021, r1, r2, cv);
- TESTCARRYEND
-
- printf("ASRS-16 0x104\n");
- TESTCARRY
- TESTINST2x("asrs r1, r2", 0x31415927, 0x00000000, r1, r2, cv);
- TESTINST2x("asrs r1, r2", 0x91415927, 0x00000001, r1, r2, cv);
- TESTINST2x("asrs r1, r2", 0x31415927, 0x00000002, r1, r2, cv);
- TESTINST2x("asrs r1, r2", 0x91415927, 0x0000000F, r1, r2, cv);
- TESTINST2x("asrs r1, r2", 0x31415927, 0x00000010, r1, r2, cv);
- TESTINST2x("asrs r1, r2", 0x91415927, 0x0000001F, r1, r2, cv);
- TESTINST2x("asrs r1, r2", 0x31415927, 0x00000020, r1, r2, cv);
- TESTINST2x("asrs r1, r2", 0x91415927, 0x00000021, r1, r2, cv);
- TESTCARRYEND
-
- printf("RORS-16 0x107\n");
- TESTCARRY
- TESTINST2x("rors r1, r2", 0x31415927, 0x00000000, r1, r2, cv);
- TESTINST2x("rors r1, r2", 0x31415927, 0x00000001, r1, r2, cv);
- TESTINST2x("rors r1, r2", 0x31415927, 0x00000002, r1, r2, cv);
- TESTINST2x("rors r1, r2", 0x31415927, 0x0000000F, r1, r2, cv);
- TESTINST2x("rors r1, r2", 0x31415927, 0x00000010, r1, r2, cv);
- TESTINST2x("rors r1, r2", 0x31415927, 0x0000001F, r1, r2, cv);
- TESTINST2x("rors r1, r2", 0x31415927, 0x00000020, r1, r2, cv);
- TESTINST2x("rors r1, r2", 0x31415927, 0x00000021, r1, r2, cv);
- TESTCARRYEND
-
- printf("ADD(HI)-16\n");
- TESTCARRY
- TESTINST2x("add r5, r12", 0x31415927, 0x12345678, r5, r12, cv);
- TESTINST2x("add r4, r9 ", 0x31415927, 0x12345678, r4, r9, cv);
- TESTCARRYEND
-
- printf("CMP(HI)-16 0x10a\n");
- TESTCARRY
- TESTINST3("cmp r5, r12", 0, 0, r12/*fake*/, r5, r12, 0);
- TESTINST3("cmp r5, r12", 1, 0, r12/*fake*/, r5, r12, 0);
- TESTINST3("cmp r5, r12", 0, 1, r12/*fake*/, r5, r12, 0);
- TESTINST3("cmp r5, r12", -1, 0, r12/*fake*/, r5, r12, 0);
- TESTINST3("cmp r5, r12", 0, -1, r12/*fake*/, r5, r12, 0);
- TESTINST3("cmp r5, r12", 0, 0x80000000, r12/*fake*/, r5, r12, 0);
- TESTINST3("cmp r5, r12", 0x80000000, 0, r12/*fake*/, r5, r12, 0);
- TESTCARRYEND
-
- printf("MOV(HI)-16\n");
- TESTCARRY
- TESTINST2x("mov r5, r12", 0x31415927, 0x12345678, r5, r12, cv);
- TESTINST2x("mov r4, r9 ", 0x31415927, 0x12345678, r4, r9, cv);
- TESTCARRYEND
-
- printf("ADDS-16 Rd, Rn, #imm3\n");
- TESTCARRY
- TESTINST2x("adds r1, r2, #1", 0x31415927, 0x27181728, r1, r2, cv);
- TESTINST2x("adds r1, r2, #7", 0x31415927, 0x97181728, r1, r2, cv);
- TESTCARRYEND
-
- printf("ADDS-16 Rd, Rn, Rm\n");
- TESTCARRY
- TESTINST3("adds r1, r2, r3", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds r1, r2, r3", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("SUBS-16 Rd, Rn, Rm\n");
- TESTCARRY
- TESTINST3("subs r1, r2, r3", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs r1, r2, r3", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("ADDS-16 Rn, #uimm8\n");
- TESTCARRY
- TESTINST1x("adds r1, #0 ", 0x31415927, r1, cv);
- TESTINST1x("adds r1, #255", 0x31415927, r1, cv);
- TESTINST1x("adds r1, #0 ", 0x91415927, r1, cv);
- TESTINST1x("adds r1, #255", 0x91415927, r1, cv);
- TESTCARRYEND
-
- printf("SUBS-16 Rn, #uimm8\n");
- TESTCARRY
- TESTINST1x("subs r1, #0 ", 0x31415927, r1, cv);
- TESTINST1x("subs r1, #255", 0x31415927, r1, cv);
- TESTINST1x("subs r1, #0 ", 0x91415927, r1, cv);
- TESTINST1x("subs r1, #255", 0x91415927, r1, cv);
- TESTCARRYEND
-
- printf("CMP-16 Rn, #uimm8\n");
- TESTCARRY
- TESTINST1x("cmp r1, #0x80 ", 0x00000080, r1, cv);
- TESTINST1x("cmp r1, #0x7f ", 0x00000080, r1, cv);
- TESTINST1x("cmp r1, #0x81 ", 0x00000080, r1, cv);
- TESTINST1x("cmp r1, #0x80 ", 0xffffff80, r1, cv);
- TESTINST1x("cmp r1, #0x7f ", 0xffffff80, r1, cv);
- TESTINST1x("cmp r1, #0x81 ", 0xffffff80, r1, cv);
- TESTINST1x("cmp r1, #0x01 ", 0x80000000, r1, cv);
- TESTCARRYEND
-
- printf("MOVS-16 Rn, #uimm8\n");
- TESTCARRY
- TESTINST1x("movs r1, #0 ", 0x31415927, r1, cv);
- TESTINST1x("movs r1, #0x7f", 0x31415927, r1, cv);
- TESTINST1x("movs r1, #0x80", 0x31415927, r1, cv);
- TESTINST1x("movs r1, #0x81", 0x31415927, r1, cv);
- TESTINST1x("movs r1, #0xff", 0x31415927, r1, cv);
- TESTCARRYEND
-
- printf("LSLS-16 Rd, Rm, imm5\n");
- TESTCARRY
- TESTINST2("lsls r1, r2, #0 ", 0x31415927, r1, r2, cv);
- TESTINST2("lsls r1, r2, #1 ", 0x31415927, r1, r2, cv);
- TESTINST2("lsls r1, r2, #2 ", 0x31415927, r1, r2, cv);
- TESTINST2("lsls r1, r2, #0xF ", 0x31415927, r1, r2, cv);
- TESTINST2("lsls r1, r2, #0x10", 0x31415927, r1, r2, cv);
- TESTINST2("lsls r1, r2, #0x1F", 0x31415927, r1, r2, cv);
- TESTCARRYEND
-
- printf("LSRS-16 Rd, Rm, imm5\n");
- TESTCARRY
- TESTINST2("lsrs r1, r2, #0 ", 0x31415927, r1, r2, cv);
- TESTINST2("lsrs r1, r2, #1 ", 0x31415927, r1, r2, cv);
- TESTINST2("lsrs r1, r2, #2 ", 0x31415927, r1, r2, cv);
- TESTINST2("lsrs r1, r2, #0xF ", 0x31415927, r1, r2, cv);
- TESTINST2("lsrs r1, r2, #0x10", 0x31415927, r1, r2, cv);
- TESTINST2("lsrs r1, r2, #0x1F", 0x31415927, r1, r2, cv);
- TESTCARRYEND
-
- printf("ASRS-16 Rd, Rm, imm5\n");
- TESTCARRY
- TESTINST2("asrs r1, r2, #0 ", 0x31415927, r1, r2, cv);
- TESTINST2("asrs r1, r2, #1 ", 0x91415927, r1, r2, cv);
- TESTINST2("asrs r1, r2, #2 ", 0x31415927, r1, r2, cv);
- TESTINST2("asrs r1, r2, #0xF ", 0x91415927, r1, r2, cv);
- TESTINST2("asrs r1, r2, #0x10", 0x31415927, r1, r2, cv);
- TESTINST2("asrs r1, r2, #0x1F", 0x91415927, r1, r2, cv);
- TESTCARRYEND
-
- // 32 bit instructions
-
- printf("(T3) ADD{S}.W Rd, Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST2("adds.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("adds.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("add.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("add.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("add.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("add.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T3) CMP.W Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST1x("cmp.w r1, #0xffffffff", 0x31415927, r1, cv);
- TESTINST1x("cmp.w r1, #0xee00ee00", 0x31415927, r1, cv);
- TESTINST1x("cmp.w r1, #255 ", 0, r1, cv);
- TESTINST1x("cmp.w r1, #0 ", 1, r1, cv);
- TESTINST1x("cmp.w r1, #1 ", 0, r1, cv);
- TESTINST1x("cmp.w r1, #0 ", -1, r1, cv);
- TESTINST1x("cmp.w r1, #-1 ", 0, r1, cv);
- TESTINST1x("cmp.w r1, #0x80000000", 0, r1, cv);
- TESTINST1x("cmp.w r1, #0 ", 0x80000000, r1, cv);
- TESTINST1x("cmp.w r1, #0x80000000", 0x80000000, r1, cv);
- TESTINST1x("cmp.w r1, #0x80000000", 0x7fffffff, r1, cv);
- TESTINST1x("cmp.w r1, #0xff000000", 0x80000000, r1, cv);
- TESTINST1x("cmp.w r1, #0x0dd00000", 0x7fffffff, r1, cv);
- TESTCARRYEND
-
- printf("(T3) CMN.W Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST1x("cmn.w r1, #0xffffffff", 0x31415927, r1, cv);
- TESTINST1x("cmn.w r1, #0xee00ee00", 0x31415927, r1, cv);
- TESTINST1x("cmn.w r1, #255 ", 0, r1, cv);
- TESTINST1x("cmn.w r1, #0 ", 1, r1, cv);
- TESTINST1x("cmn.w r1, #1 ", 0, r1, cv);
- TESTINST1x("cmn.w r1, #0 ", -1, r1, cv);
- TESTINST1x("cmn.w r1, #-1 ", 0, r1, cv);
- TESTINST1x("cmn.w r1, #0x80000000", 0, r1, cv);
- TESTINST1x("cmn.w r1, #0 ", 0x80000000, r1, cv);
- TESTINST1x("cmn.w r1, #0x80000000", 0x80000000, r1, cv);
- TESTINST1x("cmn.w r1, #0x80000000", 0x7fffffff, r1, cv);
- TESTINST1x("cmn.w r1, #0xff000000", 0x80000000, r1, cv);
- TESTINST1x("cmn.w r1, #0x0dd00000", 0x7fffffff, r1, cv);
- TESTCARRYEND
-
- printf("(T3) TST.W Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST1x("tst.w r1, #0xffffffff", 0x31415927, r1, cv);
- TESTINST1x("tst.w r1, #0xee00ee00", 0x31415927, r1, cv);
- TESTINST1x("tst.w r1, #255 ", 0, r1, cv);
- TESTINST1x("tst.w r1, #0 ", 1, r1, cv);
- TESTINST1x("tst.w r1, #1 ", 0, r1, cv);
- TESTINST1x("tst.w r1, #0 ", -1, r1, cv);
- TESTINST1x("tst.w r1, #-1 ", 0, r1, cv);
- TESTINST1x("tst.w r1, #0x80000000", 0, r1, cv);
- TESTINST1x("tst.w r1, #0 ", 0x80000000, r1, cv);
- TESTINST1x("tst.w r1, #0x80000000", 0x80000000, r1, cv);
- TESTINST1x("tst.w r1, #0x80000000", 0x7fffffff, r1, cv);
- TESTINST1x("tst.w r1, #0xff000000", 0x80000000, r1, cv);
- TESTINST1x("tst.w r1, #0x0dd00000", 0x7fffffff, r1, cv);
- TESTCARRYEND
-
- printf("(T3) TEQ.W Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST1x("teq.w r1, #0xffffffff", 0x31415927, r1, cv);
- TESTINST1x("teq.w r1, #0xee00ee00", 0x31415927, r1, cv);
- TESTINST1x("teq.w r1, #255 ", 0, r1, cv);
- TESTINST1x("teq.w r1, #0 ", 1, r1, cv);
- TESTINST1x("teq.w r1, #1 ", 0, r1, cv);
- TESTINST1x("teq.w r1, #0 ", -1, r1, cv);
- TESTINST1x("teq.w r1, #-1 ", 0, r1, cv);
- TESTINST1x("teq.w r1, #0x80000000", 0, r1, cv);
- TESTINST1x("teq.w r1, #0 ", 0x80000000, r1, cv);
- TESTINST1x("teq.w r1, #0x80000000", 0x80000000, r1, cv);
- TESTINST1x("teq.w r1, #0x80000000", 0x7fffffff, r1, cv);
- TESTINST1x("teq.w r1, #0xff000000", 0x80000000, r1, cv);
- TESTINST1x("teq.w r1, #0x0dd00000", 0x7fffffff, r1, cv);
- TESTCARRYEND
-
- printf("(T3) SUB{S}.W Rd, Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST2("subs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("subs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("sub.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T3) RSB{S}.W Rd, Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST2("rsbs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("rsbs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("rsb.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T3) ADC{S}.W Rd, Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST2("adcs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("adcs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("adc.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T3) SBC{S}.W Rd, Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST2("sbcs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("sbcs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("sbc.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T3) AND{S}.W Rd, Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST2("ands.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("ands.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("and.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("and.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("and.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("and.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T3) ORR{S}.W Rd, Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST2("orrs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("orrs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("orr.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T3) EOR{S}.W Rd, Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST2("eors.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("eors.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("eor.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T3) BIC{S}.W Rd, Rn, #constT [allegedly]\n");
- TESTCARRY
- TESTINST2("bics.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("bics.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #255 ", 0, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0 ", 1, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #1 ", 0, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0 ", -1, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #-1 ", 0, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0x80000000", 0, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0 ", 0x80000000, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
- TESTINST2("bic.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("ADD{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adds.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("add.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("SUBB{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("subs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sub.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("RSB{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("rsb.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("ADC{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("adc.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("SBC{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("sbc.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
-#if 0
- printf("XXX{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("xxx.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-#endif
-
- printf("AND{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("ands.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("and.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("ORR{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orrs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("orr.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("EOR{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eors.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("eor.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("BIC{S}.W Rd, Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0, 1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0, 1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", -1, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", -1, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0, -1, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0, -1, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0x80000000, 0, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bics.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTINST3("bic.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("(T?) LSL{S}.W Rd, Rn, Rm\n");
- TESTCARRY
- TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
- TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
- TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
- TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
- TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
- TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
- TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
- TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
- TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
- TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
- TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
- TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
- TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
- TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
- TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
- TESTINST3("lsl.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("(T?) LSR{S}.W Rd, Rn, Rm\n");
- TESTCARRY
- TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
- TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
- TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
- TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
- TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
- TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
- TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
- TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
- TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
- TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
- TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
- TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
- TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
- TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
- TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
- TESTINST3("lsr.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
- TESTCARRYEND
-
- printf("(T?) ASR{S}.W Rd, Rn, Rm\n");
- TESTCARRY
- TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
- TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x00000001, r1, r2, r3, cv);
- TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
- TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x0000000F, r1, r2, r3, cv);
- TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
- TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x0000001F, r1, r2, r3, cv);
- TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
- TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x00000021, r1, r2, r3, cv);
- TESTINST3("asr.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
- TESTINST3("asr.w r1, r2, r3", 0x91415927, 0x00000001, r1, r2, r3, cv);
- TESTINST3("asr.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
- TESTINST3("asr.w r1, r2, r3", 0x91415927, 0x0000000F, r1, r2, r3, cv);
- TESTINST3("asr.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
- TESTINST3("asr.w r1, r2, r3", 0x91415927, 0x0000001F, r1, r2, r3, cv);
- TESTINST3("asr.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
- TESTINST3("asr.w r1, r2, r3", 0x91415927, 0x00000021, r1, r2, r3, cv);
- TESTCARRYEND
-
-#if 0
- // not handled by vex
- printf("(T?) ROR{S}.W Rd, Rn, Rm\n");
- TESTCARRY
- TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
- TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
- TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
- TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
- TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
- TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
- TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
- TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
- TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
- TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
- TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
- TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
- TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
- TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
- TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
- TESTINST3("ror.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
- TESTCARRYEND
-#endif
-
- printf("MVN{S}.W Rd, Rn, shift, and MOV{S}.W ditto\n");
- TESTCARRY
- TESTINST2("lsls.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #0 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #1 ", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #15", 0x7fffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #31", 0x7fffffff, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #15", 0x00000000, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #31", 0x00000000, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #15", 0x00000000, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #31", 0x00000000, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #15", 0x00000000, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #31", 0x00000000, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #15", 0x00000000, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #31", 0x00000000, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #15", 0x00000000, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #31", 0x00000000, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #15", 0x00000000, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #31", 0x00000000, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #15", 0x00000000, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #31", 0x00000000, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #15", 0x00000000, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #31", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #15", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #31", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #15", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #31", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #15", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #31", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #15", 0x00000000, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #31", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #15", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #31", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #15", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #31", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #15", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #31", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #0 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #1 ", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #15", 0x00000000, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #31", 0x00000000, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #15", 0x00000001, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #31", 0x00000001, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #15", 0x00000001, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #31", 0x00000001, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #15", 0x00000001, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #31", 0x00000001, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #15", 0x00000001, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #31", 0x00000001, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #15", 0x00000001, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #31", 0x00000001, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #15", 0x00000001, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #31", 0x00000001, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #15", 0x00000001, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #31", 0x00000001, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #15", 0x00000001, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #31", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #15", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #31", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #15", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #31", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #15", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #31", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #15", 0x00000001, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #31", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #15", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #31", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #15", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #31", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #15", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #31", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #0 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #1 ", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #15", 0x00000001, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #31", 0x00000001, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #0 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #1 ", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #15", 0x9218abcd, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #31", 0x9218abcd, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #15", 0xffffffff, r1, r2, cv);
- TESTINST2("lsls.w r1, r2, #31", 0xffffffff, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #15", 0xffffffff, r1, r2, cv);
- TESTINST2("lsrs.w r1, r2, #31", 0xffffffff, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #15", 0xffffffff, r1, r2, cv);
- TESTINST2("asrs.w r1, r2, #31", 0xffffffff, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #15", 0xffffffff, r1, r2, cv);
- TESTINST2("rors.w r1, r2, #31", 0xffffffff, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #15", 0xffffffff, r1, r2, cv);
- TESTINST2("lsl.w r1, r2, #31", 0xffffffff, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #15", 0xffffffff, r1, r2, cv);
- TESTINST2("lsr.w r1, r2, #31", 0xffffffff, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #15", 0xffffffff, r1, r2, cv);
- TESTINST2("asr.w r1, r2, #31", 0xffffffff, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #15", 0xffffffff, r1, r2, cv);
- TESTINST2("ror.w r1, r2, #31", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #15", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsl #31", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #15", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, lsr #31", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #15", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, asr #31", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #15", 0xffffffff, r1, r2, cv);
- TESTINST2("mvns.w r1, r2, ror #31", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #15", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsl #31", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #15", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, lsr #31", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #15", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, asr #31", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #0 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #1 ", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #15", 0xffffffff, r1, r2, cv);
- TESTINST2("mvn.w r1, r2, ror #31", 0xffffffff, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T?) TST.W Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST2x("tst.w r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv);
- TESTINST2x("tst.w r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T?) TEQ.W Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST2x("teq.w r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv);
- TESTINST2x("teq.w r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T?) CMP.W Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST2x("cmp.w r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, lsr #2", 0x15555555, 0x55555555, r1, r2, cv);
- TESTINST2x("cmp.w r1, r2, ror #1", 0x55555555, 0xaaaaaaaa, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T?) CMN.W Rn, Rm, {shift}\n");
- TESTCARRY
- TESTINST2x("cmn.w r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, lsr #2", 0x15555555, 0x55555555, r1, r2, cv);
- TESTINST2x("cmn.w r1, r2, ror #1", 0x55555555, 0xaaaaaaaa, r1, r2, cv);
- TESTCARRYEND
-
- printf("(T2) MOV{S}.W Rd, #constT\n");
- TESTCARRY
- TESTINST1("movs.w r9, 0x00000000", r9, cv);
- TESTINST1("movs.w r9, 0x000000FF", r9, cv);
- TESTINST1("movs.w r9, 0x0000007F", r9, cv);
- TESTINST1("movs.w r9, 0x00FF00FF", r9, cv);
- TESTINST1("movs.w r9, 0x007F007F", r9, cv);
- TESTINST1("movs.w r9, 0x43434343", r9, cv);
- TESTINST1("movs.w r9, 0x93939393", r9, cv);
- TESTINST1("movs.w r9, 0x93000000", r9, cv);
- TESTINST1("movs.w r9, 0x43000000", r9, cv);
- TESTINST1("movs.w r9, 0x09300000", r9, cv);
- TESTINST1("movs.w r9, 0x04300000", r9, cv);
- TESTINST1("movs.w r9, 0x00930000", r9, cv);
- TESTINST1("movs.w r9, 0x00430000", r9, cv);
- TESTINST1("movs.w r9, 0x00000930", r9, cv);
- TESTINST1("movs.w r9, 0x00000430", r9, cv);
- TESTINST1("movs.w r9, 0x00000093", r9, cv);
- TESTINST1("movs.w r9, 0x00000043", r9, cv);
- TESTINST1("mov.w r9, 0x00000000", r9, cv);
- TESTINST1("mov.w r9, 0x000000FF", r9, cv);
- TESTINST1("mov.w r9, 0x0000007F", r9, cv);
- TESTINST1("mov.w r9, 0x00FF00FF", r9, cv);
- TESTINST1("mov.w r9, 0x007F007F", r9, cv);
- TESTINST1("mov.w r9, 0x43434343", r9, cv);
- TESTINST1("mov.w r9, 0x93939393", r9, cv);
- TESTINST1("mov.w r9, 0x93000000", r9, cv);
- TESTINST1("mov.w r9, 0x43000000", r9, cv);
- TESTINST1("mov.w r9, 0x09300000", r9, cv);
- TESTINST1("mov.w r9, 0x04300000", r9, cv);
- TESTINST1("mov.w r9, 0x00930000", r9, cv);
- TESTINST1("mov.w r9, 0x00430000", r9, cv);
- TESTINST1("mov.w r9, 0x00000930", r9, cv);
- TESTINST1("mov.w r9, 0x00000430", r9, cv);
- TESTINST1("mov.w r9, 0x00000093", r9, cv);
- TESTINST1("mov.w r9, 0x00000043", r9, cv);
- TESTCARRYEND
-
- printf("(T2) MVN{S}.W Rd, #constT\n");
- TESTCARRY
- TESTINST1("mvns.w r9, 0x00000000", r9, cv);
- TESTINST1("mvns.w r9, 0x000000FF", r9, cv);
- TESTINST1("mvns.w r9, 0x0000007F", r9, cv);
- TESTINST1("mvns.w r9, 0x00FF00FF", r9, cv);
- TESTINST1("mvns.w r9, 0x007F007F", r9, cv);
- TESTINST1("mvns.w r9, 0x43434343", r9, cv);
- TESTINST1("mvns.w r9, 0x93939393", r9, cv);
- TESTINST1("mvns.w r9, 0x93000000", r9, cv);
- TESTINST1("mvns.w r9, 0x43000000", r9, cv);
- TESTINST1("mvns.w r9, 0x09300000", r9, cv);
- TESTINST1("mvns.w r9, 0x04300000", r9, cv);
- TESTINST1("mvns.w r9, 0x00930000", r9, cv);
- TESTINST1("mvns.w r9, 0x00430000", r9, cv);
- TESTINST1("mvns.w r9, 0x00000930", r9, cv);
- TESTINST1("mvns.w r9, 0x00000430", r9, cv);
- TESTINST1("mvns.w r9, 0x00000093", r9, cv);
- TESTINST1("mvns.w r9, 0x00000043", r9, cv);
- TESTINST1("mvn.w r9, 0x00000000", r9, cv);
- TESTINST1("mvn.w r9, 0x000000FF", r9, cv);
- TESTINST1("mvn.w r9, 0x0000007F", r9, cv);
- TESTINST1("mvn.w r9, 0x00FF00FF", r9, cv);
- TESTINST1("mvn.w r9, 0x007F007F", r9, cv);
- TESTINST1("mvn.w r9, 0x43434343", r9, cv);
- TESTINST1("mvn.w r9, 0x93939393", r9, cv);
- TESTINST1("mvn.w r9, 0x93000000", r9, cv);
- TESTINST1("mvn.w r9, 0x43000000", r9, cv);
- TESTINST1("mvn.w r9, 0x09300000", r9, cv);
- TESTINST1("mvn.w r9, 0x04300000", r9, cv);
- TESTINST1("mvn.w r9, 0x00930000", r9, cv);
- TESTINST1("mvn.w r9, 0x00430000", r9, cv);
- TESTINST1("mvn.w r9, 0x00000930", r9, cv);
- TESTINST1("mvn.w r9, 0x00000430", r9, cv);
- TESTINST1("mvn.w r9, 0x00000093", r9, cv);
- TESTINST1("mvn.w r9, 0x00000043", r9, cv);
- TESTCARRYEND
-
- // plus whatever stuff we can throw in from the old ARM test program
- old_main();
+ TESTINST3("smmulr r0, r1, r2", 0, 0, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
+ TESTINST3("smmulr r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
return 0;
}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/arm/v6intThumb.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/arm/v6intThumb.stderr.exp
diff --git a/main/none/tests/arm/v6intThumb.stdout.exp b/main/none/tests/arm/v6intThumb.stdout.exp
index 9006e70..b40960c 100644
--- a/main/none/tests/arm/v6intThumb.stdout.exp
+++ b/main/none/tests/arm/v6intThumb.stdout.exp
@@ -16767,19 +16767,19 @@
movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
+movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
+movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
+movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N
+movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
+movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
+movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N
+movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
+movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
+movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
MVN
@@ -17450,15887 +17450,26 @@
uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
uxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
uxtah r0, r1, r2, ROR #0 :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
-CMP-16 0x10a
-cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-CMN-16 0x10a
-cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-TST-16 0x108
-tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-NEGS-16 0x109
-negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 0, cpsr 0x00000000
-negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x00000000
-negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x80000000 N
-negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 1, cpsr 0x00000000
-negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x00000000
-negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 2, cpsr 0x00000000
-negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x00000000
-negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x80000000 N
-negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 3, cpsr 0x00000000
-negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x00000000
-negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-MVNS-16 0x10F
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000
-mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 0, cpsr 0x00000000
-mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x10000000 V
-mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 1, cpsr 0x10000000 V
-mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 2, cpsr 0x20000000 C
-mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 2, cpsr 0x20000000 C
-mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 3, cpsr 0x30000000 CV
-mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-ORRS-16 0x10C
-orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 2, cpsr 0x20000000 C
-orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-ANDS-16 0x100
-ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 0, cpsr 0x00000000
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 2, cpsr 0x20000000 C
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-EORS-16 0x101
-eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 0, cpsr 0x00000000
-eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 2, cpsr 0x20000000 C
-eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-MULS-16 0x10d
-muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 0, cpsr 0x80000000 N
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 1, cpsr 0x90000000 N V
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 2, cpsr 0xa0000000 N C
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 3, cpsr 0xb0000000 N CV
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-BICS-16 0x10E
-bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 0, cpsr 0x00000000
-bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 2, cpsr 0x20000000 C
-bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ADCS-16 0x105
-adcs r1, r2 :: rd 0x5859704f rm 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-adcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adcs r1, r2 :: rd 0x5859704f rm 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000
-adcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adcs r1, r2 :: rd 0x58597050 rm 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000002 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs r1, r2 :: rd 0x80000001 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs r1, r2 :: rd 0x80000001 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs r1, r2 :: rd 0x00000001 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adcs r1, r2 :: rd 0x58597050 rm 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000002 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs r1, r2 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs r1, r2 :: rd 0x80000001 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs r1, r2 :: rd 0x80000001 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs r1, r2 :: rd 0x00000001 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-SBCS-16 0x100
-sbcs r1, r2 :: rd 0x0a2941fe rm 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs r1, r2 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs r1, r2 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs r1, r2 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs r1, r2 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000
-sbcs r1, r2 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs r1, r2 :: rd 0x0a2941fe rm 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs r1, r2 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs r1, r2 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs r1, r2 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs r1, r2 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x00000000
-sbcs r1, r2 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs r1, r2 :: rd 0x0a2941ff rm 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs r1, r2 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-sbcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs r1, r2 :: rd 0x0a2941ff rm 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs r1, r2 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x80000000 N
-sbcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-UXTB-16 0x2CB
-uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 1, cpsr 0xd0000000 NZ V
-uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 2, cpsr 0xe0000000 NZC
-uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
-SXTB-16 0x2C9
-sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 0, cpsr 0xc0000000 NZ
-sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 1, cpsr 0xd0000000 NZ V
-sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 2, cpsr 0xe0000000 NZC
-sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
-UXTH-16 0x2CA
-uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 0, cpsr 0xc0000000 NZ
-uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 1, cpsr 0xd0000000 NZ V
-uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 2, cpsr 0xe0000000 NZC
-uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
-SXTH-16 0x2C8
-sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 0, cpsr 0xc0000000 NZ
-sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 1, cpsr 0xd0000000 NZ V
-sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 2, cpsr 0xe0000000 NZC
-sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
-LSLS-16 0x102
-lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 0, cpsr 0x00000000
-lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 0, cpsr 0x80000000 N
-lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 0, cpsr 0x80000000 N
-lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 0, cpsr 0x20000000 C
-lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C
-lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 0, cpsr 0x60000000 ZC
-lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 0, cpsr 0x40000000 Z
-lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 1, cpsr 0x90000000 N V
-lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 1, cpsr 0x90000000 N V
-lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 1, cpsr 0x30000000 CV
-lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV
-lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 1, cpsr 0x70000000 ZCV
-lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 1, cpsr 0x50000000 Z V
-lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 2, cpsr 0x00000000
-lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 2, cpsr 0x80000000 N
-lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 2, cpsr 0x80000000 N
-lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 2, cpsr 0x20000000 C
-lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C
-lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 2, cpsr 0x60000000 ZC
-lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 2, cpsr 0x40000000 Z
-lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 3, cpsr 0x10000000 V
-lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 3, cpsr 0x90000000 N V
-lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 3, cpsr 0x90000000 N V
-lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 3, cpsr 0x30000000 CV
-lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV
-lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 3, cpsr 0x70000000 ZCV
-lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 3, cpsr 0x50000000 Z V
-LSRS-16 0x103
-lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 0, cpsr 0x20000000 C
-lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 0, cpsr 0x20000000 C
-lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 0, cpsr 0x20000000 C
-lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 0, cpsr 0x00000000
-lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 0, cpsr 0x40000000 Z
-lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 0, cpsr 0x40000000 Z
-lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 0, cpsr 0x40000000 Z
-lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 1, cpsr 0x30000000 CV
-lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 1, cpsr 0x30000000 CV
-lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 1, cpsr 0x30000000 CV
-lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 1, cpsr 0x10000000 V
-lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 1, cpsr 0x50000000 Z V
-lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 1, cpsr 0x50000000 Z V
-lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 1, cpsr 0x50000000 Z V
-lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 2, cpsr 0x20000000 C
-lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 2, cpsr 0x20000000 C
-lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 2, cpsr 0x00000000
-lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 2, cpsr 0x40000000 Z
-lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 2, cpsr 0x40000000 Z
-lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 2, cpsr 0x40000000 Z
-lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 3, cpsr 0x30000000 CV
-lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 3, cpsr 0x30000000 CV
-lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 3, cpsr 0x10000000 V
-lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 3, cpsr 0x50000000 Z V
-lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 3, cpsr 0x50000000 Z V
-lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 3, cpsr 0x50000000 Z V
-ASRS-16 0x104
-asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 0, cpsr 0x20000000 C
-asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 0, cpsr 0xa0000000 N C
-asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 0, cpsr 0x00000000
-asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 0, cpsr 0x80000000 N
-asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 0, cpsr 0x40000000 Z
-asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 0, cpsr 0xa0000000 N C
-asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 1, cpsr 0x30000000 CV
-asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 1, cpsr 0x10000000 V
-asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 1, cpsr 0x90000000 N V
-asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 1, cpsr 0x50000000 Z V
-asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 2, cpsr 0x20000000 C
-asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 2, cpsr 0xa0000000 N C
-asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 2, cpsr 0x00000000
-asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 2, cpsr 0x80000000 N
-asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 2, cpsr 0x40000000 Z
-asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 2, cpsr 0xa0000000 N C
-asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 3, cpsr 0x30000000 CV
-asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 3, cpsr 0x10000000 V
-asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 3, cpsr 0x90000000 N V
-asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 3, cpsr 0x50000000 Z V
-asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV
-RORS-16 0x107
-rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 0, cpsr 0xa0000000 N C
-rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 0, cpsr 0xa0000000 N C
-rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 0, cpsr 0x00000000
-rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 0, cpsr 0x00000000
-rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 0, cpsr 0x00000000
-rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 0, cpsr 0xa0000000 N C
-rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
-rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 1, cpsr 0xb0000000 N CV
-rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 1, cpsr 0xb0000000 N CV
-rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 1, cpsr 0x10000000 V
-rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 1, cpsr 0x10000000 V
-rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 1, cpsr 0x10000000 V
-rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV
-rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 2, cpsr 0xa0000000 N C
-rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 2, cpsr 0xa0000000 N C
-rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 2, cpsr 0x00000000
-rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 2, cpsr 0x00000000
-rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 2, cpsr 0x00000000
-rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 2, cpsr 0xa0000000 N C
-rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 3, cpsr 0xb0000000 N CV
-rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 3, cpsr 0xb0000000 N CV
-rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 3, cpsr 0x10000000 V
-rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 3, cpsr 0x10000000 V
-rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 3, cpsr 0x10000000 V
-rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV
-ADD(HI)-16
-add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ
-add r4, r9 :: rd 0x4375af9f rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ
-add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V
-add r4, r9 :: rd 0x4375af9f rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V
-add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC
-add r4, r9 :: rd 0x4375af9f rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC
-add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV
-add r4, r9 :: rd 0x4375af9f rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV
-CMP(HI)-16 0x10a
-cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-MOV(HI)-16
-mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ
-mov r4, r9 :: rd 0x12345678 rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ
-mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V
-mov r4, r9 :: rd 0x12345678 rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V
-mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC
-mov r4, r9 :: rd 0x12345678 rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC
-mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV
-mov r4, r9 :: rd 0x12345678 rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV
-ADDS-16 Rd, Rn, #imm3
-adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 0, cpsr 0x00000000
-adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 1, cpsr 0x00000000
-adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 2, cpsr 0x00000000
-adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 3, cpsr 0x00000000
-adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 3, cpsr 0x80000000 N
-ADDS-16 Rd, Rn, Rm
-adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV
-adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-SUBS-16 Rd, Rn, Rm
-subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-ADDS-16 Rn, #uimm8
-adds r1, #0 :: rd 0x31415927, c:v-in 0, cpsr 0x00000000
-adds r1, #255 :: rd 0x31415a26, c:v-in 0, cpsr 0x00000000
-adds r1, #0 :: rd 0x91415927, c:v-in 0, cpsr 0x80000000 N
-adds r1, #255 :: rd 0x91415a26, c:v-in 0, cpsr 0x80000000 N
-adds r1, #0 :: rd 0x31415927, c:v-in 1, cpsr 0x00000000
-adds r1, #255 :: rd 0x31415a26, c:v-in 1, cpsr 0x00000000
-adds r1, #0 :: rd 0x91415927, c:v-in 1, cpsr 0x80000000 N
-adds r1, #255 :: rd 0x91415a26, c:v-in 1, cpsr 0x80000000 N
-adds r1, #0 :: rd 0x31415927, c:v-in 2, cpsr 0x00000000
-adds r1, #255 :: rd 0x31415a26, c:v-in 2, cpsr 0x00000000
-adds r1, #0 :: rd 0x91415927, c:v-in 2, cpsr 0x80000000 N
-adds r1, #255 :: rd 0x91415a26, c:v-in 2, cpsr 0x80000000 N
-adds r1, #0 :: rd 0x31415927, c:v-in 3, cpsr 0x00000000
-adds r1, #255 :: rd 0x31415a26, c:v-in 3, cpsr 0x00000000
-adds r1, #0 :: rd 0x91415927, c:v-in 3, cpsr 0x80000000 N
-adds r1, #255 :: rd 0x91415a26, c:v-in 3, cpsr 0x80000000 N
-SUBS-16 Rn, #uimm8
-subs r1, #0 :: rd 0x31415927, c:v-in 0, cpsr 0x20000000 C
-subs r1, #255 :: rd 0x31415828, c:v-in 0, cpsr 0x20000000 C
-subs r1, #0 :: rd 0x91415927, c:v-in 0, cpsr 0xa0000000 N C
-subs r1, #255 :: rd 0x91415828, c:v-in 0, cpsr 0xa0000000 N C
-subs r1, #0 :: rd 0x31415927, c:v-in 1, cpsr 0x20000000 C
-subs r1, #255 :: rd 0x31415828, c:v-in 1, cpsr 0x20000000 C
-subs r1, #0 :: rd 0x91415927, c:v-in 1, cpsr 0xa0000000 N C
-subs r1, #255 :: rd 0x91415828, c:v-in 1, cpsr 0xa0000000 N C
-subs r1, #0 :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C
-subs r1, #255 :: rd 0x31415828, c:v-in 2, cpsr 0x20000000 C
-subs r1, #0 :: rd 0x91415927, c:v-in 2, cpsr 0xa0000000 N C
-subs r1, #255 :: rd 0x91415828, c:v-in 2, cpsr 0xa0000000 N C
-subs r1, #0 :: rd 0x31415927, c:v-in 3, cpsr 0x20000000 C
-subs r1, #255 :: rd 0x31415828, c:v-in 3, cpsr 0x20000000 C
-subs r1, #0 :: rd 0x91415927, c:v-in 3, cpsr 0xa0000000 N C
-subs r1, #255 :: rd 0x91415828, c:v-in 3, cpsr 0xa0000000 N C
-CMP-16 Rn, #uimm8
-cmp r1, #0x80 :: rd 0x00000080, c:v-in 0, cpsr 0x60000000 ZC
-cmp r1, #0x7f :: rd 0x00000080, c:v-in 0, cpsr 0x20000000 C
-cmp r1, #0x81 :: rd 0x00000080, c:v-in 0, cpsr 0x80000000 N
-cmp r1, #0x80 :: rd 0xffffff80, c:v-in 0, cpsr 0xa0000000 N C
-cmp r1, #0x7f :: rd 0xffffff80, c:v-in 0, cpsr 0xa0000000 N C
-cmp r1, #0x81 :: rd 0xffffff80, c:v-in 0, cpsr 0xa0000000 N C
-cmp r1, #0x01 :: rd 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-cmp r1, #0x80 :: rd 0x00000080, c:v-in 1, cpsr 0x60000000 ZC
-cmp r1, #0x7f :: rd 0x00000080, c:v-in 1, cpsr 0x20000000 C
-cmp r1, #0x81 :: rd 0x00000080, c:v-in 1, cpsr 0x80000000 N
-cmp r1, #0x80 :: rd 0xffffff80, c:v-in 1, cpsr 0xa0000000 N C
-cmp r1, #0x7f :: rd 0xffffff80, c:v-in 1, cpsr 0xa0000000 N C
-cmp r1, #0x81 :: rd 0xffffff80, c:v-in 1, cpsr 0xa0000000 N C
-cmp r1, #0x01 :: rd 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-cmp r1, #0x80 :: rd 0x00000080, c:v-in 2, cpsr 0x60000000 ZC
-cmp r1, #0x7f :: rd 0x00000080, c:v-in 2, cpsr 0x20000000 C
-cmp r1, #0x81 :: rd 0x00000080, c:v-in 2, cpsr 0x80000000 N
-cmp r1, #0x80 :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C
-cmp r1, #0x7f :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C
-cmp r1, #0x81 :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C
-cmp r1, #0x01 :: rd 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-cmp r1, #0x80 :: rd 0x00000080, c:v-in 3, cpsr 0x60000000 ZC
-cmp r1, #0x7f :: rd 0x00000080, c:v-in 3, cpsr 0x20000000 C
-cmp r1, #0x81 :: rd 0x00000080, c:v-in 3, cpsr 0x80000000 N
-cmp r1, #0x80 :: rd 0xffffff80, c:v-in 3, cpsr 0xa0000000 N C
-cmp r1, #0x7f :: rd 0xffffff80, c:v-in 3, cpsr 0xa0000000 N C
-cmp r1, #0x81 :: rd 0xffffff80, c:v-in 3, cpsr 0xa0000000 N C
-cmp r1, #0x01 :: rd 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-MOVS-16 Rn, #uimm8
-movs r1, #0 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-movs r1, #0x7f :: rd 0x0000007f, c:v-in 0, cpsr 0x00000000
-movs r1, #0x80 :: rd 0x00000080, c:v-in 0, cpsr 0x00000000
-movs r1, #0x81 :: rd 0x00000081, c:v-in 0, cpsr 0x00000000
-movs r1, #0xff :: rd 0x000000ff, c:v-in 0, cpsr 0x00000000
-movs r1, #0 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-movs r1, #0x7f :: rd 0x0000007f, c:v-in 1, cpsr 0x10000000 V
-movs r1, #0x80 :: rd 0x00000080, c:v-in 1, cpsr 0x10000000 V
-movs r1, #0x81 :: rd 0x00000081, c:v-in 1, cpsr 0x10000000 V
-movs r1, #0xff :: rd 0x000000ff, c:v-in 1, cpsr 0x10000000 V
-movs r1, #0 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-movs r1, #0x7f :: rd 0x0000007f, c:v-in 2, cpsr 0x20000000 C
-movs r1, #0x80 :: rd 0x00000080, c:v-in 2, cpsr 0x20000000 C
-movs r1, #0x81 :: rd 0x00000081, c:v-in 2, cpsr 0x20000000 C
-movs r1, #0xff :: rd 0x000000ff, c:v-in 2, cpsr 0x20000000 C
-movs r1, #0 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-movs r1, #0x7f :: rd 0x0000007f, c:v-in 3, cpsr 0x30000000 CV
-movs r1, #0x80 :: rd 0x00000080, c:v-in 3, cpsr 0x30000000 CV
-movs r1, #0x81 :: rd 0x00000081, c:v-in 3, cpsr 0x30000000 CV
-movs r1, #0xff :: rd 0x000000ff, c:v-in 3, cpsr 0x30000000 CV
-LSLS-16 Rd, Rm, imm5
-lsls r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-lsls r1, r2, #1 :: rd 0x6282b24e rm 0x31415927, c:v-in 0, cpsr 0x00000000
-lsls r1, r2, #2 :: rd 0xc505649c rm 0x31415927, c:v-in 0, cpsr 0x80000000 N
-lsls r1, r2, #0xF :: rd 0xac938000 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N
-lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C
-lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 0, cpsr 0xa0000000 N C
-lsls r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V
-lsls r1, r2, #1 :: rd 0x6282b24e rm 0x31415927, c:v-in 1, cpsr 0x10000000 V
-lsls r1, r2, #2 :: rd 0xc505649c rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V
-lsls r1, r2, #0xF :: rd 0xac938000 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V
-lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV
-lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 1, cpsr 0xb0000000 N CV
-lsls r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-lsls r1, r2, #1 :: rd 0x6282b24e rm 0x31415927, c:v-in 2, cpsr 0x00000000
-lsls r1, r2, #2 :: rd 0xc505649c rm 0x31415927, c:v-in 2, cpsr 0x80000000 N
-lsls r1, r2, #0xF :: rd 0xac938000 rm 0x31415927, c:v-in 2, cpsr 0x80000000 N
-lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C
-lsls r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-lsls r1, r2, #1 :: rd 0x6282b24e rm 0x31415927, c:v-in 3, cpsr 0x10000000 V
-lsls r1, r2, #2 :: rd 0xc505649c rm 0x31415927, c:v-in 3, cpsr 0x90000000 N V
-lsls r1, r2, #0xF :: rd 0xac938000 rm 0x31415927, c:v-in 3, cpsr 0x90000000 N V
-lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
-LSRS-16 Rd, Rm, imm5
-lsrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-lsrs r1, r2, #1 :: rd 0x18a0ac93 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C
-lsrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C
-lsrs r1, r2, #0xF :: rd 0x00006282 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C
-lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 0, cpsr 0x40000000 Z
-lsrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V
-lsrs r1, r2, #1 :: rd 0x18a0ac93 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV
-lsrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV
-lsrs r1, r2, #0xF :: rd 0x00006282 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV
-lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V
-lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 1, cpsr 0x50000000 Z V
-lsrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-lsrs r1, r2, #1 :: rd 0x18a0ac93 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-lsrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-lsrs r1, r2, #0xF :: rd 0x00006282 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 2, cpsr 0x00000000
-lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 2, cpsr 0x40000000 Z
-lsrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-lsrs r1, r2, #1 :: rd 0x18a0ac93 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-lsrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-lsrs r1, r2, #0xF :: rd 0x00006282 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 3, cpsr 0x10000000 V
-lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 3, cpsr 0x50000000 Z V
-ASRS-16 Rd, Rm, imm5
-asrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-asrs r1, r2, #1 :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 0, cpsr 0xa0000000 N C
-asrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C
-asrs r1, r2, #0xF :: rd 0xffff2282 rm 0x91415927, c:v-in 0, cpsr 0xa0000000 N C
-asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 0, cpsr 0x80000000 N
-asrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V
-asrs r1, r2, #1 :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 1, cpsr 0x30000000 CV
-asrs r1, r2, #0xF :: rd 0xffff2282 rm 0x91415927, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V
-asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 1, cpsr 0x90000000 N V
-asrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-asrs r1, r2, #1 :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 2, cpsr 0xa0000000 N C
-asrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-asrs r1, r2, #0xF :: rd 0xffff2282 rm 0x91415927, c:v-in 2, cpsr 0xa0000000 N C
-asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 2, cpsr 0x00000000
-asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 2, cpsr 0x80000000 N
-asrs r1, r2, #0 :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-asrs r1, r2, #1 :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r1, r2, #2 :: rd 0x0c505649 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-asrs r1, r2, #0xF :: rd 0xffff2282 rm 0x91415927, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 3, cpsr 0x10000000 V
-asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 3, cpsr 0x90000000 N V
-(T3) ADD{S}.W Rd, Rn, #constT [allegedly]
-adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C
-adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C
-adds.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-add.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0x20000000 C
-adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0x20000000 C
-adds.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-add.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-adds.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV
-adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-add.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 3, cpsr 0x20000000 C
-adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 3, cpsr 0x20000000 C
-adds.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-add.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T3) CMP.W Rn, #constT [allegedly]
-cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x00000000
-cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x00000000
-cmp.w r1, #255 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmp.w r1, #0 :: rd 0x00000001, c:v-in 0, cpsr 0x20000000 C
-cmp.w r1, #1 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmp.w r1, #0 :: rd 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-cmp.w r1, #-1 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000
-cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-cmp.w r1, #0 :: rd 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0x80000000 N
-cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x00000000
-cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x00000000
-cmp.w r1, #255 :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N
-cmp.w r1, #0 :: rd 0x00000001, c:v-in 1, cpsr 0x20000000 C
-cmp.w r1, #1 :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N
-cmp.w r1, #0 :: rd 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-cmp.w r1, #-1 :: rd 0x00000000, c:v-in 1, cpsr 0x00000000
-cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-cmp.w r1, #0 :: rd 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0x80000000 N
-cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0x00000000
-cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0x00000000
-cmp.w r1, #255 :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N
-cmp.w r1, #0 :: rd 0x00000001, c:v-in 2, cpsr 0x20000000 C
-cmp.w r1, #1 :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N
-cmp.w r1, #0 :: rd 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-cmp.w r1, #-1 :: rd 0x00000000, c:v-in 2, cpsr 0x00000000
-cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-cmp.w r1, #0 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0x80000000 N
-cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0x00000000
-cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0x00000000
-cmp.w r1, #255 :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N
-cmp.w r1, #0 :: rd 0x00000001, c:v-in 3, cpsr 0x20000000 C
-cmp.w r1, #1 :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N
-cmp.w r1, #0 :: rd 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-cmp.w r1, #-1 :: rd 0x00000000, c:v-in 3, cpsr 0x00000000
-cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-cmp.w r1, #0 :: rd 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0x80000000 N
-cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-(T3) CMN.W Rn, #constT [allegedly]
-cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x20000000 C
-cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x20000000 C
-cmn.w r1, #255 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn.w r1, #0 :: rd 0x00000001, c:v-in 0, cpsr 0x00000000
-cmn.w r1, #1 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn.w r1, #0 :: rd 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-cmn.w r1, #-1 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N
-cmn.w r1, #0 :: rd 0x80000000, c:v-in 0, cpsr 0x80000000 N
-cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x20000000 C
-cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x20000000 C
-cmn.w r1, #255 :: rd 0x00000000, c:v-in 1, cpsr 0x00000000
-cmn.w r1, #0 :: rd 0x00000001, c:v-in 1, cpsr 0x00000000
-cmn.w r1, #1 :: rd 0x00000000, c:v-in 1, cpsr 0x00000000
-cmn.w r1, #0 :: rd 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-cmn.w r1, #-1 :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N
-cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N
-cmn.w r1, #0 :: rd 0x80000000, c:v-in 1, cpsr 0x80000000 N
-cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C
-cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C
-cmn.w r1, #255 :: rd 0x00000000, c:v-in 2, cpsr 0x00000000
-cmn.w r1, #0 :: rd 0x00000001, c:v-in 2, cpsr 0x00000000
-cmn.w r1, #1 :: rd 0x00000000, c:v-in 2, cpsr 0x00000000
-cmn.w r1, #0 :: rd 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-cmn.w r1, #-1 :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N
-cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N
-cmn.w r1, #0 :: rd 0x80000000, c:v-in 2, cpsr 0x80000000 N
-cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV
-cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0x20000000 C
-cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0x20000000 C
-cmn.w r1, #255 :: rd 0x00000000, c:v-in 3, cpsr 0x00000000
-cmn.w r1, #0 :: rd 0x00000001, c:v-in 3, cpsr 0x00000000
-cmn.w r1, #1 :: rd 0x00000000, c:v-in 3, cpsr 0x00000000
-cmn.w r1, #0 :: rd 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-cmn.w r1, #-1 :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N
-cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N
-cmn.w r1, #0 :: rd 0x80000000, c:v-in 3, cpsr 0x80000000 N
-cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-(T3) TST.W Rn, #constT [allegedly]
-tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x00000000
-tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x00000000
-tst.w r1, #255 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, #0 :: rd 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, #1 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, #0 :: rd 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, #-1 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-tst.w r1, #0 :: rd 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x00000000
-tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x10000000 V
-tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x10000000 V
-tst.w r1, #255 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, #0 :: rd 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, #1 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, #0 :: rd 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, #-1 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0x70000000 ZCV
-tst.w r1, #0 :: rd 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
-tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
-tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C
-tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0x20000000 C
-tst.w r1, #255 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-tst.w r1, #0 :: rd 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-tst.w r1, #1 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-tst.w r1, #0 :: rd 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-tst.w r1, #-1 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-tst.w r1, #0 :: rd 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x00000000
-tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-tst.w r1, #255 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-tst.w r1, #0 :: rd 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-tst.w r1, #1 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-tst.w r1, #0 :: rd 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-tst.w r1, #-1 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-tst.w r1, #0 :: rd 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-(T3) TEQ.W Rn, #constT [allegedly]
-teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x80000000 N
-teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x80000000 N
-teq.w r1, #255 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000
-teq.w r1, #0 :: rd 0x00000001, c:v-in 0, cpsr 0x00000000
-teq.w r1, #1 :: rd 0x00000000, c:v-in 0, cpsr 0x00000000
-teq.w r1, #0 :: rd 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-teq.w r1, #-1 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N
-teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-teq.w r1, #0 :: rd 0x80000000, c:v-in 0, cpsr 0x80000000 N
-teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0x20000000 C
-teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x00000000
-teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x90000000 N V
-teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x90000000 N V
-teq.w r1, #255 :: rd 0x00000000, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, #0 :: rd 0x00000001, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, #1 :: rd 0x00000000, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, #0 :: rd 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-teq.w r1, #-1 :: rd 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0xb0000000 N CV
-teq.w r1, #0 :: rd 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0xa0000000 N C
-teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0xa0000000 N C
-teq.w r1, #255 :: rd 0x00000000, c:v-in 2, cpsr 0x20000000 C
-teq.w r1, #0 :: rd 0x00000001, c:v-in 2, cpsr 0x20000000 C
-teq.w r1, #1 :: rd 0x00000000, c:v-in 2, cpsr 0x20000000 C
-teq.w r1, #0 :: rd 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-teq.w r1, #-1 :: rd 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-teq.w r1, #0 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0x20000000 C
-teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x00000000
-teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
-teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
-teq.w r1, #255 :: rd 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-teq.w r1, #0 :: rd 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-teq.w r1, #1 :: rd 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-teq.w r1, #0 :: rd 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-teq.w r1, #-1 :: rd 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-teq.w r1, #0 :: rd 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-(T3) SUB{S}.W Rd, Rn, #constT [allegedly]
-subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-sub.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-sub.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-sub.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-sub.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T3) RSB{S}.W Rd, Rn, #constT [allegedly]
-rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-rsb.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-rsb.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-rsb.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-rsb.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #0 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #0 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T3) ADC{S}.W Rd, Rn, #constT [allegedly]
-adcs.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C
-adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0x20000000 C
-adcs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-adcs.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adc.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0x20000000 C
-adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0x20000000 C
-adcs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-adcs.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adc.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-adcs.w r1, r2, #255 :: rd 0x00000100 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, #0 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, #1 :: rd 0x00000002 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, #0 :: rd 0x80000001 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adc.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #255 :: rd 0x00000100 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #0 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #1 :: rd 0x00000002 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #0 :: rd 0x80000001 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x20000000 C
-adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 3, cpsr 0x20000000 C
-adcs.w r1, r2, #255 :: rd 0x00000100 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, #0 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, #1 :: rd 0x00000002 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, #0 :: rd 0x80000001 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adc.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #255 :: rd 0x00000100 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #0 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #1 :: rd 0x00000002 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #0 :: rd 0x80000001 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T3) SBC{S}.W Rd, Rn, #constT [allegedly]
-sbcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, #0 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-sbcs.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, #0 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-sbc.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #0 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #0 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, #0 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-sbcs.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, #0 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-sbc.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #255 :: rd 0xffffff00 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #1 :: rd 0xfffffffe rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #0 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #0 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-sbc.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-sbc.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #255 :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #-1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T3) AND{S}.W Rd, Rn, #constT [allegedly]
-ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-and.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
-ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
-ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-and.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0x00000000
-and.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-and.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #0 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #0 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T3) ORR{S}.W Rd, Rn, #constT [allegedly]
-orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-orr.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-orr.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x00000000
-orr.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-orr.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T3) EOR{S}.W Rd, Rn, #constT [allegedly]
-eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-eor.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-eor.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x00000000
-eor.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-eor.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #255 :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #-1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T3) BIC{S}.W Rd, Rn, #constT [allegedly]
-bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-bic.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-bic.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x00000000
-bic.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-bic.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #255 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #-1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #0 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ADD{S}.W Rd, Rn, Rm, {shift}
-adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-add.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-add.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-add.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-add.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000 Z
-add.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x40000000 Z
-adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-add.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-adds.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-add.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adds.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adds.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x00000000
-adds.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x00000000
-add.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-add.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-SUBB{S}.W Rd, Rn, Rm, {shift}
-subs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sub.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-subs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sub.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-subs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sub.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-subs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sub.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-subs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-subs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-subs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-sub.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sub.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-RSB{S}.W Rd, Rn, Rm, {shift}
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N V
-rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000 ZC
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N V
-rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-rsb.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-rsb.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsbs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-rsbs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-rsbs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-rsb.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-rsb.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ADC{S}.W Rd, Rn, Rm, {shift}
-adcs.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-adc.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000 ZCV
-adcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-adcs.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-adc.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000 Z
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z
-adcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-adcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-adcs.w r1, r2, r3, lsl #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-adc.w r1, r2, r3, lsl #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-adc.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-adcs.w r1, r2, r3, lsl #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-adc.w r1, r2, r3, lsl #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000 ZC
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-adcs.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-adc.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-adcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-adc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-adcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-adc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-adc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-SBC{S}.W Rd, Rn, Rm, {shift}
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
-sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-sbc.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000 CV
-sbc.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000 ZCV
-sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000 CV
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbc.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000 ZC
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N
-sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C
-sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000 Z
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000 Z
-sbc.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000 CV
-sbc.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbc.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N V
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000 ZC
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000 ZC
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000
-sbc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-sbc.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N
-sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbcs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-sbcs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000 ZC
-sbcs.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000 C
-sbc.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-sbc.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-AND{S}.W Rd, Rn, Rm, {shift}
-ands.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-and.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-ands.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-and.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-ands.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-and.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ands.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-and.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-ands.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-and.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-and.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ands.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-and.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-ands.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-and.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000
-ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-ands.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-and.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ands.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-and.w r1, r2, r3, lsl #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-ands.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-and.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-ands.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-and.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ands.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-ands.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-and.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-and.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ORR{S}.W Rd, Rn, Rm, {shift}
-orrs.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-orr.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-orr.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orr.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-orrs.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-orr.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-orr.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orr.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-orrs.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-orr.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-orrs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-orr.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orr.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-orrs.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-orr.w r1, r2, r3, lsl #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-orr.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orr.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orrs.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-orrs.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-orr.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-orr.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-EOR{S}.W Rd, Rn, Rm, {shift}
-eors.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-eor.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-eors.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-eor.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-eors.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-eor.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000
-eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-eors.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-eor.w r1, r2, r3, lsl #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eor.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eors.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-eors.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-eors.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-eor.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #1 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-eor.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-BIC{S}.W Rd, Rn, Rm, {shift}
-bics.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000
-bic.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bic.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bic.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bics.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000 V
-bic.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bic.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bic.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-bics.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000
-bic.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bic.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N
-bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x40000000 Z
-bic.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x40000000 Z
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000
-bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-bics.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bic.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-bics.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000 V
-bic.w r1, r2, r3, lsl #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000 V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bic.w r1, r2, r3, lsl #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x50000000 Z V
-bic.w r1, r2, r3, lsl #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x50000000 Z V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-bic.w r1, r2, r3, lsl #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bics.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-bics.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-bic.w r1, r2, r3, lsl #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #1 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #0 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #1 :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-bic.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T?) LSL{S}.W Rd, Rn, Rm
-lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0x80000000 N
-lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0x80000000 N
-lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0x20000000 C
-lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C
-lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0x60000000 ZC
-lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z
-lsl.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ
-lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0x90000000 N V
-lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0x90000000 N V
-lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0x30000000 CV
-lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV
-lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0x70000000 ZCV
-lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V
-lsl.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
-lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0x80000000 N
-lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0x80000000 N
-lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0x20000000 C
-lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C
-lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0x60000000 ZC
-lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z
-lsl.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC
-lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V
-lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0x90000000 N V
-lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0x90000000 N V
-lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0x30000000 CV
-lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV
-lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0x70000000 ZCV
-lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V
-lsl.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
-(T?) LSR{S}.W Rd, Rn, Rm
-lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C
-lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0x20000000 C
-lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0x20000000 C
-lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0x00000000
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0x40000000 Z
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0x40000000 Z
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z
-lsr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ
-lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0x30000000 CV
-lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0x30000000 CV
-lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0x30000000 CV
-lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0x10000000 V
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0x50000000 Z V
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0x50000000 Z V
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V
-lsr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
-lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0x00000000
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0x40000000 Z
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0x40000000 Z
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z
-lsr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC
-lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0x10000000 V
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0x50000000 Z V
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0x50000000 Z V
-lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V
-lsr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
-(T?) ASR{S}.W Rd, Rn, Rm
-asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0x20000000 C
-asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 0, cpsr 0xa0000000 N C
-asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0x00000000
-asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 0, cpsr 0x80000000 N
-asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0x40000000 Z
-asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 0, cpsr 0xa0000000 N C
-asr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ
-asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
-asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0x30000000 CV
-asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 1, cpsr 0xb0000000 N CV
-asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0x10000000 V
-asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 1, cpsr 0x90000000 N V
-asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0x50000000 Z V
-asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV
-asr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
-asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0x20000000 C
-asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 2, cpsr 0xa0000000 N C
-asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0x00000000
-asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 2, cpsr 0x80000000 N
-asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0x40000000 Z
-asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 2, cpsr 0xa0000000 N C
-asr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC
-asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0x30000000 CV
-asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 3, cpsr 0xb0000000 N CV
-asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0x10000000 V
-asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 3, cpsr 0x90000000 N V
-asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0x50000000 Z V
-asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV
-asr.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
-MVN{S}.W Rd, Rn, shift, and MOV{S}.W ditto
-lsls.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-lsrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-lsrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-lsrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-asrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-asrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-asrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-rors.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-rors.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-rors.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-rors.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-lsl.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvns.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-mvn.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsls.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-lsls.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-lsls.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-lsls.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-lsrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-asrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-rors.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-rors.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-rors.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-rors.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-lsl.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvns.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvn.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsls.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-lsls.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-lsls.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-lsrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-asrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x60000000 ZC
-asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000 Z
-rors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-rors.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-rors.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-rors.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-lsl.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvns.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0x00000000
-mvns.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvn.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsls.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-lsls.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 0, cpsr 0x20000000 C
-lsls.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-lsrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-lsrs.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0x20000000 C
-lsrs.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-asrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-asrs.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C
-asrs.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-asrs.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-rors.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-rors.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C
-rors.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-rors.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-lsl.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvns.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-mvns.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-mvns.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-mvns.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-mvns.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 0, cpsr 0x40000000 Z
-mvns.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000
-mvns.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-mvns.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N
-mvn.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ
-lsls.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-lsrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-lsrs.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-lsrs.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-asrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-asrs.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-asrs.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-asrs.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-rors.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rors.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-rors.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-lsl.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-ror.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvns.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-mvns.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-mvns.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-mvns.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-mvns.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-mvns.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000 Z
-mvns.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-mvns.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-mvns.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-mvn.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsls.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-lsrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-lsrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-lsrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-asrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-asrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-asrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-rors.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-rors.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-rors.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-rors.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-lsl.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvns.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-mvn.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsls.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-lsls.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-lsls.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-lsls.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-lsrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-asrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-rors.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-rors.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-rors.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-rors.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-lsl.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvns.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvn.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-lsls.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsls.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsls.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-lsrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-asrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x70000000 ZCV
-asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000 Z V
-rors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-rors.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
-rors.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-rors.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsl.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvns.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-mvns.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvn.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsls.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-lsls.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 1, cpsr 0x30000000 CV
-lsls.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-lsrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-lsrs.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0x30000000 CV
-lsrs.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-asrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-asrs.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV
-asrs.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-asrs.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-rors.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-rors.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV
-rors.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-rors.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-lsl.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvns.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-mvns.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-mvns.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-mvns.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-mvns.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 1, cpsr 0x50000000 Z V
-mvns.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000 V
-mvns.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N V
-mvn.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
-lsls.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-lsrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-lsrs.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-lsrs.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-asrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-asrs.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-asrs.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-asrs.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-rors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-rors.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-rors.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-rors.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-lsl.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsr.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-ror.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvns.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-mvns.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-mvns.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-mvns.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-mvns.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000 Z V
-mvns.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-mvns.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-mvns.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-mvn.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsls.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N
-lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-asrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-asrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-asrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-rors.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-rors.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-rors.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-rors.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsl.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvns.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0x00000000
-mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-mvn.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsls.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-lsls.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-lsls.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-lsls.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-lsrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-asrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-rors.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-rors.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-rors.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-rors.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-lsl.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvns.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N
-mvn.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-lsls.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-lsls.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-lsls.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-lsrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-asrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000 ZC
-asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000 Z
-rors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-rors.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-rors.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-rors.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-lsl.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvns.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0x00000000
-mvns.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-mvn.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsls.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C
-lsls.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C
-lsls.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N
-lsrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C
-lsrs.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000
-lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000
-asrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C
-asrs.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C
-asrs.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N
-asrs.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N
-rors.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C
-rors.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C
-rors.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000
-rors.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 2, cpsr 0x00000000
-lsl.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvns.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 2, cpsr 0x00000000
-mvns.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 2, cpsr 0x00000000
-mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 2, cpsr 0x40000000 Z
-mvns.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N
-mvns.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N
-mvn.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC
-lsls.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsrs.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-asrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-asrs.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-asrs.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-asrs.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rors.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rors.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-rors.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsl.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsr.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-asr.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-ror.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvns.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-mvns.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvns.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-mvn.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsls.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N V
-lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-asrs.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-asrs.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-asrs.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-rors.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-rors.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-rors.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-rors.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsl.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #1 :: rd 0xbfffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvns.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0x10000000 V
-mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-mvn.w r1, r2, lsl #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #1 :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #0 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #1 :: rd 0x40000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsls.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-lsls.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-lsls.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-lsls.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-lsrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-asrs.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-rors.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-rors.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-rors.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-rors.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-lsl.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvns.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N V
-mvn.w r1, r2, lsl #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #0 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-lsls.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-lsls.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V
-lsls.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-lsrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-lsrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-lsrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-asrs.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-asrs.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000 ZCV
-asrs.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-asrs.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000 Z V
-rors.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-rors.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-rors.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V
-rors.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V
-lsl.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #1 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvns.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0x10000000 V
-mvns.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-mvn.w r1, r2, lsl #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #1 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #0 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #1 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsls.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
-lsls.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV
-lsls.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V
-lsrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
-lsrs.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V
-lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V
-asrs.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
-asrs.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
-asrs.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V
-asrs.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V
-rors.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
-rors.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
-rors.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V
-rors.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V
-lsl.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #1 :: rd 0x2431579a rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #1 :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #0 :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #1 :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvns.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V
-mvns.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 3, cpsr 0x10000000 V
-mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 3, cpsr 0x50000000 Z V
-mvns.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N V
-mvn.w r1, r2, lsl #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #1 :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #1 :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #0 :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #1 :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
-lsls.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsls.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsls.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsls.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsrs.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-lsrs.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-asrs.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-asrs.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-asrs.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-asrs.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-rors.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-rors.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-rors.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-rors.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsl.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl.w r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsr.w r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-ror.w r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvns.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvns.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-mvn.w r1, r2, lsl #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #1 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #1 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #0 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-(T?) TST.W Rn, Rm, {shift}
-tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x20000000 C
-tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000
-tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000
-tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000
-tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x80000000 N
-tst.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x40000000 Z
-tst.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-tst.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x30000000 CV
-tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V
-tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V
-tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V
-tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x90000000 N V
-tst.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x50000000 Z V
-tst.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N V
-tst.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
-tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x20000000 C
-tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000
-tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000
-tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000
-tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-tst.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x80000000 N
-tst.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x40000000 Z
-tst.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N
-tst.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x30000000 CV
-tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V
-tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V
-tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V
-tst.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-tst.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-tst.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-tst.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000 Z V
-tst.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x90000000 N V
-tst.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x50000000 Z V
-tst.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N V
-tst.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-(T?) TEQ.W Rn, Rm, {shift}
-teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x20000000 C
-teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000
-teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N
-teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000
-teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-teq.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x00000000
-teq.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x80000000 N
-teq.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x00000000
-teq.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0x20000000 C
-teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x30000000 CV
-teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x90000000 N V
-teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x90000000 N V
-teq.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x10000000 V
-teq.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0x30000000 CV
-teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x20000000 C
-teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000
-teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N
-teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000
-teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-teq.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x00000000
-teq.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x80000000 N
-teq.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x00000000
-teq.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x30000000 CV
-teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V
-teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x90000000 N V
-teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000 V
-teq.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000 V
-teq.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000 V
-teq.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000 V
-teq.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000 V
-teq.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x10000000 V
-teq.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x90000000 N V
-teq.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x10000000 V
-teq.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-(T?) CMP.W Rn, Rm, {shift}
-cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N
-cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N
-cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000
-cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N
-cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000 C
-cmp.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x30000000 CV
-cmp.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-cmp.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 0, cpsr 0x60000000 ZC
-cmp.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0x60000000 ZC
-cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N
-cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N
-cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000
-cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N
-cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C
-cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C
-cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000 C
-cmp.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x30000000 CV
-cmp.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
-cmp.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 1, cpsr 0x60000000 ZC
-cmp.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 1, cpsr 0x60000000 ZC
-cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N
-cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N
-cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000
-cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N
-cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-cmp.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x30000000 CV
-cmp.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N
-cmp.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 2, cpsr 0x60000000 ZC
-cmp.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 2, cpsr 0x60000000 ZC
-cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N
-cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N
-cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000
-cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N
-cmp.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C
-cmp.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C
-cmp.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000 C
-cmp.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x30000000 CV
-cmp.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N
-cmp.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0x20000000 C
-cmp.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 3, cpsr 0x60000000 ZC
-cmp.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 3, cpsr 0x60000000 ZC
-(T?) CMN.W Rn, Rm, {shift}
-cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000
-cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000
-cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N
-cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000
-cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-cmn.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x30000000 CV
-cmn.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x80000000 N
-cmn.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x30000000 CV
-cmn.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0x30000000 CV
-cmn.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 0, cpsr 0x00000000
-cmn.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0x90000000 N V
-cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000
-cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000
-cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N
-cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000
-cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000
-cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000
-cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000
-cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000
-cmn.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x30000000 CV
-cmn.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x80000000 N
-cmn.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x30000000 CV
-cmn.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0x30000000 CV
-cmn.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 1, cpsr 0x00000000
-cmn.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 1, cpsr 0x90000000 N V
-cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000
-cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000
-cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N
-cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000
-cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000
-cmn.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x30000000 CV
-cmn.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x80000000 N
-cmn.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x30000000 CV
-cmn.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0x30000000 CV
-cmn.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 2, cpsr 0x00000000
-cmn.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 2, cpsr 0x90000000 N V
-cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000
-cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000
-cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N
-cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000
-cmn.w r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-cmn.w r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-cmn.w r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-cmn.w r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000
-cmn.w r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x30000000 CV
-cmn.w r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x80000000 N
-cmn.w r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-cmn.w r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-cmn.w r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 3, cpsr 0x00000000
-cmn.w r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 3, cpsr 0x90000000 N V
-(T2) MOV{S}.W Rd, #constT
-movs.w r9, 0x00000000 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-movs.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x43434343 :: rd 0x43434343, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x93939393 :: rd 0x93939393, c:v-in 0, cpsr 0x80000000 N
-movs.w r9, 0x93000000 :: rd 0x93000000, c:v-in 0, cpsr 0xa0000000 N C
-movs.w r9, 0x43000000 :: rd 0x43000000, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x09300000 :: rd 0x09300000, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x04300000 :: rd 0x04300000, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x00930000 :: rd 0x00930000, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x00430000 :: rd 0x00430000, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x00000930 :: rd 0x00000930, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x00000430 :: rd 0x00000430, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x00000093 :: rd 0x00000093, c:v-in 0, cpsr 0x00000000
-movs.w r9, 0x00000043 :: rd 0x00000043, c:v-in 0, cpsr 0x00000000
-mov.w r9, 0x00000000 :: rd 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x43434343 :: rd 0x43434343, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x93939393 :: rd 0x93939393, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x93000000 :: rd 0x93000000, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x43000000 :: rd 0x43000000, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x09300000 :: rd 0x09300000, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x04300000 :: rd 0x04300000, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x00930000 :: rd 0x00930000, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x00430000 :: rd 0x00430000, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x00000930 :: rd 0x00000930, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x00000430 :: rd 0x00000430, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x00000093 :: rd 0x00000093, c:v-in 0, cpsr 0xc0000000 NZ
-mov.w r9, 0x00000043 :: rd 0x00000043, c:v-in 0, cpsr 0xc0000000 NZ
-movs.w r9, 0x00000000 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-movs.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x43434343 :: rd 0x43434343, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x93939393 :: rd 0x93939393, c:v-in 1, cpsr 0x90000000 N V
-movs.w r9, 0x93000000 :: rd 0x93000000, c:v-in 1, cpsr 0xb0000000 N CV
-movs.w r9, 0x43000000 :: rd 0x43000000, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x09300000 :: rd 0x09300000, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x04300000 :: rd 0x04300000, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x00930000 :: rd 0x00930000, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x00430000 :: rd 0x00430000, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x00000930 :: rd 0x00000930, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x00000430 :: rd 0x00000430, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x00000093 :: rd 0x00000093, c:v-in 1, cpsr 0x10000000 V
-movs.w r9, 0x00000043 :: rd 0x00000043, c:v-in 1, cpsr 0x10000000 V
-mov.w r9, 0x00000000 :: rd 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x43434343 :: rd 0x43434343, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x93939393 :: rd 0x93939393, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x93000000 :: rd 0x93000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x43000000 :: rd 0x43000000, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x09300000 :: rd 0x09300000, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x04300000 :: rd 0x04300000, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x00930000 :: rd 0x00930000, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x00430000 :: rd 0x00430000, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x00000930 :: rd 0x00000930, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x00000430 :: rd 0x00000430, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x00000093 :: rd 0x00000093, c:v-in 1, cpsr 0xd0000000 NZ V
-mov.w r9, 0x00000043 :: rd 0x00000043, c:v-in 1, cpsr 0xd0000000 NZ V
-movs.w r9, 0x00000000 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-movs.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 2, cpsr 0x20000000 C
-movs.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 2, cpsr 0x20000000 C
-movs.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 2, cpsr 0x20000000 C
-movs.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 2, cpsr 0x20000000 C
-movs.w r9, 0x43434343 :: rd 0x43434343, c:v-in 2, cpsr 0x20000000 C
-movs.w r9, 0x93939393 :: rd 0x93939393, c:v-in 2, cpsr 0xa0000000 N C
-movs.w r9, 0x93000000 :: rd 0x93000000, c:v-in 2, cpsr 0xa0000000 N C
-movs.w r9, 0x43000000 :: rd 0x43000000, c:v-in 2, cpsr 0x00000000
-movs.w r9, 0x09300000 :: rd 0x09300000, c:v-in 2, cpsr 0x00000000
-movs.w r9, 0x04300000 :: rd 0x04300000, c:v-in 2, cpsr 0x00000000
-movs.w r9, 0x00930000 :: rd 0x00930000, c:v-in 2, cpsr 0x00000000
-movs.w r9, 0x00430000 :: rd 0x00430000, c:v-in 2, cpsr 0x00000000
-movs.w r9, 0x00000930 :: rd 0x00000930, c:v-in 2, cpsr 0x00000000
-movs.w r9, 0x00000430 :: rd 0x00000430, c:v-in 2, cpsr 0x00000000
-movs.w r9, 0x00000093 :: rd 0x00000093, c:v-in 2, cpsr 0x20000000 C
-movs.w r9, 0x00000043 :: rd 0x00000043, c:v-in 2, cpsr 0x20000000 C
-mov.w r9, 0x00000000 :: rd 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x43434343 :: rd 0x43434343, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x93939393 :: rd 0x93939393, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x93000000 :: rd 0x93000000, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x43000000 :: rd 0x43000000, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x09300000 :: rd 0x09300000, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x04300000 :: rd 0x04300000, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x00930000 :: rd 0x00930000, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x00430000 :: rd 0x00430000, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x00000930 :: rd 0x00000930, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x00000430 :: rd 0x00000430, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x00000093 :: rd 0x00000093, c:v-in 2, cpsr 0xe0000000 NZC
-mov.w r9, 0x00000043 :: rd 0x00000043, c:v-in 2, cpsr 0xe0000000 NZC
-movs.w r9, 0x00000000 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-movs.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 3, cpsr 0x30000000 CV
-movs.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 3, cpsr 0x30000000 CV
-movs.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 3, cpsr 0x30000000 CV
-movs.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 3, cpsr 0x30000000 CV
-movs.w r9, 0x43434343 :: rd 0x43434343, c:v-in 3, cpsr 0x30000000 CV
-movs.w r9, 0x93939393 :: rd 0x93939393, c:v-in 3, cpsr 0xb0000000 N CV
-movs.w r9, 0x93000000 :: rd 0x93000000, c:v-in 3, cpsr 0xb0000000 N CV
-movs.w r9, 0x43000000 :: rd 0x43000000, c:v-in 3, cpsr 0x10000000 V
-movs.w r9, 0x09300000 :: rd 0x09300000, c:v-in 3, cpsr 0x10000000 V
-movs.w r9, 0x04300000 :: rd 0x04300000, c:v-in 3, cpsr 0x10000000 V
-movs.w r9, 0x00930000 :: rd 0x00930000, c:v-in 3, cpsr 0x10000000 V
-movs.w r9, 0x00430000 :: rd 0x00430000, c:v-in 3, cpsr 0x10000000 V
-movs.w r9, 0x00000930 :: rd 0x00000930, c:v-in 3, cpsr 0x10000000 V
-movs.w r9, 0x00000430 :: rd 0x00000430, c:v-in 3, cpsr 0x10000000 V
-movs.w r9, 0x00000093 :: rd 0x00000093, c:v-in 3, cpsr 0x30000000 CV
-movs.w r9, 0x00000043 :: rd 0x00000043, c:v-in 3, cpsr 0x30000000 CV
-mov.w r9, 0x00000000 :: rd 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x000000FF :: rd 0x000000ff, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x0000007F :: rd 0x0000007f, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x007F007F :: rd 0x007f007f, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x43434343 :: rd 0x43434343, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x93939393 :: rd 0x93939393, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x93000000 :: rd 0x93000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x43000000 :: rd 0x43000000, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x09300000 :: rd 0x09300000, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x04300000 :: rd 0x04300000, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x00930000 :: rd 0x00930000, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x00430000 :: rd 0x00430000, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x00000930 :: rd 0x00000930, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x00000430 :: rd 0x00000430, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x00000093 :: rd 0x00000093, c:v-in 3, cpsr 0xf0000000 NZCV
-mov.w r9, 0x00000043 :: rd 0x00000043, c:v-in 3, cpsr 0xf0000000 NZCV
-(T2) MVN{S}.W Rd, #constT
-mvns.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 0, cpsr 0x00000000
-mvns.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 0, cpsr 0x20000000 C
-mvns.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 0, cpsr 0x80000000 N
-mvns.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 0, cpsr 0x80000000 N
-mvn.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 0, cpsr 0xc0000000 NZ
-mvn.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 0, cpsr 0xc0000000 NZ
-mvns.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 1, cpsr 0x10000000 V
-mvns.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 1, cpsr 0x30000000 CV
-mvns.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 1, cpsr 0x90000000 N V
-mvns.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 1, cpsr 0x90000000 N V
-mvn.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 1, cpsr 0xd0000000 NZ V
-mvn.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 1, cpsr 0xd0000000 NZ V
-mvns.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 2, cpsr 0x20000000 C
-mvns.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 2, cpsr 0x20000000 C
-mvns.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 2, cpsr 0x80000000 N
-mvns.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 2, cpsr 0x80000000 N
-mvns.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 2, cpsr 0x80000000 N
-mvns.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 2, cpsr 0x80000000 N
-mvns.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 2, cpsr 0x80000000 N
-mvns.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 2, cpsr 0x80000000 N
-mvns.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 2, cpsr 0x80000000 N
-mvns.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 2, cpsr 0xa0000000 N C
-mvns.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 2, cpsr 0xa0000000 N C
-mvn.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 2, cpsr 0xe0000000 NZC
-mvn.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 2, cpsr 0xe0000000 NZC
-mvns.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 3, cpsr 0x30000000 CV
-mvns.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 3, cpsr 0x90000000 N V
-mvns.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 3, cpsr 0xb0000000 N CV
-mvns.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 3, cpsr 0xb0000000 N CV
-mvn.w r9, 0x00000000 :: rd 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x000000FF :: rd 0xffffff00, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x0000007F :: rd 0xffffff80, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x007F007F :: rd 0xff80ff80, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x93000000 :: rd 0x6cffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x43000000 :: rd 0xbcffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x00930000 :: rd 0xff6cffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x00430000 :: rd 0xffbcffff, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x00000093 :: rd 0xffffff6c, c:v-in 3, cpsr 0xf0000000 NZCV
-mvn.w r9, 0x00000043 :: rd 0xffffffbc, c:v-in 3, cpsr 0xf0000000 NZCV
-MOV
-mov r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-cpy r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mov r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mov r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
-movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N
-movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z V
-movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000 V
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000 Z
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N
-movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000 ZC
-movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000 C
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x00000000
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x40000000 Z
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N
-movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000 ZCV
-movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-MVN
-mvn r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x10000000 V
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 2, cpsr 0x20000000 C
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 3, cpsr 0x30000000 CV
-ADD
-adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, c:v-in 0, cpsr 0x90000000 N V
-adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, c:v-in 0, cpsr 0x30000000 CV
-adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-ADC
-adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000 Z
-adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000 Z
-LSL
-lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ
-LSLS
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0x60000000 ZC
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0x80000000 N
-lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 0, cpsr 0x80000000 N
-lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 0, cpsr 0x60000000 ZC
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
-lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0xb0000000 N CV
-lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0x70000000 ZCV
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0x50000000 Z V
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0x50000000 Z V
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0x50000000 Z V
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 1, cpsr 0x90000000 N V
-lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 1, cpsr 0x90000000 N V
-lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 1, cpsr 0x70000000 ZCV
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0x60000000 ZC
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0x40000000 Z
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 2, cpsr 0xa0000000 N C
-lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 2, cpsr 0x80000000 N
-lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 2, cpsr 0x60000000 ZC
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0xb0000000 N CV
-lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0x70000000 ZCV
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0x50000000 Z V
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0x50000000 Z V
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0x50000000 Z V
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 3, cpsr 0xb0000000 N CV
-lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V
-lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 3, cpsr 0x90000000 N V
-lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 3, cpsr 0x70000000 ZCV
-LSL immediate
-lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
-lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC
-lsl r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-lsl r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
-LSLS immediate
-lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0x00000000
-lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0x80000000 N
-lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 0, cpsr 0x60000000 ZC
-lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0x10000000 V
-lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0x90000000 N V
-lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 1, cpsr 0x70000000 ZCV
-lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000 C
-lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000
-lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0x80000000 N
-lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 2, cpsr 0x60000000 ZC
-lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x10000000 V
-lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0x90000000 N V
-lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 3, cpsr 0x70000000 ZCV
-LSR
-lsr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ
-LSRS
-lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0x60000000 ZC
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0x30000000 CV
-lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0x30000000 CV
-lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0x30000000 CV
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0x70000000 ZCV
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0x50000000 Z V
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0x50000000 Z V
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0x50000000 Z V
-lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0x20000000 C
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0x60000000 ZC
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0x40000000 Z
-lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0x30000000 CV
-lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0x30000000 CV
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0x70000000 ZCV
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0x50000000 Z V
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0x50000000 Z V
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0x50000000 Z V
-LSR immediate
-lsr r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ
-lsr r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ
-LSRS immediate
-lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x20000000 C
-lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000 ZC
-lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0x00000000
-lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x60000000 ZC
-lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x40000000 Z
-lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x30000000 CV
-lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000 ZCV
-lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 1, cpsr 0x10000000 V
-lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x70000000 ZCV
-lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x50000000 Z V
-lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x20000000 C
-lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000 ZC
-lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 2, cpsr 0x00000000
-lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x60000000 ZC
-lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x40000000 Z
-lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x30000000 CV
-lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000 ZCV
-lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 3, cpsr 0x10000000 V
-lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x70000000 ZCV
-lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x50000000 Z V
-ASR
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 1, cpsr 0xd0000000 NZ V
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 2, cpsr 0xe0000000 NZC
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 3, cpsr 0xf0000000 NZCV
-asr r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 3, cpsr 0xf0000000 NZCV
-ASRS
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0x80000000 N
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 0, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 0, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 0, cpsr 0x60000000 ZC
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N V
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 1, cpsr 0x90000000 N V
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 1, cpsr 0x30000000 CV
-asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 1, cpsr 0x30000000 CV
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 1, cpsr 0x70000000 ZCV
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 1, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 1, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 1, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 1, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 1, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 1, cpsr 0x10000000 V
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 2, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 2, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 2, cpsr 0x60000000 ZC
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 2, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 2, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 2, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 2, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 2, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 2, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 3, cpsr 0x30000000 CV
-asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 3, cpsr 0x30000000 CV
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 3, cpsr 0x70000000 ZCV
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 3, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 3, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 3, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 3, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 3, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 3, cpsr 0x30000000 CV
-asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 0, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 0, cpsr 0x60000000 ZC
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 0, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 1, cpsr 0x10000000 V
-asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 1, cpsr 0x10000000 V
-asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 1, cpsr 0x10000000 V
-asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 1, cpsr 0x10000000 V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 1, cpsr 0x70000000 ZCV
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 1, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 2, cpsr 0x20000000 C
-asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 2, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 2, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 2, cpsr 0x00000000
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 2, cpsr 0x60000000 ZC
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 2, cpsr 0x40000000 Z
-asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 3, cpsr 0x30000000 CV
-asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 3, cpsr 0x10000000 V
-asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 3, cpsr 0x10000000 V
-asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 3, cpsr 0x10000000 V
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 3, cpsr 0x70000000 ZCV
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 3, cpsr 0x50000000 Z V
-asrs r0, r1, r2 :: rd 0xc0000000 rm 0x80000001, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, r2 :: rd 0xe0000000 rm 0x80000001, rn 0x00000002, c:v-in 0, cpsr 0x80000000 N
-ASR immediate
-asr r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ
-asr r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ
-ASRS immediate
-asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N
-asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C
-asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000
-asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000 C
-asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000 ZC
-asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x40000000 Z
-asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0x00000000
-asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x60000000 ZC
-asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x40000000 Z
-asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N V
-asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
-asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000 V
-asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000 CV
-asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000 ZCV
-asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x50000000 Z V
-asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 1, cpsr 0x10000000 V
-asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x70000000 ZCV
-asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x50000000 Z V
-asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C
-asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000 C
-asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000 ZC
-asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x40000000 Z
-asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 2, cpsr 0x00000000
-asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x60000000 ZC
-asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x40000000 Z
-asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
-asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000 CV
-asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000 ZCV
-asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x50000000 Z V
-asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 3, cpsr 0x10000000 V
-asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x70000000 ZCV
-asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x50000000 Z V
-MUL
-mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
-mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ
-MLA
-mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mla r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mla r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-MLS
-mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mls r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mls r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mls r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-mls r0, r1, r2, r3 :: rd 0x00020000 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-UMULL
-umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-umull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ
-umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-SMULL
-smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-smull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ
-smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-CLZ
-clz r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-clz r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-clz r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ
-clz r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-clz r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
-clz r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
-clz r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V
-clz r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
-clz r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC
-clz r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC
-clz r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC
-clz r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC
-clz r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
-clz r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
-clz r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV
-clz r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
-extend instructions
-uxtb r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r0, r1 :: rd 0x000000ff rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r0, r1 :: rd 0x000000ff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ
-sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-uxth r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-uxth r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-uxth r0, r1 :: rd 0x0000ffff rm 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ
-uxth r0, r1 :: rd 0x0000ffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-sxth r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sxth r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, c:v-in 0, cpsr 0xc0000000 NZ
-sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ
-sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, c:v-in 0, cpsr 0xc0000000 NZ
-sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, c:v-in 0, cpsr 0xc0000000 NZ
-sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, c:v-in 0, cpsr 0xc0000000 NZ
-uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, c:v-in 0, cpsr 0xc0000000 NZ
------------- BFI ------------
-bfi r0, r1, #0, #11 :: rd 0x555552aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #1, #11 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #2, #11 :: rd 0x55554aa9 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #19, #11 :: rd 0x7ffd5555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #20, #11 :: rd 0x7ff55555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #21, #11 :: rd 0xfff55555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #0, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #29, #3 :: rd 0xf5555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #30, #2 :: rd 0xd5555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfi r0, r1, #31, #1 :: rd 0xd5555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
------------- BFC ------------
-bfc r0, #0, #11 :: rd 0x55555000 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #1, #11 :: rd 0x55555001 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #2, #11 :: rd 0x55554001 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #19, #11 :: rd 0x40055555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #20, #11 :: rd 0x00055555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #21, #11 :: rd 0x00155555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #0, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #29, #3 :: rd 0x15555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #30, #2 :: rd 0x15555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
-bfc r0, #31, #1 :: rd 0x55555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
------------- SBFX ------------
-sbfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #0, #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #1, #11 :: rd 0xfffffd55 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #31, #1 :: rd 0xffffffff rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-sbfx r0, r1, #30, #2 :: rd 0xfffffffe rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
------------- UBFX ------------
-ubfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #0, #1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #1, #11 :: rd 0x00000555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #31, #1 :: rd 0x00000001 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
-ubfx r0, r1, #30, #2 :: rd 0x00000002 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ
------------- SMULL{B,T}{B,T} ------------
-smulbb r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00040000, c:v-in 0, cpsr 0xc0000000 NZ
-smulbb r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00040002, c:v-in 0, cpsr 0xc0000000 NZ
-smulbb r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x00047fff, c:v-in 0, cpsr 0xc0000000 NZ
-smulbb r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x00047fff, c:v-in 0, cpsr 0xc0000000 NZ
-smulbb r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0x0004ffff, c:v-in 0, cpsr 0xc0000000 NZ
------------- SXTAB ------------
-sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ
-sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ
-sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ
-sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ
------------- UXTAB ------------
-uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ
-uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ
-uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ
-uxtab r0, r1, r2, ROR #0 :: rd 0x314159c0 rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ
------------- SXTAH ------------
-sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
-sxtah r0, r1, r2, ROR #0 :: rd 0x3140f140 rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
------------- UXTAH ------------
-uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
-uxtah r0, r1, r2, ROR #0 :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ
+------------ SMMUL ------------
+smmul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0x00000000 rm 0x0000ffff, rn 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0x048e8c61 rm 0xe444dc25, rn 0xd5eef620, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0xfd764d51 rm 0x06ea9b2a, rn 0xa2108661, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0x0657af1f rm 0x448f3a5f, rn 0x17aecf57, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0xffe5afbd rm 0x4b0c2337, rn 0xffa63d6c, c:v-in 0, cpsr 0xc0000000 NZ
+smmul r0, r1, r2 :: rd 0xffc528bc rm 0xf91d5f56, rn 0x088bc0f9, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0x00000001 rm 0x0000ffff, rn 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0x048e8c61 rm 0xe444dc25, rn 0xd5eef620, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0xfd764d52 rm 0x06ea9b2a, rn 0xa2108661, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0x0657af1f rm 0x448f3a5f, rn 0x17aecf57, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0xffe5afbd rm 0x4b0c2337, rn 0xffa63d6c, c:v-in 0, cpsr 0xc0000000 NZ
+smmulr r0, r1, r2 :: rd 0xffc528bd rm 0xf91d5f56, rn 0x088bc0f9, c:v-in 0, cpsr 0xc0000000 NZ
diff --git a/main/none/tests/arm/v6intThumb.vgtest b/main/none/tests/arm/v6intThumb.vgtest
index 49db7b9..362326d 100644
--- a/main/none/tests/arm/v6intThumb.vgtest
+++ b/main/none/tests/arm/v6intThumb.vgtest
@@ -1,4 +1,2 @@
prog: v6intThumb
vgopts: -q
-prog: v6intThumb
-vgopts: -q
diff --git a/main/none/tests/arm/v6media.c b/main/none/tests/arm/v6media.c
index 2085cd7..5b48a21 100644
--- a/main/none/tests/arm/v6media.c
+++ b/main/none/tests/arm/v6media.c
@@ -2863,6 +2863,67 @@
TESTINST3("uhadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
TESTINST3("uhadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
+ printf("------------ UHADD16 -----------------------------------\n");
+ TESTINST3("uhadd16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
+ TESTINST3("uhadd16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
+ TESTINST3("uhadd16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
+ TESTINST3("uhadd16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
+ TESTINST3("uhadd16 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("uhadd16 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0);
+ TESTINST3("uhadd16 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("uhadd16 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
+TESTINST3("uhadd16 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
+
printf("----------------- SSAT ----------------- \n");
TESTINST2("ssat r0, #1, r1, LSL #31", 0x80008000, r0, r1, 0);
TESTINST2("ssat r0, #6, r1, LSL #24", 0x80008000, r0, r1, 0);
@@ -4073,3041 +4134,121 @@
TESTINST4("usada8 r0, r1, r2, r3",
0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0);
+ printf("---------------- QADD ---------------- \n");
+ TESTINST3("qadd r0, r1, r2", 0x00000000, 0x7fffffff, r0, r1, r2, 0);
+ TESTINST3("qadd r0, r1, r2", 0x00000001, 0x7fffffff, r0, r1, r2, 0);
+ TESTINST3("qadd r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("qadd r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
+TESTINST3("qadd r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
-
-/*
-TESTINST3("theinsn", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("theinsn", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("theinsn", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("theinsn", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("theinsn", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("theinsn", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("theinsn", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("theinsn", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("theinsn", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("theinsn", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-*/
-
- return 0;
-}
-
-/* How to compile:
- gcc -marm -O -g -Wall -mcpu=cortex-a8 -o test_arm_v6int v6int.c
-*/
-
-#include <stdio.h>
-
-static int gen_cin(cin)
-{
- int r = ((cin & 1) ? (1<<29) : 0);
- //r |= (1 << 31) | (1 << 30);
- return r;
-}
-
-/* test macros to generate and output the result of a single instruction */
-#define TESTINST2(instruction, RMval, RD, RM, carryin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_fs, %3;" \
- "mov " #RM ",%2;" \
- /* set #RD to 0x55555555 so we can see which parts get overwritten */ \
- "mov " #RD ", #0x55" "\n\t" \
- "orr " #RD "," #RD "," #RD ", LSL #8" "\n\t" \
- "orr " #RD "," #RD "," #RD ", LSL #16" "\n\t" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (gen_cin(carryin)) \
- : #RD, #RM, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
- instruction, out, RMval, \
- carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ', \
- ((1<<27) & cpsr) ? 'Q' : ' ', \
- (cpsr >> 19) & 1, (cpsr >> 18) & 1, (cpsr >> 17) & 1, (cpsr >> 16) & 1 \
- ); \
-}
-
-#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_fs, %4;" \
- "mov " #RM ",%2;" \
- "mov " #RN ",%3;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (RNval), "r" (gen_cin(carryin)) \
- : #RD, #RM, #RN, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
- instruction, out, RMval, RNval, \
- carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ', \
- ((1<<27) & cpsr) ? 'Q' : ' ', \
- (cpsr >> 19) & 1, (cpsr >> 18) & 1, (cpsr >> 17) & 1, (cpsr >> 16) & 1 \
- ); \
-}
-
-#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \
-{ \
- unsigned int out; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_fs, %5;" \
- "mov " #RM ",%2;" \
- "mov " #RN ",%3;" \
- "mov " #RS ",%4;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,cpsr;" \
- : "=&r" (out), "=&r" (cpsr) \
- : "r" (RMval), "r" (RNval), "r" (RSval), "r" (gen_cin(carryin)) \
- : #RD, #RM, #RN, #RS, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
- instruction, out, RMval, RNval, RSval, \
- carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ', \
- ((1<<27) & cpsr) ? 'Q' : ' ', \
- (cpsr >> 19) & 1, (cpsr >> 18) & 1, (cpsr >> 17) & 1, (cpsr >> 16) & 1 \
- ); \
-}
-
-#define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \
-{ \
- unsigned int out; \
- unsigned int out2; \
- unsigned int cpsr; \
-\
- __asm__ volatile( \
- "msr cpsr_fs, %7;" \
- "mov " #RD ",%3;" \
- "mov " #RD2 ",%4;" \
- "mov " #RM ",%5;" \
- "mov " #RS ",%6;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mov %1," #RD2 ";" \
- "mrs %2,cpsr;" \
- : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \
- : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (gen_cin(carryin)) \
- : #RD, #RD2, #RM, #RS, "cc", "memory" \
- ); \
- printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
- instruction, out, out2, RMval, RSval, \
- carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
- ((1<<31) & cpsr) ? 'N' : ' ', \
- ((1<<30) & cpsr) ? 'Z' : ' ', \
- ((1<<29) & cpsr) ? 'C' : ' ', \
- ((1<<28) & cpsr) ? 'V' : ' ', \
- ((1<<27) & cpsr) ? 'Q' : ' ', \
- (cpsr >> 19) & 1, (cpsr >> 18) & 1, (cpsr >> 17) & 1, (cpsr >> 16) & 1 \
- ); \
-}
-
-/* helpers */
-#define TESTCARRY { int c = 0; for (c = 0; c < 2; c++) {
-#define TESTCARRYEND }}
-
-
-
-
-int main(int argc, char **argv)
-{
- printf("MUL\n");
- TESTINST3("mul r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
- TESTINST3("mul r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
-
-#if 0
- printf("MULS\n");
- TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
- TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
-#endif
-
- printf("MLA\n");
- TESTINST4("mla r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mla r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
-#if 0
- printf("MLAS\n");
- TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mlas r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-#endif
-
- printf("MLS\n");
- TESTINST4("mls r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
- TESTINST4("mls r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
- printf("UMULL\n");
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#if 0
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
- printf("SMULL\n");
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smull r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#if 0
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
-
- printf("UMLAL\n");
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#if 0
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
-
- printf("SMLAL\n");
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlal r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#if 0
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
- TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-#endif
-
- printf("CLZ\n");
- TESTCARRY
- TESTINST2("clz r0, r1", 0, r0, r1, c);
- TESTINST2("clz r0, r1", 1, r0, r1, c);
- TESTINST2("clz r0, r1", 0x10, r0, r1, c);
- TESTINST2("clz r0, r1", 0xffffffff, r0, r1, c);
- TESTCARRYEND
-
- printf("extend instructions\n");
- TESTINST2("uxtb r0, r1", 0, r0, r1, 0);
- TESTINST2("uxtb r0, r1", 1, r0, r1, 0);
- TESTINST2("uxtb r0, r1", 0xff, r0, r1, 0);
- TESTINST2("uxtb r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 0, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 1, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 0xff, r0, r1, 0);
- TESTINST2("sxtb r0, r1", 0xffffffff, r0, r1, 0);
-
- TESTINST2("uxth r0, r1", 0, r0, r1, 0);
- TESTINST2("uxth r0, r1", 1, r0, r1, 0);
- TESTINST2("uxth r0, r1", 0xffff, r0, r1, 0);
- TESTINST2("uxth r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0, r0, r1, 0);
- TESTINST2("sxth r0, r1", 1, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0x7fff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0xffff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0x10ffff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0x107fff, r0, r1, 0);
- TESTINST2("sxth r0, r1", 0xffffffff, r0, r1, 0);
-
- TESTINST2("uxtb r0, r1, ror #0", 0x000000ff, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #8", 0x000000ff, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #8", 0x0000ff00, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #16", 0x00ff0000, r0, r1, 0);
- TESTINST2("uxtb r0, r1, ror #24", 0xff000000, r0, r1, 0);
-
- TESTINST2("uxtb16 r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("uxtb16 r0, r1, ror #16", 0x0000ffff, r0, r1, 0);
- TESTINST2("sxtb16 r0, r1", 0xffffffff, r0, r1, 0);
- TESTINST2("sxtb16 r0, r1", 0x00ff00ff, r0, r1, 0);
- TESTINST2("sxtb16 r0, r1", 0x007f007f, r0, r1, 0);
-
- printf("------------ BFI ------------\n");
- /* bfi rDst, rSrc, #lsb-in-dst, #number-of-bits-to-copy */
- TESTINST2("bfi r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfi r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfi r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("bfi r0, r1, #19, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #20, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #21, #11", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfi r0, r1, #0, #32", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #1, #31", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfi r0, r1, #29, #3", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #30, #2", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfi r0, r1, #31, #1", 0xFFFFFFFF, r0, r1, 0);
-
- printf("------------ BFC ------------\n");
- /* bfi rDst, #lsb-in-dst, #number-of-bits-to-copy */
- TESTINST2("bfc r0, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfc r0, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("bfc r0, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
- TESTINST2("bfc r0, #19, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #20, #11", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #21, #11", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfc r0, #0, #32", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #1, #31", 0xFFFFFFFF, r0, r1, 0);
-
- TESTINST2("bfc r0, #29, #3", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #30, #2", 0xFFFFFFFF, r0, r1, 0);
- TESTINST2("bfc r0, #31, #1", 0xFFFFFFFF, r0, r1, 0);
-
- printf("------------ SBFX ------------\n");
- /* sbfx rDst, rSrc, #lsb, #width */
- TESTINST2("sbfx r0, r1, #0, #1", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #0, #1", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000002, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #1", 0x00000003, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #0, #2", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #0, #2", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000000, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000001, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000002, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #2", 0x00000003, r0, r1, 0);
-
- TESTINST2("sbfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("sbfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
-
- printf("------------ UBFX ------------\n");
- /* ubfx rDst, rSrc, #lsb, #width */
- TESTINST2("ubfx r0, r1, #0, #1", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #0, #1", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000002, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #1", 0x00000003, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #0, #2", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #0, #2", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000000, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000001, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000002, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #2", 0x00000003, r0, r1, 0);
-
- TESTINST2("ubfx r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
- TESTINST2("ubfx r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
-
- printf("------------ SMUL{B,T}{B,T} ------------\n");
- /* SMULbb rD, rN, rM */
- TESTINST3("smulbb r0, r1, r2", 0x00030000, 0x00040000, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x00030001, 0x00040002, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x00038001, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x00037fff, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smulbb r0, r1, r2", 0x0003ffff, 0x0004ffff, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0);
-TESTINST3("smulbb r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0);
- /* SMULtt rD, rN, rM */
- TESTINST3("smultt r0, r1, r2", 0x00000003, 0x00000004, r0, r1, r2, 0);
- TESTINST3("smultt r0, r1, r2", 0x00010003, 0x00020004, r0, r1, r2, 0);
- TESTINST3("smultt r0, r1, r2", 0x80010003, 0x7fff0004, r0, r1, r2, 0);
- TESTINST3("smultt r0, r1, r2", 0x7fff0003, 0x7fff0004, r0, r1, r2, 0);
- TESTINST3("smultt r0, r1, r2", 0xffff0003, 0xffff0004, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0);
-TESTINST3("smultt r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0);
- /* SMULtb rD, rN, rM */
- TESTINST3("smultb r0, r1, r2", 0x00000003, 0x00040000, r0, r1, r2, 0);
- TESTINST3("smultb r0, r1, r2", 0x00010003, 0x00040002, r0, r1, r2, 0);
- TESTINST3("smultb r0, r1, r2", 0x80010003, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smultb r0, r1, r2", 0x7fff0003, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smultb r0, r1, r2", 0xffff0003, 0x0004ffff, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0);
-TESTINST3("smultb r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0);
- /* SMULbt rD, rN, rM */
- TESTINST3("smulbt r0, r1, r2", 0x00030000, 0x00000004, r0, r1, r2, 0);
- TESTINST3("smulbt r0, r1, r2", 0x00030001, 0x00020004, r0, r1, r2, 0);
- TESTINST3("smulbt r0, r1, r2", 0x00038001, 0x7fff0004, r0, r1, r2, 0);
- TESTINST3("smulbt r0, r1, r2", 0x00037fff, 0x7fff0004, r0, r1, r2, 0);
- TESTINST3("smulbt r0, r1, r2", 0x0003ffff, 0xffff0004, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0);
-TESTINST3("smulbt r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0);
-
- printf("-------------- SMULW{B,T} --------------\n");
- /* SMULWB rD, rN, rM : Rn x Rm[31..16] */
- TESTINST3("smulwb r0, r1, r2", 0x00000003, 0x00020004, r0, r1, r2, 0);
- TESTINST3("smulwb r0, r1, r2", 0x00010003, 0x47ff0004, r0, r1, r2, 0);
- TESTINST3("smulwb r0, r1, r2", 0x80010003, 0x7fff0004, r0, r1, r2, 0);
- TESTINST3("smulwb r0, r1, r2", 0x7fff0003, 0x7fff0004, r0, r1, r2, 0);
- TESTINST3("smulwb r0, r1, r2", 0xffff0003, 0xffff0004, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0);
-TESTINST3("smulwb r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0);
- /* SMULWT rD, rN, rM - Rn x Rm[15.. 0] */
- TESTINST3("smulwt r0, r1, r2", 0x00000003, 0x00040000, r0, r1, r2, 0);
- TESTINST3("smulwt r0, r1, r2", 0x00010003, 0x00040002, r0, r1, r2, 0);
- TESTINST3("smulwt r0, r1, r2", 0x80010003, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smulwt r0, r1, r2", 0x7fff0003, 0x00047fff, r0, r1, r2, 0);
- TESTINST3("smulwt r0, r1, r2", 0xffff0003, 0x0004ffff, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x2575feb2, 0xd2c4287c, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xfb412431, 0x4b90362d, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x004dfbe5, 0xe87927cc, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xf6a3fa3c, 0x083b3571, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xbf17fb9a, 0xb9743941, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x2c0bd024, 0xbce5f924, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x3e976e2e, 0xcc3c201c, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xb4bfb365, 0x1ebaf88e, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x288593c0, 0x722d5e20, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x4d7ff5b4, 0xa1d6f791, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x4557be13, 0x7b11bee7, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xadcf5772, 0xa5631488, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x989a7235, 0xb10bcc65, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x4d6f393a, 0x73f39fca, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x24a3291e, 0x5648e540, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xdd91eebf, 0xc54f79e6, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xf7ce2ec6, 0x5fc92974, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xbc1083e8, 0x7e08184e, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xa617cc31, 0x71c8315f, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xdfe1e8f0, 0x9493110e, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x6ef49020, 0xba8a7e0d, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x3dc4e36b, 0x21568e39, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x52db4a9d, 0x55fcc8cf, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x3564c76c, 0x14434a2a, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x27836b0c, 0x3c855ca8, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x62ff7c30, 0x30ece28e, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x40955fdf, 0x057b562c, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x3b34c270, 0x27e1475b, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x7fdcda96, 0xd05893a7, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xb6ab141d, 0x2dc43624, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x403d53cb, 0x5328d58c, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x21ef1aef, 0x87488a4a, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x31458a23, 0xbb246228, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x848af791, 0x339d8d88, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xda3bacdc, 0x70974249, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x649d5cbd, 0x8a8d4e7d, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xc0c8c881, 0xeb1b4335, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x7dd81a20, 0x0cd6b508, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x6892886c, 0x6731e282, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x112dcffc, 0xb6edf28f, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xabfabbe6, 0x4b4ec9ca, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xe52aabf8, 0xc1037fa4, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xf2f4df1f, 0xcb4ab48f, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x435f909a, 0xaf8f7e18, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x2106ba5f, 0x87df4510, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x246a6376, 0xabf4e8e1, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x1046a1a3, 0xf4c0eeac, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0x638ca515, 0x006a54f2, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xf63e7a9d, 0x79f74493, r0, r1, r2, 0);
-TESTINST3("smulwt r0, r1, r2", 0xbd6845cd, 0x9c09e313, r0, r1, r2, 0);
-
- printf("------------ PKHBT / PKHTB ------------\n");
- /* PKHBT */
- TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhbt r0, r1, r2, lsl #22", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhbt r0, r1, r2, lsl #31", 0x11223344, 0x55667788, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0x50c28082, 0xc1553709, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0x17962e8f, 0x69ec0212, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0xc57243b7, 0x03fa9bb5, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0x7eb226ac, 0xf52e9fbf, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0xbce0f026, 0x7fcbe5a9, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0xa5757252, 0x2dd01366, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0xf4a477c1, 0x5e4b1cbf, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0x76723a21, 0x464a21cc, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0x74d01105, 0xe8108f1b, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2", 0xc1273e2c, 0xcd90d604, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #8", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #12", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #24", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #31", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #8", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #12", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #24", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #31", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #8", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #12", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #24", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #31", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #0", 0xd5dc5407, 0xf87b961e, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #1", 0xd65db979, 0xc61b323b, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #2", 0xa3268abe, 0xed2cbf78, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #3", 0xbf73f0a5, 0x2fb714c9, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x281703ed, 0x925ef472, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #8", 0xeaa652c7, 0x137741f4, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #12", 0x71fbde8b, 0xdba5bd25, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x884c0ad8, 0xc00b821a, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #24", 0xe1bb8606, 0x58293969, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #31", 0xa3cfd624, 0x6077fb1f, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #0", 0x40b094e2, 0x17913309, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #1", 0x5388b5cd, 0x86582032, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #2", 0x5de41558, 0xccfa1c7e, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #3", 0x23ba1b46, 0x4437983c, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #4", 0x48d06549, 0xa9085781, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #8", 0xc6b4ac58, 0xb2aead21, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #12", 0xc2bdf597, 0xdde1e6a4, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #16", 0x852e3a72, 0x157b0dea, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #24", 0xe7aa57b4, 0x1584bd74, r0,r1,r2, 0);
-TESTINST3("pkhbt r0, r1, r2, lsl #31", 0xd4b64d54, 0xc53aaba9, r0,r1,r2, 0);
- /* PKHTB */
- TESTINST3("pkhtb r0, r1, r2, asr #0", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhtb r0, r1, r2, asr #1", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhtb r0, r1, r2, asr #2", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhtb r0, r1, r2, asr #3", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhtb r0, r1, r2, asr #4", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhtb r0, r1, r2, asr #16", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhtb r0, r1, r2, asr #22", 0x11223344, 0x55667788, r0,r1,r2, 0);
- TESTINST3("pkhtb r0, r1, r2, asr #31", 0x11223344, 0x55667788, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0x50c28082, 0xc1553709, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0x17962e8f, 0x69ec0212, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0xc57243b7, 0x03fa9bb5, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0x7eb226ac, 0xf52e9fbf, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0xbce0f026, 0x7fcbe5a9, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0xa5757252, 0x2dd01366, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0xf4a477c1, 0x5e4b1cbf, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0x76723a21, 0x464a21cc, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0x74d01105, 0xe8108f1b, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2", 0xc1273e2c, 0xcd90d604, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #0", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #1", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #2", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #3", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #4", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #8", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #12", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #16", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #24", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #31", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #32", 0x5f986e68, 0x35232047, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #0", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #1", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #2", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #3", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #4", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #8", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #12", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #16", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #24", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #31", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #32", 0x36f26261, 0x89d2ef86, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #0", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #1", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #2", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #3", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #4", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #8", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #12", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #16", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #24", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #31", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #32", 0x216158cb, 0x57a50a01, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #0", 0xd5dc5407, 0xf87b961e, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #1", 0xd65db979, 0xc61b323b, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #2", 0xa3268abe, 0xed2cbf78, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #3", 0xbf73f0a5, 0x2fb714c9, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #4", 0x281703ed, 0x925ef472, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #8", 0xeaa652c7, 0x137741f4, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #12", 0x71fbde8b, 0xdba5bd25, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #16", 0x884c0ad8, 0xc00b821a, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #24", 0xe1bb8606, 0x58293969, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #31", 0xa3cfd624, 0x6077fb1f, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #32", 0xa3cfd624, 0x6077fb1f, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #0", 0x40b094e2, 0x17913309, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #1", 0x5388b5cd, 0x86582032, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #2", 0x5de41558, 0xccfa1c7e, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #3", 0x23ba1b46, 0x4437983c, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #4", 0x48d06549, 0xa9085781, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #8", 0xc6b4ac58, 0xb2aead21, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #12", 0xc2bdf597, 0xdde1e6a4, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #16", 0x852e3a72, 0x157b0dea, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #24", 0xe7aa57b4, 0x1584bd74, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #31", 0xd4b64d54, 0xc53aaba9, r0,r1,r2, 0);
-TESTINST3("pkhtb r0, r1, r2, asr #32", 0xd4b64d54, 0xc53aaba9, r0,r1,r2, 0);
-
- printf("----------------- USAT ----------------- \n");
- TESTINST2("usat r0, #0, r1", 0x0123abcd, r0, r1, 0);
- TESTINST2("usat r0, #1, r1", 0x0123abcd, r0, r1, 0);
- TESTINST2("usat r0, #5, r1", 0x0123abcd, r0, r1, 0);
- TESTINST2("usat r0, #8, r1", 0x0123abcd, r0, r1, 0);
- TESTINST2("usat r0, #11, r1", 0x11110000, r0, r1, 0);
- TESTINST2("usat r0, #13, r1", 0x11110000, r0, r1, 0);
- TESTINST2("usat r0, #15, r1", 0x11110000, r0, r1, 0);
-TESTINST2("usat r0, #0, r1", 0xebbff82b, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, lsl #0", 0x5f986e68, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, lsl #0", 0xe7aa57b4, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, lsl #0", 0x89d2ef86, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, lsl #8", 0xc53aaba9, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, lsl #8", 0x216158cb, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, lsl #8", 0x3cd6cd94, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, lsl #0", 0xf87b961e, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, lsl #0", 0xc61b323b, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, lsl #0", 0xa3268abe, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, lsl #8", 0xbf73f0a5, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, lsl #8", 0x925ef472, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, lsl #8", 0x137741f4, r0, r1, 0);
-TESTINST2("usat r0, #24, r1, lsl #2", 0x50c28082, r0, r1, 0);
-TESTINST2("usat r0, #16, r1, lsl #3", 0x17962e8f, r0, r1, 0);
-TESTINST2("usat r0, #12, r1, lsl #4", 0xc57243b7, r0, r1, 0);
-TESTINST2("usat r0, #8, r1, lsl #8", 0xf20fb90f, r0, r1, 0);
-TESTINST2("usat r0, #4, r1, lsl #12", 0xbb151055, r0, r1, 0);
-TESTINST2("usat r0, #3, r1, lsl #16", 0x957440d2, r0, r1, 0);
-TESTINST2("usat r0, #2, r1, lsl #24", 0x728b7771, r0, r1, 0);
-TESTINST2("usat r0, #1, r1, lsl #31", 0xf13c20f3, r0, r1, 0);
-TESTINST2("usat r0, #0, r1", 0xebbff82b, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #0", 0x5f986e68, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #0", 0xe7aa57b4, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #0", 0x89d2ef86, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #8", 0xc53aaba9, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #8", 0x216158cb, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #8", 0x3cd6cd94, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #0", 0xf87b961e, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #0", 0xc61b323b, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #0", 0xa3268abe, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #8", 0xbf73f0a5, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #8", 0x925ef472, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #8", 0x137741f4, r0, r1, 0);
-TESTINST2("usat r0, #24, r1, asr #2", 0x50c28082, r0, r1, 0);
-TESTINST2("usat r0, #16, r1, asr #3", 0x17962e8f, r0, r1, 0);
-TESTINST2("usat r0, #12, r1, asr #4", 0xc57243b7, r0, r1, 0);
-TESTINST2("usat r0, #8, r1, asr #8", 0xf20fb90f, r0, r1, 0);
-TESTINST2("usat r0, #4, r1, asr #12", 0xbb151055, r0, r1, 0);
-TESTINST2("usat r0, #3, r1, asr #16", 0x957440d2, r0, r1, 0);
-TESTINST2("usat r0, #2, r1, asr #24", 0x728b7771, r0, r1, 0);
-TESTINST2("usat r0, #1, r1, asr #31", 0xf13c20f3, r0, r1, 0);
-TESTINST2("usat r0, #0, r1", 0xebbff82b, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #0", 0x5f986e68, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #0", 0xe7aa57b4, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #0", 0x89d2ef86, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #8", 0xc53aaba9, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #8", 0x216158cb, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #8", 0x3cd6cd94, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #0", 0xf87b961e, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #0", 0xc61b323b, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #0", 0xa3268abe, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #8", 0xbf73f0a5, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #8", 0x925ef472, r0, r1, 0);
-TESTINST2("usat r0, #0, r1, asr #8", 0x137741f4, r0, r1, 0);
-TESTINST2("usat r0, #24, r1, asr #2", 0x50c28082, r0, r1, 0);
-TESTINST2("usat r0, #16, r1, asr #3", 0x17962e8f, r0, r1, 0);
-TESTINST2("usat r0, #12, r1, asr #4", 0xc57243b7, r0, r1, 0);
-TESTINST2("usat r0, #8, r1, asr #8", 0xf20fb90f, r0, r1, 0);
-TESTINST2("usat r0, #4, r1, asr #12", 0xbb151055, r0, r1, 0);
-TESTINST2("usat r0, #3, r1, asr #16", 0x957440d2, r0, r1, 0);
-TESTINST2("usat r0, #2, r1, asr #24", 0x728b7771, r0, r1, 0);
-TESTINST2("usat r0, #1, r1, asr #31", 0xf13c20f3, r0, r1, 0);
-#ifndef __thumb__
-TESTINST2("usat r0, #0, r1, asr #32", 0xa9085781, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #32", 0x40b094e2, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #32", 0x17913309, r0, r1, 0);
-TESTINST2("usat r0, #31, r1, asr #32", 0x5388b5cd, r0, r1, 0);
-TESTINST2("usat r0, #24, r1, asr #32", 0x86582032, r0, r1, 0);
-TESTINST2("usat r0, #16, r1, asr #32", 0x5de41558, r0, r1, 0);
-TESTINST2("usat r0, #12, r1, asr #32", 0xccfa1c7e, r0, r1, 0);
-TESTINST2("usat r0, #8, r1, asr #32", 0x23ba1b46, r0, r1, 0);
-TESTINST2("usat r0, #4, r1, asr #32", 0x4437983c, r0, r1, 0);
-TESTINST2("usat r0, #3, r1, asr #32", 0x48d06549, r0, r1, 0);
-TESTINST2("usat r0, #2, r1, asr #32", 0xa9085781, r0, r1, 0);
-TESTINST2("usat r0, #1, r1, asr #32", 0xc6b4ac58, r0, r1, 0);
-#endif
-
- printf("------------ USAT16 sat_imm ------------ \n");
- TESTINST2("usat16 r0, #0, r1", 0x0123abcd, r0, r1, 0);
- TESTINST2("usat16 r0, #1, r1", 0xffcdabcd, r0, r1, 0);
- TESTINST2("usat16 r0, #5, r1", 0x0123feff, r0, r1, 0);
- TESTINST2("usat16 r0, #8, r1", 0x0123abcd, r0, r1, 0);
- TESTINST2("usat16 r0, #11, r1", 0x11110000, r0, r1, 0);
- TESTINST2("usat16 r0, #13, r1", 0x1111f111, r0, r1, 0);
- TESTINST2("usat16 r0, #15, r1", 0x00001111, r0, r1, 0);
-TESTINST2("usat16 r0, #0, r1", 0xebbff82b, r0, r1, 0);
-TESTINST2("usat16 r0, #1, r1", 0xebbff82b, r0, r1, 0);
-TESTINST2("usat16 r0, #3, r1", 0x50c28082, r0, r1, 0);
-TESTINST2("usat16 r0, #5, r1", 0x17962e8f, r0, r1, 0);
-TESTINST2("usat16 r0, #8, r1", 0xc57243b7, r0, r1, 0);
-TESTINST2("usat16 r0, #10, r1", 0xf20fb90f, r0, r1, 0);
-TESTINST2("usat16 r0, #11, r1", 0xbb151055, r0, r1, 0);
-TESTINST2("usat16 r0, #13, r1", 0x957440d2, r0, r1, 0);
-TESTINST2("usat16 r0, #14, r1", 0x728b7771, r0, r1, 0);
-TESTINST2("usat16 r0, #15, r1", 0xf13c20f3, r0, r1, 0);
-TESTINST2("usat16 r0, #0, r1", 0x86398371, r0, r1, 0);
-TESTINST2("usat16 r0, #1, r1", 0x03d0fb78, r0, r1, 0);
-TESTINST2("usat16 r0, #3, r1", 0xd0d49b7c, r0, r1, 0);
-TESTINST2("usat16 r0, #5, r1", 0x76354a58, r0, r1, 0);
-TESTINST2("usat16 r0, #8, r1", 0x9fa45fb7, r0, r1, 0);
-TESTINST2("usat16 r0, #10, r1", 0x7572bdec, r0, r1, 0);
-TESTINST2("usat16 r0, #11, r1", 0xfea59eb6, r0, r1, 0);
-TESTINST2("usat16 r0, #13, r1", 0xf2669090, r0, r1, 0);
-TESTINST2("usat16 r0, #14, r1", 0xbc1ff573, r0, r1, 0);
-TESTINST2("usat16 r0, #15, r1", 0x7eb226ac, r0, r1, 0);
-TESTINST2("usat16 r0, #0, r1", 0x22b65db1, r0, r1, 0);
-TESTINST2("usat16 r0, #1, r1", 0x776c41c7, r0, r1, 0);
-TESTINST2("usat16 r0, #3, r1", 0xe50dd77c, r0, r1, 0);
-TESTINST2("usat16 r0, #5, r1", 0xd6f9a698, r0, r1, 0);
-TESTINST2("usat16 r0, #8, r1", 0xeda5110c, r0, r1, 0);
-TESTINST2("usat16 r0, #10, r1", 0x0be36f70, r0, r1, 0);
-TESTINST2("usat16 r0, #11, r1", 0xd759eb72, r0, r1, 0);
-TESTINST2("usat16 r0, #13, r1", 0xd9c4b1f4, r0, r1, 0);
-TESTINST2("usat16 r0, #14, r1", 0xa29eb320, r0, r1, 0);
-TESTINST2("usat16 r0, #15, r1", 0xcf1e4487, r0, r1, 0);
-TESTINST2("usat16 r0, #0, r1", 0x2eb68500, r0, r1, 0);
-TESTINST2("usat16 r0, #1, r1", 0xcdb7ed11, r0, r1, 0);
-TESTINST2("usat16 r0, #3, r1", 0x2eaea305, r0, r1, 0);
-TESTINST2("usat16 r0, #5, r1", 0x6ebd04d9, r0, r1, 0);
-TESTINST2("usat16 r0, #8, r1", 0xa5ec1aa8, r0, r1, 0);
-TESTINST2("usat16 r0, #10, r1", 0x72f33509, r0, r1, 0);
-TESTINST2("usat16 r0, #11, r1", 0xa3e6f759, r0, r1, 0);
-TESTINST2("usat16 r0, #13, r1", 0xfaceab39, r0, r1, 0);
-TESTINST2("usat16 r0, #14, r1", 0x2738f0ff, r0, r1, 0);
-TESTINST2("usat16 r0, #15, r1", 0xe79fd570, r0, r1, 0);
-TESTINST2("usat16 r0, #0, r1", 0x55ea3e4e, r0, r1, 0);
-TESTINST2("usat16 r0, #1, r1", 0x2b62ba5a, r0, r1, 0);
-TESTINST2("usat16 r0, #3, r1", 0x9b41bfb1, r0, r1, 0);
-TESTINST2("usat16 r0, #5, r1", 0x557c7ba2, r0, r1, 0);
-TESTINST2("usat16 r0, #8, r1", 0x2973c051, r0, r1, 0);
-TESTINST2("usat16 r0, #10, r1", 0x6a228b19, r0, r1, 0);
-TESTINST2("usat16 r0, #11, r1", 0x0cdafabe, r0, r1, 0);
-TESTINST2("usat16 r0, #13, r1", 0x50865114, r0, r1, 0);
-TESTINST2("usat16 r0, #14, r1", 0xd83b849b, r0, r1, 0);
-TESTINST2("usat16 r0, #15, r1", 0xca5e5605, r0, r1, 0);
-
- printf("---------------- UADD16 ---------------- \n");
- TESTINST3("uadd16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("uadd16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("uadd16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("uadd16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("uadd16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
- printf("---------------- USUB16 ---------------- \n");
- TESTINST3("usub16 r0, r1, r2", 0x04000022, 0x03000011, r0, r1, r2, 0);
- TESTINST3("usub16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("usub16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("usub16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("usub16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("usub16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
- printf("---------------- UADD8 ----------------- \n");
- TESTINST3("uadd8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("uadd8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("uadd8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("uadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("uadd8 r0, r1, r2", 0x00000318, 0xff00ff09, r0, r1, r2, 0);
- TESTINST3("uadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("uadd8 r0, r1, r2", 0x00020318, 0xff07ff09, r0, r1, r2, 0);
- TESTINST3("uadd8 r0, r1, r2", 0xff07ff09, 0x00020318, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("uadd8 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
- printf("---------------- USUB8 ----------------- \n");
- TESTINST3("usub8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("usub8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("usub8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("usub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("usub8 r0, r1, r2", 0x00000318, 0xff00ff09, r0, r1, r2, 0);
- TESTINST3("usub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("usub8 r0, r1, r2", 0x00020318, 0xff07ff09, r0, r1, r2, 0);
- TESTINST3("usub8 r0, r1, r2", 0xff07ff09, 0x00020318, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("usub8 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
- printf("---------------- QADD16 ---------------- \n");
- TESTINST3("qadd16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("qadd16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("qadd16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("qadd16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("qadd16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
- printf("---------------- QSUB16 ---------------- \n");
- TESTINST3("qsub16 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("qsub16 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("qsub16 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("qsub16 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("qsub16 r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
- printf("----------------- QSAX ----------------- \n");
- TESTINST3("qsax r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
- TESTINST3("qsax r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0);
- TESTINST3("qsax r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0);
- TESTINST3("qsax r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("qsax r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0);
- TESTINST3("qsax r0, r1, r2", 0x00030003, 0x00640064, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("qsax r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
- printf("----------------- QASX ----------------- \n");
- TESTINST3("qasx r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
- TESTINST3("qasx r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0);
- TESTINST3("qasx r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0);
- TESTINST3("qasx r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("qasx r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0);
- TESTINST3("qasx r0, r1, r2", 0x00030003, 0x00640064, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("qasx r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
- printf("----------------- SMUAD ----------------- \n");
- TESTINST3("smuad r0, r1, r2", 0x80008000, 0x80008000, r0, r1, r2, 0);
- TESTINST3("smuad r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
- TESTINST3("smuad r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0);
- TESTINST3("smuad r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("smuad r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0);
- TESTINST3("smuad r0, r1, r2", 0xffffffff, 0xfffc0001, r0, r1, r2, 0);
- TESTINST3("smuad r0, r1, r2", 0xfff70fff, 0x00030003, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("smuad r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
- printf("----------------- SMUADX ---------------- \n");
- TESTINST3("smuadx r0, r1, r2", 0x80008000, 0x80008000, r0, r1, r2, 0);
- TESTINST3("smuadx r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
- TESTINST3("smuadx r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0);
- TESTINST3("smuadx r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("smuadx r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0);
- TESTINST3("smuadx r0, r1, r2", 0xffffffff, 0xfffc0001, r0, r1, r2, 0);
- TESTINST3("smuadx r0, r1, r2", 0xfff70fff, 0x00030003, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
-TESTINST3("smuadx r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
-
- printf("----------------- SMLAD ----------------- \n");
- TESTINST4("smlad r0, r1, r2, r3",
- 0x7fff7fff, 0x00000000, 0x00000000, r0, r1, r2, r3, 0);
- TESTINST4("smlad r0, r1, r2, r3",
- 0x7fff7fff, 0x00010001, 0x00000001, r0, r1, r2, r3, 0);
- TESTINST4("smlad r0, r1, r2, r3",
- 0x80008000, 0xffffffff, 0x0000001f, r0, r1, r2, r3, 0);
- TESTINST4("smlad r0, r1, r2, r3",
- 0x00640064, 0x00030003, 0x00000020, r0, r1, r2, r3, 0);
- TESTINST4("smlad r0, r1, r2, r3",
- 0xffffffff, 0xfffc0001, 0x000000ff, r0, r1, r2, r3, 0);
- TESTINST4("smlad r0, r1, r2, r3",
- 0xfff70fff, 0x00030003, 0x00000100, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0);
-TESTINST4("smlad r0, r1, r2, r3",
- 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0);
-
- printf("------------ SMLABB, SMLATT, SMLATB, SMLABT ------------\n");
- /* smlabb rD, rN, rM, rA */
- TESTINST4("smlabb r0, r1, r2, r3",
- 0x00030000, 0x00040000, 0x00000000, r0,r1,r2,r3, 0);
- TESTINST4("smlabb r0, r1, r2, r3",
- 0x00030001, 0x00040002, 0x00007fff, r0,r1,r2,r3, 0);
- TESTINST4("smlabb r0, r1, r2, r3",
- 0x00038001, 0x00047fff, 0x00005fff, r0,r1,r2,r3, 0);
- TESTINST4("smlabb r0, r1, r2, r3",
- 0x00037fff, 0x00047fff, 0x00007fff, r0,r1,r2,r3, 0);
- TESTINST4("smlabb r0, r1, r2, r3",
- 0x0003ffff, 0x0004ffff, 0x7fff7fff, r0,r1,r2,r3, 0);
- TESTINST4("smlabb r0, r1, r2, r3",
- 0x0003fffc, 0x0004ffff, 0xffffffff, r0,r1,r2,r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0);
-TESTINST4("smlabb r0, r1, r2, r3",
- 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0);
- /* smlatt rD, rN, rM, rA */
- TESTINST4("smlatt r0, r1, r2, r3",
- 0x00000003, 0x00000004, 0x00000000, r0,r1,r2,r3, 0);
- TESTINST4("smlatt r0, r1, r2, r3",
- 0x00010003, 0x00020004, 0x00007fff, r0,r1,r2,r3, 0);
- TESTINST4("smlatt r0, r1, r2, r3",
- 0x80010003, 0x7fff0004, 0x00005fff, r0,r1,r2,r3, 0);
- TESTINST4("smlatt r0, r1, r2, r3",
- 0x7fff0003, 0x7fff0004, 0x00007fff, r0,r1,r2,r3, 0);
- TESTINST4("smlatt r0, r1, r2, r3",
- 0xffff0003, 0xffff0004, 0x7fff7fff, r0,r1,r2,r3, 0);
- TESTINST4("smlatt r0, r1, r2, r3",
- 0xfffc0003, 0xffff0004, 0xffffffff, r0,r1,r2,r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0);
-TESTINST4("smlatt r0, r1, r2, r3",
- 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0);
- /* smlatb rD, rN, rM, rA */
- TESTINST4("smlatb r0, r1, r2, r3",
- 0x00000003, 0x00040000, 0x00000000, r0,r1,r2,r3, 0);
- TESTINST4("smlatb r0, r1, r2, r3",
- 0x00010003, 0x00040002, 0x00007fff, r0,r1,r2,r3, 0);
- TESTINST4("smlatb r0, r1, r2, r3",
- 0x80010003, 0x00047fff, 0x00005fff, r0,r1,r2,r3, 0);
- TESTINST4("smlatb r0, r1, r2, r3",
- 0x7fff0003, 0x00047fff, 0x00007fff, r0,r1,r2,r3, 0);
- TESTINST4("smlatb r0, r1, r2, r3",
- 0xffff0003, 0x0004ffff, 0x7fff7fff, r0,r1,r2,r3, 0);
- TESTINST4("smlatb r0, r1, r2, r3",
- 0xfffc0003, 0x0004ffff, 0xffffffff, r0,r1,r2,r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0);
-TESTINST4("smlatb r0, r1, r2, r3",
- 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0);
- /* smlabt rD, rN, rM, rA */
- TESTINST4("smlabt r0, r1, r2, r3",
- 0x00030000, 0x00000004, 0x00000000, r0,r1,r2,r3, 0);
- TESTINST4("smlabt r0, r1, r2, r3",
- 0x00030001, 0x00020004, 0x00007fff, r0,r1,r2,r3, 0);
- TESTINST4("smlabt r0, r1, r2, r3",
- 0x00038001, 0x7fff0004, 0x00005fff, r0,r1,r2,r3, 0);
- TESTINST4("smlabt r0, r1, r2, r3",
- 0x00037fff, 0x7fff0004, 0x00007fff, r0,r1,r2,r3, 0);
- TESTINST4("smlabt r0, r1, r2, r3",
- 0x0003ffff, 0xffff0004, 0x7fff7fff, r0,r1,r2,r3, 0);
- TESTINST4("smlabt r0, r1, r2, r3",
- 0x0003fffc, 0xffff0004, 0xffffffff, r0,r1,r2,r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xb8035b5b, 0xce0ce1ed, 0x5f986e68, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x35232047, 0x146275d8, 0xaae3433f, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xe7aa57b4, 0x1584bd74, 0x2c07a5b4, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x32fa0095, 0x36f26261, 0x89d2ef86, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x8ed8287c, 0x02c90120, 0xd4b64d54, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xc53aaba9, 0x29300837, 0x0b02c58a, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x216158cb, 0x57a50a01, 0xb0d20777, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x3e2e1bd7, 0x3cd6cd94, 0x7e376198, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xd5fe2dc4, 0xdd914bf7, 0xd5dc5407, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xf87b961e, 0x1d66879f, 0xf2b64835, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xd65db979, 0xc61b323b, 0xae930a1a, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x5ef1f1a8, 0xbf73f0a5, 0x2fb714c9, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x1ffe53d9, 0x815bb75b, 0xa3268abe, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xed2cbf78, 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xeaa652c7, 0x137741f4, 0x3dba1164, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x3ada0280, 0x71fbde8b, 0xdba5bd25, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xda4ba05b, 0x90f9833d, 0x884c0ad8, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xc00b821a, 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xe1bb8606, 0x58293969, 0x81616d13, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x51f31d95, 0xa3cfd624, 0x6077fb1f, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x0849a0c2, 0x0872f25a, 0x40b094e2, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x17913309, 0xf1e03d7e, 0x91edc21d, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x5388b5cd, 0x86582032, 0x6034078d, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x181c436b, 0x5de41558, 0xccfa1c7e, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x23ba1b46, 0x4437983c, 0x48d06549, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xa9085781, 0xc6b4ac58, 0xb2aead21, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xc2bdf597, 0xdde1e6a4, 0x852e3a72, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x157b0dea, 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x3edad6b6, 0x82aceb7a, 0x0557c6fc, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x6cc9bfa8, 0x7f808c15, 0x81874a02, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x6b1422c7, 0x33921b00, 0x3ccad3f7, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xd7ce1909, 0x3e435701, 0x85fbf196, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xb4e16b6e, 0x6e13680a, 0x89436f88, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x44858efc, 0x9002bc30, 0x390d2c2f, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xbea121ab, 0x953ff6ec, 0x80657c40, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x6ffed89f, 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x7795635d, 0x5e6e32dd, 0xe4999bf2, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xec0c2f30, 0x5736ed46, 0x231348c0, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x4f9ddd1b, 0x95bca5d8, 0x5765b203, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xc1553709, 0x0112b30a, 0x69ec0212, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x74bd0223, 0x03fa9bb5, 0x899d9192, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xf52e9fbf, 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x64a365ef, 0x2dd01366, 0xf7b0b13e, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x5e4b1cbf, 0x44de5ca9, 0x464a21cc, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x299da970, 0xe8108f1b, 0xf5818cfb, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xcd90d604, 0xaa5e9444, 0x8217b7df, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xe60743c3, 0x7acb4de3, 0x73c29060, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x868e7c7d, 0x5f77532e, 0x1d133d3d, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0x4e5e0760, 0x8f6d3264, 0x21ba2fb3, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xde99ac2f, 0x0be36f70, 0xeda5110c, r0, r1, r2, r3, 0);
-TESTINST4("smlabt r0, r1, r2, r3",
- 0xc57243b7, 0xcf1e4487, 0xf20fb90f, r0, r1, r2, r3, 0);
-
- printf("------------ UQSUB8 -----------------------------------\n");
- TESTINST3("uqsub8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("uqsub8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("uqsub8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("uqsub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("uqsub8 r0, r1, r2", 0x00000318, 0xff00ff09, r0, r1, r2, 0);
- TESTINST3("uqsub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("uqsub8 r0, r1, r2", 0x00020318, 0xff07ff09, r0, r1, r2, 0);
- TESTINST3("uqsub8 r0, r1, r2", 0xff07ff09, 0x00020318, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uqsub8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("------------ UQADD8 -----------------------------------\n");
- TESTINST3("uqadd8 r0, r1, r2", 0x0009ffff, 0x001800aa, r0, r1, r2, 0);
- TESTINST3("uqadd8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("uqadd8 r0, r1, r2", 0x00aa0018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("uqadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("uqadd8 r0, r1, r2", 0x0000aa18, 0xff00ff09, r0, r1, r2, 0);
- TESTINST3("uqadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("uqadd8 r0, r1, r2", 0xff9fefcc, 0xff9ffedd, r0, r1, r2, 0);
- TESTINST3("uqadd8 r0, r1, r2", 0xff07ff09, 0xaa020318, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uqadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("------------ SEL --------------------------------------\n");
- TESTINST3("sel r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
- TESTINST3("sel r0, r1, r2", 0x7fff7fff, 0x00010001, r0, r1, r2, 0);
- TESTINST3("sel r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
- TESTINST3("sel r0, r1, r2", 0x00640064, 0x00030003, r0, r1, r2, 0);
- TESTINST3("sel r0, r1, r2", 0xfffcffff, 0xffff0001, r0, r1, r2, 0);
- TESTINST3("sel r0, r1, r2", 0xfff70fff, 0x00030003, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sel r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("------------ QSUB8-------------------------------------\n");
- TESTINST3("qsub8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("qsub8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("qsub8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("qsub8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("qsub8 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
- TESTINST3("qsub8 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0);
- TESTINST3("qsub8 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0);
- TESTINST3("qsub8 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("qsub8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("------------ QADD8-------------------------------------\n");
- TESTINST3("qadd8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("qadd8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("qadd8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("qadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("qadd8 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
- TESTINST3("qadd8 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0);
- TESTINST3("qadd8 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0);
- TESTINST3("qadd8 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("qadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("------------ SHADD8 -----------------------------------\n");
- TESTINST3("shadd8 r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
- TESTINST3("shadd8 r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
- TESTINST3("shadd8 r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
- TESTINST3("shadd8 r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
- TESTINST3("shadd8 r0, r1, r2", 0x7fff7fff, 0x00000000, r0, r1, r2, 0);
- TESTINST3("shadd8 r0, r1, r2", 0x7fff00ff, 0x80017f01, r0, r1, r2, 0);
- TESTINST3("shadd8 r0, r1, r2", 0x80008000, 0x00000000, r0, r1, r2, 0);
- TESTINST3("shadd8 r0, r1, r2", 0x80008000, 0xffffffff, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("shadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("----------------- SSAT ----------------- \n");
- TESTINST2("ssat r0, #1, r1, LSL #31", 0x80008000, r0, r1, 0);
- TESTINST2("ssat r0, #6, r1, LSL #24", 0x80008000, r0, r1, 0);
- TESTINST2("ssat r0, #8, r1, ASR #18", 0x80008000, r0, r1, 0);
- TESTINST2("ssat r0, #12, r1, ASR #16", 0x80008000, r0, r1, 0);
- TESTINST2("ssat r0, #16, r1, LSL #12", 0xffff0009, r0, r1, 0);
- TESTINST2("ssat r0, #18, r1, LSL #8", 0xffff0009, r0, r1, 0);
- TESTINST2("ssat r0, #24, r1, ASR #6", 0xffff0009, r0, r1, 0);
- TESTINST2("ssat r0, #31, r1, ASR #1", 0xffff0009, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, LSL #31", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #3, r1, LSL #28", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #6, r1, LSL #24", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #8, r1, ASR #18", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #12, r1, ASR #16", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #16, r1, LSL #12", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #18, r1, LSL #8", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #24, r1, ASR #6", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #28, r1, ASR #3", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #31, r1, ASR #1", 0xffc134df, r0, r1, 0);
-#ifndef __thumb__
-TESTINST2("ssat r0, #1, r1, ASR #32", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, ASR #32", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, ASR #32", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, ASR #32", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, ASR #32", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, ASR #32", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, ASR #32", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, ASR #32", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, ASR #32", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #1, r1, ASR #32", 0xffc134df, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0x256bfdd6, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0xc02a0c05, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0xee2fa46e, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0x97a7da20, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0xa231d5e6, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0x10e1968a, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0x0e089270, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0x9e8e0185, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0x3096f12e, r0, r1, 0);
-TESTINST2("ssat r0, #32, r1, ASR #32", 0xffc134df, r0, r1, 0);
-#endif
-
- printf("---------------- SADD8 ----------------- \n");
- TESTINST3("sadd8 r0, r1, r2", 0x00f7ffff, 0x00e800fd, r0, r1, r2, 0);
- TESTINST3("sadd8 r0, r1, r2", 0x00e800fd, 0x00f7ffff, r0, r1, r2, 0);
- TESTINST3("sadd8 r0, r1, r2", 0x00fd00e8, 0xffff00f7, r0, r1, r2, 0);
- TESTINST3("sadd8 r0, r1, r2", 0xffff00f7, 0x00fd0018, r0, r1, r2, 0);
- TESTINST3("sadd8 r0, r1, r2", 0x0000fd18, 0xff00fff7, r0, r1, r2, 0);
- TESTINST3("sadd8 r0, r1, r2", 0xffff00f7, 0x00fd00e8, r0, r1, r2, 0);
- TESTINST3("sadd8 r0, r1, r2", 0x00fefd18, 0xff07fff7, r0, r1, r2, 0);
- TESTINST3("sadd8 r0, r1, r2", 0xff07fff7, 0x00fefde8, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xb8035b5b, 0xce0ce1ed, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x146275d8, 0xaae3433f, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x2c07a5b4, 0x32fa0095, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x8ed8287c, 0x02c90120, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x29300837, 0x0b02c58a, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xb0d20777, 0x3e2e1bd7, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xd5fe2dc4, 0xdd914bf7, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x1d66879f, 0xf2b64835, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xae930a1a, 0x5ef1f1a8, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x1ffe53d9, 0x815bb75b, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xc6ffabb6, 0xef9e9fd9, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x3dba1164, 0x3ada0280, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xda4ba05b, 0x90f9833d, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x7fa1d5a6, 0x9a4ff1b8, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x81616d13, 0x51f31d95, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x0849a0c2, 0x0872f25a, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xf1e03d7e, 0x91edc21d, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x6034078d, 0x181c436b, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xf0d5ff94, 0xe7b87e39, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x3edad6b6, 0x82aceb7a, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x0557c6fc, 0x6cc9bfa8, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x7f808c15, 0x81874a02, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x6b1422c7, 0x33921b00, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x3ccad3f7, 0xd7ce1909, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x3e435701, 0x85fbf196, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xb4e16b6e, 0x6e13680a, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x89436f88, 0x44858efc, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x9002bc30, 0x390d2c2f, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xbea121ab, 0x953ff6ec, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x80657c40, 0x6ffed89f, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x3e8c49b7, 0x11bd07d1, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x7795635d, 0x5e6e32dd, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xe4999bf2, 0xec0c2f30, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x5736ed46, 0x231348c0, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x4f9ddd1b, 0x95bca5d8, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x5765b203, 0xc1553709, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x0112b30a, 0x69ec0212, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x74bd0223, 0x03fa9bb5, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x899d9192, 0xf52e9fbf, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xb4c510a7, 0x7fcbe5a9, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x64a365ef, 0x2dd01366, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sadd8 r0, r1, r2", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("------------ SXTAB ------------\n");
- TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, r0, r1, r2, 0);
-
- TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, r0, r1, r2, 0);
-
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sxtab r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("------------ UXTAB ------------\n");
- TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, r0, r1, r2, 0);
-
- TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, r0, r1, r2, 0);
-
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtab r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("----------- UXTAB16 -----------\n");
- TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182819, r0, r1, r2, 0);
-
- TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182899, r0, r1, r2, 0);
- TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x3141FFFF, 0x27182899, r0, r1, r2, 0);
-
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("------------ SXTAH ------------\n");
- TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, r0, r1, r2, 0);
-
- TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, r0, r1, r2, 0);
- TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, r0, r1, r2, 0);
-
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("sxtah r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
- printf("------------ UXTAH ------------\n");
- TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, r0, r1, r2, 0);
-
- TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, r0, r1, r2, 0);
- TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, r0, r1, r2, 0);
-
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #24", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #16", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #8", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
-
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0x44de5ca9, 0x464a21cc, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0x299da970, 0xe8108f1b, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0xf5818cfb, 0xcd90d604, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0xaa5e9444, 0x8217b7df, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0xe60743c3, 0x7acb4de3, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0x73c29060, 0x868e7c7d, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0x5f77532e, 0x1d133d3d, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0x4e5e0760, 0x8f6d3264, r0, r1, r2, 0);
-TESTINST3("uxtah r0, r1, r2, ROR #0", 0x21ba2fb3, 0xde99ac2f, r0, r1, r2, 0);
+ printf("---------------- QSUB ---------------- \n");
+ TESTINST3("qsub r0, r1, r2", 0x00000000, 0x7fffffff, r0, r1, r2, 0);
+ TESTINST3("qsub r0, r1, r2", 0x00000001, 0x7fffffff, r0, r1, r2, 0);
+ TESTINST3("qsub r0, r1, r2", 0x00000000, 0x00000000, r0, r1, r2, 0);
+ TESTINST3("qsub r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+ TESTINST3("qsub r0, r1, r2", 0x0009ffff, 0x00180003, r0, r1, r2, 0);
+ TESTINST3("qsub r0, r1, r2", 0x00180003, 0x0009ffff, r0, r1, r2, 0);
+ TESTINST3("qsub r0, r1, r2", 0x00030018, 0xffff0009, r0, r1, r2, 0);
+ TESTINST3("qsub r0, r1, r2", 0xffff0009, 0x00030018, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xd83b849b, 0xca5e5605, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x0cdafabe, 0x50865114, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x2738f0ff, 0x6a228b19, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xfaceab39, 0x2973c051, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xa3e6f759, 0x557c7ba2, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x72f33509, 0x9b41bfb1, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xa5ec1aa8, 0x2b62ba5a, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x6ebd04d9, 0x55ea3e4e, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x2eaea305, 0xe79fd570, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x22b65db1, 0xcdb7ed11, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x776c41c7, 0x2eb68500, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xe50dd77c, 0xd6f9a698, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x0be36f70, 0xeda5110c, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xebbff82b, 0xd759eb72, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x50c28082, 0xd9c4b1f4, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x17962e8f, 0xa29eb320, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xc57243b7, 0xcf1e4487, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x7eb226ac, 0xf20fb90f, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xbce0f026, 0xbb151055, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xa5757252, 0x957440d2, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xf4a477c1, 0x728b7771, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x76723a21, 0xf13c20f3, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x74d01105, 0x86398371, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xc1273e2c, 0x03d0fb78, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xdd9b7653, 0xd0d49b7c, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xdde62fd1, 0x76354a58, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xc3fb4a96, 0x9fa45fb7, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xa1a10f56, 0x7572bdec, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x4b7d4fd9, 0xfea59eb6, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x9d0ddffc, 0xf2669090, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x4f82d17c, 0xbc1ff573, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x08215ca2, 0x345f67e6, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xf23595d0, 0x3f39d77e, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xf244c158, 0xfb2db55b, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x256bfdd6, 0x13aebedf, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xc02a0c05, 0x5b013000, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xee2fa46e, 0xed95b542, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x97a7da20, 0x60bb5ee8, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xa231d5e6, 0xd9000a64, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x10e1968a, 0x624f9467, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x0e089270, 0xa8c64d94, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x9e8e0185, 0x6b4f637a, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x3096f12e, 0x11f5f4b9, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xffc134df, 0x0b02eb0c, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xe444dc25, 0xd5eef620, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x06ea9b2a, 0xa2108661, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x448f3a5f, 0x17aecf57, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0x4b0c2337, 0xffa63d6c, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xf91d5f56, 0x088bc0f9, r0, r1, r2, 0);
+TESTINST3("qsub r0, r1, r2", 0xf808434e, 0xefeab836, r0, r1, r2, 0);
/*
TESTINST3("theinsn", 0xf7b0b13e, 0x5e4b1cbf, r0, r1, r2, 0);
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/arm/v6media.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/arm/v6media.stderr.exp
diff --git a/main/none/tests/arm/v6media.stdout.exp b/main/none/tests/arm/v6media.stdout.exp
index 1eaf9e1..543a3d0 100644
--- a/main/none/tests/arm/v6media.stdout.exp
+++ b/main/none/tests/arm/v6media.stdout.exp
@@ -2267,6 +2267,66 @@
uhadd8 r0, r1, r2 :: rd 0x3e454835 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
uhadd8 r0, r1, r2 :: rd 0x6e651c62 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
uhadd8 r0, r1, r2 :: rd 0x7fa96d71 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+------------ UHADD16 -----------------------------------
+uhadd16 r0, r1, r2 :: rd 0x00108001 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x00108001 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x80010010 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x80010010 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x3fff3fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x80004000 rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x40004000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xbfffbfff rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xc3079ea4 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x5fa25c8b rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x2f805324 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x48d014ce rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x1a1966e0 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x778011a7 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xd9c73cdd rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x880e67ea rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x86c27de1 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x50ac859a rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xdb4ea5c7 rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x3c4a09f2 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xb5a291cc rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x8cf8e3af rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x69aa4554 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x085dc98e rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xc1e67fcd rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x3c28257c rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xec46bee6 rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x60c3e118 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x3910c352 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x80836b0b rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x4f531ee3 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x8a4c7680 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x621fa44b rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x917a69bc rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x66e47f42 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x6487742f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xa9f08c4b rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x7831aa6f rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x282428c4 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x6b014b1d rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xe8526591 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x3d249b03 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x72acc179 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x8c5d7486 rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x357f5a8e rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x3c5b4eec rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xbf6598a8 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x9a487b28 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x49393caa rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xaafd66fe rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x45943f3a rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x88d69c45 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xe188b17f rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x963aa611 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0xb06948d3 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x7d28866e rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x3e454835 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x6ee51ce2 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+uhadd16 r0, r1, r2 :: rd 0x80296df1 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
----------------- SSAT -----------------
ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x80008000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
ssat r0, #6, r1, LSL #24 :: rd 0x00000000 rm 0x80008000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
@@ -2752,2404 +2812,6 @@
uxtah r0, r1, r2, ROR #0 :: rd 0x5f77906b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
uxtah r0, r1, r2, ROR #0 :: rd 0x4e5e39c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
uxtah r0, r1, r2, ROR #0 :: rd 0x21badbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-MUL
-mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-MLA
-mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mla r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mla r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-MLS
-mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mls r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mls r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mls r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mls r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-mls r0, r1, r2, r3 :: rd 0x00020000 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-UMULL
-umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umull r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-SMULL
-smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smull r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smull r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smull r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-UMLAL
-umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umlal r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-umlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-SMLAL
-smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlal r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-CLZ
-clz r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-clz r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-clz r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-clz r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-clz r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 1, cpsr 0x20000000 C ge[3:0]=0000
-clz r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 1, cpsr 0x20000000 C ge[3:0]=0000
-clz r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 1, cpsr 0x20000000 C ge[3:0]=0000
-clz r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x20000000 C ge[3:0]=0000
-extend instructions
-uxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb r0, r1 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb r0, r1 :: rd 0x000000ff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxth r0, r1 :: rd 0x0000ffff rm 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxth r0, r1 :: rd 0x0000ffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb16 r0, r1 :: rd 0x00ff00ff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtb16 r0, r1, ror #16 :: rd 0x00ff0000 rm 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtb16 r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtb16 r0, r1 :: rd 0xffffffff rm 0x00ff00ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtb16 r0, r1 :: rd 0x007f007f rm 0x007f007f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- BFI ------------
-bfi r0, r1, #0, #11 :: rd 0x555552aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #1, #11 :: rd 0x55555555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #2, #11 :: rd 0x55554aa9 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #19, #11 :: rd 0x7ffd5555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #20, #11 :: rd 0x7ff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #21, #11 :: rd 0xfff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #0, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #29, #3 :: rd 0xf5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #30, #2 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfi r0, r1, #31, #1 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- BFC ------------
-bfc r0, #0, #11 :: rd 0x55555000 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #1, #11 :: rd 0x55555001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #2, #11 :: rd 0x55554001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #19, #11 :: rd 0x40055555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #20, #11 :: rd 0x00055555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #21, #11 :: rd 0x00155555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #0, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #29, #3 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #30, #2 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-bfc r0, #31, #1 :: rd 0x55555555 rm 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- SBFX ------------
-sbfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #0, #1 :: rd 0xffffffff rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000002, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #1, #11 :: rd 0xfffffd55 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #31, #1 :: rd 0xffffffff rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sbfx r0, r1, #30, #2 :: rd 0xfffffffe rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- UBFX ------------
-ubfx r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #0, #1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #1, #11 :: rd 0x00000555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #31, #1 :: rd 0x00000001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ubfx r0, r1, #30, #2 :: rd 0x00000002 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- SMUL{B,T}{B,T} ------------
-smulbb r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00040000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00040002, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0x0004ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xffcb2e38 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x07a8b29d rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xff5c9d7c rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xfecbe07c rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xff042c1a rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x01484910 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x0dd1cd08 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x023a5a06 rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xd832f800 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x0056d6f4 rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x10c39d25 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x07035c90 rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xe8fa4ae9 rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xea7e2dc4 rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xfbb41d80 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf7c8c69a rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x0792e7b8 rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf437f0b0 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf602272f rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xfe76ad20 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xc8ea11a0 rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x0cb3fcd3 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xefe9fcf3 rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xef9befb8 rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x26be8fe0 rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf1b742a0 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x20456454 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xeed72dd0 rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x0fd5b9da rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x0440f214 rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf21aba04 rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf39d9f16 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xd2cefb78 rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x03c56208 rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xea7902bc rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x1c6ede49 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf16e45b5 rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf8597100 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x0dc69ed8 rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x028565c4 rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x0e6bd97c rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xd61a32e0 rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x09b06e51 rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xc9215a70 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xed3740f0 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf7045ab6 rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x06632384 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xe1d4f1da rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0x20d81c27 rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbb r0, r1, r2 :: rd 0xf81cf537 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x00000000 rm 0x00000003, rn 0x00000004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x00000002 rm 0x00010003, rn 0x00020004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xc000ffff rm 0x80010003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x3fff0001 rm 0x7fff0003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x00000001 rm 0xffff0003, rn 0xffff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xf961a794 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xfe995f90 rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xfff8ec65 rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xffb2ef91 rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x11e3356c rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xf47479d7 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xf357ff64 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xf6f7b4c6 rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x12125961 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xe37ea72a rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x215567c7 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x1d17a20d rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x1fe4089e rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x23125d5d rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x0c590fd8 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x07e4f4bf rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xfcef02be rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xde8dc080 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xd809e8f8 rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x0d7aa233 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xe1e51788 rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x080b03d8 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x1bd44694 rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x0439c92c rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x09573b0f rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x12eb1314 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x0161f097 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x0938f4b4 rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xe832b3a0 rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xf2e3e9ec rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x14ddd088 rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xefff9438 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xf2bf54b4 rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xe71bc6a2 rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xef6388cd rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xd1d70c79 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x0528ed18 rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x064f5290 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x2a26c1f2 rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xfb18e4a9 rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xe748a42c rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x069a597e rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x02afb688 rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xead49311 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xf080ee3a rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xf40b8308 rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xff48ec80 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x002937f8 rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0xfb59e3d2 rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultt r0, r1, r2 :: rd 0x1a0108a8 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x00000000 rm 0x00000003, rn 0x00040000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x00000002 rm 0x00010003, rn 0x00040002, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xc000ffff rm 0x80010003, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x3fff0001 rm 0x7fff0003, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x00000001 rm 0xffff0003, rn 0x0004ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x05ec6cac rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfefee06d rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x000bf85c rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfe0b9cf3 rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf17ba3d7 rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfed1e48c rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x07d9b884 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x023049f2 rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x0ee5e6a0 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfd726def rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xee5e2381 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf96881f8 rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x14d7ecc2 rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xe2e60a96 rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfc2bf7c0 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xef9a9946 rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfeac4758 rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf98ccce0 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xeea90989 rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfddc2f4e rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x36a1ba64 rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xe48c78a4 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xee231715 rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x0f77aa68 rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x0e4d01f8 rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf49d0772 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x15bd279c rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x1080777c rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xc9e2bc84 rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf07dc20c rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf558e25c rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf065a516 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x12e41cc8 rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x37346b50 rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf63870d3 rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x1ed8f6a9 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xef674168 rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xdb25a6c0 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf3f3fe24 rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xff192223 rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x11cafd44 rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xf29ea4e8 rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x03d8464c rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x212f12e8 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x08e8ae60 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfcb6112a rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfee60308 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x21080a58 rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0xfd62dd9a rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smultb r0, r1, r2 :: rd 0x078646b8 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00000004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00020004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0xffff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x003b0448 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x0aaeb690 rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x0060973d rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xffd08bd4 rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x01364bc8 rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x0c8ba034 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xe9b87ac8 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xf6ce2d62 rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xcfb878c0 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x03c99878 rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xe04ec043 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xe10c4b16 rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xdcc68d47 rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x19eb600e rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x0ddba470 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x03f4a7f1 rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x11803376 rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xc2e84f40 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xe8f92748 rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x09ad81d0 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x1e5af140 rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xfc4730f2 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x190f938c rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xfb85a144 rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x194e6d3c rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x17bb7c40 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x020d6b25 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xf668f470 rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x06f70390 rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x03987f34 rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x1b37e8b8 rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xf34c9c38 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x1fb3fdec rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xfe4cb6ed rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xdb6f35c4 rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xd573f619 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x0487909b rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x014f56c0 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xcfcc90ac rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x0db4b44c rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xebf7a214 rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x14acfbe8 rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x06c513f6 rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x23010c06 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x20ac71c1 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xdf589e78 rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x04259640 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xffda5ab2 rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0x3a6a827b rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulbt r0, r1, r2 :: rd 0xe4be6035 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000
--------------- SMULW{B,T} --------------
-smulwb r0, r1, r2 :: rd 0x00000000 rm 0x00000003, rn 0x00020004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x00000004 rm 0x00010003, rn 0x47ff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfffe0004 rm 0x80010003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x0001fffc rm 0x7fff0003, rn 0x7fff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfffffffc rm 0xffff0003, rn 0xffff0004, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x05ec94f3 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfefee815 rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x000c1f84 rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfe0bd12f rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf17bdc1c rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfed1def8 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x07d9c655 rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x023044ba rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x0ee61cf2 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfd7265d6 rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xee5df32b rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf96888fb rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x14d7d5bc rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xe2e5f514 rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfc2bf374 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xef9b0af4 rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfeac4eea rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf98cd965 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xeea930ea rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfddc3ed2 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x36a2015b rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xe48c1390 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xee2306fe rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x0f77e42d rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x0e4d28b6 rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf49cf929 rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x15bd47e1 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x1080adae rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xc9e26000 rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf07dc64c rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf558d476 rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf06598b3 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x12e451be rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x3733fc9d rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf6389d95 rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x1ed91317 rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xef67760b rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xdb259f19 rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf3f3ee6c rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xff191737 rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x11cad579 rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xf29efaa6 rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x03d8048b rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x212f5a21 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x08e8e0a7 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfcb6082e rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfee5f817 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x2108411e rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0xfd62fe72 rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwb r0, r1, r2 :: rd 0x07863ed4 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x00000000 rm 0x00000003, rn 0x00040000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x00000004 rm 0x00010003, rn 0x00040002, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xfffe0004 rm 0x80010003, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x0001fffc rm 0x7fff0003, rn 0x00047fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xfffffffc rm 0xffff0003, rn 0x0004ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xf9617a93 rm 0x2575feb2, rn 0xd2c4287c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xfe996a3e rm 0xfb412431, rn 0x4b90362d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xfff8d53e rm 0x004dfbe5, rn 0xe87927cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xffb2f79c rm 0xf6a3fa3c, rn 0x083b3571, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x11e2f016 rm 0xbf17fb9a, rn 0xb9743941, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xf4744347 rm 0x2c0bd024, rn 0xbce5f924, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xf357e91c rm 0x3e976e2e, rn 0xcc3c201c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xf6f7ca4e rm 0xb4bfb365, rn 0x1ebaf88e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x12129b46 rm 0x288593c0, rn 0x722d5e20, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xe37e4cc9 rm 0x4d7ff5b4, rn 0xa1d6f791, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x2155c326 rm 0x4557be13, rn 0x7b11bee7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x1d178319 rm 0xadcf5772, rn 0xa5631488, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x1fe3e564 rm 0x989a7235, rn 0xb10bcc65, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x23127748 rm 0x4d6f393a, rn 0x73f39fca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x0c591db3 rm 0x24a3291e, rn 0x5648e540, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x07e4be02 rm 0xdd91eebf, rn 0xc54f79e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xfcef143e rm 0xf7ce2ec6, rn 0x5fc92974, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xde8e0170 rm 0xbc1083e8, rn 0x7e08184e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xd80a43b9 rm 0xa617cc31, rn 0x71c8315f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x0d7a4073 rm 0xdfe1e8f0, rn 0x9493110e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xe1e4f06c rm 0x6ef49020, rn 0xba8a7e0d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x080b2175 rm 0x3dc4e36b, rn 0x21568e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x1bd45fa3 rm 0x52db4a9d, rn 0x55fcc8cf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x0439d8f4 rm 0x3564c76c, rn 0x14434a2a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x0957545d rm 0x27836b0c, rn 0x3c855ca8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x12eb2acf rm 0x62ff7c30, rn 0x30ece28e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x0161f2a4 rm 0x40955fdf, rn 0x057b562c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x093912fd rm 0x3b34c270, rn 0x27e1475b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xe8328aef rm 0x7fdcda96, rn 0xd05893a7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xf2e3ed84 rm 0xb6ab141d, rn 0x2dc43624, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x14ddebbf rm 0x403d53cb, rn 0x5328d58c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xefff8784 rm 0x21ef1aef, rn 0x87488a4a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xf2bf2f8b rm 0x31458a23, rn 0xbb246228, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xe71bf88b rm 0x848af791, rn 0x339d8d88, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xef63d4d3 rm 0xda3bacdc, rn 0x70974249, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xd1d6e1ec rm 0x649d5cbd, rn 0x8a8d4e7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x0528dcba rm 0xc0c8c881, rn 0xeb1b4335, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x064f53df rm 0x7dd81a20, rn 0x0cd6b508, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x2a26f8ef rm 0x6892886c, rn 0x6731e282, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xfb18a94a rm 0x112dcffc, rn 0xb6edf28f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xe748db71 rm 0xabfabbe6, rn 0x4b4ec9ca, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x069a2f2d rm 0xe52aabf8, rn 0xc1037fa4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x02af8897 rm 0xf2f4df1f, rn 0xcb4ab48f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xead465a1 rm 0x435f909a, rn 0xaf8f7e18, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xf08096c5 rm 0x2106ba5f, rn 0x87df4510, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xf40b6260 rm 0x246a6376, rn 0xabf4e8e1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xff48e565 rm 0x1046a1a3, rn 0xf4c0eeac, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x0029383c rm 0x638ca515, rn 0x006a54f2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0xfb5a1e3c rm 0xf63e7a9d, rn 0x79f74493, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smulwt r0, r1, r2 :: rd 0x1a00ed66 rm 0xbd6845cd, rn 0x9c09e313, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- PKHBT / PKHTB ------------
-pkhbt r0, r1, r2, lsl #0 :: rd 0x55663344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #1 :: rd 0xaacc3344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #2 :: rd 0x55993344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #3 :: rd 0xab333344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #4 :: rd 0x56673344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #16 :: rd 0x77883344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #22 :: rd 0xe2003344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #31 :: rd 0x00003344 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0xc1558082 rm 0x50c28082, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0x69ec2e8f rm 0x17962e8f, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0x03fa43b7 rm 0xc57243b7, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0xf52e26ac rm 0x7eb226ac, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0x7fcbf026 rm 0xbce0f026, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0x2dd07252 rm 0xa5757252, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0x5e4b77c1 rm 0xf4a477c1, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0x464a3a21 rm 0x76723a21, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0xe8101105 rm 0x74d01105, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2 :: rd 0xcd903e2c rm 0xc1273e2c, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #0 :: rd 0x35236e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #1 :: rd 0x6a466e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #2 :: rd 0xd48c6e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #3 :: rd 0xa9196e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #4 :: rd 0x52326e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #8 :: rd 0x23206e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #12 :: rd 0x32046e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #16 :: rd 0x20476e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #24 :: rd 0x47006e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #31 :: rd 0x80006e68 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #0 :: rd 0x89d26261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #1 :: rd 0x13a56261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #2 :: rd 0x274b6261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #3 :: rd 0x4e976261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #4 :: rd 0x9d2e6261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #8 :: rd 0xd2ef6261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #12 :: rd 0x2ef86261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #16 :: rd 0xef866261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #24 :: rd 0x86006261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #31 :: rd 0x00006261 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #0 :: rd 0x57a558cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #1 :: rd 0xaf4a58cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #2 :: rd 0x5e9458cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #3 :: rd 0xbd2858cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #4 :: rd 0x7a5058cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #8 :: rd 0xa50a58cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #12 :: rd 0x50a058cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #16 :: rd 0x0a0158cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #24 :: rd 0x010058cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #31 :: rd 0x800058cb rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #0 :: rd 0xf87b5407 rm 0xd5dc5407, rn 0xf87b961e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #1 :: rd 0x8c36b979 rm 0xd65db979, rn 0xc61b323b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #2 :: rd 0xb4b28abe rm 0xa3268abe, rn 0xed2cbf78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #3 :: rd 0x7db8f0a5 rm 0xbf73f0a5, rn 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #4 :: rd 0x25ef03ed rm 0x281703ed, rn 0x925ef472, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #8 :: rd 0x774152c7 rm 0xeaa652c7, rn 0x137741f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #12 :: rd 0x5bd2de8b rm 0x71fbde8b, rn 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #16 :: rd 0x821a0ad8 rm 0x884c0ad8, rn 0xc00b821a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #24 :: rd 0x69008606 rm 0xe1bb8606, rn 0x58293969, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #31 :: rd 0x8000d624 rm 0xa3cfd624, rn 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #0 :: rd 0x179194e2 rm 0x40b094e2, rn 0x17913309, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #1 :: rd 0x0cb0b5cd rm 0x5388b5cd, rn 0x86582032, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #2 :: rd 0x33e81558 rm 0x5de41558, rn 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #3 :: rd 0x21bc1b46 rm 0x23ba1b46, rn 0x4437983c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #4 :: rd 0x90856549 rm 0x48d06549, rn 0xa9085781, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #8 :: rd 0xaeadac58 rm 0xc6b4ac58, rn 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #12 :: rd 0x1e6af597 rm 0xc2bdf597, rn 0xdde1e6a4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #16 :: rd 0x0dea3a72 rm 0x852e3a72, rn 0x157b0dea, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #24 :: rd 0x740057b4 rm 0xe7aa57b4, rn 0x1584bd74, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhbt r0, r1, r2, lsl #31 :: rd 0x80004d54 rm 0xd4b64d54, rn 0xc53aaba9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #0 :: rd 0x11220000 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #1 :: rd 0x11223bc4 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #2 :: rd 0x11229de2 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #3 :: rd 0x1122cef1 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #4 :: rd 0x11226778 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #16 :: rd 0x11225566 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #22 :: rd 0x11220155 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #31 :: rd 0x11220000 rm 0x11223344, rn 0x55667788, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0x50c23709 rm 0x50c28082, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0x17960212 rm 0x17962e8f, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0xc5729bb5 rm 0xc57243b7, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0x7eb29fbf rm 0x7eb226ac, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0xbce0e5a9 rm 0xbce0f026, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0xa5751366 rm 0xa5757252, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0xf4a41cbf rm 0xf4a477c1, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0x767221cc rm 0x76723a21, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0x74d08f1b rm 0x74d01105, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2 :: rd 0xc127d604 rm 0xc1273e2c, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #0 :: rd 0x5f980000 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #1 :: rd 0x5f989023 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #2 :: rd 0x5f98c811 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #3 :: rd 0x5f986408 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #4 :: rd 0x5f983204 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #8 :: rd 0x5f982320 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #12 :: rd 0x5f985232 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #16 :: rd 0x5f983523 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #24 :: rd 0x5f980035 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #31 :: rd 0x5f980000 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #32 :: rd 0x5f980000 rm 0x5f986e68, rn 0x35232047, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #0 :: rd 0x36f2ffff rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #1 :: rd 0x36f277c3 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #2 :: rd 0x36f2bbe1 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #3 :: rd 0x36f25df0 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #4 :: rd 0x36f22ef8 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #8 :: rd 0x36f2d2ef rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #12 :: rd 0x36f29d2e rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #16 :: rd 0x36f289d2 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #24 :: rd 0x36f2ff89 rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #31 :: rd 0x36f2ffff rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #32 :: rd 0x36f2ffff rm 0x36f26261, rn 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #0 :: rd 0x21610000 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #1 :: rd 0x21618500 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #2 :: rd 0x21614280 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #3 :: rd 0x2161a140 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #4 :: rd 0x216150a0 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #8 :: rd 0x2161a50a rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #12 :: rd 0x21617a50 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #16 :: rd 0x216157a5 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #24 :: rd 0x21610057 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #31 :: rd 0x21610000 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #32 :: rd 0x21610000 rm 0x216158cb, rn 0x57a50a01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #0 :: rd 0xd5dcffff rm 0xd5dc5407, rn 0xf87b961e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #1 :: rd 0xd65d991d rm 0xd65db979, rn 0xc61b323b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #2 :: rd 0xa3262fde rm 0xa3268abe, rn 0xed2cbf78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #3 :: rd 0xbf73e299 rm 0xbf73f0a5, rn 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #4 :: rd 0x2817ef47 rm 0x281703ed, rn 0x925ef472, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #8 :: rd 0xeaa67741 rm 0xeaa652c7, rn 0x137741f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #12 :: rd 0x71fbba5b rm 0x71fbde8b, rn 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #16 :: rd 0x884cc00b rm 0x884c0ad8, rn 0xc00b821a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #24 :: rd 0xe1bb0058 rm 0xe1bb8606, rn 0x58293969, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #31 :: rd 0xa3cf0000 rm 0xa3cfd624, rn 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #32 :: rd 0xa3cf0000 rm 0xa3cfd624, rn 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #0 :: rd 0x40b00000 rm 0x40b094e2, rn 0x17913309, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #1 :: rd 0x53881019 rm 0x5388b5cd, rn 0x86582032, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #2 :: rd 0x5de4871f rm 0x5de41558, rn 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #3 :: rd 0x23baf307 rm 0x23ba1b46, rn 0x4437983c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #4 :: rd 0x48d08578 rm 0x48d06549, rn 0xa9085781, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #8 :: rd 0xc6b4aead rm 0xc6b4ac58, rn 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #12 :: rd 0xc2bdde1e rm 0xc2bdf597, rn 0xdde1e6a4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #16 :: rd 0x852e157b rm 0x852e3a72, rn 0x157b0dea, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #24 :: rd 0xe7aa0015 rm 0xe7aa57b4, rn 0x1584bd74, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #31 :: rd 0xd4b6ffff rm 0xd4b64d54, rn 0xc53aaba9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-pkhtb r0, r1, r2, asr #32 :: rd 0xd4b6ffff rm 0xd4b64d54, rn 0xc53aaba9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------------ USAT -----------------
-usat r0, #0, r1 :: rd 0x00000000 rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #1, r1 :: rd 0x00000001 rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #5, r1 :: rd 0x0000001f rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #8, r1 :: rd 0x000000ff rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #11, r1 :: rd 0x000007ff rm 0x11110000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #13, r1 :: rd 0x00001fff rm 0x11110000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #15, r1 :: rd 0x00007fff rm 0x11110000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, lsl #0 :: rd 0x5f986e68 rm 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat r0, #31, r1, lsl #0 :: rd 0x00000000 rm 0xe7aa57b4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, lsl #0 :: rd 0x00000000 rm 0x89d2ef86, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, lsl #8 :: rd 0x3aaba900 rm 0xc53aaba9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat r0, #31, r1, lsl #8 :: rd 0x6158cb00 rm 0x216158cb, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat r0, #31, r1, lsl #8 :: rd 0x00000000 rm 0x3cd6cd94, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, lsl #0 :: rd 0x00000000 rm 0xf87b961e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, lsl #0 :: rd 0x00000000 rm 0xc61b323b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, lsl #0 :: rd 0x00000000 rm 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, lsl #8 :: rd 0x00000000 rm 0xbf73f0a5, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, lsl #8 :: rd 0x00000000 rm 0x925ef472, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, lsl #8 :: rd 0x00000000 rm 0x137741f4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #24, r1, lsl #2 :: rd 0x00ffffff rm 0x50c28082, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #16, r1, lsl #3 :: rd 0x00000000 rm 0x17962e8f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #12, r1, lsl #4 :: rd 0x00000fff rm 0xc57243b7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #8, r1, lsl #8 :: rd 0x000000ff rm 0xf20fb90f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #4, r1, lsl #12 :: rd 0x0000000f rm 0xbb151055, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #3, r1, lsl #16 :: rd 0x00000007 rm 0x957440d2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #2, r1, lsl #24 :: rd 0x00000003 rm 0x728b7771, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #1, r1, lsl #31 :: rd 0x00000000 rm 0xf13c20f3, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, asr #0 :: rd 0x5f986e68 rm 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat r0, #31, r1, asr #0 :: rd 0x00000000 rm 0xe7aa57b4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, asr #0 :: rd 0x00000000 rm 0x89d2ef86, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, asr #8 :: rd 0x00000000 rm 0xc53aaba9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, asr #8 :: rd 0x00216158 rm 0x216158cb, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat r0, #31, r1, asr #8 :: rd 0x003cd6cd rm 0x3cd6cd94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xf87b961e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xc61b323b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0xbf73f0a5, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0x925ef472, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0x137741f4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #24, r1, asr #2 :: rd 0x00ffffff rm 0x50c28082, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #16, r1, asr #3 :: rd 0x0000ffff rm 0x17962e8f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #12, r1, asr #4 :: rd 0x00000000 rm 0xc57243b7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #8, r1, asr #8 :: rd 0x00000000 rm 0xf20fb90f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #4, r1, asr #12 :: rd 0x00000000 rm 0xbb151055, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #3, r1, asr #16 :: rd 0x00000000 rm 0x957440d2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #2, r1, asr #24 :: rd 0x00000003 rm 0x728b7771, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #1, r1, asr #31 :: rd 0x00000000 rm 0xf13c20f3, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, asr #0 :: rd 0x5f986e68 rm 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat r0, #31, r1, asr #0 :: rd 0x00000000 rm 0xe7aa57b4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, asr #0 :: rd 0x00000000 rm 0x89d2ef86, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, asr #8 :: rd 0x00000000 rm 0xc53aaba9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #31, r1, asr #8 :: rd 0x00216158 rm 0x216158cb, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat r0, #31, r1, asr #8 :: rd 0x003cd6cd rm 0x3cd6cd94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xf87b961e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xc61b323b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #0 :: rd 0x00000000 rm 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0xbf73f0a5, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0x925ef472, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #0, r1, asr #8 :: rd 0x00000000 rm 0x137741f4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #24, r1, asr #2 :: rd 0x00ffffff rm 0x50c28082, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #16, r1, asr #3 :: rd 0x0000ffff rm 0x17962e8f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #12, r1, asr #4 :: rd 0x00000000 rm 0xc57243b7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #8, r1, asr #8 :: rd 0x00000000 rm 0xf20fb90f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #4, r1, asr #12 :: rd 0x00000000 rm 0xbb151055, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #3, r1, asr #16 :: rd 0x00000000 rm 0x957440d2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #2, r1, asr #24 :: rd 0x00000003 rm 0x728b7771, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat r0, #1, r1, asr #31 :: rd 0x00000000 rm 0xf13c20f3, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
------------- USAT16 sat_imm ------------
-usat16 r0, #0, r1 :: rd 0x00000000 rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #1, r1 :: rd 0x00000000 rm 0xffcdabcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #5, r1 :: rd 0x001f0000 rm 0x0123feff, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #8, r1 :: rd 0x00ff0000 rm 0x0123abcd, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #11, r1 :: rd 0x07ff0000 rm 0x11110000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #13, r1 :: rd 0x11110000 rm 0x1111f111, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #15, r1 :: rd 0x00001111 rm 0x00001111, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat16 r0, #0, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #1, r1 :: rd 0x00000000 rm 0xebbff82b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #3, r1 :: rd 0x00070000 rm 0x50c28082, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #5, r1 :: rd 0x001f001f rm 0x17962e8f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #8, r1 :: rd 0x000000ff rm 0xc57243b7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #10, r1 :: rd 0x00000000 rm 0xf20fb90f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #11, r1 :: rd 0x000007ff rm 0xbb151055, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #13, r1 :: rd 0x00001fff rm 0x957440d2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #14, r1 :: rd 0x3fff3fff rm 0x728b7771, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #15, r1 :: rd 0x000020f3 rm 0xf13c20f3, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #0, r1 :: rd 0x00000000 rm 0x86398371, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #1, r1 :: rd 0x00010000 rm 0x03d0fb78, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #3, r1 :: rd 0x00000000 rm 0xd0d49b7c, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #5, r1 :: rd 0x001f001f rm 0x76354a58, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #8, r1 :: rd 0x000000ff rm 0x9fa45fb7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #10, r1 :: rd 0x03ff0000 rm 0x7572bdec, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #11, r1 :: rd 0x00000000 rm 0xfea59eb6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #13, r1 :: rd 0x00000000 rm 0xf2669090, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #14, r1 :: rd 0x00000000 rm 0xbc1ff573, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #15, r1 :: rd 0x7eb226ac rm 0x7eb226ac, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usat16 r0, #0, r1 :: rd 0x00000000 rm 0x22b65db1, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #1, r1 :: rd 0x00010001 rm 0x776c41c7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #3, r1 :: rd 0x00000000 rm 0xe50dd77c, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #5, r1 :: rd 0x00000000 rm 0xd6f9a698, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #8, r1 :: rd 0x000000ff rm 0xeda5110c, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #10, r1 :: rd 0x03ff03ff rm 0x0be36f70, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #11, r1 :: rd 0x00000000 rm 0xd759eb72, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #13, r1 :: rd 0x00000000 rm 0xd9c4b1f4, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #14, r1 :: rd 0x00000000 rm 0xa29eb320, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #15, r1 :: rd 0x00004487 rm 0xcf1e4487, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #0, r1 :: rd 0x00000000 rm 0x2eb68500, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #1, r1 :: rd 0x00000000 rm 0xcdb7ed11, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #3, r1 :: rd 0x00070000 rm 0x2eaea305, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #5, r1 :: rd 0x001f001f rm 0x6ebd04d9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #8, r1 :: rd 0x000000ff rm 0xa5ec1aa8, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #10, r1 :: rd 0x03ff03ff rm 0x72f33509, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #11, r1 :: rd 0x00000000 rm 0xa3e6f759, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #13, r1 :: rd 0x00000000 rm 0xfaceab39, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #14, r1 :: rd 0x27380000 rm 0x2738f0ff, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #15, r1 :: rd 0x00000000 rm 0xe79fd570, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #0, r1 :: rd 0x00000000 rm 0x55ea3e4e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #1, r1 :: rd 0x00010000 rm 0x2b62ba5a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #3, r1 :: rd 0x00000000 rm 0x9b41bfb1, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #5, r1 :: rd 0x001f001f rm 0x557c7ba2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #8, r1 :: rd 0x00ff0000 rm 0x2973c051, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #10, r1 :: rd 0x03ff0000 rm 0x6a228b19, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #11, r1 :: rd 0x07ff0000 rm 0x0cdafabe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #13, r1 :: rd 0x1fff1fff rm 0x50865114, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #14, r1 :: rd 0x00000000 rm 0xd83b849b, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-usat16 r0, #15, r1 :: rd 0x00005605 rm 0xca5e5605, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
----------------- UADD16 ----------------
-uadd16 r0, r1, r2 :: rd 0x00210002 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x00210002 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x00020021 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x00020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0xa299daa0 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x5d604bd2 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x915a7c18 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x24416b8a rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0xf96272fb rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x0e34f4ba rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0xd14ed502 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uadd16 r0, r1, r2 :: rd 0xc4a74327 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uadd16 r0, r1, r2 :: rd 0x164d7875 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0xf06d4ac2 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0xa622c6c7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uadd16 r0, r1, r2 :: rd 0xbc067e14 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0xf988807c rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uadd16 r0, r1, r2 :: rd 0xc318e39d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0x2a863276 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0xba34e1af rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uadd16 r0, r1, r2 :: rd 0x9490883e rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x70c1dfbb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x77f5007b rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0x3ae9b324 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x672fef32 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x67ae5b14 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0xfb099476 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uadd16 r0, r1, r2 :: rd 0xc4f739a4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0xae6f11cf rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0x541b7a29 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x639faa4d rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x1713cd42 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x4a22ee8f rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x8f73708c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0x0ba1c6ef rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0x3c80c488 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uadd16 r0, r1, r2 :: rd 0x316e6d4e rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0xed7176b3 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0x3919bcb5 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x1b2b3c05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0xdbc459b0 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0xf8623908 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x7b31e04a rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x73302af1 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0xb6cee004 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uadd16 r0, r1, r2 :: rd 0x09dd64ff rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x428be5e7 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x0ac31feb rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0xba32d245 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0xa8fa218b rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x5c3d09b6 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd16 r0, r1, r2 :: rd 0x4ab260a3 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd16 r0, r1, r2 :: rd 0x01a8204f rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd16 r0, r1, r2 :: rd 0xe7f2fb84 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
----------------- USUB16 ----------------
-usub16 r0, r1, r2 :: rd 0x01000011 rm 0x04000022, rn 0x03000011, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0xfff1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0x000f0004 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x0004000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0xfffcfff1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x0ddd2e96 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0xbc54a9aa rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0xbd1665e6 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0xd15beae8 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x4e6a7bb7 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0xd7b27558 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0x7a8a604e rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x18d3c68b rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x470fcd95 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0x54ff70a0 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0x48b6bcc7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x0e1430e4 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0x1e3e5e64 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0x14660cb9 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0x76fece8e rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0x74f87b6f rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0xf654ff30 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0x8ca36d9d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0x01cbdfd1 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0x10013180 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0x82190050 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0x8536192e rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0xee978d94 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0xbd5742b4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x0cc7dad7 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x67b1e579 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x2457eadf rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x2c2f516a rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x4cd8b123 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0xaaa74f6c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0x9363dc09 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0xd3c2f4bc rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0xb2fcbe52 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0xf7170bfd rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0x11bd3ef7 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0x6529dc05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x009aef2c rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x36ec7b38 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub16 r0, r1, r2 :: rd 0xc931cb82 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0xae920223 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0x654244dc rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0x333f9e0b rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x1ea1fc75 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0xf4bf49d3 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x0e56e605 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x64da14c9 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub16 r0, r1, r2 :: rd 0x2ce16b08 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x4b66e5cb rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub16 r0, r1, r2 :: rd 0xf0929e5d rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub16 r0, r1, r2 :: rd 0x081e8b18 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
----------------- UADD8 -----------------
-uadd8 r0, r1, r2 :: rd 0x0021ff02 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-uadd8 r0, r1, r2 :: rd 0x0021ff02 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-uadd8 r0, r1, r2 :: rd 0xff020021 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-uadd8 r0, r1, r2 :: rd 0xff020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-uadd8 r0, r1, r2 :: rd 0xff000221 rm 0x00000318, rn 0xff00ff09, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-uadd8 r0, r1, r2 :: rd 0xff020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-uadd8 r0, r1, r2 :: rd 0xff090221 rm 0x00020318, rn 0xff07ff09, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-uadd8 r0, r1, r2 :: rd 0xff090221 rm 0xff07ff09, rn 0x00020318, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-uadd8 r0, r1, r2 :: rd 0xa299daa0 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-uadd8 r0, r1, r2 :: rd 0x5c604bd2 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-uadd8 r0, r1, r2 :: rd 0x915a7b18 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-uadd8 r0, r1, r2 :: rd 0x23416b8a rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-uadd8 r0, r1, r2 :: rd 0xf86272fb rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-uadd8 r0, r1, r2 :: rd 0x0d34f4ba rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-uadd8 r0, r1, r2 :: rd 0xd04ed402 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-uadd8 r0, r1, r2 :: rd 0xc3a74227 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-uadd8 r0, r1, r2 :: rd 0x154d7875 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-uadd8 r0, r1, r2 :: rd 0xef6d4ac2 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-uadd8 r0, r1, r2 :: rd 0xa522c6c7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-uadd8 r0, r1, r2 :: rd 0xbb067d14 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd8 r0, r1, r2 :: rd 0xf888807c rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-uadd8 r0, r1, r2 :: rd 0xc218e39d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-uadd8 r0, r1, r2 :: rd 0x29863176 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-uadd8 r0, r1, r2 :: rd 0xb934e1af rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-uadd8 r0, r1, r2 :: rd 0x9490873e rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-uadd8 r0, r1, r2 :: rd 0x70c1dfbb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-uadd8 r0, r1, r2 :: rd 0x77f5007b rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-uadd8 r0, r1, r2 :: rd 0x3ae9b224 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-uadd8 r0, r1, r2 :: rd 0x662fee32 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-uadd8 r0, r1, r2 :: rd 0x67ae5a14 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-uadd8 r0, r1, r2 :: rd 0xfa099476 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-uadd8 r0, r1, r2 :: rd 0xc4f739a4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-uadd8 r0, r1, r2 :: rd 0xad6f11cf rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-uadd8 r0, r1, r2 :: rd 0x531b7929 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-uadd8 r0, r1, r2 :: rd 0x629fa94d rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-uadd8 r0, r1, r2 :: rd 0x1613cc42 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-uadd8 r0, r1, r2 :: rd 0x4922ed8f rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-uadd8 r0, r1, r2 :: rd 0x8f736f8c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x000b0000 ge[3:0]=1011
-uadd8 r0, r1, r2 :: rd 0x0ba1c6ef rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-uadd8 r0, r1, r2 :: rd 0x3c80c388 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-uadd8 r0, r1, r2 :: rd 0x316e6c4e rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x000b0000 ge[3:0]=1011
-uadd8 r0, r1, r2 :: rd 0xed7176b3 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-uadd8 r0, r1, r2 :: rd 0x3819bbb5 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-uadd8 r0, r1, r2 :: rd 0x1b2b3c05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-uadd8 r0, r1, r2 :: rd 0xdbc459b0 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-uadd8 r0, r1, r2 :: rd 0xf7623808 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-uadd8 r0, r1, r2 :: rd 0x7b31df4a rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-uadd8 r0, r1, r2 :: rd 0x72302af1 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-uadd8 r0, r1, r2 :: rd 0xb6cedf04 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-uadd8 r0, r1, r2 :: rd 0x09dd64ff rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-uadd8 r0, r1, r2 :: rd 0x418be5e7 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-uadd8 r0, r1, r2 :: rd 0x0ac31feb rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-uadd8 r0, r1, r2 :: rd 0xb932d245 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-uadd8 r0, r1, r2 :: rd 0xa8fa218b rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-uadd8 r0, r1, r2 :: rd 0x5b3d09b6 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-uadd8 r0, r1, r2 :: rd 0x4ab260a3 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-uadd8 r0, r1, r2 :: rd 0x01a81f4f rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x000b0000 ge[3:0]=1011
-uadd8 r0, r1, r2 :: rd 0xe7f2fb84 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00080000 ge[3:0]=1000
----------------- USUB8 -----------------
-usub8 r0, r1, r2 :: rd 0x00f1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x000b0000 ge[3:0]=1011
-usub8 r0, r1, r2 :: rd 0x000f0104 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub8 r0, r1, r2 :: rd 0x0104000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub8 r0, r1, r2 :: rd 0xfffc00f1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-usub8 r0, r1, r2 :: rd 0x0100040f rm 0x00000318, rn 0xff00ff09, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-usub8 r0, r1, r2 :: rd 0xfffc00f1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-usub8 r0, r1, r2 :: rd 0x01fb040f rm 0x00020318, rn 0xff07ff09, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-usub8 r0, r1, r2 :: rd 0xff05fcf1 rm 0xff07ff09, rn 0x00020318, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-usub8 r0, r1, r2 :: rd 0x0edd2e96 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x000b0000 ge[3:0]=1011
-usub8 r0, r1, r2 :: rd 0xbc54a9aa rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-usub8 r0, r1, r2 :: rd 0xbd1665e6 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-usub8 r0, r1, r2 :: rd 0xd15bebe8 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub8 r0, r1, r2 :: rd 0x4e6a7cb7 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-usub8 r0, r1, r2 :: rd 0xd7b27658 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-usub8 r0, r1, r2 :: rd 0x7a8a604e rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-usub8 r0, r1, r2 :: rd 0x19d3c68b rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-usub8 r0, r1, r2 :: rd 0x470fce95 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-usub8 r0, r1, r2 :: rd 0x55ff70a0 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-usub8 r0, r1, r2 :: rd 0x49b6bcc7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-usub8 r0, r1, r2 :: rd 0x0f1431e4 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-usub8 r0, r1, r2 :: rd 0x1e3e5e64 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-usub8 r0, r1, r2 :: rd 0x14660db9 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-usub8 r0, r1, r2 :: rd 0x77fecf8e rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub8 r0, r1, r2 :: rd 0x75f87b6f rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-usub8 r0, r1, r2 :: rd 0xf654ff30 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-usub8 r0, r1, r2 :: rd 0x8ca36d9d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-usub8 r0, r1, r2 :: rd 0x01cbe0d1 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-usub8 r0, r1, r2 :: rd 0x10013280 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-usub8 r0, r1, r2 :: rd 0x82190050 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-usub8 r0, r1, r2 :: rd 0x85361a2e rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-usub8 r0, r1, r2 :: rd 0xee978e94 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-usub8 r0, r1, r2 :: rd 0xbe5743b4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-usub8 r0, r1, r2 :: rd 0x0dc7dbd7 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-usub8 r0, r1, r2 :: rd 0x67b1e579 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-usub8 r0, r1, r2 :: rd 0x2457ebdf rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub8 r0, r1, r2 :: rd 0x2c2f526a rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-usub8 r0, r1, r2 :: rd 0x4dd8b123 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-usub8 r0, r1, r2 :: rd 0xaba74f6c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-usub8 r0, r1, r2 :: rd 0x9363dc09 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-usub8 r0, r1, r2 :: rd 0xd4c2f5bc rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub8 r0, r1, r2 :: rd 0xb3fcbe52 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-usub8 r0, r1, r2 :: rd 0xf7170cfd rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-usub8 r0, r1, r2 :: rd 0x12bd3ff7 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-usub8 r0, r1, r2 :: rd 0x6529dc05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-usub8 r0, r1, r2 :: rd 0x019aef2c rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-usub8 r0, r1, r2 :: rd 0x37ec7c38 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-usub8 r0, r1, r2 :: rd 0xc931cb82 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-usub8 r0, r1, r2 :: rd 0xae920223 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-usub8 r0, r1, r2 :: rd 0x664245dc rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-usub8 r0, r1, r2 :: rd 0x333f9e0b rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-usub8 r0, r1, r2 :: rd 0x1fa1fd75 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-usub8 r0, r1, r2 :: rd 0xf4bf49d3 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-usub8 r0, r1, r2 :: rd 0x0f56e605 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-usub8 r0, r1, r2 :: rd 0x64da15c9 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-usub8 r0, r1, r2 :: rd 0x2de16b08 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-usub8 r0, r1, r2 :: rd 0x4c66e6cb rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-usub8 r0, r1, r2 :: rd 0xf1929f5d rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-usub8 r0, r1, r2 :: rd 0x091e8b18 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00090000 ge[3:0]=1001
----------------- QADD16 ----------------
-qadd16 r0, r1, r2 :: rd 0x00210002 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x00210002 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x00020021 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x00020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xa299daa0 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x5d604bd2 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x7fff8000 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x24418000 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xf96272fb rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x0e34f4ba rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xd14ed502 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x7fff4327 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x164d8000 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xf06d4ac2 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x7fffc6c7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xbc068000 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xf9887fff rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xc318e39d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x2a868000 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xba34e1af rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x94907fff rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x70c1dfbb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x8000007b rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x80007fff rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x672f7fff rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x67ae5b14 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xfb099476 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xc4f739a4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xae6f11cf rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x541b7a29 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x80007fff rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x1713cd42 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x4a22ee8f rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x8f738000 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x0ba1c6ef rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x3c807fff rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x316e8000 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xed718000 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x3919bcb5 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x1b2b3c05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xdbc48000 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xf8623908 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x8000e04a rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x73308000 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xb6cee004 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x09dd64ff rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x428be5e7 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x0ac31feb rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xba32d245 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xa8fa8000 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x5c3d09b6 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x4ab260a3 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0x01a8204f rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd16 r0, r1, r2 :: rd 0xe7f2fb84 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000
----------------- QSUB16 ----------------
-qsub16 r0, r1, r2 :: rd 0xfff1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x000f0004 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x0004000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xfffcfff1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x0ddd8000 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xbc54a9aa rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xbd1665e6 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xd15beae8 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x80008000 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x7fff7558 rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x8000604e rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x18d3c68b rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x470fcd95 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x54ff70a0 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x48b67fff rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x0e1430e4 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x1e3e5e64 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x14660cb9 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x76fece8e rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x74f87b6f rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xf654ff30 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x7fff6d9d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x01cbdfd1 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x10013180 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x82190050 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x7fff192e rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x7fff7fff rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xbd5742b4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x0cc77fff rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x8000e579 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x2457eadf rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x8000516a rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x4cd87fff rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xaaa74f6c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x7fffdc09 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xd3c2f4bc rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xb2fcbe52 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xf7170bfd rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x11bd3ef7 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x8000dc05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x009aef2c rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x80008000 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xc931cb82 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xae920223 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x65428000 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x80009e0b rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x1ea1fc75 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xf4bf49d3 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x0e56e605 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x64da14c9 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x2ce16b08 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x4b66e5cb rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0xf0927fff rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub16 r0, r1, r2 :: rd 0x081e7fff rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------------ QSAX -----------------
-qsax r0, r1, r2 :: rd 0x7fff7fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7ffe7fff rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x80008000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x80018000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x00610067 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xff9f0067 rm 0x00030003, rn 0x00640064, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x82368000 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xbbc64b44 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7fff5b21 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x3a7dd4ac rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x80004cd5 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7fffd04a rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xeb92460a rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x306f5ac3 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x593e8aa4 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x35a52b68 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7fff707d rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x3e75ae75 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xfad75d15 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x004dcf84 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7fff8000 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x6476d12d rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x80eb12d5 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7fff18bb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xac8bab3b rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x800007c6 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x80007fff rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x557f2b5d rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7fff973e rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xc5af41fc rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x421f4727 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x938e7fff rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x8000ea3a rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xe3b57fff rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7fff4e7e rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x0c7dd262 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x5a0f8d9b rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xa03b7fff rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x1ab7d509 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x3ce9bc85 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x668c1184 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x902a6706 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x38ed9203 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x80003adb rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x97cdaee6 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7c7af8d9 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xc0748000 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x80006cd4 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x3bdd0323 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x14b53fe1 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0xee24b213 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7fff8000 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x7538520d rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x0da022dd rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x382467e1 rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsax r0, r1, r2 :: rd 0x3fd23338 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------------ QASX -----------------
-qasx r0, r1, r2 :: rd 0x7fff7fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x7fff7ffe rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x80008000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x80008001 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x00670061 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x0067ff9f rm 0x00030003, rn 0x00640064, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x2e40ba3d rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x5deeaa38 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xb25186dd rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xbb1f81c6 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x1f88a1dd rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x32a47fff rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x8000ef46 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x7fffaeef rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x041ebb66 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x0fc77fff rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xfc6c1311 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x8ba50083 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x1cef7fff rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xd73120d2 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x02b6a6be rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xcab67fff rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x09f97499 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x37c1349d rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xcd353511 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xe6477fff rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x6c150536 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x7fff48e5 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xf8417fff rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xbc9f3a5c rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x80007fff rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x283eb99c rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x23b27fff rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x800099e4 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xea335134 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x8000ed96 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x44f5155d rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x70072843 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xc9b38000 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xa79fc62b rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xe44aea28 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xf02ab104 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xa371b6d9 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xf68f8000 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xac95fce6 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xa5488000 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x5b9ce9aa rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x02089636 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x254fdf39 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xeacd29dd rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xda640637 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x8d4bf91a rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x13e622b1 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0x7fff2391 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xba1656cb rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qasx r0, r1, r2 :: rd 0xb03e5364 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------------ SMUAD -----------------
-smuad r0, r1, r2 :: rd 0x80000000 rm 0x80008000, rn 0x80008000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x0000fffe rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x00010000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x00000258 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x00000003 rm 0xffffffff, rn 0xfffc0001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x00002fe2 rm 0xfff70fff, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xdede9cb1 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x02608ef4 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x171c6357 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x143f9593 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xdd110aba rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xc570b2ec rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xe97b9768 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x265801e0 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x0b037b42 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xf240a3db rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xf62fb1c8 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x12780145 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x0691798f rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x03d85a8d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x1acea470 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xe96a4974 rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x1d4ea2dd rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xee624082 rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x110f3afe rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x42a15948 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x32ca703d rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x00a6620b rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xc026f485 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xfdf6ad50 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xd7e10590 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xfe23ce76 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x327a6d06 rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xd0bf2ffa rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xe1415fd7 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x13319aee rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xecd5df72 rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x27421fcb rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x0d65652d rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x1287343c rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x036d5124 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xeb8f9e2a rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x1c044eb7 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xca87d3fd rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x0c9512d8 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x32ceb0f5 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xda0472f0 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xd7be7034 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x040f97cc rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xfba979f6 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x05f0ddd8 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x2d5e498a rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xfb3f197b rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0x085893fc rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xe84c6565 rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuad r0, r1, r2 :: rd 0xeda071c4 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------------ SMUADX ----------------
-smuadx r0, r1, r2 :: rd 0x80000000 rm 0x80008000, rn 0x80008000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x0000fffe rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x00010000 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x00000258 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x00000003 rm 0xffffffff, rn 0xfffc0001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x00002fe2 rm 0xfff70fff, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x0c7d0a11 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x026a9a7c rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xe7ded456 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xf390e6c9 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xd0a195a8 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xce40b14c rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x1d063948 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x1c93fef0 rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x0117f53b rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xeb07829d rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xd29fa17a rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x0fe7ad54 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xf8cd24d4 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x02deb401 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xfa6bb070 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xe7ef0f02 rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xe3654f90 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xdac8ea82 rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xfffc2b7e rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xb97e8122 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x3048302f rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x0be45ef2 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xbf1167ed rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x0209cf08 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xf7b39cd0 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x0c2cff55 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xcd7c2f85 rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x1f64ffb8 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xe2e395bb rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x2cc61db8 rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x090e8f6a rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x163fdcc4 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xe7f54466 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x052f76a4 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xf6506ba9 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xf84db305 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x0bca2d24 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xcb0116b8 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x029b3b24 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xd068271d rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x29954740 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xdac588b7 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xfcd1f36c rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x024b26ca rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x06f653e6 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x21b7614a rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xf85e232b rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x11f523ba rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0x04e080e7 rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smuadx r0, r1, r2 :: rd 0xfe0168fc rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------------ SMLAD -----------------
-smlad r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x0000ffff rm 0x7fff7fff, rn 0x00010001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x0001001f rm 0x80008000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x00000278 rm 0x00640064, rn 0x00030003 rs 0x00000020, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x00000102 rm 0xffffffff, rn 0xfffc0001 rs 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x000030e2 rm 0xfff70fff, rn 0x00030003 rs 0x00000100, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x62e906cb rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xbdfa058d rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x132facec rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x94fd1e4f rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xd3a8b06c rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xfed933b9 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xbfb7c8c7 rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x87826758 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xe9176301 rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x23a346d9 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xaa26f4cc rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x18a2cb54 rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x7b87d52b rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x090f2dfd rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x516de33a rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xf5860663 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xc743547a rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x8f412c7f rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x5b9a2a7c rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x3e1eae90 rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x460a7598 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x9ce3256b rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x2f2d1057 rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xdb70b536 rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x47476ea7 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xa98d7719 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x8e608a4b rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xe66cced8 rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xe9e21a30 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xd4d7fe4a rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x5607de5f rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x84b77889 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x949f6c87 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x39036479 rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x9a767683 rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x21c2fb62 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x2473a541 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x18d37e68 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x42a38017 rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x591d6066 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x8a977ce3 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x7cb70fa8 rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x116c76e8 rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x6a0f70ed rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x17c9dd9b rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xa4a1fbcf rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x7beb0ad6 rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x183c60b5 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x00b7b139 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0xc79bbb47 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlad r0, r1, r2, r3 :: rd 0x0f5e5bec rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- SMLABB, SMLATT, SMLATB, SMLABT ------------
-smlabb r0, r1, r2, r3 :: rd 0x00000000 rm 0x00030000, rn 0x00040000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x00008001 rm 0x00030001, rn 0x00040002 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xc0015ffe rm 0x00038001, rn 0x00047fff rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x3fff8000 rm 0x00037fff, rn 0x00047fff rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x7fff8000 rm 0x0003ffff, rn 0x0004ffff rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x00000003 rm 0x0003fffc, rn 0x0004ffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x54dcfca7 rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xb9bef227 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x153b4744 rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x8a0c31fb rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xd4e3d8d4 rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x084deed9 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xb44a4e42 rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x78bba4e4 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xe370e823 rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x248056d7 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xa0bc6afd rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x30935611 rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x8b5b77e1 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x04dde729 rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x530d7e10 rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xdb5218a5 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xb6e8d187 rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xaf23f094 rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x6606bb89 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x5ba1b213 rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x45c47d16 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x9e30058b rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x56df2997 rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xd2991046 rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x3dc259b1 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x96166d79 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x8636392e rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xe7b29f81 rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x08a72bb8 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x9ea9e2ca rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x4075d0f7 rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x8e7e199f rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xb4ec51d4 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x56fd0b6f rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x7f33d7e4 rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x0666387a rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xf8578d3b rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x1f9f9fe0 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x63afa7cb rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x5960736c rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x88c74551 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x79890b42 rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xff6a0b78 rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x50b1bfe3 rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x1badfbcb rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x93c2e0ef rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x88604d49 rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x458622b3 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x232dd133 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0xc928c69c rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabb r0, r1, r2, r3 :: rd 0x04300a90 rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x00000000 rm 0x00000003, rn 0x00000004 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x00008001 rm 0x00010003, rn 0x00020004 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xc0015ffe rm 0x80010003, rn 0x7fff0004 rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x3fff8000 rm 0x7fff0003, rn 0x7fff0004 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x7fff8000 rm 0xffff0003, rn 0xffff0004 rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x00000003 rm 0xfffc0003, rn 0xffff0004 rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x6da4788c rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xaf1e56a5 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x29fc0b5c rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x94c3dbda rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xd37b24ec rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x018e0a6a rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xbc3f81fc rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x8cfe240c rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xdb82cee5 rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xf1d93837 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xb7fd93e9 rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x17c68a0c rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x9352e808 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xf3cfe6ad rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x3c1a768e rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xf5d9aae3 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x98a68dcb rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x7a6d2da3 rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x76f4dc06 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x42f4f79c rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x40f68d64 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x90a0e1fd rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x3881ee4d rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xd5d1c16e rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x52557a3f rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xc625b6c1 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x8d588b8f rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xe672ad90 rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xe692b574 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xb7b56582 rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x525ce15f rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x7c355080 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x68f68a3b rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x1b138539 rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x9ba81adf rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x2d19cab9 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x10b5b3f8 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x1c472748 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x36598a4f rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x69a8ef0c rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x8b6dc924 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x82f9ea0f rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x09b31cae rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x5fa7d2d6 rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xf19d6ecb rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x92f6d2bf rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0x674d4ded rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xefc97b3f rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xff440fb9 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xec1805b7 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatt r0, r1, r2, r3 :: rd 0xfd3e0a6b rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x00000000 rm 0x00000003, rn 0x00040000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x00008001 rm 0x00010003, rn 0x00040002 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xc0015ffe rm 0x80010003, rn 0x00047fff rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x3fff8000 rm 0x7fff0003, rn 0x00047fff rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x7fff8000 rm 0xffff0003, rn 0x0004ffff rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x00000003 rm 0xfffc0003, rn 0x0004ffff rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x680d6c2f rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xc35917c7 rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x325b20bc rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x9d69f440 rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xd4370054 rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x091ff500 rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xb21ff2d8 rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x71f82a30 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xc9653619 rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xf63f799a rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xa6679b89 rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x2a05361e rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x9a127c08 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xf5d1a121 rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x3839dd9c rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xd3f4bd83 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x9aac6fb7 rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xa4e49fda rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x7a97a5c6 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x5311a34b rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x403f808c rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x9796e87b rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x6ab5581d rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xcefcb21e rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x3a5534e1 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xcf1a27e1 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x8b3fc986 rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xe7af6e55 rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x004dd8e0 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x5045227f rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x4815eff7 rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x7852cb64 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x6abbe852 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x26e6b11f rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x82b6eeac rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x31fc8463 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xfc5bf193 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x2488f008 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x3b5c0f7b rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x7cc2fe64 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x5be18a33 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x7f17b6ab rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xff50e330 rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x686b554f rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xe327a38a rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x9751921f rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x6bdba395 rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xf59d74c1 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0x3127286b rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xdf1acafc rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlatb r0, r1, r2, r3 :: rd 0xe263202d rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x00000000 rm 0x00030000, rn 0x00000004 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x00008001 rm 0x00030001, rn 0x00020004 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xc0015ffe rm 0x00038001, rn 0x7fff0004 rs 0x00005fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x3fff8000 rm 0x00037fff, rn 0x7fff0004 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x7fff8000 rm 0x0003ffff, rn 0xffff0004 rs 0x7fff7fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x00000003 rm 0x0003fffc, rn 0xffff0004 rs 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x4dc4f0ac rm 0xb8035b5b, rn 0xce0ce1ed rs 0x5f986e68, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xad752a6d rm 0x35232047, rn 0x146275d8 rs 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x3366a284 rm 0xe7aa57b4, rn 0x1584bd74 rs 0x2c07a5b4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x89f2ea60 rm 0x32fa0095, rn 0x36f26261 rs 0x89d2ef86, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xd5270eb0 rm 0x8ed8287c, rn 0x02c90120 rs 0xd4b64d54, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xfd71063a rm 0xc53aaba9, rn 0x29300837 rs 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xcf383f4e rm 0x216158cb, rn 0x57a50a01 rs 0xb0d20777, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x84d50b52 rm 0x3e2e1bd7, rn 0x3cd6cd94 rs 0x7e376198, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xcfb4740b rm 0xd5fe2dc4, rn 0xdd914bf7 rs 0xd5dc5407, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xe68d7e29 rm 0xf87b961e, rn 0x1d66879f rs 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xbe862fdd rm 0xd65db979, rn 0xc61b323b rs 0xae930a1a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x3354fb41 rm 0x5ef1f1a8, rn 0xbf73f0a5 rs 0x2fb714c9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x79abb1e1 rm 0x1ffe53d9, rn 0x815bb75b rs 0xa3268abe, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xfdfd2861 rm 0xed2cbf78, rn 0xc6ffabb6 rs 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x440550e5 rm 0xeaa652c7, rn 0x137741f4 rs 0x3dba1164, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xdcc2b0a5 rm 0x3ada0280, rn 0x71fbde8b rs 0xdba5bd25, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xb1c7335b rm 0xda4ba05b, rn 0x90f9833d rs 0x884c0ad8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x5b8baa12 rm 0xc00b821a, rn 0x7fa1d5a6 rs 0x9a4ff1b8, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x575ff409 rm 0xe1bb8606, rn 0x58293969 rs 0x81616d13, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x55d0c59a rm 0x51f31d95, rn 0xa3cfd624 rs 0x6077fb1f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x3d8c3b46 rm 0x0849a0c2, rn 0x0872f25a rs 0x40b094e2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x8f1ce2fd rm 0x17913309, rn 0xf1e03d7e rs 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x8376d405 rm 0x5388b5cd, rn 0x86582032 rs 0x6034078d, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xe5b406ca rm 0x181c436b, rn 0x5de41558 rs 0xccfa1c7e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x5014d953 rm 0x23ba1b46, rn 0x4437983c rs 0x48d06549, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x9f18f9d5 rm 0xa9085781, rn 0xc6b4ac58 rs 0xb2aead21, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x86916f29 rm 0xc2bdf597, rn 0xdde1e6a4 rs 0x852e3a72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xe6e571eb rm 0x157b0dea, rn 0xf0d5ff94 rs 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x198e7544 rm 0x3edad6b6, rn 0x82aceb7a rs 0x0557c6fc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x617b7602 rm 0x6cc9bfa8, rn 0x7f808c15 rs 0x81874a02, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x43cc4e75 rm 0x6b1422c7, rn 0x33921b00 rs 0x3ccad3f7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x8c12acf1 rm 0xd7ce1909, rn 0x3e435701 rs 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xb774acb2 rm 0xb4e16b6e, rn 0x6e13680a rs 0x89436f88, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x6a7e0a27 rm 0x44858efc, rn 0x9002bc30 rs 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x725b4c55 rm 0xbea121ab, rn 0x953ff6ec rs 0x80657c40, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x081e00c5 rm 0x6ffed89f, rn 0x3e8c49b7 rs 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x094073e8 rm 0x7795635d, rn 0x5e6e32dd rs 0xe4999bf2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x33268ce0 rm 0xec0c2f30, rn 0x5736ed46 rs 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x65e1c8d7 rm 0x4f9ddd1b, rn 0x95bca5d8 rs 0x5765b203, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x6a26e9b4 rm 0xc1553709, rn 0x0112b30a rs 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x89a610c0 rm 0x74bd0223, rn 0x03fa9bb5 rs 0x899d9192, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x9c151fa4 rm 0xf52e9fbf, rn 0xb4c510a7 rs 0x7fcbe5a9, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x09ee866e rm 0x64a365ef, rn 0x2dd01366 rs 0xf7b0b13e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x4e05cb6e rm 0x5e4b1cbf, rn 0x44de5ca9 rs 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xfd99a3fb rm 0x299da970, rn 0xe8108f1b rs 0xf5818cfb, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x9022f557 rm 0xcd90d604, rn 0xaa5e9444 rs 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x94433a01 rm 0xe60743c3, rn 0x7acb4de3 rs 0x73c29060, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x4b7f7e58 rm 0x868e7c7d, rn 0x5f77532e rs 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0x1e7bf393 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xe9c0c3b9 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-smlabt r0, r1, r2, r3 :: rd 0xe521a181 rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- UQSUB8 -----------------------------------
-uqsub8 r0, r1, r2 :: rd 0x0000fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x000f0000 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x0000000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0xfffc0000 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x0000000f rm 0x00000318, rn 0xff00ff09, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0xfffc0000 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x0000000f rm 0x00020318, rn 0xff07ff09, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0xff05fc00 rm 0xff07ff09, rn 0x00020318, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00000000 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00003299 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x0000a51f rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x8c0f275c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x1e2e0000 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x72a40000 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x006d0000 rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00003f6a rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x50000000 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00a3007e rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00610c00 rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x03000f00 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x4a001d1e rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00520000 rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x30005000 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00000068 rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x60000061 rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x48180022 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x091d815b rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x002e003c rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00000754 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00004213 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x380007c7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x0000baee rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00000000 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x46ce0364 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x45000000 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x57009001 rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x29620000 rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x11000000 rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x2d004200 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x19273100 rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x008d6cc2 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x3423a500 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00003800 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00107b00 rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x0000b100 rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x71000000 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x006f0000 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x35000000 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x37005289 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x99659500 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00943b00 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x008d1a55 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x280000f7 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x28470000 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x6c000000 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00341400 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x42641600 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00000000 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqsub8 r0, r1, r2 :: rd 0x00210084 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- UQADD8 -----------------------------------
-uqadd8 r0, r1, r2 :: rd 0x0021ffff rm 0x0009ffff, rn 0x001800aa, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x0021ffff rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffff0021 rm 0x00aa0018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffff0021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xff00ff21 rm 0x0000aa18, rn 0xff00ff09, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffff0021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffffff rm 0xff9fefcc, rn 0xff9ffedd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xff09ff21 rm 0xff07ff09, rn 0xaa020318, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xff0fffff rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xbeffb8ff rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x5effa5ff rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x90ff299c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x3432cdc1 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xeeff22ff rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffff78ff rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffcfd4 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xfffffbc2 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xa0ffffff rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffffff rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x77ff13e4 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffff98 rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xfff0ffff rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xd2ff8aa8 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x10bbffff rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffff9b rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x78504af8 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffffcd rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xc0ffffff rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x71ffffff rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffd617 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x9ea63dc7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffecff rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xc3ffff97 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xfff4d378 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xcdc8fdff rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xc90fe85f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffe0ffff rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xefffffdf rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x4fff50ff rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xd5ff95ff rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffa5caff rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x7a49ffff rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xe4fffff3 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffbae90c rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x6afeb51c rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x77ff9dd8 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffcbffff rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xfffff5ff rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x91ff78ff rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xfffbcdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x8aff7dff rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffadff8b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffffff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xff75ffff rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffd290ff rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xf9ffffdd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0x7c8a906b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xddcb39c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uqadd8 r0, r1, r2 :: rd 0xffffdbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- SEL --------------------------------------
-sel r0, r1, r2 :: rd 0x00000000 rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x00010001 rm 0x7fff7fff, rn 0x00010001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xffffffff rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x00030003 rm 0x00640064, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xffff0001 rm 0xfffcffff, rn 0xffff0001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x00030003 rm 0xfff70fff, rn 0x00030003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xce0ce1ed rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xaae3433f rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x32fa0095 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x02c90120 rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x0b02c58a rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x3e2e1bd7 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xdd914bf7 rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xf2b64835 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x5ef1f1a8 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x815bb75b rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xef9e9fd9 rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x3ada0280 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x90f9833d rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x9a4ff1b8 rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x51f31d95 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x0872f25a rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x91edc21d rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x181c436b rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xe7b87e39 rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x82aceb7a rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x6cc9bfa8 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x81874a02 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x33921b00 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xd7ce1909 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x85fbf196 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x6e13680a rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x44858efc rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x390d2c2f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x953ff6ec rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x6ffed89f rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x11bd07d1 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x5e6e32dd rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xec0c2f30 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x231348c0 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x95bca5d8 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xc1553709 rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x69ec0212 rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x03fa9bb5 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xf52e9fbf rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x7fcbe5a9 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x2dd01366 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x5e4b1cbf rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x464a21cc rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xe8108f1b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xcd90d604 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x8217b7df rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x7acb4de3 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x868e7c7d rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x1d133d3d rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0x8f6d3264 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sel r0, r1, r2 :: rd 0xde99ac2f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- QSUB8-------------------------------------
-qsub8 r0, r1, r2 :: rd 0x00f1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x000f0104 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x0104000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0xfffc00f1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7fff7fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7ffe81fe rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x80008000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x81018101 rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0xeaf77a6e rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x6a7f3299 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0xfa0da51f rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x8c0f275c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x1e2e437f rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x80a4ec7f rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0xf86de2cd rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x2b7f8080 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x80a21972 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7fa37f80 rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0xd7610cdd rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x03e00f7f rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x4a521d1e rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7f80e4ee rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x806e507e rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x00d7ae80 rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x60f37b61 rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x4818c480 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x091d8180 rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7f2eeb80 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x997f0754 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7ff98013 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x387f07c7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x65fcbaee rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7f48666b rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x80ce0364 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x807f7f8c rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x80f59001 rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x29802bbf rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x80677f7f rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x2dcf42e6 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x1980317f rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0xf88d80c2 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x3423a57f rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7fe13843 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7f1080fa rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x9826b1f8 rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x71c3676e rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x9480f2d3 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x80fa2bfe rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x37d35289 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x9980957f rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0xfe943bdd rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x418d1a55 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x28f1b6f7 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x2847dd65 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x803cf6e0 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7f3480e3 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x426416f1 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x7ff1d5fc rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qsub8 r0, r1, r2 :: rd 0x43217f84 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- QADD8-------------------------------------
-qadd8 r0, r1, r2 :: rd 0x0021ff02 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x0021ff02 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xff020021 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xff020021 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x7fff7fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xff007f00 rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x80008000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x80ff80ff rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x860f3c48 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xbe457f17 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x5e01a580 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x90a1297f rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x3432cdc1 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xee00224e rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xb28f78bb rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x0f1ccfd4 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x0c84fbc2 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xa0590a34 rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xb59d808f rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x779413e4 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x8044807f rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x19f0c680 rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xd2547fa8 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x107f921c rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x82cdff7f rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x78504af8 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xd78d7dcd rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xc086c130 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x712085a4 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x0080d617 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x7fa63dc7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x1398ec00 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xc33e4897 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x22f47f78 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xcdc8fd84 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xc90fe85f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x80e01797 rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xef6354df rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x4f805088 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x7f037f3a rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xd0a5ca22 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x7a493506 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xe48082f3 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x187fe90c rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x6afeb51c rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x77b79dd8 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x80cb8080 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x3390f580 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x7f807855 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x55fbcdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x7f287d80 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x11ad807f rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xc28080ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x80758023 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x60d27fa6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xf9800c7f rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0x7c7f7f6b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xdd7f397f rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-qadd8 r0, r1, r2 :: rd 0xff80dbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- SHADD8 -----------------------------------
-shadd8 r0, r1, r2 :: rd 0x0010ff01 rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x0010ff01 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xff010010 rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xff010010 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x3fff3fff rm 0x7fff7fff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xff003f00 rm 0x7fff00ff, rn 0x80017f01, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xc000c000 rm 0x80008000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xbfffbfff rm 0x80008000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xc3071e24 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xdf225c0b rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x2f00d2a4 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xc8d0144e rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x1a19e6e0 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xf7001127 rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xd9c73cdd rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x070ee7ea rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x06c2fde1 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xd02c051a rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xdacea5c7 rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x3bca09f2 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xb522914c rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x0cf8e3af rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xe92a45d4 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x085dc90e rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xc1e6ff4d rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x3c2825fc rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xebc63ee6 rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xe0c3e018 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x3810c2d2 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x0083eb0b rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x4fd31ee3 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x09ccf600 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xe11f24cb rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x11fa693c rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xe6e4fec2 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xe407f42f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xa9f00bcb rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xf7312aef rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x27a428c4 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x6a014a1d rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xe8d2e511 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x3d241a03 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xf2acc1f9 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x0c5df406 rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x35ffda0e rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x3bdbceec rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xbfe598a8 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x19c8faa8 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x48b93c2a rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x2afde6fe rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x45143eba rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x08d69c45 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xe188b1ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x963aa511 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x30e948d3 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xfca8066e rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0x3e454835 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xee651c62 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-shadd8 r0, r1, r2 :: rd 0xffa9edf1 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------------ SSAT -----------------
-ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x80008000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0x00000000 rm 0x80008000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0x80008000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0x80008000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0xffff0009, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0xffff0009, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0xfffffc00 rm 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0xffff8004 rm 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #1, r1 :: rd 0x00000000 rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #1, r1 :: rd 0xffffffff rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #1, r1 :: rd 0xffffffff rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #1, r1 :: rd 0xffffffff rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #32, r1 :: rd 0xa231d5e6 rm 0xa231d5e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #32, r1 :: rd 0x10e1968a rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #32, r1 :: rd 0x0e089270 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #32, r1 :: rd 0x9e8e0185 rm 0x9e8e0185, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #32, r1 :: rd 0x3096f12e rm 0x3096f12e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #32, r1 :: rd 0xffc134df rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x256bfdd6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0xffffffff rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0xee2fa46e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x97a7da20, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0xa231d5e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0xffffffff rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0x00000000 rm 0x3096f12e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #1, r1, LSL #31 :: rd 0xffffffff rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0x00000003 rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0x00000003 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0xfffffffc rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0x00000000 rm 0x97a7da20, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0x00000003 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0xfffffffc rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0x00000000 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0x00000003 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0xfffffffc rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #3, r1, LSL #28 :: rd 0xfffffffc rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0x0000001f rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #6, r1, LSL #24 :: rd 0xffffffe0 rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0x0000007f rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0x0000007f rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0x0000007f rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0xffffff80 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0x0000007f rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #8, r1, ASR #18 :: rd 0xfffffff0 rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0x000007ff rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0x000007ff rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0x000007ff rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0xfffff800 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0x000007ff rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #12, r1, ASR #16 :: rd 0xffffffc1 rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0xffff8000 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #16, r1, LSL #12 :: rd 0x00007fff rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0xee2fa46e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0x10e1968a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0x0001ffff rm 0x0e089270, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #18, r1, LSL #8 :: rd 0xfffe0000 rm 0xffc134df, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0x007fffff rm 0x256bfdd6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0xff800000 rm 0xc02a0c05, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0xffb8be91 rm 0xee2fa46e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0xff800000 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0xff800000 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0x0043865a rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0x00382249 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0xff800000 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0x007fffff rm 0x3096f12e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #24, r1, ASR #6 :: rd 0xffff04d3 rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0x04ad7fba rm 0x256bfdd6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0xf8054180 rm 0xc02a0c05, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0xfdc5f48d rm 0xee2fa46e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0xf8000000 rm 0x97a7da20, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0xf8000000 rm 0xa231d5e6, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0x021c32d1 rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0x01c1124e rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0xf8000000 rm 0x9e8e0185, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0x0612de25 rm 0x3096f12e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #28, r1, ASR #3 :: rd 0xfff8269b rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0x12b5feeb rm 0x256bfdd6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0xe0150602 rm 0xc02a0c05, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0xf717d237 rm 0xee2fa46e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0xcbd3ed10 rm 0x97a7da20, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0xd118eaf3 rm 0xa231d5e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0x0870cb45 rm 0x10e1968a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0x07044938 rm 0x0e089270, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0xcf4700c2 rm 0x9e8e0185, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0x184b7897 rm 0x3096f12e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-ssat r0, #31, r1, ASR #1 :: rd 0xffe09a6f rm 0xffc134df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
----------------- SADD8 -----------------
-sadd8 r0, r1, r2 :: rd 0x00dffffc rm 0x00f7ffff, rn 0x00e800fd, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-sadd8 r0, r1, r2 :: rd 0x00dffffc rm 0x00e800fd, rn 0x00f7ffff, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-sadd8 r0, r1, r2 :: rd 0xfffc00df rm 0x00fd00e8, rn 0xffff00f7, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-sadd8 r0, r1, r2 :: rd 0xfffc000f rm 0xffff00f7, rn 0x00fd0018, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-sadd8 r0, r1, r2 :: rd 0xff00fc0f rm 0x0000fd18, rn 0xff00fff7, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-sadd8 r0, r1, r2 :: rd 0xfffc00df rm 0xffff00f7, rn 0x00fd00e8, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-sadd8 r0, r1, r2 :: rd 0xff05fc0f rm 0x00fefd18, rn 0xff07fff7, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-sadd8 r0, r1, r2 :: rd 0xff05fcdf rm 0xff07fff7, rn 0x00fefde8, carryin 0, cpsr 0x00040000 ge[3:0]=0100
-sadd8 r0, r1, r2 :: rd 0x860f3c48 rm 0xb8035b5b, rn 0xce0ce1ed, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-sadd8 r0, r1, r2 :: rd 0xbe45b817 rm 0x146275d8, rn 0xaae3433f, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-sadd8 r0, r1, r2 :: rd 0x5e01a549 rm 0x2c07a5b4, rn 0x32fa0095, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-sadd8 r0, r1, r2 :: rd 0x90a1299c rm 0x8ed8287c, rn 0x02c90120, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-sadd8 r0, r1, r2 :: rd 0x3432cdc1 rm 0x29300837, rn 0x0b02c58a, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-sadd8 r0, r1, r2 :: rd 0xee00224e rm 0xb0d20777, rn 0x3e2e1bd7, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-sadd8 r0, r1, r2 :: rd 0xb28f78bb rm 0xd5fe2dc4, rn 0xdd914bf7, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-sadd8 r0, r1, r2 :: rd 0x0f1ccfd4 rm 0x1d66879f, rn 0xf2b64835, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-sadd8 r0, r1, r2 :: rd 0x0c84fbc2 rm 0xae930a1a, rn 0x5ef1f1a8, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-sadd8 r0, r1, r2 :: rd 0xa0590a34 rm 0x1ffe53d9, rn 0x815bb75b, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-sadd8 r0, r1, r2 :: rd 0xb59d4a8f rm 0xc6ffabb6, rn 0xef9e9fd9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sadd8 r0, r1, r2 :: rd 0x779413e4 rm 0x3dba1164, rn 0x3ada0280, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-sadd8 r0, r1, r2 :: rd 0x6a442398 rm 0xda4ba05b, rn 0x90f9833d, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-sadd8 r0, r1, r2 :: rd 0x19f0c65e rm 0x7fa1d5a6, rn 0x9a4ff1b8, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-sadd8 r0, r1, r2 :: rd 0xd2548aa8 rm 0x81616d13, rn 0x51f31d95, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-sadd8 r0, r1, r2 :: rd 0x10bb921c rm 0x0849a0c2, rn 0x0872f25a, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-sadd8 r0, r1, r2 :: rd 0x82cdff9b rm 0xf1e03d7e, rn 0x91edc21d, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-sadd8 r0, r1, r2 :: rd 0x78504af8 rm 0x6034078d, rn 0x181c436b, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-sadd8 r0, r1, r2 :: rd 0xd78d7dcd rm 0xf0d5ff94, rn 0xe7b87e39, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-sadd8 r0, r1, r2 :: rd 0xc086c130 rm 0x3edad6b6, rn 0x82aceb7a, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-sadd8 r0, r1, r2 :: rd 0x712085a4 rm 0x0557c6fc, rn 0x6cc9bfa8, carryin 0, cpsr 0x000c0000 ge[3:0]=1100
-sadd8 r0, r1, r2 :: rd 0x0007d617 rm 0x7f808c15, rn 0x81874a02, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-sadd8 r0, r1, r2 :: rd 0x9ea63dc7 rm 0x6b1422c7, rn 0x33921b00, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-sadd8 r0, r1, r2 :: rd 0x1398ec00 rm 0x3ccad3f7, rn 0xd7ce1909, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-sadd8 r0, r1, r2 :: rd 0xc33e4897 rm 0x3e435701, rn 0x85fbf196, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-sadd8 r0, r1, r2 :: rd 0x22f4d378 rm 0xb4e16b6e, rn 0x6e13680a, carryin 0, cpsr 0x000b0000 ge[3:0]=1011
-sadd8 r0, r1, r2 :: rd 0xcdc8fd84 rm 0x89436f88, rn 0x44858efc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sadd8 r0, r1, r2 :: rd 0xc90fe85f rm 0x9002bc30, rn 0x390d2c2f, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-sadd8 r0, r1, r2 :: rd 0x53e01797 rm 0xbea121ab, rn 0x953ff6ec, carryin 0, cpsr 0x00020000 ge[3:0]=0010
-sadd8 r0, r1, r2 :: rd 0xef6354df rm 0x80657c40, rn 0x6ffed89f, carryin 0, cpsr 0x00060000 ge[3:0]=0110
-sadd8 r0, r1, r2 :: rd 0x4f495088 rm 0x3e8c49b7, rn 0x11bd07d1, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-sadd8 r0, r1, r2 :: rd 0xd503953a rm 0x7795635d, rn 0x5e6e32dd, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-sadd8 r0, r1, r2 :: rd 0xd0a5ca22 rm 0xe4999bf2, rn 0xec0c2f30, carryin 0, cpsr 0x00010000 ge[3:0]=0001
-sadd8 r0, r1, r2 :: rd 0x7a493506 rm 0x5736ed46, rn 0x231348c0, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-sadd8 r0, r1, r2 :: rd 0xe45982f3 rm 0x4f9ddd1b, rn 0x95bca5d8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sadd8 r0, r1, r2 :: rd 0x18bae90c rm 0x5765b203, rn 0xc1553709, carryin 0, cpsr 0x000d0000 ge[3:0]=1101
-sadd8 r0, r1, r2 :: rd 0x6afeb51c rm 0x0112b30a, rn 0x69ec0212, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-sadd8 r0, r1, r2 :: rd 0x77b79dd8 rm 0x74bd0223, rn 0x03fa9bb5, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-sadd8 r0, r1, r2 :: rd 0x7ecb3051 rm 0x899d9192, rn 0xf52e9fbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sadd8 r0, r1, r2 :: rd 0x3390f550 rm 0xb4c510a7, rn 0x7fcbe5a9, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-sadd8 r0, r1, r2 :: rd 0x91737855 rm 0x64a365ef, rn 0x2dd01366, carryin 0, cpsr 0x000b0000 ge[3:0]=1011
-sadd8 r0, r1, r2 :: rd 0x55fbcdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00080000 ge[3:0]=1000
-sadd8 r0, r1, r2 :: rd 0x8a287d75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x000e0000 ge[3:0]=1110
-sadd8 r0, r1, r2 :: rd 0x11ad388b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00090000 ge[3:0]=1001
-sadd8 r0, r1, r2 :: rd 0xc21162ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sadd8 r0, r1, r2 :: rd 0x2c754b23 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00050000 ge[3:0]=0101
-sadd8 r0, r1, r2 :: rd 0x60d290a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x000a0000 ge[3:0]=1010
-sadd8 r0, r1, r2 :: rd 0xf9500cdd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00030000 ge[3:0]=0011
-sadd8 r0, r1, r2 :: rd 0x7c8a906b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x000f0000 ge[3:0]=1111
-sadd8 r0, r1, r2 :: rd 0xddcb39c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00070000 ge[3:0]=0111
-sadd8 r0, r1, r2 :: rd 0xff53dbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- SXTAB ------------
-sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0xf7b0b19c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0x44de5cef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0x299da958 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0xf5818cc8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0xaa5e93c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0xe607443d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0x73c28fe6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0x5f77534b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0x4e5e06ef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #24 :: rd 0x21ba2f91 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0xf7b0b189 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0x44de5cf3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0x299da980 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0xf5818c8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0xaa5e945b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0xe607438e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0x73c28fee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0x5f775341 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0x4e5e07cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #16 :: rd 0x21ba2f4c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0xf7b0b15a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0x44de5cca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0x299da8ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0xf5818cd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0xaa5e93fb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0xe6074410 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0x73c290dc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0x5f77536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0x4e5e0792 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #8 :: rd 0x21ba2f5f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0xf7b0b0fd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0x44de5c75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0x299da98b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0xf5818cff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0xaa5e9423 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0xe60743a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0x73c290dd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0x5f77536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0x4e5e07c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtab r0, r1, r2, ROR #0 :: rd 0x21ba2fe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- UXTAB ------------
-uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0x314159c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0xf7b0b19c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0x44de5cef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0x299daa58 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0xf5818dc8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0xaa5e94c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0xe607443d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0x73c290e6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0x5f77534b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0x4e5e07ef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #24 :: rd 0x21ba3091 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0xf7b0b189 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0x44de5cf3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0x299da980 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0xf5818d8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0xaa5e945b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0xe607448e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0x73c290ee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0x5f775341 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0x4e5e07cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #16 :: rd 0x21ba304c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0xf7b0b15a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0x44de5cca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0x299da9ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0xf5818dd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0xaa5e94fb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0xe6074410 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0x73c290dc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0x5f77536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0x4e5e0792 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #8 :: rd 0x21ba305f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0xf7b0b1fd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0x44de5d75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0x299da98b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0xf5818cff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0xaa5e9523 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0xe60744a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0x73c290dd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0x5f77536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0x4e5e07c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab r0, r1, r2, ROR #0 :: rd 0x21ba2fe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------ UXTAB16 -----------
-uxtab16 r0, r1, r2, ROR #24 :: rd 0x3169594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0x315a593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0x3168594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0x31595940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0x3169594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0x31da593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0x3168594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0x315959c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0x31590098 rm 0x3141ffff, rn 0x27182899, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0xf7ccb19c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0x44ff5cef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0x2a2caa58 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0xf6578dc8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0xab1594c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0xe654443d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0x743e90e6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0x5fb4534b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0x4e9007ef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #24 :: rd 0x22663091 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0xf86fb189 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0x45aa5cf3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0x29b8a980 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0xf5858d8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0xab3d945b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0xe6ea448e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0x743f90ee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0x5fb45341 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0x4ec207cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #16 :: rd 0x21e9304c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0xf80eb15a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0x45245cca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0x2a85a9ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0xf64e8dd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0xaae094fb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0xe6814410 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0x744890dc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0x5f94536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0x4eed0792 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #8 :: rd 0x2298305f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0xf7fbb1fd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0x45285d75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0x29ada98b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0xf6118cff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0xaa759523 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0xe6d244a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0x745090dd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0x5f8a536b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0x4ecb07c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtab16 r0, r1, r2, ROR #0 :: rd 0x22532fe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- SXTAH ------------
-sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0x3140f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0xf7b0709c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0x44de28ef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0x299dc558 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0xf58191c8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0xaa5e73c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0xe607273d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0x73c30de6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0x5f77904b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0x4e5e6bef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #24 :: rd 0x21ba5f91 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0xf7b10f89 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0x44dea2f3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0x299d9180 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0xf5815a8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0xaa5e165b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0xe607be8e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0x73c216ee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0x5f777041 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0x4e5d96cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #16 :: rd 0x21ba0e4c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0xf7b0fc5a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0x44dea6ca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0x299db9ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0xf5811dd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0xaa5eabfb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0xe6070f10 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0x73c21edc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0x5f77666b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0x4e5e7492 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #8 :: rd 0x21b9c95f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0xf7b0cdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0x44de7e75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0x299d388b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0xf58162ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0xaa5e4c23 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0xe60791a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0x73c30cdd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0x5f77906b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0x4e5e39c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-sxtah r0, r1, r2, ROR #0 :: rd 0x21b9dbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------- UXTAH ------------
-uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0xf7b1709c rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0x44df28ef rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0x299dc558 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0xf58191c8 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0xaa5f73c6 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0xe608273d rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0x73c30de6 rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0x5f77904b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0x4e5e6bef rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #24 :: rd 0x21ba5f91 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0xf7b10f89 rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0x44dea2f3 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0x299e9180 rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0xf5825a8b rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0xaa5f165b rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0xe607be8e rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0x73c316ee rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0x5f777041 rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0x4e5e96cd rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #16 :: rd 0x21bb0e4c rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0xf7b0fc5a rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0x44dea6ca rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0x299db9ff rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0xf5821dd1 rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0xaa5eabfb rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0xe6080f10 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0x73c31edc rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0x5f77666b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0x4e5e7492 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #8 :: rd 0x21bac95f rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0xf7b0cdfd rm 0xf7b0b13e, rn 0x5e4b1cbf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0x44de7e75 rm 0x44de5ca9, rn 0x464a21cc, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0x299e388b rm 0x299da970, rn 0xe8108f1b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0xf58262ff rm 0xf5818cfb, rn 0xcd90d604, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0xaa5f4c23 rm 0xaa5e9444, rn 0x8217b7df, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0xe60791a6 rm 0xe60743c3, rn 0x7acb4de3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0x73c30cdd rm 0x73c29060, rn 0x868e7c7d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0x5f77906b rm 0x5f77532e, rn 0x1d133d3d, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0x4e5e39c4 rm 0x4e5e0760, rn 0x8f6d3264, carryin 0, cpsr 0x00000000 ge[3:0]=0000
-uxtah r0, r1, r2, ROR #0 :: rd 0x21badbe2 rm 0x21ba2fb3, rn 0xde99ac2f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
------------ SMLAWB ------------
smlawb r0, r1, r2, r3 :: rd 0x00000000 rm 0x00030000, rn 0x00040000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
smlawb r0, r1, r2, r3 :: rd 0x00008005 rm 0x00030001, rn 0x00040002 rs 0x00007fff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
@@ -5569,3 +3231,117 @@
usada8 r0, r1, r2, r3 :: rd 0x21ba3032 rm 0x4e5e0760, rn 0x8f6d3264 rs 0x21ba2fb3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
usada8 r0, r1, r2, r3 :: rd 0xeda512a7 rm 0xde99ac2f, rn 0x0be36f70 rs 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
usada8 r0, r1, r2, r3 :: rd 0xf20fb99e rm 0xc57243b7, rn 0xcf1e4487 rs 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+---------------- QADD ----------------
+qadd r0, r1, r2 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x7fffffff rm 0x00000001, rn 0x7fffffff, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xa299daa0 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x5d614bd2 rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x7fffffff rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x24426b8a rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xf96372fb rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x0e34f4ba rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xd14ed502 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x7fffffff rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x164e7875 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xf06e4ac2 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x7fffffff rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xbc077e14 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xf988807c rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xc319e39d rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x2a873276 rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xba34e1af rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x9490883e rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x70c1dfbb rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x80000000 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x80000000 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x672fef32 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x67ae5b14 rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xfb099476 rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xc4f839a4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xae7011cf rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x541b7a29 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x80000000 rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x1713cd42 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x4a22ee8f rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x8f74708c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x0ba2c6ef rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x3c80c488 rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x316f6d4e rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xed7276b3 rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x391abcb5 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x1b2b3c05 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xdbc559b0 rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xf8633908 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x80000000 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x73312af1 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xb6cee004 rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x09dd64ff rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x428ce5e7 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x0ac41feb rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xba33d245 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xa8fb218b rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x5c3e09b6 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x4ab260a3 rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0x01a9204f rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qadd r0, r1, r2 :: rd 0xe7f2fb84 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+---------------- QSUB ----------------
+qsub r0, r1, r2 :: rd 0x80000001 rm 0x00000000, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x80000002 rm 0x00000001, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xfff1fffc rm 0x0009ffff, rn 0x00180003, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x000e0004 rm 0x00180003, rn 0x0009ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x0004000f rm 0x00030018, rn 0xffff0009, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xfffbfff1 rm 0xffff0009, rn 0x00030018, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x0ddd2e96 rm 0xd83b849b, rn 0xca5e5605, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xbc54a9aa rm 0x0cdafabe, rn 0x50865114, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xbd1665e6 rm 0x2738f0ff, rn 0x6a228b19, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xd15aeae8 rm 0xfaceab39, rn 0x2973c051, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x80000000 rm 0xa3e6f759, rn 0x557c7ba2, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x7fffffff rm 0x72f33509, rn 0x9b41bfb1, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x80000000 rm 0xa5ec1aa8, rn 0x2b62ba5a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x18d2c68b rm 0x6ebd04d9, rn 0x55ea3e4e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x470ecd95 rm 0x2eaea305, rn 0xe79fd570, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x54fe70a0 rm 0x22b65db1, rn 0xcdb7ed11, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x48b5bcc7 rm 0x776c41c7, rn 0x2eb68500, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x0e1430e4 rm 0xe50dd77c, rn 0xd6f9a698, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x1e3e5e64 rm 0x0be36f70, rn 0xeda5110c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x14660cb9 rm 0xebbff82b, rn 0xd759eb72, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x76fdce8e rm 0x50c28082, rn 0xd9c4b1f4, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x74f77b6f rm 0x17962e8f, rn 0xa29eb320, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xf653ff30 rm 0xc57243b7, rn 0xcf1e4487, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x7fffffff rm 0x7eb226ac, rn 0xf20fb90f, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x01cbdfd1 rm 0xbce0f026, rn 0xbb151055, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x10013180 rm 0xa5757252, rn 0x957440d2, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x82190050 rm 0xf4a477c1, rn 0x728b7771, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x7fffffff rm 0x76723a21, rn 0xf13c20f3, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x7fffffff rm 0x74d01105, rn 0x86398371, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xbd5642b4 rm 0xc1273e2c, rn 0x03d0fb78, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x0cc6dad7 rm 0xdd9b7653, rn 0xd0d49b7c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x80000000 rm 0xdde62fd1, rn 0x76354a58, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x2456eadf rm 0xc3fb4a96, rn 0x9fa45fb7, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x80000000 rm 0xa1a10f56, rn 0x7572bdec, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x4cd7b123 rm 0x4b7d4fd9, rn 0xfea59eb6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xaaa74f6c rm 0x9d0ddffc, rn 0xf2669090, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x7fffffff rm 0x4f82d17c, rn 0xbc1ff573, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xd3c1f4bc rm 0x08215ca2, rn 0x345f67e6, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xb2fbbe52 rm 0xf23595d0, rn 0x3f39d77e, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xf7170bfd rm 0xf244c158, rn 0xfb2db55b, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x11bd3ef7 rm 0x256bfdd6, rn 0x13aebedf, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x80000000 rm 0xc02a0c05, rn 0x5b013000, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x0099ef2c rm 0xee2fa46e, rn 0xed95b542, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x80000000 rm 0x97a7da20, rn 0x60bb5ee8, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xc931cb82 rm 0xa231d5e6, rn 0xd9000a64, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xae920223 rm 0x10e1968a, rn 0x624f9467, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x654244dc rm 0x0e089270, rn 0xa8c64d94, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x80000000 rm 0x9e8e0185, rn 0x6b4f637a, carryin 0, cpsr 0x08000000 Q ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x1ea0fc75 rm 0x3096f12e, rn 0x11f5f4b9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xf4be49d3 rm 0xffc134df, rn 0x0b02eb0c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x0e55e605 rm 0xe444dc25, rn 0xd5eef620, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x64da14c9 rm 0x06ea9b2a, rn 0xa2108661, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x2ce06b08 rm 0x448f3a5f, rn 0x17aecf57, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x4b65e5cb rm 0x4b0c2337, rn 0xffa63d6c, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0xf0919e5d rm 0xf91d5f56, rn 0x088bc0f9, carryin 0, cpsr 0x00000000 ge[3:0]=0000
+qsub r0, r1, r2 :: rd 0x081d8b18 rm 0xf808434e, rn 0xefeab836, carryin 0, cpsr 0x00000000 ge[3:0]=0000
diff --git a/main/none/tests/arm/v6media.vgtest b/main/none/tests/arm/v6media.vgtest
index a9d419e..275239d 100644
--- a/main/none/tests/arm/v6media.vgtest
+++ b/main/none/tests/arm/v6media.vgtest
@@ -1,4 +1,2 @@
prog: v6media
vgopts: -q
-prog: v6media
-vgopts: -q
diff --git a/main/none/tests/arm/vcvt_fixed_float_VFP.c b/main/none/tests/arm/vcvt_fixed_float_VFP.c
new file mode 100644
index 0000000..ef6e034
--- /dev/null
+++ b/main/none/tests/arm/vcvt_fixed_float_VFP.c
@@ -0,0 +1,90 @@
+
+#include <stdio.h>
+
+__attribute__((noinline)) float s_to_f32_imm1(int x)
+{
+ float y;
+ __asm__ ("vcvt.f32.s32 %0, %1, #1" : "=w"(y) : "0"(x));
+ return y;
+}
+
+__attribute__((noinline)) float s_to_f32_imm32(int x)
+{
+ float y;
+ __asm__ ("vcvt.f32.s32 %0, %1, #32" : "=w"(y) : "0"(x));
+ return y;
+}
+
+void try_s_to_f32 ( int x )
+{
+ float f32 = s_to_f32_imm32(x);
+ printf("s_to_f32_imm32: %11d -> %18.14e\n", x, (double)f32);
+ f32 = s_to_f32_imm1(x);
+ printf("s_to_f32_imm1: %11d -> %18.14e\n", x, (double)f32);
+}
+
+
+
+__attribute__((noinline)) float u_to_f32_imm1(int x)
+{
+ float y;
+ __asm__ ("vcvt.f32.u32 %0, %1, #1" : "=w"(y) : "0"(x));
+ return y;
+}
+
+__attribute__((noinline)) float u_to_f32_imm32(int x)
+{
+ float y;
+ __asm__ ("vcvt.f32.u32 %0, %1, #32" : "=w"(y) : "0"(x));
+ return y;
+}
+
+void try_u_to_f32 ( unsigned int x )
+{
+ float f32 = u_to_f32_imm32(x);
+ printf("u_to_f32_imm32: %11u -> %18.14e\n", x, (double)f32);
+ f32 = u_to_f32_imm1(x);
+ printf("u_to_f32_imm1: %11u -> %18.14e\n", x, (double)f32);
+}
+
+
+//__attribute__((noinline)) double s_to_f64_imm1(int x)
+//{
+// double y;
+// __asm__ ("vcvt.f64.s32 %P0, %1, #4" : "=w"(y) : "0"((long long)x));
+// return y;
+//}
+
+
+
+
+int main ( void )
+{
+ int i;
+ //float f = foo(1);
+ //__asm__ __volatile__("" : : "r"(f) : "cc","memory");
+ try_s_to_f32(0);
+ try_s_to_f32(1);
+ for (i = 100; i < 200; i++) {
+ try_s_to_f32(i);
+ }
+ try_s_to_f32(0x7FFFFFFE);
+ try_s_to_f32(0x7FFFFFFF);
+ try_s_to_f32(0x80000000);
+ try_s_to_f32(0x80000001);
+ try_s_to_f32(0xFFFFFFFE);
+ try_s_to_f32(0xFFFFFFFF);
+ printf("\n");
+ try_u_to_f32(0);
+ try_u_to_f32(1);
+ for (i = 100; i < 200; i++) {
+ try_u_to_f32(i);
+ }
+ try_u_to_f32(0x7FFFFFFE);
+ try_u_to_f32(0x7FFFFFFF);
+ try_u_to_f32(0x80000000);
+ try_u_to_f32(0x80000001);
+ try_u_to_f32(0xFFFFFFFE);
+ try_u_to_f32(0xFFFFFFFF);
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/arm/vcvt_fixed_float_VFP.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/arm/vcvt_fixed_float_VFP.stderr.exp
diff --git a/main/none/tests/arm/vcvt_fixed_float_VFP.stdout.exp b/main/none/tests/arm/vcvt_fixed_float_VFP.stdout.exp
new file mode 100644
index 0000000..a444fe3
--- /dev/null
+++ b/main/none/tests/arm/vcvt_fixed_float_VFP.stdout.exp
@@ -0,0 +1,433 @@
+s_to_f32_imm32: 0 -> 0.00000000000000e+00
+s_to_f32_imm1: 0 -> 0.00000000000000e+00
+s_to_f32_imm32: 1 -> 2.32830643653870e-10
+s_to_f32_imm1: 1 -> 5.00000000000000e-01
+s_to_f32_imm32: 100 -> 2.32830643653870e-08
+s_to_f32_imm1: 100 -> 5.00000000000000e+01
+s_to_f32_imm32: 101 -> 2.35158950090408e-08
+s_to_f32_imm1: 101 -> 5.05000000000000e+01
+s_to_f32_imm32: 102 -> 2.37487256526947e-08
+s_to_f32_imm1: 102 -> 5.10000000000000e+01
+s_to_f32_imm32: 103 -> 2.39815562963486e-08
+s_to_f32_imm1: 103 -> 5.15000000000000e+01
+s_to_f32_imm32: 104 -> 2.42143869400024e-08
+s_to_f32_imm1: 104 -> 5.20000000000000e+01
+s_to_f32_imm32: 105 -> 2.44472175836563e-08
+s_to_f32_imm1: 105 -> 5.25000000000000e+01
+s_to_f32_imm32: 106 -> 2.46800482273102e-08
+s_to_f32_imm1: 106 -> 5.30000000000000e+01
+s_to_f32_imm32: 107 -> 2.49128788709641e-08
+s_to_f32_imm1: 107 -> 5.35000000000000e+01
+s_to_f32_imm32: 108 -> 2.51457095146179e-08
+s_to_f32_imm1: 108 -> 5.40000000000000e+01
+s_to_f32_imm32: 109 -> 2.53785401582718e-08
+s_to_f32_imm1: 109 -> 5.45000000000000e+01
+s_to_f32_imm32: 110 -> 2.56113708019257e-08
+s_to_f32_imm1: 110 -> 5.50000000000000e+01
+s_to_f32_imm32: 111 -> 2.58442014455795e-08
+s_to_f32_imm1: 111 -> 5.55000000000000e+01
+s_to_f32_imm32: 112 -> 2.60770320892334e-08
+s_to_f32_imm1: 112 -> 5.60000000000000e+01
+s_to_f32_imm32: 113 -> 2.63098627328873e-08
+s_to_f32_imm1: 113 -> 5.65000000000000e+01
+s_to_f32_imm32: 114 -> 2.65426933765411e-08
+s_to_f32_imm1: 114 -> 5.70000000000000e+01
+s_to_f32_imm32: 115 -> 2.67755240201950e-08
+s_to_f32_imm1: 115 -> 5.75000000000000e+01
+s_to_f32_imm32: 116 -> 2.70083546638489e-08
+s_to_f32_imm1: 116 -> 5.80000000000000e+01
+s_to_f32_imm32: 117 -> 2.72411853075027e-08
+s_to_f32_imm1: 117 -> 5.85000000000000e+01
+s_to_f32_imm32: 118 -> 2.74740159511566e-08
+s_to_f32_imm1: 118 -> 5.90000000000000e+01
+s_to_f32_imm32: 119 -> 2.77068465948105e-08
+s_to_f32_imm1: 119 -> 5.95000000000000e+01
+s_to_f32_imm32: 120 -> 2.79396772384644e-08
+s_to_f32_imm1: 120 -> 6.00000000000000e+01
+s_to_f32_imm32: 121 -> 2.81725078821182e-08
+s_to_f32_imm1: 121 -> 6.05000000000000e+01
+s_to_f32_imm32: 122 -> 2.84053385257721e-08
+s_to_f32_imm1: 122 -> 6.10000000000000e+01
+s_to_f32_imm32: 123 -> 2.86381691694260e-08
+s_to_f32_imm1: 123 -> 6.15000000000000e+01
+s_to_f32_imm32: 124 -> 2.88709998130798e-08
+s_to_f32_imm1: 124 -> 6.20000000000000e+01
+s_to_f32_imm32: 125 -> 2.91038304567337e-08
+s_to_f32_imm1: 125 -> 6.25000000000000e+01
+s_to_f32_imm32: 126 -> 2.93366611003876e-08
+s_to_f32_imm1: 126 -> 6.30000000000000e+01
+s_to_f32_imm32: 127 -> 2.95694917440414e-08
+s_to_f32_imm1: 127 -> 6.35000000000000e+01
+s_to_f32_imm32: 128 -> 2.98023223876953e-08
+s_to_f32_imm1: 128 -> 6.40000000000000e+01
+s_to_f32_imm32: 129 -> 3.00351530313492e-08
+s_to_f32_imm1: 129 -> 6.45000000000000e+01
+s_to_f32_imm32: 130 -> 3.02679836750031e-08
+s_to_f32_imm1: 130 -> 6.50000000000000e+01
+s_to_f32_imm32: 131 -> 3.05008143186569e-08
+s_to_f32_imm1: 131 -> 6.55000000000000e+01
+s_to_f32_imm32: 132 -> 3.07336449623108e-08
+s_to_f32_imm1: 132 -> 6.60000000000000e+01
+s_to_f32_imm32: 133 -> 3.09664756059647e-08
+s_to_f32_imm1: 133 -> 6.65000000000000e+01
+s_to_f32_imm32: 134 -> 3.11993062496185e-08
+s_to_f32_imm1: 134 -> 6.70000000000000e+01
+s_to_f32_imm32: 135 -> 3.14321368932724e-08
+s_to_f32_imm1: 135 -> 6.75000000000000e+01
+s_to_f32_imm32: 136 -> 3.16649675369263e-08
+s_to_f32_imm1: 136 -> 6.80000000000000e+01
+s_to_f32_imm32: 137 -> 3.18977981805801e-08
+s_to_f32_imm1: 137 -> 6.85000000000000e+01
+s_to_f32_imm32: 138 -> 3.21306288242340e-08
+s_to_f32_imm1: 138 -> 6.90000000000000e+01
+s_to_f32_imm32: 139 -> 3.23634594678879e-08
+s_to_f32_imm1: 139 -> 6.95000000000000e+01
+s_to_f32_imm32: 140 -> 3.25962901115417e-08
+s_to_f32_imm1: 140 -> 7.00000000000000e+01
+s_to_f32_imm32: 141 -> 3.28291207551956e-08
+s_to_f32_imm1: 141 -> 7.05000000000000e+01
+s_to_f32_imm32: 142 -> 3.30619513988495e-08
+s_to_f32_imm1: 142 -> 7.10000000000000e+01
+s_to_f32_imm32: 143 -> 3.32947820425034e-08
+s_to_f32_imm1: 143 -> 7.15000000000000e+01
+s_to_f32_imm32: 144 -> 3.35276126861572e-08
+s_to_f32_imm1: 144 -> 7.20000000000000e+01
+s_to_f32_imm32: 145 -> 3.37604433298111e-08
+s_to_f32_imm1: 145 -> 7.25000000000000e+01
+s_to_f32_imm32: 146 -> 3.39932739734650e-08
+s_to_f32_imm1: 146 -> 7.30000000000000e+01
+s_to_f32_imm32: 147 -> 3.42261046171188e-08
+s_to_f32_imm1: 147 -> 7.35000000000000e+01
+s_to_f32_imm32: 148 -> 3.44589352607727e-08
+s_to_f32_imm1: 148 -> 7.40000000000000e+01
+s_to_f32_imm32: 149 -> 3.46917659044266e-08
+s_to_f32_imm1: 149 -> 7.45000000000000e+01
+s_to_f32_imm32: 150 -> 3.49245965480804e-08
+s_to_f32_imm1: 150 -> 7.50000000000000e+01
+s_to_f32_imm32: 151 -> 3.51574271917343e-08
+s_to_f32_imm1: 151 -> 7.55000000000000e+01
+s_to_f32_imm32: 152 -> 3.53902578353882e-08
+s_to_f32_imm1: 152 -> 7.60000000000000e+01
+s_to_f32_imm32: 153 -> 3.56230884790421e-08
+s_to_f32_imm1: 153 -> 7.65000000000000e+01
+s_to_f32_imm32: 154 -> 3.58559191226959e-08
+s_to_f32_imm1: 154 -> 7.70000000000000e+01
+s_to_f32_imm32: 155 -> 3.60887497663498e-08
+s_to_f32_imm1: 155 -> 7.75000000000000e+01
+s_to_f32_imm32: 156 -> 3.63215804100037e-08
+s_to_f32_imm1: 156 -> 7.80000000000000e+01
+s_to_f32_imm32: 157 -> 3.65544110536575e-08
+s_to_f32_imm1: 157 -> 7.85000000000000e+01
+s_to_f32_imm32: 158 -> 3.67872416973114e-08
+s_to_f32_imm1: 158 -> 7.90000000000000e+01
+s_to_f32_imm32: 159 -> 3.70200723409653e-08
+s_to_f32_imm1: 159 -> 7.95000000000000e+01
+s_to_f32_imm32: 160 -> 3.72529029846191e-08
+s_to_f32_imm1: 160 -> 8.00000000000000e+01
+s_to_f32_imm32: 161 -> 3.74857336282730e-08
+s_to_f32_imm1: 161 -> 8.05000000000000e+01
+s_to_f32_imm32: 162 -> 3.77185642719269e-08
+s_to_f32_imm1: 162 -> 8.10000000000000e+01
+s_to_f32_imm32: 163 -> 3.79513949155807e-08
+s_to_f32_imm1: 163 -> 8.15000000000000e+01
+s_to_f32_imm32: 164 -> 3.81842255592346e-08
+s_to_f32_imm1: 164 -> 8.20000000000000e+01
+s_to_f32_imm32: 165 -> 3.84170562028885e-08
+s_to_f32_imm1: 165 -> 8.25000000000000e+01
+s_to_f32_imm32: 166 -> 3.86498868465424e-08
+s_to_f32_imm1: 166 -> 8.30000000000000e+01
+s_to_f32_imm32: 167 -> 3.88827174901962e-08
+s_to_f32_imm1: 167 -> 8.35000000000000e+01
+s_to_f32_imm32: 168 -> 3.91155481338501e-08
+s_to_f32_imm1: 168 -> 8.40000000000000e+01
+s_to_f32_imm32: 169 -> 3.93483787775040e-08
+s_to_f32_imm1: 169 -> 8.45000000000000e+01
+s_to_f32_imm32: 170 -> 3.95812094211578e-08
+s_to_f32_imm1: 170 -> 8.50000000000000e+01
+s_to_f32_imm32: 171 -> 3.98140400648117e-08
+s_to_f32_imm1: 171 -> 8.55000000000000e+01
+s_to_f32_imm32: 172 -> 4.00468707084656e-08
+s_to_f32_imm1: 172 -> 8.60000000000000e+01
+s_to_f32_imm32: 173 -> 4.02797013521194e-08
+s_to_f32_imm1: 173 -> 8.65000000000000e+01
+s_to_f32_imm32: 174 -> 4.05125319957733e-08
+s_to_f32_imm1: 174 -> 8.70000000000000e+01
+s_to_f32_imm32: 175 -> 4.07453626394272e-08
+s_to_f32_imm1: 175 -> 8.75000000000000e+01
+s_to_f32_imm32: 176 -> 4.09781932830811e-08
+s_to_f32_imm1: 176 -> 8.80000000000000e+01
+s_to_f32_imm32: 177 -> 4.12110239267349e-08
+s_to_f32_imm1: 177 -> 8.85000000000000e+01
+s_to_f32_imm32: 178 -> 4.14438545703888e-08
+s_to_f32_imm1: 178 -> 8.90000000000000e+01
+s_to_f32_imm32: 179 -> 4.16766852140427e-08
+s_to_f32_imm1: 179 -> 8.95000000000000e+01
+s_to_f32_imm32: 180 -> 4.19095158576965e-08
+s_to_f32_imm1: 180 -> 9.00000000000000e+01
+s_to_f32_imm32: 181 -> 4.21423465013504e-08
+s_to_f32_imm1: 181 -> 9.05000000000000e+01
+s_to_f32_imm32: 182 -> 4.23751771450043e-08
+s_to_f32_imm1: 182 -> 9.10000000000000e+01
+s_to_f32_imm32: 183 -> 4.26080077886581e-08
+s_to_f32_imm1: 183 -> 9.15000000000000e+01
+s_to_f32_imm32: 184 -> 4.28408384323120e-08
+s_to_f32_imm1: 184 -> 9.20000000000000e+01
+s_to_f32_imm32: 185 -> 4.30736690759659e-08
+s_to_f32_imm1: 185 -> 9.25000000000000e+01
+s_to_f32_imm32: 186 -> 4.33064997196198e-08
+s_to_f32_imm1: 186 -> 9.30000000000000e+01
+s_to_f32_imm32: 187 -> 4.35393303632736e-08
+s_to_f32_imm1: 187 -> 9.35000000000000e+01
+s_to_f32_imm32: 188 -> 4.37721610069275e-08
+s_to_f32_imm1: 188 -> 9.40000000000000e+01
+s_to_f32_imm32: 189 -> 4.40049916505814e-08
+s_to_f32_imm1: 189 -> 9.45000000000000e+01
+s_to_f32_imm32: 190 -> 4.42378222942352e-08
+s_to_f32_imm1: 190 -> 9.50000000000000e+01
+s_to_f32_imm32: 191 -> 4.44706529378891e-08
+s_to_f32_imm1: 191 -> 9.55000000000000e+01
+s_to_f32_imm32: 192 -> 4.47034835815430e-08
+s_to_f32_imm1: 192 -> 9.60000000000000e+01
+s_to_f32_imm32: 193 -> 4.49363142251968e-08
+s_to_f32_imm1: 193 -> 9.65000000000000e+01
+s_to_f32_imm32: 194 -> 4.51691448688507e-08
+s_to_f32_imm1: 194 -> 9.70000000000000e+01
+s_to_f32_imm32: 195 -> 4.54019755125046e-08
+s_to_f32_imm1: 195 -> 9.75000000000000e+01
+s_to_f32_imm32: 196 -> 4.56348061561584e-08
+s_to_f32_imm1: 196 -> 9.80000000000000e+01
+s_to_f32_imm32: 197 -> 4.58676367998123e-08
+s_to_f32_imm1: 197 -> 9.85000000000000e+01
+s_to_f32_imm32: 198 -> 4.61004674434662e-08
+s_to_f32_imm1: 198 -> 9.90000000000000e+01
+s_to_f32_imm32: 199 -> 4.63332980871201e-08
+s_to_f32_imm1: 199 -> 9.95000000000000e+01
+s_to_f32_imm32: 2147483646 -> 5.00000000000000e-01
+s_to_f32_imm1: 2147483646 -> 1.07374182400000e+09
+s_to_f32_imm32: 2147483647 -> 5.00000000000000e-01
+s_to_f32_imm1: 2147483647 -> 1.07374182400000e+09
+s_to_f32_imm32: -2147483648 -> -5.00000000000000e-01
+s_to_f32_imm1: -2147483648 -> -1.07374182400000e+09
+s_to_f32_imm32: -2147483647 -> -5.00000000000000e-01
+s_to_f32_imm1: -2147483647 -> -1.07374182400000e+09
+s_to_f32_imm32: -2 -> -4.65661287307739e-10
+s_to_f32_imm1: -2 -> -1.00000000000000e+00
+s_to_f32_imm32: -1 -> -2.32830643653870e-10
+s_to_f32_imm1: -1 -> -5.00000000000000e-01
+
+u_to_f32_imm32: 0 -> 0.00000000000000e+00
+u_to_f32_imm1: 0 -> 0.00000000000000e+00
+u_to_f32_imm32: 1 -> 2.32830643653870e-10
+u_to_f32_imm1: 1 -> 5.00000000000000e-01
+u_to_f32_imm32: 100 -> 2.32830643653870e-08
+u_to_f32_imm1: 100 -> 5.00000000000000e+01
+u_to_f32_imm32: 101 -> 2.35158950090408e-08
+u_to_f32_imm1: 101 -> 5.05000000000000e+01
+u_to_f32_imm32: 102 -> 2.37487256526947e-08
+u_to_f32_imm1: 102 -> 5.10000000000000e+01
+u_to_f32_imm32: 103 -> 2.39815562963486e-08
+u_to_f32_imm1: 103 -> 5.15000000000000e+01
+u_to_f32_imm32: 104 -> 2.42143869400024e-08
+u_to_f32_imm1: 104 -> 5.20000000000000e+01
+u_to_f32_imm32: 105 -> 2.44472175836563e-08
+u_to_f32_imm1: 105 -> 5.25000000000000e+01
+u_to_f32_imm32: 106 -> 2.46800482273102e-08
+u_to_f32_imm1: 106 -> 5.30000000000000e+01
+u_to_f32_imm32: 107 -> 2.49128788709641e-08
+u_to_f32_imm1: 107 -> 5.35000000000000e+01
+u_to_f32_imm32: 108 -> 2.51457095146179e-08
+u_to_f32_imm1: 108 -> 5.40000000000000e+01
+u_to_f32_imm32: 109 -> 2.53785401582718e-08
+u_to_f32_imm1: 109 -> 5.45000000000000e+01
+u_to_f32_imm32: 110 -> 2.56113708019257e-08
+u_to_f32_imm1: 110 -> 5.50000000000000e+01
+u_to_f32_imm32: 111 -> 2.58442014455795e-08
+u_to_f32_imm1: 111 -> 5.55000000000000e+01
+u_to_f32_imm32: 112 -> 2.60770320892334e-08
+u_to_f32_imm1: 112 -> 5.60000000000000e+01
+u_to_f32_imm32: 113 -> 2.63098627328873e-08
+u_to_f32_imm1: 113 -> 5.65000000000000e+01
+u_to_f32_imm32: 114 -> 2.65426933765411e-08
+u_to_f32_imm1: 114 -> 5.70000000000000e+01
+u_to_f32_imm32: 115 -> 2.67755240201950e-08
+u_to_f32_imm1: 115 -> 5.75000000000000e+01
+u_to_f32_imm32: 116 -> 2.70083546638489e-08
+u_to_f32_imm1: 116 -> 5.80000000000000e+01
+u_to_f32_imm32: 117 -> 2.72411853075027e-08
+u_to_f32_imm1: 117 -> 5.85000000000000e+01
+u_to_f32_imm32: 118 -> 2.74740159511566e-08
+u_to_f32_imm1: 118 -> 5.90000000000000e+01
+u_to_f32_imm32: 119 -> 2.77068465948105e-08
+u_to_f32_imm1: 119 -> 5.95000000000000e+01
+u_to_f32_imm32: 120 -> 2.79396772384644e-08
+u_to_f32_imm1: 120 -> 6.00000000000000e+01
+u_to_f32_imm32: 121 -> 2.81725078821182e-08
+u_to_f32_imm1: 121 -> 6.05000000000000e+01
+u_to_f32_imm32: 122 -> 2.84053385257721e-08
+u_to_f32_imm1: 122 -> 6.10000000000000e+01
+u_to_f32_imm32: 123 -> 2.86381691694260e-08
+u_to_f32_imm1: 123 -> 6.15000000000000e+01
+u_to_f32_imm32: 124 -> 2.88709998130798e-08
+u_to_f32_imm1: 124 -> 6.20000000000000e+01
+u_to_f32_imm32: 125 -> 2.91038304567337e-08
+u_to_f32_imm1: 125 -> 6.25000000000000e+01
+u_to_f32_imm32: 126 -> 2.93366611003876e-08
+u_to_f32_imm1: 126 -> 6.30000000000000e+01
+u_to_f32_imm32: 127 -> 2.95694917440414e-08
+u_to_f32_imm1: 127 -> 6.35000000000000e+01
+u_to_f32_imm32: 128 -> 2.98023223876953e-08
+u_to_f32_imm1: 128 -> 6.40000000000000e+01
+u_to_f32_imm32: 129 -> 3.00351530313492e-08
+u_to_f32_imm1: 129 -> 6.45000000000000e+01
+u_to_f32_imm32: 130 -> 3.02679836750031e-08
+u_to_f32_imm1: 130 -> 6.50000000000000e+01
+u_to_f32_imm32: 131 -> 3.05008143186569e-08
+u_to_f32_imm1: 131 -> 6.55000000000000e+01
+u_to_f32_imm32: 132 -> 3.07336449623108e-08
+u_to_f32_imm1: 132 -> 6.60000000000000e+01
+u_to_f32_imm32: 133 -> 3.09664756059647e-08
+u_to_f32_imm1: 133 -> 6.65000000000000e+01
+u_to_f32_imm32: 134 -> 3.11993062496185e-08
+u_to_f32_imm1: 134 -> 6.70000000000000e+01
+u_to_f32_imm32: 135 -> 3.14321368932724e-08
+u_to_f32_imm1: 135 -> 6.75000000000000e+01
+u_to_f32_imm32: 136 -> 3.16649675369263e-08
+u_to_f32_imm1: 136 -> 6.80000000000000e+01
+u_to_f32_imm32: 137 -> 3.18977981805801e-08
+u_to_f32_imm1: 137 -> 6.85000000000000e+01
+u_to_f32_imm32: 138 -> 3.21306288242340e-08
+u_to_f32_imm1: 138 -> 6.90000000000000e+01
+u_to_f32_imm32: 139 -> 3.23634594678879e-08
+u_to_f32_imm1: 139 -> 6.95000000000000e+01
+u_to_f32_imm32: 140 -> 3.25962901115417e-08
+u_to_f32_imm1: 140 -> 7.00000000000000e+01
+u_to_f32_imm32: 141 -> 3.28291207551956e-08
+u_to_f32_imm1: 141 -> 7.05000000000000e+01
+u_to_f32_imm32: 142 -> 3.30619513988495e-08
+u_to_f32_imm1: 142 -> 7.10000000000000e+01
+u_to_f32_imm32: 143 -> 3.32947820425034e-08
+u_to_f32_imm1: 143 -> 7.15000000000000e+01
+u_to_f32_imm32: 144 -> 3.35276126861572e-08
+u_to_f32_imm1: 144 -> 7.20000000000000e+01
+u_to_f32_imm32: 145 -> 3.37604433298111e-08
+u_to_f32_imm1: 145 -> 7.25000000000000e+01
+u_to_f32_imm32: 146 -> 3.39932739734650e-08
+u_to_f32_imm1: 146 -> 7.30000000000000e+01
+u_to_f32_imm32: 147 -> 3.42261046171188e-08
+u_to_f32_imm1: 147 -> 7.35000000000000e+01
+u_to_f32_imm32: 148 -> 3.44589352607727e-08
+u_to_f32_imm1: 148 -> 7.40000000000000e+01
+u_to_f32_imm32: 149 -> 3.46917659044266e-08
+u_to_f32_imm1: 149 -> 7.45000000000000e+01
+u_to_f32_imm32: 150 -> 3.49245965480804e-08
+u_to_f32_imm1: 150 -> 7.50000000000000e+01
+u_to_f32_imm32: 151 -> 3.51574271917343e-08
+u_to_f32_imm1: 151 -> 7.55000000000000e+01
+u_to_f32_imm32: 152 -> 3.53902578353882e-08
+u_to_f32_imm1: 152 -> 7.60000000000000e+01
+u_to_f32_imm32: 153 -> 3.56230884790421e-08
+u_to_f32_imm1: 153 -> 7.65000000000000e+01
+u_to_f32_imm32: 154 -> 3.58559191226959e-08
+u_to_f32_imm1: 154 -> 7.70000000000000e+01
+u_to_f32_imm32: 155 -> 3.60887497663498e-08
+u_to_f32_imm1: 155 -> 7.75000000000000e+01
+u_to_f32_imm32: 156 -> 3.63215804100037e-08
+u_to_f32_imm1: 156 -> 7.80000000000000e+01
+u_to_f32_imm32: 157 -> 3.65544110536575e-08
+u_to_f32_imm1: 157 -> 7.85000000000000e+01
+u_to_f32_imm32: 158 -> 3.67872416973114e-08
+u_to_f32_imm1: 158 -> 7.90000000000000e+01
+u_to_f32_imm32: 159 -> 3.70200723409653e-08
+u_to_f32_imm1: 159 -> 7.95000000000000e+01
+u_to_f32_imm32: 160 -> 3.72529029846191e-08
+u_to_f32_imm1: 160 -> 8.00000000000000e+01
+u_to_f32_imm32: 161 -> 3.74857336282730e-08
+u_to_f32_imm1: 161 -> 8.05000000000000e+01
+u_to_f32_imm32: 162 -> 3.77185642719269e-08
+u_to_f32_imm1: 162 -> 8.10000000000000e+01
+u_to_f32_imm32: 163 -> 3.79513949155807e-08
+u_to_f32_imm1: 163 -> 8.15000000000000e+01
+u_to_f32_imm32: 164 -> 3.81842255592346e-08
+u_to_f32_imm1: 164 -> 8.20000000000000e+01
+u_to_f32_imm32: 165 -> 3.84170562028885e-08
+u_to_f32_imm1: 165 -> 8.25000000000000e+01
+u_to_f32_imm32: 166 -> 3.86498868465424e-08
+u_to_f32_imm1: 166 -> 8.30000000000000e+01
+u_to_f32_imm32: 167 -> 3.88827174901962e-08
+u_to_f32_imm1: 167 -> 8.35000000000000e+01
+u_to_f32_imm32: 168 -> 3.91155481338501e-08
+u_to_f32_imm1: 168 -> 8.40000000000000e+01
+u_to_f32_imm32: 169 -> 3.93483787775040e-08
+u_to_f32_imm1: 169 -> 8.45000000000000e+01
+u_to_f32_imm32: 170 -> 3.95812094211578e-08
+u_to_f32_imm1: 170 -> 8.50000000000000e+01
+u_to_f32_imm32: 171 -> 3.98140400648117e-08
+u_to_f32_imm1: 171 -> 8.55000000000000e+01
+u_to_f32_imm32: 172 -> 4.00468707084656e-08
+u_to_f32_imm1: 172 -> 8.60000000000000e+01
+u_to_f32_imm32: 173 -> 4.02797013521194e-08
+u_to_f32_imm1: 173 -> 8.65000000000000e+01
+u_to_f32_imm32: 174 -> 4.05125319957733e-08
+u_to_f32_imm1: 174 -> 8.70000000000000e+01
+u_to_f32_imm32: 175 -> 4.07453626394272e-08
+u_to_f32_imm1: 175 -> 8.75000000000000e+01
+u_to_f32_imm32: 176 -> 4.09781932830811e-08
+u_to_f32_imm1: 176 -> 8.80000000000000e+01
+u_to_f32_imm32: 177 -> 4.12110239267349e-08
+u_to_f32_imm1: 177 -> 8.85000000000000e+01
+u_to_f32_imm32: 178 -> 4.14438545703888e-08
+u_to_f32_imm1: 178 -> 8.90000000000000e+01
+u_to_f32_imm32: 179 -> 4.16766852140427e-08
+u_to_f32_imm1: 179 -> 8.95000000000000e+01
+u_to_f32_imm32: 180 -> 4.19095158576965e-08
+u_to_f32_imm1: 180 -> 9.00000000000000e+01
+u_to_f32_imm32: 181 -> 4.21423465013504e-08
+u_to_f32_imm1: 181 -> 9.05000000000000e+01
+u_to_f32_imm32: 182 -> 4.23751771450043e-08
+u_to_f32_imm1: 182 -> 9.10000000000000e+01
+u_to_f32_imm32: 183 -> 4.26080077886581e-08
+u_to_f32_imm1: 183 -> 9.15000000000000e+01
+u_to_f32_imm32: 184 -> 4.28408384323120e-08
+u_to_f32_imm1: 184 -> 9.20000000000000e+01
+u_to_f32_imm32: 185 -> 4.30736690759659e-08
+u_to_f32_imm1: 185 -> 9.25000000000000e+01
+u_to_f32_imm32: 186 -> 4.33064997196198e-08
+u_to_f32_imm1: 186 -> 9.30000000000000e+01
+u_to_f32_imm32: 187 -> 4.35393303632736e-08
+u_to_f32_imm1: 187 -> 9.35000000000000e+01
+u_to_f32_imm32: 188 -> 4.37721610069275e-08
+u_to_f32_imm1: 188 -> 9.40000000000000e+01
+u_to_f32_imm32: 189 -> 4.40049916505814e-08
+u_to_f32_imm1: 189 -> 9.45000000000000e+01
+u_to_f32_imm32: 190 -> 4.42378222942352e-08
+u_to_f32_imm1: 190 -> 9.50000000000000e+01
+u_to_f32_imm32: 191 -> 4.44706529378891e-08
+u_to_f32_imm1: 191 -> 9.55000000000000e+01
+u_to_f32_imm32: 192 -> 4.47034835815430e-08
+u_to_f32_imm1: 192 -> 9.60000000000000e+01
+u_to_f32_imm32: 193 -> 4.49363142251968e-08
+u_to_f32_imm1: 193 -> 9.65000000000000e+01
+u_to_f32_imm32: 194 -> 4.51691448688507e-08
+u_to_f32_imm1: 194 -> 9.70000000000000e+01
+u_to_f32_imm32: 195 -> 4.54019755125046e-08
+u_to_f32_imm1: 195 -> 9.75000000000000e+01
+u_to_f32_imm32: 196 -> 4.56348061561584e-08
+u_to_f32_imm1: 196 -> 9.80000000000000e+01
+u_to_f32_imm32: 197 -> 4.58676367998123e-08
+u_to_f32_imm1: 197 -> 9.85000000000000e+01
+u_to_f32_imm32: 198 -> 4.61004674434662e-08
+u_to_f32_imm1: 198 -> 9.90000000000000e+01
+u_to_f32_imm32: 199 -> 4.63332980871201e-08
+u_to_f32_imm1: 199 -> 9.95000000000000e+01
+u_to_f32_imm32: 2147483646 -> 5.00000000000000e-01
+u_to_f32_imm1: 2147483646 -> 1.07374182400000e+09
+u_to_f32_imm32: 2147483647 -> 5.00000000000000e-01
+u_to_f32_imm1: 2147483647 -> 1.07374182400000e+09
+u_to_f32_imm32: 2147483648 -> 5.00000000000000e-01
+u_to_f32_imm1: 2147483648 -> 1.07374182400000e+09
+u_to_f32_imm32: 2147483649 -> 5.00000000000000e-01
+u_to_f32_imm1: 2147483649 -> 1.07374182400000e+09
+u_to_f32_imm32: 4294967294 -> 1.00000000000000e+00
+u_to_f32_imm1: 4294967294 -> 2.14748364800000e+09
+u_to_f32_imm32: 4294967295 -> 1.00000000000000e+00
+u_to_f32_imm1: 4294967295 -> 2.14748364800000e+09
diff --git a/main/none/tests/arm/vcvt_fixed_float_VFP.vgtest b/main/none/tests/arm/vcvt_fixed_float_VFP.vgtest
new file mode 100644
index 0000000..8490d60
--- /dev/null
+++ b/main/none/tests/arm/vcvt_fixed_float_VFP.vgtest
@@ -0,0 +1,2 @@
+prog: vcvt_fixed_float_VFP
+vgopts: -q
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/arm/vfp.stderr.exp
similarity index 100%
rename from main/none/tests/arm/v6int.stderr.exp
rename to main/none/tests/arm/vfp.stderr.exp
diff --git a/main/none/tests/arm/vfp.stdout.exp b/main/none/tests/arm/vfp.stdout.exp
index 1f6be32..c1530bb 100644
--- a/main/none/tests/arm/vfp.stdout.exp
+++ b/main/none/tests/arm/vfp.stdout.exp
@@ -169,22 +169,22 @@
vnmla.f64 d0, d5, d2 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000
vnmla.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000
vnmla.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000
-vnmla.f64 d20, d25, d22 :: Qd 0x409067a4 0x842fc4c9 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b
-vnmla.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f5b9999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000
-vnmla.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2ac68f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d
-vnmla.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf7191999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000
-vnmla.f64 d30, d15, d2 :: Qd 0xc20524a9 0x817fcbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148
-vnmla.f64 d23, d24, d5 :: Qd 0xc0df8bff 0x7ffffe04 Qm 0x40380000 00000000 Qn 0x40950800 00000000
-vnmla.f64 d10, d11, d2 :: Qd 0xc1895139 0x97f00000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000
-vnmla.f64 d29, d15, d7 :: Qd 0xc1b65928 0xd5fe0000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000
-vnmla.f64 d30, d11, d12 :: Qd 0xc1df20a6 0xd7bc2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa
-vnmla.f64 d27, d21, d6 :: Qd 0xbfb363ef 0x37b9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd
-vnmla.f64 d30, d31, d2 :: Qd 0xc111fc57 0xf7ffffe0 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000
-vnmla.f64 d13, d24, d5 :: Qd 0xc132771c 0x6466665e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666
-vnmla.f64 d10, d11, d2 :: Qd 0xc0e9f35f 0x34bc6981 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000
+vnmla.f64 d20, d25, d22 :: Qd 0x40906794 0x842f8549 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b
+vnmla.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f579999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000
+vnmla.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2abe8f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d
+vnmla.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf71a1999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000
+vnmla.f64 d30, d15, d2 :: Qd 0xc20524a9 0x817febf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148
+vnmla.f64 d23, d24, d5 :: Qd 0xc0df8c00 0x800001fc Qm 0x40380000 00000000 Qn 0x40950800 00000000
+vnmla.f64 d10, d11, d2 :: Qd 0xc1895139 0x98100000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000
+vnmla.f64 d29, d15, d7 :: Qd 0xc1b65928 0xd6020000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000
+vnmla.f64 d30, d11, d12 :: Qd 0xc1df20a6 0xd7bd2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa
+vnmla.f64 d27, d21, d6 :: Qd 0xbfb763ef 0x4799be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd
+vnmla.f64 d30, d31, d2 :: Qd 0xc111fc58 0x08000020 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000
+vnmla.f64 d13, d24, d5 :: Qd 0xc132771c 0x6866666e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666
+vnmla.f64 d10, d11, d2 :: Qd 0xc0e9f35f 0xb4bc6b7d Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000
vnmla.f64 d29, d25, d7 :: Qd 0x7ff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000
vnmla.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f
-vnmla.f64 d27, d21, d16 :: Qd 0x40aa004b 0x17cc0c5d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847
+vnmla.f64 d27, d21, d16 :: Qd 0x40aa0043 0x17cbec9d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847
vnmla.f64 d0, d5, d2 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000
vnmla.f64 d20, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000
vnmla.f64 d10, d23, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000
@@ -213,103 +213,103 @@
vnmla.f32 s20, s13, s15 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
vnmla.f32 s10, s23, s15 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
---- VMLS (fp) ----
-vmls.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000
-vmls.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000
-vmls.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000
-vmls.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000
-vmls.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000
-vmls.f64 d20, d25, d22 :: Qd 0xc09067a4 0x842fc4c9 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b
-vmls.f64 d23, d24, d25 :: Qd 0xc1bbe864 0x1f5b9999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000
-vmls.f64 d20, d31, d12 :: Qd 0xc1e0a1cf 0xd2ac68f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d
-vmls.f64 d19, d25, d27 :: Qd 0x41d860c7 0xf7191999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000
-vmls.f64 d30, d15, d2 :: Qd 0x420524a9 0x817fcbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148
-vmls.f64 d23, d24, d5 :: Qd 0x40df8bff 0x7ffffe04 Qm 0x40380000 00000000 Qn 0x40950800 00000000
-vmls.f64 d10, d11, d2 :: Qd 0x41895139 0x97f00000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000
-vmls.f64 d29, d15, d7 :: Qd 0x41b65928 0xd5fe0000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000
-vmls.f64 d30, d11, d12 :: Qd 0x41df20a6 0xd7bc2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa
-vmls.f64 d27, d21, d6 :: Qd 0x3fb363ef 0x37b9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd
-vmls.f64 d30, d31, d2 :: Qd 0x4111fc57 0xf7ffffe0 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000
-vmls.f64 d13, d24, d5 :: Qd 0x4132771c 0x6466665e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666
-vmls.f64 d10, d11, d2 :: Qd 0x40e9f35f 0x34bc6981 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000
-vmls.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000
-vmls.f64 d0, d11, d12 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f
-vmls.f64 d27, d21, d16 :: Qd 0xc0aa004b 0x17cc0c5d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847
-vmls.f64 d0, d5, d2 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000
-vmls.f64 d20, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000
-vmls.f64 d10, d23, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000
-vmls.f32 s0, s11, s12 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000
-vmls.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
-vmls.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000
-vmls.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
-vmls.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
-vmls.f32 s20, s25, s22 :: Sd 0xc4833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659
-vmls.f32 s23, s24, s25 :: Sd 0xcddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000
-vmls.f32 s20, s31, s12 :: Sd 0xcf050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a
-vmls.f32 s19, s25, s27 :: Sd 0x4ec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200
-vmls.f32 s30, s15, s2 :: Sd 0x5029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1
-vmls.f32 s23, s24, s5 :: Sd 0x46fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000
-vmls.f32 s10, s11, s2 :: Sd 0x4c4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000
-vmls.f32 s29, s15, s7 :: Sd 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008
-vmls.f32 s30, s11, s12 :: Sd 0x4ef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812
-vmls.f32 s27, s21, s6 :: Sd 0x3dab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02
-vmls.f32 s30, s31, s2 :: Sd 0x488fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000
-vmls.f32 s13, s24, s5 :: Sd 0x4993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333
-vmls.f32 s10, s11, s2 :: Sd 0x474f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000
-vmls.f32 s29, s25, s7 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
-vmls.f32 s0, s11, s12 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3
-vmls.f32 s27, s21, s16 :: Sd 0xc5500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19
-vmls.f32 s0, s5, s2 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xff800000
-vmls.f32 s20, s13, s15 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
-vmls.f32 s10, s23, s15 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
+vmls.f64 d0, d11, d12 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000
+vmls.f64 d7, d1, d6 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000
+vmls.f64 d0, d5, d2 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000
+vmls.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000
+vmls.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000
+vmls.f64 d20, d25, d22 :: Qd 0x409067a4 0x842fc4c9 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b
+vmls.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f5b9999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000
+vmls.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2ac68f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d
+vmls.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf7191999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000
+vmls.f64 d30, d15, d2 :: Qd 0xc20524a9 0x817fcbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148
+vmls.f64 d23, d24, d5 :: Qd 0xc0df8bff 0x7ffffe04 Qm 0x40380000 00000000 Qn 0x40950800 00000000
+vmls.f64 d10, d11, d2 :: Qd 0xc1895139 0x97f00000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000
+vmls.f64 d29, d15, d7 :: Qd 0xc1b65928 0xd5fe0000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000
+vmls.f64 d30, d11, d12 :: Qd 0xc1df20a6 0xd7bc2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa
+vmls.f64 d27, d21, d6 :: Qd 0xbfb363ef 0x37b9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd
+vmls.f64 d30, d31, d2 :: Qd 0xc111fc57 0xf7ffffe0 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000
+vmls.f64 d13, d24, d5 :: Qd 0xc132771c 0x6466665e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666
+vmls.f64 d10, d11, d2 :: Qd 0xc0e9f35f 0x34bc6981 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000
+vmls.f64 d29, d25, d7 :: Qd 0x7ff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000
+vmls.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f
+vmls.f64 d27, d21, d16 :: Qd 0x40aa004b 0x17cc0c5d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847
+vmls.f64 d0, d5, d2 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000
+vmls.f64 d20, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000
+vmls.f64 d10, d23, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000
+vmls.f32 s0, s11, s12 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000
+vmls.f32 s7, s1, s6 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
+vmls.f32 s0, s5, s2 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000
+vmls.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
+vmls.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
+vmls.f32 s20, s25, s22 :: Sd 0x44833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659
+vmls.f32 s23, s24, s25 :: Sd 0x4ddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000
+vmls.f32 s20, s31, s12 :: Sd 0x4f050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a
+vmls.f32 s19, s25, s27 :: Sd 0xcec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200
+vmls.f32 s30, s15, s2 :: Sd 0xd029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1
+vmls.f32 s23, s24, s5 :: Sd 0xc6fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000
+vmls.f32 s10, s11, s2 :: Sd 0xcc4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000
+vmls.f32 s29, s15, s7 :: Sd 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008
+vmls.f32 s30, s11, s12 :: Sd 0xcef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812
+vmls.f32 s27, s21, s6 :: Sd 0xbdab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02
+vmls.f32 s30, s31, s2 :: Sd 0xc88fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000
+vmls.f32 s13, s24, s5 :: Sd 0xc993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333
+vmls.f32 s10, s11, s2 :: Sd 0xc74f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000
+vmls.f32 s29, s25, s7 :: Sd 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
+vmls.f32 s0, s11, s12 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3
+vmls.f32 s27, s21, s16 :: Sd 0x45500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19
+vmls.f32 s0, s5, s2 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xff800000
+vmls.f32 s20, s13, s15 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
+vmls.f32 s10, s23, s15 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
---- VNMLS (fp) ----
-vnmls.f64 d0, d11, d12 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000
-vnmls.f64 d7, d1, d6 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000
-vnmls.f64 d0, d5, d2 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000
-vnmls.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000
-vnmls.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000
-vnmls.f64 d20, d25, d22 :: Qd 0x40906794 0x842f8549 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b
-vnmls.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f579999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000
-vnmls.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2abe8f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d
-vnmls.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf71a1999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000
-vnmls.f64 d30, d15, d2 :: Qd 0xc20524a9 0x817febf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148
-vnmls.f64 d23, d24, d5 :: Qd 0xc0df8c00 0x800001fc Qm 0x40380000 00000000 Qn 0x40950800 00000000
-vnmls.f64 d10, d11, d2 :: Qd 0xc1895139 0x98100000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000
-vnmls.f64 d29, d15, d7 :: Qd 0xc1b65928 0xd6020000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000
-vnmls.f64 d30, d11, d12 :: Qd 0xc1df20a6 0xd7bd2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa
-vnmls.f64 d27, d21, d6 :: Qd 0xbfb763ef 0x4799be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd
-vnmls.f64 d30, d31, d2 :: Qd 0xc111fc58 0x08000020 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000
-vnmls.f64 d13, d24, d5 :: Qd 0xc132771c 0x6866666e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666
-vnmls.f64 d10, d11, d2 :: Qd 0xc0e9f35f 0xb4bc6b7d Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000
-vnmls.f64 d29, d25, d7 :: Qd 0x7ff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000
-vnmls.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f
-vnmls.f64 d27, d21, d16 :: Qd 0x40aa0043 0x17cbec9d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847
-vnmls.f64 d0, d5, d2 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000
-vnmls.f64 d20, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000
-vnmls.f64 d10, d23, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000
-vnmls.f32 s0, s11, s12 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000
-vnmls.f32 s7, s1, s6 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
-vnmls.f32 s0, s5, s2 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000
-vnmls.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
-vnmls.f32 s10, s13, s15 :: Sd 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
-vnmls.f32 s20, s25, s22 :: Sd 0x44833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659
-vnmls.f32 s23, s24, s25 :: Sd 0x4ddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000
-vnmls.f32 s20, s31, s12 :: Sd 0x4f050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a
-vnmls.f32 s19, s25, s27 :: Sd 0xcec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200
-vnmls.f32 s30, s15, s2 :: Sd 0xd029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1
-vnmls.f32 s23, s24, s5 :: Sd 0xc6fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000
-vnmls.f32 s10, s11, s2 :: Sd 0xcc4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000
-vnmls.f32 s29, s15, s7 :: Sd 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008
-vnmls.f32 s30, s11, s12 :: Sd 0xcef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812
-vnmls.f32 s27, s21, s6 :: Sd 0xbdab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02
-vnmls.f32 s30, s31, s2 :: Sd 0xc88fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000
-vnmls.f32 s13, s24, s5 :: Sd 0xc993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333
-vnmls.f32 s10, s11, s2 :: Sd 0xc74f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000
-vnmls.f32 s29, s25, s7 :: Sd 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
-vnmls.f32 s0, s11, s12 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3
-vnmls.f32 s27, s21, s16 :: Sd 0x45500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19
-vnmls.f32 s0, s5, s2 :: Sd 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xff800000
-vnmls.f32 s20, s13, s15 :: Sd 0xffc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
-vnmls.f32 s10, s23, s15 :: Sd 0xffc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
+vnmls.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000
+vnmls.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000
+vnmls.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000
+vnmls.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000
+vnmls.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000
+vnmls.f64 d20, d25, d22 :: Qd 0xc09067a4 0x842fc4c9 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b
+vnmls.f64 d23, d24, d25 :: Qd 0xc1bbe864 0x1f5b9999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000
+vnmls.f64 d20, d31, d12 :: Qd 0xc1e0a1cf 0xd2ac68f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d
+vnmls.f64 d19, d25, d27 :: Qd 0x41d860c7 0xf7191999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000
+vnmls.f64 d30, d15, d2 :: Qd 0x420524a9 0x817fcbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148
+vnmls.f64 d23, d24, d5 :: Qd 0x40df8bff 0x7ffffe04 Qm 0x40380000 00000000 Qn 0x40950800 00000000
+vnmls.f64 d10, d11, d2 :: Qd 0x41895139 0x97f00000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000
+vnmls.f64 d29, d15, d7 :: Qd 0x41b65928 0xd5fe0000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000
+vnmls.f64 d30, d11, d12 :: Qd 0x41df20a6 0xd7bc2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa
+vnmls.f64 d27, d21, d6 :: Qd 0x3fb363ef 0x37b9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd
+vnmls.f64 d30, d31, d2 :: Qd 0x4111fc57 0xf7ffffe0 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000
+vnmls.f64 d13, d24, d5 :: Qd 0x4132771c 0x6466665e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666
+vnmls.f64 d10, d11, d2 :: Qd 0x40e9f35f 0x34bc6981 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000
+vnmls.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000
+vnmls.f64 d0, d11, d12 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f
+vnmls.f64 d27, d21, d16 :: Qd 0xc0aa004b 0x17cc0c5d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847
+vnmls.f64 d0, d5, d2 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000
+vnmls.f64 d20, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000
+vnmls.f64 d10, d23, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000
+vnmls.f32 s0, s11, s12 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000
+vnmls.f32 s7, s1, s6 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000
+vnmls.f32 s0, s5, s2 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000
+vnmls.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000
+vnmls.f32 s10, s13, s15 :: Sd 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000
+vnmls.f32 s20, s25, s22 :: Sd 0xc4833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659
+vnmls.f32 s23, s24, s25 :: Sd 0xcddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000
+vnmls.f32 s20, s31, s12 :: Sd 0xcf050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a
+vnmls.f32 s19, s25, s27 :: Sd 0x4ec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200
+vnmls.f32 s30, s15, s2 :: Sd 0x5029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1
+vnmls.f32 s23, s24, s5 :: Sd 0x46fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000
+vnmls.f32 s10, s11, s2 :: Sd 0x4c4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000
+vnmls.f32 s29, s15, s7 :: Sd 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008
+vnmls.f32 s30, s11, s12 :: Sd 0x4ef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812
+vnmls.f32 s27, s21, s6 :: Sd 0x3dab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02
+vnmls.f32 s30, s31, s2 :: Sd 0x488fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000
+vnmls.f32 s13, s24, s5 :: Sd 0x4993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333
+vnmls.f32 s10, s11, s2 :: Sd 0x474f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000
+vnmls.f32 s29, s25, s7 :: Sd 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000
+vnmls.f32 s0, s11, s12 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3
+vnmls.f32 s27, s21, s16 :: Sd 0xc5500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19
+vnmls.f32 s0, s5, s2 :: Sd 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xff800000
+vnmls.f32 s20, s13, s15 :: Sd 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000
+vnmls.f32 s10, s23, s15 :: Sd 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000
---- VMUL (fp) ----
vmul.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000
vmul.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000
@@ -635,7 +635,7 @@
vcvt.u32.f32 s15, s4 :: Sd 0xb2d05e00 Sm (i32)0x4f32d05e
vcvt.u32.f32 s25, s24 :: Sd 0x00000000 Sm (i32)0xbf000000
vcvt.u32.f32 s19, s21 :: Sd 0x00000000 Sm (i32)0xc0e33333
-vcvt.u32.f32 s12, s8 :: Sd 0x00000008 Sm (i32)0x40fff800
+vcvt.u32.f32 s12, s8 :: Sd 0x00000007 Sm (i32)0x40fff800
vcvt.u32.f32 s12, s18 :: Sd 0x00000000 Sm (i32)0xc0fff800
vcvt.u32.f32 s30, s1 :: Sd 0x00000000 Sm (i32)0x00000000
vcvt.u32.f32 s11, s1 :: Sd 0xffffffff Sm (i32)0x7f800000
@@ -650,8 +650,8 @@
vcvt.s32.f32 s15, s14 :: Sd 0x7fffffff Sm (i32)0x4f32d05e
vcvt.s32.f32 s15, s24 :: Sd 0x00000000 Sm (i32)0xbf000000
vcvt.s32.f32 s15, s29 :: Sd 0xfffffff9 Sm (i32)0xc0e33333
-vcvt.s32.f32 s12, s31 :: Sd 0x00000008 Sm (i32)0x40fff800
-vcvt.s32.f32 s1, s8 :: Sd 0xfffffff8 Sm (i32)0xc0fff800
+vcvt.s32.f32 s12, s31 :: Sd 0x00000007 Sm (i32)0x40fff800
+vcvt.s32.f32 s1, s8 :: Sd 0xfffffff9 Sm (i32)0xc0fff800
vcvt.f32.u32 s30, s1 :: Sd 0x4e81c000 Sm (i32)0x40e00000
vcvt.f32.u32 s10, s17 :: Sd 0x4f4f0000 Sm (i32)0xcf000000
vcvt.f32.u32 s20, s1 :: Sd 0x4e9e0000 Sm (i32)0x4f000000
@@ -670,21 +670,21 @@
vcvt.f32.s32 s0, s17 :: Sd 0x4eff0000 Sm (i32)0x7f800000
vcvt.f32.s32 s0, s1 :: Sd 0xcb000000 Sm (i32)0xff800000
vcvt.u32.f64 s0, d1 :: Sd 0x00000003 Dm 0x40099999 9999999a
-vcvt.u32.f64 s13, d26 :: Sd 0x000000eb Dm 0x406d5147 ae147ae1
+vcvt.u32.f64 s13, d26 :: Sd 0x000000ea Dm 0x406d5147 ae147ae1
vcvt.u32.f64 s29, d30 :: Sd 0x0000b4a5 Dm 0x40e694ab 0a3d70a4
vcvt.u32.f64 s30, d21 :: Sd 0x00000000 Dm 0xc01fff00 00000000
vcvt.u32.f64 s11, d8 :: Sd 0xffffffff Dm 0x7ff00000 00000000
vcvt.u32.f64 s8, d12 :: Sd 0x00000000 Dm 0xfff00000 00000000
vcvt.u32.f64 s19, d7 :: Sd 0x00000000 Dm 0x7ff80000 00000000
-vcvt.u32.f64 s16, d16 :: Sd 0x0000004d Dm 0x40532ae1 47ae147b
+vcvt.u32.f64 s16, d16 :: Sd 0x0000004c Dm 0x40532ae1 47ae147b
vcvt.s32.f64 s0, d1 :: Sd 0x00000003 Dm 0x40099999 9999999a
-vcvt.s32.f64 s13, d26 :: Sd 0x000000eb Dm 0x406d5147 ae147ae1
+vcvt.s32.f64 s13, d26 :: Sd 0x000000ea Dm 0x406d5147 ae147ae1
vcvt.s32.f64 s29, d30 :: Sd 0x0000b4a5 Dm 0x40e694ab 0a3d70a4
-vcvt.s32.f64 s30, d21 :: Sd 0xfffffff8 Dm 0xc01fff00 00000000
+vcvt.s32.f64 s30, d21 :: Sd 0xfffffff9 Dm 0xc01fff00 00000000
vcvt.s32.f64 s11, d8 :: Sd 0x7fffffff Dm 0x7ff00000 00000000
vcvt.s32.f64 s8, d12 :: Sd 0x80000000 Dm 0xfff00000 00000000
vcvt.s32.f64 s19, d7 :: Sd 0x00000000 Dm 0x7ff80000 00000000
-vcvt.s32.f64 s16, d16 :: Sd 0x0000004d Dm 0x40532ae1 47ae147b
+vcvt.s32.f64 s16, d16 :: Sd 0x0000004c Dm 0x40532ae1 47ae147b
vcvt.f64.u32 d0, s1 :: Dd 0xfe000000 41efffff Sm 0x404ccccd
vcvt.f64.u32 d30, s21 :: Dd 0x5c200000 41e88483 Sm 0xc4241ae1
vcvt.f64.u32 d16, s12 :: Dd 0x62400000 41d11660 Sm 0x44598189
diff --git a/main/none/tests/async-sigs.stderr.exp-mips32 b/main/none/tests/async-sigs.stderr.exp-mips32
new file mode 100644
index 0000000..d910ea9
--- /dev/null
+++ b/main/none/tests/async-sigs.stderr.exp-mips32
@@ -0,0 +1,8 @@
+testing: blocking=0 caught=11 fatal=10... PASSED
+testing: blocking=0 caught=11 fatal=1... PASSED
+testing: blocking=0 caught=16 fatal=10... PASSED
+testing: blocking=0 caught=16 fatal=1... PASSED
+testing: blocking=1 caught=11 fatal=10... PASSED
+testing: blocking=1 caught=11 fatal=1... PASSED
+testing: blocking=1 caught=16 fatal=10... PASSED
+testing: blocking=1 caught=16 fatal=1... PASSED
diff --git a/main/none/tests/cmdline1.stdout.exp b/main/none/tests/cmdline1.stdout.exp
index 35ca443..e4cb9eb 100644
--- a/main/none/tests/cmdline1.stdout.exp
+++ b/main/none/tests/cmdline1.stdout.exp
@@ -50,7 +50,9 @@
[use current 'ulimit' value]
user options for Valgrind tools that replace malloc:
- --alignment=<number> set minimum alignment of heap allocations [...]
+ --alignment=<number> set minimum alignment of heap allocations [not used by this tool]
+ --redzone-size=<number> set minimum size of redzones added before/after
+ heap blocks (in bytes). [not used by this tool]
uncommon user options for all Valgrind tools:
--fullpath-after= (with nothing after the '=')
@@ -73,21 +75,27 @@
--run-libc-freeres=no|yes free up glibc memory at exit on Linux? [yes]
--sim-hints=hint1,hint2,... known hints:
lax-ioctls, enable-outer, fuse-compatible [none]
+ --fair-sched=no|yes|try schedule threads fairly on multicore systems [no]
--kernel-variant=variant1,variant2,... known variants: bproc [none]
handle non-standard kernel variants
--show-emwarns=no|yes show warnings about emulation limits? [no]
--require-text-symbol=:sonamepattern:symbolpattern abort run if the
stated shared object doesn't have the stated
text symbol. Patterns can contain ? and *.
+ --soname-synonyms=syn1=pattern1,syn2=pattern2,... synonym soname
+ specify patterns for function wrapping or replacement.
+ To use a non-libc malloc library that is
+ in the main exe: --soname-synonyms=somalloc=NONE
+ in libxyzzy.so: --soname-synonyms=somalloc=libxyzzy.so
user options for Nulgrind:
(none)
Extra options read from ~/.valgrindrc, $VALGRIND_OPTS, ./.valgrindrc
- Nulgrind is Copyright (C) 2002-2011, and GNU GPL'd, by Nicholas Nethercote.
- Valgrind is Copyright (C) 2000-2011, and GNU GPL'd, by Julian Seward et al.
- LibVEX is Copyright (C) 2004-2011, and GNU GPL'd, by OpenWorks LLP et al.
+ Nulgrind is Copyright (C) 2002-2012, and GNU GPL'd, by Nicholas Nethercote.
+ Valgrind is Copyright (C) 2000-2012, and GNU GPL'd, by Julian Seward et al.
+ LibVEX is Copyright (C) 2004-2012, and GNU GPL'd, by OpenWorks LLP et al.
Bug reports, feedback, admiration, abuse, etc, to: www.valgrind.org.
diff --git a/main/none/tests/cmdline2.stdout.exp b/main/none/tests/cmdline2.stdout.exp
index 01a3801..f226437 100644
--- a/main/none/tests/cmdline2.stdout.exp
+++ b/main/none/tests/cmdline2.stdout.exp
@@ -50,7 +50,9 @@
[use current 'ulimit' value]
user options for Valgrind tools that replace malloc:
- --alignment=<number> set minimum alignment of heap allocations [...]
+ --alignment=<number> set minimum alignment of heap allocations [not used by this tool]
+ --redzone-size=<number> set minimum size of redzones added before/after
+ heap blocks (in bytes). [not used by this tool]
uncommon user options for all Valgrind tools:
--fullpath-after= (with nothing after the '=')
@@ -73,12 +75,18 @@
--run-libc-freeres=no|yes free up glibc memory at exit on Linux? [yes]
--sim-hints=hint1,hint2,... known hints:
lax-ioctls, enable-outer, fuse-compatible [none]
+ --fair-sched=no|yes|try schedule threads fairly on multicore systems [no]
--kernel-variant=variant1,variant2,... known variants: bproc [none]
handle non-standard kernel variants
--show-emwarns=no|yes show warnings about emulation limits? [no]
--require-text-symbol=:sonamepattern:symbolpattern abort run if the
stated shared object doesn't have the stated
text symbol. Patterns can contain ? and *.
+ --soname-synonyms=syn1=pattern1,syn2=pattern2,... synonym soname
+ specify patterns for function wrapping or replacement.
+ To use a non-libc malloc library that is
+ in the main exe: --soname-synonyms=somalloc=NONE
+ in libxyzzy.so: --soname-synonyms=somalloc=libxyzzy.so
user options for Nulgrind:
(none)
@@ -90,6 +98,7 @@
--trace-flags=<XXXXXXXX> show generated code? (X = 0|1) [00000000]
--profile-flags=<XXXXXXXX> ditto, but for profiling (X = 0|1) [00000000]
--trace-notbelow=<number> only show BBs above <number> [999999999]
+ --trace-notabove=<number> only show BBs below <number> [0]
--trace-syscalls=no|yes show all system calls? [no]
--trace-signals=no|yes show signal handling details? [no]
--trace-symtab=no|yes show symbol table details? [no]
@@ -101,6 +110,8 @@
--trace-redir=no|yes show redirection details? [no]
--trace-sched=no|yes show thread scheduler details? [no]
--profile-heap=no|yes profile Valgrind's own space use
+ --core-redzone=<number> set minimum size of redzones added before/after
+ heap blocks allocated for Valgrind internal use (in bytes) [4]
--wait-for-gdb=yes|no pause on startup to wait for gdb attach
--sym-offsets=yes|no show syms in form 'name+offset' ? [no]
--command-line-only=no|yes only use command line options [no]
@@ -108,7 +119,9 @@
Vex options for all Valgrind tools:
--vex-iropt-verbosity=<0..9> [0]
--vex-iropt-level=<0..2> [2]
- --vex-iropt-precise-memory-exns=no|yes [no]
+ --vex-iropt-register-updates=unwindregs-at-mem-access
+ |allregs-at-mem-access
+ |allregs-at-each-insn [unwindregs-at-mem-access]
--vex-iropt-unroll-thresh=<0..400> [120]
--vex-guest-max-insns=<1..100> [50]
--vex-guest-chase-thresh=<0..99> [10]
@@ -122,7 +135,7 @@
0000 0100 show selecting insns
0000 0010 show after reg-alloc
0000 0001 show final assembly
- (Nb: you need --trace-notbelow with --trace-flags for full details)
+ (Nb: you need --trace-notbelow and/or --trace-notabove with --trace-flags for full details)
debugging options for Valgrind tools that report errors
--dump-error=<number> show translation for basic block associated
@@ -136,9 +149,9 @@
Extra options read from ~/.valgrindrc, $VALGRIND_OPTS, ./.valgrindrc
- Nulgrind is Copyright (C) 2002-2011, and GNU GPL'd, by Nicholas Nethercote.
- Valgrind is Copyright (C) 2000-2011, and GNU GPL'd, by Julian Seward et al.
- LibVEX is Copyright (C) 2004-2011, and GNU GPL'd, by OpenWorks LLP et al.
+ Nulgrind is Copyright (C) 2002-2012, and GNU GPL'd, by Nicholas Nethercote.
+ Valgrind is Copyright (C) 2000-2012, and GNU GPL'd, by Julian Seward et al.
+ LibVEX is Copyright (C) 2004-2012, and GNU GPL'd, by OpenWorks LLP et al.
Bug reports, feedback, admiration, abuse, etc, to: www.valgrind.org.
diff --git a/main/none/tests/darwin/Makefile.in b/main/none/tests/darwin/Makefile.in
new file mode 100644
index 0000000..f21f9f3
--- /dev/null
+++ b/main/none/tests/darwin/Makefile.in
@@ -0,0 +1,713 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = access_extended$(EXEEXT) apple-main-arg$(EXEEXT) \
+ rlimit$(EXEEXT)
+subdir = none/tests/darwin
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+access_extended_SOURCES = access_extended.c
+access_extended_OBJECTS = access_extended.$(OBJEXT)
+access_extended_LDADD = $(LDADD)
+apple_main_arg_SOURCES = apple-main-arg.c
+apple_main_arg_OBJECTS = apple-main-arg.$(OBJEXT)
+apple_main_arg_LDADD = $(LDADD)
+rlimit_SOURCES = rlimit.c
+rlimit_OBJECTS = rlimit.$(OBJEXT)
+rlimit_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = access_extended.c apple-main-arg.c rlimit.c
+DIST_SOURCES = access_extended.c apple-main-arg.c rlimit.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ access_extended.stderr.exp access_extended.vgtest \
+ apple-main-arg.stderr.exp apple-main-arg.vgtest \
+ rlimit.stderr.exp rlimit.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/darwin/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/darwin/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+access_extended$(EXEEXT): $(access_extended_OBJECTS) $(access_extended_DEPENDENCIES)
+ @rm -f access_extended$(EXEEXT)
+ $(LINK) $(access_extended_OBJECTS) $(access_extended_LDADD) $(LIBS)
+apple-main-arg$(EXEEXT): $(apple_main_arg_OBJECTS) $(apple_main_arg_DEPENDENCIES)
+ @rm -f apple-main-arg$(EXEEXT)
+ $(LINK) $(apple_main_arg_OBJECTS) $(apple_main_arg_LDADD) $(LIBS)
+rlimit$(EXEEXT): $(rlimit_OBJECTS) $(rlimit_DEPENDENCIES)
+ @rm -f rlimit$(EXEEXT)
+ $(LINK) $(rlimit_OBJECTS) $(rlimit_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/access_extended.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/apple-main-arg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rlimit.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/execve.c b/main/none/tests/execve.c
index 842df78..aba2529 100644
--- a/main/none/tests/execve.c
+++ b/main/none/tests/execve.c
@@ -8,7 +8,7 @@
{
// This tests the case where argv and envp are NULL, which is easy to
// get wrong because it's an unusual case.
- if (execve(argv[0], NULL, NULL) < 0)
+ if (execve("/bin/true", NULL, NULL) < 0)
{
perror("execve");
exit(1);
diff --git a/main/none/tests/faultstatus.stderr.exp-s390x b/main/none/tests/faultstatus.stderr.exp-s390x
new file mode 100644
index 0000000..67c7e82
--- /dev/null
+++ b/main/none/tests/faultstatus.stderr.exp-s390x
@@ -0,0 +1,6 @@
+
+Test 1: PASS
+Test 2: PASS
+Test 3: FAIL: expected si_code==2, not 128
+Test 4: PASS
+
diff --git a/main/none/tests/ifunc.c b/main/none/tests/ifunc.c
new file mode 100644
index 0000000..523d923
--- /dev/null
+++ b/main/none/tests/ifunc.c
@@ -0,0 +1,21 @@
+/* This test made valgrind run in an infinite loop. See bugzilla #301204 */
+#include <stdio.h>
+
+static void mytest(int d)
+{
+ printf("%d\n", d);
+}
+
+static void (*resolve_test(void))(void)
+{
+ return (void (*)(void))&mytest;
+}
+
+void test(int d)
+ __attribute__((ifunc("resolve_test")));
+
+int main()
+{
+ test(5);
+ return 0;
+}
diff --git a/main/none/tests/ifunc.stderr.exp b/main/none/tests/ifunc.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ifunc.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ifunc.stdout.exp b/main/none/tests/ifunc.stdout.exp
new file mode 100644
index 0000000..7ed6ff8
--- /dev/null
+++ b/main/none/tests/ifunc.stdout.exp
@@ -0,0 +1 @@
+5
diff --git a/main/none/tests/ifunc.vgtest b/main/none/tests/ifunc.vgtest
new file mode 100644
index 0000000..f9ddd3e
--- /dev/null
+++ b/main/none/tests/ifunc.vgtest
@@ -0,0 +1,2 @@
+prereq: test -e ifunc
+prog: ifunc
diff --git a/main/none/tests/linux/Makefile.am b/main/none/tests/linux/Makefile.am
index e9edb9a..04b6f7b 100644
--- a/main/none/tests/linux/Makefile.am
+++ b/main/none/tests/linux/Makefile.am
@@ -7,12 +7,14 @@
blockfault.stderr.exp blockfault.vgtest \
mremap.stderr.exp mremap.stderr.exp-glibc27 mremap.stdout.exp \
mremap.vgtest \
- mremap2.stderr.exp mremap2.stdout.exp mremap2.vgtest
+ mremap2.stderr.exp mremap2.stdout.exp mremap2.vgtest \
+ mremap3.stderr.exp mremap3.stdout.exp mremap3.vgtest
check_PROGRAMS = \
blockfault \
mremap \
- mremap2
+ mremap2 \
+ mremap3
AM_CFLAGS += $(AM_FLAG_M3264_PRI)
diff --git a/main/none/tests/linux/Makefile.in b/main/none/tests/linux/Makefile.in
new file mode 100644
index 0000000..202bfb1
--- /dev/null
+++ b/main/none/tests/linux/Makefile.in
@@ -0,0 +1,722 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = blockfault$(EXEEXT) mremap$(EXEEXT) mremap2$(EXEEXT) \
+ mremap3$(EXEEXT)
+subdir = none/tests/linux
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+blockfault_SOURCES = blockfault.c
+blockfault_OBJECTS = blockfault.$(OBJEXT)
+blockfault_LDADD = $(LDADD)
+mremap_SOURCES = mremap.c
+mremap_OBJECTS = mremap.$(OBJEXT)
+mremap_LDADD = $(LDADD)
+mremap2_SOURCES = mremap2.c
+mremap2_OBJECTS = mremap2.$(OBJEXT)
+mremap2_LDADD = $(LDADD)
+mremap3_SOURCES = mremap3.c
+mremap3_OBJECTS = mremap3.$(OBJEXT)
+mremap3_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = blockfault.c mremap.c mremap2.c mremap3.c
+DIST_SOURCES = blockfault.c mremap.c mremap2.c mremap3.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ blockfault.stderr.exp blockfault.vgtest \
+ mremap.stderr.exp mremap.stderr.exp-glibc27 mremap.stdout.exp \
+ mremap.vgtest \
+ mremap2.stderr.exp mremap2.stdout.exp mremap2.vgtest \
+ mremap3.stderr.exp mremap3.stdout.exp mremap3.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/linux/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/linux/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+blockfault$(EXEEXT): $(blockfault_OBJECTS) $(blockfault_DEPENDENCIES)
+ @rm -f blockfault$(EXEEXT)
+ $(LINK) $(blockfault_OBJECTS) $(blockfault_LDADD) $(LIBS)
+mremap$(EXEEXT): $(mremap_OBJECTS) $(mremap_DEPENDENCIES)
+ @rm -f mremap$(EXEEXT)
+ $(LINK) $(mremap_OBJECTS) $(mremap_LDADD) $(LIBS)
+mremap2$(EXEEXT): $(mremap2_OBJECTS) $(mremap2_DEPENDENCIES)
+ @rm -f mremap2$(EXEEXT)
+ $(LINK) $(mremap2_OBJECTS) $(mremap2_LDADD) $(LIBS)
+mremap3$(EXEEXT): $(mremap3_OBJECTS) $(mremap3_DEPENDENCIES)
+ @rm -f mremap3$(EXEEXT)
+ $(LINK) $(mremap3_OBJECTS) $(mremap3_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/blockfault.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mremap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mremap2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mremap3.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/linux/mremap3.c b/main/none/tests/linux/mremap3.c
new file mode 100644
index 0000000..faf8d19
--- /dev/null
+++ b/main/none/tests/linux/mremap3.c
@@ -0,0 +1,40 @@
+#define _GNU_SOURCE 1
+#include <sys/mman.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+int main(void)
+{
+ /* first find free segment of 40K, then unmap it */
+ void *initial_area = mmap((void *)0x10000000, 40960, PROT_READ|PROT_WRITE,
+ MAP_ANONYMOUS|MAP_PRIVATE,0,0);
+
+ if (initial_area == MAP_FAILED)
+ perror ("initial area");
+ printf("initial_area= %p\n", initial_area);
+ if (munmap(initial_area, 40960) != 0)
+ perror ("munmap initial_area");
+
+ /* remap the same segment, but with 4K size */
+ void *area = mmap(initial_area, 4096, PROT_READ|PROT_WRITE,
+ MAP_ANONYMOUS|MAP_PRIVATE,0,0);
+ if (area == MAP_FAILED)
+ perror ("area");
+ if (area != initial_area)
+ printf("FAILED : was expecting to get back the initial_area\n");
+ printf("area= %p\n", area);
+ strcpy(area, "Hello World");
+
+ /* extend it to 40K */
+ void *a2 = mremap(area, 4096, 40960, 0);
+ if (a2 == MAP_FAILED) {
+ perror("mremap");
+ }
+ if (a2 != initial_area)
+ printf("FAILED : was expecting to get back the same area increased\n");
+ printf("increased area= %p\n", a2);
+ printf("%s\n", (char *)a2);
+ return 0;
+}
diff --git a/main/none/tests/linux/mremap3.stderr.exp b/main/none/tests/linux/mremap3.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/linux/mremap3.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/linux/mremap3.stdout.exp b/main/none/tests/linux/mremap3.stdout.exp
new file mode 100644
index 0000000..6d2fe2a
--- /dev/null
+++ b/main/none/tests/linux/mremap3.stdout.exp
@@ -0,0 +1,4 @@
+initial_area= 0x........
+area= 0x........
+increased area= 0x........
+Hello World
diff --git a/main/none/tests/linux/mremap3.vgtest b/main/none/tests/linux/mremap3.vgtest
new file mode 100644
index 0000000..4555994
--- /dev/null
+++ b/main/none/tests/linux/mremap3.vgtest
@@ -0,0 +1,2 @@
+prog: mremap3
+stdout_filter: ../../../tests/filter_addresses
diff --git a/main/none/tests/mips32/FPUarithmetic.c b/main/none/tests/mips32/FPUarithmetic.c
new file mode 100644
index 0000000..3a76b3f
--- /dev/null
+++ b/main/none/tests/mips32/FPUarithmetic.c
@@ -0,0 +1,195 @@
+#include <stdio.h>
+
+typedef enum {
+ ABSS=0, ABSD,
+ ADDS, ADDD,
+ DIVS, DIVD,
+ MULS, MULD,
+ NEGS, NEGD,
+ SQRTS, SQRTD,
+ SUBS, SUBD,
+ RECIPS, RECIPD,
+ RSQRTS, RSQRTD
+} flt_art_op_t;
+
+const char *flt_art_op_names[] = {
+ "abs.s", "abs.d",
+ "add.s", "add.d",
+ "div.s", "div.d",
+ "mul.s", "mul.d",
+ "neg.s", "neg.d",
+ "sqrt.s", "sqrt.d",
+ "sub.s", "sub.d",
+ "recip.s", "recip.d",
+ "rsqrt.s", "rsqrt.d"
+};
+
+const double fs_d[] = {
+ 0, 456.2489562, 3, -1,
+ 1384.6, -7.2945676, 1000000000, -5786.47,
+ 1752, 0.0024575, 0.00000001, -248562.76,
+ -45786.476, 456.2489562, 34.00046, 45786.476,
+ 1752065, 107, -45667.24, -7.2945676,
+ -347856.475, 356047.56, -1.0, 23.04
+};
+
+const double ft_d[] = {
+ -45786.476, 456.2489562, 34.00046, 45786.476,
+ 1752065, 107, -45667.24, -7.2945676,
+ -347856.475, 356047.56, -1.0, 23.04,
+ 0, 456.2489562, 3, -1,
+ 1384.6, -7.2945676, 1000000000, -5786.47,
+ 1752, 0.0024575, 0.00000001, -248562.76
+};
+
+const float fs_f[] = {
+ 0, 456.2489562, 3, -1,
+ 1384.6, -7.2945676, 1000000000, -5786.47,
+ 1752, 0.0024575, 0.00000001, -248562.76,
+ -45786.476, 456.2489562, 34.00046, 45786.476,
+ 1752065, 107, -45667.24, -7.2945676,
+ -347856.475, 356047.56, -1.0, 23.04
+};
+
+const float ft_f[] = {
+ -45786.476, 456.2489562, 34.00046, 45786.476,
+ 1752065, 107, -45667.24, -7.2945676,
+ -347856.475, 356047.56, -1.0, 23.04,
+ 0, 456.2489562, 3, -1,
+ 1384.6, -7.2945676, 1000000000, -5786.47,
+ 1752, 0.0024575, 0.00000001, -248562.76
+};
+
+#define UNOPdd(op) \
+ fd_d = 0; \
+ __asm__ volatile( \
+ op" %0, %1\n\t" \
+ : "=f"(fd_d) : "f"(fs_d[i]));
+
+#define UNOPff(op) \
+ fd_f = 0; \
+ __asm__ volatile( \
+ op" %0, %1\n\t" \
+ : "=f"(fd_f) : "f"(fs_f[i]));
+
+#define BINOPf(op) \
+ fd_f = 0; \
+ __asm__ volatile( \
+ op" %0, %1, %2\n\t" \
+ : "=f"(fd_f) : "f"(fs_f[i]) , "f"(ft_f[i]));
+
+#define BINOPd(op) \
+ fd_d = 0; \
+ __asm__ volatile( \
+ op" %0, %1, %2\n\t" \
+ : "=f"(fd_d) : "f"(fs_d[i]) , "f"(ft_d[i]));
+
+int arithmeticOperations(flt_art_op_t op)
+{
+ double fd_d = 0;
+ float fd_f = 0;
+ int i = 0;
+ for (i = 0; i < 24; i++)
+ {
+ switch(op) {
+ case ABSS:
+ UNOPff("abs.s");
+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]);
+ break;
+ case ABSD:
+ UNOPdd("abs.d");
+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]);
+ break;
+ case ADDS:
+ BINOPf("add.s");
+ printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]);
+ break;
+ case ADDD:
+ BINOPd("add.d");
+ printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]);
+ break;
+ case DIVS:
+ BINOPf("div.s");
+ printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]);
+ break;
+ case DIVD:
+ BINOPd("div.d");
+ printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]);
+ break;
+ case MULS:
+ BINOPf("mul.s");
+ printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]);
+ break;
+ case MULD:
+ BINOPd("mul.d");
+ printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]);
+ break;
+ case NEGS:
+ UNOPff("neg.s");
+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]);
+ break;
+ case NEGD:
+ UNOPdd("neg.d");
+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]);
+ break;
+ case SQRTS:
+ UNOPff("sqrt.s");
+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]);
+ break;
+ case SQRTD:
+ UNOPdd("sqrt.d");
+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]);
+ break;
+ case SUBS:
+ BINOPf("sub.s");
+ printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]);
+ break;
+ case SUBD:
+ BINOPd("sub.d");
+ printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]);
+ break;
+ case RECIPS:
+#if (__mips==32) && (__mips_isa_rev>=2)
+ UNOPff("recip.s");
+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]);
+#endif
+ break;
+ case RECIPD:
+#if (__mips==32) && (__mips_isa_rev>=2)
+ UNOPdd("recip.d");
+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]);
+#endif
+ break;
+ case RSQRTS:
+#if (__mips==32) && (__mips_isa_rev>=2)
+ UNOPff("rsqrt.s");
+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]);
+#endif
+ break;
+ case RSQRTD:
+#if (__mips==32) && (__mips_isa_rev>=2)
+ UNOPdd("rsqrt.d");
+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]);
+#endif
+ break;
+ default:
+ printf("error\n");
+ break;
+ }
+ }
+ return 0;
+}
+
+int main()
+{
+ flt_art_op_t op;
+
+ printf("-------------------------- %s --------------------------\n",
+ "test FPU Arithmetic Operations");
+ for (op = ABSS; op <= RECIPD; op++) {
+ arithmeticOperations(op);
+ }
+
+ return 0;
+}
+
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/mips32/FPUarithmetic.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/mips32/FPUarithmetic.stderr.exp
diff --git a/main/none/tests/mips32/FPUarithmetic.stdout.exp b/main/none/tests/mips32/FPUarithmetic.stdout.exp
new file mode 100644
index 0000000..0eac001
--- /dev/null
+++ b/main/none/tests/mips32/FPUarithmetic.stdout.exp
@@ -0,0 +1,385 @@
+-------------------------- test FPU Arithmetic Operations --------------------------
+abs.s 0.000000 0.000000
+abs.s 456.248962 456.248962
+abs.s 3.000000 3.000000
+abs.s 1.000000 -1.000000
+abs.s 1384.599976 1384.599976
+abs.s 7.294568 -7.294568
+abs.s 1000000000.000000 1000000000.000000
+abs.s 5786.470215 -5786.470215
+abs.s 1752.000000 1752.000000
+abs.s 0.002457 0.002457
+abs.s 0.000000 0.000000
+abs.s 248562.765625 -248562.765625
+abs.s 45786.476562 -45786.476562
+abs.s 456.248962 456.248962
+abs.s 34.000462 34.000462
+abs.s 45786.476562 45786.476562
+abs.s 1752065.000000 1752065.000000
+abs.s 107.000000 107.000000
+abs.s 45667.238281 -45667.238281
+abs.s 7.294568 -7.294568
+abs.s 347856.468750 -347856.468750
+abs.s 356047.562500 356047.562500
+abs.s 1.000000 -1.000000
+abs.s 23.040001 23.040001
+abs.d 0.000000 0.000000
+abs.d 456.248956 456.248956
+abs.d 3.000000 3.000000
+abs.d 1.000000 -1.000000
+abs.d 1384.600000 1384.600000
+abs.d 7.294568 -7.294568
+abs.d 1000000000.000000 1000000000.000000
+abs.d 5786.470000 -5786.470000
+abs.d 1752.000000 1752.000000
+abs.d 0.002458 0.002458
+abs.d 0.000000 0.000000
+abs.d 248562.760000 -248562.760000
+abs.d 45786.476000 -45786.476000
+abs.d 456.248956 456.248956
+abs.d 34.000460 34.000460
+abs.d 45786.476000 45786.476000
+abs.d 1752065.000000 1752065.000000
+abs.d 107.000000 107.000000
+abs.d 45667.240000 -45667.240000
+abs.d 7.294568 -7.294568
+abs.d 347856.475000 -347856.475000
+abs.d 356047.560000 356047.560000
+abs.d 1.000000 -1.000000
+abs.d 23.040000 23.040000
+add.s -45786.476562 0.000000 -45786.476562
+add.s 912.497925 456.248962 456.248962
+add.s 37.000462 3.000000 34.000462
+add.s 45785.476562 -1.000000 45786.476562
+add.s 1753449.625000 1384.599976 1752065.000000
+add.s 99.705429 -7.294568 107.000000
+add.s 999954304.000000 1000000000.000000 -45667.238281
+add.s -5793.764648 -5786.470215 -7.294568
+add.s -346104.468750 1752.000000 -347856.468750
+add.s 356047.562500 0.002457 356047.562500
+add.s -1.000000 0.000000 -1.000000
+add.s -248539.718750 -248562.765625 23.040001
+add.s -45786.476562 -45786.476562 0.000000
+add.s 912.497925 456.248962 456.248962
+add.s 37.000462 34.000462 3.000000
+add.s 45785.476562 45786.476562 -1.000000
+add.s 1753449.625000 1752065.000000 1384.599976
+add.s 99.705429 107.000000 -7.294568
+add.s 999954304.000000 -45667.238281 1000000000.000000
+add.s -5793.764648 -7.294568 -5786.470215
+add.s -346104.468750 -347856.468750 1752.000000
+add.s 356047.562500 356047.562500 0.002457
+add.s -1.000000 -1.000000 0.000000
+add.s -248539.718750 23.040001 -248562.765625
+add.d -45786.476000 0.000000 -45786.476000
+add.d 912.497912 456.248956 456.248956
+add.d 37.000460 3.000000 34.000460
+add.d 45785.476000 -1.000000 45786.476000
+add.d 1753449.600000 1384.600000 1752065.000000
+add.d 99.705432 -7.294568 107.000000
+add.d 999954332.760000 1000000000.000000 -45667.240000
+add.d -5793.764568 -5786.470000 -7.294568
+add.d -346104.475000 1752.000000 -347856.475000
+add.d 356047.562458 0.002458 356047.560000
+add.d -1.000000 0.000000 -1.000000
+add.d -248539.720000 -248562.760000 23.040000
+add.d -45786.476000 -45786.476000 0.000000
+add.d 912.497912 456.248956 456.248956
+add.d 37.000460 34.000460 3.000000
+add.d 45785.476000 45786.476000 -1.000000
+add.d 1753449.600000 1752065.000000 1384.600000
+add.d 99.705432 107.000000 -7.294568
+add.d 999954332.760000 -45667.240000 1000000000.000000
+add.d -5793.764568 -7.294568 -5786.470000
+add.d -346104.475000 -347856.475000 1752.000000
+add.d 356047.562458 356047.560000 0.002458
+add.d -1.000000 -1.000000 0.000000
+add.d -248539.720000 23.040000 -248562.760000
+div.s -0.000000 0.000000 -45786.476562
+div.s 1.000000 456.248962 456.248962
+div.s 0.088234 3.000000 34.000462
+div.s -0.000022 -1.000000 45786.476562
+div.s 0.000790 1384.599976 1752065.000000
+div.s -0.068174 -7.294568 107.000000
+div.s -21897.535156 1000000000.000000 -45667.238281
+div.s 793.257446 -5786.470215 -7.294568
+div.s -0.005037 1752.000000 -347856.468750
+div.s 0.000000 0.002457 356047.562500
+div.s -0.000000 0.000000 -1.000000
+div.s -10788.314453 -248562.765625 23.040001
+div.s -inf -45786.476562 0.000000
+div.s 1.000000 456.248962 456.248962
+div.s 11.333488 34.000462 3.000000
+div.s -45786.476562 45786.476562 -1.000000
+div.s 1265.394409 1752065.000000 1384.599976
+div.s -14.668450 107.000000 -7.294568
+div.s -0.000046 -45667.238281 1000000000.000000
+div.s 0.001261 -7.294568 -5786.470215
+div.s -198.548218 -347856.468750 1752.000000
+div.s 144882016.000000 356047.562500 0.002457
+div.s -100000000.000000 -1.000000 0.000000
+div.s -0.000093 23.040001 -248562.765625
+div.d -0.000000 0.000000 -45786.476000
+div.d 1.000000 456.248956 456.248956
+div.d 0.088234 3.000000 34.000460
+div.d -0.000022 -1.000000 45786.476000
+div.d 0.000790 1384.600000 1752065.000000
+div.d -0.068174 -7.294568 107.000000
+div.d -21897.535301 1000000000.000000 -45667.240000
+div.d 793.257437 -5786.470000 -7.294568
+div.d -0.005037 1752.000000 -347856.475000
+div.d 0.000000 0.002458 356047.560000
+div.d -0.000000 0.000000 -1.000000
+div.d -10788.314236 -248562.760000 23.040000
+div.d -inf -45786.476000 0.000000
+div.d 1.000000 456.248956 456.248956
+div.d 11.333487 34.000460 3.000000
+div.d -45786.476000 45786.476000 -1.000000
+div.d 1265.394338 1752065.000000 1384.600000
+div.d -14.668450 107.000000 -7.294568
+div.d -0.000046 -45667.240000 1000000000.000000
+div.d 0.001261 -7.294568 -5786.470000
+div.d -198.548216 -347856.475000 1752.000000
+div.d 144882018.311292 356047.560000 0.002458
+div.d -100000000.000000 -1.000000 0.000000
+div.d -0.000093 23.040000 -248562.760000
+mul.s -0.000000 0.000000 -45786.476562
+mul.s 208163.109375 456.248962 456.248962
+mul.s 102.001389 3.000000 34.000462
+mul.s -45786.476562 -1.000000 45786.476562
+mul.s 2425909248.000000 1384.599976 1752065.000000
+mul.s -780.518738 -7.294568 107.000000
+mul.s -45667238019072.000000 1000000000.000000 -45667.238281
+mul.s 42209.796875 -5786.470215 -7.294568
+mul.s -609444544.000000 1752.000000 -347856.468750
+mul.s 874.986877 0.002457 356047.562500
+mul.s -0.000000 0.000000 -1.000000
+mul.s -5726886.500000 -248562.765625 23.040001
+mul.s -0.000000 -45786.476562 0.000000
+mul.s 208163.109375 456.248962 456.248962
+mul.s 102.001389 34.000462 3.000000
+mul.s -45786.476562 45786.476562 -1.000000
+mul.s 2425909248.000000 1752065.000000 1384.599976
+mul.s -780.518738 107.000000 -7.294568
+mul.s -45667238019072.000000 -45667.238281 1000000000.000000
+mul.s 42209.796875 -7.294568 -5786.470215
+mul.s -609444544.000000 -347856.468750 1752.000000
+mul.s 874.986877 356047.562500 0.002457
+mul.s -0.000000 -1.000000 0.000000
+mul.s -5726886.500000 23.040001 -248562.765625
+mul.d -0.000000 0.000000 -45786.476000
+mul.d 208163.110034 456.248956 456.248956
+mul.d 102.001380 3.000000 34.000460
+mul.d -45786.476000 -1.000000 45786.476000
+mul.d 2425909199.000000 1384.600000 1752065.000000
+mul.d -780.518733 -7.294568 107.000000
+mul.d -45667240000000.000000 1000000000.000000 -45667.240000
+mul.d 42209.796580 -5786.470000 -7.294568
+mul.d -609444544.200000 1752.000000 -347856.475000
+mul.d 874.986879 0.002458 356047.560000
+mul.d -0.000000 0.000000 -1.000000
+mul.d -5726885.990400 -248562.760000 23.040000
+mul.d -0.000000 -45786.476000 0.000000
+mul.d 208163.110034 456.248956 456.248956
+mul.d 102.001380 34.000460 3.000000
+mul.d -45786.476000 45786.476000 -1.000000
+mul.d 2425909199.000000 1752065.000000 1384.600000
+mul.d -780.518733 107.000000 -7.294568
+mul.d -45667240000000.000000 -45667.240000 1000000000.000000
+mul.d 42209.796580 -7.294568 -5786.470000
+mul.d -609444544.200000 -347856.475000 1752.000000
+mul.d 874.986879 356047.560000 0.002458
+mul.d -0.000000 -1.000000 0.000000
+mul.d -5726885.990400 23.040000 -248562.760000
+neg.s -0.000000 0.000000
+neg.s -456.248962 456.248962
+neg.s -3.000000 3.000000
+neg.s 1.000000 -1.000000
+neg.s -1384.599976 1384.599976
+neg.s 7.294568 -7.294568
+neg.s -1000000000.000000 1000000000.000000
+neg.s 5786.470215 -5786.470215
+neg.s -1752.000000 1752.000000
+neg.s -0.002457 0.002457
+neg.s -0.000000 0.000000
+neg.s 248562.765625 -248562.765625
+neg.s 45786.476562 -45786.476562
+neg.s -456.248962 456.248962
+neg.s -34.000462 34.000462
+neg.s -45786.476562 45786.476562
+neg.s -1752065.000000 1752065.000000
+neg.s -107.000000 107.000000
+neg.s 45667.238281 -45667.238281
+neg.s 7.294568 -7.294568
+neg.s 347856.468750 -347856.468750
+neg.s -356047.562500 356047.562500
+neg.s 1.000000 -1.000000
+neg.s -23.040001 23.040001
+neg.d -0.000000 0.000000
+neg.d -456.248956 456.248956
+neg.d -3.000000 3.000000
+neg.d 1.000000 -1.000000
+neg.d -1384.600000 1384.600000
+neg.d 7.294568 -7.294568
+neg.d -1000000000.000000 1000000000.000000
+neg.d 5786.470000 -5786.470000
+neg.d -1752.000000 1752.000000
+neg.d -0.002458 0.002458
+neg.d -0.000000 0.000000
+neg.d 248562.760000 -248562.760000
+neg.d 45786.476000 -45786.476000
+neg.d -456.248956 456.248956
+neg.d -34.000460 34.000460
+neg.d -45786.476000 45786.476000
+neg.d -1752065.000000 1752065.000000
+neg.d -107.000000 107.000000
+neg.d 45667.240000 -45667.240000
+neg.d 7.294568 -7.294568
+neg.d 347856.475000 -347856.475000
+neg.d -356047.560000 356047.560000
+neg.d 1.000000 -1.000000
+neg.d -23.040000 23.040000
+sqrt.s 0.000000 0.000000
+sqrt.s 21.359985 456.248962
+sqrt.s 1.732051 3.000000
+sqrt.s nan -1.000000
+sqrt.s 37.210213 1384.599976
+sqrt.s nan -7.294568
+sqrt.s 31622.777344 1000000000.000000
+sqrt.s nan -5786.470215
+sqrt.s 41.856899 1752.000000
+sqrt.s 0.049573 0.002457
+sqrt.s 0.000100 0.000000
+sqrt.s nan -248562.765625
+sqrt.s nan -45786.476562
+sqrt.s 21.359985 456.248962
+sqrt.s 5.830991 34.000462
+sqrt.s 213.977753 45786.476562
+sqrt.s 1323.655884 1752065.000000
+sqrt.s 10.344080 107.000000
+sqrt.s nan -45667.238281
+sqrt.s nan -7.294568
+sqrt.s nan -347856.468750
+sqrt.s 596.697205 356047.562500
+sqrt.s nan -1.000000
+sqrt.s 4.800000 23.040001
+sqrt.d 0.000000 0.000000
+sqrt.d 21.359985 456.248956
+sqrt.d 1.732051 3.000000
+sqrt.d nan -1.000000
+sqrt.d 37.210214 1384.600000
+sqrt.d nan -7.294568
+sqrt.d 31622.776602 1000000000.000000
+sqrt.d nan -5786.470000
+sqrt.d 41.856899 1752.000000
+sqrt.d 0.049573 0.002458
+sqrt.d 0.000100 0.000000
+sqrt.d nan -248562.760000
+sqrt.d nan -45786.476000
+sqrt.d 21.359985 456.248956
+sqrt.d 5.830991 34.000460
+sqrt.d 213.977747 45786.476000
+sqrt.d 1323.655922 1752065.000000
+sqrt.d 10.344080 107.000000
+sqrt.d nan -45667.240000
+sqrt.d nan -7.294568
+sqrt.d nan -347856.475000
+sqrt.d 596.697210 356047.560000
+sqrt.d nan -1.000000
+sqrt.d 4.800000 23.040000
+sub.s 45786.476562 0.000000 -45786.476562
+sub.s 0.000000 456.248962 456.248962
+sub.s -31.000462 3.000000 34.000462
+sub.s -45787.476562 -1.000000 45786.476562
+sub.s -1750680.375000 1384.599976 1752065.000000
+sub.s -114.294571 -7.294568 107.000000
+sub.s 1000045696.000000 1000000000.000000 -45667.238281
+sub.s -5779.175781 -5786.470215 -7.294568
+sub.s 349608.468750 1752.000000 -347856.468750
+sub.s -356047.562500 0.002457 356047.562500
+sub.s 1.000000 0.000000 -1.000000
+sub.s -248585.812500 -248562.765625 23.040001
+sub.s -45786.476562 -45786.476562 0.000000
+sub.s 0.000000 456.248962 456.248962
+sub.s 31.000462 34.000462 3.000000
+sub.s 45787.476562 45786.476562 -1.000000
+sub.s 1750680.375000 1752065.000000 1384.599976
+sub.s 114.294571 107.000000 -7.294568
+sub.s -1000045696.000000 -45667.238281 1000000000.000000
+sub.s 5779.175781 -7.294568 -5786.470215
+sub.s -349608.468750 -347856.468750 1752.000000
+sub.s 356047.562500 356047.562500 0.002457
+sub.s -1.000000 -1.000000 0.000000
+sub.s 248585.812500 23.040001 -248562.765625
+sub.d 45786.476000 0.000000 -45786.476000
+sub.d 0.000000 456.248956 456.248956
+sub.d -31.000460 3.000000 34.000460
+sub.d -45787.476000 -1.000000 45786.476000
+sub.d -1750680.400000 1384.600000 1752065.000000
+sub.d -114.294568 -7.294568 107.000000
+sub.d 1000045667.240000 1000000000.000000 -45667.240000
+sub.d -5779.175432 -5786.470000 -7.294568
+sub.d 349608.475000 1752.000000 -347856.475000
+sub.d -356047.557542 0.002458 356047.560000
+sub.d 1.000000 0.000000 -1.000000
+sub.d -248585.800000 -248562.760000 23.040000
+sub.d -45786.476000 -45786.476000 0.000000
+sub.d 0.000000 456.248956 456.248956
+sub.d 31.000460 34.000460 3.000000
+sub.d 45787.476000 45786.476000 -1.000000
+sub.d 1750680.400000 1752065.000000 1384.600000
+sub.d 114.294568 107.000000 -7.294568
+sub.d -1000045667.240000 -45667.240000 1000000000.000000
+sub.d 5779.175432 -7.294568 -5786.470000
+sub.d -349608.475000 -347856.475000 1752.000000
+sub.d 356047.557542 356047.560000 0.002458
+sub.d -1.000000 -1.000000 0.000000
+sub.d 248585.800000 23.040000 -248562.760000
+recip.s inf 0.000000
+recip.s 0.002192 456.248962
+recip.s 0.333333 3.000000
+recip.s -1.000000 -1.000000
+recip.s 0.000722 1384.599976
+recip.s -0.137088 -7.294568
+recip.s 0.000000 1000000000.000000
+recip.s -0.000173 -5786.470215
+recip.s 0.000571 1752.000000
+recip.s 406.917603 0.002457
+recip.s 100000000.000000 0.000000
+recip.s -0.000004 -248562.765625
+recip.s -0.000022 -45786.476562
+recip.s 0.002192 456.248962
+recip.s 0.029411 34.000462
+recip.s 0.000022 45786.476562
+recip.s 0.000001 1752065.000000
+recip.s 0.009346 107.000000
+recip.s -0.000022 -45667.238281
+recip.s -0.137088 -7.294568
+recip.s -0.000003 -347856.468750
+recip.s 0.000003 356047.562500
+recip.s -1.000000 -1.000000
+recip.s 0.043403 23.040001
+recip.d inf 0.000000
+recip.d 0.002192 456.248956
+recip.d 0.333333 3.000000
+recip.d -1.000000 -1.000000
+recip.d 0.000722 1384.600000
+recip.d -0.137088 -7.294568
+recip.d 0.000000 1000000000.000000
+recip.d -0.000173 -5786.470000
+recip.d 0.000571 1752.000000
+recip.d 406.917599 0.002458
+recip.d 100000000.000000 0.000000
+recip.d -0.000004 -248562.760000
+recip.d -0.000022 -45786.476000
+recip.d 0.002192 456.248956
+recip.d 0.029411 34.000460
+recip.d 0.000022 45786.476000
+recip.d 0.000001 1752065.000000
+recip.d 0.009346 107.000000
+recip.d -0.000022 -45667.240000
+recip.d -0.137088 -7.294568
+recip.d -0.000003 -347856.475000
+recip.d 0.000003 356047.560000
+recip.d -1.000000 -1.000000
+recip.d 0.043403 23.040000
diff --git a/main/none/tests/mips32/FPUarithmetic.stdout.exp-mips32 b/main/none/tests/mips32/FPUarithmetic.stdout.exp-mips32
new file mode 100644
index 0000000..c33b2b2
--- /dev/null
+++ b/main/none/tests/mips32/FPUarithmetic.stdout.exp-mips32
@@ -0,0 +1,337 @@
+-------------------------- test FPU Arithmetic Operations --------------------------
+abs.s 0.000000 0.000000
+abs.s 456.248962 456.248962
+abs.s 3.000000 3.000000
+abs.s 1.000000 -1.000000
+abs.s 1384.599976 1384.599976
+abs.s 7.294568 -7.294568
+abs.s 1000000000.000000 1000000000.000000
+abs.s 5786.470215 -5786.470215
+abs.s 1752.000000 1752.000000
+abs.s 0.002457 0.002457
+abs.s 0.000000 0.000000
+abs.s 248562.765625 -248562.765625
+abs.s 45786.476562 -45786.476562
+abs.s 456.248962 456.248962
+abs.s 34.000462 34.000462
+abs.s 45786.476562 45786.476562
+abs.s 1752065.000000 1752065.000000
+abs.s 107.000000 107.000000
+abs.s 45667.238281 -45667.238281
+abs.s 7.294568 -7.294568
+abs.s 347856.468750 -347856.468750
+abs.s 356047.562500 356047.562500
+abs.s 1.000000 -1.000000
+abs.s 23.040001 23.040001
+abs.d 0.000000 0.000000
+abs.d 456.248956 456.248956
+abs.d 3.000000 3.000000
+abs.d 1.000000 -1.000000
+abs.d 1384.600000 1384.600000
+abs.d 7.294568 -7.294568
+abs.d 1000000000.000000 1000000000.000000
+abs.d 5786.470000 -5786.470000
+abs.d 1752.000000 1752.000000
+abs.d 0.002458 0.002458
+abs.d 0.000000 0.000000
+abs.d 248562.760000 -248562.760000
+abs.d 45786.476000 -45786.476000
+abs.d 456.248956 456.248956
+abs.d 34.000460 34.000460
+abs.d 45786.476000 45786.476000
+abs.d 1752065.000000 1752065.000000
+abs.d 107.000000 107.000000
+abs.d 45667.240000 -45667.240000
+abs.d 7.294568 -7.294568
+abs.d 347856.475000 -347856.475000
+abs.d 356047.560000 356047.560000
+abs.d 1.000000 -1.000000
+abs.d 23.040000 23.040000
+add.s -45786.476562 0.000000 -45786.476562
+add.s 912.497925 456.248962 456.248962
+add.s 37.000462 3.000000 34.000462
+add.s 45785.476562 -1.000000 45786.476562
+add.s 1753449.625000 1384.599976 1752065.000000
+add.s 99.705429 -7.294568 107.000000
+add.s 999954304.000000 1000000000.000000 -45667.238281
+add.s -5793.764648 -5786.470215 -7.294568
+add.s -346104.468750 1752.000000 -347856.468750
+add.s 356047.562500 0.002457 356047.562500
+add.s -1.000000 0.000000 -1.000000
+add.s -248539.718750 -248562.765625 23.040001
+add.s -45786.476562 -45786.476562 0.000000
+add.s 912.497925 456.248962 456.248962
+add.s 37.000462 34.000462 3.000000
+add.s 45785.476562 45786.476562 -1.000000
+add.s 1753449.625000 1752065.000000 1384.599976
+add.s 99.705429 107.000000 -7.294568
+add.s 999954304.000000 -45667.238281 1000000000.000000
+add.s -5793.764648 -7.294568 -5786.470215
+add.s -346104.468750 -347856.468750 1752.000000
+add.s 356047.562500 356047.562500 0.002457
+add.s -1.000000 -1.000000 0.000000
+add.s -248539.718750 23.040001 -248562.765625
+add.d -45786.476000 0.000000 -45786.476000
+add.d 912.497912 456.248956 456.248956
+add.d 37.000460 3.000000 34.000460
+add.d 45785.476000 -1.000000 45786.476000
+add.d 1753449.600000 1384.600000 1752065.000000
+add.d 99.705432 -7.294568 107.000000
+add.d 999954332.760000 1000000000.000000 -45667.240000
+add.d -5793.764568 -5786.470000 -7.294568
+add.d -346104.475000 1752.000000 -347856.475000
+add.d 356047.562458 0.002458 356047.560000
+add.d -1.000000 0.000000 -1.000000
+add.d -248539.720000 -248562.760000 23.040000
+add.d -45786.476000 -45786.476000 0.000000
+add.d 912.497912 456.248956 456.248956
+add.d 37.000460 34.000460 3.000000
+add.d 45785.476000 45786.476000 -1.000000
+add.d 1753449.600000 1752065.000000 1384.600000
+add.d 99.705432 107.000000 -7.294568
+add.d 999954332.760000 -45667.240000 1000000000.000000
+add.d -5793.764568 -7.294568 -5786.470000
+add.d -346104.475000 -347856.475000 1752.000000
+add.d 356047.562458 356047.560000 0.002458
+add.d -1.000000 -1.000000 0.000000
+add.d -248539.720000 23.040000 -248562.760000
+div.s -0.000000 0.000000 -45786.476562
+div.s 1.000000 456.248962 456.248962
+div.s 0.088234 3.000000 34.000462
+div.s -0.000022 -1.000000 45786.476562
+div.s 0.000790 1384.599976 1752065.000000
+div.s -0.068174 -7.294568 107.000000
+div.s -21897.535156 1000000000.000000 -45667.238281
+div.s 793.257446 -5786.470215 -7.294568
+div.s -0.005037 1752.000000 -347856.468750
+div.s 0.000000 0.002457 356047.562500
+div.s -0.000000 0.000000 -1.000000
+div.s -10788.314453 -248562.765625 23.040001
+div.s -inf -45786.476562 0.000000
+div.s 1.000000 456.248962 456.248962
+div.s 11.333488 34.000462 3.000000
+div.s -45786.476562 45786.476562 -1.000000
+div.s 1265.394409 1752065.000000 1384.599976
+div.s -14.668450 107.000000 -7.294568
+div.s -0.000046 -45667.238281 1000000000.000000
+div.s 0.001261 -7.294568 -5786.470215
+div.s -198.548218 -347856.468750 1752.000000
+div.s 144882016.000000 356047.562500 0.002457
+div.s -100000000.000000 -1.000000 0.000000
+div.s -0.000093 23.040001 -248562.765625
+div.d -0.000000 0.000000 -45786.476000
+div.d 1.000000 456.248956 456.248956
+div.d 0.088234 3.000000 34.000460
+div.d -0.000022 -1.000000 45786.476000
+div.d 0.000790 1384.600000 1752065.000000
+div.d -0.068174 -7.294568 107.000000
+div.d -21897.535301 1000000000.000000 -45667.240000
+div.d 793.257437 -5786.470000 -7.294568
+div.d -0.005037 1752.000000 -347856.475000
+div.d 0.000000 0.002458 356047.560000
+div.d -0.000000 0.000000 -1.000000
+div.d -10788.314236 -248562.760000 23.040000
+div.d -inf -45786.476000 0.000000
+div.d 1.000000 456.248956 456.248956
+div.d 11.333487 34.000460 3.000000
+div.d -45786.476000 45786.476000 -1.000000
+div.d 1265.394338 1752065.000000 1384.600000
+div.d -14.668450 107.000000 -7.294568
+div.d -0.000046 -45667.240000 1000000000.000000
+div.d 0.001261 -7.294568 -5786.470000
+div.d -198.548216 -347856.475000 1752.000000
+div.d 144882018.311292 356047.560000 0.002458
+div.d -100000000.000000 -1.000000 0.000000
+div.d -0.000093 23.040000 -248562.760000
+mul.s -0.000000 0.000000 -45786.476562
+mul.s 208163.109375 456.248962 456.248962
+mul.s 102.001389 3.000000 34.000462
+mul.s -45786.476562 -1.000000 45786.476562
+mul.s 2425909248.000000 1384.599976 1752065.000000
+mul.s -780.518738 -7.294568 107.000000
+mul.s -45667238019072.000000 1000000000.000000 -45667.238281
+mul.s 42209.796875 -5786.470215 -7.294568
+mul.s -609444544.000000 1752.000000 -347856.468750
+mul.s 874.986877 0.002457 356047.562500
+mul.s -0.000000 0.000000 -1.000000
+mul.s -5726886.500000 -248562.765625 23.040001
+mul.s -0.000000 -45786.476562 0.000000
+mul.s 208163.109375 456.248962 456.248962
+mul.s 102.001389 34.000462 3.000000
+mul.s -45786.476562 45786.476562 -1.000000
+mul.s 2425909248.000000 1752065.000000 1384.599976
+mul.s -780.518738 107.000000 -7.294568
+mul.s -45667238019072.000000 -45667.238281 1000000000.000000
+mul.s 42209.796875 -7.294568 -5786.470215
+mul.s -609444544.000000 -347856.468750 1752.000000
+mul.s 874.986877 356047.562500 0.002457
+mul.s -0.000000 -1.000000 0.000000
+mul.s -5726886.500000 23.040001 -248562.765625
+mul.d -0.000000 0.000000 -45786.476000
+mul.d 208163.110034 456.248956 456.248956
+mul.d 102.001380 3.000000 34.000460
+mul.d -45786.476000 -1.000000 45786.476000
+mul.d 2425909199.000000 1384.600000 1752065.000000
+mul.d -780.518733 -7.294568 107.000000
+mul.d -45667240000000.000000 1000000000.000000 -45667.240000
+mul.d 42209.796580 -5786.470000 -7.294568
+mul.d -609444544.200000 1752.000000 -347856.475000
+mul.d 874.986879 0.002458 356047.560000
+mul.d -0.000000 0.000000 -1.000000
+mul.d -5726885.990400 -248562.760000 23.040000
+mul.d -0.000000 -45786.476000 0.000000
+mul.d 208163.110034 456.248956 456.248956
+mul.d 102.001380 34.000460 3.000000
+mul.d -45786.476000 45786.476000 -1.000000
+mul.d 2425909199.000000 1752065.000000 1384.600000
+mul.d -780.518733 107.000000 -7.294568
+mul.d -45667240000000.000000 -45667.240000 1000000000.000000
+mul.d 42209.796580 -7.294568 -5786.470000
+mul.d -609444544.200000 -347856.475000 1752.000000
+mul.d 874.986879 356047.560000 0.002458
+mul.d -0.000000 -1.000000 0.000000
+mul.d -5726885.990400 23.040000 -248562.760000
+neg.s -0.000000 0.000000
+neg.s -456.248962 456.248962
+neg.s -3.000000 3.000000
+neg.s 1.000000 -1.000000
+neg.s -1384.599976 1384.599976
+neg.s 7.294568 -7.294568
+neg.s -1000000000.000000 1000000000.000000
+neg.s 5786.470215 -5786.470215
+neg.s -1752.000000 1752.000000
+neg.s -0.002457 0.002457
+neg.s -0.000000 0.000000
+neg.s 248562.765625 -248562.765625
+neg.s 45786.476562 -45786.476562
+neg.s -456.248962 456.248962
+neg.s -34.000462 34.000462
+neg.s -45786.476562 45786.476562
+neg.s -1752065.000000 1752065.000000
+neg.s -107.000000 107.000000
+neg.s 45667.238281 -45667.238281
+neg.s 7.294568 -7.294568
+neg.s 347856.468750 -347856.468750
+neg.s -356047.562500 356047.562500
+neg.s 1.000000 -1.000000
+neg.s -23.040001 23.040001
+neg.d -0.000000 0.000000
+neg.d -456.248956 456.248956
+neg.d -3.000000 3.000000
+neg.d 1.000000 -1.000000
+neg.d -1384.600000 1384.600000
+neg.d 7.294568 -7.294568
+neg.d -1000000000.000000 1000000000.000000
+neg.d 5786.470000 -5786.470000
+neg.d -1752.000000 1752.000000
+neg.d -0.002458 0.002458
+neg.d -0.000000 0.000000
+neg.d 248562.760000 -248562.760000
+neg.d 45786.476000 -45786.476000
+neg.d -456.248956 456.248956
+neg.d -34.000460 34.000460
+neg.d -45786.476000 45786.476000
+neg.d -1752065.000000 1752065.000000
+neg.d -107.000000 107.000000
+neg.d 45667.240000 -45667.240000
+neg.d 7.294568 -7.294568
+neg.d 347856.475000 -347856.475000
+neg.d -356047.560000 356047.560000
+neg.d 1.000000 -1.000000
+neg.d -23.040000 23.040000
+sqrt.s 0.000000 0.000000
+sqrt.s 21.359985 456.248962
+sqrt.s 1.732051 3.000000
+sqrt.s nan -1.000000
+sqrt.s 37.210213 1384.599976
+sqrt.s nan -7.294568
+sqrt.s 31622.777344 1000000000.000000
+sqrt.s nan -5786.470215
+sqrt.s 41.856899 1752.000000
+sqrt.s 0.049573 0.002457
+sqrt.s 0.000100 0.000000
+sqrt.s nan -248562.765625
+sqrt.s nan -45786.476562
+sqrt.s 21.359985 456.248962
+sqrt.s 5.830991 34.000462
+sqrt.s 213.977753 45786.476562
+sqrt.s 1323.655884 1752065.000000
+sqrt.s 10.344080 107.000000
+sqrt.s nan -45667.238281
+sqrt.s nan -7.294568
+sqrt.s nan -347856.468750
+sqrt.s 596.697205 356047.562500
+sqrt.s nan -1.000000
+sqrt.s 4.800000 23.040001
+sqrt.d 0.000000 0.000000
+sqrt.d 21.359985 456.248956
+sqrt.d 1.732051 3.000000
+sqrt.d nan -1.000000
+sqrt.d 37.210214 1384.600000
+sqrt.d nan -7.294568
+sqrt.d 31622.776602 1000000000.000000
+sqrt.d nan -5786.470000
+sqrt.d 41.856899 1752.000000
+sqrt.d 0.049573 0.002458
+sqrt.d 0.000100 0.000000
+sqrt.d nan -248562.760000
+sqrt.d nan -45786.476000
+sqrt.d 21.359985 456.248956
+sqrt.d 5.830991 34.000460
+sqrt.d 213.977747 45786.476000
+sqrt.d 1323.655922 1752065.000000
+sqrt.d 10.344080 107.000000
+sqrt.d nan -45667.240000
+sqrt.d nan -7.294568
+sqrt.d nan -347856.475000
+sqrt.d 596.697210 356047.560000
+sqrt.d nan -1.000000
+sqrt.d 4.800000 23.040000
+sub.s 45786.476562 0.000000 -45786.476562
+sub.s 0.000000 456.248962 456.248962
+sub.s -31.000462 3.000000 34.000462
+sub.s -45787.476562 -1.000000 45786.476562
+sub.s -1750680.375000 1384.599976 1752065.000000
+sub.s -114.294571 -7.294568 107.000000
+sub.s 1000045696.000000 1000000000.000000 -45667.238281
+sub.s -5779.175781 -5786.470215 -7.294568
+sub.s 349608.468750 1752.000000 -347856.468750
+sub.s -356047.562500 0.002457 356047.562500
+sub.s 1.000000 0.000000 -1.000000
+sub.s -248585.812500 -248562.765625 23.040001
+sub.s -45786.476562 -45786.476562 0.000000
+sub.s 0.000000 456.248962 456.248962
+sub.s 31.000462 34.000462 3.000000
+sub.s 45787.476562 45786.476562 -1.000000
+sub.s 1750680.375000 1752065.000000 1384.599976
+sub.s 114.294571 107.000000 -7.294568
+sub.s -1000045696.000000 -45667.238281 1000000000.000000
+sub.s 5779.175781 -7.294568 -5786.470215
+sub.s -349608.468750 -347856.468750 1752.000000
+sub.s 356047.562500 356047.562500 0.002457
+sub.s -1.000000 -1.000000 0.000000
+sub.s 248585.812500 23.040001 -248562.765625
+sub.d 45786.476000 0.000000 -45786.476000
+sub.d 0.000000 456.248956 456.248956
+sub.d -31.000460 3.000000 34.000460
+sub.d -45787.476000 -1.000000 45786.476000
+sub.d -1750680.400000 1384.600000 1752065.000000
+sub.d -114.294568 -7.294568 107.000000
+sub.d 1000045667.240000 1000000000.000000 -45667.240000
+sub.d -5779.175432 -5786.470000 -7.294568
+sub.d 349608.475000 1752.000000 -347856.475000
+sub.d -356047.557542 0.002458 356047.560000
+sub.d 1.000000 0.000000 -1.000000
+sub.d -248585.800000 -248562.760000 23.040000
+sub.d -45786.476000 -45786.476000 0.000000
+sub.d 0.000000 456.248956 456.248956
+sub.d 31.000460 34.000460 3.000000
+sub.d 45787.476000 45786.476000 -1.000000
+sub.d 1750680.400000 1752065.000000 1384.600000
+sub.d 114.294568 107.000000 -7.294568
+sub.d -1000045667.240000 -45667.240000 1000000000.000000
+sub.d 5779.175432 -7.294568 -5786.470000
+sub.d -349608.475000 -347856.475000 1752.000000
+sub.d 356047.557542 356047.560000 0.002458
+sub.d -1.000000 -1.000000 0.000000
+sub.d 248585.800000 23.040000 -248562.760000
diff --git a/main/none/tests/mips32/FPUarithmetic.vgtest b/main/none/tests/mips32/FPUarithmetic.vgtest
new file mode 100644
index 0000000..c33c448
--- /dev/null
+++ b/main/none/tests/mips32/FPUarithmetic.vgtest
@@ -0,0 +1,2 @@
+prog: FPUarithmetic
+vgopts: -q
diff --git a/main/none/tests/mips32/LoadStore.c b/main/none/tests/mips32/LoadStore.c
new file mode 100644
index 0000000..6b9280f
--- /dev/null
+++ b/main/none/tests/mips32/LoadStore.c
@@ -0,0 +1,353 @@
+#include <stdio.h>
+
+unsigned int mem[] = {
+ 0x121f1e1f, 0, 3, -1,
+ 0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a,
+ 0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a,
+ 0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+};
+
+unsigned int mem1[] = {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0xffffffff, 0, 0, 0,
+ 0, 0, 0, 0
+};
+
+unsigned int mem2[] = {
+0x0000e680, 0x00010700, 0x0000e7dc, 0x0000b0d0,
+0x2ab05fd0, 0x0000b6a0, 0x0000be80, 0x0000de10,
+0x0000df20, 0x2ab05fe0, 0x0000dfd0, 0x00010300
+};
+
+// sb $t0, 0($t1)
+#define TESTINST1(instruction, RTval, offset, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS", %1\n\t" \
+ "li $" #RT", " #RTval"\n\t" \
+ instruction "\n\t" \
+ "lw %0, "#offset"($"#RS")\n\t" \
+ : "=&r" (out) \
+ : "r" (mem1), "r" (RTval) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: RTval: 0x%x, out: 0x%x\n", \
+ instruction, RTval, out); \
+ out = 0; \
+ __asm__ volatile( \
+ "move $" #RS", %1\n\t" \
+ "li $" #RT", " #RTval"\n\t" \
+ instruction "\n\t" \
+ "lw %0, "#offset"($"#RS")\n\t" \
+ : "=&r" (out) \
+ : "r" (mem), "r" (RTval) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: RTval: 0x%x, out: 0x%x\n", \
+ instruction, RTval, out); \
+}
+
+// swl $t0, 3($t1)
+// swr $t0, 0($t1)
+#define TESTINSTsw(RTval, offset, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS", %1\n\t" \
+ "addiu $"#RS", $"#RS", "#offset"\n\t" \
+ "li $" #RT", " #RTval"\n\t" \
+ "swl $t0, 3($t1) \n\t" \
+ "swr $t0, 0($t1) \n\t" \
+ "lw %0, 0($"#RS")\n\t" \
+ : "=&r" (out) \
+ : "r" (mem2), "r" (RTval) \
+ : #RT, #RS, "cc", "memory" \
+ ); \
+ printf("swl $t0, 3($t1)\nswr $t0, 0($t1)\n :: RTval: 0x%x, out: 0x%x\n", \
+ RTval, out); \
+}
+
+void ppMem(unsigned int* mem, int len)
+{
+ int i;
+ printf("MEM1:\n");
+ for (i = 0; i < len; i=i+4)
+ {
+ printf("0x%x, 0x%x, 0x%x, 0x%x\n", mem[i], mem[i+1], mem[i+2], mem[i+3]);
+ mem[i] = 0;
+ mem[i+1] = 0;
+ mem[i+2] = 0;
+ mem[i+3] = 0;
+ if (i == 2)
+ {
+ mem[i] = 0xffffffff;
+ mem[i+1] = 0;
+ mem[i+2] = 0;
+ mem[i+3] = 0;
+ }
+ }
+}
+
+void ppMem1(unsigned int* mem, int len)
+{
+ int i;
+ printf("MEM:\n");
+ for (i = 0; i < len; i=i+4)
+ {
+ printf("0x%x, 0x%x, 0x%x, 0x%x\n", mem[i], mem[i+1], mem[i+2], mem[i+3]);
+ }
+ mem[0] = 0x121f1e1f;
+ mem[1] = 0;
+ mem[2] = 3;
+ mem[3] = -1;
+ mem[4] = 0x232f2e2f;
+ mem[5] = 0x242c2b2b;
+ mem[6] = 0x252a2e2b;
+ mem[7] = 0x262d2d2a;
+ mem[8] = 0x3f343f3e;
+ mem[9] = 0x3e353d3c;
+ mem[10] = 0x363a3c3b;
+ mem[11] = 0x3b373b3a;
+ mem[12] = 0x454f4e45;
+ mem[13] = 0x4e464d46;
+ mem[14] = 0x474d474c;
+ mem[15] = 0x4a484a4c;
+}
+
+void ppMem0(unsigned int* mem, int len)
+{
+ int i;
+ printf("MEM:\n");
+ for (i = 0; i < len; i=i+4)
+ {
+ printf("0x%x, 0x%x, 0x%x, 0x%x\n", mem[i], mem[i+1], mem[i+2], mem[i+3]);
+ }
+
+ mem[0] = 0x0000e680;
+ mem[1] = 0x00010700;
+ mem[2] = 0x0000e7dc;
+ mem[3] = 0x0000b0d0;
+ mem[4] = 0x2ab05fd0;
+ mem[5] = 0x0000b6a0;
+ mem[6] = 0x0000be80;
+ mem[7] = 0x0000de10;
+ mem[8] = 0x0000df20;
+ mem[9] = 0x2ab05fe0;
+ mem[10] = 0x0000dfd0;
+ mem[11] = 0x00010300;
+}
+
+int main()
+{
+ printf("sb\n");
+ TESTINST1("sb $t0, 0($t1)", 0, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 0x7fffffff, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 0x80000000, 0, t0, t1);
+ TESTINST1("sb $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("sb $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("sb $t0, 10($t1)", 0x7fffffff, 10, t0, t1);
+ TESTINST1("sb $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("sb $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sb $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sb $t0, 32($t1)", 0xffffffff, 32, t0, t1);
+ TESTINST1("sb $t0, 36($t1)", 0xffffffff, 36, t0, t1);
+ TESTINST1("sb $t0, 40($t1)", 0x31415927, 40, t0, t1);
+ TESTINST1("sb $t0, 44($t1)", 0x7fffffff, 44, t0, t1);
+ TESTINST1("sb $t0, 48($t1)", 0x80000000, 48, t0, t1);
+ TESTINST1("sb $t0, 52($t1)", 655, 52, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("sh\n");
+ TESTINST1("sh $t0, 0($t1)", 0, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 0x7fffffff, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 0x80000000, 0, t0, t1);
+ TESTINST1("sh $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("sh $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("sh $t0, 10($t1)", 0x7fffffff, 10, t0, t1);
+ TESTINST1("sh $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("sh $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sh $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sh $t0, 32($t1)", 0xffffffff, 32, t0, t1);
+ TESTINST1("sh $t0, 36($t1)", 0xffffffff, 36, t0, t1);
+ TESTINST1("sh $t0, 40($t1)", 0x31415927, 40, t0, t1);
+ TESTINST1("sh $t0, 44($t1)", 0x7fffffff, 44, t0, t1);
+ TESTINST1("sh $t0, 48($t1)", 0x80000000, 48, t0, t1);
+ TESTINST1("sh $t0, 52($t1)", 655, 52, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("sw\n");
+ TESTINST1("sw $t0, 0($t1)", 0, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 0x7fffffff, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 0x80000000, 0, t0, t1);
+ TESTINST1("sw $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("sw $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("sw $t0, 10($t1)", 0x7fffffff, 10, t0, t1);
+ TESTINST1("sw $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("sw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sw $t0, 32($t1)", 0xffffffff, 32, t0, t1);
+ TESTINST1("sw $t0, 36($t1)", 0xffffffff, 36, t0, t1);
+ TESTINST1("sw $t0, 40($t1)", 0x31415927, 40, t0, t1);
+ TESTINST1("sw $t0, 44($t1)", 0x7fffffff, 44, t0, t1);
+ TESTINST1("sw $t0, 48($t1)", 0x80000000, 48, t0, t1);
+ TESTINST1("sw $t0, 52($t1)", 655, 52, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("swl\n");
+ TESTINST1("swl $t0, 0($t1)", 0, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 0x7fffffff, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 0x80000000, 0, t0, t1);
+ TESTINST1("swl $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("swl $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("swl $t0, 10($t1)", 0x7fffffff, 10, t0, t1);
+ TESTINST1("swl $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("swl $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("swl $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("swl $t0, 32($t1)", 0xffffffff, 32, t0, t1);
+ TESTINST1("swl $t0, 36($t1)", 0xffffffff, 36, t0, t1);
+ TESTINST1("swl $t0, 40($t1)", 0x31415927, 40, t0, t1);
+ TESTINST1("swl $t0, 44($t1)", 0x7fffffff, 44, t0, t1);
+ TESTINST1("swl $t0, 48($t1)", 0x80000000, 48, t0, t1);
+ TESTINST1("swl $t0, 52($t1)", 655, 52, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("swr\n");
+ TESTINST1("swr $t0, 0($t1)", 0, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 0x7fffffff, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 0x80000000, 0, t0, t1);
+ TESTINST1("swr $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("swr $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("swr $t0, 10($t1)", 0x7fffffff, 10, t0, t1);
+ TESTINST1("swr $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("swr $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("swr $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("swr $t0, 32($t1)", 0xffffffff, 32, t0, t1);
+ TESTINST1("swr $t0, 36($t1)", 0xffffffff, 36, t0, t1);
+ TESTINST1("swr $t0, 40($t1)", 0x31415927, 40, t0, t1);
+ TESTINST1("swr $t0, 44($t1)", 0x7fffffff, 44, t0, t1);
+ TESTINST1("swr $t0, 48($t1)", 0x80000000, 48, t0, t1);
+ TESTINST1("swr $t0, 52($t1)", 655, 52, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("ulw\n");
+ TESTINST1("ulw $t0, 0($t1)", 0, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x7fffffff, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x80000000, 0, t0, t1);
+ TESTINST1("ulw $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("ulw $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("ulw $t0, 10($t1)", 0x7fffffff, 10, t0, t1);
+ TESTINST1("ulw $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("ulw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("ulw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("ulw $t0, 32($t1)", 0xffffffff, 32, t0, t1);
+ TESTINST1("ulw $t0, 36($t1)", 0xffffffff, 36, t0, t1);
+ TESTINST1("ulw $t0, 40($t1)", 0x31415927, 40, t0, t1);
+ TESTINST1("ulw $t0, 44($t1)", 0x7fffffff, 44, t0, t1);
+ TESTINST1("ulw $t0, 48($t1)", 0x80000000, 48, t0, t1);
+ TESTINST1("ulw $t0, 52($t1)", 655, 52, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("usw\n");
+ TESTINST1("usw $t0, 0($t1)", 0, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x7fffffff, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x80000000, 0, t0, t1);
+ TESTINST1("usw $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("usw $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("usw $t0, 10($t1)", 0x7fffffff, 10, t0, t1);
+ TESTINST1("usw $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("usw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("usw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("usw $t0, 32($t1)", 0xffffffff, 32, t0, t1);
+ TESTINST1("usw $t0, 36($t1)", 0xffffffff, 36, t0, t1);
+ TESTINST1("usw $t0, 40($t1)", 0x31415927, 40, t0, t1);
+ TESTINST1("usw $t0, 44($t1)", 0x7fffffff, 44, t0, t1);
+ TESTINST1("usw $t0, 48($t1)", 0x80000000, 48, t0, t1);
+ TESTINST1("usw $t0, 52($t1)", 655, 52, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("swl $t0, 3($t0)\nswr $t0, 0($t0)\n");
+ TESTINSTsw(0x4853000, 0, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x4853000, 4, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x4863700, 8, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x48aedd0, 12, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x2aaee700, 16, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x2aaee7ff, 20, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x2aaeffff, 24, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x4863700, 28, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x2aaee700, 32, t0, t1);
+ ppMem0(mem2, 12);
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/mips32/LoadStore.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/mips32/LoadStore.stderr.exp
diff --git a/main/none/tests/mips32/LoadStore.stdout.exp b/main/none/tests/mips32/LoadStore.stdout.exp
new file mode 100644
index 0000000..a26c8c5
--- /dev/null
+++ b/main/none/tests/mips32/LoadStore.stdout.exp
@@ -0,0 +1,464 @@
+sb
+sb $t0, 0($t1) :: RTval: 0x0, out: 0x0
+sb $t0, 0($t1) :: RTval: 0x0, out: 0x121f1e00
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e27
+sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff
+sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121f1eff
+sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f1e00
+sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x1200
+sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff
+sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x300ff
+sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff
+sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff00ff
+sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff
+sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x12001e27
+sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x12001e00
+sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f
+sb $t0, 0($t1) :: RTval: 0x28f, out: 0x12001e8f
+sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71
+sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x12001e71
+sb $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sb $t0, 0($t1) :: RTval: 0xf, out: 0x12001e0f
+sb $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sb $t0, 0($t1) :: RTval: 0x1, out: 0x12001e01
+sb $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sb $t0, 0($t1) :: RTval: 0x35, out: 0x12001e35
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x12ff
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x12ff
+sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f343fff
+sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff
+sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e353dff
+sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x27
+sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a3c27
+sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff
+sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b373bff
+sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f4e00
+sb $t0, 52($t1) :: RTval: 0x28f, out: 0x8f
+sb $t0, 52($t1) :: RTval: 0x28f, out: 0x4e464d8f
+MEM1:
+0xff0035, 0xff0000, 0xff00ff, 0x0
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xff, 0x27, 0xff
+0x0, 0x8f, 0x0, 0x0
+MEM:
+0x12ff1e35, 0xff0000, 0xff00ff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0x3f343fff, 0x3e353dff, 0x363a3c27, 0x3b373bff
+0x454f4e00, 0x4e464d8f, 0x474d474c, 0x4a484a4c
+sh
+sh $t0, 0($t1) :: RTval: 0x0, out: 0x0
+sh $t0, 0($t1) :: RTval: 0x0, out: 0x121f0000
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x5927
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f5927
+sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xffff
+sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121fffff
+sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f0000
+sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
+sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3ffff
+sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff
+sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffffffff
+sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x5927
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x5927
+sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd71
+sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd71
+sh $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sh $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sh $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sh $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sh $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sh $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
+sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffff
+sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f34ffff
+sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffff
+sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e35ffff
+sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x5927
+sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a5927
+sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xffff
+sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b37ffff
+sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f0000
+sh $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+sh $t0, 52($t1) :: RTval: 0x28f, out: 0x4e46028f
+MEM1:
+0xffff0035, 0xffff0000, 0xffffffff, 0x0
+0x0, 0x0, 0x0, 0x0
+0xffff, 0xffff, 0x5927, 0xffff
+0x0, 0x28f, 0x0, 0x0
+MEM:
+0xffff0035, 0xffff0000, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0x3f34ffff, 0x3e35ffff, 0x363a5927, 0x3b37ffff
+0x454f0000, 0x4e46028f, 0x474d474c, 0x4a484a4c
+sw
+sw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+sw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff0035, 0xffffffff, 0xffffffff, 0x7fff
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x0, 0x0
+MEM:
+0xffff0035, 0xffffffff, 0xffffffff, 0xffff7fff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x474d474c, 0x4a484a4c
+swl
+swl $t0, 0($t1) :: RTval: 0x0, out: 0x0
+swl $t0, 0($t1) :: RTval: 0x0, out: 0x121f1e00
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e31
+swl $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7f
+swl $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121f1e7f
+swl $t0, 0($t1) :: RTval: 0x80000000, out: 0x80
+swl $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f1e80
+swl $t0, 2($t1) :: RTval: 0x80000000, out: 0x80
+swl $t0, 2($t1) :: RTval: 0x80000000, out: 0x1280
+swl $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7f
+swl $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3007f
+swl $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7f
+swl $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff007f
+swl $t0, 8($t1) :: RTval: 0xffffffff, out: 0x7fffff
+swl $t0, 8($t1) :: RTval: 0xffffffff, out: 0x7fffff
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x800031
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x12800031
+swl $t0, 0($t1) :: RTval: 0xdd00000, out: 0x80000d
+swl $t0, 0($t1) :: RTval: 0xdd00000, out: 0x1280000d
+swl $t0, 0($t1) :: RTval: 0x28f, out: 0x800000
+swl $t0, 0($t1) :: RTval: 0x28f, out: 0x12800000
+swl $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x8000ff
+swl $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x128000ff
+swl $t0, 0($t1) :: RTval: 0xf, out: 0x800000
+swl $t0, 0($t1) :: RTval: 0xf, out: 0x12800000
+swl $t0, 0($t1) :: RTval: 0x1, out: 0x800000
+swl $t0, 0($t1) :: RTval: 0x1, out: 0x12800000
+swl $t0, 0($t1) :: RTval: 0x35, out: 0x800000
+swl $t0, 0($t1) :: RTval: 0x35, out: 0x12800000
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff00ff
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff12ff
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff00ff
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff12ff
+swl $t0, 32($t1) :: RTval: 0xffffffff, out: 0xff
+swl $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f343fff
+swl $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff
+swl $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e353dff
+swl $t0, 40($t1) :: RTval: 0x31415927, out: 0x31
+swl $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a3c31
+swl $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7f
+swl $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b373b7f
+swl $t0, 48($t1) :: RTval: 0x80000000, out: 0x80
+swl $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f4e80
+swl $t0, 52($t1) :: RTval: 0x28f, out: 0x0
+swl $t0, 52($t1) :: RTval: 0x28f, out: 0x4e464d00
+MEM1:
+0xffffff, 0x7fffff, 0x7fffff, 0x0
+0x0, 0x0, 0x0, 0x0
+0xff, 0xff, 0x31, 0x7f
+0x80, 0x0, 0x0, 0x0
+MEM:
+0x12ffffff, 0x7fffff, 0x7fffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0x3f343fff, 0x3e353dff, 0x363a3c31, 0x3b373b7f
+0x454f4e80, 0x4e464d00, 0x474d474c, 0x4a484a4c
+swr
+swr $t0, 0($t1) :: RTval: 0x0, out: 0x0
+swr $t0, 0($t1) :: RTval: 0x0, out: 0x0
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swr $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swr $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swr $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+swr $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+swr $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
+swr $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3ffff
+swr $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff
+swr $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffffffff
+swr $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swr $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+swr $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+swr $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+swr $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+swr $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+swr $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+swr $t0, 0($t1) :: RTval: 0xf, out: 0xf
+swr $t0, 0($t1) :: RTval: 0xf, out: 0xf
+swr $t0, 0($t1) :: RTval: 0x1, out: 0x1
+swr $t0, 0($t1) :: RTval: 0x1, out: 0x1
+swr $t0, 0($t1) :: RTval: 0x35, out: 0x35
+swr $t0, 0($t1) :: RTval: 0x35, out: 0x35
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
+swr $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+swr $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+swr $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swr $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swr $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+swr $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+swr $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+swr $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff0035, 0xffff0000, 0xffffffff, 0x0
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x0, 0x0
+MEM:
+0xffff0035, 0xffff0000, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x474d474c, 0x4a484a4c
+ulw
+ulw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x0, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f1e1f
+ulw $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0x80000000, out: 0x121f
+ulw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x30000
+ulw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+ulw $t0, 8($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 8($t1) :: RTval: 0xffffffff, out: 0x3
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xdd00000, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x28f, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x28f, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xf, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xf, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x1, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x1, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x35, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x35, out: 0x121f1e1f
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x121f
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x121f
+ulw $t0, 32($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f343f3e
+ulw $t0, 36($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e353d3c
+ulw $t0, 40($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a3c3b
+ulw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b373b3a
+ulw $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f4e45
+ulw $t0, 52($t1) :: RTval: 0x28f, out: 0x0
+ulw $t0, 52($t1) :: RTval: 0x28f, out: 0x4e464d46
+MEM1:
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+MEM:
+0x121f1e1f, 0x0, 0x3, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a
+0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+usw
+usw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+usw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+usw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+usw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+usw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+usw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+usw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+usw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+usw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+usw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+usw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff0035, 0xffffffff, 0xffffffff, 0x7fff
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x0, 0x0
+MEM:
+0xffff0035, 0xffffffff, 0xffffffff, 0xffff7fff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x474d474c, 0x4a484a4c
+swl $t0, 3($t0)
+swr $t0, 0($t0)
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4853000, out: 0x4853000
+MEM:
+0x4853000, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4853000, out: 0x4853000
+MEM:
+0xe680, 0x4853000, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4863700, out: 0x4863700
+MEM:
+0xe680, 0x10700, 0x4863700, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x48aedd0, out: 0x48aedd0
+MEM:
+0xe680, 0x10700, 0xe7dc, 0x48aedd0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee700, out: 0x2aaee700
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2aaee700, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee7ff, out: 0x2aaee7ff
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0x2aaee7ff, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaeffff, out: 0x2aaeffff
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0x2aaeffff, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4863700, out: 0x4863700
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0x4863700
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee700, out: 0x2aaee700
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0x2aaee700, 0x2ab05fe0, 0xdfd0, 0x10300
diff --git a/main/none/tests/mips32/LoadStore.stdout.exp-BE b/main/none/tests/mips32/LoadStore.stdout.exp-BE
new file mode 100644
index 0000000..61a5841
--- /dev/null
+++ b/main/none/tests/mips32/LoadStore.stdout.exp-BE
@@ -0,0 +1,464 @@
+sb
+sb $t0, 0($t1) :: RTval: 0x0, out: 0x0
+sb $t0, 0($t1) :: RTval: 0x0, out: 0x1f1e1f
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x271f1e1f
+sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff000000
+sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff1f1e1f
+sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x1f1e1f
+sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x1f0000
+sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000
+sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000
+sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff000000
+sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff03ffff
+sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff00
+sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff03
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x271f001f
+sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x1f001f
+sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000
+sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f1f001f
+sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000
+sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x711f001f
+sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000
+sb $t0, 0($t1) :: RTval: 0xf, out: 0xf1f001f
+sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000
+sb $t0, 0($t1) :: RTval: 0x1, out: 0x11f001f
+sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000
+sb $t0, 0($t1) :: RTval: 0x35, out: 0x351f001f
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000000
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff1f0000
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000000
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff1f0000
+sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0xff343f3e
+sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff000000
+sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff353d3c
+sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x27000000
+sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x273a3c3b
+sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff000000
+sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff373b3a
+sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x4f4e45
+sb $t0, 52($t1) :: RTval: 0x28f, out: 0x8f000000
+sb $t0, 52($t1) :: RTval: 0x28f, out: 0x8f464d46
+MEM1:
+0x3500ff00, 0xff00, 0xff00ff00, 0x0
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xff000000, 0x27000000, 0xff000000
+0x0, 0x8f000000, 0x0, 0x0
+MEM:
+0x351fff1f, 0xff00, 0xff00ff03, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xff343f3e, 0xff353d3c, 0x273a3c3b, 0xff373b3a
+0x4f4e45, 0x8f464d46, 0x474d474c, 0x4a484a4c
+sh
+sh $t0, 0($t1) :: RTval: 0x0, out: 0x0
+sh $t0, 0($t1) :: RTval: 0x0, out: 0x1e1f
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270000
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59271e1f
+sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xffff1e1f
+sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x1e1f
+sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffffffff
+sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270000
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270000
+sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0000
+sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0000
+sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710000
+sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710000
+sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0000
+sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0000
+sh $t0, 0($t1) :: RTval: 0x1, out: 0x10000
+sh $t0, 0($t1) :: RTval: 0x1, out: 0x10000
+sh $t0, 0($t1) :: RTval: 0x35, out: 0x350000
+sh $t0, 0($t1) :: RTval: 0x35, out: 0x350000
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
+sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffff0000
+sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffff3f3e
+sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffff0000
+sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffff3d3c
+sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x59270000
+sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x59273c3b
+sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xffff3b3a
+sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x4e45
+sh $t0, 52($t1) :: RTval: 0x28f, out: 0x28f0000
+sh $t0, 52($t1) :: RTval: 0x28f, out: 0x28f4d46
+MEM1:
+0x35ffff, 0xffff, 0xffffffff, 0x0
+0x0, 0x0, 0x0, 0x0
+0xffff0000, 0xffff0000, 0x59270000, 0xffff0000
+0x0, 0x28f0000, 0x0, 0x0
+MEM:
+0x35ffff, 0xffff, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffff3f3e, 0xffff3d3c, 0x59273c3b, 0xffff3b3a
+0x4e45, 0x28f4d46, 0x474d474c, 0x4a484a4c
+sw
+sw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+sw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff, 0xffff7fff, 0xffffffff, 0xffff0000
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x0, 0x0
+MEM:
+0xffff, 0xffff7fff, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x474d474c, 0x4a484a4c
+swl
+swl $t0, 0($t1) :: RTval: 0x0, out: 0x0
+swl $t0, 0($t1) :: RTval: 0x0, out: 0x0
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swl $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swl $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swl $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fff0000
+swl $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fff0000
+swl $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fff0000
+swl $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swl $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swl $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swl $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+swl $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+swl $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+swl $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+swl $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+swl $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+swl $t0, 0($t1) :: RTval: 0xf, out: 0xf
+swl $t0, 0($t1) :: RTval: 0xf, out: 0xf
+swl $t0, 0($t1) :: RTval: 0x1, out: 0x1
+swl $t0, 0($t1) :: RTval: 0x1, out: 0x1
+swl $t0, 0($t1) :: RTval: 0x35, out: 0x35
+swl $t0, 0($t1) :: RTval: 0x35, out: 0x35
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
+swl $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swl $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swl $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swl $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swl $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+swl $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+swl $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swl $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swl $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+swl $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff, 0x7fff, 0xffffffff, 0x0
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x0, 0x0
+MEM:
+0xffff, 0x7fff, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x474d474c, 0x4a484a4c
+swr
+swr $t0, 0($t1) :: RTval: 0x0, out: 0x0
+swr $t0, 0($t1) :: RTval: 0x0, out: 0x1f1e1f
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x271f1e1f
+swr $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff1f1e1f
+swr $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 0($t1) :: RTval: 0x80000000, out: 0x1f1e1f
+swr $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 2($t1) :: RTval: 0x80000000, out: 0x1f0000
+swr $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff03ffff
+swr $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffff00
+swr $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffff03
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x2700001f
+swr $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+swr $t0, 0($t1) :: RTval: 0xdd00000, out: 0x1f
+swr $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000
+swr $t0, 0($t1) :: RTval: 0x28f, out: 0x8f00001f
+swr $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000
+swr $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x7100001f
+swr $t0, 0($t1) :: RTval: 0xf, out: 0xf000000
+swr $t0, 0($t1) :: RTval: 0xf, out: 0xf00001f
+swr $t0, 0($t1) :: RTval: 0x1, out: 0x1000000
+swr $t0, 0($t1) :: RTval: 0x1, out: 0x100001f
+swr $t0, 0($t1) :: RTval: 0x35, out: 0x35000000
+swr $t0, 0($t1) :: RTval: 0x35, out: 0x3500001f
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff00ffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff1fffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff00ffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff1fffff
+swr $t0, 32($t1) :: RTval: 0xffffffff, out: 0xff000000
+swr $t0, 32($t1) :: RTval: 0xffffffff, out: 0xff343f3e
+swr $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff000000
+swr $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff353d3c
+swr $t0, 40($t1) :: RTval: 0x31415927, out: 0x27000000
+swr $t0, 40($t1) :: RTval: 0x31415927, out: 0x273a3c3b
+swr $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff373b3a
+swr $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 48($t1) :: RTval: 0x80000000, out: 0x4f4e45
+swr $t0, 52($t1) :: RTval: 0x28f, out: 0x8f000000
+swr $t0, 52($t1) :: RTval: 0x28f, out: 0x8f464d46
+MEM1:
+0xffffff00, 0xffffff00, 0xffffff00, 0x0
+0x0, 0x0, 0x0, 0x0
+0xff000000, 0xff000000, 0x27000000, 0xff000000
+0x0, 0x8f000000, 0x0, 0x0
+MEM:
+0xffffff1f, 0xffffff00, 0xffffff03, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xff343f3e, 0xff353d3c, 0x273a3c3b, 0xff373b3a
+0x4f4e45, 0x8f464d46, 0x474d474c, 0x4a484a4c
+ulw
+ulw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x0, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f1e1f
+ulw $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0x80000000, out: 0x1e1f0000
+ulw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x3ffff
+ulw $t0, 8($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 8($t1) :: RTval: 0xffffffff, out: 0x3
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xdd00000, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x28f, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x28f, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xf, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xf, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x1, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x1, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x35, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x35, out: 0x121f1e1f
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x1e1f0000
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x1e1f0000
+ulw $t0, 32($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f343f3e
+ulw $t0, 36($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e353d3c
+ulw $t0, 40($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a3c3b
+ulw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b373b3a
+ulw $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f4e45
+ulw $t0, 52($t1) :: RTval: 0x28f, out: 0x0
+ulw $t0, 52($t1) :: RTval: 0x28f, out: 0x4e464d46
+MEM1:
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+MEM:
+0x121f1e1f, 0x0, 0x3, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a
+0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+usw
+usw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+usw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+usw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+usw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+usw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+usw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+usw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+usw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+usw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+usw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+usw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff, 0xffff7fff, 0xffffffff, 0xffff0000
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x0, 0x0
+MEM:
+0xffff, 0xffff7fff, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x474d474c, 0x4a484a4c
+swl $t0, 3($t0)
+swr $t0, 0($t0)
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4853000, out: 0xe604
+MEM:
+0xe604, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4853000, out: 0x10704
+MEM:
+0xe680, 0x10704, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4863700, out: 0xe704
+MEM:
+0xe680, 0x10700, 0xe704, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x48aedd0, out: 0xd000b004
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xd000b004
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee700, out: 0xb05f2a
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0xb05f2a, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee7ff, out: 0xff00b62a
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xff00b62a, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaeffff, out: 0xff00be2a
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xff00be2a, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4863700, out: 0xde04
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde04
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee700, out: 0xdf2a
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf2a, 0x2ab05fe0, 0xdfd0, 0x10300
diff --git a/main/none/tests/mips32/LoadStore.vgtest b/main/none/tests/mips32/LoadStore.vgtest
new file mode 100644
index 0000000..9c18752
--- /dev/null
+++ b/main/none/tests/mips32/LoadStore.vgtest
@@ -0,0 +1,2 @@
+prog: LoadStore
+vgopts: -q
diff --git a/main/none/tests/mips32/LoadStore1.c b/main/none/tests/mips32/LoadStore1.c
new file mode 100644
index 0000000..334f213
--- /dev/null
+++ b/main/none/tests/mips32/LoadStore1.c
@@ -0,0 +1,354 @@
+#include <stdio.h>
+
+unsigned int mem[] = {
+ 0x121f1e1f, 0, 3, -1,
+ 0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a,
+ 0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a,
+ 0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+};
+
+unsigned int mem1[] = {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0xffffffff, 0, 0, 0,
+ 0, 0, 0, 0
+};
+
+unsigned int mem2[] = {
+0x0000e680, 0x00010700, 0x0000e7dc, 0x0000b0d0,
+0x2ab05fd0, 0x0000b6a0, 0x0000be80, 0x0000de10,
+0x0000df20, 0x2ab05fe0, 0x0000dfd0, 0x00010300
+};
+
+// sb $t0, 0($t1)
+#define TESTINST1(instruction, RTval, offset, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS", %1\n\t" \
+ "li $" #RT", " #RTval"\n\t" \
+ instruction "\n\t" \
+ "lw %0, "#offset"($"#RS")\n\t" \
+ : "=&r" (out) \
+ : "r" (mem1), "r" (RTval) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: RTval: 0x%x, out: 0x%x\n", \
+ instruction, RTval, out); \
+ out = 0; \
+ __asm__ volatile( \
+ "move $" #RS", %1\n\t" \
+ "li $" #RT", " #RTval"\n\t" \
+ instruction "\n\t" \
+ "lw %0, "#offset"($"#RS")\n\t" \
+ : "=&r" (out) \
+ : "r" (mem), "r" (RTval) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: RTval: 0x%x, out: 0x%x\n", \
+ instruction, RTval, out); \
+}
+
+// swl $t0, 3($t1)
+// swr $t0, 0($t1)
+#define TESTINSTsw(RTval, offset, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS", %1\n\t" \
+ "addiu $"#RS", $"#RS", "#offset"\n\t" \
+ "li $" #RT", " #RTval"\n\t" \
+ "swl $t0, 3($t1) \n\t" \
+ "swr $t0, 0($t1) \n\t" \
+ "lw %0, 0($"#RS")\n\t" \
+ : "=&r" (out) \
+ : "r" (mem2), "r" (RTval) \
+ : #RT, #RS, "cc", "memory" \
+ ); \
+ printf("swl $t0, 3($t1)\nswr $t0, 0($t1)\n :: RTval: 0x%x, out: 0x%x\n", \
+ RTval, out); \
+}
+
+void ppMem(unsigned int* mem, int len)
+{
+ int i;
+ printf("MEM1:\n");
+ for (i = 0; i < len; i=i+4)
+ {
+ printf("0x%x, 0x%x, 0x%x, 0x%x\n", mem[i], mem[i+1], mem[i+2], mem[i+3]);
+ mem[i] = 0;
+ mem[i+1] = 0;
+ mem[i+2] = 0;
+ mem[i+3] = 0;
+ if (i == 2)
+ {
+ mem[i] = 0xffffffff;
+ mem[i+1] = 0;
+ mem[i+2] = 0;
+ mem[i+3] = 0;
+ }
+ }
+}
+
+void ppMem1(unsigned int* mem, int len)
+{
+ int i;
+ printf("MEM:\n");
+ for (i = 0; i < len; i=i+4)
+ {
+ printf("0x%x, 0x%x, 0x%x, 0x%x\n", mem[i], mem[i+1], mem[i+2], mem[i+3]);
+ }
+ mem[0] = 0x121f1e1f;
+ mem[1] = 0;
+ mem[2] = 3;
+ mem[3] = -1;
+ mem[4] = 0x232f2e2f;
+ mem[5] = 0x242c2b2b;
+ mem[6] = 0x252a2e2b;
+ mem[7] = 0x262d2d2a;
+ mem[8] = 0x3f343f3e;
+ mem[9] = 0x3e353d3c;
+ mem[10] = 0x363a3c3b;
+ mem[11] = 0x3b373b3a;
+ mem[12] = 0x454f4e45;
+ mem[13] = 0x4e464d46;
+ mem[14] = 0x474d474c;
+ mem[15] = 0x4a484a4c;
+}
+
+void ppMem0(unsigned int* mem, int len)
+{
+ int i;
+ printf("MEM:\n");
+ for (i = 0; i < len; i=i+4)
+ {
+ printf("0x%x, 0x%x, 0x%x, 0x%x\n", mem[i], mem[i+1], mem[i+2], mem[i+3]);
+ }
+
+ mem[0] = 0x0000e680;
+ mem[1] = 0x00010700;
+ mem[2] = 0x0000e7dc;
+ mem[3] = 0x0000b0d0;
+ mem[4] = 0x2ab05fd0;
+ mem[5] = 0x0000b6a0;
+ mem[6] = 0x0000be80;
+ mem[7] = 0x0000de10;
+ mem[8] = 0x0000df20;
+ mem[9] = 0x2ab05fe0;
+ mem[10] = 0x0000dfd0;
+ mem[11] = 0x00010300;
+}
+
+int main()
+{
+ printf("sb\n");
+ TESTINST1("sb $t0, 3($t1)", 0, 3, t0, t1);
+ TESTINST1("sb $t0, 5($t1)", 0x31415927, 5, t0, t1);
+ TESTINST1("sb $t0, 7($t1)", 0x7fffffff, 7, t0, t1);
+ TESTINST1("sb $t0, 1($t1)", 0x80000000, 1, t0, t1);
+ TESTINST1("sb $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("sb $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("sb $t0, 11($t1)", 0x7fffffff, 11, t0, t1);
+ TESTINST1("sb $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("sb $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("sb $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sb $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sb $t0, 31($t1)", 0xffffffff, 31, t0, t1);
+ TESTINST1("sb $t0, 35($t1)", 0xffffffff, 35, t0, t1);
+ TESTINST1("sb $t0, 41($t1)", 0x31415927, 41, t0, t1);
+ TESTINST1("sb $t0, 42($t1)", 0x7fffffff, 42, t0, t1);
+ TESTINST1("sb $t0, 45($t1)", 0x80000000, 45, t0, t1);
+ TESTINST1("sb $t0, 51($t1)", 655, 51, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("sh\n");
+ TESTINST1("sh $t0, 1($t1)", 0, 1, t0, t1);
+ TESTINST1("sh $t0, 3($t1)", 0x31415927, 3, t0, t1);
+ TESTINST1("sh $t0, 5($t1)", 0x7fffffff, 5, t0, t1);
+ TESTINST1("sh $t0, 7($t1)", 0x80000000, 7, t0, t1);
+ TESTINST1("sh $t0, 9($t1)", 0x80000000, 9, t0, t1);
+ TESTINST1("sh $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("sh $t0, 11($t1)", 0x7fffffff, 11, t0, t1);
+ TESTINST1("sh $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("sh $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("sh $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sh $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sh $t0, 31($t1)", 0xffffffff, 31, t0, t1);
+ TESTINST1("sh $t0, 35($t1)", 0xffffffff, 35, t0, t1);
+ TESTINST1("sh $t0, 41($t1)", 0x31415927, 41, t0, t1);
+ TESTINST1("sh $t0, 47($t1)", 0x7fffffff, 47, t0, t1);
+ TESTINST1("sh $t0, 49($t1)", 0x80000000, 49, t0, t1);
+ TESTINST1("sh $t0, 51($t1)", 655, 51, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("sw\n");
+ TESTINST1("sw $t0, 1($t1)", 0, 1, t0, t1);
+ TESTINST1("sw $t0, 3($t1)", 0x31415927, 3, t0, t1);
+ TESTINST1("sw $t0, 5($t1)", 0x7fffffff, 5, t0, t1);
+ TESTINST1("sw $t0, 7($t1)", 0x80000000, 7, t0, t1);
+ TESTINST1("sw $t0, 9($t1)", 0x80000000, 9, t0, t1);
+ TESTINST1("sw $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("sw $t0, 15($t1)", 0x7fffffff, 11, t0, t1);
+ TESTINST1("sw $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("sw $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("sw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("sw $t0, 31($t1)", 0xffffffff, 31, t0, t1);
+ TESTINST1("sw $t0, 37($t1)", 0xffffffff, 37, t0, t1);
+ TESTINST1("sw $t0, 49($t1)", 0x31415927, 49, t0, t1);
+ TESTINST1("sw $t0, 41($t1)", 0x7fffffff, 41, t0, t1);
+ TESTINST1("sw $t0, 43($t1)", 0x80000000, 43, t0, t1);
+ TESTINST1("sw $t0, 51($t1)", 655, 51, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("swl\n");
+ TESTINST1("swl $t0, 1($t1)", 0, 1, t0, t1);
+ TESTINST1("swl $t0, 3($t1)", 0x31415927, 3, t0, t1);
+ TESTINST1("swl $t0, 5($t1)", 0x7fffffff, 5, t0, t1);
+ TESTINST1("swl $t0, 7($t1)", 0x80000000, 7, t0, t1);
+ TESTINST1("swl $t0, 9($t1)", 0x80000000, 9, t0, t1);
+ TESTINST1("swl $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("swl $t0, 11($t1)", 0x7fffffff, 11, t0, t1);
+ TESTINST1("swl $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("swl $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("swl $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("swl $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("swl $t0, 33($t1)", 0xffffffff, 33, t0, t1);
+ TESTINST1("swl $t0, 35($t1)", 0xffffffff, 35, t0, t1);
+ TESTINST1("swl $t0, 41($t1)", 0x31415927, 41, t0, t1);
+ TESTINST1("swl $t0, 45($t1)", 0x7fffffff, 45, t0, t1);
+ TESTINST1("swl $t0, 49($t1)", 0x80000000, 49, t0, t1);
+ TESTINST1("swl $t0, 51($t1)", 655, 51, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("swr\n");
+ TESTINST1("swr $t0, 1($t1)", 0, 1, t0, t1);
+ TESTINST1("swr $t0, 3($t1)", 0x31415927, 3, t0, t1);
+ TESTINST1("swr $t0, 5($t1)", 0x7fffffff, 5, t0, t1);
+ TESTINST1("swr $t0, 7($t1)", 0x80000000, 7, t0, t1);
+ TESTINST1("swr $t0, 9($t1)", 0x80000000, 9, t0, t1);
+ TESTINST1("swr $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("swr $t0, 11($t1)", 0x7fffffff, 11, t0, t1);
+ TESTINST1("swr $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("swr $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("swr $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("swr $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("swr $t0, 31($t1)", 0xffffffff, 31, t0, t1);
+ TESTINST1("swr $t0, 33($t1)", 0xffffffff, 33, t0, t1);
+ TESTINST1("swr $t0, 45($t1)", 0x31415927, 45, t0, t1);
+ TESTINST1("swr $t0, 47($t1)", 0x7fffffff, 47, t0, t1);
+ TESTINST1("swr $t0, 49($t1)", 0x80000000, 49, t0, t1);
+ TESTINST1("swr $t0, 51($t1)", 655, 51, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("ulw\n");
+ TESTINST1("ulw $t0, 0($t1)", 0, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x7fffffff, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x80000000, 0, t0, t1);
+ TESTINST1("ulw $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("ulw $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("ulw $t0, 10($t1)", 0x7fffffff, 10, t0, t1);
+ TESTINST1("ulw $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("ulw $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("ulw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("ulw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("ulw $t0, 32($t1)", 0xffffffff, 32, t0, t1);
+ TESTINST1("ulw $t0, 36($t1)", 0xffffffff, 36, t0, t1);
+ TESTINST1("ulw $t0, 40($t1)", 0x31415927, 40, t0, t1);
+ TESTINST1("ulw $t0, 44($t1)", 0x7fffffff, 44, t0, t1);
+ TESTINST1("ulw $t0, 48($t1)", 0x80000000, 48, t0, t1);
+ TESTINST1("ulw $t0, 52($t1)", 655, 52, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("usw\n");
+ TESTINST1("usw $t0, 0($t1)", 0, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x7fffffff, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x80000000, 0, t0, t1);
+ TESTINST1("usw $t0, 2($t1)", 0x80000000, 2, t0, t1);
+ TESTINST1("usw $t0, 6($t1)", 0x7fffffff, 6, t0, t1);
+ TESTINST1("usw $t0, 10($t1)", 0x7fffffff, 10, t0, t1);
+ TESTINST1("usw $t0, 8($t1)", -1, 8, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x31415927, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 0x0dd00000, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 655, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", -655, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 15, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 1, 0, t0, t1);
+ TESTINST1("usw $t0, 0($t1)", 53, 0, t0, t1);
+ TESTINST1("usw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("usw $t0, 2($t1)", 0xffffffff, 2, t0, t1);
+ TESTINST1("usw $t0, 32($t1)", 0xffffffff, 32, t0, t1);
+ TESTINST1("usw $t0, 36($t1)", 0xffffffff, 36, t0, t1);
+ TESTINST1("usw $t0, 40($t1)", 0x31415927, 40, t0, t1);
+ TESTINST1("usw $t0, 44($t1)", 0x7fffffff, 44, t0, t1);
+ TESTINST1("usw $t0, 48($t1)", 0x80000000, 48, t0, t1);
+ TESTINST1("usw $t0, 52($t1)", 655, 52, t0, t1);
+ ppMem(mem1, 16);
+ ppMem1(mem, 16);
+
+ printf("swl $t0, 3($t0)\nswr $t0, 0($t0)\n");
+ TESTINSTsw(0x4853000, 0, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x4853000, 4, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x4863700, 8, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x48aedd0, 12, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x2aaee700, 16, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x2aaee7ff, 20, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x2aaeffff, 24, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x4863700, 28, t0, t1);
+ ppMem0(mem2, 12);
+ TESTINSTsw(0x2aaee700, 32, t0, t1);
+ ppMem0(mem2, 12);
+ return 0;
+}
+
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/mips32/LoadStore1.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/mips32/LoadStore1.stderr.exp
diff --git a/main/none/tests/mips32/LoadStore1.stdout.exp b/main/none/tests/mips32/LoadStore1.stdout.exp
new file mode 100644
index 0000000..4e1c961
--- /dev/null
+++ b/main/none/tests/mips32/LoadStore1.stdout.exp
@@ -0,0 +1,464 @@
+sb
+sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
+sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
+sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000
+sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000
+sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000
+sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000
+sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1e0000
+sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27
+sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27
+sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff000000
+sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
+sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
+sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
+sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000
+sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000
+sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000
+sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000
+sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000
+sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000
+sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000
+sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000
+sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000
+sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
+sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xff3f343f
+sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff000000
+sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff3e353d
+sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x27000000
+sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x273c3b3b
+sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff000000
+sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff3b3b37
+sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x3b3a45
+sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f000000
+sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f4e464d
+MEM1:
+0x3500ff00, 0x27ffff, 0xff0000ff, 0x0
+0x0, 0x0, 0x0, 0xff
+0xffffffff, 0x0, 0x27ff00, 0x0
+0x8f, 0x0, 0x0, 0x0
+MEM:
+0x3500ff00, 0x27ffff, 0xff0000ff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff
+0x3f343fff, 0x3e353d3c, 0x3627ff3b, 0x3b003b3a
+0x454f4e8f, 0x4e464d46, 0x474d474c, 0x4a484a4c
+sh
+sh $t0, 1($t1) :: RTval: 0x0, out: 0x0
+sh $t0, 1($t1) :: RTval: 0x0, out: 0x1f00
+sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x59270000
+sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x59270000
+sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x3ff
+sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
+sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffff00ff
+sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffff00ff
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270059
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270059
+sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x59
+sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x59
+sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0059
+sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0059
+sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710059
+sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710059
+sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0059
+sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0059
+sh $t0, 0($t1) :: RTval: 0x1, out: 0x10059
+sh $t0, 0($t1) :: RTval: 0x1, out: 0x10059
+sh $t0, 0($t1) :: RTval: 0x35, out: 0x350059
+sh $t0, 0($t1) :: RTval: 0x35, out: 0x350059
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
+sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff0000
+sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff343f
+sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff0000
+sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff353d
+sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x59270000
+sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x59273b3b
+sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff4f4e
+sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x454e
+sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f0000
+sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f464d
+MEM1:
+0x35ffff, 0x27ffffff, 0xffff00ff, 0xff000000
+0x0, 0x0, 0x0, 0xff
+0xff0000ff, 0xff000000, 0x592700, 0xff
+0xff000002, 0x8f000000, 0x0, 0x0
+MEM:
+0x35ffff, 0x27ffffff, 0xffff00ff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff
+0xff343fff, 0xff353d3c, 0x3659273b, 0x3b373bff
+0xff000002, 0x8f464d46, 0x474d474c, 0x4a484a4c
+sw
+sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
+sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
+sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0x0
+sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0xffff
+sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff, 0xffff7fff, 0xffffffff, 0x7f
+0xffffff00, 0x0, 0x0, 0xff
+0xffffff00, 0xffffff, 0xff7fff80, 0x0
+0x314100, 0x28f00, 0x0, 0x0
+MEM:
+0xffff, 0xffff7fff, 0xffffffff, 0xffff7f
+0xffffff2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff
+0xffffff3e, 0x3effffff, 0xff7fff80, 0x3a
+0x45314100, 0x28f46, 0x474d474c, 0x4a484a4c
+swl
+swl $t0, 1($t1) :: RTval: 0x0, out: 0x0
+swl $t0, 1($t1) :: RTval: 0x0, out: 0x0
+swl $t0, 3($t1) :: RTval: 0x31415927, out: 0x31000000
+swl $t0, 3($t1) :: RTval: 0x31415927, out: 0x31000000
+swl $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffff00
+swl $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffff00
+swl $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 9($t1) :: RTval: 0x80000000, out: 0x800000ff
+swl $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fff0080
+swl $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fff0080
+swl $t0, 11($t1) :: RTval: 0x7fffffff, out: 0x7f000000
+swl $t0, 11($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+swl $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swl $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swl $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+swl $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+swl $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+swl $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+swl $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+swl $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+swl $t0, 0($t1) :: RTval: 0xf, out: 0xf
+swl $t0, 0($t1) :: RTval: 0xf, out: 0xf
+swl $t0, 0($t1) :: RTval: 0x1, out: 0x1
+swl $t0, 0($t1) :: RTval: 0x1, out: 0x1
+swl $t0, 0($t1) :: RTval: 0x35, out: 0x35
+swl $t0, 0($t1) :: RTval: 0x35, out: 0x35
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff007f
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff007f
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff007f
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff007f
+swl $t0, 33($t1) :: RTval: 0xffffffff, out: 0xffffff00
+swl $t0, 33($t1) :: RTval: 0xffffffff, out: 0xffffff3e
+swl $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff000000
+swl $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff3e353d
+swl $t0, 41($t1) :: RTval: 0x31415927, out: 0x31415900
+swl $t0, 41($t1) :: RTval: 0x31415927, out: 0x3141593b
+swl $t0, 45($t1) :: RTval: 0x7fffffff, out: 0x7fffff00
+swl $t0, 45($t1) :: RTval: 0x7fffffff, out: 0x7fffff45
+swl $t0, 49($t1) :: RTval: 0x80000000, out: 0x80000000
+swl $t0, 49($t1) :: RTval: 0x80000000, out: 0x8000004e
+swl $t0, 51($t1) :: RTval: 0x28f, out: 0x0
+swl $t0, 51($t1) :: RTval: 0x28f, out: 0x4e464d
+MEM1:
+0xffff, 0x7f7fff, 0xffffffff, 0x0
+0x0, 0x0, 0x0, 0x0
+0xffffff, 0x0, 0x314159, 0x7fffff
+0x800000, 0x0, 0x0, 0x0
+MEM:
+0xffff, 0x7f7fff, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0x3fffffff, 0x3e353d3c, 0x36314159, 0x3b7fffff
+0x45800000, 0x4e464d46, 0x474d474c, 0x4a484a4c
+swr
+swr $t0, 1($t1) :: RTval: 0x0, out: 0x0
+swr $t0, 1($t1) :: RTval: 0x0, out: 0x1e1f00
+swr $t0, 3($t1) :: RTval: 0x31415927, out: 0x27000000
+swr $t0, 3($t1) :: RTval: 0x31415927, out: 0x27000000
+swr $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 9($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 9($t1) :: RTval: 0x80000000, out: 0x3ff
+swr $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
+swr $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x27415927
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x27415927
+swr $t0, 0($t1) :: RTval: 0xdd00000, out: 0x415927
+swr $t0, 0($t1) :: RTval: 0xdd00000, out: 0x415927
+swr $t0, 0($t1) :: RTval: 0x28f, out: 0x8f415927
+swr $t0, 0($t1) :: RTval: 0x28f, out: 0x8f415927
+swr $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71415927
+swr $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71415927
+swr $t0, 0($t1) :: RTval: 0xf, out: 0xf415927
+swr $t0, 0($t1) :: RTval: 0xf, out: 0xf415927
+swr $t0, 0($t1) :: RTval: 0x1, out: 0x1415927
+swr $t0, 0($t1) :: RTval: 0x1, out: 0x1415927
+swr $t0, 0($t1) :: RTval: 0x35, out: 0x35415927
+swr $t0, 0($t1) :: RTval: 0x35, out: 0x35415927
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff27ffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff27ffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff27ffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff27ffff
+swr $t0, 31($t1) :: RTval: 0xffffffff, out: 0xff000000
+swr $t0, 31($t1) :: RTval: 0xffffffff, out: 0xff3f343f
+swr $t0, 33($t1) :: RTval: 0xffffffff, out: 0xff000000
+swr $t0, 33($t1) :: RTval: 0xffffffff, out: 0xff3f3e3e
+swr $t0, 45($t1) :: RTval: 0x31415927, out: 0x27000000
+swr $t0, 45($t1) :: RTval: 0x31415927, out: 0x273b3a45
+swr $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xff000000
+swr $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xff454f4e
+swr $t0, 49($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 49($t1) :: RTval: 0x80000000, out: 0x4e454e
+swr $t0, 51($t1) :: RTval: 0x28f, out: 0x8f000000
+swr $t0, 51($t1) :: RTval: 0x28f, out: 0x8f4e464d
+MEM1:
+0xffffff27, 0xffffff00, 0xffffffff, 0x0
+0x0, 0x0, 0x0, 0xffffffff
+0xffff0000, 0x0, 0x0, 0x7fffffff
+0x28f, 0x0, 0x0, 0x0
+MEM:
+0xffffff27, 0xffffff00, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xffffffff
+0xffff3f3e, 0x3e353d3c, 0x363a3c3b, 0x7fffffff
+0x28f, 0x4e464d46, 0x474d474c, 0x4a484a4c
+ulw
+ulw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x0, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f1e1f
+ulw $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0x80000000, out: 0x1e1f0000
+ulw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x3ffff
+ulw $t0, 8($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 8($t1) :: RTval: 0xffffffff, out: 0x3
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xdd00000, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x28f, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x28f, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xf, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xf, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x1, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x1, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x35, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x35, out: 0x121f1e1f
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x1e1f0000
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x1e1f0000
+ulw $t0, 32($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f343f3e
+ulw $t0, 36($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e353d3c
+ulw $t0, 40($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a3c3b
+ulw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b373b3a
+ulw $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f4e45
+ulw $t0, 52($t1) :: RTval: 0x28f, out: 0x0
+ulw $t0, 52($t1) :: RTval: 0x28f, out: 0x4e464d46
+MEM1:
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+MEM:
+0x121f1e1f, 0x0, 0x3, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a
+0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+usw
+usw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+usw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+usw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+usw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+usw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+usw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+usw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+usw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+usw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+usw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+usw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff, 0xffff7fff, 0xffffffff, 0xffff0000
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x0, 0x0
+MEM:
+0xffff, 0xffff7fff, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x474d474c, 0x4a484a4c
+swl $t0, 3($t0)
+swr $t0, 0($t0)
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4853000, out: 0xe604
+MEM:
+0xe604, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4853000, out: 0x10704
+MEM:
+0xe680, 0x10704, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4863700, out: 0xe704
+MEM:
+0xe680, 0x10700, 0xe704, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x48aedd0, out: 0xd000b004
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xd000b004
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee700, out: 0xb05f2a
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0xb05f2a, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee7ff, out: 0xff00b62a
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xff00b62a, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaeffff, out: 0xff00be2a
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xff00be2a, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4863700, out: 0xde04
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde04
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee700, out: 0xdf2a
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf2a, 0x2ab05fe0, 0xdfd0, 0x10300
diff --git a/main/none/tests/mips32/LoadStore1.stdout.exp-LE b/main/none/tests/mips32/LoadStore1.stdout.exp-LE
new file mode 100644
index 0000000..d9579b9
--- /dev/null
+++ b/main/none/tests/mips32/LoadStore1.stdout.exp-LE
@@ -0,0 +1,464 @@
+sb
+sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
+sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
+sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27
+sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x3000027
+sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff
+sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0x3ff
+sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1f00
+sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
+sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
+sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
+sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3ffff
+sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff
+sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
+sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
+sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
+sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
+sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f
+sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f
+sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71
+sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71
+sb $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sb $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sb $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sb $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sb $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sb $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
+sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
+sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0x343f3eff
+sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff
+sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0x353d3cff
+sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x27
+sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x3a363a27
+sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff
+sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0x3b3a36ff
+sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x0
+sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x453b3700
+sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f
+sb $t0, 51($t1) :: RTval: 0x28f, out: 0x464d468f
+MEM1:
+0xff0035, 0xffff2700, 0xff0000ff, 0x0
+0x0, 0x0, 0x0, 0xff000000
+0xffffffff, 0x0, 0xff2700, 0x0
+0x8f000000, 0x0, 0x0, 0x0
+MEM:
+0xff0035, 0xffff2700, 0xff0000ff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
+0xff343f3e, 0x3e353d3c, 0x36ff273b, 0x3b37003a
+0x8f4f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+sh
+sh $t0, 1($t1) :: RTval: 0x0, out: 0x0
+sh $t0, 1($t1) :: RTval: 0x0, out: 0x120000
+sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x5927
+sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x5927
+sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff
+sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x300ffff
+sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 9($t1) :: RTval: 0x80000000, out: 0xff000000
+sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
+sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
+sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffff
+sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
+sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ffff
+sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ffff
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x27005927
+sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x27005927
+sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x27000000
+sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x27000000
+sh $t0, 0($t1) :: RTval: 0x28f, out: 0x2700028f
+sh $t0, 0($t1) :: RTval: 0x28f, out: 0x2700028f
+sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x2700fd71
+sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x2700fd71
+sh $t0, 0($t1) :: RTval: 0xf, out: 0x2700000f
+sh $t0, 0($t1) :: RTval: 0xf, out: 0x2700000f
+sh $t0, 0($t1) :: RTval: 0x1, out: 0x27000001
+sh $t0, 0($t1) :: RTval: 0x1, out: 0x27000001
+sh $t0, 0($t1) :: RTval: 0x35, out: 0x27000035
+sh $t0, 0($t1) :: RTval: 0x35, out: 0x27000035
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
+sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
+sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff
+sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0x343fffff
+sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff
+sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0x353dffff
+sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x5927
+sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x3a365927
+sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff
+sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0x4f4effff
+sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x0
+sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x46450000
+sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
+sh $t0, 51($t1) :: RTval: 0x28f, out: 0x464d028f
+MEM1:
+0xffff0035, 0xffffff59, 0xff00ffff, 0xff
+0x0, 0x0, 0x0, 0xff000000
+0xff0000ff, 0xff, 0x592700, 0xff000000
+0x8f0000ff, 0x2, 0x0, 0x0
+MEM:
+0xffff0035, 0xffffff59, 0xff00ffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
+0xff343fff, 0x3e353dff, 0x3659273b, 0xff373b3a
+0x8f0000ff, 0x4e464d02, 0x474d474c, 0x4a484a4c
+sw
+sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
+sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
+sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0x8000
+sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0xffff8000
+sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
+sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
+sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
+sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
+sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff0035, 0xffffffff, 0xffffffff, 0xff000080
+0x7fffff, 0x0, 0x0, 0xff000000
+0xffffff, 0xffffff00, 0xffffff, 0x800000
+0x8f592700, 0x2, 0x0, 0x0
+MEM:
+0xffff0035, 0xffffffff, 0xffffffff, 0xffffff80
+0x237fffff, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
+0x3fffffff, 0xffffff3c, 0xffffff, 0x3b800000
+0x8f592745, 0x4e000002, 0x474d474c, 0x4a484a4c
+swl
+swl $t0, 1($t1) :: RTval: 0x0, out: 0x0
+swl $t0, 1($t1) :: RTval: 0x0, out: 0x121f00
+swl $t0, 3($t1) :: RTval: 0x31415927, out: 0x31
+swl $t0, 3($t1) :: RTval: 0x31415927, out: 0x31
+swl $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7f
+swl $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x300007f
+swl $t0, 7($t1) :: RTval: 0x80000000, out: 0x80
+swl $t0, 7($t1) :: RTval: 0x80000000, out: 0x380
+swl $t0, 9($t1) :: RTval: 0x80000000, out: 0x80
+swl $t0, 9($t1) :: RTval: 0x80000000, out: 0xff000080
+swl $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x8000807f
+swl $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x8000807f
+swl $t0, 11($t1) :: RTval: 0x7fffffff, out: 0x7f
+swl $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffff7f
+swl $t0, 8($t1) :: RTval: 0xffffffff, out: 0x7fffffff
+swl $t0, 8($t1) :: RTval: 0xffffffff, out: 0x7fffffff
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415931
+swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415931
+swl $t0, 0($t1) :: RTval: 0xdd00000, out: 0x3141590d
+swl $t0, 0($t1) :: RTval: 0xdd00000, out: 0x3141590d
+swl $t0, 0($t1) :: RTval: 0x28f, out: 0x31415900
+swl $t0, 0($t1) :: RTval: 0x28f, out: 0x31415900
+swl $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x314159ff
+swl $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x314159ff
+swl $t0, 0($t1) :: RTval: 0xf, out: 0x31415900
+swl $t0, 0($t1) :: RTval: 0xf, out: 0x31415900
+swl $t0, 0($t1) :: RTval: 0x1, out: 0x31415900
+swl $t0, 0($t1) :: RTval: 0x1, out: 0x31415900
+swl $t0, 0($t1) :: RTval: 0x35, out: 0x31415900
+swl $t0, 0($t1) :: RTval: 0x35, out: 0x31415900
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff31ff
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff31ff
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff31ff
+swl $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff31ff
+swl $t0, 33($t1) :: RTval: 0xffffffff, out: 0xff
+swl $t0, 33($t1) :: RTval: 0xffffffff, out: 0x3c3f34ff
+swl $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff
+swl $t0, 35($t1) :: RTval: 0xffffffff, out: 0x353d3cff
+swl $t0, 41($t1) :: RTval: 0x31415927, out: 0x31
+swl $t0, 41($t1) :: RTval: 0x31415927, out: 0x3a363a31
+swl $t0, 45($t1) :: RTval: 0x7fffffff, out: 0x7f
+swl $t0, 45($t1) :: RTval: 0x7fffffff, out: 0x453b377f
+swl $t0, 49($t1) :: RTval: 0x80000000, out: 0x80
+swl $t0, 49($t1) :: RTval: 0x80000000, out: 0x46454f80
+swl $t0, 51($t1) :: RTval: 0x28f, out: 0x0
+swl $t0, 51($t1) :: RTval: 0x28f, out: 0x464d4600
+MEM1:
+0x31ffffff, 0x807fffff, 0x7fffffff, 0x0
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0x0, 0x3141, 0x7fff
+0x28f, 0x0, 0x0, 0x0
+MEM:
+0x31ffffff, 0x807fffff, 0x7fffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffffffff, 0x3e353d3c, 0x363a3141, 0x3b377fff
+0x28f, 0x4e464d46, 0x474d474c, 0x4a484a4c
+swr
+swr $t0, 1($t1) :: RTval: 0x0, out: 0x0
+swr $t0, 1($t1) :: RTval: 0x0, out: 0x0
+swr $t0, 3($t1) :: RTval: 0x31415927, out: 0x27
+swr $t0, 3($t1) :: RTval: 0x31415927, out: 0x27
+swr $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffffff
+swr $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x3ffffff
+swr $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 7($t1) :: RTval: 0x80000000, out: 0x300
+swr $t0, 9($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 9($t1) :: RTval: 0x80000000, out: 0xff000000
+swr $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
+swr $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3ffff
+swr $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff
+swr $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
+swr $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+swr $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+swr $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+swr $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+swr $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+swr $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+swr $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+swr $t0, 0($t1) :: RTval: 0xf, out: 0xf
+swr $t0, 0($t1) :: RTval: 0xf, out: 0xf
+swr $t0, 0($t1) :: RTval: 0x1, out: 0x1
+swr $t0, 0($t1) :: RTval: 0x1, out: 0x1
+swr $t0, 0($t1) :: RTval: 0x35, out: 0x35
+swr $t0, 0($t1) :: RTval: 0x35, out: 0x35
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff00ffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff00ffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff00ffff
+swr $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff00ffff
+swr $t0, 31($t1) :: RTval: 0xffffffff, out: 0xff
+swr $t0, 31($t1) :: RTval: 0xffffffff, out: 0x343f3eff
+swr $t0, 33($t1) :: RTval: 0xffffffff, out: 0xffffff
+swr $t0, 33($t1) :: RTval: 0xffffffff, out: 0x3cffffff
+swr $t0, 45($t1) :: RTval: 0x31415927, out: 0x415927
+swr $t0, 45($t1) :: RTval: 0x31415927, out: 0x45415927
+swr $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xff
+swr $t0, 47($t1) :: RTval: 0x7fffffff, out: 0x4f4e45ff
+swr $t0, 49($t1) :: RTval: 0x80000000, out: 0x0
+swr $t0, 49($t1) :: RTval: 0x80000000, out: 0x46000000
+swr $t0, 51($t1) :: RTval: 0x28f, out: 0x8f
+swr $t0, 51($t1) :: RTval: 0x28f, out: 0x464d468f
+MEM1:
+0xffff0035, 0xffffff00, 0xffffffff, 0x0
+0x0, 0x0, 0x0, 0xff000000
+0xffffff00, 0x0, 0x0, 0xff592700
+0x8f000000, 0x0, 0x0, 0x0
+MEM:
+0xffff0035, 0xffffff00, 0xffffffff, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
+0xffffff3e, 0x3e353d3c, 0x363a3c3b, 0xff59273a
+0x8f000045, 0x4e464d46, 0x474d474c, 0x4a484a4c
+ulw
+ulw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x0, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f1e1f
+ulw $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0x80000000, out: 0x121f
+ulw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x30000
+ulw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff0000
+ulw $t0, 8($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 8($t1) :: RTval: 0xffffffff, out: 0x3
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xdd00000, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x28f, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x28f, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0xf, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0xf, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x1, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x1, out: 0x121f1e1f
+ulw $t0, 0($t1) :: RTval: 0x35, out: 0x0
+ulw $t0, 0($t1) :: RTval: 0x35, out: 0x121f1e1f
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x121f
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 2($t1) :: RTval: 0xffffffff, out: 0x121f
+ulw $t0, 32($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f343f3e
+ulw $t0, 36($t1) :: RTval: 0xffffffff, out: 0x0
+ulw $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e353d3c
+ulw $t0, 40($t1) :: RTval: 0x31415927, out: 0x0
+ulw $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a3c3b
+ulw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x0
+ulw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b373b3a
+ulw $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
+ulw $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f4e45
+ulw $t0, 52($t1) :: RTval: 0x28f, out: 0x0
+ulw $t0, 52($t1) :: RTval: 0x28f, out: 0x4e464d46
+MEM1:
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+0x0, 0x0, 0x0, 0x0
+MEM:
+0x121f1e1f, 0x0, 0x3, 0xffffffff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a
+0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+usw
+usw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+usw $t0, 0($t1) :: RTval: 0x0, out: 0x0
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+usw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
+usw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+usw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
+usw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+usw $t0, 0($t1) :: RTval: 0xf, out: 0xf
+usw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+usw $t0, 0($t1) :: RTval: 0x1, out: 0x1
+usw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+usw $t0, 0($t1) :: RTval: 0x35, out: 0x35
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
+usw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
+usw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
+usw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
+usw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+usw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
+MEM1:
+0xffff0035, 0xffffffff, 0xffffffff, 0x7fff
+0x0, 0x0, 0x0, 0x0
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x0, 0x0
+MEM:
+0xffff0035, 0xffffffff, 0xffffffff, 0xffff7fff
+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
+0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
+0x80000000, 0x28f, 0x474d474c, 0x4a484a4c
+swl $t0, 3($t0)
+swr $t0, 0($t0)
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4853000, out: 0x4853000
+MEM:
+0x4853000, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4853000, out: 0x4853000
+MEM:
+0xe680, 0x4853000, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4863700, out: 0x4863700
+MEM:
+0xe680, 0x10700, 0x4863700, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x48aedd0, out: 0x48aedd0
+MEM:
+0xe680, 0x10700, 0xe7dc, 0x48aedd0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee700, out: 0x2aaee700
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2aaee700, 0xb6a0, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee7ff, out: 0x2aaee7ff
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0x2aaee7ff, 0xbe80, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaeffff, out: 0x2aaeffff
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0x2aaeffff, 0xde10
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x4863700, out: 0x4863700
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0x4863700
+0xdf20, 0x2ab05fe0, 0xdfd0, 0x10300
+swl $t0, 3($t1)
+swr $t0, 0($t1)
+ :: RTval: 0x2aaee700, out: 0x2aaee700
+MEM:
+0xe680, 0x10700, 0xe7dc, 0xb0d0
+0x2ab05fd0, 0xb6a0, 0xbe80, 0xde10
+0x2aaee700, 0x2ab05fe0, 0xdfd0, 0x10300
diff --git a/main/none/tests/mips32/LoadStore1.vgtest b/main/none/tests/mips32/LoadStore1.vgtest
new file mode 100644
index 0000000..0c9bce2
--- /dev/null
+++ b/main/none/tests/mips32/LoadStore1.vgtest
@@ -0,0 +1,2 @@
+prog: LoadStore1
+vgopts: -q
diff --git a/main/none/tests/mips32/MIPS32int.c b/main/none/tests/mips32/MIPS32int.c
new file mode 100644
index 0000000..84f79a6
--- /dev/null
+++ b/main/none/tests/mips32/MIPS32int.c
@@ -0,0 +1,1422 @@
+#include <stdio.h>
+
+#define TESTINST1(instruction, RSval, RTval, RD, RS, RT) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "li $" #RD ", 0\n\t" \
+ "move $" #RS ", %1\n\t" \
+ "move $" #RT ", %2\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RTval) \
+ : #RD, #RS, #RT, "cc", "memory" \
+ ); \
+ printf("%s :: rd 0x%08x rs 0x%08x, rt 0x%08x\n", \
+ instruction, out, RSval, RTval); \
+}
+
+#define TESTINST2(instruction, RSval, imm, RT, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS ", %1\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RT "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval) \
+ : #RT, #RS, "cc", "memory" \
+ ); \
+ printf("%s :: rt 0x%08x rs 0x%08x, imm 0x%08x\n", \
+ instruction, out, RSval, imm); \
+}
+
+#define TESTINST3(instruction, RSval, RD, RS) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RS ", %1\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval) \
+ : #RD, #RS, "cc", "memory" \
+ ); \
+ printf("%s :: rd 0x%08x rs 0x%08x\n", \
+ instruction, out, RSval); \
+}
+
+#define TESTINST3a(instruction, RSval, RTval, RS, RT) \
+{ \
+ unsigned int HI; \
+ unsigned int LO; \
+ __asm__ volatile( \
+ "li $" #RS ", 0x0\n\t" \
+ "mthi $" #RS"\n\t" \
+ "mtlo $" #RS"\n\t" \
+ "move $" #RS ", %2\n\t" \
+ "move $" #RT ", %3\n\t" \
+ instruction "\n\t" \
+ "mfhi %0 \n\t" \
+ "mflo %1 \n\t" \
+ : "=&r" (HI), "=&r" (LO) \
+ : "r" (RSval), "r"(RTval) \
+ : #RS, #RT, "cc", "memory" \
+ ); \
+ printf("%s :: rs 0x%08x rt 0x%08x HI 0x%08x LO 0x%08x \n", \
+ instruction, RSval, RTval, HI, LO); \
+}
+
+#define TESTINST4(instruction, RTval, RSval, RT, RS, pos, size) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $" #RT ", %1\n\t" \
+ "move $" #RS ", %2\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RT "\n\t" \
+ : "=&r" (out) \
+ : "r" (RTval), "r" (RSval) \
+ : #RT, #RS, "cc", "memory" \
+ ); \
+ printf("%s :: rt 0x%08x rs 0x%08x, pos 0x%08x, size 0x%08x\n", \
+ instruction, out, RSval, pos, size); \
+}
+
+const unsigned int mem[] = {
+ 0x121f1e1f, 0, 3, -1,
+ 0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a,
+ 0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a,
+ 0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+};
+
+// load $t0, 0($t1)
+#define TESTINSN5LOAD(instruction, RTval, offset, RT) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $t1, %1\n\t" \
+ "li $t0, " #RTval"\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RT "\n\t" \
+ : "=&r" (out) \
+ : "r" (mem), "r" (RTval) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: rt 0x%08x\n", \
+ instruction, out); \
+}
+
+#define TESTINSN_HILO(RSval) \
+{ \
+ unsigned int HI; \
+ unsigned int LO; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "mthi $t0\n\t" \
+ "addiu $t0, $t0, 0xffff\n\t" \
+ "mtlo $t0\n\t" \
+ "mfhi %0\n\t" \
+ "mflo %1\n\t" \
+ : "=&r" (HI), "=&r" (LO) \
+ : "r" (RSval)\
+ : "cc", "memory" \
+ ); \
+ printf("mfhi mflo :: HI: 0x%x, LO: 0x%x\n", \
+ HI, LO); \
+}
+
+int main(int argc, char **argv)
+{
+ printf("ADD\n");
+ TESTINST1("add $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 1, 1, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 1, -1, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 0x31415927, 0x27181728, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 0x31415927, 0x97181728, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("add $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+
+ printf("ADDI\n");
+ TESTINST2("addi $t0, $t1, 0", 0, 0, t0, t1);
+ TESTINST2("addi $t0, $t1, 1", 0, 1, t0, t1);
+ TESTINST2("addi $t0, $t1, 1", 1, 0, t0, t1);
+ TESTINST2("addi $t0, $t1, 1", 1, 1, t0, t1);
+ TESTINST2("addi $t0, $t1, -1", 0, -1, t0, t1);
+ TESTINST2("addi $t0, $t1, -1", 1, -1, t0, t1);
+ TESTINST2("addi $t0, $t1, 0", 0x80000000, 0, t0, t1);
+ TESTINST2("addi $t0, $t1, 0", -1, 0, t0, t1);
+ TESTINST2("addi $t0, $t1, 0", 0x80000000, 0, t0, t1);
+
+ printf("ADDIU\n");
+ TESTINST2("addiu $t0, $t1, 0", 0, 0, t0, t1);
+ TESTINST2("addiu $t0, $t1, 1", 0, 1, t0, t1);
+ TESTINST2("addiu $t0, $t1, 1", 1, 0, t0, t1);
+ TESTINST2("addiu $t0, $t1, 1", 1, 1, t0, t1);
+ TESTINST2("addiu $t0, $t1, -1", 0, -1, t0, t1);
+ TESTINST2("addiu $t0, $t1, -1", 1, -1, t0, t1);
+ TESTINST2("addiu $t0, $t1, 0", 0x80000000, 0, t0, t1);
+ TESTINST2("addiu $t0, $t1, 0", -1, 0, t0, t1);
+ TESTINST2("addiu $t0, $t1, 0", 0x80000000, 0, t0, t1);
+
+ printf("ADDU\n");
+ TESTINST1("addu $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 1, 1, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 1, -1, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0x31415927, 0x27181728, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0x31415927, 0x97181728, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0x80000000, 0x7fffffff, t0, t1, t2);
+ TESTINST1("addu $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+
+ printf("AND\n");
+ TESTINST1("and $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("and $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+
+ printf("ANDI\n");
+ TESTINST2("andi $t0, $t1, 1", 0, 1, t0, t1);
+ TESTINST2("andi $t0, $t1, 0", 1, 0, t0, t1);
+ TESTINST2("andi $t0, $t1, 1", 1, 1, t0, t1);
+ TESTINST2("andi $t0, $t1, 1", 0x7fffffff, 0, t0, t1);
+ TESTINST2("andi $t0, $t1, 0", 0x80000000, 0, t0, t1);
+ TESTINST2("andi $t0, $t1, 0x3145", 0xffffffff, 0x3145, t0, t1);
+
+ printf("CLO\n");
+ TESTINST3("clo $t0, $t1", 0, t0, t1);
+ TESTINST3("clo $t0, $t1", 1, t0, t1);
+ TESTINST3("clo $t0, $t1", 0x10, t0, t1);
+ TESTINST3("clo $t0, $t1", 0xffffffff, t0, t1);
+
+ printf("CLZ\n");
+ TESTINST3("clz $t0, $t1", 0, t0, t1);
+ TESTINST3("clz $t0, $t1", 1, t0, t1);
+ TESTINST3("clz $t0, $t1", 0x10, t0, t1);
+ TESTINST3("clz $t0, $t1", 0xffffffff, t0, t1);
+
+ printf("DIV\n");
+ TESTINST3a("div $t0, $t1", 0x6, 0x2, t0, t1);
+ TESTINST3a("div $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
+ TESTINST3a("div $t0, $t1", 0xffffffff, 0x1, t0, t1);
+ TESTINST3a("div $t0, $t1", 0x1, 0xffffffff, t0, t1);
+ TESTINST3a("div $t0, $t1", 0x2, 0x6, t0, t1);
+
+ printf("DIVU\n");
+ TESTINST3a("divu $t0, $t1", 0x6, 0x2, t0, t1);
+ TESTINST3a("divu $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
+ TESTINST3a("divu $t0, $t1", 0xffffffff, 0x1, t0, t1);
+ TESTINST3a("divu $t0, $t1", 0x1, 0xffffffff, t0, t1);
+ TESTINST3a("divu $t0, $t1", 0x2, 0x6, t0, t1);
+ TESTINST3a("divu $t0, $t1", 0x0, 0x2, t0, t1);
+
+#if (__mips==32) && (__mips_isa_rev>=2)
+ printf("EXT\n");
+ TESTINST4("ext $t0, $t1, 2, 6", 0, 0xffffffff, t0, t1, 2, 6);
+ TESTINST4("ext $t0, $t1, 2, 6", 0xffffffff, 0xffffffff, t0, t1, 2, 6);
+ TESTINST4("ext $t0, $t1, 2, 6", 0, 0xffffffff, t0, t1, 31, 6);
+ TESTINST4("ext $t0, $t1, 2, 6", 0, 0, t0, t1, 32, 32);
+ TESTINST4("ext $t0, $t1, 2, 6", 0, 0xffff, t0, t1, 31, 0);
+ TESTINST4("ext $t0, $t1, 2, 6", 0, 0xff, t0, t1, 31, 0)
+ TESTINST4("ext $t0, $t1, 2, 6", 0, 0xf0000000, t0, t1, 31, 0)
+ TESTINST4("ext $t0, $t1, 2, 6", 0, 0xf0000000, t0, t1, 0, 31)
+ TESTINST4("ext $t0, $t1, 2, 6", 0, 0x31415927, t0, t1, 3, 25)
+
+ printf("INS\n");
+ TESTINST4("ins $t0, $t1, 2, 6", 0, 0xffffffff, t0, t1, 2, 6);
+ TESTINST4("ins $t0, $t1, 2, 6", 0xffffffff, 0xffffffff, t0, t1, 2, 6);
+ TESTINST4("ins $t0, $t1, 2, 6", 0, 0xffffffff, t0, t1, 31, 6);
+ TESTINST4("ins $t0, $t1, 2, 6", 0, 0, t0, t1, 32, 32);
+ TESTINST4("ins $t0, $t1, 2, 6", 0, 0xffff, t0, t1, 31, 0);
+ TESTINST4("ins $t0, $t1, 2, 6", 0, 0xff, t0, t1, 31, 0)
+ TESTINST4("ins $t0, $t1, 2, 6", 0, 0xf0000000, t0, t1, 31, 0)
+ TESTINST4("ins $t0, $t1, 2, 6", 0, 0xf0000000, t0, t1, 0, 31)
+ TESTINST4("ins $t0, $t1, 2, 6", 0, 0x31415927, t0, t1, 3, 25)
+#endif
+
+ printf("LB\n");
+ TESTINSN5LOAD("lb $t0, 0($t1)", 0, 0, t0);
+ TESTINSN5LOAD("lb $t0, 4($t1)", 0, 4, t0);
+ TESTINSN5LOAD("lb $t0, 8($t1)", 0, 8, t0);
+ TESTINSN5LOAD("lb $t0, 12($t1)", 0, 12, t0);
+ TESTINSN5LOAD("lb $t0, 16($t1)", 0, 16, t0);
+ TESTINSN5LOAD("lb $t0, 20($t1)", 0, 20, t0);
+ TESTINSN5LOAD("lb $t0, 24($t1)", 0, 24, t0);
+ TESTINSN5LOAD("lb $t0, 28($t1)", 0, 28, t0);
+ TESTINSN5LOAD("lb $t0, 32($t1)", 0, 32, t0);
+ TESTINSN5LOAD("lb $t0, 36($t1)", 0, 36, t0);
+ TESTINSN5LOAD("lb $t0, 40($t1)", 0, 40, t0);
+ TESTINSN5LOAD("lb $t0, 44($t1)", 0, 44, t0);
+ TESTINSN5LOAD("lb $t0, 48($t1)", 0, 48, t0);
+ TESTINSN5LOAD("lb $t0, 52($t1)", 0, 52, t0);
+ TESTINSN5LOAD("lb $t0, 56($t1)", 0, 56, t0);
+ TESTINSN5LOAD("lb $t0, 60($t1)", 0, 60, t0);
+ TESTINSN5LOAD("lb $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lb $t0, 2($t1)", 0, 2, t0);
+ TESTINSN5LOAD("lb $t0, 6($t1)", 0, 6, t0);
+ TESTINSN5LOAD("lb $t0, 10($t1)", 0, 10, t0);
+ TESTINSN5LOAD("lb $t0, 14($t1)", 0, 14, t0);
+ TESTINSN5LOAD("lb $t0, 18($t1)", 0, 18, t0);
+ TESTINSN5LOAD("lb $t0, 22($t1)", 0, 22, t0);
+ TESTINSN5LOAD("lb $t0, 26($t1)", 0, 26, t0);
+ TESTINSN5LOAD("lb $t0, 30($t1)", 0, 30, t0);
+ TESTINSN5LOAD("lb $t0, 34($t1)", 0, 34, t0);
+ TESTINSN5LOAD("lb $t0, 38($t1)", 0, 38, t0);
+
+ printf("LBU\n");
+ TESTINSN5LOAD("lbu $t0, 0($t1)", 0, 0, t0);
+ TESTINSN5LOAD("lbu $t0, 4($t1)", 0, 4, t0);
+ TESTINSN5LOAD("lbu $t0, 8($t1)", 0, 8, t0);
+ TESTINSN5LOAD("lbu $t0, 12($t1)", 0, 12, t0);
+ TESTINSN5LOAD("lbu $t0, 16($t1)", 0, 16, t0);
+ TESTINSN5LOAD("lbu $t0, 20($t1)", 0, 20, t0);
+ TESTINSN5LOAD("lbu $t0, 24($t1)", 0, 24, t0);
+ TESTINSN5LOAD("lbu $t0, 28($t1)", 0, 28, t0);
+ TESTINSN5LOAD("lbu $t0, 32($t1)", 0, 32, t0);
+ TESTINSN5LOAD("lbu $t0, 36($t1)", 0, 36, t0);
+ TESTINSN5LOAD("lbu $t0, 40($t1)", 0, 40, t0);
+ TESTINSN5LOAD("lbu $t0, 44($t1)", 0, 44, t0);
+ TESTINSN5LOAD("lbu $t0, 48($t1)", 0, 48, t0);
+ TESTINSN5LOAD("lbu $t0, 52($t1)", 0, 52, t0);
+ TESTINSN5LOAD("lbu $t0, 56($t1)", 0, 56, t0);
+ TESTINSN5LOAD("lbu $t0, 60($t1)", 0, 60, t0);
+ TESTINSN5LOAD("lbu $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lbu $t0, 2($t1)", 0, 2, t0);
+ TESTINSN5LOAD("lbu $t0, 6($t1)", 0, 6, t0);
+ TESTINSN5LOAD("lbu $t0, 10($t1)", 0, 10, t0);
+ TESTINSN5LOAD("lbu $t0, 14($t1)", 0, 14, t0);
+ TESTINSN5LOAD("lbu $t0, 18($t1)", 0, 18, t0);
+ TESTINSN5LOAD("lbu $t0, 22($t1)", 0, 22, t0);
+ TESTINSN5LOAD("lbu $t0, 26($t1)", 0, 26, t0);
+ TESTINSN5LOAD("lbu $t0, 30($t1)", 0, 30, t0);
+ TESTINSN5LOAD("lbu $t0, 34($t1)", 0, 34, t0);
+ TESTINSN5LOAD("lbu $t0, 38($t1)", 0, 38, t0);
+
+ printf("LH\n");
+ TESTINSN5LOAD("lh $t0, 0($t1)", 0, 0, t0);
+ TESTINSN5LOAD("lh $t0, 4($t1)", 0, 4, t0);
+ TESTINSN5LOAD("lh $t0, 8($t1)", 0, 8, t0);
+ TESTINSN5LOAD("lh $t0, 12($t1)", 0, 12, t0);
+ TESTINSN5LOAD("lh $t0, 16($t1)", 0, 16, t0);
+ TESTINSN5LOAD("lh $t0, 20($t1)", 0, 20, t0);
+ TESTINSN5LOAD("lh $t0, 24($t1)", 0, 24, t0);
+ TESTINSN5LOAD("lh $t0, 28($t1)", 0, 28, t0);
+ TESTINSN5LOAD("lh $t0, 32($t1)", 0, 32, t0);
+ TESTINSN5LOAD("lh $t0, 36($t1)", 0, 36, t0);
+ TESTINSN5LOAD("lh $t0, 40($t1)", 0, 40, t0);
+ TESTINSN5LOAD("lh $t0, 44($t1)", 0, 44, t0);
+ TESTINSN5LOAD("lh $t0, 48($t1)", 0, 48, t0);
+ TESTINSN5LOAD("lh $t0, 52($t1)", 0, 52, t0);
+ TESTINSN5LOAD("lh $t0, 56($t1)", 0, 56, t0);
+ TESTINSN5LOAD("lh $t0, 60($t1)", 0, 60, t0);
+ TESTINSN5LOAD("lh $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lh $t0, 2($t1)", 0, 2, t0);
+ TESTINSN5LOAD("lh $t0, 6($t1)", 0, 6, t0);
+ TESTINSN5LOAD("lh $t0, 10($t1)", 0, 10, t0);
+ TESTINSN5LOAD("lh $t0, 14($t1)", 0, 14, t0);
+ TESTINSN5LOAD("lh $t0, 18($t1)", 0, 18, t0);
+ TESTINSN5LOAD("lh $t0, 22($t1)", 0, 22, t0);
+ TESTINSN5LOAD("lh $t0, 26($t1)", 0, 26, t0);
+ TESTINSN5LOAD("lh $t0, 30($t1)", 0, 30, t0);
+ TESTINSN5LOAD("lh $t0, 34($t1)", 0, 34, t0);
+ TESTINSN5LOAD("lh $t0, 38($t1)", 0, 38, t0);
+
+ printf("LHU\n");
+ TESTINSN5LOAD("lhu $t0, 0($t1)", 0, 0, t0);
+ TESTINSN5LOAD("lhu $t0, 4($t1)", 0, 4, t0);
+ TESTINSN5LOAD("lhu $t0, 8($t1)", 0, 8, t0);
+ TESTINSN5LOAD("lhu $t0, 12($t1)", 0, 12, t0);
+ TESTINSN5LOAD("lhu $t0, 16($t1)", 0, 16, t0);
+ TESTINSN5LOAD("lhu $t0, 20($t1)", 0, 20, t0);
+ TESTINSN5LOAD("lhu $t0, 24($t1)", 0, 24, t0);
+ TESTINSN5LOAD("lhu $t0, 28($t1)", 0, 28, t0);
+ TESTINSN5LOAD("lhu $t0, 32($t1)", 0, 32, t0);
+ TESTINSN5LOAD("lhu $t0, 36($t1)", 0, 36, t0);
+ TESTINSN5LOAD("lhu $t0, 40($t1)", 0, 40, t0);
+ TESTINSN5LOAD("lhu $t0, 44($t1)", 0, 44, t0);
+ TESTINSN5LOAD("lhu $t0, 48($t1)", 0, 48, t0);
+ TESTINSN5LOAD("lhu $t0, 52($t1)", 0, 52, t0);
+ TESTINSN5LOAD("lhu $t0, 56($t1)", 0, 56, t0);
+ TESTINSN5LOAD("lhu $t0, 60($t1)", 0, 60, t0);
+ TESTINSN5LOAD("lhu $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lhu $t0, 2($t1)", 0, 2, t0);
+ TESTINSN5LOAD("lhu $t0, 6($t1)", 0, 6, t0);
+ TESTINSN5LOAD("lhu $t0, 10($t1)", 0, 10, t0);
+ TESTINSN5LOAD("lhu $t0, 14($t1)", 0, 14, t0);
+ TESTINSN5LOAD("lhu $t0, 18($t1)", 0, 18, t0);
+ TESTINSN5LOAD("lhu $t0, 22($t1)", 0, 22, t0);
+ TESTINSN5LOAD("lhu $t0, 26($t1)", 0, 26, t0);
+ TESTINSN5LOAD("lhu $t0, 30($t1)", 0, 30, t0);
+ TESTINSN5LOAD("lhu $t0, 34($t1)", 0, 34, t0);
+ TESTINSN5LOAD("lhu $t0, 38($t1)", 0, 38, t0);
+
+ printf("LUI\n");
+ TESTINST3("lui $t0, 0xffff", 0xffff, t0, t1);
+ TESTINST3("lui $t0, 0xff00", 0xff00, t0, t1);
+ TESTINST3("lui $t0, 0xff", 0xff, t0, t1);
+ TESTINST3("lui $t0, 0x0", 0x0, t0, t1);
+ TESTINST3("lui $t0, 0x5", 0x5, t0, t1);
+ TESTINST3("lui $t0, 0x387", 0x387, t0, t1);
+
+ printf("LW\n");
+ TESTINSN5LOAD("lw $t0, 0($t1)", 0, 0, t0);
+ TESTINSN5LOAD("lw $t0, 4($t1)", 0, 4, t0);
+ TESTINSN5LOAD("lw $t0, 8($t1)", 0, 8, t0);
+ TESTINSN5LOAD("lw $t0, 12($t1)", 0, 12, t0);
+ TESTINSN5LOAD("lw $t0, 16($t1)", 0, 16, t0);
+ TESTINSN5LOAD("lw $t0, 20($t1)", 0, 20, t0);
+ TESTINSN5LOAD("lw $t0, 24($t1)", 0, 24, t0);
+ TESTINSN5LOAD("lw $t0, 28($t1)", 0, 28, t0);
+ TESTINSN5LOAD("lw $t0, 32($t1)", 0, 32, t0);
+ TESTINSN5LOAD("lw $t0, 36($t1)", 0, 36, t0);
+ TESTINSN5LOAD("lw $t0, 40($t1)", 0, 40, t0);
+ TESTINSN5LOAD("lw $t0, 44($t1)", 0, 44, t0);
+ TESTINSN5LOAD("lw $t0, 48($t1)", 0, 48, t0);
+ TESTINSN5LOAD("lw $t0, 52($t1)", 0, 52, t0);
+ TESTINSN5LOAD("lw $t0, 56($t1)", 0, 56, t0);
+ TESTINSN5LOAD("lw $t0, 60($t1)", 0, 60, t0);
+ TESTINSN5LOAD("lw $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lw $t0, 2($t1)", 0, 2, t0);
+ TESTINSN5LOAD("lw $t0, 6($t1)", 0, 6, t0);
+ TESTINSN5LOAD("lw $t0, 10($t1)", 0, 10, t0);
+ TESTINSN5LOAD("lw $t0, 14($t1)", 0, 14, t0);
+ TESTINSN5LOAD("lw $t0, 18($t1)", 0, 18, t0);
+ TESTINSN5LOAD("lw $t0, 22($t1)", 0, 22, t0);
+ TESTINSN5LOAD("lw $t0, 26($t1)", 0, 26, t0);
+ TESTINSN5LOAD("lw $t0, 30($t1)", 0, 30, t0);
+ TESTINSN5LOAD("lw $t0, 34($t1)", 0, 34, t0);
+ TESTINSN5LOAD("lw $t0, 38($t1)", 0, 38, t0);
+
+ printf("LWL\n");
+ TESTINSN5LOAD("lwl $t0, 0($t1)", 0, 0, t0);
+ TESTINSN5LOAD("lwl $t0, 4($t1)", 0, 4, t0);
+ TESTINSN5LOAD("lwl $t0, 8($t1)", 0, 8, t0);
+ TESTINSN5LOAD("lwl $t0, 12($t1)", 0, 12, t0);
+ TESTINSN5LOAD("lwl $t0, 16($t1)", 0, 16, t0);
+ TESTINSN5LOAD("lwl $t0, 20($t1)", 0, 20, t0);
+ TESTINSN5LOAD("lwl $t0, 24($t1)", 0, 24, t0);
+ TESTINSN5LOAD("lwl $t0, 28($t1)", 0, 28, t0);
+ TESTINSN5LOAD("lwl $t0, 32($t1)", 0, 32, t0);
+ TESTINSN5LOAD("lwl $t0, 36($t1)", 0, 36, t0);
+ TESTINSN5LOAD("lwl $t0, 40($t1)", 0, 40, t0);
+ TESTINSN5LOAD("lwl $t0, 44($t1)", 0, 44, t0);
+ TESTINSN5LOAD("lwl $t0, 48($t1)", 0, 48, t0);
+ TESTINSN5LOAD("lwl $t0, 52($t1)", 0, 52, t0);
+ TESTINSN5LOAD("lwl $t0, 56($t1)", 0, 56, t0);
+ TESTINSN5LOAD("lwl $t0, 60($t1)", 0, 60, t0);
+ TESTINSN5LOAD("lwl $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lwl $t0, 2($t1)", 0, 2, t0);
+ TESTINSN5LOAD("lwl $t0, 6($t1)", 0, 6, t0);
+ TESTINSN5LOAD("lwl $t0, 10($t1)", 0, 10, t0);
+ TESTINSN5LOAD("lwl $t0, 14($t1)", 0, 14, t0);
+ TESTINSN5LOAD("lwl $t0, 18($t1)", 0, 18, t0);
+ TESTINSN5LOAD("lwl $t0, 22($t1)", 0, 22, t0);
+ TESTINSN5LOAD("lwl $t0, 26($t1)", 0, 26, t0);
+ TESTINSN5LOAD("lwl $t0, 30($t1)", 0, 30, t0);
+ TESTINSN5LOAD("lwl $t0, 34($t1)", 0, 34, t0);
+ TESTINSN5LOAD("lwl $t0, 38($t1)", 0, 38, t0);
+
+ printf("LWR\n");
+ TESTINSN5LOAD("lwr $t0, 0($t1)", 0, 0, t0);
+ TESTINSN5LOAD("lwr $t0, 4($t1)", 0, 4, t0);
+ TESTINSN5LOAD("lwr $t0, 8($t1)", 0, 8, t0);
+ TESTINSN5LOAD("lwr $t0, 12($t1)", 0, 12, t0);
+ TESTINSN5LOAD("lwr $t0, 16($t1)", 0, 16, t0);
+ TESTINSN5LOAD("lwr $t0, 20($t1)", 0, 20, t0);
+ TESTINSN5LOAD("lwr $t0, 24($t1)", 0, 24, t0);
+ TESTINSN5LOAD("lwr $t0, 28($t1)", 0, 28, t0);
+ TESTINSN5LOAD("lwr $t0, 32($t1)", 0, 32, t0);
+ TESTINSN5LOAD("lwr $t0, 36($t1)", 0, 36, t0);
+ TESTINSN5LOAD("lwr $t0, 40($t1)", 0, 40, t0);
+ TESTINSN5LOAD("lwr $t0, 44($t1)", 0, 44, t0);
+ TESTINSN5LOAD("lwr $t0, 48($t1)", 0, 48, t0);
+ TESTINSN5LOAD("lwr $t0, 52($t1)", 0, 52, t0);
+ TESTINSN5LOAD("lwr $t0, 56($t1)", 0, 56, t0);
+ TESTINSN5LOAD("lwr $t0, 60($t1)", 0, 60, t0);
+ TESTINSN5LOAD("lwr $t0, 64($t1)", 0, 64, t0);
+ TESTINSN5LOAD("lwr $t0, 2($t1)", 0, 2, t0);
+ TESTINSN5LOAD("lwr $t0, 6($t1)", 0, 6, t0);
+ TESTINSN5LOAD("lwr $t0, 10($t1)", 0, 10, t0);
+ TESTINSN5LOAD("lwr $t0, 14($t1)", 0, 14, t0);
+ TESTINSN5LOAD("lwr $t0, 18($t1)", 0, 18, t0);
+ TESTINSN5LOAD("lwr $t0, 22($t1)", 0, 22, t0);
+ TESTINSN5LOAD("lwr $t0, 26($t1)", 0, 26, t0);
+ TESTINSN5LOAD("lwr $t0, 30($t1)", 0, 30, t0);
+ TESTINSN5LOAD("lwr $t0, 34($t1)", 0, 34, t0);
+ TESTINSN5LOAD("lwr $t0, 38($t1)", 0, 38, t0);
+
+ printf("MADD\n");
+ TESTINST3a("madd $t0, $t1", 0x6, 0x2, t0, t1);
+ TESTINST3a("madd $t0, $t1", 0x55, 0x28, t0, t1);
+ TESTINST3a("madd $t0, $t1", 0x18, 0xfff, t0, t1);
+ TESTINST3a("madd $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
+ TESTINST3a("madd $t0, $t1", 0xffffffff, 0x1, t0, t1);
+ TESTINST3a("madd $t0, $t1", 0x1, 0xffffffff, t0, t1);
+ TESTINST3a("madd $t0, $t1", 0x2, 0x6, t0, t1);
+ TESTINST3a("madd $t0, $t1", 0x356, 0x555, t0, t1);
+
+ printf("MADDU\n");
+ TESTINST3a("maddu $t0, $t1", 0x6, 0x2, t0, t1);
+ TESTINST3a("maddu $t0, $t1", 0x55, 0x28, t0, t1);
+ TESTINST3a("maddu $t0, $t1", 0x18, 0xfff, t0, t1);
+ TESTINST3a("maddu $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
+ TESTINST3a("maddu $t0, $t1", 0xffffffff, 0x1, t0, t1);
+ TESTINST3a("maddu $t0, $t1", 0x1, 0xffffffff, t0, t1);
+ TESTINST3a("maddu $t0, $t1", 0x2, 0x6, t0, t1);
+ TESTINST3a("maddu $t0, $t1", 0x356, 0x555, t0, t1);
+
+ printf("MOVN\n");
+ TESTINST1("movn $t0, $t1, $t2", 0x31415927, 0, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x31415927, 1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x80000000, 1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x7fffffff, 1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x80000000, 1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x31415927, 0, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x80000000, 1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x80000000, 1, t0, t1, t2);
+ TESTINST1("movn $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+
+ printf("MOVZ\n");
+ TESTINST1("movz $t0, $t1, $t2", 0x31415927, 0, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x31415927, 1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x80000000, 1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x7fffffff, 1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x80000000, 1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x31415927, 0, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x80000000, 1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x80000000, 1, t0, t1, t2);
+ TESTINST1("movz $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+
+ printf("MSUB\n");
+ TESTINST3a("msub $t0, $t1", 0x6, 0x2, t0, t1);
+ TESTINST3a("msub $t0, $t1", 0x55, 0x28, t0, t1);
+ TESTINST3a("msub $t0, $t1", 0x18, 0xfff, t0, t1);
+ TESTINST3a("msub $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
+ TESTINST3a("msub $t0, $t1", 0xffffffff, 0x1, t0, t1);
+ TESTINST3a("msub $t0, $t1", 0x1, 0xffffffff, t0, t1);
+ TESTINST3a("msub $t0, $t1", 0x2, 0x6, t0, t1);
+ TESTINST3a("msub $t0, $t1", 0x356, 0x555, t0, t1);
+
+ printf("MSUBU\n");
+ TESTINST3a("msubu $t0, $t1", 0x31415927, 0xffffffff, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x31415927, 0xee00ee00, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0, 255, t0, t1);
+ TESTINST3a("msubu $t0, $t1", -1, 0, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0, 1, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0, 0, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x80000000, -1, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x80000000, 0x80000000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x7fffffff, 0, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x80000000, 0x80000000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x7fffffff, 0x80000000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x80000000, 0xff000000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x7fffffff, 0x0dd00000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x31415927, 0xffffffff, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x31415927, 0xee00ee00, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0, 255, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 1, 0, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0, 1, t0, t1);
+ TESTINST3a("msubu $t0, $t1", -1, 0, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0, -1, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0, 0x80000000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x80000000, 0, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x80000000, 0x80000000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x7fffffff, 0x80000000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x80000000, 0xff000000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x7fffffff, 0x0dd00000, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0xffffffff, 0, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0, 0xffffffff, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0xffffffff, 0xffffffff, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
+ TESTINST3a("msubu $t0, $t1", 0x0000ffff, 0x0000ffff, t0, t1);
+
+ printf("MUL\n");
+ TESTINST1("mul $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("mul $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+
+ printf("MULT\n");
+ TESTINST3a("mult $t0, $t1", 0x31415927, 0xffffffff, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x31415927, 0xee00ee00, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0, 255, t0, t1);
+ TESTINST3a("mult $t0, $t1", -1, 0, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0, 1, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0, 0, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x80000000, -1, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x80000000, 0x80000000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x7fffffff, 0, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x80000000, 0x80000000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x7fffffff, 0x80000000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x80000000, 0xff000000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x7fffffff, 0x0dd00000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x31415927, 0xffffffff, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x31415927, 0xee00ee00, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0, 255, t0, t1);
+ TESTINST3a("mult $t0, $t1", 1, 0, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0, 1, t0, t1);
+ TESTINST3a("mult $t0, $t1", -1, 0, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0, -1, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0, 0x80000000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x80000000, 0, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x80000000, 0x80000000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x7fffffff, 0x80000000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x80000000, 0xff000000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x7fffffff, 0x0dd00000, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0xffffffff, 0, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0, 0xffffffff, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0xffffffff, 0xffffffff, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
+ TESTINST3a("mult $t0, $t1", 0x0000ffff, 0x0000ffff, t0, t1);
+
+ printf("MULTU\n");
+ TESTINST3a("multu $t0, $t1", 0x31415927, 0xffffffff, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x31415927, 0xee00ee00, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0, 255, t0, t1);
+ TESTINST3a("multu $t0, $t1", -1, 0, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0, 1, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0, 0, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x80000000, -1, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x80000000, 0x80000000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x7fffffff, 0, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x80000000, 0x80000000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x7fffffff, 0x80000000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x80000000, 0xff000000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x7fffffff, 0x0dd00000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x31415927, 0xffffffff, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x31415927, 0xee00ee00, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0, 255, t0, t1);
+ TESTINST3a("multu $t0, $t1", 1, 0, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0, 1, t0, t1);
+ TESTINST3a("multu $t0, $t1", -1, 0, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0, -1, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0, 0x80000000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x80000000, 0, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x80000000, 0x80000000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x7fffffff, 0x80000000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x80000000, 0xff000000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x7fffffff, 0x0dd00000, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0xffffffff, 0, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0, 0xffffffff, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0xffffffff, 0xffffffff, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
+ TESTINST3a("multu $t0, $t1", 0x0000ffff, 0x0000ffff, t0, t1);
+
+ printf("NOR\n");
+ TESTINST1("nor $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("nor $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+
+#if (__mips==32) && (__mips_isa_rev>=2)
+ printf("WSBH\n");
+ TESTINST3("wsbh $t0, $t1", 0x2, t0, t1);
+ TESTINST3("wsbh $t0, $t1", 0x28, t0, t1);
+ TESTINST3("wsbh $t0, $t1", -258, t0, t1);
+ TESTINST3("wsbh $t0, $t1", 0x7fffffff, t0, t1);
+ TESTINST3("wsbh $t0, $t1", -11, t0, t1);
+ TESTINST3("wsbh $t0, $t1", 0xffffffff, t0, t1);
+ TESTINST3("wsbh $t0, $t1", 0x16, t0, t1);
+ TESTINST3("wsbh $t0, $t1", -1, t0, t1);
+#endif
+
+ printf("NOT\n");
+ TESTINST3("not $t0, $t1", 0x2, t0, t1);
+ TESTINST3("not $t0, $t1", 0x28, t0, t1);
+ TESTINST3("not $t0, $t1", -258, t0, t1);
+ TESTINST3("not $t0, $t1", 0x7fffffff, t0, t1);
+ TESTINST3("not $t0, $t1", -11, t0, t1);
+ TESTINST3("not $t0, $t1", 0xffffffff, t0, t1);
+ TESTINST3("not $t0, $t1", 0x16, t0, t1);
+ TESTINST3("not $t0, $t1", -1, t0, t1);
+
+ printf("NEGU\n");
+ TESTINST3("negu $t0, $t1", 0x2, t0, t1);
+ TESTINST3("negu $t0, $t1", 0x28, t0, t1);
+ TESTINST3("negu $t0, $t1", -258, t0, t1);
+ TESTINST3("negu $t0, $t1", 0x7fffffff, t0, t1);
+ TESTINST3("negu $t0, $t1", -11, t0, t1);
+ TESTINST3("negu $t0, $t1", 0xffffffff, t0, t1);
+ TESTINST3("negu $t0, $t1", 0x16, t0, t1);
+ TESTINST3("negu $t0, $t1", -1, t0, t1);
+
+ printf("OR\n");
+ TESTINST1("or $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("or $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+
+ printf("ORI\n");
+ TESTINST2("ori $t0, $t1, 0xffff", 0x31415927, 0xffff, t0, t1);
+ TESTINST2("ori $t0, $t1, 0xee00", 0x31415927, 0xee00, t0, t1);
+ TESTINST2("ori $t0, $t1, 255", 0, 255, t0, t1);
+ TESTINST2("ori $t0, $t1, 0", -1, 0, t0, t1);
+ TESTINST2("ori $t0, $t1, 1", 0, 1, t0, t1);
+ TESTINST2("ori $t0, $t1, 0", 0, 0, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x8000", 0x80000000, 0x8000, t0, t1);
+ TESTINST2("ori $t0, $t1, 0", 0x7fffffff, 0, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x8000", 0x80000000, 0x8000, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x8000", 0x7fffffff, 0x8000, t0, t1);
+ TESTINST2("ori $t0, $t1, 0xff00", 0x80000000, 0xff00, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x0dd0", 0x7fffffff, 0x0dd0, t0, t1);
+ TESTINST2("ori $t0, $t1, 0xffff", 0x31415927, 0xffff, t0, t1);
+ TESTINST2("ori $t0, $t1, 0xee00", 0x31415927, 0xee00, t0, t1);
+ TESTINST2("ori $t0, $t1, 255", 0, 255, t0, t1);
+ TESTINST2("ori $t0, $t1, 0", 1, 0, t0, t1);
+ TESTINST2("ori $t0, $t1, 1", 0, 1, t0, t1);
+ TESTINST2("ori $t0, $t1, 0", -1, 0, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x8000", 0, 0x8000, t0, t1);
+ TESTINST2("ori $t0, $t1, 0", 0x8000, 0, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x8000", 0x80000000, 0x8000, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x8000", 0x7fffffff, 0x8000, t0, t1);
+ TESTINST2("ori $t0, $t1, 0xff00", 0x80000000, 0xff00, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x0dd0", 0x7fffffff, 0x0dd0, t0, t1);
+ TESTINST2("ori $t0, $t1, 0", 0xffff, 0, t0, t1);
+ TESTINST2("ori $t0, $t1, 0xffff", 0, 0xffff, t0, t1);
+ TESTINST2("ori $t0, $t1, 0xffff", 0xffffffff, 0xffff, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x7fff", 0x7fffffff, 0x7fff, t0, t1);
+ TESTINST2("ori $t0, $t1, 0x0000", 0x0000ffff, 0x0000, t0, t1);
+
+#if (__mips==32) && (__mips_isa_rev>=2)
+ printf("ROTR\n");
+ TESTINST2("rotr $t0, $t1, 0x00000000", 0x31415927, 0x00000000, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x00000001", 0x31415927, 0x00000001, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x00000002", 0x31415927, 0x00000002, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x0000000F", 0x31415927, 0x0000000F, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x00000010", 0x31415927, 0x00000010, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x0000001F", 0x31415927, 0x0000001F, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x00000020", 0x31415927, 0x00000020, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x00000021", 0x31415927, 0x00000021, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x00000000", 0x00088000, 0x00000000, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0x00000001", 0x00088000, 0x00000001, t0, t1);
+ TESTINST2("rotr $t0, $t1, 31", 0x00088000, 31, t0, t1);
+ TESTINST2("rotr $t0, $t1, 16", 0x00010000, 16, t0, t1);
+ TESTINST2("rotr $t0, $t1, 17", 0x00010000, 17, t0, t1);
+ TESTINST2("rotr $t0, $t1, 18", 0x00010000, 18, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0", 0, 0, t0, t1);
+ TESTINST2("rotr $t0, $t1, 0xffff", 0xffff, 0xffff, t0, t1);
+#endif
+
+#if (__mips==32) && (__mips_isa_rev>=2)
+ printf("ROTRV\n");
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0x00000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0x00000001, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0x00000002, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0x0000000F, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0x00000010, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0x0000001F, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0x00000020, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x31415927, 0x00000021, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x00088000, 0x00000000, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x00088000, 0x00000001, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x00088000, 31, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x00010000, 16, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x00010000, 17, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0x00010000, 18, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("rotrv $t0, $t1, $t2", 0xffff, 0xffff, t0, t1, t2);
+
+ printf("SEB\n");
+ TESTINST3("seb $t0, $t1", 0x2, t0, t1);
+ TESTINST3("seb $t0, $t1", 0x28, t0, t1);
+ TESTINST3("seb $t0, $t1", -258, t0, t1);
+ TESTINST3("seb $t0, $t1", 0x7fffffff, t0, t1);
+ TESTINST3("seb $t0, $t1", -11, t0, t1);
+ TESTINST3("seb $t0, $t1", 0xffffffff, t0, t1);
+ TESTINST3("seb $t0, $t1", 0x16, t0, t1);
+ TESTINST3("seb $t0, $t1", -1, t0, t1);
+
+ printf("SEH\n");
+ TESTINST3("seh $t0, $t1", 0x2, t0, t1);
+ TESTINST3("seh $t0, $t1", 0x28, t0, t1);
+ TESTINST3("seh $t0, $t1", -258, t0, t1);
+ TESTINST3("seh $t0, $t1", 0x7fffffff, t0, t1);
+ TESTINST3("seh $t0, $t1", -11, t0, t1);
+ TESTINST3("seh $t0, $t1", 0xffffffff, t0, t1);
+ TESTINST3("seh $t0, $t1", 0x16, t0, t1);
+ TESTINST3("seh $t0, $t1", -1, t0, t1);
+#endif
+
+ printf("SLL\n");
+ TESTINST2("sll $t0, $t1, 0x00000000", 0x31415927, 0x00000000, t0, t1);
+ TESTINST2("sll $t0, $t1, 0x00000001", 0x31415927, 0x00000001, t0, t1);
+ TESTINST2("sll $t0, $t1, 0x00000002", 0x31415927, 0x00000002, t0, t1);
+ TESTINST2("sll $t0, $t1, 0x0000000F", 0x31415927, 0x0000000F, t0, t1);
+ TESTINST2("sll $t0, $t1, 0x00000010", 0x31415927, 0x00000010, t0, t1);
+ TESTINST2("sll $t0, $t1, 0x0000001F", 0x31415927, 0x0000001F, t0, t1);
+ TESTINST2("sll $t0, $t1, 0x00000009", 0x31415927, 0x00000009, t0, t1);
+ TESTINST2("sll $t0, $t1, 0x0000000A", 0x31415927, 0x0000000A, t0, t1);
+ TESTINST2("sll $t0, $t1, 0x00000000", 0x00088000, 0x00000000, t0, t1);
+ TESTINST2("sll $t0, $t1, 0x00000001", 0x00088000, 0x00000001, t0, t1);
+ TESTINST2("sll $t0, $t1, 31", 0x00088000, 31, t0, t1);
+ TESTINST2("sll $t0, $t1, 16", 0x00010000, 16, t0, t1);
+ TESTINST2("sll $t0, $t1, 17", 0x00010000, 17, t0, t1);
+ TESTINST2("sll $t0, $t1, 18", 0x00010000, 18, t0, t1);
+ TESTINST2("sll $t0, $t1, 0", 0, 0, t0, t1);
+
+ printf("SLLV\n");
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0x00000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0x00000001, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0x00000002, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0x0000000F, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0x00000010, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0x0000001F, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0x00000020, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x31415927, 0x00000021, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x00088000, 0x00000000, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x00088000, 0x00000001, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x00088000, 31, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x00010000, 16, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x00010000, 17, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0x00010000, 18, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("sllv $t0, $t1, $t2", 0xffff, 0xffff, t0, t1, t2);
+
+ printf("SLT\n");
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0x00000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0x00000001, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0x00000002, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0x0000000F, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0x00000010, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0x0000001F, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0x00000020, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x31415927, 0x00000021, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x00088000, 0x00000000, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x00088000, 0x00000001, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x00088000, 31, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x00010000, 16, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x00010000, 17, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0x00010000, 18, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("slt $t0, $t1, $t2", 0xffff, 0xffff, t0, t1, t2);
+
+ printf("SLTI\n");
+ TESTINST2("slti $t0, $t1, 0x00000000", 0x00000001, 0x31415927, t0, t1);
+ TESTINST2("slti $t0, $t1, 0x00000001", 0x31415927, 0x00000001, t0, t1);
+ TESTINST2("slti $t0, $t1, 0x00000002", 0x31415927, 0x00000002, t0, t1);
+ TESTINST2("slti $t0, $t1, 0x0000000F", 0x31415927, 0x0000000F, t0, t1);
+ TESTINST2("slti $t0, $t1, 0x00000010", 0x00000010, 0x00000010, t0, t1);
+ TESTINST2("slti $t0, $t1, 0x0000001F", 0x00000010, 0x31415927, t0, t1);
+ TESTINST2("slti $t0, $t1, 0x00000009", 0x31415927, 0x00000009, t0, t1);
+ TESTINST2("slti $t0, $t1, 0x0000000A", 0x31415927, 0x0000000A, t0, t1);
+ TESTINST2("slti $t0, $t1, 0x00000000", 0x00088000, 0x0000000A, t0, t1);
+ TESTINST2("slti $t0, $t1, 0x00000001", 0x00000000, 0x00000001, t0, t1);
+ TESTINST2("slti $t0, $t1, 31", 0x00088000, 31, t0, t1);
+ TESTINST2("slti $t0, $t1, 16", 0x00010000, 16, t0, t1);
+ TESTINST2("slti $t0, $t1, 17", 0x00010000, 17, t0, t1);
+ TESTINST2("slti $t0, $t1, 18", 0x00010000, 18, t0, t1);
+ TESTINST2("slti $t0, $t1, 0", 0, 0, t0, t1);
+
+ printf("SLTIU\n");
+ TESTINST2("sltiu $t0, $t1, 0x00000000", 0x00000001, 0x31415927, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0x00000001", 0x31415927, 0x00000001, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0x00000002", 0x31415927, 0x00000002, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0x0000000F", 0x31415927, 0x0000000F, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0x00000010", 0x00000010, 0x00000010, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0x0000001F", 0x00000010, 0x31415927, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0x00000009", 0x31415927, 0x00000009, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0x0000000A", 0x31415927, 0x0000000A, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0x00000000", 0x00088000, 0x0000000A, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0x00000001", 0x00000000, 0x00000001, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 31", 0x00088000, 31, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 16", 0x00010000, 16, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 17", 0x00010000, 17, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 18", 0x00010000, 18, t0, t1);
+ TESTINST2("sltiu $t0, $t1, 0", 0, 0, t0, t1);
+
+ printf("SLTU\n");
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0x00000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0x00000001, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0x00000002, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0x0000000F, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0x00000010, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0x0000001F, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0x00000020, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x31415927, 0x00000021, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x00088000, 0x00000000, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x00088000, 0x00000001, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x00088000, 31, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x00010000, 16, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x00010000, 17, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0x00010000, 18, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("sltu $t0, $t1, $t2", 0xffff, 0xffff, t0, t1, t2);
+
+ printf("SRA\n");
+ TESTINST2("sra $t0, $t1, 0x00000000", 0x00000001, 0x31415927, t0, t1);
+ TESTINST2("sra $t0, $t1, 0x00000001", 0x31415927, 0x00000001, t0, t1);
+ TESTINST2("sra $t0, $t1, 0x00000002", 0x31415927, 0x00000002, t0, t1);
+ TESTINST2("sra $t0, $t1, 0x0000000F", 0x31415927, 0x0000000F, t0, t1);
+ TESTINST2("sra $t0, $t1, 0x00000010", 0x00000010, 0x00000010, t0, t1);
+ TESTINST2("sra $t0, $t1, 0x0000001F", 0x00000010, 0x31415927, t0, t1);
+ TESTINST2("sra $t0, $t1, 0x00000009", 0x31415927, 0x00000009, t0, t1);
+ TESTINST2("sra $t0, $t1, 0x0000000A", 0x31415927, 0x0000000A, t0, t1);
+ TESTINST2("sra $t0, $t1, 0x00000000", 0x00088000, 0x0000000A, t0, t1);
+ TESTINST2("sra $t0, $t1, 0x00000001", 0x00000000, 0x00000001, t0, t1);
+ TESTINST2("sra $t0, $t1, 31", 0x00088000, 31, t0, t1);
+ TESTINST2("sra $t0, $t1, 16", 0x00010000, 16, t0, t1);
+ TESTINST2("sra $t0, $t1, 17", 0x00010000, 17, t0, t1);
+ TESTINST2("sra $t0, $t1, 18", 0x00010000, 18, t0, t1);
+ TESTINST2("sra $t0, $t1, 0", 0, 0, t0, t1);
+
+ printf("SRAV\n");
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0x00000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0x00000001, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0x00000002, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0x0000000F, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0x00000010, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0x0000001F, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0x00000020, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x31415927, 0x00000021, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x00088000, 0x00000000, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x00088000, 0x00000001, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x00088000, 31, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x00010000, 16, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x00010000, 17, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0x00010000, 18, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("srav $t0, $t1, $t2", 0xffff, 0xffff, t0, t1, t2);
+
+ printf("SRL\n");
+ TESTINST2("srl $t0, $t1, 0x00000000", 0x00000001, 0x31415927, t0, t1);
+ TESTINST2("srl $t0, $t1, 0x00000001", 0x31415927, 0x00000001, t0, t1);
+ TESTINST2("srl $t0, $t1, 0x00000002", 0x31415927, 0x00000002, t0, t1);
+ TESTINST2("srl $t0, $t1, 0x0000000F", 0x31415927, 0x0000000F, t0, t1);
+ TESTINST2("srl $t0, $t1, 0x00000010", 0x00000010, 0x00000010, t0, t1);
+ TESTINST2("srl $t0, $t1, 0x0000001F", 0x00000010, 0x31415927, t0, t1);
+ TESTINST2("srl $t0, $t1, 0x00000009", 0x31415927, 0x00000009, t0, t1);
+ TESTINST2("srl $t0, $t1, 0x0000000A", 0x31415927, 0x0000000A, t0, t1);
+ TESTINST2("srl $t0, $t1, 0x00000000", 0x00088000, 0x0000000A, t0, t1);
+ TESTINST2("srl $t0, $t1, 0x00000001", 0x00000000, 0x00000001, t0, t1);
+ TESTINST2("srl $t0, $t1, 31", 0x00088000, 31, t0, t1);
+ TESTINST2("srl $t0, $t1, 16", 0x00010000, 16, t0, t1);
+ TESTINST2("srl $t0, $t1, 17", 0x00010000, 17, t0, t1);
+ TESTINST2("srl $t0, $t1, 18", 0x00010000, 18, t0, t1);
+ TESTINST2("srl $t0, $t1, 0", 0, 0, t0, t1);
+
+ printf("SRLV\n");
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0x00000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0x00000001, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0x00000002, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0x0000000F, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0x00000010, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0x0000001F, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0x00000020, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x31415927, 0x00000021, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x00088000, 0x00000000, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x00088000, 0x00000001, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x00088000, 31, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x00010000, 16, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x00010000, 17, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0x00010000, 18, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("srlv $t0, $t1, $t2", 0xffff, 0xffff, t0, t1, t2);
+
+ printf("SUBU\n");
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x00000001, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x00001110, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x00000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x00000001, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x00000002, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x0000000F, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x00000010, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x0000001F, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x00000020, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x00000021, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x00088000, 0x00000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x00088000, 0x00000001, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x00088000, 31, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x00010000, 16, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x00010000, 17, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x00010000, 18, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0xffff, 0xffff, t0, t1, t2);
+
+ printf("SUB\n");
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x27181728, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x31415927, 0x97181728, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x80000000, 0x7fffffff, t0, t1, t2);
+ TESTINST1("subu $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+
+ printf("XOR\n");
+ TESTINST1("xor $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0, 0, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x80000000, -1, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x7fffffff, 0, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x31415927, 0xee00ee00, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0, 255, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 1, 0, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0, 1, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", -1, 0, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0, -1, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x80000000, 0, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x80000000, 0x80000000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x80000000, 0xff000000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x7fffffff, 0x0dd00000, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0xffffffff, 0, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0, 0xffffffff, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0xffffffff, 0xffffffff, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
+ TESTINST1("xor $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
+
+ printf("XORI\n");
+ TESTINST2("xori $t0, $t1, 0xffff", 0x31415927, 0xffff, t0, t1);
+ TESTINST2("xori $t0, $t1, 0xee00", 0x31415927, 0xee00, t0, t1);
+ TESTINST2("xori $t0, $t1, 255", 0, 255, t0, t1);
+ TESTINST2("xori $t0, $t1, 0", -1, 0, t0, t1);
+ TESTINST2("xori $t0, $t1, 1", 0, 1, t0, t1);
+ TESTINST2("xori $t0, $t1, 0", 0, 0, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x8000", 0x80000000, 0x8000, t0, t1);
+ TESTINST2("xori $t0, $t1, 0", 0x7fffffff, 0, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x8000", 0x80000000, 0x8000, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x8000", 0x7fffffff, 0x8000, t0, t1);
+ TESTINST2("xori $t0, $t1, 0xff00", 0x80000000, 0xff00, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x0dd0", 0x7fffffff, 0x0dd0, t0, t1);
+ TESTINST2("xori $t0, $t1, 0xffff", 0x31415927, 0xffff, t0, t1);
+ TESTINST2("xori $t0, $t1, 0xee00", 0x31415927, 0xee00, t0, t1);
+ TESTINST2("xori $t0, $t1, 255", 0, 255, t0, t1);
+ TESTINST2("xori $t0, $t1, 0", 1, 0, t0, t1);
+ TESTINST2("xori $t0, $t1, 1", 0, 1, t0, t1);
+ TESTINST2("xori $t0, $t1, 0", -1, 0, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x8000", 0, 0x8000, t0, t1);
+ TESTINST2("xori $t0, $t1, 0", 0x8000, 0, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x8000", 0x80000000, 0x8000, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x8000", 0x7fffffff, 0x8000, t0, t1);
+ TESTINST2("xori $t0, $t1, 0xff00", 0x80000000, 0xff00, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x0dd0", 0x7fffffff, 0x0dd0, t0, t1);
+ TESTINST2("xori $t0, $t1, 0", 0xffff, 0, t0, t1);
+ TESTINST2("xori $t0, $t1, 0xffff", 0, 0xffff, t0, t1);
+ TESTINST2("xori $t0, $t1, 0xffff", 0xffffffff, 0xffff, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x7fff", 0x7fffffff, 0x7fff, t0, t1);
+ TESTINST2("xori $t0, $t1, 0x0000", 0x0000ffff, 0x0000, t0, t1);
+
+ printf("MFHI MFLO\n");
+ TESTINSN_HILO(0x31415927);
+ TESTINSN_HILO(0);
+ TESTINSN_HILO(-1);
+ TESTINSN_HILO(0xffffffff);
+ TESTINSN_HILO(0x8000);
+ TESTINSN_HILO(0x80000000);
+ TESTINSN_HILO(0x0000ffff);
+ TESTINSN_HILO(0x7fff);
+ TESTINSN_HILO(0x0dd0);
+ TESTINSN_HILO(0xff00);
+
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/mips32/MIPS32int.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/mips32/MIPS32int.stderr.exp
diff --git a/main/none/tests/mips32/MIPS32int.stdout.exp b/main/none/tests/mips32/MIPS32int.stdout.exp
new file mode 100644
index 0000000..af40f50
--- /dev/null
+++ b/main/none/tests/mips32/MIPS32int.stdout.exp
@@ -0,0 +1,1227 @@
+ADD
+add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
+add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
+add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
+add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
+add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+add $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+ADDI
+addi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+addi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+addi $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000000
+addi $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000001
+addi $t0, $t1, -1 :: rt 0xffffffff rs 0x00000000, imm 0xffffffff
+addi $t0, $t1, -1 :: rt 0x00000000 rs 0x00000001, imm 0xffffffff
+addi $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+addi $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+addi $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+ADDIU
+addiu $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+addiu $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000000
+addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000001
+addiu $t0, $t1, -1 :: rt 0xffffffff rs 0x00000000, imm 0xffffffff
+addiu $t0, $t1, -1 :: rt 0x00000000 rs 0x00000001, imm 0xffffffff
+addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+addiu $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+ADDU
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
+addu $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
+addu $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+addu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+addu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0x7fffffff
+addu $t0, $t1, $t2 :: rd 0xfffffffe rs 0x7fffffff, rt 0x7fffffff
+AND
+and $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x20004800 rs 0x31415927, rt 0xee00ee00
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+and $t0, $t1, $t2 :: rd 0x0dd00000 rs 0x7fffffff, rt 0x0dd00000
+and $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x20004800 rs 0x31415927, rt 0xee00ee00
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+and $t0, $t1, $t2 :: rd 0x0dd00000 rs 0x7fffffff, rt 0x0dd00000
+ANDI
+andi $t0, $t1, 1 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
+andi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000001, imm 0x00000000
+andi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000001, imm 0x00000001
+andi $t0, $t1, 1 :: rt 0x00000001 rs 0x7fffffff, imm 0x00000000
+andi $t0, $t1, 0 :: rt 0x00000000 rs 0x80000000, imm 0x00000000
+andi $t0, $t1, 0x3145 :: rt 0x00003145 rs 0xffffffff, imm 0x00003145
+CLO
+clo $t0, $t1 :: rd 0x00000000 rs 0x00000000
+clo $t0, $t1 :: rd 0x00000000 rs 0x00000001
+clo $t0, $t1 :: rd 0x00000000 rs 0x00000010
+clo $t0, $t1 :: rd 0x00000020 rs 0xffffffff
+CLZ
+clz $t0, $t1 :: rd 0x00000020 rs 0x00000000
+clz $t0, $t1 :: rd 0x0000001f rs 0x00000001
+clz $t0, $t1 :: rd 0x0000001b rs 0x00000010
+clz $t0, $t1 :: rd 0x00000000 rs 0xffffffff
+DIV
+div $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x00000003
+div $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x00000000 LO 0x00000001
+div $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0xffffffff
+div $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0xffffffff
+div $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000002 LO 0x00000000
+DIVU
+divu $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x00000003
+divu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x00000000 LO 0x00000001
+divu $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0xffffffff
+divu $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000001 LO 0x00000000
+divu $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000002 LO 0x00000000
+divu $t0, $t1 :: rs 0x00000000 rt 0x00000002 HI 0x00000000 LO 0x00000000
+EXT
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0xffffffff, pos 0x00000002, size 0x00000006
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0xffffffff, pos 0x00000002, size 0x00000006
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0xffffffff, pos 0x0000001f, size 0x00000006
+ext $t0, $t1, 2, 6 :: rt 0x00000000 rs 0x00000000, pos 0x00000020, size 0x00000020
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0x0000ffff, pos 0x0000001f, size 0x00000000
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0x000000ff, pos 0x0000001f, size 0x00000000
+ext $t0, $t1, 2, 6 :: rt 0x00000000 rs 0xf0000000, pos 0x0000001f, size 0x00000000
+ext $t0, $t1, 2, 6 :: rt 0x00000000 rs 0xf0000000, pos 0x00000000, size 0x0000001f
+ext $t0, $t1, 2, 6 :: rt 0x00000009 rs 0x31415927, pos 0x00000003, size 0x00000019
+INS
+ins $t0, $t1, 2, 6 :: rt 0x000000fc rs 0xffffffff, pos 0x00000002, size 0x00000006
+ins $t0, $t1, 2, 6 :: rt 0xffffffff rs 0xffffffff, pos 0x00000002, size 0x00000006
+ins $t0, $t1, 2, 6 :: rt 0x000000fc rs 0xffffffff, pos 0x0000001f, size 0x00000006
+ins $t0, $t1, 2, 6 :: rt 0x00000000 rs 0x00000000, pos 0x00000020, size 0x00000020
+ins $t0, $t1, 2, 6 :: rt 0x000000fc rs 0x0000ffff, pos 0x0000001f, size 0x00000000
+ins $t0, $t1, 2, 6 :: rt 0x000000fc rs 0x000000ff, pos 0x0000001f, size 0x00000000
+ins $t0, $t1, 2, 6 :: rt 0x00000000 rs 0xf0000000, pos 0x0000001f, size 0x00000000
+ins $t0, $t1, 2, 6 :: rt 0x00000000 rs 0xf0000000, pos 0x00000000, size 0x0000001f
+ins $t0, $t1, 2, 6 :: rt 0x0000009c rs 0x31415927, pos 0x00000003, size 0x00000019
+LB
+lb $t0, 0($t1) :: rt 0x0000001f
+lb $t0, 4($t1) :: rt 0x00000000
+lb $t0, 8($t1) :: rt 0x00000003
+lb $t0, 12($t1) :: rt 0xffffffff
+lb $t0, 16($t1) :: rt 0x0000002f
+lb $t0, 20($t1) :: rt 0x0000002b
+lb $t0, 24($t1) :: rt 0x0000002b
+lb $t0, 28($t1) :: rt 0x0000002a
+lb $t0, 32($t1) :: rt 0x0000003e
+lb $t0, 36($t1) :: rt 0x0000003c
+lb $t0, 40($t1) :: rt 0x0000003b
+lb $t0, 44($t1) :: rt 0x0000003a
+lb $t0, 48($t1) :: rt 0x00000045
+lb $t0, 52($t1) :: rt 0x00000046
+lb $t0, 56($t1) :: rt 0x0000004c
+lb $t0, 60($t1) :: rt 0x0000004c
+lb $t0, 64($t1) :: rt 0x00000041
+lb $t0, 2($t1) :: rt 0x0000001f
+lb $t0, 6($t1) :: rt 0x00000000
+lb $t0, 10($t1) :: rt 0x00000000
+lb $t0, 14($t1) :: rt 0xffffffff
+lb $t0, 18($t1) :: rt 0x0000002f
+lb $t0, 22($t1) :: rt 0x0000002c
+lb $t0, 26($t1) :: rt 0x0000002a
+lb $t0, 30($t1) :: rt 0x0000002d
+lb $t0, 34($t1) :: rt 0x00000034
+lb $t0, 38($t1) :: rt 0x00000035
+LBU
+lbu $t0, 0($t1) :: rt 0x0000001f
+lbu $t0, 4($t1) :: rt 0x00000000
+lbu $t0, 8($t1) :: rt 0x00000003
+lbu $t0, 12($t1) :: rt 0x000000ff
+lbu $t0, 16($t1) :: rt 0x0000002f
+lbu $t0, 20($t1) :: rt 0x0000002b
+lbu $t0, 24($t1) :: rt 0x0000002b
+lbu $t0, 28($t1) :: rt 0x0000002a
+lbu $t0, 32($t1) :: rt 0x0000003e
+lbu $t0, 36($t1) :: rt 0x0000003c
+lbu $t0, 40($t1) :: rt 0x0000003b
+lbu $t0, 44($t1) :: rt 0x0000003a
+lbu $t0, 48($t1) :: rt 0x00000045
+lbu $t0, 52($t1) :: rt 0x00000046
+lbu $t0, 56($t1) :: rt 0x0000004c
+lbu $t0, 60($t1) :: rt 0x0000004c
+lbu $t0, 64($t1) :: rt 0x00000041
+lbu $t0, 2($t1) :: rt 0x0000001f
+lbu $t0, 6($t1) :: rt 0x00000000
+lbu $t0, 10($t1) :: rt 0x00000000
+lbu $t0, 14($t1) :: rt 0x000000ff
+lbu $t0, 18($t1) :: rt 0x0000002f
+lbu $t0, 22($t1) :: rt 0x0000002c
+lbu $t0, 26($t1) :: rt 0x0000002a
+lbu $t0, 30($t1) :: rt 0x0000002d
+lbu $t0, 34($t1) :: rt 0x00000034
+lbu $t0, 38($t1) :: rt 0x00000035
+LH
+lh $t0, 0($t1) :: rt 0x00001e1f
+lh $t0, 4($t1) :: rt 0x00000000
+lh $t0, 8($t1) :: rt 0x00000003
+lh $t0, 12($t1) :: rt 0xffffffff
+lh $t0, 16($t1) :: rt 0x00002e2f
+lh $t0, 20($t1) :: rt 0x00002b2b
+lh $t0, 24($t1) :: rt 0x00002e2b
+lh $t0, 28($t1) :: rt 0x00002d2a
+lh $t0, 32($t1) :: rt 0x00003f3e
+lh $t0, 36($t1) :: rt 0x00003d3c
+lh $t0, 40($t1) :: rt 0x00003c3b
+lh $t0, 44($t1) :: rt 0x00003b3a
+lh $t0, 48($t1) :: rt 0x00004e45
+lh $t0, 52($t1) :: rt 0x00004d46
+lh $t0, 56($t1) :: rt 0x0000474c
+lh $t0, 60($t1) :: rt 0x00004a4c
+lh $t0, 64($t1) :: rt 0x00004441
+lh $t0, 2($t1) :: rt 0x0000121f
+lh $t0, 6($t1) :: rt 0x00000000
+lh $t0, 10($t1) :: rt 0x00000000
+lh $t0, 14($t1) :: rt 0xffffffff
+lh $t0, 18($t1) :: rt 0x0000232f
+lh $t0, 22($t1) :: rt 0x0000242c
+lh $t0, 26($t1) :: rt 0x0000252a
+lh $t0, 30($t1) :: rt 0x0000262d
+lh $t0, 34($t1) :: rt 0x00003f34
+lh $t0, 38($t1) :: rt 0x00003e35
+LHU
+lhu $t0, 0($t1) :: rt 0x00001e1f
+lhu $t0, 4($t1) :: rt 0x00000000
+lhu $t0, 8($t1) :: rt 0x00000003
+lhu $t0, 12($t1) :: rt 0x0000ffff
+lhu $t0, 16($t1) :: rt 0x00002e2f
+lhu $t0, 20($t1) :: rt 0x00002b2b
+lhu $t0, 24($t1) :: rt 0x00002e2b
+lhu $t0, 28($t1) :: rt 0x00002d2a
+lhu $t0, 32($t1) :: rt 0x00003f3e
+lhu $t0, 36($t1) :: rt 0x00003d3c
+lhu $t0, 40($t1) :: rt 0x00003c3b
+lhu $t0, 44($t1) :: rt 0x00003b3a
+lhu $t0, 48($t1) :: rt 0x00004e45
+lhu $t0, 52($t1) :: rt 0x00004d46
+lhu $t0, 56($t1) :: rt 0x0000474c
+lhu $t0, 60($t1) :: rt 0x00004a4c
+lhu $t0, 64($t1) :: rt 0x00004441
+lhu $t0, 2($t1) :: rt 0x0000121f
+lhu $t0, 6($t1) :: rt 0x00000000
+lhu $t0, 10($t1) :: rt 0x00000000
+lhu $t0, 14($t1) :: rt 0x0000ffff
+lhu $t0, 18($t1) :: rt 0x0000232f
+lhu $t0, 22($t1) :: rt 0x0000242c
+lhu $t0, 26($t1) :: rt 0x0000252a
+lhu $t0, 30($t1) :: rt 0x0000262d
+lhu $t0, 34($t1) :: rt 0x00003f34
+lhu $t0, 38($t1) :: rt 0x00003e35
+LUI
+lui $t0, 0xffff :: rd 0xffff0000 rs 0x0000ffff
+lui $t0, 0xff00 :: rd 0xff000000 rs 0x0000ff00
+lui $t0, 0xff :: rd 0x00ff0000 rs 0x000000ff
+lui $t0, 0x0 :: rd 0x00000000 rs 0x00000000
+lui $t0, 0x5 :: rd 0x00050000 rs 0x00000005
+lui $t0, 0x387 :: rd 0x03870000 rs 0x00000387
+LW
+lw $t0, 0($t1) :: rt 0x121f1e1f
+lw $t0, 4($t1) :: rt 0x00000000
+lw $t0, 8($t1) :: rt 0x00000003
+lw $t0, 12($t1) :: rt 0xffffffff
+lw $t0, 16($t1) :: rt 0x232f2e2f
+lw $t0, 20($t1) :: rt 0x242c2b2b
+lw $t0, 24($t1) :: rt 0x252a2e2b
+lw $t0, 28($t1) :: rt 0x262d2d2a
+lw $t0, 32($t1) :: rt 0x3f343f3e
+lw $t0, 36($t1) :: rt 0x3e353d3c
+lw $t0, 40($t1) :: rt 0x363a3c3b
+lw $t0, 44($t1) :: rt 0x3b373b3a
+lw $t0, 48($t1) :: rt 0x454f4e45
+lw $t0, 52($t1) :: rt 0x4e464d46
+lw $t0, 56($t1) :: rt 0x474d474c
+lw $t0, 60($t1) :: rt 0x4a484a4c
+lw $t0, 64($t1) :: rt 0x00444441
+lw $t0, 2($t1) :: rt 0x0000121f
+lw $t0, 6($t1) :: rt 0x00030000
+lw $t0, 10($t1) :: rt 0xffff0000
+lw $t0, 14($t1) :: rt 0x2e2fffff
+lw $t0, 18($t1) :: rt 0x2b2b232f
+lw $t0, 22($t1) :: rt 0x2e2b242c
+lw $t0, 26($t1) :: rt 0x2d2a252a
+lw $t0, 30($t1) :: rt 0x3f3e262d
+lw $t0, 34($t1) :: rt 0x3d3c3f34
+lw $t0, 38($t1) :: rt 0x3c3b3e35
+LWL
+lwl $t0, 0($t1) :: rt 0x1f000000
+lwl $t0, 4($t1) :: rt 0x00000000
+lwl $t0, 8($t1) :: rt 0x03000000
+lwl $t0, 12($t1) :: rt 0xff000000
+lwl $t0, 16($t1) :: rt 0x2f000000
+lwl $t0, 20($t1) :: rt 0x2b000000
+lwl $t0, 24($t1) :: rt 0x2b000000
+lwl $t0, 28($t1) :: rt 0x2a000000
+lwl $t0, 32($t1) :: rt 0x3e000000
+lwl $t0, 36($t1) :: rt 0x3c000000
+lwl $t0, 40($t1) :: rt 0x3b000000
+lwl $t0, 44($t1) :: rt 0x3a000000
+lwl $t0, 48($t1) :: rt 0x45000000
+lwl $t0, 52($t1) :: rt 0x46000000
+lwl $t0, 56($t1) :: rt 0x4c000000
+lwl $t0, 60($t1) :: rt 0x4c000000
+lwl $t0, 64($t1) :: rt 0x41000000
+lwl $t0, 2($t1) :: rt 0x1f1e1f00
+lwl $t0, 6($t1) :: rt 0x00000000
+lwl $t0, 10($t1) :: rt 0x00000300
+lwl $t0, 14($t1) :: rt 0xffffff00
+lwl $t0, 18($t1) :: rt 0x2f2e2f00
+lwl $t0, 22($t1) :: rt 0x2c2b2b00
+lwl $t0, 26($t1) :: rt 0x2a2e2b00
+lwl $t0, 30($t1) :: rt 0x2d2d2a00
+lwl $t0, 34($t1) :: rt 0x343f3e00
+lwl $t0, 38($t1) :: rt 0x353d3c00
+LWR
+lwr $t0, 0($t1) :: rt 0x121f1e1f
+lwr $t0, 4($t1) :: rt 0x00000000
+lwr $t0, 8($t1) :: rt 0x00000003
+lwr $t0, 12($t1) :: rt 0xffffffff
+lwr $t0, 16($t1) :: rt 0x232f2e2f
+lwr $t0, 20($t1) :: rt 0x242c2b2b
+lwr $t0, 24($t1) :: rt 0x252a2e2b
+lwr $t0, 28($t1) :: rt 0x262d2d2a
+lwr $t0, 32($t1) :: rt 0x3f343f3e
+lwr $t0, 36($t1) :: rt 0x3e353d3c
+lwr $t0, 40($t1) :: rt 0x363a3c3b
+lwr $t0, 44($t1) :: rt 0x3b373b3a
+lwr $t0, 48($t1) :: rt 0x454f4e45
+lwr $t0, 52($t1) :: rt 0x4e464d46
+lwr $t0, 56($t1) :: rt 0x474d474c
+lwr $t0, 60($t1) :: rt 0x4a484a4c
+lwr $t0, 64($t1) :: rt 0x00444441
+lwr $t0, 2($t1) :: rt 0x0000121f
+lwr $t0, 6($t1) :: rt 0x00000000
+lwr $t0, 10($t1) :: rt 0x00000000
+lwr $t0, 14($t1) :: rt 0x0000ffff
+lwr $t0, 18($t1) :: rt 0x0000232f
+lwr $t0, 22($t1) :: rt 0x0000242c
+lwr $t0, 26($t1) :: rt 0x0000252a
+lwr $t0, 30($t1) :: rt 0x0000262d
+lwr $t0, 34($t1) :: rt 0x00003f34
+lwr $t0, 38($t1) :: rt 0x00003e35
+MADD
+madd $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
+madd $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
+madd $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0x00000000 LO 0x00017fe8
+madd $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+madd $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0xffffffff LO 0xffffffff
+madd $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0xffffffff LO 0xffffffff
+madd $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000000 LO 0x0000000c
+madd $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0x00000000 LO 0x0011c98e
+MADDU
+maddu $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
+maddu $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
+maddu $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0x00000000 LO 0x00017fe8
+maddu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+maddu $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0xffffffff
+maddu $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0xffffffff
+maddu $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000000 LO 0x0000000c
+maddu $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0x00000000 LO 0x0011c98e
+MOVN
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+MOVZ
+movz $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+movz $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xee00ee00
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+MSUB
+msub $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0xffffffff LO 0xfffffff4
+msub $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0xffffffff LO 0xfffff2b8
+msub $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0xffffffff LO 0xfffe8018
+msub $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0xc0000000 LO 0xffffffff
+msub $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0x00000001
+msub $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0x00000001
+msub $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0xffffffff LO 0xfffffff4
+msub $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0xffffffff LO 0xffee3672
+MSUBU
+msubu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xcebea6d9 LO 0x31415927
+msubu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xd2351152 LO 0xfd1dbe00
+msubu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x80000000 LO 0x80000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0xc0000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0xc0000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x80800000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0xf9180000 LO 0x0dd00000
+msubu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xcebea6d9 LO 0x31415927
+msubu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xd2351152 LO 0xfd1dbe00
+msubu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000001 rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x80000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0xc0000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x80800000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0xf9180000 LO 0x0dd00000
+msubu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0xffffffff rt 0xffffffff HI 0x00000001 LO 0xffffffff
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0xc0000000 LO 0xffffffff
+msubu $t0, $t1 :: rs 0x0000ffff rt 0x0000ffff HI 0xffffffff LO 0x0001ffff
+MUL
+mul $t0, $t1, $t2 :: rd 0xcebea6d9 rs 0x31415927, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x02e24200 rs 0x31415927, rt 0xee00ee00
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xff000000
+mul $t0, $t1, $t2 :: rd 0xf2300000 rs 0x7fffffff, rt 0x0dd00000
+mul $t0, $t1, $t2 :: rd 0xcebea6d9 rs 0x31415927, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x02e24200 rs 0x31415927, rt 0xee00ee00
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xff000000
+mul $t0, $t1, $t2 :: rd 0xf2300000 rs 0x7fffffff, rt 0x0dd00000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000001 rs 0x7fffffff, rt 0x7fffffff
+mul $t0, $t1, $t2 :: rd 0xfffe0001 rs 0x0000ffff, rt 0x0000ffff
+MULT
+mult $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xffffffff LO 0xcebea6d9
+mult $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xfc899586 LO 0x02e24200
+mult $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x00000000 LO 0x80000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+mult $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x00800000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+mult $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xffffffff LO 0xcebea6d9
+mult $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xfc899586 LO 0x02e24200
+mult $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000001 rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x80000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+mult $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x00800000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+mult $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0xffffffff rt 0xffffffff HI 0x00000000 LO 0x00000001
+mult $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+mult $t0, $t1 :: rs 0x0000ffff rt 0x0000ffff HI 0x00000000 LO 0xfffe0001
+MULTU
+multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
+multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
+multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x7fffffff LO 0x80000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0x3fffffff LO 0x80000000
+multu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x7f800000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
+multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
+multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000001 rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x80000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0x3fffffff LO 0x80000000
+multu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x7f800000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0xffffffff rt 0xffffffff HI 0xfffffffe LO 0x00000001
+multu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+multu $t0, $t1 :: rs 0x0000ffff rt 0x0000ffff HI 0x00000000 LO 0xfffe0001
+NOR
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x00be00d8 rs 0x31415927, rt 0xee00ee00
+nor $t0, $t1, $t2 :: rd 0xffffff00 rs 0x00000000, rt 0x000000ff
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0xfffffffe rs 0x00000000, rt 0x00000001
+nor $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00ffffff rs 0x80000000, rt 0xff000000
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x0dd00000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x00be00d8 rs 0x31415927, rt 0xee00ee00
+nor $t0, $t1, $t2 :: rd 0xffffff00 rs 0x00000000, rt 0x000000ff
+nor $t0, $t1, $t2 :: rd 0xfffffffe rs 0x00000001, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0xfffffffe rs 0x00000000, rt 0x00000001
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x00000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00ffffff rs 0x80000000, rt 0xff000000
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x0dd00000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x7fffffff
+nor $t0, $t1, $t2 :: rd 0xffff0000 rs 0x0000ffff, rt 0x0000ffff
+WSBH
+wsbh $t0, $t1 :: rd 0x00000200 rs 0x00000002
+wsbh $t0, $t1 :: rd 0x00002800 rs 0x00000028
+wsbh $t0, $t1 :: rd 0xfffffefe rs 0xfffffefe
+wsbh $t0, $t1 :: rd 0xff7fffff rs 0x7fffffff
+wsbh $t0, $t1 :: rd 0xfffff5ff rs 0xfffffff5
+wsbh $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+wsbh $t0, $t1 :: rd 0x00001600 rs 0x00000016
+wsbh $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+NOT
+not $t0, $t1 :: rd 0xfffffffd rs 0x00000002
+not $t0, $t1 :: rd 0xffffffd7 rs 0x00000028
+not $t0, $t1 :: rd 0x00000101 rs 0xfffffefe
+not $t0, $t1 :: rd 0x80000000 rs 0x7fffffff
+not $t0, $t1 :: rd 0x0000000a rs 0xfffffff5
+not $t0, $t1 :: rd 0x00000000 rs 0xffffffff
+not $t0, $t1 :: rd 0xffffffe9 rs 0x00000016
+not $t0, $t1 :: rd 0x00000000 rs 0xffffffff
+NEGU
+negu $t0, $t1 :: rd 0xfffffffe rs 0x00000002
+negu $t0, $t1 :: rd 0xffffffd8 rs 0x00000028
+negu $t0, $t1 :: rd 0x00000102 rs 0xfffffefe
+negu $t0, $t1 :: rd 0x80000001 rs 0x7fffffff
+negu $t0, $t1 :: rd 0x0000000b rs 0xfffffff5
+negu $t0, $t1 :: rd 0x00000001 rs 0xffffffff
+negu $t0, $t1 :: rd 0xffffffea rs 0x00000016
+negu $t0, $t1 :: rd 0x00000001 rs 0xffffffff
+OR
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x31415927, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0xff41ff27 rs 0x31415927, rt 0xee00ee00
+or $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+or $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xff000000 rs 0x80000000, rt 0xff000000
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x31415927, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0xff41ff27 rs 0x31415927, rt 0xee00ee00
+or $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+or $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xff000000 rs 0x80000000, rt 0xff000000
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x7fffffff
+or $t0, $t1, $t2 :: rd 0x0000ffff rs 0x0000ffff, rt 0x0000ffff
+ORI
+ori $t0, $t1, 0xffff :: rt 0x3141ffff rs 0x31415927, imm 0x0000ffff
+ori $t0, $t1, 0xee00 :: rt 0x3141ff27 rs 0x31415927, imm 0x0000ee00
+ori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+ori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+ori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+ori $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+ori $t0, $t1, 0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+ori $t0, $t1, 0x8000 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00008000
+ori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+ori $t0, $t1, 0x0dd0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000dd0
+ori $t0, $t1, 0xffff :: rt 0x3141ffff rs 0x31415927, imm 0x0000ffff
+ori $t0, $t1, 0xee00 :: rt 0x3141ff27 rs 0x31415927, imm 0x0000ee00
+ori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+ori $t0, $t1, 0 :: rt 0x00000001 rs 0x00000001, imm 0x00000000
+ori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+ori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x00008000 rs 0x00000000, imm 0x00008000
+ori $t0, $t1, 0 :: rt 0x00008000 rs 0x00008000, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+ori $t0, $t1, 0x8000 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00008000
+ori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+ori $t0, $t1, 0x0dd0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000dd0
+ori $t0, $t1, 0 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+ori $t0, $t1, 0xffff :: rt 0x0000ffff rs 0x00000000, imm 0x0000ffff
+ori $t0, $t1, 0xffff :: rt 0xffffffff rs 0xffffffff, imm 0x0000ffff
+ori $t0, $t1, 0x7fff :: rt 0x7fffffff rs 0x7fffffff, imm 0x00007fff
+ori $t0, $t1, 0x0000 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+ROTR
+rotr $t0, $t1, 0x00000000 :: rt 0x31415927 rs 0x31415927, imm 0x00000000
+rotr $t0, $t1, 0x00000001 :: rt 0x98a0ac93 rs 0x31415927, imm 0x00000001
+rotr $t0, $t1, 0x00000002 :: rt 0xcc505649 rs 0x31415927, imm 0x00000002
+rotr $t0, $t1, 0x0000000F :: rt 0xb24e6282 rs 0x31415927, imm 0x0000000f
+rotr $t0, $t1, 0x00000010 :: rt 0x59273141 rs 0x31415927, imm 0x00000010
+rotr $t0, $t1, 0x0000001F :: rt 0x6282b24e rs 0x31415927, imm 0x0000001f
+rotr $t0, $t1, 0x00000020 :: rt 0x31415927 rs 0x31415927, imm 0x00000020
+rotr $t0, $t1, 0x00000021 :: rt 0x98a0ac93 rs 0x31415927, imm 0x00000021
+rotr $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x00000000
+rotr $t0, $t1, 0x00000001 :: rt 0x00044000 rs 0x00088000, imm 0x00000001
+rotr $t0, $t1, 31 :: rt 0x00110000 rs 0x00088000, imm 0x0000001f
+rotr $t0, $t1, 16 :: rt 0x00000001 rs 0x00010000, imm 0x00000010
+rotr $t0, $t1, 17 :: rt 0x80000000 rs 0x00010000, imm 0x00000011
+rotr $t0, $t1, 18 :: rt 0x40000000 rs 0x00010000, imm 0x00000012
+rotr $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+rotr $t0, $t1, 0xffff :: rt 0x0001fffe rs 0x0000ffff, imm 0x0000ffff
+ROTRV
+rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0xfffffffe rs 0x7fffffff, rt 0x7fffffff
+rotrv $t0, $t1, $t2 :: rd 0x0001fffe rs 0x0000ffff, rt 0x0000ffff
+rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x98a0ac93 rs 0x31415927, rt 0x00000001
+rotrv $t0, $t1, $t2 :: rd 0xcc505649 rs 0x31415927, rt 0x00000002
+rotrv $t0, $t1, $t2 :: rd 0xb24e6282 rs 0x31415927, rt 0x0000000f
+rotrv $t0, $t1, $t2 :: rd 0x59273141 rs 0x31415927, rt 0x00000010
+rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0x0000001f
+rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+rotrv $t0, $t1, $t2 :: rd 0x98a0ac93 rs 0x31415927, rt 0x00000021
+rotrv $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00044000 rs 0x00088000, rt 0x00000001
+rotrv $t0, $t1, $t2 :: rd 0x00110000 rs 0x00088000, rt 0x0000001f
+rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00010000, rt 0x00000010
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x00010000, rt 0x00000011
+rotrv $t0, $t1, $t2 :: rd 0x40000000 rs 0x00010000, rt 0x00000012
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x0001fffe rs 0x0000ffff, rt 0x0000ffff
+SEB
+seb $t0, $t1 :: rd 0x00000002 rs 0x00000002
+seb $t0, $t1 :: rd 0x00000028 rs 0x00000028
+seb $t0, $t1 :: rd 0xfffffffe rs 0xfffffefe
+seb $t0, $t1 :: rd 0xffffffff rs 0x7fffffff
+seb $t0, $t1 :: rd 0xfffffff5 rs 0xfffffff5
+seb $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+seb $t0, $t1 :: rd 0x00000016 rs 0x00000016
+seb $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+SEH
+seh $t0, $t1 :: rd 0x00000002 rs 0x00000002
+seh $t0, $t1 :: rd 0x00000028 rs 0x00000028
+seh $t0, $t1 :: rd 0xfffffefe rs 0xfffffefe
+seh $t0, $t1 :: rd 0xffffffff rs 0x7fffffff
+seh $t0, $t1 :: rd 0xfffffff5 rs 0xfffffff5
+seh $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+seh $t0, $t1 :: rd 0x00000016 rs 0x00000016
+seh $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+SLL
+sll $t0, $t1, 0x00000000 :: rt 0x31415927 rs 0x31415927, imm 0x00000000
+sll $t0, $t1, 0x00000001 :: rt 0x6282b24e rs 0x31415927, imm 0x00000001
+sll $t0, $t1, 0x00000002 :: rt 0xc505649c rs 0x31415927, imm 0x00000002
+sll $t0, $t1, 0x0000000F :: rt 0xac938000 rs 0x31415927, imm 0x0000000f
+sll $t0, $t1, 0x00000010 :: rt 0x59270000 rs 0x31415927, imm 0x00000010
+sll $t0, $t1, 0x0000001F :: rt 0x80000000 rs 0x31415927, imm 0x0000001f
+sll $t0, $t1, 0x00000009 :: rt 0x82b24e00 rs 0x31415927, imm 0x00000009
+sll $t0, $t1, 0x0000000A :: rt 0x05649c00 rs 0x31415927, imm 0x0000000a
+sll $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x00000000
+sll $t0, $t1, 0x00000001 :: rt 0x00110000 rs 0x00088000, imm 0x00000001
+sll $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+sll $t0, $t1, 16 :: rt 0x00000000 rs 0x00010000, imm 0x00000010
+sll $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+sll $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+sll $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SLLV
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+sllv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0xffffffff, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x7fffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x0000ffff, rt 0x0000ffff
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0xc505649c rs 0x31415927, rt 0x00000002
+sllv $t0, $t1, $t2 :: rd 0xac938000 rs 0x31415927, rt 0x0000000f
+sllv $t0, $t1, $t2 :: rd 0x59270000 rs 0x31415927, rt 0x00000010
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0x0000001f
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+sllv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0x00000021
+sllv $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00110000 rs 0x00088000, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000010
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x0000ffff, rt 0x0000ffff
+SLT
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xee00ee00
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xee00ee00
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000002
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000000f
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000010
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000020
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000021
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000010
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SLTI
+slti $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00000001, imm 0x31415927
+slti $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x31415927, imm 0x00000001
+slti $t0, $t1, 0x00000002 :: rt 0x00000000 rs 0x31415927, imm 0x00000002
+slti $t0, $t1, 0x0000000F :: rt 0x00000000 rs 0x31415927, imm 0x0000000f
+slti $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+slti $t0, $t1, 0x0000001F :: rt 0x00000001 rs 0x00000010, imm 0x31415927
+slti $t0, $t1, 0x00000009 :: rt 0x00000000 rs 0x31415927, imm 0x00000009
+slti $t0, $t1, 0x0000000A :: rt 0x00000000 rs 0x31415927, imm 0x0000000a
+slti $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00088000, imm 0x0000000a
+slti $t0, $t1, 0x00000001 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+slti $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+slti $t0, $t1, 16 :: rt 0x00000000 rs 0x00010000, imm 0x00000010
+slti $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+slti $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+slti $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SLTIU
+sltiu $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00000001, imm 0x31415927
+sltiu $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x31415927, imm 0x00000001
+sltiu $t0, $t1, 0x00000002 :: rt 0x00000000 rs 0x31415927, imm 0x00000002
+sltiu $t0, $t1, 0x0000000F :: rt 0x00000000 rs 0x31415927, imm 0x0000000f
+sltiu $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+sltiu $t0, $t1, 0x0000001F :: rt 0x00000001 rs 0x00000010, imm 0x31415927
+sltiu $t0, $t1, 0x00000009 :: rt 0x00000000 rs 0x31415927, imm 0x00000009
+sltiu $t0, $t1, 0x0000000A :: rt 0x00000000 rs 0x31415927, imm 0x0000000a
+sltiu $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00088000, imm 0x0000000a
+sltiu $t0, $t1, 0x00000001 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+sltiu $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+sltiu $t0, $t1, 16 :: rt 0x00000000 rs 0x00010000, imm 0x00000010
+sltiu $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+sltiu $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+sltiu $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SLTU
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x7fffffff, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x7fffffff, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000002
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000000f
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000010
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000020
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000021
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000010
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SRA
+sra $t0, $t1, 0x00000000 :: rt 0x00000001 rs 0x00000001, imm 0x31415927
+sra $t0, $t1, 0x00000001 :: rt 0x18a0ac93 rs 0x31415927, imm 0x00000001
+sra $t0, $t1, 0x00000002 :: rt 0x0c505649 rs 0x31415927, imm 0x00000002
+sra $t0, $t1, 0x0000000F :: rt 0x00006282 rs 0x31415927, imm 0x0000000f
+sra $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+sra $t0, $t1, 0x0000001F :: rt 0x00000000 rs 0x00000010, imm 0x31415927
+sra $t0, $t1, 0x00000009 :: rt 0x0018a0ac rs 0x31415927, imm 0x00000009
+sra $t0, $t1, 0x0000000A :: rt 0x000c5056 rs 0x31415927, imm 0x0000000a
+sra $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x0000000a
+sra $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
+sra $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+sra $t0, $t1, 16 :: rt 0x00000001 rs 0x00010000, imm 0x00000010
+sra $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+sra $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+sra $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SRAV
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srav $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0x0c505649 rs 0x31415927, rt 0x00000002
+srav $t0, $t1, $t2 :: rd 0x00006282 rs 0x31415927, rt 0x0000000f
+srav $t0, $t1, $t2 :: rd 0x00003141 rs 0x31415927, rt 0x00000010
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+srav $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000021
+srav $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00044000 rs 0x00088000, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+srav $t0, $t1, $t2 :: rd 0x00000001 rs 0x00010000, rt 0x00000010
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SRL
+srl $t0, $t1, 0x00000000 :: rt 0x00000001 rs 0x00000001, imm 0x31415927
+srl $t0, $t1, 0x00000001 :: rt 0x18a0ac93 rs 0x31415927, imm 0x00000001
+srl $t0, $t1, 0x00000002 :: rt 0x0c505649 rs 0x31415927, imm 0x00000002
+srl $t0, $t1, 0x0000000F :: rt 0x00006282 rs 0x31415927, imm 0x0000000f
+srl $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+srl $t0, $t1, 0x0000001F :: rt 0x00000000 rs 0x00000010, imm 0x31415927
+srl $t0, $t1, 0x00000009 :: rt 0x0018a0ac rs 0x31415927, imm 0x00000009
+srl $t0, $t1, 0x0000000A :: rt 0x000c5056 rs 0x31415927, imm 0x0000000a
+srl $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x0000000a
+srl $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
+srl $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+srl $t0, $t1, 16 :: rt 0x00000001 rs 0x00010000, imm 0x00000010
+srl $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+srl $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+srl $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SRLV
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0x0c505649 rs 0x31415927, rt 0x00000002
+srlv $t0, $t1, $t2 :: rd 0x00006282 rs 0x31415927, rt 0x0000000f
+srlv $t0, $t1, $t2 :: rd 0x00003141 rs 0x31415927, rt 0x00000010
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+srlv $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000021
+srlv $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00044000 rs 0x00088000, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00010000, rt 0x00000010
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SUBU
+subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x31414817 rs 0x31415927, rt 0x00001110
+subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x80000001 rs 0x80000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x81000000 rs 0x80000000, rt 0xff000000
+subu $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+subu $t0, $t1, $t2 :: rd 0x31415928 rs 0x31415927, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x43406b27 rs 0x31415927, rt 0xee00ee00
+subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x81000000 rs 0x80000000, rt 0xff000000
+subu $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+subu $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x31415925 rs 0x31415927, rt 0x00000002
+subu $t0, $t1, $t2 :: rd 0x31415918 rs 0x31415927, rt 0x0000000f
+subu $t0, $t1, $t2 :: rd 0x31415917 rs 0x31415927, rt 0x00000010
+subu $t0, $t1, $t2 :: rd 0x31415908 rs 0x31415927, rt 0x0000001f
+subu $t0, $t1, $t2 :: rd 0x31415907 rs 0x31415927, rt 0x00000020
+subu $t0, $t1, $t2 :: rd 0x31415906 rs 0x31415927, rt 0x00000021
+subu $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00087fff rs 0x00088000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x00087fe1 rs 0x00088000, rt 0x0000001f
+subu $t0, $t1, $t2 :: rd 0x0000fff0 rs 0x00010000, rt 0x00000010
+subu $t0, $t1, $t2 :: rd 0x0000ffef rs 0x00010000, rt 0x00000011
+subu $t0, $t1, $t2 :: rd 0x0000ffee rs 0x00010000, rt 0x00000012
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SUB
+subu $t0, $t1, $t2 :: rd 0x31415928 rs 0x31415927, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x0a2941ff rs 0x31415927, rt 0x27181728
+subu $t0, $t1, $t2 :: rd 0x9a2941ff rs 0x31415927, rt 0x97181728
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0x7fffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+XOR
+xor $t0, $t1, $t2 :: rd 0xcebea6d8 rs 0x31415927, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0xdf41b727 rs 0x31415927, rt 0xee00ee00
+xor $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x7f000000 rs 0x80000000, rt 0xff000000
+xor $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+xor $t0, $t1, $t2 :: rd 0xcebea6d8 rs 0x31415927, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0xdf41b727 rs 0x31415927, rt 0xee00ee00
+xor $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+xor $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x7f000000 rs 0x80000000, rt 0xff000000
+xor $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+XORI
+xori $t0, $t1, 0xffff :: rt 0x3141a6d8 rs 0x31415927, imm 0x0000ffff
+xori $t0, $t1, 0xee00 :: rt 0x3141b727 rs 0x31415927, imm 0x0000ee00
+xori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+xori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+xori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+xori $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+xori $t0, $t1, 0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+xori $t0, $t1, 0x8000 :: rt 0x7fff7fff rs 0x7fffffff, imm 0x00008000
+xori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+xori $t0, $t1, 0x0dd0 :: rt 0x7ffff22f rs 0x7fffffff, imm 0x00000dd0
+xori $t0, $t1, 0xffff :: rt 0x3141a6d8 rs 0x31415927, imm 0x0000ffff
+xori $t0, $t1, 0xee00 :: rt 0x3141b727 rs 0x31415927, imm 0x0000ee00
+xori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+xori $t0, $t1, 0 :: rt 0x00000001 rs 0x00000001, imm 0x00000000
+xori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+xori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x00008000 rs 0x00000000, imm 0x00008000
+xori $t0, $t1, 0 :: rt 0x00008000 rs 0x00008000, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+xori $t0, $t1, 0x8000 :: rt 0x7fff7fff rs 0x7fffffff, imm 0x00008000
+xori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+xori $t0, $t1, 0x0dd0 :: rt 0x7ffff22f rs 0x7fffffff, imm 0x00000dd0
+xori $t0, $t1, 0 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+xori $t0, $t1, 0xffff :: rt 0x0000ffff rs 0x00000000, imm 0x0000ffff
+xori $t0, $t1, 0xffff :: rt 0xffff0000 rs 0xffffffff, imm 0x0000ffff
+xori $t0, $t1, 0x7fff :: rt 0x7fff8000 rs 0x7fffffff, imm 0x00007fff
+xori $t0, $t1, 0x0000 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+MFHI MFLO
+mfhi mflo :: HI: 0x31415927, LO: 0x31415926
+mfhi mflo :: HI: 0x0, LO: 0xffffffff
+mfhi mflo :: HI: 0xffffffff, LO: 0xfffffffe
+mfhi mflo :: HI: 0xffffffff, LO: 0xfffffffe
+mfhi mflo :: HI: 0x8000, LO: 0x7fff
+mfhi mflo :: HI: 0x80000000, LO: 0x7fffffff
+mfhi mflo :: HI: 0xffff, LO: 0xfffe
+mfhi mflo :: HI: 0x7fff, LO: 0x7ffe
+mfhi mflo :: HI: 0xdd0, LO: 0xdcf
+mfhi mflo :: HI: 0xff00, LO: 0xfeff
diff --git a/main/none/tests/mips32/MIPS32int.stdout.exp-BE b/main/none/tests/mips32/MIPS32int.stdout.exp-BE
new file mode 100644
index 0000000..923653a
--- /dev/null
+++ b/main/none/tests/mips32/MIPS32int.stdout.exp-BE
@@ -0,0 +1,1227 @@
+ADD
+add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
+add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
+add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
+add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
+add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+add $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+ADDI
+addi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+addi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+addi $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000000
+addi $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000001
+addi $t0, $t1, -1 :: rt 0xffffffff rs 0x00000000, imm 0xffffffff
+addi $t0, $t1, -1 :: rt 0x00000000 rs 0x00000001, imm 0xffffffff
+addi $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+addi $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+addi $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+ADDIU
+addiu $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+addiu $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000000
+addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000001
+addiu $t0, $t1, -1 :: rt 0xffffffff rs 0x00000000, imm 0xffffffff
+addiu $t0, $t1, -1 :: rt 0x00000000 rs 0x00000001, imm 0xffffffff
+addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+addiu $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+ADDU
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
+addu $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
+addu $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+addu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+addu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0x7fffffff
+addu $t0, $t1, $t2 :: rd 0xfffffffe rs 0x7fffffff, rt 0x7fffffff
+AND
+and $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x20004800 rs 0x31415927, rt 0xee00ee00
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+and $t0, $t1, $t2 :: rd 0x0dd00000 rs 0x7fffffff, rt 0x0dd00000
+and $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x20004800 rs 0x31415927, rt 0xee00ee00
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+and $t0, $t1, $t2 :: rd 0x0dd00000 rs 0x7fffffff, rt 0x0dd00000
+ANDI
+andi $t0, $t1, 1 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
+andi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000001, imm 0x00000000
+andi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000001, imm 0x00000001
+andi $t0, $t1, 1 :: rt 0x00000001 rs 0x7fffffff, imm 0x00000000
+andi $t0, $t1, 0 :: rt 0x00000000 rs 0x80000000, imm 0x00000000
+andi $t0, $t1, 0x3145 :: rt 0x00003145 rs 0xffffffff, imm 0x00003145
+CLO
+clo $t0, $t1 :: rd 0x00000000 rs 0x00000000
+clo $t0, $t1 :: rd 0x00000000 rs 0x00000001
+clo $t0, $t1 :: rd 0x00000000 rs 0x00000010
+clo $t0, $t1 :: rd 0x00000020 rs 0xffffffff
+CLZ
+clz $t0, $t1 :: rd 0x00000020 rs 0x00000000
+clz $t0, $t1 :: rd 0x0000001f rs 0x00000001
+clz $t0, $t1 :: rd 0x0000001b rs 0x00000010
+clz $t0, $t1 :: rd 0x00000000 rs 0xffffffff
+DIV
+div $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x00000003
+div $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x00000000 LO 0x00000001
+div $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0xffffffff
+div $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0xffffffff
+div $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000002 LO 0x00000000
+DIVU
+divu $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x00000003
+divu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x00000000 LO 0x00000001
+divu $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0xffffffff
+divu $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000001 LO 0x00000000
+divu $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000002 LO 0x00000000
+divu $t0, $t1 :: rs 0x00000000 rt 0x00000002 HI 0x00000000 LO 0x00000000
+EXT
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0xffffffff, pos 0x00000002, size 0x00000006
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0xffffffff, pos 0x00000002, size 0x00000006
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0xffffffff, pos 0x0000001f, size 0x00000006
+ext $t0, $t1, 2, 6 :: rt 0x00000000 rs 0x00000000, pos 0x00000020, size 0x00000020
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0x0000ffff, pos 0x0000001f, size 0x00000000
+ext $t0, $t1, 2, 6 :: rt 0x0000003f rs 0x000000ff, pos 0x0000001f, size 0x00000000
+ext $t0, $t1, 2, 6 :: rt 0x00000000 rs 0xf0000000, pos 0x0000001f, size 0x00000000
+ext $t0, $t1, 2, 6 :: rt 0x00000000 rs 0xf0000000, pos 0x00000000, size 0x0000001f
+ext $t0, $t1, 2, 6 :: rt 0x00000009 rs 0x31415927, pos 0x00000003, size 0x00000019
+INS
+ins $t0, $t1, 2, 6 :: rt 0x000000fc rs 0xffffffff, pos 0x00000002, size 0x00000006
+ins $t0, $t1, 2, 6 :: rt 0xffffffff rs 0xffffffff, pos 0x00000002, size 0x00000006
+ins $t0, $t1, 2, 6 :: rt 0x000000fc rs 0xffffffff, pos 0x0000001f, size 0x00000006
+ins $t0, $t1, 2, 6 :: rt 0x00000000 rs 0x00000000, pos 0x00000020, size 0x00000020
+ins $t0, $t1, 2, 6 :: rt 0x000000fc rs 0x0000ffff, pos 0x0000001f, size 0x00000000
+ins $t0, $t1, 2, 6 :: rt 0x000000fc rs 0x000000ff, pos 0x0000001f, size 0x00000000
+ins $t0, $t1, 2, 6 :: rt 0x00000000 rs 0xf0000000, pos 0x0000001f, size 0x00000000
+ins $t0, $t1, 2, 6 :: rt 0x00000000 rs 0xf0000000, pos 0x00000000, size 0x0000001f
+ins $t0, $t1, 2, 6 :: rt 0x0000009c rs 0x31415927, pos 0x00000003, size 0x00000019
+LB
+lb $t0, 0($t1) :: rt 0x00000012
+lb $t0, 4($t1) :: rt 0x00000000
+lb $t0, 8($t1) :: rt 0x00000000
+lb $t0, 12($t1) :: rt 0xffffffff
+lb $t0, 16($t1) :: rt 0x00000023
+lb $t0, 20($t1) :: rt 0x00000024
+lb $t0, 24($t1) :: rt 0x00000025
+lb $t0, 28($t1) :: rt 0x00000026
+lb $t0, 32($t1) :: rt 0x0000003f
+lb $t0, 36($t1) :: rt 0x0000003e
+lb $t0, 40($t1) :: rt 0x00000036
+lb $t0, 44($t1) :: rt 0x0000003b
+lb $t0, 48($t1) :: rt 0x00000045
+lb $t0, 52($t1) :: rt 0x0000004e
+lb $t0, 56($t1) :: rt 0x00000047
+lb $t0, 60($t1) :: rt 0x0000004a
+lb $t0, 64($t1) :: rt 0x00000041
+lb $t0, 2($t1) :: rt 0x0000001e
+lb $t0, 6($t1) :: rt 0x00000000
+lb $t0, 10($t1) :: rt 0x00000000
+lb $t0, 14($t1) :: rt 0xffffffff
+lb $t0, 18($t1) :: rt 0x0000002e
+lb $t0, 22($t1) :: rt 0x0000002b
+lb $t0, 26($t1) :: rt 0x0000002e
+lb $t0, 30($t1) :: rt 0x0000002d
+lb $t0, 34($t1) :: rt 0x0000003f
+lb $t0, 38($t1) :: rt 0x0000003d
+LBU
+lbu $t0, 0($t1) :: rt 0x00000012
+lbu $t0, 4($t1) :: rt 0x00000000
+lbu $t0, 8($t1) :: rt 0x00000000
+lbu $t0, 12($t1) :: rt 0x000000ff
+lbu $t0, 16($t1) :: rt 0x00000023
+lbu $t0, 20($t1) :: rt 0x00000024
+lbu $t0, 24($t1) :: rt 0x00000025
+lbu $t0, 28($t1) :: rt 0x00000026
+lbu $t0, 32($t1) :: rt 0x0000003f
+lbu $t0, 36($t1) :: rt 0x0000003e
+lbu $t0, 40($t1) :: rt 0x00000036
+lbu $t0, 44($t1) :: rt 0x0000003b
+lbu $t0, 48($t1) :: rt 0x00000045
+lbu $t0, 52($t1) :: rt 0x0000004e
+lbu $t0, 56($t1) :: rt 0x00000047
+lbu $t0, 60($t1) :: rt 0x0000004a
+lbu $t0, 64($t1) :: rt 0x00000041
+lbu $t0, 2($t1) :: rt 0x0000001e
+lbu $t0, 6($t1) :: rt 0x00000000
+lbu $t0, 10($t1) :: rt 0x00000000
+lbu $t0, 14($t1) :: rt 0x000000ff
+lbu $t0, 18($t1) :: rt 0x0000002e
+lbu $t0, 22($t1) :: rt 0x0000002b
+lbu $t0, 26($t1) :: rt 0x0000002e
+lbu $t0, 30($t1) :: rt 0x0000002d
+lbu $t0, 34($t1) :: rt 0x0000003f
+lbu $t0, 38($t1) :: rt 0x0000003d
+LH
+lh $t0, 0($t1) :: rt 0x0000121f
+lh $t0, 4($t1) :: rt 0x00000000
+lh $t0, 8($t1) :: rt 0x00000000
+lh $t0, 12($t1) :: rt 0xffffffff
+lh $t0, 16($t1) :: rt 0x0000232f
+lh $t0, 20($t1) :: rt 0x0000242c
+lh $t0, 24($t1) :: rt 0x0000252a
+lh $t0, 28($t1) :: rt 0x0000262d
+lh $t0, 32($t1) :: rt 0x00003f34
+lh $t0, 36($t1) :: rt 0x00003e35
+lh $t0, 40($t1) :: rt 0x0000363a
+lh $t0, 44($t1) :: rt 0x00003b37
+lh $t0, 48($t1) :: rt 0x0000454f
+lh $t0, 52($t1) :: rt 0x00004e46
+lh $t0, 56($t1) :: rt 0x0000474d
+lh $t0, 60($t1) :: rt 0x00004a48
+lh $t0, 64($t1) :: rt 0x00004144
+lh $t0, 2($t1) :: rt 0x00001e1f
+lh $t0, 6($t1) :: rt 0x00000000
+lh $t0, 10($t1) :: rt 0x00000003
+lh $t0, 14($t1) :: rt 0xffffffff
+lh $t0, 18($t1) :: rt 0x00002e2f
+lh $t0, 22($t1) :: rt 0x00002b2b
+lh $t0, 26($t1) :: rt 0x00002e2b
+lh $t0, 30($t1) :: rt 0x00002d2a
+lh $t0, 34($t1) :: rt 0x00003f3e
+lh $t0, 38($t1) :: rt 0x00003d3c
+LHU
+lhu $t0, 0($t1) :: rt 0x0000121f
+lhu $t0, 4($t1) :: rt 0x00000000
+lhu $t0, 8($t1) :: rt 0x00000000
+lhu $t0, 12($t1) :: rt 0x0000ffff
+lhu $t0, 16($t1) :: rt 0x0000232f
+lhu $t0, 20($t1) :: rt 0x0000242c
+lhu $t0, 24($t1) :: rt 0x0000252a
+lhu $t0, 28($t1) :: rt 0x0000262d
+lhu $t0, 32($t1) :: rt 0x00003f34
+lhu $t0, 36($t1) :: rt 0x00003e35
+lhu $t0, 40($t1) :: rt 0x0000363a
+lhu $t0, 44($t1) :: rt 0x00003b37
+lhu $t0, 48($t1) :: rt 0x0000454f
+lhu $t0, 52($t1) :: rt 0x00004e46
+lhu $t0, 56($t1) :: rt 0x0000474d
+lhu $t0, 60($t1) :: rt 0x00004a48
+lhu $t0, 64($t1) :: rt 0x00004144
+lhu $t0, 2($t1) :: rt 0x00001e1f
+lhu $t0, 6($t1) :: rt 0x00000000
+lhu $t0, 10($t1) :: rt 0x00000003
+lhu $t0, 14($t1) :: rt 0x0000ffff
+lhu $t0, 18($t1) :: rt 0x00002e2f
+lhu $t0, 22($t1) :: rt 0x00002b2b
+lhu $t0, 26($t1) :: rt 0x00002e2b
+lhu $t0, 30($t1) :: rt 0x00002d2a
+lhu $t0, 34($t1) :: rt 0x00003f3e
+lhu $t0, 38($t1) :: rt 0x00003d3c
+LUI
+lui $t0, 0xffff :: rd 0xffff0000 rs 0x0000ffff
+lui $t0, 0xff00 :: rd 0xff000000 rs 0x0000ff00
+lui $t0, 0xff :: rd 0x00ff0000 rs 0x000000ff
+lui $t0, 0x0 :: rd 0x00000000 rs 0x00000000
+lui $t0, 0x5 :: rd 0x00050000 rs 0x00000005
+lui $t0, 0x387 :: rd 0x03870000 rs 0x00000387
+LW
+lw $t0, 0($t1) :: rt 0x121f1e1f
+lw $t0, 4($t1) :: rt 0x00000000
+lw $t0, 8($t1) :: rt 0x00000003
+lw $t0, 12($t1) :: rt 0xffffffff
+lw $t0, 16($t1) :: rt 0x232f2e2f
+lw $t0, 20($t1) :: rt 0x242c2b2b
+lw $t0, 24($t1) :: rt 0x252a2e2b
+lw $t0, 28($t1) :: rt 0x262d2d2a
+lw $t0, 32($t1) :: rt 0x3f343f3e
+lw $t0, 36($t1) :: rt 0x3e353d3c
+lw $t0, 40($t1) :: rt 0x363a3c3b
+lw $t0, 44($t1) :: rt 0x3b373b3a
+lw $t0, 48($t1) :: rt 0x454f4e45
+lw $t0, 52($t1) :: rt 0x4e464d46
+lw $t0, 56($t1) :: rt 0x474d474c
+lw $t0, 60($t1) :: rt 0x4a484a4c
+lw $t0, 64($t1) :: rt 0x41444400
+lw $t0, 2($t1) :: rt 0x1e1f0000
+lw $t0, 6($t1) :: rt 0x00000000
+lw $t0, 10($t1) :: rt 0x0003ffff
+lw $t0, 14($t1) :: rt 0xffff232f
+lw $t0, 18($t1) :: rt 0x2e2f242c
+lw $t0, 22($t1) :: rt 0x2b2b252a
+lw $t0, 26($t1) :: rt 0x2e2b262d
+lw $t0, 30($t1) :: rt 0x2d2a3f34
+lw $t0, 34($t1) :: rt 0x3f3e3e35
+lw $t0, 38($t1) :: rt 0x3d3c363a
+LWL
+lwl $t0, 0($t1) :: rt 0x121f1e1f
+lwl $t0, 4($t1) :: rt 0x00000000
+lwl $t0, 8($t1) :: rt 0x00000003
+lwl $t0, 12($t1) :: rt 0xffffffff
+lwl $t0, 16($t1) :: rt 0x232f2e2f
+lwl $t0, 20($t1) :: rt 0x242c2b2b
+lwl $t0, 24($t1) :: rt 0x252a2e2b
+lwl $t0, 28($t1) :: rt 0x262d2d2a
+lwl $t0, 32($t1) :: rt 0x3f343f3e
+lwl $t0, 36($t1) :: rt 0x3e353d3c
+lwl $t0, 40($t1) :: rt 0x363a3c3b
+lwl $t0, 44($t1) :: rt 0x3b373b3a
+lwl $t0, 48($t1) :: rt 0x454f4e45
+lwl $t0, 52($t1) :: rt 0x4e464d46
+lwl $t0, 56($t1) :: rt 0x474d474c
+lwl $t0, 60($t1) :: rt 0x4a484a4c
+lwl $t0, 64($t1) :: rt 0x41444400
+lwl $t0, 2($t1) :: rt 0x1e1f0000
+lwl $t0, 6($t1) :: rt 0x00000000
+lwl $t0, 10($t1) :: rt 0x00030000
+lwl $t0, 14($t1) :: rt 0xffff0000
+lwl $t0, 18($t1) :: rt 0x2e2f0000
+lwl $t0, 22($t1) :: rt 0x2b2b0000
+lwl $t0, 26($t1) :: rt 0x2e2b0000
+lwl $t0, 30($t1) :: rt 0x2d2a0000
+lwl $t0, 34($t1) :: rt 0x3f3e0000
+lwl $t0, 38($t1) :: rt 0x3d3c0000
+LWR
+lwr $t0, 0($t1) :: rt 0x00000012
+lwr $t0, 4($t1) :: rt 0x00000000
+lwr $t0, 8($t1) :: rt 0x00000000
+lwr $t0, 12($t1) :: rt 0x000000ff
+lwr $t0, 16($t1) :: rt 0x00000023
+lwr $t0, 20($t1) :: rt 0x00000024
+lwr $t0, 24($t1) :: rt 0x00000025
+lwr $t0, 28($t1) :: rt 0x00000026
+lwr $t0, 32($t1) :: rt 0x0000003f
+lwr $t0, 36($t1) :: rt 0x0000003e
+lwr $t0, 40($t1) :: rt 0x00000036
+lwr $t0, 44($t1) :: rt 0x0000003b
+lwr $t0, 48($t1) :: rt 0x00000045
+lwr $t0, 52($t1) :: rt 0x0000004e
+lwr $t0, 56($t1) :: rt 0x00000047
+lwr $t0, 60($t1) :: rt 0x0000004a
+lwr $t0, 64($t1) :: rt 0x00000041
+lwr $t0, 2($t1) :: rt 0x00121f1e
+lwr $t0, 6($t1) :: rt 0x00000000
+lwr $t0, 10($t1) :: rt 0x00000000
+lwr $t0, 14($t1) :: rt 0x00ffffff
+lwr $t0, 18($t1) :: rt 0x00232f2e
+lwr $t0, 22($t1) :: rt 0x00242c2b
+lwr $t0, 26($t1) :: rt 0x00252a2e
+lwr $t0, 30($t1) :: rt 0x00262d2d
+lwr $t0, 34($t1) :: rt 0x003f343f
+lwr $t0, 38($t1) :: rt 0x003e353d
+MADD
+madd $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
+madd $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
+madd $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0x00000000 LO 0x00017fe8
+madd $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+madd $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0xffffffff LO 0xffffffff
+madd $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0xffffffff LO 0xffffffff
+madd $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000000 LO 0x0000000c
+madd $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0x00000000 LO 0x0011c98e
+MADDU
+maddu $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
+maddu $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
+maddu $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0x00000000 LO 0x00017fe8
+maddu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+maddu $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0xffffffff
+maddu $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0xffffffff
+maddu $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000000 LO 0x0000000c
+maddu $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0x00000000 LO 0x0011c98e
+MOVN
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+MOVZ
+movz $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+movz $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xee00ee00
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+MSUB
+msub $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0xffffffff LO 0xfffffff4
+msub $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0xffffffff LO 0xfffff2b8
+msub $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0xffffffff LO 0xfffe8018
+msub $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0xc0000000 LO 0xffffffff
+msub $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0x00000001
+msub $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0x00000001
+msub $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0xffffffff LO 0xfffffff4
+msub $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0xffffffff LO 0xffee3672
+MSUBU
+msubu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xcebea6d9 LO 0x31415927
+msubu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xd2351152 LO 0xfd1dbe00
+msubu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x80000000 LO 0x80000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0xc0000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0xc0000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x80800000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0xf9180000 LO 0x0dd00000
+msubu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xcebea6d9 LO 0x31415927
+msubu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xd2351152 LO 0xfd1dbe00
+msubu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000001 rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x80000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0xc0000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x80800000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0xf9180000 LO 0x0dd00000
+msubu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0xffffffff rt 0xffffffff HI 0x00000001 LO 0xffffffff
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0xc0000000 LO 0xffffffff
+msubu $t0, $t1 :: rs 0x0000ffff rt 0x0000ffff HI 0xffffffff LO 0x0001ffff
+MUL
+mul $t0, $t1, $t2 :: rd 0xcebea6d9 rs 0x31415927, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x02e24200 rs 0x31415927, rt 0xee00ee00
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xff000000
+mul $t0, $t1, $t2 :: rd 0xf2300000 rs 0x7fffffff, rt 0x0dd00000
+mul $t0, $t1, $t2 :: rd 0xcebea6d9 rs 0x31415927, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x02e24200 rs 0x31415927, rt 0xee00ee00
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xff000000
+mul $t0, $t1, $t2 :: rd 0xf2300000 rs 0x7fffffff, rt 0x0dd00000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000001 rs 0x7fffffff, rt 0x7fffffff
+mul $t0, $t1, $t2 :: rd 0xfffe0001 rs 0x0000ffff, rt 0x0000ffff
+MULT
+mult $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xffffffff LO 0xcebea6d9
+mult $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xfc899586 LO 0x02e24200
+mult $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x00000000 LO 0x80000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+mult $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x00800000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+mult $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xffffffff LO 0xcebea6d9
+mult $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xfc899586 LO 0x02e24200
+mult $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000001 rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x80000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+mult $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x00800000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+mult $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0xffffffff rt 0xffffffff HI 0x00000000 LO 0x00000001
+mult $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+mult $t0, $t1 :: rs 0x0000ffff rt 0x0000ffff HI 0x00000000 LO 0xfffe0001
+MULTU
+multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
+multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
+multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x7fffffff LO 0x80000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0x3fffffff LO 0x80000000
+multu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x7f800000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
+multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
+multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000001 rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x80000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0x3fffffff LO 0x80000000
+multu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x7f800000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0xffffffff rt 0xffffffff HI 0xfffffffe LO 0x00000001
+multu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+multu $t0, $t1 :: rs 0x0000ffff rt 0x0000ffff HI 0x00000000 LO 0xfffe0001
+NOR
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x00be00d8 rs 0x31415927, rt 0xee00ee00
+nor $t0, $t1, $t2 :: rd 0xffffff00 rs 0x00000000, rt 0x000000ff
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0xfffffffe rs 0x00000000, rt 0x00000001
+nor $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00ffffff rs 0x80000000, rt 0xff000000
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x0dd00000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x00be00d8 rs 0x31415927, rt 0xee00ee00
+nor $t0, $t1, $t2 :: rd 0xffffff00 rs 0x00000000, rt 0x000000ff
+nor $t0, $t1, $t2 :: rd 0xfffffffe rs 0x00000001, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0xfffffffe rs 0x00000000, rt 0x00000001
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x00000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00ffffff rs 0x80000000, rt 0xff000000
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x0dd00000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x7fffffff
+nor $t0, $t1, $t2 :: rd 0xffff0000 rs 0x0000ffff, rt 0x0000ffff
+WSBH
+wsbh $t0, $t1 :: rd 0x00000200 rs 0x00000002
+wsbh $t0, $t1 :: rd 0x00002800 rs 0x00000028
+wsbh $t0, $t1 :: rd 0xfffffefe rs 0xfffffefe
+wsbh $t0, $t1 :: rd 0xff7fffff rs 0x7fffffff
+wsbh $t0, $t1 :: rd 0xfffff5ff rs 0xfffffff5
+wsbh $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+wsbh $t0, $t1 :: rd 0x00001600 rs 0x00000016
+wsbh $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+NOT
+not $t0, $t1 :: rd 0xfffffffd rs 0x00000002
+not $t0, $t1 :: rd 0xffffffd7 rs 0x00000028
+not $t0, $t1 :: rd 0x00000101 rs 0xfffffefe
+not $t0, $t1 :: rd 0x80000000 rs 0x7fffffff
+not $t0, $t1 :: rd 0x0000000a rs 0xfffffff5
+not $t0, $t1 :: rd 0x00000000 rs 0xffffffff
+not $t0, $t1 :: rd 0xffffffe9 rs 0x00000016
+not $t0, $t1 :: rd 0x00000000 rs 0xffffffff
+NEGU
+negu $t0, $t1 :: rd 0xfffffffe rs 0x00000002
+negu $t0, $t1 :: rd 0xffffffd8 rs 0x00000028
+negu $t0, $t1 :: rd 0x00000102 rs 0xfffffefe
+negu $t0, $t1 :: rd 0x80000001 rs 0x7fffffff
+negu $t0, $t1 :: rd 0x0000000b rs 0xfffffff5
+negu $t0, $t1 :: rd 0x00000001 rs 0xffffffff
+negu $t0, $t1 :: rd 0xffffffea rs 0x00000016
+negu $t0, $t1 :: rd 0x00000001 rs 0xffffffff
+OR
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x31415927, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0xff41ff27 rs 0x31415927, rt 0xee00ee00
+or $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+or $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xff000000 rs 0x80000000, rt 0xff000000
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x31415927, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0xff41ff27 rs 0x31415927, rt 0xee00ee00
+or $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+or $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xff000000 rs 0x80000000, rt 0xff000000
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x7fffffff
+or $t0, $t1, $t2 :: rd 0x0000ffff rs 0x0000ffff, rt 0x0000ffff
+ORI
+ori $t0, $t1, 0xffff :: rt 0x3141ffff rs 0x31415927, imm 0x0000ffff
+ori $t0, $t1, 0xee00 :: rt 0x3141ff27 rs 0x31415927, imm 0x0000ee00
+ori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+ori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+ori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+ori $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+ori $t0, $t1, 0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+ori $t0, $t1, 0x8000 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00008000
+ori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+ori $t0, $t1, 0x0dd0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000dd0
+ori $t0, $t1, 0xffff :: rt 0x3141ffff rs 0x31415927, imm 0x0000ffff
+ori $t0, $t1, 0xee00 :: rt 0x3141ff27 rs 0x31415927, imm 0x0000ee00
+ori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+ori $t0, $t1, 0 :: rt 0x00000001 rs 0x00000001, imm 0x00000000
+ori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+ori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x00008000 rs 0x00000000, imm 0x00008000
+ori $t0, $t1, 0 :: rt 0x00008000 rs 0x00008000, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+ori $t0, $t1, 0x8000 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00008000
+ori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+ori $t0, $t1, 0x0dd0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000dd0
+ori $t0, $t1, 0 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+ori $t0, $t1, 0xffff :: rt 0x0000ffff rs 0x00000000, imm 0x0000ffff
+ori $t0, $t1, 0xffff :: rt 0xffffffff rs 0xffffffff, imm 0x0000ffff
+ori $t0, $t1, 0x7fff :: rt 0x7fffffff rs 0x7fffffff, imm 0x00007fff
+ori $t0, $t1, 0x0000 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+ROTR
+rotr $t0, $t1, 0x00000000 :: rt 0x31415927 rs 0x31415927, imm 0x00000000
+rotr $t0, $t1, 0x00000001 :: rt 0x98a0ac93 rs 0x31415927, imm 0x00000001
+rotr $t0, $t1, 0x00000002 :: rt 0xcc505649 rs 0x31415927, imm 0x00000002
+rotr $t0, $t1, 0x0000000F :: rt 0xb24e6282 rs 0x31415927, imm 0x0000000f
+rotr $t0, $t1, 0x00000010 :: rt 0x59273141 rs 0x31415927, imm 0x00000010
+rotr $t0, $t1, 0x0000001F :: rt 0x6282b24e rs 0x31415927, imm 0x0000001f
+rotr $t0, $t1, 0x00000020 :: rt 0x31415927 rs 0x31415927, imm 0x00000020
+rotr $t0, $t1, 0x00000021 :: rt 0x98a0ac93 rs 0x31415927, imm 0x00000021
+rotr $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x00000000
+rotr $t0, $t1, 0x00000001 :: rt 0x00044000 rs 0x00088000, imm 0x00000001
+rotr $t0, $t1, 31 :: rt 0x00110000 rs 0x00088000, imm 0x0000001f
+rotr $t0, $t1, 16 :: rt 0x00000001 rs 0x00010000, imm 0x00000010
+rotr $t0, $t1, 17 :: rt 0x80000000 rs 0x00010000, imm 0x00000011
+rotr $t0, $t1, 18 :: rt 0x40000000 rs 0x00010000, imm 0x00000012
+rotr $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+rotr $t0, $t1, 0xffff :: rt 0x0001fffe rs 0x0000ffff, imm 0x0000ffff
+ROTRV
+rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+rotrv $t0, $t1, $t2 :: rd 0xfffffffe rs 0x7fffffff, rt 0x7fffffff
+rotrv $t0, $t1, $t2 :: rd 0x0001fffe rs 0x0000ffff, rt 0x0000ffff
+rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x98a0ac93 rs 0x31415927, rt 0x00000001
+rotrv $t0, $t1, $t2 :: rd 0xcc505649 rs 0x31415927, rt 0x00000002
+rotrv $t0, $t1, $t2 :: rd 0xb24e6282 rs 0x31415927, rt 0x0000000f
+rotrv $t0, $t1, $t2 :: rd 0x59273141 rs 0x31415927, rt 0x00000010
+rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0x0000001f
+rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+rotrv $t0, $t1, $t2 :: rd 0x98a0ac93 rs 0x31415927, rt 0x00000021
+rotrv $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x00044000 rs 0x00088000, rt 0x00000001
+rotrv $t0, $t1, $t2 :: rd 0x00110000 rs 0x00088000, rt 0x0000001f
+rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00010000, rt 0x00000010
+rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x00010000, rt 0x00000011
+rotrv $t0, $t1, $t2 :: rd 0x40000000 rs 0x00010000, rt 0x00000012
+rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+rotrv $t0, $t1, $t2 :: rd 0x0001fffe rs 0x0000ffff, rt 0x0000ffff
+SEB
+seb $t0, $t1 :: rd 0x00000002 rs 0x00000002
+seb $t0, $t1 :: rd 0x00000028 rs 0x00000028
+seb $t0, $t1 :: rd 0xfffffffe rs 0xfffffefe
+seb $t0, $t1 :: rd 0xffffffff rs 0x7fffffff
+seb $t0, $t1 :: rd 0xfffffff5 rs 0xfffffff5
+seb $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+seb $t0, $t1 :: rd 0x00000016 rs 0x00000016
+seb $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+SEH
+seh $t0, $t1 :: rd 0x00000002 rs 0x00000002
+seh $t0, $t1 :: rd 0x00000028 rs 0x00000028
+seh $t0, $t1 :: rd 0xfffffefe rs 0xfffffefe
+seh $t0, $t1 :: rd 0xffffffff rs 0x7fffffff
+seh $t0, $t1 :: rd 0xfffffff5 rs 0xfffffff5
+seh $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+seh $t0, $t1 :: rd 0x00000016 rs 0x00000016
+seh $t0, $t1 :: rd 0xffffffff rs 0xffffffff
+SLL
+sll $t0, $t1, 0x00000000 :: rt 0x31415927 rs 0x31415927, imm 0x00000000
+sll $t0, $t1, 0x00000001 :: rt 0x6282b24e rs 0x31415927, imm 0x00000001
+sll $t0, $t1, 0x00000002 :: rt 0xc505649c rs 0x31415927, imm 0x00000002
+sll $t0, $t1, 0x0000000F :: rt 0xac938000 rs 0x31415927, imm 0x0000000f
+sll $t0, $t1, 0x00000010 :: rt 0x59270000 rs 0x31415927, imm 0x00000010
+sll $t0, $t1, 0x0000001F :: rt 0x80000000 rs 0x31415927, imm 0x0000001f
+sll $t0, $t1, 0x00000009 :: rt 0x82b24e00 rs 0x31415927, imm 0x00000009
+sll $t0, $t1, 0x0000000A :: rt 0x05649c00 rs 0x31415927, imm 0x0000000a
+sll $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x00000000
+sll $t0, $t1, 0x00000001 :: rt 0x00110000 rs 0x00088000, imm 0x00000001
+sll $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+sll $t0, $t1, 16 :: rt 0x00000000 rs 0x00010000, imm 0x00000010
+sll $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+sll $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+sll $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SLLV
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+sllv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0xffffffff, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x7fffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x0000ffff, rt 0x0000ffff
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0xc505649c rs 0x31415927, rt 0x00000002
+sllv $t0, $t1, $t2 :: rd 0xac938000 rs 0x31415927, rt 0x0000000f
+sllv $t0, $t1, $t2 :: rd 0x59270000 rs 0x31415927, rt 0x00000010
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0x0000001f
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+sllv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0x00000021
+sllv $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00110000 rs 0x00088000, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000010
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x0000ffff, rt 0x0000ffff
+SLT
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xee00ee00
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xee00ee00
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000002
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000000f
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000010
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000020
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000021
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000010
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SLTI
+slti $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00000001, imm 0x31415927
+slti $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x31415927, imm 0x00000001
+slti $t0, $t1, 0x00000002 :: rt 0x00000000 rs 0x31415927, imm 0x00000002
+slti $t0, $t1, 0x0000000F :: rt 0x00000000 rs 0x31415927, imm 0x0000000f
+slti $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+slti $t0, $t1, 0x0000001F :: rt 0x00000001 rs 0x00000010, imm 0x31415927
+slti $t0, $t1, 0x00000009 :: rt 0x00000000 rs 0x31415927, imm 0x00000009
+slti $t0, $t1, 0x0000000A :: rt 0x00000000 rs 0x31415927, imm 0x0000000a
+slti $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00088000, imm 0x0000000a
+slti $t0, $t1, 0x00000001 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+slti $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+slti $t0, $t1, 16 :: rt 0x00000000 rs 0x00010000, imm 0x00000010
+slti $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+slti $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+slti $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SLTIU
+sltiu $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00000001, imm 0x31415927
+sltiu $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x31415927, imm 0x00000001
+sltiu $t0, $t1, 0x00000002 :: rt 0x00000000 rs 0x31415927, imm 0x00000002
+sltiu $t0, $t1, 0x0000000F :: rt 0x00000000 rs 0x31415927, imm 0x0000000f
+sltiu $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+sltiu $t0, $t1, 0x0000001F :: rt 0x00000001 rs 0x00000010, imm 0x31415927
+sltiu $t0, $t1, 0x00000009 :: rt 0x00000000 rs 0x31415927, imm 0x00000009
+sltiu $t0, $t1, 0x0000000A :: rt 0x00000000 rs 0x31415927, imm 0x0000000a
+sltiu $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00088000, imm 0x0000000a
+sltiu $t0, $t1, 0x00000001 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+sltiu $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+sltiu $t0, $t1, 16 :: rt 0x00000000 rs 0x00010000, imm 0x00000010
+sltiu $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+sltiu $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+sltiu $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SLTU
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x7fffffff, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x7fffffff, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000002
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000000f
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000010
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000020
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000021
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000010
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SRA
+sra $t0, $t1, 0x00000000 :: rt 0x00000001 rs 0x00000001, imm 0x31415927
+sra $t0, $t1, 0x00000001 :: rt 0x18a0ac93 rs 0x31415927, imm 0x00000001
+sra $t0, $t1, 0x00000002 :: rt 0x0c505649 rs 0x31415927, imm 0x00000002
+sra $t0, $t1, 0x0000000F :: rt 0x00006282 rs 0x31415927, imm 0x0000000f
+sra $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+sra $t0, $t1, 0x0000001F :: rt 0x00000000 rs 0x00000010, imm 0x31415927
+sra $t0, $t1, 0x00000009 :: rt 0x0018a0ac rs 0x31415927, imm 0x00000009
+sra $t0, $t1, 0x0000000A :: rt 0x000c5056 rs 0x31415927, imm 0x0000000a
+sra $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x0000000a
+sra $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
+sra $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+sra $t0, $t1, 16 :: rt 0x00000001 rs 0x00010000, imm 0x00000010
+sra $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+sra $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+sra $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SRAV
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srav $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0x0c505649 rs 0x31415927, rt 0x00000002
+srav $t0, $t1, $t2 :: rd 0x00006282 rs 0x31415927, rt 0x0000000f
+srav $t0, $t1, $t2 :: rd 0x00003141 rs 0x31415927, rt 0x00000010
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+srav $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000021
+srav $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00044000 rs 0x00088000, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+srav $t0, $t1, $t2 :: rd 0x00000001 rs 0x00010000, rt 0x00000010
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SRL
+srl $t0, $t1, 0x00000000 :: rt 0x00000001 rs 0x00000001, imm 0x31415927
+srl $t0, $t1, 0x00000001 :: rt 0x18a0ac93 rs 0x31415927, imm 0x00000001
+srl $t0, $t1, 0x00000002 :: rt 0x0c505649 rs 0x31415927, imm 0x00000002
+srl $t0, $t1, 0x0000000F :: rt 0x00006282 rs 0x31415927, imm 0x0000000f
+srl $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+srl $t0, $t1, 0x0000001F :: rt 0x00000000 rs 0x00000010, imm 0x31415927
+srl $t0, $t1, 0x00000009 :: rt 0x0018a0ac rs 0x31415927, imm 0x00000009
+srl $t0, $t1, 0x0000000A :: rt 0x000c5056 rs 0x31415927, imm 0x0000000a
+srl $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x0000000a
+srl $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
+srl $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+srl $t0, $t1, 16 :: rt 0x00000001 rs 0x00010000, imm 0x00000010
+srl $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+srl $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+srl $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SRLV
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0x0c505649 rs 0x31415927, rt 0x00000002
+srlv $t0, $t1, $t2 :: rd 0x00006282 rs 0x31415927, rt 0x0000000f
+srlv $t0, $t1, $t2 :: rd 0x00003141 rs 0x31415927, rt 0x00000010
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+srlv $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000021
+srlv $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00044000 rs 0x00088000, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00010000, rt 0x00000010
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SUBU
+subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x31414817 rs 0x31415927, rt 0x00001110
+subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x80000001 rs 0x80000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x81000000 rs 0x80000000, rt 0xff000000
+subu $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+subu $t0, $t1, $t2 :: rd 0x31415928 rs 0x31415927, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x43406b27 rs 0x31415927, rt 0xee00ee00
+subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x81000000 rs 0x80000000, rt 0xff000000
+subu $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+subu $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x31415925 rs 0x31415927, rt 0x00000002
+subu $t0, $t1, $t2 :: rd 0x31415918 rs 0x31415927, rt 0x0000000f
+subu $t0, $t1, $t2 :: rd 0x31415917 rs 0x31415927, rt 0x00000010
+subu $t0, $t1, $t2 :: rd 0x31415908 rs 0x31415927, rt 0x0000001f
+subu $t0, $t1, $t2 :: rd 0x31415907 rs 0x31415927, rt 0x00000020
+subu $t0, $t1, $t2 :: rd 0x31415906 rs 0x31415927, rt 0x00000021
+subu $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00087fff rs 0x00088000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x00087fe1 rs 0x00088000, rt 0x0000001f
+subu $t0, $t1, $t2 :: rd 0x0000fff0 rs 0x00010000, rt 0x00000010
+subu $t0, $t1, $t2 :: rd 0x0000ffef rs 0x00010000, rt 0x00000011
+subu $t0, $t1, $t2 :: rd 0x0000ffee rs 0x00010000, rt 0x00000012
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SUB
+subu $t0, $t1, $t2 :: rd 0x31415928 rs 0x31415927, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x0a2941ff rs 0x31415927, rt 0x27181728
+subu $t0, $t1, $t2 :: rd 0x9a2941ff rs 0x31415927, rt 0x97181728
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0x7fffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+XOR
+xor $t0, $t1, $t2 :: rd 0xcebea6d8 rs 0x31415927, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0xdf41b727 rs 0x31415927, rt 0xee00ee00
+xor $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x7f000000 rs 0x80000000, rt 0xff000000
+xor $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+xor $t0, $t1, $t2 :: rd 0xcebea6d8 rs 0x31415927, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0xdf41b727 rs 0x31415927, rt 0xee00ee00
+xor $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+xor $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x7f000000 rs 0x80000000, rt 0xff000000
+xor $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+XORI
+xori $t0, $t1, 0xffff :: rt 0x3141a6d8 rs 0x31415927, imm 0x0000ffff
+xori $t0, $t1, 0xee00 :: rt 0x3141b727 rs 0x31415927, imm 0x0000ee00
+xori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+xori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+xori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+xori $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+xori $t0, $t1, 0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+xori $t0, $t1, 0x8000 :: rt 0x7fff7fff rs 0x7fffffff, imm 0x00008000
+xori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+xori $t0, $t1, 0x0dd0 :: rt 0x7ffff22f rs 0x7fffffff, imm 0x00000dd0
+xori $t0, $t1, 0xffff :: rt 0x3141a6d8 rs 0x31415927, imm 0x0000ffff
+xori $t0, $t1, 0xee00 :: rt 0x3141b727 rs 0x31415927, imm 0x0000ee00
+xori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+xori $t0, $t1, 0 :: rt 0x00000001 rs 0x00000001, imm 0x00000000
+xori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+xori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x00008000 rs 0x00000000, imm 0x00008000
+xori $t0, $t1, 0 :: rt 0x00008000 rs 0x00008000, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+xori $t0, $t1, 0x8000 :: rt 0x7fff7fff rs 0x7fffffff, imm 0x00008000
+xori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+xori $t0, $t1, 0x0dd0 :: rt 0x7ffff22f rs 0x7fffffff, imm 0x00000dd0
+xori $t0, $t1, 0 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+xori $t0, $t1, 0xffff :: rt 0x0000ffff rs 0x00000000, imm 0x0000ffff
+xori $t0, $t1, 0xffff :: rt 0xffff0000 rs 0xffffffff, imm 0x0000ffff
+xori $t0, $t1, 0x7fff :: rt 0x7fff8000 rs 0x7fffffff, imm 0x00007fff
+xori $t0, $t1, 0x0000 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+MFHI MFLO
+mfhi mflo :: HI: 0x31415927, LO: 0x31415926
+mfhi mflo :: HI: 0x0, LO: 0xffffffff
+mfhi mflo :: HI: 0xffffffff, LO: 0xfffffffe
+mfhi mflo :: HI: 0xffffffff, LO: 0xfffffffe
+mfhi mflo :: HI: 0x8000, LO: 0x7fff
+mfhi mflo :: HI: 0x80000000, LO: 0x7fffffff
+mfhi mflo :: HI: 0xffff, LO: 0xfffe
+mfhi mflo :: HI: 0x7fff, LO: 0x7ffe
+mfhi mflo :: HI: 0xdd0, LO: 0xdcf
+mfhi mflo :: HI: 0xff00, LO: 0xfeff
diff --git a/main/none/tests/mips32/MIPS32int.stdout.exp-mips32 b/main/none/tests/mips32/MIPS32int.stdout.exp-mips32
new file mode 100644
index 0000000..e7172e7
--- /dev/null
+++ b/main/none/tests/mips32/MIPS32int.stdout.exp-mips32
@@ -0,0 +1,1115 @@
+ADD
+add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
+add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
+add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
+add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
+add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+add $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+add $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+ADDI
+addi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+addi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+addi $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000000
+addi $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000001
+addi $t0, $t1, -1 :: rt 0xffffffff rs 0x00000000, imm 0xffffffff
+addi $t0, $t1, -1 :: rt 0x00000000 rs 0x00000001, imm 0xffffffff
+addi $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+addi $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+addi $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+ADDIU
+addiu $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+addiu $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000000
+addiu $t0, $t1, 1 :: rt 0x00000002 rs 0x00000001, imm 0x00000001
+addiu $t0, $t1, -1 :: rt 0xffffffff rs 0x00000000, imm 0xffffffff
+addiu $t0, $t1, -1 :: rt 0x00000000 rs 0x00000001, imm 0xffffffff
+addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+addiu $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+addiu $t0, $t1, 0 :: rt 0x80000000 rs 0x80000000, imm 0x00000000
+ADDU
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
+addu $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
+addu $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+addu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+addu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+addu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+addu $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0x7fffffff
+addu $t0, $t1, $t2 :: rd 0xfffffffe rs 0x7fffffff, rt 0x7fffffff
+AND
+and $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x20004800 rs 0x31415927, rt 0xee00ee00
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+and $t0, $t1, $t2 :: rd 0x0dd00000 rs 0x7fffffff, rt 0x0dd00000
+and $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x20004800 rs 0x31415927, rt 0xee00ee00
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+and $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+and $t0, $t1, $t2 :: rd 0x0dd00000 rs 0x7fffffff, rt 0x0dd00000
+ANDI
+andi $t0, $t1, 1 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
+andi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000001, imm 0x00000000
+andi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000001, imm 0x00000001
+andi $t0, $t1, 1 :: rt 0x00000001 rs 0x7fffffff, imm 0x00000000
+andi $t0, $t1, 0 :: rt 0x00000000 rs 0x80000000, imm 0x00000000
+andi $t0, $t1, 0x3145 :: rt 0x00003145 rs 0xffffffff, imm 0x00003145
+CLO
+clo $t0, $t1 :: rd 0x00000000 rs 0x00000000
+clo $t0, $t1 :: rd 0x00000000 rs 0x00000001
+clo $t0, $t1 :: rd 0x00000000 rs 0x00000010
+clo $t0, $t1 :: rd 0x00000020 rs 0xffffffff
+CLZ
+clz $t0, $t1 :: rd 0x00000020 rs 0x00000000
+clz $t0, $t1 :: rd 0x0000001f rs 0x00000001
+clz $t0, $t1 :: rd 0x0000001b rs 0x00000010
+clz $t0, $t1 :: rd 0x00000000 rs 0xffffffff
+DIV
+div $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x00000003
+div $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x00000000 LO 0x00000001
+div $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0xffffffff
+div $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0xffffffff
+div $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000002 LO 0x00000000
+DIVU
+divu $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x00000003
+divu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x00000000 LO 0x00000001
+divu $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0xffffffff
+divu $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000001 LO 0x00000000
+divu $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000002 LO 0x00000000
+divu $t0, $t1 :: rs 0x00000000 rt 0x00000002 HI 0x00000000 LO 0x00000000
+LB
+lb $t0, 0($t1) :: rt 0x0000001f
+lb $t0, 4($t1) :: rt 0x00000000
+lb $t0, 8($t1) :: rt 0x00000003
+lb $t0, 12($t1) :: rt 0xffffffff
+lb $t0, 16($t1) :: rt 0x0000002f
+lb $t0, 20($t1) :: rt 0x0000002b
+lb $t0, 24($t1) :: rt 0x0000002b
+lb $t0, 28($t1) :: rt 0x0000002a
+lb $t0, 32($t1) :: rt 0x0000003e
+lb $t0, 36($t1) :: rt 0x0000003c
+lb $t0, 40($t1) :: rt 0x0000003b
+lb $t0, 44($t1) :: rt 0x0000003a
+lb $t0, 48($t1) :: rt 0x00000045
+lb $t0, 52($t1) :: rt 0x00000046
+lb $t0, 56($t1) :: rt 0x0000004c
+lb $t0, 60($t1) :: rt 0x0000004c
+lb $t0, 64($t1) :: rt 0x00000041
+lb $t0, 2($t1) :: rt 0x0000001f
+lb $t0, 6($t1) :: rt 0x00000000
+lb $t0, 10($t1) :: rt 0x00000000
+lb $t0, 14($t1) :: rt 0xffffffff
+lb $t0, 18($t1) :: rt 0x0000002f
+lb $t0, 22($t1) :: rt 0x0000002c
+lb $t0, 26($t1) :: rt 0x0000002a
+lb $t0, 30($t1) :: rt 0x0000002d
+lb $t0, 34($t1) :: rt 0x00000034
+lb $t0, 38($t1) :: rt 0x00000035
+LBU
+lbu $t0, 0($t1) :: rt 0x0000001f
+lbu $t0, 4($t1) :: rt 0x00000000
+lbu $t0, 8($t1) :: rt 0x00000003
+lbu $t0, 12($t1) :: rt 0x000000ff
+lbu $t0, 16($t1) :: rt 0x0000002f
+lbu $t0, 20($t1) :: rt 0x0000002b
+lbu $t0, 24($t1) :: rt 0x0000002b
+lbu $t0, 28($t1) :: rt 0x0000002a
+lbu $t0, 32($t1) :: rt 0x0000003e
+lbu $t0, 36($t1) :: rt 0x0000003c
+lbu $t0, 40($t1) :: rt 0x0000003b
+lbu $t0, 44($t1) :: rt 0x0000003a
+lbu $t0, 48($t1) :: rt 0x00000045
+lbu $t0, 52($t1) :: rt 0x00000046
+lbu $t0, 56($t1) :: rt 0x0000004c
+lbu $t0, 60($t1) :: rt 0x0000004c
+lbu $t0, 64($t1) :: rt 0x00000041
+lbu $t0, 2($t1) :: rt 0x0000001f
+lbu $t0, 6($t1) :: rt 0x00000000
+lbu $t0, 10($t1) :: rt 0x00000000
+lbu $t0, 14($t1) :: rt 0x000000ff
+lbu $t0, 18($t1) :: rt 0x0000002f
+lbu $t0, 22($t1) :: rt 0x0000002c
+lbu $t0, 26($t1) :: rt 0x0000002a
+lbu $t0, 30($t1) :: rt 0x0000002d
+lbu $t0, 34($t1) :: rt 0x00000034
+lbu $t0, 38($t1) :: rt 0x00000035
+LH
+lh $t0, 0($t1) :: rt 0x00001e1f
+lh $t0, 4($t1) :: rt 0x00000000
+lh $t0, 8($t1) :: rt 0x00000003
+lh $t0, 12($t1) :: rt 0xffffffff
+lh $t0, 16($t1) :: rt 0x00002e2f
+lh $t0, 20($t1) :: rt 0x00002b2b
+lh $t0, 24($t1) :: rt 0x00002e2b
+lh $t0, 28($t1) :: rt 0x00002d2a
+lh $t0, 32($t1) :: rt 0x00003f3e
+lh $t0, 36($t1) :: rt 0x00003d3c
+lh $t0, 40($t1) :: rt 0x00003c3b
+lh $t0, 44($t1) :: rt 0x00003b3a
+lh $t0, 48($t1) :: rt 0x00004e45
+lh $t0, 52($t1) :: rt 0x00004d46
+lh $t0, 56($t1) :: rt 0x0000474c
+lh $t0, 60($t1) :: rt 0x00004a4c
+lh $t0, 64($t1) :: rt 0x00004441
+lh $t0, 2($t1) :: rt 0x0000121f
+lh $t0, 6($t1) :: rt 0x00000000
+lh $t0, 10($t1) :: rt 0x00000000
+lh $t0, 14($t1) :: rt 0xffffffff
+lh $t0, 18($t1) :: rt 0x0000232f
+lh $t0, 22($t1) :: rt 0x0000242c
+lh $t0, 26($t1) :: rt 0x0000252a
+lh $t0, 30($t1) :: rt 0x0000262d
+lh $t0, 34($t1) :: rt 0x00003f34
+lh $t0, 38($t1) :: rt 0x00003e35
+LHU
+lhu $t0, 0($t1) :: rt 0x00001e1f
+lhu $t0, 4($t1) :: rt 0x00000000
+lhu $t0, 8($t1) :: rt 0x00000003
+lhu $t0, 12($t1) :: rt 0x0000ffff
+lhu $t0, 16($t1) :: rt 0x00002e2f
+lhu $t0, 20($t1) :: rt 0x00002b2b
+lhu $t0, 24($t1) :: rt 0x00002e2b
+lhu $t0, 28($t1) :: rt 0x00002d2a
+lhu $t0, 32($t1) :: rt 0x00003f3e
+lhu $t0, 36($t1) :: rt 0x00003d3c
+lhu $t0, 40($t1) :: rt 0x00003c3b
+lhu $t0, 44($t1) :: rt 0x00003b3a
+lhu $t0, 48($t1) :: rt 0x00004e45
+lhu $t0, 52($t1) :: rt 0x00004d46
+lhu $t0, 56($t1) :: rt 0x0000474c
+lhu $t0, 60($t1) :: rt 0x00004a4c
+lhu $t0, 64($t1) :: rt 0x00004441
+lhu $t0, 2($t1) :: rt 0x0000121f
+lhu $t0, 6($t1) :: rt 0x00000000
+lhu $t0, 10($t1) :: rt 0x00000000
+lhu $t0, 14($t1) :: rt 0x0000ffff
+lhu $t0, 18($t1) :: rt 0x0000232f
+lhu $t0, 22($t1) :: rt 0x0000242c
+lhu $t0, 26($t1) :: rt 0x0000252a
+lhu $t0, 30($t1) :: rt 0x0000262d
+lhu $t0, 34($t1) :: rt 0x00003f34
+lhu $t0, 38($t1) :: rt 0x00003e35
+LUI
+lui $t0, 0xffff :: rd 0xffff0000 rs 0x0000ffff
+lui $t0, 0xff00 :: rd 0xff000000 rs 0x0000ff00
+lui $t0, 0xff :: rd 0x00ff0000 rs 0x000000ff
+lui $t0, 0x0 :: rd 0x00000000 rs 0x00000000
+lui $t0, 0x5 :: rd 0x00050000 rs 0x00000005
+lui $t0, 0x387 :: rd 0x03870000 rs 0x00000387
+LW
+lw $t0, 0($t1) :: rt 0x121f1e1f
+lw $t0, 4($t1) :: rt 0x00000000
+lw $t0, 8($t1) :: rt 0x00000003
+lw $t0, 12($t1) :: rt 0xffffffff
+lw $t0, 16($t1) :: rt 0x232f2e2f
+lw $t0, 20($t1) :: rt 0x242c2b2b
+lw $t0, 24($t1) :: rt 0x252a2e2b
+lw $t0, 28($t1) :: rt 0x262d2d2a
+lw $t0, 32($t1) :: rt 0x3f343f3e
+lw $t0, 36($t1) :: rt 0x3e353d3c
+lw $t0, 40($t1) :: rt 0x363a3c3b
+lw $t0, 44($t1) :: rt 0x3b373b3a
+lw $t0, 48($t1) :: rt 0x454f4e45
+lw $t0, 52($t1) :: rt 0x4e464d46
+lw $t0, 56($t1) :: rt 0x474d474c
+lw $t0, 60($t1) :: rt 0x4a484a4c
+lw $t0, 64($t1) :: rt 0x00444441
+lw $t0, 2($t1) :: rt 0x0000121f
+lw $t0, 6($t1) :: rt 0x00030000
+lw $t0, 10($t1) :: rt 0xffff0000
+lw $t0, 14($t1) :: rt 0x2e2fffff
+lw $t0, 18($t1) :: rt 0x2b2b232f
+lw $t0, 22($t1) :: rt 0x2e2b242c
+lw $t0, 26($t1) :: rt 0x2d2a252a
+lw $t0, 30($t1) :: rt 0x3f3e262d
+lw $t0, 34($t1) :: rt 0x3d3c3f34
+lw $t0, 38($t1) :: rt 0x3c3b3e35
+LWL
+lwl $t0, 0($t1) :: rt 0x1f000000
+lwl $t0, 4($t1) :: rt 0x00000000
+lwl $t0, 8($t1) :: rt 0x03000000
+lwl $t0, 12($t1) :: rt 0xff000000
+lwl $t0, 16($t1) :: rt 0x2f000000
+lwl $t0, 20($t1) :: rt 0x2b000000
+lwl $t0, 24($t1) :: rt 0x2b000000
+lwl $t0, 28($t1) :: rt 0x2a000000
+lwl $t0, 32($t1) :: rt 0x3e000000
+lwl $t0, 36($t1) :: rt 0x3c000000
+lwl $t0, 40($t1) :: rt 0x3b000000
+lwl $t0, 44($t1) :: rt 0x3a000000
+lwl $t0, 48($t1) :: rt 0x45000000
+lwl $t0, 52($t1) :: rt 0x46000000
+lwl $t0, 56($t1) :: rt 0x4c000000
+lwl $t0, 60($t1) :: rt 0x4c000000
+lwl $t0, 64($t1) :: rt 0x41000000
+lwl $t0, 2($t1) :: rt 0x1f1e1f00
+lwl $t0, 6($t1) :: rt 0x00000000
+lwl $t0, 10($t1) :: rt 0x00000300
+lwl $t0, 14($t1) :: rt 0xffffff00
+lwl $t0, 18($t1) :: rt 0x2f2e2f00
+lwl $t0, 22($t1) :: rt 0x2c2b2b00
+lwl $t0, 26($t1) :: rt 0x2a2e2b00
+lwl $t0, 30($t1) :: rt 0x2d2d2a00
+lwl $t0, 34($t1) :: rt 0x343f3e00
+lwl $t0, 38($t1) :: rt 0x353d3c00
+LWR
+lwr $t0, 0($t1) :: rt 0x121f1e1f
+lwr $t0, 4($t1) :: rt 0x00000000
+lwr $t0, 8($t1) :: rt 0x00000003
+lwr $t0, 12($t1) :: rt 0xffffffff
+lwr $t0, 16($t1) :: rt 0x232f2e2f
+lwr $t0, 20($t1) :: rt 0x242c2b2b
+lwr $t0, 24($t1) :: rt 0x252a2e2b
+lwr $t0, 28($t1) :: rt 0x262d2d2a
+lwr $t0, 32($t1) :: rt 0x3f343f3e
+lwr $t0, 36($t1) :: rt 0x3e353d3c
+lwr $t0, 40($t1) :: rt 0x363a3c3b
+lwr $t0, 44($t1) :: rt 0x3b373b3a
+lwr $t0, 48($t1) :: rt 0x454f4e45
+lwr $t0, 52($t1) :: rt 0x4e464d46
+lwr $t0, 56($t1) :: rt 0x474d474c
+lwr $t0, 60($t1) :: rt 0x4a484a4c
+lwr $t0, 64($t1) :: rt 0x00444441
+lwr $t0, 2($t1) :: rt 0x0000121f
+lwr $t0, 6($t1) :: rt 0x00000000
+lwr $t0, 10($t1) :: rt 0x00000000
+lwr $t0, 14($t1) :: rt 0x0000ffff
+lwr $t0, 18($t1) :: rt 0x0000232f
+lwr $t0, 22($t1) :: rt 0x0000242c
+lwr $t0, 26($t1) :: rt 0x0000252a
+lwr $t0, 30($t1) :: rt 0x0000262d
+lwr $t0, 34($t1) :: rt 0x00003f34
+lwr $t0, 38($t1) :: rt 0x00003e35
+MADD
+madd $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
+madd $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
+madd $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0x00000000 LO 0x00017fe8
+madd $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+madd $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0xffffffff LO 0xffffffff
+madd $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0xffffffff LO 0xffffffff
+madd $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000000 LO 0x0000000c
+madd $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0x00000000 LO 0x0011c98e
+MADDU
+maddu $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0x00000000 LO 0x0000000c
+maddu $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0x00000000 LO 0x00000d48
+maddu $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0x00000000 LO 0x00017fe8
+maddu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+maddu $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0xffffffff
+maddu $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0xffffffff
+maddu $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0x00000000 LO 0x0000000c
+maddu $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0x00000000 LO 0x0011c98e
+MOVN
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+movn $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+movn $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000001
+movn $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+MOVZ
+movz $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+movz $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xee00ee00
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+movz $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000001
+movz $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+MSUB
+msub $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0xffffffff LO 0xfffffff4
+msub $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0xffffffff LO 0xfffff2b8
+msub $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0xffffffff LO 0xfffe8018
+msub $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0xc0000000 LO 0xffffffff
+msub $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0x00000001
+msub $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0x00000001
+msub $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0xffffffff LO 0xfffffff4
+msub $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0xffffffff LO 0xffee3672
+MSUBU
+msubu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xcebea6d9 LO 0x31415927
+msubu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xd2351152 LO 0xfd1dbe00
+msubu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x80000000 LO 0x80000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0xc0000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0xc0000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x80800000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0xf9180000 LO 0x0dd00000
+msubu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xcebea6d9 LO 0x31415927
+msubu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xd2351152 LO 0xfd1dbe00
+msubu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000001 rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0x80000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0xc0000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+msubu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x80800000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0xf9180000 LO 0x0dd00000
+msubu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+msubu $t0, $t1 :: rs 0xffffffff rt 0xffffffff HI 0x00000001 LO 0xffffffff
+msubu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0xc0000000 LO 0xffffffff
+msubu $t0, $t1 :: rs 0x0000ffff rt 0x0000ffff HI 0xffffffff LO 0x0001ffff
+MUL
+mul $t0, $t1, $t2 :: rd 0xcebea6d9 rs 0x31415927, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x02e24200 rs 0x31415927, rt 0xee00ee00
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xff000000
+mul $t0, $t1, $t2 :: rd 0xf2300000 rs 0x7fffffff, rt 0x0dd00000
+mul $t0, $t1, $t2 :: rd 0xcebea6d9 rs 0x31415927, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x02e24200 rs 0x31415927, rt 0xee00ee00
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x80000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xff000000
+mul $t0, $t1, $t2 :: rd 0xf2300000 rs 0x7fffffff, rt 0x0dd00000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+mul $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0xffffffff
+mul $t0, $t1, $t2 :: rd 0x00000001 rs 0x7fffffff, rt 0x7fffffff
+mul $t0, $t1, $t2 :: rd 0xfffe0001 rs 0x0000ffff, rt 0x0000ffff
+MULT
+mult $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xffffffff LO 0xcebea6d9
+mult $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xfc899586 LO 0x02e24200
+mult $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x00000000 LO 0x80000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+mult $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x00800000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+mult $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0xffffffff LO 0xcebea6d9
+mult $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0xfc899586 LO 0x02e24200
+mult $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000001 rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0x80000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0xc0000000 LO 0x80000000
+mult $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x00800000 LO 0x00000000
+mult $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+mult $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+mult $t0, $t1 :: rs 0xffffffff rt 0xffffffff HI 0x00000000 LO 0x00000001
+mult $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+mult $t0, $t1 :: rs 0x0000ffff rt 0x0000ffff HI 0x00000000 LO 0xfffe0001
+MULTU
+multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
+multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
+multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0xffffffff HI 0x7fffffff LO 0x80000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0x3fffffff LO 0x80000000
+multu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x7f800000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+multu $t0, $t1 :: rs 0x31415927 rt 0xffffffff HI 0x31415926 LO 0xcebea6d9
+multu $t0, $t1 :: rs 0x31415927 rt 0xee00ee00 HI 0x2dcaeead LO 0x02e24200
+multu $t0, $t1 :: rs 0x00000000 rt 0x000000ff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000001 rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x00000001 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0x80000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x80000000 rt 0x80000000 HI 0x40000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x80000000 HI 0x3fffffff LO 0x80000000
+multu $t0, $t1 :: rs 0x80000000 rt 0xff000000 HI 0x7f800000 LO 0x00000000
+multu $t0, $t1 :: rs 0x7fffffff rt 0x0dd00000 HI 0x06e7ffff LO 0xf2300000
+multu $t0, $t1 :: rs 0xffffffff rt 0x00000000 HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0x00000000 rt 0xffffffff HI 0x00000000 LO 0x00000000
+multu $t0, $t1 :: rs 0xffffffff rt 0xffffffff HI 0xfffffffe LO 0x00000001
+multu $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0x3fffffff LO 0x00000001
+multu $t0, $t1 :: rs 0x0000ffff rt 0x0000ffff HI 0x00000000 LO 0xfffe0001
+NOR
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x00be00d8 rs 0x31415927, rt 0xee00ee00
+nor $t0, $t1, $t2 :: rd 0xffffff00 rs 0x00000000, rt 0x000000ff
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0xfffffffe rs 0x00000000, rt 0x00000001
+nor $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00ffffff rs 0x80000000, rt 0xff000000
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x0dd00000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x00be00d8 rs 0x31415927, rt 0xee00ee00
+nor $t0, $t1, $t2 :: rd 0xffffff00 rs 0x00000000, rt 0x000000ff
+nor $t0, $t1, $t2 :: rd 0xfffffffe rs 0x00000001, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0xfffffffe rs 0x00000000, rt 0x00000001
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x00000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+nor $t0, $t1, $t2 :: rd 0x00ffffff rs 0x80000000, rt 0xff000000
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x0dd00000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+nor $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x7fffffff
+nor $t0, $t1, $t2 :: rd 0xffff0000 rs 0x0000ffff, rt 0x0000ffff
+NOT
+not $t0, $t1 :: rd 0xfffffffd rs 0x00000002
+not $t0, $t1 :: rd 0xffffffd7 rs 0x00000028
+not $t0, $t1 :: rd 0x00000101 rs 0xfffffefe
+not $t0, $t1 :: rd 0x80000000 rs 0x7fffffff
+not $t0, $t1 :: rd 0x0000000a rs 0xfffffff5
+not $t0, $t1 :: rd 0x00000000 rs 0xffffffff
+not $t0, $t1 :: rd 0xffffffe9 rs 0x00000016
+not $t0, $t1 :: rd 0x00000000 rs 0xffffffff
+NEGU
+negu $t0, $t1 :: rd 0xfffffffe rs 0x00000002
+negu $t0, $t1 :: rd 0xffffffd8 rs 0x00000028
+negu $t0, $t1 :: rd 0x00000102 rs 0xfffffefe
+negu $t0, $t1 :: rd 0x80000001 rs 0x7fffffff
+negu $t0, $t1 :: rd 0x0000000b rs 0xfffffff5
+negu $t0, $t1 :: rd 0x00000001 rs 0xffffffff
+negu $t0, $t1 :: rd 0xffffffea rs 0x00000016
+negu $t0, $t1 :: rd 0x00000001 rs 0xffffffff
+OR
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x31415927, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0xff41ff27 rs 0x31415927, rt 0xee00ee00
+or $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+or $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xff000000 rs 0x80000000, rt 0xff000000
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x31415927, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0xff41ff27 rs 0x31415927, rt 0xee00ee00
+or $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+or $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+or $t0, $t1, $t2 :: rd 0xff000000 rs 0x80000000, rt 0xff000000
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+or $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x7fffffff
+or $t0, $t1, $t2 :: rd 0x0000ffff rs 0x0000ffff, rt 0x0000ffff
+ORI
+ori $t0, $t1, 0xffff :: rt 0x3141ffff rs 0x31415927, imm 0x0000ffff
+ori $t0, $t1, 0xee00 :: rt 0x3141ff27 rs 0x31415927, imm 0x0000ee00
+ori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+ori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+ori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+ori $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+ori $t0, $t1, 0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+ori $t0, $t1, 0x8000 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00008000
+ori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+ori $t0, $t1, 0x0dd0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000dd0
+ori $t0, $t1, 0xffff :: rt 0x3141ffff rs 0x31415927, imm 0x0000ffff
+ori $t0, $t1, 0xee00 :: rt 0x3141ff27 rs 0x31415927, imm 0x0000ee00
+ori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+ori $t0, $t1, 0 :: rt 0x00000001 rs 0x00000001, imm 0x00000000
+ori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+ori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x00008000 rs 0x00000000, imm 0x00008000
+ori $t0, $t1, 0 :: rt 0x00008000 rs 0x00008000, imm 0x00000000
+ori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+ori $t0, $t1, 0x8000 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00008000
+ori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+ori $t0, $t1, 0x0dd0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000dd0
+ori $t0, $t1, 0 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+ori $t0, $t1, 0xffff :: rt 0x0000ffff rs 0x00000000, imm 0x0000ffff
+ori $t0, $t1, 0xffff :: rt 0xffffffff rs 0xffffffff, imm 0x0000ffff
+ori $t0, $t1, 0x7fff :: rt 0x7fffffff rs 0x7fffffff, imm 0x00007fff
+ori $t0, $t1, 0x0000 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+SLL
+sll $t0, $t1, 0x00000000 :: rt 0x31415927 rs 0x31415927, imm 0x00000000
+sll $t0, $t1, 0x00000001 :: rt 0x6282b24e rs 0x31415927, imm 0x00000001
+sll $t0, $t1, 0x00000002 :: rt 0xc505649c rs 0x31415927, imm 0x00000002
+sll $t0, $t1, 0x0000000F :: rt 0xac938000 rs 0x31415927, imm 0x0000000f
+sll $t0, $t1, 0x00000010 :: rt 0x59270000 rs 0x31415927, imm 0x00000010
+sll $t0, $t1, 0x0000001F :: rt 0x80000000 rs 0x31415927, imm 0x0000001f
+sll $t0, $t1, 0x00000009 :: rt 0x82b24e00 rs 0x31415927, imm 0x00000009
+sll $t0, $t1, 0x0000000A :: rt 0x05649c00 rs 0x31415927, imm 0x0000000a
+sll $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x00000000
+sll $t0, $t1, 0x00000001 :: rt 0x00110000 rs 0x00088000, imm 0x00000001
+sll $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+sll $t0, $t1, 16 :: rt 0x00000000 rs 0x00010000, imm 0x00000010
+sll $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+sll $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+sll $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SLLV
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+sllv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+sllv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+sllv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0xffffffff, rt 0xffffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x7fffffff, rt 0x7fffffff
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x0000ffff, rt 0x0000ffff
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0xc505649c rs 0x31415927, rt 0x00000002
+sllv $t0, $t1, $t2 :: rd 0xac938000 rs 0x31415927, rt 0x0000000f
+sllv $t0, $t1, $t2 :: rd 0x59270000 rs 0x31415927, rt 0x00000010
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x31415927, rt 0x0000001f
+sllv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+sllv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0x00000021
+sllv $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x00110000 rs 0x00088000, rt 0x00000001
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000010
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+sllv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sllv $t0, $t1, $t2 :: rd 0x80000000 rs 0x0000ffff, rt 0x0000ffff
+SLT
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xee00ee00
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xee00ee00
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x80000000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+slt $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000002
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000000f
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000010
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000020
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000021
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000001
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000010
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+slt $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SLTI
+slti $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00000001, imm 0x31415927
+slti $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x31415927, imm 0x00000001
+slti $t0, $t1, 0x00000002 :: rt 0x00000000 rs 0x31415927, imm 0x00000002
+slti $t0, $t1, 0x0000000F :: rt 0x00000000 rs 0x31415927, imm 0x0000000f
+slti $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+slti $t0, $t1, 0x0000001F :: rt 0x00000001 rs 0x00000010, imm 0x31415927
+slti $t0, $t1, 0x00000009 :: rt 0x00000000 rs 0x31415927, imm 0x00000009
+slti $t0, $t1, 0x0000000A :: rt 0x00000000 rs 0x31415927, imm 0x0000000a
+slti $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00088000, imm 0x0000000a
+slti $t0, $t1, 0x00000001 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+slti $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+slti $t0, $t1, 16 :: rt 0x00000000 rs 0x00010000, imm 0x00000010
+slti $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+slti $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+slti $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SLTIU
+sltiu $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00000001, imm 0x31415927
+sltiu $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x31415927, imm 0x00000001
+sltiu $t0, $t1, 0x00000002 :: rt 0x00000000 rs 0x31415927, imm 0x00000002
+sltiu $t0, $t1, 0x0000000F :: rt 0x00000000 rs 0x31415927, imm 0x0000000f
+sltiu $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+sltiu $t0, $t1, 0x0000001F :: rt 0x00000001 rs 0x00000010, imm 0x31415927
+sltiu $t0, $t1, 0x00000009 :: rt 0x00000000 rs 0x31415927, imm 0x00000009
+sltiu $t0, $t1, 0x0000000A :: rt 0x00000000 rs 0x31415927, imm 0x0000000a
+sltiu $t0, $t1, 0x00000000 :: rt 0x00000000 rs 0x00088000, imm 0x0000000a
+sltiu $t0, $t1, 0x00000001 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+sltiu $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+sltiu $t0, $t1, 16 :: rt 0x00000000 rs 0x00010000, imm 0x00000010
+sltiu $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+sltiu $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+sltiu $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SLTU
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x7fffffff, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x31415927, rt 0xee00ee00
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x000000ff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x7fffffff, rt 0x80000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xff000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x0dd00000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000002
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000000f
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000010
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000020
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x00000021
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x00000001
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000010
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+sltu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SRA
+sra $t0, $t1, 0x00000000 :: rt 0x00000001 rs 0x00000001, imm 0x31415927
+sra $t0, $t1, 0x00000001 :: rt 0x18a0ac93 rs 0x31415927, imm 0x00000001
+sra $t0, $t1, 0x00000002 :: rt 0x0c505649 rs 0x31415927, imm 0x00000002
+sra $t0, $t1, 0x0000000F :: rt 0x00006282 rs 0x31415927, imm 0x0000000f
+sra $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+sra $t0, $t1, 0x0000001F :: rt 0x00000000 rs 0x00000010, imm 0x31415927
+sra $t0, $t1, 0x00000009 :: rt 0x0018a0ac rs 0x31415927, imm 0x00000009
+sra $t0, $t1, 0x0000000A :: rt 0x000c5056 rs 0x31415927, imm 0x0000000a
+sra $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x0000000a
+sra $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
+sra $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+sra $t0, $t1, 16 :: rt 0x00000001 rs 0x00010000, imm 0x00000010
+sra $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+sra $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+sra $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SRAV
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0x80000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srav $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srav $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srav $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0xffffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0x0c505649 rs 0x31415927, rt 0x00000002
+srav $t0, $t1, $t2 :: rd 0x00006282 rs 0x31415927, rt 0x0000000f
+srav $t0, $t1, $t2 :: rd 0x00003141 rs 0x31415927, rt 0x00000010
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+srav $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+srav $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000021
+srav $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00044000 rs 0x00088000, rt 0x00000001
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+srav $t0, $t1, $t2 :: rd 0x00000001 rs 0x00010000, rt 0x00000010
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srav $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SRL
+srl $t0, $t1, 0x00000000 :: rt 0x00000001 rs 0x00000001, imm 0x31415927
+srl $t0, $t1, 0x00000001 :: rt 0x18a0ac93 rs 0x31415927, imm 0x00000001
+srl $t0, $t1, 0x00000002 :: rt 0x0c505649 rs 0x31415927, imm 0x00000002
+srl $t0, $t1, 0x0000000F :: rt 0x00006282 rs 0x31415927, imm 0x0000000f
+srl $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
+srl $t0, $t1, 0x0000001F :: rt 0x00000000 rs 0x00000010, imm 0x31415927
+srl $t0, $t1, 0x00000009 :: rt 0x0018a0ac rs 0x31415927, imm 0x00000009
+srl $t0, $t1, 0x0000000A :: rt 0x000c5056 rs 0x31415927, imm 0x0000000a
+srl $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x0000000a
+srl $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
+srl $t0, $t1, 31 :: rt 0x00000000 rs 0x00088000, imm 0x0000001f
+srl $t0, $t1, 16 :: rt 0x00000001 rs 0x00010000, imm 0x00000010
+srl $t0, $t1, 17 :: rt 0x00000000 rs 0x00010000, imm 0x00000011
+srl $t0, $t1, 18 :: rt 0x00000000 rs 0x00010000, imm 0x00000012
+srl $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+SRLV
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x80000000
+srlv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0xff000000
+srlv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x0dd00000
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srlv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0xffffffff, rt 0xffffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0x0c505649 rs 0x31415927, rt 0x00000002
+srlv $t0, $t1, $t2 :: rd 0x00006282 rs 0x31415927, rt 0x0000000f
+srlv $t0, $t1, $t2 :: rd 0x00003141 rs 0x31415927, rt 0x00000010
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x31415927, rt 0x0000001f
+srlv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000020
+srlv $t0, $t1, $t2 :: rd 0x18a0ac93 rs 0x31415927, rt 0x00000021
+srlv $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00044000 rs 0x00088000, rt 0x00000001
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00088000, rt 0x0000001f
+srlv $t0, $t1, $t2 :: rd 0x00000001 rs 0x00010000, rt 0x00000010
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000011
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00010000, rt 0x00000012
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+srlv $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SUBU
+subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x31414817 rs 0x31415927, rt 0x00001110
+subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x80000001 rs 0x80000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x81000000 rs 0x80000000, rt 0xff000000
+subu $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+subu $t0, $t1, $t2 :: rd 0x31415928 rs 0x31415927, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x43406b27 rs 0x31415927, rt 0xee00ee00
+subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x81000000 rs 0x80000000, rt 0xff000000
+subu $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+subu $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x31415925 rs 0x31415927, rt 0x00000002
+subu $t0, $t1, $t2 :: rd 0x31415918 rs 0x31415927, rt 0x0000000f
+subu $t0, $t1, $t2 :: rd 0x31415917 rs 0x31415927, rt 0x00000010
+subu $t0, $t1, $t2 :: rd 0x31415908 rs 0x31415927, rt 0x0000001f
+subu $t0, $t1, $t2 :: rd 0x31415907 rs 0x31415927, rt 0x00000020
+subu $t0, $t1, $t2 :: rd 0x31415906 rs 0x31415927, rt 0x00000021
+subu $t0, $t1, $t2 :: rd 0x00088000 rs 0x00088000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00087fff rs 0x00088000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0x00087fe1 rs 0x00088000, rt 0x0000001f
+subu $t0, $t1, $t2 :: rd 0x0000fff0 rs 0x00010000, rt 0x00000010
+subu $t0, $t1, $t2 :: rd 0x0000ffef rs 0x00010000, rt 0x00000011
+subu $t0, $t1, $t2 :: rd 0x0000ffee rs 0x00010000, rt 0x00000012
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+SUB
+subu $t0, $t1, $t2 :: rd 0x31415928 rs 0x31415927, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x0a2941ff rs 0x31415927, rt 0x27181728
+subu $t0, $t1, $t2 :: rd 0x9a2941ff rs 0x31415927, rt 0x97181728
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0xffffffff
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+subu $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0x7fffffff
+subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+XOR
+xor $t0, $t1, $t2 :: rd 0xcebea6d8 rs 0x31415927, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0xdf41b727 rs 0x31415927, rt 0xee00ee00
+xor $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x80000000, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x7f000000 rs 0x80000000, rt 0xff000000
+xor $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+xor $t0, $t1, $t2 :: rd 0xcebea6d8 rs 0x31415927, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0xdf41b727 rs 0x31415927, rt 0xee00ee00
+xor $t0, $t1, $t2 :: rd 0x000000ff rs 0x00000000, rt 0x000000ff
+xor $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x80000000 rs 0x00000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x7fffffff, rt 0x80000000
+xor $t0, $t1, $t2 :: rd 0x7f000000 rs 0x80000000, rt 0xff000000
+xor $t0, $t1, $t2 :: rd 0x722fffff rs 0x7fffffff, rt 0x0dd00000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
+xor $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0xffffffff, rt 0xffffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x7fffffff, rt 0x7fffffff
+xor $t0, $t1, $t2 :: rd 0x00000000 rs 0x0000ffff, rt 0x0000ffff
+XORI
+xori $t0, $t1, 0xffff :: rt 0x3141a6d8 rs 0x31415927, imm 0x0000ffff
+xori $t0, $t1, 0xee00 :: rt 0x3141b727 rs 0x31415927, imm 0x0000ee00
+xori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+xori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+xori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+xori $t0, $t1, 0 :: rt 0x00000000 rs 0x00000000, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+xori $t0, $t1, 0 :: rt 0x7fffffff rs 0x7fffffff, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+xori $t0, $t1, 0x8000 :: rt 0x7fff7fff rs 0x7fffffff, imm 0x00008000
+xori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+xori $t0, $t1, 0x0dd0 :: rt 0x7ffff22f rs 0x7fffffff, imm 0x00000dd0
+xori $t0, $t1, 0xffff :: rt 0x3141a6d8 rs 0x31415927, imm 0x0000ffff
+xori $t0, $t1, 0xee00 :: rt 0x3141b727 rs 0x31415927, imm 0x0000ee00
+xori $t0, $t1, 255 :: rt 0x000000ff rs 0x00000000, imm 0x000000ff
+xori $t0, $t1, 0 :: rt 0x00000001 rs 0x00000001, imm 0x00000000
+xori $t0, $t1, 1 :: rt 0x00000001 rs 0x00000000, imm 0x00000001
+xori $t0, $t1, 0 :: rt 0xffffffff rs 0xffffffff, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x00008000 rs 0x00000000, imm 0x00008000
+xori $t0, $t1, 0 :: rt 0x00008000 rs 0x00008000, imm 0x00000000
+xori $t0, $t1, 0x8000 :: rt 0x80008000 rs 0x80000000, imm 0x00008000
+xori $t0, $t1, 0x8000 :: rt 0x7fff7fff rs 0x7fffffff, imm 0x00008000
+xori $t0, $t1, 0xff00 :: rt 0x8000ff00 rs 0x80000000, imm 0x0000ff00
+xori $t0, $t1, 0x0dd0 :: rt 0x7ffff22f rs 0x7fffffff, imm 0x00000dd0
+xori $t0, $t1, 0 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+xori $t0, $t1, 0xffff :: rt 0x0000ffff rs 0x00000000, imm 0x0000ffff
+xori $t0, $t1, 0xffff :: rt 0xffff0000 rs 0xffffffff, imm 0x0000ffff
+xori $t0, $t1, 0x7fff :: rt 0x7fff8000 rs 0x7fffffff, imm 0x00007fff
+xori $t0, $t1, 0x0000 :: rt 0x0000ffff rs 0x0000ffff, imm 0x00000000
+MFHI MFLO
+mfhi mflo :: HI: 0x31415927, LO: 0x31415926
+mfhi mflo :: HI: 0x0, LO: 0xffffffff
+mfhi mflo :: HI: 0xffffffff, LO: 0xfffffffe
+mfhi mflo :: HI: 0xffffffff, LO: 0xfffffffe
+mfhi mflo :: HI: 0x8000, LO: 0x7fff
+mfhi mflo :: HI: 0x80000000, LO: 0x7fffffff
+mfhi mflo :: HI: 0xffff, LO: 0xfffe
+mfhi mflo :: HI: 0x7fff, LO: 0x7ffe
+mfhi mflo :: HI: 0xdd0, LO: 0xdcf
+mfhi mflo :: HI: 0xff00, LO: 0xfeff
diff --git a/main/none/tests/mips32/MIPS32int.vgtest b/main/none/tests/mips32/MIPS32int.vgtest
new file mode 100644
index 0000000..a4781ae
--- /dev/null
+++ b/main/none/tests/mips32/MIPS32int.vgtest
@@ -0,0 +1,2 @@
+prog: MIPS32int
+vgopts: -q
diff --git a/main/none/tests/mips32/Makefile.am b/main/none/tests/mips32/Makefile.am
new file mode 100644
index 0000000..2ea782c
--- /dev/null
+++ b/main/none/tests/mips32/Makefile.am
@@ -0,0 +1,38 @@
+
+include $(top_srcdir)/Makefile.tool-tests.am
+
+dist_noinst_SCRIPTS = filter_stderr
+
+EXTRA_DIST = \
+ branches.stdout.exp branches.stderr.exp branches.vgtest \
+ FPUarithmetic.stdout.exp FPUarithmetic.stdout.exp-mips32 \
+ FPUarithmetic.stderr.exp FPUarithmetic.vgtest \
+ LoadStore.stdout.exp LoadStore.stdout.exp-BE LoadStore.stderr.exp \
+ LoadStore.vgtest \
+ LoadStore1.stdout.exp LoadStore1.stdout.exp-LE LoadStore1.stderr.exp \
+ LoadStore1.vgtest \
+ MemCpyTest.stdout.exp MemCpyTest.stderr.exp MemCpyTest.vgtest \
+ MIPS32int.stdout.exp MIPS32int.stdout.exp-BE MIPS32int.stdout.exp-mips32 \
+ MIPS32int.stderr.exp MIPS32int.vgtest \
+ MoveIns.stdout.exp MoveIns.stdout.exp-BE MoveIns.stderr.exp MoveIns.vgtest \
+ round.stdout.exp round.stderr.exp round.vgtest \
+ vfp.stdout.exp vfp.stdout.exp-BE vfp.stdout.exp-mips32 vfp.stderr.exp \
+ vfp.vgtest
+
+check_PROGRAMS = \
+ allexec \
+ branches \
+ FPUarithmetic \
+ LoadStore \
+ LoadStore1 \
+ MemCpyTest \
+ MIPS32int \
+ MoveIns \
+ round \
+ vfp
+
+AM_CFLAGS += @FLAG_M32@
+AM_CXXFLAGS += @FLAG_M32@
+AM_CCASFLAGS += @FLAG_M32@
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
diff --git a/main/none/tests/mips32/Makefile.in b/main/none/tests/mips32/Makefile.in
new file mode 100644
index 0000000..7edc6f5
--- /dev/null
+++ b/main/none/tests/mips32/Makefile.in
@@ -0,0 +1,794 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = allexec$(EXEEXT) branches$(EXEEXT) \
+ FPUarithmetic$(EXEEXT) LoadStore$(EXEEXT) LoadStore1$(EXEEXT) \
+ MemCpyTest$(EXEEXT) MIPS32int$(EXEEXT) MoveIns$(EXEEXT) \
+ round$(EXEEXT) vfp$(EXEEXT)
+subdir = none/tests/mips32
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+FPUarithmetic_SOURCES = FPUarithmetic.c
+FPUarithmetic_OBJECTS = FPUarithmetic.$(OBJEXT)
+FPUarithmetic_LDADD = $(LDADD)
+LoadStore_SOURCES = LoadStore.c
+LoadStore_OBJECTS = LoadStore.$(OBJEXT)
+LoadStore_LDADD = $(LDADD)
+LoadStore1_SOURCES = LoadStore1.c
+LoadStore1_OBJECTS = LoadStore1.$(OBJEXT)
+LoadStore1_LDADD = $(LDADD)
+MIPS32int_SOURCES = MIPS32int.c
+MIPS32int_OBJECTS = MIPS32int.$(OBJEXT)
+MIPS32int_LDADD = $(LDADD)
+MemCpyTest_SOURCES = MemCpyTest.c
+MemCpyTest_OBJECTS = MemCpyTest.$(OBJEXT)
+MemCpyTest_LDADD = $(LDADD)
+MoveIns_SOURCES = MoveIns.c
+MoveIns_OBJECTS = MoveIns.$(OBJEXT)
+MoveIns_LDADD = $(LDADD)
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+branches_SOURCES = branches.c
+branches_OBJECTS = branches.$(OBJEXT)
+branches_LDADD = $(LDADD)
+round_SOURCES = round.c
+round_OBJECTS = round.$(OBJEXT)
+round_LDADD = $(LDADD)
+vfp_SOURCES = vfp.c
+vfp_OBJECTS = vfp.$(OBJEXT)
+vfp_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = FPUarithmetic.c LoadStore.c LoadStore1.c MIPS32int.c \
+ MemCpyTest.c MoveIns.c allexec.c branches.c round.c vfp.c
+DIST_SOURCES = FPUarithmetic.c LoadStore.c LoadStore1.c MIPS32int.c \
+ MemCpyTest.c MoveIns.c allexec.c branches.c round.c vfp.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ branches.stdout.exp branches.stderr.exp branches.vgtest \
+ FPUarithmetic.stdout.exp FPUarithmetic.stdout.exp-mips32 \
+ FPUarithmetic.stderr.exp FPUarithmetic.vgtest \
+ LoadStore.stdout.exp LoadStore.stdout.exp-BE LoadStore.stderr.exp \
+ LoadStore.vgtest \
+ LoadStore1.stdout.exp LoadStore1.stdout.exp-LE LoadStore1.stderr.exp \
+ LoadStore1.vgtest \
+ MemCpyTest.stdout.exp MemCpyTest.stderr.exp MemCpyTest.vgtest \
+ MIPS32int.stdout.exp MIPS32int.stdout.exp-BE MIPS32int.stdout.exp-mips32 \
+ MIPS32int.stderr.exp MIPS32int.vgtest \
+ MoveIns.stdout.exp MoveIns.stdout.exp-BE MoveIns.stderr.exp MoveIns.vgtest \
+ round.stdout.exp round.stderr.exp round.vgtest \
+ vfp.stdout.exp vfp.stdout.exp-BE vfp.stdout.exp-mips32 vfp.stderr.exp \
+ vfp.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/mips32/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/mips32/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+FPUarithmetic$(EXEEXT): $(FPUarithmetic_OBJECTS) $(FPUarithmetic_DEPENDENCIES)
+ @rm -f FPUarithmetic$(EXEEXT)
+ $(LINK) $(FPUarithmetic_OBJECTS) $(FPUarithmetic_LDADD) $(LIBS)
+LoadStore$(EXEEXT): $(LoadStore_OBJECTS) $(LoadStore_DEPENDENCIES)
+ @rm -f LoadStore$(EXEEXT)
+ $(LINK) $(LoadStore_OBJECTS) $(LoadStore_LDADD) $(LIBS)
+LoadStore1$(EXEEXT): $(LoadStore1_OBJECTS) $(LoadStore1_DEPENDENCIES)
+ @rm -f LoadStore1$(EXEEXT)
+ $(LINK) $(LoadStore1_OBJECTS) $(LoadStore1_LDADD) $(LIBS)
+MIPS32int$(EXEEXT): $(MIPS32int_OBJECTS) $(MIPS32int_DEPENDENCIES)
+ @rm -f MIPS32int$(EXEEXT)
+ $(LINK) $(MIPS32int_OBJECTS) $(MIPS32int_LDADD) $(LIBS)
+MemCpyTest$(EXEEXT): $(MemCpyTest_OBJECTS) $(MemCpyTest_DEPENDENCIES)
+ @rm -f MemCpyTest$(EXEEXT)
+ $(LINK) $(MemCpyTest_OBJECTS) $(MemCpyTest_LDADD) $(LIBS)
+MoveIns$(EXEEXT): $(MoveIns_OBJECTS) $(MoveIns_DEPENDENCIES)
+ @rm -f MoveIns$(EXEEXT)
+ $(LINK) $(MoveIns_OBJECTS) $(MoveIns_LDADD) $(LIBS)
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+branches$(EXEEXT): $(branches_OBJECTS) $(branches_DEPENDENCIES)
+ @rm -f branches$(EXEEXT)
+ $(LINK) $(branches_OBJECTS) $(branches_LDADD) $(LIBS)
+round$(EXEEXT): $(round_OBJECTS) $(round_DEPENDENCIES)
+ @rm -f round$(EXEEXT)
+ $(LINK) $(round_OBJECTS) $(round_LDADD) $(LIBS)
+vfp$(EXEEXT): $(vfp_OBJECTS) $(vfp_DEPENDENCIES)
+ @rm -f vfp$(EXEEXT)
+ $(LINK) $(vfp_OBJECTS) $(vfp_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/FPUarithmetic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/LoadStore.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/LoadStore1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MIPS32int.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MemCpyTest.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MoveIns.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/branches.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/round.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vfp.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+allexec-allexec.o: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.o -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+
+allexec-allexec.obj: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.obj -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/mips32/MemCpyTest.c b/main/none/tests/mips32/MemCpyTest.c
new file mode 100644
index 0000000..7e1a60b
--- /dev/null
+++ b/main/none/tests/mips32/MemCpyTest.c
@@ -0,0 +1,57 @@
+#include <stdio.h>
+
+unsigned int mem1[] = {
+ 0x0485b210, 0x0485b190, 0x0485b1b0, 0x0485b260,
+ 0x0485b280, 0x0485b400, 0x0485b420, 0x0485b2f0,
+ 0x0485b300, 0x0485b3c0, 0x0485b3d0, 0x0485b470,
+ 0x0485b490, 0x048608b0, 0x048608a0, 0x048601f0,
+ 0x0485f240, 0x0485f1b0, 0x04860020, 0x0485f4d0,
+ 0x0485fb00, 0x048607b0, 0x04860470, 0x04860440,
+ 0x048606c0, 0x048604b0, 0x048605b0, 0x0485ac10,
+ 0x0485a570, 0x0485ac90, 0x0485ae60, 0x0485bc10,
+ 0x0485ba70, 0x0485c384, 0x0485df30, 0x0485ac00,
+ 0x04861560, 0x04861680, 0x04863700, 0x048617dc,
+ 0x0485e0d0, 0x0485e6a0, 0x0485ee80, 0x04860e10,
+ 0x04860f20, 0x04860fd0, 0x04863300, 0x04863378,
+ 0x0487b000, 0x04863490, 0x04858648, 0x0485810c,
+ 0x04868eb0, 0x00000001, 0x00000000, 0x00000000,
+ 0x00000000, 0x0487b010, 0x0487b010, 0x0487b018,
+ 0x0487b018, 0xffffffff, 0xffffffff, 0x00000000,
+ 0x00000000, 0x04019280, 0x84024238, 0x048572d0,
+ 0x04883000, 0x0487b2cc, 0x0487af24, 0x04873000,
+ 0x04853000, 0x04863000, 0x0487b2d8, 0x0487d340,
+ 0x048665b0, 0x0487b2dc, 0x0487b2d0, 0x0487b2e8,
+ 0x0485c384, 0x0485df30, 0x04857eb0, 0x048589f8,
+ 0x048587e0, 0x0487b2fc, 0x048579c0, 0x0487b2f0,
+ 0x0487b2e4, 0x0487b2d4, 0x04863490, 0x04868ef0,
+ 0x04858c2c, 0x0487b000, 0x048639a0, 0x0487b340,
+ 0x04858d68, 0x04858648, 0x04858f18, 0x04857978
+};
+
+unsigned int mem2[100];
+
+int main ()
+{
+ int i, out;
+ for (i = 0; i < 100; i++)
+ mem2[i] = 0;
+
+ __asm__ volatile(
+ "move $s0, %1\n\t" // s0 addr mem1
+ "move $a2, %2\n\t" // a2 addr mem2
+ " li $v0, 0\n\t" // v0 counter
+ " li $a1, 0x190\n\t" // a1 mem len
+ " begin:\n\t"
+ "addu $v1, $s0, $v0\n\t"
+ "lw $a0, 0($v1)\n\t"
+ "addu $v1, $a2, $v0\n\t"
+ "addiu $v0, $v0, 4\n\t"
+ "sw $a0, 0($v1)\n\t"
+ "bne $v0, $a1, begin\n\t"
+ : "=&r" (out)
+ : "r" (mem1), "r" (mem2)
+ : "s0", "a1", "a2", "v0", "v1", "cc", "memory"
+ );
+ for (i = 0; i < 100; i = i+4)
+ printf("0x%x, 0x%x, 0x%x, 0x%x\n", mem2[i], mem2[i+1], mem2[i+2], mem2[i+3]);
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/mips32/MemCpyTest.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/mips32/MemCpyTest.stderr.exp
diff --git a/main/none/tests/mips32/MemCpyTest.stdout.exp b/main/none/tests/mips32/MemCpyTest.stdout.exp
new file mode 100644
index 0000000..5047888
--- /dev/null
+++ b/main/none/tests/mips32/MemCpyTest.stdout.exp
@@ -0,0 +1,25 @@
+0x485b210, 0x485b190, 0x485b1b0, 0x485b260
+0x485b280, 0x485b400, 0x485b420, 0x485b2f0
+0x485b300, 0x485b3c0, 0x485b3d0, 0x485b470
+0x485b490, 0x48608b0, 0x48608a0, 0x48601f0
+0x485f240, 0x485f1b0, 0x4860020, 0x485f4d0
+0x485fb00, 0x48607b0, 0x4860470, 0x4860440
+0x48606c0, 0x48604b0, 0x48605b0, 0x485ac10
+0x485a570, 0x485ac90, 0x485ae60, 0x485bc10
+0x485ba70, 0x485c384, 0x485df30, 0x485ac00
+0x4861560, 0x4861680, 0x4863700, 0x48617dc
+0x485e0d0, 0x485e6a0, 0x485ee80, 0x4860e10
+0x4860f20, 0x4860fd0, 0x4863300, 0x4863378
+0x487b000, 0x4863490, 0x4858648, 0x485810c
+0x4868eb0, 0x1, 0x0, 0x0
+0x0, 0x487b010, 0x487b010, 0x487b018
+0x487b018, 0xffffffff, 0xffffffff, 0x0
+0x0, 0x4019280, 0x84024238, 0x48572d0
+0x4883000, 0x487b2cc, 0x487af24, 0x4873000
+0x4853000, 0x4863000, 0x487b2d8, 0x487d340
+0x48665b0, 0x487b2dc, 0x487b2d0, 0x487b2e8
+0x485c384, 0x485df30, 0x4857eb0, 0x48589f8
+0x48587e0, 0x487b2fc, 0x48579c0, 0x487b2f0
+0x487b2e4, 0x487b2d4, 0x4863490, 0x4868ef0
+0x4858c2c, 0x487b000, 0x48639a0, 0x487b340
+0x4858d68, 0x4858648, 0x4858f18, 0x4857978
diff --git a/main/none/tests/mips32/MemCpyTest.vgtest b/main/none/tests/mips32/MemCpyTest.vgtest
new file mode 100644
index 0000000..9bbebfe
--- /dev/null
+++ b/main/none/tests/mips32/MemCpyTest.vgtest
@@ -0,0 +1,2 @@
+prog: MemCpyTest
+vgopts: -q
diff --git a/main/none/tests/mips32/MoveIns.c b/main/none/tests/mips32/MoveIns.c
new file mode 100644
index 0000000..53ec672
--- /dev/null
+++ b/main/none/tests/mips32/MoveIns.c
@@ -0,0 +1,606 @@
+#include <stdio.h>
+
+const float fs_f[] = {
+ 0, 456.2489562, 3, -1,
+ 1384.6, -7.2945676, 1000000000, -5786.47,
+ 1752, 0.0024575, 0.00000001, -248562.76,
+ -45786.476, 456.2489562, 34.00046, 45786.476,
+ 1752065, 107, -45667.24, -7.2945676,
+ -347856.475, 356047.56, -1.0, 23.04
+};
+
+unsigned int mem[] = {
+ 0x4095A266, 0x66666666,
+ 0xBFF00000, 0x00000000,
+ 0x3FF00000, 0x00000000,
+ 0x252a2e2b, 0x262d2d2a,
+ 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x41D26580, 0xB487E5C9,
+ 0x42026580, 0xB750E388,
+ 0x3E45798E, 0xE2308C3A,
+ 0x3FBF9ADD, 0x3746F65F
+};
+
+// mfc1 rt, fs
+#define TESTINSNMOVE(instruction, offset, FS, RT) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FS"\n\t" \
+ "move %1, $" #RT "\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (mem) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
+}
+
+// mfhc1 rt, fs
+#define TESTINSNMOVEd(instruction, offset, FS, RT) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FS"\n\t" \
+ "move %1, $" #RT "\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (mem) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: fs %lf, rt 0x%x\n", \
+ instruction, out, out1); \
+}
+
+// mtc1 rt, fs
+#define TESTINSNMOVEt(instruction, offset, FS, RT) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "lw $" #RT ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FS"\n\t" \
+ "move %1, $" #RT "\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (mem) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
+}
+
+// mthc1 rt, fs
+#define TESTINSNMOVEtd(instruction, offset, FS, RT) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "lw $" #RT ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FS"\n\t" \
+ "move %1, $" #RT "\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (mem) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: fs %lf, rt 0x%x\n", \
+ instruction, out, out1); \
+}
+
+// mov.s fd, fs
+#define TESTINSNMOVE1s(instruction, offset, FD, FS) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (fs_f) \
+ : "cc", "memory" \
+ ); \
+ printf("%s :: fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
+}
+
+// mov.d fd, fs
+#define TESTINSNMOVE1d(instruction, offset, FD, FS) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (fs_f) \
+ : "cc", "memory" \
+ ); \
+ printf("%s ::fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
+}
+
+// movf rd, rs
+#define TESTINSNMOVE2(instruction, RDval, RSval, RD, RS, cc) \
+{ \
+ int out; \
+ __asm__ volatile( \
+ "li $t0, 1\n\t" \
+ "move $t1, %3\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 $t1, $f2\n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "move $" #RS ", %1\n\t" \
+ "move $" #RD ", %2\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RDval), "r" (cc) \
+ : "t0", "t1", #RD, #RS, "cc", "memory" \
+ ); \
+ printf("%s :: out: 0x%x, RDval: 0x%x, RSval: 0x%x, cc: %d\n", \
+ instruction, out, RDval, RSval, cc); \
+}
+
+// movf.s fd, fs
+#define TESTINSNMOVE2s(instruction, FD, FS, cc, offset) \
+{ \
+ float out; \
+ __asm__ volatile( \
+ "li $t0, 1\n\t" \
+ "move $t1, %1\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 $t1, $f2\n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FD"\n\t" \
+ : "=&f" (out) \
+ : "r" (cc), "r" (fs_f) \
+ : "t0", "t1", "cc", "memory" \
+ ); \
+ printf("%s :: out: %f, cc: %d\n", \
+ instruction, out, cc); \
+}
+
+// movf.d fd, fs
+#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \
+{ \
+ double out; \
+ int out1; \
+ int out2; \
+ __asm__ volatile( \
+ "li $t0, 1\n\t" \
+ "move $t1, %3\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 $t1, $f2\n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "move $t0, %4\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "mfc1 %1, $f4\n\t" \
+ "mfc1 %2, $f5\n\t" \
+ : "=&f" (out), "=&r" (out1), "=&r" (out2) \
+ : "r" (cc), "r" (mem) \
+ : "t0", "t1", "cc", "memory" \
+ ); \
+ printf("%s :: out: 0x%x 0x%x, cc: %d\n", \
+ instruction, out1, out2, cc); \
+}
+
+// movn.s fd, fs, rt
+#define TESTINSNMOVEN1s(instruction, offset, RTval, FD, FS, RT) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $" #RT ", %3\n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ "mtc1 $0, $" #FD "\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (fs_f), "r" (RTval) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: fs rt 0x%x\n", \
+ instruction, out1); \
+}
+
+// movn.d fd, fs, rt
+#define TESTINSNMOVEN1d(instruction, offset, RTval, FD, FS, RT) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $" #RT ", %3\n\t" \
+ "move $t0, %2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ "mtc1 $0, $" #FD "\n\t" \
+ "mtc1 $0, $" #FD + 1"\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (fs_f), "r" (RTval) \
+ : #RT, "cc", "memory" \
+ ); \
+ printf("%s :: fs %lf, rt 0x%x\n", \
+ instruction, out, out1); \
+}
+
+int main()
+{
+ printf("MFC1\n");
+ TESTINSNMOVE("mfc1 $t1, $f0", 0, f0, t1);
+ TESTINSNMOVE("mfc1 $t2, $f1", 4, f1, t2);
+ TESTINSNMOVE("mfc1 $t3, $f2", 8, f2, t3);
+ TESTINSNMOVE("mfc1 $t4, $f3", 12, f3, t4);
+ TESTINSNMOVE("mfc1 $t5, $f4", 16, f4, t5);
+ TESTINSNMOVE("mfc1 $t6, $f5", 20, f5, t6);
+ TESTINSNMOVE("mfc1 $t7, $f6", 24, f6, t7);
+ TESTINSNMOVE("mfc1 $v0, $f7", 28, f7, v0);
+ TESTINSNMOVE("mfc1 $v1, $f8", 32, f8, v1);
+ TESTINSNMOVE("mfc1 $s0, $f9", 36, f9, s0);
+ TESTINSNMOVE("mfc1 $s1, $f10", 40, f10, s1);
+ TESTINSNMOVE("mfc1 $s2, $f11", 44, f11, s2);
+ TESTINSNMOVE("mfc1 $s3, $f12", 48, f12, s3);
+ TESTINSNMOVE("mfc1 $s4, $f13", 52, f13, s4);
+ TESTINSNMOVE("mfc1 $s5, $f14", 56, f14, s5);
+ TESTINSNMOVE("mfc1 $s6, $f15", 60, f15, s6);
+ TESTINSNMOVE("mfc1 $s7, $f16", 64, f16, s7);
+ TESTINSNMOVE("mfc1 $a0, $f17", 0, f17, a0);
+ TESTINSNMOVE("mfc1 $a1, $f18", 4, f18, a1);
+ TESTINSNMOVE("mfc1 $a2, $f19", 8, f19, a2);
+ TESTINSNMOVE("mfc1 $a3, $f20", 12, f20, a3);
+ TESTINSNMOVE("mfc1 $v0, $f21", 16, f21, v0);
+ TESTINSNMOVE("mfc1 $v1, $f22", 20, f22, v1);
+ TESTINSNMOVE("mfc1 $t8, $f23", 24, f23, t8);
+ TESTINSNMOVE("mfc1 $t9, $f24", 28, f24, t9);
+ TESTINSNMOVE("mfc1 $t1, $f25", 32, f25, t1);
+ TESTINSNMOVE("mfc1 $t2, $f26", 36, f26, t2);
+
+ printf("MTC1\n");
+ TESTINSNMOVEt("mtc1 $t1, $f0", 0, f0, t1);
+ TESTINSNMOVEt("mtc1 $t2, $f1", 4, f1, t2);
+ TESTINSNMOVEt("mtc1 $t3, $f2", 8, f2, t3);
+ TESTINSNMOVEt("mtc1 $t4, $f3", 12, f3, t4);
+ TESTINSNMOVEt("mtc1 $t5, $f4", 16, f4, t5);
+ TESTINSNMOVEt("mtc1 $t6, $f5", 20, f5, t6);
+ TESTINSNMOVEt("mtc1 $t7, $f6", 24, f6, t7);
+ TESTINSNMOVEt("mtc1 $v0, $f7", 28, f7, v0);
+ TESTINSNMOVEt("mtc1 $v1, $f8", 32, f8, v1);
+ TESTINSNMOVEt("mtc1 $s0, $f9", 36, f9, s0);
+ TESTINSNMOVEt("mtc1 $s1, $f10", 40, f10, s1);
+ TESTINSNMOVEt("mtc1 $s2, $f11", 44, f11, s2);
+ TESTINSNMOVEt("mtc1 $s3, $f12", 48, f12, s3);
+ TESTINSNMOVEt("mtc1 $s4, $f13", 52, f13, s4);
+ TESTINSNMOVEt("mtc1 $s5, $f14", 56, f14, s5);
+ TESTINSNMOVEt("mtc1 $s6, $f15", 60, f15, s6);
+ TESTINSNMOVEt("mtc1 $s7, $f16", 64, f16, s7);
+ TESTINSNMOVEt("mtc1 $a0, $f17", 2, f17, a0);
+ TESTINSNMOVEt("mtc1 $a1, $f18", 6, f18, a1);
+ TESTINSNMOVEt("mtc1 $a2, $f19", 10, f19, a2);
+ TESTINSNMOVEt("mtc1 $a3, $f20", 14, f20, a3);
+ TESTINSNMOVEt("mtc1 $v0, $f21", 18, f21, v0);
+ TESTINSNMOVEt("mtc1 $v1, $f22", 22, f22, v1);
+ TESTINSNMOVEt("mtc1 $t8, $f23", 26, f23, t8);
+ TESTINSNMOVEt("mtc1 $t9, $f24", 30, f24, t9);
+ TESTINSNMOVEt("mtc1 $t1, $f25", 34, f25, t1);
+ TESTINSNMOVEt("mtc1 $t2, $f26", 38, f26, t2);
+
+ printf("MOV.S\n");
+ TESTINSNMOVE1s("mov.s $f0, $f0", 0, f0, f0);
+ TESTINSNMOVE1s("mov.s $f0, $f1", 4, f0, f1);
+ TESTINSNMOVE1s("mov.s $f1, $f2", 8, f1, f2);
+ TESTINSNMOVE1s("mov.s $f2, $f3", 12, f2, f3);
+ TESTINSNMOVE1s("mov.s $f3, $f4", 16, f3, f4);
+ TESTINSNMOVE1s("mov.s $f4, $f5", 20, f4, f5);
+ TESTINSNMOVE1s("mov.s $f5, $f6", 24, f5, f6);
+ TESTINSNMOVE1s("mov.s $f6, $f7", 28, f6, f7);
+ TESTINSNMOVE1s("mov.s $f7, $f8", 32, f7, f8);
+ TESTINSNMOVE1s("mov.s $f8, $f9", 36, f8, f9);
+ TESTINSNMOVE1s("mov.s $f9, $f10", 40, f9, f10);
+ TESTINSNMOVE1s("mov.s $f10, $f11", 44, f10, f11);
+ TESTINSNMOVE1s("mov.s $f11, $f12", 48, f11, f12);
+ TESTINSNMOVE1s("mov.s $f12, $f13", 52, f12, f13);
+ TESTINSNMOVE1s("mov.s $f13, $f14", 56, f13, f14);
+ TESTINSNMOVE1s("mov.s $f14, $f15", 60, f14, f15);
+ TESTINSNMOVE1s("mov.s $f15, $f16", 64, f15, f16);
+ TESTINSNMOVE1s("mov.s $f16, $f17", 0, f16, f17);
+ TESTINSNMOVE1s("mov.s $f17, $f18", 4, f17, f18);
+ TESTINSNMOVE1s("mov.s $f18, $f19", 8, f18, f19);
+ TESTINSNMOVE1s("mov.s $f19, $f20", 12, f19, f20);
+ TESTINSNMOVE1s("mov.s $f20, $f21", 16, f20, f21);
+ TESTINSNMOVE1s("mov.s $f21, $f22", 20, f21, f22);
+ TESTINSNMOVE1s("mov.s $f22, $f23", 24, f22, f23);
+ TESTINSNMOVE1s("mov.s $f23, $f24", 28, f23, f24);
+ TESTINSNMOVE1s("mov.s $f24, $f25", 32, f24, f25);
+ TESTINSNMOVE1s("mov.s $f25, $f26", 36, f25, f26);
+
+ printf("MOV.D\n");
+ TESTINSNMOVE1d("mov.d $f0, $f0", 0, f0, f0);
+ TESTINSNMOVE1d("mov.d $f0, $f0", 8, f0, f0);
+ TESTINSNMOVE1d("mov.d $f0, $f2", 16, f0, f2);
+ TESTINSNMOVE1d("mov.d $f2, $f4", 24, f2, f4);
+ TESTINSNMOVE1d("mov.d $f2, $f4", 32, f2, f4);
+ TESTINSNMOVE1d("mov.d $f4, $f6", 40, f4, f6);
+ TESTINSNMOVE1d("mov.d $f4, $f6", 48, f4, f6);
+ TESTINSNMOVE1d("mov.d $f6, $f8", 56, f6, f8);
+ TESTINSNMOVE1d("mov.d $f6, $f8", 64, f6, f8);
+ TESTINSNMOVE1d("mov.d $f8, $f10", 0, f8, f10);
+ TESTINSNMOVE1d("mov.d $f8, $f10", 8, f8, f10);
+ TESTINSNMOVE1d("mov.d $f10, $f12", 16, f10, f12);
+ TESTINSNMOVE1d("mov.d $f10, $f12", 24, f10, f12);
+ TESTINSNMOVE1d("mov.d $f12, $f14", 32, f12, f14);
+ TESTINSNMOVE1d("mov.d $f12, $f14", 40, f12, f14);
+ TESTINSNMOVE1d("mov.d $f14, $f16", 48, f14, f16);
+ TESTINSNMOVE1d("mov.d $f14, $f16", 56, f14, f16);
+ TESTINSNMOVE1d("mov.d $f16, $f18", 64, f16, f18);
+ TESTINSNMOVE1d("mov.d $f16, $f18", 0, f16, f18);
+ TESTINSNMOVE1d("mov.d $f18, $f20", 8, f18, f20);
+ TESTINSNMOVE1d("mov.d $f18, $f20", 16, f18, f20);
+ TESTINSNMOVE1d("mov.d $f20, $f22", 24, f20, f22);
+ TESTINSNMOVE1d("mov.d $f20, $f22", 32, f20, f22);
+ TESTINSNMOVE1d("mov.d $f22, $f24", 40, f22, f24);
+ TESTINSNMOVE1d("mov.d $f22, $f24", 48, f22, f24);
+ TESTINSNMOVE1d("mov.d $f24, $f26", 56, f24, f26);
+ TESTINSNMOVE1d("mov.d $f24, $f26", 64, f24, f26);
+
+ printf("MOVF\n");
+ TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0, 0xffffffff, t0, t1, 1);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0xffffffff, 0xffffffff, t0, t1, 0);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc0", 555, 0xffffffff, t0, t1, 1);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0, 5, t0, t1, 0);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0, -1, t0, t1, 1);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0xffffffff, 25, t0, t1, 0);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0xffffffff, 0, t0, t1, 1);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0xffffffff, 66, t0, t1, 0);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc4", 0, 0xffffffff, t0, t1, 1);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc4", 0xffffffff, 0xffffffff, t0, t1, 0);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc4", 555, 0xffffffff, t0, t1, 1);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc4", 0, 5, t0, t1, 0);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc4", 0, -1, t0, t1, 1);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc4", 0xffffffff, 25, t0, t1, 0);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc4", 0xffffffff, 0, t0, t1, 1);
+ TESTINSNMOVE2("movf $t0, $t1, $fcc4", 0xffffffff, 66, t0, t1, 0);
+
+ printf("MOVF.S\n");
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 0);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 4);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 8);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 12);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 16);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 20);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 24);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 28);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 32);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 36)
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 40)
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 44)
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 48)
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 52)
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 56)
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 0);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 4);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 8);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 12);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 16);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 20);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 24);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 28);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 32);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 36);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 40);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 44);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 48);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 52);
+ TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 0, 56);
+
+ printf("MOVF.D\n");
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 0);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 8);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 16);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 24);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 32);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 40);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 48);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 56);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 64);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 0)
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 8)
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 16)
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 24)
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 32)
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 40)
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 48);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 56);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 64);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 0);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 8);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 16);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 24);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 32);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 40);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 48);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 56);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 64);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 0);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 8);
+ TESTINSNMOVE2d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 16);
+
+ printf("MOVN.S\n");
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 0, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 4, 1, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 8, 0xffff, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 12, -1, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 16, 5, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 20, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 24, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 28, 5, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 32, 125487, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 36, 68, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 40, -122544, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 44, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 48, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 52, 0xffffffff, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 56, 0x80000000, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.s $f0, $f2, $t3", 60, 0x7fffffff, f0, f2, t3);
+
+ printf("MOVN.D\n");
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 0, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 4, 1, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 8, 0xffff, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 12, -1, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 16, 5, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 20, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 24, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 28, 5, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 32, 125487, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 36, 68, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 40, -122544, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 44, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 48, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 52, 0xffffffff, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 56, 0x80000000, f0, f2, t3);
+ TESTINSNMOVEN1s("movn.d $f0, $f2, $t3", 60, 0x7fffffff, f0, f2, t3);
+
+ printf("MOVT\n");
+ TESTINSNMOVE2("movt $t0, $t1, $fcc0", 0, 0xffffffff, t0, t1, 1);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc0", 0xffffffff, 0xffffffff, t0, t1, 0);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc0", 555, 0xffffffff, t0, t1, 1);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc0", 0, 5, t0, t1, 0);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc0", 0, -1, t0, t1, 1);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc0", 0xffffffff, 25, t0, t1, 0);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc0", 0xffffffff, 0, t0, t1, 1);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc0", 0xffffffff, 66, t0, t1, 0);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc4", 0, 0xffffffff, t0, t1, 1);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc4", 0xffffffff, 0xffffffff, t0, t1, 0);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc4", 555, 0xffffffff, t0, t1, 1);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc4", 0, 5, t0, t1, 0);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc4", 0, -1, t0, t1, 1);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc4", 0xffffffff, 25, t0, t1, 0);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc4", 0xffffffff, 0, t0, t1, 1);
+ TESTINSNMOVE2("movt $t0, $t1, $fcc4", 0xffffffff, 66, t0, t1, 0);
+
+ printf("MOVT.S\n");
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 0);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 4);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 8);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 12);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 16);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 20);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 24);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 28);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 32);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 36)
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 40)
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 44)
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 48)
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 52)
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 1, 56)
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 0);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 4);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 8);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 12);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 16);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 20);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 24);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 28);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 32);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 36);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 40);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 44);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 48);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 52);
+ TESTINSNMOVE2s("movt.s $f4, $f6, $fcc0", f4, f6, 0, 56);
+
+ printf("MOVT.D\n");
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 0);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 8);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 16);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 24);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 32);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 40);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 48);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 56);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 64);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 0)
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 8)
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 16)
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 24)
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 32)
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 40)
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 48);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 56);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 64);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 0);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 8);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 16);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 24);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 32);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 40);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 48);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 56);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 64);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 0);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 8);
+ TESTINSNMOVE2d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 16);
+
+ printf("MOVZ.S\n");
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 0, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 4, 1, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 8, 0xffff, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 12, -1, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 16, 5, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 20, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 24, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 24, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 28, 5, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 32, 125487, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 36, 68, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 40, -122544, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 44, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 48, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 52, 0xffffffff, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 56, 0x80000000, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 60, 0x7fffffff, f0, f2, t3);
+
+ printf("MOVZ.D\n");
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 0, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 4, 1, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 8, 0xffff, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 12, -1, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 16, 5, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 20, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 24, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 28, 5, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 32, 125487, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 36, 68, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 40, -122544, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 44, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 48, 0, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 52, 0xffffffff, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 56, 0x80000000, f0, f2, t3);
+ TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 60, 0x7fffffff, f0, f2, t3);
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/mips32/MoveIns.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/mips32/MoveIns.stderr.exp
diff --git a/main/none/tests/mips32/MoveIns.stdout.exp b/main/none/tests/mips32/MoveIns.stdout.exp
new file mode 100644
index 0000000..70306ee
--- /dev/null
+++ b/main/none/tests/mips32/MoveIns.stdout.exp
@@ -0,0 +1,339 @@
+MFC1
+mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mfc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mfc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mfc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mfc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mfc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mfc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mfc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mfc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mfc1 $a0, $f17 :: fs 4.676074, rt 0x4095a266
+mfc1 $a1, $f18 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $a2, $f19 :: fs -1.875000, rt 0xbff00000
+mfc1 $a3, $f20 :: fs 0.000000, rt 0x0
+mfc1 $v0, $f21 :: fs 1.875000, rt 0x3ff00000
+mfc1 $v1, $f22 :: fs 0.000000, rt 0x0
+mfc1 $t8, $f23 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $t9, $f24 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mfc1 $t2, $f26 :: fs nan, rt 0xffffffff
+MTC1
+mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mtc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mtc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mtc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mtc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mtc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mtc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mtc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mtc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mtc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mtc1 $a0, $f17 :: fs 271833904815561865428992.000000, rt 0x66664095
+mtc1 $a1, $f18 :: fs 0.000000, rt 0x6666
+mtc1 $a2, $f19 :: fs 0.000000, rt 0xbff0
+mtc1 $a3, $f20 :: fs 0.000000, rt 0x0
+mtc1 $v0, $f21 :: fs 0.000000, rt 0x3ff0
+mtc1 $v1, $f22 :: fs 0.000000, rt 0x2e2b0000
+mtc1 $t8, $f23 :: fs 0.000000, rt 0x2d2a252a
+mtc1 $t9, $f24 :: fs nan, rt 0xffff262d
+mtc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mtc1 $t2, $f26 :: fs 76148150529073774329856.000000, rt 0x6580ffff
+MOV.S
+mov.s $f0, $f0 :: fs 0.000000, rt 0x0
+mov.s $f0, $f1 :: fs 456.248962, rt 0x43e41fde
+mov.s $f1, $f2 :: fs 3.000000, rt 0x40400000
+mov.s $f2, $f3 :: fs -1.000000, rt 0xbf800000
+mov.s $f3, $f4 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f4, $f5 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f5, $f6 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f6, $f7 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f7, $f8 :: fs 1752.000000, rt 0x44db0000
+mov.s $f8, $f9 :: fs 0.002457, rt 0x3b210e02
+mov.s $f9, $f10 :: fs 0.000000, rt 0x322bcc77
+mov.s $f10, $f11 :: fs -248562.765625, rt 0xc872bcb1
+mov.s $f11, $f12 :: fs -45786.476562, rt 0xc732da7a
+mov.s $f12, $f13 :: fs 456.248962, rt 0x43e41fde
+mov.s $f13, $f14 :: fs 34.000462, rt 0x42080079
+mov.s $f14, $f15 :: fs 45786.476562, rt 0x4732da7a
+mov.s $f15, $f16 :: fs 1752065.000000, rt 0x49d5e008
+mov.s $f16, $f17 :: fs 0.000000, rt 0x0
+mov.s $f17, $f18 :: fs 456.248962, rt 0x43e41fde
+mov.s $f18, $f19 :: fs 3.000000, rt 0x40400000
+mov.s $f19, $f20 :: fs -1.000000, rt 0xbf800000
+mov.s $f20, $f21 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f21, $f22 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f22, $f23 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f23, $f24 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f24, $f25 :: fs 1752.000000, rt 0x44db0000
+mov.s $f25, $f26 :: fs 0.002457, rt 0x3b210e02
+MOV.D
+mov.d $f0, $f0 ::fs 11600973572943642624.000000, rt 0x0
+mov.d $f0, $f0 ::fs -0.007813, rt 0x40400000
+mov.d $f0, $f2 ::fs -52072.789633, rt 0x44ad1333
+mov.d $f2, $f4 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
+mov.d $f2, $f4 ::fs 0.000000, rt 0x44db0000
+mov.d $f4, $f6 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
+mov.d $f4, $f6 ::fs 11600980417357008896.000000, rt 0xc732da7a
+mov.d $f6, $f8 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
+mov.d $f6, $f8 ::fs 96757042599808.125000, rt 0x49d5e008
+mov.d $f8, $f10 ::fs 11600973572943642624.000000, rt 0x0
+mov.d $f8, $f10 ::fs -0.007813, rt 0x40400000
+mov.d $f10, $f12 ::fs -52072.789633, rt 0x44ad1333
+mov.d $f10, $f12 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
+mov.d $f12, $f14 ::fs 0.000000, rt 0x44db0000
+mov.d $f12, $f14 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
+mov.d $f14, $f16 ::fs 11600980417357008896.000000, rt 0xc732da7a
+mov.d $f14, $f16 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
+mov.d $f16, $f18 ::fs 96757042599808.125000, rt 0x49d5e008
+mov.d $f16, $f18 ::fs 11600973572943642624.000000, rt 0x0
+mov.d $f18, $f20 ::fs -0.007813, rt 0x40400000
+mov.d $f18, $f20 ::fs -52072.789633, rt 0x44ad1333
+mov.d $f20, $f22 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
+mov.d $f20, $f22 ::fs 0.000000, rt 0x44db0000
+mov.d $f22, $f24 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
+mov.d $f22, $f24 ::fs 11600980417357008896.000000, rt 0xc732da7a
+mov.d $f24, $f26 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
+mov.d $f24, $f26 ::fs 96757042599808.125000, rt 0x49d5e008
+MOVF
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVF.S
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+MOVF.D
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 0
+MOVN.S
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x40400000
+movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.s $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.s $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.s $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x42080079
+movn.s $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVN.D
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x40400000
+movn.d $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.d $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.d $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.d $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.d $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x42080079
+movn.d $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVT
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVT.S
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+MOVT.D
+movt.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+MOVZ.S
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.s $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+MOVZ.D
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.d $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.d $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
diff --git a/main/none/tests/mips32/MoveIns.stdout.exp-BE b/main/none/tests/mips32/MoveIns.stdout.exp-BE
new file mode 100644
index 0000000..2ff43c2
--- /dev/null
+++ b/main/none/tests/mips32/MoveIns.stdout.exp-BE
@@ -0,0 +1,339 @@
+MFC1
+mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mfc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mfc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mfc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mfc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mfc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mfc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mfc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mfc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mfc1 $a0, $f17 :: fs 4.676074, rt 0x4095a266
+mfc1 $a1, $f18 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $a2, $f19 :: fs -1.875000, rt 0xbff00000
+mfc1 $a3, $f20 :: fs 0.000000, rt 0x0
+mfc1 $v0, $f21 :: fs 1.875000, rt 0x3ff00000
+mfc1 $v1, $f22 :: fs 0.000000, rt 0x0
+mfc1 $t8, $f23 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $t9, $f24 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mfc1 $t2, $f26 :: fs nan, rt 0xffffffff
+MTC1
+mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mtc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mtc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mtc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mtc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mtc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mtc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mtc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mtc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mtc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mtc1 $a0, $f17 :: fs -0.000000, rt 0xa2666666
+mtc1 $a1, $f18 :: fs 272421228250166506553344.000000, rt 0x6666bff0
+mtc1 $a2, $f19 :: fs 0.000000, rt 0x0
+mtc1 $a3, $f20 :: fs 0.000000, rt 0x3ff0
+mtc1 $v0, $f21 :: fs 0.000000, rt 0x0
+mtc1 $v1, $f22 :: fs 0.000000, rt 0x252a
+mtc1 $t8, $f23 :: fs 0.000000, rt 0x2e2b262d
+mtc1 $t9, $f24 :: fs 0.000000, rt 0x2d2affff
+mtc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mtc1 $t2, $f26 :: fs nan, rt 0xffff41d2
+MOV.S
+mov.s $f0, $f0 :: fs 0.000000, rt 0x0
+mov.s $f0, $f1 :: fs 456.248962, rt 0x43e41fde
+mov.s $f1, $f2 :: fs 3.000000, rt 0x40400000
+mov.s $f2, $f3 :: fs -1.000000, rt 0xbf800000
+mov.s $f3, $f4 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f4, $f5 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f5, $f6 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f6, $f7 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f7, $f8 :: fs 1752.000000, rt 0x44db0000
+mov.s $f8, $f9 :: fs 0.002457, rt 0x3b210e02
+mov.s $f9, $f10 :: fs 0.000000, rt 0x322bcc77
+mov.s $f10, $f11 :: fs -248562.765625, rt 0xc872bcb1
+mov.s $f11, $f12 :: fs -45786.476562, rt 0xc732da7a
+mov.s $f12, $f13 :: fs 456.248962, rt 0x43e41fde
+mov.s $f13, $f14 :: fs 34.000462, rt 0x42080079
+mov.s $f14, $f15 :: fs 45786.476562, rt 0x4732da7a
+mov.s $f15, $f16 :: fs 1752065.000000, rt 0x49d5e008
+mov.s $f16, $f17 :: fs 0.000000, rt 0x0
+mov.s $f17, $f18 :: fs 456.248962, rt 0x43e41fde
+mov.s $f18, $f19 :: fs 3.000000, rt 0x40400000
+mov.s $f19, $f20 :: fs -1.000000, rt 0xbf800000
+mov.s $f20, $f21 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f21, $f22 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f22, $f23 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f23, $f24 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f24, $f25 :: fs 1752.000000, rt 0x44db0000
+mov.s $f25, $f26 :: fs 0.002457, rt 0x3b210e02
+MOV.D
+mov.d $f0, $f0 ::fs 0.000000, rt 0x43e41fde
+mov.d $f0, $f0 ::fs 32.000023, rt 0xbf800000
+mov.d $f0, $f2 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
+mov.d $f2, $f4 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
+mov.d $f2, $f4 ::fs 510015646723392374046720.000000, rt 0x3b210e02
+mov.d $f4, $f6 ::fs 0.000000, rt 0xc872bcb1
+mov.d $f4, $f6 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
+mov.d $f6, $f8 ::fs 12885895398.356678, rt 0x4732da7a
+mov.d $f6, $f8 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
+mov.d $f8, $f10 ::fs 0.000000, rt 0x43e41fde
+mov.d $f8, $f10 ::fs 32.000023, rt 0xbf800000
+mov.d $f10, $f12 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
+mov.d $f10, $f12 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
+mov.d $f12, $f14 ::fs 510015646723392374046720.000000, rt 0x3b210e02
+mov.d $f12, $f14 ::fs 0.000000, rt 0xc872bcb1
+mov.d $f14, $f16 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
+mov.d $f14, $f16 ::fs 12885895398.356678, rt 0x4732da7a
+mov.d $f16, $f18 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
+mov.d $f16, $f18 ::fs 0.000000, rt 0x43e41fde
+mov.d $f18, $f20 ::fs 32.000023, rt 0xbf800000
+mov.d $f18, $f20 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
+mov.d $f20, $f22 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
+mov.d $f20, $f22 ::fs 510015646723392374046720.000000, rt 0x3b210e02
+mov.d $f22, $f24 ::fs 0.000000, rt 0xc872bcb1
+mov.d $f22, $f24 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
+mov.d $f24, $f26 ::fs 12885895398.356678, rt 0x4732da7a
+mov.d $f24, $f26 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
+MOVF
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVF.S
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+MOVF.D
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 0
+MOVN.S
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x40400000
+movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.s $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.s $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.s $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x42080079
+movn.s $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVN.D
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x40400000
+movn.d $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.d $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.d $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.d $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.d $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x42080079
+movn.d $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVT
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVT.S
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+MOVT.D
+movt.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+MOVZ.S
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.s $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+MOVZ.D
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.d $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.d $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
diff --git a/main/none/tests/mips32/MoveIns.vgtest b/main/none/tests/mips32/MoveIns.vgtest
new file mode 100644
index 0000000..662bf4f
--- /dev/null
+++ b/main/none/tests/mips32/MoveIns.vgtest
@@ -0,0 +1,2 @@
+prog: MoveIns
+vgopts: -q
diff --git a/main/none/tests/mips32/allexec.c b/main/none/tests/mips32/allexec.c
new file mode 100644
index 0000000..b7177e8
--- /dev/null
+++ b/main/none/tests/mips32/allexec.c
@@ -0,0 +1,50 @@
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+extern char **environ;
+
+#define S(...) (fprintf(stdout, __VA_ARGS__),fflush(stdout))
+#define FORKEXECWAIT(exec_call) do { \
+ int status;\
+ pid_t child = fork(); \
+ if (child == 0) {exec_call; perror ("exec failed");} \
+ else if (child == -1) perror ("cannot fork\n"); \
+ else if (child != wait (&status)) perror ("error waiting child"); \
+ else S("child exited\n"); \
+ } while (0)
+
+void test_allexec (char *exec)
+{
+ FORKEXECWAIT (execlp(exec, exec, NULL));
+ FORKEXECWAIT (execlp(exec, exec, "constant_arg1", "constant_arg2", NULL));
+ FORKEXECWAIT (execve(exec, NULL, environ));
+}
+
+
+/* If a single argument "exec" is given, will execute itself
+ (in bi-arch, a 32 bit and 64 bit variant) via various exec system calls.
+ Note that this test can only be run after the prerequisite have been
+ prepared by allexec_prepare_prereq, which will a.o. make links
+ for the allexec32 and allexec64 executables. On single arch build,
+ these links points to the same executable to ensure this test works
+ everywhere the same.
+ No arguments or more arguments means just print its args. */
+int main(int argc, char **argv, char **envp)
+{
+ if ( (argc == 2) && (strcmp (argv[1], "exec") == 0)) {
+ S("%s will exec ./allexec32\n", argv[0]);
+ test_allexec ("./allexec32");
+ S("%s will exec ./allexec64\n", argv[0]);
+ test_allexec ("./allexec64");
+ } else {
+ int i;
+ S("program exec-ed:");
+ for (i = 0; i < argc; i++) S(" %s", argv[i]);
+ S("\n");
+ }
+ return 0;
+}
diff --git a/main/none/tests/mips32/branches.c b/main/none/tests/mips32/branches.c
new file mode 100644
index 0000000..67ce285
--- /dev/null
+++ b/main/none/tests/mips32/branches.c
@@ -0,0 +1,701 @@
+#include <stdio.h>
+
+#define TESTINST1(RSval, RD) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RD ", %1\n\t" \
+ "b end"#RSval"\n\t" \
+ "nop\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "end"#RSval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval) \
+ : #RD, "cc", "memory" \
+ ); \
+ printf("B :: %d, RSval: %d\n", \
+ out, RSval); \
+}
+
+#define TESTINST2(RSval, RD) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RD ", %1\n\t" \
+ "b end12"#RSval"\n\t" \
+ "addi $" #RD ", $" #RD", 3\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "end12"#RSval":\n\t" \
+ "addi $" #RD ", $" #RD", 3\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval) \
+ : #RD, "cc", "memory" \
+ ); \
+ printf("B :: %d, RSval: %d\n", \
+ out, RSval); \
+}
+
+#define TESTINST3(RSval, RD) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RD ", %1\n\t" \
+ "bal end21"#RSval"\n\t" \
+ "nop\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "b r_end"#RSval"\n\t" \
+ "nop\n\t" \
+ "end21"#RSval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "jr $ra\n\t" \
+ "r_end"#RSval":\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval) \
+ : #RD, "cc", "memory" \
+ ); \
+ printf("B BAL JR :: %d, RSval: %d\n", \
+ out, RSval); \
+}
+
+#define TESTINST3j(RSval, RD) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RD ", %1\n\t" \
+ "la $t0, end31"#RSval"\n\t" \
+ "jal $t0\n\t" \
+ "nop\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "la $t0, r_end11"#RSval"\n\t" \
+ "j $t0\n\t" \
+ "nop\n\t" \
+ "end31"#RSval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "jr $ra\n\t" \
+ "r_end11"#RSval":\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval) \
+ : #RD, "t0", "cc", "memory" \
+ ); \
+ printf("J JAL JR :: %d, RSval: %d\n", \
+ out, RSval); \
+}
+
+#define TESTINST3ja(RSval, RD) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RD ", %1\n\t" \
+ "la $t0, end41"#RSval"\n\t" \
+ "jalr $t1, $t0\n\t" \
+ "nop\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "la $t0, r_end21"#RSval"\n\t" \
+ "j $t0\n\t" \
+ "nop\n\t" \
+ "end41"#RSval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "jr $t1\n\t" \
+ "r_end21"#RSval":\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval) \
+ : #RD, "t0", "t1", "cc", "memory" \
+ ); \
+ printf("J JALR JR :: %d, RSval: %d\n", \
+ out, RSval); \
+}
+
+#define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RS ", %1\n\t" \
+ "move $" #RT ", %2\n\t" \
+ "move $" #RD ", %3\n\t" \
+ instruction" $" #RS ", $" #RT ", end"instruction#RDval"\n\t" \
+ "nop\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "end"instruction#RDval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RTval), "r" (RDval) \
+ : #RD, #RS, #RT, "cc", "memory" \
+ ); \
+ printf(instruction" :: %d, RSval: %d, RTval: %d\n", \
+ out, RSval, RTval); \
+}
+
+#define TESTINST5(instruction, RDval, RSval, RD, RS) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RS ", %1\n\t" \
+ "move $" #RD ", %2\n\t" \
+ instruction" $" #RS ", end"instruction#RDval"\n\t" \
+ "nop\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "end"instruction#RDval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RDval) \
+ : #RD, #RS, "cc", "memory" \
+ ); \
+ printf(instruction" :: %d, RSval: %d\n", \
+ out, RSval); \
+}
+
+#define TESTINST6(instruction, RDval, RSval, RD, RS) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RD ", %2\n\t" \
+ "move $" #RS ", %1\n\t" \
+ instruction" $" #RS ", end21"instruction#RDval"\n\t" \
+ "nop\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "b r_end"instruction#RDval"\n\t" \
+ "nop\n\t" \
+ "end21"instruction#RDval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "jr $ra\n\t" \
+ "r_end"instruction#RDval":\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RDval) \
+ : #RD, #RS, "cc", "memory" \
+ ); \
+ printf(instruction" :: %d, RSval: %d\n", \
+ out, RSval); \
+}
+
+#define TESTINST4l(instruction, RDval, RSval, RTval, RD, RS, RT) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RS ", %1\n\t" \
+ "move $" #RT ", %2\n\t" \
+ "move $" #RD ", %3\n\t" \
+ instruction" $" #RS ", $" #RT ", end"instruction#RDval"\n\t" \
+ "addi $" #RD ", $" #RD", 3\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "end"instruction#RDval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RTval), "r" (RDval) \
+ : #RD, #RS, #RT, "cc", "memory" \
+ ); \
+ printf(instruction" :: %d, RSval: %d, RTval: %d\n", \
+ out, RSval, RTval); \
+}
+
+#define TESTINST5l(instruction, RDval, RSval, RD, RS) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RS ", %1\n\t" \
+ "move $" #RD ", %2\n\t" \
+ instruction" $" #RS ", end"instruction#RDval"\n\t" \
+ "addi $" #RD ", $" #RD", 3\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "end"instruction#RDval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RDval) \
+ : #RD, #RS, "cc", "memory" \
+ ); \
+ printf(instruction" :: %d, RSval: %d\n", \
+ out, RSval); \
+}
+
+#define TESTINST6l(instruction, RDval, RSval, RD, RS) \
+{ \
+ unsigned int out = 0; \
+ __asm__ volatile( \
+ "move $" #RD ", %2\n\t" \
+ "move $" #RS ", %1\n\t" \
+ instruction" $" #RS ", end21"instruction#RDval"\n\t" \
+ "addi $" #RD ", $" #RD", 3\n\t" \
+ "addi $" #RD ", $" #RD", 5\n\t" \
+ "b r_end"instruction#RDval"\n\t" \
+ "nop\n\t" \
+ "end21"instruction#RDval":\n\t" \
+ "addi $" #RD ", $" #RD", 1\n\t" \
+ "jr $ra\n\t" \
+ "r_end"instruction#RDval":\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RDval) \
+ : #RD, #RS, "cc", "memory" \
+ ); \
+ printf(instruction" :: %d, RSval: %d\n", \
+ out, RSval); \
+}
+
+int main()
+{
+ printf("b \n");
+ TESTINST1(0, v0);
+ TESTINST1(1, v1);
+ TESTINST1(2, a0);
+ TESTINST1(3, a1);
+ TESTINST1(4, a2);
+ TESTINST1(5, a3);
+ TESTINST1(6, t0);
+ TESTINST1(7, t1);
+ TESTINST1(8, t2);
+ TESTINST1(9, t3);
+ TESTINST1(10, t4);
+ TESTINST1(11, t5);
+ TESTINST1(12, t6);
+ TESTINST1(13, t7);
+ TESTINST1(14, s0);
+ TESTINST1(15, s1);
+ TESTINST1(16, s2);
+ TESTINST1(17, s3);
+ TESTINST1(18, s4);
+ TESTINST1(19, s5);
+ TESTINST1(20, s6);
+ TESTINST1(21, s7);
+ TESTINST1(22, t8);
+ TESTINST1(23, t9);
+
+ printf("b \n");
+ TESTINST2(0, v0);
+ TESTINST2(1, v1);
+ TESTINST2(2, a0);
+ TESTINST2(3, a1);
+ TESTINST2(4, a2);
+ TESTINST2(5, a3);
+ TESTINST2(6, t0);
+ TESTINST2(7, t1);
+ TESTINST2(8, t2);
+ TESTINST2(9, t3);
+ TESTINST2(10, t4);
+ TESTINST2(11, t5);
+ TESTINST2(12, t6);
+ TESTINST2(13, t7);
+ TESTINST2(14, s0);
+ TESTINST2(15, s1);
+ TESTINST2(16, s2);
+ TESTINST2(17, s3);
+ TESTINST2(18, s4);
+ TESTINST2(19, s5);
+ TESTINST2(20, s6);
+ TESTINST2(21, s7);
+ TESTINST2(22, t8);
+ TESTINST2(23, t9);
+
+ printf("b, bal, jr \n");
+ TESTINST3(0, v0);
+ TESTINST3(1, v1);
+ TESTINST3(2, a0);
+ TESTINST3(3, a1);
+ TESTINST3(4, a2);
+ TESTINST3(5, a3);
+ TESTINST3(6, t0);
+ TESTINST3(7, t1);
+ TESTINST3(8, t2);
+ TESTINST3(9, t3);
+ TESTINST3(10, t4);
+ TESTINST3(11, t5);
+ TESTINST3(12, t6);
+ TESTINST3(13, t7);
+ TESTINST3(14, s0);
+ TESTINST3(15, s1);
+ TESTINST3(16, s2);
+ TESTINST3(17, s3);
+ TESTINST3(18, s4);
+ TESTINST3(19, s5);
+ TESTINST3(20, s6);
+ TESTINST3(21, s7);
+ TESTINST3(22, t8);
+ TESTINST3(23, t9);
+
+ printf("beq\n");
+ TESTINST4("beq", 0, 0, 1, v0, v1, a0);
+ TESTINST4("beq", 1, 1, 1, v1, a0, a1);
+ TESTINST4("beq", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
+ TESTINST4("beq", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
+ TESTINST4("beq", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
+ TESTINST4("beq", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
+ TESTINST4("beq", 6, 0x5, 0x5, t0, t1, t2);
+ TESTINST4("beq", 7, -3, -4, t1, t2, t3);
+ TESTINST4("beq", 8, 125, 125, t2, t3, t4);
+ TESTINST4("beq", 9, 0x80000000, 0x80000000, t3, t4, t5);
+ TESTINST4("beq", 10, 0xffffffff, 0x80000000, t4, t5, t6);
+ TESTINST4("beq", 11, 0x256, 0x256, t5, t6, t7);
+ TESTINST4("beq", 12, 0x55, 0x55, t6, t7, s0);
+ TESTINST4("beq", 13, 0xfff, 0xdd, s0, s1, s2);
+ TESTINST4("beq", 14, -1, 0x5, v0, t9, t8);
+ TESTINST4("beq", 15, -1, -1, t9, t8, a3);
+
+ printf("bne\n");
+ TESTINST4("bne", 0, 0, 1, v0, v1, a0);
+ TESTINST4("bne", 1, 1, 1, v1, a0, a1);
+ TESTINST4("bne", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
+ TESTINST4("bne", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
+ TESTINST4("bne", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
+ TESTINST4("bne", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
+ TESTINST4("bne", 6, 0x5, 0x5, t0, t1, t2);
+ TESTINST4("bne", 7, -3, -4, t1, t2, t3);
+ TESTINST4("bne", 8, 125, 125, t2, t3, t4);
+ TESTINST4("bne", 9, 0x80000000, 0x80000000, t3, t4, t5);
+ TESTINST4("bne", 10, 0xffffffff, 0x80000000, t4, t5, t6);
+ TESTINST4("bne", 11, 0x256, 0x256, t5, t6, t7);
+ TESTINST4("bne", 12, 0x55, 0x55, t6, t7, s0);
+ TESTINST4("bne", 13, 0xfff, 0xdd, s0, s1, s2);
+ TESTINST4("bne", 14, -1, 0x5, v0, t9, t8);
+ TESTINST4("bne", 15, -1, -1, t9, t8, a3);
+
+ printf("BEQZ\n");
+ TESTINST5("beqz", 0, 0, v0, v1);
+ TESTINST5("beqz", 1, 1, v1, a0);
+ TESTINST5("beqz", 2, 0xffffffff, a0, a1);
+ TESTINST5("beqz", 3, 0xffffffff, a1, a2);
+ TESTINST5("beqz", 4, 0xfffffffe, a2, t0);
+ TESTINST5("beqz", 5, 0xffffffff, a3, t0);
+ TESTINST5("beqz", 6, 0x5, t0, t1);
+ TESTINST5("beqz", 7, -3, t1, t2);
+ TESTINST5("beqz", 8, 125, t2, t3);
+ TESTINST5("beqz", 9, 0x80000000, t3, t4);
+ TESTINST5("beqz", 10, 0xffffffff, t4, t5);
+ TESTINST5("beqz", 11, 0x256, t5, t6);
+ TESTINST5("beqz", 12, 0x55, t6, t7);
+ TESTINST5("beqz", 13, 0xfff, s0, s1);
+ TESTINST5("beqz", 14, -1, v0, t9);
+ TESTINST5("beqz", 15, -1, t9, t8);
+
+ printf("BGEZ\n");
+ TESTINST5("bgez", 0, 0, v0, v1);
+ TESTINST5("bgez", 1, 1, v1, a0);
+ TESTINST5("bgez", 2, 0xffffffff, a0, a1);
+ TESTINST5("bgez", 3, 0xffffffff, a1, a2);
+ TESTINST5("bgez", 4, 0xfffffffe, a2, t0);
+ TESTINST5("bgez", 5, 0xffffffff, a3, t0);
+ TESTINST5("bgez", 6, 0x5, t0, t1);
+ TESTINST5("bgez", 7, -3, t1, t2);
+ TESTINST5("bgez", 8, 125, t2, t3);
+ TESTINST5("bgez", 9, 0x80000000, t3, t4);
+ TESTINST5("bgez", 10, 0xffffffff, t4, t5);
+ TESTINST5("bgez", 11, 0x256, t5, t6);
+ TESTINST5("bgez", 12, 0x55, t6, t7);
+ TESTINST5("bgez", 13, 0xfff, s0, s1);
+ TESTINST5("bgez", 14, -1, v0, t9);
+ TESTINST5("bgez", 15, -1, t9, t8);
+
+ printf("BGTZ\n");
+ TESTINST5("bgtz", 0, 0, v0, v1);
+ TESTINST5("bgtz", 1, 1, v1, a0);
+ TESTINST5("bgtz", 2, 0xffffffff, a0, a1);
+ TESTINST5("bgtz", 3, 0xffffffff, a1, a2);
+ TESTINST5("bgtz", 4, 0xfffffffe, a2, t0);
+ TESTINST5("bgtz", 5, 0xffffffff, a3, t0);
+ TESTINST5("bgtz", 6, 0x5, t0, t1);
+ TESTINST5("bgtz", 7, -3, t1, t2);
+ TESTINST5("bgtz", 8, 125, t2, t3);
+ TESTINST5("bgtz", 9, 0x80000000, t3, t4);
+ TESTINST5("bgtz", 10, 0xffffffff, t4, t5);
+ TESTINST5("bgtz", 11, 0x256, t5, t6);
+ TESTINST5("bgtz", 12, 0x55, t6, t7);
+ TESTINST5("bgtz", 13, 0xfff, s0, s1);
+ TESTINST5("bgtz", 14, -1, v0, t9);
+ TESTINST5("bgtz", 15, -1, t9, t8);
+
+ printf("BLEZ\n");
+ TESTINST5("blez", 0, 0, v0, v1);
+ TESTINST5("blez", 1, 1, v1, a0);
+ TESTINST5("blez", 2, 0xffffffff, a0, a1);
+ TESTINST5("blez", 3, 0xffffffff, a1, a2);
+ TESTINST5("blez", 4, 0xfffffffe, a2, t0);
+ TESTINST5("blez", 5, 0xffffffff, a3, t0);
+ TESTINST5("blez", 6, 0x5, t0, t1);
+ TESTINST5("blez", 7, -3, t1, t2);
+ TESTINST5("blez", 8, 125, t2, t3);
+ TESTINST5("blez", 9, 0x80000000, t3, t4);
+ TESTINST5("blez", 10, 0xffffffff, t4, t5);
+ TESTINST5("blez", 11, 0x256, t5, t6);
+ TESTINST5("blez", 12, 0x55, t6, t7);
+ TESTINST5("blez", 13, 0xfff, s0, s1);
+ TESTINST5("blez", 14, -1, v0, t9);
+ TESTINST5("blez", 15, -1, t9, t8);
+
+ printf("BLTZ\n");
+ TESTINST5("bltz", 0, 0, v0, v1);
+ TESTINST5("bltz", 1, 1, v1, a0);
+ TESTINST5("bltz", 2, 0xffffffff, a0, a1);
+ TESTINST5("bltz", 3, 0xffffffff, a1, a2);
+ TESTINST5("bltz", 4, 0xfffffffe, a2, t0);
+ TESTINST5("bltz", 5, 0xffffffff, a3, t0);
+ TESTINST5("bltz", 6, 0x5, t0, t1);
+ TESTINST5("bltz", 7, -3, t1, t2);
+ TESTINST5("bltz", 8, 125, t2, t3);
+ TESTINST5("bltz", 9, 0x80000000, t3, t4);
+ TESTINST5("bltz", 10, 0xffffffff, t4, t5);
+ TESTINST5("bltz", 11, 0x256, t5, t6);
+ TESTINST5("bltz", 12, 0x55, t6, t7);
+ TESTINST5("bltz", 13, 0xfff, s0, s1);
+ TESTINST5("bltz", 14, -1, v0, t9);
+ TESTINST5("bltz", 15, -1, t9, t8);
+
+ printf("BGEZAL\n");
+ TESTINST6("bgezal", 0, 0, v0, v1);
+ TESTINST6("bgezal", 1, 1, v1, a0);
+ TESTINST6("bgezal", 2, 0xffffffff, a0, a1);
+ TESTINST6("bgezal", 3, 0xffffffff, a1, a2);
+ TESTINST6("bgezal", 4, 0xfffffffe, a2, t0);
+ TESTINST6("bgezal", 5, 0xffffffff, a3, t0);
+ TESTINST6("bgezal", 6, 0x5, t0, t1);
+ TESTINST6("bgezal", 7, -3, t1, t2);
+ TESTINST6("bgezal", 8, 125, t2, t3);
+ TESTINST6("bgezal", 9, 0x80000000, t3, t4);
+ TESTINST6("bgezal", 10, 0xffffffff, t4, t5);
+ TESTINST6("bgezal", 11, 0x256, t5, t6);
+ TESTINST6("bgezal", 12, 0x55, t6, t7);
+ TESTINST6("bgezal", 13, 0xfff, s0, s1);
+ TESTINST6("bgezal", 14, -1, v0, t9);
+ TESTINST6("bgezal", 15, -1, t9, t8);
+
+ printf("BLTZAL\n");
+ TESTINST6("bltzal", 0, 0, v0, v1);
+ TESTINST6("bltzal", 1, 1, v1, a0);
+ TESTINST6("bltzal", 2, 0xffffffff, a0, a1);
+ TESTINST6("bltzal", 3, 0xffffffff, a1, a2);
+ TESTINST6("bltzal", 4, 0xfffffffe, a2, t0);
+ TESTINST6("bltzal", 5, 0xffffffff, a3, t0);
+ TESTINST6("bltzal", 6, 0x5, t0, t1);
+ TESTINST6("bltzal", 7, -3, t1, t2);
+ TESTINST6("bltzal", 8, 125, t2, t3);
+ TESTINST6("bltzal", 9, 0x80000000, t3, t4);
+ TESTINST6("bltzal", 10, 0xffffffff, t4, t5);
+ TESTINST6("bltzal", 11, 0x256, t5, t6);
+ TESTINST6("bltzal", 12, 0x55, t6, t7);
+ TESTINST6("bltzal", 13, 0xfff, s0, s1);
+ TESTINST6("bltzal", 14, -1, v0, t9);
+ TESTINST6("bltzal", 15, -1, t9, t8);
+
+ printf("BNEZ\n");
+ TESTINST5("bnez", 0, 0, v0, v1);
+ TESTINST5("bnez", 1, 1, v1, a0);
+ TESTINST5("bnez", 2, 0xffffffff, a0, a1);
+ TESTINST5("bnez", 3, 0xffffffff, a1, a2);
+ TESTINST5("bnez", 4, 0xfffffffe, a2, t0);
+ TESTINST5("bnez", 5, 0xffffffff, a3, t0);
+ TESTINST5("bnez", 6, 0x5, t0, t1);
+ TESTINST5("bnez", 7, -3, t1, t2);
+ TESTINST5("bnez", 8, 125, t2, t3);
+ TESTINST5("bnez", 9, 0x80000000, t3, t4);
+ TESTINST5("bnez", 10, 0xffffffff, t4, t5);
+ TESTINST5("bnez", 11, 0x256, t5, t6);
+ TESTINST5("bnez", 12, 0x55, t6, t7);
+ TESTINST5("bnez", 13, 0xfff, s0, s1);
+ TESTINST5("bnez", 14, -1, v0, t9);
+ TESTINST5("bnez", 15, -1, t9, t8);
+
+ printf("beql\n");
+ TESTINST4l("beql", 0, 0, 1, v0, v1, a0);
+ TESTINST4l("beql", 1, 1, 1, v1, a0, a1);
+ TESTINST4l("beql", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
+ TESTINST4l("beql", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
+ TESTINST4l("beql", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
+ TESTINST4l("beql", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
+ TESTINST4l("beql", 6, 0x5, 0x5, t0, t1, t2);
+ TESTINST4l("beql", 7, -3, -4, t1, t2, t3);
+ TESTINST4l("beql", 8, 125, 125, t2, t3, t4);
+ TESTINST4l("beql", 9, 0x80000000, 0x80000000, t3, t4, t5);
+ TESTINST4l("beql", 10, 0xffffffff, 0x80000000, t4, t5, t6);
+ TESTINST4l("beql", 11, 0x256, 0x256, t5, t6, t7);
+ TESTINST4l("beql", 12, 0x55, 0x55, t6, t7, s0);
+ TESTINST4l("beql", 13, 0xfff, 0xdd, s0, s1, s2);
+ TESTINST4l("beql", 14, -1, 0x5, v0, t9, t8);
+ TESTINST4l("beql", 15, -1, -1, t9, t8, a3);
+
+ printf("BGEZALL\n");
+ TESTINST5l("bgezall", 0, 0, v0, v1);
+ TESTINST5l("bgezall", 1, 1, v1, a0);
+ TESTINST5l("bgezall", 2, 0xffffffff, a0, a1);
+ TESTINST5l("bgezall", 3, 0xffffffff, a1, a2);
+ TESTINST5l("bgezall", 4, 0xfffffffe, a2, t0);
+ TESTINST5l("bgezall", 5, 0xffffffff, a3, t0);
+ TESTINST5l("bgezall", 6, 0x5, t0, t1);
+ TESTINST5l("bgezall", 7, -3, t1, t2);
+ TESTINST5l("bgezall", 8, 125, t2, t3);
+ TESTINST5l("bgezall", 9, 0x80000000, t3, t4);
+ TESTINST5l("bgezall", 10, 0xffffffff, t4, t5);
+ TESTINST5l("bgezall", 11, 0x256, t5, t6);
+ TESTINST5l("bgezall", 12, 0x55, t6, t7);
+ TESTINST5l("bgezall", 13, 0xfff, s0, s1);
+ TESTINST5l("bgezall", 14, -1, v0, t9);
+ TESTINST5l("bgezall", 15, -1, t9, t8);
+
+ printf("BGEZL\n");
+ TESTINST5l("bgezl", 0, 0, v0, v1);
+ TESTINST5l("bgezl", 1, 1, v1, a0);
+ TESTINST5l("bgezl", 2, 0xffffffff, a0, a1);
+ TESTINST5l("bgezl", 3, 0xffffffff, a1, a2);
+ TESTINST5l("bgezl", 4, 0xfffffffe, a2, t0);
+ TESTINST5l("bgezl", 5, 0xffffffff, a3, t0);
+ TESTINST5l("bgezl", 6, 0x5, t0, t1);
+ TESTINST5l("bgezl", 7, -3, t1, t2);
+ TESTINST5l("bgezl", 8, 125, t2, t3);
+ TESTINST5l("bgezl", 9, 0x80000000, t3, t4);
+ TESTINST5l("bgezl", 10, 0xffffffff, t4, t5);
+ TESTINST5l("bgezl", 11, 0x256, t5, t6);
+ TESTINST5l("bgezl", 12, 0x55, t6, t7);
+ TESTINST5l("bgezl", 13, 0xfff, s0, s1);
+ TESTINST5l("bgezl", 14, -1, v0, t9);
+ TESTINST5l("bgezl", 15, -1, t9, t8);
+
+ printf("BGTZL\n");
+ TESTINST5l("bgtzl", 0, 0, v0, v1);
+ TESTINST5l("bgtzl", 1, 1, v1, a0);
+ TESTINST5l("bgtzl", 2, 0xffffffff, a0, a1);
+ TESTINST5l("bgtzl", 3, 0xffffffff, a1, a2);
+ TESTINST5l("bgtzl", 4, 0xfffffffe, a2, t0);
+ TESTINST5l("bgtzl", 5, 0xffffffff, a3, t0);
+ TESTINST5l("bgtzl", 6, 0x5, t0, t1);
+ TESTINST5l("bgtzl", 7, -3, t1, t2);
+ TESTINST5l("bgtzl", 8, 125, t2, t3);
+ TESTINST5l("bgtzl", 9, 0x80000000, t3, t4);
+ TESTINST5l("bgtzl", 10, 0xffffffff, t4, t5);
+ TESTINST5l("bgtzl", 11, 0x256, t5, t6);
+ TESTINST5l("bgtzl", 12, 0x55, t6, t7);
+ TESTINST5l("bgtzl", 13, 0xfff, s0, s1);
+ TESTINST5l("bgtzl", 14, -1, v0, t9);
+ TESTINST5l("bgtzl", 15, -1, t9, t8);
+
+ printf("BLEZL\n");
+ TESTINST5l("blezl", 0, 0, v0, v1);
+ TESTINST5l("blezl", 1, 1, v1, a0);
+ TESTINST5l("blezl", 2, 0xffffffff, a0, a1);
+ TESTINST5l("blezl", 3, 0xffffffff, a1, a2);
+ TESTINST5l("blezl", 4, 0xfffffffe, a2, t0);
+ TESTINST5l("blezl", 5, 0xffffffff, a3, t0);
+ TESTINST5l("blezl", 6, 0x5, t0, t1);
+ TESTINST5l("blezl", 7, -3, t1, t2);
+ TESTINST5l("blezl", 8, 125, t2, t3);
+ TESTINST5l("blezl", 9, 0x80000000, t3, t4);
+ TESTINST5l("blezl", 10, 0xffffffff, t4, t5);
+ TESTINST5l("blezl", 11, 0x256, t5, t6);
+ TESTINST5l("blezl", 12, 0x55, t6, t7);
+ TESTINST5l("blezl", 13, 0xfff, s0, s1);
+ TESTINST5l("blezl", 14, -1, v0, t9);
+ TESTINST5l("blezl", 15, -1, t9, t8);
+
+ printf("BGEZALL\n");
+ TESTINST6l("bgezall", 0, 0, v0, v1);
+ TESTINST6l("bgezall", 1, 1, v1, a0);
+ TESTINST6l("bgezall", 2, 0xffffffff, a0, a1);
+ TESTINST6l("bgezall", 3, 0xffffffff, a1, a2);
+ TESTINST6l("bgezall", 4, 0xfffffffe, a2, t0);
+ TESTINST6l("bgezall", 5, 0xffffffff, a3, t0);
+ TESTINST6l("bgezall", 6, 0x5, t0, t1);
+ TESTINST6l("bgezall", 7, -3, t1, t2);
+ TESTINST6l("bgezall", 8, 125, t2, t3);
+ TESTINST6l("bgezall", 9, 0x80000000, t3, t4);
+ TESTINST6l("bgezall", 10, 0xffffffff, t4, t5);
+ TESTINST6l("bgezall", 11, 0x256, t5, t6);
+ TESTINST6l("bgezall", 12, 0x55, t6, t7);
+ TESTINST6l("bgezall", 13, 0xfff, s0, s1);
+ TESTINST6l("bgezall", 14, -1, v0, t9);
+ TESTINST6l("bgezall", 15, -1, t9, t8);
+
+ printf("BLTZL\n");
+ TESTINST5l("bltzl", 0, 0, v0, v1);
+ TESTINST5l("bltzl", 1, 1, v1, a0);
+ TESTINST5l("bltzl", 2, 0xffffffff, a0, a1);
+ TESTINST5l("bltzl", 3, 0xffffffff, a1, a2);
+ TESTINST5l("bltzl", 4, 0xfffffffe, a2, t0);
+ TESTINST5l("bltzl", 5, 0xffffffff, a3, t0);
+ TESTINST5l("bltzl", 6, 0x5, t0, t1);
+ TESTINST5l("bltzl", 7, -3, t1, t2);
+ TESTINST5l("bltzl", 8, 125, t2, t3);
+ TESTINST5l("bltzl", 9, 0x80000000, t3, t4);
+ TESTINST5l("bltzl", 10, 0xffffffff, t4, t5);
+ TESTINST5l("bltzl", 11, 0x256, t5, t6);
+ TESTINST5l("bltzl", 12, 0x55, t6, t7);
+ TESTINST5l("bltzl", 13, 0xfff, s0, s1);
+ TESTINST5l("bltzl", 14, -1, v0, t9);
+ TESTINST5l("bltzl", 15, -1, t9, t8);
+
+ printf("BNEL\n");
+ TESTINST4l("bnel", 0, 0, 1, v0, v1, a0);
+ TESTINST4l("bnel", 1, 1, 1, v1, a0, a1);
+ TESTINST4l("bnel", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
+ TESTINST4l("bnel", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
+ TESTINST4l("bnel", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
+ TESTINST4l("bnel", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
+ TESTINST4l("bnel", 6, 0x5, 0x5, t0, t1, t2);
+ TESTINST4l("bnel", 7, -3, -4, t1, t2, t3);
+ TESTINST4l("bnel", 8, 125, 125, t2, t3, t4);
+ TESTINST4l("bnel", 9, 0x80000000, 0x80000000, t3, t4, t5);
+ TESTINST4l("bnel", 10, 0xffffffff, 0x80000000, t4, t5, t6);
+ TESTINST4l("bnel", 11, 0x256, 0x256, t5, t6, t7);
+ TESTINST4l("bnel", 12, 0x55, 0x55, t6, t7, s0);
+ TESTINST4l("bnel", 13, 0xfff, 0xdd, s0, s1, s2);
+ TESTINST4l("bnel", 14, -1, 0x5, v0, t9, t8);
+ TESTINST4l("bnel", 15, -1, -1, t9, t8, a3);
+
+ printf("j, jal, jr \n");
+ TESTINST3j(0, v0);
+ TESTINST3j(1, v1);
+ TESTINST3j(2, a0);
+ TESTINST3j(3, a1);
+ TESTINST3j(4, a2);
+ TESTINST3j(5, a3);
+ TESTINST3j(6, a0);
+ TESTINST3j(7, t1);
+ TESTINST3j(8, t2);
+ TESTINST3j(9, t3);
+ TESTINST3j(10, t4);
+ TESTINST3j(11, t5);
+ TESTINST3j(12, t6);
+ TESTINST3j(13, t7);
+ TESTINST3j(14, s0);
+ TESTINST3j(15, s1);
+ TESTINST3j(16, s2);
+ TESTINST3j(17, s3);
+ TESTINST3j(18, s4);
+ TESTINST3j(19, s5);
+ TESTINST3j(20, s6);
+ TESTINST3j(21, s7);
+ TESTINST3j(22, t8);
+ TESTINST3j(23, t9);
+
+ printf("j, jalr, jr \n");
+ TESTINST3ja(0, v0);
+ TESTINST3ja(1, v1);
+ TESTINST3ja(2, a0);
+ TESTINST3ja(3, a1);
+ TESTINST3ja(4, a2);
+ TESTINST3ja(5, a3);
+ TESTINST3ja(6, a0);
+ TESTINST3ja(7, a3);
+ TESTINST3ja(8, t2);
+ TESTINST3ja(9, t3);
+ TESTINST3ja(10, t4);
+ TESTINST3ja(11, t5);
+ TESTINST3ja(12, t6);
+ TESTINST3ja(13, t7);
+ TESTINST3ja(14, s0);
+ TESTINST3ja(15, s1);
+ TESTINST3ja(16, s2);
+ TESTINST3ja(17, s3);
+ TESTINST3ja(18, s4);
+ TESTINST3ja(19, s5);
+ TESTINST3ja(20, s6);
+ TESTINST3ja(21, s7);
+ TESTINST3ja(22, t8);
+ TESTINST3ja(23, t9);
+
+ return 0;
+}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/mips32/branches.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/mips32/branches.stderr.exp
diff --git a/main/none/tests/mips32/branches.stdout.exp b/main/none/tests/mips32/branches.stdout.exp
new file mode 100644
index 0000000..f22933b
--- /dev/null
+++ b/main/none/tests/mips32/branches.stdout.exp
@@ -0,0 +1,431 @@
+b
+B :: 1, RSval: 0
+B :: 2, RSval: 1
+B :: 3, RSval: 2
+B :: 4, RSval: 3
+B :: 5, RSval: 4
+B :: 6, RSval: 5
+B :: 7, RSval: 6
+B :: 8, RSval: 7
+B :: 9, RSval: 8
+B :: 10, RSval: 9
+B :: 11, RSval: 10
+B :: 12, RSval: 11
+B :: 13, RSval: 12
+B :: 14, RSval: 13
+B :: 15, RSval: 14
+B :: 16, RSval: 15
+B :: 17, RSval: 16
+B :: 18, RSval: 17
+B :: 19, RSval: 18
+B :: 20, RSval: 19
+B :: 21, RSval: 20
+B :: 22, RSval: 21
+B :: 23, RSval: 22
+B :: 24, RSval: 23
+b
+B :: 3, RSval: 0
+B :: 4, RSval: 1
+B :: 5, RSval: 2
+B :: 6, RSval: 3
+B :: 7, RSval: 4
+B :: 8, RSval: 5
+B :: 9, RSval: 6
+B :: 10, RSval: 7
+B :: 11, RSval: 8
+B :: 12, RSval: 9
+B :: 13, RSval: 10
+B :: 14, RSval: 11
+B :: 15, RSval: 12
+B :: 16, RSval: 13
+B :: 17, RSval: 14
+B :: 18, RSval: 15
+B :: 19, RSval: 16
+B :: 20, RSval: 17
+B :: 21, RSval: 18
+B :: 22, RSval: 19
+B :: 23, RSval: 20
+B :: 24, RSval: 21
+B :: 25, RSval: 22
+B :: 26, RSval: 23
+b, bal, jr
+B BAL JR :: 6, RSval: 0
+B BAL JR :: 7, RSval: 1
+B BAL JR :: 8, RSval: 2
+B BAL JR :: 9, RSval: 3
+B BAL JR :: 10, RSval: 4
+B BAL JR :: 11, RSval: 5
+B BAL JR :: 12, RSval: 6
+B BAL JR :: 13, RSval: 7
+B BAL JR :: 14, RSval: 8
+B BAL JR :: 15, RSval: 9
+B BAL JR :: 16, RSval: 10
+B BAL JR :: 17, RSval: 11
+B BAL JR :: 18, RSval: 12
+B BAL JR :: 19, RSval: 13
+B BAL JR :: 20, RSval: 14
+B BAL JR :: 21, RSval: 15
+B BAL JR :: 22, RSval: 16
+B BAL JR :: 23, RSval: 17
+B BAL JR :: 24, RSval: 18
+B BAL JR :: 25, RSval: 19
+B BAL JR :: 26, RSval: 20
+B BAL JR :: 27, RSval: 21
+B BAL JR :: 28, RSval: 22
+B BAL JR :: 29, RSval: 23
+beq
+beq :: 6, RSval: 0, RTval: 1
+beq :: 2, RSval: 1, RTval: 1
+beq :: 3, RSval: -1, RTval: -1
+beq :: 9, RSval: -1, RTval: -2
+beq :: 10, RSval: -2, RTval: -1
+beq :: 6, RSval: -1, RTval: -1
+beq :: 7, RSval: 5, RTval: 5
+beq :: 13, RSval: -3, RTval: -4
+beq :: 9, RSval: 125, RTval: 125
+beq :: 10, RSval: -2147483648, RTval: -2147483648
+beq :: 16, RSval: -1, RTval: -2147483648
+beq :: 12, RSval: 598, RTval: 598
+beq :: 13, RSval: 85, RTval: 85
+beq :: 19, RSval: 4095, RTval: 221
+beq :: 20, RSval: -1, RTval: 5
+beq :: 16, RSval: -1, RTval: -1
+bne
+bne :: 1, RSval: 0, RTval: 1
+bne :: 7, RSval: 1, RTval: 1
+bne :: 8, RSval: -1, RTval: -1
+bne :: 4, RSval: -1, RTval: -2
+bne :: 5, RSval: -2, RTval: -1
+bne :: 11, RSval: -1, RTval: -1
+bne :: 12, RSval: 5, RTval: 5
+bne :: 8, RSval: -3, RTval: -4
+bne :: 14, RSval: 125, RTval: 125
+bne :: 15, RSval: -2147483648, RTval: -2147483648
+bne :: 11, RSval: -1, RTval: -2147483648
+bne :: 17, RSval: 598, RTval: 598
+bne :: 18, RSval: 85, RTval: 85
+bne :: 14, RSval: 4095, RTval: 221
+bne :: 15, RSval: -1, RTval: 5
+bne :: 21, RSval: -1, RTval: -1
+BEQZ
+beqz :: 1, RSval: 0
+beqz :: 7, RSval: 1
+beqz :: 8, RSval: -1
+beqz :: 9, RSval: -1
+beqz :: 10, RSval: -2
+beqz :: 11, RSval: -1
+beqz :: 12, RSval: 5
+beqz :: 13, RSval: -3
+beqz :: 14, RSval: 125
+beqz :: 15, RSval: -2147483648
+beqz :: 16, RSval: -1
+beqz :: 17, RSval: 598
+beqz :: 18, RSval: 85
+beqz :: 19, RSval: 4095
+beqz :: 20, RSval: -1
+beqz :: 21, RSval: -1
+BGEZ
+bgez :: 1, RSval: 0
+bgez :: 2, RSval: 1
+bgez :: 8, RSval: -1
+bgez :: 9, RSval: -1
+bgez :: 10, RSval: -2
+bgez :: 11, RSval: -1
+bgez :: 7, RSval: 5
+bgez :: 13, RSval: -3
+bgez :: 9, RSval: 125
+bgez :: 15, RSval: -2147483648
+bgez :: 16, RSval: -1
+bgez :: 12, RSval: 598
+bgez :: 13, RSval: 85
+bgez :: 14, RSval: 4095
+bgez :: 20, RSval: -1
+bgez :: 21, RSval: -1
+BGTZ
+bgtz :: 6, RSval: 0
+bgtz :: 2, RSval: 1
+bgtz :: 8, RSval: -1
+bgtz :: 9, RSval: -1
+bgtz :: 10, RSval: -2
+bgtz :: 11, RSval: -1
+bgtz :: 7, RSval: 5
+bgtz :: 13, RSval: -3
+bgtz :: 9, RSval: 125
+bgtz :: 15, RSval: -2147483648
+bgtz :: 16, RSval: -1
+bgtz :: 12, RSval: 598
+bgtz :: 13, RSval: 85
+bgtz :: 14, RSval: 4095
+bgtz :: 20, RSval: -1
+bgtz :: 21, RSval: -1
+BLEZ
+blez :: 1, RSval: 0
+blez :: 7, RSval: 1
+blez :: 3, RSval: -1
+blez :: 4, RSval: -1
+blez :: 5, RSval: -2
+blez :: 6, RSval: -1
+blez :: 12, RSval: 5
+blez :: 8, RSval: -3
+blez :: 14, RSval: 125
+blez :: 10, RSval: -2147483648
+blez :: 11, RSval: -1
+blez :: 17, RSval: 598
+blez :: 18, RSval: 85
+blez :: 19, RSval: 4095
+blez :: 15, RSval: -1
+blez :: 16, RSval: -1
+BLTZ
+bltz :: 6, RSval: 0
+bltz :: 7, RSval: 1
+bltz :: 3, RSval: -1
+bltz :: 4, RSval: -1
+bltz :: 5, RSval: -2
+bltz :: 6, RSval: -1
+bltz :: 12, RSval: 5
+bltz :: 8, RSval: -3
+bltz :: 14, RSval: 125
+bltz :: 10, RSval: -2147483648
+bltz :: 11, RSval: -1
+bltz :: 17, RSval: 598
+bltz :: 18, RSval: 85
+bltz :: 19, RSval: 4095
+bltz :: 15, RSval: -1
+bltz :: 16, RSval: -1
+BGEZAL
+bgezal :: 6, RSval: 0
+bgezal :: 7, RSval: 1
+bgezal :: 7, RSval: -1
+bgezal :: 8, RSval: -1
+bgezal :: 9, RSval: -2
+bgezal :: 10, RSval: -1
+bgezal :: 12, RSval: 5
+bgezal :: 12, RSval: -3
+bgezal :: 14, RSval: 125
+bgezal :: 14, RSval: -2147483648
+bgezal :: 15, RSval: -1
+bgezal :: 17, RSval: 598
+bgezal :: 18, RSval: 85
+bgezal :: 19, RSval: 4095
+bgezal :: 19, RSval: -1
+bgezal :: 20, RSval: -1
+BLTZAL
+bltzal :: 5, RSval: 0
+bltzal :: 6, RSval: 1
+bltzal :: 8, RSval: -1
+bltzal :: 9, RSval: -1
+bltzal :: 10, RSval: -2
+bltzal :: 11, RSval: -1
+bltzal :: 11, RSval: 5
+bltzal :: 13, RSval: -3
+bltzal :: 13, RSval: 125
+bltzal :: 15, RSval: -2147483648
+bltzal :: 16, RSval: -1
+bltzal :: 16, RSval: 598
+bltzal :: 17, RSval: 85
+bltzal :: 18, RSval: 4095
+bltzal :: 20, RSval: -1
+bltzal :: 21, RSval: -1
+BNEZ
+bnez :: 6, RSval: 0
+bnez :: 2, RSval: 1
+bnez :: 3, RSval: -1
+bnez :: 4, RSval: -1
+bnez :: 5, RSval: -2
+bnez :: 6, RSval: -1
+bnez :: 7, RSval: 5
+bnez :: 8, RSval: -3
+bnez :: 9, RSval: 125
+bnez :: 10, RSval: -2147483648
+bnez :: 11, RSval: -1
+bnez :: 12, RSval: 598
+bnez :: 13, RSval: 85
+bnez :: 14, RSval: 4095
+bnez :: 15, RSval: -1
+bnez :: 16, RSval: -1
+beql
+beql :: 9, RSval: 0, RTval: 1
+beql :: 2, RSval: 1, RTval: 1
+beql :: 3, RSval: -1, RTval: -1
+beql :: 12, RSval: -1, RTval: -2
+beql :: 13, RSval: -2, RTval: -1
+beql :: 6, RSval: -1, RTval: -1
+beql :: 7, RSval: 5, RTval: 5
+beql :: 16, RSval: -3, RTval: -4
+beql :: 9, RSval: 125, RTval: 125
+beql :: 10, RSval: -2147483648, RTval: -2147483648
+beql :: 19, RSval: -1, RTval: -2147483648
+beql :: 12, RSval: 598, RTval: 598
+beql :: 13, RSval: 85, RTval: 85
+beql :: 22, RSval: 4095, RTval: 221
+beql :: 23, RSval: -1, RTval: 5
+beql :: 16, RSval: -1, RTval: -1
+BGEZALL
+bgezall :: 1, RSval: 0
+bgezall :: 2, RSval: 1
+bgezall :: 11, RSval: -1
+bgezall :: 12, RSval: -1
+bgezall :: 13, RSval: -2
+bgezall :: 14, RSval: -1
+bgezall :: 7, RSval: 5
+bgezall :: 16, RSval: -3
+bgezall :: 9, RSval: 125
+bgezall :: 18, RSval: -2147483648
+bgezall :: 19, RSval: -1
+bgezall :: 12, RSval: 598
+bgezall :: 13, RSval: 85
+bgezall :: 14, RSval: 4095
+bgezall :: 23, RSval: -1
+bgezall :: 24, RSval: -1
+BGEZL
+bgezl :: 1, RSval: 0
+bgezl :: 2, RSval: 1
+bgezl :: 11, RSval: -1
+bgezl :: 12, RSval: -1
+bgezl :: 13, RSval: -2
+bgezl :: 14, RSval: -1
+bgezl :: 7, RSval: 5
+bgezl :: 16, RSval: -3
+bgezl :: 9, RSval: 125
+bgezl :: 18, RSval: -2147483648
+bgezl :: 19, RSval: -1
+bgezl :: 12, RSval: 598
+bgezl :: 13, RSval: 85
+bgezl :: 14, RSval: 4095
+bgezl :: 23, RSval: -1
+bgezl :: 24, RSval: -1
+BGTZL
+bgtzl :: 9, RSval: 0
+bgtzl :: 2, RSval: 1
+bgtzl :: 11, RSval: -1
+bgtzl :: 12, RSval: -1
+bgtzl :: 13, RSval: -2
+bgtzl :: 14, RSval: -1
+bgtzl :: 7, RSval: 5
+bgtzl :: 16, RSval: -3
+bgtzl :: 9, RSval: 125
+bgtzl :: 18, RSval: -2147483648
+bgtzl :: 19, RSval: -1
+bgtzl :: 12, RSval: 598
+bgtzl :: 13, RSval: 85
+bgtzl :: 14, RSval: 4095
+bgtzl :: 23, RSval: -1
+bgtzl :: 24, RSval: -1
+BLEZL
+blezl :: 1, RSval: 0
+blezl :: 10, RSval: 1
+blezl :: 3, RSval: -1
+blezl :: 4, RSval: -1
+blezl :: 5, RSval: -2
+blezl :: 6, RSval: -1
+blezl :: 15, RSval: 5
+blezl :: 8, RSval: -3
+blezl :: 17, RSval: 125
+blezl :: 10, RSval: -2147483648
+blezl :: 11, RSval: -1
+blezl :: 20, RSval: 598
+blezl :: 21, RSval: 85
+blezl :: 22, RSval: 4095
+blezl :: 15, RSval: -1
+blezl :: 16, RSval: -1
+BGEZALL
+bgezall :: 9, RSval: 0
+bgezall :: 10, RSval: 1
+bgezall :: 10, RSval: -1
+bgezall :: 11, RSval: -1
+bgezall :: 12, RSval: -2
+bgezall :: 13, RSval: -1
+bgezall :: 15, RSval: 5
+bgezall :: 15, RSval: -3
+bgezall :: 17, RSval: 125
+bgezall :: 17, RSval: -2147483648
+bgezall :: 18, RSval: -1
+bgezall :: 20, RSval: 598
+bgezall :: 21, RSval: 85
+bgezall :: 22, RSval: 4095
+bgezall :: 22, RSval: -1
+bgezall :: 23, RSval: -1
+BLTZL
+bltzl :: 9, RSval: 0
+bltzl :: 10, RSval: 1
+bltzl :: 3, RSval: -1
+bltzl :: 4, RSval: -1
+bltzl :: 5, RSval: -2
+bltzl :: 6, RSval: -1
+bltzl :: 15, RSval: 5
+bltzl :: 8, RSval: -3
+bltzl :: 17, RSval: 125
+bltzl :: 10, RSval: -2147483648
+bltzl :: 11, RSval: -1
+bltzl :: 20, RSval: 598
+bltzl :: 21, RSval: 85
+bltzl :: 22, RSval: 4095
+bltzl :: 15, RSval: -1
+bltzl :: 16, RSval: -1
+BNEL
+bnel :: 1, RSval: 0, RTval: 1
+bnel :: 10, RSval: 1, RTval: 1
+bnel :: 11, RSval: -1, RTval: -1
+bnel :: 4, RSval: -1, RTval: -2
+bnel :: 5, RSval: -2, RTval: -1
+bnel :: 14, RSval: -1, RTval: -1
+bnel :: 15, RSval: 5, RTval: 5
+bnel :: 8, RSval: -3, RTval: -4
+bnel :: 17, RSval: 125, RTval: 125
+bnel :: 18, RSval: -2147483648, RTval: -2147483648
+bnel :: 11, RSval: -1, RTval: -2147483648
+bnel :: 20, RSval: 598, RTval: 598
+bnel :: 21, RSval: 85, RTval: 85
+bnel :: 14, RSval: 4095, RTval: 221
+bnel :: 15, RSval: -1, RTval: 5
+bnel :: 24, RSval: -1, RTval: -1
+j, jal, jr
+J JAL JR :: 6, RSval: 0
+J JAL JR :: 7, RSval: 1
+J JAL JR :: 8, RSval: 2
+J JAL JR :: 9, RSval: 3
+J JAL JR :: 10, RSval: 4
+J JAL JR :: 11, RSval: 5
+J JAL JR :: 12, RSval: 6
+J JAL JR :: 13, RSval: 7
+J JAL JR :: 14, RSval: 8
+J JAL JR :: 15, RSval: 9
+J JAL JR :: 16, RSval: 10
+J JAL JR :: 17, RSval: 11
+J JAL JR :: 18, RSval: 12
+J JAL JR :: 19, RSval: 13
+J JAL JR :: 20, RSval: 14
+J JAL JR :: 21, RSval: 15
+J JAL JR :: 22, RSval: 16
+J JAL JR :: 23, RSval: 17
+J JAL JR :: 24, RSval: 18
+J JAL JR :: 25, RSval: 19
+J JAL JR :: 26, RSval: 20
+J JAL JR :: 27, RSval: 21
+J JAL JR :: 28, RSval: 22
+J JAL JR :: 29, RSval: 23
+j, jalr, jr
+J JALR JR :: 6, RSval: 0
+J JALR JR :: 7, RSval: 1
+J JALR JR :: 8, RSval: 2
+J JALR JR :: 9, RSval: 3
+J JALR JR :: 10, RSval: 4
+J JALR JR :: 11, RSval: 5
+J JALR JR :: 12, RSval: 6
+J JALR JR :: 13, RSval: 7
+J JALR JR :: 14, RSval: 8
+J JALR JR :: 15, RSval: 9
+J JALR JR :: 16, RSval: 10
+J JALR JR :: 17, RSval: 11
+J JALR JR :: 18, RSval: 12
+J JALR JR :: 19, RSval: 13
+J JALR JR :: 20, RSval: 14
+J JALR JR :: 21, RSval: 15
+J JALR JR :: 22, RSval: 16
+J JALR JR :: 23, RSval: 17
+J JALR JR :: 24, RSval: 18
+J JALR JR :: 25, RSval: 19
+J JALR JR :: 26, RSval: 20
+J JALR JR :: 27, RSval: 21
+J JALR JR :: 28, RSval: 22
+J JALR JR :: 29, RSval: 23
diff --git a/main/none/tests/mips32/branches.vgtest b/main/none/tests/mips32/branches.vgtest
new file mode 100644
index 0000000..24b9486
--- /dev/null
+++ b/main/none/tests/mips32/branches.vgtest
@@ -0,0 +1,2 @@
+prog: branches
+vgopts: -q
diff --git a/main/none/tests/mips32/filter_stderr b/main/none/tests/mips32/filter_stderr
new file mode 100755
index 0000000..616ce05
--- /dev/null
+++ b/main/none/tests/mips32/filter_stderr
@@ -0,0 +1,4 @@
+#! /bin/sh
+
+../filter_stderr
+
diff --git a/main/none/tests/mips32/round.c b/main/none/tests/mips32/round.c
new file mode 100644
index 0000000..270ea6d
--- /dev/null
+++ b/main/none/tests/mips32/round.c
@@ -0,0 +1,267 @@
+#include <stdio.h>
+
+typedef enum {
+ CEILWS=0, CEILWD,
+ FLOORWS, FLOORWD,
+ ROUNDWS, ROUNDWD,
+ TRUNCWS, TRUNCWD
+} flt_dir_op_t;
+
+typedef enum {
+ CVTDS, CVTDW,
+ CVTSD, CVTSW,
+ CVTWS, CVTWD
+} flt_round_op_t;
+
+typedef enum {
+ TO_NEAREST=0, TO_ZERO, TO_PLUS_INFINITY, TO_MINUS_INFINITY } round_mode_t;
+char *round_mode_name[] = { "near", "zero", "+inf", "-inf" };
+
+
+const char *flt_dir_op_names[] = {
+ "ceil.w.s", "ceil.w.d",
+ "floor.w.s", "floor.w.d",
+ "round.w.s", "round.w.d",
+ "trunc.w.s", "trunc.w.d"
+};
+
+const char *flt_round_op_names[] = {
+ "cvt.d.s", "cvt.d.w",
+ "cvt.s.d", "cvt.s.w",
+ "cvt.w.s", "cvt.w.d"
+};
+
+const double fs_d[] = {
+ 0, 456.2489562, 3, -1,
+ 1384.6, -7.2945676, 1000000000, -5786.47,
+ 1752, 0.0024575, 0.00000001, -248562.76,
+ -45786.476, 456.2489562, 34.00046, 45786.476,
+ 1752065, 107, -45667.24, -7.2945676,
+ -347856.475, 356047.56, -1.0, 23.04,
+};
+
+const float fs_f[] = {
+ 0, 456.2489562, 3, -1,
+ 1384.6, -7.2945676, 1000000000, -5786.47,
+ 1752, 0.0024575, 0.00000001, -248562.76,
+ -45786.476, 456.2489562, 34.00046, 45786.476,
+ 1752065, 107, -45667.24, -7.2945676,
+ -347856.475, 356047.56, -1.0, 23.04,
+};
+
+const int fs_w[] = {
+ 0, 456, 3, -1,
+ 0xffffffff, 356, 1000000000, -5786,
+ 1752, 24575, 10, -248562,
+ -45786, 456, 34, 45786,
+ 1752065, 107, -45667, -7,
+ -347856, 0x80000000, 0xFFFFFFF, 23,
+};
+
+#define BINOP(op) \
+ __asm__ volatile( \
+ op" %0, %1, %2\n\t" \
+ : "=f"(fd) : "f"(f) , "f"(fB));
+
+#define UNOPdd(op) \
+ fd_d = 0; \
+ __asm__ volatile( \
+ op" %0, %1\n\t" \
+ : "=f"(fd_d) : "f"(fs_d[i]));
+
+#define UNOPff(op) \
+ fd_f = 0; \
+ __asm__ volatile( \
+ op" %0, %1\n\t" \
+ : "=f"(fd_f) : "f"(fs_f[i]));
+
+#define UNOPfd(op) \
+ fd_d = 0; \
+ __asm__ volatile( \
+ op" %0, %1\n\t" \
+ : "=f"(fd_d) : "f"(fs_f[i]));
+
+#define UNOPdf(op) \
+ fd_f = 0; \
+ __asm__ volatile( \
+ op" %0, %1\n\t" \
+ : "=f"(fd_f) : "f"(fs_d[i]));
+
+#define UNOPfw(op) \
+ fd_w = 0; \
+ __asm__ volatile( \
+ op" $f0, %1\n\t" \
+ "mfc1 %0, $f0\n\t" \
+ : "=r"(fd_w) : "f"(fs_f[i]) \
+ : "$f0");
+
+#define UNOPdw(op) \
+ fd_w = 0; \
+ __asm__ volatile( \
+ op" $f0, %1\n\t" \
+ "mfc1 %0, $f0\n\t" \
+ : "=r"(fd_w) : "f"(fs_d[i]) \
+ : "$f0");
+
+#define UNOPwd(op) \
+ fd_d = 0; \
+ __asm__ volatile( \
+ "mtc1 %1, $f0\n\t" \
+ op" %0, $f0\n\t" \
+ : "=f"(fd_d) : "r"(fs_w[i]) \
+ : "$f0", "$f1");
+
+#define UNOPwf(op) \
+ fd_f = 0; \
+ __asm__ volatile( \
+ "mtc1 %1, $f0\n\t" \
+ op" %0, $f0\n\t" \
+ : "=f"(fd_f) : "r"(fs_w[i]) \
+ : "$f0");
+
+void set_rounding_mode(round_mode_t mode)
+{
+ switch(mode) {
+ case TO_NEAREST:
+ __asm__ volatile("cfc1 $t0, $31\n\t"
+ "srl $t0, 2\n\t"
+ "sll $t0, 2\n\t"
+ "ctc1 $t0, $31\n\t");
+
+ break;
+ case TO_ZERO:
+ __asm__ volatile("cfc1 $t0, $31\n\t"
+ "srl $t0, 2\n\t"
+ "sll $t0, 2\n\t"
+ "addiu $t0, 1\n\t"
+ "ctc1 $t0, $31\n\t");
+ break;
+ case TO_PLUS_INFINITY:
+ __asm__ volatile("cfc1 $t0, $31\n\t"
+ "srl $t0, 2\n\t"
+ "sll $t0, 2\n\t"
+ "addiu $t0, 2\n\t"
+ "ctc1 $t0, $31\n\t");
+ break;
+ case TO_MINUS_INFINITY:
+ __asm__ volatile("cfc1 $t0, $31\n\t"
+ "srl $t0, 2\n\t"
+ "sll $t0, 2\n\t"
+ "addiu $t0, 3\n\t"
+ "ctc1 $t0, $31\n\t");
+ break;
+ }
+}
+
+int directedRoundingMode(flt_dir_op_t op) {
+ int fd_w = 0;
+ int i;
+ for (i = 0; i < 24; i++) {
+ switch(op) {
+ case CEILWS:
+ UNOPfw("ceil.w.s");
+ printf("%s %d %f\n", flt_dir_op_names[op], fd_w, fs_f[i]);
+ break;
+ case CEILWD:
+ UNOPdw("ceil.w.d");
+ printf("%s %d %lf\n", flt_dir_op_names[op], fd_w, fs_d[i]);
+ break;
+ case FLOORWS:
+ UNOPfw("floor.w.s");
+ printf("%s %d %f\n", flt_dir_op_names[op], fd_w, fs_f[i]);
+ break;
+ case FLOORWD:
+ UNOPdw("floor.w.d");
+ printf("%s %d %lf\n", flt_dir_op_names[op], fd_w, fs_d[i]);
+ break;
+ case ROUNDWS:
+ UNOPfw("round.w.s");
+ printf("%s %d %f\n", flt_dir_op_names[op], fd_w, fs_f[i]);
+ break;
+ case ROUNDWD:
+ UNOPdw("round.w.d");
+ printf("%s %d %lf\n", flt_dir_op_names[op], fd_w, fs_d[i]);
+ break;
+ case TRUNCWS:
+ UNOPfw("trunc.w.s");
+ printf("%s %d %f\n", flt_dir_op_names[op], fd_w, fs_f[i]);
+ break;
+ case TRUNCWD:
+ UNOPdw("trunc.w.d");
+ printf("%s %d %lf\n", flt_dir_op_names[op], fd_w, fs_d[i]);
+ break;
+ default:
+ printf("error\n");
+ break;
+ }
+ }
+ return 0;
+}
+
+int FCSRRoundingMode(flt_round_op_t op1)
+{
+ double fd_d = 0;
+ float fd_f = 0;
+ int fd_w = 0;
+ int i;
+ round_mode_t rm;
+ for (rm = TO_NEAREST; rm <= TO_MINUS_INFINITY; rm ++)
+ {
+ set_rounding_mode(rm);
+ printf("roundig mode: %s\n", round_mode_name[rm]);
+ for (i = 0; i < 24; i++)
+ {
+ set_rounding_mode(rm);
+ switch(op1) {
+ case CVTDS:
+ UNOPfd("cvt.d.s");
+ printf("%s %lf %lf\n", flt_round_op_names[op1], fd_d, fs_f[i]);
+ break;
+ case CVTDW:
+ UNOPwd("cvt.d.w");
+ printf("%s %lf %d\n", flt_round_op_names[op1], fd_d, fs_w[i]);
+ break;
+ case CVTSD:
+ UNOPdf("cvt.s.d");
+ printf("%s %f %lf\n", flt_round_op_names[op1], fd_f, fs_d[i]);
+ break;
+ case CVTSW:
+ UNOPwf("cvt.s.w");
+ printf("%s %f %d\n", flt_round_op_names[op1], fd_f, fs_w[i]);
+ break;
+ case CVTWS:
+ UNOPfw("cvt.w.s");
+ printf("%s %d %f\n", flt_round_op_names[op1], fd_w, fs_f[i]);
+ break;
+ case CVTWD:
+ UNOPdw("cvt.w.d");
+ printf("%s %d %lf\n", flt_round_op_names[op1], fd_w, fs_d[i]);
+ break;
+ default:
+ printf("error\n");
+ break;
+ }
+ }
+ }
+ return 0;
+}
+
+int main()
+{
+ flt_dir_op_t op;
+ flt_round_op_t op1;
+
+ printf("-------------------------- %s --------------------------\n",
+ "test FPU Conversion Operations Using a Directed Rounding Mode");
+ for (op = CEILWS; op <= TRUNCWD; op++) {
+ directedRoundingMode(op);
+ }
+
+ printf("-------------------------- %s --------------------------\n",
+ "test FPU Conversion Operations Using the FCSR Rounding Mode");
+ for (op1 = CVTDS; op1 <= CVTWD; op1++) {
+ FCSRRoundingMode(op1);
+ }
+ return 0;
+}
+
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/mips32/round.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/mips32/round.stderr.exp
diff --git a/main/none/tests/mips32/round.stdout.exp b/main/none/tests/mips32/round.stdout.exp
new file mode 100644
index 0000000..0a3d655
--- /dev/null
+++ b/main/none/tests/mips32/round.stdout.exp
@@ -0,0 +1,794 @@
+-------------------------- test FPU Conversion Operations Using a Directed Rounding Mode --------------------------
+ceil.w.s 0 0.000000
+ceil.w.s 457 456.248962
+ceil.w.s 3 3.000000
+ceil.w.s -1 -1.000000
+ceil.w.s 1385 1384.599976
+ceil.w.s -7 -7.294568
+ceil.w.s 1000000000 1000000000.000000
+ceil.w.s -5786 -5786.470215
+ceil.w.s 1752 1752.000000
+ceil.w.s 1 0.002457
+ceil.w.s 1 0.000000
+ceil.w.s -248562 -248562.765625
+ceil.w.s -45786 -45786.476562
+ceil.w.s 457 456.248962
+ceil.w.s 35 34.000462
+ceil.w.s 45787 45786.476562
+ceil.w.s 1752065 1752065.000000
+ceil.w.s 107 107.000000
+ceil.w.s -45667 -45667.238281
+ceil.w.s -7 -7.294568
+ceil.w.s -347856 -347856.468750
+ceil.w.s 356048 356047.562500
+ceil.w.s -1 -1.000000
+ceil.w.s 24 23.040001
+ceil.w.d 0 0.000000
+ceil.w.d 457 456.248956
+ceil.w.d 3 3.000000
+ceil.w.d -1 -1.000000
+ceil.w.d 1385 1384.600000
+ceil.w.d -7 -7.294568
+ceil.w.d 1000000000 1000000000.000000
+ceil.w.d -5786 -5786.470000
+ceil.w.d 1752 1752.000000
+ceil.w.d 1 0.002458
+ceil.w.d 1 0.000000
+ceil.w.d -248562 -248562.760000
+ceil.w.d -45786 -45786.476000
+ceil.w.d 457 456.248956
+ceil.w.d 35 34.000460
+ceil.w.d 45787 45786.476000
+ceil.w.d 1752065 1752065.000000
+ceil.w.d 107 107.000000
+ceil.w.d -45667 -45667.240000
+ceil.w.d -7 -7.294568
+ceil.w.d -347856 -347856.475000
+ceil.w.d 356048 356047.560000
+ceil.w.d -1 -1.000000
+ceil.w.d 24 23.040000
+floor.w.s 0 0.000000
+floor.w.s 456 456.248962
+floor.w.s 3 3.000000
+floor.w.s -1 -1.000000
+floor.w.s 1384 1384.599976
+floor.w.s -8 -7.294568
+floor.w.s 1000000000 1000000000.000000
+floor.w.s -5787 -5786.470215
+floor.w.s 1752 1752.000000
+floor.w.s 0 0.002457
+floor.w.s 0 0.000000
+floor.w.s -248563 -248562.765625
+floor.w.s -45787 -45786.476562
+floor.w.s 456 456.248962
+floor.w.s 34 34.000462
+floor.w.s 45786 45786.476562
+floor.w.s 1752065 1752065.000000
+floor.w.s 107 107.000000
+floor.w.s -45668 -45667.238281
+floor.w.s -8 -7.294568
+floor.w.s -347857 -347856.468750
+floor.w.s 356047 356047.562500
+floor.w.s -1 -1.000000
+floor.w.s 23 23.040001
+floor.w.d 0 0.000000
+floor.w.d 456 456.248956
+floor.w.d 3 3.000000
+floor.w.d -1 -1.000000
+floor.w.d 1384 1384.600000
+floor.w.d -8 -7.294568
+floor.w.d 1000000000 1000000000.000000
+floor.w.d -5787 -5786.470000
+floor.w.d 1752 1752.000000
+floor.w.d 0 0.002458
+floor.w.d 0 0.000000
+floor.w.d -248563 -248562.760000
+floor.w.d -45787 -45786.476000
+floor.w.d 456 456.248956
+floor.w.d 34 34.000460
+floor.w.d 45786 45786.476000
+floor.w.d 1752065 1752065.000000
+floor.w.d 107 107.000000
+floor.w.d -45668 -45667.240000
+floor.w.d -8 -7.294568
+floor.w.d -347857 -347856.475000
+floor.w.d 356047 356047.560000
+floor.w.d -1 -1.000000
+floor.w.d 23 23.040000
+round.w.s 0 0.000000
+round.w.s 456 456.248962
+round.w.s 3 3.000000
+round.w.s -1 -1.000000
+round.w.s 1385 1384.599976
+round.w.s -7 -7.294568
+round.w.s 1000000000 1000000000.000000
+round.w.s -5786 -5786.470215
+round.w.s 1752 1752.000000
+round.w.s 0 0.002457
+round.w.s 0 0.000000
+round.w.s -248563 -248562.765625
+round.w.s -45786 -45786.476562
+round.w.s 456 456.248962
+round.w.s 34 34.000462
+round.w.s 45786 45786.476562
+round.w.s 1752065 1752065.000000
+round.w.s 107 107.000000
+round.w.s -45667 -45667.238281
+round.w.s -7 -7.294568
+round.w.s -347856 -347856.468750
+round.w.s 356048 356047.562500
+round.w.s -1 -1.000000
+round.w.s 23 23.040001
+round.w.d 0 0.000000
+round.w.d 456 456.248956
+round.w.d 3 3.000000
+round.w.d -1 -1.000000
+round.w.d 1385 1384.600000
+round.w.d -7 -7.294568
+round.w.d 1000000000 1000000000.000000
+round.w.d -5786 -5786.470000
+round.w.d 1752 1752.000000
+round.w.d 0 0.002458
+round.w.d 0 0.000000
+round.w.d -248563 -248562.760000
+round.w.d -45786 -45786.476000
+round.w.d 456 456.248956
+round.w.d 34 34.000460
+round.w.d 45786 45786.476000
+round.w.d 1752065 1752065.000000
+round.w.d 107 107.000000
+round.w.d -45667 -45667.240000
+round.w.d -7 -7.294568
+round.w.d -347856 -347856.475000
+round.w.d 356048 356047.560000
+round.w.d -1 -1.000000
+round.w.d 23 23.040000
+trunc.w.s 0 0.000000
+trunc.w.s 456 456.248962
+trunc.w.s 3 3.000000
+trunc.w.s -1 -1.000000
+trunc.w.s 1384 1384.599976
+trunc.w.s -7 -7.294568
+trunc.w.s 1000000000 1000000000.000000
+trunc.w.s -5786 -5786.470215
+trunc.w.s 1752 1752.000000
+trunc.w.s 0 0.002457
+trunc.w.s 0 0.000000
+trunc.w.s -248562 -248562.765625
+trunc.w.s -45786 -45786.476562
+trunc.w.s 456 456.248962
+trunc.w.s 34 34.000462
+trunc.w.s 45786 45786.476562
+trunc.w.s 1752065 1752065.000000
+trunc.w.s 107 107.000000
+trunc.w.s -45667 -45667.238281
+trunc.w.s -7 -7.294568
+trunc.w.s -347856 -347856.468750
+trunc.w.s 356047 356047.562500
+trunc.w.s -1 -1.000000
+trunc.w.s 23 23.040001
+trunc.w.d 0 0.000000
+trunc.w.d 456 456.248956
+trunc.w.d 3 3.000000
+trunc.w.d -1 -1.000000
+trunc.w.d 1384 1384.600000
+trunc.w.d -7 -7.294568
+trunc.w.d 1000000000 1000000000.000000
+trunc.w.d -5786 -5786.470000
+trunc.w.d 1752 1752.000000
+trunc.w.d 0 0.002458
+trunc.w.d 0 0.000000
+trunc.w.d -248562 -248562.760000
+trunc.w.d -45786 -45786.476000
+trunc.w.d 456 456.248956
+trunc.w.d 34 34.000460
+trunc.w.d 45786 45786.476000
+trunc.w.d 1752065 1752065.000000
+trunc.w.d 107 107.000000
+trunc.w.d -45667 -45667.240000
+trunc.w.d -7 -7.294568
+trunc.w.d -347856 -347856.475000
+trunc.w.d 356047 356047.560000
+trunc.w.d -1 -1.000000
+trunc.w.d 23 23.040000
+-------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode --------------------------
+roundig mode: near
+cvt.d.s 0.000000 0.000000
+cvt.d.s 456.248962 456.248962
+cvt.d.s 3.000000 3.000000
+cvt.d.s -1.000000 -1.000000
+cvt.d.s 1384.599976 1384.599976
+cvt.d.s -7.294568 -7.294568
+cvt.d.s 1000000000.000000 1000000000.000000
+cvt.d.s -5786.470215 -5786.470215
+cvt.d.s 1752.000000 1752.000000
+cvt.d.s 0.002457 0.002457
+cvt.d.s 0.000000 0.000000
+cvt.d.s -248562.765625 -248562.765625
+cvt.d.s -45786.476562 -45786.476562
+cvt.d.s 456.248962 456.248962
+cvt.d.s 34.000462 34.000462
+cvt.d.s 45786.476562 45786.476562
+cvt.d.s 1752065.000000 1752065.000000
+cvt.d.s 107.000000 107.000000
+cvt.d.s -45667.238281 -45667.238281
+cvt.d.s -7.294568 -7.294568
+cvt.d.s -347856.468750 -347856.468750
+cvt.d.s 356047.562500 356047.562500
+cvt.d.s -1.000000 -1.000000
+cvt.d.s 23.040001 23.040001
+roundig mode: zero
+cvt.d.s 0.000000 0.000000
+cvt.d.s 456.248962 456.248962
+cvt.d.s 3.000000 3.000000
+cvt.d.s -1.000000 -1.000000
+cvt.d.s 1384.599976 1384.599976
+cvt.d.s -7.294568 -7.294568
+cvt.d.s 1000000000.000000 1000000000.000000
+cvt.d.s -5786.470215 -5786.470215
+cvt.d.s 1752.000000 1752.000000
+cvt.d.s 0.002457 0.002457
+cvt.d.s 0.000000 0.000000
+cvt.d.s -248562.765625 -248562.765625
+cvt.d.s -45786.476562 -45786.476562
+cvt.d.s 456.248962 456.248962
+cvt.d.s 34.000462 34.000462
+cvt.d.s 45786.476562 45786.476562
+cvt.d.s 1752065.000000 1752065.000000
+cvt.d.s 107.000000 107.000000
+cvt.d.s -45667.238281 -45667.238281
+cvt.d.s -7.294568 -7.294568
+cvt.d.s -347856.468750 -347856.468750
+cvt.d.s 356047.562500 356047.562500
+cvt.d.s -1.000000 -1.000000
+cvt.d.s 23.040001 23.040001
+roundig mode: +inf
+cvt.d.s 0.000000 0.000000
+cvt.d.s 456.248962 456.248962
+cvt.d.s 3.000000 3.000000
+cvt.d.s -1.000000 -1.000000
+cvt.d.s 1384.599976 1384.599976
+cvt.d.s -7.294568 -7.294568
+cvt.d.s 1000000000.000000 1000000000.000000
+cvt.d.s -5786.470215 -5786.470215
+cvt.d.s 1752.000000 1752.000000
+cvt.d.s 0.002457 0.002457
+cvt.d.s 0.000000 0.000000
+cvt.d.s -248562.765625 -248562.765625
+cvt.d.s -45786.476562 -45786.476562
+cvt.d.s 456.248962 456.248962
+cvt.d.s 34.000462 34.000462
+cvt.d.s 45786.476562 45786.476562
+cvt.d.s 1752065.000000 1752065.000000
+cvt.d.s 107.000000 107.000000
+cvt.d.s -45667.238281 -45667.238281
+cvt.d.s -7.294568 -7.294568
+cvt.d.s -347856.468750 -347856.468750
+cvt.d.s 356047.562500 356047.562500
+cvt.d.s -1.000000 -1.000000
+cvt.d.s 23.040001 23.040001
+roundig mode: -inf
+cvt.d.s 0.000000 0.000000
+cvt.d.s 456.248962 456.248962
+cvt.d.s 3.000000 3.000000
+cvt.d.s -1.000000 -1.000000
+cvt.d.s 1384.599976 1384.599976
+cvt.d.s -7.294568 -7.294568
+cvt.d.s 1000000000.000000 1000000000.000000
+cvt.d.s -5786.470215 -5786.470215
+cvt.d.s 1752.000000 1752.000000
+cvt.d.s 0.002457 0.002457
+cvt.d.s 0.000000 0.000000
+cvt.d.s -248562.765625 -248562.765625
+cvt.d.s -45786.476562 -45786.476562
+cvt.d.s 456.248962 456.248962
+cvt.d.s 34.000462 34.000462
+cvt.d.s 45786.476562 45786.476562
+cvt.d.s 1752065.000000 1752065.000000
+cvt.d.s 107.000000 107.000000
+cvt.d.s -45667.238281 -45667.238281
+cvt.d.s -7.294568 -7.294568
+cvt.d.s -347856.468750 -347856.468750
+cvt.d.s 356047.562500 356047.562500
+cvt.d.s -1.000000 -1.000000
+cvt.d.s 23.040001 23.040001
+roundig mode: near
+cvt.d.w 0.000000 0
+cvt.d.w 456.000000 456
+cvt.d.w 3.000000 3
+cvt.d.w -1.000000 -1
+cvt.d.w -1.000000 -1
+cvt.d.w 356.000000 356
+cvt.d.w 1000000000.000000 1000000000
+cvt.d.w -5786.000000 -5786
+cvt.d.w 1752.000000 1752
+cvt.d.w 24575.000000 24575
+cvt.d.w 10.000000 10
+cvt.d.w -248562.000000 -248562
+cvt.d.w -45786.000000 -45786
+cvt.d.w 456.000000 456
+cvt.d.w 34.000000 34
+cvt.d.w 45786.000000 45786
+cvt.d.w 1752065.000000 1752065
+cvt.d.w 107.000000 107
+cvt.d.w -45667.000000 -45667
+cvt.d.w -7.000000 -7
+cvt.d.w -347856.000000 -347856
+cvt.d.w -2147483648.000000 -2147483648
+cvt.d.w 268435455.000000 268435455
+cvt.d.w 23.000000 23
+roundig mode: zero
+cvt.d.w 0.000000 0
+cvt.d.w 456.000000 456
+cvt.d.w 3.000000 3
+cvt.d.w -1.000000 -1
+cvt.d.w -1.000000 -1
+cvt.d.w 356.000000 356
+cvt.d.w 1000000000.000000 1000000000
+cvt.d.w -5786.000000 -5786
+cvt.d.w 1752.000000 1752
+cvt.d.w 24575.000000 24575
+cvt.d.w 10.000000 10
+cvt.d.w -248562.000000 -248562
+cvt.d.w -45786.000000 -45786
+cvt.d.w 456.000000 456
+cvt.d.w 34.000000 34
+cvt.d.w 45786.000000 45786
+cvt.d.w 1752065.000000 1752065
+cvt.d.w 107.000000 107
+cvt.d.w -45667.000000 -45667
+cvt.d.w -7.000000 -7
+cvt.d.w -347856.000000 -347856
+cvt.d.w -2147483648.000000 -2147483648
+cvt.d.w 268435455.000000 268435455
+cvt.d.w 23.000000 23
+roundig mode: +inf
+cvt.d.w 0.000000 0
+cvt.d.w 456.000000 456
+cvt.d.w 3.000000 3
+cvt.d.w -1.000000 -1
+cvt.d.w -1.000000 -1
+cvt.d.w 356.000000 356
+cvt.d.w 1000000000.000000 1000000000
+cvt.d.w -5786.000000 -5786
+cvt.d.w 1752.000000 1752
+cvt.d.w 24575.000000 24575
+cvt.d.w 10.000000 10
+cvt.d.w -248562.000000 -248562
+cvt.d.w -45786.000000 -45786
+cvt.d.w 456.000000 456
+cvt.d.w 34.000000 34
+cvt.d.w 45786.000000 45786
+cvt.d.w 1752065.000000 1752065
+cvt.d.w 107.000000 107
+cvt.d.w -45667.000000 -45667
+cvt.d.w -7.000000 -7
+cvt.d.w -347856.000000 -347856
+cvt.d.w -2147483648.000000 -2147483648
+cvt.d.w 268435455.000000 268435455
+cvt.d.w 23.000000 23
+roundig mode: -inf
+cvt.d.w 0.000000 0
+cvt.d.w 456.000000 456
+cvt.d.w 3.000000 3
+cvt.d.w -1.000000 -1
+cvt.d.w -1.000000 -1
+cvt.d.w 356.000000 356
+cvt.d.w 1000000000.000000 1000000000
+cvt.d.w -5786.000000 -5786
+cvt.d.w 1752.000000 1752
+cvt.d.w 24575.000000 24575
+cvt.d.w 10.000000 10
+cvt.d.w -248562.000000 -248562
+cvt.d.w -45786.000000 -45786
+cvt.d.w 456.000000 456
+cvt.d.w 34.000000 34
+cvt.d.w 45786.000000 45786
+cvt.d.w 1752065.000000 1752065
+cvt.d.w 107.000000 107
+cvt.d.w -45667.000000 -45667
+cvt.d.w -7.000000 -7
+cvt.d.w -347856.000000 -347856
+cvt.d.w -2147483648.000000 -2147483648
+cvt.d.w 268435455.000000 268435455
+cvt.d.w 23.000000 23
+roundig mode: near
+cvt.s.d 0.000000 0.000000
+cvt.s.d 456.248962 456.248956
+cvt.s.d 3.000000 3.000000
+cvt.s.d -1.000000 -1.000000
+cvt.s.d 1384.599976 1384.600000
+cvt.s.d -7.294568 -7.294568
+cvt.s.d 1000000000.000000 1000000000.000000
+cvt.s.d -5786.470215 -5786.470000
+cvt.s.d 1752.000000 1752.000000
+cvt.s.d 0.002457 0.002458
+cvt.s.d 0.000000 0.000000
+cvt.s.d -248562.765625 -248562.760000
+cvt.s.d -45786.476562 -45786.476000
+cvt.s.d 456.248962 456.248956
+cvt.s.d 34.000462 34.000460
+cvt.s.d 45786.476562 45786.476000
+cvt.s.d 1752065.000000 1752065.000000
+cvt.s.d 107.000000 107.000000
+cvt.s.d -45667.238281 -45667.240000
+cvt.s.d -7.294568 -7.294568
+cvt.s.d -347856.468750 -347856.475000
+cvt.s.d 356047.562500 356047.560000
+cvt.s.d -1.000000 -1.000000
+cvt.s.d 23.040001 23.040000
+roundig mode: zero
+cvt.s.d 0.000000 0.000000
+cvt.s.d 456.248932 456.248956
+cvt.s.d 3.000000 3.000000
+cvt.s.d -1.000000 -1.000000
+cvt.s.d 1384.599976 1384.600000
+cvt.s.d -7.294568 -7.294568
+cvt.s.d 1000000000.000000 1000000000.000000
+cvt.s.d -5786.469727 -5786.470000
+cvt.s.d 1752.000000 1752.000000
+cvt.s.d 0.002457 0.002458
+cvt.s.d 0.000000 0.000000
+cvt.s.d -248562.750000 -248562.760000
+cvt.s.d -45786.472656 -45786.476000
+cvt.s.d 456.248932 456.248956
+cvt.s.d 34.000458 34.000460
+cvt.s.d 45786.472656 45786.476000
+cvt.s.d 1752065.000000 1752065.000000
+cvt.s.d 107.000000 107.000000
+cvt.s.d -45667.238281 -45667.240000
+cvt.s.d -7.294568 -7.294568
+cvt.s.d -347856.468750 -347856.475000
+cvt.s.d 356047.531250 356047.560000
+cvt.s.d -1.000000 -1.000000
+cvt.s.d 23.039999 23.040000
+roundig mode: +inf
+cvt.s.d 0.000000 0.000000
+cvt.s.d 456.248962 456.248956
+cvt.s.d 3.000000 3.000000
+cvt.s.d -1.000000 -1.000000
+cvt.s.d 1384.600098 1384.600000
+cvt.s.d -7.294568 -7.294568
+cvt.s.d 1000000000.000000 1000000000.000000
+cvt.s.d -5786.469727 -5786.470000
+cvt.s.d 1752.000000 1752.000000
+cvt.s.d 0.002458 0.002458
+cvt.s.d 0.000000 0.000000
+cvt.s.d -248562.750000 -248562.760000
+cvt.s.d -45786.472656 -45786.476000
+cvt.s.d 456.248962 456.248956
+cvt.s.d 34.000462 34.000460
+cvt.s.d 45786.476562 45786.476000
+cvt.s.d 1752065.000000 1752065.000000
+cvt.s.d 107.000000 107.000000
+cvt.s.d -45667.238281 -45667.240000
+cvt.s.d -7.294568 -7.294568
+cvt.s.d -347856.468750 -347856.475000
+cvt.s.d 356047.562500 356047.560000
+cvt.s.d -1.000000 -1.000000
+cvt.s.d 23.040001 23.040000
+roundig mode: -inf
+cvt.s.d 0.000000 0.000000
+cvt.s.d 456.248932 456.248956
+cvt.s.d 3.000000 3.000000
+cvt.s.d -1.000000 -1.000000
+cvt.s.d 1384.599976 1384.600000
+cvt.s.d -7.294568 -7.294568
+cvt.s.d 1000000000.000000 1000000000.000000
+cvt.s.d -5786.470215 -5786.470000
+cvt.s.d 1752.000000 1752.000000
+cvt.s.d 0.002457 0.002458
+cvt.s.d 0.000000 0.000000
+cvt.s.d -248562.765625 -248562.760000
+cvt.s.d -45786.476562 -45786.476000
+cvt.s.d 456.248932 456.248956
+cvt.s.d 34.000458 34.000460
+cvt.s.d 45786.472656 45786.476000
+cvt.s.d 1752065.000000 1752065.000000
+cvt.s.d 107.000000 107.000000
+cvt.s.d -45667.242188 -45667.240000
+cvt.s.d -7.294568 -7.294568
+cvt.s.d -347856.500000 -347856.475000
+cvt.s.d 356047.531250 356047.560000
+cvt.s.d -1.000000 -1.000000
+cvt.s.d 23.039999 23.040000
+roundig mode: near
+cvt.s.w 0.000000 0
+cvt.s.w 456.000000 456
+cvt.s.w 3.000000 3
+cvt.s.w -1.000000 -1
+cvt.s.w -1.000000 -1
+cvt.s.w 356.000000 356
+cvt.s.w 1000000000.000000 1000000000
+cvt.s.w -5786.000000 -5786
+cvt.s.w 1752.000000 1752
+cvt.s.w 24575.000000 24575
+cvt.s.w 10.000000 10
+cvt.s.w -248562.000000 -248562
+cvt.s.w -45786.000000 -45786
+cvt.s.w 456.000000 456
+cvt.s.w 34.000000 34
+cvt.s.w 45786.000000 45786
+cvt.s.w 1752065.000000 1752065
+cvt.s.w 107.000000 107
+cvt.s.w -45667.000000 -45667
+cvt.s.w -7.000000 -7
+cvt.s.w -347856.000000 -347856
+cvt.s.w -2147483648.000000 -2147483648
+cvt.s.w 268435456.000000 268435455
+cvt.s.w 23.000000 23
+roundig mode: zero
+cvt.s.w 0.000000 0
+cvt.s.w 456.000000 456
+cvt.s.w 3.000000 3
+cvt.s.w -1.000000 -1
+cvt.s.w -1.000000 -1
+cvt.s.w 356.000000 356
+cvt.s.w 1000000000.000000 1000000000
+cvt.s.w -5786.000000 -5786
+cvt.s.w 1752.000000 1752
+cvt.s.w 24575.000000 24575
+cvt.s.w 10.000000 10
+cvt.s.w -248562.000000 -248562
+cvt.s.w -45786.000000 -45786
+cvt.s.w 456.000000 456
+cvt.s.w 34.000000 34
+cvt.s.w 45786.000000 45786
+cvt.s.w 1752065.000000 1752065
+cvt.s.w 107.000000 107
+cvt.s.w -45667.000000 -45667
+cvt.s.w -7.000000 -7
+cvt.s.w -347856.000000 -347856
+cvt.s.w -2147483648.000000 -2147483648
+cvt.s.w 268435440.000000 268435455
+cvt.s.w 23.000000 23
+roundig mode: +inf
+cvt.s.w 0.000000 0
+cvt.s.w 456.000000 456
+cvt.s.w 3.000000 3
+cvt.s.w -1.000000 -1
+cvt.s.w -1.000000 -1
+cvt.s.w 356.000000 356
+cvt.s.w 1000000000.000000 1000000000
+cvt.s.w -5786.000000 -5786
+cvt.s.w 1752.000000 1752
+cvt.s.w 24575.000000 24575
+cvt.s.w 10.000000 10
+cvt.s.w -248562.000000 -248562
+cvt.s.w -45786.000000 -45786
+cvt.s.w 456.000000 456
+cvt.s.w 34.000000 34
+cvt.s.w 45786.000000 45786
+cvt.s.w 1752065.000000 1752065
+cvt.s.w 107.000000 107
+cvt.s.w -45667.000000 -45667
+cvt.s.w -7.000000 -7
+cvt.s.w -347856.000000 -347856
+cvt.s.w -2147483648.000000 -2147483648
+cvt.s.w 268435456.000000 268435455
+cvt.s.w 23.000000 23
+roundig mode: -inf
+cvt.s.w 0.000000 0
+cvt.s.w 456.000000 456
+cvt.s.w 3.000000 3
+cvt.s.w -1.000000 -1
+cvt.s.w -1.000000 -1
+cvt.s.w 356.000000 356
+cvt.s.w 1000000000.000000 1000000000
+cvt.s.w -5786.000000 -5786
+cvt.s.w 1752.000000 1752
+cvt.s.w 24575.000000 24575
+cvt.s.w 10.000000 10
+cvt.s.w -248562.000000 -248562
+cvt.s.w -45786.000000 -45786
+cvt.s.w 456.000000 456
+cvt.s.w 34.000000 34
+cvt.s.w 45786.000000 45786
+cvt.s.w 1752065.000000 1752065
+cvt.s.w 107.000000 107
+cvt.s.w -45667.000000 -45667
+cvt.s.w -7.000000 -7
+cvt.s.w -347856.000000 -347856
+cvt.s.w -2147483648.000000 -2147483648
+cvt.s.w 268435440.000000 268435455
+cvt.s.w 23.000000 23
+roundig mode: near
+cvt.w.s 0 0.000000
+cvt.w.s 456 456.248962
+cvt.w.s 3 3.000000
+cvt.w.s -1 -1.000000
+cvt.w.s 1385 1384.599976
+cvt.w.s -7 -7.294568
+cvt.w.s 1000000000 1000000000.000000
+cvt.w.s -5786 -5786.470215
+cvt.w.s 1752 1752.000000
+cvt.w.s 0 0.002457
+cvt.w.s 0 0.000000
+cvt.w.s -248563 -248562.765625
+cvt.w.s -45786 -45786.476562
+cvt.w.s 456 456.248962
+cvt.w.s 34 34.000462
+cvt.w.s 45786 45786.476562
+cvt.w.s 1752065 1752065.000000
+cvt.w.s 107 107.000000
+cvt.w.s -45667 -45667.238281
+cvt.w.s -7 -7.294568
+cvt.w.s -347856 -347856.468750
+cvt.w.s 356048 356047.562500
+cvt.w.s -1 -1.000000
+cvt.w.s 23 23.040001
+roundig mode: zero
+cvt.w.s 0 0.000000
+cvt.w.s 456 456.248962
+cvt.w.s 3 3.000000
+cvt.w.s -1 -1.000000
+cvt.w.s 1384 1384.599976
+cvt.w.s -7 -7.294568
+cvt.w.s 1000000000 1000000000.000000
+cvt.w.s -5786 -5786.470215
+cvt.w.s 1752 1752.000000
+cvt.w.s 0 0.002457
+cvt.w.s 0 0.000000
+cvt.w.s -248562 -248562.765625
+cvt.w.s -45786 -45786.476562
+cvt.w.s 456 456.248962
+cvt.w.s 34 34.000462
+cvt.w.s 45786 45786.476562
+cvt.w.s 1752065 1752065.000000
+cvt.w.s 107 107.000000
+cvt.w.s -45667 -45667.238281
+cvt.w.s -7 -7.294568
+cvt.w.s -347856 -347856.468750
+cvt.w.s 356047 356047.562500
+cvt.w.s -1 -1.000000
+cvt.w.s 23 23.040001
+roundig mode: +inf
+cvt.w.s 0 0.000000
+cvt.w.s 457 456.248962
+cvt.w.s 3 3.000000
+cvt.w.s -1 -1.000000
+cvt.w.s 1385 1384.599976
+cvt.w.s -7 -7.294568
+cvt.w.s 1000000000 1000000000.000000
+cvt.w.s -5786 -5786.470215
+cvt.w.s 1752 1752.000000
+cvt.w.s 1 0.002457
+cvt.w.s 1 0.000000
+cvt.w.s -248562 -248562.765625
+cvt.w.s -45786 -45786.476562
+cvt.w.s 457 456.248962
+cvt.w.s 35 34.000462
+cvt.w.s 45787 45786.476562
+cvt.w.s 1752065 1752065.000000
+cvt.w.s 107 107.000000
+cvt.w.s -45667 -45667.238281
+cvt.w.s -7 -7.294568
+cvt.w.s -347856 -347856.468750
+cvt.w.s 356048 356047.562500
+cvt.w.s -1 -1.000000
+cvt.w.s 24 23.040001
+roundig mode: -inf
+cvt.w.s 0 0.000000
+cvt.w.s 456 456.248962
+cvt.w.s 3 3.000000
+cvt.w.s -1 -1.000000
+cvt.w.s 1384 1384.599976
+cvt.w.s -8 -7.294568
+cvt.w.s 1000000000 1000000000.000000
+cvt.w.s -5787 -5786.470215
+cvt.w.s 1752 1752.000000
+cvt.w.s 0 0.002457
+cvt.w.s 0 0.000000
+cvt.w.s -248563 -248562.765625
+cvt.w.s -45787 -45786.476562
+cvt.w.s 456 456.248962
+cvt.w.s 34 34.000462
+cvt.w.s 45786 45786.476562
+cvt.w.s 1752065 1752065.000000
+cvt.w.s 107 107.000000
+cvt.w.s -45668 -45667.238281
+cvt.w.s -8 -7.294568
+cvt.w.s -347857 -347856.468750
+cvt.w.s 356047 356047.562500
+cvt.w.s -1 -1.000000
+cvt.w.s 23 23.040001
+roundig mode: near
+cvt.w.d 0 0.000000
+cvt.w.d 456 456.248956
+cvt.w.d 3 3.000000
+cvt.w.d -1 -1.000000
+cvt.w.d 1385 1384.600000
+cvt.w.d -7 -7.294568
+cvt.w.d 1000000000 1000000000.000000
+cvt.w.d -5786 -5786.470000
+cvt.w.d 1752 1752.000000
+cvt.w.d 0 0.002458
+cvt.w.d 0 0.000000
+cvt.w.d -248563 -248562.760000
+cvt.w.d -45786 -45786.476000
+cvt.w.d 456 456.248956
+cvt.w.d 34 34.000460
+cvt.w.d 45786 45786.476000
+cvt.w.d 1752065 1752065.000000
+cvt.w.d 107 107.000000
+cvt.w.d -45667 -45667.240000
+cvt.w.d -7 -7.294568
+cvt.w.d -347856 -347856.475000
+cvt.w.d 356048 356047.560000
+cvt.w.d -1 -1.000000
+cvt.w.d 23 23.040000
+roundig mode: zero
+cvt.w.d 0 0.000000
+cvt.w.d 456 456.248956
+cvt.w.d 3 3.000000
+cvt.w.d -1 -1.000000
+cvt.w.d 1384 1384.600000
+cvt.w.d -7 -7.294568
+cvt.w.d 1000000000 1000000000.000000
+cvt.w.d -5786 -5786.470000
+cvt.w.d 1752 1752.000000
+cvt.w.d 0 0.002458
+cvt.w.d 0 0.000000
+cvt.w.d -248562 -248562.760000
+cvt.w.d -45786 -45786.476000
+cvt.w.d 456 456.248956
+cvt.w.d 34 34.000460
+cvt.w.d 45786 45786.476000
+cvt.w.d 1752065 1752065.000000
+cvt.w.d 107 107.000000
+cvt.w.d -45667 -45667.240000
+cvt.w.d -7 -7.294568
+cvt.w.d -347856 -347856.475000
+cvt.w.d 356047 356047.560000
+cvt.w.d -1 -1.000000
+cvt.w.d 23 23.040000
+roundig mode: +inf
+cvt.w.d 0 0.000000
+cvt.w.d 457 456.248956
+cvt.w.d 3 3.000000
+cvt.w.d -1 -1.000000
+cvt.w.d 1385 1384.600000
+cvt.w.d -7 -7.294568
+cvt.w.d 1000000000 1000000000.000000
+cvt.w.d -5786 -5786.470000
+cvt.w.d 1752 1752.000000
+cvt.w.d 1 0.002458
+cvt.w.d 1 0.000000
+cvt.w.d -248562 -248562.760000
+cvt.w.d -45786 -45786.476000
+cvt.w.d 457 456.248956
+cvt.w.d 35 34.000460
+cvt.w.d 45787 45786.476000
+cvt.w.d 1752065 1752065.000000
+cvt.w.d 107 107.000000
+cvt.w.d -45667 -45667.240000
+cvt.w.d -7 -7.294568
+cvt.w.d -347856 -347856.475000
+cvt.w.d 356048 356047.560000
+cvt.w.d -1 -1.000000
+cvt.w.d 24 23.040000
+roundig mode: -inf
+cvt.w.d 0 0.000000
+cvt.w.d 456 456.248956
+cvt.w.d 3 3.000000
+cvt.w.d -1 -1.000000
+cvt.w.d 1384 1384.600000
+cvt.w.d -8 -7.294568
+cvt.w.d 1000000000 1000000000.000000
+cvt.w.d -5787 -5786.470000
+cvt.w.d 1752 1752.000000
+cvt.w.d 0 0.002458
+cvt.w.d 0 0.000000
+cvt.w.d -248563 -248562.760000
+cvt.w.d -45787 -45786.476000
+cvt.w.d 456 456.248956
+cvt.w.d 34 34.000460
+cvt.w.d 45786 45786.476000
+cvt.w.d 1752065 1752065.000000
+cvt.w.d 107 107.000000
+cvt.w.d -45668 -45667.240000
+cvt.w.d -8 -7.294568
+cvt.w.d -347857 -347856.475000
+cvt.w.d 356047 356047.560000
+cvt.w.d -1 -1.000000
+cvt.w.d 23 23.040000
diff --git a/main/none/tests/mips32/round.vgtest b/main/none/tests/mips32/round.vgtest
new file mode 100644
index 0000000..d5eb00e
--- /dev/null
+++ b/main/none/tests/mips32/round.vgtest
@@ -0,0 +1,2 @@
+prog: round
+vgopts: -q
diff --git a/main/none/tests/mips32/vfp.c b/main/none/tests/mips32/vfp.c
new file mode 100644
index 0000000..b18c49c
--- /dev/null
+++ b/main/none/tests/mips32/vfp.c
@@ -0,0 +1,411 @@
+#include <stdio.h>
+
+unsigned int mem[] = {
+ 0x4095A266, 0x66666666,
+ 0xBFF00000, 0x00000000,
+ 0x3FF00000, 0x00000000,
+ 0x252a2e2b, 0x262d2d2a,
+ 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x41D26580, 0xB487E5C9,
+ 0x42026580, 0xB750E388,
+ 0x3E45798E, 0xE2308C3A,
+ 0x3FBF9ADD, 0x3746F65F
+};
+
+float fs_f[] = {
+ 0, 456.2489562, 3, -1,
+ 1384.6, -7.2945676, 1000000000, -5786.47,
+ 1752, 0.0024575, 0.00000001, -248562.76,
+ -45786.476, 456.2489562, 34.00046, 45786.476,
+ 1752065, 107, -45667.24, -7.2945676,
+ -347856.475, 356047.56, -1.0, 23.04
+};
+
+double fs_d[] = {
+ 0, 456.2489562, 3, -1,
+ 1384.6, -7.2945676, 1000000000, -5786.47,
+ 1752, 0.0024575, 0.00000001, -248562.76,
+ -45786.476, 456.2489562, 34.00046, 45786.476,
+ 1752065, 107, -45667.24, -7.2945676,
+ -347856.475, 356047.56, -1.0, 23.04
+};
+
+double mem1[] = {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0
+};
+
+float mem1f[] = {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0
+};
+// ldc1 $f0, 0($t1)
+#define TESTINSN5LOAD(instruction, RTval, offset, RT) \
+{ \
+ double out; \
+ int out1; \
+ int out2; \
+ __asm__ volatile( \
+ "move $t1, %3\n\t" \
+ "li $t0, " #RTval"\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #RT "\n\t" \
+ "mfc1 %1, $" #RT "\n\t" \
+ "mfc1 %2, $f1\n\t" \
+ : "=&f" (out), "=&r" (out1), "=&r" (out2) \
+ : "r" (mem), "r" (RTval) \
+ : "cc", "memory" \
+ ); \
+ printf("%s :: ft 0x%x%x\n", \
+ instruction, out1, out2); \
+}
+
+// lwc1 $f0, 0($t1)
+#define TESTINSN5LOADw(instruction, RTval, offset, RT) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t1, %2\n\t" \
+ "li $t0, " #RTval"\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #RT "\n\t" \
+ "mfc1 %1, $" #RT "\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (mem), "r" (RTval) \
+ : "cc", "memory" \
+ ); \
+ printf("%s :: ft 0x%x\n", \
+ instruction, out1); \
+}
+
+// lwxc1 $f0, $a3($v0)
+#define TESTINSN6LOADw(instruction, indexVal, fd, index, base) \
+{ \
+ int out; \
+ __asm__ volatile( \
+ "move $" #base ", %1\n\t" \
+ "li $" #index ", " #indexVal"\n\t" \
+ instruction "\n\t" \
+ "mfc1 %0, $" #fd "\n\t" \
+ : "=&r" (out) \
+ : "r" (mem) \
+ : "cc", "memory" \
+ ); \
+ printf("%s :: ft 0x%x\n", \
+ instruction, out); \
+}
+
+// ldxc1 $f0, $a3($v0)
+#define TESTINSN6LOADd(instruction, indexVal, fd, index, base) \
+{ \
+ int out; \
+ int out1; \
+ int out2; \
+ __asm__ volatile( \
+ "move $" #base ", %3\n\t" \
+ "li $" #index ", " #indexVal"\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #fd "\n\t" \
+ "mfc1 %1, $" #fd "\n\t" \
+ "mfc1 %2, $f1\n\t" \
+ : "=&f" (out), "=&r" (out1), "=&r" (out2) \
+ : "r" (mem) \
+ : "cc", "memory" \
+ ); \
+ printf("%s :: ft 0x%x\n", \
+ instruction, out); \
+}
+// sdc1 $f0, 0($t0)
+#define TESTINST1(offset) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $t0, %1\n\t" \
+ "move $t1, %2\n\t" \
+ "ldc1 $f0, "#offset"($t1)\n\t" \
+ "sdc1 $f0, "#offset"($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ : "=&r" (out) \
+ : "r" (mem1), "r" (fs_d) \
+ : "t1", "t0", "cc", "memory" \
+ ); \
+ printf("sdc1 $f0, 0($t0) :: out: 0x%x\n", \
+ out); \
+}
+
+// sdxc1 $f0, $t2($t0)
+#define TESTINST1a(offset) \
+{ \
+ unsigned int out; \
+ unsigned int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "move $t1, %3\n\t" \
+ "li $t2, "#offset"\n\t" \
+ "ldc1 $f0, "#offset"($t1)\n\t" \
+ "sdxc1 $f0, $t2($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ "addi $t0, $t0, 4 \n\t" \
+ "lw %1, "#offset"($t0)\n\t" \
+ : "=&r" (out), "=&r" (out1) \
+ : "r" (mem1), "r" (fs_d) \
+ : "t2", "t1", "t0", "cc", "memory" \
+ ); \
+ printf("sdc1 $f0, #t2($t0) :: out: 0x%x : out1: 0x%x\n", \
+ out, out1); \
+}
+
+// swc1 $f0, 0($t0)
+#define TESTINST2(offset) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $t0, %1\n\t" \
+ "move $t1, %2\n\t" \
+ "lwc1 $f0, "#offset"($t1)\n\t" \
+ "swc1 $f0, "#offset"($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ : "=&r" (out) \
+ : "r" (mem1f), "r" (fs_f) \
+ : "t1", "t0", "cc", "memory" \
+ ); \
+ printf("swc1 $f0, 0($t0) :: out: 0x%x\n", \
+ out); \
+}
+
+// SWXC1 $f0, $t2($t0)
+#define TESTINST2a(offset) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $t0, %1\n\t" \
+ "move $t1, %2\n\t" \
+ "li $t2, "#offset" \n\t" \
+ "lwc1 $f0, "#offset"($t1)\n\t" \
+ "swxc1 $f0, $t2($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ : "=&r" (out) \
+ : "r" (mem1f), "r" (fs_f) \
+ : "t2", "t1", "t0", "cc", "memory" \
+ ); \
+ printf("swxc1 $f0, 0($t0) :: out: 0x%x\n", \
+ out); \
+}
+void ppMem(double *mem, int len)
+{
+ int i;
+ printf("MEM1:\n");
+ for (i = 0; i < len; i=i+4)
+ {
+ printf("%lf, %lf, %lf, %lf\n", mem[i], mem[i+1], mem[i+2], mem[i+3]);
+ mem[i] = 0;
+ mem[i+1] = 0;
+ mem[i+2] = 0;
+ mem[i+3] = 0;
+ }
+}
+
+void ppMemF(float *mem, int len)
+{
+ int i;
+ printf("MEM1:\n");
+ for (i = 0; i < len; i=i+4)
+ {
+ printf("%lf, %lf, %lf, %lf\n", mem[i], mem[i+1], mem[i+2], mem[i+3]);
+ mem[i] = 0;
+ mem[i+1] = 0;
+ mem[i+2] = 0;
+ mem[i+3] = 0;
+ }
+}
+
+int main()
+{
+ printf("LDC1\n");
+ TESTINSN5LOAD("ldc1 $f0, 0($t1)", 0, 0, f0);
+ TESTINSN5LOAD("ldc1 $f0, 8($t1)", 0, 8, f0);
+ TESTINSN5LOAD("ldc1 $f0, 16($t1)", 0, 16, f0);
+ TESTINSN5LOAD("ldc1 $f0, 24($t1)", 0, 24, f0);
+ TESTINSN5LOAD("ldc1 $f0, 32($t1)", 0, 32, f0);
+ TESTINSN5LOAD("ldc1 $f0, 40($t1)", 0, 40, f0);
+ TESTINSN5LOAD("ldc1 $f0, 48($t1)", 0, 48, f0);
+ TESTINSN5LOAD("ldc1 $f0, 56($t1)", 0, 56, f0);
+ TESTINSN5LOAD("ldc1 $f0, 64($t1)", 0, 64, f0);
+ TESTINSN5LOAD("ldc1 $f0, 0($t1)", 0, 0, f0);
+ TESTINSN5LOAD("ldc1 $f0, 8($t1)", 0, 8, f0);
+ TESTINSN5LOAD("ldc1 $f0, 16($t1)", 0, 16, f0);
+ TESTINSN5LOAD("ldc1 $f0, 24($t1)", 0, 24, f0);
+ TESTINSN5LOAD("ldc1 $f0, 32($t1)", 0, 32, f0);
+ TESTINSN5LOAD("ldc1 $f0, 40($t1)", 0, 40, f0);
+ TESTINSN5LOAD("ldc1 $f0, 48($t1)", 0, 48, f0);
+ TESTINSN5LOAD("ldc1 $f0, 56($t1)", 0, 56, f0);
+ TESTINSN5LOAD("ldc1 $f0, 0($t1)", 0, 0, f0);
+ TESTINSN5LOAD("ldc1 $f0, 8($t1)", 0, 8, f0);
+ TESTINSN5LOAD("ldc1 $f0, 16($t1)", 0, 16, f0);
+ TESTINSN5LOAD("ldc1 $f0, 24($t1)", 0, 24, f0);
+ TESTINSN5LOAD("ldc1 $f0, 32($t1)", 0, 32, f0);
+ TESTINSN5LOAD("ldc1 $f0, 40($t1)", 0, 40, f0);
+ TESTINSN5LOAD("ldc1 $f0, 48($t1)", 0, 48, f0);
+ TESTINSN5LOAD("ldc1 $f0, 56($t1)", 0, 56, f0);
+ TESTINSN5LOAD("ldc1 $f0, 64($t1)", 0, 64, f0);
+ TESTINSN5LOAD("ldc1 $f0, 0($t1)", 0, 0, f0);
+
+ printf("LWC1\n");
+ TESTINSN5LOADw("lwc1 $f0, 0($t1)", 0, 0, f0);
+ TESTINSN5LOADw("lwc1 $f0, 4($t1)", 0, 4, f0);
+ TESTINSN5LOADw("lwc1 $f0, 8($t1)", 0, 8, f0);
+ TESTINSN5LOADw("lwc1 $f0, 12($t1)", 0, 12, f0);
+ TESTINSN5LOADw("lwc1 $f0, 16($t1)", 0, 16, f0);
+ TESTINSN5LOADw("lwc1 $f0, 20($t1)", 0, 20, f0);
+ TESTINSN5LOADw("lwc1 $f0, 24($t1)", 0, 24, f0);
+ TESTINSN5LOADw("lwc1 $f0, 28($t1)", 0, 28, f0);
+ TESTINSN5LOADw("lwc1 $f0, 32($t1)", 0, 32, f0);
+ TESTINSN5LOADw("lwc1 $f0, 36($t1)", 0, 36, f0);
+ TESTINSN5LOADw("lwc1 $f0, 40($t1)", 0, 40, f0);
+ TESTINSN5LOADw("lwc1 $f0, 44($t1)", 0, 44, f0);
+ TESTINSN5LOADw("lwc1 $f0, 48($t1)", 0, 48, f0);
+ TESTINSN5LOADw("lwc1 $f0, 52($t1)", 0, 52, f0);
+ TESTINSN5LOADw("lwc1 $f0, 56($t1)", 0, 56, f0);
+ TESTINSN5LOADw("lwc1 $f0, 60($t1)", 0, 60, f0);
+ TESTINSN5LOADw("lwc1 $f0, 64($t1)", 0, 64, f0);
+ TESTINSN5LOADw("lwc1 $f0, 0($t1)", 0, 0, f0);
+ TESTINSN5LOADw("lwc1 $f0, 8($t1)", 0, 8, f0);
+ TESTINSN5LOADw("lwc1 $f0, 16($t1)", 0, 16, f0);
+ TESTINSN5LOADw("lwc1 $f0, 24($t1)", 0, 24, f0);
+ TESTINSN5LOADw("lwc1 $f0, 32($t1)", 0, 32, f0);
+ TESTINSN5LOADw("lwc1 $f0, 40($t1)", 0, 40, f0);
+ TESTINSN5LOADw("lwc1 $f0, 48($t1)", 0, 48, f0);
+ TESTINSN5LOADw("lwc1 $f0, 56($t1)", 0, 56, f0);
+ TESTINSN5LOADw("lwc1 $f0, 64($t1)", 0, 64, f0);
+ TESTINSN5LOADw("lwc1 $f0, 0($t1)", 0, 0, f0);
+
+#if (__mips==32) && (__mips_isa_rev>=2)
+ printf("LWXC1\n");
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 4, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 12, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 20, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 28, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 36, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 44, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 52, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 60, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 4, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 12, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 20, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 28, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 36, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 44, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 52, f0, a3, v0);
+ TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+
+ printf("LDXC1\n");
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADd("ldxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+#endif
+
+ printf("SDC1\n");
+ TESTINST1(0);
+ TESTINST1(8);
+ TESTINST1(16);
+ TESTINST1(24);
+ TESTINST1(32);
+ TESTINST1(40);
+ TESTINST1(48);
+ TESTINST1(56);
+ TESTINST1(64);
+ ppMem(mem1, 16);
+
+#if (__mips==32) && (__mips_isa_rev>=2)
+ printf("SDXC1\n");
+ TESTINST1a(0);
+ TESTINST1a(8);
+ TESTINST1a(16);
+ TESTINST1a(24);
+ TESTINST1a(32);
+ TESTINST1a(40);
+ TESTINST1a(48);
+ TESTINST1a(56);
+ TESTINST1a(64);
+ ppMem(mem1, 16);
+#endif
+
+ printf("SWC1\n");
+ TESTINST2(0);
+ TESTINST2(8);
+ TESTINST2(16);
+ TESTINST2(24);
+ TESTINST2(32);
+ TESTINST2(40);
+ TESTINST2(48);
+ TESTINST2(56);
+ TESTINST2(64);
+ ppMemF(mem1f, 16);
+
+#if (__mips==32) && (__mips_isa_rev>=2)
+ printf("SWXC1\n");
+ TESTINST2a(0);
+ TESTINST2a(8);
+ TESTINST2a(16);
+ TESTINST2a(24);
+ TESTINST2a(32);
+ TESTINST2a(40);
+ TESTINST2a(48);
+ TESTINST2a(56);
+ TESTINST2a(64);
+ ppMemF(mem1f, 16);
+#endif
+
+ return 0;
+}
+
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/mips32/vfp.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/mips32/vfp.stderr.exp
diff --git a/main/none/tests/mips32/vfp.stdout.exp b/main/none/tests/mips32/vfp.stdout.exp
new file mode 100644
index 0000000..5e29c42
--- /dev/null
+++ b/main/none/tests/mips32/vfp.stdout.exp
@@ -0,0 +1,182 @@
+LDC1
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+LWC1
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 4($t1) :: ft 0x66666666
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 12($t1) :: ft 0x0
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 20($t1) :: ft 0x0
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 28($t1) :: ft 0x262d2d2a
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 36($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 44($t1) :: ft 0xb487e5c9
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 52($t1) :: ft 0xb750e388
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 60($t1) :: ft 0xe2308c3a
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+LWXC1
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+lwxc1 $f0, $a3($v0) :: ft 0xe2308c3a
+lwxc1 $f0, $a3($v0) :: ft 0x3fbf9add
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+LDXC1
+ldxc1 $f0, $a3($v0) :: ft 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft 0x41d26580
+ldxc1 $f0, $a3($v0) :: ft 0x42026580
+ldxc1 $f0, $a3($v0) :: ft 0x3e45798e
+ldxc1 $f0, $a3($v0) :: ft 0x3fbf9add
+ldxc1 $f0, $a3($v0) :: ft 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft 0x41d26580
+ldxc1 $f0, $a3($v0) :: ft 0x42026580
+ldxc1 $f0, $a3($v0) :: ft 0x3e45798e
+ldxc1 $f0, $a3($v0) :: ft 0x3fbf9add
+ldxc1 $f0, $a3($v0) :: ft 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft 0x41d26580
+ldxc1 $f0, $a3($v0) :: ft 0x42026580
+ldxc1 $f0, $a3($v0) :: ft 0x3e45798e
+ldxc1 $f0, $a3($v0) :: ft 0x3fbf9add
+ldxc1 $f0, $a3($v0) :: ft 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft 0xffffffff
+SDC1
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0xb97f122f
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x66666666
+sdc1 $f0, 0($t0) :: out: 0x2101d847
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x51eb851f
+sdc1 $f0, 0($t0) :: out: 0x0
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SDXC1
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0xb97f122f : out1: 0x407c83fb
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x40080000
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0xbff00000
+sdc1 $f0, #t2($t0) :: out: 0x66666666 : out1: 0x4095a266
+sdc1 $f0, #t2($t0) :: out: 0x2101d847 : out1: 0xc01d2da3
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x41cdcd65
+sdc1 $f0, #t2($t0) :: out: 0x51eb851f : out1: 0xc0b69a78
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x409b6000
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SWC1
+swc1 $f0, 0($t0) :: out: 0x0
+swc1 $f0, 0($t0) :: out: 0x40400000
+swc1 $f0, 0($t0) :: out: 0x44ad1333
+swc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swc1 $f0, 0($t0) :: out: 0x44db0000
+swc1 $f0, 0($t0) :: out: 0x322bcc77
+swc1 $f0, 0($t0) :: out: 0xc732da7a
+swc1 $f0, 0($t0) :: out: 0x42080079
+swc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+SWXC1
+swxc1 $f0, 0($t0) :: out: 0x0
+swxc1 $f0, 0($t0) :: out: 0x40400000
+swxc1 $f0, 0($t0) :: out: 0x44ad1333
+swxc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swxc1 $f0, 0($t0) :: out: 0x44db0000
+swxc1 $f0, 0($t0) :: out: 0x322bcc77
+swxc1 $f0, 0($t0) :: out: 0xc732da7a
+swxc1 $f0, 0($t0) :: out: 0x42080079
+swxc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
diff --git a/main/none/tests/mips32/vfp.stdout.exp-BE b/main/none/tests/mips32/vfp.stdout.exp-BE
new file mode 100644
index 0000000..df2d01b
--- /dev/null
+++ b/main/none/tests/mips32/vfp.stdout.exp-BE
@@ -0,0 +1,182 @@
+LDC1
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+ldc1 $f0, 8($t1) :: ft 0x0bff00000
+ldc1 $f0, 16($t1) :: ft 0x03ff00000
+ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
+ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
+ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
+ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9add
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+ldc1 $f0, 8($t1) :: ft 0x0bff00000
+ldc1 $f0, 16($t1) :: ft 0x03ff00000
+ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
+ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
+ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+ldc1 $f0, 8($t1) :: ft 0x0bff00000
+ldc1 $f0, 16($t1) :: ft 0x03ff00000
+ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
+ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
+ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
+ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9add
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+LWC1
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 4($t1) :: ft 0x66666666
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 12($t1) :: ft 0x0
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 20($t1) :: ft 0x0
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 28($t1) :: ft 0x262d2d2a
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 36($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 44($t1) :: ft 0xb487e5c9
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 52($t1) :: ft 0xb750e388
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 60($t1) :: ft 0xe2308c3a
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+LWXC1
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+lwxc1 $f0, $a3($v0) :: ft 0xe2308c3a
+lwxc1 $f0, $a3($v0) :: ft 0x3fbf9add
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+LDXC1
+ldxc1 $f0, $a3($v0) :: ft 0x66666666
+ldxc1 $f0, $a3($v0) :: ft 0x0
+ldxc1 $f0, $a3($v0) :: ft 0x0
+ldxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+ldxc1 $f0, $a3($v0) :: ft 0xb750e388
+ldxc1 $f0, $a3($v0) :: ft 0xe2308c3a
+ldxc1 $f0, $a3($v0) :: ft 0x3746f65f
+ldxc1 $f0, $a3($v0) :: ft 0x66666666
+ldxc1 $f0, $a3($v0) :: ft 0x0
+ldxc1 $f0, $a3($v0) :: ft 0x0
+ldxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+ldxc1 $f0, $a3($v0) :: ft 0xb750e388
+ldxc1 $f0, $a3($v0) :: ft 0xe2308c3a
+ldxc1 $f0, $a3($v0) :: ft 0x3746f65f
+ldxc1 $f0, $a3($v0) :: ft 0x66666666
+ldxc1 $f0, $a3($v0) :: ft 0x0
+ldxc1 $f0, $a3($v0) :: ft 0x0
+ldxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+ldxc1 $f0, $a3($v0) :: ft 0xb750e388
+ldxc1 $f0, $a3($v0) :: ft 0xe2308c3a
+ldxc1 $f0, $a3($v0) :: ft 0x3746f65f
+ldxc1 $f0, $a3($v0) :: ft 0x66666666
+ldxc1 $f0, $a3($v0) :: ft 0x0
+ldxc1 $f0, $a3($v0) :: ft 0x0
+ldxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft 0xffffffff
+SDC1
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x407c83fb
+sdc1 $f0, 0($t0) :: out: 0x40080000
+sdc1 $f0, 0($t0) :: out: 0xbff00000
+sdc1 $f0, 0($t0) :: out: 0x4095a266
+sdc1 $f0, 0($t0) :: out: 0xc01d2da3
+sdc1 $f0, 0($t0) :: out: 0x41cdcd65
+sdc1 $f0, 0($t0) :: out: 0xc0b69a78
+sdc1 $f0, 0($t0) :: out: 0x409b6000
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SDXC1
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0x407c83fb : out1: 0xb97f122f
+sdc1 $f0, #t2($t0) :: out: 0x40080000 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0xbff00000 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0x4095a266 : out1: 0x66666666
+sdc1 $f0, #t2($t0) :: out: 0xc01d2da3 : out1: 0x2101d847
+sdc1 $f0, #t2($t0) :: out: 0x41cdcd65 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0xc0b69a78 : out1: 0x51eb851f
+sdc1 $f0, #t2($t0) :: out: 0x409b6000 : out1: 0x0
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SWC1
+swc1 $f0, 0($t0) :: out: 0x0
+swc1 $f0, 0($t0) :: out: 0x40400000
+swc1 $f0, 0($t0) :: out: 0x44ad1333
+swc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swc1 $f0, 0($t0) :: out: 0x44db0000
+swc1 $f0, 0($t0) :: out: 0x322bcc77
+swc1 $f0, 0($t0) :: out: 0xc732da7a
+swc1 $f0, 0($t0) :: out: 0x42080079
+swc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+SWXC1
+swxc1 $f0, 0($t0) :: out: 0x0
+swxc1 $f0, 0($t0) :: out: 0x40400000
+swxc1 $f0, 0($t0) :: out: 0x44ad1333
+swxc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swxc1 $f0, 0($t0) :: out: 0x44db0000
+swxc1 $f0, 0($t0) :: out: 0x322bcc77
+swxc1 $f0, 0($t0) :: out: 0xc732da7a
+swxc1 $f0, 0($t0) :: out: 0x42080079
+swxc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
diff --git a/main/none/tests/mips32/vfp.stdout.exp-mips32 b/main/none/tests/mips32/vfp.stdout.exp-mips32
new file mode 100644
index 0000000..1184a05
--- /dev/null
+++ b/main/none/tests/mips32/vfp.stdout.exp-mips32
@@ -0,0 +1,86 @@
+LDC1
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+LWC1
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 4($t1) :: ft 0x66666666
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 12($t1) :: ft 0x0
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 20($t1) :: ft 0x0
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 28($t1) :: ft 0x262d2d2a
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 36($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 44($t1) :: ft 0xb487e5c9
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 52($t1) :: ft 0xb750e388
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 60($t1) :: ft 0xe2308c3a
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+SDC1
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0xb97f122f
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x66666666
+sdc1 $f0, 0($t0) :: out: 0x2101d847
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x51eb851f
+sdc1 $f0, 0($t0) :: out: 0x0
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SWC1
+swc1 $f0, 0($t0) :: out: 0x0
+swc1 $f0, 0($t0) :: out: 0x40400000
+swc1 $f0, 0($t0) :: out: 0x44ad1333
+swc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swc1 $f0, 0($t0) :: out: 0x44db0000
+swc1 $f0, 0($t0) :: out: 0x322bcc77
+swc1 $f0, 0($t0) :: out: 0xc732da7a
+swc1 $f0, 0($t0) :: out: 0x42080079
+swc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
diff --git a/main/none/tests/mips32/vfp.vgtest b/main/none/tests/mips32/vfp.vgtest
new file mode 100644
index 0000000..fd3e759
--- /dev/null
+++ b/main/none/tests/mips32/vfp.vgtest
@@ -0,0 +1,2 @@
+prog: vfp
+vgopts: -q
diff --git a/main/none/tests/mmap_fcntl_bug.c b/main/none/tests/mmap_fcntl_bug.c
index 056b89c..f49639a 100644
--- a/main/none/tests/mmap_fcntl_bug.c
+++ b/main/none/tests/mmap_fcntl_bug.c
@@ -19,6 +19,7 @@
const char *file = /* argv[1]; */
"mmap_fcntl_bug.c";
int fd, status;
+ off_t initial;
if (!file)
errx(1, "Usage: %s <normal-file>", argv[0]);
@@ -27,6 +28,13 @@
if (fd < 0)
err(1, "Opening %s", file);
+ // reproduce bug 297991: mmap interferes with fd position
+ initial = lseek(fd, 123, SEEK_SET);
+ if (123 != initial)
+ err(1, "initial off_t differs from 123 (TEST FAILED)");
+ if (lseek(fd, 0, SEEK_CUR) != 123)
+ err(1, "zero offset from initial differs from 123 (TEST FAILED)");
+
fl.l_type = F_WRLCK;
fl.l_whence = SEEK_SET;
fl.l_start = 0;
@@ -39,6 +47,8 @@
/* If under valgrind, mmap re-opens and closes file, screwing us */
if (mmap(NULL, getpagesize(), PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0) == MAP_FAILED)
err(1, "mmap of %s", file);
+ if (lseek(fd, 0, SEEK_CUR) != 123)
+ errx(1, "zero offset from initial after mmap differs from 123 (TEST FAILED)");
switch (fork()) {
case 0:
diff --git a/main/none/tests/mq.c b/main/none/tests/mq.c
index cd111c9..b2ab7bc 100644
--- a/main/none/tests/mq.c
+++ b/main/none/tests/mq.c
@@ -87,7 +87,7 @@
if (mq_setattr(mqdw, &mqa, &mqa) < 0)
{
- perror("mq_getattr");
+ perror("mq_setattr");
mq_close(mqdr);
mq_close(mqdw);
exit(1);
diff --git a/main/none/tests/nodir.stderr.exp b/main/none/tests/nodir.stderr.exp
new file mode 100644
index 0000000..d700ddb
--- /dev/null
+++ b/main/none/tests/nodir.stderr.exp
@@ -0,0 +1 @@
+valgrind: ./nodir.vgtest/foobar: Not a directory
diff --git a/main/none/tests/nodir.vgtest b/main/none/tests/nodir.vgtest
new file mode 100644
index 0000000..57f36bc
--- /dev/null
+++ b/main/none/tests/nodir.vgtest
@@ -0,0 +1 @@
+prog: nodir.vgtest/foobar
diff --git a/main/none/tests/ppc32/Makefile.am b/main/none/tests/ppc32/Makefile.am
index f43e1be..976d9f4 100644
--- a/main/none/tests/ppc32/Makefile.am
+++ b/main/none/tests/ppc32/Makefile.am
@@ -29,21 +29,32 @@
power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
- test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest
+ test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
+ test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
+ test_dfp2.stdout.exp_Without_dcffix \
+ test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \
+ test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
+ test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest
check_PROGRAMS = \
+ allexec \
bug129390-ppc32 \
bug139050-ppc32 \
ldstrev lsw jm-insns mftocrf mcrfs round test_fx test_gx \
testVMX twi tw xlc_dbl_u32 power5+_round power6_bcmp \
test_isa_2_06_part1 \
test_isa_2_06_part2 \
- test_isa_2_06_part3
+ test_isa_2_06_part3 \
+ test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5
+
AM_CFLAGS += @FLAG_M32@
AM_CXXFLAGS += @FLAG_M32@
AM_CCASFLAGS += @FLAG_M32@
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+
if HAS_ALTIVEC
ALTIVEC_FLAG = -DHAS_ALTIVEC
else
@@ -58,6 +69,14 @@
VSX_FLAG =
endif
+if HAS_DFP
+BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6
+DFP_FLAG = -DHAS_DFP
+else
+BUILD_FLAGS_DFP =
+DFP_FLAG =
+endif
+
jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \
@FLAG_M32@ $(ALTIVEC_FLAG)
@@ -73,3 +92,15 @@
test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
diff --git a/main/none/tests/ppc32/Makefile.in b/main/none/tests/ppc32/Makefile.in
new file mode 100644
index 0000000..55bc6db
--- /dev/null
+++ b/main/none/tests/ppc32/Makefile.in
@@ -0,0 +1,1134 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = allexec$(EXEEXT) bug129390-ppc32$(EXEEXT) \
+ bug139050-ppc32$(EXEEXT) ldstrev$(EXEEXT) lsw$(EXEEXT) \
+ jm-insns$(EXEEXT) mftocrf$(EXEEXT) mcrfs$(EXEEXT) \
+ round$(EXEEXT) test_fx$(EXEEXT) test_gx$(EXEEXT) \
+ testVMX$(EXEEXT) twi$(EXEEXT) tw$(EXEEXT) xlc_dbl_u32$(EXEEXT) \
+ power5+_round$(EXEEXT) power6_bcmp$(EXEEXT) \
+ test_isa_2_06_part1$(EXEEXT) test_isa_2_06_part2$(EXEEXT) \
+ test_isa_2_06_part3$(EXEEXT) test_dfp1$(EXEEXT) \
+ test_dfp2$(EXEEXT) test_dfp3$(EXEEXT) test_dfp4$(EXEEXT) \
+ test_dfp5$(EXEEXT)
+subdir = none/tests/ppc32
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+bug129390_ppc32_SOURCES = bug129390-ppc32.c
+bug129390_ppc32_OBJECTS = bug129390-ppc32.$(OBJEXT)
+bug129390_ppc32_LDADD = $(LDADD)
+bug139050_ppc32_SOURCES = bug139050-ppc32.c
+bug139050_ppc32_OBJECTS = bug139050-ppc32.$(OBJEXT)
+bug139050_ppc32_LDADD = $(LDADD)
+jm_insns_SOURCES = jm-insns.c
+jm_insns_OBJECTS = jm_insns-jm-insns.$(OBJEXT)
+jm_insns_LDADD = $(LDADD)
+jm_insns_LINK = $(CCLD) $(jm_insns_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+ldstrev_SOURCES = ldstrev.c
+ldstrev_OBJECTS = ldstrev.$(OBJEXT)
+ldstrev_LDADD = $(LDADD)
+lsw_SOURCES = lsw.c
+lsw_OBJECTS = lsw.$(OBJEXT)
+lsw_LDADD = $(LDADD)
+mcrfs_SOURCES = mcrfs.c
+mcrfs_OBJECTS = mcrfs.$(OBJEXT)
+mcrfs_LDADD = $(LDADD)
+mftocrf_SOURCES = mftocrf.c
+mftocrf_OBJECTS = mftocrf.$(OBJEXT)
+mftocrf_LDADD = $(LDADD)
+power5__round_SOURCES = power5+_round.c
+power5__round_OBJECTS = power5+_round.$(OBJEXT)
+power5__round_LDADD = $(LDADD)
+power6_bcmp_SOURCES = power6_bcmp.c
+power6_bcmp_OBJECTS = power6_bcmp.$(OBJEXT)
+power6_bcmp_LDADD = $(LDADD)
+round_SOURCES = round.c
+round_OBJECTS = round.$(OBJEXT)
+round_LDADD = $(LDADD)
+testVMX_SOURCES = testVMX.c
+testVMX_OBJECTS = testVMX-testVMX.$(OBJEXT)
+testVMX_LDADD = $(LDADD)
+testVMX_LINK = $(CCLD) $(testVMX_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp1_SOURCES = test_dfp1.c
+test_dfp1_OBJECTS = test_dfp1-test_dfp1.$(OBJEXT)
+test_dfp1_LDADD = $(LDADD)
+test_dfp1_LINK = $(CCLD) $(test_dfp1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp2_SOURCES = test_dfp2.c
+test_dfp2_OBJECTS = test_dfp2-test_dfp2.$(OBJEXT)
+test_dfp2_LDADD = $(LDADD)
+test_dfp2_LINK = $(CCLD) $(test_dfp2_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp3_SOURCES = test_dfp3.c
+test_dfp3_OBJECTS = test_dfp3-test_dfp3.$(OBJEXT)
+test_dfp3_LDADD = $(LDADD)
+test_dfp3_LINK = $(CCLD) $(test_dfp3_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp4_SOURCES = test_dfp4.c
+test_dfp4_OBJECTS = test_dfp4-test_dfp4.$(OBJEXT)
+test_dfp4_LDADD = $(LDADD)
+test_dfp4_LINK = $(CCLD) $(test_dfp4_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp5_SOURCES = test_dfp5.c
+test_dfp5_OBJECTS = test_dfp5-test_dfp5.$(OBJEXT)
+test_dfp5_LDADD = $(LDADD)
+test_dfp5_LINK = $(CCLD) $(test_dfp5_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_fx_SOURCES = test_fx.c
+test_fx_OBJECTS = test_fx.$(OBJEXT)
+test_fx_LDADD = $(LDADD)
+test_gx_SOURCES = test_gx.c
+test_gx_OBJECTS = test_gx.$(OBJEXT)
+test_gx_LDADD = $(LDADD)
+test_isa_2_06_part1_SOURCES = test_isa_2_06_part1.c
+test_isa_2_06_part1_OBJECTS = \
+ test_isa_2_06_part1-test_isa_2_06_part1.$(OBJEXT)
+test_isa_2_06_part1_LDADD = $(LDADD)
+test_isa_2_06_part1_LINK = $(CCLD) $(test_isa_2_06_part1_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_isa_2_06_part2_SOURCES = test_isa_2_06_part2.c
+test_isa_2_06_part2_OBJECTS = \
+ test_isa_2_06_part2-test_isa_2_06_part2.$(OBJEXT)
+test_isa_2_06_part2_LDADD = $(LDADD)
+test_isa_2_06_part2_LINK = $(CCLD) $(test_isa_2_06_part2_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_isa_2_06_part3_SOURCES = test_isa_2_06_part3.c
+test_isa_2_06_part3_OBJECTS = \
+ test_isa_2_06_part3-test_isa_2_06_part3.$(OBJEXT)
+test_isa_2_06_part3_LDADD = $(LDADD)
+test_isa_2_06_part3_LINK = $(CCLD) $(test_isa_2_06_part3_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+tw_SOURCES = tw.c
+tw_OBJECTS = tw.$(OBJEXT)
+tw_LDADD = $(LDADD)
+twi_SOURCES = twi.c
+twi_OBJECTS = twi.$(OBJEXT)
+twi_LDADD = $(LDADD)
+xlc_dbl_u32_SOURCES = xlc_dbl_u32.c
+xlc_dbl_u32_OBJECTS = xlc_dbl_u32.$(OBJEXT)
+xlc_dbl_u32_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = allexec.c bug129390-ppc32.c bug139050-ppc32.c jm-insns.c \
+ ldstrev.c lsw.c mcrfs.c mftocrf.c power5+_round.c \
+ power6_bcmp.c round.c testVMX.c test_dfp1.c test_dfp2.c \
+ test_dfp3.c test_dfp4.c test_dfp5.c test_fx.c test_gx.c \
+ test_isa_2_06_part1.c test_isa_2_06_part2.c \
+ test_isa_2_06_part3.c tw.c twi.c xlc_dbl_u32.c
+DIST_SOURCES = allexec.c bug129390-ppc32.c bug139050-ppc32.c \
+ jm-insns.c ldstrev.c lsw.c mcrfs.c mftocrf.c power5+_round.c \
+ power6_bcmp.c round.c testVMX.c test_dfp1.c test_dfp2.c \
+ test_dfp3.c test_dfp4.c test_dfp5.c test_fx.c test_gx.c \
+ test_isa_2_06_part1.c test_isa_2_06_part2.c \
+ test_isa_2_06_part3.c tw.c twi.c xlc_dbl_u32.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ bug129390-ppc32.stdout.exp bug129390-ppc32.stderr.exp \
+ bug129390-ppc32.vgtest \
+ bug139050-ppc32.stdout.exp bug139050-ppc32.stderr.exp \
+ bug139050-ppc32.vgtest \
+ ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
+ lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
+ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
+ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
+ jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
+ jm-vmx.vgtest \
+ mftocrf.stderr.exp mftocrf.stdout.exp mftocrf.vgtest \
+ mcrfs.stderr.exp mcrfs.stdout.exp mcrfs.vgtest \
+ round.stderr.exp round.stdout.exp round.vgtest \
+ test_fx.stderr.exp test_fx.stdout.exp test_fx.stdout.exp_Minus_nan \
+ test_fx.vgtest \
+ test_gx.stderr.exp test_gx.stdout.exp test_gx.stdout.exp_Minus_nan \
+ test_gx.vgtest \
+ testVMX.stderr.exp testVMX.stdout.exp testVMX.vgtest \
+ twi.stderr.exp twi.stdout.exp twi.vgtest \
+ tw.stderr.exp tw.stdout.exp tw.vgtest \
+ xlc_dbl_u32.stderr.exp xlc_dbl_u32.stdout.exp xlc_dbl_u32.vgtest \
+ power5+_round.stderr.exp power5+_round.stdout.exp power5+_round.vgtest \
+ power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
+ test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
+ test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
+ test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
+ test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
+ test_dfp2.stdout.exp_Without_dcffix \
+ test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \
+ test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
+ test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+@HAS_ALTIVEC_FALSE@ALTIVEC_FLAG =
+@HAS_ALTIVEC_TRUE@ALTIVEC_FLAG = -DHAS_ALTIVEC
+@HAS_VSX_FALSE@BUILD_FLAG_VSX =
+@HAS_VSX_TRUE@BUILD_FLAG_VSX = -mvsx
+@HAS_VSX_FALSE@VSX_FLAG =
+@HAS_VSX_TRUE@VSX_FLAG = -DHAS_VSX
+@HAS_DFP_FALSE@BUILD_FLAGS_DFP =
+@HAS_DFP_TRUE@BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6
+@HAS_DFP_FALSE@DFP_FLAG =
+@HAS_DFP_TRUE@DFP_FLAG = -DHAS_DFP
+jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \
+ @FLAG_M32@ $(ALTIVEC_FLAG)
+
+testVMX_CFLAGS = $(AM_CFLAGS) -O -g -Wall -maltivec -mabi=altivec -DALTIVEC \
+ -DGCC_COMPILER @FLAG_M32@
+
+test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
+ @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/ppc32/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/ppc32/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+bug129390-ppc32$(EXEEXT): $(bug129390_ppc32_OBJECTS) $(bug129390_ppc32_DEPENDENCIES)
+ @rm -f bug129390-ppc32$(EXEEXT)
+ $(LINK) $(bug129390_ppc32_OBJECTS) $(bug129390_ppc32_LDADD) $(LIBS)
+bug139050-ppc32$(EXEEXT): $(bug139050_ppc32_OBJECTS) $(bug139050_ppc32_DEPENDENCIES)
+ @rm -f bug139050-ppc32$(EXEEXT)
+ $(LINK) $(bug139050_ppc32_OBJECTS) $(bug139050_ppc32_LDADD) $(LIBS)
+jm-insns$(EXEEXT): $(jm_insns_OBJECTS) $(jm_insns_DEPENDENCIES)
+ @rm -f jm-insns$(EXEEXT)
+ $(jm_insns_LINK) $(jm_insns_OBJECTS) $(jm_insns_LDADD) $(LIBS)
+ldstrev$(EXEEXT): $(ldstrev_OBJECTS) $(ldstrev_DEPENDENCIES)
+ @rm -f ldstrev$(EXEEXT)
+ $(LINK) $(ldstrev_OBJECTS) $(ldstrev_LDADD) $(LIBS)
+lsw$(EXEEXT): $(lsw_OBJECTS) $(lsw_DEPENDENCIES)
+ @rm -f lsw$(EXEEXT)
+ $(LINK) $(lsw_OBJECTS) $(lsw_LDADD) $(LIBS)
+mcrfs$(EXEEXT): $(mcrfs_OBJECTS) $(mcrfs_DEPENDENCIES)
+ @rm -f mcrfs$(EXEEXT)
+ $(LINK) $(mcrfs_OBJECTS) $(mcrfs_LDADD) $(LIBS)
+mftocrf$(EXEEXT): $(mftocrf_OBJECTS) $(mftocrf_DEPENDENCIES)
+ @rm -f mftocrf$(EXEEXT)
+ $(LINK) $(mftocrf_OBJECTS) $(mftocrf_LDADD) $(LIBS)
+power5+_round$(EXEEXT): $(power5__round_OBJECTS) $(power5__round_DEPENDENCIES)
+ @rm -f power5+_round$(EXEEXT)
+ $(LINK) $(power5__round_OBJECTS) $(power5__round_LDADD) $(LIBS)
+power6_bcmp$(EXEEXT): $(power6_bcmp_OBJECTS) $(power6_bcmp_DEPENDENCIES)
+ @rm -f power6_bcmp$(EXEEXT)
+ $(LINK) $(power6_bcmp_OBJECTS) $(power6_bcmp_LDADD) $(LIBS)
+round$(EXEEXT): $(round_OBJECTS) $(round_DEPENDENCIES)
+ @rm -f round$(EXEEXT)
+ $(LINK) $(round_OBJECTS) $(round_LDADD) $(LIBS)
+testVMX$(EXEEXT): $(testVMX_OBJECTS) $(testVMX_DEPENDENCIES)
+ @rm -f testVMX$(EXEEXT)
+ $(testVMX_LINK) $(testVMX_OBJECTS) $(testVMX_LDADD) $(LIBS)
+test_dfp1$(EXEEXT): $(test_dfp1_OBJECTS) $(test_dfp1_DEPENDENCIES)
+ @rm -f test_dfp1$(EXEEXT)
+ $(test_dfp1_LINK) $(test_dfp1_OBJECTS) $(test_dfp1_LDADD) $(LIBS)
+test_dfp2$(EXEEXT): $(test_dfp2_OBJECTS) $(test_dfp2_DEPENDENCIES)
+ @rm -f test_dfp2$(EXEEXT)
+ $(test_dfp2_LINK) $(test_dfp2_OBJECTS) $(test_dfp2_LDADD) $(LIBS)
+test_dfp3$(EXEEXT): $(test_dfp3_OBJECTS) $(test_dfp3_DEPENDENCIES)
+ @rm -f test_dfp3$(EXEEXT)
+ $(test_dfp3_LINK) $(test_dfp3_OBJECTS) $(test_dfp3_LDADD) $(LIBS)
+test_dfp4$(EXEEXT): $(test_dfp4_OBJECTS) $(test_dfp4_DEPENDENCIES)
+ @rm -f test_dfp4$(EXEEXT)
+ $(test_dfp4_LINK) $(test_dfp4_OBJECTS) $(test_dfp4_LDADD) $(LIBS)
+test_dfp5$(EXEEXT): $(test_dfp5_OBJECTS) $(test_dfp5_DEPENDENCIES)
+ @rm -f test_dfp5$(EXEEXT)
+ $(test_dfp5_LINK) $(test_dfp5_OBJECTS) $(test_dfp5_LDADD) $(LIBS)
+test_fx$(EXEEXT): $(test_fx_OBJECTS) $(test_fx_DEPENDENCIES)
+ @rm -f test_fx$(EXEEXT)
+ $(LINK) $(test_fx_OBJECTS) $(test_fx_LDADD) $(LIBS)
+test_gx$(EXEEXT): $(test_gx_OBJECTS) $(test_gx_DEPENDENCIES)
+ @rm -f test_gx$(EXEEXT)
+ $(LINK) $(test_gx_OBJECTS) $(test_gx_LDADD) $(LIBS)
+test_isa_2_06_part1$(EXEEXT): $(test_isa_2_06_part1_OBJECTS) $(test_isa_2_06_part1_DEPENDENCIES)
+ @rm -f test_isa_2_06_part1$(EXEEXT)
+ $(test_isa_2_06_part1_LINK) $(test_isa_2_06_part1_OBJECTS) $(test_isa_2_06_part1_LDADD) $(LIBS)
+test_isa_2_06_part2$(EXEEXT): $(test_isa_2_06_part2_OBJECTS) $(test_isa_2_06_part2_DEPENDENCIES)
+ @rm -f test_isa_2_06_part2$(EXEEXT)
+ $(test_isa_2_06_part2_LINK) $(test_isa_2_06_part2_OBJECTS) $(test_isa_2_06_part2_LDADD) $(LIBS)
+test_isa_2_06_part3$(EXEEXT): $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_DEPENDENCIES)
+ @rm -f test_isa_2_06_part3$(EXEEXT)
+ $(test_isa_2_06_part3_LINK) $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_LDADD) $(LIBS)
+tw$(EXEEXT): $(tw_OBJECTS) $(tw_DEPENDENCIES)
+ @rm -f tw$(EXEEXT)
+ $(LINK) $(tw_OBJECTS) $(tw_LDADD) $(LIBS)
+twi$(EXEEXT): $(twi_OBJECTS) $(twi_DEPENDENCIES)
+ @rm -f twi$(EXEEXT)
+ $(LINK) $(twi_OBJECTS) $(twi_LDADD) $(LIBS)
+xlc_dbl_u32$(EXEEXT): $(xlc_dbl_u32_OBJECTS) $(xlc_dbl_u32_DEPENDENCIES)
+ @rm -f xlc_dbl_u32$(EXEEXT)
+ $(LINK) $(xlc_dbl_u32_OBJECTS) $(xlc_dbl_u32_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug129390-ppc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug139050-ppc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jm_insns-jm-insns.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ldstrev.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lsw.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mcrfs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mftocrf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/power5+_round.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/power6_bcmp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/round.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/testVMX-testVMX.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp1-test_dfp1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp2-test_dfp2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp3-test_dfp3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp4-test_dfp4.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp5-test_dfp5.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_fx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_gx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tw.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/twi.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xlc_dbl_u32.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+allexec-allexec.o: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.o -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+
+allexec-allexec.obj: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.obj -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+
+jm_insns-jm-insns.o: jm-insns.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(jm_insns_CFLAGS) $(CFLAGS) -MT jm_insns-jm-insns.o -MD -MP -MF $(DEPDIR)/jm_insns-jm-insns.Tpo -c -o jm_insns-jm-insns.o `test -f 'jm-insns.c' || echo '$(srcdir)/'`jm-insns.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/jm_insns-jm-insns.Tpo $(DEPDIR)/jm_insns-jm-insns.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='jm-insns.c' object='jm_insns-jm-insns.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(jm_insns_CFLAGS) $(CFLAGS) -c -o jm_insns-jm-insns.o `test -f 'jm-insns.c' || echo '$(srcdir)/'`jm-insns.c
+
+jm_insns-jm-insns.obj: jm-insns.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(jm_insns_CFLAGS) $(CFLAGS) -MT jm_insns-jm-insns.obj -MD -MP -MF $(DEPDIR)/jm_insns-jm-insns.Tpo -c -o jm_insns-jm-insns.obj `if test -f 'jm-insns.c'; then $(CYGPATH_W) 'jm-insns.c'; else $(CYGPATH_W) '$(srcdir)/jm-insns.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/jm_insns-jm-insns.Tpo $(DEPDIR)/jm_insns-jm-insns.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='jm-insns.c' object='jm_insns-jm-insns.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(jm_insns_CFLAGS) $(CFLAGS) -c -o jm_insns-jm-insns.obj `if test -f 'jm-insns.c'; then $(CYGPATH_W) 'jm-insns.c'; else $(CYGPATH_W) '$(srcdir)/jm-insns.c'; fi`
+
+testVMX-testVMX.o: testVMX.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testVMX_CFLAGS) $(CFLAGS) -MT testVMX-testVMX.o -MD -MP -MF $(DEPDIR)/testVMX-testVMX.Tpo -c -o testVMX-testVMX.o `test -f 'testVMX.c' || echo '$(srcdir)/'`testVMX.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/testVMX-testVMX.Tpo $(DEPDIR)/testVMX-testVMX.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='testVMX.c' object='testVMX-testVMX.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testVMX_CFLAGS) $(CFLAGS) -c -o testVMX-testVMX.o `test -f 'testVMX.c' || echo '$(srcdir)/'`testVMX.c
+
+testVMX-testVMX.obj: testVMX.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testVMX_CFLAGS) $(CFLAGS) -MT testVMX-testVMX.obj -MD -MP -MF $(DEPDIR)/testVMX-testVMX.Tpo -c -o testVMX-testVMX.obj `if test -f 'testVMX.c'; then $(CYGPATH_W) 'testVMX.c'; else $(CYGPATH_W) '$(srcdir)/testVMX.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/testVMX-testVMX.Tpo $(DEPDIR)/testVMX-testVMX.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='testVMX.c' object='testVMX-testVMX.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(testVMX_CFLAGS) $(CFLAGS) -c -o testVMX-testVMX.obj `if test -f 'testVMX.c'; then $(CYGPATH_W) 'testVMX.c'; else $(CYGPATH_W) '$(srcdir)/testVMX.c'; fi`
+
+test_dfp1-test_dfp1.o: test_dfp1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp1_CFLAGS) $(CFLAGS) -MT test_dfp1-test_dfp1.o -MD -MP -MF $(DEPDIR)/test_dfp1-test_dfp1.Tpo -c -o test_dfp1-test_dfp1.o `test -f 'test_dfp1.c' || echo '$(srcdir)/'`test_dfp1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp1-test_dfp1.Tpo $(DEPDIR)/test_dfp1-test_dfp1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp1.c' object='test_dfp1-test_dfp1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp1_CFLAGS) $(CFLAGS) -c -o test_dfp1-test_dfp1.o `test -f 'test_dfp1.c' || echo '$(srcdir)/'`test_dfp1.c
+
+test_dfp1-test_dfp1.obj: test_dfp1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp1_CFLAGS) $(CFLAGS) -MT test_dfp1-test_dfp1.obj -MD -MP -MF $(DEPDIR)/test_dfp1-test_dfp1.Tpo -c -o test_dfp1-test_dfp1.obj `if test -f 'test_dfp1.c'; then $(CYGPATH_W) 'test_dfp1.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp1-test_dfp1.Tpo $(DEPDIR)/test_dfp1-test_dfp1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp1.c' object='test_dfp1-test_dfp1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp1_CFLAGS) $(CFLAGS) -c -o test_dfp1-test_dfp1.obj `if test -f 'test_dfp1.c'; then $(CYGPATH_W) 'test_dfp1.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp1.c'; fi`
+
+test_dfp2-test_dfp2.o: test_dfp2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp2_CFLAGS) $(CFLAGS) -MT test_dfp2-test_dfp2.o -MD -MP -MF $(DEPDIR)/test_dfp2-test_dfp2.Tpo -c -o test_dfp2-test_dfp2.o `test -f 'test_dfp2.c' || echo '$(srcdir)/'`test_dfp2.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp2-test_dfp2.Tpo $(DEPDIR)/test_dfp2-test_dfp2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp2.c' object='test_dfp2-test_dfp2.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp2_CFLAGS) $(CFLAGS) -c -o test_dfp2-test_dfp2.o `test -f 'test_dfp2.c' || echo '$(srcdir)/'`test_dfp2.c
+
+test_dfp2-test_dfp2.obj: test_dfp2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp2_CFLAGS) $(CFLAGS) -MT test_dfp2-test_dfp2.obj -MD -MP -MF $(DEPDIR)/test_dfp2-test_dfp2.Tpo -c -o test_dfp2-test_dfp2.obj `if test -f 'test_dfp2.c'; then $(CYGPATH_W) 'test_dfp2.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp2.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp2-test_dfp2.Tpo $(DEPDIR)/test_dfp2-test_dfp2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp2.c' object='test_dfp2-test_dfp2.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp2_CFLAGS) $(CFLAGS) -c -o test_dfp2-test_dfp2.obj `if test -f 'test_dfp2.c'; then $(CYGPATH_W) 'test_dfp2.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp2.c'; fi`
+
+test_dfp3-test_dfp3.o: test_dfp3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp3_CFLAGS) $(CFLAGS) -MT test_dfp3-test_dfp3.o -MD -MP -MF $(DEPDIR)/test_dfp3-test_dfp3.Tpo -c -o test_dfp3-test_dfp3.o `test -f 'test_dfp3.c' || echo '$(srcdir)/'`test_dfp3.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp3-test_dfp3.Tpo $(DEPDIR)/test_dfp3-test_dfp3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp3.c' object='test_dfp3-test_dfp3.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp3_CFLAGS) $(CFLAGS) -c -o test_dfp3-test_dfp3.o `test -f 'test_dfp3.c' || echo '$(srcdir)/'`test_dfp3.c
+
+test_dfp3-test_dfp3.obj: test_dfp3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp3_CFLAGS) $(CFLAGS) -MT test_dfp3-test_dfp3.obj -MD -MP -MF $(DEPDIR)/test_dfp3-test_dfp3.Tpo -c -o test_dfp3-test_dfp3.obj `if test -f 'test_dfp3.c'; then $(CYGPATH_W) 'test_dfp3.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp3.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp3-test_dfp3.Tpo $(DEPDIR)/test_dfp3-test_dfp3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp3.c' object='test_dfp3-test_dfp3.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp3_CFLAGS) $(CFLAGS) -c -o test_dfp3-test_dfp3.obj `if test -f 'test_dfp3.c'; then $(CYGPATH_W) 'test_dfp3.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp3.c'; fi`
+
+test_dfp4-test_dfp4.o: test_dfp4.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp4_CFLAGS) $(CFLAGS) -MT test_dfp4-test_dfp4.o -MD -MP -MF $(DEPDIR)/test_dfp4-test_dfp4.Tpo -c -o test_dfp4-test_dfp4.o `test -f 'test_dfp4.c' || echo '$(srcdir)/'`test_dfp4.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp4-test_dfp4.Tpo $(DEPDIR)/test_dfp4-test_dfp4.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp4.c' object='test_dfp4-test_dfp4.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp4_CFLAGS) $(CFLAGS) -c -o test_dfp4-test_dfp4.o `test -f 'test_dfp4.c' || echo '$(srcdir)/'`test_dfp4.c
+
+test_dfp4-test_dfp4.obj: test_dfp4.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp4_CFLAGS) $(CFLAGS) -MT test_dfp4-test_dfp4.obj -MD -MP -MF $(DEPDIR)/test_dfp4-test_dfp4.Tpo -c -o test_dfp4-test_dfp4.obj `if test -f 'test_dfp4.c'; then $(CYGPATH_W) 'test_dfp4.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp4.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp4-test_dfp4.Tpo $(DEPDIR)/test_dfp4-test_dfp4.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp4.c' object='test_dfp4-test_dfp4.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp4_CFLAGS) $(CFLAGS) -c -o test_dfp4-test_dfp4.obj `if test -f 'test_dfp4.c'; then $(CYGPATH_W) 'test_dfp4.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp4.c'; fi`
+
+test_dfp5-test_dfp5.o: test_dfp5.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp5_CFLAGS) $(CFLAGS) -MT test_dfp5-test_dfp5.o -MD -MP -MF $(DEPDIR)/test_dfp5-test_dfp5.Tpo -c -o test_dfp5-test_dfp5.o `test -f 'test_dfp5.c' || echo '$(srcdir)/'`test_dfp5.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp5-test_dfp5.Tpo $(DEPDIR)/test_dfp5-test_dfp5.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp5.c' object='test_dfp5-test_dfp5.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp5_CFLAGS) $(CFLAGS) -c -o test_dfp5-test_dfp5.o `test -f 'test_dfp5.c' || echo '$(srcdir)/'`test_dfp5.c
+
+test_dfp5-test_dfp5.obj: test_dfp5.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp5_CFLAGS) $(CFLAGS) -MT test_dfp5-test_dfp5.obj -MD -MP -MF $(DEPDIR)/test_dfp5-test_dfp5.Tpo -c -o test_dfp5-test_dfp5.obj `if test -f 'test_dfp5.c'; then $(CYGPATH_W) 'test_dfp5.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp5.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp5-test_dfp5.Tpo $(DEPDIR)/test_dfp5-test_dfp5.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp5.c' object='test_dfp5-test_dfp5.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp5_CFLAGS) $(CFLAGS) -c -o test_dfp5-test_dfp5.obj `if test -f 'test_dfp5.c'; then $(CYGPATH_W) 'test_dfp5.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp5.c'; fi`
+
+test_isa_2_06_part1-test_isa_2_06_part1.o: test_isa_2_06_part1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part1_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part1-test_isa_2_06_part1.o -MD -MP -MF $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Tpo -c -o test_isa_2_06_part1-test_isa_2_06_part1.o `test -f 'test_isa_2_06_part1.c' || echo '$(srcdir)/'`test_isa_2_06_part1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Tpo $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part1.c' object='test_isa_2_06_part1-test_isa_2_06_part1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part1_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part1-test_isa_2_06_part1.o `test -f 'test_isa_2_06_part1.c' || echo '$(srcdir)/'`test_isa_2_06_part1.c
+
+test_isa_2_06_part1-test_isa_2_06_part1.obj: test_isa_2_06_part1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part1_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part1-test_isa_2_06_part1.obj -MD -MP -MF $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Tpo -c -o test_isa_2_06_part1-test_isa_2_06_part1.obj `if test -f 'test_isa_2_06_part1.c'; then $(CYGPATH_W) 'test_isa_2_06_part1.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Tpo $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part1.c' object='test_isa_2_06_part1-test_isa_2_06_part1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part1_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part1-test_isa_2_06_part1.obj `if test -f 'test_isa_2_06_part1.c'; then $(CYGPATH_W) 'test_isa_2_06_part1.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part1.c'; fi`
+
+test_isa_2_06_part2-test_isa_2_06_part2.o: test_isa_2_06_part2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part2_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part2-test_isa_2_06_part2.o -MD -MP -MF $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Tpo -c -o test_isa_2_06_part2-test_isa_2_06_part2.o `test -f 'test_isa_2_06_part2.c' || echo '$(srcdir)/'`test_isa_2_06_part2.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Tpo $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part2.c' object='test_isa_2_06_part2-test_isa_2_06_part2.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part2_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part2-test_isa_2_06_part2.o `test -f 'test_isa_2_06_part2.c' || echo '$(srcdir)/'`test_isa_2_06_part2.c
+
+test_isa_2_06_part2-test_isa_2_06_part2.obj: test_isa_2_06_part2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part2_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part2-test_isa_2_06_part2.obj -MD -MP -MF $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Tpo -c -o test_isa_2_06_part2-test_isa_2_06_part2.obj `if test -f 'test_isa_2_06_part2.c'; then $(CYGPATH_W) 'test_isa_2_06_part2.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part2.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Tpo $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part2.c' object='test_isa_2_06_part2-test_isa_2_06_part2.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part2_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part2-test_isa_2_06_part2.obj `if test -f 'test_isa_2_06_part2.c'; then $(CYGPATH_W) 'test_isa_2_06_part2.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part2.c'; fi`
+
+test_isa_2_06_part3-test_isa_2_06_part3.o: test_isa_2_06_part3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part3-test_isa_2_06_part3.o -MD -MP -MF $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Tpo -c -o test_isa_2_06_part3-test_isa_2_06_part3.o `test -f 'test_isa_2_06_part3.c' || echo '$(srcdir)/'`test_isa_2_06_part3.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Tpo $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part3.c' object='test_isa_2_06_part3-test_isa_2_06_part3.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part3-test_isa_2_06_part3.o `test -f 'test_isa_2_06_part3.c' || echo '$(srcdir)/'`test_isa_2_06_part3.c
+
+test_isa_2_06_part3-test_isa_2_06_part3.obj: test_isa_2_06_part3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part3-test_isa_2_06_part3.obj -MD -MP -MF $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Tpo -c -o test_isa_2_06_part3-test_isa_2_06_part3.obj `if test -f 'test_isa_2_06_part3.c'; then $(CYGPATH_W) 'test_isa_2_06_part3.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part3.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Tpo $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part3.c' object='test_isa_2_06_part3-test_isa_2_06_part3.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part3-test_isa_2_06_part3.obj `if test -f 'test_isa_2_06_part3.c'; then $(CYGPATH_W) 'test_isa_2_06_part3.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part3.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/ppc32/allexec.c b/main/none/tests/ppc32/allexec.c
new file mode 100644
index 0000000..b7177e8
--- /dev/null
+++ b/main/none/tests/ppc32/allexec.c
@@ -0,0 +1,50 @@
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+extern char **environ;
+
+#define S(...) (fprintf(stdout, __VA_ARGS__),fflush(stdout))
+#define FORKEXECWAIT(exec_call) do { \
+ int status;\
+ pid_t child = fork(); \
+ if (child == 0) {exec_call; perror ("exec failed");} \
+ else if (child == -1) perror ("cannot fork\n"); \
+ else if (child != wait (&status)) perror ("error waiting child"); \
+ else S("child exited\n"); \
+ } while (0)
+
+void test_allexec (char *exec)
+{
+ FORKEXECWAIT (execlp(exec, exec, NULL));
+ FORKEXECWAIT (execlp(exec, exec, "constant_arg1", "constant_arg2", NULL));
+ FORKEXECWAIT (execve(exec, NULL, environ));
+}
+
+
+/* If a single argument "exec" is given, will execute itself
+ (in bi-arch, a 32 bit and 64 bit variant) via various exec system calls.
+ Note that this test can only be run after the prerequisite have been
+ prepared by allexec_prepare_prereq, which will a.o. make links
+ for the allexec32 and allexec64 executables. On single arch build,
+ these links points to the same executable to ensure this test works
+ everywhere the same.
+ No arguments or more arguments means just print its args. */
+int main(int argc, char **argv, char **envp)
+{
+ if ( (argc == 2) && (strcmp (argv[1], "exec") == 0)) {
+ S("%s will exec ./allexec32\n", argv[0]);
+ test_allexec ("./allexec32");
+ S("%s will exec ./allexec64\n", argv[0]);
+ test_allexec ("./allexec64");
+ } else {
+ int i;
+ S("program exec-ed:");
+ for (i = 0; i < argc; i++) S(" %s", argv[i]);
+ S("\n");
+ }
+ return 0;
+}
diff --git a/main/none/tests/ppc32/jm-fp.stdout.exp b/main/none/tests/ppc32/jm-fp.stdout.exp
index b2394cf..cff9df2 100644
--- a/main/none/tests/ppc32/jm-fp.stdout.exp
+++ b/main/none/tests/ppc32/jm-fp.stdout.exp
@@ -719,8 +719,8 @@
frsqrte 8000000000000000 => fff0000000000000
frsqrte 7ff0000000000000 => 0000000000000000
frsqrte fff0000000000000 => 7ff8000000000000
- frsqrte 7ff7ffffffffffff => 7fff800000000000
- frsqrte fff7ffffffffffff => ffff800000000000
+ frsqrte 7ff7ffffffffffff => 7fff000000000000
+ frsqrte fff7ffffffffffff => ffff000000000000
frsqrte 7ff8000000000000 => 7ff8000000000000
frsqrte fff8000000000000 => fff8000000000000
@@ -891,8 +891,8 @@
frsqrte. 8000000000000000 => fff0000000000000
frsqrte. 7ff0000000000000 => 0000000000000000
frsqrte. fff0000000000000 => 7ff8000000000000
- frsqrte. 7ff7ffffffffffff => 7fff800000000000
- frsqrte. fff7ffffffffffff => ffff800000000000
+ frsqrte. 7ff7ffffffffffff => 7fff000000000000
+ frsqrte. fff7ffffffffffff => ffff000000000000
frsqrte. 7ff8000000000000 => 7ff8000000000000
frsqrte. fff8000000000000 => fff8000000000000
diff --git a/main/none/tests/ppc32/jm-insns.c b/main/none/tests/ppc32/jm-insns.c
index 3249d23..038fb73 100644
--- a/main/none/tests/ppc32/jm-insns.c
+++ b/main/none/tests/ppc32/jm-insns.c
@@ -360,6 +360,7 @@
PPC_COMPARE = 0x00000300,
PPC_CROP = 0x00000400,
PPC_LDST = 0x00000500,
+ PPC_POPCNT = 0x00000600,
PPC_TYPE = 0x00000F00,
/* Family */
PPC_INTEGER = 0x00010000,
@@ -1686,6 +1687,17 @@
{ NULL, NULL, },
};
+static void
+tests_popcnt_one(void)
+{
+ __asm__ __volatile__ ("popcntb 17, 14");
+}
+
+static test_t tests_popcnt_ops_one[] = {
+ { &tests_popcnt_one , " popcntb", },
+ { NULL, NULL, },
+};
+
#if !defined (NO_FLOAT)
static void test_fsel (void)
{
@@ -2030,7 +2042,7 @@
static void test_frsqrte_ (void)
{
- __asm__ __volatile__ ("frsqrte. 17, 14");
+ __asm__ __volatile__ ("frsqrte. 17, 14");
}
static void test_frsp_ (void)
@@ -3115,7 +3127,7 @@
#endif /* defined (HAS_ALTIVEC) */
#if defined (HAS_ALTIVEC)
-#if 0
+#if 1
static void test_vmaddfp (void)
{
__asm__ __volatile__ ("vmaddfp 17, 14, 15, 16");
@@ -3128,8 +3140,8 @@
#endif
static test_t tests_afa_ops_three[] = {
-// { &test_vmaddfp , " vmaddfp", }, // TODO: Not yet supported
-// { &test_vnmsubfp , " vnmsubfp", }, // TODO: Not yet supported
+ { &test_vmaddfp , " vmaddfp", },
+ { &test_vnmsubfp , " vnmsubfp", },
{ NULL, NULL, },
};
#endif /* defined (HAS_ALTIVEC) */
@@ -3934,6 +3946,11 @@
"PPC integer store insns with three register args",
0x0001050b,
},
+ {
+ tests_popcnt_ops_one ,
+ "PPC integer population count with one register args, no flags",
+ 0x00010601,
+ },
#if !defined (NO_FLOAT)
{
tests_fa_ops_three ,
@@ -4097,16 +4114,16 @@
#endif /* defined (HAS_ALTIVEC) */
#if defined (HAS_ALTIVEC)
{
- tests_afa_ops_three ,
- "Altivec floating point arith insns with three args",
- 0x00050103,
+ tests_afa_ops_two ,
+ "Altivec floating point arith insns with two args",
+ 0x00050102,
},
#endif /* defined (HAS_ALTIVEC) */
#if defined (HAS_ALTIVEC)
{
- tests_afa_ops_two ,
- "Altivec floating point arith insns with two args",
- 0x00050102,
+ tests_afa_ops_three ,
+ "Altivec floating point arith insns with three args",
+ 0x00050103,
},
#endif /* defined (HAS_ALTIVEC) */
#if defined (HAS_ALTIVEC)
@@ -4624,12 +4641,17 @@
{
volatile HWord_t res;
volatile uint32_t flags, xer, xer_orig;
- int i, j, is_div, zap_hi32;
+ int i, j, is_div;
+#ifdef __powerpc64__
+ int zap_hi32;
+#endif
// catches div, divwu, divo, divwu, divwuo, and . variants
is_div = strstr(name, "divw") != NULL;
+#ifdef __powerpc64__
zap_hi32 = strstr(name, "mulhw") != NULL;
+#endif
xer_orig = 0x00000000;
redo:
@@ -5741,6 +5763,14 @@
res = f17;
ur = *(uint64_t *)(&res);
+ if (strstr(name, " frsqrte") != NULL)
+ /* The 32-bit frsqrte instruction is the Floatig Reciprical Square
+ * Root Estimate instruction. The precision of the estimate will
+ * vary from Proceesor implementation. The approximation varies in
+ * bottom two bytes of the 32-bit result.
+ */
+ ur &= 0xFFFF000000000000ULL;
+
if (zap_hi_32bits)
ur &= 0x00000000FFFFFFFFULL;
if (zap_lo_44bits)
@@ -6866,12 +6896,12 @@
#endif
/* if we're doing an estimation operation, arrange to zap the
- bottom byte of the result as it's basically garbage, and differs
+ bottom 10-bits of the result as it's basically garbage, and differs
between cpus */
unsigned int mask
= (strstr(name,"vrsqrtefp") != NULL ||
strstr(name, "vrefp") != NULL)
- ? 0xFFFFFF00 : 0xFFFFFFFF;
+ ? 0xFFFFC000 : 0xFFFFFFFF;
for (i=0; i<nb_vfargs; i++) {
vec_in = (vector float)vfargs[i];
@@ -6995,7 +7025,7 @@
volatile vector float vec_in1, vec_in2, vec_in3, vec_out;
volatile vector unsigned int vscr;
unsigned int *src1, *src2, *src3, *dst;
- int i,j,k;
+ int i,j,k,n;
#if defined TEST_VSCR_SAT
unsigned int* p_vscr;
#endif
@@ -7042,6 +7072,38 @@
src3 = (unsigned int*)&vec_in3;
dst = (unsigned int*)&vec_out;
+ /* Valgrind emulation for vmaddfp and vnmsubfp generates negative
+ * NAN. Technically, NAN is not positive or negative so mask off
+ * the sign bit to eliminate false errors.
+ *
+ * Valgrind emulation is creating negative zero. Mask off negative
+ * from zero result.
+ *
+ * These are only an issue as we are printing the result in hex.
+ *
+ * The VEX emulation accuracy for the vmaddfp and vnmsubfp
+ * instructions is off by a single bit in the least significant
+ * bit position of the result. Mask off the LSB.
+ */
+
+ for (n=0; n<4; n++) {
+ /* NAN result*/
+ if (((dst[n] & 0x7F800000) == 0x7F800000) &&
+ ((dst[n] & 0x7FFFFF) != 0))
+ dst[n] &= 0x7FFFFFFF;
+
+ /* Negative zero result */
+ else if (dst[n] == 0x80000000)
+ dst[n] = 0x0;
+
+ else
+ /* The actual result and the emulated result for the
+ * vmaddfp and vnmsubfp instructions sometimes differ
+ * in the least significant bit. Mask off the bit.
+ */
+ dst[n] &= 0xFFFFFFFE;
+ }
+
printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
src1[0], src1[1], src1[2], src1[3],
src2[0], src2[1], src2[2], src2[3],
@@ -7307,7 +7369,8 @@
if ((type == PPC_ARITH && !seln_flags.arith) ||
(type == PPC_LOGICAL && !seln_flags.logical) ||
(type == PPC_COMPARE && !seln_flags.compare) ||
- (type == PPC_LDST && !seln_flags.ldst))
+ (type == PPC_LDST && !seln_flags.ldst) ||
+ (type == PPC_POPCNT && !seln_flags.arith))
continue;
/* Check instruction family */
family = all_tests[i].flags & PPC_FAMILY;
diff --git a/main/none/tests/ppc32/jm-int.stdout.exp b/main/none/tests/ppc32/jm-int.stdout.exp
index 9d524da..5198d02 100644
--- a/main/none/tests/ppc32/jm-int.stdout.exp
+++ b/main/none/tests/ppc32/jm-int.stdout.exp
@@ -1596,4 +1596,9 @@
stwux 000f423f, 4 => 000f423f, 4 (00000000 00000000)
stwux ffffffff, 8 => ffffffff, 8 (00000000 00000000)
-All done. Tested 154 different instructions
+PPC integer population count with one register args, no flags:
+ popcntb 00000000 => 00000000 (00000000 00000000)
+ popcntb 000f423f => 00040206 (00000000 00000000)
+ popcntb ffffffff => 08080808 (00000000 00000000)
+
+All done. Tested 155 different instructions
diff --git a/main/none/tests/ppc32/jm-vmx.stdout.exp b/main/none/tests/ppc32/jm-vmx.stdout.exp
index 0a0bb3e..3e19e63 100644
--- a/main/none/tests/ppc32/jm-vmx.stdout.exp
+++ b/main/none/tests/ppc32/jm-vmx.stdout.exp
@@ -1517,7 +1517,6 @@
stvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
stvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
-Altivec floating point arith insns with three args:
Altivec floating point arith insns with two args:
vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
vaddfp: => 033fffff 033fffff 033fffff 033fffff (00000000)
@@ -1907,6 +1906,585 @@
vminfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+Altivec floating point arith insns with three args:
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+
Altivec floating point arith insns with one arg:
vrfin: 02bfffff 02bfffff 02bfffff 02bfffff
vrfin: => 00000000 00000000 00000000 00000000 (00000000)
@@ -2009,13 +2587,13 @@
vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
vrefp: 02bfffff 02bfffff 02bfffff 02bfffff
- vrefp: => 7c2aa900 7c2aa900 7c2aa900 7c2aa900 (00000000)
+ vrefp: => 7c2a8000 7c2a8000 7c2a8000 7c2a8000 (00000000)
vrefp: 513fffff 513fffff 513fffff 513fffff
- vrefp: => 2daaa900 2daaa900 2daaa900 2daaa900 (00000000)
+ vrefp: => 2daa8000 2daa8000 2daa8000 2daa8000 (00000000)
vrefp: 82bfffff 82bfffff 82bfffff 82bfffff
- vrefp: => fc2aa900 fc2aa900 fc2aa900 fc2aa900 (00000000)
+ vrefp: => fc2a8000 fc2a8000 fc2a8000 fc2a8000 (00000000)
vrefp: d13fffff d13fffff d13fffff d13fffff
- vrefp: => adaaa900 adaaa900 adaaa900 adaaa900 (00000000)
+ vrefp: => adaa8000 adaa8000 adaa8000 adaa8000 (00000000)
vrefp: 00000000 00000000 00000000 00000000
vrefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
vrefp: 80000000 80000000 80000000 80000000
@@ -2025,18 +2603,18 @@
vrefp: ff800000 ff800000 ff800000 ff800000
vrefp: => 80000000 80000000 80000000 80000000 (00000000)
vrefp: 7fffffff 7fffffff 7fffffff 7fffffff
- vrefp: => 7fffff00 7fffff00 7fffff00 7fffff00 (00000000)
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
vrefp: ffffffff ffffffff ffffffff ffffffff
- vrefp: => ffffff00 ffffff00 ffffff00 ffffff00 (00000000)
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
vrefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
- vrefp: => 7fffff00 7fffff00 7fffff00 7fffff00 (00000000)
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
vrefp: ffbfffff ffbfffff ffbfffff ffbfffff
- vrefp: => ffffff00 ffffff00 ffffff00 ffffff00 (00000000)
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
vrsqrtefp: 02bfffff 02bfffff 02bfffff 02bfffff
- vrsqrtefp: => 5dd10300 5dd10300 5dd10300 5dd10300 (00000000)
+ vrsqrtefp: => 5dd10000 5dd10000 5dd10000 5dd10000 (00000000)
vrsqrtefp: 513fffff 513fffff 513fffff 513fffff
- vrsqrtefp: => 3693ca00 3693ca00 3693ca00 3693ca00 (00000000)
+ vrsqrtefp: => 3693c000 3693c000 3693c000 3693c000 (00000000)
vrsqrtefp: 82bfffff 82bfffff 82bfffff 82bfffff
vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
vrsqrtefp: d13fffff d13fffff d13fffff d13fffff
@@ -2050,13 +2628,13 @@
vrsqrtefp: ff800000 ff800000 ff800000 ff800000
vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
vrsqrtefp: 7fffffff 7fffffff 7fffffff 7fffffff
- vrsqrtefp: => 7fffff00 7fffff00 7fffff00 7fffff00 (00000000)
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
vrsqrtefp: ffffffff ffffffff ffffffff ffffffff
- vrsqrtefp: => ffffff00 ffffff00 ffffff00 ffffff00 (00000000)
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
vrsqrtefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
- vrsqrtefp: => 7fffff00 7fffff00 7fffff00 7fffff00 (00000000)
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff
- vrsqrtefp: => ffffff00 ffffff00 ffffff00 ffffff00 (00000000)
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
Altivec floating point compare insns:
vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
@@ -3033,4 +3611,4 @@
vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
-All done. Tested 163 different instructions
+All done. Tested 165 different instructions
diff --git a/main/none/tests/ppc32/jm-vmx.stdout.exp_Minus_nan b/main/none/tests/ppc32/jm-vmx.stdout.exp_Minus_nan
new file mode 100644
index 0000000..c3360e3
--- /dev/null
+++ b/main/none/tests/ppc32/jm-vmx.stdout.exp_Minus_nan
@@ -0,0 +1,3614 @@
+PPC altivec integer arith insns with three args:
+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmhaddshs: => 010403160538076a09ad0c000f970f9a (00000000)
+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhaddshs: => f1f4f406f628f85afa9dfcf00087008a (00000000)
+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000)
+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000)
+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000)
+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000)
+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmhaddshs: => 028d042605cf078909520b2c0e0f0e11 (00000000)
+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhaddshs: => f37df516f6bff879fa42fc1cfeffff01 (00000000)
+
+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmhraddshs: => 010403160538076b09ad0c000f980f9a (00000000)
+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhraddshs: => f1f4f406f628f85bfa9dfcf00088008a (00000000)
+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000)
+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000)
+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000)
+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000)
+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmhraddshs: => 028d042605d0078909530b2c0e0f0e11 (00000000)
+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhraddshs: => f37df516f6c0f879fa43fc1cfeffff01 (00000000)
+
+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmladduhm: => 05061b14412a7748bd6e139c7ab6b2f0 (00000000)
+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmladduhm: => f5f60c04321a6838ae5e048c6ba6a3e0 (00000000)
+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000)
+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000)
+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000)
+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000)
+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmladduhm: => 89c62394cd6a8748512e2b1c14161010 (00000000)
+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmladduhm: => 7ab61484be5a7838421e1c0c05060100 (00000000)
+
+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumubm: => 01020322050607b6090a0cca0e0d1121 (00000000)
+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumubm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000)
+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000)
+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000)
+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumubm: => 010599e20509bc76090ddf8a0e10fe21 (00000000)
+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumubm: => f1f68ad2f5faad66f9fed07aff01ef11 (00000000)
+
+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhm: => 010c1f180550b36c09d5c8000f981f99 (00000000)
+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhm: => f1fd1008f641a45cfac6b8f000891089 (00000000)
+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000)
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000)
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhm: => ce24ac58e1874facf52a73400a071619 (00000000)
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhm: => bf159d48d278409ce61b6430faf80709 (00000000)
+
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshs: => 010c1f180550b36c09d5c8000f981f99 (00000000)
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshs: => f1fd1008f641a45cfac6b8f000891089 (00000000)
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshs: => 0258ac5805ab4fac093e73400e0f1619 (00000000)
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshs: => f3499d48f69c409cfa2f6430ff000709 (00000000)
+
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhs: => 010c1f180550b36c09d5c8000f981f99 (00000000)
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhs: => f1fd1008f641a45cfac6b8f0ffffffff (00000000)
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000)
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000)
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000)
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000)
+
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsummbm: => 01020322050607b6090a0cca0e0d1121 (00000000)
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsummbm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000)
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsummbm: => 01020c8205062016090a342a0e0d45a1 (00000000)
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsummbm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsummbm: => 0102028205060616090a0a2a0e0d0da1 (00000000)
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsummbm: => f1f2f372f5f6f706f9fafb1afefdfe91 (00000000)
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsummbm: => 0101cfe20505e2760909f58a0e0d0621 (00000000)
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsummbm: => f1f2c0d2f5f6d366f9fae67afefdf711 (00000000)
+
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshm: => 010c1f180550b36c09d5c8000f981f99 (00000000)
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshm: => f1fd1008f641a45cfac6b8f000891089 (00000000)
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshm: => 0258ac5805ab4fac093e73400e0f1619 (00000000)
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshm: => f3499d48f69c409cfa2f6430ff000709 (00000000)
+
+PPC altivec integer logical insns with three args:
+ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000)
+ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000)
+ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000)
+ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000)
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000)
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000)
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000)
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000)
+
+ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
+ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
+ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
+ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
+
+PPC altivec integer arith insns with two args:
+ vaddubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddubm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
+ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
+ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddubm: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000)
+
+ vadduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vadduhm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vadduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
+ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
+ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduhm: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000)
+
+ vadduwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vadduwm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vadduwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
+ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
+ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduwm: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000)
+
+ vaddubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddubs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000)
+ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000)
+ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddubs: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vadduhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vadduhs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vadduhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
+ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
+ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduhs: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vadduws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vadduws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vadduws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
+ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
+ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduws: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddsbs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
+ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
+ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddsbs: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000)
+
+ vaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddshs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
+ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
+ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddshs: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000)
+
+ vaddsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddsws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
+ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
+ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddsws: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000)
+
+ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddcuw: => 00000000 00000000 00000000 00000000 (00000000)
+ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000)
+ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000)
+ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddcuw: => 00000001 00000001 00000001 00000001 (00000000)
+
+ vsububm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsububm: => 00000000 00000000 00000000 00000000 (00000000)
+ vsububm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsububm: => 10101010 10101010 10101010 10101010 (00000000)
+ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsububm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsububm: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuhm: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000)
+ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubuhm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuwm: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000)
+ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubuwm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsububs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsububs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsububs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubuhs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubuws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubuws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubsbs: => 10101010 10101010 10101010 10101010 (00000000)
+ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubsbs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubshs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubshs: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000)
+ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubshs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubshs: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubsws: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubsws: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000)
+ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubsws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubsws: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
+ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubcuw: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
+ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
+
+ vmuloub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmuloub: => 00040010 00240040 00640090 00a900e1 (00000000)
+ vmuloub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000)
+ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000)
+ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuloub: => e4c4e890 ec64f040 f424f810 fa09fe01 (00000000)
+
+ vmulouh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulouh: => 00091810 00317040 007a0890 00c5a4e1 (00000000)
+ vmulouh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000)
+ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000)
+ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulouh: => e8792090 f0308040 f8082010 fdff0201 (00000000)
+
+ vmulosb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulosb: => 00040010 00240040 00640090 00a900e1 (00000000)
+ vmulosb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000)
+ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000)
+ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulosb: => 00c40090 00640040 00240010 00090001 (00000000)
+
+ vmulosh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulosh: => 00091810 00317040 007a0890 00c5a4e1 (00000000)
+ vmulosh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000)
+ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000)
+ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulosh: => 00912090 00408040 00102010 00010201 (00000000)
+
+ vmuleub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmuleub: => 00010009 00190031 00510079 00c400c4 (00000000)
+ vmuleub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000)
+ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000)
+ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuleub: => e2e1e6a9 ea79ee51 f231f619 fc04fc04 (00000000)
+
+ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmuleuh: => 00010404 00193c24 0051b464 00c56ca9 (00000000)
+ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000)
+ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000)
+ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuleuh: => e4a988c4 ec50c864 f4184824 fdfb0609 (00000000)
+
+ vmulesb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulesb: => 00010009 00190031 00510079 00c400c4 (00000000)
+ vmulesb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000)
+ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000)
+ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulesb: => 00e100a9 00790051 00310019 00040004 (00000000)
+
+ vmulesh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulesh: => 00010404 00193c24 0051b464 00c56ca9 (00000000)
+ vmulesh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000)
+ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000)
+ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulesh: => 00c588c4 0064c864 00244824 00010609 (00000000)
+
+ vsumsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsumsws: => 00000000 00000000 00000000 2b2c3136 (00000000)
+ vsumsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsumsws: => 00000000 00000000 00000000 1c1d2226 (00000000)
+ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsumsws: => 00000000 00000000 00000000 eeeff4f6 (00000000)
+ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsumsws: => 00000000 00000000 00000000 dfe0e5e6 (00000000)
+
+ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsum2sws: => 00000000 0b0e1114 00000000 2524272a (00000000)
+ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum2sws: => 00000000 fbff0204 00000000 1615181a (00000000)
+ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsum2sws: => 00000000 eceff2f4 00000000 0706090a (00000000)
+ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum2sws: => 00000000 dde0e3e4 00000000 f7f6f9fa (00000000)
+
+ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsum4ubs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000)
+ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4ubs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000)
+ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsum4ubs: => 010206ce 05060ae2 090a0ef6 0e0d1207 (00000000)
+ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4ubs: => f1f2f7be f5f6fbd2 f9faffe6 fefe02f7 (00000000)
+
+ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsum4sbs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000)
+ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4sbs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000)
+ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsum4sbs: => 010202ce 050606e2 090a0af6 0e0d0e07 (00000000)
+ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4sbs: => f1f2f3be f5f6f7d2 f9fafbe6 fefdfef7 (00000000)
+
+ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsum4shs: => 0102070a 05061316 090a1f22 0e0d2a2b (00000000)
+ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4shs: => f1f2f7fa f5f70406 f9fb1012 fefe1b1b (00000000)
+ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsum4shs: => 0101e8ea 0505f4f6 090a0102 0e0d0c0b (00000000)
+ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4shs: => f1f2d9da f5f6e5e6 f9faf1f2 fefdfcfb (00000000)
+
+ vavgub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavgub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavgub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavguh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavguh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavguh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavguh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavguw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavguw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavguw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavguw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavgsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavgsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavgsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000)
+ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000)
+ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavgsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavgsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavgsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000)
+ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000)
+ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavgsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavgsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavgsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000)
+ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000)
+ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+PPC altivec integer logical insns with two args:
+ vand: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vand: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vand: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vor: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vxor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vxor: => 00000000 00000000 00000000 00000000 (00000000)
+ vxor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vxor: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vandc: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vandc: => 00000000 00000000 00000000 00000000 (00000000)
+ vandc: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vandc: => 00000000 00000000 00000000 00000000 (00000000)
+ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vandc: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vandc: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vnor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vnor: => fefdfcfb faf9f8f7 f6f5f4f3 f1f2f1f0 (00000000)
+ vnor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
+ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
+ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
+
+ vrlb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000)
+ vrlb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000)
+ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000)
+ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000)
+
+ vrlh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000)
+ vrlh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000)
+ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000)
+ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000)
+
+ vrlw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vrlw: => 10203040 06070805 a0b0c090 87078706 (00000000)
+ vrlw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlw: => 30401020 08050607 c090a0b0 87068707 (00000000)
+ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vrlw: => 1f2f3f4f f6f7f8f5 afbfcf9f ff7fff7e (00000000)
+ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlw: => 3f4f1f2f f8f5f6f7 cf9fafbf ff7eff7f (00000000)
+
+ vslb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000)
+ vslb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000)
+ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000)
+ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000)
+
+ vslh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vslh: => 04083040 41800800 2800c000 a0008000 (00000000)
+ vslh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslh: => 04083040 41800800 2800c000 a0008000 (00000000)
+ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000)
+ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000)
+
+ vslw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vslw: => 10203040 06070800 a0b0c000 87078000 (00000000)
+ vslw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslw: => 30400000 08000000 c0000000 80000000 (00000000)
+ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vslw: => 1f2f3f40 f6f7f800 afbfc000 ff7f8000 (00000000)
+ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslw: => 3f400000 f8000000 c0000000 80000000 (00000000)
+
+ vsrb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrb: => 00000000 00000008 04020100 00000000 (00000000)
+ vsrb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrb: => 00000000 00000008 04020100 00000000 (00000000)
+ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000)
+ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000)
+
+ vsrh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrh: => 00400030 00140007 00020000 00000000 (00000000)
+ vsrh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrh: => 00400030 00140007 00020000 00000000 (00000000)
+ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000)
+ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000)
+
+ vsrw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrw: => 00102030 00050607 000090a0 00001c1a (00000000)
+ vsrw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrw: => 00000010 00000005 00000000 00000000 (00000000)
+ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrw: => 0f1f2f3f 00f5f6f7 000f9faf 0001fdfb (00000000)
+ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrw: => 00000f1f 000000f5 0000000f 00000001 (00000000)
+
+ vsrab: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrab: => 00000000 00000008 04020100 00000000 (00000000)
+ vsrab: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrab: => 00000000 00000008 04020100 00000000 (00000000)
+ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000)
+ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000)
+
+ vsrah: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrah: => 00400030 00140007 00020000 00000000 (00000000)
+ vsrah: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrah: => 00400030 00140007 00020000 00000000 (00000000)
+ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000)
+ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000)
+
+ vsraw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsraw: => 00102030 00050607 000090a0 00001c1a (00000000)
+ vsraw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsraw: => 00000010 00000005 00000000 00000000 (00000000)
+ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsraw: => ff1f2f3f fff5f6f7 ffff9faf fffffdfb (00000000)
+ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsraw: => ffffff1f fffffff5 ffffffff ffffffff (00000000)
+
+ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkuhum: => 02040608 0a0c0d0f 02040608 0a0c0d0f (00000000)
+ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuhum: => 02040608 0a0c0d0f f2f4f6f8 fafcfdff (00000000)
+ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkuhum: => f2f4f6f8 fafcfdff 02040608 0a0c0d0f (00000000)
+ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuhum: => f2f4f6f8 fafcfdff f2f4f6f8 fafcfdff (00000000)
+
+ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkuwum: => 03040708 0b0c0e0f 03040708 0b0c0e0f (00000000)
+ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuwum: => 03040708 0b0c0e0f f3f4f7f8 fbfcfeff (00000000)
+ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkuwum: => f3f4f7f8 fbfcfeff 03040708 0b0c0e0f (00000000)
+ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuwum: => f3f4f7f8 fbfcfeff f3f4f7f8 fbfcfeff (00000000)
+
+ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vpkshus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkshus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkshus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkshus: => ffffffff ffffffff 00000000 00000000 (00000000)
+ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkshus: => 00000000 00000000 ffffffff ffffffff (00000000)
+ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkshus: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vpkswus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkswus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkswus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkswus: => ffffffff ffffffff 00000000 00000000 (00000000)
+ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkswus: => 00000000 00000000 ffffffff ffffffff (00000000)
+ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkswus: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vpkshss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkshss: => 7f7f7f7f 7f7f7f7f 7f7f7f7f 7f7f7f7f (00000000)
+ vpkshss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkshss: => 7f7f7f7f 7f7f7f7f 80808080 80808080 (00000000)
+ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkshss: => 80808080 80808080 7f7f7f7f 7f7f7f7f (00000000)
+ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkshss: => 80808080 80808080 80808080 80808080 (00000000)
+
+ vpkswss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkswss: => 7fff7fff 7fff7fff 7fff7fff 7fff7fff (00000000)
+ vpkswss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkswss: => 7fff7fff 7fff7fff 80008000 80008000 (00000000)
+ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkswss: => 80008000 80008000 7fff7fff 7fff7fff (00000000)
+ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkswss: => 80008000 80008000 80008000 80008000 (00000000)
+
+ vpkpx: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkpx: => 80008001 84210421 80008001 84210421 (00000000)
+ vpkpx: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkpx: => 80008001 84210421 fbdefbdf ffff7fff (00000000)
+ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkpx: => fbdefbdf ffff7fff 80008001 84210421 (00000000)
+ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkpx: => fbdefbdf ffff7fff fbdefbdf ffff7fff (00000000)
+
+ vmrghb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrghb: => 01010202 03030404 05050606 07070808 (00000000)
+ vmrghb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghb: => 01f102f2 03f304f4 05f506f6 07f708f8 (00000000)
+ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrghb: => f101f202 f303f404 f505f606 f707f808 (00000000)
+ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghb: => f1f1f2f2 f3f3f4f4 f5f5f6f6 f7f7f8f8 (00000000)
+
+ vmrghh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrghh: => 01020102 03040304 05060506 07080708 (00000000)
+ vmrghh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghh: => 0102f1f2 0304f3f4 0506f5f6 0708f7f8 (00000000)
+ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrghh: => f1f20102 f3f40304 f5f60506 f7f80708 (00000000)
+ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghh: => f1f2f1f2 f3f4f3f4 f5f6f5f6 f7f8f7f8 (00000000)
+
+ vmrghw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrghw: => 01020304 01020304 05060708 05060708 (00000000)
+ vmrghw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghw: => 01020304 f1f2f3f4 05060708 f5f6f7f8 (00000000)
+ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrghw: => f1f2f3f4 01020304 f5f6f7f8 05060708 (00000000)
+ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghw: => f1f2f3f4 f1f2f3f4 f5f6f7f8 f5f6f7f8 (00000000)
+
+ vmrglb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrglb: => 09090a0a 0b0b0c0c 0e0e0d0d 0e0e0f0f (00000000)
+ vmrglb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglb: => 09f90afa 0bfb0cfc 0efe0dfd 0efe0fff (00000000)
+ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrglb: => f909fa0a fb0bfc0c fe0efd0d fe0eff0f (00000000)
+ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglb: => f9f9fafa fbfbfcfc fefefdfd fefeffff (00000000)
+
+ vmrglh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrglh: => 090a090a 0b0c0b0c 0e0d0e0d 0e0f0e0f (00000000)
+ vmrglh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglh: => 090af9fa 0b0cfbfc 0e0dfefd 0e0ffeff (00000000)
+ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrglh: => f9fa090a fbfc0b0c fefd0e0d feff0e0f (00000000)
+ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglh: => f9faf9fa fbfcfbfc fefdfefd fefffeff (00000000)
+
+ vmrglw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrglw: => 090a0b0c 090a0b0c 0e0d0e0f 0e0d0e0f (00000000)
+ vmrglw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglw: => 090a0b0c f9fafbfc 0e0d0e0f fefdfeff (00000000)
+ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrglw: => f9fafbfc 090a0b0c fefdfeff 0e0d0e0f (00000000)
+ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglw: => f9fafbfc f9fafbfc fefdfeff fefdfeff (00000000)
+
+ vslo: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vslo: => 02030405 06070809 0a0b0c0e 0d0e0f00 (00000000)
+ vslo: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslo: => 0f000000 00000000 00000000 00000000 (00000000)
+ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vslo: => f2f3f4f5 f6f7f8f9 fafbfcfe fdfeff00 (00000000)
+ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslo: => ff000000 00000000 00000000 00000000 (00000000)
+
+ vsro: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsro: => 00010203 04050607 08090a0b 0c0e0d0e (00000000)
+ vsro: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsro: => 00000000 00000000 00000000 00000001 (00000000)
+ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsro: => 00f1f2f3 f4f5f6f7 f8f9fafb fcfefdfe (00000000)
+ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsro: => 00000000 00000000 00000000 000000f1 (00000000)
+
+PPC altivec integer logical insns with one arg:
+ vupkhsb: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupkhsb: => 00010002 00030004 00050006 00070008 (00000000)
+ vupkhsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupkhsb: => fff1fff2 fff3fff4 fff5fff6 fff7fff8 (00000000)
+
+ vupkhsh: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupkhsh: => 00000102 00000304 00000506 00000708 (00000000)
+ vupkhsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupkhsh: => fffff1f2 fffff3f4 fffff5f6 fffff7f8 (00000000)
+
+ vupkhpx: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupkhpx: => 00000802 00001804 00010806 00011808 (00000000)
+ vupkhpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupkhpx: => ff1c0f12 ff1c1f14 ff1d0f16 ff1d1f18 (00000000)
+
+ vupklsb: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupklsb: => 0009000a 000b000c 000e000d 000e000f (00000000)
+ vupklsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupklsb: => fff9fffa fffbfffc fffefffd fffeffff (00000000)
+
+ vupklsh: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupklsh: => 0000090a 00000b0c 00000e0d 00000e0f (00000000)
+ vupklsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupklsh: => fffff9fa fffffbfc fffffefd fffffeff (00000000)
+
+ vupklpx: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupklpx: => 0002080a 0002180c 0003100d 0003100f (00000000)
+ vupklpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupklpx: => ff1e0f1a ff1e1f1c ff1f171d ff1f171f (00000000)
+
+Altivec integer compare insns:
+ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtub: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuh: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuw: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsb: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsh: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsw: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+Altivec integer compare insns with flags update:
+ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtub.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+
+ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+
+ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+
+Altivec integer special insns:
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000
+ vsl: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101
+ vsl: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202
+ vsl: => 04080c10 14181c20 24282c30 3834383c (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303
+ vsl: => 08101820 28303840 48505860 70687078 (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404
+ vsl: => 10203040 50607080 90a0b0c0 e0d0e0f0 (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505
+ vsl: => 20406080 a0c0e101 21416181 c1a1c1e0 (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606
+ vsl: => 4080c101 4181c202 4282c303 834383c0 (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707
+ vsl: => 81018202 83038404 85058607 06870780 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000
+ vsl: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101
+ vsl: => e3e5e7e9 ebedeff1 f3f5f7f9 fdfbfdfe (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202
+ vsl: => c7cbcfd3 d7dbdfe3 e7ebeff3 fbf7fbfc (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303
+ vsl: => 8f979fa7 afb7bfc7 cfd7dfe7 f7eff7f8 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404
+ vsl: => 1f2f3f4f 5f6f7f8f 9fafbfcf efdfeff0 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505
+ vsl: => 3e5e7e9e bedeff1f 3f5f7f9f dfbfdfe0 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606
+ vsl: => 7cbcfd3d 7dbdfe3e 7ebeff3f bf7fbfc0 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707
+ vsl: => f979fa7a fb7bfc7c fd7dfe7f 7eff7f80 (00000000)
+
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000
+ vsr: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101
+ vsr: => 00810182 02830384 04850586 07068707 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202
+ vsr: => 004080c1 014181c2 024282c3 03834383 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303
+ vsr: => 00204060 80a0c0e1 01214161 81c1a1c1 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404
+ vsr: => 00102030 40506070 8090a0b0 c0e0d0e0 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505
+ vsr: => 00081018 20283038 40485058 60706870 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606
+ vsr: => 0004080c 1014181c 2024282c 30383438 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707
+ vsr: => 00020406 080a0c0e 10121416 181c1a1c (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000
+ vsr: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101
+ vsr: => 78f979fa 7afb7bfc 7cfd7dfe 7f7eff7f (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202
+ vsr: => 3c7cbcfd 3d7dbdfe 3e7ebeff 3fbf7fbf (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303
+ vsr: => 1e3e5e7e 9ebedeff 1f3f5f7f 9fdfbfdf (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404
+ vsr: => 0f1f2f3f 4f5f6f7f 8f9fafbf cfefdfef (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505
+ vsr: => 078f979f a7afb7bf c7cfd7df e7f7eff7 (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606
+ vsr: => 03c7cbcf d3d7dbdf e3e7ebef f3fbf7fb (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707
+ vsr: => 01e3e5e7 e9ebedef f1f3f5f7 f9fdfbfd (00000000)
+
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 0
+ vspltb: => 01010101 01010101 01010101 01010101 (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 3
+ vspltb: => 04040404 04040404 04040404 04040404 (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 6
+ vspltb: => 07070707 07070707 07070707 07070707 (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 9
+ vspltb: => 0a0a0a0a 0a0a0a0a 0a0a0a0a 0a0a0a0a (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 12
+ vspltb: => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 15
+ vspltb: => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
+ vspltb: => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
+ vspltb: => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
+ vspltb: => f7f7f7f7 f7f7f7f7 f7f7f7f7 f7f7f7f7 (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
+ vspltb: => fafafafa fafafafa fafafafa fafafafa (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
+ vspltb: => fefefefe fefefefe fefefefe fefefefe (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
+ vspltb: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 0
+ vsplth: => 01020102 01020102 01020102 01020102 (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 3
+ vsplth: => 07080708 07080708 07080708 07080708 (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 6
+ vsplth: => 0e0d0e0d 0e0d0e0d 0e0d0e0d 0e0d0e0d (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 9
+ vsplth: => 03040304 03040304 03040304 03040304 (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 12
+ vsplth: => 090a090a 090a090a 090a090a 090a090a (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 15
+ vsplth: => 0e0f0e0f 0e0f0e0f 0e0f0e0f 0e0f0e0f (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
+ vsplth: => f1f2f1f2 f1f2f1f2 f1f2f1f2 f1f2f1f2 (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
+ vsplth: => f7f8f7f8 f7f8f7f8 f7f8f7f8 f7f8f7f8 (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
+ vsplth: => fefdfefd fefdfefd fefdfefd fefdfefd (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
+ vsplth: => f3f4f3f4 f3f4f3f4 f3f4f3f4 f3f4f3f4 (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
+ vsplth: => f9faf9fa f9faf9fa f9faf9fa f9faf9fa (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
+ vsplth: => fefffeff fefffeff fefffeff fefffeff (00000000)
+
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 0
+ vspltw: => 01020304 01020304 01020304 01020304 (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 3
+ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 6
+ vspltw: => 090a0b0c 090a0b0c 090a0b0c 090a0b0c (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 9
+ vspltw: => 05060708 05060708 05060708 05060708 (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 12
+ vspltw: => 01020304 01020304 01020304 01020304 (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 15
+ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
+ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
+ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
+ vspltw: => f9fafbfc f9fafbfc f9fafbfc f9fafbfc (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
+ vspltw: => f5f6f7f8 f5f6f7f8 f5f6f7f8 f5f6f7f8 (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
+ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
+ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000)
+
+ vspltisb: 0 => 00000000 00000000 00000000 00000000 (00000000)
+ vspltisb: 1 => 01010101 01010101 01010101 01010101 (00000000)
+ vspltisb: 2 => 02020202 02020202 02020202 02020202 (00000000)
+ vspltisb: 3 => 03030303 03030303 03030303 03030303 (00000000)
+ vspltisb: 4 => 04040404 04040404 04040404 04040404 (00000000)
+ vspltisb: 5 => 05050505 05050505 05050505 05050505 (00000000)
+ vspltisb: 6 => 06060606 06060606 06060606 06060606 (00000000)
+ vspltisb: 7 => 07070707 07070707 07070707 07070707 (00000000)
+ vspltisb: 8 => 08080808 08080808 08080808 08080808 (00000000)
+ vspltisb: 9 => 09090909 09090909 09090909 09090909 (00000000)
+ vspltisb: 10 => 0a0a0a0a 0a0a0a0a 0a0a0a0a 0a0a0a0a (00000000)
+ vspltisb: 11 => 0b0b0b0b 0b0b0b0b 0b0b0b0b 0b0b0b0b (00000000)
+ vspltisb: 12 => 0c0c0c0c 0c0c0c0c 0c0c0c0c 0c0c0c0c (00000000)
+ vspltisb: 13 => 0d0d0d0d 0d0d0d0d 0d0d0d0d 0d0d0d0d (00000000)
+ vspltisb: 14 => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000)
+ vspltisb: 15 => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000)
+ vspltisb: 16 => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vspltisb: 17 => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000)
+ vspltisb: 18 => f2f2f2f2 f2f2f2f2 f2f2f2f2 f2f2f2f2 (00000000)
+ vspltisb: 19 => f3f3f3f3 f3f3f3f3 f3f3f3f3 f3f3f3f3 (00000000)
+ vspltisb: 20 => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000)
+ vspltisb: 21 => f5f5f5f5 f5f5f5f5 f5f5f5f5 f5f5f5f5 (00000000)
+ vspltisb: 22 => f6f6f6f6 f6f6f6f6 f6f6f6f6 f6f6f6f6 (00000000)
+ vspltisb: 23 => f7f7f7f7 f7f7f7f7 f7f7f7f7 f7f7f7f7 (00000000)
+ vspltisb: 24 => f8f8f8f8 f8f8f8f8 f8f8f8f8 f8f8f8f8 (00000000)
+ vspltisb: 25 => f9f9f9f9 f9f9f9f9 f9f9f9f9 f9f9f9f9 (00000000)
+ vspltisb: 26 => fafafafa fafafafa fafafafa fafafafa (00000000)
+ vspltisb: 27 => fbfbfbfb fbfbfbfb fbfbfbfb fbfbfbfb (00000000)
+ vspltisb: 28 => fcfcfcfc fcfcfcfc fcfcfcfc fcfcfcfc (00000000)
+ vspltisb: 29 => fdfdfdfd fdfdfdfd fdfdfdfd fdfdfdfd (00000000)
+ vspltisb: 30 => fefefefe fefefefe fefefefe fefefefe (00000000)
+ vspltisb: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vspltish: 0 => 00000000 00000000 00000000 00000000 (00000000)
+ vspltish: 1 => 00010001 00010001 00010001 00010001 (00000000)
+ vspltish: 2 => 00020002 00020002 00020002 00020002 (00000000)
+ vspltish: 3 => 00030003 00030003 00030003 00030003 (00000000)
+ vspltish: 4 => 00040004 00040004 00040004 00040004 (00000000)
+ vspltish: 5 => 00050005 00050005 00050005 00050005 (00000000)
+ vspltish: 6 => 00060006 00060006 00060006 00060006 (00000000)
+ vspltish: 7 => 00070007 00070007 00070007 00070007 (00000000)
+ vspltish: 8 => 00080008 00080008 00080008 00080008 (00000000)
+ vspltish: 9 => 00090009 00090009 00090009 00090009 (00000000)
+ vspltish: 10 => 000a000a 000a000a 000a000a 000a000a (00000000)
+ vspltish: 11 => 000b000b 000b000b 000b000b 000b000b (00000000)
+ vspltish: 12 => 000c000c 000c000c 000c000c 000c000c (00000000)
+ vspltish: 13 => 000d000d 000d000d 000d000d 000d000d (00000000)
+ vspltish: 14 => 000e000e 000e000e 000e000e 000e000e (00000000)
+ vspltish: 15 => 000f000f 000f000f 000f000f 000f000f (00000000)
+ vspltish: 16 => fff0fff0 fff0fff0 fff0fff0 fff0fff0 (00000000)
+ vspltish: 17 => fff1fff1 fff1fff1 fff1fff1 fff1fff1 (00000000)
+ vspltish: 18 => fff2fff2 fff2fff2 fff2fff2 fff2fff2 (00000000)
+ vspltish: 19 => fff3fff3 fff3fff3 fff3fff3 fff3fff3 (00000000)
+ vspltish: 20 => fff4fff4 fff4fff4 fff4fff4 fff4fff4 (00000000)
+ vspltish: 21 => fff5fff5 fff5fff5 fff5fff5 fff5fff5 (00000000)
+ vspltish: 22 => fff6fff6 fff6fff6 fff6fff6 fff6fff6 (00000000)
+ vspltish: 23 => fff7fff7 fff7fff7 fff7fff7 fff7fff7 (00000000)
+ vspltish: 24 => fff8fff8 fff8fff8 fff8fff8 fff8fff8 (00000000)
+ vspltish: 25 => fff9fff9 fff9fff9 fff9fff9 fff9fff9 (00000000)
+ vspltish: 26 => fffafffa fffafffa fffafffa fffafffa (00000000)
+ vspltish: 27 => fffbfffb fffbfffb fffbfffb fffbfffb (00000000)
+ vspltish: 28 => fffcfffc fffcfffc fffcfffc fffcfffc (00000000)
+ vspltish: 29 => fffdfffd fffdfffd fffdfffd fffdfffd (00000000)
+ vspltish: 30 => fffefffe fffefffe fffefffe fffefffe (00000000)
+ vspltish: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vspltisw: 0 => 00000000 00000000 00000000 00000000 (00000000)
+ vspltisw: 1 => 00000001 00000001 00000001 00000001 (00000000)
+ vspltisw: 2 => 00000002 00000002 00000002 00000002 (00000000)
+ vspltisw: 3 => 00000003 00000003 00000003 00000003 (00000000)
+ vspltisw: 4 => 00000004 00000004 00000004 00000004 (00000000)
+ vspltisw: 5 => 00000005 00000005 00000005 00000005 (00000000)
+ vspltisw: 6 => 00000006 00000006 00000006 00000006 (00000000)
+ vspltisw: 7 => 00000007 00000007 00000007 00000007 (00000000)
+ vspltisw: 8 => 00000008 00000008 00000008 00000008 (00000000)
+ vspltisw: 9 => 00000009 00000009 00000009 00000009 (00000000)
+ vspltisw: 10 => 0000000a 0000000a 0000000a 0000000a (00000000)
+ vspltisw: 11 => 0000000b 0000000b 0000000b 0000000b (00000000)
+ vspltisw: 12 => 0000000c 0000000c 0000000c 0000000c (00000000)
+ vspltisw: 13 => 0000000d 0000000d 0000000d 0000000d (00000000)
+ vspltisw: 14 => 0000000e 0000000e 0000000e 0000000e (00000000)
+ vspltisw: 15 => 0000000f 0000000f 0000000f 0000000f (00000000)
+ vspltisw: 16 => fffffff0 fffffff0 fffffff0 fffffff0 (00000000)
+ vspltisw: 17 => fffffff1 fffffff1 fffffff1 fffffff1 (00000000)
+ vspltisw: 18 => fffffff2 fffffff2 fffffff2 fffffff2 (00000000)
+ vspltisw: 19 => fffffff3 fffffff3 fffffff3 fffffff3 (00000000)
+ vspltisw: 20 => fffffff4 fffffff4 fffffff4 fffffff4 (00000000)
+ vspltisw: 21 => fffffff5 fffffff5 fffffff5 fffffff5 (00000000)
+ vspltisw: 22 => fffffff6 fffffff6 fffffff6 fffffff6 (00000000)
+ vspltisw: 23 => fffffff7 fffffff7 fffffff7 fffffff7 (00000000)
+ vspltisw: 24 => fffffff8 fffffff8 fffffff8 fffffff8 (00000000)
+ vspltisw: 25 => fffffff9 fffffff9 fffffff9 fffffff9 (00000000)
+ vspltisw: 26 => fffffffa fffffffa fffffffa fffffffa (00000000)
+ vspltisw: 27 => fffffffb fffffffb fffffffb fffffffb (00000000)
+ vspltisw: 28 => fffffffc fffffffc fffffffc fffffffc (00000000)
+ vspltisw: 29 => fffffffd fffffffd fffffffd fffffffd (00000000)
+ vspltisw: 30 => fffffffe fffffffe fffffffe fffffffe (00000000)
+ vspltisw: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0
+ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000)
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 14
+ vsldoi: => 0e0f0102 03040506 0708090a 0b0c0e0d] (00000000)
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0
+ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000)
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
+ vsldoi: => 0e0ff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0
+ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000)
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 14
+ vsldoi: => feff0102 03040506 0708090a 0b0c0e0d] (00000000)
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0
+ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000)
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
+ vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
+
+ lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+ lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
+ lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+ lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
+ lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
+ lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
+ lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
+ lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
+ lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
+ lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
+ lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
+ lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
+ lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
+ lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
+ lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
+ lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
+ lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+ lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
+
+ lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+ lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
+ lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+ lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
+ lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
+ lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
+ lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
+ lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
+ lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
+ lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
+ lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
+ lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
+ lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
+ lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
+ lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
+ lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
+ lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+ lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
+
+Altivec load insns with two register args:
+ lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
+ lvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000008 00000000 00000000 (00000000)
+ lvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 00000e00 (00000000)
+ lvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1000000 00000000 00000000 00000000 (00000000)
+ lvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 000000f8 00000000 00000000 (00000000)
+ lvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 0000fe00 (00000000)
+
+ lvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020000 00000000 00000000 00000000 (00000000)
+ lvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000708 00000000 00000000 (00000000)
+ lvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 00000e0f (00000000)
+ lvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f20000 00000000 00000000 00000000 (00000000)
+ lvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 0000f7f8 00000000 00000000 (00000000)
+ lvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 0000feff (00000000)
+
+ lvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000)
+ lvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05060708 00000000 00000000 (00000000)
+ lvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 0e0d0e0f (00000000)
+ lvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000)
+ lvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5f6f7f8 00000000 00000000 (00000000)
+ lvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 fefdfeff (00000000)
+
+ lvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ lvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ lvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ lvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ lvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ lvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+Altivec store insns with three register args:
+ stvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
+ stvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000008 00000000 00000000 (00000000)
+ stvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000008 00000000 00000e00 (00000000)
+ stvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1000000 00000000 00000000 00000000 (00000000)
+ stvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1000000 000000f8 00000000 00000000 (00000000)
+ stvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1000000 000000f8 00000000 0000fe00 (00000000)
+
+ stvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020000 00000000 00000000 00000000 (00000000)
+ stvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020000 00000708 00000000 00000000 (00000000)
+ stvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020000 00000708 00000000 00000e0f (00000000)
+ stvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f20000 00000000 00000000 00000000 (00000000)
+ stvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f20000 0000f7f8 00000000 00000000 (00000000)
+ stvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f20000 0000f7f8 00000000 0000feff (00000000)
+
+ stvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000)
+ stvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 00000000 (00000000)
+ stvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 0e0d0e0f (00000000)
+ stvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000)
+ stvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 00000000 (00000000)
+ stvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 fefdfeff (00000000)
+
+ stvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ stvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ stvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ stvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ stvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ stvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+Altivec floating point arith insns with two args:
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 033fffff 033fffff 033fffff 033fffff (00000000)
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d1bfffff d1bfffff d1bfffff d1bfffff (00000000)
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 51bfffff 51bfffff 51bfffff 51bfffff (00000000)
+ vsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 833fffff 833fffff 833fffff 833fffff (00000000)
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vmaxfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vmaxfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaxfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vmaxfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vmaxfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vminfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vminfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vminfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vminfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vminfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vminfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vminfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vminfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vminfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vminfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vminfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vminfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vminfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vminfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+Altivec floating point arith insns with three args:
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+
+Altivec floating point arith insns with one arg:
+ vrfin: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrfin: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfin: 513fffff 513fffff 513fffff 513fffff
+ vrfin: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vrfin: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrfin: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfin: d13fffff d13fffff d13fffff d13fffff
+ vrfin: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vrfin: 00000000 00000000 00000000 00000000
+ vrfin: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfin: 80000000 80000000 80000000 80000000
+ vrfin: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfin: 7f800000 7f800000 7f800000 7f800000
+ vrfin: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrfin: ff800000 ff800000 ff800000 ff800000
+ vrfin: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrfin: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfin: ffffffff ffffffff ffffffff ffffffff
+ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vrfin: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfin: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vrfiz: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrfiz: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfiz: 513fffff 513fffff 513fffff 513fffff
+ vrfiz: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vrfiz: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrfiz: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfiz: d13fffff d13fffff d13fffff d13fffff
+ vrfiz: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vrfiz: 00000000 00000000 00000000 00000000
+ vrfiz: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfiz: 80000000 80000000 80000000 80000000
+ vrfiz: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfiz: 7f800000 7f800000 7f800000 7f800000
+ vrfiz: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrfiz: ff800000 ff800000 ff800000 ff800000
+ vrfiz: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrfiz: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfiz: ffffffff ffffffff ffffffff ffffffff
+ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vrfiz: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfiz: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vrfip: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrfip: => 3f800000 3f800000 3f800000 3f800000 (00000000)
+ vrfip: 513fffff 513fffff 513fffff 513fffff
+ vrfip: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vrfip: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrfip: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfip: d13fffff d13fffff d13fffff d13fffff
+ vrfip: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vrfip: 00000000 00000000 00000000 00000000
+ vrfip: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfip: 80000000 80000000 80000000 80000000
+ vrfip: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfip: 7f800000 7f800000 7f800000 7f800000
+ vrfip: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrfip: ff800000 ff800000 ff800000 ff800000
+ vrfip: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrfip: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfip: ffffffff ffffffff ffffffff ffffffff
+ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vrfip: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfip: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vrfim: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrfim: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfim: 513fffff 513fffff 513fffff 513fffff
+ vrfim: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vrfim: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrfim: => bf800000 bf800000 bf800000 bf800000 (00000000)
+ vrfim: d13fffff d13fffff d13fffff d13fffff
+ vrfim: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vrfim: 00000000 00000000 00000000 00000000
+ vrfim: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfim: 80000000 80000000 80000000 80000000
+ vrfim: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfim: 7f800000 7f800000 7f800000 7f800000
+ vrfim: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrfim: ff800000 ff800000 ff800000 ff800000
+ vrfim: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrfim: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfim: ffffffff ffffffff ffffffff ffffffff
+ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vrfim: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfim: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vrefp: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrefp: => 7c2a8000 7c2a8000 7c2a8000 7c2a8000 (00000000)
+ vrefp: 513fffff 513fffff 513fffff 513fffff
+ vrefp: => 2daa8000 2daa8000 2daa8000 2daa8000 (00000000)
+ vrefp: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrefp: => fc2a8000 fc2a8000 fc2a8000 fc2a8000 (00000000)
+ vrefp: d13fffff d13fffff d13fffff d13fffff
+ vrefp: => adaa8000 adaa8000 adaa8000 adaa8000 (00000000)
+ vrefp: 00000000 00000000 00000000 00000000
+ vrefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrefp: 80000000 80000000 80000000 80000000
+ vrefp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrefp: 7f800000 7f800000 7f800000 7f800000
+ vrefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vrefp: ff800000 ff800000 ff800000 ff800000
+ vrefp: => 80000000 80000000 80000000 80000000 (00000000)
+ vrefp: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
+ vrefp: ffffffff ffffffff ffffffff ffffffff
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
+ vrefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
+ vrefp: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
+
+ vrsqrtefp: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrsqrtefp: => 5dd10000 5dd10000 5dd10000 5dd10000 (00000000)
+ vrsqrtefp: 513fffff 513fffff 513fffff 513fffff
+ vrsqrtefp: => 3693c000 3693c000 3693c000 3693c000 (00000000)
+ vrsqrtefp: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vrsqrtefp: d13fffff d13fffff d13fffff d13fffff
+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vrsqrtefp: 00000000 00000000 00000000 00000000
+ vrsqrtefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrsqrtefp: 80000000 80000000 80000000 80000000
+ vrsqrtefp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrsqrtefp: 7f800000 7f800000 7f800000 7f800000
+ vrsqrtefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vrsqrtefp: ff800000 ff800000 ff800000 ff800000
+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vrsqrtefp: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
+ vrsqrtefp: ffffffff ffffffff ffffffff ffffffff
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
+ vrsqrtefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
+ vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
+
+Altivec floating point compare insns:
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+
+Altivec floating point compare insns with flags update:
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+
+Altivec float special insns:
+ vcfux: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
+ vcfux: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
+ vcfux: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000)
+ vcfux: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000)
+ vcfux: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000)
+ vcfux: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000)
+ vcfux: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000)
+ vcfux: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000)
+ vcfux: 82bfffff (-2.821186e-37), 0 => 4f02c000 ( 2.193621e+09) (00000000)
+ vcfux: 82bfffff (-2.821186e-37), 9 => 4a82c000 ( 4.284416e+06) (00000000)
+ vcfux: 82bfffff (-2.821186e-37), 18 => 4602c000 ( 8.368000e+03) (00000000)
+ vcfux: 82bfffff (-2.821186e-37), 27 => 4182c000 ( 1.634375e+01) (00000000)
+ vcfux: d13fffff (-5.153960e+10), 0 => 4f514000 ( 3.510632e+09) (00000000)
+ vcfux: d13fffff (-5.153960e+10), 9 => 4ad14000 ( 6.856704e+06) (00000000)
+ vcfux: d13fffff (-5.153960e+10), 18 => 46514000 ( 1.339200e+04) (00000000)
+ vcfux: d13fffff (-5.153960e+10), 27 => 41d14000 ( 2.615625e+01) (00000000)
+ vcfux: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vcfux: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vcfux: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vcfux: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vcfux: 80000000 (-0.000000e+00), 0 => 4f000000 ( 2.147484e+09) (00000000)
+ vcfux: 80000000 (-0.000000e+00), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfux: 80000000 (-0.000000e+00), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfux: 80000000 (-0.000000e+00), 27 => 41800000 ( 1.600000e+01) (00000000)
+ vcfux: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000)
+ vcfux: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000)
+ vcfux: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000)
+ vcfux: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000)
+ vcfux: ff800000 ( -inf), 0 => 4f7f8000 ( 4.286579e+09) (00000000)
+ vcfux: ff800000 ( -inf), 9 => 4aff8000 ( 8.372224e+06) (00000000)
+ vcfux: ff800000 ( -inf), 18 => 467f8000 ( 1.635200e+04) (00000000)
+ vcfux: ff800000 ( -inf), 27 => 41ff8000 ( 3.193750e+01) (00000000)
+ vcfux: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000)
+ vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
+ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
+ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
+ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
+ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
+ vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
+ vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
+ vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
+ vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
+ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
+ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
+ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
+ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
+
+ vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
+ vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
+ vcfsx: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000)
+ vcfsx: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000)
+ vcfsx: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000)
+ vcfsx: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000)
+ vcfsx: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000)
+ vcfsx: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000)
+ vcfsx: 82bfffff (-2.821186e-37), 0 => cefa8000 (-2.101346e+09) (00000000)
+ vcfsx: 82bfffff (-2.821186e-37), 9 => ca7a8000 (-4.104192e+06) (00000000)
+ vcfsx: 82bfffff (-2.821186e-37), 18 => c5fa8000 (-8.016000e+03) (00000000)
+ vcfsx: 82bfffff (-2.821186e-37), 27 => c17a8000 (-1.565625e+01) (00000000)
+ vcfsx: d13fffff (-5.153960e+10), 0 => ce3b0000 (-7.843348e+08) (00000000)
+ vcfsx: d13fffff (-5.153960e+10), 9 => c9bb0000 (-1.531904e+06) (00000000)
+ vcfsx: d13fffff (-5.153960e+10), 18 => c53b0000 (-2.992000e+03) (00000000)
+ vcfsx: d13fffff (-5.153960e+10), 27 => c0bb0000 (-5.843750e+00) (00000000)
+ vcfsx: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vcfsx: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vcfsx: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vcfsx: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vcfsx: 80000000 (-0.000000e+00), 0 => cf000000 (-2.147484e+09) (00000000)
+ vcfsx: 80000000 (-0.000000e+00), 9 => ca800000 (-4.194304e+06) (00000000)
+ vcfsx: 80000000 (-0.000000e+00), 18 => c6000000 (-8.192000e+03) (00000000)
+ vcfsx: 80000000 (-0.000000e+00), 27 => c1800000 (-1.600000e+01) (00000000)
+ vcfsx: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000)
+ vcfsx: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000)
+ vcfsx: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000)
+ vcfsx: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000)
+ vcfsx: ff800000 ( -inf), 0 => cb000000 (-8.388608e+06) (00000000)
+ vcfsx: ff800000 ( -inf), 9 => c6800000 (-1.638400e+04) (00000000)
+ vcfsx: ff800000 ( -inf), 18 => c2000000 (-3.200000e+01) (00000000)
+ vcfsx: ff800000 ( -inf), 27 => bd800000 (-6.250000e-02) (00000000)
+ vcfsx: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000)
+ vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
+ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
+ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
+ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
+ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
+ vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
+ vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
+ vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
+ vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
+ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
+ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
+ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
+ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
+
+ vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
+ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
+ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
+ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: d13fffff (-5.153960e+10), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: d13fffff (-5.153960e+10), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: d13fffff (-5.153960e+10), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: d13fffff (-5.153960e+10), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
+ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
+ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
+ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
+ vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+
+ vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 513fffff ( 5.153960e+10), 0 => 7fffffff ( nan) (00000000)
+ vctsxs: 513fffff ( 5.153960e+10), 9 => 7fffffff ( nan) (00000000)
+ vctsxs: 513fffff ( 5.153960e+10), 18 => 7fffffff ( nan) (00000000)
+ vctsxs: 513fffff ( 5.153960e+10), 27 => 7fffffff ( nan) (00000000)
+ vctsxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: d13fffff (-5.153960e+10), 0 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: d13fffff (-5.153960e+10), 9 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: d13fffff (-5.153960e+10), 18 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: d13fffff (-5.153960e+10), 27 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7f800000 ( inf), 0 => 7fffffff ( nan) (00000000)
+ vctsxs: 7f800000 ( inf), 9 => 7fffffff ( nan) (00000000)
+ vctsxs: 7f800000 ( inf), 18 => 7fffffff ( nan) (00000000)
+ vctsxs: 7f800000 ( inf), 27 => 7fffffff ( nan) (00000000)
+ vctsxs: ff800000 ( -inf), 0 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: ff800000 ( -inf), 9 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: ff800000 ( -inf), 18 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: ff800000 ( -inf), 27 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+
+All done. Tested 165 different instructions
diff --git a/main/none/tests/ppc32/power5+_round.c b/main/none/tests/ppc32/power5+_round.c
index d6f6bc3..b11e67b 100644
--- a/main/none/tests/ppc32/power5+_round.c
+++ b/main/none/tests/ppc32/power5+_round.c
@@ -86,25 +86,11 @@
double friz[] = { inf, 1.0, 1.0, 0, neg0, -1.0, -1.0, -inf, nan };
double frip[] = { inf, 2.0, 2.0, 0, neg0, -1.0, -1.0, -inf, nan };
double frim[] = { inf, 1.0, 1.0, 0, neg0, -2.0, -2.0, -inf, nan };
- int fprf[] = { POS_INF, POS_NORMAL, POS_NORMAL, POS_ZERO, NEG_ZERO,
- NEG_NORMAL, NEG_NORMAL, NEG_INF, NAN
- };
double set2[] = { 0.9, 0.1, -0.1, -0.9, 1e-40, -1e-40 };
double frin2[] = { 1.0, 0.0, -0.0, -1.0, 0.0, -0.0 };
- int frin2rf[] =
- { POS_NORMAL, POS_ZERO, NEG_ZERO, NEG_NORMAL, POS_ZERO,
- NEG_ZERO };
double friz2[] = { 0.0, 0.0, -0.0, -0.0, 0.0, -0.0 };
- int friz2rf[] =
- { POS_ZERO, POS_ZERO, NEG_ZERO, NEG_ZERO, POS_ZERO, NEG_ZERO };
double frip2[] = { 1.0, 1.0, -0.0, -0.0, 1.0, -0.0 };
- int frip2rf[] =
- { POS_NORMAL, POS_NORMAL, NEG_ZERO, NEG_ZERO, POS_NORMAL,
- NEG_ZERO };
double frim2[] = { 0.0, 0.0, -1.0, -1.0, 0.0, -1.0 };
- int frim2rf[] =
- { POS_ZERO, POS_ZERO, NEG_NORMAL, NEG_NORMAL, POS_ZERO,
- NEG_NORMAL };
double ret;
int i;
@@ -136,26 +122,15 @@
double set1[] = { inf, 0.9, 0.1, 0, neg0, -0.1, -0.9, -inf, nan };
double frsp1[] =
{ inf, 0.9f, 0.1f, 0, neg0, -0.1f, -0.9f, -inf, nan };
- int fprf1[] =
- { POS_INF, POS_NORMAL, POS_NORMAL, POS_ZERO, NEG_ZERO,
- NEG_NORMAL,
- NEG_NORMAL, NEG_INF, NAN
- };
double set2[] =
{ 1.2e-38, 1.1e-38, 1e-40, 8e-44, 9e-44, 8e-46, 7e-46 };
double frsp2[] =
{ 1.2e-38f, 1.1e-38f, 1e-40f, 8e-44f, 9e-44f, 8e-46f, 0.0 };
- int fprf2[] = { POS_NORMAL, POS_DENORMAL, POS_DENORMAL, POS_DENORMAL,
- POS_DENORMAL, POS_DENORMAL, POS_ZERO
- };
double set3[] =
{ -1.2e-38, -1.1e-38, -1e-40, -8e-44, -9e-44, -8e-46, -7e-46 };
double frsp3[] =
{ -1.2e-38f, -1.1e-38f, -1e-40f, -8e-44f, -9e-44f, -8e-46f,
-0.0 };
- int fprf3[] = { NEG_NORMAL, NEG_DENORMAL, NEG_DENORMAL, NEG_DENORMAL,
- NEG_DENORMAL, NEG_DENORMAL, NEG_ZERO
- };
double ret;
int i;
DO_TEST(frsp, set1, frsp1, fprf1);
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/none/tests/ppc32/power6_bcmp.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/none/tests/ppc32/power6_bcmp.stdout.exp
diff --git a/main/none/tests/ppc32/round.c b/main/none/tests/ppc32/round.c
index f49c0b5..dd2bef6 100644
--- a/main/none/tests/ppc32/round.c
+++ b/main/none/tests/ppc32/round.c
@@ -142,7 +142,6 @@
int status = 0;
flt_overlay R, E;
char *result;
- char *eq_ne;
set_rounding_mode(mode);
@@ -153,11 +152,9 @@
(R.layout.exp != E.layout.exp) ||
(R.layout.frac != E.layout.frac)) {
result = "FAILED";
- eq_ne = "!=";
status = 1;
} else {
result = "PASSED";
- eq_ne = "==";
status = 0;
}
printf("%s:%s:(double)(%-20a) = %20a",
diff --git a/main/none/tests/ppc32/test_dfp1.c b/main/none/tests/ppc32/test_dfp1.c
new file mode 100644
index 0000000..40c3a10
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp1.c
@@ -0,0 +1,504 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+static Bool do_dot;
+static void _test_dadd (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dadd. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dadd %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dsub (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dsub. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dsub %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dmul (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dmul. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dmul %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_ddiv (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("ddiv. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("ddiv %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+// Quad DFP arith instructions
+static void _test_daddq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("daddq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("daddq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dsubq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dsubq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dsubq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dmulq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dmulq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dmulq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_ddivq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("ddivq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("ddivq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_mffs (void)
+{
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14));
+}
+
+static void _test_mtfsf (int upper)
+{
+ if (upper)
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) );
+ else
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 0" : : "f"(f14) );
+}
+
+typedef void (*test_func_t)(void);
+typedef struct test_table
+{
+ test_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals or dfp128_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x2[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 8},
+ {7, 1},
+ {9, 15},
+ {8, 12},
+ {7, 11},
+ {13, 2},
+ {13, 14},
+ {15, 12},
+ {14, 11},
+ {12, 12},
+ {12, 11},
+ {11, 11}
+};
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+ Bool cr_supported;
+} dfp_test_t;
+
+
+static dfp_test_t
+dfp_two_arg_tests[] = {
+ { &_test_dadd, "dadd", dfp_2args_x1, 25, LONG_TEST, "+", False},
+ { &_test_dsub, "dsub", dfp_2args_x1, 25, LONG_TEST, "-", False},
+ { &_test_dmul, "dmul", dfp_2args_x2, 19, LONG_TEST, "*", False},
+ { &_test_ddiv, "ddiv", dfp_2args_x2, 19, LONG_TEST, "/", False},
+ { &_test_daddq, "daddq", dfp_2args_x1, 25, QUAD_TEST, "+", False},
+ { &_test_dsubq, "dsubq", dfp_2args_x1, 25, QUAD_TEST, "-", False},
+ { &_test_dmulq, "dmulq", dfp_2args_x2, 19, QUAD_TEST, "*", False},
+ { &_test_ddivq, "ddivq", dfp_2args_x2, 19, QUAD_TEST, "/", False},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_two_arg_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double res, d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ int k = 0;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_two_arg_tests[k].test_func)) {
+ int i, repeat = 1;
+ dfp_test_t test_group = dfp_two_arg_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_group.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_group.targs[i].fra_idx];
+ u1 = dfp64_vals[test_group.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_group.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_group.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_group.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ res = f18;
+
+ condreg = (flags & 0x000000f0) >> 4;
+ printf("%s%s %016llx", test_group.name, do_dot? "." : "", u0);
+ if (test_group.precision == LONG_TEST) {
+ printf(" %s %016llx => %016llx",
+ test_group.op, u1, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx %s %016llx %016llx ==> %016llx %016llx",
+ u0x, test_group.op, u1, u1x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ if (test_group.cr_supported)
+ printf(" (cr = %08x)\n", condreg);
+ else
+ printf("\n");
+
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+void test_move_toFrom_fpscr(void)
+{
+#define BFP_MAX_RM 3
+ int shift = 0;
+ unsigned long long i, max_rm, expected_val;
+ double fpscr_in, fpscr_out;
+ unsigned long long * hex_fpscr_in = (unsigned long long *)&fpscr_in;
+ unsigned long long * hex_fpscr_out = (unsigned long long *)&fpscr_out;
+
+
+ max_rm = 4;
+again:
+ /* NOTE: The first time through this loop is for setting the binary
+ * floating point rounding mode (bits 62:63 of FPSCR). The second time
+ * through is for setting the decimal floating point rounding mode
+ * (bits 29:31 of FPSCR). In the second time through this loop, the value
+ * returned should include the final binary FP rounding mode, along with
+ * the decimal FP rounding modes.
+ */
+ for (i = 0; i < max_rm; i++) {
+ *hex_fpscr_in = (i << shift);
+ f14 = fpscr_in;
+ _test_mtfsf(max_rm/8);
+ *hex_fpscr_in = 0ULL;
+ f14= fpscr_in;
+ _test_mffs();
+ fpscr_out = f14;
+ if (max_rm == 4) {
+ *hex_fpscr_out &= (max_rm - 1) << shift;
+ expected_val = i << shift;
+ } else {
+ *hex_fpscr_out &= BFP_MAX_RM | ((max_rm - 1) << shift);
+ expected_val = (i << shift) | BFP_MAX_RM;
+ }
+
+ printf("FPSCR %s floating point rounding mode %016llx == %016llx? %s\n",
+ (max_rm == 8) ? "decimal" : "binary",
+ *hex_fpscr_out, expected_val,
+ (expected_val == *hex_fpscr_out) ? "yes" : "no");
+ }
+ if (max_rm == 4) {
+ max_rm = 8;
+ shift = 32;
+ goto again;
+ }
+}
+
+void test_rounding_modes(void)
+{
+ int j;
+ unsigned long long u0, u1, rm_idx;
+ double res, d0, d1, *d0p, *d1p, fpscr;
+ unsigned long long * hex_fpscr = (unsigned long long *)&fpscr;
+ u0 = 0x26cc3f1f534acdd4ULL;
+ u1 = 0x27feff197a42ba06ULL;
+ d0p = &d0;
+ d1p = &d1;
+
+ for (j = 0; j < 12; j++) {
+ for (rm_idx = 0; rm_idx < 8; rm_idx++) {
+ *hex_fpscr = 0ULL;
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14));
+ fpscr = f14;
+ *hex_fpscr &= 0xFFFFFFF0FFFFFFFFULL;
+ *hex_fpscr |= (rm_idx << 32);
+ f14 = fpscr;
+ SET_FPSCR_DRN;
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ _test_dmul();
+ res = f18;
+ printf("test #%d: dmul with rounding mode %d: %016llx * %016llx => %016llx\n",
+ j, (int)rm_idx, u0, u1, *((unsigned long long *)(&res)));
+ printf("\n");
+ }
+ // Changing the least significant bit of one of the dmul arguments give us more
+ // opportunities for different rounding modes to yield different results which
+ // can then be validated.
+ u0++;
+ }
+}
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_two_arg_ops,
+ "Test DFP arithmetic instructions"},
+ { &test_rounding_modes,
+ "Test DFP rounding modes"},
+ { &test_move_toFrom_fpscr,
+ "Test move to/from FPSCR"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc32/test_dfp1.stderr.exp b/main/none/tests/ppc32/test_dfp1.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp1.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc32/test_dfp1.stdout.exp b/main/none/tests/ppc32/test_dfp1.stdout.exp
new file mode 100644
index 0000000..614895d
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp1.stdout.exp
@@ -0,0 +1,583 @@
+Test DFP arithmetic instructions
+dadd 2234000000000e50 + 223400000014c000 => 223400000014ce50
+dadd a2340000000000e0 + 223400000014c000 => 223400000014a44c
+dadd 22240000000000cf + a21400010a395bcf => a21400010a1b9bcf
+dadd 2234000000000e50 + 000400000089b000 => 2e06500000000000
+dadd a2340000000000e0 + a21400010a395bcf => a21400080a395bcf
+dadd 6e4d3f1f534acdd4 + 223400000014c000 => 6e4d3f1f534acdd5
+dadd 6e4d3f1f534acdd4 + a2340000000000e0 => 6e4d3f1f534acdd4
+dadd 2238000000000000 + 223400000014c000 => 223400000014c000
+dadd 2238000000000000 + a2340000000000e0 => a2340000000000e0
+dadd a238000000000000 + 2234000000000e50 => 2234000000000e50
+dadd a238000000000000 + 223400000014c000 => 223400000014c000
+dadd a238000000000000 + a2340000000000e0 => a2340000000000e0
+dadd 2238000000000000 + a238000000000000 => 2238000000000000
+dadd fc00000000000000 + f800000000000000 => fc00000000000000
+dadd fc00000000000000 + 223400000014c000 => fc00000000000000
+dadd fc00000000000000 + 7800000000000000 => fc00000000000000
+dadd fc00000000000000 + fc00000000000000 => fc00000000000000
+dadd fc00000000000000 + fe000000d0e0a0d0 => fc000000d0e0a0d0
+dadd fe000000d0e0a0d0 + f800000000000000 => fc000000d0e0a0d0
+dadd fe000000d0e0a0d0 + 2234000000000e50 => fc000000d0e0a0d0
+dadd fe000000d0e0a0d0 + 7800000000000000 => fc000000d0e0a0d0
+dadd fe000000d0e0a0d0 + fe000000d0e0a0d0 => fc000000d0e0a0d0
+dadd f800000000000000 + f800000000000000 => f800000000000000
+dadd f800000000000000 + 22240000000000cf => f800000000000000
+dadd f800000000000000 + 7a34000000000000 => 7c00000000000000
+
+dadd. 2234000000000e50 + 223400000014c000 => 223400000014ce50
+dadd. a2340000000000e0 + 223400000014c000 => 223400000014a44c
+dadd. 22240000000000cf + a21400010a395bcf => a21400010a1b9bcf
+dadd. 2234000000000e50 + 000400000089b000 => 2e06500000000000
+dadd. a2340000000000e0 + a21400010a395bcf => a21400080a395bcf
+dadd. 6e4d3f1f534acdd4 + 223400000014c000 => 6e4d3f1f534acdd5
+dadd. 6e4d3f1f534acdd4 + a2340000000000e0 => 6e4d3f1f534acdd4
+dadd. 2238000000000000 + 223400000014c000 => 223400000014c000
+dadd. 2238000000000000 + a2340000000000e0 => a2340000000000e0
+dadd. a238000000000000 + 2234000000000e50 => 2234000000000e50
+dadd. a238000000000000 + 223400000014c000 => 223400000014c000
+dadd. a238000000000000 + a2340000000000e0 => a2340000000000e0
+dadd. 2238000000000000 + a238000000000000 => 2238000000000000
+dadd. fc00000000000000 + f800000000000000 => fc00000000000000
+dadd. fc00000000000000 + 223400000014c000 => fc00000000000000
+dadd. fc00000000000000 + 7800000000000000 => fc00000000000000
+dadd. fc00000000000000 + fc00000000000000 => fc00000000000000
+dadd. fc00000000000000 + fe000000d0e0a0d0 => fc000000d0e0a0d0
+dadd. fe000000d0e0a0d0 + f800000000000000 => fc000000d0e0a0d0
+dadd. fe000000d0e0a0d0 + 2234000000000e50 => fc000000d0e0a0d0
+dadd. fe000000d0e0a0d0 + 7800000000000000 => fc000000d0e0a0d0
+dadd. fe000000d0e0a0d0 + fe000000d0e0a0d0 => fc000000d0e0a0d0
+dadd. f800000000000000 + f800000000000000 => f800000000000000
+dadd. f800000000000000 + 22240000000000cf => f800000000000000
+dadd. f800000000000000 + 7a34000000000000 => 7c00000000000000
+
+
+dsub 2234000000000e50 - 223400000014c000 => a234000000149ad0
+dsub a2340000000000e0 - 223400000014c000 => a23400000014c0e0
+dsub 22240000000000cf - a21400010a395bcf => 221400010a571bcf
+dsub 2234000000000e50 - 000400000089b000 => 2e06500000000000
+dsub a2340000000000e0 - a21400010a395bcf => a214000477cb0d11
+dsub 6e4d3f1f534acdd4 - 223400000014c000 => 6e4d3f1f534acdd3
+dsub 6e4d3f1f534acdd4 - a2340000000000e0 => 6e4d3f1f534acdd4
+dsub 2238000000000000 - 223400000014c000 => a23400000014c000
+dsub 2238000000000000 - a2340000000000e0 => 22340000000000e0
+dsub a238000000000000 - 2234000000000e50 => a234000000000e50
+dsub a238000000000000 - 223400000014c000 => a23400000014c000
+dsub a238000000000000 - a2340000000000e0 => 22340000000000e0
+dsub 2238000000000000 - a238000000000000 => 2238000000000000
+dsub fc00000000000000 - f800000000000000 => fc00000000000000
+dsub fc00000000000000 - 223400000014c000 => fc00000000000000
+dsub fc00000000000000 - 7800000000000000 => fc00000000000000
+dsub fc00000000000000 - fc00000000000000 => fc00000000000000
+dsub fc00000000000000 - fe000000d0e0a0d0 => fc000000d0e0a0d0
+dsub fe000000d0e0a0d0 - f800000000000000 => fc000000d0e0a0d0
+dsub fe000000d0e0a0d0 - 2234000000000e50 => fc000000d0e0a0d0
+dsub fe000000d0e0a0d0 - 7800000000000000 => fc000000d0e0a0d0
+dsub fe000000d0e0a0d0 - fe000000d0e0a0d0 => fc000000d0e0a0d0
+dsub f800000000000000 - f800000000000000 => 7c00000000000000
+dsub f800000000000000 - 22240000000000cf => f800000000000000
+dsub f800000000000000 - 7a34000000000000 => f800000000000000
+
+dsub. 2234000000000e50 - 223400000014c000 => a234000000149ad0
+dsub. a2340000000000e0 - 223400000014c000 => a23400000014c0e0
+dsub. 22240000000000cf - a21400010a395bcf => 221400010a571bcf
+dsub. 2234000000000e50 - 000400000089b000 => 2e06500000000000
+dsub. a2340000000000e0 - a21400010a395bcf => a214000477cb0d11
+dsub. 6e4d3f1f534acdd4 - 223400000014c000 => 6e4d3f1f534acdd3
+dsub. 6e4d3f1f534acdd4 - a2340000000000e0 => 6e4d3f1f534acdd4
+dsub. 2238000000000000 - 223400000014c000 => a23400000014c000
+dsub. 2238000000000000 - a2340000000000e0 => 22340000000000e0
+dsub. a238000000000000 - 2234000000000e50 => a234000000000e50
+dsub. a238000000000000 - 223400000014c000 => a23400000014c000
+dsub. a238000000000000 - a2340000000000e0 => 22340000000000e0
+dsub. 2238000000000000 - a238000000000000 => 2238000000000000
+dsub. fc00000000000000 - f800000000000000 => fc00000000000000
+dsub. fc00000000000000 - 223400000014c000 => fc00000000000000
+dsub. fc00000000000000 - 7800000000000000 => fc00000000000000
+dsub. fc00000000000000 - fc00000000000000 => fc00000000000000
+dsub. fc00000000000000 - fe000000d0e0a0d0 => fc000000d0e0a0d0
+dsub. fe000000d0e0a0d0 - f800000000000000 => fc000000d0e0a0d0
+dsub. fe000000d0e0a0d0 - 2234000000000e50 => fc000000d0e0a0d0
+dsub. fe000000d0e0a0d0 - 7800000000000000 => fc000000d0e0a0d0
+dsub. fe000000d0e0a0d0 - fe000000d0e0a0d0 => fc000000d0e0a0d0
+dsub. f800000000000000 - f800000000000000 => 7c00000000000000
+dsub. f800000000000000 - 22240000000000cf => f800000000000000
+dsub. f800000000000000 - 7a34000000000000 => f800000000000000
+
+
+dmul 2234000000000e50 * 223400000014c000 => 22300001143a0000
+dmul a2340000000000e0 * 223400000014c000 => a23000000fa03000
+dmul 22240000000000cf * a21400010a395bcf => a20000fe5b36cca1
+dmul 2234000000000e50 * 000400000089b000 => 0000000c28a03000
+dmul a2340000000000e0 * a21400010a395bcf => 221000d67d31a940
+dmul 6e4d3f1f534acdd4 * 223400000014c000 => 266510610e1d3703
+dmul 6e4d3f1f534acdd4 * a2340000000000e0 => a656f47e5fba95b7
+dmul 2238000000000000 * a238000000000000 => a238000000000000
+dmul 2238000000000000 * 223400000014c000 => 2234000000000000
+dmul 4248000000000000 * 7a34000000000000 => 7c00000000000000
+dmul a238000000000000 * fc00000000000000 => fc00000000000000
+dmul 2238000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul 7800000000000000 * a2340000000000e0 => f800000000000000
+dmul 7800000000000000 * f800000000000000 => f800000000000000
+dmul 7a34000000000000 * fc00000000000000 => fc00000000000000
+dmul f800000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul fc00000000000000 * fc00000000000000 => fc00000000000000
+dmul fc00000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul fe000000d0e0a0d0 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+
+dmul. 2234000000000e50 * 223400000014c000 => 22300001143a0000
+dmul. a2340000000000e0 * 223400000014c000 => a23000000fa03000
+dmul. 22240000000000cf * a21400010a395bcf => a20000fe5b36cca1
+dmul. 2234000000000e50 * 000400000089b000 => 0000000c28a03000
+dmul. a2340000000000e0 * a21400010a395bcf => 221000d67d31a940
+dmul. 6e4d3f1f534acdd4 * 223400000014c000 => 266510610e1d3703
+dmul. 6e4d3f1f534acdd4 * a2340000000000e0 => a656f47e5fba95b7
+dmul. 2238000000000000 * a238000000000000 => a238000000000000
+dmul. 2238000000000000 * 223400000014c000 => 2234000000000000
+dmul. 4248000000000000 * 7a34000000000000 => 7c00000000000000
+dmul. a238000000000000 * fc00000000000000 => fc00000000000000
+dmul. 2238000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul. 7800000000000000 * a2340000000000e0 => f800000000000000
+dmul. 7800000000000000 * f800000000000000 => f800000000000000
+dmul. 7a34000000000000 * fc00000000000000 => fc00000000000000
+dmul. f800000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul. fc00000000000000 * fc00000000000000 => fc00000000000000
+dmul. fc00000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul. fe000000d0e0a0d0 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+
+
+ddiv 2234000000000e50 / 223400000014c000 => 29f20ccf848e2a4e
+ddiv a2340000000000e0 / 223400000014c000 => a5ed80474082c00b
+ddiv 22240000000000cf / a21400010a395bcf => b1eeabacabd62ac3
+ddiv 2234000000000e50 / 000400000089b000 => 7800000000000000
+ddiv a2340000000000e0 / a21400010a395bcf => 2dfc0e4e6a205575
+ddiv 6e4d3f1f534acdd4 / 223400000014c000 => 3e38ff87d92ca3c3
+ddiv 6e4d3f1f534acdd4 / a2340000000000e0 => ba48c92fea1aadc6
+ddiv 2238000000000000 / a238000000000000 => 7c00000000000000
+ddiv 2238000000000000 / 223400000014c000 => 223c000000000000
+ddiv 4248000000000000 / 7a34000000000000 => 0000000000000000
+ddiv a238000000000000 / fc00000000000000 => fc00000000000000
+ddiv 2238000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv 7800000000000000 / a2340000000000e0 => f800000000000000
+ddiv 7800000000000000 / f800000000000000 => 7c00000000000000
+ddiv 7a34000000000000 / fc00000000000000 => fc00000000000000
+ddiv f800000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv fc00000000000000 / fc00000000000000 => fc00000000000000
+ddiv fc00000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv fe000000d0e0a0d0 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+
+ddiv. 2234000000000e50 / 223400000014c000 => 29f20ccf848e2a4e
+ddiv. a2340000000000e0 / 223400000014c000 => a5ed80474082c00b
+ddiv. 22240000000000cf / a21400010a395bcf => b1eeabacabd62ac3
+ddiv. 2234000000000e50 / 000400000089b000 => 7800000000000000
+ddiv. a2340000000000e0 / a21400010a395bcf => 2dfc0e4e6a205575
+ddiv. 6e4d3f1f534acdd4 / 223400000014c000 => 3e38ff87d92ca3c3
+ddiv. 6e4d3f1f534acdd4 / a2340000000000e0 => ba48c92fea1aadc6
+ddiv. 2238000000000000 / a238000000000000 => 7c00000000000000
+ddiv. 2238000000000000 / 223400000014c000 => 223c000000000000
+ddiv. 4248000000000000 / 7a34000000000000 => 0000000000000000
+ddiv. a238000000000000 / fc00000000000000 => fc00000000000000
+ddiv. 2238000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv. 7800000000000000 / a2340000000000e0 => f800000000000000
+ddiv. 7800000000000000 / f800000000000000 => 7c00000000000000
+ddiv. 7a34000000000000 / fc00000000000000 => fc00000000000000
+ddiv. f800000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv. fc00000000000000 / fc00000000000000 => fc00000000000000
+ddiv. fc00000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv. fe000000d0e0a0d0 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+
+
+daddq 2207c00000000000 0000000000000e50 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014ce50
+daddq a207c00000000000 00000000000000e0 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014a44c
+daddq 2206c00000000000 00000000000000cf + a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a1b9bcf
+daddq 2207c00000000000 0000000000000e50 + 000400000089b000 0a6000d000000049 ==> 2e00650000000000 0000000000000000
+daddq a207c00000000000 00000000000000e0 + a205c00000000000 000000010a395bcf ==> a205c00000000000 000000080a395bcf
+daddq 6209400000fd0000 00253f1f534acdd4 + 2207c00000000000 000000000014c000 ==> 2601130000000000 0000000000000000
+daddq 6209400000fd0000 00253f1f534acdd4 + a207c00000000000 00000000000000e0 ==> a600300000000000 0000000000000000
+daddq 2208000000000000 0000000000000000 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+daddq 2208000000000000 0000000000000000 + a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+daddq a208000000000000 0000000000000000 + 2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+daddq a208000000000000 0000000000000000 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+daddq a208000000000000 0000000000000000 + a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+daddq 2208000000000000 0000000000000000 + a208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+daddq 7e00000000000000 fe000000d0e0a0d0 + f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq 7e00000000000000 fe000000d0e0a0d0 + 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq 7e00000000000000 fe000000d0e0a0d0 + 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq 7e00000000000000 fe000000d0e0a0d0 + 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq 7e00000000000000 fe000000d0e0a0d0 + fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq fc00000000000000 c00100035b007700 + f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+daddq fc00000000000000 c00100035b007700 + 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+daddq fc00000000000000 c00100035b007700 + 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+daddq fc00000000000000 c00100035b007700 + fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+daddq f800000000000000 0000000000000000 + f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+daddq f800000000000000 0000000000000000 + 2206c00000000000 00000000000000cf ==> f800000000000000 0000000000000000
+daddq f800000000000000 0000000000000000 + f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+daddq. 2207c00000000000 0000000000000e50 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014ce50
+daddq. a207c00000000000 00000000000000e0 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014a44c
+daddq. 2206c00000000000 00000000000000cf + a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a1b9bcf
+daddq. 2207c00000000000 0000000000000e50 + 000400000089b000 0a6000d000000049 ==> 2e00650000000000 0000000000000000
+daddq. a207c00000000000 00000000000000e0 + a205c00000000000 000000010a395bcf ==> a205c00000000000 000000080a395bcf
+daddq. 6209400000fd0000 00253f1f534acdd4 + 2207c00000000000 000000000014c000 ==> 2601130000000000 0000000000000000
+daddq. 6209400000fd0000 00253f1f534acdd4 + a207c00000000000 00000000000000e0 ==> a600300000000000 0000000000000000
+daddq. 2208000000000000 0000000000000000 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+daddq. 2208000000000000 0000000000000000 + a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+daddq. a208000000000000 0000000000000000 + 2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+daddq. a208000000000000 0000000000000000 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+daddq. a208000000000000 0000000000000000 + a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+daddq. 2208000000000000 0000000000000000 + a208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+daddq. 7e00000000000000 fe000000d0e0a0d0 + f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. 7e00000000000000 fe000000d0e0a0d0 + 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. 7e00000000000000 fe000000d0e0a0d0 + 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. 7e00000000000000 fe000000d0e0a0d0 + 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. 7e00000000000000 fe000000d0e0a0d0 + fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. fc00000000000000 c00100035b007700 + f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+daddq. fc00000000000000 c00100035b007700 + 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+daddq. fc00000000000000 c00100035b007700 + 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+daddq. fc00000000000000 c00100035b007700 + fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+daddq. f800000000000000 0000000000000000 + f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+daddq. f800000000000000 0000000000000000 + 2206c00000000000 00000000000000cf ==> f800000000000000 0000000000000000
+daddq. f800000000000000 0000000000000000 + f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+
+dsubq 2207c00000000000 0000000000000e50 - 2207c00000000000 000000000014c000 ==> a207c00000000000 0000000000149ad0
+dsubq a207c00000000000 00000000000000e0 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c0e0
+dsubq 2206c00000000000 00000000000000cf - a205c00000000000 000000010a395bcf ==> 2205c00000000000 000000010a571bcf
+dsubq 2207c00000000000 0000000000000e50 - 000400000089b000 0a6000d000000049 ==> 2e00650000000000 0000000000000000
+dsubq a207c00000000000 00000000000000e0 - a205c00000000000 000000010a395bcf ==> a205c00000000000 0000000477cb0d11
+dsubq 6209400000fd0000 00253f1f534acdd4 - 2207c00000000000 000000000014c000 ==> a601130000000000 0000000000000000
+dsubq 6209400000fd0000 00253f1f534acdd4 - a207c00000000000 00000000000000e0 ==> 2600300000000000 0000000000000000
+dsubq 2208000000000000 0000000000000000 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c000
+dsubq 2208000000000000 0000000000000000 - a207c00000000000 00000000000000e0 ==> 2207c00000000000 00000000000000e0
+dsubq a208000000000000 0000000000000000 - 2207c00000000000 0000000000000e50 ==> a207c00000000000 0000000000000e50
+dsubq a208000000000000 0000000000000000 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c000
+dsubq a208000000000000 0000000000000000 - a207c00000000000 00000000000000e0 ==> 2207c00000000000 00000000000000e0
+dsubq 2208000000000000 0000000000000000 - a208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dsubq 7e00000000000000 fe000000d0e0a0d0 - f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq 7e00000000000000 fe000000d0e0a0d0 - 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq 7e00000000000000 fe000000d0e0a0d0 - 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq 7e00000000000000 fe000000d0e0a0d0 - 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq 7e00000000000000 fe000000d0e0a0d0 - fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq fc00000000000000 c00100035b007700 - f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dsubq fc00000000000000 c00100035b007700 - 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dsubq fc00000000000000 c00100035b007700 - 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dsubq fc00000000000000 c00100035b007700 - fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dsubq f800000000000000 0000000000000000 - f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dsubq f800000000000000 0000000000000000 - 2206c00000000000 00000000000000cf ==> f800000000000000 0000000000000000
+dsubq f800000000000000 0000000000000000 - f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+
+dsubq. 2207c00000000000 0000000000000e50 - 2207c00000000000 000000000014c000 ==> a207c00000000000 0000000000149ad0
+dsubq. a207c00000000000 00000000000000e0 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c0e0
+dsubq. 2206c00000000000 00000000000000cf - a205c00000000000 000000010a395bcf ==> 2205c00000000000 000000010a571bcf
+dsubq. 2207c00000000000 0000000000000e50 - 000400000089b000 0a6000d000000049 ==> 2e00650000000000 0000000000000000
+dsubq. a207c00000000000 00000000000000e0 - a205c00000000000 000000010a395bcf ==> a205c00000000000 0000000477cb0d11
+dsubq. 6209400000fd0000 00253f1f534acdd4 - 2207c00000000000 000000000014c000 ==> a601130000000000 0000000000000000
+dsubq. 6209400000fd0000 00253f1f534acdd4 - a207c00000000000 00000000000000e0 ==> 2600300000000000 0000000000000000
+dsubq. 2208000000000000 0000000000000000 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c000
+dsubq. 2208000000000000 0000000000000000 - a207c00000000000 00000000000000e0 ==> 2207c00000000000 00000000000000e0
+dsubq. a208000000000000 0000000000000000 - 2207c00000000000 0000000000000e50 ==> a207c00000000000 0000000000000e50
+dsubq. a208000000000000 0000000000000000 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c000
+dsubq. a208000000000000 0000000000000000 - a207c00000000000 00000000000000e0 ==> 2207c00000000000 00000000000000e0
+dsubq. 2208000000000000 0000000000000000 - a208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. fc00000000000000 c00100035b007700 - f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dsubq. fc00000000000000 c00100035b007700 - 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dsubq. fc00000000000000 c00100035b007700 - 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dsubq. fc00000000000000 c00100035b007700 - fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dsubq. f800000000000000 0000000000000000 - f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dsubq. f800000000000000 0000000000000000 - 2206c00000000000 00000000000000cf ==> f800000000000000 0000000000000000
+dsubq. f800000000000000 0000000000000000 - f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+
+
+dmulq 2207c00000000000 0000000000000e50 * 2207c00000000000 000000000014c000 ==> 2207800000000000 00000001143a0000
+dmulq a207c00000000000 00000000000000e0 * 2207c00000000000 000000000014c000 ==> a207800000000000 000000000fa03000
+dmulq 2206c00000000000 00000000000000cf * a205c00000000000 000000010a395bcf ==> a204800000000000 000000fe5b36cca1
+dmulq 2207c00000000000 0000000000000e50 * 000400000089b000 0a6000d000000049 ==> 0003c007dd9d007e b20908000003a450
+dmulq a207c00000000000 00000000000000e0 * a205c00000000000 000000010a395bcf ==> 2205800000000000 000000d67d31a940
+dmulq 6209400000fd0000 00253f1f534acdd4 * 2207c00000000000 000000000014c000 ==> 660a84c004da6c00 004883107189d825
+dmulq 6209400000fd0000 00253f1f534acdd4 * a207c00000000000 00000000000000e0 ==> 8609d0a000d57800 0006f47e5fba95b7
+dmulq 2208000000000000 0000000000000000 * a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dmulq 2208000000000000 0000000000000000 * 2207c00000000000 000000000014c000 ==> 2207c00000000000 0000000000000000
+dmulq a248000000000000 0000000000000000 * f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dmulq a208000000000000 0000000000000000 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq 2208000000000000 0000000000000000 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dmulq 7800000000000000 0000000000000000 * a207c00000000000 00000000000000e0 ==> f800000000000000 0000000000000000
+dmulq 7800000000000000 0000000000000000 * f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dmulq f900000000000000 0000000000000000 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq f800000000000000 0000000000000000 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dmulq 7e00000000000000 fe000000d0e0a0d0 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq 7e00000000000000 fe000000d0e0a0d0 * fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq fc00000000000000 c00100035b007700 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+
+dmulq. 2207c00000000000 0000000000000e50 * 2207c00000000000 000000000014c000 ==> 2207800000000000 00000001143a0000
+dmulq. a207c00000000000 00000000000000e0 * 2207c00000000000 000000000014c000 ==> a207800000000000 000000000fa03000
+dmulq. 2206c00000000000 00000000000000cf * a205c00000000000 000000010a395bcf ==> a204800000000000 000000fe5b36cca1
+dmulq. 2207c00000000000 0000000000000e50 * 000400000089b000 0a6000d000000049 ==> 0003c007dd9d007e b20908000003a450
+dmulq. a207c00000000000 00000000000000e0 * a205c00000000000 000000010a395bcf ==> 2205800000000000 000000d67d31a940
+dmulq. 6209400000fd0000 00253f1f534acdd4 * 2207c00000000000 000000000014c000 ==> 660a84c004da6c00 004883107189d825
+dmulq. 6209400000fd0000 00253f1f534acdd4 * a207c00000000000 00000000000000e0 ==> 8609d0a000d57800 0006f47e5fba95b7
+dmulq. 2208000000000000 0000000000000000 * a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dmulq. 2208000000000000 0000000000000000 * 2207c00000000000 000000000014c000 ==> 2207c00000000000 0000000000000000
+dmulq. a248000000000000 0000000000000000 * f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dmulq. a208000000000000 0000000000000000 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq. 2208000000000000 0000000000000000 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dmulq. 7800000000000000 0000000000000000 * a207c00000000000 00000000000000e0 ==> f800000000000000 0000000000000000
+dmulq. 7800000000000000 0000000000000000 * f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dmulq. f900000000000000 0000000000000000 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq. f800000000000000 0000000000000000 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dmulq. 7e00000000000000 fe000000d0e0a0d0 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq. 7e00000000000000 fe000000d0e0a0d0 * fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq. fc00000000000000 c00100035b007700 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+
+
+ddivq 2207c00000000000 0000000000000e50 / 2207c00000000000 000000000014c000 ==> 29ff20ccf848e2a6 b8333e1238a9ae0d
+ddivq a207c00000000000 00000000000000e0 / 2207c00000000000 000000000014c000 ==> a5fed80474082c00 b6011d020b002d81
+ddivq 2206c00000000000 00000000000000cf / a205c00000000000 000000010a395bcf ==> b1feeabacabd62ac 3812c9f3bf11f97a
+ddivq 2207c00000000000 0000000000000e50 / 000400000089b000 0a6000d000000049 ==> 4ffdcc9ad201f5f8 691a4dc710e32c5a
+ddivq a207c00000000000 00000000000000e0 / a205c00000000000 000000010a395bcf ==> 2dffc0e4e6a20557 44fc3ca241351d34
+ddivq 6209400000fd0000 00253f1f534acdd4 / 2207c00000000000 000000000014c000 ==> 1a082841943c02d8 00b408095bb6bed6
+ddivq 6209400000fd0000 00253f1f534acdd4 / a207c00000000000 00000000000000e0 ==> 9609000003069f40 0018c92fea1aadc6
+ddivq 2208000000000000 0000000000000000 / a208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+ddivq 2208000000000000 0000000000000000 / 2207c00000000000 000000000014c000 ==> 2208400000000000 0000000000000000
+ddivq a248000000000000 0000000000000000 / f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddivq a208000000000000 0000000000000000 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq 2208000000000000 0000000000000000 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+ddivq 7800000000000000 0000000000000000 / a207c00000000000 00000000000000e0 ==> f800000000000000 0000000000000000
+ddivq 7800000000000000 0000000000000000 / f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+ddivq f900000000000000 0000000000000000 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq f800000000000000 0000000000000000 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+ddivq 7e00000000000000 fe000000d0e0a0d0 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq 7e00000000000000 fe000000d0e0a0d0 / fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq fc00000000000000 c00100035b007700 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+
+ddivq. 2207c00000000000 0000000000000e50 / 2207c00000000000 000000000014c000 ==> 29ff20ccf848e2a6 b8333e1238a9ae0d
+ddivq. a207c00000000000 00000000000000e0 / 2207c00000000000 000000000014c000 ==> a5fed80474082c00 b6011d020b002d81
+ddivq. 2206c00000000000 00000000000000cf / a205c00000000000 000000010a395bcf ==> b1feeabacabd62ac 3812c9f3bf11f97a
+ddivq. 2207c00000000000 0000000000000e50 / 000400000089b000 0a6000d000000049 ==> 4ffdcc9ad201f5f8 691a4dc710e32c5a
+ddivq. a207c00000000000 00000000000000e0 / a205c00000000000 000000010a395bcf ==> 2dffc0e4e6a20557 44fc3ca241351d34
+ddivq. 6209400000fd0000 00253f1f534acdd4 / 2207c00000000000 000000000014c000 ==> 1a082841943c02d8 00b408095bb6bed6
+ddivq. 6209400000fd0000 00253f1f534acdd4 / a207c00000000000 00000000000000e0 ==> 9609000003069f40 0018c92fea1aadc6
+ddivq. 2208000000000000 0000000000000000 / a208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+ddivq. 2208000000000000 0000000000000000 / 2207c00000000000 000000000014c000 ==> 2208400000000000 0000000000000000
+ddivq. a248000000000000 0000000000000000 / f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddivq. a208000000000000 0000000000000000 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq. 2208000000000000 0000000000000000 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+ddivq. 7800000000000000 0000000000000000 / a207c00000000000 00000000000000e0 ==> f800000000000000 0000000000000000
+ddivq. 7800000000000000 0000000000000000 / f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+ddivq. f900000000000000 0000000000000000 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq. f800000000000000 0000000000000000 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+ddivq. 7e00000000000000 fe000000d0e0a0d0 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq. 7e00000000000000 fe000000d0e0a0d0 / fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq. fc00000000000000 c00100035b007700 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+
+
+Test DFP rounding modes
+test #0: dmul with rounding mode 0: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 1: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 2: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f6
+
+test #0: dmul with rounding mode 3: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 4: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 5: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 6: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f6
+
+test #0: dmul with rounding mode 7: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f6
+
+test #1: dmul with rounding mode 0: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 1: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 2: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f8
+
+test #1: dmul with rounding mode 3: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 4: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 5: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 6: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f8
+
+test #1: dmul with rounding mode 7: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #2: dmul with rounding mode 0: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 1: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 2: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e098a
+
+test #2: dmul with rounding mode 3: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 4: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 5: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 6: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e098a
+
+test #2: dmul with rounding mode 7: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #3: dmul with rounding mode 0: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 1: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 2: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e09aa
+
+test #3: dmul with rounding mode 3: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 4: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 5: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 6: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e09aa
+
+test #3: dmul with rounding mode 7: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #4: dmul with rounding mode 0: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 1: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 2: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ca
+
+test #4: dmul with rounding mode 3: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 4: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 5: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 6: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ca
+
+test #4: dmul with rounding mode 7: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #5: dmul with rounding mode 0: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 1: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 2: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09ea
+
+test #5: dmul with rounding mode 3: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 4: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 5: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 6: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09ea
+
+test #5: dmul with rounding mode 7: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09ea
+
+test #6: dmul with rounding mode 0: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 1: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 2: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a56
+
+test #6: dmul with rounding mode 3: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 4: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 5: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 6: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a56
+
+test #6: dmul with rounding mode 7: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a56
+
+test #7: dmul with rounding mode 0: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 1: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 2: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a58
+
+test #7: dmul with rounding mode 3: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 4: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 5: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 6: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a58
+
+test #7: dmul with rounding mode 7: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #8: dmul with rounding mode 0: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 1: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef0
+
+test #8: dmul with rounding mode 2: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 3: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef0
+
+test #8: dmul with rounding mode 4: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 5: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 6: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 7: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #9: dmul with rounding mode 0: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 1: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef2
+
+test #9: dmul with rounding mode 2: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 3: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef2
+
+test #9: dmul with rounding mode 4: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 5: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 6: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 7: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef2
+
+test #10: dmul with rounding mode 0: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 1: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 2: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a64
+
+test #10: dmul with rounding mode 3: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 4: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 5: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 6: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a64
+
+test #10: dmul with rounding mode 7: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #11: dmul with rounding mode 0: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 1: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 2: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a66
+
+test #11: dmul with rounding mode 3: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 4: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 5: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 6: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a66
+
+test #11: dmul with rounding mode 7: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a66
+
+Test move to/from FPSCR
+FPSCR binary floating point rounding mode 0000000000000000 == 0000000000000000? yes
+FPSCR binary floating point rounding mode 0000000000000001 == 0000000000000001? yes
+FPSCR binary floating point rounding mode 0000000000000002 == 0000000000000002? yes
+FPSCR binary floating point rounding mode 0000000000000003 == 0000000000000003? yes
+FPSCR decimal floating point rounding mode 0000000000000003 == 0000000000000003? yes
+FPSCR decimal floating point rounding mode 0000000100000003 == 0000000100000003? yes
+FPSCR decimal floating point rounding mode 0000000200000003 == 0000000200000003? yes
+FPSCR decimal floating point rounding mode 0000000300000003 == 0000000300000003? yes
+FPSCR decimal floating point rounding mode 0000000400000003 == 0000000400000003? yes
+FPSCR decimal floating point rounding mode 0000000500000003 == 0000000500000003? yes
+FPSCR decimal floating point rounding mode 0000000600000003 == 0000000600000003? yes
+FPSCR decimal floating point rounding mode 0000000700000003 == 0000000700000003? yes
diff --git a/main/none/tests/ppc32/test_dfp1.vgtest b/main/none/tests/ppc32/test_dfp1.vgtest
new file mode 100644
index 0000000..0efe5df
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp1.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp1
diff --git a/main/none/tests/ppc32/test_dfp2.c b/main/none/tests/ppc32/test_dfp2.c
new file mode 100644
index 0000000..31bdae9
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp2.c
@@ -0,0 +1,675 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+ Carl Love <carll@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <elf.h>
+#include <link.h>
+
+#define PPC_FEATURE_HAS_VSX 0x00000080 /* Vector Scalar Extension. */
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+#define SH_0 0
+#define SH_1 1
+#define SH_2 15
+#define SH_3 63
+
+#define NUM_RND_MODES 8
+#define CONDREG_MASK 0x0f000000
+#define CONDREG_SHIFT 24
+
+static char ** my_envp;
+static inline char** __auxv_find(void)
+{
+ char **result = my_envp;
+ /* Scan over the env vector looking for the ending NULL */
+ for (; *result != NULL; ++result) {
+ }
+ /* Bump the pointer one more step, which should be the auxv. */
+ return ++result;
+}
+
+static unsigned long fetch_at_hwcap(void)
+{
+ static unsigned long auxv_hwcap = 0;
+ int i;
+ ElfW(auxv_t) * auxv_buf = NULL;
+
+ if (auxv_hwcap)
+ return auxv_hwcap;
+
+ auxv_buf = (ElfW(auxv_t)*) __auxv_find();
+ for (i = 0; auxv_buf[i].a_type != AT_NULL; i++)
+ if (auxv_buf[i].a_type == AT_HWCAP) {
+ auxv_hwcap = auxv_buf[i].a_un.a_val;
+ break;
+ }
+
+ return auxv_hwcap;
+}
+
+int get_vsx(void)
+{
+ /* Check to see if the AUX vector has the bit set indicating the HW
+ * supports the vsx instructions. This implies the processor is
+ * at least a POWER 7.
+ */
+ unsigned long hwcap;
+
+ hwcap = fetch_at_hwcap();
+ if ((hwcap & PPC_FEATURE_HAS_VSX) == PPC_FEATURE_HAS_VSX)
+ return 1;
+
+ return 0;
+}
+
+/* The assembly-level instructions being tested */
+static void _test_dscri (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+
+ case SH_1:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+
+ case SH_2:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+
+ case SH_3:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscri, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dscli (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+
+ case SH_1:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+
+ case SH_2:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+
+ case SH_3:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscli, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dctdp (void)
+{
+ __asm__ __volatile__ ("dctdp %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_drsp (void)
+{
+ __asm__ __volatile__ ("drsp %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dctfix (void)
+{
+ __asm__ __volatile__ ("dctfix %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+/* Power 7 and newer processors support this instruction */
+static void _test_dcffix (void)
+{
+ __asm__ __volatile__ ("dcffix %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dscriq (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+ case SH_1:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+ case SH_2:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+ case SH_3:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscriq, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dscliq (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+ case SH_1:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+ case SH_2:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+ case SH_3:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscliq, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dctqpq (void)
+{
+ __asm__ __volatile__ ("dctqpq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dctfixq (void)
+{
+ __asm__ __volatile__ ("dctfixq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_drdpq (void)
+{
+ __asm__ __volatile__ ("drdpq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dcffixq (void)
+{
+ __asm__ __volatile__ ("dcffixq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+typedef void (*test_func_t)();
+typedef void (*test_func_main_t)(int);
+typedef void (*test_func_shift_t)(int);
+typedef struct test_table
+{
+ test_func_main_t test_category;
+ char * name;
+} test_table_t;
+
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2f07c00000000000ULL, 0x000000000014c000ULL, //large number
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // a small number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long int64_vals[] = {
+ // I64 values
+ 0x0ULL, // zero
+ 0x1ULL, // one
+ 0xffffffffffffffffULL, // minus one
+ 0x2386f26fc0ffffULL, // 9999999999999999
+ 0xffdc790d903f0001ULL, // -9999999999999999
+ 0x462d53c8abac0ULL, // 1234567890124567
+ 0xfffb9d2ac3754540ULL, // -1234567890124567
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// large number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+/* Index pairs from dfp64_vals or dfp128_vals array to be used with
+ * dfp_two_arg_tests */
+static dfp_test_args_t int64_args_x1[] = {
+ /* {int64 input val, unused } */
+ {0, 0},
+ {1, 0},
+ {2, 0},
+ {3, 0},
+ {4, 0},
+ {5, 0},
+ {6, 0},
+};
+
+static dfp_test_args_t dfp_2args_x1[] = {
+ /* {dfp_arg, shift_arg} */
+ {0, SH_0},
+ {0, SH_1},
+ {0, SH_2},
+ {0, SH_3},
+ {5, SH_0},
+ {5, SH_1},
+ {5, SH_2},
+ {5, SH_3},
+ {6, SH_0},
+ {6, SH_1},
+ {6, SH_2},
+ {6, SH_3},
+ {7, SH_0},
+ {7, SH_1},
+ {7, SH_2},
+ {7, SH_3},
+ {10, SH_0},
+ {10, SH_1},
+ {10, SH_2},
+ {10, SH_3},
+ {13, SH_0},
+ {13, SH_1},
+ {13, SH_2},
+ {13, SH_3},
+};
+
+/* Index pairs from dfp64_vals array to be used with dfp_one_arg_tests */
+static dfp_test_args_t dfp_1args_x1[] = {
+ /* {dfp_arg, unused} */
+ {0, 0},
+ {1, 0},
+ {2, 0},
+ {3, 0},
+ {4, 0},
+ {5, 0},
+ {6, 0},
+ {7, 0},
+ {8, 0},
+ {9, 0},
+ {10, 0},
+ {11, 0},
+ {12, 0},
+ {13, 0},
+ {14, 0},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+ Bool cr_supported;
+} dfp_test_t;
+
+/* The dcffix and dcffixq tests are a little different in that they both take
+ * an I64 input.
+ */
+static dfp_test_t
+dfp_dcffix_dcffixq_tests[] = {
+ { &_test_dcffixq,"dcffixq", int64_args_x1, 7, QUAD_TEST, "I64S->D128", True},
+ /* Power 7 instruction */
+ { &_test_dcffix, "dcffix", int64_args_x1, 7, LONG_TEST, "I64S->D64", True},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static dfp_test_t
+dfp_one_arg_tests[] = {
+ { &_test_dctdp, "dctdp", dfp_1args_x1, 15, LONG_TEST, "D32->D64", True},
+ { &_test_drsp, "drsp", dfp_1args_x1, 15, LONG_TEST, "D64->D32", True},
+ { &_test_dctfix, "dctfix", dfp_1args_x1, 15, LONG_TEST, "D64->I64S", True},
+ { &_test_dctqpq, "dctqpq", dfp_1args_x1, 15, QUAD_TEST, "D64->D128", True},
+ { &_test_dctfixq,"dctfixq", dfp_1args_x1, 15, QUAD_TEST, "D128->I64S", True},
+ { &_test_drdpq, "drdpq", dfp_1args_x1, 15, QUAD_TEST, "D128->D64", True},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+
+static dfp_test_t
+dfp_two_arg_tests[] = {
+ { &_test_dscri, "dscri", dfp_2args_x1, 20, LONG_TEST, ">>", True},
+ { &_test_dscli, "dscli", dfp_2args_x1, 20, LONG_TEST, "<<", True},
+ { &_test_dscriq, "dscriq", dfp_2args_x1, 20, QUAD_TEST, ">>", True},
+ { &_test_dscliq, "dscliq", dfp_2args_x1, 20, QUAD_TEST, "<<", True},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+void set_rounding_mode(unsigned long long rnd_mode)
+{
+ double fpscr;
+ unsigned long long * hex_fpscr = (unsigned long long *)&fpscr;
+
+ *hex_fpscr = 0ULL;
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14));
+ fpscr = f14;
+ *hex_fpscr &= 0xFFFFFFF0FFFFFFFFULL;
+ *hex_fpscr |= (rnd_mode << 32);
+ f14 = fpscr;
+ SET_FPSCR_DRN;
+}
+
+static void test_dfp_one_arg_ops(int unused)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p;
+ double d0x, *d0xp;
+ unsigned long round_mode;
+ int k = 0;
+
+ u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_one_arg_tests[k].test_func)) {
+ int i;
+
+ for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
+ /* Do each test with each of the possible rounding modes */
+ dfp_test_t test_group = dfp_one_arg_tests[k];
+
+ printf("\ntest with rounding mode %lu \n", round_mode);
+ /* The set_rounding_mode() uses the global value f14. Call the
+ * function before setting up the test for the specific instruction
+ * to avoid avoid conflicts using f14.
+ */
+ set_rounding_mode(round_mode);
+
+ for (i = 0; i < test_group.num_tests; i++) {
+
+ if (test_group.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_group.targs[i].fra_idx];
+ } else {
+ u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
+ }
+
+ *(unsigned long long *)d0p = u0;
+ f14 = d0;
+ if (test_group.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f15 = d0x;
+ }
+
+ (*func)();
+ res = f18;
+
+ printf("%s %016llx", test_group.name, u0);
+
+ if (test_group.precision == LONG_TEST) {
+ printf(" %s => %016llx",
+ test_group.op, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx %s ==> %016llx %016llx",
+ u0x, test_group.op,
+ *((unsigned long long *)(&res)),
+ *((unsigned long long *)(&resx)));
+ }
+ printf("\n");
+ }
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_dfp_two_arg_ops(int unused)
+/* Shift instructions: first argument is the DFP source, second argument
+ * is 6 bit shift amount.
+ */
+{
+ test_func_shift_t func;
+ unsigned long long u0, u0x;
+ unsigned int shift_by;
+ double res, d0, *d0p;
+ double d0x, *d0xp;
+ unsigned long round_mode;
+ int k = 0;
+
+ u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_two_arg_tests[k].test_func)) {
+ int i;
+
+ for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
+ /* Do each test with each of the possible rounding modes */
+ dfp_test_t test_group = dfp_two_arg_tests[k];
+
+ printf("\ntest with rounding mode %lu \n", round_mode);
+
+ /* The set_rounding_mode() uses the global value f14. Call the
+ * function before setting up the test for the specific instruction
+ * to avoid avoid conflicts using f14.
+ */
+ set_rounding_mode(round_mode);
+
+ for (i = 0; i < test_group.num_tests; i++) {
+
+ shift_by = test_group.targs[i].frb_idx;
+
+ if (test_group.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_group.targs[i].fra_idx];
+ } else {
+ u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
+ }
+
+ *(unsigned long long *)d0p = u0;
+ f14 = d0;
+ if (test_group.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f15 = d0x;
+ }
+
+ (*func)(shift_by);
+ res = f18;
+
+ printf("%s %016llx", test_group.name, u0);
+
+ if (test_group.precision) {
+ printf(" %s %-3d => %016llx",
+ test_group.op, shift_by, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx %s %-3d ==> %016llx %016llx",
+ u0x, test_group.op, shift_by,
+ *((unsigned long long *)(&res)),
+ *((unsigned long long *)(&resx)));
+ }
+ printf("\n" );
+ }
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_dcffix_dcffixq(int has_vsx)
+{
+ test_func_t func;
+ unsigned long long u0;
+ double res, d0, *d0p;
+ int k = 0, round_mode;
+
+ d0p = &d0;
+
+
+ while ((func = dfp_dcffix_dcffixq_tests[k].test_func)) {
+ int i;
+
+ if ((!has_vsx) && (!strcmp("dcffix", dfp_dcffix_dcffixq_tests[k].name))) {
+ k++;
+ /* The test instruction is dcffix it is supported on POWER 7
+ * and newer processors. Skip if not POWER 7 or newer.
+ */
+ continue;
+ }
+
+ for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
+ /* Do each test with each of the possible rounding modes */
+ dfp_test_t test_group = dfp_dcffix_dcffixq_tests[k];
+
+ printf("\ntest with rounding mode %u \n", round_mode);
+
+ /* The set_rounding_mode() uses the global value f14. Call the
+ * function before setting up the test for the specific instruction
+ * to avoid avoid conflicts using f14.
+ */
+ set_rounding_mode(round_mode);
+
+ for (i = 0; i < test_group.num_tests; i++) {
+
+ /* The instructions take I64 inputs */
+ u0 = int64_vals[test_group.targs[i].fra_idx];
+
+ *(unsigned long long *)d0p = u0;
+ f14 = d0;
+
+ (*func)();
+ res = f18;
+
+ printf("%s %016llx", test_group.name, u0);
+
+ if (test_group.precision) {
+ printf(" %s => %016llx",
+ test_group.op, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %s ==> %016llx %016llx",
+ test_group.op,
+ *((unsigned long long *)(&res)),
+ *((unsigned long long *)(&resx)));
+ }
+ printf("\n" );
+ }
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static test_table_t
+all_tests[] =
+{
+ { &test_dfp_one_arg_ops,
+ "Test DFP fomat conversion instructions" },
+ { &test_dfp_two_arg_ops,
+ "Test DFP shift instructions" },
+ { test_dcffix_dcffixq,
+ "Test DCFFIX and DCFFIXQ instructions" },
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main(int argc, char ** argv, char ** envp) {
+#if defined(HAS_DFP)
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0, has_vsx;
+
+ /* If the processor has the VSX functionality then it is POWER 7
+ * or newer.
+ */
+ my_envp = envp;
+ has_vsx = get_vsx();
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)(has_vsx);
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc32/test_dfp2.stderr.exp b/main/none/tests/ppc32/test_dfp2.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp2.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc32/test_dfp2.stdout.exp b/main/none/tests/ppc32/test_dfp2.stdout.exp
new file mode 100644
index 0000000..50c3540
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp2.stdout.exp
@@ -0,0 +1,1679 @@
+Test DFP fomat conversion instructions
+
+test with rounding mode 0
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 1
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 2
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 3
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 4
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 5
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 6
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 7
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+
+test with rounding mode 0
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 1
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 2
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 3
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 4
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 5
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 6
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 7
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+
+test with rounding mode 0
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 1
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 2
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 3
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 4
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 5
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 6
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 7
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+
+test with rounding mode 0
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+
+test with rounding mode 0
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 1
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 2
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 3
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 4
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 5
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 6
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 7
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+
+test with rounding mode 0
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+Test DFP shift instructions
+
+test with rounding mode 0
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 1
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 2
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 3
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 4
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 5
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 6
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 7
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+
+test with rounding mode 0
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 1
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 2
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 3
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 4
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 5
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 6
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 7
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+Test DCFFIX and DCFFIXQ instructions
+
+test with rounding mode 0
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 1
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 2
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 3
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 4
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 5
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 6
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 7
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+
+test with rounding mode 0
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 1
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 2
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 3
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 4
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 5
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 6
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 7
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
diff --git a/main/none/tests/ppc32/test_dfp2.stdout.exp_Without_dcffix b/main/none/tests/ppc32/test_dfp2.stdout.exp_Without_dcffix
new file mode 100644
index 0000000..419a036
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp2.stdout.exp_Without_dcffix
@@ -0,0 +1,1606 @@
+Test DFP fomat conversion instructions
+
+test with rounding mode 0
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 1
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 2
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 3
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 4
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 5
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 6
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 7
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+
+test with rounding mode 0
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 1
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 2
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 3
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 4
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 5
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 6
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 7
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+
+test with rounding mode 0
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 1
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 2
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 3
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 4
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 5
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 6
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 7
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+
+test with rounding mode 0
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+
+test with rounding mode 0
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 1
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 2
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 3
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 4
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 5
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 6
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 7
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+
+test with rounding mode 0
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+Test DFP shift instructions
+
+test with rounding mode 0
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 1
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 2
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 3
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 4
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 5
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 6
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 7
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+
+test with rounding mode 0
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 1
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 2
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 3
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 4
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 5
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 6
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 7
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+Test DCFFIX and DCFFIXQ instructions
+
+test with rounding mode 0
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 1
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 2
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 3
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 4
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 5
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 6
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 7
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
diff --git a/main/none/tests/ppc32/test_dfp2.vgtest b/main/none/tests/ppc32/test_dfp2.vgtest
new file mode 100644
index 0000000..7fe6c16
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp2.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp2
diff --git a/main/none/tests/ppc32/test_dfp3.c b/main/none/tests/ppc32/test_dfp3.c
new file mode 100644
index 0000000..4fe3137
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp3.c
@@ -0,0 +1,1263 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+static void _test_drintx(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drintn(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+
+static void _test_diex(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("diex %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dxex(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("dxex %0, %1" : "=f" (f18) : "f" (f16));
+}
+
+static void _test_dcmpo(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpo 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpo 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpo 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpo 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpo 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpo 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpo 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpo 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dcmpu(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpu 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpu 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpu 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpu 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpu 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpu 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpu 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpu 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+// Quad instruction testing
+static void _test_drintxq(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drintnq(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_diexq(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("diexq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dxexq(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("dxexq %0, %1" : "=f" (f18) : "f" (f16));
+}
+
+static void _test_dcmpoq(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF );
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpoq 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpoq 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpoq 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpoq 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpoq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpoq 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpoq 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpoq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dcmpuq(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpuq 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpuq 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpuq 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpuq 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpuq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpuq 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpuq 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpuq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drrnd(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 31) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drrndq(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%dn", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dqua(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dquaq(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static int TE_vals[] = { -16, -2, 0, 5};
+#define TE_VAL_LEN sizeof(TE_vals)/sizeof(int)
+static Bool __is_TE_val(int x)
+{
+ int i;
+ for (i = 0; i < TE_VAL_LEN; i++) {
+ if (x==TE_vals[i])
+ return True;
+ }
+ return False;
+}
+
+static void _test_dquai(int TE, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || !__is_TE_val(TE)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", TE, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 3:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dquaiq(int TE, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || !__is_TE_val(TE)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", TE, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 3:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+
+typedef void (*test_func_t)(int a, int b);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+// Both Long and Quad arrays of DFP values should have the same length.
+// If that length is changed, t
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+} dfp_test_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_func_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+
+static dfp_one_arg_test_t
+dfp_quai_tests[] = {
+ { &_test_dquai, "dquai", LONG_TEST, "[QI]"},
+ { &_test_dquaiq, "dquaiq", QUAD_TEST, "[QI]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_quai_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp;
+
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_quai_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_quai_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int TE, RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (TE = 0; TE < TE_VAL_LEN; TE++) {
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(TE_vals[TE], RMC);
+ res = f18;
+ printf("%s (RMC=%2d, TE=%3d) %s %016llx", test_def.name, RMC,
+ TE_vals[TE], test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_test_t
+dfp_qua_tests[] = {
+ { &_test_dqua, "dqua", dfp_2args_x1, 25, LONG_TEST, "[Q]"},
+ { &_test_dquaq, "dquaq", dfp_2args_x1, 25, QUAD_TEST, "[Q]"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_qua_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double res, d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ int k = 0;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_qua_tests[k].test_func)) {
+ int i, RMC;
+ dfp_test_t test_def = dfp_qua_tests[k];
+
+ for (i = 0; i < test_def.num_tests; i++) {
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_def.targs[i].fra_idx];
+ u1 = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(-1, RMC);
+ res = f18;
+ printf("%s (RMC=%2d) %s %016llx", test_def.name, RMC, test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(", %016llx => %016llx\n", u1, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx, %016llx %016llx ==> %016llx %016llx\n",u0x, u1, u1x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_rrnd_tests[] = {
+ { &_test_drrnd, "drrnd", LONG_TEST, "[RR]"},
+ { &_test_drrndq, "drrndq", QUAD_TEST, "[RR]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_rrnd_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp, reference_sig, *reference_sig_p;
+ long long reference_sig_vals[] = {0ULL, 2ULL, 6ULL, 63ULL};
+ int num_reference_sig_vals = sizeof(reference_sig_vals)/sizeof(long long);
+
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ reference_sig_p = &reference_sig;
+
+ while ((func = dfp_rrnd_tests[k].test_func)) {
+ int i, j;
+ dfp_one_arg_test_t test_def = dfp_rrnd_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (j = 0; j < num_reference_sig_vals; j++) {
+ *(long long *)reference_sig_p = reference_sig_vals[j];
+ f14 = reference_sig;
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(-1, RMC);
+ res = f18;
+ printf("%s (RMC=%d, ref sig=%d) %s%016llx", test_def.name, RMC,
+ (int)reference_sig_vals[j], test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_xiex_tests[] = {
+ { &_test_diex, "diex", LONG_TEST, ">>"},
+ { &_test_diexq, "diexq", QUAD_TEST, ">>"},
+ { &_test_dxex, "dxex", LONG_TEST, "<<"},
+ { &_test_dxexq, "dxexq", QUAD_TEST, "<<"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_xiex_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp, target_exp, *target_exp_p;
+ /* The first two positions are placeholders and will be filled in later,
+ * based on the precision of the DFP argument.
+ */
+ long long target_exp_vals[] = {0ULL, 0ULL, 0ULL, -1ULL, -2ULL, -3ULL, -4ULL, -5ULL};
+ int num_exp_vals = sizeof(target_exp_vals)/sizeof(long long);
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ target_exp_p = &target_exp;
+
+ while ((func = dfp_xiex_tests[k].test_func)) {
+ int i;
+ Bool insert_insn = False;
+ dfp_one_arg_test_t test_def = dfp_xiex_tests[k];
+
+ if (!strncmp(test_def.name, "di", 2))
+ insert_insn = True;
+
+ if (test_def.precision == QUAD_TEST) {
+ target_exp_vals[0] = 12288ULL; // > max biased exponent
+ target_exp_vals[1] = 5235ULL;
+ } else {
+ target_exp_vals[0] = 768ULL; // > max biased exponent
+ target_exp_vals[1] = 355ULL;
+ }
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ unsigned int j;
+
+ if (test_def.precision == QUAD_TEST) {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ } else {
+ u0 = dfp64_vals[i];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ if (!insert_insn) {
+ // This is just for extract insns (dexex[q])
+ (*func)(0, 0);
+ res = f18;
+ printf("%s %s ", test_def.name, test_def.op);
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx => %016llx\n", u0,
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf("%016llx %016llx ==> %016llx %016llx\n", u0, u0x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ continue;
+ }
+ // The following for-loop is just for insert insns (diex[q])
+ for (j = 0; j < num_exp_vals; j++) {
+ *(long long *)target_exp_p = target_exp_vals[j];
+ f14 = target_exp;
+ (*func)(0, 0);
+ res = f18;
+ printf("%s %s %5d, ", test_def.name, test_def.op, (int)target_exp_vals[j]);
+
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx => %016llx\n", u0,
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf("%016llx %016llx ==> %016llx %016llx\n", u0, u0x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_one_arg_test_t
+dfp_rint_tests[] = {
+ { &_test_drintn, "drintn", LONG_TEST, "~"},
+ { &_test_drintnq, "drintnq", QUAD_TEST, "~"},
+ { &_test_drintx, "drintx", LONG_TEST, "~"},
+ { &_test_drintxq, "drintxq", QUAD_TEST, "~"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_rint_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp;
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_rint_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_rint_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int R, RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (R = 0; R < 2; R++) {
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(R, RMC);
+ res = f18;
+ printf("%s (RM=%d) %s%016llx", test_def.name, (RMC + (R << 2)), test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_test_t
+dfp_cmp_tests[] = {
+ { &_test_dcmpo, "dcmpo", dfp_2args_x1, 25, LONG_TEST, "<>"},
+ { &_test_dcmpoq, "dcmpoq", dfp_2args_x1, 25, QUAD_TEST, "<>"},
+ { &_test_dcmpu, "dcmpu", dfp_2args_x1, 25, LONG_TEST, "<>"},
+ { &_test_dcmpuq, "dcmpuq", dfp_2args_x1, 25, QUAD_TEST, "<>"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_cmp_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ /* BF is a 3-bit instruction field that indicates the CR field in which the
+ * result of the compare should be placed. We won't iterate through all
+ * 8 possible BF values since storing compare results to a given field is
+ * a well-tested mechanism in VEX. But we will test two BF values, just as
+ * a sniff-test.
+ */
+ int k = 0, BF;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_cmp_tests[k].test_func)) {
+ int i, repeat = 1;
+ dfp_test_t test_def = dfp_cmp_tests[k];
+ BF = 0;
+
+again:
+ for (i = 0; i < test_def.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_def.targs[i].fra_idx];
+ u1 = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, 0);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s %016llx", test_def.name, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" %s %016llx => %x (BF=%d)\n",
+ test_def.op, u1, condreg, BF);
+ } else {
+ printf(" %016llx %s %016llx %016llx ==> %x (BF=%d)\n",
+ u0x, test_def.op, u1, u1x,
+ condreg, BF);
+ }
+ }
+ if (repeat) {
+ repeat = 0;
+ BF = 5;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_cmp_ops,
+ "Test DFP compare instructions"},
+ { &test_dfp_rint_ops,
+ "Test DFP round instructions"},
+ { &test_dfp_xiex_ops,
+ "Test DFP insert/extract instructions"},
+ { &test_dfp_rrnd_ops,
+ "Test DFP reround instructions"},
+ { &test_dfp_qua_ops,
+ "Test DFP quantize instructions"},
+ { &test_dfp_quai_ops,
+ "Test DFP quantize immediate instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc32/test_dfp3.stderr.exp b/main/none/tests/ppc32/test_dfp3.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp3.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc32/test_dfp3.stdout.exp b/main/none/tests/ppc32/test_dfp3.stdout.exp
new file mode 100644
index 0000000..5c21dc0
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp3.stdout.exp
@@ -0,0 +1,2248 @@
+Test DFP compare instructions
+dcmpo 2234000000000e50 <> 223400000014c000 => 8 (BF=0)
+dcmpo a2340000000000e0 <> 223400000014c000 => 8 (BF=0)
+dcmpo 22240000000000cf <> a21400010a395bcf => 4 (BF=0)
+dcmpo 2234000000000e50 <> 000400000089b000 => 4 (BF=0)
+dcmpo a2340000000000e0 <> a21400010a395bcf => 8 (BF=0)
+dcmpo 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=0)
+dcmpo 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=0)
+dcmpo 2238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpo 2238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpo a238000000000000 <> 2234000000000e50 => 8 (BF=0)
+dcmpo a238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpo a238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpo 2238000000000000 <> a238000000000000 => 2 (BF=0)
+dcmpo fc00000000000000 <> f800000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> 223400000014c000 => 1 (BF=0)
+dcmpo fc00000000000000 <> 7800000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> fc00000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpo f800000000000000 <> f800000000000000 => 2 (BF=0)
+dcmpo f800000000000000 <> 22240000000000cf => 8 (BF=0)
+dcmpo f800000000000000 <> 7a34000000000000 => 8 (BF=0)
+dcmpo 2234000000000e50 <> 223400000014c000 => 8 (BF=5)
+dcmpo a2340000000000e0 <> 223400000014c000 => 8 (BF=5)
+dcmpo 22240000000000cf <> a21400010a395bcf => 4 (BF=5)
+dcmpo 2234000000000e50 <> 000400000089b000 => 4 (BF=5)
+dcmpo a2340000000000e0 <> a21400010a395bcf => 8 (BF=5)
+dcmpo 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=5)
+dcmpo 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=5)
+dcmpo 2238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpo 2238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpo a238000000000000 <> 2234000000000e50 => 8 (BF=5)
+dcmpo a238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpo a238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpo 2238000000000000 <> a238000000000000 => 2 (BF=5)
+dcmpo fc00000000000000 <> f800000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> 223400000014c000 => 1 (BF=5)
+dcmpo fc00000000000000 <> 7800000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> fc00000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpo f800000000000000 <> f800000000000000 => 2 (BF=5)
+dcmpo f800000000000000 <> 22240000000000cf => 8 (BF=5)
+dcmpo f800000000000000 <> 7a34000000000000 => 8 (BF=5)
+
+dcmpoq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=0)
+dcmpoq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=0)
+dcmpoq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=0)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=5)
+dcmpoq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=5)
+dcmpoq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=5)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=5)
+
+dcmpu 2234000000000e50 <> 223400000014c000 => 8 (BF=0)
+dcmpu a2340000000000e0 <> 223400000014c000 => 8 (BF=0)
+dcmpu 22240000000000cf <> a21400010a395bcf => 4 (BF=0)
+dcmpu 2234000000000e50 <> 000400000089b000 => 4 (BF=0)
+dcmpu a2340000000000e0 <> a21400010a395bcf => 8 (BF=0)
+dcmpu 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=0)
+dcmpu 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=0)
+dcmpu 2238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpu 2238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpu a238000000000000 <> 2234000000000e50 => 8 (BF=0)
+dcmpu a238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpu a238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpu 2238000000000000 <> a238000000000000 => 2 (BF=0)
+dcmpu fc00000000000000 <> f800000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> 223400000014c000 => 1 (BF=0)
+dcmpu fc00000000000000 <> 7800000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> fc00000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpu f800000000000000 <> f800000000000000 => 2 (BF=0)
+dcmpu f800000000000000 <> 22240000000000cf => 8 (BF=0)
+dcmpu f800000000000000 <> 7a34000000000000 => 8 (BF=0)
+dcmpu 2234000000000e50 <> 223400000014c000 => 8 (BF=5)
+dcmpu a2340000000000e0 <> 223400000014c000 => 8 (BF=5)
+dcmpu 22240000000000cf <> a21400010a395bcf => 4 (BF=5)
+dcmpu 2234000000000e50 <> 000400000089b000 => 4 (BF=5)
+dcmpu a2340000000000e0 <> a21400010a395bcf => 8 (BF=5)
+dcmpu 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=5)
+dcmpu 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=5)
+dcmpu 2238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpu 2238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpu a238000000000000 <> 2234000000000e50 => 8 (BF=5)
+dcmpu a238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpu a238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpu 2238000000000000 <> a238000000000000 => 2 (BF=5)
+dcmpu fc00000000000000 <> f800000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> 223400000014c000 => 1 (BF=5)
+dcmpu fc00000000000000 <> 7800000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> fc00000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpu f800000000000000 <> f800000000000000 => 2 (BF=5)
+dcmpu f800000000000000 <> 22240000000000cf => 8 (BF=5)
+dcmpu f800000000000000 <> 7a34000000000000 => 8 (BF=5)
+
+dcmpuq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=0)
+dcmpuq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=0)
+dcmpuq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=0)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=5)
+dcmpuq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=5)
+dcmpuq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=5)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=5)
+
+Test DFP round instructions
+drintn (RM=0) ~2234000000000e50 => 22380000000001c5
+drintn (RM=1) ~2234000000000e50 => 22380000000001c5
+drintn (RM=2) ~2234000000000e50 => 22380000000001c5
+drintn (RM=3) ~2234000000000e50 => 22380000000001c5
+drintn (RM=4) ~2234000000000e50 => 22380000000001c5
+drintn (RM=5) ~2234000000000e50 => 22380000000001c5
+drintn (RM=6) ~2234000000000e50 => 22380000000001c5
+drintn (RM=7) ~2234000000000e50 => 22380000000001c5
+drintn (RM=0) ~223400000014c000 => 2238000000028c00
+drintn (RM=1) ~223400000014c000 => 2238000000028c00
+drintn (RM=2) ~223400000014c000 => 2238000000028c00
+drintn (RM=3) ~223400000014c000 => 2238000000028c00
+drintn (RM=4) ~223400000014c000 => 2238000000028c00
+drintn (RM=5) ~223400000014c000 => 2238000000028c00
+drintn (RM=6) ~223400000014c000 => 2238000000028c00
+drintn (RM=7) ~223400000014c000 => 2238000000028c00
+drintn (RM=0) ~a2340000000000e0 => a238000000000016
+drintn (RM=1) ~a2340000000000e0 => a238000000000016
+drintn (RM=2) ~a2340000000000e0 => a238000000000016
+drintn (RM=3) ~a2340000000000e0 => a238000000000016
+drintn (RM=4) ~a2340000000000e0 => a238000000000016
+drintn (RM=5) ~a2340000000000e0 => a238000000000016
+drintn (RM=6) ~a2340000000000e0 => a238000000000016
+drintn (RM=7) ~a2340000000000e0 => a238000000000016
+drintn (RM=0) ~22240000000000cf => 2238000000000000
+drintn (RM=1) ~22240000000000cf => 2238000000000000
+drintn (RM=2) ~22240000000000cf => 2238000000000000
+drintn (RM=3) ~22240000000000cf => 2238000000000000
+drintn (RM=4) ~22240000000000cf => 2238000000000001
+drintn (RM=5) ~22240000000000cf => 2238000000000000
+drintn (RM=6) ~22240000000000cf => 2238000000000001
+drintn (RM=7) ~22240000000000cf => 2238000000000000
+drintn (RM=0) ~a21400010a395bcf => a238000000000004
+drintn (RM=1) ~a21400010a395bcf => a238000000000004
+drintn (RM=2) ~a21400010a395bcf => a238000000000004
+drintn (RM=3) ~a21400010a395bcf => a238000000000004
+drintn (RM=4) ~a21400010a395bcf => a238000000000004
+drintn (RM=5) ~a21400010a395bcf => a238000000000005
+drintn (RM=6) ~a21400010a395bcf => a238000000000005
+drintn (RM=7) ~a21400010a395bcf => a238000000000004
+drintn (RM=0) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=1) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=2) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=3) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=4) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=5) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=6) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=7) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=0) ~000400000089b000 => 2238000000000000
+drintn (RM=1) ~000400000089b000 => 2238000000000000
+drintn (RM=2) ~000400000089b000 => 2238000000000000
+drintn (RM=3) ~000400000089b000 => 2238000000000000
+drintn (RM=4) ~000400000089b000 => 2238000000000001
+drintn (RM=5) ~000400000089b000 => 2238000000000000
+drintn (RM=6) ~000400000089b000 => 2238000000000001
+drintn (RM=7) ~000400000089b000 => 2238000000000000
+drintn (RM=0) ~2238000000000000 => 2238000000000000
+drintn (RM=1) ~2238000000000000 => 2238000000000000
+drintn (RM=2) ~2238000000000000 => 2238000000000000
+drintn (RM=3) ~2238000000000000 => 2238000000000000
+drintn (RM=4) ~2238000000000000 => 2238000000000000
+drintn (RM=5) ~2238000000000000 => 2238000000000000
+drintn (RM=6) ~2238000000000000 => 2238000000000000
+drintn (RM=7) ~2238000000000000 => 2238000000000000
+drintn (RM=0) ~a238000000000000 => a238000000000000
+drintn (RM=1) ~a238000000000000 => a238000000000000
+drintn (RM=2) ~a238000000000000 => a238000000000000
+drintn (RM=3) ~a238000000000000 => a238000000000000
+drintn (RM=4) ~a238000000000000 => a238000000000000
+drintn (RM=5) ~a238000000000000 => a238000000000000
+drintn (RM=6) ~a238000000000000 => a238000000000000
+drintn (RM=7) ~a238000000000000 => a238000000000000
+drintn (RM=0) ~4248000000000000 => 4248000000000000
+drintn (RM=1) ~4248000000000000 => 4248000000000000
+drintn (RM=2) ~4248000000000000 => 4248000000000000
+drintn (RM=3) ~4248000000000000 => 4248000000000000
+drintn (RM=4) ~4248000000000000 => 4248000000000000
+drintn (RM=5) ~4248000000000000 => 4248000000000000
+drintn (RM=6) ~4248000000000000 => 4248000000000000
+drintn (RM=7) ~4248000000000000 => 4248000000000000
+drintn (RM=0) ~7e34000000000111 => 7c00000000000111
+drintn (RM=1) ~7e34000000000111 => 7c00000000000111
+drintn (RM=2) ~7e34000000000111 => 7c00000000000111
+drintn (RM=3) ~7e34000000000111 => 7c00000000000111
+drintn (RM=4) ~7e34000000000111 => 7c00000000000111
+drintn (RM=5) ~7e34000000000111 => 7c00000000000111
+drintn (RM=6) ~7e34000000000111 => 7c00000000000111
+drintn (RM=7) ~7e34000000000111 => 7c00000000000111
+drintn (RM=0) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=1) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=2) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=3) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=4) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=5) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=6) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=7) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=0) ~fc00000000000000 => fc00000000000000
+drintn (RM=1) ~fc00000000000000 => fc00000000000000
+drintn (RM=2) ~fc00000000000000 => fc00000000000000
+drintn (RM=3) ~fc00000000000000 => fc00000000000000
+drintn (RM=4) ~fc00000000000000 => fc00000000000000
+drintn (RM=5) ~fc00000000000000 => fc00000000000000
+drintn (RM=6) ~fc00000000000000 => fc00000000000000
+drintn (RM=7) ~fc00000000000000 => fc00000000000000
+drintn (RM=0) ~7800000000000000 => 7800000000000000
+drintn (RM=1) ~7800000000000000 => 7800000000000000
+drintn (RM=2) ~7800000000000000 => 7800000000000000
+drintn (RM=3) ~7800000000000000 => 7800000000000000
+drintn (RM=4) ~7800000000000000 => 7800000000000000
+drintn (RM=5) ~7800000000000000 => 7800000000000000
+drintn (RM=6) ~7800000000000000 => 7800000000000000
+drintn (RM=7) ~7800000000000000 => 7800000000000000
+drintn (RM=0) ~f800000000000000 => f800000000000000
+drintn (RM=1) ~f800000000000000 => f800000000000000
+drintn (RM=2) ~f800000000000000 => f800000000000000
+drintn (RM=3) ~f800000000000000 => f800000000000000
+drintn (RM=4) ~f800000000000000 => f800000000000000
+drintn (RM=5) ~f800000000000000 => f800000000000000
+drintn (RM=6) ~f800000000000000 => f800000000000000
+drintn (RM=7) ~f800000000000000 => f800000000000000
+drintn (RM=0) ~7a34000000000000 => 7800000000000000
+drintn (RM=1) ~7a34000000000000 => 7800000000000000
+drintn (RM=2) ~7a34000000000000 => 7800000000000000
+drintn (RM=3) ~7a34000000000000 => 7800000000000000
+drintn (RM=4) ~7a34000000000000 => 7800000000000000
+drintn (RM=5) ~7a34000000000000 => 7800000000000000
+drintn (RM=6) ~7a34000000000000 => 7800000000000000
+drintn (RM=7) ~7a34000000000000 => 7800000000000000
+
+drintnq (RM=0) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=1) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=2) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=3) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=4) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=5) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=6) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=7) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=0) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=1) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=2) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=3) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=4) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=5) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=6) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=7) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=0) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=1) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=2) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=3) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=4) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=5) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=6) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=7) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=0) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=1) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=2) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=3) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=4) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=5) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintnq (RM=6) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintnq (RM=7) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=0) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=5) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=7) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=1) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=2) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=3) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=4) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=5) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=6) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=7) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=0) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=1) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=2) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=3) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=4) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=5) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=6) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=7) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=0) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=1) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=2) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=3) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=4) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=5) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=6) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=7) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=0) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=1) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=2) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=3) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=4) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=5) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=6) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=7) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=0) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=1) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=2) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=3) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=4) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=5) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=6) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=7) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=0) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=1) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=2) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=3) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=4) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=5) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=6) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=7) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=0) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=1) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=2) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=3) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=4) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=5) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=6) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=7) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=0) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=1) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=2) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=3) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=4) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=5) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=6) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=7) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+drintx (RM=0) ~2234000000000e50 => 22380000000001c5
+drintx (RM=1) ~2234000000000e50 => 22380000000001c5
+drintx (RM=2) ~2234000000000e50 => 22380000000001c5
+drintx (RM=3) ~2234000000000e50 => 22380000000001c5
+drintx (RM=4) ~2234000000000e50 => 22380000000001c5
+drintx (RM=5) ~2234000000000e50 => 22380000000001c5
+drintx (RM=6) ~2234000000000e50 => 22380000000001c5
+drintx (RM=7) ~2234000000000e50 => 22380000000001c5
+drintx (RM=0) ~223400000014c000 => 2238000000028c00
+drintx (RM=1) ~223400000014c000 => 2238000000028c00
+drintx (RM=2) ~223400000014c000 => 2238000000028c00
+drintx (RM=3) ~223400000014c000 => 2238000000028c00
+drintx (RM=4) ~223400000014c000 => 2238000000028c00
+drintx (RM=5) ~223400000014c000 => 2238000000028c00
+drintx (RM=6) ~223400000014c000 => 2238000000028c00
+drintx (RM=7) ~223400000014c000 => 2238000000028c00
+drintx (RM=0) ~a2340000000000e0 => a238000000000016
+drintx (RM=1) ~a2340000000000e0 => a238000000000016
+drintx (RM=2) ~a2340000000000e0 => a238000000000016
+drintx (RM=3) ~a2340000000000e0 => a238000000000016
+drintx (RM=4) ~a2340000000000e0 => a238000000000016
+drintx (RM=5) ~a2340000000000e0 => a238000000000016
+drintx (RM=6) ~a2340000000000e0 => a238000000000016
+drintx (RM=7) ~a2340000000000e0 => a238000000000016
+drintx (RM=0) ~22240000000000cf => 2238000000000000
+drintx (RM=1) ~22240000000000cf => 2238000000000000
+drintx (RM=2) ~22240000000000cf => 2238000000000000
+drintx (RM=3) ~22240000000000cf => 2238000000000000
+drintx (RM=4) ~22240000000000cf => 2238000000000001
+drintx (RM=5) ~22240000000000cf => 2238000000000000
+drintx (RM=6) ~22240000000000cf => 2238000000000001
+drintx (RM=7) ~22240000000000cf => 2238000000000000
+drintx (RM=0) ~a21400010a395bcf => a238000000000004
+drintx (RM=1) ~a21400010a395bcf => a238000000000004
+drintx (RM=2) ~a21400010a395bcf => a238000000000004
+drintx (RM=3) ~a21400010a395bcf => a238000000000004
+drintx (RM=4) ~a21400010a395bcf => a238000000000004
+drintx (RM=5) ~a21400010a395bcf => a238000000000005
+drintx (RM=6) ~a21400010a395bcf => a238000000000005
+drintx (RM=7) ~a21400010a395bcf => a238000000000004
+drintx (RM=0) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=1) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=2) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=3) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=4) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=5) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=6) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=7) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=0) ~000400000089b000 => 2238000000000000
+drintx (RM=1) ~000400000089b000 => 2238000000000000
+drintx (RM=2) ~000400000089b000 => 2238000000000000
+drintx (RM=3) ~000400000089b000 => 2238000000000000
+drintx (RM=4) ~000400000089b000 => 2238000000000001
+drintx (RM=5) ~000400000089b000 => 2238000000000000
+drintx (RM=6) ~000400000089b000 => 2238000000000001
+drintx (RM=7) ~000400000089b000 => 2238000000000000
+drintx (RM=0) ~2238000000000000 => 2238000000000000
+drintx (RM=1) ~2238000000000000 => 2238000000000000
+drintx (RM=2) ~2238000000000000 => 2238000000000000
+drintx (RM=3) ~2238000000000000 => 2238000000000000
+drintx (RM=4) ~2238000000000000 => 2238000000000000
+drintx (RM=5) ~2238000000000000 => 2238000000000000
+drintx (RM=6) ~2238000000000000 => 2238000000000000
+drintx (RM=7) ~2238000000000000 => 2238000000000000
+drintx (RM=0) ~a238000000000000 => a238000000000000
+drintx (RM=1) ~a238000000000000 => a238000000000000
+drintx (RM=2) ~a238000000000000 => a238000000000000
+drintx (RM=3) ~a238000000000000 => a238000000000000
+drintx (RM=4) ~a238000000000000 => a238000000000000
+drintx (RM=5) ~a238000000000000 => a238000000000000
+drintx (RM=6) ~a238000000000000 => a238000000000000
+drintx (RM=7) ~a238000000000000 => a238000000000000
+drintx (RM=0) ~4248000000000000 => 4248000000000000
+drintx (RM=1) ~4248000000000000 => 4248000000000000
+drintx (RM=2) ~4248000000000000 => 4248000000000000
+drintx (RM=3) ~4248000000000000 => 4248000000000000
+drintx (RM=4) ~4248000000000000 => 4248000000000000
+drintx (RM=5) ~4248000000000000 => 4248000000000000
+drintx (RM=6) ~4248000000000000 => 4248000000000000
+drintx (RM=7) ~4248000000000000 => 4248000000000000
+drintx (RM=0) ~7e34000000000111 => 7c00000000000111
+drintx (RM=1) ~7e34000000000111 => 7c00000000000111
+drintx (RM=2) ~7e34000000000111 => 7c00000000000111
+drintx (RM=3) ~7e34000000000111 => 7c00000000000111
+drintx (RM=4) ~7e34000000000111 => 7c00000000000111
+drintx (RM=5) ~7e34000000000111 => 7c00000000000111
+drintx (RM=6) ~7e34000000000111 => 7c00000000000111
+drintx (RM=7) ~7e34000000000111 => 7c00000000000111
+drintx (RM=0) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=1) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=2) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=3) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=4) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=5) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=6) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=7) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=0) ~fc00000000000000 => fc00000000000000
+drintx (RM=1) ~fc00000000000000 => fc00000000000000
+drintx (RM=2) ~fc00000000000000 => fc00000000000000
+drintx (RM=3) ~fc00000000000000 => fc00000000000000
+drintx (RM=4) ~fc00000000000000 => fc00000000000000
+drintx (RM=5) ~fc00000000000000 => fc00000000000000
+drintx (RM=6) ~fc00000000000000 => fc00000000000000
+drintx (RM=7) ~fc00000000000000 => fc00000000000000
+drintx (RM=0) ~7800000000000000 => 7800000000000000
+drintx (RM=1) ~7800000000000000 => 7800000000000000
+drintx (RM=2) ~7800000000000000 => 7800000000000000
+drintx (RM=3) ~7800000000000000 => 7800000000000000
+drintx (RM=4) ~7800000000000000 => 7800000000000000
+drintx (RM=5) ~7800000000000000 => 7800000000000000
+drintx (RM=6) ~7800000000000000 => 7800000000000000
+drintx (RM=7) ~7800000000000000 => 7800000000000000
+drintx (RM=0) ~f800000000000000 => f800000000000000
+drintx (RM=1) ~f800000000000000 => f800000000000000
+drintx (RM=2) ~f800000000000000 => f800000000000000
+drintx (RM=3) ~f800000000000000 => f800000000000000
+drintx (RM=4) ~f800000000000000 => f800000000000000
+drintx (RM=5) ~f800000000000000 => f800000000000000
+drintx (RM=6) ~f800000000000000 => f800000000000000
+drintx (RM=7) ~f800000000000000 => f800000000000000
+drintx (RM=0) ~7a34000000000000 => 7800000000000000
+drintx (RM=1) ~7a34000000000000 => 7800000000000000
+drintx (RM=2) ~7a34000000000000 => 7800000000000000
+drintx (RM=3) ~7a34000000000000 => 7800000000000000
+drintx (RM=4) ~7a34000000000000 => 7800000000000000
+drintx (RM=5) ~7a34000000000000 => 7800000000000000
+drintx (RM=6) ~7a34000000000000 => 7800000000000000
+drintx (RM=7) ~7a34000000000000 => 7800000000000000
+
+drintxq (RM=0) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=1) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=2) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=3) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=4) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=5) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=6) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=7) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=0) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=1) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=2) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=3) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=4) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=5) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=6) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=7) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=0) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=1) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=2) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=3) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=4) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=5) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=6) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=7) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=0) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=1) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=2) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=3) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=4) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=5) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintxq (RM=6) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintxq (RM=7) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=0) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=5) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=7) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=1) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=2) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=3) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=4) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=5) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=6) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=7) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=0) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=1) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=2) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=3) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=4) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=5) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=6) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=7) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=0) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=1) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=2) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=3) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=4) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=5) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=6) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=7) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=0) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=1) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=2) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=3) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=4) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=5) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=6) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=7) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=0) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=1) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=2) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=3) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=4) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=5) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=6) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=7) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=0) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=1) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=2) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=3) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=4) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=5) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=6) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=7) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=0) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=1) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=2) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=3) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=4) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=5) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=6) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=7) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=0) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=1) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=2) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=3) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=4) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=5) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=6) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=7) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP insert/extract instructions
+diex >> 768, 2234000000000e50 => 7c00000000000e50
+diex >> 355, 2234000000000e50 => 218c000000000e50
+diex >> 0, 2234000000000e50 => 0000000000000e50
+diex >> -1, 2234000000000e50 => 7800000000000e50
+diex >> -2, 2234000000000e50 => 7c00000000000e50
+diex >> -3, 2234000000000e50 => 7e00000000000e50
+diex >> -4, 2234000000000e50 => 7c00000000000e50
+diex >> -5, 2234000000000e50 => 7c00000000000e50
+diex >> 768, 223400000014c000 => 7c0000000014c000
+diex >> 355, 223400000014c000 => 218c00000014c000
+diex >> 0, 223400000014c000 => 000000000014c000
+diex >> -1, 223400000014c000 => 780000000014c000
+diex >> -2, 223400000014c000 => 7c0000000014c000
+diex >> -3, 223400000014c000 => 7e0000000014c000
+diex >> -4, 223400000014c000 => 7c0000000014c000
+diex >> -5, 223400000014c000 => 7c0000000014c000
+diex >> 768, a2340000000000e0 => fc000000000000e0
+diex >> 355, a2340000000000e0 => a18c0000000000e0
+diex >> 0, a2340000000000e0 => 80000000000000e0
+diex >> -1, a2340000000000e0 => f8000000000000e0
+diex >> -2, a2340000000000e0 => fc000000000000e0
+diex >> -3, a2340000000000e0 => fe000000000000e0
+diex >> -4, a2340000000000e0 => fc000000000000e0
+diex >> -5, a2340000000000e0 => fc000000000000e0
+diex >> 768, 22240000000000cf => 7c000000000000cf
+diex >> 355, 22240000000000cf => 218c0000000000cf
+diex >> 0, 22240000000000cf => 00000000000000cf
+diex >> -1, 22240000000000cf => 78000000000000cf
+diex >> -2, 22240000000000cf => 7c000000000000cf
+diex >> -3, 22240000000000cf => 7e000000000000cf
+diex >> -4, 22240000000000cf => 7c000000000000cf
+diex >> -5, 22240000000000cf => 7c000000000000cf
+diex >> 768, a21400010a395bcf => fc0000010a395bcf
+diex >> 355, a21400010a395bcf => a18c00010a395bcf
+diex >> 0, a21400010a395bcf => 800000010a395bcf
+diex >> -1, a21400010a395bcf => f80000010a395bcf
+diex >> -2, a21400010a395bcf => fc0000010a395bcf
+diex >> -3, a21400010a395bcf => fe0000010a395bcf
+diex >> -4, a21400010a395bcf => fc0000010a395bcf
+diex >> -5, a21400010a395bcf => fc0000010a395bcf
+diex >> 768, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> 355, 6e4d3f1f534acdd4 => 6d8d3f1f534acdd4
+diex >> 0, 6e4d3f1f534acdd4 => 64013f1f534acdd4
+diex >> -1, 6e4d3f1f534acdd4 => 78013f1f534acdd4
+diex >> -2, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> -3, 6e4d3f1f534acdd4 => 7e013f1f534acdd4
+diex >> -4, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> -5, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> 768, 000400000089b000 => 7c0000000089b000
+diex >> 355, 000400000089b000 => 218c00000089b000
+diex >> 0, 000400000089b000 => 000000000089b000
+diex >> -1, 000400000089b000 => 780000000089b000
+diex >> -2, 000400000089b000 => 7c0000000089b000
+diex >> -3, 000400000089b000 => 7e0000000089b000
+diex >> -4, 000400000089b000 => 7c0000000089b000
+diex >> -5, 000400000089b000 => 7c0000000089b000
+diex >> 768, 2238000000000000 => 7c00000000000000
+diex >> 355, 2238000000000000 => 218c000000000000
+diex >> 0, 2238000000000000 => 0000000000000000
+diex >> -1, 2238000000000000 => 7800000000000000
+diex >> -2, 2238000000000000 => 7c00000000000000
+diex >> -3, 2238000000000000 => 7e00000000000000
+diex >> -4, 2238000000000000 => 7c00000000000000
+diex >> -5, 2238000000000000 => 7c00000000000000
+diex >> 768, a238000000000000 => fc00000000000000
+diex >> 355, a238000000000000 => a18c000000000000
+diex >> 0, a238000000000000 => 8000000000000000
+diex >> -1, a238000000000000 => f800000000000000
+diex >> -2, a238000000000000 => fc00000000000000
+diex >> -3, a238000000000000 => fe00000000000000
+diex >> -4, a238000000000000 => fc00000000000000
+diex >> -5, a238000000000000 => fc00000000000000
+diex >> 768, 4248000000000000 => 7c00000000000000
+diex >> 355, 4248000000000000 => 218c000000000000
+diex >> 0, 4248000000000000 => 0000000000000000
+diex >> -1, 4248000000000000 => 7800000000000000
+diex >> -2, 4248000000000000 => 7c00000000000000
+diex >> -3, 4248000000000000 => 7e00000000000000
+diex >> -4, 4248000000000000 => 7c00000000000000
+diex >> -5, 4248000000000000 => 7c00000000000000
+diex >> 768, 7e34000000000111 => 7c00000000000111
+diex >> 355, 7e34000000000111 => 218c000000000111
+diex >> 0, 7e34000000000111 => 0000000000000111
+diex >> -1, 7e34000000000111 => 7800000000000111
+diex >> -2, 7e34000000000111 => 7c00000000000111
+diex >> -3, 7e34000000000111 => 7e00000000000111
+diex >> -4, 7e34000000000111 => 7c00000000000111
+diex >> -5, 7e34000000000111 => 7c00000000000111
+diex >> 768, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> 355, fe000000d0e0a0d0 => a18c0000d0e0a0d0
+diex >> 0, fe000000d0e0a0d0 => 80000000d0e0a0d0
+diex >> -1, fe000000d0e0a0d0 => f8000000d0e0a0d0
+diex >> -2, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> -3, fe000000d0e0a0d0 => fe000000d0e0a0d0
+diex >> -4, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> -5, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> 768, fc00000000000000 => fc00000000000000
+diex >> 355, fc00000000000000 => a18c000000000000
+diex >> 0, fc00000000000000 => 8000000000000000
+diex >> -1, fc00000000000000 => f800000000000000
+diex >> -2, fc00000000000000 => fc00000000000000
+diex >> -3, fc00000000000000 => fe00000000000000
+diex >> -4, fc00000000000000 => fc00000000000000
+diex >> -5, fc00000000000000 => fc00000000000000
+diex >> 768, 7800000000000000 => 7c00000000000000
+diex >> 355, 7800000000000000 => 218c000000000000
+diex >> 0, 7800000000000000 => 0000000000000000
+diex >> -1, 7800000000000000 => 7800000000000000
+diex >> -2, 7800000000000000 => 7c00000000000000
+diex >> -3, 7800000000000000 => 7e00000000000000
+diex >> -4, 7800000000000000 => 7c00000000000000
+diex >> -5, 7800000000000000 => 7c00000000000000
+diex >> 768, f800000000000000 => fc00000000000000
+diex >> 355, f800000000000000 => a18c000000000000
+diex >> 0, f800000000000000 => 8000000000000000
+diex >> -1, f800000000000000 => f800000000000000
+diex >> -2, f800000000000000 => fc00000000000000
+diex >> -3, f800000000000000 => fe00000000000000
+diex >> -4, f800000000000000 => fc00000000000000
+diex >> -5, f800000000000000 => fc00000000000000
+diex >> 768, 7a34000000000000 => 7c00000000000000
+diex >> 355, 7a34000000000000 => 218c000000000000
+diex >> 0, 7a34000000000000 => 0000000000000000
+diex >> -1, 7a34000000000000 => 7800000000000000
+diex >> -2, 7a34000000000000 => 7c00000000000000
+diex >> -3, 7a34000000000000 => 7e00000000000000
+diex >> -4, 7a34000000000000 => 7c00000000000000
+diex >> -5, 7a34000000000000 => 7c00000000000000
+
+diexq >> 12288, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> 5235, 2207c00000000000 0000000000000e50 ==> 211cc00000000000 0000000000000e50
+diexq >> 0, 2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000000e50
+diexq >> -1, 2207c00000000000 0000000000000e50 ==> 7800000000000000 0000000000000e50
+diexq >> -2, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> -3, 2207c00000000000 0000000000000e50 ==> 7e00000000000000 0000000000000e50
+diexq >> -4, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> -5, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> 12288, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> 5235, 2207c00000000000 000000000014c000 ==> 211cc00000000000 000000000014c000
+diexq >> 0, 2207c00000000000 000000000014c000 ==> 0000000000000000 000000000014c000
+diexq >> -1, 2207c00000000000 000000000014c000 ==> 7800000000000000 000000000014c000
+diexq >> -2, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> -3, 2207c00000000000 000000000014c000 ==> 7e00000000000000 000000000014c000
+diexq >> -4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> -5, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> 12288, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> 5235, a207c00000000000 00000000000000e0 ==> a11cc00000000000 00000000000000e0
+diexq >> 0, a207c00000000000 00000000000000e0 ==> 8000000000000000 00000000000000e0
+diexq >> -1, a207c00000000000 00000000000000e0 ==> f800000000000000 00000000000000e0
+diexq >> -2, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> -3, a207c00000000000 00000000000000e0 ==> fe00000000000000 00000000000000e0
+diexq >> -4, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> -5, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> 12288, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> 5235, 2206c00000000000 00000000000000cf ==> 211cc00000000000 00000000000000cf
+diexq >> 0, 2206c00000000000 00000000000000cf ==> 0000000000000000 00000000000000cf
+diexq >> -1, 2206c00000000000 00000000000000cf ==> 7800000000000000 00000000000000cf
+diexq >> -2, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> -3, 2206c00000000000 00000000000000cf ==> 7e00000000000000 00000000000000cf
+diexq >> -4, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> -5, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> 12288, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> 5235, a205c00000000000 000000010a395bcf ==> a11cc00000000000 000000010a395bcf
+diexq >> 0, a205c00000000000 000000010a395bcf ==> 8000000000000000 000000010a395bcf
+diexq >> -1, a205c00000000000 000000010a395bcf ==> f800000000000000 000000010a395bcf
+diexq >> -2, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> -3, a205c00000000000 000000010a395bcf ==> fe00000000000000 000000010a395bcf
+diexq >> -4, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> -5, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> 12288, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> 5235, 6209400000fd0000 00253f1f534acdd4 ==> 691cc00000fd0000 00253f1f534acdd4
+diexq >> 0, 6209400000fd0000 00253f1f534acdd4 ==> 6000000000fd0000 00253f1f534acdd4
+diexq >> -1, 6209400000fd0000 00253f1f534acdd4 ==> 7800000000fd0000 00253f1f534acdd4
+diexq >> -2, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> -3, 6209400000fd0000 00253f1f534acdd4 ==> 7e00000000fd0000 00253f1f534acdd4
+diexq >> -4, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> -5, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> 12288, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> 5235, 000400000089b000 0a6000d000000049 ==> 211cc0000089b000 0a6000d000000049
+diexq >> 0, 000400000089b000 0a6000d000000049 ==> 000000000089b000 0a6000d000000049
+diexq >> -1, 000400000089b000 0a6000d000000049 ==> 780000000089b000 0a6000d000000049
+diexq >> -2, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> -3, 000400000089b000 0a6000d000000049 ==> 7e0000000089b000 0a6000d000000049
+diexq >> -4, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> -5, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> 12288, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 2208000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 2208000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 2208000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, a208000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, a208000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, a208000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, a208000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, a248000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, a248000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, a248000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, a248000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 7c00000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 7c00000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 7c00000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> 5235, fc00000000000000 c00100035b007700 ==> a11cc00000000000 c00100035b007700
+diexq >> 0, fc00000000000000 c00100035b007700 ==> 8000000000000000 c00100035b007700
+diexq >> -1, fc00000000000000 c00100035b007700 ==> f800000000000000 c00100035b007700
+diexq >> -2, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> -3, fc00000000000000 c00100035b007700 ==> fe00000000000000 c00100035b007700
+diexq >> -4, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> -5, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> 12288, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> 5235, 7e00000000000000 fe000000d0e0a0d0 ==> 211cc00000000000 fe000000d0e0a0d0
+diexq >> 0, 7e00000000000000 fe000000d0e0a0d0 ==> 0000000000000000 fe000000d0e0a0d0
+diexq >> -1, 7e00000000000000 fe000000d0e0a0d0 ==> 7800000000000000 fe000000d0e0a0d0
+diexq >> -2, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> -3, 7e00000000000000 fe000000d0e0a0d0 ==> 7e00000000000000 fe000000d0e0a0d0
+diexq >> -4, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> -5, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> 12288, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 7800000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 7800000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, f800000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, f800000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, f800000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, f900000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, f900000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, f900000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+
+dxex << 2234000000000e50 => 000000000000018d
+dxex << 223400000014c000 => 000000000000018d
+dxex << a2340000000000e0 => 000000000000018d
+dxex << 22240000000000cf => 0000000000000189
+dxex << a21400010a395bcf => 0000000000000185
+dxex << 6e4d3f1f534acdd4 => 0000000000000193
+dxex << 000400000089b000 => 0000000000000001
+dxex << 2238000000000000 => 000000000000018e
+dxex << a238000000000000 => 000000000000018e
+dxex << 4248000000000000 => 0000000000000292
+dxex << 7e34000000000111 => fffffffffffffffd
+dxex << fe000000d0e0a0d0 => fffffffffffffffd
+dxex << fc00000000000000 => fffffffffffffffe
+dxex << 7800000000000000 => ffffffffffffffff
+dxex << f800000000000000 => ffffffffffffffff
+dxex << 7a34000000000000 => ffffffffffffffff
+
+dxexq << 2207c00000000000 0000000000000e50 ==> 000000000000181f 0000000000000000
+dxexq << 2207c00000000000 000000000014c000 ==> 000000000000181f 0000000000000000
+dxexq << a207c00000000000 00000000000000e0 ==> 000000000000181f 0000000000000000
+dxexq << 2206c00000000000 00000000000000cf ==> 000000000000181b 0000000000000000
+dxexq << a205c00000000000 000000010a395bcf ==> 0000000000001817 0000000000000000
+dxexq << 6209400000fd0000 00253f1f534acdd4 ==> 0000000000000825 0000000000000000
+dxexq << 000400000089b000 0a6000d000000049 ==> 0000000000000010 0000000000000000
+dxexq << 2208000000000000 0000000000000000 ==> 0000000000001820 0000000000000000
+dxexq << a208000000000000 0000000000000000 ==> 0000000000001820 0000000000000000
+dxexq << a248000000000000 0000000000000000 ==> 0000000000001920 0000000000000000
+dxexq << 7c00000000000000 0000000000000000 ==> fffffffffffffffe 0000000000000000
+dxexq << fc00000000000000 c00100035b007700 ==> fffffffffffffffe 0000000000000000
+dxexq << 7e00000000000000 fe000000d0e0a0d0 ==> fffffffffffffffd 0000000000000000
+dxexq << 7800000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+dxexq << f800000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+dxexq << f900000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+
+Test DFP reround instructions
+drrnd (RMC=0, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=1, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=2, ref sig=2) [RR]2234000000000e50 => 223c000000000035
+drrnd (RMC=3, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=0, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=1, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=2, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=3, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=0, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=1, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=2, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=3, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=0, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=1, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=2, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=3, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=0, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=1, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=2, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=3, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=0, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=1, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=2, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=3, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=0, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=1, ref sig=2) [RR]22240000000000cf => 2228000000000018
+drrnd (RMC=2, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=3, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=0, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=1, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=2, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=3, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=0, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=1, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=2, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=3, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=0, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=1, ref sig=6) [RR]a21400010a395bcf => a2240000000849c5
+drrnd (RMC=2, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=3, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=0, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=1, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=2, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=3, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=0, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=1, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=2, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=3, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=0, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=1, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=2, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=3, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=0, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=1, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=2, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=3, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=0, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=1, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=2, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=3, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=0, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=1, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=2, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=3, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=0, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=1, ref sig=2) [RR]000400000089b000 => 001800000000004e
+drrnd (RMC=2, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=3, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=0, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=1, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=2, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=3, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=0, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=1, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=2, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=3, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=0, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+
+drrndq (RMC=0, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=1, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=2, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000035
+drrndq (RMC=3, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=0, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=1, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=2, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=3, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=0, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=1, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=2, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=3, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=0, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=1, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=2, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=3, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=0, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=1, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=2, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=3, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=0, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=1, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=2, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=3, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=0, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=1, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000018
+drrndq (RMC=2, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=3, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=0, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=1, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=2, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=3, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=0, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=1, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=2, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=3, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=0, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+drrndq (RMC=1, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c5
+drrndq (RMC=2, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+drrndq (RMC=3, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+drrndq (RMC=0, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=1, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=2, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=3, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=0, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=1, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=2, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=3, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=0, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=1, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=2, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=3, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=0, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=1, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=2, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=3, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=0, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=1, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=2, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=3, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=0, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=1, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=2, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=3, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=0, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000011
+drrndq (RMC=1, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000010
+drrndq (RMC=2, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000011
+drrndq (RMC=3, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000011
+drrndq (RMC=0, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=1, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=2, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=3, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=0, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=1, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=2, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=3, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=0, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP quantize instructions
+dqua (RMC= 0) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 1) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 2) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 3) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 0) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 1) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 2) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 3) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 0) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 1) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c5
+dqua (RMC= 2) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 3) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 0) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 1) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 2) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 3) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 0) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 1) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 2) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 3) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 0) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 1) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 2) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 3) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 0) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 1) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 2) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 3) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 0) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 1) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 2) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 3) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 0) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 1) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 2) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 3) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 0) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 1) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 2) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 3) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 0) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 1) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 2) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 3) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 0) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 1) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 2) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 3) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 0) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 1) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 2) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 3) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 0) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 1) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 2) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 3) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 0) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 1) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 2) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 3) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 0) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 1) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 2) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 3) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+
+dquaq (RMC= 0) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 1) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 2) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 3) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 0) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 1) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 2) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 3) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 0) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 1) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c5
+dquaq (RMC= 2) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 3) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 0) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 1) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 2) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 3) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 0) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 1) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 2) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 3) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 0) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP quantize immediate instructions
+dquai (RMC= 0, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 1, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 2, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 3, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 0, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 1, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 2, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 3, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 0, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 1, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 2, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 3, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 0, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 1, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 2, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 3, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 0, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 1, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 2, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 3, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 0, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 1, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 2, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 3, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 0, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 1, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 2, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 3, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 0, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 1, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 2, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 3, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 0, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 1, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 2, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 3, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 0, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 1, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 2, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 3, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 0, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 1, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 2, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 3, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 0, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 1, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 2, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 3, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 0, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 1, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 2, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 3, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 0, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 1, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 2, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 3, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 0, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+
+dquaiq (RMC= 0, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 1, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 2, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 3, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 0, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 1, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 2, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 3, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 0, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 1, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 2, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 3, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 0, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 1, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 2, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 3, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 0, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 1, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 2, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 3, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 0, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 1, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 2, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 3, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 0, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 1, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 2, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 3, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 0, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 1, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 2, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 3, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 0, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 1, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 2, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 3, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 0, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 1, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 2, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 3, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 0, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 1, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 2, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 3, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 0, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+
diff --git a/main/none/tests/ppc32/test_dfp3.vgtest b/main/none/tests/ppc32/test_dfp3.vgtest
new file mode 100644
index 0000000..39168a3
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp3.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp3
diff --git a/main/none/tests/ppc32/test_dfp4.c b/main/none/tests/ppc32/test_dfp4.c
new file mode 100644
index 0000000..7cd8721
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp4.c
@@ -0,0 +1,626 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+typedef union stuff {
+ _Decimal64 dec_val;
+ _Decimal128 dec_val128;
+ unsigned long long u64_val;
+ struct {
+ unsigned long long valu;
+ unsigned long long vall;
+ } u128;
+} dfp_val_t;
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+
+/* In _test_dtstdc[q], DCM can be one of 6 possible data classes, numbered 0-5.
+ * In reality, DCM is a 6-bit mask field. We just test the individual values
+ * and assume that masking multiple values would work OK.
+ * BF is the condition register bit field which can range from 0-7. But for
+ * testing purposes, we only use BF values of '0' and '5'.
+ */
+static void _test_dtstdc(int BF, int DCM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
+{
+ _Decimal64 f14 = val1.dec_val;
+ if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM);
+ return;
+ }
+ switch (DCM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dtstdcq(int BF, int DCM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
+{
+ _Decimal128 f14 = val1.dec_val128;
+ if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM);
+ return;
+ }
+ switch (DCM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+/* In _test_dtstdg[q], DGM can be one of 6 possible data groups, numbered 0-5.
+ * In reality, DGM is a 6-bit mask field. We just test the individual values
+ * and assume that masking multiple values would work OK.
+ * BF is the condition register bit field which can range from 0-7. But for
+ * testing purposes, we only use BF values of '0' and '5'.
+ */
+static void _test_dtstdg(int BF, int DGM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
+{
+ _Decimal64 f14 = val1.dec_val;
+ if (DGM < 0 || DGM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DGM);
+ return;
+ }
+ switch (DGM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dtstdgq(int BF, int DGM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
+{
+ _Decimal128 f14 = val1.dec_val128;
+ if (DGM < 0 || DGM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DGM);
+ return;
+ }
+ switch (DGM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+/* In _test_dtstex[q], BF is the condition register bit field indicating the
+ * CR field in which the result of the test should be placed. BF can range
+ * from 0-7, but for testing purposes, we only use BF values of '4' and '7'.
+ */
+static void
+_test_dtstex(int BF, int x __attribute__((unused)), dfp_val_t val1, dfp_val_t val2)
+{
+ _Decimal64 f14 = val1.dec_val;
+ _Decimal64 f16 = val2.dec_val;
+ if (!(BF == 4 || BF == 7)) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 4:
+ __asm__ __volatile__ ("dtstex 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dtstex 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dtstexq(int BF, int x __attribute__((unused)), dfp_val_t val1, dfp_val_t val2)
+{
+ _Decimal128 f14 = val1.dec_val128;
+ _Decimal128 f16 = val2.dec_val128;
+ if (!(BF == 4 || BF == 7)) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 4:
+ __asm__ __volatile__ ("dtstexq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dtstexq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+
+
+typedef void (*test_func_t)(int a, int b, dfp_val_t val1, dfp_val_t val2);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+// Both Long and Quad arrays of DFP values should have the same length, so it
+// doesn't matter which array I use for calculating the following #define.
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {4, 3},
+ {6, 0},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+} dfp_test_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_func_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+
+
+static dfp_one_arg_test_t
+dfp_ClassAndGroupTest_tests[] = {
+ { &_test_dtstdc, "dtstdc", LONG_TEST, "[tCls]"},
+ { &_test_dtstdcq, "dtstdcq", QUAD_TEST, "[tCls]"},
+ { &_test_dtstdg, "dtstdg", LONG_TEST, "[tGrp]"},
+ { &_test_dtstdgq, "dtstdgq", QUAD_TEST, "[tGrp]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_ClassAndGroupTest_ops(void)
+{
+ test_func_t func;
+ dfp_val_t test_val, dummy;
+
+ int k = 0;
+
+ while ((func = dfp_ClassAndGroupTest_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_ClassAndGroupTest_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int data_class_OR_group, BF = 0;
+ Bool repeat = True;
+
+ if (test_def.precision == LONG_TEST) {
+ test_val.u64_val = dfp64_vals[i];
+ } else {
+ test_val.u128.valu = dfp128_vals[i * 2];
+ test_val.u64_val = test_val.u128.valu;
+ test_val.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+again:
+ for (data_class_OR_group = 0; data_class_OR_group < 6; data_class_OR_group++) {
+ unsigned int condreg;
+ unsigned int flags;
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, data_class_OR_group, test_val, dummy);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s (DC/DG=%d) %s%016llx", test_def.name, data_class_OR_group,
+ test_def.op, test_val.u64_val);
+ if (test_def.precision == QUAD_TEST) {
+ printf(" %016llx", test_val.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ if (repeat) {
+ repeat = False;
+ BF = 5;
+ goto again;
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_test_t
+dfp_ExpTest_tests[] = {
+ { &_test_dtstex, "dtstex", dfp_2args_x1, 25, LONG_TEST, "[tExp]"},
+ { &_test_dtstexq, "dtstexq", dfp_2args_x1, 25, QUAD_TEST, "[tExp]"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+
+static void test_dfp_ExpTest_ops(void)
+{
+ dfp_val_t test_val1, test_val2;
+ test_func_t func;
+ int k = 0;
+
+ while ((func = dfp_ExpTest_tests[k].test_func)) {
+ /* BF is a 3-bit instruction field that indicates the CR field in which the
+ * result of the test should be placed. We won't iterate through all
+ * 8 possible BF values since storing compare results to a given field is
+ * a well-tested mechanism in VEX. But we will test two BF values, just as
+ * a sniff-test.
+ */
+ int i, repeat = 1, BF = 4;
+ dfp_test_t test_def = dfp_ExpTest_tests[k];
+
+again:
+ for (i = 0; i < test_def.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_def.precision == LONG_TEST) {
+ test_val1.u64_val = dfp64_vals[test_def.targs[i].fra_idx];
+ test_val2.u64_val = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ test_val1.u128.valu = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ test_val1.u64_val = test_val1.u128.valu;
+ test_val1.u128.vall = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ test_val2.u128.valu = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ test_val2.u64_val = test_val2.u128.valu;
+ test_val2.u128.vall = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, 0, test_val1, test_val2);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s %016llx", test_def.name, test_val1.u64_val);
+ if (test_def.precision == LONG_TEST) {
+ printf(" %s %016llx ",
+ test_def.op, test_val2.u64_val);
+ } else {
+ printf(" %016llx %s %016llx %016llx ",
+ test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ if (repeat) {
+ repeat = 0;
+ BF = 7;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_ExpTest_ops,
+ "Test DFP exponent test instructions"},
+ { &test_dfp_ClassAndGroupTest_ops,
+ "Test DFP class and group test instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc32/test_dfp4.stderr.exp b/main/none/tests/ppc32/test_dfp4.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp4.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc32/test_dfp4.stdout.exp b/main/none/tests/ppc32/test_dfp4.stdout.exp
new file mode 100644
index 0000000..253b2a5
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp4.stdout.exp
@@ -0,0 +1,876 @@
+Test DFP exponent test instructions
+dtstex 2234000000000e50 [tExp] 223400000014c000 => 2 (BF=4)
+dtstex a2340000000000e0 [tExp] 223400000014c000 => 2 (BF=4)
+dtstex a21400010a395bcf [tExp] 22240000000000cf => 8 (BF=4)
+dtstex 000400000089b000 [tExp] 2234000000000e50 => 8 (BF=4)
+dtstex a2340000000000e0 [tExp] a21400010a395bcf => 4 (BF=4)
+dtstex 6e4d3f1f534acdd4 [tExp] 223400000014c000 => 4 (BF=4)
+dtstex 6e4d3f1f534acdd4 [tExp] a2340000000000e0 => 4 (BF=4)
+dtstex 2238000000000000 [tExp] 223400000014c000 => 4 (BF=4)
+dtstex 2238000000000000 [tExp] a2340000000000e0 => 4 (BF=4)
+dtstex a238000000000000 [tExp] 2234000000000e50 => 4 (BF=4)
+dtstex a238000000000000 [tExp] 223400000014c000 => 4 (BF=4)
+dtstex a238000000000000 [tExp] a2340000000000e0 => 4 (BF=4)
+dtstex 2238000000000000 [tExp] a238000000000000 => 2 (BF=4)
+dtstex fc00000000000000 [tExp] f800000000000000 => 1 (BF=4)
+dtstex fc00000000000000 [tExp] 223400000014c000 => 1 (BF=4)
+dtstex fc00000000000000 [tExp] 7800000000000000 => 1 (BF=4)
+dtstex fc00000000000000 [tExp] fc00000000000000 => 2 (BF=4)
+dtstex fc00000000000000 [tExp] fe000000d0e0a0d0 => 2 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] f800000000000000 => 1 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] 2234000000000e50 => 1 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] 7800000000000000 => 1 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] fe000000d0e0a0d0 => 2 (BF=4)
+dtstex f800000000000000 [tExp] f800000000000000 => 2 (BF=4)
+dtstex f800000000000000 [tExp] 22240000000000cf => 1 (BF=4)
+dtstex f800000000000000 [tExp] 7a34000000000000 => 2 (BF=4)
+dtstex 2234000000000e50 [tExp] 223400000014c000 => 2 (BF=7)
+dtstex a2340000000000e0 [tExp] 223400000014c000 => 2 (BF=7)
+dtstex a21400010a395bcf [tExp] 22240000000000cf => 8 (BF=7)
+dtstex 000400000089b000 [tExp] 2234000000000e50 => 8 (BF=7)
+dtstex a2340000000000e0 [tExp] a21400010a395bcf => 4 (BF=7)
+dtstex 6e4d3f1f534acdd4 [tExp] 223400000014c000 => 4 (BF=7)
+dtstex 6e4d3f1f534acdd4 [tExp] a2340000000000e0 => 4 (BF=7)
+dtstex 2238000000000000 [tExp] 223400000014c000 => 4 (BF=7)
+dtstex 2238000000000000 [tExp] a2340000000000e0 => 4 (BF=7)
+dtstex a238000000000000 [tExp] 2234000000000e50 => 4 (BF=7)
+dtstex a238000000000000 [tExp] 223400000014c000 => 4 (BF=7)
+dtstex a238000000000000 [tExp] a2340000000000e0 => 4 (BF=7)
+dtstex 2238000000000000 [tExp] a238000000000000 => 2 (BF=7)
+dtstex fc00000000000000 [tExp] f800000000000000 => 1 (BF=7)
+dtstex fc00000000000000 [tExp] 223400000014c000 => 1 (BF=7)
+dtstex fc00000000000000 [tExp] 7800000000000000 => 1 (BF=7)
+dtstex fc00000000000000 [tExp] fc00000000000000 => 2 (BF=7)
+dtstex fc00000000000000 [tExp] fe000000d0e0a0d0 => 2 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] f800000000000000 => 1 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] 2234000000000e50 => 1 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] 7800000000000000 => 1 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] fe000000d0e0a0d0 => 2 (BF=7)
+dtstex f800000000000000 [tExp] f800000000000000 => 2 (BF=7)
+dtstex f800000000000000 [tExp] 22240000000000cf => 1 (BF=7)
+dtstex f800000000000000 [tExp] 7a34000000000000 => 2 (BF=7)
+
+dtstexq 2207c00000000000 0000000000000e50 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=4)
+dtstexq a207c00000000000 00000000000000e0 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=4)
+dtstexq a205c00000000000 000000010a395bcf [tExp] 2206c00000000000 00000000000000cf => 8 (BF=4)
+dtstexq 000400000089b000 0a6000d000000049 [tExp] 2207c00000000000 0000000000000e50 => 8 (BF=4)
+dtstexq a207c00000000000 00000000000000e0 [tExp] a205c00000000000 000000010a395bcf => 4 (BF=4)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] 2207c00000000000 000000000014c000 => 8 (BF=4)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] a207c00000000000 00000000000000e0 => 8 (BF=4)
+dtstexq 2208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=4)
+dtstexq 2208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=4)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 0000000000000e50 => 4 (BF=4)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=4)
+dtstexq a208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=4)
+dtstexq 2208000000000000 0000000000000000 [tExp] a208000000000000 0000000000000000 => 2 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] f800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 2207c00000000000 000000000014c000 => 1 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7e00000000000000 fe000000d0e0a0d0 => 2 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] f800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 2207c00000000000 0000000000000e50 => 1 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 7800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=4)
+dtstexq f800000000000000 0000000000000000 [tExp] f800000000000000 0000000000000000 => 2 (BF=4)
+dtstexq f800000000000000 0000000000000000 [tExp] 2206c00000000000 00000000000000cf => 1 (BF=4)
+dtstexq f800000000000000 0000000000000000 [tExp] f900000000000000 0000000000000000 => 2 (BF=4)
+dtstexq 2207c00000000000 0000000000000e50 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=7)
+dtstexq a207c00000000000 00000000000000e0 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=7)
+dtstexq a205c00000000000 000000010a395bcf [tExp] 2206c00000000000 00000000000000cf => 8 (BF=7)
+dtstexq 000400000089b000 0a6000d000000049 [tExp] 2207c00000000000 0000000000000e50 => 8 (BF=7)
+dtstexq a207c00000000000 00000000000000e0 [tExp] a205c00000000000 000000010a395bcf => 4 (BF=7)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] 2207c00000000000 000000000014c000 => 8 (BF=7)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] a207c00000000000 00000000000000e0 => 8 (BF=7)
+dtstexq 2208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=7)
+dtstexq 2208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=7)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 0000000000000e50 => 4 (BF=7)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=7)
+dtstexq a208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=7)
+dtstexq 2208000000000000 0000000000000000 [tExp] a208000000000000 0000000000000000 => 2 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] f800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 2207c00000000000 000000000014c000 => 1 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7e00000000000000 fe000000d0e0a0d0 => 2 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] f800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 2207c00000000000 0000000000000e50 => 1 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 7800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=7)
+dtstexq f800000000000000 0000000000000000 [tExp] f800000000000000 0000000000000000 => 2 (BF=7)
+dtstexq f800000000000000 0000000000000000 [tExp] 2206c00000000000 00000000000000cf => 1 (BF=7)
+dtstexq f800000000000000 0000000000000000 [tExp] f900000000000000 0000000000000000 => 2 (BF=7)
+
+Test DFP class and group test instructions
+dtstdc (DC/DG=0) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]2234000000000e50 => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]2234000000000e50 => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]223400000014c000 => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]223400000014c000 => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]a2340000000000e0 => a (BF=0)
+dtstdc (DC/DG=4) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]a2340000000000e0 => a (BF=5)
+dtstdc (DC/DG=4) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]22240000000000cf => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]22240000000000cf => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]a21400010a395bcf => a (BF=0)
+dtstdc (DC/DG=4) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]a21400010a395bcf => a (BF=5)
+dtstdc (DC/DG=4) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]6e4d3f1f534acdd4 => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]6e4d3f1f534acdd4 => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]000400000089b000 => 2 (BF=0)
+dtstdc (DC/DG=5) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]000400000089b000 => 2 (BF=5)
+dtstdc (DC/DG=5) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]2238000000000000 => 2 (BF=0)
+dtstdc (DC/DG=0) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]2238000000000000 => 2 (BF=5)
+dtstdc (DC/DG=0) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]a238000000000000 => a (BF=0)
+dtstdc (DC/DG=0) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]a238000000000000 => a (BF=5)
+dtstdc (DC/DG=0) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]4248000000000000 => 2 (BF=0)
+dtstdc (DC/DG=0) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]4248000000000000 => 2 (BF=5)
+dtstdc (DC/DG=0) [tCls]7e34000000000111 => 2 (BF=0)
+dtstdc (DC/DG=1) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]7e34000000000111 => 2 (BF=5)
+dtstdc (DC/DG=1) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]fe000000d0e0a0d0 => a (BF=0)
+dtstdc (DC/DG=1) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]fe000000d0e0a0d0 => a (BF=5)
+dtstdc (DC/DG=1) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]fc00000000000000 => a (BF=0)
+dtstdc (DC/DG=2) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]fc00000000000000 => a (BF=5)
+dtstdc (DC/DG=2) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]7800000000000000 => 2 (BF=0)
+dtstdc (DC/DG=3) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]7800000000000000 => 2 (BF=5)
+dtstdc (DC/DG=3) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]f800000000000000 => a (BF=0)
+dtstdc (DC/DG=3) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]f800000000000000 => a (BF=5)
+dtstdc (DC/DG=3) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]7a34000000000000 => 2 (BF=0)
+dtstdc (DC/DG=3) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]7a34000000000000 => 2 (BF=5)
+dtstdc (DC/DG=3) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]7a34000000000000 => 0 (BF=5)
+
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 0000000000000e50 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 0000000000000e50 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 000000000014c000 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 000000000014c000 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a207c00000000000 00000000000000e0 => a (BF=0)
+dtstdcq (DC/DG=4) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a207c00000000000 00000000000000e0 => a (BF=5)
+dtstdcq (DC/DG=4) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2206c00000000000 00000000000000cf => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2206c00000000000 00000000000000cf => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a205c00000000000 000000010a395bcf => a (BF=0)
+dtstdcq (DC/DG=4) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a205c00000000000 000000010a395bcf => a (BF=5)
+dtstdcq (DC/DG=4) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]6209400000fd0000 00253f1f534acdd4 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]6209400000fd0000 00253f1f534acdd4 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]000400000089b000 0a6000d000000049 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]000400000089b000 0a6000d000000049 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2208000000000000 0000000000000000 => 2 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2208000000000000 0000000000000000 => 2 (BF=5)
+dtstdcq (DC/DG=0) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a208000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=0) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a208000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=0) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a248000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=0) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a248000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=0) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]7c00000000000000 0000000000000000 => 2 (BF=0)
+dtstdcq (DC/DG=2) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]7c00000000000000 0000000000000000 => 2 (BF=5)
+dtstdcq (DC/DG=2) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]fc00000000000000 c00100035b007700 => a (BF=0)
+dtstdcq (DC/DG=2) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]fc00000000000000 c00100035b007700 => a (BF=5)
+dtstdcq (DC/DG=2) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=0)
+dtstdcq (DC/DG=1) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=5)
+dtstdcq (DC/DG=1) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]7800000000000000 0000000000000000 => 2 (BF=0)
+dtstdcq (DC/DG=3) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]7800000000000000 0000000000000000 => 2 (BF=5)
+dtstdcq (DC/DG=3) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]f800000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=3) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]f800000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=3) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]f900000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=3) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]f900000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=3) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+
+dtstdg (DC/DG=0) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]2234000000000e50 => 2 (BF=0)
+dtstdg (DC/DG=3) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]2234000000000e50 => 2 (BF=5)
+dtstdg (DC/DG=3) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]223400000014c000 => 2 (BF=0)
+dtstdg (DC/DG=3) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]223400000014c000 => 2 (BF=5)
+dtstdg (DC/DG=3) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=1) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]a2340000000000e0 => a (BF=0)
+dtstdg (DC/DG=3) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=1) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]a2340000000000e0 => a (BF=5)
+dtstdg (DC/DG=3) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]22240000000000cf => 2 (BF=0)
+dtstdg (DC/DG=3) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]22240000000000cf => 2 (BF=5)
+dtstdg (DC/DG=3) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=1) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]a21400010a395bcf => a (BF=0)
+dtstdg (DC/DG=3) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=1) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]a21400010a395bcf => a (BF=5)
+dtstdg (DC/DG=3) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]6e4d3f1f534acdd4 => 2 (BF=0)
+dtstdg (DC/DG=2) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]6e4d3f1f534acdd4 => 2 (BF=5)
+dtstdg (DC/DG=2) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]000400000089b000 => 2 (BF=0)
+dtstdg (DC/DG=4) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]000400000089b000 => 2 (BF=5)
+dtstdg (DC/DG=4) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]2238000000000000 => 2 (BF=0)
+dtstdg (DC/DG=0) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]2238000000000000 => 2 (BF=5)
+dtstdg (DC/DG=0) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=1) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]a238000000000000 => a (BF=0)
+dtstdg (DC/DG=0) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=1) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]a238000000000000 => a (BF=5)
+dtstdg (DC/DG=0) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]4248000000000000 => 2 (BF=0)
+dtstdg (DC/DG=0) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]4248000000000000 => 2 (BF=5)
+dtstdg (DC/DG=0) [tGrp]7e34000000000111 => 2 (BF=0)
+dtstdg (DC/DG=1) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]7e34000000000111 => 2 (BF=5)
+dtstdg (DC/DG=1) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]fe000000d0e0a0d0 => a (BF=0)
+dtstdg (DC/DG=1) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]fe000000d0e0a0d0 => a (BF=5)
+dtstdg (DC/DG=1) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]fc00000000000000 => a (BF=0)
+dtstdg (DC/DG=1) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]fc00000000000000 => a (BF=5)
+dtstdg (DC/DG=1) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]7800000000000000 => 2 (BF=0)
+dtstdg (DC/DG=1) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]7800000000000000 => 2 (BF=5)
+dtstdg (DC/DG=1) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]f800000000000000 => a (BF=0)
+dtstdg (DC/DG=1) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]f800000000000000 => a (BF=5)
+dtstdg (DC/DG=1) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]7a34000000000000 => 2 (BF=0)
+dtstdg (DC/DG=1) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]7a34000000000000 => 2 (BF=5)
+dtstdg (DC/DG=1) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]7a34000000000000 => 0 (BF=5)
+
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 0000000000000e50 => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 0000000000000e50 => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 000000000014c000 => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 000000000014c000 => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a207c00000000000 00000000000000e0 => a (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a207c00000000000 00000000000000e0 => a (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2206c00000000000 00000000000000cf => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2206c00000000000 00000000000000cf => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a205c00000000000 000000010a395bcf => a (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a205c00000000000 000000010a395bcf => a (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]6209400000fd0000 00253f1f534acdd4 => 2 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]6209400000fd0000 00253f1f534acdd4 => 2 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]000400000089b000 0a6000d000000049 => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]000400000089b000 0a6000d000000049 => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2208000000000000 0000000000000000 => 2 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2208000000000000 0000000000000000 => 2 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a208000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a208000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a248000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a248000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=0) [tGrp]7c00000000000000 0000000000000000 => 2 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]7c00000000000000 0000000000000000 => 2 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]fc00000000000000 c00100035b007700 => a (BF=0)
+dtstdgq (DC/DG=1) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]fc00000000000000 c00100035b007700 => a (BF=5)
+dtstdgq (DC/DG=1) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]7800000000000000 0000000000000000 => 2 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]7800000000000000 0000000000000000 => 2 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]f800000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=1) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]f800000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=1) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]f900000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=1) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]f900000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=1) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+
diff --git a/main/none/tests/ppc32/test_dfp4.vgtest b/main/none/tests/ppc32/test_dfp4.vgtest
new file mode 100644
index 0000000..dac3356
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp4.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp4
diff --git a/main/none/tests/ppc32/test_dfp5.c b/main/none/tests/ppc32/test_dfp5.c
new file mode 100644
index 0000000..64008b6
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp5.c
@@ -0,0 +1,595 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+typedef union stuff {
+ _Decimal64 dec_val;
+ _Decimal128 dec_val128;
+ unsigned long long u64_val;
+ struct {
+ unsigned long long valu;
+ unsigned long long vall;
+ } u128;
+} dfp_val_t;
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+enum BF_vals { BF_val1 = 0, BF_val2 = 1, BF_val3 =6};
+
+// The assembly-level instructions being tested
+static void _test_dtstsf(unsigned int BF, unsigned int ref_sig, dfp_val_t valB)
+{
+ _Decimal64 f16 = valB.dec_val;
+ register HWord_t r14 __asm__ ("r14");
+ double f14;
+ r14 = (HWord_t)&ref_sig;
+
+ __asm __volatile__ ("lfiwax %0, 0, %1" : "=f" (f14): "r" (r14));
+ switch (BF) {
+ case BF_val1:
+ __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16));
+ break;
+ case BF_val2:
+ __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16));
+ break;
+ case BF_val3:
+ __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for BF\n", BF);
+ break;
+ }
+}
+
+static void _test_dtstsfq(unsigned int BF, unsigned int ref_sig, dfp_val_t valB)
+{
+ _Decimal128 f16 = valB.dec_val128;
+ register HWord_t r14 __asm__ ("r14");
+ double f14;
+ r14 = (HWord_t)&ref_sig;
+
+ __asm __volatile__ ("lfiwax %0, 0, %1" : "=f" (f14): "r" (r14));
+ switch (BF) {
+ case BF_val1:
+ __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16));
+ break;
+ case BF_val2:
+ __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16));
+ break;
+ case BF_val3:
+ __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for BF\n", BF);
+ break;
+ }
+}
+
+static dfp_val_t _test_ddedpd(unsigned int SP, dfp_val_t valB)
+{
+ _Decimal64 ret = 0;
+ dfp_val_t result;
+ _Decimal64 f16 = valB.dec_val;
+ switch (SP) {
+ case 0:
+ __asm__ __volatile__ ("ddedpd. 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("ddedpd. 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("ddedpd. 2, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("ddedpd. 3, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for SP\n", SP);
+ break;
+ }
+ result.dec_val = ret;
+ return result;
+}
+
+
+static dfp_val_t _test_ddedpdq(unsigned int SP, dfp_val_t valB)
+{
+ _Decimal128 ret = 0;
+ dfp_val_t result;
+ _Decimal128 f16 = valB.dec_val128;
+ switch (SP) {
+ case 0:
+ __asm__ __volatile__ ("ddedpdq 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("ddedpdq 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("ddedpdq 2, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("ddedpdq 3, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for SP\n", SP);
+ break;
+ }
+ result.dec_val128 = ret;
+ return result;
+}
+
+static dfp_val_t _test_denbcd(unsigned int S, dfp_val_t valB)
+{
+ _Decimal64 ret = 0;
+ dfp_val_t result;
+ _Decimal64 f16 = valB.dec_val;
+ switch (S) {
+ case 0:
+ __asm__ __volatile__ ("denbcd. 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("denbcd. 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for S\n", S);
+ break;
+ }
+ result.dec_val = ret;
+ return result;
+}
+
+
+static dfp_val_t _test_denbcdq(unsigned int S, dfp_val_t valB)
+{
+ _Decimal128 ret = 0;
+ dfp_val_t result;
+ _Decimal128 f16 = valB.dec_val128;
+ switch (S) {
+ case 0:
+ __asm__ __volatile__ ("denbcdq 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("denbcdq 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for S\n", S);
+ break;
+ }
+ result.dec_val128 = ret;
+ return result;
+}
+
+
+typedef void (*test_func_t)(unsigned int imm, unsigned int imm2, dfp_val_t valB);
+typedef dfp_val_t (*test_func_bcd_t)(unsigned int imm, dfp_val_t valB);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+/* The bcd64_vals and bdc128_vals hold the unique results of executing
+ * the ddedpd instruction on the basic dfp64 and dfp128 array values.
+ * Executing the inverse operation (denbcd) on these values with the
+ * appropriate S (signed) value should yield values approximating the
+ * original dfp values (except being 2^4 in magnitude since the decoding
+ * operation shifted the value one hex digit to the left to make room
+ * for signedness info).
+ */
+static unsigned long long bcd64_vals[] = {
+ 0x0000000000003450ULL,
+ 0x000000000003450cULL,
+ 0x000000000003450fULL,
+ 0x0000000001230000ULL,
+ 0x000000001230000cULL,
+ 0x000000001230000fULL,
+ 0x0000000000000160ULL,
+ 0x000000000000160dULL,
+ 0x0000000000000189ULL,
+ 0x000000000000189cULL,
+ 0x000000000000189fULL,
+ 0x0000004123456789ULL,
+ 0x000004123456789dULL,
+ 0x9839871234533354ULL,
+ 0x839871234533354cULL,
+ 0x839871234533354fULL,
+ 0x0000000008864000ULL,
+ 0x000000008864000cULL,
+ 0x000000008864000fULL,
+ 0x0000000000000000ULL,
+ 0x000000000000000cULL,
+ 0x000000000000000fULL,
+ 0x000000000000000dULL,
+ 0x0000000000000211ULL,
+ 0x000000000000211cULL,
+ 0x000000000000211fULL,
+ 0x0000003882028150ULL,
+ 0x000003882028150dULL
+ };
+
+static unsigned long long bcd128_vals[] = {
+ 0x0000000000000000ULL, 0x0000000000003450ULL,
+ 0x0000000000000000ULL, 0x000000000003450cULL,
+ 0x0000000000000000ULL, 0x000000000003450fULL,
+ 0x0000000000000000ULL, 0x0000000001230000ULL,
+ 0x0000000000000000ULL, 0x000000001230000cULL,
+ 0x0000000000000000ULL, 0x000000001230000fULL,
+ 0x0000000000000000ULL, 0x0000000000000160ULL,
+ 0x0000000000000000ULL, 0x000000000000160dULL,
+ 0x0000000000000000ULL, 0x0000000000000189ULL,
+ 0x0000000000000000ULL, 0x000000000000189cULL,
+ 0x0000000000000000ULL, 0x000000000000189fULL,
+ 0x0000000000000000ULL, 0x0000004123456789ULL,
+ 0x0000000000000000ULL, 0x000004123456789dULL,
+ 0x0000097100000000ULL, 0x9839871234533354ULL,
+ 0x0000971000000009ULL, 0x839871234533354cULL,
+ 0x0000971000000009ULL, 0x839871234533354fULL,
+ 0x0000010954000051ULL, 0x8000640000000049ULL,
+ 0x0000109540000518ULL, 0x000640000000049cULL,
+ 0x0000109540000518ULL, 0x000640000000049fULL,
+ 0x0000000000000000ULL, 0x0000000000000000ULL,
+ 0x0000000000000000ULL, 0x000000000000000cULL,
+ 0x0000000000000000ULL, 0x000000000000000fULL,
+ 0x0000000000000000ULL, 0x000000000000000dULL,
+ 0x0000000000080000ULL, 0x0200801330811600ULL,
+ 0x0000000000800000ULL, 0x200801330811600dULL,
+ 0x0000000000088170ULL, 0x0000003882028150ULL,
+ 0x0000000000881700ULL, 0x000003882028150cULL,
+ 0x0000000000881700ULL, 0x000003882028150fULL
+};
+
+// Both Long and Quad arrays of DFP values should have the same length, so it
+// doesn't matter which array I use for calculating the following #define.
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_func_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+typedef struct dfp_one_arg_bcd_test
+{
+ test_func_bcd_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_bcd_test_t;
+
+static dfp_one_arg_bcd_test_t
+dfp_test_dfp_ddedpd_tests[] = {
+ { &_test_ddedpd, "ddedpd", LONG_TEST, "[D->B]"},
+ { &_test_ddedpdq, "ddedpdq", QUAD_TEST, "[D->B]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_ddedpd_ops(void)
+{
+ test_func_bcd_t func;
+ dfp_val_t test_val;
+
+ int k = 0;
+
+ while ((func = dfp_test_dfp_ddedpd_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_bcd_test_t test_def = dfp_test_dfp_ddedpd_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ unsigned int SP;
+
+ if (test_def.precision == LONG_TEST) {
+ test_val.u64_val = dfp64_vals[i];
+ } else {
+ test_val.u128.valu = dfp128_vals[i * 2];
+ test_val.u64_val = test_val.u128.valu;
+ test_val.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+ for (SP = 0; SP < 4; SP++) {
+ dfp_val_t result;
+ result = (*func)(SP, test_val);
+ printf("%s (SP=%d) %s%016llx", test_def.name, SP,
+ test_def.op, test_val.u64_val);
+ if (test_def.precision == QUAD_TEST) {
+ printf(" %016llx", test_val.u128.vall);
+ }
+ if (test_def.precision == LONG_TEST)
+ printf(" ==> %016llx\n", result.u64_val);
+ else
+ printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_one_arg_bcd_test_t
+dfp_test_dfp_denbcd_tests[] = {
+ { &_test_denbcd, "denbcd", LONG_TEST, "[B->D]"},
+ { &_test_denbcdq, "denbcdq", QUAD_TEST, "[B->D]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_denbcd_ops(void)
+{
+ test_func_bcd_t func;
+ dfp_val_t test_val;
+ int num_test_vals;
+
+ int k = 0;
+
+ while ((func = dfp_test_dfp_denbcd_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_bcd_test_t test_def = dfp_test_dfp_denbcd_tests[k];
+ if (test_def.precision == LONG_TEST)
+ num_test_vals = sizeof(bcd64_vals)/sizeof(unsigned long long);
+ else
+ num_test_vals = sizeof(bcd128_vals)/(2 * sizeof(unsigned long long));
+
+ for (i = 0; i < num_test_vals; i++) {
+ unsigned int S;
+ dfp_val_t result;
+ /* The DPD-to-BCD decodings may contain up to 3 decodings for each normal DFP
+ * value: the first is an unsigned decoding, and the other two are
+ * signed decodings, with SP[1] set to '0' and '1' respectively at decode
+ * time. But some of the results of decodings were duplicates, so they were
+ * not included in the bcd64_vals and bcd128_vals arrays.
+ *
+ * When doing the encoding operation (denbcd), we'll attempt both S=0 and
+ * S=1; one or the other should encode the BCD value to something close to
+ * its original DFP value (except being 2^4 in magnitude since the decoding
+ * operation shifted the value one hex digit to the left to make room
+ * for signedness info).
+ */
+ for (S = 0; S < 2; S++) {
+ if (test_def.precision == LONG_TEST) {
+ test_val.u64_val = bcd64_vals[i];
+ } else {
+ test_val.u128.valu = bcd128_vals[i * 2];
+ test_val.u64_val = test_val.u128.valu;
+ test_val.u128.vall = bcd128_vals[(i * 2) + 1];
+ }
+
+ result = (*func)(S, test_val);
+ printf("%s (S=%d) %s%016llx", test_def.name, S,
+ test_def.op, test_val.u64_val);
+ if (test_def.precision == QUAD_TEST) {
+ printf(" %016llx", test_val.u128.vall);
+ }
+ if (test_def.precision == LONG_TEST)
+ printf(" ==> %016llx\n", result.u64_val);
+ else
+ printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_test_significance_tests[] = {
+ { &_test_dtstsf, "dtstsf", LONG_TEST, "[tSig]"},
+ { &_test_dtstsfq, "dtstsfq", QUAD_TEST, "[tSig]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_test_significance_ops(void)
+{
+ test_func_t func;
+ dfp_val_t test_valB;
+ int k = 0;
+ unsigned int BF_vals[] = {BF_val1, BF_val2, BF_val3};
+ unsigned int reference_sig, reference_sig_vals[] = {0U, 1U, 2U, 4U, 6U, 63U};
+ int num_reference_sig_vals = sizeof(reference_sig_vals)/sizeof(unsigned int);
+
+ while ((func = dfp_test_significance_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_test_significance_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int j;
+ if (test_def.precision == LONG_TEST) {
+ test_valB.u64_val = dfp64_vals[i];
+ } else {
+ test_valB.u128.valu = dfp128_vals[i * 2];
+ test_valB.u64_val = test_valB.u128.valu;
+ test_valB.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+ for (j = 0; j < num_reference_sig_vals; j++) {
+ int bf_idx, BF;
+ reference_sig = reference_sig_vals[j];
+ for (bf_idx = 0; bf_idx < sizeof(BF_vals)/sizeof(unsigned int); bf_idx++) {
+ unsigned int condreg;
+ unsigned int flags;
+ BF = BF_vals[bf_idx];
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, reference_sig, test_valB);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s (ref_sig=%d) %s%016llx", test_def.name, reference_sig,
+ test_def.op, test_valB.u64_val);
+ if (test_def.precision == QUAD_TEST) {
+ printf(" %016llx", test_valB.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ }
+ printf( "\n" );
+ }
+ k++;
+ }
+}
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_test_significance_ops,
+ "Test DFP test significance instructions"},
+ { &test_dfp_ddedpd_ops,
+ "Test DFP DPD-to-BCD instructions"},
+ { &test_dfp_denbcd_ops,
+ "Test DFP BCD-to-DPD instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc32/test_dfp5.stderr.exp b/main/none/tests/ppc32/test_dfp5.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp5.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc32/test_dfp5.stdout.exp b/main/none/tests/ppc32/test_dfp5.stdout.exp
new file mode 100644
index 0000000..0085526
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp5.stdout.exp
@@ -0,0 +1,855 @@
+Test DFP test significance instructions
+dtstsf (ref_sig=0) [tSig]2234000000000e50 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]2234000000000e50 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]2234000000000e50 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]2234000000000e50 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]2234000000000e50 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]2234000000000e50 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]2234000000000e50 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]2234000000000e50 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]2234000000000e50 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]2234000000000e50 => 2 (BF=0)
+dtstsf (ref_sig=4) [tSig]2234000000000e50 => 2 (BF=1)
+dtstsf (ref_sig=4) [tSig]2234000000000e50 => 2 (BF=6)
+dtstsf (ref_sig=6) [tSig]2234000000000e50 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]2234000000000e50 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]2234000000000e50 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]2234000000000e50 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]2234000000000e50 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]2234000000000e50 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]223400000014c000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]223400000014c000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]223400000014c000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]223400000014c000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]223400000014c000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]223400000014c000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]a2340000000000e0 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]a2340000000000e0 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]a2340000000000e0 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]a2340000000000e0 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]a2340000000000e0 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]a2340000000000e0 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]a2340000000000e0 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]a2340000000000e0 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]a2340000000000e0 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]a2340000000000e0 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]22240000000000cf => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]22240000000000cf => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]22240000000000cf => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]22240000000000cf => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]22240000000000cf => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]22240000000000cf => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]22240000000000cf => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]22240000000000cf => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]22240000000000cf => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]22240000000000cf => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]a21400010a395bcf => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]a21400010a395bcf => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]a21400010a395bcf => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]a21400010a395bcf => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]a21400010a395bcf => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]a21400010a395bcf => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]6e4d3f1f534acdd4 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]6e4d3f1f534acdd4 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]6e4d3f1f534acdd4 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]6e4d3f1f534acdd4 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]6e4d3f1f534acdd4 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]6e4d3f1f534acdd4 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]000400000089b000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]000400000089b000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]000400000089b000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]000400000089b000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]000400000089b000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]000400000089b000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=1) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=1) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=2) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=2) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=2) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=4) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]2238000000000000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=1) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=1) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=2) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=2) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=2) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=4) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]a238000000000000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=1) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=1) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=2) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=2) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=2) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=4) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]4248000000000000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]7e34000000000111 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]fc00000000000000 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]7800000000000000 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]f800000000000000 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]7a34000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 0000000000000e50 => 2 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 0000000000000e50 => 2 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 0000000000000e50 => 2 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 000000000014c000 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 000000000014c000 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 000000000014c000 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 000000000014c000 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 000000000014c000 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 000000000014c000 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2206c00000000000 00000000000000cf => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2206c00000000000 00000000000000cf => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2206c00000000000 00000000000000cf => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2206c00000000000 00000000000000cf => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2206c00000000000 00000000000000cf => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2206c00000000000 00000000000000cf => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+
+Test DFP DPD-to-BCD instructions
+ddedpd (SP=0) [D->B]2234000000000e50 ==> 0000000000003450
+ddedpd (SP=1) [D->B]2234000000000e50 ==> 0000000000003450
+ddedpd (SP=2) [D->B]2234000000000e50 ==> 000000000003450c
+ddedpd (SP=3) [D->B]2234000000000e50 ==> 000000000003450f
+ddedpd (SP=0) [D->B]223400000014c000 ==> 0000000001230000
+ddedpd (SP=1) [D->B]223400000014c000 ==> 0000000001230000
+ddedpd (SP=2) [D->B]223400000014c000 ==> 000000001230000c
+ddedpd (SP=3) [D->B]223400000014c000 ==> 000000001230000f
+ddedpd (SP=0) [D->B]a2340000000000e0 ==> 0000000000000160
+ddedpd (SP=1) [D->B]a2340000000000e0 ==> 0000000000000160
+ddedpd (SP=2) [D->B]a2340000000000e0 ==> 000000000000160d
+ddedpd (SP=3) [D->B]a2340000000000e0 ==> 000000000000160d
+ddedpd (SP=0) [D->B]22240000000000cf ==> 0000000000000189
+ddedpd (SP=1) [D->B]22240000000000cf ==> 0000000000000189
+ddedpd (SP=2) [D->B]22240000000000cf ==> 000000000000189c
+ddedpd (SP=3) [D->B]22240000000000cf ==> 000000000000189f
+ddedpd (SP=0) [D->B]a21400010a395bcf ==> 0000004123456789
+ddedpd (SP=1) [D->B]a21400010a395bcf ==> 0000004123456789
+ddedpd (SP=2) [D->B]a21400010a395bcf ==> 000004123456789d
+ddedpd (SP=3) [D->B]a21400010a395bcf ==> 000004123456789d
+ddedpd (SP=0) [D->B]6e4d3f1f534acdd4 ==> 9839871234533354
+ddedpd (SP=1) [D->B]6e4d3f1f534acdd4 ==> 9839871234533354
+ddedpd (SP=2) [D->B]6e4d3f1f534acdd4 ==> 839871234533354c
+ddedpd (SP=3) [D->B]6e4d3f1f534acdd4 ==> 839871234533354f
+ddedpd (SP=0) [D->B]000400000089b000 ==> 0000000008864000
+ddedpd (SP=1) [D->B]000400000089b000 ==> 0000000008864000
+ddedpd (SP=2) [D->B]000400000089b000 ==> 000000008864000c
+ddedpd (SP=3) [D->B]000400000089b000 ==> 000000008864000f
+ddedpd (SP=0) [D->B]2238000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]2238000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]2238000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]2238000000000000 ==> 000000000000000f
+ddedpd (SP=0) [D->B]a238000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]a238000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]a238000000000000 ==> 000000000000000d
+ddedpd (SP=3) [D->B]a238000000000000 ==> 000000000000000d
+ddedpd (SP=0) [D->B]4248000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]4248000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]4248000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]4248000000000000 ==> 000000000000000f
+ddedpd (SP=0) [D->B]7e34000000000111 ==> 0000000000000211
+ddedpd (SP=1) [D->B]7e34000000000111 ==> 0000000000000211
+ddedpd (SP=2) [D->B]7e34000000000111 ==> 000000000000211c
+ddedpd (SP=3) [D->B]7e34000000000111 ==> 000000000000211f
+ddedpd (SP=0) [D->B]fe000000d0e0a0d0 ==> 0000003882028150
+ddedpd (SP=1) [D->B]fe000000d0e0a0d0 ==> 0000003882028150
+ddedpd (SP=2) [D->B]fe000000d0e0a0d0 ==> 000003882028150d
+ddedpd (SP=3) [D->B]fe000000d0e0a0d0 ==> 000003882028150d
+ddedpd (SP=0) [D->B]fc00000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]fc00000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]fc00000000000000 ==> 000000000000000d
+ddedpd (SP=3) [D->B]fc00000000000000 ==> 000000000000000d
+ddedpd (SP=0) [D->B]7800000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]7800000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]7800000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]7800000000000000 ==> 000000000000000f
+ddedpd (SP=0) [D->B]f800000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]f800000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]f800000000000000 ==> 000000000000000d
+ddedpd (SP=3) [D->B]f800000000000000 ==> 000000000000000d
+ddedpd (SP=0) [D->B]7a34000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]7a34000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]7a34000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]7a34000000000000 ==> 000000000000000f
+
+ddedpdq (SP=0) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000003450
+ddedpdq (SP=1) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000003450
+ddedpdq (SP=2) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 000000000003450c
+ddedpdq (SP=3) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 000000000003450f
+ddedpdq (SP=0) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 0000000001230000
+ddedpdq (SP=1) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 0000000001230000
+ddedpdq (SP=2) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 000000001230000c
+ddedpdq (SP=3) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 000000001230000f
+ddedpdq (SP=0) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 0000000000000160
+ddedpdq (SP=1) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 0000000000000160
+ddedpdq (SP=2) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 000000000000160d
+ddedpdq (SP=3) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 000000000000160d
+ddedpdq (SP=0) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 0000000000000189
+ddedpdq (SP=1) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 0000000000000189
+ddedpdq (SP=2) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 000000000000189c
+ddedpdq (SP=3) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 000000000000189f
+ddedpdq (SP=0) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 0000004123456789
+ddedpdq (SP=1) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 0000004123456789
+ddedpdq (SP=2) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 000004123456789d
+ddedpdq (SP=3) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 000004123456789d
+ddedpdq (SP=0) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000097100000000 9839871234533354
+ddedpdq (SP=1) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000097100000000 9839871234533354
+ddedpdq (SP=2) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000971000000009 839871234533354c
+ddedpdq (SP=3) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000971000000009 839871234533354f
+ddedpdq (SP=0) [D->B]000400000089b000 0a6000d000000049 ==> 0000010954000051 8000640000000049
+ddedpdq (SP=1) [D->B]000400000089b000 0a6000d000000049 ==> 0000010954000051 8000640000000049
+ddedpdq (SP=2) [D->B]000400000089b000 0a6000d000000049 ==> 0000109540000518 000640000000049c
+ddedpdq (SP=3) [D->B]000400000089b000 0a6000d000000049 ==> 0000109540000518 000640000000049f
+ddedpdq (SP=0) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 000000000000000c
+ddedpdq (SP=3) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 000000000000000f
+ddedpdq (SP=0) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=0) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=0) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 000000000000000c
+ddedpdq (SP=3) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 000000000000000f
+ddedpdq (SP=0) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000080000 0200801330811600
+ddedpdq (SP=1) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000080000 0200801330811600
+ddedpdq (SP=2) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000800000 200801330811600d
+ddedpdq (SP=3) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000800000 200801330811600d
+ddedpdq (SP=0) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000088170 0000003882028150
+ddedpdq (SP=1) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000088170 0000003882028150
+ddedpdq (SP=2) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000881700 000003882028150c
+ddedpdq (SP=3) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000881700 000003882028150f
+ddedpdq (SP=0) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 000000000000000c
+ddedpdq (SP=3) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 000000000000000f
+ddedpdq (SP=0) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=0) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+
+Test DFP BCD-to-DPD instructions
+denbcd (S=0) [B->D]0000000000003450 ==> 2238000000000e50
+denbcd (S=1) [B->D]0000000000003450 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000003450c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000003450c ==> 2238000000000e50
+denbcd (S=0) [B->D]000000000003450f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000003450f ==> 2238000000000e50
+denbcd (S=0) [B->D]0000000001230000 ==> 223800000014c000
+denbcd (S=1) [B->D]0000000001230000 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000001230000c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000001230000c ==> 223800000014c000
+denbcd (S=0) [B->D]000000001230000f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000001230000f ==> 223800000014c000
+denbcd (S=0) [B->D]0000000000000160 ==> 22380000000000e0
+denbcd (S=1) [B->D]0000000000000160 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000160d ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000160d ==> a2380000000000e0
+denbcd (S=0) [B->D]0000000000000189 ==> 22380000000000cf
+denbcd (S=1) [B->D]0000000000000189 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000189c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000189c ==> 22380000000000cf
+denbcd (S=0) [B->D]000000000000189f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000189f ==> 22380000000000cf
+denbcd (S=0) [B->D]0000004123456789 ==> 223800010a395bcf
+denbcd (S=1) [B->D]0000004123456789 ==> 7c00000000000000
+denbcd (S=0) [B->D]000004123456789d ==> 7c00000000000000
+denbcd (S=1) [B->D]000004123456789d ==> a23800010a395bcf
+denbcd (S=0) [B->D]9839871234533354 ==> 6e393f1f534acdd4
+denbcd (S=1) [B->D]9839871234533354 ==> 7c00000000000000
+denbcd (S=0) [B->D]839871234533354c ==> 7c00000000000000
+denbcd (S=1) [B->D]839871234533354c ==> 22393f1f534acdd4
+denbcd (S=0) [B->D]839871234533354f ==> 7c00000000000000
+denbcd (S=1) [B->D]839871234533354f ==> 22393f1f534acdd4
+denbcd (S=0) [B->D]0000000008864000 ==> 223800000089b000
+denbcd (S=1) [B->D]0000000008864000 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000008864000c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000008864000c ==> 223800000089b000
+denbcd (S=0) [B->D]000000008864000f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000008864000f ==> 223800000089b000
+denbcd (S=0) [B->D]0000000000000000 ==> 2238000000000000
+denbcd (S=1) [B->D]0000000000000000 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000000c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000000c ==> 2238000000000000
+denbcd (S=0) [B->D]000000000000000f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000000f ==> 2238000000000000
+denbcd (S=0) [B->D]000000000000000d ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000000d ==> a238000000000000
+denbcd (S=0) [B->D]0000000000000211 ==> 2238000000000111
+denbcd (S=1) [B->D]0000000000000211 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000211c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000211c ==> 2238000000000111
+denbcd (S=0) [B->D]000000000000211f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000211f ==> 2238000000000111
+denbcd (S=0) [B->D]0000003882028150 ==> 22380000d0e0a0d0
+denbcd (S=1) [B->D]0000003882028150 ==> 7c00000000000000
+denbcd (S=0) [B->D]000003882028150d ==> 7c00000000000000
+denbcd (S=1) [B->D]000003882028150d ==> a2380000d0e0a0d0
+
+denbcdq (S=0) [B->D]0000000000000000 0000000000003450 ==> 2208000000000000 0000000000000e50
+denbcdq (S=1) [B->D]0000000000000000 0000000000003450 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000003450c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000003450c ==> 2208000000000000 0000000000000e50
+denbcdq (S=0) [B->D]0000000000000000 000000000003450f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000003450f ==> 2208000000000000 0000000000000e50
+denbcdq (S=0) [B->D]0000000000000000 0000000001230000 ==> 2208000000000000 000000000014c000
+denbcdq (S=1) [B->D]0000000000000000 0000000001230000 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000001230000c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000001230000c ==> 2208000000000000 000000000014c000
+denbcdq (S=0) [B->D]0000000000000000 000000001230000f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000001230000f ==> 2208000000000000 000000000014c000
+denbcdq (S=0) [B->D]0000000000000000 0000000000000160 ==> 2208000000000000 00000000000000e0
+denbcdq (S=1) [B->D]0000000000000000 0000000000000160 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000160d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000160d ==> a208000000000000 00000000000000e0
+denbcdq (S=0) [B->D]0000000000000000 0000000000000189 ==> 2208000000000000 00000000000000cf
+denbcdq (S=1) [B->D]0000000000000000 0000000000000189 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000189c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000189c ==> 2208000000000000 00000000000000cf
+denbcdq (S=0) [B->D]0000000000000000 000000000000189f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000189f ==> 2208000000000000 00000000000000cf
+denbcdq (S=0) [B->D]0000000000000000 0000004123456789 ==> 2208000000000000 000000010a395bcf
+denbcdq (S=1) [B->D]0000000000000000 0000004123456789 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000004123456789d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000004123456789d ==> a208000000000000 000000010a395bcf
+denbcdq (S=0) [B->D]0000097100000000 9839871234533354 ==> 2208000000fd0000 00253f1f534acdd4
+denbcdq (S=1) [B->D]0000097100000000 9839871234533354 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000971000000009 839871234533354c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000971000000009 839871234533354c ==> 2208000000fd0000 00253f1f534acdd4
+denbcdq (S=0) [B->D]0000971000000009 839871234533354f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000971000000009 839871234533354f ==> 2208000000fd0000 00253f1f534acdd4
+denbcdq (S=0) [B->D]0000010954000051 8000640000000049 ==> 220800000089b000 0a6000d000000049
+denbcdq (S=1) [B->D]0000010954000051 8000640000000049 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000109540000518 000640000000049c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000109540000518 000640000000049c ==> 220800000089b000 0a6000d000000049
+denbcdq (S=0) [B->D]0000109540000518 000640000000049f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000109540000518 000640000000049f ==> 220800000089b000 0a6000d000000049
+denbcdq (S=0) [B->D]0000000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000000c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000000c ==> 2208000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000000f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000000f ==> 2208000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000000d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000000d ==> a208000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000080000 0200801330811600 ==> 2208000000000000 c00100035b007700
+denbcdq (S=1) [B->D]0000000000080000 0200801330811600 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000800000 200801330811600d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000800000 200801330811600d ==> a208000000000000 c00100035b007700
+denbcdq (S=0) [B->D]0000000000088170 0000003882028150 ==> 2208000000000000 fe000000d0e0a0d0
+denbcdq (S=1) [B->D]0000000000088170 0000003882028150 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000881700 000003882028150c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000881700 000003882028150c ==> 2208000000000000 fe000000d0e0a0d0
+denbcdq (S=0) [B->D]0000000000881700 000003882028150f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000881700 000003882028150f ==> 2208000000000000 fe000000d0e0a0d0
+
diff --git a/main/none/tests/ppc32/test_dfp5.vgtest b/main/none/tests/ppc32/test_dfp5.vgtest
new file mode 100644
index 0000000..9777d05
--- /dev/null
+++ b/main/none/tests/ppc32/test_dfp5.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp5
diff --git a/main/none/tests/ppc32/test_fx.stdout.exp_Minus_nan b/main/none/tests/ppc32/test_fx.stdout.exp_Minus_nan
new file mode 100644
index 0000000..c5610f8
--- /dev/null
+++ b/main/none/tests/ppc32/test_fx.stdout.exp_Minus_nan
@@ -0,0 +1,40 @@
+
+fsqrt 0.000000e+00 -> 0.00000000000000e+00
+fsqrt inf -> inf
+fsqrt -inf -> nan
+fsqrt nan -> nan
+fsqrt -nan -> -nan
+fsqrt -5.000000e+100 -> nan
+fsqrt -5.000000e+20 -> nan
+fsqrt -5.010000e+02 -> nan
+fsqrt -6.000000e+00 -> nan
+fsqrt -1.000000e+00 -> nan
+fsqrt -2.000000e-20 -> nan
+fsqrt -2.000000e-200 -> nan
+fsqrt 2.000000e-200 -> 1.41421356237310e-100
+fsqrt 2.000000e-20 -> 1.41421356237310e-10
+fsqrt 1.000000e+00 -> 1.00000000000000e+00
+fsqrt 6.000000e+00 -> 2.44948974278318e+00
+fsqrt 5.010000e+02 -> 2.23830292855994e+01
+fsqrt 5.000000e+20 -> 2.23606797749979e+10
+fsqrt 5.000000e+100 -> 2.23606797749979e+50
+
+fsqrts 0.000000e+00 -> 0.000000e+00
+fsqrts inf -> inf
+fsqrts -inf -> nan
+fsqrts nan -> nan
+fsqrts -nan -> -nan
+fsqrts -5.000000e+100 -> nan
+fsqrts -5.000000e+20 -> nan
+fsqrts -5.010000e+02 -> nan
+fsqrts -6.000000e+00 -> nan
+fsqrts -1.000000e+00 -> nan
+fsqrts -2.000000e-20 -> nan
+fsqrts -2.000000e-200 -> nan
+fsqrts 2.000000e-200 -> 1.414214e-100
+fsqrts 2.000000e-20 -> 1.414214e-10
+fsqrts 1.000000e+00 -> 1.000000e+00
+fsqrts 6.000000e+00 -> 2.449490e+00
+fsqrts 5.010000e+02 -> 2.238303e+01
+fsqrts 5.000000e+20 -> 2.236068e+10
+fsqrts 5.000000e+100 -> 2.236068e+50
diff --git a/main/none/tests/ppc32/test_gx.stdout.exp_Minus_nan b/main/none/tests/ppc32/test_gx.stdout.exp_Minus_nan
new file mode 100644
index 0000000..5fe4e19
--- /dev/null
+++ b/main/none/tests/ppc32/test_gx.stdout.exp_Minus_nan
@@ -0,0 +1,80 @@
+
+fre 0.000000e+00 -> inf
+fre inf -> 0.0e+00
+fre -inf -> -0.0e+00
+fre nan -> nan
+fre -nan -> -nan
+fre -5.000000e+100 -> -2.0e-101
+fre -5.000000e+20 -> -2.0e-21
+fre -5.010000e+02 -> -2.0e-03
+fre -6.000000e+00 -> -1.7e-01
+fre -1.010000e+00 -> -9.9e-01
+fre -2.000000e-20 -> -5.0e+19
+fre -2.000000e-200 -> -5.0e+199
+fre 2.000000e-200 -> 5.0e+199
+fre 2.000000e-20 -> 5.0e+19
+fre 1.010000e+00 -> 9.9e-01
+fre 6.000000e+00 -> 1.7e-01
+fre 5.010000e+02 -> 2.0e-03
+fre 5.000000e+20 -> 2.0e-21
+fre 5.000000e+100 -> 2.0e-101
+
+fres 0.000000e+00 -> inf
+fres inf -> 0.0e+00
+fres -inf -> -0.0e+00
+fres nan -> nan
+fres -nan -> -nan
+fres -5.000000e+100 -> -0.0e+00
+fres -5.000000e+20 -> -2.0e-21
+fres -5.010000e+02 -> -2.0e-03
+fres -6.000000e+00 -> -1.7e-01
+fres -1.010000e+00 -> -9.9e-01
+fres -2.000000e-20 -> -5.0e+19
+fres -2.000000e-200 -> -inf
+fres 2.000000e-200 -> inf
+fres 2.000000e-20 -> 5.0e+19
+fres 1.010000e+00 -> 9.9e-01
+fres 6.000000e+00 -> 1.7e-01
+fres 5.010000e+02 -> 2.0e-03
+fres 5.000000e+20 -> 2.0e-21
+fres 5.000000e+100 -> 0.0e+00
+
+frsqrte 0.000000e+00 -> inf
+frsqrte inf -> 0.0e+00
+frsqrte -inf -> nan
+frsqrte nan -> nan
+frsqrte -nan -> -nan
+frsqrte -5.000000e+100 -> nan
+frsqrte -5.000000e+20 -> nan
+frsqrte -5.010000e+02 -> nan
+frsqrte -6.000000e+00 -> nan
+frsqrte -1.010000e+00 -> nan
+frsqrte -2.000000e-20 -> nan
+frsqrte -2.000000e-200 -> nan
+frsqrte 2.000000e-200 -> 7.1e+99
+frsqrte 2.000000e-20 -> 7.1e+09
+frsqrte 1.010000e+00 -> 1.0e+00
+frsqrte 6.000000e+00 -> 4.1e-01
+frsqrte 5.010000e+02 -> 4.5e-02
+frsqrte 5.000000e+20 -> 4.5e-11
+frsqrte 5.000000e+100 -> 4.5e-51
+
+frsqrtes 0.000000e+00 -> inf
+frsqrtes inf -> 0.0e+00
+frsqrtes -inf -> nan
+frsqrtes nan -> nan
+frsqrtes -nan -> -nan
+frsqrtes -5.000000e+100 -> nan
+frsqrtes -5.000000e+20 -> nan
+frsqrtes -5.010000e+02 -> nan
+frsqrtes -6.000000e+00 -> nan
+frsqrtes -1.010000e+00 -> nan
+frsqrtes -2.000000e-20 -> nan
+frsqrtes -2.000000e-200 -> nan
+frsqrtes 2.000000e-200 -> 7.1e+99
+frsqrtes 2.000000e-20 -> 7.1e+09
+frsqrtes 1.010000e+00 -> 1.0e+00
+frsqrtes 6.000000e+00 -> 4.1e-01
+frsqrtes 5.010000e+02 -> 4.5e-02
+frsqrtes 5.000000e+20 -> 4.5e-11
+frsqrtes 5.000000e+100 -> 4.5e-51
diff --git a/main/none/tests/ppc32/test_isa_2_06_part1.c b/main/none/tests/ppc32/test_isa_2_06_part1.c
new file mode 100644
index 0000000..25dcc2e
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part1.c
@@ -0,0 +1,2188 @@
+/* Copyright (C) 2011 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#ifdef HAS_VSX
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+static int errors;
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int cond_reg;
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+typedef void (*test_func_t)(void);
+typedef struct ldst_test ldst_test_t;
+typedef struct vsx_logic_test logic_test_t;
+typedef struct xs_conv_test xs_conv_test_t;
+typedef struct p7_fp_test fp_test_t;
+typedef struct vx_fp_test vx_fp_test_t;
+typedef struct vsx_move_test move_test_t;
+typedef struct vsx_permute_test permute_test_t;
+typedef struct test_table test_table_t;
+
+static double *fargs = NULL;
+static int nb_fargs;
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+static void build_fargs_table(void)
+/*
+ * Double precision:
+ * Sign goes from zero to one (1 bit)
+ * Exponent goes from 0 to ((1 << 12) - 1) (11 bits)
+ * Mantissa goes from 1 to ((1 << 52) - 1) (52 bits)
+ * + special values:
+ * +0.0 : 0 0x000 0x0000000000000 => 0x0000000000000000
+ * -0.0 : 1 0x000 0x0000000000000 => 0x8000000000000000
+ * +infinity : 0 0x7FF 0x0000000000000 => 0x7FF0000000000000
+ * -infinity : 1 0x7FF 0x0000000000000 => 0xFFF0000000000000
+ * +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF => 0x7FF7FFFFFFFFFFFF
+ * -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF => 0xFFF7FFFFFFFFFFFF
+ * +SNaN : 0 0x7FF 0x8000000000000 => 0x7FF8000000000000
+ * -SNaN : 1 0x7FF 0x8000000000000 => 0xFFF8000000000000
+ * (8 values)
+ *
+ * Single precision
+ * Sign: 1 bit
+ * Exponent: 8 bits
+ * Mantissa: 23 bits
+ * +0.0 : 0 0x00 0x000000 => 0x00000000
+ * -0.0 : 1 0x00 0x000000 => 0x80000000
+ * +infinity : 0 0xFF 0x000000 => 0x7F800000
+ * -infinity : 1 0xFF 0x000000 => 0xFF800000
+ * +QNaN : 0 0xFF 0x3FFFFF => 0x7FBFFFFF
+ * -QNaN : 1 0xFF 0x3FFFFF => 0xFFBFFFFF
+ * +SNaN : 0 0xFF 0x400000 => 0x7FC00000
+ * -SNaN : 1 0xFF 0x400000 => 0xFFC00000
+*/
+{
+ uint64_t mant;
+ uint16_t _exp, e1;
+ int s;
+ int i=0;
+
+ if (nb_fargs)
+ return;
+
+ fargs = malloc( 16 * sizeof(double) );
+ for (s = 0; s < 2; s++) {
+ for (e1 = 0x001;; e1 = ((e1 + 1) << 13) + 7) {
+ if (e1 >= 0x400)
+ e1 = 0x3fe;
+ _exp = e1;
+ for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
+ /* Add 'random' bits */
+ mant = ((mant + 0x4A6) << 29) + 0x359) {
+ register_farg( &fargs[i++], s, _exp, mant );
+ }
+ if (e1 == 0x3fe)
+ break;
+ }
+ }
+ // add a few smaller values to fargs . . .
+ s = 0;
+ _exp = 0x002;
+ mant = 0x0000000000b01ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ _exp = 0x000;
+ mant = 0x00000203f0b3dULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ mant = 0x00000005a203dULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ s = 1;
+ _exp = 0x002;
+ mant = 0x0000000000b01ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ _exp = 0x000;
+ mant = 0x00000203f0b3dULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ nb_fargs = i;
+}
+
+
+typedef struct ftdiv_test {
+ int fra_idx;
+ int frb_idx;
+ int cr_flags;
+} ftdiv_test_args_t;
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+ int cr_flags;
+ unsigned long long dp_bin_result;
+} fp_test_args_t;
+
+unsigned long long xscvuxddp_results[] = {
+ 0x43cfec0000000000ULL,
+ 0x43d013c000000000ULL,
+ 0x4338000000b77501ULL,
+ 0x43dffa0000000001ULL,
+ 0x4372321456990000ULL,
+ 0x0000000000000000ULL,
+ 0x43e0000000000000ULL,
+ 0x43dffc0000000000ULL,
+ 0x43effe0000000000ULL,
+ 0x43dffe0000000000ULL,
+ 0x43efff0000000000ULL,
+ 0x43dffe0000000000ULL,
+ 0x43efff0000000000ULL,
+ 0x43e00106800000f0ULL,
+ 0x43e81a0ca1eb40f6ULL
+};
+
+unsigned long long xscvsxddp_results[] = {
+ 0x43cfec0000000000ULL,
+ 0x43d013c000000000ULL,
+ 0x4338000000b77501ULL,
+ 0x43dffa0000000001ULL,
+ 0x4372321456990000ULL,
+ 0x0000000000000000ULL,
+ 0xc3e0000000000000ULL,
+ 0x43dffc0000000000ULL,
+ 0xc330000000000000ULL,
+ 0x43dffe0000000000ULL,
+ 0xc320000000000002ULL,
+ 0x43dffe0000000000ULL,
+ 0xc320000000000000ULL,
+ 0xc3dffdf2fffffe20ULL,
+ 0xc3cf97cd7852fc26ULL,
+};
+
+unsigned long long xscvdpsxds_results[] = {
+ 0x0000000000000000ULL,
+ 0x000000000000003eULL,
+ 0x0000000000000000ULL,
+ 0x7fffffffffffffffULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x7fffffffffffffffULL,
+ 0x8000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0xffffffffffffbe6cULL
+};
+
+ftdiv_test_args_t ftdiv_tests[] = {
+ {0, 1, 0x8},
+ {9, 1, 0xa},
+ {1, 12, 0xa},
+ {0, 2, 0xa},
+ {1, 3, 0xa},
+ {3, 0, 0xa},
+ {0, 3, 0xa},
+ {4, 0, 0xa},
+ {7, 1, 0xe},
+ {8, 1, 0xe},
+ {1, 7, 0xe},
+ {0, 13, 0xe},
+ {5, 5, 0xe},
+ {5, 6, 0xe},
+};
+
+fp_test_args_t xscmpX_tests[] = {
+ {8, 8, 0x2, 0ULL},
+ {8, 14, 0x8, 0ULL},
+ {8, 6, 0x8, 0ULL},
+ {8, 5, 0x8, 0ULL},
+ {8, 4, 0x8, 0ULL},
+ {8, 7, 0x8, 0ULL},
+ {8, 9, 0x1, 0ULL},
+ {8, 11, 0x1, 0ULL},
+ {14, 8, 0x4, 0ULL},
+ {14, 14, 0x2, 0ULL},
+ {14, 6, 0x8, 0ULL},
+ {14, 5, 0x8, 0ULL},
+ {14, 4, 0x8, 0ULL},
+ {14, 7, 0x8, 0ULL},
+ {14, 9, 0x1, 0ULL},
+ {14, 11, 0x1, 0ULL},
+ {6, 8, 0x4, 0ULL},
+ {6, 14, 0x4, 0ULL},
+ {6, 6, 0x2, 0ULL},
+ {6, 5, 0x2, 0ULL},
+ {6, 4, 0x8, 0ULL},
+ {6, 7, 0x8, 0ULL},
+ {6, 9, 0x1, 0ULL},
+ {6, 11, 0x1, 0ULL},
+ {5, 8, 0x4, 0ULL},
+ {5, 14, 0x4, 0ULL},
+ {5, 6, 0x2, 0ULL},
+ {5, 5, 0x2, 0ULL},
+ {5, 4, 0x8, 0ULL},
+ {5, 7, 0x8, 0ULL},
+ {5, 9, 0x1, 0ULL},
+ {5, 11, 0x1, 0ULL},
+ {4, 8, 0x4, 0ULL},
+ {4, 14, 0x4, 0ULL},
+ {4, 6, 0x4, 0ULL},
+ {4, 5, 0x4, 0ULL},
+ {4, 1, 0x8, 0ULL},
+ {4, 7, 0x8, 0ULL},
+ {4, 9, 0x1, 0ULL},
+ {4, 11, 0x1, 0ULL},
+ {7, 8, 0x4, 0ULL},
+ {7, 14, 0x4, 0ULL},
+ {7, 6, 0x4, 0ULL},
+ {7, 5, 0x4, 0ULL},
+ {7, 4, 0x4, 0ULL},
+ {7, 7, 0x2, 0ULL},
+ {7, 9, 0x1, 0ULL},
+ {7, 11, 0x1, 0ULL},
+ {10, 8, 0x1, 0ULL},
+ {10, 14, 0x1, 0ULL},
+ {10, 6, 0x1, 0ULL},
+ {10, 5, 0x1, 0ULL},
+ {10, 4, 0x1, 0ULL},
+ {10, 7, 0x1, 0ULL},
+ {10, 9, 0x1, 0ULL},
+ {10, 11, 0x1, 0ULL},
+ {12, 8, 0x1, 0ULL},
+ {12, 14, 0x1, 0ULL},
+ {12, 6, 0x1, 0ULL},
+ {12, 5, 0x1, 0ULL},
+ {12, 4, 0x1, 0ULL},
+ {12, 7, 0x1, 0ULL},
+ {12, 9, 0x1, 0ULL},
+ {12, 11, 0x1, 0ULL},
+};
+
+fp_test_args_t xsadddp_tests[] = {
+ {8, 8, 0x0, 0xfff0000000000000ULL},
+ {8, 14, 0x0, 0xfff0000000000000ULL},
+ {8, 6, 0x0, 0xfff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0x7ff8000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0xfff0000000000000ULL},
+ {14, 14, 0x0, 0xc0e0650f5a07b353ULL},
+ {14, 6, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 5, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 4, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 7, 0x0, 0x7ff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0xfff0000000000000ULL},
+ {6, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x8000000000000000ULL},
+ {6, 5, 0x0, 0x0000000000000000ULL},
+ {6, 4, 0x0, 0x0123214569900000ULL},
+ {6, 7, 0x0, 0x7ff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0xfff0000000000000ULL},
+ {5, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x0000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x0123214569900000ULL},
+ {5, 7, 0x0, 0x7ff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0xfff0000000000000ULL},
+ {4, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x0123214569900000ULL},
+ {4, 5, 0x0, 0x0123214569900000ULL},
+ {4, 1, 0x0, 0x404f000000000000ULL},
+ {4, 7, 0x0, 0x7ff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff8000000000000ULL},
+ {7, 14, 0x0, 0x7ff0000000000000ULL},
+ {7, 6, 0x0, 0x7ff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff0000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsdivdp_tests[] = {
+ {8, 8, 0x0, 0x7ff8000000000000ULL},
+ {8, 14, 0x0, 0x7ff0000000000000ULL},
+ {8, 6, 0x0, 0x7ff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0x7ff8000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x0000000000000000ULL},
+ {14, 14, 0x0, 0x3ff0000000000000ULL},
+ {14, 6, 0x0, 0x7ff0000000000000ULL},
+ {14, 5, 0x0, 0xfff0000000000000ULL},
+ {14, 4, 0x0, 0xff9b6cb57ca13c00ULL},
+ {14, 7, 0x0, 0x8000000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x0000000000000000ULL},
+ {6, 14, 0x0, 0x0000000000000000ULL},
+ {6, 6, 0x0, 0x7ff8000000000000ULL},
+ {6, 5, 0x0, 0x7ff8000000000000ULL},
+ {6, 4, 0x0, 0x8000000000000000ULL},
+ {6, 7, 0x0, 0x8000000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x8000000000000000ULL},
+ {5, 14, 0x0, 0x8000000000000000ULL},
+ {5, 6, 0x0, 0x7ff8000000000000ULL},
+ {5, 5, 0x0, 0x7ff8000000000000ULL},
+ {5, 4, 0x0, 0x0000000000000000ULL},
+ {5, 7, 0x0, 0x0000000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0x8000000000000000ULL},
+ {4, 14, 0x0, 0x8042ab59d8b6ec87ULL},
+ {4, 6, 0x0, 0xfff0000000000000ULL},
+ {4, 5, 0x0, 0x7ff0000000000000ULL},
+ {4, 1, 0x0, 0x00c3bf3f64b5ad6bULL},
+ {4, 7, 0x0, 0x0000000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff8000000000000ULL},
+ {7, 14, 0x0, 0xfff0000000000000ULL},
+ {7, 6, 0x0, 0xfff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff8000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsmaddXdp_tests[] = {
+ {8, 8, 0x0, 0x7ff8000000000000ULL},
+ {8, 14, 0x0, 0xfff0000000000000ULL},
+ {8, 6, 0x0, 0x7ff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0x7ff0000000000000ULL},
+ {8, 7, 0x0, 0x7ff8000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0xfff0000000000000ULL},
+ {14, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 5, 0x0, 0x82039a19ca8fcb5fULL},
+ {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 7, 0x0, 0x7ff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0xfff0000000000000ULL},
+ {6, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x0000000000000000ULL},
+ {6, 5, 0x0, 0x0000000000000000ULL},
+ {6, 4, 0x0, 0x0123214569900000ULL},
+ {6, 7, 0x0, 0x7ff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0xfff0000000000000ULL},
+ {5, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x8000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x0123214569900000ULL},
+ {5, 7, 0x0, 0x7ff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0xfff0000000000000ULL},
+ {4, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x82039a19ca8fcb5fULL},
+ {4, 5, 0x0, 0x0000000000000000ULL},
+ {4, 1, 0x0, 0x404f000000000000ULL},
+ {4, 7, 0x0, 0x7ff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0xfff0000000000000ULL},
+ {7, 14, 0x0, 0x7ff0000000000000ULL},
+ {7, 6, 0x0, 0xfff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0xfff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff0000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsmsubXdp_tests[] = {
+ {8, 8, 0x0, 0x7ff0000000000000ULL},
+ {8, 14, 0x0, 0xfff0000000000000ULL},
+ {8, 6, 0x0, 0x7ff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0x7ff0000000000000ULL},
+ {8, 7, 0x0, 0xfff0000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x7ff0000000000000ULL},
+ {14, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 5, 0x0, 0x82039a19ca8fcb5fULL},
+ {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 7, 0x0, 0xfff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x7ff0000000000000ULL},
+ {6, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x0000000000000000ULL},
+ {6, 5, 0x0, 0x8000000000000000ULL},
+ {6, 4, 0x0, 0x8123214569900000ULL},
+ {6, 7, 0x0, 0xfff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x7ff0000000000000ULL},
+ {5, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x0000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x8123214569900000ULL},
+ {5, 7, 0x0, 0xfff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0x7ff0000000000000ULL},
+ {4, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x82039a19ca8fcb5fULL},
+ {4, 5, 0x0, 0x0000000000000000ULL},
+ {4, 1, 0x0, 0xc04f000000000000ULL},
+ {4, 7, 0x0, 0xfff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff8000000000000ULL},
+ {7, 14, 0x0, 0x7ff0000000000000ULL},
+ {7, 6, 0x0, 0xfff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0xfff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff8000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsnmaddXdp_tests[] = {
+ {8, 8, 0x0, 0x7ff8000000000000ULL},
+ {8, 14, 0x0, 0x7ff0000000000000ULL},
+ {8, 6, 0x0, 0xfff0000000000000ULL},
+ {8, 5, 0x0, 0x7ff0000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0x7ff8000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x7ff0000000000000ULL},
+ {14, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {14, 6, 0x0, 0xc1b0cc9d05eec2a7ULL},
+ {14, 5, 0x0, 0x02039a19ca8fcb5fULL},
+ {14, 4, 0x0, 0xc1b0cc9d05eec2a7ULL},
+ {14, 7, 0x0, 0xfff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x7ff0000000000000ULL},
+ {6, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x8000000000000000ULL},
+ {6, 5, 0x0, 0x8000000000000000ULL},
+ {6, 4, 0x0, 0x8123214569900000ULL},
+ {6, 7, 0x0, 0xfff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x7ff0000000000000ULL},
+ {5, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x0000000000000000ULL},
+ {5, 5, 0x0, 0x8000000000000000ULL},
+ {5, 4, 0x0, 0x8123214569900000ULL},
+ {5, 7, 0x0, 0xfff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0x7ff0000000000000ULL},
+ {4, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x02039a19ca8fcb5fULL},
+ {4, 5, 0x0, 0x8000000000000000ULL},
+ {4, 1, 0x0, 0xc04f000000000000ULL},
+ {4, 7, 0x0, 0xfff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff0000000000000ULL},
+ {7, 14, 0x0, 0xfff0000000000000ULL},
+ {7, 6, 0x0, 0x7ff0000000000000ULL},
+ {7, 5, 0x0, 0xfff0000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0xfff0000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsmuldp_tests[] = {
+ {8, 8, 0x0, 0x7ff0000000000000ULL},
+ {8, 14, 0x0, 0x7ff0000000000000ULL},
+ {8, 6, 0x0, 0x7ff8000000000000ULL},
+ {8, 5, 0x0, 0x7ff8000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0xfff0000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x7ff0000000000000ULL},
+ {14, 14, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 6, 0x0, 0x0000000000000000ULL},
+ {14, 5, 0x0, 0x8000000000000000ULL},
+ {14, 4, 0x0, 0x82039a19ca8fcb5fULL},
+ {14, 7, 0x0, 0xfff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x7ff8000000000000ULL},
+ {6, 14, 0x0, 0x0000000000000000ULL},
+ {6, 6, 0x0, 0x0000000000000000ULL},
+ {6, 5, 0x0, 0x8000000000000000ULL},
+ {6, 4, 0x0, 0x8000000000000000ULL},
+ {6, 7, 0x0, 0x7ff8000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x7ff8000000000000ULL},
+ {5, 14, 0x0, 0x8000000000000000ULL},
+ {5, 6, 0x0, 0x8000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x0000000000000000ULL},
+ {5, 7, 0x0, 0x7ff8000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0xfff0000000000000ULL},
+ {4, 14, 0x0, 0x82039a19ca8fcb5fULL},
+ {4, 6, 0x0, 0x8000000000000000ULL},
+ {4, 5, 0x0, 0x0000000000000000ULL},
+ {4, 1, 0x0, 0x0182883b3e438000ULL},
+ {4, 7, 0x0, 0x7ff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0xfff0000000000000ULL},
+ {7, 14, 0x0, 0xfff0000000000000ULL},
+ {7, 6, 0x0, 0x7ff8000000000000ULL},
+ {7, 5, 0x0, 0x7ff8000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff0000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xssubdp_tests[] = {
+ {8, 8, 0x0, 0x7ff8000000000000ULL},
+ {8, 14, 0x0, 0xfff0000000000000ULL},
+ {8, 6, 0x0, 0xfff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0xfff0000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x7ff0000000000000ULL},
+ {14, 14, 0x0, 0x0000000000000000ULL},
+ {14, 6, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 5, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 4, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 7, 0x0, 0xfff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x7ff0000000000000ULL},
+ {6, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x0000000000000000ULL},
+ {6, 5, 0x0, 0x8000000000000000ULL},
+ {6, 4, 0x0, 0x8123214569900000ULL},
+ {6, 7, 0x0, 0xfff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x7ff0000000000000ULL},
+ {5, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x0000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x8123214569900000ULL},
+ {5, 7, 0x0, 0xfff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0x7ff0000000000000ULL},
+ {4, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x0123214569900000ULL},
+ {4, 5, 0x0, 0x0123214569900000ULL},
+ {4, 1, 0x0, 0xc04f000000000000ULL},
+ {4, 7, 0x0, 0xfff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff0000000000000ULL},
+ {7, 14, 0x0, 0x7ff0000000000000ULL},
+ {7, 6, 0x0, 0x7ff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff8000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+
+
+static int nb_special_fargs;
+static double * spec_fargs;
+
+static void build_special_fargs_table(void)
+{
+ /* The special floating point values created below are for
+ * use in the ftdiv tests for setting the fe_flag and fg_flag,
+ * but they can also be used for other tests (e.g., xscmpudp).
+ *
+ * Note that fl_flag is 'always '1' on ppc64 Linux.
+ *
+ Entry Sign Exp fraction Special value
+ 0 0 3fd 0x8000000000000ULL Positive finite number
+ 1 0 404 0xf000000000000ULL ...
+ 2 0 001 0x8000000b77501ULL ...
+ 3 0 7fe 0x800000000051bULL ...
+ 4 0 012 0x3214569900000ULL ...
+ 5 0 000 0x0000000000000ULL +0.0 (+zero)
+ 6 1 000 0x0000000000000ULL -0.0 (-zero)
+ 7 0 7ff 0x0000000000000ULL +infinity
+ 8 1 7ff 0x0000000000000ULL -infinity
+ 9 0 7ff 0x7FFFFFFFFFFFFULL +QNaN
+ 10 1 7ff 0x7FFFFFFFFFFFFULL -QNaN
+ 11 0 7ff 0x8000000000000ULL +SNaN
+ 12 1 7ff 0x8000000000000ULL -SNaN
+ 13 1 000 0x8340000078000ULL Denormalized val (zero exp and non-zero fraction)
+ 14 1 40d 0x0650f5a07b353ULL Negative finite number
+ */
+
+ uint64_t mant;
+ uint16_t _exp;
+ int s;
+ int i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 16 * sizeof(double) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* None of the ftdiv tests succeed.
+ * FRA = value #0; FRB = value #1
+ * ea_ = -2; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 100
+ */
+
+ /*************************************************
+ * fe_flag tests
+ *
+ *************************************************/
+
+ /* fe_flag <- 1 if FRA is a NaN
+ * FRA = value #9; FRB = value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRB is a NaN
+ * FRA = value #1; FRB = value #12
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if e_b <= -1022
+ * FRA = value #0; FRB = value #2
+ * e_a = -2; e_b = -1022
+ * fl_flag || fg_flag || fe_flag = 101
+ *
+ */
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if e_b >= 1021
+ * FRA = value #1; FRB = value #3
+ * e_a = 5; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b >= 1023
+ * Let FRA = value #3 and FRB be value #0.
+ * e_a = 1023; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b <= -1023
+ * Let FRA = value #0 above and FRB be value #3 above
+ * e_a = -2; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a <= -970
+ * Let FRA = value #4 and FRB be value #0
+ * e_a = -1005; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /*************************************************
+ * fg_flag tests
+ *
+ *************************************************/
+ /* fg_flag <- 1 if FRA is an Infinity
+ * NOTE: FRA = Inf also sets fe_flag
+ * Do two tests, using values #7 and #8 (+/- Inf) for FRA.
+ * Test 1:
+ * Let FRA be value #7 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ * Test 2:
+ * Let FRA be value #8 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ */
+
+ /* fg_flag <- 1 if FRB is an Infinity
+ * NOTE: FRB = Inf also sets fe_flag
+ * Let FRA be value #1 and FRB be value #7
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is denormalized
+ * NOTE: e_b < -1022 ==> fe_flag <- 1
+ * Let FRA be value #0 and FRB be value #13
+ * e_a = -2; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is +zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #5
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is -zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #6
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +SNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -SNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ nb_special_fargs = i;
+}
+
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+struct p7_fp_test
+{
+ test_func_t test_func;
+ const char *name;
+ int single; // 1=single precision result; 0=double precision result
+};
+
+typedef enum {
+ VX_FP_CMP,
+ VX_FP_SMA,
+ VX_FP_SMS,
+ VX_FP_SNMA,
+ VX_FP_OTHER
+} vx_fp_test_type;
+
+struct vx_fp_test
+{
+ test_func_t test_func;
+ const char *name;
+ fp_test_args_t * targs;
+ int num_tests;
+ vx_fp_test_type test_type;
+};
+
+struct xs_conv_test
+{
+ test_func_t test_func;
+ const char *name;
+ unsigned long long * results;
+ int num_tests;
+};
+
+typedef enum {
+ VSX_LOAD =1,
+ VSX_LOAD_SPLAT,
+ VSX_STORE
+} vsx_ldst_type;
+
+struct ldst_test
+{
+ test_func_t test_func;
+ const char *name;
+ void * base_addr;
+ uint32_t offset;
+ int num_words_to_process;
+ vsx_ldst_type type;
+};
+
+typedef enum {
+ VSX_AND = 1,
+ VSX_XOR,
+ VSX_ANDC,
+ VSX_OR,
+ VSX_NOR
+} vsx_log_op;
+
+struct vsx_logic_test
+{
+ test_func_t test_func;
+ const char *name;
+ vsx_log_op op;
+};
+
+struct vsx_move_test
+{
+ test_func_t test_func;
+ const char *name;
+ int xa_idx, xb_idx;
+ unsigned long long expected_result;
+};
+
+struct vsx_permute_test
+{
+ test_func_t test_func;
+ const char *name;
+ unsigned int xa[4];
+ unsigned int xb[4];
+ unsigned int expected_output[4];
+};
+
+static vector unsigned int vec_out, vec_inA, vec_inB;
+
+static void test_lxsdx(void)
+{
+ __asm__ __volatile__ ("lxsdx %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void
+test_lxvd2x(void)
+{
+ __asm__ __volatile__ ("lxvd2x %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_lxvdsx(void)
+{
+ __asm__ __volatile__ ("lxvdsx %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_lxvw4x(void)
+{
+ __asm__ __volatile__ ("lxvw4x %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_stxsdx(void)
+{
+ __asm__ __volatile__ ("stxsdx %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_stxvd2x(void)
+{
+ __asm__ __volatile__ ("stxvd2x %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_stxvw4x(void)
+{
+ __asm__ __volatile__ ("stxvw4x %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_xxlxor(void)
+{
+ __asm__ __volatile__ ("xxlxor %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlor(void)
+{
+ __asm__ __volatile__ ("xxlor %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlnor(void)
+{
+ __asm__ __volatile__ ("xxlnor %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxland(void)
+{
+ __asm__ __volatile__ ("xxland %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlandc(void)
+{
+ __asm__ __volatile__ ("xxlandc %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxmrghw(void)
+{
+ __asm__ __volatile__ ("xxmrghw %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxmrglw(void)
+{
+ __asm__ __volatile__ ("xxmrglw %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_00(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x0" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_01(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x1" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_10(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_11(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x3" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_0(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 0" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_1(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 1" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_2(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_3(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 3" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_fcfids (void)
+{
+ __asm__ __volatile__ ("fcfids %0, %1" : "=f" (f17): "d" (f14));
+}
+
+static void test_fcfidus (void)
+{
+ __asm__ __volatile__ ("fcfidus %0, %1" : "=f" (f17): "d" (f14));
+}
+
+static void test_fcfidu (void)
+{
+ __asm__ __volatile__ ("fcfidu %0, %1" : "=f" (f17): "d" (f14));
+}
+
+static void test_xsabsdp (void)
+{
+ __asm__ __volatile__ ("xsabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscpsgndp (void)
+{
+ __asm__ __volatile__ ("xscpsgndp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsnabsdp (void)
+{
+ __asm__ __volatile__ ("xsnabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsnegdp (void)
+{
+ __asm__ __volatile__ ("xsnegdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static int do_cmpudp;
+static void test_xscmp (void)
+{
+ if (do_cmpudp)
+ __asm__ __volatile__ ("xscmpudp cr1, %x0, %x1" : : "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xscmpodp cr1, %x0, %x1" : : "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsadddp(void)
+{
+ __asm__ __volatile__ ("xsadddp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsdivdp(void)
+{
+ __asm__ __volatile__ ("xsdivdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static int do_adp;
+static void test_xsmadd(void)
+{
+ if (do_adp)
+ __asm__ __volatile__ ("xsmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmsub(void)
+{
+ if (do_adp)
+ __asm__ __volatile__ ("xsmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsnmadd(void)
+{
+ if (do_adp)
+ __asm__ __volatile__ ("xsnmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsnmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmuldp(void)
+{
+ __asm__ __volatile__ ("xsmuldp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xssubdp(void)
+{
+ __asm__ __volatile__ ("xssubdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xscvdpsxds (void)
+{
+ __asm__ __volatile__ ("xscvdpsxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvsxddp (void)
+{
+ __asm__ __volatile__ ("xscvsxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvuxddp (void)
+{
+ __asm__ __volatile__ ("xscvuxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static unsigned int vstg[] __attribute__ ((aligned (16))) = { 0, 0, 0,0,
+ 0, 0, 0, 0 };
+
+#define NUM_VSTG_INTS (sizeof vstg/sizeof vstg[0])
+#define NUM_VSTG_VECS (NUM_VSTG_INTS/4)
+
+static unsigned int viargs[] __attribute__ ((aligned (16))) = { 0x01234567,
+ 0x89abcdef,
+ 0x00112233,
+ 0x44556677,
+ 0x8899aabb,
+ 0x91929394,
+ 0xa1a2a3a4,
+ 0xb1b2b3b4,
+ 0xc1c2c3c4,
+ 0xd1d2d3d4,
+ 0x7a6b5d3e
+};
+#define NUM_VIARGS_INTS (sizeof viargs/sizeof viargs[0])
+#define NUM_VIARGS_VECS (NUM_VIARGS_INTS/4)
+
+static ldst_test_t ldst_tests[] = { { &test_lxsdx, "lxsdx", viargs, 0, 2, VSX_LOAD },
+ { &test_lxsdx, "lxsdx", viargs, 4, 2, VSX_LOAD },
+ { &test_lxvd2x, "lxvd2x", viargs, 0, 4, VSX_LOAD },
+ { &test_lxvd2x, "lxvd2x", viargs, 4, 4, VSX_LOAD },
+ { &test_lxvdsx, "lxvdsx", viargs, 0, 4, VSX_LOAD_SPLAT },
+ { &test_lxvdsx, "lxvdsx", viargs, 4, 4, VSX_LOAD_SPLAT },
+ { &test_lxvw4x, "lxvw4x", viargs, 0, 4, VSX_LOAD },
+ { &test_lxvw4x, "lxvw4x", viargs, 4, 4, VSX_LOAD },
+ { &test_stxsdx, "stxsdx", vstg, 0, 2, VSX_STORE },
+ { &test_stxsdx, "stxsdx", vstg, 4, 2, VSX_STORE },
+ { &test_stxvd2x, "stxvd2x", vstg, 0, 4, VSX_STORE },
+ { &test_stxvd2x, "stxvd2x", vstg, 4, 4, VSX_STORE },
+ { &test_stxvw4x, "stxvw4x", vstg, 0, 4, VSX_STORE },
+ { &test_stxvw4x, "stxvw4x", vstg, 4, 4, VSX_STORE },
+ { NULL, NULL, NULL, 0, 0, 0 } };
+
+static logic_test_t logic_tests[] = { { &test_xxlxor, "xxlxor", VSX_XOR },
+ { &test_xxlor, "xxlor", VSX_OR } ,
+ { &test_xxlnor, "xxlnor", VSX_NOR },
+ { &test_xxland, "xxland", VSX_AND },
+ { &test_xxlandc, "xxlandc", VSX_ANDC },
+ { NULL, NULL}};
+
+static move_test_t move_tests[] = { { &test_xsabsdp, "xsabsdp", 0, 4, 0x0899aabb91929394ULL },
+ { &test_xscpsgndp, "xscpsgndp", 4, 0, 0x8123456789abcdefULL },
+ { &test_xsnabsdp, "xsnabsdp", 7, 3, 0xc45566778899aabbULL, },
+ { &test_xsnegdp, "xsnegdp", 0, 7, 0x31b2b3b4c1c2c3c4ULL, },
+ { NULL, NULL, 0, 0, 0 }
+
+};
+
+static permute_test_t permute_tests[] =
+{
+ { &test_xxmrghw, "xxmrghw",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x11111111, 0x55555555, 0x22222222, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxmrghw, "xxmrghw",
+ { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff }, /* XA input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XB input */
+ { 0x00112233, 0x11111111, 0x44556677, 0x22222222 } /* XT expected output */
+ },
+ { &test_xxmrglw, "xxmrglw",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x33333333, 0x77777777, 0x44444444, 0x88888888 } /* XT expected output */
+ },
+ { &test_xxmrglw, "xxmrglw",
+ { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff}, /* XA input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444}, /* XB input */
+ { 0x8899aabb, 0x33333333, 0xccddeeff, 0x44444444} /* XT expected output */
+ },
+ { &test_xxpermdi_00, "xxpermdi DM=00",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x11111111, 0x22222222, 0x55555555, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxpermdi_01, "xxpermdi DM=01",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x11111111, 0x22222222, 0x77777777, 0x88888888 } /* XT expected output */
+ },
+ { &test_xxpermdi_10, "xxpermdi DM=10",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxpermdi_11, "xxpermdi DM=11",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x33333333, 0x44444444, 0x77777777, 0x88888888 } /* XT expected output */
+ },
+ { &test_xxsldwi_0, "xxsldwi SHW=0",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 } /* XT expected output */
+ },
+ { &test_xxsldwi_1, "xxsldwi SHW=1",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x22222222, 0x33333333, 0x44444444, 0x55555555 } /* XT expected output */
+ },
+ { &test_xxsldwi_2, "xxsldwi SHW=2",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxsldwi_3, "xxsldwi SHW=3",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x44444444, 0x55555555, 0x66666666, 0x77777777 } /* XT expected output */
+ },
+ { NULL, NULL }
+};
+
+static fp_test_t fp_tests[] = { { &test_fcfids, "fcfids", 1 },
+ { &test_fcfidus, "fcfidus", 1 },
+ { &test_fcfidu, "fcfidu", 1 },
+ { NULL, NULL, 0 },
+
+};
+
+static vx_fp_test_t vx_fp_tests[] = {
+ { &test_xscmp, "xscmp", xscmpX_tests, 64, VX_FP_CMP},
+ { &test_xsadddp, "xsadddp", xsadddp_tests, 64, VX_FP_OTHER},
+ { &test_xsdivdp, "xsdivdp", xsdivdp_tests, 64, VX_FP_OTHER},
+ { &test_xsmadd, "xsmadd", xsmaddXdp_tests, 64, VX_FP_SMA},
+ { &test_xsmsub, "xsmsub", xsmsubXdp_tests, 64, VX_FP_SMS},
+ { &test_xsnmadd, "xsnmadd", xsnmaddXdp_tests, 64, VX_FP_SNMA},
+ { & test_xsmuldp, "xsmuldp", xsmuldp_tests, 64, VX_FP_OTHER},
+ { & test_xssubdp, "xssubdp", xssubdp_tests, 64, VX_FP_OTHER},
+ { NULL, NULL, NULL, 0, 0 }
+};
+
+static xs_conv_test_t xs_conv_tests[] = {
+ { &test_xscvdpsxds, "xscvdpsxds", xscvdpsxds_results, 15},
+ { &test_xscvsxddp, "xscvsxddp", xscvsxddp_results, 15},
+ { &test_xscvuxddp, "xscvuxddp", xscvuxddp_results, 15},
+ { NULL, NULL, NULL, 0}
+};
+
+#ifdef __powerpc64__
+static void test_ldbrx(void)
+{
+ int i, equality;
+ HWord_t reg_out;
+ unsigned char * byteIn, * byteOut;
+ r14 = (HWord_t)viargs;
+ // Just try the instruction an arbitrary number of times at different r15 offsets.
+ for (i = 0; i < 3; i++) {
+ int j, k;
+ reg_out = 0;
+ r15 = i * 4;
+ equality = 1;
+ __asm__ __volatile__ ("ldbrx %0, %1, %2" : "=r" (reg_out): "b" (r14),"r" (r15));
+ byteIn = ((unsigned char *)(r14 + r15));
+ byteOut = (unsigned char *)®_out;
+
+ printf("ldbrx:");
+ for (k = 0; k < 7; k++) {
+ printf( " %02x", (byteIn[k]));
+ }
+ printf(" (reverse) =>");
+ for (j = 0; j < 8; j++) {
+ printf( " %02x", (byteOut[j]));
+ }
+ printf("\n");
+ for (j = 0, k = 7; j < 8; j++, k--) {
+ equality &= (byteIn[k] == byteOut[j]);
+ }
+ if (!equality) {
+ printf("FAILED: load with byte reversal is incorrect\n");
+ errors++;
+ }
+ }
+ printf( "\n" );
+}
+
+static void
+test_popcntd(void)
+{
+ uint64_t res;
+ unsigned long long src = 0x9182736405504536ULL;
+ int i, answer = 0;
+ r14 = src;
+ __asm__ __volatile__ ("popcntd %0, %1" : "=r" (res): "r" (r14));
+ for (i = 0; i < 64; i++) {
+ answer += (r14 & 1ULL);
+ r14 = r14 >> 1;
+ }
+ printf("popcntd: 0x%llx => %d\n", src, (int)res);
+ if (res!= answer) {
+ printf("Error: unexpected result from popcntd\n");
+ errors++;
+ }
+ printf( "\n" );
+}
+#endif
+
+static void
+test_lfiwzx(void)
+{
+ unsigned int i;
+ unsigned int * src;
+ uint64_t reg_out;
+ r14 = (HWord_t)viargs;
+ // Just try the instruction an arbitrary number of times at different r15 offsets.
+ for (i = 0; i < 3; i++) {
+ reg_out = 0;
+ r15 = i * 4;
+ __asm__ __volatile__ ("lfiwzx %0, %1, %2" : "=d" (reg_out): "b" (r14),"r" (r15));
+ src = ((unsigned int *)(r14 + r15));
+ printf("lfiwzx: %u => %llu.00\n", *src, (unsigned long long)reg_out);
+
+ if (reg_out > 0xFFFFFFFFULL || *src != (unsigned int)reg_out) {
+ printf("FAILED: integer load to FP register is incorrect\n");
+ errors++;
+ }
+ }
+ printf( "\n" );
+}
+
+static void test_vx_fp_ops(void)
+{
+
+ test_func_t func;
+ int k;
+ char * test_name = (char *)malloc(20);
+ k = 0;
+
+ build_special_fargs_table();
+ while ((func = vx_fp_tests[k].test_func)) {
+ int i, condreg, repeat = 0;
+ unsigned int flags;
+ unsigned long long * frap, * frbp, * dst;
+ vx_fp_test_t test_group = vx_fp_tests[k];
+ vx_fp_test_type test_type = test_group.test_type;
+
+ switch (test_type) {
+ case VX_FP_CMP:
+ strcpy(test_name, "xscmp");
+ if (!repeat) {
+ repeat = 1;
+ strcat(test_name, "udp");
+ do_cmpudp = 1;
+ }
+ break;
+ case VX_FP_SMA:
+ case VX_FP_SMS:
+ case VX_FP_SNMA:
+ if (test_type == VX_FP_SMA)
+ strcpy(test_name, "xsmadd");
+ else if (test_type == VX_FP_SMS)
+ strcpy(test_name, "xsmsub");
+ else
+ strcpy(test_name, "xsnmadd");
+ if (!repeat) {
+ repeat = 1;
+ strcat(test_name, "adp");
+ do_adp = 1;
+ }
+ break;
+ case VX_FP_OTHER:
+ strcpy(test_name, test_group.name);
+ break;
+ default:
+ printf("ERROR: Invalid VX FP test type %d\n", test_type);
+ exit(1);
+ }
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * inA, * inB, * pv;
+
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (unsigned int *)&spec_fargs[aTest.fra_idx];
+ inB = (unsigned int *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+ memcpy(&vec_inA, inA, 8);
+ memcpy(&vec_inB, inB, 8);
+
+ switch (test_type) {
+ case VX_FP_CMP:
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ condreg = (flags & 0x0f000000) >> 24;
+ printf("#%d: %s %016llx <=> %016llx ? %x (CRx)\n", i, test_name, *frap, *frbp, condreg);
+ // printf("\tFRA: %e; FRB: %e\n", spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx]);
+ if ( condreg != aTest.cr_flags) {
+ printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, condreg);
+ errors++;
+ }
+ break;
+ case VX_FP_SMA:
+ case VX_FP_SMS:
+ case VX_FP_SNMA:
+ case VX_FP_OTHER:
+ {
+ int idx;
+ unsigned long long vsr_XT;
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (test_type != VX_FP_OTHER) {
+ /* Then we need a third src argument, which is stored in element 0 of
+ * VSX[XT] -- i.e., vec_out. For the xs<ZZZ>mdp cases, VSX[XT] holds
+ * src3 and VSX[XB] holds src2; for the xs<ZZZ>adp cases, VSX[XT] holds
+ * src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test
+ * data (input args, result) contain only two inputs, so I arbitrarily
+ * use spec_fargs elements 4 and 14 (alternating) for the third source
+ * argument. We can use the same input data for a given pair of
+ * adp/mdp-type instructions by swapping the src2 and src3 arguments; thus
+ * the expected result should be the same.
+ */
+ int extra_arg_idx;
+ if (i % 2)
+ extra_arg_idx = 4;
+ else
+ extra_arg_idx = 14;
+
+ //memcpy(&vec_out, &spec_fargs[14], 8);
+
+ if (repeat) {
+ /* We're on the first time through of one of the VX_FP_SMx
+ * test types, meaning we're testing a xs<ZZZ>adp case, thus we
+ * have to swap inputs as described above:
+ * src2 <= VSX[XT]
+ * src3 <= VSX[XB]
+ */
+ memcpy(&vec_out, inB, 8); // src2
+ memcpy(&vec_inB, &spec_fargs[extra_arg_idx], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[extra_arg_idx];
+ } else {
+ // Don't need to init src2, as it's done before the switch()
+ memcpy(&vec_out, &spec_fargs[extra_arg_idx], 8); //src3
+ }
+ memcpy(&vsr_XT, &vec_out, 8);
+ }
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (test_type == VX_FP_OTHER)
+ printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name, *frap, *frbp, *dst);
+ else
+ printf( "#%d: %s %016llx %016llx %016llx = %016llx\n", i,
+ test_name, vsr_XT, *frap, *frbp, *dst );
+
+ if ( *dst != aTest.dp_bin_result) {
+ printf("Error: Expected result %016llx; actual result %016llx\n", aTest.dp_bin_result, *dst);
+ errors++;
+ }
+ /*
+ {
+ // Debug code. Keep this block commented out except when debugging.
+ double result, expected;
+ memcpy(&result, dst, 8);
+ memcpy(&expected, &aTest.dp_bin_result, 8);
+ printf( "\tFRA + FRB: %e + %e: Expected = %e; Actual = %e\n",
+ spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx],
+ expected, result );
+ }
+ */
+ break;
+ }
+ }
+
+
+ }
+ printf( "\n" );
+
+ if (repeat) {
+ repeat = 0;
+ switch (test_type) {
+ case VX_FP_CMP:
+ strcpy(test_name, "xscmp");
+ strcat(test_name, "odp");
+ do_cmpudp = 0;
+ break;
+ case VX_FP_SMA:
+ case VX_FP_SMS:
+ case VX_FP_SNMA:
+ if (test_type == VX_FP_SMA)
+ strcpy(test_name, "xsmadd");
+ else if (test_type == VX_FP_SMS)
+ strcpy(test_name, "xsmsub");
+ else
+ strcpy(test_name, "xsnmadd");
+ strcat(test_name, "mdp");
+ do_adp = 0;
+ break;
+ case VX_FP_OTHER:
+ break;
+ }
+ goto again;
+ }
+ k++;
+ }
+ printf( "\n" );
+ free(test_name);
+}
+
+static void test_xs_conv_ops(void)
+{
+
+ test_func_t func;
+ int k = 0;
+
+ build_special_fargs_table();
+ while ((func = xs_conv_tests[k].test_func)) {
+ int i;
+ unsigned long long * frbp, * dst;
+ xs_conv_test_t test_group = xs_conv_tests[k];
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * inB, * pv;
+ int idx;
+ unsigned long long exp_result = test_group.results[i];
+ inB = (unsigned int *)&spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+ memcpy(&vec_inB, inB, 8);
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp, *dst);
+
+ if ( *dst != exp_result) {
+ printf("Error: Expected result %016llx; actual result %016llx\n", exp_result, *dst);
+ errors++;
+ }
+ }
+ k++;
+ printf("\n");
+ }
+ printf( "\n" );
+}
+
+static void do_load_test(ldst_test_t loadTest)
+{
+ test_func_t func;
+ unsigned int *src, *dst;
+ int splat = loadTest.type == VSX_LOAD_SPLAT ? 1: 0;
+ int i, j, m, equality;
+ i = j = 0;
+
+ func = loadTest.test_func;
+ for (i = 0, r14 = (HWord_t) loadTest.base_addr; i < NUM_VIARGS_VECS; i++) {
+ int again;
+ j = 0;
+ r14 += i * 16;
+ do {
+ unsigned int * pv = (unsigned int *)&vec_out;
+ int idx;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv+=idx)
+ *pv = 0;
+
+ again = 0;
+ r15 = j;
+
+ // execute test insn
+ (*func)();
+
+ src = (unsigned int*) (((unsigned char *)r14) + j);
+ dst = (unsigned int*) &vec_out;
+
+ printf( "%s:", loadTest.name);
+ for (m = 0; m < loadTest.num_words_to_process; m++) {
+ printf( " %08x", src[splat ? m % 2 : m]);
+ }
+ printf( " =>");
+ for (m = 0; m < loadTest.num_words_to_process; m++) {
+ printf( " %08x", dst[m]);
+ }
+ printf("\n");
+ equality = 1;
+ for (m = 0; m < loadTest.num_words_to_process; m++) {
+ equality = equality && (src[splat ? m % 2 : m] == dst[m]);
+ }
+
+ if (!equality) {
+ printf("FAILED: loaded vector is incorrect\n");
+ errors++;
+ }
+
+ if (j == 0 && loadTest.offset) {
+ again = 1;
+ j += loadTest.offset;
+ }
+ }
+ while (again);
+ }
+}
+
+static void
+do_store_test ( ldst_test_t storeTest )
+{
+ test_func_t func;
+ unsigned int *src, *dst;
+ int m, equality;
+
+ func = storeTest.test_func;
+ r14 = (HWord_t) storeTest.base_addr;
+ r15 = (HWord_t) storeTest.offset;
+ unsigned int * pv = (unsigned int *) storeTest.base_addr;
+ int idx;
+ // clear out storage destination
+ for (idx = 0; idx < 4; idx++, pv += idx)
+ *pv = 0;
+
+ memcpy(&vec_inA, &viargs[0], sizeof(vector unsigned char));
+
+ // execute test insn
+ (*func)();
+ src = &viargs[0];
+ dst = (unsigned int*) (((unsigned char *) r14) + storeTest.offset);
+
+ printf( "%s:", storeTest.name );
+ for (m = 0; m < storeTest.num_words_to_process; m++) {
+ printf( " %08x", src[m] );
+ }
+ printf( " =>" );
+ for (m = 0; m < storeTest.num_words_to_process; m++) {
+ printf( " %08x", dst[m] );
+ }
+ printf( "\n" );
+ equality = 1;
+ for (m = 0; m < storeTest.num_words_to_process; m++) {
+ equality = equality && (src[m] == dst[m]);
+ }
+
+ if (!equality) {
+ printf( "FAILED: vector store result is incorrect\n" );
+ errors++;
+ }
+
+}
+
+
+static void test_ldst(void)
+{
+ int k = 0;
+
+ while (ldst_tests[k].test_func) {
+ if (ldst_tests[k].type == VSX_STORE)
+ do_store_test(ldst_tests[k]);
+ else
+ do_load_test(ldst_tests[k]);
+ k++;
+ printf("\n");
+ }
+}
+
+static void test_ftdiv(void)
+{
+ int i, num_tests, crx;
+ unsigned int flags;
+ unsigned long long * frap, * frbp;
+ build_special_fargs_table();
+
+ num_tests = sizeof ftdiv_tests/sizeof ftdiv_tests[0];
+
+ for (i = 0; i < num_tests; i++) {
+ ftdiv_test_args_t aTest = ftdiv_tests[i];
+ f14 = spec_fargs[aTest.fra_idx];
+ f15 = spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("ftdiv cr1, %0, %1" : : "d" (f14), "d" (f15));
+ GET_CR(flags);
+ crx = (flags & 0x0f000000) >> 24;
+ printf( "ftdiv: %016llx <=> %016llx ? %x (CRx)\n", *frap, *frbp, crx);
+// printf("\tFRA: %e; FRB: %e\n", f14, f15);
+ if ( crx != aTest.cr_flags) {
+ printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, crx);
+ errors++;
+ }
+ }
+ printf( "\n" );
+}
+
+
+static void test_p7_fpops ( void )
+{
+ int k = 0;
+ test_func_t func;
+
+ build_fargs_table();
+ while ((func = fp_tests[k].test_func)) {
+ float res;
+ double resd;
+ unsigned long long u0;
+ int i;
+ int res32 = strcmp(fp_tests[k].name, "fcfidu");
+
+ for (i = 0; i < nb_fargs; i++) {
+ u0 = *(unsigned long long *) (&fargs[i]);
+ f14 = fargs[i];
+ (*func)();
+ if (res32) {
+ res = f17;
+ printf( "%s %016llx => (raw sp) %08x)",
+ fp_tests[k].name, u0, *((unsigned int *)&res));
+ } else {
+ resd = f17;
+ printf( "%s %016llx => (raw sp) %016llx)",
+ fp_tests[k].name, u0, *(unsigned long long *)(&resd));
+ }
+ printf( "\n" );
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_vsx_logic(void)
+{
+ logic_test_t aTest;
+ test_func_t func;
+ int equality, k;
+ k = 0;
+
+ while ((func = logic_tests[k].test_func)) {
+ unsigned int * pv;
+ int startA, startB;
+ unsigned int * inA, * inB, * dst;
+ int idx, i;
+ startA = 0;
+ aTest = logic_tests[k];
+ for (i = 0; i <= (NUM_VIARGS_INTS - (NUM_VIARGS_VECS * sizeof(int))); i++, startA++) {
+ startB = startA + 4;
+ pv = (unsigned int *)&vec_out;
+ inA = &viargs[startA];
+ inB = &viargs[startB];
+ memcpy(&vec_inA, inA, sizeof(vector unsigned char));
+ memcpy(&vec_inB, inB, sizeof(vector unsigned char));
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ (*func)();
+ dst = (unsigned int*) &vec_out;
+
+ printf( "%s:", aTest.name);
+ printf( " %08x %08x %08x %08x %s", inA[0], inA[1], inA[2], inA[3], aTest.name);
+ printf( " %08x %08x %08x %08x", inB[0], inB[1], inB[2], inB[3]);
+ printf(" => %08x %08x %08x %08x\n", dst[0], dst[1], dst[2], dst[3]);
+
+ equality = 1;
+ for (idx = 0; idx < 4; idx++) {
+ switch (aTest.op) {
+ case VSX_AND:
+ equality &= (dst[idx] == (inA[idx] & inB[idx]));
+ break;
+ case VSX_ANDC:
+ equality &= (dst[idx] == (inA[idx] & ~inB[idx]));
+ break;
+ case VSX_NOR:
+ equality &= (dst[idx] == ~(inA[idx] | inB[idx]));
+ break;
+ case VSX_XOR:
+ equality &= (dst[idx] == (inA[idx] ^ inB[idx]));
+ break;
+ case VSX_OR:
+ equality &= (dst[idx] == (inA[idx] | inB[idx]));
+ break;
+ default:
+ fprintf(stderr, "Error in test_vsx_logic(): unknown VSX logical op %d\n", aTest.op);
+ exit(1);
+ }
+ }
+ if (!equality) {
+ printf( "FAILED: vector out is incorrect\n" );
+ errors++;
+ }
+ }
+ k++;
+ }
+ printf( "\n" );
+}
+
+static void test_move_ops (void)
+{
+ move_test_t aTest;
+ test_func_t func;
+ int equality, k;
+ k = 0;
+
+ while ((func = move_tests[k].test_func)) {
+ unsigned int * pv;
+ int startA, startB;
+ unsigned int * inA, * inB, * dst;
+ unsigned long long exp_out;
+ int idx;
+ aTest = move_tests[k];
+ exp_out = aTest.expected_result;
+ startA = aTest.xa_idx;
+ startB = aTest.xb_idx;
+ pv = (unsigned int *)&vec_out;
+ inA = &viargs[startA];
+ inB = &viargs[startB];
+ memcpy(&vec_inA, inA, sizeof(vector unsigned char));
+ memcpy(&vec_inB, inB, sizeof(vector unsigned char));
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ (*func)();
+ dst = (unsigned int*) &vec_out;
+
+ printf( "%s:", aTest.name);
+ printf( " %08x %08x %s", inA[0], inA[1], aTest.name);
+ printf( " %08x %08xx", inB[0], inB[1]);
+ printf(" => %08x %08x\n", dst[0], dst[1]);
+
+ equality = 1;
+ pv = (unsigned int *)&exp_out;
+ for (idx = 0; idx < 2; idx++) {
+ equality &= (dst[idx] == pv[idx]);
+ }
+ if (!equality) {
+ printf( "FAILED: vector out is incorrect\n" );
+ errors++;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_permute_ops (void)
+{
+ permute_test_t *aTest;
+ unsigned int *dst = (unsigned int *) &vec_out;
+
+ for (aTest = &(permute_tests[0]); aTest->test_func != NULL; aTest++)
+ {
+ /* Grab test input and clear output vector. */
+ memcpy(&vec_inA, aTest->xa, sizeof(vec_inA));
+ memcpy(&vec_inB, aTest->xb, sizeof(vec_inB));
+ memset(dst, 0, sizeof(vec_out));
+
+ /* execute test insn */
+ aTest->test_func();
+
+ printf( "%s:\n", aTest->name);
+ printf( " XA[%08x,%08x,%08x,%08x]\n",
+ aTest->xa[0], aTest->xa[1], aTest->xa[2], aTest->xa[3]);
+ printf( " XB[%08x,%08x,%08x,%08x]\n",
+ aTest->xb[0], aTest->xb[1], aTest->xb[2], aTest->xb[3]);
+ printf( " => XT[%08x,%08x,%08x,%08x]\n",
+ dst[0], dst[1], dst[2], dst[3]);
+
+ if (memcmp (dst, &aTest->expected_output, sizeof(vec_out)))
+ {
+ printf( "FAILED: vector out is incorrect\n" );
+ errors++;
+ }
+ }
+ printf( "\n" );
+}
+
+static test_table_t all_tests[] = { { &test_ldst,
+ "Test VSX load/store instructions" },
+ { &test_vsx_logic,
+ "Test VSX logic instructions" },
+#ifdef __powerpc64__
+ { &test_ldbrx,
+ "Test ldbrx instruction" },
+ { &test_popcntd,
+ "Test popcntd instruction" },
+#endif
+ { &test_lfiwzx,
+ "Test lfiwzx instruction" },
+ { &test_p7_fpops,
+ "Test P7 floating point convert instructions"},
+ { &test_ftdiv,
+ "Test ftdiv instruction" },
+ { &test_move_ops,
+ "Test VSX move instructions"},
+ { &test_permute_ops,
+ "Test VSX permute instructions"},
+ { &test_vx_fp_ops,
+ "Test VSX floating point instructions"},
+ { &test_xs_conv_ops,
+ "Test VSX scalar integer conversion instructions" },
+ { NULL, NULL }
+};
+#endif // HAS_VSX
+
+int main(int argc, char *argv[])
+{
+#ifdef HAS_VSX
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+ if (errors)
+ printf("Testcase FAILED with %d errors \n", errors);
+ else
+ printf("Testcase PASSED\n");
+
+#endif // HAS _VSX
+
+ return 0;
+}
diff --git a/main/none/tests/ppc32/test_isa_2_06_part1.stderr.exp b/main/none/tests/ppc32/test_isa_2_06_part1.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part1.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc32/test_isa_2_06_part1.stdout.exp b/main/none/tests/ppc32/test_isa_2_06_part1.stdout.exp
new file mode 100644
index 0000000..80f8564
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part1.stdout.exp
@@ -0,0 +1,1023 @@
+Test VSX load/store instructions
+lxsdx: 01234567 89abcdef => 01234567 89abcdef
+lxsdx: 8899aabb 91929394 => 8899aabb 91929394
+
+lxsdx: 01234567 89abcdef => 01234567 89abcdef
+lxsdx: 89abcdef 00112233 => 89abcdef 00112233
+lxsdx: 8899aabb 91929394 => 8899aabb 91929394
+lxsdx: 91929394 a1a2a3a4 => 91929394 a1a2a3a4
+
+lxvd2x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 8899aabb 91929394 a1a2a3a4 b1b2b3b4
+
+lxvd2x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+lxvd2x: 89abcdef 00112233 44556677 8899aabb => 89abcdef 00112233 44556677 8899aabb
+lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 8899aabb 91929394 a1a2a3a4 b1b2b3b4
+lxvd2x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4
+
+lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef
+lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394
+
+lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef
+lxvdsx: 89abcdef 00112233 89abcdef 00112233 => 89abcdef 00112233 89abcdef 00112233
+lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394
+lxvdsx: 91929394 a1a2a3a4 91929394 a1a2a3a4 => 91929394 a1a2a3a4 91929394 a1a2a3a4
+
+lxvw4x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 8899aabb 91929394 a1a2a3a4 b1b2b3b4
+
+lxvw4x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+lxvw4x: 89abcdef 00112233 44556677 8899aabb => 89abcdef 00112233 44556677 8899aabb
+lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 8899aabb 91929394 a1a2a3a4 b1b2b3b4
+lxvw4x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4
+
+stxsdx: 01234567 89abcdef => 01234567 89abcdef
+
+stxsdx: 01234567 89abcdef => 01234567 89abcdef
+
+stxvd2x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+
+stxvd2x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+
+stxvw4x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+
+stxvw4x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+
+Test VSX logic instructions
+xxlxor: 01234567 89abcdef 00112233 44556677 xxlxor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89baefdc 18395e7b a1b38197 f5e7d5c3
+xxlxor: 89abcdef 00112233 44556677 8899aabb xxlxor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 18395e7b a1b38197 f5e7d5c3 495b697f
+xxlxor: 00112233 44556677 8899aabb 91929394 xxlxor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b38197 f5e7d5c3 495b697f 40404040
+xxlxor: 44556677 8899aabb 91929394 a1a2a3a4 xxlxor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5e7d5c3 495b697f 40404040 dbc9fe9a
+xxlor: 01234567 89abcdef 00112233 44556677 xxlor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89bbefff 99bbdfff a1b3a3b7 f5f7f7f7
+xxlor: 89abcdef 00112233 44556677 8899aabb xxlor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 99bbdfff a1b3a3b7 f5f7f7f7 c9dbebff
+xxlor: 00112233 44556677 8899aabb 91929394 xxlor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b3a3b7 f5f7f7f7 c9dbebff d1d2d3d4
+xxlor: 44556677 8899aabb 91929394 a1a2a3a4 xxlor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5f7f7f7 c9dbebff d1d2d3d4 fbebffbe
+xxlnor: 01234567 89abcdef 00112233 44556677 xxlnor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 76441000 66442000 5e4c5c48 0a080808
+xxlnor: 89abcdef 00112233 44556677 8899aabb xxlnor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 66442000 5e4c5c48 0a080808 36241400
+xxlnor: 00112233 44556677 8899aabb 91929394 xxlnor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 5e4c5c48 0a080808 36241400 2e2d2c2b
+xxlnor: 44556677 8899aabb 91929394 a1a2a3a4 xxlnor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 0a080808 36241400 2e2d2c2b 04140041
+xxland: 01234567 89abcdef 00112233 44556677 xxland 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 00010023 81828184 00002220 00102234
+xxland: 89abcdef 00112233 44556677 8899aabb xxland 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 81828184 00002220 00102234 80808280
+xxland: 00112233 44556677 8899aabb 91929394 xxland a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00002220 00102234 80808280 91929394
+xxland: 44556677 8899aabb 91929394 a1a2a3a4 xxland b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 00102234 80808280 91929394 20220124
+xxlandc: 01234567 89abcdef 00112233 44556677 xxlandc 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 01224544 08294c6b 00110013 44454443
+xxlandc: 89abcdef 00112233 44556677 8899aabb xxlandc 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 08294c6b 00110013 44454443 0819283b
+xxlandc: 00112233 44556677 8899aabb 91929394 xxlandc a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00110013 44454443 0819283b 00000000
+xxlandc: 44556677 8899aabb 91929394 a1a2a3a4 xxlandc b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 44454443 0819283b 00000000 8180a280
+
+Test lfiwzx instruction
+lfiwzx: 19088743 => 19088743.00
+lfiwzx: 2309737967 => 2309737967.00
+lfiwzx: 1122867 => 1122867.00
+
+Test P7 floating point convert instructions
+fcfids 0010000000000001 => (raw sp) 59800000)
+fcfids 00100094e0000359 => (raw sp) 598004a7)
+fcfids 3fe0000000000001 => (raw sp) 5e7f8000)
+fcfids 3fe00094e0000359 => (raw sp) 5e7f8002)
+fcfids 8010000000000001 => (raw sp) deffe000)
+fcfids 80100094e0000359 => (raw sp) deffdfff)
+fcfids bfe0000000000001 => (raw sp) de804000)
+fcfids bfe00094e0000359 => (raw sp) de803fff)
+fcfids 0020000000000b01 => (raw sp) 5a000000)
+fcfids 00000000203f0b3d => (raw sp) 4e00fc2d)
+fcfids 00000000005a203d => (raw sp) 4ab4407a)
+fcfids 8020000000000b01 => (raw sp) deffc000)
+fcfids 80000000203f0b3d => (raw sp) df000000)
+
+fcfidus 0010000000000001 => (raw sp) 59800000)
+fcfidus 00100094e0000359 => (raw sp) 598004a7)
+fcfidus 3fe0000000000001 => (raw sp) 5e7f8000)
+fcfidus 3fe00094e0000359 => (raw sp) 5e7f8002)
+fcfidus 8010000000000001 => (raw sp) 5f001000)
+fcfidus 80100094e0000359 => (raw sp) 5f001001)
+fcfidus bfe0000000000001 => (raw sp) 5f3fe000)
+fcfidus bfe00094e0000359 => (raw sp) 5f3fe001)
+fcfidus 0020000000000b01 => (raw sp) 5a000000)
+fcfidus 00000000203f0b3d => (raw sp) 4e00fc2d)
+fcfidus 00000000005a203d => (raw sp) 4ab4407a)
+fcfidus 8020000000000b01 => (raw sp) 5f002000)
+fcfidus 80000000203f0b3d => (raw sp) 5f000000)
+
+fcfidu 0010000000000001 => (raw sp) 4330000000000001)
+fcfidu 00100094e0000359 => (raw sp) 43300094e0000359)
+fcfidu 3fe0000000000001 => (raw sp) 43cff00000000000)
+fcfidu 3fe00094e0000359 => (raw sp) 43cff0004a700002)
+fcfidu 8010000000000001 => (raw sp) 43e0020000000000)
+fcfidu 80100094e0000359 => (raw sp) 43e00200129c0000)
+fcfidu bfe0000000000001 => (raw sp) 43e7fc0000000000)
+fcfidu bfe00094e0000359 => (raw sp) 43e7fc00129c0000)
+fcfidu 0020000000000b01 => (raw sp) 4340000000000580)
+fcfidu 00000000203f0b3d => (raw sp) 41c01f859e800000)
+fcfidu 00000000005a203d => (raw sp) 4156880f40000000)
+fcfidu 8020000000000b01 => (raw sp) 43e0040000000001)
+fcfidu 80000000203f0b3d => (raw sp) 43e00000000407e1)
+
+Test ftdiv instruction
+ftdiv: 3fd8000000000000 <=> 404f000000000000 ? 8 (CRx)
+ftdiv: 7ff7ffffffffffff <=> 404f000000000000 ? a (CRx)
+ftdiv: 404f000000000000 <=> fff8000000000000 ? a (CRx)
+ftdiv: 3fd8000000000000 <=> 0018000000b77501 ? a (CRx)
+ftdiv: 404f000000000000 <=> 7fe800000000051b ? a (CRx)
+ftdiv: 7fe800000000051b <=> 3fd8000000000000 ? a (CRx)
+ftdiv: 3fd8000000000000 <=> 7fe800000000051b ? a (CRx)
+ftdiv: 0123214569900000 <=> 3fd8000000000000 ? a (CRx)
+ftdiv: 7ff0000000000000 <=> 404f000000000000 ? e (CRx)
+ftdiv: fff0000000000000 <=> 404f000000000000 ? e (CRx)
+ftdiv: 404f000000000000 <=> 7ff0000000000000 ? e (CRx)
+ftdiv: 3fd8000000000000 <=> 8008340000078000 ? e (CRx)
+ftdiv: 0000000000000000 <=> 0000000000000000 ? e (CRx)
+ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
+
+Test VSX move instructions
+xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394
+
+xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef
+
+xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb
+
+xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4
+
+Test VSX permute instructions
+xxmrghw:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[11111111,55555555,22222222,66666666]
+xxmrghw:
+ XA[00112233,44556677,8899aabb,ccddeeff]
+ XB[11111111,22222222,33333333,44444444]
+ => XT[00112233,11111111,44556677,22222222]
+xxmrglw:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[33333333,77777777,44444444,88888888]
+xxmrglw:
+ XA[00112233,44556677,8899aabb,ccddeeff]
+ XB[11111111,22222222,33333333,44444444]
+ => XT[8899aabb,33333333,ccddeeff,44444444]
+xxpermdi DM=00:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[11111111,22222222,55555555,66666666]
+xxpermdi DM=01:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[11111111,22222222,77777777,88888888]
+xxpermdi DM=10:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[33333333,44444444,55555555,66666666]
+xxpermdi DM=11:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[33333333,44444444,77777777,88888888]
+xxsldwi SHW=0:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[11111111,22222222,33333333,44444444]
+xxsldwi SHW=1:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[22222222,33333333,44444444,55555555]
+xxsldwi SHW=2:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[33333333,44444444,55555555,66666666]
+xxsldwi SHW=3:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[44444444,55555555,66666666,77777777]
+
+Test VSX floating point instructions
+#0: xscmpudp fff0000000000000 <=> fff0000000000000 ? 2 (CRx)
+#1: xscmpudp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx)
+#2: xscmpudp fff0000000000000 <=> 8000000000000000 ? 8 (CRx)
+#3: xscmpudp fff0000000000000 <=> 0000000000000000 ? 8 (CRx)
+#4: xscmpudp fff0000000000000 <=> 0123214569900000 ? 8 (CRx)
+#5: xscmpudp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#6: xscmpudp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#7: xscmpudp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#8: xscmpudp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx)
+#9: xscmpudp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx)
+#10: xscmpudp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx)
+#11: xscmpudp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx)
+#12: xscmpudp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx)
+#13: xscmpudp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx)
+#14: xscmpudp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx)
+#15: xscmpudp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx)
+#16: xscmpudp 8000000000000000 <=> fff0000000000000 ? 4 (CRx)
+#17: xscmpudp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#18: xscmpudp 8000000000000000 <=> 8000000000000000 ? 2 (CRx)
+#19: xscmpudp 8000000000000000 <=> 0000000000000000 ? 2 (CRx)
+#20: xscmpudp 8000000000000000 <=> 0123214569900000 ? 8 (CRx)
+#21: xscmpudp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#22: xscmpudp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#23: xscmpudp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#24: xscmpudp 0000000000000000 <=> fff0000000000000 ? 4 (CRx)
+#25: xscmpudp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#26: xscmpudp 0000000000000000 <=> 8000000000000000 ? 2 (CRx)
+#27: xscmpudp 0000000000000000 <=> 0000000000000000 ? 2 (CRx)
+#28: xscmpudp 0000000000000000 <=> 0123214569900000 ? 8 (CRx)
+#29: xscmpudp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#30: xscmpudp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#31: xscmpudp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#32: xscmpudp 0123214569900000 <=> fff0000000000000 ? 4 (CRx)
+#33: xscmpudp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#34: xscmpudp 0123214569900000 <=> 8000000000000000 ? 4 (CRx)
+#35: xscmpudp 0123214569900000 <=> 0000000000000000 ? 4 (CRx)
+#36: xscmpudp 0123214569900000 <=> 404f000000000000 ? 8 (CRx)
+#37: xscmpudp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx)
+#38: xscmpudp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#39: xscmpudp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx)
+#40: xscmpudp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx)
+#41: xscmpudp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#42: xscmpudp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx)
+#43: xscmpudp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx)
+#44: xscmpudp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx)
+#45: xscmpudp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx)
+#46: xscmpudp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#47: xscmpudp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#48: xscmpudp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx)
+#49: xscmpudp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx)
+#50: xscmpudp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx)
+#51: xscmpudp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx)
+#52: xscmpudp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx)
+#53: xscmpudp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx)
+#54: xscmpudp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx)
+#55: xscmpudp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx)
+#56: xscmpudp fff8000000000000 <=> fff0000000000000 ? 1 (CRx)
+#57: xscmpudp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx)
+#58: xscmpudp fff8000000000000 <=> 8000000000000000 ? 1 (CRx)
+#59: xscmpudp fff8000000000000 <=> 0000000000000000 ? 1 (CRx)
+#60: xscmpudp fff8000000000000 <=> 0123214569900000 ? 1 (CRx)
+#61: xscmpudp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx)
+#62: xscmpudp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#63: xscmpudp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+
+#0: xscmpodp fff0000000000000 <=> fff0000000000000 ? 2 (CRx)
+#1: xscmpodp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx)
+#2: xscmpodp fff0000000000000 <=> 8000000000000000 ? 8 (CRx)
+#3: xscmpodp fff0000000000000 <=> 0000000000000000 ? 8 (CRx)
+#4: xscmpodp fff0000000000000 <=> 0123214569900000 ? 8 (CRx)
+#5: xscmpodp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#6: xscmpodp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#7: xscmpodp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#8: xscmpodp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx)
+#9: xscmpodp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx)
+#10: xscmpodp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx)
+#11: xscmpodp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx)
+#12: xscmpodp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx)
+#13: xscmpodp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx)
+#14: xscmpodp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx)
+#15: xscmpodp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx)
+#16: xscmpodp 8000000000000000 <=> fff0000000000000 ? 4 (CRx)
+#17: xscmpodp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#18: xscmpodp 8000000000000000 <=> 8000000000000000 ? 2 (CRx)
+#19: xscmpodp 8000000000000000 <=> 0000000000000000 ? 2 (CRx)
+#20: xscmpodp 8000000000000000 <=> 0123214569900000 ? 8 (CRx)
+#21: xscmpodp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#22: xscmpodp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#23: xscmpodp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#24: xscmpodp 0000000000000000 <=> fff0000000000000 ? 4 (CRx)
+#25: xscmpodp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#26: xscmpodp 0000000000000000 <=> 8000000000000000 ? 2 (CRx)
+#27: xscmpodp 0000000000000000 <=> 0000000000000000 ? 2 (CRx)
+#28: xscmpodp 0000000000000000 <=> 0123214569900000 ? 8 (CRx)
+#29: xscmpodp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#30: xscmpodp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#31: xscmpodp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#32: xscmpodp 0123214569900000 <=> fff0000000000000 ? 4 (CRx)
+#33: xscmpodp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#34: xscmpodp 0123214569900000 <=> 8000000000000000 ? 4 (CRx)
+#35: xscmpodp 0123214569900000 <=> 0000000000000000 ? 4 (CRx)
+#36: xscmpodp 0123214569900000 <=> 404f000000000000 ? 8 (CRx)
+#37: xscmpodp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx)
+#38: xscmpodp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#39: xscmpodp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx)
+#40: xscmpodp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx)
+#41: xscmpodp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#42: xscmpodp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx)
+#43: xscmpodp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx)
+#44: xscmpodp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx)
+#45: xscmpodp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx)
+#46: xscmpodp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#47: xscmpodp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#48: xscmpodp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx)
+#49: xscmpodp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx)
+#50: xscmpodp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx)
+#51: xscmpodp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx)
+#52: xscmpodp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx)
+#53: xscmpodp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx)
+#54: xscmpodp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx)
+#55: xscmpodp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx)
+#56: xscmpodp fff8000000000000 <=> fff0000000000000 ? 1 (CRx)
+#57: xscmpodp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx)
+#58: xscmpodp fff8000000000000 <=> 8000000000000000 ? 1 (CRx)
+#59: xscmpodp fff8000000000000 <=> 0000000000000000 ? 1 (CRx)
+#60: xscmpodp fff8000000000000 <=> 0123214569900000 ? 1 (CRx)
+#61: xscmpodp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx)
+#62: xscmpodp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#63: xscmpodp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+
+#0: xsadddp fff0000000000000 fff0000000000000 = fff0000000000000
+#1: xsadddp fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#2: xsadddp fff0000000000000 8000000000000000 = fff0000000000000
+#3: xsadddp fff0000000000000 0000000000000000 = fff0000000000000
+#4: xsadddp fff0000000000000 0123214569900000 = fff0000000000000
+#5: xsadddp fff0000000000000 7ff0000000000000 = 7ff8000000000000
+#6: xsadddp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsadddp fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsadddp c0d0650f5a07b353 fff0000000000000 = fff0000000000000
+#9: xsadddp c0d0650f5a07b353 c0d0650f5a07b353 = c0e0650f5a07b353
+#10: xsadddp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353
+#11: xsadddp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353
+#12: xsadddp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
+#13: xsadddp c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000
+#14: xsadddp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsadddp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsadddp 8000000000000000 fff0000000000000 = fff0000000000000
+#17: xsadddp 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
+#18: xsadddp 8000000000000000 8000000000000000 = 8000000000000000
+#19: xsadddp 8000000000000000 0000000000000000 = 0000000000000000
+#20: xsadddp 8000000000000000 0123214569900000 = 0123214569900000
+#21: xsadddp 8000000000000000 7ff0000000000000 = 7ff0000000000000
+#22: xsadddp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsadddp 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsadddp 0000000000000000 fff0000000000000 = fff0000000000000
+#25: xsadddp 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
+#26: xsadddp 0000000000000000 8000000000000000 = 0000000000000000
+#27: xsadddp 0000000000000000 0000000000000000 = 0000000000000000
+#28: xsadddp 0000000000000000 0123214569900000 = 0123214569900000
+#29: xsadddp 0000000000000000 7ff0000000000000 = 7ff0000000000000
+#30: xsadddp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsadddp 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsadddp 0123214569900000 fff0000000000000 = fff0000000000000
+#33: xsadddp 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353
+#34: xsadddp 0123214569900000 8000000000000000 = 0123214569900000
+#35: xsadddp 0123214569900000 0000000000000000 = 0123214569900000
+#36: xsadddp 0123214569900000 404f000000000000 = 404f000000000000
+#37: xsadddp 0123214569900000 7ff0000000000000 = 7ff0000000000000
+#38: xsadddp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsadddp 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsadddp 7ff0000000000000 fff0000000000000 = 7ff8000000000000
+#41: xsadddp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#42: xsadddp 7ff0000000000000 8000000000000000 = 7ff0000000000000
+#43: xsadddp 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xsadddp 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xsadddp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
+#46: xsadddp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsadddp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsadddp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsadddp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsadddp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsadddp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsadddp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsadddp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsadddp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsadddp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsadddp fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsadddp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsadddp fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsadddp fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsadddp fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsadddp fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsadddp fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsadddp fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsdivdp fff0000000000000 fff0000000000000 = 7ff8000000000000
+#1: xsdivdp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#2: xsdivdp fff0000000000000 8000000000000000 = 7ff0000000000000
+#3: xsdivdp fff0000000000000 0000000000000000 = fff0000000000000
+#4: xsdivdp fff0000000000000 0123214569900000 = fff0000000000000
+#5: xsdivdp fff0000000000000 7ff0000000000000 = 7ff8000000000000
+#6: xsdivdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsdivdp fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsdivdp c0d0650f5a07b353 fff0000000000000 = 0000000000000000
+#9: xsdivdp c0d0650f5a07b353 c0d0650f5a07b353 = 3ff0000000000000
+#10: xsdivdp c0d0650f5a07b353 8000000000000000 = 7ff0000000000000
+#11: xsdivdp c0d0650f5a07b353 0000000000000000 = fff0000000000000
+#12: xsdivdp c0d0650f5a07b353 0123214569900000 = ff9b6cb57ca13c00
+#13: xsdivdp c0d0650f5a07b353 7ff0000000000000 = 8000000000000000
+#14: xsdivdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsdivdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsdivdp 8000000000000000 fff0000000000000 = 0000000000000000
+#17: xsdivdp 8000000000000000 c0d0650f5a07b353 = 0000000000000000
+#18: xsdivdp 8000000000000000 8000000000000000 = 7ff8000000000000
+#19: xsdivdp 8000000000000000 0000000000000000 = 7ff8000000000000
+#20: xsdivdp 8000000000000000 0123214569900000 = 8000000000000000
+#21: xsdivdp 8000000000000000 7ff0000000000000 = 8000000000000000
+#22: xsdivdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsdivdp 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsdivdp 0000000000000000 fff0000000000000 = 8000000000000000
+#25: xsdivdp 0000000000000000 c0d0650f5a07b353 = 8000000000000000
+#26: xsdivdp 0000000000000000 8000000000000000 = 7ff8000000000000
+#27: xsdivdp 0000000000000000 0000000000000000 = 7ff8000000000000
+#28: xsdivdp 0000000000000000 0123214569900000 = 0000000000000000
+#29: xsdivdp 0000000000000000 7ff0000000000000 = 0000000000000000
+#30: xsdivdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsdivdp 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsdivdp 0123214569900000 fff0000000000000 = 8000000000000000
+#33: xsdivdp 0123214569900000 c0d0650f5a07b353 = 8042ab59d8b6ec87
+#34: xsdivdp 0123214569900000 8000000000000000 = fff0000000000000
+#35: xsdivdp 0123214569900000 0000000000000000 = 7ff0000000000000
+#36: xsdivdp 0123214569900000 404f000000000000 = 00c3bf3f64b5ad6b
+#37: xsdivdp 0123214569900000 7ff0000000000000 = 0000000000000000
+#38: xsdivdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsdivdp 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsdivdp 7ff0000000000000 fff0000000000000 = 7ff8000000000000
+#41: xsdivdp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#42: xsdivdp 7ff0000000000000 8000000000000000 = fff0000000000000
+#43: xsdivdp 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xsdivdp 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xsdivdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
+#46: xsdivdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsdivdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsdivdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsdivdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsdivdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsdivdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsdivdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsdivdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsdivdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsdivdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsdivdp fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsdivdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsdivdp fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsdivdp fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsdivdp fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsdivdp fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsdivdp fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsdivdp fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
+#1: xsmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
+#2: xsmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#3: xsmaddadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000
+#4: xsmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#5: xsmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#6: xsmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#7: xsmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#8: xsmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = fff0000000000000
+#9: xsmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
+#10: xsmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#11: xsmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
+#12: xsmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#13: xsmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = 7ff0000000000000
+#14: xsmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
+#15: xsmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
+#16: xsmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = fff0000000000000
+#17: xsmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = c0d0650f5a07b353
+#18: xsmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000
+#19: xsmaddadp 0000000000000000 8000000000000000 0123214569900000 = 0000000000000000
+#20: xsmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 0123214569900000
+#21: xsmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = 7ff0000000000000
+#22: xsmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#23: xsmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
+#24: xsmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = fff0000000000000
+#25: xsmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = c0d0650f5a07b353
+#26: xsmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 8000000000000000
+#27: xsmaddadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000
+#28: xsmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 0123214569900000
+#29: xsmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = 7ff0000000000000
+#30: xsmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#31: xsmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
+#32: xsmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = fff0000000000000
+#33: xsmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = c0d0650f5a07b353
+#34: xsmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
+#35: xsmaddadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000
+#36: xsmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = 404f000000000000
+#37: xsmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = 7ff0000000000000
+#38: xsmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
+#39: xsmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
+#40: xsmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#41: xsmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#42: xsmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#43: xsmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#44: xsmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#45: xsmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#46: xsmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#47: xsmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
+#48: xsmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#49: xsmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#50: xsmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#51: xsmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#52: xsmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#53: xsmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#54: xsmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#55: xsmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#56: xsmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#57: xsmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#58: xsmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#59: xsmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#60: xsmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#61: xsmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#62: xsmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#63: xsmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+
+#0: xsmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000
+#1: xsmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#2: xsmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000
+#3: xsmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000
+#4: xsmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
+#5: xsmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000
+#6: xsmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = fff0000000000000
+#9: xsmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c0d0650f5a07b353
+#10: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7
+#11: xsmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f
+#12: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7
+#13: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000
+#14: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = fff0000000000000
+#17: xsmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
+#18: xsmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000
+#19: xsmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 0000000000000000
+#20: xsmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 0123214569900000
+#21: xsmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = 7ff0000000000000
+#22: xsmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = fff0000000000000
+#25: xsmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
+#26: xsmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 8000000000000000
+#27: xsmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000
+#28: xsmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 0123214569900000
+#29: xsmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = 7ff0000000000000
+#30: xsmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = fff0000000000000
+#33: xsmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353
+#34: xsmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f
+#35: xsmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000
+#36: xsmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = 404f000000000000
+#37: xsmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = 7ff0000000000000
+#38: xsmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = fff0000000000000
+#41: xsmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#42: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000
+#43: xsmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
+#45: xsmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
+#46: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsmsubadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#1: xsmsubadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
+#2: xsmsubadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#3: xsmsubadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000
+#4: xsmsubadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#5: xsmsubadp 7ff0000000000000 fff0000000000000 0123214569900000 = fff0000000000000
+#6: xsmsubadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#7: xsmsubadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#8: xsmsubadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000
+#9: xsmsubadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353
+#10: xsmsubadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#11: xsmsubadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
+#12: xsmsubadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#13: xsmsubadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000
+#14: xsmsubadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
+#15: xsmsubadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
+#16: xsmsubadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#17: xsmsubadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353
+#18: xsmsubadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000
+#19: xsmsubadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000
+#20: xsmsubadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000
+#21: xsmsubadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000
+#22: xsmsubadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#23: xsmsubadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
+#24: xsmsubadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#25: xsmsubadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353
+#26: xsmsubadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000
+#27: xsmsubadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000
+#28: xsmsubadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000
+#29: xsmsubadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000
+#30: xsmsubadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#31: xsmsubadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
+#32: xsmsubadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000
+#33: xsmsubadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353
+#34: xsmsubadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
+#35: xsmsubadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000
+#36: xsmsubadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000
+#37: xsmsubadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000
+#38: xsmsubadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
+#39: xsmsubadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
+#40: xsmsubadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
+#41: xsmsubadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#42: xsmsubadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#43: xsmsubadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#44: xsmsubadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#45: xsmsubadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
+#46: xsmsubadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#47: xsmsubadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
+#48: xsmsubadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#49: xsmsubadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#50: xsmsubadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#51: xsmsubadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#52: xsmsubadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#53: xsmsubadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#54: xsmsubadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#55: xsmsubadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#56: xsmsubadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#57: xsmsubadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#58: xsmsubadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#59: xsmsubadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#60: xsmsubadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#61: xsmsubadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#62: xsmsubadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#63: xsmsubadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+
+#0: xsmsubmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff0000000000000
+#1: xsmsubmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#2: xsmsubmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000
+#3: xsmsubmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000
+#4: xsmsubmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
+#5: xsmsubmdp 0123214569900000 fff0000000000000 7ff0000000000000 = fff0000000000000
+#6: xsmsubmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsmsubmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
+#9: xsmsubmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353
+#10: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7
+#11: xsmsubmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f
+#12: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7
+#13: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
+#14: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsmsubmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000
+#17: xsmsubmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#18: xsmsubmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000
+#19: xsmsubmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000
+#20: xsmsubmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000
+#21: xsmsubmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000
+#22: xsmsubmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsmsubmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsmsubmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000
+#25: xsmsubmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#26: xsmsubmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000
+#27: xsmsubmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000
+#28: xsmsubmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000
+#29: xsmsubmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000
+#30: xsmsubmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsmsubmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsmsubmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000
+#33: xsmsubmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
+#34: xsmsubmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f
+#35: xsmsubmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000
+#36: xsmsubmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000
+#37: xsmsubmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000
+#38: xsmsubmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsmsubmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff8000000000000
+#41: xsmsubmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#42: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000
+#43: xsmsubmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
+#45: xsmsubmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
+#46: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsmsubmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsmsubmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsmsubmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsmsubmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsmsubmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsmsubmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsmsubmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsmsubmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsmsubmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsmsubmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsmsubmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsnmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
+#1: xsnmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
+#2: xsnmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#3: xsnmaddadp 0000000000000000 fff0000000000000 0123214569900000 = 7ff0000000000000
+#4: xsnmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#5: xsnmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#6: xsnmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#7: xsnmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#8: xsnmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000
+#9: xsnmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353
+#10: xsnmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7
+#11: xsnmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 02039a19ca8fcb5f
+#12: xsnmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7
+#13: xsnmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000
+#14: xsnmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
+#15: xsnmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
+#16: xsnmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#17: xsnmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353
+#18: xsnmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 8000000000000000
+#19: xsnmaddadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000
+#20: xsnmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000
+#21: xsnmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000
+#22: xsnmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#23: xsnmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
+#24: xsnmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#25: xsnmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353
+#26: xsnmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000
+#27: xsnmaddadp 0000000000000000 0000000000000000 0123214569900000 = 8000000000000000
+#28: xsnmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000
+#29: xsnmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000
+#30: xsnmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#31: xsnmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
+#32: xsnmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000
+#33: xsnmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353
+#34: xsnmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 02039a19ca8fcb5f
+#35: xsnmaddadp 0000000000000000 0123214569900000 0123214569900000 = 8000000000000000
+#36: xsnmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000
+#37: xsnmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000
+#38: xsnmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
+#39: xsnmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
+#40: xsnmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#41: xsnmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
+#42: xsnmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#43: xsnmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = fff0000000000000
+#44: xsnmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#45: xsnmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = fff0000000000000
+#46: xsnmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#47: xsnmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
+#48: xsnmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#49: xsnmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#50: xsnmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#51: xsnmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#52: xsnmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#53: xsnmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#54: xsnmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#55: xsnmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#56: xsnmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#57: xsnmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#58: xsnmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#59: xsnmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#60: xsnmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#61: xsnmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#62: xsnmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#63: xsnmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+
+#0: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000
+#1: xsnmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#2: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = fff0000000000000
+#3: xsnmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = 7ff0000000000000
+#4: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
+#5: xsnmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000
+#6: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsnmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
+#9: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353
+#10: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = c1b0cc9d05eec2a7
+#11: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 02039a19ca8fcb5f
+#12: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c1b0cc9d05eec2a7
+#13: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
+#14: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsnmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000
+#17: xsnmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#18: xsnmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 8000000000000000
+#19: xsnmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000
+#20: xsnmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000
+#21: xsnmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000
+#22: xsnmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsnmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsnmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000
+#25: xsnmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#26: xsnmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000
+#27: xsnmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 8000000000000000
+#28: xsnmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000
+#29: xsnmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000
+#30: xsnmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsnmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsnmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000
+#33: xsnmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
+#34: xsnmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 02039a19ca8fcb5f
+#35: xsnmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 8000000000000000
+#36: xsnmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000
+#37: xsnmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000
+#38: xsnmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsnmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff0000000000000
+#41: xsnmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#42: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = 7ff0000000000000
+#43: xsnmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = fff0000000000000
+#44: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = fff0000000000000
+#46: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsnmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsnmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsnmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsnmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsnmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsnmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsmuldp fff0000000000000 fff0000000000000 = 7ff0000000000000
+#1: xsmuldp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#2: xsmuldp fff0000000000000 8000000000000000 = 7ff8000000000000
+#3: xsmuldp fff0000000000000 0000000000000000 = 7ff8000000000000
+#4: xsmuldp fff0000000000000 0123214569900000 = fff0000000000000
+#5: xsmuldp fff0000000000000 7ff0000000000000 = fff0000000000000
+#6: xsmuldp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsmuldp fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsmuldp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
+#9: xsmuldp c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#10: xsmuldp c0d0650f5a07b353 8000000000000000 = 0000000000000000
+#11: xsmuldp c0d0650f5a07b353 0000000000000000 = 8000000000000000
+#12: xsmuldp c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
+#13: xsmuldp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
+#14: xsmuldp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsmuldp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsmuldp 8000000000000000 fff0000000000000 = 7ff8000000000000
+#17: xsmuldp 8000000000000000 c0d0650f5a07b353 = 0000000000000000
+#18: xsmuldp 8000000000000000 8000000000000000 = 0000000000000000
+#19: xsmuldp 8000000000000000 0000000000000000 = 8000000000000000
+#20: xsmuldp 8000000000000000 0123214569900000 = 8000000000000000
+#21: xsmuldp 8000000000000000 7ff0000000000000 = 7ff8000000000000
+#22: xsmuldp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsmuldp 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsmuldp 0000000000000000 fff0000000000000 = 7ff8000000000000
+#25: xsmuldp 0000000000000000 c0d0650f5a07b353 = 8000000000000000
+#26: xsmuldp 0000000000000000 8000000000000000 = 8000000000000000
+#27: xsmuldp 0000000000000000 0000000000000000 = 0000000000000000
+#28: xsmuldp 0000000000000000 0123214569900000 = 0000000000000000
+#29: xsmuldp 0000000000000000 7ff0000000000000 = 7ff8000000000000
+#30: xsmuldp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsmuldp 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsmuldp 0123214569900000 fff0000000000000 = fff0000000000000
+#33: xsmuldp 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
+#34: xsmuldp 0123214569900000 8000000000000000 = 8000000000000000
+#35: xsmuldp 0123214569900000 0000000000000000 = 0000000000000000
+#36: xsmuldp 0123214569900000 404f000000000000 = 0182883b3e438000
+#37: xsmuldp 0123214569900000 7ff0000000000000 = 7ff0000000000000
+#38: xsmuldp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsmuldp 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsmuldp 7ff0000000000000 fff0000000000000 = fff0000000000000
+#41: xsmuldp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#42: xsmuldp 7ff0000000000000 8000000000000000 = 7ff8000000000000
+#43: xsmuldp 7ff0000000000000 0000000000000000 = 7ff8000000000000
+#44: xsmuldp 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xsmuldp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
+#46: xsmuldp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsmuldp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsmuldp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsmuldp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsmuldp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsmuldp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsmuldp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsmuldp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsmuldp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsmuldp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsmuldp fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsmuldp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsmuldp fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsmuldp fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsmuldp fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsmuldp fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsmuldp fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsmuldp fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xssubdp fff0000000000000 fff0000000000000 = 7ff8000000000000
+#1: xssubdp fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#2: xssubdp fff0000000000000 8000000000000000 = fff0000000000000
+#3: xssubdp fff0000000000000 0000000000000000 = fff0000000000000
+#4: xssubdp fff0000000000000 0123214569900000 = fff0000000000000
+#5: xssubdp fff0000000000000 7ff0000000000000 = fff0000000000000
+#6: xssubdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xssubdp fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xssubdp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
+#9: xssubdp c0d0650f5a07b353 c0d0650f5a07b353 = 0000000000000000
+#10: xssubdp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353
+#11: xssubdp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353
+#12: xssubdp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
+#13: xssubdp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
+#14: xssubdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xssubdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xssubdp 8000000000000000 fff0000000000000 = 7ff0000000000000
+#17: xssubdp 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#18: xssubdp 8000000000000000 8000000000000000 = 0000000000000000
+#19: xssubdp 8000000000000000 0000000000000000 = 8000000000000000
+#20: xssubdp 8000000000000000 0123214569900000 = 8123214569900000
+#21: xssubdp 8000000000000000 7ff0000000000000 = fff0000000000000
+#22: xssubdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xssubdp 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xssubdp 0000000000000000 fff0000000000000 = 7ff0000000000000
+#25: xssubdp 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#26: xssubdp 0000000000000000 8000000000000000 = 0000000000000000
+#27: xssubdp 0000000000000000 0000000000000000 = 0000000000000000
+#28: xssubdp 0000000000000000 0123214569900000 = 8123214569900000
+#29: xssubdp 0000000000000000 7ff0000000000000 = fff0000000000000
+#30: xssubdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xssubdp 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xssubdp 0123214569900000 fff0000000000000 = 7ff0000000000000
+#33: xssubdp 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
+#34: xssubdp 0123214569900000 8000000000000000 = 0123214569900000
+#35: xssubdp 0123214569900000 0000000000000000 = 0123214569900000
+#36: xssubdp 0123214569900000 404f000000000000 = c04f000000000000
+#37: xssubdp 0123214569900000 7ff0000000000000 = fff0000000000000
+#38: xssubdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xssubdp 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xssubdp 7ff0000000000000 fff0000000000000 = 7ff0000000000000
+#41: xssubdp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#42: xssubdp 7ff0000000000000 8000000000000000 = 7ff0000000000000
+#43: xssubdp 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xssubdp 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xssubdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
+#46: xssubdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xssubdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xssubdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xssubdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xssubdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xssubdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xssubdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xssubdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xssubdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xssubdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xssubdp fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xssubdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xssubdp fff8000000000000 8000000000000000 = fff8000000000000
+#59: xssubdp fff8000000000000 0000000000000000 = fff8000000000000
+#60: xssubdp fff8000000000000 0123214569900000 = fff8000000000000
+#61: xssubdp fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xssubdp fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xssubdp fff8000000000000 7ff8000000000000 = fff8000000000000
+
+
+Test VSX scalar integer conversion instructions
+#0: xscvdpsxds 3fd8000000000000 => 0000000000000000
+#1: xscvdpsxds 404f000000000000 => 000000000000003e
+#2: xscvdpsxds 0018000000b77501 => 0000000000000000
+#3: xscvdpsxds 7fe800000000051b => 7fffffffffffffff
+#4: xscvdpsxds 0123214569900000 => 0000000000000000
+#5: xscvdpsxds 0000000000000000 => 0000000000000000
+#6: xscvdpsxds 8000000000000000 => 0000000000000000
+#7: xscvdpsxds 7ff0000000000000 => 7fffffffffffffff
+#8: xscvdpsxds fff0000000000000 => 8000000000000000
+#9: xscvdpsxds 7ff7ffffffffffff => 8000000000000000
+#10: xscvdpsxds fff7ffffffffffff => 8000000000000000
+#11: xscvdpsxds 7ff8000000000000 => 8000000000000000
+#12: xscvdpsxds fff8000000000000 => 8000000000000000
+#13: xscvdpsxds 8008340000078000 => 0000000000000000
+#14: xscvdpsxds c0d0650f5a07b353 => ffffffffffffbe6c
+
+#0: xscvsxddp 3fd8000000000000 => 43cfec0000000000
+#1: xscvsxddp 404f000000000000 => 43d013c000000000
+#2: xscvsxddp 0018000000b77501 => 4338000000b77501
+#3: xscvsxddp 7fe800000000051b => 43dffa0000000001
+#4: xscvsxddp 0123214569900000 => 4372321456990000
+#5: xscvsxddp 0000000000000000 => 0000000000000000
+#6: xscvsxddp 8000000000000000 => c3e0000000000000
+#7: xscvsxddp 7ff0000000000000 => 43dffc0000000000
+#8: xscvsxddp fff0000000000000 => c330000000000000
+#9: xscvsxddp 7ff7ffffffffffff => 43dffe0000000000
+#10: xscvsxddp fff7ffffffffffff => c320000000000002
+#11: xscvsxddp 7ff8000000000000 => 43dffe0000000000
+#12: xscvsxddp fff8000000000000 => c320000000000000
+#13: xscvsxddp 8008340000078000 => c3dffdf2fffffe20
+#14: xscvsxddp c0d0650f5a07b353 => c3cf97cd7852fc26
+
+#0: xscvuxddp 3fd8000000000000 => 43cfec0000000000
+#1: xscvuxddp 404f000000000000 => 43d013c000000000
+#2: xscvuxddp 0018000000b77501 => 4338000000b77501
+#3: xscvuxddp 7fe800000000051b => 43dffa0000000001
+#4: xscvuxddp 0123214569900000 => 4372321456990000
+#5: xscvuxddp 0000000000000000 => 0000000000000000
+#6: xscvuxddp 8000000000000000 => 43e0000000000000
+#7: xscvuxddp 7ff0000000000000 => 43dffc0000000000
+#8: xscvuxddp fff0000000000000 => 43effe0000000000
+#9: xscvuxddp 7ff7ffffffffffff => 43dffe0000000000
+#10: xscvuxddp fff7ffffffffffff => 43efff0000000000
+#11: xscvuxddp 7ff8000000000000 => 43dffe0000000000
+#12: xscvuxddp fff8000000000000 => 43efff0000000000
+#13: xscvuxddp 8008340000078000 => 43e00106800000f0
+#14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
+
+
+Testcase PASSED
diff --git a/main/none/tests/ppc32/test_isa_2_06_part1.vgtest b/main/none/tests/ppc32/test_isa_2_06_part1.vgtest
new file mode 100644
index 0000000..512a218
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part1.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_06_cap
+prog: test_isa_2_06_part1
diff --git a/main/none/tests/ppc32/test_isa_2_06_part2.c b/main/none/tests/ppc32/test_isa_2_06_part2.c
new file mode 100644
index 0000000..d9f2453
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part2.c
@@ -0,0 +1,1730 @@
+/* Copyright (C) 2011 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#ifdef HAS_VSX
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+#include <math.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int div_flags, div_xer;
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+typedef void (*test_func_t)(void);
+typedef struct test_table test_table_t;
+
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+} fp_test_args_t;
+
+
+fp_test_args_t fp_cmp_tests[] = {
+ {8, 8},
+ {8, 14},
+ {8, 6},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {10, 6},
+ {10, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 10},
+ {12, 8},
+ {12, 14},
+ {12, 6},
+ {12, 5},
+ {1, 1},
+ {2, 2},
+ {3, 3},
+ {4, 4},
+};
+
+
+fp_test_args_t two_arg_fp_tests[] = {
+ {8, 8},
+ {8, 14},
+ {15, 16},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {12, 6},
+ {12, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 11},
+ {12, 8 },
+ {12, 14},
+ {12, 6},
+ {15, 16},
+ {15, 16},
+ {9, 11},
+ {11, 11},
+ {11, 12}
+};
+
+
+static int nb_special_fargs;
+static double * spec_fargs;
+static float * spec_sp_fargs;
+
+static void build_special_fargs_table(void)
+{
+/*
+ Entry Sign Exp fraction Special value
+ 0 0 3fd 0x8000000000000ULL Positive finite number
+ 1 0 404 0xf000000000000ULL ...
+ 2 0 001 0x8000000b77501ULL ...
+ 3 0 7fe 0x800000000051bULL ...
+ 4 0 012 0x3214569900000ULL ...
+ 5 0 000 0x0000000000000ULL +0.0 (+zero)
+ 6 1 000 0x0000000000000ULL -0.0 (-zero)
+ 7 0 7ff 0x0000000000000ULL +infinity
+ 8 1 7ff 0x0000000000000ULL -infinity
+ 9 0 7ff 0x7FFFFFFFFFFFFULL +SNaN
+ 10 1 7ff 0x7FFFFFFFFFFFFULL -SNaN
+ 11 0 7ff 0x8000000000000ULL +QNaN
+ 12 1 7ff 0x8000000000000ULL -QNaN
+ 13 1 000 0x8340000078000ULL Denormalized val (zero exp and non-zero fraction)
+ 14 1 40d 0x0650f5a07b353ULL Negative finite number
+ 15 0 412 0x32585a9900000ULL A couple more positive finite numbers
+ 16 0 413 0x82511a2000000ULL ...
+*/
+
+ uint64_t mant;
+ uint16_t _exp;
+ int s;
+ int j, i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 17 * sizeof(double) );
+ spec_sp_fargs = malloc( 17 * sizeof(float) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* None of the ftdiv tests succeed.
+ * FRA = value #0; FRB = value #1
+ * ea_ = -2; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 100
+ */
+
+ /*************************************************
+ * fe_flag tests
+ *
+ *************************************************/
+
+ /* fe_flag <- 1 if FRA is a NaN
+ * FRA = value #9; FRB = value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRB is a NaN
+ * FRA = value #1; FRB = value #12
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if e_b <= -1022
+ * FRA = value #0; FRB = value #2
+ * e_a = -2; e_b = -1022
+ * fl_flag || fg_flag || fe_flag = 101
+ *
+ */
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if e_b >= 1021
+ * FRA = value #1; FRB = value #3
+ * e_a = 5; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b >= 1023
+ * Let FRA = value #3 and FRB be value #0.
+ * e_a = 1023; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b <= -1023
+ * Let FRA = value #0 above and FRB be value #3 above
+ * e_a = -2; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a <= -970
+ * Let FRA = value #4 and FRB be value #0
+ * e_a = -1005; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /*************************************************
+ * fg_flag tests
+ *
+ *************************************************/
+ /* fg_flag <- 1 if FRA is an Infinity
+ * NOTE: FRA = Inf also sets fe_flag
+ * Do two tests, using values #7 and #8 (+/- Inf) for FRA.
+ * Test 1:
+ * Let FRA be value #7 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ * Test 2:
+ * Let FRA be value #8 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ */
+
+ /* fg_flag <- 1 if FRB is an Infinity
+ * NOTE: FRB = Inf also sets fe_flag
+ * Let FRA be value #1 and FRB be value #7
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is denormalized
+ * NOTE: e_b < -1022 ==> fe_flag <- 1
+ * Let FRA be value #0 and FRB be value #13
+ * e_a = -2; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is +zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #5
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is -zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #6
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +SNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -SNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* A couple positive finite numbers ... */
+ // #15
+ s = 0;
+ _exp = 0x412;
+ mant = 0x32585a9900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #16
+ s = 0;
+ _exp = 0x413;
+ mant = 0x82511a2000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ nb_special_fargs = i;
+ for (j = 0; j < i; j++) {
+ spec_sp_fargs[j] = spec_fargs[j];
+ }
+}
+
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+typedef enum {
+ SINGLE_TEST,
+ DOUBLE_TEST
+} precision_type_t;
+
+typedef enum {
+ VX_SCALAR_FP_NMSUB = 0,
+ // ALL VECTOR-TYPE OPS SHOULD BE ADDED AFTER THIS LINE
+ VX_VECTOR_FP_MULT_AND_OP2 = 10,
+ // and before this line
+ VX_BASIC_CMP = 30,
+ VX_CONV_WORD,
+ VX_DEFAULT
+} vx_fp_test_type;
+
+typedef struct vx_fp_test
+{
+ test_func_t test_func;
+ const char * name;
+ fp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type type;
+ const char * op;
+} vx_fp_test_t;
+
+static vector unsigned int vec_out, vec_inA, vec_inB, vec_inC;
+
+static Bool do_dot;
+static void test_xvcmpeqdp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpeqdp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpeqdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgedp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgedp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgedp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgtdp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgtdp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgtdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpeqsp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpeqsp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpeqsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgesp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgesp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgesp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgtsp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgtsp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgtsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static Bool do_aXp;
+static Bool do_dp;
+static void test_xsnmsub(void)
+{
+ if (do_aXp)
+ __asm__ __volatile__ ("xsnmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsnmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmadd(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmaddasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmaddmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvnmadd(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmaddasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmaddmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvnmsub(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmsubasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmsubmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmsub(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmsubasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmsubmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xssqrtdp(void)
+{
+ __asm__ __volatile__ ("xssqrtdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpim(void)
+{
+ __asm__ __volatile__ ("xsrdpim %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpip(void)
+{
+ __asm__ __volatile__ ("xsrdpip %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xstdivdp(void)
+{
+ __asm__ __volatile__ ("xstdivdp 6, %x0, %x1" : : "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xsmaxdp(void)
+{
+ __asm__ __volatile__ ("xsmaxdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmindp(void)
+{
+ __asm__ __volatile__ ("xsmindp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvadddp(void)
+{
+ __asm__ __volatile__ ("xvadddp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvaddsp(void)
+{
+ __asm__ __volatile__ ("xvaddsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvdivdp(void)
+{
+ __asm__ __volatile__ ("xvdivdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvdivsp(void)
+{
+ __asm__ __volatile__ ("xvdivsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmuldp(void)
+{
+ __asm__ __volatile__ ("xvmuldp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmulsp(void)
+{
+ __asm__ __volatile__ ("xvmulsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvsubdp(void)
+{
+ __asm__ __volatile__ ("xvsubdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmaxdp(void)
+{
+ __asm__ __volatile__ ("xvmaxdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmindp(void)
+{
+ __asm__ __volatile__ ("xvmindp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmaxsp(void)
+{
+ __asm__ __volatile__ ("xvmaxsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvminsp(void)
+{
+ __asm__ __volatile__ ("xvminsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvsubsp(void)
+{
+ __asm__ __volatile__ ("xvsubsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvresp(void)
+{
+ __asm__ __volatile__ ("xvresp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xxsel(void)
+{
+ unsigned long long * dst;
+ unsigned long long xa[] = { 0xa12bc37de56f9708ULL, 0x3894c1fddeadbeefULL};
+ unsigned long long xb[] = { 0xfedc432124681235ULL, 0xf1e2d3c4e0057708ULL};
+ unsigned long long xc[] = { 0xffffffff01020304ULL, 0x128934bd00000000ULL};
+
+ memcpy(&vec_inA, xa, 16);
+ memcpy(&vec_inB, xb, 16);
+ memcpy(&vec_inC, xc, 16);
+
+
+ __asm__ __volatile__ ("xxsel %x0, %x1, %x2, %x3" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB),"wa" (vec_inC));
+ dst = (unsigned long long *) &vec_out;
+ printf("xxsel %016llx,%016llx,%016llx => %016llx\n", xa[0], xb[0], xc[0], *dst);
+ dst++;
+ printf("xxsel %016llx,%016llx,%016llx => %016llx\n", xa[1], xb[1], xc[1], *dst);
+ printf("\n");
+}
+
+static void test_xxspltw(void)
+{
+ int uim;
+ unsigned long long * dst = NULL;
+ unsigned long long xb[] = { 0xfedc432124681235ULL, 0xf1e2d3c4e0057708ULL};
+ memcpy(&vec_inB, xb, 16);
+
+ for (uim = 0; uim < 4; uim++) {
+ switch (uim) {
+ case 0:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 0" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ case 1:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 1" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ case 2:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 2" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ case 3:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 3" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ }
+ dst = (unsigned long long *) &vec_out;
+ printf("xxspltw 0x%016llx%016llx %d=> 0x%016llx", xb[0], xb[1], uim, *dst);
+ dst++;
+ printf("%016llx\n", *dst);
+ }
+ printf("\n");
+}
+
+static void test_xscvdpsxws(void)
+{
+ __asm__ __volatile__ ("xscvdpsxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvdpuxds(void)
+{
+ __asm__ __volatile__ ("xscvdpuxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcpsgndp(void)
+{
+ __asm__ __volatile__ ("xvcpsgndp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcpsgnsp(void)
+{
+ __asm__ __volatile__ ("xvcpsgnsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcvdpsxws(void)
+{
+ __asm__ __volatile__ ("xvcvdpsxws %x0, %x1 " : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspsxws(void)
+{
+ __asm__ __volatile__ ("xvcvspsxws %x0, %x1 " : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static vx_fp_test_t
+vx_vector_one_fp_arg_tests[] = {
+ { &test_xvresp, "xvresp", NULL, 16, SINGLE_TEST, VX_BASIC_CMP, "1/x"},
+ { &test_xvcvdpsxws, "xvcvdpsxws", NULL, 16, DOUBLE_TEST, VX_CONV_WORD, "conv"},
+ { &test_xvcvspsxws, "xvcvspsxws", NULL, 16, SINGLE_TEST, VX_CONV_WORD, "conv"},
+ { NULL, NULL, NULL, 0 , 0, 0, NULL}
+};
+
+static vx_fp_test_t
+vx_vector_fp_tests[] = {
+ { &test_xvcmpeqdp, "xvcmpeqdp", fp_cmp_tests, 64, DOUBLE_TEST, VX_BASIC_CMP, "eq"},
+ { &test_xvcmpgedp, "xvcmpgedp", fp_cmp_tests, 64, DOUBLE_TEST, VX_BASIC_CMP, "ge"},
+ { &test_xvcmpgtdp, "xvcmpgtdp", fp_cmp_tests, 64, DOUBLE_TEST, VX_BASIC_CMP, "gt"},
+ { &test_xvcmpeqsp, "xvcmpeqsp", fp_cmp_tests, 64, SINGLE_TEST, VX_BASIC_CMP, "eq"},
+ { &test_xvcmpgesp, "xvcmpgesp", fp_cmp_tests, 64, SINGLE_TEST, VX_BASIC_CMP, "ge"},
+ { &test_xvcmpgtsp, "xvcmpgtsp", fp_cmp_tests, 64, SINGLE_TEST, VX_BASIC_CMP, "gt"},
+ { &test_xvadddp, "xvadddp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "+" },
+ { &test_xvaddsp, "xvaddsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "+" },
+ { &test_xvdivdp, "xvdivdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "/" },
+ { &test_xvdivsp, "xvdivsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "/" },
+ { &test_xvmuldp, "xvmuldp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "*" },
+ { &test_xvmulsp, "xvmulsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "*" },
+ { &test_xvsubdp, "xvsubdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "-" },
+ { &test_xvsubsp, "xvsubsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "-" },
+ { &test_xvmaxdp, "xvmaxdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "@max@" },
+ { &test_xvmindp, "xvmindp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "@min@" },
+ { &test_xvmaxsp, "xvmaxsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "@max@" },
+ { &test_xvminsp, "xvminsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "@min@" },
+ { &test_xvcpsgndp, "xvcpsgndp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "+-cp"},
+ { &test_xvcpsgnsp, "xvcpsgnsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "+-cp"},
+ { NULL, NULL, NULL, 0 , 0, 0, NULL}
+};
+
+
+static vx_fp_test_t
+vx_aORm_fp_tests[] = {
+ { &test_xsnmsub, "xsnmsub", two_arg_fp_tests, 64, DOUBLE_TEST, VX_SCALAR_FP_NMSUB, "!*-"},
+ { &test_xvmadd, "xvmadd", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*+"},
+ { &test_xvmadd, "xvmadd", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*+"},
+ { &test_xvnmadd, "xvnmadd", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*+"},
+ { &test_xvnmadd, "xvnmadd", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*+"},
+ { &test_xvmsub, "xvmsub", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*-"},
+ { &test_xvmsub, "xvmsub", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*-"},
+ { &test_xvnmsub, "xvnmsub", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*-"},
+ { &test_xvnmsub, "xvnmsub", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*-"},
+ { NULL, NULL, NULL, 0, 0, 0, NULL }
+};
+
+static vx_fp_test_t
+vx_simple_scalar_fp_tests[] = {
+ { &test_xssqrtdp, "xssqrtdp", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsrdpim, "xsrdpim", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsrdpip, "xsrdpip", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xstdivdp, "xstdivdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsmaxdp, "xsmaxdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsmindp, "xsmindp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xscvdpsxws, "xscvdpsxws", NULL, 17, DOUBLE_TEST, VX_CONV_WORD, NULL},
+ { &test_xscvdpuxds, "xscvdpuxds", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { NULL, NULL, NULL, 0, 0, 0, NULL }
+};
+
+
+#ifdef __powerpc64__
+static void test_bpermd(void)
+{
+ /* NOTE: Bit number is '0 . . . 63'
+ *
+ * Permuted bits are generated bit 0 -7 as follows:
+ * index = (r14)8*i:8*i+7
+ * perm[i] = (r15)index
+ *
+ * So, for i = 0, index is (r14)8*0:8*0+7, or (r14)0:7, which is the MSB
+ * byte of r14, 0x1b(27/base 10). This identifies bit 27 of r15, which is '1'.
+ * For i = 1, index is 0x2c, identifying bit 44 of r15, which is '1'.
+ * So the result of the first two iterations of i are:
+ * perm = 0b01xxxxxx
+ *
+ */
+ r15 = 0xa12bc37de56f9708ULL;
+ r14 = 0x1b2c31f030000001ULL;
+ __asm__ __volatile__ ("bpermd %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ printf("bpermd: 0x%016llx : 0x%016llx => 0x%llx\n", (unsigned long long)r14,
+ (unsigned long long)r15, (unsigned long long)r17);
+ printf("\n");
+}
+#endif
+
+static Bool do_OE;
+typedef enum {
+ DIV_BASE = 1,
+ DIV_OE = 2,
+ DIV_DOT = 4,
+} div_type_t;
+/* Possible divde type combinations are:
+ * - base
+ * - base+dot
+ * - base+OE
+ * - base+OE+dot
+ */
+#ifdef __powerpc64__
+static void test_divde(void)
+{
+ int divde_type = DIV_BASE;
+ if (do_OE)
+ divde_type |= DIV_OE;
+ if (do_dot)
+ divde_type |= DIV_DOT;
+
+ switch (divde_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divde %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divde. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divde type. Exiting\n");
+ exit(1);
+ }
+}
+#endif
+
+static void test_divweu(void)
+{
+ int divweu_type = DIV_BASE;
+ if (do_OE)
+ divweu_type |= DIV_OE;
+ if (do_dot)
+ divweu_type |= DIV_DOT;
+
+ switch (divweu_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweu %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweuo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweu. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweuo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divweu type. Exiting\n");
+ exit(1);
+ }
+}
+
+static void test_fctiduz(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctiduz. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctiduz %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+static void test_fctidu(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctidu. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctidu %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+static void test_fctiwuz(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctiwuz. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctiwuz %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+static void test_fctiwu(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctiwu. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctiwu %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+typedef struct simple_test {
+ test_func_t test_func;
+ char * name;
+ precision_type_t precision;
+} simple_test_t;
+
+static simple_test_t fct_tests[] = {
+ { &test_fctiduz, "fctiduz", DOUBLE_TEST },
+ { &test_fctidu, "fctidu", DOUBLE_TEST },
+ { &test_fctiwuz, "fctiwuz", SINGLE_TEST },
+ { &test_fctiwu, "fctiwu", SINGLE_TEST },
+ { NULL, NULL }
+};
+
+static void setup_sp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? &vec_out : &vec_inB;
+
+ for (i = 0; i < 4; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_sp_fargs[a_idx];
+ inB = (void *)&spec_sp_fargs[b_idx];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 4), inA, 4);
+ memcpy(vec_src + (i * 4), inB, 4);
+ targs++;
+ }
+}
+
+static void setup_dp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? (void *)&vec_out : (void *)&vec_inB;
+
+ for (i = 0; i < 2; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_fargs[a_idx];
+ inB = (void *)&spec_fargs[b_idx];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 8), inA, 8);
+ memcpy(vec_src + (i * 8), inB, 8);
+ targs++;
+ }
+}
+
+#define VX_NOT_CMP_OP 0xffffffff
+static void print_vector_fp_result(unsigned int cc, vx_fp_test_t * test_group, int i)
+{
+ int a_idx, b_idx, k;
+ char * name = malloc(20);
+ int dp = test_group->precision == DOUBLE_TEST ? 1 : 0;
+ int loops = dp ? 2 : 4;
+ fp_test_args_t * targs = &test_group->targs[i];
+ unsigned long long * frA_dp, * frB_dp, * dst_dp;
+ unsigned int * frA_sp, *frB_sp, * dst_sp;
+ strcpy(name, test_group->name);
+ printf("#%d: %s%s ", dp? i/2 : i/4, name, (do_dot ? "." : ""));
+ for (k = 0; k < loops; k++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ if (k)
+ printf(" AND ");
+ if (dp) {
+ frA_dp = (unsigned long long *)&spec_fargs[a_idx];
+ frB_dp = (unsigned long long *)&spec_fargs[b_idx];
+ printf("%016llx %s %016llx", *frA_dp, test_group->op, *frB_dp);
+ } else {
+ frA_sp = (unsigned int *)&spec_sp_fargs[a_idx];
+ frB_sp = (unsigned int *)&spec_sp_fargs[b_idx];
+ printf("%08x %s %08x", *frA_sp, test_group->op, *frB_sp);
+ }
+ targs++;
+ }
+ if (cc != VX_NOT_CMP_OP)
+ printf(" ? cc=%x", cc);
+
+ if (dp) {
+ dst_dp = (unsigned long long *) &vec_out;
+ printf(" => %016llx %016llx\n", dst_dp[0], dst_dp[1]);
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ printf(" => %08x %08x %08x %08x\n", dst_sp[0], dst_sp[1], dst_sp[2], dst_sp[3]);
+ }
+ free(name);
+}
+
+
+static void print_vx_aORm_fp_result(unsigned long long * XT_arg, unsigned long long * XB_arg,
+ vx_fp_test_t * test_group, int i)
+{
+ int a_idx, k;
+ char * name = malloc(20);
+ int dp = test_group->precision == DOUBLE_TEST ? 1 : 0;
+ int loops = dp ? 2 : 4;
+ fp_test_args_t * targs = &test_group->targs[i];
+ unsigned long long frA_dp, * dst_dp;
+ unsigned int frA_sp, * dst_sp;
+
+ strcpy(name, test_group->name);
+ if (do_aXp)
+ if (dp)
+ strcat(name, "adp");
+ else
+ strcat(name, "asp");
+ else
+ if (dp)
+ strcat(name, "mdp");
+ else
+ strcat(name, "msp");
+
+ printf("#%d: %s ", dp? i/2 : i/4, name);
+ for (k = 0; k < loops; k++) {
+ a_idx = targs->fra_idx;
+ if (k)
+ printf(" AND ");
+ if (dp) {
+ frA_dp = *((unsigned long long *)&spec_fargs[a_idx]);
+ printf("%s(%016llx,%016llx,%016llx)", test_group->op, XT_arg[k], frA_dp, XB_arg[k]);
+ } else {
+ unsigned int * xt_sp = (unsigned int *)XT_arg;
+ unsigned int * xb_sp = (unsigned int *)XB_arg;
+ frA_sp = *((unsigned int *)&spec_sp_fargs[a_idx]);
+ printf("%s(%08x,%08x,%08x)", test_group->op, xt_sp[k], frA_sp, xb_sp[k]);
+ }
+ targs++;
+ }
+
+ if (dp) {
+ dst_dp = (unsigned long long *) &vec_out;
+ printf(" => %016llx %016llx\n", dst_dp[0], dst_dp[1]);
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ printf(" => %08x %08x %08x %08x\n", dst_sp[0], dst_sp[1], dst_sp[2], dst_sp[3]);
+ }
+ free(name);
+}
+
+/* This function currently only supports double precision input arguments. */
+static void test_vx_simple_scalar_fp_ops(void)
+{
+ test_func_t func;
+ int k = 0;
+
+ build_special_fargs_table();
+ while ((func = vx_simple_scalar_fp_tests[k].test_func)) {
+ unsigned long long * frap, * frbp, * dst;
+ unsigned int * pv;
+ int idx;
+ vx_fp_test_t test_group = vx_simple_scalar_fp_tests[k];
+ Bool convToWord = (test_group.type == VX_CONV_WORD);
+ if (test_group.precision != DOUBLE_TEST) {
+ fprintf(stderr, "Unsupported single precision for scalar op in test_vx_aORm_fp_ops\n");
+ exit(1);
+ }
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ /* If num_tests is exactly equal to nb_special_fargs, this implies the
+ * instruction being tested only requires one floating point argument
+ * (e.g. xssqrtdp).
+ */
+ if (test_group.num_tests == nb_special_fargs && !test_group.targs) {
+ void * inB;
+ int i;
+ for (i = 0; i < nb_special_fargs; i++) {
+ inB = (void *)&spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+ memcpy(&vec_inB, inB, 8);
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp,
+ convToWord ? (*dst & 0x00000000ffffffffULL) : *dst);
+ }
+ } else {
+ void * inA, * inB;
+ unsigned int condreg, flags;
+ int isTdiv = (strstr(test_group.name, "xstdivdp") != NULL) ? 1 : 0;
+ int i;
+ for (i = 0; i < test_group.num_tests; i++) {
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (void *)&spec_fargs[aTest.fra_idx];
+ inB = (void *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+ memcpy(&vec_inA, inA, 8);
+ memcpy(&vec_inB, inB, 8);
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ if (isTdiv) {
+ condreg = (flags & 0x000000f0) >> 4;
+ printf("#%d: %s %016llx,%016llx => cr %x\n", i, test_group.name, *frap, *frbp, condreg);
+ } else {
+ dst = (unsigned long long *) &vec_out;
+ printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
+ *frap, *frbp, *dst);
+ }
+ }
+ }
+ printf( "\n" );
+ k++;
+ }
+}
+
+static void test_vx_aORm_fp_ops(void)
+{
+ /* These ops need a third src argument, which is stored in element 0 of
+ * VSX[XT] -- i.e., vec_out. For the xs<ZZZ>m{d|s}p cases, VSX[XT] holds
+ * src3 and VSX[XB] holds src2; for the xs<ZZZ>a{d|s}p cases, VSX[XT] holds
+ * src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test
+ * data (input args, result) contain only two inputs, so I arbitrarily
+ * choose some spec_fargs elements for the third source argument.
+ * Note that that by using the same input data for a given pair of
+ * a{d|s}p/m{d|s}p-type instructions (by swapping the src2 and src3
+ * arguments), the expected result should be the same.
+ */
+
+ test_func_t func;
+ int k;
+ char * test_name = (char *)malloc(20);
+ k = 0;
+ do_dot = False;
+
+ build_special_fargs_table();
+ while ((func = vx_aORm_fp_tests[k].test_func)) {
+ int i, stride;
+ Bool repeat = False;
+ Bool scalar = False;
+ unsigned long long * frap, * frbp, * dst;
+ vx_fp_test_t test_group = vx_aORm_fp_tests[k];
+ vx_fp_test_type test_type = test_group.type;
+ do_dp = test_group.precision == DOUBLE_TEST ? True : False;
+ frap = frbp = NULL;
+
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2) {
+ scalar = True;
+ strcpy(test_name, test_group.name);
+ if (!repeat) {
+ repeat = 1;
+ stride = 1;
+ // Only support double precision scalar ops in this function
+ if (do_dp) {
+ strcat(test_name, "adp");
+ } else {
+ fprintf(stderr, "Unsupported single precision for scalar op in test_vx_aORm_fp_ops\n");
+ exit(1);
+ }
+ do_aXp = True;
+ }
+ } else if (test_type < VX_BASIC_CMP) {
+ // Then it must be a VX_VECTOR_xxx type
+ stride = do_dp ? 2 : 4;
+ if (!repeat) {
+ // No need to work up the testcase name here, since that will be done in
+ // the print_vx_aORm_fp_result() function we'll call for vector-type ops.
+ repeat = 1;
+ do_aXp = True;
+ }
+ } else {
+ printf("ERROR: Invalid VX FP test type %d\n", test_type);
+ exit(1);
+ }
+
+again:
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ void * inA, * inB;
+ int m, fp_idx[4];
+ unsigned long long vsr_XT[2];
+ unsigned long long vsr_XB[2];
+ fp_test_args_t aTest = test_group.targs[i];
+ for (m = 0; m < stride; m++)
+ fp_idx[m] = i % (nb_special_fargs - stride) + m;
+
+ /* When repeat == True, we're on the first time through of one of the VX_FP_SMx
+ * test types, meaning we're testing a xs<ZZZ>adp case, thus we have to swap
+ * inputs as described above:
+ * src2 <= VSX[XT]
+ * src3 <= VSX[XB]
+ */
+ if (scalar) {
+ // For scalar op, only need to copy one doubleword into each vector's element 0
+ inA = (void *)&spec_fargs[aTest.fra_idx];
+ inB = (void *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ memcpy(&vec_inA, inA, 8);
+ if (repeat) {
+ memcpy(&vec_out, inB, 8); // src2
+ memcpy(&vec_inB, &spec_fargs[fp_idx[0]], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[fp_idx[0]];
+ } else {
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ memcpy(&vec_inB, inB, 8); // src2
+ memcpy(&vec_out, &spec_fargs[fp_idx[0]], 8); //src3
+ }
+ memcpy(vsr_XT, &vec_out, 8);
+ } else {
+ int j, loops = do_dp ? 2 : 4;
+ size_t len = do_dp ? 8 : 4;
+ void * vec_src = repeat ? (void *)&vec_inB : (void *)&vec_out;
+ for (j = 0; j < loops; j++) {
+ if (do_dp)
+ memcpy(vec_src + (j * len), &spec_fargs[fp_idx[j]], len);
+ else
+ memcpy(vec_src + (j * len), &spec_sp_fargs[fp_idx[j]], len);
+ }
+ if (do_dp)
+ setup_dp_fp_args(&test_group.targs[i], repeat);
+ else
+ setup_sp_fp_args(&test_group.targs[i], repeat);
+
+ memcpy(vsr_XT, &vec_out, 16);
+ memcpy(vsr_XB, &vec_inB, 16);
+ }
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2)
+ printf( "#%d: %s %s(%016llx,%016llx,%016llx) = %016llx\n", i,
+ test_name, test_group.op, vsr_XT[0], *frap, *frbp, *dst );
+ else
+ print_vx_aORm_fp_result(vsr_XT, vsr_XB, &test_group, i);
+ }
+ printf( "\n" );
+
+ if (repeat) {
+ repeat = 0;
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2) {
+ strcpy(test_name, test_group.name);
+ strcat(test_name, "mdp");
+ }
+ do_aXp = False;
+ goto again;
+ }
+ k++;
+ }
+ printf( "\n" );
+ free(test_name);
+}
+
+static void test_vx_vector_one_fp_arg(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vx_vector_one_fp_arg_tests[k].test_func)) {
+ int idx, i;
+ vx_fp_test_t test_group = vx_vector_one_fp_arg_tests[k];
+ Bool convToWord = (test_group.type == VX_CONV_WORD);
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool xvrespTest = (strstr(test_group.name , "xvresp") != NULL) ? True: False;
+ int stride = dp ? 2 : 4;
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long * frB_dp, *dst_dp;
+ for (j = 0; j < 2; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
+ printf("#%d: %s ", i/2, test_group.name);
+ for (j = 0; j < 2; j++) {
+ if (j)
+ printf("; ");
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ printf(" = %016llx", convToWord ? (dst_dp[j] & 0x00000000ffffffffULL) : dst_dp[j]);
+ }
+ printf("\n");
+ } else {
+ int j;
+ unsigned int * frB_sp, * dst_sp;
+
+ for (j = 0; j < 4; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ // execute test insn
+ (*func)();
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+ printf("#%d: %s ", i/4, test_group.name);
+ for (j = 0; j < 4; j++) {
+ if (j)
+ printf("; ");
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ if (xvrespTest) {
+ float calc_diff = fabs(spec_sp_fargs[i + j]/256);
+ float sp_res;
+ memcpy(&sp_res, &dst_sp[j], 4);
+ float div_result = 1/spec_sp_fargs[i + j];
+ float real_diff = fabs(sp_res - div_result);
+ printf( " ==> %s",
+ ( ( sp_res == div_result )
+ || ( isnan(sp_res) && isnan(div_result) )
+ || ( real_diff <= calc_diff ) ) ? "PASS"
+ : "FAIL");
+ } else {
+ printf(" = %08x", dst_sp[j]);
+ }
+ }
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+
+}
+
+/* This function assumes the instruction being tested requires two args. */
+static void test_vx_vector_fp_ops(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vx_vector_fp_tests[k].test_func)) {
+ int idx, i, repeat = 1;
+ vx_fp_test_t test_group = vx_vector_fp_tests[k];
+ int stride = test_group.precision == DOUBLE_TEST ? 2 : 4;
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv, condreg;
+ unsigned int flags;
+
+ pv = (unsigned int *)&vec_out;
+ if (test_group.precision == DOUBLE_TEST)
+ setup_dp_fp_args(&test_group.targs[i], False);
+ else
+ setup_sp_fp_args(&test_group.targs[i], False);
+
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ if (test_group.type == VX_BASIC_CMP) {
+ condreg = (flags & 0x000000f0) >> 4;
+ } else {
+ condreg = VX_NOT_CMP_OP;
+ }
+ print_vector_fp_result(condreg, &test_group, i);
+ }
+ printf("\n");
+ if (repeat && test_group.type == VX_BASIC_CMP) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+// The div doubleword test data
+signed long long div_dw_tdata[13][2] = {
+ { 4, -4 },
+ { 4, -3 },
+ { 4, 4 },
+ { 4, -5 },
+ { 3, 8 },
+ { 0x8000000000000000ULL, 0xa },
+ { 0x50c, -1 },
+ { 0x50c, -4096 },
+ { 0x1234fedc, 0x8000a873 },
+ { 0xabcd87651234fedcULL, 0xa123b893 },
+ { 0x123456789abdcULL, 0 },
+ { 0, 2 },
+ { 0x77, 0xa3499 }
+};
+#define dw_tdata_len (sizeof(div_dw_tdata)/sizeof(signed long long)/2)
+
+// The div word test data
+unsigned int div_w_tdata[6][2] = {
+ { 0, 2 },
+ { 2, 0 },
+ { 0x7abc1234, 0xf0000000 },
+ { 0xfabc1234, 5 },
+ { 77, 66 },
+ { 5, 0xfabc1234 },
+};
+#define w_tdata_len (sizeof(div_w_tdata)/sizeof(unsigned int)/2)
+
+typedef struct div_ext_test
+{
+ test_func_t test_func;
+ const char *name;
+ int num_tests;
+ div_type_t div_type;
+ precision_type_t precision;
+} div_ext_test_t;
+
+static div_ext_test_t div_tests[] = {
+#ifdef __powerpc64__
+ { &test_divde, "divde", dw_tdata_len, DIV_BASE, DOUBLE_TEST },
+ { &test_divde, "divdeo", dw_tdata_len, DIV_OE, DOUBLE_TEST },
+#endif
+ { &test_divweu, "divweu", w_tdata_len, DIV_BASE, SINGLE_TEST },
+ { &test_divweu, "divweuo", w_tdata_len, DIV_OE, SINGLE_TEST },
+ { NULL, NULL, 0, 0, 0 }
+};
+
+static void test_div_extensions(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = div_tests[k].test_func)) {
+ int i, repeat = 1;
+ div_ext_test_t test_group = div_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int condreg;
+
+ if (test_group.div_type == DIV_OE)
+ do_OE = True;
+ else
+ do_OE = False;
+
+ if (test_group.precision == DOUBLE_TEST) {
+ r14 = div_dw_tdata[i][0];
+ r15 = div_dw_tdata[i][1];
+ } else {
+ r14 = div_w_tdata[i][0];
+ r15 = div_w_tdata[i][1];
+ }
+ // execute test insn
+ (*func)();
+ condreg = (div_flags & 0xf0000000) >> 28;
+ printf("#%d: %s%s: ", i, test_group.name, do_dot ? "." : "");
+ if (test_group.precision == DOUBLE_TEST) {
+ printf("0x%016llx / 0x%016llx = 0x%016llx;",
+ div_dw_tdata[i][0], div_dw_tdata[i][1], (signed long long) r17);
+ } else {
+ printf("0x%08x / 0x%08x = 0x%08x;",
+ div_w_tdata[i][0], div_w_tdata[i][1], (unsigned int) r17);
+ }
+ printf(" CR=%x; XER=%x\n", condreg, div_xer);
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+
+}
+
+static void test_fct_ops(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = fct_tests[k].test_func)) {
+ int i, repeat = 1;
+ simple_test_t test_group = fct_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < nb_special_fargs; i++) {
+ double result;
+#define SINGLE_MASK 0x00000000FFFFFFFFULL
+
+ f14 = spec_fargs[i];
+ // execute test insn
+ SET_FPSCR_ZERO;
+ (*func)();
+ result = f17;
+ printf("#%d: %s%s: ", i, test_group.name, do_dot ? "." : "");
+ printf("0x%016llx (%e) ==> 0x%016llx\n",
+ *((unsigned long long *)(&spec_fargs[i])), spec_fargs[i],
+ test_group.precision == SINGLE_TEST ? (SINGLE_MASK &
+ *((unsigned long long *)(&result))) :
+ *((unsigned long long *)(&result)));
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+#ifdef __powerpc64__
+void test_stdbrx(void)
+{
+ unsigned long long store, val = 0xdeadbacf12345678ULL;
+ printf("stdbrx: 0x%llx ==> ", val);
+ r17 = (HWord_t)val;
+ r14 = (HWord_t)&store;
+ __asm__ __volatile__ ("stdbrx %0, 0, %1" : : "r"(r17), "r"(r14));
+ printf("0x%llx\n", store);
+ printf( "\n" );
+}
+#endif
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_vx_vector_one_fp_arg,
+ "Test VSX vector single arg instructions"},
+ { &test_vx_vector_fp_ops,
+ "Test VSX floating point compare and basic arithmetic instructions" },
+#ifdef __powerpc64__
+ { &test_bpermd,
+ "Test bit permute double"},
+#endif
+ { &test_xxsel,
+ "Test xxsel instruction" },
+ { &test_xxspltw,
+ "Test xxspltw instruction" },
+ { &test_div_extensions,
+ "Test div extensions" },
+ { &test_fct_ops,
+ "Test floating point convert [word | doubleword] unsigned, with round toward zero" },
+#ifdef __powerpc64__
+ { &test_stdbrx,
+ "Test stdbrx instruction"},
+#endif
+ { &test_vx_aORm_fp_ops,
+ "Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p"},
+ { &test_vx_simple_scalar_fp_ops,
+ "Test scalar floating point arithmetic instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_VSX
+
+int main(int argc, char *argv[])
+{
+#ifdef HAS_VSX
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+ if (spec_fargs)
+ free(spec_fargs);
+ if (spec_sp_fargs)
+ free(spec_sp_fargs);
+
+#endif // HAS _VSX
+
+ return 0;
+}
diff --git a/main/none/tests/ppc32/test_isa_2_06_part2.stderr.exp b/main/none/tests/ppc32/test_isa_2_06_part2.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part2.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc32/test_isa_2_06_part2.stdout.exp b/main/none/tests/ppc32/test_isa_2_06_part2.stdout.exp
new file mode 100644
index 0000000..92bbbf2
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part2.stdout.exp
@@ -0,0 +1,1699 @@
+Test VSX vector single arg instructions
+#0: xvresp 1/x(3ec00000) ==> PASS; 1/x(42780000) ==> PASS; 1/x(00000000) ==> PASS; 1/x(7f800000) ==> PASS
+#1: xvresp 1/x(00000000) ==> PASS; 1/x(00000000) ==> PASS; 1/x(80000000) ==> PASS; 1/x(7f800000) ==> PASS
+#2: xvresp 1/x(ff800000) ==> PASS; 1/x(7fffffff) ==> PASS; 1/x(ffffffff) ==> PASS; 1/x(7fc00000) ==> PASS
+#3: xvresp 1/x(ffc00000) ==> PASS; 1/x(80000000) ==> PASS; 1/x(c683287b) ==> PASS; 1/x(49192c2d) ==> PASS
+
+#0: xvcvdpsxws conv(3fd8000000000000) = 0000000000000000; conv(404f000000000000) = 000000000000003e
+#1: xvcvdpsxws conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = 000000007fffffff
+#2: xvcvdpsxws conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpsxws conv(8000000000000000) = 0000000000000000; conv(7ff0000000000000) = 000000007fffffff
+#4: xvcvdpsxws conv(fff0000000000000) = 0000000080000000; conv(7ff7ffffffffffff) = 0000000080000000
+#5: xvcvdpsxws conv(fff7ffffffffffff) = 0000000080000000; conv(7ff8000000000000) = 0000000080000000
+#6: xvcvdpsxws conv(fff8000000000000) = 0000000080000000; conv(8008340000078000) = 0000000000000000
+#7: xvcvdpsxws conv(c0d0650f5a07b353) = 00000000ffffbe6c; conv(41232585a9900000) = 00000000000992c2
+
+#0: xvcvspsxws conv(3ec00000) = 00000000; conv(42780000) = 0000003e; conv(00000000) = 00000000; conv(7f800000) = 7fffffff
+#1: xvcvspsxws conv(00000000) = 00000000; conv(00000000) = 00000000; conv(80000000) = 00000000; conv(7f800000) = 7fffffff
+#2: xvcvspsxws conv(ff800000) = 80000000; conv(7fffffff) = 80000000; conv(ffffffff) = 80000000; conv(7fc00000) = 80000000
+#3: xvcvspsxws conv(ffc00000) = 80000000; conv(80000000) = 00000000; conv(c683287b) = ffffbe6c; conv(49192c2d) = 000992c2
+
+Test VSX floating point compare and basic arithmetic instructions
+#0: xvcmpeqdp fff0000000000000 eq fff0000000000000 AND fff0000000000000 eq c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#1: xvcmpeqdp fff0000000000000 eq 8000000000000000 AND fff0000000000000 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#2: xvcmpeqdp fff0000000000000 eq 0123214569900000 AND fff0000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#3: xvcmpeqdp fff0000000000000 eq 7ff7ffffffffffff AND fff0000000000000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#4: xvcmpeqdp c0d0650f5a07b353 eq fff0000000000000 AND c0d0650f5a07b353 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 ffffffffffffffff
+#5: xvcmpeqdp c0d0650f5a07b353 eq 8000000000000000 AND c0d0650f5a07b353 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#6: xvcmpeqdp c0d0650f5a07b353 eq 0123214569900000 AND c0d0650f5a07b353 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#7: xvcmpeqdp c0d0650f5a07b353 eq 7ff7ffffffffffff AND c0d0650f5a07b353 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#8: xvcmpeqdp 8000000000000000 eq fff0000000000000 AND 8000000000000000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#9: xvcmpeqdp 8000000000000000 eq 8000000000000000 AND 8000000000000000 eq 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#10: xvcmpeqdp 8000000000000000 eq 0123214569900000 AND 8000000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#11: xvcmpeqdp 8000000000000000 eq 7ff7ffffffffffff AND 8000000000000000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#12: xvcmpeqdp 0000000000000000 eq fff0000000000000 AND 0000000000000000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#13: xvcmpeqdp 0000000000000000 eq 8000000000000000 AND 0000000000000000 eq 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#14: xvcmpeqdp 0000000000000000 eq 0123214569900000 AND 0000000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#15: xvcmpeqdp 0000000000000000 eq 7ff7ffffffffffff AND 0000000000000000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#16: xvcmpeqdp 0123214569900000 eq fff0000000000000 AND 0123214569900000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#17: xvcmpeqdp 0123214569900000 eq 8000000000000000 AND 0123214569900000 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#18: xvcmpeqdp 0123214569900000 eq 404f000000000000 AND 0123214569900000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#19: xvcmpeqdp 0123214569900000 eq 7ff7ffffffffffff AND 0123214569900000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#20: xvcmpeqdp 7ff0000000000000 eq fff0000000000000 AND 7ff0000000000000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#21: xvcmpeqdp 7ff0000000000000 eq 8000000000000000 AND 7ff0000000000000 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#22: xvcmpeqdp 7ff0000000000000 eq 0123214569900000 AND 7ff0000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 ffffffffffffffff
+#23: xvcmpeqdp 7ff0000000000000 eq 7ff7ffffffffffff AND 7ff0000000000000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#24: xvcmpeqdp fff7ffffffffffff eq fff0000000000000 AND fff7ffffffffffff eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#25: xvcmpeqdp fff7ffffffffffff eq 8000000000000000 AND fff7ffffffffffff eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#26: xvcmpeqdp fff7ffffffffffff eq 0123214569900000 AND fff7ffffffffffff eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#27: xvcmpeqdp fff7ffffffffffff eq 7ff7ffffffffffff AND fff7ffffffffffff eq fff7ffffffffffff ? cc=0 => 0000000000000000 0000000000000000
+#28: xvcmpeqdp fff8000000000000 eq fff0000000000000 AND fff8000000000000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#29: xvcmpeqdp fff8000000000000 eq 8000000000000000 AND fff8000000000000 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#30: xvcmpeqdp 404f000000000000 eq 404f000000000000 AND 0018000000b77501 eq 0018000000b77501 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#31: xvcmpeqdp 7fe800000000051b eq 7fe800000000051b AND 0123214569900000 eq 0123214569900000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+
+#0: xvcmpeqdp. fff0000000000000 eq fff0000000000000 AND fff0000000000000 eq c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#1: xvcmpeqdp. fff0000000000000 eq 8000000000000000 AND fff0000000000000 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#2: xvcmpeqdp. fff0000000000000 eq 0123214569900000 AND fff0000000000000 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#3: xvcmpeqdp. fff0000000000000 eq 7ff7ffffffffffff AND fff0000000000000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#4: xvcmpeqdp. c0d0650f5a07b353 eq fff0000000000000 AND c0d0650f5a07b353 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 ffffffffffffffff
+#5: xvcmpeqdp. c0d0650f5a07b353 eq 8000000000000000 AND c0d0650f5a07b353 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#6: xvcmpeqdp. c0d0650f5a07b353 eq 0123214569900000 AND c0d0650f5a07b353 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#7: xvcmpeqdp. c0d0650f5a07b353 eq 7ff7ffffffffffff AND c0d0650f5a07b353 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#8: xvcmpeqdp. 8000000000000000 eq fff0000000000000 AND 8000000000000000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#9: xvcmpeqdp. 8000000000000000 eq 8000000000000000 AND 8000000000000000 eq 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#10: xvcmpeqdp. 8000000000000000 eq 0123214569900000 AND 8000000000000000 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#11: xvcmpeqdp. 8000000000000000 eq 7ff7ffffffffffff AND 8000000000000000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#12: xvcmpeqdp. 0000000000000000 eq fff0000000000000 AND 0000000000000000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#13: xvcmpeqdp. 0000000000000000 eq 8000000000000000 AND 0000000000000000 eq 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#14: xvcmpeqdp. 0000000000000000 eq 0123214569900000 AND 0000000000000000 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#15: xvcmpeqdp. 0000000000000000 eq 7ff7ffffffffffff AND 0000000000000000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#16: xvcmpeqdp. 0123214569900000 eq fff0000000000000 AND 0123214569900000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#17: xvcmpeqdp. 0123214569900000 eq 8000000000000000 AND 0123214569900000 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#18: xvcmpeqdp. 0123214569900000 eq 404f000000000000 AND 0123214569900000 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#19: xvcmpeqdp. 0123214569900000 eq 7ff7ffffffffffff AND 0123214569900000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#20: xvcmpeqdp. 7ff0000000000000 eq fff0000000000000 AND 7ff0000000000000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#21: xvcmpeqdp. 7ff0000000000000 eq 8000000000000000 AND 7ff0000000000000 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#22: xvcmpeqdp. 7ff0000000000000 eq 0123214569900000 AND 7ff0000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 ffffffffffffffff
+#23: xvcmpeqdp. 7ff0000000000000 eq 7ff7ffffffffffff AND 7ff0000000000000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#24: xvcmpeqdp. fff7ffffffffffff eq fff0000000000000 AND fff7ffffffffffff eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#25: xvcmpeqdp. fff7ffffffffffff eq 8000000000000000 AND fff7ffffffffffff eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#26: xvcmpeqdp. fff7ffffffffffff eq 0123214569900000 AND fff7ffffffffffff eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#27: xvcmpeqdp. fff7ffffffffffff eq 7ff7ffffffffffff AND fff7ffffffffffff eq fff7ffffffffffff ? cc=2 => 0000000000000000 0000000000000000
+#28: xvcmpeqdp. fff8000000000000 eq fff0000000000000 AND fff8000000000000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#29: xvcmpeqdp. fff8000000000000 eq 8000000000000000 AND fff8000000000000 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#30: xvcmpeqdp. 404f000000000000 eq 404f000000000000 AND 0018000000b77501 eq 0018000000b77501 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#31: xvcmpeqdp. 7fe800000000051b eq 7fe800000000051b AND 0123214569900000 eq 0123214569900000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+
+
+#0: xvcmpgedp fff0000000000000 ge fff0000000000000 AND fff0000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#1: xvcmpgedp fff0000000000000 ge 8000000000000000 AND fff0000000000000 ge 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#2: xvcmpgedp fff0000000000000 ge 0123214569900000 AND fff0000000000000 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#3: xvcmpgedp fff0000000000000 ge 7ff7ffffffffffff AND fff0000000000000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#4: xvcmpgedp c0d0650f5a07b353 ge fff0000000000000 AND c0d0650f5a07b353 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#5: xvcmpgedp c0d0650f5a07b353 ge 8000000000000000 AND c0d0650f5a07b353 ge 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#6: xvcmpgedp c0d0650f5a07b353 ge 0123214569900000 AND c0d0650f5a07b353 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#7: xvcmpgedp c0d0650f5a07b353 ge 7ff7ffffffffffff AND c0d0650f5a07b353 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#8: xvcmpgedp 8000000000000000 ge fff0000000000000 AND 8000000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#9: xvcmpgedp 8000000000000000 ge 8000000000000000 AND 8000000000000000 ge 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#10: xvcmpgedp 8000000000000000 ge 0123214569900000 AND 8000000000000000 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#11: xvcmpgedp 8000000000000000 ge 7ff7ffffffffffff AND 8000000000000000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#12: xvcmpgedp 0000000000000000 ge fff0000000000000 AND 0000000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#13: xvcmpgedp 0000000000000000 ge 8000000000000000 AND 0000000000000000 ge 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#14: xvcmpgedp 0000000000000000 ge 0123214569900000 AND 0000000000000000 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#15: xvcmpgedp 0000000000000000 ge 7ff7ffffffffffff AND 0000000000000000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#16: xvcmpgedp 0123214569900000 ge fff0000000000000 AND 0123214569900000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#17: xvcmpgedp 0123214569900000 ge 8000000000000000 AND 0123214569900000 ge 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#18: xvcmpgedp 0123214569900000 ge 404f000000000000 AND 0123214569900000 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#19: xvcmpgedp 0123214569900000 ge 7ff7ffffffffffff AND 0123214569900000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#20: xvcmpgedp 7ff0000000000000 ge fff0000000000000 AND 7ff0000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#21: xvcmpgedp 7ff0000000000000 ge 8000000000000000 AND 7ff0000000000000 ge 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#22: xvcmpgedp 7ff0000000000000 ge 0123214569900000 AND 7ff0000000000000 ge 7ff0000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#23: xvcmpgedp 7ff0000000000000 ge 7ff7ffffffffffff AND 7ff0000000000000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#24: xvcmpgedp fff7ffffffffffff ge fff0000000000000 AND fff7ffffffffffff ge c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#25: xvcmpgedp fff7ffffffffffff ge 8000000000000000 AND fff7ffffffffffff ge 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#26: xvcmpgedp fff7ffffffffffff ge 0123214569900000 AND fff7ffffffffffff ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#27: xvcmpgedp fff7ffffffffffff ge 7ff7ffffffffffff AND fff7ffffffffffff ge fff7ffffffffffff ? cc=0 => 0000000000000000 0000000000000000
+#28: xvcmpgedp fff8000000000000 ge fff0000000000000 AND fff8000000000000 ge c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#29: xvcmpgedp fff8000000000000 ge 8000000000000000 AND fff8000000000000 ge 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#30: xvcmpgedp 404f000000000000 ge 404f000000000000 AND 0018000000b77501 ge 0018000000b77501 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#31: xvcmpgedp 7fe800000000051b ge 7fe800000000051b AND 0123214569900000 ge 0123214569900000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+
+#0: xvcmpgedp. fff0000000000000 ge fff0000000000000 AND fff0000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#1: xvcmpgedp. fff0000000000000 ge 8000000000000000 AND fff0000000000000 ge 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#2: xvcmpgedp. fff0000000000000 ge 0123214569900000 AND fff0000000000000 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#3: xvcmpgedp. fff0000000000000 ge 7ff7ffffffffffff AND fff0000000000000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#4: xvcmpgedp. c0d0650f5a07b353 ge fff0000000000000 AND c0d0650f5a07b353 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#5: xvcmpgedp. c0d0650f5a07b353 ge 8000000000000000 AND c0d0650f5a07b353 ge 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#6: xvcmpgedp. c0d0650f5a07b353 ge 0123214569900000 AND c0d0650f5a07b353 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#7: xvcmpgedp. c0d0650f5a07b353 ge 7ff7ffffffffffff AND c0d0650f5a07b353 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#8: xvcmpgedp. 8000000000000000 ge fff0000000000000 AND 8000000000000000 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#9: xvcmpgedp. 8000000000000000 ge 8000000000000000 AND 8000000000000000 ge 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#10: xvcmpgedp. 8000000000000000 ge 0123214569900000 AND 8000000000000000 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#11: xvcmpgedp. 8000000000000000 ge 7ff7ffffffffffff AND 8000000000000000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#12: xvcmpgedp. 0000000000000000 ge fff0000000000000 AND 0000000000000000 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#13: xvcmpgedp. 0000000000000000 ge 8000000000000000 AND 0000000000000000 ge 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#14: xvcmpgedp. 0000000000000000 ge 0123214569900000 AND 0000000000000000 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#15: xvcmpgedp. 0000000000000000 ge 7ff7ffffffffffff AND 0000000000000000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#16: xvcmpgedp. 0123214569900000 ge fff0000000000000 AND 0123214569900000 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#17: xvcmpgedp. 0123214569900000 ge 8000000000000000 AND 0123214569900000 ge 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#18: xvcmpgedp. 0123214569900000 ge 404f000000000000 AND 0123214569900000 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#19: xvcmpgedp. 0123214569900000 ge 7ff7ffffffffffff AND 0123214569900000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#20: xvcmpgedp. 7ff0000000000000 ge fff0000000000000 AND 7ff0000000000000 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#21: xvcmpgedp. 7ff0000000000000 ge 8000000000000000 AND 7ff0000000000000 ge 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#22: xvcmpgedp. 7ff0000000000000 ge 0123214569900000 AND 7ff0000000000000 ge 7ff0000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#23: xvcmpgedp. 7ff0000000000000 ge 7ff7ffffffffffff AND 7ff0000000000000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#24: xvcmpgedp. fff7ffffffffffff ge fff0000000000000 AND fff7ffffffffffff ge c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#25: xvcmpgedp. fff7ffffffffffff ge 8000000000000000 AND fff7ffffffffffff ge 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#26: xvcmpgedp. fff7ffffffffffff ge 0123214569900000 AND fff7ffffffffffff ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#27: xvcmpgedp. fff7ffffffffffff ge 7ff7ffffffffffff AND fff7ffffffffffff ge fff7ffffffffffff ? cc=2 => 0000000000000000 0000000000000000
+#28: xvcmpgedp. fff8000000000000 ge fff0000000000000 AND fff8000000000000 ge c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#29: xvcmpgedp. fff8000000000000 ge 8000000000000000 AND fff8000000000000 ge 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#30: xvcmpgedp. 404f000000000000 ge 404f000000000000 AND 0018000000b77501 ge 0018000000b77501 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#31: xvcmpgedp. 7fe800000000051b ge 7fe800000000051b AND 0123214569900000 ge 0123214569900000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+
+
+#0: xvcmpgtdp fff0000000000000 gt fff0000000000000 AND fff0000000000000 gt c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#1: xvcmpgtdp fff0000000000000 gt 8000000000000000 AND fff0000000000000 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#2: xvcmpgtdp fff0000000000000 gt 0123214569900000 AND fff0000000000000 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#3: xvcmpgtdp fff0000000000000 gt 7ff7ffffffffffff AND fff0000000000000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#4: xvcmpgtdp c0d0650f5a07b353 gt fff0000000000000 AND c0d0650f5a07b353 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#5: xvcmpgtdp c0d0650f5a07b353 gt 8000000000000000 AND c0d0650f5a07b353 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#6: xvcmpgtdp c0d0650f5a07b353 gt 0123214569900000 AND c0d0650f5a07b353 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#7: xvcmpgtdp c0d0650f5a07b353 gt 7ff7ffffffffffff AND c0d0650f5a07b353 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#8: xvcmpgtdp 8000000000000000 gt fff0000000000000 AND 8000000000000000 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#9: xvcmpgtdp 8000000000000000 gt 8000000000000000 AND 8000000000000000 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#10: xvcmpgtdp 8000000000000000 gt 0123214569900000 AND 8000000000000000 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#11: xvcmpgtdp 8000000000000000 gt 7ff7ffffffffffff AND 8000000000000000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#12: xvcmpgtdp 0000000000000000 gt fff0000000000000 AND 0000000000000000 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#13: xvcmpgtdp 0000000000000000 gt 8000000000000000 AND 0000000000000000 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#14: xvcmpgtdp 0000000000000000 gt 0123214569900000 AND 0000000000000000 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#15: xvcmpgtdp 0000000000000000 gt 7ff7ffffffffffff AND 0000000000000000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#16: xvcmpgtdp 0123214569900000 gt fff0000000000000 AND 0123214569900000 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#17: xvcmpgtdp 0123214569900000 gt 8000000000000000 AND 0123214569900000 gt 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#18: xvcmpgtdp 0123214569900000 gt 404f000000000000 AND 0123214569900000 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#19: xvcmpgtdp 0123214569900000 gt 7ff7ffffffffffff AND 0123214569900000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#20: xvcmpgtdp 7ff0000000000000 gt fff0000000000000 AND 7ff0000000000000 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#21: xvcmpgtdp 7ff0000000000000 gt 8000000000000000 AND 7ff0000000000000 gt 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#22: xvcmpgtdp 7ff0000000000000 gt 0123214569900000 AND 7ff0000000000000 gt 7ff0000000000000 ? cc=0 => ffffffffffffffff 0000000000000000
+#23: xvcmpgtdp 7ff0000000000000 gt 7ff7ffffffffffff AND 7ff0000000000000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#24: xvcmpgtdp fff7ffffffffffff gt fff0000000000000 AND fff7ffffffffffff gt c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#25: xvcmpgtdp fff7ffffffffffff gt 8000000000000000 AND fff7ffffffffffff gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#26: xvcmpgtdp fff7ffffffffffff gt 0123214569900000 AND fff7ffffffffffff gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#27: xvcmpgtdp fff7ffffffffffff gt 7ff7ffffffffffff AND fff7ffffffffffff gt fff7ffffffffffff ? cc=0 => 0000000000000000 0000000000000000
+#28: xvcmpgtdp fff8000000000000 gt fff0000000000000 AND fff8000000000000 gt c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#29: xvcmpgtdp fff8000000000000 gt 8000000000000000 AND fff8000000000000 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#30: xvcmpgtdp 404f000000000000 gt 404f000000000000 AND 0018000000b77501 gt 0018000000b77501 ? cc=0 => 0000000000000000 0000000000000000
+#31: xvcmpgtdp 7fe800000000051b gt 7fe800000000051b AND 0123214569900000 gt 0123214569900000 ? cc=0 => 0000000000000000 0000000000000000
+
+#0: xvcmpgtdp. fff0000000000000 gt fff0000000000000 AND fff0000000000000 gt c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#1: xvcmpgtdp. fff0000000000000 gt 8000000000000000 AND fff0000000000000 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#2: xvcmpgtdp. fff0000000000000 gt 0123214569900000 AND fff0000000000000 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#3: xvcmpgtdp. fff0000000000000 gt 7ff7ffffffffffff AND fff0000000000000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#4: xvcmpgtdp. c0d0650f5a07b353 gt fff0000000000000 AND c0d0650f5a07b353 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#5: xvcmpgtdp. c0d0650f5a07b353 gt 8000000000000000 AND c0d0650f5a07b353 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#6: xvcmpgtdp. c0d0650f5a07b353 gt 0123214569900000 AND c0d0650f5a07b353 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#7: xvcmpgtdp. c0d0650f5a07b353 gt 7ff7ffffffffffff AND c0d0650f5a07b353 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#8: xvcmpgtdp. 8000000000000000 gt fff0000000000000 AND 8000000000000000 gt c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#9: xvcmpgtdp. 8000000000000000 gt 8000000000000000 AND 8000000000000000 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#10: xvcmpgtdp. 8000000000000000 gt 0123214569900000 AND 8000000000000000 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#11: xvcmpgtdp. 8000000000000000 gt 7ff7ffffffffffff AND 8000000000000000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#12: xvcmpgtdp. 0000000000000000 gt fff0000000000000 AND 0000000000000000 gt c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#13: xvcmpgtdp. 0000000000000000 gt 8000000000000000 AND 0000000000000000 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#14: xvcmpgtdp. 0000000000000000 gt 0123214569900000 AND 0000000000000000 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#15: xvcmpgtdp. 0000000000000000 gt 7ff7ffffffffffff AND 0000000000000000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#16: xvcmpgtdp. 0123214569900000 gt fff0000000000000 AND 0123214569900000 gt c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#17: xvcmpgtdp. 0123214569900000 gt 8000000000000000 AND 0123214569900000 gt 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#18: xvcmpgtdp. 0123214569900000 gt 404f000000000000 AND 0123214569900000 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#19: xvcmpgtdp. 0123214569900000 gt 7ff7ffffffffffff AND 0123214569900000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#20: xvcmpgtdp. 7ff0000000000000 gt fff0000000000000 AND 7ff0000000000000 gt c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#21: xvcmpgtdp. 7ff0000000000000 gt 8000000000000000 AND 7ff0000000000000 gt 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#22: xvcmpgtdp. 7ff0000000000000 gt 0123214569900000 AND 7ff0000000000000 gt 7ff0000000000000 ? cc=0 => ffffffffffffffff 0000000000000000
+#23: xvcmpgtdp. 7ff0000000000000 gt 7ff7ffffffffffff AND 7ff0000000000000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#24: xvcmpgtdp. fff7ffffffffffff gt fff0000000000000 AND fff7ffffffffffff gt c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#25: xvcmpgtdp. fff7ffffffffffff gt 8000000000000000 AND fff7ffffffffffff gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#26: xvcmpgtdp. fff7ffffffffffff gt 0123214569900000 AND fff7ffffffffffff gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#27: xvcmpgtdp. fff7ffffffffffff gt 7ff7ffffffffffff AND fff7ffffffffffff gt fff7ffffffffffff ? cc=2 => 0000000000000000 0000000000000000
+#28: xvcmpgtdp. fff8000000000000 gt fff0000000000000 AND fff8000000000000 gt c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#29: xvcmpgtdp. fff8000000000000 gt 8000000000000000 AND fff8000000000000 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#30: xvcmpgtdp. 404f000000000000 gt 404f000000000000 AND 0018000000b77501 gt 0018000000b77501 ? cc=2 => 0000000000000000 0000000000000000
+#31: xvcmpgtdp. 7fe800000000051b gt 7fe800000000051b AND 0123214569900000 gt 0123214569900000 ? cc=2 => 0000000000000000 0000000000000000
+
+
+#0: xvcmpeqsp ff800000 eq ff800000 AND ff800000 eq c683287b AND ff800000 eq 80000000 AND ff800000 eq 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#1: xvcmpeqsp ff800000 eq 00000000 AND ff800000 eq 7f800000 AND ff800000 eq 7fffffff AND ff800000 eq 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#2: xvcmpeqsp c683287b eq ff800000 AND c683287b eq c683287b AND c683287b eq 80000000 AND c683287b eq 00000000 ? cc=0 => 00000000 ffffffff 00000000 00000000
+#3: xvcmpeqsp c683287b eq 00000000 AND c683287b eq 7f800000 AND c683287b eq 7fffffff AND c683287b eq 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#4: xvcmpeqsp 80000000 eq ff800000 AND 80000000 eq c683287b AND 80000000 eq 80000000 AND 80000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#5: xvcmpeqsp 80000000 eq 00000000 AND 80000000 eq 7f800000 AND 80000000 eq 7fffffff AND 80000000 eq 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#6: xvcmpeqsp 00000000 eq ff800000 AND 00000000 eq c683287b AND 00000000 eq 80000000 AND 00000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#7: xvcmpeqsp 00000000 eq 00000000 AND 00000000 eq 7f800000 AND 00000000 eq 7fffffff AND 00000000 eq 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#8: xvcmpeqsp 00000000 eq ff800000 AND 00000000 eq c683287b AND 00000000 eq 80000000 AND 00000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#9: xvcmpeqsp 00000000 eq 42780000 AND 00000000 eq 7f800000 AND 00000000 eq 7fffffff AND 00000000 eq 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#10: xvcmpeqsp 7f800000 eq ff800000 AND 7f800000 eq c683287b AND 7f800000 eq 80000000 AND 7f800000 eq 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#11: xvcmpeqsp 7f800000 eq 00000000 AND 7f800000 eq 7f800000 AND 7f800000 eq 7fffffff AND 7f800000 eq 7fc00000 ? cc=0 => 00000000 ffffffff 00000000 00000000
+#12: xvcmpeqsp ffffffff eq ff800000 AND ffffffff eq c683287b AND ffffffff eq 80000000 AND ffffffff eq 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#13: xvcmpeqsp ffffffff eq 00000000 AND ffffffff eq 7f800000 AND ffffffff eq 7fffffff AND ffffffff eq ffffffff ? cc=0 => 00000000 00000000 00000000 00000000
+#14: xvcmpeqsp ffc00000 eq ff800000 AND ffc00000 eq c683287b AND ffc00000 eq 80000000 AND ffc00000 eq 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#15: xvcmpeqsp 42780000 eq 42780000 AND 00000000 eq 00000000 AND 7f800000 eq 7f800000 AND 00000000 eq 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+
+#0: xvcmpeqsp. ff800000 eq ff800000 AND ff800000 eq c683287b AND ff800000 eq 80000000 AND ff800000 eq 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#1: xvcmpeqsp. ff800000 eq 00000000 AND ff800000 eq 7f800000 AND ff800000 eq 7fffffff AND ff800000 eq 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#2: xvcmpeqsp. c683287b eq ff800000 AND c683287b eq c683287b AND c683287b eq 80000000 AND c683287b eq 00000000 ? cc=0 => 00000000 ffffffff 00000000 00000000
+#3: xvcmpeqsp. c683287b eq 00000000 AND c683287b eq 7f800000 AND c683287b eq 7fffffff AND c683287b eq 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#4: xvcmpeqsp. 80000000 eq ff800000 AND 80000000 eq c683287b AND 80000000 eq 80000000 AND 80000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#5: xvcmpeqsp. 80000000 eq 00000000 AND 80000000 eq 7f800000 AND 80000000 eq 7fffffff AND 80000000 eq 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#6: xvcmpeqsp. 00000000 eq ff800000 AND 00000000 eq c683287b AND 00000000 eq 80000000 AND 00000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#7: xvcmpeqsp. 00000000 eq 00000000 AND 00000000 eq 7f800000 AND 00000000 eq 7fffffff AND 00000000 eq 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#8: xvcmpeqsp. 00000000 eq ff800000 AND 00000000 eq c683287b AND 00000000 eq 80000000 AND 00000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#9: xvcmpeqsp. 00000000 eq 42780000 AND 00000000 eq 7f800000 AND 00000000 eq 7fffffff AND 00000000 eq 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#10: xvcmpeqsp. 7f800000 eq ff800000 AND 7f800000 eq c683287b AND 7f800000 eq 80000000 AND 7f800000 eq 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#11: xvcmpeqsp. 7f800000 eq 00000000 AND 7f800000 eq 7f800000 AND 7f800000 eq 7fffffff AND 7f800000 eq 7fc00000 ? cc=0 => 00000000 ffffffff 00000000 00000000
+#12: xvcmpeqsp. ffffffff eq ff800000 AND ffffffff eq c683287b AND ffffffff eq 80000000 AND ffffffff eq 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#13: xvcmpeqsp. ffffffff eq 00000000 AND ffffffff eq 7f800000 AND ffffffff eq 7fffffff AND ffffffff eq ffffffff ? cc=2 => 00000000 00000000 00000000 00000000
+#14: xvcmpeqsp. ffc00000 eq ff800000 AND ffc00000 eq c683287b AND ffc00000 eq 80000000 AND ffc00000 eq 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#15: xvcmpeqsp. 42780000 eq 42780000 AND 00000000 eq 00000000 AND 7f800000 eq 7f800000 AND 00000000 eq 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+
+
+#0: xvcmpgesp ff800000 ge ff800000 AND ff800000 ge c683287b AND ff800000 ge 80000000 AND ff800000 ge 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#1: xvcmpgesp ff800000 ge 00000000 AND ff800000 ge 7f800000 AND ff800000 ge 7fffffff AND ff800000 ge 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#2: xvcmpgesp c683287b ge ff800000 AND c683287b ge c683287b AND c683287b ge 80000000 AND c683287b ge 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#3: xvcmpgesp c683287b ge 00000000 AND c683287b ge 7f800000 AND c683287b ge 7fffffff AND c683287b ge 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#4: xvcmpgesp 80000000 ge ff800000 AND 80000000 ge c683287b AND 80000000 ge 80000000 AND 80000000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#5: xvcmpgesp 80000000 ge 00000000 AND 80000000 ge 7f800000 AND 80000000 ge 7fffffff AND 80000000 ge 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#6: xvcmpgesp 00000000 ge ff800000 AND 00000000 ge c683287b AND 00000000 ge 80000000 AND 00000000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#7: xvcmpgesp 00000000 ge 00000000 AND 00000000 ge 7f800000 AND 00000000 ge 7fffffff AND 00000000 ge 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#8: xvcmpgesp 00000000 ge ff800000 AND 00000000 ge c683287b AND 00000000 ge 80000000 AND 00000000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#9: xvcmpgesp 00000000 ge 42780000 AND 00000000 ge 7f800000 AND 00000000 ge 7fffffff AND 00000000 ge 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#10: xvcmpgesp 7f800000 ge ff800000 AND 7f800000 ge c683287b AND 7f800000 ge 80000000 AND 7f800000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#11: xvcmpgesp 7f800000 ge 00000000 AND 7f800000 ge 7f800000 AND 7f800000 ge 7fffffff AND 7f800000 ge 7fc00000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#12: xvcmpgesp ffffffff ge ff800000 AND ffffffff ge c683287b AND ffffffff ge 80000000 AND ffffffff ge 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#13: xvcmpgesp ffffffff ge 00000000 AND ffffffff ge 7f800000 AND ffffffff ge 7fffffff AND ffffffff ge ffffffff ? cc=0 => 00000000 00000000 00000000 00000000
+#14: xvcmpgesp ffc00000 ge ff800000 AND ffc00000 ge c683287b AND ffc00000 ge 80000000 AND ffc00000 ge 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#15: xvcmpgesp 42780000 ge 42780000 AND 00000000 ge 00000000 AND 7f800000 ge 7f800000 AND 00000000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+
+#0: xvcmpgesp. ff800000 ge ff800000 AND ff800000 ge c683287b AND ff800000 ge 80000000 AND ff800000 ge 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#1: xvcmpgesp. ff800000 ge 00000000 AND ff800000 ge 7f800000 AND ff800000 ge 7fffffff AND ff800000 ge 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#2: xvcmpgesp. c683287b ge ff800000 AND c683287b ge c683287b AND c683287b ge 80000000 AND c683287b ge 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#3: xvcmpgesp. c683287b ge 00000000 AND c683287b ge 7f800000 AND c683287b ge 7fffffff AND c683287b ge 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#4: xvcmpgesp. 80000000 ge ff800000 AND 80000000 ge c683287b AND 80000000 ge 80000000 AND 80000000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#5: xvcmpgesp. 80000000 ge 00000000 AND 80000000 ge 7f800000 AND 80000000 ge 7fffffff AND 80000000 ge 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#6: xvcmpgesp. 00000000 ge ff800000 AND 00000000 ge c683287b AND 00000000 ge 80000000 AND 00000000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#7: xvcmpgesp. 00000000 ge 00000000 AND 00000000 ge 7f800000 AND 00000000 ge 7fffffff AND 00000000 ge 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#8: xvcmpgesp. 00000000 ge ff800000 AND 00000000 ge c683287b AND 00000000 ge 80000000 AND 00000000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#9: xvcmpgesp. 00000000 ge 42780000 AND 00000000 ge 7f800000 AND 00000000 ge 7fffffff AND 00000000 ge 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#10: xvcmpgesp. 7f800000 ge ff800000 AND 7f800000 ge c683287b AND 7f800000 ge 80000000 AND 7f800000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#11: xvcmpgesp. 7f800000 ge 00000000 AND 7f800000 ge 7f800000 AND 7f800000 ge 7fffffff AND 7f800000 ge 7fc00000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#12: xvcmpgesp. ffffffff ge ff800000 AND ffffffff ge c683287b AND ffffffff ge 80000000 AND ffffffff ge 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#13: xvcmpgesp. ffffffff ge 00000000 AND ffffffff ge 7f800000 AND ffffffff ge 7fffffff AND ffffffff ge ffffffff ? cc=2 => 00000000 00000000 00000000 00000000
+#14: xvcmpgesp. ffc00000 ge ff800000 AND ffc00000 ge c683287b AND ffc00000 ge 80000000 AND ffc00000 ge 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#15: xvcmpgesp. 42780000 ge 42780000 AND 00000000 ge 00000000 AND 7f800000 ge 7f800000 AND 00000000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+
+
+#0: xvcmpgtsp ff800000 gt ff800000 AND ff800000 gt c683287b AND ff800000 gt 80000000 AND ff800000 gt 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#1: xvcmpgtsp ff800000 gt 00000000 AND ff800000 gt 7f800000 AND ff800000 gt 7fffffff AND ff800000 gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#2: xvcmpgtsp c683287b gt ff800000 AND c683287b gt c683287b AND c683287b gt 80000000 AND c683287b gt 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#3: xvcmpgtsp c683287b gt 00000000 AND c683287b gt 7f800000 AND c683287b gt 7fffffff AND c683287b gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#4: xvcmpgtsp 80000000 gt ff800000 AND 80000000 gt c683287b AND 80000000 gt 80000000 AND 80000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#5: xvcmpgtsp 80000000 gt 00000000 AND 80000000 gt 7f800000 AND 80000000 gt 7fffffff AND 80000000 gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#6: xvcmpgtsp 00000000 gt ff800000 AND 00000000 gt c683287b AND 00000000 gt 80000000 AND 00000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#7: xvcmpgtsp 00000000 gt 00000000 AND 00000000 gt 7f800000 AND 00000000 gt 7fffffff AND 00000000 gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#8: xvcmpgtsp 00000000 gt ff800000 AND 00000000 gt c683287b AND 00000000 gt 80000000 AND 00000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#9: xvcmpgtsp 00000000 gt 42780000 AND 00000000 gt 7f800000 AND 00000000 gt 7fffffff AND 00000000 gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#10: xvcmpgtsp 7f800000 gt ff800000 AND 7f800000 gt c683287b AND 7f800000 gt 80000000 AND 7f800000 gt 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#11: xvcmpgtsp 7f800000 gt 00000000 AND 7f800000 gt 7f800000 AND 7f800000 gt 7fffffff AND 7f800000 gt 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#12: xvcmpgtsp ffffffff gt ff800000 AND ffffffff gt c683287b AND ffffffff gt 80000000 AND ffffffff gt 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#13: xvcmpgtsp ffffffff gt 00000000 AND ffffffff gt 7f800000 AND ffffffff gt 7fffffff AND ffffffff gt ffffffff ? cc=0 => 00000000 00000000 00000000 00000000
+#14: xvcmpgtsp ffc00000 gt ff800000 AND ffc00000 gt c683287b AND ffc00000 gt 80000000 AND ffc00000 gt 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#15: xvcmpgtsp 42780000 gt 42780000 AND 00000000 gt 00000000 AND 7f800000 gt 7f800000 AND 00000000 gt 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+
+#0: xvcmpgtsp. ff800000 gt ff800000 AND ff800000 gt c683287b AND ff800000 gt 80000000 AND ff800000 gt 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#1: xvcmpgtsp. ff800000 gt 00000000 AND ff800000 gt 7f800000 AND ff800000 gt 7fffffff AND ff800000 gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#2: xvcmpgtsp. c683287b gt ff800000 AND c683287b gt c683287b AND c683287b gt 80000000 AND c683287b gt 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#3: xvcmpgtsp. c683287b gt 00000000 AND c683287b gt 7f800000 AND c683287b gt 7fffffff AND c683287b gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#4: xvcmpgtsp. 80000000 gt ff800000 AND 80000000 gt c683287b AND 80000000 gt 80000000 AND 80000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#5: xvcmpgtsp. 80000000 gt 00000000 AND 80000000 gt 7f800000 AND 80000000 gt 7fffffff AND 80000000 gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#6: xvcmpgtsp. 00000000 gt ff800000 AND 00000000 gt c683287b AND 00000000 gt 80000000 AND 00000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#7: xvcmpgtsp. 00000000 gt 00000000 AND 00000000 gt 7f800000 AND 00000000 gt 7fffffff AND 00000000 gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#8: xvcmpgtsp. 00000000 gt ff800000 AND 00000000 gt c683287b AND 00000000 gt 80000000 AND 00000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#9: xvcmpgtsp. 00000000 gt 42780000 AND 00000000 gt 7f800000 AND 00000000 gt 7fffffff AND 00000000 gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#10: xvcmpgtsp. 7f800000 gt ff800000 AND 7f800000 gt c683287b AND 7f800000 gt 80000000 AND 7f800000 gt 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#11: xvcmpgtsp. 7f800000 gt 00000000 AND 7f800000 gt 7f800000 AND 7f800000 gt 7fffffff AND 7f800000 gt 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#12: xvcmpgtsp. ffffffff gt ff800000 AND ffffffff gt c683287b AND ffffffff gt 80000000 AND ffffffff gt 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#13: xvcmpgtsp. ffffffff gt 00000000 AND ffffffff gt 7f800000 AND ffffffff gt 7fffffff AND ffffffff gt ffffffff ? cc=2 => 00000000 00000000 00000000 00000000
+#14: xvcmpgtsp. ffc00000 gt ff800000 AND ffc00000 gt c683287b AND ffc00000 gt 80000000 AND ffc00000 gt 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#15: xvcmpgtsp. 42780000 gt 42780000 AND 00000000 gt 00000000 AND 7f800000 gt 7f800000 AND 00000000 gt 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+
+
+#0: xvadddp fff0000000000000 + fff0000000000000 AND fff0000000000000 + c0d0650f5a07b353 => fff0000000000000 fff0000000000000
+#1: xvadddp 41232585a9900000 + 41382511a2000000 AND fff0000000000000 + 0000000000000000 => 4140dbea3b640000 fff0000000000000
+#2: xvadddp fff0000000000000 + 0123214569900000 AND fff0000000000000 + 7ff0000000000000 => fff0000000000000 7ff8000000000000
+#3: xvadddp fff0000000000000 + 7ff7ffffffffffff AND fff0000000000000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#4: xvadddp c0d0650f5a07b353 + fff0000000000000 AND c0d0650f5a07b353 + c0d0650f5a07b353 => fff0000000000000 c0e0650f5a07b353
+#5: xvadddp c0d0650f5a07b353 + 8000000000000000 AND c0d0650f5a07b353 + 0000000000000000 => c0d0650f5a07b353 c0d0650f5a07b353
+#6: xvadddp c0d0650f5a07b353 + 0123214569900000 AND c0d0650f5a07b353 + 7ff0000000000000 => c0d0650f5a07b353 7ff0000000000000
+#7: xvadddp c0d0650f5a07b353 + 7ff7ffffffffffff AND c0d0650f5a07b353 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#8: xvadddp 8000000000000000 + fff0000000000000 AND 8000000000000000 + c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#9: xvadddp 8000000000000000 + 8000000000000000 AND 8000000000000000 + 0000000000000000 => 8000000000000000 0000000000000000
+#10: xvadddp 8000000000000000 + 0123214569900000 AND 8000000000000000 + 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#11: xvadddp 8000000000000000 + 7ff7ffffffffffff AND 8000000000000000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#12: xvadddp 0000000000000000 + fff0000000000000 AND 0000000000000000 + c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#13: xvadddp 0000000000000000 + 8000000000000000 AND 0000000000000000 + 0000000000000000 => 0000000000000000 0000000000000000
+#14: xvadddp 0000000000000000 + 0123214569900000 AND 0000000000000000 + 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#15: xvadddp 0000000000000000 + 7ff7ffffffffffff AND 0000000000000000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#16: xvadddp 0123214569900000 + fff0000000000000 AND 0123214569900000 + c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#17: xvadddp 0123214569900000 + 8000000000000000 AND 0123214569900000 + 0000000000000000 => 0123214569900000 0123214569900000
+#18: xvadddp 0123214569900000 + 404f000000000000 AND 0123214569900000 + 7ff0000000000000 => 404f000000000000 7ff0000000000000
+#19: xvadddp 0123214569900000 + 7ff7ffffffffffff AND 0123214569900000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#20: xvadddp 7ff0000000000000 + fff0000000000000 AND 7ff0000000000000 + c0d0650f5a07b353 => 7ff8000000000000 7ff0000000000000
+#21: xvadddp 7ff0000000000000 + 8000000000000000 AND 7ff0000000000000 + 0000000000000000 => 7ff0000000000000 7ff0000000000000
+#22: xvadddp 7ff0000000000000 + 0123214569900000 AND 7ff0000000000000 + 7ff0000000000000 => 7ff0000000000000 7ff0000000000000
+#23: xvadddp 7ff0000000000000 + 7ff7ffffffffffff AND 7ff0000000000000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#24: xvadddp fff7ffffffffffff + fff0000000000000 AND fff7ffffffffffff + c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvadddp fff8000000000000 + 8000000000000000 AND fff8000000000000 + 0000000000000000 => fff8000000000000 fff8000000000000
+#26: xvadddp fff7ffffffffffff + 0123214569900000 AND fff7ffffffffffff + 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvadddp fff7ffffffffffff + 7ff7ffffffffffff AND fff7ffffffffffff + 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvadddp fff8000000000000 + fff0000000000000 AND fff8000000000000 + c0d0650f5a07b353 => fff8000000000000 fff8000000000000
+#29: xvadddp fff8000000000000 + 8000000000000000 AND 41232585a9900000 + 41382511a2000000 => fff8000000000000 4140dbea3b640000
+#30: xvadddp 41232585a9900000 + 41382511a2000000 AND 7ff7ffffffffffff + 7ff8000000000000 => 4140dbea3b640000 7fffffffffffffff
+#31: xvadddp 7ff8000000000000 + 7ff8000000000000 AND 7ff8000000000000 + fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvaddsp ff800000 + ff800000 AND ff800000 + c683287b AND 49192c2d + 49c1288d AND ff800000 + 00000000 => ff800000 ff800000 4a06df52 ff800000
+#1: xvaddsp ff800000 + 00000000 AND ff800000 + 7f800000 AND ff800000 + 7fffffff AND ff800000 + 7fc00000 => ff800000 7fc00000 7fffffff 7fc00000
+#2: xvaddsp c683287b + ff800000 AND c683287b + c683287b AND c683287b + 80000000 AND c683287b + 00000000 => ff800000 c703287b c683287b c683287b
+#3: xvaddsp c683287b + 00000000 AND c683287b + 7f800000 AND c683287b + 7fffffff AND c683287b + 7fc00000 => c683287b 7f800000 7fffffff 7fc00000
+#4: xvaddsp 80000000 + ff800000 AND 80000000 + c683287b AND 80000000 + 80000000 AND 80000000 + 00000000 => ff800000 c683287b 80000000 00000000
+#5: xvaddsp 80000000 + 00000000 AND 80000000 + 7f800000 AND 80000000 + 7fffffff AND 80000000 + 7fc00000 => 00000000 7f800000 7fffffff 7fc00000
+#6: xvaddsp 00000000 + ff800000 AND 00000000 + c683287b AND 00000000 + 80000000 AND 00000000 + 00000000 => ff800000 c683287b 00000000 00000000
+#7: xvaddsp 00000000 + 00000000 AND 00000000 + 7f800000 AND 00000000 + 7fffffff AND 00000000 + 7fc00000 => 00000000 7f800000 7fffffff 7fc00000
+#8: xvaddsp 00000000 + ff800000 AND 00000000 + c683287b AND 00000000 + 80000000 AND 00000000 + 00000000 => ff800000 c683287b 00000000 00000000
+#9: xvaddsp 00000000 + 42780000 AND 00000000 + 7f800000 AND 00000000 + 7fffffff AND 00000000 + 7fc00000 => 42780000 7f800000 7fffffff 7fc00000
+#10: xvaddsp 7f800000 + ff800000 AND 7f800000 + c683287b AND 7f800000 + 80000000 AND 7f800000 + 00000000 => 7fc00000 7f800000 7f800000 7f800000
+#11: xvaddsp 7f800000 + 00000000 AND 7f800000 + 7f800000 AND 7f800000 + 7fffffff AND 7f800000 + 7fc00000 => 7f800000 7f800000 7fffffff 7fc00000
+#12: xvaddsp ffffffff + ff800000 AND ffffffff + c683287b AND ffc00000 + 80000000 AND ffc00000 + 00000000 => ffffffff ffffffff ffc00000 ffc00000
+#13: xvaddsp ffffffff + 00000000 AND ffffffff + 7f800000 AND ffffffff + 7fffffff AND ffffffff + 7fc00000 => ffffffff ffffffff ffffffff ffffffff
+#14: xvaddsp ffc00000 + ff800000 AND ffc00000 + c683287b AND ffc00000 + 80000000 AND 49192c2d + 49c1288d => ffc00000 ffc00000 ffc00000 4a06df52
+#15: xvaddsp 49192c2d + 49c1288d AND 7fffffff + 7fc00000 AND 7fc00000 + 7fc00000 AND 7fc00000 + ffc00000 => 4a06df52 7fffffff 7fc00000 7fc00000
+
+
+#0: xvdivdp fff0000000000000 / fff0000000000000 AND fff0000000000000 / c0d0650f5a07b353 => 7ff8000000000000 7ff0000000000000
+#1: xvdivdp 41232585a9900000 / 41382511a2000000 AND fff0000000000000 / 0000000000000000 => 3fd9602b4fe7a892 fff0000000000000
+#2: xvdivdp fff0000000000000 / 0123214569900000 AND fff0000000000000 / 7ff0000000000000 => fff0000000000000 7ff8000000000000
+#3: xvdivdp fff0000000000000 / 7ff7ffffffffffff AND fff0000000000000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#4: xvdivdp c0d0650f5a07b353 / fff0000000000000 AND c0d0650f5a07b353 / c0d0650f5a07b353 => 0000000000000000 3ff0000000000000
+#5: xvdivdp c0d0650f5a07b353 / 8000000000000000 AND c0d0650f5a07b353 / 0000000000000000 => 7ff0000000000000 fff0000000000000
+#6: xvdivdp c0d0650f5a07b353 / 0123214569900000 AND c0d0650f5a07b353 / 7ff0000000000000 => ff9b6cb57ca13c00 8000000000000000
+#7: xvdivdp c0d0650f5a07b353 / 7ff7ffffffffffff AND c0d0650f5a07b353 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#8: xvdivdp 8000000000000000 / fff0000000000000 AND 8000000000000000 / c0d0650f5a07b353 => 0000000000000000 0000000000000000
+#9: xvdivdp 8000000000000000 / 8000000000000000 AND 8000000000000000 / 0000000000000000 => 7ff8000000000000 7ff8000000000000
+#10: xvdivdp 8000000000000000 / 0123214569900000 AND 8000000000000000 / 7ff0000000000000 => 8000000000000000 8000000000000000
+#11: xvdivdp 8000000000000000 / 7ff7ffffffffffff AND 8000000000000000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#12: xvdivdp 0000000000000000 / fff0000000000000 AND 0000000000000000 / c0d0650f5a07b353 => 8000000000000000 8000000000000000
+#13: xvdivdp 0000000000000000 / 8000000000000000 AND 0000000000000000 / 0000000000000000 => 7ff8000000000000 7ff8000000000000
+#14: xvdivdp 0000000000000000 / 0123214569900000 AND 0000000000000000 / 7ff0000000000000 => 0000000000000000 0000000000000000
+#15: xvdivdp 0000000000000000 / 7ff7ffffffffffff AND 0000000000000000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#16: xvdivdp 0123214569900000 / fff0000000000000 AND 0123214569900000 / c0d0650f5a07b353 => 8000000000000000 8042ab59d8b6ec87
+#17: xvdivdp 0123214569900000 / 8000000000000000 AND 0123214569900000 / 0000000000000000 => fff0000000000000 7ff0000000000000
+#18: xvdivdp 0123214569900000 / 404f000000000000 AND 0123214569900000 / 7ff0000000000000 => 00c3bf3f64b5ad6b 0000000000000000
+#19: xvdivdp 0123214569900000 / 7ff7ffffffffffff AND 0123214569900000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#20: xvdivdp 7ff0000000000000 / fff0000000000000 AND 7ff0000000000000 / c0d0650f5a07b353 => 7ff8000000000000 fff0000000000000
+#21: xvdivdp 7ff0000000000000 / 8000000000000000 AND 7ff0000000000000 / 0000000000000000 => fff0000000000000 7ff0000000000000
+#22: xvdivdp 7ff0000000000000 / 0123214569900000 AND 7ff0000000000000 / 7ff0000000000000 => 7ff0000000000000 7ff8000000000000
+#23: xvdivdp 7ff0000000000000 / 7ff7ffffffffffff AND 7ff0000000000000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#24: xvdivdp fff7ffffffffffff / fff0000000000000 AND fff7ffffffffffff / c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvdivdp fff8000000000000 / 8000000000000000 AND fff8000000000000 / 0000000000000000 => fff8000000000000 fff8000000000000
+#26: xvdivdp fff7ffffffffffff / 0123214569900000 AND fff7ffffffffffff / 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvdivdp fff7ffffffffffff / 7ff7ffffffffffff AND fff7ffffffffffff / 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvdivdp fff8000000000000 / fff0000000000000 AND fff8000000000000 / c0d0650f5a07b353 => fff8000000000000 fff8000000000000
+#29: xvdivdp fff8000000000000 / 8000000000000000 AND 41232585a9900000 / 41382511a2000000 => fff8000000000000 3fd9602b4fe7a892
+#30: xvdivdp 41232585a9900000 / 41382511a2000000 AND 7ff7ffffffffffff / 7ff8000000000000 => 3fd9602b4fe7a892 7fffffffffffffff
+#31: xvdivdp 7ff8000000000000 / 7ff8000000000000 AND 7ff8000000000000 / fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvdivsp ff800000 / ff800000 AND ff800000 / c683287b AND 49192c2d / 49c1288d AND ff800000 / 00000000 => 7fc00000 7f800000 3ecb015a ff800000
+#1: xvdivsp ff800000 / 00000000 AND ff800000 / 7f800000 AND ff800000 / 7fffffff AND ff800000 / 7fc00000 => ff800000 7fc00000 7fffffff 7fc00000
+#2: xvdivsp c683287b / ff800000 AND c683287b / c683287b AND c683287b / 80000000 AND c683287b / 00000000 => 00000000 3f800000 7f800000 ff800000
+#3: xvdivsp c683287b / 00000000 AND c683287b / 7f800000 AND c683287b / 7fffffff AND c683287b / 7fc00000 => ff800000 80000000 7fffffff 7fc00000
+#4: xvdivsp 80000000 / ff800000 AND 80000000 / c683287b AND 80000000 / 80000000 AND 80000000 / 00000000 => 00000000 00000000 7fc00000 7fc00000
+#5: xvdivsp 80000000 / 00000000 AND 80000000 / 7f800000 AND 80000000 / 7fffffff AND 80000000 / 7fc00000 => 7fc00000 80000000 7fffffff 7fc00000
+#6: xvdivsp 00000000 / ff800000 AND 00000000 / c683287b AND 00000000 / 80000000 AND 00000000 / 00000000 => 80000000 80000000 7fc00000 7fc00000
+#7: xvdivsp 00000000 / 00000000 AND 00000000 / 7f800000 AND 00000000 / 7fffffff AND 00000000 / 7fc00000 => 7fc00000 00000000 7fffffff 7fc00000
+#8: xvdivsp 00000000 / ff800000 AND 00000000 / c683287b AND 00000000 / 80000000 AND 00000000 / 00000000 => 80000000 80000000 7fc00000 7fc00000
+#9: xvdivsp 00000000 / 42780000 AND 00000000 / 7f800000 AND 00000000 / 7fffffff AND 00000000 / 7fc00000 => 00000000 00000000 7fffffff 7fc00000
+#10: xvdivsp 7f800000 / ff800000 AND 7f800000 / c683287b AND 7f800000 / 80000000 AND 7f800000 / 00000000 => 7fc00000 ff800000 ff800000 7f800000
+#11: xvdivsp 7f800000 / 00000000 AND 7f800000 / 7f800000 AND 7f800000 / 7fffffff AND 7f800000 / 7fc00000 => 7f800000 7fc00000 7fffffff 7fc00000
+#12: xvdivsp ffffffff / ff800000 AND ffffffff / c683287b AND ffc00000 / 80000000 AND ffc00000 / 00000000 => ffffffff ffffffff ffc00000 ffc00000
+#13: xvdivsp ffffffff / 00000000 AND ffffffff / 7f800000 AND ffffffff / 7fffffff AND ffffffff / 7fc00000 => ffffffff ffffffff ffffffff ffffffff
+#14: xvdivsp ffc00000 / ff800000 AND ffc00000 / c683287b AND ffc00000 / 80000000 AND 49192c2d / 49c1288d => ffc00000 ffc00000 ffc00000 3ecb015a
+#15: xvdivsp 49192c2d / 49c1288d AND 7fffffff / 7fc00000 AND 7fc00000 / 7fc00000 AND 7fc00000 / ffc00000 => 3ecb015a 7fffffff 7fc00000 7fc00000
+
+
+#0: xvmuldp fff0000000000000 * fff0000000000000 AND fff0000000000000 * c0d0650f5a07b353 => 7ff0000000000000 7ff0000000000000
+#1: xvmuldp 41232585a9900000 * 41382511a2000000 AND fff0000000000000 * 0000000000000000 => 426ce4a45d2a0a7e 7ff8000000000000
+#2: xvmuldp fff0000000000000 * 0123214569900000 AND fff0000000000000 * 7ff0000000000000 => fff0000000000000 fff0000000000000
+#3: xvmuldp fff0000000000000 * 7ff7ffffffffffff AND fff0000000000000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#4: xvmuldp c0d0650f5a07b353 * fff0000000000000 AND c0d0650f5a07b353 * c0d0650f5a07b353 => 7ff0000000000000 41b0cc9d05eec2a7
+#5: xvmuldp c0d0650f5a07b353 * 8000000000000000 AND c0d0650f5a07b353 * 0000000000000000 => 0000000000000000 8000000000000000
+#6: xvmuldp c0d0650f5a07b353 * 0123214569900000 AND c0d0650f5a07b353 * 7ff0000000000000 => 82039a19ca8fcb5f fff0000000000000
+#7: xvmuldp c0d0650f5a07b353 * 7ff7ffffffffffff AND c0d0650f5a07b353 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#8: xvmuldp 8000000000000000 * fff0000000000000 AND 8000000000000000 * c0d0650f5a07b353 => 7ff8000000000000 0000000000000000
+#9: xvmuldp 8000000000000000 * 8000000000000000 AND 8000000000000000 * 0000000000000000 => 0000000000000000 8000000000000000
+#10: xvmuldp 8000000000000000 * 0123214569900000 AND 8000000000000000 * 7ff0000000000000 => 8000000000000000 7ff8000000000000
+#11: xvmuldp 8000000000000000 * 7ff7ffffffffffff AND 8000000000000000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#12: xvmuldp 0000000000000000 * fff0000000000000 AND 0000000000000000 * c0d0650f5a07b353 => 7ff8000000000000 8000000000000000
+#13: xvmuldp 0000000000000000 * 8000000000000000 AND 0000000000000000 * 0000000000000000 => 8000000000000000 0000000000000000
+#14: xvmuldp 0000000000000000 * 0123214569900000 AND 0000000000000000 * 7ff0000000000000 => 0000000000000000 7ff8000000000000
+#15: xvmuldp 0000000000000000 * 7ff7ffffffffffff AND 0000000000000000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#16: xvmuldp 0123214569900000 * fff0000000000000 AND 0123214569900000 * c0d0650f5a07b353 => fff0000000000000 82039a19ca8fcb5f
+#17: xvmuldp 0123214569900000 * 8000000000000000 AND 0123214569900000 * 0000000000000000 => 8000000000000000 0000000000000000
+#18: xvmuldp 0123214569900000 * 404f000000000000 AND 0123214569900000 * 7ff0000000000000 => 0182883b3e438000 7ff0000000000000
+#19: xvmuldp 0123214569900000 * 7ff7ffffffffffff AND 0123214569900000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#20: xvmuldp 7ff0000000000000 * fff0000000000000 AND 7ff0000000000000 * c0d0650f5a07b353 => fff0000000000000 fff0000000000000
+#21: xvmuldp 7ff0000000000000 * 8000000000000000 AND 7ff0000000000000 * 0000000000000000 => 7ff8000000000000 7ff8000000000000
+#22: xvmuldp 7ff0000000000000 * 0123214569900000 AND 7ff0000000000000 * 7ff0000000000000 => 7ff0000000000000 7ff0000000000000
+#23: xvmuldp 7ff0000000000000 * 7ff7ffffffffffff AND 7ff0000000000000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#24: xvmuldp fff7ffffffffffff * fff0000000000000 AND fff7ffffffffffff * c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvmuldp fff8000000000000 * 8000000000000000 AND fff8000000000000 * 0000000000000000 => fff8000000000000 fff8000000000000
+#26: xvmuldp fff7ffffffffffff * 0123214569900000 AND fff7ffffffffffff * 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvmuldp fff7ffffffffffff * 7ff7ffffffffffff AND fff7ffffffffffff * 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvmuldp fff8000000000000 * fff0000000000000 AND fff8000000000000 * c0d0650f5a07b353 => fff8000000000000 fff8000000000000
+#29: xvmuldp fff8000000000000 * 8000000000000000 AND 41232585a9900000 * 41382511a2000000 => fff8000000000000 426ce4a45d2a0a7e
+#30: xvmuldp 41232585a9900000 * 41382511a2000000 AND 7ff7ffffffffffff * 7ff8000000000000 => 426ce4a45d2a0a7e 7fffffffffffffff
+#31: xvmuldp 7ff8000000000000 * 7ff8000000000000 AND 7ff8000000000000 * fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvmulsp ff800000 * ff800000 AND ff800000 * c683287b AND 49192c2d * 49c1288d AND ff800000 * 00000000 => 7f800000 7f800000 53672522 7fc00000
+#1: xvmulsp ff800000 * 00000000 AND ff800000 * 7f800000 AND ff800000 * 7fffffff AND ff800000 * 7fc00000 => 7fc00000 ff800000 7fffffff 7fc00000
+#2: xvmulsp c683287b * ff800000 AND c683287b * c683287b AND c683287b * 80000000 AND c683287b * 00000000 => 7f800000 4d8664e9 00000000 80000000
+#3: xvmulsp c683287b * 00000000 AND c683287b * 7f800000 AND c683287b * 7fffffff AND c683287b * 7fc00000 => 80000000 ff800000 7fffffff 7fc00000
+#4: xvmulsp 80000000 * ff800000 AND 80000000 * c683287b AND 80000000 * 80000000 AND 80000000 * 00000000 => 7fc00000 00000000 00000000 80000000
+#5: xvmulsp 80000000 * 00000000 AND 80000000 * 7f800000 AND 80000000 * 7fffffff AND 80000000 * 7fc00000 => 80000000 7fc00000 7fffffff 7fc00000
+#6: xvmulsp 00000000 * ff800000 AND 00000000 * c683287b AND 00000000 * 80000000 AND 00000000 * 00000000 => 7fc00000 80000000 80000000 00000000
+#7: xvmulsp 00000000 * 00000000 AND 00000000 * 7f800000 AND 00000000 * 7fffffff AND 00000000 * 7fc00000 => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmulsp 00000000 * ff800000 AND 00000000 * c683287b AND 00000000 * 80000000 AND 00000000 * 00000000 => 7fc00000 80000000 80000000 00000000
+#9: xvmulsp 00000000 * 42780000 AND 00000000 * 7f800000 AND 00000000 * 7fffffff AND 00000000 * 7fc00000 => 00000000 7fc00000 7fffffff 7fc00000
+#10: xvmulsp 7f800000 * ff800000 AND 7f800000 * c683287b AND 7f800000 * 80000000 AND 7f800000 * 00000000 => ff800000 ff800000 7fc00000 7fc00000
+#11: xvmulsp 7f800000 * 00000000 AND 7f800000 * 7f800000 AND 7f800000 * 7fffffff AND 7f800000 * 7fc00000 => 7fc00000 7f800000 7fffffff 7fc00000
+#12: xvmulsp ffffffff * ff800000 AND ffffffff * c683287b AND ffc00000 * 80000000 AND ffc00000 * 00000000 => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmulsp ffffffff * 00000000 AND ffffffff * 7f800000 AND ffffffff * 7fffffff AND ffffffff * 7fc00000 => ffffffff ffffffff ffffffff ffffffff
+#14: xvmulsp ffc00000 * ff800000 AND ffc00000 * c683287b AND ffc00000 * 80000000 AND 49192c2d * 49c1288d => ffc00000 ffc00000 ffc00000 53672522
+#15: xvmulsp 49192c2d * 49c1288d AND 7fffffff * 7fc00000 AND 7fc00000 * 7fc00000 AND 7fc00000 * ffc00000 => 53672522 7fffffff 7fc00000 7fc00000
+
+
+#0: xvsubdp fff0000000000000 - fff0000000000000 AND fff0000000000000 - c0d0650f5a07b353 => 7ff8000000000000 fff0000000000000
+#1: xvsubdp 41232585a9900000 - 41382511a2000000 AND fff0000000000000 - 0000000000000000 => c12d249d9a700000 fff0000000000000
+#2: xvsubdp fff0000000000000 - 0123214569900000 AND fff0000000000000 - 7ff0000000000000 => fff0000000000000 fff0000000000000
+#3: xvsubdp fff0000000000000 - 7ff7ffffffffffff AND fff0000000000000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#4: xvsubdp c0d0650f5a07b353 - fff0000000000000 AND c0d0650f5a07b353 - c0d0650f5a07b353 => 7ff0000000000000 0000000000000000
+#5: xvsubdp c0d0650f5a07b353 - 8000000000000000 AND c0d0650f5a07b353 - 0000000000000000 => c0d0650f5a07b353 c0d0650f5a07b353
+#6: xvsubdp c0d0650f5a07b353 - 0123214569900000 AND c0d0650f5a07b353 - 7ff0000000000000 => c0d0650f5a07b353 fff0000000000000
+#7: xvsubdp c0d0650f5a07b353 - 7ff7ffffffffffff AND c0d0650f5a07b353 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#8: xvsubdp 8000000000000000 - fff0000000000000 AND 8000000000000000 - c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#9: xvsubdp 8000000000000000 - 8000000000000000 AND 8000000000000000 - 0000000000000000 => 0000000000000000 8000000000000000
+#10: xvsubdp 8000000000000000 - 0123214569900000 AND 8000000000000000 - 7ff0000000000000 => 8123214569900000 fff0000000000000
+#11: xvsubdp 8000000000000000 - 7ff7ffffffffffff AND 8000000000000000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#12: xvsubdp 0000000000000000 - fff0000000000000 AND 0000000000000000 - c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#13: xvsubdp 0000000000000000 - 8000000000000000 AND 0000000000000000 - 0000000000000000 => 0000000000000000 0000000000000000
+#14: xvsubdp 0000000000000000 - 0123214569900000 AND 0000000000000000 - 7ff0000000000000 => 8123214569900000 fff0000000000000
+#15: xvsubdp 0000000000000000 - 7ff7ffffffffffff AND 0000000000000000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#16: xvsubdp 0123214569900000 - fff0000000000000 AND 0123214569900000 - c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#17: xvsubdp 0123214569900000 - 8000000000000000 AND 0123214569900000 - 0000000000000000 => 0123214569900000 0123214569900000
+#18: xvsubdp 0123214569900000 - 404f000000000000 AND 0123214569900000 - 7ff0000000000000 => c04f000000000000 fff0000000000000
+#19: xvsubdp 0123214569900000 - 7ff7ffffffffffff AND 0123214569900000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#20: xvsubdp 7ff0000000000000 - fff0000000000000 AND 7ff0000000000000 - c0d0650f5a07b353 => 7ff0000000000000 7ff0000000000000
+#21: xvsubdp 7ff0000000000000 - 8000000000000000 AND 7ff0000000000000 - 0000000000000000 => 7ff0000000000000 7ff0000000000000
+#22: xvsubdp 7ff0000000000000 - 0123214569900000 AND 7ff0000000000000 - 7ff0000000000000 => 7ff0000000000000 7ff8000000000000
+#23: xvsubdp 7ff0000000000000 - 7ff7ffffffffffff AND 7ff0000000000000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#24: xvsubdp fff7ffffffffffff - fff0000000000000 AND fff7ffffffffffff - c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvsubdp fff8000000000000 - 8000000000000000 AND fff8000000000000 - 0000000000000000 => fff8000000000000 fff8000000000000
+#26: xvsubdp fff7ffffffffffff - 0123214569900000 AND fff7ffffffffffff - 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvsubdp fff7ffffffffffff - 7ff7ffffffffffff AND fff7ffffffffffff - 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvsubdp fff8000000000000 - fff0000000000000 AND fff8000000000000 - c0d0650f5a07b353 => fff8000000000000 fff8000000000000
+#29: xvsubdp fff8000000000000 - 8000000000000000 AND 41232585a9900000 - 41382511a2000000 => fff8000000000000 c12d249d9a700000
+#30: xvsubdp 41232585a9900000 - 41382511a2000000 AND 7ff7ffffffffffff - 7ff8000000000000 => c12d249d9a700000 7fffffffffffffff
+#31: xvsubdp 7ff8000000000000 - 7ff8000000000000 AND 7ff8000000000000 - fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvsubsp ff800000 - ff800000 AND ff800000 - c683287b AND 49192c2d - 49c1288d AND ff800000 - 00000000 => 7fc00000 ff800000 c96924ed ff800000
+#1: xvsubsp ff800000 - 00000000 AND ff800000 - 7f800000 AND ff800000 - 7fffffff AND ff800000 - 7fc00000 => ff800000 ff800000 7fffffff 7fc00000
+#2: xvsubsp c683287b - ff800000 AND c683287b - c683287b AND c683287b - 80000000 AND c683287b - 00000000 => 7f800000 00000000 c683287b c683287b
+#3: xvsubsp c683287b - 00000000 AND c683287b - 7f800000 AND c683287b - 7fffffff AND c683287b - 7fc00000 => c683287b ff800000 7fffffff 7fc00000
+#4: xvsubsp 80000000 - ff800000 AND 80000000 - c683287b AND 80000000 - 80000000 AND 80000000 - 00000000 => 7f800000 4683287b 00000000 80000000
+#5: xvsubsp 80000000 - 00000000 AND 80000000 - 7f800000 AND 80000000 - 7fffffff AND 80000000 - 7fc00000 => 80000000 ff800000 7fffffff 7fc00000
+#6: xvsubsp 00000000 - ff800000 AND 00000000 - c683287b AND 00000000 - 80000000 AND 00000000 - 00000000 => 7f800000 4683287b 00000000 00000000
+#7: xvsubsp 00000000 - 00000000 AND 00000000 - 7f800000 AND 00000000 - 7fffffff AND 00000000 - 7fc00000 => 00000000 ff800000 7fffffff 7fc00000
+#8: xvsubsp 00000000 - ff800000 AND 00000000 - c683287b AND 00000000 - 80000000 AND 00000000 - 00000000 => 7f800000 4683287b 00000000 00000000
+#9: xvsubsp 00000000 - 42780000 AND 00000000 - 7f800000 AND 00000000 - 7fffffff AND 00000000 - 7fc00000 => c2780000 ff800000 7fffffff 7fc00000
+#10: xvsubsp 7f800000 - ff800000 AND 7f800000 - c683287b AND 7f800000 - 80000000 AND 7f800000 - 00000000 => 7f800000 7f800000 7f800000 7f800000
+#11: xvsubsp 7f800000 - 00000000 AND 7f800000 - 7f800000 AND 7f800000 - 7fffffff AND 7f800000 - 7fc00000 => 7f800000 7fc00000 7fffffff 7fc00000
+#12: xvsubsp ffffffff - ff800000 AND ffffffff - c683287b AND ffc00000 - 80000000 AND ffc00000 - 00000000 => ffffffff ffffffff ffc00000 ffc00000
+#13: xvsubsp ffffffff - 00000000 AND ffffffff - 7f800000 AND ffffffff - 7fffffff AND ffffffff - 7fc00000 => ffffffff ffffffff ffffffff ffffffff
+#14: xvsubsp ffc00000 - ff800000 AND ffc00000 - c683287b AND ffc00000 - 80000000 AND 49192c2d - 49c1288d => ffc00000 ffc00000 ffc00000 c96924ed
+#15: xvsubsp 49192c2d - 49c1288d AND 7fffffff - 7fc00000 AND 7fc00000 - 7fc00000 AND 7fc00000 - ffc00000 => c96924ed 7fffffff 7fc00000 7fc00000
+
+
+#0: xvmaxdp fff0000000000000 @max@ fff0000000000000 AND fff0000000000000 @max@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#1: xvmaxdp 41232585a9900000 @max@ 41382511a2000000 AND fff0000000000000 @max@ 0000000000000000 => 41382511a2000000 0000000000000000
+#2: xvmaxdp fff0000000000000 @max@ 0123214569900000 AND fff0000000000000 @max@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#3: xvmaxdp fff0000000000000 @max@ 7ff7ffffffffffff AND fff0000000000000 @max@ 7ff8000000000000 => 7fffffffffffffff fff0000000000000
+#4: xvmaxdp c0d0650f5a07b353 @max@ fff0000000000000 AND c0d0650f5a07b353 @max@ c0d0650f5a07b353 => c0d0650f5a07b353 c0d0650f5a07b353
+#5: xvmaxdp c0d0650f5a07b353 @max@ 8000000000000000 AND c0d0650f5a07b353 @max@ 0000000000000000 => 8000000000000000 0000000000000000
+#6: xvmaxdp c0d0650f5a07b353 @max@ 0123214569900000 AND c0d0650f5a07b353 @max@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#7: xvmaxdp c0d0650f5a07b353 @max@ 7ff7ffffffffffff AND c0d0650f5a07b353 @max@ 7ff8000000000000 => 7fffffffffffffff c0d0650f5a07b353
+#8: xvmaxdp 8000000000000000 @max@ fff0000000000000 AND 8000000000000000 @max@ c0d0650f5a07b353 => 8000000000000000 8000000000000000
+#9: xvmaxdp 8000000000000000 @max@ 8000000000000000 AND 8000000000000000 @max@ 0000000000000000 => 8000000000000000 0000000000000000
+#10: xvmaxdp 8000000000000000 @max@ 0123214569900000 AND 8000000000000000 @max@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#11: xvmaxdp 8000000000000000 @max@ 7ff7ffffffffffff AND 8000000000000000 @max@ 7ff8000000000000 => 7fffffffffffffff 8000000000000000
+#12: xvmaxdp 0000000000000000 @max@ fff0000000000000 AND 0000000000000000 @max@ c0d0650f5a07b353 => 0000000000000000 0000000000000000
+#13: xvmaxdp 0000000000000000 @max@ 8000000000000000 AND 0000000000000000 @max@ 0000000000000000 => 0000000000000000 0000000000000000
+#14: xvmaxdp 0000000000000000 @max@ 0123214569900000 AND 0000000000000000 @max@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#15: xvmaxdp 0000000000000000 @max@ 7ff7ffffffffffff AND 0000000000000000 @max@ 7ff8000000000000 => 7fffffffffffffff 0000000000000000
+#16: xvmaxdp 0123214569900000 @max@ fff0000000000000 AND 0123214569900000 @max@ c0d0650f5a07b353 => 0123214569900000 0123214569900000
+#17: xvmaxdp 0123214569900000 @max@ 8000000000000000 AND 0123214569900000 @max@ 0000000000000000 => 0123214569900000 0123214569900000
+#18: xvmaxdp 0123214569900000 @max@ 404f000000000000 AND 0123214569900000 @max@ 7ff0000000000000 => 404f000000000000 7ff0000000000000
+#19: xvmaxdp 0123214569900000 @max@ 7ff7ffffffffffff AND 0123214569900000 @max@ 7ff8000000000000 => 7fffffffffffffff 0123214569900000
+#20: xvmaxdp 7ff0000000000000 @max@ fff0000000000000 AND 7ff0000000000000 @max@ c0d0650f5a07b353 => 7ff0000000000000 7ff0000000000000
+#21: xvmaxdp 7ff0000000000000 @max@ 8000000000000000 AND 7ff0000000000000 @max@ 0000000000000000 => 7ff0000000000000 7ff0000000000000
+#22: xvmaxdp 7ff0000000000000 @max@ 0123214569900000 AND 7ff0000000000000 @max@ 7ff0000000000000 => 7ff0000000000000 7ff0000000000000
+#23: xvmaxdp 7ff0000000000000 @max@ 7ff7ffffffffffff AND 7ff0000000000000 @max@ 7ff8000000000000 => 7fffffffffffffff 7ff0000000000000
+#24: xvmaxdp fff7ffffffffffff @max@ fff0000000000000 AND fff7ffffffffffff @max@ c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvmaxdp fff8000000000000 @max@ 8000000000000000 AND fff8000000000000 @max@ 0000000000000000 => 8000000000000000 0000000000000000
+#26: xvmaxdp fff7ffffffffffff @max@ 0123214569900000 AND fff7ffffffffffff @max@ 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvmaxdp fff7ffffffffffff @max@ 7ff7ffffffffffff AND fff7ffffffffffff @max@ 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvmaxdp fff8000000000000 @max@ fff0000000000000 AND fff8000000000000 @max@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#29: xvmaxdp fff8000000000000 @max@ 8000000000000000 AND 41232585a9900000 @max@ 41382511a2000000 => 8000000000000000 41382511a2000000
+#30: xvmaxdp 41232585a9900000 @max@ 41382511a2000000 AND 7ff7ffffffffffff @max@ 7ff8000000000000 => 41382511a2000000 7fffffffffffffff
+#31: xvmaxdp 7ff8000000000000 @max@ 7ff8000000000000 AND 7ff8000000000000 @max@ fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvmindp fff0000000000000 @min@ fff0000000000000 AND fff0000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 fff0000000000000
+#1: xvmindp 41232585a9900000 @min@ 41382511a2000000 AND fff0000000000000 @min@ 0000000000000000 => 41232585a9900000 fff0000000000000
+#2: xvmindp fff0000000000000 @min@ 0123214569900000 AND fff0000000000000 @min@ 7ff0000000000000 => fff0000000000000 fff0000000000000
+#3: xvmindp fff0000000000000 @min@ 7ff7ffffffffffff AND fff0000000000000 @min@ 7ff8000000000000 => 7fffffffffffffff fff0000000000000
+#4: xvmindp c0d0650f5a07b353 @min@ fff0000000000000 AND c0d0650f5a07b353 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#5: xvmindp c0d0650f5a07b353 @min@ 8000000000000000 AND c0d0650f5a07b353 @min@ 0000000000000000 => c0d0650f5a07b353 c0d0650f5a07b353
+#6: xvmindp c0d0650f5a07b353 @min@ 0123214569900000 AND c0d0650f5a07b353 @min@ 7ff0000000000000 => c0d0650f5a07b353 c0d0650f5a07b353
+#7: xvmindp c0d0650f5a07b353 @min@ 7ff7ffffffffffff AND c0d0650f5a07b353 @min@ 7ff8000000000000 => 7fffffffffffffff c0d0650f5a07b353
+#8: xvmindp 8000000000000000 @min@ fff0000000000000 AND 8000000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#9: xvmindp 8000000000000000 @min@ 8000000000000000 AND 8000000000000000 @min@ 0000000000000000 => 8000000000000000 8000000000000000
+#10: xvmindp 8000000000000000 @min@ 0123214569900000 AND 8000000000000000 @min@ 7ff0000000000000 => 8000000000000000 8000000000000000
+#11: xvmindp 8000000000000000 @min@ 7ff7ffffffffffff AND 8000000000000000 @min@ 7ff8000000000000 => 7fffffffffffffff 8000000000000000
+#12: xvmindp 0000000000000000 @min@ fff0000000000000 AND 0000000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#13: xvmindp 0000000000000000 @min@ 8000000000000000 AND 0000000000000000 @min@ 0000000000000000 => 8000000000000000 0000000000000000
+#14: xvmindp 0000000000000000 @min@ 0123214569900000 AND 0000000000000000 @min@ 7ff0000000000000 => 0000000000000000 0000000000000000
+#15: xvmindp 0000000000000000 @min@ 7ff7ffffffffffff AND 0000000000000000 @min@ 7ff8000000000000 => 7fffffffffffffff 0000000000000000
+#16: xvmindp 0123214569900000 @min@ fff0000000000000 AND 0123214569900000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#17: xvmindp 0123214569900000 @min@ 8000000000000000 AND 0123214569900000 @min@ 0000000000000000 => 8000000000000000 0000000000000000
+#18: xvmindp 0123214569900000 @min@ 404f000000000000 AND 0123214569900000 @min@ 7ff0000000000000 => 0123214569900000 0123214569900000
+#19: xvmindp 0123214569900000 @min@ 7ff7ffffffffffff AND 0123214569900000 @min@ 7ff8000000000000 => 7fffffffffffffff 0123214569900000
+#20: xvmindp 7ff0000000000000 @min@ fff0000000000000 AND 7ff0000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#21: xvmindp 7ff0000000000000 @min@ 8000000000000000 AND 7ff0000000000000 @min@ 0000000000000000 => 8000000000000000 0000000000000000
+#22: xvmindp 7ff0000000000000 @min@ 0123214569900000 AND 7ff0000000000000 @min@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#23: xvmindp 7ff0000000000000 @min@ 7ff7ffffffffffff AND 7ff0000000000000 @min@ 7ff8000000000000 => 7fffffffffffffff 7ff0000000000000
+#24: xvmindp fff7ffffffffffff @min@ fff0000000000000 AND fff7ffffffffffff @min@ c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvmindp fff8000000000000 @min@ 8000000000000000 AND fff8000000000000 @min@ 0000000000000000 => 8000000000000000 0000000000000000
+#26: xvmindp fff7ffffffffffff @min@ 0123214569900000 AND fff7ffffffffffff @min@ 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvmindp fff7ffffffffffff @min@ 7ff7ffffffffffff AND fff7ffffffffffff @min@ 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvmindp fff8000000000000 @min@ fff0000000000000 AND fff8000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#29: xvmindp fff8000000000000 @min@ 8000000000000000 AND 41232585a9900000 @min@ 41382511a2000000 => 8000000000000000 41232585a9900000
+#30: xvmindp 41232585a9900000 @min@ 41382511a2000000 AND 7ff7ffffffffffff @min@ 7ff8000000000000 => 41232585a9900000 7fffffffffffffff
+#31: xvmindp 7ff8000000000000 @min@ 7ff8000000000000 AND 7ff8000000000000 @min@ fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvmaxsp ff800000 @max@ ff800000 AND ff800000 @max@ c683287b AND 49192c2d @max@ 49c1288d AND ff800000 @max@ 00000000 => ff800000 c683287b 49c1288d 00000000
+#1: xvmaxsp ff800000 @max@ 00000000 AND ff800000 @max@ 7f800000 AND ff800000 @max@ 7fffffff AND ff800000 @max@ 7fc00000 => 00000000 7f800000 ff800000 ff800000
+#2: xvmaxsp c683287b @max@ ff800000 AND c683287b @max@ c683287b AND c683287b @max@ 80000000 AND c683287b @max@ 00000000 => c683287b c683287b 80000000 00000000
+#3: xvmaxsp c683287b @max@ 00000000 AND c683287b @max@ 7f800000 AND c683287b @max@ 7fffffff AND c683287b @max@ 7fc00000 => 00000000 7f800000 c683287b c683287b
+#4: xvmaxsp 80000000 @max@ ff800000 AND 80000000 @max@ c683287b AND 80000000 @max@ 80000000 AND 80000000 @max@ 00000000 => 80000000 80000000 80000000 00000000
+#5: xvmaxsp 80000000 @max@ 00000000 AND 80000000 @max@ 7f800000 AND 80000000 @max@ 7fffffff AND 80000000 @max@ 7fc00000 => 00000000 7f800000 80000000 80000000
+#6: xvmaxsp 00000000 @max@ ff800000 AND 00000000 @max@ c683287b AND 00000000 @max@ 80000000 AND 00000000 @max@ 00000000 => 00000000 00000000 00000000 00000000
+#7: xvmaxsp 00000000 @max@ 00000000 AND 00000000 @max@ 7f800000 AND 00000000 @max@ 7fffffff AND 00000000 @max@ 7fc00000 => 00000000 7f800000 00000000 00000000
+#8: xvmaxsp 00000000 @max@ ff800000 AND 00000000 @max@ c683287b AND 00000000 @max@ 80000000 AND 00000000 @max@ 00000000 => 00000000 00000000 00000000 00000000
+#9: xvmaxsp 00000000 @max@ 42780000 AND 00000000 @max@ 7f800000 AND 00000000 @max@ 7fffffff AND 00000000 @max@ 7fc00000 => 42780000 7f800000 00000000 00000000
+#10: xvmaxsp 7f800000 @max@ ff800000 AND 7f800000 @max@ c683287b AND 7f800000 @max@ 80000000 AND 7f800000 @max@ 00000000 => 7f800000 7f800000 7f800000 7f800000
+#11: xvmaxsp 7f800000 @max@ 00000000 AND 7f800000 @max@ 7f800000 AND 7f800000 @max@ 7fffffff AND 7f800000 @max@ 7fc00000 => 7f800000 7f800000 7f800000 7f800000
+#12: xvmaxsp ffffffff @max@ ff800000 AND ffffffff @max@ c683287b AND ffc00000 @max@ 80000000 AND ffc00000 @max@ 00000000 => ff800000 c683287b 80000000 00000000
+#13: xvmaxsp ffffffff @max@ 00000000 AND ffffffff @max@ 7f800000 AND ffffffff @max@ 7fffffff AND ffffffff @max@ 7fc00000 => 00000000 7f800000 ffffffff ffffffff
+#14: xvmaxsp ffc00000 @max@ ff800000 AND ffc00000 @max@ c683287b AND ffc00000 @max@ 80000000 AND 49192c2d @max@ 49c1288d => ff800000 c683287b 80000000 49c1288d
+#15: xvmaxsp 49192c2d @max@ 49c1288d AND 7fffffff @max@ 7fc00000 AND 7fc00000 @max@ 7fc00000 AND 7fc00000 @max@ ffc00000 => 49c1288d 7fffffff 7fc00000 7fc00000
+
+
+#0: xvminsp ff800000 @min@ ff800000 AND ff800000 @min@ c683287b AND 49192c2d @min@ 49c1288d AND ff800000 @min@ 00000000 => ff800000 ff800000 49192c2d ff800000
+#1: xvminsp ff800000 @min@ 00000000 AND ff800000 @min@ 7f800000 AND ff800000 @min@ 7fffffff AND ff800000 @min@ 7fc00000 => ff800000 ff800000 ff800000 ff800000
+#2: xvminsp c683287b @min@ ff800000 AND c683287b @min@ c683287b AND c683287b @min@ 80000000 AND c683287b @min@ 00000000 => ff800000 c683287b c683287b c683287b
+#3: xvminsp c683287b @min@ 00000000 AND c683287b @min@ 7f800000 AND c683287b @min@ 7fffffff AND c683287b @min@ 7fc00000 => c683287b c683287b c683287b c683287b
+#4: xvminsp 80000000 @min@ ff800000 AND 80000000 @min@ c683287b AND 80000000 @min@ 80000000 AND 80000000 @min@ 00000000 => ff800000 c683287b 80000000 80000000
+#5: xvminsp 80000000 @min@ 00000000 AND 80000000 @min@ 7f800000 AND 80000000 @min@ 7fffffff AND 80000000 @min@ 7fc00000 => 80000000 80000000 80000000 80000000
+#6: xvminsp 00000000 @min@ ff800000 AND 00000000 @min@ c683287b AND 00000000 @min@ 80000000 AND 00000000 @min@ 00000000 => ff800000 c683287b 80000000 00000000
+#7: xvminsp 00000000 @min@ 00000000 AND 00000000 @min@ 7f800000 AND 00000000 @min@ 7fffffff AND 00000000 @min@ 7fc00000 => 00000000 00000000 00000000 00000000
+#8: xvminsp 00000000 @min@ ff800000 AND 00000000 @min@ c683287b AND 00000000 @min@ 80000000 AND 00000000 @min@ 00000000 => ff800000 c683287b 80000000 00000000
+#9: xvminsp 00000000 @min@ 42780000 AND 00000000 @min@ 7f800000 AND 00000000 @min@ 7fffffff AND 00000000 @min@ 7fc00000 => 00000000 00000000 00000000 00000000
+#10: xvminsp 7f800000 @min@ ff800000 AND 7f800000 @min@ c683287b AND 7f800000 @min@ 80000000 AND 7f800000 @min@ 00000000 => ff800000 c683287b 80000000 00000000
+#11: xvminsp 7f800000 @min@ 00000000 AND 7f800000 @min@ 7f800000 AND 7f800000 @min@ 7fffffff AND 7f800000 @min@ 7fc00000 => 00000000 7f800000 7f800000 7f800000
+#12: xvminsp ffffffff @min@ ff800000 AND ffffffff @min@ c683287b AND ffc00000 @min@ 80000000 AND ffc00000 @min@ 00000000 => ff800000 c683287b 80000000 00000000
+#13: xvminsp ffffffff @min@ 00000000 AND ffffffff @min@ 7f800000 AND ffffffff @min@ 7fffffff AND ffffffff @min@ 7fc00000 => 00000000 7f800000 ffffffff ffffffff
+#14: xvminsp ffc00000 @min@ ff800000 AND ffc00000 @min@ c683287b AND ffc00000 @min@ 80000000 AND 49192c2d @min@ 49c1288d => ff800000 c683287b 80000000 49192c2d
+#15: xvminsp 49192c2d @min@ 49c1288d AND 7fffffff @min@ 7fc00000 AND 7fc00000 @min@ 7fc00000 AND 7fc00000 @min@ ffc00000 => 49192c2d 7fffffff 7fc00000 7fc00000
+
+
+#0: xvcpsgndp fff0000000000000 +-cp fff0000000000000 AND fff0000000000000 +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#1: xvcpsgndp 41232585a9900000 +-cp 41382511a2000000 AND fff0000000000000 +-cp 0000000000000000 => 41382511a2000000 8000000000000000
+#2: xvcpsgndp fff0000000000000 +-cp 0123214569900000 AND fff0000000000000 +-cp 7ff0000000000000 => 8123214569900000 fff0000000000000
+#3: xvcpsgndp fff0000000000000 +-cp 7ff7ffffffffffff AND fff0000000000000 +-cp 7ff8000000000000 => fff7ffffffffffff fff8000000000000
+#4: xvcpsgndp c0d0650f5a07b353 +-cp fff0000000000000 AND c0d0650f5a07b353 +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#5: xvcpsgndp c0d0650f5a07b353 +-cp 8000000000000000 AND c0d0650f5a07b353 +-cp 0000000000000000 => 8000000000000000 8000000000000000
+#6: xvcpsgndp c0d0650f5a07b353 +-cp 0123214569900000 AND c0d0650f5a07b353 +-cp 7ff0000000000000 => 8123214569900000 fff0000000000000
+#7: xvcpsgndp c0d0650f5a07b353 +-cp 7ff7ffffffffffff AND c0d0650f5a07b353 +-cp 7ff8000000000000 => fff7ffffffffffff fff8000000000000
+#8: xvcpsgndp 8000000000000000 +-cp fff0000000000000 AND 8000000000000000 +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#9: xvcpsgndp 8000000000000000 +-cp 8000000000000000 AND 8000000000000000 +-cp 0000000000000000 => 8000000000000000 8000000000000000
+#10: xvcpsgndp 8000000000000000 +-cp 0123214569900000 AND 8000000000000000 +-cp 7ff0000000000000 => 8123214569900000 fff0000000000000
+#11: xvcpsgndp 8000000000000000 +-cp 7ff7ffffffffffff AND 8000000000000000 +-cp 7ff8000000000000 => fff7ffffffffffff fff8000000000000
+#12: xvcpsgndp 0000000000000000 +-cp fff0000000000000 AND 0000000000000000 +-cp c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#13: xvcpsgndp 0000000000000000 +-cp 8000000000000000 AND 0000000000000000 +-cp 0000000000000000 => 0000000000000000 0000000000000000
+#14: xvcpsgndp 0000000000000000 +-cp 0123214569900000 AND 0000000000000000 +-cp 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#15: xvcpsgndp 0000000000000000 +-cp 7ff7ffffffffffff AND 0000000000000000 +-cp 7ff8000000000000 => 7ff7ffffffffffff 7ff8000000000000
+#16: xvcpsgndp 0123214569900000 +-cp fff0000000000000 AND 0123214569900000 +-cp c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#17: xvcpsgndp 0123214569900000 +-cp 8000000000000000 AND 0123214569900000 +-cp 0000000000000000 => 0000000000000000 0000000000000000
+#18: xvcpsgndp 0123214569900000 +-cp 404f000000000000 AND 0123214569900000 +-cp 7ff0000000000000 => 404f000000000000 7ff0000000000000
+#19: xvcpsgndp 0123214569900000 +-cp 7ff7ffffffffffff AND 0123214569900000 +-cp 7ff8000000000000 => 7ff7ffffffffffff 7ff8000000000000
+#20: xvcpsgndp 7ff0000000000000 +-cp fff0000000000000 AND 7ff0000000000000 +-cp c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#21: xvcpsgndp 7ff0000000000000 +-cp 8000000000000000 AND 7ff0000000000000 +-cp 0000000000000000 => 0000000000000000 0000000000000000
+#22: xvcpsgndp 7ff0000000000000 +-cp 0123214569900000 AND 7ff0000000000000 +-cp 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#23: xvcpsgndp 7ff0000000000000 +-cp 7ff7ffffffffffff AND 7ff0000000000000 +-cp 7ff8000000000000 => 7ff7ffffffffffff 7ff8000000000000
+#24: xvcpsgndp fff7ffffffffffff +-cp fff0000000000000 AND fff7ffffffffffff +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#25: xvcpsgndp fff8000000000000 +-cp 8000000000000000 AND fff8000000000000 +-cp 0000000000000000 => 8000000000000000 8000000000000000
+#26: xvcpsgndp fff7ffffffffffff +-cp 0123214569900000 AND fff7ffffffffffff +-cp 7ff0000000000000 => 8123214569900000 fff0000000000000
+#27: xvcpsgndp fff7ffffffffffff +-cp 7ff7ffffffffffff AND fff7ffffffffffff +-cp 7ff8000000000000 => fff7ffffffffffff fff8000000000000
+#28: xvcpsgndp fff8000000000000 +-cp fff0000000000000 AND fff8000000000000 +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#29: xvcpsgndp fff8000000000000 +-cp 8000000000000000 AND 41232585a9900000 +-cp 41382511a2000000 => 8000000000000000 41382511a2000000
+#30: xvcpsgndp 41232585a9900000 +-cp 41382511a2000000 AND 7ff7ffffffffffff +-cp 7ff8000000000000 => 41382511a2000000 7ff8000000000000
+#31: xvcpsgndp 7ff8000000000000 +-cp 7ff8000000000000 AND 7ff8000000000000 +-cp fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvcpsgnsp ff800000 +-cp ff800000 AND ff800000 +-cp c683287b AND 49192c2d +-cp 49c1288d AND ff800000 +-cp 00000000 => ff800000 c683287b 49c1288d 80000000
+#1: xvcpsgnsp ff800000 +-cp 00000000 AND ff800000 +-cp 7f800000 AND ff800000 +-cp 7fffffff AND ff800000 +-cp 7fc00000 => 80000000 ff800000 ffffffff ffc00000
+#2: xvcpsgnsp c683287b +-cp ff800000 AND c683287b +-cp c683287b AND c683287b +-cp 80000000 AND c683287b +-cp 00000000 => ff800000 c683287b 80000000 80000000
+#3: xvcpsgnsp c683287b +-cp 00000000 AND c683287b +-cp 7f800000 AND c683287b +-cp 7fffffff AND c683287b +-cp 7fc00000 => 80000000 ff800000 ffffffff ffc00000
+#4: xvcpsgnsp 80000000 +-cp ff800000 AND 80000000 +-cp c683287b AND 80000000 +-cp 80000000 AND 80000000 +-cp 00000000 => ff800000 c683287b 80000000 80000000
+#5: xvcpsgnsp 80000000 +-cp 00000000 AND 80000000 +-cp 7f800000 AND 80000000 +-cp 7fffffff AND 80000000 +-cp 7fc00000 => 80000000 ff800000 ffffffff ffc00000
+#6: xvcpsgnsp 00000000 +-cp ff800000 AND 00000000 +-cp c683287b AND 00000000 +-cp 80000000 AND 00000000 +-cp 00000000 => 7f800000 4683287b 00000000 00000000
+#7: xvcpsgnsp 00000000 +-cp 00000000 AND 00000000 +-cp 7f800000 AND 00000000 +-cp 7fffffff AND 00000000 +-cp 7fc00000 => 00000000 7f800000 7fffffff 7fc00000
+#8: xvcpsgnsp 00000000 +-cp ff800000 AND 00000000 +-cp c683287b AND 00000000 +-cp 80000000 AND 00000000 +-cp 00000000 => 7f800000 4683287b 00000000 00000000
+#9: xvcpsgnsp 00000000 +-cp 42780000 AND 00000000 +-cp 7f800000 AND 00000000 +-cp 7fffffff AND 00000000 +-cp 7fc00000 => 42780000 7f800000 7fffffff 7fc00000
+#10: xvcpsgnsp 7f800000 +-cp ff800000 AND 7f800000 +-cp c683287b AND 7f800000 +-cp 80000000 AND 7f800000 +-cp 00000000 => 7f800000 4683287b 00000000 00000000
+#11: xvcpsgnsp 7f800000 +-cp 00000000 AND 7f800000 +-cp 7f800000 AND 7f800000 +-cp 7fffffff AND 7f800000 +-cp 7fc00000 => 00000000 7f800000 7fffffff 7fc00000
+#12: xvcpsgnsp ffffffff +-cp ff800000 AND ffffffff +-cp c683287b AND ffc00000 +-cp 80000000 AND ffc00000 +-cp 00000000 => ff800000 c683287b 80000000 80000000
+#13: xvcpsgnsp ffffffff +-cp 00000000 AND ffffffff +-cp 7f800000 AND ffffffff +-cp 7fffffff AND ffffffff +-cp 7fc00000 => 80000000 ff800000 ffffffff ffc00000
+#14: xvcpsgnsp ffc00000 +-cp ff800000 AND ffc00000 +-cp c683287b AND ffc00000 +-cp 80000000 AND 49192c2d +-cp 49c1288d => ff800000 c683287b 80000000 49c1288d
+#15: xvcpsgnsp 49192c2d +-cp 49c1288d AND 7fffffff +-cp 7fc00000 AND 7fc00000 +-cp 7fc00000 AND 7fc00000 +-cp ffc00000 => 49c1288d 7fc00000 7fc00000 7fc00000
+
+
+Test xxsel instruction
+xxsel a12bc37de56f9708,fedc432124681235,ffffffff01020304 => fedc4321e46d960c
+xxsel 3894c1fddeadbeef,f1e2d3c4e0057708,128934bd00000000 => 3894d1c4deadbeef
+
+Test xxspltw instruction
+xxspltw 0xfedc432124681235f1e2d3c4e0057708 0=> 0xfedc4321fedc4321fedc4321fedc4321
+xxspltw 0xfedc432124681235f1e2d3c4e0057708 1=> 0x24681235246812352468123524681235
+xxspltw 0xfedc432124681235f1e2d3c4e0057708 2=> 0xf1e2d3c4f1e2d3c4f1e2d3c4f1e2d3c4
+xxspltw 0xfedc432124681235f1e2d3c4e0057708 3=> 0xe0057708e0057708e0057708e0057708
+
+Test div extensions
+#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
+#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
+#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
+#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
+Test floating point convert [word | doubleword] unsigned, with round toward zero
+#0: fctiduz: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiduz: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiduz: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiduz: 0x7fe800000000051b (1.348270e+308) ==> 0xffffffffffffffff
+#4: fctiduz: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiduz: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiduz: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiduz: 0x7ff0000000000000 (inf) ==> 0xffffffffffffffff
+#8: fctiduz: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiduz: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiduz: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiduz: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiduz: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiduz: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiduz: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiduz: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c2
+#16: fctiduz: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182511
+
+#0: fctiduz.: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiduz.: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiduz.: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiduz.: 0x7fe800000000051b (1.348270e+308) ==> 0xffffffffffffffff
+#4: fctiduz.: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiduz.: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiduz.: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiduz.: 0x7ff0000000000000 (inf) ==> 0xffffffffffffffff
+#8: fctiduz.: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiduz.: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiduz.: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiduz.: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiduz.: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiduz.: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiduz.: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiduz.: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c2
+#16: fctiduz.: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182511
+
+
+#0: fctidu: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctidu: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctidu: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctidu: 0x7fe800000000051b (1.348270e+308) ==> 0xffffffffffffffff
+#4: fctidu: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctidu: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctidu: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctidu: 0x7ff0000000000000 (inf) ==> 0xffffffffffffffff
+#8: fctidu: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctidu: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctidu: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctidu: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctidu: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctidu: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctidu: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctidu: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c3
+#16: fctidu: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182512
+
+#0: fctidu.: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctidu.: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctidu.: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctidu.: 0x7fe800000000051b (1.348270e+308) ==> 0xffffffffffffffff
+#4: fctidu.: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctidu.: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctidu.: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctidu.: 0x7ff0000000000000 (inf) ==> 0xffffffffffffffff
+#8: fctidu.: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctidu.: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctidu.: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctidu.: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctidu.: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctidu.: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctidu.: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctidu.: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c3
+#16: fctidu.: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182512
+
+
+#0: fctiwuz: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiwuz: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiwuz: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiwuz: 0x7fe800000000051b (1.348270e+308) ==> 0x00000000ffffffff
+#4: fctiwuz: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiwuz: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiwuz: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiwuz: 0x7ff0000000000000 (inf) ==> 0x00000000ffffffff
+#8: fctiwuz: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiwuz: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiwuz: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiwuz: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiwuz: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiwuz: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiwuz: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiwuz: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c2
+#16: fctiwuz: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182511
+
+#0: fctiwuz.: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiwuz.: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiwuz.: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiwuz.: 0x7fe800000000051b (1.348270e+308) ==> 0x00000000ffffffff
+#4: fctiwuz.: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiwuz.: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiwuz.: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiwuz.: 0x7ff0000000000000 (inf) ==> 0x00000000ffffffff
+#8: fctiwuz.: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiwuz.: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiwuz.: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiwuz.: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiwuz.: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiwuz.: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiwuz.: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiwuz.: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c2
+#16: fctiwuz.: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182511
+
+
+#0: fctiwu: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiwu: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiwu: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiwu: 0x7fe800000000051b (1.348270e+308) ==> 0x00000000ffffffff
+#4: fctiwu: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiwu: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiwu: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiwu: 0x7ff0000000000000 (inf) ==> 0x00000000ffffffff
+#8: fctiwu: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiwu: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiwu: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiwu: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiwu: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiwu: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiwu: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiwu: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c3
+#16: fctiwu: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182512
+
+#0: fctiwu.: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiwu.: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiwu.: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiwu.: 0x7fe800000000051b (1.348270e+308) ==> 0x00000000ffffffff
+#4: fctiwu.: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiwu.: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiwu.: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiwu.: 0x7ff0000000000000 (inf) ==> 0x00000000ffffffff
+#8: fctiwu.: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiwu.: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiwu.: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiwu.: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiwu.: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiwu.: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiwu.: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiwu.: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c3
+#16: fctiwu.: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182512
+
+
+Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p
+#0: xsnmsubadp !*-(fff0000000000000,fff0000000000000,3fd8000000000000) = 7ff8000000000000
+#1: xsnmsubadp !*-(c0d0650f5a07b353,fff0000000000000,404f000000000000) = 7ff0000000000000
+#2: xsnmsubadp !*-(41382511a2000000,41232585a9900000,0018000000b77501) = 41382511a2000000
+#3: xsnmsubadp !*-(0000000000000000,fff0000000000000,7fe800000000051b) = 7ff0000000000000
+#4: xsnmsubadp !*-(0123214569900000,fff0000000000000,0123214569900000) = 7ff0000000000000
+#5: xsnmsubadp !*-(7ff0000000000000,fff0000000000000,0000000000000000) = 7ff8000000000000
+#6: xsnmsubadp !*-(7ff7ffffffffffff,fff0000000000000,8000000000000000) = 7fffffffffffffff
+#7: xsnmsubadp !*-(7ff8000000000000,fff0000000000000,7ff0000000000000) = 7ff8000000000000
+#8: xsnmsubadp !*-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) = fff0000000000000
+#9: xsnmsubadp !*-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) = 7fffffffffffffff
+#10: xsnmsubadp !*-(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) = ffffffffffffffff
+#11: xsnmsubadp !*-(0000000000000000,c0d0650f5a07b353,7ff8000000000000) = 7ff8000000000000
+#12: xsnmsubadp !*-(0123214569900000,c0d0650f5a07b353,fff8000000000000) = fff8000000000000
+#13: xsnmsubadp !*-(7ff0000000000000,c0d0650f5a07b353,8008340000078000) = 7ff0000000000000
+#14: xsnmsubadp !*-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) = 7fffffffffffffff
+#15: xsnmsubadp !*-(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) = 7ff8000000000000
+#16: xsnmsubadp !*-(fff0000000000000,8000000000000000,3fd8000000000000) = fff0000000000000
+#17: xsnmsubadp !*-(c0d0650f5a07b353,8000000000000000,404f000000000000) = c0d0650f5a07b353
+#18: xsnmsubadp !*-(8000000000000000,8000000000000000,0018000000b77501) = 8000000000000000
+#19: xsnmsubadp !*-(0000000000000000,8000000000000000,7fe800000000051b) = 0000000000000000
+#20: xsnmsubadp !*-(0123214569900000,8000000000000000,0123214569900000) = 0123214569900000
+#21: xsnmsubadp !*-(7ff0000000000000,8000000000000000,0000000000000000) = 7ff0000000000000
+#22: xsnmsubadp !*-(7ff7ffffffffffff,8000000000000000,8000000000000000) = 7fffffffffffffff
+#23: xsnmsubadp !*-(7ff8000000000000,8000000000000000,7ff0000000000000) = 7ff8000000000000
+#24: xsnmsubadp !*-(fff0000000000000,0000000000000000,fff0000000000000) = 7ff8000000000000
+#25: xsnmsubadp !*-(c0d0650f5a07b353,0000000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#26: xsnmsubadp !*-(8000000000000000,0000000000000000,fff7ffffffffffff) = ffffffffffffffff
+#27: xsnmsubadp !*-(0000000000000000,0000000000000000,7ff8000000000000) = 7ff8000000000000
+#28: xsnmsubadp !*-(0123214569900000,0000000000000000,fff8000000000000) = fff8000000000000
+#29: xsnmsubadp !*-(7ff0000000000000,0000000000000000,8008340000078000) = 7ff0000000000000
+#30: xsnmsubadp !*-(7ff7ffffffffffff,0000000000000000,c0d0650f5a07b353) = 7fffffffffffffff
+#31: xsnmsubadp !*-(7ff8000000000000,0000000000000000,41232585a9900000) = 7ff8000000000000
+#32: xsnmsubadp !*-(fff0000000000000,0123214569900000,3fd8000000000000) = fff0000000000000
+#33: xsnmsubadp !*-(c0d0650f5a07b353,0123214569900000,404f000000000000) = c0d0650f5a07b353
+#34: xsnmsubadp !*-(8000000000000000,0123214569900000,0018000000b77501) = 8000000000000000
+#35: xsnmsubadp !*-(0000000000000000,0123214569900000,7fe800000000051b) = c11cb1e81e58061b
+#36: xsnmsubadp !*-(404f000000000000,0123214569900000,0123214569900000) = 404f000000000000
+#37: xsnmsubadp !*-(7ff0000000000000,0123214569900000,0000000000000000) = 7ff0000000000000
+#38: xsnmsubadp !*-(7ff7ffffffffffff,0123214569900000,8000000000000000) = 7fffffffffffffff
+#39: xsnmsubadp !*-(7ff8000000000000,0123214569900000,7ff0000000000000) = 7ff8000000000000
+#40: xsnmsubadp !*-(fff0000000000000,7ff0000000000000,fff0000000000000) = 7ff8000000000000
+#41: xsnmsubadp !*-(c0d0650f5a07b353,7ff0000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#42: xsnmsubadp !*-(8000000000000000,7ff0000000000000,fff7ffffffffffff) = ffffffffffffffff
+#43: xsnmsubadp !*-(0000000000000000,7ff0000000000000,7ff8000000000000) = 7ff8000000000000
+#44: xsnmsubadp !*-(0123214569900000,7ff0000000000000,fff8000000000000) = fff8000000000000
+#45: xsnmsubadp !*-(7ff0000000000000,7ff0000000000000,8008340000078000) = 7ff0000000000000
+#46: xsnmsubadp !*-(7ff7ffffffffffff,7ff0000000000000,c0d0650f5a07b353) = 7fffffffffffffff
+#47: xsnmsubadp !*-(7ff8000000000000,7ff0000000000000,41232585a9900000) = 7ff8000000000000
+#48: xsnmsubadp !*-(fff0000000000000,fff7ffffffffffff,3fd8000000000000) = ffffffffffffffff
+#49: xsnmsubadp !*-(c0d0650f5a07b353,fff7ffffffffffff,404f000000000000) = ffffffffffffffff
+#50: xsnmsubadp !*-(8000000000000000,fff8000000000000,0018000000b77501) = fff8000000000000
+#51: xsnmsubadp !*-(0000000000000000,fff8000000000000,7fe800000000051b) = fff8000000000000
+#52: xsnmsubadp !*-(0123214569900000,fff7ffffffffffff,0123214569900000) = ffffffffffffffff
+#53: xsnmsubadp !*-(7ff0000000000000,fff7ffffffffffff,0000000000000000) = ffffffffffffffff
+#54: xsnmsubadp !*-(7ff7ffffffffffff,fff7ffffffffffff,8000000000000000) = ffffffffffffffff
+#55: xsnmsubadp !*-(7ff8000000000000,fff7ffffffffffff,7ff0000000000000) = ffffffffffffffff
+#56: xsnmsubadp !*-(fff0000000000000,fff8000000000000,fff0000000000000) = fff8000000000000
+#57: xsnmsubadp !*-(c0d0650f5a07b353,fff8000000000000,7ff7ffffffffffff) = fff8000000000000
+#58: xsnmsubadp !*-(8000000000000000,fff8000000000000,fff7ffffffffffff) = fff8000000000000
+#59: xsnmsubadp !*-(41382511a2000000,41232585a9900000,7ff8000000000000) = 7ff8000000000000
+#60: xsnmsubadp !*-(41382511a2000000,41232585a9900000,fff8000000000000) = fff8000000000000
+#61: xsnmsubadp !*-(7ff8000000000000,7ff7ffffffffffff,8008340000078000) = 7fffffffffffffff
+#62: xsnmsubadp !*-(7ff8000000000000,7ff8000000000000,c0d0650f5a07b353) = 7ff8000000000000
+#63: xsnmsubadp !*-(fff8000000000000,7ff8000000000000,41232585a9900000) = 7ff8000000000000
+
+#0: xsnmsubmdp !*-(3fd8000000000000,fff0000000000000,fff0000000000000) = 7ff8000000000000
+#1: xsnmsubmdp !*-(404f000000000000,fff0000000000000,c0d0650f5a07b353) = 7ff0000000000000
+#2: xsnmsubmdp !*-(0018000000b77501,41232585a9900000,41382511a2000000) = 41382511a2000000
+#3: xsnmsubmdp !*-(7fe800000000051b,fff0000000000000,0000000000000000) = 7ff0000000000000
+#4: xsnmsubmdp !*-(0123214569900000,fff0000000000000,0123214569900000) = 7ff0000000000000
+#5: xsnmsubmdp !*-(0000000000000000,fff0000000000000,7ff0000000000000) = 7ff8000000000000
+#6: xsnmsubmdp !*-(8000000000000000,fff0000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#7: xsnmsubmdp !*-(7ff0000000000000,fff0000000000000,7ff8000000000000) = 7ff8000000000000
+#8: xsnmsubmdp !*-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) = fff0000000000000
+#9: xsnmsubmdp !*-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) = 7fffffffffffffff
+#10: xsnmsubmdp !*-(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) = ffffffffffffffff
+#11: xsnmsubmdp !*-(7ff8000000000000,c0d0650f5a07b353,0000000000000000) = 7ff8000000000000
+#12: xsnmsubmdp !*-(fff8000000000000,c0d0650f5a07b353,0123214569900000) = fff8000000000000
+#13: xsnmsubmdp !*-(8008340000078000,c0d0650f5a07b353,7ff0000000000000) = 7ff0000000000000
+#14: xsnmsubmdp !*-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) = 7fffffffffffffff
+#15: xsnmsubmdp !*-(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) = 7ff8000000000000
+#16: xsnmsubmdp !*-(3fd8000000000000,8000000000000000,fff0000000000000) = fff0000000000000
+#17: xsnmsubmdp !*-(404f000000000000,8000000000000000,c0d0650f5a07b353) = c0d0650f5a07b353
+#18: xsnmsubmdp !*-(0018000000b77501,8000000000000000,8000000000000000) = 8000000000000000
+#19: xsnmsubmdp !*-(7fe800000000051b,8000000000000000,0000000000000000) = 0000000000000000
+#20: xsnmsubmdp !*-(0123214569900000,8000000000000000,0123214569900000) = 0123214569900000
+#21: xsnmsubmdp !*-(0000000000000000,8000000000000000,7ff0000000000000) = 7ff0000000000000
+#22: xsnmsubmdp !*-(8000000000000000,8000000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#23: xsnmsubmdp !*-(7ff0000000000000,8000000000000000,7ff8000000000000) = 7ff8000000000000
+#24: xsnmsubmdp !*-(fff0000000000000,0000000000000000,fff0000000000000) = 7ff8000000000000
+#25: xsnmsubmdp !*-(7ff7ffffffffffff,0000000000000000,c0d0650f5a07b353) = 7fffffffffffffff
+#26: xsnmsubmdp !*-(fff7ffffffffffff,0000000000000000,8000000000000000) = ffffffffffffffff
+#27: xsnmsubmdp !*-(7ff8000000000000,0000000000000000,0000000000000000) = 7ff8000000000000
+#28: xsnmsubmdp !*-(fff8000000000000,0000000000000000,0123214569900000) = fff8000000000000
+#29: xsnmsubmdp !*-(8008340000078000,0000000000000000,7ff0000000000000) = 7ff0000000000000
+#30: xsnmsubmdp !*-(c0d0650f5a07b353,0000000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#31: xsnmsubmdp !*-(41232585a9900000,0000000000000000,7ff8000000000000) = 7ff8000000000000
+#32: xsnmsubmdp !*-(3fd8000000000000,0123214569900000,fff0000000000000) = fff0000000000000
+#33: xsnmsubmdp !*-(404f000000000000,0123214569900000,c0d0650f5a07b353) = c0d0650f5a07b353
+#34: xsnmsubmdp !*-(0018000000b77501,0123214569900000,8000000000000000) = 8000000000000000
+#35: xsnmsubmdp !*-(7fe800000000051b,0123214569900000,0000000000000000) = c11cb1e81e58061b
+#36: xsnmsubmdp !*-(0123214569900000,0123214569900000,404f000000000000) = 404f000000000000
+#37: xsnmsubmdp !*-(0000000000000000,0123214569900000,7ff0000000000000) = 7ff0000000000000
+#38: xsnmsubmdp !*-(8000000000000000,0123214569900000,7ff7ffffffffffff) = 7fffffffffffffff
+#39: xsnmsubmdp !*-(7ff0000000000000,0123214569900000,7ff8000000000000) = 7ff8000000000000
+#40: xsnmsubmdp !*-(fff0000000000000,7ff0000000000000,fff0000000000000) = 7ff8000000000000
+#41: xsnmsubmdp !*-(7ff7ffffffffffff,7ff0000000000000,c0d0650f5a07b353) = 7fffffffffffffff
+#42: xsnmsubmdp !*-(fff7ffffffffffff,7ff0000000000000,8000000000000000) = ffffffffffffffff
+#43: xsnmsubmdp !*-(7ff8000000000000,7ff0000000000000,0000000000000000) = 7ff8000000000000
+#44: xsnmsubmdp !*-(fff8000000000000,7ff0000000000000,0123214569900000) = fff8000000000000
+#45: xsnmsubmdp !*-(8008340000078000,7ff0000000000000,7ff0000000000000) = 7ff0000000000000
+#46: xsnmsubmdp !*-(c0d0650f5a07b353,7ff0000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#47: xsnmsubmdp !*-(41232585a9900000,7ff0000000000000,7ff8000000000000) = 7ff8000000000000
+#48: xsnmsubmdp !*-(3fd8000000000000,fff7ffffffffffff,fff0000000000000) = ffffffffffffffff
+#49: xsnmsubmdp !*-(404f000000000000,fff7ffffffffffff,c0d0650f5a07b353) = ffffffffffffffff
+#50: xsnmsubmdp !*-(0018000000b77501,fff8000000000000,8000000000000000) = fff8000000000000
+#51: xsnmsubmdp !*-(7fe800000000051b,fff8000000000000,0000000000000000) = fff8000000000000
+#52: xsnmsubmdp !*-(0123214569900000,fff7ffffffffffff,0123214569900000) = ffffffffffffffff
+#53: xsnmsubmdp !*-(0000000000000000,fff7ffffffffffff,7ff0000000000000) = ffffffffffffffff
+#54: xsnmsubmdp !*-(8000000000000000,fff7ffffffffffff,7ff7ffffffffffff) = ffffffffffffffff
+#55: xsnmsubmdp !*-(7ff0000000000000,fff7ffffffffffff,7ff8000000000000) = ffffffffffffffff
+#56: xsnmsubmdp !*-(fff0000000000000,fff8000000000000,fff0000000000000) = fff8000000000000
+#57: xsnmsubmdp !*-(7ff7ffffffffffff,fff8000000000000,c0d0650f5a07b353) = fff8000000000000
+#58: xsnmsubmdp !*-(fff7ffffffffffff,fff8000000000000,8000000000000000) = fff8000000000000
+#59: xsnmsubmdp !*-(7ff8000000000000,41232585a9900000,41382511a2000000) = 7ff8000000000000
+#60: xsnmsubmdp !*-(fff8000000000000,41232585a9900000,41382511a2000000) = fff8000000000000
+#61: xsnmsubmdp !*-(8008340000078000,7ff7ffffffffffff,7ff8000000000000) = 7fffffffffffffff
+#62: xsnmsubmdp !*-(c0d0650f5a07b353,7ff8000000000000,7ff8000000000000) = 7ff8000000000000
+#63: xsnmsubmdp !*-(41232585a9900000,7ff8000000000000,fff8000000000000) = 7ff8000000000000
+
+#0: xvmaddadp *+(fff0000000000000,fff0000000000000,3fd8000000000000) AND *+(c0d0650f5a07b353,fff0000000000000,404f000000000000) => fff0000000000000 fff0000000000000
+#1: xvmaddadp *+(41382511a2000000,41232585a9900000,0018000000b77501) AND *+(0000000000000000,fff0000000000000,7fe800000000051b) => 41382511a2000000 fff0000000000000
+#2: xvmaddadp *+(0123214569900000,fff0000000000000,0123214569900000) AND *+(7ff0000000000000,fff0000000000000,0000000000000000) => fff0000000000000 7ff8000000000000
+#3: xvmaddadp *+(7ff7ffffffffffff,fff0000000000000,8000000000000000) AND *+(7ff8000000000000,fff0000000000000,7ff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvmaddadp *+(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND *+(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) => 7ff8000000000000 7fffffffffffffff
+#5: xvmaddadp *+(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) AND *+(0000000000000000,c0d0650f5a07b353,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvmaddadp *+(0123214569900000,c0d0650f5a07b353,fff8000000000000) AND *+(7ff0000000000000,c0d0650f5a07b353,8008340000078000) => fff8000000000000 7ff0000000000000
+#7: xvmaddadp *+(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) AND *+(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) => 7fffffffffffffff 7ff8000000000000
+#8: xvmaddadp *+(fff0000000000000,8000000000000000,404f000000000000) AND *+(c0d0650f5a07b353,8000000000000000,0018000000b77501) => fff0000000000000 c0d0650f5a07b353
+#9: xvmaddadp *+(8000000000000000,8000000000000000,7fe800000000051b) AND *+(0000000000000000,8000000000000000,0123214569900000) => 8000000000000000 0000000000000000
+#10: xvmaddadp *+(0123214569900000,8000000000000000,0000000000000000) AND *+(7ff0000000000000,8000000000000000,8000000000000000) => 0123214569900000 7ff0000000000000
+#11: xvmaddadp *+(7ff7ffffffffffff,8000000000000000,7ff0000000000000) AND *+(7ff8000000000000,8000000000000000,fff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvmaddadp *+(fff0000000000000,0000000000000000,7ff7ffffffffffff) AND *+(c0d0650f5a07b353,0000000000000000,fff7ffffffffffff) => 7fffffffffffffff ffffffffffffffff
+#13: xvmaddadp *+(8000000000000000,0000000000000000,7ff8000000000000) AND *+(0000000000000000,0000000000000000,fff8000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvmaddadp *+(0123214569900000,0000000000000000,8008340000078000) AND *+(7ff0000000000000,0000000000000000,c0d0650f5a07b353) => 0123214569900000 7ff0000000000000
+#15: xvmaddadp *+(7ff7ffffffffffff,0000000000000000,3fd8000000000000) AND *+(7ff8000000000000,0000000000000000,404f000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvmaddadp *+(fff0000000000000,0123214569900000,0018000000b77501) AND *+(c0d0650f5a07b353,0123214569900000,7fe800000000051b) => fff0000000000000 411bab9728b78ae5
+#17: xvmaddadp *+(8000000000000000,0123214569900000,0123214569900000) AND *+(0000000000000000,0123214569900000,0000000000000000) => 0000000000000000 0000000000000000
+#18: xvmaddadp *+(404f000000000000,0123214569900000,8000000000000000) AND *+(7ff0000000000000,0123214569900000,7ff0000000000000) => 404f000000000000 7ff0000000000000
+#19: xvmaddadp *+(7ff7ffffffffffff,0123214569900000,fff0000000000000) AND *+(7ff8000000000000,0123214569900000,7ff7ffffffffffff) => 7fffffffffffffff 7ff8000000000000
+#20: xvmaddadp *+(fff0000000000000,7ff0000000000000,fff7ffffffffffff) AND *+(c0d0650f5a07b353,7ff0000000000000,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#21: xvmaddadp *+(8000000000000000,7ff0000000000000,fff8000000000000) AND *+(0000000000000000,7ff0000000000000,8008340000078000) => fff8000000000000 fff0000000000000
+#22: xvmaddadp *+(0123214569900000,7ff0000000000000,c0d0650f5a07b353) AND *+(7ff0000000000000,7ff0000000000000,41232585a9900000) => fff0000000000000 7ff0000000000000
+#23: xvmaddadp *+(7ff7ffffffffffff,7ff0000000000000,404f000000000000) AND *+(7ff8000000000000,7ff0000000000000,0018000000b77501) => 7fffffffffffffff 7ff8000000000000
+#24: xvmaddadp *+(fff0000000000000,fff7ffffffffffff,7fe800000000051b) AND *+(c0d0650f5a07b353,fff7ffffffffffff,0123214569900000) => ffffffffffffffff ffffffffffffffff
+#25: xvmaddadp *+(8000000000000000,fff8000000000000,0000000000000000) AND *+(0000000000000000,fff8000000000000,8000000000000000) => fff8000000000000 fff8000000000000
+#26: xvmaddadp *+(0123214569900000,fff7ffffffffffff,7ff0000000000000) AND *+(7ff0000000000000,fff7ffffffffffff,fff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvmaddadp *+(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND *+(7ff8000000000000,fff7ffffffffffff,fff7ffffffffffff) => ffffffffffffffff ffffffffffffffff
+#28: xvmaddadp *+(fff0000000000000,fff8000000000000,7ff8000000000000) AND *+(c0d0650f5a07b353,fff8000000000000,fff8000000000000) => fff8000000000000 fff8000000000000
+#29: xvmaddadp *+(8000000000000000,fff8000000000000,8008340000078000) AND *+(41382511a2000000,41232585a9900000,c0d0650f5a07b353) => fff8000000000000 c2039db3bbaae2d2
+#30: xvmaddadp *+(41382511a2000000,41232585a9900000,3fd8000000000000) AND *+(7ff8000000000000,7ff7ffffffffffff,404f000000000000) => 413bbc1ab1cb0000 7fffffffffffffff
+#31: xvmaddadp *+(7ff8000000000000,7ff8000000000000,0018000000b77501) AND *+(fff8000000000000,7ff8000000000000,7fe800000000051b) => 7ff8000000000000 7ff8000000000000
+
+#0: xvmaddmdp *+(3fd8000000000000,fff0000000000000,fff0000000000000) AND *+(404f000000000000,fff0000000000000,c0d0650f5a07b353) => fff0000000000000 fff0000000000000
+#1: xvmaddmdp *+(0018000000b77501,41232585a9900000,41382511a2000000) AND *+(7fe800000000051b,fff0000000000000,0000000000000000) => 41382511a2000000 fff0000000000000
+#2: xvmaddmdp *+(0123214569900000,fff0000000000000,0123214569900000) AND *+(0000000000000000,fff0000000000000,7ff0000000000000) => fff0000000000000 7ff8000000000000
+#3: xvmaddmdp *+(8000000000000000,fff0000000000000,7ff7ffffffffffff) AND *+(7ff0000000000000,fff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvmaddmdp *+(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND *+(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) => 7ff8000000000000 7fffffffffffffff
+#5: xvmaddmdp *+(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) AND *+(7ff8000000000000,c0d0650f5a07b353,0000000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvmaddmdp *+(fff8000000000000,c0d0650f5a07b353,0123214569900000) AND *+(8008340000078000,c0d0650f5a07b353,7ff0000000000000) => fff8000000000000 7ff0000000000000
+#7: xvmaddmdp *+(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) AND *+(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#8: xvmaddmdp *+(404f000000000000,8000000000000000,fff0000000000000) AND *+(0018000000b77501,8000000000000000,c0d0650f5a07b353) => fff0000000000000 c0d0650f5a07b353
+#9: xvmaddmdp *+(7fe800000000051b,8000000000000000,8000000000000000) AND *+(0123214569900000,8000000000000000,0000000000000000) => 8000000000000000 0000000000000000
+#10: xvmaddmdp *+(0000000000000000,8000000000000000,0123214569900000) AND *+(8000000000000000,8000000000000000,7ff0000000000000) => 0123214569900000 7ff0000000000000
+#11: xvmaddmdp *+(7ff0000000000000,8000000000000000,7ff7ffffffffffff) AND *+(fff0000000000000,8000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvmaddmdp *+(7ff7ffffffffffff,0000000000000000,fff0000000000000) AND *+(fff7ffffffffffff,0000000000000000,c0d0650f5a07b353) => 7fffffffffffffff ffffffffffffffff
+#13: xvmaddmdp *+(7ff8000000000000,0000000000000000,8000000000000000) AND *+(fff8000000000000,0000000000000000,0000000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvmaddmdp *+(8008340000078000,0000000000000000,0123214569900000) AND *+(c0d0650f5a07b353,0000000000000000,7ff0000000000000) => 0123214569900000 7ff0000000000000
+#15: xvmaddmdp *+(3fd8000000000000,0000000000000000,7ff7ffffffffffff) AND *+(404f000000000000,0000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvmaddmdp *+(0018000000b77501,0123214569900000,fff0000000000000) AND *+(7fe800000000051b,0123214569900000,c0d0650f5a07b353) => fff0000000000000 411bab9728b78ae5
+#17: xvmaddmdp *+(0123214569900000,0123214569900000,8000000000000000) AND *+(0000000000000000,0123214569900000,0000000000000000) => 0000000000000000 0000000000000000
+#18: xvmaddmdp *+(8000000000000000,0123214569900000,404f000000000000) AND *+(7ff0000000000000,0123214569900000,7ff0000000000000) => 404f000000000000 7ff0000000000000
+#19: xvmaddmdp *+(fff0000000000000,0123214569900000,7ff7ffffffffffff) AND *+(7ff7ffffffffffff,0123214569900000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#20: xvmaddmdp *+(fff7ffffffffffff,7ff0000000000000,fff0000000000000) AND *+(7ff8000000000000,7ff0000000000000,c0d0650f5a07b353) => ffffffffffffffff 7ff8000000000000
+#21: xvmaddmdp *+(fff8000000000000,7ff0000000000000,8000000000000000) AND *+(8008340000078000,7ff0000000000000,0000000000000000) => fff8000000000000 fff0000000000000
+#22: xvmaddmdp *+(c0d0650f5a07b353,7ff0000000000000,0123214569900000) AND *+(41232585a9900000,7ff0000000000000,7ff0000000000000) => fff0000000000000 7ff0000000000000
+#23: xvmaddmdp *+(404f000000000000,7ff0000000000000,7ff7ffffffffffff) AND *+(0018000000b77501,7ff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#24: xvmaddmdp *+(7fe800000000051b,fff7ffffffffffff,fff0000000000000) AND *+(0123214569900000,fff7ffffffffffff,c0d0650f5a07b353) => ffffffffffffffff ffffffffffffffff
+#25: xvmaddmdp *+(0000000000000000,fff8000000000000,8000000000000000) AND *+(8000000000000000,fff8000000000000,0000000000000000) => fff8000000000000 fff8000000000000
+#26: xvmaddmdp *+(7ff0000000000000,fff7ffffffffffff,0123214569900000) AND *+(fff0000000000000,fff7ffffffffffff,7ff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvmaddmdp *+(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND *+(fff7ffffffffffff,fff7ffffffffffff,7ff8000000000000) => ffffffffffffffff ffffffffffffffff
+#28: xvmaddmdp *+(7ff8000000000000,fff8000000000000,fff0000000000000) AND *+(fff8000000000000,fff8000000000000,c0d0650f5a07b353) => fff8000000000000 fff8000000000000
+#29: xvmaddmdp *+(8008340000078000,fff8000000000000,8000000000000000) AND *+(c0d0650f5a07b353,41232585a9900000,41382511a2000000) => fff8000000000000 c2039db3bbaae2d2
+#30: xvmaddmdp *+(3fd8000000000000,41232585a9900000,41382511a2000000) AND *+(404f000000000000,7ff7ffffffffffff,7ff8000000000000) => 413bbc1ab1cb0000 7fffffffffffffff
+#31: xvmaddmdp *+(0018000000b77501,7ff8000000000000,7ff8000000000000) AND *+(7fe800000000051b,7ff8000000000000,fff8000000000000) => 7ff8000000000000 7ff8000000000000
+
+#0: xvmaddasp *+(ff800000,ff800000,3ec00000) AND *+(c683287b,ff800000,42780000) AND *+(49c1288d,49192c2d,00000000) AND *+(00000000,ff800000,7f800000) => ff800000 ff800000 49c1288d ff800000
+#1: xvmaddasp *+(00000000,ff800000,00000000) AND *+(7f800000,ff800000,00000000) AND *+(7fffffff,ff800000,80000000) AND *+(7fc00000,ff800000,7f800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvmaddasp *+(ff800000,c683287b,ff800000) AND *+(c683287b,c683287b,7fffffff) AND *+(80000000,c683287b,ffffffff) AND *+(00000000,c683287b,7fc00000) => 7fc00000 7fffffff ffffffff 7fc00000
+#3: xvmaddasp *+(00000000,c683287b,ffc00000) AND *+(7f800000,c683287b,80000000) AND *+(7fffffff,c683287b,c683287b) AND *+(7fc00000,c683287b,49192c2d) => ffc00000 7f800000 7fffffff 7fc00000
+#4: xvmaddasp *+(ff800000,80000000,7f800000) AND *+(c683287b,80000000,00000000) AND *+(80000000,80000000,00000000) AND *+(00000000,80000000,80000000) => 7fc00000 c683287b 80000000 00000000
+#5: xvmaddasp *+(00000000,80000000,7f800000) AND *+(7f800000,80000000,ff800000) AND *+(7fffffff,80000000,7fffffff) AND *+(7fc00000,80000000,ffffffff) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvmaddasp *+(ff800000,00000000,7fc00000) AND *+(c683287b,00000000,ffc00000) AND *+(80000000,00000000,80000000) AND *+(00000000,00000000,c683287b) => 7fc00000 ffc00000 80000000 00000000
+#7: xvmaddasp *+(00000000,00000000,00000000) AND *+(7f800000,00000000,7f800000) AND *+(7fffffff,00000000,00000000) AND *+(7fc00000,00000000,00000000) => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmaddasp *+(ff800000,00000000,80000000) AND *+(c683287b,00000000,7f800000) AND *+(80000000,00000000,ff800000) AND *+(00000000,00000000,7fffffff) => ff800000 7fc00000 7fc00000 7fffffff
+#9: xvmaddasp *+(42780000,00000000,ffffffff) AND *+(7f800000,00000000,7fc00000) AND *+(7fffffff,00000000,ffc00000) AND *+(7fc00000,00000000,80000000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvmaddasp *+(ff800000,7f800000,42780000) AND *+(c683287b,7f800000,00000000) AND *+(80000000,7f800000,7f800000) AND *+(00000000,7f800000,00000000) => 7fc00000 7fc00000 7f800000 7fc00000
+#11: xvmaddasp *+(00000000,7f800000,00000000) AND *+(7f800000,7f800000,80000000) AND *+(7fffffff,7f800000,7f800000) AND *+(7fc00000,7f800000,ff800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvmaddasp *+(ff800000,ffffffff,7fffffff) AND *+(c683287b,ffffffff,ffffffff) AND *+(80000000,ffc00000,7fc00000) AND *+(00000000,ffc00000,ffc00000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmaddasp *+(00000000,ffffffff,3ec00000) AND *+(7f800000,ffffffff,42780000) AND *+(7fffffff,ffffffff,00000000) AND *+(7fc00000,ffffffff,7f800000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvmaddasp *+(ff800000,ffc00000,00000000) AND *+(c683287b,ffc00000,00000000) AND *+(80000000,ffc00000,80000000) AND *+(49c1288d,49192c2d,7f800000) => ffc00000 ffc00000 ffc00000 7f800000
+#15: xvmaddasp *+(49c1288d,49192c2d,ff800000) AND *+(7fc00000,7fffffff,7fffffff) AND *+(7fc00000,7fc00000,ffffffff) AND *+(ffc00000,7fc00000,7fc00000) => ff800000 7fffffff 7fc00000 7fc00000
+
+#0: xvmaddmsp *+(3ec00000,ff800000,ff800000) AND *+(42780000,ff800000,c683287b) AND *+(00000000,49192c2d,49c1288d) AND *+(7f800000,ff800000,00000000) => ff800000 ff800000 49c1288d ff800000
+#1: xvmaddmsp *+(00000000,ff800000,00000000) AND *+(00000000,ff800000,7f800000) AND *+(80000000,ff800000,7fffffff) AND *+(7f800000,ff800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvmaddmsp *+(ff800000,c683287b,ff800000) AND *+(7fffffff,c683287b,c683287b) AND *+(ffffffff,c683287b,80000000) AND *+(7fc00000,c683287b,00000000) => 7fc00000 7fffffff ffffffff 7fc00000
+#3: xvmaddmsp *+(ffc00000,c683287b,00000000) AND *+(80000000,c683287b,7f800000) AND *+(c683287b,c683287b,7fffffff) AND *+(49192c2d,c683287b,7fc00000) => ffc00000 7f800000 7fffffff 7fc00000
+#4: xvmaddmsp *+(7f800000,80000000,ff800000) AND *+(00000000,80000000,c683287b) AND *+(00000000,80000000,80000000) AND *+(80000000,80000000,00000000) => 7fc00000 c683287b 80000000 00000000
+#5: xvmaddmsp *+(7f800000,80000000,00000000) AND *+(ff800000,80000000,7f800000) AND *+(7fffffff,80000000,7fffffff) AND *+(ffffffff,80000000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvmaddmsp *+(7fc00000,00000000,ff800000) AND *+(ffc00000,00000000,c683287b) AND *+(80000000,00000000,80000000) AND *+(c683287b,00000000,00000000) => 7fc00000 ffc00000 80000000 00000000
+#7: xvmaddmsp *+(00000000,00000000,00000000) AND *+(7f800000,00000000,7f800000) AND *+(00000000,00000000,7fffffff) AND *+(00000000,00000000,7fc00000) => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmaddmsp *+(80000000,00000000,ff800000) AND *+(7f800000,00000000,c683287b) AND *+(ff800000,00000000,80000000) AND *+(7fffffff,00000000,00000000) => ff800000 7fc00000 7fc00000 7fffffff
+#9: xvmaddmsp *+(ffffffff,00000000,42780000) AND *+(7fc00000,00000000,7f800000) AND *+(ffc00000,00000000,7fffffff) AND *+(80000000,00000000,7fc00000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvmaddmsp *+(42780000,7f800000,ff800000) AND *+(00000000,7f800000,c683287b) AND *+(7f800000,7f800000,80000000) AND *+(00000000,7f800000,00000000) => 7fc00000 7fc00000 7f800000 7fc00000
+#11: xvmaddmsp *+(00000000,7f800000,00000000) AND *+(80000000,7f800000,7f800000) AND *+(7f800000,7f800000,7fffffff) AND *+(ff800000,7f800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvmaddmsp *+(7fffffff,ffffffff,ff800000) AND *+(ffffffff,ffffffff,c683287b) AND *+(7fc00000,ffc00000,80000000) AND *+(ffc00000,ffc00000,00000000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmaddmsp *+(3ec00000,ffffffff,00000000) AND *+(42780000,ffffffff,7f800000) AND *+(00000000,ffffffff,7fffffff) AND *+(7f800000,ffffffff,7fc00000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvmaddmsp *+(00000000,ffc00000,ff800000) AND *+(00000000,ffc00000,c683287b) AND *+(80000000,ffc00000,80000000) AND *+(7f800000,49192c2d,49c1288d) => ffc00000 ffc00000 ffc00000 7f800000
+#15: xvmaddmsp *+(ff800000,49192c2d,49c1288d) AND *+(7fffffff,7fffffff,7fc00000) AND *+(ffffffff,7fc00000,7fc00000) AND *+(7fc00000,7fc00000,ffc00000) => ff800000 7fffffff 7fc00000 7fc00000
+
+#0: xvnmaddadp !*+(fff0000000000000,fff0000000000000,3fd8000000000000) AND !*+(c0d0650f5a07b353,fff0000000000000,404f000000000000) => 7ff0000000000000 7ff0000000000000
+#1: xvnmaddadp !*+(41382511a2000000,41232585a9900000,0018000000b77501) AND !*+(0000000000000000,fff0000000000000,7fe800000000051b) => c1382511a2000000 7ff0000000000000
+#2: xvnmaddadp !*+(0123214569900000,fff0000000000000,0123214569900000) AND !*+(7ff0000000000000,fff0000000000000,0000000000000000) => 7ff0000000000000 7ff8000000000000
+#3: xvnmaddadp !*+(7ff7ffffffffffff,fff0000000000000,8000000000000000) AND !*+(7ff8000000000000,fff0000000000000,7ff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvnmaddadp !*+(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND !*+(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) => 7ff8000000000000 7fffffffffffffff
+#5: xvnmaddadp !*+(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) AND !*+(0000000000000000,c0d0650f5a07b353,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvnmaddadp !*+(0123214569900000,c0d0650f5a07b353,fff8000000000000) AND !*+(7ff0000000000000,c0d0650f5a07b353,8008340000078000) => fff8000000000000 fff0000000000000
+#7: xvnmaddadp !*+(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) AND !*+(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) => 7fffffffffffffff 7ff8000000000000
+#8: xvnmaddadp !*+(fff0000000000000,8000000000000000,404f000000000000) AND !*+(c0d0650f5a07b353,8000000000000000,0018000000b77501) => 7ff0000000000000 40d0650f5a07b353
+#9: xvnmaddadp !*+(8000000000000000,8000000000000000,7fe800000000051b) AND !*+(0000000000000000,8000000000000000,0123214569900000) => 0000000000000000 8000000000000000
+#10: xvnmaddadp !*+(0123214569900000,8000000000000000,0000000000000000) AND !*+(7ff0000000000000,8000000000000000,8000000000000000) => 8123214569900000 fff0000000000000
+#11: xvnmaddadp !*+(7ff7ffffffffffff,8000000000000000,7ff0000000000000) AND !*+(7ff8000000000000,8000000000000000,fff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvnmaddadp !*+(fff0000000000000,0000000000000000,7ff7ffffffffffff) AND !*+(c0d0650f5a07b353,0000000000000000,fff7ffffffffffff) => 7fffffffffffffff ffffffffffffffff
+#13: xvnmaddadp !*+(8000000000000000,0000000000000000,7ff8000000000000) AND !*+(0000000000000000,0000000000000000,fff8000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvnmaddadp !*+(0123214569900000,0000000000000000,8008340000078000) AND !*+(7ff0000000000000,0000000000000000,c0d0650f5a07b353) => 8123214569900000 fff0000000000000
+#15: xvnmaddadp !*+(7ff7ffffffffffff,0000000000000000,3fd8000000000000) AND !*+(7ff8000000000000,0000000000000000,404f000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvnmaddadp !*+(fff0000000000000,0123214569900000,0018000000b77501) AND !*+(c0d0650f5a07b353,0123214569900000,7fe800000000051b) => 7ff0000000000000 c11bab9728b78ae5
+#17: xvnmaddadp !*+(8000000000000000,0123214569900000,0123214569900000) AND !*+(0000000000000000,0123214569900000,0000000000000000) => 8000000000000000 8000000000000000
+#18: xvnmaddadp !*+(404f000000000000,0123214569900000,8000000000000000) AND !*+(7ff0000000000000,0123214569900000,7ff0000000000000) => c04f000000000000 fff0000000000000
+#19: xvnmaddadp !*+(7ff7ffffffffffff,0123214569900000,fff0000000000000) AND !*+(7ff8000000000000,0123214569900000,7ff7ffffffffffff) => 7fffffffffffffff 7ff8000000000000
+#20: xvnmaddadp !*+(fff0000000000000,7ff0000000000000,fff7ffffffffffff) AND !*+(c0d0650f5a07b353,7ff0000000000000,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#21: xvnmaddadp !*+(8000000000000000,7ff0000000000000,fff8000000000000) AND !*+(0000000000000000,7ff0000000000000,8008340000078000) => fff8000000000000 7ff0000000000000
+#22: xvnmaddadp !*+(0123214569900000,7ff0000000000000,c0d0650f5a07b353) AND !*+(7ff0000000000000,7ff0000000000000,41232585a9900000) => 7ff0000000000000 fff0000000000000
+#23: xvnmaddadp !*+(7ff7ffffffffffff,7ff0000000000000,404f000000000000) AND !*+(7ff8000000000000,7ff0000000000000,0018000000b77501) => 7fffffffffffffff 7ff8000000000000
+#24: xvnmaddadp !*+(fff0000000000000,fff7ffffffffffff,7fe800000000051b) AND !*+(c0d0650f5a07b353,fff7ffffffffffff,0123214569900000) => ffffffffffffffff ffffffffffffffff
+#25: xvnmaddadp !*+(8000000000000000,fff8000000000000,0000000000000000) AND !*+(0000000000000000,fff8000000000000,8000000000000000) => fff8000000000000 fff8000000000000
+#26: xvnmaddadp !*+(0123214569900000,fff7ffffffffffff,7ff0000000000000) AND !*+(7ff0000000000000,fff7ffffffffffff,fff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvnmaddadp !*+(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND !*+(7ff8000000000000,fff7ffffffffffff,fff7ffffffffffff) => ffffffffffffffff ffffffffffffffff
+#28: xvnmaddadp !*+(fff0000000000000,fff8000000000000,7ff8000000000000) AND !*+(c0d0650f5a07b353,fff8000000000000,fff8000000000000) => fff8000000000000 fff8000000000000
+#29: xvnmaddadp !*+(8000000000000000,fff8000000000000,8008340000078000) AND !*+(41382511a2000000,41232585a9900000,c0d0650f5a07b353) => fff8000000000000 42039db3bbaae2d2
+#30: xvnmaddadp !*+(41382511a2000000,41232585a9900000,3fd8000000000000) AND !*+(7ff8000000000000,7ff7ffffffffffff,404f000000000000) => c13bbc1ab1cb0000 7fffffffffffffff
+#31: xvnmaddadp !*+(7ff8000000000000,7ff8000000000000,0018000000b77501) AND !*+(fff8000000000000,7ff8000000000000,7fe800000000051b) => 7ff8000000000000 7ff8000000000000
+
+#0: xvnmaddmdp !*+(3fd8000000000000,fff0000000000000,fff0000000000000) AND !*+(404f000000000000,fff0000000000000,c0d0650f5a07b353) => 7ff0000000000000 7ff0000000000000
+#1: xvnmaddmdp !*+(0018000000b77501,41232585a9900000,41382511a2000000) AND !*+(7fe800000000051b,fff0000000000000,0000000000000000) => c1382511a2000000 7ff0000000000000
+#2: xvnmaddmdp !*+(0123214569900000,fff0000000000000,0123214569900000) AND !*+(0000000000000000,fff0000000000000,7ff0000000000000) => 7ff0000000000000 7ff8000000000000
+#3: xvnmaddmdp !*+(8000000000000000,fff0000000000000,7ff7ffffffffffff) AND !*+(7ff0000000000000,fff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvnmaddmdp !*+(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND !*+(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) => 7ff8000000000000 7fffffffffffffff
+#5: xvnmaddmdp !*+(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) AND !*+(7ff8000000000000,c0d0650f5a07b353,0000000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvnmaddmdp !*+(fff8000000000000,c0d0650f5a07b353,0123214569900000) AND !*+(8008340000078000,c0d0650f5a07b353,7ff0000000000000) => fff8000000000000 fff0000000000000
+#7: xvnmaddmdp !*+(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) AND !*+(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#8: xvnmaddmdp !*+(404f000000000000,8000000000000000,fff0000000000000) AND !*+(0018000000b77501,8000000000000000,c0d0650f5a07b353) => 7ff0000000000000 40d0650f5a07b353
+#9: xvnmaddmdp !*+(7fe800000000051b,8000000000000000,8000000000000000) AND !*+(0123214569900000,8000000000000000,0000000000000000) => 0000000000000000 8000000000000000
+#10: xvnmaddmdp !*+(0000000000000000,8000000000000000,0123214569900000) AND !*+(8000000000000000,8000000000000000,7ff0000000000000) => 8123214569900000 fff0000000000000
+#11: xvnmaddmdp !*+(7ff0000000000000,8000000000000000,7ff7ffffffffffff) AND !*+(fff0000000000000,8000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvnmaddmdp !*+(7ff7ffffffffffff,0000000000000000,fff0000000000000) AND !*+(fff7ffffffffffff,0000000000000000,c0d0650f5a07b353) => 7fffffffffffffff ffffffffffffffff
+#13: xvnmaddmdp !*+(7ff8000000000000,0000000000000000,8000000000000000) AND !*+(fff8000000000000,0000000000000000,0000000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvnmaddmdp !*+(8008340000078000,0000000000000000,0123214569900000) AND !*+(c0d0650f5a07b353,0000000000000000,7ff0000000000000) => 8123214569900000 fff0000000000000
+#15: xvnmaddmdp !*+(3fd8000000000000,0000000000000000,7ff7ffffffffffff) AND !*+(404f000000000000,0000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvnmaddmdp !*+(0018000000b77501,0123214569900000,fff0000000000000) AND !*+(7fe800000000051b,0123214569900000,c0d0650f5a07b353) => 7ff0000000000000 c11bab9728b78ae5
+#17: xvnmaddmdp !*+(0123214569900000,0123214569900000,8000000000000000) AND !*+(0000000000000000,0123214569900000,0000000000000000) => 8000000000000000 8000000000000000
+#18: xvnmaddmdp !*+(8000000000000000,0123214569900000,404f000000000000) AND !*+(7ff0000000000000,0123214569900000,7ff0000000000000) => c04f000000000000 fff0000000000000
+#19: xvnmaddmdp !*+(fff0000000000000,0123214569900000,7ff7ffffffffffff) AND !*+(7ff7ffffffffffff,0123214569900000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#20: xvnmaddmdp !*+(fff7ffffffffffff,7ff0000000000000,fff0000000000000) AND !*+(7ff8000000000000,7ff0000000000000,c0d0650f5a07b353) => ffffffffffffffff 7ff8000000000000
+#21: xvnmaddmdp !*+(fff8000000000000,7ff0000000000000,8000000000000000) AND !*+(8008340000078000,7ff0000000000000,0000000000000000) => fff8000000000000 7ff0000000000000
+#22: xvnmaddmdp !*+(c0d0650f5a07b353,7ff0000000000000,0123214569900000) AND !*+(41232585a9900000,7ff0000000000000,7ff0000000000000) => 7ff0000000000000 fff0000000000000
+#23: xvnmaddmdp !*+(404f000000000000,7ff0000000000000,7ff7ffffffffffff) AND !*+(0018000000b77501,7ff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#24: xvnmaddmdp !*+(7fe800000000051b,fff7ffffffffffff,fff0000000000000) AND !*+(0123214569900000,fff7ffffffffffff,c0d0650f5a07b353) => ffffffffffffffff ffffffffffffffff
+#25: xvnmaddmdp !*+(0000000000000000,fff8000000000000,8000000000000000) AND !*+(8000000000000000,fff8000000000000,0000000000000000) => fff8000000000000 fff8000000000000
+#26: xvnmaddmdp !*+(7ff0000000000000,fff7ffffffffffff,0123214569900000) AND !*+(fff0000000000000,fff7ffffffffffff,7ff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvnmaddmdp !*+(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND !*+(fff7ffffffffffff,fff7ffffffffffff,7ff8000000000000) => ffffffffffffffff ffffffffffffffff
+#28: xvnmaddmdp !*+(7ff8000000000000,fff8000000000000,fff0000000000000) AND !*+(fff8000000000000,fff8000000000000,c0d0650f5a07b353) => fff8000000000000 fff8000000000000
+#29: xvnmaddmdp !*+(8008340000078000,fff8000000000000,8000000000000000) AND !*+(c0d0650f5a07b353,41232585a9900000,41382511a2000000) => fff8000000000000 42039db3bbaae2d2
+#30: xvnmaddmdp !*+(3fd8000000000000,41232585a9900000,41382511a2000000) AND !*+(404f000000000000,7ff7ffffffffffff,7ff8000000000000) => c13bbc1ab1cb0000 7fffffffffffffff
+#31: xvnmaddmdp !*+(0018000000b77501,7ff8000000000000,7ff8000000000000) AND !*+(7fe800000000051b,7ff8000000000000,fff8000000000000) => 7ff8000000000000 7ff8000000000000
+
+#0: xvnmaddasp !*+(ff800000,ff800000,3ec00000) AND !*+(c683287b,ff800000,42780000) AND !*+(49c1288d,49192c2d,00000000) AND !*+(00000000,ff800000,7f800000) => 7f800000 7f800000 c9c1288d 7f800000
+#1: xvnmaddasp !*+(00000000,ff800000,00000000) AND !*+(7f800000,ff800000,00000000) AND !*+(7fffffff,ff800000,80000000) AND !*+(7fc00000,ff800000,7f800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvnmaddasp !*+(ff800000,c683287b,ff800000) AND !*+(c683287b,c683287b,7fffffff) AND !*+(80000000,c683287b,ffffffff) AND !*+(00000000,c683287b,7fc00000) => 7fc00000 7fffffff ffffffff 7fc00000
+#3: xvnmaddasp !*+(00000000,c683287b,ffc00000) AND !*+(7f800000,c683287b,80000000) AND !*+(7fffffff,c683287b,c683287b) AND !*+(7fc00000,c683287b,49192c2d) => ffc00000 ff800000 7fffffff 7fc00000
+#4: xvnmaddasp !*+(ff800000,80000000,7f800000) AND !*+(c683287b,80000000,00000000) AND !*+(80000000,80000000,00000000) AND !*+(00000000,80000000,80000000) => 7fc00000 4683287b 00000000 80000000
+#5: xvnmaddasp !*+(00000000,80000000,7f800000) AND !*+(7f800000,80000000,ff800000) AND !*+(7fffffff,80000000,7fffffff) AND !*+(7fc00000,80000000,ffffffff) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvnmaddasp !*+(ff800000,00000000,7fc00000) AND !*+(c683287b,00000000,ffc00000) AND !*+(80000000,00000000,80000000) AND !*+(00000000,00000000,c683287b) => 7fc00000 ffc00000 00000000 80000000
+#7: xvnmaddasp !*+(00000000,00000000,00000000) AND !*+(7f800000,00000000,7f800000) AND !*+(7fffffff,00000000,00000000) AND !*+(7fc00000,00000000,00000000) => 80000000 7fc00000 7fffffff 7fc00000
+#8: xvnmaddasp !*+(ff800000,00000000,80000000) AND !*+(c683287b,00000000,7f800000) AND !*+(80000000,00000000,ff800000) AND !*+(00000000,00000000,7fffffff) => 7f800000 7fc00000 7fc00000 7fffffff
+#9: xvnmaddasp !*+(42780000,00000000,ffffffff) AND !*+(7f800000,00000000,7fc00000) AND !*+(7fffffff,00000000,ffc00000) AND !*+(7fc00000,00000000,80000000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvnmaddasp !*+(ff800000,7f800000,42780000) AND !*+(c683287b,7f800000,00000000) AND !*+(80000000,7f800000,7f800000) AND !*+(00000000,7f800000,00000000) => 7fc00000 7fc00000 ff800000 7fc00000
+#11: xvnmaddasp !*+(00000000,7f800000,00000000) AND !*+(7f800000,7f800000,80000000) AND !*+(7fffffff,7f800000,7f800000) AND !*+(7fc00000,7f800000,ff800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvnmaddasp !*+(ff800000,ffffffff,7fffffff) AND !*+(c683287b,ffffffff,ffffffff) AND !*+(80000000,ffc00000,7fc00000) AND !*+(00000000,ffc00000,ffc00000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvnmaddasp !*+(00000000,ffffffff,3ec00000) AND !*+(7f800000,ffffffff,42780000) AND !*+(7fffffff,ffffffff,00000000) AND !*+(7fc00000,ffffffff,7f800000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvnmaddasp !*+(ff800000,ffc00000,00000000) AND !*+(c683287b,ffc00000,00000000) AND !*+(80000000,ffc00000,80000000) AND !*+(49c1288d,49192c2d,7f800000) => ffc00000 ffc00000 ffc00000 ff800000
+#15: xvnmaddasp !*+(49c1288d,49192c2d,ff800000) AND !*+(7fc00000,7fffffff,7fffffff) AND !*+(7fc00000,7fc00000,ffffffff) AND !*+(ffc00000,7fc00000,7fc00000) => 7f800000 7fffffff 7fc00000 7fc00000
+
+#0: xvnmaddmsp !*+(3ec00000,ff800000,ff800000) AND !*+(42780000,ff800000,c683287b) AND !*+(00000000,49192c2d,49c1288d) AND !*+(7f800000,ff800000,00000000) => 7f800000 7f800000 c9c1288d 7f800000
+#1: xvnmaddmsp !*+(00000000,ff800000,00000000) AND !*+(00000000,ff800000,7f800000) AND !*+(80000000,ff800000,7fffffff) AND !*+(7f800000,ff800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvnmaddmsp !*+(ff800000,c683287b,ff800000) AND !*+(7fffffff,c683287b,c683287b) AND !*+(ffffffff,c683287b,80000000) AND !*+(7fc00000,c683287b,00000000) => 7fc00000 7fffffff ffffffff 7fc00000
+#3: xvnmaddmsp !*+(ffc00000,c683287b,00000000) AND !*+(80000000,c683287b,7f800000) AND !*+(c683287b,c683287b,7fffffff) AND !*+(49192c2d,c683287b,7fc00000) => ffc00000 ff800000 7fffffff 7fc00000
+#4: xvnmaddmsp !*+(7f800000,80000000,ff800000) AND !*+(00000000,80000000,c683287b) AND !*+(00000000,80000000,80000000) AND !*+(80000000,80000000,00000000) => 7fc00000 4683287b 00000000 80000000
+#5: xvnmaddmsp !*+(7f800000,80000000,00000000) AND !*+(ff800000,80000000,7f800000) AND !*+(7fffffff,80000000,7fffffff) AND !*+(ffffffff,80000000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvnmaddmsp !*+(7fc00000,00000000,ff800000) AND !*+(ffc00000,00000000,c683287b) AND !*+(80000000,00000000,80000000) AND !*+(c683287b,00000000,00000000) => 7fc00000 ffc00000 00000000 80000000
+#7: xvnmaddmsp !*+(00000000,00000000,00000000) AND !*+(7f800000,00000000,7f800000) AND !*+(00000000,00000000,7fffffff) AND !*+(00000000,00000000,7fc00000) => 80000000 7fc00000 7fffffff 7fc00000
+#8: xvnmaddmsp !*+(80000000,00000000,ff800000) AND !*+(7f800000,00000000,c683287b) AND !*+(ff800000,00000000,80000000) AND !*+(7fffffff,00000000,00000000) => 7f800000 7fc00000 7fc00000 7fffffff
+#9: xvnmaddmsp !*+(ffffffff,00000000,42780000) AND !*+(7fc00000,00000000,7f800000) AND !*+(ffc00000,00000000,7fffffff) AND !*+(80000000,00000000,7fc00000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvnmaddmsp !*+(42780000,7f800000,ff800000) AND !*+(00000000,7f800000,c683287b) AND !*+(7f800000,7f800000,80000000) AND !*+(00000000,7f800000,00000000) => 7fc00000 7fc00000 ff800000 7fc00000
+#11: xvnmaddmsp !*+(00000000,7f800000,00000000) AND !*+(80000000,7f800000,7f800000) AND !*+(7f800000,7f800000,7fffffff) AND !*+(ff800000,7f800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvnmaddmsp !*+(7fffffff,ffffffff,ff800000) AND !*+(ffffffff,ffffffff,c683287b) AND !*+(7fc00000,ffc00000,80000000) AND !*+(ffc00000,ffc00000,00000000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvnmaddmsp !*+(3ec00000,ffffffff,00000000) AND !*+(42780000,ffffffff,7f800000) AND !*+(00000000,ffffffff,7fffffff) AND !*+(7f800000,ffffffff,7fc00000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvnmaddmsp !*+(00000000,ffc00000,ff800000) AND !*+(00000000,ffc00000,c683287b) AND !*+(80000000,ffc00000,80000000) AND !*+(7f800000,49192c2d,49c1288d) => ffc00000 ffc00000 ffc00000 ff800000
+#15: xvnmaddmsp !*+(ff800000,49192c2d,49c1288d) AND !*+(7fffffff,7fffffff,7fc00000) AND !*+(ffffffff,7fc00000,7fc00000) AND !*+(7fc00000,7fc00000,ffc00000) => 7f800000 7fffffff 7fc00000 7fc00000
+
+#0: xvmsubadp *-(fff0000000000000,fff0000000000000,3fd8000000000000) AND *-(c0d0650f5a07b353,fff0000000000000,404f000000000000) => 7ff8000000000000 fff0000000000000
+#1: xvmsubadp *-(41382511a2000000,41232585a9900000,0018000000b77501) AND *-(0000000000000000,fff0000000000000,7fe800000000051b) => c1382511a2000000 fff0000000000000
+#2: xvmsubadp *-(0123214569900000,fff0000000000000,0123214569900000) AND *-(7ff0000000000000,fff0000000000000,0000000000000000) => fff0000000000000 7ff8000000000000
+#3: xvmsubadp *-(7ff7ffffffffffff,fff0000000000000,8000000000000000) AND *-(7ff8000000000000,fff0000000000000,7ff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvmsubadp *-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND *-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) => 7ff0000000000000 7fffffffffffffff
+#5: xvmsubadp *-(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) AND *-(0000000000000000,c0d0650f5a07b353,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvmsubadp *-(0123214569900000,c0d0650f5a07b353,fff8000000000000) AND *-(7ff0000000000000,c0d0650f5a07b353,8008340000078000) => fff8000000000000 fff0000000000000
+#7: xvmsubadp *-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) AND *-(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) => 7fffffffffffffff 7ff8000000000000
+#8: xvmsubadp *-(fff0000000000000,8000000000000000,404f000000000000) AND *-(c0d0650f5a07b353,8000000000000000,0018000000b77501) => 7ff0000000000000 40d0650f5a07b353
+#9: xvmsubadp *-(8000000000000000,8000000000000000,7fe800000000051b) AND *-(0000000000000000,8000000000000000,0123214569900000) => 0000000000000000 8000000000000000
+#10: xvmsubadp *-(0123214569900000,8000000000000000,0000000000000000) AND *-(7ff0000000000000,8000000000000000,8000000000000000) => 8123214569900000 fff0000000000000
+#11: xvmsubadp *-(7ff7ffffffffffff,8000000000000000,7ff0000000000000) AND *-(7ff8000000000000,8000000000000000,fff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvmsubadp *-(fff0000000000000,0000000000000000,7ff7ffffffffffff) AND *-(c0d0650f5a07b353,0000000000000000,fff7ffffffffffff) => 7fffffffffffffff ffffffffffffffff
+#13: xvmsubadp *-(8000000000000000,0000000000000000,7ff8000000000000) AND *-(0000000000000000,0000000000000000,fff8000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvmsubadp *-(0123214569900000,0000000000000000,8008340000078000) AND *-(7ff0000000000000,0000000000000000,c0d0650f5a07b353) => 8123214569900000 fff0000000000000
+#15: xvmsubadp *-(7ff7ffffffffffff,0000000000000000,3fd8000000000000) AND *-(7ff8000000000000,0000000000000000,404f000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvmsubadp *-(fff0000000000000,0123214569900000,0018000000b77501) AND *-(c0d0650f5a07b353,0123214569900000,7fe800000000051b) => 7ff0000000000000 411db83913f88150
+#17: xvmsubadp *-(8000000000000000,0123214569900000,0123214569900000) AND *-(0000000000000000,0123214569900000,0000000000000000) => 0000000000000000 0000000000000000
+#18: xvmsubadp *-(404f000000000000,0123214569900000,8000000000000000) AND *-(7ff0000000000000,0123214569900000,7ff0000000000000) => c04f000000000000 7ff8000000000000
+#19: xvmsubadp *-(7ff7ffffffffffff,0123214569900000,fff0000000000000) AND *-(7ff8000000000000,0123214569900000,7ff7ffffffffffff) => 7fffffffffffffff 7ff8000000000000
+#20: xvmsubadp *-(fff0000000000000,7ff0000000000000,fff7ffffffffffff) AND *-(c0d0650f5a07b353,7ff0000000000000,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#21: xvmsubadp *-(8000000000000000,7ff0000000000000,fff8000000000000) AND *-(0000000000000000,7ff0000000000000,8008340000078000) => fff8000000000000 fff0000000000000
+#22: xvmsubadp *-(0123214569900000,7ff0000000000000,c0d0650f5a07b353) AND *-(7ff0000000000000,7ff0000000000000,41232585a9900000) => fff0000000000000 7ff8000000000000
+#23: xvmsubadp *-(7ff7ffffffffffff,7ff0000000000000,404f000000000000) AND *-(7ff8000000000000,7ff0000000000000,0018000000b77501) => 7fffffffffffffff 7ff8000000000000
+#24: xvmsubadp *-(fff0000000000000,fff7ffffffffffff,7fe800000000051b) AND *-(c0d0650f5a07b353,fff7ffffffffffff,0123214569900000) => ffffffffffffffff ffffffffffffffff
+#25: xvmsubadp *-(8000000000000000,fff8000000000000,0000000000000000) AND *-(0000000000000000,fff8000000000000,8000000000000000) => fff8000000000000 fff8000000000000
+#26: xvmsubadp *-(0123214569900000,fff7ffffffffffff,7ff0000000000000) AND *-(7ff0000000000000,fff7ffffffffffff,fff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvmsubadp *-(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND *-(7ff8000000000000,fff7ffffffffffff,fff7ffffffffffff) => ffffffffffffffff ffffffffffffffff
+#28: xvmsubadp *-(fff0000000000000,fff8000000000000,7ff8000000000000) AND *-(c0d0650f5a07b353,fff8000000000000,fff8000000000000) => fff8000000000000 fff8000000000000
+#29: xvmsubadp *-(8000000000000000,fff8000000000000,8008340000078000) AND *-(41382511a2000000,41232585a9900000,c0d0650f5a07b353) => fff8000000000000 c2039f360cc502d2
+#30: xvmsubadp *-(41382511a2000000,41232585a9900000,3fd8000000000000) AND *-(7ff8000000000000,7ff7ffffffffffff,404f000000000000) => c1348e0892350000 7fffffffffffffff
+#31: xvmsubadp *-(7ff8000000000000,7ff8000000000000,0018000000b77501) AND *-(fff8000000000000,7ff8000000000000,7fe800000000051b) => 7ff8000000000000 7ff8000000000000
+
+#0: xvmsubmdp *-(3fd8000000000000,fff0000000000000,fff0000000000000) AND *-(404f000000000000,fff0000000000000,c0d0650f5a07b353) => 7ff8000000000000 fff0000000000000
+#1: xvmsubmdp *-(0018000000b77501,41232585a9900000,41382511a2000000) AND *-(7fe800000000051b,fff0000000000000,0000000000000000) => c1382511a2000000 fff0000000000000
+#2: xvmsubmdp *-(0123214569900000,fff0000000000000,0123214569900000) AND *-(0000000000000000,fff0000000000000,7ff0000000000000) => fff0000000000000 7ff8000000000000
+#3: xvmsubmdp *-(8000000000000000,fff0000000000000,7ff7ffffffffffff) AND *-(7ff0000000000000,fff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvmsubmdp *-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND *-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) => 7ff0000000000000 7fffffffffffffff
+#5: xvmsubmdp *-(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) AND *-(7ff8000000000000,c0d0650f5a07b353,0000000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvmsubmdp *-(fff8000000000000,c0d0650f5a07b353,0123214569900000) AND *-(8008340000078000,c0d0650f5a07b353,7ff0000000000000) => fff8000000000000 fff0000000000000
+#7: xvmsubmdp *-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) AND *-(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#8: xvmsubmdp *-(404f000000000000,8000000000000000,fff0000000000000) AND *-(0018000000b77501,8000000000000000,c0d0650f5a07b353) => 7ff0000000000000 40d0650f5a07b353
+#9: xvmsubmdp *-(7fe800000000051b,8000000000000000,8000000000000000) AND *-(0123214569900000,8000000000000000,0000000000000000) => 0000000000000000 8000000000000000
+#10: xvmsubmdp *-(0000000000000000,8000000000000000,0123214569900000) AND *-(8000000000000000,8000000000000000,7ff0000000000000) => 8123214569900000 fff0000000000000
+#11: xvmsubmdp *-(7ff0000000000000,8000000000000000,7ff7ffffffffffff) AND *-(fff0000000000000,8000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvmsubmdp *-(7ff7ffffffffffff,0000000000000000,fff0000000000000) AND *-(fff7ffffffffffff,0000000000000000,c0d0650f5a07b353) => 7fffffffffffffff ffffffffffffffff
+#13: xvmsubmdp *-(7ff8000000000000,0000000000000000,8000000000000000) AND *-(fff8000000000000,0000000000000000,0000000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvmsubmdp *-(8008340000078000,0000000000000000,0123214569900000) AND *-(c0d0650f5a07b353,0000000000000000,7ff0000000000000) => 8123214569900000 fff0000000000000
+#15: xvmsubmdp *-(3fd8000000000000,0000000000000000,7ff7ffffffffffff) AND *-(404f000000000000,0000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvmsubmdp *-(0018000000b77501,0123214569900000,fff0000000000000) AND *-(7fe800000000051b,0123214569900000,c0d0650f5a07b353) => 7ff0000000000000 411db83913f88150
+#17: xvmsubmdp *-(0123214569900000,0123214569900000,8000000000000000) AND *-(0000000000000000,0123214569900000,0000000000000000) => 0000000000000000 0000000000000000
+#18: xvmsubmdp *-(8000000000000000,0123214569900000,404f000000000000) AND *-(7ff0000000000000,0123214569900000,7ff0000000000000) => c04f000000000000 7ff8000000000000
+#19: xvmsubmdp *-(fff0000000000000,0123214569900000,7ff7ffffffffffff) AND *-(7ff7ffffffffffff,0123214569900000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#20: xvmsubmdp *-(fff7ffffffffffff,7ff0000000000000,fff0000000000000) AND *-(7ff8000000000000,7ff0000000000000,c0d0650f5a07b353) => ffffffffffffffff 7ff8000000000000
+#21: xvmsubmdp *-(fff8000000000000,7ff0000000000000,8000000000000000) AND *-(8008340000078000,7ff0000000000000,0000000000000000) => fff8000000000000 fff0000000000000
+#22: xvmsubmdp *-(c0d0650f5a07b353,7ff0000000000000,0123214569900000) AND *-(41232585a9900000,7ff0000000000000,7ff0000000000000) => fff0000000000000 7ff8000000000000
+#23: xvmsubmdp *-(404f000000000000,7ff0000000000000,7ff7ffffffffffff) AND *-(0018000000b77501,7ff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#24: xvmsubmdp *-(7fe800000000051b,fff7ffffffffffff,fff0000000000000) AND *-(0123214569900000,fff7ffffffffffff,c0d0650f5a07b353) => ffffffffffffffff ffffffffffffffff
+#25: xvmsubmdp *-(0000000000000000,fff8000000000000,8000000000000000) AND *-(8000000000000000,fff8000000000000,0000000000000000) => fff8000000000000 fff8000000000000
+#26: xvmsubmdp *-(7ff0000000000000,fff7ffffffffffff,0123214569900000) AND *-(fff0000000000000,fff7ffffffffffff,7ff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvmsubmdp *-(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND *-(fff7ffffffffffff,fff7ffffffffffff,7ff8000000000000) => ffffffffffffffff ffffffffffffffff
+#28: xvmsubmdp *-(7ff8000000000000,fff8000000000000,fff0000000000000) AND *-(fff8000000000000,fff8000000000000,c0d0650f5a07b353) => fff8000000000000 fff8000000000000
+#29: xvmsubmdp *-(8008340000078000,fff8000000000000,8000000000000000) AND *-(c0d0650f5a07b353,41232585a9900000,41382511a2000000) => fff8000000000000 c2039f360cc502d2
+#30: xvmsubmdp *-(3fd8000000000000,41232585a9900000,41382511a2000000) AND *-(404f000000000000,7ff7ffffffffffff,7ff8000000000000) => c1348e0892350000 7fffffffffffffff
+#31: xvmsubmdp *-(0018000000b77501,7ff8000000000000,7ff8000000000000) AND *-(7fe800000000051b,7ff8000000000000,fff8000000000000) => 7ff8000000000000 7ff8000000000000
+
+#0: xvmsubasp *-(ff800000,ff800000,3ec00000) AND *-(c683287b,ff800000,42780000) AND *-(49c1288d,49192c2d,00000000) AND *-(00000000,ff800000,7f800000) => 7fc00000 ff800000 c9c1288d ff800000
+#1: xvmsubasp *-(00000000,ff800000,00000000) AND *-(7f800000,ff800000,00000000) AND *-(7fffffff,ff800000,80000000) AND *-(7fc00000,ff800000,7f800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvmsubasp *-(ff800000,c683287b,ff800000) AND *-(c683287b,c683287b,7fffffff) AND *-(80000000,c683287b,ffffffff) AND *-(00000000,c683287b,7fc00000) => 7f800000 7fffffff ffffffff 7fc00000
+#3: xvmsubasp *-(00000000,c683287b,ffc00000) AND *-(7f800000,c683287b,80000000) AND *-(7fffffff,c683287b,c683287b) AND *-(7fc00000,c683287b,49192c2d) => ffc00000 ff800000 7fffffff 7fc00000
+#4: xvmsubasp *-(ff800000,80000000,7f800000) AND *-(c683287b,80000000,00000000) AND *-(80000000,80000000,00000000) AND *-(00000000,80000000,80000000) => 7fc00000 4683287b 00000000 00000000
+#5: xvmsubasp *-(00000000,80000000,7f800000) AND *-(7f800000,80000000,ff800000) AND *-(7fffffff,80000000,7fffffff) AND *-(7fc00000,80000000,ffffffff) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvmsubasp *-(ff800000,00000000,7fc00000) AND *-(c683287b,00000000,ffc00000) AND *-(80000000,00000000,80000000) AND *-(00000000,00000000,c683287b) => 7fc00000 ffc00000 00000000 80000000
+#7: xvmsubasp *-(00000000,00000000,00000000) AND *-(7f800000,00000000,7f800000) AND *-(7fffffff,00000000,00000000) AND *-(7fc00000,00000000,00000000) => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmsubasp *-(ff800000,00000000,80000000) AND *-(c683287b,00000000,7f800000) AND *-(80000000,00000000,ff800000) AND *-(00000000,00000000,7fffffff) => 7f800000 7fc00000 7fc00000 7fffffff
+#9: xvmsubasp *-(42780000,00000000,ffffffff) AND *-(7f800000,00000000,7fc00000) AND *-(7fffffff,00000000,ffc00000) AND *-(7fc00000,00000000,80000000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvmsubasp *-(ff800000,7f800000,42780000) AND *-(c683287b,7f800000,00000000) AND *-(80000000,7f800000,7f800000) AND *-(00000000,7f800000,00000000) => 7f800000 7fc00000 7f800000 7fc00000
+#11: xvmsubasp *-(00000000,7f800000,00000000) AND *-(7f800000,7f800000,80000000) AND *-(7fffffff,7f800000,7f800000) AND *-(7fc00000,7f800000,ff800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvmsubasp *-(ff800000,ffffffff,7fffffff) AND *-(c683287b,ffffffff,ffffffff) AND *-(80000000,ffc00000,7fc00000) AND *-(00000000,ffc00000,ffc00000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmsubasp *-(00000000,ffffffff,3ec00000) AND *-(7f800000,ffffffff,42780000) AND *-(7fffffff,ffffffff,00000000) AND *-(7fc00000,ffffffff,7f800000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvmsubasp *-(ff800000,ffc00000,00000000) AND *-(c683287b,ffc00000,00000000) AND *-(80000000,ffc00000,80000000) AND *-(49c1288d,49192c2d,7f800000) => ffc00000 ffc00000 ffc00000 7f800000
+#15: xvmsubasp *-(49c1288d,49192c2d,ff800000) AND *-(7fc00000,7fffffff,7fffffff) AND *-(7fc00000,7fc00000,ffffffff) AND *-(ffc00000,7fc00000,7fc00000) => ff800000 7fffffff 7fc00000 7fc00000
+
+#0: xvmsubmsp *-(3ec00000,ff800000,ff800000) AND *-(42780000,ff800000,c683287b) AND *-(00000000,49192c2d,49c1288d) AND *-(7f800000,ff800000,00000000) => 7fc00000 ff800000 c9c1288d ff800000
+#1: xvmsubmsp *-(00000000,ff800000,00000000) AND *-(00000000,ff800000,7f800000) AND *-(80000000,ff800000,7fffffff) AND *-(7f800000,ff800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvmsubmsp *-(ff800000,c683287b,ff800000) AND *-(7fffffff,c683287b,c683287b) AND *-(ffffffff,c683287b,80000000) AND *-(7fc00000,c683287b,00000000) => 7f800000 7fffffff ffffffff 7fc00000
+#3: xvmsubmsp *-(ffc00000,c683287b,00000000) AND *-(80000000,c683287b,7f800000) AND *-(c683287b,c683287b,7fffffff) AND *-(49192c2d,c683287b,7fc00000) => ffc00000 ff800000 7fffffff 7fc00000
+#4: xvmsubmsp *-(7f800000,80000000,ff800000) AND *-(00000000,80000000,c683287b) AND *-(00000000,80000000,80000000) AND *-(80000000,80000000,00000000) => 7fc00000 4683287b 00000000 00000000
+#5: xvmsubmsp *-(7f800000,80000000,00000000) AND *-(ff800000,80000000,7f800000) AND *-(7fffffff,80000000,7fffffff) AND *-(ffffffff,80000000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvmsubmsp *-(7fc00000,00000000,ff800000) AND *-(ffc00000,00000000,c683287b) AND *-(80000000,00000000,80000000) AND *-(c683287b,00000000,00000000) => 7fc00000 ffc00000 00000000 80000000
+#7: xvmsubmsp *-(00000000,00000000,00000000) AND *-(7f800000,00000000,7f800000) AND *-(00000000,00000000,7fffffff) AND *-(00000000,00000000,7fc00000) => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmsubmsp *-(80000000,00000000,ff800000) AND *-(7f800000,00000000,c683287b) AND *-(ff800000,00000000,80000000) AND *-(7fffffff,00000000,00000000) => 7f800000 7fc00000 7fc00000 7fffffff
+#9: xvmsubmsp *-(ffffffff,00000000,42780000) AND *-(7fc00000,00000000,7f800000) AND *-(ffc00000,00000000,7fffffff) AND *-(80000000,00000000,7fc00000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvmsubmsp *-(42780000,7f800000,ff800000) AND *-(00000000,7f800000,c683287b) AND *-(7f800000,7f800000,80000000) AND *-(00000000,7f800000,00000000) => 7f800000 7fc00000 7f800000 7fc00000
+#11: xvmsubmsp *-(00000000,7f800000,00000000) AND *-(80000000,7f800000,7f800000) AND *-(7f800000,7f800000,7fffffff) AND *-(ff800000,7f800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvmsubmsp *-(7fffffff,ffffffff,ff800000) AND *-(ffffffff,ffffffff,c683287b) AND *-(7fc00000,ffc00000,80000000) AND *-(ffc00000,ffc00000,00000000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmsubmsp *-(3ec00000,ffffffff,00000000) AND *-(42780000,ffffffff,7f800000) AND *-(00000000,ffffffff,7fffffff) AND *-(7f800000,ffffffff,7fc00000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvmsubmsp *-(00000000,ffc00000,ff800000) AND *-(00000000,ffc00000,c683287b) AND *-(80000000,ffc00000,80000000) AND *-(7f800000,49192c2d,49c1288d) => ffc00000 ffc00000 ffc00000 7f800000
+#15: xvmsubmsp *-(ff800000,49192c2d,49c1288d) AND *-(7fffffff,7fffffff,7fc00000) AND *-(ffffffff,7fc00000,7fc00000) AND *-(7fc00000,7fc00000,ffc00000) => ff800000 7fffffff 7fc00000 7fc00000
+
+#0: xvnmsubadp !*-(fff0000000000000,fff0000000000000,3fd8000000000000) AND !*-(c0d0650f5a07b353,fff0000000000000,404f000000000000) => 7ff8000000000000 7ff0000000000000
+#1: xvnmsubadp !*-(41382511a2000000,41232585a9900000,0018000000b77501) AND !*-(0000000000000000,fff0000000000000,7fe800000000051b) => 41382511a2000000 7ff0000000000000
+#2: xvnmsubadp !*-(0123214569900000,fff0000000000000,0123214569900000) AND !*-(7ff0000000000000,fff0000000000000,0000000000000000) => 7ff0000000000000 7ff8000000000000
+#3: xvnmsubadp !*-(7ff7ffffffffffff,fff0000000000000,8000000000000000) AND !*-(7ff8000000000000,fff0000000000000,7ff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvnmsubadp !*-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND !*-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) => fff0000000000000 7fffffffffffffff
+#5: xvnmsubadp !*-(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) AND !*-(0000000000000000,c0d0650f5a07b353,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvnmsubadp !*-(0123214569900000,c0d0650f5a07b353,fff8000000000000) AND !*-(7ff0000000000000,c0d0650f5a07b353,8008340000078000) => fff8000000000000 7ff0000000000000
+#7: xvnmsubadp !*-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) AND !*-(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) => 7fffffffffffffff 7ff8000000000000
+#8: xvnmsubadp !*-(fff0000000000000,8000000000000000,404f000000000000) AND !*-(c0d0650f5a07b353,8000000000000000,0018000000b77501) => fff0000000000000 c0d0650f5a07b353
+#9: xvnmsubadp !*-(8000000000000000,8000000000000000,7fe800000000051b) AND !*-(0000000000000000,8000000000000000,0123214569900000) => 8000000000000000 0000000000000000
+#10: xvnmsubadp !*-(0123214569900000,8000000000000000,0000000000000000) AND !*-(7ff0000000000000,8000000000000000,8000000000000000) => 0123214569900000 7ff0000000000000
+#11: xvnmsubadp !*-(7ff7ffffffffffff,8000000000000000,7ff0000000000000) AND !*-(7ff8000000000000,8000000000000000,fff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvnmsubadp !*-(fff0000000000000,0000000000000000,7ff7ffffffffffff) AND !*-(c0d0650f5a07b353,0000000000000000,fff7ffffffffffff) => 7fffffffffffffff ffffffffffffffff
+#13: xvnmsubadp !*-(8000000000000000,0000000000000000,7ff8000000000000) AND !*-(0000000000000000,0000000000000000,fff8000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvnmsubadp !*-(0123214569900000,0000000000000000,8008340000078000) AND !*-(7ff0000000000000,0000000000000000,c0d0650f5a07b353) => 0123214569900000 7ff0000000000000
+#15: xvnmsubadp !*-(7ff7ffffffffffff,0000000000000000,3fd8000000000000) AND !*-(7ff8000000000000,0000000000000000,404f000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvnmsubadp !*-(fff0000000000000,0123214569900000,0018000000b77501) AND !*-(c0d0650f5a07b353,0123214569900000,7fe800000000051b) => fff0000000000000 c11db83913f88150
+#17: xvnmsubadp !*-(8000000000000000,0123214569900000,0123214569900000) AND !*-(0000000000000000,0123214569900000,0000000000000000) => 8000000000000000 8000000000000000
+#18: xvnmsubadp !*-(404f000000000000,0123214569900000,8000000000000000) AND !*-(7ff0000000000000,0123214569900000,7ff0000000000000) => 404f000000000000 7ff8000000000000
+#19: xvnmsubadp !*-(7ff7ffffffffffff,0123214569900000,fff0000000000000) AND !*-(7ff8000000000000,0123214569900000,7ff7ffffffffffff) => 7fffffffffffffff 7ff8000000000000
+#20: xvnmsubadp !*-(fff0000000000000,7ff0000000000000,fff7ffffffffffff) AND !*-(c0d0650f5a07b353,7ff0000000000000,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#21: xvnmsubadp !*-(8000000000000000,7ff0000000000000,fff8000000000000) AND !*-(0000000000000000,7ff0000000000000,8008340000078000) => fff8000000000000 7ff0000000000000
+#22: xvnmsubadp !*-(0123214569900000,7ff0000000000000,c0d0650f5a07b353) AND !*-(7ff0000000000000,7ff0000000000000,41232585a9900000) => 7ff0000000000000 7ff8000000000000
+#23: xvnmsubadp !*-(7ff7ffffffffffff,7ff0000000000000,404f000000000000) AND !*-(7ff8000000000000,7ff0000000000000,0018000000b77501) => 7fffffffffffffff 7ff8000000000000
+#24: xvnmsubadp !*-(fff0000000000000,fff7ffffffffffff,7fe800000000051b) AND !*-(c0d0650f5a07b353,fff7ffffffffffff,0123214569900000) => ffffffffffffffff ffffffffffffffff
+#25: xvnmsubadp !*-(8000000000000000,fff8000000000000,0000000000000000) AND !*-(0000000000000000,fff8000000000000,8000000000000000) => fff8000000000000 fff8000000000000
+#26: xvnmsubadp !*-(0123214569900000,fff7ffffffffffff,7ff0000000000000) AND !*-(7ff0000000000000,fff7ffffffffffff,fff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvnmsubadp !*-(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND !*-(7ff8000000000000,fff7ffffffffffff,fff7ffffffffffff) => ffffffffffffffff ffffffffffffffff
+#28: xvnmsubadp !*-(fff0000000000000,fff8000000000000,7ff8000000000000) AND !*-(c0d0650f5a07b353,fff8000000000000,fff8000000000000) => fff8000000000000 fff8000000000000
+#29: xvnmsubadp !*-(8000000000000000,fff8000000000000,8008340000078000) AND !*-(41382511a2000000,41232585a9900000,c0d0650f5a07b353) => fff8000000000000 42039f360cc502d2
+#30: xvnmsubadp !*-(41382511a2000000,41232585a9900000,3fd8000000000000) AND !*-(7ff8000000000000,7ff7ffffffffffff,404f000000000000) => 41348e0892350000 7fffffffffffffff
+#31: xvnmsubadp !*-(7ff8000000000000,7ff8000000000000,0018000000b77501) AND !*-(fff8000000000000,7ff8000000000000,7fe800000000051b) => 7ff8000000000000 7ff8000000000000
+
+#0: xvnmsubmdp !*-(3fd8000000000000,fff0000000000000,fff0000000000000) AND !*-(404f000000000000,fff0000000000000,c0d0650f5a07b353) => 7ff8000000000000 7ff0000000000000
+#1: xvnmsubmdp !*-(0018000000b77501,41232585a9900000,41382511a2000000) AND !*-(7fe800000000051b,fff0000000000000,0000000000000000) => 41382511a2000000 7ff0000000000000
+#2: xvnmsubmdp !*-(0123214569900000,fff0000000000000,0123214569900000) AND !*-(0000000000000000,fff0000000000000,7ff0000000000000) => 7ff0000000000000 7ff8000000000000
+#3: xvnmsubmdp !*-(8000000000000000,fff0000000000000,7ff7ffffffffffff) AND !*-(7ff0000000000000,fff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvnmsubmdp !*-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND !*-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) => fff0000000000000 7fffffffffffffff
+#5: xvnmsubmdp !*-(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) AND !*-(7ff8000000000000,c0d0650f5a07b353,0000000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvnmsubmdp !*-(fff8000000000000,c0d0650f5a07b353,0123214569900000) AND !*-(8008340000078000,c0d0650f5a07b353,7ff0000000000000) => fff8000000000000 7ff0000000000000
+#7: xvnmsubmdp !*-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) AND !*-(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#8: xvnmsubmdp !*-(404f000000000000,8000000000000000,fff0000000000000) AND !*-(0018000000b77501,8000000000000000,c0d0650f5a07b353) => fff0000000000000 c0d0650f5a07b353
+#9: xvnmsubmdp !*-(7fe800000000051b,8000000000000000,8000000000000000) AND !*-(0123214569900000,8000000000000000,0000000000000000) => 8000000000000000 0000000000000000
+#10: xvnmsubmdp !*-(0000000000000000,8000000000000000,0123214569900000) AND !*-(8000000000000000,8000000000000000,7ff0000000000000) => 0123214569900000 7ff0000000000000
+#11: xvnmsubmdp !*-(7ff0000000000000,8000000000000000,7ff7ffffffffffff) AND !*-(fff0000000000000,8000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvnmsubmdp !*-(7ff7ffffffffffff,0000000000000000,fff0000000000000) AND !*-(fff7ffffffffffff,0000000000000000,c0d0650f5a07b353) => 7fffffffffffffff ffffffffffffffff
+#13: xvnmsubmdp !*-(7ff8000000000000,0000000000000000,8000000000000000) AND !*-(fff8000000000000,0000000000000000,0000000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvnmsubmdp !*-(8008340000078000,0000000000000000,0123214569900000) AND !*-(c0d0650f5a07b353,0000000000000000,7ff0000000000000) => 0123214569900000 7ff0000000000000
+#15: xvnmsubmdp !*-(3fd8000000000000,0000000000000000,7ff7ffffffffffff) AND !*-(404f000000000000,0000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvnmsubmdp !*-(0018000000b77501,0123214569900000,fff0000000000000) AND !*-(7fe800000000051b,0123214569900000,c0d0650f5a07b353) => fff0000000000000 c11db83913f88150
+#17: xvnmsubmdp !*-(0123214569900000,0123214569900000,8000000000000000) AND !*-(0000000000000000,0123214569900000,0000000000000000) => 8000000000000000 8000000000000000
+#18: xvnmsubmdp !*-(8000000000000000,0123214569900000,404f000000000000) AND !*-(7ff0000000000000,0123214569900000,7ff0000000000000) => 404f000000000000 7ff8000000000000
+#19: xvnmsubmdp !*-(fff0000000000000,0123214569900000,7ff7ffffffffffff) AND !*-(7ff7ffffffffffff,0123214569900000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#20: xvnmsubmdp !*-(fff7ffffffffffff,7ff0000000000000,fff0000000000000) AND !*-(7ff8000000000000,7ff0000000000000,c0d0650f5a07b353) => ffffffffffffffff 7ff8000000000000
+#21: xvnmsubmdp !*-(fff8000000000000,7ff0000000000000,8000000000000000) AND !*-(8008340000078000,7ff0000000000000,0000000000000000) => fff8000000000000 7ff0000000000000
+#22: xvnmsubmdp !*-(c0d0650f5a07b353,7ff0000000000000,0123214569900000) AND !*-(41232585a9900000,7ff0000000000000,7ff0000000000000) => 7ff0000000000000 7ff8000000000000
+#23: xvnmsubmdp !*-(404f000000000000,7ff0000000000000,7ff7ffffffffffff) AND !*-(0018000000b77501,7ff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#24: xvnmsubmdp !*-(7fe800000000051b,fff7ffffffffffff,fff0000000000000) AND !*-(0123214569900000,fff7ffffffffffff,c0d0650f5a07b353) => ffffffffffffffff ffffffffffffffff
+#25: xvnmsubmdp !*-(0000000000000000,fff8000000000000,8000000000000000) AND !*-(8000000000000000,fff8000000000000,0000000000000000) => fff8000000000000 fff8000000000000
+#26: xvnmsubmdp !*-(7ff0000000000000,fff7ffffffffffff,0123214569900000) AND !*-(fff0000000000000,fff7ffffffffffff,7ff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvnmsubmdp !*-(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND !*-(fff7ffffffffffff,fff7ffffffffffff,7ff8000000000000) => ffffffffffffffff ffffffffffffffff
+#28: xvnmsubmdp !*-(7ff8000000000000,fff8000000000000,fff0000000000000) AND !*-(fff8000000000000,fff8000000000000,c0d0650f5a07b353) => fff8000000000000 fff8000000000000
+#29: xvnmsubmdp !*-(8008340000078000,fff8000000000000,8000000000000000) AND !*-(c0d0650f5a07b353,41232585a9900000,41382511a2000000) => fff8000000000000 42039f360cc502d2
+#30: xvnmsubmdp !*-(3fd8000000000000,41232585a9900000,41382511a2000000) AND !*-(404f000000000000,7ff7ffffffffffff,7ff8000000000000) => 41348e0892350000 7fffffffffffffff
+#31: xvnmsubmdp !*-(0018000000b77501,7ff8000000000000,7ff8000000000000) AND !*-(7fe800000000051b,7ff8000000000000,fff8000000000000) => 7ff8000000000000 7ff8000000000000
+
+#0: xvnmsubasp !*-(ff800000,ff800000,3ec00000) AND !*-(c683287b,ff800000,42780000) AND !*-(49c1288d,49192c2d,00000000) AND !*-(00000000,ff800000,7f800000) => 7fc00000 7f800000 49c1288d 7f800000
+#1: xvnmsubasp !*-(00000000,ff800000,00000000) AND !*-(7f800000,ff800000,00000000) AND !*-(7fffffff,ff800000,80000000) AND !*-(7fc00000,ff800000,7f800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvnmsubasp !*-(ff800000,c683287b,ff800000) AND !*-(c683287b,c683287b,7fffffff) AND !*-(80000000,c683287b,ffffffff) AND !*-(00000000,c683287b,7fc00000) => ff800000 7fffffff ffffffff 7fc00000
+#3: xvnmsubasp !*-(00000000,c683287b,ffc00000) AND !*-(7f800000,c683287b,80000000) AND !*-(7fffffff,c683287b,c683287b) AND !*-(7fc00000,c683287b,49192c2d) => ffc00000 7f800000 7fffffff 7fc00000
+#4: xvnmsubasp !*-(ff800000,80000000,7f800000) AND !*-(c683287b,80000000,00000000) AND !*-(80000000,80000000,00000000) AND !*-(00000000,80000000,80000000) => 7fc00000 c683287b 80000000 80000000
+#5: xvnmsubasp !*-(00000000,80000000,7f800000) AND !*-(7f800000,80000000,ff800000) AND !*-(7fffffff,80000000,7fffffff) AND !*-(7fc00000,80000000,ffffffff) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvnmsubasp !*-(ff800000,00000000,7fc00000) AND !*-(c683287b,00000000,ffc00000) AND !*-(80000000,00000000,80000000) AND !*-(00000000,00000000,c683287b) => 7fc00000 ffc00000 80000000 00000000
+#7: xvnmsubasp !*-(00000000,00000000,00000000) AND !*-(7f800000,00000000,7f800000) AND !*-(7fffffff,00000000,00000000) AND !*-(7fc00000,00000000,00000000) => 80000000 7fc00000 7fffffff 7fc00000
+#8: xvnmsubasp !*-(ff800000,00000000,80000000) AND !*-(c683287b,00000000,7f800000) AND !*-(80000000,00000000,ff800000) AND !*-(00000000,00000000,7fffffff) => ff800000 7fc00000 7fc00000 7fffffff
+#9: xvnmsubasp !*-(42780000,00000000,ffffffff) AND !*-(7f800000,00000000,7fc00000) AND !*-(7fffffff,00000000,ffc00000) AND !*-(7fc00000,00000000,80000000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvnmsubasp !*-(ff800000,7f800000,42780000) AND !*-(c683287b,7f800000,00000000) AND !*-(80000000,7f800000,7f800000) AND !*-(00000000,7f800000,00000000) => ff800000 7fc00000 ff800000 7fc00000
+#11: xvnmsubasp !*-(00000000,7f800000,00000000) AND !*-(7f800000,7f800000,80000000) AND !*-(7fffffff,7f800000,7f800000) AND !*-(7fc00000,7f800000,ff800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvnmsubasp !*-(ff800000,ffffffff,7fffffff) AND !*-(c683287b,ffffffff,ffffffff) AND !*-(80000000,ffc00000,7fc00000) AND !*-(00000000,ffc00000,ffc00000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvnmsubasp !*-(00000000,ffffffff,3ec00000) AND !*-(7f800000,ffffffff,42780000) AND !*-(7fffffff,ffffffff,00000000) AND !*-(7fc00000,ffffffff,7f800000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvnmsubasp !*-(ff800000,ffc00000,00000000) AND !*-(c683287b,ffc00000,00000000) AND !*-(80000000,ffc00000,80000000) AND !*-(49c1288d,49192c2d,7f800000) => ffc00000 ffc00000 ffc00000 ff800000
+#15: xvnmsubasp !*-(49c1288d,49192c2d,ff800000) AND !*-(7fc00000,7fffffff,7fffffff) AND !*-(7fc00000,7fc00000,ffffffff) AND !*-(ffc00000,7fc00000,7fc00000) => 7f800000 7fffffff 7fc00000 7fc00000
+
+#0: xvnmsubmsp !*-(3ec00000,ff800000,ff800000) AND !*-(42780000,ff800000,c683287b) AND !*-(00000000,49192c2d,49c1288d) AND !*-(7f800000,ff800000,00000000) => 7fc00000 7f800000 49c1288d 7f800000
+#1: xvnmsubmsp !*-(00000000,ff800000,00000000) AND !*-(00000000,ff800000,7f800000) AND !*-(80000000,ff800000,7fffffff) AND !*-(7f800000,ff800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvnmsubmsp !*-(ff800000,c683287b,ff800000) AND !*-(7fffffff,c683287b,c683287b) AND !*-(ffffffff,c683287b,80000000) AND !*-(7fc00000,c683287b,00000000) => ff800000 7fffffff ffffffff 7fc00000
+#3: xvnmsubmsp !*-(ffc00000,c683287b,00000000) AND !*-(80000000,c683287b,7f800000) AND !*-(c683287b,c683287b,7fffffff) AND !*-(49192c2d,c683287b,7fc00000) => ffc00000 7f800000 7fffffff 7fc00000
+#4: xvnmsubmsp !*-(7f800000,80000000,ff800000) AND !*-(00000000,80000000,c683287b) AND !*-(00000000,80000000,80000000) AND !*-(80000000,80000000,00000000) => 7fc00000 c683287b 80000000 80000000
+#5: xvnmsubmsp !*-(7f800000,80000000,00000000) AND !*-(ff800000,80000000,7f800000) AND !*-(7fffffff,80000000,7fffffff) AND !*-(ffffffff,80000000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvnmsubmsp !*-(7fc00000,00000000,ff800000) AND !*-(ffc00000,00000000,c683287b) AND !*-(80000000,00000000,80000000) AND !*-(c683287b,00000000,00000000) => 7fc00000 ffc00000 80000000 00000000
+#7: xvnmsubmsp !*-(00000000,00000000,00000000) AND !*-(7f800000,00000000,7f800000) AND !*-(00000000,00000000,7fffffff) AND !*-(00000000,00000000,7fc00000) => 80000000 7fc00000 7fffffff 7fc00000
+#8: xvnmsubmsp !*-(80000000,00000000,ff800000) AND !*-(7f800000,00000000,c683287b) AND !*-(ff800000,00000000,80000000) AND !*-(7fffffff,00000000,00000000) => ff800000 7fc00000 7fc00000 7fffffff
+#9: xvnmsubmsp !*-(ffffffff,00000000,42780000) AND !*-(7fc00000,00000000,7f800000) AND !*-(ffc00000,00000000,7fffffff) AND !*-(80000000,00000000,7fc00000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvnmsubmsp !*-(42780000,7f800000,ff800000) AND !*-(00000000,7f800000,c683287b) AND !*-(7f800000,7f800000,80000000) AND !*-(00000000,7f800000,00000000) => ff800000 7fc00000 ff800000 7fc00000
+#11: xvnmsubmsp !*-(00000000,7f800000,00000000) AND !*-(80000000,7f800000,7f800000) AND !*-(7f800000,7f800000,7fffffff) AND !*-(ff800000,7f800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvnmsubmsp !*-(7fffffff,ffffffff,ff800000) AND !*-(ffffffff,ffffffff,c683287b) AND !*-(7fc00000,ffc00000,80000000) AND !*-(ffc00000,ffc00000,00000000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvnmsubmsp !*-(3ec00000,ffffffff,00000000) AND !*-(42780000,ffffffff,7f800000) AND !*-(00000000,ffffffff,7fffffff) AND !*-(7f800000,ffffffff,7fc00000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvnmsubmsp !*-(00000000,ffc00000,ff800000) AND !*-(00000000,ffc00000,c683287b) AND !*-(80000000,ffc00000,80000000) AND !*-(7f800000,49192c2d,49c1288d) => ffc00000 ffc00000 ffc00000 ff800000
+#15: xvnmsubmsp !*-(ff800000,49192c2d,49c1288d) AND !*-(7fffffff,7fffffff,7fc00000) AND !*-(ffffffff,7fc00000,7fc00000) AND !*-(7fc00000,7fc00000,ffc00000) => 7f800000 7fffffff 7fc00000 7fc00000
+
+
+Test scalar floating point arithmetic instructions
+#0: xssqrtdp 3fd8000000000000 => 3fe3988e1409212e
+#1: xssqrtdp 404f000000000000 => 401f7efbeb8d4f12
+#2: xssqrtdp 0018000000b77501 => 2003988e14540690
+#3: xssqrtdp 7fe800000000051b => 5febb67ae8584f9d
+#4: xssqrtdp 0123214569900000 => 2088bde98d60ebe6
+#5: xssqrtdp 0000000000000000 => 0000000000000000
+#6: xssqrtdp 8000000000000000 => 8000000000000000
+#7: xssqrtdp 7ff0000000000000 => 7ff0000000000000
+#8: xssqrtdp fff0000000000000 => 7ff8000000000000
+#9: xssqrtdp 7ff7ffffffffffff => 7fffffffffffffff
+#10: xssqrtdp fff7ffffffffffff => ffffffffffffffff
+#11: xssqrtdp 7ff8000000000000 => 7ff8000000000000
+#12: xssqrtdp fff8000000000000 => fff8000000000000
+#13: xssqrtdp 8008340000078000 => 7ff8000000000000
+#14: xssqrtdp c0d0650f5a07b353 => 7ff8000000000000
+#15: xssqrtdp 41232585a9900000 => 4088c0a9258a4a8b
+#16: xssqrtdp 41382511a2000000 => 4093a7aa60f34e85
+
+#0: xsrdpim 3fd8000000000000 => 0000000000000000
+#1: xsrdpim 404f000000000000 => 404f000000000000
+#2: xsrdpim 0018000000b77501 => 0000000000000000
+#3: xsrdpim 7fe800000000051b => 7fe800000000051b
+#4: xsrdpim 0123214569900000 => 0000000000000000
+#5: xsrdpim 0000000000000000 => 0000000000000000
+#6: xsrdpim 8000000000000000 => 8000000000000000
+#7: xsrdpim 7ff0000000000000 => 7ff0000000000000
+#8: xsrdpim fff0000000000000 => fff0000000000000
+#9: xsrdpim 7ff7ffffffffffff => 7fffffffffffffff
+#10: xsrdpim fff7ffffffffffff => ffffffffffffffff
+#11: xsrdpim 7ff8000000000000 => 7ff8000000000000
+#12: xsrdpim fff8000000000000 => fff8000000000000
+#13: xsrdpim 8008340000078000 => bff0000000000000
+#14: xsrdpim c0d0650f5a07b353 => c0d0654000000000
+#15: xsrdpim 41232585a9900000 => 4123258400000000
+#16: xsrdpim 41382511a2000000 => 4138251100000000
+
+#0: xsrdpip 3fd8000000000000 => 3ff0000000000000
+#1: xsrdpip 404f000000000000 => 404f000000000000
+#2: xsrdpip 0018000000b77501 => 3ff0000000000000
+#3: xsrdpip 7fe800000000051b => 7fe800000000051b
+#4: xsrdpip 0123214569900000 => 3ff0000000000000
+#5: xsrdpip 0000000000000000 => 0000000000000000
+#6: xsrdpip 8000000000000000 => 8000000000000000
+#7: xsrdpip 7ff0000000000000 => 7ff0000000000000
+#8: xsrdpip fff0000000000000 => fff0000000000000
+#9: xsrdpip 7ff7ffffffffffff => 7fffffffffffffff
+#10: xsrdpip fff7ffffffffffff => ffffffffffffffff
+#11: xsrdpip 7ff8000000000000 => 7ff8000000000000
+#12: xsrdpip fff8000000000000 => fff8000000000000
+#13: xsrdpip 8008340000078000 => 8000000000000000
+#14: xsrdpip c0d0650f5a07b353 => c0d0650000000000
+#15: xsrdpip 41232585a9900000 => 4123258600000000
+#16: xsrdpip 41382511a2000000 => 4138251200000000
+
+#0: xstdivdp fff0000000000000,fff0000000000000 => cr e
+#1: xstdivdp fff0000000000000,c0d0650f5a07b353 => cr e
+#2: xstdivdp 41232585a9900000,41382511a2000000 => cr 8
+#3: xstdivdp fff0000000000000,0000000000000000 => cr e
+#4: xstdivdp fff0000000000000,0123214569900000 => cr e
+#5: xstdivdp fff0000000000000,7ff0000000000000 => cr e
+#6: xstdivdp fff0000000000000,7ff7ffffffffffff => cr e
+#7: xstdivdp fff0000000000000,7ff8000000000000 => cr e
+#8: xstdivdp c0d0650f5a07b353,fff0000000000000 => cr e
+#9: xstdivdp c0d0650f5a07b353,c0d0650f5a07b353 => cr 8
+#10: xstdivdp c0d0650f5a07b353,8000000000000000 => cr e
+#11: xstdivdp c0d0650f5a07b353,0000000000000000 => cr e
+#12: xstdivdp c0d0650f5a07b353,0123214569900000 => cr 8
+#13: xstdivdp c0d0650f5a07b353,7ff0000000000000 => cr e
+#14: xstdivdp c0d0650f5a07b353,7ff7ffffffffffff => cr a
+#15: xstdivdp c0d0650f5a07b353,7ff8000000000000 => cr a
+#16: xstdivdp 8000000000000000,fff0000000000000 => cr e
+#17: xstdivdp 8000000000000000,c0d0650f5a07b353 => cr 8
+#18: xstdivdp 8000000000000000,8000000000000000 => cr e
+#19: xstdivdp 8000000000000000,0000000000000000 => cr e
+#20: xstdivdp 8000000000000000,0123214569900000 => cr 8
+#21: xstdivdp 8000000000000000,7ff0000000000000 => cr e
+#22: xstdivdp 8000000000000000,7ff7ffffffffffff => cr a
+#23: xstdivdp 8000000000000000,7ff8000000000000 => cr a
+#24: xstdivdp 0000000000000000,fff0000000000000 => cr e
+#25: xstdivdp 0000000000000000,c0d0650f5a07b353 => cr 8
+#26: xstdivdp 0000000000000000,8000000000000000 => cr e
+#27: xstdivdp 0000000000000000,0000000000000000 => cr e
+#28: xstdivdp 0000000000000000,0123214569900000 => cr 8
+#29: xstdivdp 0000000000000000,7ff0000000000000 => cr e
+#30: xstdivdp 0000000000000000,7ff7ffffffffffff => cr a
+#31: xstdivdp 0000000000000000,7ff8000000000000 => cr a
+#32: xstdivdp 0123214569900000,fff0000000000000 => cr e
+#33: xstdivdp 0123214569900000,c0d0650f5a07b353 => cr a
+#34: xstdivdp 0123214569900000,8000000000000000 => cr e
+#35: xstdivdp 0123214569900000,0000000000000000 => cr e
+#36: xstdivdp 0123214569900000,404f000000000000 => cr a
+#37: xstdivdp 0123214569900000,7ff0000000000000 => cr e
+#38: xstdivdp 0123214569900000,7ff7ffffffffffff => cr a
+#39: xstdivdp 0123214569900000,7ff8000000000000 => cr a
+#40: xstdivdp 7ff0000000000000,fff0000000000000 => cr e
+#41: xstdivdp 7ff0000000000000,c0d0650f5a07b353 => cr e
+#42: xstdivdp 7ff0000000000000,8000000000000000 => cr e
+#43: xstdivdp 7ff0000000000000,0000000000000000 => cr e
+#44: xstdivdp 7ff0000000000000,0123214569900000 => cr e
+#45: xstdivdp 7ff0000000000000,7ff0000000000000 => cr e
+#46: xstdivdp 7ff0000000000000,7ff7ffffffffffff => cr e
+#47: xstdivdp 7ff0000000000000,7ff8000000000000 => cr e
+#48: xstdivdp fff7ffffffffffff,fff0000000000000 => cr e
+#49: xstdivdp fff7ffffffffffff,c0d0650f5a07b353 => cr a
+#50: xstdivdp fff8000000000000,8000000000000000 => cr e
+#51: xstdivdp fff8000000000000,0000000000000000 => cr e
+#52: xstdivdp fff7ffffffffffff,0123214569900000 => cr a
+#53: xstdivdp fff7ffffffffffff,7ff0000000000000 => cr e
+#54: xstdivdp fff7ffffffffffff,7ff7ffffffffffff => cr a
+#55: xstdivdp fff7ffffffffffff,7ff8000000000000 => cr a
+#56: xstdivdp fff8000000000000,fff0000000000000 => cr e
+#57: xstdivdp fff8000000000000,c0d0650f5a07b353 => cr a
+#58: xstdivdp fff8000000000000,8000000000000000 => cr e
+#59: xstdivdp 41232585a9900000,41382511a2000000 => cr 8
+#60: xstdivdp 41232585a9900000,41382511a2000000 => cr 8
+#61: xstdivdp 7ff7ffffffffffff,7ff8000000000000 => cr a
+#62: xstdivdp 7ff8000000000000,7ff8000000000000 => cr a
+#63: xstdivdp 7ff8000000000000,fff8000000000000 => cr a
+
+#0: xsmaxdp fff0000000000000,fff0000000000000 => fff0000000000000
+#1: xsmaxdp fff0000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#2: xsmaxdp 41232585a9900000,41382511a2000000 => 41382511a2000000
+#3: xsmaxdp fff0000000000000,0000000000000000 => 0000000000000000
+#4: xsmaxdp fff0000000000000,0123214569900000 => 0123214569900000
+#5: xsmaxdp fff0000000000000,7ff0000000000000 => 7ff0000000000000
+#6: xsmaxdp fff0000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#7: xsmaxdp fff0000000000000,7ff8000000000000 => fff0000000000000
+#8: xsmaxdp c0d0650f5a07b353,fff0000000000000 => c0d0650f5a07b353
+#9: xsmaxdp c0d0650f5a07b353,c0d0650f5a07b353 => c0d0650f5a07b353
+#10: xsmaxdp c0d0650f5a07b353,8000000000000000 => 8000000000000000
+#11: xsmaxdp c0d0650f5a07b353,0000000000000000 => 0000000000000000
+#12: xsmaxdp c0d0650f5a07b353,0123214569900000 => 0123214569900000
+#13: xsmaxdp c0d0650f5a07b353,7ff0000000000000 => 7ff0000000000000
+#14: xsmaxdp c0d0650f5a07b353,7ff7ffffffffffff => 7fffffffffffffff
+#15: xsmaxdp c0d0650f5a07b353,7ff8000000000000 => c0d0650f5a07b353
+#16: xsmaxdp 8000000000000000,fff0000000000000 => 8000000000000000
+#17: xsmaxdp 8000000000000000,c0d0650f5a07b353 => 8000000000000000
+#18: xsmaxdp 8000000000000000,8000000000000000 => 8000000000000000
+#19: xsmaxdp 8000000000000000,0000000000000000 => 0000000000000000
+#20: xsmaxdp 8000000000000000,0123214569900000 => 0123214569900000
+#21: xsmaxdp 8000000000000000,7ff0000000000000 => 7ff0000000000000
+#22: xsmaxdp 8000000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#23: xsmaxdp 8000000000000000,7ff8000000000000 => 8000000000000000
+#24: xsmaxdp 0000000000000000,fff0000000000000 => 0000000000000000
+#25: xsmaxdp 0000000000000000,c0d0650f5a07b353 => 0000000000000000
+#26: xsmaxdp 0000000000000000,8000000000000000 => 0000000000000000
+#27: xsmaxdp 0000000000000000,0000000000000000 => 0000000000000000
+#28: xsmaxdp 0000000000000000,0123214569900000 => 0123214569900000
+#29: xsmaxdp 0000000000000000,7ff0000000000000 => 7ff0000000000000
+#30: xsmaxdp 0000000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#31: xsmaxdp 0000000000000000,7ff8000000000000 => 0000000000000000
+#32: xsmaxdp 0123214569900000,fff0000000000000 => 0123214569900000
+#33: xsmaxdp 0123214569900000,c0d0650f5a07b353 => 0123214569900000
+#34: xsmaxdp 0123214569900000,8000000000000000 => 0123214569900000
+#35: xsmaxdp 0123214569900000,0000000000000000 => 0123214569900000
+#36: xsmaxdp 0123214569900000,404f000000000000 => 404f000000000000
+#37: xsmaxdp 0123214569900000,7ff0000000000000 => 7ff0000000000000
+#38: xsmaxdp 0123214569900000,7ff7ffffffffffff => 7fffffffffffffff
+#39: xsmaxdp 0123214569900000,7ff8000000000000 => 0123214569900000
+#40: xsmaxdp 7ff0000000000000,fff0000000000000 => 7ff0000000000000
+#41: xsmaxdp 7ff0000000000000,c0d0650f5a07b353 => 7ff0000000000000
+#42: xsmaxdp 7ff0000000000000,8000000000000000 => 7ff0000000000000
+#43: xsmaxdp 7ff0000000000000,0000000000000000 => 7ff0000000000000
+#44: xsmaxdp 7ff0000000000000,0123214569900000 => 7ff0000000000000
+#45: xsmaxdp 7ff0000000000000,7ff0000000000000 => 7ff0000000000000
+#46: xsmaxdp 7ff0000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#47: xsmaxdp 7ff0000000000000,7ff8000000000000 => 7ff0000000000000
+#48: xsmaxdp fff7ffffffffffff,fff0000000000000 => ffffffffffffffff
+#49: xsmaxdp fff7ffffffffffff,c0d0650f5a07b353 => ffffffffffffffff
+#50: xsmaxdp fff8000000000000,8000000000000000 => 8000000000000000
+#51: xsmaxdp fff8000000000000,0000000000000000 => 0000000000000000
+#52: xsmaxdp fff7ffffffffffff,0123214569900000 => ffffffffffffffff
+#53: xsmaxdp fff7ffffffffffff,7ff0000000000000 => ffffffffffffffff
+#54: xsmaxdp fff7ffffffffffff,7ff7ffffffffffff => ffffffffffffffff
+#55: xsmaxdp fff7ffffffffffff,7ff8000000000000 => ffffffffffffffff
+#56: xsmaxdp fff8000000000000,fff0000000000000 => fff0000000000000
+#57: xsmaxdp fff8000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#58: xsmaxdp fff8000000000000,8000000000000000 => 8000000000000000
+#59: xsmaxdp 41232585a9900000,41382511a2000000 => 41382511a2000000
+#60: xsmaxdp 41232585a9900000,41382511a2000000 => 41382511a2000000
+#61: xsmaxdp 7ff7ffffffffffff,7ff8000000000000 => 7fffffffffffffff
+#62: xsmaxdp 7ff8000000000000,7ff8000000000000 => 7ff8000000000000
+#63: xsmaxdp 7ff8000000000000,fff8000000000000 => 7ff8000000000000
+
+#0: xsmindp fff0000000000000,fff0000000000000 => fff0000000000000
+#1: xsmindp fff0000000000000,c0d0650f5a07b353 => fff0000000000000
+#2: xsmindp 41232585a9900000,41382511a2000000 => 41232585a9900000
+#3: xsmindp fff0000000000000,0000000000000000 => fff0000000000000
+#4: xsmindp fff0000000000000,0123214569900000 => fff0000000000000
+#5: xsmindp fff0000000000000,7ff0000000000000 => fff0000000000000
+#6: xsmindp fff0000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#7: xsmindp fff0000000000000,7ff8000000000000 => fff0000000000000
+#8: xsmindp c0d0650f5a07b353,fff0000000000000 => fff0000000000000
+#9: xsmindp c0d0650f5a07b353,c0d0650f5a07b353 => c0d0650f5a07b353
+#10: xsmindp c0d0650f5a07b353,8000000000000000 => c0d0650f5a07b353
+#11: xsmindp c0d0650f5a07b353,0000000000000000 => c0d0650f5a07b353
+#12: xsmindp c0d0650f5a07b353,0123214569900000 => c0d0650f5a07b353
+#13: xsmindp c0d0650f5a07b353,7ff0000000000000 => c0d0650f5a07b353
+#14: xsmindp c0d0650f5a07b353,7ff7ffffffffffff => 7fffffffffffffff
+#15: xsmindp c0d0650f5a07b353,7ff8000000000000 => c0d0650f5a07b353
+#16: xsmindp 8000000000000000,fff0000000000000 => fff0000000000000
+#17: xsmindp 8000000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#18: xsmindp 8000000000000000,8000000000000000 => 8000000000000000
+#19: xsmindp 8000000000000000,0000000000000000 => 8000000000000000
+#20: xsmindp 8000000000000000,0123214569900000 => 8000000000000000
+#21: xsmindp 8000000000000000,7ff0000000000000 => 8000000000000000
+#22: xsmindp 8000000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#23: xsmindp 8000000000000000,7ff8000000000000 => 8000000000000000
+#24: xsmindp 0000000000000000,fff0000000000000 => fff0000000000000
+#25: xsmindp 0000000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#26: xsmindp 0000000000000000,8000000000000000 => 8000000000000000
+#27: xsmindp 0000000000000000,0000000000000000 => 0000000000000000
+#28: xsmindp 0000000000000000,0123214569900000 => 0000000000000000
+#29: xsmindp 0000000000000000,7ff0000000000000 => 0000000000000000
+#30: xsmindp 0000000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#31: xsmindp 0000000000000000,7ff8000000000000 => 0000000000000000
+#32: xsmindp 0123214569900000,fff0000000000000 => fff0000000000000
+#33: xsmindp 0123214569900000,c0d0650f5a07b353 => c0d0650f5a07b353
+#34: xsmindp 0123214569900000,8000000000000000 => 8000000000000000
+#35: xsmindp 0123214569900000,0000000000000000 => 0000000000000000
+#36: xsmindp 0123214569900000,404f000000000000 => 0123214569900000
+#37: xsmindp 0123214569900000,7ff0000000000000 => 0123214569900000
+#38: xsmindp 0123214569900000,7ff7ffffffffffff => 7fffffffffffffff
+#39: xsmindp 0123214569900000,7ff8000000000000 => 0123214569900000
+#40: xsmindp 7ff0000000000000,fff0000000000000 => fff0000000000000
+#41: xsmindp 7ff0000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#42: xsmindp 7ff0000000000000,8000000000000000 => 8000000000000000
+#43: xsmindp 7ff0000000000000,0000000000000000 => 0000000000000000
+#44: xsmindp 7ff0000000000000,0123214569900000 => 0123214569900000
+#45: xsmindp 7ff0000000000000,7ff0000000000000 => 7ff0000000000000
+#46: xsmindp 7ff0000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#47: xsmindp 7ff0000000000000,7ff8000000000000 => 7ff0000000000000
+#48: xsmindp fff7ffffffffffff,fff0000000000000 => ffffffffffffffff
+#49: xsmindp fff7ffffffffffff,c0d0650f5a07b353 => ffffffffffffffff
+#50: xsmindp fff8000000000000,8000000000000000 => 8000000000000000
+#51: xsmindp fff8000000000000,0000000000000000 => 0000000000000000
+#52: xsmindp fff7ffffffffffff,0123214569900000 => ffffffffffffffff
+#53: xsmindp fff7ffffffffffff,7ff0000000000000 => ffffffffffffffff
+#54: xsmindp fff7ffffffffffff,7ff7ffffffffffff => ffffffffffffffff
+#55: xsmindp fff7ffffffffffff,7ff8000000000000 => ffffffffffffffff
+#56: xsmindp fff8000000000000,fff0000000000000 => fff0000000000000
+#57: xsmindp fff8000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#58: xsmindp fff8000000000000,8000000000000000 => 8000000000000000
+#59: xsmindp 41232585a9900000,41382511a2000000 => 41232585a9900000
+#60: xsmindp 41232585a9900000,41382511a2000000 => 41232585a9900000
+#61: xsmindp 7ff7ffffffffffff,7ff8000000000000 => 7fffffffffffffff
+#62: xsmindp 7ff8000000000000,7ff8000000000000 => 7ff8000000000000
+#63: xsmindp 7ff8000000000000,fff8000000000000 => 7ff8000000000000
+
+#0: xscvdpsxws 3fd8000000000000 => 0000000000000000
+#1: xscvdpsxws 404f000000000000 => 000000000000003e
+#2: xscvdpsxws 0018000000b77501 => 0000000000000000
+#3: xscvdpsxws 7fe800000000051b => 000000007fffffff
+#4: xscvdpsxws 0123214569900000 => 0000000000000000
+#5: xscvdpsxws 0000000000000000 => 0000000000000000
+#6: xscvdpsxws 8000000000000000 => 0000000000000000
+#7: xscvdpsxws 7ff0000000000000 => 000000007fffffff
+#8: xscvdpsxws fff0000000000000 => 0000000080000000
+#9: xscvdpsxws 7ff7ffffffffffff => 0000000080000000
+#10: xscvdpsxws fff7ffffffffffff => 0000000080000000
+#11: xscvdpsxws 7ff8000000000000 => 0000000080000000
+#12: xscvdpsxws fff8000000000000 => 0000000080000000
+#13: xscvdpsxws 8008340000078000 => 0000000000000000
+#14: xscvdpsxws c0d0650f5a07b353 => 00000000ffffbe6c
+#15: xscvdpsxws 41232585a9900000 => 00000000000992c2
+#16: xscvdpsxws 41382511a2000000 => 0000000000182511
+
+#0: xscvdpuxds 3fd8000000000000 => 0000000000000000
+#1: xscvdpuxds 404f000000000000 => 000000000000003e
+#2: xscvdpuxds 0018000000b77501 => 0000000000000000
+#3: xscvdpuxds 7fe800000000051b => ffffffffffffffff
+#4: xscvdpuxds 0123214569900000 => 0000000000000000
+#5: xscvdpuxds 0000000000000000 => 0000000000000000
+#6: xscvdpuxds 8000000000000000 => 0000000000000000
+#7: xscvdpuxds 7ff0000000000000 => ffffffffffffffff
+#8: xscvdpuxds fff0000000000000 => 0000000000000000
+#9: xscvdpuxds 7ff7ffffffffffff => 0000000000000000
+#10: xscvdpuxds fff7ffffffffffff => 0000000000000000
+#11: xscvdpuxds 7ff8000000000000 => 0000000000000000
+#12: xscvdpuxds fff8000000000000 => 0000000000000000
+#13: xscvdpuxds 8008340000078000 => 0000000000000000
+#14: xscvdpuxds c0d0650f5a07b353 => 0000000000000000
+#15: xscvdpuxds 41232585a9900000 => 00000000000992c2
+#16: xscvdpuxds 41382511a2000000 => 0000000000182511
+
diff --git a/main/none/tests/ppc32/test_isa_2_06_part2.vgtest b/main/none/tests/ppc32/test_isa_2_06_part2.vgtest
new file mode 100644
index 0000000..7ae01be
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part2.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_06_cap
+prog: test_isa_2_06_part2
diff --git a/main/none/tests/ppc32/test_isa_2_06_part3.c b/main/none/tests/ppc32/test_isa_2_06_part3.c
new file mode 100644
index 0000000..a3639a6
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part3.c
@@ -0,0 +1,1582 @@
+/* Copyright (C) 2011 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#ifdef HAS_VSX
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+#include <math.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int div_flags, div_xer;
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+typedef void (*test_func_t)(void);
+typedef struct test_table test_table_t;
+
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+} fp_test_args_t;
+
+
+fp_test_args_t two_arg_fp_tests[] = {
+ {8, 8},
+ {8, 14},
+ {15, 16},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {12, 6},
+ {12, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 11},
+ {12, 8 },
+ {12, 14},
+ {12, 6},
+ {15, 16},
+ {15, 16},
+ {9, 11},
+ {11, 11},
+ {11, 12},
+ {16, 18},
+ {17, 16},
+ {19, 19},
+ {19, 18}
+};
+
+
+static int nb_special_fargs;
+static double * spec_fargs;
+static float * spec_sp_fargs;
+
+static void build_special_fargs_table(void)
+{
+/*
+ Entry Sign Exp fraction Special value
+ 0 0 3fd 0x8000000000000ULL Positive finite number
+ 1 0 404 0xf000000000000ULL ...
+ 2 0 001 0x8000000b77501ULL ...
+ 3 0 7fe 0x800000000051bULL ...
+ 4 0 012 0x3214569900000ULL ...
+ 5 0 000 0x0000000000000ULL +0.0 (+zero)
+ 6 1 000 0x0000000000000ULL -0.0 (-zero)
+ 7 0 7ff 0x0000000000000ULL +infinity
+ 8 1 7ff 0x0000000000000ULL -infinity
+ 9 0 7ff 0x7FFFFFFFFFFFFULL +SNaN
+ 10 1 7ff 0x7FFFFFFFFFFFFULL -SNaN
+ 11 0 7ff 0x8000000000000ULL +QNaN
+ 12 1 7ff 0x8000000000000ULL -QNaN
+ 13 1 000 0x8340000078000ULL Denormalized val (zero exp and non-zero fraction)
+ 14 1 40d 0x0650f5a07b353ULL Negative finite number
+ 15 0 412 0x32585a9900000ULL A few more positive finite numbers
+ 16 0 413 0x82511a2000000ULL ...
+ 17 . . . . . . . . . . . . . . . . . . . . . . .
+ 18 . . . . . . . . . . . . . . . . . . . . . . .
+ 19 . . . . . . . . . . . . . . . . . . . . . . .
+*/
+
+ uint64_t mant;
+ uint16_t _exp;
+ int s;
+ int j, i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 20 * sizeof(double) );
+ spec_sp_fargs = malloc( 20 * sizeof(float) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +SNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -SNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* A few positive finite numbers ... */
+ // #15
+ s = 0;
+ _exp = 0x412;
+ mant = 0x32585a9900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #16
+ s = 0;
+ _exp = 0x413;
+ mant = 0x82511a2000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #17
+ s = 0;
+ _exp = 0x403;
+ mant = 0x12ef5a9300000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #18
+ s = 0;
+ _exp = 0x405;
+ mant = 0x14bf5d2300000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #19
+ s = 0;
+ _exp = 0x409;
+ mant = 0x76bf982440000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ nb_special_fargs = i;
+ for (j = 0; j < i; j++) {
+ spec_sp_fargs[j] = spec_fargs[j];
+ }
+}
+
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+/* Type of input for floating point operations.*/
+typedef enum {
+ SINGLE_TEST,
+ DOUBLE_TEST
+} precision_type_t;
+
+typedef enum {
+ VX_SCALAR_CONV_TO_WORD,
+ VX_CONV_TO_SINGLE,
+ VX_CONV_TO_DOUBLE,
+ VX_ESTIMATE,
+ VX_DEFAULT
+} vx_fp_test_type;
+
+static vector unsigned int vec_out, vec_inA, vec_inB;
+
+/* This function is for checking the reciprocal and reciprocal square root
+ * estimate instructions.
+ */
+Bool check_estimate(precision_type_t type, Bool is_rsqrte, int idx, int output_vec_idx)
+{
+ /* Technically, the number of bits of precision for xvredp and xvrsqrtedp is
+ * 14 bits (14 = log2 16384). However, the VEX emulation of these instructions
+ * does an actual reciprocal calculation versus estimation, so the answer we get back from
+ * valgrind can easily differ from the estimate in the lower bits (within the 14 bits of
+ * precision) and the estimate may still be within expected tolerances. On top of that,
+ * we can't count on these estimates always being the same across implementations.
+ * For example, with the fre[s] instruction (which should be correct to within one part
+ * in 256 -- i.e., 8 bits of precision) . . . When approximating the value 1.0111_1111_1111,
+ * one implementation could return 1.0111_1111_0000 and another implementation could return
+ * 1.1000_0000_0000. Both estimates meet the 1/256 accuracy requirement, but share only a
+ * single bit in common.
+ *
+ * The upshot is we can't validate the VEX output for these instructions by comparing against
+ * stored bit patterns. We must check that the result is within expected tolerances.
+ */
+
+
+ /* A mask to be used for validation as a last resort.
+ * Only use 12 bits of precision for reasons discussed above.
+ */
+#define VSX_RECIP_ESTIMATE_MASK_DP 0xFFFFFF0000000000ULL
+#define VSX_RECIP_ESTIMATE_MASK_SP 0xFFFFFF00
+
+ Bool result = False;
+ Bool dp_test = type == DOUBLE_TEST;
+ double src_dp, res_dp;
+ float src_sp, res_sp;
+ src_dp = res_dp = 0;
+ src_sp = res_sp = 0;
+#define SRC (dp_test ? src_dp : src_sp)
+#define RES (dp_test ? res_dp : res_sp)
+ Bool src_is_negative = False;
+ Bool res_is_negative = False;
+ unsigned long long * dst_dp = NULL;
+ unsigned int * dst_sp = NULL;
+ if (dp_test) {
+ unsigned long long * src_dp_ull;
+ dst_dp = (unsigned long long *) &vec_out;
+ src_dp = spec_fargs[idx];
+ src_dp_ull = (unsigned long long *) &src_dp;
+ src_is_negative = (*src_dp_ull & 0x8000000000000000ULL) ? True : False;
+ res_is_negative = (dst_dp[output_vec_idx] & 0x8000000000000000ULL) ? True : False;
+ memcpy(&res_dp, &dst_dp[output_vec_idx], 8);
+ } else {
+ unsigned int * src_sp_uint;
+ dst_sp = (unsigned int *) &vec_out;
+ src_sp = spec_sp_fargs[idx];
+ src_sp_uint = (unsigned int *) &src_sp;
+ src_is_negative = (*src_sp_uint & 0x80000000) ? True : False;
+ res_is_negative = (dst_sp[output_vec_idx] & 0x80000000) ? True : False;
+ memcpy(&res_sp, &dst_sp[output_vec_idx], 4);
+ }
+
+ // Below are common rules for xvre{d|s}p and xvrsqrte{d|s}p
+ if (isnan(SRC))
+ return isnan(RES);
+ if (fpclassify(SRC) == FP_ZERO)
+ return isinf(RES);
+ if (!src_is_negative && isinf(SRC))
+ return !res_is_negative && (fpclassify(RES) == FP_ZERO);
+ if (is_rsqrte) {
+ if (src_is_negative)
+ return isnan(RES);
+ } else {
+ if (src_is_negative && isinf(SRC))
+ return res_is_negative && (fpclassify(RES) == FP_ZERO);
+ }
+ if (dp_test) {
+ double calc_diff;
+ double real_diff;
+ double recip_divisor;
+ double div_result;
+ double calc_diff_tmp;
+
+ if (is_rsqrte)
+ recip_divisor = sqrt(src_dp);
+ else
+ recip_divisor = src_dp;
+
+ div_result = 1.0/recip_divisor;
+ calc_diff_tmp = recip_divisor * 16384.0;
+ if (isnormal(calc_diff_tmp)) {
+ calc_diff = fabs(1.0/calc_diff_tmp);
+ real_diff = fabs(res_dp - div_result);
+ result = ( ( res_dp == div_result )
+ || ( real_diff <= calc_diff ) );
+ } else {
+ /* Unable to compute theoretical difference, so we fall back to masking out
+ * un-precise bits.
+ */
+ unsigned long long * div_result_dp = (unsigned long long *) &div_result;
+ result = (dst_dp[output_vec_idx] & VSX_RECIP_ESTIMATE_MASK_DP) == (*div_result_dp & VSX_RECIP_ESTIMATE_MASK_DP);
+ }
+ /* For debug use . . .
+ if (!result) {
+ unsigned long long * dv = &div_result;
+ unsigned long long * rd = &real_diff;
+ unsigned long long * cd = &calc_diff;
+ printf("\n\t {actual div_result: %016llx; real_diff: %016llx; calc_diff: %016llx}\n",
+ *dv, *rd, *cd);
+ }
+ */
+ } else { // single precision test (only have xvrsqrtesp, since xvresp was implemented in stage 2)
+ float calc_diff;
+ float real_diff;
+ float div_result;
+ float calc_diff_tmp;
+ float recip_divisor = sqrt(src_sp);
+
+ div_result = 1.0/recip_divisor;
+ calc_diff_tmp = recip_divisor * 16384.0;
+ if (isnormal(calc_diff_tmp)) {
+ calc_diff = fabsf(1.0/calc_diff_tmp);
+ real_diff = fabsf(res_sp - div_result);
+ result = ( ( res_sp == div_result )
+ || ( real_diff <= calc_diff ) );
+ } else {
+ /* Unable to compute theoretical difference, so we fall back to masking out
+ * un-precise bits.
+ */
+ unsigned int * div_result_sp = (unsigned int *) &div_result;
+ result = (dst_sp[output_vec_idx] & VSX_RECIP_ESTIMATE_MASK_SP) == (*div_result_sp & VSX_RECIP_ESTIMATE_MASK_SP);
+ }
+ /* For debug use . . .
+ if (!result) {
+ unsigned long long * dv = &div_result;
+ unsigned long long * rd = &real_diff;
+ unsigned long long * cd = &calc_diff;
+ printf("\n\t {actual div_result: %016llx; real_diff: %016llx; calc_diff: %016llx}\n",
+ *dv, *rd, *cd);
+ }
+ */
+ }
+ return result;
+}
+
+typedef struct vx_fp_test
+{
+ test_func_t test_func;
+ const char * name;
+ fp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type type;
+ const char * op;
+} vx_fp_test_t;
+
+
+static Bool do_dot;
+
+static void test_xvredp(void)
+{
+ __asm__ __volatile__ ("xvredp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsredp(void)
+{
+ __asm__ __volatile__ ("xsredp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrsqrtedp(void)
+{
+ __asm__ __volatile__ ("xvrsqrtedp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrsqrtedp(void)
+{
+ __asm__ __volatile__ ("xsrsqrtedp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrsqrtesp(void)
+{
+ __asm__ __volatile__ ("xvrsqrtesp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xstsqrtdp(void)
+{
+ __asm__ __volatile__ ("xstsqrtdp cr1, %x0" : : "wa" (vec_inB));
+}
+
+static void test_xvtsqrtdp(void)
+{
+ __asm__ __volatile__ ("xvtsqrtdp cr1, %x0" : : "wa" (vec_inB));
+}
+
+static void test_xvtsqrtsp(void)
+{
+ __asm__ __volatile__ ("xvtsqrtsp cr1, %x0" : : "wa" (vec_inB));
+}
+
+static void test_xvsqrtdp(void)
+{
+ __asm__ __volatile__ ("xvsqrtdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvsqrtsp(void)
+{
+ __asm__ __volatile__ ("xvsqrtsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvtdivdp(void)
+{
+ __asm__ __volatile__ ("xvtdivdp cr1, %x0, %x1" : : "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xvtdivsp(void)
+{
+ __asm__ __volatile__ ("xvtdivsp cr1, %x0, %x1" : : "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xscvdpsp(void)
+{
+ __asm__ __volatile__ ("xscvdpsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvdpuxws(void)
+{
+ __asm__ __volatile__ ("xscvdpuxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvspdp(void)
+{
+ __asm__ __volatile__ ("xscvspdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpsp(void)
+{
+ __asm__ __volatile__ ("xvcvdpsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpuxds(void)
+{
+ __asm__ __volatile__ ("xvcvdpuxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpuxws(void)
+{
+ __asm__ __volatile__ ("xvcvdpuxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspdp(void)
+{
+ __asm__ __volatile__ ("xvcvspdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspsxds(void)
+{
+ __asm__ __volatile__ ("xvcvspsxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspuxds(void)
+{
+ __asm__ __volatile__ ("xvcvspuxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpsxds(void)
+{
+ __asm__ __volatile__ ("xvcvdpsxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspuxws(void)
+{
+ __asm__ __volatile__ ("xvcvspuxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxddp(void)
+{
+ __asm__ __volatile__ ("xvcvsxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxddp(void)
+{
+ __asm__ __volatile__ ("xvcvuxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxdsp(void)
+{
+ __asm__ __volatile__ ("xvcvsxdsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxdsp(void)
+{
+ __asm__ __volatile__ ("xvcvuxdsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxwdp(void)
+{
+ __asm__ __volatile__ ("xvcvsxwdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxwdp(void)
+{
+ __asm__ __volatile__ ("xvcvuxwdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxwsp(void)
+{
+ __asm__ __volatile__ ("xvcvsxwsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxwsp(void)
+{
+ __asm__ __volatile__ ("xvcvuxwsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpic(void)
+{
+ __asm__ __volatile__ ("xsrdpic %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpiz(void)
+{
+ __asm__ __volatile__ ("xsrdpiz %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpi(void)
+{
+ __asm__ __volatile__ ("xsrdpi %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvabsdp(void)
+{
+ __asm__ __volatile__ ("xvabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvnabsdp(void)
+{
+ __asm__ __volatile__ ("xvnabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvnegdp(void)
+{
+ __asm__ __volatile__ ("xvnegdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvabssp(void)
+{
+ __asm__ __volatile__ ("xvabssp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvnabssp(void)
+{
+ __asm__ __volatile__ ("xvnabssp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpi(void)
+{
+ __asm__ __volatile__ ("xvrdpi %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpic(void)
+{
+ __asm__ __volatile__ ("xvrdpic %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpim(void)
+{
+ __asm__ __volatile__ ("xvrdpim %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpip(void)
+{
+ __asm__ __volatile__ ("xvrdpip %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpiz(void)
+{
+ __asm__ __volatile__ ("xvrdpiz %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspi(void)
+{
+ __asm__ __volatile__ ("xvrspi %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspic(void)
+{
+ __asm__ __volatile__ ("xvrspic %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspim(void)
+{
+ __asm__ __volatile__ ("xvrspim %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspip(void)
+{
+ __asm__ __volatile__ ("xvrspip %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspiz(void)
+{
+ __asm__ __volatile__ ("xvrspiz %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static vx_fp_test_t
+vsx_one_fp_arg_tests[] = {
+ { &test_xvredp, "xvredp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
+ { &test_xsredp, "xsredp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
+ { &test_xvrsqrtedp, "xvrsqrtedp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x-sqrt"},
+ { &test_xsrsqrtedp, "xsrsqrtedp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x-sqrt"},
+ { &test_xvrsqrtesp, "xvrsqrtesp", NULL, 18, SINGLE_TEST, VX_ESTIMATE, "1/x-sqrt"},
+ { &test_xvsqrtdp, "xvsqrtdp", NULL, 18, DOUBLE_TEST, VX_DEFAULT, "sqrt"},
+ { &test_xvsqrtsp, "xvsqrtsp", NULL, 18, SINGLE_TEST, VX_DEFAULT, "sqrt"},
+ { &test_xscvdpsp, "xscvdpsp", NULL, 20, DOUBLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xscvdpuxws, "xscvdpuxws", NULL, 20, DOUBLE_TEST, VX_SCALAR_CONV_TO_WORD, "conv"},
+ { &test_xscvspdp, "xscvspdp", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvdpsp, "xvcvdpsp", NULL, 20, DOUBLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xvcvdpuxds, "xvcvdpuxds", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvdpuxws, "xvcvdpuxws", NULL, 20, DOUBLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xvcvspdp, "xvcvspdp", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvspsxds, "xvcvspsxds", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvdpsxds, "xvcvdpsxds", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvspuxds, "xvcvspuxds", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvspuxws, "xvcvspuxws", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xsrdpic, "xsrdpic", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xsrdpiz, "xsrdpiz", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xsrdpi, "xsrdpi", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvabsdp, "xvabsdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "abs"},
+ { &test_xvnabsdp, "xvnabsdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "nabs"},
+ { &test_xvnegdp, "xvnegdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "neg"},
+ { &test_xvabssp, "xvabssp", NULL, 20, SINGLE_TEST, VX_DEFAULT, "abs"},
+ { &test_xvnabssp, "xvnabssp", NULL, 20, SINGLE_TEST, VX_DEFAULT, "nabs"},
+ { &test_xvrdpi, "xvrdpi", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpic, "xvrdpic", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpim, "xvrdpim", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpip, "xvrdpip", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpiz, "xvrdpiz", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrspi, "xvrspi", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspic, "xvrspic", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspim, "xvrspim", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspip, "xvrspip", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspiz, "xvrspiz", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { NULL, NULL, NULL, 0, 0, 0, NULL}
+};
+
+static vx_fp_test_t
+vx_tdivORtsqrt_tests[] = {
+ { &test_xstsqrtdp, "xstsqrtdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "test-sqrt"},
+ { &test_xvtsqrtdp, "xvtsqrtdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "test-sqrt"},
+ { &test_xvtsqrtsp, "xvtsqrtsp", NULL, 20, SINGLE_TEST, VX_DEFAULT, "test-sqrt"},
+ { &test_xvtdivdp, "xvtdivdp", two_arg_fp_tests, 68, DOUBLE_TEST, VX_DEFAULT, "test-div"},
+ { &test_xvtdivsp, "xvtdivsp", two_arg_fp_tests, 68, SINGLE_TEST, VX_DEFAULT, "test-div"},
+ { NULL, NULL, NULL, 0 , 0, 0, NULL}
+};
+
+static unsigned long long doubleWord[] = { 0,
+ 0xffffffff00000000LL,
+ 0x00000000ffffffffLL,
+ 0xffffffffffffffffLL,
+ 0x89abcde123456789LL,
+ 0x0102030405060708LL,
+ 0x00000000a0b1c2d3LL,
+ 0x1111222233334444LL
+};
+
+static unsigned int singleWord[] = {0,
+ 0xffff0000,
+ 0x0000ffff,
+ 0xffffffff,
+ 0x89a73522,
+ 0x01020304,
+ 0x0000abcd,
+ 0x11223344
+};
+
+typedef struct vx_intToFp_test
+{
+ test_func_t test_func;
+ const char * name;
+ void * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type type;
+} vx_intToFp_test_t;
+
+static vx_intToFp_test_t
+intToFp_tests[] = {
+ { test_xvcvsxddp, "xvcvsxddp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvuxddp, "xvcvuxddp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvsxdsp, "xvcvsxdsp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_SINGLE },
+ { test_xvcvuxdsp, "xvcvuxdsp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_SINGLE },
+ { test_xvcvsxwdp, "xvcvsxwdp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvuxwdp, "xvcvuxwdp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvsxwsp, "xvcvsxwsp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_SINGLE },
+ { test_xvcvuxwsp, "xvcvuxwsp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_SINGLE },
+ { NULL, NULL, NULL, 0, 0 }
+};
+
+static Bool do_OE;
+typedef enum {
+ DIV_BASE = 1,
+ DIV_OE = 2,
+ DIV_DOT = 4,
+} div_type_t;
+/* Possible divde type combinations are:
+ * - base
+ * - base+dot
+ * - base+OE
+ * - base+OE+dot
+ */
+#ifdef __powerpc64__
+static void test_divdeu(void)
+{
+ int divdeu_type = DIV_BASE;
+ if (do_OE)
+ divdeu_type |= DIV_OE;
+ if (do_dot)
+ divdeu_type |= DIV_DOT;
+
+ switch (divdeu_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeu %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeuo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeu. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeuo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divdeu type. Exiting\n");
+ exit(1);
+ }
+}
+#endif
+
+static void test_divwe(void)
+{
+ int divwe_type = DIV_BASE;
+ if (do_OE)
+ divwe_type |= DIV_OE;
+ if (do_dot)
+ divwe_type |= DIV_DOT;
+
+ switch (divwe_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divwe %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divwe. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divweu type. Exiting\n");
+ exit(1);
+ }
+}
+
+
+typedef struct simple_test {
+ test_func_t test_func;
+ char * name;
+ precision_type_t precision;
+} simple_test_t;
+
+
+static void setup_sp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? &vec_out : &vec_inB;
+
+ for (i = 0; i < 4; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_sp_fargs[a_idx];
+ inB = (void *)&spec_sp_fargs[b_idx];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 4), inA, 4);
+ memcpy(vec_src + (i * 4), inB, 4);
+ targs++;
+ }
+}
+
+static void setup_dp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? (void *)&vec_out : (void *)&vec_inB;
+
+ for (i = 0; i < 2; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_fargs[a_idx];
+ inB = (void *)&spec_fargs[b_idx];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 8), inA, 8);
+ memcpy(vec_src + (i * 8), inB, 8);
+ targs++;
+ }
+}
+
+#define VX_NOT_CMP_OP 0xffffffff
+static void print_vector_fp_result(unsigned int cc, vx_fp_test_t * test_group, int i, Bool print_vec_out)
+{
+ int a_idx, b_idx, k;
+ char * name = malloc(20);
+ int dp = test_group->precision == DOUBLE_TEST ? 1 : 0;
+ int loops = dp ? 2 : 4;
+ fp_test_args_t * targs = &test_group->targs[i];
+ unsigned long long * frA_dp, * frB_dp, * dst_dp;
+ unsigned int * frA_sp, *frB_sp, * dst_sp;
+ strcpy(name, test_group->name);
+ printf("#%d: %s%s ", dp? i/2 : i/4, name, (do_dot ? "." : ""));
+ for (k = 0; k < loops; k++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ if (k)
+ printf(" AND ");
+ if (dp) {
+ frA_dp = (unsigned long long *)&spec_fargs[a_idx];
+ frB_dp = (unsigned long long *)&spec_fargs[b_idx];
+ printf("%016llx %s %016llx", *frA_dp, test_group->op, *frB_dp);
+ } else {
+ frA_sp = (unsigned int *)&spec_sp_fargs[a_idx];
+ frB_sp = (unsigned int *)&spec_sp_fargs[b_idx];
+ printf("%08x %s %08x", *frA_sp, test_group->op, *frB_sp);
+ }
+ targs++;
+ }
+ if (cc != VX_NOT_CMP_OP)
+ printf(" ? cc=%x", cc);
+
+ if (print_vec_out) {
+ if (dp) {
+ dst_dp = (unsigned long long *) &vec_out;
+ printf(" => %016llx %016llx\n", dst_dp[0], dst_dp[1]);
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ printf(" => %08x %08x %08x %08x\n", dst_sp[0], dst_sp[1], dst_sp[2], dst_sp[3]);
+ }
+ } else {
+ printf("\n");
+ }
+ free(name);
+}
+
+
+
+static void test_vsx_one_fp_arg(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vsx_one_fp_arg_tests[k].test_func)) {
+ int idx, i;
+ vx_fp_test_t test_group = vsx_one_fp_arg_tests[k];
+ Bool estimate = (test_group.type == VX_ESTIMATE);
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool is_sqrt = (strstr(test_group.name, "sqrt")) ? True : False;
+ Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False;
+ Bool sparse_sp = False;
+ int stride = dp ? 2 : 4;
+ int loops = is_scalar ? 1 : stride;
+ stride = is_scalar ? 1: stride;
+
+ /* For conversions of single to double, the 128-bit input register is sparsely populated:
+ * |___ SP___|_Unused_|___SP___|__Unused__| // for vector op
+ * or
+ * |___ SP___|_Unused_|_Unused_|__Unused__| // for scalar op
+ *
+ * For the vector op case, we need to adjust stride from '4' to '2', since
+ * we'll only be loading two values per loop into the input register.
+ */
+ if (!dp && !is_scalar && test_group.type == VX_CONV_TO_DOUBLE) {
+ sparse_sp = True;
+ stride = 2;
+ }
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long * frB_dp, *dst_dp;
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ if (estimate) {
+ Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, j);
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
+ /* For debugging . . .
+ printf(" ==> %s (res=%016llx)", res ? "PASS" : "FAIL", dst_dp[j]);
+ */
+ } else {
+ vx_fp_test_type type = test_group.type;
+ switch (type) {
+ case VX_SCALAR_CONV_TO_WORD:
+ printf(" = %016llx", dst_dp[j] & 0x00000000ffffffffULL);
+ break;
+ case VX_CONV_TO_SINGLE:
+ printf(" = %016llx", dst_dp[j] & 0xffffffff00000000ULL);
+ break;
+ default: // For VX_CONV_TO_DOUBLE and non-convert instructions . . .
+ printf(" = %016llx", dst_dp[j]);
+ }
+ }
+ }
+ printf("\n");
+ } else {
+ int j, skip_slot;
+ unsigned int * frB_sp, * dst_sp = NULL;
+ unsigned long long * dst_dp = NULL;
+ if (sparse_sp) {
+ skip_slot = 1;
+ loops = 2;
+ } else {
+ skip_slot = 0;
+ }
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+ if (skip_slot && j > 0)
+ memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
+ else
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ // execute test insn
+ (*func)();
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ dst_dp = (unsigned long long *) &vec_out;
+ else
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ if (estimate) {
+ Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, j);
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
+ } else {
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ printf(" = %016llx", dst_dp[j]);
+ else
+ /* Special case: Current VEX implementation for fsqrts (single precision)
+ * uses the same implementation as that used for double precision fsqrt.
+ * However, I've found that for xvsqrtsp, the result from that implementation
+ * may be off by the two LSBs. Generally, even this small inaccuracy can cause the
+ * output to appear very different if you end up with a carry. But for the given
+ * inputs in this testcase, we can simply mask out these bits.
+ */
+ printf(" = %08x", is_sqrt ? (dst_sp[j] & 0xfffffffc) : dst_sp[j]);
+ }
+ }
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_int_to_fp_convert(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = intToFp_tests[k].test_func)) {
+ int idx, i;
+ vx_intToFp_test_t test_group = intToFp_tests[k];
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool sparse_sp = False;
+ int stride = dp ? 2 : 4;
+ int loops = stride;
+
+ /* For conversions of single to double, the 128-bit input register is sparsely populated:
+ * |___ int___|_Unused_|___int___|__Unused__| // for vector op
+ * or
+ * We need to adjust stride from '4' to '2', since we'll only be loading
+ * two values per loop into the input register.
+ */
+ if (!dp && test_group.type == VX_CONV_TO_DOUBLE) {
+ sparse_sp = True;
+ stride = 2;
+ }
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long *dst_dw, * targs = test_group.targs;
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&targs[i + j];
+ // copy doubleword into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dw = (unsigned long long *) &vec_out;
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ printf("conv(%016llx)", targs[i + j]);
+
+ if (test_group.type == VX_CONV_TO_SINGLE)
+ printf(" = %016llx", dst_dw[j] & 0xffffffff00000000ULL);
+ else
+ printf(" = %016llx", dst_dw[j]);
+ }
+ printf("\n");
+ } else {
+ int j, skip_slot;
+ unsigned int * dst_sp = NULL;
+ unsigned int * targs = test_group.targs;
+ unsigned long long * dst_dp = NULL;
+ if (sparse_sp) {
+ skip_slot = 1;
+ loops = 2;
+ } else {
+ skip_slot = 0;
+ }
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&targs[i + j];
+ // copy single word into vector element i
+ if (skip_slot && j > 0)
+ memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
+ else
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ // execute test insn
+ (*func)();
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ dst_dp = (unsigned long long *) &vec_out;
+ else
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ printf("conv(%08x)", targs[i + j]);
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ printf(" = %016llx", dst_dp[j]);
+ else
+ printf(" = %08x", dst_sp[j]);
+ }
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+
+// The div doubleword test data
+signed long long div_dw_tdata[13][2] = {
+ { 4, -4 },
+ { 4, -3 },
+ { 4, 4 },
+ { 4, -5 },
+ { 3, 8 },
+ { 0x8000000000000000ULL, 0xa },
+ { 0x50c, -1 },
+ { 0x50c, -4096 },
+ { 0x1234fedc, 0x8000a873 },
+ { 0xabcd87651234fedcULL, 0xa123b893 },
+ { 0x123456789abdcULL, 0 },
+ { 0, 2 },
+ { 0x77, 0xa3499 }
+};
+#define dw_tdata_len (sizeof(div_dw_tdata)/sizeof(signed long long)/2)
+
+// The div word test data
+unsigned int div_w_tdata[6][2] = {
+ { 0, 2 },
+ { 2, 0 },
+ { 0x7abc1234, 0xf0000000 },
+ { 0xfabc1234, 5 },
+ { 77, 66 },
+ { 5, 0xfabc1234 },
+};
+#define w_tdata_len (sizeof(div_w_tdata)/sizeof(unsigned int)/2)
+
+typedef struct div_ext_test
+{
+ test_func_t test_func;
+ const char *name;
+ int num_tests;
+ div_type_t div_type;
+ precision_type_t precision;
+} div_ext_test_t;
+
+static div_ext_test_t div_tests[] = {
+#ifdef __powerpc64__
+ { &test_divdeu, "divdeu", dw_tdata_len, DIV_BASE, DOUBLE_TEST },
+ { &test_divdeu, "divdeuo", dw_tdata_len, DIV_OE, DOUBLE_TEST },
+#endif
+ { &test_divwe, "divwe", w_tdata_len, DIV_BASE, SINGLE_TEST },
+ { &test_divwe, "divweo", w_tdata_len, DIV_OE, SINGLE_TEST },
+ { NULL, NULL, 0, 0, 0 }
+};
+
+static void test_div_extensions(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = div_tests[k].test_func)) {
+ int i, repeat = 1;
+ div_ext_test_t test_group = div_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int condreg;
+
+ if (test_group.div_type == DIV_OE)
+ do_OE = True;
+ else
+ do_OE = False;
+
+ if (test_group.precision == DOUBLE_TEST) {
+ r14 = div_dw_tdata[i][0];
+ r15 = div_dw_tdata[i][1];
+ } else {
+ r14 = div_w_tdata[i][0];
+ r15 = div_w_tdata[i][1];
+ }
+ // execute test insn
+ (*func)();
+ condreg = (div_flags & 0xf0000000) >> 28;
+ printf("#%d: %s%s: ", i, test_group.name, do_dot ? "." : "");
+ if (test_group.precision == DOUBLE_TEST) {
+ printf("0x%016llx0000000000000000 / 0x%016llx = 0x%016llx;",
+ div_dw_tdata[i][0], div_dw_tdata[i][1], (signed long long) r17);
+ } else {
+ printf("0x%08x00000000 / 0x%08x = 0x%08x;",
+ div_w_tdata[i][0], div_w_tdata[i][1], (unsigned int) r17);
+ }
+ printf(" CR=%x; XER=%x\n", condreg, div_xer);
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static void test_vx_tdivORtsqrt(void)
+{
+ test_func_t func;
+ int k, crx;
+ unsigned int flags;
+ k = 0;
+ do_dot = False;
+ build_special_fargs_table();
+
+ while ((func = vx_tdivORtsqrt_tests[k].test_func)) {
+ int idx, i;
+ vx_fp_test_t test_group = vx_tdivORtsqrt_tests[k];
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False;
+ Bool two_args = test_group.targs ? True : False;
+ int stride = dp ? 2 : 4;
+ int loops = is_scalar ? 1 : stride;
+ stride = is_scalar ? 1: stride;
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long * frB_dp;
+ if (two_args) {
+ setup_dp_fp_args(&test_group.targs[i], False);
+ } else {
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ }
+ // execute test insn
+ // Must do set/get of CRs immediately before/after calling the asm func
+ // to avoid CRs being modified by other instructions.
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ // assumes using CR1
+ crx = (flags & 0x0f000000) >> 24;
+ if (two_args) {
+ print_vector_fp_result(crx, &test_group, i, False/*do not print vec_out*/);
+ } else {
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ }
+ printf( " ? %x (CRx)\n", crx);
+ }
+ } else {
+ int j;
+ unsigned int * frB_sp;
+ if (two_args) {
+ setup_sp_fp_args(&test_group.targs[i], False);
+ } else {
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ }
+ // execute test insn
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ crx = (flags & 0x0f000000) >> 24;
+ // print result
+ if (two_args) {
+ print_vector_fp_result(crx, &test_group, i, False/*do not print vec_out*/);
+ } else {
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ }
+ printf( " ? %x (CRx)\n", crx);
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static void test_ftsqrt(void)
+{
+ int i, crx;
+ unsigned int flags;
+ unsigned long long * frbp;
+ build_special_fargs_table();
+
+
+ for (i = 0; i < nb_special_fargs; i++) {
+ f14 = spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("ftsqrt cr1, %0" : : "d" (f14));
+ GET_CR(flags);
+ crx = (flags & 0x0f000000) >> 24;
+ printf( "ftsqrt: %016llx ? %x (CRx)\n", *frbp, crx);
+ }
+ printf( "\n" );
+}
+
+static void
+test_popcntw(void)
+{
+#ifdef __powerpc64__
+ uint64_t res;
+ unsigned long long src = 0x9182736405504536ULL;
+ r14 = src;
+ __asm__ __volatile__ ("popcntw %0, %1" : "=r" (res): "r" (r14));
+ printf("popcntw: 0x%llx => 0x%016llx\n", (unsigned long long)src, (unsigned long long)res);
+#else
+ uint32_t res;
+ unsigned int src = 0x9182730E;
+ r14 = src;
+ __asm__ __volatile__ ("popcntw %0, %1" : "=r" (res): "r" (r14));
+ printf("popcntw: 0x%x => 0x%08x\n", src, (int)res);
+#endif
+ printf( "\n" );
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+
+ { &test_vsx_one_fp_arg,
+ "Test VSX vector and scalar single argument instructions"} ,
+ { &test_int_to_fp_convert,
+ "Test VSX vector integer to float conversion instructions" },
+ { &test_div_extensions,
+ "Test div extensions" },
+ { &test_ftsqrt,
+ "Test ftsqrt instruction" },
+ { &test_vx_tdivORtsqrt,
+ "Test vector and scalar tdiv and tsqrt instructions" },
+ { &test_popcntw,
+ "Test popcntw instruction" },
+ { NULL, NULL }
+};
+#endif // HAS_VSX
+
+int main(int argc, char *argv[])
+{
+#ifdef HAS_VSX
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+ if (spec_fargs)
+ free(spec_fargs);
+ if (spec_sp_fargs)
+ free(spec_sp_fargs);
+
+#endif // HAS _VSX
+
+ return 0;
+}
diff --git a/main/none/tests/ppc32/test_isa_2_06_part3.stderr.exp b/main/none/tests/ppc32/test_isa_2_06_part3.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part3.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc32/test_isa_2_06_part3.stdout.exp b/main/none/tests/ppc32/test_isa_2_06_part3.stdout.exp
new file mode 100644
index 0000000..df25d90
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part3.stdout.exp
@@ -0,0 +1,605 @@
+Test VSX vector and scalar single argument instructions
+#0: xvredp 1/x(3fd8000000000000) ==> PASS); 1/x(404f000000000000) ==> PASS)
+#1: xvredp 1/x(0018000000b77501) ==> PASS); 1/x(7fe800000000051b) ==> PASS)
+#2: xvredp 1/x(0123214569900000) ==> PASS); 1/x(0000000000000000) ==> PASS)
+#3: xvredp 1/x(8000000000000000) ==> PASS); 1/x(7ff0000000000000) ==> PASS)
+#4: xvredp 1/x(fff0000000000000) ==> PASS); 1/x(7ff7ffffffffffff) ==> PASS)
+#5: xvredp 1/x(fff7ffffffffffff) ==> PASS); 1/x(7ff8000000000000) ==> PASS)
+#6: xvredp 1/x(fff8000000000000) ==> PASS); 1/x(8008340000078000) ==> PASS)
+#7: xvredp 1/x(c0d0650f5a07b353) ==> PASS); 1/x(41232585a9900000) ==> PASS)
+#8: xvredp 1/x(41382511a2000000) ==> PASS); 1/x(40312ef5a9300000) ==> PASS)
+
+#0: xsredp 1/x(3fd8000000000000) ==> PASS)
+#1: xsredp 1/x(404f000000000000) ==> PASS)
+#2: xsredp 1/x(0018000000b77501) ==> PASS)
+#3: xsredp 1/x(7fe800000000051b) ==> PASS)
+#4: xsredp 1/x(0123214569900000) ==> PASS)
+#5: xsredp 1/x(0000000000000000) ==> PASS)
+#6: xsredp 1/x(8000000000000000) ==> PASS)
+#7: xsredp 1/x(7ff0000000000000) ==> PASS)
+#8: xsredp 1/x(fff0000000000000) ==> PASS)
+#9: xsredp 1/x(7ff7ffffffffffff) ==> PASS)
+#10: xsredp 1/x(fff7ffffffffffff) ==> PASS)
+#11: xsredp 1/x(7ff8000000000000) ==> PASS)
+#12: xsredp 1/x(fff8000000000000) ==> PASS)
+#13: xsredp 1/x(8008340000078000) ==> PASS)
+#14: xsredp 1/x(c0d0650f5a07b353) ==> PASS)
+#15: xsredp 1/x(41232585a9900000) ==> PASS)
+#16: xsredp 1/x(41382511a2000000) ==> PASS)
+#17: xsredp 1/x(40312ef5a9300000) ==> PASS)
+
+#0: xvrsqrtedp 1/x-sqrt(3fd8000000000000) ==> PASS); 1/x-sqrt(404f000000000000) ==> PASS)
+#1: xvrsqrtedp 1/x-sqrt(0018000000b77501) ==> PASS); 1/x-sqrt(7fe800000000051b) ==> PASS)
+#2: xvrsqrtedp 1/x-sqrt(0123214569900000) ==> PASS); 1/x-sqrt(0000000000000000) ==> PASS)
+#3: xvrsqrtedp 1/x-sqrt(8000000000000000) ==> PASS); 1/x-sqrt(7ff0000000000000) ==> PASS)
+#4: xvrsqrtedp 1/x-sqrt(fff0000000000000) ==> PASS); 1/x-sqrt(7ff7ffffffffffff) ==> PASS)
+#5: xvrsqrtedp 1/x-sqrt(fff7ffffffffffff) ==> PASS); 1/x-sqrt(7ff8000000000000) ==> PASS)
+#6: xvrsqrtedp 1/x-sqrt(fff8000000000000) ==> PASS); 1/x-sqrt(8008340000078000) ==> PASS)
+#7: xvrsqrtedp 1/x-sqrt(c0d0650f5a07b353) ==> PASS); 1/x-sqrt(41232585a9900000) ==> PASS)
+#8: xvrsqrtedp 1/x-sqrt(41382511a2000000) ==> PASS); 1/x-sqrt(40312ef5a9300000) ==> PASS)
+
+#0: xsrsqrtedp 1/x-sqrt(3fd8000000000000) ==> PASS)
+#1: xsrsqrtedp 1/x-sqrt(404f000000000000) ==> PASS)
+#2: xsrsqrtedp 1/x-sqrt(0018000000b77501) ==> PASS)
+#3: xsrsqrtedp 1/x-sqrt(7fe800000000051b) ==> PASS)
+#4: xsrsqrtedp 1/x-sqrt(0123214569900000) ==> PASS)
+#5: xsrsqrtedp 1/x-sqrt(0000000000000000) ==> PASS)
+#6: xsrsqrtedp 1/x-sqrt(8000000000000000) ==> PASS)
+#7: xsrsqrtedp 1/x-sqrt(7ff0000000000000) ==> PASS)
+#8: xsrsqrtedp 1/x-sqrt(fff0000000000000) ==> PASS)
+#9: xsrsqrtedp 1/x-sqrt(7ff7ffffffffffff) ==> PASS)
+#10: xsrsqrtedp 1/x-sqrt(fff7ffffffffffff) ==> PASS)
+#11: xsrsqrtedp 1/x-sqrt(7ff8000000000000) ==> PASS)
+#12: xsrsqrtedp 1/x-sqrt(fff8000000000000) ==> PASS)
+#13: xsrsqrtedp 1/x-sqrt(8008340000078000) ==> PASS)
+#14: xsrsqrtedp 1/x-sqrt(c0d0650f5a07b353) ==> PASS)
+#15: xsrsqrtedp 1/x-sqrt(41232585a9900000) ==> PASS)
+#16: xsrsqrtedp 1/x-sqrt(41382511a2000000) ==> PASS)
+#17: xsrsqrtedp 1/x-sqrt(40312ef5a9300000) ==> PASS)
+
+#0: xvrsqrtesp 1/x-sqrt(3ec00000) ==> PASS); 1/x-sqrt(42780000) ==> PASS); 1/x-sqrt(00000000) ==> PASS); 1/x-sqrt(7f800000) ==> PASS)
+#1: xvrsqrtesp 1/x-sqrt(00000000) ==> PASS); 1/x-sqrt(00000000) ==> PASS); 1/x-sqrt(80000000) ==> PASS); 1/x-sqrt(7f800000) ==> PASS)
+#2: xvrsqrtesp 1/x-sqrt(ff800000) ==> PASS); 1/x-sqrt(7fffffff) ==> PASS); 1/x-sqrt(ffffffff) ==> PASS); 1/x-sqrt(7fc00000) ==> PASS)
+#3: xvrsqrtesp 1/x-sqrt(ffc00000) ==> PASS); 1/x-sqrt(80000000) ==> PASS); 1/x-sqrt(c683287b) ==> PASS); 1/x-sqrt(49192c2d) ==> PASS)
+#4: xvrsqrtesp 1/x-sqrt(49c1288d) ==> PASS); 1/x-sqrt(418977ad) ==> PASS); 1/x-sqrt(428a5faf) ==> PASS); 1/x-sqrt(44bb5fcc) ==> PASS)
+
+#0: xvsqrtdp sqrt(3fd8000000000000) = 3fe3988e1409212e; sqrt(404f000000000000) = 401f7efbeb8d4f12
+#1: xvsqrtdp sqrt(0018000000b77501) = 2003988e14540690; sqrt(7fe800000000051b) = 5febb67ae8584f9d
+#2: xvsqrtdp sqrt(0123214569900000) = 2088bde98d60ebe6; sqrt(0000000000000000) = 0000000000000000
+#3: xvsqrtdp sqrt(8000000000000000) = 8000000000000000; sqrt(7ff0000000000000) = 7ff0000000000000
+#4: xvsqrtdp sqrt(fff0000000000000) = 7ff8000000000000; sqrt(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvsqrtdp sqrt(fff7ffffffffffff) = ffffffffffffffff; sqrt(7ff8000000000000) = 7ff8000000000000
+#6: xvsqrtdp sqrt(fff8000000000000) = fff8000000000000; sqrt(8008340000078000) = 7ff8000000000000
+#7: xvsqrtdp sqrt(c0d0650f5a07b353) = 7ff8000000000000; sqrt(41232585a9900000) = 4088c0a9258a4a8b
+#8: xvsqrtdp sqrt(41382511a2000000) = 4093a7aa60f34e85; sqrt(40312ef5a9300000) = 401094c71dec3a9c
+
+#0: xvsqrtsp sqrt(3ec00000) = 3f1cc470; sqrt(42780000) = 40fbf7dc; sqrt(00000000) = 00000000; sqrt(7f800000) = 7f800000
+#1: xvsqrtsp sqrt(00000000) = 00000000; sqrt(00000000) = 00000000; sqrt(80000000) = 80000000; sqrt(7f800000) = 7f800000
+#2: xvsqrtsp sqrt(ff800000) = 7fc00000; sqrt(7fffffff) = 7ffffffc; sqrt(ffffffff) = fffffffc; sqrt(7fc00000) = 7fc00000
+#3: xvsqrtsp sqrt(ffc00000) = ffc00000; sqrt(80000000) = 80000000; sqrt(c683287b) = 7fc00000; sqrt(49192c2d) = 44460548
+#4: xvsqrtsp sqrt(49c1288d) = 449d3d50; sqrt(418977ad) = 4084a638; sqrt(428a5faf) = 410515f8; sqrt(44bb5fcc) = 421ade08
+
+#0: xscvdpsp conv(3fd8000000000000) = 3ec0000000000000
+#1: xscvdpsp conv(404f000000000000) = 4278000000000000
+#2: xscvdpsp conv(0018000000b77501) = 0000000000000000
+#3: xscvdpsp conv(7fe800000000051b) = 7f80000000000000
+#4: xscvdpsp conv(0123214569900000) = 0000000000000000
+#5: xscvdpsp conv(0000000000000000) = 0000000000000000
+#6: xscvdpsp conv(8000000000000000) = 8000000000000000
+#7: xscvdpsp conv(7ff0000000000000) = 7f80000000000000
+#8: xscvdpsp conv(fff0000000000000) = ff80000000000000
+#9: xscvdpsp conv(7ff7ffffffffffff) = 7fffffff00000000
+#10: xscvdpsp conv(fff7ffffffffffff) = ffffffff00000000
+#11: xscvdpsp conv(7ff8000000000000) = 7fc0000000000000
+#12: xscvdpsp conv(fff8000000000000) = ffc0000000000000
+#13: xscvdpsp conv(8008340000078000) = 8000000000000000
+#14: xscvdpsp conv(c0d0650f5a07b353) = c683287b00000000
+#15: xscvdpsp conv(41232585a9900000) = 49192c2d00000000
+#16: xscvdpsp conv(41382511a2000000) = 49c1288d00000000
+#17: xscvdpsp conv(40312ef5a9300000) = 418977ad00000000
+#18: xscvdpsp conv(40514bf5d2300000) = 428a5faf00000000
+#19: xscvdpsp conv(40976bf982440000) = 44bb5fcc00000000
+
+#0: xscvdpuxws conv(3fd8000000000000) = 0000000000000000
+#1: xscvdpuxws conv(404f000000000000) = 000000000000003e
+#2: xscvdpuxws conv(0018000000b77501) = 0000000000000000
+#3: xscvdpuxws conv(7fe800000000051b) = 00000000ffffffff
+#4: xscvdpuxws conv(0123214569900000) = 0000000000000000
+#5: xscvdpuxws conv(0000000000000000) = 0000000000000000
+#6: xscvdpuxws conv(8000000000000000) = 0000000000000000
+#7: xscvdpuxws conv(7ff0000000000000) = 00000000ffffffff
+#8: xscvdpuxws conv(fff0000000000000) = 0000000000000000
+#9: xscvdpuxws conv(7ff7ffffffffffff) = 0000000000000000
+#10: xscvdpuxws conv(fff7ffffffffffff) = 0000000000000000
+#11: xscvdpuxws conv(7ff8000000000000) = 0000000000000000
+#12: xscvdpuxws conv(fff8000000000000) = 0000000000000000
+#13: xscvdpuxws conv(8008340000078000) = 0000000000000000
+#14: xscvdpuxws conv(c0d0650f5a07b353) = 0000000000000000
+#15: xscvdpuxws conv(41232585a9900000) = 00000000000992c2
+#16: xscvdpuxws conv(41382511a2000000) = 0000000000182511
+#17: xscvdpuxws conv(40312ef5a9300000) = 0000000000000011
+#18: xscvdpuxws conv(40514bf5d2300000) = 0000000000000045
+#19: xscvdpuxws conv(40976bf982440000) = 00000000000005da
+
+#0: xscvspdp conv(3ec00000) = 3fd8000000000000
+#1: xscvspdp conv(42780000) = 404f000000000000
+#2: xscvspdp conv(00000000) = 0000000000000000
+#3: xscvspdp conv(7f800000) = 7ff0000000000000
+#4: xscvspdp conv(00000000) = 0000000000000000
+#5: xscvspdp conv(00000000) = 0000000000000000
+#6: xscvspdp conv(80000000) = 8000000000000000
+#7: xscvspdp conv(7f800000) = 7ff0000000000000
+#8: xscvspdp conv(ff800000) = fff0000000000000
+#9: xscvspdp conv(7fffffff) = 7fffffffe0000000
+#10: xscvspdp conv(ffffffff) = ffffffffe0000000
+#11: xscvspdp conv(7fc00000) = 7ff8000000000000
+#12: xscvspdp conv(ffc00000) = fff8000000000000
+#13: xscvspdp conv(80000000) = 8000000000000000
+#14: xscvspdp conv(c683287b) = c0d0650f60000000
+#15: xscvspdp conv(49192c2d) = 41232585a0000000
+#16: xscvspdp conv(49c1288d) = 41382511a0000000
+#17: xscvspdp conv(418977ad) = 40312ef5a0000000
+#18: xscvspdp conv(428a5faf) = 40514bf5e0000000
+#19: xscvspdp conv(44bb5fcc) = 40976bf980000000
+
+#0: xvcvdpsp conv(3fd8000000000000) = 3ec0000000000000; conv(404f000000000000) = 4278000000000000
+#1: xvcvdpsp conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = 7f80000000000000
+#2: xvcvdpsp conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpsp conv(8000000000000000) = 8000000000000000; conv(7ff0000000000000) = 7f80000000000000
+#4: xvcvdpsp conv(fff0000000000000) = ff80000000000000; conv(7ff7ffffffffffff) = 7fffffff00000000
+#5: xvcvdpsp conv(fff7ffffffffffff) = ffffffff00000000; conv(7ff8000000000000) = 7fc0000000000000
+#6: xvcvdpsp conv(fff8000000000000) = ffc0000000000000; conv(8008340000078000) = 8000000000000000
+#7: xvcvdpsp conv(c0d0650f5a07b353) = c683287b00000000; conv(41232585a9900000) = 49192c2d00000000
+#8: xvcvdpsp conv(41382511a2000000) = 49c1288d00000000; conv(40312ef5a9300000) = 418977ad00000000
+#9: xvcvdpsp conv(40514bf5d2300000) = 428a5faf00000000; conv(40976bf982440000) = 44bb5fcc00000000
+
+#0: xvcvdpuxds conv(3fd8000000000000) = 0000000000000000; conv(404f000000000000) = 000000000000003e
+#1: xvcvdpuxds conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = ffffffffffffffff
+#2: xvcvdpuxds conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpuxds conv(8000000000000000) = 0000000000000000; conv(7ff0000000000000) = ffffffffffffffff
+#4: xvcvdpuxds conv(fff0000000000000) = 0000000000000000; conv(7ff7ffffffffffff) = 0000000000000000
+#5: xvcvdpuxds conv(fff7ffffffffffff) = 0000000000000000; conv(7ff8000000000000) = 0000000000000000
+#6: xvcvdpuxds conv(fff8000000000000) = 0000000000000000; conv(8008340000078000) = 0000000000000000
+#7: xvcvdpuxds conv(c0d0650f5a07b353) = 0000000000000000; conv(41232585a9900000) = 00000000000992c2
+#8: xvcvdpuxds conv(41382511a2000000) = 0000000000182511; conv(40312ef5a9300000) = 0000000000000011
+#9: xvcvdpuxds conv(40514bf5d2300000) = 0000000000000045; conv(40976bf982440000) = 00000000000005da
+
+#0: xvcvdpuxws conv(3fd8000000000000) = 0000000000000000; conv(404f000000000000) = 0000003e00000000
+#1: xvcvdpuxws conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = ffffffff00000000
+#2: xvcvdpuxws conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpuxws conv(8000000000000000) = 0000000000000000; conv(7ff0000000000000) = ffffffff00000000
+#4: xvcvdpuxws conv(fff0000000000000) = 0000000000000000; conv(7ff7ffffffffffff) = 0000000000000000
+#5: xvcvdpuxws conv(fff7ffffffffffff) = 0000000000000000; conv(7ff8000000000000) = 0000000000000000
+#6: xvcvdpuxws conv(fff8000000000000) = 0000000000000000; conv(8008340000078000) = 0000000000000000
+#7: xvcvdpuxws conv(c0d0650f5a07b353) = 0000000000000000; conv(41232585a9900000) = 000992c200000000
+#8: xvcvdpuxws conv(41382511a2000000) = 0018251100000000; conv(40312ef5a9300000) = 0000001100000000
+#9: xvcvdpuxws conv(40514bf5d2300000) = 0000004500000000; conv(40976bf982440000) = 000005da00000000
+
+#0: xvcvspdp conv(3ec00000) = 3fd8000000000000; conv(42780000) = 404f000000000000
+#1: xvcvspdp conv(00000000) = 0000000000000000; conv(7f800000) = 7ff0000000000000
+#2: xvcvspdp conv(00000000) = 0000000000000000; conv(00000000) = 0000000000000000
+#3: xvcvspdp conv(80000000) = 8000000000000000; conv(7f800000) = 7ff0000000000000
+#4: xvcvspdp conv(ff800000) = fff0000000000000; conv(7fffffff) = 7fffffffe0000000
+#5: xvcvspdp conv(ffffffff) = ffffffffe0000000; conv(7fc00000) = 7ff8000000000000
+#6: xvcvspdp conv(ffc00000) = fff8000000000000; conv(80000000) = 8000000000000000
+#7: xvcvspdp conv(c683287b) = c0d0650f60000000; conv(49192c2d) = 41232585a0000000
+#8: xvcvspdp conv(49c1288d) = 41382511a0000000; conv(418977ad) = 40312ef5a0000000
+#9: xvcvspdp conv(428a5faf) = 40514bf5e0000000; conv(44bb5fcc) = 40976bf980000000
+
+#0: xvcvspsxds conv(3ec00000) = 0000000000000000; conv(42780000) = 000000000000003e
+#1: xvcvspsxds conv(00000000) = 0000000000000000; conv(7f800000) = 7fffffffffffffff
+#2: xvcvspsxds conv(00000000) = 0000000000000000; conv(00000000) = 0000000000000000
+#3: xvcvspsxds conv(80000000) = 0000000000000000; conv(7f800000) = 7fffffffffffffff
+#4: xvcvspsxds conv(ff800000) = 8000000000000000; conv(7fffffff) = 8000000000000000
+#5: xvcvspsxds conv(ffffffff) = 8000000000000000; conv(7fc00000) = 8000000000000000
+#6: xvcvspsxds conv(ffc00000) = 8000000000000000; conv(80000000) = 0000000000000000
+#7: xvcvspsxds conv(c683287b) = ffffffffffffbe6c; conv(49192c2d) = 00000000000992c2
+#8: xvcvspsxds conv(49c1288d) = 0000000000182511; conv(418977ad) = 0000000000000011
+#9: xvcvspsxds conv(428a5faf) = 0000000000000045; conv(44bb5fcc) = 00000000000005da
+
+#0: xvcvdpsxds conv(3fd8000000000000) = 0000000000000000; conv(404f000000000000) = 000000000000003e
+#1: xvcvdpsxds conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = 7fffffffffffffff
+#2: xvcvdpsxds conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpsxds conv(8000000000000000) = 0000000000000000; conv(7ff0000000000000) = 7fffffffffffffff
+#4: xvcvdpsxds conv(fff0000000000000) = 8000000000000000; conv(7ff7ffffffffffff) = 8000000000000000
+#5: xvcvdpsxds conv(fff7ffffffffffff) = 8000000000000000; conv(7ff8000000000000) = 8000000000000000
+#6: xvcvdpsxds conv(fff8000000000000) = 8000000000000000; conv(8008340000078000) = 0000000000000000
+#7: xvcvdpsxds conv(c0d0650f5a07b353) = ffffffffffffbe6c; conv(41232585a9900000) = 00000000000992c2
+#8: xvcvdpsxds conv(41382511a2000000) = 0000000000182511; conv(40312ef5a9300000) = 0000000000000011
+#9: xvcvdpsxds conv(40514bf5d2300000) = 0000000000000045; conv(40976bf982440000) = 00000000000005da
+
+#0: xvcvspuxds conv(3ec00000) = 0000000000000000; conv(42780000) = 000000000000003e
+#1: xvcvspuxds conv(00000000) = 0000000000000000; conv(7f800000) = ffffffffffffffff
+#2: xvcvspuxds conv(00000000) = 0000000000000000; conv(00000000) = 0000000000000000
+#3: xvcvspuxds conv(80000000) = 0000000000000000; conv(7f800000) = ffffffffffffffff
+#4: xvcvspuxds conv(ff800000) = 0000000000000000; conv(7fffffff) = 0000000000000000
+#5: xvcvspuxds conv(ffffffff) = 0000000000000000; conv(7fc00000) = 0000000000000000
+#6: xvcvspuxds conv(ffc00000) = 0000000000000000; conv(80000000) = 0000000000000000
+#7: xvcvspuxds conv(c683287b) = 0000000000000000; conv(49192c2d) = 00000000000992c2
+#8: xvcvspuxds conv(49c1288d) = 0000000000182511; conv(418977ad) = 0000000000000011
+#9: xvcvspuxds conv(428a5faf) = 0000000000000045; conv(44bb5fcc) = 00000000000005da
+
+#0: xvcvspuxws conv(3ec00000) = 00000000; conv(42780000) = 0000003e; conv(00000000) = 00000000; conv(7f800000) = ffffffff
+#1: xvcvspuxws conv(00000000) = 00000000; conv(00000000) = 00000000; conv(80000000) = 00000000; conv(7f800000) = ffffffff
+#2: xvcvspuxws conv(ff800000) = 00000000; conv(7fffffff) = 00000000; conv(ffffffff) = 00000000; conv(7fc00000) = 00000000
+#3: xvcvspuxws conv(ffc00000) = 00000000; conv(80000000) = 00000000; conv(c683287b) = 00000000; conv(49192c2d) = 000992c2
+#4: xvcvspuxws conv(49c1288d) = 00182511; conv(418977ad) = 00000011; conv(428a5faf) = 00000045; conv(44bb5fcc) = 000005da
+
+#0: xsrdpic round(3fd8000000000000) = 0000000000000000
+#1: xsrdpic round(404f000000000000) = 404f000000000000
+#2: xsrdpic round(0018000000b77501) = 0000000000000000
+#3: xsrdpic round(7fe800000000051b) = 7fe800000000051b
+#4: xsrdpic round(0123214569900000) = 0000000000000000
+#5: xsrdpic round(0000000000000000) = 0000000000000000
+#6: xsrdpic round(8000000000000000) = 8000000000000000
+#7: xsrdpic round(7ff0000000000000) = 7ff0000000000000
+#8: xsrdpic round(fff0000000000000) = fff0000000000000
+#9: xsrdpic round(7ff7ffffffffffff) = 7fffffffffffffff
+#10: xsrdpic round(fff7ffffffffffff) = ffffffffffffffff
+#11: xsrdpic round(7ff8000000000000) = 7ff8000000000000
+#12: xsrdpic round(fff8000000000000) = fff8000000000000
+#13: xsrdpic round(8008340000078000) = 8000000000000000
+#14: xsrdpic round(c0d0650f5a07b353) = c0d0650000000000
+#15: xsrdpic round(41232585a9900000) = 4123258600000000
+#16: xsrdpic round(41382511a2000000) = 4138251200000000
+#17: xsrdpic round(40312ef5a9300000) = 4031000000000000
+#18: xsrdpic round(40514bf5d2300000) = 4051400000000000
+#19: xsrdpic round(40976bf982440000) = 40976c0000000000
+
+#0: xsrdpiz round(3fd8000000000000) = 0000000000000000
+#1: xsrdpiz round(404f000000000000) = 404f000000000000
+#2: xsrdpiz round(0018000000b77501) = 0000000000000000
+#3: xsrdpiz round(7fe800000000051b) = 7fe800000000051b
+#4: xsrdpiz round(0123214569900000) = 0000000000000000
+#5: xsrdpiz round(0000000000000000) = 0000000000000000
+#6: xsrdpiz round(8000000000000000) = 8000000000000000
+#7: xsrdpiz round(7ff0000000000000) = 7ff0000000000000
+#8: xsrdpiz round(fff0000000000000) = fff0000000000000
+#9: xsrdpiz round(7ff7ffffffffffff) = 7fffffffffffffff
+#10: xsrdpiz round(fff7ffffffffffff) = ffffffffffffffff
+#11: xsrdpiz round(7ff8000000000000) = 7ff8000000000000
+#12: xsrdpiz round(fff8000000000000) = fff8000000000000
+#13: xsrdpiz round(8008340000078000) = 8000000000000000
+#14: xsrdpiz round(c0d0650f5a07b353) = c0d0650000000000
+#15: xsrdpiz round(41232585a9900000) = 4123258400000000
+#16: xsrdpiz round(41382511a2000000) = 4138251100000000
+#17: xsrdpiz round(40312ef5a9300000) = 4031000000000000
+#18: xsrdpiz round(40514bf5d2300000) = 4051400000000000
+#19: xsrdpiz round(40976bf982440000) = 4097680000000000
+
+#0: xsrdpi round(3fd8000000000000) = 0000000000000000
+#1: xsrdpi round(404f000000000000) = 404f000000000000
+#2: xsrdpi round(0018000000b77501) = 0000000000000000
+#3: xsrdpi round(7fe800000000051b) = 7fe800000000051b
+#4: xsrdpi round(0123214569900000) = 0000000000000000
+#5: xsrdpi round(0000000000000000) = 0000000000000000
+#6: xsrdpi round(8000000000000000) = 8000000000000000
+#7: xsrdpi round(7ff0000000000000) = 7ff0000000000000
+#8: xsrdpi round(fff0000000000000) = fff0000000000000
+#9: xsrdpi round(7ff7ffffffffffff) = 7fffffffffffffff
+#10: xsrdpi round(fff7ffffffffffff) = ffffffffffffffff
+#11: xsrdpi round(7ff8000000000000) = 7ff8000000000000
+#12: xsrdpi round(fff8000000000000) = fff8000000000000
+#13: xsrdpi round(8008340000078000) = 8000000000000000
+#14: xsrdpi round(c0d0650f5a07b353) = c0d0650000000000
+#15: xsrdpi round(41232585a9900000) = 4123258600000000
+#16: xsrdpi round(41382511a2000000) = 4138251200000000
+#17: xsrdpi round(40312ef5a9300000) = 4031000000000000
+#18: xsrdpi round(40514bf5d2300000) = 4051400000000000
+#19: xsrdpi round(40976bf982440000) = 40976c0000000000
+
+#0: xvabsdp abs(3fd8000000000000) = 3fd8000000000000; abs(404f000000000000) = 404f000000000000
+#1: xvabsdp abs(0018000000b77501) = 0018000000b77501; abs(7fe800000000051b) = 7fe800000000051b
+#2: xvabsdp abs(0123214569900000) = 0123214569900000; abs(0000000000000000) = 0000000000000000
+#3: xvabsdp abs(8000000000000000) = 0000000000000000; abs(7ff0000000000000) = 7ff0000000000000
+#4: xvabsdp abs(fff0000000000000) = 7ff0000000000000; abs(7ff7ffffffffffff) = 7ff7ffffffffffff
+#5: xvabsdp abs(fff7ffffffffffff) = 7ff7ffffffffffff; abs(7ff8000000000000) = 7ff8000000000000
+#6: xvabsdp abs(fff8000000000000) = 7ff8000000000000; abs(8008340000078000) = 0008340000078000
+#7: xvabsdp abs(c0d0650f5a07b353) = 40d0650f5a07b353; abs(41232585a9900000) = 41232585a9900000
+#8: xvabsdp abs(41382511a2000000) = 41382511a2000000; abs(40312ef5a9300000) = 40312ef5a9300000
+#9: xvabsdp abs(40514bf5d2300000) = 40514bf5d2300000; abs(40976bf982440000) = 40976bf982440000
+
+#0: xvnabsdp nabs(3fd8000000000000) = bfd8000000000000; nabs(404f000000000000) = c04f000000000000
+#1: xvnabsdp nabs(0018000000b77501) = 8018000000b77501; nabs(7fe800000000051b) = ffe800000000051b
+#2: xvnabsdp nabs(0123214569900000) = 8123214569900000; nabs(0000000000000000) = 8000000000000000
+#3: xvnabsdp nabs(8000000000000000) = 8000000000000000; nabs(7ff0000000000000) = fff0000000000000
+#4: xvnabsdp nabs(fff0000000000000) = fff0000000000000; nabs(7ff7ffffffffffff) = fff7ffffffffffff
+#5: xvnabsdp nabs(fff7ffffffffffff) = fff7ffffffffffff; nabs(7ff8000000000000) = fff8000000000000
+#6: xvnabsdp nabs(fff8000000000000) = fff8000000000000; nabs(8008340000078000) = 8008340000078000
+#7: xvnabsdp nabs(c0d0650f5a07b353) = c0d0650f5a07b353; nabs(41232585a9900000) = c1232585a9900000
+#8: xvnabsdp nabs(41382511a2000000) = c1382511a2000000; nabs(40312ef5a9300000) = c0312ef5a9300000
+#9: xvnabsdp nabs(40514bf5d2300000) = c0514bf5d2300000; nabs(40976bf982440000) = c0976bf982440000
+
+#0: xvnegdp neg(3fd8000000000000) = bfd8000000000000; neg(404f000000000000) = c04f000000000000
+#1: xvnegdp neg(0018000000b77501) = 8018000000b77501; neg(7fe800000000051b) = ffe800000000051b
+#2: xvnegdp neg(0123214569900000) = 8123214569900000; neg(0000000000000000) = 8000000000000000
+#3: xvnegdp neg(8000000000000000) = 0000000000000000; neg(7ff0000000000000) = fff0000000000000
+#4: xvnegdp neg(fff0000000000000) = 7ff0000000000000; neg(7ff7ffffffffffff) = fff7ffffffffffff
+#5: xvnegdp neg(fff7ffffffffffff) = 7ff7ffffffffffff; neg(7ff8000000000000) = fff8000000000000
+#6: xvnegdp neg(fff8000000000000) = 7ff8000000000000; neg(8008340000078000) = 0008340000078000
+#7: xvnegdp neg(c0d0650f5a07b353) = 40d0650f5a07b353; neg(41232585a9900000) = c1232585a9900000
+#8: xvnegdp neg(41382511a2000000) = c1382511a2000000; neg(40312ef5a9300000) = c0312ef5a9300000
+#9: xvnegdp neg(40514bf5d2300000) = c0514bf5d2300000; neg(40976bf982440000) = c0976bf982440000
+
+#0: xvabssp abs(3ec00000) = 3ec00000; abs(42780000) = 42780000; abs(00000000) = 00000000; abs(7f800000) = 7f800000
+#1: xvabssp abs(00000000) = 00000000; abs(00000000) = 00000000; abs(80000000) = 00000000; abs(7f800000) = 7f800000
+#2: xvabssp abs(ff800000) = 7f800000; abs(7fffffff) = 7fffffff; abs(ffffffff) = 7fffffff; abs(7fc00000) = 7fc00000
+#3: xvabssp abs(ffc00000) = 7fc00000; abs(80000000) = 00000000; abs(c683287b) = 4683287b; abs(49192c2d) = 49192c2d
+#4: xvabssp abs(49c1288d) = 49c1288d; abs(418977ad) = 418977ad; abs(428a5faf) = 428a5faf; abs(44bb5fcc) = 44bb5fcc
+
+#0: xvnabssp nabs(3ec00000) = bec00000; nabs(42780000) = c2780000; nabs(00000000) = 80000000; nabs(7f800000) = ff800000
+#1: xvnabssp nabs(00000000) = 80000000; nabs(00000000) = 80000000; nabs(80000000) = 80000000; nabs(7f800000) = ff800000
+#2: xvnabssp nabs(ff800000) = ff800000; nabs(7fffffff) = ffffffff; nabs(ffffffff) = ffffffff; nabs(7fc00000) = ffc00000
+#3: xvnabssp nabs(ffc00000) = ffc00000; nabs(80000000) = 80000000; nabs(c683287b) = c683287b; nabs(49192c2d) = c9192c2d
+#4: xvnabssp nabs(49c1288d) = c9c1288d; nabs(418977ad) = c18977ad; nabs(428a5faf) = c28a5faf; nabs(44bb5fcc) = c4bb5fcc
+
+#0: xvrdpi round(3fd8000000000000) = 0000000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpi round(0018000000b77501) = 0000000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpi round(0123214569900000) = 0000000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpi round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpi round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpi round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpi round(fff8000000000000) = fff8000000000000; round(8008340000078000) = 8000000000000000
+#7: xvrdpi round(c0d0650f5a07b353) = c0d0650000000000; round(41232585a9900000) = 4123258600000000
+#8: xvrdpi round(41382511a2000000) = 4138251200000000; round(40312ef5a9300000) = 4031000000000000
+#9: xvrdpi round(40514bf5d2300000) = 4051400000000000; round(40976bf982440000) = 40976c0000000000
+
+#0: xvrdpic round(3fd8000000000000) = 0000000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpic round(0018000000b77501) = 0000000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpic round(0123214569900000) = 0000000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpic round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpic round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpic round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpic round(fff8000000000000) = fff8000000000000; round(8008340000078000) = 8000000000000000
+#7: xvrdpic round(c0d0650f5a07b353) = c0d0650000000000; round(41232585a9900000) = 4123258600000000
+#8: xvrdpic round(41382511a2000000) = 4138251200000000; round(40312ef5a9300000) = 4031000000000000
+#9: xvrdpic round(40514bf5d2300000) = 4051400000000000; round(40976bf982440000) = 40976c0000000000
+
+#0: xvrdpim round(3fd8000000000000) = 0000000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpim round(0018000000b77501) = 0000000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpim round(0123214569900000) = 0000000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpim round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpim round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpim round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpim round(fff8000000000000) = fff8000000000000; round(8008340000078000) = bff0000000000000
+#7: xvrdpim round(c0d0650f5a07b353) = c0d0654000000000; round(41232585a9900000) = 4123258400000000
+#8: xvrdpim round(41382511a2000000) = 4138251100000000; round(40312ef5a9300000) = 4031000000000000
+#9: xvrdpim round(40514bf5d2300000) = 4051400000000000; round(40976bf982440000) = 4097680000000000
+
+#0: xvrdpip round(3fd8000000000000) = 3ff0000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpip round(0018000000b77501) = 3ff0000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpip round(0123214569900000) = 3ff0000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpip round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpip round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpip round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpip round(fff8000000000000) = fff8000000000000; round(8008340000078000) = 8000000000000000
+#7: xvrdpip round(c0d0650f5a07b353) = c0d0650000000000; round(41232585a9900000) = 4123258600000000
+#8: xvrdpip round(41382511a2000000) = 4138251200000000; round(40312ef5a9300000) = 4032000000000000
+#9: xvrdpip round(40514bf5d2300000) = 4051800000000000; round(40976bf982440000) = 40976c0000000000
+
+#0: xvrdpiz round(3fd8000000000000) = 0000000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpiz round(0018000000b77501) = 0000000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpiz round(0123214569900000) = 0000000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpiz round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpiz round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpiz round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpiz round(fff8000000000000) = fff8000000000000; round(8008340000078000) = 8000000000000000
+#7: xvrdpiz round(c0d0650f5a07b353) = c0d0650000000000; round(41232585a9900000) = 4123258400000000
+#8: xvrdpiz round(41382511a2000000) = 4138251100000000; round(40312ef5a9300000) = 4031000000000000
+#9: xvrdpiz round(40514bf5d2300000) = 4051400000000000; round(40976bf982440000) = 4097680000000000
+
+#0: xvrspi round(3ec00000) = 00000000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspi round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspi round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspi round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832800; round(49192c2d) = 49192c30
+#4: xvrspi round(49c1288d) = 49c12890; round(418977ad) = 41880000; round(428a5faf) = 428a0000; round(44bb5fcc) = 44bb6000
+
+#0: xvrspic round(3ec00000) = 00000000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspic round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspic round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspic round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832800; round(49192c2d) = 49192c30
+#4: xvrspic round(49c1288d) = 49c12890; round(418977ad) = 41880000; round(428a5faf) = 428a0000; round(44bb5fcc) = 44bb6000
+
+#0: xvrspim round(3ec00000) = 00000000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspim round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspim round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspim round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832a00; round(49192c2d) = 49192c20
+#4: xvrspim round(49c1288d) = 49c12888; round(418977ad) = 41880000; round(428a5faf) = 428a0000; round(44bb5fcc) = 44bb4000
+
+#0: xvrspip round(3ec00000) = 3f800000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspip round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspip round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspip round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832800; round(49192c2d) = 49192c30
+#4: xvrspip round(49c1288d) = 49c12890; round(418977ad) = 41900000; round(428a5faf) = 428c0000; round(44bb5fcc) = 44bb6000
+
+#0: xvrspiz round(3ec00000) = 00000000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspiz round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspiz round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspiz round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832800; round(49192c2d) = 49192c20
+#4: xvrspiz round(49c1288d) = 49c12888; round(418977ad) = 41880000; round(428a5faf) = 428a0000; round(44bb5fcc) = 44bb4000
+
+Test VSX vector integer to float conversion instructions
+#0: xvcvsxddp conv(0000000000000000) = 0000000000000000; conv(ffffffff00000000) = c1f0000000000000
+#1: xvcvsxddp conv(00000000ffffffff) = 41efffffffe00000; conv(ffffffffffffffff) = bff0000000000000
+#2: xvcvsxddp conv(89abcde123456789) = c3dd950c87b72ea6; conv(0102030405060708) = 4370203040506070
+#3: xvcvsxddp conv(00000000a0b1c2d3) = 41e416385a600000; conv(1111222233334444) = 43b1112222333344
+
+#0: xvcvuxddp conv(0000000000000000) = 0000000000000000; conv(ffffffff00000000) = 43efffffffe00000
+#1: xvcvuxddp conv(00000000ffffffff) = 41efffffffe00000; conv(ffffffffffffffff) = 43f0000000000000
+#2: xvcvuxddp conv(89abcde123456789) = 43e13579bc2468ad; conv(0102030405060708) = 4370203040506070
+#3: xvcvuxddp conv(00000000a0b1c2d3) = 41e416385a600000; conv(1111222233334444) = 43b1112222333344
+
+#0: xvcvsxdsp conv(0000000000000000) = 0000000000000000; conv(ffffffff00000000) = cf80000000000000
+#1: xvcvsxdsp conv(00000000ffffffff) = 4f80000000000000; conv(ffffffffffffffff) = bf80000000000000
+#2: xvcvsxdsp conv(89abcde123456789) = deeca86400000000; conv(0102030405060708) = 5b81018200000000
+#3: xvcvsxdsp conv(00000000a0b1c2d3) = 4f20b1c300000000; conv(1111222233334444) = 5d88891100000000
+
+#0: xvcvuxdsp conv(0000000000000000) = 0000000000000000; conv(ffffffff00000000) = 5f80000000000000
+#1: xvcvuxdsp conv(00000000ffffffff) = 4f80000000000000; conv(ffffffffffffffff) = 5f80000000000000
+#2: xvcvuxdsp conv(89abcde123456789) = 5f09abce00000000; conv(0102030405060708) = 5b81018200000000
+#3: xvcvuxdsp conv(00000000a0b1c2d3) = 4f20b1c300000000; conv(1111222233334444) = 5d88891100000000
+
+#0: xvcvsxwdp conv(00000000) = 0000000000000000; conv(ffff0000) = c0f0000000000000
+#1: xvcvsxwdp conv(0000ffff) = 40efffe000000000; conv(ffffffff) = bff0000000000000
+#2: xvcvsxwdp conv(89a73522) = c1dd9632b7800000; conv(01020304) = 4170203040000000
+#3: xvcvsxwdp conv(0000abcd) = 40e579a000000000; conv(11223344) = 41b1223344000000
+
+#0: xvcvuxwdp conv(00000000) = 0000000000000000; conv(ffff0000) = 41efffe000000000
+#1: xvcvuxwdp conv(0000ffff) = 40efffe000000000; conv(ffffffff) = 41efffffffe00000
+#2: xvcvuxwdp conv(89a73522) = 41e134e6a4400000; conv(01020304) = 4170203040000000
+#3: xvcvuxwdp conv(0000abcd) = 40e579a000000000; conv(11223344) = 41b1223344000000
+
+#0: xvcvsxwsp conv(00000000) = 00000000; conv(ffff0000) = c7800000; conv(0000ffff) = 477fff00; conv(ffffffff) = bf800000
+#1: xvcvsxwsp conv(89a73522) = ceecb196; conv(01020304) = 4b810182; conv(0000abcd) = 472bcd00; conv(11223344) = 4d89119a
+
+#0: xvcvuxwsp conv(00000000) = 00000000; conv(ffff0000) = 4f7fff00; conv(0000ffff) = 477fff00; conv(ffffffff) = 4f800000
+#1: xvcvuxwsp conv(89a73522) = 4f09a735; conv(01020304) = 4b810182; conv(0000abcd) = 472bcd00; conv(11223344) = 4d89119a
+
+Test div extensions
+#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divwe: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divwe: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=0
+#3: divwe: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divwe: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divwe: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divwe.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divwe.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divwe.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=2; XER=0
+#3: divwe.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divwe.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divwe.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
+
+
+#0: divweo: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweo: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweo: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=c0000000
+#3: divweo: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweo: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweo: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divweo.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweo.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweo.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=3; XER=c0000000
+#3: divweo.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweo.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweo.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
+
+
+Test ftsqrt instruction
+ftsqrt: 3fd8000000000000 ? 8 (CRx)
+ftsqrt: 404f000000000000 ? 8 (CRx)
+ftsqrt: 0018000000b77501 ? a (CRx)
+ftsqrt: 7fe800000000051b ? 8 (CRx)
+ftsqrt: 0123214569900000 ? a (CRx)
+ftsqrt: 0000000000000000 ? e (CRx)
+ftsqrt: 8000000000000000 ? e (CRx)
+ftsqrt: 7ff0000000000000 ? e (CRx)
+ftsqrt: fff0000000000000 ? e (CRx)
+ftsqrt: 7ff7ffffffffffff ? a (CRx)
+ftsqrt: fff7ffffffffffff ? a (CRx)
+ftsqrt: 7ff8000000000000 ? a (CRx)
+ftsqrt: fff8000000000000 ? a (CRx)
+ftsqrt: 8008340000078000 ? e (CRx)
+ftsqrt: c0d0650f5a07b353 ? a (CRx)
+ftsqrt: 41232585a9900000 ? 8 (CRx)
+ftsqrt: 41382511a2000000 ? 8 (CRx)
+ftsqrt: 40312ef5a9300000 ? 8 (CRx)
+ftsqrt: 40514bf5d2300000 ? 8 (CRx)
+ftsqrt: 40976bf982440000 ? 8 (CRx)
+
+Test vector and scalar tdiv and tsqrt instructions
+#0: xstsqrtdp test-sqrt(3fd8000000000000) ? 8 (CRx)
+#1: xstsqrtdp test-sqrt(404f000000000000) ? 8 (CRx)
+#2: xstsqrtdp test-sqrt(0018000000b77501) ? a (CRx)
+#3: xstsqrtdp test-sqrt(7fe800000000051b) ? 8 (CRx)
+#4: xstsqrtdp test-sqrt(0123214569900000) ? a (CRx)
+#5: xstsqrtdp test-sqrt(0000000000000000) ? e (CRx)
+#6: xstsqrtdp test-sqrt(8000000000000000) ? e (CRx)
+#7: xstsqrtdp test-sqrt(7ff0000000000000) ? e (CRx)
+#8: xstsqrtdp test-sqrt(fff0000000000000) ? e (CRx)
+#9: xstsqrtdp test-sqrt(7ff7ffffffffffff) ? a (CRx)
+#10: xstsqrtdp test-sqrt(fff7ffffffffffff) ? a (CRx)
+#11: xstsqrtdp test-sqrt(7ff8000000000000) ? a (CRx)
+#12: xstsqrtdp test-sqrt(fff8000000000000) ? a (CRx)
+#13: xstsqrtdp test-sqrt(8008340000078000) ? e (CRx)
+#14: xstsqrtdp test-sqrt(c0d0650f5a07b353) ? a (CRx)
+#15: xstsqrtdp test-sqrt(41232585a9900000) ? 8 (CRx)
+#16: xstsqrtdp test-sqrt(41382511a2000000) ? 8 (CRx)
+#17: xstsqrtdp test-sqrt(40312ef5a9300000) ? 8 (CRx)
+#18: xstsqrtdp test-sqrt(40514bf5d2300000) ? 8 (CRx)
+#19: xstsqrtdp test-sqrt(40976bf982440000) ? 8 (CRx)
+
+#0: xvtsqrtdp test-sqrt(3fd8000000000000); test-sqrt(404f000000000000) ? 8 (CRx)
+#1: xvtsqrtdp test-sqrt(0018000000b77501); test-sqrt(7fe800000000051b) ? a (CRx)
+#2: xvtsqrtdp test-sqrt(0123214569900000); test-sqrt(0000000000000000) ? e (CRx)
+#3: xvtsqrtdp test-sqrt(8000000000000000); test-sqrt(7ff0000000000000) ? e (CRx)
+#4: xvtsqrtdp test-sqrt(fff0000000000000); test-sqrt(7ff7ffffffffffff) ? e (CRx)
+#5: xvtsqrtdp test-sqrt(fff7ffffffffffff); test-sqrt(7ff8000000000000) ? a (CRx)
+#6: xvtsqrtdp test-sqrt(fff8000000000000); test-sqrt(8008340000078000) ? e (CRx)
+#7: xvtsqrtdp test-sqrt(c0d0650f5a07b353); test-sqrt(41232585a9900000) ? a (CRx)
+#8: xvtsqrtdp test-sqrt(41382511a2000000); test-sqrt(40312ef5a9300000) ? 8 (CRx)
+#9: xvtsqrtdp test-sqrt(40514bf5d2300000); test-sqrt(40976bf982440000) ? 8 (CRx)
+
+#0: xvtsqrtsp test-sqrt(3ec00000); test-sqrt(42780000); test-sqrt(00000000); test-sqrt(7f800000) ? e (CRx)
+#1: xvtsqrtsp test-sqrt(00000000); test-sqrt(00000000); test-sqrt(80000000); test-sqrt(7f800000) ? e (CRx)
+#2: xvtsqrtsp test-sqrt(ff800000); test-sqrt(7fffffff); test-sqrt(ffffffff); test-sqrt(7fc00000) ? e (CRx)
+#3: xvtsqrtsp test-sqrt(ffc00000); test-sqrt(80000000); test-sqrt(c683287b); test-sqrt(49192c2d) ? e (CRx)
+#4: xvtsqrtsp test-sqrt(49c1288d); test-sqrt(418977ad); test-sqrt(428a5faf); test-sqrt(44bb5fcc) ? 8 (CRx)
+
+#0: xvtdivdp fff0000000000000 test-div fff0000000000000 AND fff0000000000000 test-div c0d0650f5a07b353 ? cc=e
+#1: xvtdivdp 41232585a9900000 test-div 41382511a2000000 AND fff0000000000000 test-div 0000000000000000 ? cc=e
+#2: xvtdivdp fff0000000000000 test-div 0123214569900000 AND fff0000000000000 test-div 7ff0000000000000 ? cc=e
+#3: xvtdivdp fff0000000000000 test-div 7ff7ffffffffffff AND fff0000000000000 test-div 7ff8000000000000 ? cc=e
+#4: xvtdivdp c0d0650f5a07b353 test-div fff0000000000000 AND c0d0650f5a07b353 test-div c0d0650f5a07b353 ? cc=e
+#5: xvtdivdp c0d0650f5a07b353 test-div 8000000000000000 AND c0d0650f5a07b353 test-div 0000000000000000 ? cc=e
+#6: xvtdivdp c0d0650f5a07b353 test-div 0123214569900000 AND c0d0650f5a07b353 test-div 7ff0000000000000 ? cc=e
+#7: xvtdivdp c0d0650f5a07b353 test-div 7ff7ffffffffffff AND c0d0650f5a07b353 test-div 7ff8000000000000 ? cc=a
+#8: xvtdivdp 8000000000000000 test-div fff0000000000000 AND 8000000000000000 test-div c0d0650f5a07b353 ? cc=e
+#9: xvtdivdp 8000000000000000 test-div 8000000000000000 AND 8000000000000000 test-div 0000000000000000 ? cc=e
+#10: xvtdivdp 8000000000000000 test-div 0123214569900000 AND 8000000000000000 test-div 7ff0000000000000 ? cc=e
+#11: xvtdivdp 8000000000000000 test-div 7ff7ffffffffffff AND 8000000000000000 test-div 7ff8000000000000 ? cc=a
+#12: xvtdivdp 0000000000000000 test-div fff0000000000000 AND 0000000000000000 test-div c0d0650f5a07b353 ? cc=e
+#13: xvtdivdp 0000000000000000 test-div 8000000000000000 AND 0000000000000000 test-div 0000000000000000 ? cc=e
+#14: xvtdivdp 0000000000000000 test-div 0123214569900000 AND 0000000000000000 test-div 7ff0000000000000 ? cc=e
+#15: xvtdivdp 0000000000000000 test-div 7ff7ffffffffffff AND 0000000000000000 test-div 7ff8000000000000 ? cc=a
+#16: xvtdivdp 0123214569900000 test-div fff0000000000000 AND 0123214569900000 test-div c0d0650f5a07b353 ? cc=e
+#17: xvtdivdp 0123214569900000 test-div 8000000000000000 AND 0123214569900000 test-div 0000000000000000 ? cc=e
+#18: xvtdivdp 0123214569900000 test-div 404f000000000000 AND 0123214569900000 test-div 7ff0000000000000 ? cc=e
+#19: xvtdivdp 0123214569900000 test-div 7ff7ffffffffffff AND 0123214569900000 test-div 7ff8000000000000 ? cc=a
+#20: xvtdivdp 7ff0000000000000 test-div fff0000000000000 AND 7ff0000000000000 test-div c0d0650f5a07b353 ? cc=e
+#21: xvtdivdp 7ff0000000000000 test-div 8000000000000000 AND 7ff0000000000000 test-div 0000000000000000 ? cc=e
+#22: xvtdivdp 7ff0000000000000 test-div 0123214569900000 AND 7ff0000000000000 test-div 7ff0000000000000 ? cc=e
+#23: xvtdivdp 7ff0000000000000 test-div 7ff7ffffffffffff AND 7ff0000000000000 test-div 7ff8000000000000 ? cc=e
+#24: xvtdivdp fff7ffffffffffff test-div fff0000000000000 AND fff7ffffffffffff test-div c0d0650f5a07b353 ? cc=e
+#25: xvtdivdp fff8000000000000 test-div 8000000000000000 AND fff8000000000000 test-div 0000000000000000 ? cc=e
+#26: xvtdivdp fff7ffffffffffff test-div 0123214569900000 AND fff7ffffffffffff test-div 7ff0000000000000 ? cc=e
+#27: xvtdivdp fff7ffffffffffff test-div 7ff7ffffffffffff AND fff7ffffffffffff test-div 7ff8000000000000 ? cc=a
+#28: xvtdivdp fff8000000000000 test-div fff0000000000000 AND fff8000000000000 test-div c0d0650f5a07b353 ? cc=e
+#29: xvtdivdp fff8000000000000 test-div 8000000000000000 AND 41232585a9900000 test-div 41382511a2000000 ? cc=e
+#30: xvtdivdp 41232585a9900000 test-div 41382511a2000000 AND 7ff7ffffffffffff test-div 7ff8000000000000 ? cc=a
+#31: xvtdivdp 7ff8000000000000 test-div 7ff8000000000000 AND 7ff8000000000000 test-div fff8000000000000 ? cc=a
+#32: xvtdivdp 41382511a2000000 test-div 40514bf5d2300000 AND 40312ef5a9300000 test-div 41382511a2000000 ? cc=8
+#33: xvtdivdp 40976bf982440000 test-div 40976bf982440000 AND 40976bf982440000 test-div 40514bf5d2300000 ? cc=8
+
+#0: xvtdivsp ff800000 test-div ff800000 AND ff800000 test-div c683287b AND 49192c2d test-div 49c1288d AND ff800000 test-div 00000000 ? cc=e
+#1: xvtdivsp ff800000 test-div 00000000 AND ff800000 test-div 7f800000 AND ff800000 test-div 7fffffff AND ff800000 test-div 7fc00000 ? cc=e
+#2: xvtdivsp c683287b test-div ff800000 AND c683287b test-div c683287b AND c683287b test-div 80000000 AND c683287b test-div 00000000 ? cc=e
+#3: xvtdivsp c683287b test-div 00000000 AND c683287b test-div 7f800000 AND c683287b test-div 7fffffff AND c683287b test-div 7fc00000 ? cc=e
+#4: xvtdivsp 80000000 test-div ff800000 AND 80000000 test-div c683287b AND 80000000 test-div 80000000 AND 80000000 test-div 00000000 ? cc=e
+#5: xvtdivsp 80000000 test-div 00000000 AND 80000000 test-div 7f800000 AND 80000000 test-div 7fffffff AND 80000000 test-div 7fc00000 ? cc=e
+#6: xvtdivsp 00000000 test-div ff800000 AND 00000000 test-div c683287b AND 00000000 test-div 80000000 AND 00000000 test-div 00000000 ? cc=e
+#7: xvtdivsp 00000000 test-div 00000000 AND 00000000 test-div 7f800000 AND 00000000 test-div 7fffffff AND 00000000 test-div 7fc00000 ? cc=e
+#8: xvtdivsp 00000000 test-div ff800000 AND 00000000 test-div c683287b AND 00000000 test-div 80000000 AND 00000000 test-div 00000000 ? cc=e
+#9: xvtdivsp 00000000 test-div 42780000 AND 00000000 test-div 7f800000 AND 00000000 test-div 7fffffff AND 00000000 test-div 7fc00000 ? cc=e
+#10: xvtdivsp 7f800000 test-div ff800000 AND 7f800000 test-div c683287b AND 7f800000 test-div 80000000 AND 7f800000 test-div 00000000 ? cc=e
+#11: xvtdivsp 7f800000 test-div 00000000 AND 7f800000 test-div 7f800000 AND 7f800000 test-div 7fffffff AND 7f800000 test-div 7fc00000 ? cc=e
+#12: xvtdivsp ffffffff test-div ff800000 AND ffffffff test-div c683287b AND ffc00000 test-div 80000000 AND ffc00000 test-div 00000000 ? cc=e
+#13: xvtdivsp ffffffff test-div 00000000 AND ffffffff test-div 7f800000 AND ffffffff test-div 7fffffff AND ffffffff test-div 7fc00000 ? cc=e
+#14: xvtdivsp ffc00000 test-div ff800000 AND ffc00000 test-div c683287b AND ffc00000 test-div 80000000 AND 49192c2d test-div 49c1288d ? cc=e
+#15: xvtdivsp 49192c2d test-div 49c1288d AND 7fffffff test-div 7fc00000 AND 7fc00000 test-div 7fc00000 AND 7fc00000 test-div ffc00000 ? cc=a
+#16: xvtdivsp 49c1288d test-div 428a5faf AND 418977ad test-div 49c1288d AND 44bb5fcc test-div 44bb5fcc AND 44bb5fcc test-div 428a5faf ? cc=8
+
+Test popcntw instruction
+popcntw: 0x9182730e => 0x0000000d
+
diff --git a/main/none/tests/ppc32/test_isa_2_06_part3.vgtest b/main/none/tests/ppc32/test_isa_2_06_part3.vgtest
new file mode 100644
index 0000000..3519c8a
--- /dev/null
+++ b/main/none/tests/ppc32/test_isa_2_06_part3.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_06_cap
+prog: test_isa_2_06_part3
diff --git a/main/none/tests/ppc64/Makefile.am b/main/none/tests/ppc64/Makefile.am
index 15b4b39..3213e53 100644
--- a/main/none/tests/ppc64/Makefile.am
+++ b/main/none/tests/ppc64/Makefile.am
@@ -17,16 +17,25 @@
power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \
test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
- test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest
+ test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
+ test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
+ test_dfp2.stdout.exp_Without_dcffix \
+ test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \
+ test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
+ test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest
check_PROGRAMS = \
+ allexec \
jm-insns lsw round std_reg_imm twi_tdi tw_td power6_bcmp power6_mf_gpr test_isa_2_06_part1 \
- test_isa_2_06_part2 test_isa_2_06_part3
+ test_isa_2_06_part2 test_isa_2_06_part3 test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5
AM_CFLAGS += @FLAG_M64@
AM_CXXFLAGS += @FLAG_M64@
AM_CCASFLAGS += @FLAG_M64@
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+
if HAS_ALTIVEC
ALTIVEC_FLAG = -DHAS_ALTIVEC
else
@@ -41,6 +50,14 @@
BUILD_FLAG_VSX =
endif
+if HAS_DFP
+BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6
+DFP_FLAG = -DHAS_DFP
+else
+BUILD_FLAGS_DFP =
+DFP_FLAG =
+endif
+
test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
@@ -53,3 +70,17 @@
jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \
@FLAG_M64@ $(ALTIVEC_FLAG)
+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
diff --git a/main/none/tests/ppc64/Makefile.in b/main/none/tests/ppc64/Makefile.in
new file mode 100644
index 0000000..cdbabab
--- /dev/null
+++ b/main/none/tests/ppc64/Makefile.in
@@ -0,0 +1,1040 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = allexec$(EXEEXT) jm-insns$(EXEEXT) lsw$(EXEEXT) \
+ round$(EXEEXT) std_reg_imm$(EXEEXT) twi_tdi$(EXEEXT) \
+ tw_td$(EXEEXT) power6_bcmp$(EXEEXT) power6_mf_gpr$(EXEEXT) \
+ test_isa_2_06_part1$(EXEEXT) test_isa_2_06_part2$(EXEEXT) \
+ test_isa_2_06_part3$(EXEEXT) test_dfp1$(EXEEXT) \
+ test_dfp2$(EXEEXT) test_dfp3$(EXEEXT) test_dfp4$(EXEEXT) \
+ test_dfp5$(EXEEXT)
+subdir = none/tests/ppc64
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+jm_insns_SOURCES = jm-insns.c
+jm_insns_OBJECTS = jm_insns-jm-insns.$(OBJEXT)
+jm_insns_LDADD = $(LDADD)
+jm_insns_LINK = $(CCLD) $(jm_insns_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+lsw_SOURCES = lsw.c
+lsw_OBJECTS = lsw.$(OBJEXT)
+lsw_LDADD = $(LDADD)
+power6_bcmp_SOURCES = power6_bcmp.c
+power6_bcmp_OBJECTS = power6_bcmp.$(OBJEXT)
+power6_bcmp_LDADD = $(LDADD)
+power6_mf_gpr_SOURCES = power6_mf_gpr.c
+power6_mf_gpr_OBJECTS = power6_mf_gpr.$(OBJEXT)
+power6_mf_gpr_LDADD = $(LDADD)
+round_SOURCES = round.c
+round_OBJECTS = round.$(OBJEXT)
+round_LDADD = $(LDADD)
+std_reg_imm_SOURCES = std_reg_imm.c
+std_reg_imm_OBJECTS = std_reg_imm.$(OBJEXT)
+std_reg_imm_LDADD = $(LDADD)
+test_dfp1_SOURCES = test_dfp1.c
+test_dfp1_OBJECTS = test_dfp1-test_dfp1.$(OBJEXT)
+test_dfp1_LDADD = $(LDADD)
+test_dfp1_LINK = $(CCLD) $(test_dfp1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp2_SOURCES = test_dfp2.c
+test_dfp2_OBJECTS = test_dfp2-test_dfp2.$(OBJEXT)
+test_dfp2_LDADD = $(LDADD)
+test_dfp2_LINK = $(CCLD) $(test_dfp2_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp3_SOURCES = test_dfp3.c
+test_dfp3_OBJECTS = test_dfp3-test_dfp3.$(OBJEXT)
+test_dfp3_LDADD = $(LDADD)
+test_dfp3_LINK = $(CCLD) $(test_dfp3_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp4_SOURCES = test_dfp4.c
+test_dfp4_OBJECTS = test_dfp4-test_dfp4.$(OBJEXT)
+test_dfp4_LDADD = $(LDADD)
+test_dfp4_LINK = $(CCLD) $(test_dfp4_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp5_SOURCES = test_dfp5.c
+test_dfp5_OBJECTS = test_dfp5-test_dfp5.$(OBJEXT)
+test_dfp5_LDADD = $(LDADD)
+test_dfp5_LINK = $(CCLD) $(test_dfp5_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_isa_2_06_part1_SOURCES = test_isa_2_06_part1.c
+test_isa_2_06_part1_OBJECTS = \
+ test_isa_2_06_part1-test_isa_2_06_part1.$(OBJEXT)
+test_isa_2_06_part1_LDADD = $(LDADD)
+test_isa_2_06_part1_LINK = $(CCLD) $(test_isa_2_06_part1_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_isa_2_06_part2_SOURCES = test_isa_2_06_part2.c
+test_isa_2_06_part2_OBJECTS = \
+ test_isa_2_06_part2-test_isa_2_06_part2.$(OBJEXT)
+test_isa_2_06_part2_LDADD = $(LDADD)
+test_isa_2_06_part2_LINK = $(CCLD) $(test_isa_2_06_part2_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_isa_2_06_part3_SOURCES = test_isa_2_06_part3.c
+test_isa_2_06_part3_OBJECTS = \
+ test_isa_2_06_part3-test_isa_2_06_part3.$(OBJEXT)
+test_isa_2_06_part3_LDADD = $(LDADD)
+test_isa_2_06_part3_LINK = $(CCLD) $(test_isa_2_06_part3_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+tw_td_SOURCES = tw_td.c
+tw_td_OBJECTS = tw_td.$(OBJEXT)
+tw_td_LDADD = $(LDADD)
+twi_tdi_SOURCES = twi_tdi.c
+twi_tdi_OBJECTS = twi_tdi.$(OBJEXT)
+twi_tdi_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = allexec.c jm-insns.c lsw.c power6_bcmp.c power6_mf_gpr.c \
+ round.c std_reg_imm.c test_dfp1.c test_dfp2.c test_dfp3.c \
+ test_dfp4.c test_dfp5.c test_isa_2_06_part1.c \
+ test_isa_2_06_part2.c test_isa_2_06_part3.c tw_td.c twi_tdi.c
+DIST_SOURCES = allexec.c jm-insns.c lsw.c power6_bcmp.c \
+ power6_mf_gpr.c round.c std_reg_imm.c test_dfp1.c test_dfp2.c \
+ test_dfp3.c test_dfp4.c test_dfp5.c test_isa_2_06_part1.c \
+ test_isa_2_06_part2.c test_isa_2_06_part3.c tw_td.c twi_tdi.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
+ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
+ jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
+ jm-vmx.vgtest \
+ lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
+ std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp \
+ round.stderr.exp round.stdout.exp round.vgtest \
+ twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \
+ tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \
+ power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
+ power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \
+ test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
+ test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
+ test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
+ test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
+ test_dfp2.stdout.exp_Without_dcffix \
+ test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \
+ test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
+ test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+@HAS_ALTIVEC_FALSE@ALTIVEC_FLAG =
+@HAS_ALTIVEC_TRUE@ALTIVEC_FLAG = -DHAS_ALTIVEC
+@HAS_VSX_FALSE@BUILD_FLAG_VSX =
+@HAS_VSX_TRUE@BUILD_FLAG_VSX = -mvsx
+@HAS_VSX_FALSE@VSX_FLAG =
+@HAS_VSX_TRUE@VSX_FLAG = -DHAS_VSX
+@HAS_DFP_FALSE@BUILD_FLAGS_DFP =
+@HAS_DFP_TRUE@BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6
+@HAS_DFP_FALSE@DFP_FLAG =
+@HAS_DFP_TRUE@DFP_FLAG = -DHAS_DFP
+test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
+ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \
+ @FLAG_M64@ $(ALTIVEC_FLAG)
+
+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/ppc64/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/ppc64/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+jm-insns$(EXEEXT): $(jm_insns_OBJECTS) $(jm_insns_DEPENDENCIES)
+ @rm -f jm-insns$(EXEEXT)
+ $(jm_insns_LINK) $(jm_insns_OBJECTS) $(jm_insns_LDADD) $(LIBS)
+lsw$(EXEEXT): $(lsw_OBJECTS) $(lsw_DEPENDENCIES)
+ @rm -f lsw$(EXEEXT)
+ $(LINK) $(lsw_OBJECTS) $(lsw_LDADD) $(LIBS)
+power6_bcmp$(EXEEXT): $(power6_bcmp_OBJECTS) $(power6_bcmp_DEPENDENCIES)
+ @rm -f power6_bcmp$(EXEEXT)
+ $(LINK) $(power6_bcmp_OBJECTS) $(power6_bcmp_LDADD) $(LIBS)
+power6_mf_gpr$(EXEEXT): $(power6_mf_gpr_OBJECTS) $(power6_mf_gpr_DEPENDENCIES)
+ @rm -f power6_mf_gpr$(EXEEXT)
+ $(LINK) $(power6_mf_gpr_OBJECTS) $(power6_mf_gpr_LDADD) $(LIBS)
+round$(EXEEXT): $(round_OBJECTS) $(round_DEPENDENCIES)
+ @rm -f round$(EXEEXT)
+ $(LINK) $(round_OBJECTS) $(round_LDADD) $(LIBS)
+std_reg_imm$(EXEEXT): $(std_reg_imm_OBJECTS) $(std_reg_imm_DEPENDENCIES)
+ @rm -f std_reg_imm$(EXEEXT)
+ $(LINK) $(std_reg_imm_OBJECTS) $(std_reg_imm_LDADD) $(LIBS)
+test_dfp1$(EXEEXT): $(test_dfp1_OBJECTS) $(test_dfp1_DEPENDENCIES)
+ @rm -f test_dfp1$(EXEEXT)
+ $(test_dfp1_LINK) $(test_dfp1_OBJECTS) $(test_dfp1_LDADD) $(LIBS)
+test_dfp2$(EXEEXT): $(test_dfp2_OBJECTS) $(test_dfp2_DEPENDENCIES)
+ @rm -f test_dfp2$(EXEEXT)
+ $(test_dfp2_LINK) $(test_dfp2_OBJECTS) $(test_dfp2_LDADD) $(LIBS)
+test_dfp3$(EXEEXT): $(test_dfp3_OBJECTS) $(test_dfp3_DEPENDENCIES)
+ @rm -f test_dfp3$(EXEEXT)
+ $(test_dfp3_LINK) $(test_dfp3_OBJECTS) $(test_dfp3_LDADD) $(LIBS)
+test_dfp4$(EXEEXT): $(test_dfp4_OBJECTS) $(test_dfp4_DEPENDENCIES)
+ @rm -f test_dfp4$(EXEEXT)
+ $(test_dfp4_LINK) $(test_dfp4_OBJECTS) $(test_dfp4_LDADD) $(LIBS)
+test_dfp5$(EXEEXT): $(test_dfp5_OBJECTS) $(test_dfp5_DEPENDENCIES)
+ @rm -f test_dfp5$(EXEEXT)
+ $(test_dfp5_LINK) $(test_dfp5_OBJECTS) $(test_dfp5_LDADD) $(LIBS)
+test_isa_2_06_part1$(EXEEXT): $(test_isa_2_06_part1_OBJECTS) $(test_isa_2_06_part1_DEPENDENCIES)
+ @rm -f test_isa_2_06_part1$(EXEEXT)
+ $(test_isa_2_06_part1_LINK) $(test_isa_2_06_part1_OBJECTS) $(test_isa_2_06_part1_LDADD) $(LIBS)
+test_isa_2_06_part2$(EXEEXT): $(test_isa_2_06_part2_OBJECTS) $(test_isa_2_06_part2_DEPENDENCIES)
+ @rm -f test_isa_2_06_part2$(EXEEXT)
+ $(test_isa_2_06_part2_LINK) $(test_isa_2_06_part2_OBJECTS) $(test_isa_2_06_part2_LDADD) $(LIBS)
+test_isa_2_06_part3$(EXEEXT): $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_DEPENDENCIES)
+ @rm -f test_isa_2_06_part3$(EXEEXT)
+ $(test_isa_2_06_part3_LINK) $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_LDADD) $(LIBS)
+tw_td$(EXEEXT): $(tw_td_OBJECTS) $(tw_td_DEPENDENCIES)
+ @rm -f tw_td$(EXEEXT)
+ $(LINK) $(tw_td_OBJECTS) $(tw_td_LDADD) $(LIBS)
+twi_tdi$(EXEEXT): $(twi_tdi_OBJECTS) $(twi_tdi_DEPENDENCIES)
+ @rm -f twi_tdi$(EXEEXT)
+ $(LINK) $(twi_tdi_OBJECTS) $(twi_tdi_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jm_insns-jm-insns.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lsw.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/power6_bcmp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/power6_mf_gpr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/round.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/std_reg_imm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp1-test_dfp1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp2-test_dfp2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp3-test_dfp3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp4-test_dfp4.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_dfp5-test_dfp5.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tw_td.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/twi_tdi.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+allexec-allexec.o: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.o -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+
+allexec-allexec.obj: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.obj -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+
+jm_insns-jm-insns.o: jm-insns.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(jm_insns_CFLAGS) $(CFLAGS) -MT jm_insns-jm-insns.o -MD -MP -MF $(DEPDIR)/jm_insns-jm-insns.Tpo -c -o jm_insns-jm-insns.o `test -f 'jm-insns.c' || echo '$(srcdir)/'`jm-insns.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/jm_insns-jm-insns.Tpo $(DEPDIR)/jm_insns-jm-insns.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='jm-insns.c' object='jm_insns-jm-insns.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(jm_insns_CFLAGS) $(CFLAGS) -c -o jm_insns-jm-insns.o `test -f 'jm-insns.c' || echo '$(srcdir)/'`jm-insns.c
+
+jm_insns-jm-insns.obj: jm-insns.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(jm_insns_CFLAGS) $(CFLAGS) -MT jm_insns-jm-insns.obj -MD -MP -MF $(DEPDIR)/jm_insns-jm-insns.Tpo -c -o jm_insns-jm-insns.obj `if test -f 'jm-insns.c'; then $(CYGPATH_W) 'jm-insns.c'; else $(CYGPATH_W) '$(srcdir)/jm-insns.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/jm_insns-jm-insns.Tpo $(DEPDIR)/jm_insns-jm-insns.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='jm-insns.c' object='jm_insns-jm-insns.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(jm_insns_CFLAGS) $(CFLAGS) -c -o jm_insns-jm-insns.obj `if test -f 'jm-insns.c'; then $(CYGPATH_W) 'jm-insns.c'; else $(CYGPATH_W) '$(srcdir)/jm-insns.c'; fi`
+
+test_dfp1-test_dfp1.o: test_dfp1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp1_CFLAGS) $(CFLAGS) -MT test_dfp1-test_dfp1.o -MD -MP -MF $(DEPDIR)/test_dfp1-test_dfp1.Tpo -c -o test_dfp1-test_dfp1.o `test -f 'test_dfp1.c' || echo '$(srcdir)/'`test_dfp1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp1-test_dfp1.Tpo $(DEPDIR)/test_dfp1-test_dfp1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp1.c' object='test_dfp1-test_dfp1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp1_CFLAGS) $(CFLAGS) -c -o test_dfp1-test_dfp1.o `test -f 'test_dfp1.c' || echo '$(srcdir)/'`test_dfp1.c
+
+test_dfp1-test_dfp1.obj: test_dfp1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp1_CFLAGS) $(CFLAGS) -MT test_dfp1-test_dfp1.obj -MD -MP -MF $(DEPDIR)/test_dfp1-test_dfp1.Tpo -c -o test_dfp1-test_dfp1.obj `if test -f 'test_dfp1.c'; then $(CYGPATH_W) 'test_dfp1.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp1-test_dfp1.Tpo $(DEPDIR)/test_dfp1-test_dfp1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp1.c' object='test_dfp1-test_dfp1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp1_CFLAGS) $(CFLAGS) -c -o test_dfp1-test_dfp1.obj `if test -f 'test_dfp1.c'; then $(CYGPATH_W) 'test_dfp1.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp1.c'; fi`
+
+test_dfp2-test_dfp2.o: test_dfp2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp2_CFLAGS) $(CFLAGS) -MT test_dfp2-test_dfp2.o -MD -MP -MF $(DEPDIR)/test_dfp2-test_dfp2.Tpo -c -o test_dfp2-test_dfp2.o `test -f 'test_dfp2.c' || echo '$(srcdir)/'`test_dfp2.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp2-test_dfp2.Tpo $(DEPDIR)/test_dfp2-test_dfp2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp2.c' object='test_dfp2-test_dfp2.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp2_CFLAGS) $(CFLAGS) -c -o test_dfp2-test_dfp2.o `test -f 'test_dfp2.c' || echo '$(srcdir)/'`test_dfp2.c
+
+test_dfp2-test_dfp2.obj: test_dfp2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp2_CFLAGS) $(CFLAGS) -MT test_dfp2-test_dfp2.obj -MD -MP -MF $(DEPDIR)/test_dfp2-test_dfp2.Tpo -c -o test_dfp2-test_dfp2.obj `if test -f 'test_dfp2.c'; then $(CYGPATH_W) 'test_dfp2.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp2.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp2-test_dfp2.Tpo $(DEPDIR)/test_dfp2-test_dfp2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp2.c' object='test_dfp2-test_dfp2.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp2_CFLAGS) $(CFLAGS) -c -o test_dfp2-test_dfp2.obj `if test -f 'test_dfp2.c'; then $(CYGPATH_W) 'test_dfp2.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp2.c'; fi`
+
+test_dfp3-test_dfp3.o: test_dfp3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp3_CFLAGS) $(CFLAGS) -MT test_dfp3-test_dfp3.o -MD -MP -MF $(DEPDIR)/test_dfp3-test_dfp3.Tpo -c -o test_dfp3-test_dfp3.o `test -f 'test_dfp3.c' || echo '$(srcdir)/'`test_dfp3.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp3-test_dfp3.Tpo $(DEPDIR)/test_dfp3-test_dfp3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp3.c' object='test_dfp3-test_dfp3.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp3_CFLAGS) $(CFLAGS) -c -o test_dfp3-test_dfp3.o `test -f 'test_dfp3.c' || echo '$(srcdir)/'`test_dfp3.c
+
+test_dfp3-test_dfp3.obj: test_dfp3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp3_CFLAGS) $(CFLAGS) -MT test_dfp3-test_dfp3.obj -MD -MP -MF $(DEPDIR)/test_dfp3-test_dfp3.Tpo -c -o test_dfp3-test_dfp3.obj `if test -f 'test_dfp3.c'; then $(CYGPATH_W) 'test_dfp3.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp3.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp3-test_dfp3.Tpo $(DEPDIR)/test_dfp3-test_dfp3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp3.c' object='test_dfp3-test_dfp3.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp3_CFLAGS) $(CFLAGS) -c -o test_dfp3-test_dfp3.obj `if test -f 'test_dfp3.c'; then $(CYGPATH_W) 'test_dfp3.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp3.c'; fi`
+
+test_dfp4-test_dfp4.o: test_dfp4.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp4_CFLAGS) $(CFLAGS) -MT test_dfp4-test_dfp4.o -MD -MP -MF $(DEPDIR)/test_dfp4-test_dfp4.Tpo -c -o test_dfp4-test_dfp4.o `test -f 'test_dfp4.c' || echo '$(srcdir)/'`test_dfp4.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp4-test_dfp4.Tpo $(DEPDIR)/test_dfp4-test_dfp4.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp4.c' object='test_dfp4-test_dfp4.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp4_CFLAGS) $(CFLAGS) -c -o test_dfp4-test_dfp4.o `test -f 'test_dfp4.c' || echo '$(srcdir)/'`test_dfp4.c
+
+test_dfp4-test_dfp4.obj: test_dfp4.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp4_CFLAGS) $(CFLAGS) -MT test_dfp4-test_dfp4.obj -MD -MP -MF $(DEPDIR)/test_dfp4-test_dfp4.Tpo -c -o test_dfp4-test_dfp4.obj `if test -f 'test_dfp4.c'; then $(CYGPATH_W) 'test_dfp4.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp4.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp4-test_dfp4.Tpo $(DEPDIR)/test_dfp4-test_dfp4.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp4.c' object='test_dfp4-test_dfp4.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp4_CFLAGS) $(CFLAGS) -c -o test_dfp4-test_dfp4.obj `if test -f 'test_dfp4.c'; then $(CYGPATH_W) 'test_dfp4.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp4.c'; fi`
+
+test_dfp5-test_dfp5.o: test_dfp5.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp5_CFLAGS) $(CFLAGS) -MT test_dfp5-test_dfp5.o -MD -MP -MF $(DEPDIR)/test_dfp5-test_dfp5.Tpo -c -o test_dfp5-test_dfp5.o `test -f 'test_dfp5.c' || echo '$(srcdir)/'`test_dfp5.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp5-test_dfp5.Tpo $(DEPDIR)/test_dfp5-test_dfp5.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp5.c' object='test_dfp5-test_dfp5.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp5_CFLAGS) $(CFLAGS) -c -o test_dfp5-test_dfp5.o `test -f 'test_dfp5.c' || echo '$(srcdir)/'`test_dfp5.c
+
+test_dfp5-test_dfp5.obj: test_dfp5.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp5_CFLAGS) $(CFLAGS) -MT test_dfp5-test_dfp5.obj -MD -MP -MF $(DEPDIR)/test_dfp5-test_dfp5.Tpo -c -o test_dfp5-test_dfp5.obj `if test -f 'test_dfp5.c'; then $(CYGPATH_W) 'test_dfp5.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp5.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_dfp5-test_dfp5.Tpo $(DEPDIR)/test_dfp5-test_dfp5.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_dfp5.c' object='test_dfp5-test_dfp5.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_dfp5_CFLAGS) $(CFLAGS) -c -o test_dfp5-test_dfp5.obj `if test -f 'test_dfp5.c'; then $(CYGPATH_W) 'test_dfp5.c'; else $(CYGPATH_W) '$(srcdir)/test_dfp5.c'; fi`
+
+test_isa_2_06_part1-test_isa_2_06_part1.o: test_isa_2_06_part1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part1_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part1-test_isa_2_06_part1.o -MD -MP -MF $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Tpo -c -o test_isa_2_06_part1-test_isa_2_06_part1.o `test -f 'test_isa_2_06_part1.c' || echo '$(srcdir)/'`test_isa_2_06_part1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Tpo $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part1.c' object='test_isa_2_06_part1-test_isa_2_06_part1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part1_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part1-test_isa_2_06_part1.o `test -f 'test_isa_2_06_part1.c' || echo '$(srcdir)/'`test_isa_2_06_part1.c
+
+test_isa_2_06_part1-test_isa_2_06_part1.obj: test_isa_2_06_part1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part1_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part1-test_isa_2_06_part1.obj -MD -MP -MF $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Tpo -c -o test_isa_2_06_part1-test_isa_2_06_part1.obj `if test -f 'test_isa_2_06_part1.c'; then $(CYGPATH_W) 'test_isa_2_06_part1.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Tpo $(DEPDIR)/test_isa_2_06_part1-test_isa_2_06_part1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part1.c' object='test_isa_2_06_part1-test_isa_2_06_part1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part1_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part1-test_isa_2_06_part1.obj `if test -f 'test_isa_2_06_part1.c'; then $(CYGPATH_W) 'test_isa_2_06_part1.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part1.c'; fi`
+
+test_isa_2_06_part2-test_isa_2_06_part2.o: test_isa_2_06_part2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part2_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part2-test_isa_2_06_part2.o -MD -MP -MF $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Tpo -c -o test_isa_2_06_part2-test_isa_2_06_part2.o `test -f 'test_isa_2_06_part2.c' || echo '$(srcdir)/'`test_isa_2_06_part2.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Tpo $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part2.c' object='test_isa_2_06_part2-test_isa_2_06_part2.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part2_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part2-test_isa_2_06_part2.o `test -f 'test_isa_2_06_part2.c' || echo '$(srcdir)/'`test_isa_2_06_part2.c
+
+test_isa_2_06_part2-test_isa_2_06_part2.obj: test_isa_2_06_part2.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part2_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part2-test_isa_2_06_part2.obj -MD -MP -MF $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Tpo -c -o test_isa_2_06_part2-test_isa_2_06_part2.obj `if test -f 'test_isa_2_06_part2.c'; then $(CYGPATH_W) 'test_isa_2_06_part2.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part2.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Tpo $(DEPDIR)/test_isa_2_06_part2-test_isa_2_06_part2.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part2.c' object='test_isa_2_06_part2-test_isa_2_06_part2.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part2_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part2-test_isa_2_06_part2.obj `if test -f 'test_isa_2_06_part2.c'; then $(CYGPATH_W) 'test_isa_2_06_part2.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part2.c'; fi`
+
+test_isa_2_06_part3-test_isa_2_06_part3.o: test_isa_2_06_part3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part3-test_isa_2_06_part3.o -MD -MP -MF $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Tpo -c -o test_isa_2_06_part3-test_isa_2_06_part3.o `test -f 'test_isa_2_06_part3.c' || echo '$(srcdir)/'`test_isa_2_06_part3.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Tpo $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part3.c' object='test_isa_2_06_part3-test_isa_2_06_part3.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part3-test_isa_2_06_part3.o `test -f 'test_isa_2_06_part3.c' || echo '$(srcdir)/'`test_isa_2_06_part3.c
+
+test_isa_2_06_part3-test_isa_2_06_part3.obj: test_isa_2_06_part3.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -MT test_isa_2_06_part3-test_isa_2_06_part3.obj -MD -MP -MF $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Tpo -c -o test_isa_2_06_part3-test_isa_2_06_part3.obj `if test -f 'test_isa_2_06_part3.c'; then $(CYGPATH_W) 'test_isa_2_06_part3.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part3.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Tpo $(DEPDIR)/test_isa_2_06_part3-test_isa_2_06_part3.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='test_isa_2_06_part3.c' object='test_isa_2_06_part3-test_isa_2_06_part3.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(test_isa_2_06_part3_CFLAGS) $(CFLAGS) -c -o test_isa_2_06_part3-test_isa_2_06_part3.obj `if test -f 'test_isa_2_06_part3.c'; then $(CYGPATH_W) 'test_isa_2_06_part3.c'; else $(CYGPATH_W) '$(srcdir)/test_isa_2_06_part3.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/ppc64/allexec.c b/main/none/tests/ppc64/allexec.c
new file mode 100644
index 0000000..b7177e8
--- /dev/null
+++ b/main/none/tests/ppc64/allexec.c
@@ -0,0 +1,50 @@
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+extern char **environ;
+
+#define S(...) (fprintf(stdout, __VA_ARGS__),fflush(stdout))
+#define FORKEXECWAIT(exec_call) do { \
+ int status;\
+ pid_t child = fork(); \
+ if (child == 0) {exec_call; perror ("exec failed");} \
+ else if (child == -1) perror ("cannot fork\n"); \
+ else if (child != wait (&status)) perror ("error waiting child"); \
+ else S("child exited\n"); \
+ } while (0)
+
+void test_allexec (char *exec)
+{
+ FORKEXECWAIT (execlp(exec, exec, NULL));
+ FORKEXECWAIT (execlp(exec, exec, "constant_arg1", "constant_arg2", NULL));
+ FORKEXECWAIT (execve(exec, NULL, environ));
+}
+
+
+/* If a single argument "exec" is given, will execute itself
+ (in bi-arch, a 32 bit and 64 bit variant) via various exec system calls.
+ Note that this test can only be run after the prerequisite have been
+ prepared by allexec_prepare_prereq, which will a.o. make links
+ for the allexec32 and allexec64 executables. On single arch build,
+ these links points to the same executable to ensure this test works
+ everywhere the same.
+ No arguments or more arguments means just print its args. */
+int main(int argc, char **argv, char **envp)
+{
+ if ( (argc == 2) && (strcmp (argv[1], "exec") == 0)) {
+ S("%s will exec ./allexec32\n", argv[0]);
+ test_allexec ("./allexec32");
+ S("%s will exec ./allexec64\n", argv[0]);
+ test_allexec ("./allexec64");
+ } else {
+ int i;
+ S("program exec-ed:");
+ for (i = 0; i < argc; i++) S(" %s", argv[i]);
+ S("\n");
+ }
+ return 0;
+}
diff --git a/main/none/tests/ppc64/jm-fp.stdout.exp b/main/none/tests/ppc64/jm-fp.stdout.exp
index adbdabf..00bd727 100644
--- a/main/none/tests/ppc64/jm-fp.stdout.exp
+++ b/main/none/tests/ppc64/jm-fp.stdout.exp
@@ -719,8 +719,8 @@
frsqrte 8000000000000000 => fff0000000000000
frsqrte 7ff0000000000000 => 0000000000000000
frsqrte fff0000000000000 => 7ff8000000000000
- frsqrte 7ff7ffffffffffff => 7fff800000000000
- frsqrte fff7ffffffffffff => ffff800000000000
+ frsqrte 7ff7ffffffffffff => 7fff000000000000
+ frsqrte fff7ffffffffffff => ffff000000000000
frsqrte 7ff8000000000000 => 7ff8000000000000
frsqrte fff8000000000000 => fff8000000000000
@@ -942,8 +942,8 @@
frsqrte. 8000000000000000 => fff0000000000000
frsqrte. 7ff0000000000000 => 0000000000000000
frsqrte. fff0000000000000 => 7ff8000000000000
- frsqrte. 7ff7ffffffffffff => 7fff800000000000
- frsqrte. fff7ffffffffffff => ffff800000000000
+ frsqrte. 7ff7ffffffffffff => 7fff000000000000
+ frsqrte. fff7ffffffffffff => ffff000000000000
frsqrte. 7ff8000000000000 => 7ff8000000000000
frsqrte. fff8000000000000 => fff8000000000000
diff --git a/main/none/tests/ppc64/jm-int.stdout.exp b/main/none/tests/ppc64/jm-int.stdout.exp
index dec9370..4dba79b 100644
--- a/main/none/tests/ppc64/jm-int.stdout.exp
+++ b/main/none/tests/ppc64/jm-int.stdout.exp
@@ -4705,4 +4705,9 @@
stdux 0000001cbe991def, 8 => 0000001cbe991def, 8 (00000000 00000000)
stdux ffffffffffffffff, 16 => ffffffffffffffff, 16 (00000000 00000000)
-All done. Tested 203 different instructions
+PPC integer population count with one register args, no flags:
+ popcntb 0000000000000000 => 0000000000000000 (00000000 00000000)
+ popcntb 0000001cbe991def => 0000000306040407 (00000000 00000000)
+ popcntb ffffffffffffffff => 0808080808080808 (00000000 00000000)
+
+All done. Tested 204 different instructions
diff --git a/main/none/tests/ppc64/jm-vmx.stdout.exp b/main/none/tests/ppc64/jm-vmx.stdout.exp
index 0a0bb3e..3e19e63 100644
--- a/main/none/tests/ppc64/jm-vmx.stdout.exp
+++ b/main/none/tests/ppc64/jm-vmx.stdout.exp
@@ -1517,7 +1517,6 @@
stvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
stvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
-Altivec floating point arith insns with three args:
Altivec floating point arith insns with two args:
vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
vaddfp: => 033fffff 033fffff 033fffff 033fffff (00000000)
@@ -1907,6 +1906,585 @@
vminfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+Altivec floating point arith insns with three args:
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+
Altivec floating point arith insns with one arg:
vrfin: 02bfffff 02bfffff 02bfffff 02bfffff
vrfin: => 00000000 00000000 00000000 00000000 (00000000)
@@ -2009,13 +2587,13 @@
vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
vrefp: 02bfffff 02bfffff 02bfffff 02bfffff
- vrefp: => 7c2aa900 7c2aa900 7c2aa900 7c2aa900 (00000000)
+ vrefp: => 7c2a8000 7c2a8000 7c2a8000 7c2a8000 (00000000)
vrefp: 513fffff 513fffff 513fffff 513fffff
- vrefp: => 2daaa900 2daaa900 2daaa900 2daaa900 (00000000)
+ vrefp: => 2daa8000 2daa8000 2daa8000 2daa8000 (00000000)
vrefp: 82bfffff 82bfffff 82bfffff 82bfffff
- vrefp: => fc2aa900 fc2aa900 fc2aa900 fc2aa900 (00000000)
+ vrefp: => fc2a8000 fc2a8000 fc2a8000 fc2a8000 (00000000)
vrefp: d13fffff d13fffff d13fffff d13fffff
- vrefp: => adaaa900 adaaa900 adaaa900 adaaa900 (00000000)
+ vrefp: => adaa8000 adaa8000 adaa8000 adaa8000 (00000000)
vrefp: 00000000 00000000 00000000 00000000
vrefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
vrefp: 80000000 80000000 80000000 80000000
@@ -2025,18 +2603,18 @@
vrefp: ff800000 ff800000 ff800000 ff800000
vrefp: => 80000000 80000000 80000000 80000000 (00000000)
vrefp: 7fffffff 7fffffff 7fffffff 7fffffff
- vrefp: => 7fffff00 7fffff00 7fffff00 7fffff00 (00000000)
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
vrefp: ffffffff ffffffff ffffffff ffffffff
- vrefp: => ffffff00 ffffff00 ffffff00 ffffff00 (00000000)
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
vrefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
- vrefp: => 7fffff00 7fffff00 7fffff00 7fffff00 (00000000)
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
vrefp: ffbfffff ffbfffff ffbfffff ffbfffff
- vrefp: => ffffff00 ffffff00 ffffff00 ffffff00 (00000000)
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
vrsqrtefp: 02bfffff 02bfffff 02bfffff 02bfffff
- vrsqrtefp: => 5dd10300 5dd10300 5dd10300 5dd10300 (00000000)
+ vrsqrtefp: => 5dd10000 5dd10000 5dd10000 5dd10000 (00000000)
vrsqrtefp: 513fffff 513fffff 513fffff 513fffff
- vrsqrtefp: => 3693ca00 3693ca00 3693ca00 3693ca00 (00000000)
+ vrsqrtefp: => 3693c000 3693c000 3693c000 3693c000 (00000000)
vrsqrtefp: 82bfffff 82bfffff 82bfffff 82bfffff
vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
vrsqrtefp: d13fffff d13fffff d13fffff d13fffff
@@ -2050,13 +2628,13 @@
vrsqrtefp: ff800000 ff800000 ff800000 ff800000
vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
vrsqrtefp: 7fffffff 7fffffff 7fffffff 7fffffff
- vrsqrtefp: => 7fffff00 7fffff00 7fffff00 7fffff00 (00000000)
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
vrsqrtefp: ffffffff ffffffff ffffffff ffffffff
- vrsqrtefp: => ffffff00 ffffff00 ffffff00 ffffff00 (00000000)
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
vrsqrtefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
- vrsqrtefp: => 7fffff00 7fffff00 7fffff00 7fffff00 (00000000)
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff
- vrsqrtefp: => ffffff00 ffffff00 ffffff00 ffffff00 (00000000)
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
Altivec floating point compare insns:
vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
@@ -3033,4 +3611,4 @@
vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
-All done. Tested 163 different instructions
+All done. Tested 165 different instructions
diff --git a/main/none/tests/ppc64/jm-vmx.stdout.exp_Minus_nan b/main/none/tests/ppc64/jm-vmx.stdout.exp_Minus_nan
new file mode 100644
index 0000000..c3360e3
--- /dev/null
+++ b/main/none/tests/ppc64/jm-vmx.stdout.exp_Minus_nan
@@ -0,0 +1,3614 @@
+PPC altivec integer arith insns with three args:
+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmhaddshs: => 010403160538076a09ad0c000f970f9a (00000000)
+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhaddshs: => f1f4f406f628f85afa9dfcf00087008a (00000000)
+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000)
+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000)
+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000)
+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000)
+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmhaddshs: => 028d042605cf078909520b2c0e0f0e11 (00000000)
+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhaddshs: => f37df516f6bff879fa42fc1cfeffff01 (00000000)
+
+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmhraddshs: => 010403160538076b09ad0c000f980f9a (00000000)
+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhraddshs: => f1f4f406f628f85bfa9dfcf00088008a (00000000)
+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000)
+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000)
+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000)
+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000)
+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmhraddshs: => 028d042605d0078909530b2c0e0f0e11 (00000000)
+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmhraddshs: => f37df516f6c0f879fa43fc1cfeffff01 (00000000)
+
+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmladduhm: => 05061b14412a7748bd6e139c7ab6b2f0 (00000000)
+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmladduhm: => f5f60c04321a6838ae5e048c6ba6a3e0 (00000000)
+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000)
+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000)
+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000)
+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000)
+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmladduhm: => 89c62394cd6a8748512e2b1c14161010 (00000000)
+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmladduhm: => 7ab61484be5a7838421e1c0c05060100 (00000000)
+
+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumubm: => 01020322050607b6090a0cca0e0d1121 (00000000)
+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumubm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000)
+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000)
+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000)
+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumubm: => 010599e20509bc76090ddf8a0e10fe21 (00000000)
+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumubm: => f1f68ad2f5faad66f9fed07aff01ef11 (00000000)
+
+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhm: => 010c1f180550b36c09d5c8000f981f99 (00000000)
+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhm: => f1fd1008f641a45cfac6b8f000891089 (00000000)
+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000)
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000)
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhm: => ce24ac58e1874facf52a73400a071619 (00000000)
+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhm: => bf159d48d278409ce61b6430faf80709 (00000000)
+
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshs: => 010c1f180550b36c09d5c8000f981f99 (00000000)
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshs: => f1fd1008f641a45cfac6b8f000891089 (00000000)
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshs: => 0258ac5805ab4fac093e73400e0f1619 (00000000)
+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshs: => f3499d48f69c409cfa2f6430ff000709 (00000000)
+
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhs: => 010c1f180550b36c09d5c8000f981f99 (00000000)
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhs: => f1fd1008f641a45cfac6b8f0ffffffff (00000000)
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000)
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000)
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000)
+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000)
+
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsummbm: => 01020322050607b6090a0cca0e0d1121 (00000000)
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsummbm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000)
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsummbm: => 01020c8205062016090a342a0e0d45a1 (00000000)
+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsummbm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsummbm: => 0102028205060616090a0a2a0e0d0da1 (00000000)
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsummbm: => f1f2f372f5f6f706f9fafb1afefdfe91 (00000000)
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsummbm: => 0101cfe20505e2760909f58a0e0d0621 (00000000)
+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsummbm: => f1f2c0d2f5f6d366f9fae67afefdf711 (00000000)
+
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshm: => 010c1f180550b36c09d5c8000f981f99 (00000000)
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshm: => f1fd1008f641a45cfac6b8f000891089 (00000000)
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmsumshm: => 0258ac5805ab4fac093e73400e0f1619 (00000000)
+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmsumshm: => f3499d48f69c409cfa2f6430ff000709 (00000000)
+
+PPC altivec integer logical insns with three args:
+ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000)
+ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000)
+ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000)
+ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000)
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000)
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vperm: => 02030405060708090a0b0c0e0e0d0e0f (00000000)
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000)
+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vperm: => f2f3f4f5f6f7f8f9fafbfcfefefdfeff (00000000)
+
+ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
+ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
+ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
+ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
+
+PPC altivec integer arith insns with two args:
+ vaddubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddubm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
+ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
+ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddubm: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000)
+
+ vadduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vadduhm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vadduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
+ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
+ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduhm: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000)
+
+ vadduwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vadduwm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vadduwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
+ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
+ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduwm: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000)
+
+ vaddubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddubs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000)
+ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000)
+ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddubs: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vadduhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vadduhs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vadduhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
+ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
+ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduhs: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vadduws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vadduws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vadduws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
+ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
+ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vadduws: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddsbs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
+ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
+ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddsbs: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000)
+
+ vaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddshs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
+ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
+ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddshs: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000)
+
+ vaddsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddsws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vaddsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
+ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
+ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddsws: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000)
+
+ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vaddcuw: => 00000000 00000000 00000000 00000000 (00000000)
+ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000)
+ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000)
+ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vaddcuw: => 00000001 00000001 00000001 00000001 (00000000)
+
+ vsububm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsububm: => 00000000 00000000 00000000 00000000 (00000000)
+ vsububm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsububm: => 10101010 10101010 10101010 10101010 (00000000)
+ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsububm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsububm: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuhm: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000)
+ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubuhm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuwm: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000)
+ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubuwm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsububs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsububs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsububs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubuhs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubuws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubuws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubsbs: => 10101010 10101010 10101010 10101010 (00000000)
+ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubsbs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubshs: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubshs: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000)
+ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubshs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubshs: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubsws: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubsws: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000)
+ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubsws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubsws: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
+ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubcuw: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
+ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
+
+ vmuloub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmuloub: => 00040010 00240040 00640090 00a900e1 (00000000)
+ vmuloub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000)
+ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000)
+ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuloub: => e4c4e890 ec64f040 f424f810 fa09fe01 (00000000)
+
+ vmulouh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulouh: => 00091810 00317040 007a0890 00c5a4e1 (00000000)
+ vmulouh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000)
+ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000)
+ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulouh: => e8792090 f0308040 f8082010 fdff0201 (00000000)
+
+ vmulosb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulosb: => 00040010 00240040 00640090 00a900e1 (00000000)
+ vmulosb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000)
+ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000)
+ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulosb: => 00c40090 00640040 00240010 00090001 (00000000)
+
+ vmulosh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulosh: => 00091810 00317040 007a0890 00c5a4e1 (00000000)
+ vmulosh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000)
+ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000)
+ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulosh: => 00912090 00408040 00102010 00010201 (00000000)
+
+ vmuleub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmuleub: => 00010009 00190031 00510079 00c400c4 (00000000)
+ vmuleub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000)
+ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000)
+ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuleub: => e2e1e6a9 ea79ee51 f231f619 fc04fc04 (00000000)
+
+ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmuleuh: => 00010404 00193c24 0051b464 00c56ca9 (00000000)
+ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000)
+ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000)
+ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmuleuh: => e4a988c4 ec50c864 f4184824 fdfb0609 (00000000)
+
+ vmulesb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulesb: => 00010009 00190031 00510079 00c400c4 (00000000)
+ vmulesb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000)
+ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000)
+ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulesb: => 00e100a9 00790051 00310019 00040004 (00000000)
+
+ vmulesh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmulesh: => 00010404 00193c24 0051b464 00c56ca9 (00000000)
+ vmulesh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000)
+ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000)
+ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmulesh: => 00c588c4 0064c864 00244824 00010609 (00000000)
+
+ vsumsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsumsws: => 00000000 00000000 00000000 2b2c3136 (00000000)
+ vsumsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsumsws: => 00000000 00000000 00000000 1c1d2226 (00000000)
+ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsumsws: => 00000000 00000000 00000000 eeeff4f6 (00000000)
+ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsumsws: => 00000000 00000000 00000000 dfe0e5e6 (00000000)
+
+ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsum2sws: => 00000000 0b0e1114 00000000 2524272a (00000000)
+ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum2sws: => 00000000 fbff0204 00000000 1615181a (00000000)
+ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsum2sws: => 00000000 eceff2f4 00000000 0706090a (00000000)
+ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum2sws: => 00000000 dde0e3e4 00000000 f7f6f9fa (00000000)
+
+ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsum4ubs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000)
+ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4ubs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000)
+ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsum4ubs: => 010206ce 05060ae2 090a0ef6 0e0d1207 (00000000)
+ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4ubs: => f1f2f7be f5f6fbd2 f9faffe6 fefe02f7 (00000000)
+
+ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsum4sbs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000)
+ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4sbs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000)
+ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsum4sbs: => 010202ce 050606e2 090a0af6 0e0d0e07 (00000000)
+ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4sbs: => f1f2f3be f5f6f7d2 f9fafbe6 fefdfef7 (00000000)
+
+ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsum4shs: => 0102070a 05061316 090a1f22 0e0d2a2b (00000000)
+ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4shs: => f1f2f7fa f5f70406 f9fb1012 fefe1b1b (00000000)
+ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsum4shs: => 0101e8ea 0505f4f6 090a0102 0e0d0c0b (00000000)
+ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsum4shs: => f1f2d9da f5f6e5e6 f9faf1f2 fefdfcfb (00000000)
+
+ vavgub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavgub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavgub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavguh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavguh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavguh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavguh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavguw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavguw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavguw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
+ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavguw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavgsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavgsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavgsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000)
+ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000)
+ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavgsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavgsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavgsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000)
+ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000)
+ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vavgsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vavgsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vavgsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000)
+ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000)
+ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vavgsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmaxsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vminsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vminsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vminsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+PPC altivec integer logical insns with two args:
+ vand: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vand: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vand: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vor: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ vxor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vxor: => 00000000 00000000 00000000 00000000 (00000000)
+ vxor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vxor: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vandc: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vandc: => 00000000 00000000 00000000 00000000 (00000000)
+ vandc: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vandc: => 00000000 00000000 00000000 00000000 (00000000)
+ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vandc: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vandc: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vnor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vnor: => fefdfcfb faf9f8f7 f6f5f4f3 f1f2f1f0 (00000000)
+ vnor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
+ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
+ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
+
+ vrlb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000)
+ vrlb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000)
+ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000)
+ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000)
+
+ vrlh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000)
+ vrlh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000)
+ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000)
+ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000)
+
+ vrlw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vrlw: => 10203040 06070805 a0b0c090 87078706 (00000000)
+ vrlw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlw: => 30401020 08050607 c090a0b0 87068707 (00000000)
+ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vrlw: => 1f2f3f4f f6f7f8f5 afbfcf9f ff7fff7e (00000000)
+ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vrlw: => 3f4f1f2f f8f5f6f7 cf9fafbf ff7eff7f (00000000)
+
+ vslb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000)
+ vslb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000)
+ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000)
+ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000)
+
+ vslh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vslh: => 04083040 41800800 2800c000 a0008000 (00000000)
+ vslh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslh: => 04083040 41800800 2800c000 a0008000 (00000000)
+ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000)
+ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000)
+
+ vslw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vslw: => 10203040 06070800 a0b0c000 87078000 (00000000)
+ vslw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslw: => 30400000 08000000 c0000000 80000000 (00000000)
+ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vslw: => 1f2f3f40 f6f7f800 afbfc000 ff7f8000 (00000000)
+ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslw: => 3f400000 f8000000 c0000000 80000000 (00000000)
+
+ vsrb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrb: => 00000000 00000008 04020100 00000000 (00000000)
+ vsrb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrb: => 00000000 00000008 04020100 00000000 (00000000)
+ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000)
+ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000)
+
+ vsrh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrh: => 00400030 00140007 00020000 00000000 (00000000)
+ vsrh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrh: => 00400030 00140007 00020000 00000000 (00000000)
+ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000)
+ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000)
+
+ vsrw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrw: => 00102030 00050607 000090a0 00001c1a (00000000)
+ vsrw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrw: => 00000010 00000005 00000000 00000000 (00000000)
+ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrw: => 0f1f2f3f 00f5f6f7 000f9faf 0001fdfb (00000000)
+ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrw: => 00000f1f 000000f5 0000000f 00000001 (00000000)
+
+ vsrab: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrab: => 00000000 00000008 04020100 00000000 (00000000)
+ vsrab: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrab: => 00000000 00000008 04020100 00000000 (00000000)
+ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000)
+ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000)
+
+ vsrah: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsrah: => 00400030 00140007 00020000 00000000 (00000000)
+ vsrah: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrah: => 00400030 00140007 00020000 00000000 (00000000)
+ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000)
+ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000)
+
+ vsraw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsraw: => 00102030 00050607 000090a0 00001c1a (00000000)
+ vsraw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsraw: => 00000010 00000005 00000000 00000000 (00000000)
+ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsraw: => ff1f2f3f fff5f6f7 ffff9faf fffffdfb (00000000)
+ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsraw: => ffffff1f fffffff5 ffffffff ffffffff (00000000)
+
+ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkuhum: => 02040608 0a0c0d0f 02040608 0a0c0d0f (00000000)
+ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuhum: => 02040608 0a0c0d0f f2f4f6f8 fafcfdff (00000000)
+ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkuhum: => f2f4f6f8 fafcfdff 02040608 0a0c0d0f (00000000)
+ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuhum: => f2f4f6f8 fafcfdff f2f4f6f8 fafcfdff (00000000)
+
+ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkuwum: => 03040708 0b0c0e0f 03040708 0b0c0e0f (00000000)
+ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuwum: => 03040708 0b0c0e0f f3f4f7f8 fbfcfeff (00000000)
+ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkuwum: => f3f4f7f8 fbfcfeff 03040708 0b0c0e0f (00000000)
+ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuwum: => f3f4f7f8 fbfcfeff f3f4f7f8 fbfcfeff (00000000)
+
+ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vpkshus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkshus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkshus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkshus: => ffffffff ffffffff 00000000 00000000 (00000000)
+ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkshus: => 00000000 00000000 ffffffff ffffffff (00000000)
+ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkshus: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vpkswus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkswus: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vpkswus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkswus: => ffffffff ffffffff 00000000 00000000 (00000000)
+ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkswus: => 00000000 00000000 ffffffff ffffffff (00000000)
+ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkswus: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vpkshss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkshss: => 7f7f7f7f 7f7f7f7f 7f7f7f7f 7f7f7f7f (00000000)
+ vpkshss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkshss: => 7f7f7f7f 7f7f7f7f 80808080 80808080 (00000000)
+ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkshss: => 80808080 80808080 7f7f7f7f 7f7f7f7f (00000000)
+ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkshss: => 80808080 80808080 80808080 80808080 (00000000)
+
+ vpkswss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkswss: => 7fff7fff 7fff7fff 7fff7fff 7fff7fff (00000000)
+ vpkswss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkswss: => 7fff7fff 7fff7fff 80008000 80008000 (00000000)
+ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkswss: => 80008000 80008000 7fff7fff 7fff7fff (00000000)
+ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkswss: => 80008000 80008000 80008000 80008000 (00000000)
+
+ vpkpx: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vpkpx: => 80008001 84210421 80008001 84210421 (00000000)
+ vpkpx: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkpx: => 80008001 84210421 fbdefbdf ffff7fff (00000000)
+ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vpkpx: => fbdefbdf ffff7fff 80008001 84210421 (00000000)
+ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vpkpx: => fbdefbdf ffff7fff fbdefbdf ffff7fff (00000000)
+
+ vmrghb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrghb: => 01010202 03030404 05050606 07070808 (00000000)
+ vmrghb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghb: => 01f102f2 03f304f4 05f506f6 07f708f8 (00000000)
+ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrghb: => f101f202 f303f404 f505f606 f707f808 (00000000)
+ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghb: => f1f1f2f2 f3f3f4f4 f5f5f6f6 f7f7f8f8 (00000000)
+
+ vmrghh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrghh: => 01020102 03040304 05060506 07080708 (00000000)
+ vmrghh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghh: => 0102f1f2 0304f3f4 0506f5f6 0708f7f8 (00000000)
+ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrghh: => f1f20102 f3f40304 f5f60506 f7f80708 (00000000)
+ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghh: => f1f2f1f2 f3f4f3f4 f5f6f5f6 f7f8f7f8 (00000000)
+
+ vmrghw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrghw: => 01020304 01020304 05060708 05060708 (00000000)
+ vmrghw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghw: => 01020304 f1f2f3f4 05060708 f5f6f7f8 (00000000)
+ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrghw: => f1f2f3f4 01020304 f5f6f7f8 05060708 (00000000)
+ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrghw: => f1f2f3f4 f1f2f3f4 f5f6f7f8 f5f6f7f8 (00000000)
+
+ vmrglb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrglb: => 09090a0a 0b0b0c0c 0e0e0d0d 0e0e0f0f (00000000)
+ vmrglb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglb: => 09f90afa 0bfb0cfc 0efe0dfd 0efe0fff (00000000)
+ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrglb: => f909fa0a fb0bfc0c fe0efd0d fe0eff0f (00000000)
+ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglb: => f9f9fafa fbfbfcfc fefefdfd fefeffff (00000000)
+
+ vmrglh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrglh: => 090a090a 0b0c0b0c 0e0d0e0d 0e0f0e0f (00000000)
+ vmrglh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglh: => 090af9fa 0b0cfbfc 0e0dfefd 0e0ffeff (00000000)
+ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrglh: => f9fa090a fbfc0b0c fefd0e0d feff0e0f (00000000)
+ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglh: => f9faf9fa fbfcfbfc fefdfefd fefffeff (00000000)
+
+ vmrglw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vmrglw: => 090a0b0c 090a0b0c 0e0d0e0f 0e0d0e0f (00000000)
+ vmrglw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglw: => 090a0b0c f9fafbfc 0e0d0e0f fefdfeff (00000000)
+ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vmrglw: => f9fafbfc 090a0b0c fefdfeff 0e0d0e0f (00000000)
+ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vmrglw: => f9fafbfc f9fafbfc fefdfeff fefdfeff (00000000)
+
+ vslo: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vslo: => 02030405 06070809 0a0b0c0e 0d0e0f00 (00000000)
+ vslo: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslo: => 0f000000 00000000 00000000 00000000 (00000000)
+ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vslo: => f2f3f4f5 f6f7f8f9 fafbfcfe fdfeff00 (00000000)
+ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vslo: => ff000000 00000000 00000000 00000000 (00000000)
+
+ vsro: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vsro: => 00010203 04050607 08090a0b 0c0e0d0e (00000000)
+ vsro: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsro: => 00000000 00000000 00000000 00000001 (00000000)
+ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vsro: => 00f1f2f3 f4f5f6f7 f8f9fafb fcfefdfe (00000000)
+ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vsro: => 00000000 00000000 00000000 000000f1 (00000000)
+
+PPC altivec integer logical insns with one arg:
+ vupkhsb: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupkhsb: => 00010002 00030004 00050006 00070008 (00000000)
+ vupkhsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupkhsb: => fff1fff2 fff3fff4 fff5fff6 fff7fff8 (00000000)
+
+ vupkhsh: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupkhsh: => 00000102 00000304 00000506 00000708 (00000000)
+ vupkhsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupkhsh: => fffff1f2 fffff3f4 fffff5f6 fffff7f8 (00000000)
+
+ vupkhpx: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupkhpx: => 00000802 00001804 00010806 00011808 (00000000)
+ vupkhpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupkhpx: => ff1c0f12 ff1c1f14 ff1d0f16 ff1d1f18 (00000000)
+
+ vupklsb: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupklsb: => 0009000a 000b000c 000e000d 000e000f (00000000)
+ vupklsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupklsb: => fff9fffa fffbfffc fffefffd fffeffff (00000000)
+
+ vupklsh: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupklsh: => 0000090a 00000b0c 00000e0d 00000e0f (00000000)
+ vupklsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupklsh: => fffff9fa fffffbfc fffffefd fffffeff (00000000)
+
+ vupklpx: 01020304 05060708 090a0b0c 0e0d0e0f
+ vupklpx: => 0002080a 0002180c 0003100d 0003100f (00000000)
+ vupklpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
+ vupklpx: => ff1e0f1a ff1e1f1c ff1f171d ff1f171f (00000000)
+
+Altivec integer compare insns:
+ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtub: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuh: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuw: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsb: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsh: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsw: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+Altivec integer compare insns with flags update:
+ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtub.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtuw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+
+ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+
+ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
+ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
+ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+
+Altivec integer special insns:
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000
+ vsl: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101
+ vsl: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202
+ vsl: => 04080c10 14181c20 24282c30 3834383c (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303
+ vsl: => 08101820 28303840 48505860 70687078 (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404
+ vsl: => 10203040 50607080 90a0b0c0 e0d0e0f0 (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505
+ vsl: => 20406080 a0c0e101 21416181 c1a1c1e0 (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606
+ vsl: => 4080c101 4181c202 4282c303 834383c0 (00000000)
+ vsl: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707
+ vsl: => 81018202 83038404 85058607 06870780 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000
+ vsl: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101
+ vsl: => e3e5e7e9 ebedeff1 f3f5f7f9 fdfbfdfe (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202
+ vsl: => c7cbcfd3 d7dbdfe3 e7ebeff3 fbf7fbfc (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303
+ vsl: => 8f979fa7 afb7bfc7 cfd7dfe7 f7eff7f8 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404
+ vsl: => 1f2f3f4f 5f6f7f8f 9fafbfcf efdfeff0 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505
+ vsl: => 3e5e7e9e bedeff1f 3f5f7f9f dfbfdfe0 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606
+ vsl: => 7cbcfd3d 7dbdfe3e 7ebeff3f bf7fbfc0 (00000000)
+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707
+ vsl: => f979fa7a fb7bfc7c fd7dfe7f 7eff7f80 (00000000)
+
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000
+ vsr: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101
+ vsr: => 00810182 02830384 04850586 07068707 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202
+ vsr: => 004080c1 014181c2 024282c3 03834383 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303
+ vsr: => 00204060 80a0c0e1 01214161 81c1a1c1 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404
+ vsr: => 00102030 40506070 8090a0b0 c0e0d0e0 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505
+ vsr: => 00081018 20283038 40485058 60706870 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606
+ vsr: => 0004080c 1014181c 2024282c 30383438 (00000000)
+ vsr: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707
+ vsr: => 00020406 080a0c0e 10121416 181c1a1c (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000
+ vsr: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101
+ vsr: => 78f979fa 7afb7bfc 7cfd7dfe 7f7eff7f (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202
+ vsr: => 3c7cbcfd 3d7dbdfe 3e7ebeff 3fbf7fbf (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303
+ vsr: => 1e3e5e7e 9ebedeff 1f3f5f7f 9fdfbfdf (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404
+ vsr: => 0f1f2f3f 4f5f6f7f 8f9fafbf cfefdfef (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505
+ vsr: => 078f979f a7afb7bf c7cfd7df e7f7eff7 (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606
+ vsr: => 03c7cbcf d3d7dbdf e3e7ebef f3fbf7fb (00000000)
+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707
+ vsr: => 01e3e5e7 e9ebedef f1f3f5f7 f9fdfbfd (00000000)
+
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 0
+ vspltb: => 01010101 01010101 01010101 01010101 (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 3
+ vspltb: => 04040404 04040404 04040404 04040404 (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 6
+ vspltb: => 07070707 07070707 07070707 07070707 (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 9
+ vspltb: => 0a0a0a0a 0a0a0a0a 0a0a0a0a 0a0a0a0a (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 12
+ vspltb: => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000)
+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 15
+ vspltb: => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
+ vspltb: => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
+ vspltb: => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
+ vspltb: => f7f7f7f7 f7f7f7f7 f7f7f7f7 f7f7f7f7 (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
+ vspltb: => fafafafa fafafafa fafafafa fafafafa (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
+ vspltb: => fefefefe fefefefe fefefefe fefefefe (00000000)
+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
+ vspltb: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 0
+ vsplth: => 01020102 01020102 01020102 01020102 (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 3
+ vsplth: => 07080708 07080708 07080708 07080708 (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 6
+ vsplth: => 0e0d0e0d 0e0d0e0d 0e0d0e0d 0e0d0e0d (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 9
+ vsplth: => 03040304 03040304 03040304 03040304 (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 12
+ vsplth: => 090a090a 090a090a 090a090a 090a090a (00000000)
+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 15
+ vsplth: => 0e0f0e0f 0e0f0e0f 0e0f0e0f 0e0f0e0f (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
+ vsplth: => f1f2f1f2 f1f2f1f2 f1f2f1f2 f1f2f1f2 (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
+ vsplth: => f7f8f7f8 f7f8f7f8 f7f8f7f8 f7f8f7f8 (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
+ vsplth: => fefdfefd fefdfefd fefdfefd fefdfefd (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
+ vsplth: => f3f4f3f4 f3f4f3f4 f3f4f3f4 f3f4f3f4 (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
+ vsplth: => f9faf9fa f9faf9fa f9faf9fa f9faf9fa (00000000)
+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
+ vsplth: => fefffeff fefffeff fefffeff fefffeff (00000000)
+
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 0
+ vspltw: => 01020304 01020304 01020304 01020304 (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 3
+ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 6
+ vspltw: => 090a0b0c 090a0b0c 090a0b0c 090a0b0c (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 9
+ vspltw: => 05060708 05060708 05060708 05060708 (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 12
+ vspltw: => 01020304 01020304 01020304 01020304 (00000000)
+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 15
+ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
+ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
+ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
+ vspltw: => f9fafbfc f9fafbfc f9fafbfc f9fafbfc (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
+ vspltw: => f5f6f7f8 f5f6f7f8 f5f6f7f8 f5f6f7f8 (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
+ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000)
+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
+ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000)
+
+ vspltisb: 0 => 00000000 00000000 00000000 00000000 (00000000)
+ vspltisb: 1 => 01010101 01010101 01010101 01010101 (00000000)
+ vspltisb: 2 => 02020202 02020202 02020202 02020202 (00000000)
+ vspltisb: 3 => 03030303 03030303 03030303 03030303 (00000000)
+ vspltisb: 4 => 04040404 04040404 04040404 04040404 (00000000)
+ vspltisb: 5 => 05050505 05050505 05050505 05050505 (00000000)
+ vspltisb: 6 => 06060606 06060606 06060606 06060606 (00000000)
+ vspltisb: 7 => 07070707 07070707 07070707 07070707 (00000000)
+ vspltisb: 8 => 08080808 08080808 08080808 08080808 (00000000)
+ vspltisb: 9 => 09090909 09090909 09090909 09090909 (00000000)
+ vspltisb: 10 => 0a0a0a0a 0a0a0a0a 0a0a0a0a 0a0a0a0a (00000000)
+ vspltisb: 11 => 0b0b0b0b 0b0b0b0b 0b0b0b0b 0b0b0b0b (00000000)
+ vspltisb: 12 => 0c0c0c0c 0c0c0c0c 0c0c0c0c 0c0c0c0c (00000000)
+ vspltisb: 13 => 0d0d0d0d 0d0d0d0d 0d0d0d0d 0d0d0d0d (00000000)
+ vspltisb: 14 => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000)
+ vspltisb: 15 => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000)
+ vspltisb: 16 => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
+ vspltisb: 17 => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000)
+ vspltisb: 18 => f2f2f2f2 f2f2f2f2 f2f2f2f2 f2f2f2f2 (00000000)
+ vspltisb: 19 => f3f3f3f3 f3f3f3f3 f3f3f3f3 f3f3f3f3 (00000000)
+ vspltisb: 20 => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000)
+ vspltisb: 21 => f5f5f5f5 f5f5f5f5 f5f5f5f5 f5f5f5f5 (00000000)
+ vspltisb: 22 => f6f6f6f6 f6f6f6f6 f6f6f6f6 f6f6f6f6 (00000000)
+ vspltisb: 23 => f7f7f7f7 f7f7f7f7 f7f7f7f7 f7f7f7f7 (00000000)
+ vspltisb: 24 => f8f8f8f8 f8f8f8f8 f8f8f8f8 f8f8f8f8 (00000000)
+ vspltisb: 25 => f9f9f9f9 f9f9f9f9 f9f9f9f9 f9f9f9f9 (00000000)
+ vspltisb: 26 => fafafafa fafafafa fafafafa fafafafa (00000000)
+ vspltisb: 27 => fbfbfbfb fbfbfbfb fbfbfbfb fbfbfbfb (00000000)
+ vspltisb: 28 => fcfcfcfc fcfcfcfc fcfcfcfc fcfcfcfc (00000000)
+ vspltisb: 29 => fdfdfdfd fdfdfdfd fdfdfdfd fdfdfdfd (00000000)
+ vspltisb: 30 => fefefefe fefefefe fefefefe fefefefe (00000000)
+ vspltisb: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vspltish: 0 => 00000000 00000000 00000000 00000000 (00000000)
+ vspltish: 1 => 00010001 00010001 00010001 00010001 (00000000)
+ vspltish: 2 => 00020002 00020002 00020002 00020002 (00000000)
+ vspltish: 3 => 00030003 00030003 00030003 00030003 (00000000)
+ vspltish: 4 => 00040004 00040004 00040004 00040004 (00000000)
+ vspltish: 5 => 00050005 00050005 00050005 00050005 (00000000)
+ vspltish: 6 => 00060006 00060006 00060006 00060006 (00000000)
+ vspltish: 7 => 00070007 00070007 00070007 00070007 (00000000)
+ vspltish: 8 => 00080008 00080008 00080008 00080008 (00000000)
+ vspltish: 9 => 00090009 00090009 00090009 00090009 (00000000)
+ vspltish: 10 => 000a000a 000a000a 000a000a 000a000a (00000000)
+ vspltish: 11 => 000b000b 000b000b 000b000b 000b000b (00000000)
+ vspltish: 12 => 000c000c 000c000c 000c000c 000c000c (00000000)
+ vspltish: 13 => 000d000d 000d000d 000d000d 000d000d (00000000)
+ vspltish: 14 => 000e000e 000e000e 000e000e 000e000e (00000000)
+ vspltish: 15 => 000f000f 000f000f 000f000f 000f000f (00000000)
+ vspltish: 16 => fff0fff0 fff0fff0 fff0fff0 fff0fff0 (00000000)
+ vspltish: 17 => fff1fff1 fff1fff1 fff1fff1 fff1fff1 (00000000)
+ vspltish: 18 => fff2fff2 fff2fff2 fff2fff2 fff2fff2 (00000000)
+ vspltish: 19 => fff3fff3 fff3fff3 fff3fff3 fff3fff3 (00000000)
+ vspltish: 20 => fff4fff4 fff4fff4 fff4fff4 fff4fff4 (00000000)
+ vspltish: 21 => fff5fff5 fff5fff5 fff5fff5 fff5fff5 (00000000)
+ vspltish: 22 => fff6fff6 fff6fff6 fff6fff6 fff6fff6 (00000000)
+ vspltish: 23 => fff7fff7 fff7fff7 fff7fff7 fff7fff7 (00000000)
+ vspltish: 24 => fff8fff8 fff8fff8 fff8fff8 fff8fff8 (00000000)
+ vspltish: 25 => fff9fff9 fff9fff9 fff9fff9 fff9fff9 (00000000)
+ vspltish: 26 => fffafffa fffafffa fffafffa fffafffa (00000000)
+ vspltish: 27 => fffbfffb fffbfffb fffbfffb fffbfffb (00000000)
+ vspltish: 28 => fffcfffc fffcfffc fffcfffc fffcfffc (00000000)
+ vspltish: 29 => fffdfffd fffdfffd fffdfffd fffdfffd (00000000)
+ vspltish: 30 => fffefffe fffefffe fffefffe fffefffe (00000000)
+ vspltish: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vspltisw: 0 => 00000000 00000000 00000000 00000000 (00000000)
+ vspltisw: 1 => 00000001 00000001 00000001 00000001 (00000000)
+ vspltisw: 2 => 00000002 00000002 00000002 00000002 (00000000)
+ vspltisw: 3 => 00000003 00000003 00000003 00000003 (00000000)
+ vspltisw: 4 => 00000004 00000004 00000004 00000004 (00000000)
+ vspltisw: 5 => 00000005 00000005 00000005 00000005 (00000000)
+ vspltisw: 6 => 00000006 00000006 00000006 00000006 (00000000)
+ vspltisw: 7 => 00000007 00000007 00000007 00000007 (00000000)
+ vspltisw: 8 => 00000008 00000008 00000008 00000008 (00000000)
+ vspltisw: 9 => 00000009 00000009 00000009 00000009 (00000000)
+ vspltisw: 10 => 0000000a 0000000a 0000000a 0000000a (00000000)
+ vspltisw: 11 => 0000000b 0000000b 0000000b 0000000b (00000000)
+ vspltisw: 12 => 0000000c 0000000c 0000000c 0000000c (00000000)
+ vspltisw: 13 => 0000000d 0000000d 0000000d 0000000d (00000000)
+ vspltisw: 14 => 0000000e 0000000e 0000000e 0000000e (00000000)
+ vspltisw: 15 => 0000000f 0000000f 0000000f 0000000f (00000000)
+ vspltisw: 16 => fffffff0 fffffff0 fffffff0 fffffff0 (00000000)
+ vspltisw: 17 => fffffff1 fffffff1 fffffff1 fffffff1 (00000000)
+ vspltisw: 18 => fffffff2 fffffff2 fffffff2 fffffff2 (00000000)
+ vspltisw: 19 => fffffff3 fffffff3 fffffff3 fffffff3 (00000000)
+ vspltisw: 20 => fffffff4 fffffff4 fffffff4 fffffff4 (00000000)
+ vspltisw: 21 => fffffff5 fffffff5 fffffff5 fffffff5 (00000000)
+ vspltisw: 22 => fffffff6 fffffff6 fffffff6 fffffff6 (00000000)
+ vspltisw: 23 => fffffff7 fffffff7 fffffff7 fffffff7 (00000000)
+ vspltisw: 24 => fffffff8 fffffff8 fffffff8 fffffff8 (00000000)
+ vspltisw: 25 => fffffff9 fffffff9 fffffff9 fffffff9 (00000000)
+ vspltisw: 26 => fffffffa fffffffa fffffffa fffffffa (00000000)
+ vspltisw: 27 => fffffffb fffffffb fffffffb fffffffb (00000000)
+ vspltisw: 28 => fffffffc fffffffc fffffffc fffffffc (00000000)
+ vspltisw: 29 => fffffffd fffffffd fffffffd fffffffd (00000000)
+ vspltisw: 30 => fffffffe fffffffe fffffffe fffffffe (00000000)
+ vspltisw: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0
+ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000)
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 14
+ vsldoi: => 0e0f0102 03040506 0708090a 0b0c0e0d] (00000000)
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0
+ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000)
+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
+ vsldoi: => 0e0ff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0
+ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000)
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 14
+ vsldoi: => feff0102 03040506 0708090a 0b0c0e0d] (00000000)
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0
+ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000)
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
+ vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
+
+ lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+ lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
+ lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+ lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
+ lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
+ lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
+ lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
+ lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
+ lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
+ lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
+ lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
+ lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
+ lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
+ lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
+ lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
+ lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
+ lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+ lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
+
+ lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+ lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
+ lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+ lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
+ lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
+ lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
+ lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
+ lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
+ lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
+ lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
+ lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
+ lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
+ lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
+ lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
+ lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
+ lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
+ lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+ lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
+
+Altivec load insns with two register args:
+ lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
+ lvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000008 00000000 00000000 (00000000)
+ lvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 00000e00 (00000000)
+ lvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1000000 00000000 00000000 00000000 (00000000)
+ lvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 000000f8 00000000 00000000 (00000000)
+ lvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 0000fe00 (00000000)
+
+ lvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020000 00000000 00000000 00000000 (00000000)
+ lvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000708 00000000 00000000 (00000000)
+ lvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 00000e0f (00000000)
+ lvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f20000 00000000 00000000 00000000 (00000000)
+ lvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 0000f7f8 00000000 00000000 (00000000)
+ lvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 0000feff (00000000)
+
+ lvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000)
+ lvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05060708 00000000 00000000 (00000000)
+ lvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 0e0d0e0f (00000000)
+ lvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000)
+ lvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5f6f7f8 00000000 00000000 (00000000)
+ lvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 fefdfeff (00000000)
+
+ lvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ lvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ lvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ lvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ lvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ lvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ lvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+Altivec store insns with three register args:
+ stvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
+ stvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000008 00000000 00000000 (00000000)
+ stvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000008 00000000 00000e00 (00000000)
+ stvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1000000 00000000 00000000 00000000 (00000000)
+ stvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1000000 000000f8 00000000 00000000 (00000000)
+ stvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1000000 000000f8 00000000 0000fe00 (00000000)
+
+ stvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020000 00000000 00000000 00000000 (00000000)
+ stvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020000 00000708 00000000 00000000 (00000000)
+ stvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020000 00000708 00000000 00000e0f (00000000)
+ stvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f20000 00000000 00000000 00000000 (00000000)
+ stvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f20000 0000f7f8 00000000 00000000 (00000000)
+ stvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f20000 0000f7f8 00000000 0000feff (00000000)
+
+ stvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000)
+ stvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 00000000 (00000000)
+ stvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 0e0d0e0f (00000000)
+ stvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000)
+ stvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 00000000 (00000000)
+ stvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 fefdfeff (00000000)
+
+ stvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ stvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ stvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+ stvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+ stvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ stvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+ stvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
+Altivec floating point arith insns with two args:
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 033fffff 033fffff 033fffff 033fffff (00000000)
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d1bfffff d1bfffff d1bfffff d1bfffff (00000000)
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 51bfffff 51bfffff 51bfffff 51bfffff (00000000)
+ vsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 833fffff 833fffff 833fffff 833fffff (00000000)
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vmaxfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vmaxfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaxfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vmaxfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vmaxfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vmaxfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaxfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vminfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vminfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vminfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
+ vminfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vminfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vminfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vminfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vminfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vminfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vminfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
+ vminfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vminfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vminfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vminfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vminfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vminfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vminfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vminfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+Altivec floating point arith insns with three args:
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+
+Altivec floating point arith insns with one arg:
+ vrfin: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrfin: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfin: 513fffff 513fffff 513fffff 513fffff
+ vrfin: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vrfin: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrfin: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfin: d13fffff d13fffff d13fffff d13fffff
+ vrfin: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vrfin: 00000000 00000000 00000000 00000000
+ vrfin: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfin: 80000000 80000000 80000000 80000000
+ vrfin: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfin: 7f800000 7f800000 7f800000 7f800000
+ vrfin: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrfin: ff800000 ff800000 ff800000 ff800000
+ vrfin: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrfin: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfin: ffffffff ffffffff ffffffff ffffffff
+ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vrfin: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfin: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vrfiz: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrfiz: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfiz: 513fffff 513fffff 513fffff 513fffff
+ vrfiz: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vrfiz: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrfiz: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfiz: d13fffff d13fffff d13fffff d13fffff
+ vrfiz: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vrfiz: 00000000 00000000 00000000 00000000
+ vrfiz: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfiz: 80000000 80000000 80000000 80000000
+ vrfiz: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfiz: 7f800000 7f800000 7f800000 7f800000
+ vrfiz: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrfiz: ff800000 ff800000 ff800000 ff800000
+ vrfiz: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrfiz: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfiz: ffffffff ffffffff ffffffff ffffffff
+ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vrfiz: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfiz: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vrfip: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrfip: => 3f800000 3f800000 3f800000 3f800000 (00000000)
+ vrfip: 513fffff 513fffff 513fffff 513fffff
+ vrfip: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vrfip: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrfip: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfip: d13fffff d13fffff d13fffff d13fffff
+ vrfip: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vrfip: 00000000 00000000 00000000 00000000
+ vrfip: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfip: 80000000 80000000 80000000 80000000
+ vrfip: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfip: 7f800000 7f800000 7f800000 7f800000
+ vrfip: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrfip: ff800000 ff800000 ff800000 ff800000
+ vrfip: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrfip: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfip: ffffffff ffffffff ffffffff ffffffff
+ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vrfip: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfip: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vrfim: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrfim: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfim: 513fffff 513fffff 513fffff 513fffff
+ vrfim: => 513fffff 513fffff 513fffff 513fffff (00000000)
+ vrfim: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrfim: => bf800000 bf800000 bf800000 bf800000 (00000000)
+ vrfim: d13fffff d13fffff d13fffff d13fffff
+ vrfim: => d13fffff d13fffff d13fffff d13fffff (00000000)
+ vrfim: 00000000 00000000 00000000 00000000
+ vrfim: => 00000000 00000000 00000000 00000000 (00000000)
+ vrfim: 80000000 80000000 80000000 80000000
+ vrfim: => 80000000 80000000 80000000 80000000 (00000000)
+ vrfim: 7f800000 7f800000 7f800000 7f800000
+ vrfim: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrfim: ff800000 ff800000 ff800000 ff800000
+ vrfim: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrfim: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfim: ffffffff ffffffff ffffffff ffffffff
+ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vrfim: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
+ vrfim: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
+
+ vrefp: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrefp: => 7c2a8000 7c2a8000 7c2a8000 7c2a8000 (00000000)
+ vrefp: 513fffff 513fffff 513fffff 513fffff
+ vrefp: => 2daa8000 2daa8000 2daa8000 2daa8000 (00000000)
+ vrefp: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrefp: => fc2a8000 fc2a8000 fc2a8000 fc2a8000 (00000000)
+ vrefp: d13fffff d13fffff d13fffff d13fffff
+ vrefp: => adaa8000 adaa8000 adaa8000 adaa8000 (00000000)
+ vrefp: 00000000 00000000 00000000 00000000
+ vrefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrefp: 80000000 80000000 80000000 80000000
+ vrefp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrefp: 7f800000 7f800000 7f800000 7f800000
+ vrefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vrefp: ff800000 ff800000 ff800000 ff800000
+ vrefp: => 80000000 80000000 80000000 80000000 (00000000)
+ vrefp: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
+ vrefp: ffffffff ffffffff ffffffff ffffffff
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
+ vrefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
+ vrefp: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
+
+ vrsqrtefp: 02bfffff 02bfffff 02bfffff 02bfffff
+ vrsqrtefp: => 5dd10000 5dd10000 5dd10000 5dd10000 (00000000)
+ vrsqrtefp: 513fffff 513fffff 513fffff 513fffff
+ vrsqrtefp: => 3693c000 3693c000 3693c000 3693c000 (00000000)
+ vrsqrtefp: 82bfffff 82bfffff 82bfffff 82bfffff
+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vrsqrtefp: d13fffff d13fffff d13fffff d13fffff
+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vrsqrtefp: 00000000 00000000 00000000 00000000
+ vrsqrtefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
+ vrsqrtefp: 80000000 80000000 80000000 80000000
+ vrsqrtefp: => ff800000 ff800000 ff800000 ff800000 (00000000)
+ vrsqrtefp: 7f800000 7f800000 7f800000 7f800000
+ vrsqrtefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vrsqrtefp: ff800000 ff800000 ff800000 ff800000
+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
+ vrsqrtefp: 7fffffff 7fffffff 7fffffff 7fffffff
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
+ vrsqrtefp: ffffffff ffffffff ffffffff ffffffff
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
+ vrsqrtefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
+ vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff
+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
+
+Altivec floating point compare insns:
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpeqfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
+ vcmpgefp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
+
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
+ vcmpbfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
+
+Altivec floating point compare insns with flags update:
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
+ vcmpgefp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
+
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
+ vcmpbfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
+ vcmpbfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
+
+Altivec float special insns:
+ vcfux: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
+ vcfux: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
+ vcfux: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000)
+ vcfux: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000)
+ vcfux: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000)
+ vcfux: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000)
+ vcfux: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000)
+ vcfux: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000)
+ vcfux: 82bfffff (-2.821186e-37), 0 => 4f02c000 ( 2.193621e+09) (00000000)
+ vcfux: 82bfffff (-2.821186e-37), 9 => 4a82c000 ( 4.284416e+06) (00000000)
+ vcfux: 82bfffff (-2.821186e-37), 18 => 4602c000 ( 8.368000e+03) (00000000)
+ vcfux: 82bfffff (-2.821186e-37), 27 => 4182c000 ( 1.634375e+01) (00000000)
+ vcfux: d13fffff (-5.153960e+10), 0 => 4f514000 ( 3.510632e+09) (00000000)
+ vcfux: d13fffff (-5.153960e+10), 9 => 4ad14000 ( 6.856704e+06) (00000000)
+ vcfux: d13fffff (-5.153960e+10), 18 => 46514000 ( 1.339200e+04) (00000000)
+ vcfux: d13fffff (-5.153960e+10), 27 => 41d14000 ( 2.615625e+01) (00000000)
+ vcfux: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vcfux: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vcfux: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vcfux: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vcfux: 80000000 (-0.000000e+00), 0 => 4f000000 ( 2.147484e+09) (00000000)
+ vcfux: 80000000 (-0.000000e+00), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfux: 80000000 (-0.000000e+00), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfux: 80000000 (-0.000000e+00), 27 => 41800000 ( 1.600000e+01) (00000000)
+ vcfux: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000)
+ vcfux: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000)
+ vcfux: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000)
+ vcfux: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000)
+ vcfux: ff800000 ( -inf), 0 => 4f7f8000 ( 4.286579e+09) (00000000)
+ vcfux: ff800000 ( -inf), 9 => 4aff8000 ( 8.372224e+06) (00000000)
+ vcfux: ff800000 ( -inf), 18 => 467f8000 ( 1.635200e+04) (00000000)
+ vcfux: ff800000 ( -inf), 27 => 41ff8000 ( 3.193750e+01) (00000000)
+ vcfux: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000)
+ vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
+ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
+ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
+ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
+ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
+ vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
+ vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
+ vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
+ vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
+ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
+ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
+ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
+ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
+
+ vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
+ vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
+ vcfsx: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000)
+ vcfsx: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000)
+ vcfsx: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000)
+ vcfsx: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000)
+ vcfsx: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000)
+ vcfsx: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000)
+ vcfsx: 82bfffff (-2.821186e-37), 0 => cefa8000 (-2.101346e+09) (00000000)
+ vcfsx: 82bfffff (-2.821186e-37), 9 => ca7a8000 (-4.104192e+06) (00000000)
+ vcfsx: 82bfffff (-2.821186e-37), 18 => c5fa8000 (-8.016000e+03) (00000000)
+ vcfsx: 82bfffff (-2.821186e-37), 27 => c17a8000 (-1.565625e+01) (00000000)
+ vcfsx: d13fffff (-5.153960e+10), 0 => ce3b0000 (-7.843348e+08) (00000000)
+ vcfsx: d13fffff (-5.153960e+10), 9 => c9bb0000 (-1.531904e+06) (00000000)
+ vcfsx: d13fffff (-5.153960e+10), 18 => c53b0000 (-2.992000e+03) (00000000)
+ vcfsx: d13fffff (-5.153960e+10), 27 => c0bb0000 (-5.843750e+00) (00000000)
+ vcfsx: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vcfsx: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vcfsx: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vcfsx: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vcfsx: 80000000 (-0.000000e+00), 0 => cf000000 (-2.147484e+09) (00000000)
+ vcfsx: 80000000 (-0.000000e+00), 9 => ca800000 (-4.194304e+06) (00000000)
+ vcfsx: 80000000 (-0.000000e+00), 18 => c6000000 (-8.192000e+03) (00000000)
+ vcfsx: 80000000 (-0.000000e+00), 27 => c1800000 (-1.600000e+01) (00000000)
+ vcfsx: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000)
+ vcfsx: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000)
+ vcfsx: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000)
+ vcfsx: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000)
+ vcfsx: ff800000 ( -inf), 0 => cb000000 (-8.388608e+06) (00000000)
+ vcfsx: ff800000 ( -inf), 9 => c6800000 (-1.638400e+04) (00000000)
+ vcfsx: ff800000 ( -inf), 18 => c2000000 (-3.200000e+01) (00000000)
+ vcfsx: ff800000 ( -inf), 27 => bd800000 (-6.250000e-02) (00000000)
+ vcfsx: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000)
+ vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
+ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
+ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
+ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
+ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
+ vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
+ vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
+ vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
+ vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
+ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
+ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
+ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
+ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
+
+ vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
+ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
+ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
+ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: d13fffff (-5.153960e+10), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: d13fffff (-5.153960e+10), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: d13fffff (-5.153960e+10), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: d13fffff (-5.153960e+10), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
+ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
+ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
+ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
+ vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+
+ vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 513fffff ( 5.153960e+10), 0 => 7fffffff ( nan) (00000000)
+ vctsxs: 513fffff ( 5.153960e+10), 9 => 7fffffff ( nan) (00000000)
+ vctsxs: 513fffff ( 5.153960e+10), 18 => 7fffffff ( nan) (00000000)
+ vctsxs: 513fffff ( 5.153960e+10), 27 => 7fffffff ( nan) (00000000)
+ vctsxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: d13fffff (-5.153960e+10), 0 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: d13fffff (-5.153960e+10), 9 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: d13fffff (-5.153960e+10), 18 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: d13fffff (-5.153960e+10), 27 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7f800000 ( inf), 0 => 7fffffff ( nan) (00000000)
+ vctsxs: 7f800000 ( inf), 9 => 7fffffff ( nan) (00000000)
+ vctsxs: 7f800000 ( inf), 18 => 7fffffff ( nan) (00000000)
+ vctsxs: 7f800000 ( inf), 27 => 7fffffff ( nan) (00000000)
+ vctsxs: ff800000 ( -inf), 0 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: ff800000 ( -inf), 9 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: ff800000 ( -inf), 18 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: ff800000 ( -inf), 27 => 80000000 (-0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+
+All done. Tested 165 different instructions
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/none/tests/ppc64/power6_bcmp.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/none/tests/ppc64/power6_bcmp.stdout.exp
diff --git a/main/none/tests/ppc64/round.c b/main/none/tests/ppc64/round.c
index f49c0b5..dd2bef6 100644
--- a/main/none/tests/ppc64/round.c
+++ b/main/none/tests/ppc64/round.c
@@ -142,7 +142,6 @@
int status = 0;
flt_overlay R, E;
char *result;
- char *eq_ne;
set_rounding_mode(mode);
@@ -153,11 +152,9 @@
(R.layout.exp != E.layout.exp) ||
(R.layout.frac != E.layout.frac)) {
result = "FAILED";
- eq_ne = "!=";
status = 1;
} else {
result = "PASSED";
- eq_ne = "==";
status = 0;
}
printf("%s:%s:(double)(%-20a) = %20a",
diff --git a/main/none/tests/ppc64/test_dfp1.c b/main/none/tests/ppc64/test_dfp1.c
new file mode 100644
index 0000000..40c3a10
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp1.c
@@ -0,0 +1,504 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+static Bool do_dot;
+static void _test_dadd (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dadd. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dadd %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dsub (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dsub. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dsub %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dmul (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dmul. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dmul %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_ddiv (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("ddiv. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("ddiv %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+// Quad DFP arith instructions
+static void _test_daddq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("daddq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("daddq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dsubq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dsubq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dsubq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dmulq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dmulq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dmulq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_ddivq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("ddivq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("ddivq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_mffs (void)
+{
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14));
+}
+
+static void _test_mtfsf (int upper)
+{
+ if (upper)
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) );
+ else
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 0" : : "f"(f14) );
+}
+
+typedef void (*test_func_t)(void);
+typedef struct test_table
+{
+ test_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals or dfp128_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x2[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 8},
+ {7, 1},
+ {9, 15},
+ {8, 12},
+ {7, 11},
+ {13, 2},
+ {13, 14},
+ {15, 12},
+ {14, 11},
+ {12, 12},
+ {12, 11},
+ {11, 11}
+};
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+ Bool cr_supported;
+} dfp_test_t;
+
+
+static dfp_test_t
+dfp_two_arg_tests[] = {
+ { &_test_dadd, "dadd", dfp_2args_x1, 25, LONG_TEST, "+", False},
+ { &_test_dsub, "dsub", dfp_2args_x1, 25, LONG_TEST, "-", False},
+ { &_test_dmul, "dmul", dfp_2args_x2, 19, LONG_TEST, "*", False},
+ { &_test_ddiv, "ddiv", dfp_2args_x2, 19, LONG_TEST, "/", False},
+ { &_test_daddq, "daddq", dfp_2args_x1, 25, QUAD_TEST, "+", False},
+ { &_test_dsubq, "dsubq", dfp_2args_x1, 25, QUAD_TEST, "-", False},
+ { &_test_dmulq, "dmulq", dfp_2args_x2, 19, QUAD_TEST, "*", False},
+ { &_test_ddivq, "ddivq", dfp_2args_x2, 19, QUAD_TEST, "/", False},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_two_arg_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double res, d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ int k = 0;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_two_arg_tests[k].test_func)) {
+ int i, repeat = 1;
+ dfp_test_t test_group = dfp_two_arg_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_group.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_group.targs[i].fra_idx];
+ u1 = dfp64_vals[test_group.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_group.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_group.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_group.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ res = f18;
+
+ condreg = (flags & 0x000000f0) >> 4;
+ printf("%s%s %016llx", test_group.name, do_dot? "." : "", u0);
+ if (test_group.precision == LONG_TEST) {
+ printf(" %s %016llx => %016llx",
+ test_group.op, u1, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx %s %016llx %016llx ==> %016llx %016llx",
+ u0x, test_group.op, u1, u1x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ if (test_group.cr_supported)
+ printf(" (cr = %08x)\n", condreg);
+ else
+ printf("\n");
+
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+void test_move_toFrom_fpscr(void)
+{
+#define BFP_MAX_RM 3
+ int shift = 0;
+ unsigned long long i, max_rm, expected_val;
+ double fpscr_in, fpscr_out;
+ unsigned long long * hex_fpscr_in = (unsigned long long *)&fpscr_in;
+ unsigned long long * hex_fpscr_out = (unsigned long long *)&fpscr_out;
+
+
+ max_rm = 4;
+again:
+ /* NOTE: The first time through this loop is for setting the binary
+ * floating point rounding mode (bits 62:63 of FPSCR). The second time
+ * through is for setting the decimal floating point rounding mode
+ * (bits 29:31 of FPSCR). In the second time through this loop, the value
+ * returned should include the final binary FP rounding mode, along with
+ * the decimal FP rounding modes.
+ */
+ for (i = 0; i < max_rm; i++) {
+ *hex_fpscr_in = (i << shift);
+ f14 = fpscr_in;
+ _test_mtfsf(max_rm/8);
+ *hex_fpscr_in = 0ULL;
+ f14= fpscr_in;
+ _test_mffs();
+ fpscr_out = f14;
+ if (max_rm == 4) {
+ *hex_fpscr_out &= (max_rm - 1) << shift;
+ expected_val = i << shift;
+ } else {
+ *hex_fpscr_out &= BFP_MAX_RM | ((max_rm - 1) << shift);
+ expected_val = (i << shift) | BFP_MAX_RM;
+ }
+
+ printf("FPSCR %s floating point rounding mode %016llx == %016llx? %s\n",
+ (max_rm == 8) ? "decimal" : "binary",
+ *hex_fpscr_out, expected_val,
+ (expected_val == *hex_fpscr_out) ? "yes" : "no");
+ }
+ if (max_rm == 4) {
+ max_rm = 8;
+ shift = 32;
+ goto again;
+ }
+}
+
+void test_rounding_modes(void)
+{
+ int j;
+ unsigned long long u0, u1, rm_idx;
+ double res, d0, d1, *d0p, *d1p, fpscr;
+ unsigned long long * hex_fpscr = (unsigned long long *)&fpscr;
+ u0 = 0x26cc3f1f534acdd4ULL;
+ u1 = 0x27feff197a42ba06ULL;
+ d0p = &d0;
+ d1p = &d1;
+
+ for (j = 0; j < 12; j++) {
+ for (rm_idx = 0; rm_idx < 8; rm_idx++) {
+ *hex_fpscr = 0ULL;
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14));
+ fpscr = f14;
+ *hex_fpscr &= 0xFFFFFFF0FFFFFFFFULL;
+ *hex_fpscr |= (rm_idx << 32);
+ f14 = fpscr;
+ SET_FPSCR_DRN;
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ _test_dmul();
+ res = f18;
+ printf("test #%d: dmul with rounding mode %d: %016llx * %016llx => %016llx\n",
+ j, (int)rm_idx, u0, u1, *((unsigned long long *)(&res)));
+ printf("\n");
+ }
+ // Changing the least significant bit of one of the dmul arguments give us more
+ // opportunities for different rounding modes to yield different results which
+ // can then be validated.
+ u0++;
+ }
+}
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_two_arg_ops,
+ "Test DFP arithmetic instructions"},
+ { &test_rounding_modes,
+ "Test DFP rounding modes"},
+ { &test_move_toFrom_fpscr,
+ "Test move to/from FPSCR"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc64/test_dfp1.stderr.exp b/main/none/tests/ppc64/test_dfp1.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp1.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc64/test_dfp1.stdout.exp b/main/none/tests/ppc64/test_dfp1.stdout.exp
new file mode 100644
index 0000000..614895d
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp1.stdout.exp
@@ -0,0 +1,583 @@
+Test DFP arithmetic instructions
+dadd 2234000000000e50 + 223400000014c000 => 223400000014ce50
+dadd a2340000000000e0 + 223400000014c000 => 223400000014a44c
+dadd 22240000000000cf + a21400010a395bcf => a21400010a1b9bcf
+dadd 2234000000000e50 + 000400000089b000 => 2e06500000000000
+dadd a2340000000000e0 + a21400010a395bcf => a21400080a395bcf
+dadd 6e4d3f1f534acdd4 + 223400000014c000 => 6e4d3f1f534acdd5
+dadd 6e4d3f1f534acdd4 + a2340000000000e0 => 6e4d3f1f534acdd4
+dadd 2238000000000000 + 223400000014c000 => 223400000014c000
+dadd 2238000000000000 + a2340000000000e0 => a2340000000000e0
+dadd a238000000000000 + 2234000000000e50 => 2234000000000e50
+dadd a238000000000000 + 223400000014c000 => 223400000014c000
+dadd a238000000000000 + a2340000000000e0 => a2340000000000e0
+dadd 2238000000000000 + a238000000000000 => 2238000000000000
+dadd fc00000000000000 + f800000000000000 => fc00000000000000
+dadd fc00000000000000 + 223400000014c000 => fc00000000000000
+dadd fc00000000000000 + 7800000000000000 => fc00000000000000
+dadd fc00000000000000 + fc00000000000000 => fc00000000000000
+dadd fc00000000000000 + fe000000d0e0a0d0 => fc000000d0e0a0d0
+dadd fe000000d0e0a0d0 + f800000000000000 => fc000000d0e0a0d0
+dadd fe000000d0e0a0d0 + 2234000000000e50 => fc000000d0e0a0d0
+dadd fe000000d0e0a0d0 + 7800000000000000 => fc000000d0e0a0d0
+dadd fe000000d0e0a0d0 + fe000000d0e0a0d0 => fc000000d0e0a0d0
+dadd f800000000000000 + f800000000000000 => f800000000000000
+dadd f800000000000000 + 22240000000000cf => f800000000000000
+dadd f800000000000000 + 7a34000000000000 => 7c00000000000000
+
+dadd. 2234000000000e50 + 223400000014c000 => 223400000014ce50
+dadd. a2340000000000e0 + 223400000014c000 => 223400000014a44c
+dadd. 22240000000000cf + a21400010a395bcf => a21400010a1b9bcf
+dadd. 2234000000000e50 + 000400000089b000 => 2e06500000000000
+dadd. a2340000000000e0 + a21400010a395bcf => a21400080a395bcf
+dadd. 6e4d3f1f534acdd4 + 223400000014c000 => 6e4d3f1f534acdd5
+dadd. 6e4d3f1f534acdd4 + a2340000000000e0 => 6e4d3f1f534acdd4
+dadd. 2238000000000000 + 223400000014c000 => 223400000014c000
+dadd. 2238000000000000 + a2340000000000e0 => a2340000000000e0
+dadd. a238000000000000 + 2234000000000e50 => 2234000000000e50
+dadd. a238000000000000 + 223400000014c000 => 223400000014c000
+dadd. a238000000000000 + a2340000000000e0 => a2340000000000e0
+dadd. 2238000000000000 + a238000000000000 => 2238000000000000
+dadd. fc00000000000000 + f800000000000000 => fc00000000000000
+dadd. fc00000000000000 + 223400000014c000 => fc00000000000000
+dadd. fc00000000000000 + 7800000000000000 => fc00000000000000
+dadd. fc00000000000000 + fc00000000000000 => fc00000000000000
+dadd. fc00000000000000 + fe000000d0e0a0d0 => fc000000d0e0a0d0
+dadd. fe000000d0e0a0d0 + f800000000000000 => fc000000d0e0a0d0
+dadd. fe000000d0e0a0d0 + 2234000000000e50 => fc000000d0e0a0d0
+dadd. fe000000d0e0a0d0 + 7800000000000000 => fc000000d0e0a0d0
+dadd. fe000000d0e0a0d0 + fe000000d0e0a0d0 => fc000000d0e0a0d0
+dadd. f800000000000000 + f800000000000000 => f800000000000000
+dadd. f800000000000000 + 22240000000000cf => f800000000000000
+dadd. f800000000000000 + 7a34000000000000 => 7c00000000000000
+
+
+dsub 2234000000000e50 - 223400000014c000 => a234000000149ad0
+dsub a2340000000000e0 - 223400000014c000 => a23400000014c0e0
+dsub 22240000000000cf - a21400010a395bcf => 221400010a571bcf
+dsub 2234000000000e50 - 000400000089b000 => 2e06500000000000
+dsub a2340000000000e0 - a21400010a395bcf => a214000477cb0d11
+dsub 6e4d3f1f534acdd4 - 223400000014c000 => 6e4d3f1f534acdd3
+dsub 6e4d3f1f534acdd4 - a2340000000000e0 => 6e4d3f1f534acdd4
+dsub 2238000000000000 - 223400000014c000 => a23400000014c000
+dsub 2238000000000000 - a2340000000000e0 => 22340000000000e0
+dsub a238000000000000 - 2234000000000e50 => a234000000000e50
+dsub a238000000000000 - 223400000014c000 => a23400000014c000
+dsub a238000000000000 - a2340000000000e0 => 22340000000000e0
+dsub 2238000000000000 - a238000000000000 => 2238000000000000
+dsub fc00000000000000 - f800000000000000 => fc00000000000000
+dsub fc00000000000000 - 223400000014c000 => fc00000000000000
+dsub fc00000000000000 - 7800000000000000 => fc00000000000000
+dsub fc00000000000000 - fc00000000000000 => fc00000000000000
+dsub fc00000000000000 - fe000000d0e0a0d0 => fc000000d0e0a0d0
+dsub fe000000d0e0a0d0 - f800000000000000 => fc000000d0e0a0d0
+dsub fe000000d0e0a0d0 - 2234000000000e50 => fc000000d0e0a0d0
+dsub fe000000d0e0a0d0 - 7800000000000000 => fc000000d0e0a0d0
+dsub fe000000d0e0a0d0 - fe000000d0e0a0d0 => fc000000d0e0a0d0
+dsub f800000000000000 - f800000000000000 => 7c00000000000000
+dsub f800000000000000 - 22240000000000cf => f800000000000000
+dsub f800000000000000 - 7a34000000000000 => f800000000000000
+
+dsub. 2234000000000e50 - 223400000014c000 => a234000000149ad0
+dsub. a2340000000000e0 - 223400000014c000 => a23400000014c0e0
+dsub. 22240000000000cf - a21400010a395bcf => 221400010a571bcf
+dsub. 2234000000000e50 - 000400000089b000 => 2e06500000000000
+dsub. a2340000000000e0 - a21400010a395bcf => a214000477cb0d11
+dsub. 6e4d3f1f534acdd4 - 223400000014c000 => 6e4d3f1f534acdd3
+dsub. 6e4d3f1f534acdd4 - a2340000000000e0 => 6e4d3f1f534acdd4
+dsub. 2238000000000000 - 223400000014c000 => a23400000014c000
+dsub. 2238000000000000 - a2340000000000e0 => 22340000000000e0
+dsub. a238000000000000 - 2234000000000e50 => a234000000000e50
+dsub. a238000000000000 - 223400000014c000 => a23400000014c000
+dsub. a238000000000000 - a2340000000000e0 => 22340000000000e0
+dsub. 2238000000000000 - a238000000000000 => 2238000000000000
+dsub. fc00000000000000 - f800000000000000 => fc00000000000000
+dsub. fc00000000000000 - 223400000014c000 => fc00000000000000
+dsub. fc00000000000000 - 7800000000000000 => fc00000000000000
+dsub. fc00000000000000 - fc00000000000000 => fc00000000000000
+dsub. fc00000000000000 - fe000000d0e0a0d0 => fc000000d0e0a0d0
+dsub. fe000000d0e0a0d0 - f800000000000000 => fc000000d0e0a0d0
+dsub. fe000000d0e0a0d0 - 2234000000000e50 => fc000000d0e0a0d0
+dsub. fe000000d0e0a0d0 - 7800000000000000 => fc000000d0e0a0d0
+dsub. fe000000d0e0a0d0 - fe000000d0e0a0d0 => fc000000d0e0a0d0
+dsub. f800000000000000 - f800000000000000 => 7c00000000000000
+dsub. f800000000000000 - 22240000000000cf => f800000000000000
+dsub. f800000000000000 - 7a34000000000000 => f800000000000000
+
+
+dmul 2234000000000e50 * 223400000014c000 => 22300001143a0000
+dmul a2340000000000e0 * 223400000014c000 => a23000000fa03000
+dmul 22240000000000cf * a21400010a395bcf => a20000fe5b36cca1
+dmul 2234000000000e50 * 000400000089b000 => 0000000c28a03000
+dmul a2340000000000e0 * a21400010a395bcf => 221000d67d31a940
+dmul 6e4d3f1f534acdd4 * 223400000014c000 => 266510610e1d3703
+dmul 6e4d3f1f534acdd4 * a2340000000000e0 => a656f47e5fba95b7
+dmul 2238000000000000 * a238000000000000 => a238000000000000
+dmul 2238000000000000 * 223400000014c000 => 2234000000000000
+dmul 4248000000000000 * 7a34000000000000 => 7c00000000000000
+dmul a238000000000000 * fc00000000000000 => fc00000000000000
+dmul 2238000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul 7800000000000000 * a2340000000000e0 => f800000000000000
+dmul 7800000000000000 * f800000000000000 => f800000000000000
+dmul 7a34000000000000 * fc00000000000000 => fc00000000000000
+dmul f800000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul fc00000000000000 * fc00000000000000 => fc00000000000000
+dmul fc00000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul fe000000d0e0a0d0 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+
+dmul. 2234000000000e50 * 223400000014c000 => 22300001143a0000
+dmul. a2340000000000e0 * 223400000014c000 => a23000000fa03000
+dmul. 22240000000000cf * a21400010a395bcf => a20000fe5b36cca1
+dmul. 2234000000000e50 * 000400000089b000 => 0000000c28a03000
+dmul. a2340000000000e0 * a21400010a395bcf => 221000d67d31a940
+dmul. 6e4d3f1f534acdd4 * 223400000014c000 => 266510610e1d3703
+dmul. 6e4d3f1f534acdd4 * a2340000000000e0 => a656f47e5fba95b7
+dmul. 2238000000000000 * a238000000000000 => a238000000000000
+dmul. 2238000000000000 * 223400000014c000 => 2234000000000000
+dmul. 4248000000000000 * 7a34000000000000 => 7c00000000000000
+dmul. a238000000000000 * fc00000000000000 => fc00000000000000
+dmul. 2238000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul. 7800000000000000 * a2340000000000e0 => f800000000000000
+dmul. 7800000000000000 * f800000000000000 => f800000000000000
+dmul. 7a34000000000000 * fc00000000000000 => fc00000000000000
+dmul. f800000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul. fc00000000000000 * fc00000000000000 => fc00000000000000
+dmul. fc00000000000000 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+dmul. fe000000d0e0a0d0 * fe000000d0e0a0d0 => fc000000d0e0a0d0
+
+
+ddiv 2234000000000e50 / 223400000014c000 => 29f20ccf848e2a4e
+ddiv a2340000000000e0 / 223400000014c000 => a5ed80474082c00b
+ddiv 22240000000000cf / a21400010a395bcf => b1eeabacabd62ac3
+ddiv 2234000000000e50 / 000400000089b000 => 7800000000000000
+ddiv a2340000000000e0 / a21400010a395bcf => 2dfc0e4e6a205575
+ddiv 6e4d3f1f534acdd4 / 223400000014c000 => 3e38ff87d92ca3c3
+ddiv 6e4d3f1f534acdd4 / a2340000000000e0 => ba48c92fea1aadc6
+ddiv 2238000000000000 / a238000000000000 => 7c00000000000000
+ddiv 2238000000000000 / 223400000014c000 => 223c000000000000
+ddiv 4248000000000000 / 7a34000000000000 => 0000000000000000
+ddiv a238000000000000 / fc00000000000000 => fc00000000000000
+ddiv 2238000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv 7800000000000000 / a2340000000000e0 => f800000000000000
+ddiv 7800000000000000 / f800000000000000 => 7c00000000000000
+ddiv 7a34000000000000 / fc00000000000000 => fc00000000000000
+ddiv f800000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv fc00000000000000 / fc00000000000000 => fc00000000000000
+ddiv fc00000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv fe000000d0e0a0d0 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+
+ddiv. 2234000000000e50 / 223400000014c000 => 29f20ccf848e2a4e
+ddiv. a2340000000000e0 / 223400000014c000 => a5ed80474082c00b
+ddiv. 22240000000000cf / a21400010a395bcf => b1eeabacabd62ac3
+ddiv. 2234000000000e50 / 000400000089b000 => 7800000000000000
+ddiv. a2340000000000e0 / a21400010a395bcf => 2dfc0e4e6a205575
+ddiv. 6e4d3f1f534acdd4 / 223400000014c000 => 3e38ff87d92ca3c3
+ddiv. 6e4d3f1f534acdd4 / a2340000000000e0 => ba48c92fea1aadc6
+ddiv. 2238000000000000 / a238000000000000 => 7c00000000000000
+ddiv. 2238000000000000 / 223400000014c000 => 223c000000000000
+ddiv. 4248000000000000 / 7a34000000000000 => 0000000000000000
+ddiv. a238000000000000 / fc00000000000000 => fc00000000000000
+ddiv. 2238000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv. 7800000000000000 / a2340000000000e0 => f800000000000000
+ddiv. 7800000000000000 / f800000000000000 => 7c00000000000000
+ddiv. 7a34000000000000 / fc00000000000000 => fc00000000000000
+ddiv. f800000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv. fc00000000000000 / fc00000000000000 => fc00000000000000
+ddiv. fc00000000000000 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+ddiv. fe000000d0e0a0d0 / fe000000d0e0a0d0 => fc000000d0e0a0d0
+
+
+daddq 2207c00000000000 0000000000000e50 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014ce50
+daddq a207c00000000000 00000000000000e0 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014a44c
+daddq 2206c00000000000 00000000000000cf + a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a1b9bcf
+daddq 2207c00000000000 0000000000000e50 + 000400000089b000 0a6000d000000049 ==> 2e00650000000000 0000000000000000
+daddq a207c00000000000 00000000000000e0 + a205c00000000000 000000010a395bcf ==> a205c00000000000 000000080a395bcf
+daddq 6209400000fd0000 00253f1f534acdd4 + 2207c00000000000 000000000014c000 ==> 2601130000000000 0000000000000000
+daddq 6209400000fd0000 00253f1f534acdd4 + a207c00000000000 00000000000000e0 ==> a600300000000000 0000000000000000
+daddq 2208000000000000 0000000000000000 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+daddq 2208000000000000 0000000000000000 + a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+daddq a208000000000000 0000000000000000 + 2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+daddq a208000000000000 0000000000000000 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+daddq a208000000000000 0000000000000000 + a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+daddq 2208000000000000 0000000000000000 + a208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+daddq 7e00000000000000 fe000000d0e0a0d0 + f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq 7e00000000000000 fe000000d0e0a0d0 + 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq 7e00000000000000 fe000000d0e0a0d0 + 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq 7e00000000000000 fe000000d0e0a0d0 + 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq 7e00000000000000 fe000000d0e0a0d0 + fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq fc00000000000000 c00100035b007700 + f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+daddq fc00000000000000 c00100035b007700 + 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+daddq fc00000000000000 c00100035b007700 + 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+daddq fc00000000000000 c00100035b007700 + fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+daddq f800000000000000 0000000000000000 + f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+daddq f800000000000000 0000000000000000 + 2206c00000000000 00000000000000cf ==> f800000000000000 0000000000000000
+daddq f800000000000000 0000000000000000 + f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+daddq. 2207c00000000000 0000000000000e50 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014ce50
+daddq. a207c00000000000 00000000000000e0 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014a44c
+daddq. 2206c00000000000 00000000000000cf + a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a1b9bcf
+daddq. 2207c00000000000 0000000000000e50 + 000400000089b000 0a6000d000000049 ==> 2e00650000000000 0000000000000000
+daddq. a207c00000000000 00000000000000e0 + a205c00000000000 000000010a395bcf ==> a205c00000000000 000000080a395bcf
+daddq. 6209400000fd0000 00253f1f534acdd4 + 2207c00000000000 000000000014c000 ==> 2601130000000000 0000000000000000
+daddq. 6209400000fd0000 00253f1f534acdd4 + a207c00000000000 00000000000000e0 ==> a600300000000000 0000000000000000
+daddq. 2208000000000000 0000000000000000 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+daddq. 2208000000000000 0000000000000000 + a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+daddq. a208000000000000 0000000000000000 + 2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+daddq. a208000000000000 0000000000000000 + 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+daddq. a208000000000000 0000000000000000 + a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+daddq. 2208000000000000 0000000000000000 + a208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+daddq. 7e00000000000000 fe000000d0e0a0d0 + f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. 7e00000000000000 fe000000d0e0a0d0 + 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. 7e00000000000000 fe000000d0e0a0d0 + 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. 7e00000000000000 fe000000d0e0a0d0 + 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. 7e00000000000000 fe000000d0e0a0d0 + fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+daddq. fc00000000000000 c00100035b007700 + f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+daddq. fc00000000000000 c00100035b007700 + 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+daddq. fc00000000000000 c00100035b007700 + 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+daddq. fc00000000000000 c00100035b007700 + fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+daddq. f800000000000000 0000000000000000 + f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+daddq. f800000000000000 0000000000000000 + 2206c00000000000 00000000000000cf ==> f800000000000000 0000000000000000
+daddq. f800000000000000 0000000000000000 + f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+
+dsubq 2207c00000000000 0000000000000e50 - 2207c00000000000 000000000014c000 ==> a207c00000000000 0000000000149ad0
+dsubq a207c00000000000 00000000000000e0 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c0e0
+dsubq 2206c00000000000 00000000000000cf - a205c00000000000 000000010a395bcf ==> 2205c00000000000 000000010a571bcf
+dsubq 2207c00000000000 0000000000000e50 - 000400000089b000 0a6000d000000049 ==> 2e00650000000000 0000000000000000
+dsubq a207c00000000000 00000000000000e0 - a205c00000000000 000000010a395bcf ==> a205c00000000000 0000000477cb0d11
+dsubq 6209400000fd0000 00253f1f534acdd4 - 2207c00000000000 000000000014c000 ==> a601130000000000 0000000000000000
+dsubq 6209400000fd0000 00253f1f534acdd4 - a207c00000000000 00000000000000e0 ==> 2600300000000000 0000000000000000
+dsubq 2208000000000000 0000000000000000 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c000
+dsubq 2208000000000000 0000000000000000 - a207c00000000000 00000000000000e0 ==> 2207c00000000000 00000000000000e0
+dsubq a208000000000000 0000000000000000 - 2207c00000000000 0000000000000e50 ==> a207c00000000000 0000000000000e50
+dsubq a208000000000000 0000000000000000 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c000
+dsubq a208000000000000 0000000000000000 - a207c00000000000 00000000000000e0 ==> 2207c00000000000 00000000000000e0
+dsubq 2208000000000000 0000000000000000 - a208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dsubq 7e00000000000000 fe000000d0e0a0d0 - f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq 7e00000000000000 fe000000d0e0a0d0 - 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq 7e00000000000000 fe000000d0e0a0d0 - 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq 7e00000000000000 fe000000d0e0a0d0 - 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq 7e00000000000000 fe000000d0e0a0d0 - fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq fc00000000000000 c00100035b007700 - f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dsubq fc00000000000000 c00100035b007700 - 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dsubq fc00000000000000 c00100035b007700 - 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dsubq fc00000000000000 c00100035b007700 - fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dsubq f800000000000000 0000000000000000 - f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dsubq f800000000000000 0000000000000000 - 2206c00000000000 00000000000000cf ==> f800000000000000 0000000000000000
+dsubq f800000000000000 0000000000000000 - f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+
+dsubq. 2207c00000000000 0000000000000e50 - 2207c00000000000 000000000014c000 ==> a207c00000000000 0000000000149ad0
+dsubq. a207c00000000000 00000000000000e0 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c0e0
+dsubq. 2206c00000000000 00000000000000cf - a205c00000000000 000000010a395bcf ==> 2205c00000000000 000000010a571bcf
+dsubq. 2207c00000000000 0000000000000e50 - 000400000089b000 0a6000d000000049 ==> 2e00650000000000 0000000000000000
+dsubq. a207c00000000000 00000000000000e0 - a205c00000000000 000000010a395bcf ==> a205c00000000000 0000000477cb0d11
+dsubq. 6209400000fd0000 00253f1f534acdd4 - 2207c00000000000 000000000014c000 ==> a601130000000000 0000000000000000
+dsubq. 6209400000fd0000 00253f1f534acdd4 - a207c00000000000 00000000000000e0 ==> 2600300000000000 0000000000000000
+dsubq. 2208000000000000 0000000000000000 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c000
+dsubq. 2208000000000000 0000000000000000 - a207c00000000000 00000000000000e0 ==> 2207c00000000000 00000000000000e0
+dsubq. a208000000000000 0000000000000000 - 2207c00000000000 0000000000000e50 ==> a207c00000000000 0000000000000e50
+dsubq. a208000000000000 0000000000000000 - 2207c00000000000 000000000014c000 ==> a207c00000000000 000000000014c000
+dsubq. a208000000000000 0000000000000000 - a207c00000000000 00000000000000e0 ==> 2207c00000000000 00000000000000e0
+dsubq. 2208000000000000 0000000000000000 - a208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. 7e00000000000000 fe000000d0e0a0d0 - fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dsubq. fc00000000000000 c00100035b007700 - f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dsubq. fc00000000000000 c00100035b007700 - 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dsubq. fc00000000000000 c00100035b007700 - 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dsubq. fc00000000000000 c00100035b007700 - fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dsubq. f800000000000000 0000000000000000 - f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dsubq. f800000000000000 0000000000000000 - 2206c00000000000 00000000000000cf ==> f800000000000000 0000000000000000
+dsubq. f800000000000000 0000000000000000 - f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+
+
+dmulq 2207c00000000000 0000000000000e50 * 2207c00000000000 000000000014c000 ==> 2207800000000000 00000001143a0000
+dmulq a207c00000000000 00000000000000e0 * 2207c00000000000 000000000014c000 ==> a207800000000000 000000000fa03000
+dmulq 2206c00000000000 00000000000000cf * a205c00000000000 000000010a395bcf ==> a204800000000000 000000fe5b36cca1
+dmulq 2207c00000000000 0000000000000e50 * 000400000089b000 0a6000d000000049 ==> 0003c007dd9d007e b20908000003a450
+dmulq a207c00000000000 00000000000000e0 * a205c00000000000 000000010a395bcf ==> 2205800000000000 000000d67d31a940
+dmulq 6209400000fd0000 00253f1f534acdd4 * 2207c00000000000 000000000014c000 ==> 660a84c004da6c00 004883107189d825
+dmulq 6209400000fd0000 00253f1f534acdd4 * a207c00000000000 00000000000000e0 ==> 8609d0a000d57800 0006f47e5fba95b7
+dmulq 2208000000000000 0000000000000000 * a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dmulq 2208000000000000 0000000000000000 * 2207c00000000000 000000000014c000 ==> 2207c00000000000 0000000000000000
+dmulq a248000000000000 0000000000000000 * f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dmulq a208000000000000 0000000000000000 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq 2208000000000000 0000000000000000 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dmulq 7800000000000000 0000000000000000 * a207c00000000000 00000000000000e0 ==> f800000000000000 0000000000000000
+dmulq 7800000000000000 0000000000000000 * f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dmulq f900000000000000 0000000000000000 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq f800000000000000 0000000000000000 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dmulq 7e00000000000000 fe000000d0e0a0d0 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq 7e00000000000000 fe000000d0e0a0d0 * fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq fc00000000000000 c00100035b007700 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+
+dmulq. 2207c00000000000 0000000000000e50 * 2207c00000000000 000000000014c000 ==> 2207800000000000 00000001143a0000
+dmulq. a207c00000000000 00000000000000e0 * 2207c00000000000 000000000014c000 ==> a207800000000000 000000000fa03000
+dmulq. 2206c00000000000 00000000000000cf * a205c00000000000 000000010a395bcf ==> a204800000000000 000000fe5b36cca1
+dmulq. 2207c00000000000 0000000000000e50 * 000400000089b000 0a6000d000000049 ==> 0003c007dd9d007e b20908000003a450
+dmulq. a207c00000000000 00000000000000e0 * a205c00000000000 000000010a395bcf ==> 2205800000000000 000000d67d31a940
+dmulq. 6209400000fd0000 00253f1f534acdd4 * 2207c00000000000 000000000014c000 ==> 660a84c004da6c00 004883107189d825
+dmulq. 6209400000fd0000 00253f1f534acdd4 * a207c00000000000 00000000000000e0 ==> 8609d0a000d57800 0006f47e5fba95b7
+dmulq. 2208000000000000 0000000000000000 * a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dmulq. 2208000000000000 0000000000000000 * 2207c00000000000 000000000014c000 ==> 2207c00000000000 0000000000000000
+dmulq. a248000000000000 0000000000000000 * f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dmulq. a208000000000000 0000000000000000 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq. 2208000000000000 0000000000000000 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dmulq. 7800000000000000 0000000000000000 * a207c00000000000 00000000000000e0 ==> f800000000000000 0000000000000000
+dmulq. 7800000000000000 0000000000000000 * f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dmulq. f900000000000000 0000000000000000 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq. f800000000000000 0000000000000000 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dmulq. 7e00000000000000 fe000000d0e0a0d0 * 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq. 7e00000000000000 fe000000d0e0a0d0 * fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dmulq. fc00000000000000 c00100035b007700 * fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+
+
+ddivq 2207c00000000000 0000000000000e50 / 2207c00000000000 000000000014c000 ==> 29ff20ccf848e2a6 b8333e1238a9ae0d
+ddivq a207c00000000000 00000000000000e0 / 2207c00000000000 000000000014c000 ==> a5fed80474082c00 b6011d020b002d81
+ddivq 2206c00000000000 00000000000000cf / a205c00000000000 000000010a395bcf ==> b1feeabacabd62ac 3812c9f3bf11f97a
+ddivq 2207c00000000000 0000000000000e50 / 000400000089b000 0a6000d000000049 ==> 4ffdcc9ad201f5f8 691a4dc710e32c5a
+ddivq a207c00000000000 00000000000000e0 / a205c00000000000 000000010a395bcf ==> 2dffc0e4e6a20557 44fc3ca241351d34
+ddivq 6209400000fd0000 00253f1f534acdd4 / 2207c00000000000 000000000014c000 ==> 1a082841943c02d8 00b408095bb6bed6
+ddivq 6209400000fd0000 00253f1f534acdd4 / a207c00000000000 00000000000000e0 ==> 9609000003069f40 0018c92fea1aadc6
+ddivq 2208000000000000 0000000000000000 / a208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+ddivq 2208000000000000 0000000000000000 / 2207c00000000000 000000000014c000 ==> 2208400000000000 0000000000000000
+ddivq a248000000000000 0000000000000000 / f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddivq a208000000000000 0000000000000000 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq 2208000000000000 0000000000000000 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+ddivq 7800000000000000 0000000000000000 / a207c00000000000 00000000000000e0 ==> f800000000000000 0000000000000000
+ddivq 7800000000000000 0000000000000000 / f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+ddivq f900000000000000 0000000000000000 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq f800000000000000 0000000000000000 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+ddivq 7e00000000000000 fe000000d0e0a0d0 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq 7e00000000000000 fe000000d0e0a0d0 / fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq fc00000000000000 c00100035b007700 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+
+ddivq. 2207c00000000000 0000000000000e50 / 2207c00000000000 000000000014c000 ==> 29ff20ccf848e2a6 b8333e1238a9ae0d
+ddivq. a207c00000000000 00000000000000e0 / 2207c00000000000 000000000014c000 ==> a5fed80474082c00 b6011d020b002d81
+ddivq. 2206c00000000000 00000000000000cf / a205c00000000000 000000010a395bcf ==> b1feeabacabd62ac 3812c9f3bf11f97a
+ddivq. 2207c00000000000 0000000000000e50 / 000400000089b000 0a6000d000000049 ==> 4ffdcc9ad201f5f8 691a4dc710e32c5a
+ddivq. a207c00000000000 00000000000000e0 / a205c00000000000 000000010a395bcf ==> 2dffc0e4e6a20557 44fc3ca241351d34
+ddivq. 6209400000fd0000 00253f1f534acdd4 / 2207c00000000000 000000000014c000 ==> 1a082841943c02d8 00b408095bb6bed6
+ddivq. 6209400000fd0000 00253f1f534acdd4 / a207c00000000000 00000000000000e0 ==> 9609000003069f40 0018c92fea1aadc6
+ddivq. 2208000000000000 0000000000000000 / a208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+ddivq. 2208000000000000 0000000000000000 / 2207c00000000000 000000000014c000 ==> 2208400000000000 0000000000000000
+ddivq. a248000000000000 0000000000000000 / f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddivq. a208000000000000 0000000000000000 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq. 2208000000000000 0000000000000000 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+ddivq. 7800000000000000 0000000000000000 / a207c00000000000 00000000000000e0 ==> f800000000000000 0000000000000000
+ddivq. 7800000000000000 0000000000000000 / f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+ddivq. f900000000000000 0000000000000000 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq. f800000000000000 0000000000000000 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+ddivq. 7e00000000000000 fe000000d0e0a0d0 / 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq. 7e00000000000000 fe000000d0e0a0d0 / fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+ddivq. fc00000000000000 c00100035b007700 / fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+
+
+Test DFP rounding modes
+test #0: dmul with rounding mode 0: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 1: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 2: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f6
+
+test #0: dmul with rounding mode 3: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 4: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 5: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f5
+
+test #0: dmul with rounding mode 6: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f6
+
+test #0: dmul with rounding mode 7: 26cc3f1f534acdd4 * 27feff197a42ba06 => 4ccf3810908e09f6
+
+test #1: dmul with rounding mode 0: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 1: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 2: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f8
+
+test #1: dmul with rounding mode 3: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 4: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 5: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #1: dmul with rounding mode 6: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f8
+
+test #1: dmul with rounding mode 7: 26cc3f1f534acdd5 * 27feff197a42ba06 => 4ccf3810908e09f7
+
+test #2: dmul with rounding mode 0: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 1: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 2: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e098a
+
+test #2: dmul with rounding mode 3: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 4: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 5: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #2: dmul with rounding mode 6: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e098a
+
+test #2: dmul with rounding mode 7: 26cc3f1f534acdd6 * 27feff197a42ba06 => 4ccf3810908e09f9
+
+test #3: dmul with rounding mode 0: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 1: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 2: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e09aa
+
+test #3: dmul with rounding mode 3: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 4: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 5: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #3: dmul with rounding mode 6: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e09aa
+
+test #3: dmul with rounding mode 7: 26cc3f1f534acdd7 * 27feff197a42ba06 => 4ccf3810908e098b
+
+test #4: dmul with rounding mode 0: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 1: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 2: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ca
+
+test #4: dmul with rounding mode 3: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 4: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 5: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #4: dmul with rounding mode 6: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ca
+
+test #4: dmul with rounding mode 7: 26cc3f1f534acdd8 * 27feff197a42ba06 => 4ccf3810908e09ab
+
+test #5: dmul with rounding mode 0: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 1: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 2: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09ea
+
+test #5: dmul with rounding mode 3: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 4: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 5: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09cb
+
+test #5: dmul with rounding mode 6: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09ea
+
+test #5: dmul with rounding mode 7: 26cc3f1f534acdd9 * 27feff197a42ba06 => 4ccf3810908e09ea
+
+test #6: dmul with rounding mode 0: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 1: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 2: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a56
+
+test #6: dmul with rounding mode 3: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 4: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 5: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a55
+
+test #6: dmul with rounding mode 6: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a56
+
+test #6: dmul with rounding mode 7: 26cc3f1f534acdda * 27feff197a42ba06 => 4ccf3810908e0a56
+
+test #7: dmul with rounding mode 0: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 1: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 2: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a58
+
+test #7: dmul with rounding mode 3: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 4: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 5: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #7: dmul with rounding mode 6: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a58
+
+test #7: dmul with rounding mode 7: 26cc3f1f534acddb * 27feff197a42ba06 => 4ccf3810908e0a57
+
+test #8: dmul with rounding mode 0: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 1: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef0
+
+test #8: dmul with rounding mode 2: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 3: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef0
+
+test #8: dmul with rounding mode 4: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 5: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 6: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #8: dmul with rounding mode 7: 26cc3f1f534acddc * 27feff197a42ba06 => 4ccf3810908e0ef1
+
+test #9: dmul with rounding mode 0: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 1: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef2
+
+test #9: dmul with rounding mode 2: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 3: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef2
+
+test #9: dmul with rounding mode 4: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 5: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 6: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef3
+
+test #9: dmul with rounding mode 7: 26cc3f1f534acddd * 27feff197a42ba06 => 4ccf3810908e0ef2
+
+test #10: dmul with rounding mode 0: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 1: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 2: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a64
+
+test #10: dmul with rounding mode 3: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 4: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 5: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #10: dmul with rounding mode 6: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a64
+
+test #10: dmul with rounding mode 7: 26cc3f1f534acdde * 27feff197a42ba06 => 4ccf3810908e0a63
+
+test #11: dmul with rounding mode 0: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 1: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 2: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a66
+
+test #11: dmul with rounding mode 3: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 4: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 5: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a65
+
+test #11: dmul with rounding mode 6: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a66
+
+test #11: dmul with rounding mode 7: 26cc3f1f534acddf * 27feff197a42ba06 => 4ccf3810908e0a66
+
+Test move to/from FPSCR
+FPSCR binary floating point rounding mode 0000000000000000 == 0000000000000000? yes
+FPSCR binary floating point rounding mode 0000000000000001 == 0000000000000001? yes
+FPSCR binary floating point rounding mode 0000000000000002 == 0000000000000002? yes
+FPSCR binary floating point rounding mode 0000000000000003 == 0000000000000003? yes
+FPSCR decimal floating point rounding mode 0000000000000003 == 0000000000000003? yes
+FPSCR decimal floating point rounding mode 0000000100000003 == 0000000100000003? yes
+FPSCR decimal floating point rounding mode 0000000200000003 == 0000000200000003? yes
+FPSCR decimal floating point rounding mode 0000000300000003 == 0000000300000003? yes
+FPSCR decimal floating point rounding mode 0000000400000003 == 0000000400000003? yes
+FPSCR decimal floating point rounding mode 0000000500000003 == 0000000500000003? yes
+FPSCR decimal floating point rounding mode 0000000600000003 == 0000000600000003? yes
+FPSCR decimal floating point rounding mode 0000000700000003 == 0000000700000003? yes
diff --git a/main/none/tests/ppc64/test_dfp1.vgtest b/main/none/tests/ppc64/test_dfp1.vgtest
new file mode 100644
index 0000000..0efe5df
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp1.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp1
diff --git a/main/none/tests/ppc64/test_dfp2.c b/main/none/tests/ppc64/test_dfp2.c
new file mode 100644
index 0000000..31bdae9
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp2.c
@@ -0,0 +1,675 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+ Carl Love <carll@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <elf.h>
+#include <link.h>
+
+#define PPC_FEATURE_HAS_VSX 0x00000080 /* Vector Scalar Extension. */
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+#define SH_0 0
+#define SH_1 1
+#define SH_2 15
+#define SH_3 63
+
+#define NUM_RND_MODES 8
+#define CONDREG_MASK 0x0f000000
+#define CONDREG_SHIFT 24
+
+static char ** my_envp;
+static inline char** __auxv_find(void)
+{
+ char **result = my_envp;
+ /* Scan over the env vector looking for the ending NULL */
+ for (; *result != NULL; ++result) {
+ }
+ /* Bump the pointer one more step, which should be the auxv. */
+ return ++result;
+}
+
+static unsigned long fetch_at_hwcap(void)
+{
+ static unsigned long auxv_hwcap = 0;
+ int i;
+ ElfW(auxv_t) * auxv_buf = NULL;
+
+ if (auxv_hwcap)
+ return auxv_hwcap;
+
+ auxv_buf = (ElfW(auxv_t)*) __auxv_find();
+ for (i = 0; auxv_buf[i].a_type != AT_NULL; i++)
+ if (auxv_buf[i].a_type == AT_HWCAP) {
+ auxv_hwcap = auxv_buf[i].a_un.a_val;
+ break;
+ }
+
+ return auxv_hwcap;
+}
+
+int get_vsx(void)
+{
+ /* Check to see if the AUX vector has the bit set indicating the HW
+ * supports the vsx instructions. This implies the processor is
+ * at least a POWER 7.
+ */
+ unsigned long hwcap;
+
+ hwcap = fetch_at_hwcap();
+ if ((hwcap & PPC_FEATURE_HAS_VSX) == PPC_FEATURE_HAS_VSX)
+ return 1;
+
+ return 0;
+}
+
+/* The assembly-level instructions being tested */
+static void _test_dscri (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+
+ case SH_1:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+
+ case SH_2:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+
+ case SH_3:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscri, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dscli (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+
+ case SH_1:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+
+ case SH_2:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+
+ case SH_3:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscli, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dctdp (void)
+{
+ __asm__ __volatile__ ("dctdp %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_drsp (void)
+{
+ __asm__ __volatile__ ("drsp %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dctfix (void)
+{
+ __asm__ __volatile__ ("dctfix %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+/* Power 7 and newer processors support this instruction */
+static void _test_dcffix (void)
+{
+ __asm__ __volatile__ ("dcffix %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dscriq (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+ case SH_1:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+ case SH_2:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+ case SH_3:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscriq, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dscliq (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+ case SH_1:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+ case SH_2:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+ case SH_3:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscliq, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dctqpq (void)
+{
+ __asm__ __volatile__ ("dctqpq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dctfixq (void)
+{
+ __asm__ __volatile__ ("dctfixq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_drdpq (void)
+{
+ __asm__ __volatile__ ("drdpq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dcffixq (void)
+{
+ __asm__ __volatile__ ("dcffixq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+typedef void (*test_func_t)();
+typedef void (*test_func_main_t)(int);
+typedef void (*test_func_shift_t)(int);
+typedef struct test_table
+{
+ test_func_main_t test_category;
+ char * name;
+} test_table_t;
+
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2f07c00000000000ULL, 0x000000000014c000ULL, //large number
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // a small number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long int64_vals[] = {
+ // I64 values
+ 0x0ULL, // zero
+ 0x1ULL, // one
+ 0xffffffffffffffffULL, // minus one
+ 0x2386f26fc0ffffULL, // 9999999999999999
+ 0xffdc790d903f0001ULL, // -9999999999999999
+ 0x462d53c8abac0ULL, // 1234567890124567
+ 0xfffb9d2ac3754540ULL, // -1234567890124567
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// large number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+/* Index pairs from dfp64_vals or dfp128_vals array to be used with
+ * dfp_two_arg_tests */
+static dfp_test_args_t int64_args_x1[] = {
+ /* {int64 input val, unused } */
+ {0, 0},
+ {1, 0},
+ {2, 0},
+ {3, 0},
+ {4, 0},
+ {5, 0},
+ {6, 0},
+};
+
+static dfp_test_args_t dfp_2args_x1[] = {
+ /* {dfp_arg, shift_arg} */
+ {0, SH_0},
+ {0, SH_1},
+ {0, SH_2},
+ {0, SH_3},
+ {5, SH_0},
+ {5, SH_1},
+ {5, SH_2},
+ {5, SH_3},
+ {6, SH_0},
+ {6, SH_1},
+ {6, SH_2},
+ {6, SH_3},
+ {7, SH_0},
+ {7, SH_1},
+ {7, SH_2},
+ {7, SH_3},
+ {10, SH_0},
+ {10, SH_1},
+ {10, SH_2},
+ {10, SH_3},
+ {13, SH_0},
+ {13, SH_1},
+ {13, SH_2},
+ {13, SH_3},
+};
+
+/* Index pairs from dfp64_vals array to be used with dfp_one_arg_tests */
+static dfp_test_args_t dfp_1args_x1[] = {
+ /* {dfp_arg, unused} */
+ {0, 0},
+ {1, 0},
+ {2, 0},
+ {3, 0},
+ {4, 0},
+ {5, 0},
+ {6, 0},
+ {7, 0},
+ {8, 0},
+ {9, 0},
+ {10, 0},
+ {11, 0},
+ {12, 0},
+ {13, 0},
+ {14, 0},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+ Bool cr_supported;
+} dfp_test_t;
+
+/* The dcffix and dcffixq tests are a little different in that they both take
+ * an I64 input.
+ */
+static dfp_test_t
+dfp_dcffix_dcffixq_tests[] = {
+ { &_test_dcffixq,"dcffixq", int64_args_x1, 7, QUAD_TEST, "I64S->D128", True},
+ /* Power 7 instruction */
+ { &_test_dcffix, "dcffix", int64_args_x1, 7, LONG_TEST, "I64S->D64", True},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static dfp_test_t
+dfp_one_arg_tests[] = {
+ { &_test_dctdp, "dctdp", dfp_1args_x1, 15, LONG_TEST, "D32->D64", True},
+ { &_test_drsp, "drsp", dfp_1args_x1, 15, LONG_TEST, "D64->D32", True},
+ { &_test_dctfix, "dctfix", dfp_1args_x1, 15, LONG_TEST, "D64->I64S", True},
+ { &_test_dctqpq, "dctqpq", dfp_1args_x1, 15, QUAD_TEST, "D64->D128", True},
+ { &_test_dctfixq,"dctfixq", dfp_1args_x1, 15, QUAD_TEST, "D128->I64S", True},
+ { &_test_drdpq, "drdpq", dfp_1args_x1, 15, QUAD_TEST, "D128->D64", True},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+
+static dfp_test_t
+dfp_two_arg_tests[] = {
+ { &_test_dscri, "dscri", dfp_2args_x1, 20, LONG_TEST, ">>", True},
+ { &_test_dscli, "dscli", dfp_2args_x1, 20, LONG_TEST, "<<", True},
+ { &_test_dscriq, "dscriq", dfp_2args_x1, 20, QUAD_TEST, ">>", True},
+ { &_test_dscliq, "dscliq", dfp_2args_x1, 20, QUAD_TEST, "<<", True},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+void set_rounding_mode(unsigned long long rnd_mode)
+{
+ double fpscr;
+ unsigned long long * hex_fpscr = (unsigned long long *)&fpscr;
+
+ *hex_fpscr = 0ULL;
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14));
+ fpscr = f14;
+ *hex_fpscr &= 0xFFFFFFF0FFFFFFFFULL;
+ *hex_fpscr |= (rnd_mode << 32);
+ f14 = fpscr;
+ SET_FPSCR_DRN;
+}
+
+static void test_dfp_one_arg_ops(int unused)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p;
+ double d0x, *d0xp;
+ unsigned long round_mode;
+ int k = 0;
+
+ u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_one_arg_tests[k].test_func)) {
+ int i;
+
+ for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
+ /* Do each test with each of the possible rounding modes */
+ dfp_test_t test_group = dfp_one_arg_tests[k];
+
+ printf("\ntest with rounding mode %lu \n", round_mode);
+ /* The set_rounding_mode() uses the global value f14. Call the
+ * function before setting up the test for the specific instruction
+ * to avoid avoid conflicts using f14.
+ */
+ set_rounding_mode(round_mode);
+
+ for (i = 0; i < test_group.num_tests; i++) {
+
+ if (test_group.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_group.targs[i].fra_idx];
+ } else {
+ u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
+ }
+
+ *(unsigned long long *)d0p = u0;
+ f14 = d0;
+ if (test_group.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f15 = d0x;
+ }
+
+ (*func)();
+ res = f18;
+
+ printf("%s %016llx", test_group.name, u0);
+
+ if (test_group.precision == LONG_TEST) {
+ printf(" %s => %016llx",
+ test_group.op, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx %s ==> %016llx %016llx",
+ u0x, test_group.op,
+ *((unsigned long long *)(&res)),
+ *((unsigned long long *)(&resx)));
+ }
+ printf("\n");
+ }
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_dfp_two_arg_ops(int unused)
+/* Shift instructions: first argument is the DFP source, second argument
+ * is 6 bit shift amount.
+ */
+{
+ test_func_shift_t func;
+ unsigned long long u0, u0x;
+ unsigned int shift_by;
+ double res, d0, *d0p;
+ double d0x, *d0xp;
+ unsigned long round_mode;
+ int k = 0;
+
+ u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_two_arg_tests[k].test_func)) {
+ int i;
+
+ for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
+ /* Do each test with each of the possible rounding modes */
+ dfp_test_t test_group = dfp_two_arg_tests[k];
+
+ printf("\ntest with rounding mode %lu \n", round_mode);
+
+ /* The set_rounding_mode() uses the global value f14. Call the
+ * function before setting up the test for the specific instruction
+ * to avoid avoid conflicts using f14.
+ */
+ set_rounding_mode(round_mode);
+
+ for (i = 0; i < test_group.num_tests; i++) {
+
+ shift_by = test_group.targs[i].frb_idx;
+
+ if (test_group.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_group.targs[i].fra_idx];
+ } else {
+ u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
+ }
+
+ *(unsigned long long *)d0p = u0;
+ f14 = d0;
+ if (test_group.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f15 = d0x;
+ }
+
+ (*func)(shift_by);
+ res = f18;
+
+ printf("%s %016llx", test_group.name, u0);
+
+ if (test_group.precision) {
+ printf(" %s %-3d => %016llx",
+ test_group.op, shift_by, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx %s %-3d ==> %016llx %016llx",
+ u0x, test_group.op, shift_by,
+ *((unsigned long long *)(&res)),
+ *((unsigned long long *)(&resx)));
+ }
+ printf("\n" );
+ }
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_dcffix_dcffixq(int has_vsx)
+{
+ test_func_t func;
+ unsigned long long u0;
+ double res, d0, *d0p;
+ int k = 0, round_mode;
+
+ d0p = &d0;
+
+
+ while ((func = dfp_dcffix_dcffixq_tests[k].test_func)) {
+ int i;
+
+ if ((!has_vsx) && (!strcmp("dcffix", dfp_dcffix_dcffixq_tests[k].name))) {
+ k++;
+ /* The test instruction is dcffix it is supported on POWER 7
+ * and newer processors. Skip if not POWER 7 or newer.
+ */
+ continue;
+ }
+
+ for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
+ /* Do each test with each of the possible rounding modes */
+ dfp_test_t test_group = dfp_dcffix_dcffixq_tests[k];
+
+ printf("\ntest with rounding mode %u \n", round_mode);
+
+ /* The set_rounding_mode() uses the global value f14. Call the
+ * function before setting up the test for the specific instruction
+ * to avoid avoid conflicts using f14.
+ */
+ set_rounding_mode(round_mode);
+
+ for (i = 0; i < test_group.num_tests; i++) {
+
+ /* The instructions take I64 inputs */
+ u0 = int64_vals[test_group.targs[i].fra_idx];
+
+ *(unsigned long long *)d0p = u0;
+ f14 = d0;
+
+ (*func)();
+ res = f18;
+
+ printf("%s %016llx", test_group.name, u0);
+
+ if (test_group.precision) {
+ printf(" %s => %016llx",
+ test_group.op, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %s ==> %016llx %016llx",
+ test_group.op,
+ *((unsigned long long *)(&res)),
+ *((unsigned long long *)(&resx)));
+ }
+ printf("\n" );
+ }
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static test_table_t
+all_tests[] =
+{
+ { &test_dfp_one_arg_ops,
+ "Test DFP fomat conversion instructions" },
+ { &test_dfp_two_arg_ops,
+ "Test DFP shift instructions" },
+ { test_dcffix_dcffixq,
+ "Test DCFFIX and DCFFIXQ instructions" },
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main(int argc, char ** argv, char ** envp) {
+#if defined(HAS_DFP)
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0, has_vsx;
+
+ /* If the processor has the VSX functionality then it is POWER 7
+ * or newer.
+ */
+ my_envp = envp;
+ has_vsx = get_vsx();
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)(has_vsx);
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc64/test_dfp2.stderr.exp b/main/none/tests/ppc64/test_dfp2.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp2.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc64/test_dfp2.stdout.exp b/main/none/tests/ppc64/test_dfp2.stdout.exp
new file mode 100644
index 0000000..50c3540
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp2.stdout.exp
@@ -0,0 +1,1679 @@
+Test DFP fomat conversion instructions
+
+test with rounding mode 0
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 1
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 2
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 3
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 4
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 5
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 6
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 7
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+
+test with rounding mode 0
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 1
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 2
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 3
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 4
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 5
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 6
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 7
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+
+test with rounding mode 0
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 1
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 2
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 3
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 4
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 5
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 6
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 7
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+
+test with rounding mode 0
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+
+test with rounding mode 0
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 1
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 2
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 3
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 4
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 5
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 6
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 7
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+
+test with rounding mode 0
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+Test DFP shift instructions
+
+test with rounding mode 0
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 1
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 2
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 3
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 4
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 5
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 6
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 7
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+
+test with rounding mode 0
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 1
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 2
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 3
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 4
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 5
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 6
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 7
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+Test DCFFIX and DCFFIXQ instructions
+
+test with rounding mode 0
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 1
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 2
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 3
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 4
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 5
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 6
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 7
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+
+test with rounding mode 0
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 1
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 2
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 3
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 4
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 5
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 6
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 7
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
diff --git a/main/none/tests/ppc64/test_dfp2.stdout.exp_Without_dcffix b/main/none/tests/ppc64/test_dfp2.stdout.exp_Without_dcffix
new file mode 100644
index 0000000..419a036
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp2.stdout.exp_Without_dcffix
@@ -0,0 +1,1606 @@
+Test DFP fomat conversion instructions
+
+test with rounding mode 0
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 1
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 2
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 3
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 4
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 5
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 6
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 7
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+
+test with rounding mode 0
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 1
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 2
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 3
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 4
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 5
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 6
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 7
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+
+test with rounding mode 0
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 1
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 2
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 3
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 4
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 5
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 6
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 7
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+
+test with rounding mode 0
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+
+test with rounding mode 0
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 1
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 2
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 3
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 4
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 5
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 6
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 7
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+
+test with rounding mode 0
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+Test DFP shift instructions
+
+test with rounding mode 0
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 1
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 2
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 3
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 4
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 5
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 6
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 7
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+
+test with rounding mode 0
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 1
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 2
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 3
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 4
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 5
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 6
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 7
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+Test DCFFIX and DCFFIXQ instructions
+
+test with rounding mode 0
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 1
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 2
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 3
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 4
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 5
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 6
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 7
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
diff --git a/main/none/tests/ppc64/test_dfp2.vgtest b/main/none/tests/ppc64/test_dfp2.vgtest
new file mode 100644
index 0000000..7fe6c16
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp2.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp2
diff --git a/main/none/tests/ppc64/test_dfp3.c b/main/none/tests/ppc64/test_dfp3.c
new file mode 100644
index 0000000..4fe3137
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp3.c
@@ -0,0 +1,1263 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+static void _test_drintx(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drintn(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+
+static void _test_diex(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("diex %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dxex(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("dxex %0, %1" : "=f" (f18) : "f" (f16));
+}
+
+static void _test_dcmpo(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpo 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpo 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpo 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpo 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpo 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpo 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpo 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpo 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dcmpu(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpu 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpu 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpu 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpu 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpu 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpu 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpu 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpu 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+// Quad instruction testing
+static void _test_drintxq(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drintnq(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_diexq(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("diexq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dxexq(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("dxexq %0, %1" : "=f" (f18) : "f" (f16));
+}
+
+static void _test_dcmpoq(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF );
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpoq 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpoq 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpoq 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpoq 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpoq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpoq 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpoq 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpoq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dcmpuq(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpuq 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpuq 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpuq 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpuq 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpuq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpuq 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpuq 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpuq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drrnd(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 31) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drrndq(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%dn", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dqua(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dquaq(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static int TE_vals[] = { -16, -2, 0, 5};
+#define TE_VAL_LEN sizeof(TE_vals)/sizeof(int)
+static Bool __is_TE_val(int x)
+{
+ int i;
+ for (i = 0; i < TE_VAL_LEN; i++) {
+ if (x==TE_vals[i])
+ return True;
+ }
+ return False;
+}
+
+static void _test_dquai(int TE, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || !__is_TE_val(TE)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", TE, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 3:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dquaiq(int TE, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || !__is_TE_val(TE)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", TE, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 3:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+
+typedef void (*test_func_t)(int a, int b);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+// Both Long and Quad arrays of DFP values should have the same length.
+// If that length is changed, t
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+} dfp_test_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_func_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+
+static dfp_one_arg_test_t
+dfp_quai_tests[] = {
+ { &_test_dquai, "dquai", LONG_TEST, "[QI]"},
+ { &_test_dquaiq, "dquaiq", QUAD_TEST, "[QI]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_quai_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp;
+
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_quai_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_quai_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int TE, RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (TE = 0; TE < TE_VAL_LEN; TE++) {
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(TE_vals[TE], RMC);
+ res = f18;
+ printf("%s (RMC=%2d, TE=%3d) %s %016llx", test_def.name, RMC,
+ TE_vals[TE], test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_test_t
+dfp_qua_tests[] = {
+ { &_test_dqua, "dqua", dfp_2args_x1, 25, LONG_TEST, "[Q]"},
+ { &_test_dquaq, "dquaq", dfp_2args_x1, 25, QUAD_TEST, "[Q]"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_qua_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double res, d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ int k = 0;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_qua_tests[k].test_func)) {
+ int i, RMC;
+ dfp_test_t test_def = dfp_qua_tests[k];
+
+ for (i = 0; i < test_def.num_tests; i++) {
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_def.targs[i].fra_idx];
+ u1 = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(-1, RMC);
+ res = f18;
+ printf("%s (RMC=%2d) %s %016llx", test_def.name, RMC, test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(", %016llx => %016llx\n", u1, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx, %016llx %016llx ==> %016llx %016llx\n",u0x, u1, u1x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_rrnd_tests[] = {
+ { &_test_drrnd, "drrnd", LONG_TEST, "[RR]"},
+ { &_test_drrndq, "drrndq", QUAD_TEST, "[RR]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_rrnd_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp, reference_sig, *reference_sig_p;
+ long long reference_sig_vals[] = {0ULL, 2ULL, 6ULL, 63ULL};
+ int num_reference_sig_vals = sizeof(reference_sig_vals)/sizeof(long long);
+
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ reference_sig_p = &reference_sig;
+
+ while ((func = dfp_rrnd_tests[k].test_func)) {
+ int i, j;
+ dfp_one_arg_test_t test_def = dfp_rrnd_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (j = 0; j < num_reference_sig_vals; j++) {
+ *(long long *)reference_sig_p = reference_sig_vals[j];
+ f14 = reference_sig;
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(-1, RMC);
+ res = f18;
+ printf("%s (RMC=%d, ref sig=%d) %s%016llx", test_def.name, RMC,
+ (int)reference_sig_vals[j], test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_xiex_tests[] = {
+ { &_test_diex, "diex", LONG_TEST, ">>"},
+ { &_test_diexq, "diexq", QUAD_TEST, ">>"},
+ { &_test_dxex, "dxex", LONG_TEST, "<<"},
+ { &_test_dxexq, "dxexq", QUAD_TEST, "<<"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_xiex_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp, target_exp, *target_exp_p;
+ /* The first two positions are placeholders and will be filled in later,
+ * based on the precision of the DFP argument.
+ */
+ long long target_exp_vals[] = {0ULL, 0ULL, 0ULL, -1ULL, -2ULL, -3ULL, -4ULL, -5ULL};
+ int num_exp_vals = sizeof(target_exp_vals)/sizeof(long long);
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ target_exp_p = &target_exp;
+
+ while ((func = dfp_xiex_tests[k].test_func)) {
+ int i;
+ Bool insert_insn = False;
+ dfp_one_arg_test_t test_def = dfp_xiex_tests[k];
+
+ if (!strncmp(test_def.name, "di", 2))
+ insert_insn = True;
+
+ if (test_def.precision == QUAD_TEST) {
+ target_exp_vals[0] = 12288ULL; // > max biased exponent
+ target_exp_vals[1] = 5235ULL;
+ } else {
+ target_exp_vals[0] = 768ULL; // > max biased exponent
+ target_exp_vals[1] = 355ULL;
+ }
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ unsigned int j;
+
+ if (test_def.precision == QUAD_TEST) {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ } else {
+ u0 = dfp64_vals[i];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ if (!insert_insn) {
+ // This is just for extract insns (dexex[q])
+ (*func)(0, 0);
+ res = f18;
+ printf("%s %s ", test_def.name, test_def.op);
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx => %016llx\n", u0,
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf("%016llx %016llx ==> %016llx %016llx\n", u0, u0x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ continue;
+ }
+ // The following for-loop is just for insert insns (diex[q])
+ for (j = 0; j < num_exp_vals; j++) {
+ *(long long *)target_exp_p = target_exp_vals[j];
+ f14 = target_exp;
+ (*func)(0, 0);
+ res = f18;
+ printf("%s %s %5d, ", test_def.name, test_def.op, (int)target_exp_vals[j]);
+
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx => %016llx\n", u0,
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf("%016llx %016llx ==> %016llx %016llx\n", u0, u0x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_one_arg_test_t
+dfp_rint_tests[] = {
+ { &_test_drintn, "drintn", LONG_TEST, "~"},
+ { &_test_drintnq, "drintnq", QUAD_TEST, "~"},
+ { &_test_drintx, "drintx", LONG_TEST, "~"},
+ { &_test_drintxq, "drintxq", QUAD_TEST, "~"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_rint_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp;
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_rint_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_rint_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int R, RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (R = 0; R < 2; R++) {
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(R, RMC);
+ res = f18;
+ printf("%s (RM=%d) %s%016llx", test_def.name, (RMC + (R << 2)), test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_test_t
+dfp_cmp_tests[] = {
+ { &_test_dcmpo, "dcmpo", dfp_2args_x1, 25, LONG_TEST, "<>"},
+ { &_test_dcmpoq, "dcmpoq", dfp_2args_x1, 25, QUAD_TEST, "<>"},
+ { &_test_dcmpu, "dcmpu", dfp_2args_x1, 25, LONG_TEST, "<>"},
+ { &_test_dcmpuq, "dcmpuq", dfp_2args_x1, 25, QUAD_TEST, "<>"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_cmp_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ /* BF is a 3-bit instruction field that indicates the CR field in which the
+ * result of the compare should be placed. We won't iterate through all
+ * 8 possible BF values since storing compare results to a given field is
+ * a well-tested mechanism in VEX. But we will test two BF values, just as
+ * a sniff-test.
+ */
+ int k = 0, BF;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_cmp_tests[k].test_func)) {
+ int i, repeat = 1;
+ dfp_test_t test_def = dfp_cmp_tests[k];
+ BF = 0;
+
+again:
+ for (i = 0; i < test_def.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_def.targs[i].fra_idx];
+ u1 = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, 0);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s %016llx", test_def.name, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" %s %016llx => %x (BF=%d)\n",
+ test_def.op, u1, condreg, BF);
+ } else {
+ printf(" %016llx %s %016llx %016llx ==> %x (BF=%d)\n",
+ u0x, test_def.op, u1, u1x,
+ condreg, BF);
+ }
+ }
+ if (repeat) {
+ repeat = 0;
+ BF = 5;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_cmp_ops,
+ "Test DFP compare instructions"},
+ { &test_dfp_rint_ops,
+ "Test DFP round instructions"},
+ { &test_dfp_xiex_ops,
+ "Test DFP insert/extract instructions"},
+ { &test_dfp_rrnd_ops,
+ "Test DFP reround instructions"},
+ { &test_dfp_qua_ops,
+ "Test DFP quantize instructions"},
+ { &test_dfp_quai_ops,
+ "Test DFP quantize immediate instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc64/test_dfp3.stderr.exp b/main/none/tests/ppc64/test_dfp3.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp3.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc64/test_dfp3.stdout.exp b/main/none/tests/ppc64/test_dfp3.stdout.exp
new file mode 100644
index 0000000..5c21dc0
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp3.stdout.exp
@@ -0,0 +1,2248 @@
+Test DFP compare instructions
+dcmpo 2234000000000e50 <> 223400000014c000 => 8 (BF=0)
+dcmpo a2340000000000e0 <> 223400000014c000 => 8 (BF=0)
+dcmpo 22240000000000cf <> a21400010a395bcf => 4 (BF=0)
+dcmpo 2234000000000e50 <> 000400000089b000 => 4 (BF=0)
+dcmpo a2340000000000e0 <> a21400010a395bcf => 8 (BF=0)
+dcmpo 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=0)
+dcmpo 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=0)
+dcmpo 2238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpo 2238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpo a238000000000000 <> 2234000000000e50 => 8 (BF=0)
+dcmpo a238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpo a238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpo 2238000000000000 <> a238000000000000 => 2 (BF=0)
+dcmpo fc00000000000000 <> f800000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> 223400000014c000 => 1 (BF=0)
+dcmpo fc00000000000000 <> 7800000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> fc00000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpo f800000000000000 <> f800000000000000 => 2 (BF=0)
+dcmpo f800000000000000 <> 22240000000000cf => 8 (BF=0)
+dcmpo f800000000000000 <> 7a34000000000000 => 8 (BF=0)
+dcmpo 2234000000000e50 <> 223400000014c000 => 8 (BF=5)
+dcmpo a2340000000000e0 <> 223400000014c000 => 8 (BF=5)
+dcmpo 22240000000000cf <> a21400010a395bcf => 4 (BF=5)
+dcmpo 2234000000000e50 <> 000400000089b000 => 4 (BF=5)
+dcmpo a2340000000000e0 <> a21400010a395bcf => 8 (BF=5)
+dcmpo 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=5)
+dcmpo 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=5)
+dcmpo 2238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpo 2238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpo a238000000000000 <> 2234000000000e50 => 8 (BF=5)
+dcmpo a238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpo a238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpo 2238000000000000 <> a238000000000000 => 2 (BF=5)
+dcmpo fc00000000000000 <> f800000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> 223400000014c000 => 1 (BF=5)
+dcmpo fc00000000000000 <> 7800000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> fc00000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpo f800000000000000 <> f800000000000000 => 2 (BF=5)
+dcmpo f800000000000000 <> 22240000000000cf => 8 (BF=5)
+dcmpo f800000000000000 <> 7a34000000000000 => 8 (BF=5)
+
+dcmpoq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=0)
+dcmpoq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=0)
+dcmpoq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=0)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=5)
+dcmpoq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=5)
+dcmpoq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=5)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=5)
+
+dcmpu 2234000000000e50 <> 223400000014c000 => 8 (BF=0)
+dcmpu a2340000000000e0 <> 223400000014c000 => 8 (BF=0)
+dcmpu 22240000000000cf <> a21400010a395bcf => 4 (BF=0)
+dcmpu 2234000000000e50 <> 000400000089b000 => 4 (BF=0)
+dcmpu a2340000000000e0 <> a21400010a395bcf => 8 (BF=0)
+dcmpu 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=0)
+dcmpu 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=0)
+dcmpu 2238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpu 2238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpu a238000000000000 <> 2234000000000e50 => 8 (BF=0)
+dcmpu a238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpu a238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpu 2238000000000000 <> a238000000000000 => 2 (BF=0)
+dcmpu fc00000000000000 <> f800000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> 223400000014c000 => 1 (BF=0)
+dcmpu fc00000000000000 <> 7800000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> fc00000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpu f800000000000000 <> f800000000000000 => 2 (BF=0)
+dcmpu f800000000000000 <> 22240000000000cf => 8 (BF=0)
+dcmpu f800000000000000 <> 7a34000000000000 => 8 (BF=0)
+dcmpu 2234000000000e50 <> 223400000014c000 => 8 (BF=5)
+dcmpu a2340000000000e0 <> 223400000014c000 => 8 (BF=5)
+dcmpu 22240000000000cf <> a21400010a395bcf => 4 (BF=5)
+dcmpu 2234000000000e50 <> 000400000089b000 => 4 (BF=5)
+dcmpu a2340000000000e0 <> a21400010a395bcf => 8 (BF=5)
+dcmpu 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=5)
+dcmpu 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=5)
+dcmpu 2238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpu 2238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpu a238000000000000 <> 2234000000000e50 => 8 (BF=5)
+dcmpu a238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpu a238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpu 2238000000000000 <> a238000000000000 => 2 (BF=5)
+dcmpu fc00000000000000 <> f800000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> 223400000014c000 => 1 (BF=5)
+dcmpu fc00000000000000 <> 7800000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> fc00000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpu f800000000000000 <> f800000000000000 => 2 (BF=5)
+dcmpu f800000000000000 <> 22240000000000cf => 8 (BF=5)
+dcmpu f800000000000000 <> 7a34000000000000 => 8 (BF=5)
+
+dcmpuq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=0)
+dcmpuq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=0)
+dcmpuq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=0)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=5)
+dcmpuq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=5)
+dcmpuq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=5)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=5)
+
+Test DFP round instructions
+drintn (RM=0) ~2234000000000e50 => 22380000000001c5
+drintn (RM=1) ~2234000000000e50 => 22380000000001c5
+drintn (RM=2) ~2234000000000e50 => 22380000000001c5
+drintn (RM=3) ~2234000000000e50 => 22380000000001c5
+drintn (RM=4) ~2234000000000e50 => 22380000000001c5
+drintn (RM=5) ~2234000000000e50 => 22380000000001c5
+drintn (RM=6) ~2234000000000e50 => 22380000000001c5
+drintn (RM=7) ~2234000000000e50 => 22380000000001c5
+drintn (RM=0) ~223400000014c000 => 2238000000028c00
+drintn (RM=1) ~223400000014c000 => 2238000000028c00
+drintn (RM=2) ~223400000014c000 => 2238000000028c00
+drintn (RM=3) ~223400000014c000 => 2238000000028c00
+drintn (RM=4) ~223400000014c000 => 2238000000028c00
+drintn (RM=5) ~223400000014c000 => 2238000000028c00
+drintn (RM=6) ~223400000014c000 => 2238000000028c00
+drintn (RM=7) ~223400000014c000 => 2238000000028c00
+drintn (RM=0) ~a2340000000000e0 => a238000000000016
+drintn (RM=1) ~a2340000000000e0 => a238000000000016
+drintn (RM=2) ~a2340000000000e0 => a238000000000016
+drintn (RM=3) ~a2340000000000e0 => a238000000000016
+drintn (RM=4) ~a2340000000000e0 => a238000000000016
+drintn (RM=5) ~a2340000000000e0 => a238000000000016
+drintn (RM=6) ~a2340000000000e0 => a238000000000016
+drintn (RM=7) ~a2340000000000e0 => a238000000000016
+drintn (RM=0) ~22240000000000cf => 2238000000000000
+drintn (RM=1) ~22240000000000cf => 2238000000000000
+drintn (RM=2) ~22240000000000cf => 2238000000000000
+drintn (RM=3) ~22240000000000cf => 2238000000000000
+drintn (RM=4) ~22240000000000cf => 2238000000000001
+drintn (RM=5) ~22240000000000cf => 2238000000000000
+drintn (RM=6) ~22240000000000cf => 2238000000000001
+drintn (RM=7) ~22240000000000cf => 2238000000000000
+drintn (RM=0) ~a21400010a395bcf => a238000000000004
+drintn (RM=1) ~a21400010a395bcf => a238000000000004
+drintn (RM=2) ~a21400010a395bcf => a238000000000004
+drintn (RM=3) ~a21400010a395bcf => a238000000000004
+drintn (RM=4) ~a21400010a395bcf => a238000000000004
+drintn (RM=5) ~a21400010a395bcf => a238000000000005
+drintn (RM=6) ~a21400010a395bcf => a238000000000005
+drintn (RM=7) ~a21400010a395bcf => a238000000000004
+drintn (RM=0) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=1) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=2) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=3) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=4) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=5) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=6) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=7) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=0) ~000400000089b000 => 2238000000000000
+drintn (RM=1) ~000400000089b000 => 2238000000000000
+drintn (RM=2) ~000400000089b000 => 2238000000000000
+drintn (RM=3) ~000400000089b000 => 2238000000000000
+drintn (RM=4) ~000400000089b000 => 2238000000000001
+drintn (RM=5) ~000400000089b000 => 2238000000000000
+drintn (RM=6) ~000400000089b000 => 2238000000000001
+drintn (RM=7) ~000400000089b000 => 2238000000000000
+drintn (RM=0) ~2238000000000000 => 2238000000000000
+drintn (RM=1) ~2238000000000000 => 2238000000000000
+drintn (RM=2) ~2238000000000000 => 2238000000000000
+drintn (RM=3) ~2238000000000000 => 2238000000000000
+drintn (RM=4) ~2238000000000000 => 2238000000000000
+drintn (RM=5) ~2238000000000000 => 2238000000000000
+drintn (RM=6) ~2238000000000000 => 2238000000000000
+drintn (RM=7) ~2238000000000000 => 2238000000000000
+drintn (RM=0) ~a238000000000000 => a238000000000000
+drintn (RM=1) ~a238000000000000 => a238000000000000
+drintn (RM=2) ~a238000000000000 => a238000000000000
+drintn (RM=3) ~a238000000000000 => a238000000000000
+drintn (RM=4) ~a238000000000000 => a238000000000000
+drintn (RM=5) ~a238000000000000 => a238000000000000
+drintn (RM=6) ~a238000000000000 => a238000000000000
+drintn (RM=7) ~a238000000000000 => a238000000000000
+drintn (RM=0) ~4248000000000000 => 4248000000000000
+drintn (RM=1) ~4248000000000000 => 4248000000000000
+drintn (RM=2) ~4248000000000000 => 4248000000000000
+drintn (RM=3) ~4248000000000000 => 4248000000000000
+drintn (RM=4) ~4248000000000000 => 4248000000000000
+drintn (RM=5) ~4248000000000000 => 4248000000000000
+drintn (RM=6) ~4248000000000000 => 4248000000000000
+drintn (RM=7) ~4248000000000000 => 4248000000000000
+drintn (RM=0) ~7e34000000000111 => 7c00000000000111
+drintn (RM=1) ~7e34000000000111 => 7c00000000000111
+drintn (RM=2) ~7e34000000000111 => 7c00000000000111
+drintn (RM=3) ~7e34000000000111 => 7c00000000000111
+drintn (RM=4) ~7e34000000000111 => 7c00000000000111
+drintn (RM=5) ~7e34000000000111 => 7c00000000000111
+drintn (RM=6) ~7e34000000000111 => 7c00000000000111
+drintn (RM=7) ~7e34000000000111 => 7c00000000000111
+drintn (RM=0) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=1) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=2) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=3) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=4) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=5) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=6) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=7) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=0) ~fc00000000000000 => fc00000000000000
+drintn (RM=1) ~fc00000000000000 => fc00000000000000
+drintn (RM=2) ~fc00000000000000 => fc00000000000000
+drintn (RM=3) ~fc00000000000000 => fc00000000000000
+drintn (RM=4) ~fc00000000000000 => fc00000000000000
+drintn (RM=5) ~fc00000000000000 => fc00000000000000
+drintn (RM=6) ~fc00000000000000 => fc00000000000000
+drintn (RM=7) ~fc00000000000000 => fc00000000000000
+drintn (RM=0) ~7800000000000000 => 7800000000000000
+drintn (RM=1) ~7800000000000000 => 7800000000000000
+drintn (RM=2) ~7800000000000000 => 7800000000000000
+drintn (RM=3) ~7800000000000000 => 7800000000000000
+drintn (RM=4) ~7800000000000000 => 7800000000000000
+drintn (RM=5) ~7800000000000000 => 7800000000000000
+drintn (RM=6) ~7800000000000000 => 7800000000000000
+drintn (RM=7) ~7800000000000000 => 7800000000000000
+drintn (RM=0) ~f800000000000000 => f800000000000000
+drintn (RM=1) ~f800000000000000 => f800000000000000
+drintn (RM=2) ~f800000000000000 => f800000000000000
+drintn (RM=3) ~f800000000000000 => f800000000000000
+drintn (RM=4) ~f800000000000000 => f800000000000000
+drintn (RM=5) ~f800000000000000 => f800000000000000
+drintn (RM=6) ~f800000000000000 => f800000000000000
+drintn (RM=7) ~f800000000000000 => f800000000000000
+drintn (RM=0) ~7a34000000000000 => 7800000000000000
+drintn (RM=1) ~7a34000000000000 => 7800000000000000
+drintn (RM=2) ~7a34000000000000 => 7800000000000000
+drintn (RM=3) ~7a34000000000000 => 7800000000000000
+drintn (RM=4) ~7a34000000000000 => 7800000000000000
+drintn (RM=5) ~7a34000000000000 => 7800000000000000
+drintn (RM=6) ~7a34000000000000 => 7800000000000000
+drintn (RM=7) ~7a34000000000000 => 7800000000000000
+
+drintnq (RM=0) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=1) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=2) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=3) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=4) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=5) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=6) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=7) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=0) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=1) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=2) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=3) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=4) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=5) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=6) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=7) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=0) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=1) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=2) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=3) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=4) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=5) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=6) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=7) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=0) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=1) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=2) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=3) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=4) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=5) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintnq (RM=6) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintnq (RM=7) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=0) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=5) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=7) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=1) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=2) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=3) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=4) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=5) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=6) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=7) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=0) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=1) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=2) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=3) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=4) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=5) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=6) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=7) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=0) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=1) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=2) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=3) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=4) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=5) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=6) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=7) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=0) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=1) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=2) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=3) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=4) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=5) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=6) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=7) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=0) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=1) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=2) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=3) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=4) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=5) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=6) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=7) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=0) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=1) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=2) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=3) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=4) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=5) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=6) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=7) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=0) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=1) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=2) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=3) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=4) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=5) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=6) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=7) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=0) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=1) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=2) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=3) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=4) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=5) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=6) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=7) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+drintx (RM=0) ~2234000000000e50 => 22380000000001c5
+drintx (RM=1) ~2234000000000e50 => 22380000000001c5
+drintx (RM=2) ~2234000000000e50 => 22380000000001c5
+drintx (RM=3) ~2234000000000e50 => 22380000000001c5
+drintx (RM=4) ~2234000000000e50 => 22380000000001c5
+drintx (RM=5) ~2234000000000e50 => 22380000000001c5
+drintx (RM=6) ~2234000000000e50 => 22380000000001c5
+drintx (RM=7) ~2234000000000e50 => 22380000000001c5
+drintx (RM=0) ~223400000014c000 => 2238000000028c00
+drintx (RM=1) ~223400000014c000 => 2238000000028c00
+drintx (RM=2) ~223400000014c000 => 2238000000028c00
+drintx (RM=3) ~223400000014c000 => 2238000000028c00
+drintx (RM=4) ~223400000014c000 => 2238000000028c00
+drintx (RM=5) ~223400000014c000 => 2238000000028c00
+drintx (RM=6) ~223400000014c000 => 2238000000028c00
+drintx (RM=7) ~223400000014c000 => 2238000000028c00
+drintx (RM=0) ~a2340000000000e0 => a238000000000016
+drintx (RM=1) ~a2340000000000e0 => a238000000000016
+drintx (RM=2) ~a2340000000000e0 => a238000000000016
+drintx (RM=3) ~a2340000000000e0 => a238000000000016
+drintx (RM=4) ~a2340000000000e0 => a238000000000016
+drintx (RM=5) ~a2340000000000e0 => a238000000000016
+drintx (RM=6) ~a2340000000000e0 => a238000000000016
+drintx (RM=7) ~a2340000000000e0 => a238000000000016
+drintx (RM=0) ~22240000000000cf => 2238000000000000
+drintx (RM=1) ~22240000000000cf => 2238000000000000
+drintx (RM=2) ~22240000000000cf => 2238000000000000
+drintx (RM=3) ~22240000000000cf => 2238000000000000
+drintx (RM=4) ~22240000000000cf => 2238000000000001
+drintx (RM=5) ~22240000000000cf => 2238000000000000
+drintx (RM=6) ~22240000000000cf => 2238000000000001
+drintx (RM=7) ~22240000000000cf => 2238000000000000
+drintx (RM=0) ~a21400010a395bcf => a238000000000004
+drintx (RM=1) ~a21400010a395bcf => a238000000000004
+drintx (RM=2) ~a21400010a395bcf => a238000000000004
+drintx (RM=3) ~a21400010a395bcf => a238000000000004
+drintx (RM=4) ~a21400010a395bcf => a238000000000004
+drintx (RM=5) ~a21400010a395bcf => a238000000000005
+drintx (RM=6) ~a21400010a395bcf => a238000000000005
+drintx (RM=7) ~a21400010a395bcf => a238000000000004
+drintx (RM=0) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=1) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=2) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=3) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=4) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=5) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=6) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=7) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=0) ~000400000089b000 => 2238000000000000
+drintx (RM=1) ~000400000089b000 => 2238000000000000
+drintx (RM=2) ~000400000089b000 => 2238000000000000
+drintx (RM=3) ~000400000089b000 => 2238000000000000
+drintx (RM=4) ~000400000089b000 => 2238000000000001
+drintx (RM=5) ~000400000089b000 => 2238000000000000
+drintx (RM=6) ~000400000089b000 => 2238000000000001
+drintx (RM=7) ~000400000089b000 => 2238000000000000
+drintx (RM=0) ~2238000000000000 => 2238000000000000
+drintx (RM=1) ~2238000000000000 => 2238000000000000
+drintx (RM=2) ~2238000000000000 => 2238000000000000
+drintx (RM=3) ~2238000000000000 => 2238000000000000
+drintx (RM=4) ~2238000000000000 => 2238000000000000
+drintx (RM=5) ~2238000000000000 => 2238000000000000
+drintx (RM=6) ~2238000000000000 => 2238000000000000
+drintx (RM=7) ~2238000000000000 => 2238000000000000
+drintx (RM=0) ~a238000000000000 => a238000000000000
+drintx (RM=1) ~a238000000000000 => a238000000000000
+drintx (RM=2) ~a238000000000000 => a238000000000000
+drintx (RM=3) ~a238000000000000 => a238000000000000
+drintx (RM=4) ~a238000000000000 => a238000000000000
+drintx (RM=5) ~a238000000000000 => a238000000000000
+drintx (RM=6) ~a238000000000000 => a238000000000000
+drintx (RM=7) ~a238000000000000 => a238000000000000
+drintx (RM=0) ~4248000000000000 => 4248000000000000
+drintx (RM=1) ~4248000000000000 => 4248000000000000
+drintx (RM=2) ~4248000000000000 => 4248000000000000
+drintx (RM=3) ~4248000000000000 => 4248000000000000
+drintx (RM=4) ~4248000000000000 => 4248000000000000
+drintx (RM=5) ~4248000000000000 => 4248000000000000
+drintx (RM=6) ~4248000000000000 => 4248000000000000
+drintx (RM=7) ~4248000000000000 => 4248000000000000
+drintx (RM=0) ~7e34000000000111 => 7c00000000000111
+drintx (RM=1) ~7e34000000000111 => 7c00000000000111
+drintx (RM=2) ~7e34000000000111 => 7c00000000000111
+drintx (RM=3) ~7e34000000000111 => 7c00000000000111
+drintx (RM=4) ~7e34000000000111 => 7c00000000000111
+drintx (RM=5) ~7e34000000000111 => 7c00000000000111
+drintx (RM=6) ~7e34000000000111 => 7c00000000000111
+drintx (RM=7) ~7e34000000000111 => 7c00000000000111
+drintx (RM=0) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=1) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=2) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=3) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=4) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=5) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=6) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=7) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=0) ~fc00000000000000 => fc00000000000000
+drintx (RM=1) ~fc00000000000000 => fc00000000000000
+drintx (RM=2) ~fc00000000000000 => fc00000000000000
+drintx (RM=3) ~fc00000000000000 => fc00000000000000
+drintx (RM=4) ~fc00000000000000 => fc00000000000000
+drintx (RM=5) ~fc00000000000000 => fc00000000000000
+drintx (RM=6) ~fc00000000000000 => fc00000000000000
+drintx (RM=7) ~fc00000000000000 => fc00000000000000
+drintx (RM=0) ~7800000000000000 => 7800000000000000
+drintx (RM=1) ~7800000000000000 => 7800000000000000
+drintx (RM=2) ~7800000000000000 => 7800000000000000
+drintx (RM=3) ~7800000000000000 => 7800000000000000
+drintx (RM=4) ~7800000000000000 => 7800000000000000
+drintx (RM=5) ~7800000000000000 => 7800000000000000
+drintx (RM=6) ~7800000000000000 => 7800000000000000
+drintx (RM=7) ~7800000000000000 => 7800000000000000
+drintx (RM=0) ~f800000000000000 => f800000000000000
+drintx (RM=1) ~f800000000000000 => f800000000000000
+drintx (RM=2) ~f800000000000000 => f800000000000000
+drintx (RM=3) ~f800000000000000 => f800000000000000
+drintx (RM=4) ~f800000000000000 => f800000000000000
+drintx (RM=5) ~f800000000000000 => f800000000000000
+drintx (RM=6) ~f800000000000000 => f800000000000000
+drintx (RM=7) ~f800000000000000 => f800000000000000
+drintx (RM=0) ~7a34000000000000 => 7800000000000000
+drintx (RM=1) ~7a34000000000000 => 7800000000000000
+drintx (RM=2) ~7a34000000000000 => 7800000000000000
+drintx (RM=3) ~7a34000000000000 => 7800000000000000
+drintx (RM=4) ~7a34000000000000 => 7800000000000000
+drintx (RM=5) ~7a34000000000000 => 7800000000000000
+drintx (RM=6) ~7a34000000000000 => 7800000000000000
+drintx (RM=7) ~7a34000000000000 => 7800000000000000
+
+drintxq (RM=0) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=1) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=2) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=3) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=4) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=5) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=6) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=7) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=0) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=1) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=2) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=3) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=4) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=5) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=6) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=7) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=0) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=1) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=2) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=3) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=4) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=5) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=6) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=7) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=0) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=1) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=2) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=3) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=4) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=5) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintxq (RM=6) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintxq (RM=7) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=0) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=5) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=7) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=1) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=2) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=3) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=4) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=5) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=6) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=7) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=0) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=1) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=2) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=3) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=4) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=5) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=6) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=7) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=0) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=1) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=2) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=3) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=4) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=5) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=6) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=7) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=0) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=1) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=2) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=3) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=4) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=5) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=6) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=7) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=0) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=1) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=2) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=3) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=4) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=5) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=6) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=7) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=0) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=1) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=2) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=3) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=4) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=5) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=6) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=7) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=0) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=1) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=2) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=3) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=4) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=5) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=6) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=7) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=0) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=1) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=2) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=3) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=4) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=5) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=6) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=7) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP insert/extract instructions
+diex >> 768, 2234000000000e50 => 7c00000000000e50
+diex >> 355, 2234000000000e50 => 218c000000000e50
+diex >> 0, 2234000000000e50 => 0000000000000e50
+diex >> -1, 2234000000000e50 => 7800000000000e50
+diex >> -2, 2234000000000e50 => 7c00000000000e50
+diex >> -3, 2234000000000e50 => 7e00000000000e50
+diex >> -4, 2234000000000e50 => 7c00000000000e50
+diex >> -5, 2234000000000e50 => 7c00000000000e50
+diex >> 768, 223400000014c000 => 7c0000000014c000
+diex >> 355, 223400000014c000 => 218c00000014c000
+diex >> 0, 223400000014c000 => 000000000014c000
+diex >> -1, 223400000014c000 => 780000000014c000
+diex >> -2, 223400000014c000 => 7c0000000014c000
+diex >> -3, 223400000014c000 => 7e0000000014c000
+diex >> -4, 223400000014c000 => 7c0000000014c000
+diex >> -5, 223400000014c000 => 7c0000000014c000
+diex >> 768, a2340000000000e0 => fc000000000000e0
+diex >> 355, a2340000000000e0 => a18c0000000000e0
+diex >> 0, a2340000000000e0 => 80000000000000e0
+diex >> -1, a2340000000000e0 => f8000000000000e0
+diex >> -2, a2340000000000e0 => fc000000000000e0
+diex >> -3, a2340000000000e0 => fe000000000000e0
+diex >> -4, a2340000000000e0 => fc000000000000e0
+diex >> -5, a2340000000000e0 => fc000000000000e0
+diex >> 768, 22240000000000cf => 7c000000000000cf
+diex >> 355, 22240000000000cf => 218c0000000000cf
+diex >> 0, 22240000000000cf => 00000000000000cf
+diex >> -1, 22240000000000cf => 78000000000000cf
+diex >> -2, 22240000000000cf => 7c000000000000cf
+diex >> -3, 22240000000000cf => 7e000000000000cf
+diex >> -4, 22240000000000cf => 7c000000000000cf
+diex >> -5, 22240000000000cf => 7c000000000000cf
+diex >> 768, a21400010a395bcf => fc0000010a395bcf
+diex >> 355, a21400010a395bcf => a18c00010a395bcf
+diex >> 0, a21400010a395bcf => 800000010a395bcf
+diex >> -1, a21400010a395bcf => f80000010a395bcf
+diex >> -2, a21400010a395bcf => fc0000010a395bcf
+diex >> -3, a21400010a395bcf => fe0000010a395bcf
+diex >> -4, a21400010a395bcf => fc0000010a395bcf
+diex >> -5, a21400010a395bcf => fc0000010a395bcf
+diex >> 768, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> 355, 6e4d3f1f534acdd4 => 6d8d3f1f534acdd4
+diex >> 0, 6e4d3f1f534acdd4 => 64013f1f534acdd4
+diex >> -1, 6e4d3f1f534acdd4 => 78013f1f534acdd4
+diex >> -2, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> -3, 6e4d3f1f534acdd4 => 7e013f1f534acdd4
+diex >> -4, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> -5, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> 768, 000400000089b000 => 7c0000000089b000
+diex >> 355, 000400000089b000 => 218c00000089b000
+diex >> 0, 000400000089b000 => 000000000089b000
+diex >> -1, 000400000089b000 => 780000000089b000
+diex >> -2, 000400000089b000 => 7c0000000089b000
+diex >> -3, 000400000089b000 => 7e0000000089b000
+diex >> -4, 000400000089b000 => 7c0000000089b000
+diex >> -5, 000400000089b000 => 7c0000000089b000
+diex >> 768, 2238000000000000 => 7c00000000000000
+diex >> 355, 2238000000000000 => 218c000000000000
+diex >> 0, 2238000000000000 => 0000000000000000
+diex >> -1, 2238000000000000 => 7800000000000000
+diex >> -2, 2238000000000000 => 7c00000000000000
+diex >> -3, 2238000000000000 => 7e00000000000000
+diex >> -4, 2238000000000000 => 7c00000000000000
+diex >> -5, 2238000000000000 => 7c00000000000000
+diex >> 768, a238000000000000 => fc00000000000000
+diex >> 355, a238000000000000 => a18c000000000000
+diex >> 0, a238000000000000 => 8000000000000000
+diex >> -1, a238000000000000 => f800000000000000
+diex >> -2, a238000000000000 => fc00000000000000
+diex >> -3, a238000000000000 => fe00000000000000
+diex >> -4, a238000000000000 => fc00000000000000
+diex >> -5, a238000000000000 => fc00000000000000
+diex >> 768, 4248000000000000 => 7c00000000000000
+diex >> 355, 4248000000000000 => 218c000000000000
+diex >> 0, 4248000000000000 => 0000000000000000
+diex >> -1, 4248000000000000 => 7800000000000000
+diex >> -2, 4248000000000000 => 7c00000000000000
+diex >> -3, 4248000000000000 => 7e00000000000000
+diex >> -4, 4248000000000000 => 7c00000000000000
+diex >> -5, 4248000000000000 => 7c00000000000000
+diex >> 768, 7e34000000000111 => 7c00000000000111
+diex >> 355, 7e34000000000111 => 218c000000000111
+diex >> 0, 7e34000000000111 => 0000000000000111
+diex >> -1, 7e34000000000111 => 7800000000000111
+diex >> -2, 7e34000000000111 => 7c00000000000111
+diex >> -3, 7e34000000000111 => 7e00000000000111
+diex >> -4, 7e34000000000111 => 7c00000000000111
+diex >> -5, 7e34000000000111 => 7c00000000000111
+diex >> 768, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> 355, fe000000d0e0a0d0 => a18c0000d0e0a0d0
+diex >> 0, fe000000d0e0a0d0 => 80000000d0e0a0d0
+diex >> -1, fe000000d0e0a0d0 => f8000000d0e0a0d0
+diex >> -2, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> -3, fe000000d0e0a0d0 => fe000000d0e0a0d0
+diex >> -4, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> -5, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> 768, fc00000000000000 => fc00000000000000
+diex >> 355, fc00000000000000 => a18c000000000000
+diex >> 0, fc00000000000000 => 8000000000000000
+diex >> -1, fc00000000000000 => f800000000000000
+diex >> -2, fc00000000000000 => fc00000000000000
+diex >> -3, fc00000000000000 => fe00000000000000
+diex >> -4, fc00000000000000 => fc00000000000000
+diex >> -5, fc00000000000000 => fc00000000000000
+diex >> 768, 7800000000000000 => 7c00000000000000
+diex >> 355, 7800000000000000 => 218c000000000000
+diex >> 0, 7800000000000000 => 0000000000000000
+diex >> -1, 7800000000000000 => 7800000000000000
+diex >> -2, 7800000000000000 => 7c00000000000000
+diex >> -3, 7800000000000000 => 7e00000000000000
+diex >> -4, 7800000000000000 => 7c00000000000000
+diex >> -5, 7800000000000000 => 7c00000000000000
+diex >> 768, f800000000000000 => fc00000000000000
+diex >> 355, f800000000000000 => a18c000000000000
+diex >> 0, f800000000000000 => 8000000000000000
+diex >> -1, f800000000000000 => f800000000000000
+diex >> -2, f800000000000000 => fc00000000000000
+diex >> -3, f800000000000000 => fe00000000000000
+diex >> -4, f800000000000000 => fc00000000000000
+diex >> -5, f800000000000000 => fc00000000000000
+diex >> 768, 7a34000000000000 => 7c00000000000000
+diex >> 355, 7a34000000000000 => 218c000000000000
+diex >> 0, 7a34000000000000 => 0000000000000000
+diex >> -1, 7a34000000000000 => 7800000000000000
+diex >> -2, 7a34000000000000 => 7c00000000000000
+diex >> -3, 7a34000000000000 => 7e00000000000000
+diex >> -4, 7a34000000000000 => 7c00000000000000
+diex >> -5, 7a34000000000000 => 7c00000000000000
+
+diexq >> 12288, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> 5235, 2207c00000000000 0000000000000e50 ==> 211cc00000000000 0000000000000e50
+diexq >> 0, 2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000000e50
+diexq >> -1, 2207c00000000000 0000000000000e50 ==> 7800000000000000 0000000000000e50
+diexq >> -2, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> -3, 2207c00000000000 0000000000000e50 ==> 7e00000000000000 0000000000000e50
+diexq >> -4, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> -5, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> 12288, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> 5235, 2207c00000000000 000000000014c000 ==> 211cc00000000000 000000000014c000
+diexq >> 0, 2207c00000000000 000000000014c000 ==> 0000000000000000 000000000014c000
+diexq >> -1, 2207c00000000000 000000000014c000 ==> 7800000000000000 000000000014c000
+diexq >> -2, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> -3, 2207c00000000000 000000000014c000 ==> 7e00000000000000 000000000014c000
+diexq >> -4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> -5, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> 12288, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> 5235, a207c00000000000 00000000000000e0 ==> a11cc00000000000 00000000000000e0
+diexq >> 0, a207c00000000000 00000000000000e0 ==> 8000000000000000 00000000000000e0
+diexq >> -1, a207c00000000000 00000000000000e0 ==> f800000000000000 00000000000000e0
+diexq >> -2, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> -3, a207c00000000000 00000000000000e0 ==> fe00000000000000 00000000000000e0
+diexq >> -4, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> -5, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> 12288, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> 5235, 2206c00000000000 00000000000000cf ==> 211cc00000000000 00000000000000cf
+diexq >> 0, 2206c00000000000 00000000000000cf ==> 0000000000000000 00000000000000cf
+diexq >> -1, 2206c00000000000 00000000000000cf ==> 7800000000000000 00000000000000cf
+diexq >> -2, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> -3, 2206c00000000000 00000000000000cf ==> 7e00000000000000 00000000000000cf
+diexq >> -4, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> -5, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> 12288, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> 5235, a205c00000000000 000000010a395bcf ==> a11cc00000000000 000000010a395bcf
+diexq >> 0, a205c00000000000 000000010a395bcf ==> 8000000000000000 000000010a395bcf
+diexq >> -1, a205c00000000000 000000010a395bcf ==> f800000000000000 000000010a395bcf
+diexq >> -2, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> -3, a205c00000000000 000000010a395bcf ==> fe00000000000000 000000010a395bcf
+diexq >> -4, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> -5, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> 12288, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> 5235, 6209400000fd0000 00253f1f534acdd4 ==> 691cc00000fd0000 00253f1f534acdd4
+diexq >> 0, 6209400000fd0000 00253f1f534acdd4 ==> 6000000000fd0000 00253f1f534acdd4
+diexq >> -1, 6209400000fd0000 00253f1f534acdd4 ==> 7800000000fd0000 00253f1f534acdd4
+diexq >> -2, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> -3, 6209400000fd0000 00253f1f534acdd4 ==> 7e00000000fd0000 00253f1f534acdd4
+diexq >> -4, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> -5, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> 12288, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> 5235, 000400000089b000 0a6000d000000049 ==> 211cc0000089b000 0a6000d000000049
+diexq >> 0, 000400000089b000 0a6000d000000049 ==> 000000000089b000 0a6000d000000049
+diexq >> -1, 000400000089b000 0a6000d000000049 ==> 780000000089b000 0a6000d000000049
+diexq >> -2, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> -3, 000400000089b000 0a6000d000000049 ==> 7e0000000089b000 0a6000d000000049
+diexq >> -4, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> -5, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> 12288, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 2208000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 2208000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 2208000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, a208000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, a208000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, a208000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, a208000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, a248000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, a248000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, a248000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, a248000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 7c00000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 7c00000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 7c00000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> 5235, fc00000000000000 c00100035b007700 ==> a11cc00000000000 c00100035b007700
+diexq >> 0, fc00000000000000 c00100035b007700 ==> 8000000000000000 c00100035b007700
+diexq >> -1, fc00000000000000 c00100035b007700 ==> f800000000000000 c00100035b007700
+diexq >> -2, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> -3, fc00000000000000 c00100035b007700 ==> fe00000000000000 c00100035b007700
+diexq >> -4, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> -5, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> 12288, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> 5235, 7e00000000000000 fe000000d0e0a0d0 ==> 211cc00000000000 fe000000d0e0a0d0
+diexq >> 0, 7e00000000000000 fe000000d0e0a0d0 ==> 0000000000000000 fe000000d0e0a0d0
+diexq >> -1, 7e00000000000000 fe000000d0e0a0d0 ==> 7800000000000000 fe000000d0e0a0d0
+diexq >> -2, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> -3, 7e00000000000000 fe000000d0e0a0d0 ==> 7e00000000000000 fe000000d0e0a0d0
+diexq >> -4, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> -5, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> 12288, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 7800000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 7800000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, f800000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, f800000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, f800000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, f900000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, f900000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, f900000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+
+dxex << 2234000000000e50 => 000000000000018d
+dxex << 223400000014c000 => 000000000000018d
+dxex << a2340000000000e0 => 000000000000018d
+dxex << 22240000000000cf => 0000000000000189
+dxex << a21400010a395bcf => 0000000000000185
+dxex << 6e4d3f1f534acdd4 => 0000000000000193
+dxex << 000400000089b000 => 0000000000000001
+dxex << 2238000000000000 => 000000000000018e
+dxex << a238000000000000 => 000000000000018e
+dxex << 4248000000000000 => 0000000000000292
+dxex << 7e34000000000111 => fffffffffffffffd
+dxex << fe000000d0e0a0d0 => fffffffffffffffd
+dxex << fc00000000000000 => fffffffffffffffe
+dxex << 7800000000000000 => ffffffffffffffff
+dxex << f800000000000000 => ffffffffffffffff
+dxex << 7a34000000000000 => ffffffffffffffff
+
+dxexq << 2207c00000000000 0000000000000e50 ==> 000000000000181f 0000000000000000
+dxexq << 2207c00000000000 000000000014c000 ==> 000000000000181f 0000000000000000
+dxexq << a207c00000000000 00000000000000e0 ==> 000000000000181f 0000000000000000
+dxexq << 2206c00000000000 00000000000000cf ==> 000000000000181b 0000000000000000
+dxexq << a205c00000000000 000000010a395bcf ==> 0000000000001817 0000000000000000
+dxexq << 6209400000fd0000 00253f1f534acdd4 ==> 0000000000000825 0000000000000000
+dxexq << 000400000089b000 0a6000d000000049 ==> 0000000000000010 0000000000000000
+dxexq << 2208000000000000 0000000000000000 ==> 0000000000001820 0000000000000000
+dxexq << a208000000000000 0000000000000000 ==> 0000000000001820 0000000000000000
+dxexq << a248000000000000 0000000000000000 ==> 0000000000001920 0000000000000000
+dxexq << 7c00000000000000 0000000000000000 ==> fffffffffffffffe 0000000000000000
+dxexq << fc00000000000000 c00100035b007700 ==> fffffffffffffffe 0000000000000000
+dxexq << 7e00000000000000 fe000000d0e0a0d0 ==> fffffffffffffffd 0000000000000000
+dxexq << 7800000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+dxexq << f800000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+dxexq << f900000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+
+Test DFP reround instructions
+drrnd (RMC=0, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=1, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=2, ref sig=2) [RR]2234000000000e50 => 223c000000000035
+drrnd (RMC=3, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=0, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=1, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=2, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=3, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=0, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=1, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=2, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=3, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=0, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=1, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=2, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=3, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=0, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=1, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=2, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=3, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=0, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=1, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=2, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=3, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=0, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=1, ref sig=2) [RR]22240000000000cf => 2228000000000018
+drrnd (RMC=2, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=3, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=0, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=1, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=2, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=3, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=0, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=1, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=2, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=3, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=0, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=1, ref sig=6) [RR]a21400010a395bcf => a2240000000849c5
+drrnd (RMC=2, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=3, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=0, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=1, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=2, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=3, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=0, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=1, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=2, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=3, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=0, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=1, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=2, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=3, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=0, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=1, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=2, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=3, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=0, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=1, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=2, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=3, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=0, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=1, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=2, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=3, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=0, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=1, ref sig=2) [RR]000400000089b000 => 001800000000004e
+drrnd (RMC=2, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=3, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=0, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=1, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=2, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=3, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=0, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=1, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=2, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=3, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=0, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+
+drrndq (RMC=0, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=1, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=2, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000035
+drrndq (RMC=3, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=0, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=1, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=2, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=3, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=0, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=1, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=2, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=3, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=0, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=1, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=2, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=3, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=0, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=1, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=2, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=3, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=0, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=1, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=2, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=3, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=0, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=1, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000018
+drrndq (RMC=2, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=3, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=0, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=1, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=2, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=3, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=0, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=1, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=2, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=3, ref sig=2) [RR]a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+drrndq (RMC=0, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+drrndq (RMC=1, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c5
+drrndq (RMC=2, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+drrndq (RMC=3, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+drrndq (RMC=0, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=1, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=2, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=3, ref sig=63) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=0, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=1, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=2, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=3, ref sig=0) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=0, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=1, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=2, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=3, ref sig=2) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0211400000000000 000000000000000a
+drrndq (RMC=0, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=1, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=2, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=3, ref sig=6) [RR]6209400000fd0000 00253f1f534acdd4 ==> 0210400000000000 0000000000003000
+drrndq (RMC=0, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=1, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=2, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=3, ref sig=63) [RR]6209400000fd0000 00253f1f534acdd4 ==> 6209400000fd0000 00253f1f534acdd4
+drrndq (RMC=0, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=1, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=2, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=3, ref sig=0) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=0, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000011
+drrndq (RMC=1, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000010
+drrndq (RMC=2, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000011
+drrndq (RMC=3, ref sig=2) [RR]000400000089b000 0a6000d000000049 ==> 000a400000000000 0000000000000011
+drrndq (RMC=0, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=1, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=2, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=3, ref sig=6) [RR]000400000089b000 0a6000d000000049 ==> 0009400000000000 00000000000226c0
+drrndq (RMC=0, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=1, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=2, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=3, ref sig=63) [RR]000400000089b000 0a6000d000000049 ==> 000400000089b000 0a6000d000000049
+drrndq (RMC=0, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=0) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=2) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=6) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=1, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=2, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=3, ref sig=63) [RR]fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drrndq (RMC=0, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=0) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=2) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=6) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=1, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=2, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=3, ref sig=63) [RR]7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drrndq (RMC=0, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP quantize instructions
+dqua (RMC= 0) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 1) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 2) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 3) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 0) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 1) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 2) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 3) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 0) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 1) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c5
+dqua (RMC= 2) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 3) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 0) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 1) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 2) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 3) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 0) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 1) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 2) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 3) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 0) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 1) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 2) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 3) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 0) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 1) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 2) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 3) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 0) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 1) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 2) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 3) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 0) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 1) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 2) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 3) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 0) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 1) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 2) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 3) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 0) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 1) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 2) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 3) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 0) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 1) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 2) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 3) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 0) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 1) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 2) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 3) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 0) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 1) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 2) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 3) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 0) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 1) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 2) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 3) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 0) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 1) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 2) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 3) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+
+dquaq (RMC= 0) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 1) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 2) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 3) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 0) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 1) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 2) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 3) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 0) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 1) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c5
+dquaq (RMC= 2) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 3) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 0) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 1) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 2) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 3) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 0) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 1) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 2) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 3) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 0) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP quantize immediate instructions
+dquai (RMC= 0, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 1, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 2, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 3, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 0, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 1, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 2, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 3, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 0, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 1, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 2, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 3, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 0, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 1, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 2, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 3, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 0, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 1, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 2, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 3, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 0, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 1, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 2, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 3, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 0, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 1, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 2, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 3, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 0, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 1, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 2, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 3, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 0, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 1, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 2, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 3, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 0, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 1, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 2, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 3, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 0, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 1, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 2, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 3, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 0, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 1, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 2, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 3, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 0, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 1, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 2, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 3, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 0, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 1, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 2, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 3, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 0, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+
+dquaiq (RMC= 0, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 1, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 2, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 3, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 0, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 1, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 2, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 3, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 0, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 1, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 2, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 3, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 0, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 1, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 2, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 3, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 0, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 1, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 2, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 3, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 0, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 1, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 2, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 3, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 0, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 1, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 2, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 3, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 0, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 1, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 2, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 3, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 0, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 1, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 2, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 3, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 0, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 1, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 2, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 3, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 0, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 1, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 2, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 3, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 0, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+
diff --git a/main/none/tests/ppc64/test_dfp3.vgtest b/main/none/tests/ppc64/test_dfp3.vgtest
new file mode 100644
index 0000000..39168a3
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp3.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp3
diff --git a/main/none/tests/ppc64/test_dfp4.c b/main/none/tests/ppc64/test_dfp4.c
new file mode 100644
index 0000000..7cd8721
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp4.c
@@ -0,0 +1,626 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+typedef union stuff {
+ _Decimal64 dec_val;
+ _Decimal128 dec_val128;
+ unsigned long long u64_val;
+ struct {
+ unsigned long long valu;
+ unsigned long long vall;
+ } u128;
+} dfp_val_t;
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+
+/* In _test_dtstdc[q], DCM can be one of 6 possible data classes, numbered 0-5.
+ * In reality, DCM is a 6-bit mask field. We just test the individual values
+ * and assume that masking multiple values would work OK.
+ * BF is the condition register bit field which can range from 0-7. But for
+ * testing purposes, we only use BF values of '0' and '5'.
+ */
+static void _test_dtstdc(int BF, int DCM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
+{
+ _Decimal64 f14 = val1.dec_val;
+ if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM);
+ return;
+ }
+ switch (DCM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dtstdcq(int BF, int DCM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
+{
+ _Decimal128 f14 = val1.dec_val128;
+ if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM);
+ return;
+ }
+ switch (DCM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+/* In _test_dtstdg[q], DGM can be one of 6 possible data groups, numbered 0-5.
+ * In reality, DGM is a 6-bit mask field. We just test the individual values
+ * and assume that masking multiple values would work OK.
+ * BF is the condition register bit field which can range from 0-7. But for
+ * testing purposes, we only use BF values of '0' and '5'.
+ */
+static void _test_dtstdg(int BF, int DGM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
+{
+ _Decimal64 f14 = val1.dec_val;
+ if (DGM < 0 || DGM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DGM);
+ return;
+ }
+ switch (DGM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dtstdgq(int BF, int DGM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
+{
+ _Decimal128 f14 = val1.dec_val128;
+ if (DGM < 0 || DGM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DGM);
+ return;
+ }
+ switch (DGM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+/* In _test_dtstex[q], BF is the condition register bit field indicating the
+ * CR field in which the result of the test should be placed. BF can range
+ * from 0-7, but for testing purposes, we only use BF values of '4' and '7'.
+ */
+static void
+_test_dtstex(int BF, int x __attribute__((unused)), dfp_val_t val1, dfp_val_t val2)
+{
+ _Decimal64 f14 = val1.dec_val;
+ _Decimal64 f16 = val2.dec_val;
+ if (!(BF == 4 || BF == 7)) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 4:
+ __asm__ __volatile__ ("dtstex 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dtstex 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dtstexq(int BF, int x __attribute__((unused)), dfp_val_t val1, dfp_val_t val2)
+{
+ _Decimal128 f14 = val1.dec_val128;
+ _Decimal128 f16 = val2.dec_val128;
+ if (!(BF == 4 || BF == 7)) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 4:
+ __asm__ __volatile__ ("dtstexq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dtstexq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+
+
+typedef void (*test_func_t)(int a, int b, dfp_val_t val1, dfp_val_t val2);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+// Both Long and Quad arrays of DFP values should have the same length, so it
+// doesn't matter which array I use for calculating the following #define.
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {4, 3},
+ {6, 0},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+} dfp_test_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_func_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+
+
+static dfp_one_arg_test_t
+dfp_ClassAndGroupTest_tests[] = {
+ { &_test_dtstdc, "dtstdc", LONG_TEST, "[tCls]"},
+ { &_test_dtstdcq, "dtstdcq", QUAD_TEST, "[tCls]"},
+ { &_test_dtstdg, "dtstdg", LONG_TEST, "[tGrp]"},
+ { &_test_dtstdgq, "dtstdgq", QUAD_TEST, "[tGrp]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_ClassAndGroupTest_ops(void)
+{
+ test_func_t func;
+ dfp_val_t test_val, dummy;
+
+ int k = 0;
+
+ while ((func = dfp_ClassAndGroupTest_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_ClassAndGroupTest_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int data_class_OR_group, BF = 0;
+ Bool repeat = True;
+
+ if (test_def.precision == LONG_TEST) {
+ test_val.u64_val = dfp64_vals[i];
+ } else {
+ test_val.u128.valu = dfp128_vals[i * 2];
+ test_val.u64_val = test_val.u128.valu;
+ test_val.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+again:
+ for (data_class_OR_group = 0; data_class_OR_group < 6; data_class_OR_group++) {
+ unsigned int condreg;
+ unsigned int flags;
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, data_class_OR_group, test_val, dummy);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s (DC/DG=%d) %s%016llx", test_def.name, data_class_OR_group,
+ test_def.op, test_val.u64_val);
+ if (test_def.precision == QUAD_TEST) {
+ printf(" %016llx", test_val.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ if (repeat) {
+ repeat = False;
+ BF = 5;
+ goto again;
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_test_t
+dfp_ExpTest_tests[] = {
+ { &_test_dtstex, "dtstex", dfp_2args_x1, 25, LONG_TEST, "[tExp]"},
+ { &_test_dtstexq, "dtstexq", dfp_2args_x1, 25, QUAD_TEST, "[tExp]"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+
+static void test_dfp_ExpTest_ops(void)
+{
+ dfp_val_t test_val1, test_val2;
+ test_func_t func;
+ int k = 0;
+
+ while ((func = dfp_ExpTest_tests[k].test_func)) {
+ /* BF is a 3-bit instruction field that indicates the CR field in which the
+ * result of the test should be placed. We won't iterate through all
+ * 8 possible BF values since storing compare results to a given field is
+ * a well-tested mechanism in VEX. But we will test two BF values, just as
+ * a sniff-test.
+ */
+ int i, repeat = 1, BF = 4;
+ dfp_test_t test_def = dfp_ExpTest_tests[k];
+
+again:
+ for (i = 0; i < test_def.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_def.precision == LONG_TEST) {
+ test_val1.u64_val = dfp64_vals[test_def.targs[i].fra_idx];
+ test_val2.u64_val = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ test_val1.u128.valu = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ test_val1.u64_val = test_val1.u128.valu;
+ test_val1.u128.vall = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ test_val2.u128.valu = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ test_val2.u64_val = test_val2.u128.valu;
+ test_val2.u128.vall = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, 0, test_val1, test_val2);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s %016llx", test_def.name, test_val1.u64_val);
+ if (test_def.precision == LONG_TEST) {
+ printf(" %s %016llx ",
+ test_def.op, test_val2.u64_val);
+ } else {
+ printf(" %016llx %s %016llx %016llx ",
+ test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ if (repeat) {
+ repeat = 0;
+ BF = 7;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_ExpTest_ops,
+ "Test DFP exponent test instructions"},
+ { &test_dfp_ClassAndGroupTest_ops,
+ "Test DFP class and group test instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc64/test_dfp4.stderr.exp b/main/none/tests/ppc64/test_dfp4.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp4.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc64/test_dfp4.stdout.exp b/main/none/tests/ppc64/test_dfp4.stdout.exp
new file mode 100644
index 0000000..253b2a5
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp4.stdout.exp
@@ -0,0 +1,876 @@
+Test DFP exponent test instructions
+dtstex 2234000000000e50 [tExp] 223400000014c000 => 2 (BF=4)
+dtstex a2340000000000e0 [tExp] 223400000014c000 => 2 (BF=4)
+dtstex a21400010a395bcf [tExp] 22240000000000cf => 8 (BF=4)
+dtstex 000400000089b000 [tExp] 2234000000000e50 => 8 (BF=4)
+dtstex a2340000000000e0 [tExp] a21400010a395bcf => 4 (BF=4)
+dtstex 6e4d3f1f534acdd4 [tExp] 223400000014c000 => 4 (BF=4)
+dtstex 6e4d3f1f534acdd4 [tExp] a2340000000000e0 => 4 (BF=4)
+dtstex 2238000000000000 [tExp] 223400000014c000 => 4 (BF=4)
+dtstex 2238000000000000 [tExp] a2340000000000e0 => 4 (BF=4)
+dtstex a238000000000000 [tExp] 2234000000000e50 => 4 (BF=4)
+dtstex a238000000000000 [tExp] 223400000014c000 => 4 (BF=4)
+dtstex a238000000000000 [tExp] a2340000000000e0 => 4 (BF=4)
+dtstex 2238000000000000 [tExp] a238000000000000 => 2 (BF=4)
+dtstex fc00000000000000 [tExp] f800000000000000 => 1 (BF=4)
+dtstex fc00000000000000 [tExp] 223400000014c000 => 1 (BF=4)
+dtstex fc00000000000000 [tExp] 7800000000000000 => 1 (BF=4)
+dtstex fc00000000000000 [tExp] fc00000000000000 => 2 (BF=4)
+dtstex fc00000000000000 [tExp] fe000000d0e0a0d0 => 2 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] f800000000000000 => 1 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] 2234000000000e50 => 1 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] 7800000000000000 => 1 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] fe000000d0e0a0d0 => 2 (BF=4)
+dtstex f800000000000000 [tExp] f800000000000000 => 2 (BF=4)
+dtstex f800000000000000 [tExp] 22240000000000cf => 1 (BF=4)
+dtstex f800000000000000 [tExp] 7a34000000000000 => 2 (BF=4)
+dtstex 2234000000000e50 [tExp] 223400000014c000 => 2 (BF=7)
+dtstex a2340000000000e0 [tExp] 223400000014c000 => 2 (BF=7)
+dtstex a21400010a395bcf [tExp] 22240000000000cf => 8 (BF=7)
+dtstex 000400000089b000 [tExp] 2234000000000e50 => 8 (BF=7)
+dtstex a2340000000000e0 [tExp] a21400010a395bcf => 4 (BF=7)
+dtstex 6e4d3f1f534acdd4 [tExp] 223400000014c000 => 4 (BF=7)
+dtstex 6e4d3f1f534acdd4 [tExp] a2340000000000e0 => 4 (BF=7)
+dtstex 2238000000000000 [tExp] 223400000014c000 => 4 (BF=7)
+dtstex 2238000000000000 [tExp] a2340000000000e0 => 4 (BF=7)
+dtstex a238000000000000 [tExp] 2234000000000e50 => 4 (BF=7)
+dtstex a238000000000000 [tExp] 223400000014c000 => 4 (BF=7)
+dtstex a238000000000000 [tExp] a2340000000000e0 => 4 (BF=7)
+dtstex 2238000000000000 [tExp] a238000000000000 => 2 (BF=7)
+dtstex fc00000000000000 [tExp] f800000000000000 => 1 (BF=7)
+dtstex fc00000000000000 [tExp] 223400000014c000 => 1 (BF=7)
+dtstex fc00000000000000 [tExp] 7800000000000000 => 1 (BF=7)
+dtstex fc00000000000000 [tExp] fc00000000000000 => 2 (BF=7)
+dtstex fc00000000000000 [tExp] fe000000d0e0a0d0 => 2 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] f800000000000000 => 1 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] 2234000000000e50 => 1 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] 7800000000000000 => 1 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] fe000000d0e0a0d0 => 2 (BF=7)
+dtstex f800000000000000 [tExp] f800000000000000 => 2 (BF=7)
+dtstex f800000000000000 [tExp] 22240000000000cf => 1 (BF=7)
+dtstex f800000000000000 [tExp] 7a34000000000000 => 2 (BF=7)
+
+dtstexq 2207c00000000000 0000000000000e50 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=4)
+dtstexq a207c00000000000 00000000000000e0 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=4)
+dtstexq a205c00000000000 000000010a395bcf [tExp] 2206c00000000000 00000000000000cf => 8 (BF=4)
+dtstexq 000400000089b000 0a6000d000000049 [tExp] 2207c00000000000 0000000000000e50 => 8 (BF=4)
+dtstexq a207c00000000000 00000000000000e0 [tExp] a205c00000000000 000000010a395bcf => 4 (BF=4)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] 2207c00000000000 000000000014c000 => 8 (BF=4)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] a207c00000000000 00000000000000e0 => 8 (BF=4)
+dtstexq 2208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=4)
+dtstexq 2208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=4)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 0000000000000e50 => 4 (BF=4)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=4)
+dtstexq a208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=4)
+dtstexq 2208000000000000 0000000000000000 [tExp] a208000000000000 0000000000000000 => 2 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] f800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 2207c00000000000 000000000014c000 => 1 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7e00000000000000 fe000000d0e0a0d0 => 2 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] f800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 2207c00000000000 0000000000000e50 => 1 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 7800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=4)
+dtstexq f800000000000000 0000000000000000 [tExp] f800000000000000 0000000000000000 => 2 (BF=4)
+dtstexq f800000000000000 0000000000000000 [tExp] 2206c00000000000 00000000000000cf => 1 (BF=4)
+dtstexq f800000000000000 0000000000000000 [tExp] f900000000000000 0000000000000000 => 2 (BF=4)
+dtstexq 2207c00000000000 0000000000000e50 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=7)
+dtstexq a207c00000000000 00000000000000e0 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=7)
+dtstexq a205c00000000000 000000010a395bcf [tExp] 2206c00000000000 00000000000000cf => 8 (BF=7)
+dtstexq 000400000089b000 0a6000d000000049 [tExp] 2207c00000000000 0000000000000e50 => 8 (BF=7)
+dtstexq a207c00000000000 00000000000000e0 [tExp] a205c00000000000 000000010a395bcf => 4 (BF=7)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] 2207c00000000000 000000000014c000 => 8 (BF=7)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] a207c00000000000 00000000000000e0 => 8 (BF=7)
+dtstexq 2208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=7)
+dtstexq 2208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=7)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 0000000000000e50 => 4 (BF=7)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=7)
+dtstexq a208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=7)
+dtstexq 2208000000000000 0000000000000000 [tExp] a208000000000000 0000000000000000 => 2 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] f800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 2207c00000000000 000000000014c000 => 1 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7e00000000000000 fe000000d0e0a0d0 => 2 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] f800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 2207c00000000000 0000000000000e50 => 1 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 7800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=7)
+dtstexq f800000000000000 0000000000000000 [tExp] f800000000000000 0000000000000000 => 2 (BF=7)
+dtstexq f800000000000000 0000000000000000 [tExp] 2206c00000000000 00000000000000cf => 1 (BF=7)
+dtstexq f800000000000000 0000000000000000 [tExp] f900000000000000 0000000000000000 => 2 (BF=7)
+
+Test DFP class and group test instructions
+dtstdc (DC/DG=0) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]2234000000000e50 => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]2234000000000e50 => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]223400000014c000 => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]223400000014c000 => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]a2340000000000e0 => a (BF=0)
+dtstdc (DC/DG=4) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]a2340000000000e0 => a (BF=5)
+dtstdc (DC/DG=4) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]22240000000000cf => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]22240000000000cf => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]a21400010a395bcf => a (BF=0)
+dtstdc (DC/DG=4) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]a21400010a395bcf => a (BF=5)
+dtstdc (DC/DG=4) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]6e4d3f1f534acdd4 => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]6e4d3f1f534acdd4 => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]000400000089b000 => 2 (BF=0)
+dtstdc (DC/DG=5) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]000400000089b000 => 2 (BF=5)
+dtstdc (DC/DG=5) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]2238000000000000 => 2 (BF=0)
+dtstdc (DC/DG=0) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]2238000000000000 => 2 (BF=5)
+dtstdc (DC/DG=0) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]a238000000000000 => a (BF=0)
+dtstdc (DC/DG=0) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]a238000000000000 => a (BF=5)
+dtstdc (DC/DG=0) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]4248000000000000 => 2 (BF=0)
+dtstdc (DC/DG=0) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]4248000000000000 => 2 (BF=5)
+dtstdc (DC/DG=0) [tCls]7e34000000000111 => 2 (BF=0)
+dtstdc (DC/DG=1) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]7e34000000000111 => 2 (BF=5)
+dtstdc (DC/DG=1) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]fe000000d0e0a0d0 => a (BF=0)
+dtstdc (DC/DG=1) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]fe000000d0e0a0d0 => a (BF=5)
+dtstdc (DC/DG=1) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]fc00000000000000 => a (BF=0)
+dtstdc (DC/DG=2) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]fc00000000000000 => a (BF=5)
+dtstdc (DC/DG=2) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]7800000000000000 => 2 (BF=0)
+dtstdc (DC/DG=3) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]7800000000000000 => 2 (BF=5)
+dtstdc (DC/DG=3) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]f800000000000000 => a (BF=0)
+dtstdc (DC/DG=3) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]f800000000000000 => a (BF=5)
+dtstdc (DC/DG=3) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]7a34000000000000 => 2 (BF=0)
+dtstdc (DC/DG=3) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]7a34000000000000 => 2 (BF=5)
+dtstdc (DC/DG=3) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]7a34000000000000 => 0 (BF=5)
+
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 0000000000000e50 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 0000000000000e50 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 000000000014c000 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 000000000014c000 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a207c00000000000 00000000000000e0 => a (BF=0)
+dtstdcq (DC/DG=4) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a207c00000000000 00000000000000e0 => a (BF=5)
+dtstdcq (DC/DG=4) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2206c00000000000 00000000000000cf => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2206c00000000000 00000000000000cf => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a205c00000000000 000000010a395bcf => a (BF=0)
+dtstdcq (DC/DG=4) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a205c00000000000 000000010a395bcf => a (BF=5)
+dtstdcq (DC/DG=4) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]6209400000fd0000 00253f1f534acdd4 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]6209400000fd0000 00253f1f534acdd4 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]000400000089b000 0a6000d000000049 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]000400000089b000 0a6000d000000049 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2208000000000000 0000000000000000 => 2 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2208000000000000 0000000000000000 => 2 (BF=5)
+dtstdcq (DC/DG=0) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a208000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=0) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a208000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=0) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a248000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=0) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a248000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=0) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]7c00000000000000 0000000000000000 => 2 (BF=0)
+dtstdcq (DC/DG=2) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]7c00000000000000 0000000000000000 => 2 (BF=5)
+dtstdcq (DC/DG=2) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]fc00000000000000 c00100035b007700 => a (BF=0)
+dtstdcq (DC/DG=2) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]fc00000000000000 c00100035b007700 => a (BF=5)
+dtstdcq (DC/DG=2) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=0)
+dtstdcq (DC/DG=1) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=5)
+dtstdcq (DC/DG=1) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]7800000000000000 0000000000000000 => 2 (BF=0)
+dtstdcq (DC/DG=3) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]7800000000000000 0000000000000000 => 2 (BF=5)
+dtstdcq (DC/DG=3) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]f800000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=3) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]f800000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=3) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]f900000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=3) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]f900000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=3) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+
+dtstdg (DC/DG=0) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]2234000000000e50 => 2 (BF=0)
+dtstdg (DC/DG=3) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]2234000000000e50 => 2 (BF=5)
+dtstdg (DC/DG=3) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]223400000014c000 => 2 (BF=0)
+dtstdg (DC/DG=3) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]223400000014c000 => 2 (BF=5)
+dtstdg (DC/DG=3) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=1) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]a2340000000000e0 => a (BF=0)
+dtstdg (DC/DG=3) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=1) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]a2340000000000e0 => a (BF=5)
+dtstdg (DC/DG=3) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]22240000000000cf => 2 (BF=0)
+dtstdg (DC/DG=3) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]22240000000000cf => 2 (BF=5)
+dtstdg (DC/DG=3) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=1) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]a21400010a395bcf => a (BF=0)
+dtstdg (DC/DG=3) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=1) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]a21400010a395bcf => a (BF=5)
+dtstdg (DC/DG=3) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]6e4d3f1f534acdd4 => 2 (BF=0)
+dtstdg (DC/DG=2) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]6e4d3f1f534acdd4 => 2 (BF=5)
+dtstdg (DC/DG=2) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]000400000089b000 => 2 (BF=0)
+dtstdg (DC/DG=4) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]000400000089b000 => 2 (BF=5)
+dtstdg (DC/DG=4) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]2238000000000000 => 2 (BF=0)
+dtstdg (DC/DG=0) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]2238000000000000 => 2 (BF=5)
+dtstdg (DC/DG=0) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=1) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]a238000000000000 => a (BF=0)
+dtstdg (DC/DG=0) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=1) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]a238000000000000 => a (BF=5)
+dtstdg (DC/DG=0) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]4248000000000000 => 2 (BF=0)
+dtstdg (DC/DG=0) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]4248000000000000 => 2 (BF=5)
+dtstdg (DC/DG=0) [tGrp]7e34000000000111 => 2 (BF=0)
+dtstdg (DC/DG=1) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]7e34000000000111 => 2 (BF=5)
+dtstdg (DC/DG=1) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]fe000000d0e0a0d0 => a (BF=0)
+dtstdg (DC/DG=1) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]fe000000d0e0a0d0 => a (BF=5)
+dtstdg (DC/DG=1) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]fc00000000000000 => a (BF=0)
+dtstdg (DC/DG=1) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]fc00000000000000 => a (BF=5)
+dtstdg (DC/DG=1) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]7800000000000000 => 2 (BF=0)
+dtstdg (DC/DG=1) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]7800000000000000 => 2 (BF=5)
+dtstdg (DC/DG=1) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]f800000000000000 => a (BF=0)
+dtstdg (DC/DG=1) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]f800000000000000 => a (BF=5)
+dtstdg (DC/DG=1) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]7a34000000000000 => 2 (BF=0)
+dtstdg (DC/DG=1) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]7a34000000000000 => 2 (BF=5)
+dtstdg (DC/DG=1) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]7a34000000000000 => 0 (BF=5)
+
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 0000000000000e50 => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 0000000000000e50 => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 000000000014c000 => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 000000000014c000 => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a207c00000000000 00000000000000e0 => a (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a207c00000000000 00000000000000e0 => a (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2206c00000000000 00000000000000cf => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2206c00000000000 00000000000000cf => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a205c00000000000 000000010a395bcf => a (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a205c00000000000 000000010a395bcf => a (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]6209400000fd0000 00253f1f534acdd4 => 2 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]6209400000fd0000 00253f1f534acdd4 => 2 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]000400000089b000 0a6000d000000049 => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]000400000089b000 0a6000d000000049 => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2208000000000000 0000000000000000 => 2 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2208000000000000 0000000000000000 => 2 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a208000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a208000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a248000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a248000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=0) [tGrp]7c00000000000000 0000000000000000 => 2 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]7c00000000000000 0000000000000000 => 2 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]fc00000000000000 c00100035b007700 => a (BF=0)
+dtstdgq (DC/DG=1) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]fc00000000000000 c00100035b007700 => a (BF=5)
+dtstdgq (DC/DG=1) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]7800000000000000 0000000000000000 => 2 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]7800000000000000 0000000000000000 => 2 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]f800000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=1) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]f800000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=1) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]f900000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=1) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]f900000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=1) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+
diff --git a/main/none/tests/ppc64/test_dfp4.vgtest b/main/none/tests/ppc64/test_dfp4.vgtest
new file mode 100644
index 0000000..dac3356
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp4.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp4
diff --git a/main/none/tests/ppc64/test_dfp5.c b/main/none/tests/ppc64/test_dfp5.c
new file mode 100644
index 0000000..64008b6
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp5.c
@@ -0,0 +1,595 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+typedef union stuff {
+ _Decimal64 dec_val;
+ _Decimal128 dec_val128;
+ unsigned long long u64_val;
+ struct {
+ unsigned long long valu;
+ unsigned long long vall;
+ } u128;
+} dfp_val_t;
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+enum BF_vals { BF_val1 = 0, BF_val2 = 1, BF_val3 =6};
+
+// The assembly-level instructions being tested
+static void _test_dtstsf(unsigned int BF, unsigned int ref_sig, dfp_val_t valB)
+{
+ _Decimal64 f16 = valB.dec_val;
+ register HWord_t r14 __asm__ ("r14");
+ double f14;
+ r14 = (HWord_t)&ref_sig;
+
+ __asm __volatile__ ("lfiwax %0, 0, %1" : "=f" (f14): "r" (r14));
+ switch (BF) {
+ case BF_val1:
+ __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16));
+ break;
+ case BF_val2:
+ __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16));
+ break;
+ case BF_val3:
+ __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for BF\n", BF);
+ break;
+ }
+}
+
+static void _test_dtstsfq(unsigned int BF, unsigned int ref_sig, dfp_val_t valB)
+{
+ _Decimal128 f16 = valB.dec_val128;
+ register HWord_t r14 __asm__ ("r14");
+ double f14;
+ r14 = (HWord_t)&ref_sig;
+
+ __asm __volatile__ ("lfiwax %0, 0, %1" : "=f" (f14): "r" (r14));
+ switch (BF) {
+ case BF_val1:
+ __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16));
+ break;
+ case BF_val2:
+ __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16));
+ break;
+ case BF_val3:
+ __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for BF\n", BF);
+ break;
+ }
+}
+
+static dfp_val_t _test_ddedpd(unsigned int SP, dfp_val_t valB)
+{
+ _Decimal64 ret = 0;
+ dfp_val_t result;
+ _Decimal64 f16 = valB.dec_val;
+ switch (SP) {
+ case 0:
+ __asm__ __volatile__ ("ddedpd. 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("ddedpd. 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("ddedpd. 2, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("ddedpd. 3, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for SP\n", SP);
+ break;
+ }
+ result.dec_val = ret;
+ return result;
+}
+
+
+static dfp_val_t _test_ddedpdq(unsigned int SP, dfp_val_t valB)
+{
+ _Decimal128 ret = 0;
+ dfp_val_t result;
+ _Decimal128 f16 = valB.dec_val128;
+ switch (SP) {
+ case 0:
+ __asm__ __volatile__ ("ddedpdq 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("ddedpdq 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("ddedpdq 2, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("ddedpdq 3, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for SP\n", SP);
+ break;
+ }
+ result.dec_val128 = ret;
+ return result;
+}
+
+static dfp_val_t _test_denbcd(unsigned int S, dfp_val_t valB)
+{
+ _Decimal64 ret = 0;
+ dfp_val_t result;
+ _Decimal64 f16 = valB.dec_val;
+ switch (S) {
+ case 0:
+ __asm__ __volatile__ ("denbcd. 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("denbcd. 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for S\n", S);
+ break;
+ }
+ result.dec_val = ret;
+ return result;
+}
+
+
+static dfp_val_t _test_denbcdq(unsigned int S, dfp_val_t valB)
+{
+ _Decimal128 ret = 0;
+ dfp_val_t result;
+ _Decimal128 f16 = valB.dec_val128;
+ switch (S) {
+ case 0:
+ __asm__ __volatile__ ("denbcdq 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("denbcdq 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for S\n", S);
+ break;
+ }
+ result.dec_val128 = ret;
+ return result;
+}
+
+
+typedef void (*test_func_t)(unsigned int imm, unsigned int imm2, dfp_val_t valB);
+typedef dfp_val_t (*test_func_bcd_t)(unsigned int imm, dfp_val_t valB);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+/* The bcd64_vals and bdc128_vals hold the unique results of executing
+ * the ddedpd instruction on the basic dfp64 and dfp128 array values.
+ * Executing the inverse operation (denbcd) on these values with the
+ * appropriate S (signed) value should yield values approximating the
+ * original dfp values (except being 2^4 in magnitude since the decoding
+ * operation shifted the value one hex digit to the left to make room
+ * for signedness info).
+ */
+static unsigned long long bcd64_vals[] = {
+ 0x0000000000003450ULL,
+ 0x000000000003450cULL,
+ 0x000000000003450fULL,
+ 0x0000000001230000ULL,
+ 0x000000001230000cULL,
+ 0x000000001230000fULL,
+ 0x0000000000000160ULL,
+ 0x000000000000160dULL,
+ 0x0000000000000189ULL,
+ 0x000000000000189cULL,
+ 0x000000000000189fULL,
+ 0x0000004123456789ULL,
+ 0x000004123456789dULL,
+ 0x9839871234533354ULL,
+ 0x839871234533354cULL,
+ 0x839871234533354fULL,
+ 0x0000000008864000ULL,
+ 0x000000008864000cULL,
+ 0x000000008864000fULL,
+ 0x0000000000000000ULL,
+ 0x000000000000000cULL,
+ 0x000000000000000fULL,
+ 0x000000000000000dULL,
+ 0x0000000000000211ULL,
+ 0x000000000000211cULL,
+ 0x000000000000211fULL,
+ 0x0000003882028150ULL,
+ 0x000003882028150dULL
+ };
+
+static unsigned long long bcd128_vals[] = {
+ 0x0000000000000000ULL, 0x0000000000003450ULL,
+ 0x0000000000000000ULL, 0x000000000003450cULL,
+ 0x0000000000000000ULL, 0x000000000003450fULL,
+ 0x0000000000000000ULL, 0x0000000001230000ULL,
+ 0x0000000000000000ULL, 0x000000001230000cULL,
+ 0x0000000000000000ULL, 0x000000001230000fULL,
+ 0x0000000000000000ULL, 0x0000000000000160ULL,
+ 0x0000000000000000ULL, 0x000000000000160dULL,
+ 0x0000000000000000ULL, 0x0000000000000189ULL,
+ 0x0000000000000000ULL, 0x000000000000189cULL,
+ 0x0000000000000000ULL, 0x000000000000189fULL,
+ 0x0000000000000000ULL, 0x0000004123456789ULL,
+ 0x0000000000000000ULL, 0x000004123456789dULL,
+ 0x0000097100000000ULL, 0x9839871234533354ULL,
+ 0x0000971000000009ULL, 0x839871234533354cULL,
+ 0x0000971000000009ULL, 0x839871234533354fULL,
+ 0x0000010954000051ULL, 0x8000640000000049ULL,
+ 0x0000109540000518ULL, 0x000640000000049cULL,
+ 0x0000109540000518ULL, 0x000640000000049fULL,
+ 0x0000000000000000ULL, 0x0000000000000000ULL,
+ 0x0000000000000000ULL, 0x000000000000000cULL,
+ 0x0000000000000000ULL, 0x000000000000000fULL,
+ 0x0000000000000000ULL, 0x000000000000000dULL,
+ 0x0000000000080000ULL, 0x0200801330811600ULL,
+ 0x0000000000800000ULL, 0x200801330811600dULL,
+ 0x0000000000088170ULL, 0x0000003882028150ULL,
+ 0x0000000000881700ULL, 0x000003882028150cULL,
+ 0x0000000000881700ULL, 0x000003882028150fULL
+};
+
+// Both Long and Quad arrays of DFP values should have the same length, so it
+// doesn't matter which array I use for calculating the following #define.
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_func_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+typedef struct dfp_one_arg_bcd_test
+{
+ test_func_bcd_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_bcd_test_t;
+
+static dfp_one_arg_bcd_test_t
+dfp_test_dfp_ddedpd_tests[] = {
+ { &_test_ddedpd, "ddedpd", LONG_TEST, "[D->B]"},
+ { &_test_ddedpdq, "ddedpdq", QUAD_TEST, "[D->B]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_ddedpd_ops(void)
+{
+ test_func_bcd_t func;
+ dfp_val_t test_val;
+
+ int k = 0;
+
+ while ((func = dfp_test_dfp_ddedpd_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_bcd_test_t test_def = dfp_test_dfp_ddedpd_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ unsigned int SP;
+
+ if (test_def.precision == LONG_TEST) {
+ test_val.u64_val = dfp64_vals[i];
+ } else {
+ test_val.u128.valu = dfp128_vals[i * 2];
+ test_val.u64_val = test_val.u128.valu;
+ test_val.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+ for (SP = 0; SP < 4; SP++) {
+ dfp_val_t result;
+ result = (*func)(SP, test_val);
+ printf("%s (SP=%d) %s%016llx", test_def.name, SP,
+ test_def.op, test_val.u64_val);
+ if (test_def.precision == QUAD_TEST) {
+ printf(" %016llx", test_val.u128.vall);
+ }
+ if (test_def.precision == LONG_TEST)
+ printf(" ==> %016llx\n", result.u64_val);
+ else
+ printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_one_arg_bcd_test_t
+dfp_test_dfp_denbcd_tests[] = {
+ { &_test_denbcd, "denbcd", LONG_TEST, "[B->D]"},
+ { &_test_denbcdq, "denbcdq", QUAD_TEST, "[B->D]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_denbcd_ops(void)
+{
+ test_func_bcd_t func;
+ dfp_val_t test_val;
+ int num_test_vals;
+
+ int k = 0;
+
+ while ((func = dfp_test_dfp_denbcd_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_bcd_test_t test_def = dfp_test_dfp_denbcd_tests[k];
+ if (test_def.precision == LONG_TEST)
+ num_test_vals = sizeof(bcd64_vals)/sizeof(unsigned long long);
+ else
+ num_test_vals = sizeof(bcd128_vals)/(2 * sizeof(unsigned long long));
+
+ for (i = 0; i < num_test_vals; i++) {
+ unsigned int S;
+ dfp_val_t result;
+ /* The DPD-to-BCD decodings may contain up to 3 decodings for each normal DFP
+ * value: the first is an unsigned decoding, and the other two are
+ * signed decodings, with SP[1] set to '0' and '1' respectively at decode
+ * time. But some of the results of decodings were duplicates, so they were
+ * not included in the bcd64_vals and bcd128_vals arrays.
+ *
+ * When doing the encoding operation (denbcd), we'll attempt both S=0 and
+ * S=1; one or the other should encode the BCD value to something close to
+ * its original DFP value (except being 2^4 in magnitude since the decoding
+ * operation shifted the value one hex digit to the left to make room
+ * for signedness info).
+ */
+ for (S = 0; S < 2; S++) {
+ if (test_def.precision == LONG_TEST) {
+ test_val.u64_val = bcd64_vals[i];
+ } else {
+ test_val.u128.valu = bcd128_vals[i * 2];
+ test_val.u64_val = test_val.u128.valu;
+ test_val.u128.vall = bcd128_vals[(i * 2) + 1];
+ }
+
+ result = (*func)(S, test_val);
+ printf("%s (S=%d) %s%016llx", test_def.name, S,
+ test_def.op, test_val.u64_val);
+ if (test_def.precision == QUAD_TEST) {
+ printf(" %016llx", test_val.u128.vall);
+ }
+ if (test_def.precision == LONG_TEST)
+ printf(" ==> %016llx\n", result.u64_val);
+ else
+ printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_test_significance_tests[] = {
+ { &_test_dtstsf, "dtstsf", LONG_TEST, "[tSig]"},
+ { &_test_dtstsfq, "dtstsfq", QUAD_TEST, "[tSig]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_test_significance_ops(void)
+{
+ test_func_t func;
+ dfp_val_t test_valB;
+ int k = 0;
+ unsigned int BF_vals[] = {BF_val1, BF_val2, BF_val3};
+ unsigned int reference_sig, reference_sig_vals[] = {0U, 1U, 2U, 4U, 6U, 63U};
+ int num_reference_sig_vals = sizeof(reference_sig_vals)/sizeof(unsigned int);
+
+ while ((func = dfp_test_significance_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_test_significance_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int j;
+ if (test_def.precision == LONG_TEST) {
+ test_valB.u64_val = dfp64_vals[i];
+ } else {
+ test_valB.u128.valu = dfp128_vals[i * 2];
+ test_valB.u64_val = test_valB.u128.valu;
+ test_valB.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+ for (j = 0; j < num_reference_sig_vals; j++) {
+ int bf_idx, BF;
+ reference_sig = reference_sig_vals[j];
+ for (bf_idx = 0; bf_idx < sizeof(BF_vals)/sizeof(unsigned int); bf_idx++) {
+ unsigned int condreg;
+ unsigned int flags;
+ BF = BF_vals[bf_idx];
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, reference_sig, test_valB);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s (ref_sig=%d) %s%016llx", test_def.name, reference_sig,
+ test_def.op, test_valB.u64_val);
+ if (test_def.precision == QUAD_TEST) {
+ printf(" %016llx", test_valB.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ }
+ printf( "\n" );
+ }
+ k++;
+ }
+}
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_test_significance_ops,
+ "Test DFP test significance instructions"},
+ { &test_dfp_ddedpd_ops,
+ "Test DFP DPD-to-BCD instructions"},
+ { &test_dfp_denbcd_ops,
+ "Test DFP BCD-to-DPD instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/main/none/tests/ppc64/test_dfp5.stderr.exp b/main/none/tests/ppc64/test_dfp5.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp5.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc64/test_dfp5.stdout.exp b/main/none/tests/ppc64/test_dfp5.stdout.exp
new file mode 100644
index 0000000..0085526
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp5.stdout.exp
@@ -0,0 +1,855 @@
+Test DFP test significance instructions
+dtstsf (ref_sig=0) [tSig]2234000000000e50 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]2234000000000e50 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]2234000000000e50 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]2234000000000e50 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]2234000000000e50 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]2234000000000e50 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]2234000000000e50 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]2234000000000e50 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]2234000000000e50 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]2234000000000e50 => 2 (BF=0)
+dtstsf (ref_sig=4) [tSig]2234000000000e50 => 2 (BF=1)
+dtstsf (ref_sig=4) [tSig]2234000000000e50 => 2 (BF=6)
+dtstsf (ref_sig=6) [tSig]2234000000000e50 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]2234000000000e50 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]2234000000000e50 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]2234000000000e50 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]2234000000000e50 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]2234000000000e50 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]223400000014c000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]223400000014c000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]223400000014c000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]223400000014c000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]223400000014c000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]223400000014c000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]a2340000000000e0 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]a2340000000000e0 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]a2340000000000e0 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]a2340000000000e0 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]a2340000000000e0 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]a2340000000000e0 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]a2340000000000e0 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]a2340000000000e0 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]a2340000000000e0 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]a2340000000000e0 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]22240000000000cf => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]22240000000000cf => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]22240000000000cf => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]22240000000000cf => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]22240000000000cf => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]22240000000000cf => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]22240000000000cf => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]22240000000000cf => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]22240000000000cf => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]22240000000000cf => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]a21400010a395bcf => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]a21400010a395bcf => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]a21400010a395bcf => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]a21400010a395bcf => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]a21400010a395bcf => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]a21400010a395bcf => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]6e4d3f1f534acdd4 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]6e4d3f1f534acdd4 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]6e4d3f1f534acdd4 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]6e4d3f1f534acdd4 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]6e4d3f1f534acdd4 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]6e4d3f1f534acdd4 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]000400000089b000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]000400000089b000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]000400000089b000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]000400000089b000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]000400000089b000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]000400000089b000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=1) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=1) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=2) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=2) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=2) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=4) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]2238000000000000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=1) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=1) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=2) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=2) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=2) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=4) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]a238000000000000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=1) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=1) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=2) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=2) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=2) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=4) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]4248000000000000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]7e34000000000111 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]fc00000000000000 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]7800000000000000 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]f800000000000000 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]7a34000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 0000000000000e50 => 2 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 0000000000000e50 => 2 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 0000000000000e50 => 2 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 000000000014c000 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 000000000014c000 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 000000000014c000 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 000000000014c000 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 000000000014c000 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 000000000014c000 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2206c00000000000 00000000000000cf => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2206c00000000000 00000000000000cf => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2206c00000000000 00000000000000cf => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2206c00000000000 00000000000000cf => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2206c00000000000 00000000000000cf => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2206c00000000000 00000000000000cf => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]000400000089b000 0a6000d000000049 => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]000400000089b000 0a6000d000000049 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2208000000000000 0000000000000000 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a208000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a208000000000000 0000000000000000 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a248000000000000 0000000000000000 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a248000000000000 0000000000000000 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a248000000000000 0000000000000000 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]7c00000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]7c00000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]7c00000000000000 0000000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]7e00000000000000 fe000000d0e0a0d0 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]7800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]7800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]7800000000000000 0000000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+
+Test DFP DPD-to-BCD instructions
+ddedpd (SP=0) [D->B]2234000000000e50 ==> 0000000000003450
+ddedpd (SP=1) [D->B]2234000000000e50 ==> 0000000000003450
+ddedpd (SP=2) [D->B]2234000000000e50 ==> 000000000003450c
+ddedpd (SP=3) [D->B]2234000000000e50 ==> 000000000003450f
+ddedpd (SP=0) [D->B]223400000014c000 ==> 0000000001230000
+ddedpd (SP=1) [D->B]223400000014c000 ==> 0000000001230000
+ddedpd (SP=2) [D->B]223400000014c000 ==> 000000001230000c
+ddedpd (SP=3) [D->B]223400000014c000 ==> 000000001230000f
+ddedpd (SP=0) [D->B]a2340000000000e0 ==> 0000000000000160
+ddedpd (SP=1) [D->B]a2340000000000e0 ==> 0000000000000160
+ddedpd (SP=2) [D->B]a2340000000000e0 ==> 000000000000160d
+ddedpd (SP=3) [D->B]a2340000000000e0 ==> 000000000000160d
+ddedpd (SP=0) [D->B]22240000000000cf ==> 0000000000000189
+ddedpd (SP=1) [D->B]22240000000000cf ==> 0000000000000189
+ddedpd (SP=2) [D->B]22240000000000cf ==> 000000000000189c
+ddedpd (SP=3) [D->B]22240000000000cf ==> 000000000000189f
+ddedpd (SP=0) [D->B]a21400010a395bcf ==> 0000004123456789
+ddedpd (SP=1) [D->B]a21400010a395bcf ==> 0000004123456789
+ddedpd (SP=2) [D->B]a21400010a395bcf ==> 000004123456789d
+ddedpd (SP=3) [D->B]a21400010a395bcf ==> 000004123456789d
+ddedpd (SP=0) [D->B]6e4d3f1f534acdd4 ==> 9839871234533354
+ddedpd (SP=1) [D->B]6e4d3f1f534acdd4 ==> 9839871234533354
+ddedpd (SP=2) [D->B]6e4d3f1f534acdd4 ==> 839871234533354c
+ddedpd (SP=3) [D->B]6e4d3f1f534acdd4 ==> 839871234533354f
+ddedpd (SP=0) [D->B]000400000089b000 ==> 0000000008864000
+ddedpd (SP=1) [D->B]000400000089b000 ==> 0000000008864000
+ddedpd (SP=2) [D->B]000400000089b000 ==> 000000008864000c
+ddedpd (SP=3) [D->B]000400000089b000 ==> 000000008864000f
+ddedpd (SP=0) [D->B]2238000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]2238000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]2238000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]2238000000000000 ==> 000000000000000f
+ddedpd (SP=0) [D->B]a238000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]a238000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]a238000000000000 ==> 000000000000000d
+ddedpd (SP=3) [D->B]a238000000000000 ==> 000000000000000d
+ddedpd (SP=0) [D->B]4248000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]4248000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]4248000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]4248000000000000 ==> 000000000000000f
+ddedpd (SP=0) [D->B]7e34000000000111 ==> 0000000000000211
+ddedpd (SP=1) [D->B]7e34000000000111 ==> 0000000000000211
+ddedpd (SP=2) [D->B]7e34000000000111 ==> 000000000000211c
+ddedpd (SP=3) [D->B]7e34000000000111 ==> 000000000000211f
+ddedpd (SP=0) [D->B]fe000000d0e0a0d0 ==> 0000003882028150
+ddedpd (SP=1) [D->B]fe000000d0e0a0d0 ==> 0000003882028150
+ddedpd (SP=2) [D->B]fe000000d0e0a0d0 ==> 000003882028150d
+ddedpd (SP=3) [D->B]fe000000d0e0a0d0 ==> 000003882028150d
+ddedpd (SP=0) [D->B]fc00000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]fc00000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]fc00000000000000 ==> 000000000000000d
+ddedpd (SP=3) [D->B]fc00000000000000 ==> 000000000000000d
+ddedpd (SP=0) [D->B]7800000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]7800000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]7800000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]7800000000000000 ==> 000000000000000f
+ddedpd (SP=0) [D->B]f800000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]f800000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]f800000000000000 ==> 000000000000000d
+ddedpd (SP=3) [D->B]f800000000000000 ==> 000000000000000d
+ddedpd (SP=0) [D->B]7a34000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]7a34000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]7a34000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]7a34000000000000 ==> 000000000000000f
+
+ddedpdq (SP=0) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000003450
+ddedpdq (SP=1) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000003450
+ddedpdq (SP=2) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 000000000003450c
+ddedpdq (SP=3) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 000000000003450f
+ddedpdq (SP=0) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 0000000001230000
+ddedpdq (SP=1) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 0000000001230000
+ddedpdq (SP=2) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 000000001230000c
+ddedpdq (SP=3) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 000000001230000f
+ddedpdq (SP=0) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 0000000000000160
+ddedpdq (SP=1) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 0000000000000160
+ddedpdq (SP=2) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 000000000000160d
+ddedpdq (SP=3) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 000000000000160d
+ddedpdq (SP=0) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 0000000000000189
+ddedpdq (SP=1) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 0000000000000189
+ddedpdq (SP=2) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 000000000000189c
+ddedpdq (SP=3) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 000000000000189f
+ddedpdq (SP=0) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 0000004123456789
+ddedpdq (SP=1) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 0000004123456789
+ddedpdq (SP=2) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 000004123456789d
+ddedpdq (SP=3) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 000004123456789d
+ddedpdq (SP=0) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000097100000000 9839871234533354
+ddedpdq (SP=1) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000097100000000 9839871234533354
+ddedpdq (SP=2) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000971000000009 839871234533354c
+ddedpdq (SP=3) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000971000000009 839871234533354f
+ddedpdq (SP=0) [D->B]000400000089b000 0a6000d000000049 ==> 0000010954000051 8000640000000049
+ddedpdq (SP=1) [D->B]000400000089b000 0a6000d000000049 ==> 0000010954000051 8000640000000049
+ddedpdq (SP=2) [D->B]000400000089b000 0a6000d000000049 ==> 0000109540000518 000640000000049c
+ddedpdq (SP=3) [D->B]000400000089b000 0a6000d000000049 ==> 0000109540000518 000640000000049f
+ddedpdq (SP=0) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 000000000000000c
+ddedpdq (SP=3) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 000000000000000f
+ddedpdq (SP=0) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=0) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=0) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 000000000000000c
+ddedpdq (SP=3) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 000000000000000f
+ddedpdq (SP=0) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000080000 0200801330811600
+ddedpdq (SP=1) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000080000 0200801330811600
+ddedpdq (SP=2) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000800000 200801330811600d
+ddedpdq (SP=3) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000800000 200801330811600d
+ddedpdq (SP=0) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000088170 0000003882028150
+ddedpdq (SP=1) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000088170 0000003882028150
+ddedpdq (SP=2) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000881700 000003882028150c
+ddedpdq (SP=3) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000881700 000003882028150f
+ddedpdq (SP=0) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 000000000000000c
+ddedpdq (SP=3) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 000000000000000f
+ddedpdq (SP=0) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=0) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+
+Test DFP BCD-to-DPD instructions
+denbcd (S=0) [B->D]0000000000003450 ==> 2238000000000e50
+denbcd (S=1) [B->D]0000000000003450 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000003450c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000003450c ==> 2238000000000e50
+denbcd (S=0) [B->D]000000000003450f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000003450f ==> 2238000000000e50
+denbcd (S=0) [B->D]0000000001230000 ==> 223800000014c000
+denbcd (S=1) [B->D]0000000001230000 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000001230000c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000001230000c ==> 223800000014c000
+denbcd (S=0) [B->D]000000001230000f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000001230000f ==> 223800000014c000
+denbcd (S=0) [B->D]0000000000000160 ==> 22380000000000e0
+denbcd (S=1) [B->D]0000000000000160 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000160d ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000160d ==> a2380000000000e0
+denbcd (S=0) [B->D]0000000000000189 ==> 22380000000000cf
+denbcd (S=1) [B->D]0000000000000189 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000189c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000189c ==> 22380000000000cf
+denbcd (S=0) [B->D]000000000000189f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000189f ==> 22380000000000cf
+denbcd (S=0) [B->D]0000004123456789 ==> 223800010a395bcf
+denbcd (S=1) [B->D]0000004123456789 ==> 7c00000000000000
+denbcd (S=0) [B->D]000004123456789d ==> 7c00000000000000
+denbcd (S=1) [B->D]000004123456789d ==> a23800010a395bcf
+denbcd (S=0) [B->D]9839871234533354 ==> 6e393f1f534acdd4
+denbcd (S=1) [B->D]9839871234533354 ==> 7c00000000000000
+denbcd (S=0) [B->D]839871234533354c ==> 7c00000000000000
+denbcd (S=1) [B->D]839871234533354c ==> 22393f1f534acdd4
+denbcd (S=0) [B->D]839871234533354f ==> 7c00000000000000
+denbcd (S=1) [B->D]839871234533354f ==> 22393f1f534acdd4
+denbcd (S=0) [B->D]0000000008864000 ==> 223800000089b000
+denbcd (S=1) [B->D]0000000008864000 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000008864000c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000008864000c ==> 223800000089b000
+denbcd (S=0) [B->D]000000008864000f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000008864000f ==> 223800000089b000
+denbcd (S=0) [B->D]0000000000000000 ==> 2238000000000000
+denbcd (S=1) [B->D]0000000000000000 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000000c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000000c ==> 2238000000000000
+denbcd (S=0) [B->D]000000000000000f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000000f ==> 2238000000000000
+denbcd (S=0) [B->D]000000000000000d ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000000d ==> a238000000000000
+denbcd (S=0) [B->D]0000000000000211 ==> 2238000000000111
+denbcd (S=1) [B->D]0000000000000211 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000211c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000211c ==> 2238000000000111
+denbcd (S=0) [B->D]000000000000211f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000211f ==> 2238000000000111
+denbcd (S=0) [B->D]0000003882028150 ==> 22380000d0e0a0d0
+denbcd (S=1) [B->D]0000003882028150 ==> 7c00000000000000
+denbcd (S=0) [B->D]000003882028150d ==> 7c00000000000000
+denbcd (S=1) [B->D]000003882028150d ==> a2380000d0e0a0d0
+
+denbcdq (S=0) [B->D]0000000000000000 0000000000003450 ==> 2208000000000000 0000000000000e50
+denbcdq (S=1) [B->D]0000000000000000 0000000000003450 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000003450c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000003450c ==> 2208000000000000 0000000000000e50
+denbcdq (S=0) [B->D]0000000000000000 000000000003450f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000003450f ==> 2208000000000000 0000000000000e50
+denbcdq (S=0) [B->D]0000000000000000 0000000001230000 ==> 2208000000000000 000000000014c000
+denbcdq (S=1) [B->D]0000000000000000 0000000001230000 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000001230000c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000001230000c ==> 2208000000000000 000000000014c000
+denbcdq (S=0) [B->D]0000000000000000 000000001230000f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000001230000f ==> 2208000000000000 000000000014c000
+denbcdq (S=0) [B->D]0000000000000000 0000000000000160 ==> 2208000000000000 00000000000000e0
+denbcdq (S=1) [B->D]0000000000000000 0000000000000160 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000160d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000160d ==> a208000000000000 00000000000000e0
+denbcdq (S=0) [B->D]0000000000000000 0000000000000189 ==> 2208000000000000 00000000000000cf
+denbcdq (S=1) [B->D]0000000000000000 0000000000000189 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000189c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000189c ==> 2208000000000000 00000000000000cf
+denbcdq (S=0) [B->D]0000000000000000 000000000000189f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000189f ==> 2208000000000000 00000000000000cf
+denbcdq (S=0) [B->D]0000000000000000 0000004123456789 ==> 2208000000000000 000000010a395bcf
+denbcdq (S=1) [B->D]0000000000000000 0000004123456789 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000004123456789d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000004123456789d ==> a208000000000000 000000010a395bcf
+denbcdq (S=0) [B->D]0000097100000000 9839871234533354 ==> 2208000000fd0000 00253f1f534acdd4
+denbcdq (S=1) [B->D]0000097100000000 9839871234533354 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000971000000009 839871234533354c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000971000000009 839871234533354c ==> 2208000000fd0000 00253f1f534acdd4
+denbcdq (S=0) [B->D]0000971000000009 839871234533354f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000971000000009 839871234533354f ==> 2208000000fd0000 00253f1f534acdd4
+denbcdq (S=0) [B->D]0000010954000051 8000640000000049 ==> 220800000089b000 0a6000d000000049
+denbcdq (S=1) [B->D]0000010954000051 8000640000000049 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000109540000518 000640000000049c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000109540000518 000640000000049c ==> 220800000089b000 0a6000d000000049
+denbcdq (S=0) [B->D]0000109540000518 000640000000049f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000109540000518 000640000000049f ==> 220800000089b000 0a6000d000000049
+denbcdq (S=0) [B->D]0000000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000000c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000000c ==> 2208000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000000f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000000f ==> 2208000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000000d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000000d ==> a208000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000080000 0200801330811600 ==> 2208000000000000 c00100035b007700
+denbcdq (S=1) [B->D]0000000000080000 0200801330811600 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000800000 200801330811600d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000800000 200801330811600d ==> a208000000000000 c00100035b007700
+denbcdq (S=0) [B->D]0000000000088170 0000003882028150 ==> 2208000000000000 fe000000d0e0a0d0
+denbcdq (S=1) [B->D]0000000000088170 0000003882028150 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000881700 000003882028150c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000881700 000003882028150c ==> 2208000000000000 fe000000d0e0a0d0
+denbcdq (S=0) [B->D]0000000000881700 000003882028150f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000881700 000003882028150f ==> 2208000000000000 fe000000d0e0a0d0
+
diff --git a/main/none/tests/ppc64/test_dfp5.vgtest b/main/none/tests/ppc64/test_dfp5.vgtest
new file mode 100644
index 0000000..9777d05
--- /dev/null
+++ b/main/none/tests/ppc64/test_dfp5.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_dfp_cap
+prog: test_dfp5
diff --git a/main/none/tests/ppc64/test_isa_2_06_part1.c b/main/none/tests/ppc64/test_isa_2_06_part1.c
new file mode 100644
index 0000000..25dcc2e
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part1.c
@@ -0,0 +1,2188 @@
+/* Copyright (C) 2011 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#ifdef HAS_VSX
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+static int errors;
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int cond_reg;
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+typedef void (*test_func_t)(void);
+typedef struct ldst_test ldst_test_t;
+typedef struct vsx_logic_test logic_test_t;
+typedef struct xs_conv_test xs_conv_test_t;
+typedef struct p7_fp_test fp_test_t;
+typedef struct vx_fp_test vx_fp_test_t;
+typedef struct vsx_move_test move_test_t;
+typedef struct vsx_permute_test permute_test_t;
+typedef struct test_table test_table_t;
+
+static double *fargs = NULL;
+static int nb_fargs;
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+static void build_fargs_table(void)
+/*
+ * Double precision:
+ * Sign goes from zero to one (1 bit)
+ * Exponent goes from 0 to ((1 << 12) - 1) (11 bits)
+ * Mantissa goes from 1 to ((1 << 52) - 1) (52 bits)
+ * + special values:
+ * +0.0 : 0 0x000 0x0000000000000 => 0x0000000000000000
+ * -0.0 : 1 0x000 0x0000000000000 => 0x8000000000000000
+ * +infinity : 0 0x7FF 0x0000000000000 => 0x7FF0000000000000
+ * -infinity : 1 0x7FF 0x0000000000000 => 0xFFF0000000000000
+ * +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF => 0x7FF7FFFFFFFFFFFF
+ * -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF => 0xFFF7FFFFFFFFFFFF
+ * +SNaN : 0 0x7FF 0x8000000000000 => 0x7FF8000000000000
+ * -SNaN : 1 0x7FF 0x8000000000000 => 0xFFF8000000000000
+ * (8 values)
+ *
+ * Single precision
+ * Sign: 1 bit
+ * Exponent: 8 bits
+ * Mantissa: 23 bits
+ * +0.0 : 0 0x00 0x000000 => 0x00000000
+ * -0.0 : 1 0x00 0x000000 => 0x80000000
+ * +infinity : 0 0xFF 0x000000 => 0x7F800000
+ * -infinity : 1 0xFF 0x000000 => 0xFF800000
+ * +QNaN : 0 0xFF 0x3FFFFF => 0x7FBFFFFF
+ * -QNaN : 1 0xFF 0x3FFFFF => 0xFFBFFFFF
+ * +SNaN : 0 0xFF 0x400000 => 0x7FC00000
+ * -SNaN : 1 0xFF 0x400000 => 0xFFC00000
+*/
+{
+ uint64_t mant;
+ uint16_t _exp, e1;
+ int s;
+ int i=0;
+
+ if (nb_fargs)
+ return;
+
+ fargs = malloc( 16 * sizeof(double) );
+ for (s = 0; s < 2; s++) {
+ for (e1 = 0x001;; e1 = ((e1 + 1) << 13) + 7) {
+ if (e1 >= 0x400)
+ e1 = 0x3fe;
+ _exp = e1;
+ for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
+ /* Add 'random' bits */
+ mant = ((mant + 0x4A6) << 29) + 0x359) {
+ register_farg( &fargs[i++], s, _exp, mant );
+ }
+ if (e1 == 0x3fe)
+ break;
+ }
+ }
+ // add a few smaller values to fargs . . .
+ s = 0;
+ _exp = 0x002;
+ mant = 0x0000000000b01ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ _exp = 0x000;
+ mant = 0x00000203f0b3dULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ mant = 0x00000005a203dULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ s = 1;
+ _exp = 0x002;
+ mant = 0x0000000000b01ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ _exp = 0x000;
+ mant = 0x00000203f0b3dULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ nb_fargs = i;
+}
+
+
+typedef struct ftdiv_test {
+ int fra_idx;
+ int frb_idx;
+ int cr_flags;
+} ftdiv_test_args_t;
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+ int cr_flags;
+ unsigned long long dp_bin_result;
+} fp_test_args_t;
+
+unsigned long long xscvuxddp_results[] = {
+ 0x43cfec0000000000ULL,
+ 0x43d013c000000000ULL,
+ 0x4338000000b77501ULL,
+ 0x43dffa0000000001ULL,
+ 0x4372321456990000ULL,
+ 0x0000000000000000ULL,
+ 0x43e0000000000000ULL,
+ 0x43dffc0000000000ULL,
+ 0x43effe0000000000ULL,
+ 0x43dffe0000000000ULL,
+ 0x43efff0000000000ULL,
+ 0x43dffe0000000000ULL,
+ 0x43efff0000000000ULL,
+ 0x43e00106800000f0ULL,
+ 0x43e81a0ca1eb40f6ULL
+};
+
+unsigned long long xscvsxddp_results[] = {
+ 0x43cfec0000000000ULL,
+ 0x43d013c000000000ULL,
+ 0x4338000000b77501ULL,
+ 0x43dffa0000000001ULL,
+ 0x4372321456990000ULL,
+ 0x0000000000000000ULL,
+ 0xc3e0000000000000ULL,
+ 0x43dffc0000000000ULL,
+ 0xc330000000000000ULL,
+ 0x43dffe0000000000ULL,
+ 0xc320000000000002ULL,
+ 0x43dffe0000000000ULL,
+ 0xc320000000000000ULL,
+ 0xc3dffdf2fffffe20ULL,
+ 0xc3cf97cd7852fc26ULL,
+};
+
+unsigned long long xscvdpsxds_results[] = {
+ 0x0000000000000000ULL,
+ 0x000000000000003eULL,
+ 0x0000000000000000ULL,
+ 0x7fffffffffffffffULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0x7fffffffffffffffULL,
+ 0x8000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x8000000000000000ULL,
+ 0x0000000000000000ULL,
+ 0xffffffffffffbe6cULL
+};
+
+ftdiv_test_args_t ftdiv_tests[] = {
+ {0, 1, 0x8},
+ {9, 1, 0xa},
+ {1, 12, 0xa},
+ {0, 2, 0xa},
+ {1, 3, 0xa},
+ {3, 0, 0xa},
+ {0, 3, 0xa},
+ {4, 0, 0xa},
+ {7, 1, 0xe},
+ {8, 1, 0xe},
+ {1, 7, 0xe},
+ {0, 13, 0xe},
+ {5, 5, 0xe},
+ {5, 6, 0xe},
+};
+
+fp_test_args_t xscmpX_tests[] = {
+ {8, 8, 0x2, 0ULL},
+ {8, 14, 0x8, 0ULL},
+ {8, 6, 0x8, 0ULL},
+ {8, 5, 0x8, 0ULL},
+ {8, 4, 0x8, 0ULL},
+ {8, 7, 0x8, 0ULL},
+ {8, 9, 0x1, 0ULL},
+ {8, 11, 0x1, 0ULL},
+ {14, 8, 0x4, 0ULL},
+ {14, 14, 0x2, 0ULL},
+ {14, 6, 0x8, 0ULL},
+ {14, 5, 0x8, 0ULL},
+ {14, 4, 0x8, 0ULL},
+ {14, 7, 0x8, 0ULL},
+ {14, 9, 0x1, 0ULL},
+ {14, 11, 0x1, 0ULL},
+ {6, 8, 0x4, 0ULL},
+ {6, 14, 0x4, 0ULL},
+ {6, 6, 0x2, 0ULL},
+ {6, 5, 0x2, 0ULL},
+ {6, 4, 0x8, 0ULL},
+ {6, 7, 0x8, 0ULL},
+ {6, 9, 0x1, 0ULL},
+ {6, 11, 0x1, 0ULL},
+ {5, 8, 0x4, 0ULL},
+ {5, 14, 0x4, 0ULL},
+ {5, 6, 0x2, 0ULL},
+ {5, 5, 0x2, 0ULL},
+ {5, 4, 0x8, 0ULL},
+ {5, 7, 0x8, 0ULL},
+ {5, 9, 0x1, 0ULL},
+ {5, 11, 0x1, 0ULL},
+ {4, 8, 0x4, 0ULL},
+ {4, 14, 0x4, 0ULL},
+ {4, 6, 0x4, 0ULL},
+ {4, 5, 0x4, 0ULL},
+ {4, 1, 0x8, 0ULL},
+ {4, 7, 0x8, 0ULL},
+ {4, 9, 0x1, 0ULL},
+ {4, 11, 0x1, 0ULL},
+ {7, 8, 0x4, 0ULL},
+ {7, 14, 0x4, 0ULL},
+ {7, 6, 0x4, 0ULL},
+ {7, 5, 0x4, 0ULL},
+ {7, 4, 0x4, 0ULL},
+ {7, 7, 0x2, 0ULL},
+ {7, 9, 0x1, 0ULL},
+ {7, 11, 0x1, 0ULL},
+ {10, 8, 0x1, 0ULL},
+ {10, 14, 0x1, 0ULL},
+ {10, 6, 0x1, 0ULL},
+ {10, 5, 0x1, 0ULL},
+ {10, 4, 0x1, 0ULL},
+ {10, 7, 0x1, 0ULL},
+ {10, 9, 0x1, 0ULL},
+ {10, 11, 0x1, 0ULL},
+ {12, 8, 0x1, 0ULL},
+ {12, 14, 0x1, 0ULL},
+ {12, 6, 0x1, 0ULL},
+ {12, 5, 0x1, 0ULL},
+ {12, 4, 0x1, 0ULL},
+ {12, 7, 0x1, 0ULL},
+ {12, 9, 0x1, 0ULL},
+ {12, 11, 0x1, 0ULL},
+};
+
+fp_test_args_t xsadddp_tests[] = {
+ {8, 8, 0x0, 0xfff0000000000000ULL},
+ {8, 14, 0x0, 0xfff0000000000000ULL},
+ {8, 6, 0x0, 0xfff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0x7ff8000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0xfff0000000000000ULL},
+ {14, 14, 0x0, 0xc0e0650f5a07b353ULL},
+ {14, 6, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 5, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 4, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 7, 0x0, 0x7ff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0xfff0000000000000ULL},
+ {6, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x8000000000000000ULL},
+ {6, 5, 0x0, 0x0000000000000000ULL},
+ {6, 4, 0x0, 0x0123214569900000ULL},
+ {6, 7, 0x0, 0x7ff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0xfff0000000000000ULL},
+ {5, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x0000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x0123214569900000ULL},
+ {5, 7, 0x0, 0x7ff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0xfff0000000000000ULL},
+ {4, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x0123214569900000ULL},
+ {4, 5, 0x0, 0x0123214569900000ULL},
+ {4, 1, 0x0, 0x404f000000000000ULL},
+ {4, 7, 0x0, 0x7ff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff8000000000000ULL},
+ {7, 14, 0x0, 0x7ff0000000000000ULL},
+ {7, 6, 0x0, 0x7ff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff0000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsdivdp_tests[] = {
+ {8, 8, 0x0, 0x7ff8000000000000ULL},
+ {8, 14, 0x0, 0x7ff0000000000000ULL},
+ {8, 6, 0x0, 0x7ff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0x7ff8000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x0000000000000000ULL},
+ {14, 14, 0x0, 0x3ff0000000000000ULL},
+ {14, 6, 0x0, 0x7ff0000000000000ULL},
+ {14, 5, 0x0, 0xfff0000000000000ULL},
+ {14, 4, 0x0, 0xff9b6cb57ca13c00ULL},
+ {14, 7, 0x0, 0x8000000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x0000000000000000ULL},
+ {6, 14, 0x0, 0x0000000000000000ULL},
+ {6, 6, 0x0, 0x7ff8000000000000ULL},
+ {6, 5, 0x0, 0x7ff8000000000000ULL},
+ {6, 4, 0x0, 0x8000000000000000ULL},
+ {6, 7, 0x0, 0x8000000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x8000000000000000ULL},
+ {5, 14, 0x0, 0x8000000000000000ULL},
+ {5, 6, 0x0, 0x7ff8000000000000ULL},
+ {5, 5, 0x0, 0x7ff8000000000000ULL},
+ {5, 4, 0x0, 0x0000000000000000ULL},
+ {5, 7, 0x0, 0x0000000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0x8000000000000000ULL},
+ {4, 14, 0x0, 0x8042ab59d8b6ec87ULL},
+ {4, 6, 0x0, 0xfff0000000000000ULL},
+ {4, 5, 0x0, 0x7ff0000000000000ULL},
+ {4, 1, 0x0, 0x00c3bf3f64b5ad6bULL},
+ {4, 7, 0x0, 0x0000000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff8000000000000ULL},
+ {7, 14, 0x0, 0xfff0000000000000ULL},
+ {7, 6, 0x0, 0xfff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff8000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsmaddXdp_tests[] = {
+ {8, 8, 0x0, 0x7ff8000000000000ULL},
+ {8, 14, 0x0, 0xfff0000000000000ULL},
+ {8, 6, 0x0, 0x7ff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0x7ff0000000000000ULL},
+ {8, 7, 0x0, 0x7ff8000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0xfff0000000000000ULL},
+ {14, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 5, 0x0, 0x82039a19ca8fcb5fULL},
+ {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 7, 0x0, 0x7ff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0xfff0000000000000ULL},
+ {6, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x0000000000000000ULL},
+ {6, 5, 0x0, 0x0000000000000000ULL},
+ {6, 4, 0x0, 0x0123214569900000ULL},
+ {6, 7, 0x0, 0x7ff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0xfff0000000000000ULL},
+ {5, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x8000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x0123214569900000ULL},
+ {5, 7, 0x0, 0x7ff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0xfff0000000000000ULL},
+ {4, 14, 0x0, 0xc0d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x82039a19ca8fcb5fULL},
+ {4, 5, 0x0, 0x0000000000000000ULL},
+ {4, 1, 0x0, 0x404f000000000000ULL},
+ {4, 7, 0x0, 0x7ff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0xfff0000000000000ULL},
+ {7, 14, 0x0, 0x7ff0000000000000ULL},
+ {7, 6, 0x0, 0xfff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0xfff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff0000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsmsubXdp_tests[] = {
+ {8, 8, 0x0, 0x7ff0000000000000ULL},
+ {8, 14, 0x0, 0xfff0000000000000ULL},
+ {8, 6, 0x0, 0x7ff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0x7ff0000000000000ULL},
+ {8, 7, 0x0, 0xfff0000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x7ff0000000000000ULL},
+ {14, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 5, 0x0, 0x82039a19ca8fcb5fULL},
+ {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 7, 0x0, 0xfff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x7ff0000000000000ULL},
+ {6, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x0000000000000000ULL},
+ {6, 5, 0x0, 0x8000000000000000ULL},
+ {6, 4, 0x0, 0x8123214569900000ULL},
+ {6, 7, 0x0, 0xfff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x7ff0000000000000ULL},
+ {5, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x0000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x8123214569900000ULL},
+ {5, 7, 0x0, 0xfff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0x7ff0000000000000ULL},
+ {4, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x82039a19ca8fcb5fULL},
+ {4, 5, 0x0, 0x0000000000000000ULL},
+ {4, 1, 0x0, 0xc04f000000000000ULL},
+ {4, 7, 0x0, 0xfff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff8000000000000ULL},
+ {7, 14, 0x0, 0x7ff0000000000000ULL},
+ {7, 6, 0x0, 0xfff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0xfff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff8000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsnmaddXdp_tests[] = {
+ {8, 8, 0x0, 0x7ff8000000000000ULL},
+ {8, 14, 0x0, 0x7ff0000000000000ULL},
+ {8, 6, 0x0, 0xfff0000000000000ULL},
+ {8, 5, 0x0, 0x7ff0000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0x7ff8000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x7ff0000000000000ULL},
+ {14, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {14, 6, 0x0, 0xc1b0cc9d05eec2a7ULL},
+ {14, 5, 0x0, 0x02039a19ca8fcb5fULL},
+ {14, 4, 0x0, 0xc1b0cc9d05eec2a7ULL},
+ {14, 7, 0x0, 0xfff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x7ff0000000000000ULL},
+ {6, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x8000000000000000ULL},
+ {6, 5, 0x0, 0x8000000000000000ULL},
+ {6, 4, 0x0, 0x8123214569900000ULL},
+ {6, 7, 0x0, 0xfff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x7ff0000000000000ULL},
+ {5, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x0000000000000000ULL},
+ {5, 5, 0x0, 0x8000000000000000ULL},
+ {5, 4, 0x0, 0x8123214569900000ULL},
+ {5, 7, 0x0, 0xfff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0x7ff0000000000000ULL},
+ {4, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x02039a19ca8fcb5fULL},
+ {4, 5, 0x0, 0x8000000000000000ULL},
+ {4, 1, 0x0, 0xc04f000000000000ULL},
+ {4, 7, 0x0, 0xfff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff0000000000000ULL},
+ {7, 14, 0x0, 0xfff0000000000000ULL},
+ {7, 6, 0x0, 0x7ff0000000000000ULL},
+ {7, 5, 0x0, 0xfff0000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0xfff0000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xsmuldp_tests[] = {
+ {8, 8, 0x0, 0x7ff0000000000000ULL},
+ {8, 14, 0x0, 0x7ff0000000000000ULL},
+ {8, 6, 0x0, 0x7ff8000000000000ULL},
+ {8, 5, 0x0, 0x7ff8000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0xfff0000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x7ff0000000000000ULL},
+ {14, 14, 0x0, 0x41b0cc9d05eec2a7ULL},
+ {14, 6, 0x0, 0x0000000000000000ULL},
+ {14, 5, 0x0, 0x8000000000000000ULL},
+ {14, 4, 0x0, 0x82039a19ca8fcb5fULL},
+ {14, 7, 0x0, 0xfff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x7ff8000000000000ULL},
+ {6, 14, 0x0, 0x0000000000000000ULL},
+ {6, 6, 0x0, 0x0000000000000000ULL},
+ {6, 5, 0x0, 0x8000000000000000ULL},
+ {6, 4, 0x0, 0x8000000000000000ULL},
+ {6, 7, 0x0, 0x7ff8000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x7ff8000000000000ULL},
+ {5, 14, 0x0, 0x8000000000000000ULL},
+ {5, 6, 0x0, 0x8000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x0000000000000000ULL},
+ {5, 7, 0x0, 0x7ff8000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0xfff0000000000000ULL},
+ {4, 14, 0x0, 0x82039a19ca8fcb5fULL},
+ {4, 6, 0x0, 0x8000000000000000ULL},
+ {4, 5, 0x0, 0x0000000000000000ULL},
+ {4, 1, 0x0, 0x0182883b3e438000ULL},
+ {4, 7, 0x0, 0x7ff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0xfff0000000000000ULL},
+ {7, 14, 0x0, 0xfff0000000000000ULL},
+ {7, 6, 0x0, 0x7ff8000000000000ULL},
+ {7, 5, 0x0, 0x7ff8000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff0000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+fp_test_args_t xssubdp_tests[] = {
+ {8, 8, 0x0, 0x7ff8000000000000ULL},
+ {8, 14, 0x0, 0xfff0000000000000ULL},
+ {8, 6, 0x0, 0xfff0000000000000ULL},
+ {8, 5, 0x0, 0xfff0000000000000ULL},
+ {8, 4, 0x0, 0xfff0000000000000ULL},
+ {8, 7, 0x0, 0xfff0000000000000ULL},
+ {8, 9, 0x0, 0x7fffffffffffffffULL},
+ {8, 11, 0x0, 0x7ff8000000000000ULL},
+ {14, 8, 0x0, 0x7ff0000000000000ULL},
+ {14, 14, 0x0, 0x0000000000000000ULL},
+ {14, 6, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 5, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 4, 0x0, 0xc0d0650f5a07b353ULL},
+ {14, 7, 0x0, 0xfff0000000000000ULL},
+ {14, 9, 0x0, 0x7fffffffffffffffULL},
+ {14, 11, 0x0, 0x7ff8000000000000ULL},
+ {6, 8, 0x0, 0x7ff0000000000000ULL},
+ {6, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {6, 6, 0x0, 0x0000000000000000ULL},
+ {6, 5, 0x0, 0x8000000000000000ULL},
+ {6, 4, 0x0, 0x8123214569900000ULL},
+ {6, 7, 0x0, 0xfff0000000000000ULL},
+ {6, 9, 0x0, 0x7fffffffffffffffULL},
+ {6, 11, 0x0, 0x7ff8000000000000ULL},
+ {5, 8, 0x0, 0x7ff0000000000000ULL},
+ {5, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {5, 6, 0x0, 0x0000000000000000ULL},
+ {5, 5, 0x0, 0x0000000000000000ULL},
+ {5, 4, 0x0, 0x8123214569900000ULL},
+ {5, 7, 0x0, 0xfff0000000000000ULL},
+ {5, 9, 0x0, 0x7fffffffffffffffULL},
+ {5, 11, 0x0, 0x7ff8000000000000ULL},
+ {4, 8, 0x0, 0x7ff0000000000000ULL},
+ {4, 14, 0x0, 0x40d0650f5a07b353ULL},
+ {4, 6, 0x0, 0x0123214569900000ULL},
+ {4, 5, 0x0, 0x0123214569900000ULL},
+ {4, 1, 0x0, 0xc04f000000000000ULL},
+ {4, 7, 0x0, 0xfff0000000000000ULL},
+ {4, 9, 0x0, 0x7fffffffffffffffULL},
+ {4, 11, 0x0, 0x7ff8000000000000ULL},
+ {7, 8, 0x0, 0x7ff0000000000000ULL},
+ {7, 14, 0x0, 0x7ff0000000000000ULL},
+ {7, 6, 0x0, 0x7ff0000000000000ULL},
+ {7, 5, 0x0, 0x7ff0000000000000ULL},
+ {7, 4, 0x0, 0x7ff0000000000000ULL},
+ {7, 7, 0x0, 0x7ff8000000000000ULL},
+ {7, 9, 0x0, 0x7fffffffffffffffULL},
+ {7, 11, 0x0, 0x7ff8000000000000ULL},
+ {10, 8, 0x0, 0xffffffffffffffffULL},
+ {10, 14, 0x0, 0xffffffffffffffffULL},
+ {10, 6, 0x0, 0xffffffffffffffffULL},
+ {10, 5, 0x0, 0xffffffffffffffffULL},
+ {10, 4, 0x0, 0xffffffffffffffffULL},
+ {10, 7, 0x0, 0xffffffffffffffffULL},
+ {10, 9, 0x0, 0xffffffffffffffffULL},
+ {10, 11, 0x0, 0xffffffffffffffffULL},
+ {12, 8, 0x0, 0xfff8000000000000ULL},
+ {12, 14, 0x0, 0xfff8000000000000ULL},
+ {12, 6, 0x0, 0xfff8000000000000ULL},
+ {12, 5, 0x0, 0xfff8000000000000ULL},
+ {12, 4, 0x0, 0xfff8000000000000ULL},
+ {12, 7, 0x0, 0xfff8000000000000ULL},
+ {12, 9, 0x0, 0xfff8000000000000ULL},
+ {12, 11, 0x0, 0xfff8000000000000ULL},
+};
+
+
+
+static int nb_special_fargs;
+static double * spec_fargs;
+
+static void build_special_fargs_table(void)
+{
+ /* The special floating point values created below are for
+ * use in the ftdiv tests for setting the fe_flag and fg_flag,
+ * but they can also be used for other tests (e.g., xscmpudp).
+ *
+ * Note that fl_flag is 'always '1' on ppc64 Linux.
+ *
+ Entry Sign Exp fraction Special value
+ 0 0 3fd 0x8000000000000ULL Positive finite number
+ 1 0 404 0xf000000000000ULL ...
+ 2 0 001 0x8000000b77501ULL ...
+ 3 0 7fe 0x800000000051bULL ...
+ 4 0 012 0x3214569900000ULL ...
+ 5 0 000 0x0000000000000ULL +0.0 (+zero)
+ 6 1 000 0x0000000000000ULL -0.0 (-zero)
+ 7 0 7ff 0x0000000000000ULL +infinity
+ 8 1 7ff 0x0000000000000ULL -infinity
+ 9 0 7ff 0x7FFFFFFFFFFFFULL +QNaN
+ 10 1 7ff 0x7FFFFFFFFFFFFULL -QNaN
+ 11 0 7ff 0x8000000000000ULL +SNaN
+ 12 1 7ff 0x8000000000000ULL -SNaN
+ 13 1 000 0x8340000078000ULL Denormalized val (zero exp and non-zero fraction)
+ 14 1 40d 0x0650f5a07b353ULL Negative finite number
+ */
+
+ uint64_t mant;
+ uint16_t _exp;
+ int s;
+ int i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 16 * sizeof(double) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* None of the ftdiv tests succeed.
+ * FRA = value #0; FRB = value #1
+ * ea_ = -2; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 100
+ */
+
+ /*************************************************
+ * fe_flag tests
+ *
+ *************************************************/
+
+ /* fe_flag <- 1 if FRA is a NaN
+ * FRA = value #9; FRB = value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRB is a NaN
+ * FRA = value #1; FRB = value #12
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if e_b <= -1022
+ * FRA = value #0; FRB = value #2
+ * e_a = -2; e_b = -1022
+ * fl_flag || fg_flag || fe_flag = 101
+ *
+ */
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if e_b >= 1021
+ * FRA = value #1; FRB = value #3
+ * e_a = 5; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b >= 1023
+ * Let FRA = value #3 and FRB be value #0.
+ * e_a = 1023; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b <= -1023
+ * Let FRA = value #0 above and FRB be value #3 above
+ * e_a = -2; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a <= -970
+ * Let FRA = value #4 and FRB be value #0
+ * e_a = -1005; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /*************************************************
+ * fg_flag tests
+ *
+ *************************************************/
+ /* fg_flag <- 1 if FRA is an Infinity
+ * NOTE: FRA = Inf also sets fe_flag
+ * Do two tests, using values #7 and #8 (+/- Inf) for FRA.
+ * Test 1:
+ * Let FRA be value #7 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ * Test 2:
+ * Let FRA be value #8 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ */
+
+ /* fg_flag <- 1 if FRB is an Infinity
+ * NOTE: FRB = Inf also sets fe_flag
+ * Let FRA be value #1 and FRB be value #7
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is denormalized
+ * NOTE: e_b < -1022 ==> fe_flag <- 1
+ * Let FRA be value #0 and FRB be value #13
+ * e_a = -2; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is +zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #5
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is -zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #6
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +SNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -SNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ nb_special_fargs = i;
+}
+
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+struct p7_fp_test
+{
+ test_func_t test_func;
+ const char *name;
+ int single; // 1=single precision result; 0=double precision result
+};
+
+typedef enum {
+ VX_FP_CMP,
+ VX_FP_SMA,
+ VX_FP_SMS,
+ VX_FP_SNMA,
+ VX_FP_OTHER
+} vx_fp_test_type;
+
+struct vx_fp_test
+{
+ test_func_t test_func;
+ const char *name;
+ fp_test_args_t * targs;
+ int num_tests;
+ vx_fp_test_type test_type;
+};
+
+struct xs_conv_test
+{
+ test_func_t test_func;
+ const char *name;
+ unsigned long long * results;
+ int num_tests;
+};
+
+typedef enum {
+ VSX_LOAD =1,
+ VSX_LOAD_SPLAT,
+ VSX_STORE
+} vsx_ldst_type;
+
+struct ldst_test
+{
+ test_func_t test_func;
+ const char *name;
+ void * base_addr;
+ uint32_t offset;
+ int num_words_to_process;
+ vsx_ldst_type type;
+};
+
+typedef enum {
+ VSX_AND = 1,
+ VSX_XOR,
+ VSX_ANDC,
+ VSX_OR,
+ VSX_NOR
+} vsx_log_op;
+
+struct vsx_logic_test
+{
+ test_func_t test_func;
+ const char *name;
+ vsx_log_op op;
+};
+
+struct vsx_move_test
+{
+ test_func_t test_func;
+ const char *name;
+ int xa_idx, xb_idx;
+ unsigned long long expected_result;
+};
+
+struct vsx_permute_test
+{
+ test_func_t test_func;
+ const char *name;
+ unsigned int xa[4];
+ unsigned int xb[4];
+ unsigned int expected_output[4];
+};
+
+static vector unsigned int vec_out, vec_inA, vec_inB;
+
+static void test_lxsdx(void)
+{
+ __asm__ __volatile__ ("lxsdx %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void
+test_lxvd2x(void)
+{
+ __asm__ __volatile__ ("lxvd2x %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_lxvdsx(void)
+{
+ __asm__ __volatile__ ("lxvdsx %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_lxvw4x(void)
+{
+ __asm__ __volatile__ ("lxvw4x %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_stxsdx(void)
+{
+ __asm__ __volatile__ ("stxsdx %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_stxvd2x(void)
+{
+ __asm__ __volatile__ ("stxvd2x %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_stxvw4x(void)
+{
+ __asm__ __volatile__ ("stxvw4x %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_xxlxor(void)
+{
+ __asm__ __volatile__ ("xxlxor %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlor(void)
+{
+ __asm__ __volatile__ ("xxlor %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlnor(void)
+{
+ __asm__ __volatile__ ("xxlnor %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxland(void)
+{
+ __asm__ __volatile__ ("xxland %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlandc(void)
+{
+ __asm__ __volatile__ ("xxlandc %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxmrghw(void)
+{
+ __asm__ __volatile__ ("xxmrghw %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxmrglw(void)
+{
+ __asm__ __volatile__ ("xxmrglw %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_00(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x0" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_01(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x1" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_10(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_11(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x3" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_0(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 0" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_1(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 1" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_2(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_3(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 3" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_fcfids (void)
+{
+ __asm__ __volatile__ ("fcfids %0, %1" : "=f" (f17): "d" (f14));
+}
+
+static void test_fcfidus (void)
+{
+ __asm__ __volatile__ ("fcfidus %0, %1" : "=f" (f17): "d" (f14));
+}
+
+static void test_fcfidu (void)
+{
+ __asm__ __volatile__ ("fcfidu %0, %1" : "=f" (f17): "d" (f14));
+}
+
+static void test_xsabsdp (void)
+{
+ __asm__ __volatile__ ("xsabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscpsgndp (void)
+{
+ __asm__ __volatile__ ("xscpsgndp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsnabsdp (void)
+{
+ __asm__ __volatile__ ("xsnabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsnegdp (void)
+{
+ __asm__ __volatile__ ("xsnegdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static int do_cmpudp;
+static void test_xscmp (void)
+{
+ if (do_cmpudp)
+ __asm__ __volatile__ ("xscmpudp cr1, %x0, %x1" : : "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xscmpodp cr1, %x0, %x1" : : "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsadddp(void)
+{
+ __asm__ __volatile__ ("xsadddp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsdivdp(void)
+{
+ __asm__ __volatile__ ("xsdivdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static int do_adp;
+static void test_xsmadd(void)
+{
+ if (do_adp)
+ __asm__ __volatile__ ("xsmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmsub(void)
+{
+ if (do_adp)
+ __asm__ __volatile__ ("xsmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsnmadd(void)
+{
+ if (do_adp)
+ __asm__ __volatile__ ("xsnmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsnmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmuldp(void)
+{
+ __asm__ __volatile__ ("xsmuldp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xssubdp(void)
+{
+ __asm__ __volatile__ ("xssubdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xscvdpsxds (void)
+{
+ __asm__ __volatile__ ("xscvdpsxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvsxddp (void)
+{
+ __asm__ __volatile__ ("xscvsxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvuxddp (void)
+{
+ __asm__ __volatile__ ("xscvuxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static unsigned int vstg[] __attribute__ ((aligned (16))) = { 0, 0, 0,0,
+ 0, 0, 0, 0 };
+
+#define NUM_VSTG_INTS (sizeof vstg/sizeof vstg[0])
+#define NUM_VSTG_VECS (NUM_VSTG_INTS/4)
+
+static unsigned int viargs[] __attribute__ ((aligned (16))) = { 0x01234567,
+ 0x89abcdef,
+ 0x00112233,
+ 0x44556677,
+ 0x8899aabb,
+ 0x91929394,
+ 0xa1a2a3a4,
+ 0xb1b2b3b4,
+ 0xc1c2c3c4,
+ 0xd1d2d3d4,
+ 0x7a6b5d3e
+};
+#define NUM_VIARGS_INTS (sizeof viargs/sizeof viargs[0])
+#define NUM_VIARGS_VECS (NUM_VIARGS_INTS/4)
+
+static ldst_test_t ldst_tests[] = { { &test_lxsdx, "lxsdx", viargs, 0, 2, VSX_LOAD },
+ { &test_lxsdx, "lxsdx", viargs, 4, 2, VSX_LOAD },
+ { &test_lxvd2x, "lxvd2x", viargs, 0, 4, VSX_LOAD },
+ { &test_lxvd2x, "lxvd2x", viargs, 4, 4, VSX_LOAD },
+ { &test_lxvdsx, "lxvdsx", viargs, 0, 4, VSX_LOAD_SPLAT },
+ { &test_lxvdsx, "lxvdsx", viargs, 4, 4, VSX_LOAD_SPLAT },
+ { &test_lxvw4x, "lxvw4x", viargs, 0, 4, VSX_LOAD },
+ { &test_lxvw4x, "lxvw4x", viargs, 4, 4, VSX_LOAD },
+ { &test_stxsdx, "stxsdx", vstg, 0, 2, VSX_STORE },
+ { &test_stxsdx, "stxsdx", vstg, 4, 2, VSX_STORE },
+ { &test_stxvd2x, "stxvd2x", vstg, 0, 4, VSX_STORE },
+ { &test_stxvd2x, "stxvd2x", vstg, 4, 4, VSX_STORE },
+ { &test_stxvw4x, "stxvw4x", vstg, 0, 4, VSX_STORE },
+ { &test_stxvw4x, "stxvw4x", vstg, 4, 4, VSX_STORE },
+ { NULL, NULL, NULL, 0, 0, 0 } };
+
+static logic_test_t logic_tests[] = { { &test_xxlxor, "xxlxor", VSX_XOR },
+ { &test_xxlor, "xxlor", VSX_OR } ,
+ { &test_xxlnor, "xxlnor", VSX_NOR },
+ { &test_xxland, "xxland", VSX_AND },
+ { &test_xxlandc, "xxlandc", VSX_ANDC },
+ { NULL, NULL}};
+
+static move_test_t move_tests[] = { { &test_xsabsdp, "xsabsdp", 0, 4, 0x0899aabb91929394ULL },
+ { &test_xscpsgndp, "xscpsgndp", 4, 0, 0x8123456789abcdefULL },
+ { &test_xsnabsdp, "xsnabsdp", 7, 3, 0xc45566778899aabbULL, },
+ { &test_xsnegdp, "xsnegdp", 0, 7, 0x31b2b3b4c1c2c3c4ULL, },
+ { NULL, NULL, 0, 0, 0 }
+
+};
+
+static permute_test_t permute_tests[] =
+{
+ { &test_xxmrghw, "xxmrghw",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x11111111, 0x55555555, 0x22222222, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxmrghw, "xxmrghw",
+ { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff }, /* XA input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XB input */
+ { 0x00112233, 0x11111111, 0x44556677, 0x22222222 } /* XT expected output */
+ },
+ { &test_xxmrglw, "xxmrglw",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x33333333, 0x77777777, 0x44444444, 0x88888888 } /* XT expected output */
+ },
+ { &test_xxmrglw, "xxmrglw",
+ { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff}, /* XA input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444}, /* XB input */
+ { 0x8899aabb, 0x33333333, 0xccddeeff, 0x44444444} /* XT expected output */
+ },
+ { &test_xxpermdi_00, "xxpermdi DM=00",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x11111111, 0x22222222, 0x55555555, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxpermdi_01, "xxpermdi DM=01",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x11111111, 0x22222222, 0x77777777, 0x88888888 } /* XT expected output */
+ },
+ { &test_xxpermdi_10, "xxpermdi DM=10",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxpermdi_11, "xxpermdi DM=11",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x33333333, 0x44444444, 0x77777777, 0x88888888 } /* XT expected output */
+ },
+ { &test_xxsldwi_0, "xxsldwi SHW=0",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 } /* XT expected output */
+ },
+ { &test_xxsldwi_1, "xxsldwi SHW=1",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x22222222, 0x33333333, 0x44444444, 0x55555555 } /* XT expected output */
+ },
+ { &test_xxsldwi_2, "xxsldwi SHW=2",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxsldwi_3, "xxsldwi SHW=3",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ { 0x44444444, 0x55555555, 0x66666666, 0x77777777 } /* XT expected output */
+ },
+ { NULL, NULL }
+};
+
+static fp_test_t fp_tests[] = { { &test_fcfids, "fcfids", 1 },
+ { &test_fcfidus, "fcfidus", 1 },
+ { &test_fcfidu, "fcfidu", 1 },
+ { NULL, NULL, 0 },
+
+};
+
+static vx_fp_test_t vx_fp_tests[] = {
+ { &test_xscmp, "xscmp", xscmpX_tests, 64, VX_FP_CMP},
+ { &test_xsadddp, "xsadddp", xsadddp_tests, 64, VX_FP_OTHER},
+ { &test_xsdivdp, "xsdivdp", xsdivdp_tests, 64, VX_FP_OTHER},
+ { &test_xsmadd, "xsmadd", xsmaddXdp_tests, 64, VX_FP_SMA},
+ { &test_xsmsub, "xsmsub", xsmsubXdp_tests, 64, VX_FP_SMS},
+ { &test_xsnmadd, "xsnmadd", xsnmaddXdp_tests, 64, VX_FP_SNMA},
+ { & test_xsmuldp, "xsmuldp", xsmuldp_tests, 64, VX_FP_OTHER},
+ { & test_xssubdp, "xssubdp", xssubdp_tests, 64, VX_FP_OTHER},
+ { NULL, NULL, NULL, 0, 0 }
+};
+
+static xs_conv_test_t xs_conv_tests[] = {
+ { &test_xscvdpsxds, "xscvdpsxds", xscvdpsxds_results, 15},
+ { &test_xscvsxddp, "xscvsxddp", xscvsxddp_results, 15},
+ { &test_xscvuxddp, "xscvuxddp", xscvuxddp_results, 15},
+ { NULL, NULL, NULL, 0}
+};
+
+#ifdef __powerpc64__
+static void test_ldbrx(void)
+{
+ int i, equality;
+ HWord_t reg_out;
+ unsigned char * byteIn, * byteOut;
+ r14 = (HWord_t)viargs;
+ // Just try the instruction an arbitrary number of times at different r15 offsets.
+ for (i = 0; i < 3; i++) {
+ int j, k;
+ reg_out = 0;
+ r15 = i * 4;
+ equality = 1;
+ __asm__ __volatile__ ("ldbrx %0, %1, %2" : "=r" (reg_out): "b" (r14),"r" (r15));
+ byteIn = ((unsigned char *)(r14 + r15));
+ byteOut = (unsigned char *)®_out;
+
+ printf("ldbrx:");
+ for (k = 0; k < 7; k++) {
+ printf( " %02x", (byteIn[k]));
+ }
+ printf(" (reverse) =>");
+ for (j = 0; j < 8; j++) {
+ printf( " %02x", (byteOut[j]));
+ }
+ printf("\n");
+ for (j = 0, k = 7; j < 8; j++, k--) {
+ equality &= (byteIn[k] == byteOut[j]);
+ }
+ if (!equality) {
+ printf("FAILED: load with byte reversal is incorrect\n");
+ errors++;
+ }
+ }
+ printf( "\n" );
+}
+
+static void
+test_popcntd(void)
+{
+ uint64_t res;
+ unsigned long long src = 0x9182736405504536ULL;
+ int i, answer = 0;
+ r14 = src;
+ __asm__ __volatile__ ("popcntd %0, %1" : "=r" (res): "r" (r14));
+ for (i = 0; i < 64; i++) {
+ answer += (r14 & 1ULL);
+ r14 = r14 >> 1;
+ }
+ printf("popcntd: 0x%llx => %d\n", src, (int)res);
+ if (res!= answer) {
+ printf("Error: unexpected result from popcntd\n");
+ errors++;
+ }
+ printf( "\n" );
+}
+#endif
+
+static void
+test_lfiwzx(void)
+{
+ unsigned int i;
+ unsigned int * src;
+ uint64_t reg_out;
+ r14 = (HWord_t)viargs;
+ // Just try the instruction an arbitrary number of times at different r15 offsets.
+ for (i = 0; i < 3; i++) {
+ reg_out = 0;
+ r15 = i * 4;
+ __asm__ __volatile__ ("lfiwzx %0, %1, %2" : "=d" (reg_out): "b" (r14),"r" (r15));
+ src = ((unsigned int *)(r14 + r15));
+ printf("lfiwzx: %u => %llu.00\n", *src, (unsigned long long)reg_out);
+
+ if (reg_out > 0xFFFFFFFFULL || *src != (unsigned int)reg_out) {
+ printf("FAILED: integer load to FP register is incorrect\n");
+ errors++;
+ }
+ }
+ printf( "\n" );
+}
+
+static void test_vx_fp_ops(void)
+{
+
+ test_func_t func;
+ int k;
+ char * test_name = (char *)malloc(20);
+ k = 0;
+
+ build_special_fargs_table();
+ while ((func = vx_fp_tests[k].test_func)) {
+ int i, condreg, repeat = 0;
+ unsigned int flags;
+ unsigned long long * frap, * frbp, * dst;
+ vx_fp_test_t test_group = vx_fp_tests[k];
+ vx_fp_test_type test_type = test_group.test_type;
+
+ switch (test_type) {
+ case VX_FP_CMP:
+ strcpy(test_name, "xscmp");
+ if (!repeat) {
+ repeat = 1;
+ strcat(test_name, "udp");
+ do_cmpudp = 1;
+ }
+ break;
+ case VX_FP_SMA:
+ case VX_FP_SMS:
+ case VX_FP_SNMA:
+ if (test_type == VX_FP_SMA)
+ strcpy(test_name, "xsmadd");
+ else if (test_type == VX_FP_SMS)
+ strcpy(test_name, "xsmsub");
+ else
+ strcpy(test_name, "xsnmadd");
+ if (!repeat) {
+ repeat = 1;
+ strcat(test_name, "adp");
+ do_adp = 1;
+ }
+ break;
+ case VX_FP_OTHER:
+ strcpy(test_name, test_group.name);
+ break;
+ default:
+ printf("ERROR: Invalid VX FP test type %d\n", test_type);
+ exit(1);
+ }
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * inA, * inB, * pv;
+
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (unsigned int *)&spec_fargs[aTest.fra_idx];
+ inB = (unsigned int *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+ memcpy(&vec_inA, inA, 8);
+ memcpy(&vec_inB, inB, 8);
+
+ switch (test_type) {
+ case VX_FP_CMP:
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ condreg = (flags & 0x0f000000) >> 24;
+ printf("#%d: %s %016llx <=> %016llx ? %x (CRx)\n", i, test_name, *frap, *frbp, condreg);
+ // printf("\tFRA: %e; FRB: %e\n", spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx]);
+ if ( condreg != aTest.cr_flags) {
+ printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, condreg);
+ errors++;
+ }
+ break;
+ case VX_FP_SMA:
+ case VX_FP_SMS:
+ case VX_FP_SNMA:
+ case VX_FP_OTHER:
+ {
+ int idx;
+ unsigned long long vsr_XT;
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (test_type != VX_FP_OTHER) {
+ /* Then we need a third src argument, which is stored in element 0 of
+ * VSX[XT] -- i.e., vec_out. For the xs<ZZZ>mdp cases, VSX[XT] holds
+ * src3 and VSX[XB] holds src2; for the xs<ZZZ>adp cases, VSX[XT] holds
+ * src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test
+ * data (input args, result) contain only two inputs, so I arbitrarily
+ * use spec_fargs elements 4 and 14 (alternating) for the third source
+ * argument. We can use the same input data for a given pair of
+ * adp/mdp-type instructions by swapping the src2 and src3 arguments; thus
+ * the expected result should be the same.
+ */
+ int extra_arg_idx;
+ if (i % 2)
+ extra_arg_idx = 4;
+ else
+ extra_arg_idx = 14;
+
+ //memcpy(&vec_out, &spec_fargs[14], 8);
+
+ if (repeat) {
+ /* We're on the first time through of one of the VX_FP_SMx
+ * test types, meaning we're testing a xs<ZZZ>adp case, thus we
+ * have to swap inputs as described above:
+ * src2 <= VSX[XT]
+ * src3 <= VSX[XB]
+ */
+ memcpy(&vec_out, inB, 8); // src2
+ memcpy(&vec_inB, &spec_fargs[extra_arg_idx], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[extra_arg_idx];
+ } else {
+ // Don't need to init src2, as it's done before the switch()
+ memcpy(&vec_out, &spec_fargs[extra_arg_idx], 8); //src3
+ }
+ memcpy(&vsr_XT, &vec_out, 8);
+ }
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (test_type == VX_FP_OTHER)
+ printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name, *frap, *frbp, *dst);
+ else
+ printf( "#%d: %s %016llx %016llx %016llx = %016llx\n", i,
+ test_name, vsr_XT, *frap, *frbp, *dst );
+
+ if ( *dst != aTest.dp_bin_result) {
+ printf("Error: Expected result %016llx; actual result %016llx\n", aTest.dp_bin_result, *dst);
+ errors++;
+ }
+ /*
+ {
+ // Debug code. Keep this block commented out except when debugging.
+ double result, expected;
+ memcpy(&result, dst, 8);
+ memcpy(&expected, &aTest.dp_bin_result, 8);
+ printf( "\tFRA + FRB: %e + %e: Expected = %e; Actual = %e\n",
+ spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx],
+ expected, result );
+ }
+ */
+ break;
+ }
+ }
+
+
+ }
+ printf( "\n" );
+
+ if (repeat) {
+ repeat = 0;
+ switch (test_type) {
+ case VX_FP_CMP:
+ strcpy(test_name, "xscmp");
+ strcat(test_name, "odp");
+ do_cmpudp = 0;
+ break;
+ case VX_FP_SMA:
+ case VX_FP_SMS:
+ case VX_FP_SNMA:
+ if (test_type == VX_FP_SMA)
+ strcpy(test_name, "xsmadd");
+ else if (test_type == VX_FP_SMS)
+ strcpy(test_name, "xsmsub");
+ else
+ strcpy(test_name, "xsnmadd");
+ strcat(test_name, "mdp");
+ do_adp = 0;
+ break;
+ case VX_FP_OTHER:
+ break;
+ }
+ goto again;
+ }
+ k++;
+ }
+ printf( "\n" );
+ free(test_name);
+}
+
+static void test_xs_conv_ops(void)
+{
+
+ test_func_t func;
+ int k = 0;
+
+ build_special_fargs_table();
+ while ((func = xs_conv_tests[k].test_func)) {
+ int i;
+ unsigned long long * frbp, * dst;
+ xs_conv_test_t test_group = xs_conv_tests[k];
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * inB, * pv;
+ int idx;
+ unsigned long long exp_result = test_group.results[i];
+ inB = (unsigned int *)&spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+ memcpy(&vec_inB, inB, 8);
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp, *dst);
+
+ if ( *dst != exp_result) {
+ printf("Error: Expected result %016llx; actual result %016llx\n", exp_result, *dst);
+ errors++;
+ }
+ }
+ k++;
+ printf("\n");
+ }
+ printf( "\n" );
+}
+
+static void do_load_test(ldst_test_t loadTest)
+{
+ test_func_t func;
+ unsigned int *src, *dst;
+ int splat = loadTest.type == VSX_LOAD_SPLAT ? 1: 0;
+ int i, j, m, equality;
+ i = j = 0;
+
+ func = loadTest.test_func;
+ for (i = 0, r14 = (HWord_t) loadTest.base_addr; i < NUM_VIARGS_VECS; i++) {
+ int again;
+ j = 0;
+ r14 += i * 16;
+ do {
+ unsigned int * pv = (unsigned int *)&vec_out;
+ int idx;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv+=idx)
+ *pv = 0;
+
+ again = 0;
+ r15 = j;
+
+ // execute test insn
+ (*func)();
+
+ src = (unsigned int*) (((unsigned char *)r14) + j);
+ dst = (unsigned int*) &vec_out;
+
+ printf( "%s:", loadTest.name);
+ for (m = 0; m < loadTest.num_words_to_process; m++) {
+ printf( " %08x", src[splat ? m % 2 : m]);
+ }
+ printf( " =>");
+ for (m = 0; m < loadTest.num_words_to_process; m++) {
+ printf( " %08x", dst[m]);
+ }
+ printf("\n");
+ equality = 1;
+ for (m = 0; m < loadTest.num_words_to_process; m++) {
+ equality = equality && (src[splat ? m % 2 : m] == dst[m]);
+ }
+
+ if (!equality) {
+ printf("FAILED: loaded vector is incorrect\n");
+ errors++;
+ }
+
+ if (j == 0 && loadTest.offset) {
+ again = 1;
+ j += loadTest.offset;
+ }
+ }
+ while (again);
+ }
+}
+
+static void
+do_store_test ( ldst_test_t storeTest )
+{
+ test_func_t func;
+ unsigned int *src, *dst;
+ int m, equality;
+
+ func = storeTest.test_func;
+ r14 = (HWord_t) storeTest.base_addr;
+ r15 = (HWord_t) storeTest.offset;
+ unsigned int * pv = (unsigned int *) storeTest.base_addr;
+ int idx;
+ // clear out storage destination
+ for (idx = 0; idx < 4; idx++, pv += idx)
+ *pv = 0;
+
+ memcpy(&vec_inA, &viargs[0], sizeof(vector unsigned char));
+
+ // execute test insn
+ (*func)();
+ src = &viargs[0];
+ dst = (unsigned int*) (((unsigned char *) r14) + storeTest.offset);
+
+ printf( "%s:", storeTest.name );
+ for (m = 0; m < storeTest.num_words_to_process; m++) {
+ printf( " %08x", src[m] );
+ }
+ printf( " =>" );
+ for (m = 0; m < storeTest.num_words_to_process; m++) {
+ printf( " %08x", dst[m] );
+ }
+ printf( "\n" );
+ equality = 1;
+ for (m = 0; m < storeTest.num_words_to_process; m++) {
+ equality = equality && (src[m] == dst[m]);
+ }
+
+ if (!equality) {
+ printf( "FAILED: vector store result is incorrect\n" );
+ errors++;
+ }
+
+}
+
+
+static void test_ldst(void)
+{
+ int k = 0;
+
+ while (ldst_tests[k].test_func) {
+ if (ldst_tests[k].type == VSX_STORE)
+ do_store_test(ldst_tests[k]);
+ else
+ do_load_test(ldst_tests[k]);
+ k++;
+ printf("\n");
+ }
+}
+
+static void test_ftdiv(void)
+{
+ int i, num_tests, crx;
+ unsigned int flags;
+ unsigned long long * frap, * frbp;
+ build_special_fargs_table();
+
+ num_tests = sizeof ftdiv_tests/sizeof ftdiv_tests[0];
+
+ for (i = 0; i < num_tests; i++) {
+ ftdiv_test_args_t aTest = ftdiv_tests[i];
+ f14 = spec_fargs[aTest.fra_idx];
+ f15 = spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("ftdiv cr1, %0, %1" : : "d" (f14), "d" (f15));
+ GET_CR(flags);
+ crx = (flags & 0x0f000000) >> 24;
+ printf( "ftdiv: %016llx <=> %016llx ? %x (CRx)\n", *frap, *frbp, crx);
+// printf("\tFRA: %e; FRB: %e\n", f14, f15);
+ if ( crx != aTest.cr_flags) {
+ printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, crx);
+ errors++;
+ }
+ }
+ printf( "\n" );
+}
+
+
+static void test_p7_fpops ( void )
+{
+ int k = 0;
+ test_func_t func;
+
+ build_fargs_table();
+ while ((func = fp_tests[k].test_func)) {
+ float res;
+ double resd;
+ unsigned long long u0;
+ int i;
+ int res32 = strcmp(fp_tests[k].name, "fcfidu");
+
+ for (i = 0; i < nb_fargs; i++) {
+ u0 = *(unsigned long long *) (&fargs[i]);
+ f14 = fargs[i];
+ (*func)();
+ if (res32) {
+ res = f17;
+ printf( "%s %016llx => (raw sp) %08x)",
+ fp_tests[k].name, u0, *((unsigned int *)&res));
+ } else {
+ resd = f17;
+ printf( "%s %016llx => (raw sp) %016llx)",
+ fp_tests[k].name, u0, *(unsigned long long *)(&resd));
+ }
+ printf( "\n" );
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_vsx_logic(void)
+{
+ logic_test_t aTest;
+ test_func_t func;
+ int equality, k;
+ k = 0;
+
+ while ((func = logic_tests[k].test_func)) {
+ unsigned int * pv;
+ int startA, startB;
+ unsigned int * inA, * inB, * dst;
+ int idx, i;
+ startA = 0;
+ aTest = logic_tests[k];
+ for (i = 0; i <= (NUM_VIARGS_INTS - (NUM_VIARGS_VECS * sizeof(int))); i++, startA++) {
+ startB = startA + 4;
+ pv = (unsigned int *)&vec_out;
+ inA = &viargs[startA];
+ inB = &viargs[startB];
+ memcpy(&vec_inA, inA, sizeof(vector unsigned char));
+ memcpy(&vec_inB, inB, sizeof(vector unsigned char));
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ (*func)();
+ dst = (unsigned int*) &vec_out;
+
+ printf( "%s:", aTest.name);
+ printf( " %08x %08x %08x %08x %s", inA[0], inA[1], inA[2], inA[3], aTest.name);
+ printf( " %08x %08x %08x %08x", inB[0], inB[1], inB[2], inB[3]);
+ printf(" => %08x %08x %08x %08x\n", dst[0], dst[1], dst[2], dst[3]);
+
+ equality = 1;
+ for (idx = 0; idx < 4; idx++) {
+ switch (aTest.op) {
+ case VSX_AND:
+ equality &= (dst[idx] == (inA[idx] & inB[idx]));
+ break;
+ case VSX_ANDC:
+ equality &= (dst[idx] == (inA[idx] & ~inB[idx]));
+ break;
+ case VSX_NOR:
+ equality &= (dst[idx] == ~(inA[idx] | inB[idx]));
+ break;
+ case VSX_XOR:
+ equality &= (dst[idx] == (inA[idx] ^ inB[idx]));
+ break;
+ case VSX_OR:
+ equality &= (dst[idx] == (inA[idx] | inB[idx]));
+ break;
+ default:
+ fprintf(stderr, "Error in test_vsx_logic(): unknown VSX logical op %d\n", aTest.op);
+ exit(1);
+ }
+ }
+ if (!equality) {
+ printf( "FAILED: vector out is incorrect\n" );
+ errors++;
+ }
+ }
+ k++;
+ }
+ printf( "\n" );
+}
+
+static void test_move_ops (void)
+{
+ move_test_t aTest;
+ test_func_t func;
+ int equality, k;
+ k = 0;
+
+ while ((func = move_tests[k].test_func)) {
+ unsigned int * pv;
+ int startA, startB;
+ unsigned int * inA, * inB, * dst;
+ unsigned long long exp_out;
+ int idx;
+ aTest = move_tests[k];
+ exp_out = aTest.expected_result;
+ startA = aTest.xa_idx;
+ startB = aTest.xb_idx;
+ pv = (unsigned int *)&vec_out;
+ inA = &viargs[startA];
+ inB = &viargs[startB];
+ memcpy(&vec_inA, inA, sizeof(vector unsigned char));
+ memcpy(&vec_inB, inB, sizeof(vector unsigned char));
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ (*func)();
+ dst = (unsigned int*) &vec_out;
+
+ printf( "%s:", aTest.name);
+ printf( " %08x %08x %s", inA[0], inA[1], aTest.name);
+ printf( " %08x %08xx", inB[0], inB[1]);
+ printf(" => %08x %08x\n", dst[0], dst[1]);
+
+ equality = 1;
+ pv = (unsigned int *)&exp_out;
+ for (idx = 0; idx < 2; idx++) {
+ equality &= (dst[idx] == pv[idx]);
+ }
+ if (!equality) {
+ printf( "FAILED: vector out is incorrect\n" );
+ errors++;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_permute_ops (void)
+{
+ permute_test_t *aTest;
+ unsigned int *dst = (unsigned int *) &vec_out;
+
+ for (aTest = &(permute_tests[0]); aTest->test_func != NULL; aTest++)
+ {
+ /* Grab test input and clear output vector. */
+ memcpy(&vec_inA, aTest->xa, sizeof(vec_inA));
+ memcpy(&vec_inB, aTest->xb, sizeof(vec_inB));
+ memset(dst, 0, sizeof(vec_out));
+
+ /* execute test insn */
+ aTest->test_func();
+
+ printf( "%s:\n", aTest->name);
+ printf( " XA[%08x,%08x,%08x,%08x]\n",
+ aTest->xa[0], aTest->xa[1], aTest->xa[2], aTest->xa[3]);
+ printf( " XB[%08x,%08x,%08x,%08x]\n",
+ aTest->xb[0], aTest->xb[1], aTest->xb[2], aTest->xb[3]);
+ printf( " => XT[%08x,%08x,%08x,%08x]\n",
+ dst[0], dst[1], dst[2], dst[3]);
+
+ if (memcmp (dst, &aTest->expected_output, sizeof(vec_out)))
+ {
+ printf( "FAILED: vector out is incorrect\n" );
+ errors++;
+ }
+ }
+ printf( "\n" );
+}
+
+static test_table_t all_tests[] = { { &test_ldst,
+ "Test VSX load/store instructions" },
+ { &test_vsx_logic,
+ "Test VSX logic instructions" },
+#ifdef __powerpc64__
+ { &test_ldbrx,
+ "Test ldbrx instruction" },
+ { &test_popcntd,
+ "Test popcntd instruction" },
+#endif
+ { &test_lfiwzx,
+ "Test lfiwzx instruction" },
+ { &test_p7_fpops,
+ "Test P7 floating point convert instructions"},
+ { &test_ftdiv,
+ "Test ftdiv instruction" },
+ { &test_move_ops,
+ "Test VSX move instructions"},
+ { &test_permute_ops,
+ "Test VSX permute instructions"},
+ { &test_vx_fp_ops,
+ "Test VSX floating point instructions"},
+ { &test_xs_conv_ops,
+ "Test VSX scalar integer conversion instructions" },
+ { NULL, NULL }
+};
+#endif // HAS_VSX
+
+int main(int argc, char *argv[])
+{
+#ifdef HAS_VSX
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+ if (errors)
+ printf("Testcase FAILED with %d errors \n", errors);
+ else
+ printf("Testcase PASSED\n");
+
+#endif // HAS _VSX
+
+ return 0;
+}
diff --git a/main/none/tests/ppc64/test_isa_2_06_part1.stderr.exp b/main/none/tests/ppc64/test_isa_2_06_part1.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part1.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc64/test_isa_2_06_part1.stdout.exp b/main/none/tests/ppc64/test_isa_2_06_part1.stdout.exp
new file mode 100644
index 0000000..d234f79
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part1.stdout.exp
@@ -0,0 +1,1031 @@
+Test VSX load/store instructions
+lxsdx: 01234567 89abcdef => 01234567 89abcdef
+lxsdx: 8899aabb 91929394 => 8899aabb 91929394
+
+lxsdx: 01234567 89abcdef => 01234567 89abcdef
+lxsdx: 89abcdef 00112233 => 89abcdef 00112233
+lxsdx: 8899aabb 91929394 => 8899aabb 91929394
+lxsdx: 91929394 a1a2a3a4 => 91929394 a1a2a3a4
+
+lxvd2x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 8899aabb 91929394 a1a2a3a4 b1b2b3b4
+
+lxvd2x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+lxvd2x: 89abcdef 00112233 44556677 8899aabb => 89abcdef 00112233 44556677 8899aabb
+lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 8899aabb 91929394 a1a2a3a4 b1b2b3b4
+lxvd2x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4
+
+lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef
+lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394
+
+lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef
+lxvdsx: 89abcdef 00112233 89abcdef 00112233 => 89abcdef 00112233 89abcdef 00112233
+lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394
+lxvdsx: 91929394 a1a2a3a4 91929394 a1a2a3a4 => 91929394 a1a2a3a4 91929394 a1a2a3a4
+
+lxvw4x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 8899aabb 91929394 a1a2a3a4 b1b2b3b4
+
+lxvw4x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+lxvw4x: 89abcdef 00112233 44556677 8899aabb => 89abcdef 00112233 44556677 8899aabb
+lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 8899aabb 91929394 a1a2a3a4 b1b2b3b4
+lxvw4x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4
+
+stxsdx: 01234567 89abcdef => 01234567 89abcdef
+
+stxsdx: 01234567 89abcdef => 01234567 89abcdef
+
+stxvd2x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+
+stxvd2x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+
+stxvw4x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+
+stxvw4x: 01234567 89abcdef 00112233 44556677 => 01234567 89abcdef 00112233 44556677
+
+Test VSX logic instructions
+xxlxor: 01234567 89abcdef 00112233 44556677 xxlxor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89baefdc 18395e7b a1b38197 f5e7d5c3
+xxlxor: 89abcdef 00112233 44556677 8899aabb xxlxor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 18395e7b a1b38197 f5e7d5c3 495b697f
+xxlxor: 00112233 44556677 8899aabb 91929394 xxlxor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b38197 f5e7d5c3 495b697f 40404040
+xxlxor: 44556677 8899aabb 91929394 a1a2a3a4 xxlxor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5e7d5c3 495b697f 40404040 dbc9fe9a
+xxlor: 01234567 89abcdef 00112233 44556677 xxlor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89bbefff 99bbdfff a1b3a3b7 f5f7f7f7
+xxlor: 89abcdef 00112233 44556677 8899aabb xxlor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 99bbdfff a1b3a3b7 f5f7f7f7 c9dbebff
+xxlor: 00112233 44556677 8899aabb 91929394 xxlor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b3a3b7 f5f7f7f7 c9dbebff d1d2d3d4
+xxlor: 44556677 8899aabb 91929394 a1a2a3a4 xxlor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5f7f7f7 c9dbebff d1d2d3d4 fbebffbe
+xxlnor: 01234567 89abcdef 00112233 44556677 xxlnor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 76441000 66442000 5e4c5c48 0a080808
+xxlnor: 89abcdef 00112233 44556677 8899aabb xxlnor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 66442000 5e4c5c48 0a080808 36241400
+xxlnor: 00112233 44556677 8899aabb 91929394 xxlnor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 5e4c5c48 0a080808 36241400 2e2d2c2b
+xxlnor: 44556677 8899aabb 91929394 a1a2a3a4 xxlnor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 0a080808 36241400 2e2d2c2b 04140041
+xxland: 01234567 89abcdef 00112233 44556677 xxland 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 00010023 81828184 00002220 00102234
+xxland: 89abcdef 00112233 44556677 8899aabb xxland 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 81828184 00002220 00102234 80808280
+xxland: 00112233 44556677 8899aabb 91929394 xxland a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00002220 00102234 80808280 91929394
+xxland: 44556677 8899aabb 91929394 a1a2a3a4 xxland b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 00102234 80808280 91929394 20220124
+xxlandc: 01234567 89abcdef 00112233 44556677 xxlandc 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 01224544 08294c6b 00110013 44454443
+xxlandc: 89abcdef 00112233 44556677 8899aabb xxlandc 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 08294c6b 00110013 44454443 0819283b
+xxlandc: 00112233 44556677 8899aabb 91929394 xxlandc a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00110013 44454443 0819283b 00000000
+xxlandc: 44556677 8899aabb 91929394 a1a2a3a4 xxlandc b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 44454443 0819283b 00000000 8180a280
+
+Test ldbrx instruction
+ldbrx: 01 23 45 67 89 ab cd (reverse) => ef cd ab 89 67 45 23 01
+ldbrx: 89 ab cd ef 00 11 22 (reverse) => 33 22 11 00 ef cd ab 89
+ldbrx: 00 11 22 33 44 55 66 (reverse) => 77 66 55 44 33 22 11 00
+
+Test popcntd instruction
+popcntd: 0x9182736405504536 => 24
+
+Test lfiwzx instruction
+lfiwzx: 19088743 => 19088743.00
+lfiwzx: 2309737967 => 2309737967.00
+lfiwzx: 1122867 => 1122867.00
+
+Test P7 floating point convert instructions
+fcfids 0010000000000001 => (raw sp) 59800000)
+fcfids 00100094e0000359 => (raw sp) 598004a7)
+fcfids 3fe0000000000001 => (raw sp) 5e7f8000)
+fcfids 3fe00094e0000359 => (raw sp) 5e7f8002)
+fcfids 8010000000000001 => (raw sp) deffe000)
+fcfids 80100094e0000359 => (raw sp) deffdfff)
+fcfids bfe0000000000001 => (raw sp) de804000)
+fcfids bfe00094e0000359 => (raw sp) de803fff)
+fcfids 0020000000000b01 => (raw sp) 5a000000)
+fcfids 00000000203f0b3d => (raw sp) 4e00fc2d)
+fcfids 00000000005a203d => (raw sp) 4ab4407a)
+fcfids 8020000000000b01 => (raw sp) deffc000)
+fcfids 80000000203f0b3d => (raw sp) df000000)
+
+fcfidus 0010000000000001 => (raw sp) 59800000)
+fcfidus 00100094e0000359 => (raw sp) 598004a7)
+fcfidus 3fe0000000000001 => (raw sp) 5e7f8000)
+fcfidus 3fe00094e0000359 => (raw sp) 5e7f8002)
+fcfidus 8010000000000001 => (raw sp) 5f001000)
+fcfidus 80100094e0000359 => (raw sp) 5f001001)
+fcfidus bfe0000000000001 => (raw sp) 5f3fe000)
+fcfidus bfe00094e0000359 => (raw sp) 5f3fe001)
+fcfidus 0020000000000b01 => (raw sp) 5a000000)
+fcfidus 00000000203f0b3d => (raw sp) 4e00fc2d)
+fcfidus 00000000005a203d => (raw sp) 4ab4407a)
+fcfidus 8020000000000b01 => (raw sp) 5f002000)
+fcfidus 80000000203f0b3d => (raw sp) 5f000000)
+
+fcfidu 0010000000000001 => (raw sp) 4330000000000001)
+fcfidu 00100094e0000359 => (raw sp) 43300094e0000359)
+fcfidu 3fe0000000000001 => (raw sp) 43cff00000000000)
+fcfidu 3fe00094e0000359 => (raw sp) 43cff0004a700002)
+fcfidu 8010000000000001 => (raw sp) 43e0020000000000)
+fcfidu 80100094e0000359 => (raw sp) 43e00200129c0000)
+fcfidu bfe0000000000001 => (raw sp) 43e7fc0000000000)
+fcfidu bfe00094e0000359 => (raw sp) 43e7fc00129c0000)
+fcfidu 0020000000000b01 => (raw sp) 4340000000000580)
+fcfidu 00000000203f0b3d => (raw sp) 41c01f859e800000)
+fcfidu 00000000005a203d => (raw sp) 4156880f40000000)
+fcfidu 8020000000000b01 => (raw sp) 43e0040000000001)
+fcfidu 80000000203f0b3d => (raw sp) 43e00000000407e1)
+
+Test ftdiv instruction
+ftdiv: 3fd8000000000000 <=> 404f000000000000 ? 8 (CRx)
+ftdiv: 7ff7ffffffffffff <=> 404f000000000000 ? a (CRx)
+ftdiv: 404f000000000000 <=> fff8000000000000 ? a (CRx)
+ftdiv: 3fd8000000000000 <=> 0018000000b77501 ? a (CRx)
+ftdiv: 404f000000000000 <=> 7fe800000000051b ? a (CRx)
+ftdiv: 7fe800000000051b <=> 3fd8000000000000 ? a (CRx)
+ftdiv: 3fd8000000000000 <=> 7fe800000000051b ? a (CRx)
+ftdiv: 0123214569900000 <=> 3fd8000000000000 ? a (CRx)
+ftdiv: 7ff0000000000000 <=> 404f000000000000 ? e (CRx)
+ftdiv: fff0000000000000 <=> 404f000000000000 ? e (CRx)
+ftdiv: 404f000000000000 <=> 7ff0000000000000 ? e (CRx)
+ftdiv: 3fd8000000000000 <=> 8008340000078000 ? e (CRx)
+ftdiv: 0000000000000000 <=> 0000000000000000 ? e (CRx)
+ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
+
+Test VSX move instructions
+xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394
+
+xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef
+
+xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb
+
+xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4
+
+Test VSX permute instructions
+xxmrghw:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[11111111,55555555,22222222,66666666]
+xxmrghw:
+ XA[00112233,44556677,8899aabb,ccddeeff]
+ XB[11111111,22222222,33333333,44444444]
+ => XT[00112233,11111111,44556677,22222222]
+xxmrglw:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[33333333,77777777,44444444,88888888]
+xxmrglw:
+ XA[00112233,44556677,8899aabb,ccddeeff]
+ XB[11111111,22222222,33333333,44444444]
+ => XT[8899aabb,33333333,ccddeeff,44444444]
+xxpermdi DM=00:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[11111111,22222222,55555555,66666666]
+xxpermdi DM=01:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[11111111,22222222,77777777,88888888]
+xxpermdi DM=10:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[33333333,44444444,55555555,66666666]
+xxpermdi DM=11:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[33333333,44444444,77777777,88888888]
+xxsldwi SHW=0:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[11111111,22222222,33333333,44444444]
+xxsldwi SHW=1:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[22222222,33333333,44444444,55555555]
+xxsldwi SHW=2:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[33333333,44444444,55555555,66666666]
+xxsldwi SHW=3:
+ XA[11111111,22222222,33333333,44444444]
+ XB[55555555,66666666,77777777,88888888]
+ => XT[44444444,55555555,66666666,77777777]
+
+Test VSX floating point instructions
+#0: xscmpudp fff0000000000000 <=> fff0000000000000 ? 2 (CRx)
+#1: xscmpudp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx)
+#2: xscmpudp fff0000000000000 <=> 8000000000000000 ? 8 (CRx)
+#3: xscmpudp fff0000000000000 <=> 0000000000000000 ? 8 (CRx)
+#4: xscmpudp fff0000000000000 <=> 0123214569900000 ? 8 (CRx)
+#5: xscmpudp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#6: xscmpudp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#7: xscmpudp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#8: xscmpudp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx)
+#9: xscmpudp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx)
+#10: xscmpudp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx)
+#11: xscmpudp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx)
+#12: xscmpudp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx)
+#13: xscmpudp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx)
+#14: xscmpudp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx)
+#15: xscmpudp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx)
+#16: xscmpudp 8000000000000000 <=> fff0000000000000 ? 4 (CRx)
+#17: xscmpudp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#18: xscmpudp 8000000000000000 <=> 8000000000000000 ? 2 (CRx)
+#19: xscmpudp 8000000000000000 <=> 0000000000000000 ? 2 (CRx)
+#20: xscmpudp 8000000000000000 <=> 0123214569900000 ? 8 (CRx)
+#21: xscmpudp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#22: xscmpudp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#23: xscmpudp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#24: xscmpudp 0000000000000000 <=> fff0000000000000 ? 4 (CRx)
+#25: xscmpudp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#26: xscmpudp 0000000000000000 <=> 8000000000000000 ? 2 (CRx)
+#27: xscmpudp 0000000000000000 <=> 0000000000000000 ? 2 (CRx)
+#28: xscmpudp 0000000000000000 <=> 0123214569900000 ? 8 (CRx)
+#29: xscmpudp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#30: xscmpudp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#31: xscmpudp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#32: xscmpudp 0123214569900000 <=> fff0000000000000 ? 4 (CRx)
+#33: xscmpudp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#34: xscmpudp 0123214569900000 <=> 8000000000000000 ? 4 (CRx)
+#35: xscmpudp 0123214569900000 <=> 0000000000000000 ? 4 (CRx)
+#36: xscmpudp 0123214569900000 <=> 404f000000000000 ? 8 (CRx)
+#37: xscmpudp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx)
+#38: xscmpudp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#39: xscmpudp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx)
+#40: xscmpudp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx)
+#41: xscmpudp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#42: xscmpudp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx)
+#43: xscmpudp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx)
+#44: xscmpudp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx)
+#45: xscmpudp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx)
+#46: xscmpudp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#47: xscmpudp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#48: xscmpudp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx)
+#49: xscmpudp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx)
+#50: xscmpudp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx)
+#51: xscmpudp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx)
+#52: xscmpudp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx)
+#53: xscmpudp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx)
+#54: xscmpudp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx)
+#55: xscmpudp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx)
+#56: xscmpudp fff8000000000000 <=> fff0000000000000 ? 1 (CRx)
+#57: xscmpudp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx)
+#58: xscmpudp fff8000000000000 <=> 8000000000000000 ? 1 (CRx)
+#59: xscmpudp fff8000000000000 <=> 0000000000000000 ? 1 (CRx)
+#60: xscmpudp fff8000000000000 <=> 0123214569900000 ? 1 (CRx)
+#61: xscmpudp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx)
+#62: xscmpudp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#63: xscmpudp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+
+#0: xscmpodp fff0000000000000 <=> fff0000000000000 ? 2 (CRx)
+#1: xscmpodp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx)
+#2: xscmpodp fff0000000000000 <=> 8000000000000000 ? 8 (CRx)
+#3: xscmpodp fff0000000000000 <=> 0000000000000000 ? 8 (CRx)
+#4: xscmpodp fff0000000000000 <=> 0123214569900000 ? 8 (CRx)
+#5: xscmpodp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#6: xscmpodp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#7: xscmpodp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#8: xscmpodp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx)
+#9: xscmpodp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx)
+#10: xscmpodp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx)
+#11: xscmpodp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx)
+#12: xscmpodp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx)
+#13: xscmpodp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx)
+#14: xscmpodp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx)
+#15: xscmpodp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx)
+#16: xscmpodp 8000000000000000 <=> fff0000000000000 ? 4 (CRx)
+#17: xscmpodp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#18: xscmpodp 8000000000000000 <=> 8000000000000000 ? 2 (CRx)
+#19: xscmpodp 8000000000000000 <=> 0000000000000000 ? 2 (CRx)
+#20: xscmpodp 8000000000000000 <=> 0123214569900000 ? 8 (CRx)
+#21: xscmpodp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#22: xscmpodp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#23: xscmpodp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#24: xscmpodp 0000000000000000 <=> fff0000000000000 ? 4 (CRx)
+#25: xscmpodp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#26: xscmpodp 0000000000000000 <=> 8000000000000000 ? 2 (CRx)
+#27: xscmpodp 0000000000000000 <=> 0000000000000000 ? 2 (CRx)
+#28: xscmpodp 0000000000000000 <=> 0123214569900000 ? 8 (CRx)
+#29: xscmpodp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
+#30: xscmpodp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#31: xscmpodp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#32: xscmpodp 0123214569900000 <=> fff0000000000000 ? 4 (CRx)
+#33: xscmpodp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#34: xscmpodp 0123214569900000 <=> 8000000000000000 ? 4 (CRx)
+#35: xscmpodp 0123214569900000 <=> 0000000000000000 ? 4 (CRx)
+#36: xscmpodp 0123214569900000 <=> 404f000000000000 ? 8 (CRx)
+#37: xscmpodp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx)
+#38: xscmpodp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#39: xscmpodp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx)
+#40: xscmpodp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx)
+#41: xscmpodp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
+#42: xscmpodp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx)
+#43: xscmpodp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx)
+#44: xscmpodp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx)
+#45: xscmpodp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx)
+#46: xscmpodp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#47: xscmpodp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+#48: xscmpodp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx)
+#49: xscmpodp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx)
+#50: xscmpodp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx)
+#51: xscmpodp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx)
+#52: xscmpodp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx)
+#53: xscmpodp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx)
+#54: xscmpodp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx)
+#55: xscmpodp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx)
+#56: xscmpodp fff8000000000000 <=> fff0000000000000 ? 1 (CRx)
+#57: xscmpodp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx)
+#58: xscmpodp fff8000000000000 <=> 8000000000000000 ? 1 (CRx)
+#59: xscmpodp fff8000000000000 <=> 0000000000000000 ? 1 (CRx)
+#60: xscmpodp fff8000000000000 <=> 0123214569900000 ? 1 (CRx)
+#61: xscmpodp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx)
+#62: xscmpodp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
+#63: xscmpodp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx)
+
+#0: xsadddp fff0000000000000 fff0000000000000 = fff0000000000000
+#1: xsadddp fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#2: xsadddp fff0000000000000 8000000000000000 = fff0000000000000
+#3: xsadddp fff0000000000000 0000000000000000 = fff0000000000000
+#4: xsadddp fff0000000000000 0123214569900000 = fff0000000000000
+#5: xsadddp fff0000000000000 7ff0000000000000 = 7ff8000000000000
+#6: xsadddp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsadddp fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsadddp c0d0650f5a07b353 fff0000000000000 = fff0000000000000
+#9: xsadddp c0d0650f5a07b353 c0d0650f5a07b353 = c0e0650f5a07b353
+#10: xsadddp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353
+#11: xsadddp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353
+#12: xsadddp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
+#13: xsadddp c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000
+#14: xsadddp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsadddp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsadddp 8000000000000000 fff0000000000000 = fff0000000000000
+#17: xsadddp 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
+#18: xsadddp 8000000000000000 8000000000000000 = 8000000000000000
+#19: xsadddp 8000000000000000 0000000000000000 = 0000000000000000
+#20: xsadddp 8000000000000000 0123214569900000 = 0123214569900000
+#21: xsadddp 8000000000000000 7ff0000000000000 = 7ff0000000000000
+#22: xsadddp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsadddp 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsadddp 0000000000000000 fff0000000000000 = fff0000000000000
+#25: xsadddp 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
+#26: xsadddp 0000000000000000 8000000000000000 = 0000000000000000
+#27: xsadddp 0000000000000000 0000000000000000 = 0000000000000000
+#28: xsadddp 0000000000000000 0123214569900000 = 0123214569900000
+#29: xsadddp 0000000000000000 7ff0000000000000 = 7ff0000000000000
+#30: xsadddp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsadddp 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsadddp 0123214569900000 fff0000000000000 = fff0000000000000
+#33: xsadddp 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353
+#34: xsadddp 0123214569900000 8000000000000000 = 0123214569900000
+#35: xsadddp 0123214569900000 0000000000000000 = 0123214569900000
+#36: xsadddp 0123214569900000 404f000000000000 = 404f000000000000
+#37: xsadddp 0123214569900000 7ff0000000000000 = 7ff0000000000000
+#38: xsadddp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsadddp 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsadddp 7ff0000000000000 fff0000000000000 = 7ff8000000000000
+#41: xsadddp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#42: xsadddp 7ff0000000000000 8000000000000000 = 7ff0000000000000
+#43: xsadddp 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xsadddp 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xsadddp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
+#46: xsadddp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsadddp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsadddp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsadddp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsadddp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsadddp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsadddp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsadddp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsadddp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsadddp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsadddp fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsadddp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsadddp fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsadddp fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsadddp fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsadddp fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsadddp fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsadddp fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsdivdp fff0000000000000 fff0000000000000 = 7ff8000000000000
+#1: xsdivdp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#2: xsdivdp fff0000000000000 8000000000000000 = 7ff0000000000000
+#3: xsdivdp fff0000000000000 0000000000000000 = fff0000000000000
+#4: xsdivdp fff0000000000000 0123214569900000 = fff0000000000000
+#5: xsdivdp fff0000000000000 7ff0000000000000 = 7ff8000000000000
+#6: xsdivdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsdivdp fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsdivdp c0d0650f5a07b353 fff0000000000000 = 0000000000000000
+#9: xsdivdp c0d0650f5a07b353 c0d0650f5a07b353 = 3ff0000000000000
+#10: xsdivdp c0d0650f5a07b353 8000000000000000 = 7ff0000000000000
+#11: xsdivdp c0d0650f5a07b353 0000000000000000 = fff0000000000000
+#12: xsdivdp c0d0650f5a07b353 0123214569900000 = ff9b6cb57ca13c00
+#13: xsdivdp c0d0650f5a07b353 7ff0000000000000 = 8000000000000000
+#14: xsdivdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsdivdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsdivdp 8000000000000000 fff0000000000000 = 0000000000000000
+#17: xsdivdp 8000000000000000 c0d0650f5a07b353 = 0000000000000000
+#18: xsdivdp 8000000000000000 8000000000000000 = 7ff8000000000000
+#19: xsdivdp 8000000000000000 0000000000000000 = 7ff8000000000000
+#20: xsdivdp 8000000000000000 0123214569900000 = 8000000000000000
+#21: xsdivdp 8000000000000000 7ff0000000000000 = 8000000000000000
+#22: xsdivdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsdivdp 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsdivdp 0000000000000000 fff0000000000000 = 8000000000000000
+#25: xsdivdp 0000000000000000 c0d0650f5a07b353 = 8000000000000000
+#26: xsdivdp 0000000000000000 8000000000000000 = 7ff8000000000000
+#27: xsdivdp 0000000000000000 0000000000000000 = 7ff8000000000000
+#28: xsdivdp 0000000000000000 0123214569900000 = 0000000000000000
+#29: xsdivdp 0000000000000000 7ff0000000000000 = 0000000000000000
+#30: xsdivdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsdivdp 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsdivdp 0123214569900000 fff0000000000000 = 8000000000000000
+#33: xsdivdp 0123214569900000 c0d0650f5a07b353 = 8042ab59d8b6ec87
+#34: xsdivdp 0123214569900000 8000000000000000 = fff0000000000000
+#35: xsdivdp 0123214569900000 0000000000000000 = 7ff0000000000000
+#36: xsdivdp 0123214569900000 404f000000000000 = 00c3bf3f64b5ad6b
+#37: xsdivdp 0123214569900000 7ff0000000000000 = 0000000000000000
+#38: xsdivdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsdivdp 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsdivdp 7ff0000000000000 fff0000000000000 = 7ff8000000000000
+#41: xsdivdp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#42: xsdivdp 7ff0000000000000 8000000000000000 = fff0000000000000
+#43: xsdivdp 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xsdivdp 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xsdivdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
+#46: xsdivdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsdivdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsdivdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsdivdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsdivdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsdivdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsdivdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsdivdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsdivdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsdivdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsdivdp fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsdivdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsdivdp fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsdivdp fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsdivdp fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsdivdp fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsdivdp fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsdivdp fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
+#1: xsmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
+#2: xsmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#3: xsmaddadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000
+#4: xsmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#5: xsmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#6: xsmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#7: xsmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#8: xsmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = fff0000000000000
+#9: xsmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
+#10: xsmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#11: xsmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
+#12: xsmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#13: xsmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = 7ff0000000000000
+#14: xsmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
+#15: xsmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
+#16: xsmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = fff0000000000000
+#17: xsmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = c0d0650f5a07b353
+#18: xsmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000
+#19: xsmaddadp 0000000000000000 8000000000000000 0123214569900000 = 0000000000000000
+#20: xsmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 0123214569900000
+#21: xsmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = 7ff0000000000000
+#22: xsmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#23: xsmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
+#24: xsmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = fff0000000000000
+#25: xsmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = c0d0650f5a07b353
+#26: xsmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 8000000000000000
+#27: xsmaddadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000
+#28: xsmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 0123214569900000
+#29: xsmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = 7ff0000000000000
+#30: xsmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#31: xsmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
+#32: xsmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = fff0000000000000
+#33: xsmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = c0d0650f5a07b353
+#34: xsmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
+#35: xsmaddadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000
+#36: xsmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = 404f000000000000
+#37: xsmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = 7ff0000000000000
+#38: xsmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
+#39: xsmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
+#40: xsmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#41: xsmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#42: xsmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#43: xsmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#44: xsmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#45: xsmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#46: xsmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#47: xsmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
+#48: xsmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#49: xsmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#50: xsmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#51: xsmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#52: xsmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#53: xsmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#54: xsmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#55: xsmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#56: xsmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#57: xsmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#58: xsmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#59: xsmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#60: xsmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#61: xsmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#62: xsmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#63: xsmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+
+#0: xsmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000
+#1: xsmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#2: xsmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000
+#3: xsmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000
+#4: xsmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
+#5: xsmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000
+#6: xsmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = fff0000000000000
+#9: xsmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c0d0650f5a07b353
+#10: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7
+#11: xsmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f
+#12: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7
+#13: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000
+#14: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = fff0000000000000
+#17: xsmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
+#18: xsmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000
+#19: xsmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 0000000000000000
+#20: xsmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 0123214569900000
+#21: xsmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = 7ff0000000000000
+#22: xsmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = fff0000000000000
+#25: xsmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
+#26: xsmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 8000000000000000
+#27: xsmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000
+#28: xsmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 0123214569900000
+#29: xsmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = 7ff0000000000000
+#30: xsmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = fff0000000000000
+#33: xsmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353
+#34: xsmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f
+#35: xsmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000
+#36: xsmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = 404f000000000000
+#37: xsmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = 7ff0000000000000
+#38: xsmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = fff0000000000000
+#41: xsmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#42: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000
+#43: xsmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
+#45: xsmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
+#46: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsmsubadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#1: xsmsubadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
+#2: xsmsubadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#3: xsmsubadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000
+#4: xsmsubadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#5: xsmsubadp 7ff0000000000000 fff0000000000000 0123214569900000 = fff0000000000000
+#6: xsmsubadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#7: xsmsubadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#8: xsmsubadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000
+#9: xsmsubadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353
+#10: xsmsubadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#11: xsmsubadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
+#12: xsmsubadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#13: xsmsubadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000
+#14: xsmsubadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
+#15: xsmsubadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
+#16: xsmsubadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#17: xsmsubadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353
+#18: xsmsubadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000
+#19: xsmsubadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000
+#20: xsmsubadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000
+#21: xsmsubadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000
+#22: xsmsubadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#23: xsmsubadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
+#24: xsmsubadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#25: xsmsubadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353
+#26: xsmsubadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000
+#27: xsmsubadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000
+#28: xsmsubadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000
+#29: xsmsubadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000
+#30: xsmsubadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#31: xsmsubadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
+#32: xsmsubadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000
+#33: xsmsubadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353
+#34: xsmsubadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
+#35: xsmsubadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000
+#36: xsmsubadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000
+#37: xsmsubadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000
+#38: xsmsubadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
+#39: xsmsubadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
+#40: xsmsubadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
+#41: xsmsubadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#42: xsmsubadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#43: xsmsubadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#44: xsmsubadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#45: xsmsubadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
+#46: xsmsubadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#47: xsmsubadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
+#48: xsmsubadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#49: xsmsubadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#50: xsmsubadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#51: xsmsubadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#52: xsmsubadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#53: xsmsubadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#54: xsmsubadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#55: xsmsubadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#56: xsmsubadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#57: xsmsubadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#58: xsmsubadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#59: xsmsubadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#60: xsmsubadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#61: xsmsubadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#62: xsmsubadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#63: xsmsubadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+
+#0: xsmsubmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff0000000000000
+#1: xsmsubmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#2: xsmsubmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000
+#3: xsmsubmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000
+#4: xsmsubmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
+#5: xsmsubmdp 0123214569900000 fff0000000000000 7ff0000000000000 = fff0000000000000
+#6: xsmsubmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsmsubmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
+#9: xsmsubmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353
+#10: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7
+#11: xsmsubmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f
+#12: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7
+#13: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
+#14: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsmsubmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000
+#17: xsmsubmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#18: xsmsubmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000
+#19: xsmsubmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000
+#20: xsmsubmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000
+#21: xsmsubmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000
+#22: xsmsubmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsmsubmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsmsubmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000
+#25: xsmsubmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#26: xsmsubmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000
+#27: xsmsubmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000
+#28: xsmsubmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000
+#29: xsmsubmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000
+#30: xsmsubmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsmsubmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsmsubmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000
+#33: xsmsubmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
+#34: xsmsubmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f
+#35: xsmsubmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000
+#36: xsmsubmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000
+#37: xsmsubmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000
+#38: xsmsubmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsmsubmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff8000000000000
+#41: xsmsubmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#42: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000
+#43: xsmsubmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
+#45: xsmsubmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
+#46: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsmsubmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsmsubmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsmsubmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsmsubmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsmsubmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsmsubmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsmsubmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsmsubmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsmsubmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsmsubmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsmsubmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsnmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
+#1: xsnmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
+#2: xsnmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#3: xsnmaddadp 0000000000000000 fff0000000000000 0123214569900000 = 7ff0000000000000
+#4: xsnmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#5: xsnmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#6: xsnmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#7: xsnmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
+#8: xsnmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000
+#9: xsnmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353
+#10: xsnmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7
+#11: xsnmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 02039a19ca8fcb5f
+#12: xsnmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7
+#13: xsnmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000
+#14: xsnmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
+#15: xsnmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
+#16: xsnmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#17: xsnmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353
+#18: xsnmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 8000000000000000
+#19: xsnmaddadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000
+#20: xsnmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000
+#21: xsnmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000
+#22: xsnmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#23: xsnmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
+#24: xsnmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#25: xsnmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353
+#26: xsnmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000
+#27: xsnmaddadp 0000000000000000 0000000000000000 0123214569900000 = 8000000000000000
+#28: xsnmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000
+#29: xsnmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000
+#30: xsnmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#31: xsnmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
+#32: xsnmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000
+#33: xsnmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353
+#34: xsnmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 02039a19ca8fcb5f
+#35: xsnmaddadp 0000000000000000 0123214569900000 0123214569900000 = 8000000000000000
+#36: xsnmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000
+#37: xsnmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000
+#38: xsnmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
+#39: xsnmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
+#40: xsnmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#41: xsnmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
+#42: xsnmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#43: xsnmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = fff0000000000000
+#44: xsnmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#45: xsnmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = fff0000000000000
+#46: xsnmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
+#47: xsnmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
+#48: xsnmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#49: xsnmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#50: xsnmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#51: xsnmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#52: xsnmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#53: xsnmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#54: xsnmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#55: xsnmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#56: xsnmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#57: xsnmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#58: xsnmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#59: xsnmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#60: xsnmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#61: xsnmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+#62: xsnmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#63: xsnmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
+
+#0: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000
+#1: xsnmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#2: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = fff0000000000000
+#3: xsnmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = 7ff0000000000000
+#4: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
+#5: xsnmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000
+#6: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsnmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
+#9: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353
+#10: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = c1b0cc9d05eec2a7
+#11: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 02039a19ca8fcb5f
+#12: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c1b0cc9d05eec2a7
+#13: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
+#14: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsnmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000
+#17: xsnmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#18: xsnmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 8000000000000000
+#19: xsnmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000
+#20: xsnmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000
+#21: xsnmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000
+#22: xsnmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsnmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsnmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000
+#25: xsnmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#26: xsnmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000
+#27: xsnmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 8000000000000000
+#28: xsnmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000
+#29: xsnmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000
+#30: xsnmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsnmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsnmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000
+#33: xsnmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
+#34: xsnmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 02039a19ca8fcb5f
+#35: xsnmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 8000000000000000
+#36: xsnmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000
+#37: xsnmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000
+#38: xsnmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsnmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff0000000000000
+#41: xsnmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#42: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = 7ff0000000000000
+#43: xsnmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = fff0000000000000
+#44: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = fff0000000000000
+#46: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsnmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsnmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsnmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsnmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsnmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsnmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xsmuldp fff0000000000000 fff0000000000000 = 7ff0000000000000
+#1: xsmuldp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#2: xsmuldp fff0000000000000 8000000000000000 = 7ff8000000000000
+#3: xsmuldp fff0000000000000 0000000000000000 = 7ff8000000000000
+#4: xsmuldp fff0000000000000 0123214569900000 = fff0000000000000
+#5: xsmuldp fff0000000000000 7ff0000000000000 = fff0000000000000
+#6: xsmuldp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xsmuldp fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xsmuldp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
+#9: xsmuldp c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
+#10: xsmuldp c0d0650f5a07b353 8000000000000000 = 0000000000000000
+#11: xsmuldp c0d0650f5a07b353 0000000000000000 = 8000000000000000
+#12: xsmuldp c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
+#13: xsmuldp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
+#14: xsmuldp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xsmuldp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xsmuldp 8000000000000000 fff0000000000000 = 7ff8000000000000
+#17: xsmuldp 8000000000000000 c0d0650f5a07b353 = 0000000000000000
+#18: xsmuldp 8000000000000000 8000000000000000 = 0000000000000000
+#19: xsmuldp 8000000000000000 0000000000000000 = 8000000000000000
+#20: xsmuldp 8000000000000000 0123214569900000 = 8000000000000000
+#21: xsmuldp 8000000000000000 7ff0000000000000 = 7ff8000000000000
+#22: xsmuldp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xsmuldp 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xsmuldp 0000000000000000 fff0000000000000 = 7ff8000000000000
+#25: xsmuldp 0000000000000000 c0d0650f5a07b353 = 8000000000000000
+#26: xsmuldp 0000000000000000 8000000000000000 = 8000000000000000
+#27: xsmuldp 0000000000000000 0000000000000000 = 0000000000000000
+#28: xsmuldp 0000000000000000 0123214569900000 = 0000000000000000
+#29: xsmuldp 0000000000000000 7ff0000000000000 = 7ff8000000000000
+#30: xsmuldp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xsmuldp 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xsmuldp 0123214569900000 fff0000000000000 = fff0000000000000
+#33: xsmuldp 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
+#34: xsmuldp 0123214569900000 8000000000000000 = 8000000000000000
+#35: xsmuldp 0123214569900000 0000000000000000 = 0000000000000000
+#36: xsmuldp 0123214569900000 404f000000000000 = 0182883b3e438000
+#37: xsmuldp 0123214569900000 7ff0000000000000 = 7ff0000000000000
+#38: xsmuldp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xsmuldp 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xsmuldp 7ff0000000000000 fff0000000000000 = fff0000000000000
+#41: xsmuldp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#42: xsmuldp 7ff0000000000000 8000000000000000 = 7ff8000000000000
+#43: xsmuldp 7ff0000000000000 0000000000000000 = 7ff8000000000000
+#44: xsmuldp 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xsmuldp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
+#46: xsmuldp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xsmuldp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xsmuldp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xsmuldp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xsmuldp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xsmuldp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xsmuldp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xsmuldp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xsmuldp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xsmuldp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xsmuldp fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xsmuldp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xsmuldp fff8000000000000 8000000000000000 = fff8000000000000
+#59: xsmuldp fff8000000000000 0000000000000000 = fff8000000000000
+#60: xsmuldp fff8000000000000 0123214569900000 = fff8000000000000
+#61: xsmuldp fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xsmuldp fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xsmuldp fff8000000000000 7ff8000000000000 = fff8000000000000
+
+#0: xssubdp fff0000000000000 fff0000000000000 = 7ff8000000000000
+#1: xssubdp fff0000000000000 c0d0650f5a07b353 = fff0000000000000
+#2: xssubdp fff0000000000000 8000000000000000 = fff0000000000000
+#3: xssubdp fff0000000000000 0000000000000000 = fff0000000000000
+#4: xssubdp fff0000000000000 0123214569900000 = fff0000000000000
+#5: xssubdp fff0000000000000 7ff0000000000000 = fff0000000000000
+#6: xssubdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#7: xssubdp fff0000000000000 7ff8000000000000 = 7ff8000000000000
+#8: xssubdp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
+#9: xssubdp c0d0650f5a07b353 c0d0650f5a07b353 = 0000000000000000
+#10: xssubdp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353
+#11: xssubdp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353
+#12: xssubdp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
+#13: xssubdp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
+#14: xssubdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
+#15: xssubdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
+#16: xssubdp 8000000000000000 fff0000000000000 = 7ff0000000000000
+#17: xssubdp 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#18: xssubdp 8000000000000000 8000000000000000 = 0000000000000000
+#19: xssubdp 8000000000000000 0000000000000000 = 8000000000000000
+#20: xssubdp 8000000000000000 0123214569900000 = 8123214569900000
+#21: xssubdp 8000000000000000 7ff0000000000000 = fff0000000000000
+#22: xssubdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#23: xssubdp 8000000000000000 7ff8000000000000 = 7ff8000000000000
+#24: xssubdp 0000000000000000 fff0000000000000 = 7ff0000000000000
+#25: xssubdp 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
+#26: xssubdp 0000000000000000 8000000000000000 = 0000000000000000
+#27: xssubdp 0000000000000000 0000000000000000 = 0000000000000000
+#28: xssubdp 0000000000000000 0123214569900000 = 8123214569900000
+#29: xssubdp 0000000000000000 7ff0000000000000 = fff0000000000000
+#30: xssubdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#31: xssubdp 0000000000000000 7ff8000000000000 = 7ff8000000000000
+#32: xssubdp 0123214569900000 fff0000000000000 = 7ff0000000000000
+#33: xssubdp 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
+#34: xssubdp 0123214569900000 8000000000000000 = 0123214569900000
+#35: xssubdp 0123214569900000 0000000000000000 = 0123214569900000
+#36: xssubdp 0123214569900000 404f000000000000 = c04f000000000000
+#37: xssubdp 0123214569900000 7ff0000000000000 = fff0000000000000
+#38: xssubdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
+#39: xssubdp 0123214569900000 7ff8000000000000 = 7ff8000000000000
+#40: xssubdp 7ff0000000000000 fff0000000000000 = 7ff0000000000000
+#41: xssubdp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
+#42: xssubdp 7ff0000000000000 8000000000000000 = 7ff0000000000000
+#43: xssubdp 7ff0000000000000 0000000000000000 = 7ff0000000000000
+#44: xssubdp 7ff0000000000000 0123214569900000 = 7ff0000000000000
+#45: xssubdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
+#46: xssubdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
+#47: xssubdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
+#48: xssubdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
+#49: xssubdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
+#50: xssubdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
+#51: xssubdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
+#52: xssubdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
+#53: xssubdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
+#54: xssubdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
+#55: xssubdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
+#56: xssubdp fff8000000000000 fff0000000000000 = fff8000000000000
+#57: xssubdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
+#58: xssubdp fff8000000000000 8000000000000000 = fff8000000000000
+#59: xssubdp fff8000000000000 0000000000000000 = fff8000000000000
+#60: xssubdp fff8000000000000 0123214569900000 = fff8000000000000
+#61: xssubdp fff8000000000000 7ff0000000000000 = fff8000000000000
+#62: xssubdp fff8000000000000 7ff7ffffffffffff = fff8000000000000
+#63: xssubdp fff8000000000000 7ff8000000000000 = fff8000000000000
+
+
+Test VSX scalar integer conversion instructions
+#0: xscvdpsxds 3fd8000000000000 => 0000000000000000
+#1: xscvdpsxds 404f000000000000 => 000000000000003e
+#2: xscvdpsxds 0018000000b77501 => 0000000000000000
+#3: xscvdpsxds 7fe800000000051b => 7fffffffffffffff
+#4: xscvdpsxds 0123214569900000 => 0000000000000000
+#5: xscvdpsxds 0000000000000000 => 0000000000000000
+#6: xscvdpsxds 8000000000000000 => 0000000000000000
+#7: xscvdpsxds 7ff0000000000000 => 7fffffffffffffff
+#8: xscvdpsxds fff0000000000000 => 8000000000000000
+#9: xscvdpsxds 7ff7ffffffffffff => 8000000000000000
+#10: xscvdpsxds fff7ffffffffffff => 8000000000000000
+#11: xscvdpsxds 7ff8000000000000 => 8000000000000000
+#12: xscvdpsxds fff8000000000000 => 8000000000000000
+#13: xscvdpsxds 8008340000078000 => 0000000000000000
+#14: xscvdpsxds c0d0650f5a07b353 => ffffffffffffbe6c
+
+#0: xscvsxddp 3fd8000000000000 => 43cfec0000000000
+#1: xscvsxddp 404f000000000000 => 43d013c000000000
+#2: xscvsxddp 0018000000b77501 => 4338000000b77501
+#3: xscvsxddp 7fe800000000051b => 43dffa0000000001
+#4: xscvsxddp 0123214569900000 => 4372321456990000
+#5: xscvsxddp 0000000000000000 => 0000000000000000
+#6: xscvsxddp 8000000000000000 => c3e0000000000000
+#7: xscvsxddp 7ff0000000000000 => 43dffc0000000000
+#8: xscvsxddp fff0000000000000 => c330000000000000
+#9: xscvsxddp 7ff7ffffffffffff => 43dffe0000000000
+#10: xscvsxddp fff7ffffffffffff => c320000000000002
+#11: xscvsxddp 7ff8000000000000 => 43dffe0000000000
+#12: xscvsxddp fff8000000000000 => c320000000000000
+#13: xscvsxddp 8008340000078000 => c3dffdf2fffffe20
+#14: xscvsxddp c0d0650f5a07b353 => c3cf97cd7852fc26
+
+#0: xscvuxddp 3fd8000000000000 => 43cfec0000000000
+#1: xscvuxddp 404f000000000000 => 43d013c000000000
+#2: xscvuxddp 0018000000b77501 => 4338000000b77501
+#3: xscvuxddp 7fe800000000051b => 43dffa0000000001
+#4: xscvuxddp 0123214569900000 => 4372321456990000
+#5: xscvuxddp 0000000000000000 => 0000000000000000
+#6: xscvuxddp 8000000000000000 => 43e0000000000000
+#7: xscvuxddp 7ff0000000000000 => 43dffc0000000000
+#8: xscvuxddp fff0000000000000 => 43effe0000000000
+#9: xscvuxddp 7ff7ffffffffffff => 43dffe0000000000
+#10: xscvuxddp fff7ffffffffffff => 43efff0000000000
+#11: xscvuxddp 7ff8000000000000 => 43dffe0000000000
+#12: xscvuxddp fff8000000000000 => 43efff0000000000
+#13: xscvuxddp 8008340000078000 => 43e00106800000f0
+#14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
+
+
+Testcase PASSED
diff --git a/main/none/tests/ppc64/test_isa_2_06_part1.vgtest b/main/none/tests/ppc64/test_isa_2_06_part1.vgtest
new file mode 100644
index 0000000..512a218
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part1.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_06_cap
+prog: test_isa_2_06_part1
diff --git a/main/none/tests/ppc64/test_isa_2_06_part2.c b/main/none/tests/ppc64/test_isa_2_06_part2.c
new file mode 100644
index 0000000..d9f2453
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part2.c
@@ -0,0 +1,1730 @@
+/* Copyright (C) 2011 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#ifdef HAS_VSX
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+#include <math.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int div_flags, div_xer;
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+typedef void (*test_func_t)(void);
+typedef struct test_table test_table_t;
+
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+} fp_test_args_t;
+
+
+fp_test_args_t fp_cmp_tests[] = {
+ {8, 8},
+ {8, 14},
+ {8, 6},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {10, 6},
+ {10, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 10},
+ {12, 8},
+ {12, 14},
+ {12, 6},
+ {12, 5},
+ {1, 1},
+ {2, 2},
+ {3, 3},
+ {4, 4},
+};
+
+
+fp_test_args_t two_arg_fp_tests[] = {
+ {8, 8},
+ {8, 14},
+ {15, 16},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {12, 6},
+ {12, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 11},
+ {12, 8 },
+ {12, 14},
+ {12, 6},
+ {15, 16},
+ {15, 16},
+ {9, 11},
+ {11, 11},
+ {11, 12}
+};
+
+
+static int nb_special_fargs;
+static double * spec_fargs;
+static float * spec_sp_fargs;
+
+static void build_special_fargs_table(void)
+{
+/*
+ Entry Sign Exp fraction Special value
+ 0 0 3fd 0x8000000000000ULL Positive finite number
+ 1 0 404 0xf000000000000ULL ...
+ 2 0 001 0x8000000b77501ULL ...
+ 3 0 7fe 0x800000000051bULL ...
+ 4 0 012 0x3214569900000ULL ...
+ 5 0 000 0x0000000000000ULL +0.0 (+zero)
+ 6 1 000 0x0000000000000ULL -0.0 (-zero)
+ 7 0 7ff 0x0000000000000ULL +infinity
+ 8 1 7ff 0x0000000000000ULL -infinity
+ 9 0 7ff 0x7FFFFFFFFFFFFULL +SNaN
+ 10 1 7ff 0x7FFFFFFFFFFFFULL -SNaN
+ 11 0 7ff 0x8000000000000ULL +QNaN
+ 12 1 7ff 0x8000000000000ULL -QNaN
+ 13 1 000 0x8340000078000ULL Denormalized val (zero exp and non-zero fraction)
+ 14 1 40d 0x0650f5a07b353ULL Negative finite number
+ 15 0 412 0x32585a9900000ULL A couple more positive finite numbers
+ 16 0 413 0x82511a2000000ULL ...
+*/
+
+ uint64_t mant;
+ uint16_t _exp;
+ int s;
+ int j, i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 17 * sizeof(double) );
+ spec_sp_fargs = malloc( 17 * sizeof(float) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* None of the ftdiv tests succeed.
+ * FRA = value #0; FRB = value #1
+ * ea_ = -2; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 100
+ */
+
+ /*************************************************
+ * fe_flag tests
+ *
+ *************************************************/
+
+ /* fe_flag <- 1 if FRA is a NaN
+ * FRA = value #9; FRB = value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRB is a NaN
+ * FRA = value #1; FRB = value #12
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if e_b <= -1022
+ * FRA = value #0; FRB = value #2
+ * e_a = -2; e_b = -1022
+ * fl_flag || fg_flag || fe_flag = 101
+ *
+ */
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if e_b >= 1021
+ * FRA = value #1; FRB = value #3
+ * e_a = 5; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b >= 1023
+ * Let FRA = value #3 and FRB be value #0.
+ * e_a = 1023; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b <= -1023
+ * Let FRA = value #0 above and FRB be value #3 above
+ * e_a = -2; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a <= -970
+ * Let FRA = value #4 and FRB be value #0
+ * e_a = -1005; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /*************************************************
+ * fg_flag tests
+ *
+ *************************************************/
+ /* fg_flag <- 1 if FRA is an Infinity
+ * NOTE: FRA = Inf also sets fe_flag
+ * Do two tests, using values #7 and #8 (+/- Inf) for FRA.
+ * Test 1:
+ * Let FRA be value #7 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ * Test 2:
+ * Let FRA be value #8 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ */
+
+ /* fg_flag <- 1 if FRB is an Infinity
+ * NOTE: FRB = Inf also sets fe_flag
+ * Let FRA be value #1 and FRB be value #7
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is denormalized
+ * NOTE: e_b < -1022 ==> fe_flag <- 1
+ * Let FRA be value #0 and FRB be value #13
+ * e_a = -2; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is +zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #5
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is -zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #6
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +SNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -SNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* A couple positive finite numbers ... */
+ // #15
+ s = 0;
+ _exp = 0x412;
+ mant = 0x32585a9900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #16
+ s = 0;
+ _exp = 0x413;
+ mant = 0x82511a2000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ nb_special_fargs = i;
+ for (j = 0; j < i; j++) {
+ spec_sp_fargs[j] = spec_fargs[j];
+ }
+}
+
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+typedef enum {
+ SINGLE_TEST,
+ DOUBLE_TEST
+} precision_type_t;
+
+typedef enum {
+ VX_SCALAR_FP_NMSUB = 0,
+ // ALL VECTOR-TYPE OPS SHOULD BE ADDED AFTER THIS LINE
+ VX_VECTOR_FP_MULT_AND_OP2 = 10,
+ // and before this line
+ VX_BASIC_CMP = 30,
+ VX_CONV_WORD,
+ VX_DEFAULT
+} vx_fp_test_type;
+
+typedef struct vx_fp_test
+{
+ test_func_t test_func;
+ const char * name;
+ fp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type type;
+ const char * op;
+} vx_fp_test_t;
+
+static vector unsigned int vec_out, vec_inA, vec_inB, vec_inC;
+
+static Bool do_dot;
+static void test_xvcmpeqdp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpeqdp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpeqdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgedp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgedp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgedp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgtdp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgtdp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgtdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpeqsp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpeqsp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpeqsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgesp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgesp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgesp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgtsp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgtsp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgtsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static Bool do_aXp;
+static Bool do_dp;
+static void test_xsnmsub(void)
+{
+ if (do_aXp)
+ __asm__ __volatile__ ("xsnmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsnmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmadd(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmaddasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmaddmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvnmadd(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmaddasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmaddmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvnmsub(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmsubasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmsubmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmsub(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmsubasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmsubmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xssqrtdp(void)
+{
+ __asm__ __volatile__ ("xssqrtdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpim(void)
+{
+ __asm__ __volatile__ ("xsrdpim %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpip(void)
+{
+ __asm__ __volatile__ ("xsrdpip %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xstdivdp(void)
+{
+ __asm__ __volatile__ ("xstdivdp 6, %x0, %x1" : : "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xsmaxdp(void)
+{
+ __asm__ __volatile__ ("xsmaxdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmindp(void)
+{
+ __asm__ __volatile__ ("xsmindp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvadddp(void)
+{
+ __asm__ __volatile__ ("xvadddp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvaddsp(void)
+{
+ __asm__ __volatile__ ("xvaddsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvdivdp(void)
+{
+ __asm__ __volatile__ ("xvdivdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvdivsp(void)
+{
+ __asm__ __volatile__ ("xvdivsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmuldp(void)
+{
+ __asm__ __volatile__ ("xvmuldp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmulsp(void)
+{
+ __asm__ __volatile__ ("xvmulsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvsubdp(void)
+{
+ __asm__ __volatile__ ("xvsubdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmaxdp(void)
+{
+ __asm__ __volatile__ ("xvmaxdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmindp(void)
+{
+ __asm__ __volatile__ ("xvmindp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmaxsp(void)
+{
+ __asm__ __volatile__ ("xvmaxsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvminsp(void)
+{
+ __asm__ __volatile__ ("xvminsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvsubsp(void)
+{
+ __asm__ __volatile__ ("xvsubsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvresp(void)
+{
+ __asm__ __volatile__ ("xvresp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xxsel(void)
+{
+ unsigned long long * dst;
+ unsigned long long xa[] = { 0xa12bc37de56f9708ULL, 0x3894c1fddeadbeefULL};
+ unsigned long long xb[] = { 0xfedc432124681235ULL, 0xf1e2d3c4e0057708ULL};
+ unsigned long long xc[] = { 0xffffffff01020304ULL, 0x128934bd00000000ULL};
+
+ memcpy(&vec_inA, xa, 16);
+ memcpy(&vec_inB, xb, 16);
+ memcpy(&vec_inC, xc, 16);
+
+
+ __asm__ __volatile__ ("xxsel %x0, %x1, %x2, %x3" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB),"wa" (vec_inC));
+ dst = (unsigned long long *) &vec_out;
+ printf("xxsel %016llx,%016llx,%016llx => %016llx\n", xa[0], xb[0], xc[0], *dst);
+ dst++;
+ printf("xxsel %016llx,%016llx,%016llx => %016llx\n", xa[1], xb[1], xc[1], *dst);
+ printf("\n");
+}
+
+static void test_xxspltw(void)
+{
+ int uim;
+ unsigned long long * dst = NULL;
+ unsigned long long xb[] = { 0xfedc432124681235ULL, 0xf1e2d3c4e0057708ULL};
+ memcpy(&vec_inB, xb, 16);
+
+ for (uim = 0; uim < 4; uim++) {
+ switch (uim) {
+ case 0:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 0" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ case 1:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 1" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ case 2:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 2" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ case 3:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 3" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ }
+ dst = (unsigned long long *) &vec_out;
+ printf("xxspltw 0x%016llx%016llx %d=> 0x%016llx", xb[0], xb[1], uim, *dst);
+ dst++;
+ printf("%016llx\n", *dst);
+ }
+ printf("\n");
+}
+
+static void test_xscvdpsxws(void)
+{
+ __asm__ __volatile__ ("xscvdpsxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvdpuxds(void)
+{
+ __asm__ __volatile__ ("xscvdpuxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcpsgndp(void)
+{
+ __asm__ __volatile__ ("xvcpsgndp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcpsgnsp(void)
+{
+ __asm__ __volatile__ ("xvcpsgnsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcvdpsxws(void)
+{
+ __asm__ __volatile__ ("xvcvdpsxws %x0, %x1 " : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspsxws(void)
+{
+ __asm__ __volatile__ ("xvcvspsxws %x0, %x1 " : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static vx_fp_test_t
+vx_vector_one_fp_arg_tests[] = {
+ { &test_xvresp, "xvresp", NULL, 16, SINGLE_TEST, VX_BASIC_CMP, "1/x"},
+ { &test_xvcvdpsxws, "xvcvdpsxws", NULL, 16, DOUBLE_TEST, VX_CONV_WORD, "conv"},
+ { &test_xvcvspsxws, "xvcvspsxws", NULL, 16, SINGLE_TEST, VX_CONV_WORD, "conv"},
+ { NULL, NULL, NULL, 0 , 0, 0, NULL}
+};
+
+static vx_fp_test_t
+vx_vector_fp_tests[] = {
+ { &test_xvcmpeqdp, "xvcmpeqdp", fp_cmp_tests, 64, DOUBLE_TEST, VX_BASIC_CMP, "eq"},
+ { &test_xvcmpgedp, "xvcmpgedp", fp_cmp_tests, 64, DOUBLE_TEST, VX_BASIC_CMP, "ge"},
+ { &test_xvcmpgtdp, "xvcmpgtdp", fp_cmp_tests, 64, DOUBLE_TEST, VX_BASIC_CMP, "gt"},
+ { &test_xvcmpeqsp, "xvcmpeqsp", fp_cmp_tests, 64, SINGLE_TEST, VX_BASIC_CMP, "eq"},
+ { &test_xvcmpgesp, "xvcmpgesp", fp_cmp_tests, 64, SINGLE_TEST, VX_BASIC_CMP, "ge"},
+ { &test_xvcmpgtsp, "xvcmpgtsp", fp_cmp_tests, 64, SINGLE_TEST, VX_BASIC_CMP, "gt"},
+ { &test_xvadddp, "xvadddp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "+" },
+ { &test_xvaddsp, "xvaddsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "+" },
+ { &test_xvdivdp, "xvdivdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "/" },
+ { &test_xvdivsp, "xvdivsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "/" },
+ { &test_xvmuldp, "xvmuldp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "*" },
+ { &test_xvmulsp, "xvmulsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "*" },
+ { &test_xvsubdp, "xvsubdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "-" },
+ { &test_xvsubsp, "xvsubsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "-" },
+ { &test_xvmaxdp, "xvmaxdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "@max@" },
+ { &test_xvmindp, "xvmindp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "@min@" },
+ { &test_xvmaxsp, "xvmaxsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "@max@" },
+ { &test_xvminsp, "xvminsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "@min@" },
+ { &test_xvcpsgndp, "xvcpsgndp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "+-cp"},
+ { &test_xvcpsgnsp, "xvcpsgnsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "+-cp"},
+ { NULL, NULL, NULL, 0 , 0, 0, NULL}
+};
+
+
+static vx_fp_test_t
+vx_aORm_fp_tests[] = {
+ { &test_xsnmsub, "xsnmsub", two_arg_fp_tests, 64, DOUBLE_TEST, VX_SCALAR_FP_NMSUB, "!*-"},
+ { &test_xvmadd, "xvmadd", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*+"},
+ { &test_xvmadd, "xvmadd", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*+"},
+ { &test_xvnmadd, "xvnmadd", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*+"},
+ { &test_xvnmadd, "xvnmadd", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*+"},
+ { &test_xvmsub, "xvmsub", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*-"},
+ { &test_xvmsub, "xvmsub", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*-"},
+ { &test_xvnmsub, "xvnmsub", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*-"},
+ { &test_xvnmsub, "xvnmsub", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*-"},
+ { NULL, NULL, NULL, 0, 0, 0, NULL }
+};
+
+static vx_fp_test_t
+vx_simple_scalar_fp_tests[] = {
+ { &test_xssqrtdp, "xssqrtdp", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsrdpim, "xsrdpim", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsrdpip, "xsrdpip", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xstdivdp, "xstdivdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsmaxdp, "xsmaxdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsmindp, "xsmindp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xscvdpsxws, "xscvdpsxws", NULL, 17, DOUBLE_TEST, VX_CONV_WORD, NULL},
+ { &test_xscvdpuxds, "xscvdpuxds", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { NULL, NULL, NULL, 0, 0, 0, NULL }
+};
+
+
+#ifdef __powerpc64__
+static void test_bpermd(void)
+{
+ /* NOTE: Bit number is '0 . . . 63'
+ *
+ * Permuted bits are generated bit 0 -7 as follows:
+ * index = (r14)8*i:8*i+7
+ * perm[i] = (r15)index
+ *
+ * So, for i = 0, index is (r14)8*0:8*0+7, or (r14)0:7, which is the MSB
+ * byte of r14, 0x1b(27/base 10). This identifies bit 27 of r15, which is '1'.
+ * For i = 1, index is 0x2c, identifying bit 44 of r15, which is '1'.
+ * So the result of the first two iterations of i are:
+ * perm = 0b01xxxxxx
+ *
+ */
+ r15 = 0xa12bc37de56f9708ULL;
+ r14 = 0x1b2c31f030000001ULL;
+ __asm__ __volatile__ ("bpermd %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ printf("bpermd: 0x%016llx : 0x%016llx => 0x%llx\n", (unsigned long long)r14,
+ (unsigned long long)r15, (unsigned long long)r17);
+ printf("\n");
+}
+#endif
+
+static Bool do_OE;
+typedef enum {
+ DIV_BASE = 1,
+ DIV_OE = 2,
+ DIV_DOT = 4,
+} div_type_t;
+/* Possible divde type combinations are:
+ * - base
+ * - base+dot
+ * - base+OE
+ * - base+OE+dot
+ */
+#ifdef __powerpc64__
+static void test_divde(void)
+{
+ int divde_type = DIV_BASE;
+ if (do_OE)
+ divde_type |= DIV_OE;
+ if (do_dot)
+ divde_type |= DIV_DOT;
+
+ switch (divde_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divde %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divde. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divde type. Exiting\n");
+ exit(1);
+ }
+}
+#endif
+
+static void test_divweu(void)
+{
+ int divweu_type = DIV_BASE;
+ if (do_OE)
+ divweu_type |= DIV_OE;
+ if (do_dot)
+ divweu_type |= DIV_DOT;
+
+ switch (divweu_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweu %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweuo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweu. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweuo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divweu type. Exiting\n");
+ exit(1);
+ }
+}
+
+static void test_fctiduz(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctiduz. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctiduz %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+static void test_fctidu(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctidu. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctidu %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+static void test_fctiwuz(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctiwuz. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctiwuz %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+static void test_fctiwu(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctiwu. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctiwu %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+typedef struct simple_test {
+ test_func_t test_func;
+ char * name;
+ precision_type_t precision;
+} simple_test_t;
+
+static simple_test_t fct_tests[] = {
+ { &test_fctiduz, "fctiduz", DOUBLE_TEST },
+ { &test_fctidu, "fctidu", DOUBLE_TEST },
+ { &test_fctiwuz, "fctiwuz", SINGLE_TEST },
+ { &test_fctiwu, "fctiwu", SINGLE_TEST },
+ { NULL, NULL }
+};
+
+static void setup_sp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? &vec_out : &vec_inB;
+
+ for (i = 0; i < 4; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_sp_fargs[a_idx];
+ inB = (void *)&spec_sp_fargs[b_idx];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 4), inA, 4);
+ memcpy(vec_src + (i * 4), inB, 4);
+ targs++;
+ }
+}
+
+static void setup_dp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? (void *)&vec_out : (void *)&vec_inB;
+
+ for (i = 0; i < 2; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_fargs[a_idx];
+ inB = (void *)&spec_fargs[b_idx];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 8), inA, 8);
+ memcpy(vec_src + (i * 8), inB, 8);
+ targs++;
+ }
+}
+
+#define VX_NOT_CMP_OP 0xffffffff
+static void print_vector_fp_result(unsigned int cc, vx_fp_test_t * test_group, int i)
+{
+ int a_idx, b_idx, k;
+ char * name = malloc(20);
+ int dp = test_group->precision == DOUBLE_TEST ? 1 : 0;
+ int loops = dp ? 2 : 4;
+ fp_test_args_t * targs = &test_group->targs[i];
+ unsigned long long * frA_dp, * frB_dp, * dst_dp;
+ unsigned int * frA_sp, *frB_sp, * dst_sp;
+ strcpy(name, test_group->name);
+ printf("#%d: %s%s ", dp? i/2 : i/4, name, (do_dot ? "." : ""));
+ for (k = 0; k < loops; k++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ if (k)
+ printf(" AND ");
+ if (dp) {
+ frA_dp = (unsigned long long *)&spec_fargs[a_idx];
+ frB_dp = (unsigned long long *)&spec_fargs[b_idx];
+ printf("%016llx %s %016llx", *frA_dp, test_group->op, *frB_dp);
+ } else {
+ frA_sp = (unsigned int *)&spec_sp_fargs[a_idx];
+ frB_sp = (unsigned int *)&spec_sp_fargs[b_idx];
+ printf("%08x %s %08x", *frA_sp, test_group->op, *frB_sp);
+ }
+ targs++;
+ }
+ if (cc != VX_NOT_CMP_OP)
+ printf(" ? cc=%x", cc);
+
+ if (dp) {
+ dst_dp = (unsigned long long *) &vec_out;
+ printf(" => %016llx %016llx\n", dst_dp[0], dst_dp[1]);
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ printf(" => %08x %08x %08x %08x\n", dst_sp[0], dst_sp[1], dst_sp[2], dst_sp[3]);
+ }
+ free(name);
+}
+
+
+static void print_vx_aORm_fp_result(unsigned long long * XT_arg, unsigned long long * XB_arg,
+ vx_fp_test_t * test_group, int i)
+{
+ int a_idx, k;
+ char * name = malloc(20);
+ int dp = test_group->precision == DOUBLE_TEST ? 1 : 0;
+ int loops = dp ? 2 : 4;
+ fp_test_args_t * targs = &test_group->targs[i];
+ unsigned long long frA_dp, * dst_dp;
+ unsigned int frA_sp, * dst_sp;
+
+ strcpy(name, test_group->name);
+ if (do_aXp)
+ if (dp)
+ strcat(name, "adp");
+ else
+ strcat(name, "asp");
+ else
+ if (dp)
+ strcat(name, "mdp");
+ else
+ strcat(name, "msp");
+
+ printf("#%d: %s ", dp? i/2 : i/4, name);
+ for (k = 0; k < loops; k++) {
+ a_idx = targs->fra_idx;
+ if (k)
+ printf(" AND ");
+ if (dp) {
+ frA_dp = *((unsigned long long *)&spec_fargs[a_idx]);
+ printf("%s(%016llx,%016llx,%016llx)", test_group->op, XT_arg[k], frA_dp, XB_arg[k]);
+ } else {
+ unsigned int * xt_sp = (unsigned int *)XT_arg;
+ unsigned int * xb_sp = (unsigned int *)XB_arg;
+ frA_sp = *((unsigned int *)&spec_sp_fargs[a_idx]);
+ printf("%s(%08x,%08x,%08x)", test_group->op, xt_sp[k], frA_sp, xb_sp[k]);
+ }
+ targs++;
+ }
+
+ if (dp) {
+ dst_dp = (unsigned long long *) &vec_out;
+ printf(" => %016llx %016llx\n", dst_dp[0], dst_dp[1]);
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ printf(" => %08x %08x %08x %08x\n", dst_sp[0], dst_sp[1], dst_sp[2], dst_sp[3]);
+ }
+ free(name);
+}
+
+/* This function currently only supports double precision input arguments. */
+static void test_vx_simple_scalar_fp_ops(void)
+{
+ test_func_t func;
+ int k = 0;
+
+ build_special_fargs_table();
+ while ((func = vx_simple_scalar_fp_tests[k].test_func)) {
+ unsigned long long * frap, * frbp, * dst;
+ unsigned int * pv;
+ int idx;
+ vx_fp_test_t test_group = vx_simple_scalar_fp_tests[k];
+ Bool convToWord = (test_group.type == VX_CONV_WORD);
+ if (test_group.precision != DOUBLE_TEST) {
+ fprintf(stderr, "Unsupported single precision for scalar op in test_vx_aORm_fp_ops\n");
+ exit(1);
+ }
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ /* If num_tests is exactly equal to nb_special_fargs, this implies the
+ * instruction being tested only requires one floating point argument
+ * (e.g. xssqrtdp).
+ */
+ if (test_group.num_tests == nb_special_fargs && !test_group.targs) {
+ void * inB;
+ int i;
+ for (i = 0; i < nb_special_fargs; i++) {
+ inB = (void *)&spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+ memcpy(&vec_inB, inB, 8);
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp,
+ convToWord ? (*dst & 0x00000000ffffffffULL) : *dst);
+ }
+ } else {
+ void * inA, * inB;
+ unsigned int condreg, flags;
+ int isTdiv = (strstr(test_group.name, "xstdivdp") != NULL) ? 1 : 0;
+ int i;
+ for (i = 0; i < test_group.num_tests; i++) {
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (void *)&spec_fargs[aTest.fra_idx];
+ inB = (void *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+ memcpy(&vec_inA, inA, 8);
+ memcpy(&vec_inB, inB, 8);
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ if (isTdiv) {
+ condreg = (flags & 0x000000f0) >> 4;
+ printf("#%d: %s %016llx,%016llx => cr %x\n", i, test_group.name, *frap, *frbp, condreg);
+ } else {
+ dst = (unsigned long long *) &vec_out;
+ printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
+ *frap, *frbp, *dst);
+ }
+ }
+ }
+ printf( "\n" );
+ k++;
+ }
+}
+
+static void test_vx_aORm_fp_ops(void)
+{
+ /* These ops need a third src argument, which is stored in element 0 of
+ * VSX[XT] -- i.e., vec_out. For the xs<ZZZ>m{d|s}p cases, VSX[XT] holds
+ * src3 and VSX[XB] holds src2; for the xs<ZZZ>a{d|s}p cases, VSX[XT] holds
+ * src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test
+ * data (input args, result) contain only two inputs, so I arbitrarily
+ * choose some spec_fargs elements for the third source argument.
+ * Note that that by using the same input data for a given pair of
+ * a{d|s}p/m{d|s}p-type instructions (by swapping the src2 and src3
+ * arguments), the expected result should be the same.
+ */
+
+ test_func_t func;
+ int k;
+ char * test_name = (char *)malloc(20);
+ k = 0;
+ do_dot = False;
+
+ build_special_fargs_table();
+ while ((func = vx_aORm_fp_tests[k].test_func)) {
+ int i, stride;
+ Bool repeat = False;
+ Bool scalar = False;
+ unsigned long long * frap, * frbp, * dst;
+ vx_fp_test_t test_group = vx_aORm_fp_tests[k];
+ vx_fp_test_type test_type = test_group.type;
+ do_dp = test_group.precision == DOUBLE_TEST ? True : False;
+ frap = frbp = NULL;
+
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2) {
+ scalar = True;
+ strcpy(test_name, test_group.name);
+ if (!repeat) {
+ repeat = 1;
+ stride = 1;
+ // Only support double precision scalar ops in this function
+ if (do_dp) {
+ strcat(test_name, "adp");
+ } else {
+ fprintf(stderr, "Unsupported single precision for scalar op in test_vx_aORm_fp_ops\n");
+ exit(1);
+ }
+ do_aXp = True;
+ }
+ } else if (test_type < VX_BASIC_CMP) {
+ // Then it must be a VX_VECTOR_xxx type
+ stride = do_dp ? 2 : 4;
+ if (!repeat) {
+ // No need to work up the testcase name here, since that will be done in
+ // the print_vx_aORm_fp_result() function we'll call for vector-type ops.
+ repeat = 1;
+ do_aXp = True;
+ }
+ } else {
+ printf("ERROR: Invalid VX FP test type %d\n", test_type);
+ exit(1);
+ }
+
+again:
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ void * inA, * inB;
+ int m, fp_idx[4];
+ unsigned long long vsr_XT[2];
+ unsigned long long vsr_XB[2];
+ fp_test_args_t aTest = test_group.targs[i];
+ for (m = 0; m < stride; m++)
+ fp_idx[m] = i % (nb_special_fargs - stride) + m;
+
+ /* When repeat == True, we're on the first time through of one of the VX_FP_SMx
+ * test types, meaning we're testing a xs<ZZZ>adp case, thus we have to swap
+ * inputs as described above:
+ * src2 <= VSX[XT]
+ * src3 <= VSX[XB]
+ */
+ if (scalar) {
+ // For scalar op, only need to copy one doubleword into each vector's element 0
+ inA = (void *)&spec_fargs[aTest.fra_idx];
+ inB = (void *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ memcpy(&vec_inA, inA, 8);
+ if (repeat) {
+ memcpy(&vec_out, inB, 8); // src2
+ memcpy(&vec_inB, &spec_fargs[fp_idx[0]], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[fp_idx[0]];
+ } else {
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ memcpy(&vec_inB, inB, 8); // src2
+ memcpy(&vec_out, &spec_fargs[fp_idx[0]], 8); //src3
+ }
+ memcpy(vsr_XT, &vec_out, 8);
+ } else {
+ int j, loops = do_dp ? 2 : 4;
+ size_t len = do_dp ? 8 : 4;
+ void * vec_src = repeat ? (void *)&vec_inB : (void *)&vec_out;
+ for (j = 0; j < loops; j++) {
+ if (do_dp)
+ memcpy(vec_src + (j * len), &spec_fargs[fp_idx[j]], len);
+ else
+ memcpy(vec_src + (j * len), &spec_sp_fargs[fp_idx[j]], len);
+ }
+ if (do_dp)
+ setup_dp_fp_args(&test_group.targs[i], repeat);
+ else
+ setup_sp_fp_args(&test_group.targs[i], repeat);
+
+ memcpy(vsr_XT, &vec_out, 16);
+ memcpy(vsr_XB, &vec_inB, 16);
+ }
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2)
+ printf( "#%d: %s %s(%016llx,%016llx,%016llx) = %016llx\n", i,
+ test_name, test_group.op, vsr_XT[0], *frap, *frbp, *dst );
+ else
+ print_vx_aORm_fp_result(vsr_XT, vsr_XB, &test_group, i);
+ }
+ printf( "\n" );
+
+ if (repeat) {
+ repeat = 0;
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2) {
+ strcpy(test_name, test_group.name);
+ strcat(test_name, "mdp");
+ }
+ do_aXp = False;
+ goto again;
+ }
+ k++;
+ }
+ printf( "\n" );
+ free(test_name);
+}
+
+static void test_vx_vector_one_fp_arg(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vx_vector_one_fp_arg_tests[k].test_func)) {
+ int idx, i;
+ vx_fp_test_t test_group = vx_vector_one_fp_arg_tests[k];
+ Bool convToWord = (test_group.type == VX_CONV_WORD);
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool xvrespTest = (strstr(test_group.name , "xvresp") != NULL) ? True: False;
+ int stride = dp ? 2 : 4;
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long * frB_dp, *dst_dp;
+ for (j = 0; j < 2; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
+ printf("#%d: %s ", i/2, test_group.name);
+ for (j = 0; j < 2; j++) {
+ if (j)
+ printf("; ");
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ printf(" = %016llx", convToWord ? (dst_dp[j] & 0x00000000ffffffffULL) : dst_dp[j]);
+ }
+ printf("\n");
+ } else {
+ int j;
+ unsigned int * frB_sp, * dst_sp;
+
+ for (j = 0; j < 4; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ // execute test insn
+ (*func)();
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+ printf("#%d: %s ", i/4, test_group.name);
+ for (j = 0; j < 4; j++) {
+ if (j)
+ printf("; ");
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ if (xvrespTest) {
+ float calc_diff = fabs(spec_sp_fargs[i + j]/256);
+ float sp_res;
+ memcpy(&sp_res, &dst_sp[j], 4);
+ float div_result = 1/spec_sp_fargs[i + j];
+ float real_diff = fabs(sp_res - div_result);
+ printf( " ==> %s",
+ ( ( sp_res == div_result )
+ || ( isnan(sp_res) && isnan(div_result) )
+ || ( real_diff <= calc_diff ) ) ? "PASS"
+ : "FAIL");
+ } else {
+ printf(" = %08x", dst_sp[j]);
+ }
+ }
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+
+}
+
+/* This function assumes the instruction being tested requires two args. */
+static void test_vx_vector_fp_ops(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vx_vector_fp_tests[k].test_func)) {
+ int idx, i, repeat = 1;
+ vx_fp_test_t test_group = vx_vector_fp_tests[k];
+ int stride = test_group.precision == DOUBLE_TEST ? 2 : 4;
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv, condreg;
+ unsigned int flags;
+
+ pv = (unsigned int *)&vec_out;
+ if (test_group.precision == DOUBLE_TEST)
+ setup_dp_fp_args(&test_group.targs[i], False);
+ else
+ setup_sp_fp_args(&test_group.targs[i], False);
+
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ if (test_group.type == VX_BASIC_CMP) {
+ condreg = (flags & 0x000000f0) >> 4;
+ } else {
+ condreg = VX_NOT_CMP_OP;
+ }
+ print_vector_fp_result(condreg, &test_group, i);
+ }
+ printf("\n");
+ if (repeat && test_group.type == VX_BASIC_CMP) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+// The div doubleword test data
+signed long long div_dw_tdata[13][2] = {
+ { 4, -4 },
+ { 4, -3 },
+ { 4, 4 },
+ { 4, -5 },
+ { 3, 8 },
+ { 0x8000000000000000ULL, 0xa },
+ { 0x50c, -1 },
+ { 0x50c, -4096 },
+ { 0x1234fedc, 0x8000a873 },
+ { 0xabcd87651234fedcULL, 0xa123b893 },
+ { 0x123456789abdcULL, 0 },
+ { 0, 2 },
+ { 0x77, 0xa3499 }
+};
+#define dw_tdata_len (sizeof(div_dw_tdata)/sizeof(signed long long)/2)
+
+// The div word test data
+unsigned int div_w_tdata[6][2] = {
+ { 0, 2 },
+ { 2, 0 },
+ { 0x7abc1234, 0xf0000000 },
+ { 0xfabc1234, 5 },
+ { 77, 66 },
+ { 5, 0xfabc1234 },
+};
+#define w_tdata_len (sizeof(div_w_tdata)/sizeof(unsigned int)/2)
+
+typedef struct div_ext_test
+{
+ test_func_t test_func;
+ const char *name;
+ int num_tests;
+ div_type_t div_type;
+ precision_type_t precision;
+} div_ext_test_t;
+
+static div_ext_test_t div_tests[] = {
+#ifdef __powerpc64__
+ { &test_divde, "divde", dw_tdata_len, DIV_BASE, DOUBLE_TEST },
+ { &test_divde, "divdeo", dw_tdata_len, DIV_OE, DOUBLE_TEST },
+#endif
+ { &test_divweu, "divweu", w_tdata_len, DIV_BASE, SINGLE_TEST },
+ { &test_divweu, "divweuo", w_tdata_len, DIV_OE, SINGLE_TEST },
+ { NULL, NULL, 0, 0, 0 }
+};
+
+static void test_div_extensions(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = div_tests[k].test_func)) {
+ int i, repeat = 1;
+ div_ext_test_t test_group = div_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int condreg;
+
+ if (test_group.div_type == DIV_OE)
+ do_OE = True;
+ else
+ do_OE = False;
+
+ if (test_group.precision == DOUBLE_TEST) {
+ r14 = div_dw_tdata[i][0];
+ r15 = div_dw_tdata[i][1];
+ } else {
+ r14 = div_w_tdata[i][0];
+ r15 = div_w_tdata[i][1];
+ }
+ // execute test insn
+ (*func)();
+ condreg = (div_flags & 0xf0000000) >> 28;
+ printf("#%d: %s%s: ", i, test_group.name, do_dot ? "." : "");
+ if (test_group.precision == DOUBLE_TEST) {
+ printf("0x%016llx / 0x%016llx = 0x%016llx;",
+ div_dw_tdata[i][0], div_dw_tdata[i][1], (signed long long) r17);
+ } else {
+ printf("0x%08x / 0x%08x = 0x%08x;",
+ div_w_tdata[i][0], div_w_tdata[i][1], (unsigned int) r17);
+ }
+ printf(" CR=%x; XER=%x\n", condreg, div_xer);
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+
+}
+
+static void test_fct_ops(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = fct_tests[k].test_func)) {
+ int i, repeat = 1;
+ simple_test_t test_group = fct_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < nb_special_fargs; i++) {
+ double result;
+#define SINGLE_MASK 0x00000000FFFFFFFFULL
+
+ f14 = spec_fargs[i];
+ // execute test insn
+ SET_FPSCR_ZERO;
+ (*func)();
+ result = f17;
+ printf("#%d: %s%s: ", i, test_group.name, do_dot ? "." : "");
+ printf("0x%016llx (%e) ==> 0x%016llx\n",
+ *((unsigned long long *)(&spec_fargs[i])), spec_fargs[i],
+ test_group.precision == SINGLE_TEST ? (SINGLE_MASK &
+ *((unsigned long long *)(&result))) :
+ *((unsigned long long *)(&result)));
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+#ifdef __powerpc64__
+void test_stdbrx(void)
+{
+ unsigned long long store, val = 0xdeadbacf12345678ULL;
+ printf("stdbrx: 0x%llx ==> ", val);
+ r17 = (HWord_t)val;
+ r14 = (HWord_t)&store;
+ __asm__ __volatile__ ("stdbrx %0, 0, %1" : : "r"(r17), "r"(r14));
+ printf("0x%llx\n", store);
+ printf( "\n" );
+}
+#endif
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_vx_vector_one_fp_arg,
+ "Test VSX vector single arg instructions"},
+ { &test_vx_vector_fp_ops,
+ "Test VSX floating point compare and basic arithmetic instructions" },
+#ifdef __powerpc64__
+ { &test_bpermd,
+ "Test bit permute double"},
+#endif
+ { &test_xxsel,
+ "Test xxsel instruction" },
+ { &test_xxspltw,
+ "Test xxspltw instruction" },
+ { &test_div_extensions,
+ "Test div extensions" },
+ { &test_fct_ops,
+ "Test floating point convert [word | doubleword] unsigned, with round toward zero" },
+#ifdef __powerpc64__
+ { &test_stdbrx,
+ "Test stdbrx instruction"},
+#endif
+ { &test_vx_aORm_fp_ops,
+ "Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p"},
+ { &test_vx_simple_scalar_fp_ops,
+ "Test scalar floating point arithmetic instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_VSX
+
+int main(int argc, char *argv[])
+{
+#ifdef HAS_VSX
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+ if (spec_fargs)
+ free(spec_fargs);
+ if (spec_sp_fargs)
+ free(spec_sp_fargs);
+
+#endif // HAS _VSX
+
+ return 0;
+}
diff --git a/main/none/tests/ppc64/test_isa_2_06_part2.stderr.exp b/main/none/tests/ppc64/test_isa_2_06_part2.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part2.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc64/test_isa_2_06_part2.stdout.exp b/main/none/tests/ppc64/test_isa_2_06_part2.stdout.exp
new file mode 100644
index 0000000..4c9b439
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part2.stdout.exp
@@ -0,0 +1,1763 @@
+Test VSX vector single arg instructions
+#0: xvresp 1/x(3ec00000) ==> PASS; 1/x(42780000) ==> PASS; 1/x(00000000) ==> PASS; 1/x(7f800000) ==> PASS
+#1: xvresp 1/x(00000000) ==> PASS; 1/x(00000000) ==> PASS; 1/x(80000000) ==> PASS; 1/x(7f800000) ==> PASS
+#2: xvresp 1/x(ff800000) ==> PASS; 1/x(7fffffff) ==> PASS; 1/x(ffffffff) ==> PASS; 1/x(7fc00000) ==> PASS
+#3: xvresp 1/x(ffc00000) ==> PASS; 1/x(80000000) ==> PASS; 1/x(c683287b) ==> PASS; 1/x(49192c2d) ==> PASS
+
+#0: xvcvdpsxws conv(3fd8000000000000) = 0000000000000000; conv(404f000000000000) = 000000000000003e
+#1: xvcvdpsxws conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = 000000007fffffff
+#2: xvcvdpsxws conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpsxws conv(8000000000000000) = 0000000000000000; conv(7ff0000000000000) = 000000007fffffff
+#4: xvcvdpsxws conv(fff0000000000000) = 0000000080000000; conv(7ff7ffffffffffff) = 0000000080000000
+#5: xvcvdpsxws conv(fff7ffffffffffff) = 0000000080000000; conv(7ff8000000000000) = 0000000080000000
+#6: xvcvdpsxws conv(fff8000000000000) = 0000000080000000; conv(8008340000078000) = 0000000000000000
+#7: xvcvdpsxws conv(c0d0650f5a07b353) = 00000000ffffbe6c; conv(41232585a9900000) = 00000000000992c2
+
+#0: xvcvspsxws conv(3ec00000) = 00000000; conv(42780000) = 0000003e; conv(00000000) = 00000000; conv(7f800000) = 7fffffff
+#1: xvcvspsxws conv(00000000) = 00000000; conv(00000000) = 00000000; conv(80000000) = 00000000; conv(7f800000) = 7fffffff
+#2: xvcvspsxws conv(ff800000) = 80000000; conv(7fffffff) = 80000000; conv(ffffffff) = 80000000; conv(7fc00000) = 80000000
+#3: xvcvspsxws conv(ffc00000) = 80000000; conv(80000000) = 00000000; conv(c683287b) = ffffbe6c; conv(49192c2d) = 000992c2
+
+Test VSX floating point compare and basic arithmetic instructions
+#0: xvcmpeqdp fff0000000000000 eq fff0000000000000 AND fff0000000000000 eq c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#1: xvcmpeqdp fff0000000000000 eq 8000000000000000 AND fff0000000000000 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#2: xvcmpeqdp fff0000000000000 eq 0123214569900000 AND fff0000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#3: xvcmpeqdp fff0000000000000 eq 7ff7ffffffffffff AND fff0000000000000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#4: xvcmpeqdp c0d0650f5a07b353 eq fff0000000000000 AND c0d0650f5a07b353 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 ffffffffffffffff
+#5: xvcmpeqdp c0d0650f5a07b353 eq 8000000000000000 AND c0d0650f5a07b353 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#6: xvcmpeqdp c0d0650f5a07b353 eq 0123214569900000 AND c0d0650f5a07b353 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#7: xvcmpeqdp c0d0650f5a07b353 eq 7ff7ffffffffffff AND c0d0650f5a07b353 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#8: xvcmpeqdp 8000000000000000 eq fff0000000000000 AND 8000000000000000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#9: xvcmpeqdp 8000000000000000 eq 8000000000000000 AND 8000000000000000 eq 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#10: xvcmpeqdp 8000000000000000 eq 0123214569900000 AND 8000000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#11: xvcmpeqdp 8000000000000000 eq 7ff7ffffffffffff AND 8000000000000000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#12: xvcmpeqdp 0000000000000000 eq fff0000000000000 AND 0000000000000000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#13: xvcmpeqdp 0000000000000000 eq 8000000000000000 AND 0000000000000000 eq 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#14: xvcmpeqdp 0000000000000000 eq 0123214569900000 AND 0000000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#15: xvcmpeqdp 0000000000000000 eq 7ff7ffffffffffff AND 0000000000000000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#16: xvcmpeqdp 0123214569900000 eq fff0000000000000 AND 0123214569900000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#17: xvcmpeqdp 0123214569900000 eq 8000000000000000 AND 0123214569900000 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#18: xvcmpeqdp 0123214569900000 eq 404f000000000000 AND 0123214569900000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#19: xvcmpeqdp 0123214569900000 eq 7ff7ffffffffffff AND 0123214569900000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#20: xvcmpeqdp 7ff0000000000000 eq fff0000000000000 AND 7ff0000000000000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#21: xvcmpeqdp 7ff0000000000000 eq 8000000000000000 AND 7ff0000000000000 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#22: xvcmpeqdp 7ff0000000000000 eq 0123214569900000 AND 7ff0000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 ffffffffffffffff
+#23: xvcmpeqdp 7ff0000000000000 eq 7ff7ffffffffffff AND 7ff0000000000000 eq 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#24: xvcmpeqdp fff7ffffffffffff eq fff0000000000000 AND fff7ffffffffffff eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#25: xvcmpeqdp fff7ffffffffffff eq 8000000000000000 AND fff7ffffffffffff eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#26: xvcmpeqdp fff7ffffffffffff eq 0123214569900000 AND fff7ffffffffffff eq 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#27: xvcmpeqdp fff7ffffffffffff eq 7ff7ffffffffffff AND fff7ffffffffffff eq fff7ffffffffffff ? cc=0 => 0000000000000000 0000000000000000
+#28: xvcmpeqdp fff8000000000000 eq fff0000000000000 AND fff8000000000000 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#29: xvcmpeqdp fff8000000000000 eq 8000000000000000 AND fff8000000000000 eq 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#30: xvcmpeqdp 404f000000000000 eq 404f000000000000 AND 0018000000b77501 eq 0018000000b77501 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#31: xvcmpeqdp 7fe800000000051b eq 7fe800000000051b AND 0123214569900000 eq 0123214569900000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+
+#0: xvcmpeqdp. fff0000000000000 eq fff0000000000000 AND fff0000000000000 eq c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#1: xvcmpeqdp. fff0000000000000 eq 8000000000000000 AND fff0000000000000 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#2: xvcmpeqdp. fff0000000000000 eq 0123214569900000 AND fff0000000000000 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#3: xvcmpeqdp. fff0000000000000 eq 7ff7ffffffffffff AND fff0000000000000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#4: xvcmpeqdp. c0d0650f5a07b353 eq fff0000000000000 AND c0d0650f5a07b353 eq c0d0650f5a07b353 ? cc=0 => 0000000000000000 ffffffffffffffff
+#5: xvcmpeqdp. c0d0650f5a07b353 eq 8000000000000000 AND c0d0650f5a07b353 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#6: xvcmpeqdp. c0d0650f5a07b353 eq 0123214569900000 AND c0d0650f5a07b353 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#7: xvcmpeqdp. c0d0650f5a07b353 eq 7ff7ffffffffffff AND c0d0650f5a07b353 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#8: xvcmpeqdp. 8000000000000000 eq fff0000000000000 AND 8000000000000000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#9: xvcmpeqdp. 8000000000000000 eq 8000000000000000 AND 8000000000000000 eq 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#10: xvcmpeqdp. 8000000000000000 eq 0123214569900000 AND 8000000000000000 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#11: xvcmpeqdp. 8000000000000000 eq 7ff7ffffffffffff AND 8000000000000000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#12: xvcmpeqdp. 0000000000000000 eq fff0000000000000 AND 0000000000000000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#13: xvcmpeqdp. 0000000000000000 eq 8000000000000000 AND 0000000000000000 eq 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#14: xvcmpeqdp. 0000000000000000 eq 0123214569900000 AND 0000000000000000 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#15: xvcmpeqdp. 0000000000000000 eq 7ff7ffffffffffff AND 0000000000000000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#16: xvcmpeqdp. 0123214569900000 eq fff0000000000000 AND 0123214569900000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#17: xvcmpeqdp. 0123214569900000 eq 8000000000000000 AND 0123214569900000 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#18: xvcmpeqdp. 0123214569900000 eq 404f000000000000 AND 0123214569900000 eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#19: xvcmpeqdp. 0123214569900000 eq 7ff7ffffffffffff AND 0123214569900000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#20: xvcmpeqdp. 7ff0000000000000 eq fff0000000000000 AND 7ff0000000000000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#21: xvcmpeqdp. 7ff0000000000000 eq 8000000000000000 AND 7ff0000000000000 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#22: xvcmpeqdp. 7ff0000000000000 eq 0123214569900000 AND 7ff0000000000000 eq 7ff0000000000000 ? cc=0 => 0000000000000000 ffffffffffffffff
+#23: xvcmpeqdp. 7ff0000000000000 eq 7ff7ffffffffffff AND 7ff0000000000000 eq 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#24: xvcmpeqdp. fff7ffffffffffff eq fff0000000000000 AND fff7ffffffffffff eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#25: xvcmpeqdp. fff7ffffffffffff eq 8000000000000000 AND fff7ffffffffffff eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#26: xvcmpeqdp. fff7ffffffffffff eq 0123214569900000 AND fff7ffffffffffff eq 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#27: xvcmpeqdp. fff7ffffffffffff eq 7ff7ffffffffffff AND fff7ffffffffffff eq fff7ffffffffffff ? cc=2 => 0000000000000000 0000000000000000
+#28: xvcmpeqdp. fff8000000000000 eq fff0000000000000 AND fff8000000000000 eq c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#29: xvcmpeqdp. fff8000000000000 eq 8000000000000000 AND fff8000000000000 eq 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#30: xvcmpeqdp. 404f000000000000 eq 404f000000000000 AND 0018000000b77501 eq 0018000000b77501 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#31: xvcmpeqdp. 7fe800000000051b eq 7fe800000000051b AND 0123214569900000 eq 0123214569900000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+
+
+#0: xvcmpgedp fff0000000000000 ge fff0000000000000 AND fff0000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#1: xvcmpgedp fff0000000000000 ge 8000000000000000 AND fff0000000000000 ge 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#2: xvcmpgedp fff0000000000000 ge 0123214569900000 AND fff0000000000000 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#3: xvcmpgedp fff0000000000000 ge 7ff7ffffffffffff AND fff0000000000000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#4: xvcmpgedp c0d0650f5a07b353 ge fff0000000000000 AND c0d0650f5a07b353 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#5: xvcmpgedp c0d0650f5a07b353 ge 8000000000000000 AND c0d0650f5a07b353 ge 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#6: xvcmpgedp c0d0650f5a07b353 ge 0123214569900000 AND c0d0650f5a07b353 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#7: xvcmpgedp c0d0650f5a07b353 ge 7ff7ffffffffffff AND c0d0650f5a07b353 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#8: xvcmpgedp 8000000000000000 ge fff0000000000000 AND 8000000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#9: xvcmpgedp 8000000000000000 ge 8000000000000000 AND 8000000000000000 ge 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#10: xvcmpgedp 8000000000000000 ge 0123214569900000 AND 8000000000000000 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#11: xvcmpgedp 8000000000000000 ge 7ff7ffffffffffff AND 8000000000000000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#12: xvcmpgedp 0000000000000000 ge fff0000000000000 AND 0000000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#13: xvcmpgedp 0000000000000000 ge 8000000000000000 AND 0000000000000000 ge 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#14: xvcmpgedp 0000000000000000 ge 0123214569900000 AND 0000000000000000 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#15: xvcmpgedp 0000000000000000 ge 7ff7ffffffffffff AND 0000000000000000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#16: xvcmpgedp 0123214569900000 ge fff0000000000000 AND 0123214569900000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#17: xvcmpgedp 0123214569900000 ge 8000000000000000 AND 0123214569900000 ge 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#18: xvcmpgedp 0123214569900000 ge 404f000000000000 AND 0123214569900000 ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#19: xvcmpgedp 0123214569900000 ge 7ff7ffffffffffff AND 0123214569900000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#20: xvcmpgedp 7ff0000000000000 ge fff0000000000000 AND 7ff0000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#21: xvcmpgedp 7ff0000000000000 ge 8000000000000000 AND 7ff0000000000000 ge 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#22: xvcmpgedp 7ff0000000000000 ge 0123214569900000 AND 7ff0000000000000 ge 7ff0000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#23: xvcmpgedp 7ff0000000000000 ge 7ff7ffffffffffff AND 7ff0000000000000 ge 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#24: xvcmpgedp fff7ffffffffffff ge fff0000000000000 AND fff7ffffffffffff ge c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#25: xvcmpgedp fff7ffffffffffff ge 8000000000000000 AND fff7ffffffffffff ge 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#26: xvcmpgedp fff7ffffffffffff ge 0123214569900000 AND fff7ffffffffffff ge 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#27: xvcmpgedp fff7ffffffffffff ge 7ff7ffffffffffff AND fff7ffffffffffff ge fff7ffffffffffff ? cc=0 => 0000000000000000 0000000000000000
+#28: xvcmpgedp fff8000000000000 ge fff0000000000000 AND fff8000000000000 ge c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#29: xvcmpgedp fff8000000000000 ge 8000000000000000 AND fff8000000000000 ge 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#30: xvcmpgedp 404f000000000000 ge 404f000000000000 AND 0018000000b77501 ge 0018000000b77501 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#31: xvcmpgedp 7fe800000000051b ge 7fe800000000051b AND 0123214569900000 ge 0123214569900000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+
+#0: xvcmpgedp. fff0000000000000 ge fff0000000000000 AND fff0000000000000 ge c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#1: xvcmpgedp. fff0000000000000 ge 8000000000000000 AND fff0000000000000 ge 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#2: xvcmpgedp. fff0000000000000 ge 0123214569900000 AND fff0000000000000 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#3: xvcmpgedp. fff0000000000000 ge 7ff7ffffffffffff AND fff0000000000000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#4: xvcmpgedp. c0d0650f5a07b353 ge fff0000000000000 AND c0d0650f5a07b353 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#5: xvcmpgedp. c0d0650f5a07b353 ge 8000000000000000 AND c0d0650f5a07b353 ge 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#6: xvcmpgedp. c0d0650f5a07b353 ge 0123214569900000 AND c0d0650f5a07b353 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#7: xvcmpgedp. c0d0650f5a07b353 ge 7ff7ffffffffffff AND c0d0650f5a07b353 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#8: xvcmpgedp. 8000000000000000 ge fff0000000000000 AND 8000000000000000 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#9: xvcmpgedp. 8000000000000000 ge 8000000000000000 AND 8000000000000000 ge 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#10: xvcmpgedp. 8000000000000000 ge 0123214569900000 AND 8000000000000000 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#11: xvcmpgedp. 8000000000000000 ge 7ff7ffffffffffff AND 8000000000000000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#12: xvcmpgedp. 0000000000000000 ge fff0000000000000 AND 0000000000000000 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#13: xvcmpgedp. 0000000000000000 ge 8000000000000000 AND 0000000000000000 ge 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#14: xvcmpgedp. 0000000000000000 ge 0123214569900000 AND 0000000000000000 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#15: xvcmpgedp. 0000000000000000 ge 7ff7ffffffffffff AND 0000000000000000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#16: xvcmpgedp. 0123214569900000 ge fff0000000000000 AND 0123214569900000 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#17: xvcmpgedp. 0123214569900000 ge 8000000000000000 AND 0123214569900000 ge 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#18: xvcmpgedp. 0123214569900000 ge 404f000000000000 AND 0123214569900000 ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#19: xvcmpgedp. 0123214569900000 ge 7ff7ffffffffffff AND 0123214569900000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#20: xvcmpgedp. 7ff0000000000000 ge fff0000000000000 AND 7ff0000000000000 ge c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#21: xvcmpgedp. 7ff0000000000000 ge 8000000000000000 AND 7ff0000000000000 ge 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#22: xvcmpgedp. 7ff0000000000000 ge 0123214569900000 AND 7ff0000000000000 ge 7ff0000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#23: xvcmpgedp. 7ff0000000000000 ge 7ff7ffffffffffff AND 7ff0000000000000 ge 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#24: xvcmpgedp. fff7ffffffffffff ge fff0000000000000 AND fff7ffffffffffff ge c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#25: xvcmpgedp. fff7ffffffffffff ge 8000000000000000 AND fff7ffffffffffff ge 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#26: xvcmpgedp. fff7ffffffffffff ge 0123214569900000 AND fff7ffffffffffff ge 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#27: xvcmpgedp. fff7ffffffffffff ge 7ff7ffffffffffff AND fff7ffffffffffff ge fff7ffffffffffff ? cc=2 => 0000000000000000 0000000000000000
+#28: xvcmpgedp. fff8000000000000 ge fff0000000000000 AND fff8000000000000 ge c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#29: xvcmpgedp. fff8000000000000 ge 8000000000000000 AND fff8000000000000 ge 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#30: xvcmpgedp. 404f000000000000 ge 404f000000000000 AND 0018000000b77501 ge 0018000000b77501 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#31: xvcmpgedp. 7fe800000000051b ge 7fe800000000051b AND 0123214569900000 ge 0123214569900000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+
+
+#0: xvcmpgtdp fff0000000000000 gt fff0000000000000 AND fff0000000000000 gt c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#1: xvcmpgtdp fff0000000000000 gt 8000000000000000 AND fff0000000000000 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#2: xvcmpgtdp fff0000000000000 gt 0123214569900000 AND fff0000000000000 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#3: xvcmpgtdp fff0000000000000 gt 7ff7ffffffffffff AND fff0000000000000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#4: xvcmpgtdp c0d0650f5a07b353 gt fff0000000000000 AND c0d0650f5a07b353 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#5: xvcmpgtdp c0d0650f5a07b353 gt 8000000000000000 AND c0d0650f5a07b353 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#6: xvcmpgtdp c0d0650f5a07b353 gt 0123214569900000 AND c0d0650f5a07b353 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#7: xvcmpgtdp c0d0650f5a07b353 gt 7ff7ffffffffffff AND c0d0650f5a07b353 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#8: xvcmpgtdp 8000000000000000 gt fff0000000000000 AND 8000000000000000 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#9: xvcmpgtdp 8000000000000000 gt 8000000000000000 AND 8000000000000000 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#10: xvcmpgtdp 8000000000000000 gt 0123214569900000 AND 8000000000000000 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#11: xvcmpgtdp 8000000000000000 gt 7ff7ffffffffffff AND 8000000000000000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#12: xvcmpgtdp 0000000000000000 gt fff0000000000000 AND 0000000000000000 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#13: xvcmpgtdp 0000000000000000 gt 8000000000000000 AND 0000000000000000 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#14: xvcmpgtdp 0000000000000000 gt 0123214569900000 AND 0000000000000000 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#15: xvcmpgtdp 0000000000000000 gt 7ff7ffffffffffff AND 0000000000000000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#16: xvcmpgtdp 0123214569900000 gt fff0000000000000 AND 0123214569900000 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#17: xvcmpgtdp 0123214569900000 gt 8000000000000000 AND 0123214569900000 gt 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#18: xvcmpgtdp 0123214569900000 gt 404f000000000000 AND 0123214569900000 gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#19: xvcmpgtdp 0123214569900000 gt 7ff7ffffffffffff AND 0123214569900000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#20: xvcmpgtdp 7ff0000000000000 gt fff0000000000000 AND 7ff0000000000000 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#21: xvcmpgtdp 7ff0000000000000 gt 8000000000000000 AND 7ff0000000000000 gt 0000000000000000 ? cc=0 => ffffffffffffffff ffffffffffffffff
+#22: xvcmpgtdp 7ff0000000000000 gt 0123214569900000 AND 7ff0000000000000 gt 7ff0000000000000 ? cc=0 => ffffffffffffffff 0000000000000000
+#23: xvcmpgtdp 7ff0000000000000 gt 7ff7ffffffffffff AND 7ff0000000000000 gt 7ff8000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#24: xvcmpgtdp fff7ffffffffffff gt fff0000000000000 AND fff7ffffffffffff gt c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#25: xvcmpgtdp fff7ffffffffffff gt 8000000000000000 AND fff7ffffffffffff gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#26: xvcmpgtdp fff7ffffffffffff gt 0123214569900000 AND fff7ffffffffffff gt 7ff0000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#27: xvcmpgtdp fff7ffffffffffff gt 7ff7ffffffffffff AND fff7ffffffffffff gt fff7ffffffffffff ? cc=0 => 0000000000000000 0000000000000000
+#28: xvcmpgtdp fff8000000000000 gt fff0000000000000 AND fff8000000000000 gt c0d0650f5a07b353 ? cc=0 => 0000000000000000 0000000000000000
+#29: xvcmpgtdp fff8000000000000 gt 8000000000000000 AND fff8000000000000 gt 0000000000000000 ? cc=0 => 0000000000000000 0000000000000000
+#30: xvcmpgtdp 404f000000000000 gt 404f000000000000 AND 0018000000b77501 gt 0018000000b77501 ? cc=0 => 0000000000000000 0000000000000000
+#31: xvcmpgtdp 7fe800000000051b gt 7fe800000000051b AND 0123214569900000 gt 0123214569900000 ? cc=0 => 0000000000000000 0000000000000000
+
+#0: xvcmpgtdp. fff0000000000000 gt fff0000000000000 AND fff0000000000000 gt c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#1: xvcmpgtdp. fff0000000000000 gt 8000000000000000 AND fff0000000000000 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#2: xvcmpgtdp. fff0000000000000 gt 0123214569900000 AND fff0000000000000 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#3: xvcmpgtdp. fff0000000000000 gt 7ff7ffffffffffff AND fff0000000000000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#4: xvcmpgtdp. c0d0650f5a07b353 gt fff0000000000000 AND c0d0650f5a07b353 gt c0d0650f5a07b353 ? cc=0 => ffffffffffffffff 0000000000000000
+#5: xvcmpgtdp. c0d0650f5a07b353 gt 8000000000000000 AND c0d0650f5a07b353 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#6: xvcmpgtdp. c0d0650f5a07b353 gt 0123214569900000 AND c0d0650f5a07b353 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#7: xvcmpgtdp. c0d0650f5a07b353 gt 7ff7ffffffffffff AND c0d0650f5a07b353 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#8: xvcmpgtdp. 8000000000000000 gt fff0000000000000 AND 8000000000000000 gt c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#9: xvcmpgtdp. 8000000000000000 gt 8000000000000000 AND 8000000000000000 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#10: xvcmpgtdp. 8000000000000000 gt 0123214569900000 AND 8000000000000000 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#11: xvcmpgtdp. 8000000000000000 gt 7ff7ffffffffffff AND 8000000000000000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#12: xvcmpgtdp. 0000000000000000 gt fff0000000000000 AND 0000000000000000 gt c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#13: xvcmpgtdp. 0000000000000000 gt 8000000000000000 AND 0000000000000000 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#14: xvcmpgtdp. 0000000000000000 gt 0123214569900000 AND 0000000000000000 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#15: xvcmpgtdp. 0000000000000000 gt 7ff7ffffffffffff AND 0000000000000000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#16: xvcmpgtdp. 0123214569900000 gt fff0000000000000 AND 0123214569900000 gt c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#17: xvcmpgtdp. 0123214569900000 gt 8000000000000000 AND 0123214569900000 gt 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#18: xvcmpgtdp. 0123214569900000 gt 404f000000000000 AND 0123214569900000 gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#19: xvcmpgtdp. 0123214569900000 gt 7ff7ffffffffffff AND 0123214569900000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#20: xvcmpgtdp. 7ff0000000000000 gt fff0000000000000 AND 7ff0000000000000 gt c0d0650f5a07b353 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#21: xvcmpgtdp. 7ff0000000000000 gt 8000000000000000 AND 7ff0000000000000 gt 0000000000000000 ? cc=8 => ffffffffffffffff ffffffffffffffff
+#22: xvcmpgtdp. 7ff0000000000000 gt 0123214569900000 AND 7ff0000000000000 gt 7ff0000000000000 ? cc=0 => ffffffffffffffff 0000000000000000
+#23: xvcmpgtdp. 7ff0000000000000 gt 7ff7ffffffffffff AND 7ff0000000000000 gt 7ff8000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#24: xvcmpgtdp. fff7ffffffffffff gt fff0000000000000 AND fff7ffffffffffff gt c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#25: xvcmpgtdp. fff7ffffffffffff gt 8000000000000000 AND fff7ffffffffffff gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#26: xvcmpgtdp. fff7ffffffffffff gt 0123214569900000 AND fff7ffffffffffff gt 7ff0000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#27: xvcmpgtdp. fff7ffffffffffff gt 7ff7ffffffffffff AND fff7ffffffffffff gt fff7ffffffffffff ? cc=2 => 0000000000000000 0000000000000000
+#28: xvcmpgtdp. fff8000000000000 gt fff0000000000000 AND fff8000000000000 gt c0d0650f5a07b353 ? cc=2 => 0000000000000000 0000000000000000
+#29: xvcmpgtdp. fff8000000000000 gt 8000000000000000 AND fff8000000000000 gt 0000000000000000 ? cc=2 => 0000000000000000 0000000000000000
+#30: xvcmpgtdp. 404f000000000000 gt 404f000000000000 AND 0018000000b77501 gt 0018000000b77501 ? cc=2 => 0000000000000000 0000000000000000
+#31: xvcmpgtdp. 7fe800000000051b gt 7fe800000000051b AND 0123214569900000 gt 0123214569900000 ? cc=2 => 0000000000000000 0000000000000000
+
+
+#0: xvcmpeqsp ff800000 eq ff800000 AND ff800000 eq c683287b AND ff800000 eq 80000000 AND ff800000 eq 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#1: xvcmpeqsp ff800000 eq 00000000 AND ff800000 eq 7f800000 AND ff800000 eq 7fffffff AND ff800000 eq 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#2: xvcmpeqsp c683287b eq ff800000 AND c683287b eq c683287b AND c683287b eq 80000000 AND c683287b eq 00000000 ? cc=0 => 00000000 ffffffff 00000000 00000000
+#3: xvcmpeqsp c683287b eq 00000000 AND c683287b eq 7f800000 AND c683287b eq 7fffffff AND c683287b eq 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#4: xvcmpeqsp 80000000 eq ff800000 AND 80000000 eq c683287b AND 80000000 eq 80000000 AND 80000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#5: xvcmpeqsp 80000000 eq 00000000 AND 80000000 eq 7f800000 AND 80000000 eq 7fffffff AND 80000000 eq 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#6: xvcmpeqsp 00000000 eq ff800000 AND 00000000 eq c683287b AND 00000000 eq 80000000 AND 00000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#7: xvcmpeqsp 00000000 eq 00000000 AND 00000000 eq 7f800000 AND 00000000 eq 7fffffff AND 00000000 eq 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#8: xvcmpeqsp 00000000 eq ff800000 AND 00000000 eq c683287b AND 00000000 eq 80000000 AND 00000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#9: xvcmpeqsp 00000000 eq 42780000 AND 00000000 eq 7f800000 AND 00000000 eq 7fffffff AND 00000000 eq 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#10: xvcmpeqsp 7f800000 eq ff800000 AND 7f800000 eq c683287b AND 7f800000 eq 80000000 AND 7f800000 eq 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#11: xvcmpeqsp 7f800000 eq 00000000 AND 7f800000 eq 7f800000 AND 7f800000 eq 7fffffff AND 7f800000 eq 7fc00000 ? cc=0 => 00000000 ffffffff 00000000 00000000
+#12: xvcmpeqsp ffffffff eq ff800000 AND ffffffff eq c683287b AND ffffffff eq 80000000 AND ffffffff eq 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#13: xvcmpeqsp ffffffff eq 00000000 AND ffffffff eq 7f800000 AND ffffffff eq 7fffffff AND ffffffff eq ffffffff ? cc=0 => 00000000 00000000 00000000 00000000
+#14: xvcmpeqsp ffc00000 eq ff800000 AND ffc00000 eq c683287b AND ffc00000 eq 80000000 AND ffc00000 eq 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#15: xvcmpeqsp 42780000 eq 42780000 AND 00000000 eq 00000000 AND 7f800000 eq 7f800000 AND 00000000 eq 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+
+#0: xvcmpeqsp. ff800000 eq ff800000 AND ff800000 eq c683287b AND ff800000 eq 80000000 AND ff800000 eq 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#1: xvcmpeqsp. ff800000 eq 00000000 AND ff800000 eq 7f800000 AND ff800000 eq 7fffffff AND ff800000 eq 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#2: xvcmpeqsp. c683287b eq ff800000 AND c683287b eq c683287b AND c683287b eq 80000000 AND c683287b eq 00000000 ? cc=0 => 00000000 ffffffff 00000000 00000000
+#3: xvcmpeqsp. c683287b eq 00000000 AND c683287b eq 7f800000 AND c683287b eq 7fffffff AND c683287b eq 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#4: xvcmpeqsp. 80000000 eq ff800000 AND 80000000 eq c683287b AND 80000000 eq 80000000 AND 80000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#5: xvcmpeqsp. 80000000 eq 00000000 AND 80000000 eq 7f800000 AND 80000000 eq 7fffffff AND 80000000 eq 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#6: xvcmpeqsp. 00000000 eq ff800000 AND 00000000 eq c683287b AND 00000000 eq 80000000 AND 00000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#7: xvcmpeqsp. 00000000 eq 00000000 AND 00000000 eq 7f800000 AND 00000000 eq 7fffffff AND 00000000 eq 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#8: xvcmpeqsp. 00000000 eq ff800000 AND 00000000 eq c683287b AND 00000000 eq 80000000 AND 00000000 eq 00000000 ? cc=0 => 00000000 00000000 ffffffff ffffffff
+#9: xvcmpeqsp. 00000000 eq 42780000 AND 00000000 eq 7f800000 AND 00000000 eq 7fffffff AND 00000000 eq 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#10: xvcmpeqsp. 7f800000 eq ff800000 AND 7f800000 eq c683287b AND 7f800000 eq 80000000 AND 7f800000 eq 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#11: xvcmpeqsp. 7f800000 eq 00000000 AND 7f800000 eq 7f800000 AND 7f800000 eq 7fffffff AND 7f800000 eq 7fc00000 ? cc=0 => 00000000 ffffffff 00000000 00000000
+#12: xvcmpeqsp. ffffffff eq ff800000 AND ffffffff eq c683287b AND ffffffff eq 80000000 AND ffffffff eq 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#13: xvcmpeqsp. ffffffff eq 00000000 AND ffffffff eq 7f800000 AND ffffffff eq 7fffffff AND ffffffff eq ffffffff ? cc=2 => 00000000 00000000 00000000 00000000
+#14: xvcmpeqsp. ffc00000 eq ff800000 AND ffc00000 eq c683287b AND ffc00000 eq 80000000 AND ffc00000 eq 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#15: xvcmpeqsp. 42780000 eq 42780000 AND 00000000 eq 00000000 AND 7f800000 eq 7f800000 AND 00000000 eq 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+
+
+#0: xvcmpgesp ff800000 ge ff800000 AND ff800000 ge c683287b AND ff800000 ge 80000000 AND ff800000 ge 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#1: xvcmpgesp ff800000 ge 00000000 AND ff800000 ge 7f800000 AND ff800000 ge 7fffffff AND ff800000 ge 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#2: xvcmpgesp c683287b ge ff800000 AND c683287b ge c683287b AND c683287b ge 80000000 AND c683287b ge 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#3: xvcmpgesp c683287b ge 00000000 AND c683287b ge 7f800000 AND c683287b ge 7fffffff AND c683287b ge 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#4: xvcmpgesp 80000000 ge ff800000 AND 80000000 ge c683287b AND 80000000 ge 80000000 AND 80000000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#5: xvcmpgesp 80000000 ge 00000000 AND 80000000 ge 7f800000 AND 80000000 ge 7fffffff AND 80000000 ge 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#6: xvcmpgesp 00000000 ge ff800000 AND 00000000 ge c683287b AND 00000000 ge 80000000 AND 00000000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#7: xvcmpgesp 00000000 ge 00000000 AND 00000000 ge 7f800000 AND 00000000 ge 7fffffff AND 00000000 ge 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#8: xvcmpgesp 00000000 ge ff800000 AND 00000000 ge c683287b AND 00000000 ge 80000000 AND 00000000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#9: xvcmpgesp 00000000 ge 42780000 AND 00000000 ge 7f800000 AND 00000000 ge 7fffffff AND 00000000 ge 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#10: xvcmpgesp 7f800000 ge ff800000 AND 7f800000 ge c683287b AND 7f800000 ge 80000000 AND 7f800000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#11: xvcmpgesp 7f800000 ge 00000000 AND 7f800000 ge 7f800000 AND 7f800000 ge 7fffffff AND 7f800000 ge 7fc00000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#12: xvcmpgesp ffffffff ge ff800000 AND ffffffff ge c683287b AND ffffffff ge 80000000 AND ffffffff ge 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#13: xvcmpgesp ffffffff ge 00000000 AND ffffffff ge 7f800000 AND ffffffff ge 7fffffff AND ffffffff ge ffffffff ? cc=0 => 00000000 00000000 00000000 00000000
+#14: xvcmpgesp ffc00000 ge ff800000 AND ffc00000 ge c683287b AND ffc00000 ge 80000000 AND ffc00000 ge 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#15: xvcmpgesp 42780000 ge 42780000 AND 00000000 ge 00000000 AND 7f800000 ge 7f800000 AND 00000000 ge 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+
+#0: xvcmpgesp. ff800000 ge ff800000 AND ff800000 ge c683287b AND ff800000 ge 80000000 AND ff800000 ge 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#1: xvcmpgesp. ff800000 ge 00000000 AND ff800000 ge 7f800000 AND ff800000 ge 7fffffff AND ff800000 ge 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#2: xvcmpgesp. c683287b ge ff800000 AND c683287b ge c683287b AND c683287b ge 80000000 AND c683287b ge 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#3: xvcmpgesp. c683287b ge 00000000 AND c683287b ge 7f800000 AND c683287b ge 7fffffff AND c683287b ge 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#4: xvcmpgesp. 80000000 ge ff800000 AND 80000000 ge c683287b AND 80000000 ge 80000000 AND 80000000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#5: xvcmpgesp. 80000000 ge 00000000 AND 80000000 ge 7f800000 AND 80000000 ge 7fffffff AND 80000000 ge 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#6: xvcmpgesp. 00000000 ge ff800000 AND 00000000 ge c683287b AND 00000000 ge 80000000 AND 00000000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#7: xvcmpgesp. 00000000 ge 00000000 AND 00000000 ge 7f800000 AND 00000000 ge 7fffffff AND 00000000 ge 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#8: xvcmpgesp. 00000000 ge ff800000 AND 00000000 ge c683287b AND 00000000 ge 80000000 AND 00000000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#9: xvcmpgesp. 00000000 ge 42780000 AND 00000000 ge 7f800000 AND 00000000 ge 7fffffff AND 00000000 ge 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#10: xvcmpgesp. 7f800000 ge ff800000 AND 7f800000 ge c683287b AND 7f800000 ge 80000000 AND 7f800000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#11: xvcmpgesp. 7f800000 ge 00000000 AND 7f800000 ge 7f800000 AND 7f800000 ge 7fffffff AND 7f800000 ge 7fc00000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#12: xvcmpgesp. ffffffff ge ff800000 AND ffffffff ge c683287b AND ffffffff ge 80000000 AND ffffffff ge 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#13: xvcmpgesp. ffffffff ge 00000000 AND ffffffff ge 7f800000 AND ffffffff ge 7fffffff AND ffffffff ge ffffffff ? cc=2 => 00000000 00000000 00000000 00000000
+#14: xvcmpgesp. ffc00000 ge ff800000 AND ffc00000 ge c683287b AND ffc00000 ge 80000000 AND ffc00000 ge 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#15: xvcmpgesp. 42780000 ge 42780000 AND 00000000 ge 00000000 AND 7f800000 ge 7f800000 AND 00000000 ge 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+
+
+#0: xvcmpgtsp ff800000 gt ff800000 AND ff800000 gt c683287b AND ff800000 gt 80000000 AND ff800000 gt 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#1: xvcmpgtsp ff800000 gt 00000000 AND ff800000 gt 7f800000 AND ff800000 gt 7fffffff AND ff800000 gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#2: xvcmpgtsp c683287b gt ff800000 AND c683287b gt c683287b AND c683287b gt 80000000 AND c683287b gt 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#3: xvcmpgtsp c683287b gt 00000000 AND c683287b gt 7f800000 AND c683287b gt 7fffffff AND c683287b gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#4: xvcmpgtsp 80000000 gt ff800000 AND 80000000 gt c683287b AND 80000000 gt 80000000 AND 80000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#5: xvcmpgtsp 80000000 gt 00000000 AND 80000000 gt 7f800000 AND 80000000 gt 7fffffff AND 80000000 gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#6: xvcmpgtsp 00000000 gt ff800000 AND 00000000 gt c683287b AND 00000000 gt 80000000 AND 00000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#7: xvcmpgtsp 00000000 gt 00000000 AND 00000000 gt 7f800000 AND 00000000 gt 7fffffff AND 00000000 gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#8: xvcmpgtsp 00000000 gt ff800000 AND 00000000 gt c683287b AND 00000000 gt 80000000 AND 00000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#9: xvcmpgtsp 00000000 gt 42780000 AND 00000000 gt 7f800000 AND 00000000 gt 7fffffff AND 00000000 gt 7fc00000 ? cc=0 => 00000000 00000000 00000000 00000000
+#10: xvcmpgtsp 7f800000 gt ff800000 AND 7f800000 gt c683287b AND 7f800000 gt 80000000 AND 7f800000 gt 00000000 ? cc=0 => ffffffff ffffffff ffffffff ffffffff
+#11: xvcmpgtsp 7f800000 gt 00000000 AND 7f800000 gt 7f800000 AND 7f800000 gt 7fffffff AND 7f800000 gt 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#12: xvcmpgtsp ffffffff gt ff800000 AND ffffffff gt c683287b AND ffffffff gt 80000000 AND ffffffff gt 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#13: xvcmpgtsp ffffffff gt 00000000 AND ffffffff gt 7f800000 AND ffffffff gt 7fffffff AND ffffffff gt ffffffff ? cc=0 => 00000000 00000000 00000000 00000000
+#14: xvcmpgtsp ffc00000 gt ff800000 AND ffc00000 gt c683287b AND ffc00000 gt 80000000 AND ffc00000 gt 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+#15: xvcmpgtsp 42780000 gt 42780000 AND 00000000 gt 00000000 AND 7f800000 gt 7f800000 AND 00000000 gt 00000000 ? cc=0 => 00000000 00000000 00000000 00000000
+
+#0: xvcmpgtsp. ff800000 gt ff800000 AND ff800000 gt c683287b AND ff800000 gt 80000000 AND ff800000 gt 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#1: xvcmpgtsp. ff800000 gt 00000000 AND ff800000 gt 7f800000 AND ff800000 gt 7fffffff AND ff800000 gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#2: xvcmpgtsp. c683287b gt ff800000 AND c683287b gt c683287b AND c683287b gt 80000000 AND c683287b gt 00000000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#3: xvcmpgtsp. c683287b gt 00000000 AND c683287b gt 7f800000 AND c683287b gt 7fffffff AND c683287b gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#4: xvcmpgtsp. 80000000 gt ff800000 AND 80000000 gt c683287b AND 80000000 gt 80000000 AND 80000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#5: xvcmpgtsp. 80000000 gt 00000000 AND 80000000 gt 7f800000 AND 80000000 gt 7fffffff AND 80000000 gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#6: xvcmpgtsp. 00000000 gt ff800000 AND 00000000 gt c683287b AND 00000000 gt 80000000 AND 00000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#7: xvcmpgtsp. 00000000 gt 00000000 AND 00000000 gt 7f800000 AND 00000000 gt 7fffffff AND 00000000 gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#8: xvcmpgtsp. 00000000 gt ff800000 AND 00000000 gt c683287b AND 00000000 gt 80000000 AND 00000000 gt 00000000 ? cc=0 => ffffffff ffffffff 00000000 00000000
+#9: xvcmpgtsp. 00000000 gt 42780000 AND 00000000 gt 7f800000 AND 00000000 gt 7fffffff AND 00000000 gt 7fc00000 ? cc=2 => 00000000 00000000 00000000 00000000
+#10: xvcmpgtsp. 7f800000 gt ff800000 AND 7f800000 gt c683287b AND 7f800000 gt 80000000 AND 7f800000 gt 00000000 ? cc=8 => ffffffff ffffffff ffffffff ffffffff
+#11: xvcmpgtsp. 7f800000 gt 00000000 AND 7f800000 gt 7f800000 AND 7f800000 gt 7fffffff AND 7f800000 gt 7fc00000 ? cc=0 => ffffffff 00000000 00000000 00000000
+#12: xvcmpgtsp. ffffffff gt ff800000 AND ffffffff gt c683287b AND ffffffff gt 80000000 AND ffffffff gt 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#13: xvcmpgtsp. ffffffff gt 00000000 AND ffffffff gt 7f800000 AND ffffffff gt 7fffffff AND ffffffff gt ffffffff ? cc=2 => 00000000 00000000 00000000 00000000
+#14: xvcmpgtsp. ffc00000 gt ff800000 AND ffc00000 gt c683287b AND ffc00000 gt 80000000 AND ffc00000 gt 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+#15: xvcmpgtsp. 42780000 gt 42780000 AND 00000000 gt 00000000 AND 7f800000 gt 7f800000 AND 00000000 gt 00000000 ? cc=2 => 00000000 00000000 00000000 00000000
+
+
+#0: xvadddp fff0000000000000 + fff0000000000000 AND fff0000000000000 + c0d0650f5a07b353 => fff0000000000000 fff0000000000000
+#1: xvadddp 41232585a9900000 + 41382511a2000000 AND fff0000000000000 + 0000000000000000 => 4140dbea3b640000 fff0000000000000
+#2: xvadddp fff0000000000000 + 0123214569900000 AND fff0000000000000 + 7ff0000000000000 => fff0000000000000 7ff8000000000000
+#3: xvadddp fff0000000000000 + 7ff7ffffffffffff AND fff0000000000000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#4: xvadddp c0d0650f5a07b353 + fff0000000000000 AND c0d0650f5a07b353 + c0d0650f5a07b353 => fff0000000000000 c0e0650f5a07b353
+#5: xvadddp c0d0650f5a07b353 + 8000000000000000 AND c0d0650f5a07b353 + 0000000000000000 => c0d0650f5a07b353 c0d0650f5a07b353
+#6: xvadddp c0d0650f5a07b353 + 0123214569900000 AND c0d0650f5a07b353 + 7ff0000000000000 => c0d0650f5a07b353 7ff0000000000000
+#7: xvadddp c0d0650f5a07b353 + 7ff7ffffffffffff AND c0d0650f5a07b353 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#8: xvadddp 8000000000000000 + fff0000000000000 AND 8000000000000000 + c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#9: xvadddp 8000000000000000 + 8000000000000000 AND 8000000000000000 + 0000000000000000 => 8000000000000000 0000000000000000
+#10: xvadddp 8000000000000000 + 0123214569900000 AND 8000000000000000 + 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#11: xvadddp 8000000000000000 + 7ff7ffffffffffff AND 8000000000000000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#12: xvadddp 0000000000000000 + fff0000000000000 AND 0000000000000000 + c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#13: xvadddp 0000000000000000 + 8000000000000000 AND 0000000000000000 + 0000000000000000 => 0000000000000000 0000000000000000
+#14: xvadddp 0000000000000000 + 0123214569900000 AND 0000000000000000 + 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#15: xvadddp 0000000000000000 + 7ff7ffffffffffff AND 0000000000000000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#16: xvadddp 0123214569900000 + fff0000000000000 AND 0123214569900000 + c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#17: xvadddp 0123214569900000 + 8000000000000000 AND 0123214569900000 + 0000000000000000 => 0123214569900000 0123214569900000
+#18: xvadddp 0123214569900000 + 404f000000000000 AND 0123214569900000 + 7ff0000000000000 => 404f000000000000 7ff0000000000000
+#19: xvadddp 0123214569900000 + 7ff7ffffffffffff AND 0123214569900000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#20: xvadddp 7ff0000000000000 + fff0000000000000 AND 7ff0000000000000 + c0d0650f5a07b353 => 7ff8000000000000 7ff0000000000000
+#21: xvadddp 7ff0000000000000 + 8000000000000000 AND 7ff0000000000000 + 0000000000000000 => 7ff0000000000000 7ff0000000000000
+#22: xvadddp 7ff0000000000000 + 0123214569900000 AND 7ff0000000000000 + 7ff0000000000000 => 7ff0000000000000 7ff0000000000000
+#23: xvadddp 7ff0000000000000 + 7ff7ffffffffffff AND 7ff0000000000000 + 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#24: xvadddp fff7ffffffffffff + fff0000000000000 AND fff7ffffffffffff + c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvadddp fff8000000000000 + 8000000000000000 AND fff8000000000000 + 0000000000000000 => fff8000000000000 fff8000000000000
+#26: xvadddp fff7ffffffffffff + 0123214569900000 AND fff7ffffffffffff + 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvadddp fff7ffffffffffff + 7ff7ffffffffffff AND fff7ffffffffffff + 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvadddp fff8000000000000 + fff0000000000000 AND fff8000000000000 + c0d0650f5a07b353 => fff8000000000000 fff8000000000000
+#29: xvadddp fff8000000000000 + 8000000000000000 AND 41232585a9900000 + 41382511a2000000 => fff8000000000000 4140dbea3b640000
+#30: xvadddp 41232585a9900000 + 41382511a2000000 AND 7ff7ffffffffffff + 7ff8000000000000 => 4140dbea3b640000 7fffffffffffffff
+#31: xvadddp 7ff8000000000000 + 7ff8000000000000 AND 7ff8000000000000 + fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvaddsp ff800000 + ff800000 AND ff800000 + c683287b AND 49192c2d + 49c1288d AND ff800000 + 00000000 => ff800000 ff800000 4a06df52 ff800000
+#1: xvaddsp ff800000 + 00000000 AND ff800000 + 7f800000 AND ff800000 + 7fffffff AND ff800000 + 7fc00000 => ff800000 7fc00000 7fffffff 7fc00000
+#2: xvaddsp c683287b + ff800000 AND c683287b + c683287b AND c683287b + 80000000 AND c683287b + 00000000 => ff800000 c703287b c683287b c683287b
+#3: xvaddsp c683287b + 00000000 AND c683287b + 7f800000 AND c683287b + 7fffffff AND c683287b + 7fc00000 => c683287b 7f800000 7fffffff 7fc00000
+#4: xvaddsp 80000000 + ff800000 AND 80000000 + c683287b AND 80000000 + 80000000 AND 80000000 + 00000000 => ff800000 c683287b 80000000 00000000
+#5: xvaddsp 80000000 + 00000000 AND 80000000 + 7f800000 AND 80000000 + 7fffffff AND 80000000 + 7fc00000 => 00000000 7f800000 7fffffff 7fc00000
+#6: xvaddsp 00000000 + ff800000 AND 00000000 + c683287b AND 00000000 + 80000000 AND 00000000 + 00000000 => ff800000 c683287b 00000000 00000000
+#7: xvaddsp 00000000 + 00000000 AND 00000000 + 7f800000 AND 00000000 + 7fffffff AND 00000000 + 7fc00000 => 00000000 7f800000 7fffffff 7fc00000
+#8: xvaddsp 00000000 + ff800000 AND 00000000 + c683287b AND 00000000 + 80000000 AND 00000000 + 00000000 => ff800000 c683287b 00000000 00000000
+#9: xvaddsp 00000000 + 42780000 AND 00000000 + 7f800000 AND 00000000 + 7fffffff AND 00000000 + 7fc00000 => 42780000 7f800000 7fffffff 7fc00000
+#10: xvaddsp 7f800000 + ff800000 AND 7f800000 + c683287b AND 7f800000 + 80000000 AND 7f800000 + 00000000 => 7fc00000 7f800000 7f800000 7f800000
+#11: xvaddsp 7f800000 + 00000000 AND 7f800000 + 7f800000 AND 7f800000 + 7fffffff AND 7f800000 + 7fc00000 => 7f800000 7f800000 7fffffff 7fc00000
+#12: xvaddsp ffffffff + ff800000 AND ffffffff + c683287b AND ffc00000 + 80000000 AND ffc00000 + 00000000 => ffffffff ffffffff ffc00000 ffc00000
+#13: xvaddsp ffffffff + 00000000 AND ffffffff + 7f800000 AND ffffffff + 7fffffff AND ffffffff + 7fc00000 => ffffffff ffffffff ffffffff ffffffff
+#14: xvaddsp ffc00000 + ff800000 AND ffc00000 + c683287b AND ffc00000 + 80000000 AND 49192c2d + 49c1288d => ffc00000 ffc00000 ffc00000 4a06df52
+#15: xvaddsp 49192c2d + 49c1288d AND 7fffffff + 7fc00000 AND 7fc00000 + 7fc00000 AND 7fc00000 + ffc00000 => 4a06df52 7fffffff 7fc00000 7fc00000
+
+
+#0: xvdivdp fff0000000000000 / fff0000000000000 AND fff0000000000000 / c0d0650f5a07b353 => 7ff8000000000000 7ff0000000000000
+#1: xvdivdp 41232585a9900000 / 41382511a2000000 AND fff0000000000000 / 0000000000000000 => 3fd9602b4fe7a892 fff0000000000000
+#2: xvdivdp fff0000000000000 / 0123214569900000 AND fff0000000000000 / 7ff0000000000000 => fff0000000000000 7ff8000000000000
+#3: xvdivdp fff0000000000000 / 7ff7ffffffffffff AND fff0000000000000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#4: xvdivdp c0d0650f5a07b353 / fff0000000000000 AND c0d0650f5a07b353 / c0d0650f5a07b353 => 0000000000000000 3ff0000000000000
+#5: xvdivdp c0d0650f5a07b353 / 8000000000000000 AND c0d0650f5a07b353 / 0000000000000000 => 7ff0000000000000 fff0000000000000
+#6: xvdivdp c0d0650f5a07b353 / 0123214569900000 AND c0d0650f5a07b353 / 7ff0000000000000 => ff9b6cb57ca13c00 8000000000000000
+#7: xvdivdp c0d0650f5a07b353 / 7ff7ffffffffffff AND c0d0650f5a07b353 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#8: xvdivdp 8000000000000000 / fff0000000000000 AND 8000000000000000 / c0d0650f5a07b353 => 0000000000000000 0000000000000000
+#9: xvdivdp 8000000000000000 / 8000000000000000 AND 8000000000000000 / 0000000000000000 => 7ff8000000000000 7ff8000000000000
+#10: xvdivdp 8000000000000000 / 0123214569900000 AND 8000000000000000 / 7ff0000000000000 => 8000000000000000 8000000000000000
+#11: xvdivdp 8000000000000000 / 7ff7ffffffffffff AND 8000000000000000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#12: xvdivdp 0000000000000000 / fff0000000000000 AND 0000000000000000 / c0d0650f5a07b353 => 8000000000000000 8000000000000000
+#13: xvdivdp 0000000000000000 / 8000000000000000 AND 0000000000000000 / 0000000000000000 => 7ff8000000000000 7ff8000000000000
+#14: xvdivdp 0000000000000000 / 0123214569900000 AND 0000000000000000 / 7ff0000000000000 => 0000000000000000 0000000000000000
+#15: xvdivdp 0000000000000000 / 7ff7ffffffffffff AND 0000000000000000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#16: xvdivdp 0123214569900000 / fff0000000000000 AND 0123214569900000 / c0d0650f5a07b353 => 8000000000000000 8042ab59d8b6ec87
+#17: xvdivdp 0123214569900000 / 8000000000000000 AND 0123214569900000 / 0000000000000000 => fff0000000000000 7ff0000000000000
+#18: xvdivdp 0123214569900000 / 404f000000000000 AND 0123214569900000 / 7ff0000000000000 => 00c3bf3f64b5ad6b 0000000000000000
+#19: xvdivdp 0123214569900000 / 7ff7ffffffffffff AND 0123214569900000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#20: xvdivdp 7ff0000000000000 / fff0000000000000 AND 7ff0000000000000 / c0d0650f5a07b353 => 7ff8000000000000 fff0000000000000
+#21: xvdivdp 7ff0000000000000 / 8000000000000000 AND 7ff0000000000000 / 0000000000000000 => fff0000000000000 7ff0000000000000
+#22: xvdivdp 7ff0000000000000 / 0123214569900000 AND 7ff0000000000000 / 7ff0000000000000 => 7ff0000000000000 7ff8000000000000
+#23: xvdivdp 7ff0000000000000 / 7ff7ffffffffffff AND 7ff0000000000000 / 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#24: xvdivdp fff7ffffffffffff / fff0000000000000 AND fff7ffffffffffff / c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvdivdp fff8000000000000 / 8000000000000000 AND fff8000000000000 / 0000000000000000 => fff8000000000000 fff8000000000000
+#26: xvdivdp fff7ffffffffffff / 0123214569900000 AND fff7ffffffffffff / 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvdivdp fff7ffffffffffff / 7ff7ffffffffffff AND fff7ffffffffffff / 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvdivdp fff8000000000000 / fff0000000000000 AND fff8000000000000 / c0d0650f5a07b353 => fff8000000000000 fff8000000000000
+#29: xvdivdp fff8000000000000 / 8000000000000000 AND 41232585a9900000 / 41382511a2000000 => fff8000000000000 3fd9602b4fe7a892
+#30: xvdivdp 41232585a9900000 / 41382511a2000000 AND 7ff7ffffffffffff / 7ff8000000000000 => 3fd9602b4fe7a892 7fffffffffffffff
+#31: xvdivdp 7ff8000000000000 / 7ff8000000000000 AND 7ff8000000000000 / fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvdivsp ff800000 / ff800000 AND ff800000 / c683287b AND 49192c2d / 49c1288d AND ff800000 / 00000000 => 7fc00000 7f800000 3ecb015a ff800000
+#1: xvdivsp ff800000 / 00000000 AND ff800000 / 7f800000 AND ff800000 / 7fffffff AND ff800000 / 7fc00000 => ff800000 7fc00000 7fffffff 7fc00000
+#2: xvdivsp c683287b / ff800000 AND c683287b / c683287b AND c683287b / 80000000 AND c683287b / 00000000 => 00000000 3f800000 7f800000 ff800000
+#3: xvdivsp c683287b / 00000000 AND c683287b / 7f800000 AND c683287b / 7fffffff AND c683287b / 7fc00000 => ff800000 80000000 7fffffff 7fc00000
+#4: xvdivsp 80000000 / ff800000 AND 80000000 / c683287b AND 80000000 / 80000000 AND 80000000 / 00000000 => 00000000 00000000 7fc00000 7fc00000
+#5: xvdivsp 80000000 / 00000000 AND 80000000 / 7f800000 AND 80000000 / 7fffffff AND 80000000 / 7fc00000 => 7fc00000 80000000 7fffffff 7fc00000
+#6: xvdivsp 00000000 / ff800000 AND 00000000 / c683287b AND 00000000 / 80000000 AND 00000000 / 00000000 => 80000000 80000000 7fc00000 7fc00000
+#7: xvdivsp 00000000 / 00000000 AND 00000000 / 7f800000 AND 00000000 / 7fffffff AND 00000000 / 7fc00000 => 7fc00000 00000000 7fffffff 7fc00000
+#8: xvdivsp 00000000 / ff800000 AND 00000000 / c683287b AND 00000000 / 80000000 AND 00000000 / 00000000 => 80000000 80000000 7fc00000 7fc00000
+#9: xvdivsp 00000000 / 42780000 AND 00000000 / 7f800000 AND 00000000 / 7fffffff AND 00000000 / 7fc00000 => 00000000 00000000 7fffffff 7fc00000
+#10: xvdivsp 7f800000 / ff800000 AND 7f800000 / c683287b AND 7f800000 / 80000000 AND 7f800000 / 00000000 => 7fc00000 ff800000 ff800000 7f800000
+#11: xvdivsp 7f800000 / 00000000 AND 7f800000 / 7f800000 AND 7f800000 / 7fffffff AND 7f800000 / 7fc00000 => 7f800000 7fc00000 7fffffff 7fc00000
+#12: xvdivsp ffffffff / ff800000 AND ffffffff / c683287b AND ffc00000 / 80000000 AND ffc00000 / 00000000 => ffffffff ffffffff ffc00000 ffc00000
+#13: xvdivsp ffffffff / 00000000 AND ffffffff / 7f800000 AND ffffffff / 7fffffff AND ffffffff / 7fc00000 => ffffffff ffffffff ffffffff ffffffff
+#14: xvdivsp ffc00000 / ff800000 AND ffc00000 / c683287b AND ffc00000 / 80000000 AND 49192c2d / 49c1288d => ffc00000 ffc00000 ffc00000 3ecb015a
+#15: xvdivsp 49192c2d / 49c1288d AND 7fffffff / 7fc00000 AND 7fc00000 / 7fc00000 AND 7fc00000 / ffc00000 => 3ecb015a 7fffffff 7fc00000 7fc00000
+
+
+#0: xvmuldp fff0000000000000 * fff0000000000000 AND fff0000000000000 * c0d0650f5a07b353 => 7ff0000000000000 7ff0000000000000
+#1: xvmuldp 41232585a9900000 * 41382511a2000000 AND fff0000000000000 * 0000000000000000 => 426ce4a45d2a0a7e 7ff8000000000000
+#2: xvmuldp fff0000000000000 * 0123214569900000 AND fff0000000000000 * 7ff0000000000000 => fff0000000000000 fff0000000000000
+#3: xvmuldp fff0000000000000 * 7ff7ffffffffffff AND fff0000000000000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#4: xvmuldp c0d0650f5a07b353 * fff0000000000000 AND c0d0650f5a07b353 * c0d0650f5a07b353 => 7ff0000000000000 41b0cc9d05eec2a7
+#5: xvmuldp c0d0650f5a07b353 * 8000000000000000 AND c0d0650f5a07b353 * 0000000000000000 => 0000000000000000 8000000000000000
+#6: xvmuldp c0d0650f5a07b353 * 0123214569900000 AND c0d0650f5a07b353 * 7ff0000000000000 => 82039a19ca8fcb5f fff0000000000000
+#7: xvmuldp c0d0650f5a07b353 * 7ff7ffffffffffff AND c0d0650f5a07b353 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#8: xvmuldp 8000000000000000 * fff0000000000000 AND 8000000000000000 * c0d0650f5a07b353 => 7ff8000000000000 0000000000000000
+#9: xvmuldp 8000000000000000 * 8000000000000000 AND 8000000000000000 * 0000000000000000 => 0000000000000000 8000000000000000
+#10: xvmuldp 8000000000000000 * 0123214569900000 AND 8000000000000000 * 7ff0000000000000 => 8000000000000000 7ff8000000000000
+#11: xvmuldp 8000000000000000 * 7ff7ffffffffffff AND 8000000000000000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#12: xvmuldp 0000000000000000 * fff0000000000000 AND 0000000000000000 * c0d0650f5a07b353 => 7ff8000000000000 8000000000000000
+#13: xvmuldp 0000000000000000 * 8000000000000000 AND 0000000000000000 * 0000000000000000 => 8000000000000000 0000000000000000
+#14: xvmuldp 0000000000000000 * 0123214569900000 AND 0000000000000000 * 7ff0000000000000 => 0000000000000000 7ff8000000000000
+#15: xvmuldp 0000000000000000 * 7ff7ffffffffffff AND 0000000000000000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#16: xvmuldp 0123214569900000 * fff0000000000000 AND 0123214569900000 * c0d0650f5a07b353 => fff0000000000000 82039a19ca8fcb5f
+#17: xvmuldp 0123214569900000 * 8000000000000000 AND 0123214569900000 * 0000000000000000 => 8000000000000000 0000000000000000
+#18: xvmuldp 0123214569900000 * 404f000000000000 AND 0123214569900000 * 7ff0000000000000 => 0182883b3e438000 7ff0000000000000
+#19: xvmuldp 0123214569900000 * 7ff7ffffffffffff AND 0123214569900000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#20: xvmuldp 7ff0000000000000 * fff0000000000000 AND 7ff0000000000000 * c0d0650f5a07b353 => fff0000000000000 fff0000000000000
+#21: xvmuldp 7ff0000000000000 * 8000000000000000 AND 7ff0000000000000 * 0000000000000000 => 7ff8000000000000 7ff8000000000000
+#22: xvmuldp 7ff0000000000000 * 0123214569900000 AND 7ff0000000000000 * 7ff0000000000000 => 7ff0000000000000 7ff0000000000000
+#23: xvmuldp 7ff0000000000000 * 7ff7ffffffffffff AND 7ff0000000000000 * 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#24: xvmuldp fff7ffffffffffff * fff0000000000000 AND fff7ffffffffffff * c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvmuldp fff8000000000000 * 8000000000000000 AND fff8000000000000 * 0000000000000000 => fff8000000000000 fff8000000000000
+#26: xvmuldp fff7ffffffffffff * 0123214569900000 AND fff7ffffffffffff * 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvmuldp fff7ffffffffffff * 7ff7ffffffffffff AND fff7ffffffffffff * 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvmuldp fff8000000000000 * fff0000000000000 AND fff8000000000000 * c0d0650f5a07b353 => fff8000000000000 fff8000000000000
+#29: xvmuldp fff8000000000000 * 8000000000000000 AND 41232585a9900000 * 41382511a2000000 => fff8000000000000 426ce4a45d2a0a7e
+#30: xvmuldp 41232585a9900000 * 41382511a2000000 AND 7ff7ffffffffffff * 7ff8000000000000 => 426ce4a45d2a0a7e 7fffffffffffffff
+#31: xvmuldp 7ff8000000000000 * 7ff8000000000000 AND 7ff8000000000000 * fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvmulsp ff800000 * ff800000 AND ff800000 * c683287b AND 49192c2d * 49c1288d AND ff800000 * 00000000 => 7f800000 7f800000 53672522 7fc00000
+#1: xvmulsp ff800000 * 00000000 AND ff800000 * 7f800000 AND ff800000 * 7fffffff AND ff800000 * 7fc00000 => 7fc00000 ff800000 7fffffff 7fc00000
+#2: xvmulsp c683287b * ff800000 AND c683287b * c683287b AND c683287b * 80000000 AND c683287b * 00000000 => 7f800000 4d8664e9 00000000 80000000
+#3: xvmulsp c683287b * 00000000 AND c683287b * 7f800000 AND c683287b * 7fffffff AND c683287b * 7fc00000 => 80000000 ff800000 7fffffff 7fc00000
+#4: xvmulsp 80000000 * ff800000 AND 80000000 * c683287b AND 80000000 * 80000000 AND 80000000 * 00000000 => 7fc00000 00000000 00000000 80000000
+#5: xvmulsp 80000000 * 00000000 AND 80000000 * 7f800000 AND 80000000 * 7fffffff AND 80000000 * 7fc00000 => 80000000 7fc00000 7fffffff 7fc00000
+#6: xvmulsp 00000000 * ff800000 AND 00000000 * c683287b AND 00000000 * 80000000 AND 00000000 * 00000000 => 7fc00000 80000000 80000000 00000000
+#7: xvmulsp 00000000 * 00000000 AND 00000000 * 7f800000 AND 00000000 * 7fffffff AND 00000000 * 7fc00000 => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmulsp 00000000 * ff800000 AND 00000000 * c683287b AND 00000000 * 80000000 AND 00000000 * 00000000 => 7fc00000 80000000 80000000 00000000
+#9: xvmulsp 00000000 * 42780000 AND 00000000 * 7f800000 AND 00000000 * 7fffffff AND 00000000 * 7fc00000 => 00000000 7fc00000 7fffffff 7fc00000
+#10: xvmulsp 7f800000 * ff800000 AND 7f800000 * c683287b AND 7f800000 * 80000000 AND 7f800000 * 00000000 => ff800000 ff800000 7fc00000 7fc00000
+#11: xvmulsp 7f800000 * 00000000 AND 7f800000 * 7f800000 AND 7f800000 * 7fffffff AND 7f800000 * 7fc00000 => 7fc00000 7f800000 7fffffff 7fc00000
+#12: xvmulsp ffffffff * ff800000 AND ffffffff * c683287b AND ffc00000 * 80000000 AND ffc00000 * 00000000 => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmulsp ffffffff * 00000000 AND ffffffff * 7f800000 AND ffffffff * 7fffffff AND ffffffff * 7fc00000 => ffffffff ffffffff ffffffff ffffffff
+#14: xvmulsp ffc00000 * ff800000 AND ffc00000 * c683287b AND ffc00000 * 80000000 AND 49192c2d * 49c1288d => ffc00000 ffc00000 ffc00000 53672522
+#15: xvmulsp 49192c2d * 49c1288d AND 7fffffff * 7fc00000 AND 7fc00000 * 7fc00000 AND 7fc00000 * ffc00000 => 53672522 7fffffff 7fc00000 7fc00000
+
+
+#0: xvsubdp fff0000000000000 - fff0000000000000 AND fff0000000000000 - c0d0650f5a07b353 => 7ff8000000000000 fff0000000000000
+#1: xvsubdp 41232585a9900000 - 41382511a2000000 AND fff0000000000000 - 0000000000000000 => c12d249d9a700000 fff0000000000000
+#2: xvsubdp fff0000000000000 - 0123214569900000 AND fff0000000000000 - 7ff0000000000000 => fff0000000000000 fff0000000000000
+#3: xvsubdp fff0000000000000 - 7ff7ffffffffffff AND fff0000000000000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#4: xvsubdp c0d0650f5a07b353 - fff0000000000000 AND c0d0650f5a07b353 - c0d0650f5a07b353 => 7ff0000000000000 0000000000000000
+#5: xvsubdp c0d0650f5a07b353 - 8000000000000000 AND c0d0650f5a07b353 - 0000000000000000 => c0d0650f5a07b353 c0d0650f5a07b353
+#6: xvsubdp c0d0650f5a07b353 - 0123214569900000 AND c0d0650f5a07b353 - 7ff0000000000000 => c0d0650f5a07b353 fff0000000000000
+#7: xvsubdp c0d0650f5a07b353 - 7ff7ffffffffffff AND c0d0650f5a07b353 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#8: xvsubdp 8000000000000000 - fff0000000000000 AND 8000000000000000 - c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#9: xvsubdp 8000000000000000 - 8000000000000000 AND 8000000000000000 - 0000000000000000 => 0000000000000000 8000000000000000
+#10: xvsubdp 8000000000000000 - 0123214569900000 AND 8000000000000000 - 7ff0000000000000 => 8123214569900000 fff0000000000000
+#11: xvsubdp 8000000000000000 - 7ff7ffffffffffff AND 8000000000000000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#12: xvsubdp 0000000000000000 - fff0000000000000 AND 0000000000000000 - c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#13: xvsubdp 0000000000000000 - 8000000000000000 AND 0000000000000000 - 0000000000000000 => 0000000000000000 0000000000000000
+#14: xvsubdp 0000000000000000 - 0123214569900000 AND 0000000000000000 - 7ff0000000000000 => 8123214569900000 fff0000000000000
+#15: xvsubdp 0000000000000000 - 7ff7ffffffffffff AND 0000000000000000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#16: xvsubdp 0123214569900000 - fff0000000000000 AND 0123214569900000 - c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#17: xvsubdp 0123214569900000 - 8000000000000000 AND 0123214569900000 - 0000000000000000 => 0123214569900000 0123214569900000
+#18: xvsubdp 0123214569900000 - 404f000000000000 AND 0123214569900000 - 7ff0000000000000 => c04f000000000000 fff0000000000000
+#19: xvsubdp 0123214569900000 - 7ff7ffffffffffff AND 0123214569900000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#20: xvsubdp 7ff0000000000000 - fff0000000000000 AND 7ff0000000000000 - c0d0650f5a07b353 => 7ff0000000000000 7ff0000000000000
+#21: xvsubdp 7ff0000000000000 - 8000000000000000 AND 7ff0000000000000 - 0000000000000000 => 7ff0000000000000 7ff0000000000000
+#22: xvsubdp 7ff0000000000000 - 0123214569900000 AND 7ff0000000000000 - 7ff0000000000000 => 7ff0000000000000 7ff8000000000000
+#23: xvsubdp 7ff0000000000000 - 7ff7ffffffffffff AND 7ff0000000000000 - 7ff8000000000000 => 7fffffffffffffff 7ff8000000000000
+#24: xvsubdp fff7ffffffffffff - fff0000000000000 AND fff7ffffffffffff - c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvsubdp fff8000000000000 - 8000000000000000 AND fff8000000000000 - 0000000000000000 => fff8000000000000 fff8000000000000
+#26: xvsubdp fff7ffffffffffff - 0123214569900000 AND fff7ffffffffffff - 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvsubdp fff7ffffffffffff - 7ff7ffffffffffff AND fff7ffffffffffff - 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvsubdp fff8000000000000 - fff0000000000000 AND fff8000000000000 - c0d0650f5a07b353 => fff8000000000000 fff8000000000000
+#29: xvsubdp fff8000000000000 - 8000000000000000 AND 41232585a9900000 - 41382511a2000000 => fff8000000000000 c12d249d9a700000
+#30: xvsubdp 41232585a9900000 - 41382511a2000000 AND 7ff7ffffffffffff - 7ff8000000000000 => c12d249d9a700000 7fffffffffffffff
+#31: xvsubdp 7ff8000000000000 - 7ff8000000000000 AND 7ff8000000000000 - fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvsubsp ff800000 - ff800000 AND ff800000 - c683287b AND 49192c2d - 49c1288d AND ff800000 - 00000000 => 7fc00000 ff800000 c96924ed ff800000
+#1: xvsubsp ff800000 - 00000000 AND ff800000 - 7f800000 AND ff800000 - 7fffffff AND ff800000 - 7fc00000 => ff800000 ff800000 7fffffff 7fc00000
+#2: xvsubsp c683287b - ff800000 AND c683287b - c683287b AND c683287b - 80000000 AND c683287b - 00000000 => 7f800000 00000000 c683287b c683287b
+#3: xvsubsp c683287b - 00000000 AND c683287b - 7f800000 AND c683287b - 7fffffff AND c683287b - 7fc00000 => c683287b ff800000 7fffffff 7fc00000
+#4: xvsubsp 80000000 - ff800000 AND 80000000 - c683287b AND 80000000 - 80000000 AND 80000000 - 00000000 => 7f800000 4683287b 00000000 80000000
+#5: xvsubsp 80000000 - 00000000 AND 80000000 - 7f800000 AND 80000000 - 7fffffff AND 80000000 - 7fc00000 => 80000000 ff800000 7fffffff 7fc00000
+#6: xvsubsp 00000000 - ff800000 AND 00000000 - c683287b AND 00000000 - 80000000 AND 00000000 - 00000000 => 7f800000 4683287b 00000000 00000000
+#7: xvsubsp 00000000 - 00000000 AND 00000000 - 7f800000 AND 00000000 - 7fffffff AND 00000000 - 7fc00000 => 00000000 ff800000 7fffffff 7fc00000
+#8: xvsubsp 00000000 - ff800000 AND 00000000 - c683287b AND 00000000 - 80000000 AND 00000000 - 00000000 => 7f800000 4683287b 00000000 00000000
+#9: xvsubsp 00000000 - 42780000 AND 00000000 - 7f800000 AND 00000000 - 7fffffff AND 00000000 - 7fc00000 => c2780000 ff800000 7fffffff 7fc00000
+#10: xvsubsp 7f800000 - ff800000 AND 7f800000 - c683287b AND 7f800000 - 80000000 AND 7f800000 - 00000000 => 7f800000 7f800000 7f800000 7f800000
+#11: xvsubsp 7f800000 - 00000000 AND 7f800000 - 7f800000 AND 7f800000 - 7fffffff AND 7f800000 - 7fc00000 => 7f800000 7fc00000 7fffffff 7fc00000
+#12: xvsubsp ffffffff - ff800000 AND ffffffff - c683287b AND ffc00000 - 80000000 AND ffc00000 - 00000000 => ffffffff ffffffff ffc00000 ffc00000
+#13: xvsubsp ffffffff - 00000000 AND ffffffff - 7f800000 AND ffffffff - 7fffffff AND ffffffff - 7fc00000 => ffffffff ffffffff ffffffff ffffffff
+#14: xvsubsp ffc00000 - ff800000 AND ffc00000 - c683287b AND ffc00000 - 80000000 AND 49192c2d - 49c1288d => ffc00000 ffc00000 ffc00000 c96924ed
+#15: xvsubsp 49192c2d - 49c1288d AND 7fffffff - 7fc00000 AND 7fc00000 - 7fc00000 AND 7fc00000 - ffc00000 => c96924ed 7fffffff 7fc00000 7fc00000
+
+
+#0: xvmaxdp fff0000000000000 @max@ fff0000000000000 AND fff0000000000000 @max@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#1: xvmaxdp 41232585a9900000 @max@ 41382511a2000000 AND fff0000000000000 @max@ 0000000000000000 => 41382511a2000000 0000000000000000
+#2: xvmaxdp fff0000000000000 @max@ 0123214569900000 AND fff0000000000000 @max@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#3: xvmaxdp fff0000000000000 @max@ 7ff7ffffffffffff AND fff0000000000000 @max@ 7ff8000000000000 => 7fffffffffffffff fff0000000000000
+#4: xvmaxdp c0d0650f5a07b353 @max@ fff0000000000000 AND c0d0650f5a07b353 @max@ c0d0650f5a07b353 => c0d0650f5a07b353 c0d0650f5a07b353
+#5: xvmaxdp c0d0650f5a07b353 @max@ 8000000000000000 AND c0d0650f5a07b353 @max@ 0000000000000000 => 8000000000000000 0000000000000000
+#6: xvmaxdp c0d0650f5a07b353 @max@ 0123214569900000 AND c0d0650f5a07b353 @max@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#7: xvmaxdp c0d0650f5a07b353 @max@ 7ff7ffffffffffff AND c0d0650f5a07b353 @max@ 7ff8000000000000 => 7fffffffffffffff c0d0650f5a07b353
+#8: xvmaxdp 8000000000000000 @max@ fff0000000000000 AND 8000000000000000 @max@ c0d0650f5a07b353 => 8000000000000000 8000000000000000
+#9: xvmaxdp 8000000000000000 @max@ 8000000000000000 AND 8000000000000000 @max@ 0000000000000000 => 8000000000000000 0000000000000000
+#10: xvmaxdp 8000000000000000 @max@ 0123214569900000 AND 8000000000000000 @max@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#11: xvmaxdp 8000000000000000 @max@ 7ff7ffffffffffff AND 8000000000000000 @max@ 7ff8000000000000 => 7fffffffffffffff 8000000000000000
+#12: xvmaxdp 0000000000000000 @max@ fff0000000000000 AND 0000000000000000 @max@ c0d0650f5a07b353 => 0000000000000000 0000000000000000
+#13: xvmaxdp 0000000000000000 @max@ 8000000000000000 AND 0000000000000000 @max@ 0000000000000000 => 0000000000000000 0000000000000000
+#14: xvmaxdp 0000000000000000 @max@ 0123214569900000 AND 0000000000000000 @max@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#15: xvmaxdp 0000000000000000 @max@ 7ff7ffffffffffff AND 0000000000000000 @max@ 7ff8000000000000 => 7fffffffffffffff 0000000000000000
+#16: xvmaxdp 0123214569900000 @max@ fff0000000000000 AND 0123214569900000 @max@ c0d0650f5a07b353 => 0123214569900000 0123214569900000
+#17: xvmaxdp 0123214569900000 @max@ 8000000000000000 AND 0123214569900000 @max@ 0000000000000000 => 0123214569900000 0123214569900000
+#18: xvmaxdp 0123214569900000 @max@ 404f000000000000 AND 0123214569900000 @max@ 7ff0000000000000 => 404f000000000000 7ff0000000000000
+#19: xvmaxdp 0123214569900000 @max@ 7ff7ffffffffffff AND 0123214569900000 @max@ 7ff8000000000000 => 7fffffffffffffff 0123214569900000
+#20: xvmaxdp 7ff0000000000000 @max@ fff0000000000000 AND 7ff0000000000000 @max@ c0d0650f5a07b353 => 7ff0000000000000 7ff0000000000000
+#21: xvmaxdp 7ff0000000000000 @max@ 8000000000000000 AND 7ff0000000000000 @max@ 0000000000000000 => 7ff0000000000000 7ff0000000000000
+#22: xvmaxdp 7ff0000000000000 @max@ 0123214569900000 AND 7ff0000000000000 @max@ 7ff0000000000000 => 7ff0000000000000 7ff0000000000000
+#23: xvmaxdp 7ff0000000000000 @max@ 7ff7ffffffffffff AND 7ff0000000000000 @max@ 7ff8000000000000 => 7fffffffffffffff 7ff0000000000000
+#24: xvmaxdp fff7ffffffffffff @max@ fff0000000000000 AND fff7ffffffffffff @max@ c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvmaxdp fff8000000000000 @max@ 8000000000000000 AND fff8000000000000 @max@ 0000000000000000 => 8000000000000000 0000000000000000
+#26: xvmaxdp fff7ffffffffffff @max@ 0123214569900000 AND fff7ffffffffffff @max@ 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvmaxdp fff7ffffffffffff @max@ 7ff7ffffffffffff AND fff7ffffffffffff @max@ 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvmaxdp fff8000000000000 @max@ fff0000000000000 AND fff8000000000000 @max@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#29: xvmaxdp fff8000000000000 @max@ 8000000000000000 AND 41232585a9900000 @max@ 41382511a2000000 => 8000000000000000 41382511a2000000
+#30: xvmaxdp 41232585a9900000 @max@ 41382511a2000000 AND 7ff7ffffffffffff @max@ 7ff8000000000000 => 41382511a2000000 7fffffffffffffff
+#31: xvmaxdp 7ff8000000000000 @max@ 7ff8000000000000 AND 7ff8000000000000 @max@ fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvmindp fff0000000000000 @min@ fff0000000000000 AND fff0000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 fff0000000000000
+#1: xvmindp 41232585a9900000 @min@ 41382511a2000000 AND fff0000000000000 @min@ 0000000000000000 => 41232585a9900000 fff0000000000000
+#2: xvmindp fff0000000000000 @min@ 0123214569900000 AND fff0000000000000 @min@ 7ff0000000000000 => fff0000000000000 fff0000000000000
+#3: xvmindp fff0000000000000 @min@ 7ff7ffffffffffff AND fff0000000000000 @min@ 7ff8000000000000 => 7fffffffffffffff fff0000000000000
+#4: xvmindp c0d0650f5a07b353 @min@ fff0000000000000 AND c0d0650f5a07b353 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#5: xvmindp c0d0650f5a07b353 @min@ 8000000000000000 AND c0d0650f5a07b353 @min@ 0000000000000000 => c0d0650f5a07b353 c0d0650f5a07b353
+#6: xvmindp c0d0650f5a07b353 @min@ 0123214569900000 AND c0d0650f5a07b353 @min@ 7ff0000000000000 => c0d0650f5a07b353 c0d0650f5a07b353
+#7: xvmindp c0d0650f5a07b353 @min@ 7ff7ffffffffffff AND c0d0650f5a07b353 @min@ 7ff8000000000000 => 7fffffffffffffff c0d0650f5a07b353
+#8: xvmindp 8000000000000000 @min@ fff0000000000000 AND 8000000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#9: xvmindp 8000000000000000 @min@ 8000000000000000 AND 8000000000000000 @min@ 0000000000000000 => 8000000000000000 8000000000000000
+#10: xvmindp 8000000000000000 @min@ 0123214569900000 AND 8000000000000000 @min@ 7ff0000000000000 => 8000000000000000 8000000000000000
+#11: xvmindp 8000000000000000 @min@ 7ff7ffffffffffff AND 8000000000000000 @min@ 7ff8000000000000 => 7fffffffffffffff 8000000000000000
+#12: xvmindp 0000000000000000 @min@ fff0000000000000 AND 0000000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#13: xvmindp 0000000000000000 @min@ 8000000000000000 AND 0000000000000000 @min@ 0000000000000000 => 8000000000000000 0000000000000000
+#14: xvmindp 0000000000000000 @min@ 0123214569900000 AND 0000000000000000 @min@ 7ff0000000000000 => 0000000000000000 0000000000000000
+#15: xvmindp 0000000000000000 @min@ 7ff7ffffffffffff AND 0000000000000000 @min@ 7ff8000000000000 => 7fffffffffffffff 0000000000000000
+#16: xvmindp 0123214569900000 @min@ fff0000000000000 AND 0123214569900000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#17: xvmindp 0123214569900000 @min@ 8000000000000000 AND 0123214569900000 @min@ 0000000000000000 => 8000000000000000 0000000000000000
+#18: xvmindp 0123214569900000 @min@ 404f000000000000 AND 0123214569900000 @min@ 7ff0000000000000 => 0123214569900000 0123214569900000
+#19: xvmindp 0123214569900000 @min@ 7ff7ffffffffffff AND 0123214569900000 @min@ 7ff8000000000000 => 7fffffffffffffff 0123214569900000
+#20: xvmindp 7ff0000000000000 @min@ fff0000000000000 AND 7ff0000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#21: xvmindp 7ff0000000000000 @min@ 8000000000000000 AND 7ff0000000000000 @min@ 0000000000000000 => 8000000000000000 0000000000000000
+#22: xvmindp 7ff0000000000000 @min@ 0123214569900000 AND 7ff0000000000000 @min@ 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#23: xvmindp 7ff0000000000000 @min@ 7ff7ffffffffffff AND 7ff0000000000000 @min@ 7ff8000000000000 => 7fffffffffffffff 7ff0000000000000
+#24: xvmindp fff7ffffffffffff @min@ fff0000000000000 AND fff7ffffffffffff @min@ c0d0650f5a07b353 => ffffffffffffffff ffffffffffffffff
+#25: xvmindp fff8000000000000 @min@ 8000000000000000 AND fff8000000000000 @min@ 0000000000000000 => 8000000000000000 0000000000000000
+#26: xvmindp fff7ffffffffffff @min@ 0123214569900000 AND fff7ffffffffffff @min@ 7ff0000000000000 => ffffffffffffffff ffffffffffffffff
+#27: xvmindp fff7ffffffffffff @min@ 7ff7ffffffffffff AND fff7ffffffffffff @min@ 7ff8000000000000 => ffffffffffffffff ffffffffffffffff
+#28: xvmindp fff8000000000000 @min@ fff0000000000000 AND fff8000000000000 @min@ c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#29: xvmindp fff8000000000000 @min@ 8000000000000000 AND 41232585a9900000 @min@ 41382511a2000000 => 8000000000000000 41232585a9900000
+#30: xvmindp 41232585a9900000 @min@ 41382511a2000000 AND 7ff7ffffffffffff @min@ 7ff8000000000000 => 41232585a9900000 7fffffffffffffff
+#31: xvmindp 7ff8000000000000 @min@ 7ff8000000000000 AND 7ff8000000000000 @min@ fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvmaxsp ff800000 @max@ ff800000 AND ff800000 @max@ c683287b AND 49192c2d @max@ 49c1288d AND ff800000 @max@ 00000000 => ff800000 c683287b 49c1288d 00000000
+#1: xvmaxsp ff800000 @max@ 00000000 AND ff800000 @max@ 7f800000 AND ff800000 @max@ 7fffffff AND ff800000 @max@ 7fc00000 => 00000000 7f800000 ff800000 ff800000
+#2: xvmaxsp c683287b @max@ ff800000 AND c683287b @max@ c683287b AND c683287b @max@ 80000000 AND c683287b @max@ 00000000 => c683287b c683287b 80000000 00000000
+#3: xvmaxsp c683287b @max@ 00000000 AND c683287b @max@ 7f800000 AND c683287b @max@ 7fffffff AND c683287b @max@ 7fc00000 => 00000000 7f800000 c683287b c683287b
+#4: xvmaxsp 80000000 @max@ ff800000 AND 80000000 @max@ c683287b AND 80000000 @max@ 80000000 AND 80000000 @max@ 00000000 => 80000000 80000000 80000000 00000000
+#5: xvmaxsp 80000000 @max@ 00000000 AND 80000000 @max@ 7f800000 AND 80000000 @max@ 7fffffff AND 80000000 @max@ 7fc00000 => 00000000 7f800000 80000000 80000000
+#6: xvmaxsp 00000000 @max@ ff800000 AND 00000000 @max@ c683287b AND 00000000 @max@ 80000000 AND 00000000 @max@ 00000000 => 00000000 00000000 00000000 00000000
+#7: xvmaxsp 00000000 @max@ 00000000 AND 00000000 @max@ 7f800000 AND 00000000 @max@ 7fffffff AND 00000000 @max@ 7fc00000 => 00000000 7f800000 00000000 00000000
+#8: xvmaxsp 00000000 @max@ ff800000 AND 00000000 @max@ c683287b AND 00000000 @max@ 80000000 AND 00000000 @max@ 00000000 => 00000000 00000000 00000000 00000000
+#9: xvmaxsp 00000000 @max@ 42780000 AND 00000000 @max@ 7f800000 AND 00000000 @max@ 7fffffff AND 00000000 @max@ 7fc00000 => 42780000 7f800000 00000000 00000000
+#10: xvmaxsp 7f800000 @max@ ff800000 AND 7f800000 @max@ c683287b AND 7f800000 @max@ 80000000 AND 7f800000 @max@ 00000000 => 7f800000 7f800000 7f800000 7f800000
+#11: xvmaxsp 7f800000 @max@ 00000000 AND 7f800000 @max@ 7f800000 AND 7f800000 @max@ 7fffffff AND 7f800000 @max@ 7fc00000 => 7f800000 7f800000 7f800000 7f800000
+#12: xvmaxsp ffffffff @max@ ff800000 AND ffffffff @max@ c683287b AND ffc00000 @max@ 80000000 AND ffc00000 @max@ 00000000 => ff800000 c683287b 80000000 00000000
+#13: xvmaxsp ffffffff @max@ 00000000 AND ffffffff @max@ 7f800000 AND ffffffff @max@ 7fffffff AND ffffffff @max@ 7fc00000 => 00000000 7f800000 ffffffff ffffffff
+#14: xvmaxsp ffc00000 @max@ ff800000 AND ffc00000 @max@ c683287b AND ffc00000 @max@ 80000000 AND 49192c2d @max@ 49c1288d => ff800000 c683287b 80000000 49c1288d
+#15: xvmaxsp 49192c2d @max@ 49c1288d AND 7fffffff @max@ 7fc00000 AND 7fc00000 @max@ 7fc00000 AND 7fc00000 @max@ ffc00000 => 49c1288d 7fffffff 7fc00000 7fc00000
+
+
+#0: xvminsp ff800000 @min@ ff800000 AND ff800000 @min@ c683287b AND 49192c2d @min@ 49c1288d AND ff800000 @min@ 00000000 => ff800000 ff800000 49192c2d ff800000
+#1: xvminsp ff800000 @min@ 00000000 AND ff800000 @min@ 7f800000 AND ff800000 @min@ 7fffffff AND ff800000 @min@ 7fc00000 => ff800000 ff800000 ff800000 ff800000
+#2: xvminsp c683287b @min@ ff800000 AND c683287b @min@ c683287b AND c683287b @min@ 80000000 AND c683287b @min@ 00000000 => ff800000 c683287b c683287b c683287b
+#3: xvminsp c683287b @min@ 00000000 AND c683287b @min@ 7f800000 AND c683287b @min@ 7fffffff AND c683287b @min@ 7fc00000 => c683287b c683287b c683287b c683287b
+#4: xvminsp 80000000 @min@ ff800000 AND 80000000 @min@ c683287b AND 80000000 @min@ 80000000 AND 80000000 @min@ 00000000 => ff800000 c683287b 80000000 80000000
+#5: xvminsp 80000000 @min@ 00000000 AND 80000000 @min@ 7f800000 AND 80000000 @min@ 7fffffff AND 80000000 @min@ 7fc00000 => 80000000 80000000 80000000 80000000
+#6: xvminsp 00000000 @min@ ff800000 AND 00000000 @min@ c683287b AND 00000000 @min@ 80000000 AND 00000000 @min@ 00000000 => ff800000 c683287b 80000000 00000000
+#7: xvminsp 00000000 @min@ 00000000 AND 00000000 @min@ 7f800000 AND 00000000 @min@ 7fffffff AND 00000000 @min@ 7fc00000 => 00000000 00000000 00000000 00000000
+#8: xvminsp 00000000 @min@ ff800000 AND 00000000 @min@ c683287b AND 00000000 @min@ 80000000 AND 00000000 @min@ 00000000 => ff800000 c683287b 80000000 00000000
+#9: xvminsp 00000000 @min@ 42780000 AND 00000000 @min@ 7f800000 AND 00000000 @min@ 7fffffff AND 00000000 @min@ 7fc00000 => 00000000 00000000 00000000 00000000
+#10: xvminsp 7f800000 @min@ ff800000 AND 7f800000 @min@ c683287b AND 7f800000 @min@ 80000000 AND 7f800000 @min@ 00000000 => ff800000 c683287b 80000000 00000000
+#11: xvminsp 7f800000 @min@ 00000000 AND 7f800000 @min@ 7f800000 AND 7f800000 @min@ 7fffffff AND 7f800000 @min@ 7fc00000 => 00000000 7f800000 7f800000 7f800000
+#12: xvminsp ffffffff @min@ ff800000 AND ffffffff @min@ c683287b AND ffc00000 @min@ 80000000 AND ffc00000 @min@ 00000000 => ff800000 c683287b 80000000 00000000
+#13: xvminsp ffffffff @min@ 00000000 AND ffffffff @min@ 7f800000 AND ffffffff @min@ 7fffffff AND ffffffff @min@ 7fc00000 => 00000000 7f800000 ffffffff ffffffff
+#14: xvminsp ffc00000 @min@ ff800000 AND ffc00000 @min@ c683287b AND ffc00000 @min@ 80000000 AND 49192c2d @min@ 49c1288d => ff800000 c683287b 80000000 49192c2d
+#15: xvminsp 49192c2d @min@ 49c1288d AND 7fffffff @min@ 7fc00000 AND 7fc00000 @min@ 7fc00000 AND 7fc00000 @min@ ffc00000 => 49192c2d 7fffffff 7fc00000 7fc00000
+
+
+#0: xvcpsgndp fff0000000000000 +-cp fff0000000000000 AND fff0000000000000 +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#1: xvcpsgndp 41232585a9900000 +-cp 41382511a2000000 AND fff0000000000000 +-cp 0000000000000000 => 41382511a2000000 8000000000000000
+#2: xvcpsgndp fff0000000000000 +-cp 0123214569900000 AND fff0000000000000 +-cp 7ff0000000000000 => 8123214569900000 fff0000000000000
+#3: xvcpsgndp fff0000000000000 +-cp 7ff7ffffffffffff AND fff0000000000000 +-cp 7ff8000000000000 => fff7ffffffffffff fff8000000000000
+#4: xvcpsgndp c0d0650f5a07b353 +-cp fff0000000000000 AND c0d0650f5a07b353 +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#5: xvcpsgndp c0d0650f5a07b353 +-cp 8000000000000000 AND c0d0650f5a07b353 +-cp 0000000000000000 => 8000000000000000 8000000000000000
+#6: xvcpsgndp c0d0650f5a07b353 +-cp 0123214569900000 AND c0d0650f5a07b353 +-cp 7ff0000000000000 => 8123214569900000 fff0000000000000
+#7: xvcpsgndp c0d0650f5a07b353 +-cp 7ff7ffffffffffff AND c0d0650f5a07b353 +-cp 7ff8000000000000 => fff7ffffffffffff fff8000000000000
+#8: xvcpsgndp 8000000000000000 +-cp fff0000000000000 AND 8000000000000000 +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#9: xvcpsgndp 8000000000000000 +-cp 8000000000000000 AND 8000000000000000 +-cp 0000000000000000 => 8000000000000000 8000000000000000
+#10: xvcpsgndp 8000000000000000 +-cp 0123214569900000 AND 8000000000000000 +-cp 7ff0000000000000 => 8123214569900000 fff0000000000000
+#11: xvcpsgndp 8000000000000000 +-cp 7ff7ffffffffffff AND 8000000000000000 +-cp 7ff8000000000000 => fff7ffffffffffff fff8000000000000
+#12: xvcpsgndp 0000000000000000 +-cp fff0000000000000 AND 0000000000000000 +-cp c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#13: xvcpsgndp 0000000000000000 +-cp 8000000000000000 AND 0000000000000000 +-cp 0000000000000000 => 0000000000000000 0000000000000000
+#14: xvcpsgndp 0000000000000000 +-cp 0123214569900000 AND 0000000000000000 +-cp 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#15: xvcpsgndp 0000000000000000 +-cp 7ff7ffffffffffff AND 0000000000000000 +-cp 7ff8000000000000 => 7ff7ffffffffffff 7ff8000000000000
+#16: xvcpsgndp 0123214569900000 +-cp fff0000000000000 AND 0123214569900000 +-cp c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#17: xvcpsgndp 0123214569900000 +-cp 8000000000000000 AND 0123214569900000 +-cp 0000000000000000 => 0000000000000000 0000000000000000
+#18: xvcpsgndp 0123214569900000 +-cp 404f000000000000 AND 0123214569900000 +-cp 7ff0000000000000 => 404f000000000000 7ff0000000000000
+#19: xvcpsgndp 0123214569900000 +-cp 7ff7ffffffffffff AND 0123214569900000 +-cp 7ff8000000000000 => 7ff7ffffffffffff 7ff8000000000000
+#20: xvcpsgndp 7ff0000000000000 +-cp fff0000000000000 AND 7ff0000000000000 +-cp c0d0650f5a07b353 => 7ff0000000000000 40d0650f5a07b353
+#21: xvcpsgndp 7ff0000000000000 +-cp 8000000000000000 AND 7ff0000000000000 +-cp 0000000000000000 => 0000000000000000 0000000000000000
+#22: xvcpsgndp 7ff0000000000000 +-cp 0123214569900000 AND 7ff0000000000000 +-cp 7ff0000000000000 => 0123214569900000 7ff0000000000000
+#23: xvcpsgndp 7ff0000000000000 +-cp 7ff7ffffffffffff AND 7ff0000000000000 +-cp 7ff8000000000000 => 7ff7ffffffffffff 7ff8000000000000
+#24: xvcpsgndp fff7ffffffffffff +-cp fff0000000000000 AND fff7ffffffffffff +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#25: xvcpsgndp fff8000000000000 +-cp 8000000000000000 AND fff8000000000000 +-cp 0000000000000000 => 8000000000000000 8000000000000000
+#26: xvcpsgndp fff7ffffffffffff +-cp 0123214569900000 AND fff7ffffffffffff +-cp 7ff0000000000000 => 8123214569900000 fff0000000000000
+#27: xvcpsgndp fff7ffffffffffff +-cp 7ff7ffffffffffff AND fff7ffffffffffff +-cp 7ff8000000000000 => fff7ffffffffffff fff8000000000000
+#28: xvcpsgndp fff8000000000000 +-cp fff0000000000000 AND fff8000000000000 +-cp c0d0650f5a07b353 => fff0000000000000 c0d0650f5a07b353
+#29: xvcpsgndp fff8000000000000 +-cp 8000000000000000 AND 41232585a9900000 +-cp 41382511a2000000 => 8000000000000000 41382511a2000000
+#30: xvcpsgndp 41232585a9900000 +-cp 41382511a2000000 AND 7ff7ffffffffffff +-cp 7ff8000000000000 => 41382511a2000000 7ff8000000000000
+#31: xvcpsgndp 7ff8000000000000 +-cp 7ff8000000000000 AND 7ff8000000000000 +-cp fff8000000000000 => 7ff8000000000000 7ff8000000000000
+
+
+#0: xvcpsgnsp ff800000 +-cp ff800000 AND ff800000 +-cp c683287b AND 49192c2d +-cp 49c1288d AND ff800000 +-cp 00000000 => ff800000 c683287b 49c1288d 80000000
+#1: xvcpsgnsp ff800000 +-cp 00000000 AND ff800000 +-cp 7f800000 AND ff800000 +-cp 7fffffff AND ff800000 +-cp 7fc00000 => 80000000 ff800000 ffffffff ffc00000
+#2: xvcpsgnsp c683287b +-cp ff800000 AND c683287b +-cp c683287b AND c683287b +-cp 80000000 AND c683287b +-cp 00000000 => ff800000 c683287b 80000000 80000000
+#3: xvcpsgnsp c683287b +-cp 00000000 AND c683287b +-cp 7f800000 AND c683287b +-cp 7fffffff AND c683287b +-cp 7fc00000 => 80000000 ff800000 ffffffff ffc00000
+#4: xvcpsgnsp 80000000 +-cp ff800000 AND 80000000 +-cp c683287b AND 80000000 +-cp 80000000 AND 80000000 +-cp 00000000 => ff800000 c683287b 80000000 80000000
+#5: xvcpsgnsp 80000000 +-cp 00000000 AND 80000000 +-cp 7f800000 AND 80000000 +-cp 7fffffff AND 80000000 +-cp 7fc00000 => 80000000 ff800000 ffffffff ffc00000
+#6: xvcpsgnsp 00000000 +-cp ff800000 AND 00000000 +-cp c683287b AND 00000000 +-cp 80000000 AND 00000000 +-cp 00000000 => 7f800000 4683287b 00000000 00000000
+#7: xvcpsgnsp 00000000 +-cp 00000000 AND 00000000 +-cp 7f800000 AND 00000000 +-cp 7fffffff AND 00000000 +-cp 7fc00000 => 00000000 7f800000 7fffffff 7fc00000
+#8: xvcpsgnsp 00000000 +-cp ff800000 AND 00000000 +-cp c683287b AND 00000000 +-cp 80000000 AND 00000000 +-cp 00000000 => 7f800000 4683287b 00000000 00000000
+#9: xvcpsgnsp 00000000 +-cp 42780000 AND 00000000 +-cp 7f800000 AND 00000000 +-cp 7fffffff AND 00000000 +-cp 7fc00000 => 42780000 7f800000 7fffffff 7fc00000
+#10: xvcpsgnsp 7f800000 +-cp ff800000 AND 7f800000 +-cp c683287b AND 7f800000 +-cp 80000000 AND 7f800000 +-cp 00000000 => 7f800000 4683287b 00000000 00000000
+#11: xvcpsgnsp 7f800000 +-cp 00000000 AND 7f800000 +-cp 7f800000 AND 7f800000 +-cp 7fffffff AND 7f800000 +-cp 7fc00000 => 00000000 7f800000 7fffffff 7fc00000
+#12: xvcpsgnsp ffffffff +-cp ff800000 AND ffffffff +-cp c683287b AND ffc00000 +-cp 80000000 AND ffc00000 +-cp 00000000 => ff800000 c683287b 80000000 80000000
+#13: xvcpsgnsp ffffffff +-cp 00000000 AND ffffffff +-cp 7f800000 AND ffffffff +-cp 7fffffff AND ffffffff +-cp 7fc00000 => 80000000 ff800000 ffffffff ffc00000
+#14: xvcpsgnsp ffc00000 +-cp ff800000 AND ffc00000 +-cp c683287b AND ffc00000 +-cp 80000000 AND 49192c2d +-cp 49c1288d => ff800000 c683287b 80000000 49c1288d
+#15: xvcpsgnsp 49192c2d +-cp 49c1288d AND 7fffffff +-cp 7fc00000 AND 7fc00000 +-cp 7fc00000 AND 7fc00000 +-cp ffc00000 => 49c1288d 7fc00000 7fc00000 7fc00000
+
+
+Test bit permute double
+bpermd: 0x1b2c31f030000001 : 0xa12bc37de56f9708 => 0xce
+
+Test xxsel instruction
+xxsel a12bc37de56f9708,fedc432124681235,ffffffff01020304 => fedc4321e46d960c
+xxsel 3894c1fddeadbeef,f1e2d3c4e0057708,128934bd00000000 => 3894d1c4deadbeef
+
+Test xxspltw instruction
+xxspltw 0xfedc432124681235f1e2d3c4e0057708 0=> 0xfedc4321fedc4321fedc4321fedc4321
+xxspltw 0xfedc432124681235f1e2d3c4e0057708 1=> 0x24681235246812352468123524681235
+xxspltw 0xfedc432124681235f1e2d3c4e0057708 2=> 0xf1e2d3c4f1e2d3c4f1e2d3c4f1e2d3c4
+xxspltw 0xfedc432124681235f1e2d3c4e0057708 3=> 0xe0057708e0057708e0057708e0057708
+
+Test div extensions
+#0: divde: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=0; XER=0
+#1: divde: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=0; XER=0
+#2: divde: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=0
+#3: divde: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=0; XER=0
+#4: divde: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divde: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=0
+#6: divde: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=0; XER=0
+#7: divde: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=0; XER=0
+#8: divde: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divde: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=0
+#10: divde: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=0
+#11: divde: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divde: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divde.: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=2; XER=0
+#1: divde.: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=2; XER=0
+#2: divde.: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=2; XER=0
+#3: divde.: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=2; XER=0
+#4: divde.: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divde.: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=2; XER=0
+#6: divde.: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=2; XER=0
+#7: divde.: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=8; XER=0
+#8: divde.: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divde.: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=2; XER=0
+#10: divde.: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=2; XER=0
+#11: divde.: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divde.: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divdeo: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=0; XER=c0000000
+#1: divdeo: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=0; XER=c0000000
+#2: divdeo: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=c0000000
+#3: divdeo: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=0; XER=c0000000
+#4: divdeo: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divdeo: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=c0000000
+#6: divdeo: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=0; XER=c0000000
+#7: divdeo: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=0; XER=0
+#8: divdeo: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divdeo: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=c0000000
+#10: divdeo: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=c0000000
+#11: divdeo: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divdeo: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divdeo.: 0x0000000000000004 / 0xfffffffffffffffc = 0x0000000000000000; CR=3; XER=c0000000
+#1: divdeo.: 0x0000000000000004 / 0xfffffffffffffffd = 0x0000000000000000; CR=3; XER=c0000000
+#2: divdeo.: 0x0000000000000004 / 0x0000000000000004 = 0x0000000000000000; CR=3; XER=c0000000
+#3: divdeo.: 0x0000000000000004 / 0xfffffffffffffffb = 0x0000000000000000; CR=3; XER=c0000000
+#4: divdeo.: 0x0000000000000003 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divdeo.: 0x8000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=3; XER=c0000000
+#6: divdeo.: 0x000000000000050c / 0xffffffffffffffff = 0x0000000000000000; CR=3; XER=c0000000
+#7: divdeo.: 0x000000000000050c / 0xfffffffffffff000 = 0xaf40000000000000; CR=8; XER=0
+#8: divdeo.: 0x000000001234fedc / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divdeo.: 0xabcd87651234fedc / 0x00000000a123b893 = 0x0000000000000000; CR=3; XER=c0000000
+#10: divdeo.: 0x000123456789abdc / 0x0000000000000000 = 0x0000000000000000; CR=3; XER=c0000000
+#11: divdeo.: 0x0000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divdeo.: 0x0000000000000077 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=4; XER=0
+#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
+#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=4; XER=0
+#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
+Test floating point convert [word | doubleword] unsigned, with round toward zero
+#0: fctiduz: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiduz: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiduz: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiduz: 0x7fe800000000051b (1.348270e+308) ==> 0xffffffffffffffff
+#4: fctiduz: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiduz: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiduz: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiduz: 0x7ff0000000000000 (inf) ==> 0xffffffffffffffff
+#8: fctiduz: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiduz: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiduz: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiduz: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiduz: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiduz: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiduz: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiduz: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c2
+#16: fctiduz: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182511
+
+#0: fctiduz.: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiduz.: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiduz.: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiduz.: 0x7fe800000000051b (1.348270e+308) ==> 0xffffffffffffffff
+#4: fctiduz.: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiduz.: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiduz.: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiduz.: 0x7ff0000000000000 (inf) ==> 0xffffffffffffffff
+#8: fctiduz.: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiduz.: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiduz.: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiduz.: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiduz.: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiduz.: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiduz.: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiduz.: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c2
+#16: fctiduz.: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182511
+
+
+#0: fctidu: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctidu: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctidu: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctidu: 0x7fe800000000051b (1.348270e+308) ==> 0xffffffffffffffff
+#4: fctidu: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctidu: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctidu: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctidu: 0x7ff0000000000000 (inf) ==> 0xffffffffffffffff
+#8: fctidu: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctidu: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctidu: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctidu: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctidu: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctidu: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctidu: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctidu: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c3
+#16: fctidu: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182512
+
+#0: fctidu.: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctidu.: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctidu.: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctidu.: 0x7fe800000000051b (1.348270e+308) ==> 0xffffffffffffffff
+#4: fctidu.: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctidu.: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctidu.: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctidu.: 0x7ff0000000000000 (inf) ==> 0xffffffffffffffff
+#8: fctidu.: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctidu.: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctidu.: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctidu.: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctidu.: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctidu.: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctidu.: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctidu.: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c3
+#16: fctidu.: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182512
+
+
+#0: fctiwuz: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiwuz: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiwuz: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiwuz: 0x7fe800000000051b (1.348270e+308) ==> 0x00000000ffffffff
+#4: fctiwuz: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiwuz: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiwuz: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiwuz: 0x7ff0000000000000 (inf) ==> 0x00000000ffffffff
+#8: fctiwuz: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiwuz: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiwuz: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiwuz: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiwuz: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiwuz: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiwuz: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiwuz: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c2
+#16: fctiwuz: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182511
+
+#0: fctiwuz.: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiwuz.: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiwuz.: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiwuz.: 0x7fe800000000051b (1.348270e+308) ==> 0x00000000ffffffff
+#4: fctiwuz.: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiwuz.: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiwuz.: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiwuz.: 0x7ff0000000000000 (inf) ==> 0x00000000ffffffff
+#8: fctiwuz.: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiwuz.: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiwuz.: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiwuz.: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiwuz.: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiwuz.: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiwuz.: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiwuz.: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c2
+#16: fctiwuz.: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182511
+
+
+#0: fctiwu: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiwu: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiwu: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiwu: 0x7fe800000000051b (1.348270e+308) ==> 0x00000000ffffffff
+#4: fctiwu: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiwu: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiwu: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiwu: 0x7ff0000000000000 (inf) ==> 0x00000000ffffffff
+#8: fctiwu: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiwu: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiwu: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiwu: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiwu: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiwu: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiwu: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiwu: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c3
+#16: fctiwu: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182512
+
+#0: fctiwu.: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
+#1: fctiwu.: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e
+#2: fctiwu.: 0x0018000000b77501 (3.337611e-308) ==> 0x0000000000000000
+#3: fctiwu.: 0x7fe800000000051b (1.348270e+308) ==> 0x00000000ffffffff
+#4: fctiwu.: 0x0123214569900000 (3.486973e-303) ==> 0x0000000000000000
+#5: fctiwu.: 0x0000000000000000 (0.000000e+00) ==> 0x0000000000000000
+#6: fctiwu.: 0x8000000000000000 (-0.000000e+00) ==> 0x0000000000000000
+#7: fctiwu.: 0x7ff0000000000000 (inf) ==> 0x00000000ffffffff
+#8: fctiwu.: 0xfff0000000000000 (-inf) ==> 0x0000000000000000
+#9: fctiwu.: 0x7ff7ffffffffffff (nan) ==> 0x0000000000000000
+#10: fctiwu.: 0xfff7ffffffffffff (-nan) ==> 0x0000000000000000
+#11: fctiwu.: 0x7ff8000000000000 (nan) ==> 0x0000000000000000
+#12: fctiwu.: 0xfff8000000000000 (-nan) ==> 0x0000000000000000
+#13: fctiwu.: 0x8008340000078000 (-1.140785e-308) ==> 0x0000000000000000
+#14: fctiwu.: 0xc0d0650f5a07b353 (-1.678824e+04) ==> 0x0000000000000000
+#15: fctiwu.: 0x41232585a9900000 (6.273948e+05) ==> 0x00000000000992c3
+#16: fctiwu.: 0x41382511a2000000 (1.582354e+06) ==> 0x0000000000182512
+
+
+Test stdbrx instruction
+stdbrx: 0xdeadbacf12345678 ==> 0x78563412cfbaadde
+
+Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p
+#0: xsnmsubadp !*-(fff0000000000000,fff0000000000000,3fd8000000000000) = 7ff8000000000000
+#1: xsnmsubadp !*-(c0d0650f5a07b353,fff0000000000000,404f000000000000) = 7ff0000000000000
+#2: xsnmsubadp !*-(41382511a2000000,41232585a9900000,0018000000b77501) = 41382511a2000000
+#3: xsnmsubadp !*-(0000000000000000,fff0000000000000,7fe800000000051b) = 7ff0000000000000
+#4: xsnmsubadp !*-(0123214569900000,fff0000000000000,0123214569900000) = 7ff0000000000000
+#5: xsnmsubadp !*-(7ff0000000000000,fff0000000000000,0000000000000000) = 7ff8000000000000
+#6: xsnmsubadp !*-(7ff7ffffffffffff,fff0000000000000,8000000000000000) = 7fffffffffffffff
+#7: xsnmsubadp !*-(7ff8000000000000,fff0000000000000,7ff0000000000000) = 7ff8000000000000
+#8: xsnmsubadp !*-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) = fff0000000000000
+#9: xsnmsubadp !*-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) = 7fffffffffffffff
+#10: xsnmsubadp !*-(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) = ffffffffffffffff
+#11: xsnmsubadp !*-(0000000000000000,c0d0650f5a07b353,7ff8000000000000) = 7ff8000000000000
+#12: xsnmsubadp !*-(0123214569900000,c0d0650f5a07b353,fff8000000000000) = fff8000000000000
+#13: xsnmsubadp !*-(7ff0000000000000,c0d0650f5a07b353,8008340000078000) = 7ff0000000000000
+#14: xsnmsubadp !*-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) = 7fffffffffffffff
+#15: xsnmsubadp !*-(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) = 7ff8000000000000
+#16: xsnmsubadp !*-(fff0000000000000,8000000000000000,3fd8000000000000) = fff0000000000000
+#17: xsnmsubadp !*-(c0d0650f5a07b353,8000000000000000,404f000000000000) = c0d0650f5a07b353
+#18: xsnmsubadp !*-(8000000000000000,8000000000000000,0018000000b77501) = 8000000000000000
+#19: xsnmsubadp !*-(0000000000000000,8000000000000000,7fe800000000051b) = 0000000000000000
+#20: xsnmsubadp !*-(0123214569900000,8000000000000000,0123214569900000) = 0123214569900000
+#21: xsnmsubadp !*-(7ff0000000000000,8000000000000000,0000000000000000) = 7ff0000000000000
+#22: xsnmsubadp !*-(7ff7ffffffffffff,8000000000000000,8000000000000000) = 7fffffffffffffff
+#23: xsnmsubadp !*-(7ff8000000000000,8000000000000000,7ff0000000000000) = 7ff8000000000000
+#24: xsnmsubadp !*-(fff0000000000000,0000000000000000,fff0000000000000) = 7ff8000000000000
+#25: xsnmsubadp !*-(c0d0650f5a07b353,0000000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#26: xsnmsubadp !*-(8000000000000000,0000000000000000,fff7ffffffffffff) = ffffffffffffffff
+#27: xsnmsubadp !*-(0000000000000000,0000000000000000,7ff8000000000000) = 7ff8000000000000
+#28: xsnmsubadp !*-(0123214569900000,0000000000000000,fff8000000000000) = fff8000000000000
+#29: xsnmsubadp !*-(7ff0000000000000,0000000000000000,8008340000078000) = 7ff0000000000000
+#30: xsnmsubadp !*-(7ff7ffffffffffff,0000000000000000,c0d0650f5a07b353) = 7fffffffffffffff
+#31: xsnmsubadp !*-(7ff8000000000000,0000000000000000,41232585a9900000) = 7ff8000000000000
+#32: xsnmsubadp !*-(fff0000000000000,0123214569900000,3fd8000000000000) = fff0000000000000
+#33: xsnmsubadp !*-(c0d0650f5a07b353,0123214569900000,404f000000000000) = c0d0650f5a07b353
+#34: xsnmsubadp !*-(8000000000000000,0123214569900000,0018000000b77501) = 8000000000000000
+#35: xsnmsubadp !*-(0000000000000000,0123214569900000,7fe800000000051b) = c11cb1e81e58061b
+#36: xsnmsubadp !*-(404f000000000000,0123214569900000,0123214569900000) = 404f000000000000
+#37: xsnmsubadp !*-(7ff0000000000000,0123214569900000,0000000000000000) = 7ff0000000000000
+#38: xsnmsubadp !*-(7ff7ffffffffffff,0123214569900000,8000000000000000) = 7fffffffffffffff
+#39: xsnmsubadp !*-(7ff8000000000000,0123214569900000,7ff0000000000000) = 7ff8000000000000
+#40: xsnmsubadp !*-(fff0000000000000,7ff0000000000000,fff0000000000000) = 7ff8000000000000
+#41: xsnmsubadp !*-(c0d0650f5a07b353,7ff0000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#42: xsnmsubadp !*-(8000000000000000,7ff0000000000000,fff7ffffffffffff) = ffffffffffffffff
+#43: xsnmsubadp !*-(0000000000000000,7ff0000000000000,7ff8000000000000) = 7ff8000000000000
+#44: xsnmsubadp !*-(0123214569900000,7ff0000000000000,fff8000000000000) = fff8000000000000
+#45: xsnmsubadp !*-(7ff0000000000000,7ff0000000000000,8008340000078000) = 7ff0000000000000
+#46: xsnmsubadp !*-(7ff7ffffffffffff,7ff0000000000000,c0d0650f5a07b353) = 7fffffffffffffff
+#47: xsnmsubadp !*-(7ff8000000000000,7ff0000000000000,41232585a9900000) = 7ff8000000000000
+#48: xsnmsubadp !*-(fff0000000000000,fff7ffffffffffff,3fd8000000000000) = ffffffffffffffff
+#49: xsnmsubadp !*-(c0d0650f5a07b353,fff7ffffffffffff,404f000000000000) = ffffffffffffffff
+#50: xsnmsubadp !*-(8000000000000000,fff8000000000000,0018000000b77501) = fff8000000000000
+#51: xsnmsubadp !*-(0000000000000000,fff8000000000000,7fe800000000051b) = fff8000000000000
+#52: xsnmsubadp !*-(0123214569900000,fff7ffffffffffff,0123214569900000) = ffffffffffffffff
+#53: xsnmsubadp !*-(7ff0000000000000,fff7ffffffffffff,0000000000000000) = ffffffffffffffff
+#54: xsnmsubadp !*-(7ff7ffffffffffff,fff7ffffffffffff,8000000000000000) = ffffffffffffffff
+#55: xsnmsubadp !*-(7ff8000000000000,fff7ffffffffffff,7ff0000000000000) = ffffffffffffffff
+#56: xsnmsubadp !*-(fff0000000000000,fff8000000000000,fff0000000000000) = fff8000000000000
+#57: xsnmsubadp !*-(c0d0650f5a07b353,fff8000000000000,7ff7ffffffffffff) = fff8000000000000
+#58: xsnmsubadp !*-(8000000000000000,fff8000000000000,fff7ffffffffffff) = fff8000000000000
+#59: xsnmsubadp !*-(41382511a2000000,41232585a9900000,7ff8000000000000) = 7ff8000000000000
+#60: xsnmsubadp !*-(41382511a2000000,41232585a9900000,fff8000000000000) = fff8000000000000
+#61: xsnmsubadp !*-(7ff8000000000000,7ff7ffffffffffff,8008340000078000) = 7fffffffffffffff
+#62: xsnmsubadp !*-(7ff8000000000000,7ff8000000000000,c0d0650f5a07b353) = 7ff8000000000000
+#63: xsnmsubadp !*-(fff8000000000000,7ff8000000000000,41232585a9900000) = 7ff8000000000000
+
+#0: xsnmsubmdp !*-(3fd8000000000000,fff0000000000000,fff0000000000000) = 7ff8000000000000
+#1: xsnmsubmdp !*-(404f000000000000,fff0000000000000,c0d0650f5a07b353) = 7ff0000000000000
+#2: xsnmsubmdp !*-(0018000000b77501,41232585a9900000,41382511a2000000) = 41382511a2000000
+#3: xsnmsubmdp !*-(7fe800000000051b,fff0000000000000,0000000000000000) = 7ff0000000000000
+#4: xsnmsubmdp !*-(0123214569900000,fff0000000000000,0123214569900000) = 7ff0000000000000
+#5: xsnmsubmdp !*-(0000000000000000,fff0000000000000,7ff0000000000000) = 7ff8000000000000
+#6: xsnmsubmdp !*-(8000000000000000,fff0000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#7: xsnmsubmdp !*-(7ff0000000000000,fff0000000000000,7ff8000000000000) = 7ff8000000000000
+#8: xsnmsubmdp !*-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) = fff0000000000000
+#9: xsnmsubmdp !*-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) = 7fffffffffffffff
+#10: xsnmsubmdp !*-(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) = ffffffffffffffff
+#11: xsnmsubmdp !*-(7ff8000000000000,c0d0650f5a07b353,0000000000000000) = 7ff8000000000000
+#12: xsnmsubmdp !*-(fff8000000000000,c0d0650f5a07b353,0123214569900000) = fff8000000000000
+#13: xsnmsubmdp !*-(8008340000078000,c0d0650f5a07b353,7ff0000000000000) = 7ff0000000000000
+#14: xsnmsubmdp !*-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) = 7fffffffffffffff
+#15: xsnmsubmdp !*-(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) = 7ff8000000000000
+#16: xsnmsubmdp !*-(3fd8000000000000,8000000000000000,fff0000000000000) = fff0000000000000
+#17: xsnmsubmdp !*-(404f000000000000,8000000000000000,c0d0650f5a07b353) = c0d0650f5a07b353
+#18: xsnmsubmdp !*-(0018000000b77501,8000000000000000,8000000000000000) = 8000000000000000
+#19: xsnmsubmdp !*-(7fe800000000051b,8000000000000000,0000000000000000) = 0000000000000000
+#20: xsnmsubmdp !*-(0123214569900000,8000000000000000,0123214569900000) = 0123214569900000
+#21: xsnmsubmdp !*-(0000000000000000,8000000000000000,7ff0000000000000) = 7ff0000000000000
+#22: xsnmsubmdp !*-(8000000000000000,8000000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#23: xsnmsubmdp !*-(7ff0000000000000,8000000000000000,7ff8000000000000) = 7ff8000000000000
+#24: xsnmsubmdp !*-(fff0000000000000,0000000000000000,fff0000000000000) = 7ff8000000000000
+#25: xsnmsubmdp !*-(7ff7ffffffffffff,0000000000000000,c0d0650f5a07b353) = 7fffffffffffffff
+#26: xsnmsubmdp !*-(fff7ffffffffffff,0000000000000000,8000000000000000) = ffffffffffffffff
+#27: xsnmsubmdp !*-(7ff8000000000000,0000000000000000,0000000000000000) = 7ff8000000000000
+#28: xsnmsubmdp !*-(fff8000000000000,0000000000000000,0123214569900000) = fff8000000000000
+#29: xsnmsubmdp !*-(8008340000078000,0000000000000000,7ff0000000000000) = 7ff0000000000000
+#30: xsnmsubmdp !*-(c0d0650f5a07b353,0000000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#31: xsnmsubmdp !*-(41232585a9900000,0000000000000000,7ff8000000000000) = 7ff8000000000000
+#32: xsnmsubmdp !*-(3fd8000000000000,0123214569900000,fff0000000000000) = fff0000000000000
+#33: xsnmsubmdp !*-(404f000000000000,0123214569900000,c0d0650f5a07b353) = c0d0650f5a07b353
+#34: xsnmsubmdp !*-(0018000000b77501,0123214569900000,8000000000000000) = 8000000000000000
+#35: xsnmsubmdp !*-(7fe800000000051b,0123214569900000,0000000000000000) = c11cb1e81e58061b
+#36: xsnmsubmdp !*-(0123214569900000,0123214569900000,404f000000000000) = 404f000000000000
+#37: xsnmsubmdp !*-(0000000000000000,0123214569900000,7ff0000000000000) = 7ff0000000000000
+#38: xsnmsubmdp !*-(8000000000000000,0123214569900000,7ff7ffffffffffff) = 7fffffffffffffff
+#39: xsnmsubmdp !*-(7ff0000000000000,0123214569900000,7ff8000000000000) = 7ff8000000000000
+#40: xsnmsubmdp !*-(fff0000000000000,7ff0000000000000,fff0000000000000) = 7ff8000000000000
+#41: xsnmsubmdp !*-(7ff7ffffffffffff,7ff0000000000000,c0d0650f5a07b353) = 7fffffffffffffff
+#42: xsnmsubmdp !*-(fff7ffffffffffff,7ff0000000000000,8000000000000000) = ffffffffffffffff
+#43: xsnmsubmdp !*-(7ff8000000000000,7ff0000000000000,0000000000000000) = 7ff8000000000000
+#44: xsnmsubmdp !*-(fff8000000000000,7ff0000000000000,0123214569900000) = fff8000000000000
+#45: xsnmsubmdp !*-(8008340000078000,7ff0000000000000,7ff0000000000000) = 7ff0000000000000
+#46: xsnmsubmdp !*-(c0d0650f5a07b353,7ff0000000000000,7ff7ffffffffffff) = 7fffffffffffffff
+#47: xsnmsubmdp !*-(41232585a9900000,7ff0000000000000,7ff8000000000000) = 7ff8000000000000
+#48: xsnmsubmdp !*-(3fd8000000000000,fff7ffffffffffff,fff0000000000000) = ffffffffffffffff
+#49: xsnmsubmdp !*-(404f000000000000,fff7ffffffffffff,c0d0650f5a07b353) = ffffffffffffffff
+#50: xsnmsubmdp !*-(0018000000b77501,fff8000000000000,8000000000000000) = fff8000000000000
+#51: xsnmsubmdp !*-(7fe800000000051b,fff8000000000000,0000000000000000) = fff8000000000000
+#52: xsnmsubmdp !*-(0123214569900000,fff7ffffffffffff,0123214569900000) = ffffffffffffffff
+#53: xsnmsubmdp !*-(0000000000000000,fff7ffffffffffff,7ff0000000000000) = ffffffffffffffff
+#54: xsnmsubmdp !*-(8000000000000000,fff7ffffffffffff,7ff7ffffffffffff) = ffffffffffffffff
+#55: xsnmsubmdp !*-(7ff0000000000000,fff7ffffffffffff,7ff8000000000000) = ffffffffffffffff
+#56: xsnmsubmdp !*-(fff0000000000000,fff8000000000000,fff0000000000000) = fff8000000000000
+#57: xsnmsubmdp !*-(7ff7ffffffffffff,fff8000000000000,c0d0650f5a07b353) = fff8000000000000
+#58: xsnmsubmdp !*-(fff7ffffffffffff,fff8000000000000,8000000000000000) = fff8000000000000
+#59: xsnmsubmdp !*-(7ff8000000000000,41232585a9900000,41382511a2000000) = 7ff8000000000000
+#60: xsnmsubmdp !*-(fff8000000000000,41232585a9900000,41382511a2000000) = fff8000000000000
+#61: xsnmsubmdp !*-(8008340000078000,7ff7ffffffffffff,7ff8000000000000) = 7fffffffffffffff
+#62: xsnmsubmdp !*-(c0d0650f5a07b353,7ff8000000000000,7ff8000000000000) = 7ff8000000000000
+#63: xsnmsubmdp !*-(41232585a9900000,7ff8000000000000,fff8000000000000) = 7ff8000000000000
+
+#0: xvmaddadp *+(fff0000000000000,fff0000000000000,3fd8000000000000) AND *+(c0d0650f5a07b353,fff0000000000000,404f000000000000) => fff0000000000000 fff0000000000000
+#1: xvmaddadp *+(41382511a2000000,41232585a9900000,0018000000b77501) AND *+(0000000000000000,fff0000000000000,7fe800000000051b) => 41382511a2000000 fff0000000000000
+#2: xvmaddadp *+(0123214569900000,fff0000000000000,0123214569900000) AND *+(7ff0000000000000,fff0000000000000,0000000000000000) => fff0000000000000 7ff8000000000000
+#3: xvmaddadp *+(7ff7ffffffffffff,fff0000000000000,8000000000000000) AND *+(7ff8000000000000,fff0000000000000,7ff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvmaddadp *+(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND *+(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) => 7ff8000000000000 7fffffffffffffff
+#5: xvmaddadp *+(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) AND *+(0000000000000000,c0d0650f5a07b353,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvmaddadp *+(0123214569900000,c0d0650f5a07b353,fff8000000000000) AND *+(7ff0000000000000,c0d0650f5a07b353,8008340000078000) => fff8000000000000 7ff0000000000000
+#7: xvmaddadp *+(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) AND *+(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) => 7fffffffffffffff 7ff8000000000000
+#8: xvmaddadp *+(fff0000000000000,8000000000000000,404f000000000000) AND *+(c0d0650f5a07b353,8000000000000000,0018000000b77501) => fff0000000000000 c0d0650f5a07b353
+#9: xvmaddadp *+(8000000000000000,8000000000000000,7fe800000000051b) AND *+(0000000000000000,8000000000000000,0123214569900000) => 8000000000000000 0000000000000000
+#10: xvmaddadp *+(0123214569900000,8000000000000000,0000000000000000) AND *+(7ff0000000000000,8000000000000000,8000000000000000) => 0123214569900000 7ff0000000000000
+#11: xvmaddadp *+(7ff7ffffffffffff,8000000000000000,7ff0000000000000) AND *+(7ff8000000000000,8000000000000000,fff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvmaddadp *+(fff0000000000000,0000000000000000,7ff7ffffffffffff) AND *+(c0d0650f5a07b353,0000000000000000,fff7ffffffffffff) => 7fffffffffffffff ffffffffffffffff
+#13: xvmaddadp *+(8000000000000000,0000000000000000,7ff8000000000000) AND *+(0000000000000000,0000000000000000,fff8000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvmaddadp *+(0123214569900000,0000000000000000,8008340000078000) AND *+(7ff0000000000000,0000000000000000,c0d0650f5a07b353) => 0123214569900000 7ff0000000000000
+#15: xvmaddadp *+(7ff7ffffffffffff,0000000000000000,3fd8000000000000) AND *+(7ff8000000000000,0000000000000000,404f000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvmaddadp *+(fff0000000000000,0123214569900000,0018000000b77501) AND *+(c0d0650f5a07b353,0123214569900000,7fe800000000051b) => fff0000000000000 411bab9728b78ae5
+#17: xvmaddadp *+(8000000000000000,0123214569900000,0123214569900000) AND *+(0000000000000000,0123214569900000,0000000000000000) => 0000000000000000 0000000000000000
+#18: xvmaddadp *+(404f000000000000,0123214569900000,8000000000000000) AND *+(7ff0000000000000,0123214569900000,7ff0000000000000) => 404f000000000000 7ff0000000000000
+#19: xvmaddadp *+(7ff7ffffffffffff,0123214569900000,fff0000000000000) AND *+(7ff8000000000000,0123214569900000,7ff7ffffffffffff) => 7fffffffffffffff 7ff8000000000000
+#20: xvmaddadp *+(fff0000000000000,7ff0000000000000,fff7ffffffffffff) AND *+(c0d0650f5a07b353,7ff0000000000000,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#21: xvmaddadp *+(8000000000000000,7ff0000000000000,fff8000000000000) AND *+(0000000000000000,7ff0000000000000,8008340000078000) => fff8000000000000 fff0000000000000
+#22: xvmaddadp *+(0123214569900000,7ff0000000000000,c0d0650f5a07b353) AND *+(7ff0000000000000,7ff0000000000000,41232585a9900000) => fff0000000000000 7ff0000000000000
+#23: xvmaddadp *+(7ff7ffffffffffff,7ff0000000000000,404f000000000000) AND *+(7ff8000000000000,7ff0000000000000,0018000000b77501) => 7fffffffffffffff 7ff8000000000000
+#24: xvmaddadp *+(fff0000000000000,fff7ffffffffffff,7fe800000000051b) AND *+(c0d0650f5a07b353,fff7ffffffffffff,0123214569900000) => ffffffffffffffff ffffffffffffffff
+#25: xvmaddadp *+(8000000000000000,fff8000000000000,0000000000000000) AND *+(0000000000000000,fff8000000000000,8000000000000000) => fff8000000000000 fff8000000000000
+#26: xvmaddadp *+(0123214569900000,fff7ffffffffffff,7ff0000000000000) AND *+(7ff0000000000000,fff7ffffffffffff,fff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvmaddadp *+(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND *+(7ff8000000000000,fff7ffffffffffff,fff7ffffffffffff) => ffffffffffffffff ffffffffffffffff
+#28: xvmaddadp *+(fff0000000000000,fff8000000000000,7ff8000000000000) AND *+(c0d0650f5a07b353,fff8000000000000,fff8000000000000) => fff8000000000000 fff8000000000000
+#29: xvmaddadp *+(8000000000000000,fff8000000000000,8008340000078000) AND *+(41382511a2000000,41232585a9900000,c0d0650f5a07b353) => fff8000000000000 c2039db3bbaae2d2
+#30: xvmaddadp *+(41382511a2000000,41232585a9900000,3fd8000000000000) AND *+(7ff8000000000000,7ff7ffffffffffff,404f000000000000) => 413bbc1ab1cb0000 7fffffffffffffff
+#31: xvmaddadp *+(7ff8000000000000,7ff8000000000000,0018000000b77501) AND *+(fff8000000000000,7ff8000000000000,7fe800000000051b) => 7ff8000000000000 7ff8000000000000
+
+#0: xvmaddmdp *+(3fd8000000000000,fff0000000000000,fff0000000000000) AND *+(404f000000000000,fff0000000000000,c0d0650f5a07b353) => fff0000000000000 fff0000000000000
+#1: xvmaddmdp *+(0018000000b77501,41232585a9900000,41382511a2000000) AND *+(7fe800000000051b,fff0000000000000,0000000000000000) => 41382511a2000000 fff0000000000000
+#2: xvmaddmdp *+(0123214569900000,fff0000000000000,0123214569900000) AND *+(0000000000000000,fff0000000000000,7ff0000000000000) => fff0000000000000 7ff8000000000000
+#3: xvmaddmdp *+(8000000000000000,fff0000000000000,7ff7ffffffffffff) AND *+(7ff0000000000000,fff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvmaddmdp *+(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND *+(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) => 7ff8000000000000 7fffffffffffffff
+#5: xvmaddmdp *+(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) AND *+(7ff8000000000000,c0d0650f5a07b353,0000000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvmaddmdp *+(fff8000000000000,c0d0650f5a07b353,0123214569900000) AND *+(8008340000078000,c0d0650f5a07b353,7ff0000000000000) => fff8000000000000 7ff0000000000000
+#7: xvmaddmdp *+(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) AND *+(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#8: xvmaddmdp *+(404f000000000000,8000000000000000,fff0000000000000) AND *+(0018000000b77501,8000000000000000,c0d0650f5a07b353) => fff0000000000000 c0d0650f5a07b353
+#9: xvmaddmdp *+(7fe800000000051b,8000000000000000,8000000000000000) AND *+(0123214569900000,8000000000000000,0000000000000000) => 8000000000000000 0000000000000000
+#10: xvmaddmdp *+(0000000000000000,8000000000000000,0123214569900000) AND *+(8000000000000000,8000000000000000,7ff0000000000000) => 0123214569900000 7ff0000000000000
+#11: xvmaddmdp *+(7ff0000000000000,8000000000000000,7ff7ffffffffffff) AND *+(fff0000000000000,8000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvmaddmdp *+(7ff7ffffffffffff,0000000000000000,fff0000000000000) AND *+(fff7ffffffffffff,0000000000000000,c0d0650f5a07b353) => 7fffffffffffffff ffffffffffffffff
+#13: xvmaddmdp *+(7ff8000000000000,0000000000000000,8000000000000000) AND *+(fff8000000000000,0000000000000000,0000000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvmaddmdp *+(8008340000078000,0000000000000000,0123214569900000) AND *+(c0d0650f5a07b353,0000000000000000,7ff0000000000000) => 0123214569900000 7ff0000000000000
+#15: xvmaddmdp *+(3fd8000000000000,0000000000000000,7ff7ffffffffffff) AND *+(404f000000000000,0000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvmaddmdp *+(0018000000b77501,0123214569900000,fff0000000000000) AND *+(7fe800000000051b,0123214569900000,c0d0650f5a07b353) => fff0000000000000 411bab9728b78ae5
+#17: xvmaddmdp *+(0123214569900000,0123214569900000,8000000000000000) AND *+(0000000000000000,0123214569900000,0000000000000000) => 0000000000000000 0000000000000000
+#18: xvmaddmdp *+(8000000000000000,0123214569900000,404f000000000000) AND *+(7ff0000000000000,0123214569900000,7ff0000000000000) => 404f000000000000 7ff0000000000000
+#19: xvmaddmdp *+(fff0000000000000,0123214569900000,7ff7ffffffffffff) AND *+(7ff7ffffffffffff,0123214569900000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#20: xvmaddmdp *+(fff7ffffffffffff,7ff0000000000000,fff0000000000000) AND *+(7ff8000000000000,7ff0000000000000,c0d0650f5a07b353) => ffffffffffffffff 7ff8000000000000
+#21: xvmaddmdp *+(fff8000000000000,7ff0000000000000,8000000000000000) AND *+(8008340000078000,7ff0000000000000,0000000000000000) => fff8000000000000 fff0000000000000
+#22: xvmaddmdp *+(c0d0650f5a07b353,7ff0000000000000,0123214569900000) AND *+(41232585a9900000,7ff0000000000000,7ff0000000000000) => fff0000000000000 7ff0000000000000
+#23: xvmaddmdp *+(404f000000000000,7ff0000000000000,7ff7ffffffffffff) AND *+(0018000000b77501,7ff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#24: xvmaddmdp *+(7fe800000000051b,fff7ffffffffffff,fff0000000000000) AND *+(0123214569900000,fff7ffffffffffff,c0d0650f5a07b353) => ffffffffffffffff ffffffffffffffff
+#25: xvmaddmdp *+(0000000000000000,fff8000000000000,8000000000000000) AND *+(8000000000000000,fff8000000000000,0000000000000000) => fff8000000000000 fff8000000000000
+#26: xvmaddmdp *+(7ff0000000000000,fff7ffffffffffff,0123214569900000) AND *+(fff0000000000000,fff7ffffffffffff,7ff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvmaddmdp *+(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND *+(fff7ffffffffffff,fff7ffffffffffff,7ff8000000000000) => ffffffffffffffff ffffffffffffffff
+#28: xvmaddmdp *+(7ff8000000000000,fff8000000000000,fff0000000000000) AND *+(fff8000000000000,fff8000000000000,c0d0650f5a07b353) => fff8000000000000 fff8000000000000
+#29: xvmaddmdp *+(8008340000078000,fff8000000000000,8000000000000000) AND *+(c0d0650f5a07b353,41232585a9900000,41382511a2000000) => fff8000000000000 c2039db3bbaae2d2
+#30: xvmaddmdp *+(3fd8000000000000,41232585a9900000,41382511a2000000) AND *+(404f000000000000,7ff7ffffffffffff,7ff8000000000000) => 413bbc1ab1cb0000 7fffffffffffffff
+#31: xvmaddmdp *+(0018000000b77501,7ff8000000000000,7ff8000000000000) AND *+(7fe800000000051b,7ff8000000000000,fff8000000000000) => 7ff8000000000000 7ff8000000000000
+
+#0: xvmaddasp *+(ff800000,ff800000,3ec00000) AND *+(c683287b,ff800000,42780000) AND *+(49c1288d,49192c2d,00000000) AND *+(00000000,ff800000,7f800000) => ff800000 ff800000 49c1288d ff800000
+#1: xvmaddasp *+(00000000,ff800000,00000000) AND *+(7f800000,ff800000,00000000) AND *+(7fffffff,ff800000,80000000) AND *+(7fc00000,ff800000,7f800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvmaddasp *+(ff800000,c683287b,ff800000) AND *+(c683287b,c683287b,7fffffff) AND *+(80000000,c683287b,ffffffff) AND *+(00000000,c683287b,7fc00000) => 7fc00000 7fffffff ffffffff 7fc00000
+#3: xvmaddasp *+(00000000,c683287b,ffc00000) AND *+(7f800000,c683287b,80000000) AND *+(7fffffff,c683287b,c683287b) AND *+(7fc00000,c683287b,49192c2d) => ffc00000 7f800000 7fffffff 7fc00000
+#4: xvmaddasp *+(ff800000,80000000,7f800000) AND *+(c683287b,80000000,00000000) AND *+(80000000,80000000,00000000) AND *+(00000000,80000000,80000000) => 7fc00000 c683287b 80000000 00000000
+#5: xvmaddasp *+(00000000,80000000,7f800000) AND *+(7f800000,80000000,ff800000) AND *+(7fffffff,80000000,7fffffff) AND *+(7fc00000,80000000,ffffffff) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvmaddasp *+(ff800000,00000000,7fc00000) AND *+(c683287b,00000000,ffc00000) AND *+(80000000,00000000,80000000) AND *+(00000000,00000000,c683287b) => 7fc00000 ffc00000 80000000 00000000
+#7: xvmaddasp *+(00000000,00000000,00000000) AND *+(7f800000,00000000,7f800000) AND *+(7fffffff,00000000,00000000) AND *+(7fc00000,00000000,00000000) => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmaddasp *+(ff800000,00000000,80000000) AND *+(c683287b,00000000,7f800000) AND *+(80000000,00000000,ff800000) AND *+(00000000,00000000,7fffffff) => ff800000 7fc00000 7fc00000 7fffffff
+#9: xvmaddasp *+(42780000,00000000,ffffffff) AND *+(7f800000,00000000,7fc00000) AND *+(7fffffff,00000000,ffc00000) AND *+(7fc00000,00000000,80000000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvmaddasp *+(ff800000,7f800000,42780000) AND *+(c683287b,7f800000,00000000) AND *+(80000000,7f800000,7f800000) AND *+(00000000,7f800000,00000000) => 7fc00000 7fc00000 7f800000 7fc00000
+#11: xvmaddasp *+(00000000,7f800000,00000000) AND *+(7f800000,7f800000,80000000) AND *+(7fffffff,7f800000,7f800000) AND *+(7fc00000,7f800000,ff800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvmaddasp *+(ff800000,ffffffff,7fffffff) AND *+(c683287b,ffffffff,ffffffff) AND *+(80000000,ffc00000,7fc00000) AND *+(00000000,ffc00000,ffc00000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmaddasp *+(00000000,ffffffff,3ec00000) AND *+(7f800000,ffffffff,42780000) AND *+(7fffffff,ffffffff,00000000) AND *+(7fc00000,ffffffff,7f800000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvmaddasp *+(ff800000,ffc00000,00000000) AND *+(c683287b,ffc00000,00000000) AND *+(80000000,ffc00000,80000000) AND *+(49c1288d,49192c2d,7f800000) => ffc00000 ffc00000 ffc00000 7f800000
+#15: xvmaddasp *+(49c1288d,49192c2d,ff800000) AND *+(7fc00000,7fffffff,7fffffff) AND *+(7fc00000,7fc00000,ffffffff) AND *+(ffc00000,7fc00000,7fc00000) => ff800000 7fffffff 7fc00000 7fc00000
+
+#0: xvmaddmsp *+(3ec00000,ff800000,ff800000) AND *+(42780000,ff800000,c683287b) AND *+(00000000,49192c2d,49c1288d) AND *+(7f800000,ff800000,00000000) => ff800000 ff800000 49c1288d ff800000
+#1: xvmaddmsp *+(00000000,ff800000,00000000) AND *+(00000000,ff800000,7f800000) AND *+(80000000,ff800000,7fffffff) AND *+(7f800000,ff800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvmaddmsp *+(ff800000,c683287b,ff800000) AND *+(7fffffff,c683287b,c683287b) AND *+(ffffffff,c683287b,80000000) AND *+(7fc00000,c683287b,00000000) => 7fc00000 7fffffff ffffffff 7fc00000
+#3: xvmaddmsp *+(ffc00000,c683287b,00000000) AND *+(80000000,c683287b,7f800000) AND *+(c683287b,c683287b,7fffffff) AND *+(49192c2d,c683287b,7fc00000) => ffc00000 7f800000 7fffffff 7fc00000
+#4: xvmaddmsp *+(7f800000,80000000,ff800000) AND *+(00000000,80000000,c683287b) AND *+(00000000,80000000,80000000) AND *+(80000000,80000000,00000000) => 7fc00000 c683287b 80000000 00000000
+#5: xvmaddmsp *+(7f800000,80000000,00000000) AND *+(ff800000,80000000,7f800000) AND *+(7fffffff,80000000,7fffffff) AND *+(ffffffff,80000000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvmaddmsp *+(7fc00000,00000000,ff800000) AND *+(ffc00000,00000000,c683287b) AND *+(80000000,00000000,80000000) AND *+(c683287b,00000000,00000000) => 7fc00000 ffc00000 80000000 00000000
+#7: xvmaddmsp *+(00000000,00000000,00000000) AND *+(7f800000,00000000,7f800000) AND *+(00000000,00000000,7fffffff) AND *+(00000000,00000000,7fc00000) => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmaddmsp *+(80000000,00000000,ff800000) AND *+(7f800000,00000000,c683287b) AND *+(ff800000,00000000,80000000) AND *+(7fffffff,00000000,00000000) => ff800000 7fc00000 7fc00000 7fffffff
+#9: xvmaddmsp *+(ffffffff,00000000,42780000) AND *+(7fc00000,00000000,7f800000) AND *+(ffc00000,00000000,7fffffff) AND *+(80000000,00000000,7fc00000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvmaddmsp *+(42780000,7f800000,ff800000) AND *+(00000000,7f800000,c683287b) AND *+(7f800000,7f800000,80000000) AND *+(00000000,7f800000,00000000) => 7fc00000 7fc00000 7f800000 7fc00000
+#11: xvmaddmsp *+(00000000,7f800000,00000000) AND *+(80000000,7f800000,7f800000) AND *+(7f800000,7f800000,7fffffff) AND *+(ff800000,7f800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvmaddmsp *+(7fffffff,ffffffff,ff800000) AND *+(ffffffff,ffffffff,c683287b) AND *+(7fc00000,ffc00000,80000000) AND *+(ffc00000,ffc00000,00000000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmaddmsp *+(3ec00000,ffffffff,00000000) AND *+(42780000,ffffffff,7f800000) AND *+(00000000,ffffffff,7fffffff) AND *+(7f800000,ffffffff,7fc00000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvmaddmsp *+(00000000,ffc00000,ff800000) AND *+(00000000,ffc00000,c683287b) AND *+(80000000,ffc00000,80000000) AND *+(7f800000,49192c2d,49c1288d) => ffc00000 ffc00000 ffc00000 7f800000
+#15: xvmaddmsp *+(ff800000,49192c2d,49c1288d) AND *+(7fffffff,7fffffff,7fc00000) AND *+(ffffffff,7fc00000,7fc00000) AND *+(7fc00000,7fc00000,ffc00000) => ff800000 7fffffff 7fc00000 7fc00000
+
+#0: xvnmaddadp !*+(fff0000000000000,fff0000000000000,3fd8000000000000) AND !*+(c0d0650f5a07b353,fff0000000000000,404f000000000000) => 7ff0000000000000 7ff0000000000000
+#1: xvnmaddadp !*+(41382511a2000000,41232585a9900000,0018000000b77501) AND !*+(0000000000000000,fff0000000000000,7fe800000000051b) => c1382511a2000000 7ff0000000000000
+#2: xvnmaddadp !*+(0123214569900000,fff0000000000000,0123214569900000) AND !*+(7ff0000000000000,fff0000000000000,0000000000000000) => 7ff0000000000000 7ff8000000000000
+#3: xvnmaddadp !*+(7ff7ffffffffffff,fff0000000000000,8000000000000000) AND !*+(7ff8000000000000,fff0000000000000,7ff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvnmaddadp !*+(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND !*+(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) => 7ff8000000000000 7fffffffffffffff
+#5: xvnmaddadp !*+(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) AND !*+(0000000000000000,c0d0650f5a07b353,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvnmaddadp !*+(0123214569900000,c0d0650f5a07b353,fff8000000000000) AND !*+(7ff0000000000000,c0d0650f5a07b353,8008340000078000) => fff8000000000000 fff0000000000000
+#7: xvnmaddadp !*+(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) AND !*+(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) => 7fffffffffffffff 7ff8000000000000
+#8: xvnmaddadp !*+(fff0000000000000,8000000000000000,404f000000000000) AND !*+(c0d0650f5a07b353,8000000000000000,0018000000b77501) => 7ff0000000000000 40d0650f5a07b353
+#9: xvnmaddadp !*+(8000000000000000,8000000000000000,7fe800000000051b) AND !*+(0000000000000000,8000000000000000,0123214569900000) => 0000000000000000 8000000000000000
+#10: xvnmaddadp !*+(0123214569900000,8000000000000000,0000000000000000) AND !*+(7ff0000000000000,8000000000000000,8000000000000000) => 8123214569900000 fff0000000000000
+#11: xvnmaddadp !*+(7ff7ffffffffffff,8000000000000000,7ff0000000000000) AND !*+(7ff8000000000000,8000000000000000,fff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvnmaddadp !*+(fff0000000000000,0000000000000000,7ff7ffffffffffff) AND !*+(c0d0650f5a07b353,0000000000000000,fff7ffffffffffff) => 7fffffffffffffff ffffffffffffffff
+#13: xvnmaddadp !*+(8000000000000000,0000000000000000,7ff8000000000000) AND !*+(0000000000000000,0000000000000000,fff8000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvnmaddadp !*+(0123214569900000,0000000000000000,8008340000078000) AND !*+(7ff0000000000000,0000000000000000,c0d0650f5a07b353) => 8123214569900000 fff0000000000000
+#15: xvnmaddadp !*+(7ff7ffffffffffff,0000000000000000,3fd8000000000000) AND !*+(7ff8000000000000,0000000000000000,404f000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvnmaddadp !*+(fff0000000000000,0123214569900000,0018000000b77501) AND !*+(c0d0650f5a07b353,0123214569900000,7fe800000000051b) => 7ff0000000000000 c11bab9728b78ae5
+#17: xvnmaddadp !*+(8000000000000000,0123214569900000,0123214569900000) AND !*+(0000000000000000,0123214569900000,0000000000000000) => 8000000000000000 8000000000000000
+#18: xvnmaddadp !*+(404f000000000000,0123214569900000,8000000000000000) AND !*+(7ff0000000000000,0123214569900000,7ff0000000000000) => c04f000000000000 fff0000000000000
+#19: xvnmaddadp !*+(7ff7ffffffffffff,0123214569900000,fff0000000000000) AND !*+(7ff8000000000000,0123214569900000,7ff7ffffffffffff) => 7fffffffffffffff 7ff8000000000000
+#20: xvnmaddadp !*+(fff0000000000000,7ff0000000000000,fff7ffffffffffff) AND !*+(c0d0650f5a07b353,7ff0000000000000,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#21: xvnmaddadp !*+(8000000000000000,7ff0000000000000,fff8000000000000) AND !*+(0000000000000000,7ff0000000000000,8008340000078000) => fff8000000000000 7ff0000000000000
+#22: xvnmaddadp !*+(0123214569900000,7ff0000000000000,c0d0650f5a07b353) AND !*+(7ff0000000000000,7ff0000000000000,41232585a9900000) => 7ff0000000000000 fff0000000000000
+#23: xvnmaddadp !*+(7ff7ffffffffffff,7ff0000000000000,404f000000000000) AND !*+(7ff8000000000000,7ff0000000000000,0018000000b77501) => 7fffffffffffffff 7ff8000000000000
+#24: xvnmaddadp !*+(fff0000000000000,fff7ffffffffffff,7fe800000000051b) AND !*+(c0d0650f5a07b353,fff7ffffffffffff,0123214569900000) => ffffffffffffffff ffffffffffffffff
+#25: xvnmaddadp !*+(8000000000000000,fff8000000000000,0000000000000000) AND !*+(0000000000000000,fff8000000000000,8000000000000000) => fff8000000000000 fff8000000000000
+#26: xvnmaddadp !*+(0123214569900000,fff7ffffffffffff,7ff0000000000000) AND !*+(7ff0000000000000,fff7ffffffffffff,fff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvnmaddadp !*+(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND !*+(7ff8000000000000,fff7ffffffffffff,fff7ffffffffffff) => ffffffffffffffff ffffffffffffffff
+#28: xvnmaddadp !*+(fff0000000000000,fff8000000000000,7ff8000000000000) AND !*+(c0d0650f5a07b353,fff8000000000000,fff8000000000000) => fff8000000000000 fff8000000000000
+#29: xvnmaddadp !*+(8000000000000000,fff8000000000000,8008340000078000) AND !*+(41382511a2000000,41232585a9900000,c0d0650f5a07b353) => fff8000000000000 42039db3bbaae2d2
+#30: xvnmaddadp !*+(41382511a2000000,41232585a9900000,3fd8000000000000) AND !*+(7ff8000000000000,7ff7ffffffffffff,404f000000000000) => c13bbc1ab1cb0000 7fffffffffffffff
+#31: xvnmaddadp !*+(7ff8000000000000,7ff8000000000000,0018000000b77501) AND !*+(fff8000000000000,7ff8000000000000,7fe800000000051b) => 7ff8000000000000 7ff8000000000000
+
+#0: xvnmaddmdp !*+(3fd8000000000000,fff0000000000000,fff0000000000000) AND !*+(404f000000000000,fff0000000000000,c0d0650f5a07b353) => 7ff0000000000000 7ff0000000000000
+#1: xvnmaddmdp !*+(0018000000b77501,41232585a9900000,41382511a2000000) AND !*+(7fe800000000051b,fff0000000000000,0000000000000000) => c1382511a2000000 7ff0000000000000
+#2: xvnmaddmdp !*+(0123214569900000,fff0000000000000,0123214569900000) AND !*+(0000000000000000,fff0000000000000,7ff0000000000000) => 7ff0000000000000 7ff8000000000000
+#3: xvnmaddmdp !*+(8000000000000000,fff0000000000000,7ff7ffffffffffff) AND !*+(7ff0000000000000,fff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvnmaddmdp !*+(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND !*+(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) => 7ff8000000000000 7fffffffffffffff
+#5: xvnmaddmdp !*+(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) AND !*+(7ff8000000000000,c0d0650f5a07b353,0000000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvnmaddmdp !*+(fff8000000000000,c0d0650f5a07b353,0123214569900000) AND !*+(8008340000078000,c0d0650f5a07b353,7ff0000000000000) => fff8000000000000 fff0000000000000
+#7: xvnmaddmdp !*+(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) AND !*+(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#8: xvnmaddmdp !*+(404f000000000000,8000000000000000,fff0000000000000) AND !*+(0018000000b77501,8000000000000000,c0d0650f5a07b353) => 7ff0000000000000 40d0650f5a07b353
+#9: xvnmaddmdp !*+(7fe800000000051b,8000000000000000,8000000000000000) AND !*+(0123214569900000,8000000000000000,0000000000000000) => 0000000000000000 8000000000000000
+#10: xvnmaddmdp !*+(0000000000000000,8000000000000000,0123214569900000) AND !*+(8000000000000000,8000000000000000,7ff0000000000000) => 8123214569900000 fff0000000000000
+#11: xvnmaddmdp !*+(7ff0000000000000,8000000000000000,7ff7ffffffffffff) AND !*+(fff0000000000000,8000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvnmaddmdp !*+(7ff7ffffffffffff,0000000000000000,fff0000000000000) AND !*+(fff7ffffffffffff,0000000000000000,c0d0650f5a07b353) => 7fffffffffffffff ffffffffffffffff
+#13: xvnmaddmdp !*+(7ff8000000000000,0000000000000000,8000000000000000) AND !*+(fff8000000000000,0000000000000000,0000000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvnmaddmdp !*+(8008340000078000,0000000000000000,0123214569900000) AND !*+(c0d0650f5a07b353,0000000000000000,7ff0000000000000) => 8123214569900000 fff0000000000000
+#15: xvnmaddmdp !*+(3fd8000000000000,0000000000000000,7ff7ffffffffffff) AND !*+(404f000000000000,0000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvnmaddmdp !*+(0018000000b77501,0123214569900000,fff0000000000000) AND !*+(7fe800000000051b,0123214569900000,c0d0650f5a07b353) => 7ff0000000000000 c11bab9728b78ae5
+#17: xvnmaddmdp !*+(0123214569900000,0123214569900000,8000000000000000) AND !*+(0000000000000000,0123214569900000,0000000000000000) => 8000000000000000 8000000000000000
+#18: xvnmaddmdp !*+(8000000000000000,0123214569900000,404f000000000000) AND !*+(7ff0000000000000,0123214569900000,7ff0000000000000) => c04f000000000000 fff0000000000000
+#19: xvnmaddmdp !*+(fff0000000000000,0123214569900000,7ff7ffffffffffff) AND !*+(7ff7ffffffffffff,0123214569900000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#20: xvnmaddmdp !*+(fff7ffffffffffff,7ff0000000000000,fff0000000000000) AND !*+(7ff8000000000000,7ff0000000000000,c0d0650f5a07b353) => ffffffffffffffff 7ff8000000000000
+#21: xvnmaddmdp !*+(fff8000000000000,7ff0000000000000,8000000000000000) AND !*+(8008340000078000,7ff0000000000000,0000000000000000) => fff8000000000000 7ff0000000000000
+#22: xvnmaddmdp !*+(c0d0650f5a07b353,7ff0000000000000,0123214569900000) AND !*+(41232585a9900000,7ff0000000000000,7ff0000000000000) => 7ff0000000000000 fff0000000000000
+#23: xvnmaddmdp !*+(404f000000000000,7ff0000000000000,7ff7ffffffffffff) AND !*+(0018000000b77501,7ff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#24: xvnmaddmdp !*+(7fe800000000051b,fff7ffffffffffff,fff0000000000000) AND !*+(0123214569900000,fff7ffffffffffff,c0d0650f5a07b353) => ffffffffffffffff ffffffffffffffff
+#25: xvnmaddmdp !*+(0000000000000000,fff8000000000000,8000000000000000) AND !*+(8000000000000000,fff8000000000000,0000000000000000) => fff8000000000000 fff8000000000000
+#26: xvnmaddmdp !*+(7ff0000000000000,fff7ffffffffffff,0123214569900000) AND !*+(fff0000000000000,fff7ffffffffffff,7ff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvnmaddmdp !*+(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND !*+(fff7ffffffffffff,fff7ffffffffffff,7ff8000000000000) => ffffffffffffffff ffffffffffffffff
+#28: xvnmaddmdp !*+(7ff8000000000000,fff8000000000000,fff0000000000000) AND !*+(fff8000000000000,fff8000000000000,c0d0650f5a07b353) => fff8000000000000 fff8000000000000
+#29: xvnmaddmdp !*+(8008340000078000,fff8000000000000,8000000000000000) AND !*+(c0d0650f5a07b353,41232585a9900000,41382511a2000000) => fff8000000000000 42039db3bbaae2d2
+#30: xvnmaddmdp !*+(3fd8000000000000,41232585a9900000,41382511a2000000) AND !*+(404f000000000000,7ff7ffffffffffff,7ff8000000000000) => c13bbc1ab1cb0000 7fffffffffffffff
+#31: xvnmaddmdp !*+(0018000000b77501,7ff8000000000000,7ff8000000000000) AND !*+(7fe800000000051b,7ff8000000000000,fff8000000000000) => 7ff8000000000000 7ff8000000000000
+
+#0: xvnmaddasp !*+(ff800000,ff800000,3ec00000) AND !*+(c683287b,ff800000,42780000) AND !*+(49c1288d,49192c2d,00000000) AND !*+(00000000,ff800000,7f800000) => 7f800000 7f800000 c9c1288d 7f800000
+#1: xvnmaddasp !*+(00000000,ff800000,00000000) AND !*+(7f800000,ff800000,00000000) AND !*+(7fffffff,ff800000,80000000) AND !*+(7fc00000,ff800000,7f800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvnmaddasp !*+(ff800000,c683287b,ff800000) AND !*+(c683287b,c683287b,7fffffff) AND !*+(80000000,c683287b,ffffffff) AND !*+(00000000,c683287b,7fc00000) => 7fc00000 7fffffff ffffffff 7fc00000
+#3: xvnmaddasp !*+(00000000,c683287b,ffc00000) AND !*+(7f800000,c683287b,80000000) AND !*+(7fffffff,c683287b,c683287b) AND !*+(7fc00000,c683287b,49192c2d) => ffc00000 ff800000 7fffffff 7fc00000
+#4: xvnmaddasp !*+(ff800000,80000000,7f800000) AND !*+(c683287b,80000000,00000000) AND !*+(80000000,80000000,00000000) AND !*+(00000000,80000000,80000000) => 7fc00000 4683287b 00000000 80000000
+#5: xvnmaddasp !*+(00000000,80000000,7f800000) AND !*+(7f800000,80000000,ff800000) AND !*+(7fffffff,80000000,7fffffff) AND !*+(7fc00000,80000000,ffffffff) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvnmaddasp !*+(ff800000,00000000,7fc00000) AND !*+(c683287b,00000000,ffc00000) AND !*+(80000000,00000000,80000000) AND !*+(00000000,00000000,c683287b) => 7fc00000 ffc00000 00000000 80000000
+#7: xvnmaddasp !*+(00000000,00000000,00000000) AND !*+(7f800000,00000000,7f800000) AND !*+(7fffffff,00000000,00000000) AND !*+(7fc00000,00000000,00000000) => 80000000 7fc00000 7fffffff 7fc00000
+#8: xvnmaddasp !*+(ff800000,00000000,80000000) AND !*+(c683287b,00000000,7f800000) AND !*+(80000000,00000000,ff800000) AND !*+(00000000,00000000,7fffffff) => 7f800000 7fc00000 7fc00000 7fffffff
+#9: xvnmaddasp !*+(42780000,00000000,ffffffff) AND !*+(7f800000,00000000,7fc00000) AND !*+(7fffffff,00000000,ffc00000) AND !*+(7fc00000,00000000,80000000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvnmaddasp !*+(ff800000,7f800000,42780000) AND !*+(c683287b,7f800000,00000000) AND !*+(80000000,7f800000,7f800000) AND !*+(00000000,7f800000,00000000) => 7fc00000 7fc00000 ff800000 7fc00000
+#11: xvnmaddasp !*+(00000000,7f800000,00000000) AND !*+(7f800000,7f800000,80000000) AND !*+(7fffffff,7f800000,7f800000) AND !*+(7fc00000,7f800000,ff800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvnmaddasp !*+(ff800000,ffffffff,7fffffff) AND !*+(c683287b,ffffffff,ffffffff) AND !*+(80000000,ffc00000,7fc00000) AND !*+(00000000,ffc00000,ffc00000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvnmaddasp !*+(00000000,ffffffff,3ec00000) AND !*+(7f800000,ffffffff,42780000) AND !*+(7fffffff,ffffffff,00000000) AND !*+(7fc00000,ffffffff,7f800000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvnmaddasp !*+(ff800000,ffc00000,00000000) AND !*+(c683287b,ffc00000,00000000) AND !*+(80000000,ffc00000,80000000) AND !*+(49c1288d,49192c2d,7f800000) => ffc00000 ffc00000 ffc00000 ff800000
+#15: xvnmaddasp !*+(49c1288d,49192c2d,ff800000) AND !*+(7fc00000,7fffffff,7fffffff) AND !*+(7fc00000,7fc00000,ffffffff) AND !*+(ffc00000,7fc00000,7fc00000) => 7f800000 7fffffff 7fc00000 7fc00000
+
+#0: xvnmaddmsp !*+(3ec00000,ff800000,ff800000) AND !*+(42780000,ff800000,c683287b) AND !*+(00000000,49192c2d,49c1288d) AND !*+(7f800000,ff800000,00000000) => 7f800000 7f800000 c9c1288d 7f800000
+#1: xvnmaddmsp !*+(00000000,ff800000,00000000) AND !*+(00000000,ff800000,7f800000) AND !*+(80000000,ff800000,7fffffff) AND !*+(7f800000,ff800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvnmaddmsp !*+(ff800000,c683287b,ff800000) AND !*+(7fffffff,c683287b,c683287b) AND !*+(ffffffff,c683287b,80000000) AND !*+(7fc00000,c683287b,00000000) => 7fc00000 7fffffff ffffffff 7fc00000
+#3: xvnmaddmsp !*+(ffc00000,c683287b,00000000) AND !*+(80000000,c683287b,7f800000) AND !*+(c683287b,c683287b,7fffffff) AND !*+(49192c2d,c683287b,7fc00000) => ffc00000 ff800000 7fffffff 7fc00000
+#4: xvnmaddmsp !*+(7f800000,80000000,ff800000) AND !*+(00000000,80000000,c683287b) AND !*+(00000000,80000000,80000000) AND !*+(80000000,80000000,00000000) => 7fc00000 4683287b 00000000 80000000
+#5: xvnmaddmsp !*+(7f800000,80000000,00000000) AND !*+(ff800000,80000000,7f800000) AND !*+(7fffffff,80000000,7fffffff) AND !*+(ffffffff,80000000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvnmaddmsp !*+(7fc00000,00000000,ff800000) AND !*+(ffc00000,00000000,c683287b) AND !*+(80000000,00000000,80000000) AND !*+(c683287b,00000000,00000000) => 7fc00000 ffc00000 00000000 80000000
+#7: xvnmaddmsp !*+(00000000,00000000,00000000) AND !*+(7f800000,00000000,7f800000) AND !*+(00000000,00000000,7fffffff) AND !*+(00000000,00000000,7fc00000) => 80000000 7fc00000 7fffffff 7fc00000
+#8: xvnmaddmsp !*+(80000000,00000000,ff800000) AND !*+(7f800000,00000000,c683287b) AND !*+(ff800000,00000000,80000000) AND !*+(7fffffff,00000000,00000000) => 7f800000 7fc00000 7fc00000 7fffffff
+#9: xvnmaddmsp !*+(ffffffff,00000000,42780000) AND !*+(7fc00000,00000000,7f800000) AND !*+(ffc00000,00000000,7fffffff) AND !*+(80000000,00000000,7fc00000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvnmaddmsp !*+(42780000,7f800000,ff800000) AND !*+(00000000,7f800000,c683287b) AND !*+(7f800000,7f800000,80000000) AND !*+(00000000,7f800000,00000000) => 7fc00000 7fc00000 ff800000 7fc00000
+#11: xvnmaddmsp !*+(00000000,7f800000,00000000) AND !*+(80000000,7f800000,7f800000) AND !*+(7f800000,7f800000,7fffffff) AND !*+(ff800000,7f800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvnmaddmsp !*+(7fffffff,ffffffff,ff800000) AND !*+(ffffffff,ffffffff,c683287b) AND !*+(7fc00000,ffc00000,80000000) AND !*+(ffc00000,ffc00000,00000000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvnmaddmsp !*+(3ec00000,ffffffff,00000000) AND !*+(42780000,ffffffff,7f800000) AND !*+(00000000,ffffffff,7fffffff) AND !*+(7f800000,ffffffff,7fc00000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvnmaddmsp !*+(00000000,ffc00000,ff800000) AND !*+(00000000,ffc00000,c683287b) AND !*+(80000000,ffc00000,80000000) AND !*+(7f800000,49192c2d,49c1288d) => ffc00000 ffc00000 ffc00000 ff800000
+#15: xvnmaddmsp !*+(ff800000,49192c2d,49c1288d) AND !*+(7fffffff,7fffffff,7fc00000) AND !*+(ffffffff,7fc00000,7fc00000) AND !*+(7fc00000,7fc00000,ffc00000) => 7f800000 7fffffff 7fc00000 7fc00000
+
+#0: xvmsubadp *-(fff0000000000000,fff0000000000000,3fd8000000000000) AND *-(c0d0650f5a07b353,fff0000000000000,404f000000000000) => 7ff8000000000000 fff0000000000000
+#1: xvmsubadp *-(41382511a2000000,41232585a9900000,0018000000b77501) AND *-(0000000000000000,fff0000000000000,7fe800000000051b) => c1382511a2000000 fff0000000000000
+#2: xvmsubadp *-(0123214569900000,fff0000000000000,0123214569900000) AND *-(7ff0000000000000,fff0000000000000,0000000000000000) => fff0000000000000 7ff8000000000000
+#3: xvmsubadp *-(7ff7ffffffffffff,fff0000000000000,8000000000000000) AND *-(7ff8000000000000,fff0000000000000,7ff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvmsubadp *-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND *-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) => 7ff0000000000000 7fffffffffffffff
+#5: xvmsubadp *-(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) AND *-(0000000000000000,c0d0650f5a07b353,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvmsubadp *-(0123214569900000,c0d0650f5a07b353,fff8000000000000) AND *-(7ff0000000000000,c0d0650f5a07b353,8008340000078000) => fff8000000000000 fff0000000000000
+#7: xvmsubadp *-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) AND *-(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) => 7fffffffffffffff 7ff8000000000000
+#8: xvmsubadp *-(fff0000000000000,8000000000000000,404f000000000000) AND *-(c0d0650f5a07b353,8000000000000000,0018000000b77501) => 7ff0000000000000 40d0650f5a07b353
+#9: xvmsubadp *-(8000000000000000,8000000000000000,7fe800000000051b) AND *-(0000000000000000,8000000000000000,0123214569900000) => 0000000000000000 8000000000000000
+#10: xvmsubadp *-(0123214569900000,8000000000000000,0000000000000000) AND *-(7ff0000000000000,8000000000000000,8000000000000000) => 8123214569900000 fff0000000000000
+#11: xvmsubadp *-(7ff7ffffffffffff,8000000000000000,7ff0000000000000) AND *-(7ff8000000000000,8000000000000000,fff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvmsubadp *-(fff0000000000000,0000000000000000,7ff7ffffffffffff) AND *-(c0d0650f5a07b353,0000000000000000,fff7ffffffffffff) => 7fffffffffffffff ffffffffffffffff
+#13: xvmsubadp *-(8000000000000000,0000000000000000,7ff8000000000000) AND *-(0000000000000000,0000000000000000,fff8000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvmsubadp *-(0123214569900000,0000000000000000,8008340000078000) AND *-(7ff0000000000000,0000000000000000,c0d0650f5a07b353) => 8123214569900000 fff0000000000000
+#15: xvmsubadp *-(7ff7ffffffffffff,0000000000000000,3fd8000000000000) AND *-(7ff8000000000000,0000000000000000,404f000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvmsubadp *-(fff0000000000000,0123214569900000,0018000000b77501) AND *-(c0d0650f5a07b353,0123214569900000,7fe800000000051b) => 7ff0000000000000 411db83913f88150
+#17: xvmsubadp *-(8000000000000000,0123214569900000,0123214569900000) AND *-(0000000000000000,0123214569900000,0000000000000000) => 0000000000000000 0000000000000000
+#18: xvmsubadp *-(404f000000000000,0123214569900000,8000000000000000) AND *-(7ff0000000000000,0123214569900000,7ff0000000000000) => c04f000000000000 7ff8000000000000
+#19: xvmsubadp *-(7ff7ffffffffffff,0123214569900000,fff0000000000000) AND *-(7ff8000000000000,0123214569900000,7ff7ffffffffffff) => 7fffffffffffffff 7ff8000000000000
+#20: xvmsubadp *-(fff0000000000000,7ff0000000000000,fff7ffffffffffff) AND *-(c0d0650f5a07b353,7ff0000000000000,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#21: xvmsubadp *-(8000000000000000,7ff0000000000000,fff8000000000000) AND *-(0000000000000000,7ff0000000000000,8008340000078000) => fff8000000000000 fff0000000000000
+#22: xvmsubadp *-(0123214569900000,7ff0000000000000,c0d0650f5a07b353) AND *-(7ff0000000000000,7ff0000000000000,41232585a9900000) => fff0000000000000 7ff8000000000000
+#23: xvmsubadp *-(7ff7ffffffffffff,7ff0000000000000,404f000000000000) AND *-(7ff8000000000000,7ff0000000000000,0018000000b77501) => 7fffffffffffffff 7ff8000000000000
+#24: xvmsubadp *-(fff0000000000000,fff7ffffffffffff,7fe800000000051b) AND *-(c0d0650f5a07b353,fff7ffffffffffff,0123214569900000) => ffffffffffffffff ffffffffffffffff
+#25: xvmsubadp *-(8000000000000000,fff8000000000000,0000000000000000) AND *-(0000000000000000,fff8000000000000,8000000000000000) => fff8000000000000 fff8000000000000
+#26: xvmsubadp *-(0123214569900000,fff7ffffffffffff,7ff0000000000000) AND *-(7ff0000000000000,fff7ffffffffffff,fff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvmsubadp *-(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND *-(7ff8000000000000,fff7ffffffffffff,fff7ffffffffffff) => ffffffffffffffff ffffffffffffffff
+#28: xvmsubadp *-(fff0000000000000,fff8000000000000,7ff8000000000000) AND *-(c0d0650f5a07b353,fff8000000000000,fff8000000000000) => fff8000000000000 fff8000000000000
+#29: xvmsubadp *-(8000000000000000,fff8000000000000,8008340000078000) AND *-(41382511a2000000,41232585a9900000,c0d0650f5a07b353) => fff8000000000000 c2039f360cc502d2
+#30: xvmsubadp *-(41382511a2000000,41232585a9900000,3fd8000000000000) AND *-(7ff8000000000000,7ff7ffffffffffff,404f000000000000) => c1348e0892350000 7fffffffffffffff
+#31: xvmsubadp *-(7ff8000000000000,7ff8000000000000,0018000000b77501) AND *-(fff8000000000000,7ff8000000000000,7fe800000000051b) => 7ff8000000000000 7ff8000000000000
+
+#0: xvmsubmdp *-(3fd8000000000000,fff0000000000000,fff0000000000000) AND *-(404f000000000000,fff0000000000000,c0d0650f5a07b353) => 7ff8000000000000 fff0000000000000
+#1: xvmsubmdp *-(0018000000b77501,41232585a9900000,41382511a2000000) AND *-(7fe800000000051b,fff0000000000000,0000000000000000) => c1382511a2000000 fff0000000000000
+#2: xvmsubmdp *-(0123214569900000,fff0000000000000,0123214569900000) AND *-(0000000000000000,fff0000000000000,7ff0000000000000) => fff0000000000000 7ff8000000000000
+#3: xvmsubmdp *-(8000000000000000,fff0000000000000,7ff7ffffffffffff) AND *-(7ff0000000000000,fff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvmsubmdp *-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND *-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) => 7ff0000000000000 7fffffffffffffff
+#5: xvmsubmdp *-(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) AND *-(7ff8000000000000,c0d0650f5a07b353,0000000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvmsubmdp *-(fff8000000000000,c0d0650f5a07b353,0123214569900000) AND *-(8008340000078000,c0d0650f5a07b353,7ff0000000000000) => fff8000000000000 fff0000000000000
+#7: xvmsubmdp *-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) AND *-(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#8: xvmsubmdp *-(404f000000000000,8000000000000000,fff0000000000000) AND *-(0018000000b77501,8000000000000000,c0d0650f5a07b353) => 7ff0000000000000 40d0650f5a07b353
+#9: xvmsubmdp *-(7fe800000000051b,8000000000000000,8000000000000000) AND *-(0123214569900000,8000000000000000,0000000000000000) => 0000000000000000 8000000000000000
+#10: xvmsubmdp *-(0000000000000000,8000000000000000,0123214569900000) AND *-(8000000000000000,8000000000000000,7ff0000000000000) => 8123214569900000 fff0000000000000
+#11: xvmsubmdp *-(7ff0000000000000,8000000000000000,7ff7ffffffffffff) AND *-(fff0000000000000,8000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvmsubmdp *-(7ff7ffffffffffff,0000000000000000,fff0000000000000) AND *-(fff7ffffffffffff,0000000000000000,c0d0650f5a07b353) => 7fffffffffffffff ffffffffffffffff
+#13: xvmsubmdp *-(7ff8000000000000,0000000000000000,8000000000000000) AND *-(fff8000000000000,0000000000000000,0000000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvmsubmdp *-(8008340000078000,0000000000000000,0123214569900000) AND *-(c0d0650f5a07b353,0000000000000000,7ff0000000000000) => 8123214569900000 fff0000000000000
+#15: xvmsubmdp *-(3fd8000000000000,0000000000000000,7ff7ffffffffffff) AND *-(404f000000000000,0000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvmsubmdp *-(0018000000b77501,0123214569900000,fff0000000000000) AND *-(7fe800000000051b,0123214569900000,c0d0650f5a07b353) => 7ff0000000000000 411db83913f88150
+#17: xvmsubmdp *-(0123214569900000,0123214569900000,8000000000000000) AND *-(0000000000000000,0123214569900000,0000000000000000) => 0000000000000000 0000000000000000
+#18: xvmsubmdp *-(8000000000000000,0123214569900000,404f000000000000) AND *-(7ff0000000000000,0123214569900000,7ff0000000000000) => c04f000000000000 7ff8000000000000
+#19: xvmsubmdp *-(fff0000000000000,0123214569900000,7ff7ffffffffffff) AND *-(7ff7ffffffffffff,0123214569900000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#20: xvmsubmdp *-(fff7ffffffffffff,7ff0000000000000,fff0000000000000) AND *-(7ff8000000000000,7ff0000000000000,c0d0650f5a07b353) => ffffffffffffffff 7ff8000000000000
+#21: xvmsubmdp *-(fff8000000000000,7ff0000000000000,8000000000000000) AND *-(8008340000078000,7ff0000000000000,0000000000000000) => fff8000000000000 fff0000000000000
+#22: xvmsubmdp *-(c0d0650f5a07b353,7ff0000000000000,0123214569900000) AND *-(41232585a9900000,7ff0000000000000,7ff0000000000000) => fff0000000000000 7ff8000000000000
+#23: xvmsubmdp *-(404f000000000000,7ff0000000000000,7ff7ffffffffffff) AND *-(0018000000b77501,7ff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#24: xvmsubmdp *-(7fe800000000051b,fff7ffffffffffff,fff0000000000000) AND *-(0123214569900000,fff7ffffffffffff,c0d0650f5a07b353) => ffffffffffffffff ffffffffffffffff
+#25: xvmsubmdp *-(0000000000000000,fff8000000000000,8000000000000000) AND *-(8000000000000000,fff8000000000000,0000000000000000) => fff8000000000000 fff8000000000000
+#26: xvmsubmdp *-(7ff0000000000000,fff7ffffffffffff,0123214569900000) AND *-(fff0000000000000,fff7ffffffffffff,7ff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvmsubmdp *-(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND *-(fff7ffffffffffff,fff7ffffffffffff,7ff8000000000000) => ffffffffffffffff ffffffffffffffff
+#28: xvmsubmdp *-(7ff8000000000000,fff8000000000000,fff0000000000000) AND *-(fff8000000000000,fff8000000000000,c0d0650f5a07b353) => fff8000000000000 fff8000000000000
+#29: xvmsubmdp *-(8008340000078000,fff8000000000000,8000000000000000) AND *-(c0d0650f5a07b353,41232585a9900000,41382511a2000000) => fff8000000000000 c2039f360cc502d2
+#30: xvmsubmdp *-(3fd8000000000000,41232585a9900000,41382511a2000000) AND *-(404f000000000000,7ff7ffffffffffff,7ff8000000000000) => c1348e0892350000 7fffffffffffffff
+#31: xvmsubmdp *-(0018000000b77501,7ff8000000000000,7ff8000000000000) AND *-(7fe800000000051b,7ff8000000000000,fff8000000000000) => 7ff8000000000000 7ff8000000000000
+
+#0: xvmsubasp *-(ff800000,ff800000,3ec00000) AND *-(c683287b,ff800000,42780000) AND *-(49c1288d,49192c2d,00000000) AND *-(00000000,ff800000,7f800000) => 7fc00000 ff800000 c9c1288d ff800000
+#1: xvmsubasp *-(00000000,ff800000,00000000) AND *-(7f800000,ff800000,00000000) AND *-(7fffffff,ff800000,80000000) AND *-(7fc00000,ff800000,7f800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvmsubasp *-(ff800000,c683287b,ff800000) AND *-(c683287b,c683287b,7fffffff) AND *-(80000000,c683287b,ffffffff) AND *-(00000000,c683287b,7fc00000) => 7f800000 7fffffff ffffffff 7fc00000
+#3: xvmsubasp *-(00000000,c683287b,ffc00000) AND *-(7f800000,c683287b,80000000) AND *-(7fffffff,c683287b,c683287b) AND *-(7fc00000,c683287b,49192c2d) => ffc00000 ff800000 7fffffff 7fc00000
+#4: xvmsubasp *-(ff800000,80000000,7f800000) AND *-(c683287b,80000000,00000000) AND *-(80000000,80000000,00000000) AND *-(00000000,80000000,80000000) => 7fc00000 4683287b 00000000 00000000
+#5: xvmsubasp *-(00000000,80000000,7f800000) AND *-(7f800000,80000000,ff800000) AND *-(7fffffff,80000000,7fffffff) AND *-(7fc00000,80000000,ffffffff) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvmsubasp *-(ff800000,00000000,7fc00000) AND *-(c683287b,00000000,ffc00000) AND *-(80000000,00000000,80000000) AND *-(00000000,00000000,c683287b) => 7fc00000 ffc00000 00000000 80000000
+#7: xvmsubasp *-(00000000,00000000,00000000) AND *-(7f800000,00000000,7f800000) AND *-(7fffffff,00000000,00000000) AND *-(7fc00000,00000000,00000000) => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmsubasp *-(ff800000,00000000,80000000) AND *-(c683287b,00000000,7f800000) AND *-(80000000,00000000,ff800000) AND *-(00000000,00000000,7fffffff) => 7f800000 7fc00000 7fc00000 7fffffff
+#9: xvmsubasp *-(42780000,00000000,ffffffff) AND *-(7f800000,00000000,7fc00000) AND *-(7fffffff,00000000,ffc00000) AND *-(7fc00000,00000000,80000000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvmsubasp *-(ff800000,7f800000,42780000) AND *-(c683287b,7f800000,00000000) AND *-(80000000,7f800000,7f800000) AND *-(00000000,7f800000,00000000) => 7f800000 7fc00000 7f800000 7fc00000
+#11: xvmsubasp *-(00000000,7f800000,00000000) AND *-(7f800000,7f800000,80000000) AND *-(7fffffff,7f800000,7f800000) AND *-(7fc00000,7f800000,ff800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvmsubasp *-(ff800000,ffffffff,7fffffff) AND *-(c683287b,ffffffff,ffffffff) AND *-(80000000,ffc00000,7fc00000) AND *-(00000000,ffc00000,ffc00000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmsubasp *-(00000000,ffffffff,3ec00000) AND *-(7f800000,ffffffff,42780000) AND *-(7fffffff,ffffffff,00000000) AND *-(7fc00000,ffffffff,7f800000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvmsubasp *-(ff800000,ffc00000,00000000) AND *-(c683287b,ffc00000,00000000) AND *-(80000000,ffc00000,80000000) AND *-(49c1288d,49192c2d,7f800000) => ffc00000 ffc00000 ffc00000 7f800000
+#15: xvmsubasp *-(49c1288d,49192c2d,ff800000) AND *-(7fc00000,7fffffff,7fffffff) AND *-(7fc00000,7fc00000,ffffffff) AND *-(ffc00000,7fc00000,7fc00000) => ff800000 7fffffff 7fc00000 7fc00000
+
+#0: xvmsubmsp *-(3ec00000,ff800000,ff800000) AND *-(42780000,ff800000,c683287b) AND *-(00000000,49192c2d,49c1288d) AND *-(7f800000,ff800000,00000000) => 7fc00000 ff800000 c9c1288d ff800000
+#1: xvmsubmsp *-(00000000,ff800000,00000000) AND *-(00000000,ff800000,7f800000) AND *-(80000000,ff800000,7fffffff) AND *-(7f800000,ff800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvmsubmsp *-(ff800000,c683287b,ff800000) AND *-(7fffffff,c683287b,c683287b) AND *-(ffffffff,c683287b,80000000) AND *-(7fc00000,c683287b,00000000) => 7f800000 7fffffff ffffffff 7fc00000
+#3: xvmsubmsp *-(ffc00000,c683287b,00000000) AND *-(80000000,c683287b,7f800000) AND *-(c683287b,c683287b,7fffffff) AND *-(49192c2d,c683287b,7fc00000) => ffc00000 ff800000 7fffffff 7fc00000
+#4: xvmsubmsp *-(7f800000,80000000,ff800000) AND *-(00000000,80000000,c683287b) AND *-(00000000,80000000,80000000) AND *-(80000000,80000000,00000000) => 7fc00000 4683287b 00000000 00000000
+#5: xvmsubmsp *-(7f800000,80000000,00000000) AND *-(ff800000,80000000,7f800000) AND *-(7fffffff,80000000,7fffffff) AND *-(ffffffff,80000000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvmsubmsp *-(7fc00000,00000000,ff800000) AND *-(ffc00000,00000000,c683287b) AND *-(80000000,00000000,80000000) AND *-(c683287b,00000000,00000000) => 7fc00000 ffc00000 00000000 80000000
+#7: xvmsubmsp *-(00000000,00000000,00000000) AND *-(7f800000,00000000,7f800000) AND *-(00000000,00000000,7fffffff) AND *-(00000000,00000000,7fc00000) => 00000000 7fc00000 7fffffff 7fc00000
+#8: xvmsubmsp *-(80000000,00000000,ff800000) AND *-(7f800000,00000000,c683287b) AND *-(ff800000,00000000,80000000) AND *-(7fffffff,00000000,00000000) => 7f800000 7fc00000 7fc00000 7fffffff
+#9: xvmsubmsp *-(ffffffff,00000000,42780000) AND *-(7fc00000,00000000,7f800000) AND *-(ffc00000,00000000,7fffffff) AND *-(80000000,00000000,7fc00000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvmsubmsp *-(42780000,7f800000,ff800000) AND *-(00000000,7f800000,c683287b) AND *-(7f800000,7f800000,80000000) AND *-(00000000,7f800000,00000000) => 7f800000 7fc00000 7f800000 7fc00000
+#11: xvmsubmsp *-(00000000,7f800000,00000000) AND *-(80000000,7f800000,7f800000) AND *-(7f800000,7f800000,7fffffff) AND *-(ff800000,7f800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvmsubmsp *-(7fffffff,ffffffff,ff800000) AND *-(ffffffff,ffffffff,c683287b) AND *-(7fc00000,ffc00000,80000000) AND *-(ffc00000,ffc00000,00000000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvmsubmsp *-(3ec00000,ffffffff,00000000) AND *-(42780000,ffffffff,7f800000) AND *-(00000000,ffffffff,7fffffff) AND *-(7f800000,ffffffff,7fc00000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvmsubmsp *-(00000000,ffc00000,ff800000) AND *-(00000000,ffc00000,c683287b) AND *-(80000000,ffc00000,80000000) AND *-(7f800000,49192c2d,49c1288d) => ffc00000 ffc00000 ffc00000 7f800000
+#15: xvmsubmsp *-(ff800000,49192c2d,49c1288d) AND *-(7fffffff,7fffffff,7fc00000) AND *-(ffffffff,7fc00000,7fc00000) AND *-(7fc00000,7fc00000,ffc00000) => ff800000 7fffffff 7fc00000 7fc00000
+
+#0: xvnmsubadp !*-(fff0000000000000,fff0000000000000,3fd8000000000000) AND !*-(c0d0650f5a07b353,fff0000000000000,404f000000000000) => 7ff8000000000000 7ff0000000000000
+#1: xvnmsubadp !*-(41382511a2000000,41232585a9900000,0018000000b77501) AND !*-(0000000000000000,fff0000000000000,7fe800000000051b) => 41382511a2000000 7ff0000000000000
+#2: xvnmsubadp !*-(0123214569900000,fff0000000000000,0123214569900000) AND !*-(7ff0000000000000,fff0000000000000,0000000000000000) => 7ff0000000000000 7ff8000000000000
+#3: xvnmsubadp !*-(7ff7ffffffffffff,fff0000000000000,8000000000000000) AND !*-(7ff8000000000000,fff0000000000000,7ff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvnmsubadp !*-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND !*-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) => fff0000000000000 7fffffffffffffff
+#5: xvnmsubadp !*-(8000000000000000,c0d0650f5a07b353,fff7ffffffffffff) AND !*-(0000000000000000,c0d0650f5a07b353,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvnmsubadp !*-(0123214569900000,c0d0650f5a07b353,fff8000000000000) AND !*-(7ff0000000000000,c0d0650f5a07b353,8008340000078000) => fff8000000000000 7ff0000000000000
+#7: xvnmsubadp !*-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) AND !*-(7ff8000000000000,c0d0650f5a07b353,41232585a9900000) => 7fffffffffffffff 7ff8000000000000
+#8: xvnmsubadp !*-(fff0000000000000,8000000000000000,404f000000000000) AND !*-(c0d0650f5a07b353,8000000000000000,0018000000b77501) => fff0000000000000 c0d0650f5a07b353
+#9: xvnmsubadp !*-(8000000000000000,8000000000000000,7fe800000000051b) AND !*-(0000000000000000,8000000000000000,0123214569900000) => 8000000000000000 0000000000000000
+#10: xvnmsubadp !*-(0123214569900000,8000000000000000,0000000000000000) AND !*-(7ff0000000000000,8000000000000000,8000000000000000) => 0123214569900000 7ff0000000000000
+#11: xvnmsubadp !*-(7ff7ffffffffffff,8000000000000000,7ff0000000000000) AND !*-(7ff8000000000000,8000000000000000,fff0000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvnmsubadp !*-(fff0000000000000,0000000000000000,7ff7ffffffffffff) AND !*-(c0d0650f5a07b353,0000000000000000,fff7ffffffffffff) => 7fffffffffffffff ffffffffffffffff
+#13: xvnmsubadp !*-(8000000000000000,0000000000000000,7ff8000000000000) AND !*-(0000000000000000,0000000000000000,fff8000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvnmsubadp !*-(0123214569900000,0000000000000000,8008340000078000) AND !*-(7ff0000000000000,0000000000000000,c0d0650f5a07b353) => 0123214569900000 7ff0000000000000
+#15: xvnmsubadp !*-(7ff7ffffffffffff,0000000000000000,3fd8000000000000) AND !*-(7ff8000000000000,0000000000000000,404f000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvnmsubadp !*-(fff0000000000000,0123214569900000,0018000000b77501) AND !*-(c0d0650f5a07b353,0123214569900000,7fe800000000051b) => fff0000000000000 c11db83913f88150
+#17: xvnmsubadp !*-(8000000000000000,0123214569900000,0123214569900000) AND !*-(0000000000000000,0123214569900000,0000000000000000) => 8000000000000000 8000000000000000
+#18: xvnmsubadp !*-(404f000000000000,0123214569900000,8000000000000000) AND !*-(7ff0000000000000,0123214569900000,7ff0000000000000) => 404f000000000000 7ff8000000000000
+#19: xvnmsubadp !*-(7ff7ffffffffffff,0123214569900000,fff0000000000000) AND !*-(7ff8000000000000,0123214569900000,7ff7ffffffffffff) => 7fffffffffffffff 7ff8000000000000
+#20: xvnmsubadp !*-(fff0000000000000,7ff0000000000000,fff7ffffffffffff) AND !*-(c0d0650f5a07b353,7ff0000000000000,7ff8000000000000) => ffffffffffffffff 7ff8000000000000
+#21: xvnmsubadp !*-(8000000000000000,7ff0000000000000,fff8000000000000) AND !*-(0000000000000000,7ff0000000000000,8008340000078000) => fff8000000000000 7ff0000000000000
+#22: xvnmsubadp !*-(0123214569900000,7ff0000000000000,c0d0650f5a07b353) AND !*-(7ff0000000000000,7ff0000000000000,41232585a9900000) => 7ff0000000000000 7ff8000000000000
+#23: xvnmsubadp !*-(7ff7ffffffffffff,7ff0000000000000,404f000000000000) AND !*-(7ff8000000000000,7ff0000000000000,0018000000b77501) => 7fffffffffffffff 7ff8000000000000
+#24: xvnmsubadp !*-(fff0000000000000,fff7ffffffffffff,7fe800000000051b) AND !*-(c0d0650f5a07b353,fff7ffffffffffff,0123214569900000) => ffffffffffffffff ffffffffffffffff
+#25: xvnmsubadp !*-(8000000000000000,fff8000000000000,0000000000000000) AND !*-(0000000000000000,fff8000000000000,8000000000000000) => fff8000000000000 fff8000000000000
+#26: xvnmsubadp !*-(0123214569900000,fff7ffffffffffff,7ff0000000000000) AND !*-(7ff0000000000000,fff7ffffffffffff,fff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvnmsubadp !*-(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND !*-(7ff8000000000000,fff7ffffffffffff,fff7ffffffffffff) => ffffffffffffffff ffffffffffffffff
+#28: xvnmsubadp !*-(fff0000000000000,fff8000000000000,7ff8000000000000) AND !*-(c0d0650f5a07b353,fff8000000000000,fff8000000000000) => fff8000000000000 fff8000000000000
+#29: xvnmsubadp !*-(8000000000000000,fff8000000000000,8008340000078000) AND !*-(41382511a2000000,41232585a9900000,c0d0650f5a07b353) => fff8000000000000 42039f360cc502d2
+#30: xvnmsubadp !*-(41382511a2000000,41232585a9900000,3fd8000000000000) AND !*-(7ff8000000000000,7ff7ffffffffffff,404f000000000000) => 41348e0892350000 7fffffffffffffff
+#31: xvnmsubadp !*-(7ff8000000000000,7ff8000000000000,0018000000b77501) AND !*-(fff8000000000000,7ff8000000000000,7fe800000000051b) => 7ff8000000000000 7ff8000000000000
+
+#0: xvnmsubmdp !*-(3fd8000000000000,fff0000000000000,fff0000000000000) AND !*-(404f000000000000,fff0000000000000,c0d0650f5a07b353) => 7ff8000000000000 7ff0000000000000
+#1: xvnmsubmdp !*-(0018000000b77501,41232585a9900000,41382511a2000000) AND !*-(7fe800000000051b,fff0000000000000,0000000000000000) => 41382511a2000000 7ff0000000000000
+#2: xvnmsubmdp !*-(0123214569900000,fff0000000000000,0123214569900000) AND !*-(0000000000000000,fff0000000000000,7ff0000000000000) => 7ff0000000000000 7ff8000000000000
+#3: xvnmsubmdp !*-(8000000000000000,fff0000000000000,7ff7ffffffffffff) AND !*-(7ff0000000000000,fff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#4: xvnmsubmdp !*-(fff0000000000000,c0d0650f5a07b353,fff0000000000000) AND !*-(7ff7ffffffffffff,c0d0650f5a07b353,c0d0650f5a07b353) => fff0000000000000 7fffffffffffffff
+#5: xvnmsubmdp !*-(fff7ffffffffffff,c0d0650f5a07b353,8000000000000000) AND !*-(7ff8000000000000,c0d0650f5a07b353,0000000000000000) => ffffffffffffffff 7ff8000000000000
+#6: xvnmsubmdp !*-(fff8000000000000,c0d0650f5a07b353,0123214569900000) AND !*-(8008340000078000,c0d0650f5a07b353,7ff0000000000000) => fff8000000000000 7ff0000000000000
+#7: xvnmsubmdp !*-(c0d0650f5a07b353,c0d0650f5a07b353,7ff7ffffffffffff) AND !*-(41232585a9900000,c0d0650f5a07b353,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#8: xvnmsubmdp !*-(404f000000000000,8000000000000000,fff0000000000000) AND !*-(0018000000b77501,8000000000000000,c0d0650f5a07b353) => fff0000000000000 c0d0650f5a07b353
+#9: xvnmsubmdp !*-(7fe800000000051b,8000000000000000,8000000000000000) AND !*-(0123214569900000,8000000000000000,0000000000000000) => 8000000000000000 0000000000000000
+#10: xvnmsubmdp !*-(0000000000000000,8000000000000000,0123214569900000) AND !*-(8000000000000000,8000000000000000,7ff0000000000000) => 0123214569900000 7ff0000000000000
+#11: xvnmsubmdp !*-(7ff0000000000000,8000000000000000,7ff7ffffffffffff) AND !*-(fff0000000000000,8000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#12: xvnmsubmdp !*-(7ff7ffffffffffff,0000000000000000,fff0000000000000) AND !*-(fff7ffffffffffff,0000000000000000,c0d0650f5a07b353) => 7fffffffffffffff ffffffffffffffff
+#13: xvnmsubmdp !*-(7ff8000000000000,0000000000000000,8000000000000000) AND !*-(fff8000000000000,0000000000000000,0000000000000000) => 7ff8000000000000 fff8000000000000
+#14: xvnmsubmdp !*-(8008340000078000,0000000000000000,0123214569900000) AND !*-(c0d0650f5a07b353,0000000000000000,7ff0000000000000) => 0123214569900000 7ff0000000000000
+#15: xvnmsubmdp !*-(3fd8000000000000,0000000000000000,7ff7ffffffffffff) AND !*-(404f000000000000,0000000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#16: xvnmsubmdp !*-(0018000000b77501,0123214569900000,fff0000000000000) AND !*-(7fe800000000051b,0123214569900000,c0d0650f5a07b353) => fff0000000000000 c11db83913f88150
+#17: xvnmsubmdp !*-(0123214569900000,0123214569900000,8000000000000000) AND !*-(0000000000000000,0123214569900000,0000000000000000) => 8000000000000000 8000000000000000
+#18: xvnmsubmdp !*-(8000000000000000,0123214569900000,404f000000000000) AND !*-(7ff0000000000000,0123214569900000,7ff0000000000000) => 404f000000000000 7ff8000000000000
+#19: xvnmsubmdp !*-(fff0000000000000,0123214569900000,7ff7ffffffffffff) AND !*-(7ff7ffffffffffff,0123214569900000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#20: xvnmsubmdp !*-(fff7ffffffffffff,7ff0000000000000,fff0000000000000) AND !*-(7ff8000000000000,7ff0000000000000,c0d0650f5a07b353) => ffffffffffffffff 7ff8000000000000
+#21: xvnmsubmdp !*-(fff8000000000000,7ff0000000000000,8000000000000000) AND !*-(8008340000078000,7ff0000000000000,0000000000000000) => fff8000000000000 7ff0000000000000
+#22: xvnmsubmdp !*-(c0d0650f5a07b353,7ff0000000000000,0123214569900000) AND !*-(41232585a9900000,7ff0000000000000,7ff0000000000000) => 7ff0000000000000 7ff8000000000000
+#23: xvnmsubmdp !*-(404f000000000000,7ff0000000000000,7ff7ffffffffffff) AND !*-(0018000000b77501,7ff0000000000000,7ff8000000000000) => 7fffffffffffffff 7ff8000000000000
+#24: xvnmsubmdp !*-(7fe800000000051b,fff7ffffffffffff,fff0000000000000) AND !*-(0123214569900000,fff7ffffffffffff,c0d0650f5a07b353) => ffffffffffffffff ffffffffffffffff
+#25: xvnmsubmdp !*-(0000000000000000,fff8000000000000,8000000000000000) AND !*-(8000000000000000,fff8000000000000,0000000000000000) => fff8000000000000 fff8000000000000
+#26: xvnmsubmdp !*-(7ff0000000000000,fff7ffffffffffff,0123214569900000) AND !*-(fff0000000000000,fff7ffffffffffff,7ff0000000000000) => ffffffffffffffff ffffffffffffffff
+#27: xvnmsubmdp !*-(7ff7ffffffffffff,fff7ffffffffffff,7ff7ffffffffffff) AND !*-(fff7ffffffffffff,fff7ffffffffffff,7ff8000000000000) => ffffffffffffffff ffffffffffffffff
+#28: xvnmsubmdp !*-(7ff8000000000000,fff8000000000000,fff0000000000000) AND !*-(fff8000000000000,fff8000000000000,c0d0650f5a07b353) => fff8000000000000 fff8000000000000
+#29: xvnmsubmdp !*-(8008340000078000,fff8000000000000,8000000000000000) AND !*-(c0d0650f5a07b353,41232585a9900000,41382511a2000000) => fff8000000000000 42039f360cc502d2
+#30: xvnmsubmdp !*-(3fd8000000000000,41232585a9900000,41382511a2000000) AND !*-(404f000000000000,7ff7ffffffffffff,7ff8000000000000) => 41348e0892350000 7fffffffffffffff
+#31: xvnmsubmdp !*-(0018000000b77501,7ff8000000000000,7ff8000000000000) AND !*-(7fe800000000051b,7ff8000000000000,fff8000000000000) => 7ff8000000000000 7ff8000000000000
+
+#0: xvnmsubasp !*-(ff800000,ff800000,3ec00000) AND !*-(c683287b,ff800000,42780000) AND !*-(49c1288d,49192c2d,00000000) AND !*-(00000000,ff800000,7f800000) => 7fc00000 7f800000 49c1288d 7f800000
+#1: xvnmsubasp !*-(00000000,ff800000,00000000) AND !*-(7f800000,ff800000,00000000) AND !*-(7fffffff,ff800000,80000000) AND !*-(7fc00000,ff800000,7f800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvnmsubasp !*-(ff800000,c683287b,ff800000) AND !*-(c683287b,c683287b,7fffffff) AND !*-(80000000,c683287b,ffffffff) AND !*-(00000000,c683287b,7fc00000) => ff800000 7fffffff ffffffff 7fc00000
+#3: xvnmsubasp !*-(00000000,c683287b,ffc00000) AND !*-(7f800000,c683287b,80000000) AND !*-(7fffffff,c683287b,c683287b) AND !*-(7fc00000,c683287b,49192c2d) => ffc00000 7f800000 7fffffff 7fc00000
+#4: xvnmsubasp !*-(ff800000,80000000,7f800000) AND !*-(c683287b,80000000,00000000) AND !*-(80000000,80000000,00000000) AND !*-(00000000,80000000,80000000) => 7fc00000 c683287b 80000000 80000000
+#5: xvnmsubasp !*-(00000000,80000000,7f800000) AND !*-(7f800000,80000000,ff800000) AND !*-(7fffffff,80000000,7fffffff) AND !*-(7fc00000,80000000,ffffffff) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvnmsubasp !*-(ff800000,00000000,7fc00000) AND !*-(c683287b,00000000,ffc00000) AND !*-(80000000,00000000,80000000) AND !*-(00000000,00000000,c683287b) => 7fc00000 ffc00000 80000000 00000000
+#7: xvnmsubasp !*-(00000000,00000000,00000000) AND !*-(7f800000,00000000,7f800000) AND !*-(7fffffff,00000000,00000000) AND !*-(7fc00000,00000000,00000000) => 80000000 7fc00000 7fffffff 7fc00000
+#8: xvnmsubasp !*-(ff800000,00000000,80000000) AND !*-(c683287b,00000000,7f800000) AND !*-(80000000,00000000,ff800000) AND !*-(00000000,00000000,7fffffff) => ff800000 7fc00000 7fc00000 7fffffff
+#9: xvnmsubasp !*-(42780000,00000000,ffffffff) AND !*-(7f800000,00000000,7fc00000) AND !*-(7fffffff,00000000,ffc00000) AND !*-(7fc00000,00000000,80000000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvnmsubasp !*-(ff800000,7f800000,42780000) AND !*-(c683287b,7f800000,00000000) AND !*-(80000000,7f800000,7f800000) AND !*-(00000000,7f800000,00000000) => ff800000 7fc00000 ff800000 7fc00000
+#11: xvnmsubasp !*-(00000000,7f800000,00000000) AND !*-(7f800000,7f800000,80000000) AND !*-(7fffffff,7f800000,7f800000) AND !*-(7fc00000,7f800000,ff800000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvnmsubasp !*-(ff800000,ffffffff,7fffffff) AND !*-(c683287b,ffffffff,ffffffff) AND !*-(80000000,ffc00000,7fc00000) AND !*-(00000000,ffc00000,ffc00000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvnmsubasp !*-(00000000,ffffffff,3ec00000) AND !*-(7f800000,ffffffff,42780000) AND !*-(7fffffff,ffffffff,00000000) AND !*-(7fc00000,ffffffff,7f800000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvnmsubasp !*-(ff800000,ffc00000,00000000) AND !*-(c683287b,ffc00000,00000000) AND !*-(80000000,ffc00000,80000000) AND !*-(49c1288d,49192c2d,7f800000) => ffc00000 ffc00000 ffc00000 ff800000
+#15: xvnmsubasp !*-(49c1288d,49192c2d,ff800000) AND !*-(7fc00000,7fffffff,7fffffff) AND !*-(7fc00000,7fc00000,ffffffff) AND !*-(ffc00000,7fc00000,7fc00000) => 7f800000 7fffffff 7fc00000 7fc00000
+
+#0: xvnmsubmsp !*-(3ec00000,ff800000,ff800000) AND !*-(42780000,ff800000,c683287b) AND !*-(00000000,49192c2d,49c1288d) AND !*-(7f800000,ff800000,00000000) => 7fc00000 7f800000 49c1288d 7f800000
+#1: xvnmsubmsp !*-(00000000,ff800000,00000000) AND !*-(00000000,ff800000,7f800000) AND !*-(80000000,ff800000,7fffffff) AND !*-(7f800000,ff800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#2: xvnmsubmsp !*-(ff800000,c683287b,ff800000) AND !*-(7fffffff,c683287b,c683287b) AND !*-(ffffffff,c683287b,80000000) AND !*-(7fc00000,c683287b,00000000) => ff800000 7fffffff ffffffff 7fc00000
+#3: xvnmsubmsp !*-(ffc00000,c683287b,00000000) AND !*-(80000000,c683287b,7f800000) AND !*-(c683287b,c683287b,7fffffff) AND !*-(49192c2d,c683287b,7fc00000) => ffc00000 7f800000 7fffffff 7fc00000
+#4: xvnmsubmsp !*-(7f800000,80000000,ff800000) AND !*-(00000000,80000000,c683287b) AND !*-(00000000,80000000,80000000) AND !*-(80000000,80000000,00000000) => 7fc00000 c683287b 80000000 80000000
+#5: xvnmsubmsp !*-(7f800000,80000000,00000000) AND !*-(ff800000,80000000,7f800000) AND !*-(7fffffff,80000000,7fffffff) AND !*-(ffffffff,80000000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#6: xvnmsubmsp !*-(7fc00000,00000000,ff800000) AND !*-(ffc00000,00000000,c683287b) AND !*-(80000000,00000000,80000000) AND !*-(c683287b,00000000,00000000) => 7fc00000 ffc00000 80000000 00000000
+#7: xvnmsubmsp !*-(00000000,00000000,00000000) AND !*-(7f800000,00000000,7f800000) AND !*-(00000000,00000000,7fffffff) AND !*-(00000000,00000000,7fc00000) => 80000000 7fc00000 7fffffff 7fc00000
+#8: xvnmsubmsp !*-(80000000,00000000,ff800000) AND !*-(7f800000,00000000,c683287b) AND !*-(ff800000,00000000,80000000) AND !*-(7fffffff,00000000,00000000) => ff800000 7fc00000 7fc00000 7fffffff
+#9: xvnmsubmsp !*-(ffffffff,00000000,42780000) AND !*-(7fc00000,00000000,7f800000) AND !*-(ffc00000,00000000,7fffffff) AND !*-(80000000,00000000,7fc00000) => ffffffff 7fc00000 7fffffff 7fc00000
+#10: xvnmsubmsp !*-(42780000,7f800000,ff800000) AND !*-(00000000,7f800000,c683287b) AND !*-(7f800000,7f800000,80000000) AND !*-(00000000,7f800000,00000000) => ff800000 7fc00000 ff800000 7fc00000
+#11: xvnmsubmsp !*-(00000000,7f800000,00000000) AND !*-(80000000,7f800000,7f800000) AND !*-(7f800000,7f800000,7fffffff) AND !*-(ff800000,7f800000,7fc00000) => 7fc00000 7fc00000 7fffffff 7fc00000
+#12: xvnmsubmsp !*-(7fffffff,ffffffff,ff800000) AND !*-(ffffffff,ffffffff,c683287b) AND !*-(7fc00000,ffc00000,80000000) AND !*-(ffc00000,ffc00000,00000000) => ffffffff ffffffff ffc00000 ffc00000
+#13: xvnmsubmsp !*-(3ec00000,ffffffff,00000000) AND !*-(42780000,ffffffff,7f800000) AND !*-(00000000,ffffffff,7fffffff) AND !*-(7f800000,ffffffff,7fc00000) => ffffffff ffffffff ffffffff ffffffff
+#14: xvnmsubmsp !*-(00000000,ffc00000,ff800000) AND !*-(00000000,ffc00000,c683287b) AND !*-(80000000,ffc00000,80000000) AND !*-(7f800000,49192c2d,49c1288d) => ffc00000 ffc00000 ffc00000 ff800000
+#15: xvnmsubmsp !*-(ff800000,49192c2d,49c1288d) AND !*-(7fffffff,7fffffff,7fc00000) AND !*-(ffffffff,7fc00000,7fc00000) AND !*-(7fc00000,7fc00000,ffc00000) => 7f800000 7fffffff 7fc00000 7fc00000
+
+
+Test scalar floating point arithmetic instructions
+#0: xssqrtdp 3fd8000000000000 => 3fe3988e1409212e
+#1: xssqrtdp 404f000000000000 => 401f7efbeb8d4f12
+#2: xssqrtdp 0018000000b77501 => 2003988e14540690
+#3: xssqrtdp 7fe800000000051b => 5febb67ae8584f9d
+#4: xssqrtdp 0123214569900000 => 2088bde98d60ebe6
+#5: xssqrtdp 0000000000000000 => 0000000000000000
+#6: xssqrtdp 8000000000000000 => 8000000000000000
+#7: xssqrtdp 7ff0000000000000 => 7ff0000000000000
+#8: xssqrtdp fff0000000000000 => 7ff8000000000000
+#9: xssqrtdp 7ff7ffffffffffff => 7fffffffffffffff
+#10: xssqrtdp fff7ffffffffffff => ffffffffffffffff
+#11: xssqrtdp 7ff8000000000000 => 7ff8000000000000
+#12: xssqrtdp fff8000000000000 => fff8000000000000
+#13: xssqrtdp 8008340000078000 => 7ff8000000000000
+#14: xssqrtdp c0d0650f5a07b353 => 7ff8000000000000
+#15: xssqrtdp 41232585a9900000 => 4088c0a9258a4a8b
+#16: xssqrtdp 41382511a2000000 => 4093a7aa60f34e85
+
+#0: xsrdpim 3fd8000000000000 => 0000000000000000
+#1: xsrdpim 404f000000000000 => 404f000000000000
+#2: xsrdpim 0018000000b77501 => 0000000000000000
+#3: xsrdpim 7fe800000000051b => 7fe800000000051b
+#4: xsrdpim 0123214569900000 => 0000000000000000
+#5: xsrdpim 0000000000000000 => 0000000000000000
+#6: xsrdpim 8000000000000000 => 8000000000000000
+#7: xsrdpim 7ff0000000000000 => 7ff0000000000000
+#8: xsrdpim fff0000000000000 => fff0000000000000
+#9: xsrdpim 7ff7ffffffffffff => 7fffffffffffffff
+#10: xsrdpim fff7ffffffffffff => ffffffffffffffff
+#11: xsrdpim 7ff8000000000000 => 7ff8000000000000
+#12: xsrdpim fff8000000000000 => fff8000000000000
+#13: xsrdpim 8008340000078000 => bff0000000000000
+#14: xsrdpim c0d0650f5a07b353 => c0d0654000000000
+#15: xsrdpim 41232585a9900000 => 4123258400000000
+#16: xsrdpim 41382511a2000000 => 4138251100000000
+
+#0: xsrdpip 3fd8000000000000 => 3ff0000000000000
+#1: xsrdpip 404f000000000000 => 404f000000000000
+#2: xsrdpip 0018000000b77501 => 3ff0000000000000
+#3: xsrdpip 7fe800000000051b => 7fe800000000051b
+#4: xsrdpip 0123214569900000 => 3ff0000000000000
+#5: xsrdpip 0000000000000000 => 0000000000000000
+#6: xsrdpip 8000000000000000 => 8000000000000000
+#7: xsrdpip 7ff0000000000000 => 7ff0000000000000
+#8: xsrdpip fff0000000000000 => fff0000000000000
+#9: xsrdpip 7ff7ffffffffffff => 7fffffffffffffff
+#10: xsrdpip fff7ffffffffffff => ffffffffffffffff
+#11: xsrdpip 7ff8000000000000 => 7ff8000000000000
+#12: xsrdpip fff8000000000000 => fff8000000000000
+#13: xsrdpip 8008340000078000 => 8000000000000000
+#14: xsrdpip c0d0650f5a07b353 => c0d0650000000000
+#15: xsrdpip 41232585a9900000 => 4123258600000000
+#16: xsrdpip 41382511a2000000 => 4138251200000000
+
+#0: xstdivdp fff0000000000000,fff0000000000000 => cr e
+#1: xstdivdp fff0000000000000,c0d0650f5a07b353 => cr e
+#2: xstdivdp 41232585a9900000,41382511a2000000 => cr 8
+#3: xstdivdp fff0000000000000,0000000000000000 => cr e
+#4: xstdivdp fff0000000000000,0123214569900000 => cr e
+#5: xstdivdp fff0000000000000,7ff0000000000000 => cr e
+#6: xstdivdp fff0000000000000,7ff7ffffffffffff => cr e
+#7: xstdivdp fff0000000000000,7ff8000000000000 => cr e
+#8: xstdivdp c0d0650f5a07b353,fff0000000000000 => cr e
+#9: xstdivdp c0d0650f5a07b353,c0d0650f5a07b353 => cr 8
+#10: xstdivdp c0d0650f5a07b353,8000000000000000 => cr e
+#11: xstdivdp c0d0650f5a07b353,0000000000000000 => cr e
+#12: xstdivdp c0d0650f5a07b353,0123214569900000 => cr 8
+#13: xstdivdp c0d0650f5a07b353,7ff0000000000000 => cr e
+#14: xstdivdp c0d0650f5a07b353,7ff7ffffffffffff => cr a
+#15: xstdivdp c0d0650f5a07b353,7ff8000000000000 => cr a
+#16: xstdivdp 8000000000000000,fff0000000000000 => cr e
+#17: xstdivdp 8000000000000000,c0d0650f5a07b353 => cr 8
+#18: xstdivdp 8000000000000000,8000000000000000 => cr e
+#19: xstdivdp 8000000000000000,0000000000000000 => cr e
+#20: xstdivdp 8000000000000000,0123214569900000 => cr 8
+#21: xstdivdp 8000000000000000,7ff0000000000000 => cr e
+#22: xstdivdp 8000000000000000,7ff7ffffffffffff => cr a
+#23: xstdivdp 8000000000000000,7ff8000000000000 => cr a
+#24: xstdivdp 0000000000000000,fff0000000000000 => cr e
+#25: xstdivdp 0000000000000000,c0d0650f5a07b353 => cr 8
+#26: xstdivdp 0000000000000000,8000000000000000 => cr e
+#27: xstdivdp 0000000000000000,0000000000000000 => cr e
+#28: xstdivdp 0000000000000000,0123214569900000 => cr 8
+#29: xstdivdp 0000000000000000,7ff0000000000000 => cr e
+#30: xstdivdp 0000000000000000,7ff7ffffffffffff => cr a
+#31: xstdivdp 0000000000000000,7ff8000000000000 => cr a
+#32: xstdivdp 0123214569900000,fff0000000000000 => cr e
+#33: xstdivdp 0123214569900000,c0d0650f5a07b353 => cr a
+#34: xstdivdp 0123214569900000,8000000000000000 => cr e
+#35: xstdivdp 0123214569900000,0000000000000000 => cr e
+#36: xstdivdp 0123214569900000,404f000000000000 => cr a
+#37: xstdivdp 0123214569900000,7ff0000000000000 => cr e
+#38: xstdivdp 0123214569900000,7ff7ffffffffffff => cr a
+#39: xstdivdp 0123214569900000,7ff8000000000000 => cr a
+#40: xstdivdp 7ff0000000000000,fff0000000000000 => cr e
+#41: xstdivdp 7ff0000000000000,c0d0650f5a07b353 => cr e
+#42: xstdivdp 7ff0000000000000,8000000000000000 => cr e
+#43: xstdivdp 7ff0000000000000,0000000000000000 => cr e
+#44: xstdivdp 7ff0000000000000,0123214569900000 => cr e
+#45: xstdivdp 7ff0000000000000,7ff0000000000000 => cr e
+#46: xstdivdp 7ff0000000000000,7ff7ffffffffffff => cr e
+#47: xstdivdp 7ff0000000000000,7ff8000000000000 => cr e
+#48: xstdivdp fff7ffffffffffff,fff0000000000000 => cr e
+#49: xstdivdp fff7ffffffffffff,c0d0650f5a07b353 => cr a
+#50: xstdivdp fff8000000000000,8000000000000000 => cr e
+#51: xstdivdp fff8000000000000,0000000000000000 => cr e
+#52: xstdivdp fff7ffffffffffff,0123214569900000 => cr a
+#53: xstdivdp fff7ffffffffffff,7ff0000000000000 => cr e
+#54: xstdivdp fff7ffffffffffff,7ff7ffffffffffff => cr a
+#55: xstdivdp fff7ffffffffffff,7ff8000000000000 => cr a
+#56: xstdivdp fff8000000000000,fff0000000000000 => cr e
+#57: xstdivdp fff8000000000000,c0d0650f5a07b353 => cr a
+#58: xstdivdp fff8000000000000,8000000000000000 => cr e
+#59: xstdivdp 41232585a9900000,41382511a2000000 => cr 8
+#60: xstdivdp 41232585a9900000,41382511a2000000 => cr 8
+#61: xstdivdp 7ff7ffffffffffff,7ff8000000000000 => cr a
+#62: xstdivdp 7ff8000000000000,7ff8000000000000 => cr a
+#63: xstdivdp 7ff8000000000000,fff8000000000000 => cr a
+
+#0: xsmaxdp fff0000000000000,fff0000000000000 => fff0000000000000
+#1: xsmaxdp fff0000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#2: xsmaxdp 41232585a9900000,41382511a2000000 => 41382511a2000000
+#3: xsmaxdp fff0000000000000,0000000000000000 => 0000000000000000
+#4: xsmaxdp fff0000000000000,0123214569900000 => 0123214569900000
+#5: xsmaxdp fff0000000000000,7ff0000000000000 => 7ff0000000000000
+#6: xsmaxdp fff0000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#7: xsmaxdp fff0000000000000,7ff8000000000000 => fff0000000000000
+#8: xsmaxdp c0d0650f5a07b353,fff0000000000000 => c0d0650f5a07b353
+#9: xsmaxdp c0d0650f5a07b353,c0d0650f5a07b353 => c0d0650f5a07b353
+#10: xsmaxdp c0d0650f5a07b353,8000000000000000 => 8000000000000000
+#11: xsmaxdp c0d0650f5a07b353,0000000000000000 => 0000000000000000
+#12: xsmaxdp c0d0650f5a07b353,0123214569900000 => 0123214569900000
+#13: xsmaxdp c0d0650f5a07b353,7ff0000000000000 => 7ff0000000000000
+#14: xsmaxdp c0d0650f5a07b353,7ff7ffffffffffff => 7fffffffffffffff
+#15: xsmaxdp c0d0650f5a07b353,7ff8000000000000 => c0d0650f5a07b353
+#16: xsmaxdp 8000000000000000,fff0000000000000 => 8000000000000000
+#17: xsmaxdp 8000000000000000,c0d0650f5a07b353 => 8000000000000000
+#18: xsmaxdp 8000000000000000,8000000000000000 => 8000000000000000
+#19: xsmaxdp 8000000000000000,0000000000000000 => 0000000000000000
+#20: xsmaxdp 8000000000000000,0123214569900000 => 0123214569900000
+#21: xsmaxdp 8000000000000000,7ff0000000000000 => 7ff0000000000000
+#22: xsmaxdp 8000000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#23: xsmaxdp 8000000000000000,7ff8000000000000 => 8000000000000000
+#24: xsmaxdp 0000000000000000,fff0000000000000 => 0000000000000000
+#25: xsmaxdp 0000000000000000,c0d0650f5a07b353 => 0000000000000000
+#26: xsmaxdp 0000000000000000,8000000000000000 => 0000000000000000
+#27: xsmaxdp 0000000000000000,0000000000000000 => 0000000000000000
+#28: xsmaxdp 0000000000000000,0123214569900000 => 0123214569900000
+#29: xsmaxdp 0000000000000000,7ff0000000000000 => 7ff0000000000000
+#30: xsmaxdp 0000000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#31: xsmaxdp 0000000000000000,7ff8000000000000 => 0000000000000000
+#32: xsmaxdp 0123214569900000,fff0000000000000 => 0123214569900000
+#33: xsmaxdp 0123214569900000,c0d0650f5a07b353 => 0123214569900000
+#34: xsmaxdp 0123214569900000,8000000000000000 => 0123214569900000
+#35: xsmaxdp 0123214569900000,0000000000000000 => 0123214569900000
+#36: xsmaxdp 0123214569900000,404f000000000000 => 404f000000000000
+#37: xsmaxdp 0123214569900000,7ff0000000000000 => 7ff0000000000000
+#38: xsmaxdp 0123214569900000,7ff7ffffffffffff => 7fffffffffffffff
+#39: xsmaxdp 0123214569900000,7ff8000000000000 => 0123214569900000
+#40: xsmaxdp 7ff0000000000000,fff0000000000000 => 7ff0000000000000
+#41: xsmaxdp 7ff0000000000000,c0d0650f5a07b353 => 7ff0000000000000
+#42: xsmaxdp 7ff0000000000000,8000000000000000 => 7ff0000000000000
+#43: xsmaxdp 7ff0000000000000,0000000000000000 => 7ff0000000000000
+#44: xsmaxdp 7ff0000000000000,0123214569900000 => 7ff0000000000000
+#45: xsmaxdp 7ff0000000000000,7ff0000000000000 => 7ff0000000000000
+#46: xsmaxdp 7ff0000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#47: xsmaxdp 7ff0000000000000,7ff8000000000000 => 7ff0000000000000
+#48: xsmaxdp fff7ffffffffffff,fff0000000000000 => ffffffffffffffff
+#49: xsmaxdp fff7ffffffffffff,c0d0650f5a07b353 => ffffffffffffffff
+#50: xsmaxdp fff8000000000000,8000000000000000 => 8000000000000000
+#51: xsmaxdp fff8000000000000,0000000000000000 => 0000000000000000
+#52: xsmaxdp fff7ffffffffffff,0123214569900000 => ffffffffffffffff
+#53: xsmaxdp fff7ffffffffffff,7ff0000000000000 => ffffffffffffffff
+#54: xsmaxdp fff7ffffffffffff,7ff7ffffffffffff => ffffffffffffffff
+#55: xsmaxdp fff7ffffffffffff,7ff8000000000000 => ffffffffffffffff
+#56: xsmaxdp fff8000000000000,fff0000000000000 => fff0000000000000
+#57: xsmaxdp fff8000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#58: xsmaxdp fff8000000000000,8000000000000000 => 8000000000000000
+#59: xsmaxdp 41232585a9900000,41382511a2000000 => 41382511a2000000
+#60: xsmaxdp 41232585a9900000,41382511a2000000 => 41382511a2000000
+#61: xsmaxdp 7ff7ffffffffffff,7ff8000000000000 => 7fffffffffffffff
+#62: xsmaxdp 7ff8000000000000,7ff8000000000000 => 7ff8000000000000
+#63: xsmaxdp 7ff8000000000000,fff8000000000000 => 7ff8000000000000
+
+#0: xsmindp fff0000000000000,fff0000000000000 => fff0000000000000
+#1: xsmindp fff0000000000000,c0d0650f5a07b353 => fff0000000000000
+#2: xsmindp 41232585a9900000,41382511a2000000 => 41232585a9900000
+#3: xsmindp fff0000000000000,0000000000000000 => fff0000000000000
+#4: xsmindp fff0000000000000,0123214569900000 => fff0000000000000
+#5: xsmindp fff0000000000000,7ff0000000000000 => fff0000000000000
+#6: xsmindp fff0000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#7: xsmindp fff0000000000000,7ff8000000000000 => fff0000000000000
+#8: xsmindp c0d0650f5a07b353,fff0000000000000 => fff0000000000000
+#9: xsmindp c0d0650f5a07b353,c0d0650f5a07b353 => c0d0650f5a07b353
+#10: xsmindp c0d0650f5a07b353,8000000000000000 => c0d0650f5a07b353
+#11: xsmindp c0d0650f5a07b353,0000000000000000 => c0d0650f5a07b353
+#12: xsmindp c0d0650f5a07b353,0123214569900000 => c0d0650f5a07b353
+#13: xsmindp c0d0650f5a07b353,7ff0000000000000 => c0d0650f5a07b353
+#14: xsmindp c0d0650f5a07b353,7ff7ffffffffffff => 7fffffffffffffff
+#15: xsmindp c0d0650f5a07b353,7ff8000000000000 => c0d0650f5a07b353
+#16: xsmindp 8000000000000000,fff0000000000000 => fff0000000000000
+#17: xsmindp 8000000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#18: xsmindp 8000000000000000,8000000000000000 => 8000000000000000
+#19: xsmindp 8000000000000000,0000000000000000 => 8000000000000000
+#20: xsmindp 8000000000000000,0123214569900000 => 8000000000000000
+#21: xsmindp 8000000000000000,7ff0000000000000 => 8000000000000000
+#22: xsmindp 8000000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#23: xsmindp 8000000000000000,7ff8000000000000 => 8000000000000000
+#24: xsmindp 0000000000000000,fff0000000000000 => fff0000000000000
+#25: xsmindp 0000000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#26: xsmindp 0000000000000000,8000000000000000 => 8000000000000000
+#27: xsmindp 0000000000000000,0000000000000000 => 0000000000000000
+#28: xsmindp 0000000000000000,0123214569900000 => 0000000000000000
+#29: xsmindp 0000000000000000,7ff0000000000000 => 0000000000000000
+#30: xsmindp 0000000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#31: xsmindp 0000000000000000,7ff8000000000000 => 0000000000000000
+#32: xsmindp 0123214569900000,fff0000000000000 => fff0000000000000
+#33: xsmindp 0123214569900000,c0d0650f5a07b353 => c0d0650f5a07b353
+#34: xsmindp 0123214569900000,8000000000000000 => 8000000000000000
+#35: xsmindp 0123214569900000,0000000000000000 => 0000000000000000
+#36: xsmindp 0123214569900000,404f000000000000 => 0123214569900000
+#37: xsmindp 0123214569900000,7ff0000000000000 => 0123214569900000
+#38: xsmindp 0123214569900000,7ff7ffffffffffff => 7fffffffffffffff
+#39: xsmindp 0123214569900000,7ff8000000000000 => 0123214569900000
+#40: xsmindp 7ff0000000000000,fff0000000000000 => fff0000000000000
+#41: xsmindp 7ff0000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#42: xsmindp 7ff0000000000000,8000000000000000 => 8000000000000000
+#43: xsmindp 7ff0000000000000,0000000000000000 => 0000000000000000
+#44: xsmindp 7ff0000000000000,0123214569900000 => 0123214569900000
+#45: xsmindp 7ff0000000000000,7ff0000000000000 => 7ff0000000000000
+#46: xsmindp 7ff0000000000000,7ff7ffffffffffff => 7fffffffffffffff
+#47: xsmindp 7ff0000000000000,7ff8000000000000 => 7ff0000000000000
+#48: xsmindp fff7ffffffffffff,fff0000000000000 => ffffffffffffffff
+#49: xsmindp fff7ffffffffffff,c0d0650f5a07b353 => ffffffffffffffff
+#50: xsmindp fff8000000000000,8000000000000000 => 8000000000000000
+#51: xsmindp fff8000000000000,0000000000000000 => 0000000000000000
+#52: xsmindp fff7ffffffffffff,0123214569900000 => ffffffffffffffff
+#53: xsmindp fff7ffffffffffff,7ff0000000000000 => ffffffffffffffff
+#54: xsmindp fff7ffffffffffff,7ff7ffffffffffff => ffffffffffffffff
+#55: xsmindp fff7ffffffffffff,7ff8000000000000 => ffffffffffffffff
+#56: xsmindp fff8000000000000,fff0000000000000 => fff0000000000000
+#57: xsmindp fff8000000000000,c0d0650f5a07b353 => c0d0650f5a07b353
+#58: xsmindp fff8000000000000,8000000000000000 => 8000000000000000
+#59: xsmindp 41232585a9900000,41382511a2000000 => 41232585a9900000
+#60: xsmindp 41232585a9900000,41382511a2000000 => 41232585a9900000
+#61: xsmindp 7ff7ffffffffffff,7ff8000000000000 => 7fffffffffffffff
+#62: xsmindp 7ff8000000000000,7ff8000000000000 => 7ff8000000000000
+#63: xsmindp 7ff8000000000000,fff8000000000000 => 7ff8000000000000
+
+#0: xscvdpsxws 3fd8000000000000 => 0000000000000000
+#1: xscvdpsxws 404f000000000000 => 000000000000003e
+#2: xscvdpsxws 0018000000b77501 => 0000000000000000
+#3: xscvdpsxws 7fe800000000051b => 000000007fffffff
+#4: xscvdpsxws 0123214569900000 => 0000000000000000
+#5: xscvdpsxws 0000000000000000 => 0000000000000000
+#6: xscvdpsxws 8000000000000000 => 0000000000000000
+#7: xscvdpsxws 7ff0000000000000 => 000000007fffffff
+#8: xscvdpsxws fff0000000000000 => 0000000080000000
+#9: xscvdpsxws 7ff7ffffffffffff => 0000000080000000
+#10: xscvdpsxws fff7ffffffffffff => 0000000080000000
+#11: xscvdpsxws 7ff8000000000000 => 0000000080000000
+#12: xscvdpsxws fff8000000000000 => 0000000080000000
+#13: xscvdpsxws 8008340000078000 => 0000000000000000
+#14: xscvdpsxws c0d0650f5a07b353 => 00000000ffffbe6c
+#15: xscvdpsxws 41232585a9900000 => 00000000000992c2
+#16: xscvdpsxws 41382511a2000000 => 0000000000182511
+
+#0: xscvdpuxds 3fd8000000000000 => 0000000000000000
+#1: xscvdpuxds 404f000000000000 => 000000000000003e
+#2: xscvdpuxds 0018000000b77501 => 0000000000000000
+#3: xscvdpuxds 7fe800000000051b => ffffffffffffffff
+#4: xscvdpuxds 0123214569900000 => 0000000000000000
+#5: xscvdpuxds 0000000000000000 => 0000000000000000
+#6: xscvdpuxds 8000000000000000 => 0000000000000000
+#7: xscvdpuxds 7ff0000000000000 => ffffffffffffffff
+#8: xscvdpuxds fff0000000000000 => 0000000000000000
+#9: xscvdpuxds 7ff7ffffffffffff => 0000000000000000
+#10: xscvdpuxds fff7ffffffffffff => 0000000000000000
+#11: xscvdpuxds 7ff8000000000000 => 0000000000000000
+#12: xscvdpuxds fff8000000000000 => 0000000000000000
+#13: xscvdpuxds 8008340000078000 => 0000000000000000
+#14: xscvdpuxds c0d0650f5a07b353 => 0000000000000000
+#15: xscvdpuxds 41232585a9900000 => 00000000000992c2
+#16: xscvdpuxds 41382511a2000000 => 0000000000182511
+
diff --git a/main/none/tests/ppc64/test_isa_2_06_part2.vgtest b/main/none/tests/ppc64/test_isa_2_06_part2.vgtest
new file mode 100644
index 0000000..7ae01be
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part2.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_06_cap
+prog: test_isa_2_06_part2
diff --git a/main/none/tests/ppc64/test_isa_2_06_part3.c b/main/none/tests/ppc64/test_isa_2_06_part3.c
new file mode 100644
index 0000000..a3639a6
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part3.c
@@ -0,0 +1,1582 @@
+/* Copyright (C) 2011 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#ifdef HAS_VSX
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+#include <math.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int div_flags, div_xer;
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+typedef void (*test_func_t)(void);
+typedef struct test_table test_table_t;
+
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+} fp_test_args_t;
+
+
+fp_test_args_t two_arg_fp_tests[] = {
+ {8, 8},
+ {8, 14},
+ {15, 16},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {12, 6},
+ {12, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 11},
+ {12, 8 },
+ {12, 14},
+ {12, 6},
+ {15, 16},
+ {15, 16},
+ {9, 11},
+ {11, 11},
+ {11, 12},
+ {16, 18},
+ {17, 16},
+ {19, 19},
+ {19, 18}
+};
+
+
+static int nb_special_fargs;
+static double * spec_fargs;
+static float * spec_sp_fargs;
+
+static void build_special_fargs_table(void)
+{
+/*
+ Entry Sign Exp fraction Special value
+ 0 0 3fd 0x8000000000000ULL Positive finite number
+ 1 0 404 0xf000000000000ULL ...
+ 2 0 001 0x8000000b77501ULL ...
+ 3 0 7fe 0x800000000051bULL ...
+ 4 0 012 0x3214569900000ULL ...
+ 5 0 000 0x0000000000000ULL +0.0 (+zero)
+ 6 1 000 0x0000000000000ULL -0.0 (-zero)
+ 7 0 7ff 0x0000000000000ULL +infinity
+ 8 1 7ff 0x0000000000000ULL -infinity
+ 9 0 7ff 0x7FFFFFFFFFFFFULL +SNaN
+ 10 1 7ff 0x7FFFFFFFFFFFFULL -SNaN
+ 11 0 7ff 0x8000000000000ULL +QNaN
+ 12 1 7ff 0x8000000000000ULL -QNaN
+ 13 1 000 0x8340000078000ULL Denormalized val (zero exp and non-zero fraction)
+ 14 1 40d 0x0650f5a07b353ULL Negative finite number
+ 15 0 412 0x32585a9900000ULL A few more positive finite numbers
+ 16 0 413 0x82511a2000000ULL ...
+ 17 . . . . . . . . . . . . . . . . . . . . . . .
+ 18 . . . . . . . . . . . . . . . . . . . . . . .
+ 19 . . . . . . . . . . . . . . . . . . . . . . .
+*/
+
+ uint64_t mant;
+ uint16_t _exp;
+ int s;
+ int j, i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 20 * sizeof(double) );
+ spec_sp_fargs = malloc( 20 * sizeof(float) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +SNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -SNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* A few positive finite numbers ... */
+ // #15
+ s = 0;
+ _exp = 0x412;
+ mant = 0x32585a9900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #16
+ s = 0;
+ _exp = 0x413;
+ mant = 0x82511a2000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #17
+ s = 0;
+ _exp = 0x403;
+ mant = 0x12ef5a9300000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #18
+ s = 0;
+ _exp = 0x405;
+ mant = 0x14bf5d2300000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #19
+ s = 0;
+ _exp = 0x409;
+ mant = 0x76bf982440000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ nb_special_fargs = i;
+ for (j = 0; j < i; j++) {
+ spec_sp_fargs[j] = spec_fargs[j];
+ }
+}
+
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+/* Type of input for floating point operations.*/
+typedef enum {
+ SINGLE_TEST,
+ DOUBLE_TEST
+} precision_type_t;
+
+typedef enum {
+ VX_SCALAR_CONV_TO_WORD,
+ VX_CONV_TO_SINGLE,
+ VX_CONV_TO_DOUBLE,
+ VX_ESTIMATE,
+ VX_DEFAULT
+} vx_fp_test_type;
+
+static vector unsigned int vec_out, vec_inA, vec_inB;
+
+/* This function is for checking the reciprocal and reciprocal square root
+ * estimate instructions.
+ */
+Bool check_estimate(precision_type_t type, Bool is_rsqrte, int idx, int output_vec_idx)
+{
+ /* Technically, the number of bits of precision for xvredp and xvrsqrtedp is
+ * 14 bits (14 = log2 16384). However, the VEX emulation of these instructions
+ * does an actual reciprocal calculation versus estimation, so the answer we get back from
+ * valgrind can easily differ from the estimate in the lower bits (within the 14 bits of
+ * precision) and the estimate may still be within expected tolerances. On top of that,
+ * we can't count on these estimates always being the same across implementations.
+ * For example, with the fre[s] instruction (which should be correct to within one part
+ * in 256 -- i.e., 8 bits of precision) . . . When approximating the value 1.0111_1111_1111,
+ * one implementation could return 1.0111_1111_0000 and another implementation could return
+ * 1.1000_0000_0000. Both estimates meet the 1/256 accuracy requirement, but share only a
+ * single bit in common.
+ *
+ * The upshot is we can't validate the VEX output for these instructions by comparing against
+ * stored bit patterns. We must check that the result is within expected tolerances.
+ */
+
+
+ /* A mask to be used for validation as a last resort.
+ * Only use 12 bits of precision for reasons discussed above.
+ */
+#define VSX_RECIP_ESTIMATE_MASK_DP 0xFFFFFF0000000000ULL
+#define VSX_RECIP_ESTIMATE_MASK_SP 0xFFFFFF00
+
+ Bool result = False;
+ Bool dp_test = type == DOUBLE_TEST;
+ double src_dp, res_dp;
+ float src_sp, res_sp;
+ src_dp = res_dp = 0;
+ src_sp = res_sp = 0;
+#define SRC (dp_test ? src_dp : src_sp)
+#define RES (dp_test ? res_dp : res_sp)
+ Bool src_is_negative = False;
+ Bool res_is_negative = False;
+ unsigned long long * dst_dp = NULL;
+ unsigned int * dst_sp = NULL;
+ if (dp_test) {
+ unsigned long long * src_dp_ull;
+ dst_dp = (unsigned long long *) &vec_out;
+ src_dp = spec_fargs[idx];
+ src_dp_ull = (unsigned long long *) &src_dp;
+ src_is_negative = (*src_dp_ull & 0x8000000000000000ULL) ? True : False;
+ res_is_negative = (dst_dp[output_vec_idx] & 0x8000000000000000ULL) ? True : False;
+ memcpy(&res_dp, &dst_dp[output_vec_idx], 8);
+ } else {
+ unsigned int * src_sp_uint;
+ dst_sp = (unsigned int *) &vec_out;
+ src_sp = spec_sp_fargs[idx];
+ src_sp_uint = (unsigned int *) &src_sp;
+ src_is_negative = (*src_sp_uint & 0x80000000) ? True : False;
+ res_is_negative = (dst_sp[output_vec_idx] & 0x80000000) ? True : False;
+ memcpy(&res_sp, &dst_sp[output_vec_idx], 4);
+ }
+
+ // Below are common rules for xvre{d|s}p and xvrsqrte{d|s}p
+ if (isnan(SRC))
+ return isnan(RES);
+ if (fpclassify(SRC) == FP_ZERO)
+ return isinf(RES);
+ if (!src_is_negative && isinf(SRC))
+ return !res_is_negative && (fpclassify(RES) == FP_ZERO);
+ if (is_rsqrte) {
+ if (src_is_negative)
+ return isnan(RES);
+ } else {
+ if (src_is_negative && isinf(SRC))
+ return res_is_negative && (fpclassify(RES) == FP_ZERO);
+ }
+ if (dp_test) {
+ double calc_diff;
+ double real_diff;
+ double recip_divisor;
+ double div_result;
+ double calc_diff_tmp;
+
+ if (is_rsqrte)
+ recip_divisor = sqrt(src_dp);
+ else
+ recip_divisor = src_dp;
+
+ div_result = 1.0/recip_divisor;
+ calc_diff_tmp = recip_divisor * 16384.0;
+ if (isnormal(calc_diff_tmp)) {
+ calc_diff = fabs(1.0/calc_diff_tmp);
+ real_diff = fabs(res_dp - div_result);
+ result = ( ( res_dp == div_result )
+ || ( real_diff <= calc_diff ) );
+ } else {
+ /* Unable to compute theoretical difference, so we fall back to masking out
+ * un-precise bits.
+ */
+ unsigned long long * div_result_dp = (unsigned long long *) &div_result;
+ result = (dst_dp[output_vec_idx] & VSX_RECIP_ESTIMATE_MASK_DP) == (*div_result_dp & VSX_RECIP_ESTIMATE_MASK_DP);
+ }
+ /* For debug use . . .
+ if (!result) {
+ unsigned long long * dv = &div_result;
+ unsigned long long * rd = &real_diff;
+ unsigned long long * cd = &calc_diff;
+ printf("\n\t {actual div_result: %016llx; real_diff: %016llx; calc_diff: %016llx}\n",
+ *dv, *rd, *cd);
+ }
+ */
+ } else { // single precision test (only have xvrsqrtesp, since xvresp was implemented in stage 2)
+ float calc_diff;
+ float real_diff;
+ float div_result;
+ float calc_diff_tmp;
+ float recip_divisor = sqrt(src_sp);
+
+ div_result = 1.0/recip_divisor;
+ calc_diff_tmp = recip_divisor * 16384.0;
+ if (isnormal(calc_diff_tmp)) {
+ calc_diff = fabsf(1.0/calc_diff_tmp);
+ real_diff = fabsf(res_sp - div_result);
+ result = ( ( res_sp == div_result )
+ || ( real_diff <= calc_diff ) );
+ } else {
+ /* Unable to compute theoretical difference, so we fall back to masking out
+ * un-precise bits.
+ */
+ unsigned int * div_result_sp = (unsigned int *) &div_result;
+ result = (dst_sp[output_vec_idx] & VSX_RECIP_ESTIMATE_MASK_SP) == (*div_result_sp & VSX_RECIP_ESTIMATE_MASK_SP);
+ }
+ /* For debug use . . .
+ if (!result) {
+ unsigned long long * dv = &div_result;
+ unsigned long long * rd = &real_diff;
+ unsigned long long * cd = &calc_diff;
+ printf("\n\t {actual div_result: %016llx; real_diff: %016llx; calc_diff: %016llx}\n",
+ *dv, *rd, *cd);
+ }
+ */
+ }
+ return result;
+}
+
+typedef struct vx_fp_test
+{
+ test_func_t test_func;
+ const char * name;
+ fp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type type;
+ const char * op;
+} vx_fp_test_t;
+
+
+static Bool do_dot;
+
+static void test_xvredp(void)
+{
+ __asm__ __volatile__ ("xvredp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsredp(void)
+{
+ __asm__ __volatile__ ("xsredp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrsqrtedp(void)
+{
+ __asm__ __volatile__ ("xvrsqrtedp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrsqrtedp(void)
+{
+ __asm__ __volatile__ ("xsrsqrtedp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrsqrtesp(void)
+{
+ __asm__ __volatile__ ("xvrsqrtesp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xstsqrtdp(void)
+{
+ __asm__ __volatile__ ("xstsqrtdp cr1, %x0" : : "wa" (vec_inB));
+}
+
+static void test_xvtsqrtdp(void)
+{
+ __asm__ __volatile__ ("xvtsqrtdp cr1, %x0" : : "wa" (vec_inB));
+}
+
+static void test_xvtsqrtsp(void)
+{
+ __asm__ __volatile__ ("xvtsqrtsp cr1, %x0" : : "wa" (vec_inB));
+}
+
+static void test_xvsqrtdp(void)
+{
+ __asm__ __volatile__ ("xvsqrtdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvsqrtsp(void)
+{
+ __asm__ __volatile__ ("xvsqrtsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvtdivdp(void)
+{
+ __asm__ __volatile__ ("xvtdivdp cr1, %x0, %x1" : : "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xvtdivsp(void)
+{
+ __asm__ __volatile__ ("xvtdivsp cr1, %x0, %x1" : : "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xscvdpsp(void)
+{
+ __asm__ __volatile__ ("xscvdpsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvdpuxws(void)
+{
+ __asm__ __volatile__ ("xscvdpuxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvspdp(void)
+{
+ __asm__ __volatile__ ("xscvspdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpsp(void)
+{
+ __asm__ __volatile__ ("xvcvdpsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpuxds(void)
+{
+ __asm__ __volatile__ ("xvcvdpuxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpuxws(void)
+{
+ __asm__ __volatile__ ("xvcvdpuxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspdp(void)
+{
+ __asm__ __volatile__ ("xvcvspdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspsxds(void)
+{
+ __asm__ __volatile__ ("xvcvspsxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspuxds(void)
+{
+ __asm__ __volatile__ ("xvcvspuxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpsxds(void)
+{
+ __asm__ __volatile__ ("xvcvdpsxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspuxws(void)
+{
+ __asm__ __volatile__ ("xvcvspuxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxddp(void)
+{
+ __asm__ __volatile__ ("xvcvsxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxddp(void)
+{
+ __asm__ __volatile__ ("xvcvuxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxdsp(void)
+{
+ __asm__ __volatile__ ("xvcvsxdsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxdsp(void)
+{
+ __asm__ __volatile__ ("xvcvuxdsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxwdp(void)
+{
+ __asm__ __volatile__ ("xvcvsxwdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxwdp(void)
+{
+ __asm__ __volatile__ ("xvcvuxwdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxwsp(void)
+{
+ __asm__ __volatile__ ("xvcvsxwsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxwsp(void)
+{
+ __asm__ __volatile__ ("xvcvuxwsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpic(void)
+{
+ __asm__ __volatile__ ("xsrdpic %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpiz(void)
+{
+ __asm__ __volatile__ ("xsrdpiz %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpi(void)
+{
+ __asm__ __volatile__ ("xsrdpi %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvabsdp(void)
+{
+ __asm__ __volatile__ ("xvabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvnabsdp(void)
+{
+ __asm__ __volatile__ ("xvnabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvnegdp(void)
+{
+ __asm__ __volatile__ ("xvnegdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvabssp(void)
+{
+ __asm__ __volatile__ ("xvabssp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvnabssp(void)
+{
+ __asm__ __volatile__ ("xvnabssp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpi(void)
+{
+ __asm__ __volatile__ ("xvrdpi %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpic(void)
+{
+ __asm__ __volatile__ ("xvrdpic %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpim(void)
+{
+ __asm__ __volatile__ ("xvrdpim %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpip(void)
+{
+ __asm__ __volatile__ ("xvrdpip %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpiz(void)
+{
+ __asm__ __volatile__ ("xvrdpiz %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspi(void)
+{
+ __asm__ __volatile__ ("xvrspi %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspic(void)
+{
+ __asm__ __volatile__ ("xvrspic %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspim(void)
+{
+ __asm__ __volatile__ ("xvrspim %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspip(void)
+{
+ __asm__ __volatile__ ("xvrspip %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspiz(void)
+{
+ __asm__ __volatile__ ("xvrspiz %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static vx_fp_test_t
+vsx_one_fp_arg_tests[] = {
+ { &test_xvredp, "xvredp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
+ { &test_xsredp, "xsredp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
+ { &test_xvrsqrtedp, "xvrsqrtedp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x-sqrt"},
+ { &test_xsrsqrtedp, "xsrsqrtedp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x-sqrt"},
+ { &test_xvrsqrtesp, "xvrsqrtesp", NULL, 18, SINGLE_TEST, VX_ESTIMATE, "1/x-sqrt"},
+ { &test_xvsqrtdp, "xvsqrtdp", NULL, 18, DOUBLE_TEST, VX_DEFAULT, "sqrt"},
+ { &test_xvsqrtsp, "xvsqrtsp", NULL, 18, SINGLE_TEST, VX_DEFAULT, "sqrt"},
+ { &test_xscvdpsp, "xscvdpsp", NULL, 20, DOUBLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xscvdpuxws, "xscvdpuxws", NULL, 20, DOUBLE_TEST, VX_SCALAR_CONV_TO_WORD, "conv"},
+ { &test_xscvspdp, "xscvspdp", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvdpsp, "xvcvdpsp", NULL, 20, DOUBLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xvcvdpuxds, "xvcvdpuxds", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvdpuxws, "xvcvdpuxws", NULL, 20, DOUBLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xvcvspdp, "xvcvspdp", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvspsxds, "xvcvspsxds", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvdpsxds, "xvcvdpsxds", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvspuxds, "xvcvspuxds", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvspuxws, "xvcvspuxws", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xsrdpic, "xsrdpic", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xsrdpiz, "xsrdpiz", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xsrdpi, "xsrdpi", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvabsdp, "xvabsdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "abs"},
+ { &test_xvnabsdp, "xvnabsdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "nabs"},
+ { &test_xvnegdp, "xvnegdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "neg"},
+ { &test_xvabssp, "xvabssp", NULL, 20, SINGLE_TEST, VX_DEFAULT, "abs"},
+ { &test_xvnabssp, "xvnabssp", NULL, 20, SINGLE_TEST, VX_DEFAULT, "nabs"},
+ { &test_xvrdpi, "xvrdpi", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpic, "xvrdpic", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpim, "xvrdpim", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpip, "xvrdpip", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpiz, "xvrdpiz", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrspi, "xvrspi", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspic, "xvrspic", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspim, "xvrspim", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspip, "xvrspip", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspiz, "xvrspiz", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { NULL, NULL, NULL, 0, 0, 0, NULL}
+};
+
+static vx_fp_test_t
+vx_tdivORtsqrt_tests[] = {
+ { &test_xstsqrtdp, "xstsqrtdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "test-sqrt"},
+ { &test_xvtsqrtdp, "xvtsqrtdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "test-sqrt"},
+ { &test_xvtsqrtsp, "xvtsqrtsp", NULL, 20, SINGLE_TEST, VX_DEFAULT, "test-sqrt"},
+ { &test_xvtdivdp, "xvtdivdp", two_arg_fp_tests, 68, DOUBLE_TEST, VX_DEFAULT, "test-div"},
+ { &test_xvtdivsp, "xvtdivsp", two_arg_fp_tests, 68, SINGLE_TEST, VX_DEFAULT, "test-div"},
+ { NULL, NULL, NULL, 0 , 0, 0, NULL}
+};
+
+static unsigned long long doubleWord[] = { 0,
+ 0xffffffff00000000LL,
+ 0x00000000ffffffffLL,
+ 0xffffffffffffffffLL,
+ 0x89abcde123456789LL,
+ 0x0102030405060708LL,
+ 0x00000000a0b1c2d3LL,
+ 0x1111222233334444LL
+};
+
+static unsigned int singleWord[] = {0,
+ 0xffff0000,
+ 0x0000ffff,
+ 0xffffffff,
+ 0x89a73522,
+ 0x01020304,
+ 0x0000abcd,
+ 0x11223344
+};
+
+typedef struct vx_intToFp_test
+{
+ test_func_t test_func;
+ const char * name;
+ void * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type type;
+} vx_intToFp_test_t;
+
+static vx_intToFp_test_t
+intToFp_tests[] = {
+ { test_xvcvsxddp, "xvcvsxddp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvuxddp, "xvcvuxddp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvsxdsp, "xvcvsxdsp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_SINGLE },
+ { test_xvcvuxdsp, "xvcvuxdsp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_SINGLE },
+ { test_xvcvsxwdp, "xvcvsxwdp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvuxwdp, "xvcvuxwdp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvsxwsp, "xvcvsxwsp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_SINGLE },
+ { test_xvcvuxwsp, "xvcvuxwsp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_SINGLE },
+ { NULL, NULL, NULL, 0, 0 }
+};
+
+static Bool do_OE;
+typedef enum {
+ DIV_BASE = 1,
+ DIV_OE = 2,
+ DIV_DOT = 4,
+} div_type_t;
+/* Possible divde type combinations are:
+ * - base
+ * - base+dot
+ * - base+OE
+ * - base+OE+dot
+ */
+#ifdef __powerpc64__
+static void test_divdeu(void)
+{
+ int divdeu_type = DIV_BASE;
+ if (do_OE)
+ divdeu_type |= DIV_OE;
+ if (do_dot)
+ divdeu_type |= DIV_DOT;
+
+ switch (divdeu_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeu %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeuo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeu. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeuo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divdeu type. Exiting\n");
+ exit(1);
+ }
+}
+#endif
+
+static void test_divwe(void)
+{
+ int divwe_type = DIV_BASE;
+ if (do_OE)
+ divwe_type |= DIV_OE;
+ if (do_dot)
+ divwe_type |= DIV_DOT;
+
+ switch (divwe_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divwe %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divwe. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divweu type. Exiting\n");
+ exit(1);
+ }
+}
+
+
+typedef struct simple_test {
+ test_func_t test_func;
+ char * name;
+ precision_type_t precision;
+} simple_test_t;
+
+
+static void setup_sp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? &vec_out : &vec_inB;
+
+ for (i = 0; i < 4; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_sp_fargs[a_idx];
+ inB = (void *)&spec_sp_fargs[b_idx];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 4), inA, 4);
+ memcpy(vec_src + (i * 4), inB, 4);
+ targs++;
+ }
+}
+
+static void setup_dp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? (void *)&vec_out : (void *)&vec_inB;
+
+ for (i = 0; i < 2; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_fargs[a_idx];
+ inB = (void *)&spec_fargs[b_idx];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 8), inA, 8);
+ memcpy(vec_src + (i * 8), inB, 8);
+ targs++;
+ }
+}
+
+#define VX_NOT_CMP_OP 0xffffffff
+static void print_vector_fp_result(unsigned int cc, vx_fp_test_t * test_group, int i, Bool print_vec_out)
+{
+ int a_idx, b_idx, k;
+ char * name = malloc(20);
+ int dp = test_group->precision == DOUBLE_TEST ? 1 : 0;
+ int loops = dp ? 2 : 4;
+ fp_test_args_t * targs = &test_group->targs[i];
+ unsigned long long * frA_dp, * frB_dp, * dst_dp;
+ unsigned int * frA_sp, *frB_sp, * dst_sp;
+ strcpy(name, test_group->name);
+ printf("#%d: %s%s ", dp? i/2 : i/4, name, (do_dot ? "." : ""));
+ for (k = 0; k < loops; k++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ if (k)
+ printf(" AND ");
+ if (dp) {
+ frA_dp = (unsigned long long *)&spec_fargs[a_idx];
+ frB_dp = (unsigned long long *)&spec_fargs[b_idx];
+ printf("%016llx %s %016llx", *frA_dp, test_group->op, *frB_dp);
+ } else {
+ frA_sp = (unsigned int *)&spec_sp_fargs[a_idx];
+ frB_sp = (unsigned int *)&spec_sp_fargs[b_idx];
+ printf("%08x %s %08x", *frA_sp, test_group->op, *frB_sp);
+ }
+ targs++;
+ }
+ if (cc != VX_NOT_CMP_OP)
+ printf(" ? cc=%x", cc);
+
+ if (print_vec_out) {
+ if (dp) {
+ dst_dp = (unsigned long long *) &vec_out;
+ printf(" => %016llx %016llx\n", dst_dp[0], dst_dp[1]);
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ printf(" => %08x %08x %08x %08x\n", dst_sp[0], dst_sp[1], dst_sp[2], dst_sp[3]);
+ }
+ } else {
+ printf("\n");
+ }
+ free(name);
+}
+
+
+
+static void test_vsx_one_fp_arg(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vsx_one_fp_arg_tests[k].test_func)) {
+ int idx, i;
+ vx_fp_test_t test_group = vsx_one_fp_arg_tests[k];
+ Bool estimate = (test_group.type == VX_ESTIMATE);
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool is_sqrt = (strstr(test_group.name, "sqrt")) ? True : False;
+ Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False;
+ Bool sparse_sp = False;
+ int stride = dp ? 2 : 4;
+ int loops = is_scalar ? 1 : stride;
+ stride = is_scalar ? 1: stride;
+
+ /* For conversions of single to double, the 128-bit input register is sparsely populated:
+ * |___ SP___|_Unused_|___SP___|__Unused__| // for vector op
+ * or
+ * |___ SP___|_Unused_|_Unused_|__Unused__| // for scalar op
+ *
+ * For the vector op case, we need to adjust stride from '4' to '2', since
+ * we'll only be loading two values per loop into the input register.
+ */
+ if (!dp && !is_scalar && test_group.type == VX_CONV_TO_DOUBLE) {
+ sparse_sp = True;
+ stride = 2;
+ }
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long * frB_dp, *dst_dp;
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ if (estimate) {
+ Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, j);
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
+ /* For debugging . . .
+ printf(" ==> %s (res=%016llx)", res ? "PASS" : "FAIL", dst_dp[j]);
+ */
+ } else {
+ vx_fp_test_type type = test_group.type;
+ switch (type) {
+ case VX_SCALAR_CONV_TO_WORD:
+ printf(" = %016llx", dst_dp[j] & 0x00000000ffffffffULL);
+ break;
+ case VX_CONV_TO_SINGLE:
+ printf(" = %016llx", dst_dp[j] & 0xffffffff00000000ULL);
+ break;
+ default: // For VX_CONV_TO_DOUBLE and non-convert instructions . . .
+ printf(" = %016llx", dst_dp[j]);
+ }
+ }
+ }
+ printf("\n");
+ } else {
+ int j, skip_slot;
+ unsigned int * frB_sp, * dst_sp = NULL;
+ unsigned long long * dst_dp = NULL;
+ if (sparse_sp) {
+ skip_slot = 1;
+ loops = 2;
+ } else {
+ skip_slot = 0;
+ }
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+ if (skip_slot && j > 0)
+ memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
+ else
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ // execute test insn
+ (*func)();
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ dst_dp = (unsigned long long *) &vec_out;
+ else
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ if (estimate) {
+ Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, j);
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
+ } else {
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ printf(" = %016llx", dst_dp[j]);
+ else
+ /* Special case: Current VEX implementation for fsqrts (single precision)
+ * uses the same implementation as that used for double precision fsqrt.
+ * However, I've found that for xvsqrtsp, the result from that implementation
+ * may be off by the two LSBs. Generally, even this small inaccuracy can cause the
+ * output to appear very different if you end up with a carry. But for the given
+ * inputs in this testcase, we can simply mask out these bits.
+ */
+ printf(" = %08x", is_sqrt ? (dst_sp[j] & 0xfffffffc) : dst_sp[j]);
+ }
+ }
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_int_to_fp_convert(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = intToFp_tests[k].test_func)) {
+ int idx, i;
+ vx_intToFp_test_t test_group = intToFp_tests[k];
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool sparse_sp = False;
+ int stride = dp ? 2 : 4;
+ int loops = stride;
+
+ /* For conversions of single to double, the 128-bit input register is sparsely populated:
+ * |___ int___|_Unused_|___int___|__Unused__| // for vector op
+ * or
+ * We need to adjust stride from '4' to '2', since we'll only be loading
+ * two values per loop into the input register.
+ */
+ if (!dp && test_group.type == VX_CONV_TO_DOUBLE) {
+ sparse_sp = True;
+ stride = 2;
+ }
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long *dst_dw, * targs = test_group.targs;
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&targs[i + j];
+ // copy doubleword into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dw = (unsigned long long *) &vec_out;
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ printf("conv(%016llx)", targs[i + j]);
+
+ if (test_group.type == VX_CONV_TO_SINGLE)
+ printf(" = %016llx", dst_dw[j] & 0xffffffff00000000ULL);
+ else
+ printf(" = %016llx", dst_dw[j]);
+ }
+ printf("\n");
+ } else {
+ int j, skip_slot;
+ unsigned int * dst_sp = NULL;
+ unsigned int * targs = test_group.targs;
+ unsigned long long * dst_dp = NULL;
+ if (sparse_sp) {
+ skip_slot = 1;
+ loops = 2;
+ } else {
+ skip_slot = 0;
+ }
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&targs[i + j];
+ // copy single word into vector element i
+ if (skip_slot && j > 0)
+ memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
+ else
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ // execute test insn
+ (*func)();
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ dst_dp = (unsigned long long *) &vec_out;
+ else
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ printf("conv(%08x)", targs[i + j]);
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ printf(" = %016llx", dst_dp[j]);
+ else
+ printf(" = %08x", dst_sp[j]);
+ }
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+
+// The div doubleword test data
+signed long long div_dw_tdata[13][2] = {
+ { 4, -4 },
+ { 4, -3 },
+ { 4, 4 },
+ { 4, -5 },
+ { 3, 8 },
+ { 0x8000000000000000ULL, 0xa },
+ { 0x50c, -1 },
+ { 0x50c, -4096 },
+ { 0x1234fedc, 0x8000a873 },
+ { 0xabcd87651234fedcULL, 0xa123b893 },
+ { 0x123456789abdcULL, 0 },
+ { 0, 2 },
+ { 0x77, 0xa3499 }
+};
+#define dw_tdata_len (sizeof(div_dw_tdata)/sizeof(signed long long)/2)
+
+// The div word test data
+unsigned int div_w_tdata[6][2] = {
+ { 0, 2 },
+ { 2, 0 },
+ { 0x7abc1234, 0xf0000000 },
+ { 0xfabc1234, 5 },
+ { 77, 66 },
+ { 5, 0xfabc1234 },
+};
+#define w_tdata_len (sizeof(div_w_tdata)/sizeof(unsigned int)/2)
+
+typedef struct div_ext_test
+{
+ test_func_t test_func;
+ const char *name;
+ int num_tests;
+ div_type_t div_type;
+ precision_type_t precision;
+} div_ext_test_t;
+
+static div_ext_test_t div_tests[] = {
+#ifdef __powerpc64__
+ { &test_divdeu, "divdeu", dw_tdata_len, DIV_BASE, DOUBLE_TEST },
+ { &test_divdeu, "divdeuo", dw_tdata_len, DIV_OE, DOUBLE_TEST },
+#endif
+ { &test_divwe, "divwe", w_tdata_len, DIV_BASE, SINGLE_TEST },
+ { &test_divwe, "divweo", w_tdata_len, DIV_OE, SINGLE_TEST },
+ { NULL, NULL, 0, 0, 0 }
+};
+
+static void test_div_extensions(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = div_tests[k].test_func)) {
+ int i, repeat = 1;
+ div_ext_test_t test_group = div_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int condreg;
+
+ if (test_group.div_type == DIV_OE)
+ do_OE = True;
+ else
+ do_OE = False;
+
+ if (test_group.precision == DOUBLE_TEST) {
+ r14 = div_dw_tdata[i][0];
+ r15 = div_dw_tdata[i][1];
+ } else {
+ r14 = div_w_tdata[i][0];
+ r15 = div_w_tdata[i][1];
+ }
+ // execute test insn
+ (*func)();
+ condreg = (div_flags & 0xf0000000) >> 28;
+ printf("#%d: %s%s: ", i, test_group.name, do_dot ? "." : "");
+ if (test_group.precision == DOUBLE_TEST) {
+ printf("0x%016llx0000000000000000 / 0x%016llx = 0x%016llx;",
+ div_dw_tdata[i][0], div_dw_tdata[i][1], (signed long long) r17);
+ } else {
+ printf("0x%08x00000000 / 0x%08x = 0x%08x;",
+ div_w_tdata[i][0], div_w_tdata[i][1], (unsigned int) r17);
+ }
+ printf(" CR=%x; XER=%x\n", condreg, div_xer);
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static void test_vx_tdivORtsqrt(void)
+{
+ test_func_t func;
+ int k, crx;
+ unsigned int flags;
+ k = 0;
+ do_dot = False;
+ build_special_fargs_table();
+
+ while ((func = vx_tdivORtsqrt_tests[k].test_func)) {
+ int idx, i;
+ vx_fp_test_t test_group = vx_tdivORtsqrt_tests[k];
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False;
+ Bool two_args = test_group.targs ? True : False;
+ int stride = dp ? 2 : 4;
+ int loops = is_scalar ? 1 : stride;
+ stride = is_scalar ? 1: stride;
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long * frB_dp;
+ if (two_args) {
+ setup_dp_fp_args(&test_group.targs[i], False);
+ } else {
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ }
+ // execute test insn
+ // Must do set/get of CRs immediately before/after calling the asm func
+ // to avoid CRs being modified by other instructions.
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ // assumes using CR1
+ crx = (flags & 0x0f000000) >> 24;
+ if (two_args) {
+ print_vector_fp_result(crx, &test_group, i, False/*do not print vec_out*/);
+ } else {
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ }
+ printf( " ? %x (CRx)\n", crx);
+ }
+ } else {
+ int j;
+ unsigned int * frB_sp;
+ if (two_args) {
+ setup_sp_fp_args(&test_group.targs[i], False);
+ } else {
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ }
+ // execute test insn
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ crx = (flags & 0x0f000000) >> 24;
+ // print result
+ if (two_args) {
+ print_vector_fp_result(crx, &test_group, i, False/*do not print vec_out*/);
+ } else {
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ }
+ printf( " ? %x (CRx)\n", crx);
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static void test_ftsqrt(void)
+{
+ int i, crx;
+ unsigned int flags;
+ unsigned long long * frbp;
+ build_special_fargs_table();
+
+
+ for (i = 0; i < nb_special_fargs; i++) {
+ f14 = spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("ftsqrt cr1, %0" : : "d" (f14));
+ GET_CR(flags);
+ crx = (flags & 0x0f000000) >> 24;
+ printf( "ftsqrt: %016llx ? %x (CRx)\n", *frbp, crx);
+ }
+ printf( "\n" );
+}
+
+static void
+test_popcntw(void)
+{
+#ifdef __powerpc64__
+ uint64_t res;
+ unsigned long long src = 0x9182736405504536ULL;
+ r14 = src;
+ __asm__ __volatile__ ("popcntw %0, %1" : "=r" (res): "r" (r14));
+ printf("popcntw: 0x%llx => 0x%016llx\n", (unsigned long long)src, (unsigned long long)res);
+#else
+ uint32_t res;
+ unsigned int src = 0x9182730E;
+ r14 = src;
+ __asm__ __volatile__ ("popcntw %0, %1" : "=r" (res): "r" (r14));
+ printf("popcntw: 0x%x => 0x%08x\n", src, (int)res);
+#endif
+ printf( "\n" );
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+
+ { &test_vsx_one_fp_arg,
+ "Test VSX vector and scalar single argument instructions"} ,
+ { &test_int_to_fp_convert,
+ "Test VSX vector integer to float conversion instructions" },
+ { &test_div_extensions,
+ "Test div extensions" },
+ { &test_ftsqrt,
+ "Test ftsqrt instruction" },
+ { &test_vx_tdivORtsqrt,
+ "Test vector and scalar tdiv and tsqrt instructions" },
+ { &test_popcntw,
+ "Test popcntw instruction" },
+ { NULL, NULL }
+};
+#endif // HAS_VSX
+
+int main(int argc, char *argv[])
+{
+#ifdef HAS_VSX
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+ if (spec_fargs)
+ free(spec_fargs);
+ if (spec_sp_fargs)
+ free(spec_sp_fargs);
+
+#endif // HAS _VSX
+
+ return 0;
+}
diff --git a/main/none/tests/ppc64/test_isa_2_06_part3.stderr.exp b/main/none/tests/ppc64/test_isa_2_06_part3.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part3.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/ppc64/test_isa_2_06_part3.stdout.exp b/main/none/tests/ppc64/test_isa_2_06_part3.stdout.exp
new file mode 100644
index 0000000..c3da39f
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part3.stdout.exp
@@ -0,0 +1,663 @@
+Test VSX vector and scalar single argument instructions
+#0: xvredp 1/x(3fd8000000000000) ==> PASS); 1/x(404f000000000000) ==> PASS)
+#1: xvredp 1/x(0018000000b77501) ==> PASS); 1/x(7fe800000000051b) ==> PASS)
+#2: xvredp 1/x(0123214569900000) ==> PASS); 1/x(0000000000000000) ==> PASS)
+#3: xvredp 1/x(8000000000000000) ==> PASS); 1/x(7ff0000000000000) ==> PASS)
+#4: xvredp 1/x(fff0000000000000) ==> PASS); 1/x(7ff7ffffffffffff) ==> PASS)
+#5: xvredp 1/x(fff7ffffffffffff) ==> PASS); 1/x(7ff8000000000000) ==> PASS)
+#6: xvredp 1/x(fff8000000000000) ==> PASS); 1/x(8008340000078000) ==> PASS)
+#7: xvredp 1/x(c0d0650f5a07b353) ==> PASS); 1/x(41232585a9900000) ==> PASS)
+#8: xvredp 1/x(41382511a2000000) ==> PASS); 1/x(40312ef5a9300000) ==> PASS)
+
+#0: xsredp 1/x(3fd8000000000000) ==> PASS)
+#1: xsredp 1/x(404f000000000000) ==> PASS)
+#2: xsredp 1/x(0018000000b77501) ==> PASS)
+#3: xsredp 1/x(7fe800000000051b) ==> PASS)
+#4: xsredp 1/x(0123214569900000) ==> PASS)
+#5: xsredp 1/x(0000000000000000) ==> PASS)
+#6: xsredp 1/x(8000000000000000) ==> PASS)
+#7: xsredp 1/x(7ff0000000000000) ==> PASS)
+#8: xsredp 1/x(fff0000000000000) ==> PASS)
+#9: xsredp 1/x(7ff7ffffffffffff) ==> PASS)
+#10: xsredp 1/x(fff7ffffffffffff) ==> PASS)
+#11: xsredp 1/x(7ff8000000000000) ==> PASS)
+#12: xsredp 1/x(fff8000000000000) ==> PASS)
+#13: xsredp 1/x(8008340000078000) ==> PASS)
+#14: xsredp 1/x(c0d0650f5a07b353) ==> PASS)
+#15: xsredp 1/x(41232585a9900000) ==> PASS)
+#16: xsredp 1/x(41382511a2000000) ==> PASS)
+#17: xsredp 1/x(40312ef5a9300000) ==> PASS)
+
+#0: xvrsqrtedp 1/x-sqrt(3fd8000000000000) ==> PASS); 1/x-sqrt(404f000000000000) ==> PASS)
+#1: xvrsqrtedp 1/x-sqrt(0018000000b77501) ==> PASS); 1/x-sqrt(7fe800000000051b) ==> PASS)
+#2: xvrsqrtedp 1/x-sqrt(0123214569900000) ==> PASS); 1/x-sqrt(0000000000000000) ==> PASS)
+#3: xvrsqrtedp 1/x-sqrt(8000000000000000) ==> PASS); 1/x-sqrt(7ff0000000000000) ==> PASS)
+#4: xvrsqrtedp 1/x-sqrt(fff0000000000000) ==> PASS); 1/x-sqrt(7ff7ffffffffffff) ==> PASS)
+#5: xvrsqrtedp 1/x-sqrt(fff7ffffffffffff) ==> PASS); 1/x-sqrt(7ff8000000000000) ==> PASS)
+#6: xvrsqrtedp 1/x-sqrt(fff8000000000000) ==> PASS); 1/x-sqrt(8008340000078000) ==> PASS)
+#7: xvrsqrtedp 1/x-sqrt(c0d0650f5a07b353) ==> PASS); 1/x-sqrt(41232585a9900000) ==> PASS)
+#8: xvrsqrtedp 1/x-sqrt(41382511a2000000) ==> PASS); 1/x-sqrt(40312ef5a9300000) ==> PASS)
+
+#0: xsrsqrtedp 1/x-sqrt(3fd8000000000000) ==> PASS)
+#1: xsrsqrtedp 1/x-sqrt(404f000000000000) ==> PASS)
+#2: xsrsqrtedp 1/x-sqrt(0018000000b77501) ==> PASS)
+#3: xsrsqrtedp 1/x-sqrt(7fe800000000051b) ==> PASS)
+#4: xsrsqrtedp 1/x-sqrt(0123214569900000) ==> PASS)
+#5: xsrsqrtedp 1/x-sqrt(0000000000000000) ==> PASS)
+#6: xsrsqrtedp 1/x-sqrt(8000000000000000) ==> PASS)
+#7: xsrsqrtedp 1/x-sqrt(7ff0000000000000) ==> PASS)
+#8: xsrsqrtedp 1/x-sqrt(fff0000000000000) ==> PASS)
+#9: xsrsqrtedp 1/x-sqrt(7ff7ffffffffffff) ==> PASS)
+#10: xsrsqrtedp 1/x-sqrt(fff7ffffffffffff) ==> PASS)
+#11: xsrsqrtedp 1/x-sqrt(7ff8000000000000) ==> PASS)
+#12: xsrsqrtedp 1/x-sqrt(fff8000000000000) ==> PASS)
+#13: xsrsqrtedp 1/x-sqrt(8008340000078000) ==> PASS)
+#14: xsrsqrtedp 1/x-sqrt(c0d0650f5a07b353) ==> PASS)
+#15: xsrsqrtedp 1/x-sqrt(41232585a9900000) ==> PASS)
+#16: xsrsqrtedp 1/x-sqrt(41382511a2000000) ==> PASS)
+#17: xsrsqrtedp 1/x-sqrt(40312ef5a9300000) ==> PASS)
+
+#0: xvrsqrtesp 1/x-sqrt(3ec00000) ==> PASS); 1/x-sqrt(42780000) ==> PASS); 1/x-sqrt(00000000) ==> PASS); 1/x-sqrt(7f800000) ==> PASS)
+#1: xvrsqrtesp 1/x-sqrt(00000000) ==> PASS); 1/x-sqrt(00000000) ==> PASS); 1/x-sqrt(80000000) ==> PASS); 1/x-sqrt(7f800000) ==> PASS)
+#2: xvrsqrtesp 1/x-sqrt(ff800000) ==> PASS); 1/x-sqrt(7fffffff) ==> PASS); 1/x-sqrt(ffffffff) ==> PASS); 1/x-sqrt(7fc00000) ==> PASS)
+#3: xvrsqrtesp 1/x-sqrt(ffc00000) ==> PASS); 1/x-sqrt(80000000) ==> PASS); 1/x-sqrt(c683287b) ==> PASS); 1/x-sqrt(49192c2d) ==> PASS)
+#4: xvrsqrtesp 1/x-sqrt(49c1288d) ==> PASS); 1/x-sqrt(418977ad) ==> PASS); 1/x-sqrt(428a5faf) ==> PASS); 1/x-sqrt(44bb5fcc) ==> PASS)
+
+#0: xvsqrtdp sqrt(3fd8000000000000) = 3fe3988e1409212e; sqrt(404f000000000000) = 401f7efbeb8d4f12
+#1: xvsqrtdp sqrt(0018000000b77501) = 2003988e14540690; sqrt(7fe800000000051b) = 5febb67ae8584f9d
+#2: xvsqrtdp sqrt(0123214569900000) = 2088bde98d60ebe6; sqrt(0000000000000000) = 0000000000000000
+#3: xvsqrtdp sqrt(8000000000000000) = 8000000000000000; sqrt(7ff0000000000000) = 7ff0000000000000
+#4: xvsqrtdp sqrt(fff0000000000000) = 7ff8000000000000; sqrt(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvsqrtdp sqrt(fff7ffffffffffff) = ffffffffffffffff; sqrt(7ff8000000000000) = 7ff8000000000000
+#6: xvsqrtdp sqrt(fff8000000000000) = fff8000000000000; sqrt(8008340000078000) = 7ff8000000000000
+#7: xvsqrtdp sqrt(c0d0650f5a07b353) = 7ff8000000000000; sqrt(41232585a9900000) = 4088c0a9258a4a8b
+#8: xvsqrtdp sqrt(41382511a2000000) = 4093a7aa60f34e85; sqrt(40312ef5a9300000) = 401094c71dec3a9c
+
+#0: xvsqrtsp sqrt(3ec00000) = 3f1cc470; sqrt(42780000) = 40fbf7dc; sqrt(00000000) = 00000000; sqrt(7f800000) = 7f800000
+#1: xvsqrtsp sqrt(00000000) = 00000000; sqrt(00000000) = 00000000; sqrt(80000000) = 80000000; sqrt(7f800000) = 7f800000
+#2: xvsqrtsp sqrt(ff800000) = 7fc00000; sqrt(7fffffff) = 7ffffffc; sqrt(ffffffff) = fffffffc; sqrt(7fc00000) = 7fc00000
+#3: xvsqrtsp sqrt(ffc00000) = ffc00000; sqrt(80000000) = 80000000; sqrt(c683287b) = 7fc00000; sqrt(49192c2d) = 44460548
+#4: xvsqrtsp sqrt(49c1288d) = 449d3d50; sqrt(418977ad) = 4084a638; sqrt(428a5faf) = 410515f8; sqrt(44bb5fcc) = 421ade08
+
+#0: xscvdpsp conv(3fd8000000000000) = 3ec0000000000000
+#1: xscvdpsp conv(404f000000000000) = 4278000000000000
+#2: xscvdpsp conv(0018000000b77501) = 0000000000000000
+#3: xscvdpsp conv(7fe800000000051b) = 7f80000000000000
+#4: xscvdpsp conv(0123214569900000) = 0000000000000000
+#5: xscvdpsp conv(0000000000000000) = 0000000000000000
+#6: xscvdpsp conv(8000000000000000) = 8000000000000000
+#7: xscvdpsp conv(7ff0000000000000) = 7f80000000000000
+#8: xscvdpsp conv(fff0000000000000) = ff80000000000000
+#9: xscvdpsp conv(7ff7ffffffffffff) = 7fffffff00000000
+#10: xscvdpsp conv(fff7ffffffffffff) = ffffffff00000000
+#11: xscvdpsp conv(7ff8000000000000) = 7fc0000000000000
+#12: xscvdpsp conv(fff8000000000000) = ffc0000000000000
+#13: xscvdpsp conv(8008340000078000) = 8000000000000000
+#14: xscvdpsp conv(c0d0650f5a07b353) = c683287b00000000
+#15: xscvdpsp conv(41232585a9900000) = 49192c2d00000000
+#16: xscvdpsp conv(41382511a2000000) = 49c1288d00000000
+#17: xscvdpsp conv(40312ef5a9300000) = 418977ad00000000
+#18: xscvdpsp conv(40514bf5d2300000) = 428a5faf00000000
+#19: xscvdpsp conv(40976bf982440000) = 44bb5fcc00000000
+
+#0: xscvdpuxws conv(3fd8000000000000) = 0000000000000000
+#1: xscvdpuxws conv(404f000000000000) = 000000000000003e
+#2: xscvdpuxws conv(0018000000b77501) = 0000000000000000
+#3: xscvdpuxws conv(7fe800000000051b) = 00000000ffffffff
+#4: xscvdpuxws conv(0123214569900000) = 0000000000000000
+#5: xscvdpuxws conv(0000000000000000) = 0000000000000000
+#6: xscvdpuxws conv(8000000000000000) = 0000000000000000
+#7: xscvdpuxws conv(7ff0000000000000) = 00000000ffffffff
+#8: xscvdpuxws conv(fff0000000000000) = 0000000000000000
+#9: xscvdpuxws conv(7ff7ffffffffffff) = 0000000000000000
+#10: xscvdpuxws conv(fff7ffffffffffff) = 0000000000000000
+#11: xscvdpuxws conv(7ff8000000000000) = 0000000000000000
+#12: xscvdpuxws conv(fff8000000000000) = 0000000000000000
+#13: xscvdpuxws conv(8008340000078000) = 0000000000000000
+#14: xscvdpuxws conv(c0d0650f5a07b353) = 0000000000000000
+#15: xscvdpuxws conv(41232585a9900000) = 00000000000992c2
+#16: xscvdpuxws conv(41382511a2000000) = 0000000000182511
+#17: xscvdpuxws conv(40312ef5a9300000) = 0000000000000011
+#18: xscvdpuxws conv(40514bf5d2300000) = 0000000000000045
+#19: xscvdpuxws conv(40976bf982440000) = 00000000000005da
+
+#0: xscvspdp conv(3ec00000) = 3fd8000000000000
+#1: xscvspdp conv(42780000) = 404f000000000000
+#2: xscvspdp conv(00000000) = 0000000000000000
+#3: xscvspdp conv(7f800000) = 7ff0000000000000
+#4: xscvspdp conv(00000000) = 0000000000000000
+#5: xscvspdp conv(00000000) = 0000000000000000
+#6: xscvspdp conv(80000000) = 8000000000000000
+#7: xscvspdp conv(7f800000) = 7ff0000000000000
+#8: xscvspdp conv(ff800000) = fff0000000000000
+#9: xscvspdp conv(7fffffff) = 7fffffffe0000000
+#10: xscvspdp conv(ffffffff) = ffffffffe0000000
+#11: xscvspdp conv(7fc00000) = 7ff8000000000000
+#12: xscvspdp conv(ffc00000) = fff8000000000000
+#13: xscvspdp conv(80000000) = 8000000000000000
+#14: xscvspdp conv(c683287b) = c0d0650f60000000
+#15: xscvspdp conv(49192c2d) = 41232585a0000000
+#16: xscvspdp conv(49c1288d) = 41382511a0000000
+#17: xscvspdp conv(418977ad) = 40312ef5a0000000
+#18: xscvspdp conv(428a5faf) = 40514bf5e0000000
+#19: xscvspdp conv(44bb5fcc) = 40976bf980000000
+
+#0: xvcvdpsp conv(3fd8000000000000) = 3ec0000000000000; conv(404f000000000000) = 4278000000000000
+#1: xvcvdpsp conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = 7f80000000000000
+#2: xvcvdpsp conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpsp conv(8000000000000000) = 8000000000000000; conv(7ff0000000000000) = 7f80000000000000
+#4: xvcvdpsp conv(fff0000000000000) = ff80000000000000; conv(7ff7ffffffffffff) = 7fffffff00000000
+#5: xvcvdpsp conv(fff7ffffffffffff) = ffffffff00000000; conv(7ff8000000000000) = 7fc0000000000000
+#6: xvcvdpsp conv(fff8000000000000) = ffc0000000000000; conv(8008340000078000) = 8000000000000000
+#7: xvcvdpsp conv(c0d0650f5a07b353) = c683287b00000000; conv(41232585a9900000) = 49192c2d00000000
+#8: xvcvdpsp conv(41382511a2000000) = 49c1288d00000000; conv(40312ef5a9300000) = 418977ad00000000
+#9: xvcvdpsp conv(40514bf5d2300000) = 428a5faf00000000; conv(40976bf982440000) = 44bb5fcc00000000
+
+#0: xvcvdpuxds conv(3fd8000000000000) = 0000000000000000; conv(404f000000000000) = 000000000000003e
+#1: xvcvdpuxds conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = ffffffffffffffff
+#2: xvcvdpuxds conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpuxds conv(8000000000000000) = 0000000000000000; conv(7ff0000000000000) = ffffffffffffffff
+#4: xvcvdpuxds conv(fff0000000000000) = 0000000000000000; conv(7ff7ffffffffffff) = 0000000000000000
+#5: xvcvdpuxds conv(fff7ffffffffffff) = 0000000000000000; conv(7ff8000000000000) = 0000000000000000
+#6: xvcvdpuxds conv(fff8000000000000) = 0000000000000000; conv(8008340000078000) = 0000000000000000
+#7: xvcvdpuxds conv(c0d0650f5a07b353) = 0000000000000000; conv(41232585a9900000) = 00000000000992c2
+#8: xvcvdpuxds conv(41382511a2000000) = 0000000000182511; conv(40312ef5a9300000) = 0000000000000011
+#9: xvcvdpuxds conv(40514bf5d2300000) = 0000000000000045; conv(40976bf982440000) = 00000000000005da
+
+#0: xvcvdpuxws conv(3fd8000000000000) = 0000000000000000; conv(404f000000000000) = 0000003e00000000
+#1: xvcvdpuxws conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = ffffffff00000000
+#2: xvcvdpuxws conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpuxws conv(8000000000000000) = 0000000000000000; conv(7ff0000000000000) = ffffffff00000000
+#4: xvcvdpuxws conv(fff0000000000000) = 0000000000000000; conv(7ff7ffffffffffff) = 0000000000000000
+#5: xvcvdpuxws conv(fff7ffffffffffff) = 0000000000000000; conv(7ff8000000000000) = 0000000000000000
+#6: xvcvdpuxws conv(fff8000000000000) = 0000000000000000; conv(8008340000078000) = 0000000000000000
+#7: xvcvdpuxws conv(c0d0650f5a07b353) = 0000000000000000; conv(41232585a9900000) = 000992c200000000
+#8: xvcvdpuxws conv(41382511a2000000) = 0018251100000000; conv(40312ef5a9300000) = 0000001100000000
+#9: xvcvdpuxws conv(40514bf5d2300000) = 0000004500000000; conv(40976bf982440000) = 000005da00000000
+
+#0: xvcvspdp conv(3ec00000) = 3fd8000000000000; conv(42780000) = 404f000000000000
+#1: xvcvspdp conv(00000000) = 0000000000000000; conv(7f800000) = 7ff0000000000000
+#2: xvcvspdp conv(00000000) = 0000000000000000; conv(00000000) = 0000000000000000
+#3: xvcvspdp conv(80000000) = 8000000000000000; conv(7f800000) = 7ff0000000000000
+#4: xvcvspdp conv(ff800000) = fff0000000000000; conv(7fffffff) = 7fffffffe0000000
+#5: xvcvspdp conv(ffffffff) = ffffffffe0000000; conv(7fc00000) = 7ff8000000000000
+#6: xvcvspdp conv(ffc00000) = fff8000000000000; conv(80000000) = 8000000000000000
+#7: xvcvspdp conv(c683287b) = c0d0650f60000000; conv(49192c2d) = 41232585a0000000
+#8: xvcvspdp conv(49c1288d) = 41382511a0000000; conv(418977ad) = 40312ef5a0000000
+#9: xvcvspdp conv(428a5faf) = 40514bf5e0000000; conv(44bb5fcc) = 40976bf980000000
+
+#0: xvcvspsxds conv(3ec00000) = 0000000000000000; conv(42780000) = 000000000000003e
+#1: xvcvspsxds conv(00000000) = 0000000000000000; conv(7f800000) = 7fffffffffffffff
+#2: xvcvspsxds conv(00000000) = 0000000000000000; conv(00000000) = 0000000000000000
+#3: xvcvspsxds conv(80000000) = 0000000000000000; conv(7f800000) = 7fffffffffffffff
+#4: xvcvspsxds conv(ff800000) = 8000000000000000; conv(7fffffff) = 8000000000000000
+#5: xvcvspsxds conv(ffffffff) = 8000000000000000; conv(7fc00000) = 8000000000000000
+#6: xvcvspsxds conv(ffc00000) = 8000000000000000; conv(80000000) = 0000000000000000
+#7: xvcvspsxds conv(c683287b) = ffffffffffffbe6c; conv(49192c2d) = 00000000000992c2
+#8: xvcvspsxds conv(49c1288d) = 0000000000182511; conv(418977ad) = 0000000000000011
+#9: xvcvspsxds conv(428a5faf) = 0000000000000045; conv(44bb5fcc) = 00000000000005da
+
+#0: xvcvdpsxds conv(3fd8000000000000) = 0000000000000000; conv(404f000000000000) = 000000000000003e
+#1: xvcvdpsxds conv(0018000000b77501) = 0000000000000000; conv(7fe800000000051b) = 7fffffffffffffff
+#2: xvcvdpsxds conv(0123214569900000) = 0000000000000000; conv(0000000000000000) = 0000000000000000
+#3: xvcvdpsxds conv(8000000000000000) = 0000000000000000; conv(7ff0000000000000) = 7fffffffffffffff
+#4: xvcvdpsxds conv(fff0000000000000) = 8000000000000000; conv(7ff7ffffffffffff) = 8000000000000000
+#5: xvcvdpsxds conv(fff7ffffffffffff) = 8000000000000000; conv(7ff8000000000000) = 8000000000000000
+#6: xvcvdpsxds conv(fff8000000000000) = 8000000000000000; conv(8008340000078000) = 0000000000000000
+#7: xvcvdpsxds conv(c0d0650f5a07b353) = ffffffffffffbe6c; conv(41232585a9900000) = 00000000000992c2
+#8: xvcvdpsxds conv(41382511a2000000) = 0000000000182511; conv(40312ef5a9300000) = 0000000000000011
+#9: xvcvdpsxds conv(40514bf5d2300000) = 0000000000000045; conv(40976bf982440000) = 00000000000005da
+
+#0: xvcvspuxds conv(3ec00000) = 0000000000000000; conv(42780000) = 000000000000003e
+#1: xvcvspuxds conv(00000000) = 0000000000000000; conv(7f800000) = ffffffffffffffff
+#2: xvcvspuxds conv(00000000) = 0000000000000000; conv(00000000) = 0000000000000000
+#3: xvcvspuxds conv(80000000) = 0000000000000000; conv(7f800000) = ffffffffffffffff
+#4: xvcvspuxds conv(ff800000) = 0000000000000000; conv(7fffffff) = 0000000000000000
+#5: xvcvspuxds conv(ffffffff) = 0000000000000000; conv(7fc00000) = 0000000000000000
+#6: xvcvspuxds conv(ffc00000) = 0000000000000000; conv(80000000) = 0000000000000000
+#7: xvcvspuxds conv(c683287b) = 0000000000000000; conv(49192c2d) = 00000000000992c2
+#8: xvcvspuxds conv(49c1288d) = 0000000000182511; conv(418977ad) = 0000000000000011
+#9: xvcvspuxds conv(428a5faf) = 0000000000000045; conv(44bb5fcc) = 00000000000005da
+
+#0: xvcvspuxws conv(3ec00000) = 00000000; conv(42780000) = 0000003e; conv(00000000) = 00000000; conv(7f800000) = ffffffff
+#1: xvcvspuxws conv(00000000) = 00000000; conv(00000000) = 00000000; conv(80000000) = 00000000; conv(7f800000) = ffffffff
+#2: xvcvspuxws conv(ff800000) = 00000000; conv(7fffffff) = 00000000; conv(ffffffff) = 00000000; conv(7fc00000) = 00000000
+#3: xvcvspuxws conv(ffc00000) = 00000000; conv(80000000) = 00000000; conv(c683287b) = 00000000; conv(49192c2d) = 000992c2
+#4: xvcvspuxws conv(49c1288d) = 00182511; conv(418977ad) = 00000011; conv(428a5faf) = 00000045; conv(44bb5fcc) = 000005da
+
+#0: xsrdpic round(3fd8000000000000) = 0000000000000000
+#1: xsrdpic round(404f000000000000) = 404f000000000000
+#2: xsrdpic round(0018000000b77501) = 0000000000000000
+#3: xsrdpic round(7fe800000000051b) = 7fe800000000051b
+#4: xsrdpic round(0123214569900000) = 0000000000000000
+#5: xsrdpic round(0000000000000000) = 0000000000000000
+#6: xsrdpic round(8000000000000000) = 8000000000000000
+#7: xsrdpic round(7ff0000000000000) = 7ff0000000000000
+#8: xsrdpic round(fff0000000000000) = fff0000000000000
+#9: xsrdpic round(7ff7ffffffffffff) = 7fffffffffffffff
+#10: xsrdpic round(fff7ffffffffffff) = ffffffffffffffff
+#11: xsrdpic round(7ff8000000000000) = 7ff8000000000000
+#12: xsrdpic round(fff8000000000000) = fff8000000000000
+#13: xsrdpic round(8008340000078000) = 8000000000000000
+#14: xsrdpic round(c0d0650f5a07b353) = c0d0650000000000
+#15: xsrdpic round(41232585a9900000) = 4123258600000000
+#16: xsrdpic round(41382511a2000000) = 4138251200000000
+#17: xsrdpic round(40312ef5a9300000) = 4031000000000000
+#18: xsrdpic round(40514bf5d2300000) = 4051400000000000
+#19: xsrdpic round(40976bf982440000) = 40976c0000000000
+
+#0: xsrdpiz round(3fd8000000000000) = 0000000000000000
+#1: xsrdpiz round(404f000000000000) = 404f000000000000
+#2: xsrdpiz round(0018000000b77501) = 0000000000000000
+#3: xsrdpiz round(7fe800000000051b) = 7fe800000000051b
+#4: xsrdpiz round(0123214569900000) = 0000000000000000
+#5: xsrdpiz round(0000000000000000) = 0000000000000000
+#6: xsrdpiz round(8000000000000000) = 8000000000000000
+#7: xsrdpiz round(7ff0000000000000) = 7ff0000000000000
+#8: xsrdpiz round(fff0000000000000) = fff0000000000000
+#9: xsrdpiz round(7ff7ffffffffffff) = 7fffffffffffffff
+#10: xsrdpiz round(fff7ffffffffffff) = ffffffffffffffff
+#11: xsrdpiz round(7ff8000000000000) = 7ff8000000000000
+#12: xsrdpiz round(fff8000000000000) = fff8000000000000
+#13: xsrdpiz round(8008340000078000) = 8000000000000000
+#14: xsrdpiz round(c0d0650f5a07b353) = c0d0650000000000
+#15: xsrdpiz round(41232585a9900000) = 4123258400000000
+#16: xsrdpiz round(41382511a2000000) = 4138251100000000
+#17: xsrdpiz round(40312ef5a9300000) = 4031000000000000
+#18: xsrdpiz round(40514bf5d2300000) = 4051400000000000
+#19: xsrdpiz round(40976bf982440000) = 4097680000000000
+
+#0: xsrdpi round(3fd8000000000000) = 0000000000000000
+#1: xsrdpi round(404f000000000000) = 404f000000000000
+#2: xsrdpi round(0018000000b77501) = 0000000000000000
+#3: xsrdpi round(7fe800000000051b) = 7fe800000000051b
+#4: xsrdpi round(0123214569900000) = 0000000000000000
+#5: xsrdpi round(0000000000000000) = 0000000000000000
+#6: xsrdpi round(8000000000000000) = 8000000000000000
+#7: xsrdpi round(7ff0000000000000) = 7ff0000000000000
+#8: xsrdpi round(fff0000000000000) = fff0000000000000
+#9: xsrdpi round(7ff7ffffffffffff) = 7fffffffffffffff
+#10: xsrdpi round(fff7ffffffffffff) = ffffffffffffffff
+#11: xsrdpi round(7ff8000000000000) = 7ff8000000000000
+#12: xsrdpi round(fff8000000000000) = fff8000000000000
+#13: xsrdpi round(8008340000078000) = 8000000000000000
+#14: xsrdpi round(c0d0650f5a07b353) = c0d0650000000000
+#15: xsrdpi round(41232585a9900000) = 4123258600000000
+#16: xsrdpi round(41382511a2000000) = 4138251200000000
+#17: xsrdpi round(40312ef5a9300000) = 4031000000000000
+#18: xsrdpi round(40514bf5d2300000) = 4051400000000000
+#19: xsrdpi round(40976bf982440000) = 40976c0000000000
+
+#0: xvabsdp abs(3fd8000000000000) = 3fd8000000000000; abs(404f000000000000) = 404f000000000000
+#1: xvabsdp abs(0018000000b77501) = 0018000000b77501; abs(7fe800000000051b) = 7fe800000000051b
+#2: xvabsdp abs(0123214569900000) = 0123214569900000; abs(0000000000000000) = 0000000000000000
+#3: xvabsdp abs(8000000000000000) = 0000000000000000; abs(7ff0000000000000) = 7ff0000000000000
+#4: xvabsdp abs(fff0000000000000) = 7ff0000000000000; abs(7ff7ffffffffffff) = 7ff7ffffffffffff
+#5: xvabsdp abs(fff7ffffffffffff) = 7ff7ffffffffffff; abs(7ff8000000000000) = 7ff8000000000000
+#6: xvabsdp abs(fff8000000000000) = 7ff8000000000000; abs(8008340000078000) = 0008340000078000
+#7: xvabsdp abs(c0d0650f5a07b353) = 40d0650f5a07b353; abs(41232585a9900000) = 41232585a9900000
+#8: xvabsdp abs(41382511a2000000) = 41382511a2000000; abs(40312ef5a9300000) = 40312ef5a9300000
+#9: xvabsdp abs(40514bf5d2300000) = 40514bf5d2300000; abs(40976bf982440000) = 40976bf982440000
+
+#0: xvnabsdp nabs(3fd8000000000000) = bfd8000000000000; nabs(404f000000000000) = c04f000000000000
+#1: xvnabsdp nabs(0018000000b77501) = 8018000000b77501; nabs(7fe800000000051b) = ffe800000000051b
+#2: xvnabsdp nabs(0123214569900000) = 8123214569900000; nabs(0000000000000000) = 8000000000000000
+#3: xvnabsdp nabs(8000000000000000) = 8000000000000000; nabs(7ff0000000000000) = fff0000000000000
+#4: xvnabsdp nabs(fff0000000000000) = fff0000000000000; nabs(7ff7ffffffffffff) = fff7ffffffffffff
+#5: xvnabsdp nabs(fff7ffffffffffff) = fff7ffffffffffff; nabs(7ff8000000000000) = fff8000000000000
+#6: xvnabsdp nabs(fff8000000000000) = fff8000000000000; nabs(8008340000078000) = 8008340000078000
+#7: xvnabsdp nabs(c0d0650f5a07b353) = c0d0650f5a07b353; nabs(41232585a9900000) = c1232585a9900000
+#8: xvnabsdp nabs(41382511a2000000) = c1382511a2000000; nabs(40312ef5a9300000) = c0312ef5a9300000
+#9: xvnabsdp nabs(40514bf5d2300000) = c0514bf5d2300000; nabs(40976bf982440000) = c0976bf982440000
+
+#0: xvnegdp neg(3fd8000000000000) = bfd8000000000000; neg(404f000000000000) = c04f000000000000
+#1: xvnegdp neg(0018000000b77501) = 8018000000b77501; neg(7fe800000000051b) = ffe800000000051b
+#2: xvnegdp neg(0123214569900000) = 8123214569900000; neg(0000000000000000) = 8000000000000000
+#3: xvnegdp neg(8000000000000000) = 0000000000000000; neg(7ff0000000000000) = fff0000000000000
+#4: xvnegdp neg(fff0000000000000) = 7ff0000000000000; neg(7ff7ffffffffffff) = fff7ffffffffffff
+#5: xvnegdp neg(fff7ffffffffffff) = 7ff7ffffffffffff; neg(7ff8000000000000) = fff8000000000000
+#6: xvnegdp neg(fff8000000000000) = 7ff8000000000000; neg(8008340000078000) = 0008340000078000
+#7: xvnegdp neg(c0d0650f5a07b353) = 40d0650f5a07b353; neg(41232585a9900000) = c1232585a9900000
+#8: xvnegdp neg(41382511a2000000) = c1382511a2000000; neg(40312ef5a9300000) = c0312ef5a9300000
+#9: xvnegdp neg(40514bf5d2300000) = c0514bf5d2300000; neg(40976bf982440000) = c0976bf982440000
+
+#0: xvabssp abs(3ec00000) = 3ec00000; abs(42780000) = 42780000; abs(00000000) = 00000000; abs(7f800000) = 7f800000
+#1: xvabssp abs(00000000) = 00000000; abs(00000000) = 00000000; abs(80000000) = 00000000; abs(7f800000) = 7f800000
+#2: xvabssp abs(ff800000) = 7f800000; abs(7fffffff) = 7fffffff; abs(ffffffff) = 7fffffff; abs(7fc00000) = 7fc00000
+#3: xvabssp abs(ffc00000) = 7fc00000; abs(80000000) = 00000000; abs(c683287b) = 4683287b; abs(49192c2d) = 49192c2d
+#4: xvabssp abs(49c1288d) = 49c1288d; abs(418977ad) = 418977ad; abs(428a5faf) = 428a5faf; abs(44bb5fcc) = 44bb5fcc
+
+#0: xvnabssp nabs(3ec00000) = bec00000; nabs(42780000) = c2780000; nabs(00000000) = 80000000; nabs(7f800000) = ff800000
+#1: xvnabssp nabs(00000000) = 80000000; nabs(00000000) = 80000000; nabs(80000000) = 80000000; nabs(7f800000) = ff800000
+#2: xvnabssp nabs(ff800000) = ff800000; nabs(7fffffff) = ffffffff; nabs(ffffffff) = ffffffff; nabs(7fc00000) = ffc00000
+#3: xvnabssp nabs(ffc00000) = ffc00000; nabs(80000000) = 80000000; nabs(c683287b) = c683287b; nabs(49192c2d) = c9192c2d
+#4: xvnabssp nabs(49c1288d) = c9c1288d; nabs(418977ad) = c18977ad; nabs(428a5faf) = c28a5faf; nabs(44bb5fcc) = c4bb5fcc
+
+#0: xvrdpi round(3fd8000000000000) = 0000000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpi round(0018000000b77501) = 0000000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpi round(0123214569900000) = 0000000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpi round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpi round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpi round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpi round(fff8000000000000) = fff8000000000000; round(8008340000078000) = 8000000000000000
+#7: xvrdpi round(c0d0650f5a07b353) = c0d0650000000000; round(41232585a9900000) = 4123258600000000
+#8: xvrdpi round(41382511a2000000) = 4138251200000000; round(40312ef5a9300000) = 4031000000000000
+#9: xvrdpi round(40514bf5d2300000) = 4051400000000000; round(40976bf982440000) = 40976c0000000000
+
+#0: xvrdpic round(3fd8000000000000) = 0000000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpic round(0018000000b77501) = 0000000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpic round(0123214569900000) = 0000000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpic round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpic round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpic round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpic round(fff8000000000000) = fff8000000000000; round(8008340000078000) = 8000000000000000
+#7: xvrdpic round(c0d0650f5a07b353) = c0d0650000000000; round(41232585a9900000) = 4123258600000000
+#8: xvrdpic round(41382511a2000000) = 4138251200000000; round(40312ef5a9300000) = 4031000000000000
+#9: xvrdpic round(40514bf5d2300000) = 4051400000000000; round(40976bf982440000) = 40976c0000000000
+
+#0: xvrdpim round(3fd8000000000000) = 0000000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpim round(0018000000b77501) = 0000000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpim round(0123214569900000) = 0000000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpim round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpim round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpim round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpim round(fff8000000000000) = fff8000000000000; round(8008340000078000) = bff0000000000000
+#7: xvrdpim round(c0d0650f5a07b353) = c0d0654000000000; round(41232585a9900000) = 4123258400000000
+#8: xvrdpim round(41382511a2000000) = 4138251100000000; round(40312ef5a9300000) = 4031000000000000
+#9: xvrdpim round(40514bf5d2300000) = 4051400000000000; round(40976bf982440000) = 4097680000000000
+
+#0: xvrdpip round(3fd8000000000000) = 3ff0000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpip round(0018000000b77501) = 3ff0000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpip round(0123214569900000) = 3ff0000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpip round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpip round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpip round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpip round(fff8000000000000) = fff8000000000000; round(8008340000078000) = 8000000000000000
+#7: xvrdpip round(c0d0650f5a07b353) = c0d0650000000000; round(41232585a9900000) = 4123258600000000
+#8: xvrdpip round(41382511a2000000) = 4138251200000000; round(40312ef5a9300000) = 4032000000000000
+#9: xvrdpip round(40514bf5d2300000) = 4051800000000000; round(40976bf982440000) = 40976c0000000000
+
+#0: xvrdpiz round(3fd8000000000000) = 0000000000000000; round(404f000000000000) = 404f000000000000
+#1: xvrdpiz round(0018000000b77501) = 0000000000000000; round(7fe800000000051b) = 7fe800000000051b
+#2: xvrdpiz round(0123214569900000) = 0000000000000000; round(0000000000000000) = 0000000000000000
+#3: xvrdpiz round(8000000000000000) = 8000000000000000; round(7ff0000000000000) = 7ff0000000000000
+#4: xvrdpiz round(fff0000000000000) = fff0000000000000; round(7ff7ffffffffffff) = 7fffffffffffffff
+#5: xvrdpiz round(fff7ffffffffffff) = ffffffffffffffff; round(7ff8000000000000) = 7ff8000000000000
+#6: xvrdpiz round(fff8000000000000) = fff8000000000000; round(8008340000078000) = 8000000000000000
+#7: xvrdpiz round(c0d0650f5a07b353) = c0d0650000000000; round(41232585a9900000) = 4123258400000000
+#8: xvrdpiz round(41382511a2000000) = 4138251100000000; round(40312ef5a9300000) = 4031000000000000
+#9: xvrdpiz round(40514bf5d2300000) = 4051400000000000; round(40976bf982440000) = 4097680000000000
+
+#0: xvrspi round(3ec00000) = 00000000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspi round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspi round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspi round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832800; round(49192c2d) = 49192c30
+#4: xvrspi round(49c1288d) = 49c12890; round(418977ad) = 41880000; round(428a5faf) = 428a0000; round(44bb5fcc) = 44bb6000
+
+#0: xvrspic round(3ec00000) = 00000000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspic round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspic round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspic round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832800; round(49192c2d) = 49192c30
+#4: xvrspic round(49c1288d) = 49c12890; round(418977ad) = 41880000; round(428a5faf) = 428a0000; round(44bb5fcc) = 44bb6000
+
+#0: xvrspim round(3ec00000) = 00000000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspim round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspim round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspim round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832a00; round(49192c2d) = 49192c20
+#4: xvrspim round(49c1288d) = 49c12888; round(418977ad) = 41880000; round(428a5faf) = 428a0000; round(44bb5fcc) = 44bb4000
+
+#0: xvrspip round(3ec00000) = 3f800000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspip round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspip round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspip round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832800; round(49192c2d) = 49192c30
+#4: xvrspip round(49c1288d) = 49c12890; round(418977ad) = 41900000; round(428a5faf) = 428c0000; round(44bb5fcc) = 44bb6000
+
+#0: xvrspiz round(3ec00000) = 00000000; round(42780000) = 42780000; round(00000000) = 00000000; round(7f800000) = 7f800000
+#1: xvrspiz round(00000000) = 00000000; round(00000000) = 00000000; round(80000000) = 80000000; round(7f800000) = 7f800000
+#2: xvrspiz round(ff800000) = ff800000; round(7fffffff) = 7fffffff; round(ffffffff) = ffffffff; round(7fc00000) = 7fc00000
+#3: xvrspiz round(ffc00000) = ffc00000; round(80000000) = 80000000; round(c683287b) = c6832800; round(49192c2d) = 49192c20
+#4: xvrspiz round(49c1288d) = 49c12888; round(418977ad) = 41880000; round(428a5faf) = 428a0000; round(44bb5fcc) = 44bb4000
+
+Test VSX vector integer to float conversion instructions
+#0: xvcvsxddp conv(0000000000000000) = 0000000000000000; conv(ffffffff00000000) = c1f0000000000000
+#1: xvcvsxddp conv(00000000ffffffff) = 41efffffffe00000; conv(ffffffffffffffff) = bff0000000000000
+#2: xvcvsxddp conv(89abcde123456789) = c3dd950c87b72ea6; conv(0102030405060708) = 4370203040506070
+#3: xvcvsxddp conv(00000000a0b1c2d3) = 41e416385a600000; conv(1111222233334444) = 43b1112222333344
+
+#0: xvcvuxddp conv(0000000000000000) = 0000000000000000; conv(ffffffff00000000) = 43efffffffe00000
+#1: xvcvuxddp conv(00000000ffffffff) = 41efffffffe00000; conv(ffffffffffffffff) = 43f0000000000000
+#2: xvcvuxddp conv(89abcde123456789) = 43e13579bc2468ad; conv(0102030405060708) = 4370203040506070
+#3: xvcvuxddp conv(00000000a0b1c2d3) = 41e416385a600000; conv(1111222233334444) = 43b1112222333344
+
+#0: xvcvsxdsp conv(0000000000000000) = 0000000000000000; conv(ffffffff00000000) = cf80000000000000
+#1: xvcvsxdsp conv(00000000ffffffff) = 4f80000000000000; conv(ffffffffffffffff) = bf80000000000000
+#2: xvcvsxdsp conv(89abcde123456789) = deeca86400000000; conv(0102030405060708) = 5b81018200000000
+#3: xvcvsxdsp conv(00000000a0b1c2d3) = 4f20b1c300000000; conv(1111222233334444) = 5d88891100000000
+
+#0: xvcvuxdsp conv(0000000000000000) = 0000000000000000; conv(ffffffff00000000) = 5f80000000000000
+#1: xvcvuxdsp conv(00000000ffffffff) = 4f80000000000000; conv(ffffffffffffffff) = 5f80000000000000
+#2: xvcvuxdsp conv(89abcde123456789) = 5f09abce00000000; conv(0102030405060708) = 5b81018200000000
+#3: xvcvuxdsp conv(00000000a0b1c2d3) = 4f20b1c300000000; conv(1111222233334444) = 5d88891100000000
+
+#0: xvcvsxwdp conv(00000000) = 0000000000000000; conv(ffff0000) = c0f0000000000000
+#1: xvcvsxwdp conv(0000ffff) = 40efffe000000000; conv(ffffffff) = bff0000000000000
+#2: xvcvsxwdp conv(89a73522) = c1dd9632b7800000; conv(01020304) = 4170203040000000
+#3: xvcvsxwdp conv(0000abcd) = 40e579a000000000; conv(11223344) = 41b1223344000000
+
+#0: xvcvuxwdp conv(00000000) = 0000000000000000; conv(ffff0000) = 41efffe000000000
+#1: xvcvuxwdp conv(0000ffff) = 40efffe000000000; conv(ffffffff) = 41efffffffe00000
+#2: xvcvuxwdp conv(89a73522) = 41e134e6a4400000; conv(01020304) = 4170203040000000
+#3: xvcvuxwdp conv(0000abcd) = 40e579a000000000; conv(11223344) = 41b1223344000000
+
+#0: xvcvsxwsp conv(00000000) = 00000000; conv(ffff0000) = c7800000; conv(0000ffff) = 477fff00; conv(ffffffff) = bf800000
+#1: xvcvsxwsp conv(89a73522) = ceecb196; conv(01020304) = 4b810182; conv(0000abcd) = 472bcd00; conv(11223344) = 4d89119a
+
+#0: xvcvuxwsp conv(00000000) = 00000000; conv(ffff0000) = 4f7fff00; conv(0000ffff) = 477fff00; conv(ffffffff) = 4f800000
+#1: xvcvuxwsp conv(89a73522) = 4f09a735; conv(01020304) = 4b810182; conv(0000abcd) = 472bcd00; conv(11223344) = 4d89119a
+
+Test div extensions
+#0: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=0; XER=0
+#1: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=0; XER=0
+#2: divdeu: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=0
+#3: divdeu: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=0; XER=0
+#4: divdeu: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divdeu: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=0
+#6: divdeu: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=0; XER=0
+#7: divdeu: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=0; XER=0
+#8: divdeu: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divdeu: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=0
+#10: divdeu: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=0
+#11: divdeu: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divdeu: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=4; XER=0
+#1: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=4; XER=0
+#2: divdeu.: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=2; XER=0
+#3: divdeu.: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=4; XER=0
+#4: divdeu.: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divdeu.: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=2; XER=0
+#6: divdeu.: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=4; XER=0
+#7: divdeu.: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=4; XER=0
+#8: divdeu.: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divdeu.: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=2; XER=0
+#10: divdeu.: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=2; XER=0
+#11: divdeu.: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divdeu.: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=0; XER=0
+#1: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=0; XER=0
+#2: divdeuo: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=0; XER=c0000000
+#3: divdeuo: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=0; XER=0
+#4: divdeuo: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=0; XER=0
+#5: divdeuo: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=0; XER=c0000000
+#6: divdeuo: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=0; XER=0
+#7: divdeuo: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=0; XER=0
+#8: divdeuo: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=0; XER=0
+#9: divdeuo: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=0; XER=c0000000
+#10: divdeuo: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=0; XER=c0000000
+#11: divdeuo: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=0; XER=0
+#12: divdeuo: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=0; XER=0
+
+#0: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffc = 0x0000000000000004; CR=4; XER=0
+#1: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffd = 0x0000000000000004; CR=4; XER=0
+#2: divdeuo.: 0x00000000000000040000000000000000 / 0x0000000000000004 = 0x0000000000000000; CR=3; XER=c0000000
+#3: divdeuo.: 0x00000000000000040000000000000000 / 0xfffffffffffffffb = 0x0000000000000004; CR=4; XER=0
+#4: divdeuo.: 0x00000000000000030000000000000000 / 0x0000000000000008 = 0x6000000000000000; CR=4; XER=0
+#5: divdeuo.: 0x80000000000000000000000000000000 / 0x000000000000000a = 0x0000000000000000; CR=3; XER=c0000000
+#6: divdeuo.: 0x000000000000050c0000000000000000 / 0xffffffffffffffff = 0x000000000000050c; CR=4; XER=0
+#7: divdeuo.: 0x000000000000050c0000000000000000 / 0xfffffffffffff000 = 0x000000000000050c; CR=4; XER=0
+#8: divdeuo.: 0x000000001234fedc0000000000000000 / 0x000000008000a873 = 0x2469cdcc6ad4ce20; CR=4; XER=0
+#9: divdeuo.: 0xabcd87651234fedc0000000000000000 / 0x00000000a123b893 = 0x0000000000000000; CR=3; XER=c0000000
+#10: divdeuo.: 0x000123456789abdc0000000000000000 / 0x0000000000000000 = 0x0000000000000000; CR=3; XER=c0000000
+#11: divdeuo.: 0x00000000000000000000000000000000 / 0x0000000000000002 = 0x0000000000000000; CR=2; XER=0
+#12: divdeuo.: 0x00000000000000770000000000000000 / 0x00000000000a3499 = 0x000ba911a321dcca; CR=4; XER=0
+
+
+#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divwe: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divwe: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=0
+#3: divwe: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divwe: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divwe: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divwe.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divwe.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divwe.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=2; XER=0
+#3: divwe.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divwe.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divwe.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=4; XER=0
+
+
+#0: divweo: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweo: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweo: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=c0000000
+#3: divweo: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweo: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweo: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divweo.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweo.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweo.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=3; XER=c0000000
+#3: divweo.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweo.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweo.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=4; XER=0
+
+
+Test ftsqrt instruction
+ftsqrt: 3fd8000000000000 ? 8 (CRx)
+ftsqrt: 404f000000000000 ? 8 (CRx)
+ftsqrt: 0018000000b77501 ? a (CRx)
+ftsqrt: 7fe800000000051b ? 8 (CRx)
+ftsqrt: 0123214569900000 ? a (CRx)
+ftsqrt: 0000000000000000 ? e (CRx)
+ftsqrt: 8000000000000000 ? e (CRx)
+ftsqrt: 7ff0000000000000 ? e (CRx)
+ftsqrt: fff0000000000000 ? e (CRx)
+ftsqrt: 7ff7ffffffffffff ? a (CRx)
+ftsqrt: fff7ffffffffffff ? a (CRx)
+ftsqrt: 7ff8000000000000 ? a (CRx)
+ftsqrt: fff8000000000000 ? a (CRx)
+ftsqrt: 8008340000078000 ? e (CRx)
+ftsqrt: c0d0650f5a07b353 ? a (CRx)
+ftsqrt: 41232585a9900000 ? 8 (CRx)
+ftsqrt: 41382511a2000000 ? 8 (CRx)
+ftsqrt: 40312ef5a9300000 ? 8 (CRx)
+ftsqrt: 40514bf5d2300000 ? 8 (CRx)
+ftsqrt: 40976bf982440000 ? 8 (CRx)
+
+Test vector and scalar tdiv and tsqrt instructions
+#0: xstsqrtdp test-sqrt(3fd8000000000000) ? 8 (CRx)
+#1: xstsqrtdp test-sqrt(404f000000000000) ? 8 (CRx)
+#2: xstsqrtdp test-sqrt(0018000000b77501) ? a (CRx)
+#3: xstsqrtdp test-sqrt(7fe800000000051b) ? 8 (CRx)
+#4: xstsqrtdp test-sqrt(0123214569900000) ? a (CRx)
+#5: xstsqrtdp test-sqrt(0000000000000000) ? e (CRx)
+#6: xstsqrtdp test-sqrt(8000000000000000) ? e (CRx)
+#7: xstsqrtdp test-sqrt(7ff0000000000000) ? e (CRx)
+#8: xstsqrtdp test-sqrt(fff0000000000000) ? e (CRx)
+#9: xstsqrtdp test-sqrt(7ff7ffffffffffff) ? a (CRx)
+#10: xstsqrtdp test-sqrt(fff7ffffffffffff) ? a (CRx)
+#11: xstsqrtdp test-sqrt(7ff8000000000000) ? a (CRx)
+#12: xstsqrtdp test-sqrt(fff8000000000000) ? a (CRx)
+#13: xstsqrtdp test-sqrt(8008340000078000) ? e (CRx)
+#14: xstsqrtdp test-sqrt(c0d0650f5a07b353) ? a (CRx)
+#15: xstsqrtdp test-sqrt(41232585a9900000) ? 8 (CRx)
+#16: xstsqrtdp test-sqrt(41382511a2000000) ? 8 (CRx)
+#17: xstsqrtdp test-sqrt(40312ef5a9300000) ? 8 (CRx)
+#18: xstsqrtdp test-sqrt(40514bf5d2300000) ? 8 (CRx)
+#19: xstsqrtdp test-sqrt(40976bf982440000) ? 8 (CRx)
+
+#0: xvtsqrtdp test-sqrt(3fd8000000000000); test-sqrt(404f000000000000) ? 8 (CRx)
+#1: xvtsqrtdp test-sqrt(0018000000b77501); test-sqrt(7fe800000000051b) ? a (CRx)
+#2: xvtsqrtdp test-sqrt(0123214569900000); test-sqrt(0000000000000000) ? e (CRx)
+#3: xvtsqrtdp test-sqrt(8000000000000000); test-sqrt(7ff0000000000000) ? e (CRx)
+#4: xvtsqrtdp test-sqrt(fff0000000000000); test-sqrt(7ff7ffffffffffff) ? e (CRx)
+#5: xvtsqrtdp test-sqrt(fff7ffffffffffff); test-sqrt(7ff8000000000000) ? a (CRx)
+#6: xvtsqrtdp test-sqrt(fff8000000000000); test-sqrt(8008340000078000) ? e (CRx)
+#7: xvtsqrtdp test-sqrt(c0d0650f5a07b353); test-sqrt(41232585a9900000) ? a (CRx)
+#8: xvtsqrtdp test-sqrt(41382511a2000000); test-sqrt(40312ef5a9300000) ? 8 (CRx)
+#9: xvtsqrtdp test-sqrt(40514bf5d2300000); test-sqrt(40976bf982440000) ? 8 (CRx)
+
+#0: xvtsqrtsp test-sqrt(3ec00000); test-sqrt(42780000); test-sqrt(00000000); test-sqrt(7f800000) ? e (CRx)
+#1: xvtsqrtsp test-sqrt(00000000); test-sqrt(00000000); test-sqrt(80000000); test-sqrt(7f800000) ? e (CRx)
+#2: xvtsqrtsp test-sqrt(ff800000); test-sqrt(7fffffff); test-sqrt(ffffffff); test-sqrt(7fc00000) ? e (CRx)
+#3: xvtsqrtsp test-sqrt(ffc00000); test-sqrt(80000000); test-sqrt(c683287b); test-sqrt(49192c2d) ? e (CRx)
+#4: xvtsqrtsp test-sqrt(49c1288d); test-sqrt(418977ad); test-sqrt(428a5faf); test-sqrt(44bb5fcc) ? 8 (CRx)
+
+#0: xvtdivdp fff0000000000000 test-div fff0000000000000 AND fff0000000000000 test-div c0d0650f5a07b353 ? cc=e
+#1: xvtdivdp 41232585a9900000 test-div 41382511a2000000 AND fff0000000000000 test-div 0000000000000000 ? cc=e
+#2: xvtdivdp fff0000000000000 test-div 0123214569900000 AND fff0000000000000 test-div 7ff0000000000000 ? cc=e
+#3: xvtdivdp fff0000000000000 test-div 7ff7ffffffffffff AND fff0000000000000 test-div 7ff8000000000000 ? cc=e
+#4: xvtdivdp c0d0650f5a07b353 test-div fff0000000000000 AND c0d0650f5a07b353 test-div c0d0650f5a07b353 ? cc=e
+#5: xvtdivdp c0d0650f5a07b353 test-div 8000000000000000 AND c0d0650f5a07b353 test-div 0000000000000000 ? cc=e
+#6: xvtdivdp c0d0650f5a07b353 test-div 0123214569900000 AND c0d0650f5a07b353 test-div 7ff0000000000000 ? cc=e
+#7: xvtdivdp c0d0650f5a07b353 test-div 7ff7ffffffffffff AND c0d0650f5a07b353 test-div 7ff8000000000000 ? cc=a
+#8: xvtdivdp 8000000000000000 test-div fff0000000000000 AND 8000000000000000 test-div c0d0650f5a07b353 ? cc=e
+#9: xvtdivdp 8000000000000000 test-div 8000000000000000 AND 8000000000000000 test-div 0000000000000000 ? cc=e
+#10: xvtdivdp 8000000000000000 test-div 0123214569900000 AND 8000000000000000 test-div 7ff0000000000000 ? cc=e
+#11: xvtdivdp 8000000000000000 test-div 7ff7ffffffffffff AND 8000000000000000 test-div 7ff8000000000000 ? cc=a
+#12: xvtdivdp 0000000000000000 test-div fff0000000000000 AND 0000000000000000 test-div c0d0650f5a07b353 ? cc=e
+#13: xvtdivdp 0000000000000000 test-div 8000000000000000 AND 0000000000000000 test-div 0000000000000000 ? cc=e
+#14: xvtdivdp 0000000000000000 test-div 0123214569900000 AND 0000000000000000 test-div 7ff0000000000000 ? cc=e
+#15: xvtdivdp 0000000000000000 test-div 7ff7ffffffffffff AND 0000000000000000 test-div 7ff8000000000000 ? cc=a
+#16: xvtdivdp 0123214569900000 test-div fff0000000000000 AND 0123214569900000 test-div c0d0650f5a07b353 ? cc=e
+#17: xvtdivdp 0123214569900000 test-div 8000000000000000 AND 0123214569900000 test-div 0000000000000000 ? cc=e
+#18: xvtdivdp 0123214569900000 test-div 404f000000000000 AND 0123214569900000 test-div 7ff0000000000000 ? cc=e
+#19: xvtdivdp 0123214569900000 test-div 7ff7ffffffffffff AND 0123214569900000 test-div 7ff8000000000000 ? cc=a
+#20: xvtdivdp 7ff0000000000000 test-div fff0000000000000 AND 7ff0000000000000 test-div c0d0650f5a07b353 ? cc=e
+#21: xvtdivdp 7ff0000000000000 test-div 8000000000000000 AND 7ff0000000000000 test-div 0000000000000000 ? cc=e
+#22: xvtdivdp 7ff0000000000000 test-div 0123214569900000 AND 7ff0000000000000 test-div 7ff0000000000000 ? cc=e
+#23: xvtdivdp 7ff0000000000000 test-div 7ff7ffffffffffff AND 7ff0000000000000 test-div 7ff8000000000000 ? cc=e
+#24: xvtdivdp fff7ffffffffffff test-div fff0000000000000 AND fff7ffffffffffff test-div c0d0650f5a07b353 ? cc=e
+#25: xvtdivdp fff8000000000000 test-div 8000000000000000 AND fff8000000000000 test-div 0000000000000000 ? cc=e
+#26: xvtdivdp fff7ffffffffffff test-div 0123214569900000 AND fff7ffffffffffff test-div 7ff0000000000000 ? cc=e
+#27: xvtdivdp fff7ffffffffffff test-div 7ff7ffffffffffff AND fff7ffffffffffff test-div 7ff8000000000000 ? cc=a
+#28: xvtdivdp fff8000000000000 test-div fff0000000000000 AND fff8000000000000 test-div c0d0650f5a07b353 ? cc=e
+#29: xvtdivdp fff8000000000000 test-div 8000000000000000 AND 41232585a9900000 test-div 41382511a2000000 ? cc=e
+#30: xvtdivdp 41232585a9900000 test-div 41382511a2000000 AND 7ff7ffffffffffff test-div 7ff8000000000000 ? cc=a
+#31: xvtdivdp 7ff8000000000000 test-div 7ff8000000000000 AND 7ff8000000000000 test-div fff8000000000000 ? cc=a
+#32: xvtdivdp 41382511a2000000 test-div 40514bf5d2300000 AND 40312ef5a9300000 test-div 41382511a2000000 ? cc=8
+#33: xvtdivdp 40976bf982440000 test-div 40976bf982440000 AND 40976bf982440000 test-div 40514bf5d2300000 ? cc=8
+
+#0: xvtdivsp ff800000 test-div ff800000 AND ff800000 test-div c683287b AND 49192c2d test-div 49c1288d AND ff800000 test-div 00000000 ? cc=e
+#1: xvtdivsp ff800000 test-div 00000000 AND ff800000 test-div 7f800000 AND ff800000 test-div 7fffffff AND ff800000 test-div 7fc00000 ? cc=e
+#2: xvtdivsp c683287b test-div ff800000 AND c683287b test-div c683287b AND c683287b test-div 80000000 AND c683287b test-div 00000000 ? cc=e
+#3: xvtdivsp c683287b test-div 00000000 AND c683287b test-div 7f800000 AND c683287b test-div 7fffffff AND c683287b test-div 7fc00000 ? cc=e
+#4: xvtdivsp 80000000 test-div ff800000 AND 80000000 test-div c683287b AND 80000000 test-div 80000000 AND 80000000 test-div 00000000 ? cc=e
+#5: xvtdivsp 80000000 test-div 00000000 AND 80000000 test-div 7f800000 AND 80000000 test-div 7fffffff AND 80000000 test-div 7fc00000 ? cc=e
+#6: xvtdivsp 00000000 test-div ff800000 AND 00000000 test-div c683287b AND 00000000 test-div 80000000 AND 00000000 test-div 00000000 ? cc=e
+#7: xvtdivsp 00000000 test-div 00000000 AND 00000000 test-div 7f800000 AND 00000000 test-div 7fffffff AND 00000000 test-div 7fc00000 ? cc=e
+#8: xvtdivsp 00000000 test-div ff800000 AND 00000000 test-div c683287b AND 00000000 test-div 80000000 AND 00000000 test-div 00000000 ? cc=e
+#9: xvtdivsp 00000000 test-div 42780000 AND 00000000 test-div 7f800000 AND 00000000 test-div 7fffffff AND 00000000 test-div 7fc00000 ? cc=e
+#10: xvtdivsp 7f800000 test-div ff800000 AND 7f800000 test-div c683287b AND 7f800000 test-div 80000000 AND 7f800000 test-div 00000000 ? cc=e
+#11: xvtdivsp 7f800000 test-div 00000000 AND 7f800000 test-div 7f800000 AND 7f800000 test-div 7fffffff AND 7f800000 test-div 7fc00000 ? cc=e
+#12: xvtdivsp ffffffff test-div ff800000 AND ffffffff test-div c683287b AND ffc00000 test-div 80000000 AND ffc00000 test-div 00000000 ? cc=e
+#13: xvtdivsp ffffffff test-div 00000000 AND ffffffff test-div 7f800000 AND ffffffff test-div 7fffffff AND ffffffff test-div 7fc00000 ? cc=e
+#14: xvtdivsp ffc00000 test-div ff800000 AND ffc00000 test-div c683287b AND ffc00000 test-div 80000000 AND 49192c2d test-div 49c1288d ? cc=e
+#15: xvtdivsp 49192c2d test-div 49c1288d AND 7fffffff test-div 7fc00000 AND 7fc00000 test-div 7fc00000 AND 7fc00000 test-div ffc00000 ? cc=a
+#16: xvtdivsp 49c1288d test-div 428a5faf AND 418977ad test-div 49c1288d AND 44bb5fcc test-div 44bb5fcc AND 44bb5fcc test-div 428a5faf ? cc=8
+
+Test popcntw instruction
+popcntw: 0x9182736405504536 => 0x0000000d0000000b
+
diff --git a/main/none/tests/ppc64/test_isa_2_06_part3.vgtest b/main/none/tests/ppc64/test_isa_2_06_part3.vgtest
new file mode 100644
index 0000000..3519c8a
--- /dev/null
+++ b/main/none/tests/ppc64/test_isa_2_06_part3.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_isa-2_06_cap
+prog: test_isa_2_06_part3
diff --git a/main/none/tests/process_vm_readv_writev.c b/main/none/tests/process_vm_readv_writev.c
new file mode 100644
index 0000000..851cd33
--- /dev/null
+++ b/main/none/tests/process_vm_readv_writev.c
@@ -0,0 +1,92 @@
+#include <config.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/uio.h>
+
+static int status = EXIT_SUCCESS;
+
+#ifdef HAVE_PROCESS_VM_READV
+
+static void test_process_vm_readv()
+{
+ char lbuf[] = "123456";
+ char rbuf[] = "ABCDEF";
+
+ struct iovec lvec[2];
+ struct iovec rvec[2];
+
+ lvec[0].iov_base = lbuf + 1;
+ lvec[0].iov_len = 1;
+ lvec[1].iov_base = lbuf + 3;
+ lvec[1].iov_len = 2;
+
+ rvec[0].iov_base = rbuf + 1;
+ rvec[0].iov_len = 2;
+ rvec[1].iov_base = rbuf + 4;
+ rvec[1].iov_len = 1;
+
+ if (process_vm_readv(getpid(),
+ lvec, 2,
+ rvec, 2,
+ 0 ) < 0 ) {
+ perror("process_vm_readv");
+ status = EXIT_FAILURE;
+ }
+
+ if (strcmp(lbuf, "1B3CE6") != 0) {
+ fprintf(stderr, "Expected: \"1B3CE6\"; Got: \"%s\"\n", lbuf);
+ status = EXIT_FAILURE;
+ }
+}
+
+#endif /* defined( HAVE_PROCESS_VM_READV ) */
+
+#ifdef HAVE_PROCESS_VM_WRITEV
+
+static void test_process_vm_writev()
+{
+ char lbuf[] = "123456";
+ char rbuf[] = "ABCDEF";
+
+ struct iovec lvec[2];
+ struct iovec rvec[2];
+
+ lvec[0].iov_base = lbuf + 1;
+ lvec[0].iov_len = 1;
+ lvec[1].iov_base = lbuf + 3;
+ lvec[1].iov_len = 2;
+
+ rvec[0].iov_base = rbuf + 1;
+ rvec[0].iov_len = 2;
+ rvec[1].iov_base = rbuf + 4;
+ rvec[1].iov_len = 1;
+
+ if (process_vm_writev(getpid(),
+ lvec, 2,
+ rvec, 2,
+ 0 ) < 0 ) {
+ perror("process_vm_writev");
+ status = EXIT_FAILURE;
+ }
+
+ if (strcmp(rbuf, "A24D5F") != 0) {
+ fprintf(stderr, "Expected: \"A24D5F\"; Got: \"%s\"\n", rbuf);
+ status = EXIT_FAILURE;
+ }
+}
+
+#endif /* defined( HAVE_PROCESS_VM_WRITEV ) */
+
+int main(int argc, char *argv[])
+{
+#ifdef HAVE_PROCESS_VM_READV
+ test_process_vm_readv();
+#endif
+#ifdef HAVE_PROCESS_VM_WRITEV
+ test_process_vm_writev();
+#endif
+ return status;
+}
diff --git a/main/none/tests/process_vm_readv_writev.stderr.exp b/main/none/tests/process_vm_readv_writev.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/process_vm_readv_writev.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/process_vm_readv_writev.vgtest b/main/none/tests/process_vm_readv_writev.vgtest
new file mode 100644
index 0000000..4094ab0
--- /dev/null
+++ b/main/none/tests/process_vm_readv_writev.vgtest
@@ -0,0 +1 @@
+prog: process_vm_readv_writev
diff --git a/main/none/tests/rlimit64_nofile.c b/main/none/tests/rlimit64_nofile.c
new file mode 100644
index 0000000..54c3edf
--- /dev/null
+++ b/main/none/tests/rlimit64_nofile.c
@@ -0,0 +1,105 @@
+#define _LARGEFILE_SOURCE
+#define _LARGEFILE64_SOURCE
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/resource.h>
+#include <unistd.h>
+#include "fdleak.h"
+
+int main(int argc, char **argv)
+{
+ struct rlimit64 oldrlim;
+ struct rlimit64 newrlim;
+ int fd;
+
+ CLOSE_INHERITED_FDS;
+
+ if (getrlimit64(RLIMIT_NOFILE, &oldrlim) < 0)
+ {
+ perror("getrlimit");
+ exit(1);
+ }
+
+ newrlim.rlim_cur = oldrlim.rlim_max+1;
+ newrlim.rlim_max = oldrlim.rlim_max;
+ if (setrlimit64(RLIMIT_NOFILE, &newrlim) == -1)
+ {
+ if (errno != EINVAL) {
+ fprintf(stderr, "setrlimit64 exceeding hardlimit must set errno=EINVAL\n");
+ exit(1);
+ }
+ }
+ else
+ {
+ fprintf(stderr, "setrlimit64 exceeding hardlimit must return -1\n");
+ exit(1);
+ }
+
+ newrlim.rlim_cur = oldrlim.rlim_max;
+ newrlim.rlim_max = oldrlim.rlim_max+1;
+ if (setrlimit64(RLIMIT_NOFILE, &newrlim) == -1)
+ {
+ if (errno != EPERM) {
+ fprintf(stderr, "setrlimit64 changing hardlimit must set errno=EPERM\n");
+ exit(1);
+ }
+ }
+ else
+ {
+ fprintf(stderr, "setrlimit64 changing hardlimit must return -1\n");
+ exit(1);
+ }
+
+ newrlim.rlim_cur = oldrlim.rlim_cur / 2;
+ newrlim.rlim_max = oldrlim.rlim_max;
+
+ if (setrlimit64(RLIMIT_NOFILE, &newrlim) < 0)
+ {
+ perror("setrlimit64");
+ exit(1);
+ }
+
+ if (getrlimit64(RLIMIT_NOFILE, &newrlim) < 0)
+ {
+ perror("getrlimit");
+ exit(1);
+ }
+
+ if (newrlim.rlim_cur != oldrlim.rlim_cur / 2)
+ {
+ fprintf(stderr, "rlim_cur is %llu (should be %llu)\n",
+ (unsigned long long)newrlim.rlim_cur,
+ (unsigned long long)oldrlim.rlim_cur / 2);
+ }
+
+ if (newrlim.rlim_max != oldrlim.rlim_max)
+ {
+ fprintf(stderr, "rlim_max is %llu (should be %llu)\n",
+ (unsigned long long)newrlim.rlim_max,
+ (unsigned long long)oldrlim.rlim_max);
+ }
+
+ newrlim.rlim_cur -= 3; /* allow for stdin, stdout and stderr */
+
+ while (newrlim.rlim_cur-- > 0)
+ {
+ if (open("/dev/null", O_RDONLY) < 0)
+ {
+ perror("open");
+ }
+ }
+
+ if ((fd = open("/dev/null", O_RDONLY)) >= 0)
+ {
+ fprintf(stderr, "open succeeded with fd %d - it should have failed!\n", fd);
+ }
+ else if (errno != EMFILE)
+ {
+ perror("open");
+ }
+
+ exit(0);
+}
diff --git a/main/none/tests/rlimit64_nofile.stderr.exp b/main/none/tests/rlimit64_nofile.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/rlimit64_nofile.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/none/tests/rlimit64_nofile.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/none/tests/rlimit64_nofile.stdout.exp
diff --git a/main/none/tests/rlimit64_nofile.vgtest b/main/none/tests/rlimit64_nofile.vgtest
new file mode 100644
index 0000000..de86a21
--- /dev/null
+++ b/main/none/tests/rlimit64_nofile.vgtest
@@ -0,0 +1 @@
+prog: rlimit64_nofile
diff --git a/main/none/tests/rlimit_nofile.c b/main/none/tests/rlimit_nofile.c
index c5a0a41..135f1a1 100644
--- a/main/none/tests/rlimit_nofile.c
+++ b/main/none/tests/rlimit_nofile.c
@@ -20,6 +20,36 @@
exit(1);
}
+ newrlim.rlim_cur = oldrlim.rlim_max+1;
+ newrlim.rlim_max = oldrlim.rlim_max;
+ if (setrlimit(RLIMIT_NOFILE, &newrlim) == -1)
+ {
+ if (errno != EINVAL) {
+ fprintf(stderr, "setrlimit exceeding hardlimit must set errno=EINVAL\n");
+ exit(1);
+ }
+ }
+ else
+ {
+ fprintf(stderr, "setrlimit exceeding hardlimit must return -1\n");
+ exit(1);
+ }
+
+ newrlim.rlim_cur = oldrlim.rlim_max;
+ newrlim.rlim_max = oldrlim.rlim_max+1;
+ if (setrlimit(RLIMIT_NOFILE, &newrlim) == -1)
+ {
+ if (errno != EPERM) {
+ fprintf(stderr, "setrlimit changing hardlimit must set errno=EPERM\n");
+ exit(1);
+ }
+ }
+ else
+ {
+ fprintf(stderr, "setrlimit changing hardlimit must return -1\n");
+ exit(1);
+ }
+
newrlim.rlim_cur = oldrlim.rlim_cur / 2;
newrlim.rlim_max = oldrlim.rlim_max;
diff --git a/main/none/tests/s390x/Makefile.am b/main/none/tests/s390x/Makefile.am
index 95b2004..04aaaf8 100644
--- a/main/none/tests/s390x/Makefile.am
+++ b/main/none/tests/s390x/Makefile.am
@@ -5,26 +5,32 @@
INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \
and or xor insert div srst fold_And16 flogr sub_EI add_EI \
and_EI or_EI xor_EI insert_EI mul_GE add_GE condloadstore \
- op_exception fgx stck stckf stcke stfle cksm mvcl clcl
+ op_exception fgx stck stckf stcke stfle cksm mvcl clcl troo \
+ trto trot trtt tr tre cij cgij clij clgij crj cgrj clrj clgrj \
+ cs csg cds cdsg cu21 cu21_1 cu24 cu24_1 cu42 cu12 cu12_1 \
+ ex_sig ex_clone cu14 cu14_1 cu41 fpconv
check_PROGRAMS = $(INSN_TESTS) \
- ex_sig \
- ex_clone \
+ allexec \
op00
EXTRA_DIST = \
$(addsuffix .stderr.exp,$(INSN_TESTS)) \
$(addsuffix .stdout.exp,$(INSN_TESTS)) \
$(addsuffix .vgtest,$(INSN_TESTS)) \
- ex_sig.stdout.exp ex_sig.stderr.exp ex_sig.vgtest \
- ex_clone.stdout.exp ex_clone.stderr.exp ex_clone.vgtest \
op00.stderr.exp1 op00.stderr.exp2 op00.vgtest \
test.h opcodes.h add.h and.h div.h insert.h \
- mul.h or.h sub.h test.h xor.h
+ mul.h or.h sub.h test.h xor.h table.h
AM_CFLAGS += @FLAG_M64@
AM_CXXFLAGS += @FLAG_M64@
AM_CCASFLAGS += @FLAG_M64@
-ex_clone_LDFLAGS = -lpthread
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
tcxb_CFLAGS = $(AM_CFLAGS) -std=gnu99
+cu12_1_CFLAGS = $(AM_CFLAGS) -DM3=1
+cu14_1_CFLAGS = $(AM_CFLAGS) -DM3=1
+cu21_1_CFLAGS = $(AM_CFLAGS) -DM3=1
+cu24_1_CFLAGS = $(AM_CFLAGS) -DM3=1
+
+ex_clone_LDFLAGS = -lpthread
diff --git a/main/none/tests/s390x/Makefile.in b/main/none/tests/s390x/Makefile.in
new file mode 100644
index 0000000..7555aab
--- /dev/null
+++ b/main/none/tests/s390x/Makefile.in
@@ -0,0 +1,1348 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = $(am__EXEEXT_1) allexec$(EXEEXT) op00$(EXEEXT)
+subdir = none/tests/s390x
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+am__EXEEXT_1 = clc$(EXEEXT) clcle$(EXEEXT) cvb$(EXEEXT) cvd$(EXEEXT) \
+ icm$(EXEEXT) lpr$(EXEEXT) tcxb$(EXEEXT) lam_stam$(EXEEXT) \
+ xc$(EXEEXT) mvst$(EXEEXT) add$(EXEEXT) sub$(EXEEXT) \
+ mul$(EXEEXT) and$(EXEEXT) or$(EXEEXT) xor$(EXEEXT) \
+ insert$(EXEEXT) div$(EXEEXT) srst$(EXEEXT) fold_And16$(EXEEXT) \
+ flogr$(EXEEXT) sub_EI$(EXEEXT) add_EI$(EXEEXT) and_EI$(EXEEXT) \
+ or_EI$(EXEEXT) xor_EI$(EXEEXT) insert_EI$(EXEEXT) \
+ mul_GE$(EXEEXT) add_GE$(EXEEXT) condloadstore$(EXEEXT) \
+ op_exception$(EXEEXT) fgx$(EXEEXT) stck$(EXEEXT) \
+ stckf$(EXEEXT) stcke$(EXEEXT) stfle$(EXEEXT) cksm$(EXEEXT) \
+ mvcl$(EXEEXT) clcl$(EXEEXT) troo$(EXEEXT) trto$(EXEEXT) \
+ trot$(EXEEXT) trtt$(EXEEXT) tr$(EXEEXT) tre$(EXEEXT) \
+ cij$(EXEEXT) cgij$(EXEEXT) clij$(EXEEXT) clgij$(EXEEXT) \
+ crj$(EXEEXT) cgrj$(EXEEXT) clrj$(EXEEXT) clgrj$(EXEEXT) \
+ cs$(EXEEXT) csg$(EXEEXT) cds$(EXEEXT) cdsg$(EXEEXT) \
+ cu21$(EXEEXT) cu21_1$(EXEEXT) cu24$(EXEEXT) cu24_1$(EXEEXT) \
+ cu42$(EXEEXT) cu12$(EXEEXT) cu12_1$(EXEEXT) ex_sig$(EXEEXT) \
+ ex_clone$(EXEEXT) cu14$(EXEEXT) cu14_1$(EXEEXT) cu41$(EXEEXT) \
+ fpconv$(EXEEXT)
+add_SOURCES = add.c
+add_OBJECTS = add.$(OBJEXT)
+add_LDADD = $(LDADD)
+add_EI_SOURCES = add_EI.c
+add_EI_OBJECTS = add_EI.$(OBJEXT)
+add_EI_LDADD = $(LDADD)
+add_GE_SOURCES = add_GE.c
+add_GE_OBJECTS = add_GE.$(OBJEXT)
+add_GE_LDADD = $(LDADD)
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+and_SOURCES = and.c
+and_OBJECTS = and.$(OBJEXT)
+and_LDADD = $(LDADD)
+and_EI_SOURCES = and_EI.c
+and_EI_OBJECTS = and_EI.$(OBJEXT)
+and_EI_LDADD = $(LDADD)
+cds_SOURCES = cds.c
+cds_OBJECTS = cds.$(OBJEXT)
+cds_LDADD = $(LDADD)
+cdsg_SOURCES = cdsg.c
+cdsg_OBJECTS = cdsg.$(OBJEXT)
+cdsg_LDADD = $(LDADD)
+cgij_SOURCES = cgij.c
+cgij_OBJECTS = cgij.$(OBJEXT)
+cgij_LDADD = $(LDADD)
+cgrj_SOURCES = cgrj.c
+cgrj_OBJECTS = cgrj.$(OBJEXT)
+cgrj_LDADD = $(LDADD)
+cij_SOURCES = cij.c
+cij_OBJECTS = cij.$(OBJEXT)
+cij_LDADD = $(LDADD)
+cksm_SOURCES = cksm.c
+cksm_OBJECTS = cksm.$(OBJEXT)
+cksm_LDADD = $(LDADD)
+clc_SOURCES = clc.c
+clc_OBJECTS = clc.$(OBJEXT)
+clc_LDADD = $(LDADD)
+clcl_SOURCES = clcl.c
+clcl_OBJECTS = clcl.$(OBJEXT)
+clcl_LDADD = $(LDADD)
+clcle_SOURCES = clcle.c
+clcle_OBJECTS = clcle.$(OBJEXT)
+clcle_LDADD = $(LDADD)
+clgij_SOURCES = clgij.c
+clgij_OBJECTS = clgij.$(OBJEXT)
+clgij_LDADD = $(LDADD)
+clgrj_SOURCES = clgrj.c
+clgrj_OBJECTS = clgrj.$(OBJEXT)
+clgrj_LDADD = $(LDADD)
+clij_SOURCES = clij.c
+clij_OBJECTS = clij.$(OBJEXT)
+clij_LDADD = $(LDADD)
+clrj_SOURCES = clrj.c
+clrj_OBJECTS = clrj.$(OBJEXT)
+clrj_LDADD = $(LDADD)
+condloadstore_SOURCES = condloadstore.c
+condloadstore_OBJECTS = condloadstore.$(OBJEXT)
+condloadstore_LDADD = $(LDADD)
+crj_SOURCES = crj.c
+crj_OBJECTS = crj.$(OBJEXT)
+crj_LDADD = $(LDADD)
+cs_SOURCES = cs.c
+cs_OBJECTS = cs.$(OBJEXT)
+cs_LDADD = $(LDADD)
+csg_SOURCES = csg.c
+csg_OBJECTS = csg.$(OBJEXT)
+csg_LDADD = $(LDADD)
+cu12_SOURCES = cu12.c
+cu12_OBJECTS = cu12.$(OBJEXT)
+cu12_LDADD = $(LDADD)
+cu12_1_SOURCES = cu12_1.c
+cu12_1_OBJECTS = cu12_1-cu12_1.$(OBJEXT)
+cu12_1_LDADD = $(LDADD)
+cu12_1_LINK = $(CCLD) $(cu12_1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cu14_SOURCES = cu14.c
+cu14_OBJECTS = cu14.$(OBJEXT)
+cu14_LDADD = $(LDADD)
+cu14_1_SOURCES = cu14_1.c
+cu14_1_OBJECTS = cu14_1-cu14_1.$(OBJEXT)
+cu14_1_LDADD = $(LDADD)
+cu14_1_LINK = $(CCLD) $(cu14_1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cu21_SOURCES = cu21.c
+cu21_OBJECTS = cu21.$(OBJEXT)
+cu21_LDADD = $(LDADD)
+cu21_1_SOURCES = cu21_1.c
+cu21_1_OBJECTS = cu21_1-cu21_1.$(OBJEXT)
+cu21_1_LDADD = $(LDADD)
+cu21_1_LINK = $(CCLD) $(cu21_1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cu24_SOURCES = cu24.c
+cu24_OBJECTS = cu24.$(OBJEXT)
+cu24_LDADD = $(LDADD)
+cu24_1_SOURCES = cu24_1.c
+cu24_1_OBJECTS = cu24_1-cu24_1.$(OBJEXT)
+cu24_1_LDADD = $(LDADD)
+cu24_1_LINK = $(CCLD) $(cu24_1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cu41_SOURCES = cu41.c
+cu41_OBJECTS = cu41.$(OBJEXT)
+cu41_LDADD = $(LDADD)
+cu42_SOURCES = cu42.c
+cu42_OBJECTS = cu42.$(OBJEXT)
+cu42_LDADD = $(LDADD)
+cvb_SOURCES = cvb.c
+cvb_OBJECTS = cvb.$(OBJEXT)
+cvb_LDADD = $(LDADD)
+cvd_SOURCES = cvd.c
+cvd_OBJECTS = cvd.$(OBJEXT)
+cvd_LDADD = $(LDADD)
+div_SOURCES = div.c
+div_OBJECTS = div.$(OBJEXT)
+div_LDADD = $(LDADD)
+ex_clone_SOURCES = ex_clone.c
+ex_clone_OBJECTS = ex_clone.$(OBJEXT)
+ex_clone_LDADD = $(LDADD)
+ex_clone_LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(ex_clone_LDFLAGS) \
+ $(LDFLAGS) -o $@
+ex_sig_SOURCES = ex_sig.c
+ex_sig_OBJECTS = ex_sig.$(OBJEXT)
+ex_sig_LDADD = $(LDADD)
+fgx_SOURCES = fgx.c
+fgx_OBJECTS = fgx.$(OBJEXT)
+fgx_LDADD = $(LDADD)
+flogr_SOURCES = flogr.c
+flogr_OBJECTS = flogr.$(OBJEXT)
+flogr_LDADD = $(LDADD)
+fold_And16_SOURCES = fold_And16.c
+fold_And16_OBJECTS = fold_And16.$(OBJEXT)
+fold_And16_LDADD = $(LDADD)
+fpconv_SOURCES = fpconv.c
+fpconv_OBJECTS = fpconv.$(OBJEXT)
+fpconv_LDADD = $(LDADD)
+icm_SOURCES = icm.c
+icm_OBJECTS = icm.$(OBJEXT)
+icm_LDADD = $(LDADD)
+insert_SOURCES = insert.c
+insert_OBJECTS = insert.$(OBJEXT)
+insert_LDADD = $(LDADD)
+insert_EI_SOURCES = insert_EI.c
+insert_EI_OBJECTS = insert_EI.$(OBJEXT)
+insert_EI_LDADD = $(LDADD)
+lam_stam_SOURCES = lam_stam.c
+lam_stam_OBJECTS = lam_stam.$(OBJEXT)
+lam_stam_LDADD = $(LDADD)
+lpr_SOURCES = lpr.c
+lpr_OBJECTS = lpr.$(OBJEXT)
+lpr_LDADD = $(LDADD)
+mul_SOURCES = mul.c
+mul_OBJECTS = mul.$(OBJEXT)
+mul_LDADD = $(LDADD)
+mul_GE_SOURCES = mul_GE.c
+mul_GE_OBJECTS = mul_GE.$(OBJEXT)
+mul_GE_LDADD = $(LDADD)
+mvcl_SOURCES = mvcl.c
+mvcl_OBJECTS = mvcl.$(OBJEXT)
+mvcl_LDADD = $(LDADD)
+mvst_SOURCES = mvst.c
+mvst_OBJECTS = mvst.$(OBJEXT)
+mvst_LDADD = $(LDADD)
+op00_SOURCES = op00.c
+op00_OBJECTS = op00.$(OBJEXT)
+op00_LDADD = $(LDADD)
+op_exception_SOURCES = op_exception.c
+op_exception_OBJECTS = op_exception.$(OBJEXT)
+op_exception_LDADD = $(LDADD)
+or_SOURCES = or.c
+or_OBJECTS = or.$(OBJEXT)
+or_LDADD = $(LDADD)
+or_EI_SOURCES = or_EI.c
+or_EI_OBJECTS = or_EI.$(OBJEXT)
+or_EI_LDADD = $(LDADD)
+srst_SOURCES = srst.c
+srst_OBJECTS = srst.$(OBJEXT)
+srst_LDADD = $(LDADD)
+stck_SOURCES = stck.c
+stck_OBJECTS = stck.$(OBJEXT)
+stck_LDADD = $(LDADD)
+stcke_SOURCES = stcke.c
+stcke_OBJECTS = stcke.$(OBJEXT)
+stcke_LDADD = $(LDADD)
+stckf_SOURCES = stckf.c
+stckf_OBJECTS = stckf.$(OBJEXT)
+stckf_LDADD = $(LDADD)
+stfle_SOURCES = stfle.c
+stfle_OBJECTS = stfle.$(OBJEXT)
+stfle_LDADD = $(LDADD)
+sub_SOURCES = sub.c
+sub_OBJECTS = sub.$(OBJEXT)
+sub_LDADD = $(LDADD)
+sub_EI_SOURCES = sub_EI.c
+sub_EI_OBJECTS = sub_EI.$(OBJEXT)
+sub_EI_LDADD = $(LDADD)
+tcxb_SOURCES = tcxb.c
+tcxb_OBJECTS = tcxb-tcxb.$(OBJEXT)
+tcxb_LDADD = $(LDADD)
+tcxb_LINK = $(CCLD) $(tcxb_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+tr_SOURCES = tr.c
+tr_OBJECTS = tr.$(OBJEXT)
+tr_LDADD = $(LDADD)
+tre_SOURCES = tre.c
+tre_OBJECTS = tre.$(OBJEXT)
+tre_LDADD = $(LDADD)
+troo_SOURCES = troo.c
+troo_OBJECTS = troo.$(OBJEXT)
+troo_LDADD = $(LDADD)
+trot_SOURCES = trot.c
+trot_OBJECTS = trot.$(OBJEXT)
+trot_LDADD = $(LDADD)
+trto_SOURCES = trto.c
+trto_OBJECTS = trto.$(OBJEXT)
+trto_LDADD = $(LDADD)
+trtt_SOURCES = trtt.c
+trtt_OBJECTS = trtt.$(OBJEXT)
+trtt_LDADD = $(LDADD)
+xc_SOURCES = xc.c
+xc_OBJECTS = xc.$(OBJEXT)
+xc_LDADD = $(LDADD)
+xor_SOURCES = xor.c
+xor_OBJECTS = xor.$(OBJEXT)
+xor_LDADD = $(LDADD)
+xor_EI_SOURCES = xor_EI.c
+xor_EI_OBJECTS = xor_EI.$(OBJEXT)
+xor_EI_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = add.c add_EI.c add_GE.c allexec.c and.c and_EI.c cds.c \
+ cdsg.c cgij.c cgrj.c cij.c cksm.c clc.c clcl.c clcle.c clgij.c \
+ clgrj.c clij.c clrj.c condloadstore.c crj.c cs.c csg.c cu12.c \
+ cu12_1.c cu14.c cu14_1.c cu21.c cu21_1.c cu24.c cu24_1.c \
+ cu41.c cu42.c cvb.c cvd.c div.c ex_clone.c ex_sig.c fgx.c \
+ flogr.c fold_And16.c fpconv.c icm.c insert.c insert_EI.c \
+ lam_stam.c lpr.c mul.c mul_GE.c mvcl.c mvst.c op00.c \
+ op_exception.c or.c or_EI.c srst.c stck.c stcke.c stckf.c \
+ stfle.c sub.c sub_EI.c tcxb.c tr.c tre.c troo.c trot.c trto.c \
+ trtt.c xc.c xor.c xor_EI.c
+DIST_SOURCES = add.c add_EI.c add_GE.c allexec.c and.c and_EI.c cds.c \
+ cdsg.c cgij.c cgrj.c cij.c cksm.c clc.c clcl.c clcle.c clgij.c \
+ clgrj.c clij.c clrj.c condloadstore.c crj.c cs.c csg.c cu12.c \
+ cu12_1.c cu14.c cu14_1.c cu21.c cu21_1.c cu24.c cu24_1.c \
+ cu41.c cu42.c cvb.c cvd.c div.c ex_clone.c ex_sig.c fgx.c \
+ flogr.c fold_And16.c fpconv.c icm.c insert.c insert_EI.c \
+ lam_stam.c lpr.c mul.c mul_GE.c mvcl.c mvst.c op00.c \
+ op_exception.c or.c or_EI.c srst.c stck.c stcke.c stckf.c \
+ stfle.c sub.c sub_EI.c tcxb.c tr.c tre.c troo.c trot.c trto.c \
+ trtt.c xc.c xor.c xor_EI.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \
+ and or xor insert div srst fold_And16 flogr sub_EI add_EI \
+ and_EI or_EI xor_EI insert_EI mul_GE add_GE condloadstore \
+ op_exception fgx stck stckf stcke stfle cksm mvcl clcl troo \
+ trto trot trtt tr tre cij cgij clij clgij crj cgrj clrj clgrj \
+ cs csg cds cdsg cu21 cu21_1 cu24 cu24_1 cu42 cu12 cu12_1 \
+ ex_sig ex_clone cu14 cu14_1 cu41 fpconv
+
+EXTRA_DIST = \
+ $(addsuffix .stderr.exp,$(INSN_TESTS)) \
+ $(addsuffix .stdout.exp,$(INSN_TESTS)) \
+ $(addsuffix .vgtest,$(INSN_TESTS)) \
+ op00.stderr.exp1 op00.stderr.exp2 op00.vgtest \
+ test.h opcodes.h add.h and.h div.h insert.h \
+ mul.h or.h sub.h test.h xor.h table.h
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+tcxb_CFLAGS = $(AM_CFLAGS) -std=gnu99
+cu12_1_CFLAGS = $(AM_CFLAGS) -DM3=1
+cu14_1_CFLAGS = $(AM_CFLAGS) -DM3=1
+cu21_1_CFLAGS = $(AM_CFLAGS) -DM3=1
+cu24_1_CFLAGS = $(AM_CFLAGS) -DM3=1
+ex_clone_LDFLAGS = -lpthread
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/s390x/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/s390x/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+add$(EXEEXT): $(add_OBJECTS) $(add_DEPENDENCIES)
+ @rm -f add$(EXEEXT)
+ $(LINK) $(add_OBJECTS) $(add_LDADD) $(LIBS)
+add_EI$(EXEEXT): $(add_EI_OBJECTS) $(add_EI_DEPENDENCIES)
+ @rm -f add_EI$(EXEEXT)
+ $(LINK) $(add_EI_OBJECTS) $(add_EI_LDADD) $(LIBS)
+add_GE$(EXEEXT): $(add_GE_OBJECTS) $(add_GE_DEPENDENCIES)
+ @rm -f add_GE$(EXEEXT)
+ $(LINK) $(add_GE_OBJECTS) $(add_GE_LDADD) $(LIBS)
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+and$(EXEEXT): $(and_OBJECTS) $(and_DEPENDENCIES)
+ @rm -f and$(EXEEXT)
+ $(LINK) $(and_OBJECTS) $(and_LDADD) $(LIBS)
+and_EI$(EXEEXT): $(and_EI_OBJECTS) $(and_EI_DEPENDENCIES)
+ @rm -f and_EI$(EXEEXT)
+ $(LINK) $(and_EI_OBJECTS) $(and_EI_LDADD) $(LIBS)
+cds$(EXEEXT): $(cds_OBJECTS) $(cds_DEPENDENCIES)
+ @rm -f cds$(EXEEXT)
+ $(LINK) $(cds_OBJECTS) $(cds_LDADD) $(LIBS)
+cdsg$(EXEEXT): $(cdsg_OBJECTS) $(cdsg_DEPENDENCIES)
+ @rm -f cdsg$(EXEEXT)
+ $(LINK) $(cdsg_OBJECTS) $(cdsg_LDADD) $(LIBS)
+cgij$(EXEEXT): $(cgij_OBJECTS) $(cgij_DEPENDENCIES)
+ @rm -f cgij$(EXEEXT)
+ $(LINK) $(cgij_OBJECTS) $(cgij_LDADD) $(LIBS)
+cgrj$(EXEEXT): $(cgrj_OBJECTS) $(cgrj_DEPENDENCIES)
+ @rm -f cgrj$(EXEEXT)
+ $(LINK) $(cgrj_OBJECTS) $(cgrj_LDADD) $(LIBS)
+cij$(EXEEXT): $(cij_OBJECTS) $(cij_DEPENDENCIES)
+ @rm -f cij$(EXEEXT)
+ $(LINK) $(cij_OBJECTS) $(cij_LDADD) $(LIBS)
+cksm$(EXEEXT): $(cksm_OBJECTS) $(cksm_DEPENDENCIES)
+ @rm -f cksm$(EXEEXT)
+ $(LINK) $(cksm_OBJECTS) $(cksm_LDADD) $(LIBS)
+clc$(EXEEXT): $(clc_OBJECTS) $(clc_DEPENDENCIES)
+ @rm -f clc$(EXEEXT)
+ $(LINK) $(clc_OBJECTS) $(clc_LDADD) $(LIBS)
+clcl$(EXEEXT): $(clcl_OBJECTS) $(clcl_DEPENDENCIES)
+ @rm -f clcl$(EXEEXT)
+ $(LINK) $(clcl_OBJECTS) $(clcl_LDADD) $(LIBS)
+clcle$(EXEEXT): $(clcle_OBJECTS) $(clcle_DEPENDENCIES)
+ @rm -f clcle$(EXEEXT)
+ $(LINK) $(clcle_OBJECTS) $(clcle_LDADD) $(LIBS)
+clgij$(EXEEXT): $(clgij_OBJECTS) $(clgij_DEPENDENCIES)
+ @rm -f clgij$(EXEEXT)
+ $(LINK) $(clgij_OBJECTS) $(clgij_LDADD) $(LIBS)
+clgrj$(EXEEXT): $(clgrj_OBJECTS) $(clgrj_DEPENDENCIES)
+ @rm -f clgrj$(EXEEXT)
+ $(LINK) $(clgrj_OBJECTS) $(clgrj_LDADD) $(LIBS)
+clij$(EXEEXT): $(clij_OBJECTS) $(clij_DEPENDENCIES)
+ @rm -f clij$(EXEEXT)
+ $(LINK) $(clij_OBJECTS) $(clij_LDADD) $(LIBS)
+clrj$(EXEEXT): $(clrj_OBJECTS) $(clrj_DEPENDENCIES)
+ @rm -f clrj$(EXEEXT)
+ $(LINK) $(clrj_OBJECTS) $(clrj_LDADD) $(LIBS)
+condloadstore$(EXEEXT): $(condloadstore_OBJECTS) $(condloadstore_DEPENDENCIES)
+ @rm -f condloadstore$(EXEEXT)
+ $(LINK) $(condloadstore_OBJECTS) $(condloadstore_LDADD) $(LIBS)
+crj$(EXEEXT): $(crj_OBJECTS) $(crj_DEPENDENCIES)
+ @rm -f crj$(EXEEXT)
+ $(LINK) $(crj_OBJECTS) $(crj_LDADD) $(LIBS)
+cs$(EXEEXT): $(cs_OBJECTS) $(cs_DEPENDENCIES)
+ @rm -f cs$(EXEEXT)
+ $(LINK) $(cs_OBJECTS) $(cs_LDADD) $(LIBS)
+csg$(EXEEXT): $(csg_OBJECTS) $(csg_DEPENDENCIES)
+ @rm -f csg$(EXEEXT)
+ $(LINK) $(csg_OBJECTS) $(csg_LDADD) $(LIBS)
+cu12$(EXEEXT): $(cu12_OBJECTS) $(cu12_DEPENDENCIES)
+ @rm -f cu12$(EXEEXT)
+ $(LINK) $(cu12_OBJECTS) $(cu12_LDADD) $(LIBS)
+cu12_1$(EXEEXT): $(cu12_1_OBJECTS) $(cu12_1_DEPENDENCIES)
+ @rm -f cu12_1$(EXEEXT)
+ $(cu12_1_LINK) $(cu12_1_OBJECTS) $(cu12_1_LDADD) $(LIBS)
+cu14$(EXEEXT): $(cu14_OBJECTS) $(cu14_DEPENDENCIES)
+ @rm -f cu14$(EXEEXT)
+ $(LINK) $(cu14_OBJECTS) $(cu14_LDADD) $(LIBS)
+cu14_1$(EXEEXT): $(cu14_1_OBJECTS) $(cu14_1_DEPENDENCIES)
+ @rm -f cu14_1$(EXEEXT)
+ $(cu14_1_LINK) $(cu14_1_OBJECTS) $(cu14_1_LDADD) $(LIBS)
+cu21$(EXEEXT): $(cu21_OBJECTS) $(cu21_DEPENDENCIES)
+ @rm -f cu21$(EXEEXT)
+ $(LINK) $(cu21_OBJECTS) $(cu21_LDADD) $(LIBS)
+cu21_1$(EXEEXT): $(cu21_1_OBJECTS) $(cu21_1_DEPENDENCIES)
+ @rm -f cu21_1$(EXEEXT)
+ $(cu21_1_LINK) $(cu21_1_OBJECTS) $(cu21_1_LDADD) $(LIBS)
+cu24$(EXEEXT): $(cu24_OBJECTS) $(cu24_DEPENDENCIES)
+ @rm -f cu24$(EXEEXT)
+ $(LINK) $(cu24_OBJECTS) $(cu24_LDADD) $(LIBS)
+cu24_1$(EXEEXT): $(cu24_1_OBJECTS) $(cu24_1_DEPENDENCIES)
+ @rm -f cu24_1$(EXEEXT)
+ $(cu24_1_LINK) $(cu24_1_OBJECTS) $(cu24_1_LDADD) $(LIBS)
+cu41$(EXEEXT): $(cu41_OBJECTS) $(cu41_DEPENDENCIES)
+ @rm -f cu41$(EXEEXT)
+ $(LINK) $(cu41_OBJECTS) $(cu41_LDADD) $(LIBS)
+cu42$(EXEEXT): $(cu42_OBJECTS) $(cu42_DEPENDENCIES)
+ @rm -f cu42$(EXEEXT)
+ $(LINK) $(cu42_OBJECTS) $(cu42_LDADD) $(LIBS)
+cvb$(EXEEXT): $(cvb_OBJECTS) $(cvb_DEPENDENCIES)
+ @rm -f cvb$(EXEEXT)
+ $(LINK) $(cvb_OBJECTS) $(cvb_LDADD) $(LIBS)
+cvd$(EXEEXT): $(cvd_OBJECTS) $(cvd_DEPENDENCIES)
+ @rm -f cvd$(EXEEXT)
+ $(LINK) $(cvd_OBJECTS) $(cvd_LDADD) $(LIBS)
+div$(EXEEXT): $(div_OBJECTS) $(div_DEPENDENCIES)
+ @rm -f div$(EXEEXT)
+ $(LINK) $(div_OBJECTS) $(div_LDADD) $(LIBS)
+ex_clone$(EXEEXT): $(ex_clone_OBJECTS) $(ex_clone_DEPENDENCIES)
+ @rm -f ex_clone$(EXEEXT)
+ $(ex_clone_LINK) $(ex_clone_OBJECTS) $(ex_clone_LDADD) $(LIBS)
+ex_sig$(EXEEXT): $(ex_sig_OBJECTS) $(ex_sig_DEPENDENCIES)
+ @rm -f ex_sig$(EXEEXT)
+ $(LINK) $(ex_sig_OBJECTS) $(ex_sig_LDADD) $(LIBS)
+fgx$(EXEEXT): $(fgx_OBJECTS) $(fgx_DEPENDENCIES)
+ @rm -f fgx$(EXEEXT)
+ $(LINK) $(fgx_OBJECTS) $(fgx_LDADD) $(LIBS)
+flogr$(EXEEXT): $(flogr_OBJECTS) $(flogr_DEPENDENCIES)
+ @rm -f flogr$(EXEEXT)
+ $(LINK) $(flogr_OBJECTS) $(flogr_LDADD) $(LIBS)
+fold_And16$(EXEEXT): $(fold_And16_OBJECTS) $(fold_And16_DEPENDENCIES)
+ @rm -f fold_And16$(EXEEXT)
+ $(LINK) $(fold_And16_OBJECTS) $(fold_And16_LDADD) $(LIBS)
+fpconv$(EXEEXT): $(fpconv_OBJECTS) $(fpconv_DEPENDENCIES)
+ @rm -f fpconv$(EXEEXT)
+ $(LINK) $(fpconv_OBJECTS) $(fpconv_LDADD) $(LIBS)
+icm$(EXEEXT): $(icm_OBJECTS) $(icm_DEPENDENCIES)
+ @rm -f icm$(EXEEXT)
+ $(LINK) $(icm_OBJECTS) $(icm_LDADD) $(LIBS)
+insert$(EXEEXT): $(insert_OBJECTS) $(insert_DEPENDENCIES)
+ @rm -f insert$(EXEEXT)
+ $(LINK) $(insert_OBJECTS) $(insert_LDADD) $(LIBS)
+insert_EI$(EXEEXT): $(insert_EI_OBJECTS) $(insert_EI_DEPENDENCIES)
+ @rm -f insert_EI$(EXEEXT)
+ $(LINK) $(insert_EI_OBJECTS) $(insert_EI_LDADD) $(LIBS)
+lam_stam$(EXEEXT): $(lam_stam_OBJECTS) $(lam_stam_DEPENDENCIES)
+ @rm -f lam_stam$(EXEEXT)
+ $(LINK) $(lam_stam_OBJECTS) $(lam_stam_LDADD) $(LIBS)
+lpr$(EXEEXT): $(lpr_OBJECTS) $(lpr_DEPENDENCIES)
+ @rm -f lpr$(EXEEXT)
+ $(LINK) $(lpr_OBJECTS) $(lpr_LDADD) $(LIBS)
+mul$(EXEEXT): $(mul_OBJECTS) $(mul_DEPENDENCIES)
+ @rm -f mul$(EXEEXT)
+ $(LINK) $(mul_OBJECTS) $(mul_LDADD) $(LIBS)
+mul_GE$(EXEEXT): $(mul_GE_OBJECTS) $(mul_GE_DEPENDENCIES)
+ @rm -f mul_GE$(EXEEXT)
+ $(LINK) $(mul_GE_OBJECTS) $(mul_GE_LDADD) $(LIBS)
+mvcl$(EXEEXT): $(mvcl_OBJECTS) $(mvcl_DEPENDENCIES)
+ @rm -f mvcl$(EXEEXT)
+ $(LINK) $(mvcl_OBJECTS) $(mvcl_LDADD) $(LIBS)
+mvst$(EXEEXT): $(mvst_OBJECTS) $(mvst_DEPENDENCIES)
+ @rm -f mvst$(EXEEXT)
+ $(LINK) $(mvst_OBJECTS) $(mvst_LDADD) $(LIBS)
+op00$(EXEEXT): $(op00_OBJECTS) $(op00_DEPENDENCIES)
+ @rm -f op00$(EXEEXT)
+ $(LINK) $(op00_OBJECTS) $(op00_LDADD) $(LIBS)
+op_exception$(EXEEXT): $(op_exception_OBJECTS) $(op_exception_DEPENDENCIES)
+ @rm -f op_exception$(EXEEXT)
+ $(LINK) $(op_exception_OBJECTS) $(op_exception_LDADD) $(LIBS)
+or$(EXEEXT): $(or_OBJECTS) $(or_DEPENDENCIES)
+ @rm -f or$(EXEEXT)
+ $(LINK) $(or_OBJECTS) $(or_LDADD) $(LIBS)
+or_EI$(EXEEXT): $(or_EI_OBJECTS) $(or_EI_DEPENDENCIES)
+ @rm -f or_EI$(EXEEXT)
+ $(LINK) $(or_EI_OBJECTS) $(or_EI_LDADD) $(LIBS)
+srst$(EXEEXT): $(srst_OBJECTS) $(srst_DEPENDENCIES)
+ @rm -f srst$(EXEEXT)
+ $(LINK) $(srst_OBJECTS) $(srst_LDADD) $(LIBS)
+stck$(EXEEXT): $(stck_OBJECTS) $(stck_DEPENDENCIES)
+ @rm -f stck$(EXEEXT)
+ $(LINK) $(stck_OBJECTS) $(stck_LDADD) $(LIBS)
+stcke$(EXEEXT): $(stcke_OBJECTS) $(stcke_DEPENDENCIES)
+ @rm -f stcke$(EXEEXT)
+ $(LINK) $(stcke_OBJECTS) $(stcke_LDADD) $(LIBS)
+stckf$(EXEEXT): $(stckf_OBJECTS) $(stckf_DEPENDENCIES)
+ @rm -f stckf$(EXEEXT)
+ $(LINK) $(stckf_OBJECTS) $(stckf_LDADD) $(LIBS)
+stfle$(EXEEXT): $(stfle_OBJECTS) $(stfle_DEPENDENCIES)
+ @rm -f stfle$(EXEEXT)
+ $(LINK) $(stfle_OBJECTS) $(stfle_LDADD) $(LIBS)
+sub$(EXEEXT): $(sub_OBJECTS) $(sub_DEPENDENCIES)
+ @rm -f sub$(EXEEXT)
+ $(LINK) $(sub_OBJECTS) $(sub_LDADD) $(LIBS)
+sub_EI$(EXEEXT): $(sub_EI_OBJECTS) $(sub_EI_DEPENDENCIES)
+ @rm -f sub_EI$(EXEEXT)
+ $(LINK) $(sub_EI_OBJECTS) $(sub_EI_LDADD) $(LIBS)
+tcxb$(EXEEXT): $(tcxb_OBJECTS) $(tcxb_DEPENDENCIES)
+ @rm -f tcxb$(EXEEXT)
+ $(tcxb_LINK) $(tcxb_OBJECTS) $(tcxb_LDADD) $(LIBS)
+tr$(EXEEXT): $(tr_OBJECTS) $(tr_DEPENDENCIES)
+ @rm -f tr$(EXEEXT)
+ $(LINK) $(tr_OBJECTS) $(tr_LDADD) $(LIBS)
+tre$(EXEEXT): $(tre_OBJECTS) $(tre_DEPENDENCIES)
+ @rm -f tre$(EXEEXT)
+ $(LINK) $(tre_OBJECTS) $(tre_LDADD) $(LIBS)
+troo$(EXEEXT): $(troo_OBJECTS) $(troo_DEPENDENCIES)
+ @rm -f troo$(EXEEXT)
+ $(LINK) $(troo_OBJECTS) $(troo_LDADD) $(LIBS)
+trot$(EXEEXT): $(trot_OBJECTS) $(trot_DEPENDENCIES)
+ @rm -f trot$(EXEEXT)
+ $(LINK) $(trot_OBJECTS) $(trot_LDADD) $(LIBS)
+trto$(EXEEXT): $(trto_OBJECTS) $(trto_DEPENDENCIES)
+ @rm -f trto$(EXEEXT)
+ $(LINK) $(trto_OBJECTS) $(trto_LDADD) $(LIBS)
+trtt$(EXEEXT): $(trtt_OBJECTS) $(trtt_DEPENDENCIES)
+ @rm -f trtt$(EXEEXT)
+ $(LINK) $(trtt_OBJECTS) $(trtt_LDADD) $(LIBS)
+xc$(EXEEXT): $(xc_OBJECTS) $(xc_DEPENDENCIES)
+ @rm -f xc$(EXEEXT)
+ $(LINK) $(xc_OBJECTS) $(xc_LDADD) $(LIBS)
+xor$(EXEEXT): $(xor_OBJECTS) $(xor_DEPENDENCIES)
+ @rm -f xor$(EXEEXT)
+ $(LINK) $(xor_OBJECTS) $(xor_LDADD) $(LIBS)
+xor_EI$(EXEEXT): $(xor_EI_OBJECTS) $(xor_EI_DEPENDENCIES)
+ @rm -f xor_EI$(EXEEXT)
+ $(LINK) $(xor_EI_OBJECTS) $(xor_EI_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/add.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/add_EI.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/add_GE.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/and.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/and_EI.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cds.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cdsg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgij.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgrj.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cij.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cksm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clcl.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clcle.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clgij.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clgrj.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clij.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/clrj.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/condloadstore.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/crj.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cs.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/csg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu12.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu12_1-cu12_1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu14.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu14_1-cu14_1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu21.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu21_1-cu21_1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu24.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu24_1-cu24_1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu41.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cu42.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cvb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cvd.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/div.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ex_clone.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ex_sig.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fgx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/flogr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fold_And16.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fpconv.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/icm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insert.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insert_EI.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lam_stam.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lpr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mul.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mul_GE.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mvcl.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mvst.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/op00.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/op_exception.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or_EI.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/srst.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stck.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stcke.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stckf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stfle.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sub.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sub_EI.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tcxb-tcxb.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tre.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/troo.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/trot.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/trto.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/trtt.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xor.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xor_EI.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+allexec-allexec.o: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.o -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+
+allexec-allexec.obj: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.obj -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+
+cu12_1-cu12_1.o: cu12_1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu12_1_CFLAGS) $(CFLAGS) -MT cu12_1-cu12_1.o -MD -MP -MF $(DEPDIR)/cu12_1-cu12_1.Tpo -c -o cu12_1-cu12_1.o `test -f 'cu12_1.c' || echo '$(srcdir)/'`cu12_1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cu12_1-cu12_1.Tpo $(DEPDIR)/cu12_1-cu12_1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cu12_1.c' object='cu12_1-cu12_1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu12_1_CFLAGS) $(CFLAGS) -c -o cu12_1-cu12_1.o `test -f 'cu12_1.c' || echo '$(srcdir)/'`cu12_1.c
+
+cu12_1-cu12_1.obj: cu12_1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu12_1_CFLAGS) $(CFLAGS) -MT cu12_1-cu12_1.obj -MD -MP -MF $(DEPDIR)/cu12_1-cu12_1.Tpo -c -o cu12_1-cu12_1.obj `if test -f 'cu12_1.c'; then $(CYGPATH_W) 'cu12_1.c'; else $(CYGPATH_W) '$(srcdir)/cu12_1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cu12_1-cu12_1.Tpo $(DEPDIR)/cu12_1-cu12_1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cu12_1.c' object='cu12_1-cu12_1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu12_1_CFLAGS) $(CFLAGS) -c -o cu12_1-cu12_1.obj `if test -f 'cu12_1.c'; then $(CYGPATH_W) 'cu12_1.c'; else $(CYGPATH_W) '$(srcdir)/cu12_1.c'; fi`
+
+cu14_1-cu14_1.o: cu14_1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu14_1_CFLAGS) $(CFLAGS) -MT cu14_1-cu14_1.o -MD -MP -MF $(DEPDIR)/cu14_1-cu14_1.Tpo -c -o cu14_1-cu14_1.o `test -f 'cu14_1.c' || echo '$(srcdir)/'`cu14_1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cu14_1-cu14_1.Tpo $(DEPDIR)/cu14_1-cu14_1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cu14_1.c' object='cu14_1-cu14_1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu14_1_CFLAGS) $(CFLAGS) -c -o cu14_1-cu14_1.o `test -f 'cu14_1.c' || echo '$(srcdir)/'`cu14_1.c
+
+cu14_1-cu14_1.obj: cu14_1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu14_1_CFLAGS) $(CFLAGS) -MT cu14_1-cu14_1.obj -MD -MP -MF $(DEPDIR)/cu14_1-cu14_1.Tpo -c -o cu14_1-cu14_1.obj `if test -f 'cu14_1.c'; then $(CYGPATH_W) 'cu14_1.c'; else $(CYGPATH_W) '$(srcdir)/cu14_1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cu14_1-cu14_1.Tpo $(DEPDIR)/cu14_1-cu14_1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cu14_1.c' object='cu14_1-cu14_1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu14_1_CFLAGS) $(CFLAGS) -c -o cu14_1-cu14_1.obj `if test -f 'cu14_1.c'; then $(CYGPATH_W) 'cu14_1.c'; else $(CYGPATH_W) '$(srcdir)/cu14_1.c'; fi`
+
+cu21_1-cu21_1.o: cu21_1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu21_1_CFLAGS) $(CFLAGS) -MT cu21_1-cu21_1.o -MD -MP -MF $(DEPDIR)/cu21_1-cu21_1.Tpo -c -o cu21_1-cu21_1.o `test -f 'cu21_1.c' || echo '$(srcdir)/'`cu21_1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cu21_1-cu21_1.Tpo $(DEPDIR)/cu21_1-cu21_1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cu21_1.c' object='cu21_1-cu21_1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu21_1_CFLAGS) $(CFLAGS) -c -o cu21_1-cu21_1.o `test -f 'cu21_1.c' || echo '$(srcdir)/'`cu21_1.c
+
+cu21_1-cu21_1.obj: cu21_1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu21_1_CFLAGS) $(CFLAGS) -MT cu21_1-cu21_1.obj -MD -MP -MF $(DEPDIR)/cu21_1-cu21_1.Tpo -c -o cu21_1-cu21_1.obj `if test -f 'cu21_1.c'; then $(CYGPATH_W) 'cu21_1.c'; else $(CYGPATH_W) '$(srcdir)/cu21_1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cu21_1-cu21_1.Tpo $(DEPDIR)/cu21_1-cu21_1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cu21_1.c' object='cu21_1-cu21_1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu21_1_CFLAGS) $(CFLAGS) -c -o cu21_1-cu21_1.obj `if test -f 'cu21_1.c'; then $(CYGPATH_W) 'cu21_1.c'; else $(CYGPATH_W) '$(srcdir)/cu21_1.c'; fi`
+
+cu24_1-cu24_1.o: cu24_1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu24_1_CFLAGS) $(CFLAGS) -MT cu24_1-cu24_1.o -MD -MP -MF $(DEPDIR)/cu24_1-cu24_1.Tpo -c -o cu24_1-cu24_1.o `test -f 'cu24_1.c' || echo '$(srcdir)/'`cu24_1.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cu24_1-cu24_1.Tpo $(DEPDIR)/cu24_1-cu24_1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cu24_1.c' object='cu24_1-cu24_1.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu24_1_CFLAGS) $(CFLAGS) -c -o cu24_1-cu24_1.o `test -f 'cu24_1.c' || echo '$(srcdir)/'`cu24_1.c
+
+cu24_1-cu24_1.obj: cu24_1.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu24_1_CFLAGS) $(CFLAGS) -MT cu24_1-cu24_1.obj -MD -MP -MF $(DEPDIR)/cu24_1-cu24_1.Tpo -c -o cu24_1-cu24_1.obj `if test -f 'cu24_1.c'; then $(CYGPATH_W) 'cu24_1.c'; else $(CYGPATH_W) '$(srcdir)/cu24_1.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/cu24_1-cu24_1.Tpo $(DEPDIR)/cu24_1-cu24_1.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='cu24_1.c' object='cu24_1-cu24_1.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(cu24_1_CFLAGS) $(CFLAGS) -c -o cu24_1-cu24_1.obj `if test -f 'cu24_1.c'; then $(CYGPATH_W) 'cu24_1.c'; else $(CYGPATH_W) '$(srcdir)/cu24_1.c'; fi`
+
+tcxb-tcxb.o: tcxb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tcxb_CFLAGS) $(CFLAGS) -MT tcxb-tcxb.o -MD -MP -MF $(DEPDIR)/tcxb-tcxb.Tpo -c -o tcxb-tcxb.o `test -f 'tcxb.c' || echo '$(srcdir)/'`tcxb.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tcxb-tcxb.Tpo $(DEPDIR)/tcxb-tcxb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='tcxb.c' object='tcxb-tcxb.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tcxb_CFLAGS) $(CFLAGS) -c -o tcxb-tcxb.o `test -f 'tcxb.c' || echo '$(srcdir)/'`tcxb.c
+
+tcxb-tcxb.obj: tcxb.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tcxb_CFLAGS) $(CFLAGS) -MT tcxb-tcxb.obj -MD -MP -MF $(DEPDIR)/tcxb-tcxb.Tpo -c -o tcxb-tcxb.obj `if test -f 'tcxb.c'; then $(CYGPATH_W) 'tcxb.c'; else $(CYGPATH_W) '$(srcdir)/tcxb.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tcxb-tcxb.Tpo $(DEPDIR)/tcxb-tcxb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='tcxb.c' object='tcxb-tcxb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tcxb_CFLAGS) $(CFLAGS) -c -o tcxb-tcxb.obj `if test -f 'tcxb.c'; then $(CYGPATH_W) 'tcxb.c'; else $(CYGPATH_W) '$(srcdir)/tcxb.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/s390x/add_EI.vgtest b/main/none/tests/s390x/add_EI.vgtest
index 26b4491..e93e42b 100644
--- a/main/none/tests/s390x/add_EI.vgtest
+++ b/main/none/tests/s390x/add_EI.vgtest
@@ -1,2 +1 @@
prog: add_EI
-prereq: test -x add_EI
diff --git a/main/none/tests/s390x/add_GE.vgtest b/main/none/tests/s390x/add_GE.vgtest
index 836b526..ad135b7 100644
--- a/main/none/tests/s390x/add_GE.vgtest
+++ b/main/none/tests/s390x/add_GE.vgtest
@@ -1,2 +1 @@
prog: add_GE
-prereq: test -x add_GE
diff --git a/main/none/tests/s390x/allexec.c b/main/none/tests/s390x/allexec.c
new file mode 100644
index 0000000..b7177e8
--- /dev/null
+++ b/main/none/tests/s390x/allexec.c
@@ -0,0 +1,50 @@
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+extern char **environ;
+
+#define S(...) (fprintf(stdout, __VA_ARGS__),fflush(stdout))
+#define FORKEXECWAIT(exec_call) do { \
+ int status;\
+ pid_t child = fork(); \
+ if (child == 0) {exec_call; perror ("exec failed");} \
+ else if (child == -1) perror ("cannot fork\n"); \
+ else if (child != wait (&status)) perror ("error waiting child"); \
+ else S("child exited\n"); \
+ } while (0)
+
+void test_allexec (char *exec)
+{
+ FORKEXECWAIT (execlp(exec, exec, NULL));
+ FORKEXECWAIT (execlp(exec, exec, "constant_arg1", "constant_arg2", NULL));
+ FORKEXECWAIT (execve(exec, NULL, environ));
+}
+
+
+/* If a single argument "exec" is given, will execute itself
+ (in bi-arch, a 32 bit and 64 bit variant) via various exec system calls.
+ Note that this test can only be run after the prerequisite have been
+ prepared by allexec_prepare_prereq, which will a.o. make links
+ for the allexec32 and allexec64 executables. On single arch build,
+ these links points to the same executable to ensure this test works
+ everywhere the same.
+ No arguments or more arguments means just print its args. */
+int main(int argc, char **argv, char **envp)
+{
+ if ( (argc == 2) && (strcmp (argv[1], "exec") == 0)) {
+ S("%s will exec ./allexec32\n", argv[0]);
+ test_allexec ("./allexec32");
+ S("%s will exec ./allexec64\n", argv[0]);
+ test_allexec ("./allexec64");
+ } else {
+ int i;
+ S("program exec-ed:");
+ for (i = 0; i < argc; i++) S(" %s", argv[i]);
+ S("\n");
+ }
+ return 0;
+}
diff --git a/main/none/tests/s390x/and_EI.vgtest b/main/none/tests/s390x/and_EI.vgtest
index 0f2a829..af04836 100644
--- a/main/none/tests/s390x/and_EI.vgtest
+++ b/main/none/tests/s390x/and_EI.vgtest
@@ -1,2 +1 @@
prog: and_EI
-prereq: test -x and_EI
diff --git a/main/none/tests/s390x/cds.c b/main/none/tests/s390x/cds.c
new file mode 100644
index 0000000..693f19b
--- /dev/null
+++ b/main/none/tests/s390x/cds.c
@@ -0,0 +1,114 @@
+#include <stdint.h>
+#include <stdio.h>
+
+typedef struct {
+ uint64_t high;
+ uint64_t low;
+} quad_word;
+
+void
+test(quad_word op1_init, uint64_t op2_init, quad_word op3_init,
+ int expected_cc)
+{
+ int cc = 1 - expected_cc;
+
+ quad_word op1 = op1_init;
+ uint64_t op2 = op2_init;
+ quad_word op3 = op3_init;
+
+ quad_word op1_before = op1;
+ uint64_t op2_before = op2;
+ quad_word op3_before = op3;
+
+ printf("before op1 = (%#lx, %#lx)\n", op1.high, op1.low);
+ printf("before op2 = %#lx\n", op2);
+ printf("before op3 = (%#lx, %#lx)\n", op3.high, op3.low);
+
+ __asm__ volatile (
+ "lmg %%r0,%%r1,%1\n\t"
+ "lmg %%r2,%%r3,%3\n\t"
+ "cds %%r0,%%r2,%2\n\t" // cds 1st,3rd,2nd
+ "stmg %%r0,%%r1,%1\n" // store r0,r1 to op1
+ "stmg %%r2,%%r3,%3\n" // store r2,r3 to op3
+ "ipm %0\n\t"
+ "srl %0,28\n\t"
+ : "=d" (cc), "+QS" (op1), "+QS" (op2), "+QS" (op3)
+ :
+ : "r0", "r1", "r2", "r3", "cc");
+
+ printf("after op1 = (%#lx, %#lx)\n", op1.high, op1.low);
+ printf("after op2 = %#lx\n", op2);
+ printf("after op3 = (%#lx, %#lx)\n", op3.high, op3.low);
+ printf("cc = %d\n", cc);
+
+ // Check the condition code
+ if (cc != expected_cc) {
+ printf("condition code is incorrect\n");
+ }
+
+ // op3 never changes
+ if (op3.low != op3_before.low || op3.high != op3_before.high) {
+ printf("operand #3 modified\n");
+ }
+
+ if (expected_cc == 0) {
+ // 3rd operand stored at 2nd operand location
+
+ // op1 did not change
+ if (op1.low != op1_before.low || op1.high != op1_before.high) {
+ printf("operand #1 modified\n");
+ }
+
+ // lower 32 bits of op2 are the lower 32 bits of op3.low
+ if ((op2 & 0xffffffff) != (op3.low & 0xffffffff)) {
+ printf("operand #2 [32:63] incorrect\n");
+ }
+ // higher 32 bits of op2 are the lower 32 bits of op3.high
+ if ((op2 >> 32) != (op3.high & 0xffffffff)) {
+ printf("operand #2 [0:31] incorrect\n");
+ }
+ } else {
+ // 2nd operand stored at 1st operand location
+
+ // op2 did not change
+ if (op2 != op2_before) {
+ printf("operand #2 modified\n");
+ }
+
+ // bits [0:31] of op1 (both parts) are unchanged
+ if ((op1.high >> 32) != (op1_before.high >> 32) ||
+ (op1.low >> 32) != (op1_before.low >> 32)) {
+ printf("operand #1 [0:31] modified\n");
+ }
+
+ if ((op1.low & 0xffffffff) != (op2 & 0xffffffff)) {
+ printf("operand #1 low[32:63] incorrect\n");
+ }
+ if ((op1.high & 0xffffffff) != (op2 >> 32)) {
+ printf("operand #1 high[32:63] not updated\n");
+ }
+ }
+}
+
+int main ()
+{
+ quad_word op1, op3;
+ uint64_t op2;
+
+ // (op1.high[32:63], op1.low[32:63]) == op2
+ op1.high = 0x0000000044556677ull;
+ op1.low = 0x111111118899aabbull;
+ op2 = 0x445566778899aabbull;
+
+ op3.high = op3.low = 0xdeadbeefdeadbabeull;
+ test(op1, op2, op3, 0);
+
+ // (op1.high[32:63], op1.low[32:63]) != op2
+ op1.high = 0x1000000000000000ull;
+ op1.low = 0x0000000000000000ull;
+ op2 = 0x8000000000000001ull;;
+ op3.high = op3.low = 0xdeadbeefdeadbabeull;
+ test(op1, op2, op3, 1);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cds.stderr.exp b/main/none/tests/s390x/cds.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cds.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cds.stdout.exp b/main/none/tests/s390x/cds.stdout.exp
new file mode 100644
index 0000000..7636947
--- /dev/null
+++ b/main/none/tests/s390x/cds.stdout.exp
@@ -0,0 +1,14 @@
+before op1 = (0x44556677, 0x111111118899aabb)
+before op2 = 0x445566778899aabb
+before op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+after op1 = (0x44556677, 0x111111118899aabb)
+after op2 = 0xdeadbabedeadbabe
+after op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+cc = 0
+before op1 = (0x1000000000000000, 0)
+before op2 = 0x8000000000000001
+before op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+after op1 = (0x1000000080000000, 0x1)
+after op2 = 0x8000000000000001
+after op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+cc = 1
diff --git a/main/none/tests/s390x/cds.vgtest b/main/none/tests/s390x/cds.vgtest
new file mode 100644
index 0000000..0daf980
--- /dev/null
+++ b/main/none/tests/s390x/cds.vgtest
@@ -0,0 +1 @@
+prog: cds
diff --git a/main/none/tests/s390x/cdsg.c b/main/none/tests/s390x/cdsg.c
new file mode 100644
index 0000000..6143f56
--- /dev/null
+++ b/main/none/tests/s390x/cdsg.c
@@ -0,0 +1,110 @@
+#include <stdint.h>
+#include <stdio.h>
+
+typedef struct {
+ uint64_t high;
+ uint64_t low;
+} __attribute__((aligned(16))) quad_word;
+
+
+/* CDSG needs quad-word alignment */
+quad_word _op1, _op2, _op3;
+
+void
+test(quad_word op1_init, quad_word op2_init, quad_word op3_init,
+ int expected_cc)
+{
+ quad_word op1_before, op2_before, op3_before;
+ int cc = 1 - expected_cc;
+
+ _op1 = op1_init;
+ _op2 = op2_init;
+ _op3 = op3_init;
+
+ op1_before = _op1;
+ op2_before = _op2;
+ op3_before = _op3;
+
+ printf("before op1 = (%#lx, %#lx)\n", _op1.high, _op1.low);
+ printf("before op2 = (%#lx, %#lx)\n", _op2.high, _op2.low);
+ printf("before op3 = (%#lx, %#lx)\n", _op3.high, _op3.low);
+
+ __asm__ volatile (
+ "lmg %%r0,%%r1,%1\n\t"
+ "lmg %%r2,%%r3,%3\n\t"
+ "cdsg %%r0,%%r2,%2\n\t" // cdsg 1st,3rd,2nd
+ "stmg %%r0,%%r1,%1\n" // store r0,r1 to _op1
+ "stmg %%r2,%%r3,%3\n" // store r2,r3 to _op3
+ "ipm %0\n\t"
+ "srl %0,28\n\t"
+ : "=d" (cc), "+QS" (_op1), "+QS" (_op2), "+QS" (_op3)
+ :
+ : "r0", "r1", "r2", "r3", "cc");
+
+ printf("after op1 = (%#lx, %#lx)\n", _op1.high, _op1.low);
+ printf("after op2 = (%#lx, %#lx)\n", _op2.high, _op2.low);
+ printf("after op3 = (%#lx, %#lx)\n", _op3.high, _op3.low);
+ printf("cc = %d\n", cc);
+
+ if (cc != expected_cc) {
+ printf("condition code is incorrect\n");
+ }
+
+ // _op3 never changes
+ if (_op3.low != op3_before.low || _op3.high != op3_before.high) {
+ printf("operand #3 modified\n");
+ }
+
+ if (expected_cc == 0) {
+ // 3rd operand stored at 2nd operand location
+
+ // _op1 did not change
+ if (_op1.low != op1_before.low || _op1.high != op1_before.high) {
+ printf("operand #1 modified\n");
+ }
+ if (_op2.high != _op3.high || _op2.low != _op3.low) {
+ printf("operand #2 incorrect\n");
+ }
+ } else {
+ // 2nd operand stored at 1st operand location
+
+ // _op2 did not change
+ if (_op2.low != op2_before.low || _op2.high != op2_before.high) {
+ printf("operand #2 modified\n");
+ }
+
+ if (_op1.high != _op2.high || _op1.low != _op2.low) {
+ printf("operand #1 incorrect\n");
+ }
+ }
+}
+
+int main ()
+{
+ quad_word op1, op2, op3;
+
+ // op1 == op2
+ op1.high = 0x0011223344556677ull;
+ op1.low = 0x8899aabbccddeeffull;
+ op2 = op1;
+ op3.high = op3.low = 0xdeadbeefdeadbabeull;
+ test(op1, op2, op3, 0);
+
+ // op1 != op2 (only MSB differs)
+ op1.high = 0x8000000000000000ull;
+ op1.low = 0x0000000000000000ull;
+ op2.high = 0;
+ op2.low = 1;
+ op3.high = op3.low = 0xdeadbeefdeadbabeull;
+ test(op1, op2, op3, 1);
+
+ // op1 != op2 (only LSB differs)
+ op1.high = 0x0000000000000000ull;
+ op1.low = 0x0000000000000001ull;
+ op2.high = 1;
+ op2.low = 0;
+ op3.high = op3.low = 0xdeadbeefdeadbabeull;
+ test(op1, op2, op3, 1);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cdsg.stderr.exp b/main/none/tests/s390x/cdsg.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cdsg.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cdsg.stdout.exp b/main/none/tests/s390x/cdsg.stdout.exp
new file mode 100644
index 0000000..460bfbf
--- /dev/null
+++ b/main/none/tests/s390x/cdsg.stdout.exp
@@ -0,0 +1,21 @@
+before op1 = (0x11223344556677, 0x8899aabbccddeeff)
+before op2 = (0x11223344556677, 0x8899aabbccddeeff)
+before op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+after op1 = (0x11223344556677, 0x8899aabbccddeeff)
+after op2 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+after op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+cc = 0
+before op1 = (0x8000000000000000, 0)
+before op2 = (0, 0x1)
+before op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+after op1 = (0, 0x1)
+after op2 = (0, 0x1)
+after op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+cc = 1
+before op1 = (0, 0x1)
+before op2 = (0x1, 0)
+before op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+after op1 = (0x1, 0)
+after op2 = (0x1, 0)
+after op3 = (0xdeadbeefdeadbabe, 0xdeadbeefdeadbabe)
+cc = 1
diff --git a/main/none/tests/s390x/cdsg.vgtest b/main/none/tests/s390x/cdsg.vgtest
new file mode 100644
index 0000000..e0cd61f
--- /dev/null
+++ b/main/none/tests/s390x/cdsg.vgtest
@@ -0,0 +1 @@
+prog: cdsg
diff --git a/main/none/tests/s390x/cgij.c b/main/none/tests/s390x/cgij.c
new file mode 100644
index 0000000..962e56e
--- /dev/null
+++ b/main/none/tests/s390x/cgij.c
@@ -0,0 +1,175 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7"
+
+void if_eq(void) { printf("equal\n"); }
+void if_ne(void) { printf("not equal\n"); }
+void if_gt(void) { printf("greater than\n"); }
+void if_le(void) { printf("less or equal\n"); }
+void if_lt(void) { printf("less than\n"); }
+void if_ge(void) { printf("greater or equal\n"); }
+void if_taken(void) { printf("taken\n"); }
+void if_not_taken(void) { printf("not taken\n"); }
+
+#undef LT
+#define NEVER 0
+#define GT 2
+#define LT 4
+#define NE 6
+#define EQ 8
+#define LE C
+#define GE A
+#define ALWAYS E
+
+
+void compare_never(int64_t value)
+{
+ register int64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGIJ(7,NEVER,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_always(int64_t value)
+{
+ register int64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGIJ(7,ALWAYS,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_le42(int64_t value)
+{
+ register int64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGIJ(7,LE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_gt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_le\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ge42(int64_t value)
+{
+ register int64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGIJ(7,GE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_lt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ge\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_gt42(int64_t value)
+{
+ register int64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGIJ(7,GT,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_le\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_gt\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_lt42(int64_t value)
+{
+ register int64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGIJ(7,LT,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_ge\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_lt\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_eq42(int64_t value)
+{
+ register int64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGIJ(7,EQ,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_ne\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_eq\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ne42(int64_t value)
+{
+ register int64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGIJ(7,NE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_eq\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ne\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+int main()
+{
+ compare_eq42(-12);
+ compare_eq42(42);
+ compare_eq42(100);
+
+ compare_ne42(-12);
+ compare_ne42(42);
+ compare_ne42(100);
+
+ compare_gt42(-12);
+ compare_gt42(42);
+ compare_gt42(100);
+
+ compare_lt42(-12);
+ compare_lt42(42);
+ compare_lt42(100);
+
+ compare_le42(-12);
+ compare_le42(42);
+ compare_le42(100);
+
+ compare_ge42(-12);
+ compare_ge42(42);
+ compare_ge42(100);
+
+ compare_never(-12);
+ compare_never(42);
+ compare_never(100);
+
+ compare_always(-12);
+ compare_always(42);
+ compare_always(100);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cgij.stderr.exp b/main/none/tests/s390x/cgij.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cgij.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cgij.stdout.exp b/main/none/tests/s390x/cgij.stdout.exp
new file mode 100644
index 0000000..bd98295
--- /dev/null
+++ b/main/none/tests/s390x/cgij.stdout.exp
@@ -0,0 +1,24 @@
+not equal
+equal
+not equal
+not equal
+equal
+not equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+not taken
+not taken
+not taken
+taken
+taken
+taken
diff --git a/main/none/tests/s390x/cgij.vgtest b/main/none/tests/s390x/cgij.vgtest
new file mode 100644
index 0000000..1a75de9
--- /dev/null
+++ b/main/none/tests/s390x/cgij.vgtest
@@ -0,0 +1 @@
+prog: cgij
diff --git a/main/none/tests/s390x/cgrj.c b/main/none/tests/s390x/cgrj.c
new file mode 100644
index 0000000..f269918
--- /dev/null
+++ b/main/none/tests/s390x/cgrj.c
@@ -0,0 +1,191 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7"
+
+void if_eq(void) { printf("equal\n"); }
+void if_ne(void) { printf("not equal\n"); }
+void if_gt(void) { printf("greater than\n"); }
+void if_le(void) { printf("less or equal\n"); }
+void if_lt(void) { printf("less than\n"); }
+void if_ge(void) { printf("greater or equal\n"); }
+void if_taken(void) { printf("taken\n"); }
+void if_not_taken(void) { printf("not taken\n"); }
+
+#undef LT
+#define NEVER 0
+#define GT 2
+#define LT 4
+#define NE 6
+#define EQ 8
+#define LE C
+#define GE A
+#define ALWAYS E
+
+
+void compare_never(int64_t value1, int64_t value2)
+{
+ register int64_t val1 asm("r7") = value1;
+ register int64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGRJ(7,8,8,NEVER) "\n\t"
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_always(int64_t value1, int64_t value2)
+{
+ register int64_t val1 asm("r7") = value1;
+ register int64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGRJ(7,8,8,ALWAYS) "\n\t"
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_le(int64_t value1, int64_t value2)
+{
+ register int64_t val1 asm("r7") = value1;
+ register int64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGRJ(7,8,8,LE) "\n\t"
+ "brasl 14,if_gt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_le\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ge(int64_t value1, int64_t value2)
+{
+ register int64_t val1 asm("r7") = value1;
+ register int64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGRJ(7,8,8,GE) "\n\t"
+ "brasl 14,if_lt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ge\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_gt(int64_t value1, int64_t value2)
+{
+ register int64_t val1 asm("r7") = value1;
+ register int64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGRJ(7,8,8,GT) "\n\t"
+ "brasl 14,if_le\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_gt\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_lt(int64_t value1, int64_t value2)
+{
+ register int64_t val1 asm("r7") = value1;
+ register int64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGRJ(7,8,8,LT) "\n\t"
+ "brasl 14,if_ge\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_lt\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_eq(int64_t value1, int64_t value2)
+{
+ register int64_t val1 asm("r7") = value1;
+ register int64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGRJ(7,8,8,EQ) "\n\t"
+ "brasl 14,if_ne\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_eq\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ne(int64_t value1, int64_t value2)
+{
+ register int64_t val1 asm("r7") = value1;
+ register int64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CGRJ(7,8,8,NE) "\n\t"
+ "brasl 14,if_eq\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ne\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+int main()
+{
+ compare_eq(-12, 42);
+ compare_eq(42, 42);
+ compare_eq(100, 42);
+
+ compare_ne(-12, 42);
+ compare_ne(42, 42);
+ compare_ne(100, 42);
+
+ compare_gt(-12, 42);
+ compare_gt(42, 42);
+ compare_gt(100, 42);
+
+ compare_lt(-12, 42);
+ compare_lt(42, 42);
+ compare_lt(100, 42);
+
+ compare_le(-12, 42);
+ compare_le(42, 42);
+ compare_le(100, 42);
+
+ compare_ge(-12, 42);
+ compare_ge(42, 42);
+ compare_ge(100, 42);
+
+ compare_never(-12, 42);
+ compare_never(42, 42);
+ compare_never(100, 42);
+
+ compare_always(-12, 42);
+ compare_always(42, 42);
+ compare_always(100, 42);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cgrj.stderr.exp b/main/none/tests/s390x/cgrj.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cgrj.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cgrj.stdout.exp b/main/none/tests/s390x/cgrj.stdout.exp
new file mode 100644
index 0000000..bd98295
--- /dev/null
+++ b/main/none/tests/s390x/cgrj.stdout.exp
@@ -0,0 +1,24 @@
+not equal
+equal
+not equal
+not equal
+equal
+not equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+not taken
+not taken
+not taken
+taken
+taken
+taken
diff --git a/main/none/tests/s390x/cgrj.vgtest b/main/none/tests/s390x/cgrj.vgtest
new file mode 100644
index 0000000..f61e06e
--- /dev/null
+++ b/main/none/tests/s390x/cgrj.vgtest
@@ -0,0 +1 @@
+prog: cgrj
diff --git a/main/none/tests/s390x/cij.c b/main/none/tests/s390x/cij.c
new file mode 100644
index 0000000..4f2913e
--- /dev/null
+++ b/main/none/tests/s390x/cij.c
@@ -0,0 +1,175 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7"
+
+void if_eq(void) { printf("equal\n"); }
+void if_ne(void) { printf("not equal\n"); }
+void if_gt(void) { printf("greater than\n"); }
+void if_le(void) { printf("less or equal\n"); }
+void if_lt(void) { printf("less than\n"); }
+void if_ge(void) { printf("greater or equal\n"); }
+void if_taken(void) { printf("taken\n"); }
+void if_not_taken(void) { printf("not taken\n"); }
+
+#undef LT
+#define NEVER 0
+#define GT 2
+#define LT 4
+#define NE 6
+#define EQ 8
+#define LE C
+#define GE A
+#define ALWAYS E
+
+
+void compare_never(int32_t value)
+{
+ register int32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CIJ(7,NEVER,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_always(int32_t value)
+{
+ register int32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CIJ(7,ALWAYS,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_le42(int32_t value)
+{
+ register int32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CIJ(7,LE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_gt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_le\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ge42(int32_t value)
+{
+ register int32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CIJ(7,GE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_lt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ge\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_gt42(int32_t value)
+{
+ register int32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CIJ(7,GT,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_le\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_gt\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_lt42(int32_t value)
+{
+ register int32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CIJ(7,LT,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_ge\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_lt\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_eq42(int32_t value)
+{
+ register int32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CIJ(7,EQ,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_ne\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_eq\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ne42(int32_t value)
+{
+ register int32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CIJ(7,NE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_eq\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ne\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+int main()
+{
+ compare_eq42(-12);
+ compare_eq42(42);
+ compare_eq42(100);
+
+ compare_ne42(-12);
+ compare_ne42(42);
+ compare_ne42(100);
+
+ compare_gt42(-12);
+ compare_gt42(42);
+ compare_gt42(100);
+
+ compare_lt42(-12);
+ compare_lt42(42);
+ compare_lt42(100);
+
+ compare_le42(-12);
+ compare_le42(42);
+ compare_le42(100);
+
+ compare_ge42(-12);
+ compare_ge42(42);
+ compare_ge42(100);
+
+ compare_never(-12);
+ compare_never(42);
+ compare_never(100);
+
+ compare_always(-12);
+ compare_always(42);
+ compare_always(100);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cij.stderr.exp b/main/none/tests/s390x/cij.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cij.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cij.stdout.exp b/main/none/tests/s390x/cij.stdout.exp
new file mode 100644
index 0000000..bd98295
--- /dev/null
+++ b/main/none/tests/s390x/cij.stdout.exp
@@ -0,0 +1,24 @@
+not equal
+equal
+not equal
+not equal
+equal
+not equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+not taken
+not taken
+not taken
+taken
+taken
+taken
diff --git a/main/none/tests/s390x/cij.vgtest b/main/none/tests/s390x/cij.vgtest
new file mode 100644
index 0000000..959413f
--- /dev/null
+++ b/main/none/tests/s390x/cij.vgtest
@@ -0,0 +1 @@
+prog: cij
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/none/tests/s390x/cksm.stdout.exp
similarity index 100%
rename from main/none/tests/arm/v6int.stdout.exp
rename to main/none/tests/s390x/cksm.stdout.exp
diff --git a/main/none/tests/s390x/clgij.c b/main/none/tests/s390x/clgij.c
new file mode 100644
index 0000000..87d3a3a
--- /dev/null
+++ b/main/none/tests/s390x/clgij.c
@@ -0,0 +1,175 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7"
+
+void if_eq(void) { printf("equal\n"); }
+void if_ne(void) { printf("not equal\n"); }
+void if_gt(void) { printf("greater than\n"); }
+void if_le(void) { printf("less or equal\n"); }
+void if_lt(void) { printf("less than\n"); }
+void if_ge(void) { printf("greater or equal\n"); }
+void if_taken(void) { printf("taken\n"); }
+void if_not_taken(void) { printf("not taken\n"); }
+
+#undef LT
+#define NEVER 0
+#define GT 2
+#define LT 4
+#define NE 6
+#define EQ 8
+#define LE C
+#define GE A
+#define ALWAYS E
+
+
+void compare_never(uint64_t value)
+{
+ register uint64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGIJ(7,NEVER,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_always(uint64_t value)
+{
+ register uint64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGIJ(7,ALWAYS,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_le42(uint64_t value)
+{
+ register uint64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGIJ(7,LE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_gt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_le\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ge42(uint64_t value)
+{
+ register uint64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGIJ(7,GE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_lt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ge\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_gt42(uint64_t value)
+{
+ register uint64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGIJ(7,GT,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_le\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_gt\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_lt42(uint64_t value)
+{
+ register uint64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGIJ(7,LT,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_ge\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_lt\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_eq42(uint64_t value)
+{
+ register uint64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGIJ(7,EQ,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_ne\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_eq\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ne42(uint64_t value)
+{
+ register uint64_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGIJ(7,NE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_eq\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ne\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+int main()
+{
+ compare_eq42(12);
+ compare_eq42(42);
+ compare_eq42(100);
+
+ compare_ne42(12);
+ compare_ne42(42);
+ compare_ne42(100);
+
+ compare_gt42(12);
+ compare_gt42(42);
+ compare_gt42(100);
+
+ compare_lt42(12);
+ compare_lt42(42);
+ compare_lt42(100);
+
+ compare_le42(12);
+ compare_le42(42);
+ compare_le42(100);
+
+ compare_ge42(12);
+ compare_ge42(42);
+ compare_ge42(100);
+
+ compare_never(12);
+ compare_never(42);
+ compare_never(100);
+
+ compare_always(12);
+ compare_always(42);
+ compare_always(100);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/clgij.stderr.exp b/main/none/tests/s390x/clgij.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/clgij.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/clgij.stdout.exp b/main/none/tests/s390x/clgij.stdout.exp
new file mode 100644
index 0000000..bd98295
--- /dev/null
+++ b/main/none/tests/s390x/clgij.stdout.exp
@@ -0,0 +1,24 @@
+not equal
+equal
+not equal
+not equal
+equal
+not equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+not taken
+not taken
+not taken
+taken
+taken
+taken
diff --git a/main/none/tests/s390x/clgij.vgtest b/main/none/tests/s390x/clgij.vgtest
new file mode 100644
index 0000000..b400a6b
--- /dev/null
+++ b/main/none/tests/s390x/clgij.vgtest
@@ -0,0 +1 @@
+prog: clgij
diff --git a/main/none/tests/s390x/clgrj.c b/main/none/tests/s390x/clgrj.c
new file mode 100644
index 0000000..de6b825
--- /dev/null
+++ b/main/none/tests/s390x/clgrj.c
@@ -0,0 +1,191 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7"
+
+void if_eq(void) { printf("equal\n"); }
+void if_ne(void) { printf("not equal\n"); }
+void if_gt(void) { printf("greater than\n"); }
+void if_le(void) { printf("less or equal\n"); }
+void if_lt(void) { printf("less than\n"); }
+void if_ge(void) { printf("greater or equal\n"); }
+void if_taken(void) { printf("taken\n"); }
+void if_not_taken(void) { printf("not taken\n"); }
+
+#undef LT
+#define NEVER 0
+#define GT 2
+#define LT 4
+#define NE 6
+#define EQ 8
+#define LE C
+#define GE A
+#define ALWAYS E
+
+
+void compare_never(uint64_t value1, uint64_t value2)
+{
+ register uint64_t val1 asm("r7") = value1;
+ register uint64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGRJ(7,8,8,NEVER) "\n\t"
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_always(uint64_t value1, uint64_t value2)
+{
+ register uint64_t val1 asm("r7") = value1;
+ register uint64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGRJ(7,8,8,ALWAYS) "\n\t"
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_le(uint64_t value1, uint64_t value2)
+{
+ register uint64_t val1 asm("r7") = value1;
+ register uint64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGRJ(7,8,8,LE) "\n\t"
+ "brasl 14,if_gt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_le\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ge(uint64_t value1, uint64_t value2)
+{
+ register uint64_t val1 asm("r7") = value1;
+ register uint64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGRJ(7,8,8,GE) "\n\t"
+ "brasl 14,if_lt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ge\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_gt(uint64_t value1, uint64_t value2)
+{
+ register uint64_t val1 asm("r7") = value1;
+ register uint64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGRJ(7,8,8,GT) "\n\t"
+ "brasl 14,if_le\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_gt\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_lt(uint64_t value1, uint64_t value2)
+{
+ register uint64_t val1 asm("r7") = value1;
+ register uint64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGRJ(7,8,8,LT) "\n\t"
+ "brasl 14,if_ge\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_lt\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_eq(uint64_t value1, uint64_t value2)
+{
+ register uint64_t val1 asm("r7") = value1;
+ register uint64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGRJ(7,8,8,EQ) "\n\t"
+ "brasl 14,if_ne\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_eq\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ne(uint64_t value1, uint64_t value2)
+{
+ register uint64_t val1 asm("r7") = value1;
+ register uint64_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLGRJ(7,8,8,NE) "\n\t"
+ "brasl 14,if_eq\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ne\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+int main()
+{
+ compare_eq(12, 42);
+ compare_eq(42, 42);
+ compare_eq(100, 42);
+
+ compare_ne(12, 42);
+ compare_ne(42, 42);
+ compare_ne(100, 42);
+
+ compare_gt(12, 42);
+ compare_gt(42, 42);
+ compare_gt(100, 42);
+
+ compare_lt(12, 42);
+ compare_lt(42, 42);
+ compare_lt(100, 42);
+
+ compare_le(12, 42);
+ compare_le(42, 42);
+ compare_le(100, 42);
+
+ compare_ge(12, 42);
+ compare_ge(42, 42);
+ compare_ge(100, 42);
+
+ compare_never(12, 42);
+ compare_never(42, 42);
+ compare_never(100, 42);
+
+ compare_always(12, 42);
+ compare_always(42, 42);
+ compare_always(100, 42);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/clgrj.stderr.exp b/main/none/tests/s390x/clgrj.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/clgrj.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/clgrj.stdout.exp b/main/none/tests/s390x/clgrj.stdout.exp
new file mode 100644
index 0000000..bd98295
--- /dev/null
+++ b/main/none/tests/s390x/clgrj.stdout.exp
@@ -0,0 +1,24 @@
+not equal
+equal
+not equal
+not equal
+equal
+not equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+not taken
+not taken
+not taken
+taken
+taken
+taken
diff --git a/main/none/tests/s390x/clgrj.vgtest b/main/none/tests/s390x/clgrj.vgtest
new file mode 100644
index 0000000..b0dedcc
--- /dev/null
+++ b/main/none/tests/s390x/clgrj.vgtest
@@ -0,0 +1 @@
+prog: clgrj
diff --git a/main/none/tests/s390x/clij.c b/main/none/tests/s390x/clij.c
new file mode 100644
index 0000000..3b62e1c
--- /dev/null
+++ b/main/none/tests/s390x/clij.c
@@ -0,0 +1,175 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7"
+
+void if_eq(void) { printf("equal\n"); }
+void if_ne(void) { printf("not equal\n"); }
+void if_gt(void) { printf("greater than\n"); }
+void if_le(void) { printf("less or equal\n"); }
+void if_lt(void) { printf("less than\n"); }
+void if_ge(void) { printf("greater or equal\n"); }
+void if_taken(void) { printf("taken\n"); }
+void if_not_taken(void) { printf("not taken\n"); }
+
+#undef LT
+#define NEVER 0
+#define GT 2
+#define LT 4
+#define NE 6
+#define EQ 8
+#define LE C
+#define GE A
+#define ALWAYS E
+
+
+void compare_never(uint32_t value)
+{
+ register uint32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLIJ(7,NEVER,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_always(uint32_t value)
+{
+ register uint32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLIJ(7,ALWAYS,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_le42(uint32_t value)
+{
+ register uint32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLIJ(7,LE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_gt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_le\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ge42(uint32_t value)
+{
+ register uint32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLIJ(7,GE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_lt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ge\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_gt42(uint32_t value)
+{
+ register uint32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLIJ(7,GT,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_le\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_gt\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_lt42(uint32_t value)
+{
+ register uint32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLIJ(7,LT,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_ge\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_lt\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_eq42(uint32_t value)
+{
+ register uint32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLIJ(7,EQ,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_ne\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_eq\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ne42(uint32_t value)
+{
+ register uint32_t val asm("r7") = value;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLIJ(7,NE,8,2a) "\n\t" /* 0x2a == 42 */
+ "brasl 14,if_eq\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ne\n\t"
+ "0: aghi 15,160\n\t" : : "d"(val) : "15", BRASLCLOBBER);
+ return;
+}
+
+int main()
+{
+ compare_eq42(12);
+ compare_eq42(42);
+ compare_eq42(100);
+
+ compare_ne42(12);
+ compare_ne42(42);
+ compare_ne42(100);
+
+ compare_gt42(12);
+ compare_gt42(42);
+ compare_gt42(100);
+
+ compare_lt42(12);
+ compare_lt42(42);
+ compare_lt42(100);
+
+ compare_le42(12);
+ compare_le42(42);
+ compare_le42(100);
+
+ compare_ge42(12);
+ compare_ge42(42);
+ compare_ge42(100);
+
+ compare_never(12);
+ compare_never(42);
+ compare_never(100);
+
+ compare_always(12);
+ compare_always(42);
+ compare_always(100);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/clij.stderr.exp b/main/none/tests/s390x/clij.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/clij.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/clij.stdout.exp b/main/none/tests/s390x/clij.stdout.exp
new file mode 100644
index 0000000..bd98295
--- /dev/null
+++ b/main/none/tests/s390x/clij.stdout.exp
@@ -0,0 +1,24 @@
+not equal
+equal
+not equal
+not equal
+equal
+not equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+not taken
+not taken
+not taken
+taken
+taken
+taken
diff --git a/main/none/tests/s390x/clij.vgtest b/main/none/tests/s390x/clij.vgtest
new file mode 100644
index 0000000..2cc05ad
--- /dev/null
+++ b/main/none/tests/s390x/clij.vgtest
@@ -0,0 +1 @@
+prog: clij
diff --git a/main/none/tests/s390x/clrj.c b/main/none/tests/s390x/clrj.c
new file mode 100644
index 0000000..4e3454f
--- /dev/null
+++ b/main/none/tests/s390x/clrj.c
@@ -0,0 +1,191 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7"
+
+void if_eq(void) { printf("equal\n"); }
+void if_ne(void) { printf("not equal\n"); }
+void if_gt(void) { printf("greater than\n"); }
+void if_le(void) { printf("less or equal\n"); }
+void if_lt(void) { printf("less than\n"); }
+void if_ge(void) { printf("greater or equal\n"); }
+void if_taken(void) { printf("taken\n"); }
+void if_not_taken(void) { printf("not taken\n"); }
+
+#undef LT
+#define NEVER 0
+#define GT 2
+#define LT 4
+#define NE 6
+#define EQ 8
+#define LE C
+#define GE A
+#define ALWAYS E
+
+
+void compare_never(uint32_t value1, uint32_t value2)
+{
+ register uint32_t val1 asm("r7") = value1;
+ register uint32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLRJ(7,8,8,NEVER) "\n\t"
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_always(uint32_t value1, uint32_t value2)
+{
+ register uint32_t val1 asm("r7") = value1;
+ register uint32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLRJ(7,8,8,ALWAYS) "\n\t"
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_le(uint32_t value1, uint32_t value2)
+{
+ register uint32_t val1 asm("r7") = value1;
+ register uint32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLRJ(7,8,8,LE) "\n\t"
+ "brasl 14,if_gt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_le\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ge(uint32_t value1, uint32_t value2)
+{
+ register uint32_t val1 asm("r7") = value1;
+ register uint32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLRJ(7,8,8,GE) "\n\t"
+ "brasl 14,if_lt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ge\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_gt(uint32_t value1, uint32_t value2)
+{
+ register uint32_t val1 asm("r7") = value1;
+ register uint32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLRJ(7,8,8,GT) "\n\t"
+ "brasl 14,if_le\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_gt\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_lt(uint32_t value1, uint32_t value2)
+{
+ register uint32_t val1 asm("r7") = value1;
+ register uint32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLRJ(7,8,8,LT) "\n\t"
+ "brasl 14,if_ge\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_lt\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_eq(uint32_t value1, uint32_t value2)
+{
+ register uint32_t val1 asm("r7") = value1;
+ register uint32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLRJ(7,8,8,EQ) "\n\t"
+ "brasl 14,if_ne\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_eq\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ne(uint32_t value1, uint32_t value2)
+{
+ register uint32_t val1 asm("r7") = value1;
+ register uint32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CLRJ(7,8,8,NE) "\n\t"
+ "brasl 14,if_eq\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ne\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+int main()
+{
+ compare_eq(12, 42);
+ compare_eq(42, 42);
+ compare_eq(100, 42);
+
+ compare_ne(12, 42);
+ compare_ne(42, 42);
+ compare_ne(100, 42);
+
+ compare_gt(12, 42);
+ compare_gt(42, 42);
+ compare_gt(100, 42);
+
+ compare_lt(12, 42);
+ compare_lt(42, 42);
+ compare_lt(100, 42);
+
+ compare_le(12, 42);
+ compare_le(42, 42);
+ compare_le(100, 42);
+
+ compare_ge(12, 42);
+ compare_ge(42, 42);
+ compare_ge(100, 42);
+
+ compare_never(12, 42);
+ compare_never(42, 42);
+ compare_never(100, 42);
+
+ compare_always(12, 42);
+ compare_always(42, 42);
+ compare_always(100, 42);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/clrj.stderr.exp b/main/none/tests/s390x/clrj.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/clrj.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/clrj.stdout.exp b/main/none/tests/s390x/clrj.stdout.exp
new file mode 100644
index 0000000..bd98295
--- /dev/null
+++ b/main/none/tests/s390x/clrj.stdout.exp
@@ -0,0 +1,24 @@
+not equal
+equal
+not equal
+not equal
+equal
+not equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+not taken
+not taken
+not taken
+taken
+taken
+taken
diff --git a/main/none/tests/s390x/clrj.vgtest b/main/none/tests/s390x/clrj.vgtest
new file mode 100644
index 0000000..75fcf1b
--- /dev/null
+++ b/main/none/tests/s390x/clrj.vgtest
@@ -0,0 +1 @@
+prog: clrj
diff --git a/main/none/tests/s390x/condloadstore.vgtest b/main/none/tests/s390x/condloadstore.vgtest
index be500e9..4291811 100644
--- a/main/none/tests/s390x/condloadstore.vgtest
+++ b/main/none/tests/s390x/condloadstore.vgtest
@@ -1,2 +1 @@
prog: condloadstore
-prereq: test -x condloadstore
diff --git a/main/none/tests/s390x/crj.c b/main/none/tests/s390x/crj.c
new file mode 100644
index 0000000..936b70c
--- /dev/null
+++ b/main/none/tests/s390x/crj.c
@@ -0,0 +1,191 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7"
+
+void if_eq(void) { printf("equal\n"); }
+void if_ne(void) { printf("not equal\n"); }
+void if_gt(void) { printf("greater than\n"); }
+void if_le(void) { printf("less or equal\n"); }
+void if_lt(void) { printf("less than\n"); }
+void if_ge(void) { printf("greater or equal\n"); }
+void if_taken(void) { printf("taken\n"); }
+void if_not_taken(void) { printf("not taken\n"); }
+
+#undef LT
+#define NEVER 0
+#define GT 2
+#define LT 4
+#define NE 6
+#define EQ 8
+#define LE C
+#define GE A
+#define ALWAYS E
+
+
+void compare_never(int32_t value1, int32_t value2)
+{
+ register int32_t val1 asm("r7") = value1;
+ register int32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CRJ(7,8,8,NEVER) "\n\t"
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_always(int32_t value1, int32_t value2)
+{
+ register int32_t val1 asm("r7") = value1;
+ register int32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CRJ(7,8,8,ALWAYS) "\n\t"
+ "brasl 14,if_not_taken\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_taken\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_le(int32_t value1, int32_t value2)
+{
+ register int32_t val1 asm("r7") = value1;
+ register int32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CRJ(7,8,8,LE) "\n\t"
+ "brasl 14,if_gt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_le\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ge(int32_t value1, int32_t value2)
+{
+ register int32_t val1 asm("r7") = value1;
+ register int32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CRJ(7,8,8,GE) "\n\t"
+ "brasl 14,if_lt\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ge\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_gt(int32_t value1, int32_t value2)
+{
+ register int32_t val1 asm("r7") = value1;
+ register int32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CRJ(7,8,8,GT) "\n\t"
+ "brasl 14,if_le\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_gt\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_lt(int32_t value1, int32_t value2)
+{
+ register int32_t val1 asm("r7") = value1;
+ register int32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CRJ(7,8,8,LT) "\n\t"
+ "brasl 14,if_ge\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_lt\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_eq(int32_t value1, int32_t value2)
+{
+ register int32_t val1 asm("r7") = value1;
+ register int32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CRJ(7,8,8,EQ) "\n\t"
+ "brasl 14,if_ne\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_eq\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+void compare_ne(int32_t value1, int32_t value2)
+{
+ register int32_t val1 asm("r7") = value1;
+ register int32_t val2 asm("r8") = value2;
+
+ asm volatile(
+ "aghi 15,-160\n\t"
+ CRJ(7,8,8,NE) "\n\t"
+ "brasl 14,if_eq\n\t"
+ "j 0f\n\t"
+ "brasl 14,if_ne\n\t"
+ "0: aghi 15,160\n\t"
+ : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER);
+ return;
+}
+
+int main()
+{
+ compare_eq(-12, 42);
+ compare_eq(42, 42);
+ compare_eq(100, 42);
+
+ compare_ne(-12, 42);
+ compare_ne(42, 42);
+ compare_ne(100, 42);
+
+ compare_gt(-12, 42);
+ compare_gt(42, 42);
+ compare_gt(100, 42);
+
+ compare_lt(-12, 42);
+ compare_lt(42, 42);
+ compare_lt(100, 42);
+
+ compare_le(-12, 42);
+ compare_le(42, 42);
+ compare_le(100, 42);
+
+ compare_ge(-12, 42);
+ compare_ge(42, 42);
+ compare_ge(100, 42);
+
+ compare_never(-12, 42);
+ compare_never(42, 42);
+ compare_never(100, 42);
+
+ compare_always(-12, 42);
+ compare_always(42, 42);
+ compare_always(100, 42);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/crj.stderr.exp b/main/none/tests/s390x/crj.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/crj.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/crj.stdout.exp b/main/none/tests/s390x/crj.stdout.exp
new file mode 100644
index 0000000..bd98295
--- /dev/null
+++ b/main/none/tests/s390x/crj.stdout.exp
@@ -0,0 +1,24 @@
+not equal
+equal
+not equal
+not equal
+equal
+not equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+less or equal
+less or equal
+greater than
+less than
+greater or equal
+greater or equal
+not taken
+not taken
+not taken
+taken
+taken
+taken
diff --git a/main/none/tests/s390x/crj.vgtest b/main/none/tests/s390x/crj.vgtest
new file mode 100644
index 0000000..1e1bba6
--- /dev/null
+++ b/main/none/tests/s390x/crj.vgtest
@@ -0,0 +1 @@
+prog: crj
diff --git a/main/none/tests/s390x/cs.c b/main/none/tests/s390x/cs.c
new file mode 100644
index 0000000..ab1021d
--- /dev/null
+++ b/main/none/tests/s390x/cs.c
@@ -0,0 +1,51 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+void
+test(int32_t op1_init, int32_t op2_init, int32_t op3_init, int expected_cc)
+{
+ register int32_t op1 asm("8") = op1_init;
+ register int32_t op3 asm("9") = op3_init;
+
+ int32_t op2 = op2_init;
+ int cc = 1 - expected_cc;
+
+ printf("before op1 = %#x\n", op1);
+ printf("before op2 = %#x\n", op2);
+ printf("before op3 = %#x\n", op3);
+
+ __asm__ volatile (
+ "cs 8,9,%1\n\t"
+ "ipm %0\n\t"
+ "srl %0,28\n\t"
+ : "=d" (cc), "+Q" (op2), "+d"(op1), "+d"(op3)
+ :
+ : "cc");
+
+ printf("after op1 = %#x\n", op1);
+ printf("after op2 = %#x\n", op2);
+ printf("after op3 = %#x\n", op3);
+ printf("cc = %d\n", cc);
+
+ if (cc != expected_cc) {
+ printf("condition code is incorrect\n");
+ }
+ if (expected_cc == 0) {
+ if (op2 != op3) {
+ printf("operand #2 not updated\n");
+ }
+ } else {
+ if (op1 != op2) {
+ printf("operand #1 not updated\n");
+ }
+ }
+}
+
+int main ()
+{
+ test(0x10000000, 0x10000000, 0x12345678, 0);
+ test(0x10000000, 0x20000000, 0x12345678, 1);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cs.stderr.exp b/main/none/tests/s390x/cs.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cs.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cs.stdout.exp b/main/none/tests/s390x/cs.stdout.exp
new file mode 100644
index 0000000..803a8b3
--- /dev/null
+++ b/main/none/tests/s390x/cs.stdout.exp
@@ -0,0 +1,14 @@
+before op1 = 0x10000000
+before op2 = 0x10000000
+before op3 = 0x12345678
+after op1 = 0x10000000
+after op2 = 0x12345678
+after op3 = 0x12345678
+cc = 0
+before op1 = 0x10000000
+before op2 = 0x20000000
+before op3 = 0x12345678
+after op1 = 0x20000000
+after op2 = 0x20000000
+after op3 = 0x12345678
+cc = 1
diff --git a/main/none/tests/s390x/cs.vgtest b/main/none/tests/s390x/cs.vgtest
new file mode 100644
index 0000000..9d9bdd9
--- /dev/null
+++ b/main/none/tests/s390x/cs.vgtest
@@ -0,0 +1 @@
+prog: cs
diff --git a/main/none/tests/s390x/csg.c b/main/none/tests/s390x/csg.c
new file mode 100644
index 0000000..398c461
--- /dev/null
+++ b/main/none/tests/s390x/csg.c
@@ -0,0 +1,51 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+void
+test(int64_t op1_init, int64_t op2_init, int64_t op3_init, int expected_cc)
+{
+ register int64_t op1 asm("8") = op1_init;
+ register int64_t op3 asm("9") = op3_init;
+
+ int64_t op2 = op2_init;
+ int cc = 1 - expected_cc;
+
+ printf("before op1 = %#lx\n", op1);
+ printf("before op2 = %#lx\n", op2);
+ printf("before op3 = %#lx\n", op3);
+
+ __asm__ volatile (
+ "csg 8,9,%1\n\t"
+ "ipm %0\n\t"
+ "srl %0,28\n\t"
+ : "=d" (cc), "+Q" (op2), "+d"(op1), "+d"(op3)
+ :
+ : "cc");
+
+ printf("after op1 = %#lx\n", op1);
+ printf("after op2 = %#lx\n", op2);
+ printf("after op3 = %#lx\n", op3);
+ printf("cc = %d\n", cc);
+
+ if (cc != expected_cc) {
+ printf("condition code is incorrect\n");
+ }
+ if (expected_cc == 0) {
+ if (op2 != op3) {
+ printf("operand #2 not updated\n");
+ }
+ } else {
+ if (op1 != op2) {
+ printf("operand #1 not updated\n");
+ }
+ }
+}
+
+int main ()
+{
+ test(0x1000000000000000ull, 0x1000000000000000ull, 0x1234567887654321ull, 0);
+ test(0x1000000000000000ull, 0x2000000000000000ull, 0x1234567887654321ull, 1);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/csg.stderr.exp b/main/none/tests/s390x/csg.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/csg.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/csg.stdout.exp b/main/none/tests/s390x/csg.stdout.exp
new file mode 100644
index 0000000..1258ece
--- /dev/null
+++ b/main/none/tests/s390x/csg.stdout.exp
@@ -0,0 +1,14 @@
+before op1 = 0x1000000000000000
+before op2 = 0x1000000000000000
+before op3 = 0x1234567887654321
+after op1 = 0x1000000000000000
+after op2 = 0x1234567887654321
+after op3 = 0x1234567887654321
+cc = 0
+before op1 = 0x1000000000000000
+before op2 = 0x2000000000000000
+before op3 = 0x1234567887654321
+after op1 = 0x2000000000000000
+after op2 = 0x2000000000000000
+after op3 = 0x1234567887654321
+cc = 1
diff --git a/main/none/tests/s390x/csg.vgtest b/main/none/tests/s390x/csg.vgtest
new file mode 100644
index 0000000..c765a1b
--- /dev/null
+++ b/main/none/tests/s390x/csg.vgtest
@@ -0,0 +1 @@
+prog: csg
diff --git a/main/none/tests/s390x/cu12.c b/main/none/tests/s390x/cu12.c
new file mode 100644
index 0000000..1281118
--- /dev/null
+++ b/main/none/tests/s390x/cu12.c
@@ -0,0 +1,595 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU12 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu12_t;
+
+/* Define various input buffers. */
+
+/* 1-byte UTF-8 character */
+uint8_t pattern1[] = {
+ 0x00, 0x01, 0x02, 0x03
+};
+
+/* 2-byte UTF-8 character */
+uint8_t pattern2[] = {
+ 0xc2, 0x80,
+ 0xc2, 0x81,
+ 0xc2, 0x82,
+ 0xc2, 0x83,
+};
+
+/* 3-byte UTF-8 character */
+uint8_t pattern3[] = {
+ 0xe1, 0x80, 0x80,
+ 0xe1, 0x80, 0x81,
+ 0xe1, 0x80, 0x82,
+ 0xe1, 0x80, 0x83,
+};
+
+/* 4-byte UTF-8 character */
+uint8_t pattern4[] = {
+ 0xf4, 0x80, 0x80, 0x80,
+ 0xf4, 0x80, 0x80, 0x81,
+ 0xf4, 0x80, 0x80, 0x82,
+ 0xf4, 0x80, 0x80, 0x83,
+};
+
+
+/* Mixed bytes */
+uint8_t mixed[] = {
+ 0x01, // 1 byte
+ 0xc3, 0x80, // 2 bytes
+ 0x12, // 1 byte
+ 0xe1, 0x90, 0x93, // 3 bytes
+ 0x23, // 1 byte
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0x34, // 1 byte
+ 0xc4, 0x8c, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+};
+
+/* This is the buffer for the converted bytes. */
+uint16_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+
+static cu12_t
+do_cu12(uint16_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu12_t regs;
+
+ /* build up the register pairs */
+ register uint8_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint16_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU12(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu12 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint16_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int i;
+ cu12_t result;
+
+ printf("UTF8: ");
+ if (src_len == 0)
+ printf(" <none>");
+ else {
+ for(i = 0; i < src_len; ++i)
+ printf(" %02x", src[i]);
+ }
+ printf("\n");
+
+ result = do_cu12(dst, dst_len, src, src_len);
+
+ // Write out the converted byte, if any
+ printf("UTF16: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else {
+ uint64_t num_bytes = dst_len - result.len1;
+
+ /* The number of bytes that were written must be divisible by 2 */
+ if (num_bytes % 2 != 0)
+ fprintf(stderr, "*** number of bytes is not a multiple of 2\n");
+
+ for (i = 0; i < num_bytes / 2; i++) {
+ printf(" %04x", dst[i]);
+ }
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+// Test conversion of a one-byte character
+void convert_1_byte(void)
+{
+ int i;
+
+ printf("===== Conversion of a one-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0x00, 0x7f, // corner cases
+ 0x01, 0x10, 0x7e, 0x5d // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters -----\n");
+ uint8_t always_invalid[] = {
+ 0x80, 0xbf, // corner cases
+ 0xf8, 0xff, // corner cases
+ 0x81, 0xbe, 0x95, 0xab // misc
+ };
+ for (i = 0; i < sizeof always_invalid; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = always_invalid[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ // In case of m3 == 0 we get cc=0 indicating exhaustion of source
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t invalid_if_m3[] = { // contains all such invalid characters
+ 0xc0, 0xc1,
+ 0xf5, 0xf6, 0xf7
+ };
+ for (i = 0; i < sizeof invalid_if_m3; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = invalid_if_m3[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0x10, // valid
+ 0xaa // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a two-byte character
+void convert_2_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a two-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0xc2, 0x80, // corner case
+ 0xc2, 0xbf, // corner case
+ 0xdf, 0x80, // corner case
+ 0xdf, 0xbf, // corner case
+ 0xc3, 0xbe, 0xda, 0xbc // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xc0 or 0xc1
+ uint8_t valid_if_not_m3[] = {
+ 0xc0, 0x80,
+ 0xc0, 0xbf,
+ 0xc1, 0x80,
+ 0xc0, 0xbf
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // Test for invalid two-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid if not in range 0x80..0xbf, inclusive
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t always_invalid[] = {
+ 0xc2, 0x00,
+ 0xc2, 0x7f,
+ 0xc2, 0xc0,
+ 0xc2, 0xff
+ };
+ for (i = 0; i < sizeof always_invalid; i += 2) {
+ uint8_t invalid_char[2];
+ invalid_char[0] = always_invalid[i];
+ invalid_char[1] = always_invalid[i+1];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ /* Nb: for a two-byte character we need not test the case where
+ invalidity of the character (cc=2) takes precedence over exhaustion
+ of the 1st operand (cc=1). Invalidity of the character has already
+ been tested when testing the 1st byte. */
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xc3, 0x81, // valid
+ 0xc4, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a three-byte character
+void
+convert_3_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a three-byte character =====\n");
+
+ /* Exhaustively test the 1st byte E0 - EF, and the interval boundaries for
+ the 2nd and 3rd bytes */
+ printf("\n----- Valid characters -----\n");
+ uint8_t e0[] = {
+ 0xe0, 0xa0, 0x80,
+ 0xe0, 0xbf, 0x80,
+ 0xe0, 0xa0, 0xbf,
+ 0xe0, 0xbf, 0xbf,
+ 0xe0, 0xaa, 0xbb, // random e0 .. ..
+ };
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ uint8_t ed[] = {
+ 0xed, 0x80, 0x80,
+ 0xed, 0x9f, 0x80,
+ 0xed, 0x80, 0xbf,
+ 0xed, 0x9f, 0xbf,
+ 0xed, 0x8a, 0xbb, // random ed .. ..
+ };
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x80, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xbf, 0x80 };
+ uint8_t exxx_3[3] = { 0x0, 0x80, 0xbf };
+ uint8_t exxx_4[3] = { 0x0, 0xbf, 0xbf };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ exxx_3[0] = 0xe0 | i;
+ exxx_4[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ run_test(buff, sizeof buff, exxx_3, sizeof exxx_3);
+ run_test(buff, sizeof buff, exxx_4, sizeof exxx_4);
+ };
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid three-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid.
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ e0[0] = 0xe0; // valid
+ e0[1] = 0x9f; // invalid because outside [0xa0 .. 0xbf]
+ e0[2] = 0x80; // valid
+ run_test(buff, sizeof buff, e0, sizeof e0);
+ e0[1] = 0xc0; // invalid because outside [0xa0 .. 0xbf]
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ ed[0] = 0xed; // valid
+ ed[1] = 0x7f; // invalid because outside [0x80 .. 0x9f]
+ ed[2] = 0x80; // valid
+ run_test(buff, sizeof buff, ed, sizeof ed);
+ ed[1] = 0xa0; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x7f, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xc0, 0x80 };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // For all 1st bytes 0xe0 .. 0xef the 3rd bytes must be in [0x80 .. 0xbf]
+ // No need to special case 0xe0 and 0xed
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0xab, 0x7f };
+ uint8_t exxx_2[3] = { 0x0, 0xab, 0xc0 };
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xe0, 0x00, 0x80
+ };
+ run_test(buff, 1, pat1, 3);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xe4, 0x84, 0x00
+ };
+ run_test(buff, 1, pat2, 3);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xe1, 0x90, 0x90, // valid
+ 0xe1, 0x00, 0x90 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a four-byte character
+void
+convert_4_bytes(void)
+{
+ int i, j;
+
+ printf("\n===== Conversion of a four-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ for (i = 0; i <= 4; ++i) {
+ uint8_t valid[4];
+
+ valid[0] = 0xf0 | i;
+
+ for (j = 0; j <= 1; ++j) {
+ // Byte 2
+ if (i == 0) {
+ valid[1] = j == 0 ? 0x90 : 0xbf; // 0xf0
+ } else if (i == 4) {
+ valid[1] = j == 0 ? 0x80 : 0x8f; // 0xf4
+ } else {
+ valid[1] = j == 0 ? 0x80 : 0xbf; // 0xf1 .. 0xf3
+ }
+ // Byte 3 and byte 4 have same interval 0x80 .. 0xbf
+ valid[2] = 0x80;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0x80;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ }
+ }
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xf5 .. 0xf7
+ uint8_t valid_if_not_m3[] = {
+ 0xf5, 0x00, 0x00, 0x00,
+ 0xf6, 0x11, 0x22, 0x33,
+ 0xf7, 0x44, 0x55, 0x66,
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 2nd byte is invalid.
+ // All other bytes are valid
+ uint8_t f0[4], f4[4];
+
+ f0[0] = 0xf0; // valid
+ f0[1] = 0x8f; // invalid because outside [0x90 .. 0xbf]
+ f0[2] = 0x80; // valid
+ f0[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f0, sizeof f0);
+ f0[1] = 0xc0; // invalid because outside [0x90 .. 0xbf]
+ run_test(buff, sizeof buff, f0, sizeof f0);
+
+ f4[0] = 0xf4; // valid
+ f4[1] = 0x7f; // invalid because outside [0x80 .. 0x8f]
+ f4[2] = 0x80; // valid
+ f4[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f4, sizeof f4);
+ f4[1] = 0x90; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, f4, sizeof f4);
+
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx_1[4] = { 0x0, 0x7f, 0x80, 0x80 };
+ uint8_t fxxx_2[4] = { 0x0, 0xc0, 0x80, 0x80 };
+
+ if (i == 0) continue; // special case f0
+ if (i == 4) continue; // special case f4
+
+ fxxx_1[0] = 0xf0 | i;
+ fxxx_2[0] = 0xf0 | i;
+ run_test(buff, sizeof buff, fxxx_1, sizeof fxxx_1);
+ run_test(buff, sizeof buff, fxxx_2, sizeof fxxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x0, 0x80 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[2] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[2] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid characters (4th byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x80, 0x0 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[3] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[3] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xf0, 0x00, 0x80, 0x80
+ };
+ run_test(buff, 1, pat1, 4);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xf0, 0xaa, 0x00, 0x80
+ };
+ run_test(buff, 3, pat2, 4);
+
+ printf("\n----- Invalid 4th char AND output exhausted -----\n");
+ /* The character is invalid in its 4th byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat3[] = {
+ 0xf0, 0xaa, 0xaa, 0x00
+ };
+ run_test(buff, 3, pat3, 4);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xf0, 0xaa, 0xaa, 0xaa, // valid
+ 0xf0, 0x00, 0x00, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+
+int main()
+{
+ convert_1_byte();
+ convert_2_bytes();
+ convert_3_bytes();
+ convert_4_bytes();
+
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 0);
+ run_test(buff, sizeof buff, pattern1, 0);
+ run_test(buff, sizeof buff, pattern2, 0);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern3, 0);
+ run_test(buff, sizeof buff, pattern3, 1);
+ run_test(buff, sizeof buff, pattern3, 2);
+ run_test(buff, sizeof buff, pattern4, 0);
+ run_test(buff, sizeof buff, pattern4, 1);
+ run_test(buff, sizeof buff, pattern4, 2);
+ run_test(buff, sizeof buff, pattern4, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 2);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern3, 6);
+ run_test(buff, sizeof buff, pattern4, 9);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write 2 or 4 bytes at a time */
+ run_test(NULL, 0, pattern1, sizeof pattern1); // 2-byte result
+ run_test(NULL, 0, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 1, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 0, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 1, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 0, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 1, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 2, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 3, pattern4, sizeof pattern4); // 4-byte result
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 4, pattern1, sizeof pattern1);
+ run_test(buff, 5, pattern1, sizeof pattern2);
+ run_test(buff, 6, pattern1, sizeof pattern3);
+ run_test(buff, 7, pattern1, sizeof pattern4);
+
+ /* Convert buffer with mixed characters */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cu12.stderr.exp b/main/none/tests/s390x/cu12.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu12.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu12.stdout.exp b/main/none/tests/s390x/cu12.stdout.exp
new file mode 100644
index 0000000..59c5dc9
--- /dev/null
+++ b/main/none/tests/s390x/cu12.stdout.exp
@@ -0,0 +1,1325 @@
+===== Conversion of a one-byte character =====
+
+----- Valid characters -----
+UTF8: 00 7f 01 10 7e 5d
+UTF16: 0000 007f 0001 0010 007e 005d
+ cc = 0
+ dst address difference: 12 dst len: 1988
+ src address difference: 6 src len: 0
+
+----- Invalid characters -----
+UTF8: 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: bf
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f8
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: ff
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: 81
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: be
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: 95
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: ab
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+
+----- Invalid characters if m3 == 1 -----
+UTF8: c0
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: c1
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f5
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f6
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f7
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: 10 aa
+UTF16: 0010
+ cc = 2
+ dst address difference: 2 dst len: 1998
+ src address difference: 1 src len: 1
+
+===== Conversion of a two-byte character =====
+
+----- Valid characters -----
+UTF8: c2 80 c2 bf df 80 df bf c3 be da bc
+UTF16: 0080 00bf 07c0 07ff 00fe 06bc
+ cc = 0
+ dst address difference: 12 dst len: 1988
+ src address difference: 12 src len: 0
+
+----- Valid characters if m3 == 0 -----
+UTF8: c0 80 c0 bf c1 80 c0 bf
+UTF16: 0000 003f 0040 003f
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 8 src len: 0
+
+----- Invalid characters if m3 == 1 -----
+UTF8: c2 00
+UTF16: 0080
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 2 src len: 0
+UTF8: c2 7f
+UTF16: 00bf
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 2 src len: 0
+UTF8: c2 c0
+UTF16: 0080
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 2 src len: 0
+UTF8: c2 ff
+UTF16: 00bf
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 2 src len: 0
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: c3 81 c4 00
+UTF16: 00c1 0100
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+===== Conversion of a three-byte character =====
+
+----- Valid characters -----
+UTF8: e0 a0 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF16: 0800 0fc0 083f 0fff 0abb
+ cc = 0
+ dst address difference: 10 dst len: 1990
+ src address difference: 15 src len: 0
+UTF8: ed 80 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF16: d000 d7c0 d03f d7ff d2bb
+ cc = 0
+ dst address difference: 10 dst len: 1990
+ src address difference: 15 src len: 0
+UTF8: e1 80 80
+UTF16: 1000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e1 bf 80
+UTF16: 1fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e1 80 bf
+UTF16: 103f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e1 bf bf
+UTF16: 1fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 80 80
+UTF16: 2000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 bf 80
+UTF16: 2fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 80 bf
+UTF16: 203f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 bf bf
+UTF16: 2fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 80 80
+UTF16: 3000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 bf 80
+UTF16: 3fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 80 bf
+UTF16: 303f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 bf bf
+UTF16: 3fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 80 80
+UTF16: 4000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 bf 80
+UTF16: 4fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 80 bf
+UTF16: 403f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 bf bf
+UTF16: 4fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 80 80
+UTF16: 5000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 bf 80
+UTF16: 5fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 80 bf
+UTF16: 503f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 bf bf
+UTF16: 5fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 80 80
+UTF16: 6000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 bf 80
+UTF16: 6fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 80 bf
+UTF16: 603f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 bf bf
+UTF16: 6fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 80 80
+UTF16: 7000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 bf 80
+UTF16: 7fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 80 bf
+UTF16: 703f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 bf bf
+UTF16: 7fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 80 80
+UTF16: 8000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 bf 80
+UTF16: 8fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 80 bf
+UTF16: 803f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 bf bf
+UTF16: 8fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 80 80
+UTF16: 9000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 bf 80
+UTF16: 9fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 80 bf
+UTF16: 903f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 bf bf
+UTF16: 9fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea 80 80
+UTF16: a000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea bf 80
+UTF16: afc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea 80 bf
+UTF16: a03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea bf bf
+UTF16: afff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb 80 80
+UTF16: b000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb bf 80
+UTF16: bfc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb 80 bf
+UTF16: b03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb bf bf
+UTF16: bfff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec 80 80
+UTF16: c000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec bf 80
+UTF16: cfc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec 80 bf
+UTF16: c03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec bf bf
+UTF16: cfff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee 80 80
+UTF16: e000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee bf 80
+UTF16: efc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee 80 bf
+UTF16: e03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee bf bf
+UTF16: efff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef 80 80
+UTF16: f000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef bf 80
+UTF16: ffc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef 80 bf
+UTF16: f03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef bf bf
+UTF16: ffff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+
+----- Invalid characters (2nd byte is invalid) -----
+UTF8: e0 9f 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF16: 07c0 0fc0 083f 0fff 0abb
+ cc = 0
+ dst address difference: 10 dst len: 1990
+ src address difference: 15 src len: 0
+UTF8: e0 c0 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF16: 0000 0fc0 083f 0fff 0abb
+ cc = 0
+ dst address difference: 10 dst len: 1990
+ src address difference: 15 src len: 0
+UTF8: ed 7f 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF16: dfc0 d7c0 d03f d7ff d2bb
+ cc = 0
+ dst address difference: 10 dst len: 1990
+ src address difference: 15 src len: 0
+UTF8: ed a0 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF16: d800 d7c0 d03f d7ff d2bb
+ cc = 0
+ dst address difference: 10 dst len: 1990
+ src address difference: 15 src len: 0
+UTF8: e1 7f 80
+UTF16: 1fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e1 c0 80
+UTF16: 1000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 7f 80
+UTF16: 2fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 c0 80
+UTF16: 2000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 7f 80
+UTF16: 3fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 c0 80
+UTF16: 3000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 7f 80
+UTF16: 4fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 c0 80
+UTF16: 4000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 7f 80
+UTF16: 5fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 c0 80
+UTF16: 5000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 7f 80
+UTF16: 6fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 c0 80
+UTF16: 6000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 7f 80
+UTF16: 7fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 c0 80
+UTF16: 7000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 7f 80
+UTF16: 8fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 c0 80
+UTF16: 8000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 7f 80
+UTF16: 9fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 c0 80
+UTF16: 9000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea 7f 80
+UTF16: afc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea c0 80
+UTF16: a000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb 7f 80
+UTF16: bfc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb c0 80
+UTF16: b000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec 7f 80
+UTF16: cfc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec c0 80
+UTF16: c000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee 7f 80
+UTF16: efc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee c0 80
+UTF16: e000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef 7f 80
+UTF16: ffc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef c0 80
+UTF16: f000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+
+----- Invalid characters (3rd byte is invalid) -----
+UTF8: e0 ab 7f
+UTF16: 0aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e0 ab c0
+UTF16: 0ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e1 ab 7f
+UTF16: 1aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e1 ab c0
+UTF16: 1ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 ab 7f
+UTF16: 2aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 ab c0
+UTF16: 2ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 ab 7f
+UTF16: 3aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 ab c0
+UTF16: 3ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 ab 7f
+UTF16: 4aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 ab c0
+UTF16: 4ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 ab 7f
+UTF16: 5aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 ab c0
+UTF16: 5ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 ab 7f
+UTF16: 6aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 ab c0
+UTF16: 6ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 ab 7f
+UTF16: 7aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 ab c0
+UTF16: 7ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 ab 7f
+UTF16: 8aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 ab c0
+UTF16: 8ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 ab 7f
+UTF16: 9aff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 ab c0
+UTF16: 9ac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea ab 7f
+UTF16: aaff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea ab c0
+UTF16: aac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb ab 7f
+UTF16: baff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb ab c0
+UTF16: bac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec ab 7f
+UTF16: caff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec ab c0
+UTF16: cac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ed ab 7f
+UTF16: daff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ed ab c0
+UTF16: dac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee ab 7f
+UTF16: eaff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee ab c0
+UTF16: eac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef ab 7f
+UTF16: faff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef ab c0
+UTF16: fac0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+
+----- Invalid 2nd char AND output exhausted -----
+UTF8: e0 00 80
+UTF16: <none>
+ cc = 1
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 3
+
+----- Invalid 3rd char AND output exhausted -----
+UTF8: e4 84 00
+UTF16: <none>
+ cc = 1
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 3
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: e1 90 90 e1 00 90
+UTF16: 1410 1010
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 6 src len: 0
+
+===== Conversion of a four-byte character =====
+
+----- Valid characters -----
+UTF8: f0 90 80 80
+UTF16: d800 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 80 bf
+UTF16: d800 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 bf 80
+UTF16: d803 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 bf bf
+UTF16: d803 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf 80 80
+UTF16: d8bc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf 80 bf
+UTF16: d8bc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf bf 80
+UTF16: d8bf dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf bf bf
+UTF16: d8bf dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 80 80
+UTF16: d8c0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 80 bf
+UTF16: d8c0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 bf 80
+UTF16: d8c3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 bf bf
+UTF16: d8c3 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf 80 80
+UTF16: d9bc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf 80 bf
+UTF16: d9bc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf bf 80
+UTF16: d9bf dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf bf bf
+UTF16: d9bf dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 80 80
+UTF16: d9c0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 80 bf
+UTF16: d9c0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 bf 80
+UTF16: d9c3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 bf bf
+UTF16: d9c3 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf 80 80
+UTF16: dabc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf 80 bf
+UTF16: dabc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf bf 80
+UTF16: dabf dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf bf bf
+UTF16: dabf dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 80 80
+UTF16: dac0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 80 bf
+UTF16: dac0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 bf 80
+UTF16: dac3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 bf bf
+UTF16: dac3 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf 80 80
+UTF16: dbbc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf 80 bf
+UTF16: dbbc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf bf 80
+UTF16: dbbf dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf bf bf
+UTF16: dbbf dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 80 80
+UTF16: dbc0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 80 bf
+UTF16: dbc0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 bf 80
+UTF16: dbc3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 bf bf
+UTF16: dbc3 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f 80 80
+UTF16: dbfc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f 80 bf
+UTF16: dbfc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f bf 80
+UTF16: dbff dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f bf bf
+UTF16: dbff dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Valid characters if m3 == 0 -----
+UTF8: f5 00 00 00 f6 11 22 33 f7 44 55 66
+UTF16: d8c0 dc00 da06 dcb3 dad1 dd66
+ cc = 0
+ dst address difference: 12 dst len: 1988
+ src address difference: 12 src len: 0
+
+----- Invalid characters (2nd byte is invalid) -----
+UTF8: f0 8f 80 80
+UTF16: dbfc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 c0 80 80
+UTF16: dbc0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 7f 80 80
+UTF16: d8bc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 90 80 80
+UTF16: d800 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 7f 80 80
+UTF16: d9bc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 c0 80 80
+UTF16: d8c0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 7f 80 80
+UTF16: dabc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 c0 80 80
+UTF16: d9c0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 7f 80 80
+UTF16: dbbc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 c0 80 80
+UTF16: dac0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Invalid characters (3rd byte is invalid) -----
+UTF8: f0 94 7f 80
+UTF16: d813 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 94 c0 80
+UTF16: d810 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 84 7f 80
+UTF16: d8d3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 84 c0 80
+UTF16: d8d0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 84 7f 80
+UTF16: d9d3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 84 c0 80
+UTF16: d9d0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 84 7f 80
+UTF16: dad3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 84 c0 80
+UTF16: dad0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 84 7f 80
+UTF16: dbd3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 84 c0 80
+UTF16: dbd0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Invalid characters (4th byte is invalid) -----
+UTF8: f0 94 80 7f
+UTF16: d810 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 94 80 c0
+UTF16: d810 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 84 80 7f
+UTF16: d8d0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 84 80 c0
+UTF16: d8d0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 84 80 7f
+UTF16: d9d0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 84 80 c0
+UTF16: d9d0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 84 80 7f
+UTF16: dad0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 84 80 c0
+UTF16: dad0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 84 80 7f
+UTF16: dbd0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 84 80 c0
+UTF16: dbd0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Invalid 2nd char AND output exhausted -----
+UTF8: f0 00 80 80
+UTF16: <none>
+ cc = 1
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 4
+
+----- Invalid 3rd char AND output exhausted -----
+UTF8: f0 aa 00 80
+UTF16: <none>
+ cc = 1
+ dst address difference: 0 dst len: 3
+ src address difference: 0 src len: 4
+
+----- Invalid 4th char AND output exhausted -----
+UTF8: f0 aa aa 00
+UTF16: <none>
+ cc = 1
+ dst address difference: 0 dst len: 3
+ src address difference: 0 src len: 4
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: f0 aa aa aa f0 00 00 00
+UTF16: d86a deaa dbc0 dc00
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 8 src len: 0
+
+------------- test1 ----------------
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src len: 0
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: c2
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: e1
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: e1 80
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: f4
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f4 80
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: f4 80 80
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF8: 00 01
+UTF16: 0000 0001
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 2 src len: 0
+UTF8: c2 80 c2 81 c2
+UTF16: 0080 0081
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 1
+UTF8: e1 80 80 e1 80 81
+UTF16: 1000 1001
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 6 src len: 0
+UTF8: f4 80 80 80 f4 80 80 81 f4
+UTF16: dbc0 dc00 dbc0 dc01
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 8 src len: 1
+
+------------- test3.1 ----------------
+UTF8: 00 01 02 03
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 4
+UTF8: c2 80 c2 81 c2 82 c2 83
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 8
+UTF8: c2 80 c2 81 c2 82 c2 83
+UTF16: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 8
+UTF8: e1 80 80 e1 80 81 e1 80 82 e1 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 12
+UTF8: e1 80 80 e1 80 81 e1 80 82 e1 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 12
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 16
+
+------------- test3.2 ----------------
+UTF8: 00 01 02 03
+UTF16: 0000 0001
+ cc = 1
+ dst address difference: 4 dst len: 0
+ src address difference: 2 src len: 2
+UTF8: 00 01 02 03 c2 80 c2 81
+UTF16: 0000 0001
+ cc = 1
+ dst address difference: 4 dst len: 1
+ src address difference: 2 src len: 6
+UTF8: 00 01 02 03 c2 80 c2 81 c2 82 c2 83
+UTF16: 0000 0001 0002
+ cc = 1
+ dst address difference: 6 dst len: 0
+ src address difference: 3 src len: 9
+UTF8: 00 01 02 03 c2 80 c2 81 c2 82 c2 83 e1 80 80 e1
+UTF16: 0000 0001 0002
+ cc = 1
+ dst address difference: 6 dst len: 1
+ src address difference: 3 src len: 13
+
+------------- test4 ----------------
+UTF8: 01 c3 80 12 e1 90 93 23 f4 80 90 8a 34 c4 8c e1 91 94 c5 8a f4 80 90 8a c5 8a e1 91 94 f4 80 90 8a e1 91 94
+UTF16: 0001 00c0 0012 1413 0023 dbc1 dc0a 0034 010c 1454 014a dbc1 dc0a 014a 1454 dbc1 dc0a 1454
+ cc = 0
+ dst address difference: 36 dst len: 1964
+ src address difference: 36 src len: 0
diff --git a/main/none/tests/s390x/cu12.vgtest b/main/none/tests/s390x/cu12.vgtest
new file mode 100644
index 0000000..cdf8071
--- /dev/null
+++ b/main/none/tests/s390x/cu12.vgtest
@@ -0,0 +1 @@
+prog: cu12
diff --git a/main/none/tests/s390x/cu12_1.c b/main/none/tests/s390x/cu12_1.c
new file mode 100644
index 0000000..1281118
--- /dev/null
+++ b/main/none/tests/s390x/cu12_1.c
@@ -0,0 +1,595 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU12 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu12_t;
+
+/* Define various input buffers. */
+
+/* 1-byte UTF-8 character */
+uint8_t pattern1[] = {
+ 0x00, 0x01, 0x02, 0x03
+};
+
+/* 2-byte UTF-8 character */
+uint8_t pattern2[] = {
+ 0xc2, 0x80,
+ 0xc2, 0x81,
+ 0xc2, 0x82,
+ 0xc2, 0x83,
+};
+
+/* 3-byte UTF-8 character */
+uint8_t pattern3[] = {
+ 0xe1, 0x80, 0x80,
+ 0xe1, 0x80, 0x81,
+ 0xe1, 0x80, 0x82,
+ 0xe1, 0x80, 0x83,
+};
+
+/* 4-byte UTF-8 character */
+uint8_t pattern4[] = {
+ 0xf4, 0x80, 0x80, 0x80,
+ 0xf4, 0x80, 0x80, 0x81,
+ 0xf4, 0x80, 0x80, 0x82,
+ 0xf4, 0x80, 0x80, 0x83,
+};
+
+
+/* Mixed bytes */
+uint8_t mixed[] = {
+ 0x01, // 1 byte
+ 0xc3, 0x80, // 2 bytes
+ 0x12, // 1 byte
+ 0xe1, 0x90, 0x93, // 3 bytes
+ 0x23, // 1 byte
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0x34, // 1 byte
+ 0xc4, 0x8c, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+};
+
+/* This is the buffer for the converted bytes. */
+uint16_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+
+static cu12_t
+do_cu12(uint16_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu12_t regs;
+
+ /* build up the register pairs */
+ register uint8_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint16_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU12(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu12 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint16_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int i;
+ cu12_t result;
+
+ printf("UTF8: ");
+ if (src_len == 0)
+ printf(" <none>");
+ else {
+ for(i = 0; i < src_len; ++i)
+ printf(" %02x", src[i]);
+ }
+ printf("\n");
+
+ result = do_cu12(dst, dst_len, src, src_len);
+
+ // Write out the converted byte, if any
+ printf("UTF16: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else {
+ uint64_t num_bytes = dst_len - result.len1;
+
+ /* The number of bytes that were written must be divisible by 2 */
+ if (num_bytes % 2 != 0)
+ fprintf(stderr, "*** number of bytes is not a multiple of 2\n");
+
+ for (i = 0; i < num_bytes / 2; i++) {
+ printf(" %04x", dst[i]);
+ }
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+// Test conversion of a one-byte character
+void convert_1_byte(void)
+{
+ int i;
+
+ printf("===== Conversion of a one-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0x00, 0x7f, // corner cases
+ 0x01, 0x10, 0x7e, 0x5d // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters -----\n");
+ uint8_t always_invalid[] = {
+ 0x80, 0xbf, // corner cases
+ 0xf8, 0xff, // corner cases
+ 0x81, 0xbe, 0x95, 0xab // misc
+ };
+ for (i = 0; i < sizeof always_invalid; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = always_invalid[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ // In case of m3 == 0 we get cc=0 indicating exhaustion of source
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t invalid_if_m3[] = { // contains all such invalid characters
+ 0xc0, 0xc1,
+ 0xf5, 0xf6, 0xf7
+ };
+ for (i = 0; i < sizeof invalid_if_m3; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = invalid_if_m3[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0x10, // valid
+ 0xaa // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a two-byte character
+void convert_2_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a two-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0xc2, 0x80, // corner case
+ 0xc2, 0xbf, // corner case
+ 0xdf, 0x80, // corner case
+ 0xdf, 0xbf, // corner case
+ 0xc3, 0xbe, 0xda, 0xbc // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xc0 or 0xc1
+ uint8_t valid_if_not_m3[] = {
+ 0xc0, 0x80,
+ 0xc0, 0xbf,
+ 0xc1, 0x80,
+ 0xc0, 0xbf
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // Test for invalid two-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid if not in range 0x80..0xbf, inclusive
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t always_invalid[] = {
+ 0xc2, 0x00,
+ 0xc2, 0x7f,
+ 0xc2, 0xc0,
+ 0xc2, 0xff
+ };
+ for (i = 0; i < sizeof always_invalid; i += 2) {
+ uint8_t invalid_char[2];
+ invalid_char[0] = always_invalid[i];
+ invalid_char[1] = always_invalid[i+1];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ /* Nb: for a two-byte character we need not test the case where
+ invalidity of the character (cc=2) takes precedence over exhaustion
+ of the 1st operand (cc=1). Invalidity of the character has already
+ been tested when testing the 1st byte. */
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xc3, 0x81, // valid
+ 0xc4, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a three-byte character
+void
+convert_3_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a three-byte character =====\n");
+
+ /* Exhaustively test the 1st byte E0 - EF, and the interval boundaries for
+ the 2nd and 3rd bytes */
+ printf("\n----- Valid characters -----\n");
+ uint8_t e0[] = {
+ 0xe0, 0xa0, 0x80,
+ 0xe0, 0xbf, 0x80,
+ 0xe0, 0xa0, 0xbf,
+ 0xe0, 0xbf, 0xbf,
+ 0xe0, 0xaa, 0xbb, // random e0 .. ..
+ };
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ uint8_t ed[] = {
+ 0xed, 0x80, 0x80,
+ 0xed, 0x9f, 0x80,
+ 0xed, 0x80, 0xbf,
+ 0xed, 0x9f, 0xbf,
+ 0xed, 0x8a, 0xbb, // random ed .. ..
+ };
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x80, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xbf, 0x80 };
+ uint8_t exxx_3[3] = { 0x0, 0x80, 0xbf };
+ uint8_t exxx_4[3] = { 0x0, 0xbf, 0xbf };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ exxx_3[0] = 0xe0 | i;
+ exxx_4[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ run_test(buff, sizeof buff, exxx_3, sizeof exxx_3);
+ run_test(buff, sizeof buff, exxx_4, sizeof exxx_4);
+ };
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid three-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid.
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ e0[0] = 0xe0; // valid
+ e0[1] = 0x9f; // invalid because outside [0xa0 .. 0xbf]
+ e0[2] = 0x80; // valid
+ run_test(buff, sizeof buff, e0, sizeof e0);
+ e0[1] = 0xc0; // invalid because outside [0xa0 .. 0xbf]
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ ed[0] = 0xed; // valid
+ ed[1] = 0x7f; // invalid because outside [0x80 .. 0x9f]
+ ed[2] = 0x80; // valid
+ run_test(buff, sizeof buff, ed, sizeof ed);
+ ed[1] = 0xa0; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x7f, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xc0, 0x80 };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // For all 1st bytes 0xe0 .. 0xef the 3rd bytes must be in [0x80 .. 0xbf]
+ // No need to special case 0xe0 and 0xed
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0xab, 0x7f };
+ uint8_t exxx_2[3] = { 0x0, 0xab, 0xc0 };
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xe0, 0x00, 0x80
+ };
+ run_test(buff, 1, pat1, 3);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xe4, 0x84, 0x00
+ };
+ run_test(buff, 1, pat2, 3);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xe1, 0x90, 0x90, // valid
+ 0xe1, 0x00, 0x90 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a four-byte character
+void
+convert_4_bytes(void)
+{
+ int i, j;
+
+ printf("\n===== Conversion of a four-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ for (i = 0; i <= 4; ++i) {
+ uint8_t valid[4];
+
+ valid[0] = 0xf0 | i;
+
+ for (j = 0; j <= 1; ++j) {
+ // Byte 2
+ if (i == 0) {
+ valid[1] = j == 0 ? 0x90 : 0xbf; // 0xf0
+ } else if (i == 4) {
+ valid[1] = j == 0 ? 0x80 : 0x8f; // 0xf4
+ } else {
+ valid[1] = j == 0 ? 0x80 : 0xbf; // 0xf1 .. 0xf3
+ }
+ // Byte 3 and byte 4 have same interval 0x80 .. 0xbf
+ valid[2] = 0x80;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0x80;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ }
+ }
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xf5 .. 0xf7
+ uint8_t valid_if_not_m3[] = {
+ 0xf5, 0x00, 0x00, 0x00,
+ 0xf6, 0x11, 0x22, 0x33,
+ 0xf7, 0x44, 0x55, 0x66,
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 2nd byte is invalid.
+ // All other bytes are valid
+ uint8_t f0[4], f4[4];
+
+ f0[0] = 0xf0; // valid
+ f0[1] = 0x8f; // invalid because outside [0x90 .. 0xbf]
+ f0[2] = 0x80; // valid
+ f0[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f0, sizeof f0);
+ f0[1] = 0xc0; // invalid because outside [0x90 .. 0xbf]
+ run_test(buff, sizeof buff, f0, sizeof f0);
+
+ f4[0] = 0xf4; // valid
+ f4[1] = 0x7f; // invalid because outside [0x80 .. 0x8f]
+ f4[2] = 0x80; // valid
+ f4[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f4, sizeof f4);
+ f4[1] = 0x90; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, f4, sizeof f4);
+
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx_1[4] = { 0x0, 0x7f, 0x80, 0x80 };
+ uint8_t fxxx_2[4] = { 0x0, 0xc0, 0x80, 0x80 };
+
+ if (i == 0) continue; // special case f0
+ if (i == 4) continue; // special case f4
+
+ fxxx_1[0] = 0xf0 | i;
+ fxxx_2[0] = 0xf0 | i;
+ run_test(buff, sizeof buff, fxxx_1, sizeof fxxx_1);
+ run_test(buff, sizeof buff, fxxx_2, sizeof fxxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x0, 0x80 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[2] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[2] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid characters (4th byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x80, 0x0 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[3] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[3] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xf0, 0x00, 0x80, 0x80
+ };
+ run_test(buff, 1, pat1, 4);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xf0, 0xaa, 0x00, 0x80
+ };
+ run_test(buff, 3, pat2, 4);
+
+ printf("\n----- Invalid 4th char AND output exhausted -----\n");
+ /* The character is invalid in its 4th byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat3[] = {
+ 0xf0, 0xaa, 0xaa, 0x00
+ };
+ run_test(buff, 3, pat3, 4);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xf0, 0xaa, 0xaa, 0xaa, // valid
+ 0xf0, 0x00, 0x00, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+
+int main()
+{
+ convert_1_byte();
+ convert_2_bytes();
+ convert_3_bytes();
+ convert_4_bytes();
+
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 0);
+ run_test(buff, sizeof buff, pattern1, 0);
+ run_test(buff, sizeof buff, pattern2, 0);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern3, 0);
+ run_test(buff, sizeof buff, pattern3, 1);
+ run_test(buff, sizeof buff, pattern3, 2);
+ run_test(buff, sizeof buff, pattern4, 0);
+ run_test(buff, sizeof buff, pattern4, 1);
+ run_test(buff, sizeof buff, pattern4, 2);
+ run_test(buff, sizeof buff, pattern4, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 2);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern3, 6);
+ run_test(buff, sizeof buff, pattern4, 9);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write 2 or 4 bytes at a time */
+ run_test(NULL, 0, pattern1, sizeof pattern1); // 2-byte result
+ run_test(NULL, 0, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 1, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 0, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 1, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 0, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 1, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 2, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 3, pattern4, sizeof pattern4); // 4-byte result
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 4, pattern1, sizeof pattern1);
+ run_test(buff, 5, pattern1, sizeof pattern2);
+ run_test(buff, 6, pattern1, sizeof pattern3);
+ run_test(buff, 7, pattern1, sizeof pattern4);
+
+ /* Convert buffer with mixed characters */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cu12_1.stderr.exp b/main/none/tests/s390x/cu12_1.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu12_1.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu12_1.stdout.exp b/main/none/tests/s390x/cu12_1.stdout.exp
new file mode 100644
index 0000000..d5a616f
--- /dev/null
+++ b/main/none/tests/s390x/cu12_1.stdout.exp
@@ -0,0 +1,1325 @@
+===== Conversion of a one-byte character =====
+
+----- Valid characters -----
+UTF8: 00 7f 01 10 7e 5d
+UTF16: 0000 007f 0001 0010 007e 005d
+ cc = 0
+ dst address difference: 12 dst len: 1988
+ src address difference: 6 src len: 0
+
+----- Invalid characters -----
+UTF8: 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: bf
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f8
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: ff
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: 81
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: be
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: 95
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: ab
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+
+----- Invalid characters if m3 == 1 -----
+UTF8: c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: c1
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f5
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f6
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f7
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: 10 aa
+UTF16: 0010
+ cc = 2
+ dst address difference: 2 dst len: 1998
+ src address difference: 1 src len: 1
+
+===== Conversion of a two-byte character =====
+
+----- Valid characters -----
+UTF8: c2 80 c2 bf df 80 df bf c3 be da bc
+UTF16: 0080 00bf 07c0 07ff 00fe 06bc
+ cc = 0
+ dst address difference: 12 dst len: 1988
+ src address difference: 12 src len: 0
+
+----- Valid characters if m3 == 0 -----
+UTF8: c0 80 c0 bf c1 80 c0 bf
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 8
+
+----- Invalid characters if m3 == 1 -----
+UTF8: c2 00
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: c2 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: c2 c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: c2 ff
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: c3 81 c4 00
+UTF16: 00c1
+ cc = 2
+ dst address difference: 2 dst len: 1998
+ src address difference: 2 src len: 2
+
+===== Conversion of a three-byte character =====
+
+----- Valid characters -----
+UTF8: e0 a0 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF16: 0800 0fc0 083f 0fff 0abb
+ cc = 0
+ dst address difference: 10 dst len: 1990
+ src address difference: 15 src len: 0
+UTF8: ed 80 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF16: d000 d7c0 d03f d7ff d2bb
+ cc = 0
+ dst address difference: 10 dst len: 1990
+ src address difference: 15 src len: 0
+UTF8: e1 80 80
+UTF16: 1000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e1 bf 80
+UTF16: 1fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e1 80 bf
+UTF16: 103f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e1 bf bf
+UTF16: 1fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 80 80
+UTF16: 2000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 bf 80
+UTF16: 2fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 80 bf
+UTF16: 203f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e2 bf bf
+UTF16: 2fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 80 80
+UTF16: 3000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 bf 80
+UTF16: 3fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 80 bf
+UTF16: 303f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e3 bf bf
+UTF16: 3fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 80 80
+UTF16: 4000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 bf 80
+UTF16: 4fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 80 bf
+UTF16: 403f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e4 bf bf
+UTF16: 4fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 80 80
+UTF16: 5000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 bf 80
+UTF16: 5fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 80 bf
+UTF16: 503f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e5 bf bf
+UTF16: 5fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 80 80
+UTF16: 6000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 bf 80
+UTF16: 6fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 80 bf
+UTF16: 603f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e6 bf bf
+UTF16: 6fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 80 80
+UTF16: 7000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 bf 80
+UTF16: 7fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 80 bf
+UTF16: 703f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e7 bf bf
+UTF16: 7fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 80 80
+UTF16: 8000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 bf 80
+UTF16: 8fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 80 bf
+UTF16: 803f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e8 bf bf
+UTF16: 8fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 80 80
+UTF16: 9000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 bf 80
+UTF16: 9fc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 80 bf
+UTF16: 903f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: e9 bf bf
+UTF16: 9fff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea 80 80
+UTF16: a000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea bf 80
+UTF16: afc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea 80 bf
+UTF16: a03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ea bf bf
+UTF16: afff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb 80 80
+UTF16: b000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb bf 80
+UTF16: bfc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb 80 bf
+UTF16: b03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: eb bf bf
+UTF16: bfff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec 80 80
+UTF16: c000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec bf 80
+UTF16: cfc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec 80 bf
+UTF16: c03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ec bf bf
+UTF16: cfff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee 80 80
+UTF16: e000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee bf 80
+UTF16: efc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee 80 bf
+UTF16: e03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ee bf bf
+UTF16: efff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef 80 80
+UTF16: f000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef bf 80
+UTF16: ffc0
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef 80 bf
+UTF16: f03f
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+UTF8: ef bf bf
+UTF16: ffff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 0
+
+----- Invalid characters (2nd byte is invalid) -----
+UTF8: e0 9f 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 15
+UTF8: e0 c0 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 15
+UTF8: ed 7f 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 15
+UTF8: ed a0 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 15
+UTF8: e1 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e1 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e2 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e2 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e3 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e3 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e4 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e4 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e5 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e5 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e6 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e6 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e7 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e7 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e8 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e8 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e9 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e9 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ea 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ea c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: eb 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: eb c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ec 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ec c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ee 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ee c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ef 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ef c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+
+----- Invalid characters (3rd byte is invalid) -----
+UTF8: e0 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e0 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e1 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e1 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e2 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e2 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e3 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e3 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e4 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e4 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e5 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e5 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e6 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e6 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e7 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e7 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e8 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e8 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e9 ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e9 ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ea ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ea ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: eb ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: eb ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ec ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ec ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ed ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ed ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ee ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ee ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ef ab 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ef ab c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+
+----- Invalid 2nd char AND output exhausted -----
+UTF8: e0 00 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 3
+
+----- Invalid 3rd char AND output exhausted -----
+UTF8: e4 84 00
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 3
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: e1 90 90 e1 00 90
+UTF16: 1410
+ cc = 2
+ dst address difference: 2 dst len: 1998
+ src address difference: 3 src len: 3
+
+===== Conversion of a four-byte character =====
+
+----- Valid characters -----
+UTF8: f0 90 80 80
+UTF16: d800 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 80 bf
+UTF16: d800 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 bf 80
+UTF16: d803 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 bf bf
+UTF16: d803 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf 80 80
+UTF16: d8bc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf 80 bf
+UTF16: d8bc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf bf 80
+UTF16: d8bf dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf bf bf
+UTF16: d8bf dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 80 80
+UTF16: d8c0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 80 bf
+UTF16: d8c0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 bf 80
+UTF16: d8c3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 bf bf
+UTF16: d8c3 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf 80 80
+UTF16: d9bc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf 80 bf
+UTF16: d9bc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf bf 80
+UTF16: d9bf dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf bf bf
+UTF16: d9bf dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 80 80
+UTF16: d9c0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 80 bf
+UTF16: d9c0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 bf 80
+UTF16: d9c3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 bf bf
+UTF16: d9c3 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf 80 80
+UTF16: dabc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf 80 bf
+UTF16: dabc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf bf 80
+UTF16: dabf dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf bf bf
+UTF16: dabf dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 80 80
+UTF16: dac0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 80 bf
+UTF16: dac0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 bf 80
+UTF16: dac3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 bf bf
+UTF16: dac3 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf 80 80
+UTF16: dbbc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf 80 bf
+UTF16: dbbc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf bf 80
+UTF16: dbbf dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf bf bf
+UTF16: dbbf dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 80 80
+UTF16: dbc0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 80 bf
+UTF16: dbc0 dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 bf 80
+UTF16: dbc3 dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 bf bf
+UTF16: dbc3 dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f 80 80
+UTF16: dbfc dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f 80 bf
+UTF16: dbfc dc3f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f bf 80
+UTF16: dbff dfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f bf bf
+UTF16: dbff dfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Valid characters if m3 == 0 -----
+UTF8: f5 00 00 00 f6 11 22 33 f7 44 55 66
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 12
+
+----- Invalid characters (2nd byte is invalid) -----
+UTF8: f0 8f 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f0 c0 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 7f 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 90 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 7f 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 c0 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 7f 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 c0 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 7f 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 c0 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+
+----- Invalid characters (3rd byte is invalid) -----
+UTF8: f0 94 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f0 94 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 84 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 84 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 84 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 84 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 84 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 84 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 84 7f 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 84 c0 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+
+----- Invalid characters (4th byte is invalid) -----
+UTF8: f0 94 80 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f0 94 80 c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 84 80 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 84 80 c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 84 80 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 84 80 c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 84 80 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 84 80 c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 84 80 7f
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 84 80 c0
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+
+----- Invalid 2nd char AND output exhausted -----
+UTF8: f0 00 80 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 4
+
+----- Invalid 3rd char AND output exhausted -----
+UTF8: f0 aa 00 80
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 3
+ src address difference: 0 src len: 4
+
+----- Invalid 4th char AND output exhausted -----
+UTF8: f0 aa aa 00
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 3
+ src address difference: 0 src len: 4
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: f0 aa aa aa f0 00 00 00
+UTF16: d86a deaa
+ cc = 2
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 4
+
+------------- test1 ----------------
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src len: 0
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: c2
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: e1
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: e1 80
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: <none>
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: f4
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f4 80
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: f4 80 80
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF8: 00 01
+UTF16: 0000 0001
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 2 src len: 0
+UTF8: c2 80 c2 81 c2
+UTF16: 0080 0081
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 1
+UTF8: e1 80 80 e1 80 81
+UTF16: 1000 1001
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 6 src len: 0
+UTF8: f4 80 80 80 f4 80 80 81 f4
+UTF16: dbc0 dc00 dbc0 dc01
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 8 src len: 1
+
+------------- test3.1 ----------------
+UTF8: 00 01 02 03
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 4
+UTF8: c2 80 c2 81 c2 82 c2 83
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 8
+UTF8: c2 80 c2 81 c2 82 c2 83
+UTF16: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 8
+UTF8: e1 80 80 e1 80 81 e1 80 82 e1 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 12
+UTF8: e1 80 80 e1 80 81 e1 80 82 e1 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 12
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF16: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 16
+
+------------- test3.2 ----------------
+UTF8: 00 01 02 03
+UTF16: 0000 0001
+ cc = 1
+ dst address difference: 4 dst len: 0
+ src address difference: 2 src len: 2
+UTF8: 00 01 02 03 c2 80 c2 81
+UTF16: 0000 0001
+ cc = 1
+ dst address difference: 4 dst len: 1
+ src address difference: 2 src len: 6
+UTF8: 00 01 02 03 c2 80 c2 81 c2 82 c2 83
+UTF16: 0000 0001 0002
+ cc = 1
+ dst address difference: 6 dst len: 0
+ src address difference: 3 src len: 9
+UTF8: 00 01 02 03 c2 80 c2 81 c2 82 c2 83 e1 80 80 e1
+UTF16: 0000 0001 0002
+ cc = 1
+ dst address difference: 6 dst len: 1
+ src address difference: 3 src len: 13
+
+------------- test4 ----------------
+UTF8: 01 c3 80 12 e1 90 93 23 f4 80 90 8a 34 c4 8c e1 91 94 c5 8a f4 80 90 8a c5 8a e1 91 94 f4 80 90 8a e1 91 94
+UTF16: 0001 00c0 0012 1413 0023 dbc1 dc0a 0034 010c 1454 014a dbc1 dc0a 014a 1454 dbc1 dc0a 1454
+ cc = 0
+ dst address difference: 36 dst len: 1964
+ src address difference: 36 src len: 0
diff --git a/main/none/tests/s390x/cu12_1.vgtest b/main/none/tests/s390x/cu12_1.vgtest
new file mode 100644
index 0000000..f712482
--- /dev/null
+++ b/main/none/tests/s390x/cu12_1.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/s390x_features s390x-etf3
+prog: cu12_1
diff --git a/main/none/tests/s390x/cu14.c b/main/none/tests/s390x/cu14.c
new file mode 100644
index 0000000..44738c7
--- /dev/null
+++ b/main/none/tests/s390x/cu14.c
@@ -0,0 +1,595 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU14 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu14_t;
+
+/* Define various input buffers. */
+
+/* 1-byte UTF-8 character */
+uint8_t pattern1[] = {
+ 0x00, 0x01, 0x02, 0x03
+};
+
+/* 2-byte UTF-8 character */
+uint8_t pattern2[] = {
+ 0xc2, 0x80,
+ 0xc2, 0x81,
+ 0xc2, 0x82,
+ 0xc2, 0x83,
+};
+
+/* 3-byte UTF-8 character */
+uint8_t pattern3[] = {
+ 0xe1, 0x80, 0x80,
+ 0xe1, 0x80, 0x81,
+ 0xe1, 0x80, 0x82,
+ 0xe1, 0x80, 0x83,
+};
+
+/* 4-byte UTF-8 character */
+uint8_t pattern4[] = {
+ 0xf4, 0x80, 0x80, 0x80,
+ 0xf4, 0x80, 0x80, 0x81,
+ 0xf4, 0x80, 0x80, 0x82,
+ 0xf4, 0x80, 0x80, 0x83,
+};
+
+
+/* Mixed bytes */
+uint8_t mixed[] = {
+ 0x01, // 1 byte
+ 0xc3, 0x80, // 2 bytes
+ 0x12, // 1 byte
+ 0xe1, 0x90, 0x93, // 3 bytes
+ 0x23, // 1 byte
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0x34, // 1 byte
+ 0xc4, 0x8c, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+};
+
+/* This is the buffer for the converted bytes. */
+uint32_t buff[500]; /* Large so we con'don't have to worry about it */
+
+
+static cu14_t
+do_cu14(uint32_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu14_t regs;
+
+ /* build up the register pairs */
+ register uint8_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint32_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU14(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu14 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint32_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int i;
+ cu14_t result;
+
+ printf("UTF8: ");
+ if (src_len == 0)
+ printf(" <none>");
+ else {
+ for(i = 0; i < src_len; ++i)
+ printf(" %02x", src[i]);
+ }
+ printf("\n");
+
+ result = do_cu14(dst, dst_len, src, src_len);
+
+ // Write out the converted bytes, if any
+ printf("UTF32: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else {
+ uint64_t num_bytes = dst_len - result.len1;
+
+ /* The number of bytes that were written must be divisible by 4 */
+ if (num_bytes % 4 != 0)
+ fprintf(stderr, "*** number of bytes is not a multiple of 4\n");
+
+ for (i = 0; i < num_bytes / 4; i++) {
+ printf(" %08x", dst[i]);
+ }
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+// Test conversion of a one-byte character
+void convert_1_byte(void)
+{
+ int i;
+
+ printf("===== Conversion of a one-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0x00, 0x7f, // corner cases
+ 0x01, 0x10, 0x7e, 0x5d // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters -----\n");
+ uint8_t always_invalid[] = {
+ 0x80, 0xbf, // corner cases
+ 0xf8, 0xff, // corner cases
+ 0x81, 0xbe, 0x95, 0xab // misc
+ };
+ for (i = 0; i < sizeof always_invalid; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = always_invalid[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ // In case of m3 == 0 we get cc=0 indicating exhaustion of source
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t invalid_if_m3[] = { // contains all such invalid characters
+ 0xc0, 0xc1,
+ 0xf5, 0xf6, 0xf7
+ };
+ for (i = 0; i < sizeof invalid_if_m3; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = invalid_if_m3[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0x10, // valid
+ 0xaa // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a two-byte character
+void convert_2_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a two-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0xc2, 0x80, // corner case
+ 0xc2, 0xbf, // corner case
+ 0xdf, 0x80, // corner case
+ 0xdf, 0xbf, // corner case
+ 0xc3, 0xbe, 0xda, 0xbc // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xc0 or 0xc1
+ uint8_t valid_if_not_m3[] = {
+ 0xc0, 0x80,
+ 0xc0, 0xbf,
+ 0xc1, 0x80,
+ 0xc0, 0xbf
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // Test for invalid two-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid if not in range 0x80..0xbf, inclusive
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t always_invalid[] = {
+ 0xc2, 0x00,
+ 0xc2, 0x7f,
+ 0xc2, 0xc0,
+ 0xc2, 0xff
+ };
+ for (i = 0; i < sizeof always_invalid; i += 2) {
+ uint8_t invalid_char[2];
+ invalid_char[0] = always_invalid[i];
+ invalid_char[1] = always_invalid[i+1];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ /* Nb: for a two-byte character we need not test the case where
+ invalidity of the character (cc=2) takes precedence over exhaustion
+ of the 1st operand (cc=1). Invalidity of the character has already
+ been tested when testing the 1st byte. */
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xc3, 0x81, // valid
+ 0xc4, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a three-byte character
+void
+convert_3_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a three-byte character =====\n");
+
+ /* Exhaustively test the 1st byte E0 - EF, and the interval boundaries for
+ the 2nd and 3rd bytes */
+ printf("\n----- Valid characters -----\n");
+ uint8_t e0[] = {
+ 0xe0, 0xa0, 0x80,
+ 0xe0, 0xbf, 0x80,
+ 0xe0, 0xa0, 0xbf,
+ 0xe0, 0xbf, 0xbf,
+ 0xe0, 0xaa, 0xbb, // random e0 .. ..
+ };
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ uint8_t ed[] = {
+ 0xed, 0x80, 0x80,
+ 0xed, 0x9f, 0x80,
+ 0xed, 0x80, 0xbf,
+ 0xed, 0x9f, 0xbf,
+ 0xed, 0x8a, 0xbb, // random ed .. ..
+ };
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x80, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xbf, 0x80 };
+ uint8_t exxx_3[3] = { 0x0, 0x80, 0xbf };
+ uint8_t exxx_4[3] = { 0x0, 0xbf, 0xbf };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ exxx_3[0] = 0xe0 | i;
+ exxx_4[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ run_test(buff, sizeof buff, exxx_3, sizeof exxx_3);
+ run_test(buff, sizeof buff, exxx_4, sizeof exxx_4);
+ };
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid three-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid.
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ e0[0] = 0xe0; // valid
+ e0[1] = 0x9f; // invalid because outside [0xa0 .. 0xbf]
+ e0[2] = 0x80; // valid
+ run_test(buff, sizeof buff, e0, sizeof e0);
+ e0[1] = 0xc0; // invalid because outside [0xa0 .. 0xbf]
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ ed[0] = 0xed; // valid
+ ed[1] = 0x7f; // invalid because outside [0x80 .. 0x9f]
+ ed[2] = 0x80; // valid
+ run_test(buff, sizeof buff, ed, sizeof ed);
+ ed[1] = 0xa0; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x7f, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xc0, 0x80 };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // For all 1st bytes 0xe0 .. 0xef the 3rd bytes must be in [0x80 .. 0xbf]
+ // No need to special case 0xe0 and 0xed
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0xab, 0x7f };
+ uint8_t exxx_2[3] = { 0x0, 0xab, 0xc0 };
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xe0, 0x00, 0x80
+ };
+ run_test(buff, 1, pat1, 3);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xe4, 0x84, 0x00
+ };
+ run_test(buff, 1, pat2, 3);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xe1, 0x90, 0x90, // valid
+ 0xe1, 0x00, 0x90 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a four-byte character
+void
+convert_4_bytes(void)
+{
+ int i, j;
+
+ printf("\n===== Conversion of a four-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ for (i = 0; i <= 4; ++i) {
+ uint8_t valid[4];
+
+ valid[0] = 0xf0 | i;
+
+ for (j = 0; j <= 1; ++j) {
+ // Byte 2
+ if (i == 0) {
+ valid[1] = j == 0 ? 0x90 : 0xbf; // 0xf0
+ } else if (i == 4) {
+ valid[1] = j == 0 ? 0x80 : 0x8f; // 0xf4
+ } else {
+ valid[1] = j == 0 ? 0x80 : 0xbf; // 0xf1 .. 0xf3
+ }
+ // Byte 3 and byte 4 have same interval 0x80 .. 0xbf
+ valid[2] = 0x80;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0x80;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ }
+ }
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xf5 .. 0xf7
+ uint8_t valid_if_not_m3[] = {
+ 0xf5, 0x00, 0x00, 0x00,
+ 0xf6, 0x11, 0x22, 0x33,
+ 0xf7, 0x44, 0x55, 0x66,
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 2nd byte is invalid.
+ // All other bytes are valid
+ uint8_t f0[4], f4[4];
+
+ f0[0] = 0xf0; // valid
+ f0[1] = 0x8f; // invalid because outside [0x90 .. 0xbf]
+ f0[2] = 0x80; // valid
+ f0[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f0, sizeof f0);
+ f0[1] = 0xc0; // invalid because outside [0x90 .. 0xbf]
+ run_test(buff, sizeof buff, f0, sizeof f0);
+
+ f4[0] = 0xf4; // valid
+ f4[1] = 0x7f; // invalid because outside [0x80 .. 0x8f]
+ f4[2] = 0x80; // valid
+ f4[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f4, sizeof f4);
+ f4[1] = 0x90; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, f4, sizeof f4);
+
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx_1[4] = { 0x0, 0x7f, 0x80, 0x80 };
+ uint8_t fxxx_2[4] = { 0x0, 0xc0, 0x80, 0x80 };
+
+ if (i == 0) continue; // special case f0
+ if (i == 4) continue; // special case f4
+
+ fxxx_1[0] = 0xf0 | i;
+ fxxx_2[0] = 0xf0 | i;
+ run_test(buff, sizeof buff, fxxx_1, sizeof fxxx_1);
+ run_test(buff, sizeof buff, fxxx_2, sizeof fxxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x0, 0x80 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[2] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[2] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid characters (4th byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x80, 0x0 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[3] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[3] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xf0, 0x00, 0x80, 0x80
+ };
+ run_test(buff, 1, pat1, 4);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xf0, 0xaa, 0x00, 0x80
+ };
+ run_test(buff, 3, pat2, 4);
+
+ printf("\n----- Invalid 4th char AND output exhausted -----\n");
+ /* The character is invalid in its 4th byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat3[] = {
+ 0xf0, 0xaa, 0xaa, 0x00
+ };
+ run_test(buff, 3, pat3, 4);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xf0, 0xaa, 0xaa, 0xaa, // valid
+ 0xf0, 0x00, 0x00, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+
+int main()
+{
+ convert_1_byte();
+ convert_2_bytes();
+ convert_3_bytes();
+ convert_4_bytes();
+
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 0);
+ run_test(buff, sizeof buff, pattern1, 0);
+ run_test(buff, sizeof buff, pattern2, 0);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern3, 0);
+ run_test(buff, sizeof buff, pattern3, 1);
+ run_test(buff, sizeof buff, pattern3, 2);
+ run_test(buff, sizeof buff, pattern4, 0);
+ run_test(buff, sizeof buff, pattern4, 1);
+ run_test(buff, sizeof buff, pattern4, 2);
+ run_test(buff, sizeof buff, pattern4, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 2);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern3, 6);
+ run_test(buff, sizeof buff, pattern4, 9);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write 2 or 4 bytes at a time */
+ run_test(NULL, 0, pattern1, sizeof pattern1); // 2-byte result
+ run_test(NULL, 0, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 1, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 0, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 1, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 0, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 1, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 2, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 3, pattern4, sizeof pattern4); // 4-byte result
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 4, pattern1, sizeof pattern1);
+ run_test(buff, 5, pattern1, sizeof pattern2);
+ run_test(buff, 6, pattern1, sizeof pattern3);
+ run_test(buff, 7, pattern1, sizeof pattern4);
+
+ /* Convert buffer with mixed characters */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cu14.stderr.exp b/main/none/tests/s390x/cu14.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu14.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu14.stdout.exp b/main/none/tests/s390x/cu14.stdout.exp
new file mode 100644
index 0000000..9cba92d
--- /dev/null
+++ b/main/none/tests/s390x/cu14.stdout.exp
@@ -0,0 +1,1325 @@
+===== Conversion of a one-byte character =====
+
+----- Valid characters -----
+UTF8: 00 7f 01 10 7e 5d
+UTF32: 00000000 0000007f 00000001 00000010 0000007e 0000005d
+ cc = 0
+ dst address difference: 24 dst len: 1976
+ src address difference: 6 src len: 0
+
+----- Invalid characters -----
+UTF8: 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: bf
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f8
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: ff
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: 81
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: be
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: 95
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: ab
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+
+----- Invalid characters if m3 == 1 -----
+UTF8: c0
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: c1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f5
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f6
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f7
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: 10 aa
+UTF32: 00000010
+ cc = 2
+ dst address difference: 4 dst len: 1996
+ src address difference: 1 src len: 1
+
+===== Conversion of a two-byte character =====
+
+----- Valid characters -----
+UTF8: c2 80 c2 bf df 80 df bf c3 be da bc
+UTF32: 00000080 000000bf 000007c0 000007ff 000000fe 000006bc
+ cc = 0
+ dst address difference: 24 dst len: 1976
+ src address difference: 12 src len: 0
+
+----- Valid characters if m3 == 0 -----
+UTF8: c0 80 c0 bf c1 80 c0 bf
+UTF32: 00000000 0000003f 00000040 0000003f
+ cc = 0
+ dst address difference: 16 dst len: 1984
+ src address difference: 8 src len: 0
+
+----- Invalid characters if m3 == 1 -----
+UTF8: c2 00
+UTF32: 00000080
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 2 src len: 0
+UTF8: c2 7f
+UTF32: 000000bf
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 2 src len: 0
+UTF8: c2 c0
+UTF32: 00000080
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 2 src len: 0
+UTF8: c2 ff
+UTF32: 000000bf
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 2 src len: 0
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: c3 81 c4 00
+UTF32: 000000c1 00000100
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 4 src len: 0
+
+===== Conversion of a three-byte character =====
+
+----- Valid characters -----
+UTF8: e0 a0 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF32: 00000800 00000fc0 0000083f 00000fff 00000abb
+ cc = 0
+ dst address difference: 20 dst len: 1980
+ src address difference: 15 src len: 0
+UTF8: ed 80 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF32: 0000d000 0000d7c0 0000d03f 0000d7ff 0000d2bb
+ cc = 0
+ dst address difference: 20 dst len: 1980
+ src address difference: 15 src len: 0
+UTF8: e1 80 80
+UTF32: 00001000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e1 bf 80
+UTF32: 00001fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e1 80 bf
+UTF32: 0000103f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e1 bf bf
+UTF32: 00001fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 80 80
+UTF32: 00002000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 bf 80
+UTF32: 00002fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 80 bf
+UTF32: 0000203f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 bf bf
+UTF32: 00002fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 80 80
+UTF32: 00003000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 bf 80
+UTF32: 00003fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 80 bf
+UTF32: 0000303f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 bf bf
+UTF32: 00003fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 80 80
+UTF32: 00004000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 bf 80
+UTF32: 00004fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 80 bf
+UTF32: 0000403f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 bf bf
+UTF32: 00004fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 80 80
+UTF32: 00005000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 bf 80
+UTF32: 00005fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 80 bf
+UTF32: 0000503f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 bf bf
+UTF32: 00005fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 80 80
+UTF32: 00006000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 bf 80
+UTF32: 00006fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 80 bf
+UTF32: 0000603f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 bf bf
+UTF32: 00006fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 80 80
+UTF32: 00007000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 bf 80
+UTF32: 00007fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 80 bf
+UTF32: 0000703f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 bf bf
+UTF32: 00007fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 80 80
+UTF32: 00008000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 bf 80
+UTF32: 00008fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 80 bf
+UTF32: 0000803f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 bf bf
+UTF32: 00008fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 80 80
+UTF32: 00009000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 bf 80
+UTF32: 00009fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 80 bf
+UTF32: 0000903f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 bf bf
+UTF32: 00009fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea 80 80
+UTF32: 0000a000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea bf 80
+UTF32: 0000afc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea 80 bf
+UTF32: 0000a03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea bf bf
+UTF32: 0000afff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb 80 80
+UTF32: 0000b000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb bf 80
+UTF32: 0000bfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb 80 bf
+UTF32: 0000b03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb bf bf
+UTF32: 0000bfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec 80 80
+UTF32: 0000c000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec bf 80
+UTF32: 0000cfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec 80 bf
+UTF32: 0000c03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec bf bf
+UTF32: 0000cfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee 80 80
+UTF32: 0000e000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee bf 80
+UTF32: 0000efc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee 80 bf
+UTF32: 0000e03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee bf bf
+UTF32: 0000efff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef 80 80
+UTF32: 0000f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef bf 80
+UTF32: 0000ffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef 80 bf
+UTF32: 0000f03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef bf bf
+UTF32: 0000ffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+
+----- Invalid characters (2nd byte is invalid) -----
+UTF8: e0 9f 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF32: 000007c0 00000fc0 0000083f 00000fff 00000abb
+ cc = 0
+ dst address difference: 20 dst len: 1980
+ src address difference: 15 src len: 0
+UTF8: e0 c0 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF32: 00000000 00000fc0 0000083f 00000fff 00000abb
+ cc = 0
+ dst address difference: 20 dst len: 1980
+ src address difference: 15 src len: 0
+UTF8: ed 7f 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF32: 0000dfc0 0000d7c0 0000d03f 0000d7ff 0000d2bb
+ cc = 0
+ dst address difference: 20 dst len: 1980
+ src address difference: 15 src len: 0
+UTF8: ed a0 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF32: 0000d800 0000d7c0 0000d03f 0000d7ff 0000d2bb
+ cc = 0
+ dst address difference: 20 dst len: 1980
+ src address difference: 15 src len: 0
+UTF8: e1 7f 80
+UTF32: 00001fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e1 c0 80
+UTF32: 00001000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 7f 80
+UTF32: 00002fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 c0 80
+UTF32: 00002000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 7f 80
+UTF32: 00003fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 c0 80
+UTF32: 00003000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 7f 80
+UTF32: 00004fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 c0 80
+UTF32: 00004000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 7f 80
+UTF32: 00005fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 c0 80
+UTF32: 00005000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 7f 80
+UTF32: 00006fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 c0 80
+UTF32: 00006000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 7f 80
+UTF32: 00007fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 c0 80
+UTF32: 00007000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 7f 80
+UTF32: 00008fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 c0 80
+UTF32: 00008000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 7f 80
+UTF32: 00009fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 c0 80
+UTF32: 00009000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea 7f 80
+UTF32: 0000afc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea c0 80
+UTF32: 0000a000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb 7f 80
+UTF32: 0000bfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb c0 80
+UTF32: 0000b000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec 7f 80
+UTF32: 0000cfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec c0 80
+UTF32: 0000c000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee 7f 80
+UTF32: 0000efc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee c0 80
+UTF32: 0000e000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef 7f 80
+UTF32: 0000ffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef c0 80
+UTF32: 0000f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+
+----- Invalid characters (3rd byte is invalid) -----
+UTF8: e0 ab 7f
+UTF32: 00000aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e0 ab c0
+UTF32: 00000ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e1 ab 7f
+UTF32: 00001aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e1 ab c0
+UTF32: 00001ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 ab 7f
+UTF32: 00002aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 ab c0
+UTF32: 00002ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 ab 7f
+UTF32: 00003aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 ab c0
+UTF32: 00003ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 ab 7f
+UTF32: 00004aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 ab c0
+UTF32: 00004ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 ab 7f
+UTF32: 00005aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 ab c0
+UTF32: 00005ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 ab 7f
+UTF32: 00006aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 ab c0
+UTF32: 00006ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 ab 7f
+UTF32: 00007aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 ab c0
+UTF32: 00007ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 ab 7f
+UTF32: 00008aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 ab c0
+UTF32: 00008ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 ab 7f
+UTF32: 00009aff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 ab c0
+UTF32: 00009ac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea ab 7f
+UTF32: 0000aaff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea ab c0
+UTF32: 0000aac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb ab 7f
+UTF32: 0000baff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb ab c0
+UTF32: 0000bac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec ab 7f
+UTF32: 0000caff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec ab c0
+UTF32: 0000cac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ed ab 7f
+UTF32: 0000daff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ed ab c0
+UTF32: 0000dac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee ab 7f
+UTF32: 0000eaff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee ab c0
+UTF32: 0000eac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef ab 7f
+UTF32: 0000faff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef ab c0
+UTF32: 0000fac0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+
+----- Invalid 2nd char AND output exhausted -----
+UTF8: e0 00 80
+UTF32: <none>
+ cc = 1
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 3
+
+----- Invalid 3rd char AND output exhausted -----
+UTF8: e4 84 00
+UTF32: <none>
+ cc = 1
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 3
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: e1 90 90 e1 00 90
+UTF32: 00001410 00001010
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 6 src len: 0
+
+===== Conversion of a four-byte character =====
+
+----- Valid characters -----
+UTF8: f0 90 80 80
+UTF32: 00010000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 80 bf
+UTF32: 0001003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 bf 80
+UTF32: 00010fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 bf bf
+UTF32: 00010fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf 80 80
+UTF32: 0003f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf 80 bf
+UTF32: 0003f03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf bf 80
+UTF32: 0003ffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf bf bf
+UTF32: 0003ffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 80 80
+UTF32: 00040000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 80 bf
+UTF32: 0004003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 bf 80
+UTF32: 00040fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 bf bf
+UTF32: 00040fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf 80 80
+UTF32: 0007f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf 80 bf
+UTF32: 0007f03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf bf 80
+UTF32: 0007ffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf bf bf
+UTF32: 0007ffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 80 80
+UTF32: 00080000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 80 bf
+UTF32: 0008003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 bf 80
+UTF32: 00080fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 bf bf
+UTF32: 00080fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf 80 80
+UTF32: 000bf000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf 80 bf
+UTF32: 000bf03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf bf 80
+UTF32: 000bffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf bf bf
+UTF32: 000bffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 80 80
+UTF32: 000c0000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 80 bf
+UTF32: 000c003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 bf 80
+UTF32: 000c0fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 bf bf
+UTF32: 000c0fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf 80 80
+UTF32: 000ff000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf 80 bf
+UTF32: 000ff03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf bf 80
+UTF32: 000fffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf bf bf
+UTF32: 000fffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 80 80
+UTF32: 00100000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 80 bf
+UTF32: 0010003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 bf 80
+UTF32: 00100fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 bf bf
+UTF32: 00100fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f 80 80
+UTF32: 0010f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f 80 bf
+UTF32: 0010f03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f bf 80
+UTF32: 0010ffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f bf bf
+UTF32: 0010ffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Valid characters if m3 == 0 -----
+UTF8: f5 00 00 00 f6 11 22 33 f7 44 55 66
+UTF32: 00140000 001918b3 001c4566
+ cc = 0
+ dst address difference: 12 dst len: 1988
+ src address difference: 12 src len: 0
+
+----- Invalid characters (2nd byte is invalid) -----
+UTF8: f0 8f 80 80
+UTF32: 0000f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 c0 80 80
+UTF32: 00000000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 7f 80 80
+UTF32: 0013f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 90 80 80
+UTF32: 00110000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 7f 80 80
+UTF32: 0007f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 c0 80 80
+UTF32: 00040000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 7f 80 80
+UTF32: 000bf000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 c0 80 80
+UTF32: 00080000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 7f 80 80
+UTF32: 000ff000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 c0 80 80
+UTF32: 000c0000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Invalid characters (3rd byte is invalid) -----
+UTF8: f0 94 7f 80
+UTF32: 00014fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 94 c0 80
+UTF32: 00014000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 84 7f 80
+UTF32: 00044fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 84 c0 80
+UTF32: 00044000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 84 7f 80
+UTF32: 00084fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 84 c0 80
+UTF32: 00084000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 84 7f 80
+UTF32: 000c4fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 84 c0 80
+UTF32: 000c4000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 84 7f 80
+UTF32: 00104fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 84 c0 80
+UTF32: 00104000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Invalid characters (4th byte is invalid) -----
+UTF8: f0 94 80 7f
+UTF32: 0001403f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 94 80 c0
+UTF32: 00014000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 84 80 7f
+UTF32: 0004403f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 84 80 c0
+UTF32: 00044000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 84 80 7f
+UTF32: 0008403f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 84 80 c0
+UTF32: 00084000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 84 80 7f
+UTF32: 000c403f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 84 80 c0
+UTF32: 000c4000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 84 80 7f
+UTF32: 0010403f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 84 80 c0
+UTF32: 00104000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Invalid 2nd char AND output exhausted -----
+UTF8: f0 00 80 80
+UTF32: <none>
+ cc = 1
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 4
+
+----- Invalid 3rd char AND output exhausted -----
+UTF8: f0 aa 00 80
+UTF32: <none>
+ cc = 1
+ dst address difference: 0 dst len: 3
+ src address difference: 0 src len: 4
+
+----- Invalid 4th char AND output exhausted -----
+UTF8: f0 aa aa 00
+UTF32: <none>
+ cc = 1
+ dst address difference: 0 dst len: 3
+ src address difference: 0 src len: 4
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: f0 aa aa aa f0 00 00 00
+UTF32: 0002aaaa 00000000
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 8 src len: 0
+
+------------- test1 ----------------
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src len: 0
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: c2
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: e1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: e1 80
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: f4
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f4 80
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: f4 80 80
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF8: 00 01
+UTF32: 00000000 00000001
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 2 src len: 0
+UTF8: c2 80 c2 81 c2
+UTF32: 00000080 00000081
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 4 src len: 1
+UTF8: e1 80 80 e1 80 81
+UTF32: 00001000 00001001
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 6 src len: 0
+UTF8: f4 80 80 80 f4 80 80 81 f4
+UTF32: 00100000 00100001
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 8 src len: 1
+
+------------- test3.1 ----------------
+UTF8: 00 01 02 03
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 4
+UTF8: c2 80 c2 81 c2 82 c2 83
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 8
+UTF8: c2 80 c2 81 c2 82 c2 83
+UTF32: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 8
+UTF8: e1 80 80 e1 80 81 e1 80 82 e1 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 12
+UTF8: e1 80 80 e1 80 81 e1 80 82 e1 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 12
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 16
+
+------------- test3.2 ----------------
+UTF8: 00 01 02 03
+UTF32: 00000000
+ cc = 1
+ dst address difference: 4 dst len: 0
+ src address difference: 1 src len: 3
+UTF8: 00 01 02 03 c2 80 c2 81
+UTF32: 00000000
+ cc = 1
+ dst address difference: 4 dst len: 1
+ src address difference: 1 src len: 7
+UTF8: 00 01 02 03 c2 80 c2 81 c2 82 c2 83
+UTF32: 00000000
+ cc = 1
+ dst address difference: 4 dst len: 2
+ src address difference: 1 src len: 11
+UTF8: 00 01 02 03 c2 80 c2 81 c2 82 c2 83 e1 80 80 e1
+UTF32: 00000000
+ cc = 1
+ dst address difference: 4 dst len: 3
+ src address difference: 1 src len: 15
+
+------------- test4 ----------------
+UTF8: 01 c3 80 12 e1 90 93 23 f4 80 90 8a 34 c4 8c e1 91 94 c5 8a f4 80 90 8a c5 8a e1 91 94 f4 80 90 8a e1 91 94
+UTF32: 00000001 000000c0 00000012 00001413 00000023 0010040a 00000034 0000010c 00001454 0000014a 0010040a 0000014a 00001454 0010040a 00001454
+ cc = 0
+ dst address difference: 60 dst len: 1940
+ src address difference: 36 src len: 0
diff --git a/main/none/tests/s390x/cu14.vgtest b/main/none/tests/s390x/cu14.vgtest
new file mode 100644
index 0000000..5c71bcb
--- /dev/null
+++ b/main/none/tests/s390x/cu14.vgtest
@@ -0,0 +1 @@
+prog: cu14
diff --git a/main/none/tests/s390x/cu14_1.c b/main/none/tests/s390x/cu14_1.c
new file mode 100644
index 0000000..44738c7
--- /dev/null
+++ b/main/none/tests/s390x/cu14_1.c
@@ -0,0 +1,595 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU14 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu14_t;
+
+/* Define various input buffers. */
+
+/* 1-byte UTF-8 character */
+uint8_t pattern1[] = {
+ 0x00, 0x01, 0x02, 0x03
+};
+
+/* 2-byte UTF-8 character */
+uint8_t pattern2[] = {
+ 0xc2, 0x80,
+ 0xc2, 0x81,
+ 0xc2, 0x82,
+ 0xc2, 0x83,
+};
+
+/* 3-byte UTF-8 character */
+uint8_t pattern3[] = {
+ 0xe1, 0x80, 0x80,
+ 0xe1, 0x80, 0x81,
+ 0xe1, 0x80, 0x82,
+ 0xe1, 0x80, 0x83,
+};
+
+/* 4-byte UTF-8 character */
+uint8_t pattern4[] = {
+ 0xf4, 0x80, 0x80, 0x80,
+ 0xf4, 0x80, 0x80, 0x81,
+ 0xf4, 0x80, 0x80, 0x82,
+ 0xf4, 0x80, 0x80, 0x83,
+};
+
+
+/* Mixed bytes */
+uint8_t mixed[] = {
+ 0x01, // 1 byte
+ 0xc3, 0x80, // 2 bytes
+ 0x12, // 1 byte
+ 0xe1, 0x90, 0x93, // 3 bytes
+ 0x23, // 1 byte
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0x34, // 1 byte
+ 0xc4, 0x8c, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+};
+
+/* This is the buffer for the converted bytes. */
+uint32_t buff[500]; /* Large so we con'don't have to worry about it */
+
+
+static cu14_t
+do_cu14(uint32_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu14_t regs;
+
+ /* build up the register pairs */
+ register uint8_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint32_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU14(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu14 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint32_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int i;
+ cu14_t result;
+
+ printf("UTF8: ");
+ if (src_len == 0)
+ printf(" <none>");
+ else {
+ for(i = 0; i < src_len; ++i)
+ printf(" %02x", src[i]);
+ }
+ printf("\n");
+
+ result = do_cu14(dst, dst_len, src, src_len);
+
+ // Write out the converted bytes, if any
+ printf("UTF32: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else {
+ uint64_t num_bytes = dst_len - result.len1;
+
+ /* The number of bytes that were written must be divisible by 4 */
+ if (num_bytes % 4 != 0)
+ fprintf(stderr, "*** number of bytes is not a multiple of 4\n");
+
+ for (i = 0; i < num_bytes / 4; i++) {
+ printf(" %08x", dst[i]);
+ }
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+// Test conversion of a one-byte character
+void convert_1_byte(void)
+{
+ int i;
+
+ printf("===== Conversion of a one-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0x00, 0x7f, // corner cases
+ 0x01, 0x10, 0x7e, 0x5d // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters -----\n");
+ uint8_t always_invalid[] = {
+ 0x80, 0xbf, // corner cases
+ 0xf8, 0xff, // corner cases
+ 0x81, 0xbe, 0x95, 0xab // misc
+ };
+ for (i = 0; i < sizeof always_invalid; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = always_invalid[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ // In case of m3 == 0 we get cc=0 indicating exhaustion of source
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t invalid_if_m3[] = { // contains all such invalid characters
+ 0xc0, 0xc1,
+ 0xf5, 0xf6, 0xf7
+ };
+ for (i = 0; i < sizeof invalid_if_m3; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = invalid_if_m3[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0x10, // valid
+ 0xaa // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a two-byte character
+void convert_2_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a two-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0xc2, 0x80, // corner case
+ 0xc2, 0xbf, // corner case
+ 0xdf, 0x80, // corner case
+ 0xdf, 0xbf, // corner case
+ 0xc3, 0xbe, 0xda, 0xbc // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xc0 or 0xc1
+ uint8_t valid_if_not_m3[] = {
+ 0xc0, 0x80,
+ 0xc0, 0xbf,
+ 0xc1, 0x80,
+ 0xc0, 0xbf
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // Test for invalid two-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid if not in range 0x80..0xbf, inclusive
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t always_invalid[] = {
+ 0xc2, 0x00,
+ 0xc2, 0x7f,
+ 0xc2, 0xc0,
+ 0xc2, 0xff
+ };
+ for (i = 0; i < sizeof always_invalid; i += 2) {
+ uint8_t invalid_char[2];
+ invalid_char[0] = always_invalid[i];
+ invalid_char[1] = always_invalid[i+1];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ /* Nb: for a two-byte character we need not test the case where
+ invalidity of the character (cc=2) takes precedence over exhaustion
+ of the 1st operand (cc=1). Invalidity of the character has already
+ been tested when testing the 1st byte. */
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xc3, 0x81, // valid
+ 0xc4, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a three-byte character
+void
+convert_3_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a three-byte character =====\n");
+
+ /* Exhaustively test the 1st byte E0 - EF, and the interval boundaries for
+ the 2nd and 3rd bytes */
+ printf("\n----- Valid characters -----\n");
+ uint8_t e0[] = {
+ 0xe0, 0xa0, 0x80,
+ 0xe0, 0xbf, 0x80,
+ 0xe0, 0xa0, 0xbf,
+ 0xe0, 0xbf, 0xbf,
+ 0xe0, 0xaa, 0xbb, // random e0 .. ..
+ };
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ uint8_t ed[] = {
+ 0xed, 0x80, 0x80,
+ 0xed, 0x9f, 0x80,
+ 0xed, 0x80, 0xbf,
+ 0xed, 0x9f, 0xbf,
+ 0xed, 0x8a, 0xbb, // random ed .. ..
+ };
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x80, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xbf, 0x80 };
+ uint8_t exxx_3[3] = { 0x0, 0x80, 0xbf };
+ uint8_t exxx_4[3] = { 0x0, 0xbf, 0xbf };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ exxx_3[0] = 0xe0 | i;
+ exxx_4[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ run_test(buff, sizeof buff, exxx_3, sizeof exxx_3);
+ run_test(buff, sizeof buff, exxx_4, sizeof exxx_4);
+ };
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid three-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid.
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ e0[0] = 0xe0; // valid
+ e0[1] = 0x9f; // invalid because outside [0xa0 .. 0xbf]
+ e0[2] = 0x80; // valid
+ run_test(buff, sizeof buff, e0, sizeof e0);
+ e0[1] = 0xc0; // invalid because outside [0xa0 .. 0xbf]
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ ed[0] = 0xed; // valid
+ ed[1] = 0x7f; // invalid because outside [0x80 .. 0x9f]
+ ed[2] = 0x80; // valid
+ run_test(buff, sizeof buff, ed, sizeof ed);
+ ed[1] = 0xa0; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x7f, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xc0, 0x80 };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // For all 1st bytes 0xe0 .. 0xef the 3rd bytes must be in [0x80 .. 0xbf]
+ // No need to special case 0xe0 and 0xed
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0xab, 0x7f };
+ uint8_t exxx_2[3] = { 0x0, 0xab, 0xc0 };
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xe0, 0x00, 0x80
+ };
+ run_test(buff, 1, pat1, 3);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xe4, 0x84, 0x00
+ };
+ run_test(buff, 1, pat2, 3);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xe1, 0x90, 0x90, // valid
+ 0xe1, 0x00, 0x90 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a four-byte character
+void
+convert_4_bytes(void)
+{
+ int i, j;
+
+ printf("\n===== Conversion of a four-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ for (i = 0; i <= 4; ++i) {
+ uint8_t valid[4];
+
+ valid[0] = 0xf0 | i;
+
+ for (j = 0; j <= 1; ++j) {
+ // Byte 2
+ if (i == 0) {
+ valid[1] = j == 0 ? 0x90 : 0xbf; // 0xf0
+ } else if (i == 4) {
+ valid[1] = j == 0 ? 0x80 : 0x8f; // 0xf4
+ } else {
+ valid[1] = j == 0 ? 0x80 : 0xbf; // 0xf1 .. 0xf3
+ }
+ // Byte 3 and byte 4 have same interval 0x80 .. 0xbf
+ valid[2] = 0x80;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0x80;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ }
+ }
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xf5 .. 0xf7
+ uint8_t valid_if_not_m3[] = {
+ 0xf5, 0x00, 0x00, 0x00,
+ 0xf6, 0x11, 0x22, 0x33,
+ 0xf7, 0x44, 0x55, 0x66,
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 2nd byte is invalid.
+ // All other bytes are valid
+ uint8_t f0[4], f4[4];
+
+ f0[0] = 0xf0; // valid
+ f0[1] = 0x8f; // invalid because outside [0x90 .. 0xbf]
+ f0[2] = 0x80; // valid
+ f0[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f0, sizeof f0);
+ f0[1] = 0xc0; // invalid because outside [0x90 .. 0xbf]
+ run_test(buff, sizeof buff, f0, sizeof f0);
+
+ f4[0] = 0xf4; // valid
+ f4[1] = 0x7f; // invalid because outside [0x80 .. 0x8f]
+ f4[2] = 0x80; // valid
+ f4[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f4, sizeof f4);
+ f4[1] = 0x90; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, f4, sizeof f4);
+
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx_1[4] = { 0x0, 0x7f, 0x80, 0x80 };
+ uint8_t fxxx_2[4] = { 0x0, 0xc0, 0x80, 0x80 };
+
+ if (i == 0) continue; // special case f0
+ if (i == 4) continue; // special case f4
+
+ fxxx_1[0] = 0xf0 | i;
+ fxxx_2[0] = 0xf0 | i;
+ run_test(buff, sizeof buff, fxxx_1, sizeof fxxx_1);
+ run_test(buff, sizeof buff, fxxx_2, sizeof fxxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x0, 0x80 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[2] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[2] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid characters (4th byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x80, 0x0 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[3] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[3] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xf0, 0x00, 0x80, 0x80
+ };
+ run_test(buff, 1, pat1, 4);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xf0, 0xaa, 0x00, 0x80
+ };
+ run_test(buff, 3, pat2, 4);
+
+ printf("\n----- Invalid 4th char AND output exhausted -----\n");
+ /* The character is invalid in its 4th byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat3[] = {
+ 0xf0, 0xaa, 0xaa, 0x00
+ };
+ run_test(buff, 3, pat3, 4);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xf0, 0xaa, 0xaa, 0xaa, // valid
+ 0xf0, 0x00, 0x00, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+
+int main()
+{
+ convert_1_byte();
+ convert_2_bytes();
+ convert_3_bytes();
+ convert_4_bytes();
+
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 0);
+ run_test(buff, sizeof buff, pattern1, 0);
+ run_test(buff, sizeof buff, pattern2, 0);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern3, 0);
+ run_test(buff, sizeof buff, pattern3, 1);
+ run_test(buff, sizeof buff, pattern3, 2);
+ run_test(buff, sizeof buff, pattern4, 0);
+ run_test(buff, sizeof buff, pattern4, 1);
+ run_test(buff, sizeof buff, pattern4, 2);
+ run_test(buff, sizeof buff, pattern4, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 2);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern3, 6);
+ run_test(buff, sizeof buff, pattern4, 9);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write 2 or 4 bytes at a time */
+ run_test(NULL, 0, pattern1, sizeof pattern1); // 2-byte result
+ run_test(NULL, 0, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 1, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 0, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 1, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 0, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 1, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 2, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 3, pattern4, sizeof pattern4); // 4-byte result
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 4, pattern1, sizeof pattern1);
+ run_test(buff, 5, pattern1, sizeof pattern2);
+ run_test(buff, 6, pattern1, sizeof pattern3);
+ run_test(buff, 7, pattern1, sizeof pattern4);
+
+ /* Convert buffer with mixed characters */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cu14_1.stderr.exp b/main/none/tests/s390x/cu14_1.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu14_1.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu14_1.stdout.exp b/main/none/tests/s390x/cu14_1.stdout.exp
new file mode 100644
index 0000000..a685c0e
--- /dev/null
+++ b/main/none/tests/s390x/cu14_1.stdout.exp
@@ -0,0 +1,1325 @@
+===== Conversion of a one-byte character =====
+
+----- Valid characters -----
+UTF8: 00 7f 01 10 7e 5d
+UTF32: 00000000 0000007f 00000001 00000010 0000007e 0000005d
+ cc = 0
+ dst address difference: 24 dst len: 1976
+ src address difference: 6 src len: 0
+
+----- Invalid characters -----
+UTF8: 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: bf
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f8
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: ff
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: 81
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: be
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: 95
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: ab
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+
+----- Invalid characters if m3 == 1 -----
+UTF8: c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: c1
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f5
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f6
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f7
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: 10 aa
+UTF32: 00000010
+ cc = 2
+ dst address difference: 4 dst len: 1996
+ src address difference: 1 src len: 1
+
+===== Conversion of a two-byte character =====
+
+----- Valid characters -----
+UTF8: c2 80 c2 bf df 80 df bf c3 be da bc
+UTF32: 00000080 000000bf 000007c0 000007ff 000000fe 000006bc
+ cc = 0
+ dst address difference: 24 dst len: 1976
+ src address difference: 12 src len: 0
+
+----- Valid characters if m3 == 0 -----
+UTF8: c0 80 c0 bf c1 80 c0 bf
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 8
+
+----- Invalid characters if m3 == 1 -----
+UTF8: c2 00
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: c2 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: c2 c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: c2 ff
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: c3 81 c4 00
+UTF32: 000000c1
+ cc = 2
+ dst address difference: 4 dst len: 1996
+ src address difference: 2 src len: 2
+
+===== Conversion of a three-byte character =====
+
+----- Valid characters -----
+UTF8: e0 a0 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF32: 00000800 00000fc0 0000083f 00000fff 00000abb
+ cc = 0
+ dst address difference: 20 dst len: 1980
+ src address difference: 15 src len: 0
+UTF8: ed 80 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF32: 0000d000 0000d7c0 0000d03f 0000d7ff 0000d2bb
+ cc = 0
+ dst address difference: 20 dst len: 1980
+ src address difference: 15 src len: 0
+UTF8: e1 80 80
+UTF32: 00001000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e1 bf 80
+UTF32: 00001fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e1 80 bf
+UTF32: 0000103f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e1 bf bf
+UTF32: 00001fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 80 80
+UTF32: 00002000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 bf 80
+UTF32: 00002fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 80 bf
+UTF32: 0000203f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e2 bf bf
+UTF32: 00002fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 80 80
+UTF32: 00003000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 bf 80
+UTF32: 00003fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 80 bf
+UTF32: 0000303f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e3 bf bf
+UTF32: 00003fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 80 80
+UTF32: 00004000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 bf 80
+UTF32: 00004fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 80 bf
+UTF32: 0000403f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e4 bf bf
+UTF32: 00004fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 80 80
+UTF32: 00005000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 bf 80
+UTF32: 00005fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 80 bf
+UTF32: 0000503f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e5 bf bf
+UTF32: 00005fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 80 80
+UTF32: 00006000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 bf 80
+UTF32: 00006fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 80 bf
+UTF32: 0000603f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e6 bf bf
+UTF32: 00006fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 80 80
+UTF32: 00007000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 bf 80
+UTF32: 00007fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 80 bf
+UTF32: 0000703f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e7 bf bf
+UTF32: 00007fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 80 80
+UTF32: 00008000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 bf 80
+UTF32: 00008fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 80 bf
+UTF32: 0000803f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e8 bf bf
+UTF32: 00008fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 80 80
+UTF32: 00009000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 bf 80
+UTF32: 00009fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 80 bf
+UTF32: 0000903f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: e9 bf bf
+UTF32: 00009fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea 80 80
+UTF32: 0000a000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea bf 80
+UTF32: 0000afc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea 80 bf
+UTF32: 0000a03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ea bf bf
+UTF32: 0000afff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb 80 80
+UTF32: 0000b000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb bf 80
+UTF32: 0000bfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb 80 bf
+UTF32: 0000b03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: eb bf bf
+UTF32: 0000bfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec 80 80
+UTF32: 0000c000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec bf 80
+UTF32: 0000cfc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec 80 bf
+UTF32: 0000c03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ec bf bf
+UTF32: 0000cfff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee 80 80
+UTF32: 0000e000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee bf 80
+UTF32: 0000efc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee 80 bf
+UTF32: 0000e03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ee bf bf
+UTF32: 0000efff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef 80 80
+UTF32: 0000f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef bf 80
+UTF32: 0000ffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef 80 bf
+UTF32: 0000f03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+UTF8: ef bf bf
+UTF32: 0000ffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 0
+
+----- Invalid characters (2nd byte is invalid) -----
+UTF8: e0 9f 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 15
+UTF8: e0 c0 80 e0 bf 80 e0 a0 bf e0 bf bf e0 aa bb
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 15
+UTF8: ed 7f 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 15
+UTF8: ed a0 80 ed 9f 80 ed 80 bf ed 9f bf ed 8a bb
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 15
+UTF8: e1 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e1 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e2 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e2 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e3 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e3 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e4 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e4 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e5 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e5 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e6 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e6 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e7 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e7 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e8 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e8 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e9 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e9 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ea 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ea c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: eb 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: eb c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ec 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ec c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ee 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ee c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ef 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ef c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+
+----- Invalid characters (3rd byte is invalid) -----
+UTF8: e0 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e0 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e1 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e1 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e2 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e2 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e3 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e3 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e4 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e4 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e5 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e5 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e6 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e6 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e7 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e7 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e8 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e8 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e9 ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: e9 ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ea ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ea ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: eb ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: eb ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ec ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ec ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ed ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ed ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ee ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ee ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ef ab 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+UTF8: ef ab c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+
+----- Invalid 2nd char AND output exhausted -----
+UTF8: e0 00 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 3
+
+----- Invalid 3rd char AND output exhausted -----
+UTF8: e4 84 00
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 3
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: e1 90 90 e1 00 90
+UTF32: 00001410
+ cc = 2
+ dst address difference: 4 dst len: 1996
+ src address difference: 3 src len: 3
+
+===== Conversion of a four-byte character =====
+
+----- Valid characters -----
+UTF8: f0 90 80 80
+UTF32: 00010000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 80 bf
+UTF32: 0001003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 bf 80
+UTF32: 00010fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 90 bf bf
+UTF32: 00010fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf 80 80
+UTF32: 0003f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf 80 bf
+UTF32: 0003f03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf bf 80
+UTF32: 0003ffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f0 bf bf bf
+UTF32: 0003ffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 80 80
+UTF32: 00040000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 80 bf
+UTF32: 0004003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 bf 80
+UTF32: 00040fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 80 bf bf
+UTF32: 00040fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf 80 80
+UTF32: 0007f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf 80 bf
+UTF32: 0007f03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf bf 80
+UTF32: 0007ffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f1 bf bf bf
+UTF32: 0007ffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 80 80
+UTF32: 00080000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 80 bf
+UTF32: 0008003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 bf 80
+UTF32: 00080fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 80 bf bf
+UTF32: 00080fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf 80 80
+UTF32: 000bf000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf 80 bf
+UTF32: 000bf03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf bf 80
+UTF32: 000bffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f2 bf bf bf
+UTF32: 000bffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 80 80
+UTF32: 000c0000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 80 bf
+UTF32: 000c003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 bf 80
+UTF32: 000c0fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 80 bf bf
+UTF32: 000c0fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf 80 80
+UTF32: 000ff000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf 80 bf
+UTF32: 000ff03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf bf 80
+UTF32: 000fffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f3 bf bf bf
+UTF32: 000fffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 80 80
+UTF32: 00100000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 80 bf
+UTF32: 0010003f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 bf 80
+UTF32: 00100fc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 80 bf bf
+UTF32: 00100fff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f 80 80
+UTF32: 0010f000
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f 80 bf
+UTF32: 0010f03f
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f bf 80
+UTF32: 0010ffc0
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF8: f4 8f bf bf
+UTF32: 0010ffff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+
+----- Valid characters if m3 == 0 -----
+UTF8: f5 00 00 00 f6 11 22 33 f7 44 55 66
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 12
+
+----- Invalid characters (2nd byte is invalid) -----
+UTF8: f0 8f 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f0 c0 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 7f 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 90 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 7f 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 c0 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 7f 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 c0 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 7f 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 c0 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+
+----- Invalid characters (3rd byte is invalid) -----
+UTF8: f0 94 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f0 94 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 84 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 84 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 84 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 84 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 84 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 84 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 84 7f 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 84 c0 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+
+----- Invalid characters (4th byte is invalid) -----
+UTF8: f0 94 80 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f0 94 80 c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 84 80 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f1 84 80 c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 84 80 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f2 84 80 c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 84 80 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f3 84 80 c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 84 80 7f
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF8: f4 84 80 c0
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+
+----- Invalid 2nd char AND output exhausted -----
+UTF8: f0 00 80 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1
+ src address difference: 0 src len: 4
+
+----- Invalid 3rd char AND output exhausted -----
+UTF8: f0 aa 00 80
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 3
+ src address difference: 0 src len: 4
+
+----- Invalid 4th char AND output exhausted -----
+UTF8: f0 aa aa 00
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 3
+ src address difference: 0 src len: 4
+
+----- 1st char valid, 2nd char invalid -----
+UTF8: f0 aa aa aa f0 00 00 00
+UTF32: 0002aaaa
+ cc = 2
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 4
+
+------------- test1 ----------------
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src len: 0
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: c2
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: e1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: e1 80
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: <none>
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF8: f4
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF8: f4 80
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF8: f4 80 80
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF8: 00 01
+UTF32: 00000000 00000001
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 2 src len: 0
+UTF8: c2 80 c2 81 c2
+UTF32: 00000080 00000081
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 4 src len: 1
+UTF8: e1 80 80 e1 80 81
+UTF32: 00001000 00001001
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 6 src len: 0
+UTF8: f4 80 80 80 f4 80 80 81 f4
+UTF32: 00100000 00100001
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 8 src len: 1
+
+------------- test3.1 ----------------
+UTF8: 00 01 02 03
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 4
+UTF8: c2 80 c2 81 c2 82 c2 83
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 8
+UTF8: c2 80 c2 81 c2 82 c2 83
+UTF32: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 8
+UTF8: e1 80 80 e1 80 81 e1 80 82 e1 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 12
+UTF8: e1 80 80 e1 80 81 e1 80 82 e1 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 12
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 16
+UTF8: f4 80 80 80 f4 80 80 81 f4 80 80 82 f4 80 80 83
+UTF32: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 16
+
+------------- test3.2 ----------------
+UTF8: 00 01 02 03
+UTF32: 00000000
+ cc = 1
+ dst address difference: 4 dst len: 0
+ src address difference: 1 src len: 3
+UTF8: 00 01 02 03 c2 80 c2 81
+UTF32: 00000000
+ cc = 1
+ dst address difference: 4 dst len: 1
+ src address difference: 1 src len: 7
+UTF8: 00 01 02 03 c2 80 c2 81 c2 82 c2 83
+UTF32: 00000000
+ cc = 1
+ dst address difference: 4 dst len: 2
+ src address difference: 1 src len: 11
+UTF8: 00 01 02 03 c2 80 c2 81 c2 82 c2 83 e1 80 80 e1
+UTF32: 00000000
+ cc = 1
+ dst address difference: 4 dst len: 3
+ src address difference: 1 src len: 15
+
+------------- test4 ----------------
+UTF8: 01 c3 80 12 e1 90 93 23 f4 80 90 8a 34 c4 8c e1 91 94 c5 8a f4 80 90 8a c5 8a e1 91 94 f4 80 90 8a e1 91 94
+UTF32: 00000001 000000c0 00000012 00001413 00000023 0010040a 00000034 0000010c 00001454 0000014a 0010040a 0000014a 00001454 0010040a 00001454
+ cc = 0
+ dst address difference: 60 dst len: 1940
+ src address difference: 36 src len: 0
diff --git a/main/none/tests/s390x/cu14_1.vgtest b/main/none/tests/s390x/cu14_1.vgtest
new file mode 100644
index 0000000..330a2cf
--- /dev/null
+++ b/main/none/tests/s390x/cu14_1.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/s390x_features s390x-etf3
+prog: cu14_1
diff --git a/main/none/tests/s390x/cu21.c b/main/none/tests/s390x/cu21.c
new file mode 100644
index 0000000..d2d1f11
--- /dev/null
+++ b/main/none/tests/s390x/cu21.c
@@ -0,0 +1,270 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU21 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu21_t;
+
+/* Define various input buffers. */
+
+/* U+0000 to U+007f: Result is 1 byte for each uint16_t */
+uint16_t pattern1[] = {
+ 0x0000, 0x007f, /* corner cases */
+ 0x0047, 0x0056, 0x0045, 0x0021, 0x007b, 0x003a /* misc */
+};
+
+/* U+0080 to U+07ff: Result is 2 bytes for each uint16_t */
+uint16_t pattern2[] = {
+ 0x0080, 0x07ff, /* corner cases */
+ 0x07df, 0x008f, 0x0100, 0x017f, 0x052f, 0x0600, 0x06ff /* misc */
+};
+
+/* U+0800 to U+d7ff: Result is 3 bytes for each uint16_t
+ U+dc00 to U+ffff: Result is 3 bytes for each uint16_t */
+uint16_t pattern3[] = {
+ 0x0800, 0xd7ff, /* corner cases */
+ 0xdc00, 0xffff, /* corner cases */
+ 0x083f, 0x1a21, 0x1b10, 0x2200, 0x225e, 0x22c9, 0xe001 /* misc */
+};
+
+/* U+d800 to U+dbff: Result is 4 bytes for each uint16_t pair */
+uint16_t pattern4[] = {
+ 0xd800, 0xdc00, /* left corner case */
+ 0xdbff, 0xdfff, /* right corner case */
+ 0xdada, 0xdddd, 0xdeaf, 0xdcdc /* misc */
+};
+
+/* Invalid low surrogate */
+uint16_t invalid[] = { 0xd801, 0x0098 };
+
+/* Mixed bytes */
+uint16_t mixed[] = {
+ 0x0078 /* 1 byte */,
+ 0x0200 /* 2 bytes */,
+ 0xffff /* 3 bytes */,
+ 0xd800, 0xdc01 /* 4 bytes */
+};
+
+/* This is the buffer for the converted bytes. */
+uint8_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+void write_and_check(uint16_t *, unsigned, unsigned);
+
+
+static cu21_t
+do_cu21(uint8_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu21_t regs;
+
+ /* build up the register pairs */
+ register uint16_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint8_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU21(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu21 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint8_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int i;
+ cu21_t result;
+
+ result = do_cu21(dst, dst_len, src, src_len);
+
+ // Write out the converted bytes, if any
+ printf("UTF8: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else
+ for (i = 0; i < dst_len - result.len1; i++) {
+ printf(" %02x", dst[i]);
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+int main()
+{
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 1);
+ run_test(buff, sizeof buff, pattern1, 1);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern3, 1);
+ run_test(buff, sizeof buff, pattern4, 1);
+ run_test(buff, sizeof buff, pattern4, 2);
+ run_test(buff, sizeof buff, pattern4, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 3);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern3, 7);
+ run_test(buff, sizeof buff, pattern4, 9);
+ run_test(buff, sizeof buff, pattern4, 10);
+ run_test(buff, sizeof buff, pattern4, 11);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write a single byte */
+ run_test(NULL, 0, pattern1, sizeof pattern1);
+
+ /* Want to write two bytes */
+ run_test(NULL, 0, pattern2, sizeof pattern2);
+ run_test(NULL, 1, pattern2, sizeof pattern2);
+
+ /* Want to write three bytes */
+ run_test(NULL, 0, pattern3, sizeof pattern3);
+ run_test(NULL, 1, pattern3, sizeof pattern3);
+ run_test(NULL, 2, pattern3, sizeof pattern3);
+
+ /* Want to write four bytes */
+ run_test(NULL, 0, pattern4, sizeof pattern4);
+ run_test(NULL, 1, pattern4, sizeof pattern4);
+ run_test(NULL, 2, pattern4, sizeof pattern4);
+ run_test(NULL, 3, pattern4, sizeof pattern4);
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 3, pattern1, sizeof pattern1);
+
+ run_test(buff, 5, pattern2, sizeof pattern2);
+
+ run_test(buff, 7, pattern3, sizeof pattern3);
+ run_test(buff, 8, pattern3, sizeof pattern3);
+
+ run_test(buff, 9, pattern4, sizeof pattern4);
+ run_test(buff, 10, pattern4, sizeof pattern4);
+ run_test(buff, 11, pattern4, sizeof pattern4);
+
+ /* When both operands are exhausted, cc=0 takes precedence.
+ (test1 tests this for len == 0) */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, 6, pattern1, 6);
+
+ /* Input has invalid low surrogate. */
+ printf("\n------------- test5 ----------------\n");
+ run_test(buff, sizeof buff, invalid, sizeof invalid);
+ run_test(buff, 0, invalid, sizeof invalid);
+
+ /* Convert all pattern buffers */
+ printf("\n------------- test6 ----------------\n");
+ run_test(buff, sizeof buff, pattern1, sizeof pattern1);
+ run_test(buff, sizeof buff, pattern2, sizeof pattern2);
+ run_test(buff, sizeof buff, pattern3, sizeof pattern3);
+ run_test(buff, sizeof buff, pattern4, sizeof pattern4);
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ /* Make sure we only write the exact number of bytes (and not more) */
+ uint16_t pat[2];
+
+ /* Write 1 byte */
+ printf("\n------------- test7.1 ----------------\n");
+ pat[0] = 0x10;
+ write_and_check(pat, 2, 1);
+
+ /* Write 2 bytes */
+ printf("\n------------- test7.2 ----------------\n");
+ pat[0] = 0x8f;
+ write_and_check(pat, 2, 2);
+
+ /* Write 3 bytes */
+ printf("\n------------- test7.3 ----------------\n");
+ pat[0] = 0x842;
+ write_and_check(pat, 2, 3);
+
+ /* Write 4 bytes */
+ printf("\n------------- test7.4 ----------------\n");
+ pat[0] = 0xd842;
+ pat[1] = 0xdc42;
+ write_and_check(pat, 2, 4);
+
+ return 0;
+}
+
+
+void
+write_and_check_aux(uint16_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes,
+ unsigned fill_byte)
+{
+ int num_errors, i;
+
+ /* Fill output buffer with FILL_BYTE */
+ memset(buff, fill_byte, sizeof buff);
+
+ /* Execute cu21 */
+ run_test(buff, sizeof buff, input, num_input_bytes);
+
+ /* Make sure the rest of the buffer is unmodified. */
+ num_errors = 0;
+ for (i = num_expected_output_bytes; i < sizeof buff; ++i)
+ if (buff[i] != fill_byte) ++num_errors;
+ if (num_errors)
+ fprintf(stderr, "*** wrote more than %u bytes\n",
+ num_expected_output_bytes);
+}
+
+void
+write_and_check(uint16_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes)
+{
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0x0);
+
+ /* Run again with different fill pattern to make sure we did not write
+ an extra 0x0 byte */
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0xFF);
+}
diff --git a/main/none/tests/s390x/cu21.stderr.exp b/main/none/tests/s390x/cu21.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu21.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu21.stdout.exp b/main/none/tests/s390x/cu21.stdout.exp
new file mode 100644
index 0000000..1119f20
--- /dev/null
+++ b/main/none/tests/s390x/cu21.stdout.exp
@@ -0,0 +1,212 @@
+
+------------- test1 ----------------
+UTF8: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 2
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF8: 00
+ cc = 0
+ dst address difference: 1 dst len: 999
+ src address difference: 2 src len: 1
+UTF8: c2 80 df bf
+ cc = 0
+ dst address difference: 4 dst len: 996
+ src address difference: 4 src len: 1
+UTF8: e0 a0 80 ed 9f bf ed b0 80
+ cc = 0
+ dst address difference: 9 dst len: 991
+ src address difference: 6 src len: 1
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 0
+ dst address difference: 8 dst len: 992
+ src address difference: 8 src len: 1
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 0
+ dst address difference: 8 dst len: 992
+ src address difference: 8 src len: 2
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 0
+ dst address difference: 8 dst len: 992
+ src address difference: 8 src len: 3
+
+------------- test3.1 ----------------
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 16
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 18
+UTF8: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 18
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 22
+UTF8: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 22
+UTF8: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 22
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 16
+UTF8: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 16
+UTF8: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 16
+UTF8: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 16
+
+------------- test3.2 ----------------
+UTF8: 00 7f 47
+ cc = 1
+ dst address difference: 3 dst len: 0
+ src address difference: 6 src len: 10
+UTF8: c2 80 df bf
+ cc = 1
+ dst address difference: 4 dst len: 1
+ src address difference: 4 src len: 14
+UTF8: e0 a0 80 ed 9f bf
+ cc = 1
+ dst address difference: 6 dst len: 1
+ src address difference: 4 src len: 18
+UTF8: e0 a0 80 ed 9f bf
+ cc = 1
+ dst address difference: 6 dst len: 2
+ src address difference: 4 src len: 18
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 1
+ dst address difference: 8 dst len: 1
+ src address difference: 8 src len: 8
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 1
+ dst address difference: 8 dst len: 2
+ src address difference: 8 src len: 8
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 1
+ dst address difference: 8 dst len: 3
+ src address difference: 8 src len: 8
+
+------------- test4 ----------------
+UTF8: 00 7f 47
+ cc = 0
+ dst address difference: 3 dst len: 3
+ src address difference: 6 src len: 0
+
+------------- test5 ----------------
+UTF8: f0 90 92 98
+ cc = 0
+ dst address difference: 4 dst len: 996
+ src address difference: 4 src len: 0
+UTF8: <none>
+ cc = 1
+ dst address difference: 0 dst len: 0
+ src address difference: 0 src len: 4
+
+------------- test6 ----------------
+UTF8: 00 7f 47 56 45 21 7b 3a
+ cc = 0
+ dst address difference: 8 dst len: 992
+ src address difference: 16 src len: 0
+UTF8: c2 80 df bf df 9f c2 8f c4 80 c5 bf d4 af d8 80 db bf
+ cc = 0
+ dst address difference: 18 dst len: 982
+ src address difference: 18 src len: 0
+UTF8: e0 a0 80 ed 9f bf ed b0 80 ef bf bf e0 a0 bf e1 a8 a1 e1 ac 90 e2 88 80 e2 89 9e e2 8b 89 ee 80 81
+ cc = 0
+ dst address difference: 33 dst len: 967
+ src address difference: 22 src len: 0
+UTF8: f0 90 80 80 f4 8f bf bf f3 86 a7 9d ed ba af ed b3 9c
+ cc = 0
+ dst address difference: 18 dst len: 982
+ src address difference: 16 src len: 0
+UTF8: 78 c8 80 ef bf bf f0 90 80 81
+ cc = 0
+ dst address difference: 10 dst len: 990
+ src address difference: 10 src len: 0
+
+------------- test7.1 ----------------
+UTF8: 10
+ cc = 0
+ dst address difference: 1 dst len: 999
+ src address difference: 2 src len: 0
+UTF8: 10
+ cc = 0
+ dst address difference: 1 dst len: 999
+ src address difference: 2 src len: 0
+
+------------- test7.2 ----------------
+UTF8: c2 8f
+ cc = 0
+ dst address difference: 2 dst len: 998
+ src address difference: 2 src len: 0
+UTF8: c2 8f
+ cc = 0
+ dst address difference: 2 dst len: 998
+ src address difference: 2 src len: 0
+
+------------- test7.3 ----------------
+UTF8: e0 a1 82
+ cc = 0
+ dst address difference: 3 dst len: 997
+ src address difference: 2 src len: 0
+UTF8: e0 a1 82
+ cc = 0
+ dst address difference: 3 dst len: 997
+ src address difference: 2 src len: 0
+
+------------- test7.4 ----------------
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 2
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 2
diff --git a/main/none/tests/s390x/cu21.vgtest b/main/none/tests/s390x/cu21.vgtest
new file mode 100644
index 0000000..39bb6c6
--- /dev/null
+++ b/main/none/tests/s390x/cu21.vgtest
@@ -0,0 +1 @@
+prog: cu21
diff --git a/main/none/tests/s390x/cu21_1.c b/main/none/tests/s390x/cu21_1.c
new file mode 100644
index 0000000..d2d1f11
--- /dev/null
+++ b/main/none/tests/s390x/cu21_1.c
@@ -0,0 +1,270 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU21 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu21_t;
+
+/* Define various input buffers. */
+
+/* U+0000 to U+007f: Result is 1 byte for each uint16_t */
+uint16_t pattern1[] = {
+ 0x0000, 0x007f, /* corner cases */
+ 0x0047, 0x0056, 0x0045, 0x0021, 0x007b, 0x003a /* misc */
+};
+
+/* U+0080 to U+07ff: Result is 2 bytes for each uint16_t */
+uint16_t pattern2[] = {
+ 0x0080, 0x07ff, /* corner cases */
+ 0x07df, 0x008f, 0x0100, 0x017f, 0x052f, 0x0600, 0x06ff /* misc */
+};
+
+/* U+0800 to U+d7ff: Result is 3 bytes for each uint16_t
+ U+dc00 to U+ffff: Result is 3 bytes for each uint16_t */
+uint16_t pattern3[] = {
+ 0x0800, 0xd7ff, /* corner cases */
+ 0xdc00, 0xffff, /* corner cases */
+ 0x083f, 0x1a21, 0x1b10, 0x2200, 0x225e, 0x22c9, 0xe001 /* misc */
+};
+
+/* U+d800 to U+dbff: Result is 4 bytes for each uint16_t pair */
+uint16_t pattern4[] = {
+ 0xd800, 0xdc00, /* left corner case */
+ 0xdbff, 0xdfff, /* right corner case */
+ 0xdada, 0xdddd, 0xdeaf, 0xdcdc /* misc */
+};
+
+/* Invalid low surrogate */
+uint16_t invalid[] = { 0xd801, 0x0098 };
+
+/* Mixed bytes */
+uint16_t mixed[] = {
+ 0x0078 /* 1 byte */,
+ 0x0200 /* 2 bytes */,
+ 0xffff /* 3 bytes */,
+ 0xd800, 0xdc01 /* 4 bytes */
+};
+
+/* This is the buffer for the converted bytes. */
+uint8_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+void write_and_check(uint16_t *, unsigned, unsigned);
+
+
+static cu21_t
+do_cu21(uint8_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu21_t regs;
+
+ /* build up the register pairs */
+ register uint16_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint8_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU21(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu21 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint8_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int i;
+ cu21_t result;
+
+ result = do_cu21(dst, dst_len, src, src_len);
+
+ // Write out the converted bytes, if any
+ printf("UTF8: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else
+ for (i = 0; i < dst_len - result.len1; i++) {
+ printf(" %02x", dst[i]);
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+int main()
+{
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 1);
+ run_test(buff, sizeof buff, pattern1, 1);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern3, 1);
+ run_test(buff, sizeof buff, pattern4, 1);
+ run_test(buff, sizeof buff, pattern4, 2);
+ run_test(buff, sizeof buff, pattern4, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 3);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern3, 7);
+ run_test(buff, sizeof buff, pattern4, 9);
+ run_test(buff, sizeof buff, pattern4, 10);
+ run_test(buff, sizeof buff, pattern4, 11);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write a single byte */
+ run_test(NULL, 0, pattern1, sizeof pattern1);
+
+ /* Want to write two bytes */
+ run_test(NULL, 0, pattern2, sizeof pattern2);
+ run_test(NULL, 1, pattern2, sizeof pattern2);
+
+ /* Want to write three bytes */
+ run_test(NULL, 0, pattern3, sizeof pattern3);
+ run_test(NULL, 1, pattern3, sizeof pattern3);
+ run_test(NULL, 2, pattern3, sizeof pattern3);
+
+ /* Want to write four bytes */
+ run_test(NULL, 0, pattern4, sizeof pattern4);
+ run_test(NULL, 1, pattern4, sizeof pattern4);
+ run_test(NULL, 2, pattern4, sizeof pattern4);
+ run_test(NULL, 3, pattern4, sizeof pattern4);
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 3, pattern1, sizeof pattern1);
+
+ run_test(buff, 5, pattern2, sizeof pattern2);
+
+ run_test(buff, 7, pattern3, sizeof pattern3);
+ run_test(buff, 8, pattern3, sizeof pattern3);
+
+ run_test(buff, 9, pattern4, sizeof pattern4);
+ run_test(buff, 10, pattern4, sizeof pattern4);
+ run_test(buff, 11, pattern4, sizeof pattern4);
+
+ /* When both operands are exhausted, cc=0 takes precedence.
+ (test1 tests this for len == 0) */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, 6, pattern1, 6);
+
+ /* Input has invalid low surrogate. */
+ printf("\n------------- test5 ----------------\n");
+ run_test(buff, sizeof buff, invalid, sizeof invalid);
+ run_test(buff, 0, invalid, sizeof invalid);
+
+ /* Convert all pattern buffers */
+ printf("\n------------- test6 ----------------\n");
+ run_test(buff, sizeof buff, pattern1, sizeof pattern1);
+ run_test(buff, sizeof buff, pattern2, sizeof pattern2);
+ run_test(buff, sizeof buff, pattern3, sizeof pattern3);
+ run_test(buff, sizeof buff, pattern4, sizeof pattern4);
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ /* Make sure we only write the exact number of bytes (and not more) */
+ uint16_t pat[2];
+
+ /* Write 1 byte */
+ printf("\n------------- test7.1 ----------------\n");
+ pat[0] = 0x10;
+ write_and_check(pat, 2, 1);
+
+ /* Write 2 bytes */
+ printf("\n------------- test7.2 ----------------\n");
+ pat[0] = 0x8f;
+ write_and_check(pat, 2, 2);
+
+ /* Write 3 bytes */
+ printf("\n------------- test7.3 ----------------\n");
+ pat[0] = 0x842;
+ write_and_check(pat, 2, 3);
+
+ /* Write 4 bytes */
+ printf("\n------------- test7.4 ----------------\n");
+ pat[0] = 0xd842;
+ pat[1] = 0xdc42;
+ write_and_check(pat, 2, 4);
+
+ return 0;
+}
+
+
+void
+write_and_check_aux(uint16_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes,
+ unsigned fill_byte)
+{
+ int num_errors, i;
+
+ /* Fill output buffer with FILL_BYTE */
+ memset(buff, fill_byte, sizeof buff);
+
+ /* Execute cu21 */
+ run_test(buff, sizeof buff, input, num_input_bytes);
+
+ /* Make sure the rest of the buffer is unmodified. */
+ num_errors = 0;
+ for (i = num_expected_output_bytes; i < sizeof buff; ++i)
+ if (buff[i] != fill_byte) ++num_errors;
+ if (num_errors)
+ fprintf(stderr, "*** wrote more than %u bytes\n",
+ num_expected_output_bytes);
+}
+
+void
+write_and_check(uint16_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes)
+{
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0x0);
+
+ /* Run again with different fill pattern to make sure we did not write
+ an extra 0x0 byte */
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0xFF);
+}
diff --git a/main/none/tests/s390x/cu21_1.stderr.exp b/main/none/tests/s390x/cu21_1.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu21_1.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu21_1.stdout.exp b/main/none/tests/s390x/cu21_1.stdout.exp
new file mode 100644
index 0000000..95a829f
--- /dev/null
+++ b/main/none/tests/s390x/cu21_1.stdout.exp
@@ -0,0 +1,212 @@
+
+------------- test1 ----------------
+UTF8: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 2
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF8: 00
+ cc = 0
+ dst address difference: 1 dst len: 999
+ src address difference: 2 src len: 1
+UTF8: c2 80 df bf
+ cc = 0
+ dst address difference: 4 dst len: 996
+ src address difference: 4 src len: 1
+UTF8: e0 a0 80 ed 9f bf ed b0 80
+ cc = 0
+ dst address difference: 9 dst len: 991
+ src address difference: 6 src len: 1
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 0
+ dst address difference: 8 dst len: 992
+ src address difference: 8 src len: 1
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 0
+ dst address difference: 8 dst len: 992
+ src address difference: 8 src len: 2
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 0
+ dst address difference: 8 dst len: 992
+ src address difference: 8 src len: 3
+
+------------- test3.1 ----------------
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 16
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 18
+UTF8: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 18
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 22
+UTF8: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 22
+UTF8: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 22
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 16
+UTF8: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 16
+UTF8: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 16
+UTF8: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 16
+
+------------- test3.2 ----------------
+UTF8: 00 7f 47
+ cc = 1
+ dst address difference: 3 dst len: 0
+ src address difference: 6 src len: 10
+UTF8: c2 80 df bf
+ cc = 1
+ dst address difference: 4 dst len: 1
+ src address difference: 4 src len: 14
+UTF8: e0 a0 80 ed 9f bf
+ cc = 1
+ dst address difference: 6 dst len: 1
+ src address difference: 4 src len: 18
+UTF8: e0 a0 80 ed 9f bf
+ cc = 1
+ dst address difference: 6 dst len: 2
+ src address difference: 4 src len: 18
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 1
+ dst address difference: 8 dst len: 1
+ src address difference: 8 src len: 8
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 1
+ dst address difference: 8 dst len: 2
+ src address difference: 8 src len: 8
+UTF8: f0 90 80 80 f4 8f bf bf
+ cc = 1
+ dst address difference: 8 dst len: 3
+ src address difference: 8 src len: 8
+
+------------- test4 ----------------
+UTF8: 00 7f 47
+ cc = 0
+ dst address difference: 3 dst len: 3
+ src address difference: 6 src len: 0
+
+------------- test5 ----------------
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 0
+ src address difference: 0 src len: 4
+
+------------- test6 ----------------
+UTF8: 00 7f 47 56 45 21 7b 3a
+ cc = 0
+ dst address difference: 8 dst len: 992
+ src address difference: 16 src len: 0
+UTF8: c2 80 df bf df 9f c2 8f c4 80 c5 bf d4 af d8 80 db bf
+ cc = 0
+ dst address difference: 18 dst len: 982
+ src address difference: 18 src len: 0
+UTF8: e0 a0 80 ed 9f bf ed b0 80 ef bf bf e0 a0 bf e1 a8 a1 e1 ac 90 e2 88 80 e2 89 9e e2 8b 89 ee 80 81
+ cc = 0
+ dst address difference: 33 dst len: 967
+ src address difference: 22 src len: 0
+UTF8: f0 90 80 80 f4 8f bf bf f3 86 a7 9d ed ba af ed b3 9c
+ cc = 0
+ dst address difference: 18 dst len: 982
+ src address difference: 16 src len: 0
+UTF8: 78 c8 80 ef bf bf f0 90 80 81
+ cc = 0
+ dst address difference: 10 dst len: 990
+ src address difference: 10 src len: 0
+
+------------- test7.1 ----------------
+UTF8: 10
+ cc = 0
+ dst address difference: 1 dst len: 999
+ src address difference: 2 src len: 0
+UTF8: 10
+ cc = 0
+ dst address difference: 1 dst len: 999
+ src address difference: 2 src len: 0
+
+------------- test7.2 ----------------
+UTF8: c2 8f
+ cc = 0
+ dst address difference: 2 dst len: 998
+ src address difference: 2 src len: 0
+UTF8: c2 8f
+ cc = 0
+ dst address difference: 2 dst len: 998
+ src address difference: 2 src len: 0
+
+------------- test7.3 ----------------
+UTF8: e0 a1 82
+ cc = 0
+ dst address difference: 3 dst len: 997
+ src address difference: 2 src len: 0
+UTF8: e0 a1 82
+ cc = 0
+ dst address difference: 3 dst len: 997
+ src address difference: 2 src len: 0
+
+------------- test7.4 ----------------
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 2
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 2
diff --git a/main/none/tests/s390x/cu21_1.vgtest b/main/none/tests/s390x/cu21_1.vgtest
new file mode 100644
index 0000000..153c7a4
--- /dev/null
+++ b/main/none/tests/s390x/cu21_1.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/s390x_features s390x-etf3
+prog: cu21_1
diff --git a/main/none/tests/s390x/cu24.c b/main/none/tests/s390x/cu24.c
new file mode 100644
index 0000000..2cd8828
--- /dev/null
+++ b/main/none/tests/s390x/cu24.c
@@ -0,0 +1,183 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU24 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu24_t;
+
+/* Define various input buffers. */
+
+/* Single UTF-16 value */
+uint16_t pattern1[] = {
+ 0x0000, 0xd7ff, /* [0000 ... d7ff] corner cases */
+ 0xdc00, 0xffff, /* [dc00 ... ffff] corner cases */
+ 0x0047, 0x0156, 0x1245, 0xa021, 0xfffe /* misc */
+};
+
+/* UTF-16 surrogate pair */
+uint16_t pattern2[] = {
+ 0xd800, 0xdc00, /* left corner case */
+ 0xdbff, 0xdfff, /* right corner case */
+ 0xdada, 0xdddd, 0xdeaf, 0xdcdc /* misc */
+};
+
+/* Invalid low surrogate */
+uint16_t invalid[] = { 0xd801, 0x0098 };
+
+/* Mixed bytes */
+uint16_t mixed[] = {
+ 0x0078,
+ 0x0200,
+ 0xffff,
+ 0xd800, 0xdc01,
+ 0xde00, 0xdd00,
+ 0xc0c0
+};
+
+/* This is the buffer for the converted bytes. */
+uint32_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+
+static cu24_t
+do_cu24(uint32_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu24_t regs;
+
+ /* build up the register pairs */
+ register uint16_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint32_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU24(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu24 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint32_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int i;
+ cu24_t result;
+
+ result = do_cu24(dst, dst_len, src, src_len);
+
+ // Write out the converted byte, if any
+ printf("UTF32: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else {
+ uint64_t num_bytes = dst_len - result.len1;
+
+ /* The number of bytes that were written must be divisible by 4 */
+ if (num_bytes % 4 != 0)
+ fprintf(stderr, "*** number of bytes is not a multiple of 4\n");
+
+ for (i = 0; i < num_bytes / 4; i++) {
+ printf(" %02x", dst[i]);
+ }
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+int main()
+{
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 1);
+ run_test(buff, sizeof buff, pattern1, 1);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern2, 2);
+ run_test(buff, sizeof buff, pattern2, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 3);
+ run_test(buff, sizeof buff, pattern1, 5);
+ run_test(buff, sizeof buff, pattern2, 2);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern2, 7);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write 4 bytes at a time */
+ run_test(NULL, 0, pattern1, sizeof pattern1);
+ run_test(NULL, 1, pattern1, sizeof pattern1);
+ run_test(NULL, 2, pattern1, sizeof pattern1);
+ run_test(NULL, 3, pattern1, sizeof pattern1);
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 4, pattern1, sizeof pattern1);
+ run_test(buff, 5, pattern1, sizeof pattern1);
+ run_test(buff, 6, pattern1, sizeof pattern1);
+ run_test(buff, 7, pattern1, sizeof pattern1);
+
+ /* When both operands are exhausted, cc=0 takes precedence.
+ (test1 tests this for len == 0) */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, 4, pattern1, 2); // no iteration
+ run_test(buff, 8, pattern1, 4); // iteration
+
+ /* Input has invalid low surrogate. */
+ printf("\n------------- test5 ----------------\n");
+ run_test(buff, sizeof buff, invalid, sizeof invalid);
+ run_test(buff, 0, invalid, sizeof invalid);
+
+ /* Convert all pattern buffers */
+ printf("\n------------- test6 ----------------\n");
+ run_test(buff, sizeof buff, pattern1, sizeof pattern1);
+ run_test(buff, sizeof buff, pattern2, sizeof pattern2);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cu24.stderr.exp b/main/none/tests/s390x/cu24.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu24.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu24.stdout.exp b/main/none/tests/s390x/cu24.stdout.exp
new file mode 100644
index 0000000..d29f4dd
--- /dev/null
+++ b/main/none/tests/s390x/cu24.stdout.exp
@@ -0,0 +1,116 @@
+
+------------- test1 ----------------
+UTF32: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src len: 1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 2
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF32: 00
+ cc = 0
+ dst address difference: 4 dst len: 3996
+ src address difference: 2 src len: 1
+UTF32: 00 d7ff
+ cc = 0
+ dst address difference: 8 dst len: 3992
+ src address difference: 4 src len: 1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 2
+UTF32: 10000
+ cc = 0
+ dst address difference: 4 dst len: 3996
+ src address difference: 4 src len: 1
+UTF32: 10000
+ cc = 0
+ dst address difference: 4 dst len: 3996
+ src address difference: 4 src len: 3
+
+------------- test3.1 ----------------
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 18
+UTF32: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 18
+UTF32: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 18
+UTF32: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 18
+
+------------- test3.2 ----------------
+UTF32: 00
+ cc = 1
+ dst address difference: 4 dst len: 0
+ src address difference: 2 src len: 16
+UTF32: 00
+ cc = 1
+ dst address difference: 4 dst len: 1
+ src address difference: 2 src len: 16
+UTF32: 00
+ cc = 1
+ dst address difference: 4 dst len: 2
+ src address difference: 2 src len: 16
+UTF32: 00
+ cc = 1
+ dst address difference: 4 dst len: 3
+ src address difference: 2 src len: 16
+
+------------- test4 ----------------
+UTF32: 00
+ cc = 0
+ dst address difference: 4 dst len: 0
+ src address difference: 2 src len: 0
+UTF32: 00 d7ff
+ cc = 0
+ dst address difference: 8 dst len: 0
+ src address difference: 4 src len: 0
+
+------------- test5 ----------------
+UTF32: 10498
+ cc = 0
+ dst address difference: 4 dst len: 3996
+ src address difference: 4 src len: 0
+UTF32: <none>
+ cc = 1
+ dst address difference: 0 dst len: 0
+ src address difference: 0 src len: 4
+
+------------- test6 ----------------
+UTF32: 00 d7ff dc00 ffff 47 156 1245 a021 fffe
+ cc = 0
+ dst address difference: 36 dst len: 3964
+ src address difference: 18 src len: 0
+UTF32: 10000 10ffff c69dd deaf dcdc
+ cc = 0
+ dst address difference: 20 dst len: 3980
+ src address difference: 16 src len: 0
diff --git a/main/none/tests/s390x/cu24.vgtest b/main/none/tests/s390x/cu24.vgtest
new file mode 100644
index 0000000..a130e91
--- /dev/null
+++ b/main/none/tests/s390x/cu24.vgtest
@@ -0,0 +1 @@
+prog: cu24
diff --git a/main/none/tests/s390x/cu24_1.c b/main/none/tests/s390x/cu24_1.c
new file mode 100644
index 0000000..2cd8828
--- /dev/null
+++ b/main/none/tests/s390x/cu24_1.c
@@ -0,0 +1,183 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU24 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu24_t;
+
+/* Define various input buffers. */
+
+/* Single UTF-16 value */
+uint16_t pattern1[] = {
+ 0x0000, 0xd7ff, /* [0000 ... d7ff] corner cases */
+ 0xdc00, 0xffff, /* [dc00 ... ffff] corner cases */
+ 0x0047, 0x0156, 0x1245, 0xa021, 0xfffe /* misc */
+};
+
+/* UTF-16 surrogate pair */
+uint16_t pattern2[] = {
+ 0xd800, 0xdc00, /* left corner case */
+ 0xdbff, 0xdfff, /* right corner case */
+ 0xdada, 0xdddd, 0xdeaf, 0xdcdc /* misc */
+};
+
+/* Invalid low surrogate */
+uint16_t invalid[] = { 0xd801, 0x0098 };
+
+/* Mixed bytes */
+uint16_t mixed[] = {
+ 0x0078,
+ 0x0200,
+ 0xffff,
+ 0xd800, 0xdc01,
+ 0xde00, 0xdd00,
+ 0xc0c0
+};
+
+/* This is the buffer for the converted bytes. */
+uint32_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+
+static cu24_t
+do_cu24(uint32_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu24_t regs;
+
+ /* build up the register pairs */
+ register uint16_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint32_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU24(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu24 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint32_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int i;
+ cu24_t result;
+
+ result = do_cu24(dst, dst_len, src, src_len);
+
+ // Write out the converted byte, if any
+ printf("UTF32: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else {
+ uint64_t num_bytes = dst_len - result.len1;
+
+ /* The number of bytes that were written must be divisible by 4 */
+ if (num_bytes % 4 != 0)
+ fprintf(stderr, "*** number of bytes is not a multiple of 4\n");
+
+ for (i = 0; i < num_bytes / 4; i++) {
+ printf(" %02x", dst[i]);
+ }
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+int main()
+{
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 1);
+ run_test(buff, sizeof buff, pattern1, 1);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern2, 2);
+ run_test(buff, sizeof buff, pattern2, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 3);
+ run_test(buff, sizeof buff, pattern1, 5);
+ run_test(buff, sizeof buff, pattern2, 2);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern2, 7);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write 4 bytes at a time */
+ run_test(NULL, 0, pattern1, sizeof pattern1);
+ run_test(NULL, 1, pattern1, sizeof pattern1);
+ run_test(NULL, 2, pattern1, sizeof pattern1);
+ run_test(NULL, 3, pattern1, sizeof pattern1);
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 4, pattern1, sizeof pattern1);
+ run_test(buff, 5, pattern1, sizeof pattern1);
+ run_test(buff, 6, pattern1, sizeof pattern1);
+ run_test(buff, 7, pattern1, sizeof pattern1);
+
+ /* When both operands are exhausted, cc=0 takes precedence.
+ (test1 tests this for len == 0) */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, 4, pattern1, 2); // no iteration
+ run_test(buff, 8, pattern1, 4); // iteration
+
+ /* Input has invalid low surrogate. */
+ printf("\n------------- test5 ----------------\n");
+ run_test(buff, sizeof buff, invalid, sizeof invalid);
+ run_test(buff, 0, invalid, sizeof invalid);
+
+ /* Convert all pattern buffers */
+ printf("\n------------- test6 ----------------\n");
+ run_test(buff, sizeof buff, pattern1, sizeof pattern1);
+ run_test(buff, sizeof buff, pattern2, sizeof pattern2);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/cu24_1.stderr.exp b/main/none/tests/s390x/cu24_1.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu24_1.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu24_1.stdout.exp b/main/none/tests/s390x/cu24_1.stdout.exp
new file mode 100644
index 0000000..c6e22d5
--- /dev/null
+++ b/main/none/tests/s390x/cu24_1.stdout.exp
@@ -0,0 +1,116 @@
+
+------------- test1 ----------------
+UTF32: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src len: 1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 2
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF32: 00
+ cc = 0
+ dst address difference: 4 dst len: 3996
+ src address difference: 2 src len: 1
+UTF32: 00 d7ff
+ cc = 0
+ dst address difference: 8 dst len: 3992
+ src address difference: 4 src len: 1
+UTF32: <none>
+ cc = 0
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 2
+UTF32: 10000
+ cc = 0
+ dst address difference: 4 dst len: 3996
+ src address difference: 4 src len: 1
+UTF32: 10000
+ cc = 0
+ dst address difference: 4 dst len: 3996
+ src address difference: 4 src len: 3
+
+------------- test3.1 ----------------
+UTF32: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 18
+UTF32: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 18
+UTF32: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 18
+UTF32: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 18
+
+------------- test3.2 ----------------
+UTF32: 00
+ cc = 1
+ dst address difference: 4 dst len: 0
+ src address difference: 2 src len: 16
+UTF32: 00
+ cc = 1
+ dst address difference: 4 dst len: 1
+ src address difference: 2 src len: 16
+UTF32: 00
+ cc = 1
+ dst address difference: 4 dst len: 2
+ src address difference: 2 src len: 16
+UTF32: 00
+ cc = 1
+ dst address difference: 4 dst len: 3
+ src address difference: 2 src len: 16
+
+------------- test4 ----------------
+UTF32: 00
+ cc = 0
+ dst address difference: 4 dst len: 0
+ src address difference: 2 src len: 0
+UTF32: 00 d7ff
+ cc = 0
+ dst address difference: 8 dst len: 0
+ src address difference: 4 src len: 0
+
+------------- test5 ----------------
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 4000
+ src address difference: 0 src len: 4
+UTF32: <none>
+ cc = 2
+ dst address difference: 0 dst len: 0
+ src address difference: 0 src len: 4
+
+------------- test6 ----------------
+UTF32: 00 d7ff dc00 ffff 47 156 1245 a021 fffe
+ cc = 0
+ dst address difference: 36 dst len: 3964
+ src address difference: 18 src len: 0
+UTF32: 10000 10ffff c69dd deaf dcdc
+ cc = 0
+ dst address difference: 20 dst len: 3980
+ src address difference: 16 src len: 0
diff --git a/main/none/tests/s390x/cu24_1.vgtest b/main/none/tests/s390x/cu24_1.vgtest
new file mode 100644
index 0000000..992ccdc
--- /dev/null
+++ b/main/none/tests/s390x/cu24_1.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/s390x_features s390x-etf3
+prog: cu24_1
diff --git a/main/none/tests/s390x/cu41.c b/main/none/tests/s390x/cu41.c
new file mode 100644
index 0000000..d6a2f7a
--- /dev/null
+++ b/main/none/tests/s390x/cu41.c
@@ -0,0 +1,259 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <assert.h>
+#include "opcodes.h"
+
+/* The abstracted result of an CU41 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu41_t;
+
+/* Define various input buffers. */
+
+/* 0000 to 00ff: Result is 1 byte for each uint32_t */
+uint32_t pattern1[] = {
+ 0x0000, 0x007f, /* corner cases */
+ 0x0001, 0x007e, 0x0030, 0x005e /* misc */
+};
+
+/* 0080 to 07ff: Result is 2 bytes for each uint32_t */
+uint32_t pattern2[] = {
+ 0x0080, 0x07ff, /* corner cases */
+ 0x0081, 0x07fe, 0x100, 0x333, 0x555, 0x6aa /* misc */
+};
+
+/* 0800 to d7ff: Result is 3 bytes for each uint32_t */
+/* dc00 to ffff: Result is 3 bytes for each uint32_t */
+uint32_t pattern3[] = {
+ 0x0800, 0xd7ff, /* corner cases */
+ 0xdc00, 0xffff, /* corner cases */
+ 0xdc01, 0xfffe, 0xdea0, 0xd00d, 0xe555 /* misc */
+};
+
+/* 10000 to 10ffff: Result is 4 bytes for each uint32_t */
+uint32_t pattern4[] = {
+ 0x10000, 0x10ffff, /* corner cases */
+ 0x10001, 0x10fffe, 0x12345, 0x23456, 0xfedcb /* misc */
+};
+
+/* Invalid UTF-32 character */
+uint32_t invalid[] = {
+ 0x0000d800, 0x0000dbff, /* corner cases */
+ 0x00110000, 0xffffffff, /* corner cases */
+ 0x0000daad, 0x0000d901, 0x0000d8ff, /* misc */
+ 0x00110011, 0x01000000, 0x10000000, 0xdeadbeef /* misc */
+};
+
+/* Mixed bytes */
+uint32_t mixed[] = {
+ 0x00000078 /* 1 byte */,
+ 0x00000111 /* 2 bytes */,
+ 0x00001234 /* 3 bytes */,
+ 0x00040404 /* 4 bytes */,
+};
+
+/* This is the buffer for the converted bytes. */
+uint8_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+void write_and_check(uint32_t *, unsigned, unsigned);
+
+
+static cu41_t
+do_cu41(uint8_t *dst, uint64_t dst_len, uint32_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu41_t regs;
+
+ /* build up the register pairs */
+ register uint32_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint8_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU41(2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu41 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint8_t *dst, uint64_t dst_len, uint32_t *src, uint64_t src_len)
+{
+ int i;
+ cu41_t result;
+
+ result = do_cu41(dst, dst_len, src, src_len);
+
+ // Write out the converted values, if any
+ printf("UTF8: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else
+ for (i = 0; i < dst_len - result.len1; ++i) {
+ printf(" %02x", dst[i]);
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+int main()
+{
+ int i;
+
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 0);
+ run_test(buff, sizeof buff, NULL, 1);
+ run_test(buff, sizeof buff, NULL, 2);
+ run_test(buff, sizeof buff, NULL, 3);
+ run_test(buff, sizeof buff, pattern1, 0);
+ run_test(buff, sizeof buff, pattern1, 1);
+ run_test(buff, sizeof buff, pattern1, 2);
+ run_test(buff, sizeof buff, pattern1, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 4); /* 1 utf32 -> 1 1-byte utf8 */
+ run_test(buff, sizeof buff, pattern2, 10); /* 2 utf32 -> 2 2-byte utf8 */
+ run_test(buff, sizeof buff, pattern3, 5); /* 1 utf32 -> 1 3-byte utf8 */
+ run_test(buff, sizeof buff, pattern4, 21); /* 5 utf32 -> 5 4-byte utf8 */
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write at least 1 byte */
+ run_test(NULL, 0, pattern1, sizeof pattern1);
+
+ /* Want to write at least 2 bytes */
+ run_test(NULL, 0, pattern2, sizeof pattern2);
+ run_test(NULL, 1, pattern2, sizeof pattern2);
+
+ /* Want to write at least 3 bytes */
+ run_test(NULL, 0, pattern3, sizeof pattern3);
+ run_test(NULL, 1, pattern3, sizeof pattern3);
+
+ /* Want to write at least 4 bytes */
+ run_test(NULL, 0, pattern4, sizeof pattern4);
+ run_test(NULL, 1, pattern4, sizeof pattern4);
+ run_test(NULL, 2, pattern4, sizeof pattern4);
+ run_test(NULL, 3, pattern4, sizeof pattern4);
+
+ /* When both operands are exhausted, cc=0 takes precedence.
+ (test1 tests this for len == 0) */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, 2, pattern1, 8);
+
+ /* Input contains invalid characters */
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n------------- test5 ----------------\n");
+ for (i = 0; i < sizeof invalid / 4; ++i) {
+ run_test(buff, sizeof buff, invalid + i, 4);
+ }
+ run_test(buff, 0, invalid, sizeof invalid); // cc = 2
+ run_test(buff, 100, invalid, sizeof invalid);
+
+ /* Convert all pattern buffers */
+ printf("\n------------- test6 ----------------\n");
+ run_test(buff, sizeof buff, pattern1, sizeof pattern1);
+ run_test(buff, sizeof buff, pattern2, sizeof pattern2);
+ run_test(buff, sizeof buff, pattern3, sizeof pattern3);
+ run_test(buff, sizeof buff, pattern4, sizeof pattern4);
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ /* Make sure we only write the exact number of bytes (and not more) */
+
+ /* Write 1 byte */
+ printf("\n------------- test7.0 ----------------\n");
+ write_and_check(pattern1 + 2, 4, 1);
+
+ /* Write 2 bytes */
+ printf("\n------------- test7.1 ----------------\n");
+ write_and_check(pattern2 + 3, 4, 2);
+
+ /* Write 3 bytes */
+ printf("\n------------- test7.2 ----------------\n");
+ write_and_check(pattern3 + 6, 4, 3);
+
+ /* Write 4 bytes */
+ printf("\n------------- test7.3 ----------------\n");
+ write_and_check(pattern4 + 5, 4, 4);
+
+ return 0;
+}
+
+
+void
+write_and_check_aux(uint32_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes,
+ unsigned fill_byte)
+{
+ int num_errors, i;
+
+ /* Fill output buffer with FILL_BYTE */
+ memset(buff, fill_byte, sizeof buff);
+
+ /* Execute cu41 */
+ run_test(buff, sizeof buff, input, num_input_bytes);
+
+ /* Make sure the rest of the buffer is unmodified. */
+ num_errors = 0;
+ for (i = num_expected_output_bytes; i < sizeof buff; ++i)
+ if (((unsigned char *)buff)[i] != fill_byte) ++num_errors;
+ if (num_errors)
+ fprintf(stderr, "*** wrote more than %d bytes\n",
+ num_expected_output_bytes);
+}
+
+void
+write_and_check(uint32_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes)
+{
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0x0);
+
+ /* Run again with different fill pattern to make sure we did not write
+ an extra 0x0 byte */
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0xFF);
+}
diff --git a/main/none/tests/s390x/cu41.stderr.exp b/main/none/tests/s390x/cu41.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu41.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu41.stdout.exp b/main/none/tests/s390x/cu41.stdout.exp
new file mode 100644
index 0000000..c7fa41f
--- /dev/null
+++ b/main/none/tests/s390x/cu41.stdout.exp
@@ -0,0 +1,218 @@
+
+------------- test1 ----------------
+UTF8: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src len: 0
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src len: 2
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src len: 3
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 0
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 1
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 2
+UTF8: <none>
+ cc = 0
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF8: 00
+ cc = 0
+ dst address difference: 1 dst len: 999
+ src address difference: 4 src len: 0
+UTF8: c2 80 df bf
+ cc = 0
+ dst address difference: 4 dst len: 996
+ src address difference: 8 src len: 2
+UTF8: e0 a0 80
+ cc = 0
+ dst address difference: 3 dst len: 997
+ src address difference: 4 src len: 1
+UTF8: f0 90 80 80 f4 8f bf bf f0 90 80 81 f4 8f bf be f0 92 8d 85
+ cc = 0
+ dst address difference: 20 dst len: 980
+ src address difference: 20 src len: 1
+
+------------- test3.1 ----------------
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 24
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 32
+UTF8: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 32
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 36
+UTF8: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 36
+UTF8: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 28
+UTF8: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 28
+UTF8: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 28
+UTF8: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 28
+
+------------- test4 ----------------
+UTF8: 00 7f
+ cc = 0
+ dst address difference: 2 dst len: 0
+ src address difference: 8 src len: 0
+
+------------- test5 ----------------
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 1000
+ src address difference: 0 src len: 4
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 0
+ src address difference: 0 src len: 44
+UTF8: <none>
+ cc = 2
+ dst address difference: 0 dst len: 100
+ src address difference: 0 src len: 44
+
+------------- test6 ----------------
+UTF8: 00 7f 01 7e 30 5e
+ cc = 0
+ dst address difference: 6 dst len: 994
+ src address difference: 24 src len: 0
+UTF8: c2 80 df bf c2 81 df be c4 80 cc b3 d5 95 da aa
+ cc = 0
+ dst address difference: 16 dst len: 984
+ src address difference: 32 src len: 0
+UTF8: e0 a0 80 ed 9f bf ed b0 80 ef bf bf ed b0 81 ef bf be ed ba a0 ed 80 8d ee 95 95
+ cc = 0
+ dst address difference: 27 dst len: 973
+ src address difference: 36 src len: 0
+UTF8: f0 90 80 80 f4 8f bf bf f0 90 80 81 f4 8f bf be f0 92 8d 85 f0 a3 91 96 f3 be b7 8b
+ cc = 0
+ dst address difference: 28 dst len: 972
+ src address difference: 28 src len: 0
+UTF8: 78 c4 91 e1 88 b4 f1 80 90 84
+ cc = 0
+ dst address difference: 10 dst len: 990
+ src address difference: 16 src len: 0
+
+------------- test7.0 ----------------
+UTF8: 01
+ cc = 0
+ dst address difference: 1 dst len: 999
+ src address difference: 4 src len: 0
+UTF8: 01
+ cc = 0
+ dst address difference: 1 dst len: 999
+ src address difference: 4 src len: 0
+
+------------- test7.1 ----------------
+UTF8: df be
+ cc = 0
+ dst address difference: 2 dst len: 998
+ src address difference: 4 src len: 0
+UTF8: df be
+ cc = 0
+ dst address difference: 2 dst len: 998
+ src address difference: 4 src len: 0
+
+------------- test7.2 ----------------
+UTF8: ed ba a0
+ cc = 0
+ dst address difference: 3 dst len: 997
+ src address difference: 4 src len: 0
+UTF8: ed ba a0
+ cc = 0
+ dst address difference: 3 dst len: 997
+ src address difference: 4 src len: 0
+
+------------- test7.3 ----------------
+UTF8: f0 a3 91 96
+ cc = 0
+ dst address difference: 4 dst len: 996
+ src address difference: 4 src len: 0
+UTF8: f0 a3 91 96
+ cc = 0
+ dst address difference: 4 dst len: 996
+ src address difference: 4 src len: 0
diff --git a/main/none/tests/s390x/cu41.vgtest b/main/none/tests/s390x/cu41.vgtest
new file mode 100644
index 0000000..815e594
--- /dev/null
+++ b/main/none/tests/s390x/cu41.vgtest
@@ -0,0 +1 @@
+prog: cu41
diff --git a/main/none/tests/s390x/cu42.c b/main/none/tests/s390x/cu42.c
new file mode 100644
index 0000000..2b41d76
--- /dev/null
+++ b/main/none/tests/s390x/cu42.c
@@ -0,0 +1,236 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <assert.h>
+#include "opcodes.h"
+
+/* The abstracted result of an CU42 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu42_t;
+
+/* Define various input buffers. */
+
+/* U+0000 to U+d7ff: Result is 2 bytes for each uint32_t
+ U+dc00 to U+ffff: Result is 2 bytes for each uint32_t */
+uint32_t pattern2[] = {
+ 0x0000, 0xd7ff, /* corner cases */
+ 0xdc00, 0xffff, /* corner cases */
+ 0xabba, 0xf00d, 0xd00f, 0x1234 /* misc */
+};
+
+/* U+00010000 to U+0010ffff: Result is 4 bytes for each uint32_t */
+uint32_t pattern4[] = {
+ 0x00010000, 0x0010ffff, /* corner cases */
+ 0x00010123, 0x00023456, 0x000789ab, 0x00100000 /* misc */
+};
+
+/* Invalid UTF-32 character */
+uint32_t invalid[] = {
+ 0x0000d800, 0x0000dbff, /* corner cases */
+ 0x00110000, 0xffffffff, /* corner cases */
+ 0x0000daad, 0x0000d901, 0x0000d8ff, /* misc */
+ 0x00110011, 0x01000000, 0x10000000, 0xdeadbeef /* misc */
+};
+
+/* Mixed bytes */
+uint32_t mixed[] = {
+ 0x00000078 /* 2 bytes */,
+ 0x0000d000 /* 2 bytes */,
+ 0x00033333 /* 4 bytes */,
+ 0x00040404 /* 4 bytes */,
+ 0x0000abcd /* 2 bytes */,
+};
+
+/* This is the buffer for the converted bytes. */
+uint16_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+void write_and_check(uint32_t *, unsigned, unsigned);
+
+
+static cu42_t
+do_cu42(uint16_t *dst, uint64_t dst_len, uint32_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu42_t regs;
+
+ /* build up the register pairs */
+ register uint32_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint16_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU42(2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu42 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint16_t *dst, uint64_t dst_len, uint32_t *src, uint64_t src_len)
+{
+ int i;
+ cu42_t result;
+
+ result = do_cu42(dst, dst_len, src, src_len);
+
+ // Write out the converted values, if any
+ printf("UTF16: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else
+ assert((dst_len - result.len1) % 2 == 0);
+ for (i = 0; i < (dst_len - result.len1) / 2; ++i) {
+ printf(" %04x", dst[i]);
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+int main()
+{
+ int i;
+
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 0);
+ run_test(buff, sizeof buff, NULL, 1);
+ run_test(buff, sizeof buff, NULL, 2);
+ run_test(buff, sizeof buff, NULL, 3);
+ run_test(buff, sizeof buff, pattern2, 0);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern2, 2);
+ run_test(buff, sizeof buff, pattern2, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern2, 4); /* 1 utf32 -> 1 utf16 */
+ run_test(buff, sizeof buff, pattern2, 10); /* 2 utf32 -> 2 utf16 */
+ run_test(buff, sizeof buff, pattern4, 5); /* 1 utf32 -> 2 utf16 */
+ run_test(buff, sizeof buff, pattern4, 11); /* 2 utf32 -> 4 utf16 */
+ run_test(buff, sizeof buff, pattern4, 18); /* 4 utf32 -> 8 utf16 */
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write at least 1 UTF-16 */
+ run_test(NULL, 0, pattern2, sizeof pattern2);
+
+ /* Want to write at least 1 UTF-16 */
+ run_test(NULL, 0, pattern2, sizeof pattern2);
+ run_test(NULL, 1, pattern2, sizeof pattern2);
+
+ /* Want to write at least 2 UTF-16 */
+ run_test(NULL, 0, pattern4, sizeof pattern4);
+ run_test(NULL, 1, pattern4, sizeof pattern4);
+ run_test(NULL, 2, pattern4, sizeof pattern4);
+ run_test(NULL, 3, pattern4, sizeof pattern4);
+
+ /* When both operands are exhausted, cc=0 takes precedence.
+ (test1 tests this for len == 0) */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, 4, pattern2, 8);
+
+ /* Input contains invalid characters */
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n------------- test5 ----------------\n");
+ for (i = 0; i < sizeof invalid / 4; ++i) {
+ run_test(buff, sizeof buff, invalid + i, 4);
+ }
+ run_test(buff, 0, invalid, sizeof invalid); // cc = 2
+ run_test(buff, 100, invalid, sizeof invalid);
+
+ /* Convert all pattern buffers */
+ printf("\n------------- test6 ----------------\n");
+ run_test(buff, sizeof buff, pattern2, sizeof pattern2);
+ run_test(buff, sizeof buff, pattern4, sizeof pattern4);
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ /* Make sure we only write the exact number of bytes (and not more) */
+
+ /* Write 2 bytes */
+ printf("\n------------- test7.1 ----------------\n");
+ write_and_check(pattern2 + 3, 4, 2);
+
+ /* Write 4 bytes */
+ printf("\n------------- test7.2 ----------------\n");
+ write_and_check(pattern4 + 5, 4, 4);
+
+ return 0;
+}
+
+
+void
+write_and_check_aux(uint32_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes,
+ unsigned fill_byte)
+{
+ int num_errors, i;
+
+ /* Fill output buffer with FILL_BYTE */
+ memset(buff, fill_byte, sizeof buff);
+
+ /* Execute cu42 */
+ run_test(buff, sizeof buff, input, num_input_bytes);
+
+ /* Make sure the rest of the buffer is unmodified. */
+ num_errors = 0;
+ for (i = num_expected_output_bytes; i < sizeof buff; ++i)
+ if (((unsigned char *)buff)[i] != fill_byte) ++num_errors;
+ if (num_errors)
+ fprintf(stderr, "*** wrote more than %d bytes\n",
+ num_expected_output_bytes);
+}
+
+void
+write_and_check(uint32_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes)
+{
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0x0);
+
+ /* Run again with different fill pattern to make sure we did not write
+ an extra 0x0 byte */
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0xFF);
+}
diff --git a/main/none/tests/s390x/cu42.stderr.exp b/main/none/tests/s390x/cu42.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/cu42.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/cu42.stdout.exp b/main/none/tests/s390x/cu42.stdout.exp
new file mode 100644
index 0000000..8bb3e24
--- /dev/null
+++ b/main/none/tests/s390x/cu42.stdout.exp
@@ -0,0 +1,186 @@
+
+------------- test1 ----------------
+UTF16: <none>
+ cc = 0
+ dst len: 0
+ src len: 0
+
+------------- test2.1 ----------------
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src len: 0
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src len: 1
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src len: 2
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src len: 3
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 0
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 1
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 2
+UTF16: <none>
+ cc = 0
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 3
+
+------------- test2.2 ----------------
+UTF16: 0000
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 4 src len: 0
+UTF16: 0000 d7ff
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 8 src len: 2
+UTF16: d800 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 1
+UTF16: d800 dc00 dbff dfff
+ cc = 0
+ dst address difference: 8 dst len: 1992
+ src address difference: 8 src len: 3
+UTF16: d800 dc00 dbff dfff d800 dd23 d84d dc56
+ cc = 0
+ dst address difference: 16 dst len: 1984
+ src address difference: 16 src len: 2
+
+------------- test3.1 ----------------
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 32
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 32
+UTF16: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 32
+UTF16: <none>
+ cc = 1
+ dst len: 0
+ src address difference: 0 src len: 24
+UTF16: <none>
+ cc = 1
+ dst len: 1
+ src address difference: 0 src len: 24
+UTF16: <none>
+ cc = 1
+ dst len: 2
+ src address difference: 0 src len: 24
+UTF16: <none>
+ cc = 1
+ dst len: 3
+ src address difference: 0 src len: 24
+
+------------- test4 ----------------
+UTF16: 0000 d7ff
+ cc = 0
+ dst address difference: 4 dst len: 0
+ src address difference: 8 src len: 0
+
+------------- test5 ----------------
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 2000
+ src address difference: 0 src len: 4
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 0
+ src address difference: 0 src len: 44
+UTF16: <none>
+ cc = 2
+ dst address difference: 0 dst len: 100
+ src address difference: 0 src len: 44
+
+------------- test6 ----------------
+UTF16: 0000 d7ff dc00 ffff abba f00d d00f 1234
+ cc = 0
+ dst address difference: 16 dst len: 1984
+ src address difference: 32 src len: 0
+UTF16: d800 dc00 dbff dfff d800 dd23 d84d dc56 d9a2 ddab dbc0 dc00
+ cc = 0
+ dst address difference: 24 dst len: 1976
+ src address difference: 24 src len: 0
+UTF16: 0078 d000 d88c df33 d8c1 dc04 abcd
+ cc = 0
+ dst address difference: 14 dst len: 1986
+ src address difference: 20 src len: 0
+
+------------- test7.1 ----------------
+UTF16: ffff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 4 src len: 0
+UTF16: ffff
+ cc = 0
+ dst address difference: 2 dst len: 1998
+ src address difference: 4 src len: 0
+
+------------- test7.2 ----------------
+UTF16: dbc0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
+UTF16: dbc0 dc00
+ cc = 0
+ dst address difference: 4 dst len: 1996
+ src address difference: 4 src len: 0
diff --git a/main/none/tests/s390x/cu42.vgtest b/main/none/tests/s390x/cu42.vgtest
new file mode 100644
index 0000000..da601bc
--- /dev/null
+++ b/main/none/tests/s390x/cu42.vgtest
@@ -0,0 +1 @@
+prog: cu42
diff --git a/main/none/tests/arm/v6int.stdout.exp b/main/none/tests/s390x/flogr.stdout.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stdout.exp
copy to main/none/tests/s390x/flogr.stdout.exp
diff --git a/main/none/tests/s390x/flogr.vgtest b/main/none/tests/s390x/flogr.vgtest
index c5a32db..68d4aa6 100644
--- a/main/none/tests/s390x/flogr.vgtest
+++ b/main/none/tests/s390x/flogr.vgtest
@@ -1,2 +1 @@
prog: flogr
-prereq: test -x flogr
diff --git a/main/none/tests/s390x/fpconv.c b/main/none/tests/s390x/fpconv.c
new file mode 100644
index 0000000..c83749d
--- /dev/null
+++ b/main/none/tests/s390x/fpconv.c
@@ -0,0 +1,147 @@
+/* basic float <-> signed int conversions available since z900 */
+#include <float.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#define I2F(insn, initial, target,round) \
+({ \
+ register unsigned long source asm("2") = initial; \
+ register typeof(target) _t asm("f0"); \
+ asm volatile(insn " 0,2\n\t" :"=f" (_t):"d"(source)); \
+ _t; \
+})
+
+#define F2L(insn, initial, type, round, cc) \
+({ \
+ register type source asm("f0") = initial; \
+ register unsigned long target asm ("2") = 0; \
+ asm volatile(insn " 2," #round ",0\n\t" \
+ "ipm %1\n\t" \
+ "srl %1,28\n\t" \
+ :"=d" (target), "=d" (cc) :"f"(source):"cc"); \
+ target; \
+})
+
+
+#define DO_INSN_I2F32(insn, round) \
+({ \
+ float f32; \
+ printf(#insn " %f\n", I2F(insn, 0, f32, round)); \
+ printf(#insn " %f\n", I2F(insn, 1, f32, round)); \
+ printf(#insn " %f\n", I2F(insn, 0xffffffffUL, f32, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x80000000UL, f32, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x7fffffffUL, f32, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x100000000UL, f32, round)); \
+ printf(#insn " %f\n", I2F(insn, 0xffffffffffffffffUL, f32, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x8000000000000000UL, f32, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x7fffffffffffffffUL, f32, round)); \
+})
+
+#define DO_INSN_I2F64(insn, round) \
+({ \
+ double f64; \
+ printf(#insn " %f\n", I2F(insn, 0, f64, round)); \
+ printf(#insn " %f\n", I2F(insn, 1, f64, round)); \
+ printf(#insn " %f\n", I2F(insn, 0xffffffffUL, f64, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x80000000UL, f64, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x7fffffffUL, f64, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x100000000UL, f64, round)); \
+ printf(#insn " %f\n", I2F(insn, 0xffffffffffffffffUL, f64, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x8000000000000000UL, f64, round)); \
+ printf(#insn " %f\n", I2F(insn, 0x7fffffffffffffffUL, f64, round)); \
+})
+
+#define DO_INSN_I2F128(insn, round) \
+({ \
+ long double f128; \
+ printf(#insn " %Lf\n", I2F(insn, 0, f128, round)); \
+ printf(#insn " %Lf\n", I2F(insn, 1, f128, round)); \
+ printf(#insn " %Lf\n", I2F(insn, 0xffffffffUL, f128, round)); \
+ printf(#insn " %Lf\n", I2F(insn, 0x80000000UL, f128, round)); \
+ printf(#insn " %Lf\n", I2F(insn, 0x7fffffffUL, f128, round)); \
+ printf(#insn " %Lf\n", I2F(insn, 0x100000000UL, f128, round)); \
+ printf(#insn " %Lf\n", I2F(insn, 0xffffffffffffffffUL, f128, round)); \
+ printf(#insn " %Lf\n", I2F(insn, 0x8000000000000000UL, f128, round)); \
+ printf(#insn " %Lf\n", I2F(insn, 0x7fffffffffffffffUL, f128, round)); \
+})
+
+#define DO_INSN_F2L(insn, round, type) \
+({ \
+ int cc; \
+ printf(#insn " %ld ", F2L(insn, -1.1, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 0, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.4, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.5, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.6, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.6E+4, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.6E+8, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.6E+12, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.6E+20, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.6E+200, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.6E+2000L, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, 1.6E-4, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, FLT_MIN, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, FLT_MAX, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, DBL_MIN, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, DBL_MAX, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, LDBL_MIN, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %ld ", F2L(insn, LDBL_MAX, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+})
+
+#define DO_I2F(round) \
+({ \
+ DO_INSN_I2F32("cefbr", round); \
+ DO_INSN_I2F32("cegbr", round); \
+ DO_INSN_I2F64("cdfbr", round); \
+ DO_INSN_I2F64("cdgbr", round); \
+ DO_INSN_I2F128("cxfbr", round); \
+ DO_INSN_I2F128("cxgbr", round); \
+})
+
+#define DO_F2L(round) \
+({ \
+ DO_INSN_F2L("cfebr", round, float); \
+ DO_INSN_F2L("cgebr", round, float); \
+ DO_INSN_F2L("cfdbr", round, double); \
+ DO_INSN_F2L("cgdbr", round, double); \
+ DO_INSN_F2L("cfxbr", round, long double); \
+ DO_INSN_F2L("cgxbr", round, long double); \
+})
+
+
+int main()
+{
+ DO_I2F(4);
+ DO_F2L(4);
+
+ DO_I2F(5);
+ DO_F2L(5);
+
+ DO_I2F(6);
+ DO_F2L(6);
+
+ DO_I2F(7);
+ DO_F2L(7);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/fpconv.stderr.exp b/main/none/tests/s390x/fpconv.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/fpconv.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/fpconv.stdout.exp b/main/none/tests/s390x/fpconv.stdout.exp
new file mode 100644
index 0000000..57ef18e
--- /dev/null
+++ b/main/none/tests/s390x/fpconv.stdout.exp
@@ -0,0 +1,672 @@
+"cefbr" 0.000000
+"cefbr" 1.000000
+"cefbr" -1.000000
+"cefbr" -2147483648.000000
+"cefbr" 2147483648.000000
+"cefbr" 0.000000
+"cefbr" -1.000000
+"cefbr" 0.000000
+"cefbr" -1.000000
+"cegbr" 0.000000
+"cegbr" 1.000000
+"cegbr" 4294967296.000000
+"cegbr" 2147483648.000000
+"cegbr" 2147483648.000000
+"cegbr" 4294967296.000000
+"cegbr" -1.000000
+"cegbr" -9223372036854775808.000000
+"cegbr" 9223372036854775808.000000
+"cdfbr" 0.000000
+"cdfbr" 1.000000
+"cdfbr" -1.000000
+"cdfbr" -2147483648.000000
+"cdfbr" 2147483647.000000
+"cdfbr" 0.000000
+"cdfbr" -1.000000
+"cdfbr" 0.000000
+"cdfbr" -1.000000
+"cdgbr" 0.000000
+"cdgbr" 1.000000
+"cdgbr" 4294967295.000000
+"cdgbr" 2147483648.000000
+"cdgbr" 2147483647.000000
+"cdgbr" 4294967296.000000
+"cdgbr" -1.000000
+"cdgbr" -9223372036854775808.000000
+"cdgbr" 9223372036854775808.000000
+"cxfbr" 0.000000
+"cxfbr" 1.000000
+"cxfbr" -1.000000
+"cxfbr" -2147483648.000000
+"cxfbr" 2147483647.000000
+"cxfbr" 0.000000
+"cxfbr" -1.000000
+"cxfbr" 0.000000
+"cxfbr" -1.000000
+"cxgbr" 0.000000
+"cxgbr" 1.000000
+"cxgbr" 4294967295.000000
+"cxgbr" 2147483648.000000
+"cxgbr" 2147483647.000000
+"cxgbr" 4294967296.000000
+"cxgbr" -1.000000
+"cxgbr" -9223372036854775808.000000
+"cxgbr" 9223372036854775807.000000
+"cfebr" 4294967295 cc=1
+"cfebr" 0 cc=0
+"cfebr" 1 cc=2
+"cfebr" 1 cc=2
+"cfebr" 2 cc=2
+"cfebr" 2 cc=2
+"cfebr" 16000 cc=2
+"cfebr" 160000000 cc=2
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=2
+"cfebr" 0 cc=2
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=0
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=0
+"cfebr" 2147483647 cc=3
+"cgebr" -1 cc=1
+"cgebr" 0 cc=0
+"cgebr" 1 cc=2
+"cgebr" 1 cc=2
+"cgebr" 2 cc=2
+"cgebr" 2 cc=2
+"cgebr" 16000 cc=2
+"cgebr" 160000000 cc=2
+"cgebr" 1599999967232 cc=2
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=2
+"cgebr" 0 cc=2
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=0
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=0
+"cgebr" 9223372036854775807 cc=3
+"cfdbr" 4294967295 cc=1
+"cfdbr" 0 cc=0
+"cfdbr" 1 cc=2
+"cfdbr" 1 cc=2
+"cfdbr" 2 cc=2
+"cfdbr" 2 cc=2
+"cfdbr" 16000 cc=2
+"cfdbr" 160000000 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=2
+"cfdbr" 0 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=0
+"cfdbr" 2147483647 cc=3
+"cgdbr" -1 cc=1
+"cgdbr" 0 cc=0
+"cgdbr" 1 cc=2
+"cgdbr" 1 cc=2
+"cgdbr" 2 cc=2
+"cgdbr" 2 cc=2
+"cgdbr" 16000 cc=2
+"cgdbr" 160000000 cc=2
+"cgdbr" 1600000000000 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=2
+"cgdbr" 0 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=0
+"cgdbr" 9223372036854775807 cc=3
+"cfxbr" 4294967295 cc=1
+"cfxbr" 0 cc=0
+"cfxbr" 1 cc=2
+"cfxbr" 1 cc=2
+"cfxbr" 2 cc=2
+"cfxbr" 2 cc=2
+"cfxbr" 16000 cc=2
+"cfxbr" 160000000 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 0 cc=2
+"cfxbr" 0 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 0 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 0 cc=2
+"cfxbr" 2147483647 cc=3
+"cgxbr" -1 cc=1
+"cgxbr" 0 cc=0
+"cgxbr" 1 cc=2
+"cgxbr" 1 cc=2
+"cgxbr" 2 cc=2
+"cgxbr" 2 cc=2
+"cgxbr" 16000 cc=2
+"cgxbr" 160000000 cc=2
+"cgxbr" 1600000000000 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 0 cc=2
+"cgxbr" 0 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 0 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 0 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cefbr" 0.000000
+"cefbr" 1.000000
+"cefbr" -1.000000
+"cefbr" -2147483648.000000
+"cefbr" 2147483648.000000
+"cefbr" 0.000000
+"cefbr" -1.000000
+"cefbr" 0.000000
+"cefbr" -1.000000
+"cegbr" 0.000000
+"cegbr" 1.000000
+"cegbr" 4294967296.000000
+"cegbr" 2147483648.000000
+"cegbr" 2147483648.000000
+"cegbr" 4294967296.000000
+"cegbr" -1.000000
+"cegbr" -9223372036854775808.000000
+"cegbr" 9223372036854775808.000000
+"cdfbr" 0.000000
+"cdfbr" 1.000000
+"cdfbr" -1.000000
+"cdfbr" -2147483648.000000
+"cdfbr" 2147483647.000000
+"cdfbr" 0.000000
+"cdfbr" -1.000000
+"cdfbr" 0.000000
+"cdfbr" -1.000000
+"cdgbr" 0.000000
+"cdgbr" 1.000000
+"cdgbr" 4294967295.000000
+"cdgbr" 2147483648.000000
+"cdgbr" 2147483647.000000
+"cdgbr" 4294967296.000000
+"cdgbr" -1.000000
+"cdgbr" -9223372036854775808.000000
+"cdgbr" 9223372036854775808.000000
+"cxfbr" 0.000000
+"cxfbr" 1.000000
+"cxfbr" -1.000000
+"cxfbr" -2147483648.000000
+"cxfbr" 2147483647.000000
+"cxfbr" 0.000000
+"cxfbr" -1.000000
+"cxfbr" 0.000000
+"cxfbr" -1.000000
+"cxgbr" 0.000000
+"cxgbr" 1.000000
+"cxgbr" 4294967295.000000
+"cxgbr" 2147483648.000000
+"cxgbr" 2147483647.000000
+"cxgbr" 4294967296.000000
+"cxgbr" -1.000000
+"cxgbr" -9223372036854775808.000000
+"cxgbr" 9223372036854775807.000000
+"cfebr" 4294967295 cc=1
+"cfebr" 0 cc=0
+"cfebr" 1 cc=2
+"cfebr" 1 cc=2
+"cfebr" 1 cc=2
+"cfebr" 1 cc=2
+"cfebr" 16000 cc=2
+"cfebr" 160000000 cc=2
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=2
+"cfebr" 0 cc=2
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=0
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=0
+"cfebr" 2147483647 cc=3
+"cgebr" -1 cc=1
+"cgebr" 0 cc=0
+"cgebr" 1 cc=2
+"cgebr" 1 cc=2
+"cgebr" 1 cc=2
+"cgebr" 1 cc=2
+"cgebr" 16000 cc=2
+"cgebr" 160000000 cc=2
+"cgebr" 1599999967232 cc=2
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=2
+"cgebr" 0 cc=2
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=0
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=0
+"cgebr" 9223372036854775807 cc=3
+"cfdbr" 4294967295 cc=1
+"cfdbr" 0 cc=0
+"cfdbr" 1 cc=2
+"cfdbr" 1 cc=2
+"cfdbr" 1 cc=2
+"cfdbr" 1 cc=2
+"cfdbr" 16000 cc=2
+"cfdbr" 160000000 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=2
+"cfdbr" 0 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=0
+"cfdbr" 2147483647 cc=3
+"cgdbr" -1 cc=1
+"cgdbr" 0 cc=0
+"cgdbr" 1 cc=2
+"cgdbr" 1 cc=2
+"cgdbr" 1 cc=2
+"cgdbr" 1 cc=2
+"cgdbr" 16000 cc=2
+"cgdbr" 160000000 cc=2
+"cgdbr" 1600000000000 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=2
+"cgdbr" 0 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=0
+"cgdbr" 9223372036854775807 cc=3
+"cfxbr" 4294967295 cc=1
+"cfxbr" 0 cc=0
+"cfxbr" 1 cc=2
+"cfxbr" 1 cc=2
+"cfxbr" 1 cc=2
+"cfxbr" 1 cc=2
+"cfxbr" 16000 cc=2
+"cfxbr" 160000000 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 0 cc=2
+"cfxbr" 0 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 0 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 0 cc=2
+"cfxbr" 2147483647 cc=3
+"cgxbr" -1 cc=1
+"cgxbr" 0 cc=0
+"cgxbr" 1 cc=2
+"cgxbr" 1 cc=2
+"cgxbr" 1 cc=2
+"cgxbr" 1 cc=2
+"cgxbr" 16000 cc=2
+"cgxbr" 160000000 cc=2
+"cgxbr" 1600000000000 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 0 cc=2
+"cgxbr" 0 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 0 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 0 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cefbr" 0.000000
+"cefbr" 1.000000
+"cefbr" -1.000000
+"cefbr" -2147483648.000000
+"cefbr" 2147483648.000000
+"cefbr" 0.000000
+"cefbr" -1.000000
+"cefbr" 0.000000
+"cefbr" -1.000000
+"cegbr" 0.000000
+"cegbr" 1.000000
+"cegbr" 4294967296.000000
+"cegbr" 2147483648.000000
+"cegbr" 2147483648.000000
+"cegbr" 4294967296.000000
+"cegbr" -1.000000
+"cegbr" -9223372036854775808.000000
+"cegbr" 9223372036854775808.000000
+"cdfbr" 0.000000
+"cdfbr" 1.000000
+"cdfbr" -1.000000
+"cdfbr" -2147483648.000000
+"cdfbr" 2147483647.000000
+"cdfbr" 0.000000
+"cdfbr" -1.000000
+"cdfbr" 0.000000
+"cdfbr" -1.000000
+"cdgbr" 0.000000
+"cdgbr" 1.000000
+"cdgbr" 4294967295.000000
+"cdgbr" 2147483648.000000
+"cdgbr" 2147483647.000000
+"cdgbr" 4294967296.000000
+"cdgbr" -1.000000
+"cdgbr" -9223372036854775808.000000
+"cdgbr" 9223372036854775808.000000
+"cxfbr" 0.000000
+"cxfbr" 1.000000
+"cxfbr" -1.000000
+"cxfbr" -2147483648.000000
+"cxfbr" 2147483647.000000
+"cxfbr" 0.000000
+"cxfbr" -1.000000
+"cxfbr" 0.000000
+"cxfbr" -1.000000
+"cxgbr" 0.000000
+"cxgbr" 1.000000
+"cxgbr" 4294967295.000000
+"cxgbr" 2147483648.000000
+"cxgbr" 2147483647.000000
+"cxgbr" 4294967296.000000
+"cxgbr" -1.000000
+"cxgbr" -9223372036854775808.000000
+"cxgbr" 9223372036854775807.000000
+"cfebr" 4294967295 cc=1
+"cfebr" 0 cc=0
+"cfebr" 1 cc=2
+"cfebr" 2 cc=2
+"cfebr" 2 cc=2
+"cfebr" 2 cc=2
+"cfebr" 16000 cc=2
+"cfebr" 160000000 cc=2
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 1 cc=2
+"cfebr" 1 cc=2
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=0
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=0
+"cfebr" 2147483647 cc=3
+"cgebr" -1 cc=1
+"cgebr" 0 cc=0
+"cgebr" 1 cc=2
+"cgebr" 2 cc=2
+"cgebr" 2 cc=2
+"cgebr" 2 cc=2
+"cgebr" 16000 cc=2
+"cgebr" 160000000 cc=2
+"cgebr" 1599999967232 cc=2
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 1 cc=2
+"cgebr" 1 cc=2
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=0
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=0
+"cgebr" 9223372036854775807 cc=3
+"cfdbr" 4294967295 cc=1
+"cfdbr" 0 cc=0
+"cfdbr" 1 cc=2
+"cfdbr" 2 cc=2
+"cfdbr" 2 cc=2
+"cfdbr" 2 cc=2
+"cfdbr" 16000 cc=2
+"cfdbr" 160000000 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 1 cc=2
+"cfdbr" 1 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 1 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=0
+"cfdbr" 2147483647 cc=3
+"cgdbr" -1 cc=1
+"cgdbr" 0 cc=0
+"cgdbr" 1 cc=2
+"cgdbr" 2 cc=2
+"cgdbr" 2 cc=2
+"cgdbr" 2 cc=2
+"cgdbr" 16000 cc=2
+"cgdbr" 160000000 cc=2
+"cgdbr" 1600000000000 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 1 cc=2
+"cgdbr" 1 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 1 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=0
+"cgdbr" 9223372036854775807 cc=3
+"cfxbr" 4294967295 cc=1
+"cfxbr" 0 cc=0
+"cfxbr" 1 cc=2
+"cfxbr" 2 cc=2
+"cfxbr" 2 cc=2
+"cfxbr" 2 cc=2
+"cfxbr" 16000 cc=2
+"cfxbr" 160000000 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 1 cc=2
+"cfxbr" 1 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 1 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 1 cc=2
+"cfxbr" 2147483647 cc=3
+"cgxbr" -1 cc=1
+"cgxbr" 0 cc=0
+"cgxbr" 1 cc=2
+"cgxbr" 2 cc=2
+"cgxbr" 2 cc=2
+"cgxbr" 2 cc=2
+"cgxbr" 16000 cc=2
+"cgxbr" 160000000 cc=2
+"cgxbr" 1600000000000 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 1 cc=2
+"cgxbr" 1 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 1 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 1 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cefbr" 0.000000
+"cefbr" 1.000000
+"cefbr" -1.000000
+"cefbr" -2147483648.000000
+"cefbr" 2147483648.000000
+"cefbr" 0.000000
+"cefbr" -1.000000
+"cefbr" 0.000000
+"cefbr" -1.000000
+"cegbr" 0.000000
+"cegbr" 1.000000
+"cegbr" 4294967296.000000
+"cegbr" 2147483648.000000
+"cegbr" 2147483648.000000
+"cegbr" 4294967296.000000
+"cegbr" -1.000000
+"cegbr" -9223372036854775808.000000
+"cegbr" 9223372036854775808.000000
+"cdfbr" 0.000000
+"cdfbr" 1.000000
+"cdfbr" -1.000000
+"cdfbr" -2147483648.000000
+"cdfbr" 2147483647.000000
+"cdfbr" 0.000000
+"cdfbr" -1.000000
+"cdfbr" 0.000000
+"cdfbr" -1.000000
+"cdgbr" 0.000000
+"cdgbr" 1.000000
+"cdgbr" 4294967295.000000
+"cdgbr" 2147483648.000000
+"cdgbr" 2147483647.000000
+"cdgbr" 4294967296.000000
+"cdgbr" -1.000000
+"cdgbr" -9223372036854775808.000000
+"cdgbr" 9223372036854775808.000000
+"cxfbr" 0.000000
+"cxfbr" 1.000000
+"cxfbr" -1.000000
+"cxfbr" -2147483648.000000
+"cxfbr" 2147483647.000000
+"cxfbr" 0.000000
+"cxfbr" -1.000000
+"cxfbr" 0.000000
+"cxfbr" -1.000000
+"cxgbr" 0.000000
+"cxgbr" 1.000000
+"cxgbr" 4294967295.000000
+"cxgbr" 2147483648.000000
+"cxgbr" 2147483647.000000
+"cxgbr" 4294967296.000000
+"cxgbr" -1.000000
+"cxgbr" -9223372036854775808.000000
+"cxgbr" 9223372036854775807.000000
+"cfebr" 4294967294 cc=1
+"cfebr" 0 cc=0
+"cfebr" 1 cc=2
+"cfebr" 1 cc=2
+"cfebr" 1 cc=2
+"cfebr" 1 cc=2
+"cfebr" 16000 cc=2
+"cfebr" 160000000 cc=2
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=2
+"cfebr" 0 cc=2
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=0
+"cfebr" 2147483647 cc=3
+"cfebr" 0 cc=0
+"cfebr" 2147483647 cc=3
+"cgebr" -2 cc=1
+"cgebr" 0 cc=0
+"cgebr" 1 cc=2
+"cgebr" 1 cc=2
+"cgebr" 1 cc=2
+"cgebr" 1 cc=2
+"cgebr" 16000 cc=2
+"cgebr" 160000000 cc=2
+"cgebr" 1599999967232 cc=2
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=2
+"cgebr" 0 cc=2
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=0
+"cgebr" 9223372036854775807 cc=3
+"cgebr" 0 cc=0
+"cgebr" 9223372036854775807 cc=3
+"cfdbr" 4294967294 cc=1
+"cfdbr" 0 cc=0
+"cfdbr" 1 cc=2
+"cfdbr" 1 cc=2
+"cfdbr" 1 cc=2
+"cfdbr" 1 cc=2
+"cfdbr" 16000 cc=2
+"cfdbr" 160000000 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=2
+"cfdbr" 0 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=2
+"cfdbr" 2147483647 cc=3
+"cfdbr" 0 cc=0
+"cfdbr" 2147483647 cc=3
+"cgdbr" -2 cc=1
+"cgdbr" 0 cc=0
+"cgdbr" 1 cc=2
+"cgdbr" 1 cc=2
+"cgdbr" 1 cc=2
+"cgdbr" 1 cc=2
+"cgdbr" 16000 cc=2
+"cgdbr" 160000000 cc=2
+"cgdbr" 1600000000000 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=2
+"cgdbr" 0 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=2
+"cgdbr" 9223372036854775807 cc=3
+"cgdbr" 0 cc=0
+"cgdbr" 9223372036854775807 cc=3
+"cfxbr" 4294967294 cc=1
+"cfxbr" 0 cc=0
+"cfxbr" 1 cc=2
+"cfxbr" 1 cc=2
+"cfxbr" 1 cc=2
+"cfxbr" 1 cc=2
+"cfxbr" 16000 cc=2
+"cfxbr" 160000000 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 2147483647 cc=3
+"cfxbr" 0 cc=2
+"cfxbr" 0 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 0 cc=2
+"cfxbr" 2147483647 cc=3
+"cfxbr" 0 cc=2
+"cfxbr" 2147483647 cc=3
+"cgxbr" -2 cc=1
+"cgxbr" 0 cc=0
+"cgxbr" 1 cc=2
+"cgxbr" 1 cc=2
+"cgxbr" 1 cc=2
+"cgxbr" 1 cc=2
+"cgxbr" 16000 cc=2
+"cgxbr" 160000000 cc=2
+"cgxbr" 1600000000000 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 0 cc=2
+"cgxbr" 0 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 0 cc=2
+"cgxbr" 9223372036854775807 cc=3
+"cgxbr" 0 cc=2
+"cgxbr" 9223372036854775807 cc=3
diff --git a/main/none/tests/s390x/fpconv.vgtest b/main/none/tests/s390x/fpconv.vgtest
new file mode 100644
index 0000000..e2e3c28
--- /dev/null
+++ b/main/none/tests/s390x/fpconv.vgtest
@@ -0,0 +1 @@
+prog: fpconv
diff --git a/main/none/tests/s390x/insert_EI.vgtest b/main/none/tests/s390x/insert_EI.vgtest
index 31daf83..6459eff 100644
--- a/main/none/tests/s390x/insert_EI.vgtest
+++ b/main/none/tests/s390x/insert_EI.vgtest
@@ -1,2 +1 @@
prog: insert_EI
-prereq: test -x insert_EI
diff --git a/main/none/tests/s390x/mul_GE.vgtest b/main/none/tests/s390x/mul_GE.vgtest
index 8ed8428..007a2e6 100644
--- a/main/none/tests/s390x/mul_GE.vgtest
+++ b/main/none/tests/s390x/mul_GE.vgtest
@@ -1,2 +1 @@
prog: mul_GE
-prereq: test -x mul_GE
diff --git a/main/none/tests/s390x/op00.stderr.exp1 b/main/none/tests/s390x/op00.stderr.exp1
index 73d098c..b7552bf 100644
--- a/main/none/tests/s390x/op00.stderr.exp1
+++ b/main/none/tests/s390x/op00.stderr.exp1
@@ -1,5 +1,19 @@
+vex s390->IR: unknown insn: 0000
+valgrind: Unrecognised instruction at address 0x.........
+ at 0x........: main (op00.c:3)
+Your program just tried to execute an instruction that Valgrind
+did not recognise. There are two possible reasons for this.
+1. Your program has a bug and erroneously jumped to a non-code
+ location. If you are running Memcheck and you just saw a
+ warning about a bad jump, it's probably your program's fault.
+2. The instruction is legitimate but Valgrind doesn't handle it,
+ i.e. it's Valgrind's fault. If you think this is the case or
+ you are not sure, please let us know and we'll try to fix it.
+Either way, Valgrind will now raise a SIGILL signal which will
+probably kill your program.
Process terminating with default action of signal 4 (SIGILL)
- at 0x........: main (op00.c:5)
+ Illegal opcode at address 0x........
+ at 0x........: main (op00.c:3)
diff --git a/main/none/tests/s390x/op00.stderr.exp2 b/main/none/tests/s390x/op00.stderr.exp2
index d587a66..b7552bf 100644
--- a/main/none/tests/s390x/op00.stderr.exp2
+++ b/main/none/tests/s390x/op00.stderr.exp2
@@ -1,6 +1,19 @@
+vex s390->IR: unknown insn: 0000
+valgrind: Unrecognised instruction at address 0x.........
+ at 0x........: main (op00.c:3)
+Your program just tried to execute an instruction that Valgrind
+did not recognise. There are two possible reasons for this.
+1. Your program has a bug and erroneously jumped to a non-code
+ location. If you are running Memcheck and you just saw a
+ warning about a bad jump, it's probably your program's fault.
+2. The instruction is legitimate but Valgrind doesn't handle it,
+ i.e. it's Valgrind's fault. If you think this is the case or
+ you are not sure, please let us know and we'll try to fix it.
+Either way, Valgrind will now raise a SIGILL signal which will
+probably kill your program.
Process terminating with default action of signal 4 (SIGILL)
Illegal opcode at address 0x........
- at 0x........: main (op00.c:5)
+ at 0x........: main (op00.c:3)
diff --git a/main/none/tests/s390x/op_exception.stderr.exp b/main/none/tests/s390x/op_exception.stderr.exp
index 24c6bf3..4373ff5 100644
--- a/main/none/tests/s390x/op_exception.stderr.exp
+++ b/main/none/tests/s390x/op_exception.stderr.exp
@@ -1,4 +1,30 @@
+vex s390->IR: unknown insn: 0000
+valgrind: Unrecognised instruction at address 0x.........
+ at 0x........: main (op_exception.c:23)
+Your program just tried to execute an instruction that Valgrind
+did not recognise. There are two possible reasons for this.
+1. Your program has a bug and erroneously jumped to a non-code
+ location. If you are running Memcheck and you just saw a
+ warning about a bad jump, it's probably your program's fault.
+2. The instruction is legitimate but Valgrind doesn't handle it,
+ i.e. it's Valgrind's fault. If you think this is the case or
+ you are not sure, please let us know and we'll try to fix it.
+Either way, Valgrind will now raise a SIGILL signal which will
+probably kill your program.
+vex s390->IR: unknown insn: 0000
+valgrind: Unrecognised instruction at address 0x.........
+ at 0x........: main (op_exception.c:23)
+Your program just tried to execute an instruction that Valgrind
+did not recognise. There are two possible reasons for this.
+1. Your program has a bug and erroneously jumped to a non-code
+ location. If you are running Memcheck and you just saw a
+ warning about a bad jump, it's probably your program's fault.
+2. The instruction is legitimate but Valgrind doesn't handle it,
+ i.e. it's Valgrind's fault. If you think this is the case or
+ you are not sure, please let us know and we'll try to fix it.
+Either way, Valgrind will now raise a SIGILL signal which will
+probably kill your program.
vex s390->IR: unknown insn: FFFF FFFF FFFF
valgrind: Unrecognised instruction at address 0x.........
at 0x........: main (op_exception.c:30)
@@ -12,4 +38,17 @@
you are not sure, please let us know and we'll try to fix it.
Either way, Valgrind will now raise a SIGILL signal which will
probably kill your program.
+vex s390->IR: unknown insn: 0000
+valgrind: Unrecognised instruction at address 0x.........
+ at 0x........: main (op_exception.c:30)
+Your program just tried to execute an instruction that Valgrind
+did not recognise. There are two possible reasons for this.
+1. Your program has a bug and erroneously jumped to a non-code
+ location. If you are running Memcheck and you just saw a
+ warning about a bad jump, it's probably your program's fault.
+2. The instruction is legitimate but Valgrind doesn't handle it,
+ i.e. it's Valgrind's fault. If you think this is the case or
+ you are not sure, please let us know and we'll try to fix it.
+Either way, Valgrind will now raise a SIGILL signal which will
+probably kill your program.
diff --git a/main/none/tests/s390x/opcodes.h b/main/none/tests/s390x/opcodes.h
index 7469c87..8dcdea5 100644
--- a/main/none/tests/s390x/opcodes.h
+++ b/main/none/tests/s390x/opcodes.h
@@ -51,6 +51,7 @@
".short 0x" #op1 #r1 #r2 "\n\t" \
".long 0x" #i4 #m3 #u0 #op2 "\n\t"
#define RRE_RR(op,u0,r1,r2) ".long 0x" #op #u0 #r1 #r2 "\n\t"
+#define RRE_RERE(op,r1,r2) ".long 0x" #op "00" #r1 #r2 "\n\t"
#define SIL_RDU(op,b1,d1,i2) \
".short 0x" #op "\n\t" \
".long 0x" #b1 #d1 #i2 "\n\t"
@@ -92,6 +93,7 @@
#define RIE_RRUUU(op1,r1,r2,i3,i4,i5,op2) \
".short 0x" #op1 #r1 #r2 "\n\t" \
".long 0x" #i3 #i4 #i5 #op2 "\n\t"
+#define RRF_M0RERE(op,m3,r1,r2) ".long 0x" #op #m3 "0" #r1 #r2 "\n\t"
#define AFI(r1,i2) RIL_RI(c2,r1,9,i2)
#define AGFI(r1,i2) RIL_RI(c2,r1,8,i2)
@@ -170,6 +172,12 @@
#define CRJ(r1,r2,i4,m3) RIE_RRPU(ec,r1,r2,i4,m3,0,76)
#define CRL(r1,i2) RIL_RP(c6,r1,d,i2)
#define CSY(r1,r3,b2,dl2,dh2) RSY_RRRD(eb,r1,r3,b2,dl2,dh2,14)
+#define CU12(m3,r1,r2) RRF_M0RERE(b2a7,m3,r1,r2)
+#define CU14(m3,r1,r2) RRF_M0RERE(b9b0,m3,r1,r2)
+#define CU21(m3,r1,r2) RRF_M0RERE(b2a6,m3,r1,r2)
+#define CU24(m3,r1,r2) RRF_M0RERE(b9b1,m3,r1,r2)
+#define CU41(r1,r2) RRE_RERE(b9b2,r1,r2)
+#define CU42(r1,r2) RRE_RERE(b9b3,r1,r2)
#define CVBY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,06)
#define CVDY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,26)
#define CY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,59)
diff --git a/main/none/tests/s390x/or_EI.vgtest b/main/none/tests/s390x/or_EI.vgtest
index f455267..5b33c7d 100644
--- a/main/none/tests/s390x/or_EI.vgtest
+++ b/main/none/tests/s390x/or_EI.vgtest
@@ -1,2 +1 @@
prog: or_EI
-prereq: test -x or_EI
diff --git a/main/none/tests/s390x/sub_EI.vgtest b/main/none/tests/s390x/sub_EI.vgtest
index cca7720..1bc6e37 100644
--- a/main/none/tests/s390x/sub_EI.vgtest
+++ b/main/none/tests/s390x/sub_EI.vgtest
@@ -1,2 +1 @@
prog: sub_EI
-prereq: test -x sub_EI
diff --git a/main/none/tests/s390x/table.h b/main/none/tests/s390x/table.h
new file mode 100644
index 0000000..f6d475b
--- /dev/null
+++ b/main/none/tests/s390x/table.h
@@ -0,0 +1,75 @@
+char touppercase[256] =
+{
+
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F,
+ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
+ 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F,
+ 0x30, 0x31, 0x32/*50*/, 0x33, 0x34, 0x35, 0x36, 0x37,
+ 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F,
+ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
+ 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F,
+ 0x50/*80*/, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
+ 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F,
+ 0x60, 0x41/*97*/, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
+ 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F,
+ 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
+ 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F,
+ 0x80, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
+ 0xC8, 0xC9, 0x8A, 0x8B, 0xAC, 0xAD, 0xAE, 0x8F,
+ 0x90, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+ 0xD8, 0xD9, 0x9A, 0x9B, 0x9E, 0x9D, 0x9E, 0x9F,
+ 0xA0, 0xA1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+ 0xE8, 0xE9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF,
+ 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7,
+ 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF,
+ 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
+ 0xC8, 0xC9, 0xCA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+ 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+ 0xD8, 0xD9, 0xDA, 0xFB, 0xFC, 0xFD, 0xFE, 0xDF,
+ 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+ 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
+ 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
+ 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
+
+};
+
+char tolowercase[256] =
+{
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F,
+ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
+ 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F,
+ 0x30, 0x31, 0x32/*50*/, 0x33, 0x34, 0x35, 0x36, 0x37,
+ 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F,
+ 0x40, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+ 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F,
+ 0x70/*80*/, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
+ 0x78, 0x79, 0x7A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F,
+ 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+ 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F,
+ 0x70, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
+ 0x58, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F,
+ 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+ 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F,
+ 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
+ 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9C, 0x9F,
+ 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7,
+ 0xA8, 0xA9, 0xAA, 0xAB, 0x8C, 0x8D, 0x8E, 0xAF,
+ 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7,
+ 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF,
+ 0xC0, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+ 0x88, 0x89, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF,
+ 0xD0, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
+ 0x98, 0x99, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF,
+ 0xE0, 0xE1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7,
+ 0xA8, 0xA9, 0xEA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF,
+ 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
+ 0xF8, 0xF9, 0xFA, 0xDB, 0xDC, 0xDD, 0xDE, 0xFF
+};
+
+
diff --git a/main/none/tests/s390x/tr.c b/main/none/tests/s390x/tr.c
new file mode 100644
index 0000000..a99b736
--- /dev/null
+++ b/main/none/tests/s390x/tr.c
@@ -0,0 +1,56 @@
+#include<stdio.h>
+#include<stdlib.h>
+#include<asm/types.h>
+#include<stdint.h>
+#include<string.h>
+#include "table.h"
+
+uint8_t buff[40];
+
+void tr(uint8_t *codepage, uint8_t *addr, uint64_t len)
+{
+ asm volatile(
+ " larl 1,1f\n"
+ "1: tr 0(1,%0),0(%2)\n"
+ " ex %1,0(1)"
+ : "+&a" (addr), "+a" (len)
+ : "a" (codepage) : "cc", "memory", "1");
+}
+
+void run_test(void *tran_table, void *srcaddr, uint64_t len)
+{
+ int i;
+
+ tr(tran_table, buff, len);
+ printf("the translated string is ");
+ for (i = 0; i < len; i++) {
+ printf("%c", buff[i]);
+ }
+ printf("\n");
+}
+
+int main()
+{
+ /* Test 1: length = 0 */
+ run_test((char *)&touppercase, &buff, 0);
+ run_test((char *)&touppercase, &buff, 0);
+
+ /* Test 2 : length > 0 */
+ memset(buff, 'a', 1);
+ run_test((char *)&touppercase, &buff, 1);
+
+ memcpy(buff, "abcdefgh", 8);
+ run_test((char *)&touppercase, &buff, 3);
+ run_test((char *)&touppercase, &buff, 3);
+ run_test((char *)&touppercase, &buff, 8);
+
+ memcpy(buff, "ABCDEFGH", 8);
+ run_test((char *)&tolowercase, &buff, 3);
+ run_test((char *)&tolowercase, &buff, 3);
+ run_test((char *)&tolowercase, &buff, 8);
+
+ memcpy(buff, "0123456789", 9);
+ run_test((char *)&touppercase, &buff, 9);
+ run_test((char *)&tolowercase, &buff, 9);
+ return 0;
+}
diff --git a/main/none/tests/s390x/tr.stderr.exp b/main/none/tests/s390x/tr.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/tr.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/tr.stdout.exp b/main/none/tests/s390x/tr.stdout.exp
new file mode 100644
index 0000000..51d906f
--- /dev/null
+++ b/main/none/tests/s390x/tr.stdout.exp
@@ -0,0 +1,11 @@
+the translated string is
+the translated string is
+the translated string is A
+the translated string is ABC
+the translated string is ABC
+the translated string is ABCDEFGH
+the translated string is abc
+the translated string is abc
+the translated string is abcdefgh
+the translated string is 012345678
+the translated string is 012345678
diff --git a/main/none/tests/s390x/tr.vgtest b/main/none/tests/s390x/tr.vgtest
new file mode 100644
index 0000000..6e3f34c
--- /dev/null
+++ b/main/none/tests/s390x/tr.vgtest
@@ -0,0 +1 @@
+prog: tr
diff --git a/main/none/tests/s390x/tre.c b/main/none/tests/s390x/tre.c
new file mode 100644
index 0000000..dd2e1ef
--- /dev/null
+++ b/main/none/tests/s390x/tre.c
@@ -0,0 +1,94 @@
+#include<stdio.h>
+#include<stdlib.h>
+#include<stdint.h>
+#include<inttypes.h>
+#include<string.h>
+#include "table.h"
+
+/* Register contents after executing an TRE insn */
+typedef struct {
+ uint64_t addr;
+ uint64_t len;
+ uint64_t tabaddr;
+ uint8_t testbyte;
+ uint64_t cc;
+} tre_regs;
+
+uint8_t buff[40];
+
+tre_regs tre(uint8_t *codepage, uint8_t *addr, uint64_t len, uint8_t test_byte)
+{
+ int cc;
+ tre_regs regs;
+
+ register uint64_t param asm("0") = test_byte;
+ register uint64_t a2 asm ("4") = (uint64_t)codepage;
+ register uint64_t a1 asm ("2") = (uint64_t)addr;
+ register uint64_t l1 asm ("3") = len;
+
+ asm volatile(
+ " tre %1,%2\n"
+ " ipm %0\n"
+ " srl %0,28\n"
+ :"=d"(cc),"+&d"(a1)
+ :"d"(a2),"d"(param),"d"(l1),"d"(test_byte): "memory" );
+
+ regs.addr = a1;
+ regs.len = l1;
+ regs.tabaddr = a2;
+ regs.testbyte = param;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void run_test(void *tran_table, void *srcaddr, uint64_t len, uint8_t test)
+{
+ tre_regs regs;
+ int i;
+
+ regs = tre(tran_table, srcaddr, len, test);
+
+ if ((uint64_t)tran_table != regs.tabaddr)
+ printf("translation table address changed\n");
+ if (test != regs.testbyte)
+ printf("test byte changed\n");
+ if ((uint64_t)srcaddr + (len - regs.len) != regs.addr)
+ printf("source address/length not updated properly\n");
+
+ printf("Resulting cc is %"PRIu64" and the string is ", regs.cc);
+ for ( i = 0; i < len; i++) {
+ printf("%c", buff[i]);
+ }
+
+ printf("\n");
+}
+
+int main()
+{
+
+ /* Test 1: length = 0 */
+ run_test(NULL, NULL, 0, 0x0);
+ run_test((char *)&touppercase, &buff, 0, 0x0);
+ run_test((char *)&touppercase, &buff, 0, 'b');
+
+ /* Test 2 : length > 0 */
+ memset(buff, 'a', 1);
+ run_test((char *)&touppercase, &buff, 1, 'a'); //cc = 1
+ run_test((char *)&touppercase, &buff, 1, 'b');
+
+ memcpy(buff, "abcdefgh", 8);
+ run_test((char *)&touppercase, &buff, 3, 'a'); //cc = 1
+ run_test((char *)&touppercase, &buff, 3, 'f'); //cc = 0
+ run_test((char *)&touppercase, &buff, 8, 'l'); //cc = 0
+
+ memcpy(buff, "ABCDEFGH", 8);
+ run_test((char *)&tolowercase, &buff, 3, 'A'); // cc = 1
+ run_test((char *)&tolowercase, &buff, 3, 'C'); // cc = 0
+ run_test((char *)&tolowercase, &buff, 8, 0x0); // cc = 0
+
+ memcpy(buff, "01234567", 8);
+ run_test((char *)&touppercase, &buff, 8, 'A');
+ run_test((char *)&tolowercase, &buff, 8, 'A');
+ return 0;
+}
diff --git a/main/none/tests/s390x/tre.stderr.exp b/main/none/tests/s390x/tre.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/tre.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/tre.stdout.exp b/main/none/tests/s390x/tre.stdout.exp
new file mode 100644
index 0000000..3a42b52
--- /dev/null
+++ b/main/none/tests/s390x/tre.stdout.exp
@@ -0,0 +1,13 @@
+Resulting cc is 0 and the string is
+Resulting cc is 0 and the string is
+Resulting cc is 0 and the string is
+Resulting cc is 1 and the string is a
+Resulting cc is 0 and the string is A
+Resulting cc is 1 and the string is abc
+Resulting cc is 0 and the string is ABC
+Resulting cc is 0 and the string is ABCDEFGH
+Resulting cc is 1 and the string is ABC
+Resulting cc is 1 and the string is abC
+Resulting cc is 0 and the string is abcdefgh
+Resulting cc is 0 and the string is 01234567
+Resulting cc is 0 and the string is 01234567
diff --git a/main/none/tests/s390x/tre.vgtest b/main/none/tests/s390x/tre.vgtest
new file mode 100644
index 0000000..19a4755
--- /dev/null
+++ b/main/none/tests/s390x/tre.vgtest
@@ -0,0 +1 @@
+prog: tre
diff --git a/main/none/tests/s390x/troo.c b/main/none/tests/s390x/troo.c
new file mode 100644
index 0000000..374f3cd
--- /dev/null
+++ b/main/none/tests/s390x/troo.c
@@ -0,0 +1,126 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+
+/* Register contents after executing an TROO insn */
+typedef struct {
+ uint64_t srcaddr;
+ uint64_t len;
+ uint64_t desaddr;
+ uint64_t tabaddr;
+ uint8_t testbyte;
+ uint64_t cc;
+} troo_regs;
+
+uint8_t tran_table[20] = {
+ 0xaa,0xbb,0xcc,0xdd,0xff,0xda,0xbc,0xab,0xca,0xea,0xcc,0xee
+};
+
+uint8_t src[20] = {
+ 0x04,0x01,0x03,0x07,0x08,0x06,0x02,0x05,0x09
+};
+
+uint8_t des[20];
+
+troo_regs tr(uint8_t *addr, uint8_t *codepage, uint8_t *dest, uint64_t len,
+ uint8_t test)
+{
+ troo_regs regs;
+ register uint64_t test_byte asm("0") = test;
+ register uint64_t length asm("3") = len;
+ register uint64_t srcaddr asm("4") = (uint64_t)addr;
+ register uint64_t codepage2 asm("1") = (uint64_t)codepage;
+ register uint64_t desaddr asm("2") = (uint64_t)dest;
+ register uint64_t cc asm("5");
+
+ cc = 2; /* cc result will never be 2 */
+ asm volatile(
+ " troo %1,%2\n"
+ " ipm %0\n"
+ " srl %0,28\n"
+ : "=d"(cc),"+&d"(desaddr)
+ : "d" (srcaddr),"d"(test_byte),"d" (codepage2),"d"(length)
+ : "memory" );
+
+ regs.srcaddr = srcaddr;
+ regs.len = length;
+ regs.desaddr = desaddr;
+ regs.tabaddr = codepage2;
+ regs.testbyte = test_byte;
+ regs.cc = cc;
+ return regs;
+}
+
+int run_test(void *srcaddr, void *tableaddr, void *desaddr, uint64_t len,
+ uint8_t testbyte)
+{
+ troo_regs regs;
+ int i;
+
+ assert(len <= sizeof src);
+
+ if ((testbyte & 0xff) != testbyte)
+ printf("testbyte should be 1 byte only\n");
+
+ regs = tr(srcaddr, tableaddr, desaddr, len, testbyte);
+
+ if ((uint64_t)tableaddr != regs.tabaddr)
+ printf("translation table address changed\n");
+ if ((uint64_t)srcaddr + (len - regs.len) != regs.srcaddr)
+ printf("source address/length not updated properly\n");
+ if ((uint64_t)desaddr + (len - regs.len) != regs.desaddr)
+ printf("destination address/length not updated properly\n");
+ if (regs.cc == 0 && regs.len != 0)
+ printf("length is not zero but cc is zero\n");
+ printf("%u bytes translated\n", (unsigned)(len - regs.len));
+ printf("the translated values are");
+ for (i = 0; i < len - regs.len; i++) {
+ printf(" %x", des[i]);
+ }
+ printf("\n");
+
+ return regs.cc;
+}
+
+int main()
+{
+ int cc;
+
+ assert(sizeof des >= sizeof src);
+
+ /* Test 1 : len == 0 */
+ cc = run_test(NULL, NULL, NULL, 0, 0x0);
+ if (cc != 0)
+ printf("cc not updated properly:%d", cc);
+
+ cc = run_test(&src, &tran_table, &des, 0, 0xca);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ /* Test 2 : len > 0, testbyte not matching */
+ cc = run_test(&src, &tran_table, &des, 5, 0xee);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 10, 0x00);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ memset((char *)&des, 0, 10);
+
+ /* Test 3 : len > 0, testbyte matching */
+ cc = run_test(&src, &tran_table, &des, 5, 0xff); /* 1st byte matches */
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 5, 0xbb); /* 2nd byte matches */
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 10, 0xea);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/troo.stderr.exp b/main/none/tests/s390x/troo.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/troo.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/troo.stdout.exp b/main/none/tests/s390x/troo.stdout.exp
new file mode 100644
index 0000000..bebf998
--- /dev/null
+++ b/main/none/tests/s390x/troo.stdout.exp
@@ -0,0 +1,14 @@
+0 bytes translated
+the translated values are
+0 bytes translated
+the translated values are
+5 bytes translated
+the translated values are ff bb dd ab ca
+10 bytes translated
+the translated values are ff bb dd ab ca bc cc da ea aa
+0 bytes translated
+the translated values are
+1 bytes translated
+the translated values are ff
+8 bytes translated
+the translated values are ff bb dd ab ca bc cc da
diff --git a/main/none/tests/s390x/troo.vgtest b/main/none/tests/s390x/troo.vgtest
new file mode 100644
index 0000000..500076e
--- /dev/null
+++ b/main/none/tests/s390x/troo.vgtest
@@ -0,0 +1 @@
+prog: troo
diff --git a/main/none/tests/s390x/trot.c b/main/none/tests/s390x/trot.c
new file mode 100644
index 0000000..b4b44c8
--- /dev/null
+++ b/main/none/tests/s390x/trot.c
@@ -0,0 +1,132 @@
+#include<stdio.h>
+#include<stdint.h>
+#include<string.h>
+#include<assert.h>
+
+/* Register contents after executing an TROT insn */
+typedef struct {
+ uint64_t srcaddr;
+ uint64_t len;
+ uint64_t desaddr;
+ uint64_t tabaddr;
+ uint16_t testbyte;
+ uint64_t cc;
+} trot_regs;
+
+uint16_t tran_table[40] = {
+ 0xaaaa,0xbbbb,0xcccc,0xccdd,0xffff,0xdada,0xbcbc,0xabab,0xcaca,0xeaea,
+ 0xbbbb,0xeeee
+};
+
+uint8_t src[40] = {
+ 0x01,0x03,0x04,0x02,0x07,0x08,0x06,0x02,0x05,0x09
+};
+
+uint16_t des[40];
+
+trot_regs tr(uint8_t *addr, uint16_t *codepage, uint16_t *dest, uint64_t len,
+ uint16_t test)
+{
+ trot_regs regs;
+ register uint64_t test_byte asm("0") = test;
+ register uint64_t length asm("3") = len;
+ register uint64_t srcaddr asm("4") = (uint64_t)addr;
+ register uint64_t codepage2 asm("1") = (uint64_t)codepage;
+ register uint64_t desaddr asm("2") = (uint64_t)dest;
+ register uint64_t cc asm("5");
+
+ cc = 2; /* cc result will never be 2 */
+ asm volatile(
+ " trot %1,%2\n"
+ " ipm %0\n"
+ " srl %0,28\n"
+ : "=d"(cc),"+&d"(desaddr)
+ : "d" (srcaddr),"d"(test_byte),"d" (codepage2),"d"(length)
+ : "memory" );
+
+ regs.srcaddr = srcaddr;
+ regs.len = length;
+ regs.desaddr = desaddr;
+ regs.tabaddr = codepage2;
+ regs.testbyte = test_byte;
+ regs.cc = cc;
+ return regs;
+}
+
+int run_test(void *srcaddr, void *tableaddr, void *desaddr, uint64_t len,
+ uint16_t testbyte)
+{
+ trot_regs regs;
+ int i;
+
+ assert(len <= sizeof src);
+
+ if ((testbyte & 0xffff) != testbyte)
+ printf("testbyte should be 2 byte only\n");
+
+ regs = tr(srcaddr, tableaddr, desaddr, len, testbyte);
+
+ if ((uint64_t)tableaddr != regs.tabaddr)
+ printf("translation table address changed\n");
+ if ((uint64_t)srcaddr + (len - regs.len) != regs.srcaddr)
+ printf("source address/length not updated properly\n");
+ if ((uint64_t)desaddr + 2*(len - regs.len) != regs.desaddr)
+ printf("destination address/length not updated properly\n");
+ if (regs.cc == 0 && regs.len != 0)
+ printf("length is not zero but cc is zero\n");
+ printf("%u bytes translated\n", (unsigned)(len - regs.len));
+ printf("the translated values is");
+ for (i = 0; i < len; i++) {
+ printf(" %hx", des[i]);
+ }
+ printf("\n");
+
+ return regs.cc;
+}
+
+
+int main()
+{
+ int cc;
+
+ assert(sizeof des >= sizeof src);
+
+ /* Test 1 : len == 0 */
+ cc = run_test(NULL, NULL, NULL, 0, 0x0);
+ if (cc != 0)
+ printf("cc not updated properly:%d", cc);
+
+ cc = run_test(&src, &tran_table, &des, 0, 0x0);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 0, 0xcaca);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ /* Test 2 : len > 0, testbyte not matching */
+ cc = run_test(&src, &tran_table, &des, 3, 0xeeee);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 10, 0xeeee);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ memset((uint16_t *)&des, 0, 10);
+
+ /* Test 3 : len > 0 , testbyte matching */
+ cc = run_test(&src, &tran_table, &des, 5, 0xffff);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 5, 0xcccc);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 10, 0xeaea);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/trot.stderr.exp b/main/none/tests/s390x/trot.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/trot.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/trot.stdout.exp b/main/none/tests/s390x/trot.stdout.exp
new file mode 100644
index 0000000..cdd1c6e
--- /dev/null
+++ b/main/none/tests/s390x/trot.stdout.exp
@@ -0,0 +1,16 @@
+0 bytes translated
+the translated values is
+0 bytes translated
+the translated values is
+0 bytes translated
+the translated values is
+3 bytes translated
+the translated values is bbbb ccdd ffff
+10 bytes translated
+the translated values is bbbb ccdd ffff cccc abab caca bcbc cccc dada eaea
+2 bytes translated
+the translated values is bbbb ccdd 0 0 0
+3 bytes translated
+the translated values is bbbb ccdd ffff 0 0
+9 bytes translated
+the translated values is bbbb ccdd ffff cccc abab caca bcbc cccc dada eaea
diff --git a/main/none/tests/s390x/trot.vgtest b/main/none/tests/s390x/trot.vgtest
new file mode 100644
index 0000000..bf85e59
--- /dev/null
+++ b/main/none/tests/s390x/trot.vgtest
@@ -0,0 +1 @@
+prog: trot
diff --git a/main/none/tests/s390x/trto.c b/main/none/tests/s390x/trto.c
new file mode 100644
index 0000000..b79721d
--- /dev/null
+++ b/main/none/tests/s390x/trto.c
@@ -0,0 +1,130 @@
+#include<stdio.h>
+#include<stdint.h>
+#include<assert.h>
+#include<string.h>
+
+/* Register contents after executing an TRTO insn */
+typedef struct {
+ uint64_t srcaddr;
+ uint64_t len;
+ uint64_t desaddr;
+ uint64_t tabaddr;
+ uint8_t testbyte;
+ uint64_t cc;
+} trto_regs;
+
+uint8_t tran_table[40] = {
+ 0xaa,0xbb,0xcc,0xdd,0xff,0xdd,0xbc,0xab,0xca,0xea,0xbb,0xee
+};
+
+int16_t src[40] = {
+ 0x2,0x03,0x04,0x02,0x07,0x08,0x06,0x02,0x05,0x09
+};
+
+uint8_t des[20];
+
+trto_regs tr(uint16_t *addr, uint16_t *codepage, uint8_t *dest, uint64_t len,
+ uint8_t test)
+{
+ trto_regs regs;
+ register uint64_t test_byte asm("0") = test;
+ register uint64_t length asm("3") = len;
+ register uint64_t srcaddr asm("4") = (uint64_t)addr;
+ register uint64_t codepage2 asm("1") = (uint64_t)codepage;
+ register uint64_t desaddr asm("2") = (uint64_t)dest;
+ register uint64_t cc asm("5");
+
+ cc = 2; /* cc result will never be 2 */
+ asm volatile(
+ " trto %1,%2\n"
+ " ipm %0\n"
+ " srl %0,28\n"
+ : "=d"(cc),"+&d"(desaddr)
+ : "d" (srcaddr),"d"(test_byte),"d" (codepage2),"d"(length)
+ : "memory" );
+
+ regs.srcaddr = srcaddr;
+ regs.len = length;
+ regs.desaddr = desaddr;
+ regs.tabaddr = codepage2;
+ regs.testbyte = test_byte;
+ regs.cc = cc;
+ return regs;
+}
+
+int run_test(void *srcaddr, void *tableaddr, void *desaddr, uint64_t len,
+ uint8_t testbyte)
+{
+ trto_regs regs;
+ int i;
+
+ assert(len <= sizeof src);
+
+ if ((testbyte & 0xffff) != testbyte)
+ printf("testbyte should be 1 byte only\n");
+
+ regs = tr(srcaddr, tableaddr, desaddr, len, testbyte);
+
+ if ((uint64_t)tableaddr != regs.tabaddr)
+ printf("translation table address changed\n");
+ if ((uint64_t)srcaddr + (len - regs.len) != regs.srcaddr)
+ printf("source address/length not updated properly\n");
+ if ((uint64_t)desaddr + ((len - regs.len)/2) != regs.desaddr)
+ printf("destination address/length not updated properly\n");
+ if (regs.cc == 0 && regs.len != 0)
+ printf("length is not zero but cc is zero\n");
+ printf("%u bytes translated\n", ((unsigned)(len - regs.len)/2));
+ printf("the translated values is");
+ for (i = 0; i < len/2; i++) {
+ printf(" %x", des[i]);
+ }
+ printf("\n");
+
+ return regs.cc;
+}
+
+int main()
+{
+ int cc;
+
+ assert(sizeof des <= sizeof src);
+
+ /* Test 1 : len == 0 */
+ cc = run_test(NULL, NULL, NULL, 0, 0x0);
+ if (cc != 0)
+ printf("cc not updated properly:%d", cc);
+
+ cc = run_test(&src, &tran_table, &des, 0, 0x0);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 0, 0xca);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ /* Test 2 : len > 0, testbyte not matching */
+ cc = run_test(&src, &tran_table, &des, 12, 0xee);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 20, 0x00);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ memset((uint16_t *)&des, 0, 10);
+
+ /* Test 3 : len > 0 , testbyte matching */
+ cc = run_test(&src, &tran_table, &des, 12, 0xff);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 12, 0xcc);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 20, 0xea);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/trto.stderr.exp b/main/none/tests/s390x/trto.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/trto.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/trto.stdout.exp b/main/none/tests/s390x/trto.stdout.exp
new file mode 100644
index 0000000..d3a4fc0
--- /dev/null
+++ b/main/none/tests/s390x/trto.stdout.exp
@@ -0,0 +1,16 @@
+0 bytes translated
+the translated values is
+0 bytes translated
+the translated values is
+0 bytes translated
+the translated values is
+6 bytes translated
+the translated values is cc dd ff cc ab ca
+10 bytes translated
+the translated values is cc dd ff cc ab ca bc cc dd ea
+2 bytes translated
+the translated values is cc dd 0 0 0 0
+0 bytes translated
+the translated values is cc dd 0 0 0 0
+9 bytes translated
+the translated values is cc dd ff cc ab ca bc cc dd 0
diff --git a/main/none/tests/s390x/trto.vgtest b/main/none/tests/s390x/trto.vgtest
new file mode 100644
index 0000000..d3fe588
--- /dev/null
+++ b/main/none/tests/s390x/trto.vgtest
@@ -0,0 +1 @@
+prog: trto
diff --git a/main/none/tests/s390x/trtt.c b/main/none/tests/s390x/trtt.c
new file mode 100644
index 0000000..e9cb899
--- /dev/null
+++ b/main/none/tests/s390x/trtt.c
@@ -0,0 +1,133 @@
+#include<stdio.h>
+#include<stdint.h>
+#include<string.h>
+#include<assert.h>
+
+/* Register contents after executing an TRTT insn */
+typedef struct {
+ uint64_t srcaddr;
+ uint64_t len;
+ uint64_t desaddr;
+ uint64_t tabaddr;
+ uint16_t testbyte;
+ uint64_t cc;
+} trtt_regs;
+
+uint16_t tran_table[40] = {
+ 0xaaaa,0xcccc,0xcccc,0xdddd,0xffff,0xdada,0xbcbc,0xabab,0xcaca,0xeaea,
+ 0xbbbb,0xeeee
+};
+
+uint16_t src[40] = {
+ 0x4,0x03,0x04,0x02,0x07,0x08,0x06,0x02,0x05,0x09,0xa
+};
+
+uint16_t des[20];
+
+trtt_regs tr(uint16_t *addr, uint16_t *codepage, uint16_t *dest, uint64_t len,
+ uint16_t test)
+{
+ trtt_regs regs;
+ register uint64_t test_byte asm("0") = test;
+ register uint64_t length asm("3") = len;
+ register uint64_t srcaddr asm("4") = (uint64_t)addr;
+ register uint64_t codepage2 asm("1") = (uint64_t)codepage;
+ register uint64_t desaddr asm("2") = (uint64_t)dest;
+ register uint64_t cc asm("5");
+
+ cc = 2; /* cc result will never be 2 */
+ asm volatile(
+ " trtt %1,%2\n"
+ " ipm %0\n"
+ " srl %0,28\n"
+ : "=d"(cc),"+d"(desaddr),"+d"(srcaddr)
+ : "d"(test_byte),"d" (codepage2),"d"(length)
+ : "memory" );
+
+ regs.srcaddr = srcaddr;
+ regs.len = length;
+ regs.desaddr = desaddr;
+ regs.tabaddr = codepage2;
+ regs.testbyte = test_byte;
+ regs.cc = cc;
+
+ return regs;
+}
+
+int run_test(void *srcaddr, void *tableaddr, void *desaddr, uint64_t len,
+ uint16_t testbyte)
+{
+ trtt_regs regs;
+ int i;
+
+ assert(len <= sizeof src);
+
+ if ((testbyte & 0xffff) != testbyte)
+ printf("testbyte should be 2 byte only\n");
+
+ regs = tr(srcaddr, tableaddr, desaddr, len, testbyte);
+
+ if ((uint64_t)tableaddr != regs.tabaddr)
+ printf("translation table address changed\n");
+ if ((uint64_t)srcaddr + (len - regs.len) != regs.srcaddr)
+ printf("source address/length not updated properly\n");
+ if ((uint64_t)desaddr + (len - regs.len) != regs.desaddr)
+ printf("destination address/length not updated properly\n");
+ if (regs.cc == 0 && regs.len != 0)
+ printf("length is not zero but cc is zero\n");
+ printf("%u bytes translated\n", ((unsigned)(len - regs.len))/2);
+ printf("the translated values is");
+ for (i = 0; i < len/2; i++) {
+ printf(" %hx", des[i]);
+ }
+ printf("\n");
+
+ return regs.cc;
+}
+
+
+int main()
+{
+ int cc;
+
+ assert(sizeof des <= sizeof src);
+
+ /* Test 1 : len == 0 */
+ cc = run_test(NULL, NULL, NULL, 0, 0x0);
+ if (cc != 0)
+ printf("cc not updated properly:%d", cc);
+
+ cc = run_test(&src, &tran_table, &des, 0, 0x0);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 0, 0xcaca);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ /* Test 2 : len > 0, testbyte not matching */
+ cc = run_test(&src, &tran_table, &des, 4, 0xdada);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 10, 0x00);
+ if (cc != 0)
+ printf("cc not updated properly:%d",cc);
+
+ memset((uint16_t *)&des, 0, 10);
+
+ /* Test 3 : len > 0 , testbyte matching */
+ cc = run_test(&src, &tran_table, &des, 10, 0xffff);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 10, 0xcccc);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ cc = run_test(&src, &tran_table, &des, 20, 0xeaea);
+ if (cc != 1)
+ printf("cc not updated properly:%d",cc);
+
+ return 0;
+}
diff --git a/main/none/tests/s390x/trtt.stderr.exp b/main/none/tests/s390x/trtt.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/main/none/tests/s390x/trtt.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/main/none/tests/s390x/trtt.stdout.exp b/main/none/tests/s390x/trtt.stdout.exp
new file mode 100644
index 0000000..068c3f9
--- /dev/null
+++ b/main/none/tests/s390x/trtt.stdout.exp
@@ -0,0 +1,16 @@
+0 bytes translated
+the translated values is
+0 bytes translated
+the translated values is
+0 bytes translated
+the translated values is
+2 bytes translated
+the translated values is ffff dddd
+5 bytes translated
+the translated values is ffff dddd ffff cccc abab
+0 bytes translated
+the translated values is 0 0 0 0 0
+3 bytes translated
+the translated values is ffff dddd ffff 0 0
+9 bytes translated
+the translated values is ffff dddd ffff cccc abab caca bcbc cccc dada 0
diff --git a/main/none/tests/s390x/trtt.vgtest b/main/none/tests/s390x/trtt.vgtest
new file mode 100644
index 0000000..5255d78
--- /dev/null
+++ b/main/none/tests/s390x/trtt.vgtest
@@ -0,0 +1 @@
+prog: trtt
diff --git a/main/none/tests/s390x/xor_EI.vgtest b/main/none/tests/s390x/xor_EI.vgtest
index 27baf35..53b7ee1 100644
--- a/main/none/tests/s390x/xor_EI.vgtest
+++ b/main/none/tests/s390x/xor_EI.vgtest
@@ -1,2 +1 @@
prog: xor_EI
-prereq: test -x xor_EI
diff --git a/main/none/tests/selfrun.vgtest b/main/none/tests/selfrun.vgtest
index 8db2779..55cc8c9 100644
--- a/main/none/tests/selfrun.vgtest
+++ b/main/none/tests/selfrun.vgtest
@@ -1,3 +1,3 @@
prog: ../../coregrind/valgrind --tool=none --command-line-only=yes ./selfrun
-vgopts: --vex-iropt-precise-memory-exns=yes
+vgopts: --vex-iropt-register-updates=allregs-at-mem-access
prereq: grep '^#define HAVE_PIE 1' ../../config.h > /dev/null
diff --git a/main/none/tests/shell b/main/none/tests/shell
index 5c71c35..588a95d 100755
--- a/main/none/tests/shell
+++ b/main/none/tests/shell
@@ -5,7 +5,7 @@
#----------------------------------------------------------------------------
# Shell scripts that should fail
#----------------------------------------------------------------------------
-
+LC_ALL=C
echo "Execute a directory"
./x86/
diff --git a/main/none/tests/shell.stderr.exp-dash2 b/main/none/tests/shell.stderr.exp-dash2
new file mode 100644
index 0000000..1e7f02c
--- /dev/null
+++ b/main/none/tests/shell.stderr.exp-dash2
@@ -0,0 +1,8 @@
+./shell: 10: ./shell: ./x86/: Permission denied
+./shell: 13: ./shell: ./shell.vgtest: Permission denied
+execve(0x........(./shell_badinterp), 0x........, 0x........) failed, errno 2
+EXEC FAILED: I can't recover from execve() failing, so I'm dying.
+Add more stringent tests in PRE(sys_execve), or work out how to recover.
+./shell_binaryfile: 4: ./shell_binaryfile: Syntax error: ")" unexpected
+./shell: 22: ./shell: ./shell_nosuchfile: not found
+./shell: 25: ./shell: shell_nosuchfile: not found
diff --git a/main/none/tests/x86-linux/Makefile.in b/main/none/tests/x86-linux/Makefile.in
new file mode 100644
index 0000000..3a3272c
--- /dev/null
+++ b/main/none/tests/x86-linux/Makefile.in
@@ -0,0 +1,708 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+check_PROGRAMS = seg_override$(EXEEXT) sigcontext$(EXEEXT)
+subdir = none/tests/x86-linux
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+seg_override_SOURCES = seg_override.c
+seg_override_OBJECTS = seg_override.$(OBJEXT)
+seg_override_LDADD = $(LDADD)
+sigcontext_SOURCES = sigcontext.c
+sigcontext_OBJECTS = sigcontext.$(OBJEXT)
+sigcontext_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = seg_override.c sigcontext.c
+DIST_SOURCES = seg_override.c sigcontext.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+ filter_stderr
+
+EXTRA_DIST = \
+ seg_override.stderr.exp seg_override.stdout.exp seg_override.vgtest \
+ sigcontext.stdout.exp sigcontext.stderr.exp sigcontext.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/x86-linux/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/x86-linux/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+seg_override$(EXEEXT): $(seg_override_OBJECTS) $(seg_override_DEPENDENCIES)
+ @rm -f seg_override$(EXEEXT)
+ $(LINK) $(seg_override_OBJECTS) $(seg_override_LDADD) $(LIBS)
+sigcontext$(EXEEXT): $(sigcontext_OBJECTS) $(sigcontext_DEPENDENCIES)
+ @rm -f sigcontext$(EXEEXT)
+ $(LINK) $(sigcontext_OBJECTS) $(sigcontext_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/seg_override.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sigcontext.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/x86/Makefile.am b/main/none/tests/x86/Makefile.am
index 74affee..99b2fa0 100644
--- a/main/none/tests/x86/Makefile.am
+++ b/main/none/tests/x86/Makefile.am
@@ -65,6 +65,7 @@
check_PROGRAMS = \
aad_aam \
+ allexec \
badseg \
bt_everything \
bt_literal \
@@ -109,6 +110,8 @@
AM_CXXFLAGS += @FLAG_M32@ $(FLAG_MMMX) $(FLAG_MSSE)
AM_CCASFLAGS += @FLAG_M32@
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+
if VGCONF_OS_IS_DARWIN
# Some of the tests (bug125959_x86, bug152818_x86, insn_*) need
# -mdynamic-no-pic. I tried setting *_CFLAGS separately for all of them,
diff --git a/main/none/tests/x86/Makefile.in b/main/none/tests/x86/Makefile.in
new file mode 100644
index 0000000..07bee25
--- /dev/null
+++ b/main/none/tests/x86/Makefile.in
@@ -0,0 +1,1203 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+ $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_1 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+@BUILD_SSE3_TESTS_TRUE@am__append_3 = insn_sse3
+@BUILD_SSSE3_TESTS_TRUE@am__append_4 = insn_ssse3
+check_PROGRAMS = aad_aam$(EXEEXT) allexec$(EXEEXT) badseg$(EXEEXT) \
+ bt_everything$(EXEEXT) bt_literal$(EXEEXT) \
+ bug125959-x86$(EXEEXT) bug126147-x86$(EXEEXT) \
+ bug132813-x86$(EXEEXT) bug135421-x86$(EXEEXT) \
+ bug137714-x86$(EXEEXT) bug152818-x86$(EXEEXT) \
+ cmpxchg8b$(EXEEXT) cpuid$(EXEEXT) fcmovnu$(EXEEXT) \
+ fpu_lazy_eflags$(EXEEXT) fxtract$(EXEEXT) getseg$(EXEEXT) \
+ incdec_alt$(EXEEXT) $(am__EXEEXT_3) int$(EXEEXT) jcxz$(EXEEXT) \
+ lahf$(EXEEXT) looper$(EXEEXT) movx$(EXEEXT) \
+ pushpopseg$(EXEEXT) sbbmisc$(EXEEXT) shift_ndep$(EXEEXT) \
+ smc1$(EXEEXT) x86locked$(EXEEXT) yield$(EXEEXT) xadd$(EXEEXT) \
+ $(am__EXEEXT_4) $(am__EXEEXT_5) $(am__EXEEXT_6)
+@BUILD_SSSE3_TESTS_TRUE@am__append_5 = ssse3_misaligned
+@BUILD_LZCNT_TESTS_TRUE@am__append_6 = lzcnt32
+@VGCONF_OS_IS_DARWIN_FALSE@am__append_7 = cse_fail faultstatus
+
+# Some of the tests (bug125959_x86, bug152818_x86, insn_*) need
+# -mdynamic-no-pic. I tried setting *_CFLAGS separately for all of them,
+# but it caused problems with the generation of insn_*.c. So just use this
+# crude approach of setting -mdynamic-no-pic for all tests in this
+# directory.
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_8 = -mdynamic-no-pic
+subdir = none/tests/x86
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@BUILD_SSE3_TESTS_TRUE@am__EXEEXT_1 = insn_sse3$(EXEEXT)
+@BUILD_SSSE3_TESTS_TRUE@am__EXEEXT_2 = insn_ssse3$(EXEEXT)
+am__EXEEXT_3 = insn_basic$(EXEEXT) insn_fpu$(EXEEXT) \
+ insn_cmov$(EXEEXT) insn_mmx$(EXEEXT) insn_mmxext$(EXEEXT) \
+ insn_sse$(EXEEXT) insn_sse2$(EXEEXT) $(am__EXEEXT_1) \
+ $(am__EXEEXT_2)
+@BUILD_SSSE3_TESTS_TRUE@am__EXEEXT_4 = ssse3_misaligned$(EXEEXT)
+@BUILD_LZCNT_TESTS_TRUE@am__EXEEXT_5 = lzcnt32$(EXEEXT)
+@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_6 = cse_fail$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ faultstatus$(EXEEXT)
+aad_aam_SOURCES = aad_aam.c
+aad_aam_OBJECTS = aad_aam.$(OBJEXT)
+aad_aam_LDADD = $(LDADD)
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+badseg_SOURCES = badseg.c
+badseg_OBJECTS = badseg.$(OBJEXT)
+badseg_LDADD = $(LDADD)
+bt_everything_SOURCES = bt_everything.c
+bt_everything_OBJECTS = bt_everything.$(OBJEXT)
+bt_everything_LDADD = $(LDADD)
+bt_literal_SOURCES = bt_literal.c
+bt_literal_OBJECTS = bt_literal.$(OBJEXT)
+bt_literal_LDADD = $(LDADD)
+bug125959_x86_SOURCES = bug125959-x86.c
+bug125959_x86_OBJECTS = bug125959-x86.$(OBJEXT)
+bug125959_x86_LDADD = $(LDADD)
+bug126147_x86_SOURCES = bug126147-x86.c
+bug126147_x86_OBJECTS = bug126147-x86.$(OBJEXT)
+bug126147_x86_LDADD = $(LDADD)
+bug132813_x86_SOURCES = bug132813-x86.c
+bug132813_x86_OBJECTS = bug132813-x86.$(OBJEXT)
+bug132813_x86_LDADD = $(LDADD)
+bug135421_x86_SOURCES = bug135421-x86.c
+bug135421_x86_OBJECTS = bug135421-x86.$(OBJEXT)
+bug135421_x86_LDADD = $(LDADD)
+bug137714_x86_SOURCES = bug137714-x86.c
+bug137714_x86_OBJECTS = bug137714-x86.$(OBJEXT)
+bug137714_x86_LDADD = $(LDADD)
+bug152818_x86_SOURCES = bug152818-x86.c
+bug152818_x86_OBJECTS = bug152818-x86.$(OBJEXT)
+bug152818_x86_LDADD = $(LDADD)
+cmpxchg8b_SOURCES = cmpxchg8b.c
+cmpxchg8b_OBJECTS = cmpxchg8b.$(OBJEXT)
+cmpxchg8b_LDADD = $(LDADD)
+am_cpuid_OBJECTS = cpuid_c.$(OBJEXT) cpuid_s.$(OBJEXT)
+cpuid_OBJECTS = $(am_cpuid_OBJECTS)
+cpuid_LDADD = $(LDADD)
+cse_fail_SOURCES = cse_fail.c
+cse_fail_OBJECTS = cse_fail.$(OBJEXT)
+cse_fail_LDADD = $(LDADD)
+faultstatus_SOURCES = faultstatus.c
+faultstatus_OBJECTS = faultstatus.$(OBJEXT)
+faultstatus_LDADD = $(LDADD)
+fcmovnu_SOURCES = fcmovnu.c
+fcmovnu_OBJECTS = fcmovnu.$(OBJEXT)
+fcmovnu_LDADD = $(LDADD)
+fpu_lazy_eflags_SOURCES = fpu_lazy_eflags.c
+fpu_lazy_eflags_OBJECTS = fpu_lazy_eflags-fpu_lazy_eflags.$(OBJEXT)
+fpu_lazy_eflags_LDADD = $(LDADD)
+fpu_lazy_eflags_LINK = $(CCLD) $(fpu_lazy_eflags_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+fxtract_SOURCES = fxtract.c
+fxtract_OBJECTS = fxtract-fxtract.$(OBJEXT)
+fxtract_DEPENDENCIES =
+fxtract_LINK = $(CCLD) $(fxtract_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+getseg_SOURCES = getseg.c
+getseg_OBJECTS = getseg.$(OBJEXT)
+getseg_LDADD = $(LDADD)
+incdec_alt_SOURCES = incdec_alt.c
+incdec_alt_OBJECTS = incdec_alt.$(OBJEXT)
+incdec_alt_LDADD = $(LDADD)
+am_insn_basic_OBJECTS = insn_basic.$(OBJEXT)
+insn_basic_OBJECTS = $(am_insn_basic_OBJECTS)
+insn_basic_DEPENDENCIES =
+am_insn_cmov_OBJECTS = insn_cmov.$(OBJEXT)
+insn_cmov_OBJECTS = $(am_insn_cmov_OBJECTS)
+insn_cmov_DEPENDENCIES =
+am_insn_fpu_OBJECTS = insn_fpu.$(OBJEXT)
+insn_fpu_OBJECTS = $(am_insn_fpu_OBJECTS)
+insn_fpu_DEPENDENCIES =
+am_insn_mmx_OBJECTS = insn_mmx.$(OBJEXT)
+insn_mmx_OBJECTS = $(am_insn_mmx_OBJECTS)
+insn_mmx_DEPENDENCIES =
+am_insn_mmxext_OBJECTS = insn_mmxext.$(OBJEXT)
+insn_mmxext_OBJECTS = $(am_insn_mmxext_OBJECTS)
+insn_mmxext_DEPENDENCIES =
+am_insn_sse_OBJECTS = insn_sse.$(OBJEXT)
+insn_sse_OBJECTS = $(am_insn_sse_OBJECTS)
+insn_sse_DEPENDENCIES =
+am_insn_sse2_OBJECTS = insn_sse2.$(OBJEXT)
+insn_sse2_OBJECTS = $(am_insn_sse2_OBJECTS)
+insn_sse2_DEPENDENCIES =
+am_insn_sse3_OBJECTS = insn_sse3.$(OBJEXT)
+insn_sse3_OBJECTS = $(am_insn_sse3_OBJECTS)
+insn_sse3_DEPENDENCIES =
+am_insn_ssse3_OBJECTS = insn_ssse3.$(OBJEXT)
+insn_ssse3_OBJECTS = $(am_insn_ssse3_OBJECTS)
+insn_ssse3_DEPENDENCIES =
+int_SOURCES = int.c
+int_OBJECTS = int.$(OBJEXT)
+int_LDADD = $(LDADD)
+jcxz_SOURCES = jcxz.c
+jcxz_OBJECTS = jcxz.$(OBJEXT)
+jcxz_LDADD = $(LDADD)
+lahf_SOURCES = lahf.c
+lahf_OBJECTS = lahf.$(OBJEXT)
+lahf_LDADD = $(LDADD)
+looper_SOURCES = looper.c
+looper_OBJECTS = looper.$(OBJEXT)
+looper_LDADD = $(LDADD)
+lzcnt32_SOURCES = lzcnt32.c
+lzcnt32_OBJECTS = lzcnt32.$(OBJEXT)
+lzcnt32_LDADD = $(LDADD)
+movx_SOURCES = movx.c
+movx_OBJECTS = movx.$(OBJEXT)
+movx_LDADD = $(LDADD)
+pushpopseg_SOURCES = pushpopseg.c
+pushpopseg_OBJECTS = pushpopseg.$(OBJEXT)
+pushpopseg_LDADD = $(LDADD)
+sbbmisc_SOURCES = sbbmisc.c
+sbbmisc_OBJECTS = sbbmisc.$(OBJEXT)
+sbbmisc_LDADD = $(LDADD)
+shift_ndep_SOURCES = shift_ndep.c
+shift_ndep_OBJECTS = shift_ndep.$(OBJEXT)
+shift_ndep_LDADD = $(LDADD)
+smc1_SOURCES = smc1.c
+smc1_OBJECTS = smc1.$(OBJEXT)
+smc1_LDADD = $(LDADD)
+ssse3_misaligned_SOURCES = ssse3_misaligned.c
+ssse3_misaligned_OBJECTS = ssse3_misaligned.$(OBJEXT)
+ssse3_misaligned_LDADD = $(LDADD)
+x86locked_SOURCES = x86locked.c
+x86locked_OBJECTS = x86locked-x86locked.$(OBJEXT)
+x86locked_LDADD = $(LDADD)
+x86locked_LINK = $(CCLD) $(x86locked_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+xadd_SOURCES = xadd.c
+xadd_OBJECTS = xadd.$(OBJEXT)
+xadd_LDADD = $(LDADD)
+yield_SOURCES = yield.c
+yield_OBJECTS = yield.$(OBJEXT)
+yield_DEPENDENCIES =
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+CPPASCOMPILE = $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CCASFLAGS) $(CCASFLAGS)
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = aad_aam.c allexec.c badseg.c bt_everything.c bt_literal.c \
+ bug125959-x86.c bug126147-x86.c bug132813-x86.c \
+ bug135421-x86.c bug137714-x86.c bug152818-x86.c cmpxchg8b.c \
+ $(cpuid_SOURCES) cse_fail.c faultstatus.c fcmovnu.c \
+ fpu_lazy_eflags.c fxtract.c getseg.c incdec_alt.c \
+ $(insn_basic_SOURCES) $(insn_cmov_SOURCES) $(insn_fpu_SOURCES) \
+ $(insn_mmx_SOURCES) $(insn_mmxext_SOURCES) $(insn_sse_SOURCES) \
+ $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
+ $(insn_ssse3_SOURCES) int.c jcxz.c lahf.c looper.c lzcnt32.c \
+ movx.c pushpopseg.c sbbmisc.c shift_ndep.c smc1.c \
+ ssse3_misaligned.c x86locked.c xadd.c yield.c
+DIST_SOURCES = aad_aam.c allexec.c badseg.c bt_everything.c \
+ bt_literal.c bug125959-x86.c bug126147-x86.c bug132813-x86.c \
+ bug135421-x86.c bug137714-x86.c bug152818-x86.c cmpxchg8b.c \
+ $(cpuid_SOURCES) cse_fail.c faultstatus.c fcmovnu.c \
+ fpu_lazy_eflags.c fxtract.c getseg.c incdec_alt.c \
+ $(insn_basic_SOURCES) $(insn_cmov_SOURCES) $(insn_fpu_SOURCES) \
+ $(insn_mmx_SOURCES) $(insn_mmxext_SOURCES) $(insn_sse_SOURCES) \
+ $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
+ $(insn_ssse3_SOURCES) int.c jcxz.c lahf.c looper.c lzcnt32.c \
+ movx.c pushpopseg.c sbbmisc.c shift_ndep.c smc1.c \
+ ssse3_misaligned.c x86locked.c xadd.c yield.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = \
+ -O2 -g \
+ -Wall \
+ -Wmissing-prototypes \
+ -Wshadow \
+ -Wpointer-arith \
+ -Wstrict-prototypes \
+ -Wmissing-declarations \
+ @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+ -fno-strict-aliasing \
+ -fno-builtin
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fno-builtin
+
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -mno-dynamic-no-pic -fpic -fPIC \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fno-builtin
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_1)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_2)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE) $(am__append_8)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M32@ $(FLAG_MMMX) \
+ $(FLAG_MSSE)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_cpuid filter_stderr gen_insn_test.pl
+CLEANFILES = $(addsuffix .c,$(INSN_TESTS))
+INSN_TESTS = insn_basic insn_fpu insn_cmov insn_mmx insn_mmxext \
+ insn_sse insn_sse2 $(am__append_3) $(am__append_4)
+
+# Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS,
+# to avoid packaging screwups if 'make dist' is run on a machine
+# which failed the BUILD_SSE3_TESTS test in configure.in.
+EXTRA_DIST = \
+ aad_aam.stdout.exp aad_aam.stderr.exp aad_aam.vgtest \
+ badseg.stderr.exp badseg.stdout.exp badseg.vgtest \
+ bt_everything.stderr.exp bt_everything.stdout.exp bt_everything.vgtest \
+ bt_literal.stderr.exp bt_literal.stdout.exp bt_literal.vgtest \
+ bug125959-x86.stderr.exp bug125959-x86.stdout.exp bug125959-x86.vgtest \
+ bug126147-x86.stderr.exp bug126147-x86.stdout.exp bug126147-x86.vgtest \
+ bug132813-x86.stderr.exp bug132813-x86.stdout.exp bug132813-x86.vgtest \
+ bug135421-x86.stderr.exp bug135421-x86.stdout.exp bug135421-x86.vgtest \
+ bug137714-x86.stderr.exp bug137714-x86.stdout.exp bug137714-x86.vgtest \
+ bug152818-x86.stderr.exp bug152818-x86.stdout.exp bug152818-x86.vgtest \
+ cmpxchg8b.stderr.exp cmpxchg8b.stdout.exp cmpxchg8b.vgtest \
+ cpuid.stderr.exp cpuid.stdout.exp cpuid.vgtest \
+ cse_fail.stderr.exp cse_fail.stdout.exp cse_fail.vgtest \
+ faultstatus.disabled faultstatus.stderr.exp \
+ fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \
+ fpu_lazy_eflags.stderr.exp fpu_lazy_eflags.stdout.exp \
+ fpu_lazy_eflags.vgtest \
+ fxtract.stdout.exp fxtract.stderr.exp fxtract.vgtest \
+ fxtract.stdout.exp-older-glibc \
+ getseg.stdout.exp getseg.stderr.exp getseg.vgtest \
+ incdec_alt.stdout.exp incdec_alt.stderr.exp incdec_alt.vgtest \
+ int.stderr.exp int.stdout.exp int.disabled \
+ $(addsuffix .stderr.exp,$(INSN_TESTS)) \
+ $(addsuffix .stdout.exp,$(INSN_TESTS)) \
+ $(addsuffix .vgtest,$(INSN_TESTS)) \
+ insn_sse3.stdout.exp insn_sse3.stderr.exp insn_sse3.vgtest \
+ insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
+ jcxz.stdout.exp jcxz.stderr.exp jcxz.vgtest \
+ lahf.stdout.exp lahf.stderr.exp lahf.vgtest \
+ looper.stderr.exp looper.stdout.exp looper.vgtest \
+ lzcnt32.stderr.exp lzcnt32.stdout.exp lzcnt32.vgtest \
+ movx.stderr.exp movx.stdout.exp movx.vgtest \
+ pushpopseg.stderr.exp pushpopseg.stdout.exp pushpopseg.vgtest \
+ sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \
+ shift_ndep.stderr.exp shift_ndep.stdout.exp shift_ndep.vgtest \
+ smc1.stderr.exp smc1.stdout.exp smc1.vgtest \
+ ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
+ ssse3_misaligned.vgtest ssse3_misaligned.c \
+ x86locked.vgtest x86locked.stdout.exp x86locked.stderr.exp \
+ yield.stderr.exp yield.stdout.exp yield.disabled \
+ xadd.stdout.exp xadd.stderr.exp xadd.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+cpuid_SOURCES = cpuid_c.c cpuid_s.S
+# fpu_lazy_eflags must use these flags -- the bug only occurred with them.
+fpu_lazy_eflags_CFLAGS = $(AM_CFLAGS) -O2 -march=pentiumpro
+fxtract_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_OVERFLOW@
+fxtract_LDADD = -lm
+insn_basic_SOURCES = insn_basic.def
+insn_basic_LDADD = -lm
+insn_fpu_SOURCES = insn_fpu.def
+insn_fpu_LDADD = -lm
+insn_cmov_SOURCES = insn_cmov.def
+insn_cmov_LDADD = -lm
+insn_mmx_SOURCES = insn_mmx.def
+insn_mmx_LDADD = -lm
+insn_mmxext_SOURCES = insn_mmxext.def
+insn_mmxext_LDADD = -lm
+insn_sse_SOURCES = insn_sse.def
+insn_sse_LDADD = -lm
+insn_sse2_SOURCES = insn_sse2.def
+insn_sse2_LDADD = -lm
+insn_sse3_SOURCES = insn_sse3.def
+insn_sse3_LDADD = -lm
+insn_ssse3_SOURCES = insn_ssse3.def
+insn_ssse3_LDADD = -lm
+x86locked_CFLAGS = $(AM_CFLAGS) -O
+yield_LDADD = -lpthread
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .S .c .def .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/x86/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/x86/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+aad_aam$(EXEEXT): $(aad_aam_OBJECTS) $(aad_aam_DEPENDENCIES)
+ @rm -f aad_aam$(EXEEXT)
+ $(LINK) $(aad_aam_OBJECTS) $(aad_aam_LDADD) $(LIBS)
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+badseg$(EXEEXT): $(badseg_OBJECTS) $(badseg_DEPENDENCIES)
+ @rm -f badseg$(EXEEXT)
+ $(LINK) $(badseg_OBJECTS) $(badseg_LDADD) $(LIBS)
+bt_everything$(EXEEXT): $(bt_everything_OBJECTS) $(bt_everything_DEPENDENCIES)
+ @rm -f bt_everything$(EXEEXT)
+ $(LINK) $(bt_everything_OBJECTS) $(bt_everything_LDADD) $(LIBS)
+bt_literal$(EXEEXT): $(bt_literal_OBJECTS) $(bt_literal_DEPENDENCIES)
+ @rm -f bt_literal$(EXEEXT)
+ $(LINK) $(bt_literal_OBJECTS) $(bt_literal_LDADD) $(LIBS)
+bug125959-x86$(EXEEXT): $(bug125959_x86_OBJECTS) $(bug125959_x86_DEPENDENCIES)
+ @rm -f bug125959-x86$(EXEEXT)
+ $(LINK) $(bug125959_x86_OBJECTS) $(bug125959_x86_LDADD) $(LIBS)
+bug126147-x86$(EXEEXT): $(bug126147_x86_OBJECTS) $(bug126147_x86_DEPENDENCIES)
+ @rm -f bug126147-x86$(EXEEXT)
+ $(LINK) $(bug126147_x86_OBJECTS) $(bug126147_x86_LDADD) $(LIBS)
+bug132813-x86$(EXEEXT): $(bug132813_x86_OBJECTS) $(bug132813_x86_DEPENDENCIES)
+ @rm -f bug132813-x86$(EXEEXT)
+ $(LINK) $(bug132813_x86_OBJECTS) $(bug132813_x86_LDADD) $(LIBS)
+bug135421-x86$(EXEEXT): $(bug135421_x86_OBJECTS) $(bug135421_x86_DEPENDENCIES)
+ @rm -f bug135421-x86$(EXEEXT)
+ $(LINK) $(bug135421_x86_OBJECTS) $(bug135421_x86_LDADD) $(LIBS)
+bug137714-x86$(EXEEXT): $(bug137714_x86_OBJECTS) $(bug137714_x86_DEPENDENCIES)
+ @rm -f bug137714-x86$(EXEEXT)
+ $(LINK) $(bug137714_x86_OBJECTS) $(bug137714_x86_LDADD) $(LIBS)
+bug152818-x86$(EXEEXT): $(bug152818_x86_OBJECTS) $(bug152818_x86_DEPENDENCIES)
+ @rm -f bug152818-x86$(EXEEXT)
+ $(LINK) $(bug152818_x86_OBJECTS) $(bug152818_x86_LDADD) $(LIBS)
+cmpxchg8b$(EXEEXT): $(cmpxchg8b_OBJECTS) $(cmpxchg8b_DEPENDENCIES)
+ @rm -f cmpxchg8b$(EXEEXT)
+ $(LINK) $(cmpxchg8b_OBJECTS) $(cmpxchg8b_LDADD) $(LIBS)
+cpuid$(EXEEXT): $(cpuid_OBJECTS) $(cpuid_DEPENDENCIES)
+ @rm -f cpuid$(EXEEXT)
+ $(LINK) $(cpuid_OBJECTS) $(cpuid_LDADD) $(LIBS)
+cse_fail$(EXEEXT): $(cse_fail_OBJECTS) $(cse_fail_DEPENDENCIES)
+ @rm -f cse_fail$(EXEEXT)
+ $(LINK) $(cse_fail_OBJECTS) $(cse_fail_LDADD) $(LIBS)
+faultstatus$(EXEEXT): $(faultstatus_OBJECTS) $(faultstatus_DEPENDENCIES)
+ @rm -f faultstatus$(EXEEXT)
+ $(LINK) $(faultstatus_OBJECTS) $(faultstatus_LDADD) $(LIBS)
+fcmovnu$(EXEEXT): $(fcmovnu_OBJECTS) $(fcmovnu_DEPENDENCIES)
+ @rm -f fcmovnu$(EXEEXT)
+ $(LINK) $(fcmovnu_OBJECTS) $(fcmovnu_LDADD) $(LIBS)
+fpu_lazy_eflags$(EXEEXT): $(fpu_lazy_eflags_OBJECTS) $(fpu_lazy_eflags_DEPENDENCIES)
+ @rm -f fpu_lazy_eflags$(EXEEXT)
+ $(fpu_lazy_eflags_LINK) $(fpu_lazy_eflags_OBJECTS) $(fpu_lazy_eflags_LDADD) $(LIBS)
+fxtract$(EXEEXT): $(fxtract_OBJECTS) $(fxtract_DEPENDENCIES)
+ @rm -f fxtract$(EXEEXT)
+ $(fxtract_LINK) $(fxtract_OBJECTS) $(fxtract_LDADD) $(LIBS)
+getseg$(EXEEXT): $(getseg_OBJECTS) $(getseg_DEPENDENCIES)
+ @rm -f getseg$(EXEEXT)
+ $(LINK) $(getseg_OBJECTS) $(getseg_LDADD) $(LIBS)
+incdec_alt$(EXEEXT): $(incdec_alt_OBJECTS) $(incdec_alt_DEPENDENCIES)
+ @rm -f incdec_alt$(EXEEXT)
+ $(LINK) $(incdec_alt_OBJECTS) $(incdec_alt_LDADD) $(LIBS)
+insn_basic$(EXEEXT): $(insn_basic_OBJECTS) $(insn_basic_DEPENDENCIES)
+ @rm -f insn_basic$(EXEEXT)
+ $(LINK) $(insn_basic_OBJECTS) $(insn_basic_LDADD) $(LIBS)
+insn_cmov$(EXEEXT): $(insn_cmov_OBJECTS) $(insn_cmov_DEPENDENCIES)
+ @rm -f insn_cmov$(EXEEXT)
+ $(LINK) $(insn_cmov_OBJECTS) $(insn_cmov_LDADD) $(LIBS)
+insn_fpu$(EXEEXT): $(insn_fpu_OBJECTS) $(insn_fpu_DEPENDENCIES)
+ @rm -f insn_fpu$(EXEEXT)
+ $(LINK) $(insn_fpu_OBJECTS) $(insn_fpu_LDADD) $(LIBS)
+insn_mmx$(EXEEXT): $(insn_mmx_OBJECTS) $(insn_mmx_DEPENDENCIES)
+ @rm -f insn_mmx$(EXEEXT)
+ $(LINK) $(insn_mmx_OBJECTS) $(insn_mmx_LDADD) $(LIBS)
+insn_mmxext$(EXEEXT): $(insn_mmxext_OBJECTS) $(insn_mmxext_DEPENDENCIES)
+ @rm -f insn_mmxext$(EXEEXT)
+ $(LINK) $(insn_mmxext_OBJECTS) $(insn_mmxext_LDADD) $(LIBS)
+insn_sse$(EXEEXT): $(insn_sse_OBJECTS) $(insn_sse_DEPENDENCIES)
+ @rm -f insn_sse$(EXEEXT)
+ $(LINK) $(insn_sse_OBJECTS) $(insn_sse_LDADD) $(LIBS)
+insn_sse2$(EXEEXT): $(insn_sse2_OBJECTS) $(insn_sse2_DEPENDENCIES)
+ @rm -f insn_sse2$(EXEEXT)
+ $(LINK) $(insn_sse2_OBJECTS) $(insn_sse2_LDADD) $(LIBS)
+insn_sse3$(EXEEXT): $(insn_sse3_OBJECTS) $(insn_sse3_DEPENDENCIES)
+ @rm -f insn_sse3$(EXEEXT)
+ $(LINK) $(insn_sse3_OBJECTS) $(insn_sse3_LDADD) $(LIBS)
+insn_ssse3$(EXEEXT): $(insn_ssse3_OBJECTS) $(insn_ssse3_DEPENDENCIES)
+ @rm -f insn_ssse3$(EXEEXT)
+ $(LINK) $(insn_ssse3_OBJECTS) $(insn_ssse3_LDADD) $(LIBS)
+int$(EXEEXT): $(int_OBJECTS) $(int_DEPENDENCIES)
+ @rm -f int$(EXEEXT)
+ $(LINK) $(int_OBJECTS) $(int_LDADD) $(LIBS)
+jcxz$(EXEEXT): $(jcxz_OBJECTS) $(jcxz_DEPENDENCIES)
+ @rm -f jcxz$(EXEEXT)
+ $(LINK) $(jcxz_OBJECTS) $(jcxz_LDADD) $(LIBS)
+lahf$(EXEEXT): $(lahf_OBJECTS) $(lahf_DEPENDENCIES)
+ @rm -f lahf$(EXEEXT)
+ $(LINK) $(lahf_OBJECTS) $(lahf_LDADD) $(LIBS)
+looper$(EXEEXT): $(looper_OBJECTS) $(looper_DEPENDENCIES)
+ @rm -f looper$(EXEEXT)
+ $(LINK) $(looper_OBJECTS) $(looper_LDADD) $(LIBS)
+lzcnt32$(EXEEXT): $(lzcnt32_OBJECTS) $(lzcnt32_DEPENDENCIES)
+ @rm -f lzcnt32$(EXEEXT)
+ $(LINK) $(lzcnt32_OBJECTS) $(lzcnt32_LDADD) $(LIBS)
+movx$(EXEEXT): $(movx_OBJECTS) $(movx_DEPENDENCIES)
+ @rm -f movx$(EXEEXT)
+ $(LINK) $(movx_OBJECTS) $(movx_LDADD) $(LIBS)
+pushpopseg$(EXEEXT): $(pushpopseg_OBJECTS) $(pushpopseg_DEPENDENCIES)
+ @rm -f pushpopseg$(EXEEXT)
+ $(LINK) $(pushpopseg_OBJECTS) $(pushpopseg_LDADD) $(LIBS)
+sbbmisc$(EXEEXT): $(sbbmisc_OBJECTS) $(sbbmisc_DEPENDENCIES)
+ @rm -f sbbmisc$(EXEEXT)
+ $(LINK) $(sbbmisc_OBJECTS) $(sbbmisc_LDADD) $(LIBS)
+shift_ndep$(EXEEXT): $(shift_ndep_OBJECTS) $(shift_ndep_DEPENDENCIES)
+ @rm -f shift_ndep$(EXEEXT)
+ $(LINK) $(shift_ndep_OBJECTS) $(shift_ndep_LDADD) $(LIBS)
+smc1$(EXEEXT): $(smc1_OBJECTS) $(smc1_DEPENDENCIES)
+ @rm -f smc1$(EXEEXT)
+ $(LINK) $(smc1_OBJECTS) $(smc1_LDADD) $(LIBS)
+ssse3_misaligned$(EXEEXT): $(ssse3_misaligned_OBJECTS) $(ssse3_misaligned_DEPENDENCIES)
+ @rm -f ssse3_misaligned$(EXEEXT)
+ $(LINK) $(ssse3_misaligned_OBJECTS) $(ssse3_misaligned_LDADD) $(LIBS)
+x86locked$(EXEEXT): $(x86locked_OBJECTS) $(x86locked_DEPENDENCIES)
+ @rm -f x86locked$(EXEEXT)
+ $(x86locked_LINK) $(x86locked_OBJECTS) $(x86locked_LDADD) $(LIBS)
+xadd$(EXEEXT): $(xadd_OBJECTS) $(xadd_DEPENDENCIES)
+ @rm -f xadd$(EXEEXT)
+ $(LINK) $(xadd_OBJECTS) $(xadd_LDADD) $(LIBS)
+yield$(EXEEXT): $(yield_OBJECTS) $(yield_DEPENDENCIES)
+ @rm -f yield$(EXEEXT)
+ $(LINK) $(yield_OBJECTS) $(yield_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aad_aam.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/badseg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bt_everything.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bt_literal.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug125959-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug126147-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132813-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug135421-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug137714-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug152818-x86.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cmpxchg8b.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpuid_c.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpuid_s.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cse_fail.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/faultstatus.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fcmovnu.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fpu_lazy_eflags-fpu_lazy_eflags.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxtract-fxtract.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/getseg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/incdec_alt.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_basic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_cmov.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_fpu.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_mmx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_mmxext.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_sse.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_sse2.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_sse3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_ssse3.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/int.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jcxz.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lahf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/looper.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lzcnt32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/movx.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pushpopseg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sbbmisc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shift_ndep.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/smc1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ssse3_misaligned.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/x86locked-x86locked.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xadd.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/yield.Po@am__quote@
+
+.S.o:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ $<
+
+.S.obj:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@ $(CPPASCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+.c.o:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'`
+
+allexec-allexec.o: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.o -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+
+allexec-allexec.obj: allexec.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.obj -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='allexec.c' object='allexec-allexec.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+
+fpu_lazy_eflags-fpu_lazy_eflags.o: fpu_lazy_eflags.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fpu_lazy_eflags_CFLAGS) $(CFLAGS) -MT fpu_lazy_eflags-fpu_lazy_eflags.o -MD -MP -MF $(DEPDIR)/fpu_lazy_eflags-fpu_lazy_eflags.Tpo -c -o fpu_lazy_eflags-fpu_lazy_eflags.o `test -f 'fpu_lazy_eflags.c' || echo '$(srcdir)/'`fpu_lazy_eflags.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/fpu_lazy_eflags-fpu_lazy_eflags.Tpo $(DEPDIR)/fpu_lazy_eflags-fpu_lazy_eflags.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fpu_lazy_eflags.c' object='fpu_lazy_eflags-fpu_lazy_eflags.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fpu_lazy_eflags_CFLAGS) $(CFLAGS) -c -o fpu_lazy_eflags-fpu_lazy_eflags.o `test -f 'fpu_lazy_eflags.c' || echo '$(srcdir)/'`fpu_lazy_eflags.c
+
+fpu_lazy_eflags-fpu_lazy_eflags.obj: fpu_lazy_eflags.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fpu_lazy_eflags_CFLAGS) $(CFLAGS) -MT fpu_lazy_eflags-fpu_lazy_eflags.obj -MD -MP -MF $(DEPDIR)/fpu_lazy_eflags-fpu_lazy_eflags.Tpo -c -o fpu_lazy_eflags-fpu_lazy_eflags.obj `if test -f 'fpu_lazy_eflags.c'; then $(CYGPATH_W) 'fpu_lazy_eflags.c'; else $(CYGPATH_W) '$(srcdir)/fpu_lazy_eflags.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/fpu_lazy_eflags-fpu_lazy_eflags.Tpo $(DEPDIR)/fpu_lazy_eflags-fpu_lazy_eflags.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fpu_lazy_eflags.c' object='fpu_lazy_eflags-fpu_lazy_eflags.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fpu_lazy_eflags_CFLAGS) $(CFLAGS) -c -o fpu_lazy_eflags-fpu_lazy_eflags.obj `if test -f 'fpu_lazy_eflags.c'; then $(CYGPATH_W) 'fpu_lazy_eflags.c'; else $(CYGPATH_W) '$(srcdir)/fpu_lazy_eflags.c'; fi`
+
+fxtract-fxtract.o: fxtract.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxtract_CFLAGS) $(CFLAGS) -MT fxtract-fxtract.o -MD -MP -MF $(DEPDIR)/fxtract-fxtract.Tpo -c -o fxtract-fxtract.o `test -f 'fxtract.c' || echo '$(srcdir)/'`fxtract.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/fxtract-fxtract.Tpo $(DEPDIR)/fxtract-fxtract.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fxtract.c' object='fxtract-fxtract.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxtract_CFLAGS) $(CFLAGS) -c -o fxtract-fxtract.o `test -f 'fxtract.c' || echo '$(srcdir)/'`fxtract.c
+
+fxtract-fxtract.obj: fxtract.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxtract_CFLAGS) $(CFLAGS) -MT fxtract-fxtract.obj -MD -MP -MF $(DEPDIR)/fxtract-fxtract.Tpo -c -o fxtract-fxtract.obj `if test -f 'fxtract.c'; then $(CYGPATH_W) 'fxtract.c'; else $(CYGPATH_W) '$(srcdir)/fxtract.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/fxtract-fxtract.Tpo $(DEPDIR)/fxtract-fxtract.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='fxtract.c' object='fxtract-fxtract.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxtract_CFLAGS) $(CFLAGS) -c -o fxtract-fxtract.obj `if test -f 'fxtract.c'; then $(CYGPATH_W) 'fxtract.c'; else $(CYGPATH_W) '$(srcdir)/fxtract.c'; fi`
+
+x86locked-x86locked.o: x86locked.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(x86locked_CFLAGS) $(CFLAGS) -MT x86locked-x86locked.o -MD -MP -MF $(DEPDIR)/x86locked-x86locked.Tpo -c -o x86locked-x86locked.o `test -f 'x86locked.c' || echo '$(srcdir)/'`x86locked.c
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/x86locked-x86locked.Tpo $(DEPDIR)/x86locked-x86locked.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='x86locked.c' object='x86locked-x86locked.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(x86locked_CFLAGS) $(CFLAGS) -c -o x86locked-x86locked.o `test -f 'x86locked.c' || echo '$(srcdir)/'`x86locked.c
+
+x86locked-x86locked.obj: x86locked.c
+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(x86locked_CFLAGS) $(CFLAGS) -MT x86locked-x86locked.obj -MD -MP -MF $(DEPDIR)/x86locked-x86locked.Tpo -c -o x86locked-x86locked.obj `if test -f 'x86locked.c'; then $(CYGPATH_W) 'x86locked.c'; else $(CYGPATH_W) '$(srcdir)/x86locked.c'; fi`
+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/x86locked-x86locked.Tpo $(DEPDIR)/x86locked-x86locked.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='x86locked.c' object='x86locked-x86locked.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(x86locked_CFLAGS) $(CFLAGS) -c -o x86locked-x86locked.obj `if test -f 'x86locked.c'; then $(CYGPATH_W) 'x86locked.c'; else $(CYGPATH_W) '$(srcdir)/x86locked.c'; fi`
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ mkid -fID $$unique
+tags: TAGS
+
+TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ set x; \
+ here=`pwd`; \
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: CTAGS
+CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
+ $(TAGS_FILES) $(LISP)
+ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | \
+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in files) print i; }; }'`; \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ `test -z '$(STRIP)' || \
+ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+ -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-data install-data-am install-dvi install-dvi-am \
+ install-exec install-exec-am install-html install-html-am \
+ install-info install-info-am install-man install-pdf \
+ install-pdf-am install-ps install-ps-am install-strip \
+ installcheck installcheck-am installdirs maintainer-clean \
+ maintainer-clean-generic mostlyclean mostlyclean-compile \
+ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+ uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+.def.c: $(srcdir)/gen_insn_test.pl
+ $(PERL) $(srcdir)/gen_insn_test.pl < $< > $@
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/x86/aad_aam.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/x86/aad_aam.stderr.exp
diff --git a/main/none/tests/x86/allexec.c b/main/none/tests/x86/allexec.c
new file mode 100644
index 0000000..b7177e8
--- /dev/null
+++ b/main/none/tests/x86/allexec.c
@@ -0,0 +1,50 @@
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+extern char **environ;
+
+#define S(...) (fprintf(stdout, __VA_ARGS__),fflush(stdout))
+#define FORKEXECWAIT(exec_call) do { \
+ int status;\
+ pid_t child = fork(); \
+ if (child == 0) {exec_call; perror ("exec failed");} \
+ else if (child == -1) perror ("cannot fork\n"); \
+ else if (child != wait (&status)) perror ("error waiting child"); \
+ else S("child exited\n"); \
+ } while (0)
+
+void test_allexec (char *exec)
+{
+ FORKEXECWAIT (execlp(exec, exec, NULL));
+ FORKEXECWAIT (execlp(exec, exec, "constant_arg1", "constant_arg2", NULL));
+ FORKEXECWAIT (execve(exec, NULL, environ));
+}
+
+
+/* If a single argument "exec" is given, will execute itself
+ (in bi-arch, a 32 bit and 64 bit variant) via various exec system calls.
+ Note that this test can only be run after the prerequisite have been
+ prepared by allexec_prepare_prereq, which will a.o. make links
+ for the allexec32 and allexec64 executables. On single arch build,
+ these links points to the same executable to ensure this test works
+ everywhere the same.
+ No arguments or more arguments means just print its args. */
+int main(int argc, char **argv, char **envp)
+{
+ if ( (argc == 2) && (strcmp (argv[1], "exec") == 0)) {
+ S("%s will exec ./allexec32\n", argv[0]);
+ test_allexec ("./allexec32");
+ S("%s will exec ./allexec64\n", argv[0]);
+ test_allexec ("./allexec64");
+ } else {
+ int i;
+ S("program exec-ed:");
+ for (i = 0; i < argc; i++) S(" %s", argv[i]);
+ S("\n");
+ }
+ return 0;
+}
diff --git a/main/none/tests/x86/bug125959-x86.c b/main/none/tests/x86/bug125959-x86.c
index 96a04e2..2f4f09c 100644
--- a/main/none/tests/x86/bug125959-x86.c
+++ b/main/none/tests/x86/bug125959-x86.c
@@ -22,7 +22,9 @@
int main(void)
{
- int i, j;
+ int i;
+ unsigned j;
+
for (i = 0; i < 256; i++)
buf[i] = (unsigned char) i;
diff --git a/main/none/tests/x86/fxtract.stdout.exp-older-glibc b/main/none/tests/x86/fxtract.stdout.exp-older-glibc
new file mode 100644
index 0000000..4508fd6
--- /dev/null
+++ b/main/none/tests/x86/fxtract.stdout.exp-older-glibc
@@ -0,0 +1,131 @@
+-2.8104666125e+02 -> -1.0978385205 8.0000000000
+-2.6690452563e+02 -> -1.0425958032 8.0000000000
+-2.5276239000e+02 -> -1.9747061719 7.0000000000
+-2.3862025438e+02 -> -1.8642207373 7.0000000000
+-2.2447811876e+02 -> -1.7537353028 7.0000000000
+-2.1033598313e+02 -> -1.6432498682 7.0000000000
+-1.9619384751e+02 -> -1.5327644337 7.0000000000
+-1.8205171188e+02 -> -1.4222789991 7.0000000000
+-1.6790957626e+02 -> -1.3117935645 7.0000000000
+-1.5376744064e+02 -> -1.2013081300 7.0000000000
+-1.3962530501e+02 -> -1.0908226954 7.0000000000
+-1.2548316939e+02 -> -1.9606745217 6.0000000000
+-1.1134103377e+02 -> -1.7397036526 6.0000000000
+-9.7198898142e+01 -> -1.5187327835 6.0000000000
+-8.3056762518e+01 -> -1.2977619143 6.0000000000
+-6.8914626894e+01 -> -1.0767910452 6.0000000000
+-5.4772491271e+01 -> -1.7116403522 5.0000000000
+-4.0630355647e+01 -> -1.2696986140 5.0000000000
+-2.6488220023e+01 -> -1.6555137515 4.0000000000
+-1.2346084400e+01 -> -1.5432605499 3.0000000000
+ 1.7960512242e+00 -> 1.7960512242 0.0000000000
+ 1.5938186848e+01 -> 1.9922733560 3.0000000000
+ 3.0080322472e+01 -> 1.8800201545 4.0000000000
+ 4.4222458095e+01 -> 1.3819518155 5.0000000000
+ 5.8364593719e+01 -> 1.8238935537 5.0000000000
+ 7.2506729343e+01 -> 1.1329176460 6.0000000000
+ 8.6648864967e+01 -> 1.3538885151 6.0000000000
+ 1.0079100059e+02 -> 1.5748593842 6.0000000000
+ 1.1493313621e+02 -> 1.7958302533 6.0000000000
+ 1.2907527184e+02 -> 1.0084005612 7.0000000000
+ 1.4321740746e+02 -> 1.1188859958 7.0000000000
+ 1.5735954309e+02 -> 1.2293714304 7.0000000000
+ 1.7150167871e+02 -> 1.3398568649 7.0000000000
+ 1.8564381433e+02 -> 1.4503422995 7.0000000000
+ 1.9978594996e+02 -> 1.5608277340 7.0000000000
+ 2.1392808558e+02 -> 1.6713131686 7.0000000000
+ 2.2807022120e+02 -> 1.7817986032 7.0000000000
+ 2.4221235683e+02 -> 1.8922840377 7.0000000000
+ 2.5635449245e+02 -> 1.0013847361 8.0000000000
+ 2.7049662808e+02 -> 1.0566274534 8.0000000000
+ 0.0000000000e+00 -> 0.0000000000 -inf
+ inf -> inf inf
+ nan -> nan nan
+7.2124891681e-308 -> 1.6207302828 -1021.0000000000
+5.7982756057e-308 -> 1.3029400313 -1021.0000000000
+4.3840620434e-308 -> 1.9702995595 -1022.0000000000
+2.9698484810e-308 -> 1.3347190565 -1022.0000000000
+1.5556349186e-308 -> 1.3982771068 -1023.0000000000
+1.2727922061e-308 -> 1.1440449055 -1023.0000000000
+9.8994949366e-309 -> 1.7796254086 -1024.0000000000
+8.4852813742e-309 -> 1.5253932074 -1024.0000000000
+7.0710678119e-309 -> 1.2711610062 -1024.0000000000
+5.6568542495e-309 -> 1.0169288049 -1024.0000000000
+4.2426406871e-309 -> 1.5253932074 -1025.0000000000
+1.4142135624e-309 -> 1.0169288049 -1026.0000000000
+1.8384182682e-320 -> 1.8168945312 -1063.0000000000
+1.8379242025e-321 -> 1.4531250000 -1066.0000000000
+1.8280428896e-322 -> 1.1562500000 -1069.0000000000
+1.9762625834e-323 -> 1.0000000000 -1072.0000000000
+1.4821969375e-323 -> 1.5000000000 -1073.0000000000
+4.9406564584e-324 -> 1.0000000000 -1074.0000000000
+4.9406564584e-324 -> 1.0000000000 -1074.0000000000
+4.9406564584e-324 -> 1.0000000000 -1074.0000000000
+ 0.0000000000e+00 -> 0.0000000000 -inf
+ 0.0000000000e+00 -> 0.0000000000 -inf
+
+ 2.8104666125e+02 -> 1.0978385205 8.0000000000
+ 2.6690452563e+02 -> 1.0425958032 8.0000000000
+ 2.5276239000e+02 -> 1.9747061719 7.0000000000
+ 2.3862025438e+02 -> 1.8642207373 7.0000000000
+ 2.2447811876e+02 -> 1.7537353028 7.0000000000
+ 2.1033598313e+02 -> 1.6432498682 7.0000000000
+ 1.9619384751e+02 -> 1.5327644337 7.0000000000
+ 1.8205171188e+02 -> 1.4222789991 7.0000000000
+ 1.6790957626e+02 -> 1.3117935645 7.0000000000
+ 1.5376744064e+02 -> 1.2013081300 7.0000000000
+ 1.3962530501e+02 -> 1.0908226954 7.0000000000
+ 1.2548316939e+02 -> 1.9606745217 6.0000000000
+ 1.1134103377e+02 -> 1.7397036526 6.0000000000
+ 9.7198898142e+01 -> 1.5187327835 6.0000000000
+ 8.3056762518e+01 -> 1.2977619143 6.0000000000
+ 6.8914626894e+01 -> 1.0767910452 6.0000000000
+ 5.4772491271e+01 -> 1.7116403522 5.0000000000
+ 4.0630355647e+01 -> 1.2696986140 5.0000000000
+ 2.6488220023e+01 -> 1.6555137515 4.0000000000
+ 1.2346084400e+01 -> 1.5432605499 3.0000000000
+-1.7960512242e+00 -> -1.7960512242 0.0000000000
+-1.5938186848e+01 -> -1.9922733560 3.0000000000
+-3.0080322472e+01 -> -1.8800201545 4.0000000000
+-4.4222458095e+01 -> -1.3819518155 5.0000000000
+-5.8364593719e+01 -> -1.8238935537 5.0000000000
+-7.2506729343e+01 -> -1.1329176460 6.0000000000
+-8.6648864967e+01 -> -1.3538885151 6.0000000000
+-1.0079100059e+02 -> -1.5748593842 6.0000000000
+-1.1493313621e+02 -> -1.7958302533 6.0000000000
+-1.2907527184e+02 -> -1.0084005612 7.0000000000
+-1.4321740746e+02 -> -1.1188859958 7.0000000000
+-1.5735954309e+02 -> -1.2293714304 7.0000000000
+-1.7150167871e+02 -> -1.3398568649 7.0000000000
+-1.8564381433e+02 -> -1.4503422995 7.0000000000
+-1.9978594996e+02 -> -1.5608277340 7.0000000000
+-2.1392808558e+02 -> -1.6713131686 7.0000000000
+-2.2807022120e+02 -> -1.7817986032 7.0000000000
+-2.4221235683e+02 -> -1.8922840377 7.0000000000
+-2.5635449245e+02 -> -1.0013847361 8.0000000000
+-2.7049662808e+02 -> -1.0566274534 8.0000000000
+-0.0000000000e+00 -> -0.0000000000 -inf
+ -inf -> -inf inf
+ nan -> nan nan
+-7.2124891681e-308 -> -1.6207302828 -1021.0000000000
+-5.7982756057e-308 -> -1.3029400313 -1021.0000000000
+-4.3840620434e-308 -> -1.9702995595 -1022.0000000000
+-2.9698484810e-308 -> -1.3347190565 -1022.0000000000
+-1.5556349186e-308 -> -1.3982771068 -1023.0000000000
+-1.2727922061e-308 -> -1.1440449055 -1023.0000000000
+-9.8994949366e-309 -> -1.7796254086 -1024.0000000000
+-8.4852813742e-309 -> -1.5253932074 -1024.0000000000
+-7.0710678119e-309 -> -1.2711610062 -1024.0000000000
+-5.6568542495e-309 -> -1.0169288049 -1024.0000000000
+-4.2426406871e-309 -> -1.5253932074 -1025.0000000000
+-1.4142135624e-309 -> -1.0169288049 -1026.0000000000
+-1.8384182682e-320 -> -1.8168945312 -1063.0000000000
+-1.8379242025e-321 -> -1.4531250000 -1066.0000000000
+-1.8280428896e-322 -> -1.1562500000 -1069.0000000000
+-1.9762625834e-323 -> -1.0000000000 -1072.0000000000
+-1.4821969375e-323 -> -1.5000000000 -1073.0000000000
+-4.9406564584e-324 -> -1.0000000000 -1074.0000000000
+-4.9406564584e-324 -> -1.0000000000 -1074.0000000000
+-4.9406564584e-324 -> -1.0000000000 -1074.0000000000
+-0.0000000000e+00 -> -0.0000000000 -inf
+-0.0000000000e+00 -> -0.0000000000 -inf
diff --git a/main/none/tests/x86/insn_ssse3.vgtest b/main/none/tests/x86/insn_ssse3.vgtest
index 73ce799..1ef3641 100644
--- a/main/none/tests/x86/insn_ssse3.vgtest
+++ b/main/none/tests/x86/insn_ssse3.vgtest
@@ -1,3 +1,3 @@
prog: ../../../none/tests/x86/insn_ssse3
-prereq: ../../../tests/x86_amd64_features x86-ssse3
+prereq: test -x insn_ssse3 && ../../../tests/x86_amd64_features x86-ssse3
vgopts: -q
diff --git a/main/none/tests/x86/lzcnt32.c b/main/none/tests/x86/lzcnt32.c
index a11dbfd..107a25d 100644
--- a/main/none/tests/x86/lzcnt32.c
+++ b/main/none/tests/x86/lzcnt32.c
@@ -64,69 +64,3 @@
return 0;
}
-
-#include <stdio.h>
-
-typedef unsigned long long int ULong;
-typedef unsigned int UInt;
-
-__attribute__((noinline))
-void do_lzcnt32 ( /*OUT*/UInt* flags, /*OUT*/UInt* res, UInt arg )
-{
- UInt block[3] = { arg, 0, 0 };
- __asm__ __volatile__(
- "movl $0x55555555, %%esi" "\n\t"
- "lzcntl 0(%0), %%esi" "\n\t"
- "movl %%esi, 4(%0)" "\n\t"
- "pushfl" "\n\t"
- "popl %%esi" "\n\t"
- "movl %%esi, 8(%0)" "\n"
- : : "r"(&block[0]) : "esi","cc","memory"
- );
- *res = block[1];
- *flags = block[2] & 0x8d5;
-}
-
-__attribute__((noinline))
-void do_lzcnt16 ( /*OUT*/UInt* flags, /*OUT*/UInt* res, UInt arg )
-{
- UInt block[3] = { arg, 0, 0 };
- __asm__ __volatile__(
- "movl $0x55555555, %%esi" "\n\t"
- "lzcntw 0(%0), %%si" "\n\t"
- "movl %%esi, 4(%0)" "\n\t"
- "pushfl" "\n\t"
- "popl %%esi" "\n\t"
- "movl %%esi, 8(%0)" "\n"
- : : "r"(&block[0]) : "esi","cc","memory"
- );
- *res = block[1];
- *flags = block[2] & 0x8d5;
-}
-
-int main ( void )
-{
- UInt w;
-
- w = 0xFEDC1928;
- while (1) {
- UInt res;
- UInt flags;
- do_lzcnt32(&flags, &res, w);
- printf("lzcntl %08x -> %08x %04x\n", w, res, flags);
- if (w == 0) break;
- w = ((w >> 2) | (w >> 1)) + (w / 17);
- }
-
- w = 0xFEDC1928;
- while (1) {
- UInt res;
- UInt flags;
- do_lzcnt16(&flags, &res, w);
- printf("lzcntw %08x -> %08x %04x\n", w, res, flags);
- if (w == 0) break;
- w = ((w >> 2) | (w >> 1)) + (w / 17);
- }
-
- return 0;
-}
diff --git a/main/none/tests/arm/v6int.stderr.exp b/main/none/tests/x86/lzcnt32.stderr.exp
similarity index 100%
copy from main/none/tests/arm/v6int.stderr.exp
copy to main/none/tests/x86/lzcnt32.stderr.exp
diff --git a/main/none/tests/x86/lzcnt32.stdout.exp b/main/none/tests/x86/lzcnt32.stdout.exp
index 388dc93..41773d3 100644
--- a/main/none/tests/x86/lzcnt32.stdout.exp
+++ b/main/none/tests/x86/lzcnt32.stdout.exp
@@ -120,125 +120,3 @@
lzcntw 00000003 -> 5555000e 0000
lzcntw 00000001 -> 5555000f 0000
lzcntw 00000000 -> 55550010 0001
-lzcntl fedc1928 -> 00000000 0040
-lzcntl 8efcf23a -> 00000000 0040
-lzcntl 7068b90b -> 00000001 0000
-lzcntl 42db3e5e -> 00000001 0000
-lzcntl 35eea72d -> 00000002 0000
-lzcntl 232c23d2 -> 00000002 0000
-lzcntl 1bf0c1be -> 00000003 0000
-lzcntl 11a13119 -> 00000003 0000
-lzcntl 0e025829 -> 00000004 0000
-lzcntl 0854b43e -> 00000004 0000
-lzcntl 06bcf322 -> 00000005 0000
-lzcntl 0464f58f -> 00000005 0000
-lzcntl 037dac76 -> 00000006 0000
-lzcntl 023490eb -> 00000006 0000
-lzcntl 01c0a232 -> 00000007 0000
-lzcntl 010add81 -> 00000007 0000
-lzcntl 00d7b28d -> 00000008 0000
-lzcntl 008cae0d -> 00000008 0000
-lzcntl 006fc600 -> 00000009 0000
-lzcntl 004686ad -> 00000009 0000
-lzcntl 00380a09 -> 0000000a 0000
-lzcntl 00215368 -> 0000000a 0000
-lzcntl 001af3d6 -> 0000000b 0000
-lzcntl 001193de -> 0000000b 0000
-lzcntl 000df6b1 -> 0000000c 0000
-lzcntl 0008d242 -> 0000000c 0000
-lzcntl 00070287 -> 0000000d 0000
-lzcntl 00042b72 -> 0000000d 0000
-lzcntl 00035ec7 -> 0000000e 0000
-lzcntl 000232b3 -> 0000000e 0000
-lzcntl 0001bf16 -> 0000000f 0000
-lzcntl 00011a1b -> 0000000f 0000
-lzcntl 0000e027 -> 00000010 0000
-lzcntl 0000854a -> 00000010 0000
-lzcntl 00006bce -> 00000011 0000
-lzcntl 0000464e -> 00000011 0000
-lzcntl 000037d9 -> 00000012 0000
-lzcntl 00002347 -> 00000012 0000
-lzcntl 00001c06 -> 00000013 0000
-lzcntl 000010a9 -> 00000013 0000
-lzcntl 00000d78 -> 00000014 0000
-lzcntl 000008c8 -> 00000014 0000
-lzcntl 000006fa -> 00000015 0000
-lzcntl 00000468 -> 00000015 0000
-lzcntl 00000380 -> 00000016 0000
-lzcntl 00000214 -> 00000016 0000
-lzcntl 000001ae -> 00000017 0000
-lzcntl 00000118 -> 00000017 0000
-lzcntl 000000de -> 00000018 0000
-lzcntl 0000008c -> 00000018 0000
-lzcntl 0000006f -> 00000019 0000
-lzcntl 00000045 -> 00000019 0000
-lzcntl 00000037 -> 0000001a 0000
-lzcntl 00000022 -> 0000001a 0000
-lzcntl 0000001b -> 0000001b 0000
-lzcntl 00000010 -> 0000001b 0000
-lzcntl 0000000c -> 0000001c 0000
-lzcntl 00000007 -> 0000001d 0000
-lzcntl 00000003 -> 0000001e 0000
-lzcntl 00000001 -> 0000001f 0000
-lzcntl 00000000 -> 00000020 0001
-lzcntw fedc1928 -> 55550003 0000
-lzcntw 8efcf23a -> 55550000 0040
-lzcntw 7068b90b -> 55550000 0040
-lzcntw 42db3e5e -> 55550002 0000
-lzcntw 35eea72d -> 55550000 0040
-lzcntw 232c23d2 -> 55550002 0000
-lzcntw 1bf0c1be -> 55550000 0040
-lzcntw 11a13119 -> 55550002 0000
-lzcntw 0e025829 -> 55550001 0000
-lzcntw 0854b43e -> 55550000 0040
-lzcntw 06bcf322 -> 55550000 0040
-lzcntw 0464f58f -> 55550000 0040
-lzcntw 037dac76 -> 55550000 0040
-lzcntw 023490eb -> 55550000 0040
-lzcntw 01c0a232 -> 55550000 0040
-lzcntw 010add81 -> 55550000 0040
-lzcntw 00d7b28d -> 55550000 0040
-lzcntw 008cae0d -> 55550000 0040
-lzcntw 006fc600 -> 55550000 0040
-lzcntw 004686ad -> 55550000 0040
-lzcntw 00380a09 -> 55550004 0000
-lzcntw 00215368 -> 55550001 0000
-lzcntw 001af3d6 -> 55550000 0040
-lzcntw 001193de -> 55550000 0040
-lzcntw 000df6b1 -> 55550000 0040
-lzcntw 0008d242 -> 55550000 0040
-lzcntw 00070287 -> 55550006 0000
-lzcntw 00042b72 -> 55550002 0000
-lzcntw 00035ec7 -> 55550001 0000
-lzcntw 000232b3 -> 55550002 0000
-lzcntw 0001bf16 -> 55550000 0040
-lzcntw 00011a1b -> 55550003 0000
-lzcntw 0000e027 -> 55550000 0040
-lzcntw 0000854a -> 55550000 0040
-lzcntw 00006bce -> 55550001 0000
-lzcntw 0000464e -> 55550001 0000
-lzcntw 000037d9 -> 55550002 0000
-lzcntw 00002347 -> 55550002 0000
-lzcntw 00001c06 -> 55550003 0000
-lzcntw 000010a9 -> 55550003 0000
-lzcntw 00000d78 -> 55550004 0000
-lzcntw 000008c8 -> 55550004 0000
-lzcntw 000006fa -> 55550005 0000
-lzcntw 00000468 -> 55550005 0000
-lzcntw 00000380 -> 55550006 0000
-lzcntw 00000214 -> 55550006 0000
-lzcntw 000001ae -> 55550007 0000
-lzcntw 00000118 -> 55550007 0000
-lzcntw 000000de -> 55550008 0000
-lzcntw 0000008c -> 55550008 0000
-lzcntw 0000006f -> 55550009 0000
-lzcntw 00000045 -> 55550009 0000
-lzcntw 00000037 -> 5555000a 0000
-lzcntw 00000022 -> 5555000a 0000
-lzcntw 0000001b -> 5555000b 0000
-lzcntw 00000010 -> 5555000b 0000
-lzcntw 0000000c -> 5555000c 0000
-lzcntw 00000007 -> 5555000d 0000
-lzcntw 00000003 -> 5555000e 0000
-lzcntw 00000001 -> 5555000f 0000
-lzcntw 00000000 -> 55550010 0001
diff --git a/main/none/tests/x86/lzcnt32.vgtest b/main/none/tests/x86/lzcnt32.vgtest
index aba6c02..d1e95be 100644
--- a/main/none/tests/x86/lzcnt32.vgtest
+++ b/main/none/tests/x86/lzcnt32.vgtest
@@ -1,6 +1,3 @@
prog: lzcnt32
prereq: ../../../tests/x86_amd64_features x86-lzcnt
vgopts: -q
-prog: lzcnt32
-prereq: ../../../tests/x86_amd64_features x86-lzcnt
-vgopts: -q
diff --git a/main/none/tests/x86/ssse3_misaligned.vgtest b/main/none/tests/x86/ssse3_misaligned.vgtest
index 45db4f0..17d1137 100644
--- a/main/none/tests/x86/ssse3_misaligned.vgtest
+++ b/main/none/tests/x86/ssse3_misaligned.vgtest
@@ -1,3 +1,3 @@
prog: ssse3_misaligned
-prereq: ../../../tests/x86_amd64_features x86-ssse3
+prereq: test -x ssse3_misaligned && ../../../tests/x86_amd64_features x86-ssse3
vgopts: -q